diff --git a/rel/build/a2x/a2x_impl_step.tcl b/rel/build/a2x/a2x_impl_step.tcl new file mode 100644 index 0000000..fd0fcb3 --- /dev/null +++ b/rel/build/a2x/a2x_impl_step.tcl @@ -0,0 +1,20 @@ +#synth_design -top a2x_axi_bd_wrapper -part xcvu3p-ffvc1517-2-e -verbose +#source ila_axi.tcl +set version v0 + +write_checkpoint -force a2x_axi_synth_${version}.dcp + +opt_design -retarget -propconst -bram_power_opt +place_design -directive Explore +phys_opt_design -directive Explore +route_design -directive Explore +phys_opt_design -directive Explore +write_checkpoint -force a2x_axi_routed_${version}.dcp + +report_utilization -file utilization_route_design_${version}.rpt +report_timing_summary -max_paths 100 -file timing_routed_summary_${version}.rpt + +write_bitstream -force -bin_file a2x_axi_${version} +write_debug_probes -force a2x_axi_${version} +write_cfgmem -force -format BIN -interface SPIx8 -size 256 -loadbit "up 0 a2x_axi_${version}.bit" a2x_axi_${version} + diff --git a/rel/build/a2x/bd/hdl/a2x_axi_bd_wrapper.v b/rel/build/a2x/bd/hdl/a2x_axi_bd_wrapper.v new file mode 100644 index 0000000..37c4608 --- /dev/null +++ b/rel/build/a2x/bd/hdl/a2x_axi_bd_wrapper.v @@ -0,0 +1,24 @@ +//Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +//-------------------------------------------------------------------------------- +//Tool Version: Vivado v.2019.1.3_CR1055600 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +//Date : Wed Apr 8 10:49:50 2020 +//Host : apdegl15aa.pok.ibm.com running 64-bit Red Hat Enterprise Linux Workstation release 7.5 (Maipo) +//Command : generate_target a2x_axi_bd_wrapper.bd +//Design : a2x_axi_bd_wrapper +//Purpose : IP block netlist +//-------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module a2x_axi_bd_wrapper + (clk_in1_n_0, + clk_in1_p_0); + input clk_in1_n_0; + input clk_in1_p_0; + + wire clk_in1_n_0; + wire clk_in1_p_0; + + a2x_axi_bd a2x_axi_bd_i + (.clk_in1_n_0(clk_in1_n_0), + .clk_in1_p_0(clk_in1_p_0)); +endmodule diff --git a/rel/build/a2x/create_a2x_project.tcl b/rel/build/a2x/create_a2x_project.tcl new file mode 100644 index 0000000..55d11de --- /dev/null +++ b/rel/build/a2x/create_a2x_project.tcl @@ -0,0 +1,1975 @@ +# Set the reference directory for source file relative paths (by default the value is script directory path) +set origin_dir "./" + +# Use origin directory path location variable, if specified in the tcl shell +if { [info exists ::origin_dir_loc] } { + set origin_dir $::origin_dir_loc +} + +# Set the project name +set _xil_proj_name_ "proj_a2x_axi" + +# Use project name variable, if specified in the tcl shell +if { [info exists ::user_project_name] } { + set _xil_proj_name_ $::user_project_name +} + +variable script_file +set script_file "create_a2x_project.tcl" + +# Help information for this script +proc print_help {} { + variable script_file + puts "\nDescription:" + puts "Recreate a Vivado project from this script. The created project will be" + puts "functionally equivalent to the original project for which this script was" + puts "generated. The script contains commands for creating a project, filesets," + puts "runs, adding/importing sources and setting properties on various objects.\n" + puts "Syntax:" + puts "$script_file" + puts "$script_file -tclargs \[--origin_dir \]" + puts "$script_file -tclargs \[--project_name \]" + puts "$script_file -tclargs \[--help\]\n" + puts "Usage:" + puts "Name Description" + puts "-------------------------------------------------------------------------" + puts "\[--origin_dir \] Determine source file paths wrt this path. Default" + puts " origin_dir path value is \".\", otherwise, the value" + puts " that was set with the \"-paths_relative_to\" switch" + puts " when this script was generated.\n" + puts "\[--project_name \] Create project with the specified name. Default" + puts " name is the name of the project from where this" + puts " script was generated.\n" + puts "\[--help\] Print help information for this script" + puts "-------------------------------------------------------------------------\n" + exit 0 +} + +if { $::argc > 0 } { + for {set i 0} {$i < $::argc} {incr i} { + set option [string trim [lindex $::argv $i]] + switch -regexp -- $option { + "--origin_dir" { incr i; set origin_dir [lindex $::argv $i] } + "--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] } + "--help" { print_help } + default { + if { [regexp {^-} $option] } { + puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n" + return 1 + } + } + } + } +} + +# Set the directory path for the original project from where this script was exported +set orig_proj_dir "[file normalize "$origin_dir/"]" + +# Create project +create_project ${_xil_proj_name_} -force "./proj" -part xcvu3p-ffvc1517-2-e + +# Set the directory path for the new project +set proj_dir [get_property directory [current_project]] + +# Set project properties +set obj [current_project] +set_property -name "board_part" -value "" -objects $obj +set_property -name "compxlib.activehdl_compiled_library_dir" -value "$proj_dir/${_xil_proj_name_}.cache/compile_simlib/activehdl" -objects $obj +set_property -name "compxlib.funcsim" -value "1" -objects $obj +set_property -name "compxlib.ies_compiled_library_dir" -value "$proj_dir/${_xil_proj_name_}.cache/compile_simlib/ies" -objects $obj +set_property -name "compxlib.modelsim_compiled_library_dir" -value "$proj_dir/${_xil_proj_name_}.cache/compile_simlib/modelsim" -objects $obj +set_property -name "compxlib.overwrite_libs" -value "0" -objects $obj +set_property -name "compxlib.questa_compiled_library_dir" -value "$proj_dir/${_xil_proj_name_}.cache/compile_simlib/questa" -objects $obj +set_property -name "compxlib.riviera_compiled_library_dir" -value "$proj_dir/${_xil_proj_name_}.cache/compile_simlib/riviera" -objects $obj +set_property -name "compxlib.timesim" -value "1" -objects $obj +set_property -name "compxlib.vcs_compiled_library_dir" -value "$proj_dir/${_xil_proj_name_}.cache/compile_simlib/vcs" -objects $obj +set_property -name "compxlib.xsim_compiled_library_dir" -value "" -objects $obj +set_property -name "corecontainer.enable" -value "0" -objects $obj +set_property -name "default_lib" -value "xil_defaultlib" -objects $obj +set_property -name "dsa.accelerator_binary_content" -value "bitstream" -objects $obj +set_property -name "dsa.accelerator_binary_format" -value "xclbin2" -objects $obj +set_property -name "dsa.description" -value "Vivado generated DSA" -objects $obj +set_property -name "dsa.dr_bd_base_address" -value "0" -objects $obj +set_property -name "dsa.emu_dir" -value "emu" -objects $obj +set_property -name "dsa.flash_interface_type" -value "bpix16" -objects $obj +set_property -name "dsa.flash_offset_address" -value "0" -objects $obj +set_property -name "dsa.flash_size" -value "1024" -objects $obj +set_property -name "dsa.host_architecture" -value "x86_64" -objects $obj +set_property -name "dsa.host_interface" -value "pcie" -objects $obj +set_property -name "dsa.num_compute_units" -value "60" -objects $obj +set_property -name "dsa.platform_state" -value "pre_synth" -objects $obj +set_property -name "dsa.rom.debug_type" -value "0" -objects $obj +set_property -name "dsa.rom.prom_type" -value "0" -objects $obj +set_property -name "dsa.vendor" -value "xilinx" -objects $obj +set_property -name "dsa.version" -value "0.0" -objects $obj +set_property -name "enable_optional_runs_sta" -value "0" -objects $obj +set_property -name "enable_vhdl_2008" -value "1" -objects $obj +set_property -name "generate_ip_upgrade_log" -value "1" -objects $obj +set_property -name "ip_cache_permissions" -value "read write" -objects $obj +set_property -name "ip_interface_inference_priority" -value "" -objects $obj +set_property -name "ip_output_repo" -value [file normalize "../ip_cache"] -objects $obj +set_property -name "legacy_ip_repo_paths" -value "" -objects $obj +set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj +set_property -name "part" -value "xcvu3p-ffvc1517-2-e" -objects $obj +set_property -name "project_type" -value "Default" -objects $obj +set_property -name "pr_flow" -value "0" -objects $obj +set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj +set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj +set_property -name "sim.use_ip_compiled_libs" -value "1" -objects $obj +set_property -name "simulator_language" -value "Mixed" -objects $obj +set_property -name "source_mgmt_mode" -value "All" -objects $obj +set_property -name "target_language" -value "VHDL" -objects $obj +set_property -name "target_simulator" -value "XSim" -objects $obj +set_property -name "tool_flow" -value "Vivado" -objects $obj +set_property -name "webtalk.activehdl_export_sim" -value "55" -objects $obj +set_property -name "webtalk.ies_export_sim" -value "55" -objects $obj +set_property -name "webtalk.modelsim_export_sim" -value "55" -objects $obj +set_property -name "webtalk.questa_export_sim" -value "55" -objects $obj +set_property -name "webtalk.riviera_export_sim" -value "55" -objects $obj +set_property -name "webtalk.vcs_export_sim" -value "55" -objects $obj +set_property -name "webtalk.xsim_export_sim" -value "55" -objects $obj +set_property -name "webtalk.xsim_launch_sim" -value "27" -objects $obj +set_property -name "xpm_libraries" -value "XPM_CDC XPM_FIFO XPM_MEMORY" -objects $obj +set_property -name "xsim.array_display_limit" -value "1024" -objects $obj +set_property -name "xsim.radix" -value "hex" -objects $obj +set_property -name "xsim.time_unit" -value "ns" -objects $obj +set_property -name "xsim.trace_limit" -value "65536" -objects $obj + +# Create 'sources_1' fileset (if not found) +if {[string equal [get_filesets -quiet sources_1] ""]} { + create_fileset -srcset sources_1 +} + +# Set IP repository paths +set obj [get_filesets sources_1] +set_property "ip_repo_paths" [file normalize "../ip_repo"] $obj + +# Rebuild user ip_repo's index before adding any source files +update_ip_catalog -rebuild + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +# Import local files from the original project +set files [list \ + [file normalize "${origin_dir}/bd/hdl/a2x_axi_bd_wrapper.v" ]\ +] +set imported_files [import_files -fileset sources_1 $files] + +# Set 'sources_1' fileset file properties for remote files +# None + +# Set 'sources_1' fileset file properties for local files +set file "hdl/a2x_axi_bd_wrapper.v" +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "file_type" -value "Verilog" -objects $file_obj +set_property -name "is_enabled" -value "1" -objects $file_obj +set_property -name "is_global_include" -value "0" -objects $file_obj +set_property -name "library" -value "xil_defaultlib" -objects $file_obj +set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj +set_property -name "used_in" -value "synthesis implementation simulation" -objects $file_obj +set_property -name "used_in_implementation" -value "1" -objects $file_obj +set_property -name "used_in_simulation" -value "1" -objects $file_obj +set_property -name "used_in_synthesis" -value "1" -objects $file_obj + + +# Set 'sources_1' fileset properties +set obj [get_filesets sources_1] +set_property -name "design_mode" -value "RTL" -objects $obj +set_property -name "edif_extra_search_paths" -value "" -objects $obj +set_property -name "elab_link_dcps" -value "1" -objects $obj +set_property -name "elab_load_timing_constraints" -value "1" -objects $obj +set_property -name "generic" -value "" -objects $obj +set_property -name "include_dirs" -value "" -objects $obj +set_property -name "lib_map_file" -value "" -objects $obj +set_property -name "loop_count" -value "1000" -objects $obj +set_property -name "name" -value "sources_1" -objects $obj +set_property -name "top" -value "a2x_axi_bd_wrapper" -objects $obj +set_property -name "verilog_define" -value "" -objects $obj +set_property -name "verilog_uppercase" -value "0" -objects $obj +set_property -name "verilog_version" -value "verilog_2001" -objects $obj +set_property -name "vhdl_version" -value "vhdl_2k" -objects $obj + +# Create 'constrs_1' fileset (if not found) +if {[string equal [get_filesets -quiet constrs_1] ""]} { + create_fileset -constrset constrs_1 +} + +# Set 'constrs_1' fileset object +set obj [get_filesets constrs_1] + +# Add/Import constrs file and set constrs file properties +set file "[file normalize ${origin_dir}/xdc/main_pinout.xdc]" +set file_added [add_files -norecurse -fileset $obj [list $file]] +set file "$origin_dir/xdc/main_pinout.xdc" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]] +set_property -name "file_type" -value "XDC" -objects $file_obj +set_property -name "is_enabled" -value "1" -objects $file_obj +set_property -name "is_global_include" -value "0" -objects $file_obj +set_property -name "library" -value "xil_defaultlib" -objects $file_obj +set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj +set_property -name "processing_order" -value "NORMAL" -objects $file_obj +set_property -name "scoped_to_cells" -value "" -objects $file_obj +set_property -name "scoped_to_ref" -value "" -objects $file_obj +set_property -name "used_in" -value "synthesis implementation" -objects $file_obj +set_property -name "used_in_implementation" -value "1" -objects $file_obj +set_property -name "used_in_synthesis" -value "1" -objects $file_obj + +# Add/Import constrs file and set constrs file properties +set file "[file normalize ${origin_dir}/xdc/main_spi.xdc]" +set file_added [add_files -norecurse -fileset $obj [list $file]] +set file "$origin_dir/xdc/main_spi.xdc" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]] +set_property -name "file_type" -value "XDC" -objects $file_obj +set_property -name "is_enabled" -value "1" -objects $file_obj +set_property -name "is_global_include" -value "0" -objects $file_obj +set_property -name "library" -value "xil_defaultlib" -objects $file_obj +set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj +set_property -name "processing_order" -value "NORMAL" -objects $file_obj +set_property -name "scoped_to_cells" -value "" -objects $file_obj +set_property -name "scoped_to_ref" -value "" -objects $file_obj +set_property -name "used_in" -value "synthesis implementation" -objects $file_obj +set_property -name "used_in_implementation" -value "1" -objects $file_obj +set_property -name "used_in_synthesis" -value "1" -objects $file_obj + +# Add/Import constrs file and set constrs file properties +set file "[file normalize ${origin_dir}/xdc/main_timing.xdc]" +set file_added [add_files -norecurse -fileset $obj [list $file]] +set file "$origin_dir/xdc/main_timing.xdc" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]] +set_property -name "file_type" -value "XDC" -objects $file_obj +set_property -name "is_enabled" -value "1" -objects $file_obj +set_property -name "is_global_include" -value "0" -objects $file_obj +set_property -name "library" -value "xil_defaultlib" -objects $file_obj +set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj +set_property -name "processing_order" -value "NORMAL" -objects $file_obj +set_property -name "scoped_to_cells" -value "" -objects $file_obj +set_property -name "scoped_to_ref" -value "" -objects $file_obj +set_property -name "used_in" -value "synthesis implementation" -objects $file_obj +set_property -name "used_in_implementation" -value "1" -objects $file_obj +set_property -name "used_in_synthesis" -value "1" -objects $file_obj + +# Add/Import constrs file and set constrs file properties +set file "[file normalize "$origin_dir/xdc/main_extras.xdc"]" +set file_added [add_files -norecurse -fileset $obj [list $file]] +set file "$origin_dir/xdc/main_extras.xdc" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]] +set_property -name "file_type" -value "XDC" -objects $file_obj +set_property -name "is_enabled" -value "1" -objects $file_obj +set_property -name "is_global_include" -value "0" -objects $file_obj +set_property -name "library" -value "xil_defaultlib" -objects $file_obj +set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj +set_property -name "processing_order" -value "NORMAL" -objects $file_obj +set_property -name "scoped_to_cells" -value "" -objects $file_obj +set_property -name "scoped_to_ref" -value "" -objects $file_obj +set_property -name "used_in" -value "synthesis implementation" -objects $file_obj +set_property -name "used_in_implementation" -value "1" -objects $file_obj +set_property -name "used_in_synthesis" -value "1" -objects $file_obj + +# Set 'constrs_1' fileset properties +set obj [get_filesets constrs_1] +set_property -name "constrs_type" -value "XDC" -objects $obj +set_property -name "name" -value "constrs_1" -objects $obj +set_property -name "target_constrs_file" -value [file normalize "xdc/main_extras.xdc"] -objects $obj +set_property -name "target_part" -value "xcvu3p-ffvc1517-2-e" -objects $obj +set_property -name "target_ucf" -value [file normalize "xdc/main_extras.xdc"] -objects $obj + +# Create 'sim_1' fileset (if not found) +if {[string equal [get_filesets -quiet sim_1] ""]} { + create_fileset -simset sim_1 +} + +# Set 'sim_1' fileset object +set obj [get_filesets sim_1] +# Empty (no sources present) + +# Set 'sim_1' fileset properties +set obj [get_filesets sim_1] +set_property -name "32bit" -value "0" -objects $obj +set_property -name "generic" -value "" -objects $obj +set_property -name "include_dirs" -value "" -objects $obj +set_property -name "incremental" -value "1" -objects $obj +set_property -name "name" -value "sim_1" -objects $obj +set_property -name "nl.cell" -value "" -objects $obj +set_property -name "nl.incl_unisim_models" -value "0" -objects $obj +set_property -name "nl.mode" -value "funcsim" -objects $obj +set_property -name "nl.process_corner" -value "slow" -objects $obj +set_property -name "nl.rename_top" -value "" -objects $obj +set_property -name "nl.sdf_anno" -value "1" -objects $obj +set_property -name "nl.write_all_overrides" -value "0" -objects $obj +set_property -name "source_set" -value "sources_1" -objects $obj +set_property -name "systemc_include_dirs" -value "" -objects $obj +set_property -name "top" -value "a2x_axi_bd_wrapper" -objects $obj +set_property -name "top_lib" -value "xil_defaultlib" -objects $obj +set_property -name "transport_int_delay" -value "0" -objects $obj +set_property -name "transport_path_delay" -value "0" -objects $obj +set_property -name "verilog_define" -value "" -objects $obj +set_property -name "verilog_uppercase" -value "0" -objects $obj +set_property -name "xelab.dll" -value "0" -objects $obj +set_property -name "xsim.compile.tcl.pre" -value "" -objects $obj +set_property -name "xsim.compile.xsc.more_options" -value "" -objects $obj +set_property -name "xsim.compile.xvhdl.more_options" -value "" -objects $obj +set_property -name "xsim.compile.xvhdl.nosort" -value "1" -objects $obj +set_property -name "xsim.compile.xvhdl.relax" -value "1" -objects $obj +set_property -name "xsim.compile.xvlog.more_options" -value "" -objects $obj +set_property -name "xsim.compile.xvlog.nosort" -value "1" -objects $obj +set_property -name "xsim.compile.xvlog.relax" -value "1" -objects $obj +set_property -name "xsim.elaborate.debug_level" -value "typical" -objects $obj +set_property -name "xsim.elaborate.load_glbl" -value "1" -objects $obj +set_property -name "xsim.elaborate.mt_level" -value "auto" -objects $obj +set_property -name "xsim.elaborate.rangecheck" -value "0" -objects $obj +set_property -name "xsim.elaborate.relax" -value "1" -objects $obj +set_property -name "xsim.elaborate.sdf_delay" -value "sdfmax" -objects $obj +set_property -name "xsim.elaborate.snapshot" -value "" -objects $obj +set_property -name "xsim.elaborate.xelab.more_options" -value "" -objects $obj +set_property -name "xsim.elaborate.xsc.more_options" -value "" -objects $obj +set_property -name "xsim.simulate.add_positional" -value "0" -objects $obj +set_property -name "xsim.simulate.custom_tcl" -value "" -objects $obj +set_property -name "xsim.simulate.log_all_signals" -value "0" -objects $obj +set_property -name "xsim.simulate.no_quit" -value "0" -objects $obj +set_property -name "xsim.simulate.runtime" -value "1000ns" -objects $obj +set_property -name "xsim.simulate.saif" -value "" -objects $obj +set_property -name "xsim.simulate.saif_all_signals" -value "0" -objects $obj +set_property -name "xsim.simulate.saif_scope" -value "" -objects $obj +set_property -name "xsim.simulate.tcl.post" -value "" -objects $obj +set_property -name "xsim.simulate.wdb" -value "" -objects $obj +set_property -name "xsim.simulate.xsim.more_options" -value "" -objects $obj + +# Set 'utils_1' fileset object +set obj [get_filesets utils_1] +# Empty (no sources present) + +# Set 'utils_1' fileset properties +set obj [get_filesets utils_1] +set_property -name "name" -value "utils_1" -objects $obj + + +# Adding sources referenced in BDs, if not already added + + +# Proc to create BD a2x_axi_bd +proc cr_bd_a2x_axi_bd { parentCell } { + + # CHANGE DESIGN NAME HERE + set design_name a2x_axi_bd + + common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + set bCheckIPsPassed 1 + ################################################################## + # CHECK IPs + ################################################################## + set bCheckIPs 1 + if { $bCheckIPs == 1 } { + set list_check_ips "\ + user.org:user:a2x_axi:1.0\ + user.org:user:a2x_axi_reg:1.0\ + user.org:user:a2x_dbug:1.0\ + user.org:user:a2x_reset:1.0\ + user.org:user:reverserator_3:1.0\ + user.org:user:reverserator_4:1.0\ + user.org:user:reverserator_32:1.0\ + user.org:user:reverserator_64:1.0\ + xilinx.com:ip:axi_bram_ctrl:4.1\ + xilinx.com:ip:axi_protocol_checker:2.0\ + xilinx.com:ip:smartconnect:1.0\ + xilinx.com:ip:blk_mem_gen:8.4\ + xilinx.com:ip:clk_wiz:6.0\ + xilinx.com:ip:system_ila:1.1\ + xilinx.com:ip:jtag_axi:1.2\ + xilinx.com:ip:xlconstant:1.1\ + xilinx.com:ip:vio:3.0\ + " + + set list_ips_missing "" + common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + + } + + if { $bCheckIPsPassed != 1 } { + common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 + } + + variable script_folder + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + + # Create ports + set clk_in1_n_0 [ create_bd_port -dir I -type clk clk_in1_n_0 ] + set clk_in1_p_0 [ create_bd_port -dir I -type clk clk_in1_p_0 ] + + # Create instance: a2x_axi_1, and set properties + set a2x_axi_1 [ create_bd_cell -type ip -vlnv user.org:user:a2x_axi:1.0 a2x_axi_1 ] + + # Create instance: a2x_axi_reg_0, and set properties + set a2x_axi_reg_0 [ create_bd_cell -type ip -vlnv user.org:user:a2x_axi_reg:1.0 a2x_axi_reg_0 ] + + # Create instance: a2x_dbug, and set properties + set a2x_dbug [ create_bd_cell -type ip -vlnv user.org:user:a2x_dbug:1.0 a2x_dbug ] + + # Create instance: a2x_reset_0, and set properties + set a2x_reset_0 [ create_bd_cell -type ip -vlnv user.org:user:a2x_reset:1.0 a2x_reset_0 ] + + # Create instance: axi_bram_ctrl_1, and set properties + set axi_bram_ctrl_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 axi_bram_ctrl_1 ] + set_property -dict [ list \ + CONFIG.SINGLE_PORT_BRAM {1} \ + ] $axi_bram_ctrl_1 + + # Create instance: axi_bram_ctrl_2, and set properties + set axi_bram_ctrl_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 axi_bram_ctrl_2 ] + set_property -dict [ list \ + CONFIG.SINGLE_PORT_BRAM {1} \ + ] $axi_bram_ctrl_2 + + # Create instance: axi_protocol_checker, and set properties + set axi_protocol_checker [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_protocol_checker:2.0 axi_protocol_checker ] + set_property -dict [ list \ + CONFIG.ENABLE_CONTROL {1} \ + CONFIG.ENABLE_MARK_DEBUG {0} \ + CONFIG.HAS_SYSTEM_RESET {1} \ + CONFIG.MAX_RD_BURSTS {4} \ + CONFIG.MAX_WR_BURSTS {4} \ + ] $axi_protocol_checker + + # Create instance: axi_reg00_rv, and set properties + set axi_reg00_rv [ create_bd_cell -type ip -vlnv user.org:user:reverserator_32:1.0 axi_reg00_rv ] + + # Create instance: axi_smc, and set properties + set axi_smc [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_smc ] + set_property -dict [ list \ + CONFIG.HAS_ARESETN {1} \ + CONFIG.NUM_MI {5} \ + CONFIG.NUM_SI {2} \ + ] $axi_smc + + # Create instance: blk_mem_gen_1, and set properties + set blk_mem_gen_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 blk_mem_gen_1 ] + + # Create instance: blk_mem_gen_2, and set properties + set blk_mem_gen_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 blk_mem_gen_2 ] + + # Create instance: checkstop_rv, and set properties + set checkstop_rv [ create_bd_cell -type ip -vlnv user.org:user:reverserator_3:1.0 checkstop_rv ] + + # Create instance: clk_wiz_0, and set properties + set clk_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0 ] + set_property -dict [ list \ + CONFIG.CLKIN1_JITTER_PS {33.330000000000005} \ + CONFIG.CLKOUT1_DRIVES {Buffer} \ + CONFIG.CLKOUT1_JITTER {143.207} \ + CONFIG.CLKOUT1_PHASE_ERROR {114.212} \ + CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {100.000} \ + CONFIG.CLKOUT2_DRIVES {Buffer} \ + CONFIG.CLKOUT2_JITTER {125.285} \ + CONFIG.CLKOUT2_PHASE_ERROR {114.212} \ + CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {200.000} \ + CONFIG.CLKOUT2_USED {true} \ + CONFIG.CLKOUT3_DRIVES {Buffer} \ + CONFIG.CLKOUT4_DRIVES {Buffer} \ + CONFIG.CLKOUT5_DRIVES {Buffer} \ + CONFIG.CLKOUT6_DRIVES {Buffer} \ + CONFIG.CLKOUT7_DRIVES {Buffer} \ + CONFIG.CLK_OUT1_PORT {clk} \ + CONFIG.CLK_OUT2_PORT {clk2x} \ + CONFIG.MMCM_BANDWIDTH {OPTIMIZED} \ + CONFIG.MMCM_CLKFBOUT_MULT_F {8} \ + CONFIG.MMCM_CLKIN1_PERIOD {3.333} \ + CONFIG.MMCM_CLKIN2_PERIOD {10.0} \ + CONFIG.MMCM_CLKOUT0_DIVIDE_F {8} \ + CONFIG.MMCM_CLKOUT1_DIVIDE {4} \ + CONFIG.MMCM_COMPENSATION {AUTO} \ + CONFIG.MMCM_DIVCLK_DIVIDE {3} \ + CONFIG.NUM_OUT_CLKS {2} \ + CONFIG.PRIMITIVE {PLL} \ + CONFIG.PRIM_IN_FREQ {300.000} \ + CONFIG.PRIM_SOURCE {Differential_clock_capable_pin} \ + CONFIG.RESET_PORT {resetn} \ + CONFIG.RESET_TYPE {ACTIVE_LOW} \ + CONFIG.USE_LOCKED {false} \ + CONFIG.USE_RESET {false} \ + ] $clk_wiz_0 + + # Create instance: ila_axi, and set properties + set ila_axi [ create_bd_cell -type ip -vlnv xilinx.com:ip:system_ila:1.1 ila_axi ] + set_property -dict [ list \ + CONFIG.ALL_PROBE_SAME_MU_CNT {2} \ + CONFIG.C_ADV_TRIGGER {true} \ + CONFIG.C_BRAM_CNT {48} \ + CONFIG.C_DATA_DEPTH {8192} \ + CONFIG.C_EN_STRG_QUAL {1} \ + CONFIG.C_INPUT_PIPE_STAGES {3} \ + CONFIG.C_PROBE0_MU_CNT {2} \ + CONFIG.C_SLOT_0_APC_EN {1} \ + CONFIG.C_SLOT_0_MAX_RD_BURSTS {8} \ + CONFIG.C_SLOT_0_MAX_WR_BURSTS {16} \ + CONFIG.C_TRIGIN_EN {true} \ + CONFIG.C_TRIGOUT_EN {true} \ + ] $ila_axi + + # Create instance: ila_axi_protocol, and set properties + set ila_axi_protocol [ create_bd_cell -type ip -vlnv xilinx.com:ip:system_ila:1.1 ila_axi_protocol ] + set_property -dict [ list \ + CONFIG.ALL_PROBE_SAME_MU_CNT {4} \ + CONFIG.C_BRAM_CNT {0.5} \ + CONFIG.C_DATA_DEPTH {2048} \ + CONFIG.C_EN_STRG_QUAL {1} \ + CONFIG.C_MON_TYPE {NATIVE} \ + CONFIG.C_NUM_MONITOR_SLOTS {2} \ + CONFIG.C_NUM_OF_PROBES {2} \ + CONFIG.C_PROBE0_MU_CNT {4} \ + CONFIG.C_PROBE1_MU_CNT {4} \ + CONFIG.C_TRIGIN_EN {false} \ + CONFIG.C_TRIGOUT_EN {true} \ + ] $ila_axi_protocol + + # Create instance: jtag_axi_0, and set properties + set jtag_axi_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:jtag_axi:1.2 jtag_axi_0 ] + + # Create instance: mchk_rv, and set properties + set mchk_rv [ create_bd_cell -type ip -vlnv user.org:user:reverserator_4:1.0 mchk_rv ] + + # Create instance: pain, and set properties + set pain [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 pain ] + set_property -dict [ list \ + CONFIG.CONST_VAL {0} \ + CONFIG.CONST_WIDTH {1} \ + ] $pain + + # Create instance: rcov_rv, and set properties + set rcov_rv [ create_bd_cell -type ip -vlnv user.org:user:reverserator_3:1.0 rcov_rv ] + + # Create instance: reverserator_4_0, and set properties + set reverserator_4_0 [ create_bd_cell -type ip -vlnv user.org:user:reverserator_4:1.0 reverserator_4_0 ] + + # Create instance: scomdata_rv, and set properties + set scomdata_rv [ create_bd_cell -type ip -vlnv user.org:user:reverserator_64:1.0 scomdata_rv ] + + # Create instance: thold_0, and set properties + set thold_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 thold_0 ] + set_property -dict [ list \ + CONFIG.CONST_VAL {0} \ + ] $thold_0 + + # Create instance: thread_running_rv, and set properties + set thread_running_rv [ create_bd_cell -type ip -vlnv user.org:user:reverserator_4:1.0 thread_running_rv ] + + # Create instance: vio_ctrl, and set properties + set vio_ctrl [ create_bd_cell -type ip -vlnv xilinx.com:ip:vio:3.0 vio_ctrl ] + set_property -dict [ list \ + CONFIG.C_NUM_PROBE_IN {16} \ + CONFIG.C_NUM_PROBE_OUT {17} \ + CONFIG.C_PROBE_OUT0_INIT_VAL {0xf} \ + CONFIG.C_PROBE_OUT0_WIDTH {4} \ + CONFIG.C_PROBE_OUT12_WIDTH {4} \ + CONFIG.C_PROBE_OUT13_WIDTH {4} \ + CONFIG.C_PROBE_OUT15_WIDTH {4} \ + CONFIG.C_PROBE_OUT1_INIT_VAL {0x1} \ + CONFIG.C_PROBE_OUT3_WIDTH {8} \ + CONFIG.C_PROBE_OUT4_WIDTH {4} \ + CONFIG.C_PROBE_OUT6_WIDTH {4} \ + CONFIG.C_PROBE_OUT7_WIDTH {4} \ + CONFIG.C_PROBE_OUT8_WIDTH {4} \ + CONFIG.C_PROBE_OUT9_INIT_VAL {0001} \ + ] $vio_ctrl + + # Create instance: vio_dbug, and set properties + set vio_dbug [ create_bd_cell -type ip -vlnv xilinx.com:ip:vio:3.0 vio_dbug ] + set_property -dict [ list \ + CONFIG.C_NUM_PROBE_IN {3} \ + CONFIG.C_NUM_PROBE_OUT {5} \ + CONFIG.C_PROBE_OUT1_INIT_VAL {0x1} \ + CONFIG.C_PROBE_OUT2_WIDTH {4} \ + CONFIG.C_PROBE_OUT3_WIDTH {6} \ + CONFIG.C_PROBE_OUT4_WIDTH {64} \ + ] $vio_dbug + + # Create instance: vio_reg, and set properties + set vio_reg [ create_bd_cell -type ip -vlnv xilinx.com:ip:vio:3.0 vio_reg ] + set_property -dict [ list \ + CONFIG.C_NUM_PROBE_IN {2} \ + CONFIG.C_NUM_PROBE_OUT {2} \ + CONFIG.C_PROBE_OUT0_INIT_VAL {00000000000000000000000000000000} \ + CONFIG.C_PROBE_OUT0_WIDTH {32} \ + CONFIG.C_PROBE_OUT1_INIT_VAL {00} \ + CONFIG.C_PROBE_OUT1_WIDTH {2} \ + ] $vio_reg + + # Create instance: vio_terror, and set properties + set vio_terror [ create_bd_cell -type ip -vlnv xilinx.com:ip:vio:3.0 vio_terror ] + set_property -dict [ list \ + CONFIG.C_NUM_PROBE_IN {4} \ + CONFIG.C_NUM_PROBE_OUT {0} \ + ] $vio_terror + + # Create instance: xlconstant_0, and set properties + set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ] + set_property -dict [ list \ + CONFIG.CONST_VAL {0} \ + CONFIG.CONST_WIDTH {2} \ + ] $xlconstant_0 + + # Create instance: xlconstant_1, and set properties + set xlconstant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_1 ] + set_property -dict [ list \ + CONFIG.CONST_VAL {0} \ + CONFIG.CONST_WIDTH {32} \ + ] $xlconstant_1 + + # Create interface connections + connect_bd_intf_net -intf_net a2x_axi_1_m00_axi [get_bd_intf_pins a2x_axi_1/m00_axi] [get_bd_intf_pins axi_smc/S00_AXI] +connect_bd_intf_net -intf_net [get_bd_intf_nets a2x_axi_1_m00_axi] [get_bd_intf_pins axi_protocol_checker/PC_AXI] [get_bd_intf_pins axi_smc/S00_AXI] +connect_bd_intf_net -intf_net [get_bd_intf_nets a2x_axi_1_m00_axi] [get_bd_intf_pins axi_smc/S00_AXI] [get_bd_intf_pins ila_axi/SLOT_0_AXI] + connect_bd_intf_net -intf_net axi_bram_ctrl_1_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl_1/BRAM_PORTA] [get_bd_intf_pins blk_mem_gen_1/BRAM_PORTA] + connect_bd_intf_net -intf_net axi_bram_ctrl_2_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl_2/BRAM_PORTA] [get_bd_intf_pins blk_mem_gen_2/BRAM_PORTA] + connect_bd_intf_net -intf_net axi_smc_M00_AXI [get_bd_intf_pins a2x_axi_reg_0/s_axi_intr] [get_bd_intf_pins axi_smc/M00_AXI] + connect_bd_intf_net -intf_net axi_smc_M01_AXI [get_bd_intf_pins axi_bram_ctrl_1/S_AXI] [get_bd_intf_pins axi_smc/M01_AXI] + connect_bd_intf_net -intf_net axi_smc_M02_AXI [get_bd_intf_pins axi_bram_ctrl_2/S_AXI] [get_bd_intf_pins axi_smc/M02_AXI] + connect_bd_intf_net -intf_net axi_smc_M03_AXI [get_bd_intf_pins a2x_axi_reg_0/s00_axi] [get_bd_intf_pins axi_smc/M03_AXI] + connect_bd_intf_net -intf_net axi_smc_M04_AXI [get_bd_intf_pins axi_protocol_checker/S_AXI] [get_bd_intf_pins axi_smc/M04_AXI] + connect_bd_intf_net -intf_net jtag_axi_0_M_AXI [get_bd_intf_pins axi_smc/S01_AXI] [get_bd_intf_pins jtag_axi_0/M_AXI] + + # Create port connections + connect_bd_net -net a2l2_err_rv [get_bd_pins reverserator_4_0/outtie] [get_bd_pins vio_ctrl/probe_in14] + connect_bd_net -net a2x_axi_1_a2l2_axi_err [get_bd_pins a2x_axi_1/a2l2_axi_err] [get_bd_pins reverserator_4_0/innnie] + connect_bd_net -net a2x_axi_1_checkstop [get_bd_pins a2x_axi_1/checkstop] [get_bd_pins checkstop_rv/outdoor] + connect_bd_net -net a2x_axi_1_scom_cch_out [get_bd_pins a2x_axi_1/scom_cch_out] [get_bd_pins a2x_dbug/cch_in] + connect_bd_net -net a2x_axi_1_scom_dch_out [get_bd_pins a2x_axi_1/scom_dch_out] [get_bd_pins a2x_dbug/dch_in] + connect_bd_net -net a2x_axi_1_thread_running [get_bd_pins a2x_axi_1/thread_running] [get_bd_pins thread_running_rv/innnie] + connect_bd_net -net a2x_axi_reg_0_irq [get_bd_pins a2x_axi_reg_0/irq] [get_bd_pins vio_reg/probe_in0] + connect_bd_net -net a2x_axi_reg_0_reg_out_00 [get_bd_pins a2x_axi_reg_0/reg_out_00] [get_bd_pins axi_reg00_rv/hell] + connect_bd_net -net a2x_dbug_0_cch_out [get_bd_pins a2x_axi_1/scom_cch_in] [get_bd_pins a2x_dbug/cch_out] + connect_bd_net -net a2x_dbug_0_dch_out [get_bd_pins a2x_axi_1/scom_dch_in] [get_bd_pins a2x_dbug/dch_out] + connect_bd_net -net a2x_dbug_0_err [get_bd_pins a2x_dbug/err] [get_bd_pins vio_dbug/probe_in1] + connect_bd_net -net a2x_dbug_0_rsp_valid [get_bd_pins a2x_dbug/rsp_valid] [get_bd_pins vio_dbug/probe_in0] + connect_bd_net -net a2x_dbug_1_rsp_data [get_bd_pins a2x_dbug/rsp_data] [get_bd_pins scomdata_rv/parkavenue] + connect_bd_net -net a2x_dbug_threadstop_out [get_bd_pins a2x_axi_1/thread_stop] [get_bd_pins a2x_dbug/threadstop_out] + connect_bd_net -net a2x_dbug_trigger_out [get_bd_pins a2x_dbug/trigger_out] [get_bd_pins ila_axi/TRIG_IN_trig] + connect_bd_net -net a2x_reset_0_reset [get_bd_pins a2x_axi_1/reset_n] [get_bd_pins a2x_axi_reg_0/s00_axi_aresetn] [get_bd_pins a2x_axi_reg_0/s_axi_intr_aresetn] [get_bd_pins a2x_dbug/reset_n] [get_bd_pins a2x_reset_0/reset] [get_bd_pins axi_bram_ctrl_1/s_axi_aresetn] [get_bd_pins axi_bram_ctrl_2/s_axi_aresetn] [get_bd_pins axi_protocol_checker/aresetn] [get_bd_pins axi_smc/aresetn] [get_bd_pins ila_axi/resetn] [get_bd_pins jtag_axi_0/aresetn] + connect_bd_net -net axi_protocol_checker_pc_asserted [get_bd_pins axi_protocol_checker/pc_asserted] [get_bd_pins ila_axi_protocol/probe1] [get_bd_pins vio_ctrl/probe_in0] + connect_bd_net -net axi_protocol_checker_pc_status [get_bd_pins axi_protocol_checker/pc_status] [get_bd_pins ila_axi_protocol/probe0] + connect_bd_net -net axi_reg00_rv [get_bd_pins axi_reg00_rv/cowboys] [get_bd_pins vio_reg/probe_in1] + connect_bd_net -net checkstop_rv [get_bd_pins checkstop_rv/inndoor] [get_bd_pins vio_terror/probe_in2] + connect_bd_net -net clk_in1_n_0_1 [get_bd_ports clk_in1_n_0] [get_bd_pins clk_wiz_0/clk_in1_n] + connect_bd_net -net clk_in1_p_0_1 [get_bd_ports clk_in1_p_0] [get_bd_pins clk_wiz_0/clk_in1_p] + connect_bd_net -net clk_wiz_0_clk [get_bd_pins a2x_axi_1/clk] [get_bd_pins a2x_axi_reg_0/s00_axi_aclk] [get_bd_pins a2x_axi_reg_0/s_axi_intr_aclk] [get_bd_pins a2x_dbug/clk] [get_bd_pins a2x_reset_0/clk] [get_bd_pins axi_bram_ctrl_1/s_axi_aclk] [get_bd_pins axi_bram_ctrl_2/s_axi_aclk] [get_bd_pins axi_protocol_checker/aclk] [get_bd_pins axi_smc/aclk] [get_bd_pins clk_wiz_0/clk] [get_bd_pins ila_axi/clk] [get_bd_pins ila_axi_protocol/clk] [get_bd_pins jtag_axi_0/aclk] [get_bd_pins vio_ctrl/clk] [get_bd_pins vio_dbug/clk] [get_bd_pins vio_reg/clk] [get_bd_pins vio_terror/clk] + connect_bd_net -net clk_wiz_0_clk2x [get_bd_pins a2x_axi_1/clk2x] [get_bd_pins clk_wiz_0/clk2x] + connect_bd_net -net ila_axi_protocol_TRIG_OUT_trig [get_bd_pins a2x_dbug/trigger_in] [get_bd_pins ila_axi_protocol/TRIG_OUT_trig] [get_bd_pins vio_ctrl/probe_in1] + connect_bd_net -net marvio_probe_out0 [get_bd_pins a2x_dbug/threadstop_in] [get_bd_pins vio_ctrl/probe_out0] + connect_bd_net -net marvio_probe_out2 [get_bd_pins ila_axi_protocol/TRIG_OUT_ack] [get_bd_pins vio_ctrl/probe_out2] + connect_bd_net -net marvio_probe_out14 [get_bd_pins a2x_dbug/trigger_ack_enable] [get_bd_pins vio_ctrl/probe_out14] + connect_bd_net -net marvio_probe_out15 [get_bd_pins a2x_dbug/trigger_threadstop] [get_bd_pins vio_ctrl/probe_out15] + connect_bd_net -net marvio_probe_out16 [get_bd_pins a2x_axi_1/debug_stop] [get_bd_pins vio_ctrl/probe_out16] + connect_bd_net -net mch [get_bd_pins a2x_axi_1/mchk] [get_bd_pins mchk_rv/innnie] + connect_bd_net -net mchk_rv [get_bd_pins mchk_rv/outtie] [get_bd_pins vio_terror/probe_in0] + connect_bd_net -net rcov_r [get_bd_pins a2x_axi_1/recov_err] [get_bd_pins rcov_rv/outdoor] + connect_bd_net -net rcov_rv [get_bd_pins rcov_rv/inndoor] [get_bd_pins vio_terror/probe_in1] + connect_bd_net -net scomdata_rv [get_bd_pins scomdata_rv/skidrowwww] [get_bd_pins vio_dbug/probe_in2] + connect_bd_net -net thread_running_rv [get_bd_pins thread_running_rv/outtie] [get_bd_pins vio_ctrl/probe_in2] + connect_bd_net -net unused_zero [get_bd_pins pain/dout] [get_bd_pins vio_ctrl/probe_in3] [get_bd_pins vio_ctrl/probe_in4] [get_bd_pins vio_ctrl/probe_in5] [get_bd_pins vio_ctrl/probe_in6] [get_bd_pins vio_ctrl/probe_in7] [get_bd_pins vio_ctrl/probe_in8] [get_bd_pins vio_ctrl/probe_in9] [get_bd_pins vio_ctrl/probe_in10] [get_bd_pins vio_ctrl/probe_in11] [get_bd_pins vio_ctrl/probe_in12] [get_bd_pins vio_ctrl/probe_in13] [get_bd_pins vio_ctrl/probe_in15] [get_bd_pins vio_terror/probe_in3] + connect_bd_net -net vio_0_probe_out0 [get_bd_pins a2x_dbug/req_valid] [get_bd_pins vio_dbug/probe_out0] + connect_bd_net -net vio_0_probe_out1 [get_bd_pins a2x_reset_0/reset_in] [get_bd_pins vio_ctrl/probe_out1] + connect_bd_net -net vio_0_probe_out2 [get_bd_pins a2x_dbug/req_id] [get_bd_pins vio_dbug/probe_out2] + connect_bd_net -net vio_0_probe_out3 [get_bd_pins a2x_axi_1/core_id] [get_bd_pins vio_ctrl/probe_out3] + connect_bd_net -net vio_0_probe_out4 [get_bd_pins a2x_axi_1/ext_mchk] [get_bd_pins vio_ctrl/probe_out4] + connect_bd_net -net vio_0_probe_out5 [get_bd_pins a2x_axi_1/ext_checkstop] [get_bd_pins vio_ctrl/probe_out5] + connect_bd_net -net vio_0_probe_out6 [get_bd_pins a2x_axi_1/crit_interrupt] [get_bd_pins vio_ctrl/probe_out6] + connect_bd_net -net vio_0_probe_out7 [get_bd_pins a2x_axi_1/ext_interrupt] [get_bd_pins vio_ctrl/probe_out7] + connect_bd_net -net vio_0_probe_out8 [get_bd_pins a2x_axi_1/perf_interrupt] [get_bd_pins vio_ctrl/probe_out8] + connect_bd_net -net vio_0_probe_out9 [get_bd_pins a2x_axi_1/tb_update_enable] [get_bd_pins vio_ctrl/probe_out9] + connect_bd_net -net vio_0_probe_out10 [get_bd_pins a2x_axi_1/tb_update_pulse] [get_bd_pins vio_ctrl/probe_out10] + connect_bd_net -net vio_0_probe_out11 [get_bd_pins a2x_axi_1/flh2l2_gate] [get_bd_pins vio_ctrl/probe_out11] + connect_bd_net -net vio_0_probe_out12 [get_bd_pins a2x_axi_1/hang_pulse] [get_bd_pins vio_ctrl/probe_out12] + connect_bd_net -net vio_0_probe_out13 [get_bd_pins a2x_axi_1/scom_sat_id] [get_bd_pins vio_ctrl/probe_out13] + connect_bd_net -net vio_0_probe_out14 [get_bd_pins a2x_dbug/req_wr_data] [get_bd_pins vio_dbug/probe_out4] + connect_bd_net -net vio_0_probe_out15 [get_bd_pins a2x_dbug/req_addr] [get_bd_pins vio_dbug/probe_out3] + connect_bd_net -net vio_0_probe_out16 [get_bd_pins a2x_dbug/req_rw] [get_bd_pins vio_dbug/probe_out1] + connect_bd_net -net vio_0_probe_out17 [get_bd_pins a2x_axi_reg_0/reg_in_00] [get_bd_pins vio_reg/probe_out0] + connect_bd_net -net vio_0_probe_out18 [get_bd_pins a2x_axi_reg_0/reg_cmd_00] [get_bd_pins vio_reg/probe_out1] + connect_bd_net -net xlconstant_0_dout [get_bd_pins a2x_axi_reg_0/reg_cmd_01] [get_bd_pins a2x_axi_reg_0/reg_cmd_02] [get_bd_pins a2x_axi_reg_0/reg_cmd_03] [get_bd_pins a2x_axi_reg_0/reg_cmd_04] [get_bd_pins a2x_axi_reg_0/reg_cmd_05] [get_bd_pins a2x_axi_reg_0/reg_cmd_06] [get_bd_pins a2x_axi_reg_0/reg_cmd_07] [get_bd_pins a2x_axi_reg_0/reg_cmd_08] [get_bd_pins a2x_axi_reg_0/reg_cmd_09] [get_bd_pins a2x_axi_reg_0/reg_cmd_0A] [get_bd_pins a2x_axi_reg_0/reg_cmd_0B] [get_bd_pins a2x_axi_reg_0/reg_cmd_0C] [get_bd_pins a2x_axi_reg_0/reg_cmd_0D] [get_bd_pins a2x_axi_reg_0/reg_cmd_0E] [get_bd_pins a2x_axi_reg_0/reg_cmd_0F] [get_bd_pins xlconstant_0/dout] + connect_bd_net -net xlconstant_1_dout [get_bd_pins a2x_axi_reg_0/reg_in_01] [get_bd_pins a2x_axi_reg_0/reg_in_02] [get_bd_pins a2x_axi_reg_0/reg_in_03] [get_bd_pins a2x_axi_reg_0/reg_in_04] [get_bd_pins a2x_axi_reg_0/reg_in_05] [get_bd_pins a2x_axi_reg_0/reg_in_06] [get_bd_pins a2x_axi_reg_0/reg_in_07] [get_bd_pins a2x_axi_reg_0/reg_in_08] [get_bd_pins a2x_axi_reg_0/reg_in_09] [get_bd_pins a2x_axi_reg_0/reg_in_0A] [get_bd_pins a2x_axi_reg_0/reg_in_0B] [get_bd_pins a2x_axi_reg_0/reg_in_0C] [get_bd_pins a2x_axi_reg_0/reg_in_0D] [get_bd_pins a2x_axi_reg_0/reg_in_0E] [get_bd_pins a2x_axi_reg_0/reg_in_0F] [get_bd_pins xlconstant_1/dout] + connect_bd_net -net xlconstant_2_dout [get_bd_pins a2x_axi_1/thold] [get_bd_pins thold_0/dout] + + # Create address segments + create_bd_addr_seg -range 0x00001000 -offset 0xFFFFE000 [get_bd_addr_spaces a2x_axi_1/m00_axi] [get_bd_addr_segs a2x_axi_reg_0/s_axi_intr/reg0] SEG_a2x_axi_reg_0_reg0 + create_bd_addr_seg -range 0x00001000 -offset 0xFFFFF000 [get_bd_addr_spaces a2x_axi_1/m00_axi] [get_bd_addr_segs a2x_axi_reg_0/s00_axi/reg0] SEG_a2x_axi_reg_0_reg01 + create_bd_addr_seg -range 0x00040000 -offset 0x00000000 [get_bd_addr_spaces a2x_axi_1/m00_axi] [get_bd_addr_segs axi_bram_ctrl_1/S_AXI/Mem0] SEG_axi_bram_ctrl_1_Mem0 + create_bd_addr_seg -range 0x00100000 -offset 0x10000000 [get_bd_addr_spaces a2x_axi_1/m00_axi] [get_bd_addr_segs axi_bram_ctrl_2/S_AXI/Mem0] SEG_axi_bram_ctrl_2_Mem0 + create_bd_addr_seg -range 0x00010000 -offset 0xFE000000 [get_bd_addr_spaces a2x_axi_1/m00_axi] [get_bd_addr_segs axi_protocol_checker/S_AXI/Reg] SEG_axi_protocol_checker_Reg + create_bd_addr_seg -range 0x00001000 -offset 0xFFFFE000 [get_bd_addr_spaces jtag_axi_0/Data] [get_bd_addr_segs a2x_axi_reg_0/s_axi_intr/reg0] SEG_a2x_axi_reg_0_reg0 + create_bd_addr_seg -range 0x00001000 -offset 0xFFFFF000 [get_bd_addr_spaces jtag_axi_0/Data] [get_bd_addr_segs a2x_axi_reg_0/s00_axi/reg0] SEG_a2x_axi_reg_0_reg03 + create_bd_addr_seg -range 0x00040000 -offset 0x00000000 [get_bd_addr_spaces jtag_axi_0/Data] [get_bd_addr_segs axi_bram_ctrl_1/S_AXI/Mem0] SEG_axi_bram_ctrl_1_Mem0 + create_bd_addr_seg -range 0x00100000 -offset 0x10000000 [get_bd_addr_spaces jtag_axi_0/Data] [get_bd_addr_segs axi_bram_ctrl_2/S_AXI/Mem0] SEG_axi_bram_ctrl_2_Mem0 + create_bd_addr_seg -range 0x00010000 -offset 0xFE000000 [get_bd_addr_spaces jtag_axi_0/Data] [get_bd_addr_segs axi_protocol_checker/S_AXI/Reg] SEG_axi_protocol_checker_Reg + + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design + close_bd_design $design_name +} +# End of cr_bd_a2x_axi_bd() +cr_bd_a2x_axi_bd "" +set_property EXCLUDE_DEBUG_LOGIC "0" [get_files a2x_axi_bd.bd ] +set_property GENERATE_SYNTH_CHECKPOINT "0" [get_files a2x_axi_bd.bd ] +set_property IS_ENABLED "1" [get_files a2x_axi_bd.bd ] +set_property IS_GLOBAL_INCLUDE "0" [get_files a2x_axi_bd.bd ] +set_property IS_LOCKED "0" [get_files a2x_axi_bd.bd ] +set_property LIBRARY "xil_defaultlib" [get_files a2x_axi_bd.bd ] +set_property PATH_MODE "RelativeFirst" [get_files a2x_axi_bd.bd ] +set_property PFM_NAME "" [get_files a2x_axi_bd.bd ] +set_property REGISTERED_WITH_MANAGER "1" [get_files a2x_axi_bd.bd ] +set_property SYNTH_CHECKPOINT_MODE "None" [get_files a2x_axi_bd.bd ] +set_property USED_IN "synthesis implementation simulation" [get_files a2x_axi_bd.bd ] +set_property USED_IN_IMPLEMENTATION "1" [get_files a2x_axi_bd.bd ] +set_property USED_IN_SIMULATION "1" [get_files a2x_axi_bd.bd ] +set_property USED_IN_SYNTHESIS "1" [get_files a2x_axi_bd.bd ] + +# Create 'synth_1' run (if not found) +if {[string equal [get_runs -quiet synth_1] ""]} { + create_run -name synth_1 -part xcvu3p-ffvc1517-2-e -flow {Vivado Synthesis 2019} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1 +} else { + set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1] + set_property flow "Vivado Synthesis 2019" [get_runs synth_1] +} +set obj [get_runs synth_1] +set_property set_report_strategy_name 1 $obj +set_property report_strategy {Vivado Synthesis Default Reports} $obj +set_property set_report_strategy_name 0 $obj +# Create 'synth_1_synth_report_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } { + create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1 +} +set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "options.pblocks" -value "" -objects $obj +set_property -name "options.cells" -value "" -objects $obj +set_property -name "options.slr" -value "0" -objects $obj +set_property -name "options.packthru" -value "0" -objects $obj +set_property -name "options.hierarchical" -value "0" -objects $obj +set_property -name "options.hierarchical_depth" -value "" -objects $obj +set_property -name "options.hierarchical_percentages" -value "0" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +set obj [get_runs synth_1] +set_property -name "constrset" -value "constrs_1" -objects $obj +set_property -name "description" -value "Vivado Synthesis Defaults" -objects $obj +set_property -name "flow" -value "Vivado Synthesis 2019" -objects $obj +set_property -name "name" -value "synth_1" -objects $obj +set_property -name "needs_refresh" -value "0" -objects $obj +set_property -name "part" -value "xcvu3p-ffvc1517-2-e" -objects $obj +set_property -name "srcset" -value "sources_1" -objects $obj +set_property -name "auto_incremental_checkpoint" -value "0" -objects $obj +set_property -name "incremental_checkpoint" -value "" -objects $obj +set_property -name "incremental_checkpoint.more_options" -value "" -objects $obj +set_property -name "include_in_archive" -value "1" -objects $obj +set_property -name "gen_full_bitstream" -value "1" -objects $obj +set_property -name "write_incremental_synth_checkpoint" -value "0" -objects $obj +set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj +set_property -name "steps.synth_design.tcl.pre" -value "" -objects $obj +set_property -name "steps.synth_design.tcl.post" -value "" -objects $obj +set_property -name "steps.synth_design.args.flatten_hierarchy" -value "rebuilt" -objects $obj +set_property -name "steps.synth_design.args.gated_clock_conversion" -value "off" -objects $obj +set_property -name "steps.synth_design.args.bufg" -value "12" -objects $obj +set_property -name "steps.synth_design.args.fanout_limit" -value "10000" -objects $obj +set_property -name "steps.synth_design.args.directive" -value "Default" -objects $obj +set_property -name "steps.synth_design.args.retiming" -value "0" -objects $obj +set_property -name "steps.synth_design.args.fsm_extraction" -value "auto" -objects $obj +set_property -name "steps.synth_design.args.keep_equivalent_registers" -value "0" -objects $obj +set_property -name "steps.synth_design.args.resource_sharing" -value "auto" -objects $obj +set_property -name "steps.synth_design.args.control_set_opt_threshold" -value "auto" -objects $obj +set_property -name "steps.synth_design.args.no_lc" -value "0" -objects $obj +set_property -name "steps.synth_design.args.no_srlextract" -value "0" -objects $obj +set_property -name "steps.synth_design.args.shreg_min_size" -value "3" -objects $obj +set_property -name "steps.synth_design.args.max_bram" -value "-1" -objects $obj +set_property -name "steps.synth_design.args.max_uram" -value "-1" -objects $obj +set_property -name "steps.synth_design.args.max_dsp" -value "-1" -objects $obj +set_property -name "steps.synth_design.args.max_bram_cascade_height" -value "-1" -objects $obj +set_property -name "steps.synth_design.args.max_uram_cascade_height" -value "-1" -objects $obj +set_property -name "steps.synth_design.args.cascade_dsp" -value "auto" -objects $obj +set_property -name "steps.synth_design.args.assert" -value "0" -objects $obj +set_property -name "steps.synth_design.args.more options" -value "-verbose" -objects $obj + +# Create 'synth_2' run (if not found) +if {[string equal [get_runs -quiet synth_2] ""]} { + create_run -name synth_2 -part xcvu3p-ffvc1517-2-e -flow {Vivado Synthesis 2019} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1 +} else { + set_property strategy "Vivado Synthesis Defaults" [get_runs synth_2] + set_property flow "Vivado Synthesis 2019" [get_runs synth_2] +} +set obj [get_runs synth_2] +set_property set_report_strategy_name 1 $obj +set_property report_strategy {Vivado Synthesis Default Reports} $obj +set_property set_report_strategy_name 0 $obj +# Create 'synth_2_synth_report_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs synth_2] synth_2_synth_report_utilization_0] "" ] } { + create_report_config -report_name synth_2_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_2 +} +set obj [get_report_configs -of_objects [get_runs synth_2] synth_2_synth_report_utilization_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "options.pblocks" -value "" -objects $obj +set_property -name "options.cells" -value "" -objects $obj +set_property -name "options.slr" -value "0" -objects $obj +set_property -name "options.packthru" -value "0" -objects $obj +set_property -name "options.hierarchical" -value "0" -objects $obj +set_property -name "options.hierarchical_depth" -value "" -objects $obj +set_property -name "options.hierarchical_percentages" -value "0" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +set obj [get_runs synth_2] +set_property -name "constrset" -value "constrs_1" -objects $obj +set_property -name "description" -value "Vivado Synthesis Defaults" -objects $obj +set_property -name "flow" -value "Vivado Synthesis 2019" -objects $obj +set_property -name "name" -value "synth_2" -objects $obj +set_property -name "needs_refresh" -value "0" -objects $obj +set_property -name "part" -value "xcvu3p-ffvc1517-2-e" -objects $obj +set_property -name "srcset" -value "sources_1" -objects $obj +set_property -name "auto_incremental_checkpoint" -value "0" -objects $obj +set_property -name "incremental_checkpoint" -value "" -objects $obj +set_property -name "incremental_checkpoint.more_options" -value "" -objects $obj +set_property -name "include_in_archive" -value "1" -objects $obj +set_property -name "gen_full_bitstream" -value "1" -objects $obj +set_property -name "write_incremental_synth_checkpoint" -value "0" -objects $obj +set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj +set_property -name "steps.synth_design.tcl.pre" -value "" -objects $obj +set_property -name "steps.synth_design.tcl.post" -value "" -objects $obj +set_property -name "steps.synth_design.args.flatten_hierarchy" -value "none" -objects $obj +set_property -name "steps.synth_design.args.gated_clock_conversion" -value "off" -objects $obj +set_property -name "steps.synth_design.args.bufg" -value "12" -objects $obj +set_property -name "steps.synth_design.args.fanout_limit" -value "10000" -objects $obj +set_property -name "steps.synth_design.args.directive" -value "Default" -objects $obj +set_property -name "steps.synth_design.args.retiming" -value "0" -objects $obj +set_property -name "steps.synth_design.args.fsm_extraction" -value "auto" -objects $obj +set_property -name "steps.synth_design.args.keep_equivalent_registers" -value "0" -objects $obj +set_property -name "steps.synth_design.args.resource_sharing" -value "auto" -objects $obj +set_property -name "steps.synth_design.args.control_set_opt_threshold" -value "auto" -objects $obj +set_property -name "steps.synth_design.args.no_lc" -value "0" -objects $obj +set_property -name "steps.synth_design.args.no_srlextract" -value "0" -objects $obj +set_property -name "steps.synth_design.args.shreg_min_size" -value "3" -objects $obj +set_property -name "steps.synth_design.args.max_bram" -value "-1" -objects $obj +set_property -name "steps.synth_design.args.max_uram" -value "-1" -objects $obj +set_property -name "steps.synth_design.args.max_dsp" -value "-1" -objects $obj +set_property -name "steps.synth_design.args.max_bram_cascade_height" -value "-1" -objects $obj +set_property -name "steps.synth_design.args.max_uram_cascade_height" -value "-1" -objects $obj +set_property -name "steps.synth_design.args.cascade_dsp" -value "auto" -objects $obj +set_property -name "steps.synth_design.args.assert" -value "0" -objects $obj +set_property -name "steps.synth_design.args.more options" -value "-verbose" -objects $obj + +# set the current synth run +current_run -synthesis [get_runs synth_2] + +# Create 'impl_1' run (if not found) +if {[string equal [get_runs -quiet impl_1] ""]} { + create_run -name impl_1 -part xcvu3p-ffvc1517-2-e -flow {Vivado Implementation 2019} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1 +} else { + set_property strategy "Vivado Implementation Defaults" [get_runs impl_1] + set_property flow "Vivado Implementation 2019" [get_runs impl_1] +} +set obj [get_runs impl_1] +set_property set_report_strategy_name 1 $obj +set_property report_strategy {Vivado Implementation Default Reports} $obj +set_property set_report_strategy_name 0 $obj +# Create 'impl_1_init_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.check_timing_verbose" -value "0" -objects $obj +set_property -name "options.delay_type" -value "" -objects $obj +set_property -name "options.setup" -value "0" -objects $obj +set_property -name "options.hold" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.nworst" -value "" -objects $obj +set_property -name "options.unique_pins" -value "0" -objects $obj +set_property -name "options.path_type" -value "" -objects $obj +set_property -name "options.slack_lesser_than" -value "" -objects $obj +set_property -name "options.report_unconstrained" -value "0" -objects $obj +set_property -name "options.warn_on_violation" -value "0" -objects $obj +set_property -name "options.significant_digits" -value "" -objects $obj +set_property -name "options.cell" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_opt_report_drc_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } { + create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "options.upgrade_cw" -value "0" -objects $obj +set_property -name "options.checks" -value "" -objects $obj +set_property -name "options.ruledecks" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.check_timing_verbose" -value "0" -objects $obj +set_property -name "options.delay_type" -value "" -objects $obj +set_property -name "options.setup" -value "0" -objects $obj +set_property -name "options.hold" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.nworst" -value "" -objects $obj +set_property -name "options.unique_pins" -value "0" -objects $obj +set_property -name "options.path_type" -value "" -objects $obj +set_property -name "options.slack_lesser_than" -value "" -objects $obj +set_property -name "options.report_unconstrained" -value "0" -objects $obj +set_property -name "options.warn_on_violation" -value "0" -objects $obj +set_property -name "options.significant_digits" -value "" -objects $obj +set_property -name "options.cell" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_power_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.check_timing_verbose" -value "0" -objects $obj +set_property -name "options.delay_type" -value "" -objects $obj +set_property -name "options.setup" -value "0" -objects $obj +set_property -name "options.hold" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.nworst" -value "" -objects $obj +set_property -name "options.unique_pins" -value "0" -objects $obj +set_property -name "options.path_type" -value "" -objects $obj +set_property -name "options.slack_lesser_than" -value "" -objects $obj +set_property -name "options.report_unconstrained" -value "0" -objects $obj +set_property -name "options.warn_on_violation" -value "0" -objects $obj +set_property -name "options.significant_digits" -value "" -objects $obj +set_property -name "options.cell" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_place_report_io_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } { + create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_place_report_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } { + create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "options.pblocks" -value "" -objects $obj +set_property -name "options.cells" -value "" -objects $obj +set_property -name "options.slr" -value "0" -objects $obj +set_property -name "options.packthru" -value "0" -objects $obj +set_property -name "options.hierarchical" -value "0" -objects $obj +set_property -name "options.hierarchical_depth" -value "" -objects $obj +set_property -name "options.hierarchical_percentages" -value "0" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_place_report_control_sets_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } { + create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "options.verbose" -value "1" -objects $obj +set_property -name "options.cells" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_place_report_incremental_reuse_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } { + create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.cells" -value "" -objects $obj +set_property -name "options.hierarchical" -value "0" -objects $obj +set_property -name "options.hierarchical_depth" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_place_report_incremental_reuse_1' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } { + create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.cells" -value "" -objects $obj +set_property -name "options.hierarchical" -value "0" -objects $obj +set_property -name "options.hierarchical_depth" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_place_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.check_timing_verbose" -value "0" -objects $obj +set_property -name "options.delay_type" -value "" -objects $obj +set_property -name "options.setup" -value "0" -objects $obj +set_property -name "options.hold" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.nworst" -value "" -objects $obj +set_property -name "options.unique_pins" -value "0" -objects $obj +set_property -name "options.path_type" -value "" -objects $obj +set_property -name "options.slack_lesser_than" -value "" -objects $obj +set_property -name "options.report_unconstrained" -value "0" -objects $obj +set_property -name "options.warn_on_violation" -value "0" -objects $obj +set_property -name "options.significant_digits" -value "" -objects $obj +set_property -name "options.cell" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.check_timing_verbose" -value "0" -objects $obj +set_property -name "options.delay_type" -value "" -objects $obj +set_property -name "options.setup" -value "0" -objects $obj +set_property -name "options.hold" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.nworst" -value "" -objects $obj +set_property -name "options.unique_pins" -value "0" -objects $obj +set_property -name "options.path_type" -value "" -objects $obj +set_property -name "options.slack_lesser_than" -value "" -objects $obj +set_property -name "options.report_unconstrained" -value "0" -objects $obj +set_property -name "options.warn_on_violation" -value "0" -objects $obj +set_property -name "options.significant_digits" -value "" -objects $obj +set_property -name "options.cell" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.check_timing_verbose" -value "0" -objects $obj +set_property -name "options.delay_type" -value "" -objects $obj +set_property -name "options.setup" -value "0" -objects $obj +set_property -name "options.hold" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.nworst" -value "" -objects $obj +set_property -name "options.unique_pins" -value "0" -objects $obj +set_property -name "options.path_type" -value "" -objects $obj +set_property -name "options.slack_lesser_than" -value "" -objects $obj +set_property -name "options.report_unconstrained" -value "0" -objects $obj +set_property -name "options.warn_on_violation" -value "0" -objects $obj +set_property -name "options.significant_digits" -value "" -objects $obj +set_property -name "options.cell" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_route_report_drc_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } { + create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "options.upgrade_cw" -value "0" -objects $obj +set_property -name "options.checks" -value "" -objects $obj +set_property -name "options.ruledecks" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_route_report_methodology_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } { + create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "options.checks" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_route_report_power_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } { + create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "options.advisory" -value "0" -objects $obj +set_property -name "options.xpe" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_route_report_route_status_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } { + create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "options.of_objects" -value "" -objects $obj +set_property -name "options.route_type" -value "" -objects $obj +set_property -name "options.list_all_nets" -value "0" -objects $obj +set_property -name "options.show_all" -value "0" -objects $obj +set_property -name "options.has_routing" -value "0" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_route_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "options.check_timing_verbose" -value "0" -objects $obj +set_property -name "options.delay_type" -value "" -objects $obj +set_property -name "options.setup" -value "0" -objects $obj +set_property -name "options.hold" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.nworst" -value "" -objects $obj +set_property -name "options.unique_pins" -value "0" -objects $obj +set_property -name "options.path_type" -value "" -objects $obj +set_property -name "options.slack_lesser_than" -value "" -objects $obj +set_property -name "options.report_unconstrained" -value "0" -objects $obj +set_property -name "options.warn_on_violation" -value "0" -objects $obj +set_property -name "options.significant_digits" -value "" -objects $obj +set_property -name "options.cell" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_route_report_incremental_reuse_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } { + create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "options.cells" -value "" -objects $obj +set_property -name "options.hierarchical" -value "0" -objects $obj +set_property -name "options.hierarchical_depth" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_route_report_clock_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } { + create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "options.write_xdc" -value "0" -objects $obj +set_property -name "options.clock_roots_only" -value "0" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_route_report_bus_skew_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } { + create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "options.delay_type" -value "" -objects $obj +set_property -name "options.setup" -value "0" -objects $obj +set_property -name "options.hold" -value "0" -objects $obj +set_property -name "options.max_paths" -value "" -objects $obj +set_property -name "options.nworst" -value "" -objects $obj +set_property -name "options.unique_pins" -value "0" -objects $obj +set_property -name "options.path_type" -value "" -objects $obj +set_property -name "options.slack_lesser_than" -value "" -objects $obj +set_property -name "options.slack_greater_than" -value "" -objects $obj +set_property -name "options.significant_digits" -value "" -objects $obj +set_property -name "options.warn_on_violation" -value "1" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "options.check_timing_verbose" -value "0" -objects $obj +set_property -name "options.delay_type" -value "" -objects $obj +set_property -name "options.setup" -value "0" -objects $obj +set_property -name "options.hold" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.nworst" -value "" -objects $obj +set_property -name "options.unique_pins" -value "0" -objects $obj +set_property -name "options.path_type" -value "" -objects $obj +set_property -name "options.slack_lesser_than" -value "" -objects $obj +set_property -name "options.report_unconstrained" -value "0" -objects $obj +set_property -name "options.warn_on_violation" -value "1" -objects $obj +set_property -name "options.significant_digits" -value "" -objects $obj +set_property -name "options.cell" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_post_route_phys_opt_report_bus_skew_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } { + create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "options.delay_type" -value "" -objects $obj +set_property -name "options.setup" -value "0" -objects $obj +set_property -name "options.hold" -value "0" -objects $obj +set_property -name "options.max_paths" -value "" -objects $obj +set_property -name "options.nworst" -value "" -objects $obj +set_property -name "options.unique_pins" -value "0" -objects $obj +set_property -name "options.path_type" -value "" -objects $obj +set_property -name "options.slack_lesser_than" -value "" -objects $obj +set_property -name "options.slack_greater_than" -value "" -objects $obj +set_property -name "options.significant_digits" -value "" -objects $obj +set_property -name "options.warn_on_violation" -value "1" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +set obj [get_runs impl_1] +set_property -name "constrset" -value "constrs_1" -objects $obj +set_property -name "description" -value "Default settings for Implementation." -objects $obj +set_property -name "flow" -value "Vivado Implementation 2019" -objects $obj +set_property -name "name" -value "impl_1" -objects $obj +set_property -name "needs_refresh" -value "0" -objects $obj +set_property -name "part" -value "xcvu3p-ffvc1517-2-e" -objects $obj +set_property -name "pr_configuration" -value "" -objects $obj +set_property -name "srcset" -value "sources_1" -objects $obj +set_property -name "auto_incremental_checkpoint" -value "0" -objects $obj +set_property -name "incremental_checkpoint" -value "" -objects $obj +set_property -name "incremental_checkpoint.more_options" -value "" -objects $obj +set_property -name "include_in_archive" -value "1" -objects $obj +set_property -name "gen_full_bitstream" -value "1" -objects $obj +set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj +set_property -name "steps.init_design.tcl.pre" -value "" -objects $obj +set_property -name "steps.init_design.tcl.post" -value "" -objects $obj +set_property -name "steps.opt_design.is_enabled" -value "1" -objects $obj +set_property -name "steps.opt_design.tcl.pre" -value "" -objects $obj +set_property -name "steps.opt_design.tcl.post" -value "" -objects $obj +set_property -name "steps.opt_design.args.verbose" -value "0" -objects $obj +set_property -name "steps.opt_design.args.directive" -value "Default" -objects $obj +set_property -name "steps.opt_design.args.more options" -value "" -objects $obj +set_property -name "steps.power_opt_design.is_enabled" -value "0" -objects $obj +set_property -name "steps.power_opt_design.tcl.pre" -value "" -objects $obj +set_property -name "steps.power_opt_design.tcl.post" -value "" -objects $obj +set_property -name "steps.power_opt_design.args.more options" -value "" -objects $obj +set_property -name "steps.place_design.tcl.pre" -value "" -objects $obj +set_property -name "steps.place_design.tcl.post" -value "" -objects $obj +set_property -name "steps.place_design.args.directive" -value "Default" -objects $obj +set_property -name "steps.place_design.args.more options" -value "" -objects $obj +set_property -name "steps.post_place_power_opt_design.is_enabled" -value "0" -objects $obj +set_property -name "steps.post_place_power_opt_design.tcl.pre" -value "" -objects $obj +set_property -name "steps.post_place_power_opt_design.tcl.post" -value "" -objects $obj +set_property -name "steps.post_place_power_opt_design.args.more options" -value "" -objects $obj +set_property -name "steps.phys_opt_design.is_enabled" -value "0" -objects $obj +set_property -name "steps.phys_opt_design.tcl.pre" -value "" -objects $obj +set_property -name "steps.phys_opt_design.tcl.post" -value "" -objects $obj +set_property -name "steps.phys_opt_design.args.directive" -value "Default" -objects $obj +set_property -name "steps.phys_opt_design.args.more options" -value "" -objects $obj +set_property -name "steps.route_design.tcl.pre" -value "" -objects $obj +set_property -name "steps.route_design.tcl.post" -value "" -objects $obj +set_property -name "steps.route_design.args.directive" -value "Default" -objects $obj +set_property -name "steps.route_design.args.more options" -value "" -objects $obj +set_property -name "steps.post_route_phys_opt_design.is_enabled" -value "0" -objects $obj +set_property -name "steps.post_route_phys_opt_design.tcl.pre" -value "" -objects $obj +set_property -name "steps.post_route_phys_opt_design.tcl.post" -value "" -objects $obj +set_property -name "steps.post_route_phys_opt_design.args.directive" -value "Default" -objects $obj +set_property -name "steps.post_route_phys_opt_design.args.more options" -value "" -objects $obj +set_property -name "steps.write_bitstream.tcl.pre" -value "" -objects $obj +set_property -name "steps.write_bitstream.tcl.post" -value "" -objects $obj +set_property -name "steps.write_bitstream.args.raw_bitfile" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.mask_file" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.no_binary_bitfile" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.bin_file" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.logic_location_file" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.more options" -value "" -objects $obj + +# Create 'impl_2' run (if not found) +if {[string equal [get_runs -quiet impl_2] ""]} { + create_run -name impl_2 -part xcvu3p-ffvc1517-2-e -flow {Vivado Implementation 2019} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_2 +} else { + set_property strategy "Vivado Implementation Defaults" [get_runs impl_2] + set_property flow "Vivado Implementation 2019" [get_runs impl_2] +} +set obj [get_runs impl_2] +set_property set_report_strategy_name 1 $obj +set_property report_strategy {Vivado Implementation Default Reports} $obj +set_property set_report_strategy_name 0 $obj +# Create 'impl_2_init_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_2] impl_2_init_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_2_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_2 +} +set obj [get_report_configs -of_objects [get_runs impl_2] impl_2_init_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.check_timing_verbose" -value "0" -objects $obj +set_property -name "options.delay_type" -value "" -objects $obj +set_property -name "options.setup" -value "0" -objects $obj +set_property -name "options.hold" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.nworst" -value "" -objects $obj +set_property -name "options.unique_pins" -value "0" -objects $obj +set_property -name "options.path_type" -value "" -objects $obj +set_property -name "options.slack_lesser_than" -value "" -objects $obj +set_property -name "options.report_unconstrained" -value "0" -objects $obj +set_property -name "options.warn_on_violation" -value "0" -objects $obj +set_property -name "options.significant_digits" -value "" -objects $obj +set_property -name "options.cell" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_2_opt_report_drc_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_2] impl_2_opt_report_drc_0] "" ] } { + create_report_config -report_name impl_2_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_2 +} +set obj [get_report_configs -of_objects [get_runs impl_2] impl_2_opt_report_drc_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "options.upgrade_cw" -value "0" -objects $obj +set_property -name "options.checks" -value "" -objects $obj +set_property -name "options.ruledecks" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_2_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_2] impl_2_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_2_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_2 +} +set obj [get_report_configs -of_objects [get_runs impl_2] impl_2_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.check_timing_verbose" -value "0" -objects $obj +set_property -name "options.delay_type" -value "" -objects $obj +set_property -name "options.setup" -value "0" -objects $obj +set_property -name "options.hold" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.nworst" -value "" -objects $obj +set_property -name "options.unique_pins" -value "0" -objects $obj +set_property -name "options.path_type" -value "" -objects $obj +set_property -name "options.slack_lesser_than" -value "" -objects $obj +set_property -name "options.report_unconstrained" -value "0" -objects $obj +set_property -name "options.warn_on_violation" -value "0" -objects $obj +set_property -name "options.significant_digits" -value "" -objects $obj +set_property -name "options.cell" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_2_power_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_2] impl_2_power_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_2_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_2 +} +set obj [get_report_configs -of_objects [get_runs impl_2] impl_2_power_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.check_timing_verbose" -value "0" -objects $obj +set_property -name "options.delay_type" -value "" -objects $obj +set_property -name "options.setup" -value "0" -objects $obj +set_property -name "options.hold" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.nworst" -value "" -objects $obj +set_property -name "options.unique_pins" -value "0" -objects $obj +set_property -name "options.path_type" -value "" -objects $obj +set_property -name "options.slack_lesser_than" -value "" -objects $obj +set_property -name "options.report_unconstrained" -value "0" -objects $obj +set_property -name "options.warn_on_violation" -value "0" -objects $obj +set_property -name "options.significant_digits" -value "" -objects $obj +set_property -name "options.cell" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_2_place_report_io_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_2] impl_2_place_report_io_0] "" ] } { + create_report_config -report_name impl_2_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_2 +} +set obj [get_report_configs -of_objects [get_runs impl_2] impl_2_place_report_io_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_2_place_report_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_2] impl_2_place_report_utilization_0] "" ] } { + create_report_config -report_name impl_2_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_2 +} +set obj [get_report_configs -of_objects [get_runs impl_2] impl_2_place_report_utilization_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "options.pblocks" -value "" -objects $obj +set_property -name "options.cells" -value "" -objects $obj +set_property -name "options.slr" -value "0" -objects $obj +set_property -name "options.packthru" -value "0" -objects $obj +set_property -name "options.hierarchical" -value "0" -objects $obj +set_property -name "options.hierarchical_depth" -value "" -objects $obj +set_property -name "options.hierarchical_percentages" -value "0" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_2_place_report_control_sets_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_2] impl_2_place_report_control_sets_0] "" ] } { + create_report_config -report_name impl_2_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_2 +} +set obj [get_report_configs -of_objects [get_runs impl_2] impl_2_place_report_control_sets_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "options.verbose" -value "1" -objects $obj +set_property -name "options.cells" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_2_place_report_incremental_reuse_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_2] impl_2_place_report_incremental_reuse_0] "" ] } { + create_report_config -report_name impl_2_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_2 +} +set obj [get_report_configs -of_objects [get_runs impl_2] impl_2_place_report_incremental_reuse_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.cells" -value "" -objects $obj +set_property -name "options.hierarchical" -value "0" -objects $obj +set_property -name "options.hierarchical_depth" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_2_place_report_incremental_reuse_1' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_2] impl_2_place_report_incremental_reuse_1] "" ] } { + create_report_config -report_name impl_2_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_2 +} +set obj [get_report_configs -of_objects [get_runs impl_2] impl_2_place_report_incremental_reuse_1] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.cells" -value "" -objects $obj +set_property -name "options.hierarchical" -value "0" -objects $obj +set_property -name "options.hierarchical_depth" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_2_place_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_2] impl_2_place_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_2_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_2 +} +set obj [get_report_configs -of_objects [get_runs impl_2] impl_2_place_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.check_timing_verbose" -value "0" -objects $obj +set_property -name "options.delay_type" -value "" -objects $obj +set_property -name "options.setup" -value "0" -objects $obj +set_property -name "options.hold" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.nworst" -value "" -objects $obj +set_property -name "options.unique_pins" -value "0" -objects $obj +set_property -name "options.path_type" -value "" -objects $obj +set_property -name "options.slack_lesser_than" -value "" -objects $obj +set_property -name "options.report_unconstrained" -value "0" -objects $obj +set_property -name "options.warn_on_violation" -value "0" -objects $obj +set_property -name "options.significant_digits" -value "" -objects $obj +set_property -name "options.cell" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_2_post_place_power_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_2] impl_2_post_place_power_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_2_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_2 +} +set obj [get_report_configs -of_objects [get_runs impl_2] impl_2_post_place_power_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.check_timing_verbose" -value "0" -objects $obj +set_property -name "options.delay_type" -value "" -objects $obj +set_property -name "options.setup" -value "0" -objects $obj +set_property -name "options.hold" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.nworst" -value "" -objects $obj +set_property -name "options.unique_pins" -value "0" -objects $obj +set_property -name "options.path_type" -value "" -objects $obj +set_property -name "options.slack_lesser_than" -value "" -objects $obj +set_property -name "options.report_unconstrained" -value "0" -objects $obj +set_property -name "options.warn_on_violation" -value "0" -objects $obj +set_property -name "options.significant_digits" -value "" -objects $obj +set_property -name "options.cell" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_2_phys_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_2] impl_2_phys_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_2_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_2 +} +set obj [get_report_configs -of_objects [get_runs impl_2] impl_2_phys_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.check_timing_verbose" -value "0" -objects $obj +set_property -name "options.delay_type" -value "" -objects $obj +set_property -name "options.setup" -value "0" -objects $obj +set_property -name "options.hold" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.nworst" -value "" -objects $obj +set_property -name "options.unique_pins" -value "0" -objects $obj +set_property -name "options.path_type" -value "" -objects $obj +set_property -name "options.slack_lesser_than" -value "" -objects $obj +set_property -name "options.report_unconstrained" -value "0" -objects $obj +set_property -name "options.warn_on_violation" -value "0" -objects $obj +set_property -name "options.significant_digits" -value "" -objects $obj +set_property -name "options.cell" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_2_route_report_drc_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_2] impl_2_route_report_drc_0] "" ] } { + create_report_config -report_name impl_2_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_2 +} +set obj [get_report_configs -of_objects [get_runs impl_2] impl_2_route_report_drc_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "options.upgrade_cw" -value "0" -objects $obj +set_property -name "options.checks" -value "" -objects $obj +set_property -name "options.ruledecks" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_2_route_report_methodology_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_2] impl_2_route_report_methodology_0] "" ] } { + create_report_config -report_name impl_2_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_2 +} +set obj [get_report_configs -of_objects [get_runs impl_2] impl_2_route_report_methodology_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "options.checks" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_2_route_report_power_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_2] impl_2_route_report_power_0] "" ] } { + create_report_config -report_name impl_2_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_2 +} +set obj [get_report_configs -of_objects [get_runs impl_2] impl_2_route_report_power_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "options.advisory" -value "0" -objects $obj +set_property -name "options.xpe" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_2_route_report_route_status_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_2] impl_2_route_report_route_status_0] "" ] } { + create_report_config -report_name impl_2_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_2 +} +set obj [get_report_configs -of_objects [get_runs impl_2] impl_2_route_report_route_status_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "options.of_objects" -value "" -objects $obj +set_property -name "options.route_type" -value "" -objects $obj +set_property -name "options.list_all_nets" -value "0" -objects $obj +set_property -name "options.show_all" -value "0" -objects $obj +set_property -name "options.has_routing" -value "0" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_2_route_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_2] impl_2_route_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_2_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_2 +} +set obj [get_report_configs -of_objects [get_runs impl_2] impl_2_route_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "options.check_timing_verbose" -value "0" -objects $obj +set_property -name "options.delay_type" -value "" -objects $obj +set_property -name "options.setup" -value "0" -objects $obj +set_property -name "options.hold" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.nworst" -value "" -objects $obj +set_property -name "options.unique_pins" -value "0" -objects $obj +set_property -name "options.path_type" -value "" -objects $obj +set_property -name "options.slack_lesser_than" -value "" -objects $obj +set_property -name "options.report_unconstrained" -value "0" -objects $obj +set_property -name "options.warn_on_violation" -value "0" -objects $obj +set_property -name "options.significant_digits" -value "" -objects $obj +set_property -name "options.cell" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_2_route_report_incremental_reuse_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_2] impl_2_route_report_incremental_reuse_0] "" ] } { + create_report_config -report_name impl_2_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_2 +} +set obj [get_report_configs -of_objects [get_runs impl_2] impl_2_route_report_incremental_reuse_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "options.cells" -value "" -objects $obj +set_property -name "options.hierarchical" -value "0" -objects $obj +set_property -name "options.hierarchical_depth" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_2_route_report_clock_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_2] impl_2_route_report_clock_utilization_0] "" ] } { + create_report_config -report_name impl_2_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_2 +} +set obj [get_report_configs -of_objects [get_runs impl_2] impl_2_route_report_clock_utilization_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "options.write_xdc" -value "0" -objects $obj +set_property -name "options.clock_roots_only" -value "0" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_2_route_report_bus_skew_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_2] impl_2_route_report_bus_skew_0] "" ] } { + create_report_config -report_name impl_2_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_2 +} +set obj [get_report_configs -of_objects [get_runs impl_2] impl_2_route_report_bus_skew_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "options.delay_type" -value "" -objects $obj +set_property -name "options.setup" -value "0" -objects $obj +set_property -name "options.hold" -value "0" -objects $obj +set_property -name "options.max_paths" -value "" -objects $obj +set_property -name "options.nworst" -value "" -objects $obj +set_property -name "options.unique_pins" -value "0" -objects $obj +set_property -name "options.path_type" -value "" -objects $obj +set_property -name "options.slack_lesser_than" -value "" -objects $obj +set_property -name "options.slack_greater_than" -value "" -objects $obj +set_property -name "options.significant_digits" -value "" -objects $obj +set_property -name "options.warn_on_violation" -value "1" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_2_post_route_phys_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_2] impl_2_post_route_phys_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_2_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_2 +} +set obj [get_report_configs -of_objects [get_runs impl_2] impl_2_post_route_phys_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "options.check_timing_verbose" -value "0" -objects $obj +set_property -name "options.delay_type" -value "" -objects $obj +set_property -name "options.setup" -value "0" -objects $obj +set_property -name "options.hold" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.nworst" -value "" -objects $obj +set_property -name "options.unique_pins" -value "0" -objects $obj +set_property -name "options.path_type" -value "" -objects $obj +set_property -name "options.slack_lesser_than" -value "" -objects $obj +set_property -name "options.report_unconstrained" -value "0" -objects $obj +set_property -name "options.warn_on_violation" -value "1" -objects $obj +set_property -name "options.significant_digits" -value "" -objects $obj +set_property -name "options.cell" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_2_post_route_phys_opt_report_bus_skew_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_2] impl_2_post_route_phys_opt_report_bus_skew_0] "" ] } { + create_report_config -report_name impl_2_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_2 +} +set obj [get_report_configs -of_objects [get_runs impl_2] impl_2_post_route_phys_opt_report_bus_skew_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "options.delay_type" -value "" -objects $obj +set_property -name "options.setup" -value "0" -objects $obj +set_property -name "options.hold" -value "0" -objects $obj +set_property -name "options.max_paths" -value "" -objects $obj +set_property -name "options.nworst" -value "" -objects $obj +set_property -name "options.unique_pins" -value "0" -objects $obj +set_property -name "options.path_type" -value "" -objects $obj +set_property -name "options.slack_lesser_than" -value "" -objects $obj +set_property -name "options.slack_greater_than" -value "" -objects $obj +set_property -name "options.significant_digits" -value "" -objects $obj +set_property -name "options.warn_on_violation" -value "1" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +set obj [get_runs impl_2] +set_property -name "constrset" -value "constrs_1" -objects $obj +set_property -name "description" -value "Default settings for Implementation." -objects $obj +set_property -name "flow" -value "Vivado Implementation 2019" -objects $obj +set_property -name "name" -value "impl_2" -objects $obj +set_property -name "needs_refresh" -value "0" -objects $obj +set_property -name "part" -value "xcvu3p-ffvc1517-2-e" -objects $obj +set_property -name "pr_configuration" -value "" -objects $obj +set_property -name "srcset" -value "sources_1" -objects $obj +set_property -name "auto_incremental_checkpoint" -value "0" -objects $obj +set_property -name "incremental_checkpoint" -value "" -objects $obj +set_property -name "incremental_checkpoint.more_options" -value "" -objects $obj +set_property -name "include_in_archive" -value "1" -objects $obj +set_property -name "gen_full_bitstream" -value "1" -objects $obj +set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj +set_property -name "steps.init_design.tcl.pre" -value "" -objects $obj +set_property -name "steps.init_design.tcl.post" -value "" -objects $obj +set_property -name "steps.opt_design.is_enabled" -value "1" -objects $obj +set_property -name "steps.opt_design.tcl.pre" -value "" -objects $obj +set_property -name "steps.opt_design.tcl.post" -value "" -objects $obj +set_property -name "steps.opt_design.args.verbose" -value "0" -objects $obj +set_property -name "steps.opt_design.args.directive" -value "Default" -objects $obj +set_property -name "steps.opt_design.args.more options" -value "" -objects $obj +set_property -name "steps.power_opt_design.is_enabled" -value "0" -objects $obj +set_property -name "steps.power_opt_design.tcl.pre" -value "" -objects $obj +set_property -name "steps.power_opt_design.tcl.post" -value "" -objects $obj +set_property -name "steps.power_opt_design.args.more options" -value "" -objects $obj +set_property -name "steps.place_design.tcl.pre" -value "" -objects $obj +set_property -name "steps.place_design.tcl.post" -value "" -objects $obj +set_property -name "steps.place_design.args.directive" -value "Default" -objects $obj +set_property -name "steps.place_design.args.more options" -value "" -objects $obj +set_property -name "steps.post_place_power_opt_design.is_enabled" -value "0" -objects $obj +set_property -name "steps.post_place_power_opt_design.tcl.pre" -value "" -objects $obj +set_property -name "steps.post_place_power_opt_design.tcl.post" -value "" -objects $obj +set_property -name "steps.post_place_power_opt_design.args.more options" -value "" -objects $obj +set_property -name "steps.phys_opt_design.is_enabled" -value "0" -objects $obj +set_property -name "steps.phys_opt_design.tcl.pre" -value "" -objects $obj +set_property -name "steps.phys_opt_design.tcl.post" -value "" -objects $obj +set_property -name "steps.phys_opt_design.args.directive" -value "Default" -objects $obj +set_property -name "steps.phys_opt_design.args.more options" -value "" -objects $obj +set_property -name "steps.route_design.tcl.pre" -value "" -objects $obj +set_property -name "steps.route_design.tcl.post" -value "" -objects $obj +set_property -name "steps.route_design.args.directive" -value "Default" -objects $obj +set_property -name "steps.route_design.args.more options" -value "" -objects $obj +set_property -name "steps.post_route_phys_opt_design.is_enabled" -value "0" -objects $obj +set_property -name "steps.post_route_phys_opt_design.tcl.pre" -value "" -objects $obj +set_property -name "steps.post_route_phys_opt_design.tcl.post" -value "" -objects $obj +set_property -name "steps.post_route_phys_opt_design.args.directive" -value "Default" -objects $obj +set_property -name "steps.post_route_phys_opt_design.args.more options" -value "" -objects $obj +set_property -name "steps.write_bitstream.tcl.pre" -value "" -objects $obj +set_property -name "steps.write_bitstream.tcl.post" -value "" -objects $obj +set_property -name "steps.write_bitstream.args.raw_bitfile" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.mask_file" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.no_binary_bitfile" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.bin_file" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.logic_location_file" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.more options" -value "" -objects $obj + +# set the current impl run +current_run -implementation [get_runs impl_2] + +puts "INFO: Project created:${_xil_proj_name_}" +# Create 'drc_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "drc_1" ] ] ""]} { +create_dashboard_gadget -name {drc_1} -type drc +} +set obj [get_dashboard_gadgets [ list "drc_1" ] ] +set_property -name "active_reports" -value "" -objects $obj +set_property -name "active_reports_invalid" -value "" -objects $obj +set_property -name "active_run" -value "0" -objects $obj +set_property -name "hide_unused_data" -value "1" -objects $obj +set_property -name "incl_new_reports" -value "0" -objects $obj +set_property -name "reports" -value "" -objects $obj +set_property -name "run.step" -value "route_design" -objects $obj +set_property -name "run.type" -value "implementation" -objects $obj +set_property -name "statistics.critical_warning" -value "1" -objects $obj +set_property -name "statistics.error" -value "1" -objects $obj +set_property -name "statistics.info" -value "1" -objects $obj +set_property -name "statistics.warning" -value "1" -objects $obj +set_property -name "view.orientation" -value "Horizontal" -objects $obj +set_property -name "view.type" -value "Graph" -objects $obj + +# Create 'methodology_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "methodology_1" ] ] ""]} { +create_dashboard_gadget -name {methodology_1} -type methodology +} +set obj [get_dashboard_gadgets [ list "methodology_1" ] ] +set_property -name "active_reports" -value "" -objects $obj +set_property -name "active_reports_invalid" -value "" -objects $obj +set_property -name "active_run" -value "0" -objects $obj +set_property -name "hide_unused_data" -value "1" -objects $obj +set_property -name "incl_new_reports" -value "0" -objects $obj +set_property -name "reports" -value "" -objects $obj +set_property -name "run.step" -value "route_design" -objects $obj +set_property -name "run.type" -value "implementation" -objects $obj +set_property -name "statistics.critical_warning" -value "1" -objects $obj +set_property -name "statistics.error" -value "1" -objects $obj +set_property -name "statistics.info" -value "1" -objects $obj +set_property -name "statistics.warning" -value "1" -objects $obj +set_property -name "view.orientation" -value "Horizontal" -objects $obj +set_property -name "view.type" -value "Graph" -objects $obj + +# Create 'power_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "power_1" ] ] ""]} { +create_dashboard_gadget -name {power_1} -type power +} +set obj [get_dashboard_gadgets [ list "power_1" ] ] +set_property -name "active_reports" -value "" -objects $obj +set_property -name "active_reports_invalid" -value "" -objects $obj +set_property -name "active_run" -value "0" -objects $obj +set_property -name "hide_unused_data" -value "1" -objects $obj +set_property -name "incl_new_reports" -value "0" -objects $obj +set_property -name "reports" -value "" -objects $obj +set_property -name "run.step" -value "route_design" -objects $obj +set_property -name "run.type" -value "implementation" -objects $obj +set_property -name "statistics.bram" -value "1" -objects $obj +set_property -name "statistics.clocks" -value "1" -objects $obj +set_property -name "statistics.dsp" -value "1" -objects $obj +set_property -name "statistics.gth" -value "1" -objects $obj +set_property -name "statistics.gtp" -value "1" -objects $obj +set_property -name "statistics.gtx" -value "1" -objects $obj +set_property -name "statistics.gtz" -value "1" -objects $obj +set_property -name "statistics.io" -value "1" -objects $obj +set_property -name "statistics.logic" -value "1" -objects $obj +set_property -name "statistics.mmcm" -value "1" -objects $obj +set_property -name "statistics.pcie" -value "1" -objects $obj +set_property -name "statistics.phaser" -value "1" -objects $obj +set_property -name "statistics.pll" -value "1" -objects $obj +set_property -name "statistics.pl_static" -value "1" -objects $obj +set_property -name "statistics.ps7" -value "1" -objects $obj +set_property -name "statistics.ps" -value "1" -objects $obj +set_property -name "statistics.ps_static" -value "1" -objects $obj +set_property -name "statistics.signals" -value "1" -objects $obj +set_property -name "statistics.total_power" -value "1" -objects $obj +set_property -name "statistics.transceiver" -value "1" -objects $obj +set_property -name "statistics.xadc" -value "1" -objects $obj +set_property -name "view.orientation" -value "Horizontal" -objects $obj +set_property -name "view.type" -value "Graph" -objects $obj + +# Create 'timing_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "timing_1" ] ] ""]} { +create_dashboard_gadget -name {timing_1} -type timing +} +set obj [get_dashboard_gadgets [ list "timing_1" ] ] +set_property -name "active_reports" -value "" -objects $obj +set_property -name "active_reports_invalid" -value "" -objects $obj +set_property -name "active_run" -value "0" -objects $obj +set_property -name "hide_unused_data" -value "1" -objects $obj +set_property -name "incl_new_reports" -value "0" -objects $obj +set_property -name "reports" -value "" -objects $obj +set_property -name "run.step" -value "route_design" -objects $obj +set_property -name "run.type" -value "implementation" -objects $obj +set_property -name "statistics.ths" -value "1" -objects $obj +set_property -name "statistics.tns" -value "1" -objects $obj +set_property -name "statistics.tpws" -value "1" -objects $obj +set_property -name "statistics.whs" -value "1" -objects $obj +set_property -name "statistics.wns" -value "1" -objects $obj +set_property -name "view.orientation" -value "Horizontal" -objects $obj +set_property -name "view.type" -value "Table" -objects $obj + +# Create 'utilization_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "utilization_1" ] ] ""]} { +create_dashboard_gadget -name {utilization_1} -type utilization +} +set obj [get_dashboard_gadgets [ list "utilization_1" ] ] +set_property -name "active_reports" -value "" -objects $obj +set_property -name "active_reports_invalid" -value "" -objects $obj +set_property -name "active_run" -value "0" -objects $obj +set_property -name "hide_unused_data" -value "1" -objects $obj +set_property -name "incl_new_reports" -value "0" -objects $obj +set_property -name "reports" -value "" -objects $obj +set_property -name "run.step" -value "synth_design" -objects $obj +set_property -name "run.type" -value "synthesis" -objects $obj +set_property -name "statistics.bram" -value "1" -objects $obj +set_property -name "statistics.bufg" -value "1" -objects $obj +set_property -name "statistics.dsp" -value "1" -objects $obj +set_property -name "statistics.ff" -value "1" -objects $obj +set_property -name "statistics.gt" -value "1" -objects $obj +set_property -name "statistics.io" -value "1" -objects $obj +set_property -name "statistics.lut" -value "1" -objects $obj +set_property -name "statistics.lutram" -value "1" -objects $obj +set_property -name "statistics.mmcm" -value "1" -objects $obj +set_property -name "statistics.pcie" -value "1" -objects $obj +set_property -name "statistics.pll" -value "1" -objects $obj +set_property -name "statistics.uram" -value "1" -objects $obj +set_property -name "view.orientation" -value "Horizontal" -objects $obj +set_property -name "view.type" -value "Graph" -objects $obj + +# Create 'utilization_2' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "utilization_2" ] ] ""]} { +create_dashboard_gadget -name {utilization_2} -type utilization +} +set obj [get_dashboard_gadgets [ list "utilization_2" ] ] +set_property -name "active_reports" -value "" -objects $obj +set_property -name "active_reports_invalid" -value "" -objects $obj +set_property -name "active_run" -value "0" -objects $obj +set_property -name "hide_unused_data" -value "1" -objects $obj +set_property -name "incl_new_reports" -value "0" -objects $obj +set_property -name "reports" -value "" -objects $obj +set_property -name "run.step" -value "place_design" -objects $obj +set_property -name "run.type" -value "implementation" -objects $obj +set_property -name "statistics.bram" -value "1" -objects $obj +set_property -name "statistics.bufg" -value "1" -objects $obj +set_property -name "statistics.dsp" -value "1" -objects $obj +set_property -name "statistics.ff" -value "1" -objects $obj +set_property -name "statistics.gt" -value "1" -objects $obj +set_property -name "statistics.io" -value "1" -objects $obj +set_property -name "statistics.lut" -value "1" -objects $obj +set_property -name "statistics.lutram" -value "1" -objects $obj +set_property -name "statistics.mmcm" -value "1" -objects $obj +set_property -name "statistics.pcie" -value "1" -objects $obj +set_property -name "statistics.pll" -value "1" -objects $obj +set_property -name "statistics.uram" -value "1" -objects $obj +set_property -name "view.orientation" -value "Horizontal" -objects $obj +set_property -name "view.type" -value "Graph" -objects $obj + +move_dashboard_gadget -name {utilization_1} -row 0 -col 0 +move_dashboard_gadget -name {power_1} -row 1 -col 0 +move_dashboard_gadget -name {drc_1} -row 2 -col 0 +move_dashboard_gadget -name {timing_1} -row 0 -col 1 +move_dashboard_gadget -name {utilization_2} -row 1 -col 1 +move_dashboard_gadget -name {methodology_1} -row 2 -col 1 diff --git a/rel/build/a2x/fixup_a2x_bd.tcl b/rel/build/a2x/fixup_a2x_bd.tcl new file mode 100644 index 0000000..0b67086 --- /dev/null +++ b/rel/build/a2x/fixup_a2x_bd.tcl @@ -0,0 +1,50 @@ +open_bd_design "[get_property DIRECTORY [current_project]]/proj_a2x_axi.srcs/sources_1/bd/a2x_axi_bd/a2x_axi_bd.bd" + +set_property SCREENSIZE {1 1} [get_bd_cells /pain] +set_property location {5 1506 2372} [get_bd_cells pain] +set_property SCREENSIZE {1 1} [get_bd_cells /thold_0] +set_property SCREENSIZE {1 1} [get_bd_cells /xlconstant_0] +set_property location {6 2778 2069} [get_bd_cells xlconstant_0] +set_property SCREENSIZE {1 1} [get_bd_cells /xlconstant_1] +set_property location {6 2734 2210} [get_bd_cells xlconstant_1] + +# so xil actually connects as bus +set_property SCREENSIZE {1 1} [get_bd_cells /mchk_rv] +set_property location {6 2767 2847} [get_bd_cells mchk_rv] +set_property SCREENSIZE {1 1} [get_bd_cells /rcov_rv] +set_property location {6 2777 2748} [get_bd_cells rcov_rv] +set_property SCREENSIZE {1 1} [get_bd_cells /checkstop_rv] +set_property location {7 2850 2630} [get_bd_cells rcov_rv] +set_property SCREENSIZE {1 1} [get_bd_cells /scomdata_rv] +set_property location {4 1355 2564} [get_bd_cells scomdata_rv] +set_property SCREENSIZE {1 1} [get_bd_cells /thread_running_rv] +set_property location {5 2152 2682} [get_bd_cells thread_running_rv] +set_property SCREENSIZE {1 1} [get_bd_cells /axi_reg00_rv] +set_property location {7 3176 2490} [get_bd_cells axi_reg00_rv] +set_property SCREENSIZE {1 1} [get_bd_cells /reverserator_4_0] +set_property location {7 2156 2797} [get_bd_cells reverserator_4_0] + + + +set_property SCREENSIZE {600 600} [get_bd_cells /a2x_axi_1] +set_property location {5 2000 1000} [get_bd_cells /a2x_axi_1] +set_property location {4 1306 1980} [get_bd_cells a2x_dbug] + +set_property location {4.5 1482 792} [get_bd_cells jtag_axi_0] + +set_property location {4 1259 2326} [get_bd_cells vio_dbug] ;# no orientation, highlight, etc. +set_property location {5 1957 2377} [get_bd_cells vio_ctrl] +set_property location {6 2704 2401} [get_bd_cells vio_terror] +set_property location {7 3253 2629} [get_bd_cells vio_reg] + +set_property location {10.5 4307 861} [get_bd_cells blk_mem_gen_1] +set_property location {11 4297 974} [get_bd_cells blk_mem_gen_2] + +set_property location {6 2034 684} [get_bd_cells axi_smc] + +set_property location {7 3129 422} [get_bd_cells ila_axi] +set_property location {9 3542 548} [get_bd_cells ila_axi_protocol] +set_property location {7 3173 580} [get_bd_cells axi_protocol_checker] + +save_bd_design + diff --git a/rel/build/a2x/ila_axi.tcl b/rel/build/a2x/ila_axi.tcl new file mode 100644 index 0000000..5940518 --- /dev/null +++ b/rel/build/a2x/ila_axi.tcl @@ -0,0 +1,58 @@ +set_property mark_debug true [get_nets [list a2x_axi_bd_i/a2x_reset_0/reset]] + +set_property mark_debug true [get_nets [list {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[13]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[17]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[3]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[25]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[23]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[21]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[19]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[15]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[1]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[5]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[8]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[9]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[41]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[39]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[37]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[35]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[33]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[31]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[29]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[47]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[45]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[43]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[59]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[61]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[63]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[27]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[49]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[51]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[53]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[55]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[57]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[11]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[12]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[0]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[24]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[22]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[20]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[18]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[16]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[14]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[2]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[4]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[6]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[7]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[10]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[40]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[38]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[36]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[34]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[32]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[30]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[28]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[26]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[54]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[56]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[50]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[52]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[48]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[46]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[44]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[42]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[62]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[58]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[60]}]] + +set_property mark_debug true [get_nets [list {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[31]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[3]} a2x_axi_bd_i/a2x_axi_1/m00_axi_bready a2x_axi_bd_i/a2x_axi_1/m00_axi_wlast {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[9]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[11]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[15]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[19]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[23]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[27]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[2]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[10]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[6]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[14]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[18]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[26]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[22]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[30]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[9]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_bresp[1]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[3]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[15]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[11]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[23]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[19]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[31]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[27]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[1]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[8]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[17]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[25]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[29]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[21]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[13]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[5]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[24]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[16]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[0]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[4]} a2x_axi_bd_i/a2x_axi_1/m00_axi_awready a2x_axi_bd_i/a2x_axi_1/m00_axi_wready a2x_axi_bd_i/a2x_axi_1/m00_axi_rlast {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[7]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[12]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[20]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[28]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[3]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[11]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[9]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[19]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[15]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[27]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[23]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[31]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[0]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[4]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[7]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[16]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[12]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[24]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[20]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[28]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[2]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[10]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[18]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[26]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[30]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[22]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[14]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[6]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[4]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[17]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[13]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[1]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[5]} a2x_axi_bd_i/a2x_axi_1/m00_axi_arready a2x_axi_bd_i/a2x_axi_1/m00_axi_rready a2x_axi_bd_i/a2x_axi_1/m00_axi_wvalid a2x_axi_bd_i/a2x_axi_1/m00_axi_bvalid {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[8]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[21]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[29]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[25]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[0]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[12]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[7]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[20]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[16]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[28]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[24]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[1]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[8]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[5]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[17]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[13]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[25]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[21]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[29]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[3]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[11]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[19]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[27]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[31]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[23]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[15]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[9]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[26]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[18]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[2]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[6]} a2x_axi_bd_i/a2x_axi_1/m00_axi_rvalid a2x_axi_bd_i/a2x_axi_1/m00_axi_arvalid a2x_axi_bd_i/a2x_axi_1/m00_axi_awvalid {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[14]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[10]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[22]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[30]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[5]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[1]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[13]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[8]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[21]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[17]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[29]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[25]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[2]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_bresp[0]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[10]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[6]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[18]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[14]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[26]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[22]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[30]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[0]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[4]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[12]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[20]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[28]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[24]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[16]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[7]}]] + +set_property mark_debug true [get_nets [list \ + {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[0]} \ + {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[1]} \ + {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[2]} \ + {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[3]} \ + {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[4]} \ + {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[5]} \ + {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[6]} \ + {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[7]} \ + {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[8]} \ + {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[9]} \ + {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[10]} \ + {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[11]} \ + {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[12]} \ + {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[13]} \ + {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[14]} \ + {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[15]} \ + {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[16]} \ + {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[17]} \ + {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[18]} \ + {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[19]} \ + {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[20]} \ + {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[21]} \ + {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[22]} \ + {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[23]} \ + {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[24]} \ + {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[25]} \ + {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[26]} \ + {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[27]} \ + {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[28]} \ + {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[29]} \ + {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[30]} \ + {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[31]} \ +]] + +set_property mark_debug true [get_nets [list {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[19]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[3]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[0]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[26]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[27]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[24]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[25]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[22]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[23]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[20]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[21]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[18]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[16]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[17]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[14]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[15]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[12]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[30]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[31]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[28]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[29]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[13]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[1]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[2]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[4]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[5]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[6]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[7]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[8]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[9]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[10]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[11]}]] +set_property mark_debug true [get_nets [list {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[19]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[3]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[0]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[26]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[27]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[24]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[25]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[22]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[23]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[20]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[21]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[18]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[16]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[17]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[14]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[15]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[12]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[30]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[31]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[28]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[29]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[13]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[1]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[2]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[4]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[5]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[6]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[7]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[8]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[9]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[10]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[11]}]] +set_property mark_debug true [get_nets [list {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[21]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[18]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[19]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[20]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[22]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[23]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[24]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[25]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[26]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[27]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[28]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[29]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[30]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[31]}]] + +set_property MARK_DEBUG 1 [get_nets {a2x_axi_bd_i/ila_axi_protocol/TRIG_OUT_trig[0]}] +set_property MARK_DEBUG 1 [get_nets {a2x_axi_bd_i/ila_axi_protocol/TRIG_OUT_ack[0]}] + +set p [create_debug_port u_ila_0 probe] +set_property port_width 1 $p +set_property PROBE_TYPE DATA_AND_TRIGGER $p +connect_debug_port $p [get_nets [list {a2x_axi_bd_i/ila_axi_protocol/TRIG_OUT_trig[0]} ]] + +set p [create_debug_port u_ila_0 probe] +set_property port_width 1 $p +set_property PROBE_TYPE DATA_AND_TRIGGER $p +connect_debug_port $p [get_nets [list {a2x_axi_bd_i/ila_axi_protocol/TRIG_OUT_ack[0]} ]] + diff --git a/rel/build/a2x/readme.md b/rel/build/a2x/readme.md new file mode 100644 index 0000000..bba0b9d --- /dev/null +++ b/rel/build/a2x/readme.md @@ -0,0 +1,31 @@ +# create/build project + +``` +$VIVADO -mode tcl -source create_a2x_project.tcl + +$VIVADO proj/proj_a2x_axi.xpr + +source ./fixup_a2x_bd.tcl + +>run synthesis (synth_2) +>open synthesized design + +source ./ila_axi.tcl +>set up debug +> all clk +> 8192/3 + +source ./a2x_impl_step.tcl +``` + +``` +a2x_axi_routed_v0.dcp +a2x_axi_synth_v0.dcp +a2x_axi_v0.bin +a2x_axi_v0.bit +a2x_axi_v0.ltx +a2x_axi_v0_primary.bin +a2x_axi_v0_primary.prm +a2x_axi_v0_secondary.bin +a2x_axi_v0_secondary.prm +``` diff --git a/rel/build/a2x/xdc b/rel/build/a2x/xdc new file mode 120000 index 0000000..d0099a4 --- /dev/null +++ b/rel/build/a2x/xdc @@ -0,0 +1 @@ +../xdc \ No newline at end of file diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/component.xml b/rel/build/ip_user/a2x_axi/a2x_axi/component.xml new file mode 100644 index 0000000..dae731d --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/component.xml @@ -0,0 +1,5113 @@ + + + user.org + user + a2x_axi + 1.0 + + + m00_axi + + + + + + + + + AWID + + + m00_axi_awid + + + + + AWADDR + + + m00_axi_awaddr + + + + + AWLEN + + + m00_axi_awlen + + + + + AWSIZE + + + m00_axi_awsize + + + + + AWBURST + + + m00_axi_awburst + + + + + AWLOCK + + + m00_axi_awlock + + + + + AWCACHE + + + m00_axi_awcache + + + + + AWPROT + + + m00_axi_awprot + + + + + AWQOS + + + m00_axi_awqos + + + + + AWUSER + + + m00_axi_awuser + + + + + AWVALID + + + m00_axi_awvalid + + + + + AWREADY + + + m00_axi_awready + + + + + WDATA + + + m00_axi_wdata + + + + + WSTRB + + + m00_axi_wstrb + + + + + WLAST + + + m00_axi_wlast + + + + + WUSER + + + m00_axi_wuser + + + + + WVALID + + + m00_axi_wvalid + + + + + WREADY + + + m00_axi_wready + + + + + BID + + + m00_axi_bid + + + + + BRESP + + + m00_axi_bresp + + + + + BUSER + + + m00_axi_buser + + + + + BVALID + + + m00_axi_bvalid + + + + + BREADY + + + m00_axi_bready + + + + + ARID + + + m00_axi_arid + + + + + ARADDR + + + m00_axi_araddr + + + + + ARLEN + + + m00_axi_arlen + + + + + ARSIZE + + + m00_axi_arsize + + + + + ARBURST + + + m00_axi_arburst + + + + + ARLOCK + + + m00_axi_arlock + + + + + ARCACHE + + + m00_axi_arcache + + + + + ARPROT + + + m00_axi_arprot + + + + + ARQOS + + + m00_axi_arqos + + + + + ARUSER + + + m00_axi_aruser + + + + + ARVALID + + + m00_axi_arvalid + + + + + ARREADY + + + m00_axi_arready + + + + + RID + + + m00_axi_rid + + + + + RDATA + + + m00_axi_rdata + + + + + RRESP + + + m00_axi_rresp + + + + + RLAST + + + m00_axi_rlast + + + + + RUSER + + + m00_axi_ruser + + + + + RVALID + + + m00_axi_rvalid + + + + + RREADY + + + m00_axi_rready + + + + + + reset_n + + + + + + + RST + + + reset_n + + + + + + clk + + + + + + + CLK + + + clk + + + + + + ASSOCIATED_BUSIF + m00_axi + + + + + crit_interrupt + + + + + + + INTERRUPT + + + crit_interrupt + + + + + + SENSITIVITY + LEVEL_HIGH + + + + + ext_interrupt + + + + + + + INTERRUPT + + + ext_interrupt + + + + + + SENSITIVITY + LEVEL_HIGH + + + + + perf_interrupt + + + + + + + INTERRUPT + + + perf_interrupt + + + + + + SENSITIVITY + LEVEL_HIGH + + + + + + + m00_axi + 4294967296 + 32 + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + VHDL-2008 + a2x_axi + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 8ab27bcb + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + VHDL-2008 + a2x_axi + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 8ab27bcb + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + acba2114 + + + + + + + clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + clk2x + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + reset_n + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + thold + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + core_id + + in + + 0 + 7 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + thread_stop + + in + + 0 + 3 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + thread_running + + out + + 0 + 3 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + ext_mchk + + in + + 0 + 3 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + ext_checkstop + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + debug_stop + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + mchk + + out + + 0 + 3 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + recov_err + + out + + 0 + 2 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + checkstop + + out + + 0 + 2 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + a2l2_axi_err + + out + + 0 + 3 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + crit_interrupt + + in + + 0 + 3 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + ext_interrupt + + in + + 0 + 3 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + perf_interrupt + + in + + 0 + 3 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + tb_update_enable + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + tb_update_pulse + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + scom_sat_id + + in + + 0 + 3 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + scom_dch_in + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + scom_cch_in + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + scom_dch_out + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + scom_cch_out + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + flh2l2_gate + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + hang_pulse + + in + + 0 + 3 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axi_awid + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axi_awaddr + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axi_awlen + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axi_awsize + + out + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axi_awburst + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axi_awlock + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axi_awcache + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axi_awprot + + out + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axi_awqos + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axi_awuser + + out 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+ C_M00_AXI_ARUSER_WIDTH + C M00 Axi Aruser Width + 4 + + + C_M00_AXI_WUSER_WIDTH + C M00 Axi Wuser Width + 4 + + + C_M00_AXI_RUSER_WIDTH + C M00 Axi Ruser Width + 4 + + + C_M00_AXI_BUSER_WIDTH + C M00 Axi Buser Width + 4 + + + Component_Name + a2x_axi_v1_0 + + + + + + virtex7 + qvirtex7 + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + kintexu + + + /UserIP + + a2x_axi_v1_0 + package_project + 2 + 2020-06-26T14:25:23Z + + + 2019.1.3 + + + + + + + + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_debug_mux16.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_debug_mux16.vhdl new file mode 100644 index 0000000..f850c0c --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_debug_mux16.vhdl @@ -0,0 +1,154 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee; use ieee.std_logic_1164.all; +library support; use support.power_logic_pkg.all; + +entity c_debug_mux16 is +generic( DBG_WIDTH : integer := 88 +); +port( + vd : inout power_logic; + gd : inout power_logic; + + select_bits : in std_ulogic_vector(0 to 15); + trace_data_in : in std_ulogic_vector(0 to DBG_WIDTH-1); + trigger_data_in : in std_ulogic_vector(0 to 11); + + dbg_group0 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group1 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group2 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group3 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group4 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group5 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group6 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group7 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group8 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group9 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group10 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group11 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group12 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group13 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group14 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group15 : in std_ulogic_vector(0 to DBG_WIDTH-1); + + trg_group0 : in std_ulogic_vector(0 to 11); + trg_group1 : in std_ulogic_vector(0 to 11); + trg_group2 : in std_ulogic_vector(0 to 11); + trg_group3 : in std_ulogic_vector(0 to 11); + + trace_data_out : out std_ulogic_vector(0 to DBG_WIDTH-1); + trigger_data_out : out std_ulogic_vector(0 to 11) +); +-- synopsys translate_off + +-- synopsys translate_on + +end c_debug_mux16; + + +architecture c_debug_mux16 of c_debug_mux16 is + +constant DBG_1FOURTH : positive := DBG_WIDTH/4; +constant DBG_2FOURTH : positive := DBG_WIDTH/2; +constant DBG_3FOURTH : positive := 3*DBG_WIDTH/4; + +signal debug_grp_selected : std_ulogic_vector(0 to DBG_WIDTH-1); +signal debug_grp_rotated : std_ulogic_vector(0 to DBG_WIDTH-1); +signal trigg_grp_selected : std_ulogic_vector(0 to 11); +signal trigg_grp_rotated : std_ulogic_vector(0 to 11); + +signal unused : std_ulogic; + +begin + + unused <= select_bits(4); + + with select_bits(0 to 3) select debug_grp_selected <= + dbg_group0 when "0000", + dbg_group1 when "0001", + dbg_group2 when "0010", + dbg_group3 when "0011", + dbg_group4 when "0100", + dbg_group5 when "0101", + dbg_group6 when "0110", + dbg_group7 when "0111", + dbg_group8 when "1000", + dbg_group9 when "1001", + dbg_group10 when "1010", + dbg_group11 when "1011", + dbg_group12 when "1100", + dbg_group13 when "1101", + dbg_group14 when "1110", + dbg_group15 when others; + + with select_bits(5 to 6) select + debug_grp_rotated <= debug_grp_selected(DBG_1FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_1FOURTH-1) when "11", + debug_grp_selected(DBG_2FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_2FOURTH-1) when "10", + debug_grp_selected(DBG_3FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_3FOURTH-1) when "01", + debug_grp_selected(0 to DBG_WIDTH-1) when others; + + + with select_bits(7) select trace_data_out(0 to DBG_1FOURTH-1) <= + trace_data_in(0 to DBG_1FOURTH-1) when '0', + debug_grp_rotated(0 to DBG_1FOURTH-1) when others; + + with select_bits(8) select trace_data_out(DBG_1FOURTH to DBG_2FOURTH-1) <= + trace_data_in(DBG_1FOURTH to DBG_2FOURTH-1) when '0', + debug_grp_rotated(DBG_1FOURTH to DBG_2FOURTH-1) when others; + + with select_bits(9) select trace_data_out(DBG_2FOURTH to DBG_3FOURTH-1) <= + trace_data_in(DBG_2FOURTH to DBG_3FOURTH-1) when '0', + debug_grp_rotated(DBG_2FOURTH to DBG_3FOURTH-1) when others; + + with select_bits(10) select trace_data_out(DBG_3FOURTH to DBG_WIDTH-1) <= + trace_data_in(DBG_3FOURTH to DBG_WIDTH-1) when '0', + debug_grp_rotated(DBG_3FOURTH to DBG_WIDTH-1) when others; + + + + with select_bits(11 to 12) select trigg_grp_selected <= + trg_group0 when "00", + trg_group1 when "01", + trg_group2 when "10", + trg_group3 when others; + + with select_bits(13) select + trigg_grp_rotated <= trigg_grp_selected(6 to 11) & trigg_grp_selected(0 to 5) when '1', + trigg_grp_selected(0 to 11) when others; + + with select_bits(14) select trigger_data_out(0 to 5) <= + trigger_data_in(0 to 5) when '0', + trigg_grp_rotated(0 to 5) when others; + + with select_bits(15) select trigger_data_out(6 to 11) <= + trigger_data_in(6 to 11) when '0', + trigg_grp_rotated(6 to 11) when others; + + +end c_debug_mux16; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_debug_mux32.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_debug_mux32.vhdl new file mode 100644 index 0000000..a52c244 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_debug_mux32.vhdl @@ -0,0 +1,184 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee; use ieee.std_logic_1164.all; +library support; +use support.power_logic_pkg.all; + +entity c_debug_mux32 is +generic( DBG_WIDTH : integer := 88 +); +port( + vd : inout power_logic; + gd : inout power_logic; + + select_bits : in std_ulogic_vector(0 to 15); + trace_data_in : in std_ulogic_vector(0 to DBG_WIDTH-1); + trigger_data_in : in std_ulogic_vector(0 to 11); + + dbg_group0 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group1 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group2 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group3 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group4 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group5 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group6 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group7 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group8 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group9 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group10 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group11 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group12 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group13 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group14 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group15 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group16 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group17 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group18 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group19 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group20 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group21 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group22 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group23 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group24 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group25 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group26 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group27 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group28 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group29 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group30 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group31 : in std_ulogic_vector(0 to DBG_WIDTH-1); + + trg_group0 : in std_ulogic_vector(0 to 11); + trg_group1 : in std_ulogic_vector(0 to 11); + trg_group2 : in std_ulogic_vector(0 to 11); + trg_group3 : in std_ulogic_vector(0 to 11); + + trace_data_out : out std_ulogic_vector(0 to DBG_WIDTH-1); + trigger_data_out : out std_ulogic_vector(0 to 11) +); +-- synopsys translate_off + +-- synopsys translate_on + +end c_debug_mux32; + + +architecture c_debug_mux32 of c_debug_mux32 is + +constant DBG_1FOURTH : positive := DBG_WIDTH/4; +constant DBG_2FOURTH : positive := DBG_WIDTH/2; +constant DBG_3FOURTH : positive := 3*DBG_WIDTH/4; + +signal debug_grp_selected : std_ulogic_vector(0 to DBG_WIDTH-1); +signal debug_grp_rotated : std_ulogic_vector(0 to DBG_WIDTH-1); +signal trigg_grp_selected : std_ulogic_vector(0 to 11); +signal trigg_grp_rotated : std_ulogic_vector(0 to 11); + +begin + + + with select_bits(0 to 4) select debug_grp_selected <= + dbg_group0 when "00000", + dbg_group1 when "00001", + dbg_group2 when "00010", + dbg_group3 when "00011", + dbg_group4 when "00100", + dbg_group5 when "00101", + dbg_group6 when "00110", + dbg_group7 when "00111", + dbg_group8 when "01000", + dbg_group9 when "01001", + dbg_group10 when "01010", + dbg_group11 when "01011", + dbg_group12 when "01100", + dbg_group13 when "01101", + dbg_group14 when "01110", + dbg_group15 when "01111", + dbg_group16 when "10000", + dbg_group17 when "10001", + dbg_group18 when "10010", + dbg_group19 when "10011", + dbg_group20 when "10100", + dbg_group21 when "10101", + dbg_group22 when "10110", + dbg_group23 when "10111", + dbg_group24 when "11000", + dbg_group25 when "11001", + dbg_group26 when "11010", + dbg_group27 when "11011", + dbg_group28 when "11100", + dbg_group29 when "11101", + dbg_group30 when "11110", + dbg_group31 when others; + + with select_bits(5 to 6) select + debug_grp_rotated <= debug_grp_selected(DBG_1FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_1FOURTH-1) when "11", + debug_grp_selected(DBG_2FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_2FOURTH-1) when "10", + debug_grp_selected(DBG_3FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_3FOURTH-1) when "01", + debug_grp_selected(0 to DBG_WIDTH-1) when others; + + + with select_bits(7) select trace_data_out(0 to DBG_1FOURTH-1) <= + trace_data_in(0 to DBG_1FOURTH-1) when '0', + debug_grp_rotated(0 to DBG_1FOURTH-1) when others; + + with select_bits(8) select trace_data_out(DBG_1FOURTH to DBG_2FOURTH-1) <= + trace_data_in(DBG_1FOURTH to DBG_2FOURTH-1) when '0', + debug_grp_rotated(DBG_1FOURTH to DBG_2FOURTH-1) when others; + + with select_bits(9) select trace_data_out(DBG_2FOURTH to DBG_3FOURTH-1) <= + trace_data_in(DBG_2FOURTH to DBG_3FOURTH-1) when '0', + debug_grp_rotated(DBG_2FOURTH to DBG_3FOURTH-1) when others; + + with select_bits(10) select trace_data_out(DBG_3FOURTH to DBG_WIDTH-1) <= + trace_data_in(DBG_3FOURTH to DBG_WIDTH-1) when '0', + debug_grp_rotated(DBG_3FOURTH to DBG_WIDTH-1) when others; + + + + with select_bits(11 to 12) select trigg_grp_selected <= + trg_group0 when "00", + trg_group1 when "01", + trg_group2 when "10", + trg_group3 when others; + + with select_bits(13) select + trigg_grp_rotated <= trigg_grp_selected(6 to 11) & trigg_grp_selected(0 to 5) when '1', + trigg_grp_selected(0 to 11) when others; + + with select_bits(14) select trigger_data_out(0 to 5) <= + trigger_data_in(0 to 5) when '0', + trigg_grp_rotated(0 to 5) when others; + + with select_bits(15) select trigger_data_out(6 to 11) <= + trigger_data_in(6 to 11) when '0', + trigg_grp_rotated(6 to 11) when others; + + +end c_debug_mux32; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_debug_mux4.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_debug_mux4.vhdl new file mode 100644 index 0000000..9ec1c8b --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_debug_mux4.vhdl @@ -0,0 +1,131 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee; use ieee.std_logic_1164.all; +library support; +use support.power_logic_pkg.all; + +entity c_debug_mux4 is +generic( DBG_WIDTH : integer := 88 +); +port( + vd : inout power_logic; + gd : inout power_logic; + + select_bits : in std_ulogic_vector(0 to 15); + trace_data_in : in std_ulogic_vector(0 to DBG_WIDTH-1); + trigger_data_in : in std_ulogic_vector(0 to 11); + + dbg_group0 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group1 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group2 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group3 : in std_ulogic_vector(0 to DBG_WIDTH-1); + + trg_group0 : in std_ulogic_vector(0 to 11); + trg_group1 : in std_ulogic_vector(0 to 11); + trg_group2 : in std_ulogic_vector(0 to 11); + trg_group3 : in std_ulogic_vector(0 to 11); + + trace_data_out : out std_ulogic_vector(0 to DBG_WIDTH-1); + trigger_data_out : out std_ulogic_vector(0 to 11) +); +-- synopsys translate_off + +-- synopsys translate_on + +end c_debug_mux4; + + +architecture c_debug_mux4 of c_debug_mux4 is + +constant DBG_1FOURTH : positive := DBG_WIDTH/4; +constant DBG_2FOURTH : positive := DBG_WIDTH/2; +constant DBG_3FOURTH : positive := 3*DBG_WIDTH/4; + +signal debug_grp_selected : std_ulogic_vector(0 to DBG_WIDTH-1); +signal debug_grp_rotated : std_ulogic_vector(0 to DBG_WIDTH-1); +signal trigg_grp_selected : std_ulogic_vector(0 to 11); +signal trigg_grp_rotated : std_ulogic_vector(0 to 11); + +signal unused : std_ulogic; + +begin + + unused <= select_bits(2) or select_bits(3) or select_bits(4); + + with select_bits(0 to 1) select debug_grp_selected <= + dbg_group0 when "00", + dbg_group1 when "01", + dbg_group2 when "10", + dbg_group3 when others; + + with select_bits(5 to 6) select + debug_grp_rotated <= debug_grp_selected(DBG_1FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_1FOURTH-1) when "11", + debug_grp_selected(DBG_2FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_2FOURTH-1) when "10", + debug_grp_selected(DBG_3FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_3FOURTH-1) when "01", + debug_grp_selected(0 to DBG_WIDTH-1) when others; + + + with select_bits(7) select trace_data_out(0 to DBG_1FOURTH-1) <= + trace_data_in(0 to DBG_1FOURTH-1) when '0', + debug_grp_rotated(0 to DBG_1FOURTH-1) when others; + + with select_bits(8) select trace_data_out(DBG_1FOURTH to DBG_2FOURTH-1) <= + trace_data_in(DBG_1FOURTH to DBG_2FOURTH-1) when '0', + debug_grp_rotated(DBG_1FOURTH to DBG_2FOURTH-1) when others; + + with select_bits(9) select trace_data_out(DBG_2FOURTH to DBG_3FOURTH-1) <= + trace_data_in(DBG_2FOURTH to DBG_3FOURTH-1) when '0', + debug_grp_rotated(DBG_2FOURTH to DBG_3FOURTH-1) when others; + + with select_bits(10) select trace_data_out(DBG_3FOURTH to DBG_WIDTH-1) <= + trace_data_in(DBG_3FOURTH to DBG_WIDTH-1) when '0', + debug_grp_rotated(DBG_3FOURTH to DBG_WIDTH-1) when others; + + + + with select_bits(11 to 12) select trigg_grp_selected <= + trg_group0 when "00", + trg_group1 when "01", + trg_group2 when "10", + trg_group3 when others; + + with select_bits(13) select + trigg_grp_rotated <= trigg_grp_selected(6 to 11) & trigg_grp_selected(0 to 5) when '1', + trigg_grp_selected(0 to 11) when others; + + with select_bits(14) select trigger_data_out(0 to 5) <= + trigger_data_in(0 to 5) when '0', + trigg_grp_rotated(0 to 5) when others; + + with select_bits(15) select trigger_data_out(6 to 11) <= + trigger_data_in(6 to 11) when '0', + trigg_grp_rotated(6 to 11) when others; + + +end c_debug_mux4; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_debug_mux8.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_debug_mux8.vhdl new file mode 100644 index 0000000..cdbc4e5 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_debug_mux8.vhdl @@ -0,0 +1,139 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee; use ieee.std_logic_1164.all; +library support; +use support.power_logic_pkg.all; + +entity c_debug_mux8 is +generic( DBG_WIDTH : integer := 88 +); +port( + vd : inout power_logic; + gd : inout power_logic; + + select_bits : in std_ulogic_vector(0 to 15); + trace_data_in : in std_ulogic_vector(0 to DBG_WIDTH-1); + trigger_data_in : in std_ulogic_vector(0 to 11); + + dbg_group0 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group1 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group2 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group3 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group4 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group5 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group6 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group7 : in std_ulogic_vector(0 to DBG_WIDTH-1); + + trg_group0 : in std_ulogic_vector(0 to 11); + trg_group1 : in std_ulogic_vector(0 to 11); + trg_group2 : in std_ulogic_vector(0 to 11); + trg_group3 : in std_ulogic_vector(0 to 11); + + trace_data_out : out std_ulogic_vector(0 to DBG_WIDTH-1); + trigger_data_out : out std_ulogic_vector(0 to 11) +); +-- synopsys translate_off + +-- synopsys translate_on + +end c_debug_mux8; + + +architecture c_debug_mux8 of c_debug_mux8 is + +constant DBG_1FOURTH : positive := DBG_WIDTH/4; +constant DBG_2FOURTH : positive := DBG_WIDTH/2; +constant DBG_3FOURTH : positive := 3*DBG_WIDTH/4; + +signal debug_grp_selected : std_ulogic_vector(0 to DBG_WIDTH-1); +signal debug_grp_rotated : std_ulogic_vector(0 to DBG_WIDTH-1); +signal trigg_grp_selected : std_ulogic_vector(0 to 11); +signal trigg_grp_rotated : std_ulogic_vector(0 to 11); + +signal unused : std_ulogic; + +begin + + unused <= select_bits(3) or select_bits(4); + + with select_bits(0 to 2) select debug_grp_selected <= + dbg_group0 when "000", + dbg_group1 when "001", + dbg_group2 when "010", + dbg_group3 when "011", + dbg_group4 when "100", + dbg_group5 when "101", + dbg_group6 when "110", + dbg_group7 when others; + + with select_bits(5 to 6) select + debug_grp_rotated <= debug_grp_selected(DBG_1FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_1FOURTH-1) when "11", + debug_grp_selected(DBG_2FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_2FOURTH-1) when "10", + debug_grp_selected(DBG_3FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_3FOURTH-1) when "01", + debug_grp_selected(0 to DBG_WIDTH-1) when others; + + + with select_bits(7) select trace_data_out(0 to DBG_1FOURTH-1) <= + trace_data_in(0 to DBG_1FOURTH-1) when '0', + debug_grp_rotated(0 to DBG_1FOURTH-1) when others; + + with select_bits(8) select trace_data_out(DBG_1FOURTH to DBG_2FOURTH-1) <= + trace_data_in(DBG_1FOURTH to DBG_2FOURTH-1) when '0', + debug_grp_rotated(DBG_1FOURTH to DBG_2FOURTH-1) when others; + + with select_bits(9) select trace_data_out(DBG_2FOURTH to DBG_3FOURTH-1) <= + trace_data_in(DBG_2FOURTH to DBG_3FOURTH-1) when '0', + debug_grp_rotated(DBG_2FOURTH to DBG_3FOURTH-1) when others; + + with select_bits(10) select trace_data_out(DBG_3FOURTH to DBG_WIDTH-1) <= + trace_data_in(DBG_3FOURTH to DBG_WIDTH-1) when '0', + debug_grp_rotated(DBG_3FOURTH to DBG_WIDTH-1) when others; + + + + with select_bits(11 to 12) select trigg_grp_selected <= + trg_group0 when "00", + trg_group1 when "01", + trg_group2 when "10", + trg_group3 when others; + + with select_bits(13) select + trigg_grp_rotated <= trigg_grp_selected(6 to 11) & trigg_grp_selected(0 to 5) when '1', + trigg_grp_selected(0 to 11) when others; + + with select_bits(14) select trigger_data_out(0 to 5) <= + trigger_data_in(0 to 5) when '0', + trigg_grp_rotated(0 to 5) when others; + + with select_bits(15) select trigger_data_out(6 to 11) <= + trigger_data_in(6 to 11) when '0', + trigg_grp_rotated(6 to 11) when others; + + +end c_debug_mux8; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_event_mux.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_event_mux.vhdl new file mode 100644 index 0000000..629fd0c --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_event_mux.vhdl @@ -0,0 +1,146 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee,support,ibm; +use ieee.std_logic_1164.all; +use ibm.std_ulogic_function_support.all; +use support.power_logic_pkg.all; + +entity c_event_mux is + generic( events_in : integer := 32; + events_out : integer := 8 ); + port( + vd : inout power_logic; + gd : inout power_logic; + t0_events : in std_ulogic_vector(0 to events_in/4-1); + t1_events : in std_ulogic_vector(0 to events_in/4-1); + t2_events : in std_ulogic_vector(0 to events_in/4-1); + t3_events : in std_ulogic_vector(0 to events_in/4-1); + + select_bits : in std_ulogic_vector(0 to ((events_in/64+4)*events_out)-1); + + event_bits : out std_ulogic_vector(0 to events_out-1) +); +-- synopsys translate_off + +-- synopsys translate_on + +end c_event_mux; + + +architecture c_event_mux of c_event_mux is + + constant INCR : natural := events_in/64+4; + constant SIZE : natural := events_in/64+1; + + + signal inMuxDec : std_ulogic_vector(0 to events_out*events_in/4-1); + signal inMuxOut : std_ulogic_vector(0 to events_out*events_in/4-1); + + signal thrd_sel : std_ulogic_vector(0 to events_out-1); + signal inMux_sel : std_ulogic_vector(0 to ((events_in/64+3)*events_out)-1); + + +begin + thrd_sel <= select_bits(0*INCR) & select_bits(1*INCR) & + select_bits(2*INCR) & select_bits(3*INCR) & + select_bits(4*INCR) & select_bits(5*INCR) & + select_bits(6*INCR) & select_bits(7*INCR) ; + + inMux_sel <= select_bits(0*INCR+1 to (0+1)*INCR-1) & + select_bits(1*INCR+1 to (1+1)*INCR-1) & + select_bits(2*INCR+1 to (2+1)*INCR-1) & + select_bits(3*INCR+1 to (3+1)*INCR-1) & + select_bits(4*INCR+1 to (4+1)*INCR-1) & + select_bits(5*INCR+1 to (5+1)*INCR-1) & + select_bits(6*INCR+1 to (6+1)*INCR-1) & + select_bits(7*INCR+1 to (7+1)*INCR-1) ; + + + decode: for X in 0 to events_out-1 generate + Mux32: if (events_in = 32) generate + inMuxDec(X*events_in/4 to X*events_in/4+7) <= decode_3to8(inMux_sel(X*3 to X*3+2)); + end generate Mux32; + + Mux64: if (events_in = 64) generate + inMuxDec(X*events_in/4 to X*events_in/4+15) <= decode_4to16(inMux_sel(X*4 to X*4+3)); + end generate Mux64; + + Mux128: if (events_in = 128) generate + inMuxDec(X*events_in/4 to X*events_in/4+31) <= decode_5to32(inMux_sel(X*5 to X*5+4)); + end generate Mux128; + end generate decode; + + + inpMuxHi: for X in 0 to events_out/2-1 generate + eventSel: for I in 0 to events_in/4-1 generate + inMuxOut(X*events_in/4 + I) <= + ((inMuxDec(X*events_in/4 + I) and not thrd_sel(X) and t0_events(I)) or + (inMuxDec(X*events_in/4 + I) and thrd_sel(X) and t1_events(I)) ); + end generate eventSel; + end generate inpMuxHi; + + inpMuxLo: for X in events_out/2 to events_out-1 generate + eventSel: for I in 0 to events_in/4-1 generate + inMuxOut(X*events_in/4 + I) <= + ((inMuxDec(X*events_in/4 + I) and not thrd_sel(X) and t2_events(I)) or + (inMuxDec(X*events_in/4 + I) and thrd_sel(X) and t3_events(I)) ); + end generate eventSel; + end generate inpMuxLo; + + + bitOutHi: for X in 0 to events_out/2-1 generate + Mux32: if (events_in = 32) generate + event_bits(X) <= or_reduce(inMuxOut(X*events_in/4 to X*events_in/4 + 7)); + end generate Mux32; + + Mux64: if (events_in = 64) generate + event_bits(X) <= or_reduce(inMuxOut(X*events_in/4 to X*events_in/4 + 15)); + end generate Mux64; + + Mux128: if (events_in = 128) generate + event_bits(X) <= or_reduce(inMuxOut(X*events_in/4 to X*events_in/4 + 31)); + end generate Mux128; + end generate bitOutHi; + + bitOutLo: for X in events_out/2 to events_out-1 generate + Mux32: if (events_in = 32) generate + event_bits(X) <= or_reduce(inMuxOut(X*events_in/4 to X*events_in/4 + 7)); + end generate Mux32; + + Mux64: if (events_in = 64) generate + event_bits(X) <= or_reduce(inMuxOut(X*events_in/4 to X*events_in/4 + 15)); + end generate Mux64; + + Mux128: if (events_in = 128) generate + event_bits(X) <= or_reduce(inMuxOut(X*events_in/4 to X*events_in/4 + 31)); + end generate Mux128; + end generate bitOutLo; + +end c_event_mux; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_prism_bthmx.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_prism_bthmx.vhdl new file mode 100644 index 0000000..ad8f4de --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_prism_bthmx.vhdl @@ -0,0 +1,97 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee; use ieee.std_logic_1164.all ; +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; +library support; use support.power_logic_pkg.all; + +ENTITY c_prism_bthmx IS + GENERIC ( btr : string := "BTHMX_X1_A12TH" ); + PORT( + X : IN STD_ULOGIC; + SNEG : IN STD_ULOGIC; + SX : IN STD_ULOGIC; + SX2 : IN STD_ULOGIC; + RIGHT : IN STD_ULOGIC; + LEFT : OUT STD_ULOGIC; + Q : OUT STD_ULOGIC; + vd : inout power_logic; + gd : inout power_logic + ); + +-- synopsys translate_off + + + ATTRIBUTE PIN_BIT_INFORMATION of c_prism_bthmx : entity is + ( + 1 => (" ","X ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","SNEG ","SAME","PIN_BIT_SCALAR"), + 3 => (" ","SX ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","SX2 ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","RIGHT ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","LEFT ","SAME","PIN_BIT_SCALAR"), + 7 => (" ","Q ","SAME","PIN_BIT_SCALAR"), + 8 => (" ","VDD ","SAME","PIN_BIT_SCALAR"), + 9 => (" ","VSS ","SAME","PIN_BIT_SCALAR") + ); +-- synopsys translate_on +END c_prism_bthmx; + +ARCHITECTURE c_prism_bthmx OF c_prism_bthmx IS + + SIGNAL CENTER :STD_ULOGIC; + SIGNAL XN :STD_ULOGIC; + SIGNAL SPOS :STD_ULOGIC; + + +BEGIN + + XN <= NOT X; + + SPOS <= NOT SNEG; + + CENTER <= NOT( ( XN AND SPOS ) OR + ( X AND SNEG ) ); + + LEFT <= CENTER; + + + Q <= ( CENTER AND SX ) OR + ( RIGHT AND SX2 ) ; + + +END; + + + + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_prism_csa32.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_prism_csa32.vhdl new file mode 100644 index 0000000..4923c6f --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_prism_csa32.vhdl @@ -0,0 +1,82 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee; use ieee.std_logic_1164.all ; +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; +library support; use support.power_logic_pkg.all; + +ENTITY c_prism_csa32 IS + GENERIC ( btr : string := "CSA32_A2_A12TH" ); + PORT( + A : IN std_ulogic; + B : IN std_ulogic; + C : IN std_ulogic; + CAR : OUT std_ulogic; + SUM : OUT std_ulogic; + vd : inout power_logic; + gd : inout power_logic + ); + +-- synopsys translate_off + + + ATTRIBUTE PIN_BIT_INFORMATION of c_prism_csa32 : entity is + ( + 1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 3 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","CAR ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","SUM ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","VDD ","SAME","PIN_BIT_SCALAR"), + 7 => (" ","VSS ","SAME","PIN_BIT_SCALAR") + ); +-- synopsys translate_on +END c_prism_csa32; + +ARCHITECTURE c_prism_csa32 OF c_prism_csa32 IS + + +BEGIN + + sum <= a XOR b XOR c ; + + car <= (a AND b ) OR + (a AND c ) OR + (b AND c ); + + +END; + + + + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_prism_csa42.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_prism_csa42.vhdl new file mode 100644 index 0000000..30c661c --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_prism_csa42.vhdl @@ -0,0 +1,96 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; use ieee.std_logic_1164.all ; +library support; +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + use support.power_logic_pkg.all; + +ENTITY c_prism_csa42 IS + GENERIC ( btr : string := "CSA42_A2_A12TH" ); + PORT( + A : IN std_ulogic; + B : IN std_ulogic; + C : IN std_ulogic; + D : IN std_ulogic; + KI : IN std_ulogic; + KO : OUT std_ulogic; + CAR : OUT std_ulogic; + SUM : OUT std_ulogic; + vd : inout power_logic; + gd : inout power_logic + ); + +-- synopsys translate_off + + + ATTRIBUTE PIN_BIT_INFORMATION of c_prism_csa42 : entity is + ( + 1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 3 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","D ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","KI ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","KO ","SAME","PIN_BIT_SCALAR"), + 7 => (" ","CAR ","SAME","PIN_BIT_SCALAR"), + 8 => (" ","SUM ","SAME","PIN_BIT_SCALAR"), + 9 => (" ","VDD ","SAME","PIN_BIT_SCALAR"), + 10 => (" ","VSS ","SAME","PIN_BIT_SCALAR") + ); +-- synopsys translate_on +END c_prism_csa42; + +ARCHITECTURE c_prism_csa42 OF c_prism_csa42 IS + + signal s1 : std_ulogic; + +BEGIN + + s1 <= b XOR c XOR d ; + sum <= s1 XOR a XOR ki; + + car <= (s1 AND a ) OR + (s1 AND ki) OR + (a AND ki); + + ko <= (b AND c ) OR + (b AND d ) OR + (c AND d ); + + +END; + + + + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_scom_addr_decode.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_scom_addr_decode.vhdl new file mode 100644 index 0000000..1993fc7 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_scom_addr_decode.vhdl @@ -0,0 +1,70 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee,ibm,latches,clib, support; +use ieee.std_logic_1164.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use support.power_logic_pkg.all; + +entity c_scom_addr_decode is + generic( satid_nobits : positive := 5 + ; use_addr : std_ulogic_vector := "1" + ; addr_is_rdable : std_ulogic_vector := "1" + ; addr_is_wrable : std_ulogic_vector := "1" + ); + port( sc_addr : in std_ulogic_vector(0 to 11-satid_nobits-1) + ; scaddr_dec : out std_ulogic_vector(0 to use_addr'length-1) + ; sc_req : in std_ulogic + ; sc_r_nw : in std_ulogic + ; scaddr_nvld : out std_ulogic + ; sc_wr_nvld : out std_ulogic + ; sc_rd_nvld : out std_ulogic + ; vd : inout power_logic + ; gd : inout power_logic + ); + +end c_scom_addr_decode; + + + +architecture c_scom_addr_decode of c_scom_addr_decode is + signal address : std_ulogic_vector(0 to use_addr'length-1); +begin + decode_it : for i in 0 to use_addr'length-1 generate + address(i) <= ((sc_addr = tconv(i,sc_addr'length)) and (use_addr(i)='1')); + end generate decode_it; + + scaddr_dec <= address; + scaddr_nvld <= sc_req and not or_reduce(address); + sc_wr_nvld <= not or_reduce(address and addr_is_wrable) and sc_req and not sc_r_nw; + sc_rd_nvld <= not or_reduce(address and addr_is_rdable) and sc_req and sc_r_nw; +end c_scom_addr_decode; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/ibm/std_ulogic_ao_support.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/ibm/std_ulogic_ao_support.vhdl new file mode 100644 index 0000000..b162f61 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/ibm/std_ulogic_ao_support.vhdl @@ -0,0 +1,11616 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +--*************************************************************************** +-- Copyright 2020 International Business Machines +-- +-- Licensed under the Apache License, Version 2.0 (the “License”); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- The patent license granted to you in Section 3 of the License, as applied +-- to the “Work,” hereby includes implementations of the Work in physical form. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an “AS IS” BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- +--*************************************************************************** +library ibm,ieee ; +use ieee.std_logic_1164.all ; +use ibm.std_ulogic_support.all; + +package std_ulogic_ao_support is + -- ============================================================= + -- 2 input Port AO/OA Gates + -- ============================================================= + -- Single bit case + -- Multiple vectors logically ed bitwise + function gate_ao_2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_ao_2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_ao_2x1 : function is "VHDL-AO" ; + attribute recursive_synthesis of gate_ao_2x1 : function is 1; + attribute pin_bit_information of gate_ao_2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","PASS "," "," "), + 5 => (" ","PASS "," "," "), + 6 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function ao_2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function ao_2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of ao_2x1 : function is "VHDL-AO" ; + attribute recursive_synthesis of ao_2x1 : function is 1; + attribute pin_bit_information of ao_2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","PASS "," "," "), + 5 => (" ","PASS "," "," "), + 6 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_aoi_2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_aoi_2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_aoi_2x1 : function is "VHDL-AOI" ; + attribute recursive_synthesis of gate_aoi_2x1 : function is 1; + attribute pin_bit_information of gate_aoi_2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","PASS "," "," "), + 5 => (" ","PASS "," "," "), + 6 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function aoi_2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function aoi_2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of aoi_2x1 : function is "VHDL-AOI" ; + attribute recursive_synthesis of aoi_2x1 : function is 1; + attribute pin_bit_information of aoi_2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","PASS "," "," "), + 5 => (" ","PASS "," "," "), + 6 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oa_2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oa_2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oa_2x1 : function is "VHDL-OA" ; + attribute recursive_synthesis of gate_oa_2x1 : function is 1; + attribute pin_bit_information of gate_oa_2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","PASS "," "," "), + 5 => (" ","PASS "," "," "), + 6 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oa_2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oa_2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oa_2x1 : function is "VHDL-OA" ; + attribute recursive_synthesis of oa_2x1 : function is 1; + attribute pin_bit_information of oa_2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","PASS "," "," "), + 5 => (" ","PASS "," "," "), + 6 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oai_2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oai_2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oai_2x1 : function is "VHDL-OAI" ; + attribute recursive_synthesis of gate_oai_2x1 : function is 1; + attribute pin_bit_information of gate_oai_2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","PASS "," "," "), + 5 => (" ","PASS "," "," "), + 6 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oai_2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oai_2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oai_2x1 : function is "VHDL-OAI" ; + attribute recursive_synthesis of oai_2x1 : function is 1; + attribute pin_bit_information of oai_2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","PASS "," "," "), + 5 => (" ","PASS "," "," "), + 6 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_ao_2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_ao_2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_ao_2x2 : function is "VHDL-AO" ; + attribute recursive_synthesis of gate_ao_2x2 : function is 1; + attribute pin_bit_information of gate_ao_2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function ao_2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function ao_2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of ao_2x2 : function is "VHDL-AO" ; + attribute recursive_synthesis of ao_2x2 : function is 1; + attribute pin_bit_information of ao_2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_aoi_2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_aoi_2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_aoi_2x2 : function is "VHDL-AOI" ; + attribute recursive_synthesis of gate_aoi_2x2 : function is 1; + attribute pin_bit_information of gate_aoi_2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function aoi_2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function aoi_2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of aoi_2x2 : function is "VHDL-AOI" ; + attribute recursive_synthesis of aoi_2x2 : function is 1; + attribute pin_bit_information of aoi_2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oa_2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oa_2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oa_2x2 : function is "VHDL-OA" ; + attribute recursive_synthesis of gate_oa_2x2 : function is 1; + attribute pin_bit_information of gate_oa_2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oa_2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oa_2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oa_2x2 : function is "VHDL-OA" ; + attribute recursive_synthesis of oa_2x2 : function is 1; + attribute pin_bit_information of oa_2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oai_2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oai_2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oai_2x2 : function is "VHDL-OAI" ; + attribute recursive_synthesis of gate_oai_2x2 : function is 1; + attribute pin_bit_information of gate_oai_2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oai_2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oai_2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oai_2x2 : function is "VHDL-OAI" ; + attribute recursive_synthesis of oai_2x2 : function is 1; + attribute pin_bit_information of oai_2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + -- ============================================================= + -- 2x3 input Port AO/OA Gates + -- ============================================================= + -- Vectored primitive input functions + -- Single bit case + -- Multiple vectors logically ed bitwise + function gate_ao_2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_ao_2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_ao_2x1x1 : function is "VHDL-AO" ; + attribute recursive_synthesis of gate_ao_2x1x1 : function is 1; + attribute pin_bit_information of gate_ao_2x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function ao_2x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in2a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function ao_2x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in2a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of ao_2x1x1 : function is "VHDL-AO" ; + attribute recursive_synthesis of ao_2x1x1 : function is 1; + attribute pin_bit_information of ao_2x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_aoi_2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_aoi_2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_aoi_2x1x1 : function is "VHDL-AOI" ; + attribute recursive_synthesis of gate_aoi_2x1x1 : function is 1; + attribute pin_bit_information of gate_aoi_2x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function aoi_2x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in2a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function aoi_2x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in2a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of aoi_2x1x1 : function is "VHDL-AOI" ; + attribute recursive_synthesis of aoi_2x1x1 : function is 1; + attribute pin_bit_information of aoi_2x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oa_2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oa_2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oa_2x1x1 : function is "VHDL-OA" ; + attribute recursive_synthesis of gate_oa_2x1x1 : function is 1; + attribute pin_bit_information of gate_oa_2x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oa_2x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in2a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oa_2x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in2a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oa_2x1x1 : function is "VHDL-OA" ; + attribute recursive_synthesis of oa_2x1x1 : function is 1; + attribute pin_bit_information of oa_2x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oai_2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oai_2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oai_2x1x1 : function is "VHDL-OAI" ; + attribute recursive_synthesis of gate_oai_2x1x1 : function is 1; + attribute pin_bit_information of gate_oai_2x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oai_2x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in2a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oai_2x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in2a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oai_2x1x1 : function is "VHDL-OAI" ; + attribute recursive_synthesis of oai_2x1x1 : function is 1; + attribute pin_bit_information of oai_2x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_ao_2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_ao_2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_ao_2x2x1 : function is "VHDL-AO" ; + attribute recursive_synthesis of gate_ao_2x2x1 : function is 1; + attribute pin_bit_information of gate_ao_2x2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function ao_2x2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function ao_2x2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of ao_2x2x1 : function is "VHDL-AO" ; + attribute recursive_synthesis of ao_2x2x1 : function is 1; + attribute pin_bit_information of ao_2x2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_aoi_2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_aoi_2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_aoi_2x2x1 : function is "VHDL-AOI" ; + attribute recursive_synthesis of gate_aoi_2x2x1 : function is 1; + attribute pin_bit_information of gate_aoi_2x2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function aoi_2x2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function aoi_2x2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of aoi_2x2x1 : function is "VHDL-AOI" ; + attribute recursive_synthesis of aoi_2x2x1 : function is 1; + attribute pin_bit_information of aoi_2x2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oa_2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oa_2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oa_2x2x1 : function is "VHDL-OA" ; + attribute recursive_synthesis of gate_oa_2x2x1 : function is 1; + attribute pin_bit_information of gate_oa_2x2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oa_2x2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oa_2x2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oa_2x2x1 : function is "VHDL-OA" ; + attribute recursive_synthesis of oa_2x2x1 : function is 1; + attribute pin_bit_information of oa_2x2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oai_2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oai_2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oai_2x2x1 : function is "VHDL-OAI" ; + attribute recursive_synthesis of gate_oai_2x2x1 : function is 1; + attribute pin_bit_information of gate_oai_2x2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oai_2x2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oai_2x2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oai_2x2x1 : function is "VHDL-OAI" ; + attribute recursive_synthesis of oai_2x2x1 : function is 1; + attribute pin_bit_information of oai_2x2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_ao_2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_ao_2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_ao_2x2x2 : function is "VHDL-AO" ; + attribute recursive_synthesis of gate_ao_2x2x2 : function is 1; + attribute pin_bit_information of gate_ao_2x2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function ao_2x2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function ao_2x2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of ao_2x2x2 : function is "VHDL-AO" ; + attribute recursive_synthesis of ao_2x2x2 : function is 1; + attribute pin_bit_information of ao_2x2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_aoi_2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_aoi_2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_aoi_2x2x2 : function is "VHDL-AOI" ; + attribute recursive_synthesis of gate_aoi_2x2x2 : function is 1; + attribute pin_bit_information of gate_aoi_2x2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function aoi_2x2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function aoi_2x2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of aoi_2x2x2 : function is "VHDL-AOI" ; + attribute recursive_synthesis of aoi_2x2x2 : function is 1; + attribute pin_bit_information of aoi_2x2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oa_2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oa_2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oa_2x2x2 : function is "VHDL-OA" ; + attribute recursive_synthesis of gate_oa_2x2x2 : function is 1; + attribute pin_bit_information of gate_oa_2x2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oa_2x2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oa_2x2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oa_2x2x2 : function is "VHDL-OA" ; + attribute recursive_synthesis of oa_2x2x2 : function is 1; + attribute pin_bit_information of oa_2x2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oai_2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oai_2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oai_2x2x2 : function is "VHDL-OAI" ; + attribute recursive_synthesis of gate_oai_2x2x2 : function is 1; + attribute pin_bit_information of gate_oai_2x2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oai_2x2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oai_2x2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oai_2x2x2 : function is "VHDL-OAI" ; + attribute recursive_synthesis of oai_2x2x2 : function is 1; + attribute pin_bit_information of oai_2x2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + -- ============================================================= + -- 2x4 input Port AO/OA Gates + -- ============================================================= + -- Vectored primitive input functions + -- Single bit case + -- Multiple vectors logically ed bitwise + function gate_ao_2x1x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_ao_2x1x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_ao_2x1x1x1 : function is "VHDL-AO" ; + attribute recursive_synthesis of gate_ao_2x1x1x1 : function is 1; + attribute pin_bit_information of gate_ao_2x1x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","D ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function ao_2x1x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in2a : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function ao_2x1x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of ao_2x1x1x1 : function is "VHDL-AO" ; + attribute recursive_synthesis of ao_2x1x1x1 : function is 1; + attribute pin_bit_information of ao_2x1x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_aoi_2x1x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_aoi_2x1x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_aoi_2x1x1x1 : function is "VHDL-AOI" ; + attribute recursive_synthesis of gate_aoi_2x1x1x1 : function is 1; + attribute pin_bit_information of gate_aoi_2x1x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","D ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function aoi_2x1x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in2a : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function aoi_2x1x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of aoi_2x1x1x1 : function is "VHDL-AOI" ; + attribute recursive_synthesis of aoi_2x1x1x1 : function is 1; + attribute pin_bit_information of aoi_2x1x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oa_2x1x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oa_2x1x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oa_2x1x1x1 : function is "VHDL-OA" ; + attribute recursive_synthesis of gate_oa_2x1x1x1 : function is 1; + attribute pin_bit_information of gate_oa_2x1x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","D ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oa_2x1x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in2a : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oa_2x1x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oa_2x1x1x1 : function is "VHDL-OA" ; + attribute recursive_synthesis of oa_2x1x1x1 : function is 1; + attribute pin_bit_information of oa_2x1x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oai_2x1x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oai_2x1x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oai_2x1x1x1 : function is "VHDL-OAI" ; + attribute recursive_synthesis of gate_oai_2x1x1x1 : function is 1; + attribute pin_bit_information of gate_oai_2x1x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","D ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oai_2x1x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in2a : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oai_2x1x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oai_2x1x1x1 : function is "VHDL-OAI" ; + attribute recursive_synthesis of oai_2x1x1x1 : function is 1; + attribute pin_bit_information of oai_2x1x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_ao_2x2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_ao_2x2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_ao_2x2x1x1 : function is "VHDL-AO" ; + attribute recursive_synthesis of gate_ao_2x2x1x1 : function is 1; + attribute pin_bit_information of gate_ao_2x2x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","D ","SAME","PIN_BIT_SCALAR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function ao_2x2x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function ao_2x2x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of ao_2x2x1x1 : function is "VHDL-AO" ; + attribute recursive_synthesis of ao_2x2x1x1 : function is 1; + attribute pin_bit_information of ao_2x2x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_aoi_2x2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_aoi_2x2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_aoi_2x2x1x1 : function is "VHDL-AOI" ; + attribute recursive_synthesis of gate_aoi_2x2x1x1 : function is 1; + attribute pin_bit_information of gate_aoi_2x2x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","D ","SAME","PIN_BIT_SCALAR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function aoi_2x2x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function aoi_2x2x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of aoi_2x2x1x1 : function is "VHDL-AOI" ; + attribute recursive_synthesis of aoi_2x2x1x1 : function is 1; + attribute pin_bit_information of aoi_2x2x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oa_2x2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oa_2x2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oa_2x2x1x1 : function is "VHDL-OA" ; + attribute recursive_synthesis of gate_oa_2x2x1x1 : function is 1; + attribute pin_bit_information of gate_oa_2x2x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","D ","SAME","PIN_BIT_SCALAR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oa_2x2x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oa_2x2x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oa_2x2x1x1 : function is "VHDL-OA" ; + attribute recursive_synthesis of oa_2x2x1x1 : function is 1; + attribute pin_bit_information of oa_2x2x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oai_2x2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oai_2x2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oai_2x2x1x1 : function is "VHDL-OAI" ; + attribute recursive_synthesis of gate_oai_2x2x1x1 : function is 1; + attribute pin_bit_information of gate_oai_2x2x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","D ","SAME","PIN_BIT_SCALAR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oai_2x2x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oai_2x2x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oai_2x2x1x1 : function is "VHDL-OAI" ; + attribute recursive_synthesis of oai_2x2x1x1 : function is 1; + attribute pin_bit_information of oai_2x2x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_ao_2x2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_ao_2x2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_ao_2x2x2x1 : function is "VHDL-AO" ; + attribute recursive_synthesis of gate_ao_2x2x2x1 : function is 1; + attribute pin_bit_information of gate_ao_2x2x2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","D ","SAME","PIN_BIT_SCALAR"), + 8 => (" ","PASS "," "," "), + 9 => (" ","PASS "," "," "), + 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function ao_2x2x2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function ao_2x2x2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of ao_2x2x2x1 : function is "VHDL-AO" ; + attribute recursive_synthesis of ao_2x2x2x1 : function is 1; + attribute pin_bit_information of ao_2x2x2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","PASS "," "," "), + 9 => (" ","PASS "," "," "), + 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_aoi_2x2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_aoi_2x2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_aoi_2x2x2x1 : function is "VHDL-AOI" ; + attribute recursive_synthesis of gate_aoi_2x2x2x1 : function is 1; + attribute pin_bit_information of gate_aoi_2x2x2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","D ","SAME","PIN_BIT_SCALAR"), + 8 => (" ","PASS "," "," "), + 9 => (" ","PASS "," "," "), + 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function aoi_2x2x2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function aoi_2x2x2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of aoi_2x2x2x1 : function is "VHDL-AOI" ; + attribute recursive_synthesis of aoi_2x2x2x1 : function is 1; + attribute pin_bit_information of aoi_2x2x2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","PASS "," "," "), + 9 => (" ","PASS "," "," "), + 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oa_2x2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oa_2x2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oa_2x2x2x1 : function is "VHDL-OA" ; + attribute recursive_synthesis of gate_oa_2x2x2x1 : function is 1; + attribute pin_bit_information of gate_oa_2x2x2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","D ","SAME","PIN_BIT_SCALAR"), + 8 => (" ","PASS "," "," "), + 9 => (" ","PASS "," "," "), + 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oa_2x2x2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oa_2x2x2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oa_2x2x2x1 : function is "VHDL-OA" ; + attribute recursive_synthesis of oa_2x2x2x1 : function is 1; + attribute pin_bit_information of oa_2x2x2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","PASS "," "," "), + 9 => (" ","PASS "," "," "), + 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oai_2x2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oai_2x2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oai_2x2x2x1 : function is "VHDL-OAI" ; + attribute recursive_synthesis of gate_oai_2x2x2x1 : function is 1; + attribute pin_bit_information of gate_oai_2x2x2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","D ","SAME","PIN_BIT_SCALAR"), + 8 => (" ","PASS "," "," "), + 9 => (" ","PASS "," "," "), + 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oai_2x2x2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oai_2x2x2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oai_2x2x2x1 : function is "VHDL-OAI" ; + attribute recursive_synthesis of oai_2x2x2x1 : function is 1; + attribute pin_bit_information of oai_2x2x2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","PASS "," "," "), + 9 => (" ","PASS "," "," "), + 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_ao_2x2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_ao_2x2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_ao_2x2x2x2 : function is "VHDL-AO" ; + attribute recursive_synthesis of gate_ao_2x2x2x2 : function is 1; + attribute pin_bit_information of gate_ao_2x2x2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","D ","SAME","PIN_BIT_SCALAR"), + 8 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function ao_2x2x2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic ; + in3a : std_ulogic ; + in3b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function ao_2x2x2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector ; + in3a : std_ulogic_vector ; + in3b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of ao_2x2x2x2 : function is "VHDL-AO" ; + attribute recursive_synthesis of ao_2x2x2x2 : function is 1; + attribute pin_bit_information of ao_2x2x2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_aoi_2x2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_aoi_2x2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_aoi_2x2x2x2 : function is "VHDL-AOI" ; + attribute recursive_synthesis of gate_aoi_2x2x2x2 : function is 1; + attribute pin_bit_information of gate_aoi_2x2x2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","D ","SAME","PIN_BIT_SCALAR"), + 8 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function aoi_2x2x2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic ; + in3a : std_ulogic ; + in3b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function aoi_2x2x2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector ; + in3a : std_ulogic_vector ; + in3b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of aoi_2x2x2x2 : function is "VHDL-AOI" ; + attribute recursive_synthesis of aoi_2x2x2x2 : function is 1; + attribute pin_bit_information of aoi_2x2x2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oa_2x2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oa_2x2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oa_2x2x2x2 : function is "VHDL-OA" ; + attribute recursive_synthesis of gate_oa_2x2x2x2 : function is 1; + attribute pin_bit_information of gate_oa_2x2x2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","D ","SAME","PIN_BIT_SCALAR"), + 8 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oa_2x2x2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic ; + in3a : std_ulogic ; + in3b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oa_2x2x2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector ; + in3a : std_ulogic_vector ; + in3b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oa_2x2x2x2 : function is "VHDL-OA" ; + attribute recursive_synthesis of oa_2x2x2x2 : function is 1; + attribute pin_bit_information of oa_2x2x2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oai_2x2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oai_2x2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oai_2x2x2x2 : function is "VHDL-OAI" ; + attribute recursive_synthesis of gate_oai_2x2x2x2 : function is 1; + attribute pin_bit_information of gate_oai_2x2x2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","D ","SAME","PIN_BIT_SCALAR"), + 8 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oai_2x2x2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic ; + in3a : std_ulogic ; + in3b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oai_2x2x2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector ; + in3a : std_ulogic_vector ; + in3b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oai_2x2x2x2 : function is "VHDL-OAI" ; + attribute recursive_synthesis of oai_2x2x2x2 : function is 1; + attribute pin_bit_information of oai_2x2x2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + -- ============================================================= + -- 3 input Port AO/OA Gates + -- ============================================================= + -- Vectored primitive input functions + -- Single bit case + -- Multiple vectors logically ed bitwise + function gate_ao_3x1 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_ao_3x1 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_ao_3x1 : function is "VHDL-AO" ; + attribute recursive_synthesis of gate_ao_3x1 : function is 1; + attribute pin_bit_information of gate_ao_3x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function ao_3x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function ao_3x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of ao_3x1 : function is "VHDL-AO" ; + attribute recursive_synthesis of ao_3x1 : function is 1; + attribute pin_bit_information of ao_3x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_aoi_3x1 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_aoi_3x1 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_aoi_3x1 : function is "VHDL-AOI" ; + attribute recursive_synthesis of gate_aoi_3x1 : function is 1; + attribute pin_bit_information of gate_aoi_3x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function aoi_3x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function aoi_3x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of aoi_3x1 : function is "VHDL-AOI" ; + attribute recursive_synthesis of aoi_3x1 : function is 1; + attribute pin_bit_information of aoi_3x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oa_3x1 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oa_3x1 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oa_3x1 : function is "VHDL-OA" ; + attribute recursive_synthesis of gate_oa_3x1 : function is 1; + attribute pin_bit_information of gate_oa_3x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oa_3x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oa_3x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oa_3x1 : function is "VHDL-OA" ; + attribute recursive_synthesis of oa_3x1 : function is 1; + attribute pin_bit_information of oa_3x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oai_3x1 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oai_3x1 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oai_3x1 : function is "VHDL-OAI" ; + attribute recursive_synthesis of gate_oai_3x1 : function is 1; + attribute pin_bit_information of gate_oai_3x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oai_3x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oai_3x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oai_3x1 : function is "VHDL-OAI" ; + attribute recursive_synthesis of oai_3x1 : function is 1; + attribute pin_bit_information of oai_3x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_ao_3x2 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_ao_3x2 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_ao_3x2 : function is "VHDL-AO" ; + attribute recursive_synthesis of gate_ao_3x2 : function is 1; + attribute pin_bit_information of gate_ao_3x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function ao_3x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function ao_3x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of ao_3x2 : function is "VHDL-AO" ; + attribute recursive_synthesis of ao_3x2 : function is 1; + attribute pin_bit_information of ao_3x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_aoi_3x2 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_aoi_3x2 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_aoi_3x2 : function is "VHDL-AOI" ; + attribute recursive_synthesis of gate_aoi_3x2 : function is 1; + attribute pin_bit_information of gate_aoi_3x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function aoi_3x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function aoi_3x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of aoi_3x2 : function is "VHDL-AOI" ; + attribute recursive_synthesis of aoi_3x2 : function is 1; + attribute pin_bit_information of aoi_3x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oa_3x2 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oa_3x2 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oa_3x2 : function is "VHDL-OA" ; + attribute recursive_synthesis of gate_oa_3x2 : function is 1; + attribute pin_bit_information of gate_oa_3x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oa_3x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oa_3x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oa_3x2 : function is "VHDL-OA" ; + attribute recursive_synthesis of oa_3x2 : function is 1; + attribute pin_bit_information of oa_3x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oai_3x2 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oai_3x2 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oai_3x2 : function is "VHDL-OAI" ; + attribute recursive_synthesis of gate_oai_3x2 : function is 1; + attribute pin_bit_information of gate_oai_3x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oai_3x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oai_3x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oai_3x2 : function is "VHDL-OAI" ; + attribute recursive_synthesis of oai_3x2 : function is 1; + attribute pin_bit_information of oai_3x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_ao_3x3 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_ao_3x3 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_ao_3x3 : function is "VHDL-AO" ; + attribute recursive_synthesis of gate_ao_3x3 : function is 1; + attribute pin_bit_information of gate_ao_3x3 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function ao_3x3 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function ao_3x3 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of ao_3x3 : function is "VHDL-AO" ; + attribute recursive_synthesis of ao_3x3 : function is 1; + attribute pin_bit_information of ao_3x3 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_aoi_3x3 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_aoi_3x3 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_aoi_3x3 : function is "VHDL-AOI" ; + attribute recursive_synthesis of gate_aoi_3x3 : function is 1; + attribute pin_bit_information of gate_aoi_3x3 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function aoi_3x3 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function aoi_3x3 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of aoi_3x3 : function is "VHDL-AOI" ; + attribute recursive_synthesis of aoi_3x3 : function is 1; + attribute pin_bit_information of aoi_3x3 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oa_3x3 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oa_3x3 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oa_3x3 : function is "VHDL-OA" ; + attribute recursive_synthesis of gate_oa_3x3 : function is 1; + attribute pin_bit_information of gate_oa_3x3 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oa_3x3 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oa_3x3 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oa_3x3 : function is "VHDL-OA" ; + attribute recursive_synthesis of oa_3x3 : function is 1; + attribute pin_bit_information of oa_3x3 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oai_3x3 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oai_3x3 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oai_3x3 : function is "VHDL-OAI" ; + attribute recursive_synthesis of gate_oai_3x3 : function is 1; + attribute pin_bit_information of gate_oai_3x3 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oai_3x3 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oai_3x3 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oai_3x3 : function is "VHDL-OAI" ; + attribute recursive_synthesis of oai_3x3 : function is 1; + attribute pin_bit_information of oai_3x3 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + -- ============================================================= + -- 4 input Port AO/OA Gates + -- ============================================================= + -- Vectored primitive input functions + -- Single bit case + -- Multiple vectors logically ed bitwise + function gate_ao_4x1 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_ao_4x1 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_ao_4x1 : function is "VHDL-AO" ; + attribute recursive_synthesis of gate_ao_4x1 : function is 1; + attribute pin_bit_information of gate_ao_4x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function ao_4x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function ao_4x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of ao_4x1 : function is "VHDL-AO" ; + attribute recursive_synthesis of ao_4x1 : function is 1; + attribute pin_bit_information of ao_4x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_aoi_4x1 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_aoi_4x1 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_aoi_4x1 : function is "VHDL-AOI" ; + attribute recursive_synthesis of gate_aoi_4x1 : function is 1; + attribute pin_bit_information of gate_aoi_4x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function aoi_4x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function aoi_4x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of aoi_4x1 : function is "VHDL-AOI" ; + attribute recursive_synthesis of aoi_4x1 : function is 1; + attribute pin_bit_information of aoi_4x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oa_4x1 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oa_4x1 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oa_4x1 : function is "VHDL-OA" ; + attribute recursive_synthesis of gate_oa_4x1 : function is 1; + attribute pin_bit_information of gate_oa_4x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oa_4x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oa_4x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oa_4x1 : function is "VHDL-OA" ; + attribute recursive_synthesis of oa_4x1 : function is 1; + attribute pin_bit_information of oa_4x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oai_4x1 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oai_4x1 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oai_4x1 : function is "VHDL-OAI" ; + attribute recursive_synthesis of gate_oai_4x1 : function is 1; + attribute pin_bit_information of gate_oai_4x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oai_4x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oai_4x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oai_4x1 : function is "VHDL-OAI" ; + attribute recursive_synthesis of oai_4x1 : function is 1; + attribute pin_bit_information of oai_4x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_ao_4x2 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_ao_4x2 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_ao_4x2 : function is "VHDL-AO" ; + attribute recursive_synthesis of gate_ao_4x2 : function is 1; + attribute pin_bit_information of gate_ao_4x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function ao_4x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function ao_4x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of ao_4x2 : function is "VHDL-AO" ; + attribute recursive_synthesis of ao_4x2 : function is 1; + attribute pin_bit_information of ao_4x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_aoi_4x2 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_aoi_4x2 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_aoi_4x2 : function is "VHDL-AOI" ; + attribute recursive_synthesis of gate_aoi_4x2 : function is 1; + attribute pin_bit_information of gate_aoi_4x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function aoi_4x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function aoi_4x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of aoi_4x2 : function is "VHDL-AOI" ; + attribute recursive_synthesis of aoi_4x2 : function is 1; + attribute pin_bit_information of aoi_4x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oa_4x2 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oa_4x2 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oa_4x2 : function is "VHDL-OA" ; + attribute recursive_synthesis of gate_oa_4x2 : function is 1; + attribute pin_bit_information of gate_oa_4x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oa_4x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oa_4x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oa_4x2 : function is "VHDL-OA" ; + attribute recursive_synthesis of oa_4x2 : function is 1; + attribute pin_bit_information of oa_4x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oai_4x2 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oai_4x2 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oai_4x2 : function is "VHDL-OAI" ; + attribute recursive_synthesis of gate_oai_4x2 : function is 1; + attribute pin_bit_information of gate_oai_4x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oai_4x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oai_4x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oai_4x2 : function is "VHDL-OAI" ; + attribute recursive_synthesis of oai_4x2 : function is 1; + attribute pin_bit_information of oai_4x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_ao_4x3 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_ao_4x3 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_ao_4x3 : function is "VHDL-AO" ; + attribute recursive_synthesis of gate_ao_4x3 : function is 1; + attribute pin_bit_information of gate_ao_4x3 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","PASS "," "," "), + 9 => (" ","PASS "," "," "), + 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function ao_4x3 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function ao_4x3 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of ao_4x3 : function is "VHDL-AO" ; + attribute recursive_synthesis of ao_4x3 : function is 1; + attribute pin_bit_information of ao_4x3 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","PASS "," "," "), + 9 => (" ","PASS "," "," "), + 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_aoi_4x3 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_aoi_4x3 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_aoi_4x3 : function is "VHDL-AOI" ; + attribute recursive_synthesis of gate_aoi_4x3 : function is 1; + attribute pin_bit_information of gate_aoi_4x3 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","PASS "," "," "), + 9 => (" ","PASS "," "," "), + 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function aoi_4x3 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function aoi_4x3 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of aoi_4x3 : function is "VHDL-AOI" ; + attribute recursive_synthesis of aoi_4x3 : function is 1; + attribute pin_bit_information of aoi_4x3 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","PASS "," "," "), + 9 => (" ","PASS "," "," "), + 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oa_4x3 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oa_4x3 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oa_4x3 : function is "VHDL-OA" ; + attribute recursive_synthesis of gate_oa_4x3 : function is 1; + attribute pin_bit_information of gate_oa_4x3 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","PASS "," "," "), + 9 => (" ","PASS "," "," "), + 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oa_4x3 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oa_4x3 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oa_4x3 : function is "VHDL-OA" ; + attribute recursive_synthesis of oa_4x3 : function is 1; + attribute pin_bit_information of oa_4x3 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","PASS "," "," "), + 9 => (" ","PASS "," "," "), + 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oai_4x3 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oai_4x3 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oai_4x3 : function is "VHDL-OAI" ; + attribute recursive_synthesis of gate_oai_4x3 : function is 1; + attribute pin_bit_information of gate_oai_4x3 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","PASS "," "," "), + 9 => (" ","PASS "," "," "), + 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oai_4x3 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oai_4x3 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oai_4x3 : function is "VHDL-OAI" ; + attribute recursive_synthesis of oai_4x3 : function is 1; + attribute pin_bit_information of oai_4x3 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","PASS "," "," "), + 9 => (" ","PASS "," "," "), + 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_ao_4x4 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_ao_4x4 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_ao_4x4 : function is "VHDL-AO" ; + attribute recursive_synthesis of gate_ao_4x4 : function is 1; + attribute pin_bit_information of gate_ao_4x4 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function ao_4x4 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic ; + in1d : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function ao_4x4 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector ; + in1d : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of ao_4x4 : function is "VHDL-AO" ; + attribute recursive_synthesis of ao_4x4 : function is 1; + attribute pin_bit_information of ao_4x4 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_aoi_4x4 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_aoi_4x4 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_aoi_4x4 : function is "VHDL-AOI" ; + attribute recursive_synthesis of gate_aoi_4x4 : function is 1; + attribute pin_bit_information of gate_aoi_4x4 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function aoi_4x4 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic ; + in1d : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function aoi_4x4 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector ; + in1d : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of aoi_4x4 : function is "VHDL-AOI" ; + attribute recursive_synthesis of aoi_4x4 : function is 1; + attribute pin_bit_information of aoi_4x4 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oa_4x4 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oa_4x4 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oa_4x4 : function is "VHDL-OA" ; + attribute recursive_synthesis of gate_oa_4x4 : function is 1; + attribute pin_bit_information of gate_oa_4x4 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oa_4x4 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic ; + in1d : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oa_4x4 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector ; + in1d : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oa_4x4 : function is "VHDL-OA" ; + attribute recursive_synthesis of oa_4x4 : function is 1; + attribute pin_bit_information of oa_4x4 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oai_4x4 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oai_4x4 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oai_4x4 : function is "VHDL-OAI" ; + attribute recursive_synthesis of gate_oai_4x4 : function is 1; + attribute pin_bit_information of gate_oai_4x4 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oai_4x4 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic ; + in1d : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oai_4x4 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector ; + in1d : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oai_4x4 : function is "VHDL-OAI" ; + attribute recursive_synthesis of oai_4x4 : function is 1; + attribute pin_bit_information of oai_4x4 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + +end std_ulogic_ao_support; + +package body std_ulogic_ao_support is + -- ============================================================= + -- 2 input port ao/oa gates + -- ============================================================= + function gate_ao_2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 and in0 ) or gate1 ; + return result ; + end gate_ao_2x1 ; + + function gate_ao_2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( 0 to in0'length-1 => gate1 ) ; + return result ; + end gate_ao_2x1 ; + + function ao_2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a and in0b ) or in1a; + return result ; + end ao_2x1 ; + + function ao_2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a and in0b ) or in1a; + return result ; + end ao_2x1 ; + + function gate_aoi_2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not ( ( gate0 and in0 ) or gate1 ); + return result ; + end gate_aoi_2x1 ; + + function gate_aoi_2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not ( ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( 0 to in0'length-1 => gate1 ) ); + return result ; + end gate_aoi_2x1 ; + + function aoi_2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a and in0b ) or in1a ) ; + return result ; + end aoi_2x1 ; + + function aoi_2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a and in0b ) or in1a ) ; + return result ; + end aoi_2x1 ; + + function gate_oa_2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 or in0 ) and gate1 ; + return result ; + end gate_oa_2x1 ; + + function gate_oa_2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) or in0 ) and + ( 0 to in0'length-1 => gate1 ) ; + return result ; + end gate_oa_2x1 ; + + function oa_2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a or in0b ) and in1a ; + return result ; + end oa_2x1 ; + + function oa_2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a or in0b ) and in1a ; + return result ; + end oa_2x1 ; + + function gate_oai_2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 or in0 ) and gate1 ) ; + return result ; + end gate_oai_2x1 ; + + function gate_oai_2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not( ( ( 0 to in0'length-1 => gate0 ) or in0 ) and + ( 0 to in0'length-1 => gate1 ) ) ; + return result ; + end gate_oai_2x1 ; + + function oai_2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a or in0b ) and in1a ) ; + return result ; + end oai_2x1 ; + + function oai_2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a or in0b ) and in1a ) ; + return result ; + end oai_2x1 ; + + function gate_ao_2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( ( gate0 and in0 ) or ( gate1 and in1 ) ) ; + return result ; + end gate_ao_2x2 ; + + function gate_ao_2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( ( 0 to in1'length-1 => gate1 ) and in1 ) ; + return result ; + end gate_ao_2x2 ; + + function ao_2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ((in0a and in0b) or (in1a and in1b)); + return result ; + end ao_2x2 ; + + function ao_2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ((in0a and in0b) or (in1a and in1b)); + return result ; + end ao_2x2 ; + + function gate_aoi_2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not ((gate0 and in0) or (gate1 and in1)); + return result ; + end gate_aoi_2x2 ; + + function gate_aoi_2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not ( ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( ( 0 to in0'length-1 => gate1 ) and in1 ) ); + return result ; + end gate_aoi_2x2 ; + + function aoi_2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not ((in0a and in0b) or (in1a and in1b)); + return result ; + end aoi_2x2 ; + + function aoi_2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not ( ( in0a and in0b ) or ( in1a and in1b ) ); + return result ; + end aoi_2x2 ; + + function gate_oa_2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ((gate0 or in0) and (gate1 or in1)); + return result ; + end gate_oa_2x2 ; + + function gate_oa_2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) or in0 ) and + ( ( 0 to in1'length-1 => gate1 ) or in1 ); + return result ; + end gate_oa_2x2 ; + + function oa_2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ((in0a or in0b) and (in1a or in1b)); + return result ; + end oa_2x2 ; + + function oa_2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( ( in0a or in0b ) and ( in1a or in1b ) ); + return result ; + end oa_2x2 ; + + function gate_oai_2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not ((gate0 or in0) and (gate1 or in1)); + return result ; + end gate_oai_2x2 ; + + function gate_oai_2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not ( ( ( 0 to in0'length-1 => gate0 ) or in0 ) and + ( ( 0 to in1'length-1 => gate1 ) or in1 ) ); + return result ; + end gate_oai_2x2 ; + + function oai_2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not ((in0a or in0b) and (in1a or in1b)); + return result ; + end oai_2x2 ; + + function oai_2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not ( ( in0a or in0b ) and ( in1a or in1b ) ); + return result ; + end oai_2x2 ; + + -- ============================================================= + -- 3x2 input Port AO/OA Gates + -- ============================================================= + + function gate_ao_2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 and in0 ) or + ( gate1 ) or + ( gate2 ); + return result ; + end gate_ao_2x1x1 ; + + function gate_ao_2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( 0 to in0'length-1 => gate1 ) or + ( 0 to in0'length-1 => gate2 ) ; + return result ; + end gate_ao_2x1x1 ; + + function ao_2x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in2a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a and in0b ) or ( in1a ) or ( in2a ) ; + return result ; + end ao_2x1x1 ; + + function ao_2x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in2a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a and in0b ) or + ( in1a ) or + ( in2a ) ; + return result ; + end ao_2x1x1 ; + + function gate_aoi_2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not ( ( gate0 and in0 ) or + ( gate1 ) or + ( gate2 ) ); + return result ; + end gate_aoi_2x1x1 ; + + function gate_aoi_2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not( ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( 0 to in0'length-1 => gate1 ) or + ( 0 to in0'length-1 => gate2 ) ); + return result ; + end gate_aoi_2x1x1 ; + + function aoi_2x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in2a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not ((in0a and in0b) or (in1a) or (in2a)); + return result ; + end aoi_2x1x1 ; + + function aoi_2x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in2a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not ( ( in0a and in0b ) or + ( in1a ) or + ( in2a ) ); + return result ; + end aoi_2x1x1 ; + + function gate_oa_2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 or in0 ) and + ( gate1 ) and + ( gate2 ); + return result ; + end gate_oa_2x1x1 ; + + function gate_oa_2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) or in0 ) and + ( 0 to in0'length-1 => gate1 ) and + ( 0 to in0'length-1 => gate2 ) ; + return result ; + end gate_oa_2x1x1 ; + + function oa_2x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in2a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( ( in0a or in0b ) and ( in1a ) and ( in2a ) ); + return result ; + end oa_2x1x1 ; + + function oa_2x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in2a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector(0 to in0a'length-1); + begin + result := ( ( in0a or in0b ) and + ( in1a ) and + ( in2a ) ); + return result ; + end oa_2x1x1 ; + + function gate_oai_2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not ( ( gate0 or in0 ) and + ( gate1 ) and + ( gate2 ) ) ; + return result ; + end gate_oai_2x1x1 ; + + function gate_oai_2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not ( ( ( 0 to in0'length-1 => gate0 ) or in0 ) and + ( 0 to in0'length-1 => gate1 ) and + ( 0 to in0'length-1 => gate2 ) ) ; + return result ; + end gate_oai_2x1x1 ; + + function oai_2x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in2a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not ((in0a or in0b) and (in1a) and (in2a)); + return result ; + end oai_2x1x1 ; + + function oai_2x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in2a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not ((in0a or in0b) and + (in1a) and + (in2a)); + return result ; + end oai_2x1x1 ; + + function gate_ao_2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 and in0 ) or + ( gate1 and in1 ) or + ( gate2 ) ; + return result ; + end gate_ao_2x2x1 ; + + function gate_ao_2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( ( 0 to in1'length-1 => gate1 ) and in1 ) or + ( 0 to in0'length-1 => gate2 ) ; + return result ; + end gate_ao_2x2x1 ; + + function ao_2x2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a and in0b ) or + ( in1a and in1b ) or + ( in2a ) ; + return result ; + end ao_2x2x1 ; + + function ao_2x2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ((in0a and in0b) or + (in1a and in1b) or + (in2a)); + return result ; + end ao_2x2x1 ; + + function gate_aoi_2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 and in0 ) or + ( gate1 and in1 ) or + ( gate2 ) ) ; + return result ; + end gate_aoi_2x2x1 ; + + function gate_aoi_2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not( ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( ( 0 to in1'length-1 => gate1 ) and in1 ) or + ( 0 to in0'length-1 => gate2 ) ) ; + return result ; + end gate_aoi_2x2x1 ; + + function aoi_2x2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a and in0b ) or + ( in1a and in1b ) or + ( in2a ) ) ; + return result ; + end aoi_2x2x1 ; + + function aoi_2x2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a and in0b ) or + ( in1a and in1b ) or + ( in2a ) ) ; + return result ; + end aoi_2x2x1 ; + + function gate_oa_2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 or in0 ) and + ( gate1 or in1 ) and + ( gate2 ) ; + return result ; + end gate_oa_2x2x1 ; + + function gate_oa_2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) or in0 ) and + ( ( 0 to in1'length-1 => gate1 ) or in1 ) and + ( 0 to in0'length-1 => gate2 ) ; + return result ; + end gate_oa_2x2x1 ; + + function oa_2x2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a or in0b ) and + ( in1a or in1b ) and + ( in2a ) ; + return result ; + end oa_2x2x1 ; + + function oa_2x2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a or in0b ) and + ( in1a or in1b ) and + ( in2a ) ; + return result ; + end oa_2x2x1 ; + + function gate_oai_2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 or in0 ) and + ( gate1 or in1 ) and + ( gate2 ) ); + return result ; + end gate_oai_2x2x1 ; + + function gate_oai_2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not( ( ( 0 to in0'length-1 => gate0 ) or in0 ) and + ( ( 0 to in1'length-1 => gate1 ) or in1 ) and + ( 0 to in0'length-1 => gate2 ) ) ; + return result ; + end gate_oai_2x2x1 ; + + function oai_2x2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a or in0b ) and + ( in1a or in1b ) and + ( in2a ) ); + return result ; + end oai_2x2x1 ; + + function oai_2x2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a or in0b ) and + ( in1a or in1b ) and + ( in2a ) ); + return result ; + end oai_2x2x1 ; + + function gate_ao_2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 and in0 ) or + ( gate1 and in1 ) or + ( gate2 and in2 ) ; + return result ; + end gate_ao_2x2x2 ; + + function gate_ao_2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( ( 0 to in1'length-1 => gate1 ) and in1 ) or + ( ( 0 to in2'length-1 => gate2 ) and in2 ) ; + return result ; + end gate_ao_2x2x2 ; + + function ao_2x2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a and in0b ) or + ( in1a and in1b ) or + ( in2a and in2b ) ; + return result ; + end ao_2x2x2 ; + + function ao_2x2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a and in0b ) or + ( in1a and in1b ) or + ( in2a and in2b ) ; + return result ; + end ao_2x2x2 ; + + function gate_aoi_2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 and in0 ) or + ( gate1 and in1 ) or + ( gate2 and in2 ) ); + return result ; + end gate_aoi_2x2x2 ; + + function gate_aoi_2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not( ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( ( 0 to in1'length-1 => gate1 ) and in1 ) or + ( ( 0 to in2'length-1 => gate2 ) and in2 ) ) ; + return result ; + end gate_aoi_2x2x2 ; + + function aoi_2x2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a and in0b ) or + ( in1a and in1b ) or + ( in2a and in2b ) ); + return result ; + end aoi_2x2x2 ; + + function aoi_2x2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a and in0b ) or + ( in1a and in1b ) or + ( in2a and in2b ) ); + return result ; + end aoi_2x2x2 ; + + function gate_oa_2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 or in0 ) and + ( gate1 or in1 ) and + ( gate2 or in2 ) ; + return result ; + end gate_oa_2x2x2 ; + + function gate_oa_2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) or in0 ) and + ( ( 0 to in1'length-1 => gate1 ) or in1 ) and + ( ( 0 to in2'length-1 => gate2 ) or in2 ) ; + return result ; + end gate_oa_2x2x2 ; + + function oa_2x2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a or in0b ) and + ( in1a or in1b ) and + ( in2a or in2b ) ; + return result ; + end oa_2x2x2 ; + + function oa_2x2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a or in0b ) and + ( in1a or in1b ) and + ( in2a or in2b ) ; + return result ; + end oa_2x2x2 ; + + function gate_oai_2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 or in0 ) and + ( gate1 or in1 ) and + ( gate2 or in2 ) ) ; + return result ; + end gate_oai_2x2x2 ; + + function gate_oai_2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not( ( ( 0 to in0'length-1 => gate0 ) or in0 ) and + ( ( 0 to in1'length-1 => gate1 ) or in1 ) and + ( ( 0 to in2'length-1 => gate2 ) or in2 ) ) ; + return result ; + end gate_oai_2x2x2 ; + + function oai_2x2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a or in0b ) and + ( in1a or in1b ) and + ( in2a or in2b ) ) ; + return result ; + end oai_2x2x2 ; + + function oai_2x2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a or in0b ) and + ( in1a or in1b ) and + ( in2a or in2b ) ) ; + return result ; + end oai_2x2x2 ; + + -- ============================================================= + -- 4x2 input Port AO/OA Gates + -- ============================================================= + + function gate_ao_2x1x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 and in0 ) or + ( gate1 ) or + ( gate2 ) or + ( gate3 ) ; + return result ; + end gate_ao_2x1x1x1 ; + + function gate_ao_2x1x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( 0 to in0'length-1 => gate1 ) or + ( 0 to in0'length-1 => gate2 ) or + ( 0 to in0'length-1 => gate3 ) ; + return result ; + end gate_ao_2x1x1x1 ; + + function ao_2x1x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in2a : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a and in0b ) or + ( in1a ) or + ( in2a ) or + ( in3a ) ; + return result ; + end ao_2x1x1x1 ; + + function ao_2x1x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a and in0b ) or + ( in1a ) or + ( in2a ) or + ( in3a ) ; + return result ; + end ao_2x1x1x1 ; + + function gate_aoi_2x1x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 and in0 ) or + ( gate1 ) or + ( gate2 ) or + ( gate3 ) ) ; + return result ; + end gate_aoi_2x1x1x1 ; + + function gate_aoi_2x1x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not( ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( 0 to in0'length-1 => gate1 ) or + ( 0 to in0'length-1 => gate2 ) or + ( 0 to in0'length-1 => gate3 ) ) ; + return result ; + end gate_aoi_2x1x1x1 ; + + function aoi_2x1x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in2a : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a and in0b ) or + ( in1a ) or + ( in2a ) or + ( in3a ) ) ; + return result ; + end aoi_2x1x1x1 ; + + function aoi_2x1x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a and in0b ) or + ( in1a ) or + ( in2a ) or + ( in3a ) ) ; + return result ; + end aoi_2x1x1x1 ; + + function gate_oa_2x1x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 or in0 ) and + ( gate1 ) and + ( gate2 ) and + ( gate3 ); + return result ; + end gate_oa_2x1x1x1 ; + + function gate_oa_2x1x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) or in0 ) and + ( 0 to in0'length-1 => gate1 ) and + ( 0 to in0'length-1 => gate2 ) and + ( 0 to in0'length-1 => gate3 ); + return result ; + end gate_oa_2x1x1x1 ; + + function oa_2x1x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in2a : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a or in0b ) and + ( in1a ) and + ( in2a ) and + ( in3a ) ; + return result ; + end oa_2x1x1x1 ; + + function oa_2x1x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a or in0b ) and + ( in1a ) and + ( in2a ) and + ( in3a ) ; + return result ; + end oa_2x1x1x1 ; + + function gate_oai_2x1x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 or in0 ) and + ( gate1 ) and + ( gate2 ) and + ( gate3 ) ) ; + return result ; + end gate_oai_2x1x1x1 ; + + function gate_oai_2x1x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not( ( ( 0 to in0'length-1 => gate0 ) or in0 ) and + ( 0 to in0'length-1 => gate1 ) and + ( 0 to in0'length-1 => gate2 ) and + ( 0 to in0'length-1 => gate3 ) ) ; + return result ; + end gate_oai_2x1x1x1 ; + + function oai_2x1x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in2a : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a or in0b ) and + ( in1a ) and + ( in2a ) and + ( in3a ) ) ; + return result ; + end oai_2x1x1x1 ; + + function oai_2x1x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a or in0b ) and + ( in1a ) and + ( in2a ) and + ( in3a ) ) ; + return result ; + end oai_2x1x1x1 ; + + function gate_ao_2x2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 and in0 ) or + ( gate1 and in1 ) or + ( gate2 ) or + ( gate3 ) ; + return result ; + end gate_ao_2x2x1x1 ; + + function gate_ao_2x2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( ( 0 to in1'length-1 => gate1 ) and in1 ) or + ( 0 to in0'length-1 => gate2 ) or + ( 0 to in0'length-1 => gate3 ) ; + return result ; + end gate_ao_2x2x1x1 ; + + function ao_2x2x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a and in0b ) or + ( in1a and in1b ) or + ( in2a ) or + ( in3a ) ; + return result ; + end ao_2x2x1x1 ; + + function ao_2x2x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a and in0b ) or + ( in1a and in1b ) or + ( in2a ) or + ( in3a ) ; + return result ; + end ao_2x2x1x1 ; + + function gate_aoi_2x2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 and in0 ) or + ( gate1 and in1 ) or + ( gate2 ) or + ( gate3 ) ) ; + return result ; + end gate_aoi_2x2x1x1 ; + + function gate_aoi_2x2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not( ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( ( 0 to in1'length-1 => gate1 ) and in1 ) or + ( 0 to in0'length-1 => gate2 ) or + ( 0 to in0'length-1 => gate3 ) ) ; + return result ; + end gate_aoi_2x2x1x1 ; + + function aoi_2x2x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a and in0b ) or + ( in1a and in1b ) or + ( in2a ) or + ( in3a ) ) ; + return result ; + end aoi_2x2x1x1 ; + + function aoi_2x2x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a and in0b ) or + ( in1a and in1b ) or + ( in2a ) or + ( in3a ) ) ; + return result ; + end aoi_2x2x1x1 ; + + function gate_oa_2x2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 or in0 ) and + ( gate1 or in1 ) and + ( gate2 ) and + ( gate3 ) ; + return result ; + end gate_oa_2x2x1x1 ; + + function gate_oa_2x2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) or in0 ) and + ( ( 0 to in1'length-1 => gate1 ) or in1 ) and + ( 0 to in0'length-1 => gate2 ) and + ( 0 to in0'length-1 => gate3 ) ; + return result ; + end gate_oa_2x2x1x1 ; + + function oa_2x2x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a or in0b ) and + ( in1a or in1b ) and + ( in2a ) and + ( in3a ) ; + return result ; + end oa_2x2x1x1 ; + + function oa_2x2x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a or in0b ) and + ( in1a or in1b ) and + ( in2a ) and + ( in3a ) ; + return result ; + end oa_2x2x1x1 ; + + function gate_oai_2x2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 or in0 ) and + ( gate1 or in1 ) and + ( gate2 ) and + ( gate3 ) ) ; + return result ; + end gate_oai_2x2x1x1 ; + + function gate_oai_2x2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not( ( ( 0 to in0'length-1 => gate0 ) or in0 ) and + ( ( 0 to in1'length-1 => gate1 ) or in1 ) and + ( 0 to in0'length-1 => gate2 ) and + ( 0 to in0'length-1 => gate3 ) ) ; + return result ; + end gate_oai_2x2x1x1 ; + + function oai_2x2x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a or in0b ) and + ( in1a or in1b ) and + ( in2a ) and + ( in3a ) ) ; + return result ; + end oai_2x2x1x1 ; + + function oai_2x2x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a or in0b ) and + ( in1a or in1b ) and + ( in2a ) and + ( in3a ) ) ; + return result ; + end oai_2x2x1x1 ; + + function gate_ao_2x2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 and in0 ) or + ( gate1 and in1 ) or + ( gate2 and in2 ) or + ( gate3 ) ; + return result ; + end gate_ao_2x2x2x1 ; + + function gate_ao_2x2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( ( 0 to in1'length-1 => gate1 ) and in1 ) or + ( ( 0 to in2'length-1 => gate2 ) and in2 ) or + ( 0 to in0'length-1 => gate3 ) ; + return result ; + end gate_ao_2x2x2x1 ; + + function ao_2x2x2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a and in0b ) or + ( in1a and in1b ) or + ( in2a and in2b ) or + ( in3a ) ; + return result ; + end ao_2x2x2x1 ; + + function ao_2x2x2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a and in0b ) or + ( in1a and in1b ) or + ( in2a and in2b ) or + ( in3a ) ; + return result ; + end ao_2x2x2x1 ; + + function gate_aoi_2x2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 and in0 ) or + ( gate1 and in1 ) or + ( gate2 and in2 ) or + ( gate3 ) ); + return result ; + end gate_aoi_2x2x2x1 ; + + function gate_aoi_2x2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not( ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( ( 0 to in1'length-1 => gate1 ) and in1 ) or + ( ( 0 to in2'length-1 => gate2 ) and in2 ) or + ( 0 to in0'length-1 => gate3 ) ); + return result ; + end gate_aoi_2x2x2x1 ; + + function aoi_2x2x2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a and in0b ) or + ( in1a and in1b ) or + ( in2a and in2b ) or + ( in3a ) ) ; + return result ; + end aoi_2x2x2x1 ; + + function aoi_2x2x2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a and in0b ) or + ( in1a and in1b ) or + ( in2a and in2b ) or + ( in3a ) ) ; + return result ; + end aoi_2x2x2x1 ; + + function gate_oa_2x2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 or in0 ) and + ( gate1 or in1 ) and + ( gate2 or in2 ) and + ( gate3 ) ; + return result ; + end gate_oa_2x2x2x1 ; + + function gate_oa_2x2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) or in0 ) and + ( ( 0 to in1'length-1 => gate1 ) or in1 ) and + ( ( 0 to in2'length-1 => gate2 ) or in2 ) and + ( 0 to in0'length-1 => gate3 ) ; + return result ; + end gate_oa_2x2x2x1 ; + + function oa_2x2x2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a or in0b ) and + ( in1a or in1b ) and + ( in2a or in2b ) and + ( in3a ) ; + return result ; + end oa_2x2x2x1 ; + + function oa_2x2x2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a or in0b ) and + ( in1a or in1b ) and + ( in2a or in2b ) and + ( in3a ) ; + return result ; + end oa_2x2x2x1 ; + + function gate_oai_2x2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 or in0 ) and + ( gate1 or in1 ) and + ( gate2 or in2 ) and + ( gate3 ) ) ; + return result ; + end gate_oai_2x2x2x1 ; + + function gate_oai_2x2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not( ( ( 0 to in0'length-1 => gate0 ) or in0 ) and + ( ( 0 to in1'length-1 => gate1 ) or in1 ) and + ( ( 0 to in2'length-1 => gate2 ) or in2 ) and + ( 0 to in0'length-1 => gate3 ) ) ; + return result ; + end gate_oai_2x2x2x1 ; + + function oai_2x2x2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a or in0b ) and + ( in1a or in1b ) and + ( in2a or in2b ) and + ( in3a ) ) ; + return result ; + end oai_2x2x2x1 ; + + function oai_2x2x2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a or in0b ) and + ( in1a or in1b ) and + ( in2a or in2b ) and + ( in3a ) ) ; + return result ; + end oai_2x2x2x1 ; + + function gate_ao_2x2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 and in0 ) or + ( gate1 and in1 ) or + ( gate2 and in2 ) or + ( gate3 and in3 ) ; + return result ; + end gate_ao_2x2x2x2 ; + + function gate_ao_2x2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( ( 0 to in1'length-1 => gate1 ) and in1 ) or + ( ( 0 to in2'length-1 => gate2 ) and in2 ) or + ( ( 0 to in3'length-1 => gate3 ) and in3 ) ; + return result ; + end gate_ao_2x2x2x2 ; + + function ao_2x2x2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic ; + in3a : std_ulogic ; + in3b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a and in0b ) or + ( in1a and in1b ) or + ( in2a and in2b ) or + ( in3a and in3b ) ; + return result ; + end ao_2x2x2x2 ; + + function ao_2x2x2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector ; + in3a : std_ulogic_vector ; + in3b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a and in0b ) or + ( in1a and in1b ) or + ( in2a and in2b ) or + ( in3a and in3b ) ; + return result ; + end ao_2x2x2x2 ; + + function gate_aoi_2x2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 and in0 ) or + ( gate1 and in1 ) or + ( gate2 and in2 ) or + ( gate3 and in3 ) ) ; + return result ; + end gate_aoi_2x2x2x2 ; + + function gate_aoi_2x2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of BLOCK_DATA : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not( ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( ( 0 to in1'length-1 => gate1 ) and in1 ) or + ( ( 0 to in2'length-1 => gate2 ) and in2 ) or + ( ( 0 to in3'length-1 => gate3 ) and in3 ) ) ; + return result ; + end gate_aoi_2x2x2x2 ; + + function aoi_2x2x2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic ; + in3a : std_ulogic ; + in3b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a and in0b ) or + ( in1a and in1b ) or + ( in2a and in2b ) or + ( in3a and in3b ) ) ; + return result ; + end aoi_2x2x2x2 ; + + function aoi_2x2x2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector ; + in3a : std_ulogic_vector ; + in3b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a and in0b ) or + ( in1a and in1b ) or + ( in2a and in2b ) or + ( in3a and in3b ) ) ; + return result ; + end aoi_2x2x2x2 ; + + function gate_oa_2x2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 or in0 ) and + ( gate1 or in1 ) and + ( gate2 or in2 ) and + ( gate3 or in3 ) ; + return result ; + end gate_oa_2x2x2x2 ; + + function gate_oa_2x2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) or in0 ) and + ( ( 0 to in1'length-1 => gate1 ) or in1 ) and + ( ( 0 to in2'length-1 => gate2 ) or in2 ) and + ( ( 0 to in3'length-1 => gate3 ) or in3 ) ; + return result ; + end gate_oa_2x2x2x2 ; + + function oa_2x2x2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic ; + in3a : std_ulogic ; + in3b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a or in0b ) and + ( in1a or in1b ) and + ( in2a or in2b ) and + ( in3a or in3b ) ; + return result ; + end oa_2x2x2x2 ; + + function oa_2x2x2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector ; + in3a : std_ulogic_vector ; + in3b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a or in0b ) and + ( in1a or in1b ) and + ( in2a or in2b ) and + ( in3a or in3b ) ; + return result ; + end oa_2x2x2x2 ; + + function gate_oai_2x2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 or in0 ) and + ( gate1 or in1 ) and + ( gate2 or in2 ) and + ( gate3 or in3 ) ) ; + return result ; + end gate_oai_2x2x2x2 ; + + function gate_oai_2x2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not( ( ( 0 to in0'length-1 => gate0 ) or in0 ) and + ( ( 0 to in1'length-1 => gate1 ) or in1 ) and + ( ( 0 to in2'length-1 => gate2 ) or in2 ) and + ( ( 0 to in3'length-1 => gate3 ) or in3 ) ) ; + return result ; + end gate_oai_2x2x2x2 ; + + function oai_2x2x2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic ; + in3a : std_ulogic ; + in3b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a or in0b ) and + ( in1a or in1b ) and + ( in2a or in2b ) and + ( in3a or in3b ) ) ; + return result ; + end oai_2x2x2x2 ; + + function oai_2x2x2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector ; + in3a : std_ulogic_vector ; + in3b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a or in0b ) and + ( in1a or in1b ) and + ( in2a or in2b ) and + ( in3a or in3b ) ) ; + return result ; + end oai_2x2x2x2 ; + + -- ============================================================= + -- 3 input Port AO/OA Gates + -- ============================================================= + + function gate_ao_3x1 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 and in0a and in0b) or + ( gate1 ) ; + return result ; + end gate_ao_3x1 ; + + function gate_ao_3x1 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( ( 0 to in0a'length-1 => gate0 ) and in0a and in0b) or + ( 0 to in0a'length-1 => gate1 ) ; + return result ; + end gate_ao_3x1 ; + + function ao_3x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a and in0b and in0c ) or + ( in1a ) ; + return result ; + end ao_3x1 ; + + function ao_3x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector( 0 to in0a'length-1 ) ; + begin + result := ( in0a and in0b and in0c ) or + ( in1a ) ; + return result ; + end ao_3x1 ; + + function gate_aoi_3x1 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 and in0a and in0b) or + ( gate1 ) ) ; + return result ; + end gate_aoi_3x1 ; + + function gate_aoi_3x1 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( ( 0 to in0a'length-1 => gate0 ) and in0a and in0b) or + ( 0 to in0a'length-1 => gate1 ) ) ; + return result ; + end gate_aoi_3x1 ; + + function aoi_3x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a and in0b and in0c ) or + ( in1a ) ); + return result ; + end aoi_3x1 ; + + function aoi_3x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a and in0b and in0c ) or + ( in1a ) ); + return result ; + end aoi_3x1 ; + + function gate_oa_3x1 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 or in0a or in0b ) and + ( gate1 ) ; + return result ; + end gate_oa_3x1 ; + + function gate_oa_3x1 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( ( 0 to in0a'length-1 => gate0 ) or in0a or in0b ) and + ( 0 to in0a'length-1 => gate1 ) ; + return result ; + end gate_oa_3x1 ; + + function oa_3x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a or in0b or in0c ) and + ( in1a ) ; + return result ; + end oa_3x1 ; + + function oa_3x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a or in0b or in0c ) and + ( in1a ) ; + return result ; + end oa_3x1 ; + + function gate_oai_3x1 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 or in0a or in0b ) and + ( gate1 ) ) ; + return result ; + end gate_oai_3x1 ; + + function gate_oai_3x1 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( ( 0 to in0a'length-1 => gate0 ) or in0a or in0b ) and + ( 0 to in0a'length-1 => gate1 ) ) ; + return result ; + end gate_oai_3x1 ; + + function oai_3x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a or in0b or in0c ) and + ( in1a ) ); + return result ; + end oai_3x1 ; + + function oai_3x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a or in0b or in0c ) and + ( in1a ) ); + return result ; + end oai_3x1 ; + + function gate_ao_3x2 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 and in0a and in0b ) or + ( gate1 and in1a ) ; + return result ; + end gate_ao_3x2 ; + + function gate_ao_3x2 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( ( 0 to in0a'length-1 => gate0 ) and in0a and in0b ) or + ( ( 0 to in1a'length-1 => gate1 ) and in1a ) ; + return result ; + end gate_ao_3x2 ; + + function ao_3x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a and in0b and in0c ) or + ( in1a and in1b ) ; + return result ; + end ao_3x2 ; + + function ao_3x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a and in0b and in0c ) or + ( in1a and in1b ) ; + return result ; + end ao_3x2 ; + + function gate_aoi_3x2 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 and in0a and in0b ) or + ( gate1 and in1a ) ) ; + return result ; + end gate_aoi_3x2 ; + + function gate_aoi_3x2 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( ( 0 to in0a'length-1 => gate0 ) and in0a and in0b ) or + ( ( 0 to in1a'length-1 => gate1 ) and in1a ) ) ; + return result ; + end gate_aoi_3x2 ; + + function aoi_3x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a and in0b and in0c ) or + ( in1a and in1b ) ) ; + return result ; + end aoi_3x2 ; + + function aoi_3x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a and in0b and in0c ) or + ( in1a and in1b ) ) ; + return result ; + end aoi_3x2 ; + + function gate_oa_3x2 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 or in0a or in0b ) and + ( gate1 or in1a ) ; + return result ; + end gate_oa_3x2 ; + + function gate_oa_3x2 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( ( 0 to in0a'length-1 => gate0 ) or in0a or in0b ) and + ( ( 0 to in1a'length-1 => gate1 ) or in1a ) ; + return result ; + end gate_oa_3x2 ; + + function oa_3x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a or in0b or in0c ) and + ( in1a or in1b ) ; + return result ; + end oa_3x2 ; + + function oa_3x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a or in0b or in0c ) and + ( in1a or in1b ) ; + return result ; + end oa_3x2 ; + + function gate_oai_3x2 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 or in0a or in0b ) and + ( gate1 or in1a ) ); + return result ; + end gate_oai_3x2 ; + + function gate_oai_3x2 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( ( 0 to in0a'length-1 => gate0 ) or in0a or in0b ) and + ( ( 0 to in1a'length-1 => gate1 ) or in1a ) ); + return result ; + end gate_oai_3x2 ; + + function oai_3x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a or in0b or in0c ) and + ( in1a or in1b ) ); + return result ; + end oai_3x2 ; + + function oai_3x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a or in0b or in0c ) and + ( in1a or in1b ) ); + return result ; + end oai_3x2 ; + + function gate_ao_3x3 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 and in0a and in0b ) or + ( gate1 and in1a and in1b ) ; + return result ; + end gate_ao_3x3 ; + + function gate_ao_3x3 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( ( 0 to in0a'length-1 => gate0 ) and in0a and in0b ) or + ( ( 0 to in1a'length-1 => gate1 ) and in1a and in1b ) ; + return result ; + end gate_ao_3x3 ; + + function ao_3x3 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a and in0b and in0c ) or + ( in1a and in1b and in1c ) ; + return result ; + end ao_3x3 ; + + function ao_3x3 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a and in0b and in0c ) or + ( in1a and in1b and in1c ) ; + return result ; + end ao_3x3 ; + + function gate_aoi_3x3 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 and in0a and in0b ) or + ( gate1 and in1a and in1b ) ) ; + return result ; + end gate_aoi_3x3 ; + + function gate_aoi_3x3 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( ( 0 to in0a'length => gate0 ) and in0a and in0b ) or + ( ( 0 to in1a'length => gate1 ) and in1a and in1b ) ) ; + return result ; + end gate_aoi_3x3 ; + + function aoi_3x3 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a and in0b and in0c ) or + ( in1a and in1b and in1c ) ); + return result ; + end aoi_3x3 ; + + function aoi_3x3 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a and in0b and in0c ) or + ( in1a and in1b and in1c ) ); + return result ; + end aoi_3x3 ; + + function gate_oa_3x3 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 or in0a or in0b ) and + ( gate1 or in1a or in1b ) ; + return result ; + end gate_oa_3x3 ; + + function gate_oa_3x3 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( ( 0 to in0a'length-1 => gate0 ) or in0a or in0b ) and + ( ( 0 to in1a'length-1 => gate1 ) or in1a or in1b ) ; + return result ; + end gate_oa_3x3 ; + + function oa_3x3 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a or in0b or in0c ) and + ( in1a or in1b or in1c ) ; + return result ; + end oa_3x3 ; + + function oa_3x3 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a or in0b or in0c ) and + ( in1a or in1b or in1c ) ; + return result ; + end oa_3x3 ; + + function gate_oai_3x3 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 or in0a or in0b ) and + ( gate1 or in1a or in1b ) ) ; + return result ; + end gate_oai_3x3 ; + + function gate_oai_3x3 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( ( 0 to in0a'length-1 => gate0 ) or in0a or in0b ) and + ( ( 0 to in1a'length-1 => gate1 ) or in1a or in1b ) ) ; + return result ; + end gate_oai_3x3 ; + + function oai_3x3 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a or in0b or in0c ) and + ( in1a or in1b or in1c ) ) ; + return result ; + end oai_3x3 ; + + function oai_3x3 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a or in0b or in0c ) and + ( in1a or in1b or in1c ) ) ; + return result ; + end oai_3x3 ; + + -- ============================================================= + -- 4 input Port AO/OA Gates + -- ============================================================= + + function gate_ao_4x1 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 and in0a and in0b and in0c ) or + ( gate1 ) ; + return result ; + end gate_ao_4x1 ; + + function gate_ao_4x1 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( ( 0 to in0a'length-1 => gate0 ) and in0a and in0b and in0c ) or + ( 0 to in0a'length-1 => gate1 ) ; + return result ; + end gate_ao_4x1 ; + + function ao_4x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a and in0b and in0c and in0d ) or + ( in1a ) ; + return result ; + end ao_4x1 ; + + function ao_4x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a and in0b and in0c and in0d ) or + ( in1a ) ; + return result ; + end ao_4x1 ; + + function gate_aoi_4x1 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 and in0a and in0b and in0c ) or + ( gate1 ) ); + return result ; + end gate_aoi_4x1 ; + + function gate_aoi_4x1 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( ( 0 to in0a'length-1 => gate0 ) and in0a and in0b and in0c ) or + ( 0 to in0a'length-1 => gate1 ) ) ; + return result ; + end gate_aoi_4x1 ; + + function aoi_4x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a and in0b and in0c and in0d ) or + ( in1a ) ) ; + return result ; + end aoi_4x1 ; + + function aoi_4x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a and in0b and in0c and in0d ) or + ( in1a ) ) ; + return result ; + end aoi_4x1 ; + + function gate_oa_4x1 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 or in0a or in0b or in0c ) and + ( gate1 ) ; + return result ; + end gate_oa_4x1 ; + + function gate_oa_4x1 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( ( 0 to in0a'length-1 => gate0 ) or in0a or in0b or in0c ) and + ( 0 to in0a'length-1 => gate1 ) ; + return result ; + end gate_oa_4x1 ; + + function oa_4x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a or in0b or in0c or in0d ) and + ( in1a ) ; + return result ; + end oa_4x1 ; + + function oa_4x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a or in0b or in0c or in0d ) and + ( in1a ) ; + return result ; + end oa_4x1 ; + + function gate_oai_4x1 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 or in0a or in0b or in0c ) and + ( gate1 ) ) ; + return result ; + end gate_oai_4x1 ; + + function gate_oai_4x1 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( ( 0 to in0a'length-1 => gate0 ) or in0a or in0b or in0c ) and + ( 0 to in0a'length-1 => gate1 ) ) ; + return result ; + end gate_oai_4x1 ; + + function oai_4x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a or in0b or in0c or in0d ) and + ( in1a ) ) ; + return result ; + end oai_4x1 ; + + function oai_4x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a or in0b or in0c or in0d ) and + ( in1a ) ) ; + return result ; + end oai_4x1 ; + + function gate_ao_4x2 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 and in0a and in0b and in0c ) or + ( gate1 and in1a ) ; + return result ; + end gate_ao_4x2 ; + + function gate_ao_4x2 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( ( 0 to in0a'length-1 => gate0 ) and in0a and in0b and in0c ) or + ( ( 0 to in1a'length-1 => gate1 ) and in1a ) ; + return result ; + end gate_ao_4x2 ; + + function ao_4x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a and in0b and in0c and in0d ) or + ( in1a and in1b ) ; + return result ; + end ao_4x2 ; + + function ao_4x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a and in0b and in0c and in0d ) or + ( in1a and in1b ) ; + return result ; + end ao_4x2 ; + + function gate_aoi_4x2 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 and in0a and in0b and in0c ) or + ( gate1 and in1a ) ) ; + return result ; + end gate_aoi_4x2 ; + + function gate_aoi_4x2 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( ( 0 to in0a'length-1 => gate0 ) and in0a and in0b and in0c ) or + ( ( 0 to in1a'length-1 => gate1 ) and in1a ) ) ; + return result ; + end gate_aoi_4x2 ; + + function aoi_4x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a and in0b and in0c and in0d ) or + ( in1a and in1b ) ) ; + return result ; + end aoi_4x2 ; + + function aoi_4x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a and in0b and in0c and in0d ) or + ( in1a and in1b ) ) ; + return result ; + end aoi_4x2 ; + + function gate_oa_4x2 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 or in0a or in0b or in0c ) and + ( gate1 or in1a ) ; + return result ; + end gate_oa_4x2 ; + + function gate_oa_4x2 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( ( 0 to in0a'length-1 => gate0 ) or in0a or in0b or in0c ) and + ( ( 0 to in1a'length-1 => gate1 ) or in1a ) ; + return result ; + end gate_oa_4x2 ; + + function oa_4x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a or in0b or in0c or in0d ) and + ( in1a or in1b ) ; + return result ; + end oa_4x2 ; + + function oa_4x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a or in0b or in0c or in0d ) and + ( in1a or in1b ) ; + return result ; + end oa_4x2 ; + + function gate_oai_4x2 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 or in0a or in0b or in0c ) and + ( gate1 or in1a ) ); + return result ; + end gate_oai_4x2 ; + + function gate_oai_4x2 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( ( 0 to in0a'length-1 => gate0 ) or in0a or in0b or in0c ) and + ( ( 0 to in1a'length-1 => gate1 ) or in1a ) ); + return result ; + end gate_oai_4x2 ; + + function oai_4x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a or in0b or in0c or in0d ) and + ( in1a or in1b ) ) ; + return result ; + end oai_4x2 ; + + function oai_4x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a or in0b or in0c or in0d ) and + ( in1a or in1b ) ) ; + return result ; + end oai_4x2 ; + + function gate_ao_4x3 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 and in0a and in0b and in0c ) or + ( gate1 and in1a and in1b ) ; + return result ; + end gate_ao_4x3 ; + + function gate_ao_4x3 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( ( 0 to in0a'length-1 => gate0 ) and in0a and in0b and in0c ) or + ( ( 0 to in1a'length-1 => gate1 ) and in1a and in1b ) ; + return result ; + end gate_ao_4x3 ; + + function ao_4x3 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a and in0b and in0c and in0d ) or + ( in1a and in1b and in1c ) ; + return result ; + end ao_4x3 ; + + function ao_4x3 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a and in0b and in0c and in0d ) or + ( in1a and in1b and in1c ) ; + return result ; + end ao_4x3 ; + + function gate_aoi_4x3 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 and in0a and in0b and in0c ) or + ( gate1 and in1a and in1b ) ) ; + return result ; + end gate_aoi_4x3 ; + + function gate_aoi_4x3 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( ( 0 to in0a'length-1 => gate0 ) and in0a and in0b and in0c ) or + ( ( 0 to in1a'length-1 => gate1 ) and in1a and in1b ) ) ; + return result ; + end gate_aoi_4x3 ; + + function aoi_4x3 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a and in0b and in0c and in0d ) or + ( in1a and in1b and in1c ) ) ; + return result ; + end aoi_4x3 ; + + function aoi_4x3 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a and in0b and in0c and in0d ) or + ( in1a and in1b and in1c ) ) ; + return result ; + end aoi_4x3 ; + + function gate_oa_4x3 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 or in0a or in0b or in0c ) and + ( gate1 or in1a or in1b ) ; + return result ; + end gate_oa_4x3 ; + + function gate_oa_4x3 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( ( 0 to in0a'length-1 => gate0 ) or in0a or in0b or in0c ) and + ( ( 0 to in1a'length-1 => gate1 ) or in1a or in1b ) ; + return result ; + end gate_oa_4x3 ; + + function oa_4x3 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a or in0b or in0c or in0d ) and + ( in1a or in1b or in1c ) ; + return result ; + end oa_4x3 ; + + function oa_4x3 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a or in0b or in0c or in0d ) and + ( in1a or in1b or in1c ) ; + return result ; + end oa_4x3 ; + + function gate_oai_4x3 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 or in0a or in0b or in0c ) and + ( gate1 or in1a or in1b ) ) ; + return result ; + end gate_oai_4x3 ; + + function gate_oai_4x3 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( ( 0 to in0a'length-1 => gate0 ) or in0a or in0b or in0c ) and + ( ( 0 to in1a'length-1 => gate1 ) or in1a or in1b ) ) ; + return result ; + end gate_oai_4x3 ; + + function oai_4x3 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a or in0b or in0c or in0d ) and + ( in1a or in1b or in1c ) ) ; + return result ; + end oai_4x3 ; + + function oai_4x3 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a or in0b or in0c or in0d ) and + ( in1a or in1b or in1c ) ) ; + return result ; + end oai_4x3 ; + + function gate_ao_4x4 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 and in0a and in0b and in0c ) or + ( gate1 and in1a and in1b and in1c ) ; + return result ; + end gate_ao_4x4 ; + + function gate_ao_4x4 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( ( 0 to in0a'length-1 => gate0 ) and in0a and in0b and in0c ) or + ( ( 0 to in1a'length-1 => gate1 ) and in1a and in1b and in1c ) ; + return result ; + end gate_ao_4x4 ; + + function ao_4x4 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic ; + in1d : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a and in0b and in0c and in0d ) or + ( in1a and in1b and in1c and in1d ) ; + return result ; + end ao_4x4 ; + + function ao_4x4 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector ; + in1d : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a and in0b and in0c and in0d ) or + ( in1a and in1b and in1c and in1d ) ; + return result ; + end ao_4x4 ; + + function gate_aoi_4x4 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 and in0a and in0b and in0c ) or + ( gate1 and in1a and in1b and in1c ) ) ; + return result ; + end gate_aoi_4x4 ; + + function gate_aoi_4x4 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( ( 0 to in0a'length-1 => gate0 ) and in0a and in0b and in0c ) or + ( ( 0 to in1a'length-1 => gate1 ) and in1a and in1b and in1c ) ) ; + return result ; + end gate_aoi_4x4 ; + + function aoi_4x4 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic ; + in1d : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a and in0b and in0c and in0d ) or + ( in1a and in1b and in1c and in1d ) ) ; + return result ; + end aoi_4x4 ; + + function aoi_4x4 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector ; + in1d : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a and in0b and in0c and in0d ) or + ( in1a and in1b and in1c and in1d ) ) ; + return result ; + end aoi_4x4 ; + + function gate_oa_4x4 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 or in0a or in0b or in0c ) and + ( gate1 or in1a or in1b or in1c ) ; + return result ; + end gate_oa_4x4 ; + + function gate_oa_4x4 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( ( 0 to in0a'length-1 => gate0 ) or in0a or in0b or in0c ) and + ( ( 0 to in1a'length-1 => gate1 ) or in1a or in1b or in1c ) ; + return result ; + end gate_oa_4x4 ; + + function oa_4x4 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic ; + in1d : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a or in0b or in0c or in0d ) and + ( in1a or in1b or in1c or in1d ) ; + return result ; + end oa_4x4 ; + + function oa_4x4 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector ; + in1d : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a or in0b or in0c or in0d ) and + ( in1a or in1b or in1c or in1d ) ; + return result ; + end oa_4x4 ; + + function gate_oai_4x4 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 or in0a or in0b or in0c ) and + ( gate1 or in1a or in1b or in1c ) ) ; + return result ; + end gate_oai_4x4 ; + + function gate_oai_4x4 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( ( 0 to in0a'length-1 => gate0 ) or in0a or in0b or in0c ) and + ( ( 0 to in1a'length-1 => gate1 ) or in1a or in1b or in1c ) ) ; + return result ; + end gate_oai_4x4 ; + + function oai_4x4 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic ; + in1d : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a or in0b or in0c or in0d ) and + ( in1a or in1b or in1c or in1d ) ) ; + return result ; + end oai_4x4 ; + + function oai_4x4 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector ; + in1d : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a or in0b or in0c or in0d ) and + ( in1a or in1b or in1c or in1d ) ) ; + return result ; + end oai_4x4 ; + +end std_ulogic_ao_support; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/ibm/std_ulogic_function_support.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/ibm/std_ulogic_function_support.vhdl new file mode 100644 index 0000000..b190bde --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/ibm/std_ulogic_function_support.vhdl @@ -0,0 +1,5179 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +--*************************************************************************** +-- Copyright 2020 International Business Machines +-- +-- Licensed under the Apache License, Version 2.0 (the “License”); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- The patent license granted to you in Section 3 of the License, as applied +-- to the “Work,” hereby includes implementations of the Work in physical form. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an “AS IS” BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- +--*************************************************************************** +library ibm,ieee ; +use ieee.std_logic_1164.all ; +use ibm.std_ulogic_support.all; + +package std_ulogic_function_support is + -- Subtypes used for constraining return values in package + subtype std_return_2 is std_ulogic_vector(0 to 1); + subtype std_return_4 is std_ulogic_vector(0 to 3); + subtype std_return_8 is std_ulogic_vector(0 to 7); + subtype std_return_16 is std_ulogic_vector(0 to 15); + subtype std_return_32 is std_ulogic_vector(0 to 31); + subtype std_return_64 is std_ulogic_vector(0 to 63); + -- Test Case Evaluation Attributes + -- These attributes are used to control the generation of TCE tests + -- within the VHDL code. + -- Valid on PORT, SIGNAL and LABEL . + + -- Used to turn task model generation on or off. The attribute is applied + -- to a label. If on a block it turns off generation for the whole block. + -- If on a statement it is for that statement alone. + -- The string specifies which task statement alone. + -- attribute TCE_ON of : label is "T,LTP,STP,DLTP,LST,STC,ASSRT,CMBN | ALL" ; + attribute tce_on : string; + attribute tce_off : string; + attribute tce_last : string; + attribute tce_reset : string; + attribute tce_all_off : string; + attribute tce_ignore : string; + -- The string specifies which task statement alone. + attribute tce_assertion : string; + attribute tce_combination : string; + attribute tce_seqcond : string; + + -- Global Signals + signal audit_bit_dump : std_ulogic ; + signal assertion_summary : boolean ; + signal assertion_clock : std_ulogic ; + + -- Synopsys translate_off + component assertion + generic( counted : boolean := false; + Delay : natural := 0; + Duration : natural := 0); + port( + assert_in : in std_ulogic ; + sample : in std_ulogic ; + assert_out : out std_ulogic + ); + end component; + -- Synopsys translate_on + + -- Function Declarations and Attributes + -- Gate Function + function gate + (in0 : std_ulogic_vector; + cond : std_ulogic ) + return std_ulogic_vector ; + -- Synopsys translate_off + attribute btr_name of gate : function is "AND" ; + attribute recursive_synthesis of gate : function is 1 ; + attribute pin_bit_information of gate : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 3 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + -- Dot Functions + function dot_and + (in0 : std_ulogic_vector ) + return std_ulogic ; + -- Synopsys translate_off + attribute btr_name of dot_and : function is "VHDL-DOTA" ; + attribute recursive_synthesis of dot_and : function is 1 ; + attribute pin_bit_information of dot_and : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); + -- Synopsys translate_on + + function dot_or + (in0 : std_ulogic_vector ) + return std_ulogic ; + -- synopsys translate_off + attribute btr_name of dot_or : function is "VHDL-DOTO" ; + attribute recursive_synthesis of dot_or : function is 1 ; + attribute pin_bit_information of dot_or : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); + -- Synopsys translate_on + + function clock_tree_dot + (in0 : std_ulogic_vector ) + return std_ulogic ; + + function clock_tree_dot + (in0 : bit_vector ) + return bit ; + -- Synopsys translate_off + attribute btr_name of clock_tree_dot : function is "VHDL-CDOT" ; + attribute recursive_synthesis of clock_tree_dot : function is 1 ; + attribute pin_bit_information of clock_tree_dot : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); + -- Synopsys translate_on + + -- Generic Terminator + procedure terminator + (in0 : in std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ); + + procedure terminator + (in0 : in std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ); + -- synopsys translate_off + attribute btr_name of terminator : procedure is "TERMINATOR"; + attribute recursive_synthesis of terminator : procedure is 1 ; + attribute pin_bit_information of terminator : procedure is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," ")); + -- Synopsys translate_on + + -- Generic Delay + function delay + (in0 : std_ulogic + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic ; + + function delay + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of delay : function is "IDENT" ; + attribute recursive_synthesis of delay : function is 1 ; + attribute block_data of delay : function is + "SUB_FUNC=/DELAY/LOGIC_STYLE=/DIRECT/" ; + attribute pin_bit_information of delay : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + -- Generic Buffer + function buff + (in0 : std_ulogic + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic ; + + function buff + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of buff : function is "IDENT" ; + attribute recursive_synthesis of buff : function is 1 ; + attribute block_data of buff : function is + "LOGIC_STYLE=/DIRECT/" ; + attribute pin_bit_information of buff : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + -- Invert single bit + function invert + (in0 : std_ulogic + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic ; + -- inverter vectored + function invert + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of invert : function is "NOT" ; + attribute recursive_synthesis of invert : function is 1 ; + attribute pin_bit_information of invert : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + -- Compare single bit + function compare + (in0 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic ; + -- compare multi-bit + function compare + (in0 : std_ulogic_vector; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic ; + -- synopsys translate_off + attribute btr_name of compare : function is "VHDL-COMPARE" ; + attribute recursive_synthesis of compare : function is 1 ; + attribute pin_bit_information of compare : function is + (1 => (" ","A0 ","INCR","PIN_BIT_SCALAR"), + 2 => (" ","M0 ","INCR","PIN_BIT_SCALAR"), + 3 => (" ","PASS "," "," "), + 4 => (" ","PASS "," "," "), + 5 => (" ","EQ ","SAME","PIN_BIT_SCALAR")); + -- Synopsys translate_on + + -- Parity Functions + -- General XOR_Tree Building Parity Function + function parity + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic ; + -- synopsys translate_off + attribute btr_name of parity : function is "XOR" ; + attribute recursive_synthesis of parity : function is 1 ; + attribute pin_bit_information of parity : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); + -- Synopsys translate_on + function parity_map + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic ; + + -- synopsys translate_off + attribute btr_name of parity_map : function is "XOR" ; + attribute recursive_synthesis of parity_map : function is 1 ; + attribute block_data of parity_map : function is + "LOGIC_STYLE=/DIRECT/" ; + attribute pin_bit_information of parity_map : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); + -- Synopsys translate_on + + -- Parity gneration/checking functions + function parity_gen_odd + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic ; + + -- synopsys translate_off + attribute btr_name of parity_gen_odd : function is "XNOR" ; + attribute recursive_synthesis of parity_gen_odd : function is 1; + attribute pin_bit_information of parity_gen_odd : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); + -- Synopsys translate_on + + function parity_gen_even + (in0 : std_ulogic_vector + -- Synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- Synopsys translate_on + ) + return std_ulogic ; + -- Synopsys translate_off + attribute btr_name of parity_gen_even : function is "XOR" ; + attribute recursive_synthesis of parity_gen_even : function is 1; + attribute pin_bit_information of parity_gen_even : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); + -- Synopsys translate_on + + function is_parity_odd + (in0 : std_ulogic_vector + -- Synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- Synopsys translate_on + ) + return std_ulogic ; + -- Synopsys translate_off + attribute btr_name of is_parity_odd : function is "XOR" ; + attribute recursive_synthesis of is_parity_odd : function is 1; + attribute pin_bit_information of is_parity_odd : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); + -- Synopsys translate_on + + function is_parity_even + (in0 : std_ulogic_vector + -- Synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- Synopsys translate_on + ) + return std_ulogic ; + -- Synopsys translate_off + attribute btr_name of is_parity_even : function is "XNOR" ; + attribute recursive_synthesis of is_parity_even : function is 1; + attribute pin_bit_information of is_parity_even : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); + -- Synopsys translate_on + + -- Full Adder + procedure full_add + (add_1 : in std_ulogic ; + add_2 : in std_ulogic ; + cryin : in std_ulogic ; + signal sum : out std_ulogic ; + signal carry : out std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ); + procedure full_add + (add_1 : in std_ulogic_vector ; + add_2 : in std_ulogic_vector ; + cryin : in std_ulogic_vector ; + signal sum : out std_ulogic_vector ; + signal carry : out std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ); + -- synopsys translate_off + attribute btr_name of full_add : procedure is "VHDL-FA"; + attribute recursive_synthesis of full_add : procedure is 1 ; + attribute pin_bit_information of full_add : procedure is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","CIN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","SUM ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","COUT ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," ")); + -- Synopsys translate_on + + -- Ripple Adder function + procedure ripple_adder + (add_1 : in std_ulogic_vector ; + add_2 : in std_ulogic_vector ; + signal sum : out std_ulogic_vector ; + signal carry : out std_ulogic ) ; + + procedure ripple_adder + (add_1 : in std_ulogic_vector ; + add_2 : in std_ulogic_vector ; + signal sum : out std_ulogic_vector ); + + -- Generic Tie Blocks + function tie_0 + -- synopsys translate_off + (btr : in string :="" + ;blkdata : in string :="" + ) + -- synopsys translate_on + return std_ulogic ; + -- synopsys translate_off + attribute btr_name of tie_0 : function is "VHDL-TIDN" ; + attribute recursive_synthesis of tie_0 : function is 1 ; + attribute block_data of tie_0 : function is + "LOGIC_STYLE=/DIRECT/" ; + attribute pin_bit_information of tie_0 : function is + (1 => (" ","PASS "," "," "), + 2 => (" ","PASS "," "," "), + 3 => (" ","ZERO ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function vector_tie_0 + (width : integer := 1 + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of vector_tie_0 : function is "VHDL-TIDN" ; + attribute recursive_synthesis of vector_tie_0 : function is 1 ; + attribute block_data of vector_tie_0 : function is + "LOGIC_STYLE=/DIRECT/" ; + attribute pin_bit_information of vector_tie_0 : function is + (1 => (" ","IGNR "," "," "), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","ZERO ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function tie_1 + -- synopsys translate_off + (btr : in string :="" + ;blkdata : in string :="" + ) + -- synopsys translate_on + return std_ulogic ; + -- synopsys translate_off + attribute btr_name of tie_1 : function is "VHDL-TIUP" ; + attribute recursive_synthesis of tie_1 : function is 1 ; + attribute block_data of tie_1 : function is + "LOGIC_STYLE=/DIRECT/" ; + attribute pin_bit_information of tie_1 : function is + (1 => (" ","PASS "," "," "), + 2 => (" ","PASS "," "," "), + 3 => (" ","ONE ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function vector_tie_1 + (width : integer := 1 + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of vector_tie_1 : function is "VHDL-TIUP" ; + attribute recursive_synthesis of vector_tie_1 : function is 1 ; + attribute block_data of vector_tie_1 : function is + "LOGIC_STYLE=/DIRECT/" ; + attribute pin_bit_information of vector_tie_1 : function is + (1 => (" ","IGNR "," "," "), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","ONE ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function reverse + (arg: std_ulogic_vector) + return std_ulogic_vector ; + + function and_reduce + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic ; + -- synopsys translate_off + attribute btr_name of and_reduce : function is "AND" ; + attribute recursive_synthesis of and_reduce : function is 1 ; + attribute pin_bit_information of and_reduce : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); + -- Synopsys translate_on + + function or_reduce + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic ; + -- synopsys translate_off + attribute btr_name of or_reduce : function is "OR" ; + attribute recursive_synthesis of or_reduce : function is 1 ; + attribute pin_bit_information of or_reduce : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); + -- Synopsys translate_on + + function nand_reduce + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic ; + -- synopsys translate_off + attribute btr_name of nand_reduce : function is "NAND" ; + attribute recursive_synthesis of nand_reduce : function is 1 ; + attribute pin_bit_information of nand_reduce : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); + -- Synopsys translate_on + + function nor_reduce + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic ; + -- synopsys translate_off + attribute btr_name of nor_reduce : function is "NOR" ; + attribute recursive_synthesis of nor_reduce : function is 1 ; + attribute pin_bit_information of nor_reduce : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); + -- Synopsys translate_on + + function xor_reduce + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic ; + -- synopsys translate_off + attribute btr_name of xor_reduce : function is "XOR" ; + attribute recursive_synthesis of xor_reduce : function is 1 ; + attribute pin_bit_information of xor_reduce : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); + -- Synopsys translate_on + + function xnor_reduce + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic ; + -- synopsys translate_off + attribute btr_name of xnor_reduce : function is "XNOR" ; + attribute recursive_synthesis of xnor_reduce : function is 1 ; + attribute pin_bit_information of xnor_reduce : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); + -- Synopsys translate_on + + -- Vector of gating bits gating a single vector of data bits + function gate_and + (gate : std_ulogic_vector; + in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + function gate_and + (gate : std_ulogic ; + in0 : std_ulogic + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic ; + function gate_and + (gate : std_ulogic ; + in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_and : function is "AND" ; + attribute recursive_synthesis of gate_and : function is 1 ; + attribute pin_bit_information of gate_and : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","PASS "," "," "), + 4 => (" ","PASS "," "," "), + 5 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function gate_or + (gate : std_ulogic_vector; + in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + function gate_or + (gate : std_ulogic ; + in0 : std_ulogic + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic ; + function gate_or + (gate : std_ulogic ; + in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_or : function is "OR" ; + attribute recursive_synthesis of gate_or : function is 1 ; + attribute pin_bit_information of gate_or : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","PASS "," "," "), + 4 => (" ","PASS "," "," "), + 5 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function gate_nand + (gate : std_ulogic_vector; + in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + function gate_nand + (gate : std_ulogic ; + in0 : std_ulogic + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic ; + function gate_nand + (gate : std_ulogic ; + in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_nand : function is "NAND" ; + attribute recursive_synthesis of gate_nand : function is 1 ; + attribute pin_bit_information of gate_nand : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","PASS "," "," "), + 4 => (" ","PASS "," "," "), + 5 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function gate_nor + (gate : std_ulogic_vector; + in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + function gate_nor + (gate : std_ulogic ; + in0 : std_ulogic + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic ; + function gate_nor + (gate : std_ulogic ; + in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_nor : function is "NOR" ; + attribute recursive_synthesis of gate_nor : function is 1 ; + attribute pin_bit_information of gate_nor : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","PASS "," "," "), + 4 => (" ","PASS "," "," "), + 5 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function gate_xor + (gate : std_ulogic ; + in0 : std_ulogic + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic ; + function gate_xor + (gate : std_ulogic ; + in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_xor : function is "XOR" ; + attribute recursive_synthesis of gate_xor : function is 1 ; + attribute pin_bit_information of gate_xor : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","PASS "," "," "), + 4 => (" ","PASS "," "," "), + 5 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function gate_xnor + (gate : std_ulogic ; + in0 : std_ulogic + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic ; + function gate_xnor + (gate : std_ulogic ; + in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_xnor : function is "XNOR" ; + attribute recursive_synthesis of gate_xnor : function is 1 ; + attribute pin_bit_information of gate_xnor : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","PASS "," "," "), + 4 => (" ","PASS "," "," "), + 5 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + -- Vectored primitive 2 input functions + -- Single bit case + -- Multiple vectors logically ed bitwise + function and_2 + (in0 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function and_2 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of and_2 : function is "AND" ; + attribute recursive_synthesis of and_2 : function is 1 ; + attribute pin_bit_information of and_2 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","PASS "," "," "), + 4 => (" ","PASS "," "," "), + 5 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function or_2 + (in0 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function or_2 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of or_2 : function is "OR" ; + attribute recursive_synthesis of or_2 : function is 1 ; + attribute pin_bit_information of or_2 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","PASS "," "," "), + 4 => (" ","PASS "," "," "), + 5 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function nand_2 + (in0 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function nand_2 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of nand_2 : function is "NAND" ; + attribute recursive_synthesis of nand_2 : function is 1 ; + attribute pin_bit_information of nand_2 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","PASS "," "," "), + 4 => (" ","PASS "," "," "), + 5 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function nor_2 + (in0 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function nor_2 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of nor_2 : function is "NOR" ; + attribute recursive_synthesis of nor_2 : function is 1 ; + attribute pin_bit_information of nor_2 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","PASS "," "," "), + 4 => (" ","PASS "," "," "), + 5 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function xor_2 + (in0 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function xor_2 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of xor_2 : function is "XOR" ; + attribute recursive_synthesis of xor_2 : function is 1 ; + attribute pin_bit_information of xor_2 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","PASS "," "," "), + 4 => (" ","PASS "," "," "), + 5 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function xnor_2 + (in0 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function xnor_2 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of xnor_2 : function is "XNOR" ; + attribute recursive_synthesis of xnor_2 : function is 1 ; + attribute pin_bit_information of xnor_2 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","PASS "," "," "), + 4 => (" ","PASS "," "," "), + 5 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + -- Vectored primitive 3 input functions + -- Single bit case + function and_3 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + -- multiple vectors logically ed bitwise + function and_3 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of and_3 : function is "AND" ; + attribute recursive_synthesis of and_3 : function is 1 ; + attribute pin_bit_information of and_3 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","PASS "," "," "), + 5 => (" ","PASS "," "," "), + 6 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function or_3 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function or_3 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of or_3 : function is "OR" ; + attribute recursive_synthesis of or_3 : function is 1 ; + attribute pin_bit_information of or_3 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","PASS "," "," "), + 5 => (" ","PASS "," "," "), + 6 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function nand_3 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function nand_3 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of nand_3 : function is "NAND" ; + attribute recursive_synthesis of nand_3 : function is 1 ; + attribute pin_bit_information of nand_3 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","PASS "," "," "), + 5 => (" ","PASS "," "," "), + 6 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function nor_3 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function nor_3 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of nor_3 : function is "NOR" ; + attribute recursive_synthesis of nor_3 : function is 1 ; + attribute pin_bit_information of nor_3 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","PASS "," "," "), + 5 => (" ","PASS "," "," "), + 6 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function xor_3 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function xor_3 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of xor_3 : function is "XOR" ; + attribute recursive_synthesis of xor_3 : function is 1 ; + attribute pin_bit_information of xor_3 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","PASS "," "," "), + 5 => (" ","PASS "," "," "), + 6 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function xnor_3 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function xnor_3 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of xnor_3 : function is "XNOR" ; + attribute recursive_synthesis of xnor_3 : function is 1 ; + attribute pin_bit_information of xnor_3 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","PASS "," "," "), + 5 => (" ","PASS "," "," "), + 6 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + -- Vectored primitive 4 input functions + -- Single bit case + function and_4 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function and_4 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of and_4 : function is "AND" ; + attribute recursive_synthesis of and_4 : function is 1 ; + attribute pin_bit_information of and_4 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function or_4 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function or_4 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of or_4 : function is "OR" ; + attribute recursive_synthesis of or_4 : function is 1 ; + attribute pin_bit_information of or_4 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function nand_4 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function nand_4 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of nand_4 : function is "NAND" ; + attribute recursive_synthesis of nand_4 : function is 1 ; + attribute pin_bit_information of nand_4 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function nor_4 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function nor_4 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of nor_4 : function is "NOR" ; + attribute recursive_synthesis of nor_4 : function is 1 ; + attribute pin_bit_information of nor_4 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + -- Vectored primitive 5 input functions + -- Single bit case + -- Multiple vectors logically ed bitwise + function and_5 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function and_5 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of and_5 : function is "AND" ; + attribute recursive_synthesis of and_5 : function is 1 ; + attribute pin_bit_information of and_5 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function or_5 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function or_5 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of or_5 : function is "OR" ; + attribute recursive_synthesis of or_5 : function is 1 ; + attribute pin_bit_information of or_5 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function nand_5 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function nand_5 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of nand_5 : function is "NAND" ; + attribute recursive_synthesis of nand_5 : function is 1 ; + attribute pin_bit_information of nand_5 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function nor_5 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function nor_5 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of nor_5 : function is "NOR" ; + attribute recursive_synthesis of nor_5 : function is 1 ; + attribute pin_bit_information of nor_5 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + -- Vectored primitive 6 input functions + -- Single bit case + function and_6 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function and_6 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of and_6 : function is "AND" ; + attribute recursive_synthesis of and_6 : function is 1 ; + attribute pin_bit_information of and_6 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function or_6 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function or_6 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of or_6 : function is "OR" ; + attribute recursive_synthesis of or_6 : function is 1 ; + attribute pin_bit_information of or_6 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function nand_6 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function nand_6 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of nand_6 : function is "NAND" ; + attribute recursive_synthesis of nand_6 : function is 1 ; + attribute pin_bit_information of nand_6 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function nor_6 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function nor_6 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of nor_6 : function is "NOR" ; + attribute recursive_synthesis of nor_6 : function is 1 ; + attribute pin_bit_information of nor_6 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + -- Vectored primitive 7 input functions + -- Single bit case + -- Multiple vectors logically ed bitwise + function and_7 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic ; + in6 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function and_7 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector ; + in6 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of and_7 : function is "AND" ; + attribute recursive_synthesis of and_7 : function is 1 ; + attribute pin_bit_information of and_7 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","PASS "," "," "), + 9 => (" ","PASS "," "," "), + 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function or_7 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic ; + in6 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function or_7 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector ; + in6 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of or_7 : function is "OR" ; + attribute recursive_synthesis of or_7 : function is 1 ; + attribute pin_bit_information of or_7 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","PASS "," "," "), + 9 => (" ","PASS "," "," "), + 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function nand_7 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic ; + in6 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function nand_7 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector ; + in6 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of nand_7 : function is "NAND" ; + attribute recursive_synthesis of nand_7 : function is 1 ; + attribute pin_bit_information of nand_7 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","PASS "," "," "), + 9 => (" ","PASS "," "," "), + 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function nor_7 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic ; + in6 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function nor_7 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector ; + in6 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of nor_7 : function is "NOR" ; + attribute recursive_synthesis of nor_7 : function is 1 ; + attribute pin_bit_information of nor_7 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","PASS "," "," "), + 9 => (" ","PASS "," "," "), + 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + -- Vectored primitive 8 input functions + -- Single bit case + -- Multiple vectors logically ed bitwise + function and_8 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic ; + in6 : std_ulogic ; + in7 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function and_8 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector ; + in6 : std_ulogic_vector ; + in7 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of and_8 : function is "AND" ; + attribute recursive_synthesis of and_8 : function is 1 ; + attribute pin_bit_information of and_8 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function or_8 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic ; + in6 : std_ulogic ; + in7 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function or_8 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector ; + in6 : std_ulogic_vector ; + in7 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of or_8 : function is "OR" ; + attribute recursive_synthesis of or_8 : function is 1 ; + attribute pin_bit_information of or_8 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function nand_8 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic ; + in6 : std_ulogic ; + in7 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function nand_8 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector ; + in6 : std_ulogic_vector ; + in7 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of nand_8 : function is "NAND" ; + attribute recursive_synthesis of nand_8 : function is 1 ; + attribute pin_bit_information of nand_8 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function nor_8 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic ; + in6 : std_ulogic ; + in7 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function nor_8 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector ; + in6 : std_ulogic_vector ; + in7 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of nor_8 : function is "NOR" ; + attribute recursive_synthesis of nor_8 : function is 1 ; + attribute pin_bit_information of nor_8 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function decode( code : std_ulogic_vector ) return std_ulogic_vector; + -- Synopsys translate_off + attribute functionality of decode: function is "DECODER"; + -- Synopsys translate_on + + function decode_2to4 + (code : std_ulogic_vector(0 to 1) + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_return_4 ; + -- synopsys translate_off + attribute btr_name of decode_2to4 : function is "VHDL-DECODE"; + attribute recursive_synthesis of decode_2to4 : function is 1 ; + attribute pin_bit_information of decode_2to4 : function is + (1 => (" ","D1 ","DECR","PIN_BIT_SCALAR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","F0 ","INCR","PIN_BIT_SCALAR")); + -- Synopsys translate_on + + function decode_3to8 + (code : std_ulogic_vector(0 to 2) + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_return_8 ; + -- synopsys translate_off + attribute btr_name of decode_3to8 : function is "VHDL-DECODE"; + attribute recursive_synthesis of decode_3to8 : function is 1 ; + attribute pin_bit_information of decode_3to8 : function is + (1 => (" ","D2 ","DECR","PIN_BIT_SCALAR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","F0 ","INCR","PIN_BIT_SCALAR")); + -- Synopsys translate_on + + function decode_4to16 + (code : std_ulogic_vector(0 to 3) + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_return_16 ; + -- synopsys translate_off + attribute btr_name of decode_4to16 : function is "VHDL-DECODE"; + attribute recursive_synthesis of decode_4to16 : function is 1 ; + attribute pin_bit_information of decode_4to16 : function is + (1 => (" ","D3 ","DECR","PIN_BIT_SCALAR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","F0 ","INCR","PIN_BIT_SCALAR")); + -- Synopsys translate_on + + function decode_5to32 + (code : std_ulogic_vector(0 to 4) + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_return_32 ; + -- synopsys translate_off + attribute btr_name of decode_5to32 : function is "VHDL-DECODE"; + attribute recursive_synthesis of decode_5to32 : function is 1 ; + attribute pin_bit_information of decode_5to32 : function is + (1 => (" ","D4 ","DECR","PIN_BIT_SCALAR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","F0 ","INCR","PIN_BIT_SCALAR")); + -- Synopsys translate_on + + function decode_6to64 + (code : std_ulogic_vector(0 to 5) + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_return_64 ; + -- synopsys translate_off + attribute btr_name of decode_6to64 : function is "VHDL-DECODE"; + attribute recursive_synthesis of decode_6to64 : function is 1 ; + attribute pin_bit_information of decode_6to64 : function is + (1 => (" ","D5 ","DECR","PIN_BIT_SCALAR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","F0 ","INCR","PIN_BIT_SCALAR")); + -- Synopsys translate_on + +end std_ulogic_function_support; + +package body std_ulogic_function_support is + -- Function Declarations and Attributes + -- Gate Function + function gate + (in0 : std_ulogic_vector; + cond : std_ulogic ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + subtype vec_length is std_ulogic_vector(0 to in0'length-1); + begin + result := in0 and vec_length'(0 to in0'length-1 => cond) ; + return result; + end gate; + + -- This function everses the range direction. + function reverse (arg: std_ulogic_vector) + return std_ulogic_vector + is + variable d, result : std_ulogic_vector(0 to arg'length-1); + begin + d := arg; + for i in 0 to d'length-1 loop + result(result'right - i) := d(i); + end loop; + return result; + end reverse; + + -- Generic Terminator + procedure terminator + (in0 : in std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- Synopsys translate_on + begin + result := in0 ; + end terminator ; + + procedure terminator + (in0 : in std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1); + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 ; + end terminator ; + + -- Generic Delay + function delay + (in0 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + -- initialize variable attribute values + result := in0; + return result; + end delay ; + + function delay + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0; + return result; + end delay ; + + function buff + (in0 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0; + return result; + end buff ; + + function buff + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0; + return result; + end buff ; + +-- inverter single bit + function invert + (in0 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not in0; + return result; + end invert ; + + -- inverter vectored + function invert + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not in0; + return result; + end invert ; + + -- Comparator + function compare + (in0 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 = in1 ; + return result; + end compare ; + +-- comparator mult-bit + function compare + (in0 : std_ulogic_vector; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 = in1 ; + return result; + end compare ; + + -- General XOR_Tree Building Parity Function + function parity + (In0 : std_ulogic_vector + -- Synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- Synopsys translate_on + ) + return Std_uLogic + is + -- Synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- Synopsys translate_on + variable result : std_ulogic; + begin + result := in0(in0'low); + for i in in0'low+1 to in0'high loop + result := in0(i) xor result ; + end loop; + return result; + end parity ; + + -- Specific Size Parity Block Map Function + function parity_map + (In0 : std_ulogic_vector + -- Synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- Synopsys translate_on + ) + return std_ulogic + is + -- Synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- Synopsys translate_on + variable result : std_ulogic; + begin + result := in0(in0'low); + for i in in0'low+1 to in0'high loop + result := in0(i) xor result ; + end loop; + return result; + end parity_map ; + +-- Parity gneration/checking functions + function parity_gen_odd + (in0 : std_ulogic_vector + -- Synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- Synopsys translate_on + ) + return std_ulogic + is + -- Synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- Synopsys translate_on + variable result : std_ulogic; + begin + result := in0(in0'low); + for i in in0'low+1 to in0'high loop + result := in0(i) xor result ; + end loop; + return not result; + end parity_gen_odd ; + + function parity_gen_even + (in0 : std_ulogic_vector + -- Synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- Synopsys translate_on + ) + return std_ulogic + is + -- Synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- Synopsys translate_on + variable result : std_ulogic; + begin + result := in0(in0'low); + for i in in0'low+1 to in0'high loop + result := in0(i) xor result ; + end loop; + return result; + end parity_gen_even ; + + function is_parity_odd + (in0 : std_ulogic_vector + -- Synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- Synopsys translate_on + ) + return std_ulogic + is + -- Synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- Synopsys translate_on + variable result : std_ulogic; + begin + result := in0(in0'low); + for i in in0'low+1 to in0'high loop + result := in0(i) xor result ; + end loop; + return result; + end is_parity_odd ; + + function is_parity_even + (in0 : std_ulogic_vector + -- Synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- Synopsys translate_on + ) + return std_ulogic + is + -- Synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- Synopsys translate_on + variable result : std_ulogic; + begin + result := in0(in0'low); + for i in in0'low+1 to in0'high loop + result := in0(i) xor result ; + end loop; + return not result; + end is_parity_even ; + + function and_reduce + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0(in0'left) ; + for i in in0'range loop + result := result and in0(i); + end loop; + result := result ; + return result; + end and_reduce ; + + function or_reduce + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0(in0'left) ; + for i in in0'range loop + result := result or in0(i); + end loop; + result := result ; + return result; + end or_reduce ; + + function nand_reduce + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0(in0'left) ; + for i in in0'range loop + result := result and in0(i); + end loop; + result := not result ; + return result; + end nand_reduce ; + + function nor_reduce + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0(in0'left) ; + for i in in0'range loop + result := result or in0(i); + end loop; + result := not result ; + return result; + end nor_reduce ; + + function xor_reduce + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := '0' ; + for i in in0'range loop + result := result xor in0(i); + end loop; + result := result ; + return result ; + end xor_reduce ; + + function xnor_reduce + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := '0' ; + for i in in0'range loop + result := result xor in0(i); + end loop; + result := not result ; + return result ; + end xnor_reduce ; + + function gate_and + (gate : std_ulogic ; + in0 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := gate and in0 ; + return result; + end gate_and; + + function gate_and + (gate : std_ulogic ; + in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + variable result : std_ulogic_vector(0 to in0'length-1); + subtype vec_length is std_ulogic_vector(0 to in0'length-1); + begin + result := in0 and vec_length'(0 to in0'length-1 => gate) ; + return result; + end gate_and; + + function gate_or + (gate : std_ulogic ; + in0 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := gate or in0 ; + return result; + end gate_or; + + function gate_or + (gate : std_ulogic ; + in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + variable result : std_ulogic_vector(0 to in0'length-1); + subtype vec_length is std_ulogic_vector(0 to in0'length-1); + begin + result := in0 or vec_length'(0 to in0'length-1 => gate) ; + return result; + end gate_or; + + function gate_nand + (gate : std_ulogic ; + in0 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := gate nand in0 ; + return result; + end gate_nand; + + function gate_nand + (gate : std_ulogic ; + in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + variable result : std_ulogic_vector(0 to in0'length-1); + subtype vec_length is std_ulogic_vector(0 to in0'length-1); + begin + result := in0 nand vec_length'( 0 to in0'length-1 => gate ); + return result; + end gate_nand; + + function gate_nor + (gate : std_ulogic ; + in0 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := gate nor in0 ; + return result; + end gate_nor; + + function gate_nor + (gate : std_ulogic ; + in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + variable result : std_ulogic_vector(0 to in0'length-1); + subtype vec_length is std_ulogic_vector(0 to in0'length-1); + begin + result := in0 nor vec_length'(0 to in0'length-1 => gate) ; + return result; + end gate_nor; + + function gate_xor + (gate : std_ulogic ; + in0 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := gate xor in0 ; + return result; + end gate_xor; + + function gate_xor + (gate : std_ulogic ; + in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + variable result : std_ulogic_vector(0 to in0'length-1); + subtype vec_length is std_ulogic_vector(0 to in0'length-1); + begin + result := in0 xor vec_length'(0 to in0'length-1 => gate) ; + return result; + end gate_xor; + + function gate_xnor + (gate : std_ulogic ; + in0 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := gate = in0 ; + return result; + end gate_xnor; + + function gate_xnor + (gate : std_ulogic ; + in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + subtype vec_length is std_ulogic_vector(0 to in0'length-1); + begin + result := not( in0 xor vec_length'(0 to in0'length-1 => gate) ) ; + return result; + end gate_xnor; + + function gate_and + (gate : std_ulogic_vector; + in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + variable result : std_ulogic_vector(0 to in0'length-1); + variable gate_int : std_ulogic ; + subtype vec_length is std_ulogic_vector(0 to in0'length-1); + begin + gate_int := gate(gate'low) ; + for i in gate'low+1 to gate'high loop + gate_int := gate_int and gate(i); + end loop; + result := in0 and vec_length'(0 to in0'length-1 => gate_int) ; + return result ; + end gate_and; + + function gate_or + (gate : std_ulogic_vector; + in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + variable result : std_ulogic_vector(0 to in0'length-1); + variable gate_int : std_ulogic ; + subtype vec_length is std_ulogic_vector(0 to in0'length-1); + begin + gate_int := gate(gate'low) ; + for i in gate'low+1 to gate'high loop + gate_int := gate_int or gate(i); + end loop; + result := in0 or vec_length'(0 to in0'length-1 => gate_int) ; + return result ; + end gate_or; + + function gate_nand + (gate : std_ulogic_vector; + in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + variable result : std_ulogic_vector(0 to in0'length-1); + variable gate_int : std_ulogic ; + subtype vec_length is std_ulogic_vector(0 to in0'length-1); + begin + gate_int := gate(gate'low) ; + for i in gate'low+1 to gate'high loop + gate_int := gate_int and gate(i); + end loop; + result := in0 and vec_length'(0 to in0'length-1 => gate_int) ; + result := not result ; + return result; + end gate_nand; + + function gate_nor + (gate : std_ulogic_vector; + in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + variable result : std_ulogic_vector(0 to in0'length-1); + variable gate_int : std_ulogic ; + subtype vec_length is std_ulogic_vector(0 to in0'length-1); + begin + gate_int := gate(gate'low) ; + for i in gate'low+1 to gate'high loop + gate_int := gate_int or gate(i); + end loop; + result := in0 or vec_length'(0 to in0'length-1 => gate_int) ; + result := not result ; + return result ; + end gate_nor; + + function xor_2 + (in0 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 xor in1 ; + return result ; + end xor_2 ; + + function xor_2 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 xor in1; + return result ; + end xor_2 ; + + function xor_3 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := (in0 xor in1 xor in2) ; + return result ; + end xor_3 ; + + function xor_3 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 xor in1 xor in2 ; + return result ; + end xor_3 ; + + function xnor_2 + (in0 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 xor in1 ) ; + return result ; + end xnor_2 ; + + function xnor_2 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 xor in1 ) ; + return result ; + end xnor_2 ; + + function xnor_3 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 xor in1 xor in2 ) ; + return result ; + end xnor_3 ; + + function xnor_3 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 xor in1 xor in2 ) ; + return result ; + end xnor_3 ; + + function and_2 + (in0 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 and in1 ; + return result ; + end and_2 ; + + function and_2 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 and in1 ; + return result ; + end and_2 ; + + function and_3 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 and in1 and in2 ; + return result ; + end and_3 ; + + function and_3 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 and in1 and in2 ; + return result ; + end and_3 ; + + function and_4 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 and in1 and in2 and in3 ; + return result ; + end and_4 ; + + function and_4 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 and in1 and in2 and in3 ; + return result ; + end and_4 ; + + function and_5 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 and in1 and in2 and in3 and in4 ; + return result ; + end and_5 ; + + function and_5 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 and in1 and in2 and in3 and in4; + return result ; + end and_5 ; + + function and_6 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 and in1 and in2 and in3 and in4 and in5 ; + return result ; + end and_6 ; + + function and_6 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 and in1 and in2 and in3 and in4 and in5 ; + return result ; + end and_6 ; + + function and_7 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic ; + in6 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 and in1 and in2 and in3 and in4 and in5 and in6 ; + return result ; + end and_7 ; + + function and_7 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector ; + in6 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 and in1 and in2 and in3 and in4 and in5 and in6 ; + return result ; + end and_7 ; + + function and_8 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic ; + in6 : std_ulogic ; + in7 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 and in1 and in2 and in3 and in4 and in5 and in6 and in7 ; + return result ; + end and_8 ; + + function and_8 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector ; + in6 : std_ulogic_vector ; + in7 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 and in1 and in2 and in3 and in4 and in5 and in6 and in7 ; + return result ; + end and_8 ; + + function or_2 + (in0 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 or in1 ; + return result ; + end or_2 ; + + function or_2 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 or in1 ; + return result ; + end or_2 ; + + function or_3 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 or in1 or in2 ; + return result ; + end or_3 ; + + function or_3 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 or in1 or in2 ; + return result ; + end or_3 ; + + function or_4 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 or in1 or in2 or in3 ; + return result ; + end or_4 ; + + function or_4 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 or in1 or in2 or in3 ; + return result ; + end or_4 ; + + function or_5 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 or in1 or in2 or in3 or in4 ; + return result ; + end or_5 ; + + function or_5 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 or in1 or in2 or in3 or in4 ; + return result ; + end or_5 ; + + function or_6 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 or in1 or in2 or in3 or in4 or in5 ; + return result ; + end or_6 ; + + function or_6 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 or in1 or in2 or in3 or in4 or in5 ; + return result ; + end or_6 ; + + function or_7 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic ; + in6 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 or in1 or in2 or in3 or in4 or in5 or in6 ; + return result ; + end or_7 ; + + function or_7 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector ; + in6 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 or in1 or in2 or in3 or in4 or in5 or in6 ; + return result ; + end or_7 ; + + function or_8 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic ; + in6 : std_ulogic ; + in7 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 or in1 or in2 or in3 or in4 or in5 or in6 or in7 ; + return result ; + end or_8 ; + + function or_8 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector ; + in6 : std_ulogic_vector ; + in7 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 or in1 or in2 or in3 or in4 or in5 or in6 or in7 ; + return result ; + end or_8 ; + + function nand_2 + (in0 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 and in1 ) ; + return result ; + end nand_2 ; + + function nand_2 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 and in1 ) ; + return result ; + end nand_2 ; + + function nand_3 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 and in1 and in2 ) ; + return result ; + end nand_3 ; + + function nand_3 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 and in1 and in2 ) ; + return result ; + end nand_3 ; + + function nand_4 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 and in1 and in2 and in3 ) ; + return result ; + end nand_4 ; + + function nand_4 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 and in1 and in2 and in3 ) ; + return result ; + end nand_4 ; + + function nand_5 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 and in1 and in2 and in3 and in4 ) ; + return result ; + end nand_5 ; + + function nand_5 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 and in1 and in2 and in3 and in4 ) ; + return result ; + end nand_5 ; + + function nand_6 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 and in1 and in2 and in3 and in4 and in5 ) ; + return result ; + end nand_6 ; + + function nand_6 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 and in1 and in2 and in3 and in4 and in5 ) ; + return result ; + end nand_6 ; + + function nand_7 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic ; + in6 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 and in1 and in2 and in3 and in4 and in5 and in6) ; + return result ; + end nand_7 ; + + function nand_7 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector ; + in6 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 and in1 and in2 and in3 and in4 and in5 and in6) ; + return result ; + end nand_7 ; + + function nand_8 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic ; + in6 : std_ulogic ; + in7 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 and in1 and in2 and in3 and in4 and in5 and in6 and in7 ) ; + return result ; + end nand_8 ; + + function nand_8 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector ; + in6 : std_ulogic_vector ; + in7 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 and in1 and in2 and in3 and in4 and in5 and in6 and in7 ) ; + return result ; + end nand_8 ; + + function nor_2 + (in0 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 or in1 ) ; + return result ; + end nor_2 ; + + function nor_2 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 or in1 ) ; + return result ; + end nor_2 ; + + function nor_3 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 or in1 or in2 ) ; + return result ; + end nor_3 ; + + function nor_3 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1) ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 or in1 or in2 ) ; + return result ; + end nor_3 ; + + function nor_4 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 or in1 or in2 or in3 ) ; + return result ; + end nor_4 ; + + function nor_4 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1) ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 or in1 or in2 or in3 ) ; + return result ; + end nor_4 ; + + function nor_5 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 or in1 or in2 or in3 or in4 ) ; + return result ; + end nor_5 ; + + function nor_5 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 or in1 or in2 or in3 or in4 ) ; + return result ; + end nor_5 ; + + function nor_6 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 or in1 or in2 or in3 or in4 or in5 ) ; + return result ; + end nor_6 ; + + function nor_6 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 or in1 or in2 or in3 or in4 or in5 ) ; + return result ; + end nor_6 ; + + function nor_7 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic ; + in6 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 or in1 or in2 or in3 or in4 or in5 or in6 ) ; + return result ; + end nor_7 ; + + function nor_7 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector ; + in6 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 or in1 or in2 or in3 or in4 or in5 or in6 ) ; + return result ; + end nor_7 ; + + function nor_8 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic ; + in6 : std_ulogic ; + in7 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 or in1 or in2 or in3 or in4 or in5 or in6 or in7 ) ; + return result ; + end nor_8 ; + + function nor_8 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector ; + in6 : std_ulogic_vector ; + in7 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 or in1 or in2 or in3 or in4 or in5 or in6 or in7 ) ; + return result ; + end nor_8 ; + + function tie_0 + -- synopsys translate_off + (btr : in string :=""; + blkdata : in string :="" + ) + -- synopsys translate_on + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := '0'; + return result; + end tie_0; + + function vector_tie_0 + (width : integer := 1 + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector(0 to width-1) ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + for i in 0 to width-1 loop + result(i) := '0'; + end loop; + return result; + end vector_tie_0; + + function tie_1 + -- synopsys translate_off + (btr : in string :="" + ;blkdata : in string :="" + ) + -- synopsys translate_on + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := '1'; + return result; + end tie_1; + + function vector_tie_1 + (width : integer := 1 + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector(0 to width-1) ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + for i in 0 to width-1 loop + result(i) := '1'; + end loop; + return result; + end vector_tie_1; + + function decode( code : std_ulogic_vector ) return std_ulogic_vector is + variable result : std_ulogic_vector(0 to (2**(code'length)-1)) := (others => '0'); + begin + result := (others => '0'); + result( tconv( code ) ) := '1'; + for i in code'low to code'high loop + if code(i) = 'U' then + result := (others => 'U'); + end if; + end loop; + for i in code'low to code'high loop + if code(i) = 'X' then + result := (others => 'X'); + end if; + end loop; + return result; + end decode; + + function decode_2to4 + (code : std_ulogic_vector(0 to 1) + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_return_4 + is + variable result : std_ulogic_vector(0 to 3) ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + case code is + when "00" => result := "1000"; + when "01" => result := "0100"; + when "10" => result := "0010"; + when "11" => result := "0001"; + when others => result := "XXXX"; + end case; + return result; + end decode_2to4; + + function decode_3to8 + (code : std_ulogic_vector(0 to 2) + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_return_8 + is + variable result : std_ulogic_vector(0 to 7) ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + case code is + when "000" => result := "10000000"; + when "001" => result := "01000000"; + when "010" => result := "00100000"; + when "011" => result := "00010000"; + when "100" => result := "00001000"; + when "101" => result := "00000100"; + when "110" => result := "00000010"; + when "111" => result := "00000001"; + when others => result := "XXXXXXXX"; + end case; + return result; + end decode_3to8; + + function decode_4to16 + (code : std_ulogic_vector(0 to 3) + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_return_16 + is + variable result : std_ulogic_vector(0 to 15) ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + case code is + when "0000" => result := "1000000000000000"; + when "0001" => result := "0100000000000000"; + when "0010" => result := "0010000000000000"; + when "0011" => result := "0001000000000000"; + when "0100" => result := "0000100000000000"; + when "0101" => result := "0000010000000000"; + when "0110" => result := "0000001000000000"; + when "0111" => result := "0000000100000000"; + when "1000" => result := "0000000010000000"; + when "1001" => result := "0000000001000000"; + when "1010" => result := "0000000000100000"; + when "1011" => result := "0000000000010000"; + when "1100" => result := "0000000000001000"; + when "1101" => result := "0000000000000100"; + when "1110" => result := "0000000000000010"; + when "1111" => result := "0000000000000001"; + when others => result := "XXXXXXXXXXXXXXXX"; + end case; + return result; + end decode_4to16; + + function decode_5to32 + (code : std_ulogic_vector(0 to 4) + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_return_32 + is + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + variable result : std_ulogic_vector(0 to 31) ; + begin + case code is + when "00000" => result := "10000000000000000000000000000000"; + when "00001" => result := "01000000000000000000000000000000"; + when "00010" => result := "00100000000000000000000000000000"; + when "00011" => result := "00010000000000000000000000000000"; + when "00100" => result := "00001000000000000000000000000000"; + when "00101" => result := "00000100000000000000000000000000"; + when "00110" => result := "00000010000000000000000000000000"; + when "00111" => result := "00000001000000000000000000000000"; + when "01000" => result := "00000000100000000000000000000000"; + when "01001" => result := "00000000010000000000000000000000"; + when "01010" => result := "00000000001000000000000000000000"; + when "01011" => result := "00000000000100000000000000000000"; + when "01100" => result := "00000000000010000000000000000000"; + when "01101" => result := "00000000000001000000000000000000"; + when "01110" => result := "00000000000000100000000000000000"; + when "01111" => result := "00000000000000010000000000000000"; + when "10000" => result := "00000000000000001000000000000000"; + when "10001" => result := "00000000000000000100000000000000"; + when "10010" => result := "00000000000000000010000000000000"; + when "10011" => result := "00000000000000000001000000000000"; + when "10100" => result := "00000000000000000000100000000000"; + when "10101" => result := "00000000000000000000010000000000"; + when "10110" => result := "00000000000000000000001000000000"; + when "10111" => result := "00000000000000000000000100000000"; + when "11000" => result := "00000000000000000000000010000000"; + when "11001" => result := "00000000000000000000000001000000"; + when "11010" => result := "00000000000000000000000000100000"; + when "11011" => result := "00000000000000000000000000010000"; + when "11100" => result := "00000000000000000000000000001000"; + when "11101" => result := "00000000000000000000000000000100"; + when "11110" => result := "00000000000000000000000000000010"; + when "11111" => result := "00000000000000000000000000000001"; + when others => result := "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; + end case; + return result; + end decode_5to32; + + function decode_6to64 + (code : std_ulogic_vector(0 to 5) + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_return_64 + is + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + variable result : std_ulogic_vector(0 to 63) ; + begin + case code is + when "000000" => result := "1000000000000000000000000000000000000000000000000000000000000000"; + when "000001" => result := "0100000000000000000000000000000000000000000000000000000000000000"; + when "000010" => result := "0010000000000000000000000000000000000000000000000000000000000000"; + when "000011" => result := "0001000000000000000000000000000000000000000000000000000000000000"; + when "000100" => result := "0000100000000000000000000000000000000000000000000000000000000000"; + when "000101" => result := "0000010000000000000000000000000000000000000000000000000000000000"; + when "000110" => result := "0000001000000000000000000000000000000000000000000000000000000000"; + when "000111" => result := "0000000100000000000000000000000000000000000000000000000000000000"; + when "001000" => result := "0000000010000000000000000000000000000000000000000000000000000000"; + when "001001" => result := "0000000001000000000000000000000000000000000000000000000000000000"; + when "001010" => result := "0000000000100000000000000000000000000000000000000000000000000000"; + when "001011" => result := "0000000000010000000000000000000000000000000000000000000000000000"; + when "001100" => result := "0000000000001000000000000000000000000000000000000000000000000000"; + when "001101" => result := "0000000000000100000000000000000000000000000000000000000000000000"; + when "001110" => result := "0000000000000010000000000000000000000000000000000000000000000000"; + when "001111" => result := "0000000000000001000000000000000000000000000000000000000000000000"; + when "010000" => result := "0000000000000000100000000000000000000000000000000000000000000000"; + when "010001" => result := "0000000000000000010000000000000000000000000000000000000000000000"; + when "010010" => result := "0000000000000000001000000000000000000000000000000000000000000000"; + when "010011" => result := "0000000000000000000100000000000000000000000000000000000000000000"; + when "010100" => result := "0000000000000000000010000000000000000000000000000000000000000000"; + when "010101" => result := "0000000000000000000001000000000000000000000000000000000000000000"; + when "010110" => result := "0000000000000000000000100000000000000000000000000000000000000000"; + when "010111" => result := "0000000000000000000000010000000000000000000000000000000000000000"; + when "011000" => result := "0000000000000000000000001000000000000000000000000000000000000000"; + when "011001" => result := "0000000000000000000000000100000000000000000000000000000000000000"; + when "011010" => result := "0000000000000000000000000010000000000000000000000000000000000000"; + when "011011" => result := "0000000000000000000000000001000000000000000000000000000000000000"; + when "011100" => result := "0000000000000000000000000000100000000000000000000000000000000000"; + when "011101" => result := "0000000000000000000000000000010000000000000000000000000000000000"; + when "011110" => result := "0000000000000000000000000000001000000000000000000000000000000000"; + when "011111" => result := "0000000000000000000000000000000100000000000000000000000000000000"; + when "100000" => result := "0000000000000000000000000000000010000000000000000000000000000000"; + when "100001" => result := "0000000000000000000000000000000001000000000000000000000000000000"; + when "100010" => result := "0000000000000000000000000000000000100000000000000000000000000000"; + when "100011" => result := "0000000000000000000000000000000000010000000000000000000000000000"; + when "100100" => result := "0000000000000000000000000000000000001000000000000000000000000000"; + when "100101" => result := "0000000000000000000000000000000000000100000000000000000000000000"; + when "100110" => result := "0000000000000000000000000000000000000010000000000000000000000000"; + when "100111" => result := "0000000000000000000000000000000000000001000000000000000000000000"; + when "101000" => result := "0000000000000000000000000000000000000000100000000000000000000000"; + when "101001" => result := "0000000000000000000000000000000000000000010000000000000000000000"; + when "101010" => result := "0000000000000000000000000000000000000000001000000000000000000000"; + when "101011" => result := "0000000000000000000000000000000000000000000100000000000000000000"; + when "101100" => result := "0000000000000000000000000000000000000000000010000000000000000000"; + when "101101" => result := "0000000000000000000000000000000000000000000001000000000000000000"; + when "101110" => result := "0000000000000000000000000000000000000000000000100000000000000000"; + when "101111" => result := "0000000000000000000000000000000000000000000000010000000000000000"; + when "110000" => result := "0000000000000000000000000000000000000000000000001000000000000000"; + when "110001" => result := "0000000000000000000000000000000000000000000000000100000000000000"; + when "110010" => result := "0000000000000000000000000000000000000000000000000010000000000000"; + when "110011" => result := "0000000000000000000000000000000000000000000000000001000000000000"; + when "110100" => result := "0000000000000000000000000000000000000000000000000000100000000000"; + when "110101" => result := "0000000000000000000000000000000000000000000000000000010000000000"; + when "110110" => result := "0000000000000000000000000000000000000000000000000000001000000000"; + when "110111" => result := "0000000000000000000000000000000000000000000000000000000100000000"; + when "111000" => result := "0000000000000000000000000000000000000000000000000000000010000000"; + when "111001" => result := "0000000000000000000000000000000000000000000000000000000001000000"; + when "111010" => result := "0000000000000000000000000000000000000000000000000000000000100000"; + when "111011" => result := "0000000000000000000000000000000000000000000000000000000000010000"; + when "111100" => result := "0000000000000000000000000000000000000000000000000000000000001000"; + when "111101" => result := "0000000000000000000000000000000000000000000000000000000000000100"; + when "111110" => result := "0000000000000000000000000000000000000000000000000000000000000010"; + when "111111" => result := "0000000000000000000000000000000000000000000000000000000000000001"; + when others => result := "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; + end case; + return result; + end decode_6to64; + +-- full adder function + procedure full_add + (add_1 : in std_ulogic ; + add_2 : in std_ulogic ; + cryin : in std_ulogic ; + signal sum : out std_ulogic ; + signal carry : out std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + is + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + sum <= add_1 xor add_2 xor cryin; + carry <= (add_1 and add_2) or + (add_1 and cryin) or + (add_2 and cryin); + end full_add; + + procedure full_add + (add_1 : in std_ulogic_vector ; + add_2 : in std_ulogic_vector ; + cryin : in std_ulogic_vector ; + signal sum : out std_ulogic_vector ; + signal carry : out std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + is + variable sum_result : std_ulogic_vector(sum'range) ; + variable carry_result : std_ulogic_vector(carry'range) ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + -- synopsys translate_off + assert (add_1'length = add_2'length) + report "Addends of Full_Add are not the same length." + severity error; + assert (add_1'length = cryin'length) and (add_2'length = cryin'length) + report "Addends of Full_Add are not the same length as the CryIn." + severity error; + -- synopsys translate_on + sum_result := add_1 xor add_2 xor cryin; + carry_result := (add_1 and add_2) or + (add_1 and cryin) or + (add_2 and cryin); + sum <= sum_result ; + carry <= carry_result ; + end full_add; + + -- Ripple adder function + procedure ripple_adder + ( add_1 : in std_ulogic_vector ; + add_2 : in std_ulogic_vector ; + signal sum : out std_ulogic_vector ; + signal carry : out std_ulogic ) + is + -- Synopsys translate_off + attribute unroll_loop : boolean; + attribute unroll_loop of ripple : label is true; + -- Synopsys translate_on + variable a : std_ulogic_vector(1 to add_1'length) ; + variable b : std_ulogic_vector(1 to add_2'length) ; + variable c : std_ulogic_vector(0 to add_1'length) ; + variable result : std_ulogic_vector(1 to add_1'length) ; + begin + a := add_1; + b := add_2; + c(c'right) := '0' ; + ripple:for i in result'right downto 1 loop + c(i-1) := ( c(i) and a(i) ) or + ( c(i) and b(i) ) or + ( a(i) and b(i) ) ; + result(i) := a(i) xor b(i) xor c(i) ; + end loop ; + sum <= result ; + carry <= c(c'left) ; + end ripple_adder ; + + procedure ripple_adder + ( add_1 : in std_ulogic_vector ; + add_2 : in std_ulogic_vector ; + signal sum : out std_ulogic_vector ) + is + -- Synopsys translate_off + attribute unroll_loop : boolean; + attribute unroll_loop of ripple : label is true; + -- Synopsys translate_on + variable a : std_ulogic_vector(1 to add_1'length) ; + variable b : std_ulogic_vector(1 to add_2'length) ; + variable c : std_ulogic_vector(1 to add_1'length) ; + variable result : std_ulogic_vector(1 to add_1'length) ; + begin + a := add_1; + b := add_2; + c(c'right) := '0' ; + ripple:for i in result'right downto 2 loop + c(i-1) := ( c(i) and a(i) ) or + ( c(i) and b(i) ) or + ( a(i) and b(i) ) ; + result(i) := a(i) xor b(i) xor c(i) ; + end loop ; + result(1) := a(1) xor b(1) xor c(1) ; + sum <= result ; + end ripple_adder ; + + -- Dot Functions + function dot_and + (in0 : std_ulogic_vector ) + return std_ulogic + is + variable result : std_ulogic ; + begin + result := '1'; + for i in in0'range loop + result := in0(i) and result ; + end loop ; + return result; + end dot_and ; + + function dot_or + (in0 : std_ulogic_vector ) + return std_ulogic + is + variable result : std_ulogic ; + begin + result := '0'; + for i in in0'range loop + result := in0(i) or result ; + end loop ; + return result; + end dot_or ; + + function clock_tree_dot + (in0 : std_ulogic_vector ) + return std_ulogic + is + variable result : std_ulogic ; + begin + result := '1'; + for i in in0'range loop + result := in0(i) and result ; + end loop ; + return result; + end clock_tree_dot ; + + function clock_tree_dot + (in0 : bit_vector ) + return bit + is + variable result : bit ; + begin + result := '1'; + for i in in0'range loop + result := in0(i) and result ; + end loop ; + return result; + end clock_tree_dot ; + +end std_ulogic_function_support; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/ibm/std_ulogic_mux_support.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/ibm/std_ulogic_mux_support.vhdl new file mode 100644 index 0000000..19c0bce --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/ibm/std_ulogic_mux_support.vhdl @@ -0,0 +1,1545 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +--*************************************************************************** +-- Copyright 2020 International Business Machines +-- +-- Licensed under the Apache License, Version 2.0 (the “License”); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- The patent license granted to you in Section 3 of the License, as applied +-- to the “Work,” hereby includes implementations of the Work in physical form. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an “AS IS” BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- +--*************************************************************************** +library ibm,ieee ; +use ieee.std_logic_1164.all ; +use ibm.std_ulogic_support.all; + +package std_ulogic_mux_support is + + -- Multiplexor/Selector Functions + function mux_2to1 + (code : std_ulogic ; + in0 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + + function mux_2to1 + (code : std_ulogic ; + in0 : std_ulogic_vector ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of mux_2to1 : function is "VHDL-MUX" ; + attribute recursive_synthesis of mux_2to1 : function is 1; + attribute pin_bit_information of mux_2to1 : function is + (1 => (" ","S0 ","DECR","PIN_BIT_SCALAR"), + 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","D1 ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","PASS "," "," "), + 5 => (" ","PASS "," "," "), + 6 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function mux_4to1 + (code : std_ulogic_vector(0 to 1) ; + in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + + function mux_4to1 + (code : std_ulogic_vector(0 to 1) ; + in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of mux_4to1 : function is "VHDL-MUX" ; + attribute recursive_synthesis of mux_4to1 : function is 1; + attribute pin_bit_information of mux_4to1 : function is + (1 => (" ","S1 ","DECR","PIN_BIT_SCALAR"), + 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","D1 ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","D2 ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","D3 ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function mux_8to1 + (code : std_ulogic_vector(0 to 2) ; + in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic ; + in6 : std_ulogic ; + in7 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + + function mux_8to1 + (code : std_ulogic_vector(0 to 2) ; + in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector ; + in6 : std_ulogic_vector ; + in7 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of mux_8to1 : function is "VHDL-MUX" ; + attribute recursive_synthesis of mux_8to1 : function is 1; + attribute pin_bit_information of mux_8to1 : function is + (1 => (" ","S2 ","DECR","PIN_BIT_SCALAR"), + 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","D1 ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","D2 ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","D3 ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","D4 ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","D5 ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","D6 ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","D7 ","SAME","PIN_BIT_VECTOR"), + 10 => (" ","PASS "," "," "), + 11 => (" ","PASS "," "," "), + 12 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function not_mux_2to1 + (code : std_ulogic ; + in0 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + + function not_mux_2to1 + (code : std_ulogic ; + in0 : std_ulogic_vector ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of not_mux_2to1 : function is "VHDL-MUX" ; + attribute recursive_synthesis of not_mux_2to1 : function is 1; + attribute pin_bit_information of not_mux_2to1 : function is + (1 => (" ","S0 ","DECR","PIN_BIT_SCALAR"), + 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","D1 ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","PASS "," "," "), + 5 => (" ","PASS "," "," "), + 6 => (" ","INV ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function not_mux_4to1 + (code : std_ulogic_vector(0 to 1) ; + in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + + function not_mux_4to1 + (code : std_ulogic_vector(0 to 1) ; + in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of not_mux_4to1 : function is "VHDL-MUX" ; + attribute recursive_synthesis of not_mux_4to1 : function is 1; + attribute pin_bit_information of not_mux_4to1 : function is + (1 => (" ","S1 ","DECR","PIN_BIT_SCALAR"), + 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","D1 ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","D2 ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","D3 ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","INV ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function not_mux_8to1 + (code : std_ulogic_vector(0 to 2) ; + in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic ; + in6 : std_ulogic ; + in7 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + + function not_mux_8to1 + (code : std_ulogic_vector(0 to 2) ; + in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector ; + in6 : std_ulogic_vector ; + in7 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of not_mux_8to1 : function is "VHDL-MUX" ; + attribute recursive_synthesis of not_mux_8to1 : function is 1; + attribute pin_bit_information of not_mux_8to1 : function is + (1 => (" ","S2 ","DECR","PIN_BIT_SCALAR"), + 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","D1 ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","D2 ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","D3 ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","D4 ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","D5 ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","D6 ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","D7 ","SAME","PIN_BIT_VECTOR"), + 10 => (" ","PASS "," "," "), + 11 => (" ","PASS "," "," "), + 12 => (" ","INV ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + -- Primitive selector input functions + function select_1of2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + + function select_1of2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of select_1of2 : function is "VHDL-SELECT" ; + attribute recursive_synthesis of select_1of2 : function is 1; + attribute pin_bit_information of select_1of2 : function is + (1 => (" ","S0 ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","S1 ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","D1 ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function select_1of3 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + + function select_1of3 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of select_1of3 : function is "VHDL-SELECT" ; + attribute recursive_synthesis of select_1of3 : function is 1; + attribute pin_bit_information of select_1of3 : function is + (1 => (" ","S0 ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","S1 ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","D1 ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","S2 ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","D2 ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function select_1of4 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + + function select_1of4 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of select_1of4 : function is "VHDL-SELECT" ; + attribute recursive_synthesis of select_1of4 : function is 1; + attribute pin_bit_information of select_1of4 : function is + (1 => (" ","S0 ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","S1 ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","D1 ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","S2 ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","D2 ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","S3 ","SAME","PIN_BIT_SCALAR"), + 8 => (" ","D3 ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function select_1of8 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic ; + in3 : std_ulogic ; + gate4 : std_ulogic ; + in4 : std_ulogic ; + gate5 : std_ulogic ; + in5 : std_ulogic ; + gate6 : std_ulogic ; + in6 : std_ulogic ; + gate7 : std_ulogic ; + in7 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + + function select_1of8 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic ; + in3 : std_ulogic_vector ; + gate4 : std_ulogic ; + in4 : std_ulogic_vector ; + gate5 : std_ulogic ; + in5 : std_ulogic_vector ; + gate6 : std_ulogic ; + in6 : std_ulogic_vector ; + gate7 : std_ulogic ; + in7 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of select_1of8 : function is "VHDL-SELECT" ; + attribute recursive_synthesis of select_1of8 : function is 1; + attribute pin_bit_information of select_1of8 : function is + (1 => (" ","S0 ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","S1 ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","D1 ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","S2 ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","D2 ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","S3 ","SAME","PIN_BIT_SCALAR"), + 8 => (" ","D3 ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","S4 ","SAME","PIN_BIT_SCALAR"), + 10 => (" ","D4 ","SAME","PIN_BIT_VECTOR"), + 11 => (" ","S5 ","SAME","PIN_BIT_SCALAR"), + 12 => (" ","D5 ","SAME","PIN_BIT_VECTOR"), + 13 => (" ","S6 ","SAME","PIN_BIT_SCALAR"), + 14 => (" ","D6 ","SAME","PIN_BIT_VECTOR"), + 15 => (" ","S7 ","SAME","PIN_BIT_SCALAR"), + 16 => (" ","D7 ","SAME","PIN_BIT_VECTOR"), + 17 => (" ","PASS "," "," "), + 18 => (" ","PASS "," "," "), + 19 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function not_select_1of2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + + function not_select_1of2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of not_select_1of2 : function is "VHDL-SELECT" ; + attribute recursive_synthesis of not_select_1of2 : function is 1; + attribute pin_bit_information of not_select_1of2 : function is + (1 => (" ","S0 ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","S1 ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","D1 ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","INV ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function not_select_1of3 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + + function not_select_1of3 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of not_select_1of3 : function is "VHDL-SELECT" ; + attribute recursive_synthesis of not_select_1of3 : function is 1; + attribute PIN_BIT_INFORMATION of not_select_1of3 : function is + (1 => (" ","S0 ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","S1 ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","D1 ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","S2 ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","D2 ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","INV ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function not_select_1of4 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + + function not_select_1of4 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of not_select_1of4 : function is "VHDL-SELECT" ; + attribute recursive_synthesis of not_select_1of4 : function is 1; + attribute pin_bit_information of not_select_1of4 : function is + (1 => (" ","S0 ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","S1 ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","D1 ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","S2 ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","D2 ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","S3 ","SAME","PIN_BIT_SCALAR"), + 8 => (" ","D3 ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","INV ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function not_select_1of8 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic ; + in3 : std_ulogic ; + gate4 : std_ulogic ; + in4 : std_ulogic ; + gate5 : std_ulogic ; + in5 : std_ulogic ; + gate6 : std_ulogic ; + in6 : std_ulogic ; + gate7 : std_ulogic ; + in7 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + + function not_select_1of8 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic ; + in3 : std_ulogic_vector ; + gate4 : std_ulogic ; + in4 : std_ulogic_vector ; + gate5 : std_ulogic ; + in5 : std_ulogic_vector ; + gate6 : std_ulogic ; + in6 : std_ulogic_vector ; + gate7 : std_ulogic ; + in7 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of not_select_1of8 : function is "VHDL-SELECT" ; + attribute recursive_synthesis of not_select_1of8 : function is 1; + attribute pin_bit_information of not_select_1of8 : function is + (1 => (" ","S0 ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","S1 ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","D1 ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","S2 ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","D2 ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","S3 ","SAME","PIN_BIT_SCALAR"), + 8 => (" ","D3 ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","S4 ","SAME","PIN_BIT_SCALAR"), + 10 => (" ","D4 ","SAME","PIN_BIT_VECTOR"), + 11 => (" ","S5 ","SAME","PIN_BIT_SCALAR"), + 12 => (" ","D5 ","SAME","PIN_BIT_VECTOR"), + 13 => (" ","S6 ","SAME","PIN_BIT_SCALAR"), + 14 => (" ","D6 ","SAME","PIN_BIT_VECTOR"), + 15 => (" ","S7 ","SAME","PIN_BIT_SCALAR"), + 16 => (" ","D7 ","SAME","PIN_BIT_VECTOR"), + 17 => (" ","PASS "," "," "), + 18 => (" ","PASS "," "," "), + 19 => (" ","INV ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + +end std_ulogic_mux_support; + +-- The Source code for this program is not published or otherwise +package body std_ulogic_mux_support is + + -- Multiplexor/Selector Functions + function mux_2to1 + (code : std_ulogic ; + in0 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic; + begin + case code is + when '0' => result := in0; + when '1' => result := in1; + when others => result := 'X'; + end case; + return result; + end mux_2to1 ; + + function mux_2to1 + (code : std_ulogic ; + in0 : std_ulogic_vector ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + case code is + when '0' => result := in0; + when '1' => result := in1; + when others => result := (others => 'X'); + end case; + return result; + end mux_2to1 ; + + function mux_4to1 + (code : std_ulogic_vector(0 to 1) ; + in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic; + begin + case code is + when "00" => result := in0; + when "01" => result := in1; + when "10" => result := in2; + when "11" => result := in3; + when others => result := 'X'; + end case; + return result; + end mux_4to1 ; + + function mux_4to1 + (code : std_ulogic_vector(0 to 1) ; + in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + case code is + when "00" => result := in0; + when "01" => result := in1; + when "10" => result := in2; + when "11" => result := in3; + when others => result := (others => 'X'); + end case; + return result; + end mux_4to1 ; + + function mux_8to1 + (code : std_ulogic_vector(0 to 2) ; + in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic ; + in6 : std_ulogic ; + in7 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic; + begin + case code is + when "000" => result := in0; + when "001" => result := in1; + when "010" => result := in2; + when "011" => result := in3; + when "100" => result := in4; + when "101" => result := in5; + when "110" => result := in6; + when "111" => result := in7; + when others => result := 'X'; + end case; + return result; + end mux_8to1 ; + + function mux_8to1 + (code : std_ulogic_vector(0 to 2) ; + in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector ; + in6 : std_ulogic_vector ; + in7 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + case code is + when "000" => result := in0; + when "001" => result := in1; + when "010" => result := in2; + when "011" => result := in3; + when "100" => result := in4; + when "101" => result := in5; + when "110" => result := in6; + when "111" => result := in7; + when others => result := (others => 'X'); + end case; + return result; + end mux_8to1 ; + + -- Inverted Multiplexor Selector/Functions + function not_mux_2to1 + (code : std_ulogic ; + in0 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic; + begin + case code is + when '0' => result := not in0; + when '1' => result := not in1; + when others => result := 'X'; + end case; + return result; + end not_mux_2to1 ; + + function not_mux_2to1 + (code : std_ulogic ; + in0 : std_ulogic_vector ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + case code is + when '0' => result := not in0; + when '1' => result := not in1; + when others => result := (others => 'X'); + end case; + return result; + end not_mux_2to1 ; + + function not_mux_4to1 + (code : std_ulogic_vector(0 to 1) ; + in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic; + begin + case code is + when "00" => result := not in0; + when "01" => result := not in1; + when "10" => result := not in2; + when "11" => result := not in3; + when others => result := 'X'; + end case; + return result; + end not_mux_4to1 ; + + function not_mux_4to1 + (code : std_ulogic_vector(0 to 1) ; + in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + case code is + when "00" => result := not in0; + when "01" => result := not in1; + when "10" => result := not in2; + when "11" => result := not in3; + when others => result := (others => 'X'); + end case; + return result; + end not_mux_4to1 ; + + function not_mux_8to1 + (code : std_ulogic_vector(0 to 2) ; + in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic ; + in6 : std_ulogic ; + in7 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic; + begin + case code is + when "000" => result := not in0; + when "001" => result := not in1; + when "010" => result := not in2; + when "011" => result := not in3; + when "100" => result := not in4; + when "101" => result := not in5; + when "110" => result := not in6; + when "111" => result := not in7; + when others => result := 'X'; + end case; + return result; + end not_mux_8to1 ; + + function not_mux_8to1 + (code : std_ulogic_vector(0 to 2) ; + in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector ; + in6 : std_ulogic_vector ; + in7 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + case code is + when "000" => result := not in0; + when "001" => result := not in1; + when "010" => result := not in2; + when "011" => result := not in3; + when "100" => result := not in4; + when "101" => result := not in5; + when "110" => result := not in6; + when "111" => result := not in7; + when others => result := (others => 'X'); + end case; + return result; + end not_mux_8to1 ; + + -- Vectored primitive selector input functions + function select_1of2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 and in0 ) or + ( gate1 and in1 ); + return result ; + end select_1of2 ; + + function select_1of2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector(0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( ( 0 to in1'length-1 => gate1 ) and in1 ); + return result ; + end select_1of2 ; + + function select_1of3 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 and in0 ) or + ( gate1 and in1 ) or + ( gate2 and in2 ) ; + return result ; + end select_1of3 ; + + function select_1of3 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( ( 0 to in1'length-1 => gate1 ) and in1 ) or + ( ( 0 to in1'length-1 => gate2 ) and in2 ); + return result ; + end select_1of3 ; + + function select_1of4 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 and in0 ) or + ( gate1 and in1 ) or + ( gate2 and in2 ) or + ( gate3 and in3 ); + return result ; + end select_1of4 ; + + function select_1of4 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( ( 0 to in1'length-1 => gate1 ) and in1 ) or + ( ( 0 to in2'length-1 => gate2 ) and in2 ) or + ( ( 0 to in3'length-1 => gate3 ) and in3 ) ; + return result ; + end select_1of4 ; + + function select_1of8 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic ; + in3 : std_ulogic ; + gate4 : std_ulogic ; + in4 : std_ulogic ; + gate5 : std_ulogic ; + in5 : std_ulogic ; + gate6 : std_ulogic ; + in6 : std_ulogic ; + gate7 : std_ulogic ; + in7 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 and in0 ) or + ( gate1 and in1 ) or + ( gate2 and in2 ) or + ( gate3 and in3 ) or + ( gate4 and in4 ) or + ( gate5 and in5 ) or + ( gate6 and in6 ) or + ( gate7 and in7 ) ; + return result ; + end select_1of8 ; + + function select_1of8 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic ; + in3 : std_ulogic_vector ; + gate4 : std_ulogic ; + in4 : std_ulogic_vector ; + gate5 : std_ulogic ; + in5 : std_ulogic_vector ; + gate6 : std_ulogic ; + in6 : std_ulogic_vector ; + gate7 : std_ulogic ; + in7 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( ( 0 to in1'length-1 => gate1 ) and in1 ) or + ( ( 0 to in2'length-1 => gate2 ) and in2 ) or + ( ( 0 to in3'length-1 => gate3 ) and in3 ) or + ( ( 0 to in4'length-1 => gate4 ) and in4 ) or + ( ( 0 to in5'length-1 => gate5 ) and in5 ) or + ( ( 0 to in6'length-1 => gate6 ) and in6 ) or + ( ( 0 to in7'length-1 => gate7 ) and in7 ) ; + return result ; + end select_1of8 ; + + function not_select_1of2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 and in0 ) or + ( gate1 and in1 ) ) ; + return result ; + end not_select_1of2 ; + + function not_select_1of2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not( ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( ( 0 to in1'length-1 => gate1 ) and in1 ) ) ; + return result ; + end not_select_1of2 ; + + function not_select_1of3 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 and in0 ) or + ( gate1 and in1 ) or + ( gate2 and in2 ) ) ; + return result ; + end not_select_1of3 ; + + function not_select_1of3 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not( ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( ( 0 to in1'length-1 => gate1 ) and in1 ) or + ( ( 0 to in1'length-1 => gate2 ) and in2 ) ) ; + return result ; + end not_select_1of3 ; + + function not_select_1of4 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 and in0 ) or + ( gate1 and in1 ) or + ( gate2 and in2 ) or + ( gate3 and in3 ) ) ; + return result ; + end not_select_1of4 ; + + function not_select_1of4 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not( ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( ( 0 to in1'length-1 => gate1 ) and in1 ) or + ( ( 0 to in2'length-1 => gate2 ) and in2 ) or + ( ( 0 to in3'length-1 => gate3 ) and in3 ) ) ; + return result ; + end not_select_1of4 ; + + function not_select_1of8 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic ; + in3 : std_ulogic ; + gate4 : std_ulogic ; + in4 : std_ulogic ; + gate5 : std_ulogic ; + in5 : std_ulogic ; + gate6 : std_ulogic ; + in6 : std_ulogic ; + gate7 : std_ulogic ; + in7 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 and in0 ) or + ( gate1 and in1 ) or + ( gate2 and in2 ) or + ( gate3 and in3 ) or + ( gate4 and in4 ) or + ( gate5 and in5 ) or + ( gate6 and in6 ) or + ( gate7 and in7 ) ) ; + return result ; + end not_select_1of8 ; + + function not_select_1of8 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic ; + in3 : std_ulogic_vector ; + gate4 : std_ulogic ; + in4 : std_ulogic_vector ; + gate5 : std_ulogic ; + in5 : std_ulogic_vector ; + gate6 : std_ulogic ; + in6 : std_ulogic_vector ; + gate7 : std_ulogic ; + in7 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not( ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( ( 0 to in1'length-1 => gate1 ) and in1 ) or + ( ( 0 to in2'length-1 => gate2 ) and in2 ) or + ( ( 0 to in3'length-1 => gate3 ) and in3 ) or + ( ( 0 to in4'length-1 => gate4 ) and in4 ) or + ( ( 0 to in5'length-1 => gate5 ) and in5 ) or + ( ( 0 to in6'length-1 => gate6 ) and in6 ) or + ( ( 0 to in7'length-1 => gate7 ) and in7 ) ) ; + return result ; + end not_select_1of8 ; + +end std_ulogic_mux_support; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/ibm/std_ulogic_support.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/ibm/std_ulogic_support.vhdl new file mode 100644 index 0000000..42cdeaa --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/ibm/std_ulogic_support.vhdl @@ -0,0 +1,2694 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +--*************************************************************************** +-- Copyright 2020 International Business Machines +-- +-- Licensed under the Apache License, Version 2.0 (the “License”); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- The patent license granted to you in Section 3 of the License, as applied +-- to the “Work,” hereby includes implementations of the Work in physical form. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an “AS IS” BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- +--*************************************************************************** +library ieee, ibm ; +use ieee.std_logic_1164.all ; +use ieee.numeric_std.all ; + +package std_ulogic_support is + + type base_t is ( bin, oct, dec, hex ); + + ------------------------------------------------------------------- + -- Overloaded Relational Operator that can return std_ulogic + ------------------------------------------------------------------- + function "=" ( l,r : integer ) return std_ulogic; + function "/=" ( l,r : integer ) return std_ulogic; + function ">" ( l,r : integer ) return std_ulogic; + function ">=" ( l,r : integer ) return std_ulogic; + function "<" ( l,r : integer ) return std_ulogic; + function "<=" ( l,r : integer ) return std_ulogic; + + function "=" ( l,r : std_ulogic ) return std_ulogic; + function "/=" ( l,r : std_ulogic ) return std_ulogic; + function ">" ( l,r : std_ulogic ) return std_ulogic; + function ">=" ( l,r : std_ulogic ) return std_ulogic; + function "<" ( l,r : std_ulogic ) return std_ulogic; + function "<=" ( l,r : std_ulogic ) return std_ulogic; + + function "=" ( l, r : std_ulogic_vector ) return std_ulogic; + function "/=" ( l, r : std_ulogic_vector ) return std_ulogic; + function ">" ( l, r : std_ulogic_vector ) return std_ulogic; + function ">=" ( l, r : std_ulogic_vector ) return std_ulogic; + function "<" ( l, r : std_ulogic_vector ) return std_ulogic; + function "<=" ( l, r : std_ulogic_vector ) return std_ulogic; +-- synopsys translate_off + attribute like_builtin of "=" :function is true; + attribute like_builtin of "/=" :function is true; + attribute like_builtin of ">" :function is true; + attribute like_builtin of ">=" :function is true; + attribute like_builtin of "<" :function is true; + attribute like_builtin of "<=" :function is true; +-- Synopsys translate_on + ------------------------------------------------------------------- + -- Relational Functions that can return Boolean + ------------------------------------------------------------------- + function eq( l,r : std_ulogic ) return boolean; + function ne( l,r : std_ulogic ) return boolean; + function gt( l,r : std_ulogic ) return boolean; + function ge( l,r : std_ulogic ) return boolean; + function lt( l,r : std_ulogic ) return boolean; + function le( l,r : std_ulogic ) return boolean; + + ------------------------------------------------------------------- + -- Relational Functions that can return std_ulogic + ------------------------------------------------------------------- + + function eq( l,r : std_ulogic ) return std_ulogic; + function ne( l,r : std_ulogic ) return std_ulogic; + function gt( l,r : std_ulogic ) return std_ulogic; + function ge( l,r : std_ulogic ) return std_ulogic; + function lt( l,r : std_ulogic ) return std_ulogic; + function le( l,r : std_ulogic ) return std_ulogic; + + ------------------------------------------------------------------- + -- Vectorized Relational Functions + ------------------------------------------------------------------- + + function eq( l,r : std_ulogic_vector ) return boolean; + function ne( l,r : std_ulogic_vector ) return boolean; + function gt( l,r : std_ulogic_vector ) return boolean; + function ge( l,r : std_ulogic_vector ) return boolean; + function lt( l,r : std_ulogic_vector ) return boolean; + function le( l,r : std_ulogic_vector ) return boolean; + + function eq( l,r : std_ulogic_vector ) return std_ulogic; + function ne( l,r : std_ulogic_vector ) return std_ulogic; + function gt( l,r : std_ulogic_vector ) return std_ulogic; + function ge( l,r : std_ulogic_vector ) return std_ulogic; + function lt( l,r : std_ulogic_vector ) return std_ulogic; + function le( l,r : std_ulogic_vector ) return std_ulogic; +-- Synopsys translate_off + attribute functionality of eq : function is "="; + attribute functionality of ne : function is "/="; + attribute functionality of gt : function is ">"; + attribute functionality of ge : function is ">="; + attribute functionality of lt : function is "<"; + attribute functionality of le : function is "<="; + + attribute dc_allow of eq : function is true; + attribute dc_allow of ne : function is true; +-- Synopsys translate_on + + ------------------------------------------------------------------- + -- Type Conversion Functions + ------------------------------------------------------------------- + + -- Boolean conversion to other types + function tconv( b : boolean ) return bit; + function tconv( b : boolean ) return std_ulogic; +-- Synopsys translate_off + function tconv( b : boolean ) return string; +-- Synopsys translate_on + + -- Bit to other types + function tconv( b : bit ) return boolean; + function tconv( b : bit ) return integer; + function tconv( b : bit ) return std_ulogic; +-- Synopsys translate_off + function tconv( b : bit ) return character; + function tconv( b : bit ) return string; +-- Synopsys translate_on + + -- Bit_vector to other types + function tconv( b : bit_vector ) return integer; + function tconv( b : bit_vector ) return std_ulogic_vector; +-- function tconv( b : bit_vector ) return std_logic_vector; +-- synopsys translate_off + function tconv( b : bit_vector ) return string; + function tconv( b : bit_vector; base : base_t ) return string; +-- synopsys translate_on + + -- Integer conversion to other types + function tconv( n : integer; w: positive ) return bit_vector ; + function tconv( n : integer; w: positive ) return std_ulogic_vector ; +-- synopsys translate_off + function tconv( n : integer; w: positive ) return string ; + function tconv( n : integer ) return string ; +-- synopsys translate_on + +-- Synopsys translate_off + -- String conversion to other types + function tconv( s : string ) return integer ; + function tconv( s : string; base : base_t ) return integer ; + function tconv( s : string ) return bit ; + function tconv( s : string ) return bit_vector ; + function tconv( s : string; base : base_t ) return bit_vector ; + function tconv( s : string ) return std_ulogic ; + function tconv( s : string ) return std_ulogic_vector ; + function tconv( s : string; base : base_t ) return std_ulogic_vector ; +-- Synopsys translate_on + + -- Std_uLogic to other types + function tconv( s : std_ulogic ) return boolean; + function tconv( s : std_ulogic ) return bit; + function tconv( s : std_ulogic ) return integer; + function tconv( s : std_ulogic ) return std_ulogic_vector; +-- synopsys translate_off + function tconv( s : std_ulogic ) return character; + function tconv( s : std_ulogic ) return string; +-- synopsys translate_on + + -- std_ulogic_vector to other types + function tconv( s : std_ulogic_vector ) return bit_vector; + function tconv( s : std_ulogic_vector ) return std_logic_vector; + function tconv( s : std_ulogic_vector ) return integer; + function tconv( s : std_ulogic_vector ) return std_ulogic; +-- synopsys translate_off + function tconv( s : std_ulogic_vector ) return string; + function tconv( s : std_ulogic_vector; base : base_t ) return string; +-- synopsys translate_on + + -- std_logic_vector to other types +-- function tconv( s : std_logic_vector ) return bit_vector; +-- function tconv( s : std_logic_vector ) return std_ulogic_vector; +-- function tconv( s : std_logic_vector ) return integer; +-- synopsys translate_off +-- function tconv( s : std_logic_vector ) return string; +-- function tconv( s : std_logic_vector; base : base_t ) return string; +-- synopsys translate_on + +-- synopsys translate_off + function hexstring( d : std_ulogic_vector ) return string ; + function octstring( d : std_ulogic_vector ) return string ; + function bitstring( d : std_ulogic_vector ) return string ; +-- synopsys translate_on + + ------------------------------------------------------------------- + -- HIS ATTRIBUTEs for Type Conversion Functions + ------------------------------------------------------------------- +-- Synopsys translate_off + attribute type_convert of tconv : function is true; + + ------------------------------------------------------------------- + -- synthesis ATTRIBUTEs for Type Conversion Functions + ------------------------------------------------------------------- + + attribute btr_name of tconv : function is "PASS"; + attribute pin_bit_information of tconv : function is + (1 => (" ","A0 ","INCR","PIN_BIT_SCALAR"), + 2 => (" ","10 ","INCR","PIN_BIT_SCALAR")); +-- Synopsys translate_on + + --============================================================================ + -- Match Functions + --============================================================================ + + function std_match (l, r: std_ulogic) return std_ulogic; + function std_match (l, r: std_ulogic_vector) return std_ulogic; + +-- Synopsys translate_off + attribute functionality of std_match : function is "="; + attribute dc_allow of std_match : function is true; +-- Synopsys translate_on +--============================================================== + -- Shift and Rotate Functions +--============================================================== + + -- Id: S.1 + function shift_left (arg: std_ulogic_vector; count: natural) return std_ulogic_vector; + -- Result subtype: std_ulogic_vector(ARG'LENGTH-1 downto 0) + -- Result: Performs a shift-left on an std_ulogic_vector vector COUNT times. + -- The vacated positions are filled with '0'. + -- The COUNT leftmost elements are lost. + + -- Id: S.2 + function shift_right (arg: std_ulogic_vector; count: natural) return std_ulogic_vector; + -- Result subtype: std_ulogic_vector(ARG'LENGTH-1 downto 0) + -- Result: Performs a shift-right on an std_ulogic_vector vector COUNT times. + -- The vacated positions are filled with '0'. + -- The COUNT rightmost elements are lost. + + -- Id: S.5 + function rotate_left (arg: std_ulogic_vector; count: natural) return std_ulogic_vector; + -- Result subtype: std_ulogic_vector(ARG'LENGTH-1 downto 0) + -- Result: Performs a rotate-left of an std_ulogic_vector vector COUNT times. + + -- Id: S.6 + function rotate_right (arg: std_ulogic_vector; count: natural) return std_ulogic_vector; + -- Result subtype: std_ulogic_vector(ARG'LENGTH-1 downto 0) + -- Result: Performs a rotate-right of an std_ulogic_vector vector COUNT times. + + -- Id: S.9 + function "sll" (arg: std_ulogic_vector; count: integer) return std_ulogic_vector; + -- Result subtype: std_ulogic_vector(ARG'LENGTH-1 downto 0) + -- Result: SHIFT_LEFT(ARG, COUNT) + + -- Id: S.11 + function "srl" (arg: std_ulogic_vector; count: integer) return std_ulogic_vector; + -- Result subtype: std_ulogic_vector(ARG'LENGTH-1 downto 0) + -- Result: SHIFT_RIGHT(ARG, COUNT) + + -- Id: S.13 + function "rol" (arg: std_ulogic_vector; count: integer) return std_ulogic_vector; + -- Result subtype: std_ulogic_vector(ARG'LENGTH-1 downto 0) + -- Result: ROTATE_LEFT(ARG, COUNT) + + -- Id: S.15 + function "ror" (arg: std_ulogic_vector; count: integer) return std_ulogic_vector; + -- Result subtype: std_ulogic_vector(ARG'LENGTH-1 downto 0) + -- Result: ROTATE_RIGHT(ARG, COUNT) + --=========================================================== + --End shift and rotate functions............................. + --=========================================================== +end std_ulogic_support ; + +package body std_ulogic_support is + + ------------------------------------------------------------------- + -- Look Up tables for operator overloading + ------------------------------------------------------------------- + -- Types used for overloaded operator lookup tables + ------------------------------------------------------------------- + +-- Synopsys synthesis_off + type std_ulogic_to_character_type is array( std_ulogic ) of character; + + constant std_ulogic_to_character : std_ulogic_to_character_type := + ( 'U','X','0','1','Z','W','L','H','-'); + + type stdlogic_2d is array ( std_ulogic, std_ulogic ) of std_ulogic; + type b_stdlogic_2d is array ( std_ulogic, std_ulogic ) of boolean; +-- Synopsys synthesis_on + ------------------------------------------------------------------- + -- Logic operation lookup tables + ------------------------------------------------------------------- +-- Synopsys synthesis_off + -- LessThan Logic Operator + + constant lt_table : stdlogic_2D := ( + -- RHS U X 0 1 Z W L H - | + -- LHS ---------------------------------------------------+--- + ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U + ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X + ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 + ( 'U', 'X', '0', '0', 'X', 'X', '0', '0', 'X' ), -- | 1 + ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z + ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W + ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L + ( 'U', 'X', '0', '0', 'X', 'X', '0', '0', 'X' ), -- | H + ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | - + others=>(others=>'-') + ); + + constant b_lt_table : b_stdlogic_2D := ( + 'U'=>( others=>false ), + 'X'=>( others=>false ), + '0'=>( '1'=>true, 'H'=>true, others=>false ), + '1'=>( others=>false ), + 'Z'=>( others=>false ), + 'W'=>( others=>false ), + 'L'=>( '1'=>true, 'H'=>true, others=>false ), + 'H'=>( others=>false ), + '-'=>( others=>false ), + others=>( others=>false ) + ); + + -- LessThanorEqual Logic Operator + + constant le_table : stdlogic_2D := ( + -- RHS U X 0 1 Z W L H - | + -- LHS ---------------------------------------------------+--- + ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U + ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X + ( 'U', 'X', '1', '1', 'X', 'X', '1', '1', 'X' ), -- | 0 + ( 'U', 'X', '0', '0', 'X', 'X', '0', '0', 'X' ), -- | 1 + ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z + ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W + ( 'U', 'X', '1', '1', 'X', 'X', '0', '1', 'X' ), -- | L + ( 'U', 'X', '0', '0', 'X', 'X', '0', '0', 'X' ), -- | H + ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | - + others=>(others=>'-') + ); + + constant b_le_table : b_stdlogic_2D := ( + -- RHS => - 0 U X 1 Z W L H + -- LHS -------------------------------------------------------------------------------------------------- + 'U'=>( others=>false ), + 'X'=>( others=>false ), + '0'=>( '0'=>true, '1'=>true, 'L'=>true, 'H'=>true, others=>false ), + '1'=>( '1'=>true, 'H'=>true, others=>false ), + 'Z'=>( others=>false ), + 'W'=>( others=>false ), + 'L'=>( '0'=>true, '1'=>true, 'L'=>true, 'H'=>true, others=>false ), + 'H'=>( '1'=>true, 'H'=>true, others=>false ), + '-'=>( others=>false ), + others=>( others=>false ) + ); + + -- GreaterThan Logic Operator + + constant gt_table : stdlogic_2D := ( + -- RHS U X 0 1 Z W L H - | + -- LHS ---------------------------------------------------+--- + ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U + ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X + ( 'U', 'X', '0', '0', 'X', 'X', '0', '0', 'X' ), -- | 0 + ( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 1 + ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z + ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W + ( 'U', 'X', '0', '0', 'X', 'X', '0', '0', 'X' ), -- | L + ( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | H + ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | - + others=>(others=>'-') + ); + + constant b_gt_table : b_stdlogic_2D := ( + -- LHS => ( RHS ) + 'U'=>( others=>false ), + 'X'=>( others=>false ), + '0'=>( others=>false ), + '1'=>( '0'=>true, 'L'=>true, others=>false ), + 'Z'=>( others=>false ), + 'W'=>( others=>false ), + 'L'=>( others=>false ), + 'H'=>( '0'=>true, 'L'=>true, others=>false ), + '-'=>( others=>false ), + others=>(others=>false)); + + -- GreaterThanorEqual Logic Operator + + constant ge_table : stdlogic_2D := ( + -- RHS U X 0 1 Z W L H - | + -- LHS ---------------------------------------------------+--- + ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U + ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X + ( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 0 + ( 'U', 'X', '1', '1', 'X', 'X', '1', '1', 'X' ), -- | 1 + ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z + ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W + ( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | L + ( 'U', 'X', '1', '1', 'X', 'X', '1', '1', 'X' ), -- | H + ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | - + others=>(others=>'-') + ); + + constant b_ge_table : b_stdlogic_2D := ( + -- RHS => - 0 U X 1 Z W L H + -- LHS -------------------------------------------------------------------------------------------------- + 'U'=>( others=>false ), + 'X'=>( others=>false ), + '0'=>( '0'=>true, 'L'=>true, others=>false ), + '1'=>( '0'=>true, '1'=>true, 'L'=>true, 'H'=>true, others=>false ), + 'Z'=>( others=>false ), + 'W'=>( others=>false ), + 'L'=>( '0'=>true, 'L'=>true, others=>false ), + 'H'=>( '0'=>true, '1'=>true, 'L'=>true, 'H'=>true, others=>false ), + '-'=>( others=>false ), + others=>( others=>false ) + ); +-- Synopsys synthesis_on + + ------------------------------------------------------------------- + -- Relational Functions returning Boolean + ------------------------------------------------------------------- + + function eq( l,r : std_ulogic ) return boolean is + begin + return std_match( l, r ); + end eq; + + function ne( l,r : std_ulogic ) return boolean is + begin + return not( std_match( l, r ) ); + end ne; + + function gt( l,r : std_ulogic ) return boolean is + variable result : boolean; + -- pragma built_in SYN_GT + begin + -- Synopsys translate_off + assert ( l /= '-' ) and ( r /= '-' ) + report "Invalid dont_care in relational function" + severity error; + result := b_gt_table( l, r ); + -- Synopsys translate_on + return result; + end gt; + + function ge( l,r : std_ulogic ) return boolean is + variable result : boolean; + -- pragma built_in SYN_GEQ + begin + -- synopsys translate_off + assert ( l /= '-' ) and ( r /= '-' ) + report "Invalid dont_care in relational function" + severity error; + result := b_ge_table( l, r ); + -- synopsys translate_on + return result; + end ge; + + function lt( l,r : std_ulogic ) return boolean is + variable result : boolean; + -- pragma built_in SYN_LT + begin + -- synopsys translate_off + assert ( l /= '-' ) and ( r /= '-' ) + report "Invalid dont_care in relational function" + severity error; + result := b_lt_table( l, r ); + -- synopsys translate_on + return result; + end lt; + + function le( l,r : std_ulogic ) return boolean is + variable result : boolean; + -- pragma built_in SYN_LEQ + begin + -- synopsys translate_off + assert ( l /= '-' ) and ( r /= '-' ) + report "Invalid dont_care in relational function" + severity error; + result := b_le_table( l, r ); + -- synopsys translate_on + return result; + end le; + + ------------------------------------------------------------------- + -- Relational Functions returning std_ulogic + ------------------------------------------------------------------- + + function eq( l,r : std_ulogic ) return std_ulogic is + begin + return std_match( l, r ); + end eq; + + function ne( l,r : std_ulogic ) return std_ulogic is + begin + return not std_match( l, r ) ; + end ne; + + function gt( l,r : std_ulogic ) return std_ulogic is + variable result : std_ulogic; + -- pragma built_in SYN_GT + begin + -- Synopsys translate_off + assert ( l /= '-' ) and ( r /= '-' ) + report "Invalid dont_care in relational function" + severity error; + result := gt_table( l, r ); + -- synopsys translate_on + return result; + end gt; + + function ge( l,r : std_ulogic ) return std_ulogic is + variable result : std_ulogic; + -- pragma built_in SYN_GEQ + begin + -- Synopsys translate_off + assert ( l /= '-' ) and ( r /= '-' ) + report "Invalid dont_care in relational function" + severity error; + result := ge_table( l, r ); + -- Synopsys translate_on + return result; + end ge; + + function lt( l,r : std_ulogic ) return std_ulogic is + variable result : std_ulogic; + -- pragma built_in SYN_LT + begin + -- Synopsys translate_off + assert ( l /= '-' ) and ( r /= '-' ) + report "Invalid dont_care in relational function" + severity error; + result := lt_table( l, r ); + -- Synopsys translate_on + return result; + end lt; + + function le( l,r : std_ulogic ) return std_ulogic is + variable result : std_ulogic; + -- pragma built_in SYN_LEQ + begin + -- Synopsys translate_off + assert ( l /= '-' ) and ( r /= '-' ) + report "Invalid dont_care in relational function" + severity error; + result := le_table( l, r ); + -- Synopsys translate_on + return result; + end le; + + -- + -- utility function get rid of most meta values + -- + function to_x01d( d : std_ulogic ) return std_ulogic is + -- pragma built_in SYN_FEED_THRU + variable result : std_ulogic; + begin + -- Synopsys translate_off + case d is + when '0' | 'L' => result := '0'; + when '1' | 'H' => result := '1'; + when '-' => result := '-'; + when others => result := 'X'; + end case; + -- Synopsys translate_on + return result; + end to_x01d; + + ------------------------------------------------------------------- + -- Vectored Relational Functions returning Boolean + ------------------------------------------------------------------- + function eq( l,r : std_ulogic_vector) return boolean is + variable result : boolean ; + begin + result := std_match(l,r); + return result; + end eq; + + --------------------------------------------------------------------- + function ne( l,r : std_ulogic_vector) return boolean is + variable result : boolean ; + begin + result := not std_match(l,r); + return result; + end ne; + + ------------------------------------------------------------------- + function gt( l,r : std_ulogic_vector) return boolean is + variable result : boolean ; + begin + result := unsigned(l) > unsigned(r); + return result; + end gt; + + ------------------------------------------------------------------- + function ge( l,r : std_ulogic_vector) return boolean is + variable result : boolean ; + begin + result := unsigned(l) >= unsigned(r); + return result; + end ge; + + ------------------------------------------------------------------- + function lt( l,r : std_ulogic_vector) return boolean is + variable result : boolean ; + begin + result := unsigned(l) < unsigned(r); + return result; + end lt; + + ------------------------------------------------------------------- + function le( l,r : std_ulogic_vector) return boolean is + variable result : boolean ; + begin + result := unsigned(l) <= unsigned(r); + return result; + end le; + + ------------------------------------------------------------------- + -- vectored relational functions returning std_ulogic + ------------------------------------------------------------------- + function eq( l,r : std_ulogic_vector) return std_ulogic is + variable result : std_ulogic ; + begin + result := std_match( l, r ) ; + --result := (l ?= r); + return result; + end eq; + --------------------------------------------------------------------- + function ne( l,r : std_ulogic_vector) return std_ulogic is + variable result :std_ulogic ; + begin + result := not std_match( l, r ) ; + --result := not (l ?= r); + return result; + end ne; + + ------------------------------------------------------------------- + function gt( l,r : std_ulogic_vector) return std_ulogic is + variable result : boolean ; + -- pragma built_in SYN_GT + begin + result := unsigned(l) > unsigned(r); + if (result = true ) then + return '1' ; + else + return '0'; + end if ; + end gt; + + ------------------------------------------------------------------- + function ge( l,r : std_ulogic_vector) return std_ulogic is + variable result : boolean ; + -- pragma built_in SYN_GEQ + begin + result := unsigned(l) >= unsigned(r); + if (result = true ) then + return '1' ; + else + return '0'; + end if ; + end ge; + + ------------------------------------------------------------------- + function lt( l,r : std_ulogic_vector) return std_ulogic is + variable result : boolean ; + -- pragma built_in SYN_LT + begin + result := unsigned(l) < unsigned(r); + if (result = true ) then + return '1' ; + else + return '0'; + end if ; + end lt; + + ------------------------------------------------------------------- + function le( l,r : std_ulogic_vector) return std_ulogic is + variable result : boolean ; + -- pragma built_in SYN_LEQ + begin + result := unsigned(l) <= unsigned(r); + if (result = true ) then + return '1' ; + else + return '0'; + end if ; + end le; + + ------------------------------------------------------------------- + -- Type Conversion Functions + ------------------------------------------------------------------- + ------------------------------------------------------------------- + -- Boolean Conversions + ------------------------------------------------------------------- + function tconv ( b : boolean ) return bit is + -- pragma built_in SYN_FEED_THRU + begin + case b is + when false => return('0'); + when true => return('1'); + end case; + end tconv ; + +-- Synopsys translate_off + function tconv ( b : boolean ) return string is + begin + case b is + when false => return("FALSE"); + when true => return("TRUE"); + end case; + end tconv ; +-- Synopsys translate_on + + function tconv ( b : boolean ) return std_ulogic is + -- pragma built_in SYN_FEED_THRU + begin + case b is + when false => return('0'); + when true => return('1'); + end case; + end tconv ; + + ------------------------------------------------------------------- + -- Bit Conversions + ------------------------------------------------------------------- + function tconv ( b : bit ) return boolean is + -- pragma built_in SYN_FEED_THRU + begin + case b is + when '0' => return(false); + when '1' => return(true); + end case; + end tconv ; + +-- Synopsys translate_off + function tconv ( b : bit ) return character is + begin + case b is + when '0' => return('0'); + when '1' => return('1'); + end case; + end tconv ; + + function tconv ( b : bit ) return string is + begin + case b is + when '0' => return("0"); + when '1' => return("1"); + end case; + end tconv ; +-- Synopsys translate_on + + function tconv ( b : bit ) return integer is + -- pragma built_in SYN_UNSIGNED_TO_INTEGER + begin + case b is + when '0' => return(0); + when '1' => return(1); + end case; + end tconv ; + + function tconv ( b : bit ) return std_ulogic is + -- pragma built_in SYN_FEED_THRU + begin + case b is + when '0' => return('0'); + when '1' => return('1'); + end case; + end tconv ; + + ------------------------------------------------------------------- + -- Bit_vector Conversions + ------------------------------------------------------------------- + function tconv ( b : bit_vector ) return integer is + variable int_result : integer ; + variable int_exp : integer ; + variable new_value : bit_vector(1 to b'length); + -- pragma built_in SYN_UNSIGNED_TO_INTEGER + begin + -- Synopsys translate_off + int_result := 0; + int_exp := 0; + new_value := b; + for i in new_value'length to 1 loop + if b(i)='1' then + int_result := int_result + (2**int_exp); + end if; + int_exp := int_exp + 1; + end loop; + -- synopsys translate_on + return int_result; + end tconv ; + +-- Synopsys translate_off + function tconv ( b : bit_vector ) return string is + alias sv : bit_vector ( 1 to b'length ) is b; + variable result : string ( 1 to b'length ); + begin + result := (others => '0'); + for i in result'range loop + case sv(i) is + when '0' => result(i) := '0'; + when '1' => result(i) := '1'; + end case; + end loop; + return result; + end tconv ; +-- Synopsys translate_on + +-- Synopsys translate_off + function tconv ( b : bit_vector; base : base_t ) return string is + alias sv : bit_vector ( 1 to b'length ) is b; + variable result : string ( 1 to b'length ); + variable start : positive; + variable extra : natural; + variable resultlength : positive; + subtype bv is bit_vector( 1 to 1 ); + subtype qv is bit_vector( 1 to 2 ); + subtype ov is bit_vector( 1 to 3 ); + subtype hv is bit_vector( 1 to 4 ); + begin + case base is + when bin => + resultlength := sv'length; + start := 1; + for i in start to resultlength loop + case sv( i ) is + when '0' => result( i ) := '0'; + when '1' => result( i ) := '1'; + end case; + end loop; + + when oct => + extra := sv'length rem ov'length; + case extra is + when 0 => + resultlength := b'length/ov'length; + start := 1; + when 1 => + resultlength := ( b'length/ov'length ) + 1; + start := 2; + case sv( 1 ) is + when '0' => result( 1 ) := '0'; + when '1' => result( 1 ) := '1'; + end case; + when 2 => + resultlength := ( b'length/ov'length ) + 1; + start := 2; + case qv'( sv( 1 to 2 ) ) is + when "00" => result( 1 ) := '0'; + when "01" => result( 1 ) := '1'; + when "10" => result( 1 ) := '2'; + when "11" => result( 1 ) := '3'; + end case; + when others => + assert false report "TCONV fatal condition" severity failure; + end case; + + for i in 0 to resultLength - start loop + case ov'( SV( (ov'length*i)+(extra+1) to (ov'length*i)+(extra+3) ) ) is + when "000" => result( i+start ) := '0'; + when "001" => result( i+start ) := '1'; + when "010" => result( i+start ) := '2'; + when "011" => result( i+start ) := '3'; + when "100" => result( i+start ) := '4'; + when "101" => result( i+start ) := '5'; + when "110" => result( i+start ) := '6'; + when "111" => result( i+start ) := '7'; + when others => result( i+start ) := '.'; + end case; + end loop; + + when hex => + extra := b'length rem hv'length; + case extra is + when 0 => + resultLength := b'length/hv'length; + start := 1; + when 1 => + resultLength := ( b'length/hv'length ) + 1; + start := 2; + case sv( 1 ) is + when '0' => result( 1 ) := '0'; + when '1' => result( 1 ) := '1'; + end case; + when 2 => + resultLength := ( b'length/hv'length ) + 1; + start := 2; + case qv'( sv( 1 to 2 ) ) is + when "00" => result( 1 ) := '0'; + when "01" => result( 1 ) := '1'; + when "10" => result( 1 ) := '2'; + when "11" => result( 1 ) := '3'; + end case; + when 3 => + resultLength := ( b'length/hv'length ) + 1; + start := 2; + case ov'( sv( 1 to 3 ) ) is + when o"0" => result( 1 ) := '0'; + when o"1" => result( 1 ) := '1'; + when o"2" => result( 1 ) := '2'; + when o"3" => result( 1 ) := '3'; + when o"4" => result( 1 ) := '4'; + when o"5" => result( 1 ) := '5'; + when o"6" => result( 1 ) := '6'; + when o"7" => result( 1 ) := '7'; + end case; + when others => + assert false report "TCONV fatal condition" severity failure; + end case; + + for i in 0 to resultLength - start loop + case hv'( SV( (hv'length*i)+(extra+1) to (hv'length*i)+(extra+4) ) ) is + when "0000" => result( i+start ) := '0'; + when "0001" => result( i+start ) := '1'; + when "0010" => result( i+start ) := '2'; + when "0011" => result( i+start ) := '3'; + when "0100" => result( i+start ) := '4'; + when "0101" => result( i+start ) := '5'; + when "0110" => result( i+start ) := '6'; + when "0111" => result( i+start ) := '7'; + when "1000" => result( i+start ) := '8'; + when "1001" => result( i+start ) := '9'; + when "1010" => result( i+start ) := 'A'; + when "1011" => result( i+start ) := 'B'; + when "1100" => result( i+start ) := 'C'; + when "1101" => result( i+start ) := 'D'; + when "1110" => result( i+start ) := 'E'; + when "1111" => result( i+start ) := 'F'; + when others => result( i+start ) := '.'; + end case; + end loop; + + when others => + assert false report "Unsupported base passed." severity warning; + + end case; + + return result( 1 to resultLength ); + end tconv ; +-- Synopsys translate_on + + function tconv ( b : bit_vector ) return std_ulogic_vector is + alias sv : bit_vector ( 1 to b'length ) is b; + variable result : std_ulogic_vector ( 1 to b'length ); + -- pragma built_in SYN_FEED_THRU + begin + for i in result'range loop + case sv(i) is + when '0' => result(i) := '0'; + when '1' => result(i) := '1'; + end case; + end loop; + return result; + end tconv ; + + --function tconv ( b : bit_vector ) return std_logic_vector is + -- alias sv : bit_vector ( 1 to b'length ) is b; + -- variable result : std_logic_vector ( 1 to b'length ); + ---- pragma built_in SYN_FEED_THRU + --begin + -- for i in result'range loop + -- case sv(i) is + -- when '0' => result(i) := '0'; + -- when '1' => result(i) := '1'; + -- end case; + -- end loop; + -- return result; + --end tconv ; + + ------------------------------------------------------------------- + -- Integer conversion to other types + ------------------------------------------------------------------- + function tconv ( n : integer;w : positive) return bit_vector is + variable result : bit_vector(w-1 downto 0) ; + variable ib : integer; + variable test : integer; + -- pragma built_in SYN_INTEGER_TO_UNSIGNED + begin + if n < 0 then + result := (others => '0'); + else + ib := n; + result := (others => '0'); + for i in result'reverse_range loop + exit when ib = 0; + test := ib rem 2; + if test = 1 then + result(i) := '1'; + else + result(i) := '0'; + end if; + ib := ib / 2; + end loop; + end if; + -- synopsys translate_off + assert n >= 0 + report "tconv: n < 0 is not permitted" + severity warning; + assert ib = 0 + report "tconv: integer overflows requested result width" + severity warning; + -- synopsys translate_on + return result; + end tconv; + + function tconv ( n : integer; w : positive) return std_ulogic_vector is + variable result : std_ulogic_vector(w-1 downto 0) ; + variable ib : integer; + variable test : integer; + -- pragma built_in SYN_INTEGER_TO_UNSIGNED + begin + if n < 0 then + result := (others => 'X'); + else + ib := n; + result := (others => '0'); + for i in result'reverse_range loop + exit when ib = 0; + test := ib rem 2; + if test = 1 then + result(i) := '1'; + else + result(i) := '0'; + end if; + ib := ib / 2; + end loop; + end if; + -- Synopsys translate_off + assert n >= 0 + report "tconv: n < 0 is not permitted" + severity warning; + assert ib = 0 + report "tconv: integer overflows requested result width" + severity warning; + -- Synopsys translate_on + return result; + end tconv; + +-- Synopsys translate_off + function tconv ( n : integer; w : positive ) return string is + subtype digit is integer range 0 to 9; + variable result : string( 1 to w ) ; + variable ib : integer; + variable msd : integer; + variable sign : character := '-'; + variable test : digit; + begin + ib := abs n; + for i in result'reverse_range loop + test := ib rem 10; + + case test is + when 0 => result(i) := '0'; + when 1 => result(i) := '1'; + when 2 => result(i) := '2'; + when 3 => result(i) := '3'; + when 4 => result(i) := '4'; + when 5 => result(i) := '5'; + when 6 => result(i) := '6'; + when 7 => result(i) := '7'; + when 8 => result(i) := '8'; + when 9 => result(i) := '9'; + end case; + + ib := ib / 10; + + exit when ib = 0; + end loop; + + if ib < 0 then + result(1) := sign; + end if; + + assert + not( ( ( ib < 0 ) and ( ( abs ib ) > ( 10**(w-1) - 1 ) ) ) or + ( ( ib >= 0 ) and ( ib > ( 10**w - 1 ) ) ) ) + report "tconv: integer overflows requested result width" + severity warning; + + return result; + end tconv; +-- Synopsys translate_on + +-- Synopsys translate_off + function tconv ( n : integer) return string is + subtype digit is integer range 0 to 9; + variable result : string( 1 to 10 ) ; + variable ib : integer; + variable msd : integer; + variable sign : character := '-'; + variable test : digit; + begin + ib := abs n ; + for i in result'reverse_range loop + test := ib rem 10; + case test is + when 0 => result(i) := '0'; + when 1 => result(i) := '1'; + when 2 => result(i) := '2'; + when 3 => result(i) := '3'; + when 4 => result(i) := '4'; + when 5 => result(i) := '5'; + when 6 => result(i) := '6'; + when 7 => result(i) := '7'; + when 8 => result(i) := '8'; + when 9 => result(i) := '9'; + end case; + ib := ib / 10; + if ib = 0 then + msd := i; + exit; + end if; + end loop; + if ib < 0 then + return sign & result(msd to 10); + else + return result(msd to 10); + end if; + end tconv; +-- Synopsys translate_on + + ------------------------------------------------------------------- + -- String conversion to other types + ------------------------------------------------------------------- +-- Synopsys translate_off + function TConv ( s : string ) return integer is + variable result : integer ; + alias si : string( s'length downto 1 ) is s; + variable invalid : boolean ; + begin + invalid := false ; + for i in si'range loop + case si( i ) is + when '0' => null; + when '1' => result := result + 10 ** ( i - 1 ) ; + when '2' => result := result + 2 * 10 ** ( i - 1 ) ; + when '3' => result := result + 3 * 10 ** ( i - 1 ) ; + when '4' => result := result + 4 * 10 ** ( i - 1 ) ; + when '5' => result := result + 5 * 10 ** ( i - 1 ) ; + when '6' => result := result + 6 * 10 ** ( i - 1 ) ; + when '7' => result := result + 7 * 10 ** ( i - 1 ) ; + when '8' => result := result + 8 * 10 ** ( i - 1 ) ; + when '9' => result := result + 9 * 10 ** ( i - 1 ) ; + when others => invalid := true; + end case; + end loop; + assert not invalid + report "String contained characters other than 0 thru 9" & + "; treating invalid characters as 0's" + severity warning; + return result; + end tconv; +-- Synopsys translate_on + +-- Synopsys translate_off + function tconv ( s : string; base : base_t ) return integer is + alias sv : string ( s'length downto 1 ) is s; + variable result : integer ; + variable invalid : boolean ; + variable vc_len : integer ; + variable validchars : string(1 to 20) := "0 thru 9 or A thru F"; + begin + invalid := false ; + case base is + when bin => + vc_len := 6; + validchars(1 to 6) := "0 or 1"; + for i in sv'range loop + case sv( i ) is + when '0' => null; + when '1' => result := result + 2 ** ( i - 1 ) ; + when others => invalid := true; + end case; + end loop; + + when oct => + vc_len := 8; + validchars(1 to 8) := "0 thru 7"; + for i in sv'range loop + case sv( i ) is + when '0' => null; + when '1' => result := result + 8 ** ( i - 1 ) ; + when '2' => result := result + 2 * 8 ** ( i - 1 ) ; + when '3' => result := result + 3 * 8 ** ( i - 1 ) ; + when '4' => result := result + 4 * 8 ** ( i - 1 ) ; + when '5' => result := result + 5 * 8 ** ( i - 1 ) ; + when '6' => result := result + 6 * 8 ** ( i - 1 ) ; + when '7' => result := result + 7 * 8 ** ( i - 1 ) ; + when others => invalid := true; + end case; + end loop; + + when dec => + vc_len := 8; + validchars(1 to 8) := "0 thru 9"; + for i in sv'range loop + case sv( i ) is + when '0' => null; + when '1' => result := result + 10 ** ( i - 1 ) ; + when '2' => result := result + 2 * 10 ** ( i - 1 ) ; + when '3' => result := result + 3 * 10 ** ( i - 1 ) ; + when '4' => result := result + 4 * 10 ** ( i - 1 ) ; + when '5' => result := result + 5 * 10 ** ( i - 1 ) ; + when '6' => result := result + 6 * 10 ** ( i - 1 ) ; + when '7' => result := result + 7 * 10 ** ( i - 1 ) ; + when '8' => result := result + 8 * 10 ** ( i - 1 ) ; + when '9' => result := result + 9 * 10 ** ( i - 1 ) ; + when others => invalid := true; + end case; + end loop; + + when hex => + for i in sv'range loop + case sv( i ) is + when '0' => null; + when '1' => result := result + 16 ** ( i - 1 ) ; + when '2' => result := result + 2 * 16 ** ( i - 1 ) ; + when '3' => result := result + 3 * 16 ** ( i - 1 ) ; + when '4' => result := result + 4 * 16 ** ( i - 1 ) ; + when '5' => result := result + 5 * 16 ** ( i - 1 ) ; + when '6' => result := result + 6 * 16 ** ( i - 1 ) ; + when '7' => result := result + 7 * 16 ** ( i - 1 ) ; + when '8' => result := result + 8 * 16 ** ( i - 1 ) ; + when '9' => result := result + 9 * 16 ** ( i - 1 ) ; + when 'A' | 'a' => result := result + 10 * 16 ** ( i - 1 ) ; + when 'B' | 'b' => result := result + 11 * 16 ** ( i - 1 ) ; + when 'C' | 'c' => result := result + 12 * 16 ** ( i - 1 ) ; + when 'D' | 'd' => result := result + 13 * 16 ** ( i - 1 ) ; + when 'E' | 'e' => result := result + 14 * 16 ** ( i - 1 ) ; + when 'F' | 'f' => result := result + 15 * 16 ** ( i - 1 ) ; + when others => invalid := true; + end case; + end loop; + + when others => + assert false report "Unsupported base passed." severity warning; + + end case; + + assert not invalid + report "String contained characters other than " & + validchars(1 to vc_len) & "; treating invalid characters as 0's" + severity warning; + + return result; + end; +-- Synopsys translate_on + +-- Synopsys translate_off + function tconv ( s : string ) return bit is + variable result : bit; + alias si : string( 1 to s'length ) is s; + variable invalid : boolean := false; + begin + assert s'length = 1 + report "String conversion to bit longer that 1 character" + severity warning; + case si(1) is + when '0' => result := '0'; + when '1' => result := '1'; + when others => + invalid := true; + result := '0'; + end case; + assert not invalid + report "String contained characters other than 0 or 1; " & + "treating invalid characters as 0's" + severity warning; + return result; + end tconv; +-- Synopsys translate_on + +-- Synopsys translate_off + function tconv ( s : string ) return bit_vector is + variable result : bit_vector( 1 to s'length ); + alias si : string( 1 to s'length ) is s; + variable invalid : boolean := false; + begin + for i in si'range loop + case si(i) is + when '0' => result( i ) := '0'; + when '1' => result( i ) := '1'; + when others => + invalid := true; + result( i ) := '0'; + end case; + end loop; + assert not invalid + report "String contained characters other than 0 or 1; " & + "treating invalid characters as 0's" + severity warning; + return result( 1 to result'length ); + end tconv; +-- Synopsys translate_on + +-- Synopsys translate_off + function tconv ( s : string; base : base_t ) return bit_vector is + variable result : bit_vector( 1 to 4*s'length ); + alias si : string( 1 to s'length ) is s; + variable invalid : boolean := false; + begin + case base is + when bin => + for i in si'range loop + case si(i) is + when '0' => result( i ) := '0'; + when '1' => result( i ) := '1'; + when others => + invalid := true; + result( i ) := '0'; + end case; + end loop; + assert not invalid + report "String contained characters other than 0 or 1; " & + "treated invalid characters as 0's" + severity warning; + return result(1 to s'length) ; + + when oct => + for i in si'range loop + case si(i) is + when '0' => result( (3*i)-2 to 3*i ) := o"0"; + when '1' => result( (3*i)-2 to 3*i ) := o"1"; + when '2' => result( (3*i)-2 to 3*i ) := o"2"; + when '3' => result( (3*i)-2 to 3*i ) := o"3"; + when '4' => result( (3*i)-2 to 3*i ) := o"4"; + when '5' => result( (3*i)-2 to 3*i ) := o"5"; + when '6' => result( (3*i)-2 to 3*i ) := o"6"; + when '7' => result( (3*i)-2 to 3*i ) := o"7"; + when others => + invalid := true; + result( (3*i)-2 to 3*i ) := o"0"; + end case; + end loop; + assert not invalid + report "String contained characters other than 0 through 7; " & + "treated invalid characters as 0's" + severity warning; + return result( 1 to 3*s'length ); + + when hex => + for i in si'range loop + case si(i) is + when '0' => result( (4*i)-3 to 4*i ) := x"0"; + when '1' => result( (4*i)-3 to 4*i ) := x"1"; + when '2' => result( (4*i)-3 to 4*i ) := x"2"; + when '3' => result( (4*i)-3 to 4*i ) := x"3"; + when '4' => result( (4*i)-3 to 4*i ) := x"4"; + when '5' => result( (4*i)-3 to 4*i ) := x"5"; + when '6' => result( (4*i)-3 to 4*i ) := x"6"; + when '7' => result( (4*i)-3 to 4*i ) := x"7"; + when '8' => result( (4*i)-3 to 4*i ) := x"8"; + when '9' => result( (4*i)-3 to 4*i ) := x"9"; + when 'A' | 'a' => result( (4*i)-3 to 4*i ) := x"A"; + when 'B' | 'b' => result( (4*i)-3 to 4*i ) := x"B"; + when 'C' | 'c' => result( (4*i)-3 to 4*i ) := x"C"; + when 'D' | 'd' => result( (4*i)-3 to 4*i ) := x"D"; + when 'E' | 'e' => result( (4*i)-3 to 4*i ) := x"E"; + when 'F' | 'f' => result( (4*i)-3 to 4*i ) := x"F"; + when others => + invalid := true; + result( (4*i)-3 to 4*i ) := x"0"; + end case; + end loop; + assert not invalid + report "String contained characters other than 0 through 9 or " & + "A through F; " & + "treated invalid characters as 0's" + severity warning; + return result( 1 to 4*s'length ); + + when others => + assert false report "Unsupported base passed." severity warning; + return result ; + + end case; + end tconv; +-- Synopsys translate_on + +-- Synopsys translate_off + function tconv ( s : string ) return std_ulogic is + variable result : std_ulogic; + alias si : string( 1 to s'length ) is s; + variable invalid : boolean := false; + begin + assert s'length = 1 + report "String conversion to bit longer that 1 character" + severity warning; + case si(1) is + when '0' => result := '0'; + when '1' => result := '1'; + when others => + invalid := true; + result := 'X'; + end case; + assert not invalid + report "String contained characters other than 0 or 1; " & + "treating invalid characters as X's" + severity warning; + return result; + end tconv; +-- Synopsys translate_on + +-- Synopsys translate_off + function tconv ( s : string ) return std_ulogic_vector is + variable result : std_ulogic_vector( 1 to s'length ); + alias si : string( 1 to s'length ) is s; + variable invalid : boolean := false; + begin + for i in si'range loop + case si(i) is + when '0' => result( i ) := '0'; + when '1' => result( i ) := '1'; + when others => + invalid := true; + result( i ) := 'X'; + end case; + end loop; + assert not invalid + report "String contained characters other than 0 or 1; " & + "treating invalid characters as X's" + severity warning; + return result( 1 to result'length ); + end tconv; +-- Synopsys translate_on + +-- Synopsys translate_off + function tconv ( s : string; base : base_t ) return std_ulogic_vector is + variable result : std_ulogic_vector( 1 to 4*s'length ); + alias si : string( 1 to s'length ) is s; + variable invalid : boolean := false; + begin + case base is + when bin => + for i in si'range loop + case si(i) is + when '0' => result( i ) := '0'; + when '1' => result( i ) := '1'; + when others => + invalid := true; + result( i ) := '0'; + end case; + end loop; + assert not invalid + report "String contained characters other than 0 or 1; " & + "treated invalid characters as 0's" + severity warning; + return result(1 to s'length) ; + + when oct => + for i in si'range loop + case si(i) is + when '0' => result( (3*i)-2 to 3*i ) := "000"; + when '1' => result( (3*i)-2 to 3*i ) := "001"; + when '2' => result( (3*i)-2 to 3*i ) := "010"; + when '3' => result( (3*i)-2 to 3*i ) := "011"; + when '4' => result( (3*i)-2 to 3*i ) := "100"; + when '5' => result( (3*i)-2 to 3*i ) := "101"; + when '6' => result( (3*i)-2 to 3*i ) := "110"; + when '7' => result( (3*i)-2 to 3*i ) := "111"; + when others => + invalid := true; + result( (3*i)-2 to 3*i ) := "XXX"; + end case; + end loop; + assert not invalid + report "String contained characters other than 0 through 7; " & + "treated invalid characters as X's" + severity warning; + return result( 1 to 3*s'length ); + + when hex => + for i in si'range loop + case si(i) is + when '0' => result( (4*i)-3 to 4*i ) := "0000"; + when '1' => result( (4*i)-3 to 4*i ) := "0001"; + when '2' => result( (4*i)-3 to 4*i ) := "0010"; + when '3' => result( (4*i)-3 to 4*i ) := "0011"; + when '4' => result( (4*i)-3 to 4*i ) := "0100"; + when '5' => result( (4*i)-3 to 4*i ) := "0101"; + when '6' => result( (4*i)-3 to 4*i ) := "0110"; + when '7' => result( (4*i)-3 to 4*i ) := "0111"; + when '8' => result( (4*i)-3 to 4*i ) := "1000"; + when '9' => result( (4*i)-3 to 4*i ) := "1001"; + when 'A' | 'a' => result( (4*i)-3 to 4*i ) := "1010"; + when 'B' | 'b' => result( (4*i)-3 to 4*i ) := "1011"; + when 'C' | 'c' => result( (4*i)-3 to 4*i ) := "1100"; + when 'D' | 'd' => result( (4*i)-3 to 4*i ) := "1101"; + when 'E' | 'e' => result( (4*i)-3 to 4*i ) := "1110"; + when 'F' | 'f' => result( (4*i)-3 to 4*i ) := "1111"; + when others => + invalid := true; + result( (4*i)-3 to 4*i ) := "XXXX"; + end case; + end loop; + assert not invalid + report "String contained characters other than 0 through 9 or " & + "A through F; " & + "treated invalid characters as X's" + severity warning; + return result( 1 to 4*s'length ); + + when others => + assert false report "Unsupported base passed." severity warning; + return result ; + + end case; + end tconv; +-- Synopsys translate_on + + ------------------------------------------------------------------- + -- Std_uLogic Conversions + ------------------------------------------------------------------- + function tconv ( s : std_ulogic ) return boolean is + -- pragma built_in SYN_FEED_THRU + begin + case s is + when '0' => return(false); + when '1' => return(true); + when 'L' => return(false); + when 'H' => return(true); + when others => return(false); + end case; + end; + + function tconv ( s : std_ulogic ) return bit is + -- pragma built_in SYN_FEED_THRU + begin + case s is + when '0' => return('0'); + when '1' => return('1'); + when 'L' => return('0'); + when 'H' => return('1'); + when others => return('0'); + end case; + end; + +-- Synopsys translate_off + function tconv ( s : std_ulogic ) return character is + begin + case s is + when '0' => return('0'); + when 'L' => return('L'); + when '1' => return('1'); + when 'H' => return('H'); + when 'U' => return('U'); + when 'W' => return('W'); + when '-' => return('-'); + when 'Z' => return('Z'); + when others => return('X'); + end case; + end; +-- Synopsys translate_on + +-- Synopsys translate_off + function tconv ( s : std_ulogic ) return string is + begin + case s is + when '0' => return("0"); + when 'L' => return("L"); + when '1' => return("1"); + when 'H' => return("H"); + when 'U' => return("U"); + when 'W' => return("W"); + when '-' => return("-"); + when 'Z' => return("Z"); + when others => return("X"); + end case; + end; +-- Synopsys translate_on + + function tconv ( s : std_ulogic ) return integer is + -- pragma built_in SYN_UNSIGNED_TO_INTEGER + begin + case s is + when '0' => return(0); + when 'L' => return(0); + when '1' => return(1); + when 'H' => return(1); + when 'U' => return(0); + when 'W' => return(0); + when '-' => return(0); + when 'Z' => return(0); + when others => return(0); + end case; + end; + + function tconv ( s : std_ulogic ) return std_ulogic_vector is + -- pragma built_in SYN_FEED_THRU + begin + case s is + when '0' => return("0"); + when 'L' => return("L"); + when '1' => return("1"); + when 'H' => return("H"); + when 'U' => return("U"); + when 'W' => return("W"); + when '-' => return("-"); + when 'Z' => return("Z"); + when others => return("X"); + end case; + end; + + ------------------------------------------------------------------- + -- std_ulogic_vector Conversions + ------------------------------------------------------------------- + function tconv ( s : std_ulogic_vector ) return bit_vector is + alias sv : std_ulogic_vector ( 1 to s'length ) is s; + variable result : bit_vector ( 1 to s'length ) ; + -- pragma built_in SYN_FEED_THRU + begin + for i in result'range loop + case sv(i) is + when '0' => result(i) := '0'; + when '1' => result(i) := '1'; + when 'L' => result(i) := '0'; + when 'H' => result(i) := '1'; + when others => result(i) := '0'; + end case; + end loop; + return result; + end; + + function tconv ( s : std_ulogic_vector ) return std_logic_vector is + alias sv : std_ulogic_vector ( 1 to s'length ) is s; + variable result : std_logic_vector ( 1 to s'length ) := (others => 'X'); + -- pragma built_in SYN_FEED_THRU + begin + for i in result'range loop + case sv(i) is + when '0' => result(i) := '0'; + when '1' => result(i) := '1'; + when 'L' => result(i) := '0'; + when 'H' => result(i) := '1'; + when 'W' => result(i) := 'W'; + when '-' => result(i) := '-'; + when 'U' => result(i) := 'U'; + when 'X' => result(i) := 'X'; + when 'Z' => result(i) := 'Z'; + end case; + end loop; + return result; + end; + + function tconv ( s : std_ulogic_vector ) return integer is + variable int_result : integer ; + variable int_exp : integer ; + variable new_value : std_ulogic_vector(1 to s'length) ; + variable invalid : boolean ; + -- pragma built_in SYN_UNSIGNED_TO_INTEGER + begin + -- Synopsys translate_off + int_result := 0; + int_exp := 0; + invalid := false ; + new_value := s ; + for i in new_value'length downto 1 loop + case new_value(i) is + when '1' => int_result := int_result + (2**int_exp); + when '0' => null; + when others => + invalid := true; + end case; + int_exp := int_exp + 1; + end loop; + assert not invalid + report "The std_ulogic_Vector input contained values " & + "other than '0' and '1'. They were treated as zeroes." + severity warning; + -- Synopsys translate_on + return int_result; + end tconv ; + +-- Synopsys translate_off + function tconv ( s : std_ulogic_vector ) return string is + alias sv : std_ulogic_vector ( 1 to s'length ) is s; + variable result : string ( 1 to s'length ) := (others => 'X'); + begin + for i in result'range loop + case sv(i) is + when '0' => result(i) := '0'; + when 'L' => result(i) := 'L'; + when '1' => result(i) := '1'; + when 'H' => result(i) := 'H'; + when 'U' => result(i) := 'U'; + when '-' => result(i) := '-'; + when 'W' => result(i) := 'W'; + when 'Z' => result(i) := 'Z'; + when others => result(i) := 'X'; + end case; + end loop; + return result; + end; +-- Synopsys translate_on + +-- Synopsys translate_off + function tconv ( s : std_ulogic_vector; base : base_t ) return string is + alias sv : std_ulogic_vector ( 1 to s'length ) is s; + variable result : string ( 1 to s'length ); + variable start : positive; + variable extra : natural; + variable resultLength : positive; + subtype bv is std_ulogic_vector( 1 to 1 ); + subtype qv is std_ulogic_vector( 1 to 2 ); + subtype ov is std_ulogic_vector( 1 to 3 ); + subtype hv is std_ulogic_vector( 1 to 4 ); + begin + case base is + when bin => + resultLength := sv'length; + start := 1; + for i in start to resultLength loop + case sv( i ) is + when '0' => result( i ) := '0'; + when '1' => result( i ) := '1'; + when 'X' => result( i ) := 'X'; + when 'L' => result( i ) := 'L'; + when 'H' => result( i ) := 'H'; + when 'W' => result( i ) := 'W'; + when '-' => result( i ) := '-'; + when 'U' => result( i ) := 'U'; + when 'Z' => result( i ) := 'Z'; + end case; + end loop; + + when oct => + extra := sv'length rem ov'length; + case extra is + when 0 => + resultLength := s'length/ov'length; + start := 1; + when 1 => + resultLength := ( s'length/ov'length ) + 1; + start := 2; + case sv( 1 ) is + when '0' => result( 1 ) := '0'; + when '1' => result( 1 ) := '1'; + when '-' => result( 1 ) := '-'; + when 'X' => result( 1 ) := 'X'; + when 'U' => result( 1 ) := 'U'; + when 'Z' => result( 1 ) := 'Z'; + when others => result( 1 ) := '.'; + end case; + when 2 => + resultLength := ( s'length/ov'length ) + 1; + start := 2; + case qv'( sv( 1 to 2 ) ) is + when "00" => result( 1 ) := '0'; + when "01" => result( 1 ) := '1'; + when "10" => result( 1 ) := '2'; + when "11" => result( 1 ) := '3'; + when "--" => result( 1 ) := '-'; + when "XX" => result( 1 ) := 'X'; + when "UU" => result( 1 ) := 'U'; + when "ZZ" => result( 1 ) := 'Z'; + when others => result( 1 ) := '.'; + end case; + when others => + assert false report "TCONV fatal condition" severity failure; + end case; + + for i in 0 to resultLength - start loop + case ov'( SV( (ov'length*i)+(extra+1) to (ov'length*i)+(extra+3) ) ) is + when "000" => result( i+start ) := '0'; + when "001" => result( i+start ) := '1'; + when "010" => result( i+start ) := '2'; + when "011" => result( i+start ) := '3'; + when "100" => result( i+start ) := '4'; + when "101" => result( i+start ) := '5'; + when "110" => result( i+start ) := '6'; + when "111" => result( i+start ) := '7'; + when "---" => result( i+start ) := '-'; + when "XXX" => result( i+start ) := 'X'; + when "UUU" => result( i+start ) := 'U'; + when "ZZZ" => result( i+start ) := 'Z'; + when others => result( i+start ) := '.'; + end case; + end loop; + + when hex => + extra := s'length rem hv'length; + case extra is + when 0 => + resultLength := s'length/hv'length; + start := 1; + when 1 => + resultLength := ( s'length/hv'length ) + 1; + start := 2; + case sv( 1 ) is + when '0' => result( 1 ) := '0'; + when '1' => result( 1 ) := '1'; + when '-' => result( 1 ) := '-'; + when 'X' => result( 1 ) := 'X'; + when 'U' => result( 1 ) := 'U'; + when 'Z' => result( 1 ) := 'Z'; + when others => result( 1 ) := '.'; + end case; + when 2 => + resultLength := ( s'length/hv'length ) + 1; + start := 2; + case qv'( sv( 1 to 2 ) ) is + when "00" => result( 1 ) := '0'; + when "01" => result( 1 ) := '1'; + when "10" => result( 1 ) := '2'; + when "11" => result( 1 ) := '3'; + when "--" => result( 1 ) := '-'; + when "XX" => result( 1 ) := 'X'; + when "UU" => result( 1 ) := 'U'; + when "ZZ" => result( 1 ) := 'Z'; + when others => result( 1 ) := '.'; + end case; + when 3 => + resultLength := ( s'length/hv'length ) + 1; + start := 2; + case ov'( sv( 1 to 3 ) ) is + when "000" => result( 1 ) := '0'; + when "001" => result( 1 ) := '1'; + when "010" => result( 1 ) := '2'; + when "011" => result( 1 ) := '3'; + when "100" => result( 1 ) := '4'; + when "101" => result( 1 ) := '5'; + when "110" => result( 1 ) := '6'; + when "111" => result( 1 ) := '7'; + when "---" => result( 1 ) := '-'; + when "XXX" => result( 1 ) := 'X'; + when "UUU" => result( 1 ) := 'U'; + when "ZZZ" => result( 1 ) := 'Z'; + when others => result( 1 ) := '.'; + end case; + when others => + assert false report "TCONV fatal condition" severity failure; + end case; + + for i in 0 to resultLength - start loop + case hv'( SV( (hv'length*i)+(extra+1) to (hv'length*i)+(extra+4) ) ) is + when "0000" => result( i+start ) := '0'; + when "0001" => result( i+start ) := '1'; + when "0010" => result( i+start ) := '2'; + when "0011" => result( i+start ) := '3'; + when "0100" => result( i+start ) := '4'; + when "0101" => result( i+start ) := '5'; + when "0110" => result( i+start ) := '6'; + when "0111" => result( i+start ) := '7'; + when "1000" => result( i+start ) := '8'; + when "1001" => result( i+start ) := '9'; + when "1010" => result( i+start ) := 'A'; + when "1011" => result( i+start ) := 'B'; + when "1100" => result( i+start ) := 'C'; + when "1101" => result( i+start ) := 'D'; + when "1110" => result( i+start ) := 'E'; + when "1111" => result( i+start ) := 'F'; + when "----" => result( i+start ) := '-'; + when "XXXX" => result( i+start ) := 'X'; + when "UUUU" => result( i+start ) := 'U'; + when "ZZZZ" => result( i+start ) := 'Z'; + when others => result( i+start ) := '.'; + end case; + end loop; + + when others => + assert false report "Unsupported base passed." severity warning; + end case; + return result( 1 to resultLength ); + end; +-- Synopsys translate_on + + function tconv ( s : std_ulogic_vector ) return std_ulogic is + alias sv : std_ulogic_vector( 1 to s'length ) is s; + variable result : std_ulogic; + -- pragma built_in SYN_FEED_THRU + begin + case sv(s'length) is + when '0' => return('0'); + when 'L' => return('L'); + when '1' => return('1'); + when 'H' => return('H'); + when 'U' => return('U'); + when 'W' => return('W'); + when '-' => return('-'); + when 'Z' => return('Z'); + when others => return('X'); + end case; + end; + + ------------------------------------------------------------------- + -- std_logic_vector Conversions + ------------------------------------------------------------------- + --function tconv ( s : std_logic_vector ) return bit_vector is + -- alias sv : std_logic_vector ( 1 to s'length ) is s; + -- variable result : bit_vector ( 1 to s'length ) := (others => '0'); + ---- pragma built_in SYN_FEED_THRU + --begin + -- for i in result'range loop + -- case sv(i) is + -- when '0' => result(i) := '0'; + -- when '1' => result(i) := '1'; + -- when 'L' => result(i) := '0'; + -- when 'H' => result(i) := '1'; + -- when others => result(i) := '0'; + -- end case; + -- end loop; + -- return result; + --end; + + --function tconv ( s : std_logic_vector ) return std_ulogic_vector is + -- alias sv : std_logic_vector ( 1 to s'length ) is s; + -- variable result : std_ulogic_vector ( 1 to s'length ) := (others => 'X'); + ---- pragma built_in SYN_FEED_THRU + --begin + -- for i in result'range loop + -- case sv(i) is + -- when '0' => result(i) := '0'; + -- when '1' => result(i) := '1'; + -- when 'L' => result(i) := '0'; + -- when 'H' => result(i) := '1'; + -- when 'W' => result(i) := 'W'; + -- when '-' => result(i) := '-'; + -- when 'U' => result(i) := 'U'; + -- when 'X' => result(i) := 'X'; + -- when 'Z' => result(i) := 'Z'; + -- end case; + -- end loop; + -- return result; + --end; + + --function tconv ( s : std_logic_vector ) return integer is + -- variable int_result : integer := 0; + -- variable int_exp : integer := 0; + -- alias new_value : std_logic_vector(1 to s'length) is s ; + -- variable invalid : boolean := false; + ---- pragma built_in SYN_UNSIGNED_TO_INTEGER + --begin + ---- Synopsys translate_off + -- for i in new_value'length downto 1 loop + -- case new_value(i) is + -- when '1' => int_result := int_result + (2**int_exp); + -- when '0' => null; + -- when others => + -- invalid := true; + -- end case; + -- int_exp := int_exp + 1; + -- end loop; + -- assert not invalid + -- report "The std_logic_Vector input contained values " & + -- "other than '0' and '1'. They were treated as zeroes." + -- severity warning; + ---- Synopsys translate_on + -- return int_result; + --end tconv ; + +-- Synopsys translate_off + --function tconv ( s : std_logic_vector ) return string is + -- alias sv : std_logic_vector ( 1 to s'length ) is s; + -- variable result : string ( 1 to s'length ) := (others => 'X'); + --begin + -- for i in result'range loop + -- case sv(i) is + -- when '0' => result(i) := '0'; + -- when 'L' => result(i) := 'L'; + -- when '1' => result(i) := '1'; + -- when 'H' => result(i) := 'H'; + -- when 'U' => result(i) := 'U'; + -- when '-' => result(i) := '-'; + -- when 'W' => result(i) := 'W'; + -- when 'Z' => result(i) := 'Z'; + -- when others => result(i) := 'X'; + -- end case; + -- end loop; + -- return result; + --end; +-- Synopsys translate_on + +-- Synopsys translate_off + --function tconv ( s : std_logic_vector; base : base_t ) return string is + -- alias sv : std_logic_vector ( 1 to s'length ) is s; + -- variable result : string ( 1 to s'length ); + -- variable start : positive; + -- variable extra : natural; + -- variable resultlength : positive; + -- subtype bv is std_logic_vector( 1 to 1 ); + -- subtype qv is std_logic_vector( 1 to 2 ); + -- subtype ov is std_logic_vector( 1 to 3 ); + -- subtype hv is std_logic_vector( 1 to 4 ); + --begin + -- case base is + -- when bin => + -- resultLength := sv'length; + -- start := 1; + -- for i in start to resultLength loop + -- case sv( i ) is + -- when '0' => result( i ) := '0'; + -- when '1' => result( i ) := '1'; + -- when 'X' => result( i ) := 'X'; + -- when 'L' => result( i ) := 'L'; + -- when 'H' => result( i ) := 'H'; + -- when 'W' => result( i ) := 'W'; + -- when '-' => result( i ) := '-'; + -- when 'U' => result( i ) := 'U'; + -- when 'Z' => result( i ) := 'Z'; + -- end case; + -- end loop; + + -- when oct => + -- extra := sv'length rem ov'length; + -- case extra is + -- when 0 => + -- resultLength := s'length/ov'length; + -- start := 1; + -- when 1 => + -- resultLength := ( s'length/ov'length ) + 1; + -- start := 2; + -- case sv( 1 ) is + -- when '0' => result( 1 ) := '0'; + -- when '1' => result( 1 ) := '1'; + -- when '-' => result( 1 ) := '-'; + -- when 'X' => result( 1 ) := 'X'; + -- when 'U' => result( 1 ) := 'U'; + -- when 'Z' => result( 1 ) := 'Z'; + -- when others => result( 1 ) := '.'; + -- end case; + -- when 2 => + -- resultLength := ( s'length/ov'length ) + 1; + -- start := 2; + -- case qv'( sv( 1 to 2 ) ) is + -- when "00" => result( 1 ) := '0'; + -- when "01" => result( 1 ) := '1'; + -- when "10" => result( 1 ) := '2'; + -- when "11" => result( 1 ) := '3'; + -- when "--" => result( 1 ) := '-'; + -- when "XX" => result( 1 ) := 'X'; + -- when "UU" => result( 1 ) := 'U'; + -- when "ZZ" => result( 1 ) := 'Z'; + -- when others => result( 1 ) := '.'; + -- end case; + -- when others => + -- assert false report "TCONV fatal condition" severity failure; + -- end case; + + -- for i in 0 to resultLength - start loop + -- case ov'( sv( (ov'length*i)+(extra+1) to (ov'length*i)+(extra+3) ) ) is + -- when "000" => result( i+start ) := '0'; + -- when "001" => result( i+start ) := '1'; + -- when "010" => result( i+start ) := '2'; + -- when "011" => result( i+start ) := '3'; + -- when "100" => result( i+start ) := '4'; + -- when "101" => result( i+start ) := '5'; + -- when "110" => result( i+start ) := '6'; + -- when "111" => result( i+start ) := '7'; + -- when "---" => result( i+start ) := '-'; + -- when "XXX" => result( i+start ) := 'X'; + -- when "UUU" => result( i+start ) := 'U'; + -- when "ZZZ" => result( i+start ) := 'Z'; + -- when others => result( i+start ) := '.'; + -- end case; + -- end loop; + + -- when hex => + -- extra := s'length rem hv'length; + -- case extra is + -- when 0 => + -- resultLength := s'length/hv'length; + -- start := 1; + -- when 1 => + -- resultLength := ( s'length/hv'length ) + 1; + -- start := 2; + -- case sv( 1 ) is + -- when '0' => result( 1 ) := '0'; + -- when '1' => result( 1 ) := '1'; + -- when '-' => result( 1 ) := '-'; + -- when 'X' => result( 1 ) := 'X'; + -- when 'U' => result( 1 ) := 'U'; + -- when 'Z' => result( 1 ) := 'Z'; + -- when others => result( 1 ) := '.'; + -- end case; + -- when 2 => + -- resultLength := ( s'length/hv'length ) + 1; + -- start := 2; + -- case qv'( sv( 1 to 2 ) ) is + -- when "00" => result( 1 ) := '0'; + -- when "01" => result( 1 ) := '1'; + -- when "10" => result( 1 ) := '2'; + -- when "11" => result( 1 ) := '3'; + -- when "--" => result( 1 ) := '-'; + -- when "XX" => result( 1 ) := 'X'; + -- when "UU" => result( 1 ) := 'U'; + -- when "ZZ" => result( 1 ) := 'Z'; + -- when others => result( 1 ) := '.'; + -- end case; + -- when 3 => + -- resultLength := ( s'length/hv'length ) + 1; + -- start := 2; + -- case ov'( sv( 1 to 3 ) ) is + -- when "000" => result( 1 ) := '0'; + -- when "001" => result( 1 ) := '1'; + -- when "010" => result( 1 ) := '2'; + -- when "011" => result( 1 ) := '3'; + -- when "100" => result( 1 ) := '4'; + -- when "101" => result( 1 ) := '5'; + -- when "110" => result( 1 ) := '6'; + -- when "111" => result( 1 ) := '7'; + -- when "---" => result( 1 ) := '-'; + -- when "XXX" => result( 1 ) := 'X'; + -- when "UUU" => result( 1 ) := 'U'; + -- when "ZZZ" => result( 1 ) := 'Z'; + -- when others => result( 1 ) := '.'; + -- end case; + -- when others => + -- assert false report "TCONV fatal condition" severity failure; + -- end case; + + -- for i in 0 to resultLength - start loop + -- case hv'( SV( (hv'length*i)+(extra+1) to (hv'length*i)+(extra+4) ) ) is + -- when "0000" => result( i+start ) := '0'; + -- when "0001" => result( i+start ) := '1'; + -- when "0010" => result( i+start ) := '2'; + -- when "0011" => result( i+start ) := '3'; + -- when "0100" => result( i+start ) := '4'; + -- when "0101" => result( i+start ) := '5'; + -- when "0110" => result( i+start ) := '6'; + -- when "0111" => result( i+start ) := '7'; + -- when "1000" => result( i+start ) := '8'; + -- when "1001" => result( i+start ) := '9'; + -- when "1010" => result( i+start ) := 'A'; + -- when "1011" => result( i+start ) := 'B'; + -- when "1100" => result( i+start ) := 'C'; + -- when "1101" => result( i+start ) := 'D'; + -- when "1110" => result( i+start ) := 'E'; + -- when "1111" => result( i+start ) := 'F'; + -- when "----" => result( i+start ) := '-'; + -- when "XXXX" => result( i+start ) := 'X'; + -- when "UUUU" => result( i+start ) := 'U'; + -- when "ZZZZ" => result( i+start ) := 'Z'; + -- when others => result( i+start ) := '.'; + -- end case; + -- end loop; + + -- when others => + -- assert false report "Unsupported base passed." severity warning; + -- end case; + -- return result( 1 to resultLength ); + --end; +-- Synopsys translate_on + +-- Synopsys translate_off + function hexstring( d : std_ulogic_vector ) return string is + variable nd : + Std_Ulogic_vector( 0 to ((d'length + (4 - (d'length mod 4))) - 1) ) := ( others => '0' ); + variable r : string(1 to (nd'length/4)); + variable hexsize : integer; + variable offset : integer; + subtype iv4 is Std_Ulogic_vector(1 to 4); + begin + + offset := d'length mod 4; + + if offset = 0 then + hexsize := d'length / 4; + nd( 0 to d'length - 1 ) := d; + else + hexsize := nd'length / 4; + nd( ( nd'left + (4 - offset) ) to nd'right ) := d; + end if; + + for i in 0 to hexsize - 1 loop + + case iv4( nd( ( i * 4 ) to ( ( i * 4 ) + 3 ) ) ) is + when "0000" => r(i + 1) := '0'; + when "0001" => r(i + 1) := '1'; + when "0010" => r(i + 1) := '2'; + when "0011" => r(i + 1) := '3'; + when "0100" => r(i + 1) := '4'; + when "0101" => r(i + 1) := '5'; + when "0110" => r(i + 1) := '6'; + when "0111" => r(i + 1) := '7'; + when "1000" => r(i + 1) := '8'; + when "1001" => r(i + 1) := '9'; + when "1010" => r(i + 1) := 'A'; + when "1011" => r(i + 1) := 'B'; + when "1100" => r(i + 1) := 'C'; + when "1101" => r(i + 1) := 'D'; + when "1110" => r(i + 1) := 'E'; + when "1111" => r(i + 1) := 'F'; + when "----" => r(i + 1) := '-'; + when "XXXX" => r(i + 1) := 'X'; + when "UUUU" => r(i + 1) := 'U'; + when "ZZZZ" => r(i + 1) := 'Z'; + when others => r(i + 1) := '.'; + end case; + + end loop; + + return r(1 to hexsize); + end hexstring; +-- Synopsys translate_on + +-- Synopsys translate_off + function octstring( d : std_ulogic_vector ) return string is + variable nd : + Std_Ulogic_vector( 0 to ((d'length + (3 - (d'length mod 3))) - 1) ) := ( others => '0' ); + variable offset : integer; + variable r : string(1 to (nd'length/3)); + variable octsize : integer; + subtype iv3 is Std_Ulogic_vector(1 to 3); + begin + + offset := d'length mod 3; + + if offset = 0 then + octsize := d'length / 3; + nd( 0 to d'length - 1 ) := d; + else + octsize := nd'length / 3; + nd( ( nd'left + (3 - offset) ) to nd'right ) := d; + end if; + + for i in 0 to octsize - 1 loop + + case iv3( nd( ( i * 3 ) to ( ( i * 3 ) + 2 ) ) ) is + when "000" => r(i + 1) := '0'; + when "001" => r(i + 1) := '1'; + when "010" => r(i + 1) := '2'; + when "011" => r(i + 1) := '3'; + when "100" => r(i + 1) := '4'; + when "101" => r(i + 1) := '5'; + when "110" => r(i + 1) := '6'; + when "111" => r(i + 1) := '7'; + when "---" => r(i + 1) := '-'; + when "XXX" => r(i + 1) := 'X'; + when "UUU" => r(i + 1) := 'U'; + when "ZZZ" => r(i + 1) := 'Z'; + when others => r(i + 1) := '.'; + end case; + + end loop; + + return r; + end octstring; +-- Synopsys translate_on + +-- Synopsys translate_off + function bitstring( d : std_ulogic_vector ) return string is + variable nd : + Std_Ulogic_vector(0 to ( d'length - 1 ) ) := ( others => '0' ); + variable r : string(1 to (nd'length)); + begin + nd := d; + for i in nd'range loop + r(i + 1) := std_ulogic_to_character( nd(i) ); + end loop; + return r; + end bitstring; +-- Synopsys translate_on + + ------------------------------------------------------------------- + -- Std_Match functions + ------------------------------------------------------------------- + constant no_warning: boolean := false; -- default to emit warnings + + -- Id: M.1a + function std_match (l, r: std_ulogic) return std_ulogic is + begin + if (l ?= r) then + return '1' ; + else + return '0' ; + end if ; + end std_match; + + -- Id: M.4b + function std_match (l, r: std_ulogic_vector) return std_ulogic is + variable result : boolean ; + begin + if (l ?= r) then + return '1' ; + else + return '0' ; + end if; + end std_match; + + ------------------------------------------------------------------- + -- Overloaded Relational Operators returning std_ulogic + ------------------------------------------------------------------- + function "=" ( l,r : integer ) return std_ulogic is + -- pragma built_in SYN_EQL + begin + if (l - r) = 0 then + return ('1'); + else + return ('0'); + end if ; + end "="; + + function "/=" ( l,r : integer ) return std_ulogic is + -- pragma built_in SYN_NEQ + begin + if (l - r) = 0 then + return ('0'); + else + return ('1'); + end if ; + end "/="; + + function ">" ( l,r : integer ) return std_ulogic is + -- pragma built_in SYN_GT + begin + if (l - r) > 0 then + return ('1'); + else + return ('0'); + end if ; + end ">"; + + function ">=" ( l,r : integer ) return std_ulogic is + -- pragma built_in SYN_GEQ + begin + if (l - r) >= 0 then + return ('1'); + else + return ('0'); + end if ; + end ">="; + + function "<" ( l,r : integer ) return std_ulogic is + -- pragma built_in SYN_LT + begin + if (r - l) > 0 then + return ('1'); + else + return ('0'); + end if ; + end "<"; + + function "<=" ( l,r : integer ) return std_ulogic is + -- pragma built_in SYN_LEQ + begin + if (r - l) >= 0 then + return ('1'); + else + return ('0'); + end if ; + end "<="; + + ------------------------------------------------------------------- + -- Overloaded Relational Operators returning STD_uLogic + ------------------------------------------------------------------- + function "=" ( l,r : std_ulogic ) return std_ulogic is + -- pragma built_in SYN_EQL + begin + return ( tconv( l = r ) ); + end "="; + + function "/=" ( l,r : std_ulogic ) return std_ulogic is + -- pragma built_in SYN_NEQ + begin + return ( tconv( l /= r ) ); + end "/="; + + function ">" ( l,r : std_ulogic ) return std_ulogic is + -- pragma built_in SYN_GT + begin + return ( tconv( l > r ) ); + end ">"; + + function ">=" ( l,r : std_ulogic ) return std_ulogic is + -- pragma built_in SYN_GEQ + begin + return ( tconv( l >= r ) ); + end ">="; + + function "<" ( l,r : std_ulogic ) return std_ulogic is + -- pragma built_in SYN_LT + begin + return ( tconv( l < r ) ); + end "<"; + + function "<=" ( l,r : std_ulogic ) return std_ulogic is + -- pragma built_in SYN_LEQ + begin + return ( tconv( l <= r ) ); + end "<="; + + ------------------------------------------------------------------- + -- Overloaded Relational Operators returning STD_uLogic + ------------------------------------------------------------------- + + function "=" ( l,r : std_ulogic_vector) return std_ulogic is + -- pragma built_in SYN_EQL + begin + -- Synopsys translate_off + if l'length /= r'length then + assert false + report "The bit lengths of the two inputs to the = " & + "operator are unequal. " + severity error; + return '0' ; + end if ; + -- Synopsys translate_on + return ( tconv( l = r ) ); + end "="; + + ------------------------------------------------------------------- + function "/=" ( l,r : std_ulogic_vector) return std_ulogic is + -- pragma built_in SYN_NEQ + begin + -- Synopsys translate_off + if l'length /= r'length then + assert false + report "The bit lengths of the two inputs to the /= " & + "operator are unequal. " + severity error; + return '0' ; + end if ; + -- Synopsys translate_on + return ( tconv( l /= r ) ); + end "/="; + + ------------------------------------------------------------------- + function ">" ( l,r : std_ulogic_vector) return std_ulogic is + -- pragma built_in SYN_GT + begin + -- Synopsys translate_off + if l'length /= r'length then + assert false + report "The bit lengths of the two inputs to the > " & + "operator are unequal. " + severity error; + return '0' ; + end if ; + -- Synopsys translate_on + return ( tconv( l > r ) ); + end ">"; + + ------------------------------------------------------------------- + function ">=" ( l,r : std_ulogic_vector) return std_ulogic is + -- pragma built_in SYN_GEQ + begin + -- Synopsys translate_off + if l'length /= r'length then + assert false + report "The bit lengths of the two inputs to the >= " & + "operator are unequal. " + severity error; + return '0' ; + end if ; + -- Synopsys translate_on + return ( tconv( l >= r ) ); + end ">="; + + ------------------------------------------------------------------- + function "<" ( l,r : std_ulogic_vector) return std_ulogic is + -- pragma built_in SYN_LT + begin + -- Synopsys translate_off + if l'length /= r'length then + assert false + report "The bit lengths of the two inputs to the < " & + "operator are unequal. " + severity error; + return '0' ; + end if ; + -- Synopsys translate_on + return ( tconv( l < r ) ); + end "<"; + + ------------------------------------------------------------------- + function "<=" ( l,r : std_ulogic_vector) return std_ulogic is + -- pragma built_in SYN_LEQ + begin + -- Synopsys translate_off + if l'length /= r'length then + assert false + report "The bit lengths of the two inputs to the <= " & + "operator are unequal. " + severity error; + return '0' ; + end if ; + -- Synopsys translate_on + return ( tconv( l <= r ) ); + end "<="; + +--============================================================== + -- Shift and Rotate Functions +--============================================================== +----------Local Subprograms - shift/rotate ops------------------- + -- Synopsys translate_off + constant NAU: std_ulogic_vector(0 downto 1) := (others => '0'); + -- Synopsys translate_on + + function xsll (arg: std_ulogic_vector; count: natural) return std_ulogic_vector + is + constant arg_l: integer := arg'length-1; + alias xarg: std_ulogic_vector(arg_l downto 0) is arg; + variable result: std_ulogic_vector(arg_l downto 0) ; + -- pragma built_in SYN_SLLU + begin + result := (others => '0'); + if count <= arg_l then + result(arg_l downto count) := xarg(arg_l-count downto 0); + end if; + return result; + end xsll; + + function xsrl (arg: std_ulogic_vector; count: natural) return std_ulogic_vector + is + constant arg_l: integer := arg'length-1; + alias xarg: std_ulogic_vector(arg_l downto 0) is arg; + variable result: std_ulogic_vector(arg_l downto 0) ; + -- pragma built_in SYN_SRLU + begin + result := (others => '0'); + if count <= arg_l then + result(arg_l-count downto 0) := xarg(arg_l downto count); + end if; + return result; + end xsrl; + + function xsra (arg: std_ulogic_vector; count: natural) return std_ulogic_vector + is + constant arg_l: integer := arg'length-1; + alias xarg: std_ulogic_vector(arg_l downto 0) is arg; + variable result: std_ulogic_vector(arg_l downto 0); + variable xcount: natural ; + -- pragma built_in SYN_SHR + begin + xcount := count; + if ((arg'length <= 1) or (xcount = 0)) then return arg; + else + if (xcount > arg_l) then xcount := arg_l; + end if; + result(arg_l-xcount downto 0) := xarg(arg_l downto xcount); + result(arg_l downto (arg_l - xcount + 1)) := (others => xarg(arg_l)); + end if; + return result; + end xsra; + + function xrol (arg: std_ulogic_vector; count: natural) return std_ulogic_vector + is + constant arg_l: integer := arg'length-1; + alias xarg: std_ulogic_vector(arg_l downto 0) is arg; + variable result: std_ulogic_vector(arg_l downto 0) ; + variable countm: integer; + -- pragma built_in SYN_ROLU + begin + result := xarg; + countm := count mod (arg_l + 1); + if countm /= 0 then + result(arg_l downto countm) := xarg(arg_l-countm downto 0); + result(countm-1 downto 0) := xarg(arg_l downto arg_l-countm+1); + end if; + return result; + end xrol; + + function xror (arg: std_ulogic_vector; count: natural) return std_ulogic_vector + is + constant arg_l: integer := arg'length-1; + alias xarg: std_ulogic_vector(arg_l downto 0) is arg; + variable result: std_ulogic_vector(arg_l downto 0) ; + variable countm: integer; + -- pragma built_in SYN_RORU + begin + countm := count mod (arg_l + 1); + result := xarg; + if countm /= 0 then + result(arg_l-countm downto 0) := xarg(arg_l downto countm); + result(arg_l downto arg_l-countm+1) := xarg(countm-1 downto 0); + end if; + return result; + end xror; + +--=================================================================== + + -- Id: S.1 + function shift_left (arg: std_ulogic_vector; count: natural) return std_ulogic_vector is + -- pragma built_in SYN_SLLU + begin + -- Synopsys translate_off + if (arg'length < 1) then return NAU; + end if; + -- Synopsys translate_on + return std_ulogic_vector( xsll( std_ulogic_vector(arg), count ) ); + end shift_left; + + -- Id: S.2 + function shift_right (arg: std_ulogic_vector; count: natural) return std_ulogic_vector is + -- pragma built_in SYN_SRLU + begin + -- Synopsys translate_off + if (arg'length < 1) then return NAU; + end if; + -- Synopsys translate_on + return std_ulogic_vector( xsrl( std_ulogic_vector(arg), count ) ); + end shift_right; + + + -- Id: S.5 + function rotate_left (arg: std_ulogic_vector; count: natural) return std_ulogic_vector is + -- pragma built_in SYN_ROLU + begin + -- Synopsys translate_off + if (arg'length < 1) then return NAU; + end if; + -- Synopsys translate_on + return std_ulogic_vector( xrol( std_ulogic_vector(arg), count ) ); + end rotate_left; + + -- Id: S.6 + function rotate_right (arg: std_ulogic_vector; count: natural) return std_ulogic_vector is + -- pragma built_in SYN_RORU + begin + -- Synopsys translate_off + if (arg'length < 1) then return NAU; + end if; + -- Synopsys translate_on + return std_ulogic_vector( xror( std_ulogic_vector(arg), count ) ); + end rotate_right; + + -- Id: S.9 + function "sll" (arg: std_ulogic_vector; count: integer) return std_ulogic_vector is + -- pragma built_in SYN_SLL + begin + if (count >= 0) then + return shift_left(arg, count); + else + return shift_right(arg, -count); + end if; + end "sll"; + + -- Id: S.11 + function "srl" (arg: std_ulogic_vector; count: integer) return std_ulogic_vector is + -- pragma built_in SYN_SRL + begin + if (count >= 0) then + return shift_right(arg, count); + else + return shift_left(arg, -count); + end if; + end "srl"; + + -- Id: S.13 + function "rol" (arg: std_ulogic_vector; count: integer) return std_ulogic_vector is + -- pragma built_in SYN_ROL + begin + if (count >= 0) then + return rotate_left(arg, count); + else + return rotate_right(arg, -count); + end if; + end "rol"; + + -- Id: S.15 + function "ror" (arg: std_ulogic_vector; count: integer) return std_ulogic_vector is + -- pragma built_in SYN_ROR + begin + if (count >= 0) then + return rotate_right(arg, count); + else + return rotate_left(arg, -count); + end if; + end "ror"; + +--============================================================== + --End Shift and Rotate Functions +--============================================================== + +end std_ulogic_support ; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/ibm/std_ulogic_unsigned.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/ibm/std_ulogic_unsigned.vhdl new file mode 100644 index 0000000..bcd9c26 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/ibm/std_ulogic_unsigned.vhdl @@ -0,0 +1,374 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +--*************************************************************************** +-- Copyright 2020 International Business Machines +-- +-- Licensed under the Apache License, Version 2.0 (the “License”); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- The patent license granted to you in Section 3 of the License, as applied +-- to the “Work,” hereby includes implementations of the Work in physical form. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an “AS IS” BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- +--*************************************************************************** +library IEEE, IBM; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use IBM.std_ulogic_support.all; + +package std_ulogic_unsigned is + + function "+"(l: std_ulogic_vector; r: std_ulogic_vector) return std_ulogic_vector; + function "+"(l: std_ulogic_vector; r: integer) return std_ulogic_vector; + function "+"(l: integer; r: std_ulogic_vector) return std_ulogic_vector; + function "+"(l: std_ulogic_vector; r: std_ulogic) return std_ulogic_vector; + function "+"(l: std_ulogic; r: std_ulogic_vector) return std_ulogic_vector; + + function "-"(l: std_ulogic_vector; r: std_ulogic_vector) return std_ulogic_vector; + function "-"(l: std_ulogic_vector; r: integer) return std_ulogic_vector; + function "-"(l: integer; r: std_ulogic_vector) return std_ulogic_vector; + function "-"(l: std_ulogic_vector; r: std_ulogic) return std_ulogic_vector; + function "-"(l: std_ulogic; r: std_ulogic_vector) return std_ulogic_vector; + + function "+"(l: std_ulogic_vector) return std_ulogic_vector; + + function "*"(l: std_ulogic_vector; r: std_ulogic_vector) return std_ulogic_vector; + + function "=" ( l : natural; r : std_ulogic_vector) return boolean; + function "/="( l : natural; r : std_ulogic_vector) return boolean; + function "<" ( l : natural; r : std_ulogic_vector) return boolean; + function "<="( l : natural; r : std_ulogic_vector) return boolean; + function ">" ( l : natural; r : std_ulogic_vector) return boolean; + function ">="( l : natural; r : std_ulogic_vector) return boolean; + + function "=" ( l : std_ulogic_vector; r : natural) return boolean; + function "/="( l : std_ulogic_vector; r : natural) return boolean; + function "<" ( l : std_ulogic_vector; r : natural) return boolean; + function "<="( l : std_ulogic_vector; r : natural) return boolean; + function ">" ( l : std_ulogic_vector; r : natural) return boolean; + function ">="( l : std_ulogic_vector; r : natural) return boolean; + + function "=" ( l : natural; r : std_ulogic_vector) return std_ulogic; + function "/="( l : natural; r : std_ulogic_vector) return std_ulogic; + function "<" ( l : natural; r : std_ulogic_vector) return std_ulogic; + function "<="( l : natural; r : std_ulogic_vector) return std_ulogic; + function ">" ( l : natural; r : std_ulogic_vector) return std_ulogic; + function ">="( l : natural; r : std_ulogic_vector) return std_ulogic; + + function "=" ( l : std_ulogic_vector; r : natural) return std_ulogic; + function "/="( l : std_ulogic_vector; r : natural) return std_ulogic; + function "<" ( l : std_ulogic_vector; r : natural) return std_ulogic; + function "<="( l : std_ulogic_vector; r : natural) return std_ulogic; + function ">" ( l : std_ulogic_vector; r : natural) return std_ulogic; + function ">="( l : std_ulogic_vector; r : natural) return std_ulogic; + + function to_integer( d : std_ulogic_vector ) return natural; + -- synopsys translate_off + attribute type_convert of to_integer : function is true; + attribute btr_name of to_integer : function is "PASS"; + attribute pin_bit_information of to_integer : function is + (1 => (" ","A0 ","INCR","PIN_BIT_SCALAR"), + 2 => (" ","10 ","INCR","PIN_BIT_SCALAR")); + -- synopsys translate_on + + -- synopsys translate_off + function to_std_ulogic_vector( d : natural; w : positive ) return std_ulogic_vector; + attribute type_convert of to_std_ulogic_vector : function is true; + attribute btr_name of to_std_ulogic_vector : function is "PASS"; + attribute pin_bit_information of to_std_ulogic_vector : function is + (1 => (" ","A0 ","INCR","PIN_BIT_SCALAR"), + 2 => (" ","10 ","INCR","PIN_BIT_SCALAR")); + -- synopsys translate_on + +end std_ulogic_unsigned; + +package body std_ulogic_unsigned is + + function maximum(L, R: INTEGER) return INTEGER is + begin + if L > R then + return L; + else + return R; + end if; + end; + + function "+"(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is + constant length : INTEGER := maximum(L'length, R'length); + variable result : UNSIGNED(length-1 downto 0); + -- pragma label_applies_to plus + begin + result := UNSIGNED(L) + UNSIGNED(R); -- pragma label plus + return std_ulogic_vector(result); + end; + + function "+"(L: STD_ULOGIC_VECTOR; R: INTEGER) return STD_ULOGIC_VECTOR is + variable result : STD_ULOGIC_VECTOR (L'range); + -- pragma label_applies_to plus + begin + result := std_ulogic_vector( UNSIGNED(L) + R ); -- pragma label plus + return result ; + end; + + function "+"(L: INTEGER; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is + variable result : STD_ULOGIC_VECTOR (R'range); + -- pragma label_applies_to plus + begin + result := std_ulogic_vector( L + UNSIGNED(R) ); -- pragma label plus + return result; + end; + + function "+"(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC) return STD_ULOGIC_VECTOR is + variable result : STD_ULOGIC_VECTOR (L'range); + -- pragma label_applies_to plus + begin + if R = '1' then + result := std_ulogic_vector( UNSIGNED(L) + 1 ); + else + result := L; + end if; + return result ; + end; + + function "+"(L: STD_ULOGIC; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is + variable result : STD_ULOGIC_VECTOR (R'range); + -- pragma label_applies_to plus + begin + if L = '1' then + result := std_ulogic_vector( UNSIGNED(R) + 1 ); + else + result := R; + end if; + return result ; + end; + + function "+"(L: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is + variable result : STD_ULOGIC_VECTOR (L'range); + -- pragma label_applies_to plus + begin + result := L; + return result ; + end; + + function "-"(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is + constant length: INTEGER := maximum(L'length, R'length); + variable result : STD_ULOGIC_VECTOR (length-1 downto 0); + -- pragma label_applies_to minus + begin + result := std_ulogic_vector( UNSIGNED(L) - UNSIGNED(R) ); -- pragma label minus + return result ; + end; + + function "-"(L: STD_ULOGIC_VECTOR; R: INTEGER) return STD_ULOGIC_VECTOR is + variable result : STD_ULOGIC_VECTOR (L'range); + -- pragma label_applies_to minus + begin + result := std_ulogic_vector( UNSIGNED(L) - R ); -- pragma label minus + return result ; + end; + + function "-"(L: INTEGER; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is + variable result : STD_ULOGIC_VECTOR (R'range); + -- pragma label_applies_to minus + begin + result := std_ulogic_vector( L - UNSIGNED(R) ); -- pragma label minus + return result ; + end; + + function "-"(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC) return STD_ULOGIC_VECTOR is + variable result : STD_ULOGIC_VECTOR (L'range); + -- pragma label_applies_to minus + begin + if R = '1' then + result := std_ulogic_vector( UNSIGNED(L) - 1 ); + else + result := L; + end if; + return result ; + end; + + function "-"(L: STD_ULOGIC; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is + variable result : STD_ULOGIC_VECTOR (R'range); + -- pragma label_applies_to minus + begin + if L = '1' then + result := std_ulogic_vector( 1 - UNSIGNED(R) ); + else + result := std_ulogic_vector( 0 - UNSIGNED(R) ); + end if; + return result ; + end; + + function "*"(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is + constant length: INTEGER := maximum(L'length, R'length); + variable result : STD_ULOGIC_VECTOR ((L'length+R'length-1) downto 0); + -- pragma label_applies_to mult + begin + result := std_ulogic_vector( UNSIGNED(L) * UNSIGNED(R) ); -- pragma label mult + return result ; + end; + + function "=" ( l : natural; r : std_ulogic_vector) return boolean is + begin + return l = unsigned(r); + end "="; + + function "/="( l : natural; r : std_ulogic_vector) return boolean is + begin + return l /= unsigned(r); + end "/="; + + function "<" ( l : natural; r : std_ulogic_vector) return boolean is + begin + return l < unsigned(r); + end "<"; + + function "<="( l : natural; r : std_ulogic_vector) return boolean is + begin + return l <= unsigned(r); + end "<="; + + function ">" ( l : natural; r : std_ulogic_vector) return boolean is + begin + return l > unsigned(r); + end ">"; + + function ">="( l : natural; r : std_ulogic_vector) return boolean is + begin + return l >= unsigned(r); + end ">="; + + function "=" ( l : std_ulogic_vector; r : natural) return boolean is + begin + return unsigned(l) = r; + end "="; + + function "/="( l : std_ulogic_vector; r : natural) return boolean is + begin + return unsigned(l) /= r; + end "/="; + + function "<" ( l : std_ulogic_vector; r : natural) return boolean is + begin + return unsigned(l) < r; + end "<"; + + function "<="( l : std_ulogic_vector; r : natural) return boolean is + begin + return unsigned(l) <= r; + end "<="; + + function ">" ( l : std_ulogic_vector; r : natural) return boolean is + begin + return unsigned(l) > r; + end ">"; + + function ">="( l : std_ulogic_vector; r : natural) return boolean is + begin + return unsigned(l) >= r; + end ">="; + + function "=" ( l : natural; r : std_ulogic_vector) return std_ulogic is + begin + return tconv( l = unsigned(r) ); + end "="; + + function "/="( l : natural; r : std_ulogic_vector) return std_ulogic is + begin + return tconv( l /= unsigned(r) ); + end "/="; + + function "<" ( l : natural; r : std_ulogic_vector) return std_ulogic is + begin + return tconv( l < unsigned(r) ); + end "<"; + + function "<="( l : natural; r : std_ulogic_vector) return std_ulogic is + begin + return tconv( l <= unsigned(r) ); + end "<="; + + function ">" ( l : natural; r : std_ulogic_vector) return std_ulogic is + begin + return tconv( l > unsigned(r) ); + end ">"; + + function ">="( l : natural; r : std_ulogic_vector) return std_ulogic is + begin + return tconv( l >= unsigned(r) ); + end ">="; + + function "=" ( l : std_ulogic_vector; r : natural) return std_ulogic is + begin + return tconv( unsigned(l) = r ); + end "="; + + function "/="( l : std_ulogic_vector; r : natural) return std_ulogic is + begin + return tconv( unsigned(l) /= r ); + end "/="; + + function "<" ( l : std_ulogic_vector; r : natural) return std_ulogic is + begin + return tconv( unsigned(l) < r ); + end "<"; + + function "<="( l : std_ulogic_vector; r : natural) return std_ulogic is + begin + return tconv( unsigned(l) <= r ); + end "<="; + + function ">" ( l : std_ulogic_vector; r : natural) return std_ulogic is + begin + return tconv( unsigned(l) > r ); + end ">"; + + function ">="( l : std_ulogic_vector; r : natural) return std_ulogic is + begin + return tconv( unsigned(l) >= r ); + end ">="; + + function to_integer( d : std_ulogic_vector ) return natural is + begin + return tconv( d ); + end to_integer; + + function to_std_ulogic_vector( d : natural; w : positive ) return std_ulogic_vector is + begin + return tconv( d, w ); + end to_std_ulogic_vector; + +end std_ulogic_unsigned; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/support/power_logic_pkg.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/support/power_logic_pkg.vhdl new file mode 100644 index 0000000..eafa752 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/support/power_logic_pkg.vhdl @@ -0,0 +1,38 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee; +use ieee.std_logic_1164.all; + +package power_logic_pkg is + + subtype power_logic is std_logic; + subtype power_logic_vector is std_logic_vector; + +end package power_logic_pkg; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/ramb16_s18_s18.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/ramb16_s18_s18.vhdl new file mode 100644 index 0000000..9562068 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/ramb16_s18_s18.vhdl @@ -0,0 +1,360 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; +use ieee.std_logic_1164.all; + +library ibm; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; + +library UNISIM; +use UNISIM.vcomponents.all; + +library UNIMACRO; +use UNIMACRO.vcomponents.all; + +entity RAMB16_S18_S18 is + generic ( + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_A : bit_vector := X"000000000"; + INIT_B : bit_vector := X"000000000"; + SIM_COLLISION_CHECK : string := "ALL"; + SRVAL_A : bit_vector := X"000000000"; + SRVAL_B : bit_vector := X"000000000"; + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + port ( + DOA : out std_logic_vector(15 downto 0); + DOB : out std_logic_vector(15 downto 0); + DOPA : out std_logic_vector(1 downto 0); + DOPB : out std_logic_vector(1 downto 0); + ADDRA : in std_logic_vector(9 downto 0); + ADDRB : in std_logic_vector(9 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(15 downto 0); + DIB : in std_logic_vector(15 downto 0); + DIPA : in std_logic_vector(1 downto 0); + DIPB : in std_logic_vector(1 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); +end RAMB16_S18_S18; + +architecture RAMB16_S18_S18 of RAMB16_S18_S18 is + +signal DINA, DINB : std_logic_vector(17 downto 0); +signal DOUTA, DOUTB : std_logic_vector(17 downto 0); +signal SSRA_t, SSRB_t : std_logic; +signal WEA_t, WEB_t : std_logic_vector(1 downto 0); + +begin + +DINA <= DIPA & DIA; +DOPA <= DOUTA(17 downto 16); +DOA <= DOUTA(15 downto 0); + +DINB <= DIPB & DIB; +DOPB <= DOUTB(17 downto 16); +DOB <= DOUTB(15 downto 0); + +SSRA_t <= SSRA; +SSRB_t <= SSRB; +WEA_t <= WEA & WEA; +WEB_t <= WEB & WEB; + + + + + + BRAM_0 : BRAM_TDP_MACRO + generic map ( + BRAM_SIZE => "18Kb", + DEVICE => "7SERIES", + DOA_REG => 0, + DOB_REG => 0, + INIT_A => INIT_A, + INIT_B => INIT_B, + INIT_FILE => "NONE", + READ_WIDTH_A => 18, + READ_WIDTH_B => 18, + SIM_COLLISION_CHECK => "NONE", + SRVAL_A => SRVAL_A, + SRVAL_B => SRVAL_A, + WRITE_MODE_A => WRITE_MODE_A, + WRITE_MODE_B => WRITE_MODE_B, + WRITE_WIDTH_A => 18, + WRITE_WIDTH_B => 18, + INIT_00 => INIT_00, + INIT_01 => INIT_01, + INIT_02 => INIT_02, + INIT_03 => INIT_03, + INIT_04 => INIT_04, + INIT_05 => INIT_05, + INIT_06 => INIT_06, + INIT_07 => INIT_07, + INIT_08 => INIT_08, + INIT_09 => INIT_09, + INIT_0A => INIT_0A, + INIT_0B => INIT_0B, + INIT_0C => INIT_0C, + INIT_0D => INIT_0D, + INIT_0E => INIT_0E, + INIT_0F => INIT_0F, + INIT_10 => INIT_10, + INIT_11 => INIT_11, + INIT_12 => INIT_12, + INIT_13 => INIT_13, + INIT_14 => INIT_14, + INIT_15 => INIT_15, + INIT_16 => INIT_16, + INIT_17 => INIT_17, + INIT_18 => INIT_18, + INIT_19 => INIT_19, + INIT_1A => INIT_1A, + INIT_1B => INIT_1B, + INIT_1C => INIT_1C, + INIT_1D => INIT_1D, + INIT_1E => INIT_1E, + INIT_1F => INIT_1F, + INIT_20 => INIT_20, + INIT_21 => INIT_21, + INIT_22 => INIT_22, + INIT_23 => INIT_23, + INIT_24 => INIT_24, + INIT_25 => INIT_25, + INIT_26 => INIT_26, + INIT_27 => INIT_27, + INIT_28 => INIT_28, + INIT_29 => INIT_29, + INIT_2A => INIT_2A, + INIT_2B => INIT_2B, + INIT_2C => INIT_2C, + INIT_2D => INIT_2D, + INIT_2E => INIT_2E, + INIT_2F => INIT_2F, + INIT_30 => INIT_30, + INIT_31 => INIT_31, + INIT_32 => INIT_32, + INIT_33 => INIT_33, + INIT_34 => INIT_34, + INIT_35 => INIT_35, + INIT_36 => INIT_36, + INIT_37 => INIT_37, + INIT_38 => INIT_38, + INIT_39 => INIT_39, + INIT_3A => INIT_3A, + INIT_3B => INIT_3B, + INIT_3C => INIT_3C, + INIT_3D => INIT_3D, + INIT_3E => INIT_3E, + INIT_3F => INIT_3F, + + INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", + + INITP_00 => INITP_00, + INITP_01 => INITP_01, + INITP_02 => INITP_02, + INITP_03 => INITP_03, + INITP_04 => INITP_04, + INITP_05 => INITP_05, + INITP_06 => INITP_06, + INITP_07 => INITP_07, + + INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000" + ) + port map ( + DOA => DOUTA, + DOB => DOUTB, + ADDRA => ADDRA, + ADDRB => ADDRB, + CLKA => CLKA, + CLKB => CLKB, + DIA => DINA, + DIB => DINB, + ENA => ENA, + ENB => ENB, + REGCEA => '1', + REGCEB => '1', + RSTA => SSRA_t, + RSTB => SSRB_t, + WEA => WEA_t, + WEB => WEB_t + ); + + + +end RAMB16_S18_S18; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/ramb16_s36_s36.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/ramb16_s36_s36.vhdl new file mode 100644 index 0000000..ea9362d --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/ramb16_s36_s36.vhdl @@ -0,0 +1,364 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; +use ieee.std_logic_1164.all; + +library ibm; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; + +library UNISIM; +use UNISIM.vcomponents.all; + +library UNIMACRO; +use UNIMACRO.vcomponents.all; + +entity RAMB16_S36_S36 is + generic ( + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_A : bit_vector := X"000000000"; + INIT_B : bit_vector := X"000000000"; + SIM_COLLISION_CHECK : string := "ALL"; + SRVAL_A : bit_vector := X"000000000"; + SRVAL_B : bit_vector := X"000000000"; + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + port ( + DOA : out std_logic_vector(31 downto 0); + DOB : out std_logic_vector(31 downto 0); + DOPA : out std_logic_vector(3 downto 0); + DOPB : out std_logic_vector(3 downto 0); + ADDRA : in std_logic_vector(8 downto 0); + ADDRB : in std_logic_vector(8 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(31 downto 0); + DIB : in std_logic_vector(31 downto 0); + DIPA : in std_logic_vector(3 downto 0); + DIPB : in std_logic_vector(3 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); +end RAMB16_S36_S36; + +architecture RAMB16_S36_S36 of RAMB16_S36_S36 is + +signal ADDRA_10, ADDRB_10 : std_logic_vector(9 downto 0); +signal DINA, DINB : std_logic_vector(35 downto 0); +signal DOUTA, DOUTB : std_logic_vector(35 downto 0); +signal SSRA_t, SSRB_t : std_logic; +signal WEA_t, WEB_t : std_logic_vector(3 downto 0); + +begin + +ADDRA_10 <= '0' & ADDRA; +ADDRB_10 <= '0' & ADDRB; + +DINA <= DIPA & DIA; +DOPA <= DOUTA(35 downto 32); +DOA <= DOUTA(31 downto 0); + +DINB <= DIPB & DIB; +DOPB <= DOUTB(35 downto 32); +DOB <= DOUTB(31 downto 0); + +SSRA_t <= SSRA; +SSRB_t <= SSRB; +WEA_t <= WEA & WEA & WEA & WEA; +WEB_t <= WEB & WEB & WEB & WEB; + + + + + + BRAM_0 : BRAM_TDP_MACRO + generic map ( + BRAM_SIZE => "36Kb", + DEVICE => "7SERIES", + DOA_REG => 0, + DOB_REG => 0, + INIT_A => INIT_A, + INIT_B => INIT_B, + INIT_FILE => "NONE", + READ_WIDTH_A => 36, + READ_WIDTH_B => 36, + SIM_COLLISION_CHECK => "NONE", + SRVAL_A => SRVAL_A, + SRVAL_B => SRVAL_A, + WRITE_MODE_A => WRITE_MODE_A, + WRITE_MODE_B => WRITE_MODE_B, + WRITE_WIDTH_A => 36, + WRITE_WIDTH_B => 36, + INIT_00 => INIT_00, + INIT_01 => INIT_01, + INIT_02 => INIT_02, + INIT_03 => INIT_03, + INIT_04 => INIT_04, + INIT_05 => INIT_05, + INIT_06 => INIT_06, + INIT_07 => INIT_07, + INIT_08 => INIT_08, + INIT_09 => INIT_09, + INIT_0A => INIT_0A, + INIT_0B => INIT_0B, + INIT_0C => INIT_0C, + INIT_0D => INIT_0D, + INIT_0E => INIT_0E, + INIT_0F => INIT_0F, + INIT_10 => INIT_10, + INIT_11 => INIT_11, + INIT_12 => INIT_12, + INIT_13 => INIT_13, + INIT_14 => INIT_14, + INIT_15 => INIT_15, + INIT_16 => INIT_16, + INIT_17 => INIT_17, + INIT_18 => INIT_18, + INIT_19 => INIT_19, + INIT_1A => INIT_1A, + INIT_1B => INIT_1B, + INIT_1C => INIT_1C, + INIT_1D => INIT_1D, + INIT_1E => INIT_1E, + INIT_1F => INIT_1F, + INIT_20 => INIT_20, + INIT_21 => INIT_21, + INIT_22 => INIT_22, + INIT_23 => INIT_23, + INIT_24 => INIT_24, + INIT_25 => INIT_25, + INIT_26 => INIT_26, + INIT_27 => INIT_27, + INIT_28 => INIT_28, + INIT_29 => INIT_29, + INIT_2A => INIT_2A, + INIT_2B => INIT_2B, + INIT_2C => INIT_2C, + INIT_2D => INIT_2D, + INIT_2E => INIT_2E, + INIT_2F => INIT_2F, + INIT_30 => INIT_30, + INIT_31 => INIT_31, + INIT_32 => INIT_32, + INIT_33 => INIT_33, + INIT_34 => INIT_34, + INIT_35 => INIT_35, + INIT_36 => INIT_36, + INIT_37 => INIT_37, + INIT_38 => INIT_38, + INIT_39 => INIT_39, + INIT_3A => INIT_3A, + INIT_3B => INIT_3B, + INIT_3C => INIT_3C, + INIT_3D => INIT_3D, + INIT_3E => INIT_3E, + INIT_3F => INIT_3F, + + INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", + + INITP_00 => INITP_00, + INITP_01 => INITP_01, + INITP_02 => INITP_02, + INITP_03 => INITP_03, + INITP_04 => INITP_04, + INITP_05 => INITP_05, + INITP_06 => INITP_06, + INITP_07 => INITP_07, + + INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000" + ) + port map ( + DOA => DOUTA, + DOB => DOUTB, + ADDRA => ADDRA_10, + ADDRB => ADDRB_10, + CLKA => CLKA, + CLKB => CLKB, + DIA => DINA, + DIB => DINB, + ENA => ENA, + ENB => ENB, + REGCEA => '1', + REGCEB => '1', + RSTA => SSRA_t, + RSTB => SSRB_t, + WEA => WEA_t, + WEB => WEB_t + ); + + + +end RAMB16_S36_S36; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/ramb16_s9_s9.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/ramb16_s9_s9.vhdl new file mode 100644 index 0000000..e85c457 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/ramb16_s9_s9.vhdl @@ -0,0 +1,360 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; +use ieee.std_logic_1164.all; + +library ibm; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; + +library UNISIM; +use UNISIM.vcomponents.all; + +library UNIMACRO; +use UNIMACRO.vcomponents.all; + +entity RAMB16_S9_S9 is + generic ( + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_A : bit_vector := X"000000000"; + INIT_B : bit_vector := X"000000000"; + SIM_COLLISION_CHECK : string := "ALL"; + SRVAL_A : bit_vector := X"000000000"; + SRVAL_B : bit_vector := X"000000000"; + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + port ( + DOA : out std_logic_vector(7 downto 0); + DOB : out std_logic_vector(7 downto 0); + DOPA : out std_logic_vector(0 downto 0); + DOPB : out std_logic_vector(0 downto 0); + ADDRA : in std_logic_vector(10 downto 0); + ADDRB : in std_logic_vector(10 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(7 downto 0); + DIB : in std_logic_vector(7 downto 0); + DIPA : in std_logic_vector(0 downto 0); + DIPB : in std_logic_vector(0 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); +end RAMB16_S9_S9; + +architecture RAMB16_S9_S9 of RAMB16_S9_S9 is + +signal DINA, DINB : std_logic_vector(8 downto 0); +signal DOUTA, DOUTB : std_logic_vector(8 downto 0); +signal SSRA_t, SSRB_t : std_logic; +signal WEA_t, WEB_t : std_logic_vector(0 downto 0); + +begin + +DINA <= DIPA & DIA; +DOPA(0) <= DOUTA(8); +DOA <= DOUTA(7 downto 0); + +DINB <= DIPB & DIB; +DOPB(0) <= DOUTB(8); +DOB <= DOUTB(7 downto 0); + +SSRA_t <= SSRA; +SSRB_t <= SSRB; +WEA_t(0) <= WEA; +WEB_t(0) <= WEB; + + + + + + BRAM_0 : BRAM_TDP_MACRO + generic map ( + BRAM_SIZE => "18Kb", + DEVICE => "7SERIES", + DOA_REG => 0, + DOB_REG => 0, + INIT_A => INIT_A, + INIT_B => INIT_B, + INIT_FILE => "NONE", + READ_WIDTH_A => 9, + READ_WIDTH_B => 9, + SIM_COLLISION_CHECK => "NONE", + SRVAL_A => SRVAL_A, + SRVAL_B => SRVAL_A, + WRITE_MODE_A => WRITE_MODE_A, + WRITE_MODE_B => WRITE_MODE_B, + WRITE_WIDTH_A => 9, + WRITE_WIDTH_B => 9, + INIT_00 => INIT_00, + INIT_01 => INIT_01, + INIT_02 => INIT_02, + INIT_03 => INIT_03, + INIT_04 => INIT_04, + INIT_05 => INIT_05, + INIT_06 => INIT_06, + INIT_07 => INIT_07, + INIT_08 => INIT_08, + INIT_09 => INIT_09, + INIT_0A => INIT_0A, + INIT_0B => INIT_0B, + INIT_0C => INIT_0C, + INIT_0D => INIT_0D, + INIT_0E => INIT_0E, + INIT_0F => INIT_0F, + INIT_10 => INIT_10, + INIT_11 => INIT_11, + INIT_12 => INIT_12, + INIT_13 => INIT_13, + INIT_14 => INIT_14, + INIT_15 => INIT_15, + INIT_16 => INIT_16, + INIT_17 => INIT_17, + INIT_18 => INIT_18, + INIT_19 => INIT_19, + INIT_1A => INIT_1A, + INIT_1B => INIT_1B, + INIT_1C => INIT_1C, + INIT_1D => INIT_1D, + INIT_1E => INIT_1E, + INIT_1F => INIT_1F, + INIT_20 => INIT_20, + INIT_21 => INIT_21, + INIT_22 => INIT_22, + INIT_23 => INIT_23, + INIT_24 => INIT_24, + INIT_25 => INIT_25, + INIT_26 => INIT_26, + INIT_27 => INIT_27, + INIT_28 => INIT_28, + INIT_29 => INIT_29, + INIT_2A => INIT_2A, + INIT_2B => INIT_2B, + INIT_2C => INIT_2C, + INIT_2D => INIT_2D, + INIT_2E => INIT_2E, + INIT_2F => INIT_2F, + INIT_30 => INIT_30, + INIT_31 => INIT_31, + INIT_32 => INIT_32, + INIT_33 => INIT_33, + INIT_34 => INIT_34, + INIT_35 => INIT_35, + INIT_36 => INIT_36, + INIT_37 => INIT_37, + INIT_38 => INIT_38, + INIT_39 => INIT_39, + INIT_3A => INIT_3A, + INIT_3B => INIT_3B, + INIT_3C => INIT_3C, + INIT_3D => INIT_3D, + INIT_3E => INIT_3E, + INIT_3F => INIT_3F, + + INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", + + INITP_00 => INITP_00, + INITP_01 => INITP_01, + INITP_02 => INITP_02, + INITP_03 => INITP_03, + INITP_04 => INITP_04, + INITP_05 => INITP_05, + INITP_06 => INITP_06, + INITP_07 => INITP_07, + + INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000" + ) + port map ( + DOA => DOUTA, + DOB => DOUTB, + ADDRA => ADDRA, + ADDRB => ADDRB, + CLKA => CLKA, + CLKB => CLKB, + DIA => DINA, + DIB => DINB, + ENA => ENA, + ENB => ENB, + REGCEA => '1', + REGCEB => '1', + RSTA => SSRA_t, + RSTB => SSRB_t, + WEA => WEA_t, + WEB => WEB_t + ); + + + +end RAMB16_S9_S9; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_128x168_1w_0.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_128x168_1w_0.vhdl new file mode 100644 index 0000000..3db90b8 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_128x168_1w_0.vhdl @@ -0,0 +1,338 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; use ieee.std_logic_1164.all ; +library ibm; + use ibm.std_ulogic_support.all ; + use ibm.std_ulogic_function_support.all; +library support; + use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; +-- pragma translate_off +-- pragma translate_on + +entity tri_128x168_1w_0 is + generic (addressable_ports : positive := 128; + addressbus_width : positive := 7; + port_bitwidth : positive := 168; + ways : positive := 1; + expand_type : integer := 1); + port ( + gnd : inout power_logic; + vdd : inout power_logic; + vcs : inout power_logic; + + nclk : in clk_logic; + act : in std_ulogic; + ccflush_dc : in std_ulogic; + scan_dis_dc_b : in std_ulogic; + scan_diag_dc : in std_ulogic; + + abst_scan_in : in std_ulogic; + repr_scan_in : in std_ulogic; + time_scan_in : in std_ulogic; + abst_scan_out : out std_ulogic; + repr_scan_out : out std_ulogic; + time_scan_out : out std_ulogic; + + lcb_d_mode_dc : in std_ulogic; + lcb_clkoff_dc_b : in std_ulogic; + lcb_act_dis_dc : in std_ulogic; + lcb_mpw1_dc_b : in std_ulogic_vector(0 to 4); + lcb_mpw2_dc_b : in std_ulogic; + lcb_delay_lclkr_dc : in std_ulogic_vector(0 to 4); + + lcb_sg_1 : in std_ulogic; + lcb_time_sg_0 : in std_ulogic; + lcb_repr_sg_0 : in std_ulogic; + + lcb_abst_sl_thold_0 : in std_ulogic; + lcb_repr_sl_thold_0 : in std_ulogic; + lcb_time_sl_thold_0 : in std_ulogic; + lcb_ary_nsl_thold_0 : in std_ulogic; + lcb_bolt_sl_thold_0 : in std_ulogic; + + tc_lbist_ary_wrt_thru_dc : in std_ulogic; + abist_en_1 : in std_ulogic; + din_abist : in std_ulogic_vector(0 to 3); + abist_cmp_en : in std_ulogic; + abist_raw_b_dc : in std_ulogic; + data_cmp_abist : in std_ulogic_vector(0 to 3); + addr_abist : in std_ulogic_vector(0 to 6); + r_wb_abist : in std_ulogic; + + pc_bo_enable_2 : in std_ulogic; + pc_bo_reset : in std_ulogic; + pc_bo_unload : in std_ulogic; + pc_bo_repair : in std_ulogic; + pc_bo_shdata : in std_ulogic; + pc_bo_select : in std_ulogic; + bo_pc_failout : out std_ulogic; + bo_pc_diagloop : out std_ulogic; + tri_lcb_mpw1_dc_b : in std_ulogic; + tri_lcb_mpw2_dc_b : in std_ulogic; + tri_lcb_delay_lclkr_dc : in std_ulogic; + tri_lcb_clkoff_dc_b : in std_ulogic; + tri_lcb_act_dis_dc : in std_ulogic; + + write_enable : in std_ulogic; + addr : in std_ulogic_vector (0 to addressbus_width-1); + data_in : in std_ulogic_vector (0 to port_bitwidth-1); + data_out : out std_ulogic_vector(0 to port_bitwidth-1) +); + + -- synopsys translate_off + + -- synopsys translate_on + +end entity tri_128x168_1w_0; + +architecture tri_128x168_1w_0 of tri_128x168_1w_0 is + +constant wga_base_width : integer := 168; +constant wga_width_mult : integer := (port_bitwidth*ways-1)/wga_base_width + 1; +constant ramb_base_width : integer := 36; +constant ramb_base_addr : integer := 9; +constant ramb_width_mult : integer := (port_bitwidth-1)/ramb_base_width + 1; +constant way : std_ulogic_vector(0 to 0) := "0"; + + +type RAMB_DATA_ARRAY is array (natural range <>) of std_logic_vector(0 to (ramb_base_width*ramb_width_mult - 1)); + + +begin + + -- synopsys translate_off + um: if expand_type = 0 generate + signal tiup : std_ulogic; + signal tidn : std_ulogic; + + signal addr_l2 : std_ulogic_vector (0 TO addressbus_width-1); + signal write_enable_d : std_ulogic; + signal write_enable_l2 : std_ulogic; + signal data_in_l2 : std_ulogic_vector(0 to port_bitwidth-1); + signal array_d : std_ulogic_vector(0 to addressable_ports*port_bitwidth*ways-1); + signal array_l2 : std_ulogic_vector(0 to addressable_ports*port_bitwidth*ways-1); + begin + tiup <= '1'; + tidn <= '0'; + + addr_latch: tri_rlmreg_p + generic map (width => addr'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act, + scin => (others => '0'), + scout => open, + din => addr, + dout => addr_l2 ); + + + write_enable_latch: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + scin => tidn, + scout => open, + din => write_enable_d, + dout => write_enable_l2 ); + + data_in_latch: tri_rlmreg_p + generic map (width => port_bitwidth, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act, + scin => (others => '0'), + scout => open, + din => data_in, + dout => data_in_l2 ); + + array_latch: tri_rlmreg_p + generic map (width => addressable_ports*port_bitwidth*ways, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + scin => (others => '0'), + scout => open, + din => array_d, + dout => array_l2 ); + + write_enable_d <= act and write_enable; + + ww: for w in 0 to ways-1 generate + begin + wy: for y in 0 to addressable_ports-1 generate + begin + wx: for x in 0 to port_bitwidth-1 generate + begin + array_d(y*port_bitwidth*ways+w*port_bitwidth+x) <= + data_in_l2(x) when (( write_enable_l2 and addr_l2 = tconv(y, addressbus_width)) = '1') + else array_l2(y*port_bitwidth*ways+w*port_bitwidth+x); + + end generate wx; + end generate wy; + end generate ww; + + data_out <= array_l2( tconv(addr_l2)*port_bitwidth*ways to tconv(addr_l2)*port_bitwidth*ways+port_bitwidth*ways-1 ); + + abst_scan_out <= abst_scan_in; + repr_scan_out <= repr_scan_in; + time_scan_out <= time_scan_in; + + bo_pc_failout <= '0'; + bo_pc_diagloop <= '0'; + + end generate um; + -- synopsys translate_on + + + a: if expand_type = 1 generate + component RAMB16_S36_S36 + -- pragma translate_off + generic( + SIM_COLLISION_CHECK : string := "none"); + -- pragma translate_on + port( + DOA : out std_logic_vector(31 downto 0); + DOB : out std_logic_vector(31 downto 0); + DOPA : out std_logic_vector(3 downto 0); + DOPB : out std_logic_vector(3 downto 0); + ADDRA : in std_logic_vector(8 downto 0); + ADDRB : in std_logic_vector(8 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(31 downto 0); + DIB : in std_logic_vector(31 downto 0); + DIPA : in std_logic_vector(3 downto 0); + DIPB : in std_logic_vector(3 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic); + end component; + + -- pragma translate_off + -- pragma translate_on + + signal ramb_data_in : std_logic_vector(0 to (ramb_base_width*ramb_width_mult - 1)); + signal ramb_data_out : RAMB_DATA_ARRAY(way'range); + signal ramb_addr : std_logic_vector(0 to ramb_base_addr - 1); + + signal write : std_ulogic_vector(way'range); + signal tidn : std_ulogic; + signal unused : std_ulogic; + -- synopsys translate_off + -- synopsys translate_on + begin + + tidn <= '0'; + + add0: if (addressbus_width < ramb_base_addr) generate + begin + ramb_addr(0 to (ramb_base_addr-addressbus_width-1)) <= (others => '0'); + ramb_addr(ramb_base_addr-addressbus_width to ramb_base_addr-1) <= tconv( addr ); + end generate; + add1: if (addressbus_width >= ramb_base_addr) generate + begin + ramb_addr <= tconv( addr(addressbus_width-ramb_base_addr to addressbus_width-1) ); + end generate; + + din: for i in ramb_data_in'range generate + begin + R0: if(i < port_bitwidth) generate begin ramb_data_in(i) <= data_in(i); end generate; + R1: if(i >= port_bitwidth) generate begin ramb_data_in(i) <= '0'; end generate; + end generate; + + aw: for w in way'range generate begin + write(w) <= write_enable; + + ax: for x in 0 to (ramb_width_mult - 1) generate begin + ram: RAMB16_S36_S36 + -- pragma translate_off + generic map( + sim_collision_check => "none") + -- pragma translate_on + port map( + DOA => ramb_data_out(w)(x*ramb_base_width to x*ramb_base_width+31), + DOB => open, + DOPA => ramb_data_out(w)(x*ramb_base_width+32 to x*ramb_base_width+35), + DOPB => open, + ADDRA => ramb_addr, + ADDRB => ramb_addr, + CLKA => nclk.clk, + CLKB => tidn, + DIA => ramb_data_in(x*ramb_base_width to x*ramb_base_width+31), + DIB => ramb_data_in(x*ramb_base_width to x*ramb_base_width+31), + DIPA => ramb_data_in(x*ramb_base_width+32 to x*ramb_base_width+35), + DIPB => ramb_data_in(x*ramb_base_width+32 to x*ramb_base_width+35), + ENA => act, + ENB => tidn, + SSRA => nclk.sreset, + SSRB => tidn, + WEA => write(w), + WEB => tidn + ); + + end generate ax; + + data_out(w*port_bitwidth to ((w+1)*port_bitwidth)-1 ) <= tconv( ramb_data_out(w)(0 to port_bitwidth-1) ); + + end generate aw; + + abst_scan_out <= abst_scan_in; + repr_scan_out <= repr_scan_in; + time_scan_out <= time_scan_in; + + bo_pc_failout <= '0'; + bo_pc_diagloop <= '0'; + + unused <= or_reduce( std_ulogic_vector(ramb_data_out(0)(port_bitwidth to ramb_base_width*ramb_width_mult - 1)) + & ccflush_dc & scan_dis_dc_b & scan_diag_dc & lcb_d_mode_dc + & lcb_clkoff_dc_b & lcb_act_dis_dc & lcb_mpw1_dc_b & lcb_mpw2_dc_b + & lcb_delay_lclkr_dc & lcb_sg_1 & lcb_time_sg_0 & lcb_repr_sg_0 + & lcb_abst_sl_thold_0 & lcb_repr_sl_thold_0 & lcb_time_sl_thold_0 + & lcb_ary_nsl_thold_0 & lcb_bolt_sl_thold_0 & tc_lbist_ary_wrt_thru_dc + & abist_en_1 & din_abist & abist_cmp_en & abist_raw_b_dc & data_cmp_abist + & addr_abist & r_wb_abist & pc_bo_enable_2 & pc_bo_reset + & pc_bo_unload & pc_bo_repair & pc_bo_shdata & pc_bo_select + & tri_lcb_mpw1_dc_b & tri_lcb_mpw2_dc_b & tri_lcb_delay_lclkr_dc + & tri_lcb_clkoff_dc_b & tri_lcb_act_dis_dc ); + + end generate a; + +end tri_128x168_1w_0; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_128x16_1r1w_1.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_128x16_1r1w_1.vhdl new file mode 100644 index 0000000..b3a0746 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_128x16_1r1w_1.vhdl @@ -0,0 +1,466 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee; use ieee.std_logic_1164.all; +library support; + use support.power_logic_pkg.all; +library ibm; + use ibm.std_ulogic_support.all ; + use ibm.std_ulogic_function_support.all; +library tri; use tri.tri_latches_pkg.all; + +entity tri_128x16_1r1w_1 is + generic (addressable_ports : positive := 128; + addressbus_width : positive := 7; + port_bitwidth : positive := 16; + ways : positive := 1; + expand_type : integer := 1); +port ( + vdd : INOUT power_logic; + vcs : INOUT power_logic; + gnd : INOUT power_logic; + + nclk : IN clk_logic; + + rd_act : IN std_ulogic; + wr_act : IN std_ulogic; + + lcb_d_mode_dc : IN std_ulogic; + lcb_clkoff_dc_b : IN std_ulogic; + lcb_mpw1_dc_b : IN std_ulogic_vector(0 TO 4); + lcb_mpw2_dc_b : IN std_ulogic; + lcb_delay_lclkr_dc : IN std_ulogic_vector(0 TO 4); + + ccflush_dc : IN std_ulogic; + scan_dis_dc_b : IN std_ulogic; + scan_diag_dc : IN std_ulogic; + func_scan_in : IN std_ulogic; + func_scan_out : OUT std_ulogic; + + lcb_sg_0 : IN std_ulogic; + lcb_sl_thold_0_b : IN std_ulogic; + lcb_time_sl_thold_0 : IN std_ulogic; + lcb_abst_sl_thold_0 : IN std_ulogic; + lcb_ary_nsl_thold_0 : IN std_ulogic; + lcb_repr_sl_thold_0 : IN std_ulogic; + time_scan_in : IN std_ulogic; + time_scan_out : OUT std_ulogic; + abst_scan_in : IN std_ulogic; + abst_scan_out : OUT std_ulogic; + repr_scan_in : IN std_ulogic; + repr_scan_out : OUT std_ulogic; + + abist_di : IN std_ulogic_vector(0 TO 3); + abist_bw_odd : IN std_ulogic; + abist_bw_even : IN std_ulogic; + abist_wr_adr : IN std_ulogic_vector(0 TO 6); + wr_abst_act : IN std_ulogic; + abist_rd0_adr : IN std_ulogic_vector(0 TO 6); + rd0_abst_act : IN std_ulogic; + tc_lbist_ary_wrt_thru_dc : IN std_ulogic; + abist_ena_1 : IN std_ulogic; + abist_g8t_rd0_comp_ena : IN std_ulogic; + abist_raw_dc_b : IN std_ulogic; + obs0_abist_cmp : IN std_ulogic_vector(0 TO 3); + + lcb_bolt_sl_thold_0 : in std_ulogic; + pc_bo_enable_2 : in std_ulogic; + pc_bo_reset : in std_ulogic; + pc_bo_unload : in std_ulogic; + pc_bo_repair : in std_ulogic; + pc_bo_shdata : in std_ulogic; + pc_bo_select : in std_ulogic; + bo_pc_failout : out std_ulogic; + bo_pc_diagloop : out std_ulogic; + tri_lcb_mpw1_dc_b : in std_ulogic; + tri_lcb_mpw2_dc_b : in std_ulogic; + tri_lcb_delay_lclkr_dc : in std_ulogic; + tri_lcb_clkoff_dc_b : in std_ulogic; + tri_lcb_act_dis_dc : in std_ulogic; + + bw : IN std_ulogic_vector( 0 TO 15 ); + wr_adr : IN std_ulogic_vector( 0 TO 6 ); + rd_adr : IN std_ulogic_vector( 0 TO 6 ); + di : IN std_ulogic_vector( 0 TO 15 ); + do : OUT std_ulogic_vector( 0 TO 15 ) + + ); + + -- synopsys translate_off + -- synopsys translate_on + +end entity tri_128x16_1r1w_1; + +architecture tri_128x16_1r1w_1 of tri_128x16_1r1w_1 is + +begin + + -- synopsys translate_off + um: if expand_type = 0 generate + + constant rd_addr_offset : natural := 0; + constant wr_addr_offset : natural := rd_addr_offset + addressbus_width; + constant write_enable_offset : natural := wr_addr_offset + addressbus_width; + constant data_in_offset : natural := write_enable_offset + port_bitwidth; + constant data_out_offset : natural := data_in_offset + port_bitwidth; + constant array_offset : natural := data_out_offset + port_bitwidth; + constant scan_right : natural := array_offset + addressable_ports*port_bitwidth*ways - 1; + + signal tiup : std_ulogic; + signal tidn : std_ulogic; + + signal rd_addr_l2 : std_ulogic_vector (0 TO addressbus_width-1); + signal wr_addr_l2 : std_ulogic_vector (0 TO addressbus_width-1); + signal write_enable_d : std_ulogic_vector(0 to port_bitwidth-1); + signal write_enable_l2 : std_ulogic_vector(0 to port_bitwidth-1); + signal data_in_l2 : std_ulogic_vector(0 to port_bitwidth-1); + signal data_out_d : std_ulogic_vector(0 to port_bitwidth-1); + signal data_out_l2 : std_ulogic_vector(0 to port_bitwidth-1); + signal array_d : std_ulogic_vector(0 to addressable_ports*port_bitwidth*ways-1); + signal array_l2 : std_ulogic_vector(0 to addressable_ports*port_bitwidth*ways-1); + signal siv : std_ulogic_vector(0 to scan_right); + signal sov : std_ulogic_vector(0 to scan_right); + begin + tiup <= '1'; + tidn <= '0'; + + rd_addr_latch: tri_rlmreg_p + generic map (width => rd_adr'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rd_act, + scin => siv(rd_addr_offset to rd_addr_offset+rd_addr_l2'length-1), + scout => sov(rd_addr_offset to rd_addr_offset+rd_addr_l2'length-1), + din => rd_adr, + dout => rd_addr_l2 ); + + wr_addr_latch: tri_rlmreg_p + generic map (width => wr_adr'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => wr_act, + scin => siv(wr_addr_offset to wr_addr_offset+wr_addr_l2'length-1), + scout => sov(wr_addr_offset to wr_addr_offset+wr_addr_l2'length-1), + din => wr_adr, + dout => wr_addr_l2 ); + + + + write_enable_latch: tri_rlmreg_p + generic map (width => port_bitwidth, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => wr_act, + scin => siv(write_enable_offset to write_enable_offset+write_enable_l2'length-1), + scout => sov(write_enable_offset to write_enable_offset+write_enable_l2'length-1), + din => write_enable_d, + dout => write_enable_l2 ); + + data_in_latch: tri_rlmreg_p + generic map (width => port_bitwidth, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => wr_act, + scin => siv(data_in_offset to data_in_offset+data_in_l2'length-1), + scout => sov(data_in_offset to data_in_offset+data_in_l2'length-1), + din => di, + dout => data_in_l2 ); + + data_out_latch: tri_rlmreg_p + generic map (width => port_bitwidth, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => wr_act, + scin => siv(data_out_offset to data_out_offset+data_out_l2'length-1), + scout => sov(data_out_offset to data_out_offset+data_out_l2'length-1), + din => data_out_d, + dout => data_out_l2 ); + + array_latch: tri_rlmreg_p + generic map (width => addressable_ports*port_bitwidth*ways, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + scin => siv(array_offset to array_offset+array_l2'length-1), + scout => sov(array_offset to array_offset+array_l2'length-1), + din => array_d, + dout => array_l2 ); + + write_enable_d <= bw when wr_act='1' else (others => '0'); + + ww: for w in 0 to ways-1 generate + begin + wy: for y in 0 to addressable_ports-1 generate + begin + wx: for x in 0 to port_bitwidth-1 generate + begin + array_d(y*port_bitwidth*ways+w*port_bitwidth+x) <= + data_in_l2(x) when ( write_enable_l2(x)='1' and wr_addr_l2 = tconv(y, addressbus_width)) + else array_l2(y*port_bitwidth*ways+w*port_bitwidth+x); + + end generate wx; + end generate wy; + end generate ww; + + data_out_d(0) <= array_l2( tconv(rd_addr_l2)*port_bitwidth); + data_out_d(1) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+1); + data_out_d(2) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+2); + data_out_d(3) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+3); + data_out_d(4) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+4); + data_out_d(5) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+5); + data_out_d(6) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+6); + data_out_d(7) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+7); + data_out_d(8) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+8); + data_out_d(9) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+9); + data_out_d(10) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+10); + data_out_d(11) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+11); + data_out_d(12) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+12); + data_out_d(13) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+13); + data_out_d(14) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+14); + data_out_d(15) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+15); + + do(0) <= array_l2( tconv(rd_addr_l2)*port_bitwidth); + do(1) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+1); + do(2) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+2); + do(3) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+3); + do(4) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+4); + do(5) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+5); + do(6) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+6); + do(7) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+7); + do(8) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+8); + do(9) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+9); + do(10) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+10); + do(11) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+11); + do(12) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+12); + do(13) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+13); + do(14) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+14); + do(15) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+15); + + siv(0 to scan_right) <= sov(1 to scan_right) & func_scan_in; + func_scan_out <= sov(0); + + time_scan_out <= time_scan_in; + abst_scan_out <= abst_scan_in; + repr_scan_out <= repr_scan_in; + + bo_pc_failout <= '0'; + bo_pc_diagloop <= '0'; + + end generate um; + -- synopsys translate_on + + +a : if expand_type = 1 generate + +component RAMB16_S36_S36 +-- pragma translate_off + generic( + SIM_COLLISION_CHECK : string := "none"); +-- pragma translate_on + port( + DOA : out std_logic_vector(31 downto 0); + DOB : out std_logic_vector(31 downto 0); + DOPA : out std_logic_vector(3 downto 0); + DOPB : out std_logic_vector(3 downto 0); + ADDRA : in std_logic_vector(8 downto 0); + ADDRB : in std_logic_vector(8 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(31 downto 0); + DIB : in std_logic_vector(31 downto 0); + DIPA : in std_logic_vector(3 downto 0); + DIPB : in std_logic_vector(3 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic); +end component; + + + +-- pragma translate_off +-- pragma translate_on + + + +signal clk,clk2x : std_ulogic; +signal b0addra, b0addrb : std_ulogic_vector(0 to 8); +signal wea, web : std_ulogic; +signal wren_a : std_ulogic; +signal reset_q : std_ulogic; +signal gate_fq, gate_d : std_ulogic; +signal r_data_out_1_d, r_data_out_1_fq : std_ulogic_vector(0 to 35); +signal w_data_in_0 : std_ulogic_vector(0 to 35); + +signal r_data_out_0_bram : std_logic_vector(0 to 35); +signal r_data_out_1_bram : std_logic_vector(0 to 35); + +signal toggle_d : std_ulogic; +signal toggle_q : std_ulogic; +signal toggle2x_d : std_ulogic; +signal toggle2x_q : std_ulogic; + +signal unused : std_ulogic; +-- synopsys translate_off +-- synopsys translate_on + +begin + +clk <= nclk.clk; +clk2x <= nclk.clk2x; + +rlatch: process (clk) begin + if(rising_edge(clk)) then + reset_q <= nclk.sreset; + end if; +end process; + + +tlatch: process (nclk.clk,reset_q) +begin + if(rising_edge(nclk.clk)) then + if (reset_q = '1') then + toggle_q <= '1'; + else + toggle_q <= toggle_d; + end if; + end if; +end process; + +flatch: process (nclk.clk2x) +begin + if(rising_edge(nclk.clk2x)) then + toggle2x_q <= toggle2x_d; + gate_fq <= gate_d; + r_data_out_1_fq <= r_data_out_1_d; + end if; +end process; + +toggle_d <= not toggle_q; +toggle2x_d <= toggle_q; + +gate_d <= not(toggle_q xor toggle2x_q); + + + + + +b0addra(2 to 8) <= wr_adr; +b0addrb(2 to 8) <= rd_adr; + +b0addra(0 to 1) <= "00"; +b0addrb(0 to 1) <= "00"; + + + +wren_a <= '1' when bw /= "0000000000000000" else '0'; +wea <= wren_a and not(gate_fq); +web <= '0'; +w_data_in_0(0) <= di(0) when bw(0)='1' else r_data_out_0_bram(0); +w_data_in_0(1) <= di(1) when bw(1)='1' else r_data_out_0_bram(1); +w_data_in_0(2) <= di(2) when bw(2)='1' else r_data_out_0_bram(2); +w_data_in_0(3) <= di(3) when bw(3)='1' else r_data_out_0_bram(3); +w_data_in_0(4) <= di(4) when bw(4)='1' else r_data_out_0_bram(4); +w_data_in_0(5) <= di(5) when bw(5)='1' else r_data_out_0_bram(5); +w_data_in_0(6) <= di(6) when bw(6)='1' else r_data_out_0_bram(6); +w_data_in_0(7) <= di(7) when bw(7)='1' else r_data_out_0_bram(7); +w_data_in_0(8) <= di(8) when bw(8)='1' else r_data_out_0_bram(8); +w_data_in_0(9) <= di(9) when bw(9)='1' else r_data_out_0_bram(9); +w_data_in_0(10) <= di(10) when bw(10)='1' else r_data_out_0_bram(10); +w_data_in_0(11) <= di(11) when bw(11)='1' else r_data_out_0_bram(11); +w_data_in_0(12) <= di(12) when bw(12)='1' else r_data_out_0_bram(12); +w_data_in_0(13) <= di(13) when bw(13)='1' else r_data_out_0_bram(13); +w_data_in_0(14) <= di(14) when bw(14)='1' else r_data_out_0_bram(14); +w_data_in_0(15) <= di(15) when bw(15)='1' else r_data_out_0_bram(15); +w_data_in_0(16 to 35) <= (others => '0'); + +r_data_out_1_d <= std_ulogic_vector(r_data_out_1_bram); + +bram0a : ramb16_s36_s36 +-- pragma translate_off +generic map( + sim_collision_check => "none") +-- pragma translate_on +port map( + clka => clk2x, + clkb => clk2x, + ssra => reset_q, + ssrb => reset_q, + addra => std_logic_vector(b0addra), + addrb => std_logic_vector(b0addrb), + dia => std_logic_vector(w_data_in_0(0 to 31)), + dib => (others => '0'), + doa => r_data_out_0_bram(0 to 31), + dob => r_data_out_1_bram(0 to 31), + dopa => r_data_out_0_bram(32 to 35), + dopb => r_data_out_1_bram(32 to 35), + dipa => std_logic_vector(w_data_in_0(32 to 35)), + dipb => (others => '0'), + ena => '1', + enb => '1', + wea => wea, + web => web + ); + + +do <= r_data_out_1_fq(0 to 15); + +func_scan_out <= func_scan_in; +time_scan_out <= time_scan_in; +abst_scan_out <= abst_scan_in; +repr_scan_out <= repr_scan_in; + +bo_pc_failout <= '0'; +bo_pc_diagloop <= '0'; + +unused <= or_reduce( std_ulogic_vector(r_data_out_0_bram(16 to 35)) & rd_act & wr_act + & lcb_d_mode_dc & lcb_clkoff_dc_b & lcb_mpw1_dc_b & lcb_mpw2_dc_b + & lcb_delay_lclkr_dc & ccflush_dc & scan_dis_dc_b & scan_diag_dc + & lcb_sg_0 & lcb_sl_thold_0_b & lcb_time_sl_thold_0 & lcb_abst_sl_thold_0 + & lcb_ary_nsl_thold_0 & lcb_repr_sl_thold_0 & abist_di & abist_bw_odd + & abist_bw_even & abist_wr_adr & wr_abst_act & abist_rd0_adr & rd0_abst_act + & tc_lbist_ary_wrt_thru_dc & abist_ena_1 & abist_g8t_rd0_comp_ena + & abist_raw_dc_b & obs0_abist_cmp & lcb_bolt_sl_thold_0 & pc_bo_enable_2 + & pc_bo_reset & pc_bo_unload & pc_bo_repair & pc_bo_shdata & pc_bo_select + & tri_lcb_mpw1_dc_b & tri_lcb_mpw2_dc_b & tri_lcb_delay_lclkr_dc + & tri_lcb_clkoff_dc_b & tri_lcb_act_dis_dc ); + +end generate a; + + +end architecture tri_128x16_1r1w_1; + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_144x78_2r2w.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_144x78_2r2w.vhdl new file mode 100644 index 0000000..8e7c017 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_144x78_2r2w.vhdl @@ -0,0 +1,411 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee,ibm,support,tri; +use ieee.std_logic_1164.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_support.all; +use support.power_logic_pkg.all; +use tri.tri_latches_pkg.all; + +entity tri_144x78_2r2w is +generic( + expand_type : integer := 1); +port ( + vdd :inout power_logic; + gnd :inout power_logic; + nclk :in clk_logic; + abist_en :in std_ulogic; + abist_raw_dc_b :in std_ulogic; + r0e_abist_comp_en :in std_ulogic; + r1e_abist_comp_en :in std_ulogic; + lbist_en :in std_ulogic; + + lcb_act_dis_dc :in std_ulogic; + lcb_clkoff_dc_b :in std_ulogic_vector(0 to 1); + lcb_d_mode_dc :in std_ulogic; + lcb_delay_lclkr_dc :in std_ulogic_vector(0 to 9); + lcb_fce_0 :in std_ulogic; + lcb_mpw1_dc_b :in std_ulogic_vector(1 to 9); + lcb_mpw2_dc_b :in std_ulogic; + lcb_scan_diag_dc :in std_ulogic; + lcb_scan_dis_dc_b :in std_ulogic; + lcb_sg_0 :in std_ulogic; + lcb_time_sg_0 :in std_ulogic; + lcb_obs0_sg_0 :in std_ulogic; + lcb_obs1_sg_0 :in std_ulogic; + lcb_obs0_sl_thold_0 :in std_ulogic; + lcb_obs1_sl_thold_0 :in std_ulogic; + + lcb_abst_sl_thold_0 :in std_ulogic; + lcb_time_sl_thold_0 :in std_ulogic; + lcb_ary_nsl_thold_0 :in std_ulogic; + + r_scan_in :in std_ulogic; + r_scan_out :out std_ulogic; + w_scan_in :in std_ulogic; + w_scan_out :out std_ulogic; + time_scan_in :in std_ulogic; + time_scan_out :out std_ulogic; + obs0_scan_in :in std_ulogic; + obs0_scan_out :out std_ulogic; + obs1_scan_in :in std_ulogic; + obs1_scan_out :out std_ulogic; + + lcb_bolt_sl_thold_0 :in std_ulogic; + pc_bo_enable_2 :in std_ulogic; + pc_bo_reset :in std_ulogic; + pc_bo_unload :in std_ulogic; + pc_bo_load :in std_ulogic; + pc_bo_shdata :in std_ulogic; + pc_bo_select :in std_ulogic; + bo_pc_failout :out std_ulogic; + bo_pc_diagloop :out std_ulogic; + tri_lcb_mpw1_dc_b :in std_ulogic; + tri_lcb_mpw2_dc_b :in std_ulogic; + tri_lcb_delay_lclkr_dc :in std_ulogic; + tri_lcb_clkoff_dc_b :in std_ulogic; + tri_lcb_act_dis_dc :in std_ulogic; + + r0e_act :in std_ulogic; + r0e_en_func :in std_ulogic; + r0e_en_abist :in std_ulogic; + r0e_addr_func :in std_ulogic_vector(0 to 7); + r0e_addr_abist :in std_ulogic_vector(0 to 7); + r0e_data_out :out std_ulogic_vector(0 to 77); + r0e_byp_e :in std_ulogic; + r0e_byp_l :in std_ulogic; + r0e_byp_r :in std_ulogic; + r0e_sel_lbist :in std_ulogic; + + r1e_act :in std_ulogic; + r1e_en_func :in std_ulogic; + r1e_en_abist :in std_ulogic; + r1e_addr_func :in std_ulogic_vector(0 to 7); + r1e_addr_abist :in std_ulogic_vector(0 to 7); + r1e_data_out :out std_ulogic_vector(0 to 77); + r1e_byp_e :in std_ulogic; + r1e_byp_l :in std_ulogic; + r1e_byp_r :in std_ulogic; + r1e_sel_lbist :in std_ulogic; + + w0e_act :in std_ulogic; + w0e_en_func :in std_ulogic; + w0e_en_abist :in std_ulogic; + w0e_addr_func :in std_ulogic_vector(0 to 7); + w0e_addr_abist :in std_ulogic_vector(0 to 7); + w0e_data_func :in std_ulogic_vector(0 to 77); + w0e_data_abist :in std_ulogic_vector(0 to 3); + + w0l_act :in std_ulogic; + w0l_en_func :in std_ulogic; + w0l_en_abist :in std_ulogic; + w0l_addr_func :in std_ulogic_vector(0 to 7); + w0l_addr_abist :in std_ulogic_vector(0 to 7); + w0l_data_func :in std_ulogic_vector(0 to 77); + w0l_data_abist :in std_ulogic_vector(0 to 3) ); + + -- synopsys translate_off + -- synopsys translate_on + +end entity tri_144x78_2r2w; +architecture tri_144x78_2r2w of tri_144x78_2r2w is + +begin + +a : if expand_type = 1 generate + +component RAMB16_S36_S36 +-- pragma translate_off + generic( + SIM_COLLISION_CHECK : string := "none"); +-- pragma translate_on + port( + DOA : out std_logic_vector(31 downto 0); + DOB : out std_logic_vector(31 downto 0); + DOPA : out std_logic_vector(3 downto 0); + DOPB : out std_logic_vector(3 downto 0); + ADDRA : in std_logic_vector(8 downto 0); + ADDRB : in std_logic_vector(8 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(31 downto 0); + DIB : in std_logic_vector(31 downto 0); + DIPA : in std_logic_vector(3 downto 0); + DIPB : in std_logic_vector(3 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic); +end component; + +-- pragma translate_off +-- pragma translate_on + +signal tilo : std_ulogic; +signal tihi : std_ulogic; +signal zeross : std_logic_vector(0 to 3); + +signal correct_clk : std_ulogic; +signal clk2x : std_ulogic; +signal reset : std_ulogic; +signal reset_hi : std_ulogic; +signal reset_lo : std_ulogic; +signal reset_q : std_ulogic; +signal sinit0_q : std_logic; +signal sinit1_q : std_logic; +signal flipper_d : std_ulogic; +signal flipper_q : std_ulogic; + +signal doutb0 : std_logic_vector(0 to 77); +signal doutb0_q : std_ulogic_vector(0 to 77); +signal dinfa0_par : std_logic_vector(64 to 95); +signal doutb0_par : std_logic_vector(64 to 95); +signal weaf : std_logic; +signal addra : std_logic_vector(0 to 8); +signal addrb0 : std_logic_vector(0 to 8); +signal dinfa : std_logic_vector(0 to 77); +signal dinfb : std_logic_vector(0 to 31); + +signal w0e_data_q : std_ulogic_vector(0 to 77); +signal w0l_data_q : std_ulogic_vector(0 to 77); +signal w0l_en_q : std_ulogic; +signal w0l_addr_q : std_ulogic_vector(0 to 7); +signal r1e_addr_q : std_ulogic_vector(0 to 7); + +signal r0e_byp_e_q : std_ulogic; +signal r0e_byp_l_q : std_ulogic; +signal r1e_byp_e_q : std_ulogic; +signal r1e_byp_l_q : std_ulogic; +signal r0_byp_sel : std_ulogic_vector(0 to 1); +signal r1_byp_sel : std_ulogic_vector(0 to 1); + +signal unused : std_ulogic; +-- synopsys translate_off +-- synopsys translate_on + +begin + + tilo <= '0'; + tihi <= '1'; + zeross <= (0 to 3 => '0'); + + reset <= nclk.sreset; + correct_clk <= nclk.clk; + clk2x <= nclk.clk2x; + + reset_hi <= reset; + reset_lo <= not reset_q after 1 ns ; + + + flipper_d <= not flipper_q; + + slatch: process (correct_clk,reset) begin + if rising_edge(correct_clk) then + if (reset = '1') then + w0l_en_q <= '0'; + r1e_addr_q <= (others => '0'); + r0e_byp_e_q <= '0'; + r0e_byp_l_q <= '0'; + r1e_byp_e_q <= '0'; + r1e_byp_l_q <= '0'; + + else + w0e_data_q <= w0e_data_func; + w0l_data_q <= w0l_data_func; + w0l_en_q <= w0l_en_func; + w0l_addr_q <= w0l_addr_func; + r1e_addr_q <= r1e_addr_func; + r0e_byp_e_q <= r0e_byp_e; + r0e_byp_l_q <= r0e_byp_l; + r1e_byp_e_q <= r1e_byp_e; + r1e_byp_l_q <= r1e_byp_l; + + end if; + end if; + end process; + + flatch: process (clk2x,reset_lo) begin + if clk2x'event and clk2x = '1' then + if (reset_lo = '0') then + flipper_q <= '0'; + + else + flipper_q <= flipper_d; + doutb0_q <= tconv(doutb0); + + end if; + end if; + end process; + + rlatch: process (correct_clk) begin + if(rising_edge(correct_clk)) then + reset_q <= reset_hi; + sinit0_q <= reset_hi; + sinit1_q <= reset_hi; + end if; + end process; + + + addra(0) <= '0'; + addra(1 to 8) <= (tconv((w0e_addr_func and (0 to 7 => flipper_q)) or (w0l_addr_q and (0 to 7 => not flipper_q)))) after 1 ns ; + weaf <= (( w0e_en_func and flipper_q) or ( w0l_en_q and not flipper_q)) after 1 ns; + dinfa <= (tconv((w0e_data_func and (0 to 77 => flipper_q)) or (w0l_data_q and (0 to 77 => not flipper_q)))) after 1 ns; + + dinfb <= (others => '0'); + addrb0(0) <= '0'; + addrb0(1 to 8) <= (tconv((r0e_addr_func and (0 to 7 => flipper_q)) or (r1e_addr_q and (0 to 7 => not flipper_q)))) after 1 ns ; + + r0_byp_sel <= r0e_byp_e & r0e_byp_l; + with r0_byp_sel select + r0e_data_out <= w0e_data_q when "10", + w0l_data_q when "01", + doutb0_q when others; + + r1_byp_sel <= r1e_byp_e & r1e_byp_l; + with r1_byp_sel select + r1e_data_out <= w0e_data_q when "10", + w0l_data_q when "01", + tconv(doutb0) when others; + + +U0 : RAMB16_S36_S36 +-- pragma translate_off +generic map( + sim_collision_check => "none") +-- pragma translate_on + port map + ( + DOA => open, + DOB => doutb0(0 to 31), + DOPA => open, + DOPB => open, + ADDRA => addra, + ADDRB => addrb0, + CLKA => clk2x, + CLKB => clk2x, + DIA => dinfa(0 to 31), + DIB => dinfb, + DIPA => zeross, + DIPB => zeross, + ENA => tihi, + ENB => tihi, + SSRA => sinit0_q, + SSRB => sinit0_q, + WEA => weaf, + WEB => tilo + ); +U1 : RAMB16_S36_S36 +-- pragma translate_off +generic map( + sim_collision_check => "none") +-- pragma translate_on + + port map + ( + DOA => open, + DOB => doutb0(32 to 63), + DOPA => open, + DOPB => open, + ADDRA => addra, + ADDRB => addrb0, + CLKA => clk2x, + CLKB => clk2x, + DIA => dinfa(32 to 63), + DIB => dinfb, + DIPA => zeross, + DIPB => zeross, + ENA => tihi, + ENB => tihi, + SSRA => sinit1_q, + SSRB => sinit1_q, + WEA => weaf, + WEB => tilo + ); + +doutb0(64 to 77) <= doutb0_par(64 to 77); +dinfa0_par(64 to 95) <= dinfa(64 to 77) & (78 to 95 => '0'); + +U2 : RAMB16_S36_S36 +-- pragma translate_off +generic map( + sim_collision_check => "none") +-- pragma translate_on + port map + ( + DOA => open, + DOB => doutb0_par(64 to 95), + DOPA => open, + DOPB => open, + ADDRA => addra, + ADDRB => addrb0, + CLKA => clk2x, + CLKB => clk2x, + DIA => dinfa0_par(64 to 95), + DIB => dinfb, + DIPA => zeross, + DIPB => zeross, + ENA => tihi, + ENB => tihi, + SSRA => sinit1_q, + SSRB => sinit1_q, + WEA => weaf, + WEB => tilo + ); + +r_scan_out <= '0'; +w_scan_out <= '0'; +time_scan_out <= '0'; +obs0_scan_out <= '0'; +obs1_scan_out <= '0'; + +bo_pc_failout <= '0'; +bo_pc_diagloop <= '0'; + +unused <= or_reduce( std_ulogic_vector(doutb0_par(78 to 95)) + & abist_en & abist_raw_dc_b & r0e_abist_comp_en & r1e_abist_comp_en + & lbist_en & lcb_act_dis_dc & lcb_clkoff_dc_b & lcb_d_mode_dc + & lcb_delay_lclkr_dc & lcb_fce_0 & lcb_mpw1_dc_b & lcb_mpw2_dc_b + & lcb_scan_diag_dc & lcb_scan_dis_dc_b & lcb_sg_0 & lcb_time_sg_0 + & lcb_obs0_sg_0 & lcb_obs1_sg_0 & lcb_obs0_sl_thold_0 & lcb_obs1_sl_thold_0 + & lcb_abst_sl_thold_0 & lcb_time_sl_thold_0 & lcb_ary_nsl_thold_0 + & r_scan_in & w_scan_in & time_scan_in & obs0_scan_in & obs1_scan_in + & r0e_act & r0e_en_func & r0e_en_abist & r0e_addr_abist & r0e_byp_r & r0e_sel_lbist + & r1e_act & r1e_en_func & r1e_en_abist & r1e_addr_abist & r1e_byp_r & r1e_sel_lbist + & w0e_act & w0e_en_abist & w0e_addr_abist & w0e_data_abist + & w0l_act & w0l_en_abist & w0l_addr_abist & w0l_data_abist + & lcb_bolt_sl_thold_0 & pc_bo_enable_2 & pc_bo_reset + & pc_bo_unload & pc_bo_load & pc_bo_shdata & pc_bo_select + & tri_lcb_mpw1_dc_b & tri_lcb_mpw2_dc_b & tri_lcb_delay_lclkr_dc + & tri_lcb_clkoff_dc_b & tri_lcb_act_dis_dc ); + +end generate; + +end architecture tri_144x78_2r2w; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_144x78_2r2w_eco.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_144x78_2r2w_eco.vhdl new file mode 100644 index 0000000..f0ac6c9 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_144x78_2r2w_eco.vhdl @@ -0,0 +1,412 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee,ibm,support,tri; +use ieee.std_logic_1164.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_support.all; +use support.power_logic_pkg.all; +use tri.tri_latches_pkg.all; + +entity tri_144x78_2r2w_eco is +generic( + expand_type : integer := 1); +port ( + vdd :inout power_logic; + gnd :inout power_logic; + nclk :in clk_logic; + abist_en :in std_ulogic; + abist_raw_dc_b :in std_ulogic; + r0e_abist_comp_en :in std_ulogic; + r1e_abist_comp_en :in std_ulogic; + lbist_en :in std_ulogic; + + lcb_act_dis_dc :in std_ulogic; + lcb_clkoff_dc_b :in std_ulogic_vector(0 to 1); + lcb_d_mode_dc :in std_ulogic; + lcb_delay_lclkr_dc :in std_ulogic_vector(0 to 9); + lcb_fce_0 :in std_ulogic; + lcb_mpw1_dc_b :in std_ulogic_vector(1 to 9); + lcb_mpw2_dc_b :in std_ulogic; + lcb_scan_diag_dc :in std_ulogic; + lcb_scan_dis_dc_b :in std_ulogic; + lcb_sg_0 :in std_ulogic; + lcb_time_sg_0 :in std_ulogic; + + lcb_obs0_sg_0 :in std_ulogic; + lcb_obs1_sg_0 :in std_ulogic; + lcb_obs0_sl_thold_0 :in std_ulogic; + lcb_obs1_sl_thold_0 :in std_ulogic; + + lcb_abst_sl_thold_0 :in std_ulogic; + lcb_time_sl_thold_0 :in std_ulogic; + lcb_ary_nsl_thold_0 :in std_ulogic; + + r_scan_in :in std_ulogic; + r_scan_out :out std_ulogic; + w_scan_in :in std_ulogic; + w_scan_out :out std_ulogic; + time_scan_in :in std_ulogic; + time_scan_out :out std_ulogic; + obs0_scan_in :in std_ulogic; + obs0_scan_out :out std_ulogic; + obs1_scan_in :in std_ulogic; + obs1_scan_out :out std_ulogic; + + lcb_bolt_sl_thold_0 :in std_ulogic; + pc_bo_enable_2 :in std_ulogic; + pc_bo_reset :in std_ulogic; + pc_bo_unload :in std_ulogic; + pc_bo_load :in std_ulogic; + pc_bo_shdata :in std_ulogic; + pc_bo_select :in std_ulogic; + bo_pc_failout :out std_ulogic; + bo_pc_diagloop :out std_ulogic; + tri_lcb_mpw1_dc_b :in std_ulogic; + tri_lcb_mpw2_dc_b :in std_ulogic; + tri_lcb_delay_lclkr_dc :in std_ulogic; + tri_lcb_clkoff_dc_b :in std_ulogic; + tri_lcb_act_dis_dc :in std_ulogic; + + r0e_act :in std_ulogic; + r0e_en_func :in std_ulogic; + r0e_en_abist :in std_ulogic; + r0e_addr_func :in std_ulogic_vector(0 to 7); + r0e_addr_abist :in std_ulogic_vector(0 to 7); + r0e_data_out :out std_ulogic_vector(0 to 77); + r0e_byp_e :in std_ulogic; + r0e_byp_l :in std_ulogic; + r0e_byp_r :in std_ulogic; + r0e_sel_lbist :in std_ulogic; + + r1e_act :in std_ulogic; + r1e_en_func :in std_ulogic; + r1e_en_abist :in std_ulogic; + r1e_addr_func :in std_ulogic_vector(0 to 7); + r1e_addr_abist :in std_ulogic_vector(0 to 7); + r1e_data_out :out std_ulogic_vector(0 to 77); + r1e_byp_e :in std_ulogic; + r1e_byp_l :in std_ulogic; + r1e_byp_r :in std_ulogic; + r1e_sel_lbist :in std_ulogic; + + w0e_act :in std_ulogic; + w0e_en_func :in std_ulogic; + w0e_en_abist :in std_ulogic; + w0e_addr_func :in std_ulogic_vector(0 to 7); + w0e_addr_abist :in std_ulogic_vector(0 to 7); + w0e_data_func :in std_ulogic_vector(0 to 77); + w0e_data_abist :in std_ulogic_vector(0 to 3); + + w0l_act :in std_ulogic; + w0l_en_func :in std_ulogic; + w0l_en_abist :in std_ulogic; + w0l_addr_func :in std_ulogic_vector(0 to 7); + w0l_addr_abist :in std_ulogic_vector(0 to 7); + w0l_data_func :in std_ulogic_vector(0 to 77); + w0l_data_abist :in std_ulogic_vector(0 to 3) ); + + -- synopsys translate_off + -- synopsys translate_on + +end entity tri_144x78_2r2w_eco; +architecture tri_144x78_2r2w_eco of tri_144x78_2r2w_eco is + +begin + +a : if expand_type = 1 generate + +component RAMB16_S36_S36 +-- pragma translate_off + generic( + SIM_COLLISION_CHECK : string := "none"); +-- pragma translate_on + port( + DOA : out std_logic_vector(31 downto 0); + DOB : out std_logic_vector(31 downto 0); + DOPA : out std_logic_vector(3 downto 0); + DOPB : out std_logic_vector(3 downto 0); + ADDRA : in std_logic_vector(8 downto 0); + ADDRB : in std_logic_vector(8 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(31 downto 0); + DIB : in std_logic_vector(31 downto 0); + DIPA : in std_logic_vector(3 downto 0); + DIPB : in std_logic_vector(3 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic); +end component; + +-- pragma translate_off +-- pragma translate_on + +signal tilo : std_ulogic; +signal tihi : std_ulogic; +signal zeross : std_logic_vector(0 to 3); + +signal correct_clk : std_ulogic; +signal clk2x : std_ulogic; +signal reset : std_ulogic; +signal reset_hi : std_ulogic; +signal reset_lo : std_ulogic; +signal reset_q : std_ulogic; +signal sinit0_q : std_logic; +signal sinit1_q : std_logic; +signal flipper_d : std_ulogic; +signal flipper_q : std_ulogic; + +signal doutb0 : std_logic_vector(0 to 77); +signal doutb0_q : std_ulogic_vector(0 to 77); +signal dinfa0_par : std_logic_vector(64 to 95); +signal doutb0_par : std_logic_vector(64 to 95); +signal weaf : std_logic; +signal addra : std_logic_vector(0 to 8); +signal addrb0 : std_logic_vector(0 to 8); +signal dinfa : std_logic_vector(0 to 77); +signal dinfb : std_logic_vector(0 to 31); + +signal w0e_data_q : std_ulogic_vector(0 to 77); +signal w0l_data_q : std_ulogic_vector(0 to 77); +signal w0l_en_q : std_ulogic; +signal w0l_addr_q : std_ulogic_vector(0 to 7); +signal r1e_addr_q : std_ulogic_vector(0 to 7); + +signal r0e_byp_e_q : std_ulogic; +signal r0e_byp_l_q : std_ulogic; +signal r1e_byp_e_q : std_ulogic; +signal r1e_byp_l_q : std_ulogic; +signal r0_byp_sel : std_ulogic_vector(0 to 1); +signal r1_byp_sel : std_ulogic_vector(0 to 1); + +signal unused : std_ulogic; +-- synopsys translate_off +-- synopsys translate_on + +begin + + tilo <= '0'; + tihi <= '1'; + zeross <= (0 to 3 => '0'); + + reset <= nclk.sreset; + correct_clk <= nclk.clk; + clk2x <= nclk.clk2x; + + reset_hi <= reset; + reset_lo <= not reset_q after 1 ns ; + + + flipper_d <= not flipper_q; + + slatch: process (correct_clk,reset) begin + if rising_edge(correct_clk) then + if (reset = '1') then + w0l_en_q <= '0'; + r1e_addr_q <= (others => '0'); + r0e_byp_e_q <= '0'; + r0e_byp_l_q <= '0'; + r1e_byp_e_q <= '0'; + r1e_byp_l_q <= '0'; + + else + w0e_data_q <= w0e_data_func; + w0l_data_q <= w0l_data_func; + w0l_en_q <= w0l_en_func; + w0l_addr_q <= w0l_addr_func; + r1e_addr_q <= r1e_addr_func; + r0e_byp_e_q <= r0e_byp_e; + r0e_byp_l_q <= r0e_byp_l; + r1e_byp_e_q <= r1e_byp_e; + r1e_byp_l_q <= r1e_byp_l; + + end if; + end if; + end process; + + flatch: process (clk2x,reset_lo) begin + if clk2x'event and clk2x = '1' then + if (reset_lo = '0') then + flipper_q <= '0'; + + else + flipper_q <= flipper_d; + doutb0_q <= tconv(doutb0); + + end if; + end if; + end process; + + rlatch: process (correct_clk) begin + if(rising_edge(correct_clk)) then + reset_q <= reset_hi; + sinit0_q <= reset_hi; + sinit1_q <= reset_hi; + end if; + end process; + + + addra(0) <= '0'; + addra(1 to 8) <= (tconv((w0e_addr_func and (0 to 7 => flipper_q)) or (w0l_addr_q and (0 to 7 => not flipper_q)))) after 1 ns ; + weaf <= (( w0e_en_func and flipper_q) or ( w0l_en_q and not flipper_q)) after 1 ns; + dinfa <= (tconv((w0e_data_func and (0 to 77 => flipper_q)) or (w0l_data_q and (0 to 77 => not flipper_q)))) after 1 ns; + + dinfb <= (others => '0'); + addrb0(0) <= '0'; + addrb0(1 to 8) <= (tconv((r0e_addr_func and (0 to 7 => flipper_q)) or (r1e_addr_q and (0 to 7 => not flipper_q)))) after 1 ns ; + + r0_byp_sel <= r0e_byp_e & r0e_byp_l; + with r0_byp_sel select + r0e_data_out <= w0e_data_q when "10", + w0l_data_q when "01", + doutb0_q when others; + + r1_byp_sel <= r1e_byp_e & r1e_byp_l; + with r1_byp_sel select + r1e_data_out <= w0e_data_q when "10", + w0l_data_q when "01", + tconv(doutb0) when others; + + +U0 : RAMB16_S36_S36 +-- pragma translate_off +generic map( + sim_collision_check => "none") +-- pragma translate_on + port map + ( + DOA => open, + DOB => doutb0(0 to 31), + DOPA => open, + DOPB => open, + ADDRA => addra, + ADDRB => addrb0, + CLKA => clk2x, + CLKB => clk2x, + DIA => dinfa(0 to 31), + DIB => dinfb, + DIPA => zeross, + DIPB => zeross, + ENA => tihi, + ENB => tihi, + SSRA => sinit0_q, + SSRB => sinit0_q, + WEA => weaf, + WEB => tilo + ); +U1 : RAMB16_S36_S36 +-- pragma translate_off +generic map( + sim_collision_check => "none") +-- pragma translate_on + + port map + ( + DOA => open, + DOB => doutb0(32 to 63), + DOPA => open, + DOPB => open, + ADDRA => addra, + ADDRB => addrb0, + CLKA => clk2x, + CLKB => clk2x, + DIA => dinfa(32 to 63), + DIB => dinfb, + DIPA => zeross, + DIPB => zeross, + ENA => tihi, + ENB => tihi, + SSRA => sinit1_q, + SSRB => sinit1_q, + WEA => weaf, + WEB => tilo + ); + +doutb0(64 to 77) <= doutb0_par(64 to 77); +dinfa0_par(64 to 95) <= dinfa(64 to 77) & (78 to 95 => '0'); + +U2 : RAMB16_S36_S36 +-- pragma translate_off +generic map( + sim_collision_check => "none") +-- pragma translate_on + port map + ( + DOA => open, + DOB => doutb0_par(64 to 95), + DOPA => open, + DOPB => open, + ADDRA => addra, + ADDRB => addrb0, + CLKA => clk2x, + CLKB => clk2x, + DIA => dinfa0_par(64 to 95), + DIB => dinfb, + DIPA => zeross, + DIPB => zeross, + ENA => tihi, + ENB => tihi, + SSRA => sinit1_q, + SSRB => sinit1_q, + WEA => weaf, + WEB => tilo + ); + +r_scan_out <= '0'; +w_scan_out <= '0'; +time_scan_out <= '0'; +obs0_scan_out <= '0'; +obs1_scan_out <= '0'; + +bo_pc_failout <= '0'; +bo_pc_diagloop <= '0'; + +unused <= or_reduce( std_ulogic_vector(doutb0_par(78 to 95)) + & abist_en & abist_raw_dc_b & r0e_abist_comp_en & r1e_abist_comp_en + & lbist_en & lcb_act_dis_dc & lcb_clkoff_dc_b & lcb_d_mode_dc + & lcb_delay_lclkr_dc & lcb_fce_0 & lcb_mpw1_dc_b & lcb_mpw2_dc_b + & lcb_scan_diag_dc & lcb_scan_dis_dc_b & lcb_sg_0 & lcb_time_sg_0 + & lcb_obs0_sg_0 & lcb_obs1_sg_0 & lcb_obs0_sl_thold_0 & lcb_obs1_sl_thold_0 + & lcb_abst_sl_thold_0 & lcb_time_sl_thold_0 & lcb_ary_nsl_thold_0 + & r_scan_in & w_scan_in & time_scan_in & obs0_scan_in & obs1_scan_in + & r0e_act & r0e_en_func & r0e_en_abist & r0e_addr_abist & r0e_byp_r & r0e_sel_lbist + & r1e_act & r1e_en_func & r1e_en_abist & r1e_addr_abist & r1e_byp_r & r1e_sel_lbist + & w0e_act & w0e_en_abist & w0e_addr_abist & w0e_data_abist + & w0l_act & w0l_en_abist & w0l_addr_abist & w0l_data_abist + & lcb_bolt_sl_thold_0 & pc_bo_enable_2 & pc_bo_reset + & pc_bo_unload & pc_bo_load & pc_bo_shdata & pc_bo_select + & tri_lcb_mpw1_dc_b & tri_lcb_mpw2_dc_b & tri_lcb_delay_lclkr_dc + & tri_lcb_clkoff_dc_b & tri_lcb_act_dis_dc ); + +end generate; + +end architecture tri_144x78_2r2w_eco; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_256x162_4w_0.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_256x162_4w_0.vhdl new file mode 100644 index 0000000..a8284cd --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_256x162_4w_0.vhdl @@ -0,0 +1,359 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; use ieee.std_logic_1164.all ; +library ibm; use ibm.std_ulogic_support.all ; + use ibm.std_ulogic_function_support.all; +library support; + use support.power_logic_pkg.all; +library tri; use tri.tri_latches_pkg.all; + +entity tri_256x162_4w_0 is + generic (addressable_ports : positive := 256; + addressbus_width : positive := 8; + port_bitwidth : positive := 162; + ways : positive := 4; + expand_type : integer := 1); + port ( + gnd : inout power_logic; + vdd : inout power_logic; + vcs : inout power_logic; + nclk : in clk_logic; + ccflush_dc : in std_ulogic; + lcb_clkoff_dc_b : in std_ulogic; + lcb_d_mode_dc : in std_ulogic; + lcb_act_dis_dc : in std_ulogic; + lcb_ary_nsl_thold_0 : in std_ulogic; + lcb_sg_1 : in std_ulogic; + lcb_abst_sl_thold_0 : in std_ulogic; + scan_diag_dc : in std_ulogic; + scan_dis_dc_b : in std_ulogic; + abst_scan_in : in std_ulogic_vector(0 to 1); + abst_scan_out : out std_ulogic_vector(0 to 1); + lcb_delay_lclkr_np_dc : in std_ulogic; + ctrl_lcb_delay_lclkr_np_dc : in std_ulogic; + dibw_lcb_delay_lclkr_np_dc : in std_ulogic; + ctrl_lcb_mpw1_np_dc_b : in std_ulogic; + dibw_lcb_mpw1_np_dc_b : in std_ulogic; + lcb_mpw1_pp_dc_b : in std_ulogic; + lcb_mpw1_2_pp_dc_b : in std_ulogic; + aodo_lcb_delay_lclkr_dc : in std_ulogic; + aodo_lcb_mpw1_dc_b : in std_ulogic; + aodo_lcb_mpw2_dc_b : in std_ulogic; + lcb_time_sg_0 : in std_ulogic; + lcb_time_sl_thold_0 : in std_ulogic; + time_scan_in : in std_ulogic; + time_scan_out : out std_ulogic; + bitw_abist : in std_ulogic_vector(0 to 1); + lcb_repr_sl_thold_0 : in std_ulogic; + lcb_repr_sg_0 : in std_ulogic; + repr_scan_in : in std_ulogic; + repr_scan_out : out std_ulogic; + tc_lbist_ary_wrt_thru_dc : in std_ulogic; + abist_en_1 : in std_ulogic; + din_abist : in std_ulogic_vector(0 to 3); + abist_cmp_en : in std_ulogic; + abist_raw_b_dc : in std_ulogic; + data_cmp_abist : in std_ulogic_vector(0 to 3); + addr_abist : in std_ulogic_vector(0 to (addressbus_width-1)); + r_wb_abist : in std_ulogic; + write_thru_en_dc : in std_ulogic; + lcb_bolt_sl_thold_0 : in std_ulogic; + pc_bo_enable_2 : in std_ulogic; + pc_bo_reset : in std_ulogic; + pc_bo_unload : in std_ulogic; + pc_bo_repair : in std_ulogic; + pc_bo_shdata : in std_ulogic; + pc_bo_select : in std_ulogic_vector(0 to 1); + bo_pc_failout : out std_ulogic_vector(0 to 1); + bo_pc_diagloop : out std_ulogic_vector(0 to 1); + tri_lcb_mpw1_dc_b : in std_ulogic; + tri_lcb_mpw2_dc_b : in std_ulogic; + tri_lcb_delay_lclkr_dc : in std_ulogic; + tri_lcb_clkoff_dc_b : in std_ulogic; + tri_lcb_act_dis_dc : in std_ulogic; + read_act : in std_ulogic; + write_enable : in std_ulogic; + write_way : in std_ulogic_vector (0 to (ways-1)); + addr : in std_ulogic_vector (0 to (addressbus_width-1)); + data_in : in std_ulogic_vector (0 to (port_bitwidth-1)); + data_out : out std_ulogic_vector(0 to (port_bitwidth*ways-1)) +); + + -- synopsys translate_off + + -- synopsys translate_on + +end entity tri_256x162_4w_0; + +architecture tri_256x162_4w_0 of tri_256x162_4w_0 is + +constant wga_base_width : integer := 324; +constant wga_width_mult : integer := (port_bitwidth*ways-1)/wga_base_width + 1; +constant ramb_base_width : integer := 36; +constant ramb_base_addr : integer := 9; +constant ramb_width_mult : integer := (port_bitwidth-1)/ramb_base_width + 1; + + +type RAMB_DATA_ARRAY is array (natural range <>) of std_logic_vector(0 to (ramb_base_width*ramb_width_mult - 1)); + + +begin + + -- synopsys translate_off + um: if expand_type = 0 generate + signal tiup : std_ulogic; + signal tidn : std_ulogic; + + signal act : std_ulogic; + signal addr_l2 : std_ulogic_vector (0 TO addressbus_width-1); + signal write_way_l2 : std_ulogic_vector (0 TO write_way'right); + signal write_enable_d : std_ulogic; + signal write_enable_l2 : std_ulogic; + signal data_in_l2 : std_ulogic_vector(0 to port_bitwidth-1); + signal array_d : std_ulogic_vector(0 to addressable_ports*port_bitwidth*ways-1); + signal array_l2 : std_ulogic_vector(0 to addressable_ports*port_bitwidth*ways-1); + begin + tiup <= '1'; + tidn <= '0'; + + act <= read_act or or_reduce(write_way); + + addr_latch: tri_rlmreg_p + generic map (width => addr'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act, + scin => (others => '0'), + scout => open, + din => addr, + dout => addr_l2 ); + + write_way_latch: tri_rlmreg_p + generic map (width => write_way'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act, + scin => (others => '0'), + scout => open, + din => write_way, + dout => write_way_l2 ); + + write_enable_latch: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + scin => tidn, + scout => open, + din => write_enable_d, + dout => write_enable_l2 ); + + data_in_latch: tri_rlmreg_p + generic map (width => port_bitwidth, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act, + scin => (others => '0'), + scout => open, + din => data_in, + dout => data_in_l2 ); + + array_latch: tri_rlmreg_p + generic map (width => addressable_ports*port_bitwidth*ways, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + scin => (others => '0'), + scout => open, + din => array_d, + dout => array_l2 ); + + write_enable_d <= act and write_enable; + + ww: for w in 0 to ways-1 generate + begin + wy: for y in 0 to addressable_ports-1 generate + begin + wx: for x in 0 to port_bitwidth-1 generate + begin + array_d(y*port_bitwidth*ways+w*port_bitwidth+x) <= + data_in_l2(x) when (( write_enable_l2 and addr_l2 = tconv(y, addressbus_width) and + write_way_l2(w)) = '1') + else array_l2(y*port_bitwidth*ways+w*port_bitwidth+x); + + end generate wx; + end generate wy; + end generate ww; + + data_out <= array_l2( tconv(addr_l2)*port_bitwidth*ways to tconv(addr_l2)*port_bitwidth*ways+port_bitwidth*ways-1 ); + + abst_scan_out <= "00"; + time_scan_out <= '0'; + repr_scan_out <= '0'; + + bo_pc_failout <= "00"; + bo_pc_diagloop <= "00"; + + end generate um; + -- synopsys translate_on + + + a: if expand_type = 1 generate + component RAMB16_S36_S36 + -- pragma translate_off + generic( + SIM_COLLISION_CHECK : string := "none"); + -- pragma translate_on + port( + DOA : out std_logic_vector(31 downto 0); + DOB : out std_logic_vector(31 downto 0); + DOPA : out std_logic_vector(3 downto 0); + DOPB : out std_logic_vector(3 downto 0); + ADDRA : in std_logic_vector(8 downto 0); + ADDRB : in std_logic_vector(8 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(31 downto 0); + DIB : in std_logic_vector(31 downto 0); + DIPA : in std_logic_vector(3 downto 0); + DIPB : in std_logic_vector(3 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic); + end component; + + -- pragma translate_off + -- pragma translate_on + + signal ramb_data_in : std_logic_vector(0 to (ramb_base_width*ramb_width_mult - 1)); + signal ramb_data_out : RAMB_DATA_ARRAY(0 to ways-1); + signal ramb_addr : std_logic_vector(0 to ramb_base_addr - 1); + + signal act : std_ulogic_vector(0 to ways-1); + signal write : std_ulogic_vector(0 to ways-1); + signal tidn : std_ulogic; + signal unused : std_ulogic; + -- synopsys translate_off + -- synopsys translate_on + begin + + tidn <= '0'; + + add0: if (addressbus_width < ramb_base_addr) generate + begin + ramb_addr(0 to (ramb_base_addr-addressbus_width-1)) <= (others => '0'); + ramb_addr(ramb_base_addr-addressbus_width to ramb_base_addr-1) <= tconv( addr ); + end generate; + add1: if (addressbus_width >= ramb_base_addr) generate + begin + ramb_addr <= tconv( addr(addressbus_width-ramb_base_addr to addressbus_width-1) ); + end generate; + + din: for i in ramb_data_in'range generate + begin + R0: if(i < port_bitwidth) generate begin ramb_data_in(i) <= data_in(i); end generate; + R1: if(i >= port_bitwidth) generate begin ramb_data_in(i) <= '0'; end generate; + end generate; + + aw: for w in 0 to ways-1 generate begin + act(w) <= read_act or write_way(w); + write(w) <= write_enable and write_way(w); + + ax: for x in 0 to (ramb_width_mult - 1) generate begin + arr: RAMB16_S36_S36 + -- pragma translate_off + generic map( + sim_collision_check => "none") + -- pragma translate_on + port map( + DOA => ramb_data_out(w)(x*ramb_base_width to x*ramb_base_width+31), + DOB => open, + DOPA => ramb_data_out(w)(x*ramb_base_width+32 to x*ramb_base_width+35), + DOPB => open, + ADDRA => ramb_addr, + ADDRB => ramb_addr, + CLKA => nclk.clk, + CLKB => tidn, + DIA => ramb_data_in(x*ramb_base_width to x*ramb_base_width+31), + DIB => ramb_data_in(x*ramb_base_width to x*ramb_base_width+31), + DIPA => ramb_data_in(x*ramb_base_width+32 to x*ramb_base_width+35), + DIPB => ramb_data_in(x*ramb_base_width+32 to x*ramb_base_width+35), + ENA => act(w), + ENB => tidn, + SSRA => nclk.sreset, + SSRB => tidn, + WEA => write(w), + WEB => tidn + ); + + end generate ax; + + data_out(w*port_bitwidth to ((w+1)*port_bitwidth)-1 ) <= tconv( ramb_data_out(w)(0 to port_bitwidth-1) ); + + end generate aw; + + abst_scan_out <= "00"; + time_scan_out <= '0'; + repr_scan_out <= '0'; + + bo_pc_failout <= "00"; + bo_pc_diagloop <= "00"; + + unused <= or_reduce( std_ulogic_vector(ramb_data_out(0)(port_bitwidth to ramb_base_width*ramb_width_mult - 1)) + & std_ulogic_vector(ramb_data_out(1)(port_bitwidth to ramb_base_width*ramb_width_mult - 1)) + & std_ulogic_vector(ramb_data_out(2)(port_bitwidth to ramb_base_width*ramb_width_mult - 1)) + & std_ulogic_vector(ramb_data_out(3)(port_bitwidth to ramb_base_width*ramb_width_mult - 1)) + & ccflush_dc & lcb_clkoff_dc_b & lcb_d_mode_dc & lcb_act_dis_dc + & scan_dis_dc_b & scan_diag_dc & bitw_abist + & lcb_sg_1 & lcb_time_sg_0 & lcb_repr_sg_0 + & lcb_abst_sl_thold_0 & lcb_repr_sl_thold_0 + & lcb_time_sl_thold_0 & lcb_ary_nsl_thold_0 & tc_lbist_ary_wrt_thru_dc + & abist_en_1 & din_abist & abist_cmp_en & abist_raw_b_dc & data_cmp_abist + & addr_abist & r_wb_abist & write_thru_en_dc & abst_scan_in & time_scan_in & repr_scan_in + & lcb_delay_lclkr_np_dc & ctrl_lcb_delay_lclkr_np_dc & dibw_lcb_delay_lclkr_np_dc + & ctrl_lcb_mpw1_np_dc_b & dibw_lcb_mpw1_np_dc_b & lcb_mpw1_pp_dc_b & lcb_mpw1_2_pp_dc_b + & aodo_lcb_delay_lclkr_dc & aodo_lcb_mpw1_dc_b & aodo_lcb_mpw2_dc_b + & lcb_bolt_sl_thold_0 & pc_bo_enable_2 & pc_bo_reset + & pc_bo_unload & pc_bo_repair & pc_bo_shdata & pc_bo_select + & tri_lcb_mpw1_dc_b & tri_lcb_mpw2_dc_b & tri_lcb_delay_lclkr_dc + & tri_lcb_clkoff_dc_b & tri_lcb_act_dis_dc ); + + end generate a; + +end tri_256x162_4w_0; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_32x35_8w_1r1w.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_32x35_8w_1r1w.vhdl new file mode 100644 index 0000000..be9086f --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_32x35_8w_1r1w.vhdl @@ -0,0 +1,578 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; use ieee.std_logic_1164.all ; +library ibm; use ibm.std_ulogic_support.all ; + use ibm.std_ulogic_function_support.all; +library support; use support.power_logic_pkg.all; +library tri; use tri.tri_latches_pkg.all; + +-- pragma translate_off +-- pragma translate_on + +entity tri_32x35_8w_1r1w is + generic (addressable_ports : positive := 32; + addressbus_width : positive := 5; + port_bitwidth : positive := 35; + ways : positive := 8; + expand_type : integer := 1); + port ( + gnd : inout power_logic; + vdd : inout power_logic; + vcs : inout power_logic; + nclk : in clk_logic; + rd0_act : in std_ulogic; + sg_0 : in std_ulogic; + abst_slp_sl_thold_0 : in std_ulogic; + ary_slp_nsl_thold_0 : in std_ulogic; + time_sl_thold_0 : in std_ulogic; + repr_sl_thold_0 : in std_ulogic; + clkoff_dc_b : in std_ulogic; + ccflush_dc : in std_ulogic; + scan_dis_dc_b : in std_ulogic; + scan_diag_dc : in std_ulogic; + d_mode_dc : in std_ulogic; + mpw1_dc_b : in std_ulogic_vector(0 to 4); + mpw2_dc_b : in std_ulogic; + delay_lclkr_dc : in std_ulogic_vector(0 to 4); + wr_abst_act : in std_ulogic; + rd0_abst_act : in std_ulogic; + abist_di : in std_ulogic_vector(0 to 3); + abist_bw_odd : in std_ulogic; + abist_bw_even : in std_ulogic; + abist_wr_adr : in std_ulogic_vector(0 to 4); + abist_rd0_adr : in std_ulogic_vector(0 to 4); + tc_lbist_ary_wrt_thru_dc : in std_ulogic; + abist_ena_1 : in std_ulogic; + abist_g8t_rd0_comp_ena : in std_ulogic; + abist_raw_dc_b : in std_ulogic; + obs0_abist_cmp : in std_ulogic_vector(0 to 3); + abst_scan_in : in std_ulogic; + time_scan_in : in std_ulogic; + repr_scan_in : in std_ulogic; + abst_scan_out : out std_ulogic; + time_scan_out : out std_ulogic; + repr_scan_out : out std_ulogic; + lcb_bolt_sl_thold_0 : in std_ulogic; + pc_bo_enable_2 : in std_ulogic; + pc_bo_reset : in std_ulogic; + pc_bo_unload : in std_ulogic; + pc_bo_repair : in std_ulogic; + pc_bo_shdata : in std_ulogic; + pc_bo_select : in std_ulogic_vector(0 to 3); + bo_pc_failout : out std_ulogic_vector(0 to 3); + bo_pc_diagloop : out std_ulogic_vector(0 to 3); + tri_lcb_mpw1_dc_b : in std_ulogic; + tri_lcb_mpw2_dc_b : in std_ulogic; + tri_lcb_delay_lclkr_dc : in std_ulogic; + tri_lcb_clkoff_dc_b : in std_ulogic; + tri_lcb_act_dis_dc : in std_ulogic; + write_enable : in std_ulogic_vector (0 to ((port_bitwidth*ways-1)/(port_bitwidth*2))); + way : in std_ulogic_vector (0 to (ways-1)); + addr_wr : in std_ulogic_vector (0 to (addressbus_width-1)); + data_in : in std_ulogic_vector (0 to (port_bitwidth-1)); + addr_rd_01 : in std_ulogic_vector (0 to (addressbus_width-1)); + addr_rd_23 : in std_ulogic_vector (0 to (addressbus_width-1)); + addr_rd_45 : in std_ulogic_vector (0 to (addressbus_width-1)); + addr_rd_67 : in std_ulogic_vector (0 to (addressbus_width-1)); + data_out : out std_ulogic_vector(0 to (port_bitwidth*ways-1)) +); + + -- synopsys translate_off + + -- synopsys translate_on + +end entity tri_32x35_8w_1r1w; + +architecture tri_32x35_8w_1r1w of tri_32x35_8w_1r1w is + +constant wga_base_width : integer := 70; +constant wga_base_addr : integer := 5; +constant wga_width_mult : integer := (port_bitwidth*ways-1)/wga_base_width + 1; +constant ramb_base_width : integer := 36; +constant ramb_base_addr : integer := 9; +constant ramb_width_mult : integer := (port_bitwidth-1)/ramb_base_width + 1; + + + + +begin + + -- synopsys translate_off + um: if expand_type = 0 generate + signal tiup : std_ulogic; + signal tidn : std_ulogic; + + signal addr_rd_l2 : std_ulogic_vector (0 TO addressbus_width-1); + signal addr_wr_l2 : std_ulogic_vector (0 TO addressbus_width-1); + signal way_l2 : std_ulogic_vector (0 TO way'right); + signal write_enable_d : std_ulogic_vector(0 to wga_width_mult-1); + signal write_enable_l2 : std_ulogic_vector(0 to wga_width_mult-1); + signal data_in_l2 : std_ulogic_vector(0 to port_bitwidth-1); + signal array_d : std_ulogic_vector(0 to addressable_ports*port_bitwidth*ways-1); + signal array_l2 : std_ulogic_vector(0 to addressable_ports*port_bitwidth*ways-1); + signal act : std_ulogic; + begin + tiup <= '1'; + tidn <= '0'; + + act <= or_reduce(write_enable) or rd0_act; + + addr_rd_latch: tri_rlmreg_p + generic map (width => addr_rd_01'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => act, + scin => (others => '0'), + scout => open, + din => addr_rd_01, + dout => addr_rd_l2 ); + + addr_wr_latch: tri_rlmreg_p + generic map (width => addr_wr'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => act, + scin => (others => '0'), + scout => open, + din => addr_wr, + dout => addr_wr_l2 ); + + way_latch: tri_rlmreg_p + generic map (width => way'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => act, + scin => (others => '0'), + scout => open, + din => way, + dout => way_l2 ); + + write_enable_latch: tri_rlmreg_p + generic map (width => wga_width_mult, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => act, + scin => (others => '0'), + scout => open, + din => write_enable_d, + dout => write_enable_l2 ); + + data_in_latch: tri_rlmreg_p + generic map (width => port_bitwidth, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => act, + scin => (others => '0'), + scout => open, + din => data_in, + dout => data_in_l2 ); + + array_latch: tri_rlmreg_p + generic map (width => addressable_ports*port_bitwidth*ways, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => tiup, + scin => (others => '0'), + scout => open, + din => array_d, + dout => array_l2 ); + + write_enable_d <= write_enable; + + ww: for w in 0 to ways-1 generate + begin + wy: for y in 0 to addressable_ports-1 generate + begin + wx: for x in 0 to port_bitwidth-1 generate + begin + array_d(y*port_bitwidth*ways+w*port_bitwidth+x) <= + data_in_l2(x) when (( or_reduce(write_enable_l2) and addr_wr_l2 = tconv(y, addressbus_width) and + way_l2(w)) = '1') + else array_l2(y*port_bitwidth*ways+w*port_bitwidth+x); + + end generate wx; + end generate wy; + end generate ww; + + data_out <= array_l2( tconv(addr_rd_l2)*port_bitwidth*ways to tconv(addr_rd_l2)*port_bitwidth*ways+port_bitwidth*ways-1 ); + + abst_scan_out <= tidn; + time_scan_out <= tidn; + repr_scan_out <= tidn; + + bo_pc_failout <= "0000"; + bo_pc_diagloop <= "0000"; + end generate um; + -- synopsys translate_on + + a: if expand_type = 1 generate + component RAMB16_S36_S36 + -- pragma translate_off + generic( + SIM_COLLISION_CHECK : string := "none"); + -- pragma translate_on + port( + DOA : out std_logic_vector(31 downto 0); + DOB : out std_logic_vector(31 downto 0); + DOPA : out std_logic_vector(3 downto 0); + DOPB : out std_logic_vector(3 downto 0); + ADDRA : in std_logic_vector(8 downto 0); + ADDRB : in std_logic_vector(8 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(31 downto 0); + DIB : in std_logic_vector(31 downto 0); + DIPA : in std_logic_vector(3 downto 0); + DIPB : in std_logic_vector(3 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic); + end component; + + -- pragma translate_off + -- pragma translate_on + + signal array_wr_data : std_logic_vector(0 to port_bitwidth - 1); + signal ramb_data_in : std_logic_vector(0 to 35); + signal ramb_data_outA : std_logic_vector(0 to 35); + signal ramb_data_outB : std_logic_vector(0 to 35); + signal ramb_data_outC : std_logic_vector(0 to 35); + signal ramb_data_outD : std_logic_vector(0 to 35); + signal ramb_data_outE : std_logic_vector(0 to 35); + signal ramb_data_outF : std_logic_vector(0 to 35); + signal ramb_data_outG : std_logic_vector(0 to 35); + signal ramb_data_outH : std_logic_vector(0 to 35); + signal ramb_addr_wr : std_logic_vector(0 to ramb_base_addr - 1); + signal ramb_addr_rd : std_logic_vector(0 to ramb_base_addr - 1); + signal data_outA : std_ulogic_vector(0 to 35); + signal data_outB : std_ulogic_vector(0 to 35); + signal data_outC : std_ulogic_vector(0 to 35); + signal data_outD : std_ulogic_vector(0 to 35); + signal data_outE : std_ulogic_vector(0 to 35); + signal data_outF : std_ulogic_vector(0 to 35); + signal data_outG : std_ulogic_vector(0 to 35); + signal data_outH : std_ulogic_vector(0 to 35); + + signal rd_addr : std_ulogic_vector(0 to ramb_base_addr - 1); + signal wr_addr : std_ulogic_vector(0 to ramb_base_addr - 1); + signal write_enable_wA : std_ulogic; + signal write_enable_wB : std_ulogic; + signal write_enable_wC : std_ulogic; + signal write_enable_wD : std_ulogic; + signal write_enable_wE : std_ulogic; + signal write_enable_wF : std_ulogic; + signal write_enable_wG : std_ulogic; + signal write_enable_wH : std_ulogic; + signal tidn : std_logic_vector(0 to 35); + signal act : std_ulogic; + signal wen : std_ulogic; + signal unused : std_ulogic; + -- synopsys translate_off + -- synopsys translate_on + begin + + tidn <= (others=>'0'); + + wen <= or_reduce(write_enable); + act <= rd0_act or wen; + + array_wr_data <= tconv(data_in); + addr_calc : for t in 0 to 35 generate begin + R0 : if(t < 35 - (port_bitwidth-1)) generate begin ramb_data_in(t) <= '0'; end generate; + R1 : if(t >= 35 - (port_bitwidth-1)) generate begin ramb_data_in(t) <= array_wr_data(t-(35-(port_bitwidth-1))); end generate; + end generate addr_calc; + + write_enable_wA <= wen and way(0); + write_enable_wB <= wen and way(1); + write_enable_wC <= wen and way(2); + write_enable_wD <= wen and way(3); + write_enable_wE <= wen and way(4); + write_enable_wF <= wen and way(5); + write_enable_wG <= wen and way(6); + write_enable_wH <= wen and way(7); + + rambAddrCalc : for t in 0 to ramb_base_addr-1 generate begin + R0 : if(t < ramb_base_addr-addressbus_width) generate begin + rd_addr(t) <= '0'; + wr_addr(t) <= '0'; + end generate; + R1 : if(t >= ramb_base_addr-addressbus_width) generate begin + rd_addr(t) <= addr_rd_01(t-(ramb_base_addr-addressbus_width)); + wr_addr(t) <= addr_wr(t-(ramb_base_addr-addressbus_width)); + end generate; + end generate rambAddrCalc; + + ramb_addr_wr <= tconv(wr_addr); + ramb_addr_rd <= tconv(rd_addr); + + data_outA <= tconv(ramb_data_outA); + data_outB <= tconv(ramb_data_outB); + data_outC <= tconv(ramb_data_outC); + data_outD <= tconv(ramb_data_outD); + data_outE <= tconv(ramb_data_outE); + data_outF <= tconv(ramb_data_outF); + data_outG <= tconv(ramb_data_outG); + data_outH <= tconv(ramb_data_outH); + + data_out <= data_outA((35-(port_bitwidth-1)) to 35) & data_outB((35-(port_bitwidth-1)) to 35) & + data_outC((35-(port_bitwidth-1)) to 35) & data_outD((35-(port_bitwidth-1)) to 35) & + data_outE((35-(port_bitwidth-1)) to 35) & data_outF((35-(port_bitwidth-1)) to 35) & + data_outG((35-(port_bitwidth-1)) to 35) & data_outH((35-(port_bitwidth-1)) to 35); + + arr0_A: RAMB16_S36_S36 + -- pragma translate_off + generic map( + sim_collision_check => "none") + -- pragma translate_on + port map( + DOA => ramb_data_outA(0 to 31), + DOB => open, + DOPA => ramb_data_outA(32 to 35), + DOPB => open, + ADDRA => ramb_addr_rd, + ADDRB => ramb_addr_wr, + CLKA => nclk.clk, + CLKB => nclk.clk, + DIA => tidn(0 to 31), + DIB => ramb_data_in(0 to 31), + DIPA => tidn(32 to 35), + DIPB => ramb_data_in(32 to 35), + ENA => act, + ENB => act, + SSRA => nclk.sreset, + SSRB => nclk.sreset, + WEA => tidn(0), + WEB => write_enable_wA + ); + + arr1_B: RAMB16_S36_S36 + -- pragma translate_off + generic map( + sim_collision_check => "none") + -- pragma translate_on + port map( + DOA => ramb_data_outB(0 to 31), + DOB => open, + DOPA => ramb_data_outB(32 to 35), + DOPB => open, + ADDRA => ramb_addr_rd, + ADDRB => ramb_addr_wr, + CLKA => nclk.clk, + CLKB => nclk.clk, + DIA => tidn(0 to 31), + DIB => ramb_data_in(0 to 31), + DIPA => tidn(32 to 35), + DIPB => ramb_data_in(32 to 35), + ENA => act, + ENB => act, + SSRA => nclk.sreset, + SSRB => nclk.sreset, + WEA => tidn(0), + WEB => write_enable_wB + ); + + arr2_C: RAMB16_S36_S36 + -- pragma translate_off + generic map( + sim_collision_check => "none") + -- pragma translate_on + port map( + DOA => ramb_data_outC(0 to 31), + DOB => open, + DOPA => ramb_data_outC(32 to 35), + DOPB => open, + ADDRA => ramb_addr_rd, + ADDRB => ramb_addr_wr, + CLKA => nclk.clk, + CLKB => nclk.clk, + DIA => tidn(0 to 31), + DIB => ramb_data_in(0 to 31), + DIPA => tidn(32 to 35), + DIPB => ramb_data_in(32 to 35), + ENA => act, + ENB => act, + SSRA => nclk.sreset, + SSRB => nclk.sreset, + WEA => tidn(0), + WEB => write_enable_wC + ); + + arr3_D: RAMB16_S36_S36 + -- pragma translate_off + generic map( + sim_collision_check => "none") + -- pragma translate_on + port map( + DOA => ramb_data_outD(0 to 31), + DOB => open, + DOPA => ramb_data_outD(32 to 35), + DOPB => open, + ADDRA => ramb_addr_rd, + ADDRB => ramb_addr_wr, + CLKA => nclk.clk, + CLKB => nclk.clk, + DIA => tidn(0 to 31), + DIB => ramb_data_in(0 to 31), + DIPA => tidn(32 to 35), + DIPB => ramb_data_in(32 to 35), + ENA => act, + ENB => act, + SSRA => nclk.sreset, + SSRB => nclk.sreset, + WEA => tidn(0), + WEB => write_enable_wD + ); + + arr4_E: RAMB16_S36_S36 + -- pragma translate_off + generic map( + sim_collision_check => "none") + -- pragma translate_on + port map( + DOA => ramb_data_outE(0 to 31), + DOB => open, + DOPA => ramb_data_outE(32 to 35), + DOPB => open, + ADDRA => ramb_addr_rd, + ADDRB => ramb_addr_wr, + CLKA => nclk.clk, + CLKB => nclk.clk, + DIA => tidn(0 to 31), + DIB => ramb_data_in(0 to 31), + DIPA => tidn(32 to 35), + DIPB => ramb_data_in(32 to 35), + ENA => act, + ENB => act, + SSRA => nclk.sreset, + SSRB => nclk.sreset, + WEA => tidn(0), + WEB => write_enable_wE + ); + + arr5_F: RAMB16_S36_S36 + -- pragma translate_off + generic map( + sim_collision_check => "none") + -- pragma translate_on + port map( + DOA => ramb_data_outF(0 to 31), + DOB => open, + DOPA => ramb_data_outF(32 to 35), + DOPB => open, + ADDRA => ramb_addr_rd, + ADDRB => ramb_addr_wr, + CLKA => nclk.clk, + CLKB => nclk.clk, + DIA => tidn(0 to 31), + DIB => ramb_data_in(0 to 31), + DIPA => tidn(32 to 35), + DIPB => ramb_data_in(32 to 35), + ENA => act, + ENB => act, + SSRA => nclk.sreset, + SSRB => nclk.sreset, + WEA => tidn(0), + WEB => write_enable_wF + ); + + arr6_G: RAMB16_S36_S36 + -- pragma translate_off + generic map( + sim_collision_check => "none") + -- pragma translate_on + port map( + DOA => ramb_data_outG(0 to 31), + DOB => open, + DOPA => ramb_data_outG(32 to 35), + DOPB => open, + ADDRA => ramb_addr_rd, + ADDRB => ramb_addr_wr, + CLKA => nclk.clk, + CLKB => nclk.clk, + DIA => tidn(0 to 31), + DIB => ramb_data_in(0 to 31), + DIPA => tidn(32 to 35), + DIPB => ramb_data_in(32 to 35), + ENA => act, + ENB => act, + SSRA => nclk.sreset, + SSRB => nclk.sreset, + WEA => tidn(0), + WEB => write_enable_wG + ); + + arr7_H: RAMB16_S36_S36 + -- pragma translate_off + generic map( + sim_collision_check => "none") + -- pragma translate_on + port map( + DOA => ramb_data_outH(0 to 31), + DOB => open, + DOPA => ramb_data_outH(32 to 35), + DOPB => open, + ADDRA => ramb_addr_rd, + ADDRB => ramb_addr_wr, + CLKA => nclk.clk, + CLKB => nclk.clk, + DIA => tidn(0 to 31), + DIB => ramb_data_in(0 to 31), + DIPA => tidn(32 to 35), + DIPB => ramb_data_in(32 to 35), + ENA => act, + ENB => act, + SSRA => nclk.sreset, + SSRB => nclk.sreset, + WEA => tidn(0), + WEB => write_enable_wH + ); + + abst_scan_out <= tidn(0); + time_scan_out <= tidn(0); + repr_scan_out <= tidn(0); + + bo_pc_failout <= "0000"; + bo_pc_diagloop <= "0000"; + + unused <= or_reduce( data_outA(0) & data_outB(0) & data_outC(0) & data_outD(0) + & data_outE(0) & data_outF(0) & data_outG(0) & data_outH(0) + & sg_0 & abst_slp_sl_thold_0 & ary_slp_nsl_thold_0 + & time_sl_thold_0 & repr_sl_thold_0 & clkoff_dc_b & ccflush_dc + & scan_dis_dc_b & scan_diag_dc & d_mode_dc & mpw1_dc_b & mpw2_dc_b + & delay_lclkr_dc & wr_abst_act & rd0_abst_act & abist_di + & abist_bw_odd & abist_bw_even & abist_wr_adr & abist_rd0_adr + & tc_lbist_ary_wrt_thru_dc & abist_ena_1 & abist_g8t_rd0_comp_ena + & abist_raw_dc_b & obs0_abist_cmp & abst_scan_in & time_scan_in + & repr_scan_in & addr_rd_23 & addr_rd_45 & addr_rd_67 + & lcb_bolt_sl_thold_0 & pc_bo_enable_2 & pc_bo_reset + & pc_bo_unload & pc_bo_repair & pc_bo_shdata & pc_bo_select + & tri_lcb_mpw1_dc_b & tri_lcb_mpw2_dc_b & tri_lcb_delay_lclkr_dc + & tri_lcb_clkoff_dc_b & tri_lcb_act_dis_dc ); + end generate a; + +end tri_32x35_8w_1r1w; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_512x288_9.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_512x288_9.vhdl new file mode 100644 index 0000000..76aa508 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_512x288_9.vhdl @@ -0,0 +1,762 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; use ieee.std_logic_1164.all ; +library ibm; use ibm.std_ulogic_support.all ; + use ibm.std_ulogic_function_support.all; +library support; use support.power_logic_pkg.all; +library tri; use tri.tri_latches_pkg.all; + +entity tri_512x288_9 is + generic (addressable_ports : positive := 512; + addressbus_width : positive := 6; + port_bitwidth : positive := 288; + bit_write_type : positive := 9; + ways : positive := 1; + expand_type : integer := 1); + port ( + gnd : inout power_logic; + vdd : inout power_logic; + vcs : inout power_logic; + nclk : in clk_logic; + act : in std_ulogic; + sg_0 : in std_ulogic; + sg_1 : in std_ulogic; + ary_nsl_thold_0 : in std_ulogic; + abst_sl_thold_0 : in std_ulogic; + time_sl_thold_0 : in std_ulogic; + repr_sl_thold_0 : in std_ulogic; + clkoff_dc_b : in std_ulogic; + ccflush_dc : in std_ulogic; + scan_dis_dc_b : in std_ulogic; + scan_diag_dc : in std_ulogic; + d_mode_dc : in std_ulogic; + act_dis_dc : in std_ulogic; + lcb_delay_lclkr_np_dc : in std_ulogic; + ctrl_lcb_delay_lclkr_np_dc : in std_ulogic; + dibw_lcb_delay_lclkr_np_dc : in std_ulogic; + ctrl_lcb_mpw1_np_dc_b : in std_ulogic; + dibw_lcb_mpw1_np_dc_b : in std_ulogic; + lcb_mpw1_pp_dc_b : in std_ulogic; + lcb_mpw1_2_pp_dc_b : in std_ulogic; + aodo_lcb_delay_lclkr_dc : in std_ulogic; + aodo_lcb_mpw1_dc_b : in std_ulogic; + aodo_lcb_mpw2_dc_b : in std_ulogic; + bitw_abist : in std_ulogic_vector(0 to 1); + tc_lbist_ary_wrt_thru_dc : in std_ulogic; + abist_en_1 : in std_ulogic; + din_abist : in std_ulogic_vector(0 to 3); + abist_cmp_en : in std_ulogic; + abist_raw_b_dc : in std_ulogic; + data_cmp_abist : in std_ulogic_vector(0 to 3); + addr_abist : in std_ulogic_vector(0 to 8); + r_wb_abist : in std_ulogic; + abst_scan_in : in std_ulogic_vector(0 to 1); + time_scan_in : in std_ulogic; + repr_scan_in : in std_ulogic; + abst_scan_out : out std_ulogic_vector(0 to 1); + time_scan_out : out std_ulogic; + repr_scan_out : out std_ulogic; + lcb_bolt_sl_thold_0 : in std_ulogic; + pc_bo_enable_2 : in std_ulogic; + pc_bo_reset : in std_ulogic; + pc_bo_unload : in std_ulogic; + pc_bo_repair : in std_ulogic; + pc_bo_shdata : in std_ulogic; + pc_bo_select : in std_ulogic_vector(0 to 1); + bo_pc_failout : out std_ulogic_vector(0 to 1); + bo_pc_diagloop : out std_ulogic_vector(0 to 1); + tri_lcb_mpw1_dc_b : in std_ulogic; + tri_lcb_mpw2_dc_b : in std_ulogic; + tri_lcb_delay_lclkr_dc : in std_ulogic; + tri_lcb_clkoff_dc_b : in std_ulogic; + tri_lcb_act_dis_dc : in std_ulogic; + write_enable : in std_ulogic; + bw : in std_ulogic_vector (0 to (port_bitwidth-1)); + arr_up_addr : in std_ulogic_vector (0 to 2); + addr : in std_ulogic_vector (0 to (addressbus_width-1)); + data_in : in std_ulogic_vector (0 to (port_bitwidth-1)); + data_out : out std_ulogic_vector(0 to (port_bitwidth*ways-1)) +); + + -- synopsys translate_off + + -- synopsys translate_on + +end entity tri_512x288_9; + +architecture tri_512x288_9 of tri_512x288_9 is + + + + +constant ramb_base_addr : integer := 11; + +begin + + -- synopsys translate_off + um: if expand_type = 0 generate + signal tiup : std_ulogic; + signal tidn : std_ulogic; + + signal addr_l2 : std_ulogic_vector(0 TO addressbus_width-1); + signal bw_l2 : std_ulogic_vector(0 TO bw'right); + signal write_enable_d : std_ulogic; + signal write_enable_l2 : std_ulogic; + signal data_in_l2 : std_ulogic_vector(0 to port_bitwidth-1); + signal array_d : std_ulogic_vector(0 to addressable_ports*port_bitwidth*ways-1); + signal array_l2 : std_ulogic_vector(0 to addressable_ports*port_bitwidth*ways-1); + begin + tiup <= '1'; + tidn <= '0'; + + addr_latch: tri_rlmreg_p + generic map (width => addr'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act, + scin => (others => '0'), + scout => open, + din => addr, + dout => addr_l2 ); + + bw_latch: tri_rlmreg_p + generic map (width => bw'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act, + scin => (others => '0'), + scout => open, + din => bw, + dout => bw_l2 ); + + write_enable_latch: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + scin => tidn, + scout => open, + din => write_enable_d, + dout => write_enable_l2 ); + + data_in_latch: tri_rlmreg_p + generic map (width => port_bitwidth, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act, + scin => (others => '0'), + scout => open, + din => data_in, + dout => data_in_l2 ); + + array_latch: tri_rlmreg_p + generic map (width => addressable_ports*port_bitwidth*ways, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + scin => (others => '0'), + scout => open, + din => array_d, + dout => array_l2 ); + + write_enable_d <= act and write_enable; + + ww: for w in 0 to ways-1 generate + begin + wy: for y in 0 to addressable_ports-1 generate + begin + wx: for x in 0 to port_bitwidth-1 generate + begin + array_d(y*port_bitwidth*ways+w*port_bitwidth+x) <= + data_in_l2(x) when (( write_enable_l2 and addr_l2 = tconv(y, addressbus_width) and bw_l2(x/bit_write_type) ) = '1') + else array_l2(y*port_bitwidth*ways+w*port_bitwidth+x); + + end generate wx; + end generate wy; + end generate ww; + + data_out <= array_l2( tconv(addr_l2)*port_bitwidth*ways to tconv(addr_l2)*port_bitwidth*ways+port_bitwidth*ways-1 ); + + abst_scan_out <= (others=>'0'); + time_scan_out <= tidn; + repr_scan_out <= tidn; + + bo_pc_failout <= (others=>'0'); + bo_pc_diagloop <= (others=>'0'); + end generate um; + -- synopsys translate_on + + a: if expand_type = 1 generate + component RAMB16_S9_S9 + -- pragma translate_off + generic + ( + SIM_COLLISION_CHECK : string := "none"); + -- pragma translate_on + port + ( + DOA : out std_logic_vector(7 downto 0); + DOB : out std_logic_vector(7 downto 0); + DOPA : out std_logic_vector(0 downto 0); + DOPB : out std_logic_vector(0 downto 0); + ADDRA : in std_logic_vector(10 downto 0); + ADDRB : in std_logic_vector(10 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(7 downto 0); + DIB : in std_logic_vector(7 downto 0); + DIPA : in std_logic_vector(0 downto 0); + DIPB : in std_logic_vector(0 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); + end component; + + -- pragma translate_off + -- pragma translate_on + + constant addresswidth : integer := addressbus_width+3+1; + signal arr_data_in : std_logic_vector(0 to 287); + signal ramb_data_in : std_logic_vector(0 to 255); + signal ramb_parity_in : std_logic_vector(0 to 31); + signal ramb_uh_addr : std_ulogic_vector(0 to 10); + signal ramb_lh_addr : std_ulogic_vector(0 to 10); + signal uh_addr : std_ulogic_vector(0 to addresswidth-1); + signal lh_addr : std_ulogic_vector(0 to addresswidth-1); + signal ramb_data_out : std_logic_vector(0 to 255); + signal ramb_parity_out : std_logic_vector(0 to 31); + + signal tidn : std_ulogic; + signal wrt_en_wAH : std_ulogic_vector(0 to 31); + signal bitWrt : std_ulogic_vector(0 to 31); + signal rdDataOut : std_ulogic_vector(0 to 255); + signal rdParityOut : std_ulogic_vector(0 to 31); + + signal unused : std_ulogic; + -- synopsys translate_off + -- synopsys translate_on + begin + + tidn <= '0'; + + arr_data_in <= tconv(data_in); + + dWFixUp : for t in 0 to 31 generate begin + ramb_data_in((8*t) to (8*t)+7) <= arr_data_in(t+0) & arr_data_in(t+32) & arr_data_in(t+64) & arr_data_in(t+96) & + arr_data_in(t+144) & arr_data_in(t+176) & arr_data_in(t+208) & arr_data_in(t+240); + ramb_parity_in(t) <= arr_data_in(t+128+(128*(t/16))); + bitWrt(t) <= bw(t); + end generate dWFixUp; + + wrtEn_gen : for t in 0 to 31 generate begin + wrt_en_wAH(t) <= write_enable and bitWrt(t); + end generate wrtEn_gen; + + uh_addr <= arr_up_addr & addr & '0'; + lh_addr <= arr_up_addr & addr & '1'; + + rambAddrCalc : for t in 0 to ramb_base_addr-1 generate begin + R0 : if(t < ramb_base_addr-addresswidth) generate begin + ramb_uh_addr(t) <= '0'; + ramb_lh_addr(t) <= '0'; + end generate; + R1 : if(t >= ramb_base_addr-addresswidth) generate begin + ramb_uh_addr(t) <= uh_addr(t-(ramb_base_addr-addresswidth)); + ramb_lh_addr(t) <= lh_addr(t-(ramb_base_addr-addresswidth)); + end generate; + end generate rambAddrCalc; + + dRFixUp : for t in 0 to 31 generate begin + data_out(t+0) <= rdDataOut((t*8)+0); + data_out(t+32) <= rdDataOut((t*8)+1); + data_out(t+64) <= rdDataOut((t*8)+2); + data_out(t+96) <= rdDataOut((t*8)+3); + data_out(t+144) <= rdDataOut((t*8)+4); + data_out(t+176) <= rdDataOut((t*8)+5); + data_out(t+208) <= rdDataOut((t*8)+6); + data_out(t+240) <= rdDataOut((t*8)+7); + data_out(t+128+(128*(t/16))) <= rdParityOut(t); + end generate dRFixUp; + + rdDataOut <= tconv(ramb_data_out); + rdParityOut <= tconv(ramb_parity_out); + + arr0: RAMB16_S9_S9 + -- pragma translate_off + generic map( + sim_collision_check => "none") + -- pragma translate_on + port map( + DOA => ramb_data_out(0 to 7), + DOB => ramb_data_out(128 to 135), + DOPA => ramb_parity_out(0 to 0), + DOPB => ramb_parity_out(16 to 16), + ADDRA => tconv(ramb_uh_addr), + ADDRB => tconv(ramb_lh_addr), + CLKA => nclk.clk, + CLKB => nclk.clk, + DIA => ramb_data_in(0 to 7), + DIB => ramb_data_in(128 to 135), + DIPA => ramb_parity_in(0 to 0), + DIPB => ramb_parity_in(16 to 16), + ENA => act, + ENB => act, + SSRA => nclk.sreset, + SSRB => nclk.sreset, + WEA => wrt_en_wAH(0), + WEB => wrt_en_wAH(16) + ); + + arr1: RAMB16_S9_S9 + -- pragma translate_off + generic map( + sim_collision_check => "none") + -- pragma translate_on + port map( + DOA => ramb_data_out(8 to 15), + DOB => ramb_data_out(136 to 143), + DOPA => ramb_parity_out(1 to 1), + DOPB => ramb_parity_out(17 to 17), + ADDRA => tconv(ramb_uh_addr), + ADDRB => tconv(ramb_lh_addr), + CLKA => nclk.clk, + CLKB => nclk.clk, + DIA => ramb_data_in(8 to 15), + DIB => ramb_data_in(136 to 143), + DIPA => ramb_parity_in(1 to 1), + DIPB => ramb_parity_in(17 to 17), + ENA => act, + ENB => act, + SSRA => nclk.sreset, + SSRB => nclk.sreset, + WEA => wrt_en_wAH(1), + WEB => wrt_en_wAH(17) + ); + + arr2: RAMB16_S9_S9 + -- pragma translate_off + generic map( + sim_collision_check => "none") + -- pragma translate_on + port map( + DOA => ramb_data_out(16 to 23), + DOB => ramb_data_out(144 to 151), + DOPA => ramb_parity_out(2 to 2), + DOPB => ramb_parity_out(18 to 18), + ADDRA => tconv(ramb_uh_addr), + ADDRB => tconv(ramb_lh_addr), + CLKA => nclk.clk, + CLKB => nclk.clk, + DIA => ramb_data_in(16 to 23), + DIB => ramb_data_in(144 to 151), + DIPA => ramb_parity_in(2 to 2), + DIPB => ramb_parity_in(18 to 18), + ENA => act, + ENB => act, + SSRA => nclk.sreset, + SSRB => nclk.sreset, + WEA => wrt_en_wAH(2), + WEB => wrt_en_wAH(18) + ); + + arr3: RAMB16_S9_S9 + -- pragma translate_off + generic map( + sim_collision_check => "none") + -- pragma translate_on + port map( + DOA => ramb_data_out(24 to 31), + DOB => ramb_data_out(152 to 159), + DOPA => ramb_parity_out(3 to 3), + DOPB => ramb_parity_out(19 to 19), + ADDRA => tconv(ramb_uh_addr), + ADDRB => tconv(ramb_lh_addr), + CLKA => nclk.clk, + CLKB => nclk.clk, + DIA => ramb_data_in(24 to 31), + DIB => ramb_data_in(152 to 159), + DIPA => ramb_parity_in(3 to 3), + DIPB => ramb_parity_in(19 to 19), + ENA => act, + ENB => act, + SSRA => nclk.sreset, + SSRB => nclk.sreset, + WEA => wrt_en_wAH(3), + WEB => wrt_en_wAH(19) + ); + + arr4: RAMB16_S9_S9 + -- pragma translate_off + generic map( + sim_collision_check => "none") + -- pragma translate_on + port map( + DOA => ramb_data_out(32 to 39), + DOB => ramb_data_out(160 to 167), + DOPA => ramb_parity_out(4 to 4), + DOPB => ramb_parity_out(20 to 20), + ADDRA => tconv(ramb_uh_addr), + ADDRB => tconv(ramb_lh_addr), + CLKA => nclk.clk, + CLKB => nclk.clk, + DIA => ramb_data_in(32 to 39), + DIB => ramb_data_in(160 to 167), + DIPA => ramb_parity_in(4 to 4), + DIPB => ramb_parity_in(20 to 20), + ENA => act, + ENB => act, + SSRA => nclk.sreset, + SSRB => nclk.sreset, + WEA => wrt_en_wAH(4), + WEB => wrt_en_wAH(20) + ); + + arr5: RAMB16_S9_S9 + -- pragma translate_off + generic map( + sim_collision_check => "none") + -- pragma translate_on + port map( + DOA => ramb_data_out(40 to 47), + DOB => ramb_data_out(168 to 175), + DOPA => ramb_parity_out(5 to 5), + DOPB => ramb_parity_out(21 to 21), + ADDRA => tconv(ramb_uh_addr), + ADDRB => tconv(ramb_lh_addr), + CLKA => nclk.clk, + CLKB => nclk.clk, + DIA => ramb_data_in(40 to 47), + DIB => ramb_data_in(168 to 175), + DIPA => ramb_parity_in(5 to 5), + DIPB => ramb_parity_in(21 to 21), + ENA => act, + ENB => act, + SSRA => nclk.sreset, + SSRB => nclk.sreset, + WEA => wrt_en_wAH(5), + WEB => wrt_en_wAH(21) + ); + + arr6: RAMB16_S9_S9 + -- pragma translate_off + generic map( + sim_collision_check => "none") + -- pragma translate_on + port map( + DOA => ramb_data_out(48 to 55), + DOB => ramb_data_out(176 to 183), + DOPA => ramb_parity_out(6 to 6), + DOPB => ramb_parity_out(22 to 22), + ADDRA => tconv(ramb_uh_addr), + ADDRB => tconv(ramb_lh_addr), + CLKA => nclk.clk, + CLKB => nclk.clk, + DIA => ramb_data_in(48 to 55), + DIB => ramb_data_in(176 to 183), + DIPA => ramb_parity_in(6 to 6), + DIPB => ramb_parity_in(22 to 22), + ENA => act, + ENB => act, + SSRA => nclk.sreset, + SSRB => nclk.sreset, + WEA => wrt_en_wAH(6), + WEB => wrt_en_wAH(22) + ); + + arr7: RAMB16_S9_S9 + -- pragma translate_off + generic map( + sim_collision_check => "none") + -- pragma translate_on + port map( + DOA => ramb_data_out(56 to 63), + DOB => ramb_data_out(184 to 191), + DOPA => ramb_parity_out(7 to 7), + DOPB => ramb_parity_out(23 to 23), + ADDRA => tconv(ramb_uh_addr), + ADDRB => tconv(ramb_lh_addr), + CLKA => nclk.clk, + CLKB => nclk.clk, + DIA => ramb_data_in(56 to 63), + DIB => ramb_data_in(184 to 191), + DIPA => ramb_parity_in(7 to 7), + DIPB => ramb_parity_in(23 to 23), + ENA => act, + ENB => act, + SSRA => nclk.sreset, + SSRB => nclk.sreset, + WEA => wrt_en_wAH(7), + WEB => wrt_en_wAH(23) + ); + + arr8: RAMB16_S9_S9 + -- pragma translate_off + generic map( + sim_collision_check => "none") + -- pragma translate_on + port map( + DOA => ramb_data_out(64 to 71), + DOB => ramb_data_out(192 to 199), + DOPA => ramb_parity_out(8 to 8), + DOPB => ramb_parity_out(24 to 24), + ADDRA => tconv(ramb_uh_addr), + ADDRB => tconv(ramb_lh_addr), + CLKA => nclk.clk, + CLKB => nclk.clk, + DIA => ramb_data_in(64 to 71), + DIB => ramb_data_in(192 to 199), + DIPA => ramb_parity_in(8 to 8), + DIPB => ramb_parity_in(24 to 24), + ENA => act, + ENB => act, + SSRA => nclk.sreset, + SSRB => nclk.sreset, + WEA => wrt_en_wAH(8), + WEB => wrt_en_wAH(24) + ); + + arr9: RAMB16_S9_S9 + -- pragma translate_off + generic map( + sim_collision_check => "none") + -- pragma translate_on + port map( + DOA => ramb_data_out(72 to 79), + DOB => ramb_data_out(200 to 207), + DOPA => ramb_parity_out(9 to 9), + DOPB => ramb_parity_out(25 to 25), + ADDRA => tconv(ramb_uh_addr), + ADDRB => tconv(ramb_lh_addr), + CLKA => nclk.clk, + CLKB => nclk.clk, + DIA => ramb_data_in(72 to 79), + DIB => ramb_data_in(200 to 207), + DIPA => ramb_parity_in(9 to 9), + DIPB => ramb_parity_in(25 to 25), + ENA => act, + ENB => act, + SSRA => nclk.sreset, + SSRB => nclk.sreset, + WEA => wrt_en_wAH(9), + WEB => wrt_en_wAH(25) + ); + + arrA: RAMB16_S9_S9 + -- pragma translate_off + generic map( + sim_collision_check => "none") + -- pragma translate_on + port map( + DOA => ramb_data_out(80 to 87), + DOB => ramb_data_out(208 to 215), + DOPA => ramb_parity_out(10 to 10), + DOPB => ramb_parity_out(26 to 26), + ADDRA => tconv(ramb_uh_addr), + ADDRB => tconv(ramb_lh_addr), + CLKA => nclk.clk, + CLKB => nclk.clk, + DIA => ramb_data_in(80 to 87), + DIB => ramb_data_in(208 to 215), + DIPA => ramb_parity_in(10 to 10), + DIPB => ramb_parity_in(26 to 26), + ENA => act, + ENB => act, + SSRA => nclk.sreset, + SSRB => nclk.sreset, + WEA => wrt_en_wAH(10), + WEB => wrt_en_wAH(26) + ); + + arrB: RAMB16_S9_S9 + -- pragma translate_off + generic map( + sim_collision_check => "none") + -- pragma translate_on + port map( + DOA => ramb_data_out(88 to 95), + DOB => ramb_data_out(216 to 223), + DOPA => ramb_parity_out(11 to 11), + DOPB => ramb_parity_out(27 to 27), + ADDRA => tconv(ramb_uh_addr), + ADDRB => tconv(ramb_lh_addr), + CLKA => nclk.clk, + CLKB => nclk.clk, + DIA => ramb_data_in(88 to 95), + DIB => ramb_data_in(216 to 223), + DIPA => ramb_parity_in(11 to 11), + DIPB => ramb_parity_in(27 to 27), + ENA => act, + ENB => act, + SSRA => nclk.sreset, + SSRB => nclk.sreset, + WEA => wrt_en_wAH(11), + WEB => wrt_en_wAH(27) + ); + + arrC: RAMB16_S9_S9 + -- pragma translate_off + generic map( + sim_collision_check => "none") + -- pragma translate_on + port map( + DOA => ramb_data_out(96 to 103), + DOB => ramb_data_out(224 to 231), + DOPA => ramb_parity_out(12 to 12), + DOPB => ramb_parity_out(28 to 28), + ADDRA => tconv(ramb_uh_addr), + ADDRB => tconv(ramb_lh_addr), + CLKA => nclk.clk, + CLKB => nclk.clk, + DIA => ramb_data_in(96 to 103), + DIB => ramb_data_in(224 to 231), + DIPA => ramb_parity_in(12 to 12), + DIPB => ramb_parity_in(28 to 28), + ENA => act, + ENB => act, + SSRA => nclk.sreset, + SSRB => nclk.sreset, + WEA => wrt_en_wAH(12), + WEB => wrt_en_wAH(28) + ); + + arrD: RAMB16_S9_S9 + -- pragma translate_off + generic map( + sim_collision_check => "none") + -- pragma translate_on + port map( + DOA => ramb_data_out(104 to 111), + DOB => ramb_data_out(232 to 239), + DOPA => ramb_parity_out(13 to 13), + DOPB => ramb_parity_out(29 to 29), + ADDRA => tconv(ramb_uh_addr), + ADDRB => tconv(ramb_lh_addr), + CLKA => nclk.clk, + CLKB => nclk.clk, + DIA => ramb_data_in(104 to 111), + DIB => ramb_data_in(232 to 239), + DIPA => ramb_parity_in(13 to 13), + DIPB => ramb_parity_in(29 to 29), + ENA => act, + ENB => act, + SSRA => nclk.sreset, + SSRB => nclk.sreset, + WEA => wrt_en_wAH(13), + WEB => wrt_en_wAH(29) + ); + + arrE: RAMB16_S9_S9 + -- pragma translate_off + generic map( + sim_collision_check => "none") + -- pragma translate_on + port map( + DOA => ramb_data_out(112 to 119), + DOB => ramb_data_out(240 to 247), + DOPA => ramb_parity_out(14 to 14), + DOPB => ramb_parity_out(30 to 30), + ADDRA => tconv(ramb_uh_addr), + ADDRB => tconv(ramb_lh_addr), + CLKA => nclk.clk, + CLKB => nclk.clk, + DIA => ramb_data_in(112 to 119), + DIB => ramb_data_in(240 to 247), + DIPA => ramb_parity_in(14 to 14), + DIPB => ramb_parity_in(30 to 30), + ENA => act, + ENB => act, + SSRA => nclk.sreset, + SSRB => nclk.sreset, + WEA => wrt_en_wAH(14), + WEB => wrt_en_wAH(30) + ); + + arrF: RAMB16_S9_S9 + -- pragma translate_off + generic map( + sim_collision_check => "none") + -- pragma translate_on + port map( + DOA => ramb_data_out(120 to 127), + DOB => ramb_data_out(248 to 255), + DOPA => ramb_parity_out(15 to 15), + DOPB => ramb_parity_out(31 to 31), + ADDRA => tconv(ramb_uh_addr), + ADDRB => tconv(ramb_lh_addr), + CLKA => nclk.clk, + CLKB => nclk.clk, + DIA => ramb_data_in(120 to 127), + DIB => ramb_data_in(248 to 255), + DIPA => ramb_parity_in(15 to 15), + DIPB => ramb_parity_in(31 to 31), + ENA => act, + ENB => act, + SSRA => nclk.sreset, + SSRB => nclk.sreset, + WEA => wrt_en_wAH(15), + WEB => wrt_en_wAH(31) + ); + + abst_scan_out <= (others=>'0'); + time_scan_out <= tidn; + repr_scan_out <= tidn; + + bo_pc_failout <= (others=>'0'); + bo_pc_diagloop <= (others=>'0'); + + unused <= or_reduce( bw(32 to port_bitwidth-1) + & clkoff_dc_b & ccflush_dc & scan_dis_dc_b & scan_diag_dc & d_mode_dc & act_dis_dc + & bitw_abist & sg_0 & sg_1 + & abst_sl_thold_0 & repr_sl_thold_0 + & time_sl_thold_0 & ary_nsl_thold_0 & tc_lbist_ary_wrt_thru_dc + & abist_en_1 & din_abist & abist_cmp_en & abist_raw_b_dc & data_cmp_abist + & addr_abist & r_wb_abist & abst_scan_in & time_scan_in & repr_scan_in + & lcb_delay_lclkr_np_dc & ctrl_lcb_delay_lclkr_np_dc & dibw_lcb_delay_lclkr_np_dc + & ctrl_lcb_mpw1_np_dc_b & dibw_lcb_mpw1_np_dc_b & lcb_mpw1_pp_dc_b & lcb_mpw1_2_pp_dc_b + & aodo_lcb_delay_lclkr_dc & aodo_lcb_mpw1_dc_b & aodo_lcb_mpw2_dc_b + & lcb_bolt_sl_thold_0 & pc_bo_enable_2 & pc_bo_reset + & pc_bo_unload & pc_bo_repair & pc_bo_shdata & pc_bo_select + & tri_lcb_mpw1_dc_b & tri_lcb_mpw2_dc_b & tri_lcb_delay_lclkr_dc + & tri_lcb_clkoff_dc_b & tri_lcb_act_dis_dc ); + + end generate a; + + +end tri_512x288_9; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_64x36_4w_1r1w.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_64x36_4w_1r1w.vhdl new file mode 100644 index 0000000..21d131a --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_64x36_4w_1r1w.vhdl @@ -0,0 +1,357 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; use ieee.std_logic_1164.all ; +library ibm; use ibm.std_ulogic_support.all ; + use ibm.std_ulogic_function_support.all; +library support; + use support.power_logic_pkg.all; +library tri; use tri.tri_latches_pkg.all; +-- pragma translate_off +-- pragma translate_on + +entity tri_64x36_4w_1r1w is + generic (addressable_ports : positive := 64; + addressbus_width : positive := 6; + port_bitwidth : positive := 36; + ways : positive := 4; + expand_type : integer := 1); + port ( + gnd : inout power_logic; + vdd : inout power_logic; + vcs : inout power_logic; + nclk : in clk_logic; + rd_act : in std_ulogic; + wr_act : in std_ulogic; + sg_0 : in std_ulogic; + abst_sl_thold_0 : in std_ulogic; + ary_nsl_thold_0 : in std_ulogic; + time_sl_thold_0 : in std_ulogic; + repr_sl_thold_0 : in std_ulogic; + clkoff_dc_b : in std_ulogic; + ccflush_dc : in std_ulogic; + scan_dis_dc_b : in std_ulogic; + scan_diag_dc : in std_ulogic; + d_mode_dc : in std_ulogic; + mpw1_dc_b : in std_ulogic_vector(0 to 4); + mpw2_dc_b : in std_ulogic; + delay_lclkr_dc : in std_ulogic_vector(0 to 4); + wr_abst_act : in std_ulogic; + rd0_abst_act : in std_ulogic; + abist_di : in std_ulogic_vector(0 to 3); + abist_bw_odd : in std_ulogic; + abist_bw_even : in std_ulogic; + abist_wr_adr : in std_ulogic_vector(0 to 5); + abist_rd0_adr : in std_ulogic_vector(0 to 5); + tc_lbist_ary_wrt_thru_dc : in std_ulogic; + abist_ena_1 : in std_ulogic; + abist_g8t_rd0_comp_ena : in std_ulogic; + abist_raw_dc_b : in std_ulogic; + obs0_abist_cmp : in std_ulogic_vector(0 to 3); + abst_scan_in : in std_ulogic_vector(0 to 1); + time_scan_in : in std_ulogic; + repr_scan_in : in std_ulogic; + abst_scan_out : out std_ulogic_vector(0 to 1); + time_scan_out : out std_ulogic; + repr_scan_out : out std_ulogic; + lcb_bolt_sl_thold_0 : in std_ulogic; + pc_bo_enable_2 : in std_ulogic; + pc_bo_reset : in std_ulogic; + pc_bo_unload : in std_ulogic; + pc_bo_repair : in std_ulogic; + pc_bo_shdata : in std_ulogic; + pc_bo_select : in std_ulogic_vector(0 to 1); + bo_pc_failout : out std_ulogic_vector(0 to 1); + bo_pc_diagloop : out std_ulogic_vector(0 to 1); + tri_lcb_mpw1_dc_b : in std_ulogic; + tri_lcb_mpw2_dc_b : in std_ulogic; + tri_lcb_delay_lclkr_dc : in std_ulogic; + tri_lcb_clkoff_dc_b : in std_ulogic; + tri_lcb_act_dis_dc : in std_ulogic; + wr_way : in std_ulogic_vector (0 to (ways-1)); + wr_addr : in std_ulogic_vector (0 to (addressbus_width-1)); + data_in : in std_ulogic_vector (0 to (port_bitwidth*ways-1)); + rd_addr : in std_ulogic_vector(0 to (addressbus_width-1)); + data_out : out std_ulogic_vector(0 to (port_bitwidth*ways-1)) +); + + -- synopsys translate_off + + -- synopsys translate_on + +end entity tri_64x36_4w_1r1w; + +architecture tri_64x36_4w_1r1w of tri_64x36_4w_1r1w is + +constant wga_base_width : integer := 72; +constant wga_width_mult : integer := (port_bitwidth*ways-1)/wga_base_width + 1; +constant ramb_base_width : integer := 36; +constant ramb_base_addr : integer := 9; +constant ramb_width_mult : integer := (port_bitwidth-1)/ramb_base_width + 1; + + +type RAMB_DATA_ARRAY is array (natural range <>) of std_logic_vector(0 to (ramb_base_width*ramb_width_mult - 1)); + + +begin + + -- synopsys translate_off + um: if expand_type = 0 generate + signal tiup : std_ulogic; + signal tidn : std_ulogic; + + signal wr_addr_l2 : std_ulogic_vector (0 TO addressbus_width-1); + signal rd_addr_l2 : std_ulogic_vector (0 TO addressbus_width-1); + signal way_l2 : std_ulogic_vector (0 TO wr_way'right); + signal write_enable_l2 : std_ulogic; + signal data_in_l2 : std_ulogic_vector(0 to port_bitwidth*ways-1); + signal array_d : std_ulogic_vector(0 to addressable_ports*port_bitwidth*ways-1); + signal array_l2 : std_ulogic_vector(0 to addressable_ports*port_bitwidth*ways-1); + begin + tiup <= '1'; + tidn <= '0'; + + wr_addr_latch: tri_rlmreg_p + generic map (width => wr_addr'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => wr_act, + scin => (others => '0'), + scout => open, + din => wr_addr, + dout => wr_addr_l2 ); + + rd_addr_latch: tri_rlmreg_p + generic map (width => rd_addr'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rd_act, + scin => (others => '0'), + scout => open, + din => rd_addr, + dout => rd_addr_l2 ); + + way_latch: tri_rlmreg_p + generic map (width => wr_way'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => wr_act, + scin => (others => '0'), + scout => open, + din => wr_way, + dout => way_l2 ); + + write_enable_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + scin => tidn, + scout => open, + din => wr_act, + dout => write_enable_l2 ); + + data_in_latch: tri_rlmreg_p + generic map (width => port_bitwidth*ways, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => wr_act, + scin => (others => '0'), + scout => open, + din => data_in, + dout => data_in_l2 ); + + array_latch: tri_rlmreg_p + generic map (width => addressable_ports*port_bitwidth*ways, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + scin => (others => '0'), + scout => open, + din => array_d, + dout => array_l2 ); + + ww: for w in 0 to ways-1 generate + begin + wy: for y in 0 to addressable_ports-1 generate + begin + wx: for x in 0 to port_bitwidth-1 generate + begin + array_d(y*port_bitwidth*ways+w*port_bitwidth+x) <= + data_in_l2(w*port_bitwidth+x) when (( write_enable_l2 and wr_addr_l2 = tconv(y, addressbus_width) and + way_l2(w)) = '1') + else array_l2(y*port_bitwidth*ways+w*port_bitwidth+x); + + end generate wx; + end generate wy; + end generate ww; + + data_out <= array_l2( tconv(rd_addr_l2)*port_bitwidth*ways to tconv(rd_addr_l2)*port_bitwidth*ways+port_bitwidth*ways-1 ); + + abst_scan_out <= tidn & tidn; + time_scan_out <= tidn; + repr_scan_out <= tidn; + + bo_pc_failout <= tidn & tidn; + bo_pc_diagloop <= tidn & tidn; + end generate um; + -- synopsys translate_on + + + a: if expand_type = 1 generate + component RAMB16_S36_S36 + -- pragma translate_off + generic + ( + SIM_COLLISION_CHECK : string := "none"); + -- pragma translate_on + port + ( + DOA : out std_logic_vector(31 downto 0); + DOB : out std_logic_vector(31 downto 0); + DOPA : out std_logic_vector(3 downto 0); + DOPB : out std_logic_vector(3 downto 0); + ADDRA : in std_logic_vector(8 downto 0); + ADDRB : in std_logic_vector(8 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(31 downto 0); + DIB : in std_logic_vector(31 downto 0); + DIPA : in std_logic_vector(3 downto 0); + DIPB : in std_logic_vector(3 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); + end component; + + -- pragma translate_off + -- pragma translate_on + + signal ramb_data_in : RAMB_DATA_ARRAY(wr_way'range); + signal ramb_data_out : RAMB_DATA_ARRAY(wr_way'range); + signal ramb_rd_addr : std_logic_vector(0 to ramb_base_addr - 1); + signal ramb_wr_addr : std_logic_vector(0 to ramb_base_addr - 1); + + signal tidn : std_ulogic; + signal unused : std_ulogic; + -- synopsys translate_off + -- synopsys translate_on + begin + + tidn <= '0'; + + add0: if (addressbus_width < ramb_base_addr) generate + begin + ramb_rd_addr(0 to (ramb_base_addr-addressbus_width-1)) <= (others => '0'); + ramb_rd_addr(ramb_base_addr-addressbus_width to ramb_base_addr-1) <= tconv( rd_addr ); + + ramb_wr_addr(0 to (ramb_base_addr-addressbus_width-1)) <= (others => '0'); + ramb_wr_addr(ramb_base_addr-addressbus_width to ramb_base_addr-1) <= tconv( wr_addr ); + end generate; + add1: if (addressbus_width >= ramb_base_addr) generate + begin + ramb_rd_addr <= tconv( rd_addr(addressbus_width-ramb_base_addr to addressbus_width-1) ); + ramb_wr_addr <= tconv( wr_addr(addressbus_width-ramb_base_addr to addressbus_width-1) ); + end generate; + + dw: for w in wr_way'range generate begin + din: for i in 0 to (ramb_base_width*ramb_width_mult - 1) generate + begin + R0: if(i < port_bitwidth) generate begin ramb_data_in(w)(i) <= data_in(w*port_bitwidth+i); end generate; + R1: if(i >= port_bitwidth) generate begin ramb_data_in(w)(i) <= '0'; end generate; + end generate din; + end generate dw; + + aw: for w in wr_way'range generate begin + ax: for x in 0 to (ramb_width_mult - 1) generate begin + arr: RAMB16_S36_S36 + -- pragma translate_off + generic map( + sim_collision_check => "none") + -- pragma translate_on + port map( + DOA => ramb_data_out(w)(x*ramb_base_width to x*ramb_base_width+31), + DOB => open, + DOPA => ramb_data_out(w)(x*ramb_base_width+32 to x*ramb_base_width+35), + DOPB => open, + ADDRA => ramb_rd_addr, + ADDRB => ramb_wr_addr, + CLKA => nclk.clk, + CLKB => nclk.clk, + DIA => ramb_data_in(w)(x*ramb_base_width to x*ramb_base_width+31), + DIB => ramb_data_in(w)(x*ramb_base_width to x*ramb_base_width+31), + DIPA => ramb_data_in(w)(x*ramb_base_width+32 to x*ramb_base_width+35), + DIPB => ramb_data_in(w)(x*ramb_base_width+32 to x*ramb_base_width+35), + ENA => rd_act, + ENB => wr_act, + SSRA => nclk.sreset, + SSRB => nclk.sreset, + WEA => tidn, + WEB => wr_way(w) + ); + + end generate ax; + + data_out(w*port_bitwidth to ((w+1)*port_bitwidth)-1 ) <= tconv( ramb_data_out(w)(0 to port_bitwidth-1) ); + + end generate aw; + + abst_scan_out <= tidn & tidn; + time_scan_out <= tidn; + repr_scan_out <= tidn; + + bo_pc_failout <= tidn & tidn; + bo_pc_diagloop <= tidn & tidn; + + unused <= or_reduce( sg_0 & abst_sl_thold_0 & ary_nsl_thold_0 + & time_sl_thold_0 & repr_sl_thold_0 & clkoff_dc_b & ccflush_dc + & scan_dis_dc_b & scan_diag_dc & d_mode_dc & mpw1_dc_b & mpw2_dc_b + & delay_lclkr_dc & wr_abst_act & rd0_abst_act & abist_di + & abist_bw_odd & abist_bw_even & abist_wr_adr & abist_rd0_adr + & tc_lbist_ary_wrt_thru_dc & abist_ena_1 & abist_g8t_rd0_comp_ena + & abist_raw_dc_b & obs0_abist_cmp & abst_scan_in & time_scan_in + & repr_scan_in & lcb_bolt_sl_thold_0 & pc_bo_enable_2 & pc_bo_reset + & pc_bo_unload & pc_bo_repair & pc_bo_shdata & pc_bo_select + & tri_lcb_mpw1_dc_b & tri_lcb_mpw2_dc_b & tri_lcb_delay_lclkr_dc + & tri_lcb_clkoff_dc_b & tri_lcb_act_dis_dc ); + end generate a; + + +end tri_64x36_4w_1r1w; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_64x42_4w_1r1w.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_64x42_4w_1r1w.vhdl new file mode 100644 index 0000000..abb70ca --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_64x42_4w_1r1w.vhdl @@ -0,0 +1,381 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee,ibm,support,tri; +use ieee.std_logic_1164.all; +use ibm.std_ulogic_function_support.all; +use support.power_logic_pkg.all; +use tri.tri_latches_pkg.all; +-- pragma translate_off +-- pragma translate_on + +entity tri_64x42_4w_1r1w is +generic( + expand_type : integer := 1); +port ( + vdd : INOUT power_logic; + vcs : INOUT power_logic; + gnd : INOUT power_logic; + + nclk : in clk_logic; + sg_0 : in std_ulogic; + abst_sl_thold_0 : in std_ulogic; + ary_nsl_thold_0 : in std_ulogic; + time_sl_thold_0 : in std_ulogic; + repr_sl_thold_0 : in std_ulogic; + + rd0_act : in std_ulogic; + rd0_adr : in std_ulogic_vector(0 to 5); + do0 : out std_ulogic_vector(0 to 167); + + wr_way : in std_ulogic_vector (0 to 3); + wr_act : in std_ulogic; + wr_adr : in std_ulogic_vector(0 to 5); + di : in std_ulogic_vector(0 to 167); + + abst_scan_in : in std_ulogic; + abst_scan_out : out std_ulogic; + time_scan_in : in std_ulogic; + time_scan_out : out std_ulogic; + repr_scan_in : in std_ulogic; + repr_scan_out : out std_ulogic; + + scan_dis_dc_b : in std_ulogic; + scan_diag_dc : in std_ulogic; + ccflush_dc : in std_ulogic; + ary0_clkoff_dc_b : in std_ulogic; + ary0_d_mode_dc : in std_ulogic; + ary0_mpw1_dc_b : in std_ulogic_vector(0 to 4); + ary0_mpw2_dc_b : in std_ulogic; + ary0_delay_lclkr_dc : in std_ulogic_vector(0 to 4); + ary1_clkoff_dc_b : in std_ulogic; + ary1_d_mode_dc : in std_ulogic; + ary1_mpw1_dc_b : in std_ulogic_vector(0 to 4); + ary1_mpw2_dc_b : in std_ulogic; + ary1_delay_lclkr_dc : in std_ulogic_vector(0 to 4); + + lcb_bolt_sl_thold_0 : in std_ulogic; + pc_bo_enable_2 : in std_ulogic; + pc_bo_reset : in std_ulogic; + pc_bo_unload : in std_ulogic; + pc_bo_repair : in std_ulogic; + pc_bo_shdata : in std_ulogic; + pc_bo_select : in std_ulogic_vector(0 to 1); + bo_pc_failout : out std_ulogic_vector(0 to 1); + bo_pc_diagloop : out std_ulogic_vector(0 to 1); + tri_lcb_mpw1_dc_b : in std_ulogic; + tri_lcb_mpw2_dc_b : in std_ulogic; + tri_lcb_delay_lclkr_dc : in std_ulogic; + tri_lcb_clkoff_dc_b : in std_ulogic; + tri_lcb_act_dis_dc : in std_ulogic; + + abist_di : in std_ulogic_vector(0 to 3); + abist_bw_odd : in std_ulogic; + abist_bw_even : in std_ulogic; + abist_wr_adr : in std_ulogic_vector(0 to 5); + wr_abst_act : in std_ulogic; + abist_rd0_adr : in std_ulogic_vector(0 to 5); + rd0_abst_act : in std_ulogic; + tc_lbist_ary_wrt_thru_dc : in std_ulogic; + abist_ena_1 : in std_ulogic; + abist_g8t_rd0_comp_ena : in std_ulogic; + abist_raw_dc_b : in std_ulogic; + obs0_abist_cmp : in std_ulogic_vector(0 to 3) + ); + +-- synopsys translate_off +-- synopsys translate_on + + +end entity tri_64x42_4w_1r1w; +architecture tri_64x42_4w_1r1w of tri_64x42_4w_1r1w is + +begin + +a : if expand_type = 1 generate + +component RAMB16_S36_S36 +-- pragma translate_off +generic( + SIM_COLLISION_CHECK : string := "none"); +-- pragma translate_on +port( + DOA : out std_logic_vector(31 downto 0); + DOB : out std_logic_vector(31 downto 0); + DOPA : out std_logic_vector(3 downto 0); + DOPB : out std_logic_vector(3 downto 0); + ADDRA : in std_logic_vector(8 downto 0); + ADDRB : in std_logic_vector(8 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(31 downto 0); + DIB : in std_logic_vector(31 downto 0); + DIPA : in std_logic_vector(3 downto 0); + DIPB : in std_logic_vector(3 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic); +end component; + +-- pragma translate_off +-- pragma translate_on + +signal clk, clk2x : std_ulogic; +signal addra, addrb : std_ulogic_vector(0 to 8); +signal wea0, wea1, wea2, wea3 : std_ulogic; +signal web0, web1, web2, web3 : std_ulogic; +signal bdo0, bdo1, bdo2, bdo3 : std_logic_vector(0 to 71); +signal bdi0, bdi1, bdi2, bdi3 : std_ulogic_vector(0 to 71); +signal sreset : std_ulogic; +signal tidn : std_ulogic_vector(36 to 65); +signal reset_q : std_ulogic; +signal gate_fq, gate_d : std_ulogic; +signal bdo_d, bdo_fq : std_ulogic_vector(0 to 167); + +signal toggle_d : std_ulogic; +signal toggle_q : std_ulogic; +signal toggle2x_d : std_ulogic; +signal toggle2x_q : std_ulogic; + +signal unused : std_ulogic; +-- synopsys translate_off +-- synopsys translate_on + +begin + +tidn <= (others=>'0'); +clk <= nclk.clk; +clk2x <= nclk.clk2x; +sreset<= nclk.sreset; + +rlatch: process (clk) begin + if(rising_edge(clk)) then + reset_q <= sreset after 10 ps; + end if; +end process; + + +tlatch: process (nclk.clk,reset_q) +begin + if(rising_edge(nclk.clk)) then + if (reset_q = '1') then + toggle_q <= '1'; + else + toggle_q <= toggle_d; + end if; + end if; +end process; + +flatch: process (nclk.clk2x) +begin + if(rising_edge(nclk.clk2x)) then + toggle2x_q <= toggle2x_d; + gate_fq <= gate_d; + bdo_fq <= bdo_d; + end if; +end process; + +toggle_d <= not toggle_q; +toggle2x_d <= toggle_q; + +gate_d <= not(toggle_q xor toggle2x_q); + + + + + + + + bdi0 <= di(0 to 35) & tidn(36 to 65) & di(36 to 41); + bdi1 <= di(42 to 77) & tidn(36 to 65) & di(78 to 83); + bdi2 <= di(84 to 119) & tidn(36 to 65) & di(120 to 125); + bdi3 <= di(126 to 161) & tidn(36 to 65) & di(162 to 167); + +bdo_d(0 to 41) <= std_ulogic_vector(bdo0(0 to 35) & bdo0(66 to 71)); +bdo_d(42 to 83) <= std_ulogic_vector(bdo1(0 to 35) & bdo1(66 to 71)); +bdo_d(84 to 125) <= std_ulogic_vector(bdo2(0 to 35) & bdo2(66 to 71)); +bdo_d(126 to 167) <= std_ulogic_vector(bdo3(0 to 35) & bdo3(66 to 71)); + +do0 <= bdo_fq; + +wea0 <= (wr_act and gate_fq and wr_way(0)) after 10 ps; +web0 <= (wr_act and gate_fq and wr_way(0)) after 10 ps; +wea1 <= (wr_act and gate_fq and wr_way(1)) after 10 ps; +web1 <= (wr_act and gate_fq and wr_way(1)) after 10 ps; +wea2 <= (wr_act and gate_fq and wr_way(2)) after 10 ps; +web2 <= (wr_act and gate_fq and wr_way(2)) after 10 ps; +wea3 <= (wr_act and gate_fq and wr_way(3)) after 10 ps; +web3 <= (wr_act and gate_fq and wr_way(3)) after 10 ps; + +with gate_fq select + addra <= ("00" & wr_adr & '0') after 10 ps when '1', + ("00" & rd0_adr & '0') after 10 ps when others; + +with gate_fq select + addrb <= ("00" & wr_adr & '1') after 10 ps when '1', + ("00" & rd0_adr & '1') after 10 ps when others; + +bram0a : ramb16_s36_s36 +-- pragma translate_off +generic map( + sim_collision_check => "none") +-- pragma translate_on +port map( + clka => clk2x, + clkb => clk2x, + ssra => sreset, + ssrb => sreset, + addra => std_logic_vector(addra), + addrb => std_logic_vector(addrb), + dia => std_logic_vector(bdi0(00 to 31)), + dipa => std_logic_vector(bdi0(32 to 35)), + dib => std_logic_vector(bdi0(36 to 67)), + dipb => std_logic_vector(bdi0(68 to 71)), + doa => bdo0(00 to 31), + dopa => bdo0(32 to 35), + dob => bdo0(36 to 67), + dopb => bdo0(68 to 71), + ena => '1', + enb => '1', + wea => wea0, + web => web0 + ); + +bram0b : ramb16_s36_s36 +-- pragma translate_off +generic map( + sim_collision_check => "none") +-- pragma translate_on +port map( + clka => clk2x, + clkb => clk2x, + ssra => sreset, + ssrb => sreset, + addra => std_logic_vector(addra), + addrb => std_logic_vector(addrb), + dia => std_logic_vector(bdi1(00 to 31)), + dipa => std_logic_vector(bdi1(32 to 35)), + dib => std_logic_vector(bdi1(36 to 67)), + dipb => std_logic_vector(bdi1(68 to 71)), + doa => bdo1(00 to 31), + dopa => bdo1(32 to 35), + dob => bdo1(36 to 67), + dopb => bdo1(68 to 71), + ena => '1', + enb => '1', + wea => wea1, + web => web1 + ); + +bram0c : ramb16_s36_s36 +-- pragma translate_off +generic map( + sim_collision_check => "none") +-- pragma translate_on +port map( + clka => clk2x, + clkb => clk2x, + ssra => sreset, + ssrb => sreset, + addra => std_logic_vector(addra), + addrb => std_logic_vector(addrb), + dia => std_logic_vector(bdi2(00 to 31)), + dipa => std_logic_vector(bdi2(32 to 35)), + dib => std_logic_vector(bdi2(36 to 67)), + dipb => std_logic_vector(bdi2(68 to 71)), + doa => bdo2(00 to 31), + dopa => bdo2(32 to 35), + dob => bdo2(36 to 67), + dopb => bdo2(68 to 71), + ena => '1', + enb => '1', + wea => wea2, + web => web2 + ); + + +bram0d : ramb16_s36_s36 +-- pragma translate_off +generic map( + sim_collision_check => "none") +-- pragma translate_on +port map( + clka => clk2x, + clkb => clk2x, + ssra => sreset, + ssrb => sreset, + addra => std_logic_vector(addra), + addrb => std_logic_vector(addrb), + dia => std_logic_vector(bdi3(00 to 31)), + dipa => std_logic_vector(bdi3(32 to 35)), + dib => std_logic_vector(bdi3(36 to 67)), + dipb => std_logic_vector(bdi3(68 to 71)), + doa => bdo3(00 to 31), + dopa => bdo3(32 to 35), + dob => bdo3(36 to 67), + dopb => bdo3(68 to 71), + ena => '1', + enb => '1', + wea => wea3, + web => web3 + ); + + +abst_scan_out <= abst_scan_in; +time_scan_out <= time_scan_in; +repr_scan_out <= repr_scan_in; + +bo_pc_failout <= "00"; +bo_pc_diagloop <= "00"; + +unused <= or_reduce( sg_0 & abst_sl_thold_0 & ary_nsl_thold_0 & time_sl_thold_0 & repr_sl_thold_0 + & ary0_clkoff_dc_b & ary0_d_mode_dc & ary0_mpw1_dc_b & ary0_mpw2_dc_b + & ary0_delay_lclkr_dc & ccflush_dc & scan_dis_dc_b & scan_diag_dc + & ary1_clkoff_dc_b & ary1_d_mode_dc & ary1_mpw1_dc_b & ary1_mpw2_dc_b + & ary1_delay_lclkr_dc & abist_di + & abist_bw_odd & abist_bw_even & abist_wr_adr & abist_rd0_adr + & wr_abst_act & rd0_abst_act + & tc_lbist_ary_wrt_thru_dc & abist_ena_1 & abist_g8t_rd0_comp_ena + & abist_raw_dc_b & obs0_abist_cmp & rd0_act + & std_ulogic_vector( bdo0(36 to 65) ) & std_ulogic_vector( bdo1(36 to 65) ) + & std_ulogic_vector( bdo2(36 to 65) ) & std_ulogic_vector( bdo3(36 to 65) ) + & lcb_bolt_sl_thold_0 & pc_bo_enable_2 & pc_bo_reset + & pc_bo_unload & pc_bo_repair & pc_bo_shdata & pc_bo_select + & tri_lcb_mpw1_dc_b & tri_lcb_mpw2_dc_b & tri_lcb_delay_lclkr_dc + & tri_lcb_clkoff_dc_b & tri_lcb_act_dis_dc ); + +end generate; + +end architecture tri_64x42_4w_1r1w; + + + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_64x72_1r1w.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_64x72_1r1w.vhdl new file mode 100644 index 0000000..40b8d04 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_64x72_1r1w.vhdl @@ -0,0 +1,285 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee,ibm,support,tri; +use ieee.std_logic_1164.all; +use ibm.std_ulogic_function_support.all; +use support.power_logic_pkg.all; +use tri.tri_latches_pkg.all; +-- pragma translate_off +-- pragma translate_on + +entity tri_64x72_1r1w is +generic( + expand_type : integer := 1; + regsize : integer := 64); +port ( + vdd : INOUT power_logic; + vcs : INOUT power_logic; + gnd : INOUT power_logic; + + nclk : in clk_logic; + sg_0 : in std_ulogic; + abst_sl_thold_0 : in std_ulogic; + ary_nsl_thold_0 : in std_ulogic; + time_sl_thold_0 : in std_ulogic; + repr_sl_thold_0 : in std_ulogic; + + rd0_act : in std_ulogic; + rd0_adr : in std_ulogic_vector(0 to 5); + do0 : out std_ulogic_vector(64-regsize to 72-(64/regsize)); + + wr_act : in std_ulogic; + wr_adr : in std_ulogic_vector(0 to 5); + di : in std_ulogic_vector(64-regsize to 72-(64/regsize)); + + abst_scan_in : in std_ulogic; + abst_scan_out : out std_ulogic; + time_scan_in : in std_ulogic; + time_scan_out : out std_ulogic; + repr_scan_in : in std_ulogic; + repr_scan_out : out std_ulogic; + + scan_dis_dc_b : in std_ulogic; + scan_diag_dc : in std_ulogic; + ccflush_dc : in std_ulogic; + clkoff_dc_b : in std_ulogic; + d_mode_dc : in std_ulogic; + mpw1_dc_b : in std_ulogic_vector(0 to 4); + mpw2_dc_b : in std_ulogic; + delay_lclkr_dc : in std_ulogic_vector(0 to 4); + + lcb_bolt_sl_thold_0 : in std_ulogic; + pc_bo_enable_2 : in std_ulogic; + pc_bo_reset : in std_ulogic; + pc_bo_unload : in std_ulogic; + pc_bo_repair : in std_ulogic; + pc_bo_shdata : in std_ulogic; + pc_bo_select : in std_ulogic; + bo_pc_failout : out std_ulogic; + bo_pc_diagloop : out std_ulogic; + tri_lcb_mpw1_dc_b : in std_ulogic; + tri_lcb_mpw2_dc_b : in std_ulogic; + tri_lcb_delay_lclkr_dc : in std_ulogic; + tri_lcb_clkoff_dc_b : in std_ulogic; + tri_lcb_act_dis_dc : in std_ulogic; + + abist_di : in std_ulogic_vector(0 to 3); + abist_bw_odd : in std_ulogic; + abist_bw_even : in std_ulogic; + abist_wr_adr : in std_ulogic_vector(0 to 5); + wr_abst_act : in std_ulogic; + abist_rd0_adr : in std_ulogic_vector(0 to 5); + rd0_abst_act : in std_ulogic; + tc_lbist_ary_wrt_thru_dc : in std_ulogic; + abist_ena_1 : in std_ulogic; + abist_g8t_rd0_comp_ena : in std_ulogic; + abist_raw_dc_b : in std_ulogic; + obs0_abist_cmp : in std_ulogic_vector(0 to 3) + ); + +-- synopsys translate_off +-- synopsys translate_on + + +end entity tri_64x72_1r1w; +architecture tri_64x72_1r1w of tri_64x72_1r1w is + +begin + +a : if expand_type = 1 generate + +component RAMB16_S36_S36 +-- pragma translate_off +generic( + SIM_COLLISION_CHECK : string := "none"); +-- pragma translate_on +port( + DOA : out std_logic_vector(31 downto 0); + DOB : out std_logic_vector(31 downto 0); + DOPA : out std_logic_vector(3 downto 0); + DOPB : out std_logic_vector(3 downto 0); + ADDRA : in std_logic_vector(8 downto 0); + ADDRB : in std_logic_vector(8 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(31 downto 0); + DIB : in std_logic_vector(31 downto 0); + DIPA : in std_logic_vector(3 downto 0); + DIPB : in std_logic_vector(3 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic); +end component; + +-- pragma translate_off +-- pragma translate_on + +signal clk, clk2x : std_ulogic; +signal addra, addrb : std_ulogic_vector(0 to 8); +signal wea, web : std_ulogic; +signal bdo : std_logic_vector(0 to 71); +signal bdi : std_ulogic_vector(0 to 71); +signal sreset : std_ulogic; +signal tidn : std_ulogic_vector(0 to 71); +signal reset_q : std_ulogic; +signal gate_fq, gate_d : std_ulogic; +signal bdo_d, bdo_fq : std_ulogic_vector(64-regsize to 72-(64/regsize)); + +signal toggle_d : std_ulogic; +signal toggle_q : std_ulogic; +signal toggle2x_d : std_ulogic; +signal toggle2x_q : std_ulogic; + +signal unused : std_ulogic; +-- synopsys translate_off +-- synopsys translate_on + +begin + +tidn <= (others=>'0'); +clk <= nclk.clk; +clk2x <= nclk.clk2x; +sreset<= nclk.sreset; + +rlatch: process (clk) begin + if(rising_edge(clk)) then + reset_q <= sreset after 10 ps; + end if; +end process; + + +tlatch: process (nclk.clk,reset_q) +begin + if(rising_edge(nclk.clk)) then + if (reset_q = '1') then + toggle_q <= '1'; + else + toggle_q <= toggle_d; + end if; + end if; +end process; + +flatch: process (nclk.clk2x) +begin + if(rising_edge(nclk.clk2x)) then + toggle2x_q <= toggle2x_d; + gate_fq <= gate_d; + bdo_fq <= bdo_d; + end if; +end process; + +toggle_d <= not toggle_q; +toggle2x_d <= toggle_q; + +gate_d <= not(toggle_q xor toggle2x_q); + + + + + + +in32 : if regsize = 32 generate + bdi <= tidn(0 to 31) & di(32 to 63) & di(64 to 70) & tidn(71); +end generate; +in64 : if regsize = 64 generate + bdi <= di(0 to 71); +end generate; + +bdo_d <= std_ulogic_vector(bdo(64-regsize to 72-(64/regsize))); +do0 <= bdo_fq; + +wea <= (wr_act and gate_fq) after 10 ps; +web <= (wr_act and gate_fq) after 10 ps; + +with gate_fq select + addra <= ("00" & wr_adr & '0') after 10 ps when '1', + ("00" & rd0_adr & '0') after 10 ps when others; + +with gate_fq select + addrb <= ("00" & wr_adr & '1') after 10 ps when '1', + ("00" & rd0_adr & '1') after 10 ps when others; + +bram0a : ramb16_s36_s36 +-- pragma translate_off +generic map( + sim_collision_check => "none") +-- pragma translate_on +port map( + clka => clk2x, + clkb => clk2x, + ssra => sreset, + ssrb => sreset, + addra => std_logic_vector(addra), + addrb => std_logic_vector(addrb), + dia => std_logic_vector(bdi(00 to 31)), + dib => std_logic_vector(bdi(32 to 63)), + dipa => std_logic_vector(bdi(64 to 67)), + dipb => std_logic_vector(bdi(68 to 71)), + doa => bdo(00 to 31), + dob => bdo(32 to 63), + dopa => bdo(64 to 67), + dopb => bdo(68 to 71), + ena => '1', + enb => '1', + wea => wea, + web => web + ); + + +abst_scan_out <= abst_scan_in; +time_scan_out <= time_scan_in; +repr_scan_out <= repr_scan_in; + +bo_pc_failout <= '0'; +bo_pc_diagloop <= '0'; + +unused <= or_reduce( sg_0 & abst_sl_thold_0 & ary_nsl_thold_0 & time_sl_thold_0 & repr_sl_thold_0 + & scan_dis_dc_b & scan_diag_dc & ccflush_dc + & clkoff_dc_b & d_mode_dc & mpw1_dc_b & mpw2_dc_b + & delay_lclkr_dc & abist_di + & abist_bw_odd & abist_bw_even & abist_wr_adr & abist_rd0_adr + & wr_abst_act & rd0_abst_act + & tc_lbist_ary_wrt_thru_dc & abist_ena_1 & abist_g8t_rd0_comp_ena + & abist_raw_dc_b & obs0_abist_cmp & rd0_act & tidn + & lcb_bolt_sl_thold_0 & pc_bo_enable_2 & pc_bo_reset + & pc_bo_unload & pc_bo_repair & pc_bo_shdata & pc_bo_select + & tri_lcb_mpw1_dc_b & tri_lcb_mpw2_dc_b & tri_lcb_delay_lclkr_dc + & tri_lcb_clkoff_dc_b & tri_lcb_act_dis_dc ); + + +end generate; + +end architecture tri_64x72_1r1w; + + + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_aoi22_nlats.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_aoi22_nlats.vhdl new file mode 100644 index 0000000..5a77a6c --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_aoi22_nlats.vhdl @@ -0,0 +1,122 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library support; + use support.power_logic_pkg.all; +library tri; use tri.tri_latches_pkg.all; +-- pragma translate_off +-- pragma translate_on + +entity tri_aoi22_nlats is + + generic ( + offset : natural range 0 to 65535 := 0; + width : positive range 1 to 65536 := 1 ; + init : std_ulogic_vector := "0" ; + synthclonedlatch : string := "" ; + btr : string := "NLL0001_X2_A12TH" ; + needs_sreset : integer := 1 ; + expand_type : integer := 1 ); + port ( + vd : inout power_logic; + gd : inout power_logic; + LCLK : in clk_logic; + D1CLK : in std_ulogic; + D2CLK : in std_ulogic; + SCANIN : in std_ulogic_vector(offset to offset+width-1); + SCANOUT : out std_ulogic_vector(offset to offset+width-1); + A1 : in std_ulogic_vector(offset to offset+width-1); + A2 : in std_ulogic_vector(offset to offset+width-1); + B1 : in std_ulogic_vector(offset to offset+width-1); + B2 : in std_ulogic_vector(offset to offset+width-1); + QB : out std_ulogic_vector(offset to offset+width-1) + ); + + -- synopsys translate_off + + -- synopsys translate_on + +end entity tri_aoi22_nlats; + +architecture tri_aoi22_nlats of tri_aoi22_nlats is + +begin + + a: if expand_type = 1 generate + constant init_v : std_ulogic_vector(0 to (init'length + width-1)):=init & (0 to width-1=>'0'); + constant zeros : std_ulogic_vector(0 to width-1) := (0 to width-1 => '0'); + + signal sreset : std_ulogic; + signal int_din : std_ulogic_vector(0 to width-1); + signal int_dout : std_ulogic_vector(0 to width-1) := init_v(0 to width-1); + signal vact, vact_b : std_ulogic_vector(0 to width-1); + signal vsreset, vsreset_b : std_ulogic_vector(0 to width-1); + signal vthold, vthold_b : std_ulogic_vector(0 to width-1); + signal din : std_ulogic_vector(0 to width-1); + signal unused : std_ulogic_vector(0 to width-1); + -- synopsys translate_off + -- synopsys translate_on + begin + rst: if needs_sreset = 1 generate + sreset <= LCLK.sreset; + end generate rst; + no_rst: if needs_sreset /=1 generate + sreset <= '0'; + end generate no_rst; + + vsreset <= (0 to width-1 => sreset); + vsreset_b <= (0 to width-1 => not sreset); + din <= (A1 and A2) or (B1 and B2) ; + int_din <= (vsreset_b and din) or + (vsreset and init_v(0 to width-1)); + + vact <= (0 to width-1 => D1CLK); + vact_b <= (0 to width-1 => not D1CLK); + + vthold_b <= (0 to width-1 => D2CLK); + vthold <= (0 to width-1 => not D2CLK); + + l: process (LCLK, vact, int_din, vact_b, int_dout, vsreset, vsreset_b, vthold_b, vthold) + begin + if rising_edge(LCLK.clk) then + int_dout <= (((vact and vthold_b) or vsreset) and int_din) or + (((vact_b or vthold) and vsreset_b) and int_dout); + end if; + end process l; + QB <= not int_dout; + SCANOUT <= zeros; + + unused <= SCANIN; + end generate a; + +end tri_aoi22_nlats; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_aoi22_nlats_wlcb.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_aoi22_nlats_wlcb.vhdl new file mode 100644 index 0000000..aaa3c9e --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_aoi22_nlats_wlcb.vhdl @@ -0,0 +1,133 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library support; + use support.power_logic_pkg.all; +library tri; use tri.tri_latches_pkg.all; +-- pragma translate_off +-- pragma translate_on + +entity tri_aoi22_nlats_wlcb is + + generic ( + width : integer := 4; + offset : integer range 0 to 65535 := 0 ; + init : integer := 0; + ibuf : boolean := false; + dualscan : string := ""; + needs_sreset: integer := 1 ; + expand_type : integer := 1 ; + synthclonedlatch : string := "" ; + btr : string := "NLL0001_X2_A12TH" ); + + port ( + vd : inout power_logic; + gd : inout power_logic; + nclk : in clk_logic; + act : in std_ulogic := '1'; + forcee : in std_ulogic := '0'; + thold_b : in std_ulogic := '1'; + d_mode : in std_ulogic := '0'; + sg : in std_ulogic := '0'; + delay_lclkr : in std_ulogic := '0'; + mpw1_b : in std_ulogic := '1'; + mpw2_b : in std_ulogic := '1'; + scin : in std_ulogic_vector(offset to offset+width-1); + scout : out std_ulogic_vector(offset to offset+width-1); + A1 : in std_ulogic_vector(offset to offset+width-1); + A2 : in std_ulogic_vector(offset to offset+width-1); + B1 : in std_ulogic_vector(offset to offset+width-1); + B2 : in std_ulogic_vector(offset to offset+width-1); + QB : out std_ulogic_vector(offset to offset+width-1)); + + -- synopsys translate_off + + -- synopsys translate_on + +end entity tri_aoi22_nlats_wlcb; + +architecture tri_aoi22_nlats_wlcb of tri_aoi22_nlats_wlcb is + + constant init_v : std_ulogic_vector(0 to width-1) := std_ulogic_vector( to_unsigned( init, width ) ); + constant zeros : std_ulogic_vector(0 to width-1) := (0 to width-1 => '0'); + +begin + + a: if expand_type = 1 generate + signal sreset : std_ulogic; + signal int_din, din : std_ulogic_vector(0 to width-1); + signal int_dout : std_ulogic_vector(0 to width-1) := init_v; + signal vact, vact_b : std_ulogic_vector(0 to width-1); + signal vsreset, vsreset_b : std_ulogic_vector(0 to width-1); + signal vthold, vthold_b : std_ulogic_vector(0 to width-1); + signal unused : std_ulogic_vector(0 to width); + -- synopsys translate_off + -- synopsys translate_on + begin + rst: if needs_sreset = 1 generate + sreset <= nclk.sreset; + end generate rst; + no_rst: if needs_sreset /=1 generate + sreset <= '0'; + end generate no_rst; + + vsreset <= (0 to width-1 => sreset); + vsreset_b <= (0 to width-1 => not sreset); + + din <= (A1 and A2) or (B1 and B2) ; + int_din <= (vsreset_b and din) or + (vsreset and init_v); + + vact <= (0 to width-1 => (act or forcee)); + vact_b <= (0 to width-1 => not (act or forcee)); + + vthold_b <= (0 to width-1 => thold_b); + vthold <= (0 to width-1 => not thold_b); + + l: process (nclk, vact, int_din, vact_b, int_dout, vsreset, vsreset_b, vthold_b, vthold) + begin + if rising_edge(nclk.clk) then + int_dout <= (((vact and vthold_b) or vsreset) and int_din) or + (((vact_b or vthold) and vsreset_b) and int_dout); + end if; + end process l; + + QB <= not int_dout; + + scout <= zeros; + + unused(0) <= d_mode or sg or delay_lclkr or mpw1_b or mpw2_b; + unused(1 to width) <= scin; + end generate a; + +end tri_aoi22_nlats_wlcb; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_bht.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_bht.vhdl new file mode 100644 index 0000000..c71ddff --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_bht.vhdl @@ -0,0 +1,501 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + + +library ieee; +use ieee.std_logic_1164.all; + +library ibm; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; + +library support; +use support.power_logic_pkg.all; + +library tri; +use tri.tri_latches_pkg.all; + + +entity tri_bht is +generic(expand_type : integer := 1 ); +port( + gnd : inout power_logic; + vdd : inout power_logic; + vcs : inout power_logic; + + nclk : in clk_logic; + pc_iu_func_sl_thold_2 : in std_ulogic; + pc_iu_sg_2 : in std_ulogic; + pc_iu_time_sl_thold_2 : in std_ulogic; + pc_iu_abst_sl_thold_2 : in std_ulogic; + pc_iu_ary_nsl_thold_2 : in std_ulogic; + pc_iu_repr_sl_thold_2 : in std_ulogic; + pc_iu_bolt_sl_thold_2 : in std_ulogic; + tc_ac_ccflush_dc : in std_ulogic; + tc_ac_scan_dis_dc_b : in std_ulogic; + clkoff_b : in std_ulogic; + scan_diag_dc : in std_ulogic; + act_dis : in std_ulogic; + d_mode : in std_ulogic; + delay_lclkr : in std_ulogic; + mpw1_b : in std_ulogic; + mpw2_b : in std_ulogic; + g8t_clkoff_b : in std_ulogic; + g8t_d_mode : in std_ulogic; + g8t_delay_lclkr : in std_ulogic_vector(0 to 4); + g8t_mpw1_b : in std_ulogic_vector(0 to 4); + g8t_mpw2_b : in std_ulogic; + func_scan_in : in std_ulogic; + time_scan_in : in std_ulogic; + abst_scan_in : in std_ulogic; + repr_scan_in : in std_ulogic; + func_scan_out : out std_ulogic; + time_scan_out : out std_ulogic; + abst_scan_out : out std_ulogic; + repr_scan_out : out std_ulogic; + + pc_iu_abist_di_0 : in std_ulogic_vector(0 to 3); + pc_iu_abist_g8t_bw_1 : in std_ulogic; + pc_iu_abist_g8t_bw_0 : in std_ulogic; + pc_iu_abist_waddr_0 : in std_ulogic_vector(3 to 9); + pc_iu_abist_g8t_wenb : in std_ulogic; + pc_iu_abist_raddr_0 : in std_ulogic_vector(3 to 9); + pc_iu_abist_g8t1p_renb_0 : in std_ulogic; + an_ac_lbist_ary_wrt_thru_dc: in std_ulogic; + pc_iu_abist_ena_dc : in std_ulogic; + pc_iu_abist_wl128_comp_ena : in std_ulogic; + pc_iu_abist_raw_dc_b : in std_ulogic; + pc_iu_abist_g8t_dcomp : in std_ulogic_vector(0 to 3); + + pc_iu_bo_enable_2 : in std_ulogic; + pc_iu_bo_reset : in std_ulogic; + pc_iu_bo_unload : in std_ulogic; + pc_iu_bo_repair : in std_ulogic; + pc_iu_bo_shdata : in std_ulogic; + pc_iu_bo_select : in std_ulogic; + iu_pc_bo_fail : out std_ulogic; + iu_pc_bo_diagout : out std_ulogic; + + r_act : in std_ulogic; + w_act : in std_ulogic_vector(0 to 3); + r_addr : in std_ulogic_vector(0 to 7); + w_addr : in std_ulogic_vector(0 to 7); + data_in : in std_ulogic_vector(0 to 1); + data_out0 : out std_ulogic_vector(0 to 1); + data_out1 : out std_ulogic_vector(0 to 1); + data_out2 : out std_ulogic_vector(0 to 1); + data_out3 : out std_ulogic_vector(0 to 1) + +); + +-- pragma translate_off + + +-- pragma translate_on + +end tri_bht; +architecture tri_bht of tri_bht is + + +constant data_in_offset : natural := 0; +constant w_act_offset : natural := data_in_offset + 2; +constant r_act_offset : natural := w_act_offset + 4; +constant w_addr_offset : natural := r_act_offset + 1; +constant r_addr_offset : natural := w_addr_offset + 8; +constant data_out_offset : natural := r_addr_offset + 8; +constant array_offset : natural := data_out_offset + 8; +constant scan_right : natural := array_offset + 1 - 1; + +constant INIT_MASK : std_ulogic_vector(0 to 1) := "10"; + + +signal pc_iu_func_sl_thold_1 : std_ulogic; +signal pc_iu_func_sl_thold_0 : std_ulogic; +signal pc_iu_func_sl_thold_0_b : std_ulogic; +signal pc_iu_time_sl_thold_1 : std_ulogic; +signal pc_iu_time_sl_thold_0 : std_ulogic; +signal pc_iu_ary_nsl_thold_1 : std_ulogic; +signal pc_iu_ary_nsl_thold_0 : std_ulogic; +signal pc_iu_abst_sl_thold_1 : std_ulogic; +signal pc_iu_abst_sl_thold_0 : std_ulogic; +signal pc_iu_repr_sl_thold_1 : std_ulogic; +signal pc_iu_repr_sl_thold_0 : std_ulogic; +signal pc_iu_bolt_sl_thold_1 : std_ulogic; +signal pc_iu_bolt_sl_thold_0 : std_ulogic; +signal pc_iu_sg_1 : std_ulogic; +signal pc_iu_sg_0 : std_ulogic; +signal forcee : std_ulogic; + +signal siv : std_ulogic_vector(0 to scan_right); +signal sov : std_ulogic_vector(0 to scan_right); + +signal tiup : std_ulogic; + +signal data_out_d : std_ulogic_vector(0 to 7); +signal data_out_q : std_ulogic_vector(0 to 7); + +signal ary_w_en : std_ulogic; +signal ary_w_addr : std_ulogic_vector(0 to 6); +signal ary_w_sel : std_ulogic_vector(0 to 15); +signal ary_w_data : std_ulogic_vector(0 to 15); + +signal ary_r_en : std_ulogic; +signal ary_r_addr : std_ulogic_vector(0 to 6); +signal ary_r_data : std_ulogic_vector(0 to 15); + +signal data_out : std_ulogic_vector(0 to 7); +signal write_thru : std_ulogic_vector(0 to 3); + +signal data_in_d : std_ulogic_vector(0 to 1); +signal data_in_q : std_ulogic_vector(0 to 1); +signal w_act_d : std_ulogic_vector(0 to 3); +signal w_act_q : std_ulogic_vector(0 to 3); +signal r_act_d : std_ulogic; +signal r_act_q : std_ulogic; +signal w_addr_d : std_ulogic_vector(0 to 7); +signal w_addr_q : std_ulogic_vector(0 to 7); +signal r_addr_d : std_ulogic_vector(0 to 7); +signal r_addr_q : std_ulogic_vector(0 to 7); + + +begin + + +tiup <= '1'; + + +data_out0(0 to 1) <= data_out_q(0 to 1); +data_out1(0 to 1) <= data_out_q(2 to 3); +data_out2(0 to 1) <= data_out_q(4 to 5); +data_out3(0 to 1) <= data_out_q(6 to 7); + + +ary_w_en <= or_reduce(w_act(0 to 3)) and not ((w_addr(1 to 7) = r_addr(1 to 7)) and r_act = '1'); + +ary_w_addr(0 to 6) <= w_addr(1 to 7); + +ary_w_sel(0) <= w_act(0) and w_addr(0) = '0'; +ary_w_sel(1) <= w_act(0) and w_addr(0) = '0'; +ary_w_sel(2) <= w_act(1) and w_addr(0) = '0'; +ary_w_sel(3) <= w_act(1) and w_addr(0) = '0'; +ary_w_sel(4) <= w_act(2) and w_addr(0) = '0'; +ary_w_sel(5) <= w_act(2) and w_addr(0) = '0'; +ary_w_sel(6) <= w_act(3) and w_addr(0) = '0'; +ary_w_sel(7) <= w_act(3) and w_addr(0) = '0'; +ary_w_sel(8) <= w_act(0) and w_addr(0) = '1'; +ary_w_sel(9) <= w_act(0) and w_addr(0) = '1'; +ary_w_sel(10) <= w_act(1) and w_addr(0) = '1'; +ary_w_sel(11) <= w_act(1) and w_addr(0) = '1'; +ary_w_sel(12) <= w_act(2) and w_addr(0) = '1'; +ary_w_sel(13) <= w_act(2) and w_addr(0) = '1'; +ary_w_sel(14) <= w_act(3) and w_addr(0) = '1'; +ary_w_sel(15) <= w_act(3) and w_addr(0) = '1'; + +ary_w_data(0 to 15) <= (data_in(0 to 1) xor INIT_MASK(0 to 1)) & + (data_in(0 to 1) xor INIT_MASK(0 to 1)) & + (data_in(0 to 1) xor INIT_MASK(0 to 1)) & + (data_in(0 to 1) xor INIT_MASK(0 to 1)) & + (data_in(0 to 1) xor INIT_MASK(0 to 1)) & + (data_in(0 to 1) xor INIT_MASK(0 to 1)) & + (data_in(0 to 1) xor INIT_MASK(0 to 1)) & + (data_in(0 to 1) xor INIT_MASK(0 to 1)) ; + +ary_r_en <= r_act; + +ary_r_addr(0 to 6) <= r_addr(1 to 7); + +data_out(0 to 7) <= gate(ary_r_data(0 to 7) xor (INIT_MASK(0 to 1) & INIT_MASK(0 to 1) & INIT_MASK(0 to 1) & INIT_MASK(0 to 1)), r_addr_q(0) = '0') or + gate(ary_r_data(8 to 15) xor (INIT_MASK(0 to 1) & INIT_MASK(0 to 1) & INIT_MASK(0 to 1) & INIT_MASK(0 to 1)), r_addr_q(0) = '1') ; + + +data_in_d(0 to 1) <= data_in(0 to 1); +w_act_d(0 to 3) <= w_act(0 to 3); +r_act_d <= r_act; +w_addr_d(0 to 7) <= w_addr(0 to 7); +r_addr_d(0 to 7) <= r_addr(0 to 7); + +write_thru(0 to 3) <= w_act_q(0 to 3) when (w_addr_q(0 to 7) = r_addr_q(0 to 7)) and r_act_q = '1' else "0000"; + +data_out_d(0 to 1) <= data_in_q(0 to 1) when write_thru(0) = '1' else + data_out(0 to 1); +data_out_d(2 to 3) <= data_in_q(0 to 1) when write_thru(1) = '1' else + data_out(2 to 3); +data_out_d(4 to 5) <= data_in_q(0 to 1) when write_thru(2) = '1' else + data_out(4 to 5); +data_out_d(6 to 7) <= data_in_q(0 to 1) when write_thru(3) = '1' else + data_out(6 to 7); + + +bht0: entity tri.tri_128x16_1r1w_1 + generic map ( expand_type => expand_type ) + port map( + gnd => gnd, + vdd => vdd, + vcs => vcs, + nclk => nclk, + + rd_act => ary_r_en, + wr_act => ary_w_en, + + lcb_d_mode_dc => g8t_d_mode, + lcb_clkoff_dc_b => g8t_clkoff_b, + lcb_mpw1_dc_b => g8t_mpw1_b, + lcb_mpw2_dc_b => g8t_mpw2_b, + lcb_delay_lclkr_dc => g8t_delay_lclkr, + ccflush_dc => tc_ac_ccflush_dc, + scan_dis_dc_b => tc_ac_scan_dis_dc_b, + scan_diag_dc => scan_diag_dc, + func_scan_in => siv(array_offset), + func_scan_out => sov(array_offset), + + lcb_sg_0 => pc_iu_sg_0, + lcb_sl_thold_0_b => pc_iu_func_sl_thold_0_b, + lcb_time_sl_thold_0 => pc_iu_time_sl_thold_0, + lcb_abst_sl_thold_0 => pc_iu_abst_sl_thold_0, + lcb_ary_nsl_thold_0 => pc_iu_ary_nsl_thold_0, + lcb_repr_sl_thold_0 => pc_iu_repr_sl_thold_0, + time_scan_in => time_scan_in, + time_scan_out => time_scan_out, + abst_scan_in => abst_scan_in, + abst_scan_out => abst_scan_out, + repr_scan_in => repr_scan_in, + repr_scan_out => repr_scan_out, + + abist_di => pc_iu_abist_di_0, + abist_bw_odd => pc_iu_abist_g8t_bw_1, + abist_bw_even => pc_iu_abist_g8t_bw_0, + abist_wr_adr => pc_iu_abist_waddr_0, + wr_abst_act => pc_iu_abist_g8t_wenb, + abist_rd0_adr => pc_iu_abist_raddr_0, + rd0_abst_act => pc_iu_abist_g8t1p_renb_0, + tc_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc, + abist_ena_1 => pc_iu_abist_ena_dc, + abist_g8t_rd0_comp_ena => pc_iu_abist_wl128_comp_ena, + abist_raw_dc_b => pc_iu_abist_raw_dc_b, + obs0_abist_cmp => pc_iu_abist_g8t_dcomp, + + lcb_bolt_sl_thold_0 => pc_iu_bolt_sl_thold_0, + pc_bo_enable_2 => pc_iu_bo_enable_2, + pc_bo_reset => pc_iu_bo_reset, + pc_bo_unload => pc_iu_bo_unload, + pc_bo_repair => pc_iu_bo_repair, + pc_bo_shdata => pc_iu_bo_shdata, + pc_bo_select => pc_iu_bo_select, + bo_pc_failout => iu_pc_bo_fail, + bo_pc_diagloop => iu_pc_bo_diagout, + + tri_lcb_mpw1_dc_b => mpw1_b, + tri_lcb_mpw2_dc_b => mpw2_b, + tri_lcb_delay_lclkr_dc => delay_lclkr, + tri_lcb_clkoff_dc_b => clkoff_b, + tri_lcb_act_dis_dc => act_dis, + + bw => ary_w_sel, + wr_adr => ary_w_addr, + rd_adr => ary_r_addr, + di => ary_w_data, + do => ary_r_data +); + + + + +data_in_reg: tri_rlmreg_p +generic map (width => data_in_q'length, init => 0, expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(data_in_offset to data_in_offset + data_in_q'length-1), + scout => sov(data_in_offset to data_in_offset + data_in_q'length-1), + din => data_in_d, + dout => data_in_q); + +w_act_reg: tri_rlmreg_p +generic map (width => w_act_q'length, init => 0, expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(w_act_offset to w_act_offset + w_act_q'length-1), + scout => sov(w_act_offset to w_act_offset + w_act_q'length-1), + din => w_act_d, + dout => w_act_q); + +r_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(r_act_offset), + scout => sov(r_act_offset), + din => r_act_d, + dout => r_act_q); + +w_addr_reg: tri_rlmreg_p +generic map (width => w_addr_q'length, init => 0, expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(w_addr_offset to w_addr_offset + w_addr_q'length-1), + scout => sov(w_addr_offset to w_addr_offset + w_addr_q'length-1), + din => w_addr_d, + dout => w_addr_q); + +r_addr_reg: tri_rlmreg_p +generic map (width => r_addr_q'length, init => 0, expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(r_addr_offset to r_addr_offset + r_addr_q'length-1), + scout => sov(r_addr_offset to r_addr_offset + r_addr_q'length-1), + din => r_addr_d, + dout => r_addr_q); + + +data_out_reg: tri_rlmreg_p +generic map (width => data_out_q'length, init => 0, expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(data_out_offset to data_out_offset + data_out_q'length-1), + scout => sov(data_out_offset to data_out_offset + data_out_q'length-1), + din => data_out_d, + dout => data_out_q); + + + +perv_2to1_reg: tri_plat + generic map (width => 7, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_iu_func_sl_thold_2, + din(1) => pc_iu_sg_2, + din(2) => pc_iu_time_sl_thold_2, + din(3) => pc_iu_abst_sl_thold_2, + din(4) => pc_iu_ary_nsl_thold_2, + din(5) => pc_iu_repr_sl_thold_2, + din(6) => pc_iu_bolt_sl_thold_2, + q(0) => pc_iu_func_sl_thold_1, + q(1) => pc_iu_sg_1, + q(2) => pc_iu_time_sl_thold_1, + q(3) => pc_iu_abst_sl_thold_1, + q(4) => pc_iu_ary_nsl_thold_1, + q(5) => pc_iu_repr_sl_thold_1, + q(6) => pc_iu_bolt_sl_thold_1 +); + +perv_1to0_reg: tri_plat + generic map (width => 7, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_iu_func_sl_thold_1, + din(1) => pc_iu_sg_1, + din(2) => pc_iu_time_sl_thold_1, + din(3) => pc_iu_abst_sl_thold_1, + din(4) => pc_iu_ary_nsl_thold_1, + din(5) => pc_iu_repr_sl_thold_1, + din(6) => pc_iu_bolt_sl_thold_1, + q(0) => pc_iu_func_sl_thold_0, + q(1) => pc_iu_sg_0, + q(2) => pc_iu_time_sl_thold_0, + q(3) => pc_iu_abst_sl_thold_0, + q(4) => pc_iu_ary_nsl_thold_0, + q(5) => pc_iu_repr_sl_thold_0, + q(6) => pc_iu_bolt_sl_thold_0 +); + +perv_lcbor: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_b, + thold => pc_iu_func_sl_thold_0, + sg => pc_iu_sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => pc_iu_func_sl_thold_0_b); + + + +siv(0 to scan_right) <= func_scan_in & sov(0 to scan_right-1); +func_scan_out <= sov(scan_right); + + +end tri_bht; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_boltreg_p.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_boltreg_p.vhdl new file mode 100644 index 0000000..e938781 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_boltreg_p.vhdl @@ -0,0 +1,191 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; use ieee.std_logic_1164.all; + use ieee.numeric_std.all; +library ibm; +library support; + use support.power_logic_pkg.all; +library tri; use tri.tri_latches_pkg.all; + +entity tri_boltreg_p is + + generic ( + width : integer := 4; + offset : integer range 0 to 65535 := 0 ; + init : integer := 0; + ibuf : boolean := false; + dualscan : string := ""; + needs_sreset: integer := 1 ; + expand_type : integer := 1 ); + + port ( + vd : inout power_logic; + gd : inout power_logic; + nclk : in clk_logic; + act : in std_ulogic := '1'; + forcee : in std_ulogic := '0'; + thold_b : in std_ulogic := '1'; + d_mode : in std_ulogic := '0'; + sg : in std_ulogic := '0'; + delay_lclkr : in std_ulogic := '0'; + mpw1_b : in std_ulogic := '1'; + mpw2_b : in std_ulogic := '1'; + scin : in std_ulogic_vector(offset to offset+width-1); + din : in std_ulogic_vector(offset to offset+width-1); + scout : out std_ulogic_vector(offset to offset+width-1); + dout : out std_ulogic_vector(offset to offset+width-1) ); + + -- synopsys translate_off + + -- synopsys translate_on + +end entity tri_boltreg_p; + +architecture tri_boltreg_p of tri_boltreg_p is + + constant init_v : std_ulogic_vector(0 to width-1) := std_ulogic_vector( to_unsigned( init, width ) ); + constant zeros : std_ulogic_vector(0 to width-1) := (0 to width-1 => '0'); + +begin + + -- synopsys translate_off + um: if expand_type = 0 generate + component c_rlmreg_p + generic ( width : positive := 4 ; + init : std_ulogic_vector := "0"; + dualscan : string := "" + ); + port ( + nclk : in std_ulogic; + act : in std_ulogic; + thold_b : in std_ulogic; + sg : in std_ulogic; + scin : in std_ulogic_vector(0 to width-1); + din : in std_ulogic_vector(0 to width-1); + dout : out std_ulogic_vector(0 to width-1); + scout : out std_ulogic_vector(0 to width-1) + ); + end component; + signal scanin_inv : std_ulogic_vector(0 to width-1); + signal scanout_inv : std_ulogic_vector(0 to width-1); + signal act_or_force : std_ulogic; + signal din_buf : std_ulogic_vector(0 to width-1); + signal dout_buf : std_ulogic_vector(0 to width-1); + begin + act_or_force <= act or forcee; + + cib: + if ibuf = true generate + din_buf <= not din; + dout <= not dout_buf; + end generate cib; + cnib: + if ibuf = false generate + din_buf <= din; + dout <= dout_buf; + end generate cnib; + + l:c_rlmreg_p + generic map (width => width, init => init_v, dualscan => dualscan) + port map ( + nclk => nclk.clk, + act => act_or_force, + thold_b => thold_b, + sg => sg, + scin => scanin_inv, + din => din_buf, + scout => scanout_inv, + dout => dout_buf); + + scanin_inv <= scin xor init_v; + scout <= scanout_inv xor init_v; + end generate um; + -- synopsys translate_on + + a: if expand_type = 1 generate + signal sreset : std_ulogic; + signal int_din : std_ulogic_vector(0 to width-1); + signal int_dout : std_ulogic_vector(0 to width-1) := init_v; + signal vact, vact_b : std_ulogic_vector(0 to width-1); + signal vsreset, vsreset_b : std_ulogic_vector(0 to width-1); + signal vthold, vthold_b : std_ulogic_vector(0 to width-1); + signal unused : std_ulogic_vector(0 to width); + -- synopsys translate_off + -- synopsys translate_on + begin + rst: if needs_sreset = 1 generate + sreset <= nclk.sreset; + end generate rst; + no_rst: if needs_sreset /=1 generate + sreset <= '0'; + end generate no_rst; + + vsreset <= (0 to width-1 => sreset); + vsreset_b <= (0 to width-1 => not sreset); + + cib: if ibuf = true generate + int_din <= (vsreset_b and not din) or + (vsreset and init_v); + end generate cib; + cnib: if ibuf = false generate + int_din <= (vsreset_b and din) or + (vsreset and init_v); + end generate cnib; + + vact <= (0 to width-1 => (act or forcee)); + vact_b <= (0 to width-1 => not (act or forcee)); + + vthold_b <= (0 to width-1 => thold_b); + vthold <= (0 to width-1 => not thold_b); + + l: process (nclk, vact, int_din, vact_b, int_dout, vsreset, vsreset_b, vthold_b, vthold) + begin + if rising_edge(nclk.clk) then + int_dout <= (((vact and vthold_b) or vsreset) and int_din) or + (((vact_b or vthold) and vsreset_b) and int_dout); + end if; + end process l; + + cob: if ibuf = true generate + dout <= not int_dout; + end generate cob; + + cnob: if ibuf = false generate + dout <= int_dout; + end generate cnob; + + scout <= zeros; + + unused(0) <= d_mode or sg or delay_lclkr or mpw1_b or mpw2_b; + unused(1 to width) <= scin; + end generate a; + +end tri_boltreg_p; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_caa_prism_abist.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_caa_prism_abist.vhdl new file mode 100644 index 0000000..db0d305 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_caa_prism_abist.vhdl @@ -0,0 +1,145 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee, ibm; +use ieee.std_logic_1164.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +library support; +USE support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + + +entity tri_caa_prism_abist is +generic(expand_type : integer := 1 ); +Port (vdd : INOUT power_logic; + gnd : INOUT power_logic; + nclk : In clk_logic; + scan_dis_dc_b : In std_ulogic; + lcb_clkoff_dc_b : In std_ulogic; + lcb_mpw1_dc_b : In std_ulogic; + lcb_mpw2_dc_b : In std_ulogic; + lcb_delay_lclkr_dc : In std_ulogic; + lcb_delay_lclkr_np_dc : In std_ulogic; + lcb_act_dis_dc : In std_ulogic; + lcb_d_mode_dc : In std_ulogic; + gptr_thold : In std_ulogic; + gptr_scan_in : In std_ulogic; + gptr_scan_out : Out std_ulogic; + abist_thold : In std_ulogic; + abist_sg : In std_ulogic; + abist_scan_in : In std_ulogic; + abist_scan_out : Out std_ulogic; + abist_done_in_dc : In std_ulogic; + abist_done_out_dc : Out std_ulogic; + abist_mode_dc : In std_ulogic; + abist_start_test : In std_ulogic; + lbist_mode_dc : In std_ulogic; + lbist_ac_mode_dc : In std_ulogic; + abist_waddr_0 : Out std_ulogic_vector(0 to 9); + abist_waddr_1 : Out std_ulogic_vector(0 to 9); + abist_grf_wenb_0 : Out std_ulogic; + abist_grf_wenb_1 : Out std_ulogic; + abist_raddr_0 : Out std_ulogic_vector(0 to 9); + abist_raddr_1 : Out std_ulogic_vector(0 to 9); + abist_grf_renb_0 : Out std_ulogic; + abist_grf_renb_1 : Out std_ulogic; + abist_g8t_wenb : Out std_ulogic; + abist_g8t1p_renb_0 : Out std_ulogic; + abist_g6t_r_wb : Out std_ulogic; + abist_di_g6t_2r : Out std_ulogic_vector(0 to 3); + abist_di_0 : Out std_ulogic_vector(0 to 3); + abist_di_1 : Out std_ulogic_vector(0 to 3); + abist_dcomp : Out std_ulogic_vector(0 to 3); + abist_dcomp_g6t_2r : Out std_ulogic_vector(0 to 3); + abist_bw_0 : Out std_ulogic; + abist_bw_1 : Out std_ulogic; + abist_wl32_g8t_comp_ena : Out std_ulogic; + abist_wl64_g8t_comp_ena : Out std_ulogic; + abist_wl128_g8t_comp_ena : Out std_ulogic; + abist_wl144_comp_ena : Out std_ulogic; + abist_wl256_comp_ena : Out std_ulogic; + abist_wl512_comp_ena : Out std_ulogic; + abist_ena_dc : Out std_ulogic; + abist_raw_dc_b : Out std_ulogic +); + +-- synopsys translate_off + + + + +-- synopsys translate_on +end entity tri_caa_prism_abist; + +architecture tri_caa_prism_abist of tri_caa_prism_abist is + +signal unused : std_ulogic; +-- synopsys translate_off +-- synopsys translate_on + +begin + + gptr_scan_out <= '0'; + abist_scan_out <= '0'; + abist_done_out_dc <= '0'; + abist_waddr_0 <= "0000000000"; + abist_waddr_1 <= "0000000000"; + abist_grf_wenb_0 <= '0'; + abist_grf_wenb_1 <= '0'; + abist_raddr_0 <= "0000000000"; + abist_raddr_1 <= "0000000000"; + abist_grf_renb_0 <= '0'; + abist_grf_renb_1 <= '0'; + abist_g8t_wenb <= '0'; + abist_g8t1p_renb_0 <= '0'; + abist_g6t_r_wb <= '0'; + abist_di_g6t_2r <= "0000"; + abist_di_0 <= "0000"; + abist_di_1 <= "0000"; + abist_dcomp <= "0000"; + abist_dcomp_g6t_2r <= "0000"; + abist_bw_0 <= '0'; + abist_bw_1 <= '0'; + abist_wl32_g8t_comp_ena <= '0'; + abist_wl64_g8t_comp_ena <= '0'; + abist_wl128_g8t_comp_ena <= '0'; + abist_wl144_comp_ena <= '0'; + abist_wl256_comp_ena <= '0'; + abist_wl512_comp_ena <= '0'; + abist_ena_dc <= '0'; + abist_raw_dc_b <= '0'; + + unused <= or_reduce(scan_dis_dc_b & lcb_clkoff_dc_b & lcb_mpw1_dc_b & lcb_mpw2_dc_b & + lcb_delay_lclkr_dc & lcb_delay_lclkr_np_dc & lcb_act_dis_dc & lcb_d_mode_dc & + gptr_thold & gptr_scan_in & abist_thold & abist_sg & abist_scan_in & + abist_done_in_dc & abist_mode_dc & abist_start_test & + lbist_mode_dc & lbist_ac_mode_dc ); + +end tri_caa_prism_abist; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_cam_16x143_1r1w1c.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_cam_16x143_1r1w1c.vhdl new file mode 100644 index 0000000..2fd878b --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_cam_16x143_1r1w1c.vhdl @@ -0,0 +1,2775 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; +use ieee.std_logic_1164.all; +library ibm; +use ibm.std_ulogic_unsigned.all; +use ibm.std_ulogic_function_support.all; +library support; +use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; +-- pragma translate_off +-- pragma translate_on +entity tri_cam_16x143_1r1w1c is + + generic (cam_data_width : natural := 84; + array_data_width : natural := 68; + rpn_width : natural := 30; + num_entry : natural := 16; + num_entry_log2 : natural := 4; + expand_type : integer := 1); + port( + gnd : inout power_logic; + vdd : inout power_logic; + vcs : inout power_logic; + + nclk : in clk_logic; + tc_ccflush_dc : in std_ulogic; + tc_scan_dis_dc_b : in std_ulogic; + tc_scan_diag_dc : in std_ulogic; + tc_lbist_en_dc : in std_ulogic; + an_ac_atpg_en_dc : in std_ulogic; + + lcb_d_mode_dc : in std_ulogic; + lcb_clkoff_dc_b : in std_ulogic; + lcb_act_dis_dc : in std_ulogic; + lcb_mpw1_dc_b : in std_ulogic_vector(0 to 3); + lcb_mpw2_dc_b : in std_ulogic; + lcb_delay_lclkr_dc : in std_ulogic_vector(0 to 3); + + pc_sg_2 : in std_ulogic; + pc_func_slp_sl_thold_2 : in std_ulogic; + pc_func_slp_nsl_thold_2 : in std_ulogic; + pc_regf_slp_sl_thold_2 : in std_ulogic; + pc_time_sl_thold_2 : in std_ulogic; + pc_fce_2 : in std_ulogic; + + func_scan_in : in std_ulogic; + func_scan_out : out std_ulogic; + regfile_scan_in : in std_ulogic_vector(0 TO 4); + regfile_scan_out : out std_ulogic_vector(0 TO 4); + time_scan_in : in std_ulogic; + time_scan_out : out std_ulogic; + + + rd_val : in std_ulogic; + rd_val_late : in std_ulogic; + rw_entry : in std_ulogic_vector(0 to num_entry_log2-1); + + wr_array_data : in std_ulogic_vector(0 to array_data_width-1); + wr_cam_data : in std_ulogic_vector(0 to cam_data_width-1); + wr_array_val : in std_ulogic_vector(0 to 1); + wr_cam_val : in std_ulogic_vector(0 to 1); + wr_val_early : in std_ulogic; + + comp_request : in std_ulogic; + comp_addr : in std_ulogic_vector(0 to 51); + addr_enable : in std_ulogic_vector(0 to 1); + comp_pgsize : in std_ulogic_vector(0 to 2); + pgsize_enable : in std_ulogic; + comp_class : in std_ulogic_vector(0 to 1); + class_enable : in std_ulogic_vector(0 to 2); + comp_extclass : in std_ulogic_vector(0 to 1); + extclass_enable : in std_ulogic_vector(0 to 1); + comp_state : in std_ulogic_vector(0 to 1); + state_enable : in std_ulogic_vector(0 to 1); + comp_thdid : in std_ulogic_vector(0 to 3); + thdid_enable : in std_ulogic_vector(0 to 1); + comp_pid : in std_ulogic_vector(0 to 7); + pid_enable : in std_ulogic; + comp_invalidate : in std_ulogic; + flash_invalidate : in std_ulogic; + + array_cmp_data : out std_ulogic_vector(0 to array_data_width-1); + rd_array_data : out std_ulogic_vector(0 to array_data_width-1); + + cam_cmp_data : out std_ulogic_vector(0 to cam_data_width-1); + cam_hit : out std_ulogic; + cam_hit_entry : out std_ulogic_vector(0 to num_entry_log2-1); + entry_match : out std_ulogic_vector(0 to num_entry-1); + entry_valid : out std_ulogic_vector(0 to num_entry-1); + rd_cam_data : out std_ulogic_vector(0 to cam_data_width-1); + + +bypass_mux_enab_np1 : in std_ulogic; +bypass_attr_np1 : in std_ulogic_vector(0 to 20); +attr_np2 : out std_ulogic_vector(0 to 20); +rpn_np2 : out std_ulogic_vector(22 to 51) + + ); +-- synopsys translate_off +-- synopsys translate_on +end entity tri_cam_16x143_1r1w1c; +architecture tri_cam_16x143_1r1w1c of tri_cam_16x143_1r1w1c is +component tri_cam_16x143_1r1w1c_matchline + generic (have_xbit : integer := 1; + num_pgsizes : integer := 5; + have_cmpmask : integer := 1; + cmpmask_width : integer := 4); +port( + addr_in : in std_ulogic_vector(0 to 51); + addr_enable : in std_ulogic_vector(0 to 1); + comp_pgsize : in std_ulogic_vector(0 to 2); + pgsize_enable : in std_ulogic; + entry_size : in std_ulogic_vector(0 to 2); + entry_cmpmask : in std_ulogic_vector(0 to cmpmask_width-1); + entry_xbit : in std_ulogic; + entry_xbitmask : in std_ulogic_vector(0 to cmpmask_width-1); + entry_epn : in std_ulogic_vector(0 to 51); + comp_class : in std_ulogic_vector(0 to 1); + entry_class : in std_ulogic_vector(0 to 1); + class_enable : in std_ulogic_vector(0 to 2); + comp_extclass : in std_ulogic_vector(0 to 1); + entry_extclass : in std_ulogic_vector(0 to 1); + extclass_enable : in std_ulogic_vector(0 to 1); + comp_state : in std_ulogic_vector(0 to 1); + entry_hv : in std_ulogic; + entry_ds : in std_ulogic; + state_enable : in std_ulogic_vector(0 to 1); + entry_thdid : in std_ulogic_vector(0 to 3); + comp_thdid : in std_ulogic_vector(0 to 3); + thdid_enable : in std_ulogic_vector(0 to 1); + entry_pid : in std_ulogic_vector(0 to 7); + comp_pid : in std_ulogic_vector(0 to 7); + pid_enable : in std_ulogic; + entry_v : in std_ulogic; + comp_invalidate : in std_ulogic; + + match : out std_ulogic +); +end component; +begin +a : if expand_type = 1 generate +component RAMB16_S9_S9 +-- pragma translate_off + generic + ( + SIM_COLLISION_CHECK : string := "none"); +-- pragma translate_on + port + ( + DOA : out std_logic_vector(7 downto 0); + DOB : out std_logic_vector(7 downto 0); + DOPA : out std_logic_vector(0 downto 0); + DOPB : out std_logic_vector(0 downto 0); + ADDRA : in std_logic_vector(10 downto 0); + ADDRB : in std_logic_vector(10 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(7 downto 0); + DIB : in std_logic_vector(7 downto 0); + DIPA : in std_logic_vector(0 downto 0); + DIPB : in std_logic_vector(0 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); +end component; +component RAMB16_S18_S18 +-- pragma translate_off + generic( + SIM_COLLISION_CHECK : string := "none"); +-- pragma translate_on + port( + DOA : out std_logic_vector(15 downto 0); + DOB : out std_logic_vector(15 downto 0); + DOPA : out std_logic_vector(1 downto 0); + DOPB : out std_logic_vector(1 downto 0); + + ADDRA : in std_logic_vector(9 downto 0); + ADDRB : in std_logic_vector(9 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(15 downto 0); + DIB : in std_logic_vector(15 downto 0); + DIPA : in std_logic_vector(1 downto 0); + DIPB : in std_logic_vector(1 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic); + end component; +component RAMB16_S36_S36 +-- pragma translate_off + generic( + SIM_COLLISION_CHECK : string := "none"); +-- pragma translate_on + port( + DOA : out std_logic_vector(31 downto 0); + DOB : out std_logic_vector(31 downto 0); + DOPA : out std_logic_vector(3 downto 0); + DOPB : out std_logic_vector(3 downto 0); + ADDRA : in std_logic_vector(8 downto 0); + ADDRB : in std_logic_vector(8 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(31 downto 0); + DIB : in std_logic_vector(31 downto 0); + DIPA : in std_logic_vector(3 downto 0); + DIPB : in std_logic_vector(3 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic); + end component; +-- pragma translate_off +-- pragma translate_on +signal clk,clk2x : std_ulogic; +signal bram0_addra, bram0_addrb : std_ulogic_vector(0 to 8); +signal bram1_addra, bram1_addrb : std_ulogic_vector(0 to 10); +signal bram2_addra, bram2_addrb : std_ulogic_vector(0 to 9); +signal bram0_wea, bram1_wea, bram2_wea : std_ulogic; +signal array_cmp_data_bram : std_ulogic_vector(0 to 55); +signal array_cmp_data_bramp : std_ulogic_vector(66 to 72); +signal sreset_q : std_ulogic; +signal gate_fq, gate_d : std_ulogic; +signal comp_addr_np1_d, comp_addr_np1_q : std_ulogic_vector(52-rpn_width to 51); +signal rpn_np2_d,rpn_np2_q : std_ulogic_vector(52-rpn_width to 51); +signal attr_np2_d,attr_np2_q : std_ulogic_vector(0 to 20); +signal entry0_epn_d, entry0_epn_q : std_ulogic_vector(0 to 51); +signal entry0_xbit_d, entry0_xbit_q : std_ulogic; +signal entry0_size_d, entry0_size_q : std_ulogic_vector(0 to 2); +signal entry0_v_d, entry0_v_q : std_ulogic; +signal entry0_thdid_d, entry0_thdid_q : std_ulogic_vector(0 to 3); +signal entry0_class_d, entry0_class_q : std_ulogic_vector(0 to 1); +signal entry0_extclass_d, entry0_extclass_q : std_ulogic_vector(0 to 1); +signal entry0_hv_d, entry0_hv_q : std_ulogic; +signal entry0_ds_d, entry0_ds_q : std_ulogic; +signal entry0_pid_d, entry0_pid_q : std_ulogic_vector(0 to 7); +signal entry0_cmpmask_d, entry0_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry0_parity_d, entry0_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry0_sel : std_ulogic_vector(0 to 1); +signal entry0_inval : std_ulogic; +signal entry0_v_muxsel : std_ulogic_vector(0 to 1); +signal entry0_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry0_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry1_epn_d, entry1_epn_q : std_ulogic_vector(0 to 51); +signal entry1_xbit_d, entry1_xbit_q : std_ulogic; +signal entry1_size_d, entry1_size_q : std_ulogic_vector(0 to 2); +signal entry1_v_d, entry1_v_q : std_ulogic; +signal entry1_thdid_d, entry1_thdid_q : std_ulogic_vector(0 to 3); +signal entry1_class_d, entry1_class_q : std_ulogic_vector(0 to 1); +signal entry1_extclass_d, entry1_extclass_q : std_ulogic_vector(0 to 1); +signal entry1_hv_d, entry1_hv_q : std_ulogic; +signal entry1_ds_d, entry1_ds_q : std_ulogic; +signal entry1_pid_d, entry1_pid_q : std_ulogic_vector(0 to 7); +signal entry1_cmpmask_d, entry1_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry1_parity_d, entry1_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry1_sel : std_ulogic_vector(0 to 1); +signal entry1_inval : std_ulogic; +signal entry1_v_muxsel : std_ulogic_vector(0 to 1); +signal entry1_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry1_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry2_epn_d, entry2_epn_q : std_ulogic_vector(0 to 51); +signal entry2_xbit_d, entry2_xbit_q : std_ulogic; +signal entry2_size_d, entry2_size_q : std_ulogic_vector(0 to 2); +signal entry2_v_d, entry2_v_q : std_ulogic; +signal entry2_thdid_d, entry2_thdid_q : std_ulogic_vector(0 to 3); +signal entry2_class_d, entry2_class_q : std_ulogic_vector(0 to 1); +signal entry2_extclass_d, entry2_extclass_q : std_ulogic_vector(0 to 1); +signal entry2_hv_d, entry2_hv_q : std_ulogic; +signal entry2_ds_d, entry2_ds_q : std_ulogic; +signal entry2_pid_d, entry2_pid_q : std_ulogic_vector(0 to 7); +signal entry2_cmpmask_d, entry2_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry2_parity_d, entry2_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry2_sel : std_ulogic_vector(0 to 1); +signal entry2_inval : std_ulogic; +signal entry2_v_muxsel : std_ulogic_vector(0 to 1); +signal entry2_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry2_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry3_epn_d, entry3_epn_q : std_ulogic_vector(0 to 51); +signal entry3_xbit_d, entry3_xbit_q : std_ulogic; +signal entry3_size_d, entry3_size_q : std_ulogic_vector(0 to 2); +signal entry3_v_d, entry3_v_q : std_ulogic; +signal entry3_thdid_d, entry3_thdid_q : std_ulogic_vector(0 to 3); +signal entry3_class_d, entry3_class_q : std_ulogic_vector(0 to 1); +signal entry3_extclass_d, entry3_extclass_q : std_ulogic_vector(0 to 1); +signal entry3_hv_d, entry3_hv_q : std_ulogic; +signal entry3_ds_d, entry3_ds_q : std_ulogic; +signal entry3_pid_d, entry3_pid_q : std_ulogic_vector(0 to 7); +signal entry3_cmpmask_d, entry3_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry3_parity_d, entry3_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry3_sel : std_ulogic_vector(0 to 1); +signal entry3_inval : std_ulogic; +signal entry3_v_muxsel : std_ulogic_vector(0 to 1); +signal entry3_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry3_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry4_epn_d, entry4_epn_q : std_ulogic_vector(0 to 51); +signal entry4_xbit_d, entry4_xbit_q : std_ulogic; +signal entry4_size_d, entry4_size_q : std_ulogic_vector(0 to 2); +signal entry4_v_d, entry4_v_q : std_ulogic; +signal entry4_thdid_d, entry4_thdid_q : std_ulogic_vector(0 to 3); +signal entry4_class_d, entry4_class_q : std_ulogic_vector(0 to 1); +signal entry4_extclass_d, entry4_extclass_q : std_ulogic_vector(0 to 1); +signal entry4_hv_d, entry4_hv_q : std_ulogic; +signal entry4_ds_d, entry4_ds_q : std_ulogic; +signal entry4_pid_d, entry4_pid_q : std_ulogic_vector(0 to 7); +signal entry4_cmpmask_d, entry4_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry4_parity_d, entry4_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry4_sel : std_ulogic_vector(0 to 1); +signal entry4_inval : std_ulogic; +signal entry4_v_muxsel : std_ulogic_vector(0 to 1); +signal entry4_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry4_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry5_epn_d, entry5_epn_q : std_ulogic_vector(0 to 51); +signal entry5_xbit_d, entry5_xbit_q : std_ulogic; +signal entry5_size_d, entry5_size_q : std_ulogic_vector(0 to 2); +signal entry5_v_d, entry5_v_q : std_ulogic; +signal entry5_thdid_d, entry5_thdid_q : std_ulogic_vector(0 to 3); +signal entry5_class_d, entry5_class_q : std_ulogic_vector(0 to 1); +signal entry5_extclass_d, entry5_extclass_q : std_ulogic_vector(0 to 1); +signal entry5_hv_d, entry5_hv_q : std_ulogic; +signal entry5_ds_d, entry5_ds_q : std_ulogic; +signal entry5_pid_d, entry5_pid_q : std_ulogic_vector(0 to 7); +signal entry5_cmpmask_d, entry5_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry5_parity_d, entry5_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry5_sel : std_ulogic_vector(0 to 1); +signal entry5_inval : std_ulogic; +signal entry5_v_muxsel : std_ulogic_vector(0 to 1); +signal entry5_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry5_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry6_epn_d, entry6_epn_q : std_ulogic_vector(0 to 51); +signal entry6_xbit_d, entry6_xbit_q : std_ulogic; +signal entry6_size_d, entry6_size_q : std_ulogic_vector(0 to 2); +signal entry6_v_d, entry6_v_q : std_ulogic; +signal entry6_thdid_d, entry6_thdid_q : std_ulogic_vector(0 to 3); +signal entry6_class_d, entry6_class_q : std_ulogic_vector(0 to 1); +signal entry6_extclass_d, entry6_extclass_q : std_ulogic_vector(0 to 1); +signal entry6_hv_d, entry6_hv_q : std_ulogic; +signal entry6_ds_d, entry6_ds_q : std_ulogic; +signal entry6_pid_d, entry6_pid_q : std_ulogic_vector(0 to 7); +signal entry6_cmpmask_d, entry6_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry6_parity_d, entry6_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry6_sel : std_ulogic_vector(0 to 1); +signal entry6_inval : std_ulogic; +signal entry6_v_muxsel : std_ulogic_vector(0 to 1); +signal entry6_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry6_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry7_epn_d, entry7_epn_q : std_ulogic_vector(0 to 51); +signal entry7_xbit_d, entry7_xbit_q : std_ulogic; +signal entry7_size_d, entry7_size_q : std_ulogic_vector(0 to 2); +signal entry7_v_d, entry7_v_q : std_ulogic; +signal entry7_thdid_d, entry7_thdid_q : std_ulogic_vector(0 to 3); +signal entry7_class_d, entry7_class_q : std_ulogic_vector(0 to 1); +signal entry7_extclass_d, entry7_extclass_q : std_ulogic_vector(0 to 1); +signal entry7_hv_d, entry7_hv_q : std_ulogic; +signal entry7_ds_d, entry7_ds_q : std_ulogic; +signal entry7_pid_d, entry7_pid_q : std_ulogic_vector(0 to 7); +signal entry7_cmpmask_d, entry7_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry7_parity_d, entry7_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry7_sel : std_ulogic_vector(0 to 1); +signal entry7_inval : std_ulogic; +signal entry7_v_muxsel : std_ulogic_vector(0 to 1); +signal entry7_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry7_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry8_epn_d, entry8_epn_q : std_ulogic_vector(0 to 51); +signal entry8_xbit_d, entry8_xbit_q : std_ulogic; +signal entry8_size_d, entry8_size_q : std_ulogic_vector(0 to 2); +signal entry8_v_d, entry8_v_q : std_ulogic; +signal entry8_thdid_d, entry8_thdid_q : std_ulogic_vector(0 to 3); +signal entry8_class_d, entry8_class_q : std_ulogic_vector(0 to 1); +signal entry8_extclass_d, entry8_extclass_q : std_ulogic_vector(0 to 1); +signal entry8_hv_d, entry8_hv_q : std_ulogic; +signal entry8_ds_d, entry8_ds_q : std_ulogic; +signal entry8_pid_d, entry8_pid_q : std_ulogic_vector(0 to 7); +signal entry8_cmpmask_d, entry8_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry8_parity_d, entry8_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry8_sel : std_ulogic_vector(0 to 1); +signal entry8_inval : std_ulogic; +signal entry8_v_muxsel : std_ulogic_vector(0 to 1); +signal entry8_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry8_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry9_epn_d, entry9_epn_q : std_ulogic_vector(0 to 51); +signal entry9_xbit_d, entry9_xbit_q : std_ulogic; +signal entry9_size_d, entry9_size_q : std_ulogic_vector(0 to 2); +signal entry9_v_d, entry9_v_q : std_ulogic; +signal entry9_thdid_d, entry9_thdid_q : std_ulogic_vector(0 to 3); +signal entry9_class_d, entry9_class_q : std_ulogic_vector(0 to 1); +signal entry9_extclass_d, entry9_extclass_q : std_ulogic_vector(0 to 1); +signal entry9_hv_d, entry9_hv_q : std_ulogic; +signal entry9_ds_d, entry9_ds_q : std_ulogic; +signal entry9_pid_d, entry9_pid_q : std_ulogic_vector(0 to 7); +signal entry9_cmpmask_d, entry9_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry9_parity_d, entry9_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry9_sel : std_ulogic_vector(0 to 1); +signal entry9_inval : std_ulogic; +signal entry9_v_muxsel : std_ulogic_vector(0 to 1); +signal entry9_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry9_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry10_epn_d, entry10_epn_q : std_ulogic_vector(0 to 51); +signal entry10_xbit_d, entry10_xbit_q : std_ulogic; +signal entry10_size_d, entry10_size_q : std_ulogic_vector(0 to 2); +signal entry10_v_d, entry10_v_q : std_ulogic; +signal entry10_thdid_d, entry10_thdid_q : std_ulogic_vector(0 to 3); +signal entry10_class_d, entry10_class_q : std_ulogic_vector(0 to 1); +signal entry10_extclass_d, entry10_extclass_q : std_ulogic_vector(0 to 1); +signal entry10_hv_d, entry10_hv_q : std_ulogic; +signal entry10_ds_d, entry10_ds_q : std_ulogic; +signal entry10_pid_d, entry10_pid_q : std_ulogic_vector(0 to 7); +signal entry10_cmpmask_d, entry10_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry10_parity_d, entry10_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry10_sel : std_ulogic_vector(0 to 1); +signal entry10_inval : std_ulogic; +signal entry10_v_muxsel : std_ulogic_vector(0 to 1); +signal entry10_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry10_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry11_epn_d, entry11_epn_q : std_ulogic_vector(0 to 51); +signal entry11_xbit_d, entry11_xbit_q : std_ulogic; +signal entry11_size_d, entry11_size_q : std_ulogic_vector(0 to 2); +signal entry11_v_d, entry11_v_q : std_ulogic; +signal entry11_thdid_d, entry11_thdid_q : std_ulogic_vector(0 to 3); +signal entry11_class_d, entry11_class_q : std_ulogic_vector(0 to 1); +signal entry11_extclass_d, entry11_extclass_q : std_ulogic_vector(0 to 1); +signal entry11_hv_d, entry11_hv_q : std_ulogic; +signal entry11_ds_d, entry11_ds_q : std_ulogic; +signal entry11_pid_d, entry11_pid_q : std_ulogic_vector(0 to 7); +signal entry11_cmpmask_d, entry11_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry11_parity_d, entry11_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry11_sel : std_ulogic_vector(0 to 1); +signal entry11_inval : std_ulogic; +signal entry11_v_muxsel : std_ulogic_vector(0 to 1); +signal entry11_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry11_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry12_epn_d, entry12_epn_q : std_ulogic_vector(0 to 51); +signal entry12_xbit_d, entry12_xbit_q : std_ulogic; +signal entry12_size_d, entry12_size_q : std_ulogic_vector(0 to 2); +signal entry12_v_d, entry12_v_q : std_ulogic; +signal entry12_thdid_d, entry12_thdid_q : std_ulogic_vector(0 to 3); +signal entry12_class_d, entry12_class_q : std_ulogic_vector(0 to 1); +signal entry12_extclass_d, entry12_extclass_q : std_ulogic_vector(0 to 1); +signal entry12_hv_d, entry12_hv_q : std_ulogic; +signal entry12_ds_d, entry12_ds_q : std_ulogic; +signal entry12_pid_d, entry12_pid_q : std_ulogic_vector(0 to 7); +signal entry12_cmpmask_d, entry12_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry12_parity_d, entry12_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry12_sel : std_ulogic_vector(0 to 1); +signal entry12_inval : std_ulogic; +signal entry12_v_muxsel : std_ulogic_vector(0 to 1); +signal entry12_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry12_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry13_epn_d, entry13_epn_q : std_ulogic_vector(0 to 51); +signal entry13_xbit_d, entry13_xbit_q : std_ulogic; +signal entry13_size_d, entry13_size_q : std_ulogic_vector(0 to 2); +signal entry13_v_d, entry13_v_q : std_ulogic; +signal entry13_thdid_d, entry13_thdid_q : std_ulogic_vector(0 to 3); +signal entry13_class_d, entry13_class_q : std_ulogic_vector(0 to 1); +signal entry13_extclass_d, entry13_extclass_q : std_ulogic_vector(0 to 1); +signal entry13_hv_d, entry13_hv_q : std_ulogic; +signal entry13_ds_d, entry13_ds_q : std_ulogic; +signal entry13_pid_d, entry13_pid_q : std_ulogic_vector(0 to 7); +signal entry13_cmpmask_d, entry13_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry13_parity_d, entry13_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry13_sel : std_ulogic_vector(0 to 1); +signal entry13_inval : std_ulogic; +signal entry13_v_muxsel : std_ulogic_vector(0 to 1); +signal entry13_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry13_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry14_epn_d, entry14_epn_q : std_ulogic_vector(0 to 51); +signal entry14_xbit_d, entry14_xbit_q : std_ulogic; +signal entry14_size_d, entry14_size_q : std_ulogic_vector(0 to 2); +signal entry14_v_d, entry14_v_q : std_ulogic; +signal entry14_thdid_d, entry14_thdid_q : std_ulogic_vector(0 to 3); +signal entry14_class_d, entry14_class_q : std_ulogic_vector(0 to 1); +signal entry14_extclass_d, entry14_extclass_q : std_ulogic_vector(0 to 1); +signal entry14_hv_d, entry14_hv_q : std_ulogic; +signal entry14_ds_d, entry14_ds_q : std_ulogic; +signal entry14_pid_d, entry14_pid_q : std_ulogic_vector(0 to 7); +signal entry14_cmpmask_d, entry14_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry14_parity_d, entry14_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry14_sel : std_ulogic_vector(0 to 1); +signal entry14_inval : std_ulogic; +signal entry14_v_muxsel : std_ulogic_vector(0 to 1); +signal entry14_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry14_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry15_epn_d, entry15_epn_q : std_ulogic_vector(0 to 51); +signal entry15_xbit_d, entry15_xbit_q : std_ulogic; +signal entry15_size_d, entry15_size_q : std_ulogic_vector(0 to 2); +signal entry15_v_d, entry15_v_q : std_ulogic; +signal entry15_thdid_d, entry15_thdid_q : std_ulogic_vector(0 to 3); +signal entry15_class_d, entry15_class_q : std_ulogic_vector(0 to 1); +signal entry15_extclass_d, entry15_extclass_q : std_ulogic_vector(0 to 1); +signal entry15_hv_d, entry15_hv_q : std_ulogic; +signal entry15_ds_d, entry15_ds_q : std_ulogic; +signal entry15_pid_d, entry15_pid_q : std_ulogic_vector(0 to 7); +signal entry15_cmpmask_d, entry15_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry15_parity_d, entry15_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry15_sel : std_ulogic_vector(0 to 1); +signal entry15_inval : std_ulogic; +signal entry15_v_muxsel : std_ulogic_vector(0 to 1); +signal entry15_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry15_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal cam_cmp_data_muxsel : std_ulogic_vector(0 to 4); +signal rd_cam_data_muxsel : std_ulogic_vector(0 to 4); +signal cam_cmp_data_np1 : std_ulogic_vector(0 to cam_data_width-1); +signal array_cmp_data_np1 : std_ulogic_vector(0 to array_data_width-1); +signal wr_array_data_bram : std_ulogic_vector(0 to 72); +signal rd_array_data_d_std : std_logic_vector(0 to 72); +signal array_cmp_data_bram_std : std_logic_vector(0 to 55); +signal array_cmp_data_bramp_std : std_logic_vector(66 to 72); +signal rd_array_data_d : std_ulogic_vector(0 to array_data_width-1); +signal rd_array_data_q : std_ulogic_vector(0 to array_data_width-1); +signal cam_cmp_data_d : std_ulogic_vector(0 to cam_data_width-1); +signal cam_cmp_data_q : std_ulogic_vector(0 to cam_data_width-1); +signal cam_cmp_parity_d : std_ulogic_vector(0 to 9); +signal cam_cmp_parity_q : std_ulogic_vector(0 to 9); +signal rd_cam_data_d : std_ulogic_vector(0 to cam_data_width-1); +signal rd_cam_data_q : std_ulogic_vector(0 to cam_data_width-1); +signal entry_match_d : std_ulogic_vector(0 to num_entry-1); +signal entry_match_q : std_ulogic_vector(0 to num_entry-1); +signal match_vec : std_ulogic_vector(0 to num_entry-1); +signal cam_hit_entry_d : std_ulogic_vector(0 to num_entry_log2-1); +signal cam_hit_entry_q : std_ulogic_vector(0 to num_entry_log2-1); +signal cam_hit_d : std_ulogic; +signal cam_hit_q : std_ulogic; +signal toggle_d : std_ulogic; +signal toggle_q : std_ulogic; +signal toggle2x_d : std_ulogic; +signal toggle2x_q : std_ulogic; +begin + +clk <= not nclk.clk; +clk2x <= nclk.clk2x; +rlatch: process (clk) +begin +if(rising_edge(clk)) then +sreset_q <= nclk.sreset; +end if; +end process; +tlatch: process (nclk.clk,sreset_q) +begin +if(rising_edge(nclk.clk)) then +if (sreset_q = '1') then +toggle_q <= '1'; +else +toggle_q <= toggle_d; +end if; +end if; +end process; +flatch: process (nclk.clk2x) +begin +if(rising_edge(nclk.clk2x)) then +toggle2x_q <= toggle2x_d; +gate_fq <= gate_d; +end if; +end process; +toggle_d <= not toggle_q; +toggle2x_d <= toggle_q; +gate_d <= toggle_q xor toggle2x_q; +slatch: process (nclk,sreset_q) +begin +if(rising_edge(nclk.clk)) then +if (sreset_q = '1') then +cam_cmp_data_q <= (others => '0'); +cam_cmp_parity_q <= (others => '0'); +rd_cam_data_q <= (others => '0'); +rd_array_data_q <= (others => '0'); +entry_match_q <= (others => '0'); +cam_hit_entry_q <= (others => '0'); +cam_hit_q <= '0'; +comp_addr_np1_q <= (others => '0'); +rpn_np2_q <= (others => '0'); +attr_np2_q <= (others => '0'); +entry0_size_q <= (others => '0'); +entry0_xbit_q <= '0'; +entry0_epn_q <= (others => '0'); +entry0_class_q <= (others => '0'); +entry0_extclass_q <= (others => '0'); +entry0_hv_q <= '0'; +entry0_ds_q <= '0'; +entry0_thdid_q <= (others => '0'); +entry0_pid_q <= (others => '0'); +entry0_v_q <= '0'; +entry0_parity_q <= (others => '0'); +entry0_cmpmask_q <= (others => '0'); +entry1_size_q <= (others => '0'); +entry1_xbit_q <= '0'; +entry1_epn_q <= (others => '0'); +entry1_class_q <= (others => '0'); +entry1_extclass_q <= (others => '0'); +entry1_hv_q <= '0'; +entry1_ds_q <= '0'; +entry1_thdid_q <= (others => '0'); +entry1_pid_q <= (others => '0'); +entry1_v_q <= '0'; +entry1_parity_q <= (others => '0'); +entry1_cmpmask_q <= (others => '0'); +entry2_size_q <= (others => '0'); +entry2_xbit_q <= '0'; +entry2_epn_q <= (others => '0'); +entry2_class_q <= (others => '0'); +entry2_extclass_q <= (others => '0'); +entry2_hv_q <= '0'; +entry2_ds_q <= '0'; +entry2_thdid_q <= (others => '0'); +entry2_pid_q <= (others => '0'); +entry2_v_q <= '0'; +entry2_parity_q <= (others => '0'); +entry2_cmpmask_q <= (others => '0'); +entry3_size_q <= (others => '0'); +entry3_xbit_q <= '0'; +entry3_epn_q <= (others => '0'); +entry3_class_q <= (others => '0'); +entry3_extclass_q <= (others => '0'); +entry3_hv_q <= '0'; +entry3_ds_q <= '0'; +entry3_thdid_q <= (others => '0'); +entry3_pid_q <= (others => '0'); +entry3_v_q <= '0'; +entry3_parity_q <= (others => '0'); +entry3_cmpmask_q <= (others => '0'); +entry4_size_q <= (others => '0'); +entry4_xbit_q <= '0'; +entry4_epn_q <= (others => '0'); +entry4_class_q <= (others => '0'); +entry4_extclass_q <= (others => '0'); +entry4_hv_q <= '0'; +entry4_ds_q <= '0'; +entry4_thdid_q <= (others => '0'); +entry4_pid_q <= (others => '0'); +entry4_v_q <= '0'; +entry4_parity_q <= (others => '0'); +entry4_cmpmask_q <= (others => '0'); +entry5_size_q <= (others => '0'); +entry5_xbit_q <= '0'; +entry5_epn_q <= (others => '0'); +entry5_class_q <= (others => '0'); +entry5_extclass_q <= (others => '0'); +entry5_hv_q <= '0'; +entry5_ds_q <= '0'; +entry5_thdid_q <= (others => '0'); +entry5_pid_q <= (others => '0'); +entry5_v_q <= '0'; +entry5_parity_q <= (others => '0'); +entry5_cmpmask_q <= (others => '0'); +entry6_size_q <= (others => '0'); +entry6_xbit_q <= '0'; +entry6_epn_q <= (others => '0'); +entry6_class_q <= (others => '0'); +entry6_extclass_q <= (others => '0'); +entry6_hv_q <= '0'; +entry6_ds_q <= '0'; +entry6_thdid_q <= (others => '0'); +entry6_pid_q <= (others => '0'); +entry6_v_q <= '0'; +entry6_parity_q <= (others => '0'); +entry6_cmpmask_q <= (others => '0'); +entry7_size_q <= (others => '0'); +entry7_xbit_q <= '0'; +entry7_epn_q <= (others => '0'); +entry7_class_q <= (others => '0'); +entry7_extclass_q <= (others => '0'); +entry7_hv_q <= '0'; +entry7_ds_q <= '0'; +entry7_thdid_q <= (others => '0'); +entry7_pid_q <= (others => '0'); +entry7_v_q <= '0'; +entry7_parity_q <= (others => '0'); +entry7_cmpmask_q <= (others => '0'); +entry8_size_q <= (others => '0'); +entry8_xbit_q <= '0'; +entry8_epn_q <= (others => '0'); +entry8_class_q <= (others => '0'); +entry8_extclass_q <= (others => '0'); +entry8_hv_q <= '0'; +entry8_ds_q <= '0'; +entry8_thdid_q <= (others => '0'); +entry8_pid_q <= (others => '0'); +entry8_v_q <= '0'; +entry8_parity_q <= (others => '0'); +entry8_cmpmask_q <= (others => '0'); +entry9_size_q <= (others => '0'); +entry9_xbit_q <= '0'; +entry9_epn_q <= (others => '0'); +entry9_class_q <= (others => '0'); +entry9_extclass_q <= (others => '0'); +entry9_hv_q <= '0'; +entry9_ds_q <= '0'; +entry9_thdid_q <= (others => '0'); +entry9_pid_q <= (others => '0'); +entry9_v_q <= '0'; +entry9_parity_q <= (others => '0'); +entry9_cmpmask_q <= (others => '0'); +entry10_size_q <= (others => '0'); +entry10_xbit_q <= '0'; +entry10_epn_q <= (others => '0'); +entry10_class_q <= (others => '0'); +entry10_extclass_q <= (others => '0'); +entry10_hv_q <= '0'; +entry10_ds_q <= '0'; +entry10_thdid_q <= (others => '0'); +entry10_pid_q <= (others => '0'); +entry10_v_q <= '0'; +entry10_parity_q <= (others => '0'); +entry10_cmpmask_q <= (others => '0'); +entry11_size_q <= (others => '0'); +entry11_xbit_q <= '0'; +entry11_epn_q <= (others => '0'); +entry11_class_q <= (others => '0'); +entry11_extclass_q <= (others => '0'); +entry11_hv_q <= '0'; +entry11_ds_q <= '0'; +entry11_thdid_q <= (others => '0'); +entry11_pid_q <= (others => '0'); +entry11_v_q <= '0'; +entry11_parity_q <= (others => '0'); +entry11_cmpmask_q <= (others => '0'); +entry12_size_q <= (others => '0'); +entry12_xbit_q <= '0'; +entry12_epn_q <= (others => '0'); +entry12_class_q <= (others => '0'); +entry12_extclass_q <= (others => '0'); +entry12_hv_q <= '0'; +entry12_ds_q <= '0'; +entry12_thdid_q <= (others => '0'); +entry12_pid_q <= (others => '0'); +entry12_v_q <= '0'; +entry12_parity_q <= (others => '0'); +entry12_cmpmask_q <= (others => '0'); +entry13_size_q <= (others => '0'); +entry13_xbit_q <= '0'; +entry13_epn_q <= (others => '0'); +entry13_class_q <= (others => '0'); +entry13_extclass_q <= (others => '0'); +entry13_hv_q <= '0'; +entry13_ds_q <= '0'; +entry13_thdid_q <= (others => '0'); +entry13_pid_q <= (others => '0'); +entry13_v_q <= '0'; +entry13_parity_q <= (others => '0'); +entry13_cmpmask_q <= (others => '0'); +entry14_size_q <= (others => '0'); +entry14_xbit_q <= '0'; +entry14_epn_q <= (others => '0'); +entry14_class_q <= (others => '0'); +entry14_extclass_q <= (others => '0'); +entry14_hv_q <= '0'; +entry14_ds_q <= '0'; +entry14_thdid_q <= (others => '0'); +entry14_pid_q <= (others => '0'); +entry14_v_q <= '0'; +entry14_parity_q <= (others => '0'); +entry14_cmpmask_q <= (others => '0'); +entry15_size_q <= (others => '0'); +entry15_xbit_q <= '0'; +entry15_epn_q <= (others => '0'); +entry15_class_q <= (others => '0'); +entry15_extclass_q <= (others => '0'); +entry15_hv_q <= '0'; +entry15_ds_q <= '0'; +entry15_thdid_q <= (others => '0'); +entry15_pid_q <= (others => '0'); +entry15_v_q <= '0'; +entry15_parity_q <= (others => '0'); +entry15_cmpmask_q <= (others => '0'); +else +cam_cmp_data_q <= cam_cmp_data_d; +rd_cam_data_q <= rd_cam_data_d; +rd_array_data_q <= rd_array_data_d; +entry_match_q <= entry_match_d; +cam_hit_entry_q <= cam_hit_entry_d; +cam_hit_q <= cam_hit_d; +cam_cmp_parity_q <= cam_cmp_parity_d; +comp_addr_np1_q <= comp_addr_np1_d; +rpn_np2_q <= rpn_np2_d; +attr_np2_q <= attr_np2_d; +entry0_size_q <= entry0_size_d; +entry0_xbit_q <= entry0_xbit_d; +entry0_epn_q <= entry0_epn_d; +entry0_class_q <= entry0_class_d; +entry0_extclass_q <= entry0_extclass_d; +entry0_hv_q <= entry0_hv_d; +entry0_ds_q <= entry0_ds_d; +entry0_thdid_q <= entry0_thdid_d; +entry0_pid_q <= entry0_pid_d; +entry0_v_q <= entry0_v_d; +entry0_parity_q <= entry0_parity_d; +entry0_cmpmask_q <= entry0_cmpmask_d; +entry1_size_q <= entry1_size_d; +entry1_xbit_q <= entry1_xbit_d; +entry1_epn_q <= entry1_epn_d; +entry1_class_q <= entry1_class_d; +entry1_extclass_q <= entry1_extclass_d; +entry1_hv_q <= entry1_hv_d; +entry1_ds_q <= entry1_ds_d; +entry1_thdid_q <= entry1_thdid_d; +entry1_pid_q <= entry1_pid_d; +entry1_v_q <= entry1_v_d; +entry1_parity_q <= entry1_parity_d; +entry1_cmpmask_q <= entry1_cmpmask_d; +entry2_size_q <= entry2_size_d; +entry2_xbit_q <= entry2_xbit_d; +entry2_epn_q <= entry2_epn_d; +entry2_class_q <= entry2_class_d; +entry2_extclass_q <= entry2_extclass_d; +entry2_hv_q <= entry2_hv_d; +entry2_ds_q <= entry2_ds_d; +entry2_thdid_q <= entry2_thdid_d; +entry2_pid_q <= entry2_pid_d; +entry2_v_q <= entry2_v_d; +entry2_parity_q <= entry2_parity_d; +entry2_cmpmask_q <= entry2_cmpmask_d; +entry3_size_q <= entry3_size_d; +entry3_xbit_q <= entry3_xbit_d; +entry3_epn_q <= entry3_epn_d; +entry3_class_q <= entry3_class_d; +entry3_extclass_q <= entry3_extclass_d; +entry3_hv_q <= entry3_hv_d; +entry3_ds_q <= entry3_ds_d; +entry3_thdid_q <= entry3_thdid_d; +entry3_pid_q <= entry3_pid_d; +entry3_v_q <= entry3_v_d; +entry3_parity_q <= entry3_parity_d; +entry3_cmpmask_q <= entry3_cmpmask_d; +entry4_size_q <= entry4_size_d; +entry4_xbit_q <= entry4_xbit_d; +entry4_epn_q <= entry4_epn_d; +entry4_class_q <= entry4_class_d; +entry4_extclass_q <= entry4_extclass_d; +entry4_hv_q <= entry4_hv_d; +entry4_ds_q <= entry4_ds_d; +entry4_thdid_q <= entry4_thdid_d; +entry4_pid_q <= entry4_pid_d; +entry4_v_q <= entry4_v_d; +entry4_parity_q <= entry4_parity_d; +entry4_cmpmask_q <= entry4_cmpmask_d; +entry5_size_q <= entry5_size_d; +entry5_xbit_q <= entry5_xbit_d; +entry5_epn_q <= entry5_epn_d; +entry5_class_q <= entry5_class_d; +entry5_extclass_q <= entry5_extclass_d; +entry5_hv_q <= entry5_hv_d; +entry5_ds_q <= entry5_ds_d; +entry5_thdid_q <= entry5_thdid_d; +entry5_pid_q <= entry5_pid_d; +entry5_v_q <= entry5_v_d; +entry5_parity_q <= entry5_parity_d; +entry5_cmpmask_q <= entry5_cmpmask_d; +entry6_size_q <= entry6_size_d; +entry6_xbit_q <= entry6_xbit_d; +entry6_epn_q <= entry6_epn_d; +entry6_class_q <= entry6_class_d; +entry6_extclass_q <= entry6_extclass_d; +entry6_hv_q <= entry6_hv_d; +entry6_ds_q <= entry6_ds_d; +entry6_thdid_q <= entry6_thdid_d; +entry6_pid_q <= entry6_pid_d; +entry6_v_q <= entry6_v_d; +entry6_parity_q <= entry6_parity_d; +entry6_cmpmask_q <= entry6_cmpmask_d; +entry7_size_q <= entry7_size_d; +entry7_xbit_q <= entry7_xbit_d; +entry7_epn_q <= entry7_epn_d; +entry7_class_q <= entry7_class_d; +entry7_extclass_q <= entry7_extclass_d; +entry7_hv_q <= entry7_hv_d; +entry7_ds_q <= entry7_ds_d; +entry7_thdid_q <= entry7_thdid_d; +entry7_pid_q <= entry7_pid_d; +entry7_v_q <= entry7_v_d; +entry7_parity_q <= entry7_parity_d; +entry7_cmpmask_q <= entry7_cmpmask_d; +entry8_size_q <= entry8_size_d; +entry8_xbit_q <= entry8_xbit_d; +entry8_epn_q <= entry8_epn_d; +entry8_class_q <= entry8_class_d; +entry8_extclass_q <= entry8_extclass_d; +entry8_hv_q <= entry8_hv_d; +entry8_ds_q <= entry8_ds_d; +entry8_thdid_q <= entry8_thdid_d; +entry8_pid_q <= entry8_pid_d; +entry8_v_q <= entry8_v_d; +entry8_parity_q <= entry8_parity_d; +entry8_cmpmask_q <= entry8_cmpmask_d; +entry9_size_q <= entry9_size_d; +entry9_xbit_q <= entry9_xbit_d; +entry9_epn_q <= entry9_epn_d; +entry9_class_q <= entry9_class_d; +entry9_extclass_q <= entry9_extclass_d; +entry9_hv_q <= entry9_hv_d; +entry9_ds_q <= entry9_ds_d; +entry9_thdid_q <= entry9_thdid_d; +entry9_pid_q <= entry9_pid_d; +entry9_v_q <= entry9_v_d; +entry9_parity_q <= entry9_parity_d; +entry9_cmpmask_q <= entry9_cmpmask_d; +entry10_size_q <= entry10_size_d; +entry10_xbit_q <= entry10_xbit_d; +entry10_epn_q <= entry10_epn_d; +entry10_class_q <= entry10_class_d; +entry10_extclass_q <= entry10_extclass_d; +entry10_hv_q <= entry10_hv_d; +entry10_ds_q <= entry10_ds_d; +entry10_thdid_q <= entry10_thdid_d; +entry10_pid_q <= entry10_pid_d; +entry10_v_q <= entry10_v_d; +entry10_parity_q <= entry10_parity_d; +entry10_cmpmask_q <= entry10_cmpmask_d; +entry11_size_q <= entry11_size_d; +entry11_xbit_q <= entry11_xbit_d; +entry11_epn_q <= entry11_epn_d; +entry11_class_q <= entry11_class_d; +entry11_extclass_q <= entry11_extclass_d; +entry11_hv_q <= entry11_hv_d; +entry11_ds_q <= entry11_ds_d; +entry11_thdid_q <= entry11_thdid_d; +entry11_pid_q <= entry11_pid_d; +entry11_v_q <= entry11_v_d; +entry11_parity_q <= entry11_parity_d; +entry11_cmpmask_q <= entry11_cmpmask_d; +entry12_size_q <= entry12_size_d; +entry12_xbit_q <= entry12_xbit_d; +entry12_epn_q <= entry12_epn_d; +entry12_class_q <= entry12_class_d; +entry12_extclass_q <= entry12_extclass_d; +entry12_hv_q <= entry12_hv_d; +entry12_ds_q <= entry12_ds_d; +entry12_thdid_q <= entry12_thdid_d; +entry12_pid_q <= entry12_pid_d; +entry12_v_q <= entry12_v_d; +entry12_parity_q <= entry12_parity_d; +entry12_cmpmask_q <= entry12_cmpmask_d; +entry13_size_q <= entry13_size_d; +entry13_xbit_q <= entry13_xbit_d; +entry13_epn_q <= entry13_epn_d; +entry13_class_q <= entry13_class_d; +entry13_extclass_q <= entry13_extclass_d; +entry13_hv_q <= entry13_hv_d; +entry13_ds_q <= entry13_ds_d; +entry13_thdid_q <= entry13_thdid_d; +entry13_pid_q <= entry13_pid_d; +entry13_v_q <= entry13_v_d; +entry13_parity_q <= entry13_parity_d; +entry13_cmpmask_q <= entry13_cmpmask_d; +entry14_size_q <= entry14_size_d; +entry14_xbit_q <= entry14_xbit_d; +entry14_epn_q <= entry14_epn_d; +entry14_class_q <= entry14_class_d; +entry14_extclass_q <= entry14_extclass_d; +entry14_hv_q <= entry14_hv_d; +entry14_ds_q <= entry14_ds_d; +entry14_thdid_q <= entry14_thdid_d; +entry14_pid_q <= entry14_pid_d; +entry14_v_q <= entry14_v_d; +entry14_parity_q <= entry14_parity_d; +entry14_cmpmask_q <= entry14_cmpmask_d; +entry15_size_q <= entry15_size_d; +entry15_xbit_q <= entry15_xbit_d; +entry15_epn_q <= entry15_epn_d; +entry15_class_q <= entry15_class_d; +entry15_extclass_q <= entry15_extclass_d; +entry15_hv_q <= entry15_hv_d; +entry15_ds_q <= entry15_ds_d; +entry15_thdid_q <= entry15_thdid_d; +entry15_pid_q <= entry15_pid_d; +entry15_v_q <= entry15_v_d; +entry15_parity_q <= entry15_parity_d; +entry15_cmpmask_q <= entry15_cmpmask_d; +end if; +end if; +end process; +comp_addr_np1_d <= comp_addr(52-rpn_width to 51); +cam_hit_d <= '1' when (match_vec /= "0000000000000000" and comp_request='1') else '0'; +cam_hit_entry_d <= "0001" when match_vec(0 to 1)="01" else + "0010" when match_vec(0 to 2)="001" else + "0011" when match_vec(0 to 3)="0001" else + "0100" when match_vec(0 to 4)="00001" else + "0101" when match_vec(0 to 5)="000001" else + "0110" when match_vec(0 to 6)="0000001" else + "0111" when match_vec(0 to 7)="00000001" else + "1000" when match_vec(0 to 8)="000000001" else + "1001" when match_vec(0 to 9)="0000000001" else + "1010" when match_vec(0 to 10)="00000000001" else + "1011" when match_vec(0 to 11)="000000000001" else + "1100" when match_vec(0 to 12)="0000000000001" else + "1101" when match_vec(0 to 13)="00000000000001" else + "1110" when match_vec(0 to 14)="000000000000001" else + "1111" when match_vec(0 to 15)="0000000000000001" else + "0000"; +entry_match_d <= match_vec when (comp_request='1') else (others => '0'); +wr_entry0_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="0000")) else '0'; +wr_entry0_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="0000")) else '0'; +with wr_entry0_sel(0) select + entry0_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry0_epn_q(0 to 31) when others; +with wr_entry0_sel(0) select + entry0_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry0_epn_q(32 to 51) when others; +with wr_entry0_sel(0) select + entry0_xbit_d <= wr_cam_data(52) when '1', + entry0_xbit_q when others; +with wr_entry0_sel(0) select + entry0_size_d <= wr_cam_data(53 to 55) when '1', + entry0_size_q(0 to 2) when others; +with wr_entry0_sel(0) select + entry0_class_d <= wr_cam_data(61 to 62) when '1', + entry0_class_q(0 to 1) when others; +with wr_entry0_sel(1) select + entry0_extclass_d <= wr_cam_data(63 to 64) when '1', + entry0_extclass_q(0 to 1) when others; +with wr_entry0_sel(1) select + entry0_hv_d <= wr_cam_data(65) when '1', + entry0_hv_q when others; +with wr_entry0_sel(1) select + entry0_ds_d <= wr_cam_data(66) when '1', + entry0_ds_q when others; +with wr_entry0_sel(1) select + entry0_pid_d <= wr_cam_data(67 to 74) when '1', + entry0_pid_q(0 to 7) when others; +with wr_entry0_sel(0) select + entry0_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry0_cmpmask_q when others; +with wr_entry0_sel(0) select + entry0_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry0_parity_q(0 to 3) when others; +with wr_entry0_sel(0) select + entry0_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry0_parity_q(4 to 6) when others; +with wr_entry0_sel(0) select + entry0_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry0_parity_q(7) when others; +with wr_entry0_sel(1) select + entry0_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry0_parity_q(8) when others; +with wr_entry0_sel(1) select + entry0_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry0_parity_q(9) when others; +wr_entry1_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="0001")) else '0'; +wr_entry1_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="0001")) else '0'; +with wr_entry1_sel(0) select + entry1_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry1_epn_q(0 to 31) when others; +with wr_entry1_sel(0) select + entry1_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry1_epn_q(32 to 51) when others; +with wr_entry1_sel(0) select + entry1_xbit_d <= wr_cam_data(52) when '1', + entry1_xbit_q when others; +with wr_entry1_sel(0) select + entry1_size_d <= wr_cam_data(53 to 55) when '1', + entry1_size_q(0 to 2) when others; +with wr_entry1_sel(0) select + entry1_class_d <= wr_cam_data(61 to 62) when '1', + entry1_class_q(0 to 1) when others; +with wr_entry1_sel(1) select + entry1_extclass_d <= wr_cam_data(63 to 64) when '1', + entry1_extclass_q(0 to 1) when others; +with wr_entry1_sel(1) select + entry1_hv_d <= wr_cam_data(65) when '1', + entry1_hv_q when others; +with wr_entry1_sel(1) select + entry1_ds_d <= wr_cam_data(66) when '1', + entry1_ds_q when others; +with wr_entry1_sel(1) select + entry1_pid_d <= wr_cam_data(67 to 74) when '1', + entry1_pid_q(0 to 7) when others; +with wr_entry1_sel(0) select + entry1_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry1_cmpmask_q when others; +with wr_entry1_sel(0) select + entry1_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry1_parity_q(0 to 3) when others; +with wr_entry1_sel(0) select + entry1_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry1_parity_q(4 to 6) when others; +with wr_entry1_sel(0) select + entry1_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry1_parity_q(7) when others; +with wr_entry1_sel(1) select + entry1_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry1_parity_q(8) when others; +with wr_entry1_sel(1) select + entry1_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry1_parity_q(9) when others; +wr_entry2_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="0010")) else '0'; +wr_entry2_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="0010")) else '0'; +with wr_entry2_sel(0) select + entry2_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry2_epn_q(0 to 31) when others; +with wr_entry2_sel(0) select + entry2_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry2_epn_q(32 to 51) when others; +with wr_entry2_sel(0) select + entry2_xbit_d <= wr_cam_data(52) when '1', + entry2_xbit_q when others; +with wr_entry2_sel(0) select + entry2_size_d <= wr_cam_data(53 to 55) when '1', + entry2_size_q(0 to 2) when others; +with wr_entry2_sel(0) select + entry2_class_d <= wr_cam_data(61 to 62) when '1', + entry2_class_q(0 to 1) when others; +with wr_entry2_sel(1) select + entry2_extclass_d <= wr_cam_data(63 to 64) when '1', + entry2_extclass_q(0 to 1) when others; +with wr_entry2_sel(1) select + entry2_hv_d <= wr_cam_data(65) when '1', + entry2_hv_q when others; +with wr_entry2_sel(1) select + entry2_ds_d <= wr_cam_data(66) when '1', + entry2_ds_q when others; +with wr_entry2_sel(1) select + entry2_pid_d <= wr_cam_data(67 to 74) when '1', + entry2_pid_q(0 to 7) when others; +with wr_entry2_sel(0) select + entry2_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry2_cmpmask_q when others; +with wr_entry2_sel(0) select + entry2_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry2_parity_q(0 to 3) when others; +with wr_entry2_sel(0) select + entry2_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry2_parity_q(4 to 6) when others; +with wr_entry2_sel(0) select + entry2_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry2_parity_q(7) when others; +with wr_entry2_sel(1) select + entry2_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry2_parity_q(8) when others; +with wr_entry2_sel(1) select + entry2_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry2_parity_q(9) when others; +wr_entry3_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="0011")) else '0'; +wr_entry3_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="0011")) else '0'; +with wr_entry3_sel(0) select + entry3_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry3_epn_q(0 to 31) when others; +with wr_entry3_sel(0) select + entry3_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry3_epn_q(32 to 51) when others; +with wr_entry3_sel(0) select + entry3_xbit_d <= wr_cam_data(52) when '1', + entry3_xbit_q when others; +with wr_entry3_sel(0) select + entry3_size_d <= wr_cam_data(53 to 55) when '1', + entry3_size_q(0 to 2) when others; +with wr_entry3_sel(0) select + entry3_class_d <= wr_cam_data(61 to 62) when '1', + entry3_class_q(0 to 1) when others; +with wr_entry3_sel(1) select + entry3_extclass_d <= wr_cam_data(63 to 64) when '1', + entry3_extclass_q(0 to 1) when others; +with wr_entry3_sel(1) select + entry3_hv_d <= wr_cam_data(65) when '1', + entry3_hv_q when others; +with wr_entry3_sel(1) select + entry3_ds_d <= wr_cam_data(66) when '1', + entry3_ds_q when others; +with wr_entry3_sel(1) select + entry3_pid_d <= wr_cam_data(67 to 74) when '1', + entry3_pid_q(0 to 7) when others; +with wr_entry3_sel(0) select + entry3_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry3_cmpmask_q when others; +with wr_entry3_sel(0) select + entry3_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry3_parity_q(0 to 3) when others; +with wr_entry3_sel(0) select + entry3_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry3_parity_q(4 to 6) when others; +with wr_entry3_sel(0) select + entry3_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry3_parity_q(7) when others; +with wr_entry3_sel(1) select + entry3_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry3_parity_q(8) when others; +with wr_entry3_sel(1) select + entry3_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry3_parity_q(9) when others; +wr_entry4_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="0100")) else '0'; +wr_entry4_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="0100")) else '0'; +with wr_entry4_sel(0) select + entry4_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry4_epn_q(0 to 31) when others; +with wr_entry4_sel(0) select + entry4_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry4_epn_q(32 to 51) when others; +with wr_entry4_sel(0) select + entry4_xbit_d <= wr_cam_data(52) when '1', + entry4_xbit_q when others; +with wr_entry4_sel(0) select + entry4_size_d <= wr_cam_data(53 to 55) when '1', + entry4_size_q(0 to 2) when others; +with wr_entry4_sel(0) select + entry4_class_d <= wr_cam_data(61 to 62) when '1', + entry4_class_q(0 to 1) when others; +with wr_entry4_sel(1) select + entry4_extclass_d <= wr_cam_data(63 to 64) when '1', + entry4_extclass_q(0 to 1) when others; +with wr_entry4_sel(1) select + entry4_hv_d <= wr_cam_data(65) when '1', + entry4_hv_q when others; +with wr_entry4_sel(1) select + entry4_ds_d <= wr_cam_data(66) when '1', + entry4_ds_q when others; +with wr_entry4_sel(1) select + entry4_pid_d <= wr_cam_data(67 to 74) when '1', + entry4_pid_q(0 to 7) when others; +with wr_entry4_sel(0) select + entry4_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry4_cmpmask_q when others; +with wr_entry4_sel(0) select + entry4_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry4_parity_q(0 to 3) when others; +with wr_entry4_sel(0) select + entry4_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry4_parity_q(4 to 6) when others; +with wr_entry4_sel(0) select + entry4_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry4_parity_q(7) when others; +with wr_entry4_sel(1) select + entry4_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry4_parity_q(8) when others; +with wr_entry4_sel(1) select + entry4_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry4_parity_q(9) when others; +wr_entry5_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="0101")) else '0'; +wr_entry5_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="0101")) else '0'; +with wr_entry5_sel(0) select + entry5_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry5_epn_q(0 to 31) when others; +with wr_entry5_sel(0) select + entry5_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry5_epn_q(32 to 51) when others; +with wr_entry5_sel(0) select + entry5_xbit_d <= wr_cam_data(52) when '1', + entry5_xbit_q when others; +with wr_entry5_sel(0) select + entry5_size_d <= wr_cam_data(53 to 55) when '1', + entry5_size_q(0 to 2) when others; +with wr_entry5_sel(0) select + entry5_class_d <= wr_cam_data(61 to 62) when '1', + entry5_class_q(0 to 1) when others; +with wr_entry5_sel(1) select + entry5_extclass_d <= wr_cam_data(63 to 64) when '1', + entry5_extclass_q(0 to 1) when others; +with wr_entry5_sel(1) select + entry5_hv_d <= wr_cam_data(65) when '1', + entry5_hv_q when others; +with wr_entry5_sel(1) select + entry5_ds_d <= wr_cam_data(66) when '1', + entry5_ds_q when others; +with wr_entry5_sel(1) select + entry5_pid_d <= wr_cam_data(67 to 74) when '1', + entry5_pid_q(0 to 7) when others; +with wr_entry5_sel(0) select + entry5_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry5_cmpmask_q when others; +with wr_entry5_sel(0) select + entry5_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry5_parity_q(0 to 3) when others; +with wr_entry5_sel(0) select + entry5_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry5_parity_q(4 to 6) when others; +with wr_entry5_sel(0) select + entry5_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry5_parity_q(7) when others; +with wr_entry5_sel(1) select + entry5_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry5_parity_q(8) when others; +with wr_entry5_sel(1) select + entry5_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry5_parity_q(9) when others; +wr_entry6_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="0110")) else '0'; +wr_entry6_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="0110")) else '0'; +with wr_entry6_sel(0) select + entry6_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry6_epn_q(0 to 31) when others; +with wr_entry6_sel(0) select + entry6_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry6_epn_q(32 to 51) when others; +with wr_entry6_sel(0) select + entry6_xbit_d <= wr_cam_data(52) when '1', + entry6_xbit_q when others; +with wr_entry6_sel(0) select + entry6_size_d <= wr_cam_data(53 to 55) when '1', + entry6_size_q(0 to 2) when others; +with wr_entry6_sel(0) select + entry6_class_d <= wr_cam_data(61 to 62) when '1', + entry6_class_q(0 to 1) when others; +with wr_entry6_sel(1) select + entry6_extclass_d <= wr_cam_data(63 to 64) when '1', + entry6_extclass_q(0 to 1) when others; +with wr_entry6_sel(1) select + entry6_hv_d <= wr_cam_data(65) when '1', + entry6_hv_q when others; +with wr_entry6_sel(1) select + entry6_ds_d <= wr_cam_data(66) when '1', + entry6_ds_q when others; +with wr_entry6_sel(1) select + entry6_pid_d <= wr_cam_data(67 to 74) when '1', + entry6_pid_q(0 to 7) when others; +with wr_entry6_sel(0) select + entry6_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry6_cmpmask_q when others; +with wr_entry6_sel(0) select + entry6_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry6_parity_q(0 to 3) when others; +with wr_entry6_sel(0) select + entry6_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry6_parity_q(4 to 6) when others; +with wr_entry6_sel(0) select + entry6_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry6_parity_q(7) when others; +with wr_entry6_sel(1) select + entry6_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry6_parity_q(8) when others; +with wr_entry6_sel(1) select + entry6_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry6_parity_q(9) when others; +wr_entry7_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="0111")) else '0'; +wr_entry7_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="0111")) else '0'; +with wr_entry7_sel(0) select + entry7_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry7_epn_q(0 to 31) when others; +with wr_entry7_sel(0) select + entry7_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry7_epn_q(32 to 51) when others; +with wr_entry7_sel(0) select + entry7_xbit_d <= wr_cam_data(52) when '1', + entry7_xbit_q when others; +with wr_entry7_sel(0) select + entry7_size_d <= wr_cam_data(53 to 55) when '1', + entry7_size_q(0 to 2) when others; +with wr_entry7_sel(0) select + entry7_class_d <= wr_cam_data(61 to 62) when '1', + entry7_class_q(0 to 1) when others; +with wr_entry7_sel(1) select + entry7_extclass_d <= wr_cam_data(63 to 64) when '1', + entry7_extclass_q(0 to 1) when others; +with wr_entry7_sel(1) select + entry7_hv_d <= wr_cam_data(65) when '1', + entry7_hv_q when others; +with wr_entry7_sel(1) select + entry7_ds_d <= wr_cam_data(66) when '1', + entry7_ds_q when others; +with wr_entry7_sel(1) select + entry7_pid_d <= wr_cam_data(67 to 74) when '1', + entry7_pid_q(0 to 7) when others; +with wr_entry7_sel(0) select + entry7_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry7_cmpmask_q when others; +with wr_entry7_sel(0) select + entry7_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry7_parity_q(0 to 3) when others; +with wr_entry7_sel(0) select + entry7_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry7_parity_q(4 to 6) when others; +with wr_entry7_sel(0) select + entry7_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry7_parity_q(7) when others; +with wr_entry7_sel(1) select + entry7_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry7_parity_q(8) when others; +with wr_entry7_sel(1) select + entry7_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry7_parity_q(9) when others; +wr_entry8_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="1000")) else '0'; +wr_entry8_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="1000")) else '0'; +with wr_entry8_sel(0) select + entry8_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry8_epn_q(0 to 31) when others; +with wr_entry8_sel(0) select + entry8_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry8_epn_q(32 to 51) when others; +with wr_entry8_sel(0) select + entry8_xbit_d <= wr_cam_data(52) when '1', + entry8_xbit_q when others; +with wr_entry8_sel(0) select + entry8_size_d <= wr_cam_data(53 to 55) when '1', + entry8_size_q(0 to 2) when others; +with wr_entry8_sel(0) select + entry8_class_d <= wr_cam_data(61 to 62) when '1', + entry8_class_q(0 to 1) when others; +with wr_entry8_sel(1) select + entry8_extclass_d <= wr_cam_data(63 to 64) when '1', + entry8_extclass_q(0 to 1) when others; +with wr_entry8_sel(1) select + entry8_hv_d <= wr_cam_data(65) when '1', + entry8_hv_q when others; +with wr_entry8_sel(1) select + entry8_ds_d <= wr_cam_data(66) when '1', + entry8_ds_q when others; +with wr_entry8_sel(1) select + entry8_pid_d <= wr_cam_data(67 to 74) when '1', + entry8_pid_q(0 to 7) when others; +with wr_entry8_sel(0) select + entry8_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry8_cmpmask_q when others; +with wr_entry8_sel(0) select + entry8_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry8_parity_q(0 to 3) when others; +with wr_entry8_sel(0) select + entry8_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry8_parity_q(4 to 6) when others; +with wr_entry8_sel(0) select + entry8_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry8_parity_q(7) when others; +with wr_entry8_sel(1) select + entry8_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry8_parity_q(8) when others; +with wr_entry8_sel(1) select + entry8_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry8_parity_q(9) when others; +wr_entry9_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="1001")) else '0'; +wr_entry9_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="1001")) else '0'; +with wr_entry9_sel(0) select + entry9_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry9_epn_q(0 to 31) when others; +with wr_entry9_sel(0) select + entry9_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry9_epn_q(32 to 51) when others; +with wr_entry9_sel(0) select + entry9_xbit_d <= wr_cam_data(52) when '1', + entry9_xbit_q when others; +with wr_entry9_sel(0) select + entry9_size_d <= wr_cam_data(53 to 55) when '1', + entry9_size_q(0 to 2) when others; +with wr_entry9_sel(0) select + entry9_class_d <= wr_cam_data(61 to 62) when '1', + entry9_class_q(0 to 1) when others; +with wr_entry9_sel(1) select + entry9_extclass_d <= wr_cam_data(63 to 64) when '1', + entry9_extclass_q(0 to 1) when others; +with wr_entry9_sel(1) select + entry9_hv_d <= wr_cam_data(65) when '1', + entry9_hv_q when others; +with wr_entry9_sel(1) select + entry9_ds_d <= wr_cam_data(66) when '1', + entry9_ds_q when others; +with wr_entry9_sel(1) select + entry9_pid_d <= wr_cam_data(67 to 74) when '1', + entry9_pid_q(0 to 7) when others; +with wr_entry9_sel(0) select + entry9_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry9_cmpmask_q when others; +with wr_entry9_sel(0) select + entry9_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry9_parity_q(0 to 3) when others; +with wr_entry9_sel(0) select + entry9_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry9_parity_q(4 to 6) when others; +with wr_entry9_sel(0) select + entry9_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry9_parity_q(7) when others; +with wr_entry9_sel(1) select + entry9_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry9_parity_q(8) when others; +with wr_entry9_sel(1) select + entry9_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry9_parity_q(9) when others; +wr_entry10_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="1010")) else '0'; +wr_entry10_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="1010")) else '0'; +with wr_entry10_sel(0) select + entry10_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry10_epn_q(0 to 31) when others; +with wr_entry10_sel(0) select + entry10_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry10_epn_q(32 to 51) when others; +with wr_entry10_sel(0) select + entry10_xbit_d <= wr_cam_data(52) when '1', + entry10_xbit_q when others; +with wr_entry10_sel(0) select + entry10_size_d <= wr_cam_data(53 to 55) when '1', + entry10_size_q(0 to 2) when others; +with wr_entry10_sel(0) select + entry10_class_d <= wr_cam_data(61 to 62) when '1', + entry10_class_q(0 to 1) when others; +with wr_entry10_sel(1) select + entry10_extclass_d <= wr_cam_data(63 to 64) when '1', + entry10_extclass_q(0 to 1) when others; +with wr_entry10_sel(1) select + entry10_hv_d <= wr_cam_data(65) when '1', + entry10_hv_q when others; +with wr_entry10_sel(1) select + entry10_ds_d <= wr_cam_data(66) when '1', + entry10_ds_q when others; +with wr_entry10_sel(1) select + entry10_pid_d <= wr_cam_data(67 to 74) when '1', + entry10_pid_q(0 to 7) when others; +with wr_entry10_sel(0) select + entry10_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry10_cmpmask_q when others; +with wr_entry10_sel(0) select + entry10_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry10_parity_q(0 to 3) when others; +with wr_entry10_sel(0) select + entry10_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry10_parity_q(4 to 6) when others; +with wr_entry10_sel(0) select + entry10_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry10_parity_q(7) when others; +with wr_entry10_sel(1) select + entry10_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry10_parity_q(8) when others; +with wr_entry10_sel(1) select + entry10_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry10_parity_q(9) when others; +wr_entry11_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="1011")) else '0'; +wr_entry11_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="1011")) else '0'; +with wr_entry11_sel(0) select + entry11_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry11_epn_q(0 to 31) when others; +with wr_entry11_sel(0) select + entry11_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry11_epn_q(32 to 51) when others; +with wr_entry11_sel(0) select + entry11_xbit_d <= wr_cam_data(52) when '1', + entry11_xbit_q when others; +with wr_entry11_sel(0) select + entry11_size_d <= wr_cam_data(53 to 55) when '1', + entry11_size_q(0 to 2) when others; +with wr_entry11_sel(0) select + entry11_class_d <= wr_cam_data(61 to 62) when '1', + entry11_class_q(0 to 1) when others; +with wr_entry11_sel(1) select + entry11_extclass_d <= wr_cam_data(63 to 64) when '1', + entry11_extclass_q(0 to 1) when others; +with wr_entry11_sel(1) select + entry11_hv_d <= wr_cam_data(65) when '1', + entry11_hv_q when others; +with wr_entry11_sel(1) select + entry11_ds_d <= wr_cam_data(66) when '1', + entry11_ds_q when others; +with wr_entry11_sel(1) select + entry11_pid_d <= wr_cam_data(67 to 74) when '1', + entry11_pid_q(0 to 7) when others; +with wr_entry11_sel(0) select + entry11_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry11_cmpmask_q when others; +with wr_entry11_sel(0) select + entry11_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry11_parity_q(0 to 3) when others; +with wr_entry11_sel(0) select + entry11_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry11_parity_q(4 to 6) when others; +with wr_entry11_sel(0) select + entry11_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry11_parity_q(7) when others; +with wr_entry11_sel(1) select + entry11_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry11_parity_q(8) when others; +with wr_entry11_sel(1) select + entry11_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry11_parity_q(9) when others; +wr_entry12_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="1100")) else '0'; +wr_entry12_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="1100")) else '0'; +with wr_entry12_sel(0) select + entry12_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry12_epn_q(0 to 31) when others; +with wr_entry12_sel(0) select + entry12_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry12_epn_q(32 to 51) when others; +with wr_entry12_sel(0) select + entry12_xbit_d <= wr_cam_data(52) when '1', + entry12_xbit_q when others; +with wr_entry12_sel(0) select + entry12_size_d <= wr_cam_data(53 to 55) when '1', + entry12_size_q(0 to 2) when others; +with wr_entry12_sel(0) select + entry12_class_d <= wr_cam_data(61 to 62) when '1', + entry12_class_q(0 to 1) when others; +with wr_entry12_sel(1) select + entry12_extclass_d <= wr_cam_data(63 to 64) when '1', + entry12_extclass_q(0 to 1) when others; +with wr_entry12_sel(1) select + entry12_hv_d <= wr_cam_data(65) when '1', + entry12_hv_q when others; +with wr_entry12_sel(1) select + entry12_ds_d <= wr_cam_data(66) when '1', + entry12_ds_q when others; +with wr_entry12_sel(1) select + entry12_pid_d <= wr_cam_data(67 to 74) when '1', + entry12_pid_q(0 to 7) when others; +with wr_entry12_sel(0) select + entry12_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry12_cmpmask_q when others; +with wr_entry12_sel(0) select + entry12_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry12_parity_q(0 to 3) when others; +with wr_entry12_sel(0) select + entry12_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry12_parity_q(4 to 6) when others; +with wr_entry12_sel(0) select + entry12_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry12_parity_q(7) when others; +with wr_entry12_sel(1) select + entry12_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry12_parity_q(8) when others; +with wr_entry12_sel(1) select + entry12_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry12_parity_q(9) when others; +wr_entry13_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="1101")) else '0'; +wr_entry13_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="1101")) else '0'; +with wr_entry13_sel(0) select + entry13_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry13_epn_q(0 to 31) when others; +with wr_entry13_sel(0) select + entry13_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry13_epn_q(32 to 51) when others; +with wr_entry13_sel(0) select + entry13_xbit_d <= wr_cam_data(52) when '1', + entry13_xbit_q when others; +with wr_entry13_sel(0) select + entry13_size_d <= wr_cam_data(53 to 55) when '1', + entry13_size_q(0 to 2) when others; +with wr_entry13_sel(0) select + entry13_class_d <= wr_cam_data(61 to 62) when '1', + entry13_class_q(0 to 1) when others; +with wr_entry13_sel(1) select + entry13_extclass_d <= wr_cam_data(63 to 64) when '1', + entry13_extclass_q(0 to 1) when others; +with wr_entry13_sel(1) select + entry13_hv_d <= wr_cam_data(65) when '1', + entry13_hv_q when others; +with wr_entry13_sel(1) select + entry13_ds_d <= wr_cam_data(66) when '1', + entry13_ds_q when others; +with wr_entry13_sel(1) select + entry13_pid_d <= wr_cam_data(67 to 74) when '1', + entry13_pid_q(0 to 7) when others; +with wr_entry13_sel(0) select + entry13_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry13_cmpmask_q when others; +with wr_entry13_sel(0) select + entry13_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry13_parity_q(0 to 3) when others; +with wr_entry13_sel(0) select + entry13_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry13_parity_q(4 to 6) when others; +with wr_entry13_sel(0) select + entry13_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry13_parity_q(7) when others; +with wr_entry13_sel(1) select + entry13_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry13_parity_q(8) when others; +with wr_entry13_sel(1) select + entry13_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry13_parity_q(9) when others; +wr_entry14_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="1110")) else '0'; +wr_entry14_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="1110")) else '0'; +with wr_entry14_sel(0) select + entry14_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry14_epn_q(0 to 31) when others; +with wr_entry14_sel(0) select + entry14_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry14_epn_q(32 to 51) when others; +with wr_entry14_sel(0) select + entry14_xbit_d <= wr_cam_data(52) when '1', + entry14_xbit_q when others; +with wr_entry14_sel(0) select + entry14_size_d <= wr_cam_data(53 to 55) when '1', + entry14_size_q(0 to 2) when others; +with wr_entry14_sel(0) select + entry14_class_d <= wr_cam_data(61 to 62) when '1', + entry14_class_q(0 to 1) when others; +with wr_entry14_sel(1) select + entry14_extclass_d <= wr_cam_data(63 to 64) when '1', + entry14_extclass_q(0 to 1) when others; +with wr_entry14_sel(1) select + entry14_hv_d <= wr_cam_data(65) when '1', + entry14_hv_q when others; +with wr_entry14_sel(1) select + entry14_ds_d <= wr_cam_data(66) when '1', + entry14_ds_q when others; +with wr_entry14_sel(1) select + entry14_pid_d <= wr_cam_data(67 to 74) when '1', + entry14_pid_q(0 to 7) when others; +with wr_entry14_sel(0) select + entry14_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry14_cmpmask_q when others; +with wr_entry14_sel(0) select + entry14_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry14_parity_q(0 to 3) when others; +with wr_entry14_sel(0) select + entry14_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry14_parity_q(4 to 6) when others; +with wr_entry14_sel(0) select + entry14_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry14_parity_q(7) when others; +with wr_entry14_sel(1) select + entry14_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry14_parity_q(8) when others; +with wr_entry14_sel(1) select + entry14_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry14_parity_q(9) when others; +wr_entry15_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="1111")) else '0'; +wr_entry15_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="1111")) else '0'; +with wr_entry15_sel(0) select + entry15_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry15_epn_q(0 to 31) when others; +with wr_entry15_sel(0) select + entry15_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry15_epn_q(32 to 51) when others; +with wr_entry15_sel(0) select + entry15_xbit_d <= wr_cam_data(52) when '1', + entry15_xbit_q when others; +with wr_entry15_sel(0) select + entry15_size_d <= wr_cam_data(53 to 55) when '1', + entry15_size_q(0 to 2) when others; +with wr_entry15_sel(0) select + entry15_class_d <= wr_cam_data(61 to 62) when '1', + entry15_class_q(0 to 1) when others; +with wr_entry15_sel(1) select + entry15_extclass_d <= wr_cam_data(63 to 64) when '1', + entry15_extclass_q(0 to 1) when others; +with wr_entry15_sel(1) select + entry15_hv_d <= wr_cam_data(65) when '1', + entry15_hv_q when others; +with wr_entry15_sel(1) select + entry15_ds_d <= wr_cam_data(66) when '1', + entry15_ds_q when others; +with wr_entry15_sel(1) select + entry15_pid_d <= wr_cam_data(67 to 74) when '1', + entry15_pid_q(0 to 7) when others; +with wr_entry15_sel(0) select + entry15_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry15_cmpmask_q when others; +with wr_entry15_sel(0) select + entry15_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry15_parity_q(0 to 3) when others; +with wr_entry15_sel(0) select + entry15_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry15_parity_q(4 to 6) when others; +with wr_entry15_sel(0) select + entry15_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry15_parity_q(7) when others; +with wr_entry15_sel(1) select + entry15_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry15_parity_q(8) when others; +with wr_entry15_sel(1) select + entry15_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry15_parity_q(9) when others; +entry0_inval <= (comp_invalidate and match_vec(0)) or flash_invalidate; +entry0_v_muxsel(0 to 1) <= (entry0_inval & wr_entry0_sel(0)); +with entry0_v_muxsel(0 to 1) select + entry0_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry0_v_q when others; +with wr_entry0_sel(0) select + entry0_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry0_thdid_q(0 to 3) when others; +entry1_inval <= (comp_invalidate and match_vec(1)) or flash_invalidate; +entry1_v_muxsel(0 to 1) <= (entry1_inval & wr_entry1_sel(0)); +with entry1_v_muxsel(0 to 1) select + entry1_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry1_v_q when others; +with wr_entry1_sel(0) select + entry1_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry1_thdid_q(0 to 3) when others; +entry2_inval <= (comp_invalidate and match_vec(2)) or flash_invalidate; +entry2_v_muxsel(0 to 1) <= (entry2_inval & wr_entry2_sel(0)); +with entry2_v_muxsel(0 to 1) select + entry2_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry2_v_q when others; +with wr_entry2_sel(0) select + entry2_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry2_thdid_q(0 to 3) when others; +entry3_inval <= (comp_invalidate and match_vec(3)) or flash_invalidate; +entry3_v_muxsel(0 to 1) <= (entry3_inval & wr_entry3_sel(0)); +with entry3_v_muxsel(0 to 1) select + entry3_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry3_v_q when others; +with wr_entry3_sel(0) select + entry3_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry3_thdid_q(0 to 3) when others; +entry4_inval <= (comp_invalidate and match_vec(4)) or flash_invalidate; +entry4_v_muxsel(0 to 1) <= (entry4_inval & wr_entry4_sel(0)); +with entry4_v_muxsel(0 to 1) select + entry4_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry4_v_q when others; +with wr_entry4_sel(0) select + entry4_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry4_thdid_q(0 to 3) when others; +entry5_inval <= (comp_invalidate and match_vec(5)) or flash_invalidate; +entry5_v_muxsel(0 to 1) <= (entry5_inval & wr_entry5_sel(0)); +with entry5_v_muxsel(0 to 1) select + entry5_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry5_v_q when others; +with wr_entry5_sel(0) select + entry5_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry5_thdid_q(0 to 3) when others; +entry6_inval <= (comp_invalidate and match_vec(6)) or flash_invalidate; +entry6_v_muxsel(0 to 1) <= (entry6_inval & wr_entry6_sel(0)); +with entry6_v_muxsel(0 to 1) select + entry6_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry6_v_q when others; +with wr_entry6_sel(0) select + entry6_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry6_thdid_q(0 to 3) when others; +entry7_inval <= (comp_invalidate and match_vec(7)) or flash_invalidate; +entry7_v_muxsel(0 to 1) <= (entry7_inval & wr_entry7_sel(0)); +with entry7_v_muxsel(0 to 1) select + entry7_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry7_v_q when others; +with wr_entry7_sel(0) select + entry7_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry7_thdid_q(0 to 3) when others; +entry8_inval <= (comp_invalidate and match_vec(8)) or flash_invalidate; +entry8_v_muxsel(0 to 1) <= (entry8_inval & wr_entry8_sel(0)); +with entry8_v_muxsel(0 to 1) select + entry8_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry8_v_q when others; +with wr_entry8_sel(0) select + entry8_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry8_thdid_q(0 to 3) when others; +entry9_inval <= (comp_invalidate and match_vec(9)) or flash_invalidate; +entry9_v_muxsel(0 to 1) <= (entry9_inval & wr_entry9_sel(0)); +with entry9_v_muxsel(0 to 1) select + entry9_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry9_v_q when others; +with wr_entry9_sel(0) select + entry9_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry9_thdid_q(0 to 3) when others; +entry10_inval <= (comp_invalidate and match_vec(10)) or flash_invalidate; +entry10_v_muxsel(0 to 1) <= (entry10_inval & wr_entry10_sel(0)); +with entry10_v_muxsel(0 to 1) select + entry10_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry10_v_q when others; +with wr_entry10_sel(0) select + entry10_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry10_thdid_q(0 to 3) when others; +entry11_inval <= (comp_invalidate and match_vec(11)) or flash_invalidate; +entry11_v_muxsel(0 to 1) <= (entry11_inval & wr_entry11_sel(0)); +with entry11_v_muxsel(0 to 1) select + entry11_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry11_v_q when others; +with wr_entry11_sel(0) select + entry11_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry11_thdid_q(0 to 3) when others; +entry12_inval <= (comp_invalidate and match_vec(12)) or flash_invalidate; +entry12_v_muxsel(0 to 1) <= (entry12_inval & wr_entry12_sel(0)); +with entry12_v_muxsel(0 to 1) select + entry12_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry12_v_q when others; +with wr_entry12_sel(0) select + entry12_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry12_thdid_q(0 to 3) when others; +entry13_inval <= (comp_invalidate and match_vec(13)) or flash_invalidate; +entry13_v_muxsel(0 to 1) <= (entry13_inval & wr_entry13_sel(0)); +with entry13_v_muxsel(0 to 1) select + entry13_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry13_v_q when others; +with wr_entry13_sel(0) select + entry13_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry13_thdid_q(0 to 3) when others; +entry14_inval <= (comp_invalidate and match_vec(14)) or flash_invalidate; +entry14_v_muxsel(0 to 1) <= (entry14_inval & wr_entry14_sel(0)); +with entry14_v_muxsel(0 to 1) select + entry14_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry14_v_q when others; +with wr_entry14_sel(0) select + entry14_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry14_thdid_q(0 to 3) when others; +entry15_inval <= (comp_invalidate and match_vec(15)) or flash_invalidate; +entry15_v_muxsel(0 to 1) <= (entry15_inval & wr_entry15_sel(0)); +with entry15_v_muxsel(0 to 1) select + entry15_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry15_v_q when others; +with wr_entry15_sel(0) select + entry15_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry15_thdid_q(0 to 3) when others; +entry0_cam_vec <= entry0_epn_q & entry0_xbit_q & entry0_size_q & entry0_v_q & entry0_thdid_q & + entry0_class_q & entry0_extclass_q & entry0_hv_q & entry0_ds_q & entry0_pid_q & entry0_cmpmask_q; +entry1_cam_vec <= entry1_epn_q & entry1_xbit_q & entry1_size_q & entry1_v_q & entry1_thdid_q & + entry1_class_q & entry1_extclass_q & entry1_hv_q & entry1_ds_q & entry1_pid_q & entry1_cmpmask_q; +entry2_cam_vec <= entry2_epn_q & entry2_xbit_q & entry2_size_q & entry2_v_q & entry2_thdid_q & + entry2_class_q & entry2_extclass_q & entry2_hv_q & entry2_ds_q & entry2_pid_q & entry2_cmpmask_q; +entry3_cam_vec <= entry3_epn_q & entry3_xbit_q & entry3_size_q & entry3_v_q & entry3_thdid_q & + entry3_class_q & entry3_extclass_q & entry3_hv_q & entry3_ds_q & entry3_pid_q & entry3_cmpmask_q; +entry4_cam_vec <= entry4_epn_q & entry4_xbit_q & entry4_size_q & entry4_v_q & entry4_thdid_q & + entry4_class_q & entry4_extclass_q & entry4_hv_q & entry4_ds_q & entry4_pid_q & entry4_cmpmask_q; +entry5_cam_vec <= entry5_epn_q & entry5_xbit_q & entry5_size_q & entry5_v_q & entry5_thdid_q & + entry5_class_q & entry5_extclass_q & entry5_hv_q & entry5_ds_q & entry5_pid_q & entry5_cmpmask_q; +entry6_cam_vec <= entry6_epn_q & entry6_xbit_q & entry6_size_q & entry6_v_q & entry6_thdid_q & + entry6_class_q & entry6_extclass_q & entry6_hv_q & entry6_ds_q & entry6_pid_q & entry6_cmpmask_q; +entry7_cam_vec <= entry7_epn_q & entry7_xbit_q & entry7_size_q & entry7_v_q & entry7_thdid_q & + entry7_class_q & entry7_extclass_q & entry7_hv_q & entry7_ds_q & entry7_pid_q & entry7_cmpmask_q; +entry8_cam_vec <= entry8_epn_q & entry8_xbit_q & entry8_size_q & entry8_v_q & entry8_thdid_q & + entry8_class_q & entry8_extclass_q & entry8_hv_q & entry8_ds_q & entry8_pid_q & entry8_cmpmask_q; +entry9_cam_vec <= entry9_epn_q & entry9_xbit_q & entry9_size_q & entry9_v_q & entry9_thdid_q & + entry9_class_q & entry9_extclass_q & entry9_hv_q & entry9_ds_q & entry9_pid_q & entry9_cmpmask_q; +entry10_cam_vec <= entry10_epn_q & entry10_xbit_q & entry10_size_q & entry10_v_q & entry10_thdid_q & + entry10_class_q & entry10_extclass_q & entry10_hv_q & entry10_ds_q & entry10_pid_q & entry10_cmpmask_q; +entry11_cam_vec <= entry11_epn_q & entry11_xbit_q & entry11_size_q & entry11_v_q & entry11_thdid_q & + entry11_class_q & entry11_extclass_q & entry11_hv_q & entry11_ds_q & entry11_pid_q & entry11_cmpmask_q; +entry12_cam_vec <= entry12_epn_q & entry12_xbit_q & entry12_size_q & entry12_v_q & entry12_thdid_q & + entry12_class_q & entry12_extclass_q & entry12_hv_q & entry12_ds_q & entry12_pid_q & entry12_cmpmask_q; +entry13_cam_vec <= entry13_epn_q & entry13_xbit_q & entry13_size_q & entry13_v_q & entry13_thdid_q & + entry13_class_q & entry13_extclass_q & entry13_hv_q & entry13_ds_q & entry13_pid_q & entry13_cmpmask_q; +entry14_cam_vec <= entry14_epn_q & entry14_xbit_q & entry14_size_q & entry14_v_q & entry14_thdid_q & + entry14_class_q & entry14_extclass_q & entry14_hv_q & entry14_ds_q & entry14_pid_q & entry14_cmpmask_q; +entry15_cam_vec <= entry15_epn_q & entry15_xbit_q & entry15_size_q & entry15_v_q & entry15_thdid_q & + entry15_class_q & entry15_extclass_q & entry15_hv_q & entry15_ds_q & entry15_pid_q & entry15_cmpmask_q; +cam_cmp_data_muxsel <= not(comp_request) & cam_hit_entry_d; +with cam_cmp_data_muxsel select + cam_cmp_data_d <= entry0_cam_vec when "00000", + entry1_cam_vec when "00001", + entry2_cam_vec when "00010", + entry3_cam_vec when "00011", + entry4_cam_vec when "00100", + entry5_cam_vec when "00101", + entry6_cam_vec when "00110", + entry7_cam_vec when "00111", + entry8_cam_vec when "01000", + entry9_cam_vec when "01001", + entry10_cam_vec when "01010", + entry11_cam_vec when "01011", + entry12_cam_vec when "01100", + entry13_cam_vec when "01101", + entry14_cam_vec when "01110", + entry15_cam_vec when "01111", + cam_cmp_data_q when others; +cam_cmp_data_np1 <= cam_cmp_data_q; +rd_cam_data_muxsel <= not(rd_val) & rw_entry; +with rd_cam_data_muxsel select + rd_cam_data_d <= entry0_cam_vec when "00000", + entry1_cam_vec when "00001", + entry2_cam_vec when "00010", + entry3_cam_vec when "00011", + entry4_cam_vec when "00100", + entry5_cam_vec when "00101", + entry6_cam_vec when "00110", + entry7_cam_vec when "00111", + entry8_cam_vec when "01000", + entry9_cam_vec when "01001", + entry10_cam_vec when "01010", + entry11_cam_vec when "01011", + entry12_cam_vec when "01100", + entry13_cam_vec when "01101", + entry14_cam_vec when "01110", + entry15_cam_vec when "01111", + rd_cam_data_q when others; +with cam_cmp_data_muxsel select + cam_cmp_parity_d <= entry0_parity_q when "00000", + entry1_parity_q when "00001", + entry2_parity_q when "00010", + entry3_parity_q when "00011", + entry4_parity_q when "00100", + entry5_parity_q when "00101", + entry6_parity_q when "00110", + entry7_parity_q when "00111", + entry8_parity_q when "01000", + entry9_parity_q when "01001", + entry10_parity_q when "01010", + entry11_parity_q when "01011", + entry12_parity_q when "01100", + entry13_parity_q when "01101", + entry14_parity_q when "01110", + entry15_parity_q when "01111", + cam_cmp_parity_q when others; +array_cmp_data_np1(0 to 50) <= array_cmp_data_bram(2 to 31) & array_cmp_data_bram(34 to 39) & array_cmp_data_bram(41 to 55); +array_cmp_data_np1(51 to 60) <= cam_cmp_parity_q; +array_cmp_data_np1(61 to 67) <= array_cmp_data_bramp(66 to 72); +array_cmp_data <= array_cmp_data_np1; +with rd_cam_data_muxsel select + rd_array_data_d(51 to 60) <= entry0_parity_q when "00000", + entry1_parity_q when "00001", + entry2_parity_q when "00010", + entry3_parity_q when "00011", + entry4_parity_q when "00100", + entry5_parity_q when "00101", + entry6_parity_q when "00110", + entry7_parity_q when "00111", + entry8_parity_q when "01000", + entry9_parity_q when "01001", + entry10_parity_q when "01010", + entry11_parity_q when "01011", + entry12_parity_q when "01100", + entry13_parity_q when "01101", + entry14_parity_q when "01110", + entry15_parity_q when "01111", + rd_array_data_q(51 to 60) when others; +rpn_np2_d(22 to 33) <= ( comp_addr_np1_q(22 to 33) and (22 to 33 => bypass_mux_enab_np1 ) ) or + ( array_cmp_data_np1(0 to 11) and (0 to 11 => not(bypass_mux_enab_np1)) ); +rpn_np2_d(34 to 39) <= ( comp_addr_np1_q(34 to 39) and (34 to 39 => (not(cam_cmp_data_np1(75)) or bypass_mux_enab_np1)) ) or + ( array_cmp_data_np1(12 to 17) and (12 to 17 => (cam_cmp_data_np1(75) and not bypass_mux_enab_np1)) ); +rpn_np2_d(40 to 43) <= ( comp_addr_np1_q(40 to 43) and (40 to 43 => (not(cam_cmp_data_np1(76)) or bypass_mux_enab_np1)) ) or + ( array_cmp_data_np1(18 to 21) and (18 to 21 => (cam_cmp_data_np1(76) and not bypass_mux_enab_np1)) ); +rpn_np2_d(44 to 47) <= ( comp_addr_np1_q(44 to 47) and (44 to 47 => (not(cam_cmp_data_np1(77)) or bypass_mux_enab_np1)) ) or + ( array_cmp_data_np1(22 to 25) and (22 to 25 => (cam_cmp_data_np1(77) and not bypass_mux_enab_np1)) ); +rpn_np2_d(48 to 51) <= ( comp_addr_np1_q(48 to 51) and (48 to 51 => (not(cam_cmp_data_np1(78)) or bypass_mux_enab_np1)) ) or + ( array_cmp_data_np1(26 to 29) and (26 to 29 => (cam_cmp_data_np1(78) and not bypass_mux_enab_np1)) ); +attr_np2_d(0 to 20) <= ( bypass_attr_np1(0 to 20) and (0 to 20 => bypass_mux_enab_np1) ) or + ( array_cmp_data_np1(30 to 50) and (30 to 50 => not bypass_mux_enab_np1) ); +rpn_np2(22 to 51) <= rpn_np2_q(22 to 51); +attr_np2(0 to 20) <= attr_np2_q(0 to 20); +matchline_comb0 : tri_cam_16x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry0_size_q, + entry_cmpmask => entry0_cmpmask_q(0 to 3), + entry_xbit => entry0_xbit_q, + entry_xbitmask => entry0_cmpmask_q(4 to 7), + entry_epn => entry0_epn_q, + comp_class => comp_class, + entry_class => entry0_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry0_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry0_hv_q, + entry_ds => entry0_ds_q, + state_enable => state_enable, + entry_thdid => entry0_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry0_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry0_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(0) + ); +matchline_comb1 : tri_cam_16x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry1_size_q, + entry_cmpmask => entry1_cmpmask_q(0 to 3), + entry_xbit => entry1_xbit_q, + entry_xbitmask => entry1_cmpmask_q(4 to 7), + entry_epn => entry1_epn_q, + comp_class => comp_class, + entry_class => entry1_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry1_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry1_hv_q, + entry_ds => entry1_ds_q, + state_enable => state_enable, + entry_thdid => entry1_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry1_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry1_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(1) + ); +matchline_comb2 : tri_cam_16x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry2_size_q, + entry_cmpmask => entry2_cmpmask_q(0 to 3), + entry_xbit => entry2_xbit_q, + entry_xbitmask => entry2_cmpmask_q(4 to 7), + entry_epn => entry2_epn_q, + comp_class => comp_class, + entry_class => entry2_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry2_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry2_hv_q, + entry_ds => entry2_ds_q, + state_enable => state_enable, + entry_thdid => entry2_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry2_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry2_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(2) + ); +matchline_comb3 : tri_cam_16x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry3_size_q, + entry_cmpmask => entry3_cmpmask_q(0 to 3), + entry_xbit => entry3_xbit_q, + entry_xbitmask => entry3_cmpmask_q(4 to 7), + entry_epn => entry3_epn_q, + comp_class => comp_class, + entry_class => entry3_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry3_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry3_hv_q, + entry_ds => entry3_ds_q, + state_enable => state_enable, + entry_thdid => entry3_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry3_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry3_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(3) + ); +matchline_comb4 : tri_cam_16x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry4_size_q, + entry_cmpmask => entry4_cmpmask_q(0 to 3), + entry_xbit => entry4_xbit_q, + entry_xbitmask => entry4_cmpmask_q(4 to 7), + entry_epn => entry4_epn_q, + comp_class => comp_class, + entry_class => entry4_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry4_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry4_hv_q, + entry_ds => entry4_ds_q, + state_enable => state_enable, + entry_thdid => entry4_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry4_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry4_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(4) + ); +matchline_comb5 : tri_cam_16x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry5_size_q, + entry_cmpmask => entry5_cmpmask_q(0 to 3), + entry_xbit => entry5_xbit_q, + entry_xbitmask => entry5_cmpmask_q(4 to 7), + entry_epn => entry5_epn_q, + comp_class => comp_class, + entry_class => entry5_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry5_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry5_hv_q, + entry_ds => entry5_ds_q, + state_enable => state_enable, + entry_thdid => entry5_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry5_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry5_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(5) + ); +matchline_comb6 : tri_cam_16x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry6_size_q, + entry_cmpmask => entry6_cmpmask_q(0 to 3), + entry_xbit => entry6_xbit_q, + entry_xbitmask => entry6_cmpmask_q(4 to 7), + entry_epn => entry6_epn_q, + comp_class => comp_class, + entry_class => entry6_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry6_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry6_hv_q, + entry_ds => entry6_ds_q, + state_enable => state_enable, + entry_thdid => entry6_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry6_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry6_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(6) + ); +matchline_comb7 : tri_cam_16x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry7_size_q, + entry_cmpmask => entry7_cmpmask_q(0 to 3), + entry_xbit => entry7_xbit_q, + entry_xbitmask => entry7_cmpmask_q(4 to 7), + entry_epn => entry7_epn_q, + comp_class => comp_class, + entry_class => entry7_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry7_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry7_hv_q, + entry_ds => entry7_ds_q, + state_enable => state_enable, + entry_thdid => entry7_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry7_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry7_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(7) + ); +matchline_comb8 : tri_cam_16x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry8_size_q, + entry_cmpmask => entry8_cmpmask_q(0 to 3), + entry_xbit => entry8_xbit_q, + entry_xbitmask => entry8_cmpmask_q(4 to 7), + entry_epn => entry8_epn_q, + comp_class => comp_class, + entry_class => entry8_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry8_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry8_hv_q, + entry_ds => entry8_ds_q, + state_enable => state_enable, + entry_thdid => entry8_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry8_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry8_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(8) + ); +matchline_comb9 : tri_cam_16x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry9_size_q, + entry_cmpmask => entry9_cmpmask_q(0 to 3), + entry_xbit => entry9_xbit_q, + entry_xbitmask => entry9_cmpmask_q(4 to 7), + entry_epn => entry9_epn_q, + comp_class => comp_class, + entry_class => entry9_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry9_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry9_hv_q, + entry_ds => entry9_ds_q, + state_enable => state_enable, + entry_thdid => entry9_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry9_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry9_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(9) + ); +matchline_comb10 : tri_cam_16x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry10_size_q, + entry_cmpmask => entry10_cmpmask_q(0 to 3), + entry_xbit => entry10_xbit_q, + entry_xbitmask => entry10_cmpmask_q(4 to 7), + entry_epn => entry10_epn_q, + comp_class => comp_class, + entry_class => entry10_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry10_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry10_hv_q, + entry_ds => entry10_ds_q, + state_enable => state_enable, + entry_thdid => entry10_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry10_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry10_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(10) + ); +matchline_comb11 : tri_cam_16x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry11_size_q, + entry_cmpmask => entry11_cmpmask_q(0 to 3), + entry_xbit => entry11_xbit_q, + entry_xbitmask => entry11_cmpmask_q(4 to 7), + entry_epn => entry11_epn_q, + comp_class => comp_class, + entry_class => entry11_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry11_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry11_hv_q, + entry_ds => entry11_ds_q, + state_enable => state_enable, + entry_thdid => entry11_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry11_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry11_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(11) + ); +matchline_comb12 : tri_cam_16x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry12_size_q, + entry_cmpmask => entry12_cmpmask_q(0 to 3), + entry_xbit => entry12_xbit_q, + entry_xbitmask => entry12_cmpmask_q(4 to 7), + entry_epn => entry12_epn_q, + comp_class => comp_class, + entry_class => entry12_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry12_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry12_hv_q, + entry_ds => entry12_ds_q, + state_enable => state_enable, + entry_thdid => entry12_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry12_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry12_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(12) + ); +matchline_comb13 : tri_cam_16x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry13_size_q, + entry_cmpmask => entry13_cmpmask_q(0 to 3), + entry_xbit => entry13_xbit_q, + entry_xbitmask => entry13_cmpmask_q(4 to 7), + entry_epn => entry13_epn_q, + comp_class => comp_class, + entry_class => entry13_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry13_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry13_hv_q, + entry_ds => entry13_ds_q, + state_enable => state_enable, + entry_thdid => entry13_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry13_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry13_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(13) + ); +matchline_comb14 : tri_cam_16x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry14_size_q, + entry_cmpmask => entry14_cmpmask_q(0 to 3), + entry_xbit => entry14_xbit_q, + entry_xbitmask => entry14_cmpmask_q(4 to 7), + entry_epn => entry14_epn_q, + comp_class => comp_class, + entry_class => entry14_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry14_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry14_hv_q, + entry_ds => entry14_ds_q, + state_enable => state_enable, + entry_thdid => entry14_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry14_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry14_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(14) + ); +matchline_comb15 : tri_cam_16x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry15_size_q, + entry_cmpmask => entry15_cmpmask_q(0 to 3), + entry_xbit => entry15_xbit_q, + entry_xbitmask => entry15_cmpmask_q(4 to 7), + entry_epn => entry15_epn_q, + comp_class => comp_class, + entry_class => entry15_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry15_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry15_hv_q, + entry_ds => entry15_ds_q, + state_enable => state_enable, + entry_thdid => entry15_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry15_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry15_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(15) + ); +bram0_wea <= wr_array_val(0) and gate_fq; +bram1_wea <= wr_array_val(1) and gate_fq; +bram2_wea <= wr_array_val(1) and gate_fq; +bram0_addra(9-num_entry_log2 to 8) <= rw_entry(0 to num_entry_log2-1); +bram1_addra(11-num_entry_log2 to 10) <= rw_entry(0 to num_entry_log2-1); +bram2_addra(10-num_entry_log2 to 9) <= rw_entry(0 to num_entry_log2-1); +bram0_addrb(9-num_entry_log2 to 8) <= cam_hit_entry_q; +bram1_addrb(11-num_entry_log2 to 10) <= cam_hit_entry_q; +bram2_addrb(10-num_entry_log2 to 9) <= cam_hit_entry_q; +bram0_addra(0 to 8-num_entry_log2) <= (others => '0'); +bram0_addrb(0 to 8-num_entry_log2) <= (others => '0'); +bram1_addra(0 to 10-num_entry_log2) <= (others => '0'); +bram1_addrb(0 to 10-num_entry_log2) <= (others => '0'); +bram2_addra(0 to 9-num_entry_log2) <= (others => '0'); +bram2_addrb(0 to 9-num_entry_log2) <= (others => '0'); +bram0 : ramb16_s36_s36 + +-- pragma translate_off +generic map( + +sim_collision_check => "none") + +-- pragma translate_on +port map( + clka => clk2x, + clkb => clk2x, + ssra => sreset_q, + ssrb => sreset_q, + addra => std_logic_vector(bram0_addra), + addrb => std_logic_vector(bram0_addrb), + dia => std_logic_vector(wr_array_data_bram(0 to 31)), + dib => (others => '0'), + doa => rd_array_data_d_std(0 to 31), + dob => array_cmp_data_bram_std(0 to 31), + dopa => rd_array_data_d_std(66 to 69), + dopb => array_cmp_data_bramp_std(66 to 69), + dipa => std_logic_vector(wr_array_data_bram(66 to 69)), + dipb => (others => '0'), + ena => '1', + enb => '1', + wea => bram0_wea, + web => '0' + ); +bram1 : ramb16_s9_s9 + +-- pragma translate_off +generic map( + +sim_collision_check => "none") + +-- pragma translate_on +port map( + clka => clk2x, + clkb => clk2x, + ssra => sreset_q, + ssrb => sreset_q, + addra => std_logic_vector(bram1_addra), + addrb => std_logic_vector(bram1_addrb), + dia => std_logic_vector(wr_array_data_bram(32 to 39)), + dib => (others => '0'), + doa => rd_array_data_d_std(32 to 39), + dob => array_cmp_data_bram_std(32 to 39), + dopa => rd_array_data_d_std(70 to 70), + dopb => array_cmp_data_bramp_std(70 to 70), + dipa => std_logic_vector(wr_array_data_bram(70 to 70)), + dipb => (others => '0'), + ena => '1', + enb => '1', + wea => bram1_wea, + web => '0' + ); +bram2 : ramb16_s18_s18 + +-- pragma translate_off +generic map( + +sim_collision_check => "none") + +-- pragma translate_on +port map( + clka => clk2x, + clkb => clk2x, + ssra => sreset_q, + ssrb => sreset_q, + addra => std_logic_vector(bram2_addra), + addrb => std_logic_vector(bram2_addrb), + dia => std_logic_vector(wr_array_data_bram(40 to 55)), + dib => (others => '0'), + doa => rd_array_data_d_std(40 to 55), + dob => array_cmp_data_bram_std(40 to 55), + dopa => rd_array_data_d_std(71 to 72), + dopb => array_cmp_data_bramp_std(71 to 72), + dipa => std_logic_vector(wr_array_data_bram(71 to 72)), + dipb => (others => '0'), + ena => '1', + enb => '1', + wea => bram2_wea, + web => '0' + ); +wr_array_data_bram(0 to 72) <= "00" & wr_array_data(0 to 29) & + "00" & wr_array_data(30 to 35) & + '0' & wr_array_data(36 to 50) & + wr_array_data(51 to 60) & wr_array_data(61 to 67); +rd_array_data_d_std(56 to 65) <= (others => '0'); +rd_array_data_d(0 to 29) <= std_ulogic_vector(rd_array_data_d_std(2 to 31)); +rd_array_data_d(30 to 35) <= std_ulogic_vector(rd_array_data_d_std(34 to 39)); +rd_array_data_d(36 to 50) <= std_ulogic_vector(rd_array_data_d_std(41 to 55)); +rd_array_data_d(61 to 67) <= std_ulogic_vector(rd_array_data_d_std(66 to 72)); +array_cmp_data_bram <= std_ulogic_vector(array_cmp_data_bram_std); +array_cmp_data_bramp <= std_ulogic_vector(array_cmp_data_bramp_std); +rd_array_data <= rd_array_data_q; +cam_cmp_data <= cam_cmp_data_q; +rd_cam_data <= rd_cam_data_q; +entry_valid(0) <= entry0_v_q; +entry_valid(1) <= entry1_v_q; +entry_valid(2) <= entry2_v_q; +entry_valid(3) <= entry3_v_q; +entry_valid(4) <= entry4_v_q; +entry_valid(5) <= entry5_v_q; +entry_valid(6) <= entry6_v_q; +entry_valid(7) <= entry7_v_q; +entry_valid(8) <= entry8_v_q; +entry_valid(9) <= entry9_v_q; +entry_valid(10) <= entry10_v_q; +entry_valid(11) <= entry11_v_q; +entry_valid(12) <= entry12_v_q; +entry_valid(13) <= entry13_v_q; +entry_valid(14) <= entry14_v_q; +entry_valid(15) <= entry15_v_q; +entry_match <= entry_match_q; +cam_hit_entry <= cam_hit_entry_q; +cam_hit <= cam_hit_q; +func_scan_out <= func_scan_in; +regfile_scan_out <= regfile_scan_in; +time_scan_out <= time_scan_in; +end generate; +end tri_cam_16x143_1r1w1c; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_cam_16x143_1r1w1c_matchline.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_cam_16x143_1r1w1c_matchline.vhdl new file mode 100644 index 0000000..b566c1e --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_cam_16x143_1r1w1c_matchline.vhdl @@ -0,0 +1,396 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; +use ieee.std_logic_1164.all ; +library ibm; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; + + +entity tri_cam_16x143_1r1w1c_matchline is + generic (have_xbit : integer := 1; + num_pgsizes : integer := 5; + have_cmpmask : integer := 1; + cmpmask_width : integer := 4); + +port( + addr_in : in std_ulogic_vector(0 to 51); + addr_enable : in std_ulogic_vector(0 to 1); + comp_pgsize : in std_ulogic_vector(0 to 2); + pgsize_enable : in std_ulogic; + entry_size : in std_ulogic_vector(0 to 2); + entry_cmpmask : in std_ulogic_vector(0 to cmpmask_width-1); + entry_xbit : in std_ulogic; + entry_xbitmask : in std_ulogic_vector(0 to cmpmask_width-1); + entry_epn : in std_ulogic_vector(0 to 51); + comp_class : in std_ulogic_vector(0 to 1); + entry_class : in std_ulogic_vector(0 to 1); + class_enable : in std_ulogic_vector(0 to 2); + comp_extclass : in std_ulogic_vector(0 to 1); + entry_extclass : in std_ulogic_vector(0 to 1); + extclass_enable : in std_ulogic_vector(0 to 1); + comp_state : in std_ulogic_vector(0 to 1); + entry_hv : in std_ulogic; + entry_ds : in std_ulogic; + state_enable : in std_ulogic_vector(0 to 1); + entry_thdid : in std_ulogic_vector(0 to 3); + comp_thdid : in std_ulogic_vector(0 to 3); + thdid_enable : in std_ulogic_vector(0 to 1); + entry_pid : in std_ulogic_vector(0 to 7); + comp_pid : in std_ulogic_vector(0 to 7); + pid_enable : in std_ulogic; + entry_v : in std_ulogic; + comp_invalidate : in std_ulogic; + + match : out std_ulogic +); + + -- synopsys translate_off + -- synopsys translate_on + +end tri_cam_16x143_1r1w1c_matchline; + +architecture tri_cam_16x143_1r1w1c_matchline of tri_cam_16x143_1r1w1c_matchline is + + + + signal entry_epn_b : std_ulogic_vector(34 to 51); + signal function_50_51 : std_ulogic; + signal function_48_51 : std_ulogic; + signal function_46_51 : std_ulogic; + signal function_44_51 : std_ulogic; + signal function_40_51 : std_ulogic; + signal function_36_51 : std_ulogic; + signal function_34_51 : std_ulogic; + signal pgsize_eq_16K : std_ulogic; + signal pgsize_eq_64K : std_ulogic; + signal pgsize_eq_256K : std_ulogic; + signal pgsize_eq_1M : std_ulogic; + signal pgsize_eq_16M : std_ulogic; + signal pgsize_eq_256M : std_ulogic; + signal pgsize_eq_1G : std_ulogic; + signal pgsize_gte_16K : std_ulogic; + signal pgsize_gte_64K : std_ulogic; + signal pgsize_gte_256K : std_ulogic; + signal pgsize_gte_1M : std_ulogic; + signal pgsize_gte_16M : std_ulogic; + signal pgsize_gte_256M : std_ulogic; + signal pgsize_gte_1G : std_ulogic; + signal comp_or_34_35 : std_ulogic; + signal comp_or_34_39 : std_ulogic; + signal comp_or_36_39 : std_ulogic; + signal comp_or_40_43 : std_ulogic; + signal comp_or_44_45 : std_ulogic; + signal comp_or_44_47 : std_ulogic; + signal comp_or_46_47 : std_ulogic; + signal comp_or_48_49 : std_ulogic; + signal comp_or_48_51 : std_ulogic; + signal comp_or_50_51 : std_ulogic; + signal match_line : std_ulogic_vector(0 to 72); + signal pgsize_match : std_ulogic; + signal addr_match : std_ulogic; + signal class_match : std_ulogic; + signal extclass_match : std_ulogic; + signal state_match : std_ulogic; + signal thdid_match : std_ulogic; + signal pid_match : std_ulogic; + +begin + + match_line(0 to 72) <= not((entry_epn(0 to 51) & entry_size(0 to 2) & entry_class(0 to 1) & entry_extclass(0 to 1) & entry_hv & entry_ds & entry_pid(0 to 7) & entry_thdid(0 to 3)) xor + (addr_in(0 to 51) & comp_pgsize(0 to 2) & comp_class(0 to 1) & comp_extclass(0 to 1) & comp_state(0 to 1) & comp_pid(0 to 7) & comp_thdid(0 to 3)) + ); + +numpgsz8 : if num_pgsizes = 8 generate + + entry_epn_b(34 to 51) <= not(entry_epn(34 to 51)); + + +gen_nocmpmask80 : if have_cmpmask = 0 generate + pgsize_eq_1G <= ( entry_size(0) and entry_size(1) and entry_size(2) ); + pgsize_eq_256M <= ( entry_size(0) and entry_size(1) and not(entry_size(2))); + pgsize_eq_16M <= ( entry_size(0) and not(entry_size(1)) and entry_size(2) ); + pgsize_eq_1M <= ( entry_size(0) and not(entry_size(1)) and not(entry_size(2))); + pgsize_eq_256K <= (not(entry_size(0)) and entry_size(1) and entry_size(2) ); + pgsize_eq_64K <= (not(entry_size(0)) and entry_size(1) and not(entry_size(2))); + pgsize_eq_16K <= (not(entry_size(0)) and not(entry_size(1)) and entry_size(2) ); + + pgsize_gte_1G <= ( entry_size(0) and entry_size(1) and entry_size(2) ); + pgsize_gte_256M <= ( entry_size(0) and entry_size(1) and not(entry_size(2))) or + pgsize_gte_1G; + pgsize_gte_16M <= ( entry_size(0) and not(entry_size(1)) and entry_size(2) ) or + pgsize_gte_256M; + pgsize_gte_1M <= ( entry_size(0) and not(entry_size(1)) and not(entry_size(2))) or + pgsize_gte_16M; + pgsize_gte_256K <= (not(entry_size(0)) and entry_size(1) and entry_size(2) ) or + pgsize_gte_1M; + pgsize_gte_64K <= (not(entry_size(0)) and entry_size(1) and not(entry_size(2))) or + pgsize_gte_256K; + pgsize_gte_16K <= (not(entry_size(0)) and not(entry_size(1)) and entry_size(2) ) or + pgsize_gte_64K; + +end generate gen_nocmpmask80; + +gen_cmpmask80 : if have_cmpmask = 1 generate + pgsize_gte_1G <= not entry_cmpmask(0); + pgsize_gte_256M <= not entry_cmpmask(1); + pgsize_gte_16M <= not entry_cmpmask(2); + pgsize_gte_1M <= not entry_cmpmask(3); + pgsize_gte_256K <= not entry_cmpmask(4); + pgsize_gte_64K <= not entry_cmpmask(5); + pgsize_gte_16K <= not entry_cmpmask(6); + + pgsize_eq_1G <= entry_xbitmask(0); + pgsize_eq_256M <= entry_xbitmask(1); + pgsize_eq_16M <= entry_xbitmask(2); + pgsize_eq_1M <= entry_xbitmask(3); + pgsize_eq_256K <= entry_xbitmask(4); + pgsize_eq_64K <= entry_xbitmask(5); + pgsize_eq_16K <= entry_xbitmask(6); +end generate gen_cmpmask80; + +gen_noxbit80 : if have_xbit = 0 generate + function_34_51 <= '0'; + function_36_51 <= '0'; + function_40_51 <= '0'; + function_44_51 <= '0'; + function_46_51 <= '0'; + function_48_51 <= '0'; + function_50_51 <= '0'; +end generate gen_noxbit80; + +gen_xbit80 : if have_xbit /= 0 generate + function_34_51 <= not(entry_xbit) or + not(pgsize_eq_1G) or + or_reduce(entry_epn_b(34 to 51) and addr_in(34 to 51)); + function_36_51 <= not(entry_xbit) or + not(pgsize_eq_256M) or + or_reduce(entry_epn_b(36 to 51) and addr_in(36 to 51)); + function_40_51 <= not(entry_xbit) or + not(pgsize_eq_16M) or + or_reduce(entry_epn_b(40 to 51) and addr_in(40 to 51)); + function_44_51 <= not(entry_xbit) or + not(pgsize_eq_1M) or + or_reduce(entry_epn_b(44 to 51) and addr_in(44 to 51)); + function_46_51 <= not(entry_xbit) or + not(pgsize_eq_256K) or + or_reduce(entry_epn_b(46 to 51) and addr_in(46 to 51)); + function_48_51 <= not(entry_xbit) or + not(pgsize_eq_64K) or + or_reduce(entry_epn_b(48 to 51) and addr_in(48 to 51)); + function_50_51 <= not(entry_xbit) or + not(pgsize_eq_16K) or + or_reduce(entry_epn_b(50 to 51) and addr_in(50 to 51)); +end generate gen_xbit80; + + + + comp_or_50_51 <= and_reduce(match_line(50 to 51)) or pgsize_gte_16K; + comp_or_48_49 <= and_reduce(match_line(48 to 49)) or pgsize_gte_64K; + comp_or_46_47 <= and_reduce(match_line(46 to 47)) or pgsize_gte_256K; + comp_or_44_45 <= and_reduce(match_line(44 to 45)) or pgsize_gte_1M; + comp_or_40_43 <= and_reduce(match_line(40 to 43)) or pgsize_gte_16M; + comp_or_36_39 <= and_reduce(match_line(36 to 39)) or pgsize_gte_256M; + comp_or_34_35 <= and_reduce(match_line(34 to 35)) or pgsize_gte_1G; + +gen_noxbit81 : if have_xbit = 0 generate + addr_match <= (comp_or_34_35 and + comp_or_36_39 and + comp_or_40_43 and + comp_or_44_45 and + comp_or_46_47 and + comp_or_48_49 and + comp_or_50_51 and + and_reduce(match_line(31 to 33)) and + (and_reduce(match_line(0 to 30)) or not(addr_enable(1)))) or + not(addr_enable(0)); +end generate gen_noxbit81; + +gen_xbit81 : if have_xbit /= 0 generate + addr_match <= (function_50_51 and + function_48_51 and + function_46_51 and + function_44_51 and + function_40_51 and + function_36_51 and + function_34_51 and + comp_or_34_35 and + comp_or_36_39 and + comp_or_40_43 and + comp_or_44_45 and + comp_or_46_47 and + comp_or_48_49 and + comp_or_50_51 and + and_reduce(match_line(31 to 33)) and + (and_reduce(match_line(0 to 30)) or not(addr_enable(1)))) or + not(addr_enable(0)); +end generate gen_xbit81; + +end generate numpgsz8; + + +numpgsz5 : if num_pgsizes = 5 generate + + function_50_51 <= '0'; + function_46_51 <= '0'; + function_36_51 <= '0'; + pgsize_eq_16K <= '0'; + pgsize_eq_256K <= '0'; + pgsize_eq_256M <= '0'; + pgsize_gte_16K <= '0'; + pgsize_gte_256K <= '0'; + pgsize_gte_256M <= '0'; + comp_or_34_35 <= '0'; + comp_or_36_39 <= '0'; + comp_or_44_45 <= '0'; + comp_or_46_47 <= '0'; + comp_or_48_49 <= '0'; + comp_or_50_51 <= '0'; + + entry_epn_b(34 to 51) <= not(entry_epn(34 to 51)); + + +gen_nocmpmask50 : if have_cmpmask = 0 generate + pgsize_eq_1G <= ( entry_size(0) and entry_size(1) and not(entry_size(2)) ); + pgsize_eq_16M <= ( entry_size(0) and entry_size(1) and entry_size(2) ); + pgsize_eq_1M <= ( entry_size(0) and not(entry_size(1)) and entry_size(2)); + pgsize_eq_64K <= (not(entry_size(0)) and entry_size(1) and entry_size(2)); + + + pgsize_gte_1G <= ( entry_size(0) and entry_size(1) and not(entry_size(2)) ); + + pgsize_gte_16M <= ( entry_size(0) and entry_size(1) and entry_size(2) ) or + pgsize_gte_1G; + pgsize_gte_1M <= ( entry_size(0) and not(entry_size(1)) and entry_size(2)) or + pgsize_gte_16M; + pgsize_gte_64K <= (not(entry_size(0)) and entry_size(1) and entry_size(2)) or + pgsize_gte_1M; +end generate gen_nocmpmask50; + +gen_cmpmask50 : if have_cmpmask = 1 generate + pgsize_gte_1G <= not entry_cmpmask(0); + pgsize_gte_16M <= not entry_cmpmask(1); + pgsize_gte_1M <= not entry_cmpmask(2); + pgsize_gte_64K <= not entry_cmpmask(3); + + pgsize_eq_1G <= entry_xbitmask(0); + pgsize_eq_16M <= entry_xbitmask(1); + pgsize_eq_1M <= entry_xbitmask(2); + pgsize_eq_64K <= entry_xbitmask(3); +end generate gen_cmpmask50; + +gen_noxbit50 : if have_xbit = 0 generate + function_34_51 <= '0'; + function_40_51 <= '0'; + function_44_51 <= '0'; + function_48_51 <= '0'; +end generate gen_noxbit50; + +gen_xbit50 : if have_xbit /= 0 generate + function_34_51 <= not(entry_xbit) or + not(pgsize_eq_1G) or + or_reduce(entry_epn_b(34 to 51) and addr_in(34 to 51)); + function_40_51 <= not(entry_xbit) or + not(pgsize_eq_16M) or + or_reduce(entry_epn_b(40 to 51) and addr_in(40 to 51)); + function_44_51 <= not(entry_xbit) or + not(pgsize_eq_1M) or + or_reduce(entry_epn_b(44 to 51) and addr_in(44 to 51)); + function_48_51 <= not(entry_xbit) or + not(pgsize_eq_64K) or + or_reduce(entry_epn_b(48 to 51) and addr_in(48 to 51)); +end generate gen_xbit50; + + comp_or_48_51 <= and_reduce(match_line(48 to 51)) or pgsize_gte_64K; + comp_or_44_47 <= and_reduce(match_line(44 to 47)) or pgsize_gte_1M; + comp_or_40_43 <= and_reduce(match_line(40 to 43)) or pgsize_gte_16M; + comp_or_34_39 <= and_reduce(match_line(34 to 39)) or pgsize_gte_1G; + +gen_noxbit51 : if have_xbit = 0 generate + addr_match <= (comp_or_34_39 and + comp_or_40_43 and + comp_or_44_47 and + comp_or_48_51 and + and_reduce(match_line(31 to 33)) and + (and_reduce(match_line(0 to 30)) or not(addr_enable(1)))) or + not(addr_enable(0)); +end generate gen_noxbit51; + +gen_xbit51 : if have_xbit /= 0 generate + addr_match <= (function_48_51 and + function_44_51 and + function_40_51 and + function_34_51 and + comp_or_34_39 and + comp_or_40_43 and + comp_or_44_47 and + comp_or_48_51 and + and_reduce(match_line(31 to 33)) and + (and_reduce(match_line(0 to 30)) or not(addr_enable(1)))) or + not(addr_enable(0)); +end generate gen_xbit51; + +end generate numpgsz5; + + + pgsize_match <= and_reduce(match_line(52 to 54)) or + not(pgsize_enable); + + class_match <= (match_line(55) or not(class_enable(0))) and + (match_line(56) or not(class_enable(1))) and + (and_reduce(match_line(55 to 56)) or not(class_enable(2)) or + (not(entry_extclass(1)) and not comp_invalidate)); + + extclass_match <= (match_line(57) or not(extclass_enable(0))) and + (match_line(58) or not(extclass_enable(1))); + + state_match <= (match_line(59) or + not(state_enable(0))) and + (match_line(60) or + not(state_enable(1))); + + thdid_match <= (or_reduce(entry_thdid(0 to 3) and comp_thdid(0 to 3)) or not(thdid_enable(0))) and + (and_reduce(match_line(69 to 72)) or not(thdid_enable(1)) or + (not(entry_extclass(1)) and not comp_invalidate)); + + pid_match <= and_reduce(match_line(61 to 68)) or + (not(entry_extclass(1)) and not comp_invalidate) or + not(pid_enable); + + match <= addr_match and + pgsize_match and + class_match and + extclass_match and + state_match and + thdid_match and + pid_match and + entry_v; + +end tri_cam_16x143_1r1w1c_matchline; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_cam_32x143_1r1w1c.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_cam_32x143_1r1w1c.vhdl new file mode 100644 index 0000000..9412ce7 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_cam_32x143_1r1w1c.vhdl @@ -0,0 +1,5047 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; +use ieee.std_logic_1164.all; +library ibm; +use ibm.std_ulogic_unsigned.all; +use ibm.std_ulogic_function_support.all; +library support; +use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; +-- pragma translate_off +-- pragma translate_on +entity tri_cam_32x143_1r1w1c is + + generic (cam_data_width : natural := 84; + array_data_width : natural := 68; + rpn_width : natural := 30; + num_entry : natural := 32; + num_entry_log2 : natural := 5; + expand_type : integer := 1); + port( + gnd : inout power_logic; + vdd : inout power_logic; + vcs : inout power_logic; + + nclk : in clk_logic; + tc_ccflush_dc : in std_ulogic; + tc_scan_dis_dc_b : in std_ulogic; + tc_scan_diag_dc : in std_ulogic; + tc_lbist_en_dc : in std_ulogic; + an_ac_atpg_en_dc : in std_ulogic; + + lcb_d_mode_dc : in std_ulogic; + lcb_clkoff_dc_b : in std_ulogic; + lcb_act_dis_dc : in std_ulogic; + lcb_mpw1_dc_b : in std_ulogic_vector(0 to 3); + lcb_mpw2_dc_b : in std_ulogic; + lcb_delay_lclkr_dc : in std_ulogic_vector(0 to 3); + + pc_sg_2 : in std_ulogic; + pc_func_slp_sl_thold_2 : in std_ulogic; + pc_func_slp_nsl_thold_2 : in std_ulogic; + pc_regf_slp_sl_thold_2 : in std_ulogic; + pc_time_sl_thold_2 : in std_ulogic; + pc_fce_2 : in std_ulogic; + + func_scan_in : in std_ulogic; + func_scan_out : out std_ulogic; + regfile_scan_in : in std_ulogic_vector(0 TO 6); + regfile_scan_out : out std_ulogic_vector(0 TO 6); + time_scan_in : in std_ulogic; + time_scan_out : out std_ulogic; + + + rd_val : in std_ulogic; + rd_val_late : in std_ulogic; + rw_entry : in std_ulogic_vector(0 to num_entry_log2-1); + + wr_array_data : in std_ulogic_vector(0 to array_data_width-1); + wr_cam_data : in std_ulogic_vector(0 to cam_data_width-1); + wr_array_val : in std_ulogic_vector(0 to 1); + wr_cam_val : in std_ulogic_vector(0 to 1); + wr_val_early : in std_ulogic; + + comp_request : in std_ulogic; + comp_addr : in std_ulogic_vector(0 to 51); + addr_enable : in std_ulogic_vector(0 to 1); + comp_pgsize : in std_ulogic_vector(0 to 2); + pgsize_enable : in std_ulogic; + comp_class : in std_ulogic_vector(0 to 1); + class_enable : in std_ulogic_vector(0 to 2); + comp_extclass : in std_ulogic_vector(0 to 1); + extclass_enable : in std_ulogic_vector(0 to 1); + comp_state : in std_ulogic_vector(0 to 1); + state_enable : in std_ulogic_vector(0 to 1); + comp_thdid : in std_ulogic_vector(0 to 3); + thdid_enable : in std_ulogic_vector(0 to 1); + comp_pid : in std_ulogic_vector(0 to 7); + pid_enable : in std_ulogic; + comp_invalidate : in std_ulogic; + flash_invalidate : in std_ulogic; + + array_cmp_data : out std_ulogic_vector(0 to array_data_width-1); + rd_array_data : out std_ulogic_vector(0 to array_data_width-1); + + cam_cmp_data : out std_ulogic_vector(0 to cam_data_width-1); + cam_hit : out std_ulogic; + cam_hit_entry : out std_ulogic_vector(0 to num_entry_log2-1); + entry_match : out std_ulogic_vector(0 to num_entry-1); + entry_valid : out std_ulogic_vector(0 to num_entry-1); + rd_cam_data : out std_ulogic_vector(0 to cam_data_width-1); + + +bypass_mux_enab_np1 : in std_ulogic; +bypass_attr_np1 : in std_ulogic_vector(0 to 20); +attr_np2 : out std_ulogic_vector(0 to 20); +rpn_np2 : out std_ulogic_vector(22 to 51) + + ); +-- synopsys translate_off +-- synopsys translate_on +end entity tri_cam_32x143_1r1w1c; +architecture tri_cam_32x143_1r1w1c of tri_cam_32x143_1r1w1c is +component tri_cam_32x143_1r1w1c_matchline + generic (have_xbit : integer := 1; + num_pgsizes : integer := 5; + have_cmpmask : integer := 1; + cmpmask_width : integer := 4); +port( + addr_in : in std_ulogic_vector(0 to 51); + addr_enable : in std_ulogic_vector(0 to 1); + comp_pgsize : in std_ulogic_vector(0 to 2); + pgsize_enable : in std_ulogic; + entry_size : in std_ulogic_vector(0 to 2); + entry_cmpmask : in std_ulogic_vector(0 to cmpmask_width-1); + entry_xbit : in std_ulogic; + entry_xbitmask : in std_ulogic_vector(0 to cmpmask_width-1); + entry_epn : in std_ulogic_vector(0 to 51); + comp_class : in std_ulogic_vector(0 to 1); + entry_class : in std_ulogic_vector(0 to 1); + class_enable : in std_ulogic_vector(0 to 2); + comp_extclass : in std_ulogic_vector(0 to 1); + entry_extclass : in std_ulogic_vector(0 to 1); + extclass_enable : in std_ulogic_vector(0 to 1); + comp_state : in std_ulogic_vector(0 to 1); + entry_hv : in std_ulogic; + entry_ds : in std_ulogic; + state_enable : in std_ulogic_vector(0 to 1); + entry_thdid : in std_ulogic_vector(0 to 3); + comp_thdid : in std_ulogic_vector(0 to 3); + thdid_enable : in std_ulogic_vector(0 to 1); + entry_pid : in std_ulogic_vector(0 to 7); + comp_pid : in std_ulogic_vector(0 to 7); + pid_enable : in std_ulogic; + entry_v : in std_ulogic; + comp_invalidate : in std_ulogic; + + match : out std_ulogic +); +end component; +begin +a : if expand_type = 1 generate +component RAMB16_S9_S9 +-- pragma translate_off + generic + ( + SIM_COLLISION_CHECK : string := "none"); +-- pragma translate_on + port + ( + DOA : out std_logic_vector(7 downto 0); + DOB : out std_logic_vector(7 downto 0); + DOPA : out std_logic_vector(0 downto 0); + DOPB : out std_logic_vector(0 downto 0); + ADDRA : in std_logic_vector(10 downto 0); + ADDRB : in std_logic_vector(10 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(7 downto 0); + DIB : in std_logic_vector(7 downto 0); + DIPA : in std_logic_vector(0 downto 0); + DIPB : in std_logic_vector(0 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); +end component; +component RAMB16_S18_S18 +-- pragma translate_off + generic( + SIM_COLLISION_CHECK : string := "none"); +-- pragma translate_on + port( + DOA : out std_logic_vector(15 downto 0); + DOB : out std_logic_vector(15 downto 0); + DOPA : out std_logic_vector(1 downto 0); + DOPB : out std_logic_vector(1 downto 0); + + ADDRA : in std_logic_vector(9 downto 0); + ADDRB : in std_logic_vector(9 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(15 downto 0); + DIB : in std_logic_vector(15 downto 0); + DIPA : in std_logic_vector(1 downto 0); + DIPB : in std_logic_vector(1 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic); + end component; +component RAMB16_S36_S36 +-- pragma translate_off + generic( + SIM_COLLISION_CHECK : string := "none"); +-- pragma translate_on + port( + DOA : out std_logic_vector(31 downto 0); + DOB : out std_logic_vector(31 downto 0); + DOPA : out std_logic_vector(3 downto 0); + DOPB : out std_logic_vector(3 downto 0); + ADDRA : in std_logic_vector(8 downto 0); + ADDRB : in std_logic_vector(8 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(31 downto 0); + DIB : in std_logic_vector(31 downto 0); + DIPA : in std_logic_vector(3 downto 0); + DIPB : in std_logic_vector(3 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic); + end component; +-- pragma translate_off +-- pragma translate_on +signal clk,clk2x : std_ulogic; +signal bram0_addra, bram0_addrb : std_ulogic_vector(0 to 8); +signal bram1_addra, bram1_addrb : std_ulogic_vector(0 to 10); +signal bram2_addra, bram2_addrb : std_ulogic_vector(0 to 9); +signal bram0_wea, bram1_wea, bram2_wea : std_ulogic; +signal array_cmp_data_bram : std_ulogic_vector(0 to 55); +signal array_cmp_data_bramp : std_ulogic_vector(66 to 72); +signal sreset_q : std_ulogic; +signal gate_fq, gate_d : std_ulogic; +signal comp_addr_np1_d, comp_addr_np1_q : std_ulogic_vector(52-rpn_width to 51); +signal rpn_np2_d,rpn_np2_q : std_ulogic_vector(52-rpn_width to 51); +signal attr_np2_d,attr_np2_q : std_ulogic_vector(0 to 20); +signal entry0_epn_d, entry0_epn_q : std_ulogic_vector(0 to 51); +signal entry0_xbit_d, entry0_xbit_q : std_ulogic; +signal entry0_size_d, entry0_size_q : std_ulogic_vector(0 to 2); +signal entry0_v_d, entry0_v_q : std_ulogic; +signal entry0_thdid_d, entry0_thdid_q : std_ulogic_vector(0 to 3); +signal entry0_class_d, entry0_class_q : std_ulogic_vector(0 to 1); +signal entry0_extclass_d, entry0_extclass_q : std_ulogic_vector(0 to 1); +signal entry0_hv_d, entry0_hv_q : std_ulogic; +signal entry0_ds_d, entry0_ds_q : std_ulogic; +signal entry0_pid_d, entry0_pid_q : std_ulogic_vector(0 to 7); +signal entry0_cmpmask_d, entry0_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry0_parity_d, entry0_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry0_sel : std_ulogic_vector(0 to 1); +signal entry0_inval : std_ulogic; +signal entry0_v_muxsel : std_ulogic_vector(0 to 1); +signal entry0_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry0_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry1_epn_d, entry1_epn_q : std_ulogic_vector(0 to 51); +signal entry1_xbit_d, entry1_xbit_q : std_ulogic; +signal entry1_size_d, entry1_size_q : std_ulogic_vector(0 to 2); +signal entry1_v_d, entry1_v_q : std_ulogic; +signal entry1_thdid_d, entry1_thdid_q : std_ulogic_vector(0 to 3); +signal entry1_class_d, entry1_class_q : std_ulogic_vector(0 to 1); +signal entry1_extclass_d, entry1_extclass_q : std_ulogic_vector(0 to 1); +signal entry1_hv_d, entry1_hv_q : std_ulogic; +signal entry1_ds_d, entry1_ds_q : std_ulogic; +signal entry1_pid_d, entry1_pid_q : std_ulogic_vector(0 to 7); +signal entry1_cmpmask_d, entry1_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry1_parity_d, entry1_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry1_sel : std_ulogic_vector(0 to 1); +signal entry1_inval : std_ulogic; +signal entry1_v_muxsel : std_ulogic_vector(0 to 1); +signal entry1_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry1_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry2_epn_d, entry2_epn_q : std_ulogic_vector(0 to 51); +signal entry2_xbit_d, entry2_xbit_q : std_ulogic; +signal entry2_size_d, entry2_size_q : std_ulogic_vector(0 to 2); +signal entry2_v_d, entry2_v_q : std_ulogic; +signal entry2_thdid_d, entry2_thdid_q : std_ulogic_vector(0 to 3); +signal entry2_class_d, entry2_class_q : std_ulogic_vector(0 to 1); +signal entry2_extclass_d, entry2_extclass_q : std_ulogic_vector(0 to 1); +signal entry2_hv_d, entry2_hv_q : std_ulogic; +signal entry2_ds_d, entry2_ds_q : std_ulogic; +signal entry2_pid_d, entry2_pid_q : std_ulogic_vector(0 to 7); +signal entry2_cmpmask_d, entry2_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry2_parity_d, entry2_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry2_sel : std_ulogic_vector(0 to 1); +signal entry2_inval : std_ulogic; +signal entry2_v_muxsel : std_ulogic_vector(0 to 1); +signal entry2_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry2_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry3_epn_d, entry3_epn_q : std_ulogic_vector(0 to 51); +signal entry3_xbit_d, entry3_xbit_q : std_ulogic; +signal entry3_size_d, entry3_size_q : std_ulogic_vector(0 to 2); +signal entry3_v_d, entry3_v_q : std_ulogic; +signal entry3_thdid_d, entry3_thdid_q : std_ulogic_vector(0 to 3); +signal entry3_class_d, entry3_class_q : std_ulogic_vector(0 to 1); +signal entry3_extclass_d, entry3_extclass_q : std_ulogic_vector(0 to 1); +signal entry3_hv_d, entry3_hv_q : std_ulogic; +signal entry3_ds_d, entry3_ds_q : std_ulogic; +signal entry3_pid_d, entry3_pid_q : std_ulogic_vector(0 to 7); +signal entry3_cmpmask_d, entry3_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry3_parity_d, entry3_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry3_sel : std_ulogic_vector(0 to 1); +signal entry3_inval : std_ulogic; +signal entry3_v_muxsel : std_ulogic_vector(0 to 1); +signal entry3_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry3_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry4_epn_d, entry4_epn_q : std_ulogic_vector(0 to 51); +signal entry4_xbit_d, entry4_xbit_q : std_ulogic; +signal entry4_size_d, entry4_size_q : std_ulogic_vector(0 to 2); +signal entry4_v_d, entry4_v_q : std_ulogic; +signal entry4_thdid_d, entry4_thdid_q : std_ulogic_vector(0 to 3); +signal entry4_class_d, entry4_class_q : std_ulogic_vector(0 to 1); +signal entry4_extclass_d, entry4_extclass_q : std_ulogic_vector(0 to 1); +signal entry4_hv_d, entry4_hv_q : std_ulogic; +signal entry4_ds_d, entry4_ds_q : std_ulogic; +signal entry4_pid_d, entry4_pid_q : std_ulogic_vector(0 to 7); +signal entry4_cmpmask_d, entry4_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry4_parity_d, entry4_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry4_sel : std_ulogic_vector(0 to 1); +signal entry4_inval : std_ulogic; +signal entry4_v_muxsel : std_ulogic_vector(0 to 1); +signal entry4_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry4_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry5_epn_d, entry5_epn_q : std_ulogic_vector(0 to 51); +signal entry5_xbit_d, entry5_xbit_q : std_ulogic; +signal entry5_size_d, entry5_size_q : std_ulogic_vector(0 to 2); +signal entry5_v_d, entry5_v_q : std_ulogic; +signal entry5_thdid_d, entry5_thdid_q : std_ulogic_vector(0 to 3); +signal entry5_class_d, entry5_class_q : std_ulogic_vector(0 to 1); +signal entry5_extclass_d, entry5_extclass_q : std_ulogic_vector(0 to 1); +signal entry5_hv_d, entry5_hv_q : std_ulogic; +signal entry5_ds_d, entry5_ds_q : std_ulogic; +signal entry5_pid_d, entry5_pid_q : std_ulogic_vector(0 to 7); +signal entry5_cmpmask_d, entry5_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry5_parity_d, entry5_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry5_sel : std_ulogic_vector(0 to 1); +signal entry5_inval : std_ulogic; +signal entry5_v_muxsel : std_ulogic_vector(0 to 1); +signal entry5_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry5_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry6_epn_d, entry6_epn_q : std_ulogic_vector(0 to 51); +signal entry6_xbit_d, entry6_xbit_q : std_ulogic; +signal entry6_size_d, entry6_size_q : std_ulogic_vector(0 to 2); +signal entry6_v_d, entry6_v_q : std_ulogic; +signal entry6_thdid_d, entry6_thdid_q : std_ulogic_vector(0 to 3); +signal entry6_class_d, entry6_class_q : std_ulogic_vector(0 to 1); +signal entry6_extclass_d, entry6_extclass_q : std_ulogic_vector(0 to 1); +signal entry6_hv_d, entry6_hv_q : std_ulogic; +signal entry6_ds_d, entry6_ds_q : std_ulogic; +signal entry6_pid_d, entry6_pid_q : std_ulogic_vector(0 to 7); +signal entry6_cmpmask_d, entry6_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry6_parity_d, entry6_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry6_sel : std_ulogic_vector(0 to 1); +signal entry6_inval : std_ulogic; +signal entry6_v_muxsel : std_ulogic_vector(0 to 1); +signal entry6_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry6_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry7_epn_d, entry7_epn_q : std_ulogic_vector(0 to 51); +signal entry7_xbit_d, entry7_xbit_q : std_ulogic; +signal entry7_size_d, entry7_size_q : std_ulogic_vector(0 to 2); +signal entry7_v_d, entry7_v_q : std_ulogic; +signal entry7_thdid_d, entry7_thdid_q : std_ulogic_vector(0 to 3); +signal entry7_class_d, entry7_class_q : std_ulogic_vector(0 to 1); +signal entry7_extclass_d, entry7_extclass_q : std_ulogic_vector(0 to 1); +signal entry7_hv_d, entry7_hv_q : std_ulogic; +signal entry7_ds_d, entry7_ds_q : std_ulogic; +signal entry7_pid_d, entry7_pid_q : std_ulogic_vector(0 to 7); +signal entry7_cmpmask_d, entry7_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry7_parity_d, entry7_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry7_sel : std_ulogic_vector(0 to 1); +signal entry7_inval : std_ulogic; +signal entry7_v_muxsel : std_ulogic_vector(0 to 1); +signal entry7_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry7_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry8_epn_d, entry8_epn_q : std_ulogic_vector(0 to 51); +signal entry8_xbit_d, entry8_xbit_q : std_ulogic; +signal entry8_size_d, entry8_size_q : std_ulogic_vector(0 to 2); +signal entry8_v_d, entry8_v_q : std_ulogic; +signal entry8_thdid_d, entry8_thdid_q : std_ulogic_vector(0 to 3); +signal entry8_class_d, entry8_class_q : std_ulogic_vector(0 to 1); +signal entry8_extclass_d, entry8_extclass_q : std_ulogic_vector(0 to 1); +signal entry8_hv_d, entry8_hv_q : std_ulogic; +signal entry8_ds_d, entry8_ds_q : std_ulogic; +signal entry8_pid_d, entry8_pid_q : std_ulogic_vector(0 to 7); +signal entry8_cmpmask_d, entry8_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry8_parity_d, entry8_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry8_sel : std_ulogic_vector(0 to 1); +signal entry8_inval : std_ulogic; +signal entry8_v_muxsel : std_ulogic_vector(0 to 1); +signal entry8_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry8_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry9_epn_d, entry9_epn_q : std_ulogic_vector(0 to 51); +signal entry9_xbit_d, entry9_xbit_q : std_ulogic; +signal entry9_size_d, entry9_size_q : std_ulogic_vector(0 to 2); +signal entry9_v_d, entry9_v_q : std_ulogic; +signal entry9_thdid_d, entry9_thdid_q : std_ulogic_vector(0 to 3); +signal entry9_class_d, entry9_class_q : std_ulogic_vector(0 to 1); +signal entry9_extclass_d, entry9_extclass_q : std_ulogic_vector(0 to 1); +signal entry9_hv_d, entry9_hv_q : std_ulogic; +signal entry9_ds_d, entry9_ds_q : std_ulogic; +signal entry9_pid_d, entry9_pid_q : std_ulogic_vector(0 to 7); +signal entry9_cmpmask_d, entry9_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry9_parity_d, entry9_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry9_sel : std_ulogic_vector(0 to 1); +signal entry9_inval : std_ulogic; +signal entry9_v_muxsel : std_ulogic_vector(0 to 1); +signal entry9_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry9_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry10_epn_d, entry10_epn_q : std_ulogic_vector(0 to 51); +signal entry10_xbit_d, entry10_xbit_q : std_ulogic; +signal entry10_size_d, entry10_size_q : std_ulogic_vector(0 to 2); +signal entry10_v_d, entry10_v_q : std_ulogic; +signal entry10_thdid_d, entry10_thdid_q : std_ulogic_vector(0 to 3); +signal entry10_class_d, entry10_class_q : std_ulogic_vector(0 to 1); +signal entry10_extclass_d, entry10_extclass_q : std_ulogic_vector(0 to 1); +signal entry10_hv_d, entry10_hv_q : std_ulogic; +signal entry10_ds_d, entry10_ds_q : std_ulogic; +signal entry10_pid_d, entry10_pid_q : std_ulogic_vector(0 to 7); +signal entry10_cmpmask_d, entry10_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry10_parity_d, entry10_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry10_sel : std_ulogic_vector(0 to 1); +signal entry10_inval : std_ulogic; +signal entry10_v_muxsel : std_ulogic_vector(0 to 1); +signal entry10_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry10_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry11_epn_d, entry11_epn_q : std_ulogic_vector(0 to 51); +signal entry11_xbit_d, entry11_xbit_q : std_ulogic; +signal entry11_size_d, entry11_size_q : std_ulogic_vector(0 to 2); +signal entry11_v_d, entry11_v_q : std_ulogic; +signal entry11_thdid_d, entry11_thdid_q : std_ulogic_vector(0 to 3); +signal entry11_class_d, entry11_class_q : std_ulogic_vector(0 to 1); +signal entry11_extclass_d, entry11_extclass_q : std_ulogic_vector(0 to 1); +signal entry11_hv_d, entry11_hv_q : std_ulogic; +signal entry11_ds_d, entry11_ds_q : std_ulogic; +signal entry11_pid_d, entry11_pid_q : std_ulogic_vector(0 to 7); +signal entry11_cmpmask_d, entry11_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry11_parity_d, entry11_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry11_sel : std_ulogic_vector(0 to 1); +signal entry11_inval : std_ulogic; +signal entry11_v_muxsel : std_ulogic_vector(0 to 1); +signal entry11_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry11_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry12_epn_d, entry12_epn_q : std_ulogic_vector(0 to 51); +signal entry12_xbit_d, entry12_xbit_q : std_ulogic; +signal entry12_size_d, entry12_size_q : std_ulogic_vector(0 to 2); +signal entry12_v_d, entry12_v_q : std_ulogic; +signal entry12_thdid_d, entry12_thdid_q : std_ulogic_vector(0 to 3); +signal entry12_class_d, entry12_class_q : std_ulogic_vector(0 to 1); +signal entry12_extclass_d, entry12_extclass_q : std_ulogic_vector(0 to 1); +signal entry12_hv_d, entry12_hv_q : std_ulogic; +signal entry12_ds_d, entry12_ds_q : std_ulogic; +signal entry12_pid_d, entry12_pid_q : std_ulogic_vector(0 to 7); +signal entry12_cmpmask_d, entry12_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry12_parity_d, entry12_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry12_sel : std_ulogic_vector(0 to 1); +signal entry12_inval : std_ulogic; +signal entry12_v_muxsel : std_ulogic_vector(0 to 1); +signal entry12_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry12_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry13_epn_d, entry13_epn_q : std_ulogic_vector(0 to 51); +signal entry13_xbit_d, entry13_xbit_q : std_ulogic; +signal entry13_size_d, entry13_size_q : std_ulogic_vector(0 to 2); +signal entry13_v_d, entry13_v_q : std_ulogic; +signal entry13_thdid_d, entry13_thdid_q : std_ulogic_vector(0 to 3); +signal entry13_class_d, entry13_class_q : std_ulogic_vector(0 to 1); +signal entry13_extclass_d, entry13_extclass_q : std_ulogic_vector(0 to 1); +signal entry13_hv_d, entry13_hv_q : std_ulogic; +signal entry13_ds_d, entry13_ds_q : std_ulogic; +signal entry13_pid_d, entry13_pid_q : std_ulogic_vector(0 to 7); +signal entry13_cmpmask_d, entry13_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry13_parity_d, entry13_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry13_sel : std_ulogic_vector(0 to 1); +signal entry13_inval : std_ulogic; +signal entry13_v_muxsel : std_ulogic_vector(0 to 1); +signal entry13_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry13_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry14_epn_d, entry14_epn_q : std_ulogic_vector(0 to 51); +signal entry14_xbit_d, entry14_xbit_q : std_ulogic; +signal entry14_size_d, entry14_size_q : std_ulogic_vector(0 to 2); +signal entry14_v_d, entry14_v_q : std_ulogic; +signal entry14_thdid_d, entry14_thdid_q : std_ulogic_vector(0 to 3); +signal entry14_class_d, entry14_class_q : std_ulogic_vector(0 to 1); +signal entry14_extclass_d, entry14_extclass_q : std_ulogic_vector(0 to 1); +signal entry14_hv_d, entry14_hv_q : std_ulogic; +signal entry14_ds_d, entry14_ds_q : std_ulogic; +signal entry14_pid_d, entry14_pid_q : std_ulogic_vector(0 to 7); +signal entry14_cmpmask_d, entry14_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry14_parity_d, entry14_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry14_sel : std_ulogic_vector(0 to 1); +signal entry14_inval : std_ulogic; +signal entry14_v_muxsel : std_ulogic_vector(0 to 1); +signal entry14_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry14_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry15_epn_d, entry15_epn_q : std_ulogic_vector(0 to 51); +signal entry15_xbit_d, entry15_xbit_q : std_ulogic; +signal entry15_size_d, entry15_size_q : std_ulogic_vector(0 to 2); +signal entry15_v_d, entry15_v_q : std_ulogic; +signal entry15_thdid_d, entry15_thdid_q : std_ulogic_vector(0 to 3); +signal entry15_class_d, entry15_class_q : std_ulogic_vector(0 to 1); +signal entry15_extclass_d, entry15_extclass_q : std_ulogic_vector(0 to 1); +signal entry15_hv_d, entry15_hv_q : std_ulogic; +signal entry15_ds_d, entry15_ds_q : std_ulogic; +signal entry15_pid_d, entry15_pid_q : std_ulogic_vector(0 to 7); +signal entry15_cmpmask_d, entry15_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry15_parity_d, entry15_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry15_sel : std_ulogic_vector(0 to 1); +signal entry15_inval : std_ulogic; +signal entry15_v_muxsel : std_ulogic_vector(0 to 1); +signal entry15_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry15_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry16_epn_d, entry16_epn_q : std_ulogic_vector(0 to 51); +signal entry16_xbit_d, entry16_xbit_q : std_ulogic; +signal entry16_size_d, entry16_size_q : std_ulogic_vector(0 to 2); +signal entry16_v_d, entry16_v_q : std_ulogic; +signal entry16_thdid_d, entry16_thdid_q : std_ulogic_vector(0 to 3); +signal entry16_class_d, entry16_class_q : std_ulogic_vector(0 to 1); +signal entry16_extclass_d, entry16_extclass_q : std_ulogic_vector(0 to 1); +signal entry16_hv_d, entry16_hv_q : std_ulogic; +signal entry16_ds_d, entry16_ds_q : std_ulogic; +signal entry16_pid_d, entry16_pid_q : std_ulogic_vector(0 to 7); +signal entry16_cmpmask_d, entry16_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry16_parity_d, entry16_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry16_sel : std_ulogic_vector(0 to 1); +signal entry16_inval : std_ulogic; +signal entry16_v_muxsel : std_ulogic_vector(0 to 1); +signal entry16_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry16_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry17_epn_d, entry17_epn_q : std_ulogic_vector(0 to 51); +signal entry17_xbit_d, entry17_xbit_q : std_ulogic; +signal entry17_size_d, entry17_size_q : std_ulogic_vector(0 to 2); +signal entry17_v_d, entry17_v_q : std_ulogic; +signal entry17_thdid_d, entry17_thdid_q : std_ulogic_vector(0 to 3); +signal entry17_class_d, entry17_class_q : std_ulogic_vector(0 to 1); +signal entry17_extclass_d, entry17_extclass_q : std_ulogic_vector(0 to 1); +signal entry17_hv_d, entry17_hv_q : std_ulogic; +signal entry17_ds_d, entry17_ds_q : std_ulogic; +signal entry17_pid_d, entry17_pid_q : std_ulogic_vector(0 to 7); +signal entry17_cmpmask_d, entry17_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry17_parity_d, entry17_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry17_sel : std_ulogic_vector(0 to 1); +signal entry17_inval : std_ulogic; +signal entry17_v_muxsel : std_ulogic_vector(0 to 1); +signal entry17_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry17_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry18_epn_d, entry18_epn_q : std_ulogic_vector(0 to 51); +signal entry18_xbit_d, entry18_xbit_q : std_ulogic; +signal entry18_size_d, entry18_size_q : std_ulogic_vector(0 to 2); +signal entry18_v_d, entry18_v_q : std_ulogic; +signal entry18_thdid_d, entry18_thdid_q : std_ulogic_vector(0 to 3); +signal entry18_class_d, entry18_class_q : std_ulogic_vector(0 to 1); +signal entry18_extclass_d, entry18_extclass_q : std_ulogic_vector(0 to 1); +signal entry18_hv_d, entry18_hv_q : std_ulogic; +signal entry18_ds_d, entry18_ds_q : std_ulogic; +signal entry18_pid_d, entry18_pid_q : std_ulogic_vector(0 to 7); +signal entry18_cmpmask_d, entry18_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry18_parity_d, entry18_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry18_sel : std_ulogic_vector(0 to 1); +signal entry18_inval : std_ulogic; +signal entry18_v_muxsel : std_ulogic_vector(0 to 1); +signal entry18_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry18_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry19_epn_d, entry19_epn_q : std_ulogic_vector(0 to 51); +signal entry19_xbit_d, entry19_xbit_q : std_ulogic; +signal entry19_size_d, entry19_size_q : std_ulogic_vector(0 to 2); +signal entry19_v_d, entry19_v_q : std_ulogic; +signal entry19_thdid_d, entry19_thdid_q : std_ulogic_vector(0 to 3); +signal entry19_class_d, entry19_class_q : std_ulogic_vector(0 to 1); +signal entry19_extclass_d, entry19_extclass_q : std_ulogic_vector(0 to 1); +signal entry19_hv_d, entry19_hv_q : std_ulogic; +signal entry19_ds_d, entry19_ds_q : std_ulogic; +signal entry19_pid_d, entry19_pid_q : std_ulogic_vector(0 to 7); +signal entry19_cmpmask_d, entry19_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry19_parity_d, entry19_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry19_sel : std_ulogic_vector(0 to 1); +signal entry19_inval : std_ulogic; +signal entry19_v_muxsel : std_ulogic_vector(0 to 1); +signal entry19_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry19_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry20_epn_d, entry20_epn_q : std_ulogic_vector(0 to 51); +signal entry20_xbit_d, entry20_xbit_q : std_ulogic; +signal entry20_size_d, entry20_size_q : std_ulogic_vector(0 to 2); +signal entry20_v_d, entry20_v_q : std_ulogic; +signal entry20_thdid_d, entry20_thdid_q : std_ulogic_vector(0 to 3); +signal entry20_class_d, entry20_class_q : std_ulogic_vector(0 to 1); +signal entry20_extclass_d, entry20_extclass_q : std_ulogic_vector(0 to 1); +signal entry20_hv_d, entry20_hv_q : std_ulogic; +signal entry20_ds_d, entry20_ds_q : std_ulogic; +signal entry20_pid_d, entry20_pid_q : std_ulogic_vector(0 to 7); +signal entry20_cmpmask_d, entry20_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry20_parity_d, entry20_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry20_sel : std_ulogic_vector(0 to 1); +signal entry20_inval : std_ulogic; +signal entry20_v_muxsel : std_ulogic_vector(0 to 1); +signal entry20_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry20_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry21_epn_d, entry21_epn_q : std_ulogic_vector(0 to 51); +signal entry21_xbit_d, entry21_xbit_q : std_ulogic; +signal entry21_size_d, entry21_size_q : std_ulogic_vector(0 to 2); +signal entry21_v_d, entry21_v_q : std_ulogic; +signal entry21_thdid_d, entry21_thdid_q : std_ulogic_vector(0 to 3); +signal entry21_class_d, entry21_class_q : std_ulogic_vector(0 to 1); +signal entry21_extclass_d, entry21_extclass_q : std_ulogic_vector(0 to 1); +signal entry21_hv_d, entry21_hv_q : std_ulogic; +signal entry21_ds_d, entry21_ds_q : std_ulogic; +signal entry21_pid_d, entry21_pid_q : std_ulogic_vector(0 to 7); +signal entry21_cmpmask_d, entry21_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry21_parity_d, entry21_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry21_sel : std_ulogic_vector(0 to 1); +signal entry21_inval : std_ulogic; +signal entry21_v_muxsel : std_ulogic_vector(0 to 1); +signal entry21_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry21_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry22_epn_d, entry22_epn_q : std_ulogic_vector(0 to 51); +signal entry22_xbit_d, entry22_xbit_q : std_ulogic; +signal entry22_size_d, entry22_size_q : std_ulogic_vector(0 to 2); +signal entry22_v_d, entry22_v_q : std_ulogic; +signal entry22_thdid_d, entry22_thdid_q : std_ulogic_vector(0 to 3); +signal entry22_class_d, entry22_class_q : std_ulogic_vector(0 to 1); +signal entry22_extclass_d, entry22_extclass_q : std_ulogic_vector(0 to 1); +signal entry22_hv_d, entry22_hv_q : std_ulogic; +signal entry22_ds_d, entry22_ds_q : std_ulogic; +signal entry22_pid_d, entry22_pid_q : std_ulogic_vector(0 to 7); +signal entry22_cmpmask_d, entry22_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry22_parity_d, entry22_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry22_sel : std_ulogic_vector(0 to 1); +signal entry22_inval : std_ulogic; +signal entry22_v_muxsel : std_ulogic_vector(0 to 1); +signal entry22_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry22_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry23_epn_d, entry23_epn_q : std_ulogic_vector(0 to 51); +signal entry23_xbit_d, entry23_xbit_q : std_ulogic; +signal entry23_size_d, entry23_size_q : std_ulogic_vector(0 to 2); +signal entry23_v_d, entry23_v_q : std_ulogic; +signal entry23_thdid_d, entry23_thdid_q : std_ulogic_vector(0 to 3); +signal entry23_class_d, entry23_class_q : std_ulogic_vector(0 to 1); +signal entry23_extclass_d, entry23_extclass_q : std_ulogic_vector(0 to 1); +signal entry23_hv_d, entry23_hv_q : std_ulogic; +signal entry23_ds_d, entry23_ds_q : std_ulogic; +signal entry23_pid_d, entry23_pid_q : std_ulogic_vector(0 to 7); +signal entry23_cmpmask_d, entry23_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry23_parity_d, entry23_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry23_sel : std_ulogic_vector(0 to 1); +signal entry23_inval : std_ulogic; +signal entry23_v_muxsel : std_ulogic_vector(0 to 1); +signal entry23_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry23_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry24_epn_d, entry24_epn_q : std_ulogic_vector(0 to 51); +signal entry24_xbit_d, entry24_xbit_q : std_ulogic; +signal entry24_size_d, entry24_size_q : std_ulogic_vector(0 to 2); +signal entry24_v_d, entry24_v_q : std_ulogic; +signal entry24_thdid_d, entry24_thdid_q : std_ulogic_vector(0 to 3); +signal entry24_class_d, entry24_class_q : std_ulogic_vector(0 to 1); +signal entry24_extclass_d, entry24_extclass_q : std_ulogic_vector(0 to 1); +signal entry24_hv_d, entry24_hv_q : std_ulogic; +signal entry24_ds_d, entry24_ds_q : std_ulogic; +signal entry24_pid_d, entry24_pid_q : std_ulogic_vector(0 to 7); +signal entry24_cmpmask_d, entry24_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry24_parity_d, entry24_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry24_sel : std_ulogic_vector(0 to 1); +signal entry24_inval : std_ulogic; +signal entry24_v_muxsel : std_ulogic_vector(0 to 1); +signal entry24_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry24_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry25_epn_d, entry25_epn_q : std_ulogic_vector(0 to 51); +signal entry25_xbit_d, entry25_xbit_q : std_ulogic; +signal entry25_size_d, entry25_size_q : std_ulogic_vector(0 to 2); +signal entry25_v_d, entry25_v_q : std_ulogic; +signal entry25_thdid_d, entry25_thdid_q : std_ulogic_vector(0 to 3); +signal entry25_class_d, entry25_class_q : std_ulogic_vector(0 to 1); +signal entry25_extclass_d, entry25_extclass_q : std_ulogic_vector(0 to 1); +signal entry25_hv_d, entry25_hv_q : std_ulogic; +signal entry25_ds_d, entry25_ds_q : std_ulogic; +signal entry25_pid_d, entry25_pid_q : std_ulogic_vector(0 to 7); +signal entry25_cmpmask_d, entry25_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry25_parity_d, entry25_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry25_sel : std_ulogic_vector(0 to 1); +signal entry25_inval : std_ulogic; +signal entry25_v_muxsel : std_ulogic_vector(0 to 1); +signal entry25_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry25_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry26_epn_d, entry26_epn_q : std_ulogic_vector(0 to 51); +signal entry26_xbit_d, entry26_xbit_q : std_ulogic; +signal entry26_size_d, entry26_size_q : std_ulogic_vector(0 to 2); +signal entry26_v_d, entry26_v_q : std_ulogic; +signal entry26_thdid_d, entry26_thdid_q : std_ulogic_vector(0 to 3); +signal entry26_class_d, entry26_class_q : std_ulogic_vector(0 to 1); +signal entry26_extclass_d, entry26_extclass_q : std_ulogic_vector(0 to 1); +signal entry26_hv_d, entry26_hv_q : std_ulogic; +signal entry26_ds_d, entry26_ds_q : std_ulogic; +signal entry26_pid_d, entry26_pid_q : std_ulogic_vector(0 to 7); +signal entry26_cmpmask_d, entry26_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry26_parity_d, entry26_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry26_sel : std_ulogic_vector(0 to 1); +signal entry26_inval : std_ulogic; +signal entry26_v_muxsel : std_ulogic_vector(0 to 1); +signal entry26_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry26_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry27_epn_d, entry27_epn_q : std_ulogic_vector(0 to 51); +signal entry27_xbit_d, entry27_xbit_q : std_ulogic; +signal entry27_size_d, entry27_size_q : std_ulogic_vector(0 to 2); +signal entry27_v_d, entry27_v_q : std_ulogic; +signal entry27_thdid_d, entry27_thdid_q : std_ulogic_vector(0 to 3); +signal entry27_class_d, entry27_class_q : std_ulogic_vector(0 to 1); +signal entry27_extclass_d, entry27_extclass_q : std_ulogic_vector(0 to 1); +signal entry27_hv_d, entry27_hv_q : std_ulogic; +signal entry27_ds_d, entry27_ds_q : std_ulogic; +signal entry27_pid_d, entry27_pid_q : std_ulogic_vector(0 to 7); +signal entry27_cmpmask_d, entry27_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry27_parity_d, entry27_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry27_sel : std_ulogic_vector(0 to 1); +signal entry27_inval : std_ulogic; +signal entry27_v_muxsel : std_ulogic_vector(0 to 1); +signal entry27_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry27_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry28_epn_d, entry28_epn_q : std_ulogic_vector(0 to 51); +signal entry28_xbit_d, entry28_xbit_q : std_ulogic; +signal entry28_size_d, entry28_size_q : std_ulogic_vector(0 to 2); +signal entry28_v_d, entry28_v_q : std_ulogic; +signal entry28_thdid_d, entry28_thdid_q : std_ulogic_vector(0 to 3); +signal entry28_class_d, entry28_class_q : std_ulogic_vector(0 to 1); +signal entry28_extclass_d, entry28_extclass_q : std_ulogic_vector(0 to 1); +signal entry28_hv_d, entry28_hv_q : std_ulogic; +signal entry28_ds_d, entry28_ds_q : std_ulogic; +signal entry28_pid_d, entry28_pid_q : std_ulogic_vector(0 to 7); +signal entry28_cmpmask_d, entry28_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry28_parity_d, entry28_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry28_sel : std_ulogic_vector(0 to 1); +signal entry28_inval : std_ulogic; +signal entry28_v_muxsel : std_ulogic_vector(0 to 1); +signal entry28_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry28_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry29_epn_d, entry29_epn_q : std_ulogic_vector(0 to 51); +signal entry29_xbit_d, entry29_xbit_q : std_ulogic; +signal entry29_size_d, entry29_size_q : std_ulogic_vector(0 to 2); +signal entry29_v_d, entry29_v_q : std_ulogic; +signal entry29_thdid_d, entry29_thdid_q : std_ulogic_vector(0 to 3); +signal entry29_class_d, entry29_class_q : std_ulogic_vector(0 to 1); +signal entry29_extclass_d, entry29_extclass_q : std_ulogic_vector(0 to 1); +signal entry29_hv_d, entry29_hv_q : std_ulogic; +signal entry29_ds_d, entry29_ds_q : std_ulogic; +signal entry29_pid_d, entry29_pid_q : std_ulogic_vector(0 to 7); +signal entry29_cmpmask_d, entry29_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry29_parity_d, entry29_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry29_sel : std_ulogic_vector(0 to 1); +signal entry29_inval : std_ulogic; +signal entry29_v_muxsel : std_ulogic_vector(0 to 1); +signal entry29_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry29_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry30_epn_d, entry30_epn_q : std_ulogic_vector(0 to 51); +signal entry30_xbit_d, entry30_xbit_q : std_ulogic; +signal entry30_size_d, entry30_size_q : std_ulogic_vector(0 to 2); +signal entry30_v_d, entry30_v_q : std_ulogic; +signal entry30_thdid_d, entry30_thdid_q : std_ulogic_vector(0 to 3); +signal entry30_class_d, entry30_class_q : std_ulogic_vector(0 to 1); +signal entry30_extclass_d, entry30_extclass_q : std_ulogic_vector(0 to 1); +signal entry30_hv_d, entry30_hv_q : std_ulogic; +signal entry30_ds_d, entry30_ds_q : std_ulogic; +signal entry30_pid_d, entry30_pid_q : std_ulogic_vector(0 to 7); +signal entry30_cmpmask_d, entry30_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry30_parity_d, entry30_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry30_sel : std_ulogic_vector(0 to 1); +signal entry30_inval : std_ulogic; +signal entry30_v_muxsel : std_ulogic_vector(0 to 1); +signal entry30_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry30_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry31_epn_d, entry31_epn_q : std_ulogic_vector(0 to 51); +signal entry31_xbit_d, entry31_xbit_q : std_ulogic; +signal entry31_size_d, entry31_size_q : std_ulogic_vector(0 to 2); +signal entry31_v_d, entry31_v_q : std_ulogic; +signal entry31_thdid_d, entry31_thdid_q : std_ulogic_vector(0 to 3); +signal entry31_class_d, entry31_class_q : std_ulogic_vector(0 to 1); +signal entry31_extclass_d, entry31_extclass_q : std_ulogic_vector(0 to 1); +signal entry31_hv_d, entry31_hv_q : std_ulogic; +signal entry31_ds_d, entry31_ds_q : std_ulogic; +signal entry31_pid_d, entry31_pid_q : std_ulogic_vector(0 to 7); +signal entry31_cmpmask_d, entry31_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry31_parity_d, entry31_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry31_sel : std_ulogic_vector(0 to 1); +signal entry31_inval : std_ulogic; +signal entry31_v_muxsel : std_ulogic_vector(0 to 1); +signal entry31_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry31_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal cam_cmp_data_muxsel : std_ulogic_vector(0 to 5); +signal rd_cam_data_muxsel : std_ulogic_vector(0 to 5); +signal cam_cmp_data_np1 : std_ulogic_vector(0 to cam_data_width-1); +signal array_cmp_data_np1 : std_ulogic_vector(0 to array_data_width-1); +signal wr_array_data_bram : std_ulogic_vector(0 to 72); +signal rd_array_data_d_std : std_logic_vector(0 to 72); +signal array_cmp_data_bram_std : std_logic_vector(0 to 55); +signal array_cmp_data_bramp_std : std_logic_vector(66 to 72); +signal rd_array_data_d : std_ulogic_vector(0 to array_data_width-1); +signal rd_array_data_q : std_ulogic_vector(0 to array_data_width-1); +signal cam_cmp_data_d : std_ulogic_vector(0 to cam_data_width-1); +signal cam_cmp_data_q : std_ulogic_vector(0 to cam_data_width-1); +signal cam_cmp_parity_d : std_ulogic_vector(0 to 9); +signal cam_cmp_parity_q : std_ulogic_vector(0 to 9); +signal rd_cam_data_d : std_ulogic_vector(0 to cam_data_width-1); +signal rd_cam_data_q : std_ulogic_vector(0 to cam_data_width-1); +signal entry_match_d : std_ulogic_vector(0 to num_entry-1); +signal entry_match_q : std_ulogic_vector(0 to num_entry-1); +signal match_vec : std_ulogic_vector(0 to num_entry-1); +signal cam_hit_entry_d : std_ulogic_vector(0 to num_entry_log2-1); +signal cam_hit_entry_q : std_ulogic_vector(0 to num_entry_log2-1); +signal cam_hit_d : std_ulogic; +signal cam_hit_q : std_ulogic; +signal toggle_d : std_ulogic; +signal toggle_q : std_ulogic; +signal toggle2x_d : std_ulogic; +signal toggle2x_q : std_ulogic; +begin + +clk <= not nclk.clk; +clk2x <= nclk.clk2x; +rlatch: process (clk) +begin +if(rising_edge(clk)) then +sreset_q <= nclk.sreset; +end if; +end process; +tlatch: process (nclk.clk,sreset_q) +begin +if(rising_edge(nclk.clk)) then +if (sreset_q = '1') then +toggle_q <= '1'; +else +toggle_q <= toggle_d; +end if; +end if; +end process; +flatch: process (nclk.clk2x) +begin +if(rising_edge(nclk.clk2x)) then +toggle2x_q <= toggle2x_d; +gate_fq <= gate_d; +end if; +end process; +toggle_d <= not toggle_q; +toggle2x_d <= toggle_q; +gate_d <= toggle_q xor toggle2x_q; +slatch: process (nclk,sreset_q) +begin +if(rising_edge(nclk.clk)) then +if (sreset_q = '1') then +cam_cmp_data_q <= (others => '0'); +cam_cmp_parity_q <= (others => '0'); +rd_cam_data_q <= (others => '0'); +rd_array_data_q <= (others => '0'); +entry_match_q <= (others => '0'); +cam_hit_entry_q <= (others => '0'); +cam_hit_q <= '0'; +comp_addr_np1_q <= (others => '0'); +rpn_np2_q <= (others => '0'); +attr_np2_q <= (others => '0'); +entry0_size_q <= (others => '0'); +entry0_xbit_q <= '0'; +entry0_epn_q <= (others => '0'); +entry0_class_q <= (others => '0'); +entry0_extclass_q <= (others => '0'); +entry0_hv_q <= '0'; +entry0_ds_q <= '0'; +entry0_thdid_q <= (others => '0'); +entry0_pid_q <= (others => '0'); +entry0_v_q <= '0'; +entry0_parity_q <= (others => '0'); +entry0_cmpmask_q <= (others => '0'); +entry1_size_q <= (others => '0'); +entry1_xbit_q <= '0'; +entry1_epn_q <= (others => '0'); +entry1_class_q <= (others => '0'); +entry1_extclass_q <= (others => '0'); +entry1_hv_q <= '0'; +entry1_ds_q <= '0'; +entry1_thdid_q <= (others => '0'); +entry1_pid_q <= (others => '0'); +entry1_v_q <= '0'; +entry1_parity_q <= (others => '0'); +entry1_cmpmask_q <= (others => '0'); +entry2_size_q <= (others => '0'); +entry2_xbit_q <= '0'; +entry2_epn_q <= (others => '0'); +entry2_class_q <= (others => '0'); +entry2_extclass_q <= (others => '0'); +entry2_hv_q <= '0'; +entry2_ds_q <= '0'; +entry2_thdid_q <= (others => '0'); +entry2_pid_q <= (others => '0'); +entry2_v_q <= '0'; +entry2_parity_q <= (others => '0'); +entry2_cmpmask_q <= (others => '0'); +entry3_size_q <= (others => '0'); +entry3_xbit_q <= '0'; +entry3_epn_q <= (others => '0'); +entry3_class_q <= (others => '0'); +entry3_extclass_q <= (others => '0'); +entry3_hv_q <= '0'; +entry3_ds_q <= '0'; +entry3_thdid_q <= (others => '0'); +entry3_pid_q <= (others => '0'); +entry3_v_q <= '0'; +entry3_parity_q <= (others => '0'); +entry3_cmpmask_q <= (others => '0'); +entry4_size_q <= (others => '0'); +entry4_xbit_q <= '0'; +entry4_epn_q <= (others => '0'); +entry4_class_q <= (others => '0'); +entry4_extclass_q <= (others => '0'); +entry4_hv_q <= '0'; +entry4_ds_q <= '0'; +entry4_thdid_q <= (others => '0'); +entry4_pid_q <= (others => '0'); +entry4_v_q <= '0'; +entry4_parity_q <= (others => '0'); +entry4_cmpmask_q <= (others => '0'); +entry5_size_q <= (others => '0'); +entry5_xbit_q <= '0'; +entry5_epn_q <= (others => '0'); +entry5_class_q <= (others => '0'); +entry5_extclass_q <= (others => '0'); +entry5_hv_q <= '0'; +entry5_ds_q <= '0'; +entry5_thdid_q <= (others => '0'); +entry5_pid_q <= (others => '0'); +entry5_v_q <= '0'; +entry5_parity_q <= (others => '0'); +entry5_cmpmask_q <= (others => '0'); +entry6_size_q <= (others => '0'); +entry6_xbit_q <= '0'; +entry6_epn_q <= (others => '0'); +entry6_class_q <= (others => '0'); +entry6_extclass_q <= (others => '0'); +entry6_hv_q <= '0'; +entry6_ds_q <= '0'; +entry6_thdid_q <= (others => '0'); +entry6_pid_q <= (others => '0'); +entry6_v_q <= '0'; +entry6_parity_q <= (others => '0'); +entry6_cmpmask_q <= (others => '0'); +entry7_size_q <= (others => '0'); +entry7_xbit_q <= '0'; +entry7_epn_q <= (others => '0'); +entry7_class_q <= (others => '0'); +entry7_extclass_q <= (others => '0'); +entry7_hv_q <= '0'; +entry7_ds_q <= '0'; +entry7_thdid_q <= (others => '0'); +entry7_pid_q <= (others => '0'); +entry7_v_q <= '0'; +entry7_parity_q <= (others => '0'); +entry7_cmpmask_q <= (others => '0'); +entry8_size_q <= (others => '0'); +entry8_xbit_q <= '0'; +entry8_epn_q <= (others => '0'); +entry8_class_q <= (others => '0'); +entry8_extclass_q <= (others => '0'); +entry8_hv_q <= '0'; +entry8_ds_q <= '0'; +entry8_thdid_q <= (others => '0'); +entry8_pid_q <= (others => '0'); +entry8_v_q <= '0'; +entry8_parity_q <= (others => '0'); +entry8_cmpmask_q <= (others => '0'); +entry9_size_q <= (others => '0'); +entry9_xbit_q <= '0'; +entry9_epn_q <= (others => '0'); +entry9_class_q <= (others => '0'); +entry9_extclass_q <= (others => '0'); +entry9_hv_q <= '0'; +entry9_ds_q <= '0'; +entry9_thdid_q <= (others => '0'); +entry9_pid_q <= (others => '0'); +entry9_v_q <= '0'; +entry9_parity_q <= (others => '0'); +entry9_cmpmask_q <= (others => '0'); +entry10_size_q <= (others => '0'); +entry10_xbit_q <= '0'; +entry10_epn_q <= (others => '0'); +entry10_class_q <= (others => '0'); +entry10_extclass_q <= (others => '0'); +entry10_hv_q <= '0'; +entry10_ds_q <= '0'; +entry10_thdid_q <= (others => '0'); +entry10_pid_q <= (others => '0'); +entry10_v_q <= '0'; +entry10_parity_q <= (others => '0'); +entry10_cmpmask_q <= (others => '0'); +entry11_size_q <= (others => '0'); +entry11_xbit_q <= '0'; +entry11_epn_q <= (others => '0'); +entry11_class_q <= (others => '0'); +entry11_extclass_q <= (others => '0'); +entry11_hv_q <= '0'; +entry11_ds_q <= '0'; +entry11_thdid_q <= (others => '0'); +entry11_pid_q <= (others => '0'); +entry11_v_q <= '0'; +entry11_parity_q <= (others => '0'); +entry11_cmpmask_q <= (others => '0'); +entry12_size_q <= (others => '0'); +entry12_xbit_q <= '0'; +entry12_epn_q <= (others => '0'); +entry12_class_q <= (others => '0'); +entry12_extclass_q <= (others => '0'); +entry12_hv_q <= '0'; +entry12_ds_q <= '0'; +entry12_thdid_q <= (others => '0'); +entry12_pid_q <= (others => '0'); +entry12_v_q <= '0'; +entry12_parity_q <= (others => '0'); +entry12_cmpmask_q <= (others => '0'); +entry13_size_q <= (others => '0'); +entry13_xbit_q <= '0'; +entry13_epn_q <= (others => '0'); +entry13_class_q <= (others => '0'); +entry13_extclass_q <= (others => '0'); +entry13_hv_q <= '0'; +entry13_ds_q <= '0'; +entry13_thdid_q <= (others => '0'); +entry13_pid_q <= (others => '0'); +entry13_v_q <= '0'; +entry13_parity_q <= (others => '0'); +entry13_cmpmask_q <= (others => '0'); +entry14_size_q <= (others => '0'); +entry14_xbit_q <= '0'; +entry14_epn_q <= (others => '0'); +entry14_class_q <= (others => '0'); +entry14_extclass_q <= (others => '0'); +entry14_hv_q <= '0'; +entry14_ds_q <= '0'; +entry14_thdid_q <= (others => '0'); +entry14_pid_q <= (others => '0'); +entry14_v_q <= '0'; +entry14_parity_q <= (others => '0'); +entry14_cmpmask_q <= (others => '0'); +entry15_size_q <= (others => '0'); +entry15_xbit_q <= '0'; +entry15_epn_q <= (others => '0'); +entry15_class_q <= (others => '0'); +entry15_extclass_q <= (others => '0'); +entry15_hv_q <= '0'; +entry15_ds_q <= '0'; +entry15_thdid_q <= (others => '0'); +entry15_pid_q <= (others => '0'); +entry15_v_q <= '0'; +entry15_parity_q <= (others => '0'); +entry15_cmpmask_q <= (others => '0'); +entry16_size_q <= (others => '0'); +entry16_xbit_q <= '0'; +entry16_epn_q <= (others => '0'); +entry16_class_q <= (others => '0'); +entry16_extclass_q <= (others => '0'); +entry16_hv_q <= '0'; +entry16_ds_q <= '0'; +entry16_thdid_q <= (others => '0'); +entry16_pid_q <= (others => '0'); +entry16_v_q <= '0'; +entry16_parity_q <= (others => '0'); +entry16_cmpmask_q <= (others => '0'); +entry17_size_q <= (others => '0'); +entry17_xbit_q <= '0'; +entry17_epn_q <= (others => '0'); +entry17_class_q <= (others => '0'); +entry17_extclass_q <= (others => '0'); +entry17_hv_q <= '0'; +entry17_ds_q <= '0'; +entry17_thdid_q <= (others => '0'); +entry17_pid_q <= (others => '0'); +entry17_v_q <= '0'; +entry17_parity_q <= (others => '0'); +entry17_cmpmask_q <= (others => '0'); +entry18_size_q <= (others => '0'); +entry18_xbit_q <= '0'; +entry18_epn_q <= (others => '0'); +entry18_class_q <= (others => '0'); +entry18_extclass_q <= (others => '0'); +entry18_hv_q <= '0'; +entry18_ds_q <= '0'; +entry18_thdid_q <= (others => '0'); +entry18_pid_q <= (others => '0'); +entry18_v_q <= '0'; +entry18_parity_q <= (others => '0'); +entry18_cmpmask_q <= (others => '0'); +entry19_size_q <= (others => '0'); +entry19_xbit_q <= '0'; +entry19_epn_q <= (others => '0'); +entry19_class_q <= (others => '0'); +entry19_extclass_q <= (others => '0'); +entry19_hv_q <= '0'; +entry19_ds_q <= '0'; +entry19_thdid_q <= (others => '0'); +entry19_pid_q <= (others => '0'); +entry19_v_q <= '0'; +entry19_parity_q <= (others => '0'); +entry19_cmpmask_q <= (others => '0'); +entry20_size_q <= (others => '0'); +entry20_xbit_q <= '0'; +entry20_epn_q <= (others => '0'); +entry20_class_q <= (others => '0'); +entry20_extclass_q <= (others => '0'); +entry20_hv_q <= '0'; +entry20_ds_q <= '0'; +entry20_thdid_q <= (others => '0'); +entry20_pid_q <= (others => '0'); +entry20_v_q <= '0'; +entry20_parity_q <= (others => '0'); +entry20_cmpmask_q <= (others => '0'); +entry21_size_q <= (others => '0'); +entry21_xbit_q <= '0'; +entry21_epn_q <= (others => '0'); +entry21_class_q <= (others => '0'); +entry21_extclass_q <= (others => '0'); +entry21_hv_q <= '0'; +entry21_ds_q <= '0'; +entry21_thdid_q <= (others => '0'); +entry21_pid_q <= (others => '0'); +entry21_v_q <= '0'; +entry21_parity_q <= (others => '0'); +entry21_cmpmask_q <= (others => '0'); +entry22_size_q <= (others => '0'); +entry22_xbit_q <= '0'; +entry22_epn_q <= (others => '0'); +entry22_class_q <= (others => '0'); +entry22_extclass_q <= (others => '0'); +entry22_hv_q <= '0'; +entry22_ds_q <= '0'; +entry22_thdid_q <= (others => '0'); +entry22_pid_q <= (others => '0'); +entry22_v_q <= '0'; +entry22_parity_q <= (others => '0'); +entry22_cmpmask_q <= (others => '0'); +entry23_size_q <= (others => '0'); +entry23_xbit_q <= '0'; +entry23_epn_q <= (others => '0'); +entry23_class_q <= (others => '0'); +entry23_extclass_q <= (others => '0'); +entry23_hv_q <= '0'; +entry23_ds_q <= '0'; +entry23_thdid_q <= (others => '0'); +entry23_pid_q <= (others => '0'); +entry23_v_q <= '0'; +entry23_parity_q <= (others => '0'); +entry23_cmpmask_q <= (others => '0'); +entry24_size_q <= (others => '0'); +entry24_xbit_q <= '0'; +entry24_epn_q <= (others => '0'); +entry24_class_q <= (others => '0'); +entry24_extclass_q <= (others => '0'); +entry24_hv_q <= '0'; +entry24_ds_q <= '0'; +entry24_thdid_q <= (others => '0'); +entry24_pid_q <= (others => '0'); +entry24_v_q <= '0'; +entry24_parity_q <= (others => '0'); +entry24_cmpmask_q <= (others => '0'); +entry25_size_q <= (others => '0'); +entry25_xbit_q <= '0'; +entry25_epn_q <= (others => '0'); +entry25_class_q <= (others => '0'); +entry25_extclass_q <= (others => '0'); +entry25_hv_q <= '0'; +entry25_ds_q <= '0'; +entry25_thdid_q <= (others => '0'); +entry25_pid_q <= (others => '0'); +entry25_v_q <= '0'; +entry25_parity_q <= (others => '0'); +entry25_cmpmask_q <= (others => '0'); +entry26_size_q <= (others => '0'); +entry26_xbit_q <= '0'; +entry26_epn_q <= (others => '0'); +entry26_class_q <= (others => '0'); +entry26_extclass_q <= (others => '0'); +entry26_hv_q <= '0'; +entry26_ds_q <= '0'; +entry26_thdid_q <= (others => '0'); +entry26_pid_q <= (others => '0'); +entry26_v_q <= '0'; +entry26_parity_q <= (others => '0'); +entry26_cmpmask_q <= (others => '0'); +entry27_size_q <= (others => '0'); +entry27_xbit_q <= '0'; +entry27_epn_q <= (others => '0'); +entry27_class_q <= (others => '0'); +entry27_extclass_q <= (others => '0'); +entry27_hv_q <= '0'; +entry27_ds_q <= '0'; +entry27_thdid_q <= (others => '0'); +entry27_pid_q <= (others => '0'); +entry27_v_q <= '0'; +entry27_parity_q <= (others => '0'); +entry27_cmpmask_q <= (others => '0'); +entry28_size_q <= (others => '0'); +entry28_xbit_q <= '0'; +entry28_epn_q <= (others => '0'); +entry28_class_q <= (others => '0'); +entry28_extclass_q <= (others => '0'); +entry28_hv_q <= '0'; +entry28_ds_q <= '0'; +entry28_thdid_q <= (others => '0'); +entry28_pid_q <= (others => '0'); +entry28_v_q <= '0'; +entry28_parity_q <= (others => '0'); +entry28_cmpmask_q <= (others => '0'); +entry29_size_q <= (others => '0'); +entry29_xbit_q <= '0'; +entry29_epn_q <= (others => '0'); +entry29_class_q <= (others => '0'); +entry29_extclass_q <= (others => '0'); +entry29_hv_q <= '0'; +entry29_ds_q <= '0'; +entry29_thdid_q <= (others => '0'); +entry29_pid_q <= (others => '0'); +entry29_v_q <= '0'; +entry29_parity_q <= (others => '0'); +entry29_cmpmask_q <= (others => '0'); +entry30_size_q <= (others => '0'); +entry30_xbit_q <= '0'; +entry30_epn_q <= (others => '0'); +entry30_class_q <= (others => '0'); +entry30_extclass_q <= (others => '0'); +entry30_hv_q <= '0'; +entry30_ds_q <= '0'; +entry30_thdid_q <= (others => '0'); +entry30_pid_q <= (others => '0'); +entry30_v_q <= '0'; +entry30_parity_q <= (others => '0'); +entry30_cmpmask_q <= (others => '0'); +entry31_size_q <= (others => '0'); +entry31_xbit_q <= '0'; +entry31_epn_q <= (others => '0'); +entry31_class_q <= (others => '0'); +entry31_extclass_q <= (others => '0'); +entry31_hv_q <= '0'; +entry31_ds_q <= '0'; +entry31_thdid_q <= (others => '0'); +entry31_pid_q <= (others => '0'); +entry31_v_q <= '0'; +entry31_parity_q <= (others => '0'); +entry31_cmpmask_q <= (others => '0'); +else +cam_cmp_data_q <= cam_cmp_data_d; +rd_cam_data_q <= rd_cam_data_d; +rd_array_data_q <= rd_array_data_d; +entry_match_q <= entry_match_d; +cam_hit_entry_q <= cam_hit_entry_d; +cam_hit_q <= cam_hit_d; +cam_cmp_parity_q <= cam_cmp_parity_d; +comp_addr_np1_q <= comp_addr_np1_d; +rpn_np2_q <= rpn_np2_d; +attr_np2_q <= attr_np2_d; +entry0_size_q <= entry0_size_d; +entry0_xbit_q <= entry0_xbit_d; +entry0_epn_q <= entry0_epn_d; +entry0_class_q <= entry0_class_d; +entry0_extclass_q <= entry0_extclass_d; +entry0_hv_q <= entry0_hv_d; +entry0_ds_q <= entry0_ds_d; +entry0_thdid_q <= entry0_thdid_d; +entry0_pid_q <= entry0_pid_d; +entry0_v_q <= entry0_v_d; +entry0_parity_q <= entry0_parity_d; +entry0_cmpmask_q <= entry0_cmpmask_d; +entry1_size_q <= entry1_size_d; +entry1_xbit_q <= entry1_xbit_d; +entry1_epn_q <= entry1_epn_d; +entry1_class_q <= entry1_class_d; +entry1_extclass_q <= entry1_extclass_d; +entry1_hv_q <= entry1_hv_d; +entry1_ds_q <= entry1_ds_d; +entry1_thdid_q <= entry1_thdid_d; +entry1_pid_q <= entry1_pid_d; +entry1_v_q <= entry1_v_d; +entry1_parity_q <= entry1_parity_d; +entry1_cmpmask_q <= entry1_cmpmask_d; +entry2_size_q <= entry2_size_d; +entry2_xbit_q <= entry2_xbit_d; +entry2_epn_q <= entry2_epn_d; +entry2_class_q <= entry2_class_d; +entry2_extclass_q <= entry2_extclass_d; +entry2_hv_q <= entry2_hv_d; +entry2_ds_q <= entry2_ds_d; +entry2_thdid_q <= entry2_thdid_d; +entry2_pid_q <= entry2_pid_d; +entry2_v_q <= entry2_v_d; +entry2_parity_q <= entry2_parity_d; +entry2_cmpmask_q <= entry2_cmpmask_d; +entry3_size_q <= entry3_size_d; +entry3_xbit_q <= entry3_xbit_d; +entry3_epn_q <= entry3_epn_d; +entry3_class_q <= entry3_class_d; +entry3_extclass_q <= entry3_extclass_d; +entry3_hv_q <= entry3_hv_d; +entry3_ds_q <= entry3_ds_d; +entry3_thdid_q <= entry3_thdid_d; +entry3_pid_q <= entry3_pid_d; +entry3_v_q <= entry3_v_d; +entry3_parity_q <= entry3_parity_d; +entry3_cmpmask_q <= entry3_cmpmask_d; +entry4_size_q <= entry4_size_d; +entry4_xbit_q <= entry4_xbit_d; +entry4_epn_q <= entry4_epn_d; +entry4_class_q <= entry4_class_d; +entry4_extclass_q <= entry4_extclass_d; +entry4_hv_q <= entry4_hv_d; +entry4_ds_q <= entry4_ds_d; +entry4_thdid_q <= entry4_thdid_d; +entry4_pid_q <= entry4_pid_d; +entry4_v_q <= entry4_v_d; +entry4_parity_q <= entry4_parity_d; +entry4_cmpmask_q <= entry4_cmpmask_d; +entry5_size_q <= entry5_size_d; +entry5_xbit_q <= entry5_xbit_d; +entry5_epn_q <= entry5_epn_d; +entry5_class_q <= entry5_class_d; +entry5_extclass_q <= entry5_extclass_d; +entry5_hv_q <= entry5_hv_d; +entry5_ds_q <= entry5_ds_d; +entry5_thdid_q <= entry5_thdid_d; +entry5_pid_q <= entry5_pid_d; +entry5_v_q <= entry5_v_d; +entry5_parity_q <= entry5_parity_d; +entry5_cmpmask_q <= entry5_cmpmask_d; +entry6_size_q <= entry6_size_d; +entry6_xbit_q <= entry6_xbit_d; +entry6_epn_q <= entry6_epn_d; +entry6_class_q <= entry6_class_d; +entry6_extclass_q <= entry6_extclass_d; +entry6_hv_q <= entry6_hv_d; +entry6_ds_q <= entry6_ds_d; +entry6_thdid_q <= entry6_thdid_d; +entry6_pid_q <= entry6_pid_d; +entry6_v_q <= entry6_v_d; +entry6_parity_q <= entry6_parity_d; +entry6_cmpmask_q <= entry6_cmpmask_d; +entry7_size_q <= entry7_size_d; +entry7_xbit_q <= entry7_xbit_d; +entry7_epn_q <= entry7_epn_d; +entry7_class_q <= entry7_class_d; +entry7_extclass_q <= entry7_extclass_d; +entry7_hv_q <= entry7_hv_d; +entry7_ds_q <= entry7_ds_d; +entry7_thdid_q <= entry7_thdid_d; +entry7_pid_q <= entry7_pid_d; +entry7_v_q <= entry7_v_d; +entry7_parity_q <= entry7_parity_d; +entry7_cmpmask_q <= entry7_cmpmask_d; +entry8_size_q <= entry8_size_d; +entry8_xbit_q <= entry8_xbit_d; +entry8_epn_q <= entry8_epn_d; +entry8_class_q <= entry8_class_d; +entry8_extclass_q <= entry8_extclass_d; +entry8_hv_q <= entry8_hv_d; +entry8_ds_q <= entry8_ds_d; +entry8_thdid_q <= entry8_thdid_d; +entry8_pid_q <= entry8_pid_d; +entry8_v_q <= entry8_v_d; +entry8_parity_q <= entry8_parity_d; +entry8_cmpmask_q <= entry8_cmpmask_d; +entry9_size_q <= entry9_size_d; +entry9_xbit_q <= entry9_xbit_d; +entry9_epn_q <= entry9_epn_d; +entry9_class_q <= entry9_class_d; +entry9_extclass_q <= entry9_extclass_d; +entry9_hv_q <= entry9_hv_d; +entry9_ds_q <= entry9_ds_d; +entry9_thdid_q <= entry9_thdid_d; +entry9_pid_q <= entry9_pid_d; +entry9_v_q <= entry9_v_d; +entry9_parity_q <= entry9_parity_d; +entry9_cmpmask_q <= entry9_cmpmask_d; +entry10_size_q <= entry10_size_d; +entry10_xbit_q <= entry10_xbit_d; +entry10_epn_q <= entry10_epn_d; +entry10_class_q <= entry10_class_d; +entry10_extclass_q <= entry10_extclass_d; +entry10_hv_q <= entry10_hv_d; +entry10_ds_q <= entry10_ds_d; +entry10_thdid_q <= entry10_thdid_d; +entry10_pid_q <= entry10_pid_d; +entry10_v_q <= entry10_v_d; +entry10_parity_q <= entry10_parity_d; +entry10_cmpmask_q <= entry10_cmpmask_d; +entry11_size_q <= entry11_size_d; +entry11_xbit_q <= entry11_xbit_d; +entry11_epn_q <= entry11_epn_d; +entry11_class_q <= entry11_class_d; +entry11_extclass_q <= entry11_extclass_d; +entry11_hv_q <= entry11_hv_d; +entry11_ds_q <= entry11_ds_d; +entry11_thdid_q <= entry11_thdid_d; +entry11_pid_q <= entry11_pid_d; +entry11_v_q <= entry11_v_d; +entry11_parity_q <= entry11_parity_d; +entry11_cmpmask_q <= entry11_cmpmask_d; +entry12_size_q <= entry12_size_d; +entry12_xbit_q <= entry12_xbit_d; +entry12_epn_q <= entry12_epn_d; +entry12_class_q <= entry12_class_d; +entry12_extclass_q <= entry12_extclass_d; +entry12_hv_q <= entry12_hv_d; +entry12_ds_q <= entry12_ds_d; +entry12_thdid_q <= entry12_thdid_d; +entry12_pid_q <= entry12_pid_d; +entry12_v_q <= entry12_v_d; +entry12_parity_q <= entry12_parity_d; +entry12_cmpmask_q <= entry12_cmpmask_d; +entry13_size_q <= entry13_size_d; +entry13_xbit_q <= entry13_xbit_d; +entry13_epn_q <= entry13_epn_d; +entry13_class_q <= entry13_class_d; +entry13_extclass_q <= entry13_extclass_d; +entry13_hv_q <= entry13_hv_d; +entry13_ds_q <= entry13_ds_d; +entry13_thdid_q <= entry13_thdid_d; +entry13_pid_q <= entry13_pid_d; +entry13_v_q <= entry13_v_d; +entry13_parity_q <= entry13_parity_d; +entry13_cmpmask_q <= entry13_cmpmask_d; +entry14_size_q <= entry14_size_d; +entry14_xbit_q <= entry14_xbit_d; +entry14_epn_q <= entry14_epn_d; +entry14_class_q <= entry14_class_d; +entry14_extclass_q <= entry14_extclass_d; +entry14_hv_q <= entry14_hv_d; +entry14_ds_q <= entry14_ds_d; +entry14_thdid_q <= entry14_thdid_d; +entry14_pid_q <= entry14_pid_d; +entry14_v_q <= entry14_v_d; +entry14_parity_q <= entry14_parity_d; +entry14_cmpmask_q <= entry14_cmpmask_d; +entry15_size_q <= entry15_size_d; +entry15_xbit_q <= entry15_xbit_d; +entry15_epn_q <= entry15_epn_d; +entry15_class_q <= entry15_class_d; +entry15_extclass_q <= entry15_extclass_d; +entry15_hv_q <= entry15_hv_d; +entry15_ds_q <= entry15_ds_d; +entry15_thdid_q <= entry15_thdid_d; +entry15_pid_q <= entry15_pid_d; +entry15_v_q <= entry15_v_d; +entry15_parity_q <= entry15_parity_d; +entry15_cmpmask_q <= entry15_cmpmask_d; +entry16_size_q <= entry16_size_d; +entry16_xbit_q <= entry16_xbit_d; +entry16_epn_q <= entry16_epn_d; +entry16_class_q <= entry16_class_d; +entry16_extclass_q <= entry16_extclass_d; +entry16_hv_q <= entry16_hv_d; +entry16_ds_q <= entry16_ds_d; +entry16_thdid_q <= entry16_thdid_d; +entry16_pid_q <= entry16_pid_d; +entry16_v_q <= entry16_v_d; +entry16_parity_q <= entry16_parity_d; +entry16_cmpmask_q <= entry16_cmpmask_d; +entry17_size_q <= entry17_size_d; +entry17_xbit_q <= entry17_xbit_d; +entry17_epn_q <= entry17_epn_d; +entry17_class_q <= entry17_class_d; +entry17_extclass_q <= entry17_extclass_d; +entry17_hv_q <= entry17_hv_d; +entry17_ds_q <= entry17_ds_d; +entry17_thdid_q <= entry17_thdid_d; +entry17_pid_q <= entry17_pid_d; +entry17_v_q <= entry17_v_d; +entry17_parity_q <= entry17_parity_d; +entry17_cmpmask_q <= entry17_cmpmask_d; +entry18_size_q <= entry18_size_d; +entry18_xbit_q <= entry18_xbit_d; +entry18_epn_q <= entry18_epn_d; +entry18_class_q <= entry18_class_d; +entry18_extclass_q <= entry18_extclass_d; +entry18_hv_q <= entry18_hv_d; +entry18_ds_q <= entry18_ds_d; +entry18_thdid_q <= entry18_thdid_d; +entry18_pid_q <= entry18_pid_d; +entry18_v_q <= entry18_v_d; +entry18_parity_q <= entry18_parity_d; +entry18_cmpmask_q <= entry18_cmpmask_d; +entry19_size_q <= entry19_size_d; +entry19_xbit_q <= entry19_xbit_d; +entry19_epn_q <= entry19_epn_d; +entry19_class_q <= entry19_class_d; +entry19_extclass_q <= entry19_extclass_d; +entry19_hv_q <= entry19_hv_d; +entry19_ds_q <= entry19_ds_d; +entry19_thdid_q <= entry19_thdid_d; +entry19_pid_q <= entry19_pid_d; +entry19_v_q <= entry19_v_d; +entry19_parity_q <= entry19_parity_d; +entry19_cmpmask_q <= entry19_cmpmask_d; +entry20_size_q <= entry20_size_d; +entry20_xbit_q <= entry20_xbit_d; +entry20_epn_q <= entry20_epn_d; +entry20_class_q <= entry20_class_d; +entry20_extclass_q <= entry20_extclass_d; +entry20_hv_q <= entry20_hv_d; +entry20_ds_q <= entry20_ds_d; +entry20_thdid_q <= entry20_thdid_d; +entry20_pid_q <= entry20_pid_d; +entry20_v_q <= entry20_v_d; +entry20_parity_q <= entry20_parity_d; +entry20_cmpmask_q <= entry20_cmpmask_d; +entry21_size_q <= entry21_size_d; +entry21_xbit_q <= entry21_xbit_d; +entry21_epn_q <= entry21_epn_d; +entry21_class_q <= entry21_class_d; +entry21_extclass_q <= entry21_extclass_d; +entry21_hv_q <= entry21_hv_d; +entry21_ds_q <= entry21_ds_d; +entry21_thdid_q <= entry21_thdid_d; +entry21_pid_q <= entry21_pid_d; +entry21_v_q <= entry21_v_d; +entry21_parity_q <= entry21_parity_d; +entry21_cmpmask_q <= entry21_cmpmask_d; +entry22_size_q <= entry22_size_d; +entry22_xbit_q <= entry22_xbit_d; +entry22_epn_q <= entry22_epn_d; +entry22_class_q <= entry22_class_d; +entry22_extclass_q <= entry22_extclass_d; +entry22_hv_q <= entry22_hv_d; +entry22_ds_q <= entry22_ds_d; +entry22_thdid_q <= entry22_thdid_d; +entry22_pid_q <= entry22_pid_d; +entry22_v_q <= entry22_v_d; +entry22_parity_q <= entry22_parity_d; +entry22_cmpmask_q <= entry22_cmpmask_d; +entry23_size_q <= entry23_size_d; +entry23_xbit_q <= entry23_xbit_d; +entry23_epn_q <= entry23_epn_d; +entry23_class_q <= entry23_class_d; +entry23_extclass_q <= entry23_extclass_d; +entry23_hv_q <= entry23_hv_d; +entry23_ds_q <= entry23_ds_d; +entry23_thdid_q <= entry23_thdid_d; +entry23_pid_q <= entry23_pid_d; +entry23_v_q <= entry23_v_d; +entry23_parity_q <= entry23_parity_d; +entry23_cmpmask_q <= entry23_cmpmask_d; +entry24_size_q <= entry24_size_d; +entry24_xbit_q <= entry24_xbit_d; +entry24_epn_q <= entry24_epn_d; +entry24_class_q <= entry24_class_d; +entry24_extclass_q <= entry24_extclass_d; +entry24_hv_q <= entry24_hv_d; +entry24_ds_q <= entry24_ds_d; +entry24_thdid_q <= entry24_thdid_d; +entry24_pid_q <= entry24_pid_d; +entry24_v_q <= entry24_v_d; +entry24_parity_q <= entry24_parity_d; +entry24_cmpmask_q <= entry24_cmpmask_d; +entry25_size_q <= entry25_size_d; +entry25_xbit_q <= entry25_xbit_d; +entry25_epn_q <= entry25_epn_d; +entry25_class_q <= entry25_class_d; +entry25_extclass_q <= entry25_extclass_d; +entry25_hv_q <= entry25_hv_d; +entry25_ds_q <= entry25_ds_d; +entry25_thdid_q <= entry25_thdid_d; +entry25_pid_q <= entry25_pid_d; +entry25_v_q <= entry25_v_d; +entry25_parity_q <= entry25_parity_d; +entry25_cmpmask_q <= entry25_cmpmask_d; +entry26_size_q <= entry26_size_d; +entry26_xbit_q <= entry26_xbit_d; +entry26_epn_q <= entry26_epn_d; +entry26_class_q <= entry26_class_d; +entry26_extclass_q <= entry26_extclass_d; +entry26_hv_q <= entry26_hv_d; +entry26_ds_q <= entry26_ds_d; +entry26_thdid_q <= entry26_thdid_d; +entry26_pid_q <= entry26_pid_d; +entry26_v_q <= entry26_v_d; +entry26_parity_q <= entry26_parity_d; +entry26_cmpmask_q <= entry26_cmpmask_d; +entry27_size_q <= entry27_size_d; +entry27_xbit_q <= entry27_xbit_d; +entry27_epn_q <= entry27_epn_d; +entry27_class_q <= entry27_class_d; +entry27_extclass_q <= entry27_extclass_d; +entry27_hv_q <= entry27_hv_d; +entry27_ds_q <= entry27_ds_d; +entry27_thdid_q <= entry27_thdid_d; +entry27_pid_q <= entry27_pid_d; +entry27_v_q <= entry27_v_d; +entry27_parity_q <= entry27_parity_d; +entry27_cmpmask_q <= entry27_cmpmask_d; +entry28_size_q <= entry28_size_d; +entry28_xbit_q <= entry28_xbit_d; +entry28_epn_q <= entry28_epn_d; +entry28_class_q <= entry28_class_d; +entry28_extclass_q <= entry28_extclass_d; +entry28_hv_q <= entry28_hv_d; +entry28_ds_q <= entry28_ds_d; +entry28_thdid_q <= entry28_thdid_d; +entry28_pid_q <= entry28_pid_d; +entry28_v_q <= entry28_v_d; +entry28_parity_q <= entry28_parity_d; +entry28_cmpmask_q <= entry28_cmpmask_d; +entry29_size_q <= entry29_size_d; +entry29_xbit_q <= entry29_xbit_d; +entry29_epn_q <= entry29_epn_d; +entry29_class_q <= entry29_class_d; +entry29_extclass_q <= entry29_extclass_d; +entry29_hv_q <= entry29_hv_d; +entry29_ds_q <= entry29_ds_d; +entry29_thdid_q <= entry29_thdid_d; +entry29_pid_q <= entry29_pid_d; +entry29_v_q <= entry29_v_d; +entry29_parity_q <= entry29_parity_d; +entry29_cmpmask_q <= entry29_cmpmask_d; +entry30_size_q <= entry30_size_d; +entry30_xbit_q <= entry30_xbit_d; +entry30_epn_q <= entry30_epn_d; +entry30_class_q <= entry30_class_d; +entry30_extclass_q <= entry30_extclass_d; +entry30_hv_q <= entry30_hv_d; +entry30_ds_q <= entry30_ds_d; +entry30_thdid_q <= entry30_thdid_d; +entry30_pid_q <= entry30_pid_d; +entry30_v_q <= entry30_v_d; +entry30_parity_q <= entry30_parity_d; +entry30_cmpmask_q <= entry30_cmpmask_d; +entry31_size_q <= entry31_size_d; +entry31_xbit_q <= entry31_xbit_d; +entry31_epn_q <= entry31_epn_d; +entry31_class_q <= entry31_class_d; +entry31_extclass_q <= entry31_extclass_d; +entry31_hv_q <= entry31_hv_d; +entry31_ds_q <= entry31_ds_d; +entry31_thdid_q <= entry31_thdid_d; +entry31_pid_q <= entry31_pid_d; +entry31_v_q <= entry31_v_d; +entry31_parity_q <= entry31_parity_d; +entry31_cmpmask_q <= entry31_cmpmask_d; +end if; +end if; +end process; +comp_addr_np1_d <= comp_addr(52-rpn_width to 51); +cam_hit_d <= '1' when (match_vec /= "00000000000000000000000000000000" and comp_request='1') else '0'; +cam_hit_entry_d <= "00001" when match_vec(0 to 1)="01" else + "00010" when match_vec(0 to 2)="001" else + "00011" when match_vec(0 to 3)="0001" else + "00100" when match_vec(0 to 4)="00001" else + "00101" when match_vec(0 to 5)="000001" else + "00110" when match_vec(0 to 6)="0000001" else + "00111" when match_vec(0 to 7)="00000001" else + "01000" when match_vec(0 to 8)="000000001" else + "01001" when match_vec(0 to 9)="0000000001" else + "01010" when match_vec(0 to 10)="00000000001" else + "01011" when match_vec(0 to 11)="000000000001" else + "01100" when match_vec(0 to 12)="0000000000001" else + "01101" when match_vec(0 to 13)="00000000000001" else + "01110" when match_vec(0 to 14)="000000000000001" else + "01111" when match_vec(0 to 15)="0000000000000001" else + "10000" when match_vec(0 to 16)="00000000000000001" else + "10001" when match_vec(0 to 17)="000000000000000001" else + "10010" when match_vec(0 to 18)="0000000000000000001" else + "10011" when match_vec(0 to 19)="00000000000000000001" else + "10100" when match_vec(0 to 20)="000000000000000000001" else + "10101" when match_vec(0 to 21)="0000000000000000000001" else + "10110" when match_vec(0 to 22)="00000000000000000000001" else + "10111" when match_vec(0 to 23)="000000000000000000000001" else + "11000" when match_vec(0 to 24)="0000000000000000000000001" else + "11001" when match_vec(0 to 25)="00000000000000000000000001" else + "11010" when match_vec(0 to 26)="000000000000000000000000001" else + "11011" when match_vec(0 to 27)="0000000000000000000000000001" else + "11100" when match_vec(0 to 28)="00000000000000000000000000001" else + "11101" when match_vec(0 to 29)="000000000000000000000000000001" else + "11110" when match_vec(0 to 30)="0000000000000000000000000000001" else + "11111" when match_vec(0 to 31)="00000000000000000000000000000001" else + "00000"; +entry_match_d <= match_vec when (comp_request='1') else (others => '0'); +wr_entry0_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="00000")) else '0'; +wr_entry0_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="00000")) else '0'; +with wr_entry0_sel(0) select + entry0_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry0_epn_q(0 to 31) when others; +with wr_entry0_sel(0) select + entry0_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry0_epn_q(32 to 51) when others; +with wr_entry0_sel(0) select + entry0_xbit_d <= wr_cam_data(52) when '1', + entry0_xbit_q when others; +with wr_entry0_sel(0) select + entry0_size_d <= wr_cam_data(53 to 55) when '1', + entry0_size_q(0 to 2) when others; +with wr_entry0_sel(0) select + entry0_class_d <= wr_cam_data(61 to 62) when '1', + entry0_class_q(0 to 1) when others; +with wr_entry0_sel(1) select + entry0_extclass_d <= wr_cam_data(63 to 64) when '1', + entry0_extclass_q(0 to 1) when others; +with wr_entry0_sel(1) select + entry0_hv_d <= wr_cam_data(65) when '1', + entry0_hv_q when others; +with wr_entry0_sel(1) select + entry0_ds_d <= wr_cam_data(66) when '1', + entry0_ds_q when others; +with wr_entry0_sel(1) select + entry0_pid_d <= wr_cam_data(67 to 74) when '1', + entry0_pid_q(0 to 7) when others; +with wr_entry0_sel(0) select + entry0_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry0_cmpmask_q when others; +with wr_entry0_sel(0) select + entry0_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry0_parity_q(0 to 3) when others; +with wr_entry0_sel(0) select + entry0_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry0_parity_q(4 to 6) when others; +with wr_entry0_sel(0) select + entry0_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry0_parity_q(7) when others; +with wr_entry0_sel(1) select + entry0_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry0_parity_q(8) when others; +with wr_entry0_sel(1) select + entry0_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry0_parity_q(9) when others; +wr_entry1_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="00001")) else '0'; +wr_entry1_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="00001")) else '0'; +with wr_entry1_sel(0) select + entry1_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry1_epn_q(0 to 31) when others; +with wr_entry1_sel(0) select + entry1_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry1_epn_q(32 to 51) when others; +with wr_entry1_sel(0) select + entry1_xbit_d <= wr_cam_data(52) when '1', + entry1_xbit_q when others; +with wr_entry1_sel(0) select + entry1_size_d <= wr_cam_data(53 to 55) when '1', + entry1_size_q(0 to 2) when others; +with wr_entry1_sel(0) select + entry1_class_d <= wr_cam_data(61 to 62) when '1', + entry1_class_q(0 to 1) when others; +with wr_entry1_sel(1) select + entry1_extclass_d <= wr_cam_data(63 to 64) when '1', + entry1_extclass_q(0 to 1) when others; +with wr_entry1_sel(1) select + entry1_hv_d <= wr_cam_data(65) when '1', + entry1_hv_q when others; +with wr_entry1_sel(1) select + entry1_ds_d <= wr_cam_data(66) when '1', + entry1_ds_q when others; +with wr_entry1_sel(1) select + entry1_pid_d <= wr_cam_data(67 to 74) when '1', + entry1_pid_q(0 to 7) when others; +with wr_entry1_sel(0) select + entry1_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry1_cmpmask_q when others; +with wr_entry1_sel(0) select + entry1_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry1_parity_q(0 to 3) when others; +with wr_entry1_sel(0) select + entry1_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry1_parity_q(4 to 6) when others; +with wr_entry1_sel(0) select + entry1_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry1_parity_q(7) when others; +with wr_entry1_sel(1) select + entry1_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry1_parity_q(8) when others; +with wr_entry1_sel(1) select + entry1_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry1_parity_q(9) when others; +wr_entry2_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="00010")) else '0'; +wr_entry2_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="00010")) else '0'; +with wr_entry2_sel(0) select + entry2_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry2_epn_q(0 to 31) when others; +with wr_entry2_sel(0) select + entry2_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry2_epn_q(32 to 51) when others; +with wr_entry2_sel(0) select + entry2_xbit_d <= wr_cam_data(52) when '1', + entry2_xbit_q when others; +with wr_entry2_sel(0) select + entry2_size_d <= wr_cam_data(53 to 55) when '1', + entry2_size_q(0 to 2) when others; +with wr_entry2_sel(0) select + entry2_class_d <= wr_cam_data(61 to 62) when '1', + entry2_class_q(0 to 1) when others; +with wr_entry2_sel(1) select + entry2_extclass_d <= wr_cam_data(63 to 64) when '1', + entry2_extclass_q(0 to 1) when others; +with wr_entry2_sel(1) select + entry2_hv_d <= wr_cam_data(65) when '1', + entry2_hv_q when others; +with wr_entry2_sel(1) select + entry2_ds_d <= wr_cam_data(66) when '1', + entry2_ds_q when others; +with wr_entry2_sel(1) select + entry2_pid_d <= wr_cam_data(67 to 74) when '1', + entry2_pid_q(0 to 7) when others; +with wr_entry2_sel(0) select + entry2_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry2_cmpmask_q when others; +with wr_entry2_sel(0) select + entry2_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry2_parity_q(0 to 3) when others; +with wr_entry2_sel(0) select + entry2_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry2_parity_q(4 to 6) when others; +with wr_entry2_sel(0) select + entry2_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry2_parity_q(7) when others; +with wr_entry2_sel(1) select + entry2_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry2_parity_q(8) when others; +with wr_entry2_sel(1) select + entry2_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry2_parity_q(9) when others; +wr_entry3_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="00011")) else '0'; +wr_entry3_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="00011")) else '0'; +with wr_entry3_sel(0) select + entry3_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry3_epn_q(0 to 31) when others; +with wr_entry3_sel(0) select + entry3_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry3_epn_q(32 to 51) when others; +with wr_entry3_sel(0) select + entry3_xbit_d <= wr_cam_data(52) when '1', + entry3_xbit_q when others; +with wr_entry3_sel(0) select + entry3_size_d <= wr_cam_data(53 to 55) when '1', + entry3_size_q(0 to 2) when others; +with wr_entry3_sel(0) select + entry3_class_d <= wr_cam_data(61 to 62) when '1', + entry3_class_q(0 to 1) when others; +with wr_entry3_sel(1) select + entry3_extclass_d <= wr_cam_data(63 to 64) when '1', + entry3_extclass_q(0 to 1) when others; +with wr_entry3_sel(1) select + entry3_hv_d <= wr_cam_data(65) when '1', + entry3_hv_q when others; +with wr_entry3_sel(1) select + entry3_ds_d <= wr_cam_data(66) when '1', + entry3_ds_q when others; +with wr_entry3_sel(1) select + entry3_pid_d <= wr_cam_data(67 to 74) when '1', + entry3_pid_q(0 to 7) when others; +with wr_entry3_sel(0) select + entry3_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry3_cmpmask_q when others; +with wr_entry3_sel(0) select + entry3_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry3_parity_q(0 to 3) when others; +with wr_entry3_sel(0) select + entry3_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry3_parity_q(4 to 6) when others; +with wr_entry3_sel(0) select + entry3_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry3_parity_q(7) when others; +with wr_entry3_sel(1) select + entry3_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry3_parity_q(8) when others; +with wr_entry3_sel(1) select + entry3_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry3_parity_q(9) when others; +wr_entry4_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="00100")) else '0'; +wr_entry4_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="00100")) else '0'; +with wr_entry4_sel(0) select + entry4_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry4_epn_q(0 to 31) when others; +with wr_entry4_sel(0) select + entry4_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry4_epn_q(32 to 51) when others; +with wr_entry4_sel(0) select + entry4_xbit_d <= wr_cam_data(52) when '1', + entry4_xbit_q when others; +with wr_entry4_sel(0) select + entry4_size_d <= wr_cam_data(53 to 55) when '1', + entry4_size_q(0 to 2) when others; +with wr_entry4_sel(0) select + entry4_class_d <= wr_cam_data(61 to 62) when '1', + entry4_class_q(0 to 1) when others; +with wr_entry4_sel(1) select + entry4_extclass_d <= wr_cam_data(63 to 64) when '1', + entry4_extclass_q(0 to 1) when others; +with wr_entry4_sel(1) select + entry4_hv_d <= wr_cam_data(65) when '1', + entry4_hv_q when others; +with wr_entry4_sel(1) select + entry4_ds_d <= wr_cam_data(66) when '1', + entry4_ds_q when others; +with wr_entry4_sel(1) select + entry4_pid_d <= wr_cam_data(67 to 74) when '1', + entry4_pid_q(0 to 7) when others; +with wr_entry4_sel(0) select + entry4_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry4_cmpmask_q when others; +with wr_entry4_sel(0) select + entry4_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry4_parity_q(0 to 3) when others; +with wr_entry4_sel(0) select + entry4_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry4_parity_q(4 to 6) when others; +with wr_entry4_sel(0) select + entry4_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry4_parity_q(7) when others; +with wr_entry4_sel(1) select + entry4_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry4_parity_q(8) when others; +with wr_entry4_sel(1) select + entry4_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry4_parity_q(9) when others; +wr_entry5_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="00101")) else '0'; +wr_entry5_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="00101")) else '0'; +with wr_entry5_sel(0) select + entry5_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry5_epn_q(0 to 31) when others; +with wr_entry5_sel(0) select + entry5_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry5_epn_q(32 to 51) when others; +with wr_entry5_sel(0) select + entry5_xbit_d <= wr_cam_data(52) when '1', + entry5_xbit_q when others; +with wr_entry5_sel(0) select + entry5_size_d <= wr_cam_data(53 to 55) when '1', + entry5_size_q(0 to 2) when others; +with wr_entry5_sel(0) select + entry5_class_d <= wr_cam_data(61 to 62) when '1', + entry5_class_q(0 to 1) when others; +with wr_entry5_sel(1) select + entry5_extclass_d <= wr_cam_data(63 to 64) when '1', + entry5_extclass_q(0 to 1) when others; +with wr_entry5_sel(1) select + entry5_hv_d <= wr_cam_data(65) when '1', + entry5_hv_q when others; +with wr_entry5_sel(1) select + entry5_ds_d <= wr_cam_data(66) when '1', + entry5_ds_q when others; +with wr_entry5_sel(1) select + entry5_pid_d <= wr_cam_data(67 to 74) when '1', + entry5_pid_q(0 to 7) when others; +with wr_entry5_sel(0) select + entry5_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry5_cmpmask_q when others; +with wr_entry5_sel(0) select + entry5_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry5_parity_q(0 to 3) when others; +with wr_entry5_sel(0) select + entry5_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry5_parity_q(4 to 6) when others; +with wr_entry5_sel(0) select + entry5_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry5_parity_q(7) when others; +with wr_entry5_sel(1) select + entry5_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry5_parity_q(8) when others; +with wr_entry5_sel(1) select + entry5_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry5_parity_q(9) when others; +wr_entry6_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="00110")) else '0'; +wr_entry6_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="00110")) else '0'; +with wr_entry6_sel(0) select + entry6_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry6_epn_q(0 to 31) when others; +with wr_entry6_sel(0) select + entry6_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry6_epn_q(32 to 51) when others; +with wr_entry6_sel(0) select + entry6_xbit_d <= wr_cam_data(52) when '1', + entry6_xbit_q when others; +with wr_entry6_sel(0) select + entry6_size_d <= wr_cam_data(53 to 55) when '1', + entry6_size_q(0 to 2) when others; +with wr_entry6_sel(0) select + entry6_class_d <= wr_cam_data(61 to 62) when '1', + entry6_class_q(0 to 1) when others; +with wr_entry6_sel(1) select + entry6_extclass_d <= wr_cam_data(63 to 64) when '1', + entry6_extclass_q(0 to 1) when others; +with wr_entry6_sel(1) select + entry6_hv_d <= wr_cam_data(65) when '1', + entry6_hv_q when others; +with wr_entry6_sel(1) select + entry6_ds_d <= wr_cam_data(66) when '1', + entry6_ds_q when others; +with wr_entry6_sel(1) select + entry6_pid_d <= wr_cam_data(67 to 74) when '1', + entry6_pid_q(0 to 7) when others; +with wr_entry6_sel(0) select + entry6_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry6_cmpmask_q when others; +with wr_entry6_sel(0) select + entry6_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry6_parity_q(0 to 3) when others; +with wr_entry6_sel(0) select + entry6_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry6_parity_q(4 to 6) when others; +with wr_entry6_sel(0) select + entry6_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry6_parity_q(7) when others; +with wr_entry6_sel(1) select + entry6_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry6_parity_q(8) when others; +with wr_entry6_sel(1) select + entry6_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry6_parity_q(9) when others; +wr_entry7_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="00111")) else '0'; +wr_entry7_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="00111")) else '0'; +with wr_entry7_sel(0) select + entry7_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry7_epn_q(0 to 31) when others; +with wr_entry7_sel(0) select + entry7_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry7_epn_q(32 to 51) when others; +with wr_entry7_sel(0) select + entry7_xbit_d <= wr_cam_data(52) when '1', + entry7_xbit_q when others; +with wr_entry7_sel(0) select + entry7_size_d <= wr_cam_data(53 to 55) when '1', + entry7_size_q(0 to 2) when others; +with wr_entry7_sel(0) select + entry7_class_d <= wr_cam_data(61 to 62) when '1', + entry7_class_q(0 to 1) when others; +with wr_entry7_sel(1) select + entry7_extclass_d <= wr_cam_data(63 to 64) when '1', + entry7_extclass_q(0 to 1) when others; +with wr_entry7_sel(1) select + entry7_hv_d <= wr_cam_data(65) when '1', + entry7_hv_q when others; +with wr_entry7_sel(1) select + entry7_ds_d <= wr_cam_data(66) when '1', + entry7_ds_q when others; +with wr_entry7_sel(1) select + entry7_pid_d <= wr_cam_data(67 to 74) when '1', + entry7_pid_q(0 to 7) when others; +with wr_entry7_sel(0) select + entry7_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry7_cmpmask_q when others; +with wr_entry7_sel(0) select + entry7_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry7_parity_q(0 to 3) when others; +with wr_entry7_sel(0) select + entry7_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry7_parity_q(4 to 6) when others; +with wr_entry7_sel(0) select + entry7_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry7_parity_q(7) when others; +with wr_entry7_sel(1) select + entry7_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry7_parity_q(8) when others; +with wr_entry7_sel(1) select + entry7_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry7_parity_q(9) when others; +wr_entry8_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="01000")) else '0'; +wr_entry8_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="01000")) else '0'; +with wr_entry8_sel(0) select + entry8_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry8_epn_q(0 to 31) when others; +with wr_entry8_sel(0) select + entry8_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry8_epn_q(32 to 51) when others; +with wr_entry8_sel(0) select + entry8_xbit_d <= wr_cam_data(52) when '1', + entry8_xbit_q when others; +with wr_entry8_sel(0) select + entry8_size_d <= wr_cam_data(53 to 55) when '1', + entry8_size_q(0 to 2) when others; +with wr_entry8_sel(0) select + entry8_class_d <= wr_cam_data(61 to 62) when '1', + entry8_class_q(0 to 1) when others; +with wr_entry8_sel(1) select + entry8_extclass_d <= wr_cam_data(63 to 64) when '1', + entry8_extclass_q(0 to 1) when others; +with wr_entry8_sel(1) select + entry8_hv_d <= wr_cam_data(65) when '1', + entry8_hv_q when others; +with wr_entry8_sel(1) select + entry8_ds_d <= wr_cam_data(66) when '1', + entry8_ds_q when others; +with wr_entry8_sel(1) select + entry8_pid_d <= wr_cam_data(67 to 74) when '1', + entry8_pid_q(0 to 7) when others; +with wr_entry8_sel(0) select + entry8_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry8_cmpmask_q when others; +with wr_entry8_sel(0) select + entry8_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry8_parity_q(0 to 3) when others; +with wr_entry8_sel(0) select + entry8_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry8_parity_q(4 to 6) when others; +with wr_entry8_sel(0) select + entry8_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry8_parity_q(7) when others; +with wr_entry8_sel(1) select + entry8_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry8_parity_q(8) when others; +with wr_entry8_sel(1) select + entry8_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry8_parity_q(9) when others; +wr_entry9_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="01001")) else '0'; +wr_entry9_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="01001")) else '0'; +with wr_entry9_sel(0) select + entry9_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry9_epn_q(0 to 31) when others; +with wr_entry9_sel(0) select + entry9_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry9_epn_q(32 to 51) when others; +with wr_entry9_sel(0) select + entry9_xbit_d <= wr_cam_data(52) when '1', + entry9_xbit_q when others; +with wr_entry9_sel(0) select + entry9_size_d <= wr_cam_data(53 to 55) when '1', + entry9_size_q(0 to 2) when others; +with wr_entry9_sel(0) select + entry9_class_d <= wr_cam_data(61 to 62) when '1', + entry9_class_q(0 to 1) when others; +with wr_entry9_sel(1) select + entry9_extclass_d <= wr_cam_data(63 to 64) when '1', + entry9_extclass_q(0 to 1) when others; +with wr_entry9_sel(1) select + entry9_hv_d <= wr_cam_data(65) when '1', + entry9_hv_q when others; +with wr_entry9_sel(1) select + entry9_ds_d <= wr_cam_data(66) when '1', + entry9_ds_q when others; +with wr_entry9_sel(1) select + entry9_pid_d <= wr_cam_data(67 to 74) when '1', + entry9_pid_q(0 to 7) when others; +with wr_entry9_sel(0) select + entry9_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry9_cmpmask_q when others; +with wr_entry9_sel(0) select + entry9_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry9_parity_q(0 to 3) when others; +with wr_entry9_sel(0) select + entry9_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry9_parity_q(4 to 6) when others; +with wr_entry9_sel(0) select + entry9_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry9_parity_q(7) when others; +with wr_entry9_sel(1) select + entry9_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry9_parity_q(8) when others; +with wr_entry9_sel(1) select + entry9_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry9_parity_q(9) when others; +wr_entry10_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="01010")) else '0'; +wr_entry10_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="01010")) else '0'; +with wr_entry10_sel(0) select + entry10_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry10_epn_q(0 to 31) when others; +with wr_entry10_sel(0) select + entry10_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry10_epn_q(32 to 51) when others; +with wr_entry10_sel(0) select + entry10_xbit_d <= wr_cam_data(52) when '1', + entry10_xbit_q when others; +with wr_entry10_sel(0) select + entry10_size_d <= wr_cam_data(53 to 55) when '1', + entry10_size_q(0 to 2) when others; +with wr_entry10_sel(0) select + entry10_class_d <= wr_cam_data(61 to 62) when '1', + entry10_class_q(0 to 1) when others; +with wr_entry10_sel(1) select + entry10_extclass_d <= wr_cam_data(63 to 64) when '1', + entry10_extclass_q(0 to 1) when others; +with wr_entry10_sel(1) select + entry10_hv_d <= wr_cam_data(65) when '1', + entry10_hv_q when others; +with wr_entry10_sel(1) select + entry10_ds_d <= wr_cam_data(66) when '1', + entry10_ds_q when others; +with wr_entry10_sel(1) select + entry10_pid_d <= wr_cam_data(67 to 74) when '1', + entry10_pid_q(0 to 7) when others; +with wr_entry10_sel(0) select + entry10_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry10_cmpmask_q when others; +with wr_entry10_sel(0) select + entry10_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry10_parity_q(0 to 3) when others; +with wr_entry10_sel(0) select + entry10_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry10_parity_q(4 to 6) when others; +with wr_entry10_sel(0) select + entry10_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry10_parity_q(7) when others; +with wr_entry10_sel(1) select + entry10_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry10_parity_q(8) when others; +with wr_entry10_sel(1) select + entry10_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry10_parity_q(9) when others; +wr_entry11_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="01011")) else '0'; +wr_entry11_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="01011")) else '0'; +with wr_entry11_sel(0) select + entry11_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry11_epn_q(0 to 31) when others; +with wr_entry11_sel(0) select + entry11_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry11_epn_q(32 to 51) when others; +with wr_entry11_sel(0) select + entry11_xbit_d <= wr_cam_data(52) when '1', + entry11_xbit_q when others; +with wr_entry11_sel(0) select + entry11_size_d <= wr_cam_data(53 to 55) when '1', + entry11_size_q(0 to 2) when others; +with wr_entry11_sel(0) select + entry11_class_d <= wr_cam_data(61 to 62) when '1', + entry11_class_q(0 to 1) when others; +with wr_entry11_sel(1) select + entry11_extclass_d <= wr_cam_data(63 to 64) when '1', + entry11_extclass_q(0 to 1) when others; +with wr_entry11_sel(1) select + entry11_hv_d <= wr_cam_data(65) when '1', + entry11_hv_q when others; +with wr_entry11_sel(1) select + entry11_ds_d <= wr_cam_data(66) when '1', + entry11_ds_q when others; +with wr_entry11_sel(1) select + entry11_pid_d <= wr_cam_data(67 to 74) when '1', + entry11_pid_q(0 to 7) when others; +with wr_entry11_sel(0) select + entry11_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry11_cmpmask_q when others; +with wr_entry11_sel(0) select + entry11_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry11_parity_q(0 to 3) when others; +with wr_entry11_sel(0) select + entry11_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry11_parity_q(4 to 6) when others; +with wr_entry11_sel(0) select + entry11_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry11_parity_q(7) when others; +with wr_entry11_sel(1) select + entry11_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry11_parity_q(8) when others; +with wr_entry11_sel(1) select + entry11_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry11_parity_q(9) when others; +wr_entry12_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="01100")) else '0'; +wr_entry12_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="01100")) else '0'; +with wr_entry12_sel(0) select + entry12_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry12_epn_q(0 to 31) when others; +with wr_entry12_sel(0) select + entry12_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry12_epn_q(32 to 51) when others; +with wr_entry12_sel(0) select + entry12_xbit_d <= wr_cam_data(52) when '1', + entry12_xbit_q when others; +with wr_entry12_sel(0) select + entry12_size_d <= wr_cam_data(53 to 55) when '1', + entry12_size_q(0 to 2) when others; +with wr_entry12_sel(0) select + entry12_class_d <= wr_cam_data(61 to 62) when '1', + entry12_class_q(0 to 1) when others; +with wr_entry12_sel(1) select + entry12_extclass_d <= wr_cam_data(63 to 64) when '1', + entry12_extclass_q(0 to 1) when others; +with wr_entry12_sel(1) select + entry12_hv_d <= wr_cam_data(65) when '1', + entry12_hv_q when others; +with wr_entry12_sel(1) select + entry12_ds_d <= wr_cam_data(66) when '1', + entry12_ds_q when others; +with wr_entry12_sel(1) select + entry12_pid_d <= wr_cam_data(67 to 74) when '1', + entry12_pid_q(0 to 7) when others; +with wr_entry12_sel(0) select + entry12_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry12_cmpmask_q when others; +with wr_entry12_sel(0) select + entry12_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry12_parity_q(0 to 3) when others; +with wr_entry12_sel(0) select + entry12_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry12_parity_q(4 to 6) when others; +with wr_entry12_sel(0) select + entry12_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry12_parity_q(7) when others; +with wr_entry12_sel(1) select + entry12_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry12_parity_q(8) when others; +with wr_entry12_sel(1) select + entry12_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry12_parity_q(9) when others; +wr_entry13_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="01101")) else '0'; +wr_entry13_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="01101")) else '0'; +with wr_entry13_sel(0) select + entry13_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry13_epn_q(0 to 31) when others; +with wr_entry13_sel(0) select + entry13_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry13_epn_q(32 to 51) when others; +with wr_entry13_sel(0) select + entry13_xbit_d <= wr_cam_data(52) when '1', + entry13_xbit_q when others; +with wr_entry13_sel(0) select + entry13_size_d <= wr_cam_data(53 to 55) when '1', + entry13_size_q(0 to 2) when others; +with wr_entry13_sel(0) select + entry13_class_d <= wr_cam_data(61 to 62) when '1', + entry13_class_q(0 to 1) when others; +with wr_entry13_sel(1) select + entry13_extclass_d <= wr_cam_data(63 to 64) when '1', + entry13_extclass_q(0 to 1) when others; +with wr_entry13_sel(1) select + entry13_hv_d <= wr_cam_data(65) when '1', + entry13_hv_q when others; +with wr_entry13_sel(1) select + entry13_ds_d <= wr_cam_data(66) when '1', + entry13_ds_q when others; +with wr_entry13_sel(1) select + entry13_pid_d <= wr_cam_data(67 to 74) when '1', + entry13_pid_q(0 to 7) when others; +with wr_entry13_sel(0) select + entry13_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry13_cmpmask_q when others; +with wr_entry13_sel(0) select + entry13_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry13_parity_q(0 to 3) when others; +with wr_entry13_sel(0) select + entry13_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry13_parity_q(4 to 6) when others; +with wr_entry13_sel(0) select + entry13_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry13_parity_q(7) when others; +with wr_entry13_sel(1) select + entry13_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry13_parity_q(8) when others; +with wr_entry13_sel(1) select + entry13_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry13_parity_q(9) when others; +wr_entry14_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="01110")) else '0'; +wr_entry14_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="01110")) else '0'; +with wr_entry14_sel(0) select + entry14_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry14_epn_q(0 to 31) when others; +with wr_entry14_sel(0) select + entry14_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry14_epn_q(32 to 51) when others; +with wr_entry14_sel(0) select + entry14_xbit_d <= wr_cam_data(52) when '1', + entry14_xbit_q when others; +with wr_entry14_sel(0) select + entry14_size_d <= wr_cam_data(53 to 55) when '1', + entry14_size_q(0 to 2) when others; +with wr_entry14_sel(0) select + entry14_class_d <= wr_cam_data(61 to 62) when '1', + entry14_class_q(0 to 1) when others; +with wr_entry14_sel(1) select + entry14_extclass_d <= wr_cam_data(63 to 64) when '1', + entry14_extclass_q(0 to 1) when others; +with wr_entry14_sel(1) select + entry14_hv_d <= wr_cam_data(65) when '1', + entry14_hv_q when others; +with wr_entry14_sel(1) select + entry14_ds_d <= wr_cam_data(66) when '1', + entry14_ds_q when others; +with wr_entry14_sel(1) select + entry14_pid_d <= wr_cam_data(67 to 74) when '1', + entry14_pid_q(0 to 7) when others; +with wr_entry14_sel(0) select + entry14_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry14_cmpmask_q when others; +with wr_entry14_sel(0) select + entry14_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry14_parity_q(0 to 3) when others; +with wr_entry14_sel(0) select + entry14_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry14_parity_q(4 to 6) when others; +with wr_entry14_sel(0) select + entry14_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry14_parity_q(7) when others; +with wr_entry14_sel(1) select + entry14_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry14_parity_q(8) when others; +with wr_entry14_sel(1) select + entry14_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry14_parity_q(9) when others; +wr_entry15_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="01111")) else '0'; +wr_entry15_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="01111")) else '0'; +with wr_entry15_sel(0) select + entry15_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry15_epn_q(0 to 31) when others; +with wr_entry15_sel(0) select + entry15_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry15_epn_q(32 to 51) when others; +with wr_entry15_sel(0) select + entry15_xbit_d <= wr_cam_data(52) when '1', + entry15_xbit_q when others; +with wr_entry15_sel(0) select + entry15_size_d <= wr_cam_data(53 to 55) when '1', + entry15_size_q(0 to 2) when others; +with wr_entry15_sel(0) select + entry15_class_d <= wr_cam_data(61 to 62) when '1', + entry15_class_q(0 to 1) when others; +with wr_entry15_sel(1) select + entry15_extclass_d <= wr_cam_data(63 to 64) when '1', + entry15_extclass_q(0 to 1) when others; +with wr_entry15_sel(1) select + entry15_hv_d <= wr_cam_data(65) when '1', + entry15_hv_q when others; +with wr_entry15_sel(1) select + entry15_ds_d <= wr_cam_data(66) when '1', + entry15_ds_q when others; +with wr_entry15_sel(1) select + entry15_pid_d <= wr_cam_data(67 to 74) when '1', + entry15_pid_q(0 to 7) when others; +with wr_entry15_sel(0) select + entry15_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry15_cmpmask_q when others; +with wr_entry15_sel(0) select + entry15_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry15_parity_q(0 to 3) when others; +with wr_entry15_sel(0) select + entry15_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry15_parity_q(4 to 6) when others; +with wr_entry15_sel(0) select + entry15_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry15_parity_q(7) when others; +with wr_entry15_sel(1) select + entry15_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry15_parity_q(8) when others; +with wr_entry15_sel(1) select + entry15_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry15_parity_q(9) when others; +wr_entry16_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="10000")) else '0'; +wr_entry16_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="10000")) else '0'; +with wr_entry16_sel(0) select + entry16_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry16_epn_q(0 to 31) when others; +with wr_entry16_sel(0) select + entry16_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry16_epn_q(32 to 51) when others; +with wr_entry16_sel(0) select + entry16_xbit_d <= wr_cam_data(52) when '1', + entry16_xbit_q when others; +with wr_entry16_sel(0) select + entry16_size_d <= wr_cam_data(53 to 55) when '1', + entry16_size_q(0 to 2) when others; +with wr_entry16_sel(0) select + entry16_class_d <= wr_cam_data(61 to 62) when '1', + entry16_class_q(0 to 1) when others; +with wr_entry16_sel(1) select + entry16_extclass_d <= wr_cam_data(63 to 64) when '1', + entry16_extclass_q(0 to 1) when others; +with wr_entry16_sel(1) select + entry16_hv_d <= wr_cam_data(65) when '1', + entry16_hv_q when others; +with wr_entry16_sel(1) select + entry16_ds_d <= wr_cam_data(66) when '1', + entry16_ds_q when others; +with wr_entry16_sel(1) select + entry16_pid_d <= wr_cam_data(67 to 74) when '1', + entry16_pid_q(0 to 7) when others; +with wr_entry16_sel(0) select + entry16_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry16_cmpmask_q when others; +with wr_entry16_sel(0) select + entry16_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry16_parity_q(0 to 3) when others; +with wr_entry16_sel(0) select + entry16_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry16_parity_q(4 to 6) when others; +with wr_entry16_sel(0) select + entry16_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry16_parity_q(7) when others; +with wr_entry16_sel(1) select + entry16_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry16_parity_q(8) when others; +with wr_entry16_sel(1) select + entry16_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry16_parity_q(9) when others; +wr_entry17_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="10001")) else '0'; +wr_entry17_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="10001")) else '0'; +with wr_entry17_sel(0) select + entry17_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry17_epn_q(0 to 31) when others; +with wr_entry17_sel(0) select + entry17_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry17_epn_q(32 to 51) when others; +with wr_entry17_sel(0) select + entry17_xbit_d <= wr_cam_data(52) when '1', + entry17_xbit_q when others; +with wr_entry17_sel(0) select + entry17_size_d <= wr_cam_data(53 to 55) when '1', + entry17_size_q(0 to 2) when others; +with wr_entry17_sel(0) select + entry17_class_d <= wr_cam_data(61 to 62) when '1', + entry17_class_q(0 to 1) when others; +with wr_entry17_sel(1) select + entry17_extclass_d <= wr_cam_data(63 to 64) when '1', + entry17_extclass_q(0 to 1) when others; +with wr_entry17_sel(1) select + entry17_hv_d <= wr_cam_data(65) when '1', + entry17_hv_q when others; +with wr_entry17_sel(1) select + entry17_ds_d <= wr_cam_data(66) when '1', + entry17_ds_q when others; +with wr_entry17_sel(1) select + entry17_pid_d <= wr_cam_data(67 to 74) when '1', + entry17_pid_q(0 to 7) when others; +with wr_entry17_sel(0) select + entry17_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry17_cmpmask_q when others; +with wr_entry17_sel(0) select + entry17_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry17_parity_q(0 to 3) when others; +with wr_entry17_sel(0) select + entry17_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry17_parity_q(4 to 6) when others; +with wr_entry17_sel(0) select + entry17_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry17_parity_q(7) when others; +with wr_entry17_sel(1) select + entry17_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry17_parity_q(8) when others; +with wr_entry17_sel(1) select + entry17_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry17_parity_q(9) when others; +wr_entry18_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="10010")) else '0'; +wr_entry18_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="10010")) else '0'; +with wr_entry18_sel(0) select + entry18_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry18_epn_q(0 to 31) when others; +with wr_entry18_sel(0) select + entry18_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry18_epn_q(32 to 51) when others; +with wr_entry18_sel(0) select + entry18_xbit_d <= wr_cam_data(52) when '1', + entry18_xbit_q when others; +with wr_entry18_sel(0) select + entry18_size_d <= wr_cam_data(53 to 55) when '1', + entry18_size_q(0 to 2) when others; +with wr_entry18_sel(0) select + entry18_class_d <= wr_cam_data(61 to 62) when '1', + entry18_class_q(0 to 1) when others; +with wr_entry18_sel(1) select + entry18_extclass_d <= wr_cam_data(63 to 64) when '1', + entry18_extclass_q(0 to 1) when others; +with wr_entry18_sel(1) select + entry18_hv_d <= wr_cam_data(65) when '1', + entry18_hv_q when others; +with wr_entry18_sel(1) select + entry18_ds_d <= wr_cam_data(66) when '1', + entry18_ds_q when others; +with wr_entry18_sel(1) select + entry18_pid_d <= wr_cam_data(67 to 74) when '1', + entry18_pid_q(0 to 7) when others; +with wr_entry18_sel(0) select + entry18_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry18_cmpmask_q when others; +with wr_entry18_sel(0) select + entry18_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry18_parity_q(0 to 3) when others; +with wr_entry18_sel(0) select + entry18_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry18_parity_q(4 to 6) when others; +with wr_entry18_sel(0) select + entry18_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry18_parity_q(7) when others; +with wr_entry18_sel(1) select + entry18_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry18_parity_q(8) when others; +with wr_entry18_sel(1) select + entry18_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry18_parity_q(9) when others; +wr_entry19_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="10011")) else '0'; +wr_entry19_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="10011")) else '0'; +with wr_entry19_sel(0) select + entry19_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry19_epn_q(0 to 31) when others; +with wr_entry19_sel(0) select + entry19_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry19_epn_q(32 to 51) when others; +with wr_entry19_sel(0) select + entry19_xbit_d <= wr_cam_data(52) when '1', + entry19_xbit_q when others; +with wr_entry19_sel(0) select + entry19_size_d <= wr_cam_data(53 to 55) when '1', + entry19_size_q(0 to 2) when others; +with wr_entry19_sel(0) select + entry19_class_d <= wr_cam_data(61 to 62) when '1', + entry19_class_q(0 to 1) when others; +with wr_entry19_sel(1) select + entry19_extclass_d <= wr_cam_data(63 to 64) when '1', + entry19_extclass_q(0 to 1) when others; +with wr_entry19_sel(1) select + entry19_hv_d <= wr_cam_data(65) when '1', + entry19_hv_q when others; +with wr_entry19_sel(1) select + entry19_ds_d <= wr_cam_data(66) when '1', + entry19_ds_q when others; +with wr_entry19_sel(1) select + entry19_pid_d <= wr_cam_data(67 to 74) when '1', + entry19_pid_q(0 to 7) when others; +with wr_entry19_sel(0) select + entry19_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry19_cmpmask_q when others; +with wr_entry19_sel(0) select + entry19_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry19_parity_q(0 to 3) when others; +with wr_entry19_sel(0) select + entry19_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry19_parity_q(4 to 6) when others; +with wr_entry19_sel(0) select + entry19_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry19_parity_q(7) when others; +with wr_entry19_sel(1) select + entry19_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry19_parity_q(8) when others; +with wr_entry19_sel(1) select + entry19_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry19_parity_q(9) when others; +wr_entry20_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="10100")) else '0'; +wr_entry20_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="10100")) else '0'; +with wr_entry20_sel(0) select + entry20_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry20_epn_q(0 to 31) when others; +with wr_entry20_sel(0) select + entry20_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry20_epn_q(32 to 51) when others; +with wr_entry20_sel(0) select + entry20_xbit_d <= wr_cam_data(52) when '1', + entry20_xbit_q when others; +with wr_entry20_sel(0) select + entry20_size_d <= wr_cam_data(53 to 55) when '1', + entry20_size_q(0 to 2) when others; +with wr_entry20_sel(0) select + entry20_class_d <= wr_cam_data(61 to 62) when '1', + entry20_class_q(0 to 1) when others; +with wr_entry20_sel(1) select + entry20_extclass_d <= wr_cam_data(63 to 64) when '1', + entry20_extclass_q(0 to 1) when others; +with wr_entry20_sel(1) select + entry20_hv_d <= wr_cam_data(65) when '1', + entry20_hv_q when others; +with wr_entry20_sel(1) select + entry20_ds_d <= wr_cam_data(66) when '1', + entry20_ds_q when others; +with wr_entry20_sel(1) select + entry20_pid_d <= wr_cam_data(67 to 74) when '1', + entry20_pid_q(0 to 7) when others; +with wr_entry20_sel(0) select + entry20_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry20_cmpmask_q when others; +with wr_entry20_sel(0) select + entry20_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry20_parity_q(0 to 3) when others; +with wr_entry20_sel(0) select + entry20_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry20_parity_q(4 to 6) when others; +with wr_entry20_sel(0) select + entry20_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry20_parity_q(7) when others; +with wr_entry20_sel(1) select + entry20_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry20_parity_q(8) when others; +with wr_entry20_sel(1) select + entry20_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry20_parity_q(9) when others; +wr_entry21_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="10101")) else '0'; +wr_entry21_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="10101")) else '0'; +with wr_entry21_sel(0) select + entry21_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry21_epn_q(0 to 31) when others; +with wr_entry21_sel(0) select + entry21_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry21_epn_q(32 to 51) when others; +with wr_entry21_sel(0) select + entry21_xbit_d <= wr_cam_data(52) when '1', + entry21_xbit_q when others; +with wr_entry21_sel(0) select + entry21_size_d <= wr_cam_data(53 to 55) when '1', + entry21_size_q(0 to 2) when others; +with wr_entry21_sel(0) select + entry21_class_d <= wr_cam_data(61 to 62) when '1', + entry21_class_q(0 to 1) when others; +with wr_entry21_sel(1) select + entry21_extclass_d <= wr_cam_data(63 to 64) when '1', + entry21_extclass_q(0 to 1) when others; +with wr_entry21_sel(1) select + entry21_hv_d <= wr_cam_data(65) when '1', + entry21_hv_q when others; +with wr_entry21_sel(1) select + entry21_ds_d <= wr_cam_data(66) when '1', + entry21_ds_q when others; +with wr_entry21_sel(1) select + entry21_pid_d <= wr_cam_data(67 to 74) when '1', + entry21_pid_q(0 to 7) when others; +with wr_entry21_sel(0) select + entry21_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry21_cmpmask_q when others; +with wr_entry21_sel(0) select + entry21_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry21_parity_q(0 to 3) when others; +with wr_entry21_sel(0) select + entry21_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry21_parity_q(4 to 6) when others; +with wr_entry21_sel(0) select + entry21_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry21_parity_q(7) when others; +with wr_entry21_sel(1) select + entry21_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry21_parity_q(8) when others; +with wr_entry21_sel(1) select + entry21_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry21_parity_q(9) when others; +wr_entry22_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="10110")) else '0'; +wr_entry22_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="10110")) else '0'; +with wr_entry22_sel(0) select + entry22_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry22_epn_q(0 to 31) when others; +with wr_entry22_sel(0) select + entry22_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry22_epn_q(32 to 51) when others; +with wr_entry22_sel(0) select + entry22_xbit_d <= wr_cam_data(52) when '1', + entry22_xbit_q when others; +with wr_entry22_sel(0) select + entry22_size_d <= wr_cam_data(53 to 55) when '1', + entry22_size_q(0 to 2) when others; +with wr_entry22_sel(0) select + entry22_class_d <= wr_cam_data(61 to 62) when '1', + entry22_class_q(0 to 1) when others; +with wr_entry22_sel(1) select + entry22_extclass_d <= wr_cam_data(63 to 64) when '1', + entry22_extclass_q(0 to 1) when others; +with wr_entry22_sel(1) select + entry22_hv_d <= wr_cam_data(65) when '1', + entry22_hv_q when others; +with wr_entry22_sel(1) select + entry22_ds_d <= wr_cam_data(66) when '1', + entry22_ds_q when others; +with wr_entry22_sel(1) select + entry22_pid_d <= wr_cam_data(67 to 74) when '1', + entry22_pid_q(0 to 7) when others; +with wr_entry22_sel(0) select + entry22_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry22_cmpmask_q when others; +with wr_entry22_sel(0) select + entry22_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry22_parity_q(0 to 3) when others; +with wr_entry22_sel(0) select + entry22_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry22_parity_q(4 to 6) when others; +with wr_entry22_sel(0) select + entry22_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry22_parity_q(7) when others; +with wr_entry22_sel(1) select + entry22_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry22_parity_q(8) when others; +with wr_entry22_sel(1) select + entry22_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry22_parity_q(9) when others; +wr_entry23_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="10111")) else '0'; +wr_entry23_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="10111")) else '0'; +with wr_entry23_sel(0) select + entry23_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry23_epn_q(0 to 31) when others; +with wr_entry23_sel(0) select + entry23_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry23_epn_q(32 to 51) when others; +with wr_entry23_sel(0) select + entry23_xbit_d <= wr_cam_data(52) when '1', + entry23_xbit_q when others; +with wr_entry23_sel(0) select + entry23_size_d <= wr_cam_data(53 to 55) when '1', + entry23_size_q(0 to 2) when others; +with wr_entry23_sel(0) select + entry23_class_d <= wr_cam_data(61 to 62) when '1', + entry23_class_q(0 to 1) when others; +with wr_entry23_sel(1) select + entry23_extclass_d <= wr_cam_data(63 to 64) when '1', + entry23_extclass_q(0 to 1) when others; +with wr_entry23_sel(1) select + entry23_hv_d <= wr_cam_data(65) when '1', + entry23_hv_q when others; +with wr_entry23_sel(1) select + entry23_ds_d <= wr_cam_data(66) when '1', + entry23_ds_q when others; +with wr_entry23_sel(1) select + entry23_pid_d <= wr_cam_data(67 to 74) when '1', + entry23_pid_q(0 to 7) when others; +with wr_entry23_sel(0) select + entry23_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry23_cmpmask_q when others; +with wr_entry23_sel(0) select + entry23_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry23_parity_q(0 to 3) when others; +with wr_entry23_sel(0) select + entry23_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry23_parity_q(4 to 6) when others; +with wr_entry23_sel(0) select + entry23_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry23_parity_q(7) when others; +with wr_entry23_sel(1) select + entry23_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry23_parity_q(8) when others; +with wr_entry23_sel(1) select + entry23_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry23_parity_q(9) when others; +wr_entry24_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="11000")) else '0'; +wr_entry24_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="11000")) else '0'; +with wr_entry24_sel(0) select + entry24_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry24_epn_q(0 to 31) when others; +with wr_entry24_sel(0) select + entry24_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry24_epn_q(32 to 51) when others; +with wr_entry24_sel(0) select + entry24_xbit_d <= wr_cam_data(52) when '1', + entry24_xbit_q when others; +with wr_entry24_sel(0) select + entry24_size_d <= wr_cam_data(53 to 55) when '1', + entry24_size_q(0 to 2) when others; +with wr_entry24_sel(0) select + entry24_class_d <= wr_cam_data(61 to 62) when '1', + entry24_class_q(0 to 1) when others; +with wr_entry24_sel(1) select + entry24_extclass_d <= wr_cam_data(63 to 64) when '1', + entry24_extclass_q(0 to 1) when others; +with wr_entry24_sel(1) select + entry24_hv_d <= wr_cam_data(65) when '1', + entry24_hv_q when others; +with wr_entry24_sel(1) select + entry24_ds_d <= wr_cam_data(66) when '1', + entry24_ds_q when others; +with wr_entry24_sel(1) select + entry24_pid_d <= wr_cam_data(67 to 74) when '1', + entry24_pid_q(0 to 7) when others; +with wr_entry24_sel(0) select + entry24_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry24_cmpmask_q when others; +with wr_entry24_sel(0) select + entry24_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry24_parity_q(0 to 3) when others; +with wr_entry24_sel(0) select + entry24_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry24_parity_q(4 to 6) when others; +with wr_entry24_sel(0) select + entry24_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry24_parity_q(7) when others; +with wr_entry24_sel(1) select + entry24_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry24_parity_q(8) when others; +with wr_entry24_sel(1) select + entry24_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry24_parity_q(9) when others; +wr_entry25_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="11001")) else '0'; +wr_entry25_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="11001")) else '0'; +with wr_entry25_sel(0) select + entry25_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry25_epn_q(0 to 31) when others; +with wr_entry25_sel(0) select + entry25_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry25_epn_q(32 to 51) when others; +with wr_entry25_sel(0) select + entry25_xbit_d <= wr_cam_data(52) when '1', + entry25_xbit_q when others; +with wr_entry25_sel(0) select + entry25_size_d <= wr_cam_data(53 to 55) when '1', + entry25_size_q(0 to 2) when others; +with wr_entry25_sel(0) select + entry25_class_d <= wr_cam_data(61 to 62) when '1', + entry25_class_q(0 to 1) when others; +with wr_entry25_sel(1) select + entry25_extclass_d <= wr_cam_data(63 to 64) when '1', + entry25_extclass_q(0 to 1) when others; +with wr_entry25_sel(1) select + entry25_hv_d <= wr_cam_data(65) when '1', + entry25_hv_q when others; +with wr_entry25_sel(1) select + entry25_ds_d <= wr_cam_data(66) when '1', + entry25_ds_q when others; +with wr_entry25_sel(1) select + entry25_pid_d <= wr_cam_data(67 to 74) when '1', + entry25_pid_q(0 to 7) when others; +with wr_entry25_sel(0) select + entry25_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry25_cmpmask_q when others; +with wr_entry25_sel(0) select + entry25_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry25_parity_q(0 to 3) when others; +with wr_entry25_sel(0) select + entry25_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry25_parity_q(4 to 6) when others; +with wr_entry25_sel(0) select + entry25_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry25_parity_q(7) when others; +with wr_entry25_sel(1) select + entry25_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry25_parity_q(8) when others; +with wr_entry25_sel(1) select + entry25_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry25_parity_q(9) when others; +wr_entry26_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="11010")) else '0'; +wr_entry26_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="11010")) else '0'; +with wr_entry26_sel(0) select + entry26_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry26_epn_q(0 to 31) when others; +with wr_entry26_sel(0) select + entry26_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry26_epn_q(32 to 51) when others; +with wr_entry26_sel(0) select + entry26_xbit_d <= wr_cam_data(52) when '1', + entry26_xbit_q when others; +with wr_entry26_sel(0) select + entry26_size_d <= wr_cam_data(53 to 55) when '1', + entry26_size_q(0 to 2) when others; +with wr_entry26_sel(0) select + entry26_class_d <= wr_cam_data(61 to 62) when '1', + entry26_class_q(0 to 1) when others; +with wr_entry26_sel(1) select + entry26_extclass_d <= wr_cam_data(63 to 64) when '1', + entry26_extclass_q(0 to 1) when others; +with wr_entry26_sel(1) select + entry26_hv_d <= wr_cam_data(65) when '1', + entry26_hv_q when others; +with wr_entry26_sel(1) select + entry26_ds_d <= wr_cam_data(66) when '1', + entry26_ds_q when others; +with wr_entry26_sel(1) select + entry26_pid_d <= wr_cam_data(67 to 74) when '1', + entry26_pid_q(0 to 7) when others; +with wr_entry26_sel(0) select + entry26_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry26_cmpmask_q when others; +with wr_entry26_sel(0) select + entry26_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry26_parity_q(0 to 3) when others; +with wr_entry26_sel(0) select + entry26_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry26_parity_q(4 to 6) when others; +with wr_entry26_sel(0) select + entry26_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry26_parity_q(7) when others; +with wr_entry26_sel(1) select + entry26_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry26_parity_q(8) when others; +with wr_entry26_sel(1) select + entry26_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry26_parity_q(9) when others; +wr_entry27_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="11011")) else '0'; +wr_entry27_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="11011")) else '0'; +with wr_entry27_sel(0) select + entry27_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry27_epn_q(0 to 31) when others; +with wr_entry27_sel(0) select + entry27_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry27_epn_q(32 to 51) when others; +with wr_entry27_sel(0) select + entry27_xbit_d <= wr_cam_data(52) when '1', + entry27_xbit_q when others; +with wr_entry27_sel(0) select + entry27_size_d <= wr_cam_data(53 to 55) when '1', + entry27_size_q(0 to 2) when others; +with wr_entry27_sel(0) select + entry27_class_d <= wr_cam_data(61 to 62) when '1', + entry27_class_q(0 to 1) when others; +with wr_entry27_sel(1) select + entry27_extclass_d <= wr_cam_data(63 to 64) when '1', + entry27_extclass_q(0 to 1) when others; +with wr_entry27_sel(1) select + entry27_hv_d <= wr_cam_data(65) when '1', + entry27_hv_q when others; +with wr_entry27_sel(1) select + entry27_ds_d <= wr_cam_data(66) when '1', + entry27_ds_q when others; +with wr_entry27_sel(1) select + entry27_pid_d <= wr_cam_data(67 to 74) when '1', + entry27_pid_q(0 to 7) when others; +with wr_entry27_sel(0) select + entry27_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry27_cmpmask_q when others; +with wr_entry27_sel(0) select + entry27_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry27_parity_q(0 to 3) when others; +with wr_entry27_sel(0) select + entry27_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry27_parity_q(4 to 6) when others; +with wr_entry27_sel(0) select + entry27_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry27_parity_q(7) when others; +with wr_entry27_sel(1) select + entry27_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry27_parity_q(8) when others; +with wr_entry27_sel(1) select + entry27_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry27_parity_q(9) when others; +wr_entry28_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="11100")) else '0'; +wr_entry28_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="11100")) else '0'; +with wr_entry28_sel(0) select + entry28_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry28_epn_q(0 to 31) when others; +with wr_entry28_sel(0) select + entry28_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry28_epn_q(32 to 51) when others; +with wr_entry28_sel(0) select + entry28_xbit_d <= wr_cam_data(52) when '1', + entry28_xbit_q when others; +with wr_entry28_sel(0) select + entry28_size_d <= wr_cam_data(53 to 55) when '1', + entry28_size_q(0 to 2) when others; +with wr_entry28_sel(0) select + entry28_class_d <= wr_cam_data(61 to 62) when '1', + entry28_class_q(0 to 1) when others; +with wr_entry28_sel(1) select + entry28_extclass_d <= wr_cam_data(63 to 64) when '1', + entry28_extclass_q(0 to 1) when others; +with wr_entry28_sel(1) select + entry28_hv_d <= wr_cam_data(65) when '1', + entry28_hv_q when others; +with wr_entry28_sel(1) select + entry28_ds_d <= wr_cam_data(66) when '1', + entry28_ds_q when others; +with wr_entry28_sel(1) select + entry28_pid_d <= wr_cam_data(67 to 74) when '1', + entry28_pid_q(0 to 7) when others; +with wr_entry28_sel(0) select + entry28_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry28_cmpmask_q when others; +with wr_entry28_sel(0) select + entry28_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry28_parity_q(0 to 3) when others; +with wr_entry28_sel(0) select + entry28_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry28_parity_q(4 to 6) when others; +with wr_entry28_sel(0) select + entry28_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry28_parity_q(7) when others; +with wr_entry28_sel(1) select + entry28_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry28_parity_q(8) when others; +with wr_entry28_sel(1) select + entry28_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry28_parity_q(9) when others; +wr_entry29_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="11101")) else '0'; +wr_entry29_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="11101")) else '0'; +with wr_entry29_sel(0) select + entry29_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry29_epn_q(0 to 31) when others; +with wr_entry29_sel(0) select + entry29_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry29_epn_q(32 to 51) when others; +with wr_entry29_sel(0) select + entry29_xbit_d <= wr_cam_data(52) when '1', + entry29_xbit_q when others; +with wr_entry29_sel(0) select + entry29_size_d <= wr_cam_data(53 to 55) when '1', + entry29_size_q(0 to 2) when others; +with wr_entry29_sel(0) select + entry29_class_d <= wr_cam_data(61 to 62) when '1', + entry29_class_q(0 to 1) when others; +with wr_entry29_sel(1) select + entry29_extclass_d <= wr_cam_data(63 to 64) when '1', + entry29_extclass_q(0 to 1) when others; +with wr_entry29_sel(1) select + entry29_hv_d <= wr_cam_data(65) when '1', + entry29_hv_q when others; +with wr_entry29_sel(1) select + entry29_ds_d <= wr_cam_data(66) when '1', + entry29_ds_q when others; +with wr_entry29_sel(1) select + entry29_pid_d <= wr_cam_data(67 to 74) when '1', + entry29_pid_q(0 to 7) when others; +with wr_entry29_sel(0) select + entry29_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry29_cmpmask_q when others; +with wr_entry29_sel(0) select + entry29_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry29_parity_q(0 to 3) when others; +with wr_entry29_sel(0) select + entry29_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry29_parity_q(4 to 6) when others; +with wr_entry29_sel(0) select + entry29_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry29_parity_q(7) when others; +with wr_entry29_sel(1) select + entry29_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry29_parity_q(8) when others; +with wr_entry29_sel(1) select + entry29_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry29_parity_q(9) when others; +wr_entry30_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="11110")) else '0'; +wr_entry30_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="11110")) else '0'; +with wr_entry30_sel(0) select + entry30_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry30_epn_q(0 to 31) when others; +with wr_entry30_sel(0) select + entry30_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry30_epn_q(32 to 51) when others; +with wr_entry30_sel(0) select + entry30_xbit_d <= wr_cam_data(52) when '1', + entry30_xbit_q when others; +with wr_entry30_sel(0) select + entry30_size_d <= wr_cam_data(53 to 55) when '1', + entry30_size_q(0 to 2) when others; +with wr_entry30_sel(0) select + entry30_class_d <= wr_cam_data(61 to 62) when '1', + entry30_class_q(0 to 1) when others; +with wr_entry30_sel(1) select + entry30_extclass_d <= wr_cam_data(63 to 64) when '1', + entry30_extclass_q(0 to 1) when others; +with wr_entry30_sel(1) select + entry30_hv_d <= wr_cam_data(65) when '1', + entry30_hv_q when others; +with wr_entry30_sel(1) select + entry30_ds_d <= wr_cam_data(66) when '1', + entry30_ds_q when others; +with wr_entry30_sel(1) select + entry30_pid_d <= wr_cam_data(67 to 74) when '1', + entry30_pid_q(0 to 7) when others; +with wr_entry30_sel(0) select + entry30_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry30_cmpmask_q when others; +with wr_entry30_sel(0) select + entry30_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry30_parity_q(0 to 3) when others; +with wr_entry30_sel(0) select + entry30_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry30_parity_q(4 to 6) when others; +with wr_entry30_sel(0) select + entry30_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry30_parity_q(7) when others; +with wr_entry30_sel(1) select + entry30_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry30_parity_q(8) when others; +with wr_entry30_sel(1) select + entry30_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry30_parity_q(9) when others; +wr_entry31_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="11111")) else '0'; +wr_entry31_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="11111")) else '0'; +with wr_entry31_sel(0) select + entry31_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry31_epn_q(0 to 31) when others; +with wr_entry31_sel(0) select + entry31_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry31_epn_q(32 to 51) when others; +with wr_entry31_sel(0) select + entry31_xbit_d <= wr_cam_data(52) when '1', + entry31_xbit_q when others; +with wr_entry31_sel(0) select + entry31_size_d <= wr_cam_data(53 to 55) when '1', + entry31_size_q(0 to 2) when others; +with wr_entry31_sel(0) select + entry31_class_d <= wr_cam_data(61 to 62) when '1', + entry31_class_q(0 to 1) when others; +with wr_entry31_sel(1) select + entry31_extclass_d <= wr_cam_data(63 to 64) when '1', + entry31_extclass_q(0 to 1) when others; +with wr_entry31_sel(1) select + entry31_hv_d <= wr_cam_data(65) when '1', + entry31_hv_q when others; +with wr_entry31_sel(1) select + entry31_ds_d <= wr_cam_data(66) when '1', + entry31_ds_q when others; +with wr_entry31_sel(1) select + entry31_pid_d <= wr_cam_data(67 to 74) when '1', + entry31_pid_q(0 to 7) when others; +with wr_entry31_sel(0) select + entry31_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry31_cmpmask_q when others; +with wr_entry31_sel(0) select + entry31_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry31_parity_q(0 to 3) when others; +with wr_entry31_sel(0) select + entry31_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry31_parity_q(4 to 6) when others; +with wr_entry31_sel(0) select + entry31_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry31_parity_q(7) when others; +with wr_entry31_sel(1) select + entry31_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry31_parity_q(8) when others; +with wr_entry31_sel(1) select + entry31_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry31_parity_q(9) when others; +entry0_inval <= (comp_invalidate and match_vec(0)) or flash_invalidate; +entry0_v_muxsel(0 to 1) <= (entry0_inval & wr_entry0_sel(0)); +with entry0_v_muxsel(0 to 1) select + entry0_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry0_v_q when others; +with wr_entry0_sel(0) select + entry0_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry0_thdid_q(0 to 3) when others; +entry1_inval <= (comp_invalidate and match_vec(1)) or flash_invalidate; +entry1_v_muxsel(0 to 1) <= (entry1_inval & wr_entry1_sel(0)); +with entry1_v_muxsel(0 to 1) select + entry1_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry1_v_q when others; +with wr_entry1_sel(0) select + entry1_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry1_thdid_q(0 to 3) when others; +entry2_inval <= (comp_invalidate and match_vec(2)) or flash_invalidate; +entry2_v_muxsel(0 to 1) <= (entry2_inval & wr_entry2_sel(0)); +with entry2_v_muxsel(0 to 1) select + entry2_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry2_v_q when others; +with wr_entry2_sel(0) select + entry2_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry2_thdid_q(0 to 3) when others; +entry3_inval <= (comp_invalidate and match_vec(3)) or flash_invalidate; +entry3_v_muxsel(0 to 1) <= (entry3_inval & wr_entry3_sel(0)); +with entry3_v_muxsel(0 to 1) select + entry3_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry3_v_q when others; +with wr_entry3_sel(0) select + entry3_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry3_thdid_q(0 to 3) when others; +entry4_inval <= (comp_invalidate and match_vec(4)) or flash_invalidate; +entry4_v_muxsel(0 to 1) <= (entry4_inval & wr_entry4_sel(0)); +with entry4_v_muxsel(0 to 1) select + entry4_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry4_v_q when others; +with wr_entry4_sel(0) select + entry4_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry4_thdid_q(0 to 3) when others; +entry5_inval <= (comp_invalidate and match_vec(5)) or flash_invalidate; +entry5_v_muxsel(0 to 1) <= (entry5_inval & wr_entry5_sel(0)); +with entry5_v_muxsel(0 to 1) select + entry5_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry5_v_q when others; +with wr_entry5_sel(0) select + entry5_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry5_thdid_q(0 to 3) when others; +entry6_inval <= (comp_invalidate and match_vec(6)) or flash_invalidate; +entry6_v_muxsel(0 to 1) <= (entry6_inval & wr_entry6_sel(0)); +with entry6_v_muxsel(0 to 1) select + entry6_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry6_v_q when others; +with wr_entry6_sel(0) select + entry6_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry6_thdid_q(0 to 3) when others; +entry7_inval <= (comp_invalidate and match_vec(7)) or flash_invalidate; +entry7_v_muxsel(0 to 1) <= (entry7_inval & wr_entry7_sel(0)); +with entry7_v_muxsel(0 to 1) select + entry7_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry7_v_q when others; +with wr_entry7_sel(0) select + entry7_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry7_thdid_q(0 to 3) when others; +entry8_inval <= (comp_invalidate and match_vec(8)) or flash_invalidate; +entry8_v_muxsel(0 to 1) <= (entry8_inval & wr_entry8_sel(0)); +with entry8_v_muxsel(0 to 1) select + entry8_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry8_v_q when others; +with wr_entry8_sel(0) select + entry8_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry8_thdid_q(0 to 3) when others; +entry9_inval <= (comp_invalidate and match_vec(9)) or flash_invalidate; +entry9_v_muxsel(0 to 1) <= (entry9_inval & wr_entry9_sel(0)); +with entry9_v_muxsel(0 to 1) select + entry9_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry9_v_q when others; +with wr_entry9_sel(0) select + entry9_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry9_thdid_q(0 to 3) when others; +entry10_inval <= (comp_invalidate and match_vec(10)) or flash_invalidate; +entry10_v_muxsel(0 to 1) <= (entry10_inval & wr_entry10_sel(0)); +with entry10_v_muxsel(0 to 1) select + entry10_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry10_v_q when others; +with wr_entry10_sel(0) select + entry10_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry10_thdid_q(0 to 3) when others; +entry11_inval <= (comp_invalidate and match_vec(11)) or flash_invalidate; +entry11_v_muxsel(0 to 1) <= (entry11_inval & wr_entry11_sel(0)); +with entry11_v_muxsel(0 to 1) select + entry11_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry11_v_q when others; +with wr_entry11_sel(0) select + entry11_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry11_thdid_q(0 to 3) when others; +entry12_inval <= (comp_invalidate and match_vec(12)) or flash_invalidate; +entry12_v_muxsel(0 to 1) <= (entry12_inval & wr_entry12_sel(0)); +with entry12_v_muxsel(0 to 1) select + entry12_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry12_v_q when others; +with wr_entry12_sel(0) select + entry12_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry12_thdid_q(0 to 3) when others; +entry13_inval <= (comp_invalidate and match_vec(13)) or flash_invalidate; +entry13_v_muxsel(0 to 1) <= (entry13_inval & wr_entry13_sel(0)); +with entry13_v_muxsel(0 to 1) select + entry13_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry13_v_q when others; +with wr_entry13_sel(0) select + entry13_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry13_thdid_q(0 to 3) when others; +entry14_inval <= (comp_invalidate and match_vec(14)) or flash_invalidate; +entry14_v_muxsel(0 to 1) <= (entry14_inval & wr_entry14_sel(0)); +with entry14_v_muxsel(0 to 1) select + entry14_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry14_v_q when others; +with wr_entry14_sel(0) select + entry14_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry14_thdid_q(0 to 3) when others; +entry15_inval <= (comp_invalidate and match_vec(15)) or flash_invalidate; +entry15_v_muxsel(0 to 1) <= (entry15_inval & wr_entry15_sel(0)); +with entry15_v_muxsel(0 to 1) select + entry15_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry15_v_q when others; +with wr_entry15_sel(0) select + entry15_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry15_thdid_q(0 to 3) when others; +entry16_inval <= (comp_invalidate and match_vec(16)) or flash_invalidate; +entry16_v_muxsel(0 to 1) <= (entry16_inval & wr_entry16_sel(0)); +with entry16_v_muxsel(0 to 1) select + entry16_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry16_v_q when others; +with wr_entry16_sel(0) select + entry16_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry16_thdid_q(0 to 3) when others; +entry17_inval <= (comp_invalidate and match_vec(17)) or flash_invalidate; +entry17_v_muxsel(0 to 1) <= (entry17_inval & wr_entry17_sel(0)); +with entry17_v_muxsel(0 to 1) select + entry17_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry17_v_q when others; +with wr_entry17_sel(0) select + entry17_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry17_thdid_q(0 to 3) when others; +entry18_inval <= (comp_invalidate and match_vec(18)) or flash_invalidate; +entry18_v_muxsel(0 to 1) <= (entry18_inval & wr_entry18_sel(0)); +with entry18_v_muxsel(0 to 1) select + entry18_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry18_v_q when others; +with wr_entry18_sel(0) select + entry18_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry18_thdid_q(0 to 3) when others; +entry19_inval <= (comp_invalidate and match_vec(19)) or flash_invalidate; +entry19_v_muxsel(0 to 1) <= (entry19_inval & wr_entry19_sel(0)); +with entry19_v_muxsel(0 to 1) select + entry19_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry19_v_q when others; +with wr_entry19_sel(0) select + entry19_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry19_thdid_q(0 to 3) when others; +entry20_inval <= (comp_invalidate and match_vec(20)) or flash_invalidate; +entry20_v_muxsel(0 to 1) <= (entry20_inval & wr_entry20_sel(0)); +with entry20_v_muxsel(0 to 1) select + entry20_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry20_v_q when others; +with wr_entry20_sel(0) select + entry20_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry20_thdid_q(0 to 3) when others; +entry21_inval <= (comp_invalidate and match_vec(21)) or flash_invalidate; +entry21_v_muxsel(0 to 1) <= (entry21_inval & wr_entry21_sel(0)); +with entry21_v_muxsel(0 to 1) select + entry21_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry21_v_q when others; +with wr_entry21_sel(0) select + entry21_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry21_thdid_q(0 to 3) when others; +entry22_inval <= (comp_invalidate and match_vec(22)) or flash_invalidate; +entry22_v_muxsel(0 to 1) <= (entry22_inval & wr_entry22_sel(0)); +with entry22_v_muxsel(0 to 1) select + entry22_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry22_v_q when others; +with wr_entry22_sel(0) select + entry22_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry22_thdid_q(0 to 3) when others; +entry23_inval <= (comp_invalidate and match_vec(23)) or flash_invalidate; +entry23_v_muxsel(0 to 1) <= (entry23_inval & wr_entry23_sel(0)); +with entry23_v_muxsel(0 to 1) select + entry23_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry23_v_q when others; +with wr_entry23_sel(0) select + entry23_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry23_thdid_q(0 to 3) when others; +entry24_inval <= (comp_invalidate and match_vec(24)) or flash_invalidate; +entry24_v_muxsel(0 to 1) <= (entry24_inval & wr_entry24_sel(0)); +with entry24_v_muxsel(0 to 1) select + entry24_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry24_v_q when others; +with wr_entry24_sel(0) select + entry24_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry24_thdid_q(0 to 3) when others; +entry25_inval <= (comp_invalidate and match_vec(25)) or flash_invalidate; +entry25_v_muxsel(0 to 1) <= (entry25_inval & wr_entry25_sel(0)); +with entry25_v_muxsel(0 to 1) select + entry25_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry25_v_q when others; +with wr_entry25_sel(0) select + entry25_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry25_thdid_q(0 to 3) when others; +entry26_inval <= (comp_invalidate and match_vec(26)) or flash_invalidate; +entry26_v_muxsel(0 to 1) <= (entry26_inval & wr_entry26_sel(0)); +with entry26_v_muxsel(0 to 1) select + entry26_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry26_v_q when others; +with wr_entry26_sel(0) select + entry26_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry26_thdid_q(0 to 3) when others; +entry27_inval <= (comp_invalidate and match_vec(27)) or flash_invalidate; +entry27_v_muxsel(0 to 1) <= (entry27_inval & wr_entry27_sel(0)); +with entry27_v_muxsel(0 to 1) select + entry27_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry27_v_q when others; +with wr_entry27_sel(0) select + entry27_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry27_thdid_q(0 to 3) when others; +entry28_inval <= (comp_invalidate and match_vec(28)) or flash_invalidate; +entry28_v_muxsel(0 to 1) <= (entry28_inval & wr_entry28_sel(0)); +with entry28_v_muxsel(0 to 1) select + entry28_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry28_v_q when others; +with wr_entry28_sel(0) select + entry28_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry28_thdid_q(0 to 3) when others; +entry29_inval <= (comp_invalidate and match_vec(29)) or flash_invalidate; +entry29_v_muxsel(0 to 1) <= (entry29_inval & wr_entry29_sel(0)); +with entry29_v_muxsel(0 to 1) select + entry29_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry29_v_q when others; +with wr_entry29_sel(0) select + entry29_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry29_thdid_q(0 to 3) when others; +entry30_inval <= (comp_invalidate and match_vec(30)) or flash_invalidate; +entry30_v_muxsel(0 to 1) <= (entry30_inval & wr_entry30_sel(0)); +with entry30_v_muxsel(0 to 1) select + entry30_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry30_v_q when others; +with wr_entry30_sel(0) select + entry30_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry30_thdid_q(0 to 3) when others; +entry31_inval <= (comp_invalidate and match_vec(31)) or flash_invalidate; +entry31_v_muxsel(0 to 1) <= (entry31_inval & wr_entry31_sel(0)); +with entry31_v_muxsel(0 to 1) select + entry31_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry31_v_q when others; +with wr_entry31_sel(0) select + entry31_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry31_thdid_q(0 to 3) when others; +entry0_cam_vec <= entry0_epn_q & entry0_xbit_q & entry0_size_q & entry0_v_q & entry0_thdid_q & + entry0_class_q & entry0_extclass_q & entry0_hv_q & entry0_ds_q & entry0_pid_q & entry0_cmpmask_q; +entry1_cam_vec <= entry1_epn_q & entry1_xbit_q & entry1_size_q & entry1_v_q & entry1_thdid_q & + entry1_class_q & entry1_extclass_q & entry1_hv_q & entry1_ds_q & entry1_pid_q & entry1_cmpmask_q; +entry2_cam_vec <= entry2_epn_q & entry2_xbit_q & entry2_size_q & entry2_v_q & entry2_thdid_q & + entry2_class_q & entry2_extclass_q & entry2_hv_q & entry2_ds_q & entry2_pid_q & entry2_cmpmask_q; +entry3_cam_vec <= entry3_epn_q & entry3_xbit_q & entry3_size_q & entry3_v_q & entry3_thdid_q & + entry3_class_q & entry3_extclass_q & entry3_hv_q & entry3_ds_q & entry3_pid_q & entry3_cmpmask_q; +entry4_cam_vec <= entry4_epn_q & entry4_xbit_q & entry4_size_q & entry4_v_q & entry4_thdid_q & + entry4_class_q & entry4_extclass_q & entry4_hv_q & entry4_ds_q & entry4_pid_q & entry4_cmpmask_q; +entry5_cam_vec <= entry5_epn_q & entry5_xbit_q & entry5_size_q & entry5_v_q & entry5_thdid_q & + entry5_class_q & entry5_extclass_q & entry5_hv_q & entry5_ds_q & entry5_pid_q & entry5_cmpmask_q; +entry6_cam_vec <= entry6_epn_q & entry6_xbit_q & entry6_size_q & entry6_v_q & entry6_thdid_q & + entry6_class_q & entry6_extclass_q & entry6_hv_q & entry6_ds_q & entry6_pid_q & entry6_cmpmask_q; +entry7_cam_vec <= entry7_epn_q & entry7_xbit_q & entry7_size_q & entry7_v_q & entry7_thdid_q & + entry7_class_q & entry7_extclass_q & entry7_hv_q & entry7_ds_q & entry7_pid_q & entry7_cmpmask_q; +entry8_cam_vec <= entry8_epn_q & entry8_xbit_q & entry8_size_q & entry8_v_q & entry8_thdid_q & + entry8_class_q & entry8_extclass_q & entry8_hv_q & entry8_ds_q & entry8_pid_q & entry8_cmpmask_q; +entry9_cam_vec <= entry9_epn_q & entry9_xbit_q & entry9_size_q & entry9_v_q & entry9_thdid_q & + entry9_class_q & entry9_extclass_q & entry9_hv_q & entry9_ds_q & entry9_pid_q & entry9_cmpmask_q; +entry10_cam_vec <= entry10_epn_q & entry10_xbit_q & entry10_size_q & entry10_v_q & entry10_thdid_q & + entry10_class_q & entry10_extclass_q & entry10_hv_q & entry10_ds_q & entry10_pid_q & entry10_cmpmask_q; +entry11_cam_vec <= entry11_epn_q & entry11_xbit_q & entry11_size_q & entry11_v_q & entry11_thdid_q & + entry11_class_q & entry11_extclass_q & entry11_hv_q & entry11_ds_q & entry11_pid_q & entry11_cmpmask_q; +entry12_cam_vec <= entry12_epn_q & entry12_xbit_q & entry12_size_q & entry12_v_q & entry12_thdid_q & + entry12_class_q & entry12_extclass_q & entry12_hv_q & entry12_ds_q & entry12_pid_q & entry12_cmpmask_q; +entry13_cam_vec <= entry13_epn_q & entry13_xbit_q & entry13_size_q & entry13_v_q & entry13_thdid_q & + entry13_class_q & entry13_extclass_q & entry13_hv_q & entry13_ds_q & entry13_pid_q & entry13_cmpmask_q; +entry14_cam_vec <= entry14_epn_q & entry14_xbit_q & entry14_size_q & entry14_v_q & entry14_thdid_q & + entry14_class_q & entry14_extclass_q & entry14_hv_q & entry14_ds_q & entry14_pid_q & entry14_cmpmask_q; +entry15_cam_vec <= entry15_epn_q & entry15_xbit_q & entry15_size_q & entry15_v_q & entry15_thdid_q & + entry15_class_q & entry15_extclass_q & entry15_hv_q & entry15_ds_q & entry15_pid_q & entry15_cmpmask_q; +entry16_cam_vec <= entry16_epn_q & entry16_xbit_q & entry16_size_q & entry16_v_q & entry16_thdid_q & + entry16_class_q & entry16_extclass_q & entry16_hv_q & entry16_ds_q & entry16_pid_q & entry16_cmpmask_q; +entry17_cam_vec <= entry17_epn_q & entry17_xbit_q & entry17_size_q & entry17_v_q & entry17_thdid_q & + entry17_class_q & entry17_extclass_q & entry17_hv_q & entry17_ds_q & entry17_pid_q & entry17_cmpmask_q; +entry18_cam_vec <= entry18_epn_q & entry18_xbit_q & entry18_size_q & entry18_v_q & entry18_thdid_q & + entry18_class_q & entry18_extclass_q & entry18_hv_q & entry18_ds_q & entry18_pid_q & entry18_cmpmask_q; +entry19_cam_vec <= entry19_epn_q & entry19_xbit_q & entry19_size_q & entry19_v_q & entry19_thdid_q & + entry19_class_q & entry19_extclass_q & entry19_hv_q & entry19_ds_q & entry19_pid_q & entry19_cmpmask_q; +entry20_cam_vec <= entry20_epn_q & entry20_xbit_q & entry20_size_q & entry20_v_q & entry20_thdid_q & + entry20_class_q & entry20_extclass_q & entry20_hv_q & entry20_ds_q & entry20_pid_q & entry20_cmpmask_q; +entry21_cam_vec <= entry21_epn_q & entry21_xbit_q & entry21_size_q & entry21_v_q & entry21_thdid_q & + entry21_class_q & entry21_extclass_q & entry21_hv_q & entry21_ds_q & entry21_pid_q & entry21_cmpmask_q; +entry22_cam_vec <= entry22_epn_q & entry22_xbit_q & entry22_size_q & entry22_v_q & entry22_thdid_q & + entry22_class_q & entry22_extclass_q & entry22_hv_q & entry22_ds_q & entry22_pid_q & entry22_cmpmask_q; +entry23_cam_vec <= entry23_epn_q & entry23_xbit_q & entry23_size_q & entry23_v_q & entry23_thdid_q & + entry23_class_q & entry23_extclass_q & entry23_hv_q & entry23_ds_q & entry23_pid_q & entry23_cmpmask_q; +entry24_cam_vec <= entry24_epn_q & entry24_xbit_q & entry24_size_q & entry24_v_q & entry24_thdid_q & + entry24_class_q & entry24_extclass_q & entry24_hv_q & entry24_ds_q & entry24_pid_q & entry24_cmpmask_q; +entry25_cam_vec <= entry25_epn_q & entry25_xbit_q & entry25_size_q & entry25_v_q & entry25_thdid_q & + entry25_class_q & entry25_extclass_q & entry25_hv_q & entry25_ds_q & entry25_pid_q & entry25_cmpmask_q; +entry26_cam_vec <= entry26_epn_q & entry26_xbit_q & entry26_size_q & entry26_v_q & entry26_thdid_q & + entry26_class_q & entry26_extclass_q & entry26_hv_q & entry26_ds_q & entry26_pid_q & entry26_cmpmask_q; +entry27_cam_vec <= entry27_epn_q & entry27_xbit_q & entry27_size_q & entry27_v_q & entry27_thdid_q & + entry27_class_q & entry27_extclass_q & entry27_hv_q & entry27_ds_q & entry27_pid_q & entry27_cmpmask_q; +entry28_cam_vec <= entry28_epn_q & entry28_xbit_q & entry28_size_q & entry28_v_q & entry28_thdid_q & + entry28_class_q & entry28_extclass_q & entry28_hv_q & entry28_ds_q & entry28_pid_q & entry28_cmpmask_q; +entry29_cam_vec <= entry29_epn_q & entry29_xbit_q & entry29_size_q & entry29_v_q & entry29_thdid_q & + entry29_class_q & entry29_extclass_q & entry29_hv_q & entry29_ds_q & entry29_pid_q & entry29_cmpmask_q; +entry30_cam_vec <= entry30_epn_q & entry30_xbit_q & entry30_size_q & entry30_v_q & entry30_thdid_q & + entry30_class_q & entry30_extclass_q & entry30_hv_q & entry30_ds_q & entry30_pid_q & entry30_cmpmask_q; +entry31_cam_vec <= entry31_epn_q & entry31_xbit_q & entry31_size_q & entry31_v_q & entry31_thdid_q & + entry31_class_q & entry31_extclass_q & entry31_hv_q & entry31_ds_q & entry31_pid_q & entry31_cmpmask_q; +cam_cmp_data_muxsel <= not(comp_request) & cam_hit_entry_d; +with cam_cmp_data_muxsel select + cam_cmp_data_d <= entry0_cam_vec when "000000", + entry1_cam_vec when "000001", + entry2_cam_vec when "000010", + entry3_cam_vec when "000011", + entry4_cam_vec when "000100", + entry5_cam_vec when "000101", + entry6_cam_vec when "000110", + entry7_cam_vec when "000111", + entry8_cam_vec when "001000", + entry9_cam_vec when "001001", + entry10_cam_vec when "001010", + entry11_cam_vec when "001011", + entry12_cam_vec when "001100", + entry13_cam_vec when "001101", + entry14_cam_vec when "001110", + entry15_cam_vec when "001111", + entry16_cam_vec when "010000", + entry17_cam_vec when "010001", + entry18_cam_vec when "010010", + entry19_cam_vec when "010011", + entry20_cam_vec when "010100", + entry21_cam_vec when "010101", + entry22_cam_vec when "010110", + entry23_cam_vec when "010111", + entry24_cam_vec when "011000", + entry25_cam_vec when "011001", + entry26_cam_vec when "011010", + entry27_cam_vec when "011011", + entry28_cam_vec when "011100", + entry29_cam_vec when "011101", + entry30_cam_vec when "011110", + entry31_cam_vec when "011111", + cam_cmp_data_q when others; +cam_cmp_data_np1 <= cam_cmp_data_q; +rd_cam_data_muxsel <= not(rd_val) & rw_entry; +with rd_cam_data_muxsel select + rd_cam_data_d <= entry0_cam_vec when "000000", + entry1_cam_vec when "000001", + entry2_cam_vec when "000010", + entry3_cam_vec when "000011", + entry4_cam_vec when "000100", + entry5_cam_vec when "000101", + entry6_cam_vec when "000110", + entry7_cam_vec when "000111", + entry8_cam_vec when "001000", + entry9_cam_vec when "001001", + entry10_cam_vec when "001010", + entry11_cam_vec when "001011", + entry12_cam_vec when "001100", + entry13_cam_vec when "001101", + entry14_cam_vec when "001110", + entry15_cam_vec when "001111", + entry16_cam_vec when "010000", + entry17_cam_vec when "010001", + entry18_cam_vec when "010010", + entry19_cam_vec when "010011", + entry20_cam_vec when "010100", + entry21_cam_vec when "010101", + entry22_cam_vec when "010110", + entry23_cam_vec when "010111", + entry24_cam_vec when "011000", + entry25_cam_vec when "011001", + entry26_cam_vec when "011010", + entry27_cam_vec when "011011", + entry28_cam_vec when "011100", + entry29_cam_vec when "011101", + entry30_cam_vec when "011110", + entry31_cam_vec when "011111", + rd_cam_data_q when others; +with cam_cmp_data_muxsel select + cam_cmp_parity_d <= entry0_parity_q when "000000", + entry1_parity_q when "000001", + entry2_parity_q when "000010", + entry3_parity_q when "000011", + entry4_parity_q when "000100", + entry5_parity_q when "000101", + entry6_parity_q when "000110", + entry7_parity_q when "000111", + entry8_parity_q when "001000", + entry9_parity_q when "001001", + entry10_parity_q when "001010", + entry11_parity_q when "001011", + entry12_parity_q when "001100", + entry13_parity_q when "001101", + entry14_parity_q when "001110", + entry15_parity_q when "001111", + entry16_parity_q when "010000", + entry17_parity_q when "010001", + entry18_parity_q when "010010", + entry19_parity_q when "010011", + entry20_parity_q when "010100", + entry21_parity_q when "010101", + entry22_parity_q when "010110", + entry23_parity_q when "010111", + entry24_parity_q when "011000", + entry25_parity_q when "011001", + entry26_parity_q when "011010", + entry27_parity_q when "011011", + entry28_parity_q when "011100", + entry29_parity_q when "011101", + entry30_parity_q when "011110", + entry31_parity_q when "011111", + cam_cmp_parity_q when others; +array_cmp_data_np1(0 to 50) <= array_cmp_data_bram(2 to 31) & array_cmp_data_bram(34 to 39) & array_cmp_data_bram(41 to 55); +array_cmp_data_np1(51 to 60) <= cam_cmp_parity_q; +array_cmp_data_np1(61 to 67) <= array_cmp_data_bramp(66 to 72); +array_cmp_data <= array_cmp_data_np1; +with rd_cam_data_muxsel select + rd_array_data_d(51 to 60) <= entry0_parity_q when "000000", + entry1_parity_q when "000001", + entry2_parity_q when "000010", + entry3_parity_q when "000011", + entry4_parity_q when "000100", + entry5_parity_q when "000101", + entry6_parity_q when "000110", + entry7_parity_q when "000111", + entry8_parity_q when "001000", + entry9_parity_q when "001001", + entry10_parity_q when "001010", + entry11_parity_q when "001011", + entry12_parity_q when "001100", + entry13_parity_q when "001101", + entry14_parity_q when "001110", + entry15_parity_q when "001111", + entry16_parity_q when "010000", + entry17_parity_q when "010001", + entry18_parity_q when "010010", + entry19_parity_q when "010011", + entry20_parity_q when "010100", + entry21_parity_q when "010101", + entry22_parity_q when "010110", + entry23_parity_q when "010111", + entry24_parity_q when "011000", + entry25_parity_q when "011001", + entry26_parity_q when "011010", + entry27_parity_q when "011011", + entry28_parity_q when "011100", + entry29_parity_q when "011101", + entry30_parity_q when "011110", + entry31_parity_q when "011111", + rd_array_data_q(51 to 60) when others; +rpn_np2_d(22 to 33) <= ( comp_addr_np1_q(22 to 33) and (22 to 33 => bypass_mux_enab_np1 ) ) or + ( array_cmp_data_np1(0 to 11) and (0 to 11 => not(bypass_mux_enab_np1)) ); +rpn_np2_d(34 to 39) <= ( comp_addr_np1_q(34 to 39) and (34 to 39 => (not(cam_cmp_data_np1(75)) or bypass_mux_enab_np1)) ) or + ( array_cmp_data_np1(12 to 17) and (12 to 17 => (cam_cmp_data_np1(75) and not bypass_mux_enab_np1)) ); +rpn_np2_d(40 to 43) <= ( comp_addr_np1_q(40 to 43) and (40 to 43 => (not(cam_cmp_data_np1(76)) or bypass_mux_enab_np1)) ) or + ( array_cmp_data_np1(18 to 21) and (18 to 21 => (cam_cmp_data_np1(76) and not bypass_mux_enab_np1)) ); +rpn_np2_d(44 to 47) <= ( comp_addr_np1_q(44 to 47) and (44 to 47 => (not(cam_cmp_data_np1(77)) or bypass_mux_enab_np1)) ) or + ( array_cmp_data_np1(22 to 25) and (22 to 25 => (cam_cmp_data_np1(77) and not bypass_mux_enab_np1)) ); +rpn_np2_d(48 to 51) <= ( comp_addr_np1_q(48 to 51) and (48 to 51 => (not(cam_cmp_data_np1(78)) or bypass_mux_enab_np1)) ) or + ( array_cmp_data_np1(26 to 29) and (26 to 29 => (cam_cmp_data_np1(78) and not bypass_mux_enab_np1)) ); +attr_np2_d(0 to 20) <= ( bypass_attr_np1(0 to 20) and (0 to 20 => bypass_mux_enab_np1) ) or + ( array_cmp_data_np1(30 to 50) and (30 to 50 => not bypass_mux_enab_np1) ); +rpn_np2(22 to 51) <= rpn_np2_q(22 to 51); +attr_np2(0 to 20) <= attr_np2_q(0 to 20); +matchline_comb0 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry0_size_q, + entry_cmpmask => entry0_cmpmask_q(0 to 3), + entry_xbit => entry0_xbit_q, + entry_xbitmask => entry0_cmpmask_q(4 to 7), + entry_epn => entry0_epn_q, + comp_class => comp_class, + entry_class => entry0_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry0_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry0_hv_q, + entry_ds => entry0_ds_q, + state_enable => state_enable, + entry_thdid => entry0_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry0_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry0_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(0) + ); +matchline_comb1 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry1_size_q, + entry_cmpmask => entry1_cmpmask_q(0 to 3), + entry_xbit => entry1_xbit_q, + entry_xbitmask => entry1_cmpmask_q(4 to 7), + entry_epn => entry1_epn_q, + comp_class => comp_class, + entry_class => entry1_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry1_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry1_hv_q, + entry_ds => entry1_ds_q, + state_enable => state_enable, + entry_thdid => entry1_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry1_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry1_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(1) + ); +matchline_comb2 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry2_size_q, + entry_cmpmask => entry2_cmpmask_q(0 to 3), + entry_xbit => entry2_xbit_q, + entry_xbitmask => entry2_cmpmask_q(4 to 7), + entry_epn => entry2_epn_q, + comp_class => comp_class, + entry_class => entry2_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry2_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry2_hv_q, + entry_ds => entry2_ds_q, + state_enable => state_enable, + entry_thdid => entry2_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry2_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry2_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(2) + ); +matchline_comb3 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry3_size_q, + entry_cmpmask => entry3_cmpmask_q(0 to 3), + entry_xbit => entry3_xbit_q, + entry_xbitmask => entry3_cmpmask_q(4 to 7), + entry_epn => entry3_epn_q, + comp_class => comp_class, + entry_class => entry3_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry3_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry3_hv_q, + entry_ds => entry3_ds_q, + state_enable => state_enable, + entry_thdid => entry3_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry3_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry3_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(3) + ); +matchline_comb4 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry4_size_q, + entry_cmpmask => entry4_cmpmask_q(0 to 3), + entry_xbit => entry4_xbit_q, + entry_xbitmask => entry4_cmpmask_q(4 to 7), + entry_epn => entry4_epn_q, + comp_class => comp_class, + entry_class => entry4_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry4_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry4_hv_q, + entry_ds => entry4_ds_q, + state_enable => state_enable, + entry_thdid => entry4_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry4_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry4_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(4) + ); +matchline_comb5 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry5_size_q, + entry_cmpmask => entry5_cmpmask_q(0 to 3), + entry_xbit => entry5_xbit_q, + entry_xbitmask => entry5_cmpmask_q(4 to 7), + entry_epn => entry5_epn_q, + comp_class => comp_class, + entry_class => entry5_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry5_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry5_hv_q, + entry_ds => entry5_ds_q, + state_enable => state_enable, + entry_thdid => entry5_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry5_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry5_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(5) + ); +matchline_comb6 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry6_size_q, + entry_cmpmask => entry6_cmpmask_q(0 to 3), + entry_xbit => entry6_xbit_q, + entry_xbitmask => entry6_cmpmask_q(4 to 7), + entry_epn => entry6_epn_q, + comp_class => comp_class, + entry_class => entry6_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry6_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry6_hv_q, + entry_ds => entry6_ds_q, + state_enable => state_enable, + entry_thdid => entry6_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry6_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry6_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(6) + ); +matchline_comb7 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry7_size_q, + entry_cmpmask => entry7_cmpmask_q(0 to 3), + entry_xbit => entry7_xbit_q, + entry_xbitmask => entry7_cmpmask_q(4 to 7), + entry_epn => entry7_epn_q, + comp_class => comp_class, + entry_class => entry7_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry7_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry7_hv_q, + entry_ds => entry7_ds_q, + state_enable => state_enable, + entry_thdid => entry7_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry7_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry7_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(7) + ); +matchline_comb8 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry8_size_q, + entry_cmpmask => entry8_cmpmask_q(0 to 3), + entry_xbit => entry8_xbit_q, + entry_xbitmask => entry8_cmpmask_q(4 to 7), + entry_epn => entry8_epn_q, + comp_class => comp_class, + entry_class => entry8_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry8_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry8_hv_q, + entry_ds => entry8_ds_q, + state_enable => state_enable, + entry_thdid => entry8_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry8_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry8_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(8) + ); +matchline_comb9 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry9_size_q, + entry_cmpmask => entry9_cmpmask_q(0 to 3), + entry_xbit => entry9_xbit_q, + entry_xbitmask => entry9_cmpmask_q(4 to 7), + entry_epn => entry9_epn_q, + comp_class => comp_class, + entry_class => entry9_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry9_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry9_hv_q, + entry_ds => entry9_ds_q, + state_enable => state_enable, + entry_thdid => entry9_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry9_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry9_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(9) + ); +matchline_comb10 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry10_size_q, + entry_cmpmask => entry10_cmpmask_q(0 to 3), + entry_xbit => entry10_xbit_q, + entry_xbitmask => entry10_cmpmask_q(4 to 7), + entry_epn => entry10_epn_q, + comp_class => comp_class, + entry_class => entry10_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry10_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry10_hv_q, + entry_ds => entry10_ds_q, + state_enable => state_enable, + entry_thdid => entry10_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry10_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry10_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(10) + ); +matchline_comb11 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry11_size_q, + entry_cmpmask => entry11_cmpmask_q(0 to 3), + entry_xbit => entry11_xbit_q, + entry_xbitmask => entry11_cmpmask_q(4 to 7), + entry_epn => entry11_epn_q, + comp_class => comp_class, + entry_class => entry11_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry11_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry11_hv_q, + entry_ds => entry11_ds_q, + state_enable => state_enable, + entry_thdid => entry11_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry11_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry11_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(11) + ); +matchline_comb12 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry12_size_q, + entry_cmpmask => entry12_cmpmask_q(0 to 3), + entry_xbit => entry12_xbit_q, + entry_xbitmask => entry12_cmpmask_q(4 to 7), + entry_epn => entry12_epn_q, + comp_class => comp_class, + entry_class => entry12_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry12_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry12_hv_q, + entry_ds => entry12_ds_q, + state_enable => state_enable, + entry_thdid => entry12_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry12_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry12_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(12) + ); +matchline_comb13 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry13_size_q, + entry_cmpmask => entry13_cmpmask_q(0 to 3), + entry_xbit => entry13_xbit_q, + entry_xbitmask => entry13_cmpmask_q(4 to 7), + entry_epn => entry13_epn_q, + comp_class => comp_class, + entry_class => entry13_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry13_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry13_hv_q, + entry_ds => entry13_ds_q, + state_enable => state_enable, + entry_thdid => entry13_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry13_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry13_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(13) + ); +matchline_comb14 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry14_size_q, + entry_cmpmask => entry14_cmpmask_q(0 to 3), + entry_xbit => entry14_xbit_q, + entry_xbitmask => entry14_cmpmask_q(4 to 7), + entry_epn => entry14_epn_q, + comp_class => comp_class, + entry_class => entry14_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry14_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry14_hv_q, + entry_ds => entry14_ds_q, + state_enable => state_enable, + entry_thdid => entry14_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry14_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry14_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(14) + ); +matchline_comb15 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry15_size_q, + entry_cmpmask => entry15_cmpmask_q(0 to 3), + entry_xbit => entry15_xbit_q, + entry_xbitmask => entry15_cmpmask_q(4 to 7), + entry_epn => entry15_epn_q, + comp_class => comp_class, + entry_class => entry15_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry15_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry15_hv_q, + entry_ds => entry15_ds_q, + state_enable => state_enable, + entry_thdid => entry15_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry15_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry15_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(15) + ); +matchline_comb16 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry16_size_q, + entry_cmpmask => entry16_cmpmask_q(0 to 3), + entry_xbit => entry16_xbit_q, + entry_xbitmask => entry16_cmpmask_q(4 to 7), + entry_epn => entry16_epn_q, + comp_class => comp_class, + entry_class => entry16_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry16_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry16_hv_q, + entry_ds => entry16_ds_q, + state_enable => state_enable, + entry_thdid => entry16_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry16_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry16_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(16) + ); +matchline_comb17 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry17_size_q, + entry_cmpmask => entry17_cmpmask_q(0 to 3), + entry_xbit => entry17_xbit_q, + entry_xbitmask => entry17_cmpmask_q(4 to 7), + entry_epn => entry17_epn_q, + comp_class => comp_class, + entry_class => entry17_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry17_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry17_hv_q, + entry_ds => entry17_ds_q, + state_enable => state_enable, + entry_thdid => entry17_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry17_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry17_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(17) + ); +matchline_comb18 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry18_size_q, + entry_cmpmask => entry18_cmpmask_q(0 to 3), + entry_xbit => entry18_xbit_q, + entry_xbitmask => entry18_cmpmask_q(4 to 7), + entry_epn => entry18_epn_q, + comp_class => comp_class, + entry_class => entry18_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry18_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry18_hv_q, + entry_ds => entry18_ds_q, + state_enable => state_enable, + entry_thdid => entry18_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry18_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry18_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(18) + ); +matchline_comb19 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry19_size_q, + entry_cmpmask => entry19_cmpmask_q(0 to 3), + entry_xbit => entry19_xbit_q, + entry_xbitmask => entry19_cmpmask_q(4 to 7), + entry_epn => entry19_epn_q, + comp_class => comp_class, + entry_class => entry19_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry19_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry19_hv_q, + entry_ds => entry19_ds_q, + state_enable => state_enable, + entry_thdid => entry19_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry19_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry19_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(19) + ); +matchline_comb20 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry20_size_q, + entry_cmpmask => entry20_cmpmask_q(0 to 3), + entry_xbit => entry20_xbit_q, + entry_xbitmask => entry20_cmpmask_q(4 to 7), + entry_epn => entry20_epn_q, + comp_class => comp_class, + entry_class => entry20_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry20_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry20_hv_q, + entry_ds => entry20_ds_q, + state_enable => state_enable, + entry_thdid => entry20_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry20_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry20_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(20) + ); +matchline_comb21 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry21_size_q, + entry_cmpmask => entry21_cmpmask_q(0 to 3), + entry_xbit => entry21_xbit_q, + entry_xbitmask => entry21_cmpmask_q(4 to 7), + entry_epn => entry21_epn_q, + comp_class => comp_class, + entry_class => entry21_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry21_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry21_hv_q, + entry_ds => entry21_ds_q, + state_enable => state_enable, + entry_thdid => entry21_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry21_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry21_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(21) + ); +matchline_comb22 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry22_size_q, + entry_cmpmask => entry22_cmpmask_q(0 to 3), + entry_xbit => entry22_xbit_q, + entry_xbitmask => entry22_cmpmask_q(4 to 7), + entry_epn => entry22_epn_q, + comp_class => comp_class, + entry_class => entry22_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry22_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry22_hv_q, + entry_ds => entry22_ds_q, + state_enable => state_enable, + entry_thdid => entry22_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry22_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry22_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(22) + ); +matchline_comb23 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry23_size_q, + entry_cmpmask => entry23_cmpmask_q(0 to 3), + entry_xbit => entry23_xbit_q, + entry_xbitmask => entry23_cmpmask_q(4 to 7), + entry_epn => entry23_epn_q, + comp_class => comp_class, + entry_class => entry23_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry23_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry23_hv_q, + entry_ds => entry23_ds_q, + state_enable => state_enable, + entry_thdid => entry23_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry23_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry23_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(23) + ); +matchline_comb24 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry24_size_q, + entry_cmpmask => entry24_cmpmask_q(0 to 3), + entry_xbit => entry24_xbit_q, + entry_xbitmask => entry24_cmpmask_q(4 to 7), + entry_epn => entry24_epn_q, + comp_class => comp_class, + entry_class => entry24_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry24_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry24_hv_q, + entry_ds => entry24_ds_q, + state_enable => state_enable, + entry_thdid => entry24_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry24_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry24_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(24) + ); +matchline_comb25 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry25_size_q, + entry_cmpmask => entry25_cmpmask_q(0 to 3), + entry_xbit => entry25_xbit_q, + entry_xbitmask => entry25_cmpmask_q(4 to 7), + entry_epn => entry25_epn_q, + comp_class => comp_class, + entry_class => entry25_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry25_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry25_hv_q, + entry_ds => entry25_ds_q, + state_enable => state_enable, + entry_thdid => entry25_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry25_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry25_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(25) + ); +matchline_comb26 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry26_size_q, + entry_cmpmask => entry26_cmpmask_q(0 to 3), + entry_xbit => entry26_xbit_q, + entry_xbitmask => entry26_cmpmask_q(4 to 7), + entry_epn => entry26_epn_q, + comp_class => comp_class, + entry_class => entry26_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry26_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry26_hv_q, + entry_ds => entry26_ds_q, + state_enable => state_enable, + entry_thdid => entry26_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry26_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry26_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(26) + ); +matchline_comb27 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry27_size_q, + entry_cmpmask => entry27_cmpmask_q(0 to 3), + entry_xbit => entry27_xbit_q, + entry_xbitmask => entry27_cmpmask_q(4 to 7), + entry_epn => entry27_epn_q, + comp_class => comp_class, + entry_class => entry27_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry27_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry27_hv_q, + entry_ds => entry27_ds_q, + state_enable => state_enable, + entry_thdid => entry27_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry27_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry27_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(27) + ); +matchline_comb28 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry28_size_q, + entry_cmpmask => entry28_cmpmask_q(0 to 3), + entry_xbit => entry28_xbit_q, + entry_xbitmask => entry28_cmpmask_q(4 to 7), + entry_epn => entry28_epn_q, + comp_class => comp_class, + entry_class => entry28_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry28_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry28_hv_q, + entry_ds => entry28_ds_q, + state_enable => state_enable, + entry_thdid => entry28_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry28_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry28_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(28) + ); +matchline_comb29 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry29_size_q, + entry_cmpmask => entry29_cmpmask_q(0 to 3), + entry_xbit => entry29_xbit_q, + entry_xbitmask => entry29_cmpmask_q(4 to 7), + entry_epn => entry29_epn_q, + comp_class => comp_class, + entry_class => entry29_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry29_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry29_hv_q, + entry_ds => entry29_ds_q, + state_enable => state_enable, + entry_thdid => entry29_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry29_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry29_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(29) + ); +matchline_comb30 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry30_size_q, + entry_cmpmask => entry30_cmpmask_q(0 to 3), + entry_xbit => entry30_xbit_q, + entry_xbitmask => entry30_cmpmask_q(4 to 7), + entry_epn => entry30_epn_q, + comp_class => comp_class, + entry_class => entry30_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry30_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry30_hv_q, + entry_ds => entry30_ds_q, + state_enable => state_enable, + entry_thdid => entry30_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry30_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry30_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(30) + ); +matchline_comb31 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry31_size_q, + entry_cmpmask => entry31_cmpmask_q(0 to 3), + entry_xbit => entry31_xbit_q, + entry_xbitmask => entry31_cmpmask_q(4 to 7), + entry_epn => entry31_epn_q, + comp_class => comp_class, + entry_class => entry31_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry31_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry31_hv_q, + entry_ds => entry31_ds_q, + state_enable => state_enable, + entry_thdid => entry31_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry31_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry31_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(31) + ); +bram0_wea <= wr_array_val(0) and gate_fq; +bram1_wea <= wr_array_val(1) and gate_fq; +bram2_wea <= wr_array_val(1) and gate_fq; +bram0_addra(9-num_entry_log2 to 8) <= rw_entry(0 to num_entry_log2-1); +bram1_addra(11-num_entry_log2 to 10) <= rw_entry(0 to num_entry_log2-1); +bram2_addra(10-num_entry_log2 to 9) <= rw_entry(0 to num_entry_log2-1); +bram0_addrb(9-num_entry_log2 to 8) <= cam_hit_entry_q; +bram1_addrb(11-num_entry_log2 to 10) <= cam_hit_entry_q; +bram2_addrb(10-num_entry_log2 to 9) <= cam_hit_entry_q; +bram0_addra(0 to 8-num_entry_log2) <= (others => '0'); +bram0_addrb(0 to 8-num_entry_log2) <= (others => '0'); +bram1_addra(0 to 10-num_entry_log2) <= (others => '0'); +bram1_addrb(0 to 10-num_entry_log2) <= (others => '0'); +bram2_addra(0 to 9-num_entry_log2) <= (others => '0'); +bram2_addrb(0 to 9-num_entry_log2) <= (others => '0'); +bram0 : ramb16_s36_s36 + +-- pragma translate_off +generic map( + +sim_collision_check => "none") + +-- pragma translate_on +port map( + clka => clk2x, + clkb => clk2x, + ssra => sreset_q, + ssrb => sreset_q, + addra => std_logic_vector(bram0_addra), + addrb => std_logic_vector(bram0_addrb), + dia => std_logic_vector(wr_array_data_bram(0 to 31)), + dib => (others => '0'), + doa => rd_array_data_d_std(0 to 31), + dob => array_cmp_data_bram_std(0 to 31), + dopa => rd_array_data_d_std(66 to 69), + dopb => array_cmp_data_bramp_std(66 to 69), + dipa => std_logic_vector(wr_array_data_bram(66 to 69)), + dipb => (others => '0'), + ena => '1', + enb => '1', + wea => bram0_wea, + web => '0' + ); +bram1 : ramb16_s9_s9 + +-- pragma translate_off +generic map( + +sim_collision_check => "none") + +-- pragma translate_on +port map( + clka => clk2x, + clkb => clk2x, + ssra => sreset_q, + ssrb => sreset_q, + addra => std_logic_vector(bram1_addra), + addrb => std_logic_vector(bram1_addrb), + dia => std_logic_vector(wr_array_data_bram(32 to 39)), + dib => (others => '0'), + doa => rd_array_data_d_std(32 to 39), + dob => array_cmp_data_bram_std(32 to 39), + dopa => rd_array_data_d_std(70 to 70), + dopb => array_cmp_data_bramp_std(70 to 70), + dipa => std_logic_vector(wr_array_data_bram(70 to 70)), + dipb => (others => '0'), + ena => '1', + enb => '1', + wea => bram1_wea, + web => '0' + ); +bram2 : ramb16_s18_s18 + +-- pragma translate_off +generic map( + +sim_collision_check => "none") + +-- pragma translate_on +port map( + clka => clk2x, + clkb => clk2x, + ssra => sreset_q, + ssrb => sreset_q, + addra => std_logic_vector(bram2_addra), + addrb => std_logic_vector(bram2_addrb), + dia => std_logic_vector(wr_array_data_bram(40 to 55)), + dib => (others => '0'), + doa => rd_array_data_d_std(40 to 55), + dob => array_cmp_data_bram_std(40 to 55), + dopa => rd_array_data_d_std(71 to 72), + dopb => array_cmp_data_bramp_std(71 to 72), + dipa => std_logic_vector(wr_array_data_bram(71 to 72)), + dipb => (others => '0'), + ena => '1', + enb => '1', + wea => bram2_wea, + web => '0' + ); +wr_array_data_bram(0 to 72) <= "00" & wr_array_data(0 to 29) & + "00" & wr_array_data(30 to 35) & + '0' & wr_array_data(36 to 50) & + wr_array_data(51 to 60) & wr_array_data(61 to 67); +rd_array_data_d_std(56 to 65) <= (others => '0'); +rd_array_data_d(0 to 29) <= std_ulogic_vector(rd_array_data_d_std(2 to 31)); +rd_array_data_d(30 to 35) <= std_ulogic_vector(rd_array_data_d_std(34 to 39)); +rd_array_data_d(36 to 50) <= std_ulogic_vector(rd_array_data_d_std(41 to 55)); +rd_array_data_d(61 to 67) <= std_ulogic_vector(rd_array_data_d_std(66 to 72)); +array_cmp_data_bram <= std_ulogic_vector(array_cmp_data_bram_std); +array_cmp_data_bramp <= std_ulogic_vector(array_cmp_data_bramp_std); +rd_array_data <= rd_array_data_q; +cam_cmp_data <= cam_cmp_data_q; +rd_cam_data <= rd_cam_data_q; +entry_valid(0) <= entry0_v_q; +entry_valid(1) <= entry1_v_q; +entry_valid(2) <= entry2_v_q; +entry_valid(3) <= entry3_v_q; +entry_valid(4) <= entry4_v_q; +entry_valid(5) <= entry5_v_q; +entry_valid(6) <= entry6_v_q; +entry_valid(7) <= entry7_v_q; +entry_valid(8) <= entry8_v_q; +entry_valid(9) <= entry9_v_q; +entry_valid(10) <= entry10_v_q; +entry_valid(11) <= entry11_v_q; +entry_valid(12) <= entry12_v_q; +entry_valid(13) <= entry13_v_q; +entry_valid(14) <= entry14_v_q; +entry_valid(15) <= entry15_v_q; +entry_valid(16) <= entry16_v_q; +entry_valid(17) <= entry17_v_q; +entry_valid(18) <= entry18_v_q; +entry_valid(19) <= entry19_v_q; +entry_valid(20) <= entry20_v_q; +entry_valid(21) <= entry21_v_q; +entry_valid(22) <= entry22_v_q; +entry_valid(23) <= entry23_v_q; +entry_valid(24) <= entry24_v_q; +entry_valid(25) <= entry25_v_q; +entry_valid(26) <= entry26_v_q; +entry_valid(27) <= entry27_v_q; +entry_valid(28) <= entry28_v_q; +entry_valid(29) <= entry29_v_q; +entry_valid(30) <= entry30_v_q; +entry_valid(31) <= entry31_v_q; +entry_match <= entry_match_q; +cam_hit_entry <= cam_hit_entry_q; +cam_hit <= cam_hit_q; +func_scan_out <= func_scan_in; +regfile_scan_out <= regfile_scan_in; +time_scan_out <= time_scan_in; +end generate; +end tri_cam_32x143_1r1w1c; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_cam_32x143_1r1w1c_matchline.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_cam_32x143_1r1w1c_matchline.vhdl new file mode 100644 index 0000000..8677236 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_cam_32x143_1r1w1c_matchline.vhdl @@ -0,0 +1,398 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; +use ieee.std_logic_1164.all ; +library ibm; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; + + +entity tri_cam_32x143_1r1w1c_matchline is + generic (have_xbit : integer := 1; + num_pgsizes : integer := 5; + have_cmpmask : integer := 1; + cmpmask_width : integer := 4); + +port( + addr_in : in std_ulogic_vector(0 to 51); + addr_enable : in std_ulogic_vector(0 to 1); + comp_pgsize : in std_ulogic_vector(0 to 2); + pgsize_enable : in std_ulogic; + entry_size : in std_ulogic_vector(0 to 2); + entry_cmpmask : in std_ulogic_vector(0 to cmpmask_width-1); + entry_xbit : in std_ulogic; + entry_xbitmask : in std_ulogic_vector(0 to cmpmask_width-1); + entry_epn : in std_ulogic_vector(0 to 51); + comp_class : in std_ulogic_vector(0 to 1); + entry_class : in std_ulogic_vector(0 to 1); + class_enable : in std_ulogic_vector(0 to 2); + comp_extclass : in std_ulogic_vector(0 to 1); + entry_extclass : in std_ulogic_vector(0 to 1); + extclass_enable : in std_ulogic_vector(0 to 1); + comp_state : in std_ulogic_vector(0 to 1); + entry_hv : in std_ulogic; + entry_ds : in std_ulogic; + state_enable : in std_ulogic_vector(0 to 1); + entry_thdid : in std_ulogic_vector(0 to 3); + comp_thdid : in std_ulogic_vector(0 to 3); + thdid_enable : in std_ulogic_vector(0 to 1); + entry_pid : in std_ulogic_vector(0 to 7); + comp_pid : in std_ulogic_vector(0 to 7); + pid_enable : in std_ulogic; + entry_v : in std_ulogic; + comp_invalidate : in std_ulogic; + + match : out std_ulogic +); + + -- synopsys translate_off + -- synopsys translate_on + +end tri_cam_32x143_1r1w1c_matchline; + +architecture tri_cam_32x143_1r1w1c_matchline of tri_cam_32x143_1r1w1c_matchline is + + + + signal entry_epn_b : std_ulogic_vector(34 to 51); + signal function_50_51 : std_ulogic; + signal function_48_51 : std_ulogic; + signal function_46_51 : std_ulogic; + signal function_44_51 : std_ulogic; + signal function_40_51 : std_ulogic; + signal function_36_51 : std_ulogic; + signal function_34_51 : std_ulogic; + signal pgsize_eq_16K : std_ulogic; + signal pgsize_eq_64K : std_ulogic; + signal pgsize_eq_256K : std_ulogic; + signal pgsize_eq_1M : std_ulogic; + signal pgsize_eq_16M : std_ulogic; + signal pgsize_eq_256M : std_ulogic; + signal pgsize_eq_1G : std_ulogic; + signal pgsize_gte_16K : std_ulogic; + signal pgsize_gte_64K : std_ulogic; + signal pgsize_gte_256K : std_ulogic; + signal pgsize_gte_1M : std_ulogic; + signal pgsize_gte_16M : std_ulogic; + signal pgsize_gte_256M : std_ulogic; + signal pgsize_gte_1G : std_ulogic; + signal comp_or_34_35 : std_ulogic; + signal comp_or_34_39 : std_ulogic; + signal comp_or_36_39 : std_ulogic; + signal comp_or_40_43 : std_ulogic; + signal comp_or_44_45 : std_ulogic; + signal comp_or_44_47 : std_ulogic; + signal comp_or_46_47 : std_ulogic; + signal comp_or_48_49 : std_ulogic; + signal comp_or_48_51 : std_ulogic; + signal comp_or_50_51 : std_ulogic; + signal match_line : std_ulogic_vector(0 to 72); + signal pgsize_match : std_ulogic; + signal addr_match : std_ulogic; + signal class_match : std_ulogic; + signal extclass_match : std_ulogic; + signal state_match : std_ulogic; + signal thdid_match : std_ulogic; + signal pid_match : std_ulogic; + +begin + + match_line(0 to 72) <= not((entry_epn(0 to 51) & entry_size(0 to 2) & entry_class(0 to 1) & entry_extclass(0 to 1) & entry_hv & entry_ds & entry_pid(0 to 7) & entry_thdid(0 to 3)) xor + (addr_in(0 to 51) & comp_pgsize(0 to 2) & comp_class(0 to 1) & comp_extclass(0 to 1) & comp_state(0 to 1) & comp_pid(0 to 7) & comp_thdid(0 to 3)) + ); + +numpgsz8 : if num_pgsizes = 8 generate + + entry_epn_b(34 to 51) <= not(entry_epn(34 to 51)); + + +gen_nocmpmask80 : if have_cmpmask = 0 generate + pgsize_eq_1G <= ( entry_size(0) and entry_size(1) and entry_size(2) ); + pgsize_eq_256M <= ( entry_size(0) and entry_size(1) and not(entry_size(2))); + pgsize_eq_16M <= ( entry_size(0) and not(entry_size(1)) and entry_size(2) ); + pgsize_eq_1M <= ( entry_size(0) and not(entry_size(1)) and not(entry_size(2))); + pgsize_eq_256K <= (not(entry_size(0)) and entry_size(1) and entry_size(2) ); + pgsize_eq_64K <= (not(entry_size(0)) and entry_size(1) and not(entry_size(2))); + pgsize_eq_16K <= (not(entry_size(0)) and not(entry_size(1)) and entry_size(2) ); + + pgsize_gte_1G <= ( entry_size(0) and entry_size(1) and entry_size(2) ); + pgsize_gte_256M <= ( entry_size(0) and entry_size(1) and not(entry_size(2))) or + pgsize_gte_1G; + pgsize_gte_16M <= ( entry_size(0) and not(entry_size(1)) and entry_size(2) ) or + pgsize_gte_256M; + pgsize_gte_1M <= ( entry_size(0) and not(entry_size(1)) and not(entry_size(2))) or + pgsize_gte_16M; + pgsize_gte_256K <= (not(entry_size(0)) and entry_size(1) and entry_size(2) ) or + pgsize_gte_1M; + pgsize_gte_64K <= (not(entry_size(0)) and entry_size(1) and not(entry_size(2))) or + pgsize_gte_256K; + pgsize_gte_16K <= (not(entry_size(0)) and not(entry_size(1)) and entry_size(2) ) or + pgsize_gte_64K; + + +end generate gen_nocmpmask80; + +gen_cmpmask80 : if have_cmpmask = 1 generate + pgsize_gte_1G <= not entry_cmpmask(0); + pgsize_gte_256M <= not entry_cmpmask(1); + pgsize_gte_16M <= not entry_cmpmask(2); + pgsize_gte_1M <= not entry_cmpmask(3); + pgsize_gte_256K <= not entry_cmpmask(4); + pgsize_gte_64K <= not entry_cmpmask(5); + pgsize_gte_16K <= not entry_cmpmask(6); + + pgsize_eq_1G <= entry_xbitmask(0); + pgsize_eq_256M <= entry_xbitmask(1); + pgsize_eq_16M <= entry_xbitmask(2); + pgsize_eq_1M <= entry_xbitmask(3); + pgsize_eq_256K <= entry_xbitmask(4); + pgsize_eq_64K <= entry_xbitmask(5); + pgsize_eq_16K <= entry_xbitmask(6); +end generate gen_cmpmask80; + +gen_noxbit80 : if have_xbit = 0 generate + function_34_51 <= '0'; + function_36_51 <= '0'; + function_40_51 <= '0'; + function_44_51 <= '0'; + function_46_51 <= '0'; + function_48_51 <= '0'; + function_50_51 <= '0'; +end generate gen_noxbit80; + +gen_xbit80 : if have_xbit /= 0 generate + function_34_51 <= not(entry_xbit) or + not(pgsize_eq_1G) or + or_reduce(entry_epn_b(34 to 51) and addr_in(34 to 51)); + function_36_51 <= not(entry_xbit) or + not(pgsize_eq_256M) or + or_reduce(entry_epn_b(36 to 51) and addr_in(36 to 51)); + function_40_51 <= not(entry_xbit) or + not(pgsize_eq_16M) or + or_reduce(entry_epn_b(40 to 51) and addr_in(40 to 51)); + function_44_51 <= not(entry_xbit) or + not(pgsize_eq_1M) or + or_reduce(entry_epn_b(44 to 51) and addr_in(44 to 51)); + function_46_51 <= not(entry_xbit) or + not(pgsize_eq_256K) or + or_reduce(entry_epn_b(46 to 51) and addr_in(46 to 51)); + function_48_51 <= not(entry_xbit) or + not(pgsize_eq_64K) or + or_reduce(entry_epn_b(48 to 51) and addr_in(48 to 51)); + function_50_51 <= not(entry_xbit) or + not(pgsize_eq_16K) or + or_reduce(entry_epn_b(50 to 51) and addr_in(50 to 51)); +end generate gen_xbit80; + + + comp_or_50_51 <= and_reduce(match_line(50 to 51)) or pgsize_gte_16K; + comp_or_48_49 <= and_reduce(match_line(48 to 49)) or pgsize_gte_64K; + comp_or_46_47 <= and_reduce(match_line(46 to 47)) or pgsize_gte_256K; + comp_or_44_45 <= and_reduce(match_line(44 to 45)) or pgsize_gte_1M; + comp_or_40_43 <= and_reduce(match_line(40 to 43)) or pgsize_gte_16M; + comp_or_36_39 <= and_reduce(match_line(36 to 39)) or pgsize_gte_256M; + comp_or_34_35 <= and_reduce(match_line(34 to 35)) or pgsize_gte_1G; + +gen_noxbit81 : if have_xbit = 0 generate + addr_match <= (comp_or_34_35 and + comp_or_36_39 and + comp_or_40_43 and + comp_or_44_45 and + comp_or_46_47 and + comp_or_48_49 and + comp_or_50_51 and + and_reduce(match_line(31 to 33)) and + (and_reduce(match_line(0 to 30)) or not(addr_enable(1)))) or + not(addr_enable(0)); +end generate gen_noxbit81; + +gen_xbit81 : if have_xbit /= 0 generate + addr_match <= (function_50_51 and + function_48_51 and + function_46_51 and + function_44_51 and + function_40_51 and + function_36_51 and + function_34_51 and + comp_or_34_35 and + comp_or_36_39 and + comp_or_40_43 and + comp_or_44_45 and + comp_or_46_47 and + comp_or_48_49 and + comp_or_50_51 and + and_reduce(match_line(31 to 33)) and + (and_reduce(match_line(0 to 30)) or not(addr_enable(1)))) or + not(addr_enable(0)); +end generate gen_xbit81; + +end generate numpgsz8; + + +numpgsz5 : if num_pgsizes = 5 generate + + function_50_51 <= '0'; + function_46_51 <= '0'; + function_36_51 <= '0'; + pgsize_eq_16K <= '0'; + pgsize_eq_256K <= '0'; + pgsize_eq_256M <= '0'; + pgsize_gte_16K <= '0'; + pgsize_gte_256K <= '0'; + pgsize_gte_256M <= '0'; + comp_or_34_35 <= '0'; + comp_or_36_39 <= '0'; + comp_or_44_45 <= '0'; + comp_or_46_47 <= '0'; + comp_or_48_49 <= '0'; + comp_or_50_51 <= '0'; + + entry_epn_b(34 to 51) <= not(entry_epn(34 to 51)); + + +gen_nocmpmask50 : if have_cmpmask = 0 generate + pgsize_eq_1G <= ( entry_size(0) and entry_size(1) and not(entry_size(2)) ); + pgsize_eq_16M <= ( entry_size(0) and entry_size(1) and entry_size(2) ); + pgsize_eq_1M <= ( entry_size(0) and not(entry_size(1)) and entry_size(2)); + pgsize_eq_64K <= (not(entry_size(0)) and entry_size(1) and entry_size(2)); + + + pgsize_gte_1G <= ( entry_size(0) and entry_size(1) and not(entry_size(2)) ); + + pgsize_gte_16M <= ( entry_size(0) and entry_size(1) and entry_size(2) ) or + pgsize_gte_1G; + pgsize_gte_1M <= ( entry_size(0) and not(entry_size(1)) and entry_size(2)) or + pgsize_gte_16M; + pgsize_gte_64K <= (not(entry_size(0)) and entry_size(1) and entry_size(2)) or + pgsize_gte_1M; + +end generate gen_nocmpmask50; + +gen_cmpmask50 : if have_cmpmask = 1 generate + pgsize_gte_1G <= not entry_cmpmask(0); + pgsize_gte_16M <= not entry_cmpmask(1); + pgsize_gte_1M <= not entry_cmpmask(2); + pgsize_gte_64K <= not entry_cmpmask(3); + + pgsize_eq_1G <= entry_xbitmask(0); + pgsize_eq_16M <= entry_xbitmask(1); + pgsize_eq_1M <= entry_xbitmask(2); + pgsize_eq_64K <= entry_xbitmask(3); +end generate gen_cmpmask50; + +gen_noxbit50 : if have_xbit = 0 generate + function_34_51 <= '0'; + function_40_51 <= '0'; + function_44_51 <= '0'; + function_48_51 <= '0'; +end generate gen_noxbit50; + +gen_xbit50 : if have_xbit /= 0 generate + function_34_51 <= not(entry_xbit) or + not(pgsize_eq_1G) or + or_reduce(entry_epn_b(34 to 51) and addr_in(34 to 51)); + function_40_51 <= not(entry_xbit) or + not(pgsize_eq_16M) or + or_reduce(entry_epn_b(40 to 51) and addr_in(40 to 51)); + function_44_51 <= not(entry_xbit) or + not(pgsize_eq_1M) or + or_reduce(entry_epn_b(44 to 51) and addr_in(44 to 51)); + function_48_51 <= not(entry_xbit) or + not(pgsize_eq_64K) or + or_reduce(entry_epn_b(48 to 51) and addr_in(48 to 51)); +end generate gen_xbit50; + + comp_or_48_51 <= and_reduce(match_line(48 to 51)) or pgsize_gte_64K; + comp_or_44_47 <= and_reduce(match_line(44 to 47)) or pgsize_gte_1M; + comp_or_40_43 <= and_reduce(match_line(40 to 43)) or pgsize_gte_16M; + comp_or_34_39 <= and_reduce(match_line(34 to 39)) or pgsize_gte_1G; + +gen_noxbit51 : if have_xbit = 0 generate + addr_match <= (comp_or_34_39 and + comp_or_40_43 and + comp_or_44_47 and + comp_or_48_51 and + and_reduce(match_line(31 to 33)) and + (and_reduce(match_line(0 to 30)) or not(addr_enable(1)))) or + not(addr_enable(0)); +end generate gen_noxbit51; + +gen_xbit51 : if have_xbit /= 0 generate + addr_match <= (function_48_51 and + function_44_51 and + function_40_51 and + function_34_51 and + comp_or_34_39 and + comp_or_40_43 and + comp_or_44_47 and + comp_or_48_51 and + and_reduce(match_line(31 to 33)) and + (and_reduce(match_line(0 to 30)) or not(addr_enable(1)))) or + not(addr_enable(0)); +end generate gen_xbit51; + +end generate numpgsz5; + + + pgsize_match <= and_reduce(match_line(52 to 54)) or + not(pgsize_enable); + + class_match <= (match_line(55) or not(class_enable(0))) and + (match_line(56) or not(class_enable(1))) and + (and_reduce(match_line(55 to 56)) or not(class_enable(2)) or + (not(entry_extclass(1)) and not comp_invalidate)); + + extclass_match <= (match_line(57) or not(extclass_enable(0))) and + (match_line(58) or not(extclass_enable(1))); + + state_match <= (match_line(59) or + not(state_enable(0))) and + (match_line(60) or + not(state_enable(1))); + + thdid_match <= (or_reduce(entry_thdid(0 to 3) and comp_thdid(0 to 3)) or not(thdid_enable(0))) and + (and_reduce(match_line(69 to 72)) or not(thdid_enable(1)) or + (not(entry_extclass(1)) and not comp_invalidate)); + + pid_match <= and_reduce(match_line(61 to 68)) or + (not(entry_extclass(1)) and not comp_invalidate) or + not(pid_enable); + + match <= addr_match and + pgsize_match and + class_match and + extclass_match and + state_match and + thdid_match and + pid_match and + entry_v; + + +end tri_cam_32x143_1r1w1c_matchline; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_cam_parerr_mac.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_cam_parerr_mac.vhdl new file mode 100644 index 0000000..303ac15 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_cam_parerr_mac.vhdl @@ -0,0 +1,178 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee; +use ieee.std_logic_1164.all; +library ibm; +use ibm.std_ulogic_unsigned.all; +use ibm.std_ulogic_function_support.all; +library support; +use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity tri_cam_parerr_mac is + generic (expand_type : integer := 1); + port( + + np1_cam_cmp_data :in std_ulogic_vector(0 to 83); + np1_array_cmp_data :in std_ulogic_vector(0 to 67); + + np2_cam_cmp_data :out std_ulogic_vector(0 to 83); + np2_array_cmp_data :out std_ulogic_vector(0 to 67); + np2_cmp_data_parerr_epn :out std_ulogic; + np2_cmp_data_parerr_rpn :out std_ulogic; + + gnd :inout power_logic; + vdd :inout power_logic; + nclk :in clk_logic; + act :in std_ulogic; + lcb_act_dis_dc :in std_ulogic; + lcb_delay_lclkr_dc :in std_ulogic; + lcb_clkoff_dc_b_0 :in std_ulogic; + lcb_mpw1_dc_b :in std_ulogic; + lcb_mpw2_dc_b :in std_ulogic; + lcb_sg_0 :in std_ulogic; + lcb_func_sl_thold_0 :in std_ulogic; + func_scan_in :in std_ulogic; + func_scan_out :out std_ulogic + ); +-- synopsys translate_off +-- synopsys translate_on +end entity tri_cam_parerr_mac; + +architecture tri_cam_parerr_mac of tri_cam_parerr_mac is + +begin + + um: if expand_type = 0 generate + signal np2_cam_cmp_data_q :std_ulogic_vector(0 to np1_cam_cmp_data'length-1); + signal np2_array_cmp_data_q :std_ulogic_vector(0 to np1_array_cmp_data'length-1); + signal np2_cmp_data_calc_par :std_ulogic_vector(50 to 67); + + begin + np1_cam_cmp_data_latch: tri_rlmreg_p + generic map (width => np1_cam_cmp_data'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => act, + scin => (others => '0'), + scout => open, + din => np1_cam_cmp_data, + dout => np2_cam_cmp_data_q); + + np1_array_cmp_data_latch: tri_rlmreg_p + generic map (width => np1_array_cmp_data'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => act, + scin => (others => '0'), + scout => open, + din => np1_array_cmp_data, + dout => np2_array_cmp_data_q); + + np2_cmp_data_calc_par(50) <= xor_reduce(np2_cam_cmp_data_q(75 to 82)); + np2_cmp_data_calc_par(51) <= xor_reduce(np2_cam_cmp_data_q(0 to 7)); + np2_cmp_data_calc_par(52) <= xor_reduce(np2_cam_cmp_data_q(8 to 15)); + np2_cmp_data_calc_par(53) <= xor_reduce(np2_cam_cmp_data_q(16 to 23)); + np2_cmp_data_calc_par(54) <= xor_reduce(np2_cam_cmp_data_q(24 to 31)); + np2_cmp_data_calc_par(55) <= xor_reduce(np2_cam_cmp_data_q(32 to 39)); + np2_cmp_data_calc_par(56) <= xor_reduce(np2_cam_cmp_data_q(40 to 47)); + np2_cmp_data_calc_par(57) <= xor_reduce(np2_cam_cmp_data_q(48 to 55)); + np2_cmp_data_calc_par(58) <= xor_reduce(np2_cam_cmp_data_q(57 to 62)); + np2_cmp_data_calc_par(59) <= xor_reduce(np2_cam_cmp_data_q(63 to 66)); + np2_cmp_data_calc_par(60) <= xor_reduce(np2_cam_cmp_data_q(67 to 74)); + np2_cmp_data_calc_par(61) <= xor_reduce(np2_array_cmp_data_q(0 to 5)); + np2_cmp_data_calc_par(62) <= xor_reduce(np2_array_cmp_data_q(6 to 13)); + np2_cmp_data_calc_par(63) <= xor_reduce(np2_array_cmp_data_q(14 to 21)); + np2_cmp_data_calc_par(64) <= xor_reduce(np2_array_cmp_data_q(22 to 29)); + np2_cmp_data_calc_par(65) <= xor_reduce(np2_array_cmp_data_q(30 to 37)); + np2_cmp_data_calc_par(66) <= xor_reduce(np2_array_cmp_data_q(38 to 44)); + np2_cmp_data_calc_par(67) <= xor_reduce(np2_array_cmp_data_q(45 to 50)); + + np2_cmp_data_parerr_epn <= or_reduce(np2_cmp_data_calc_par(50 to 60) xor (np2_cam_cmp_data_q(83) & np2_array_cmp_data_q(51 to 60))); + np2_cmp_data_parerr_rpn <= or_reduce(np2_cmp_data_calc_par(61 to 67) xor np2_array_cmp_data_q(61 to 67)); + np2_cam_cmp_data <= np2_cam_cmp_data_q; + np2_array_cmp_data <= np2_array_cmp_data_q; + end generate um; + + a: if expand_type = 1 generate + signal np2_cam_cmp_data_q :std_ulogic_vector(0 to np1_cam_cmp_data'length-1); + signal np2_array_cmp_data_q :std_ulogic_vector(0 to np1_array_cmp_data'length-1); + signal np2_cmp_data_calc_par :std_ulogic_vector(50 to 67); + signal clk :std_ulogic; + signal sreset_q :std_ulogic; + begin + clk <= not nclk.clk; + rlatch: process (clk) + begin + if(rising_edge(clk)) then + sreset_q <= nclk.sreset; + end if; + end process; + + slatch: process (nclk,sreset_q) + begin + if(rising_edge(nclk.clk)) then + if (sreset_q = '1') then + np2_cam_cmp_data_q <= (others=>'0'); + np2_array_cmp_data_q <= (others=>'0'); + else + np2_cam_cmp_data_q <= np1_cam_cmp_data; + np2_array_cmp_data_q <= np1_array_cmp_data; + end if; + end if; + end process; + + np2_cmp_data_calc_par(50) <= xor_reduce(np2_cam_cmp_data_q(75 to 82)); + np2_cmp_data_calc_par(51) <= xor_reduce(np2_cam_cmp_data_q(0 to 7)); + np2_cmp_data_calc_par(52) <= xor_reduce(np2_cam_cmp_data_q(8 to 15)); + np2_cmp_data_calc_par(53) <= xor_reduce(np2_cam_cmp_data_q(16 to 23)); + np2_cmp_data_calc_par(54) <= xor_reduce(np2_cam_cmp_data_q(24 to 31)); + np2_cmp_data_calc_par(55) <= xor_reduce(np2_cam_cmp_data_q(32 to 39)); + np2_cmp_data_calc_par(56) <= xor_reduce(np2_cam_cmp_data_q(40 to 47)); + np2_cmp_data_calc_par(57) <= xor_reduce(np2_cam_cmp_data_q(48 to 55)); + np2_cmp_data_calc_par(58) <= xor_reduce(np2_cam_cmp_data_q(57 to 62)); + np2_cmp_data_calc_par(59) <= xor_reduce(np2_cam_cmp_data_q(63 to 66)); + np2_cmp_data_calc_par(60) <= xor_reduce(np2_cam_cmp_data_q(67 to 74)); + np2_cmp_data_calc_par(61) <= xor_reduce(np2_array_cmp_data_q(0 to 5)); + np2_cmp_data_calc_par(62) <= xor_reduce(np2_array_cmp_data_q(6 to 13)); + np2_cmp_data_calc_par(63) <= xor_reduce(np2_array_cmp_data_q(14 to 21)); + np2_cmp_data_calc_par(64) <= xor_reduce(np2_array_cmp_data_q(22 to 29)); + np2_cmp_data_calc_par(65) <= xor_reduce(np2_array_cmp_data_q(30 to 37)); + np2_cmp_data_calc_par(66) <= xor_reduce(np2_array_cmp_data_q(38 to 44)); + np2_cmp_data_calc_par(67) <= xor_reduce(np2_array_cmp_data_q(45 to 50)); + + np2_cmp_data_parerr_epn <= or_reduce(np2_cmp_data_calc_par(50 to 60) xor (np2_cam_cmp_data_q(83) & np2_array_cmp_data_q(51 to 60))); + np2_cmp_data_parerr_rpn <= or_reduce(np2_cmp_data_calc_par(61 to 67) xor np2_array_cmp_data_q(61 to 67)); + np2_cam_cmp_data <= np2_cam_cmp_data_q; + np2_array_cmp_data <= np2_array_cmp_data_q; + + func_scan_out <= func_scan_in; + end generate a; + +end tri_cam_parerr_mac; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_direct_err_rpt.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_direct_err_rpt.vhdl new file mode 100644 index 0000000..0604c73 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_direct_err_rpt.vhdl @@ -0,0 +1,66 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library support; use support.power_logic_pkg.all; +library tri; use tri.tri_latches_pkg.all; +-- pragma translate_off +-- pragma translate_on + +entity tri_direct_err_rpt is + + generic ( + width : positive := 1 ; + expand_type : integer := 1 ); + port ( + vd : inout power_logic; + gd : inout power_logic; + + err_in : in std_ulogic_vector(0 to width-1); + err_out : out std_ulogic_vector(0 to width-1) + ); + -- synopsys translate_off + + -- synopsys translate_on + +end tri_direct_err_rpt; + +architecture tri_direct_err_rpt of tri_direct_err_rpt is + +begin + + a: if expand_type /= 2 generate + begin + err_out <= err_in; + end generate a; + +end tri_direct_err_rpt; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_err_rpt.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_err_rpt.vhdl new file mode 100644 index 0000000..c96ab1e --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_err_rpt.vhdl @@ -0,0 +1,132 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library support; + use support.power_logic_pkg.all; +library tri; use tri.tri_latches_pkg.all; +-- pragma translate_off +-- pragma translate_on + +entity tri_err_rpt is + + generic ( + width : positive := 1; + mask_reset_value : std_ulogic_vector := "0"; + inline : boolean := false; + share_mask : boolean := false; + use_nlats : boolean := false; + needs_sreset : integer := 1 ; + expand_type : integer := 1 ); + + port ( + vd : inout power_logic; + gd : inout power_logic; + err_d1clk : in std_ulogic; + err_d2clk : in std_ulogic; + err_lclk : in clk_logic; + err_scan_in : in std_ulogic_vector(0 to width-1); + err_scan_out : out std_ulogic_vector(0 to width-1); + mode_dclk : in std_ulogic; + mode_lclk : in clk_logic; + mode_scan_in : in std_ulogic_vector(0 to width-1); + mode_scan_out : out std_ulogic_vector(0 to width-1); + + err_in : in std_ulogic_vector(0 to width-1); + err_out : out std_ulogic_vector(0 to width-1); + + hold_out : out std_ulogic_vector(0 to width-1); + mask_out : out std_ulogic_vector(0 to width-1) + ); + -- synopsys translate_off + + -- synopsys translate_on + +end tri_err_rpt; + +architecture tri_err_rpt of tri_err_rpt is + +begin + + a: if expand_type /= 2 generate + constant mask_initv : std_ulogic_vector(0 to (mask_reset_value'length + width-1)):=mask_reset_value & (0 to width-1=>'0'); + signal hold_in : std_ulogic_vector(0 to width-1); + signal hold_lt : std_ulogic_vector(0 to width-1); + signal mask_lt : std_ulogic_vector(0 to width-1); + signal unused : std_ulogic_vector(0 to width); + -- synopsys translate_off + -- synopsys translate_on + begin + hold_in <= err_in or hold_lt; + + hold: entity tri.tri_nlat_scan + generic map( width => width, + needs_sreset => needs_sreset, + expand_type => expand_type ) + port map + ( vd => vd, + gd => gd, + d1clk => err_d1clk, + d2clk => err_d2clk, + lclk => err_lclk, + scan_in => err_scan_in(0 to width-1), + scan_out => err_scan_out(0 to width-1), + din => hold_in, + q => hold_lt, + q_b => open + ); + + m: if (share_mask = false) generate + mask_lt <= mask_initv(0 to width-1); + end generate m; + sm: if (share_mask = true) generate + mask_lt <= (others => mask_initv(0)); + end generate sm; + + mode_scan_out <= (others => '0'); + + hold_out <= hold_lt; + mask_out <= mask_lt; + + inline_hold: if (inline = true) generate + err_out <= hold_lt and not mask_lt; + end generate inline_hold; + + side_hold: if (inline = false) generate + err_out <= err_in and not mask_lt; + end generate side_hold; + + unused(0) <= mode_dclk; + unused(1 to width) <= mode_scan_in; + end generate a; + +end tri_err_rpt; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_inv_nlats.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_inv_nlats.vhdl new file mode 100644 index 0000000..e9b2bfb --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_inv_nlats.vhdl @@ -0,0 +1,119 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library support; + use support.power_logic_pkg.all; +library tri; use tri.tri_latches_pkg.all; + +entity tri_inv_nlats is + + generic ( + offset : natural range 0 to 65535 := 0; + width : positive range 1 to 65536 := 1 ; + init : std_ulogic_vector := "0" ; + synthclonedlatch : string := "" ; + btr : string := "NLI0001_X1_A12TH" ; + needs_sreset : integer := 1 ; + expand_type : integer := 1 ); + port ( + vd : inout power_logic; + gd : inout power_logic; + LCLK : in clk_logic; + D1CLK : in std_ulogic; + D2CLK : in std_ulogic; + SCANIN : in std_ulogic_vector(offset to offset+width-1); + SCANOUT : out std_ulogic_vector(offset to offset+width-1); + D : in std_ulogic_vector(offset to offset+width-1); + QB : out std_ulogic_vector(offset to offset+width-1) + ); + + -- synopsys translate_off + + -- synopsys translate_on + +end entity tri_inv_nlats; + +architecture tri_inv_nlats of tri_inv_nlats is + +begin + + a: if expand_type = 1 generate + constant init_v : std_ulogic_vector(0 to (init'length + width-1)):=init & (0 to width-1=>'0'); + constant zeros : std_ulogic_vector(0 to width-1) := (0 to width-1 => '0'); + + signal sreset : std_ulogic; + signal int_din : std_ulogic_vector(0 to width-1); + signal int_dout : std_ulogic_vector(0 to width-1) := init_v(0 to width-1); + signal vact, vact_b : std_ulogic_vector(0 to width-1); + signal vsreset, vsreset_b : std_ulogic_vector(0 to width-1); + signal vthold, vthold_b : std_ulogic_vector(0 to width-1); + signal din : std_ulogic_vector(0 to width-1); + signal unused : std_ulogic_vector(0 to width-1); + -- synopsys translate_off + -- synopsys translate_on + begin + rst: if needs_sreset = 1 generate + sreset <= LCLK.sreset; + end generate rst; + no_rst: if needs_sreset /=1 generate + sreset <= '0'; + end generate no_rst; + + vsreset <= (0 to width-1 => sreset); + vsreset_b <= (0 to width-1 => not sreset); + din <= D ; + int_din <= (vsreset_b and din) or + (vsreset and init_v(0 to width-1)); + + vact <= (0 to width-1 => D1CLK); + vact_b <= (0 to width-1 => not D1CLK); + + vthold_b <= (0 to width-1 => D2CLK); + vthold <= (0 to width-1 => not D2CLK); + + l: process (LCLK, vact, int_din, vact_b, int_dout, vsreset, vsreset_b, vthold_b, vthold) + begin + if rising_edge(LCLK.clk) then + int_dout <= (((vact and vthold_b) or vsreset) and int_din) or + (((vact_b or vthold) and vsreset_b) and int_dout); + end if; + end process l; + QB <= not int_dout; + SCANOUT <= zeros; + + unused <= SCANIN; + end generate a; + + + +end tri_inv_nlats; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_inv_nlats_wlcb.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_inv_nlats_wlcb.vhdl new file mode 100644 index 0000000..a749486 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_inv_nlats_wlcb.vhdl @@ -0,0 +1,128 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library support; + use support.power_logic_pkg.all; +library tri; use tri.tri_latches_pkg.all; + +entity tri_inv_nlats_wlcb is + + generic ( + width : integer := 4; + offset : integer range 0 to 65535 := 0 ; + init : integer := 0; + ibuf : boolean := false; + dualscan : string := ""; + needs_sreset: integer := 1 ; + expand_type : integer := 1 ; + synthclonedlatch : string := "" ; + btr : string := "NLI0001_X2_A12TH" ); + + port ( + vd : inout power_logic; + gd : inout power_logic; + nclk : in clk_logic; + act : in std_ulogic := '1'; + forcee : in std_ulogic := '0'; + thold_b : in std_ulogic := '1'; + d_mode : in std_ulogic := '0'; + sg : in std_ulogic := '0'; + delay_lclkr : in std_ulogic := '0'; + mpw1_b : in std_ulogic := '1'; + mpw2_b : in std_ulogic := '1'; + scin : in std_ulogic_vector(offset to offset+width-1); + scout : out std_ulogic_vector(offset to offset+width-1); + D : in std_ulogic_vector(offset to offset+width-1); + QB : out std_ulogic_vector(offset to offset+width-1)); + + -- synopsys translate_off + + -- synopsys translate_on + +end entity tri_inv_nlats_wlcb; + +architecture tri_inv_nlats_wlcb of tri_inv_nlats_wlcb is + + constant init_v : std_ulogic_vector(0 to width-1) := std_ulogic_vector( to_unsigned( init, width ) ); + constant zeros : std_ulogic_vector(0 to width-1) := (0 to width-1 => '0'); + +begin + + a: if expand_type = 1 generate + signal sreset : std_ulogic; + signal int_din, din : std_ulogic_vector(0 to width-1); + signal int_dout : std_ulogic_vector(0 to width-1) := init_v; + signal vact, vact_b : std_ulogic_vector(0 to width-1); + signal vsreset, vsreset_b : std_ulogic_vector(0 to width-1); + signal vthold, vthold_b : std_ulogic_vector(0 to width-1); + signal unused : std_ulogic_vector(0 to width); + -- synopsys translate_off + -- synopsys translate_on + begin + rst: if needs_sreset = 1 generate + sreset <= nclk.sreset; + end generate rst; + no_rst: if needs_sreset /=1 generate + sreset <= '0'; + end generate no_rst; + + vsreset <= (0 to width-1 => sreset); + vsreset_b <= (0 to width-1 => not sreset); + + din <= D; + int_din <= (vsreset_b and din) or + (vsreset and init_v); + + vact <= (0 to width-1 => (act or forcee)); + vact_b <= (0 to width-1 => not (act or forcee)); + + vthold_b <= (0 to width-1 => thold_b); + vthold <= (0 to width-1 => not thold_b); + + l: process (nclk, vact, int_din, vact_b, int_dout, vsreset, vsreset_b, vthold_b, vthold) + begin + if rising_edge(nclk.clk) then + int_dout <= (((vact and vthold_b) or vsreset) and int_din) or + (((vact_b or vthold) and vsreset_b) and int_dout); + end if; + end process l; + + QB <= not int_dout; + + scout <= zeros; + + unused(0) <= d_mode or sg or delay_lclkr or mpw1_b or mpw2_b; + unused(1 to width) <= scin; + end generate a; + +end tri_inv_nlats_wlcb; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_latches_pkg.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_latches_pkg.vhdl new file mode 100644 index 0000000..67043de --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_latches_pkg.vhdl @@ -0,0 +1,511 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +LIBRARY ieee; USE ieee.std_logic_1164.all; +LIBRARY support; USE support.power_logic_pkg.all; + +PACKAGE tri_latches_pkg IS + + type clk_logic is record + clk : std_ulogic; + sreset : std_ulogic; + clk2x : std_ulogic; + clk4x : std_ulogic; + end record; + + type clk_logic_vector is array ( NATURAL range <> ) of clk_logic; + + + component tri_cw_nlat + generic ( + bhc:string:=""; + ub:string:=""; + offset : natural range 0 to 65535 := 0; + width : positive range 1 to 65536 := 1 ; + init : std_ulogic_vector := "0"; + needs_sreset : integer := 1 ; + expand_type : integer := 1 ); + port ( + vd : inout power_logic; + gd : inout power_logic; + d_b : in std_ulogic_vector(0 to width-1); + scan_in : in std_ulogic_vector(0 to width-1); + d1clk : in std_ulogic; + d2clk : in std_ulogic; + lclk : in clk_logic; + q_b : out std_ulogic_vector(0 to width-1); + scan_out : out std_ulogic_vector(0 to width-1) + ); + end component; + + component tri_direct_err_rpt + generic ( + width : positive := 1 ; + expand_type : integer := 1 ); + port ( + vd : inout power_logic; + gd : inout power_logic; + + err_in : in std_ulogic_vector(0 to width-1); + err_out : out std_ulogic_vector(0 to width-1) + ); + end component; + + component tri_err_rpt + generic ( + width : positive := 1; + mask_reset_value : std_ulogic_vector := "0"; + inline : boolean := false; + reset_hold : boolean := false; + needs_sreset : integer := 1 ; + expand_type : integer := 1 ); + port ( + vd : inout power_logic; + gd : inout power_logic; + err_d1clk : in std_ulogic; + err_d2clk : in std_ulogic; + err_lclk : in clk_logic; + err_scan_in : in std_ulogic_vector(0 to width-1); + err_scan_out : out std_ulogic_vector(0 to width-1); + mode_dclk : in std_ulogic; + mode_lclk : in clk_logic; + mode_scan_in : in std_ulogic_vector(0 to width-1); + mode_scan_out : out std_ulogic_vector(0 to width-1); + + err_in : in std_ulogic_vector(0 to width-1); + err_out : out std_ulogic_vector(0 to width-1); + + hold_out : out std_ulogic_vector(0 to width-1); + mask_out : out std_ulogic_vector(0 to width-1) + ); + end component; + + component tri_klat + generic ( + width : positive range 1 to 65536 := 1 ; + offset : natural range 0 to 65535 := 0; + init : std_ulogic_vector := "0" ; + synthclonedlatch : string := "" ; + needs_sreset : integer := 1 ; + expand_type : integer := 1 ); + port ( + vd : inout power_logic; + gd : inout power_logic; + dclk : in std_ulogic; + lclk : in clk_logic; + din : in std_ulogic_vector(offset to offset+width-1); + q : out std_ulogic_vector(offset to offset+width-1); + q_b : out std_ulogic_vector(offset to offset+width-1) + ); + end component; + + component tri_lcbcntl_array_mac + generic ( expand_type : integer := 1 ); + port ( + vdd : inout power_logic; + gnd : inout power_logic; + sg : in std_ulogic; + nclk : in clk_logic; + scan_in : in std_ulogic; + scan_diag_dc : in std_ulogic; + thold : in std_ulogic; + clkoff_dc_b : out std_ulogic; + delay_lclkr_dc : out std_ulogic_vector(0 to 4); + act_dis_dc : out std_ulogic; + d_mode_dc : out std_ulogic; + mpw1_dc_b : out std_ulogic_vector(0 to 4); + mpw2_dc_b : out std_ulogic; + scan_out : out std_ulogic + ); + end component; + + component tri_lcbcntl_mac + generic ( expand_type : integer := 1 ); + port ( + vdd : inout power_logic; + gnd : inout power_logic; + sg : in std_ulogic; + nclk : in clk_logic; + scan_in : in std_ulogic; + scan_diag_dc : in std_ulogic; + thold : in std_ulogic; + clkoff_dc_b : out std_ulogic; + delay_lclkr_dc : out std_ulogic_vector(0 to 4); + act_dis_dc : out std_ulogic; + d_mode_dc : out std_ulogic; + mpw1_dc_b : out std_ulogic_vector(0 to 4); + mpw2_dc_b : out std_ulogic; + scan_out : out std_ulogic + ); + end component; + + component tri_lcbkd + generic ( expand_type : integer := 1 ); + port ( + vd : inout power_logic; + gd : inout power_logic; + act : in std_ulogic; + delay_lclkr : in std_ulogic; + mpw1_b : in std_ulogic; + mpw2_b : in std_ulogic; + nclk : in clk_logic; + forcee : in std_ulogic; + thold_b : in std_ulogic; + dclk : out std_ulogic; + lclk : out clk_logic + ); + end component; + + component tri_lcbnd + generic ( expand_type : integer := 1 ); + port ( + vd : inout power_logic; + gd : inout power_logic; + act : in std_ulogic; + delay_lclkr : in std_ulogic; + mpw1_b : in std_ulogic; + mpw2_b : in std_ulogic; + nclk : in clk_logic; + forcee : in std_ulogic; + sg : in std_ulogic; + thold_b : in std_ulogic; + d1clk : out std_ulogic; + d2clk : out std_ulogic; + lclk : out clk_logic + ); + end component; + + component tri_lcbor + generic ( expand_type : integer := 1 ); + port ( + clkoff_b : in std_ulogic; + thold : in std_ulogic; + sg : in std_ulogic; + act_dis : in std_ulogic; + forcee : out std_ulogic; + thold_b : out std_ulogic + ); + end component; + + component tri_lcbs + generic ( expand_type : integer := 1 ); + port ( + vd : inout power_logic; + gd : inout power_logic; + delay_lclkr : in std_ulogic; + nclk : in clk_logic; + forcee : in std_ulogic; + thold_b : in std_ulogic; + dclk : out std_ulogic; + lclk : out clk_logic + ); + end component; + + component tri_nlat + generic ( + offset : natural range 0 to 65535 := 0; + reset_inverts_scan : boolean := true; + width : positive range 1 to 65536 := 1 ; + init : std_ulogic_vector := "0" ; + synthclonedlatch : string := "" ; + needs_sreset : integer := 1 ; + expand_type : integer := 1 ); + port ( + vd : inout power_logic; + gd : inout power_logic; + d1clk : in std_ulogic; + d2clk : in std_ulogic; + lclk : in clk_logic; + scan_in : in std_ulogic; + din : in std_ulogic_vector(offset to offset+width-1); + q : out std_ulogic_vector(offset to offset+width-1); + q_b : out std_ulogic_vector(offset to offset+width-1); + scan_out : out std_ulogic + ); + end component; + + component tri_nlat_scan + generic ( + offset : natural range 0 to 65535 := 0; + width : positive range 1 to 65536 := 1 ; + init : std_ulogic_vector := "0" ; + reset_inverts_scan : boolean := true; + synthclonedlatch : string := "" ; + needs_sreset : integer := 1 ; + expand_type : integer := 1 ); + port ( + vd : inout power_logic; + gd : inout power_logic; + d1clk : in std_ulogic; + d2clk : in std_ulogic; + lclk : in clk_logic; + din : in std_ulogic_vector(offset to offset+width-1); + scan_in : in std_ulogic_vector(offset to offset+width-1); + q : out std_ulogic_vector(offset to offset+width-1); + q_b : out std_ulogic_vector(offset to offset+width-1); + scan_out : out std_ulogic_vector(offset to offset+width-1) + ); + end component; + + component tri_plat + generic ( + width : positive range 1 to 65536 := 1 ; + offset : natural range 0 to 65535 := 0 ; + init : integer := 0; + synthclonedlatch : string := "" ; + flushlat : boolean := true ; + expand_type : integer := 1 ); + port ( + vd : inout power_logic; + gd : inout power_logic; + nclk : in clk_logic; + flush : in std_ulogic; + din : in std_ulogic_vector(offset to offset+width-1); + q : out std_ulogic_vector(offset to offset+width-1) ); + end component; + + component tri_regk + generic ( + width : integer := 4; + offset : integer range 0 to 65535 := 0 ; + init : integer := 0; + synthclonedlatch : string := ""; + needs_sreset : integer := 1 ; + expand_type : integer := 1 ); + port ( + vd : inout power_logic; + gd : inout power_logic; + nclk : in clk_logic; + act : in std_ulogic := '1'; + forcee : in std_ulogic := '0'; + thold_b : in std_ulogic := '1'; + d_mode : in std_ulogic := '0'; + delay_lclkr : in std_ulogic := '0'; + mpw1_b : in std_ulogic := '1'; + mpw2_b : in std_ulogic := '1'; + din : in std_ulogic_vector(offset to offset+width-1); + dout : out std_ulogic_vector(offset to offset+width-1) ); + end component; + + component tri_regs + generic ( + width : integer := 4; + offset : integer range 0 to 65535 := 0 ; + init : integer := 0; + ibuf : boolean := false; + dualscan : string := ""; + needs_sreset : integer := 1 ; + expand_type : integer := 1 ); + port ( + vd : inout power_logic; + gd : inout power_logic; + nclk : in clk_logic; + forcee : in std_ulogic := '0'; + thold_b : in std_ulogic := '1'; + delay_lclkr : in std_ulogic := '0'; + scin : in std_ulogic_vector(offset to offset+width-1); + scout : out std_ulogic_vector(offset to offset+width-1); + dout : out std_ulogic_vector(offset to offset+width-1) ); + end component; + + component tri_rlmlatch_p + generic ( + init : integer := 0; + ibuf : boolean := false; + dualscan : string := ""; + needs_sreset: integer := 1 ; + expand_type : integer := 1 ); + port ( + vd : inout power_logic; + gd : inout power_logic; + nclk : in clk_logic; + act : in std_ulogic := '1'; + forcee : in std_ulogic := '0'; + thold_b : in std_ulogic := '1'; + d_mode : in std_ulogic := '0'; + sg : in std_ulogic := '0'; + delay_lclkr : in std_ulogic := '0'; + mpw1_b : in std_ulogic := '1'; + mpw2_b : in std_ulogic := '1'; + scin : in std_ulogic := '0'; + din : in std_ulogic; + scout : out std_ulogic; + dout : out std_ulogic); + end component; + + component tri_rlmreg_p + generic ( + width : integer := 4; + offset : integer range 0 to 65535 := 0 ; + init : integer := 0; + ibuf : boolean := false; + dualscan : string := ""; + needs_sreset: integer := 1 ; + expand_type : integer := 1 ); + port ( + vd : inout power_logic; + gd : inout power_logic; + nclk : in clk_logic; + act : in std_ulogic := '1'; + forcee : in std_ulogic := '0'; + thold_b : in std_ulogic := '1'; + d_mode : in std_ulogic := '0'; + sg : in std_ulogic := '0'; + delay_lclkr : in std_ulogic := '0'; + mpw1_b : in std_ulogic := '1'; + mpw2_b : in std_ulogic := '1'; + scin : in std_ulogic_vector(offset to offset+width-1); + din : in std_ulogic_vector(offset to offset+width-1); + scout : out std_ulogic_vector(offset to offset+width-1); + dout : out std_ulogic_vector(offset to offset+width-1) ); + end component; + + component tri_slat + generic ( + width : positive range 1 to 65536 := 1; + offset : natural range 0 to 65535 := 0; + init : std_ulogic_vector := "0"; + synthclonedlatch : string := ""; + reset_inverts_scan : boolean := true; + expand_type : integer := 1); + port ( + vd : inout power_logic; + gd : inout power_logic; + dclk : in std_ulogic; + lclk : in clk_logic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + q : out std_ulogic_vector(offset to offset+width-1); + q_b : out std_ulogic_vector(offset to offset+width-1)); + end component; + + component tri_slat_lbist + generic ( + width : positive range 1 to 65536 := 1; + offset : natural range 0 to 65535 := 0; + init : std_ulogic_vector := "0"; + synthclonedlatch : string := ""; + reset_inverts_scan : boolean := true; + expand_type : integer := 1); + port ( + vd : inout power_logic; + gd : inout power_logic; + dclk : in std_ulogic; + lclk : in clk_logic; + tc_xx_lbist_ac_mode_dc : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + q : out std_ulogic_vector(offset to offset+width-1); + q_b : out std_ulogic_vector(offset to offset+width-1)); + end component; + + component tri_slat_scan + generic ( + width : positive range 1 to 65536 := 1 ; + offset : natural range 0 to 65535 := 0; + init : std_ulogic_vector := "0" ; + synthclonedlatch : string := "" ; + btr : string := "c_slat_scan" ; + reset_inverts_scan : boolean := true; + expand_type : integer := 1 ); + port ( + vd : inout power_logic; + gd : inout power_logic; + dclk : in std_ulogic; + lclk : in clk_logic; + scan_in : in std_ulogic_vector(offset to offset+width-1); + scan_out : out std_ulogic_vector(offset to offset+width-1); + q : out std_ulogic_vector(offset to offset+width-1); + q_b : out std_ulogic_vector(offset to offset+width-1) + ); + end component; + + component tri_ser_rlmreg_p + generic ( + width : positive range 1 to 65536 := 1 ; + offset : natural range 0 to 65535 := 0 ; + init : integer := 0; + ibuf : boolean := false; + dualscan : string := ""; + needs_sreset : integer := 1 ; + expand_type : integer := 1 ); + port ( + vd : inout power_logic; + gd : inout power_logic; + nclk : in clk_logic; + act : in std_ulogic := '1'; + forcee : in std_ulogic := '0'; + thold_b : in std_ulogic := '1'; + d_mode : in std_ulogic := '0'; + sg : in std_ulogic := '0'; + delay_lclkr : in std_ulogic := '0'; + mpw1_b : in std_ulogic := '1'; + mpw2_b : in std_ulogic := '1'; + scin : in std_ulogic_vector(offset to offset+width-1); + din : in std_ulogic_vector(offset to offset+width-1); + scout : out std_ulogic_vector(offset to offset+width-1); + dout : out std_ulogic_vector(offset to offset+width-1)); + end component; + + component tri_aoi22_nlats_wlcb + generic ( + width : integer := 4; + offset : integer range 0 to 65535 := 0 ; + init : integer := 0; + ibuf : boolean := false; + dualscan : string := ""; + needs_sreset : integer := 1 ; + expand_type : integer := 1 ; + synthclonedlatch : string := "" ; + btr : string := "NLL0001_X2_A12TH" ); + port ( + vd : inout power_logic; + gd : inout power_logic; + nclk : in clk_logic; + act : in std_ulogic := '1'; + forcee : in std_ulogic := '0'; + thold_b : in std_ulogic := '1'; + d_mode : in std_ulogic := '0'; + sg : in std_ulogic := '0'; + delay_lclkr : in std_ulogic := '0'; + mpw1_b : in std_ulogic := '1'; + mpw2_b : in std_ulogic := '1'; + scin : in std_ulogic_vector(offset to offset+width-1); + scout : out std_ulogic_vector(offset to offset+width-1); + A1 : in std_ulogic_vector(offset to offset+width-1); + A2 : in std_ulogic_vector(offset to offset+width-1); + B1 : in std_ulogic_vector(offset to offset+width-1); + B2 : in std_ulogic_vector(offset to offset+width-1); + QB : out std_ulogic_vector(offset to offset+width-1)); + end component; + +end tri_latches_pkg; + +package body tri_latches_pkg is + +end tri_latches_pkg; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_lcbcntl_array_mac.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_lcbcntl_array_mac.vhdl new file mode 100644 index 0000000..b7ac741 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_lcbcntl_array_mac.vhdl @@ -0,0 +1,86 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library support; + use support.power_logic_pkg.all; +library tri; use tri.tri_latches_pkg.all; +-- pragma translate_off +-- pragma translate_on + +entity tri_lcbcntl_array_mac is + + generic ( expand_type : integer := 1 ); + + port ( + vdd : inout power_logic; + gnd : inout power_logic; + sg : in std_ulogic; + nclk : in clk_logic; + scan_in : in std_ulogic; + scan_diag_dc : in std_ulogic; + thold : in std_ulogic; + clkoff_dc_b : out std_ulogic; + delay_lclkr_dc : out std_ulogic_vector(0 to 4); + act_dis_dc : out std_ulogic; + d_mode_dc : out std_ulogic; + mpw1_dc_b : out std_ulogic_vector(0 to 4); + mpw2_dc_b : out std_ulogic; + scan_out : out std_ulogic + ); + + -- synopsys translate_off + + -- synopsys translate_on + +end entity tri_lcbcntl_array_mac; + +architecture tri_lcbcntl_array_mac of tri_lcbcntl_array_mac is + + signal unused : std_ulogic; + -- synopsys translate_off + -- synopsys translate_on + +begin + + a: if expand_type = 1 generate + clkoff_dc_b <= '1'; + delay_lclkr_dc <= "00000"; + act_dis_dc <= '0'; + d_mode_dc <= '0'; + mpw1_dc_b <= "11111"; + mpw2_dc_b <= '1'; + scan_out <= '0'; + unused <= sg or scan_in or scan_diag_dc or thold; + end generate a; + +end tri_lcbcntl_array_mac; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_lcbcntl_mac.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_lcbcntl_mac.vhdl new file mode 100644 index 0000000..89c609a --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_lcbcntl_mac.vhdl @@ -0,0 +1,86 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library support; + use support.power_logic_pkg.all; +library tri; use tri.tri_latches_pkg.all; +-- pragma translate_off +-- pragma translate_on + +entity tri_lcbcntl_mac is + + generic ( expand_type : integer := 1 ); + + port ( + vdd : inout power_logic; + gnd : inout power_logic; + sg : in std_ulogic; + nclk : in clk_logic; + scan_in : in std_ulogic; + scan_diag_dc : in std_ulogic; + thold : in std_ulogic; + clkoff_dc_b : out std_ulogic; + delay_lclkr_dc : out std_ulogic_vector(0 to 4); + act_dis_dc : out std_ulogic; + d_mode_dc : out std_ulogic; + mpw1_dc_b : out std_ulogic_vector(0 to 4); + mpw2_dc_b : out std_ulogic; + scan_out : out std_ulogic + ); + + -- synopsys translate_off + + -- synopsys translate_on + +end entity tri_lcbcntl_mac; + +architecture tri_lcbcntl_mac of tri_lcbcntl_mac is + + signal unused : std_ulogic; + -- synopsys translate_off + -- synopsys translate_on + +begin + + a: if expand_type = 1 generate + clkoff_dc_b <= '1'; + delay_lclkr_dc <= "00000"; + act_dis_dc <= '0'; + d_mode_dc <= '0'; + mpw1_dc_b <= "11111"; + mpw2_dc_b <= '1'; + scan_out <= '0'; + unused <= sg or scan_in or scan_diag_dc or thold; + end generate a; + +end tri_lcbcntl_mac; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_lcbnd.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_lcbnd.vhdl new file mode 100644 index 0000000..8faa713 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_lcbnd.vhdl @@ -0,0 +1,85 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library support; + use support.power_logic_pkg.all; +library tri; use tri.tri_latches_pkg.all; +-- pragma translate_off +-- pragma translate_on + +entity tri_lcbnd is + + generic ( expand_type : integer := 1 ); + + port ( + vd : inout power_logic; + gd : inout power_logic; + act : in std_ulogic; + delay_lclkr : in std_ulogic; + mpw1_b : in std_ulogic; + mpw2_b : in std_ulogic; + nclk : in clk_logic; + forcee : in std_ulogic; + sg : in std_ulogic; + thold_b : in std_ulogic; + d1clk : out std_ulogic; + d2clk : out std_ulogic; + lclk : out clk_logic + ); + + -- synopsys translate_off + + -- synopsys translate_on + +end entity tri_lcbnd; + +architecture tri_lcbnd of tri_lcbnd is + +begin + + a: if expand_type = 1 generate + signal gate_b : std_ulogic; + signal unused : std_ulogic; + -- synopsys translate_off + -- synopsys translate_on + begin + gate_b <= forcee or act; + + d1clk <= gate_b; + d2clk <= thold_b; + lclk <= nclk; + + unused <= delay_lclkr or mpw1_b or mpw2_b or sg; + end generate a; + +end tri_lcbnd; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_lcbor.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_lcbor.vhdl new file mode 100644 index 0000000..3aff1fc --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_lcbor.vhdl @@ -0,0 +1,71 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library support; + use support.power_logic_pkg.all; +-- pragma translate_off +-- pragma translate_on + +entity tri_lcbor is + + generic ( expand_type : integer := 1 ); + + port ( + clkoff_b : in std_ulogic; + thold : in std_ulogic; + sg : in std_ulogic; + act_dis : in std_ulogic; + forcee : out std_ulogic; + thold_b : out std_ulogic + ); + + -- synopsys translate_off + -- synopsys translate_on + +end entity tri_lcbor; + +architecture tri_lcbor of tri_lcbor is + + signal unused : std_ulogic; + -- synopsys translate_off + -- synopsys translate_on + +begin + + a: if expand_type = 1 generate + forcee <= '0'; + thold_b <= not thold; + unused <= clkoff_b or sg or act_dis; + end generate a; + +end tri_lcbor; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_lcbs.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_lcbs.vhdl new file mode 100644 index 0000000..67e0f93 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_lcbs.vhdl @@ -0,0 +1,75 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library support; + use support.power_logic_pkg.all; +library tri; use tri.tri_latches_pkg.all; +-- pragma translate_off +-- pragma translate_on + +entity tri_lcbs is + + generic ( expand_type : integer := 1 ); + + port ( + vd : inout power_logic; + gd : inout power_logic; + delay_lclkr : in std_ulogic; + nclk : in clk_logic; + forcee : in std_ulogic; + thold_b : in std_ulogic; + dclk : out std_ulogic; + lclk : out clk_logic + ); + + -- synopsys translate_off + + -- synopsys translate_on + +end entity tri_lcbs; + +architecture tri_lcbs of tri_lcbs is + +begin + + a: if expand_type = 1 generate + signal unused : std_ulogic; + -- synopsys translate_off + -- synopsys translate_on + begin + dclk <= thold_b; + lclk <= nclk; + unused <= delay_lclkr or forcee; + end generate a; + +end tri_lcbs; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_nand2_nlats.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_nand2_nlats.vhdl new file mode 100644 index 0000000..c9be68f --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_nand2_nlats.vhdl @@ -0,0 +1,120 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library support; + use support.power_logic_pkg.all; +library tri; use tri.tri_latches_pkg.all; + +entity tri_nand2_nlats is + + generic ( + offset : natural range 0 to 65535 := 0; + width : positive range 1 to 65536 := 1 ; + init : std_ulogic_vector := "0" ; + synthclonedlatch : string := "" ; + btr : string := "NLA0001_X1_A12TH" ; + needs_sreset : integer := 1 ; + expand_type : integer := 1 ); + port ( + vd : inout power_logic; + gd : inout power_logic; + LCLK : in clk_logic; + D1CLK : in std_ulogic; + D2CLK : in std_ulogic; + SCANIN : in std_ulogic_vector(offset to offset+width-1); + SCANOUT : out std_ulogic_vector(offset to offset+width-1); + A1 : in std_ulogic_vector(offset to offset+width-1); + A2 : in std_ulogic_vector(offset to offset+width-1); + QB : out std_ulogic_vector(offset to offset+width-1) + ); + + -- synopsys translate_off + + -- synopsys translate_on + +end entity tri_nand2_nlats; + +architecture tri_nand2_nlats of tri_nand2_nlats is + +begin + + a: if expand_type = 1 generate + constant init_v : std_ulogic_vector(0 to (init'length + width-1)):=init & (0 to width-1=>'0'); + constant zeros : std_ulogic_vector(0 to width-1) := (0 to width-1 => '0'); + + signal sreset : std_ulogic; + signal int_din : std_ulogic_vector(0 to width-1); + signal int_dout : std_ulogic_vector(0 to width-1) := init_v(0 to width-1); + signal vact, vact_b : std_ulogic_vector(0 to width-1); + signal vsreset, vsreset_b : std_ulogic_vector(0 to width-1); + signal vthold, vthold_b : std_ulogic_vector(0 to width-1); + signal din : std_ulogic_vector(0 to width-1); + signal unused : std_ulogic_vector(0 to width-1); + -- synopsys translate_off + -- synopsys translate_on + begin + rst: if needs_sreset = 1 generate + sreset <= LCLK.sreset; + end generate rst; + no_rst: if needs_sreset /=1 generate + sreset <= '0'; + end generate no_rst; + + vsreset <= (0 to width-1 => sreset); + vsreset_b <= (0 to width-1 => not sreset); + din <= A1 and A2; + int_din <= (vsreset_b and din) or + (vsreset and init_v(0 to width-1)); + + vact <= (0 to width-1 => D1CLK); + vact_b <= (0 to width-1 => not D1CLK); + + vthold_b <= (0 to width-1 => D2CLK); + vthold <= (0 to width-1 => not D2CLK); + + l: process (LCLK, vact, int_din, vact_b, int_dout, vsreset, vsreset_b, vthold_b, vthold) + begin + if rising_edge(LCLK.clk) then + int_dout <= (((vact and vthold_b) or vsreset) and int_din) or + (((vact_b or vthold) and vsreset_b) and int_dout); + end if; + end process l; + QB <= not int_dout; + SCANOUT <= zeros; + + unused <= SCANIN; + end generate a; + + + +end tri_nand2_nlats; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_nlat.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_nlat.vhdl new file mode 100644 index 0000000..14e6cf6 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_nlat.vhdl @@ -0,0 +1,118 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library support; + use support.power_logic_pkg.all; +library tri; use tri.tri_latches_pkg.all; +-- pragma translate_off +-- pragma translate_on + +entity tri_nlat is + + generic ( + offset : natural range 0 to 65535 := 0; + reset_inverts_scan : boolean := true; + width : positive range 1 to 65536 := 1 ; + init : std_ulogic_vector := "0" ; + synthclonedlatch : string := "" ; + needs_sreset : integer := 1 ; + expand_type : integer := 1 ); + port ( + vd : inout power_logic; + gd : inout power_logic; + d1clk : in std_ulogic; + d2clk : in std_ulogic; + lclk : in clk_logic; + scan_in : in std_ulogic; + din : in std_ulogic_vector(offset to offset+width-1); + q : out std_ulogic_vector(offset to offset+width-1); + q_b : out std_ulogic_vector(offset to offset+width-1); + scan_out : out std_ulogic + ); + + -- synopsys translate_off + + -- synopsys translate_on + +end entity tri_nlat; + +architecture tri_nlat of tri_nlat is + +begin + + a: if expand_type = 1 generate + constant init_v : std_ulogic_vector(0 to (init'length + width-1)):=init & (0 to width-1=>'0'); + constant zeros : std_ulogic_vector(0 to width-1) := (0 to width-1 => '0'); + + signal sreset : std_ulogic; + signal int_din : std_ulogic_vector(0 to width-1); + signal int_dout : std_ulogic_vector(0 to width-1) := init_v(0 to width-1); + signal vact, vact_b : std_ulogic_vector(0 to width-1); + signal vsreset, vsreset_b : std_ulogic_vector(0 to width-1); + signal vthold, vthold_b : std_ulogic_vector(0 to width-1); + signal unused : std_ulogic; + -- synopsys translate_off + -- synopsys translate_on + begin + rst: if needs_sreset = 1 generate + sreset <= lclk.sreset; + end generate rst; + no_rst: if needs_sreset /=1 generate + sreset <= '0'; + end generate no_rst; + + vsreset <= (0 to width-1 => sreset); + vsreset_b <= (0 to width-1 => not sreset); + int_din <= (vsreset_b and din) or + (vsreset and init_v(0 to width-1)); + + vact <= (0 to width-1 => d1clk); + vact_b <= (0 to width-1 => not d1clk); + + vthold_b <= (0 to width-1 => d2clk); + vthold <= (0 to width-1 => not d2clk); + + l: process (lclk, vact, int_din, vact_b, int_dout, vsreset, vsreset_b, vthold_b, vthold) + begin + if rising_edge(lclk.clk) then + int_dout <= (((vact and vthold_b) or vsreset) and int_din) or + (((vact_b or vthold) and vsreset_b) and int_dout); + end if; + end process l; + q <= int_dout; + q_b <= not int_dout; + scan_out <= zeros(0); + unused <= scan_in; + end generate a; + +end tri_nlat; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_nlat_scan.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_nlat_scan.vhdl new file mode 100644 index 0000000..dfea462 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_nlat_scan.vhdl @@ -0,0 +1,117 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library support; + use support.power_logic_pkg.all; +library tri; use tri.tri_latches_pkg.all; +-- pragma translate_off +-- pragma translate_on + +entity tri_nlat_scan is + + generic ( offset : natural range 0 to 65535 := 0; + width : positive range 1 to 65536 := 1 ; + init : std_ulogic_vector := "0" ; + reset_inverts_scan : boolean := true; + synthclonedlatch : string := "" ; + needs_sreset : integer := 1 ; + expand_type : integer := 1 ); + port ( + vd : inout power_logic; + gd : inout power_logic; + d1clk : in std_ulogic; + d2clk : in std_ulogic; + lclk : in clk_logic; + din : in std_ulogic_vector(offset to offset+width-1); + scan_in : in std_ulogic_vector(offset to offset+width-1); + q : out std_ulogic_vector(offset to offset+width-1); + q_b : out std_ulogic_vector(offset to offset+width-1); + scan_out : out std_ulogic_vector(offset to offset+width-1) + ); + + -- synopsys translate_off + + -- synopsys translate_on + +end entity tri_nlat_scan; + +architecture tri_nlat_scan of tri_nlat_scan is + +begin + + a: if expand_type = 1 generate + constant init_v : std_ulogic_vector(0 to (init'length + width-1)):=init & (0 to width-1=>'0'); + constant zeros : std_ulogic_vector(0 to width-1) := (0 to width-1 => '0'); + + signal sreset : std_ulogic; + signal int_din : std_ulogic_vector(0 to width-1); + signal int_dout : std_ulogic_vector(0 to width-1) := init_v(0 to width-1); + signal vact, vact_b : std_ulogic_vector(0 to width-1); + signal vsreset, vsreset_b : std_ulogic_vector(0 to width-1); + signal vthold, vthold_b : std_ulogic_vector(0 to width-1); + signal unused : std_ulogic_vector(0 to width-1); + -- synopsys translate_off + -- synopsys translate_on + begin + rst: if needs_sreset = 1 generate + sreset <= lclk.sreset; + end generate rst; + no_rst: if needs_sreset /=1 generate + sreset <= '0'; + end generate no_rst; + + vsreset <= (0 to width-1 => sreset); + vsreset_b <= (0 to width-1 => not sreset); + int_din <= (vsreset_b and din) or + (vsreset and init_v(0 to width-1)); + + vact <= (0 to width-1 => d1clk); + vact_b <= (0 to width-1 => not d1clk); + + vthold_b <= (0 to width-1 => d2clk); + vthold <= (0 to width-1 => not d2clk); + + l: process (lclk, vact, int_din, vact_b, int_dout, vsreset, vsreset_b, vthold_b, vthold) + begin + if rising_edge(lclk.clk) then + int_dout <= (((vact and vthold_b) or vsreset) and int_din) or + (((vact_b or vthold) and vsreset_b) and int_dout); + end if; + end process l; + q <= int_dout; + q_b <= not int_dout; + scan_out <= zeros; + unused <= scan_in; + end generate a; + +end tri_nlat_scan; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_nor2_nlats.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_nor2_nlats.vhdl new file mode 100644 index 0000000..800b7ea --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_nor2_nlats.vhdl @@ -0,0 +1,121 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library support; + use support.power_logic_pkg.all; +library tri; use tri.tri_latches_pkg.all; +-- pragma translate_off +-- pragma translate_on + +entity tri_nor2_nlats is + + generic ( + offset : natural range 0 to 65535 := 0; + width : positive range 1 to 65536 := 1 ; + init : std_ulogic_vector := "0" ; + synthclonedlatch : string := "" ; + btr : string := "NLO0001_X1_A12TH" ; + needs_sreset : integer := 1 ; + expand_type : integer := 1 ); + port ( + vd : inout power_logic; + gd : inout power_logic; + LCLK : in clk_logic; + D1CLK : in std_ulogic; + D2CLK : in std_ulogic; + SCANIN : in std_ulogic_vector(offset to offset+width-1); + SCANOUT : out std_ulogic_vector(offset to offset+width-1); + A1 : in std_ulogic_vector(offset to offset+width-1); + A2 : in std_ulogic_vector(offset to offset+width-1); + QB : out std_ulogic_vector(offset to offset+width-1) + ); + + -- synopsys translate_off + + -- synopsys translate_on + +end entity tri_nor2_nlats; + +architecture tri_nor2_nlats of tri_nor2_nlats is + +begin + + a: if expand_type = 1 generate + constant init_v : std_ulogic_vector(0 to (init'length + width-1)):=init & (0 to width-1=>'0'); + constant zeros : std_ulogic_vector(0 to width-1) := (0 to width-1 => '0'); + + signal sreset : std_ulogic; + signal int_din : std_ulogic_vector(0 to width-1); + signal int_dout : std_ulogic_vector(0 to width-1) := init_v(0 to width-1); + signal vact, vact_b : std_ulogic_vector(0 to width-1); + signal vsreset, vsreset_b : std_ulogic_vector(0 to width-1); + signal vthold, vthold_b : std_ulogic_vector(0 to width-1); + signal din : std_ulogic_vector(0 to width-1); + signal unused : std_ulogic_vector(0 to width-1); + -- synopsys translate_off + -- synopsys translate_on + begin + rst: if needs_sreset = 1 generate + sreset <= LCLK.sreset; + end generate rst; + no_rst: if needs_sreset /=1 generate + sreset <= '0'; + end generate no_rst; + + vsreset <= (0 to width-1 => sreset); + vsreset_b <= (0 to width-1 => not sreset); + din <= A1 or A2 ; + int_din <= (vsreset_b and din) or + (vsreset and init_v(0 to width-1)); + + vact <= (0 to width-1 => D1CLK); + vact_b <= (0 to width-1 => not D1CLK); + + vthold_b <= (0 to width-1 => D2CLK); + vthold <= (0 to width-1 => not D2CLK); + + l: process (LCLK, vact, int_din, vact_b, int_dout, vsreset, vsreset_b, vthold_b, vthold) + begin + if rising_edge(LCLK.clk) then + int_dout <= (((vact and vthold_b) or vsreset) and int_din) or + (((vact_b or vthold) and vsreset_b) and int_dout); + end if; + end process l; + QB <= not int_dout; + SCANOUT <= zeros; + + unused <= SCANIN; + end generate a; + + +end tri_nor2_nlats; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_oai22_nlats.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_oai22_nlats.vhdl new file mode 100644 index 0000000..6a9e4ba --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_oai22_nlats.vhdl @@ -0,0 +1,122 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; use ieee.std_logic_1164.all; + use ieee.numeric_std.all; +library support; + use support.power_logic_pkg.all; +library tri; use tri.tri_latches_pkg.all; +-- pragma translate_off +-- pragma translate_on + +entity tri_oai22_nlats is + + generic ( + offset : natural range 0 to 65535 := 0; + width : positive range 1 to 65536 := 1 ; + init : std_ulogic_vector := "0" ; + synthclonedlatch : string := "" ; + btr : string := "NLM0001_X1_A12TH" ; + needs_sreset : integer := 1 ; + expand_type : integer := 1 ); + port ( + vd : inout power_logic; + gd : inout power_logic; + LCLK : in clk_logic; + D1CLK : in std_ulogic; + D2CLK : in std_ulogic; + SCANIN : in std_ulogic_vector(offset to offset+width-1); + SCANOUT : out std_ulogic_vector(offset to offset+width-1); + A1 : in std_ulogic_vector(offset to offset+width-1); + A2 : in std_ulogic_vector(offset to offset+width-1); + B1 : in std_ulogic_vector(offset to offset+width-1); + B2 : in std_ulogic_vector(offset to offset+width-1); + QB : out std_ulogic_vector(offset to offset+width-1) + ); + + -- synopsys translate_off + + -- synopsys translate_on + +end entity tri_oai22_nlats; + +architecture tri_oai22_nlats of tri_oai22_nlats is + +begin + + a: if expand_type = 1 generate + constant init_v : std_ulogic_vector(0 to (init'length + width-1)):=init & (0 to width-1=>'0'); + constant zeros : std_ulogic_vector(0 to width-1) := (0 to width-1 => '0'); + + signal sreset : std_ulogic; + signal int_din : std_ulogic_vector(0 to width-1); + signal int_dout : std_ulogic_vector(0 to width-1) := init_v(0 to width-1); + signal vact, vact_b : std_ulogic_vector(0 to width-1); + signal vsreset, vsreset_b : std_ulogic_vector(0 to width-1); + signal vthold, vthold_b : std_ulogic_vector(0 to width-1); + signal din : std_ulogic_vector(0 to width-1); + signal unused : std_ulogic_vector(0 to width-1); + -- synopsys translate_off + -- synopsys translate_on + begin + rst: if needs_sreset = 1 generate + sreset <= LCLK.sreset; + end generate rst; + no_rst: if needs_sreset /=1 generate + sreset <= '0'; + end generate no_rst; + + vsreset <= (0 to width-1 => sreset); + vsreset_b <= (0 to width-1 => not sreset); + din <= (A1 or A2) and (B1 or B2) ; + int_din <= (vsreset_b and din) or + (vsreset and init_v(0 to width-1)); + + vact <= (0 to width-1 => D1CLK); + vact_b <= (0 to width-1 => not D1CLK); + + vthold_b <= (0 to width-1 => D2CLK); + vthold <= (0 to width-1 => not D2CLK); + + l: process (LCLK, vact, int_din, vact_b, int_dout, vsreset, vsreset_b, vthold_b, vthold) + begin + if rising_edge(LCLK.clk) then + int_dout <= (((vact and vthold_b) or vsreset) and int_din) or + (((vact_b or vthold) and vsreset_b) and int_dout); + end if; + end process l; + QB <= not int_dout; + SCANOUT <= zeros; + + unused <= SCANIN; + end generate a; + + +end tri_oai22_nlats; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_plat.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_plat.vhdl new file mode 100644 index 0000000..4d72300 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_plat.vhdl @@ -0,0 +1,99 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library support; + use support.power_logic_pkg.all; +library tri; use tri.tri_latches_pkg.all; +-- pragma translate_off +-- pragma translate_on + +entity tri_plat is + + generic ( + width : positive range 1 to 65536 := 1 ; + offset : natural range 0 to 65535 := 0 ; + init : integer := 0; + synthclonedlatch : string := "" ; + flushlat : boolean := true ; + expand_type : integer := 1 ); + + port ( + vd : inout power_logic; + gd : inout power_logic; + nclk : in clk_logic; + flush : in std_ulogic; + din : in std_ulogic_vector(offset to offset+width-1); + q : out std_ulogic_vector(offset to offset+width-1) ); + + -- synopsys translate_off + + -- synopsys translate_on + +end entity tri_plat; + +architecture tri_plat of tri_plat is + + constant init_v : std_ulogic_vector(0 to width-1) := std_ulogic_vector( to_unsigned( init, width ) ); + +begin + + a: if expand_type /= 2 generate + signal int_din : std_ulogic_vector(0 to width-1); + signal int_dout : std_ulogic_vector(0 to width-1) := init_v; + signal vsreset, vsreset_b : std_ulogic_vector(0 to width-1); + begin + + vsreset <= (0 to width-1 => nclk.sreset); + vsreset_b <= (0 to width-1 => not nclk.sreset); + + int_din <= (vsreset_b and din) or + (vsreset and init_v); + + l: process (nclk, int_din, flush, din) + begin + + if rising_edge(nclk.clk) then + int_dout <= int_din; + end if; + + if (flush = '1') then + int_dout <= din; + end if; + + end process l; + + q <= int_dout; + + end generate a; + +end tri_plat; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_psro_soft.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_psro_soft.vhdl new file mode 100644 index 0000000..f68ecbe --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_psro_soft.vhdl @@ -0,0 +1,56 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee; +use ieee.std_logic_1164.all ; +library ibm; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +library support; +use support.power_logic_pkg.all; + + +entity tri_psro_soft is + port ( + vdd : inout power_logic; + gnd : inout power_logic; + psro_enable : in std_ulogic_vector(0 to 2); + psro_ringsig : out std_ulogic + ); + +-- synopsys translate_off +-- synopsys translate_on +end tri_psro_soft; + + +architecture tri_psro_soft of tri_psro_soft is +begin + + psro_ringsig <= or_reduce(psro_enable(0 to 2)); + +end tri_psro_soft; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_regk.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_regk.vhdl new file mode 100644 index 0000000..0f58014 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_regk.vhdl @@ -0,0 +1,116 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; use ieee.std_logic_1164.all; + use ieee.numeric_std.all; +library support; + use support.power_logic_pkg.all; +library tri; use tri.tri_latches_pkg.all; +-- pragma translate_off +-- pragma translate_on + +entity tri_regk is + generic ( + width : integer := 4; + offset : integer range 0 to 65535 := 0 ; + init : integer := 0; + synthclonedlatch : string := ""; + needs_sreset : integer := 1 ; + expand_type : integer := 1 ); + + port ( + vd : inout power_logic; + gd : inout power_logic; + nclk : in clk_logic; + act : in std_ulogic := '1'; + forcee : in std_ulogic := '0'; + thold_b : in std_ulogic := '1'; + d_mode : in std_ulogic := '0'; + delay_lclkr : in std_ulogic := '0'; + mpw1_b : in std_ulogic := '1'; + mpw2_b : in std_ulogic := '1'; + din : in std_ulogic_vector(offset to offset+width-1); + dout : out std_ulogic_vector(offset to offset+width-1) ); + + -- synopsys translate_off + + -- synopsys translate_on + +end entity tri_regk; + +architecture tri_regk of tri_regk is + + constant init_v : std_ulogic_vector(0 to width-1) := std_ulogic_vector( to_unsigned( init, width ) ); + constant zeros : std_ulogic_vector(0 to width-1) := (0 to width-1 => '0'); + +begin + + a: if expand_type = 1 generate + signal sreset : std_ulogic; + signal int_din : std_ulogic_vector(0 to width-1); + signal int_dout : std_ulogic_vector(0 to width-1) := init_v; + signal vact, vact_b : std_ulogic_vector(0 to width-1); + signal vsreset, vsreset_b : std_ulogic_vector(0 to width-1); + signal vthold, vthold_b : std_ulogic_vector(0 to width-1); + signal unused : std_ulogic; + -- synopsys translate_off + -- synopsys translate_on + begin + rst: if needs_sreset = 1 generate + sreset <= nclk.sreset; + end generate rst; + no_rst: if needs_sreset /=1 generate + sreset <= '0'; + end generate no_rst; + + vsreset <= (0 to width-1 => sreset); + vsreset_b <= (0 to width-1 => not sreset); + int_din <= (vsreset_b and din) or + (vsreset and init_v); + + vact <= (0 to width-1 => (act or forcee)); + vact_b <= (0 to width-1 => not (act or forcee)); + + vthold_b <= (0 to width-1 => thold_b); + vthold <= (0 to width-1 => not thold_b); + + l: process (nclk, vact, int_din, vact_b, int_dout, vsreset, vsreset_b, vthold_b, vthold) + begin + if rising_edge(nclk.clk) then + int_dout <= (((vact and vthold_b) or vsreset) and int_din) or + (((vact_b or vthold) and vsreset_b) and int_dout); + end if; + end process l; + dout <= int_dout; + + unused <= d_mode or delay_lclkr or mpw1_b or mpw2_b; + end generate a; + +end tri_regk; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_regs.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_regs.vhdl new file mode 100644 index 0000000..cb56921 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_regs.vhdl @@ -0,0 +1,127 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library support; + use support.power_logic_pkg.all; +library tri; use tri.tri_latches_pkg.all; +-- pragma translate_off +-- pragma translate_on + +entity tri_regs is + + generic ( + width : integer := 4; + offset : integer range 0 to 65535 := 0 ; + init : integer := 0; + ibuf : boolean := false; + dualscan : string := ""; + needs_sreset: integer := 1 ; + expand_type : integer := 1 ); + + port ( + vd : inout power_logic; + gd : inout power_logic; + nclk : in clk_logic; + forcee : in std_ulogic := '0'; + thold_b : in std_ulogic := '1'; + delay_lclkr : in std_ulogic := '0'; + scin : in std_ulogic_vector(offset to offset+width-1); + scout : out std_ulogic_vector(offset to offset+width-1); + dout : out std_ulogic_vector(offset to offset+width-1) ); + + -- synopsys translate_off + + -- synopsys translate_on + +end entity tri_regs; + +architecture tri_regs of tri_regs is + + constant init_v : std_ulogic_vector(0 to width-1) := std_ulogic_vector( to_unsigned( init, width ) ); + constant zeros : std_ulogic_vector(0 to width-1) := (0 to width-1 => '0'); + +begin + + a: if expand_type = 1 generate + signal sreset : std_ulogic; + signal int_din : std_ulogic_vector(0 to width-1); + signal int_dout : std_ulogic_vector(0 to width-1) := init_v; + signal vact, vact_b : std_ulogic_vector(0 to width-1); + signal vsreset, vsreset_b : std_ulogic_vector(0 to width-1); + signal vthold, vthold_b : std_ulogic_vector(0 to width-1); + signal unused : std_ulogic_vector(0 to width); + -- synopsys translate_off + -- synopsys translate_on + begin + rst: if needs_sreset = 1 generate + sreset <= nclk.sreset; + end generate rst; + no_rst: if needs_sreset /=1 generate + sreset <= '0'; + end generate no_rst; + + vsreset <= (0 to width-1 => sreset); + vsreset_b <= (0 to width-1 => not sreset); + + int_din <= (vsreset_b and int_dout) or + (vsreset and init_v); + + vact <= (0 to width-1 => forcee); + vact_b <= (0 to width-1 => not forcee); + + vthold_b <= (0 to width-1 => thold_b); + vthold <= (0 to width-1 => not thold_b); + + l: process (nclk, vact, int_din, vact_b, int_dout, vsreset, vsreset_b, vthold_b, vthold) + begin + if rising_edge(nclk.clk) then + int_dout <= (((vact and vthold_b) or vsreset) and int_din) or + (((vact_b or vthold) and vsreset_b) and int_dout); + end if; + end process l; + + cob: if ibuf = true generate + dout <= not int_dout; + end generate cob; + + cnob: if ibuf = false generate + dout <= int_dout; + end generate cnob; + + scout <= zeros; + + unused(0) <= delay_lclkr; + unused(1 to width) <= scin; + end generate a; + +end tri_regs; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_rlmlatch_p.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_rlmlatch_p.vhdl new file mode 100644 index 0000000..74e001b --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_rlmlatch_p.vhdl @@ -0,0 +1,180 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library support; + use support.power_logic_pkg.all; +library tri; use tri.tri_latches_pkg.all; +-- pragma translate_off +-- pragma translate_on + +entity tri_rlmlatch_p is + + generic ( + init : integer := 0; + ibuf : boolean := false; + dualscan : string := ""; + needs_sreset: integer := 1 ; + expand_type : integer := 1 ); + + port ( + vd : inout power_logic; + gd : inout power_logic; + nclk : in clk_logic; + act : in std_ulogic := '1'; + forcee : in std_ulogic := '0'; + thold_b : in std_ulogic := '1'; + d_mode : in std_ulogic := '0'; + sg : in std_ulogic := '0'; + delay_lclkr : in std_ulogic := '0'; + mpw1_b : in std_ulogic := '1'; + mpw2_b : in std_ulogic := '1'; + scin : in std_ulogic := '0'; + din : in std_ulogic; + scout : out std_ulogic; + dout : out std_ulogic); + + -- synopsys translate_off + + -- synopsys translate_on + +end entity tri_rlmlatch_p; + +architecture tri_rlmlatch_p of tri_rlmlatch_p is + + constant width : integer := 1; + constant offset : natural := 0; + constant init_v : std_ulogic_vector(0 to width-1) := std_ulogic_vector( to_unsigned( init, width ) ); + constant zeros : std_ulogic_vector(0 to width-1) := (0 to width-1 => '0'); + +begin + + -- synopsys translate_off + um: if expand_type = 0 generate + component c_rlmreg_p + generic ( width : positive := 4 ; + init : std_ulogic_vector := "0"; + dualscan : string := "" + ); + port ( + nclk : in std_ulogic; + act : in std_ulogic; + thold_b : in std_ulogic; + sg : in std_ulogic; + scin : in std_ulogic_vector(0 to width-1); + din : in std_ulogic_vector(0 to width-1); + dout : out std_ulogic_vector(0 to width-1); + scout : out std_ulogic_vector(0 to width-1) + ); + end component; + signal scanin_inv : std_ulogic; + signal scanout_inv : std_ulogic; + signal act_or_force : std_ulogic; + signal din_buf : std_ulogic; + signal dout_buf : std_ulogic; + begin + act_or_force <= act or forcee; + + cib: + if ibuf = true generate + din_buf <= not din; + dout <= not dout_buf; + end generate cib; + cnib: + if ibuf = false generate + din_buf <= din; + dout <= dout_buf; + end generate cnib; + + l:c_rlmreg_p + generic map (width => width, init => init_v, dualscan => dualscan) + port map ( + nclk => nclk.clk, + act => act_or_force, + thold_b => thold_b, + sg => sg, + scin(0) => scanin_inv, + din(0) => din_buf, + scout(0) => scanout_inv, + dout(0) => dout_buf); + + scanin_inv <= scin xor init_v(0); + scout <= scanout_inv xor init_v(0); + end generate um; + -- synopsys translate_on + + a: if expand_type = 1 generate + signal sreset : std_ulogic; + signal int_din : std_ulogic; + signal int_dout : std_ulogic := init_v(0); + signal unused : std_ulogic; + -- synopsys translate_off + -- synopsys translate_on + begin + rst: if needs_sreset = 1 generate + sreset <= nclk.sreset; + end generate rst; + no_rst: if needs_sreset /=1 generate + sreset <= '0'; + end generate no_rst; + + cib: if ibuf = true generate + int_din <= (not sreset and not din) or + (sreset and init_v(0)); + end generate cib; + cnib: if ibuf = false generate + int_din <= (not sreset and din) or + (sreset and init_v(0)); + end generate cnib; + + l: process (nclk, act, forcee, int_din, int_dout, sreset, thold_b) + begin + if rising_edge(nclk.clk) then + int_dout <= ( (((act or forcee) and thold_b) or sreset ) and int_din ) or + ( ((not act and not forcee) or not thold_b) and not sreset and int_dout); + end if; + end process l; + + cob: if ibuf = true generate + dout <= not int_dout; + end generate cob; + + cnob: if ibuf = false generate + dout <= int_dout; + end generate cnob; + + scout <= zeros(0); + + unused <= d_mode or sg or delay_lclkr or mpw1_b or mpw2_b or scin; + end generate a; + +end tri_rlmlatch_p; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_rlmreg_p.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_rlmreg_p.vhdl new file mode 100644 index 0000000..f80ce5e --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_rlmreg_p.vhdl @@ -0,0 +1,191 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; use ieee.std_logic_1164.all; + use ieee.numeric_std.all; +library support; use support.power_logic_pkg.all; +library tri; use tri.tri_latches_pkg.all; +-- pragma translate_off +-- pragma translate_on + +entity tri_rlmreg_p is + + generic ( + width : integer := 4; + offset : integer range 0 to 65535 := 0 ; + init : integer := 0; + ibuf : boolean := false; + dualscan : string := ""; + needs_sreset: integer := 1 ; + expand_type : integer := 1 ); + + port ( + vd : inout power_logic; + gd : inout power_logic; + nclk : in clk_logic; + act : in std_ulogic := '1'; + forcee : in std_ulogic := '0'; + thold_b : in std_ulogic := '1'; + d_mode : in std_ulogic := '0'; + sg : in std_ulogic := '0'; + delay_lclkr : in std_ulogic := '0'; + mpw1_b : in std_ulogic := '1'; + mpw2_b : in std_ulogic := '1'; + scin : in std_ulogic_vector(offset to offset+width-1); + din : in std_ulogic_vector(offset to offset+width-1); + scout : out std_ulogic_vector(offset to offset+width-1); + dout : out std_ulogic_vector(offset to offset+width-1) ); + + -- synopsys translate_off + + -- synopsys translate_on + +end entity tri_rlmreg_p; + +architecture tri_rlmreg_p of tri_rlmreg_p is + + constant init_v : std_ulogic_vector(0 to width-1) := std_ulogic_vector( to_unsigned( init, width ) ); + constant zeros : std_ulogic_vector(0 to width-1) := (0 to width-1 => '0'); + +begin + + -- synopsys translate_off + um: if expand_type = 0 generate + component c_rlmreg_p + generic ( width : positive := 4 ; + init : std_ulogic_vector := "0"; + dualscan : string := "" + ); + port ( + nclk : in std_ulogic; + act : in std_ulogic; + thold_b : in std_ulogic; + sg : in std_ulogic; + scin : in std_ulogic_vector(0 to width-1); + din : in std_ulogic_vector(0 to width-1); + dout : out std_ulogic_vector(0 to width-1); + scout : out std_ulogic_vector(0 to width-1) + ); + end component; + signal scanin_inv : std_ulogic_vector(0 to width-1); + signal scanout_inv : std_ulogic_vector(0 to width-1); + signal act_or_force : std_ulogic; + signal din_buf : std_ulogic_vector(0 to width-1); + signal dout_buf : std_ulogic_vector(0 to width-1); + begin + act_or_force <= act or forcee; + + cib: + if ibuf = true generate + din_buf <= not din; + dout <= not dout_buf; + end generate cib; + cnib: + if ibuf = false generate + din_buf <= din; + dout <= dout_buf; + end generate cnib; + + l:c_rlmreg_p + generic map (width => width, init => init_v, dualscan => dualscan) + port map ( + nclk => nclk.clk, + act => act_or_force, + thold_b => thold_b, + sg => sg, + scin => scanin_inv, + din => din_buf, + scout => scanout_inv, + dout => dout_buf); + + scanin_inv <= scin xor init_v; + scout <= scanout_inv xor init_v; + end generate um; + -- synopsys translate_on + + a: if expand_type = 1 generate + signal sreset : std_ulogic; + signal int_din : std_ulogic_vector(0 to width-1); + signal int_dout : std_ulogic_vector(0 to width-1) := init_v; + signal vact, vact_b : std_ulogic_vector(0 to width-1); + signal vsreset, vsreset_b : std_ulogic_vector(0 to width-1); + signal vthold, vthold_b : std_ulogic_vector(0 to width-1); + signal unused : std_ulogic_vector(0 to width); + -- synopsys translate_off + -- synopsys translate_on + begin + rst: if needs_sreset = 1 generate + sreset <= nclk.sreset; + end generate rst; + no_rst: if needs_sreset /=1 generate + sreset <= '0'; + end generate no_rst; + + vsreset <= (0 to width-1 => sreset); + vsreset_b <= (0 to width-1 => not sreset); + + cib: if ibuf = true generate + int_din <= (vsreset_b and not din) or + (vsreset and init_v); + end generate cib; + cnib: if ibuf = false generate + int_din <= (vsreset_b and din) or + (vsreset and init_v); + end generate cnib; + + vact <= (0 to width-1 => (act or forcee)); + vact_b <= (0 to width-1 => not (act or forcee)); + + vthold_b <= (0 to width-1 => thold_b); + vthold <= (0 to width-1 => not thold_b); + + l: process (nclk, vact, int_din, vact_b, int_dout, vsreset, vsreset_b, vthold_b, vthold) + begin + if rising_edge(nclk.clk) then + int_dout <= (((vact and vthold_b) or vsreset) and int_din) or + (((vact_b or vthold) and vsreset_b) and int_dout); + end if; + end process l; + + cob: if ibuf = true generate + dout <= not int_dout; + end generate cob; + + cnob: if ibuf = false generate + dout <= int_dout; + end generate cnob; + + scout <= zeros; + + unused(0) <= d_mode or sg or delay_lclkr or mpw1_b or mpw2_b; + unused(1 to width) <= scin; + end generate a; + +end tri_rlmreg_p; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_ser_rlmreg_p.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_ser_rlmreg_p.vhdl new file mode 100644 index 0000000..fba2299 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_ser_rlmreg_p.vhdl @@ -0,0 +1,100 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee,ibm,support,tri; +use ieee.std_logic_1164.all; +use support.power_logic_pkg.all; +use tri.tri_latches_pkg.all; + +entity tri_ser_rlmreg_p is +generic ( + width : positive range 1 to 65536 := 1 ; + offset : natural range 0 to 65535 := 0 ; + init : integer := 0; + ibuf : boolean := false; + dualscan : string := ""; + needs_sreset : integer := 1 ; + expand_type : integer := 1 ); +port ( + vd : inout power_logic; + gd : inout power_logic; + nclk : in clk_logic; + act : in std_ulogic := '1'; + forcee : in std_ulogic := '0'; + thold_b : in std_ulogic := '1'; + d_mode : in std_ulogic := '0'; + sg : in std_ulogic := '0'; + delay_lclkr : in std_ulogic := '0'; + mpw1_b : in std_ulogic := '1'; + mpw2_b : in std_ulogic := '1'; + scin : in std_ulogic_vector(offset to offset+width-1); + din : in std_ulogic_vector(offset to offset+width-1); + scout : out std_ulogic_vector(offset to offset+width-1); + dout : out std_ulogic_vector(offset to offset+width-1)); + + -- synopsys translate_off + -- synopsys translate_on + +end entity tri_ser_rlmreg_p; + +architecture tri_ser_rlmreg_p of tri_ser_rlmreg_p is + +signal dout_b, act_buf, act_buf_b, dout_buf : std_ulogic_vector(offset to offset+width-1); + +begin + +act_buf <= (others=>act); +act_buf_b <= (others=>not(act)); +dout_buf <= not dout_b; +dout <= dout_buf; + +tri_ser_rlmreg_p : entity tri.tri_aoi22_nlats_wlcb(tri_aoi22_nlats_wlcb) + generic map ( + width => width, + offset => offset, + init => init, + ibuf => ibuf, + dualscan=> dualscan, + expand_type => expand_type, + needs_sreset => needs_sreset) + port map (nclk => nclk, vd => vd, gd => gd, + act => act, + forcee => forcee, + d_mode => d_mode, delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, mpw2_b => mpw2_b, + thold_b => thold_b, + sg => sg, + scin => scin, + scout => scout, + A1 => din, + A2 => act_buf, + B1 => dout_buf, + B2 => act_buf_b, + QB => dout_b); + +end tri_ser_rlmreg_p; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_serial_scom2.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_serial_scom2.vhdl new file mode 100644 index 0000000..943c081 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_serial_scom2.vhdl @@ -0,0 +1,973 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; use ieee.std_logic_1164.all; + use ieee.numeric_std.all; +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_unsigned.all; +library support; + use support.power_logic_pkg.all; +library tri; use tri.tri_latches_pkg.all; + +entity tri_serial_scom2 is + + generic ( + width : positive := 64; + internal_addr_decode: boolean := false; + use_addr : std_ulogic_vector := "1000000000000000000000000000000000000000000000000000000000000000"; + addr_is_rdable : std_ulogic_vector := "1000000000000000000000000000000000000000000000000000000000000000"; + addr_is_wrable : std_ulogic_vector := "1000000000000000000000000000000000000000000000000000000000000000"; + pipeline_addr_v : std_ulogic_vector := "0000000000000000000000000000000000000000000000000000000000000000"; + pipeline_paritychk : boolean := false; + satid_nobits : positive := 4; + regid_nobits : positive := 6; + ringid_nobits : positive := 3; + expand_type : integer := 1 ); + + port ( + nclk : in clk_logic; + vd : inout power_logic; + gd : inout power_logic; + scom_func_thold : in std_ulogic; + sg : in std_ulogic; + act_dis_dc : in std_ulogic; + clkoff_dc_b : in std_ulogic; + mpw1_dc_b : in std_ulogic; + mpw2_dc_b : in std_ulogic; + d_mode_dc : in std_ulogic; + delay_lclkr_dc : in std_ulogic; + + func_scan_in : in std_ulogic_vector(0 to + (((width+15)/16)*16)+2*(((((width+15)/16)*16)-1)/16+1)+(2**regid_nobits)+40 ); + func_scan_out : out std_ulogic_vector(0 to + (((width+15)/16)*16)+2*(((((width+15)/16)*16)-1)/16+1)+(2**regid_nobits)+40 ); + + + dcfg_scan_dclk : in std_ulogic; + dcfg_scan_lclk : in clk_logic; + + dcfg_d1clk : in std_ulogic; + dcfg_d2clk : in std_ulogic; + dcfg_lclk : in clk_logic; + + dcfg_scan_in : in std_ulogic_vector(0 to 1); + dcfg_scan_out : out std_ulogic_vector(0 to 1); + + scom_local_act : out std_ulogic; + + sat_id : in std_ulogic_vector(0 to satid_nobits-1); + + scom_dch_in : in std_ulogic; + + scom_cch_in : in std_ulogic; + + scom_dch_out : out std_ulogic; + + scom_cch_out : out std_ulogic; + + sc_req : out std_ulogic; + + sc_ack : in std_ulogic; + + sc_ack_info : in std_ulogic_vector(0 to 1); + + sc_r_nw : out std_ulogic; + + sc_addr : out std_ulogic_vector(0 to regid_nobits-1); + + addr_v : out std_ulogic_vector(0 to use_addr'high); + + sc_rdata : in std_ulogic_vector(0 to width-1); + + sc_wdata : out std_ulogic_vector(0 to width-1); + + sc_wparity : out std_ulogic; + + scom_err : out std_ulogic; + + fsm_reset : in std_ulogic + + ); + -- synopsys translate_off + + -- synopsys translate_on + +end tri_serial_scom2; + +architecture tri_serial_scom2 of tri_serial_scom2 is + +begin + + a: if expand_type /= 2 generate + constant state_width : positive := 5 ; + constant i_width : positive := (((width+15)/16)*16); + constant par_nobits : positive := (i_width-1)/16+1; + constant reg_nobits : positive := regid_nobits; + constant satid_regid_nobits : positive := satid_nobits + regid_nobits; + constant rw_bit_index : positive := satid_regid_nobits + 1; + constant parbit_index : positive := rw_bit_index + 1; + constant head_width : positive := parbit_index + 1; + constant head_init : std_ulogic_vector( 0 to head_width-1) := "0000000000000"; + + constant idle : std_ulogic_vector(0 to state_width-1) := "00000"; + constant rec_head : std_ulogic_vector(0 to state_width-1) := "00011"; + constant check_before : std_ulogic_vector(0 to state_width-1) := "00101"; + constant rec_wdata : std_ulogic_vector(0 to state_width-1) := "00110"; + constant rec_wpar : std_ulogic_vector(0 to state_width-1) := "01001"; + constant exe_cmd : std_ulogic_vector(0 to state_width-1) := "01010"; + constant filler0 : std_ulogic_vector(0 to state_width-1) := "01100"; + constant filler1 : std_ulogic_vector(0 to state_width-1) := "01111"; + constant gen_ulinfo : std_ulogic_vector(0 to state_width-1) := "10001"; + constant send_ulinfo : std_ulogic_vector(0 to state_width-1) := "10010"; + constant send_rdata : std_ulogic_vector(0 to state_width-1) := "10100"; + constant send_0 : std_ulogic_vector(0 to state_width-1) := "10111"; + constant send_1 : std_ulogic_vector(0 to state_width-1) := "11000"; + constant check_wpar : std_ulogic_vector(0 to state_width-1) := "11011"; + constant not_selected : std_ulogic_vector(0 to state_width-1) := "11110"; + + constant eof_wdata : positive := parbit_index-1+64; + constant eof_wpar : positive := eof_wdata + 4; + + constant eof_wdata_n : positive := parbit_index-1+ i_width; + constant eof_wpar_m : positive := eof_wdata + par_nobits; + + + signal is_idle : std_ulogic; + signal is_rec_head : std_ulogic; + signal is_check_before: std_ulogic; + signal is_rec_wdata : std_ulogic; + signal is_rec_wpar : std_ulogic; + signal is_exe_cmd : std_ulogic; + signal is_gen_ulinfo : std_ulogic; + signal is_send_ulinfo : std_ulogic; + signal is_send_rdata : std_ulogic; + signal is_send_0 : std_ulogic; + signal is_send_1 : std_ulogic; + signal is_filler_0 : std_ulogic; + signal is_filler_1 : std_ulogic; + + signal next_state, state_in, state_lt : std_ulogic_vector(0 to state_width-1); + + signal dch_lt : std_ulogic; + signal cch_in, cch_lt : std_ulogic_vector(0 to 1); + + signal reset : std_ulogic; + signal got_head, gor_eofwdata, got_eofwpar, sent_rdata, got_ulhead, do_send_par + ,cntgtheadpluswidth, cntgteofwdataplusparity : std_ulogic; + signal p0_err, any_ack_error, match : std_ulogic; + signal p0_err_in, p0_err_lt : std_ulogic; + signal do_write, do_read : std_ulogic; + signal enable_cnt : std_ulogic; + signal cnt_in, cnt_lt : std_ulogic_vector(0 to 6); + signal head_in, head_lt : std_ulogic_vector(0 to head_width-1); + signal tail_in, tail_lt : std_ulogic_vector(0 to 4); + signal sc_ack_info_in, sc_ack_info_lt : std_ulogic_vector(0 to 1); + signal head_mux : std_ulogic; + + signal data_shifter_in, data_shifter_lt : std_ulogic_vector(0 to i_width-1); + signal data_shifter_lt_tmp : std_ulogic_vector(0 to 63); + + signal datapar_shifter_in, datapar_shifter_lt : std_ulogic_vector(0 to par_nobits-1); + signal data_mux, par_mux : std_ulogic; + signal dch_out_internal_in, dch_out_internal_lt : std_ulogic; + signal parity_satid_regaddr_in : std_ulogic; + signal parity_satid_regaddr_lt : std_ulogic; + signal func_force : std_ulogic; + signal func_thold_b, d1clk, d2clk : std_ulogic; + signal lclk : clk_logic; + signal local_act, local_act_int : std_ulogic; + signal scom_err_in, scom_err_lt : std_ulogic; + signal scom_local_act_in, scom_local_act_lt : std_ulogic; + + signal wpar_err : std_ulogic; + signal wpar_err_in, wpar_err_lt : std_ulogic; + signal par_data_in, par_data_lt : std_ulogic_vector(0 to par_nobits-1); + signal sc_rparity : std_ulogic_vector(0 to par_nobits-1); + + signal read_valid, write_valid : std_ulogic; + signal dec_addr_in, dec_addr_q : std_ulogic_vector(use_addr'range); + signal addr_nvld : std_ulogic; + signal write_nvld, read_nvld : std_ulogic; + signal state_par_error : std_ulogic; + signal sat_id_net : std_ulogic_vector(0 to satid_nobits-1); + + signal unused : std_ulogic_vector(0 to 1); + + signal scom_cch_in_int : std_ulogic; + signal scom_dch_in_int : std_ulogic; + signal scom_cch_input_in, scom_cch_input_lt : std_ulogic; + signal scom_dch_input_in, scom_dch_input_lt : std_ulogic; + + + signal func_scan_temp : std_ulogic; + signal func_scan_temp_1 : std_ulogic; + signal func_scan_temp_2 : std_ulogic; + signal func_scan_temp_3 : std_ulogic; + signal func_scan_temp_4 : std_ulogic; + + signal spare_latch1_in, spare_latch1_lt : std_ulogic; + signal spare_latch2_in, spare_latch2_lt : std_ulogic; + + signal unused_signals : std_ulogic; + + + + begin + assert (or_reduce(use_addr)='1') + report "pcb if component must use at least one address, generic use_addr is all zeroes" + severity error; + + assert (use_addr'length<=2**reg_nobits) + report "use_addr is larger than 2^reg_nobits" + severity error; + + + assert (i_width > 0) + report "has to be in the range of 1..64" + severity error; + + assert (i_width < 65) + report "has to be in the range of 1..64" + severity error; + + + + lcbor_func: entity tri.tri_lcbor(tri_lcbor) + generic map ( expand_type => expand_type ) + port map ( + clkoff_b => clkoff_dc_b, + thold => scom_func_thold, + sg => sg, + act_dis => act_dis_dc, + forcee => func_force, + thold_b => func_thold_b ); + + + lcb_func: entity tri.tri_lcbnd(tri_lcbnd) + generic map ( expand_type => expand_type ) + port map ( + vd => vd, + gd => gd, + act => local_act_int, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + nclk => nclk, + forcee => func_force, + sg => sg, + thold_b => func_thold_b, + d1clk => d1clk, + d2clk => d2clk, + lclk => lclk + ); + + parity_err : entity tri.tri_err_rpt(tri_err_rpt) + generic map ( + width => 1 + , inline => false + , mask_reset_value=> "0" + , needs_sreset => 1 + , expand_type => expand_type ) + port map ( vd => vd, + gd => gd, + err_d1clk => dcfg_d1clk, + err_d2clk => dcfg_d2clk, + err_lclk => dcfg_lclk, + err_scan_in => dcfg_scan_in (0 to 0), + err_scan_out => dcfg_scan_out(0 to 0), + mode_dclk => dcfg_scan_dclk, + mode_lclk => dcfg_scan_lclk, + mode_scan_in => dcfg_scan_in (1 to 1), + mode_scan_out => dcfg_scan_out(1 to 1), + + err_in (0) => state_par_error, + err_out(0) => scom_err_in + ); + + scom_err <= scom_err_lt; + + + func_scan_out(state_width + i_width + 2*par_nobits+head_width+22+(2**regid_nobits) to func_scan_out'high) <= + func_scan_in(state_width + i_width + 2*par_nobits+head_width+22+(2**regid_nobits) to func_scan_out'high) ; + + + sat_id_net <= sat_id; + scom_cch_input_in <= scom_cch_in; + scom_cch_in_int <= scom_cch_input_lt; + scom_dch_input_in <= scom_dch_in; + scom_dch_in_int <= scom_dch_input_lt; + + + + cch_in <= scom_cch_in_int & cch_lt(0); + + reset <= (cch_lt(0) and not scom_cch_in_int) + or fsm_reset + or scom_err_lt; + + local_act <= or_reduce(scom_cch_input_in & cch_lt); + + local_act_int <= local_act or scom_local_act_lt; + + scom_local_act_in <= local_act; + scom_local_act <= scom_local_act_lt; + + scom_cch_out <= cch_lt(0); + + dch_out_internal_in <= head_lt(0) when is_send_ulinfo='1' else + '0' when is_send_0 ='1' else + '1' when is_send_1 ='1' else + data_shifter_lt(0) when (is_send_rdata and not do_send_par)='1' else + datapar_shifter_lt(0) when (is_send_rdata and do_send_par)='1' else + dch_lt; + + scom_dch_out <= dch_out_internal_lt; + + sc_req <= is_exe_cmd; + sc_addr <= head_lt(satid_nobits+1 to satid_regid_nobits); + sc_r_nw <= head_lt(rw_bit_index); + + copy2sc_wdata: if width<64 generate + copy2sc_wdata_loop_1: for i in 0 to width-1 generate + sc_wdata(i) <= data_shifter_lt(i); + end generate copy2sc_wdata_loop_1; + + + end generate copy2sc_wdata; + + copy2sc_wdata_all: if width=64 generate + sc_wdata <= data_shifter_lt; + end generate copy2sc_wdata_all; + + + sc_wparity <= xor_reduce(datapar_shifter_lt); + + fsm_transition: process (state_lt, got_head, gor_eofwdata, got_eofwpar, + got_ulhead, sent_rdata, p0_err, any_ack_error, + match, do_write, do_read, + cch_lt(0), dch_lt, sc_ack, wpar_err, read_nvld) + + begin + next_state <= state_lt; + case state_lt is + when idle => if dch_lt='1' then + next_state <= rec_head; + end if; + + when rec_head => if (got_head)='1' then + next_state <= check_before; + end if; + + when check_before => if match='0' then + next_state <= not_selected; + elsif ( (read_nvld or p0_err) and do_read)='1' then + next_state <= filler0; + elsif (not p0_err and not read_nvld and do_read)='1' then + next_state <= exe_cmd; + else + next_state <= rec_wdata; + end if; + + when rec_wdata => if gor_eofwdata='1' then + next_state <= rec_wpar; + end if; + + when rec_wpar => if (got_eofwpar and not p0_err)='1' then + next_state <= check_wpar; + elsif (got_eofwpar and p0_err)='1' then + next_state <= filler0; + end if; + + when check_wpar => if wpar_err='0' then + next_state <= exe_cmd; + else + next_state <= filler1; + end if; + + when exe_cmd => if sc_ack='1' then + next_state <= filler1; + end if; + + when filler0 => next_state <= filler1; + + when filler1 => next_state <= gen_ulinfo; + + when gen_ulinfo => next_state <= send_ulinfo; + + when send_ulinfo => if (got_ulhead and (do_write or (do_read and any_ack_error)))='1' then + next_state <= send_0; + elsif (got_ulhead and do_read)='1' then + next_state <= send_rdata; + end if; + + when send_rdata => if sent_rdata='1' then + next_state <= send_0; + end if; + + when send_0 => next_state <= send_1; + + when send_1 => next_state <= idle; + + when not_selected => if cch_lt(0)='0' then + next_state <= idle; + end if; + + when others => next_state <= idle; + + end case; + + end process fsm_transition; + + state_in <= state_lt when local_act='0' else + idle when reset='1' else + next_state; + + state_par_error <= xor_reduce(state_lt); + + is_idle <= (state_lt=idle); + is_rec_head <= (state_lt=rec_head); + is_check_before <= (state_lt=check_before); + is_rec_wdata <= (state_lt=rec_wdata); + is_rec_wpar <= (state_lt=rec_wpar); + is_exe_cmd <= (state_lt=exe_cmd); + is_gen_ulinfo <= (state_lt=gen_ulinfo); + is_send_ulinfo <= (state_lt=send_ulinfo); + is_send_rdata <= (state_lt=send_rdata); + is_send_0 <= (state_lt=send_0); + is_send_1 <= (state_lt=send_1); + is_filler_0 <= (state_lt=filler0); + is_filler_1 <= (state_lt=filler1); + + enable_cnt <= is_rec_head + or is_check_before + or is_rec_wdata + or is_rec_wpar + or is_send_ulinfo + or is_send_rdata + or is_send_0 + or is_send_1 + ; + cnt_in <= (others=>'0') when ((is_idle or is_gen_ulinfo) = '1') else + cnt_lt + "0000001" when (enable_cnt = '1') else + cnt_lt; + + got_head <= (cnt_lt = (1+satid_nobits+regid_nobits)); + + got_ulhead <= (cnt_lt = (1+satid_nobits+regid_nobits+4)); + + gor_eofwdata <= (cnt_lt = eof_wdata); + got_eofwpar <= (cnt_lt = eof_wpar); + + sent_rdata <= (cnt_lt=tconv(83,7)); + + cntgtheadpluswidth <= (cnt_lt > eof_wdata_n); + cntgteofwdataplusparity <= (cnt_lt > eof_wpar_m); + + do_send_par <= (cnt_lt > 79); + + head_in(head_width-2 to head_width-1) <= head_lt(head_width-1) & dch_lt when (is_rec_head or (is_idle and dch_lt))='1' else + head_lt(head_width-2 to head_width-1); + + head_in(0 to satid_regid_nobits) <= head_lt(1 to satid_regid_nobits) & head_mux when (is_rec_head or is_send_ulinfo)='1' else + head_lt(0 to satid_regid_nobits); + + head_mux <= head_lt(rw_bit_index) when is_rec_head='1' else + tail_lt(0); + + + tail_in(4) <= xor_reduce ( parity_satid_regaddr_lt & tail_lt(0) & (wpar_err and do_write) & sc_ack_info_lt(0 to 1)) + when is_gen_ulinfo='1'and (internal_addr_decode=false) else + xor_reduce ( parity_satid_regaddr_lt & tail_lt(0) & (wpar_err and do_write) & (write_nvld or read_nvld) & addr_nvld ) + when is_gen_ulinfo='1'and (internal_addr_decode=true) + else tail_lt(4); + + + + tail_in(2 to 3) <= sc_ack_info_lt(0 to 1) when is_gen_ulinfo='1' and internal_addr_decode=false else + (write_nvld or read_nvld) & addr_nvld when is_gen_ulinfo='1' and internal_addr_decode=true else + tail_lt(3 to 4) when is_send_ulinfo='1' else + tail_lt(2 to 3); + + + + tail_in(1) <= (wpar_err and do_write) when is_gen_ulinfo='1' else + tail_lt(2) when is_send_ulinfo='1' else + tail_lt(1); + + tail_in(0) <= not p0_err when is_check_before='1' else + tail_lt(1) when is_send_ulinfo='1' else + tail_lt(0); + + sc_ack_info_in <= sc_ack_info when (is_exe_cmd and sc_ack)='1' else + "00" when is_idle='1' else + sc_ack_info_lt; + + + do_write <= not do_read; + do_read <= head_lt(rw_bit_index); + match <= (head_lt(1 to satid_nobits)=sat_id_net); + + p0_err_in <= '0' when (is_idle = '1') else + p0_err_lt xor head_in(parbit_index) when (is_rec_head = '1') else + p0_err_lt ; + p0_err <= p0_err_lt; + parity_satid_regaddr_in <= xor_reduce (sat_id_net & head_lt(satid_nobits+1 to satid_regid_nobits)); + + any_ack_error <= or_reduce(sc_ack_info_lt); + + + data_mux <= dch_lt when (is_check_before or is_rec_wdata)='1' else + '0'; + + data_shifter_in_1: if (width = i_width) generate + data_shifter_in <= data_shifter_lt(1 to i_width-1) & data_mux when (is_check_before or + (is_rec_wdata and not cntgtheadpluswidth) or + is_send_rdata)='1' else + (sc_rdata(0 to width-1)) when (is_exe_cmd and sc_ack and do_read)='1' else + data_shifter_lt; + end generate data_shifter_in_1; + + data_shifter_in_2: if (width < i_width) generate + data_shifter_in <= data_shifter_lt(1 to i_width-1) & data_mux when (is_check_before or + (is_rec_wdata and not cntgtheadpluswidth) or + is_send_rdata)='1' else + (sc_rdata(0 to width-1) & (width to i_width-1 =>'0')) when (is_exe_cmd and sc_ack and do_read)='1' else + data_shifter_lt; + end generate data_shifter_in_2; + par_mux <= dch_lt when (is_rec_wpar)='1' else + '0'; + + datapar_shifter_in <= datapar_shifter_lt(1 to par_nobits-1) & par_mux when ((is_rec_wpar and not cntgteofwdataplusparity)or + (is_send_rdata and do_send_par))='1' else + sc_rparity when (is_filler_1 ='1') else + datapar_shifter_lt; + + + data_shifter_move_1: if (width = i_width) generate + data_shifter_lt_tmp (0 to width-1) <= data_shifter_lt; + data_shifter_padding_1: if width < 64 generate + data_shifter_lt_tmp(width to 63) <= (others=>'0'); + end generate data_shifter_padding_1; + end generate data_shifter_move_1; + + data_shifter_move_2: if (width < i_width) generate + data_shifter_lt_tmp(0 to width-1) <= data_shifter_lt(0 to width-1); + data_shifter_lt_tmp(width to i_width-1) <= data_shifter_lt(width to i_width-1); + data_shifter_padding_1: if i_width < 64 generate + data_shifter_lt_tmp(i_width to 63) <= (others=>'0'); + end generate data_shifter_padding_1; + end generate data_shifter_move_2; + + wdata_par_check: for i in 0 to par_nobits-1 generate + par_data_in(i) <= xor_reduce(data_shifter_lt_tmp(16*i to 16*(i+1)-1)); + end generate wdata_par_check; + + wdata_par_check_pipe: if pipeline_paritychk=true generate + state: entity tri.tri_nlat_scan(tri_nlat_scan) + generic map( width => par_nobits, + needs_sreset => 1, + expand_type => expand_type ) + port map + ( d1clk => d1clk + , vd => vd + , gd => gd + , lclk => lclk + , d2clk => d2clk + , scan_in => func_scan_in (state_width+i_width+par_nobits+head_width+22 to state_width+i_width+2*par_nobits+head_width+21) + , scan_out => func_scan_out(state_width+i_width+par_nobits+head_width+22 to state_width+i_width+2*par_nobits+head_width+21) + , din => par_data_in + , q => par_data_lt + ); + end generate wdata_par_check_pipe; + + wdata_par_check_nopipe: if pipeline_paritychk=false generate + par_data_lt <= par_data_in; + func_scan_out(state_width+i_width+par_nobits+head_width+22 to state_width+i_width+2*par_nobits+head_width+21) + <= func_scan_in (state_width+i_width+par_nobits+head_width+22 to state_width+i_width+2*par_nobits+head_width+21); + + end generate wdata_par_check_nopipe; + + wpar_err_in <= or_reduce(par_data_in xor datapar_shifter_in); + wpar_err <= wpar_err_lt; + + rdata_parity_gen: for i in 0 to par_nobits-1 generate + sc_rparity(i) <= xor_reduce(data_shifter_lt_tmp(16*i to 16*(i+1)-1)); + end generate rdata_parity_gen; + + internal_addr_decoding: if internal_addr_decode=true generate + foralladdresses : for i in use_addr'range generate + addr_bit_set : if (use_addr(i) = '1') generate + dec_addr_in(i) <= (head_lt(satid_nobits+1 to satid_regid_nobits) = tconv(i, reg_nobits)); + + latch_for_onehot : if pipeline_addr_v(i) = '1' generate + dec_addr : entity tri.tri_nlat(tri_nlat) + generic map( width => 1, + needs_sreset => 1, + expand_type => expand_type) + port map ( d1clk => d1clk, + vd => vd, + gd => gd, + d2clk => d2clk, + lclk => lclk, + scan_in => func_scan_in(state_width+i_width+2*par_nobits+head_width+22 +i), + din(0) => dec_addr_in(i), + q(0) => dec_addr_q(i), + scan_out => func_scan_out(state_width+i_width+2*par_nobits+head_width+22 +i) ); + end generate latch_for_onehot; + + no_latch_for_onehot : if pipeline_addr_v(i) = '0' generate + func_scan_out(state_width+i_width+2*par_nobits+head_width+22 +i) <= func_scan_in(state_width+i_width+2*par_nobits+head_width+22 +i); + dec_addr_q(i) <= dec_addr_in(i); + end generate no_latch_for_onehot; + + end generate addr_bit_set; + addr_bit_notset : if (use_addr(i) /= '1') generate + func_scan_out(state_width+i_width+2*par_nobits+head_width+22+i) <= func_scan_in(state_width+i_width+2*par_nobits+head_width+22 +i); + dec_addr_in(i) <= '0'; + dec_addr_q(i) <= dec_addr_in(i); + end generate addr_bit_notset; + end generate foralladdresses; + read_valid <= or_reduce(dec_addr_in and addr_is_rdable); + write_valid <= or_reduce(dec_addr_in and addr_is_wrable); + addr_nvld <= not or_reduce(dec_addr_in); + write_nvld <= (not write_valid and not addr_nvld) and do_write; + read_nvld <= (not read_valid and not addr_nvld) and do_read; + + unused <= "00"; + end generate internal_addr_decoding; + + + external_addr_decoding: if internal_addr_decode=false generate + foralladdresses : for i in use_addr'range generate + func_scan_out(state_width+i_width+2*par_nobits+head_width+22+i) <= func_scan_in(state_width+i_width+2*par_nobits+head_width+22 +i); + dec_addr_in(i) <= '0'; + dec_addr_q(i) <= dec_addr_in(i); + end generate foralladdresses; + read_valid <= '1'; + write_valid<= '1'; + addr_nvld <= '0'; + write_nvld <= '0'; + read_nvld <= '0'; + + unused <= write_valid & read_valid; + end generate external_addr_decoding; + + + + short_unused_addr_range: for i in use_addr'high+1 to 63 generate + func_scan_out(state_width+i_width+2*par_nobits+head_width+22+i) <= func_scan_in(state_width+i_width+2*par_nobits+head_width+22+i); + end generate short_unused_addr_range; + + addr_v <= dec_addr_q(0 to use_addr'high); + + + state: entity tri.tri_nlat_scan(tri_nlat_scan) + generic map( width => state_width, init => idle, needs_sreset => 1, expand_type => expand_type ) + port map + ( d1clk => d1clk + , vd => vd + , gd => gd + , lclk => lclk + , d2clk => d2clk + , scan_in => func_scan_in (0 to state_width-1) + , scan_out => func_scan_out(0 to state_width-1) + , din => state_in + , q => state_lt + ); + + counter: entity tri.tri_nlat_scan(tri_nlat_scan) + generic map( width => 7, init => "0000000", needs_sreset => 1, expand_type => expand_type ) + port map + ( d1clk => d1clk + , vd => vd + , gd => gd + , lclk => lclk + , d2clk => d2clk + , scan_in => func_scan_in (state_width to state_width+6) + , scan_out => func_scan_out(state_width to state_width+6) + , din => cnt_in + , q => cnt_lt + ); + + data_shifter: entity tri.tri_nlat_scan(tri_nlat_scan) + generic map( width => i_width, needs_sreset => 1, expand_type => expand_type ) + port map + ( d1clk => d1clk + , vd => vd + , gd => gd + , lclk => lclk + , d2clk => d2clk + , scan_in => func_scan_in (state_width+7 to state_width+i_width+6) + , scan_out => func_scan_out(state_width+7 to state_width+i_width+6) + , din => data_shifter_in + , q => data_shifter_lt + ); + + datapar_shifter: entity tri.tri_nlat_scan(tri_nlat_scan) + generic map( width => par_nobits, needs_sreset => 1, expand_type => expand_type ) + port map + ( d1clk => d1clk + , vd => vd + , gd => gd + , lclk => lclk + , d2clk => d2clk + , scan_in => func_scan_in (state_width+i_width+7 to state_width+i_width+par_nobits+6) + , scan_out => func_scan_out(state_width+i_width+7 to state_width+i_width+par_nobits+6) + , din => datapar_shifter_in + , q => datapar_shifter_lt + ); + + head_lat: entity tri.tri_nlat_scan(tri_nlat_scan) + generic map( width => head_width, init => head_init, needs_sreset => 1, expand_type => expand_type ) + port map + ( d1clk => d1clk + , vd => vd + , gd => gd + , lclk => lclk + , d2clk => d2clk + , scan_in => func_scan_in (state_width+i_width+par_nobits+7 to state_width+i_width+par_nobits+head_width+6) + , scan_out => func_scan_out(state_width+i_width+par_nobits+7 to state_width+i_width+par_nobits+head_width+6) + , din => head_in + , q => head_lt + ); + + tail_lat: entity tri.tri_nlat_scan(tri_nlat_scan) + generic map( width => 5, init => "00000", needs_sreset => 1, expand_type => expand_type ) + port map + ( d1clk => d1clk, + vd => vd, + gd => gd, + lclk => lclk, + d2clk => d2clk, + scan_in => func_scan_in (state_width+i_width+par_nobits+head_width+7 to state_width+i_width+par_nobits+head_width+11), + scan_out => func_scan_out(state_width+i_width+par_nobits+head_width+7 to state_width+i_width+par_nobits+head_width+11), + din => tail_in, + q => tail_lt + ); + + dch_inlatch: entity tri.tri_nlat(tri_nlat) + generic map( width => 1, needs_sreset => 1, expand_type => expand_type ) + port map + ( d1clk => d1clk + , vd => vd + , gd => gd + , lclk => lclk + , d2clk => d2clk + , scan_in => func_scan_in (state_width+i_width+par_nobits+head_width+12) + , scan_out => func_scan_out(state_width+i_width+par_nobits+head_width+12) + , din(0) => scom_dch_in_int + , q(0) => dch_lt + ); + + + ack_info: entity tri.tri_nlat_scan(tri_nlat_scan) + generic map( width => 2, needs_sreset => 1, expand_type => expand_type ) + port map + ( d1clk => d1clk + , vd => vd + , gd => gd + , lclk => lclk + , d2clk => d2clk + , scan_in => func_scan_in (state_width+i_width+par_nobits+head_width+13 to state_width+i_width+par_nobits+head_width+14) + , scan_out => func_scan_out(state_width+i_width+par_nobits+head_width+13 to state_width+i_width+par_nobits+head_width+14) + , din => sc_ack_info_in + , q => sc_ack_info_lt + ); + + dch_outlatch: entity tri.tri_nlat(tri_nlat) + generic map( width => 1, needs_sreset => 1, expand_type => expand_type ) + port map + ( d1clk => d1clk + , vd => vd + , gd => gd + , lclk => lclk + , d2clk => d2clk + , scan_in => func_scan_in (state_width+i_width+par_nobits+head_width+15) + , scan_out => func_scan_out(state_width+i_width+par_nobits+head_width+15) + , din(0) => dch_out_internal_in + , q(0) => dch_out_internal_lt + ); + + cch_latches: entity tri.tri_nlat_scan(tri_nlat_scan) + generic map( width => 2, needs_sreset => 1, expand_type => expand_type ) + port map + ( d1clk => d1clk + , vd => vd + , gd => gd + , lclk => lclk + , d2clk => d2clk + , scan_in => func_scan_in (state_width+i_width+par_nobits+head_width+16 to state_width+i_width+par_nobits+head_width+17) + , scan_out => func_scan_out(state_width+i_width+par_nobits+head_width+16 to state_width+i_width+par_nobits+head_width+17) + , din => cch_in + , q => cch_lt + ); + + scom_err_latch: entity tri.tri_nlat(tri_nlat) + generic map( width => 1, needs_sreset => 1, expand_type => expand_type ) + port map + ( d1clk => d1clk + , vd => vd + , gd => gd + , lclk => lclk + , d2clk => d2clk + , scan_in => func_scan_in (state_width+i_width+par_nobits+head_width+18) + , scan_out => func_scan_out(state_width+i_width+par_nobits+head_width+18) + , din(0) => scom_err_in + , q(0) => scom_err_lt + ); + + scom_local_act_latch: entity tri.tri_nlat(tri_nlat) + generic map( width => 1, needs_sreset => 1, expand_type => expand_type ) + port map + ( d1clk => d1clk + , vd => vd + , gd => gd + , lclk => lclk + , d2clk => d2clk + , scan_in => func_scan_in (state_width+i_width+par_nobits+head_width+19) + , scan_out => func_scan_out(state_width+i_width+par_nobits+head_width+19) + , din(0) => scom_local_act_in + , q(0) => scom_local_act_lt + ); + + spare_latch1: entity tri.tri_nlat(tri_nlat) + generic map( width => 1, needs_sreset => 1, expand_type => expand_type ) + port map + ( d1clk => d1clk + , vd => vd + , gd => gd + , lclk => lclk + , d2clk => d2clk + , scan_in => func_scan_in (state_width+i_width+par_nobits+head_width+20) + , scan_out => func_scan_out(state_width+i_width+par_nobits+head_width+20) + , din(0) => spare_latch1_in + , q(0) => spare_latch1_lt + ); + + spare_latch2: entity tri.tri_nlat(tri_nlat) + generic map( width => 1, needs_sreset => 1, expand_type => expand_type ) + port map + ( d1clk => d1clk + , vd => vd + , gd => gd + , lclk => lclk + , d2clk => d2clk + , scan_in => func_scan_in(state_width+i_width+par_nobits+head_width+21) + , scan_out => func_scan_temp + , din(0) => spare_latch2_in + , q(0) => spare_latch2_lt + ); + + scom_cch_input_latch: entity tri.tri_nlat(tri_nlat) + generic map( width => 1, needs_sreset => 1, expand_type => expand_type ) + port map + ( d1clk => d1clk + , vd => vd + , gd => gd + , lclk => lclk + , d2clk => d2clk + , scan_in => func_scan_temp + , scan_out => func_scan_temp_1 + , din(0) => scom_cch_input_in + , q(0) => scom_cch_input_lt + ); + + scom_dch_input_latch: entity tri.tri_nlat(tri_nlat) + generic map( width => 1, needs_sreset => 1, expand_type => expand_type ) + port map + ( d1clk => d1clk + , vd => vd + , gd => gd + , lclk => lclk + , d2clk => d2clk + , scan_in => func_scan_temp_1 + , scan_out => func_scan_temp_2 + , din(0) => scom_dch_input_in + , q(0) => scom_dch_input_lt + ); + + parity_reg1: entity tri.tri_nlat(tri_nlat) + generic map( width => 1, needs_sreset => 1, expand_type => expand_type ) + port map + ( d1clk => d1clk + , vd => vd + , gd => gd + , lclk => lclk + , d2clk => d2clk + , scan_in => func_scan_temp_2 + , scan_out => func_scan_temp_3 + , din(0) => parity_satid_regaddr_in + , q(0) => parity_satid_regaddr_lt + ); + + p0_err_latch: entity tri.tri_nlat(tri_nlat) + generic map( width => 1, needs_sreset => 1, expand_type => expand_type ) + port map + ( d1clk => d1clk + , vd => vd + , gd => gd + , lclk => lclk + , d2clk => d2clk + , scan_in => func_scan_temp_3 + , scan_out => func_scan_temp_4 + , din(0) => p0_err_in + , q(0) => p0_err_lt + ); + + wpar_err_latch: entity tri.tri_nlat(tri_nlat) + generic map( width => 1, needs_sreset => 1, expand_type => expand_type ) + port map + ( d1clk => d1clk + , vd => vd + , gd => gd + , lclk => lclk + , d2clk => d2clk + , scan_in => func_scan_temp_4 + , scan_out => func_scan_out(state_width+i_width+par_nobits+head_width+21) + , din(0) => wpar_err_in + , q(0) => wpar_err_lt + ); + + unused_signals <= or_reduce ( is_filler_0 & is_filler_1 + & spare_latch1_lt + & spare_latch2_lt + & par_data_lt + & d_mode_dc ) ; + + spare_latch1_in <= '0'; + spare_latch2_in <= '0'; + + + end generate a; + +end tri_serial_scom2; + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_slat_scan.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_slat_scan.vhdl new file mode 100644 index 0000000..7c942ae --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_slat_scan.vhdl @@ -0,0 +1,80 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; use ieee.std_logic_1164.all; + use ieee.numeric_std.all; +library support; use support.power_logic_pkg.all; +library tri; use tri.tri_latches_pkg.all; + +entity tri_slat_scan is + + generic ( width : positive range 1 to 65536 := 1 ; + offset : natural range 0 to 65535 := 0; + init : std_ulogic_vector := "0" ; + synthclonedlatch : string := "" ; + btr : string := "c_slat_scan" ; + reset_inverts_scan : boolean := true; + expand_type : integer := 1 ); + port ( + vd : inout power_logic; + gd : inout power_logic; + dclk : in std_ulogic; + lclk : in clk_logic; + scan_in : in std_ulogic_vector(offset to offset+width-1); + scan_out : out std_ulogic_vector(offset to offset+width-1); + q : out std_ulogic_vector(offset to offset+width-1); + q_b : out std_ulogic_vector(offset to offset+width-1) + ); + + -- synopsys translate_off + + -- synopsys translate_on + +end entity tri_slat_scan; + +architecture tri_slat_scan of tri_slat_scan is + +begin + + a: if expand_type = 1 generate + constant zeros : std_ulogic_vector(0 to width-1) := (0 to width-1 => '0'); + constant initv : std_ulogic_vector(0 to (init'length + width-1)):=init & (0 to width-1=>'0'); + signal unused : std_ulogic_vector(0 to width); + -- synopsys translate_off + -- synopsys translate_on + begin + scan_out <= zeros; + q <= initv(0 to width-1); + q_b <= not initv(0 to width-1); + unused(0) <= dclk; + unused(1 to width) <= scan_in; + end generate a; + +end tri_slat_scan; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/a2l2_axi.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/a2l2_axi.vhdl new file mode 100644 index 0000000..bfde7b1 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/a2l2_axi.vhdl @@ -0,0 +1,1424 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.all; +use work.a2x_pkg.all; + +entity a2l2_axi is + generic ( + threads : integer := 4; + xu_real_data_add : integer := 42; + st_data_32b_mode : integer := 1; + ac_st_data_32b_mode : integer := 1; + stores_32B : boolean := false; + lpid_width : integer := 8; + ld_queue_size : integer := 4; + st_queue_size : integer := 16; + C_m00_AXI_ID_WIDTH : integer := 4; + C_m00_AXI_ADDR_WIDTH : integer := 32; + C_m00_AXI_DATA_WIDTH : integer := 32; + C_m00_AXI_AWUSER_WIDTH : integer := 4; + C_m00_AXI_ARUSER_WIDTH : integer := 4; + C_m00_AXI_WUSER_WIDTH : integer := 4; + C_m00_AXI_RUSER_WIDTH : integer := 4; + C_m00_AXI_BUSER_WIDTH : integer := 4 + ); + port ( + clk : in std_logic; + reset_n : in std_logic; + err : out std_logic_vector(0 to 3); + + ac_an_req_pwr_token : in std_logic; + ac_an_req : in std_logic; + ac_an_req_endian : in std_logic; + ac_an_req_ld_core_tag : in std_logic_vector(0 to 4); + ac_an_req_ld_xfr_len : in std_logic_vector(0 to 2); + ac_an_req_ra : in std_logic_vector(64-xu_real_data_add to 63); + ac_an_req_thread : in std_logic_vector(0 to 2); + ac_an_req_ttype : in std_logic_vector(0 to 5); + ac_an_req_user_defined : in std_logic_vector(0 to 3); + ac_an_req_wimg_g : in std_logic; + ac_an_req_wimg_i : in std_logic; + ac_an_req_wimg_m : in std_logic; + ac_an_req_wimg_w : in std_logic; + + ac_an_st_data_pwr_token : in std_logic; + ac_an_st_byte_enbl : in std_logic_vector(0 to 15+(st_data_32b_mode*16)); + ac_an_st_data : in std_logic_vector(0 to 127+(st_data_32b_mode*128)); + + an_ac_reld_data_coming : out std_logic; + an_ac_reld_core_tag : out std_logic_vector(0 to 4); + an_ac_reld_data : out std_logic_vector(0 to 127); + an_ac_reld_data_vld : out std_logic; + an_ac_reld_ecc_err : out std_logic; + an_ac_reld_ecc_err_ue : out std_logic; + an_ac_reld_qw : out std_logic_vector(57 to 59); + an_ac_reld_crit_qw : out std_logic; + an_ac_reld_l1_dump : out std_logic; + + an_ac_req_ld_pop : out std_logic; + an_ac_req_st_pop : out std_logic; + an_ac_req_st_gather : out std_logic; + an_ac_req_st_pop_thrd : out std_logic_vector(0 to 2); + an_ac_reservation_vld : out std_logic_vector(0 to threads-1); + an_ac_stcx_complete : out std_logic_vector(0 to 3); + an_ac_stcx_pass : out std_logic_vector(0 to 3); + an_ac_sync_ack : out std_logic_vector(0 to 3); + + m00_axi_awid : out std_logic_vector(C_M00_AXI_ID_WIDTH-1 downto 0); + m00_axi_awaddr : out std_logic_vector(C_M00_AXI_ADDR_WIDTH-1 downto 0); + m00_axi_awlen : out std_logic_vector(7 downto 0); + m00_axi_awsize : out std_logic_vector(2 downto 0); + m00_axi_awburst : out std_logic_vector(1 downto 0); + m00_axi_awlock : out std_logic; + m00_axi_awcache : out std_logic_vector(3 downto 0); + m00_axi_awprot : out std_logic_vector(2 downto 0); + m00_axi_awqos : out std_logic_vector(3 downto 0); + m00_axi_awuser : out std_logic_vector(C_M00_AXI_AWUSER_WIDTH-1 downto 0); + m00_axi_awvalid : out std_logic; + m00_axi_awready : in std_logic; + m00_axi_wdata : out std_logic_vector(C_M00_AXI_DATA_WIDTH-1 downto 0); + m00_axi_wstrb : out std_logic_vector(C_M00_AXI_DATA_WIDTH/8-1 downto 0); + m00_axi_wlast : out std_logic; + m00_axi_wuser : out std_logic_vector(C_M00_AXI_WUSER_WIDTH-1 downto 0); + m00_axi_wvalid : out std_logic; + m00_axi_wready : in std_logic; + m00_axi_bid : in std_logic_vector(C_M00_AXI_ID_WIDTH-1 downto 0); + m00_axi_bresp : in std_logic_vector(1 downto 0); + m00_axi_buser : in std_logic_vector(C_M00_AXI_BUSER_WIDTH-1 downto 0); + m00_axi_bvalid : in std_logic; + m00_axi_bready : out std_logic; + m00_axi_arid : out std_logic_vector(C_M00_AXI_ID_WIDTH-1 downto 0); + m00_axi_araddr : out std_logic_vector(C_M00_AXI_ADDR_WIDTH-1 downto 0); + m00_axi_arlen : out std_logic_vector(7 downto 0); + m00_axi_arsize : out std_logic_vector(2 downto 0); + m00_axi_arburst : out std_logic_vector(1 downto 0); + m00_axi_arlock : out std_logic; + m00_axi_arcache : out std_logic_vector(3 downto 0); + m00_axi_arprot : out std_logic_vector(2 downto 0); + m00_axi_arqos : out std_logic_vector(3 downto 0); + m00_axi_aruser : out std_logic_vector(C_M00_AXI_ARUSER_WIDTH-1 downto 0); + m00_axi_arvalid : out std_logic; + m00_axi_arready : in std_logic; + m00_axi_rid : in std_logic_vector(C_M00_AXI_ID_WIDTH-1 downto 0); + m00_axi_rdata : in std_logic_vector(C_M00_AXI_DATA_WIDTH-1 downto 0); + m00_axi_rresp : in std_logic_vector(1 downto 0); + m00_axi_rlast : in std_logic; + m00_axi_ruser : in std_logic_vector(C_M00_AXI_RUSER_WIDTH-1 downto 0); + m00_axi_rvalid : in std_logic; + m00_axi_rready : out std_logic + ); +end a2l2_axi; + +architecture a2l2_axi of a2l2_axi is + +signal reload_d: A2L2RELOAD; +signal reload_q: A2L2RELOAD; + +signal rld_seq_d : std_logic_vector(0 to 4); +signal rld_seq_q : std_logic_vector(0 to 4); +signal rld_dseq_d : std_logic_vector(0 to 3); +signal rld_dseq_q : std_logic_vector(0 to 3); + +signal req_pwr_d: std_logic; +signal req_pwr_q: std_logic; +signal store_pwr_d: std_logic; +signal store_pwr_q: std_logic; + +signal load_queue_d: LOADQUEUE; +signal load_queue_q: LOADQUEUE; +signal ldq_head_d: std_logic_vector(0 to clog2(ld_queue_size)-1); +signal ldq_head_q: std_logic_vector(0 to clog2(ld_queue_size)-1); +signal ldq_send_d: std_logic_vector(0 to clog2(ld_queue_size)-1); +signal ldq_send_q: std_logic_vector(0 to clog2(ld_queue_size)-1); +signal ldq_data_d: std_logic_vector(0 to clog2(ld_queue_size)-1); +signal ldq_data_q: std_logic_vector(0 to clog2(ld_queue_size)-1); +signal ldq_tail_d: std_logic_vector(0 to clog2(ld_queue_size)-1); +signal ldq_tail_q: std_logic_vector(0 to clog2(ld_queue_size)-1); +signal ldq_count_d: std_logic_vector(0 to clog2(ld_queue_size)); +signal ldq_count_q: std_logic_vector(0 to clog2(ld_queue_size)); +signal load_dep_d: LOADQUEUEDEP; +signal load_dep_q: LOADQUEUEDEP; + +signal load_data_ready_d, load_data_ready_q : std_logic; +signal load_data_queue_d : LOADDATAQUEUE; +signal load_data_queue_q : LOADDATAQUEUE; +signal rdataq_head_d : std_logic_vector(0 to clog2(ld_queue_size*16)-1); +signal rdataq_head_q : std_logic_vector(0 to clog2(ld_queue_size*16)-1); +signal rdataq_tail_d : std_logic_vector(0 to clog2(ld_queue_size*16)-1); +signal rdataq_tail_q : std_logic_vector(0 to clog2(ld_queue_size*16)-1); + +signal store_queue_d : STOREQUEUE; +signal store_queue_q : STOREQUEUE; +signal store_data_queue_d : STOREDATAQUEUE; +signal store_data_queue_q : STOREDATAQUEUE; +signal store_rsp_ready_d, store_rsp_ready_q : std_logic; +signal stq_head_d: std_logic_vector(0 to clog2(st_queue_size)-1); +signal stq_head_q: std_logic_vector(0 to clog2(st_queue_size)-1); +signal stq_send_d: std_logic_vector(0 to clog2(st_queue_size)-1); +signal stq_send_q: std_logic_vector(0 to clog2(st_queue_size)-1); +signal stq_data_d: std_logic_vector(0 to clog2(st_queue_size)-1); +signal stq_data_q: std_logic_vector(0 to clog2(st_queue_size)-1); +signal stq_tail_d: std_logic_vector(0 to clog2(st_queue_size)-1); +signal stq_tail_q: std_logic_vector(0 to clog2(st_queue_size)-1); +signal stq_count_d: std_logic_vector(0 to clog2(st_queue_size)); +signal stq_count_q: std_logic_vector(0 to clog2(st_queue_size)); +signal st_data_xfer_d: std_logic_vector(0 to 2); +signal st_data_xfer_q: std_logic_vector(0 to 2); +signal store_pop_pending_d: std_logic_vector(0 to clog2(st_queue_size)-1); +signal store_pop_pending_q: std_logic_vector(0 to clog2(st_queue_size)-1); +signal store_dep_d: STOREQUEUEDEP; +signal store_dep_q: STOREQUEUEDEP; + +signal resv_d: RESVARRAY; +signal resv_q: RESVARRAY; + +signal req_p1_d: A2L2REQUEST; +signal req_p1_q: A2L2REQUEST; +signal ld_p1_entry_d: std_logic_vector(0 to clog2(ld_queue_size)); +signal ld_p1_entry_q: std_logic_vector(0 to clog2(ld_queue_size)); +signal st_p1_entry_d: std_logic_vector(0 to clog2(st_queue_size)); +signal st_p1_entry_q: std_logic_vector(0 to clog2(st_queue_size)); +signal status_d: A2L2STATUS; +signal status_q: A2L2STATUS; +signal err_d, err_q: std_logic_vector(0 to 3); + +signal axi_load_ready : std_logic; +signal axi_load_valid : std_logic; +signal axi_load_id : std_logic_vector(C_M00_AXI_ID_WIDTH-1 downto 0); +signal axi_load_ra : std_logic_vector(C_M00_AXI_ADDR_WIDTH-1 downto 0); +signal axi_load_ra_hi : std_logic_vector(C_M00_AXI_ADDR_WIDTH-1 downto 6); +signal axi_load_ra_lo : std_logic_vector(5 downto 0); +signal axi_load_len : std_logic_vector(6 downto 0); +signal axi_load_mod : std_logic_vector(11 downto 0); + +signal axi_load_data_ready : std_logic; +signal axi_load_data_valid : std_logic; +signal axi_load_data_id : std_logic_vector(C_M00_AXI_ID_WIDTH-1 downto 0); +signal axi_load_data_resp : std_logic_vector(1 downto 0); +signal axi_load_data_last : std_logic; +signal axi_load_data : std_logic_vector(C_M00_AXI_DATA_WIDTH-1 downto 0); + +signal axi_store_valid : std_logic; +signal axi_store_id : std_logic_vector(C_M00_AXI_ID_WIDTH-1 downto 0); +signal axi_store_ra : std_logic_vector(C_M00_AXI_ADDR_WIDTH-1 downto 0); +signal axi_store_len : std_logic_vector(6 downto 0); +signal axi_store_mod : std_logic_vector(11 downto 0); + +signal axi_store_data_ready : std_logic; +signal axi_store_data_valid : std_logic; +signal axi_store_data : std_logic_vector(C_M00_AXI_DATA_WIDTH-1 downto 0); +signal axi_store_data_be : std_logic_vector(C_M00_AXI_DATA_WIDTH/8-1 downto 0); + +signal axi_store_rsp_ready : std_logic; +signal axi_store_rsp_valid : std_logic; +signal axi_store_rsp_id : std_logic_vector(C_M00_AXI_ID_WIDTH-1 downto 0); +signal axi_store_rsp_resp : std_logic_vector(1 downto 0); +signal store_complete : std_logic; + +signal store_data_in : std_logic_vector(0 to 127); +signal store_be_in : std_logic_vector(0 to 15); + +signal req_in: A2L2REQUEST; +signal req_clr : A2L2REQUEST; +signal ld_req: A2L2REQUEST; +signal req_in_load : std_logic; +signal load_len : std_logic_vector(6 downto 0); +signal ldq_oflow : std_logic; +signal ldq_uflow : std_logic; +signal ldq_write_sel: std_logic_vector(0 to 2); +signal ldq_count_sel: std_logic_vector(0 to 1); +signal axi_load_taken : std_logic; +signal load_queue_clr : A2L2REQUEST; +signal load_queue_fb : LOADQUEUE; +signal load_complete : std_logic; +signal ldq_valid_rst : std_logic_vector(0 to ld_queue_size-1); +signal ldq_sent_set : std_logic_vector(0 to ld_queue_size-1); +signal ldq_data_set : std_logic_vector(0 to ld_queue_size-1); +signal ldq_data_rst : std_logic_vector(0 to ld_queue_size-1); +signal rdataq_write_sel : std_logic_vector(0 to 63); +signal rld_single : std_logic; +signal rld_ready : std_logic; +signal rld_data_ready : std_logic; +signal rld_tag : std_logic_vector(0 to 4); +signal rdataq_head_sel : std_logic_vector(0 to 1); +signal rld_complete : std_logic; +signal rld_crit_qw : std_logic_vector(0 to 1); +signal rld_data_0 : std_logic_vector(0 to 31); +signal rld_data_1 : std_logic_vector(0 to 31); +signal rld_data_2 : std_logic_vector(0 to 31); +signal rld_data_3 : std_logic_vector(0 to 31); +signal rld_data_4 : std_logic_vector(0 to 31); +signal rld_data_5 : std_logic_vector(0 to 31); +signal rld_data_6 : std_logic_vector(0 to 31); +signal rld_data_7 : std_logic_vector(0 to 31); +signal rld_data_8 : std_logic_vector(0 to 31); +signal rld_data_9 : std_logic_vector(0 to 31); +signal rld_data_10 : std_logic_vector(0 to 31); +signal rld_data_11 : std_logic_vector(0 to 31); +signal rld_data_12 : std_logic_vector(0 to 31); +signal rld_data_13 : std_logic_vector(0 to 31); +signal rld_data_14 : std_logic_vector(0 to 31); +signal rld_data_15 : std_logic_vector(0 to 31); +signal rld_data_qw0 : std_logic_vector(0 to 127); +signal rld_data_qw1 : std_logic_vector(0 to 127); +signal rld_data_qw2 : std_logic_vector(0 to 127); +signal rld_data_qw3 : std_logic_vector(0 to 127); +signal rld_seq_err : std_logic; +signal rld_dseq_err : std_logic; +signal rld_data_valid : std_logic; +signal start_rld_data : std_logic; +signal rld_data_qw : std_logic_vector(0 to 1); +signal st_req_send : A2L2REQUEST; +signal st_req_data : A2L2REQUEST; +signal req_in_store: std_logic; +signal store_queue_clr : A2L2REQUEST; +signal store_queue_fb : STOREQUEUE; +signal store_data_queue_clr : A2L2STOREDATA; +signal st_data : A2L2STOREDATA; +signal stq_count_sel: std_logic_vector(0 to 1); +signal axi_store_ready : std_logic; +signal store_taken : std_logic; +signal store_advance : std_logic; +signal axi_store_data_taken : std_logic; +signal axi_store_data_last : std_logic; +signal stq_valid_rst : std_logic_vector(0 to st_queue_size-1); +signal stq_sent_set : std_logic_vector(0 to st_queue_size-1); +signal stq_data_rst : std_logic_vector(0 to st_queue_size-1); +signal st_data_last_xfer : std_logic; +signal st_data_xfer_hold : std_logic; +signal st_data_xfer_inc : std_logic; +signal st_data_xfer_done : std_logic; +signal stq_oflow : std_logic; +signal stq_uflow : std_logic; +signal req_in_spec: std_logic; +signal req_p1_addr_hit_lhs : std_logic_vector(0 to st_queue_size-1); +signal req_p1_sync_lhs : std_logic_vector(0 to st_queue_size-1); +signal req_p1_any_lhs: std_logic_vector(0 to st_queue_size-1); +signal req_p1_addr_hit_shl: std_logic_vector(0 to ld_queue_size-1); +signal req_p1_sync_shl: std_logic_vector(0 to ld_queue_size-1); +signal req_p1_any_shl: std_logic_vector(0 to ld_queue_size-1); +signal ld_req_stall: std_logic; +signal st_req_stall: std_logic; +signal load_queue_set_dep : std_logic_vector(0 to ld_queue_size-1); +signal load_queue_rst_dep : std_logic_vector(0 to ld_queue_size-1); +signal store_queue_set_dep : std_logic_vector(0 to st_queue_size-1); +signal store_queue_rst_dep : std_logic_vector(0 to st_queue_size-1); +signal lhs_ordered : std_logic_vector(0 to st_queue_size-1); +signal lhs_ordered_youngest : std_logic_vector(0 to st_queue_size-1); +signal lhs_youngest : std_logic_vector(0 to st_queue_size-1); +signal lhs_entry : std_logic_vector(0 to 1+clog2(st_queue_size-1)-1); +signal shl_ordered : std_logic_vector(0 to ld_queue_size-1); +signal shl_ordered_youngest : std_logic_vector(0 to ld_queue_size-1); +signal shl_youngest : std_logic_vector(0 to ld_queue_size-1); +signal shl_entry : std_logic_vector(0 to 1+clog2(ld_queue_size-1)-1); +signal reload_clr : A2L2RELOAD; +signal resv_clr : A2L2RESV; +signal status_clr : A2L2STATUS; +signal req_ra_line : std_logic_vector(64-xu_real_data_add to 59); +signal larx_t : std_logic_vector(0 to 3); +signal stcx_t : std_logic_vector(0 to 3); +signal store_t : std_logic_vector(0 to 3); +signal stcx_store_t : std_logic_vector(0 to 3); +signal resv_ra_hit : std_logic_vector(0 to 3); +signal resv_set : std_logic_vector(0 to 3); +signal resv_rst : std_logic_vector(0 to 3); +signal store_spec_valid : std_logic; +signal lwsync_complete : std_logic; +signal hwsync_complete : std_logic; +signal store_spec_complete : std_logic; +signal hwsync_valid : std_logic; +signal lwsync_valid : std_logic; +signal store_pop_delayed : std_logic; +signal store_rsp_complete : std_logic; +signal store_pop_pending_sel : std_logic_vector(0 to 2); +signal ld_dep: std_logic_vector(0 to clog2(st_queue_size)); +signal st_dep: std_logic_vector(0 to clog2(ld_queue_size)); + +begin + +req_clr <= (valid => '0', sent => '0', data => '0', dseq => (others => '0'), endian => '0', tag => (others => '0'), len => (others => '0'), + ra => (others => '0'), thread => (others => '0'), ditc => '0', spec => '0', ttype => (others => '0'), user => (others => '0'), wimg => (others => '0'), hwsync => '0'); +load_queue_clr <= req_clr; +reload_clr <= (valid => '0', coming => '0', tag => (others => '0'), data => (others => '0'), qw => (others => '0'), crit => '0', dump => '0', ee => '0', ue => '0'); +store_queue_clr <= req_clr; +store_data_queue_clr <= (data => (others => '0'), be => (others => '0')); +status_clr <= (ld_pop => '0', st_pop => '0', st_pop_thrd => (others => '0'), gather => '0', res_valid => (others => '0'), stcx_complete => (others => '0'), + stcx_pass => (others => '0'), sync_ack => (others => '0')); +resv_clr <= (valid => '0', ra => (others => '0')); + +FF: process(clk) begin + +if rising_edge(clk) then + + if reset_n = '0' then + + req_pwr_q <= '0'; + req_p1_q <= req_clr; + ld_p1_entry_q <= (others => '0'); + st_p1_entry_q <= (others => '0'); + rld_seq_q <= (others => '1'); + rld_dseq_q <= (others => '1'); + ldq_count_q <= (others => '0'); + ldq_head_q <= (others => '0'); + ldq_send_q <= (others => '0'); + ldq_data_q <= (others => '0'); + ldq_tail_q <= (others => '0'); + for i in 0 to 63 loop + load_data_queue_q(i) <= (others => '0'); + end loop; + rdataq_head_q <= (others => '0'); + rdataq_tail_q <= (others => '0'); + reload_q <= reload_clr; + store_pwr_q <= '0'; + for i in 0 to 3 loop + load_queue_q(i) <= load_queue_clr; + load_dep_q(i) <= (others => '0'); + end loop; + for i in 0 to st_queue_size-1 loop + store_queue_q(i) <= store_queue_clr; + store_data_queue_q(i) <= store_data_queue_clr; + store_dep_q(i) <= (others => '0'); + end loop; + stq_count_q <= (others => '0'); + stq_head_q <= (others => '0'); + stq_send_q <= (others => '0'); + stq_data_q <= (others => '0'); + stq_tail_q <= (others => '0'); + st_data_xfer_q <= (others => '0'); + store_pop_pending_q <= (others => '0'); + status_q <= status_clr; + for i in 0 to 3 loop + resv_q(i) <= resv_clr; + end loop; + load_data_ready_q <= '0'; + store_rsp_ready_q <= '0'; + err_q <= (others => '0'); + + else + + req_pwr_q <= req_pwr_d; + req_p1_q <= req_p1_d; + ld_p1_entry_q <= ld_p1_entry_d; + st_p1_entry_q <= st_p1_entry_d; + rld_seq_q <= rld_seq_d; + rld_dseq_q <= rld_dseq_d; + ldq_count_q <= ldq_count_d; + ldq_head_q <= ldq_head_d; + ldq_send_q <= ldq_send_d; + ldq_data_q <= ldq_data_d; + ldq_tail_q <= ldq_tail_d; + for i in 0 to 63 loop + load_data_queue_q(i) <= load_data_queue_d(i); + end loop; + rdataq_head_q <= rdataq_head_d; + rdataq_tail_q <= rdataq_tail_d; + reload_q <= reload_d; + store_pwr_q <= store_pwr_d; + for i in 0 to 3 loop + load_queue_q(i) <= load_queue_d(i); + load_dep_q(i) <= load_dep_d(i); + end loop; + for i in 0 to st_queue_size-1 loop + store_queue_q(i) <= store_queue_d(i); + store_data_queue_q(i) <= store_data_queue_d(i); + store_dep_q(i) <= store_dep_d(i); + end loop; + stq_count_q <= stq_count_d; + stq_head_q <= stq_head_d; + stq_send_q <= stq_send_d; + stq_data_q <= stq_data_d; + stq_tail_q <= stq_tail_d; + st_data_xfer_q <= st_data_xfer_d; + store_pop_pending_q <= store_pop_pending_d; + status_q <= status_d; + for i in 0 to 3 loop + resv_q(i) <= resv_d(i); + end loop; + load_data_ready_q <= load_data_ready_d; + store_rsp_ready_q <= store_rsp_ready_d; + err_q <= err_d; + + end if; + +end if; + +end process FF; + + + + + +req_pwr_d <= ac_an_req_pwr_token; + +req_in.valid <= ac_an_req and req_pwr_q; +req_in.sent <= '0'; +req_in.data <= '0'; +req_in.endian <= ac_an_req_endian; +req_in.tag <= ac_an_req_ld_core_tag; +req_in.len <= ac_an_req_ld_xfr_len; +req_in.ra <= ac_an_req_ra; +req_in.thread <= ac_an_req_thread(0 to 1); +req_in.ditc <= ac_an_req_thread(2); +req_in.spec <= req_in_spec; +req_in.ttype <= ac_an_req_ttype; +req_in.user <= ac_an_req_user_defined; +req_in.wimg <= ac_an_req_wimg_w & ac_an_req_wimg_i & ac_an_req_wimg_m & ac_an_req_wimg_g; +req_in.hwsync <= req_in.spec; + + + +with req_in_load select + ldq_tail_d <= inc(ldq_tail_q) when '1', + ldq_tail_q when others; + +ldq_write_sel <= req_in_load & ldq_tail_q; + +gen_load_queue_fb: for i in 0 to 3 generate + + load_queue_fb(i).valid <= load_queue_q(i).valid and not ldq_valid_rst(i); + load_queue_fb(i).sent <= (load_queue_q(i).sent or ldq_sent_set(i)) and not ldq_valid_rst(i); + load_queue_fb(i).data <= (load_queue_q(i).data or ldq_data_set(i)) and not ldq_data_rst(i); + load_queue_fb(i).dseq <= "000"; + load_queue_fb(i).endian <= load_queue_q(i).endian; + load_queue_fb(i).tag <= load_queue_q(i).tag; + load_queue_fb(i).len <= load_queue_q(i).len; + load_queue_fb(i).ra <= load_queue_q(i).ra; + load_queue_fb(i).thread <= load_queue_q(i).thread; + load_queue_fb(i).ditc <= load_queue_q(i).ditc; + load_queue_fb(i).spec <= load_queue_q(i).spec; + load_queue_fb(i).ttype <= load_queue_q(i).ttype; + load_queue_fb(i).user <= load_queue_q(i).user; + load_queue_fb(i).wimg <= load_queue_q(i).wimg; + load_queue_fb(i).hwsync <= load_queue_q(i).hwsync; + + load_dep_d(i) <= gate_and(load_queue_set_dep(i), lhs_entry) or + gate_and(not load_queue_set_dep(i) and not load_queue_rst_dep(i), load_dep_q(i)); + + +end generate; + +with ldq_write_sel select + load_queue_d(0) <= req_in when "100", + load_queue_fb(0) when others; +with ldq_write_sel select + load_queue_d(1) <= req_in when "101", + load_queue_fb(1) when others; +with ldq_write_sel select + load_queue_d(2) <= req_in when "110", + load_queue_fb(2) when others; +with ldq_write_sel select + load_queue_d(3) <= req_in when "111", + load_queue_fb(3) when others; + +axi_load_id <= "0000"; + +with ldq_send_q select + ld_req <= load_queue_q(0) when "00", + load_queue_q(1) when "01", + load_queue_q(2) when "10", + load_queue_q(3) when others; + +with ldq_send_q select + ld_dep <= load_dep_q(0) when "00", + load_dep_q(1) when "01", + load_dep_q(2) when "10", + load_dep_q(3) when others; + +axi_load_valid <= ld_req.valid and not ld_req.sent and not ld_req_stall; + +axi_load_ra_hi <= ld_req.ra(64-C_M00_AXI_ADDR_WIDTH to 57); +with ld_req.wimg(1) select + axi_load_ra_lo <= "000000" when '0', + ld_req.ra(58 to 63) when others; +axi_load_ra <= axi_load_ra_hi & axi_load_ra_lo; + +axi_load_mod <= "000000000000"; + +with ld_req.len select + load_len <= "0000001" when "001", + "0000010" when "010", + "0000100" when "100", + "0001000" when "101", + "0010000" when "110", + "0100000" when others; + +with ld_req.wimg(1) select + axi_load_len <= load_len when '1', + "1000000" when others; + +axi_load_taken <= axi_load_valid and axi_load_ready; + +ldq_sent_set(0) <= axi_load_taken and eq(ldq_send_q, "00"); +ldq_sent_set(1) <= axi_load_taken and eq(ldq_send_q, "01"); +ldq_sent_set(2) <= axi_load_taken and eq(ldq_send_q, "10"); +ldq_sent_set(3) <= axi_load_taken and eq(ldq_send_q, "11"); + +with axi_load_taken select + ldq_send_d <= inc(ldq_send_q) when '1', + ldq_send_q when others; + +ldq_data_set(0) <= axi_load_data_last and eq(ldq_data_q, "00"); +ldq_data_set(1) <= axi_load_data_last and eq(ldq_data_q, "01"); +ldq_data_set(2) <= axi_load_data_last and eq(ldq_data_q, "10"); +ldq_data_set(3) <= axi_load_data_last and eq(ldq_data_q, "11"); + +with axi_load_data_last select + ldq_data_d <= inc(ldq_data_q) when '1', + ldq_data_q when others; + +with load_complete select + ldq_head_d <= inc(ldq_head_q) when '1', + ldq_head_q when others; + +ldq_count_sel <= req_in_load & load_complete; +with ldq_count_sel select + ldq_count_d <= inc(ldq_count_q) when "10", + dec(ldq_count_q) when "01", + ldq_count_q when others; + +ldq_oflow <= eq(ldq_count_q, "100") and eq(ldq_count_sel, "10"); +ldq_uflow <= eq(ldq_count_q, "000") and eq(ldq_count_sel, "01"); + + +load_data_ready_d <= '1'; +axi_load_data_ready <= load_data_ready_q; + +with axi_load_data_valid select + rdataq_tail_d <= inc(rdataq_tail_q) when '1', + rdataq_tail_q when others; + + + +gen_load_load_data_queue: for i in 0 to 63 generate + rdataq_write_sel(i) <= axi_load_data_valid and eq(rdataq_tail_q, i); + with rdataq_write_sel(i) select + load_data_queue_d(i) <= axi_load_data(7 downto 0) & axi_load_data(15 downto 8) & axi_load_data(23 downto 16) & axi_load_data(31 downto 24) when '1', + load_data_queue_q(i) when others; +end generate; + + +with ldq_head_q select + rld_data_valid <= load_queue_q(0).valid and load_queue_q(0).data when "00", + load_queue_q(1).valid and load_queue_q(1).data when "01", + load_queue_q(2).valid and load_queue_q(2).data when "10", + load_queue_q(3).valid and load_queue_q(3).data when others; + +with ldq_head_q select + rld_tag <= load_queue_q(0).tag when "00", + load_queue_q(1).tag when "01", + load_queue_q(2).tag when "10", + load_queue_q(3).tag when others; + +with ldq_head_q select + rld_single <= load_queue_q(0).wimg(1) when "00", + load_queue_q(1).wimg(1) when "01", + load_queue_q(2).wimg(1) when "10", + load_queue_q(3).wimg(1) when others; + +with ldq_head_q select + rld_crit_qw <= load_queue_q(0).ra(58 to 59) when "00", + load_queue_q(1).ra(58 to 59) when "01", + load_queue_q(2).ra(58 to 59) when "10", + load_queue_q(3).ra(58 to 59) when others; + +reload_d.tag <= rld_tag; +reload_d.ue <= '0'; +reload_d.ee <= '0'; +reload_d.dump <= '0'; + +rld_ready <= axi_load_data_last or rld_data_valid; + +ldq_data_rst(0) <= start_rld_data and eq(ldq_head_q, "00"); +ldq_data_rst(1) <= start_rld_data and eq(ldq_head_q, "01"); +ldq_data_rst(2) <= start_rld_data and eq(ldq_head_q, "10"); +ldq_data_rst(3) <= start_rld_data and eq(ldq_head_q, "11"); + + + + +load_complete <= rld_complete; + +ldq_valid_rst(0) <= rld_complete and eq(ldq_head_q, "00"); +ldq_valid_rst(1) <= rld_complete and eq(ldq_head_q, "01"); +ldq_valid_rst(2) <= rld_complete and eq(ldq_head_q, "10"); +ldq_valid_rst(3) <= rld_complete and eq(ldq_head_q, "11"); + +status_d.ld_pop <= rld_complete; + +an_ac_reld_data_coming <= reload_q.coming; +an_ac_reld_data_vld <= reload_q.valid; +an_ac_reld_core_tag <= reload_q.tag; +an_ac_reld_qw <= reload_q.qw; +an_ac_reld_crit_qw <= reload_q.crit; +an_ac_reld_ecc_err <= reload_q.ee; +an_ac_reld_ecc_err_ue <= reload_q.ue; +an_ac_reld_l1_dump <= reload_q.dump; +an_ac_reld_data <= reload_q.data; + +an_ac_req_ld_pop <= status_q.ld_pop; +an_ac_req_st_pop <= status_q.st_pop; +an_ac_req_st_pop_thrd <= status_q.st_pop_thrd; +an_ac_req_st_gather <= status_q.gather; +an_ac_reservation_vld <= status_q.res_valid; +an_ac_stcx_complete <= status_q.stcx_complete; +an_ac_stcx_pass <= status_q.stcx_pass; +an_ac_sync_ack <= status_q.sync_ack; + +rdataq_head_sel <= rld_complete & rld_single; +with rdataq_head_sel select + rdataq_head_d <= inc(rdataq_head_q, 4) when "11", + inc(rdataq_head_q, 16) when "10", + rdataq_head_q when others; + +rld_data_0 <= mux_queue(load_data_queue_q, rdataq_head_q); +rld_data_1 <= mux_queue(load_data_queue_q, inc(rdataq_head_q, 1)); +rld_data_2 <= mux_queue(load_data_queue_q, inc(rdataq_head_q, 2)); +rld_data_3 <= mux_queue(load_data_queue_q, inc(rdataq_head_q, 3)); +rld_data_4 <= mux_queue(load_data_queue_q, inc(rdataq_head_q, 4)); +rld_data_5 <= mux_queue(load_data_queue_q, inc(rdataq_head_q, 5)); +rld_data_6 <= mux_queue(load_data_queue_q, inc(rdataq_head_q, 6)); +rld_data_7 <= mux_queue(load_data_queue_q, inc(rdataq_head_q, 7)); +rld_data_8 <= mux_queue(load_data_queue_q, inc(rdataq_head_q, 8)); +rld_data_9 <= mux_queue(load_data_queue_q, inc(rdataq_head_q, 9)); +rld_data_10 <= mux_queue(load_data_queue_q, inc(rdataq_head_q, 10)); +rld_data_11 <= mux_queue(load_data_queue_q, inc(rdataq_head_q, 11)); +rld_data_12 <= mux_queue(load_data_queue_q, inc(rdataq_head_q, 12)); +rld_data_13 <= mux_queue(load_data_queue_q, inc(rdataq_head_q, 13)); +rld_data_14 <= mux_queue(load_data_queue_q, inc(rdataq_head_q, 14)); +rld_data_15 <= mux_queue(load_data_queue_q, inc(rdataq_head_q, 15)); + +rld_data_qw0 <= rld_data_0 & rld_data_1 & rld_data_2 & rld_data_3; +rld_data_qw1 <= rld_data_4 & rld_data_5 & rld_data_6 & rld_data_7; +rld_data_qw2 <= rld_data_8 & rld_data_9 & rld_data_10 & rld_data_11; +rld_data_qw3 <= rld_data_12 & rld_data_13 & rld_data_14 & rld_data_15; + +with rld_data_qw select + reload_d.data <= rld_data_qw0 when "00", + rld_data_qw1 when "01", + rld_data_qw2 when "10", + rld_data_qw3 when others; + + +store_pwr_d <= ac_an_st_data_pwr_token; + +with req_in_store select + stq_tail_d <= inc(stq_tail_q) when '1', + stq_tail_q when others; + +gen_store_queue_fb: for i in 0 to st_queue_size-1 generate + + store_queue_fb(i).valid <= store_queue_q(i).valid and not stq_valid_rst(i); + store_queue_fb(i).sent <= store_queue_q(i).sent or stq_sent_set(i); + store_queue_fb(i).data <= (store_queue_q(i).data or stq_sent_set(i)) and not stq_data_rst(i); + store_queue_fb(i).dseq <= "000"; + store_queue_fb(i).endian <= store_queue_q(i).endian; + store_queue_fb(i).tag <= store_queue_q(i).tag; + store_queue_fb(i).len <= store_queue_q(i).len; + store_queue_fb(i).ra <= store_queue_q(i).ra; + store_queue_fb(i).thread <= store_queue_q(i).thread; + store_queue_fb(i).ditc <= store_queue_q(i).ditc; + store_queue_fb(i).spec <= store_queue_q(i).spec; + store_queue_fb(i).ttype <= store_queue_q(i).ttype; + store_queue_fb(i).user <= store_queue_q(i).user; + store_queue_fb(i).wimg <= store_queue_q(i).wimg; + store_queue_fb(i).hwsync <= store_queue_q(i).hwsync; + + store_dep_d(i) <= gate_and(store_queue_set_dep(i), shl_entry) or + gate_and(not store_queue_set_dep(i) and not store_queue_rst_dep(i), store_dep_q(i)); + +end generate; + +gen_store_queue: for i in 0 to st_queue_size-1 generate + + store_queue_d(i) <= req_in when b(req_in_store and eq(stq_tail_q, i)) else store_queue_fb(i); + +end generate; + +axi_store_id <= "0000"; + +st_req_send <= mux_queue(store_queue_q, stq_send_q); +st_dep <= mux_queue(store_dep_q, stq_send_q); + +axi_store_valid <= st_req_send.valid and not st_req_send.spec and not st_req_send.sent; +axi_store_mod <= "000000000000"; + +axi_store_ra <= st_req_send.ra(64-C_M00_AXI_ADDR_WIDTH to 59) & "0000"; + + +gen_store_len_16B: if st_data_32b_mode = 0 generate + store_data_in <= ac_an_st_data; + store_be_in <= ac_an_st_byte_enbl; +end generate; +gen_store_len_32B: if st_data_32b_mode = 1 generate + with req_in.ra(59) select + store_data_in <= ac_an_st_data(128 to 255) when '1', + ac_an_st_data(0 to 127) when others; + with req_in.ra(59) select + store_be_in <= ac_an_st_byte_enbl(16 to 31) when '1', + ac_an_st_byte_enbl(0 to 15) when others; +end generate; + + +store_spec_valid <= st_req_send.valid and st_req_send.spec; + +hwsync_valid <= store_spec_valid and st_req_send.hwsync; + +lwsync_valid <= store_spec_valid and + (eq(st_req_send.ttype, LWSYNC) or + eq(st_req_send.ttype, MBAR) or + eq(st_req_send.ttype, TLBSYNC) or + eq(st_req_send.ttype, DCBI)); + +store_taken <= ((axi_store_valid and axi_store_ready) or store_spec_valid) and not st_req_stall; + +gen_stq_sent: for i in 0 to st_queue_size-1 generate + stq_sent_set(i) <= store_taken and eq(stq_send_q, i); +end generate; + +store_advance <= (store_taken and not hwsync_valid) or hwsync_complete; + +with store_advance select + stq_send_d <= inc(stq_send_q) when '1', + stq_send_q when others; + + +gen_store_data_queue: for i in 0 to st_queue_size-1 generate + store_data_queue_d(i) <= (data => store_data_in, be => store_be_in) when b(req_in_store and eq(stq_tail_q, i)) else store_data_queue_q(i); +end generate; + +st_req_data <= mux_queue(store_queue_q, stq_data_q); +st_data <= mux_queue(store_data_queue_q, stq_data_q); + +axi_store_data_valid <= st_req_data.valid and st_req_data.data and not st_req_data.spec; + +axi_store_data_taken <= axi_store_data_valid and axi_store_data_ready; + +st_data_xfer_inc <= axi_store_data_taken and not st_data_last_xfer; +st_data_xfer_done <= axi_store_data_taken and st_data_last_xfer; +st_data_xfer_hold <= not st_data_xfer_inc and not st_data_xfer_done; + +st_data_xfer_d <= gate_and(st_data_xfer_inc, inc(st_data_xfer_q)) or + gate_and(st_data_xfer_done, "000") or + gate_and(st_data_xfer_hold, st_data_xfer_q); + + +gen_store_data_16B: if not stores_32B generate + +axi_store_len <= "0010000"; +st_data_last_xfer <= eq(st_data_xfer_q, "011"); + +with st_data_xfer_q select + axi_store_data <= st_data.data(24 to 31) & st_data.data(16 to 23) & st_data.data(8 to 15) & st_data.data(0 to 7) when "000", + st_data.data(56 to 63) & st_data.data(48 to 55) & st_data.data(40 to 47) & st_data.data(32 to 39) when "001", + st_data.data(88 to 95) & st_data.data(80 to 87) & st_data.data(72 to 79) & st_data.data(64 to 71) when "010", + st_data.data(120 to 127) & st_data.data(112 to 119) & st_data.data(104 to 111) & st_data.data(96 to 103) when others; + +with st_data_xfer_q select + axi_store_data_be <= st_data.be( 3) & st_data.be( 2) & st_data.be( 1) & st_data.be( 0) when "000", + st_data.be( 7) & st_data.be( 6) & st_data.be( 5) & st_data.be( 4) when "001", + st_data.be(11) & st_data.be(10) & st_data.be( 9) & st_data.be( 8) when "010", + st_data.be(15) & st_data.be(14) & st_data.be(13) & st_data.be(12) when others; +end generate; + +gen_store_data_32B: if stores_32B generate + +axi_store_len <= "0100000"; +st_data_last_xfer <= eq(st_data_xfer_q, "111"); + +with st_data_xfer_q select + axi_store_data <= st_data.data(24 to 31) & st_data.data(16 to 23) & st_data.data(8 to 15) & st_data.data(0 to 7) when "000", + st_data.data(56 to 63) & st_data.data(48 to 55) & st_data.data(40 to 47) & st_data.data(32 to 39) when "001", + st_data.data(87 to 95) & st_data.data(80 to 87) & st_data.data(72 to 79) & st_data.data(64 to 71) when "010", + st_data.data(120 to 127) & st_data.data(112 to 119) & st_data.data(104 to 111) & st_data.data(96 to 103) when "011", + st_data.data(152 to 159) & st_data.data(144 to 151) & st_data.data(136 to 143) & st_data.data(128 to 135) when "100", + st_data.data(184 to 191) & st_data.data(176 to 183) & st_data.data(168 to 175) & st_data.data(160 to 167) when "101", + st_data.data(216 to 223) & st_data.data(208 to 215) & st_data.data(200 to 207) & st_data.data(192 to 199) when "110", + st_data.data(248 to 255) & st_data.data(240 to 247) & st_data.data(232 to 239) & st_data.data(224 to 231) when others; + +with st_data_xfer_q select + axi_store_data_be <= st_data.be( 3) & st_data.be( 2) & st_data.be( 1) & st_data.be( 0) when "000", + st_data.be( 7) & st_data.be( 6) & st_data.be( 5) & st_data.be( 4) when "001", + st_data.be(11) & st_data.be(10) & st_data.be( 9) & st_data.be( 8) when "010", + st_data.be(15) & st_data.be(14) & st_data.be(13) & st_data.be(12) when "011", + st_data.be(19) & st_data.be(18) & st_data.be(17) & st_data.be(16) when "100", + st_data.be(23) & st_data.be(22) & st_data.be(21) & st_data.be(20) when "101", + st_data.be(27) & st_data.be(26) & st_data.be(25) & st_data.be(24) when "110", + st_data.be(31) & st_data.be(30) & st_data.be(29) & st_data.be(28) when others; +end generate; + +axi_store_data_last <= st_data_last_xfer; + + +with st_data_xfer_done or store_spec_complete select + stq_data_d <= inc(stq_data_q) when '1', + stq_data_q when others; + +gen_store_data_rst: for i in 0 to st_queue_size-1 generate + stq_data_rst(i) <= st_data_xfer_done and eq(stq_data_q, i); +end generate; + + +store_rsp_ready_d <= '1'; +axi_store_rsp_ready <= store_rsp_ready_q; + +lwsync_complete <= st_req_data.valid and st_req_data.data and st_req_data.spec and not st_req_data.hwsync; +hwsync_complete <= st_req_data.valid and st_req_data.data and st_req_data.spec and st_req_data.hwsync and not st_req_stall; +store_spec_complete <= lwsync_complete or hwsync_complete; + +store_rsp_complete <= (axi_store_rsp_valid and eq(axi_store_rsp_resp, "00")); +store_complete <= store_rsp_complete or store_spec_complete; + +store_pop_delayed <= or_reduce(store_pop_pending_q); +store_pop_pending_sel <= store_rsp_complete & store_spec_complete & store_pop_delayed; +with store_pop_pending_sel select + store_pop_pending_d <= dec(store_pop_pending_q) when "001", + inc(store_pop_pending_q) when "110", + inc(store_pop_pending_q) when "111", + store_pop_pending_q when others; + +status_d.st_pop <= store_complete or store_pop_delayed; +status_d.st_pop_thrd <= "000"; +status_d.gather <= '0'; + +with store_complete select + stq_head_d <= inc(stq_head_q) when '1', + stq_head_q when others; + +stq_count_sel <= req_in_store & store_complete; +with stq_count_sel select + stq_count_d <= inc(stq_count_q) when "10", + dec(stq_count_q) when "01", + stq_count_q when others; + +gen_stq_valid_rst: for i in 0 to st_queue_size-1 generate + stq_valid_rst(i) <= store_complete and eq(stq_head_q, i); +end generate; + +stq_oflow <= eq(stq_count_q, st_queue_size) and req_in_store; +stq_uflow <= eq(stq_count_q, 0) and store_complete; + + + + + +stcx_store_t(0) <= stcx_t(0) or store_t(0); +stcx_store_t(1) <= stcx_t(1) or store_t(1); +stcx_store_t(2) <= stcx_t(2) or store_t(2); +stcx_store_t(3) <= stcx_t(3) or store_t(3); + +req_ra_line <= req_in.ra(64-xu_real_data_add to 59); +resv_ra_hit(0) <= eq(req_ra_line, resv_q(0).ra); +resv_ra_hit(1) <= eq(req_ra_line, resv_q(1).ra); +resv_ra_hit(2) <= eq(req_ra_line, resv_q(2).ra); +resv_ra_hit(3) <= eq(req_ra_line, resv_q(3).ra); + +resv_set(0) <= larx_t(0); +resv_set(1) <= larx_t(1); +resv_set(2) <= larx_t(2); +resv_set(3) <= larx_t(3); + +resv_rst(0) <= resv_ra_hit(0) and (stcx_store_t(0) or stcx_store_t(1) or stcx_store_t(2) or stcx_store_t(3)); +resv_rst(1) <= resv_ra_hit(1) and (stcx_store_t(0) or stcx_store_t(1) or stcx_store_t(2) or stcx_store_t(3)); +resv_rst(2) <= resv_ra_hit(2) and (stcx_store_t(0) or stcx_store_t(1) or stcx_store_t(2) or stcx_store_t(3)); +resv_rst(3) <= resv_ra_hit(3) and (stcx_store_t(0) or stcx_store_t(1) or stcx_store_t(2) or stcx_store_t(3)); + +resv_d(0).valid <= (resv_q(0).valid or resv_set(0)) and not resv_rst(0); +resv_d(1).valid <= (resv_q(1).valid or resv_set(1)) and not resv_rst(1); +resv_d(2).valid <= (resv_q(2).valid or resv_set(2)) and not resv_rst(2); +resv_d(3).valid <= (resv_q(3).valid or resv_set(3)) and not resv_rst(3); + +with resv_set(0) select + resv_d(0).ra <= req_ra_line when '1', + resv_q(0).ra when others; + +with resv_set(1) select + resv_d(1).ra <= req_ra_line when '1', + resv_q(1).ra when others; + +with resv_set(2) select + resv_d(2).ra <= req_ra_line when '1', + resv_q(2).ra when others; + +with resv_set(3) select + resv_d(3).ra <= req_ra_line when '1', + resv_q(3).ra when others; + +status_d.res_valid(0) <= resv_q(0).valid; +status_d.res_valid(1) <= resv_q(1).valid; +status_d.res_valid(2) <= resv_q(2).valid; +status_d.res_valid(3) <= resv_q(3).valid; + +status_d.stcx_complete(0) <= stcx_t(0); +status_d.stcx_complete(1) <= stcx_t(1); +status_d.stcx_complete(2) <= stcx_t(2); +status_d.stcx_complete(3) <= stcx_t(3); + +status_d.stcx_pass(0) <= stcx_t(0) and resv_q(0).valid and resv_ra_hit(0); +status_d.stcx_pass(1) <= stcx_t(1) and resv_q(1).valid and resv_ra_hit(1); +status_d.stcx_pass(2) <= stcx_t(2) and resv_q(2).valid and resv_ra_hit(2); +status_d.stcx_pass(3) <= stcx_t(3) and resv_q(3).valid and resv_ra_hit(3); + + +status_d.sync_ack(0) <= hwsync_complete and eq(st_req_data.ttype, HWSYNC) and eq(st_req_data.thread, "00"); +status_d.sync_ack(1) <= hwsync_complete and eq(st_req_data.ttype, HWSYNC) and eq(st_req_data.thread, "01"); +status_d.sync_ack(2) <= hwsync_complete and eq(st_req_data.ttype, HWSYNC) and eq(st_req_data.thread, "10"); +status_d.sync_ack(3) <= hwsync_complete and eq(st_req_data.ttype, HWSYNC) and eq(st_req_data.thread, "11"); + + + +req_p1_d <= req_in; + +ld_p1_entry_d <= req_in_load & ldq_head_q; +st_p1_entry_d <= req_in_store & stq_head_q; + +gen_dep_addr_cmp_l: for i in 0 to st_queue_size-1 generate + +req_p1_addr_hit_lhs(i) <= ld_p1_entry_q(0) and + address_check(req_p1_q, store_queue_q(i)) and + (not stq_valid_rst(i)); + +req_p1_sync_lhs(i) <= ld_p1_entry_q(0) and + store_queue_q(i).valid and + store_queue_q(i).hwsync and + (not stq_valid_rst(i)); + +req_p1_any_lhs(i) <= req_p1_addr_hit_lhs(i) or req_p1_sync_lhs(i); + +end generate; + +lhs_ordered <= rotl(req_p1_any_lhs, ldq_head_q); + +lhs_ordered_youngest <= right_one(lhs_ordered); + +lhs_youngest <= rotr(lhs_ordered_youngest, ldq_head_q); + +lhs_entry <= gate_and(or_reduce(lhs_youngest), '1' & enc(lhs_youngest)); + +gen_dep_addr_cmp_s: for i in 0 to ld_queue_size-1 generate + +req_p1_addr_hit_shl(i) <= st_p1_entry_q(0) and + not req_p1_q.spec and + address_check(req_p1_q, load_queue_q(i)) and + (not ldq_valid_rst(i)); + +req_p1_sync_shl(i) <= st_p1_entry_q(0) and + load_queue_q(i).valid and + req_p1_q.hwsync and + (not ldq_valid_rst(i)); + +req_p1_any_shl(i) <= req_p1_addr_hit_shl(i) or req_p1_sync_shl(i); + +end generate; + +shl_ordered <= rotl(req_p1_any_shl, stq_head_q); + +shl_ordered_youngest <= right_one(shl_ordered); + +shl_youngest <= rotr(shl_ordered_youngest, stq_head_q); + +shl_entry <= gate_and(or_reduce(shl_youngest), '1' & enc(shl_youngest)); + + +ld_req_stall <= lhs_entry(0) or ld_dep(0); +st_req_stall <= shl_entry(0) or st_dep(0) or + (st_req_data.hwsync and not eq(stq_send_q, stq_head_q)); + +gen_ldq_set_dep: for i in 0 to ld_queue_size-1 generate +load_queue_set_dep(i) <= ld_p1_entry_q(0) and eq(ld_p1_entry_q(1 to clog2(ld_queue_size)), std_logic_vector(to_unsigned(i, 2))) and lhs_entry(0); +end generate; + +gen_stq_set_dep: for i in 0 to st_queue_size-1 generate +store_queue_set_dep(i) <= st_p1_entry_q(0) and eq(st_p1_entry_q(1 to clog2(st_queue_size)), std_logic_vector(to_unsigned(i, 2))) and shl_entry(0); +end generate; + +gen_ldq_rst_dep: for i in 0 to ld_queue_size-1 generate +load_queue_rst_dep(i) <= store_complete and load_dep_q(i)(0) and eq(load_dep_q(i)(1 to clog2(st_queue_size)), stq_head_q); +end generate; + +gen_stq_rst_dep: for i in 0 to st_queue_size-1 generate +store_queue_rst_dep(i) <= load_complete and store_dep_q(i)(0) and eq(store_dep_q(i)(1 to clog2(ld_queue_size)), ldq_head_q); +end generate; + + + +axi_load_ready <= m00_axi_arready; +m00_axi_arvalid <= axi_load_valid; +m00_axi_arid <= axi_load_id; +m00_axi_araddr <= axi_load_ra; + +with axi_load_len select + m00_axi_arlen <= x"00" when "0000001", + x"00" when "0000010", + x"00" when "0000100", + x"01" when "0001000", + x"03" when "0010000", + x"07" when "0100000", + x"0F" when "1000000", + x"00" when others; + +m00_axi_arsize <= "010"; +m00_axi_arburst <= "01"; + +m00_axi_arlock <= '0'; +m00_axi_arcache <= "0011"; +m00_axi_arprot <= "000"; +m00_axi_arqos <= x"0"; +m00_axi_aruser <= (others => '1'); + + +m00_axi_rready <= axi_load_data_ready; +axi_load_data_valid <= m00_axi_rvalid; +axi_load_data_id <= m00_axi_rid; +axi_load_data <= m00_axi_rdata; +axi_load_data_resp <= m00_axi_rresp; +axi_load_data_last <= m00_axi_rlast; + + +axi_store_ready <= m00_axi_awready; +m00_axi_awvalid <= axi_store_valid; +m00_axi_awid <= axi_store_id; +m00_axi_awaddr <= axi_store_ra; + +with axi_store_len select + m00_axi_awlen <= x"03" when "0010000", + x"07" when "0100000", + x"00" when others; + +m00_axi_awsize <= "010"; +m00_axi_awburst <= "01"; + +m00_axi_awlock <= '0'; +m00_axi_awcache <= "0010"; +m00_axi_awprot <= "000"; +m00_axi_awqos <= x"0"; +m00_axi_awuser <= (others => '1'); + + +axi_store_data_ready <= m00_axi_wready; +m00_axi_wvalid <= axi_store_data_valid; +m00_axi_wdata <= axi_store_data; +m00_axi_wstrb <= axi_store_data_be; +m00_axi_wlast <= axi_store_data_last; +m00_axi_wuser <= (others => '0'); + + +m00_axi_bready <= axi_store_rsp_ready; +axi_store_rsp_valid <= m00_axi_bvalid; +axi_store_rsp_id <= m00_axi_bid; +axi_store_rsp_resp <= m00_axi_bresp; + + +err_d(0) <= ldq_uflow; +err_d(1) <= ldq_oflow; +err_d(2) <= stq_uflow; +err_d(3) <= stq_oflow; + +err <= err_q; + + +req_in_load <= + (req_in.valid and not req_in.ttype(0) and not req_in.ttype(1) and not req_in.ttype(2) and not req_in.ttype(3) and not req_in.ttype(4) and not req_in.ttype(5)) or + (req_in.valid and not req_in.ttype(0) and not req_in.ttype(1) and not req_in.ttype(2) and not req_in.ttype(3) and not req_in.ttype(4) and req_in.ttype(5)) or + (req_in.valid and not req_in.ttype(0) and not req_in.ttype(1) and req_in.ttype(2) and not req_in.ttype(3) and not req_in.ttype(4) and not req_in.ttype(5)) or + (req_in.valid and not req_in.ttype(0) and not req_in.ttype(1) and req_in.ttype(2) and not req_in.ttype(3) and not req_in.ttype(4) and req_in.ttype(5) and not req_in.thread(0) and not req_in.thread(1)) or + (req_in.valid and not req_in.ttype(0) and not req_in.ttype(1) and req_in.ttype(2) and not req_in.ttype(3) and not req_in.ttype(4) and req_in.ttype(5) and not req_in.thread(0) and req_in.thread(1)) or + (req_in.valid and not req_in.ttype(0) and not req_in.ttype(1) and req_in.ttype(2) and not req_in.ttype(3) and not req_in.ttype(4) and req_in.ttype(5) and req_in.thread(0) and not req_in.thread(1)) or + (req_in.valid and not req_in.ttype(0) and not req_in.ttype(1) and req_in.ttype(2) and not req_in.ttype(3) and not req_in.ttype(4) and req_in.ttype(5) and req_in.thread(0) and req_in.thread(1)); +req_in_store <= + (req_in.valid and req_in.ttype(0) and not req_in.ttype(1) and not req_in.ttype(2) and not req_in.ttype(3) and not req_in.ttype(4) and not req_in.ttype(5) and not req_in.thread(0) and not req_in.thread(1)) or + (req_in.valid and req_in.ttype(0) and not req_in.ttype(1) and not req_in.ttype(2) and not req_in.ttype(3) and not req_in.ttype(4) and not req_in.ttype(5) and not req_in.thread(0) and req_in.thread(1)) or + (req_in.valid and req_in.ttype(0) and not req_in.ttype(1) and not req_in.ttype(2) and not req_in.ttype(3) and not req_in.ttype(4) and not req_in.ttype(5) and req_in.thread(0) and not req_in.thread(1)) or + (req_in.valid and req_in.ttype(0) and not req_in.ttype(1) and not req_in.ttype(2) and not req_in.ttype(3) and not req_in.ttype(4) and not req_in.ttype(5) and req_in.thread(0) and req_in.thread(1)) or + (req_in.valid and req_in.ttype(0) and not req_in.ttype(1) and req_in.ttype(2) and not req_in.ttype(3) and not req_in.ttype(4) and req_in.ttype(5) and not req_in.thread(0) and not req_in.thread(1)) or + (req_in.valid and req_in.ttype(0) and not req_in.ttype(1) and req_in.ttype(2) and not req_in.ttype(3) and not req_in.ttype(4) and req_in.ttype(5) and not req_in.thread(0) and req_in.thread(1)) or + (req_in.valid and req_in.ttype(0) and not req_in.ttype(1) and req_in.ttype(2) and not req_in.ttype(3) and not req_in.ttype(4) and req_in.ttype(5) and req_in.thread(0) and not req_in.thread(1)) or + (req_in.valid and req_in.ttype(0) and not req_in.ttype(1) and req_in.ttype(2) and not req_in.ttype(3) and not req_in.ttype(4) and req_in.ttype(5) and req_in.thread(0) and req_in.thread(1)) or + (req_in.valid and req_in.ttype(0) and not req_in.ttype(1) and req_in.ttype(2) and not req_in.ttype(3) and req_in.ttype(4) and not req_in.ttype(5)) or + (req_in.valid and req_in.ttype(0) and not req_in.ttype(1) and req_in.ttype(2) and not req_in.ttype(3) and req_in.ttype(4) and req_in.ttype(5)) or + (req_in.valid and req_in.ttype(0) and req_in.ttype(1) and req_in.ttype(2) and not req_in.ttype(3) and req_in.ttype(4) and not req_in.ttype(5)) or + (req_in.valid and req_in.ttype(0) and req_in.ttype(1) and req_in.ttype(2) and req_in.ttype(3) and req_in.ttype(4) and req_in.ttype(5)); +req_in_spec <= + (req_in.valid and req_in.ttype(0) and not req_in.ttype(1) and req_in.ttype(2) and not req_in.ttype(3) and req_in.ttype(4) and not req_in.ttype(5)) or + (req_in.valid and req_in.ttype(0) and not req_in.ttype(1) and req_in.ttype(2) and not req_in.ttype(3) and req_in.ttype(4) and req_in.ttype(5)) or + (req_in.valid and req_in.ttype(0) and req_in.ttype(1) and req_in.ttype(2) and not req_in.ttype(3) and req_in.ttype(4) and not req_in.ttype(5)) or + (req_in.valid and req_in.ttype(0) and req_in.ttype(1) and req_in.ttype(2) and req_in.ttype(3) and req_in.ttype(4) and req_in.ttype(5)); +larx_t(0) <= + (req_in.valid and not req_in.ttype(0) and not req_in.ttype(1) and req_in.ttype(2) and not req_in.ttype(3) and not req_in.ttype(4) and req_in.ttype(5) and not req_in.thread(0) and not req_in.thread(1)); +larx_t(1) <= + (req_in.valid and not req_in.ttype(0) and not req_in.ttype(1) and req_in.ttype(2) and not req_in.ttype(3) and not req_in.ttype(4) and req_in.ttype(5) and not req_in.thread(0) and req_in.thread(1)); +larx_t(2) <= + (req_in.valid and not req_in.ttype(0) and not req_in.ttype(1) and req_in.ttype(2) and not req_in.ttype(3) and not req_in.ttype(4) and req_in.ttype(5) and req_in.thread(0) and not req_in.thread(1)); +larx_t(3) <= + (req_in.valid and not req_in.ttype(0) and not req_in.ttype(1) and req_in.ttype(2) and not req_in.ttype(3) and not req_in.ttype(4) and req_in.ttype(5) and req_in.thread(0) and req_in.thread(1)); +stcx_t(0) <= + (req_in.valid and req_in.ttype(0) and not req_in.ttype(1) and req_in.ttype(2) and not req_in.ttype(3) and not req_in.ttype(4) and req_in.ttype(5) and not req_in.thread(0) and not req_in.thread(1)); +stcx_t(1) <= + (req_in.valid and req_in.ttype(0) and not req_in.ttype(1) and req_in.ttype(2) and not req_in.ttype(3) and not req_in.ttype(4) and req_in.ttype(5) and not req_in.thread(0) and req_in.thread(1)); +stcx_t(2) <= + (req_in.valid and req_in.ttype(0) and not req_in.ttype(1) and req_in.ttype(2) and not req_in.ttype(3) and not req_in.ttype(4) and req_in.ttype(5) and req_in.thread(0) and not req_in.thread(1)); +stcx_t(3) <= + (req_in.valid and req_in.ttype(0) and not req_in.ttype(1) and req_in.ttype(2) and not req_in.ttype(3) and not req_in.ttype(4) and req_in.ttype(5) and req_in.thread(0) and req_in.thread(1)); +store_t(0) <= + (req_in.valid and req_in.ttype(0) and not req_in.ttype(1) and not req_in.ttype(2) and not req_in.ttype(3) and not req_in.ttype(4) and not req_in.ttype(5) and not req_in.thread(0) and not req_in.thread(1)); +store_t(1) <= + (req_in.valid and req_in.ttype(0) and not req_in.ttype(1) and not req_in.ttype(2) and not req_in.ttype(3) and not req_in.ttype(4) and not req_in.ttype(5) and not req_in.thread(0) and req_in.thread(1)); +store_t(2) <= + (req_in.valid and req_in.ttype(0) and not req_in.ttype(1) and not req_in.ttype(2) and not req_in.ttype(3) and not req_in.ttype(4) and not req_in.ttype(5) and req_in.thread(0) and not req_in.thread(1)); +store_t(3) <= + (req_in.valid and req_in.ttype(0) and not req_in.ttype(1) and not req_in.ttype(2) and not req_in.ttype(3) and not req_in.ttype(4) and not req_in.ttype(5) and req_in.thread(0) and req_in.thread(1)); + +rld_seq_d(0) <= + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4) and not rld_ready) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4) and rld_ready and not rld_crit_qw(0) and not rld_crit_qw(1) and not rld_single) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4) and rld_ready and not rld_crit_qw(0) and rld_crit_qw(1) and not rld_single) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4) and rld_ready and rld_crit_qw(0) and not rld_crit_qw(1) and not rld_single) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4) and rld_ready and rld_crit_qw(0) and rld_crit_qw(1) and not rld_single) or + (not rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and not rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and not rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and not rld_seq_q(2) and not rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and not rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and not rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)); +rld_seq_d(1) <= + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4) and not rld_ready) or + (not rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and not rld_seq_q(2) and not rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and not rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and not rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)); +rld_seq_d(2) <= + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4) and not rld_ready) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4) and rld_ready and rld_crit_qw(0) and not rld_crit_qw(1) and not rld_single) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4) and rld_ready and rld_crit_qw(0) and rld_crit_qw(1) and not rld_single) or + (not rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and not rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and not rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4)) or + (not rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and not rld_seq_q(3) and not rld_seq_q(4)) or + (not rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)) or + (not rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)) or + (not rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and not rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)); +rld_seq_d(3) <= + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4) and not rld_ready) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4) and rld_ready and not rld_crit_qw(0) and rld_crit_qw(1) and not rld_single) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4) and rld_ready and rld_crit_qw(0) and rld_crit_qw(1) and not rld_single) or + (not rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)) or + (not rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)) or + (not rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and not rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4)) or + (not rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)) or + (not rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)); +rld_seq_d(4) <= + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4) and not rld_ready) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4) and rld_ready and rld_single) or + (not rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)) or + (not rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and not rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and not rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and not rld_seq_q(2) and not rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and not rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4)) or + (not rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)) or + (not rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)); +reload_d.coming <= + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4) and rld_ready and not rld_crit_qw(0) and not rld_crit_qw(1) and not rld_single) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4) and rld_ready and not rld_crit_qw(0) and rld_crit_qw(1) and not rld_single) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4) and rld_ready and rld_crit_qw(0) and not rld_crit_qw(1) and not rld_single) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4) and rld_ready and rld_crit_qw(0) and rld_crit_qw(1) and not rld_single) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4) and rld_ready and rld_single) or + (rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4)); +reload_d.valid <= + (not rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and not rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and not rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and not rld_seq_q(2) and not rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and not rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4)); +reload_d.qw(58) <= + (rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and not rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4)); +reload_d.qw(59) <= + (rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and not rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4)); +reload_d.crit <= + (rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and not rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and not rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)); +start_rld_data <= + (not rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and not rld_seq_q(2) and not rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)); +rld_seq_err <= + (not rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and not rld_seq_q(3) and not rld_seq_q(4)) or + (not rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and not rld_seq_q(3) and not rld_seq_q(4)) or + (not rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)) or + (not rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)) or + (not rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and not rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)); + +rld_dseq_d(0) <= + (rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and rld_dseq_q(3) and not start_rld_data) or + (rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and rld_dseq_q(3) and start_rld_data and rld_single) or + (not rld_dseq_q(0) and not rld_dseq_q(1) and not rld_dseq_q(2) and rld_dseq_q(3)) or + (not rld_dseq_q(0) and not rld_dseq_q(1) and rld_dseq_q(2) and not rld_dseq_q(3)) or + (not rld_dseq_q(0) and not rld_dseq_q(1) and rld_dseq_q(2) and rld_dseq_q(3)) or + (not rld_dseq_q(0) and rld_dseq_q(1) and not rld_dseq_q(2) and not rld_dseq_q(3)) or + (rld_dseq_q(0) and not rld_dseq_q(1) and not rld_dseq_q(2) and rld_dseq_q(3)) or + (rld_dseq_q(0) and not rld_dseq_q(1) and rld_dseq_q(2) and not rld_dseq_q(3)) or + (rld_dseq_q(0) and not rld_dseq_q(1) and rld_dseq_q(2) and rld_dseq_q(3)) or + (rld_dseq_q(0) and rld_dseq_q(1) and not rld_dseq_q(2) and not rld_dseq_q(3)) or + (rld_dseq_q(0) and not rld_dseq_q(1) and not rld_dseq_q(2) and not rld_dseq_q(3)) or + (rld_dseq_q(0) and rld_dseq_q(1) and not rld_dseq_q(2) and rld_dseq_q(3)) or + (rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and not rld_dseq_q(3)); +rld_dseq_d(1) <= + (rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and rld_dseq_q(3) and not start_rld_data) or + (rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and rld_dseq_q(3) and start_rld_data and rld_crit_qw(0) and rld_crit_qw(1) and not rld_single) or + (rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and rld_dseq_q(3) and start_rld_data and rld_single) or + (rld_dseq_q(0) and not rld_dseq_q(1) and rld_dseq_q(2) and not rld_dseq_q(3)) or + (rld_dseq_q(0) and not rld_dseq_q(1) and rld_dseq_q(2) and rld_dseq_q(3)) or + (rld_dseq_q(0) and rld_dseq_q(1) and not rld_dseq_q(2) and not rld_dseq_q(3)) or + (not rld_dseq_q(0) and rld_dseq_q(1) and not rld_dseq_q(2) and rld_dseq_q(3)) or + (not rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and not rld_dseq_q(3)) or + (not rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and rld_dseq_q(3)) or + (rld_dseq_q(0) and rld_dseq_q(1) and not rld_dseq_q(2) and rld_dseq_q(3)) or + (rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and not rld_dseq_q(3)); +rld_dseq_d(2) <= + (rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and rld_dseq_q(3) and not start_rld_data) or + (rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and rld_dseq_q(3) and start_rld_data and not rld_crit_qw(0) and rld_crit_qw(1) and not rld_single) or + (rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and rld_dseq_q(3) and start_rld_data and rld_crit_qw(0) and not rld_crit_qw(1) and not rld_single) or + (rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and rld_dseq_q(3) and start_rld_data and rld_single) or + (not rld_dseq_q(0) and not rld_dseq_q(1) and not rld_dseq_q(2) and rld_dseq_q(3)) or + (not rld_dseq_q(0) and not rld_dseq_q(1) and rld_dseq_q(2) and not rld_dseq_q(3)) or + (rld_dseq_q(0) and not rld_dseq_q(1) and not rld_dseq_q(2) and rld_dseq_q(3)) or + (rld_dseq_q(0) and not rld_dseq_q(1) and rld_dseq_q(2) and not rld_dseq_q(3)) or + (rld_dseq_q(0) and rld_dseq_q(1) and not rld_dseq_q(2) and not rld_dseq_q(3)) or + (not rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and not rld_dseq_q(3)) or + (not rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and rld_dseq_q(3)) or + (rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and not rld_dseq_q(3)); +rld_dseq_d(3) <= + (rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and rld_dseq_q(3) and not start_rld_data) or + (rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and rld_dseq_q(3) and start_rld_data and not rld_crit_qw(0) and not rld_crit_qw(1) and not rld_single) or + (rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and rld_dseq_q(3) and start_rld_data and rld_crit_qw(0) and not rld_crit_qw(1) and not rld_single) or + (rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and rld_dseq_q(3) and start_rld_data and rld_single) or + (not rld_dseq_q(0) and not rld_dseq_q(1) and not rld_dseq_q(2) and rld_dseq_q(3)) or + (not rld_dseq_q(0) and not rld_dseq_q(1) and rld_dseq_q(2) and not rld_dseq_q(3)) or + (not rld_dseq_q(0) and not rld_dseq_q(1) and rld_dseq_q(2) and rld_dseq_q(3)) or + (not rld_dseq_q(0) and rld_dseq_q(1) and not rld_dseq_q(2) and not rld_dseq_q(3)) or + (rld_dseq_q(0) and not rld_dseq_q(1) and rld_dseq_q(2) and not rld_dseq_q(3)) or + (rld_dseq_q(0) and rld_dseq_q(1) and not rld_dseq_q(2) and not rld_dseq_q(3)) or + (not rld_dseq_q(0) and rld_dseq_q(1) and not rld_dseq_q(2) and rld_dseq_q(3)) or + (not rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and rld_dseq_q(3)) or + (rld_dseq_q(0) and rld_dseq_q(1) and not rld_dseq_q(2) and rld_dseq_q(3)); +rld_data_qw(0) <= + (rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and rld_dseq_q(3) and start_rld_data and rld_crit_qw(0) and not rld_crit_qw(1) and not rld_single) or + (rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and rld_dseq_q(3) and start_rld_data and rld_crit_qw(0) and rld_crit_qw(1) and not rld_single) or + (not rld_dseq_q(0) and not rld_dseq_q(1) and rld_dseq_q(2) and rld_dseq_q(3)) or + (not rld_dseq_q(0) and rld_dseq_q(1) and not rld_dseq_q(2) and not rld_dseq_q(3)) or + (rld_dseq_q(0) and not rld_dseq_q(1) and rld_dseq_q(2) and rld_dseq_q(3)) or + (rld_dseq_q(0) and rld_dseq_q(1) and not rld_dseq_q(2) and not rld_dseq_q(3)); +rld_data_qw(1) <= + (rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and rld_dseq_q(3) and start_rld_data and not rld_crit_qw(0) and rld_crit_qw(1) and not rld_single) or + (rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and rld_dseq_q(3) and start_rld_data and rld_crit_qw(0) and rld_crit_qw(1) and not rld_single) or + (not rld_dseq_q(0) and not rld_dseq_q(1) and not rld_dseq_q(2) and rld_dseq_q(3)) or + (not rld_dseq_q(0) and not rld_dseq_q(1) and rld_dseq_q(2) and rld_dseq_q(3)) or + (rld_dseq_q(0) and not rld_dseq_q(1) and rld_dseq_q(2) and not rld_dseq_q(3)) or + (rld_dseq_q(0) and rld_dseq_q(1) and not rld_dseq_q(2) and not rld_dseq_q(3)); +rld_complete <= + (rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and rld_dseq_q(3) and start_rld_data and rld_single) or + (rld_dseq_q(0) and not rld_dseq_q(1) and rld_dseq_q(2) and not rld_dseq_q(3)) or + (rld_dseq_q(0) and rld_dseq_q(1) and not rld_dseq_q(2) and not rld_dseq_q(3)); +rld_dseq_err <= + (not rld_dseq_q(0) and not rld_dseq_q(1) and not rld_dseq_q(2) and not rld_dseq_q(3)) or + (not rld_dseq_q(0) and rld_dseq_q(1) and not rld_dseq_q(2) and rld_dseq_q(3)) or + (not rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and not rld_dseq_q(3)) or + (not rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and rld_dseq_q(3)) or + (rld_dseq_q(0) and not rld_dseq_q(1) and not rld_dseq_q(2) and not rld_dseq_q(3)) or + (rld_dseq_q(0) and rld_dseq_q(1) and not rld_dseq_q(2) and rld_dseq_q(3)) or + (rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and not rld_dseq_q(3)); + + +end a2l2_axi; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/a2x_axi.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/a2x_axi.vhdl new file mode 100644 index 0000000..7e2b3f7 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/a2x_axi.vhdl @@ -0,0 +1,658 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; use ieee.std_logic_1164.all; +library ibm; +library work; use work.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; +library support; + use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity a2x_axi is + generic ( + C_M00_AXI_ID_WIDTH : integer := 4; + C_M00_AXI_ADDR_WIDTH : integer := 32; + C_M00_AXI_DATA_WIDTH : integer := 32; + C_M00_AXI_AWUSER_WIDTH : integer := 4; + C_M00_AXI_ARUSER_WIDTH : integer := 4; + C_M00_AXI_WUSER_WIDTH : integer := 4; + C_M00_AXI_RUSER_WIDTH : integer := 4; + C_M00_AXI_BUSER_WIDTH : integer := 4 + ); + port ( + + clk : in std_logic; + clk2x : in std_logic; + reset_n : in std_logic; + thold : in std_logic; + + core_id : in std_logic_vector(0 to 7); + thread_stop : in std_logic_vector(0 to 3); + thread_running : out std_logic_vector(0 to 3); + + ext_mchk : in std_logic_vector(0 to 3); + ext_checkstop : in std_logic; + debug_stop : in std_logic; + mchk : out std_logic_vector(0 to 3); + recov_err : out std_logic_vector(0 to 2); + checkstop : out std_logic_vector(0 to 2); + a2l2_axi_err : out std_logic_vector(0 to 3); + + crit_interrupt : in std_logic_vector(0 to 3); + ext_interrupt : in std_logic_vector(0 to 3); + perf_interrupt : in std_logic_vector(0 to 3); + + tb_update_enable : in std_logic; + tb_update_pulse : in std_logic; + + scom_sat_id : in std_logic_vector(0 to 3); + scom_dch_in : in std_logic; + scom_cch_in : in std_logic; + scom_dch_out : out std_logic; + scom_cch_out : out std_logic; + + flh2l2_gate : in std_logic; + hang_pulse : in std_logic_vector(0 to 3); + + m00_axi_awid : out std_logic_vector(C_M00_AXI_ID_WIDTH-1 downto 0); + m00_axi_awaddr : out std_logic_vector(C_M00_AXI_ADDR_WIDTH-1 downto 0); + m00_axi_awlen : out std_logic_vector(7 downto 0); + m00_axi_awsize : out std_logic_vector(2 downto 0); + m00_axi_awburst : out std_logic_vector(1 downto 0); + m00_axi_awlock : out std_logic; + m00_axi_awcache : out std_logic_vector(3 downto 0); + m00_axi_awprot : out std_logic_vector(2 downto 0); + m00_axi_awqos : out std_logic_vector(3 downto 0); + m00_axi_awuser : out std_logic_vector(C_M00_AXI_AWUSER_WIDTH-1 downto 0); + m00_axi_awvalid : out std_logic; + m00_axi_awready : in std_logic; + m00_axi_wdata : out std_logic_vector(C_M00_AXI_DATA_WIDTH-1 downto 0); + m00_axi_wstrb : out std_logic_vector(C_M00_AXI_DATA_WIDTH/8-1 downto 0); + m00_axi_wlast : out std_logic; + m00_axi_wuser : out std_logic_vector(C_M00_AXI_WUSER_WIDTH-1 downto 0); + m00_axi_wvalid : out std_logic; + m00_axi_wready : in std_logic; + m00_axi_bid : in std_logic_vector(C_M00_AXI_ID_WIDTH-1 downto 0); + m00_axi_bresp : in std_logic_vector(1 downto 0); + m00_axi_buser : in std_logic_vector(C_M00_AXI_BUSER_WIDTH-1 downto 0); + m00_axi_bvalid : in std_logic; + m00_axi_bready : out std_logic; + m00_axi_arid : out std_logic_vector(C_M00_AXI_ID_WIDTH-1 downto 0); + m00_axi_araddr : out std_logic_vector(C_M00_AXI_ADDR_WIDTH-1 downto 0); + m00_axi_arlen : out std_logic_vector(7 downto 0); + m00_axi_arsize : out std_logic_vector(2 downto 0); + m00_axi_arburst : out std_logic_vector(1 downto 0); + m00_axi_arlock : out std_logic; + m00_axi_arcache : out std_logic_vector(3 downto 0); + m00_axi_arprot : out std_logic_vector(2 downto 0); + m00_axi_arqos : out std_logic_vector(3 downto 0); + m00_axi_aruser : out std_logic_vector(C_M00_AXI_ARUSER_WIDTH-1 downto 0); + m00_axi_arvalid : out std_logic; + m00_axi_arready : in std_logic; + m00_axi_rid : in std_logic_vector(C_M00_AXI_ID_WIDTH-1 downto 0); + m00_axi_rdata : in std_logic_vector(C_M00_AXI_DATA_WIDTH-1 downto 0); + m00_axi_rresp : in std_logic_vector(1 downto 0); + m00_axi_rlast : in std_logic; + m00_axi_ruser : in std_logic_vector(C_M00_AXI_RUSER_WIDTH-1 downto 0); + m00_axi_rvalid : in std_logic; + m00_axi_rready : out std_logic + + ); +end a2x_axi; + +architecture a2x_axi of a2x_axi is + + constant expand_type : integer := 1; + constant threads : integer := 4; + constant xu_real_data_add : integer := 42; + constant st_data_32b_mode : integer := 1; + constant ac_st_data_32b_mode : integer := 1; + constant error_width : integer := 3; + constant expand_tlb_type : integer := 2; + constant extclass_width : integer := 2; + constant inv_seq_width : integer := 4; + constant lpid_width : integer := 8; + constant pid_width : integer := 14; + constant ra_entry_width : integer := 12; + constant real_addr_width : integer := 42; + +signal a2_nclk : clk_logic; + +signal an_ac_sg_7 : std_logic; +signal an_ac_back_inv : std_logic; +signal an_ac_back_inv_addr : std_logic_vector(22 to 63); +signal an_ac_back_inv_lbit : std_logic; +signal an_ac_back_inv_gs : std_logic; +signal an_ac_back_inv_ind : std_logic; +signal an_ac_back_inv_local : std_logic; +signal an_ac_back_inv_lpar_id : std_logic_vector(0 to 7); +signal an_ac_back_inv_target : std_logic_vector(0 to 4); +signal an_ac_dcr_act : std_logic; +signal an_ac_dcr_val : std_logic; +signal an_ac_dcr_read : std_logic; +signal an_ac_dcr_etid : std_logic_vector(0 to 1); +signal an_ac_dcr_data : std_logic_vector(0 to 63); +signal an_ac_dcr_done : std_logic; +signal an_ac_flh2l2_gate : std_logic; +signal an_ac_reld_core_tag : std_logic_vector(0 to 4); +signal an_ac_reld_data : std_logic_vector(0 to 127); +signal an_ac_reld_data_vld : std_logic; +signal an_ac_reld_ecc_err : std_logic; +signal an_ac_reld_ecc_err_ue : std_logic; +signal an_ac_reld_qw : std_logic_vector(57 to 59); +signal an_ac_reld_data_coming : std_logic; +signal an_ac_reld_ditc : std_logic; +signal an_ac_reld_crit_qw : std_logic; +signal an_ac_reld_l1_dump : std_logic; + +signal an_ac_req_ld_pop : std_logic; +signal an_ac_req_st_gather : std_logic; +signal an_ac_req_st_pop : std_logic; +signal an_ac_req_st_pop_thrd : std_logic_vector(0 to 2); + +signal an_ac_stcx_complete : std_logic_vector(0 to 3); +signal an_ac_stcx_pass : std_logic_vector(0 to 3); +signal an_ac_sync_ack : std_logic_vector(0 to 3); +signal an_ac_user_defined : std_logic_vector(0 to 3); +signal an_ac_reservation_vld : std_logic_vector(0 to 3); + +signal an_ac_icbi_ack : std_ulogic; +signal an_ac_icbi_ack_thread : std_ulogic_vector(0 to 1); +signal an_ac_sleep_en : std_ulogic_vector(0 to 3); +signal ac_an_back_inv_reject : std_ulogic; +signal ac_an_box_empty : std_ulogic_vector(0 to 3); +signal ac_an_lpar_id : std_ulogic_vector(0 to 7); +signal ac_an_power_managed : std_ulogic; +signal ac_an_req : std_ulogic; +signal ac_an_req_endian : std_ulogic; +signal ac_an_req_ld_core_tag : std_ulogic_vector(0 to 4); +signal ac_an_req_ld_xfr_len : std_ulogic_vector(0 to 2); +signal ac_an_req_pwr_token : std_ulogic; +signal ac_an_req_ra : std_ulogic_vector(22 to 63); +signal ac_an_req_spare_ctrl_a0 : std_ulogic_vector(0 to 3); +signal ac_an_req_thread : std_ulogic_vector(0 to 2); +signal ac_an_req_ttype : std_ulogic_vector(0 to 5); +signal ac_an_req_user_defined : std_ulogic_vector(0 to 3); +signal ac_an_req_wimg_g : std_ulogic; +signal ac_an_req_wimg_i : std_ulogic; +signal ac_an_req_wimg_m : std_ulogic; +signal ac_an_req_wimg_w : std_ulogic; +signal ac_an_reld_ditc_pop : std_ulogic_vector(0 to 3); +signal ac_an_rvwinkle_mode : std_ulogic; +signal ac_an_st_byte_enbl : std_ulogic_vector(0 to 31); +signal ac_an_st_data : std_ulogic_vector(0 to 255); +signal ac_an_st_data_pwr_token : std_ulogic; +signal ac_an_fu_bypass_events : std_ulogic_vector(0 to 7); +signal ac_an_iu_bypass_events : std_ulogic_vector(0 to 7); +signal ac_an_mm_bypass_events : std_ulogic_vector(0 to 7); +signal an_ac_debug_stop : std_ulogic; +signal ac_an_psro_ringsig : std_ulogic; +signal an_ac_psro_enable_dc : std_ulogic_vector(0 to 2); +signal an_ac_req_spare_ctrl_a1 : std_ulogic_vector(0 to 3); +signal alt_disp : std_ulogic; +signal d_mode : std_ulogic; +signal delay_lclkr : std_ulogic; +signal mpw1_b : std_ulogic; +signal mpw2_b : std_ulogic; +signal scdis_b : std_ulogic; + +signal an_ac_abist_mode_dc : std_ulogic; +signal an_ac_abist_start_test : std_ulogic; +signal an_ac_abst_scan_in : std_ulogic_vector(0 to 9); +signal an_ac_atpg_en_dc : std_ulogic; +signal an_ac_bcfg_scan_in : std_ulogic_vector(0 to 4); +signal an_ac_lbist_ary_wrt_thru_dc : std_ulogic; +signal an_ac_ccenable_dc : std_ulogic; +signal an_ac_ccflush_dc : std_ulogic; +signal an_ac_reset_1_complete : std_ulogic; +signal an_ac_reset_2_complete : std_ulogic; +signal an_ac_reset_3_complete : std_ulogic; +signal an_ac_reset_wd_complete : std_ulogic; +signal an_ac_dcfg_scan_in : std_ulogic_vector(0 to 2); +signal an_ac_fce_7 : std_ulogic; +signal an_ac_func_scan_in : std_ulogic_vector(0 to 63); +signal an_ac_gptr_scan_in : std_ulogic; +signal an_ac_hang_pulse : std_ulogic_vector(0 to 3); +signal an_ac_lbist_en_dc : std_ulogic; +signal an_ac_lbist_ac_mode_dc : std_ulogic; +signal an_ac_lbist_ip_dc : std_ulogic; +signal an_ac_malf_alert : std_ulogic; +signal an_ac_gsd_test_enable_dc : std_ulogic; +signal an_ac_gsd_test_acmode_dc : std_ulogic; +signal an_ac_repr_scan_in : std_ulogic; +signal an_ac_scan_diag_dc : std_ulogic; +signal an_ac_scan_dis_dc_b : std_ulogic; +signal an_ac_scan_type_dc : std_ulogic_vector(0 to 8); +signal an_ac_scom_sat_id : std_ulogic_vector(0 to 3); +signal an_ac_checkstop : std_ulogic; +signal an_ac_machine_check : std_ulogic_vector(0 to 3); +signal an_ac_tb_update_enable : std_ulogic; +signal an_ac_tb_update_pulse : std_ulogic; +signal an_ac_time_scan_in : std_ulogic; +signal an_ac_regf_scan_in : std_ulogic_vector(0 to 11); + +signal ac_an_debug_bus : std_ulogic_vector(0 to 87); +signal ac_an_event_bus : std_ulogic_vector(0 to 7); +signal ac_an_trace_triggers : std_ulogic_vector(0 to 11); +signal ac_an_abist_done_dc : std_ulogic; +signal ac_an_abst_scan_out : std_ulogic_vector(0 to 9); +signal ac_an_bcfg_scan_out : std_ulogic_vector(0 to 4); +signal ac_an_dcfg_scan_out : std_ulogic_vector(0 to 2); +signal ac_an_debug_trigger : std_ulogic_vector(0 to 3); +signal ac_an_func_scan_out : std_ulogic_vector(0 to 63); +signal ac_an_gptr_scan_out : std_ulogic; +signal ac_an_repr_scan_out : std_ulogic; +signal ac_an_time_scan_out : std_ulogic; +signal ac_an_special_attn : std_ulogic_vector(0 to 3); +signal ac_an_checkstop : std_ulogic_vector(0 to 2); +signal ac_an_dcr_act : std_ulogic; +signal ac_an_dcr_val : std_ulogic; +signal ac_an_dcr_read : std_ulogic; +signal ac_an_dcr_user : std_ulogic; +signal ac_an_dcr_etid : std_ulogic_vector(0 to 1); +signal ac_an_dcr_addr : std_ulogic_vector(11 to 20); +signal ac_an_dcr_data : std_ulogic_vector(0 to 63); + +signal ac_an_machine_check : std_ulogic_vector(0 to 3); +signal ac_an_pm_thread_running : std_ulogic_vector(0 to 3); +signal ac_an_recov_err : std_ulogic_vector(0 to 2); +signal ac_an_local_checkstop : std_ulogic_vector(0 to 2); +signal an_ac_external_mchk : std_ulogic_vector(0 to 3); + +signal gnd : power_logic; +signal vcs : power_logic; +signal vdd : power_logic; +signal vio : power_logic; + +signal node_scom_dch_in : std_ulogic; +signal node_scom_cch_in : std_ulogic; +signal node_scom_dch_out : std_ulogic; +signal node_scom_cch_out : std_ulogic; + +signal an_ac_camfence_en_dc : std_ulogic; + +signal tidn : std_ulogic; +signal tiup : std_ulogic; + +begin + +tidn <= '0'; +tiup <= '1'; + +a2_nclk.clk <= clk; +a2_nclk.clk2x <= clk2x; +a2_nclk.clk4x <= '0'; +a2_nclk.sreset <= not reset_n; + +alt_disp <= tidn; +d_mode <= tiup; +delay_lclkr <= tidn; +mpw1_b <= tidn; +mpw2_b <= tidn; +scdis_b <= tidn; +an_ac_ccenable_dc <= tiup; +an_ac_scan_type_dc <= tiup & tiup & tiup & tiup & tiup & tiup & tiup & tiup & tiup; + +an_ac_func_scan_in <= (others => '0'); +an_ac_regf_scan_in <= (others => '0'); +an_ac_bcfg_scan_in <= (others => '0'); +an_ac_dcfg_scan_in <= (others => '0'); +an_ac_abst_scan_in <= (others => '0'); +an_ac_gptr_scan_in <= '0'; +an_ac_repr_scan_in <= '0'; +an_ac_time_scan_in <= '0'; +an_ac_atpg_en_dc <= '0'; +an_ac_scan_dis_dc_b <= '1'; +an_ac_camfence_en_dc <= '0'; +an_ac_abist_start_test <= '0'; +an_ac_abist_mode_dc <= '0'; +an_ac_lbist_en_dc <= '0'; +an_ac_lbist_ac_mode_dc <= '0'; +an_ac_lbist_ip_dc <= '0'; +an_ac_fce_7 <= '0'; +an_ac_sg_7 <= '0'; +an_ac_gsd_test_acmode_dc <= '0'; +an_ac_lbist_ary_wrt_thru_dc <= '0'; +an_ac_gsd_test_enable_dc <= '0'; +an_ac_scan_diag_dc <= '0'; +an_ac_psro_enable_dc <= (others => '0'); +an_ac_ccflush_dc <= '0'; + +an_ac_flh2l2_gate <= flh2l2_gate; +an_ac_external_mchk <= ext_mchk; +an_ac_checkstop <= ext_checkstop; +an_ac_debug_stop <= debug_stop; +an_ac_hang_pulse <= hang_pulse; +thread_running <= ac_an_pm_thread_running; + +mchk <= ac_an_machine_check; +recov_err <= ac_an_recov_err; +checkstop <= ac_an_local_checkstop; + +an_ac_scom_sat_id <= scom_sat_id; +node_scom_dch_in <= scom_dch_in; +node_scom_cch_in <= scom_cch_in; +scom_dch_out <= node_scom_dch_out; +scom_cch_out <= node_scom_cch_out; + +an_ac_user_defined <= (others => '0'); +an_ac_req_spare_ctrl_a1 <= (others => '0'); + +an_ac_icbi_ack <= '0'; +an_ac_icbi_ack_thread <= (others => '0'); + +an_ac_back_inv <= '0'; +an_ac_back_inv_gs <= '0'; +an_ac_back_inv_local <= '0'; +an_ac_back_inv_lbit <= '0'; +an_ac_back_inv_ind <= '0'; +an_ac_back_inv_addr <= (others => '0'); +an_ac_back_inv_lpar_id <= (others => '0'); +an_ac_back_inv_target <= (others => '0'); + +an_ac_reld_ditc <= '0'; + +an_ac_dcr_act <= '0'; +an_ac_dcr_val <= '0'; +an_ac_dcr_read <= '0'; +an_ac_dcr_etid <= (others => '0'); +an_ac_dcr_data <= (others => '0'); +an_ac_dcr_done <= '0'; + +an_ac_reset_1_complete <= '0'; +an_ac_reset_2_complete <= '0'; +an_ac_reset_3_complete <= '0'; +an_ac_reset_wd_complete <= '0'; + +an_ac_sleep_en <= (others => '0'); +an_ac_malf_alert <= '0'; + +acq: entity work.acq_soft(acq_soft) + generic map( + error_width => error_width, + expand_type => expand_type, + expand_tlb_type => expand_tlb_type, + extclass_width => extclass_width, + inv_seq_width => inv_seq_width, + lpid_width => lpid_width, + pid_width => pid_width, + ra_entry_width => ra_entry_width, + real_addr_width => real_addr_width, + threads => threads, + + xu_real_data_add => xu_real_data_add, + st_data_32b_mode => st_data_32b_mode, + ac_st_data_32b_mode => ac_st_data_32b_mode + ) + port map ( + an_ac_back_inv => an_ac_back_inv, + an_ac_back_inv_addr => an_ac_back_inv_addr, + an_ac_back_inv_lbit => an_ac_back_inv_lbit, + an_ac_back_inv_gs => an_ac_back_inv_gs, + an_ac_back_inv_ind => an_ac_back_inv_ind, + an_ac_back_inv_local => an_ac_back_inv_local, + an_ac_back_inv_lpar_id => an_ac_back_inv_lpar_id, + an_ac_back_inv_target => an_ac_back_inv_target, + an_ac_crit_interrupt => crit_interrupt, + an_ac_dcr_act => an_ac_dcr_act, + an_ac_dcr_val => an_ac_dcr_val, + an_ac_dcr_read => an_ac_dcr_read, + an_ac_dcr_etid => an_ac_dcr_etid, + an_ac_dcr_data => an_ac_dcr_data, + an_ac_dcr_done => an_ac_dcr_done, + an_ac_ext_interrupt => ext_interrupt, + an_ac_flh2l2_gate => an_ac_flh2l2_gate, + an_ac_reld_core_tag => an_ac_reld_core_tag, + an_ac_reld_data => an_ac_reld_data, + an_ac_reld_data_vld => an_ac_reld_data_vld, + an_ac_reld_ecc_err => an_ac_reld_ecc_err, + an_ac_reld_ecc_err_ue => an_ac_reld_ecc_err_ue, + an_ac_reld_qw => an_ac_reld_qw, + an_ac_reld_data_coming => an_ac_reld_data_coming, + an_ac_reld_ditc => an_ac_reld_ditc, + an_ac_reld_crit_qw => an_ac_reld_crit_qw, + an_ac_reld_l1_dump => an_ac_reld_l1_dump, + an_ac_regf_scan_in => an_ac_regf_scan_in, + an_ac_req_ld_pop => an_ac_req_ld_pop, + an_ac_req_spare_ctrl_a1 => an_ac_req_spare_ctrl_a1, + an_ac_req_st_gather => an_ac_req_st_gather, + an_ac_req_st_pop => an_ac_req_st_pop, + an_ac_req_st_pop_thrd => an_ac_req_st_pop_thrd, + an_ac_reservation_vld => an_ac_reservation_vld, + an_ac_sleep_en => an_ac_sleep_en, + an_ac_stcx_complete => an_ac_stcx_complete, + an_ac_stcx_pass => an_ac_stcx_pass, + an_ac_sync_ack => an_ac_sync_ack, + an_ac_icbi_ack => an_ac_icbi_ack, + an_ac_icbi_ack_thread => an_ac_icbi_ack_thread, + a2_nclk => a2_nclk, + an_ac_abist_mode_dc => an_ac_abist_mode_dc, + an_ac_abist_start_test => an_ac_abist_start_test, + an_ac_abst_scan_in => an_ac_abst_scan_in, + an_ac_rtim_sl_thold_7 => thold, + an_ac_ary_nsl_thold_7 => thold, + an_ac_func_nsl_thold_7 => thold, + an_ac_func_sl_thold_7 => thold, + an_ac_atpg_en_dc => an_ac_atpg_en_dc, + an_ac_bcfg_scan_in => an_ac_bcfg_scan_in, + an_ac_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc, + an_ac_ccenable_dc => an_ac_ccenable_dc, + an_ac_ccflush_dc => an_ac_ccflush_dc, + an_ac_coreid => core_id, + an_ac_lbist_ip_dc => an_ac_lbist_ip_dc, + an_ac_malf_alert => an_ac_malf_alert, + an_ac_reset_1_complete => an_ac_reset_1_complete, + an_ac_reset_2_complete => an_ac_reset_2_complete, + an_ac_reset_3_complete => an_ac_reset_3_complete, + an_ac_reset_wd_complete => an_ac_reset_wd_complete, + an_ac_dcfg_scan_in => an_ac_dcfg_scan_in, + an_ac_debug_stop => an_ac_debug_stop, + an_ac_external_mchk => an_ac_external_mchk, + an_ac_fce_7 => an_ac_fce_7, + + an_ac_func_scan_in => an_ac_func_scan_in, + an_ac_gptr_scan_in => an_ac_gptr_scan_in, + an_ac_gsd_test_acmode_dc => an_ac_gsd_test_acmode_dc, + an_ac_gsd_test_enable_dc => an_ac_gsd_test_enable_dc, + an_ac_hang_pulse => an_ac_hang_pulse, + an_ac_lbist_en_dc => an_ac_lbist_en_dc, + an_ac_lbist_ac_mode_dc => an_ac_lbist_ac_mode_dc, + an_ac_perf_interrupt => perf_interrupt, + an_ac_pm_thread_stop => thread_stop, + an_ac_psro_enable_dc => an_ac_psro_enable_dc, + an_ac_repr_scan_in => an_ac_repr_scan_in, + an_ac_scan_diag_dc => an_ac_scan_diag_dc, + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b, + an_ac_scan_type_dc => an_ac_scan_type_dc, + an_ac_scom_cch => node_scom_cch_in, + an_ac_scom_dch => node_scom_dch_in, + an_ac_scom_sat_id => an_ac_scom_sat_id, + an_ac_sg_7 => an_ac_sg_7, + an_ac_checkstop => an_ac_checkstop, + an_ac_tb_update_enable => tb_update_enable, + an_ac_tb_update_pulse => tb_update_pulse, + an_ac_time_scan_in => an_ac_time_scan_in, + ac_an_back_inv_reject => ac_an_back_inv_reject, + ac_an_box_empty => ac_an_box_empty, + ac_an_lpar_id => ac_an_lpar_id, + ac_an_machine_check => ac_an_machine_check, + ac_an_power_managed => ac_an_power_managed, + ac_an_req => ac_an_req, + ac_an_req_endian => ac_an_req_endian, + ac_an_req_ld_core_tag => ac_an_req_ld_core_tag, + ac_an_req_ld_xfr_len => ac_an_req_ld_xfr_len, + ac_an_req_pwr_token => ac_an_req_pwr_token, + ac_an_req_ra => ac_an_req_ra, + ac_an_req_spare_ctrl_a0 => ac_an_req_spare_ctrl_a0, + ac_an_req_thread => ac_an_req_thread, + ac_an_req_ttype => ac_an_req_ttype, + ac_an_req_user_defined => ac_an_req_user_defined, + ac_an_req_wimg_g => ac_an_req_wimg_g, + ac_an_req_wimg_i => ac_an_req_wimg_i, + ac_an_req_wimg_m => ac_an_req_wimg_m, + ac_an_req_wimg_w => ac_an_req_wimg_w, + ac_an_reld_ditc_pop => ac_an_reld_ditc_pop, + ac_an_rvwinkle_mode => ac_an_rvwinkle_mode, + ac_an_st_byte_enbl => ac_an_st_byte_enbl, + ac_an_st_data => ac_an_st_data, + ac_an_st_data_pwr_token => ac_an_st_data_pwr_token, + ac_an_fu_bypass_events => ac_an_fu_bypass_events, + ac_an_iu_bypass_events => ac_an_iu_bypass_events, + ac_an_mm_bypass_events => ac_an_mm_bypass_events, + ac_an_debug_bus => ac_an_debug_bus, + ac_an_event_bus => ac_an_event_bus, + ac_an_trace_triggers => ac_an_trace_triggers, + ac_an_abist_done_dc => ac_an_abist_done_dc, + ac_an_abst_scan_out => ac_an_abst_scan_out, + ac_an_bcfg_scan_out => ac_an_bcfg_scan_out, + ac_an_dcfg_scan_out => ac_an_dcfg_scan_out, + ac_an_debug_trigger => ac_an_debug_trigger, + ac_an_func_scan_out => ac_an_func_scan_out, + ac_an_gptr_scan_out => ac_an_gptr_scan_out, + ac_an_pm_thread_running => ac_an_pm_thread_running, + ac_an_psro_ringsig => ac_an_psro_ringsig, + ac_an_recov_err => ac_an_recov_err, + ac_an_repr_scan_out => ac_an_repr_scan_out, + ac_an_scom_cch => node_scom_cch_out, + ac_an_scom_dch => node_scom_dch_out, + ac_an_time_scan_out => ac_an_time_scan_out, + ac_an_special_attn => ac_an_special_attn, + ac_an_checkstop => ac_an_checkstop, + ac_an_local_checkstop => ac_an_local_checkstop, + ac_an_dcr_act => ac_an_dcr_act, + ac_an_dcr_val => ac_an_dcr_val, + ac_an_dcr_read => ac_an_dcr_read, + ac_an_dcr_user => ac_an_dcr_user, + ac_an_dcr_etid => ac_an_dcr_etid, + ac_an_dcr_addr => ac_an_dcr_addr, + ac_an_dcr_data => ac_an_dcr_data, + an_ac_camfence_en_dc => an_ac_camfence_en_dc, + + gnd => gnd, + vcs => vcs, + vdd => vdd + ); + +a2l2_axi: entity work.a2l2_axi(a2l2_axi) +generic map( + C_M00_AXI_ID_WIDTH => C_M00_AXI_ID_WIDTH, + C_M00_AXI_ADDR_WIDTH => C_M00_AXI_ADDR_WIDTH, + C_M00_AXI_DATA_WIDTH => C_M00_AXI_DATA_WIDTH, + C_M00_AXI_AWUSER_WIDTH => C_M00_AXI_AWUSER_WIDTH, + C_M00_AXI_ARUSER_WIDTH => C_M00_AXI_ARUSER_WIDTH, + C_M00_AXI_WUSER_WIDTH => C_M00_AXI_WUSER_WIDTH, + C_M00_AXI_RUSER_WIDTH => C_M00_AXI_RUSER_WIDTH, + C_M00_AXI_BUSER_WIDTH => C_M00_AXI_BUSER_WIDTH + ) +port map( + clk => clk, + reset_n => reset_n, + err => a2l2_axi_err, + ac_an_req => ac_an_req, + ac_an_req_endian => ac_an_req_endian, + ac_an_req_ld_core_tag => ac_an_req_ld_core_tag, + ac_an_req_ld_xfr_len => ac_an_req_ld_xfr_len, + ac_an_req_pwr_token => ac_an_req_pwr_token, + ac_an_req_ra => ac_an_req_ra, + ac_an_req_thread => ac_an_req_thread, + ac_an_req_ttype => ac_an_req_ttype, + ac_an_req_user_defined => ac_an_req_user_defined, + ac_an_req_wimg_g => ac_an_req_wimg_g, + ac_an_req_wimg_i => ac_an_req_wimg_i, + ac_an_req_wimg_m => ac_an_req_wimg_m, + ac_an_req_wimg_w => ac_an_req_wimg_w, + ac_an_st_byte_enbl => ac_an_st_byte_enbl, + ac_an_st_data => ac_an_st_data, + ac_an_st_data_pwr_token => ac_an_st_data_pwr_token, + an_ac_reld_core_tag => an_ac_reld_core_tag, + an_ac_reld_data => an_ac_reld_data, + an_ac_reld_data_vld => an_ac_reld_data_vld, + an_ac_reld_ecc_err => an_ac_reld_ecc_err, + an_ac_reld_ecc_err_ue => an_ac_reld_ecc_err_ue, + an_ac_reld_qw => an_ac_reld_qw, + an_ac_reld_data_coming => an_ac_reld_data_coming, + an_ac_reld_crit_qw => an_ac_reld_crit_qw, + an_ac_reld_l1_dump => an_ac_reld_l1_dump, + an_ac_req_ld_pop => an_ac_req_ld_pop, + an_ac_req_st_pop => an_ac_req_st_pop, + an_ac_req_st_gather => an_ac_req_st_gather, + an_ac_req_st_pop_thrd => an_ac_req_st_pop_thrd, + an_ac_reservation_vld => an_ac_reservation_vld, + an_ac_stcx_complete => an_ac_stcx_complete, + an_ac_stcx_pass => an_ac_stcx_pass, + an_ac_sync_ack => an_ac_sync_ack, + m00_axi_awid => m00_axi_awid, + m00_axi_awaddr => m00_axi_awaddr, + m00_axi_awlen => m00_axi_awlen, + m00_axi_awsize => m00_axi_awsize, + m00_axi_awburst => m00_axi_awburst, + m00_axi_awlock => m00_axi_awlock, + m00_axi_awcache => m00_axi_awcache, + m00_axi_awprot => m00_axi_awprot, + m00_axi_awqos => m00_axi_awqos, + m00_axi_awuser => m00_axi_awuser, + m00_axi_awvalid => m00_axi_awvalid, + m00_axi_awready => m00_axi_awready, + m00_axi_wdata => m00_axi_wdata, + m00_axi_wstrb => m00_axi_wstrb, + m00_axi_wlast => m00_axi_wlast, + m00_axi_wuser => m00_axi_wuser, + m00_axi_wvalid => m00_axi_wvalid, + m00_axi_wready => m00_axi_wready, + m00_axi_bid => m00_axi_bid, + m00_axi_bresp => m00_axi_bresp, + m00_axi_buser => m00_axi_buser, + m00_axi_bvalid => m00_axi_bvalid, + m00_axi_bready => m00_axi_bready, + m00_axi_arid => m00_axi_arid, + m00_axi_araddr => m00_axi_araddr, + m00_axi_arlen => m00_axi_arlen, + m00_axi_arsize => m00_axi_arsize, + m00_axi_arburst => m00_axi_arburst, + m00_axi_arlock => m00_axi_arlock, + m00_axi_arcache => m00_axi_arcache, + m00_axi_arprot => m00_axi_arprot, + m00_axi_arqos => m00_axi_arqos, + m00_axi_aruser => m00_axi_aruser, + m00_axi_arvalid => m00_axi_arvalid, + m00_axi_arready => m00_axi_arready, + m00_axi_rid => m00_axi_rid, + m00_axi_rdata => m00_axi_rdata, + m00_axi_rresp => m00_axi_rresp, + m00_axi_rlast => m00_axi_rlast, + m00_axi_ruser => m00_axi_ruser, + m00_axi_rvalid => m00_axi_rvalid, + m00_axi_rready => m00_axi_rready + ); + +end a2x_axi; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/a2x_pkg.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/a2x_pkg.vhdl new file mode 100644 index 0000000..d583004 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/a2x_pkg.vhdl @@ -0,0 +1,501 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +package a2x_pkg is + +attribute dont_touch : string; + +constant c_ld_queue_size : integer := 4; +constant c_ld_queue_bits : integer := 2; +constant c_st_queue_size : integer := 16; +constant c_st_queue_bits : integer := 4; +constant c_max_pointer : integer := 2; + + +constant IFETCH : std_logic_vector(0 to 5) := "000000"; +constant IFETCHPRE : std_logic_vector(0 to 5) := "000001"; +constant LOAD : std_logic_vector(0 to 5) := "001000"; +constant STORE : std_logic_vector(0 to 5) := "100000"; + +constant LARX : std_logic_vector(0 to 5) := "001001"; +constant LARXHINT : std_logic_vector(0 to 5) := "001011"; +constant STCX : std_logic_vector(0 to 5) := "101011"; + +constant LWSYNC : std_logic_vector(0 to 5) := "101010"; +constant HWSYNC : std_logic_vector(0 to 5) := "101011"; +constant MBAR : std_logic_vector(0 to 5) := "110010"; +constant TLBSYNC : std_logic_vector(0 to 5) := "111010"; + +constant DCBI : std_logic_vector(0 to 5) := "111111"; + + +function or_reduce(slv: in std_logic_vector) return std_logic; +function and_reduce(slv: in std_logic_vector) return std_logic; +function inc(a: in std_logic_vector) return std_logic_vector; +function inc(a: in std_logic_vector; b: in integer) return std_logic_vector; +function dec(a: in std_logic_vector) return std_logic_vector; +function eq(a: in std_logic_vector; b: in integer) return boolean; +function eq(a: in std_logic_vector; b: in integer) return std_logic; +function eq(a: in std_logic_vector; b: in std_logic_vector) return boolean; +function eq(a: in std_logic_vector; b: in std_logic_vector) return std_logic; +function gt(a: in std_logic_vector; b: in integer) return boolean; +function gt(a: in std_logic_vector; b: in std_logic_vector) return boolean; +function gt(a: in std_logic_vector; b: in std_logic_vector) return std_logic; +function nz(a: in std_logic_vector) return boolean; +function nz(a: in std_logic_vector) return std_logic; +function b(a: in boolean) return std_logic; +function b(a: in std_logic) return boolean; + +function clog2(n : in integer) return integer; +function conv_integer(a: in std_logic_vector) return integer; +function max(a: in integer; b: in integer) return integer; + +function right_one(a: in std_logic_vector) return std_logic_vector; +function gate_and(a: in std_logic; b: in std_logic_vector) return std_logic_vector; +function rotl(a: in std_logic_vector; b: in integer) return std_logic_vector; +function rotl(a: in std_logic_vector; b: in std_logic_vector) return std_logic_vector; +function rotr(a: in std_logic_vector; b: in integer) return std_logic_vector; +function rotr(a: in std_logic_vector; b: in std_logic_vector) return std_logic_vector; +function enc(a: in std_logic_vector) return std_logic_vector; +function enc(a: in std_logic_vector; b: in integer) return std_logic_vector; + +subtype RADDR is std_logic_vector(64-42 to 63); +subtype LINEADDR is std_logic_vector(64-42 to 59); + +type A2L2REQUEST is record + valid : std_logic; + sent : std_logic; + data : std_logic; + dseq : std_logic_vector(0 to 2); + endian : std_logic; + tag : std_logic_vector(0 to 4); + len : std_logic_vector(0 to 2); + ra : RADDR; + thread : std_logic_vector(0 to 1); + spec : std_logic; + ditc : std_logic; + ttype : std_logic_vector(0 to 5); + user : std_logic_vector(0 to 3); + wimg : std_logic_vector(0 to 3); + hwsync : std_logic; +end record; + +type A2L2STOREDATA is record + data : std_logic_vector(0 to 127); + be : std_logic_vector(0 to 15); +end record; + +type A2L2RELOAD is record + coming : std_logic; + valid : std_logic; + tag : std_logic_vector(0 to 4); + data : std_logic_vector(0 to 127); + ee : std_logic; + ue : std_logic; + qw : std_logic_vector(57 to 59); + crit : std_logic; + dump : std_logic; +end record; + +type A2L2STATUS is record + ld_pop : std_logic; + st_pop : std_logic; + st_pop_thrd : std_logic_vector(0 to 2); + gather : std_logic; + res_valid : std_logic_vector(0 to 3); + stcx_complete : std_logic_vector(0 to 3); + stcx_pass : std_logic_vector(0 to 3); + sync_ack : std_logic_vector(0 to 3); +end record; + +type A2L2RESV is record + valid : std_logic; + ra : LINEADDR; +end record; + +type LOADQUEUE is array(0 to c_ld_queue_size-1) of A2L2REQUEST; +type LOADDATAQUEUE is array(0 to 63) of std_logic_vector(0 to 31); +type LOADQUEUEDEP is array(0 to c_ld_queue_size-1) of std_logic_vector(0 to c_st_queue_bits); +type STOREQUEUE is array(0 to c_st_queue_size-1) of A2L2REQUEST; +type STOREDATAQUEUE is array(0 to c_st_queue_size-1) of A2L2STOREDATA; +type STOREQUEUEDEP is array(0 to c_st_queue_size-1) of std_logic_vector(0 to c_ld_queue_bits); +type RESVARRAY is array(0 to 3) of A2L2RESV; + +function address_check(a: in A2L2REQUEST; b: in A2L2REQUEST) return std_logic; + +function mux_queue(a: in LOADQUEUE; b: in std_logic_vector) return A2L2REQUEST; +function mux_queue(a: in LOADDATAQUEUE; b: in integer) return std_logic_vector; +function mux_queue(a: in LOADDATAQUEUE; b: in std_logic_vector) return std_logic_vector; +function mux_queue(a: in LOADQUEUEDEP; b: in std_logic_vector) return std_logic_vector; +function mux_queue(a: in STOREQUEUE; b: in std_logic_vector) return A2L2REQUEST; +function mux_queue(a: in STOREDATAQUEUE; b: in std_logic_vector) return A2L2STOREDATA; +function mux_queue(a: in STOREQUEUEDEP; b: in std_logic_vector) return std_logic_vector; + +end a2x_pkg; + +package body a2x_pkg is + + +function or_reduce(slv: in std_logic_vector) return std_logic is + variable res: std_logic := '0'; +begin + for i in slv'range loop + res := res or slv(i); + end loop; + return res; +end function; + +function and_reduce(slv: in std_logic_vector) return std_logic is + variable res: std_logic := '1'; +begin + for i in slv'range loop + res := res and slv(i); + end loop; + return res; +end function; + +function inc(a: in std_logic_vector) return std_logic_vector is + variable res: std_logic_vector(0 to a'length-1); +begin + res := std_logic_vector(unsigned(a) + 1); + return res; +end function; + +function inc(a: in std_logic_vector; b: in integer) return std_logic_vector is + variable res: std_logic_vector(0 to a'length-1); +begin + res := std_logic_vector(unsigned(a) + b); + return res; +end function; + +function dec(a: in std_logic_vector) return std_logic_vector is + variable res: std_logic_vector(0 to a'length-1); +begin + res := std_logic_vector(unsigned(a) - 1); + return res; +end function; + +function eq(a: in std_logic_vector; b: in integer) return boolean is + variable res: boolean; +begin + res := unsigned(a) = b; + return res; +end function; + +function eq(a: in std_logic_vector; b: in integer) return std_logic is + variable res: std_logic; +begin + if unsigned(a) = b then + res := '1'; + else + res := '0'; + end if; + return res; +end function; + +function eq(a: in std_logic_vector; b: in std_logic_vector) return boolean is + variable res: boolean; +begin + res := unsigned(a) = unsigned(b); + return res; +end function; + +function eq(a: in std_logic_vector; b: in std_logic_vector) return std_logic is + variable res: std_logic; +begin + if unsigned(a) = unsigned(b) then + res := '1'; + else + res := '0'; + end if; + return res; +end function; + +function gt(a: in std_logic_vector; b: in integer) return boolean is + variable res: boolean; +begin + res := unsigned(a) > b; + return res; +end function; + +function gt(a: in std_logic_vector; b: in std_logic_vector) return boolean is + variable res: boolean; +begin + res := unsigned(a) > unsigned(b); + return res; +end function; + +function gt(a: in std_logic_vector; b: in std_logic_vector) return std_logic is + variable res: std_logic; +begin + if unsigned(a) > unsigned(b) then + res := '1'; + else + res := '0'; + end if; + return res; +end function; + +function nz(a: in std_logic_vector) return boolean is + variable res: boolean; +begin + res := unsigned(a) /= 0; + return res; +end function; + +function nz(a: in std_logic_vector) return std_logic is + variable res: std_logic; +begin + if unsigned(a) /= 0 then + res := '1'; + else + res := '0'; + end if; + return res; +end function; + +function b(a: in boolean) return std_logic is + variable res: std_logic; +begin + if a then + res := '1'; + else + res := '0'; + end if; + return res; +end function; + +function b(a: in std_logic) return boolean is + variable res: boolean; +begin + if a = '1' then + res := true; + else + res := false; + end if; + return res; +end function; + +function right_one(a: in std_logic_vector) return std_logic_vector is + variable res : std_logic_vector(0 to a'length - 1); +begin + for i in a'length - 1 downto 0 loop + if a(i) = '1' then + res(i) := '1'; + exit; + end if; + end loop; + return res; +end function; + +function rotl(a: in std_logic_vector; b: in integer) return std_logic_vector is + variable res : std_logic_vector(0 to a'length - 1); +begin + res := a(b to a'length - 1) & a(0 to b - 1); + return res; +end function; + +function rotl(a: in std_logic_vector; b: in std_logic_vector) return std_logic_vector is + variable res : std_logic_vector(0 to a'length - 1) := a; + variable c : integer := conv_integer(b); + variable i : integer; +begin + for i in 0 to a'length - 1 loop + if (i + c < a'length) then + res(i) := a(i + c); + else + res(i) := a(i + c - a'length); + end if; + end loop; + return res; +end function; + +function rotr(a: in std_logic_vector; b: in integer) return std_logic_vector is + variable res: std_logic_vector(0 to a'length - 1); +begin + res := a(a'length - b to a'length - 1) & a(0 to a'length - b - 1); + return res; +end function; + +function rotr(a: in std_logic_vector; b: in std_logic_vector) return std_logic_vector is + variable res: std_logic_vector(0 to a'length - 1); + variable c : integer := conv_integer(b); +begin + for i in 0 to a'length - 1 loop + if (a'length - c + i < a'length) then + res(i) := a(a'length - c + i); + else + res(i) := a(-c + i); + end if; + end loop; + return res; +end function; + +function gate_and(a: in std_logic; b: in std_logic_vector) return std_logic_vector is + variable res: std_logic_vector(0 to b'length-1); +begin + if a = '1' then + res := b; + else + res := (others => '0'); + end if; + return res; +end function; + +function enc(a: in std_logic_vector) return std_logic_vector is + variable res: std_logic_vector(0 to clog2(a'length)-1) := (others => '0'); +begin + for i in 0 to a'length - 1 loop + if (a(i) = '1') then + res := std_logic_vector(to_unsigned(i, res'length)); + exit; + end if; + end loop; + return res; +end function; + +function enc(a: in std_logic_vector; b: in integer) return std_logic_vector is + variable res: std_logic_vector(0 to b-1) := (others => '0'); +begin + for i in 0 to a'length - 1 loop + if (a(i) = '1') then + res := std_logic_vector(to_unsigned(i, res'length)); + exit; + end if; + end loop; + return res; +end function; + +function conv_integer(a: in std_logic_vector) return integer is + variable res: integer; +begin + res := to_integer(unsigned(a)); + return res; +end function; + +function max(a: in integer; b: in integer) return integer is + variable res : integer; +begin + if (a > b) then + res := a; + else + res := b; + end if; + return res; +end function; + +function mux_queue(a: in LOADQUEUE; b: in std_logic_vector) return A2L2REQUEST is + variable res: A2L2REQUEST; +begin + res := a(conv_integer(b)); + return res; +end function; + +function mux_queue(a: in LOADDATAQUEUE; b: in std_logic_vector) return std_logic_vector is + variable res: std_logic_vector(0 to a(0)'length-1); +begin + res := a(conv_integer(b)); + return res; +end function; + +function mux_queue(a: in LOADDATAQUEUE; b: in integer) return std_logic_vector is + variable res: std_logic_vector(0 to a(0)'length-1); +begin + res := a(b); + return res; +end function; + +function mux_queue(a: in LOADQUEUEDEP; b: in std_logic_vector) return std_logic_vector is + variable res: std_logic_vector(0 to a(0)'length-1); +begin + res := a(conv_integer(b)); + return res; +end function; + + +function mux_queue(a: in STOREQUEUE; b: in std_logic_vector) return A2L2REQUEST is + variable res: A2L2REQUEST; +begin + res := a(conv_integer(b)); + return res; +end function; + +function mux_queue(a: in STOREDATAQUEUE; b: in std_logic_vector) return A2L2STOREDATA is + variable res: A2L2STOREDATA; +begin + res := a(conv_integer(b)); + return res; +end function; + +function mux_queue(a: in STOREQUEUEDEP; b: in std_logic_vector) return std_logic_vector is + variable res: std_logic_vector(0 to a(0)'length-1); +begin + res := a(conv_integer(b)); + return res; +end function; + +function address_check(a: in A2L2REQUEST; b: in A2L2REQUEST) return std_logic is + variable res: std_logic := '0'; + variable a_start, a_end, b_start, b_end : unsigned(0 to a.ra'length-1); +begin + a_start := unsigned(a.ra); + a_end := unsigned(a.ra) + unsigned(a.len); + b_start := unsigned(b.ra); + b_end := unsigned(b.ra) + unsigned(b.len); + if ((a.valid = '1') and (a.spec = '0') and (b.valid = '1') and (b.spec = '0')) then + if ((a_start >= b_start) and (a_start <= b_end)) then + res := '1'; + elsif ((a_end >= b_start) and (a_end <= b_end)) then + res := '1'; + end if; + end if; + return res; +end function; + +function clog2(n : in integer) return integer is + variable i : integer; + variable j : integer := n - 1; + variable res : integer := 1; +begin + for i in 0 to 31 loop + if (j > 1) then + j := j / 2; + res := res + 1; + else + exit; + end if; + end loop; + return res; +end; + +end a2x_pkg; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/acq_soft.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/acq_soft.vhdl new file mode 100644 index 0000000..f434492 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/acq_soft.vhdl @@ -0,0 +1,4625 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee; use ieee.std_logic_1164.all; +library ibm; +library work; use work.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; +library support; + use support.power_logic_pkg.all; + use work.iuq_pkg.all; +library tri; + use tri.tri_latches_pkg.all; +use work.xuq_pkg.all; + +ENTITY acq_soft IS + GENERIC(xu_eff_ifar : integer := 62; + expand_type : integer := 2; + regmode : integer := 6; + hvmode : integer := 1; + a2mode : integer := 1; + bcfg_epn_0to15 : integer := 0; + bcfg_epn_16to31 : integer := 0; + bcfg_epn_32to47 : integer := (2**16)-1; + bcfg_epn_48to51 : integer := (2**4)-1; + bcfg_rpn_22to31 : integer := (2**10)-1; + bcfg_rpn_32to47 : integer := (2**16)-1; + bcfg_rpn_48to51 : integer := (2**4)-1; + fpr_addr_width : integer := 5; + lmq_entries : integer := 8; + threads : integer := 4; + ucode_mode : integer := 1; + uc_ifar : integer := 21; + data_out_width : integer := 64; + debug_event_width : integer := 16; + debug_trace_width : integer := 88; + epn_width : integer := 52; + eptr_width : integer := 4; + erat_ary_data_width : integer := 73; + erat_cam_data_width : integer := 75; + erat_rel_data_width : integer := 132; + error_width : integer := 3; + expand_tlb_type : integer := 2; + extclass_width : integer := 2; + inv_seq_width : integer := 6; + lpid_width : integer := 8; + lru_width : integer := 16; + mmucr0_width : integer := 20; + mmucr1_width : integer := 32; + mmucr2_width : integer := 32; + mmucr3_width : integer := 15; + pid_width : integer := 14; + pid_width_erat : integer := 8; + por_seq_width : integer := 3; + ra_entry_width : integer := 12; + real_addr_width : integer := 42; + req_epn_width : integer := 52; + rpn_width : integer := 30; + rs_data_width : integer := 64; + rs_is_width : integer := 9; + spr_addr_width : integer := 10; + spr_ctl_width : integer := 3; + spr_data_width : integer := 64; + spr_etid_width : integer := 2; + spr_xucr0_init_mod : integer := 0; + state_width : integer := 4; + thdid_width : integer := 4; + tlb_addr_width : natural := 7; + tlb_num_entry : natural := 512; + tlb_num_entry_log2 : natural := 9; + tlb_seq_width : integer := 6; + tlb_tag_width : natural := 110; + tlb_way_width : natural := 168; + tlb_ways : natural := 4; + tlb_word_width : natural := 84; + tlbsel_width : integer := 2; + ttype_width : integer := 4; + vpn_width : integer := 61; + watermark_width : integer := 4; + ws_width : integer := 2; + dc_size : natural := 14; + include_boxes : integer := 1; + l_endian_m : integer := 1; + load_credits : integer := 4; + xu_real_data_add : integer := 42; + st_data_32b_mode : integer := 1; + ac_st_data_32b_mode : integer := 0; + store_credits : integer := 20 + ); + PORT ( + an_ac_back_inv : in std_ulogic; + an_ac_back_inv_addr : in std_ulogic_vector(64-xu_real_data_add to 63); + an_ac_back_inv_lbit : in std_ulogic; + an_ac_back_inv_gs : in std_ulogic; + an_ac_back_inv_ind : in std_ulogic; + an_ac_back_inv_local : in std_ulogic; + an_ac_back_inv_lpar_id : in std_ulogic_vector(0 to lpid_width-1); + an_ac_back_inv_target : in std_ulogic_vector(0 to 4); + an_ac_dcr_act : in std_ulogic; + an_ac_dcr_val : in std_ulogic; + an_ac_dcr_read : in std_ulogic; + an_ac_dcr_etid : in std_ulogic_vector(0 to 1); + an_ac_dcr_data : in std_ulogic_vector(64-(2**regmode) to 63); + an_ac_dcr_done : in std_ulogic; + an_ac_crit_interrupt : in std_ulogic_vector(0 to threads-1); + an_ac_ext_interrupt : in std_ulogic_vector(0 to threads-1); + an_ac_camfence_en_dc : in std_ulogic; + an_ac_flh2l2_gate : in std_ulogic; + an_ac_icbi_ack : in std_ulogic; + an_ac_icbi_ack_thread : in std_ulogic_vector(0 to 1); + an_ac_reld_core_tag : in std_ulogic_vector(0 to 4); + an_ac_reld_data : in std_ulogic_vector(0 to 127); + an_ac_reld_data_vld : in std_ulogic; + an_ac_reld_ecc_err : in std_ulogic; + an_ac_reld_ecc_err_ue : in std_ulogic; + an_ac_reld_qw : in std_ulogic_vector(57 to 59); + an_ac_reld_data_coming : in std_ulogic; + an_ac_reld_ditc : in std_ulogic; + an_ac_reld_crit_qw : in std_ulogic; + an_ac_reld_l1_dump : in std_ulogic; + an_ac_req_ld_pop : in std_ulogic; + an_ac_req_spare_ctrl_a1 : in std_ulogic_vector(0 to 3); + an_ac_req_st_gather : in std_ulogic; + an_ac_req_st_pop : in std_ulogic; + an_ac_req_st_pop_thrd : in std_ulogic_vector(0 to 2); + an_ac_reservation_vld : in std_ulogic_vector(0 to threads-1); + an_ac_sleep_en : in std_ulogic_vector(0 to threads-1); + an_ac_stcx_complete : in std_ulogic_vector(0 to 3); + an_ac_stcx_pass : in std_ulogic_vector(0 to 3); + an_ac_sync_ack : in std_ulogic_vector(0 to 3); + a2_nclk : in clk_logic; + an_ac_abist_mode_dc : in std_ulogic; + an_ac_abist_start_test : in std_ulogic; + an_ac_abst_scan_in : in std_ulogic_vector(0 to 9); + an_ac_ary_nsl_thold_7 : in std_ulogic; + an_ac_atpg_en_dc : in std_ulogic; + an_ac_bcfg_scan_in : in std_ulogic_vector(0 to 4); + an_ac_lbist_ary_wrt_thru_dc : in std_ulogic; + an_ac_ccenable_dc : in std_ulogic; + an_ac_ccflush_dc : in std_ulogic; + an_ac_coreid : in std_ulogic_vector(0 to 7); + an_ac_reset_1_complete : in std_ulogic; + an_ac_reset_2_complete : in std_ulogic; + an_ac_reset_3_complete : in std_ulogic; + an_ac_reset_wd_complete : in std_ulogic; + an_ac_dcfg_scan_in : in std_ulogic_vector(0 to 2); + an_ac_debug_stop : in std_ulogic; + an_ac_external_mchk : in std_ulogic_vector(0 to 3); + an_ac_fce_7 : in std_ulogic; + an_ac_func_nsl_thold_7 : in std_ulogic; + an_ac_func_scan_in : in std_ulogic_vector(0 to 63); + an_ac_func_sl_thold_7 : in std_ulogic; + an_ac_gsd_test_enable_dc : in std_ulogic; + an_ac_gsd_test_acmode_dc : in std_ulogic; + an_ac_gptr_scan_in : in std_ulogic; + an_ac_hang_pulse : in std_ulogic_vector(0 to threads-1); + an_ac_lbist_en_dc : in std_ulogic; + an_ac_lbist_ac_mode_dc : in std_ulogic; + an_ac_lbist_ip_dc : in std_ulogic; + an_ac_malf_alert : in std_ulogic; + an_ac_perf_interrupt : in std_ulogic_vector(0 to threads-1); + an_ac_pm_thread_stop : in std_ulogic_vector(0 to 3); + an_ac_psro_enable_dc : in std_ulogic_vector(0 to 2); + an_ac_regf_scan_in : in std_ulogic_vector(0 to 11); + an_ac_repr_scan_in : in std_ulogic; + an_ac_rtim_sl_thold_7 : in std_ulogic; + an_ac_scan_diag_dc : in std_ulogic; + an_ac_scan_dis_dc_b : in std_ulogic; + an_ac_scan_type_dc : in std_ulogic_vector(0 to 8); + an_ac_scom_cch : in std_ulogic; + an_ac_scom_dch : in std_ulogic; + an_ac_scom_sat_id : in std_ulogic_vector(0 to 3); + an_ac_sg_7 : in std_ulogic; + an_ac_checkstop : in std_ulogic; + an_ac_tb_update_enable : in std_ulogic; + an_ac_tb_update_pulse : in std_ulogic; + an_ac_time_scan_in : in std_ulogic; + ac_an_back_inv_reject : out std_ulogic; + ac_an_box_empty : out std_ulogic_vector(0 to 3); + ac_an_reld_ditc_pop : out std_ulogic_vector(0 to 3); + ac_an_lpar_id : out std_ulogic_vector(0 to lpid_width-1); + ac_an_machine_check : out std_ulogic_vector(0 to threads-1); + ac_an_power_managed : out std_ulogic; + ac_an_req : out std_ulogic; + ac_an_req_endian : out std_ulogic; + ac_an_req_ld_core_tag : out std_ulogic_vector(0 to 4); + ac_an_req_ld_xfr_len : out std_ulogic_vector(0 to 2); + ac_an_req_pwr_token : out std_ulogic; + ac_an_req_ra : out std_ulogic_vector(64-xu_real_data_add to 63); + ac_an_req_spare_ctrl_a0 : out std_ulogic_vector(0 to 3); + ac_an_req_thread : out std_ulogic_vector(0 to 2); + ac_an_req_ttype : out std_ulogic_vector(0 to 5); + ac_an_req_user_defined : out std_ulogic_vector(0 to 3); + ac_an_req_wimg_g : out std_ulogic; + ac_an_req_wimg_i : out std_ulogic; + ac_an_req_wimg_m : out std_ulogic; + ac_an_req_wimg_w : out std_ulogic; + ac_an_rvwinkle_mode : out std_ulogic; + ac_an_st_byte_enbl : out std_ulogic_vector(0 to 15+(st_data_32b_mode*16)); + ac_an_st_data : out std_ulogic_vector(0 to 127+(st_data_32b_mode*128)); + ac_an_st_data_pwr_token : out std_ulogic; + ac_an_fu_bypass_events : out std_ulogic_vector(0 to 7); + ac_an_iu_bypass_events : out std_ulogic_vector(0 to 7); + ac_an_mm_bypass_events : out std_ulogic_vector(0 to 7); + ac_an_lsu_bypass_events : out std_ulogic_vector(0 to 7); + ac_an_debug_bus : out std_ulogic_vector(0 to 87); + ac_an_event_bus : out std_ulogic_vector(0 to 7); + ac_an_trace_triggers : out std_ulogic_vector(0 to 11); + ac_an_abist_done_dc : out std_ulogic; + ac_an_abst_scan_out : out std_ulogic_vector(0 to 9); + ac_an_bcfg_scan_out : out std_ulogic_vector(0 to 4); + ac_an_dcfg_scan_out : out std_ulogic_vector(0 to 2); + ac_an_debug_trigger : out std_ulogic_vector(0 to threads-1); + ac_an_func_scan_out : out std_ulogic_vector(0 to 63); + ac_an_gptr_scan_out : out std_ulogic; + ac_an_pm_thread_running : out std_ulogic_vector(0 to 3); + ac_an_psro_ringsig : out std_ulogic; + ac_an_recov_err : out std_ulogic_vector(0 to 2); + ac_an_regf_scan_out : out std_ulogic_vector(0 to 11); + ac_an_repr_scan_out : out std_ulogic; + ac_an_reset_1_request : out std_ulogic; + ac_an_reset_2_request : out std_ulogic; + ac_an_reset_3_request : out std_ulogic; + ac_an_reset_wd_request : out std_ulogic; + ac_an_scom_cch : out std_ulogic; + ac_an_scom_dch : out std_ulogic; + ac_an_time_scan_out : out std_ulogic; + ac_an_special_attn : out std_ulogic_vector(0 to 3); + ac_an_checkstop : out std_ulogic_vector(0 to 2); + ac_an_local_checkstop : out std_ulogic_vector(0 to 2); + ac_an_trace_error : out std_ulogic; + ac_an_dcr_act : out std_ulogic; + ac_an_dcr_val : out std_ulogic; + ac_an_dcr_read : out std_ulogic; + ac_an_dcr_user : out std_ulogic; + ac_an_dcr_etid : out std_ulogic_vector(0 to 1); + ac_an_dcr_addr : out std_ulogic_vector(11 to 20); + ac_an_dcr_data : out std_ulogic_vector(64-(2**regmode) to 63); + gnd : inout power_logic; + vcs : inout power_logic; + vdd : inout power_logic + ); + -- synopsys translate_off + -- synopsys translate_on +END acq_soft; + +ARCHITECTURE acq_soft OF acq_soft IS + + +signal a2_nclk_copy : clk_logic; +signal bx_pc_err_inbox_ue : std_ulogic; +signal bx_pc_err_outbox_ue : std_ulogic; +signal fu_iu_uc_special : std_ulogic_vector(0 to 3); +signal fu_pc_err_regfile_parity : std_ulogic_vector(0 to 3); +signal fu_pc_err_regfile_ue : std_ulogic_vector(0 to 3); +signal fu_pc_event_data : std_ulogic_vector(0 to 7); +signal fu_pc_ram_data : std_ulogic_vector(0 to 63); +signal fu_pc_ram_done : std_ulogic; +signal fu_xu_ex2_async_block : std_ulogic_vector(0 to 3); +signal fu_xu_ex1_ifar : std_ulogic_vector(62-xu_eff_ifar to 61); +signal fu_xu_ex2_ifar_val : std_ulogic_vector(0 to 3); +signal fu_xu_ex2_ifar_issued : std_ulogic_vector(0 to 3); +signal fu_xu_ex2_store_data : std_ulogic_vector(0 to 63); +signal fu_xu_ex2_store_data_val : std_ulogic; +signal fu_xu_ex3_ap_int_req : std_ulogic_vector(0 to 3); +signal fu_xu_ex3_flush2ucode : std_ulogic_vector(0 to 3); +signal fu_xu_ex2_instr_match : std_ulogic_vector(0 to 3); +signal fu_xu_ex2_instr_type : std_ulogic_vector(0 to 11); +signal fu_xu_ex2_is_ucode : std_ulogic_vector(0 to 3); +signal fu_xu_ex3_n_flush : std_ulogic_vector(0 to 3); +signal fu_xu_ex3_np1_flush : std_ulogic_vector(0 to 3); +signal fu_xu_ex3_regfile_err_det : std_ulogic_vector(0 to 3); +signal fu_xu_ex3_trap : std_ulogic_vector(0 to 3); +signal fu_xu_ex4_cr : std_ulogic_vector(0 to 3); +signal fu_xu_ex4_cr_bf : std_ulogic_vector(0 to 2); +signal fu_xu_ex4_cr_noflush : std_ulogic_vector(0 to 3); +signal fu_xu_ex4_cr_val : std_ulogic_vector(0 to 3); +signal fu_xu_regfile_seq_end : std_ulogic; +signal fu_xu_rf1_act : std_ulogic_vector(0 to 3); +signal fu_bx_slowspr_addr : std_ulogic_vector(0 to 9); +signal fu_bx_slowspr_data : std_ulogic_vector(64-(2**regmode) to 63); +signal fu_bx_slowspr_done : std_ulogic; +signal fu_bx_slowspr_etid : std_ulogic_vector(0 to 1); +signal fu_bx_slowspr_rw : std_ulogic; +signal fu_bx_slowspr_val : std_ulogic; +signal bx_xu_slowspr_addr : std_ulogic_vector(0 to 9); +signal bx_xu_slowspr_data : std_ulogic_vector(64-(2**regmode) to 63); +signal bx_xu_slowspr_done : std_ulogic; +signal bx_xu_slowspr_etid : std_ulogic_vector(0 to 1); +signal bx_xu_slowspr_rw : std_ulogic; +signal bx_xu_slowspr_val : std_ulogic; +signal bx_xu_quiesce : std_ulogic_vector(0 to 3); +signal iu_fu_ex2_n_flush : std_ulogic_vector(0 to 3); +signal iu_fu_is2_tid_decode : std_ulogic_vector(0 to 3); +signal iu_fu_rf0_bypsel : std_ulogic_vector(0 to 5); +signal iu_fu_rf0_fra : std_ulogic_vector(0 to 6); +signal iu_fu_rf0_fra_v : std_ulogic; +signal iu_fu_rf0_frb : std_ulogic_vector(0 to 6); +signal iu_fu_rf0_frb_v : std_ulogic; +signal iu_fu_rf0_frc : std_ulogic_vector(0 to 6); +signal iu_fu_rf0_frc_v : std_ulogic; +signal iu_fu_rf0_frt : std_ulogic_vector(0 to 6); +signal iu_fu_rf0_ifar : eff_ifar; +signal iu_fu_rf0_instr : std_ulogic_vector(0 to 31); +signal iu_fu_rf0_instr_match : std_ulogic; +signal iu_fu_rf0_instr_v : std_ulogic; +signal iu_fu_rf0_is_ucode : std_ulogic; +signal iu_fu_rf0_ucfmul : std_ulogic; +signal iu_fu_rf0_ldst_val : std_ulogic; +signal iu_fu_rf0_ldst_tid : std_ulogic_vector(0 to 1); +signal iu_fu_rf0_ldst_tag : std_ulogic_vector(0 to 8); +signal iu_fu_rf0_str_val : std_ulogic; +signal iu_fu_rf0_tid : std_ulogic_vector(0 to 1); +signal iu_mm_ierat_epn : std_ulogic_vector(0 to 51); +signal iu_mm_ierat_flush : std_ulogic_vector(0 to 3); +signal iu_mm_ierat_mmucr0 : std_ulogic_vector(0 to 17); +signal iu_mm_ierat_mmucr0_we : std_ulogic_vector(0 to 3); +signal iu_mm_ierat_mmucr1 : std_ulogic_vector(0 to 3); +signal iu_mm_ierat_mmucr1_we : std_ulogic; +signal iu_mm_ierat_req : std_ulogic; +signal iu_mm_ierat_snoop_ack : std_ulogic; +signal iu_mm_ierat_thdid : std_ulogic_vector(0 to 3); +signal iu_mm_ierat_tid : std_ulogic_vector(0 to 13); +signal iu_mm_ierat_state : std_ulogic_vector(0 to 3); +signal iu_mm_lmq_empty : std_ulogic; +signal iu_pc_err_icache_parity : std_ulogic; +signal iu_pc_err_icachedir_multihit : std_ulogic; +signal iu_pc_err_icachedir_parity : std_ulogic; +signal iu_pc_err_ucode_illegal : std_ulogic_vector(0 to 3); +signal iu_pc_event_data : std_ulogic_vector(0 to 7); +signal iu_pc_slowspr_addr : std_ulogic_vector(0 to 9); +signal iu_pc_slowspr_data : std_ulogic_vector(64-(2**regmode) to 63); +signal iu_pc_slowspr_done : std_ulogic; +signal iu_pc_slowspr_etid : std_ulogic_vector(0 to 1); +signal iu_pc_slowspr_rw : std_ulogic; +signal iu_pc_slowspr_val : std_ulogic; +signal iu_xu_ex4_tlb_data : std_ulogic_vector(64-(2**regmode) to 63); +signal iu_xu_ierat_ex2_flush_req : std_ulogic_vector(0 to threads-1); +signal iu_xu_ierat_ex3_par_err : std_ulogic_vector(0 to threads-1); +signal iu_xu_ierat_ex4_par_err : std_ulogic_vector(0 to threads-1); +signal iu_xu_is2_axu_instr_type : std_ulogic_vector(0 to 2); +signal iu_xu_is2_axu_ld_or_st : std_ulogic; +signal iu_xu_is2_axu_ldst_extpid : std_ulogic; +signal iu_xu_is2_axu_ldst_forcealign : std_ulogic; +signal iu_xu_is2_axu_ldst_forceexcept : std_ulogic; +signal iu_xu_is2_axu_ldst_indexed : std_ulogic; +signal iu_xu_is2_axu_ldst_size : std_ulogic_vector(0 to 5); +signal iu_xu_is2_axu_ldst_tag : std_ulogic_vector(0 to 8); +signal iu_xu_is2_axu_ldst_update : std_ulogic; +signal iu_xu_is2_axu_mffgpr : std_ulogic; +signal iu_xu_is2_axu_mftgpr : std_ulogic; +signal iu_xu_is2_axu_movedp : std_ulogic; +signal iu_xu_is2_axu_store : std_ulogic; +signal iu_xu_is2_error : std_ulogic_vector(0 to 2); +signal iu_xu_is2_gshare : std_ulogic_vector(0 to 3); +signal iu_xu_is2_ifar : eff_ifar; +signal iu_xu_is2_instr : std_ulogic_vector(0 to 31); +signal iu_xu_is2_is_ucode : std_ulogic; +signal iu_xu_is2_match : std_ulogic; +signal iu_xu_is2_pred_taken_cnt : std_ulogic_vector(0 to 1); +signal iu_xu_is2_pred_update : std_ulogic; +signal iu_xu_is2_s1 : std_ulogic_vector(0 to 5); +signal iu_xu_is2_s1_vld : std_ulogic; +signal iu_xu_is2_s2 : std_ulogic_vector(0 to 5); +signal iu_xu_is2_s2_vld : std_ulogic; +signal iu_xu_is2_s3 : std_ulogic_vector(0 to 5); +signal iu_xu_is2_s3_vld : std_ulogic; +signal iu_xu_is2_ta : std_ulogic_vector(0 to 5); +signal iu_xu_is2_ta_vld : std_ulogic; +signal iu_xu_is2_tid : std_ulogic_vector(0 to 3); +signal iu_xu_is2_ucode_vld : std_ulogic; +signal iu_xu_is2_vld : std_ulogic; +signal iu_xu_quiesce : std_ulogic_vector(0 to threads-1); +signal iu_xu_ra : std_ulogic_vector(real_ifar'left to 59); +signal iu_xu_request : std_ulogic; +signal iu_xu_thread : std_ulogic_vector(0 to 3); +signal iu_xu_userdef : std_ulogic_vector(0 to 3); +signal iu_xu_wimge : std_ulogic_vector(0 to 4); +signal mm_iu_ierat_mmucr0_0 : std_ulogic_vector(0 to 19); +signal mm_iu_ierat_mmucr0_1 : std_ulogic_vector(0 to 19); +signal mm_iu_ierat_mmucr0_2 : std_ulogic_vector(0 to 19); +signal mm_iu_ierat_mmucr0_3 : std_ulogic_vector(0 to 19); +signal mm_iu_ierat_mmucr1 : std_ulogic_vector(0 to 8); +signal mm_iu_ierat_pid0 : std_ulogic_vector(0 to 13); +signal mm_iu_ierat_pid1 : std_ulogic_vector(0 to 13); +signal mm_iu_ierat_pid2 : std_ulogic_vector(0 to 13); +signal mm_iu_ierat_pid3 : std_ulogic_vector(0 to 13); +signal mm_iu_ierat_rel_data : std_ulogic_vector(0 to 131); +signal mm_iu_ierat_rel_val : std_ulogic_vector(0 to 4); +signal mm_iu_ierat_snoop_attr : std_ulogic_vector(0 to 25); +signal mm_iu_ierat_snoop_coming : std_ulogic; +signal mm_iu_ierat_snoop_val : std_ulogic; +signal mm_iu_ierat_snoop_vpn : std_ulogic_vector(52-epn_width to 51); +signal mm_iu_slowspr_addr : std_ulogic_vector(0 to 9); +signal mm_iu_slowspr_data : std_ulogic_vector(64-spr_data_width to 63); +signal mm_iu_slowspr_done : std_ulogic; +signal mm_iu_slowspr_etid : std_ulogic_vector(0 to 1); +signal mm_iu_slowspr_rw : std_ulogic; +signal mm_iu_slowspr_val : std_ulogic; +signal xu_pc_err_mcsr_summary : std_ulogic_vector(0 to threads-1); +signal xu_pc_err_ierat_parity : std_ulogic; +signal xu_pc_err_derat_parity : std_ulogic; +signal xu_pc_err_tlb_parity : std_ulogic; +signal xu_pc_err_tlb_lru_parity : std_ulogic; +signal xu_pc_err_ierat_multihit : std_ulogic; +signal xu_pc_err_derat_multihit : std_ulogic; +signal xu_pc_err_tlb_multihit : std_ulogic; +signal xu_pc_err_ext_mchk : std_ulogic; +signal xu_pc_err_local_snoop_reject : std_ulogic; +signal mm_xu_derat_mmucr0_0 : std_ulogic_vector(0 to 19); +signal mm_xu_derat_mmucr0_1 : std_ulogic_vector(0 to 19); +signal mm_xu_derat_mmucr0_2 : std_ulogic_vector(0 to 19); +signal mm_xu_derat_mmucr0_3 : std_ulogic_vector(0 to 19); +signal mm_xu_derat_mmucr1 : std_ulogic_vector(0 to 9); +signal mm_xu_derat_pid0 : std_ulogic_vector(0 to 13); +signal mm_xu_derat_pid1 : std_ulogic_vector(0 to 13); +signal mm_xu_derat_pid2 : std_ulogic_vector(0 to 13); +signal mm_xu_derat_pid3 : std_ulogic_vector(0 to 13); +signal mm_xu_derat_rel_data : std_ulogic_vector(0 to 131); +signal mm_xu_derat_rel_val : std_ulogic_vector(0 to 4); +signal mm_xu_derat_snoop_attr : std_ulogic_vector(0 to 25); +signal mm_xu_derat_snoop_coming : std_ulogic; +signal mm_xu_derat_snoop_val : std_ulogic; +signal mm_xu_derat_snoop_vpn : std_ulogic_vector(52-epn_width to 51); +signal mm_iu_barrier_done : std_ulogic_vector(0 to 3); +signal mm_xu_eratmiss_done : std_ulogic_vector(0 to 3); +signal mm_xu_esr_pt : std_ulogic_vector(0 to 3); +signal mm_xu_esr_data : std_ulogic_vector(0 to 3); +signal mm_xu_esr_epid : std_ulogic_vector(0 to 3); +signal mm_xu_esr_st : std_ulogic_vector(0 to 3); +signal mm_xu_ex3_flush_req : std_ulogic_vector(0 to 3); +signal xu_mm_rf1_is_tlbsxr : std_ulogic; +signal mm_xu_hold_done : std_ulogic_vector(0 to 3); +signal mm_xu_hold_req : std_ulogic_vector(0 to 3); +signal mm_xu_hv_priv : std_ulogic_vector(0 to threads-1); +signal mm_xu_illeg_instr : std_ulogic_vector(0 to threads-1); +signal mm_xu_lru_par_err : std_ulogic_vector(0 to 3); +signal mm_xu_lrat_miss : std_ulogic_vector(0 to 3); +signal mm_xu_local_snoop_reject : std_ulogic_vector(0 to thdid_width-1); +signal mm_xu_lsu_addr : std_ulogic_vector(64-real_addr_width to 63); +signal mm_xu_lsu_lpid : std_ulogic_vector(0 to 7); +signal mm_xu_lsu_lpidr : std_ulogic_vector(0 to 7); +signal mm_xu_lsu_gs : std_ulogic; +signal mm_xu_lsu_ind : std_ulogic; +signal mm_xu_lsu_lbit : std_ulogic; +signal mm_xu_lsu_req : std_ulogic_vector(0 to 3); +signal mm_xu_lsu_ttype : std_ulogic_vector(0 to 1); +signal mm_xu_lsu_u : std_ulogic_vector(0 to 3); +signal mm_xu_lsu_wimge : std_ulogic_vector(0 to 4); +signal mm_xu_pt_fault : std_ulogic_vector(0 to 3); +signal mm_xu_quiesce : std_ulogic_vector(0 to threads-1); +signal mm_xu_tlb_inelig : std_ulogic_vector(0 to 3); +signal mm_xu_tlb_miss : std_ulogic_vector(0 to 3); +signal mm_xu_tlb_multihit_err : std_ulogic_vector(0 to 3); +signal mm_xu_tlb_par_err : std_ulogic_vector(0 to 3); +signal mm_xu_cr0_eq : std_ulogic_vector(0 to 3); +signal mm_xu_cr0_eq_valid : std_ulogic_vector(0 to 3); +signal pc_bx_inj_inbox_ecc : std_ulogic; +signal pc_bx_inj_outbox_ecc : std_ulogic; +signal pc_fu_abst_sl_thold_3 : std_ulogic; +signal pc_fu_abst_slp_sl_thold_3 : std_ulogic; +signal pc_fu_ary_nsl_thold_3 : std_ulogic; +signal pc_fu_ary_slp_nsl_thold_3 : std_ulogic; +signal pc_fu_cfg_sl_thold_3 : std_ulogic; +signal pc_fu_cfg_slp_sl_thold_3 : std_ulogic; +signal pc_bx_debug_mux1_ctrls : std_ulogic_vector(0 to 15); +signal pc_fu_debug_mux1_ctrls : std_ulogic_vector(0 to 15); +signal pc_fu_fce_3 : std_ulogic; +signal pc_fu_func_nsl_thold_3 : std_ulogic; +signal pc_fu_func_sl_thold_3 : std_ulogic_vector(0 to 1); +signal pc_fu_func_slp_nsl_thold_3 : std_ulogic; +signal pc_fu_func_slp_sl_thold_3 : std_ulogic_vector(0 to 1); +signal pc_fu_gptr_sl_thold_3 : std_ulogic; +signal pc_fu_ram_mode : std_ulogic; +signal pc_fu_ram_thread : std_ulogic_vector(0 to 1); +signal pc_fu_repr_sl_thold_3 : std_ulogic; +signal pc_fu_sg_3 : std_ulogic_vector(0 to 1); +signal pc_fu_slowspr_addr : std_ulogic_vector(0 to 9); +signal pc_fu_slowspr_data : std_ulogic_vector(64-(2**regmode) to 63); +signal pc_fu_slowspr_done : std_ulogic; +signal pc_fu_slowspr_etid : std_ulogic_vector(0 to 1); +signal pc_fu_slowspr_rw : std_ulogic; +signal pc_fu_slowspr_val : std_ulogic; +signal pc_bx_trace_bus_enable : std_ulogic; +signal pc_fu_time_sl_thold_3 : std_ulogic; +signal pc_fu_trace_bus_enable : std_ulogic; +signal pc_iu_gptr_sl_thold_4 : std_ulogic; +signal pc_iu_time_sl_thold_4 : std_ulogic; +signal pc_iu_repr_sl_thold_4 : std_ulogic; +signal pc_iu_abst_sl_thold_4 : std_ulogic; +signal pc_iu_abst_slp_sl_thold_4 : std_ulogic; +signal pc_iu_bolt_sl_thold_4 : std_ulogic; +signal pc_iu_regf_slp_sl_thold_4 : std_ulogic; +signal pc_iu_func_sl_thold_4 : std_ulogic; +signal pc_iu_func_slp_sl_thold_4 : std_ulogic; +signal pc_iu_cfg_sl_thold_4 : std_ulogic; +signal pc_iu_cfg_slp_sl_thold_4 : std_ulogic; +signal pc_iu_func_nsl_thold_4 : std_ulogic; +signal pc_iu_func_slp_nsl_thold_4 : std_ulogic; +signal pc_iu_ary_nsl_thold_4 : std_ulogic; +signal pc_iu_ary_slp_nsl_thold_4 : std_ulogic; +signal pc_iu_sg_4 : std_ulogic; +signal pc_iu_fce_4 : std_ulogic; +signal pc_iu_debug_mux1_ctrls : std_ulogic_vector(0 to 15); +signal pc_iu_debug_mux2_ctrls : std_ulogic_vector(0 to 15); +signal pc_iu_init_reset : std_ulogic; +signal pc_iu_inj_icache_parity : std_ulogic; +signal pc_iu_inj_icachedir_parity : std_ulogic; +signal pc_iu_inj_icachedir_multihit : std_ulogic; +signal pc_iu_ram_force_cmplt : std_ulogic; +signal pc_iu_ram_instr : std_ulogic_vector(0 to 31); +signal pc_iu_ram_instr_ext : std_ulogic_vector(0 to 3); +signal pc_iu_ram_mode : std_ulogic; +signal pc_iu_ram_thread : std_ulogic_vector(0 to 1); +signal pc_iu_trace_bus_enable : std_ulogic; +signal pc_xu_abst_sl_thold_3 : std_ulogic; +signal pc_xu_abst_slp_sl_thold_3 : std_ulogic; +signal pc_xu_regf_sl_thold_3 : std_ulogic; +signal pc_xu_regf_slp_sl_thold_3 : std_ulogic; +signal pc_xu_ary_nsl_thold_3 : std_ulogic; +signal pc_xu_ary_slp_nsl_thold_3 : std_ulogic; +signal pc_xu_cache_par_err_event : std_ulogic; +signal pc_xu_cfg_sl_thold_3 : std_ulogic; +signal pc_xu_cfg_slp_sl_thold_3 : std_ulogic; +signal pc_xu_dbg_action : std_ulogic_vector(0 to 11); +signal pc_xu_decrem_dis_on_stop : std_ulogic; +signal spr_pvr_version_dc : std_ulogic_vector(8 to 15); +signal spr_pvr_revision_dc : std_ulogic_vector(12 to 15); +signal xu_pc_spr_ccr0_we : std_ulogic_vector(0 to 3); +signal xu_pc_spr_ccr0_pme : std_ulogic_vector(0 to 1); +signal pc_xu_debug_mux1_ctrls : std_ulogic_vector(0 to 15); +signal pc_xu_debug_mux2_ctrls : std_ulogic_vector(0 to 15); +signal pc_xu_debug_mux3_ctrls : std_ulogic_vector(0 to 15); +signal pc_xu_debug_mux4_ctrls : std_ulogic_vector(0 to 15); +signal pc_xu_extirpts_dis_on_stop : std_ulogic; +signal pc_xu_fce_3 : std_ulogic_vector(0 to 1); +signal pc_xu_force_ude : std_ulogic_vector(0 to 3); +signal pc_xu_func_nsl_thold_3 : std_ulogic; +signal pc_xu_func_sl_thold_3 : std_ulogic_vector(0 to 4); +signal pc_xu_func_slp_nsl_thold_3 : std_ulogic; +signal pc_xu_func_slp_sl_thold_3 : std_ulogic_vector(0 to 4); +signal pc_xu_gptr_sl_thold_3 : std_ulogic; +signal pc_xu_init_reset : std_ulogic; +signal pc_xu_inj_dcache_parity : std_ulogic; +signal pc_xu_inj_dcachedir_parity : std_ulogic; +signal pc_xu_inj_llbust_attempt : std_ulogic_vector(0 to 3); +signal pc_xu_inj_llbust_failed : std_ulogic_vector(0 to 3); +signal pc_xu_inj_sprg_ecc : std_ulogic_vector(0 to 3); +signal pc_xu_inj_regfile_parity : std_ulogic_vector(0 to 3); +signal pc_xu_inj_wdt_reset : std_ulogic_vector(0 to 3); +signal pc_xu_inj_dcachedir_multihit : std_ulogic; +signal pc_xu_msrovride_enab : std_ulogic; +signal pc_xu_msrovride_pr : std_ulogic; +signal pc_xu_msrovride_gs : std_ulogic; +signal pc_xu_ram_mode : std_ulogic; +signal pc_xu_ram_thread : std_ulogic_vector(0 to 1); +signal pc_xu_ram_execute : std_ulogic; +signal pc_xu_repr_sl_thold_3 : std_ulogic; +signal pc_xu_reset_1_complete : std_ulogic; +signal pc_xu_reset_2_complete : std_ulogic; +signal pc_xu_reset_3_complete : std_ulogic; +signal pc_xu_reset_wd_complete : std_ulogic; +signal pc_xu_sg_3 : std_ulogic_vector(0 to 4); +signal pc_xu_step : std_ulogic_vector(0 to 3); +signal pc_xu_stop : std_ulogic_vector(0 to 3); +signal pc_xu_timebase_dis_on_stop : std_ulogic; +signal pc_xu_time_sl_thold_3 : std_ulogic; +signal pc_xu_trace_bus_enable : std_ulogic; +signal xu_n_is2_flush : std_ulogic_vector(0 to threads-1); +signal xu_n_rf0_flush : std_ulogic_vector(0 to threads-1); +signal xu_n_rf1_flush : std_ulogic_vector(0 to threads-1); +signal xu_n_ex1_flush : std_ulogic_vector(0 to threads-1); +signal xu_n_ex2_flush : std_ulogic_vector(0 to threads-1); +signal xu_n_ex3_flush : std_ulogic_vector(0 to threads-1); +signal xu_n_ex4_flush : std_ulogic_vector(0 to threads-1); +signal xu_n_ex5_flush : std_ulogic_vector(0 to threads-1); +signal xu_s_rf1_flush : std_ulogic_vector(0 to threads-1); +signal xu_s_ex1_flush : std_ulogic_vector(0 to threads-1); +signal xu_s_ex2_flush : std_ulogic_vector(0 to threads-1); +signal xu_s_ex3_flush : std_ulogic_vector(0 to threads-1); +signal xu_s_ex4_flush : std_ulogic_vector(0 to threads-1); +signal xu_s_ex5_flush : std_ulogic_vector(0 to threads-1); +signal xu_wu_rf1_flush : std_ulogic_vector(0 to threads-1); +signal xu_wu_ex1_flush : std_ulogic_vector(0 to threads-1); +signal xu_wu_ex2_flush : std_ulogic_vector(0 to threads-1); +signal xu_wu_ex3_flush : std_ulogic_vector(0 to threads-1); +signal xu_wu_ex4_flush : std_ulogic_vector(0 to threads-1); +signal xu_wu_ex5_flush : std_ulogic_vector(0 to threads-1); +signal xu_wl_rf1_flush : std_ulogic_vector(0 to threads-1); +signal xu_wl_ex1_flush : std_ulogic_vector(0 to threads-1); +signal xu_wl_ex2_flush : std_ulogic_vector(0 to threads-1); +signal xu_wl_ex3_flush : std_ulogic_vector(0 to threads-1); +signal xu_wl_ex4_flush : std_ulogic_vector(0 to threads-1); +signal xu_wl_ex5_flush : std_ulogic_vector(0 to threads-1); +signal xu_fu_ccr2_ap : std_ulogic_vector(0 to threads-1); +signal xu_fu_ex3_eff_addr : std_ulogic_vector(59 to 63); +signal xu_fu_ex6_load_data : std_ulogic_vector(0 to 255); +signal xu_fu_ex5_load_le : std_ulogic; +signal xu_fu_ex5_load_tag : std_ulogic_vector(0 to 8); +signal xu_fu_ex5_load_val : std_ulogic_vector(0 to threads-1); +signal xu_fu_ex5_reload_val : std_ulogic; +signal xu_fu_msr_fp : std_ulogic_vector(0 to 3); +signal xu_fu_msr_pr : std_ulogic_vector(0 to 3); +signal xu_fu_msr_gs : std_ulogic_vector(0 to 3); +signal xu_fu_msr_spv : std_ulogic_vector(0 to threads-1); +signal xu_fu_regfile_seq_beg : std_ulogic; +signal xu_iu_complete_qentry : std_ulogic_vector(0 to lmq_entries-1); +signal xu_iu_complete_target_type : std_ulogic_vector(0 to 1); +signal xu_iu_complete_tid : std_ulogic_vector(0 to 3); +signal xu_iu_ex1_ra_entry : std_ulogic_vector(8 to 11); +signal xu_iu_ex1_rb : std_ulogic_vector(64-(2**regmode) to 51); +signal xu_iu_ex1_rs_is : std_ulogic_vector(0 to 8); +signal xu_iu_ex5_bclr : std_ulogic; +signal xu_iu_ex5_bh : std_ulogic_vector(0 to 1); +signal xu_iu_ex5_br_hist : std_ulogic_vector(0 to 1); +signal xu_iu_ex5_br_taken : std_ulogic; +signal xu_iu_ex5_br_update : std_ulogic; +signal xu_iu_ex5_getNIA : std_ulogic; +signal xu_iu_ex5_gshare : std_ulogic_vector(0 to 3); +signal xu_iu_ex5_ifar : std_ulogic_vector(62-xu_eff_ifar to 61); +signal xu_iu_ex5_lk : std_ulogic; +signal xu_iu_ex5_ppc_cpl : std_ulogic_vector(0 to 3); +signal xu_iu_ex4_loadmiss_qentry : std_ulogic_vector(0 to lmq_entries-1); +signal xu_iu_ex4_loadmiss_target : std_ulogic_vector(0 to 8); +signal xu_iu_ex4_loadmiss_target_type: std_ulogic_vector(0 to 1); +signal xu_iu_ex4_loadmiss_tid : std_ulogic_vector(0 to 3); +signal xu_iu_ex4_rs_data : std_ulogic_vector(64-(2**regmode) to 63); +signal xu_iu_ex5_tid : std_ulogic_vector(0 to threads-1); +signal xu_iu_ex5_val : std_ulogic; +signal xu_iu_ex5_loadmiss_qentry : std_ulogic_vector(0 to lmq_entries-1); +signal xu_iu_ex5_loadmiss_target : std_ulogic_vector(0 to 8); +signal xu_iu_ex5_loadmiss_target_type: std_ulogic_vector(0 to 1); +signal xu_iu_ex5_loadmiss_tid : std_ulogic_vector(0 to 3); +signal xu_iu_ex6_icbi_val : std_ulogic_vector(0 to threads-1); +signal xu_iu_ex6_icbi_addr : std_ulogic_vector(64-xu_real_data_add to 57); +signal xu_iu_ex6_pri : std_ulogic_vector(0 to 2); +signal xu_iu_ex6_pri_val : std_ulogic_vector(0 to 3); +signal xu_iu_flush_2ucode : std_ulogic_vector(0 to 3); +signal xu_iu_flush_2ucode_type : std_ulogic_vector(0 to 3); +signal xu_iu_hid_mmu_mode : std_ulogic; +signal xu_iu_xucr0_rel : std_ulogic; +signal xu_iu_ici : std_ulogic; +signal xu_iu_iu0_flush_ifar0 : std_ulogic_vector(62-xu_eff_ifar to 61); +signal xu_iu_iu0_flush_ifar1 : std_ulogic_vector(62-xu_eff_ifar to 61); +signal xu_iu_iu0_flush_ifar2 : std_ulogic_vector(62-xu_eff_ifar to 61); +signal xu_iu_iu0_flush_ifar3 : std_ulogic_vector(62-xu_eff_ifar to 61); +signal xu_iu_larx_done_tid : std_ulogic_vector(0 to 3); +signal xu_iu_membar_tid : std_ulogic_vector(0 to 3); +signal xu_iu_msr_cm : std_ulogic_vector(0 to threads-1); +signal xu_iu_msr_gs : std_ulogic_vector(0 to 3); +signal xu_iu_msr_hv : std_ulogic_vector(0 to threads-1); +signal xu_iu_msr_is : std_ulogic_vector(0 to threads-1); +signal xu_iu_msr_pr : std_ulogic_vector(0 to threads-1); +signal xu_iu_multdiv_done : std_ulogic_vector(0 to threads-1); +signal xu_iu_need_hole : std_ulogic; +signal xu_iu_raise_iss_pri : std_ulogic_vector(0 to 3); +signal xu_iu_ram_issue : std_ulogic_vector(0 to threads-1); +signal xu_iu_ex1_is_csync : std_ulogic; +signal xu_iu_ex1_is_isync : std_ulogic; +signal xu_iu_rf1_is_eratilx : std_ulogic; +signal xu_iu_rf1_is_eratre : std_ulogic; +signal xu_iu_rf1_is_eratsx : std_ulogic; +signal xu_iu_rf1_is_eratwe : std_ulogic; +signal xu_iu_rf1_val : std_ulogic_vector(0 to 3); +signal xu_iu_rf1_ws : std_ulogic_vector(0 to 1); +signal xu_iu_rf1_t : std_ulogic_vector(0 to 2); +signal xu_iu_run_thread : std_ulogic_vector(0 to 3); +signal xu_iu_set_barr_tid : std_ulogic_vector(0 to 3); +signal xu_iu_single_instr_mode : std_ulogic_vector(0 to threads-1); +signal xu_iu_slowspr_done : std_ulogic_vector(0 to 3); +signal xu_iu_spr_ccr2_en_dcr : std_ulogic; +signal xu_iu_spr_ccr2_ifratsc : std_ulogic_vector(0 to 8); +signal xu_iu_spr_ccr2_ifrat : std_ulogic; +signal xu_bx_ccr2_en_ditc : std_ulogic; +signal xu_iu_spr_xer0 : std_ulogic_vector(57 to 63); +signal xu_iu_spr_xer1 : std_ulogic_vector(57 to 63); +signal xu_iu_spr_xer2 : std_ulogic_vector(57 to 63); +signal xu_iu_spr_xer3 : std_ulogic_vector(57 to 63); +signal xu_iu_uc_flush_ifar0 : std_ulogic_vector(62-uc_ifar to 61); +signal xu_iu_uc_flush_ifar1 : std_ulogic_vector(62-uc_ifar to 61); +signal xu_iu_uc_flush_ifar2 : std_ulogic_vector(62-uc_ifar to 61); +signal xu_iu_uc_flush_ifar3 : std_ulogic_vector(62-uc_ifar to 61); +signal xu_iu_ucode_restart : std_ulogic_vector(0 to 3); +signal xu_mm_derat_epn : std_ulogic_vector(64-rs_data_width to 51); +signal xu_mm_derat_lpid : std_ulogic_vector(0 to lpid_width-1); +signal xu_mm_derat_mmucr0 : std_ulogic_vector(0 to 17); +signal xu_mm_derat_mmucr0_we : std_ulogic_vector(0 to 3); +signal xu_mm_derat_mmucr1 : std_ulogic_vector(0 to 4); +signal xu_mm_derat_mmucr1_we : std_ulogic; +signal xu_mm_derat_req : std_ulogic; +signal xu_mm_derat_snoop_ack : std_ulogic; +signal xu_mm_derat_thdid : std_ulogic_vector(0 to 3); +signal xu_mm_derat_tid : std_ulogic_vector(0 to pid_width-1); +signal xu_mm_derat_ttype : std_ulogic_vector(0 to 1); +signal xu_mm_derat_state : std_ulogic_vector(0 to 3); +signal xu_mm_ex2_eff_addr : std_ulogic_vector(64-rs_data_width to 63); +signal xu_mm_ex1_rs_is : std_ulogic_vector(0 to 8); +signal xu_mm_ex4_flush : std_ulogic_vector(0 to thdid_width-1); +signal xu_mm_ex5_flush : std_ulogic_vector(0 to thdid_width-1); +signal xu_mm_ex5_perf_dtlb : std_ulogic_vector(0 to thdid_width-1); +signal xu_mm_ex5_perf_itlb : std_ulogic_vector(0 to thdid_width-1); +signal xu_mm_hid_mmu_mode : std_ulogic; +signal xu_mm_hold_ack : std_ulogic_vector(0 to thdid_width-1); +signal xu_mm_ierat_flush : std_ulogic_vector(0 to threads-1); +signal xu_mm_ierat_miss : std_ulogic_vector(0 to threads-1); +signal xu_mm_lmq_stq_empty : std_ulogic; +signal xu_mm_lsu_token : std_ulogic; +signal xu_mm_msr_cm : std_ulogic_vector(0 to threads-1); +signal xu_mm_msr_ds : std_ulogic_vector(0 to threads-1); +signal xu_mm_msr_gs : std_ulogic_vector(0 to threads-1); +signal xu_mm_msr_is : std_ulogic_vector(0 to threads-1); +signal xu_mm_msr_pr : std_ulogic_vector(0 to threads-1); +signal xu_mm_ex1_is_csync : std_ulogic; +signal xu_mm_ex1_is_isync : std_ulogic; +signal xu_mm_rf1_is_eratilx : std_ulogic; +signal xu_mm_rf1_is_erativax : std_ulogic; +signal xu_mm_rf1_is_tlbilx : std_ulogic; +signal xu_mm_rf1_is_tlbivax : std_ulogic; +signal xu_mm_rf1_is_tlbre : std_ulogic; +signal xu_mm_rf1_is_tlbsx : std_ulogic; +signal xu_mm_rf1_is_tlbsrx : std_ulogic; +signal xu_mm_rf1_is_tlbwe : std_ulogic; +signal xu_mm_rf1_val : std_ulogic_vector(0 to 3); +signal xu_mm_rf1_t : std_ulogic_vector(0 to 2); +signal xu_mm_slowspr_addr : std_ulogic_vector(0 to 9); +signal xu_mm_slowspr_data : std_ulogic_vector(64-(2**regmode) to 63); +signal xu_mm_slowspr_done : std_ulogic; +signal xu_mm_slowspr_etid : std_ulogic_vector(0 to 1); +signal xu_mm_slowspr_rw : std_ulogic; +signal xu_mm_slowspr_val : std_ulogic; +signal xu_mm_spr_epcr_dgtmi : std_ulogic_vector(0 to threads-1); +signal xu_mm_spr_epcr_dmiuh : std_ulogic_vector(0 to thdid_width-1); +signal xu_pc_err_attention_instr : std_ulogic_vector(0 to 3); +signal xu_pc_err_dcache_parity : std_ulogic; +signal xu_pc_err_dcachedir_parity : std_ulogic; +signal xu_pc_err_dcachedir_multihit : std_ulogic; +signal xu_pc_err_debug_event : std_ulogic_vector(0 to 3); +signal xu_pc_err_ditc_overrun : std_ulogic; +signal bx_pc_err_inbox_ecc : std_ulogic; +signal xu_pc_err_invld_reld : std_ulogic; +signal bx_pc_err_outbox_ecc : std_ulogic; +signal xu_pc_err_l2intrf_ecc : std_ulogic; +signal xu_pc_err_l2intrf_ue : std_ulogic; +signal xu_pc_err_l2credit_overrun : std_ulogic; +signal xu_pc_err_llbust_attempt : std_ulogic_vector(0 to 3); +signal xu_pc_err_llbust_failed : std_ulogic_vector(0 to 3); +signal xu_pc_err_nia_miscmpr : std_ulogic_vector(0 to 3); +signal xu_pc_err_regfile_parity : std_ulogic_vector(0 to 3); +signal xu_pc_err_regfile_ue : std_ulogic_vector(0 to 3); +signal xu_pc_err_sprg_ecc : std_ulogic_vector(0 to 3); +signal xu_pc_err_sprg_ue : std_ulogic_vector(0 to 3); +signal xu_pc_err_wdt_reset : std_ulogic_vector(0 to 3); +signal xu_pc_event_data : std_ulogic_vector(0 to 7); +signal xu_pc_lsu_event_data : std_ulogic_vector(0 to 7); +signal xu_pc_ram_data : std_ulogic_vector(64-(2**regmode) to 63); +signal xu_pc_ram_done : std_ulogic; +signal xu_pc_ram_interrupt : std_ulogic; +signal xu_pc_running : std_ulogic_vector(0 to 3); +signal xu_pc_step_done : std_ulogic_vector(0 to threads-1); +signal xu_pc_stop_dbg_event : std_ulogic_vector(0 to 3); +signal pc_fu_ccflush_dc : std_ulogic; +signal pc_iu_ccflush_dc : std_ulogic; +signal pc_xu_ccflush_dc : std_ulogic; +signal pc_bx_ccflush_dc : std_ulogic; +signal pc_fu_event_count_mode : std_ulogic_vector(0 to 2); +signal pc_iu_event_count_mode : std_ulogic_vector(0 to 2); +signal pc_xu_event_count_mode : std_ulogic_vector(0 to 2); +signal pc_fu_inj_regfile_parity : std_ulogic_vector(0 to 3); +signal pc_fu_instr_trace_mode : std_ulogic; +signal pc_fu_instr_trace_tid : std_ulogic_vector(0 to 1); +signal pc_xu_instr_trace_mode : std_ulogic; +signal pc_xu_instr_trace_tid : std_ulogic_vector(0 to 1); +signal pc_xu_ram_flush_thread : std_ulogic; +signal pc_bx_abist_di_0 : std_ulogic_vector(0 to 3); +signal pc_bx_abist_ena_dc : std_ulogic; +signal pc_bx_abist_g8t1p_renb_0 : std_ulogic; +signal pc_bx_abist_g8t_bw_0 : std_ulogic; +signal pc_bx_abist_g8t_bw_1 : std_ulogic; +signal pc_bx_abist_g8t_dcomp : std_ulogic_vector(0 to 3); +signal pc_bx_abist_g8t_wenb : std_ulogic; +signal pc_bx_abist_raddr_0 : std_ulogic_vector(0 to 9); +signal pc_bx_abist_raw_dc_b : std_ulogic; +signal pc_bx_abist_waddr_0 : std_ulogic_vector(0 to 9); +signal pc_bx_abist_wl64_comp_ena : std_ulogic; +signal pc_fu_abist_di_0 : std_ulogic_vector(0 to 3); +signal pc_fu_abist_di_1 : std_ulogic_vector(0 to 3); +signal pc_fu_abist_ena_dc : std_ulogic; +signal pc_fu_abist_grf_renb_0 : std_ulogic; +signal pc_fu_abist_grf_renb_1 : std_ulogic; +signal pc_fu_abist_grf_wenb_0 : std_ulogic; +signal pc_fu_abist_grf_wenb_1 : std_ulogic; +signal pc_fu_abist_raddr_0 : std_ulogic_vector(0 to 9); +signal pc_fu_abist_raddr_1 : std_ulogic_vector(0 to 9); +signal pc_fu_abist_raw_dc_b : std_ulogic; +signal pc_fu_abist_waddr_0 : std_ulogic_vector(0 to 9); +signal pc_fu_abist_waddr_1 : std_ulogic_vector(0 to 9); +signal pc_fu_abist_wl144_comp_ena : std_ulogic; +signal pc_iu_abist_dcomp_g6t_2r : std_ulogic_vector(0 to 3); +signal pc_iu_abist_di_0 : std_ulogic_vector(0 to 3); +signal pc_iu_abist_di_g6t_2r : std_ulogic_vector(0 to 3); +signal pc_iu_abist_ena_dc : std_ulogic; +signal pc_iu_abist_g6t_bw : std_ulogic_vector(0 to 1); +signal pc_iu_abist_g6t_r_wb : std_ulogic; +signal pc_iu_abist_g8t1p_renb_0 : std_ulogic; +signal pc_iu_abist_g8t_bw_0 : std_ulogic; +signal pc_iu_abist_g8t_bw_1 : std_ulogic; +signal pc_iu_abist_g8t_dcomp : std_ulogic_vector(0 to 3); +signal pc_iu_abist_g8t_wenb : std_ulogic; +signal pc_iu_abist_raddr_0 : std_ulogic_vector(0 to 9); +signal pc_iu_abist_raw_dc_b : std_ulogic; +signal pc_iu_abist_waddr_0 : std_ulogic_vector(0 to 9); +signal pc_iu_abist_wl128_comp_ena : std_ulogic; +signal pc_iu_abist_wl256_comp_ena : std_ulogic; +signal pc_iu_abist_wl64_comp_ena : std_ulogic; +signal pc_xu_abist_dcomp_g6t_2r : std_ulogic_vector(0 to 3); +signal pc_xu_abist_di_0 : std_ulogic_vector(0 to 3); +signal pc_xu_abist_di_1 : std_ulogic_vector(0 to 3); +signal pc_xu_abist_di_g6t_2r : std_ulogic_vector(0 to 3); +signal pc_xu_abist_ena_dc : std_ulogic; +signal pc_xu_abist_g6t_bw : std_ulogic_vector(0 to 1); +signal pc_xu_abist_g6t_r_wb : std_ulogic; +signal pc_xu_abist_g8t1p_renb_0 : std_ulogic; +signal pc_xu_abist_g8t_bw_0 : std_ulogic; +signal pc_xu_abist_g8t_bw_1 : std_ulogic; +signal pc_xu_abist_g8t_dcomp : std_ulogic_vector(0 to 3); +signal pc_xu_abist_g8t_wenb : std_ulogic; +signal pc_xu_abist_grf_renb_0 : std_ulogic; +signal pc_xu_abist_grf_renb_1 : std_ulogic; +signal pc_xu_abist_grf_wenb_0 : std_ulogic; +signal pc_xu_abist_grf_wenb_1 : std_ulogic; +signal pc_xu_abist_raddr_0 : std_ulogic_vector(0 to 9); +signal pc_xu_abist_raddr_1 : std_ulogic_vector(0 to 9); +signal pc_xu_abist_raw_dc_b : std_ulogic; +signal pc_xu_abist_waddr_0 : std_ulogic_vector(0 to 9); +signal pc_xu_abist_waddr_1 : std_ulogic_vector(0 to 9); +signal pc_xu_abist_wl144_comp_ena : std_ulogic; +signal pc_xu_abist_wl32_comp_ena : std_ulogic; +signal pc_xu_abist_wl512_comp_ena : std_ulogic; +signal xu_bx_ex1_mtdp_val : std_ulogic; +signal xu_bx_ex1_mfdp_val : std_ulogic; +signal xu_bx_ex1_ipc_thrd : std_ulogic_vector(0 to 1); +signal xu_bx_ex2_ipc_ba : std_ulogic_vector(0 to 4); +signal xu_bx_ex2_ipc_sz : std_ulogic_vector(0 to 1); +signal xu_bx_ex4_256st_data : std_ulogic_vector(128 to 255); +signal bx_xu_ex4_mtdp_cr_status : std_ulogic; +signal bx_xu_ex4_mfdp_cr_status : std_ulogic; +signal bx_xu_ex5_dp_data : std_ulogic_vector(0 to 127); +signal bx_lsu_ob_pwr_tok : std_ulogic; +signal bx_lsu_ob_req_val : std_ulogic; +signal bx_lsu_ob_ditc_val : std_ulogic; +signal bx_lsu_ob_thrd : std_ulogic_vector(0 to 1); +signal bx_lsu_ob_qw : std_ulogic_vector(58 to 59); +signal bx_lsu_ob_dest : std_ulogic_vector(0 to 14); +signal bx_lsu_ob_data : std_ulogic_vector(0 to 127); +signal bx_lsu_ob_addr : std_ulogic_vector(64-xu_real_data_add to 57); +signal lsu_bx_cmd_avail : std_ulogic; +signal lsu_bx_cmd_sent : std_ulogic; +signal lsu_bx_cmd_stall : std_ulogic; +signal lsu_reld_data_vld : std_ulogic; +signal bx_ib_empty_int : std_ulogic_vector(0 to 3); +signal ac_an_reld_ditc_pop_int : std_ulogic_vector(0 to 3); +signal lsu_reld_core_tag : std_ulogic_vector(3 to 4); +signal lsu_reld_ditc : std_ulogic; +signal lsu_reld_ecc_err : std_ulogic; +signal lsu_reld_qw : std_ulogic_vector(58 to 59); +signal lsu_reld_data : std_ulogic_vector(0 to 127); +signal lsu_req_st_pop : std_ulogic; +signal lsu_req_st_pop_thrd : std_ulogic_vector(0 to 2); +signal pc_bx_func_sl_thold_3 : std_ulogic; +signal pc_bx_func_slp_sl_thold_3 : std_ulogic; +signal pc_bx_gptr_sl_thold_3 : std_ulogic; +signal pc_bx_time_sl_thold_3 : std_ulogic; +signal pc_bx_repr_sl_thold_3 : std_ulogic; +signal pc_bx_abst_sl_thold_3 : std_ulogic; +signal pc_bx_ary_nsl_thold_3 : std_ulogic; +signal pc_bx_ary_slp_nsl_thold_3 : std_ulogic; +signal pc_bx_sg_3 : std_ulogic; +signal rp_pc_rtim_sl_thold_6 : std_ulogic; +signal rp_pc_func_sl_thold_6 : std_ulogic; +signal rp_pc_func_nsl_thold_6 : std_ulogic; +signal rp_pc_ary_nsl_thold_6 : std_ulogic; +signal rp_pc_sg_6 : std_ulogic; +signal rp_pc_fce_6 : std_ulogic; +signal debug_start_tiedowns : std_ulogic_vector(0 to 87); +signal trigger_start_tiedowns : std_ulogic_vector(0 to 11); +signal bx_fu_debug_data : std_ulogic_vector(0 to 87); +signal bx_fu_trigger_data : std_ulogic_vector(0 to 11); +signal fu_pc_debug_data : std_ulogic_vector(0 to 87); +signal fu_pc_trigger_data : std_ulogic_vector(0 to 11); +signal pc_iu_debug_data : std_ulogic_vector(0 to 87); +signal pc_iu_trigger_data : std_ulogic_vector(0 to 11); +signal iu_xu_debug_data : std_ulogic_vector(0 to 87); +signal iu_xu_trigger_data : std_ulogic_vector(0 to 11); +signal xu_mm_debug_data : std_ulogic_vector(0 to 87); +signal xu_mm_trigger_data : std_ulogic_vector(0 to 11); +signal iu_pc_gptr_scan_out : std_ulogic; +signal pc_fu_gptr_scan_out : std_ulogic; +signal fu_bx_gptr_scan_out : std_ulogic; +signal bx_xu_gptr_scan_out : std_ulogic; +signal xu_mm_gptr_scan_out : std_ulogic; +signal iu_fu_time_scan_out : std_ulogic; +signal fu_bx_time_scan_out : std_ulogic; +signal bx_xu_time_scan_out : std_ulogic; +signal xu_mm_time_scan_out : std_ulogic; +signal iu_fu_repr_scan_out : std_ulogic; +signal fu_bx_repr_scan_out : std_ulogic; +signal bx_xu_repr_scan_out : std_ulogic; +signal xu_mm_repr_scan_out : std_ulogic; +signal mm_iu_ccfg_scan_out : std_ulogic; +signal iu_pc_ccfg_scan_out : std_ulogic; +signal xu_fu_ccfg_scan_out : std_ulogic; +signal iu_fu_bcfg_scan_out : std_ulogic; +signal mm_rp_bcfg_scan_out : std_ulogic; +signal rp_pc_bcfg_scan_out_q : std_ulogic; +signal mm_rp_dcfg_scan_out : std_ulogic; +signal rp_pc_dcfg_scan_out_q : std_ulogic; +signal iu_fu_dcfg_scan_out : std_ulogic; +signal pc_rp_abst_scan_out : std_ulogic; +signal rp_pc_func_scan_in_q : std_ulogic_vector(0 to 1); +signal pc_rp_func_scan_out : std_ulogic_vector(0 to 1); +signal rp_fu_abst_scan_in_q : std_ulogic; +signal fu_rp_abst_scan_out : std_ulogic; +signal fu_rp_ccfg_scan_out : std_ulogic; +signal fu_rp_bcfg_scan_out : std_ulogic; +signal fu_rp_dcfg_scan_out : std_ulogic; +signal rp_fu_func_scan_in_q : std_ulogic_vector(0 to 3); +signal fu_rp_func_scan_out : std_ulogic_vector(0 to 3); +signal rp_bx_abst_scan_in_q : std_ulogic; +signal bx_rp_abst_scan_out : std_ulogic; +signal rp_bx_func_scan_in_q : std_ulogic_vector(0 to 1); +signal rp_fu_bx_abst_scan_in : std_ulogic; +signal bx_fu_rp_abst_scan_out : std_ulogic; +signal rp_fu_bx_func_scan_in : std_ulogic_vector(0 to 1); +signal bx_fu_rp_func_scan_out : std_ulogic_vector(0 to 1); +signal bx_rp_func_scan_out : std_ulogic_vector(0 to 1); +signal pc_rp_bcfg_scan_out : std_ulogic; +signal pc_rp_ccfg_scan_out : std_ulogic; +signal pc_rp_dcfg_scan_out : std_ulogic; +signal iu_pc_abst_scan_out : std_ulogic; +signal rp_pc_scom_dch_q : std_ulogic; +signal rp_pc_scom_cch_q : std_ulogic; +signal rp_pc_checkstop_q : std_ulogic; +signal rp_pc_debug_stop_q : std_ulogic; +signal rp_pc_pm_thread_stop_q : std_ulogic_vector(0 to 3); +signal rp_pc_reset_1_complete_q : std_ulogic; +signal rp_pc_reset_2_complete_q : std_ulogic; +signal rp_pc_reset_3_complete_q : std_ulogic; +signal rp_pc_reset_wd_complete_q : std_ulogic; +signal rp_pc_abist_start_test_q : std_ulogic; +signal pc_rp_scom_dch : std_ulogic; +signal pc_rp_scom_cch : std_ulogic; +signal pc_rp_special_attn : std_ulogic_vector(0 to 3); +signal pc_rp_checkstop : std_ulogic_vector(0 to 2); +signal pc_rp_trace_error : std_ulogic; +signal pc_rp_local_checkstop : std_ulogic_vector(0 to 2); +signal pc_rp_recov_err : std_ulogic_vector(0 to 2); +signal pc_rp_event_bus : std_ulogic_vector(0 to 7); +signal pc_rp_fu_bypass_events : std_ulogic_vector(0 to 7); +signal pc_rp_iu_bypass_events : std_ulogic_vector(0 to 7); +signal pc_rp_mm_bypass_events : std_ulogic_vector(0 to 7); +signal pc_rp_lsu_bypass_events : std_ulogic_vector(0 to 7); +signal pc_rp_pm_thread_running : std_ulogic_vector(0 to 3); +signal pc_rp_power_managed : std_ulogic; +signal pc_rp_rvwinkle_mode : std_ulogic; +signal pc_fu_event_mux_ctrls : std_ulogic_vector(0 to 31); +signal pc_iu_event_mux_ctrls : std_ulogic_vector(0 to 47); +signal pc_xu_event_mux_ctrls : std_ulogic_vector(0 to 47); +signal pc_xu_lsu_event_mux_ctrls : std_ulogic_vector(0 to 47); +signal pc_fu_event_bus_enable : std_ulogic; +signal pc_iu_event_bus_enable : std_ulogic; +signal pc_xu_event_bus_enable : std_ulogic; +signal pc_rp_event_bus_enable : std_ulogic; +signal rp_mm_event_bus_enable_q : std_ulogic; +signal ac_an_debug_bus_int : std_ulogic_vector(0 to 87); +signal ac_rp_trace_to_perfcntr : std_ulogic_vector(0 to 7); +signal rp_pc_trace_to_perfcntr_q : std_ulogic_vector(0 to 7); +signal ac_an_power_managed_int : std_ulogic; +signal xu_iu_reld_core_tag : std_ulogic_vector(0 to 4); +signal xu_iu_reld_core_tag_clone : std_ulogic_vector(1 to 4); +signal xu_iu_reld_data : std_ulogic_vector(0 to 127); +signal xu_iu_reld_data_coming_clone : std_ulogic; +signal xu_iu_reld_data_vld : std_ulogic; +signal xu_iu_reld_data_vld_clone : std_ulogic; +signal xu_iu_reld_ecc_err : std_ulogic; +signal xu_iu_reld_ditc_clone : std_ulogic; +signal xu_iu_reld_ecc_err_ue : std_ulogic; +signal xu_iu_reld_qw : std_ulogic_vector(57 to 59); +signal xu_iu_stcx_complete : std_ulogic_vector(0 to 3); +signal xu_st_byte_enbl : std_ulogic_vector(0 to 15+(st_data_32b_mode*16)); +signal xu_st_data : std_ulogic_vector(0 to 127+(st_data_32b_mode*128)); +signal an_ac_bo_enable : std_ulogic; +signal an_ac_bo_go : std_ulogic; +signal an_ac_bo_cntlclk : std_ulogic; +signal an_ac_bo_ccflush : std_ulogic; +signal an_ac_bo_reset : std_ulogic; +signal an_ac_bo_data : std_ulogic; +signal an_ac_bo_shcntl : std_ulogic; +signal an_ac_bo_shdata : std_ulogic; +signal an_ac_bo_exe : std_ulogic; +signal an_ac_bo_sysrepair : std_ulogic; +signal an_ac_bo_donein : std_ulogic; +signal an_ac_bo_sdin : std_ulogic; +signal an_ac_bo_waitin : std_ulogic; +signal an_ac_bo_failin : std_ulogic; +signal an_ac_bo_fcshdata : std_ulogic; +signal an_ac_bo_fcreset : std_ulogic; +signal ac_an_bo_doneout : std_ulogic; +signal ac_an_bo_sdout : std_ulogic; +signal ac_an_bo_diagloopout : std_ulogic; +signal ac_an_bo_waitout : std_ulogic; +signal ac_an_bo_failout : std_ulogic; +signal pc_bx_bolt_sl_thold_3 : std_ulogic; +signal pc_fu_bolt_sl_thold_3 : std_ulogic; +signal pc_xu_bolt_sl_thold_3 : std_ulogic; +signal pc_bx_bo_enable_3 : std_ulogic; +signal pc_bx_bo_unload : std_ulogic; +signal pc_bx_bo_repair : std_ulogic; +signal pc_bx_bo_reset : std_ulogic; +signal pc_bx_bo_shdata : std_ulogic; +signal pc_bx_bo_select : std_ulogic_vector(0 to 3); +signal bx_pc_bo_fail : std_ulogic_vector(0 to 3); +signal bx_pc_bo_diagout : std_ulogic_vector(0 to 3); +signal pc_fu_bo_enable_3 : std_ulogic; +signal pc_fu_bo_unload : std_ulogic; +signal pc_fu_bo_load : std_ulogic; +signal pc_fu_bo_reset : std_ulogic; +signal pc_fu_bo_shdata : std_ulogic; +signal pc_fu_bo_select : std_ulogic_vector(0 to 1); +signal fu_pc_bo_fail : std_ulogic_vector(0 to 1); +signal fu_pc_bo_diagout : std_ulogic_vector(0 to 1); +signal pc_iu_bo_enable_4 : std_ulogic; +signal pc_iu_bo_unload : std_ulogic; +signal pc_iu_bo_repair : std_ulogic; +signal pc_iu_bo_reset : std_ulogic; +signal pc_iu_bo_shdata : std_ulogic; +signal pc_iu_bo_select : std_ulogic_vector(0 to 4); +signal iu_pc_bo_fail : std_ulogic_vector(0 to 4); +signal iu_pc_bo_diagout : std_ulogic_vector(0 to 4); +signal pc_xu_bo_enable_3 : std_ulogic; +signal pc_xu_bo_unload : std_ulogic; +signal pc_xu_bo_load : std_ulogic; +signal pc_xu_bo_repair : std_ulogic; +signal pc_xu_bo_reset : std_ulogic; +signal pc_xu_bo_shdata : std_ulogic; +signal pc_xu_bo_select : std_ulogic_vector(0 to 8); +signal xu_pc_bo_fail : std_ulogic_vector(0 to 8); +signal xu_pc_bo_diagout : std_ulogic_vector(0 to 8); + +signal an_ac_abist_mode_dc_oiu : std_ulogic; +signal an_ac_ccflush_dc_oiu : std_ulogic; +signal an_ac_gsd_test_enable_dc_oiu : std_ulogic; +signal an_ac_gsd_test_acmode_dc_oiu : std_ulogic; +signal an_ac_lbist_ip_dc_oiu : std_ulogic; +signal an_ac_lbist_ac_mode_dc_oiu : std_ulogic; +signal an_ac_malf_alert_oiu : std_ulogic; +signal an_ac_psro_enable_dc_oiu : std_ulogic_vector(0 to 2); +signal an_ac_scan_type_dc_oiu : std_ulogic_vector(0 to 8); +signal an_ac_scom_sat_id_oiu : std_ulogic_vector(0 to 3); +signal an_ac_back_inv_oiu : std_ulogic; +signal an_ac_back_inv_addr_oiu : std_ulogic_vector(64-xu_real_data_add to 63); +signal an_ac_back_inv_target_bit1_oiu : std_ulogic; +signal an_ac_back_inv_target_bit3_oiu : std_ulogic; +signal an_ac_back_inv_target_bit4_oiu : std_ulogic; +signal an_ac_atpg_en_dc_oiu : std_ulogic; +signal an_ac_lbist_ary_wrt_thru_dc_oiu : std_ulogic; +signal an_ac_lbist_en_dc_oiu : std_ulogic; +signal an_ac_scan_diag_dc_oiu : std_ulogic; +signal an_ac_scan_dis_dc_b_oiu : std_ulogic; +signal an_ac_back_inv_omm : std_ulogic; +signal an_ac_back_inv_addr_omm : std_ulogic_vector(64-real_addr_width to 63); +signal an_ac_back_inv_target_omm_iua : std_ulogic_vector(0 to 1); +signal an_ac_back_inv_target_omm_iub : std_ulogic_vector(3 to 4); +signal an_ac_reld_core_tag_omm : std_ulogic_vector(0 to 4); +signal an_ac_reld_data_omm : std_ulogic_vector(0 to 127); +signal an_ac_reld_data_vld_omm : std_ulogic; +signal an_ac_reld_ecc_err_omm : std_ulogic; +signal an_ac_reld_ecc_err_ue_omm : std_ulogic; +signal an_ac_reld_qw_omm : std_ulogic_vector(57 to 59); +signal an_ac_reld_ditc_omm : std_ulogic; +signal an_ac_reld_crit_qw_omm : std_ulogic; +signal an_ac_reld_data_coming_omm : std_ulogic; +signal an_ac_reld_l1_dump_omm : std_ulogic; +signal an_ac_camfence_en_dc_omm : std_ulogic; +signal an_ac_stcx_complete_omm : std_ulogic_vector(0 to 3); +signal an_ac_abist_mode_dc_omm : std_ulogic; +signal an_ac_abist_start_test_omm : std_ulogic; +signal an_ac_abst_scan_in_omm_iu : std_ulogic_vector(0 to 4); +signal an_ac_abst_scan_in_omm_xu : std_ulogic_vector(7 to 9); +signal an_ac_atpg_en_dc_omm : std_ulogic; +signal an_ac_bcfg_scan_in_omm_bit1 : std_ulogic; +signal an_ac_bcfg_scan_in_omm_bit3 : std_ulogic; +signal an_ac_bcfg_scan_in_omm_bit4 : std_ulogic; +signal an_ac_lbist_ary_wrt_thru_dc_omm : std_ulogic; +signal an_ac_ccflush_dc_omm : std_ulogic; +signal an_ac_reset_1_complete_omm : std_ulogic; +signal an_ac_reset_2_complete_omm : std_ulogic; +signal an_ac_reset_3_complete_omm : std_ulogic; +signal an_ac_reset_wd_complete_omm : std_ulogic; +signal an_ac_dcfg_scan_in_omm : std_ulogic_vector(1 to 2); +signal an_ac_debug_stop_omm : std_ulogic; +signal an_ac_func_scan_in_omm_iua : std_ulogic_vector(0 to 21); +signal an_ac_func_scan_in_omm_iub : std_ulogic_vector(60 to 63); +signal an_ac_func_scan_in_omm_xu : std_ulogic_vector(31 to 58); +signal an_ac_lbist_en_dc_omm : std_ulogic; +signal an_ac_pm_thread_stop_omm : std_ulogic_vector(0 to 3); +signal an_ac_regf_scan_in_omm : std_ulogic_vector(0 to 11); +signal an_ac_scan_diag_dc_omm : std_ulogic; +signal an_ac_scan_dis_dc_b_omm : std_ulogic; +signal an_ac_scom_cch_omm : std_ulogic; +signal an_ac_scom_dch_omm : std_ulogic; +signal an_ac_checkstop_omm : std_ulogic; +signal ac_an_abst_scan_out_imm_iu : std_ulogic_vector(0 to 4); +signal ac_an_abst_scan_out_imm_xu : std_ulogic_vector(7 to 9); +signal ac_an_bcfg_scan_out_imm : std_ulogic_vector(0 to 4); +signal ac_an_dcfg_scan_out_imm : std_ulogic_vector(0 to 2); +signal ac_an_func_scan_out_imm_iua : std_ulogic_vector(0 to 21); +signal ac_an_func_scan_out_imm_iub : std_ulogic_vector(60 to 63); +signal ac_an_func_scan_out_imm_xu : std_ulogic_vector(31 to 58); +signal ac_an_reld_ditc_pop_imm : std_ulogic_vector(0 to 3); +signal ac_an_power_managed_imm : std_ulogic; +signal ac_an_rvwinkle_mode_imm : std_ulogic; +signal ac_an_fu_bypass_events_imm : std_ulogic_vector(0 to 7); +signal ac_an_iu_bypass_events_imm : std_ulogic_vector(0 to 7); +signal ac_an_mm_bypass_events_imm : std_ulogic_vector(0 to 7); +signal ac_an_lsu_bypass_events_imm : std_ulogic_vector(0 to 7); +signal ac_an_event_bus_imm : std_ulogic_vector(0 to 7); +signal ac_an_pm_thread_running_imm : std_ulogic_vector(0 to 3); +signal ac_an_recov_err_imm : std_ulogic_vector(0 to 2); +signal ac_an_regf_scan_out_imm : std_ulogic_vector(0 to 11); +signal ac_an_scom_cch_imm : std_ulogic; +signal ac_an_scom_dch_imm : std_ulogic; +signal ac_an_special_attn_imm : std_ulogic_vector(0 to 3); +signal ac_an_checkstop_imm : std_ulogic_vector(0 to 2); +signal ac_an_local_checkstop_imm : std_ulogic_vector(0 to 2); +signal ac_an_trace_error_imm : std_ulogic; + +signal bx_pc_err_inbox_ue_ofu : std_ulogic; +signal bx_pc_err_outbox_ue_ofu : std_ulogic; +signal bx_pc_err_inbox_ecc_ofu : std_ulogic; +signal bx_pc_err_outbox_ecc_ofu : std_ulogic; +signal pc_bx_bolt_sl_thold_3_ofu : std_ulogic; +signal pc_bx_bo_enable_3_ofu : std_ulogic; +signal pc_bx_bo_unload_ofu : std_ulogic; +signal pc_bx_bo_repair_ofu : std_ulogic; +signal pc_bx_bo_reset_ofu : std_ulogic; +signal pc_bx_bo_shdata_ofu : std_ulogic; +signal pc_bx_bo_select_ofu : std_ulogic_vector(0 to 3); +signal bx_pc_bo_fail_ofu : std_ulogic_vector(0 to 3); +signal bx_pc_bo_diagout_ofu : std_ulogic_vector(0 to 3); +signal pc_bx_abist_di_0_ofu : std_ulogic_vector(0 to 3); +signal pc_bx_abist_ena_dc_ofu : std_ulogic; +signal pc_bx_abist_g8t1p_renb_0_ofu : std_ulogic; +signal pc_bx_abist_g8t_bw_0_ofu : std_ulogic; +signal pc_bx_abist_g8t_bw_1_ofu : std_ulogic; +signal pc_bx_abist_g8t_dcomp_ofu : std_ulogic_vector(0 to 3); +signal pc_bx_abist_g8t_wenb_ofu : std_ulogic; +signal pc_bx_abist_raddr_0_ofu : std_ulogic_vector(4 to 9); +signal pc_bx_abist_raw_dc_b_ofu : std_ulogic; +signal pc_bx_abist_waddr_0_ofu : std_ulogic_vector(4 to 9); +signal pc_bx_abist_wl64_comp_ena_ofu : std_ulogic; +signal pc_bx_trace_bus_enable_ofu : std_ulogic; +signal pc_bx_debug_mux1_ctrls_ofu : std_ulogic_vector(0 to 15); +signal pc_bx_inj_inbox_ecc_ofu : std_ulogic; +signal pc_bx_inj_outbox_ecc_ofu : std_ulogic; +signal pc_bx_ccflush_dc_ofu : std_ulogic; +signal pc_bx_sg_3_ofu : std_ulogic; +signal pc_bx_func_sl_thold_3_ofu : std_ulogic; +signal pc_bx_func_slp_sl_thold_3_ofu : std_ulogic; +signal pc_bx_gptr_sl_thold_3_ofu : std_ulogic; +signal pc_bx_time_sl_thold_3_ofu : std_ulogic; +signal pc_bx_repr_sl_thold_3_ofu : std_ulogic; +signal pc_bx_abst_sl_thold_3_ofu : std_ulogic; +signal pc_bx_ary_nsl_thold_3_ofu : std_ulogic; +signal pc_bx_ary_slp_nsl_thold_3_ofu : std_ulogic; + +signal xu_pc_err_mcsr_summary_ofu : std_ulogic_vector(0 to 3); +signal xu_pc_err_ierat_parity_ofu : std_ulogic; +signal xu_pc_err_derat_parity_ofu : std_ulogic; +signal xu_pc_err_tlb_parity_ofu : std_ulogic; +signal xu_pc_err_tlb_lru_parity_ofu : std_ulogic; +signal xu_pc_err_ierat_multihit_ofu : std_ulogic; +signal xu_pc_err_derat_multihit_ofu : std_ulogic; +signal xu_pc_err_tlb_multihit_ofu : std_ulogic; +signal xu_pc_err_ext_mchk_ofu : std_ulogic; +signal xu_pc_err_ditc_overrun_ofu : std_ulogic; +signal xu_pc_err_local_snoop_reject_ofu : std_ulogic; +signal xu_pc_err_attention_instr_ofu : std_ulogic_vector(0 to 3); +signal xu_pc_err_dcache_parity_ofu : std_ulogic; +signal xu_pc_err_dcachedir_parity_ofu : std_ulogic; +signal xu_pc_err_dcachedir_multihit_ofu : std_ulogic; +signal xu_pc_err_debug_event_ofu : std_ulogic_vector(0 to 3); +signal xu_pc_err_invld_reld_ofu : std_ulogic; +signal xu_pc_err_l2intrf_ecc_ofu : std_ulogic; +signal xu_pc_err_l2intrf_ue_ofu : std_ulogic; +signal xu_pc_err_l2credit_overrun_ofu : std_ulogic; +signal xu_pc_err_llbust_attempt_ofu : std_ulogic_vector(0 to 3); +signal xu_pc_err_llbust_failed_ofu : std_ulogic_vector(0 to 3); +signal xu_pc_err_nia_miscmpr_ofu : std_ulogic_vector(0 to 3); +signal xu_pc_err_regfile_parity_ofu : std_ulogic_vector(0 to 3); +signal xu_pc_err_regfile_ue_ofu : std_ulogic_vector(0 to 3); +signal xu_pc_err_sprg_ecc_ofu : std_ulogic_vector(0 to 3); +signal xu_pc_err_sprg_ue_ofu : std_ulogic_vector(0 to 3); +signal xu_pc_err_wdt_reset_ofu : std_ulogic_vector(0 to 3); +signal xu_pc_event_data_ofu : std_ulogic_vector(0 to 7); +signal xu_pc_ram_data_ofu : std_ulogic_vector(64-(2**regmode) to 63); +signal xu_pc_ram_done_ofu : std_ulogic; +signal xu_pc_ram_interrupt_ofu : std_ulogic; +signal xu_pc_running_ofu : std_ulogic_vector(0 to 3); +signal xu_pc_spr_ccr0_pme_ofu : std_ulogic_vector(0 to 1); +signal xu_pc_spr_ccr0_we_ofu : std_ulogic_vector(0 to 3); +signal xu_pc_step_done_ofu : std_ulogic_vector(0 to 3); +signal xu_pc_stop_dbg_event_ofu : std_ulogic_vector(0 to 3); +signal pc_xu_bolt_sl_thold_3_ofu : std_ulogic; +signal pc_xu_bo_enable_3_ofu : std_ulogic; +signal pc_xu_bo_unload_ofu : std_ulogic; +signal pc_xu_bo_load_ofu : std_ulogic; +signal pc_xu_bo_repair_ofu : std_ulogic; +signal pc_xu_bo_reset_ofu : std_ulogic; +signal pc_xu_bo_shdata_ofu : std_ulogic; +signal pc_xu_bo_select_ofu : std_ulogic_vector(0 to 8); +signal xu_pc_bo_fail_ofu : std_ulogic_vector(0 to 8); +signal xu_pc_bo_diagout_ofu : std_ulogic_vector(0 to 8); +signal pc_xu_abist_dcomp_g6t_2r_ofu : std_ulogic_vector(0 to 3); +signal pc_xu_abist_di_0_ofu : std_ulogic_vector(0 to 3); +signal pc_xu_abist_di_1_ofu : std_ulogic_vector(0 to 3); +signal pc_xu_abist_di_g6t_2r_ofu : std_ulogic_vector(0 to 3); +signal pc_xu_abist_ena_dc_ofu : std_ulogic; +signal pc_xu_abist_g6t_bw_ofu : std_ulogic_vector(0 to 1); +signal pc_xu_abist_g6t_r_wb_ofu : std_ulogic; +signal pc_xu_abist_g8t1p_renb_0_ofu : std_ulogic; +signal pc_xu_abist_g8t_bw_0_ofu : std_ulogic; +signal pc_xu_abist_g8t_bw_1_ofu : std_ulogic; +signal pc_xu_abist_g8t_dcomp_ofu : std_ulogic_vector(0 to 3); +signal pc_xu_abist_g8t_wenb_ofu : std_ulogic; +signal pc_xu_abist_grf_renb_0_ofu : std_ulogic; +signal pc_xu_abist_grf_renb_1_ofu : std_ulogic; +signal pc_xu_abist_grf_wenb_0_ofu : std_ulogic; +signal pc_xu_abist_grf_wenb_1_ofu : std_ulogic; +signal pc_xu_abist_raddr_0_ofu : std_ulogic_vector(0 to 9); +signal pc_xu_abist_raddr_1_ofu : std_ulogic_vector(0 to 9); +signal pc_xu_abist_raw_dc_b_ofu : std_ulogic; +signal pc_xu_abist_waddr_0_ofu : std_ulogic_vector(0 to 9); +signal pc_xu_abist_waddr_1_ofu : std_ulogic_vector(0 to 9); +signal pc_xu_abist_wl144_comp_ena_ofu : std_ulogic; +signal pc_xu_abist_wl32_comp_ena_ofu : std_ulogic; +signal pc_xu_abist_wl512_comp_ena_ofu : std_ulogic; +signal pc_xu_event_mux_ctrls_ofu : std_ulogic_vector(0 to 47); +signal pc_xu_lsu_event_mux_ctrls_ofu : std_ulogic_vector(0 to 47); +signal pc_xu_event_bus_enable_ofu : std_ulogic; +signal pc_xu_abst_sl_thold_3_ofu : std_ulogic; +signal pc_xu_abst_slp_sl_thold_3_ofu : std_ulogic; +signal pc_xu_regf_sl_thold_3_ofu : std_ulogic; +signal pc_xu_regf_slp_sl_thold_3_ofu : std_ulogic; +signal pc_xu_ary_nsl_thold_3_ofu : std_ulogic; +signal pc_xu_ary_slp_nsl_thold_3_ofu : std_ulogic; +signal pc_xu_cache_par_err_event_ofu : std_ulogic; +signal pc_xu_ccflush_dc_ofu : std_ulogic; +signal pc_xu_cfg_sl_thold_3_ofu : std_ulogic; +signal pc_xu_cfg_slp_sl_thold_3_ofu : std_ulogic; +signal pc_xu_dbg_action_ofu : std_ulogic_vector(0 to 11); +signal pc_xu_debug_mux1_ctrls_ofu : std_ulogic_vector(0 to 15); +signal pc_xu_debug_mux2_ctrls_ofu : std_ulogic_vector(0 to 15); +signal pc_xu_debug_mux3_ctrls_ofu : std_ulogic_vector(0 to 15); +signal pc_xu_debug_mux4_ctrls_ofu : std_ulogic_vector(0 to 15); +signal pc_xu_decrem_dis_on_stop_ofu : std_ulogic; +signal pc_xu_event_count_mode_ofu : std_ulogic_vector(0 to 2); +signal pc_xu_extirpts_dis_on_stop_ofu : std_ulogic; +signal pc_xu_fce_3_ofu : std_ulogic_vector(0 to 1); +signal pc_xu_force_ude_ofu : std_ulogic_vector(0 to 3); +signal pc_xu_func_nsl_thold_3_ofu : std_ulogic; +signal pc_xu_func_sl_thold_3_ofu : std_ulogic_vector(0 to 4); +signal pc_xu_func_slp_nsl_thold_3_ofu : std_ulogic; +signal pc_xu_func_slp_sl_thold_3_ofu : std_ulogic_vector(0 to 4); +signal pc_xu_gptr_sl_thold_3_ofu : std_ulogic; +signal pc_xu_init_reset_ofu : std_ulogic; +signal pc_xu_inj_dcache_parity_ofu : std_ulogic; +signal pc_xu_inj_dcachedir_parity_ofu : std_ulogic; +signal pc_xu_inj_llbust_attempt_ofu : std_ulogic_vector(0 to 3); +signal pc_xu_inj_llbust_failed_ofu : std_ulogic_vector(0 to 3); +signal pc_xu_inj_sprg_ecc_ofu : std_ulogic_vector(0 to 3); +signal pc_xu_inj_regfile_parity_ofu : std_ulogic_vector(0 to 3); +signal pc_xu_inj_wdt_reset_ofu : std_ulogic_vector(0 to 3); +signal pc_xu_inj_dcachedir_multihit_ofu : std_ulogic; +signal pc_xu_instr_trace_mode_ofu : std_ulogic; +signal pc_xu_instr_trace_tid_ofu : std_ulogic_vector(0 to 1); +signal pc_xu_msrovride_enab_ofu : std_ulogic; +signal pc_xu_msrovride_gs_ofu : std_ulogic; +signal pc_xu_msrovride_pr_ofu : std_ulogic; +signal pc_xu_ram_execute_ofu : std_ulogic; +signal pc_xu_ram_flush_thread_ofu : std_ulogic; +signal pc_xu_ram_mode_ofu : std_ulogic; +signal pc_xu_ram_thread_ofu : std_ulogic_vector(0 to 1); +signal pc_xu_repr_sl_thold_3_ofu : std_ulogic; +signal pc_xu_reset_1_cmplt_ofu : std_ulogic; +signal pc_xu_reset_2_cmplt_ofu : std_ulogic; +signal pc_xu_reset_3_cmplt_ofu : std_ulogic; +signal pc_xu_reset_wd_cmplt_ofu : std_ulogic; +signal pc_xu_sg_3_ofu : std_ulogic_vector(0 to 4); +signal pc_xu_step_ofu : std_ulogic_vector(0 to 3); +signal pc_xu_stop_ofu : std_ulogic_vector(0 to 3); +signal pc_xu_time_sl_thold_3_ofu : std_ulogic; +signal pc_xu_timebase_dis_on_stop_ofu : std_ulogic; +signal pc_xu_trace_bus_enable_ofu : std_ulogic; + +signal an_ac_crit_interrupt_omm : std_ulogic_vector(0 to thdid_width-1); +signal an_ac_ext_interrupt_omm : std_ulogic_vector(0 to thdid_width-1); +signal an_ac_flh2l2_gate_omm : std_ulogic; +signal an_ac_icbi_ack_omm : std_ulogic; +signal an_ac_icbi_ack_thread_omm : std_ulogic_vector(0 to 1); +signal an_ac_req_ld_pop_omm : std_ulogic; +signal an_ac_req_spare_ctrl_a1_omm : std_ulogic_vector(0 to 3); +signal an_ac_req_st_gather_omm : std_ulogic; +signal an_ac_req_st_pop_omm : std_ulogic; +signal an_ac_req_st_pop_thrd_omm : std_ulogic_vector(0 to 2); +signal an_ac_reservation_vld_omm : std_ulogic_vector(0 to thdid_width-1); +signal an_ac_sleep_en_omm : std_ulogic_vector(0 to thdid_width-1); +signal an_ac_stcx_pass_omm : std_ulogic_vector(0 to 3); +signal an_ac_sync_ack_omm : std_ulogic_vector(0 to 3); +signal an_ac_ary_nsl_thold_7_omm : std_ulogic; +signal an_ac_coreid_omm : std_ulogic_vector(0 to 7); +signal an_ac_external_mchk_omm : std_ulogic_vector(0 to 3); +signal an_ac_fce_7_omm : std_ulogic; +signal an_ac_func_nsl_thold_7_omm : std_ulogic; +signal an_ac_func_sl_thold_7_omm : std_ulogic; +signal an_ac_gsd_test_enable_dc_omm : std_ulogic; +signal an_ac_gsd_test_acmode_dc_omm : std_ulogic; +signal an_ac_gptr_scan_in_omm : std_ulogic; +signal an_ac_hang_pulse_omm : std_ulogic_vector(0 to thdid_width-1); +signal an_ac_lbist_ac_mode_dc_omm : std_ulogic; +signal an_ac_lbist_ip_dc_omm : std_ulogic; +signal an_ac_malf_alert_omm : std_ulogic; +signal an_ac_perf_interrupt_omm : std_ulogic_vector(0 to thdid_width-1); +signal an_ac_psro_enable_dc_omm : std_ulogic_vector(0 to 2); +signal an_ac_repr_scan_in_omm : std_ulogic; +signal an_ac_rtim_sl_thold_7_omm : std_ulogic; +signal an_ac_scan_type_dc_omm : std_ulogic_vector(0 to 8); +signal an_ac_scom_sat_id_omm : std_ulogic_vector(0 to 3); +signal an_ac_sg_7_omm : std_ulogic; +signal an_ac_tb_update_enable_omm : std_ulogic; +signal an_ac_tb_update_pulse_omm : std_ulogic; +signal an_ac_time_scan_in_omm : std_ulogic; + +signal ac_an_box_empty_imm : std_ulogic_vector(0 to 3); +signal ac_an_machine_check_imm : std_ulogic_vector(0 to thdid_width-1); +signal ac_an_req_imm : std_ulogic; +signal ac_an_req_endian_imm : std_ulogic; +signal ac_an_req_ld_core_tag_imm : std_ulogic_vector(0 to 4); +signal ac_an_req_ld_xfr_len_imm : std_ulogic_vector(0 to 2); +signal ac_an_req_pwr_token_imm : std_ulogic; +signal ac_an_req_ra_imm : std_ulogic_vector(64-real_addr_width to 63); +signal ac_an_req_spare_ctrl_a0_imm : std_ulogic_vector(0 to 3); +signal ac_an_req_thread_imm : std_ulogic_vector(0 to 2); +signal ac_an_req_ttype_imm : std_ulogic_vector(0 to 5); +signal ac_an_req_user_defined_imm : std_ulogic_vector(0 to 3); +signal ac_an_req_wimg_g_imm : std_ulogic; +signal ac_an_req_wimg_i_imm : std_ulogic; +signal ac_an_req_wimg_m_imm : std_ulogic; +signal ac_an_req_wimg_w_imm : std_ulogic; +signal ac_an_st_byte_enbl_imm : std_ulogic_vector(0 to 31); +signal ac_an_st_byte_enbl_omm : std_ulogic_vector(16 to 31); +signal ac_an_st_data_imm : std_ulogic_vector(0 to 255); +signal ac_an_st_data_omm : std_ulogic_vector(128 to 255); +signal ac_an_st_data_pwr_token_imm : std_ulogic; +signal ac_an_debug_trigger_imm : std_ulogic_vector(0 to thdid_width-1); +signal ac_an_reset_1_request_imm : std_ulogic; +signal ac_an_reset_2_request_imm : std_ulogic; +signal ac_an_reset_3_request_imm : std_ulogic; +signal ac_an_reset_wd_request_imm : std_ulogic; +signal an_ac_scan_diag_dc_opc : std_ulogic; +signal an_ac_scan_dis_dc_b_opc : std_ulogic; +signal an_ac_scan_dis_dc_b_ofu : std_ulogic; +signal an_ac_scan_diag_dc_ofu : std_ulogic; + +signal ac_an_abist_done_dc_iiu : std_ulogic; +signal ac_an_psro_ringsig_iiu : std_ulogic; +signal an_ac_ccenable_dc_iiu : std_ulogic; +signal mm_pc_bo_fail_iiu : std_ulogic_vector(0 to 4); +signal mm_pc_bo_diagout_iiu : std_ulogic_vector(0 to 4); +signal mm_pc_event_data_iiu : std_ulogic_vector(0 to 7); + +signal ac_an_abist_done_dc_oiu : std_ulogic; +signal ac_an_psro_ringsig_oiu : std_ulogic; +signal an_ac_ccenable_dc_oiu : std_ulogic; +signal mm_pc_bo_fail_oiu : std_ulogic_vector(0 to 4); +signal mm_pc_bo_diagout_oiu : std_ulogic_vector(0 to 4); +signal mm_pc_event_data_oiu : std_ulogic_vector(0 to 7); + +signal pc_mm_abist_dcomp_g6t_2r_iiu : std_ulogic_vector(0 to 3); +signal pc_mm_abist_di_g6t_2r_iiu : std_ulogic_vector(0 to 3); +signal pc_mm_abist_di_0_iiu : std_ulogic_vector(0 to 3); +signal pc_mm_abist_ena_dc_iiu : std_ulogic; +signal pc_mm_abist_g6t_r_wb_iiu : std_ulogic; +signal pc_mm_abist_g8t_bw_0_iiu : std_ulogic; +signal pc_mm_abist_g8t_bw_1_iiu : std_ulogic; +signal pc_mm_abist_g8t_dcomp_iiu : std_ulogic_vector(0 to 3); +signal pc_mm_abist_g8t_wenb_iiu : std_ulogic; +signal pc_mm_abist_g8t1p_renb_0_iiu : std_ulogic; +signal pc_mm_abist_raddr_0_iiu : std_ulogic_vector(0 to 9); +signal pc_mm_abist_raw_dc_b_iiu : std_ulogic; +signal pc_mm_abist_waddr_0_iiu : std_ulogic_vector(0 to 9); +signal pc_mm_abist_wl128_comp_ena_iiu : std_ulogic; +signal pc_mm_bo_enable_4_iiu : std_ulogic; +signal pc_mm_bo_repair_iiu : std_ulogic; +signal pc_mm_bo_reset_iiu : std_ulogic; +signal pc_mm_bo_select_iiu : std_ulogic_vector(0 to 4); +signal pc_mm_bo_shdata_iiu : std_ulogic; +signal pc_mm_bo_unload_iiu : std_ulogic; +signal pc_mm_ccflush_dc_iiu : std_ulogic; +signal pc_mm_debug_mux1_ctrls_iiu : std_ulogic_vector(0 to 15); +signal pc_mm_event_count_mode_iiu : std_ulogic_vector(0 to 2); +signal pc_mm_event_mux_ctrls_iiu : std_ulogic_vector(0 to 39); +signal pc_mm_trace_bus_enable_iiu : std_ulogic; +signal pc_mm_abist_dcomp_g6t_2r_oiu : std_ulogic_vector(0 to 3); +signal pc_mm_abist_di_g6t_2r_oiu : std_ulogic_vector(0 to 3); +signal pc_mm_abist_di_0_oiu : std_ulogic_vector(0 to 3); +signal pc_mm_abist_ena_dc_oiu : std_ulogic; +signal pc_mm_abist_g6t_r_wb_oiu : std_ulogic; +signal pc_mm_abist_g8t_bw_0_oiu : std_ulogic; +signal pc_mm_abist_g8t_bw_1_oiu : std_ulogic; +signal pc_mm_abist_g8t_dcomp_oiu : std_ulogic_vector(0 to 3); +signal pc_mm_abist_g8t_wenb_oiu : std_ulogic; +signal pc_mm_abist_g8t1p_renb_0_oiu : std_ulogic; +signal pc_mm_abist_raddr_0_oiu : std_ulogic_vector(0 to 9); +signal pc_mm_abist_raw_dc_b_oiu : std_ulogic; +signal pc_mm_abist_waddr_0_oiu : std_ulogic_vector(0 to 9); +signal pc_mm_abist_wl128_comp_ena_oiu : std_ulogic; +signal pc_mm_abst_sl_thold_3_oiu : std_ulogic; +signal pc_mm_abst_slp_sl_thold_3_oiu : std_ulogic; +signal pc_mm_ary_nsl_thold_3_oiu : std_ulogic; +signal pc_mm_ary_slp_nsl_thold_3_oiu : std_ulogic; +signal pc_mm_bo_enable_3_oiu : std_ulogic; +signal pc_mm_bo_repair_oiu : std_ulogic; +signal pc_mm_bo_reset_oiu : std_ulogic; +signal pc_mm_bo_select_oiu : std_ulogic_vector(0 to 4); +signal pc_mm_bo_shdata_oiu : std_ulogic; +signal pc_mm_bo_unload_oiu : std_ulogic; +signal pc_mm_bolt_sl_thold_3_oiu : std_ulogic; +signal pc_mm_ccflush_dc_oiu : std_ulogic; +signal pc_mm_cfg_sl_thold_3_oiu : std_ulogic; +signal pc_mm_cfg_slp_sl_thold_3_oiu : std_ulogic; +signal pc_mm_debug_mux1_ctrls_oiu : std_ulogic_vector(0 to 15); +signal pc_mm_event_count_mode_oiu : std_ulogic_vector(0 to 2); +signal pc_mm_event_mux_ctrls_oiu : std_ulogic_vector(0 to 39); +signal pc_mm_fce_3_oiu : std_ulogic; +signal pc_mm_func_nsl_thold_3_oiu : std_ulogic; +signal pc_mm_func_sl_thold_3_oiu : std_ulogic_vector(0 to 1); +signal pc_mm_func_slp_nsl_thold_3_oiu : std_ulogic; +signal pc_mm_func_slp_sl_thold_3_oiu : std_ulogic_vector(0 to 1); +signal pc_mm_gptr_sl_thold_3_oiu : std_ulogic; +signal pc_mm_repr_sl_thold_3_oiu : std_ulogic; +signal pc_mm_sg_3_oiu : std_ulogic_vector(0 to 1); +signal pc_mm_time_sl_thold_3_oiu : std_ulogic; +signal pc_mm_trace_bus_enable_oiu : std_ulogic; +signal xu_ex2_flush_ofu : std_ulogic_vector(0 to 3); +signal xu_ex3_flush_ofu : std_ulogic_vector(0 to 3); +signal xu_ex4_flush_ofu : std_ulogic_vector(0 to 3); +signal xu_ex5_flush_ofu : std_ulogic_vector(0 to 3); +signal an_ac_lbist_ary_wrt_thru_dc_ofu : std_ulogic; +signal xu_pc_lsu_event_data_ofu : std_ulogic_vector(0 to 7); +signal xu_pc_err_mchk_disabled : std_ulogic; +signal xu_pc_err_mchk_disabled_ofu : std_ulogic; +signal xu_iu_l_flush : std_ulogic_vector(0 to 3); +signal xu_iu_u_flush : std_ulogic_vector(0 to 3); +signal debug_bus_out_int : std_ulogic_vector(0 to 7); +signal an_ac_grffence_en_dc_oiu : std_ulogic; +signal xu_fu_lbist_ary_wrt_thru_dc : std_ulogic; +signal pc_xu_msrovride_de : std_ulogic; + +signal bg_an_ac_func_scan_sn : std_ulogic_vector(60 to 69); +signal bg_an_ac_abst_scan_sn : std_ulogic_vector(10 to 11); +signal bg_an_ac_func_scan_sn_q : std_ulogic_vector(60 to 69); +signal bg_an_ac_abst_scan_sn_q : std_ulogic_vector(10 to 11); + +signal bg_ac_an_func_scan_ns : std_ulogic_vector(60 to 69); +signal bg_ac_an_abst_scan_ns : std_ulogic_vector(10 to 11); +signal bg_ac_an_func_scan_ns_q : std_ulogic_vector(60 to 69); +signal bg_ac_an_abst_scan_ns_q : std_ulogic_vector(10 to 11); + +signal bg_pc_l1p_abist_di_0 : std_ulogic_vector(0 to 3); +signal bg_pc_l1p_abist_g8t1p_renb_0 : std_ulogic; +signal bg_pc_l1p_abist_g8t_bw_0 : std_ulogic; +signal bg_pc_l1p_abist_g8t_bw_1 : std_ulogic; +signal bg_pc_l1p_abist_g8t_dcomp : std_ulogic_vector(0 to 3); +signal bg_pc_l1p_abist_g8t_wenb : std_ulogic; +signal bg_pc_l1p_abist_raddr_0 : std_ulogic_vector(0 to 9); +signal bg_pc_l1p_abist_waddr_0 : std_ulogic_vector(0 to 9); +signal bg_pc_l1p_abist_wl128_comp_ena : std_ulogic; +signal bg_pc_l1p_abist_wl32_comp_ena : std_ulogic; +signal bg_pc_l1p_abist_di_0_q : std_ulogic_vector(0 to 3); +signal bg_pc_l1p_abist_g8t1p_renb_0_q : std_ulogic; +signal bg_pc_l1p_abist_g8t_bw_0_q : std_ulogic; +signal bg_pc_l1p_abist_g8t_bw_1_q : std_ulogic; +signal bg_pc_l1p_abist_g8t_dcomp_q : std_ulogic_vector(0 to 3); +signal bg_pc_l1p_abist_g8t_wenb_q : std_ulogic; +signal bg_pc_l1p_abist_raddr_0_q : std_ulogic_vector(0 to 9); +signal bg_pc_l1p_abist_waddr_0_q : std_ulogic_vector(0 to 9); +signal bg_pc_l1p_abist_wl128_comp_ena_q : std_ulogic; +signal bg_pc_l1p_abist_wl32_comp_ena_q : std_ulogic; + +signal bg_pc_l1p_gptr_sl_thold_3 : std_ulogic; +signal bg_pc_l1p_time_sl_thold_3 : std_ulogic; +signal bg_pc_l1p_repr_sl_thold_3 : std_ulogic; +signal bg_pc_l1p_abst_sl_thold_3 : std_ulogic; +signal bg_pc_l1p_func_sl_thold_3 : std_ulogic_vector(0 to 1); +signal bg_pc_l1p_func_slp_sl_thold_3 : std_ulogic; +signal bg_pc_l1p_bolt_sl_thold_3 : std_ulogic; +signal bg_pc_l1p_ary_nsl_thold_3 : std_ulogic; +signal bg_pc_l1p_sg_3 : std_ulogic_vector(0 to 1); +signal bg_pc_l1p_fce_3 : std_ulogic; +signal bg_pc_l1p_bo_enable_3 : std_ulogic; +signal bg_pc_l1p_gptr_sl_thold_2 : std_ulogic; +signal bg_pc_l1p_time_sl_thold_2 : std_ulogic; +signal bg_pc_l1p_repr_sl_thold_2 : std_ulogic; +signal bg_pc_l1p_abst_sl_thold_2 : std_ulogic; +signal bg_pc_l1p_func_sl_thold_2 : std_ulogic_vector(0 to 1); +signal bg_pc_l1p_func_slp_sl_thold_2 : std_ulogic; +signal bg_pc_l1p_bolt_sl_thold_2 : std_ulogic; +signal bg_pc_l1p_ary_nsl_thold_2 : std_ulogic; +signal bg_pc_l1p_sg_2 : std_ulogic_vector(0 to 1); +signal bg_pc_l1p_fce_2 : std_ulogic; +signal bg_pc_l1p_bo_enable_2 : std_ulogic; + +signal bg_pc_bo_unload_iiu : std_ulogic; +signal bg_pc_bo_load_iiu : std_ulogic; +signal bg_pc_bo_repair_iiu : std_ulogic; +signal bg_pc_bo_reset_iiu : std_ulogic; +signal bg_pc_bo_shdata_iiu : std_ulogic; +signal bg_pc_bo_select_iiu : std_ulogic_vector(0 to 10); +signal bg_pc_l1p_ccflush_dc_iiu : std_ulogic; +signal bg_pc_l1p_abist_ena_dc_iiu : std_ulogic; +signal bg_pc_l1p_abist_raw_dc_b_iiu : std_ulogic; + +signal bg_pc_bo_unload_oiu : std_ulogic; +signal bg_pc_bo_load_oiu : std_ulogic; +signal bg_pc_bo_repair_oiu : std_ulogic; +signal bg_pc_bo_reset_oiu : std_ulogic; +signal bg_pc_bo_shdata_oiu : std_ulogic; +signal bg_pc_bo_select_oiu : std_ulogic_vector(0 to 10); +signal bg_pc_l1p_ccflush_dc_oiu : std_ulogic; +signal bg_pc_l1p_abist_ena_dc_oiu : std_ulogic; +signal bg_pc_l1p_abist_raw_dc_b_oiu : std_ulogic; + +signal bg_pc_bo_fail_oiu : std_ulogic_vector(0 to 10); +signal bg_pc_bo_diagout_oiu : std_ulogic_vector(0 to 10); + +signal bg_pc_l1p_gptr_sl_thold_2_imm : std_ulogic; +signal bg_pc_l1p_time_sl_thold_2_imm : std_ulogic; +signal bg_pc_l1p_repr_sl_thold_2_imm : std_ulogic; +signal bg_pc_l1p_abst_sl_thold_2_imm : std_ulogic; +signal bg_pc_l1p_func_sl_thold_2_imm : std_ulogic_vector(0 to 1); +signal bg_pc_l1p_func_slp_sl_thold_2_imm : std_ulogic; +signal bg_pc_l1p_bolt_sl_thold_2_imm : std_ulogic; +signal bg_pc_l1p_ary_nsl_thold_2_imm : std_ulogic; +signal bg_pc_l1p_sg_2_imm : std_ulogic_vector(0 to 1); +signal bg_pc_l1p_fce_2_imm : std_ulogic; +signal bg_pc_l1p_bo_enable_2_imm : std_ulogic; +signal bg_pc_bo_unload : std_ulogic; +signal bg_pc_bo_load : std_ulogic; +signal bg_pc_bo_repair : std_ulogic; +signal bg_pc_bo_reset : std_ulogic; +signal bg_pc_bo_shdata : std_ulogic; +signal bg_pc_bo_select : std_ulogic_vector(0 to 10); +signal bg_pc_l1p_ccflush_dc : std_ulogic; +signal bg_pc_l1p_abist_ena_dc : std_ulogic; +signal bg_pc_l1p_abist_raw_dc_b : std_ulogic; +signal bg_an_ac_func_scan_sn_omm : std_ulogic_vector(60 to 69); +signal bg_an_ac_abst_scan_sn_omm : std_ulogic_vector(10 to 11); +signal bg_pc_bo_fail : std_ulogic_vector(0 to 10); +signal bg_pc_bo_diagout : std_ulogic_vector(0 to 10); +signal bg_pc_bo_fail_omm : std_ulogic_vector(0 to 10); +signal bg_pc_bo_diagout_omm : std_ulogic_vector(0 to 10); + +signal xu_fu_lbist_en_dc : std_ulogic; +signal xu_iu_xucr4_mmu_mchk : std_ulogic; +signal xu_mm_xucr4_mmu_mchk : std_ulogic; + +-- synopsys translate_off + + + + + + + + + +-- synopsys translate_on + + +BEGIN + + +debug_start_tiedowns <= (0 to 87 => '0'); +trigger_start_tiedowns <= (0 to 11 => '0'); + +ac_rp_trace_to_perfcntr <= debug_bus_out_int; +ac_an_debug_bus <= ac_an_debug_bus_int; + +ac_an_power_managed_imm <= ac_an_power_managed_int; + +a2_nclk_copy <= a2_nclk; + + +an_ac_bo_enable <= '0'; +an_ac_bo_go <= '0'; +an_ac_bo_cntlclk <= '0'; +an_ac_bo_ccflush <= '1'; +an_ac_bo_reset <= '0'; +an_ac_bo_data <= '0'; +an_ac_bo_shcntl <= '0'; +an_ac_bo_shdata <= '0'; +an_ac_bo_exe <= '0'; +an_ac_bo_sysrepair <= '0'; +an_ac_bo_donein <= '0'; +an_ac_bo_sdin <= '0'; +an_ac_bo_waitin <= '0'; +an_ac_bo_failin <= '0'; +an_ac_bo_fcshdata <= '0'; +an_ac_bo_fcreset <= '0'; + + bg_an_ac_func_scan_sn <= "0000000000"; + bg_an_ac_abst_scan_sn <= "00"; + bg_pc_l1p_gptr_sl_thold_3 <= '0'; + bg_pc_l1p_time_sl_thold_3 <= '0'; + bg_pc_l1p_repr_sl_thold_3 <= '0'; + bg_pc_l1p_abst_sl_thold_3 <= '0'; + bg_pc_l1p_func_sl_thold_3 <= "00"; + bg_pc_l1p_func_slp_sl_thold_3 <= '0'; + bg_pc_l1p_bolt_sl_thold_3 <= '0'; + bg_pc_l1p_ary_nsl_thold_3 <= '0'; + bg_pc_l1p_sg_3 <= "00"; + bg_pc_l1p_fce_3 <= '0'; + bg_pc_l1p_bo_enable_3 <= '0'; + bg_pc_bo_unload_iiu <= '0'; + bg_pc_bo_load_iiu <= '0'; + bg_pc_bo_repair_iiu <= '0'; + bg_pc_bo_reset_iiu <= '0'; + bg_pc_bo_shdata_iiu <= '0'; + bg_pc_bo_select_iiu <= "00000000000"; + bg_pc_l1p_ccflush_dc_iiu <= '0'; + bg_pc_l1p_abist_ena_dc_iiu <= '0'; + bg_pc_l1p_abist_raw_dc_b_iiu <= '0'; + bg_pc_bo_fail <= "00000000000"; + bg_pc_bo_diagout <= "00000000000"; + + +spr_pvr_version_dc <= "01001000"; +spr_pvr_revision_dc <= "0010"; + + +a_fuq: entity work.fuq + generic map(expand_type => expand_type, eff_ifar => xu_eff_ifar, regmode => regmode) + port map ( + an_ac_abist_mode_dc => an_ac_abist_mode_dc_oiu, + an_ac_lbist_ary_wrt_thru_dc => xu_fu_lbist_ary_wrt_thru_dc, + an_ac_lbist_en_dc => xu_fu_lbist_en_dc, + pc_fu_ccflush_dc => pc_fu_ccflush_dc, + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b_opc, + an_ac_scan_diag_dc => an_ac_scan_diag_dc_opc, + abst_scan_in => rp_fu_abst_scan_in_q, + bcfg_scan_in => iu_fu_bcfg_scan_out, + ccfg_scan_in => xu_fu_ccfg_scan_out, + dcfg_scan_in => iu_fu_dcfg_scan_out, + func_scan_in => rp_fu_func_scan_in_q(0 to 3), + gptr_scan_in => pc_fu_gptr_scan_out, + repr_scan_in => iu_fu_repr_scan_out, + time_scan_in => iu_fu_time_scan_out, + bx_fu_rp_abst_scan_out => bx_fu_rp_abst_scan_out, + bx_rp_abst_scan_out => bx_rp_abst_scan_out, + rp_bx_abst_scan_in => rp_bx_abst_scan_in_q, + rp_fu_bx_abst_scan_in => rp_fu_bx_abst_scan_in, + rp_bx_func_scan_in => rp_bx_func_scan_in_q, + rp_fu_bx_func_scan_in => rp_fu_bx_func_scan_in, + bx_fu_rp_func_scan_out => bx_fu_rp_func_scan_out, + bx_rp_func_scan_out => bx_rp_func_scan_out, + debug_data_in => bx_fu_debug_data, + trace_triggers_in => bx_fu_trigger_data, + iu_fu_ex2_n_flush => iu_fu_ex2_n_flush, + iu_fu_is2_tid_decode => iu_fu_is2_tid_decode, + iu_fu_rf0_bypsel => iu_fu_rf0_bypsel, + iu_fu_rf0_fra => iu_fu_rf0_fra, + iu_fu_rf0_fra_v => iu_fu_rf0_fra_v, + iu_fu_rf0_frb => iu_fu_rf0_frb, + iu_fu_rf0_frb_v => iu_fu_rf0_frb_v, + iu_fu_rf0_frc => iu_fu_rf0_frc, + iu_fu_rf0_frc_v => iu_fu_rf0_frc_v, + iu_fu_rf0_frt => iu_fu_rf0_frt, + iu_fu_rf0_ifar => iu_fu_rf0_ifar, + iu_fu_rf0_instr => iu_fu_rf0_instr, + iu_fu_rf0_instr_match => iu_fu_rf0_instr_match, + iu_fu_rf0_instr_v => iu_fu_rf0_instr_v, + iu_fu_rf0_is_ucode => iu_fu_rf0_is_ucode, + iu_fu_rf0_ucfmul => iu_fu_rf0_ucfmul, + iu_fu_rf0_ldst_val => iu_fu_rf0_ldst_val, + iu_fu_rf0_ldst_tid => iu_fu_rf0_ldst_tid, + iu_fu_rf0_ldst_tag => iu_fu_rf0_ldst_tag, + iu_fu_rf0_str_val => iu_fu_rf0_str_val, + iu_fu_rf0_tid => iu_fu_rf0_tid, + nclk => a2_nclk, + pc_fu_abist_di_0 => pc_fu_abist_di_0(0 to 3), + pc_fu_abist_di_1 => pc_fu_abist_di_1(0 to 3), + pc_fu_abist_ena_dc => pc_fu_abist_ena_dc, + pc_fu_abist_grf_renb_0 => pc_fu_abist_grf_renb_0, + pc_fu_abist_grf_renb_1 => pc_fu_abist_grf_renb_1, + pc_fu_abist_grf_wenb_0 => pc_fu_abist_grf_wenb_0, + pc_fu_abist_grf_wenb_1 => pc_fu_abist_grf_wenb_1, + pc_fu_abist_raddr_0 => pc_fu_abist_raddr_0(0 to 9), + pc_fu_abist_raddr_1 => pc_fu_abist_raddr_1(0 to 9), + pc_fu_abist_raw_dc_b => pc_fu_abist_raw_dc_b, + pc_fu_abist_waddr_0 => pc_fu_abist_waddr_0(0 to 9), + pc_fu_abist_waddr_1 => pc_fu_abist_waddr_1(0 to 9), + pc_fu_abist_wl144_comp_ena => pc_fu_abist_wl144_comp_ena, + pc_fu_abst_sl_thold_3 => pc_fu_abst_sl_thold_3, + pc_fu_abst_slp_sl_thold_3 => pc_fu_abst_slp_sl_thold_3, + pc_fu_ary_nsl_thold_3 => pc_fu_ary_nsl_thold_3, + pc_fu_ary_slp_nsl_thold_3 => pc_fu_ary_slp_nsl_thold_3, + pc_fu_bolt_sl_thold_3 => pc_fu_bolt_sl_thold_3, + pc_fu_bo_enable_3 => pc_fu_bo_enable_3, + pc_fu_bo_unload => pc_fu_bo_unload, + pc_fu_bo_load => pc_fu_bo_load, + pc_fu_bo_reset => pc_fu_bo_reset, + pc_fu_bo_shdata => pc_fu_bo_shdata, + pc_fu_bo_select => pc_fu_bo_select, + pc_fu_cfg_sl_thold_3 => pc_fu_cfg_sl_thold_3, + pc_fu_cfg_slp_sl_thold_3 => pc_fu_cfg_slp_sl_thold_3, + pc_fu_debug_mux_ctrls => pc_fu_debug_mux1_ctrls, + pc_fu_event_mux_ctrls => pc_fu_event_mux_ctrls, + pc_fu_event_count_mode => pc_fu_event_count_mode, + pc_fu_fce_3 => pc_fu_fce_3, + pc_fu_func_nsl_thold_3 => pc_fu_func_nsl_thold_3, + pc_fu_func_sl_thold_3 => pc_fu_func_sl_thold_3, + pc_fu_func_slp_nsl_thold_3 => pc_fu_func_slp_nsl_thold_3, + pc_fu_func_slp_sl_thold_3 => pc_fu_func_slp_sl_thold_3, + pc_fu_gptr_sl_thold_3 => pc_fu_gptr_sl_thold_3, + pc_fu_inj_regfile_parity => pc_fu_inj_regfile_parity, + pc_fu_instr_trace_mode => pc_fu_instr_trace_mode, + pc_fu_instr_trace_tid => pc_fu_instr_trace_tid, + pc_fu_ram_mode => pc_fu_ram_mode, + pc_fu_ram_thread => pc_fu_ram_thread, + pc_fu_repr_sl_thold_3 => pc_fu_repr_sl_thold_3, + pc_fu_sg_3 => pc_fu_sg_3, + slowspr_addr_in => pc_fu_slowspr_addr, + slowspr_data_in => pc_fu_slowspr_data, + slowspr_done_in => pc_fu_slowspr_done, + slowspr_etid_in => pc_fu_slowspr_etid, + slowspr_rw_in => pc_fu_slowspr_rw, + slowspr_val_in => pc_fu_slowspr_val, + pc_fu_time_sl_thold_3 => pc_fu_time_sl_thold_3, + pc_fu_trace_bus_enable => pc_fu_trace_bus_enable, + pc_fu_event_bus_enable => pc_fu_event_bus_enable, + xu_ex1_flush => xu_n_ex1_flush, + xu_ex2_flush => xu_n_ex2_flush, + xu_ex3_flush => xu_n_ex3_flush, + xu_ex4_flush => xu_n_ex4_flush, + xu_ex5_flush => xu_n_ex5_flush, + xu_fu_ex3_eff_addr => xu_fu_ex3_eff_addr, + xu_fu_ex6_load_data => xu_fu_ex6_load_data(192 to 255), + xu_fu_ex5_load_le => xu_fu_ex5_load_le, + xu_fu_ex5_load_tag => xu_fu_ex5_load_tag, + xu_fu_ex5_load_val => xu_fu_ex5_load_val, + xu_fu_ex5_reload_val => xu_fu_ex5_reload_val, + xu_fu_msr_fp => xu_fu_msr_fp, + xu_fu_msr_pr => xu_fu_msr_pr, + xu_fu_msr_gs => xu_fu_msr_gs, + xu_fu_regfile_seq_beg => xu_fu_regfile_seq_beg, + xu_is2_flush => xu_n_is2_flush, + xu_rf0_flush => xu_n_rf0_flush, + xu_rf1_flush => xu_n_rf1_flush, + abst_scan_out => fu_rp_abst_scan_out, + bcfg_scan_out => fu_rp_bcfg_scan_out, + ccfg_scan_out => fu_rp_ccfg_scan_out, + dcfg_scan_out => fu_rp_dcfg_scan_out, + func_scan_out => fu_rp_func_scan_out(0 to 3), + gptr_scan_out => fu_bx_gptr_scan_out, + repr_scan_out => fu_bx_repr_scan_out, + time_scan_out => fu_bx_time_scan_out, + debug_data_out => fu_pc_debug_data, + trace_triggers_out => fu_pc_trigger_data, + fu_iu_uc_special => fu_iu_uc_special, + fu_pc_bo_fail => fu_pc_bo_fail, + fu_pc_bo_diagout => fu_pc_bo_diagout, + fu_pc_err_regfile_parity => fu_pc_err_regfile_parity, + fu_pc_err_regfile_ue => fu_pc_err_regfile_ue, + fu_pc_event_data => fu_pc_event_data, + fu_pc_ram_data => fu_pc_ram_data, + fu_pc_ram_done => fu_pc_ram_done, + fu_xu_ex1_ifar => fu_xu_ex1_ifar, + fu_xu_ex2_async_block => fu_xu_ex2_async_block, + fu_xu_ex2_ifar_val => fu_xu_ex2_ifar_val, + fu_xu_ex2_ifar_issued => fu_xu_ex2_ifar_issued, + fu_xu_ex2_store_data => fu_xu_ex2_store_data, + fu_xu_ex2_store_data_val => fu_xu_ex2_store_data_val, + fu_xu_ex3_flush2ucode => fu_xu_ex3_flush2ucode, + fu_xu_ex2_instr_match => fu_xu_ex2_instr_match, + fu_xu_ex2_instr_type => fu_xu_ex2_instr_type, + fu_xu_ex2_is_ucode => fu_xu_ex2_is_ucode, + fu_xu_ex3_ap_int_req => fu_xu_ex3_ap_int_req, + fu_xu_ex3_n_flush => fu_xu_ex3_n_flush, + fu_xu_ex3_np1_flush => fu_xu_ex3_np1_flush, + fu_xu_ex3_regfile_err_det => fu_xu_ex3_regfile_err_det, + fu_xu_ex3_trap => fu_xu_ex3_trap, + fu_xu_ex4_cr => fu_xu_ex4_cr, + fu_xu_ex4_cr_bf => fu_xu_ex4_cr_bf, + fu_xu_ex4_cr_noflush => fu_xu_ex4_cr_noflush, + fu_xu_ex4_cr_val => fu_xu_ex4_cr_val, + fu_xu_regfile_seq_end => fu_xu_regfile_seq_end, + fu_xu_rf1_act => fu_xu_rf1_act, + slowspr_addr_out => fu_bx_slowspr_addr, + slowspr_data_out => fu_bx_slowspr_data, + slowspr_done_out => fu_bx_slowspr_done, + slowspr_etid_out => fu_bx_slowspr_etid, + slowspr_rw_out => fu_bx_slowspr_rw, + slowspr_val_out => fu_bx_slowspr_val, + + bx_pc_err_inbox_ue_ifu => bx_pc_err_inbox_ue, + bx_pc_err_outbox_ue_ifu => bx_pc_err_outbox_ue, + bx_pc_err_inbox_ecc_ifu => bx_pc_err_inbox_ecc, + bx_pc_err_outbox_ecc_ifu => bx_pc_err_outbox_ecc, + pc_bx_bolt_sl_thold_3_ifu => pc_bx_bolt_sl_thold_3, + pc_bx_bo_enable_3_ifu => pc_bx_bo_enable_3, + pc_bx_bo_unload_ifu => pc_bx_bo_unload, + pc_bx_bo_repair_ifu => pc_bx_bo_repair, + pc_bx_bo_reset_ifu => pc_bx_bo_reset, + pc_bx_bo_shdata_ifu => pc_bx_bo_shdata, + pc_bx_bo_select_ifu => pc_bx_bo_select, + bx_pc_bo_fail_ifu => bx_pc_bo_fail, + bx_pc_bo_diagout_ifu => bx_pc_bo_diagout, + pc_bx_abist_di_0_ifu => pc_bx_abist_di_0, + pc_bx_abist_ena_dc_ifu => pc_bx_abist_ena_dc, + pc_bx_abist_g8t1p_renb_0_ifu => pc_bx_abist_g8t1p_renb_0, + pc_bx_abist_g8t_bw_0_ifu => pc_bx_abist_g8t_bw_0, + pc_bx_abist_g8t_bw_1_ifu => pc_bx_abist_g8t_bw_1, + pc_bx_abist_g8t_dcomp_ifu => pc_bx_abist_g8t_dcomp, + pc_bx_abist_g8t_wenb_ifu => pc_bx_abist_g8t_wenb, + pc_bx_abist_raddr_0_ifu => pc_bx_abist_raddr_0(4 to 9), + pc_bx_abist_raw_dc_b_ifu => pc_bx_abist_raw_dc_b, + pc_bx_abist_waddr_0_ifu => pc_bx_abist_waddr_0(4 to 9), + pc_bx_abist_wl64_comp_ena_ifu => pc_bx_abist_wl64_comp_ena, + pc_bx_trace_bus_enable_ifu => pc_bx_trace_bus_enable, + pc_bx_debug_mux1_ctrls_ifu => pc_bx_debug_mux1_ctrls, + pc_bx_inj_inbox_ecc_ifu => pc_bx_inj_inbox_ecc, + pc_bx_inj_outbox_ecc_ifu => pc_bx_inj_outbox_ecc, + pc_bx_ccflush_dc_ifu => pc_bx_ccflush_dc, + pc_bx_sg_3_ifu => pc_bx_sg_3, + pc_bx_func_sl_thold_3_ifu => pc_bx_func_sl_thold_3, + pc_bx_func_slp_sl_thold_3_ifu => pc_bx_func_slp_sl_thold_3, + pc_bx_gptr_sl_thold_3_ifu => pc_bx_gptr_sl_thold_3, + pc_bx_time_sl_thold_3_ifu => pc_bx_time_sl_thold_3, + pc_bx_repr_sl_thold_3_ifu => pc_bx_repr_sl_thold_3, + pc_bx_abst_sl_thold_3_ifu => pc_bx_abst_sl_thold_3, + pc_bx_ary_nsl_thold_3_ifu => pc_bx_ary_nsl_thold_3, + pc_bx_ary_slp_nsl_thold_3_ifu => pc_bx_ary_slp_nsl_thold_3, + + xu_pc_err_mcsr_summary_ifu => xu_pc_err_mcsr_summary, + xu_pc_err_ierat_parity_ifu => xu_pc_err_ierat_parity, + xu_pc_err_derat_parity_ifu => xu_pc_err_derat_parity, + xu_pc_err_tlb_parity_ifu => xu_pc_err_tlb_parity, + xu_pc_err_tlb_lru_parity_ifu => xu_pc_err_tlb_lru_parity, + xu_pc_err_ierat_multihit_ifu => xu_pc_err_ierat_multihit, + xu_pc_err_derat_multihit_ifu => xu_pc_err_derat_multihit, + xu_pc_err_tlb_multihit_ifu => xu_pc_err_tlb_multihit, + xu_pc_err_ext_mchk_ifu => xu_pc_err_ext_mchk, + xu_pc_err_ditc_overrun_ifu => xu_pc_err_ditc_overrun, + xu_pc_err_local_snoop_reject_ifu => xu_pc_err_local_snoop_reject, + xu_pc_err_attention_instr_ifu => xu_pc_err_attention_instr, + xu_pc_err_dcache_parity_ifu => xu_pc_err_dcache_parity, + xu_pc_err_dcachedir_parity_ifu => xu_pc_err_dcachedir_parity, + xu_pc_err_dcachedir_multihit_ifu => xu_pc_err_dcachedir_multihit, + xu_pc_err_debug_event_ifu => xu_pc_err_debug_event, + xu_pc_err_invld_reld_ifu => xu_pc_err_invld_reld, + xu_pc_err_l2intrf_ecc_ifu => xu_pc_err_l2intrf_ecc, + xu_pc_err_l2intrf_ue_ifu => xu_pc_err_l2intrf_ue, + xu_pc_err_l2credit_overrun_ifu => xu_pc_err_l2credit_overrun, + xu_pc_err_llbust_attempt_ifu => xu_pc_err_llbust_attempt, + xu_pc_err_llbust_failed_ifu => xu_pc_err_llbust_failed, + xu_pc_err_nia_miscmpr_ifu => xu_pc_err_nia_miscmpr, + xu_pc_err_regfile_parity_ifu => xu_pc_err_regfile_parity, + xu_pc_err_regfile_ue_ifu => xu_pc_err_regfile_ue, + xu_pc_err_sprg_ecc_ifu => xu_pc_err_sprg_ecc, + xu_pc_err_sprg_ue_ifu => xu_pc_err_sprg_ue, + xu_pc_err_wdt_reset_ifu => xu_pc_err_wdt_reset, + xu_pc_event_data_ifu => xu_pc_event_data, + xu_pc_ram_data_ifu => xu_pc_ram_data, + xu_pc_ram_done_ifu => xu_pc_ram_done, + xu_pc_ram_interrupt_ifu => xu_pc_ram_interrupt, + xu_pc_running_ifu => xu_pc_running, + xu_pc_spr_ccr0_pme_ifu => xu_pc_spr_ccr0_pme, + xu_pc_spr_ccr0_we_ifu => xu_pc_spr_ccr0_we, + xu_pc_step_done_ifu => xu_pc_step_done, + xu_pc_stop_dbg_event_ifu => xu_pc_stop_dbg_event, + pc_xu_bolt_sl_thold_3_ifu => pc_xu_bolt_sl_thold_3, + pc_xu_bo_enable_3_ifu => pc_xu_bo_enable_3, + pc_xu_bo_unload_ifu => pc_xu_bo_unload, + pc_xu_bo_load_ifu => pc_xu_bo_load, + pc_xu_bo_repair_ifu => pc_xu_bo_repair, + pc_xu_bo_reset_ifu => pc_xu_bo_reset, + pc_xu_bo_shdata_ifu => pc_xu_bo_shdata, + pc_xu_bo_select_ifu => pc_xu_bo_select, + xu_pc_bo_fail_ifu => xu_pc_bo_fail, + xu_pc_bo_diagout_ifu => xu_pc_bo_diagout, + pc_xu_abist_dcomp_g6t_2r_ifu => pc_xu_abist_dcomp_g6t_2r, + pc_xu_abist_di_0_ifu => pc_xu_abist_di_0, + pc_xu_abist_di_1_ifu => pc_xu_abist_di_1, + pc_xu_abist_di_g6t_2r_ifu => pc_xu_abist_di_g6t_2r, + pc_xu_abist_ena_dc_ifu => pc_xu_abist_ena_dc, + pc_xu_abist_g6t_bw_ifu => pc_xu_abist_g6t_bw, + pc_xu_abist_g6t_r_wb_ifu => pc_xu_abist_g6t_r_wb, + pc_xu_abist_g8t1p_renb_0_ifu => pc_xu_abist_g8t1p_renb_0, + pc_xu_abist_g8t_bw_0_ifu => pc_xu_abist_g8t_bw_0, + pc_xu_abist_g8t_bw_1_ifu => pc_xu_abist_g8t_bw_1, + pc_xu_abist_g8t_dcomp_ifu => pc_xu_abist_g8t_dcomp, + pc_xu_abist_g8t_wenb_ifu => pc_xu_abist_g8t_wenb, + pc_xu_abist_grf_renb_0_ifu => pc_xu_abist_grf_renb_0, + pc_xu_abist_grf_renb_1_ifu => pc_xu_abist_grf_renb_1, + pc_xu_abist_grf_wenb_0_ifu => pc_xu_abist_grf_wenb_0, + pc_xu_abist_grf_wenb_1_ifu => pc_xu_abist_grf_wenb_1, + pc_xu_abist_raddr_0_ifu => pc_xu_abist_raddr_0, + pc_xu_abist_raddr_1_ifu => pc_xu_abist_raddr_1, + pc_xu_abist_raw_dc_b_ifu => pc_xu_abist_raw_dc_b, + pc_xu_abist_waddr_0_ifu => pc_xu_abist_waddr_0, + pc_xu_abist_waddr_1_ifu => pc_xu_abist_waddr_1, + pc_xu_abist_wl144_comp_ena_ifu => pc_xu_abist_wl144_comp_ena, + pc_xu_abist_wl32_comp_ena_ifu => pc_xu_abist_wl32_comp_ena, + pc_xu_abist_wl512_comp_ena_ifu => pc_xu_abist_wl512_comp_ena, + pc_xu_event_mux_ctrls_ifu => pc_xu_event_mux_ctrls, + pc_xu_lsu_event_mux_ctrls_ifu => pc_xu_lsu_event_mux_ctrls, + pc_xu_event_bus_enable_ifu => pc_xu_event_bus_enable, + pc_xu_abst_sl_thold_3_ifu => pc_xu_abst_sl_thold_3, + pc_xu_abst_slp_sl_thold_3_ifu => pc_xu_abst_slp_sl_thold_3, + pc_xu_regf_sl_thold_3_ifu => pc_xu_regf_sl_thold_3, + pc_xu_regf_slp_sl_thold_3_ifu => pc_xu_regf_slp_sl_thold_3, + pc_xu_ary_nsl_thold_3_ifu => pc_xu_ary_nsl_thold_3, + pc_xu_ary_slp_nsl_thold_3_ifu => pc_xu_ary_slp_nsl_thold_3, + pc_xu_cache_par_err_event_ifu => pc_xu_cache_par_err_event, + pc_xu_ccflush_dc_ifu => pc_xu_ccflush_dc, + pc_xu_cfg_sl_thold_3_ifu => pc_xu_cfg_sl_thold_3, + pc_xu_cfg_slp_sl_thold_3_ifu => pc_xu_cfg_slp_sl_thold_3, + pc_xu_dbg_action_ifu => pc_xu_dbg_action, + pc_xu_debug_mux1_ctrls_ifu => pc_xu_debug_mux1_ctrls, + pc_xu_debug_mux2_ctrls_ifu => pc_xu_debug_mux2_ctrls, + pc_xu_debug_mux3_ctrls_ifu => pc_xu_debug_mux3_ctrls, + pc_xu_debug_mux4_ctrls_ifu => pc_xu_debug_mux4_ctrls, + pc_xu_decrem_dis_on_stop_ifu => pc_xu_decrem_dis_on_stop, + pc_xu_event_count_mode_ifu => pc_xu_event_count_mode, + pc_xu_extirpts_dis_on_stop_ifu => pc_xu_extirpts_dis_on_stop, + pc_xu_fce_3_ifu => pc_xu_fce_3, + pc_xu_force_ude_ifu => pc_xu_force_ude, + pc_xu_func_nsl_thold_3_ifu => pc_xu_func_nsl_thold_3, + pc_xu_func_sl_thold_3_ifu => pc_xu_func_sl_thold_3, + pc_xu_func_slp_nsl_thold_3_ifu => pc_xu_func_slp_nsl_thold_3, + pc_xu_func_slp_sl_thold_3_ifu => pc_xu_func_slp_sl_thold_3, + pc_xu_gptr_sl_thold_3_ifu => pc_xu_gptr_sl_thold_3, + pc_xu_init_reset_ifu => pc_xu_init_reset, + pc_xu_inj_dcache_parity_ifu => pc_xu_inj_dcache_parity, + pc_xu_inj_dcachedir_parity_ifu => pc_xu_inj_dcachedir_parity, + pc_xu_inj_llbust_attempt_ifu => pc_xu_inj_llbust_attempt, + pc_xu_inj_llbust_failed_ifu => pc_xu_inj_llbust_failed, + pc_xu_inj_sprg_ecc_ifu => pc_xu_inj_sprg_ecc, + pc_xu_inj_regfile_parity_ifu => pc_xu_inj_regfile_parity, + pc_xu_inj_wdt_reset_ifu => pc_xu_inj_wdt_reset, + pc_xu_inj_dcachedir_multihit_ifu => pc_xu_inj_dcachedir_multihit, + pc_xu_instr_trace_mode_ifu => pc_xu_instr_trace_mode, + pc_xu_instr_trace_tid_ifu => pc_xu_instr_trace_tid, + pc_xu_msrovride_enab_ifu => pc_xu_msrovride_enab, + pc_xu_msrovride_gs_ifu => pc_xu_msrovride_gs, + pc_xu_msrovride_pr_ifu => pc_xu_msrovride_pr, + pc_xu_ram_execute_ifu => pc_xu_ram_execute, + pc_xu_ram_flush_thread_ifu => pc_xu_ram_flush_thread, + pc_xu_ram_mode_ifu => pc_xu_ram_mode, + pc_xu_ram_thread_ifu => pc_xu_ram_thread, + pc_xu_repr_sl_thold_3_ifu => pc_xu_repr_sl_thold_3, + pc_xu_reset_1_cmplt_ifu => pc_xu_reset_1_complete, + pc_xu_reset_2_cmplt_ifu => pc_xu_reset_2_complete, + pc_xu_reset_3_cmplt_ifu => pc_xu_reset_3_complete, + pc_xu_reset_wd_cmplt_ifu => pc_xu_reset_wd_complete, + pc_xu_sg_3_ifu => pc_xu_sg_3, + pc_xu_step_ifu => pc_xu_step, + pc_xu_stop_ifu => pc_xu_stop, + pc_xu_time_sl_thold_3_ifu => pc_xu_time_sl_thold_3, + pc_xu_timebase_dis_on_stop_ifu => pc_xu_timebase_dis_on_stop, + pc_xu_trace_bus_enable_ifu => pc_xu_trace_bus_enable, + + bx_pc_err_inbox_ue_ofu => bx_pc_err_inbox_ue_ofu , + bx_pc_err_outbox_ue_ofu => bx_pc_err_outbox_ue_ofu, + bx_pc_err_inbox_ecc_ofu => bx_pc_err_inbox_ecc_ofu, + bx_pc_err_outbox_ecc_ofu => bx_pc_err_outbox_ecc_ofu, + pc_bx_bolt_sl_thold_3_ofu => pc_bx_bolt_sl_thold_3_ofu, + pc_bx_bo_enable_3_ofu => pc_bx_bo_enable_3_ofu , + pc_bx_bo_unload_ofu => pc_bx_bo_unload_ofu , + pc_bx_bo_repair_ofu => pc_bx_bo_repair_ofu , + pc_bx_bo_reset_ofu => pc_bx_bo_reset_ofu , + pc_bx_bo_shdata_ofu => pc_bx_bo_shdata_ofu , + pc_bx_bo_select_ofu => pc_bx_bo_select_ofu , + bx_pc_bo_fail_ofu => bx_pc_bo_fail_ofu , + bx_pc_bo_diagout_ofu => bx_pc_bo_diagout_ofu , + pc_bx_abist_di_0_ofu => pc_bx_abist_di_0_ofu , + pc_bx_abist_ena_dc_ofu => pc_bx_abist_ena_dc_ofu , + pc_bx_abist_g8t1p_renb_0_ofu => pc_bx_abist_g8t1p_renb_0_ofu, + pc_bx_abist_g8t_bw_0_ofu => pc_bx_abist_g8t_bw_0_ofu, + pc_bx_abist_g8t_bw_1_ofu => pc_bx_abist_g8t_bw_1_ofu, + pc_bx_abist_g8t_dcomp_ofu => pc_bx_abist_g8t_dcomp_ofu, + pc_bx_abist_g8t_wenb_ofu => pc_bx_abist_g8t_wenb_ofu, + pc_bx_abist_raddr_0_ofu => pc_bx_abist_raddr_0_ofu, + pc_bx_abist_raw_dc_b_ofu => pc_bx_abist_raw_dc_b_ofu, + pc_bx_abist_waddr_0_ofu => pc_bx_abist_waddr_0_ofu, + pc_bx_abist_wl64_comp_ena_ofu => pc_bx_abist_wl64_comp_ena_ofu, + pc_bx_trace_bus_enable_ofu => pc_bx_trace_bus_enable_ofu, + pc_bx_debug_mux1_ctrls_ofu => pc_bx_debug_mux1_ctrls_ofu, + pc_bx_inj_inbox_ecc_ofu => pc_bx_inj_inbox_ecc_ofu, + pc_bx_inj_outbox_ecc_ofu => pc_bx_inj_outbox_ecc_ofu, + pc_bx_ccflush_dc_ofu => pc_bx_ccflush_dc_ofu , + pc_bx_sg_3_ofu => pc_bx_sg_3_ofu , + pc_bx_func_sl_thold_3_ofu => pc_bx_func_sl_thold_3_ofu, + pc_bx_func_slp_sl_thold_3_ofu => pc_bx_func_slp_sl_thold_3_ofu, + pc_bx_gptr_sl_thold_3_ofu => pc_bx_gptr_sl_thold_3_ofu, + pc_bx_time_sl_thold_3_ofu => pc_bx_time_sl_thold_3_ofu, + pc_bx_repr_sl_thold_3_ofu => pc_bx_repr_sl_thold_3_ofu, + pc_bx_abst_sl_thold_3_ofu => pc_bx_abst_sl_thold_3_ofu, + pc_bx_ary_nsl_thold_3_ofu => pc_bx_ary_nsl_thold_3_ofu, + pc_bx_ary_slp_nsl_thold_3_ofu => pc_bx_ary_slp_nsl_thold_3_ofu, + + xu_pc_err_mcsr_summary_ofu => xu_pc_err_mcsr_summary_ofu , + xu_pc_err_ierat_parity_ofu => xu_pc_err_ierat_parity_ofu , + xu_pc_err_derat_parity_ofu => xu_pc_err_derat_parity_ofu , + xu_pc_err_tlb_parity_ofu => xu_pc_err_tlb_parity_ofu , + xu_pc_err_tlb_lru_parity_ofu => xu_pc_err_tlb_lru_parity_ofu , + xu_pc_err_ierat_multihit_ofu => xu_pc_err_ierat_multihit_ofu , + xu_pc_err_derat_multihit_ofu => xu_pc_err_derat_multihit_ofu , + xu_pc_err_tlb_multihit_ofu => xu_pc_err_tlb_multihit_ofu , + xu_pc_err_ext_mchk_ofu => xu_pc_err_ext_mchk_ofu , + xu_pc_err_ditc_overrun_ofu => xu_pc_err_ditc_overrun_ofu , + xu_pc_err_local_snoop_reject_ofu => xu_pc_err_local_snoop_reject_ofu , + xu_pc_err_attention_instr_ofu => xu_pc_err_attention_instr_ofu , + xu_pc_err_dcache_parity_ofu => xu_pc_err_dcache_parity_ofu , + xu_pc_err_dcachedir_parity_ofu => xu_pc_err_dcachedir_parity_ofu , + xu_pc_err_dcachedir_multihit_ofu => xu_pc_err_dcachedir_multihit_ofu , + xu_pc_err_debug_event_ofu => xu_pc_err_debug_event_ofu , + xu_pc_err_invld_reld_ofu => xu_pc_err_invld_reld_ofu , + xu_pc_err_l2intrf_ecc_ofu => xu_pc_err_l2intrf_ecc_ofu , + xu_pc_err_l2intrf_ue_ofu => xu_pc_err_l2intrf_ue_ofu , + xu_pc_err_l2credit_overrun_ofu => xu_pc_err_l2credit_overrun_ofu , + xu_pc_err_llbust_attempt_ofu => xu_pc_err_llbust_attempt_ofu , + xu_pc_err_llbust_failed_ofu => xu_pc_err_llbust_failed_ofu , + xu_pc_err_nia_miscmpr_ofu => xu_pc_err_nia_miscmpr_ofu , + xu_pc_err_regfile_parity_ofu => xu_pc_err_regfile_parity_ofu , + xu_pc_err_regfile_ue_ofu => xu_pc_err_regfile_ue_ofu , + xu_pc_err_sprg_ecc_ofu => xu_pc_err_sprg_ecc_ofu , + xu_pc_err_sprg_ue_ofu => xu_pc_err_sprg_ue_ofu , + xu_pc_err_wdt_reset_ofu => xu_pc_err_wdt_reset_ofu , + xu_pc_event_data_ofu => xu_pc_event_data_ofu , + xu_pc_ram_data_ofu => xu_pc_ram_data_ofu , + xu_pc_ram_done_ofu => xu_pc_ram_done_ofu , + xu_pc_ram_interrupt_ofu => xu_pc_ram_interrupt_ofu , + xu_pc_running_ofu => xu_pc_running_ofu , + xu_pc_spr_ccr0_pme_ofu => xu_pc_spr_ccr0_pme_ofu , + xu_pc_spr_ccr0_we_ofu => xu_pc_spr_ccr0_we_ofu , + xu_pc_step_done_ofu => xu_pc_step_done_ofu , + xu_pc_stop_dbg_event_ofu => xu_pc_stop_dbg_event_ofu , + pc_xu_bolt_sl_thold_3_ofu => pc_xu_bolt_sl_thold_3_ofu , + pc_xu_bo_enable_3_ofu => pc_xu_bo_enable_3_ofu , + pc_xu_bo_unload_ofu => pc_xu_bo_unload_ofu , + pc_xu_bo_load_ofu => pc_xu_bo_load_ofu , + pc_xu_bo_repair_ofu => pc_xu_bo_repair_ofu , + pc_xu_bo_reset_ofu => pc_xu_bo_reset_ofu , + pc_xu_bo_shdata_ofu => pc_xu_bo_shdata_ofu , + pc_xu_bo_select_ofu => pc_xu_bo_select_ofu , + xu_pc_bo_fail_ofu => xu_pc_bo_fail_ofu , + xu_pc_bo_diagout_ofu => xu_pc_bo_diagout_ofu , + pc_xu_abist_dcomp_g6t_2r_ofu => pc_xu_abist_dcomp_g6t_2r_ofu , + pc_xu_abist_di_0_ofu => pc_xu_abist_di_0_ofu , + pc_xu_abist_di_1_ofu => pc_xu_abist_di_1_ofu , + pc_xu_abist_di_g6t_2r_ofu => pc_xu_abist_di_g6t_2r_ofu , + pc_xu_abist_ena_dc_ofu => pc_xu_abist_ena_dc_ofu , + pc_xu_abist_g6t_bw_ofu => pc_xu_abist_g6t_bw_ofu , + pc_xu_abist_g6t_r_wb_ofu => pc_xu_abist_g6t_r_wb_ofu , + pc_xu_abist_g8t1p_renb_0_ofu => pc_xu_abist_g8t1p_renb_0_ofu , + pc_xu_abist_g8t_bw_0_ofu => pc_xu_abist_g8t_bw_0_ofu , + pc_xu_abist_g8t_bw_1_ofu => pc_xu_abist_g8t_bw_1_ofu , + pc_xu_abist_g8t_dcomp_ofu => pc_xu_abist_g8t_dcomp_ofu , + pc_xu_abist_g8t_wenb_ofu => pc_xu_abist_g8t_wenb_ofu , + pc_xu_abist_grf_renb_0_ofu => pc_xu_abist_grf_renb_0_ofu , + pc_xu_abist_grf_renb_1_ofu => pc_xu_abist_grf_renb_1_ofu , + pc_xu_abist_grf_wenb_0_ofu => pc_xu_abist_grf_wenb_0_ofu , + pc_xu_abist_grf_wenb_1_ofu => pc_xu_abist_grf_wenb_1_ofu , + pc_xu_abist_raddr_0_ofu => pc_xu_abist_raddr_0_ofu , + pc_xu_abist_raddr_1_ofu => pc_xu_abist_raddr_1_ofu , + pc_xu_abist_raw_dc_b_ofu => pc_xu_abist_raw_dc_b_ofu , + pc_xu_abist_waddr_0_ofu => pc_xu_abist_waddr_0_ofu , + pc_xu_abist_waddr_1_ofu => pc_xu_abist_waddr_1_ofu , + pc_xu_abist_wl144_comp_ena_ofu => pc_xu_abist_wl144_comp_ena_ofu , + pc_xu_abist_wl32_comp_ena_ofu => pc_xu_abist_wl32_comp_ena_ofu , + pc_xu_abist_wl512_comp_ena_ofu => pc_xu_abist_wl512_comp_ena_ofu , + pc_xu_event_mux_ctrls_ofu => pc_xu_event_mux_ctrls_ofu , + pc_xu_lsu_event_mux_ctrls_ofu => pc_xu_lsu_event_mux_ctrls_ofu , + pc_xu_event_bus_enable_ofu => pc_xu_event_bus_enable_ofu , + pc_xu_abst_sl_thold_3_ofu => pc_xu_abst_sl_thold_3_ofu , + pc_xu_abst_slp_sl_thold_3_ofu => pc_xu_abst_slp_sl_thold_3_ofu , + pc_xu_regf_sl_thold_3_ofu => pc_xu_regf_sl_thold_3_ofu , + pc_xu_regf_slp_sl_thold_3_ofu => pc_xu_regf_slp_sl_thold_3_ofu , + pc_xu_ary_nsl_thold_3_ofu => pc_xu_ary_nsl_thold_3_ofu , + pc_xu_ary_slp_nsl_thold_3_ofu => pc_xu_ary_slp_nsl_thold_3_ofu , + pc_xu_cache_par_err_event_ofu => pc_xu_cache_par_err_event_ofu , + pc_xu_ccflush_dc_ofu => pc_xu_ccflush_dc_ofu , + pc_xu_cfg_sl_thold_3_ofu => pc_xu_cfg_sl_thold_3_ofu , + pc_xu_cfg_slp_sl_thold_3_ofu => pc_xu_cfg_slp_sl_thold_3_ofu , + pc_xu_dbg_action_ofu => pc_xu_dbg_action_ofu , + pc_xu_debug_mux1_ctrls_ofu => pc_xu_debug_mux1_ctrls_ofu , + pc_xu_debug_mux2_ctrls_ofu => pc_xu_debug_mux2_ctrls_ofu , + pc_xu_debug_mux3_ctrls_ofu => pc_xu_debug_mux3_ctrls_ofu , + pc_xu_debug_mux4_ctrls_ofu => pc_xu_debug_mux4_ctrls_ofu , + pc_xu_decrem_dis_on_stop_ofu => pc_xu_decrem_dis_on_stop_ofu , + pc_xu_event_count_mode_ofu => pc_xu_event_count_mode_ofu , + pc_xu_extirpts_dis_on_stop_ofu => pc_xu_extirpts_dis_on_stop_ofu , + pc_xu_fce_3_ofu => pc_xu_fce_3_ofu , + pc_xu_force_ude_ofu => pc_xu_force_ude_ofu , + pc_xu_func_nsl_thold_3_ofu => pc_xu_func_nsl_thold_3_ofu , + pc_xu_func_sl_thold_3_ofu => pc_xu_func_sl_thold_3_ofu , + pc_xu_func_slp_nsl_thold_3_ofu => pc_xu_func_slp_nsl_thold_3_ofu , + pc_xu_func_slp_sl_thold_3_ofu => pc_xu_func_slp_sl_thold_3_ofu , + pc_xu_gptr_sl_thold_3_ofu => pc_xu_gptr_sl_thold_3_ofu , + pc_xu_init_reset_ofu => pc_xu_init_reset_ofu , + pc_xu_inj_dcache_parity_ofu => pc_xu_inj_dcache_parity_ofu , + pc_xu_inj_dcachedir_parity_ofu => pc_xu_inj_dcachedir_parity_ofu , + pc_xu_inj_llbust_attempt_ofu => pc_xu_inj_llbust_attempt_ofu , + pc_xu_inj_llbust_failed_ofu => pc_xu_inj_llbust_failed_ofu , + pc_xu_inj_sprg_ecc_ofu => pc_xu_inj_sprg_ecc_ofu , + pc_xu_inj_regfile_parity_ofu => pc_xu_inj_regfile_parity_ofu , + pc_xu_inj_wdt_reset_ofu => pc_xu_inj_wdt_reset_ofu , + pc_xu_inj_dcachedir_multihit_ofu => pc_xu_inj_dcachedir_multihit_ofu, + pc_xu_instr_trace_mode_ofu => pc_xu_instr_trace_mode_ofu , + pc_xu_instr_trace_tid_ofu => pc_xu_instr_trace_tid_ofu , + pc_xu_msrovride_enab_ofu => pc_xu_msrovride_enab_ofu , + pc_xu_msrovride_gs_ofu => pc_xu_msrovride_gs_ofu , + pc_xu_msrovride_pr_ofu => pc_xu_msrovride_pr_ofu , + pc_xu_ram_execute_ofu => pc_xu_ram_execute_ofu , + pc_xu_ram_flush_thread_ofu => pc_xu_ram_flush_thread_ofu , + pc_xu_ram_mode_ofu => pc_xu_ram_mode_ofu , + pc_xu_ram_thread_ofu => pc_xu_ram_thread_ofu , + pc_xu_repr_sl_thold_3_ofu => pc_xu_repr_sl_thold_3_ofu , + pc_xu_reset_1_cmplt_ofu => pc_xu_reset_1_cmplt_ofu , + pc_xu_reset_2_cmplt_ofu => pc_xu_reset_2_cmplt_ofu , + pc_xu_reset_3_cmplt_ofu => pc_xu_reset_3_cmplt_ofu , + pc_xu_reset_wd_cmplt_ofu => pc_xu_reset_wd_cmplt_ofu , + pc_xu_sg_3_ofu => pc_xu_sg_3_ofu , + pc_xu_step_ofu => pc_xu_step_ofu , + pc_xu_stop_ofu => pc_xu_stop_ofu , + pc_xu_time_sl_thold_3_ofu => pc_xu_time_sl_thold_3_ofu , + pc_xu_timebase_dis_on_stop_ofu => pc_xu_timebase_dis_on_stop_ofu , + pc_xu_trace_bus_enable_ofu => pc_xu_trace_bus_enable_ofu , + an_ac_scan_dis_dc_b_ofu => an_ac_scan_dis_dc_b_ofu, + an_ac_scan_diag_dc_ofu => an_ac_scan_diag_dc_ofu, + + xu_ex2_flush_ofu => xu_ex2_flush_ofu, + xu_ex3_flush_ofu => xu_ex3_flush_ofu, + xu_ex4_flush_ofu => xu_ex4_flush_ofu, + xu_ex5_flush_ofu => xu_ex5_flush_ofu, + an_ac_lbist_ary_wrt_thru_dc_ofu => an_ac_lbist_ary_wrt_thru_dc_ofu, + + xu_pc_err_mchk_disabled_ifu => xu_pc_err_mchk_disabled, + xu_pc_lsu_event_data_ifu => xu_pc_lsu_event_data, + xu_pc_err_mchk_disabled_ofu => xu_pc_err_mchk_disabled_ofu, + xu_pc_lsu_event_data_ofu => xu_pc_lsu_event_data_ofu, + + gnd => gnd, + vdd => vdd + ); + +a_iuq: entity work.iuq + generic map(expand_type => expand_type, + bcfg_epn_0to15 => bcfg_epn_0to15, + bcfg_epn_16to31 => bcfg_epn_16to31, + bcfg_epn_32to47 => bcfg_epn_32to47, + bcfg_epn_48to51 => bcfg_epn_48to51, + bcfg_rpn_22to31 => bcfg_rpn_22to31, + bcfg_rpn_32to47 => bcfg_rpn_32to47, + bcfg_rpn_48to51 => bcfg_rpn_48to51, + fpr_addr_width => fpr_addr_width, + lmq_entries => lmq_entries, + regmode => regmode, + threads => threads, + ucode_mode => ucode_mode) + port map ( + abst_scan_in => an_ac_abst_scan_in_omm_iu(0 to 2), + bcfg_scan_in => an_ac_bcfg_scan_in_omm_bit3, + ccfg_scan_in => mm_iu_ccfg_scan_out, + dcfg_scan_in => an_ac_dcfg_scan_in_omm(1), + func_scan_in => an_ac_func_scan_in_omm_iua(6 to 19), + gptr_scan_in => an_ac_gptr_scan_in_omm, + repr_scan_in => an_ac_repr_scan_in_omm, + time_scan_in => an_ac_time_scan_in_omm, + regf_scan_in => an_ac_regf_scan_in_omm(0 to 4), + debug_data_in => pc_iu_debug_data, + trace_triggers_in => pc_iu_trigger_data, + an_ac_back_inv => an_ac_back_inv_omm, + an_ac_back_inv_addr => an_ac_back_inv_addr_omm(real_ifar'left to 63), + an_ac_back_inv_target_iiu_a => an_ac_back_inv_target_omm_iua, + an_ac_back_inv_target_iiu_b => an_ac_back_inv_target_omm_iub, + an_ac_grffence_en_dc => an_ac_camfence_en_dc_omm, + an_ac_icbi_ack => an_ac_icbi_ack_omm, + an_ac_icbi_ack_thread => an_ac_icbi_ack_thread_omm, + an_ac_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc_omm, + an_ac_reld_core_tag => xu_iu_reld_core_tag, + an_ac_reld_data => xu_iu_reld_data, + an_ac_reld_data_vld => xu_iu_reld_data_vld, + an_ac_reld_data_coming_clone => xu_iu_reld_data_coming_clone, + an_ac_reld_ditc_clone => xu_iu_reld_ditc_clone, + an_ac_reld_ecc_err => xu_iu_reld_ecc_err, + an_ac_reld_ecc_err_ue => xu_iu_reld_ecc_err_ue, + an_ac_reld_qw => xu_iu_reld_qw, + an_ac_reld_data_vld_clone => xu_iu_reld_data_vld_clone, + an_ac_reld_core_tag_clone => xu_iu_reld_core_tag_clone, + an_ac_scan_diag_dc => an_ac_scan_diag_dc_omm, + an_ac_stcx_complete => xu_iu_stcx_complete, + an_ac_sync_ack => an_ac_sync_ack_omm, + fu_iu_uc_special => fu_iu_uc_special, + mm_iu_ierat_mmucr0_0 => mm_iu_ierat_mmucr0_0, + mm_iu_ierat_mmucr0_1 => mm_iu_ierat_mmucr0_1, + mm_iu_ierat_mmucr0_2 => mm_iu_ierat_mmucr0_2, + mm_iu_ierat_mmucr0_3 => mm_iu_ierat_mmucr0_3, + mm_iu_ierat_mmucr1 => mm_iu_ierat_mmucr1, + mm_iu_ierat_pid0 => mm_iu_ierat_pid0, + mm_iu_ierat_pid1 => mm_iu_ierat_pid1, + mm_iu_ierat_pid2 => mm_iu_ierat_pid2, + mm_iu_ierat_pid3 => mm_iu_ierat_pid3, + mm_iu_ierat_rel_data => mm_iu_ierat_rel_data, + mm_iu_ierat_rel_val => mm_iu_ierat_rel_val, + mm_iu_ierat_snoop_attr => mm_iu_ierat_snoop_attr, + mm_iu_ierat_snoop_coming => mm_iu_ierat_snoop_coming, + mm_iu_ierat_snoop_val => mm_iu_ierat_snoop_val, + mm_iu_ierat_snoop_vpn => mm_iu_ierat_snoop_vpn, + slowspr_addr_in => mm_iu_slowspr_addr, + slowspr_data_in => mm_iu_slowspr_data, + slowspr_done_in => mm_iu_slowspr_done, + slowspr_etid_in => mm_iu_slowspr_etid, + slowspr_rw_in => mm_iu_slowspr_rw, + slowspr_val_in => mm_iu_slowspr_val, + nclk => a2_nclk, + pc_iu_abist_dcomp_g6t_2r => pc_iu_abist_dcomp_g6t_2r(0 to 3), + pc_iu_abist_di_0 => pc_iu_abist_di_0(0 to 3), + pc_iu_abist_di_g6t_2r => pc_iu_abist_di_g6t_2r(0 to 3), + pc_iu_abist_ena_dc => pc_iu_abist_ena_dc, + pc_iu_abist_g6t_bw => pc_iu_abist_g6t_bw(0 to 1), + pc_iu_abist_g6t_r_wb => pc_iu_abist_g6t_r_wb, + pc_iu_abist_g8t1p_renb_0 => pc_iu_abist_g8t1p_renb_0, + pc_iu_abist_g8t_bw_0 => pc_iu_abist_g8t_bw_0, + pc_iu_abist_g8t_bw_1 => pc_iu_abist_g8t_bw_1, + pc_iu_abist_g8t_dcomp => pc_iu_abist_g8t_dcomp(0 to 3), + pc_iu_abist_g8t_wenb => pc_iu_abist_g8t_wenb, + pc_iu_abist_raddr_0 => pc_iu_abist_raddr_0(0 to 9), + pc_iu_abist_raw_dc_b => pc_iu_abist_raw_dc_b, + pc_iu_abist_waddr_0 => pc_iu_abist_waddr_0(0 to 9), + pc_iu_abist_wl128_comp_ena => pc_iu_abist_wl128_comp_ena, + pc_iu_abist_wl256_comp_ena => pc_iu_abist_wl256_comp_ena, + pc_iu_abist_wl64_comp_ena => pc_iu_abist_wl64_comp_ena, + pc_iu_bo_enable_4 => pc_iu_bo_enable_4, + pc_iu_bo_reset => pc_iu_bo_reset, + pc_iu_bo_unload => pc_iu_bo_unload, + pc_iu_bo_repair => pc_iu_bo_repair, + pc_iu_bo_shdata => pc_iu_bo_shdata, + pc_iu_bo_select => pc_iu_bo_select, + pc_iu_debug_mux1_ctrls => pc_iu_debug_mux1_ctrls, + pc_iu_debug_mux2_ctrls => pc_iu_debug_mux2_ctrls, + pc_iu_event_bus_enable => pc_iu_event_bus_enable, + pc_iu_event_count_mode => pc_iu_event_count_mode, + pc_iu_event_mux_ctrls => pc_iu_event_mux_ctrls, + pc_iu_gptr_sl_thold_4 => pc_iu_gptr_sl_thold_4, + pc_iu_time_sl_thold_4 => pc_iu_time_sl_thold_4, + pc_iu_repr_sl_thold_4 => pc_iu_repr_sl_thold_4, + pc_iu_abst_sl_thold_4 => pc_iu_abst_sl_thold_4, + pc_iu_abst_slp_sl_thold_4 => pc_iu_abst_slp_sl_thold_4, + pc_iu_bolt_sl_thold_4 => pc_iu_bolt_sl_thold_4, + pc_iu_regf_slp_sl_thold_4 => pc_iu_regf_slp_sl_thold_4, + pc_iu_func_sl_thold_4 => pc_iu_func_sl_thold_4, + pc_iu_func_slp_sl_thold_4 => pc_iu_func_slp_sl_thold_4, + pc_iu_cfg_sl_thold_4 => pc_iu_cfg_sl_thold_4, + pc_iu_cfg_slp_sl_thold_4 => pc_iu_cfg_slp_sl_thold_4, + pc_iu_func_nsl_thold_4 => pc_iu_func_nsl_thold_4, + pc_iu_func_slp_nsl_thold_4 => pc_iu_func_slp_nsl_thold_4, + pc_iu_ary_nsl_thold_4 => pc_iu_ary_nsl_thold_4, + pc_iu_ary_slp_nsl_thold_4 => pc_iu_ary_slp_nsl_thold_4, + pc_iu_sg_4 => pc_iu_sg_4, + pc_iu_fce_4 => pc_iu_fce_4, + pc_iu_init_reset => pc_iu_init_reset, + pc_iu_inj_icache_parity => pc_iu_inj_icache_parity, + pc_iu_inj_icachedir_multihit => pc_iu_inj_icachedir_multihit, + pc_iu_inj_icachedir_parity => pc_iu_inj_icachedir_parity, + pc_iu_ram_force_cmplt => pc_iu_ram_force_cmplt, + pc_iu_ram_instr => pc_iu_ram_instr, + pc_iu_ram_instr_ext => pc_iu_ram_instr_ext, + pc_iu_ram_mode => pc_iu_ram_mode, + pc_iu_ram_thread => pc_iu_ram_thread, + pc_iu_trace_bus_enable => pc_iu_trace_bus_enable, + tc_ac_ccflush_dc => pc_iu_ccflush_dc, + an_ac_lbist_en_dc => an_ac_lbist_en_dc_omm, + an_ac_atpg_en_dc => an_ac_atpg_en_dc_omm, + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b_omm, + xu_iu_complete_qentry => xu_iu_complete_qentry, + xu_iu_complete_target_type => xu_iu_complete_target_type, + xu_iu_complete_tid => xu_iu_complete_tid, + xu_iu_ex1_ra_entry => xu_iu_ex1_ra_entry, + xu_iu_ex1_rb => xu_iu_ex1_rb, + xu_iu_ex1_rs_is => xu_iu_ex1_rs_is, + xu_iu_ex5_bclr => xu_iu_ex5_bclr, + xu_iu_ex5_bh => xu_iu_ex5_bh, + xu_iu_ex5_br_hist => xu_iu_ex5_br_hist, + xu_iu_ex5_br_taken => xu_iu_ex5_br_taken, + xu_iu_ex5_br_update => xu_iu_ex5_br_update, + xu_iu_ex5_getNIA => xu_iu_ex5_getNIA, + xu_iu_ex5_gshare => xu_iu_ex5_gshare, + xu_iu_ex5_ifar => xu_iu_ex5_ifar, + xu_iu_ex5_lk => xu_iu_ex5_lk, + xu_iu_ex5_ppc_cpl => xu_iu_ex5_ppc_cpl, + xu_iu_ex4_loadmiss_qentry => xu_iu_ex4_loadmiss_qentry, + xu_iu_ex4_loadmiss_target => xu_iu_ex4_loadmiss_target, + xu_iu_ex4_loadmiss_target_type=> xu_iu_ex4_loadmiss_target_type, + xu_iu_ex4_loadmiss_tid => xu_iu_ex4_loadmiss_tid, + xu_iu_ex4_rs_data => xu_iu_ex4_rs_data, + xu_iu_ex5_tid => xu_iu_ex5_tid, + xu_iu_ex5_val => xu_iu_ex5_val, + xu_iu_ex5_loadmiss_qentry => xu_iu_ex5_loadmiss_qentry, + xu_iu_ex5_loadmiss_target => xu_iu_ex5_loadmiss_target, + xu_iu_ex5_loadmiss_target_type=> xu_iu_ex5_loadmiss_target_type, + xu_iu_ex5_loadmiss_tid => xu_iu_ex5_loadmiss_tid, + xu_iu_ex6_icbi_val => xu_iu_ex6_icbi_val, + xu_iu_ex6_icbi_addr => xu_iu_ex6_icbi_addr, + xu_iu_ex6_pri => xu_iu_ex6_pri, + xu_iu_ex6_pri_val => xu_iu_ex6_pri_val, + xu_iu_flush_2ucode => xu_iu_flush_2ucode, + xu_iu_flush_2ucode_type => xu_iu_flush_2ucode_type, + xu_iu_hid_mmu_mode => xu_iu_hid_mmu_mode, + xu_iu_xucr0_rel => xu_iu_xucr0_rel, + xu_iu_ici => xu_iu_ici, + xu_iu_iu0_flush_ifar0 => xu_iu_iu0_flush_ifar0, + xu_iu_iu0_flush_ifar1 => xu_iu_iu0_flush_ifar1, + xu_iu_iu0_flush_ifar2 => xu_iu_iu0_flush_ifar2, + xu_iu_iu0_flush_ifar3 => xu_iu_iu0_flush_ifar3, + xu_iu_larx_done_tid => xu_iu_larx_done_tid, + xu_iu_membar_tid => xu_iu_membar_tid, + xu_iu_msr_cm => xu_iu_msr_cm, + xu_iu_msr_gs => xu_iu_msr_gs, + xu_iu_msr_hv => xu_iu_msr_hv, + xu_iu_msr_is => xu_iu_msr_is, + xu_iu_msr_pr => xu_iu_msr_pr, + xu_iu_multdiv_done => xu_iu_multdiv_done, + xu_iu_need_hole => xu_iu_need_hole, + xu_iu_raise_iss_pri => xu_iu_raise_iss_pri, + xu_iu_ram_issue => xu_iu_ram_issue, + xu_iu_ex1_is_csync => xu_iu_ex1_is_csync, + xu_iu_ex1_is_isync => xu_iu_ex1_is_isync, + xu_iu_rf1_is_eratilx => xu_iu_rf1_is_eratilx, + xu_iu_rf1_is_eratre => xu_iu_rf1_is_eratre, + xu_iu_rf1_is_eratsx => xu_iu_rf1_is_eratsx, + xu_iu_rf1_is_eratwe => xu_iu_rf1_is_eratwe, + xu_iu_rf1_val => xu_iu_rf1_val, + xu_iu_rf1_ws => xu_iu_rf1_ws, + xu_iu_rf1_t => xu_iu_rf1_t, + xu_iu_run_thread => xu_iu_run_thread, + xu_iu_set_barr_tid => xu_iu_set_barr_tid, + xu_iu_single_instr_mode => xu_iu_single_instr_mode, + xu_iu_slowspr_done => xu_iu_slowspr_done, + xu_iu_spr_ccr2_en_dcr => xu_iu_spr_ccr2_en_dcr, + xu_iu_spr_ccr2_ifratsc => xu_iu_spr_ccr2_ifratsc, + xu_iu_spr_ccr2_ifrat => xu_iu_spr_ccr2_ifrat, + xu_iu_spr_xer0 => xu_iu_spr_xer0, + xu_iu_spr_xer1 => xu_iu_spr_xer1, + xu_iu_spr_xer2 => xu_iu_spr_xer2, + xu_iu_spr_xer3 => xu_iu_spr_xer3, + xu_iu_uc_flush_ifar0 => xu_iu_uc_flush_ifar0, + xu_iu_uc_flush_ifar1 => xu_iu_uc_flush_ifar1, + xu_iu_uc_flush_ifar2 => xu_iu_uc_flush_ifar2, + xu_iu_uc_flush_ifar3 => xu_iu_uc_flush_ifar3, + xu_iu_ucode_restart => xu_iu_ucode_restart, + abst_scan_out(0 to 1) => ac_an_abst_scan_out_imm_iu(0 to 1), + abst_scan_out(2) => iu_pc_abst_scan_out, + bcfg_scan_out => iu_fu_bcfg_scan_out, + ccfg_scan_out => iu_pc_ccfg_scan_out, + dcfg_scan_out => iu_fu_dcfg_scan_out, + func_scan_out => ac_an_func_scan_out_imm_iua(6 to 19), + gptr_scan_out => iu_pc_gptr_scan_out, + repr_scan_out => iu_fu_repr_scan_out, + time_scan_out => iu_fu_time_scan_out, + regf_scan_out => ac_an_regf_scan_out_imm(0 to 4), + debug_data_out => iu_xu_debug_data, + trace_triggers_out => iu_xu_trigger_data, + iu_fu_ex2_n_flush => iu_fu_ex2_n_flush, + iu_fu_is2_tid_decode => iu_fu_is2_tid_decode, + iu_fu_rf0_bypsel => iu_fu_rf0_bypsel, + iu_fu_rf0_fra => iu_fu_rf0_fra, + iu_fu_rf0_fra_v => iu_fu_rf0_fra_v, + iu_fu_rf0_frb => iu_fu_rf0_frb, + iu_fu_rf0_frb_v => iu_fu_rf0_frb_v, + iu_fu_rf0_frc => iu_fu_rf0_frc, + iu_fu_rf0_frc_v => iu_fu_rf0_frc_v, + iu_fu_rf0_frt => iu_fu_rf0_frt, + iu_fu_rf0_ifar => iu_fu_rf0_ifar, + iu_fu_rf0_instr => iu_fu_rf0_instr, + iu_fu_rf0_instr_match => iu_fu_rf0_instr_match, + iu_fu_rf0_instr_v => iu_fu_rf0_instr_v, + iu_fu_rf0_is_ucode => iu_fu_rf0_is_ucode, + iu_fu_rf0_ucfmul => iu_fu_rf0_ucfmul, + iu_fu_rf0_ldst_val => iu_fu_rf0_ldst_val, + iu_fu_rf0_ldst_tid => iu_fu_rf0_ldst_tid, + iu_fu_rf0_ldst_tag => iu_fu_rf0_ldst_tag, + iu_fu_rf0_str_val => iu_fu_rf0_str_val, + iu_fu_rf0_tid => iu_fu_rf0_tid, + iu_mm_ierat_epn => iu_mm_ierat_epn, + iu_mm_ierat_flush => iu_mm_ierat_flush, + iu_mm_ierat_mmucr0 => iu_mm_ierat_mmucr0, + iu_mm_ierat_mmucr0_we => iu_mm_ierat_mmucr0_we, + iu_mm_ierat_mmucr1 => iu_mm_ierat_mmucr1, + iu_mm_ierat_mmucr1_we => iu_mm_ierat_mmucr1_we, + iu_mm_ierat_req => iu_mm_ierat_req, + iu_mm_ierat_snoop_ack => iu_mm_ierat_snoop_ack, + iu_mm_ierat_thdid => iu_mm_ierat_thdid, + iu_mm_ierat_tid => iu_mm_ierat_tid, + iu_mm_ierat_state => iu_mm_ierat_state, + iu_mm_lmq_empty => iu_mm_lmq_empty, + mm_iu_barrier_done => mm_iu_barrier_done, + iu_pc_bo_fail => iu_pc_bo_fail, + iu_pc_bo_diagout => iu_pc_bo_diagout, + iu_pc_err_icache_parity => iu_pc_err_icache_parity, + iu_pc_err_icachedir_multihit => iu_pc_err_icachedir_multihit, + iu_pc_err_icachedir_parity => iu_pc_err_icachedir_parity, + iu_pc_err_ucode_illegal => iu_pc_err_ucode_illegal, + iu_pc_event_data => iu_pc_event_data, + slowspr_addr_out => iu_pc_slowspr_addr, + slowspr_data_out => iu_pc_slowspr_data, + slowspr_done_out => iu_pc_slowspr_done, + slowspr_etid_out => iu_pc_slowspr_etid, + slowspr_rw_out => iu_pc_slowspr_rw, + slowspr_val_out => iu_pc_slowspr_val, + iu_xu_ex4_tlb_data => iu_xu_ex4_tlb_data, + iu_xu_ierat_ex2_flush_req => iu_xu_ierat_ex2_flush_req, + iu_xu_ierat_ex3_par_err => iu_xu_ierat_ex3_par_err, + iu_xu_ierat_ex4_par_err => iu_xu_ierat_ex4_par_err, + iu_xu_is2_axu_instr_type => iu_xu_is2_axu_instr_type, + iu_xu_is2_axu_ld_or_st => iu_xu_is2_axu_ld_or_st, + iu_xu_is2_axu_ldst_extpid => iu_xu_is2_axu_ldst_extpid, + iu_xu_is2_axu_ldst_forcealign => iu_xu_is2_axu_ldst_forcealign, + iu_xu_is2_axu_ldst_forceexcept => iu_xu_is2_axu_ldst_forceexcept, + iu_xu_is2_axu_ldst_indexed => iu_xu_is2_axu_ldst_indexed, + iu_xu_is2_axu_ldst_size => iu_xu_is2_axu_ldst_size, + iu_xu_is2_axu_ldst_tag => iu_xu_is2_axu_ldst_tag, + iu_xu_is2_axu_ldst_update => iu_xu_is2_axu_ldst_update, + iu_xu_is2_axu_mffgpr => iu_xu_is2_axu_mffgpr, + iu_xu_is2_axu_mftgpr => iu_xu_is2_axu_mftgpr, + iu_xu_is2_axu_movedp => iu_xu_is2_axu_movedp, + iu_xu_is2_axu_store => iu_xu_is2_axu_store, + iu_xu_is2_error => iu_xu_is2_error, + iu_xu_is2_gshare => iu_xu_is2_gshare, + iu_xu_is2_ifar => iu_xu_is2_ifar, + iu_xu_is2_instr => iu_xu_is2_instr, + iu_xu_is2_is_ucode => iu_xu_is2_is_ucode, + iu_xu_is2_match => iu_xu_is2_match, + iu_xu_is2_pred_taken_cnt => iu_xu_is2_pred_taken_cnt, + iu_xu_is2_pred_update => iu_xu_is2_pred_update, + iu_xu_is2_s1 => iu_xu_is2_s1, + iu_xu_is2_s1_vld => iu_xu_is2_s1_vld, + iu_xu_is2_s2 => iu_xu_is2_s2, + iu_xu_is2_s2_vld => iu_xu_is2_s2_vld, + iu_xu_is2_s3 => iu_xu_is2_s3, + iu_xu_is2_s3_vld => iu_xu_is2_s3_vld, + iu_xu_is2_ta => iu_xu_is2_ta, + iu_xu_is2_ta_vld => iu_xu_is2_ta_vld, + iu_xu_is2_tid => iu_xu_is2_tid, + iu_xu_is2_ucode_vld => iu_xu_is2_ucode_vld, + iu_xu_is2_vld => iu_xu_is2_vld, + iu_xu_quiesce => iu_xu_quiesce, + iu_xu_ra => iu_xu_ra, + iu_xu_request => iu_xu_request, + iu_xu_thread => iu_xu_thread, + iu_xu_userdef => iu_xu_userdef, + iu_xu_wimge => iu_xu_wimge, + + rtim_sl_thold_7 => an_ac_rtim_sl_thold_7_omm, + func_sl_thold_7 => an_ac_func_sl_thold_7_omm, + func_nsl_thold_7 => an_ac_func_nsl_thold_7_omm, + ary_nsl_thold_7 => an_ac_ary_nsl_thold_7_omm, + sg_7 => an_ac_sg_7_omm, + fce_7 => an_ac_fce_7_omm, + rtim_sl_thold_6 => rp_pc_rtim_sl_thold_6, + func_sl_thold_6 => rp_pc_func_sl_thold_6, + func_nsl_thold_6 => rp_pc_func_nsl_thold_6, + ary_nsl_thold_6 => rp_pc_ary_nsl_thold_6, + sg_6 => rp_pc_sg_6, + fce_6 => rp_pc_fce_6, + an_ac_scom_dch => an_ac_scom_dch_omm, + an_ac_scom_cch => an_ac_scom_cch_omm, + an_ac_checkstop => an_ac_checkstop_omm, + an_ac_debug_stop => an_ac_debug_stop_omm, + an_ac_pm_thread_stop => an_ac_pm_thread_stop_omm, + an_ac_reset_1_complete => an_ac_reset_1_complete_omm, + an_ac_reset_2_complete => an_ac_reset_2_complete_omm, + an_ac_reset_3_complete => an_ac_reset_3_complete_omm, + an_ac_reset_wd_complete => an_ac_reset_wd_complete_omm, + an_ac_abist_start_test => an_ac_abist_start_test_omm, + ac_rp_trace_to_perfcntr => ac_rp_trace_to_perfcntr, + rp_pc_scom_dch_q => rp_pc_scom_dch_q, + rp_pc_scom_cch_q => rp_pc_scom_cch_q, + rp_pc_checkstop_q => rp_pc_checkstop_q, + rp_pc_debug_stop_q => rp_pc_debug_stop_q, + rp_pc_pm_thread_stop_q => rp_pc_pm_thread_stop_q, + rp_pc_reset_1_complete_q => rp_pc_reset_1_complete_q, + rp_pc_reset_2_complete_q => rp_pc_reset_2_complete_q, + rp_pc_reset_3_complete_q => rp_pc_reset_3_complete_q, + rp_pc_reset_wd_complete_q => rp_pc_reset_wd_complete_q, + rp_pc_abist_start_test_q => rp_pc_abist_start_test_q, + rp_pc_trace_to_perfcntr_q => rp_pc_trace_to_perfcntr_q, + pc_rp_scom_dch => pc_rp_scom_dch, + pc_rp_scom_cch => pc_rp_scom_cch, + pc_rp_special_attn => pc_rp_special_attn, + pc_rp_checkstop => pc_rp_checkstop, + pc_rp_local_checkstop => pc_rp_local_checkstop, + pc_rp_recov_err => pc_rp_recov_err, + pc_rp_trace_error => pc_rp_trace_error, + pc_rp_event_bus_enable => pc_rp_event_bus_enable, + pc_rp_event_bus => pc_rp_event_bus, + pc_rp_fu_bypass_events => pc_rp_fu_bypass_events, + pc_rp_iu_bypass_events => pc_rp_iu_bypass_events, + pc_rp_mm_bypass_events => pc_rp_mm_bypass_events, + pc_rp_lsu_bypass_events => pc_rp_lsu_bypass_events, + pc_rp_pm_thread_running => pc_rp_pm_thread_running, + pc_rp_power_managed => pc_rp_power_managed, + pc_rp_rvwinkle_mode => pc_rp_rvwinkle_mode, + ac_an_scom_dch_q => ac_an_scom_dch_imm, + ac_an_scom_cch_q => ac_an_scom_cch_imm, + ac_an_special_attn_q => ac_an_special_attn_imm, + ac_an_checkstop_q => ac_an_checkstop_imm, + ac_an_local_checkstop_q => ac_an_local_checkstop_imm, + ac_an_recov_err_q => ac_an_recov_err_imm, + ac_an_trace_error_q => ac_an_trace_error_imm, + rp_mm_event_bus_enable_q => rp_mm_event_bus_enable_q, + ac_an_event_bus_q => ac_an_event_bus_imm, + ac_an_fu_bypass_events_q => ac_an_fu_bypass_events_imm, + ac_an_iu_bypass_events_q => ac_an_iu_bypass_events_imm, + ac_an_mm_bypass_events_q => ac_an_mm_bypass_events_imm, + ac_an_lsu_bypass_events_q => ac_an_lsu_bypass_events_imm, + ac_an_pm_thread_running_q => ac_an_pm_thread_running_imm, + ac_an_power_managed_q => ac_an_power_managed_int, + ac_an_rvwinkle_mode_q => ac_an_rvwinkle_mode_imm, + + pc_func_scan_in => an_ac_func_scan_in_omm_iua(0 to 1), + pc_func_scan_in_q => rp_pc_func_scan_in_q(0 to 1), + pc_func_scan_out => pc_rp_func_scan_out(1), + pc_func_scan_out_q => ac_an_func_scan_out_imm_iua(1), + pc_bcfg_scan_in => mm_rp_bcfg_scan_out, + pc_bcfg_scan_in_q => rp_pc_bcfg_scan_out_q, + pc_dcfg_scan_in => mm_rp_dcfg_scan_out, + pc_dcfg_scan_in_q => rp_pc_dcfg_scan_out_q, + pc_bcfg_scan_out => pc_rp_bcfg_scan_out, + pc_bcfg_scan_out_q => ac_an_bcfg_scan_out_imm(2), + pc_ccfg_scan_out => pc_rp_ccfg_scan_out, + pc_ccfg_scan_out_q => ac_an_bcfg_scan_out_imm(0), + pc_dcfg_scan_out => pc_rp_dcfg_scan_out, + pc_dcfg_scan_out_q => ac_an_dcfg_scan_out_imm(0), + fu_abst_scan_in => an_ac_abst_scan_in_omm_iu(3), + fu_abst_scan_in_q => rp_fu_abst_scan_in_q, + fu_abst_scan_out => fu_rp_abst_scan_out, + fu_abst_scan_out_q => ac_an_abst_scan_out_imm_iu(3), + fu_bcfg_scan_out => fu_rp_bcfg_scan_out, + fu_bcfg_scan_out_q => ac_an_bcfg_scan_out_imm(3), + fu_ccfg_scan_out => fu_rp_ccfg_scan_out, + fu_ccfg_scan_out_q => ac_an_bcfg_scan_out_imm(1), + fu_dcfg_scan_out => fu_rp_dcfg_scan_out, + fu_dcfg_scan_out_q => ac_an_dcfg_scan_out_imm(1), + fu_func_scan_in => an_ac_func_scan_in_omm_iua(2 to 5), + fu_func_scan_in_q => rp_fu_func_scan_in_q(0 to 3), + fu_func_scan_out => fu_rp_func_scan_out(0 to 3), + fu_func_scan_out_q => ac_an_func_scan_out_imm_iua(2 to 5), + bx_abst_scan_in => an_ac_abst_scan_in_omm_iu(4), + bx_abst_scan_in_q => rp_bx_abst_scan_in_q, + bx_abst_scan_out => bx_rp_abst_scan_out, + bx_abst_scan_out_q => ac_an_abst_scan_out_imm_iu(4), + bx_func_scan_in => an_ac_func_scan_in_omm_iua(20 to 21), + bx_func_scan_in_q => rp_bx_func_scan_in_q(0 to 1), + bx_func_scan_out => bx_rp_func_scan_out(0 to 1), + bx_func_scan_out_q => ac_an_func_scan_out_imm_iua(20 to 21), + spare_func_scan_in => an_ac_func_scan_in_omm_iub(60 to 63), + spare_func_scan_out_q => ac_an_func_scan_out_imm_iub(60 to 63), + rp_abst_scan_in => pc_rp_abst_scan_out, + rp_func_scan_in => pc_rp_func_scan_out(0), + rp_abst_scan_out => ac_an_abst_scan_out_imm_iu(2), + rp_func_scan_out => ac_an_func_scan_out_imm_iua(0), + + an_ac_abist_mode_dc_iiu => an_ac_abist_mode_dc_omm, + an_ac_ccflush_dc_iiu => an_ac_ccflush_dc_omm, + an_ac_gsd_test_enable_dc_iiu => an_ac_gsd_test_enable_dc_omm, + an_ac_gsd_test_acmode_dc_iiu => an_ac_gsd_test_acmode_dc_omm, + an_ac_lbist_ip_dc_iiu => an_ac_lbist_ip_dc_omm, + an_ac_lbist_ac_mode_dc_iiu => an_ac_lbist_ac_mode_dc_omm, + an_ac_malf_alert_iiu => an_ac_malf_alert_omm, + an_ac_psro_enable_dc_iiu => an_ac_psro_enable_dc_omm, + an_ac_scan_type_dc_iiu => an_ac_scan_type_dc_omm, + an_ac_scom_sat_id_iiu => an_ac_scom_sat_id_omm, + + an_ac_abist_mode_dc_oiu => an_ac_abist_mode_dc_oiu, + an_ac_ccflush_dc_oiu => an_ac_ccflush_dc_oiu, + an_ac_gsd_test_enable_dc_oiu => an_ac_gsd_test_enable_dc_oiu, + an_ac_gsd_test_acmode_dc_oiu => an_ac_gsd_test_acmode_dc_oiu, + an_ac_lbist_ip_dc_oiu => an_ac_lbist_ip_dc_oiu, + an_ac_lbist_ac_mode_dc_oiu => an_ac_lbist_ac_mode_dc_oiu, + an_ac_malf_alert_oiu => an_ac_malf_alert_oiu, + an_ac_psro_enable_dc_oiu => an_ac_psro_enable_dc_oiu, + an_ac_scan_type_dc_oiu => an_ac_scan_type_dc_oiu, + an_ac_scom_sat_id_oiu => an_ac_scom_sat_id_oiu, + + an_ac_back_inv_oiu => an_ac_back_inv_oiu, + an_ac_back_inv_addr_oiu => an_ac_back_inv_addr_oiu, + an_ac_back_inv_target_bit1_oiu => an_ac_back_inv_target_bit1_oiu, + an_ac_back_inv_target_bit3_oiu => an_ac_back_inv_target_bit3_oiu, + an_ac_back_inv_target_bit4_oiu => an_ac_back_inv_target_bit4_oiu, + an_ac_atpg_en_dc_oiu => an_ac_atpg_en_dc_oiu, + an_ac_lbist_ary_wrt_thru_dc_oiu => an_ac_lbist_ary_wrt_thru_dc_oiu, + an_ac_lbist_en_dc_oiu => an_ac_lbist_en_dc_oiu, + an_ac_scan_diag_dc_oiu => an_ac_scan_diag_dc_oiu, + an_ac_scan_dis_dc_b_oiu => an_ac_scan_dis_dc_b_oiu, + + + + ac_an_abist_done_dc_iiu => ac_an_abist_done_dc_iiu, + ac_an_psro_ringsig_iiu => ac_an_psro_ringsig_iiu, + an_ac_ccenable_dc_iiu => an_ac_ccenable_dc_iiu, + mm_pc_bo_fail_iiu => mm_pc_bo_fail_iiu, + mm_pc_bo_diagout_iiu => mm_pc_bo_diagout_iiu, + mm_pc_event_data_iiu => mm_pc_event_data_iiu, + + ac_an_abist_done_dc_oiu => ac_an_abist_done_dc_oiu, + ac_an_psro_ringsig_oiu => ac_an_psro_ringsig_oiu, + an_ac_ccenable_dc_oiu => an_ac_ccenable_dc_oiu, + mm_pc_bo_fail_oiu => mm_pc_bo_fail_oiu, + mm_pc_bo_diagout_oiu => mm_pc_bo_diagout_oiu, + mm_pc_event_data_oiu => mm_pc_event_data_oiu, + + pc_mm_abist_dcomp_g6t_2r_iiu => pc_mm_abist_dcomp_g6t_2r_iiu, + pc_mm_abist_di_g6t_2r_iiu => pc_mm_abist_di_g6t_2r_iiu, + pc_mm_abist_di_0_iiu => pc_mm_abist_di_0_iiu, + pc_mm_abist_ena_dc_iiu => pc_mm_abist_ena_dc_iiu, + pc_mm_abist_g6t_r_wb_iiu => pc_mm_abist_g6t_r_wb_iiu, + pc_mm_abist_g8t_bw_0_iiu => pc_mm_abist_g8t_bw_0_iiu, + pc_mm_abist_g8t_bw_1_iiu => pc_mm_abist_g8t_bw_1_iiu, + pc_mm_abist_g8t_dcomp_iiu => pc_mm_abist_g8t_dcomp_iiu, + pc_mm_abist_g8t_wenb_iiu => pc_mm_abist_g8t_wenb_iiu, + pc_mm_abist_g8t1p_renb_0_iiu => pc_mm_abist_g8t1p_renb_0_iiu, + pc_mm_abist_raddr_0_iiu => pc_mm_abist_raddr_0_iiu, + pc_mm_abist_raw_dc_b_iiu => pc_mm_abist_raw_dc_b_iiu, + pc_mm_abist_waddr_0_iiu => pc_mm_abist_waddr_0_iiu, + pc_mm_abist_wl128_comp_ena_iiu => pc_mm_abist_wl128_comp_ena_iiu, + pc_mm_bo_enable_4_iiu => pc_mm_bo_enable_4_iiu, + pc_mm_bo_repair_iiu => pc_mm_bo_repair_iiu, + pc_mm_bo_reset_iiu => pc_mm_bo_reset_iiu, + pc_mm_bo_select_iiu => pc_mm_bo_select_iiu, + pc_mm_bo_shdata_iiu => pc_mm_bo_shdata_iiu, + pc_mm_bo_unload_iiu => pc_mm_bo_unload_iiu, + pc_mm_ccflush_dc_iiu => pc_mm_ccflush_dc_iiu, + pc_mm_debug_mux1_ctrls_iiu => pc_mm_debug_mux1_ctrls_iiu, + pc_mm_event_count_mode_iiu => pc_mm_event_count_mode_iiu, + pc_mm_event_mux_ctrls_iiu => pc_mm_event_mux_ctrls_iiu, + pc_mm_trace_bus_enable_iiu => pc_mm_trace_bus_enable_iiu, + pc_mm_abist_dcomp_g6t_2r_oiu => pc_mm_abist_dcomp_g6t_2r_oiu, + pc_mm_abist_di_g6t_2r_oiu => pc_mm_abist_di_g6t_2r_oiu, + pc_mm_abist_di_0_oiu => pc_mm_abist_di_0_oiu, + pc_mm_abist_ena_dc_oiu => pc_mm_abist_ena_dc_oiu, + pc_mm_abist_g6t_r_wb_oiu => pc_mm_abist_g6t_r_wb_oiu, + pc_mm_abist_g8t_bw_0_oiu => pc_mm_abist_g8t_bw_0_oiu, + pc_mm_abist_g8t_bw_1_oiu => pc_mm_abist_g8t_bw_1_oiu, + pc_mm_abist_g8t_dcomp_oiu => pc_mm_abist_g8t_dcomp_oiu, + pc_mm_abist_g8t_wenb_oiu => pc_mm_abist_g8t_wenb_oiu, + pc_mm_abist_g8t1p_renb_0_oiu => pc_mm_abist_g8t1p_renb_0_oiu, + pc_mm_abist_raddr_0_oiu => pc_mm_abist_raddr_0_oiu, + pc_mm_abist_raw_dc_b_oiu => pc_mm_abist_raw_dc_b_oiu, + pc_mm_abist_waddr_0_oiu => pc_mm_abist_waddr_0_oiu, + pc_mm_abist_wl128_comp_ena_oiu => pc_mm_abist_wl128_comp_ena_oiu, + pc_mm_abst_sl_thold_3_oiu => pc_mm_abst_sl_thold_3_oiu, + pc_mm_abst_slp_sl_thold_3_oiu => pc_mm_abst_slp_sl_thold_3_oiu, + pc_mm_ary_nsl_thold_3_oiu => pc_mm_ary_nsl_thold_3_oiu, + pc_mm_ary_slp_nsl_thold_3_oiu => pc_mm_ary_slp_nsl_thold_3_oiu, + pc_mm_bo_enable_3_oiu => pc_mm_bo_enable_3_oiu, + pc_mm_bo_repair_oiu => pc_mm_bo_repair_oiu, + pc_mm_bo_reset_oiu => pc_mm_bo_reset_oiu, + pc_mm_bo_select_oiu => pc_mm_bo_select_oiu, + pc_mm_bo_shdata_oiu => pc_mm_bo_shdata_oiu, + pc_mm_bo_unload_oiu => pc_mm_bo_unload_oiu, + pc_mm_bolt_sl_thold_3_oiu => pc_mm_bolt_sl_thold_3_oiu, + pc_mm_ccflush_dc_oiu => pc_mm_ccflush_dc_oiu, + pc_mm_cfg_sl_thold_3_oiu => pc_mm_cfg_sl_thold_3_oiu, + pc_mm_cfg_slp_sl_thold_3_oiu => pc_mm_cfg_slp_sl_thold_3_oiu, + pc_mm_debug_mux1_ctrls_oiu => pc_mm_debug_mux1_ctrls_oiu, + pc_mm_event_count_mode_oiu => pc_mm_event_count_mode_oiu, + pc_mm_event_mux_ctrls_oiu => pc_mm_event_mux_ctrls_oiu, + pc_mm_fce_3_oiu => pc_mm_fce_3_oiu, + pc_mm_func_nsl_thold_3_oiu => pc_mm_func_nsl_thold_3_oiu, + pc_mm_func_sl_thold_3_oiu => pc_mm_func_sl_thold_3_oiu, + pc_mm_func_slp_nsl_thold_3_oiu => pc_mm_func_slp_nsl_thold_3_oiu, + pc_mm_func_slp_sl_thold_3_oiu => pc_mm_func_slp_sl_thold_3_oiu, + pc_mm_gptr_sl_thold_3_oiu => pc_mm_gptr_sl_thold_3_oiu, + pc_mm_repr_sl_thold_3_oiu => pc_mm_repr_sl_thold_3_oiu, + pc_mm_sg_3_oiu => pc_mm_sg_3_oiu, + pc_mm_time_sl_thold_3_oiu => pc_mm_time_sl_thold_3_oiu, + pc_mm_trace_bus_enable_oiu => pc_mm_trace_bus_enable_oiu, + + xu_wu_rf1_flush => xu_wu_rf1_flush, + xu_wu_ex1_flush => xu_wu_ex1_flush, + xu_wu_ex2_flush => xu_wu_ex2_flush, + xu_wu_ex3_flush => xu_wu_ex3_flush, + xu_wu_ex4_flush => xu_wu_ex4_flush, + xu_wu_ex5_flush => xu_wu_ex5_flush, + xu_wl_rf1_flush => xu_wl_rf1_flush, + xu_wl_ex1_flush => xu_wl_ex1_flush, + xu_wl_ex2_flush => xu_wl_ex2_flush, + xu_wl_ex3_flush => xu_wl_ex3_flush, + xu_wl_ex4_flush => xu_wl_ex4_flush, + xu_wl_ex5_flush => xu_wl_ex5_flush, + xu_iu_l_flush => xu_iu_l_flush, + xu_iu_u_flush => xu_iu_u_flush, + + an_ac_grffence_en_dc_oiu => an_ac_grffence_en_dc_oiu, + + bg_an_ac_func_scan_sn => bg_an_ac_func_scan_sn_omm, + bg_an_ac_abst_scan_sn => bg_an_ac_abst_scan_sn_omm, + bg_an_ac_func_scan_sn_q => bg_an_ac_func_scan_sn_q, + bg_an_ac_abst_scan_sn_q => bg_an_ac_abst_scan_sn_q, + + bg_ac_an_func_scan_ns => "0000000000", + bg_ac_an_abst_scan_ns => "00", + bg_ac_an_func_scan_ns_q => bg_ac_an_func_scan_ns_q, + bg_ac_an_abst_scan_ns_q => bg_ac_an_abst_scan_ns_q, + + bg_pc_l1p_abist_di_0 => "0000", + bg_pc_l1p_abist_g8t1p_renb_0 => '0', + bg_pc_l1p_abist_g8t_bw_0 => '0', + bg_pc_l1p_abist_g8t_bw_1 => '0', + bg_pc_l1p_abist_g8t_dcomp => "0000", + bg_pc_l1p_abist_g8t_wenb => '0', + bg_pc_l1p_abist_raddr_0 => "0000000000", + bg_pc_l1p_abist_waddr_0 => "0000000000", + bg_pc_l1p_abist_wl128_comp_ena => '0', + bg_pc_l1p_abist_wl32_comp_ena => '0', + bg_pc_l1p_abist_di_0_q => bg_pc_l1p_abist_di_0_q, + bg_pc_l1p_abist_g8t1p_renb_0_q => bg_pc_l1p_abist_g8t1p_renb_0_q, + bg_pc_l1p_abist_g8t_bw_0_q => bg_pc_l1p_abist_g8t_bw_0_q, + bg_pc_l1p_abist_g8t_bw_1_q => bg_pc_l1p_abist_g8t_bw_1_q, + bg_pc_l1p_abist_g8t_dcomp_q => bg_pc_l1p_abist_g8t_dcomp_q, + bg_pc_l1p_abist_g8t_wenb_q => bg_pc_l1p_abist_g8t_wenb_q, + bg_pc_l1p_abist_raddr_0_q => bg_pc_l1p_abist_raddr_0_q, + bg_pc_l1p_abist_waddr_0_q => bg_pc_l1p_abist_waddr_0_q, + bg_pc_l1p_abist_wl128_comp_ena_q => bg_pc_l1p_abist_wl128_comp_ena_q, + bg_pc_l1p_abist_wl32_comp_ena_q => bg_pc_l1p_abist_wl32_comp_ena_q, + + bg_pc_l1p_gptr_sl_thold_3 => bg_pc_l1p_gptr_sl_thold_3, + bg_pc_l1p_time_sl_thold_3 => bg_pc_l1p_time_sl_thold_3, + bg_pc_l1p_repr_sl_thold_3 => bg_pc_l1p_repr_sl_thold_3, + bg_pc_l1p_abst_sl_thold_3 => bg_pc_l1p_abst_sl_thold_3, + bg_pc_l1p_func_sl_thold_3 => bg_pc_l1p_func_sl_thold_3, + bg_pc_l1p_func_slp_sl_thold_3 => bg_pc_l1p_func_slp_sl_thold_3, + bg_pc_l1p_bolt_sl_thold_3 => bg_pc_l1p_bolt_sl_thold_3, + bg_pc_l1p_ary_nsl_thold_3 => bg_pc_l1p_ary_nsl_thold_3, + bg_pc_l1p_sg_3 => bg_pc_l1p_sg_3, + bg_pc_l1p_fce_3 => bg_pc_l1p_fce_3, + bg_pc_l1p_bo_enable_3 => bg_pc_l1p_bo_enable_3, + bg_pc_l1p_gptr_sl_thold_2 => bg_pc_l1p_gptr_sl_thold_2_imm, + bg_pc_l1p_time_sl_thold_2 => bg_pc_l1p_time_sl_thold_2_imm, + bg_pc_l1p_repr_sl_thold_2 => bg_pc_l1p_repr_sl_thold_2_imm, + bg_pc_l1p_abst_sl_thold_2 => bg_pc_l1p_abst_sl_thold_2_imm, + bg_pc_l1p_func_sl_thold_2 => bg_pc_l1p_func_sl_thold_2_imm, + bg_pc_l1p_func_slp_sl_thold_2 => bg_pc_l1p_func_slp_sl_thold_2_imm, + bg_pc_l1p_bolt_sl_thold_2 => bg_pc_l1p_bolt_sl_thold_2_imm, + bg_pc_l1p_ary_nsl_thold_2 => bg_pc_l1p_ary_nsl_thold_2_imm, + bg_pc_l1p_sg_2 => bg_pc_l1p_sg_2_imm, + bg_pc_l1p_fce_2 => bg_pc_l1p_fce_2_imm, + bg_pc_l1p_bo_enable_2 => bg_pc_l1p_bo_enable_2_imm, + + bg_pc_bo_unload_iiu => bg_pc_bo_unload_iiu, + bg_pc_bo_load_iiu => bg_pc_bo_load_iiu, + bg_pc_bo_repair_iiu => bg_pc_bo_repair_iiu, + bg_pc_bo_reset_iiu => bg_pc_bo_reset_iiu, + bg_pc_bo_shdata_iiu => bg_pc_bo_shdata_iiu, + bg_pc_bo_select_iiu => bg_pc_bo_select_iiu, + bg_pc_l1p_ccflush_dc_iiu => bg_pc_l1p_ccflush_dc_iiu, + bg_pc_l1p_abist_ena_dc_iiu => bg_pc_l1p_abist_ena_dc_iiu, + bg_pc_l1p_abist_raw_dc_b_iiu => bg_pc_l1p_abist_raw_dc_b_iiu, + + bg_pc_bo_unload_oiu => bg_pc_bo_unload_oiu, + bg_pc_bo_load_oiu => bg_pc_bo_load_oiu, + bg_pc_bo_repair_oiu => bg_pc_bo_repair_oiu, + bg_pc_bo_reset_oiu => bg_pc_bo_reset_oiu, + bg_pc_bo_shdata_oiu => bg_pc_bo_shdata_oiu, + bg_pc_bo_select_oiu => bg_pc_bo_select_oiu, + bg_pc_l1p_ccflush_dc_oiu => bg_pc_l1p_ccflush_dc_oiu, + bg_pc_l1p_abist_ena_dc_oiu => bg_pc_l1p_abist_ena_dc_oiu, + bg_pc_l1p_abist_raw_dc_b_oiu => bg_pc_l1p_abist_raw_dc_b_oiu, + + bg_pc_bo_fail_iiu => bg_pc_bo_fail_omm, + bg_pc_bo_diagout_iiu => bg_pc_bo_diagout_omm, + bg_pc_bo_fail_oiu => bg_pc_bo_fail_oiu, + bg_pc_bo_diagout_oiu => bg_pc_bo_diagout_oiu, + + xu_iu_xucr4_mmu_mchk => xu_iu_xucr4_mmu_mchk, + + gnd => gnd, + vcs => vcs, + vdd => vdd + ); + +a_xuq: entity work.xuq + generic map(a2mode => a2mode, + bcfg_epn_0to15 => bcfg_epn_0to15, + bcfg_epn_16to31 => bcfg_epn_16to31, + bcfg_epn_32to47 => bcfg_epn_32to47, + bcfg_epn_48to51 => bcfg_epn_48to51, + bcfg_rpn_22to31 => bcfg_rpn_22to31, + bcfg_rpn_32to47 => bcfg_rpn_32to47, + bcfg_rpn_48to51 => bcfg_rpn_48to51, + eff_ifar => xu_eff_ifar, + expand_type => expand_type, + l_endian_m => l_endian_m, + lmq_entries => lmq_entries, + real_data_add => xu_real_data_add, + regmode => regmode, + hvmode => hvmode, + st_data_32b_mode => st_data_32b_mode, + threads => threads, + load_credits => load_credits, + store_credits => store_credits, + spr_xucr0_init_mod => spr_xucr0_init_mod, + dc_size => dc_size ) + port map ( + abst_scan_in => an_ac_abst_scan_in_omm_xu(7 to 9), + bcfg_scan_in => an_ac_bcfg_scan_in_omm_bit4, + ccfg_scan_in => an_ac_bcfg_scan_in_omm_bit1, + dcfg_scan_in => an_ac_dcfg_scan_in_omm(2), + func_scan_in => an_ac_func_scan_in_omm_xu(31 to 58), + gptr_scan_in => bx_xu_gptr_scan_out, + repr_scan_in => bx_xu_repr_scan_out, + time_scan_in => bx_xu_time_scan_out, + an_ac_atpg_en_dc => an_ac_atpg_en_dc_oiu, + an_ac_back_inv => an_ac_back_inv_oiu, + an_ac_back_inv_addr => an_ac_back_inv_addr_oiu(64-xu_real_data_add to 63), + an_ac_back_inv_target_bit1 => an_ac_back_inv_target_bit1_oiu, + an_ac_back_inv_target_bit3 => an_ac_back_inv_target_bit3_oiu, + an_ac_back_inv_target_bit4 => an_ac_back_inv_target_bit4_oiu, + an_ac_crit_interrupt => an_ac_crit_interrupt_omm, + an_ac_ext_interrupt => an_ac_ext_interrupt_omm, + an_ac_flh2l2_gate => an_ac_flh2l2_gate_omm, + an_ac_grffence_en_dc => an_ac_grffence_en_dc_oiu, + an_ac_lbist_en_dc => an_ac_lbist_en_dc_oiu, + an_ac_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc_oiu, + an_ac_perf_interrupt => an_ac_perf_interrupt_omm, + an_ac_reld_core_tag => an_ac_reld_core_tag_omm(0 to 4), + an_ac_reld_data => an_ac_reld_data_omm, + an_ac_reld_data_vld => an_ac_reld_data_vld_omm, + an_ac_reld_ecc_err => an_ac_reld_ecc_err_omm, + an_ac_reld_ecc_err_ue => an_ac_reld_ecc_err_ue_omm, + an_ac_reld_qw => an_ac_reld_qw_omm, + an_ac_reld_data_coming => an_ac_reld_data_coming_omm, + an_ac_reld_ditc => an_ac_reld_ditc_omm, + an_ac_reld_crit_qw => an_ac_reld_crit_qw_omm, + an_ac_req_ld_pop => an_ac_req_ld_pop_omm, + an_ac_req_spare_ctrl_a1 => an_ac_req_spare_ctrl_a1_omm, + an_ac_req_st_gather => an_ac_req_st_gather_omm, + an_ac_req_st_pop => an_ac_req_st_pop_omm, + an_ac_reservation_vld => an_ac_reservation_vld_omm, + an_ac_sleep_en => an_ac_sleep_en_omm, + an_ac_stcx_complete => an_ac_stcx_complete_omm, + an_ac_stcx_pass => an_ac_stcx_pass_omm, + xu_iu_stcx_complete => xu_iu_stcx_complete, + lsu_reld_data_vld => lsu_reld_data_vld, + lsu_reld_core_tag => lsu_reld_core_tag, + lsu_reld_qw => lsu_reld_qw , + lsu_reld_ditc => lsu_reld_ditc, + lsu_reld_ecc_err => lsu_reld_ecc_err, + lsu_reld_data => lsu_reld_data, + lsu_req_st_pop => lsu_req_st_pop, + lsu_req_st_pop_thrd => lsu_req_st_pop_thrd, + fu_xu_ex1_ifar0 => fu_xu_ex1_ifar, + fu_xu_ex1_ifar1 => fu_xu_ex1_ifar, + fu_xu_ex1_ifar2 => fu_xu_ex1_ifar, + fu_xu_ex1_ifar3 => fu_xu_ex1_ifar, + fu_xu_ex2_async_block => fu_xu_ex2_async_block, + fu_xu_ex2_ifar_val => fu_xu_ex2_ifar_val, + fu_xu_ex2_ifar_issued => fu_xu_ex2_ifar_issued, + fu_xu_ex2_store_data(0 to 63) => fu_xu_ex2_store_data, + fu_xu_ex2_store_data(64 to 127) => fu_xu_ex2_store_data, + fu_xu_ex2_store_data(128 to 191) => fu_xu_ex2_store_data, + fu_xu_ex2_store_data(192 to 255) => fu_xu_ex2_store_data, + fu_xu_ex2_store_data_val => fu_xu_ex2_store_data_val, + fu_xu_ex3_flush2ucode => fu_xu_ex3_flush2ucode, + fu_xu_ex2_instr_match => fu_xu_ex2_instr_match, + fu_xu_ex2_instr_type => fu_xu_ex2_instr_type, + fu_xu_ex2_is_ucode => fu_xu_ex2_is_ucode, + fu_xu_ex3_ap_int_req => fu_xu_ex3_ap_int_req, + fu_xu_ex3_n_flush => fu_xu_ex3_n_flush, + fu_xu_ex3_np1_flush => fu_xu_ex3_np1_flush, + fu_xu_ex3_regfile_err_det => fu_xu_ex3_regfile_err_det, + fu_xu_ex3_trap => fu_xu_ex3_trap, + fu_xu_ex4_cr0 => fu_xu_ex4_cr, + fu_xu_ex4_cr0_bf => fu_xu_ex4_cr_bf, + fu_xu_ex4_cr1 => fu_xu_ex4_cr, + fu_xu_ex4_cr1_bf => fu_xu_ex4_cr_bf, + fu_xu_ex4_cr2 => fu_xu_ex4_cr, + fu_xu_ex4_cr2_bf => fu_xu_ex4_cr_bf, + fu_xu_ex4_cr3 => fu_xu_ex4_cr, + fu_xu_ex4_cr3_bf => fu_xu_ex4_cr_bf, + fu_xu_ex4_cr_noflush => fu_xu_ex4_cr_noflush, + fu_xu_ex4_cr_val => fu_xu_ex4_cr_val, + fu_xu_regfile_seq_end => fu_xu_regfile_seq_end, + fu_xu_rf1_act => fu_xu_rf1_act, + regf_scan_in => an_ac_regf_scan_in_omm(5 to 11), + slowspr_addr_in => bx_xu_slowspr_addr, + slowspr_data_in => bx_xu_slowspr_data, + slowspr_done_in => bx_xu_slowspr_done, + slowspr_etid_in => bx_xu_slowspr_etid, + slowspr_rw_in => bx_xu_slowspr_rw, + slowspr_val_in => bx_xu_slowspr_val, + spr_pvr_version_dc => spr_pvr_version_dc, + spr_pvr_revision_dc => spr_pvr_revision_dc, + debug_data_in => iu_xu_debug_data, + trigger_data_in => iu_xu_trigger_data, + iu_xu_ex4_tlb_data => iu_xu_ex4_tlb_data, + iu_xu_ierat_ex2_flush_req => iu_xu_ierat_ex2_flush_req, + iu_xu_ierat_ex3_par_err => iu_xu_ierat_ex3_par_err, + iu_xu_ierat_ex4_par_err => iu_xu_ierat_ex4_par_err, + iu_xu_is2_axu_instr_type => iu_xu_is2_axu_instr_type, + iu_xu_is2_axu_ld_or_st => iu_xu_is2_axu_ld_or_st, + iu_xu_is2_axu_ldst_extpid => iu_xu_is2_axu_ldst_extpid, + iu_xu_is2_axu_ldst_forcealign => iu_xu_is2_axu_ldst_forcealign, + iu_xu_is2_axu_ldst_forceexcept => iu_xu_is2_axu_ldst_forceexcept, + iu_xu_is2_axu_ldst_indexed => iu_xu_is2_axu_ldst_indexed, + iu_xu_is2_axu_ldst_size => iu_xu_is2_axu_ldst_size, + iu_xu_is2_axu_ldst_tag => iu_xu_is2_axu_ldst_tag, + iu_xu_is2_axu_ldst_update => iu_xu_is2_axu_ldst_update, + iu_xu_is2_axu_mffgpr => iu_xu_is2_axu_mffgpr, + iu_xu_is2_axu_mftgpr => iu_xu_is2_axu_mftgpr, + iu_xu_is2_axu_store => iu_xu_is2_axu_store, + iu_xu_is2_axu_movedp => iu_xu_is2_axu_movedp, + iu_xu_is2_error => iu_xu_is2_error, + iu_xu_is2_gshare => iu_xu_is2_gshare, + iu_xu_is2_ifar => iu_xu_is2_ifar, + iu_xu_is2_instr => iu_xu_is2_instr, + iu_xu_is2_is_ucode => iu_xu_is2_is_ucode, + iu_xu_is2_match => iu_xu_is2_match, + iu_xu_is2_pred_taken_cnt => iu_xu_is2_pred_taken_cnt, + iu_xu_is2_pred_update => iu_xu_is2_pred_update, + iu_xu_is2_s1 => iu_xu_is2_s1, + iu_xu_is2_s1_vld => iu_xu_is2_s1_vld, + iu_xu_is2_s2 => iu_xu_is2_s2, + iu_xu_is2_s2_vld => iu_xu_is2_s2_vld, + iu_xu_is2_s3 => iu_xu_is2_s3, + iu_xu_is2_s3_vld => iu_xu_is2_s3_vld, + iu_xu_is2_ta => iu_xu_is2_ta, + iu_xu_is2_ta_vld => iu_xu_is2_ta_vld, + iu_xu_is2_tid => iu_xu_is2_tid, + iu_xu_is2_ucode_vld => iu_xu_is2_ucode_vld, + iu_xu_is2_vld => iu_xu_is2_vld, + iu_xu_quiesce => iu_xu_quiesce, + iu_xu_ra => iu_xu_ra, + iu_xu_request => iu_xu_request, + iu_xu_thread => iu_xu_thread, + iu_xu_userdef => iu_xu_userdef, + iu_xu_wimge => iu_xu_wimge, + mm_xu_derat_mmucr0_0 => mm_xu_derat_mmucr0_0, + mm_xu_derat_mmucr0_1 => mm_xu_derat_mmucr0_1, + mm_xu_derat_mmucr0_2 => mm_xu_derat_mmucr0_2, + mm_xu_derat_mmucr0_3 => mm_xu_derat_mmucr0_3, + mm_xu_derat_mmucr1 => mm_xu_derat_mmucr1, + mm_xu_derat_pid0 => mm_xu_derat_pid0, + mm_xu_derat_pid1 => mm_xu_derat_pid1, + mm_xu_derat_pid2 => mm_xu_derat_pid2, + mm_xu_derat_pid3 => mm_xu_derat_pid3, + mm_xu_derat_rel_data => mm_xu_derat_rel_data, + mm_xu_derat_rel_val => mm_xu_derat_rel_val, + mm_xu_derat_snoop_attr => mm_xu_derat_snoop_attr, + mm_xu_derat_snoop_val => mm_xu_derat_snoop_val, + mm_xu_derat_snoop_coming => mm_xu_derat_snoop_coming, + mm_xu_derat_snoop_vpn => mm_xu_derat_snoop_vpn, + mm_xu_eratmiss_done => mm_xu_eratmiss_done, + mm_xu_esr_pt => mm_xu_esr_pt, + mm_xu_esr_data => mm_xu_esr_data, + mm_xu_esr_epid => mm_xu_esr_epid, + mm_xu_esr_st => mm_xu_esr_st, + mm_xu_ex3_flush_req => mm_xu_ex3_flush_req, + xu_mm_rf1_is_tlbsxr => xu_mm_rf1_is_tlbsxr, + mm_xu_hold_done => mm_xu_hold_done, + mm_xu_hold_req => mm_xu_hold_req, + mm_xu_hv_priv => mm_xu_hv_priv, + mm_xu_illeg_instr => mm_xu_illeg_instr, + mm_xu_local_snoop_reject => mm_xu_local_snoop_reject, + mm_xu_lrat_miss => mm_xu_lrat_miss, + mm_xu_lsu_addr => mm_xu_lsu_addr, + mm_xu_lsu_lpid => mm_xu_lsu_lpid, + mm_xu_lsu_lpidr => mm_xu_lsu_lpidr, + mm_xu_lsu_gs => mm_xu_lsu_gs, + mm_xu_lsu_ind => mm_xu_lsu_ind, + mm_xu_lsu_lbit => mm_xu_lsu_lbit, + mm_xu_lsu_req => mm_xu_lsu_req, + mm_xu_lsu_ttype => mm_xu_lsu_ttype, + mm_xu_lsu_u => mm_xu_lsu_u, + mm_xu_lsu_wimge => mm_xu_lsu_wimge, + mm_xu_pt_fault => mm_xu_pt_fault, + mm_xu_quiesce => mm_xu_quiesce, + mm_xu_tlb_inelig => mm_xu_tlb_inelig, + mm_xu_tlb_miss => mm_xu_tlb_miss, + mm_xu_tlb_multihit_err => mm_xu_tlb_multihit_err, + mm_xu_tlb_par_err => mm_xu_tlb_par_err, + mm_xu_lru_par_err => mm_xu_lru_par_err, + mm_xu_cr0_eq_valid => mm_xu_cr0_eq_valid, + mm_xu_cr0_eq => mm_xu_cr0_eq, + nclk => a2_nclk, + pc_xu_abst_sl_thold_3 => pc_xu_abst_sl_thold_3_ofu, + pc_xu_abst_slp_sl_thold_3 => pc_xu_abst_slp_sl_thold_3_ofu, + pc_xu_regf_sl_thold_3 => pc_xu_regf_sl_thold_3_ofu, + pc_xu_regf_slp_sl_thold_3 => pc_xu_regf_slp_sl_thold_3_ofu, + pc_xu_ary_nsl_thold_3 => pc_xu_ary_nsl_thold_3_ofu, + pc_xu_ary_slp_nsl_thold_3 => pc_xu_ary_slp_nsl_thold_3_ofu, + pc_xu_bolt_sl_thold_3 => pc_xu_bolt_sl_thold_3_ofu, + pc_xu_bo_enable_3 => pc_xu_bo_enable_3_ofu, + pc_xu_bo_load => pc_xu_bo_load_ofu, + pc_xu_bo_unload => pc_xu_bo_unload_ofu, + pc_xu_bo_repair => pc_xu_bo_repair_ofu, + pc_xu_bo_reset => pc_xu_bo_reset_ofu, + pc_xu_bo_shdata => pc_xu_bo_shdata_ofu, + pc_xu_bo_select => pc_xu_bo_select_ofu, + pc_xu_cache_par_err_event => pc_xu_cache_par_err_event_ofu, + pc_xu_ccflush_dc => pc_xu_ccflush_dc_ofu, + pc_xu_cfg_sl_thold_3 => pc_xu_cfg_sl_thold_3_ofu, + pc_xu_cfg_slp_sl_thold_3 => pc_xu_cfg_slp_sl_thold_3_ofu, + pc_xu_dbg_action => pc_xu_dbg_action_ofu, + pc_xu_debug_mux1_ctrls => pc_xu_debug_mux1_ctrls_ofu, + pc_xu_debug_mux2_ctrls => pc_xu_debug_mux2_ctrls_ofu, + pc_xu_debug_mux3_ctrls => pc_xu_debug_mux3_ctrls_ofu, + pc_xu_debug_mux4_ctrls => pc_xu_debug_mux4_ctrls_ofu, + pc_xu_decrem_dis_on_stop => pc_xu_decrem_dis_on_stop_ofu, + xu_pc_spr_ccr0_we => xu_pc_spr_ccr0_we, + xu_pc_spr_ccr0_pme => xu_pc_spr_ccr0_pme, + pc_xu_event_bus_enable => pc_xu_event_bus_enable_ofu, + pc_xu_event_count_mode => pc_xu_event_count_mode_ofu, + pc_xu_event_mux_ctrls => pc_xu_event_mux_ctrls_ofu, + pc_xu_extirpts_dis_on_stop => pc_xu_extirpts_dis_on_stop_ofu, + pc_xu_fce_3 => pc_xu_fce_3_ofu, + pc_xu_force_ude => pc_xu_force_ude_ofu, + pc_xu_func_nsl_thold_3 => pc_xu_func_nsl_thold_3_ofu, + pc_xu_func_sl_thold_3 => pc_xu_func_sl_thold_3_ofu, + pc_xu_func_slp_nsl_thold_3 => pc_xu_func_slp_nsl_thold_3_ofu, + pc_xu_func_slp_sl_thold_3 => pc_xu_func_slp_sl_thold_3_ofu, + pc_xu_gptr_sl_thold_3 => pc_xu_gptr_sl_thold_3_ofu, + pc_xu_init_reset => pc_xu_init_reset_ofu, + pc_xu_inj_dcachedir_multihit => pc_xu_inj_dcachedir_multihit_ofu, + pc_xu_instr_trace_mode => pc_xu_instr_trace_mode_ofu, + pc_xu_instr_trace_tid => pc_xu_instr_trace_tid_ofu, + pc_xu_lsu_event_mux_ctrls => pc_xu_lsu_event_mux_ctrls_ofu, + pc_xu_msrovride_de => pc_xu_msrovride_de, + pc_xu_msrovride_enab => pc_xu_msrovride_enab_ofu, + pc_xu_msrovride_pr => pc_xu_msrovride_pr_ofu, + pc_xu_msrovride_gs => pc_xu_msrovride_gs_ofu, + pc_xu_ram_execute => pc_xu_ram_execute_ofu, + pc_xu_ram_flush_thread => pc_xu_ram_flush_thread_ofu, + pc_xu_ram_mode => pc_xu_ram_mode_ofu, + pc_xu_ram_thread => pc_xu_ram_thread_ofu, + pc_xu_repr_sl_thold_3 => pc_xu_repr_sl_thold_3_ofu, + pc_xu_reset_1_complete => pc_xu_reset_1_cmplt_ofu, + pc_xu_reset_2_complete => pc_xu_reset_2_cmplt_ofu, + pc_xu_reset_3_complete => pc_xu_reset_3_cmplt_ofu, + pc_xu_reset_wd_complete => pc_xu_reset_wd_cmplt_ofu, + pc_xu_sg_3 => pc_xu_sg_3_ofu, + pc_xu_step => pc_xu_step_ofu, + pc_xu_stop => pc_xu_stop_ofu, + pc_xu_timebase_dis_on_stop => pc_xu_timebase_dis_on_stop_ofu, + pc_xu_time_sl_thold_3 => pc_xu_time_sl_thold_3_ofu, + pc_xu_trace_bus_enable => pc_xu_trace_bus_enable_ofu, + pc_xu_inj_dcache_parity => pc_xu_inj_dcache_parity_ofu, + pc_xu_inj_dcachedir_parity => pc_xu_inj_dcachedir_parity_ofu, + pc_xu_inj_llbust_attempt => pc_xu_inj_llbust_attempt_ofu, + pc_xu_inj_llbust_failed => pc_xu_inj_llbust_failed_ofu, + pc_xu_inj_sprg_ecc => pc_xu_inj_sprg_ecc_ofu, + pc_xu_inj_regfile_parity => pc_xu_inj_regfile_parity_ofu, + pc_xu_inj_wdt_reset => pc_xu_inj_wdt_reset_ofu, + pc_xu_abist_dcomp_g6t_2r => pc_xu_abist_dcomp_g6t_2r_ofu(0 to 3), + pc_xu_abist_di_0 => pc_xu_abist_di_0_ofu(0 to 3), + pc_xu_abist_di_1 => pc_xu_abist_di_1_ofu(0 to 3), + pc_xu_abist_di_g6t_2r => pc_xu_abist_di_g6t_2r_ofu(0 to 3), + pc_xu_abist_ena_dc => pc_xu_abist_ena_dc_ofu, + pc_xu_abist_g6t_bw => pc_xu_abist_g6t_bw_ofu(0 to 1), + pc_xu_abist_g6t_r_wb => pc_xu_abist_g6t_r_wb_ofu, + pc_xu_abist_g8t1p_renb_0 => pc_xu_abist_g8t1p_renb_0_ofu, + pc_xu_abist_g8t_bw_0 => pc_xu_abist_g8t_bw_0_ofu, + pc_xu_abist_g8t_bw_1 => pc_xu_abist_g8t_bw_1_ofu, + pc_xu_abist_g8t_dcomp => pc_xu_abist_g8t_dcomp_ofu(0 to 3), + pc_xu_abist_g8t_wenb => pc_xu_abist_g8t_wenb_ofu, + pc_xu_abist_grf_renb_0 => pc_xu_abist_grf_renb_0_ofu, + pc_xu_abist_grf_renb_1 => pc_xu_abist_grf_renb_1_ofu, + pc_xu_abist_grf_wenb_0 => pc_xu_abist_grf_wenb_0_ofu, + pc_xu_abist_grf_wenb_1 => pc_xu_abist_grf_wenb_1_ofu, + pc_xu_abist_raddr_0 => pc_xu_abist_raddr_0_ofu(0 to 9), + pc_xu_abist_raddr_1 => pc_xu_abist_raddr_1_ofu(0 to 9), + pc_xu_abist_raw_dc_b => pc_xu_abist_raw_dc_b_ofu, + pc_xu_abist_waddr_0 => pc_xu_abist_waddr_0_ofu(0 to 9), + pc_xu_abist_waddr_1 => pc_xu_abist_waddr_1_ofu(0 to 9), + pc_xu_abist_wl144_comp_ena => pc_xu_abist_wl144_comp_ena_ofu, + pc_xu_abist_wl32_comp_ena => pc_xu_abist_wl32_comp_ena_ofu, + pc_xu_abist_wl512_comp_ena => pc_xu_abist_wl512_comp_ena_ofu, + an_ac_coreid => an_ac_coreid_omm, + an_ac_external_mchk => an_ac_external_mchk_omm, + an_ac_hang_pulse => an_ac_hang_pulse_omm, + an_ac_scan_diag_dc => an_ac_scan_diag_dc_oiu, + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b_oiu, + an_ac_tb_update_enable => an_ac_tb_update_enable_omm, + an_ac_tb_update_pulse => an_ac_tb_update_pulse_omm, + an_ac_reld_l1_dump => an_ac_reld_l1_dump_omm, + ac_tc_machine_check => ac_an_machine_check_imm, + ac_an_req => ac_an_req_imm, + ac_an_req_endian => ac_an_req_endian_imm, + ac_an_req_ld_core_tag => ac_an_req_ld_core_tag_imm, + ac_an_req_ld_xfr_len => ac_an_req_ld_xfr_len_imm, + ac_an_req_pwr_token => ac_an_req_pwr_token_imm, + ac_an_req_ra => ac_an_req_ra_imm, + ac_an_req_spare_ctrl_a0 => ac_an_req_spare_ctrl_a0_imm, + ac_an_req_thread => ac_an_req_thread_imm, + ac_an_req_ttype => ac_an_req_ttype_imm, + ac_an_req_user_defined => ac_an_req_user_defined_imm, + ac_an_req_wimg_g => ac_an_req_wimg_g_imm, + ac_an_req_wimg_i => ac_an_req_wimg_i_imm, + ac_an_req_wimg_m => ac_an_req_wimg_m_imm, + ac_an_req_wimg_w => ac_an_req_wimg_w_imm, + ac_an_st_byte_enbl => xu_st_byte_enbl, + ac_an_st_data => xu_st_data, + ac_an_st_data_pwr_token => ac_an_st_data_pwr_token_imm, + an_ac_req_st_pop_thrd => an_ac_req_st_pop_thrd_omm, + ac_tc_debug_trigger => ac_an_debug_trigger_imm, + ac_tc_reset_1_request => ac_an_reset_1_request_imm, + ac_tc_reset_2_request => ac_an_reset_2_request_imm, + ac_tc_reset_3_request => ac_an_reset_3_request_imm, + ac_tc_reset_wd_request => ac_an_reset_wd_request_imm, + abst_scan_out => ac_an_abst_scan_out_imm_xu(7 to 9), + bcfg_scan_out => ac_an_bcfg_scan_out_imm(4), + ccfg_scan_out => xu_fu_ccfg_scan_out, + dcfg_scan_out => ac_an_dcfg_scan_out_imm(2), + func_scan_out => ac_an_func_scan_out_imm_xu(31 to 58), + gptr_scan_out => xu_mm_gptr_scan_out, + repr_scan_out => xu_mm_repr_scan_out, + time_scan_out => xu_mm_time_scan_out, + regf_scan_out => ac_an_regf_scan_out_imm(5 to 11), + xu_n_is2_flush => xu_n_is2_flush, + xu_n_rf0_flush => xu_n_rf0_flush, + xu_n_rf1_flush => xu_n_rf1_flush, + xu_n_ex1_flush => xu_n_ex1_flush, + xu_n_ex2_flush => xu_n_ex2_flush, + xu_n_ex3_flush => xu_n_ex3_flush, + xu_n_ex4_flush => xu_n_ex4_flush, + xu_n_ex5_flush => xu_n_ex5_flush, + xu_s_rf1_flush => xu_s_rf1_flush, + xu_s_ex1_flush => xu_s_ex1_flush, + xu_s_ex2_flush => xu_s_ex2_flush, + xu_s_ex3_flush => xu_s_ex3_flush, + xu_s_ex4_flush => xu_s_ex4_flush, + xu_s_ex5_flush => xu_s_ex5_flush, + xu_wu_rf1_flush => xu_wu_rf1_flush, + xu_wu_ex1_flush => xu_wu_ex1_flush, + xu_wu_ex2_flush => xu_wu_ex2_flush, + xu_wu_ex3_flush => xu_wu_ex3_flush, + xu_wu_ex4_flush => xu_wu_ex4_flush, + xu_wu_ex5_flush => xu_wu_ex5_flush, + xu_wl_rf1_flush => xu_wl_rf1_flush, + xu_wl_ex1_flush => xu_wl_ex1_flush, + xu_wl_ex2_flush => xu_wl_ex2_flush, + xu_wl_ex3_flush => xu_wl_ex3_flush, + xu_wl_ex4_flush => xu_wl_ex4_flush, + xu_wl_ex5_flush => xu_wl_ex5_flush, + xu_fu_ccr2_ap => xu_fu_ccr2_ap, + xu_fu_ex3_eff_addr => xu_fu_ex3_eff_addr, + xu_fu_ex6_load_data => xu_fu_ex6_load_data, + xu_fu_ex5_load_le => xu_fu_ex5_load_le, + xu_fu_ex5_load_tag => xu_fu_ex5_load_tag, + xu_fu_ex5_load_val => xu_fu_ex5_load_val, + xu_fu_ex5_reload_val => xu_fu_ex5_reload_val, + xu_fu_msr_fp => xu_fu_msr_fp, + xu_fu_msr_pr => xu_fu_msr_pr, + xu_fu_msr_gs => xu_fu_msr_gs, + xu_fu_msr_spv => xu_fu_msr_spv, + xu_fu_regfile_seq_beg => xu_fu_regfile_seq_beg, + xu_iu_complete_qentry => xu_iu_complete_qentry, + xu_iu_complete_target_type => xu_iu_complete_target_type, + xu_iu_complete_tid => xu_iu_complete_tid, + xu_iu_ex1_ra_entry => xu_iu_ex1_ra_entry, + xu_iu_ex1_rb => xu_iu_ex1_rb, + xu_iu_ex1_rs_is => xu_iu_ex1_rs_is, + xu_iu_ex5_bclr => xu_iu_ex5_bclr, + xu_iu_ex5_bh => xu_iu_ex5_bh, + xu_iu_ex5_br_hist => xu_iu_ex5_br_hist, + xu_iu_ex5_br_taken => xu_iu_ex5_br_taken, + xu_iu_ex5_br_update => xu_iu_ex5_br_update, + xu_iu_ex5_getNIA => xu_iu_ex5_getNIA, + xu_iu_ex5_gshare => xu_iu_ex5_gshare, + xu_iu_ex5_ifar => xu_iu_ex5_ifar, + xu_iu_ex5_lk => xu_iu_ex5_lk, + xu_iu_ex5_ppc_cpl => xu_iu_ex5_ppc_cpl, + xu_iu_ex4_loadmiss_qentry => xu_iu_ex4_loadmiss_qentry, + xu_iu_ex4_loadmiss_target => xu_iu_ex4_loadmiss_target, + xu_iu_ex4_loadmiss_target_type=> xu_iu_ex4_loadmiss_target_type, + xu_iu_ex4_loadmiss_tid => xu_iu_ex4_loadmiss_tid, + xu_iu_ex4_rs_data => xu_iu_ex4_rs_data, + xu_iu_ex5_tid => xu_iu_ex5_tid, + xu_iu_ex5_val => xu_iu_ex5_val, + xu_iu_ex5_loadmiss_qentry => xu_iu_ex5_loadmiss_qentry, + xu_iu_ex5_loadmiss_target => xu_iu_ex5_loadmiss_target, + xu_iu_ex5_loadmiss_target_type=> xu_iu_ex5_loadmiss_target_type, + xu_iu_ex5_loadmiss_tid => xu_iu_ex5_loadmiss_tid, + xu_iu_ex6_icbi_val => xu_iu_ex6_icbi_val, + xu_iu_ex6_icbi_addr => xu_iu_ex6_icbi_addr, + xu_iu_ex6_pri => xu_iu_ex6_pri, + xu_iu_ex6_pri_val => xu_iu_ex6_pri_val, + xu_iu_flush_2ucode => xu_iu_flush_2ucode, + xu_iu_flush_2ucode_type => xu_iu_flush_2ucode_type, + xu_iu_hid_mmu_mode => xu_iu_hid_mmu_mode, + xu_iu_xucr0_rel => xu_iu_xucr0_rel, + xu_iu_ici => xu_iu_ici, + xu_iu_iu0_flush_ifar0 => xu_iu_iu0_flush_ifar0, + xu_iu_iu0_flush_ifar1 => xu_iu_iu0_flush_ifar1, + xu_iu_iu0_flush_ifar2 => xu_iu_iu0_flush_ifar2, + xu_iu_iu0_flush_ifar3 => xu_iu_iu0_flush_ifar3, + xu_iu_larx_done_tid => xu_iu_larx_done_tid, + xu_iu_set_barr_tid => xu_iu_set_barr_tid, + xu_iu_membar_tid => xu_iu_membar_tid, + xu_iu_msr_cm => xu_iu_msr_cm, + xu_iu_msr_hv => xu_iu_msr_hv, + xu_iu_msr_is => xu_iu_msr_is, + xu_iu_msr_pr => xu_iu_msr_pr, + xu_iu_multdiv_done => xu_iu_multdiv_done, + xu_iu_need_hole => xu_iu_need_hole, + xu_iu_raise_iss_pri => xu_iu_raise_iss_pri, + xu_iu_ram_issue => xu_iu_ram_issue, + xu_iu_ex1_is_csync => xu_iu_ex1_is_csync, + xu_iu_ex1_is_isync => xu_iu_ex1_is_isync, + xu_iu_rf1_is_eratilx => xu_iu_rf1_is_eratilx, + xu_iu_rf1_is_eratre => xu_iu_rf1_is_eratre, + xu_iu_rf1_is_eratsx => xu_iu_rf1_is_eratsx, + xu_iu_rf1_is_eratwe => xu_iu_rf1_is_eratwe, + xu_iu_rf1_val => xu_iu_rf1_val, + xu_iu_rf1_ws => xu_iu_rf1_ws, + xu_iu_rf1_t => xu_iu_rf1_t, + xu_iu_run_thread => xu_iu_run_thread, + xu_iu_single_instr_mode => xu_iu_single_instr_mode, + xu_iu_slowspr_done => xu_iu_slowspr_done, + xu_iu_spr_ccr2_en_dcr => xu_iu_spr_ccr2_en_dcr, + xu_iu_spr_ccr2_ifratsc => xu_iu_spr_ccr2_ifratsc, + xu_iu_spr_ccr2_ifrat => xu_iu_spr_ccr2_ifrat, + xu_bx_ccr2_en_ditc => xu_bx_ccr2_en_ditc, + xu_iu_spr_xer0 => xu_iu_spr_xer0, + xu_iu_spr_xer1 => xu_iu_spr_xer1, + xu_iu_spr_xer2 => xu_iu_spr_xer2, + xu_iu_spr_xer3 => xu_iu_spr_xer3, + xu_iu_uc_flush_ifar0 => xu_iu_uc_flush_ifar0, + xu_iu_uc_flush_ifar1 => xu_iu_uc_flush_ifar1, + xu_iu_uc_flush_ifar2 => xu_iu_uc_flush_ifar2, + xu_iu_uc_flush_ifar3 => xu_iu_uc_flush_ifar3, + xu_iu_ucode_restart => xu_iu_ucode_restart, + xu_mm_derat_epn => xu_mm_derat_epn, + xu_mm_derat_lpid => xu_mm_derat_lpid, + xu_mm_derat_mmucr0 => xu_mm_derat_mmucr0, + xu_mm_derat_mmucr0_we => xu_mm_derat_mmucr0_we, + xu_mm_derat_mmucr1 => xu_mm_derat_mmucr1, + xu_mm_derat_mmucr1_we => xu_mm_derat_mmucr1_we, + xu_mm_derat_req => xu_mm_derat_req, + xu_mm_derat_snoop_ack => xu_mm_derat_snoop_ack, + xu_mm_derat_state => xu_mm_derat_state, + xu_mm_derat_thdid => xu_mm_derat_thdid, + xu_mm_derat_tid => xu_mm_derat_tid, + xu_mm_derat_ttype => xu_mm_derat_ttype, + xu_mm_ex2_eff_addr => xu_mm_ex2_eff_addr, + xu_mm_ex1_rs_is => xu_mm_ex1_rs_is, + xu_mm_ex4_flush => xu_mm_ex4_flush, + xu_mm_ex5_flush => xu_mm_ex5_flush, + xu_mm_ex5_perf_dtlb => xu_mm_ex5_perf_dtlb, + xu_mm_ex5_perf_itlb => xu_mm_ex5_perf_itlb, + xu_mm_hid_mmu_mode => xu_mm_hid_mmu_mode, + xu_mm_hold_ack => xu_mm_hold_ack, + xu_mm_ierat_flush => xu_mm_ierat_flush, + xu_mm_ierat_miss => xu_mm_ierat_miss, + xu_mm_lmq_stq_empty => xu_mm_lmq_stq_empty, + xu_mm_lsu_token => xu_mm_lsu_token, + xu_mm_msr_cm => xu_mm_msr_cm, + xu_mm_msr_ds => xu_mm_msr_ds, + xu_mm_msr_gs => xu_mm_msr_gs, + xu_iu_msr_gs => xu_iu_msr_gs, + xu_mm_msr_is => xu_mm_msr_is, + xu_mm_msr_pr => xu_mm_msr_pr, + xu_mm_ex1_is_csync => xu_mm_ex1_is_csync, + xu_mm_ex1_is_isync => xu_mm_ex1_is_isync, + xu_mm_rf1_is_eratilx => xu_mm_rf1_is_eratilx, + xu_mm_rf1_is_erativax => xu_mm_rf1_is_erativax, + xu_mm_rf1_is_tlbilx => xu_mm_rf1_is_tlbilx, + xu_mm_rf1_is_tlbivax => xu_mm_rf1_is_tlbivax, + xu_mm_rf1_is_tlbre => xu_mm_rf1_is_tlbre, + xu_mm_rf1_is_tlbsx => xu_mm_rf1_is_tlbsx, + xu_mm_rf1_is_tlbsrx => xu_mm_rf1_is_tlbsrx, + xu_mm_rf1_is_tlbwe => xu_mm_rf1_is_tlbwe, + xu_mm_rf1_val => xu_mm_rf1_val, + xu_mm_rf1_t => xu_mm_rf1_t, + xu_mm_spr_epcr_dgtmi => xu_mm_spr_epcr_dgtmi, + xu_mm_spr_epcr_dmiuh => xu_mm_spr_epcr_dmiuh, + slowspr_addr_out => xu_mm_slowspr_addr, + slowspr_data_out => xu_mm_slowspr_data, + slowspr_done_out => xu_mm_slowspr_done, + slowspr_etid_out => xu_mm_slowspr_etid, + slowspr_rw_out => xu_mm_slowspr_rw, + slowspr_val_out => xu_mm_slowspr_val, + debug_data_out => xu_mm_debug_data, + trigger_data_out => xu_mm_trigger_data, + xu_pc_bo_fail => xu_pc_bo_fail, + xu_pc_bo_diagout => xu_pc_bo_diagout, + xu_pc_err_attention_instr => xu_pc_err_attention_instr, + xu_pc_err_dcache_parity => xu_pc_err_dcache_parity, + xu_pc_err_dcachedir_multihit => xu_pc_err_dcachedir_multihit, + xu_pc_err_dcachedir_parity => xu_pc_err_dcachedir_parity, + xu_pc_err_debug_event => xu_pc_err_debug_event, + xu_pc_err_mcsr_summary => xu_pc_err_mcsr_summary, + xu_pc_err_ierat_parity => xu_pc_err_ierat_parity, + xu_pc_err_derat_parity => xu_pc_err_derat_parity, + xu_pc_err_ditc_overrun => xu_pc_err_ditc_overrun, + xu_pc_err_tlb_parity => xu_pc_err_tlb_parity, + xu_pc_err_tlb_lru_parity => xu_pc_err_tlb_lru_parity, + xu_pc_err_ierat_multihit => xu_pc_err_ierat_multihit, + xu_pc_err_derat_multihit => xu_pc_err_derat_multihit, + xu_pc_err_tlb_multihit => xu_pc_err_tlb_multihit, + xu_pc_err_ext_mchk => xu_pc_err_ext_mchk, + xu_pc_err_local_snoop_reject => xu_pc_err_local_snoop_reject, + xu_pc_err_l2intrf_ecc => xu_pc_err_l2intrf_ecc, + xu_pc_err_l2intrf_ue => xu_pc_err_l2intrf_ue, + xu_pc_err_llbust_attempt => xu_pc_err_llbust_attempt, + xu_pc_err_llbust_failed => xu_pc_err_llbust_failed, + xu_pc_err_nia_miscmpr => xu_pc_err_nia_miscmpr, + xu_pc_err_regfile_parity => xu_pc_err_regfile_parity, + xu_pc_err_regfile_ue => xu_pc_err_regfile_ue, + xu_pc_err_sprg_ecc => xu_pc_err_sprg_ecc, + xu_pc_err_sprg_ue => xu_pc_err_sprg_ue, + xu_pc_err_wdt_reset => xu_pc_err_wdt_reset, + xu_pc_err_invld_reld => xu_pc_err_invld_reld, + xu_pc_err_l2credit_overrun => xu_pc_err_l2credit_overrun, + xu_pc_lsu_event_data => xu_pc_lsu_event_data, + xu_pc_event_data => xu_pc_event_data, + xu_pc_ram_data => xu_pc_ram_data, + xu_pc_ram_done => xu_pc_ram_done, + xu_pc_ram_interrupt => xu_pc_ram_interrupt, + xu_pc_running => xu_pc_running, + xu_pc_step_done => xu_pc_step_done, + xu_pc_stop_dbg_event => xu_pc_stop_dbg_event, + xu_bx_ex1_mtdp_val => xu_bx_ex1_mtdp_val , + xu_bx_ex1_mfdp_val => xu_bx_ex1_mfdp_val , + xu_bx_ex1_ipc_thrd => xu_bx_ex1_ipc_thrd , + xu_bx_ex2_ipc_ba => xu_bx_ex2_ipc_ba , + xu_bx_ex2_ipc_sz => xu_bx_ex2_ipc_sz , + xu_bx_ex4_256st_data => xu_bx_ex4_256st_data(128 to 255) , + xu_iu_reld_core_tag => xu_iu_reld_core_tag, + xu_iu_reld_core_tag_clone => xu_iu_reld_core_tag_clone, + xu_iu_reld_data => xu_iu_reld_data, + xu_iu_reld_data_coming_clone => xu_iu_reld_data_coming_clone, + xu_iu_reld_data_vld => xu_iu_reld_data_vld, + xu_iu_reld_data_vld_clone => xu_iu_reld_data_vld_clone, + xu_iu_reld_ditc_clone => xu_iu_reld_ditc_clone, + xu_iu_reld_ecc_err => xu_iu_reld_ecc_err, + xu_iu_reld_ecc_err_ue => xu_iu_reld_ecc_err_ue, + xu_iu_reld_qw => xu_iu_reld_qw, + + bx_xu_ex4_mtdp_cr_status => bx_xu_ex4_mtdp_cr_status , + bx_xu_ex4_mfdp_cr_status => bx_xu_ex4_mfdp_cr_status , + bx_xu_ex5_dp_data => bx_xu_ex5_dp_data , + bx_xu_quiesce => bx_xu_quiesce, + + bx_lsu_ob_pwr_tok => bx_lsu_ob_pwr_tok , + bx_lsu_ob_req_val => bx_lsu_ob_req_val , + bx_lsu_ob_ditc_val => bx_lsu_ob_ditc_val, + bx_lsu_ob_thrd => bx_lsu_ob_thrd , + bx_lsu_ob_qw => bx_lsu_ob_qw , + bx_lsu_ob_dest => bx_lsu_ob_dest , + bx_lsu_ob_data => bx_lsu_ob_data , + bx_lsu_ob_addr => bx_lsu_ob_addr , + lsu_bx_cmd_avail => lsu_bx_cmd_avail , + lsu_bx_cmd_sent => lsu_bx_cmd_sent , + lsu_bx_cmd_stall => lsu_bx_cmd_stall , + + + + ac_an_reld_ditc_pop_int => ac_an_reld_ditc_pop_int, + ac_an_reld_ditc_pop_q => ac_an_reld_ditc_pop_imm, + bx_ib_empty_int => bx_ib_empty_int, + bx_ib_empty_q => ac_an_box_empty_imm, + xu_iu_l_flush => xu_iu_l_flush, + xu_iu_u_flush => xu_iu_u_flush, + xu_pc_err_mchk_disabled => xu_pc_err_mchk_disabled, + xu_fu_lbist_ary_wrt_thru_dc => xu_fu_lbist_ary_wrt_thru_dc, + xu_fu_lbist_en_dc => xu_fu_lbist_en_dc, + xu_iu_xucr4_mmu_mchk => xu_iu_xucr4_mmu_mchk, + xu_mm_xucr4_mmu_mchk => xu_mm_xucr4_mmu_mchk, + + gnd => gnd, + vcs => vcs, + vdd => vdd + ); + + ac_an_st_byte_enbl_imm <= xu_st_byte_enbl; + ac_an_st_data_imm <= xu_st_data; + + + + + + +a_mmq: entity work.mmq + generic map(data_out_width => data_out_width, + debug_event_width => debug_event_width, + debug_trace_width => debug_trace_width, + epn_width => epn_width, + eptr_width => eptr_width, + erat_ary_data_width => erat_ary_data_width, + erat_cam_data_width => erat_cam_data_width, + erat_rel_data_width => erat_rel_data_width, + error_width => error_width, + expand_tlb_type => expand_tlb_type, + expand_type => expand_type, + extclass_width => extclass_width, + inv_seq_width => inv_seq_width, + lpid_width => lpid_width, + lru_width => lru_width, + mmucr0_width => mmucr0_width, + mmucr1_width => mmucr1_width, + mmucr2_width => mmucr2_width, + mmucr3_width => mmucr3_width, + pid_width => pid_width, + por_seq_width => por_seq_width, + ra_entry_width => ra_entry_width, + real_addr_width => real_addr_width, + req_epn_width => req_epn_width, + rpn_width => rpn_width, + rs_data_width => rs_data_width, + rs_is_width => rs_is_width, + spr_addr_width => spr_addr_width, + spr_ctl_width => spr_ctl_width, + spr_data_width => spr_data_width, + spr_etid_width => spr_etid_width, + state_width => state_width, + thdid_width => thdid_width, + tlb_addr_width => tlb_addr_width, + tlb_num_entry => tlb_num_entry, + tlb_num_entry_log2 => tlb_num_entry_log2, + tlb_seq_width => tlb_seq_width, + tlb_tag_width => tlb_tag_width, + tlb_way_width => tlb_way_width, + tlb_ways => tlb_ways, + tlb_word_width => tlb_word_width, + tlbsel_width => tlbsel_width, + ttype_width => ttype_width, + vpn_width => vpn_width, + watermark_width => watermark_width, + ws_width => ws_width) + port map ( + an_ac_abst_scan_in => an_ac_abst_scan_in(0 to 9), + an_ac_bcfg_scan_in => an_ac_bcfg_scan_in(0 to 4), + an_ac_dcfg_scan_in => an_ac_dcfg_scan_in(0 to 2), + an_ac_func_scan_in => an_ac_func_scan_in(0 to 63), + gptr_scan_in => xu_mm_gptr_scan_out, + repr_scan_in => xu_mm_repr_scan_out, + time_scan_in => xu_mm_time_scan_out, + an_ac_back_inv => an_ac_back_inv, + an_ac_back_inv_addr => an_ac_back_inv_addr, + an_ac_back_inv_lbit => an_ac_back_inv_lbit, + an_ac_back_inv_gs => an_ac_back_inv_gs, + an_ac_back_inv_ind => an_ac_back_inv_ind, + an_ac_back_inv_local => an_ac_back_inv_local, + an_ac_back_inv_lpar_id => an_ac_back_inv_lpar_id, + an_ac_back_inv_target => an_ac_back_inv_target, + an_ac_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc, + an_ac_reld_core_tag => an_ac_reld_core_tag, + an_ac_reld_data => an_ac_reld_data, + an_ac_reld_data_vld => an_ac_reld_data_vld, + an_ac_reld_ecc_err => an_ac_reld_ecc_err, + an_ac_reld_ecc_err_ue => an_ac_reld_ecc_err_ue, + an_ac_reld_qw => an_ac_reld_qw(57 to 59), + an_ac_reld_ditc => an_ac_reld_ditc, + an_ac_reld_crit_qw => an_ac_reld_crit_qw, + iu_mm_ierat_epn => iu_mm_ierat_epn, + iu_mm_ierat_flush => iu_mm_ierat_flush, + iu_mm_ierat_mmucr0 => iu_mm_ierat_mmucr0, + iu_mm_ierat_mmucr0_we => iu_mm_ierat_mmucr0_we, + iu_mm_ierat_mmucr1 => iu_mm_ierat_mmucr1, + iu_mm_ierat_mmucr1_we => iu_mm_ierat_mmucr1_we, + iu_mm_ierat_req => iu_mm_ierat_req, + iu_mm_ierat_snoop_ack => iu_mm_ierat_snoop_ack, + iu_mm_ierat_thdid => iu_mm_ierat_thdid, + iu_mm_ierat_tid => iu_mm_ierat_tid, + iu_mm_ierat_state => iu_mm_ierat_state, + iu_mm_lmq_empty => iu_mm_lmq_empty, + nclk => a2_nclk, + pc_mm_abist_dcomp_g6t_2r => pc_mm_abist_dcomp_g6t_2r_oiu, + pc_mm_abist_di_0 => pc_mm_abist_di_0_oiu, + pc_mm_abist_di_g6t_2r => pc_mm_abist_di_g6t_2r_oiu, + pc_mm_abist_ena_dc => pc_mm_abist_ena_dc_oiu, + pc_mm_abist_g6t_r_wb => pc_mm_abist_g6t_r_wb_oiu, + pc_mm_abist_g8t1p_renb_0 => pc_mm_abist_g8t1p_renb_0_oiu, + pc_mm_abist_g8t_bw_0 => pc_mm_abist_g8t_bw_0_oiu, + pc_mm_abist_g8t_bw_1 => pc_mm_abist_g8t_bw_1_oiu, + pc_mm_abist_g8t_dcomp => pc_mm_abist_g8t_dcomp_oiu, + pc_mm_abist_g8t_wenb => pc_mm_abist_g8t_wenb_oiu, + pc_mm_abist_raddr_0 => pc_mm_abist_raddr_0_oiu, + pc_mm_abist_raw_dc_b => pc_mm_abist_raw_dc_b_oiu, + pc_mm_abist_waddr_0 => pc_mm_abist_waddr_0_oiu, + pc_mm_abist_wl128_comp_ena => pc_mm_abist_wl128_comp_ena_oiu, + pc_mm_abst_sl_thold_3 => pc_mm_abst_sl_thold_3_oiu, + pc_mm_abst_slp_sl_thold_3 => pc_mm_abst_slp_sl_thold_3_oiu, + pc_mm_ary_nsl_thold_3 => pc_mm_ary_nsl_thold_3_oiu, + pc_mm_ary_slp_nsl_thold_3 => pc_mm_ary_slp_nsl_thold_3_oiu, + pc_mm_bolt_sl_thold_3 => pc_mm_bolt_sl_thold_3_oiu, + pc_mm_bo_enable_3 => pc_mm_bo_enable_3_oiu, + pc_mm_bo_reset => pc_mm_bo_reset_oiu, + pc_mm_bo_unload => pc_mm_bo_unload_oiu, + pc_mm_bo_repair => pc_mm_bo_repair_oiu, + pc_mm_bo_shdata => pc_mm_bo_shdata_oiu, + pc_mm_bo_select => pc_mm_bo_select_oiu, + pc_mm_cfg_sl_thold_3 => pc_mm_cfg_sl_thold_3_oiu, + pc_mm_cfg_slp_sl_thold_3 => pc_mm_cfg_slp_sl_thold_3_oiu, + pc_mm_debug_mux1_ctrls => pc_mm_debug_mux1_ctrls_oiu, + pc_mm_event_count_mode => pc_mm_event_count_mode_oiu, + pc_mm_event_mux_ctrls => pc_mm_event_mux_ctrls_oiu, + pc_mm_fce_3 => pc_mm_fce_3_oiu, + pc_mm_func_nsl_thold_3 => pc_mm_func_nsl_thold_3_oiu, + pc_mm_func_sl_thold_3 => pc_mm_func_sl_thold_3_oiu, + pc_mm_func_slp_nsl_thold_3 => pc_mm_func_slp_nsl_thold_3_oiu, + pc_mm_func_slp_sl_thold_3 => pc_mm_func_slp_sl_thold_3_oiu, + pc_mm_gptr_sl_thold_3 => pc_mm_gptr_sl_thold_3_oiu, + pc_mm_repr_sl_thold_3 => pc_mm_repr_sl_thold_3_oiu, + pc_mm_sg_3 => pc_mm_sg_3_oiu, + pc_mm_time_sl_thold_3 => pc_mm_time_sl_thold_3_oiu, + pc_mm_trace_bus_enable => pc_mm_trace_bus_enable_oiu, + rp_mm_event_bus_enable_q => rp_mm_event_bus_enable_q, + tc_ac_ccflush_dc => pc_mm_ccflush_dc_oiu, + tc_ac_lbist_en_dc => an_ac_lbist_en_dc, + tc_ac_scan_diag_dc => an_ac_scan_diag_dc, + tc_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b, + debug_bus_in => xu_mm_debug_data, + trace_triggers_in => xu_mm_trigger_data, + xu_ex1_flush => xu_s_ex1_flush, + xu_ex2_flush => xu_s_ex2_flush, + xu_ex3_flush => xu_s_ex3_flush, + xu_ex4_flush => xu_s_ex4_flush, + xu_ex5_flush => xu_s_ex5_flush, + mm_xu_cr0_eq => mm_xu_cr0_eq, + mm_xu_cr0_eq_valid => mm_xu_cr0_eq_valid, + xu_mm_derat_epn => xu_mm_derat_epn, + xu_mm_derat_lpid => xu_mm_derat_lpid, + xu_mm_derat_mmucr0 => xu_mm_derat_mmucr0, + xu_mm_derat_mmucr0_we => xu_mm_derat_mmucr0_we, + xu_mm_derat_mmucr1 => xu_mm_derat_mmucr1, + xu_mm_derat_mmucr1_we => xu_mm_derat_mmucr1_we, + xu_mm_derat_req => xu_mm_derat_req, + xu_mm_derat_snoop_ack => xu_mm_derat_snoop_ack, + xu_mm_derat_state => xu_mm_derat_state, + xu_mm_derat_thdid => xu_mm_derat_thdid, + xu_mm_derat_tid => xu_mm_derat_tid, + xu_mm_derat_ttype => xu_mm_derat_ttype, + xu_mm_ex2_eff_addr => xu_mm_ex2_eff_addr, + xu_mm_ex1_rs_is => xu_mm_ex1_rs_is, + xu_mm_ex4_flush => xu_mm_ex4_flush, + xu_mm_ex5_flush => xu_mm_ex5_flush, + xu_mm_ex5_perf_dtlb => xu_mm_ex5_perf_dtlb, + xu_mm_ex5_perf_itlb => xu_mm_ex5_perf_itlb, + xu_mm_hid_mmu_mode => xu_mm_hid_mmu_mode, + xu_mm_hold_ack => xu_mm_hold_ack, + xu_mm_ierat_flush => xu_mm_ierat_flush, + xu_mm_ierat_miss => xu_mm_ierat_miss, + xu_mm_lmq_stq_empty => xu_mm_lmq_stq_empty, + xu_mm_lsu_token => xu_mm_lsu_token, + xu_mm_msr_cm => xu_mm_msr_cm, + xu_mm_msr_ds => xu_mm_msr_ds, + xu_mm_msr_gs => xu_mm_msr_gs, + xu_mm_msr_is => xu_mm_msr_is, + xu_mm_msr_pr => xu_mm_msr_pr, + xu_mm_ex1_is_csync => xu_mm_ex1_is_csync, + xu_mm_ex1_is_isync => xu_mm_ex1_is_isync, + xu_mm_rf1_is_eratilx => xu_mm_rf1_is_eratilx, + xu_mm_rf1_is_erativax => xu_mm_rf1_is_erativax, + xu_mm_rf1_is_tlbilx => xu_mm_rf1_is_tlbilx, + xu_mm_rf1_is_tlbivax => xu_mm_rf1_is_tlbivax, + xu_mm_rf1_is_tlbre => xu_mm_rf1_is_tlbre, + xu_mm_rf1_is_tlbsx => xu_mm_rf1_is_tlbsx, + xu_mm_rf1_is_tlbsxr => xu_mm_rf1_is_tlbsxr, + xu_mm_rf1_is_tlbsrx => xu_mm_rf1_is_tlbsrx, + xu_mm_rf1_is_tlbwe => xu_mm_rf1_is_tlbwe, + xu_mm_rf1_val => xu_mm_rf1_val, + xu_mm_rf1_t => xu_mm_rf1_t, + xu_mm_spr_epcr_dgtmi => xu_mm_spr_epcr_dgtmi, + xu_mm_spr_epcr_dmiuh => xu_mm_spr_epcr_dmiuh, + slowspr_addr_in => xu_mm_slowspr_addr, + slowspr_data_in => xu_mm_slowspr_data, + slowspr_done_in => xu_mm_slowspr_done, + slowspr_etid_in => xu_mm_slowspr_etid, + slowspr_rw_in => xu_mm_slowspr_rw, + slowspr_val_in => xu_mm_slowspr_val, + xu_rf1_flush => xu_s_rf1_flush, + bcfg_scan_out => mm_rp_bcfg_scan_out, + ccfg_scan_out => mm_iu_ccfg_scan_out, + dcfg_scan_out => mm_rp_dcfg_scan_out, + ac_an_gptr_scan_out => ac_an_gptr_scan_out, + ac_an_repr_scan_out => ac_an_repr_scan_out, + ac_an_time_scan_out => ac_an_time_scan_out, + ac_an_back_inv_reject => ac_an_back_inv_reject, + ac_an_lpar_id => ac_an_lpar_id, + mm_iu_barrier_done => mm_iu_barrier_done, + mm_iu_ierat_mmucr0_0 => mm_iu_ierat_mmucr0_0, + mm_iu_ierat_mmucr0_1 => mm_iu_ierat_mmucr0_1, + mm_iu_ierat_mmucr0_2 => mm_iu_ierat_mmucr0_2, + mm_iu_ierat_mmucr0_3 => mm_iu_ierat_mmucr0_3, + mm_iu_ierat_mmucr1 => mm_iu_ierat_mmucr1, + mm_iu_ierat_pid0 => mm_iu_ierat_pid0, + mm_iu_ierat_pid1 => mm_iu_ierat_pid1, + mm_iu_ierat_pid2 => mm_iu_ierat_pid2, + mm_iu_ierat_pid3 => mm_iu_ierat_pid3, + mm_iu_ierat_rel_data => mm_iu_ierat_rel_data, + mm_iu_ierat_rel_val => mm_iu_ierat_rel_val, + mm_iu_ierat_snoop_attr => mm_iu_ierat_snoop_attr, + mm_iu_ierat_snoop_coming => mm_iu_ierat_snoop_coming, + mm_iu_ierat_snoop_val => mm_iu_ierat_snoop_val, + mm_iu_ierat_snoop_vpn => mm_iu_ierat_snoop_vpn, + slowspr_addr_out => mm_iu_slowspr_addr, + slowspr_data_out => mm_iu_slowspr_data, + slowspr_done_out => mm_iu_slowspr_done, + slowspr_etid_out => mm_iu_slowspr_etid, + slowspr_rw_out => mm_iu_slowspr_rw, + slowspr_val_out => mm_iu_slowspr_val, + debug_bus_out => ac_an_debug_bus_int, + trace_triggers_out => ac_an_trace_triggers, + mm_pc_bo_diagout => mm_pc_bo_diagout_iiu, + mm_pc_bo_fail => mm_pc_bo_fail_iiu, + mm_pc_event_data => mm_pc_event_data_iiu, + mm_xu_derat_mmucr0_0 => mm_xu_derat_mmucr0_0, + mm_xu_derat_mmucr0_1 => mm_xu_derat_mmucr0_1, + mm_xu_derat_mmucr0_2 => mm_xu_derat_mmucr0_2, + mm_xu_derat_mmucr0_3 => mm_xu_derat_mmucr0_3, + mm_xu_derat_mmucr1 => mm_xu_derat_mmucr1, + mm_xu_derat_pid0 => mm_xu_derat_pid0, + mm_xu_derat_pid1 => mm_xu_derat_pid1, + mm_xu_derat_pid2 => mm_xu_derat_pid2, + mm_xu_derat_pid3 => mm_xu_derat_pid3, + mm_xu_derat_rel_data => mm_xu_derat_rel_data, + mm_xu_derat_rel_val => mm_xu_derat_rel_val, + mm_xu_derat_snoop_attr => mm_xu_derat_snoop_attr, + mm_xu_derat_snoop_coming => mm_xu_derat_snoop_coming, + mm_xu_derat_snoop_val => mm_xu_derat_snoop_val, + mm_xu_derat_snoop_vpn => mm_xu_derat_snoop_vpn, + mm_xu_eratmiss_done => mm_xu_eratmiss_done, + mm_xu_esr_pt => mm_xu_esr_pt, + mm_xu_esr_data => mm_xu_esr_data, + mm_xu_esr_epid => mm_xu_esr_epid, + mm_xu_esr_st => mm_xu_esr_st, + mm_xu_ex3_flush_req => mm_xu_ex3_flush_req, + mm_xu_hold_done => mm_xu_hold_done, + mm_xu_hold_req => mm_xu_hold_req, + mm_xu_hv_priv => mm_xu_hv_priv, + mm_xu_illeg_instr => mm_xu_illeg_instr, + mm_xu_local_snoop_reject => mm_xu_local_snoop_reject, + mm_xu_lrat_miss => mm_xu_lrat_miss, + mm_xu_lsu_addr => mm_xu_lsu_addr, + mm_xu_lsu_lpid => mm_xu_lsu_lpid, + mm_xu_lsu_lpidr => mm_xu_lsu_lpidr, + mm_xu_lsu_gs => mm_xu_lsu_gs, + mm_xu_lsu_ind => mm_xu_lsu_ind, + mm_xu_lsu_lbit => mm_xu_lsu_lbit, + mm_xu_lsu_req => mm_xu_lsu_req, + mm_xu_lsu_ttype => mm_xu_lsu_ttype, + mm_xu_lsu_u => mm_xu_lsu_u, + mm_xu_lsu_wimge => mm_xu_lsu_wimge, + mm_xu_pt_fault => mm_xu_pt_fault, + mm_xu_quiesce => mm_xu_quiesce, + mm_xu_tlb_inelig => mm_xu_tlb_inelig, + mm_xu_tlb_miss => mm_xu_tlb_miss, + mm_xu_tlb_multihit_err => mm_xu_tlb_multihit_err, + mm_xu_tlb_par_err => mm_xu_tlb_par_err, + mm_xu_lru_par_err => mm_xu_lru_par_err, + + an_ac_reld_data_coming => an_ac_reld_data_coming, + an_ac_reld_l1_dump => an_ac_reld_l1_dump, + an_ac_grffence_en_dc => an_ac_camfence_en_dc, + an_ac_stcx_complete => an_ac_stcx_complete, + an_ac_abist_mode_dc => an_ac_abist_mode_dc, + an_ac_abist_start_test => an_ac_abist_start_test, + an_ac_atpg_en_dc => an_ac_atpg_en_dc, + an_ac_ccflush_dc => an_ac_ccflush_dc, + an_ac_reset_1_complete => an_ac_reset_1_complete, + an_ac_reset_2_complete => an_ac_reset_2_complete, + an_ac_reset_3_complete => an_ac_reset_3_complete, + an_ac_reset_wd_complete => an_ac_reset_wd_complete, + an_ac_debug_stop => an_ac_debug_stop, + an_ac_lbist_en_dc => an_ac_lbist_en_dc, + an_ac_pm_thread_stop => an_ac_pm_thread_stop, + an_ac_regf_scan_in => an_ac_regf_scan_in, + an_ac_scan_diag_dc => an_ac_scan_diag_dc, + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b, + an_ac_scom_cch => an_ac_scom_cch, + an_ac_scom_dch => an_ac_scom_dch, + an_ac_checkstop => an_ac_checkstop, + an_ac_back_inv_omm => an_ac_back_inv_omm, + an_ac_back_inv_addr_omm => an_ac_back_inv_addr_omm, + an_ac_back_inv_target_omm_iua => an_ac_back_inv_target_omm_iua, + an_ac_back_inv_target_omm_iub => an_ac_back_inv_target_omm_iub, + an_ac_reld_core_tag_omm => an_ac_reld_core_tag_omm, + an_ac_reld_data_omm => an_ac_reld_data_omm, + an_ac_reld_data_vld_omm => an_ac_reld_data_vld_omm, + an_ac_reld_ecc_err_omm => an_ac_reld_ecc_err_omm, + an_ac_reld_ecc_err_ue_omm => an_ac_reld_ecc_err_ue_omm, + an_ac_reld_qw_omm => an_ac_reld_qw_omm, + an_ac_reld_ditc_omm => an_ac_reld_ditc_omm, + an_ac_reld_crit_qw_omm => an_ac_reld_crit_qw_omm, + an_ac_reld_data_coming_omm => an_ac_reld_data_coming_omm, + an_ac_reld_l1_dump_omm => an_ac_reld_l1_dump_omm, + an_ac_grffence_en_dc_omm => an_ac_camfence_en_dc_omm, + an_ac_stcx_complete_omm => an_ac_stcx_complete_omm, + an_ac_abist_mode_dc_omm => an_ac_abist_mode_dc_omm, + an_ac_abist_start_test_omm => an_ac_abist_start_test_omm, + an_ac_abst_scan_in_omm_iu => an_ac_abst_scan_in_omm_iu, + an_ac_abst_scan_in_omm_xu => an_ac_abst_scan_in_omm_xu, + an_ac_atpg_en_dc_omm => an_ac_atpg_en_dc_omm, + an_ac_bcfg_scan_in_omm_bit1 => an_ac_bcfg_scan_in_omm_bit1, + an_ac_bcfg_scan_in_omm_bit3 => an_ac_bcfg_scan_in_omm_bit3, + an_ac_bcfg_scan_in_omm_bit4 => an_ac_bcfg_scan_in_omm_bit4, + an_ac_lbist_ary_wrt_thru_dc_omm => an_ac_lbist_ary_wrt_thru_dc_omm, + an_ac_ccflush_dc_omm => an_ac_ccflush_dc_omm, + an_ac_reset_1_complete_omm => an_ac_reset_1_complete_omm, + an_ac_reset_2_complete_omm => an_ac_reset_2_complete_omm, + an_ac_reset_3_complete_omm => an_ac_reset_3_complete_omm, + an_ac_reset_wd_complete_omm => an_ac_reset_wd_complete_omm, + an_ac_dcfg_scan_in_omm => an_ac_dcfg_scan_in_omm, + an_ac_debug_stop_omm => an_ac_debug_stop_omm, + an_ac_func_scan_in_omm_iua => an_ac_func_scan_in_omm_iua, + an_ac_func_scan_in_omm_iub => an_ac_func_scan_in_omm_iub, + an_ac_func_scan_in_omm_xu => an_ac_func_scan_in_omm_xu, + an_ac_lbist_en_dc_omm => an_ac_lbist_en_dc_omm, + an_ac_pm_thread_stop_omm => an_ac_pm_thread_stop_omm, + an_ac_regf_scan_in_omm => an_ac_regf_scan_in_omm, + an_ac_scan_diag_dc_omm => an_ac_scan_diag_dc_omm, + an_ac_scan_dis_dc_b_omm => an_ac_scan_dis_dc_b_omm, + an_ac_scom_cch_omm => an_ac_scom_cch_omm, + an_ac_scom_dch_omm => an_ac_scom_dch_omm, + an_ac_checkstop_omm => an_ac_checkstop_omm, + ac_an_abst_scan_out_imm_iu => ac_an_abst_scan_out_imm_iu, + ac_an_abst_scan_out_imm_xu => ac_an_abst_scan_out_imm_xu, + ac_an_bcfg_scan_out_imm => ac_an_bcfg_scan_out_imm, + ac_an_dcfg_scan_out_imm => ac_an_dcfg_scan_out_imm, + ac_an_func_scan_out_imm_iua => ac_an_func_scan_out_imm_iua, + ac_an_func_scan_out_imm_iub => ac_an_func_scan_out_imm_iub, + ac_an_func_scan_out_imm_xu => ac_an_func_scan_out_imm_xu, + ac_an_reld_ditc_pop_imm => ac_an_reld_ditc_pop_imm, + ac_an_power_managed_imm => ac_an_power_managed_imm, + ac_an_rvwinkle_mode_imm => ac_an_rvwinkle_mode_imm, + ac_an_fu_bypass_events_imm => ac_an_fu_bypass_events_imm, + ac_an_iu_bypass_events_imm => ac_an_iu_bypass_events_imm, + ac_an_mm_bypass_events_imm => ac_an_mm_bypass_events_imm, + ac_an_lsu_bypass_events_imm => ac_an_lsu_bypass_events_imm, + ac_an_event_bus_imm => ac_an_event_bus_imm, + ac_an_pm_thread_running_imm => ac_an_pm_thread_running_imm, + ac_an_recov_err_imm => ac_an_recov_err_imm, + ac_an_regf_scan_out_imm => ac_an_regf_scan_out_imm, + ac_an_scom_cch_imm => ac_an_scom_cch_imm, + ac_an_scom_dch_imm => ac_an_scom_dch_imm, + ac_an_special_attn_imm => ac_an_special_attn_imm, + ac_an_checkstop_imm => ac_an_checkstop_imm, + ac_an_local_checkstop_imm => ac_an_local_checkstop_imm, + ac_an_trace_error_imm => ac_an_trace_error_imm, + ac_an_abst_scan_out => ac_an_abst_scan_out, + ac_an_bcfg_scan_out => ac_an_bcfg_scan_out, + ac_an_dcfg_scan_out => ac_an_dcfg_scan_out, + ac_an_func_scan_out => ac_an_func_scan_out, + ac_an_reld_ditc_pop => ac_an_reld_ditc_pop, + ac_an_power_managed => ac_an_power_managed, + ac_an_rvwinkle_mode => ac_an_rvwinkle_mode, + ac_an_fu_bypass_events => ac_an_fu_bypass_events, + ac_an_iu_bypass_events => ac_an_iu_bypass_events, + ac_an_mm_bypass_events => ac_an_mm_bypass_events, + ac_an_lsu_bypass_events => ac_an_lsu_bypass_events, + ac_an_event_bus => ac_an_event_bus, + ac_an_pm_thread_running => ac_an_pm_thread_running, + ac_an_recov_err => ac_an_recov_err, + ac_an_regf_scan_out => ac_an_regf_scan_out, + ac_an_scom_cch => ac_an_scom_cch, + ac_an_scom_dch => ac_an_scom_dch, + ac_an_special_attn => ac_an_special_attn, + ac_an_checkstop => ac_an_checkstop, + ac_an_local_checkstop => ac_an_local_checkstop, + ac_an_trace_error => ac_an_trace_error, + an_ac_dcr_act => an_ac_dcr_act, + an_ac_dcr_val => an_ac_dcr_val, + an_ac_dcr_read => an_ac_dcr_read, + an_ac_dcr_etid => an_ac_dcr_etid, + an_ac_dcr_data => an_ac_dcr_data, + an_ac_dcr_done => an_ac_dcr_done, + an_ac_crit_interrupt => an_ac_crit_interrupt, + an_ac_ext_interrupt => an_ac_ext_interrupt, + an_ac_flh2l2_gate => an_ac_flh2l2_gate, + an_ac_icbi_ack => an_ac_icbi_ack, + an_ac_icbi_ack_thread => an_ac_icbi_ack_thread, + an_ac_req_ld_pop => an_ac_req_ld_pop, + an_ac_req_spare_ctrl_a1 => an_ac_req_spare_ctrl_a1, + an_ac_req_st_gather => an_ac_req_st_gather, + an_ac_req_st_pop => an_ac_req_st_pop, + an_ac_req_st_pop_thrd => an_ac_req_st_pop_thrd, + an_ac_reservation_vld => an_ac_reservation_vld, + an_ac_sleep_en => an_ac_sleep_en, + an_ac_stcx_pass => an_ac_stcx_pass, + an_ac_sync_ack => an_ac_sync_ack, + an_ac_ary_nsl_thold_7 => an_ac_ary_nsl_thold_7, + an_ac_ccenable_dc => an_ac_ccenable_dc, + an_ac_coreid => an_ac_coreid, + an_ac_external_mchk => an_ac_external_mchk, + an_ac_fce_7 => an_ac_fce_7, + an_ac_func_nsl_thold_7 => an_ac_func_nsl_thold_7, + an_ac_func_sl_thold_7 => an_ac_func_sl_thold_7, + an_ac_gsd_test_enable_dc => an_ac_gsd_test_enable_dc, + an_ac_gsd_test_acmode_dc => an_ac_gsd_test_acmode_dc, + an_ac_gptr_scan_in => an_ac_gptr_scan_in, + an_ac_hang_pulse => an_ac_hang_pulse, + an_ac_lbist_ac_mode_dc => an_ac_lbist_ac_mode_dc, + an_ac_lbist_ip_dc => an_ac_lbist_ip_dc, + an_ac_malf_alert => an_ac_malf_alert, + an_ac_perf_interrupt => an_ac_perf_interrupt, + an_ac_psro_enable_dc => an_ac_psro_enable_dc, + an_ac_repr_scan_in => an_ac_repr_scan_in, + an_ac_rtim_sl_thold_7 => an_ac_rtim_sl_thold_7, + an_ac_scan_type_dc => an_ac_scan_type_dc, + an_ac_scom_sat_id => an_ac_scom_sat_id, + an_ac_sg_7 => an_ac_sg_7, + an_ac_tb_update_enable => an_ac_tb_update_enable, + an_ac_tb_update_pulse => an_ac_tb_update_pulse, + an_ac_time_scan_in => an_ac_time_scan_in, + an_ac_crit_interrupt_omm => an_ac_crit_interrupt_omm, + an_ac_ext_interrupt_omm => an_ac_ext_interrupt_omm, + an_ac_flh2l2_gate_omm => an_ac_flh2l2_gate_omm, + an_ac_icbi_ack_omm => an_ac_icbi_ack_omm, + an_ac_icbi_ack_thread_omm => an_ac_icbi_ack_thread_omm, + an_ac_req_ld_pop_omm => an_ac_req_ld_pop_omm, + an_ac_req_spare_ctrl_a1_omm => an_ac_req_spare_ctrl_a1_omm, + an_ac_req_st_gather_omm => an_ac_req_st_gather_omm, + an_ac_req_st_pop_omm => an_ac_req_st_pop_omm, + an_ac_req_st_pop_thrd_omm => an_ac_req_st_pop_thrd_omm, + an_ac_reservation_vld_omm => an_ac_reservation_vld_omm, + an_ac_sleep_en_omm => an_ac_sleep_en_omm, + an_ac_stcx_pass_omm => an_ac_stcx_pass_omm, + an_ac_sync_ack_omm => an_ac_sync_ack_omm, + an_ac_ary_nsl_thold_7_omm => an_ac_ary_nsl_thold_7_omm, + an_ac_ccenable_dc_omm => an_ac_ccenable_dc_iiu, + an_ac_coreid_omm => an_ac_coreid_omm, + an_ac_external_mchk_omm => an_ac_external_mchk_omm, + an_ac_fce_7_omm => an_ac_fce_7_omm, + an_ac_func_nsl_thold_7_omm => an_ac_func_nsl_thold_7_omm, + an_ac_func_sl_thold_7_omm => an_ac_func_sl_thold_7_omm, + an_ac_gsd_test_enable_dc_omm => an_ac_gsd_test_enable_dc_omm, + an_ac_gsd_test_acmode_dc_omm => an_ac_gsd_test_acmode_dc_omm, + an_ac_gptr_scan_in_omm => an_ac_gptr_scan_in_omm, + an_ac_hang_pulse_omm => an_ac_hang_pulse_omm, + an_ac_lbist_ac_mode_dc_omm => an_ac_lbist_ac_mode_dc_omm, + an_ac_lbist_ip_dc_omm => an_ac_lbist_ip_dc_omm, + an_ac_malf_alert_omm => an_ac_malf_alert_omm, + an_ac_perf_interrupt_omm => an_ac_perf_interrupt_omm, + an_ac_psro_enable_dc_omm => an_ac_psro_enable_dc_omm, + an_ac_repr_scan_in_omm => an_ac_repr_scan_in_omm, + an_ac_rtim_sl_thold_7_omm => an_ac_rtim_sl_thold_7_omm, + an_ac_scan_type_dc_omm => an_ac_scan_type_dc_omm, + an_ac_scom_sat_id_omm => an_ac_scom_sat_id_omm, + an_ac_sg_7_omm => an_ac_sg_7_omm, + an_ac_tb_update_enable_omm => an_ac_tb_update_enable_omm, + an_ac_tb_update_pulse_omm => an_ac_tb_update_pulse_omm, + an_ac_time_scan_in_omm => an_ac_time_scan_in_omm, + + ac_an_box_empty_imm => ac_an_box_empty_imm, + ac_an_machine_check_imm => ac_an_machine_check_imm, + ac_an_req_imm => ac_an_req_imm, + ac_an_req_endian_imm => ac_an_req_endian_imm, + ac_an_req_ld_core_tag_imm => ac_an_req_ld_core_tag_imm, + ac_an_req_ld_xfr_len_imm => ac_an_req_ld_xfr_len_imm, + ac_an_req_pwr_token_imm => ac_an_req_pwr_token_imm, + ac_an_req_ra_imm => ac_an_req_ra_imm, + ac_an_req_spare_ctrl_a0_imm => ac_an_req_spare_ctrl_a0_imm, + ac_an_req_thread_imm => ac_an_req_thread_imm, + ac_an_req_ttype_imm => ac_an_req_ttype_imm, + ac_an_req_user_defined_imm => ac_an_req_user_defined_imm, + ac_an_req_wimg_g_imm => ac_an_req_wimg_g_imm, + ac_an_req_wimg_i_imm => ac_an_req_wimg_i_imm, + ac_an_req_wimg_m_imm => ac_an_req_wimg_m_imm, + ac_an_req_wimg_w_imm => ac_an_req_wimg_w_imm, + ac_an_st_byte_enbl_imm => ac_an_st_byte_enbl_imm, + ac_an_st_data_imm => ac_an_st_data_imm, + ac_an_st_data_pwr_token_imm => ac_an_st_data_pwr_token_imm, + ac_an_abist_done_dc_imm => ac_an_abist_done_dc_oiu, + ac_an_debug_trigger_imm => ac_an_debug_trigger_imm, + ac_an_psro_ringsig_imm => ac_an_psro_ringsig_oiu, + ac_an_reset_1_request_imm => ac_an_reset_1_request_imm, + ac_an_reset_2_request_imm => ac_an_reset_2_request_imm, + ac_an_reset_3_request_imm => ac_an_reset_3_request_imm, + ac_an_reset_wd_request_imm => ac_an_reset_wd_request_imm, + + ac_an_box_empty => ac_an_box_empty, + ac_an_machine_check => ac_an_machine_check, + ac_an_req => ac_an_req, + ac_an_req_endian => ac_an_req_endian, + ac_an_req_ld_core_tag => ac_an_req_ld_core_tag, + ac_an_req_ld_xfr_len => ac_an_req_ld_xfr_len, + ac_an_req_pwr_token => ac_an_req_pwr_token, + ac_an_req_ra => ac_an_req_ra, + ac_an_req_spare_ctrl_a0 => ac_an_req_spare_ctrl_a0, + ac_an_req_thread => ac_an_req_thread, + ac_an_req_ttype => ac_an_req_ttype, + ac_an_req_user_defined => ac_an_req_user_defined, + ac_an_req_wimg_g => ac_an_req_wimg_g, + ac_an_req_wimg_i => ac_an_req_wimg_i, + ac_an_req_wimg_m => ac_an_req_wimg_m, + ac_an_req_wimg_w => ac_an_req_wimg_w, + ac_an_st_byte_enbl => ac_an_st_byte_enbl, + ac_an_st_data => ac_an_st_data, + ac_an_st_data_pwr_token => ac_an_st_data_pwr_token, + ac_an_abist_done_dc => ac_an_abist_done_dc, + ac_an_debug_trigger => ac_an_debug_trigger, + ac_an_psro_ringsig => ac_an_psro_ringsig, + ac_an_reset_1_request => ac_an_reset_1_request, + ac_an_reset_2_request => ac_an_reset_2_request, + ac_an_reset_3_request => ac_an_reset_3_request, + ac_an_reset_wd_request => ac_an_reset_wd_request, + ac_an_dcr_act => ac_an_dcr_act, + ac_an_dcr_val => ac_an_dcr_val, + ac_an_dcr_read => ac_an_dcr_read, + ac_an_dcr_user => ac_an_dcr_user, + ac_an_dcr_etid => ac_an_dcr_etid, + ac_an_dcr_addr => ac_an_dcr_addr, + ac_an_dcr_data => ac_an_dcr_data, + + debug_bus_out_int => debug_bus_out_int, + + bg_ac_an_func_scan_ns_imm => bg_ac_an_func_scan_ns_q, + bg_ac_an_abst_scan_ns_imm => bg_ac_an_abst_scan_ns_q, + bg_ac_an_func_scan_ns => bg_ac_an_func_scan_ns, + bg_ac_an_abst_scan_ns => bg_ac_an_abst_scan_ns, + bg_pc_l1p_abist_di_0_imm => bg_pc_l1p_abist_di_0_q, + bg_pc_l1p_abist_g8t1p_renb_0_imm => bg_pc_l1p_abist_g8t1p_renb_0_q, + bg_pc_l1p_abist_g8t_bw_0_imm => bg_pc_l1p_abist_g8t_bw_0_q, + bg_pc_l1p_abist_g8t_bw_1_imm => bg_pc_l1p_abist_g8t_bw_1_q, + bg_pc_l1p_abist_g8t_dcomp_imm => bg_pc_l1p_abist_g8t_dcomp_q, + bg_pc_l1p_abist_g8t_wenb_imm => bg_pc_l1p_abist_g8t_wenb_q, + bg_pc_l1p_abist_raddr_0_imm => bg_pc_l1p_abist_raddr_0_q, + bg_pc_l1p_abist_waddr_0_imm => bg_pc_l1p_abist_waddr_0_q, + bg_pc_l1p_abist_wl128_comp_ena_imm => bg_pc_l1p_abist_wl128_comp_ena_q, + bg_pc_l1p_abist_wl32_comp_ena_imm => bg_pc_l1p_abist_wl32_comp_ena_q, + bg_pc_l1p_abist_di_0 => bg_pc_l1p_abist_di_0, + bg_pc_l1p_abist_g8t1p_renb_0 => bg_pc_l1p_abist_g8t1p_renb_0, + bg_pc_l1p_abist_g8t_bw_0 => bg_pc_l1p_abist_g8t_bw_0, + bg_pc_l1p_abist_g8t_bw_1 => bg_pc_l1p_abist_g8t_bw_1, + bg_pc_l1p_abist_g8t_dcomp => bg_pc_l1p_abist_g8t_dcomp, + bg_pc_l1p_abist_g8t_wenb => bg_pc_l1p_abist_g8t_wenb, + bg_pc_l1p_abist_raddr_0 => bg_pc_l1p_abist_raddr_0, + bg_pc_l1p_abist_waddr_0 => bg_pc_l1p_abist_waddr_0, + bg_pc_l1p_abist_wl128_comp_ena => bg_pc_l1p_abist_wl128_comp_ena, + bg_pc_l1p_abist_wl32_comp_ena => bg_pc_l1p_abist_wl32_comp_ena, + bg_pc_l1p_gptr_sl_thold_2_imm => bg_pc_l1p_gptr_sl_thold_2_imm, + bg_pc_l1p_time_sl_thold_2_imm => bg_pc_l1p_time_sl_thold_2_imm, + bg_pc_l1p_repr_sl_thold_2_imm => bg_pc_l1p_repr_sl_thold_2_imm, + bg_pc_l1p_abst_sl_thold_2_imm => bg_pc_l1p_abst_sl_thold_2_imm, + bg_pc_l1p_func_sl_thold_2_imm => bg_pc_l1p_func_sl_thold_2_imm, + bg_pc_l1p_func_slp_sl_thold_2_imm => bg_pc_l1p_func_slp_sl_thold_2_imm, + bg_pc_l1p_bolt_sl_thold_2_imm => bg_pc_l1p_bolt_sl_thold_2_imm, + bg_pc_l1p_ary_nsl_thold_2_imm => bg_pc_l1p_ary_nsl_thold_2_imm, + bg_pc_l1p_sg_2_imm => bg_pc_l1p_sg_2_imm, + bg_pc_l1p_fce_2_imm => bg_pc_l1p_fce_2_imm, + bg_pc_l1p_bo_enable_2_imm => bg_pc_l1p_bo_enable_2_imm, + bg_pc_l1p_gptr_sl_thold_2 => bg_pc_l1p_gptr_sl_thold_2, + bg_pc_l1p_time_sl_thold_2 => bg_pc_l1p_time_sl_thold_2, + bg_pc_l1p_repr_sl_thold_2 => bg_pc_l1p_repr_sl_thold_2, + bg_pc_l1p_abst_sl_thold_2 => bg_pc_l1p_abst_sl_thold_2, + bg_pc_l1p_func_sl_thold_2 => bg_pc_l1p_func_sl_thold_2, + bg_pc_l1p_func_slp_sl_thold_2 => bg_pc_l1p_func_slp_sl_thold_2, + bg_pc_l1p_bolt_sl_thold_2 => bg_pc_l1p_bolt_sl_thold_2, + bg_pc_l1p_ary_nsl_thold_2 => bg_pc_l1p_ary_nsl_thold_2, + bg_pc_l1p_sg_2 => bg_pc_l1p_sg_2, + bg_pc_l1p_fce_2 => bg_pc_l1p_fce_2, + bg_pc_l1p_bo_enable_2 => bg_pc_l1p_bo_enable_2, + bg_pc_bo_unload_imm => bg_pc_bo_unload_oiu, + bg_pc_bo_load_imm => bg_pc_bo_load_oiu, + bg_pc_bo_repair_imm => bg_pc_bo_repair_oiu, + bg_pc_bo_reset_imm => bg_pc_bo_reset_oiu, + bg_pc_bo_shdata_imm => bg_pc_bo_shdata_oiu, + bg_pc_bo_select_imm => bg_pc_bo_select_oiu, + bg_pc_l1p_ccflush_dc_imm => bg_pc_l1p_ccflush_dc_oiu, + bg_pc_l1p_abist_ena_dc_imm => bg_pc_l1p_abist_ena_dc_oiu, + bg_pc_l1p_abist_raw_dc_b_imm => bg_pc_l1p_abist_raw_dc_b_oiu, + bg_pc_bo_unload => bg_pc_bo_unload, + bg_pc_bo_load => bg_pc_bo_load, + bg_pc_bo_repair => bg_pc_bo_repair, + bg_pc_bo_reset => bg_pc_bo_reset, + bg_pc_bo_shdata => bg_pc_bo_shdata, + bg_pc_bo_select => bg_pc_bo_select, + bg_pc_l1p_ccflush_dc => bg_pc_l1p_ccflush_dc, + bg_pc_l1p_abist_ena_dc => bg_pc_l1p_abist_ena_dc, + bg_pc_l1p_abist_raw_dc_b => bg_pc_l1p_abist_raw_dc_b, + bg_an_ac_func_scan_sn => bg_an_ac_func_scan_sn, + bg_an_ac_abst_scan_sn => bg_an_ac_abst_scan_sn, + bg_an_ac_func_scan_sn_omm => bg_an_ac_func_scan_sn_omm, + bg_an_ac_abst_scan_sn_omm => bg_an_ac_abst_scan_sn_omm, + bg_pc_bo_fail => bg_pc_bo_fail, + bg_pc_bo_diagout => bg_pc_bo_diagout, + bg_pc_bo_fail_omm => bg_pc_bo_fail_omm, + bg_pc_bo_diagout_omm => bg_pc_bo_diagout_omm, + xu_mm_xucr4_mmu_mchk => xu_mm_xucr4_mmu_mchk, + + gnd => gnd, + vcs => vcs, + vdd => vdd + ); + +a_pcq: entity work.pcq + generic map(expand_type => expand_type, regmode => regmode) + port map ( + abst_scan_in => iu_pc_abst_scan_out, + bcfg_scan_in => rp_pc_bcfg_scan_out_q, + ccfg_scan_in => iu_pc_ccfg_scan_out, + dcfg_scan_in => rp_pc_dcfg_scan_out_q, + func_scan_in => rp_pc_func_scan_in_q(0 to 1), + gptr_scan_in => iu_pc_gptr_scan_out, + bx_pc_err_inbox_ue => bx_pc_err_inbox_ue_ofu, + bx_pc_err_outbox_ue => bx_pc_err_outbox_ue_ofu, + fu_pc_event_data => fu_pc_event_data, + fu_pc_ram_data => fu_pc_ram_data, + fu_pc_ram_done => fu_pc_ram_done, + iu_pc_err_icache_parity => iu_pc_err_icache_parity, + iu_pc_err_icachedir_multihit => iu_pc_err_icachedir_multihit, + iu_pc_err_icachedir_parity => iu_pc_err_icachedir_parity, + fu_pc_err_regfile_parity => fu_pc_err_regfile_parity, + fu_pc_err_regfile_ue => fu_pc_err_regfile_ue, + iu_pc_err_ucode_illegal => iu_pc_err_ucode_illegal, + iu_pc_event_data => iu_pc_event_data, + slowspr_addr_in => iu_pc_slowspr_addr, + slowspr_data_in => iu_pc_slowspr_data, + slowspr_done_in => iu_pc_slowspr_done, + slowspr_etid_in => iu_pc_slowspr_etid, + slowspr_rw_in => iu_pc_slowspr_rw, + slowspr_val_in => iu_pc_slowspr_val, + xu_pc_err_mcsr_summary => xu_pc_err_mcsr_summary_ofu, + xu_pc_err_ierat_parity => xu_pc_err_ierat_parity_ofu, + xu_pc_err_derat_parity => xu_pc_err_derat_parity_ofu, + xu_pc_err_tlb_parity => xu_pc_err_tlb_parity_ofu, + xu_pc_err_tlb_lru_parity => xu_pc_err_tlb_lru_parity_ofu, + xu_pc_err_ierat_multihit => xu_pc_err_ierat_multihit_ofu, + xu_pc_err_derat_multihit => xu_pc_err_derat_multihit_ofu, + xu_pc_err_tlb_multihit => xu_pc_err_tlb_multihit_ofu, + xu_pc_err_ext_mchk => xu_pc_err_ext_mchk_ofu, + xu_pc_err_ditc_overrun => xu_pc_err_ditc_overrun_ofu, + xu_pc_err_local_snoop_reject => xu_pc_err_local_snoop_reject_ofu, + mm_pc_event_data => mm_pc_event_data_oiu, + nclk => a2_nclk, + an_ac_rtim_sl_thold_6 => rp_pc_rtim_sl_thold_6, + an_ac_func_sl_thold_6 => rp_pc_func_sl_thold_6, + an_ac_func_nsl_thold_6 => rp_pc_func_nsl_thold_6, + an_ac_ary_nsl_thold_6 => rp_pc_ary_nsl_thold_6, + an_ac_sg_6 => rp_pc_sg_6, + an_ac_fce_6 => rp_pc_fce_6, + an_ac_abist_start_test => rp_pc_abist_start_test_q, + an_ac_ccenable_dc => an_ac_ccenable_dc_oiu, + an_ac_ccflush_dc => an_ac_ccflush_dc_oiu, + an_ac_debug_stop => rp_pc_debug_stop_q, + an_ac_gsd_test_enable_dc => an_ac_gsd_test_enable_dc_oiu, + an_ac_gsd_test_acmode_dc => an_ac_gsd_test_acmode_dc_oiu, + an_ac_lbist_en_dc => an_ac_lbist_en_dc_oiu, + an_ac_lbist_ip_dc => an_ac_lbist_ip_dc_oiu, + an_ac_lbist_ac_mode_dc => an_ac_lbist_ac_mode_dc_oiu, + an_ac_abist_mode_dc => an_ac_abist_mode_dc_oiu, + an_ac_malf_alert => an_ac_malf_alert_oiu, + an_ac_pm_thread_stop => rp_pc_pm_thread_stop_q, + an_ac_psro_enable_dc => an_ac_psro_enable_dc_oiu, + an_ac_reset_1_complete => rp_pc_reset_1_complete_q, + an_ac_reset_2_complete => rp_pc_reset_2_complete_q, + an_ac_reset_3_complete => rp_pc_reset_3_complete_q, + an_ac_reset_wd_complete => rp_pc_reset_wd_complete_q, + an_ac_scan_diag_dc => an_ac_scan_diag_dc_oiu, + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b_oiu, + an_ac_scan_type_dc => an_ac_scan_type_dc_oiu, + an_ac_scom_cch => rp_pc_scom_cch_q, + an_ac_scom_dch => rp_pc_scom_dch_q, + an_ac_scom_sat_id => an_ac_scom_sat_id_oiu, + an_ac_checkstop => rp_pc_checkstop_q, + debug_bus_in => fu_pc_debug_data, + trace_triggers_in => fu_pc_trigger_data, + xu_pc_err_attention_instr => xu_pc_err_attention_instr_ofu, + xu_pc_err_dcache_parity => xu_pc_err_dcache_parity_ofu, + xu_pc_err_dcachedir_parity => xu_pc_err_dcachedir_parity_ofu, + xu_pc_err_dcachedir_multihit => xu_pc_err_dcachedir_multihit_ofu, + xu_pc_err_debug_event => xu_pc_err_debug_event_ofu, + bx_pc_err_inbox_ecc => bx_pc_err_inbox_ecc_ofu, + xu_pc_err_invld_reld => xu_pc_err_invld_reld_ofu, + xu_pc_err_l2intrf_ecc => xu_pc_err_l2intrf_ecc_ofu, + xu_pc_err_l2intrf_ue => xu_pc_err_l2intrf_ue_ofu, + xu_pc_err_l2credit_overrun => xu_pc_err_l2credit_overrun_ofu, + xu_pc_err_llbust_attempt => xu_pc_err_llbust_attempt_ofu, + xu_pc_err_llbust_failed => xu_pc_err_llbust_failed_ofu, + xu_pc_err_nia_miscmpr => xu_pc_err_nia_miscmpr_ofu, + bx_pc_err_outbox_ecc => bx_pc_err_outbox_ecc_ofu, + xu_pc_err_regfile_parity => xu_pc_err_regfile_parity_ofu, + xu_pc_err_regfile_ue => xu_pc_err_regfile_ue_ofu, + xu_pc_err_sprg_ecc => xu_pc_err_sprg_ecc_ofu, + xu_pc_err_sprg_ue => xu_pc_err_sprg_ue_ofu, + xu_pc_err_wdt_reset => xu_pc_err_wdt_reset_ofu, + xu_pc_event_data => xu_pc_event_data_ofu, + lsu_pc_event_data => xu_pc_lsu_event_data_ofu, + ac_pc_trace_to_perfcntr => rp_pc_trace_to_perfcntr_q, + xu_pc_ram_data => xu_pc_ram_data_ofu, + xu_pc_ram_done => xu_pc_ram_done_ofu, + xu_pc_ram_interrupt => xu_pc_ram_interrupt_ofu, + xu_pc_running => xu_pc_running_ofu, + xu_pc_spr_ccr0_pme => xu_pc_spr_ccr0_pme_ofu, + xu_pc_spr_ccr0_we => xu_pc_spr_ccr0_we_ofu, + xu_pc_step_done => xu_pc_step_done_ofu, + xu_pc_stop_dbg_event => xu_pc_stop_dbg_event_ofu, + an_ac_bo_enable => an_ac_bo_enable, + an_ac_bo_go => an_ac_bo_go, + an_ac_bo_cntlclk => an_ac_bo_cntlclk, + an_ac_bo_ccflush => an_ac_bo_ccflush, + an_ac_bo_reset => an_ac_bo_reset, + an_ac_bo_data => an_ac_bo_data, + an_ac_bo_shcntl => an_ac_bo_shcntl, + an_ac_bo_shdata => an_ac_bo_shdata, + an_ac_bo_exe => an_ac_bo_exe, + an_ac_bo_sysrepair => an_ac_bo_sysrepair, + an_ac_bo_donein => an_ac_bo_donein, + an_ac_bo_sdin => an_ac_bo_sdin, + an_ac_bo_waitin => an_ac_bo_waitin, + an_ac_bo_failin => an_ac_bo_failin, + an_ac_bo_fcshdata => an_ac_bo_fcshdata, + an_ac_bo_fcreset => an_ac_bo_fcreset, + ac_an_bo_doneout => ac_an_bo_doneout, + ac_an_bo_sdout => ac_an_bo_sdout, + ac_an_bo_diagloopout => ac_an_bo_diagloopout, + ac_an_bo_waitout => ac_an_bo_waitout, + ac_an_bo_failout => ac_an_bo_failout, + pc_bx_bolt_sl_thold_3 => pc_bx_bolt_sl_thold_3, + pc_fu_bolt_sl_thold_3 => pc_fu_bolt_sl_thold_3, + pc_xu_bolt_sl_thold_3 => pc_xu_bolt_sl_thold_3, + pc_bx_bo_enable_3 => pc_bx_bo_enable_3, + pc_bx_bo_unload => pc_bx_bo_unload, + pc_bx_bo_repair => pc_bx_bo_repair, + pc_bx_bo_reset => pc_bx_bo_reset, + pc_bx_bo_shdata => pc_bx_bo_shdata, + pc_bx_bo_select => pc_bx_bo_select, + bx_pc_bo_fail => bx_pc_bo_fail_ofu, + bx_pc_bo_diagout => bx_pc_bo_diagout_ofu, + pc_fu_bo_enable_3 => pc_fu_bo_enable_3, + pc_fu_bo_unload => pc_fu_bo_unload, + pc_fu_bo_load => pc_fu_bo_load, + pc_fu_bo_reset => pc_fu_bo_reset, + pc_fu_bo_shdata => pc_fu_bo_shdata, + pc_fu_bo_select => pc_fu_bo_select, + fu_pc_bo_fail => fu_pc_bo_fail, + fu_pc_bo_diagout => fu_pc_bo_diagout, + pc_iu_bo_enable_4 => pc_iu_bo_enable_4, + pc_iu_bo_unload => pc_iu_bo_unload, + pc_iu_bo_repair => pc_iu_bo_repair, + pc_iu_bo_reset => pc_iu_bo_reset, + pc_iu_bo_shdata => pc_iu_bo_shdata, + pc_iu_bo_select => pc_iu_bo_select, + iu_pc_bo_fail => iu_pc_bo_fail, + iu_pc_bo_diagout => iu_pc_bo_diagout, + pc_mm_bo_enable_4 => pc_mm_bo_enable_4_iiu, + pc_mm_bo_unload => pc_mm_bo_unload_iiu, + pc_mm_bo_repair => pc_mm_bo_repair_iiu, + pc_mm_bo_reset => pc_mm_bo_reset_iiu, + pc_mm_bo_shdata => pc_mm_bo_shdata_iiu, + pc_mm_bo_select => pc_mm_bo_select_iiu, + mm_pc_bo_fail => mm_pc_bo_fail_oiu, + mm_pc_bo_diagout => mm_pc_bo_diagout_oiu, + pc_xu_bo_enable_3 => pc_xu_bo_enable_3, + pc_xu_bo_unload => pc_xu_bo_unload, + pc_xu_bo_load => pc_xu_bo_load, + pc_xu_bo_repair => pc_xu_bo_repair, + pc_xu_bo_reset => pc_xu_bo_reset, + pc_xu_bo_shdata => pc_xu_bo_shdata, + pc_xu_bo_select => pc_xu_bo_select, + xu_pc_bo_fail => xu_pc_bo_fail_ofu, + xu_pc_bo_diagout => xu_pc_bo_diagout_ofu, + ac_an_power_managed => pc_rp_power_managed, + ac_an_rvwinkle_mode => pc_rp_rvwinkle_mode, + ac_an_fu_bypass_events => pc_rp_fu_bypass_events, + ac_an_iu_bypass_events => pc_rp_iu_bypass_events, + ac_an_mm_bypass_events => pc_rp_mm_bypass_events, + ac_an_lsu_bypass_events => pc_rp_lsu_bypass_events, + ac_an_event_bus => pc_rp_event_bus, + ac_an_abist_done_dc => ac_an_abist_done_dc_iiu, + ac_an_local_checkstop => pc_rp_local_checkstop, + ac_an_pm_thread_running => pc_rp_pm_thread_running, + ac_an_psro_ringsig => ac_an_psro_ringsig_iiu, + ac_an_recov_err => pc_rp_recov_err, + ac_an_scom_cch => pc_rp_scom_cch, + ac_an_scom_dch => pc_rp_scom_dch, + ac_an_special_attn => pc_rp_special_attn, + ac_an_checkstop => pc_rp_checkstop, + ac_an_trace_error => pc_rp_trace_error, + debug_bus_out => pc_iu_debug_data, + trace_triggers_out => pc_iu_trigger_data, + abst_scan_out => pc_rp_abst_scan_out, + bcfg_scan_out => pc_rp_bcfg_scan_out, + ccfg_scan_out => pc_rp_ccfg_scan_out, + dcfg_scan_out => pc_rp_dcfg_scan_out, + func_scan_out => pc_rp_func_scan_out(0 to 1), + gptr_scan_out => pc_fu_gptr_scan_out, + pc_bx_abist_di_0 => pc_bx_abist_di_0(0 to 3), + pc_bx_abist_ena_dc => pc_bx_abist_ena_dc, + pc_bx_abist_g8t1p_renb_0 => pc_bx_abist_g8t1p_renb_0, + pc_bx_abist_g8t_bw_0 => pc_bx_abist_g8t_bw_0, + pc_bx_abist_g8t_bw_1 => pc_bx_abist_g8t_bw_1, + pc_bx_abist_g8t_dcomp => pc_bx_abist_g8t_dcomp(0 to 3), + pc_bx_abist_g8t_wenb => pc_bx_abist_g8t_wenb, + pc_bx_abist_raddr_0 => pc_bx_abist_raddr_0(0 to 9), + pc_bx_abist_raw_dc_b => pc_bx_abist_raw_dc_b, + pc_bx_abist_waddr_0 => pc_bx_abist_waddr_0(0 to 9), + pc_bx_abist_wl64_g8t_comp_ena => pc_bx_abist_wl64_comp_ena, + pc_fu_abist_di_0 => pc_fu_abist_di_0(0 to 3), + pc_fu_abist_di_1 => pc_fu_abist_di_1(0 to 3), + pc_fu_abist_ena_dc => pc_fu_abist_ena_dc, + pc_fu_abist_grf_renb_0 => pc_fu_abist_grf_renb_0, + pc_fu_abist_grf_renb_1 => pc_fu_abist_grf_renb_1, + pc_fu_abist_grf_wenb_0 => pc_fu_abist_grf_wenb_0, + pc_fu_abist_grf_wenb_1 => pc_fu_abist_grf_wenb_1, + pc_fu_abist_raddr_0 => pc_fu_abist_raddr_0(0 to 9), + pc_fu_abist_raddr_1 => pc_fu_abist_raddr_1(0 to 9), + pc_fu_abist_raw_dc_b => pc_fu_abist_raw_dc_b, + pc_fu_abist_waddr_0 => pc_fu_abist_waddr_0(0 to 9), + pc_fu_abist_waddr_1 => pc_fu_abist_waddr_1(0 to 9), + pc_fu_abist_wl144_comp_ena => pc_fu_abist_wl144_comp_ena, + pc_iu_abist_dcomp_g6t_2r => pc_iu_abist_dcomp_g6t_2r(0 to 3), + pc_iu_abist_di_0 => pc_iu_abist_di_0(0 to 3), + pc_iu_abist_di_g6t_2r => pc_iu_abist_di_g6t_2r(0 to 3), + pc_iu_abist_ena_dc => pc_iu_abist_ena_dc, + pc_iu_abist_g6t_bw => pc_iu_abist_g6t_bw(0 to 1), + pc_iu_abist_g6t_r_wb => pc_iu_abist_g6t_r_wb, + pc_iu_abist_g8t1p_renb_0 => pc_iu_abist_g8t1p_renb_0, + pc_iu_abist_g8t_bw_0 => pc_iu_abist_g8t_bw_0, + pc_iu_abist_g8t_bw_1 => pc_iu_abist_g8t_bw_1, + pc_iu_abist_g8t_dcomp => pc_iu_abist_g8t_dcomp(0 to 3), + pc_iu_abist_g8t_wenb => pc_iu_abist_g8t_wenb, + pc_iu_abist_raddr_0 => pc_iu_abist_raddr_0(0 to 9), + pc_iu_abist_raw_dc_b => pc_iu_abist_raw_dc_b, + pc_iu_abist_waddr_0 => pc_iu_abist_waddr_0(0 to 9), + pc_iu_abist_wl128_g8t_comp_ena => pc_iu_abist_wl128_comp_ena, + pc_iu_abist_wl256_comp_ena => pc_iu_abist_wl256_comp_ena, + pc_iu_abist_wl64_g8t_comp_ena => pc_iu_abist_wl64_comp_ena, + pc_mm_abist_dcomp_g6t_2r => pc_mm_abist_dcomp_g6t_2r_iiu(0 to 3), + pc_mm_abist_di_0 => pc_mm_abist_di_0_iiu(0 to 3), + pc_mm_abist_di_g6t_2r => pc_mm_abist_di_g6t_2r_iiu(0 to 3), + pc_mm_abist_ena_dc => pc_mm_abist_ena_dc_iiu, + pc_mm_abist_g6t_r_wb => pc_mm_abist_g6t_r_wb_iiu, + pc_mm_abist_g8t1p_renb_0 => pc_mm_abist_g8t1p_renb_0_iiu, + pc_mm_abist_g8t_bw_0 => pc_mm_abist_g8t_bw_0_iiu, + pc_mm_abist_g8t_bw_1 => pc_mm_abist_g8t_bw_1_iiu, + pc_mm_abist_g8t_dcomp => pc_mm_abist_g8t_dcomp_iiu(0 to 3), + pc_mm_abist_g8t_wenb => pc_mm_abist_g8t_wenb_iiu, + pc_mm_abist_raddr_0 => pc_mm_abist_raddr_0_iiu(0 to 9), + pc_mm_abist_raw_dc_b => pc_mm_abist_raw_dc_b_iiu, + pc_mm_abist_waddr_0 => pc_mm_abist_waddr_0_iiu(0 to 9), + pc_mm_abist_wl128_g8t_comp_ena => pc_mm_abist_wl128_comp_ena_iiu, + pc_xu_abist_dcomp_g6t_2r => pc_xu_abist_dcomp_g6t_2r(0 to 3), + pc_xu_abist_di_0 => pc_xu_abist_di_0(0 to 3), + pc_xu_abist_di_1 => pc_xu_abist_di_1(0 to 3), + pc_xu_abist_di_g6t_2r => pc_xu_abist_di_g6t_2r(0 to 3), + pc_xu_abist_ena_dc => pc_xu_abist_ena_dc, + pc_xu_abist_g6t_bw => pc_xu_abist_g6t_bw(0 to 1), + pc_xu_abist_g6t_r_wb => pc_xu_abist_g6t_r_wb, + pc_xu_abist_g8t1p_renb_0 => pc_xu_abist_g8t1p_renb_0, + pc_xu_abist_g8t_bw_0 => pc_xu_abist_g8t_bw_0, + pc_xu_abist_g8t_bw_1 => pc_xu_abist_g8t_bw_1, + pc_xu_abist_g8t_dcomp => pc_xu_abist_g8t_dcomp(0 to 3), + pc_xu_abist_g8t_wenb => pc_xu_abist_g8t_wenb, + pc_xu_abist_grf_renb_0 => pc_xu_abist_grf_renb_0, + pc_xu_abist_grf_renb_1 => pc_xu_abist_grf_renb_1, + pc_xu_abist_grf_wenb_0 => pc_xu_abist_grf_wenb_0, + pc_xu_abist_grf_wenb_1 => pc_xu_abist_grf_wenb_1, + pc_xu_abist_raddr_0 => pc_xu_abist_raddr_0(0 to 9), + pc_xu_abist_raddr_1 => pc_xu_abist_raddr_1(0 to 9), + pc_xu_abist_raw_dc_b => pc_xu_abist_raw_dc_b, + pc_xu_abist_waddr_0 => pc_xu_abist_waddr_0(0 to 9), + pc_xu_abist_waddr_1 => pc_xu_abist_waddr_1(0 to 9), + pc_xu_abist_wl144_comp_ena => pc_xu_abist_wl144_comp_ena, + pc_xu_abist_wl32_g8t_comp_ena => pc_xu_abist_wl32_comp_ena, + pc_xu_abist_wl512_comp_ena => pc_xu_abist_wl512_comp_ena, + pc_bx_trace_bus_enable => pc_bx_trace_bus_enable, + pc_bx_debug_mux1_ctrls => pc_bx_debug_mux1_ctrls, + pc_bx_inj_inbox_ecc => pc_bx_inj_inbox_ecc, + pc_bx_inj_outbox_ecc => pc_bx_inj_outbox_ecc, + pc_fu_abst_sl_thold_3 => pc_fu_abst_sl_thold_3, + pc_fu_abst_slp_sl_thold_3 => pc_fu_abst_slp_sl_thold_3, + pc_fu_ary_nsl_thold_3 => pc_fu_ary_nsl_thold_3, + pc_fu_ary_slp_nsl_thold_3 => pc_fu_ary_slp_nsl_thold_3, + pc_fu_ccflush_dc => pc_fu_ccflush_dc, + pc_fu_cfg_sl_thold_3 => pc_fu_cfg_sl_thold_3, + pc_fu_cfg_slp_sl_thold_3 => pc_fu_cfg_slp_sl_thold_3, + pc_fu_debug_mux1_ctrls => pc_fu_debug_mux1_ctrls, + pc_fu_event_count_mode => pc_fu_event_count_mode, + pc_fu_event_mux_ctrls => pc_fu_event_mux_ctrls, + pc_iu_event_mux_ctrls => pc_iu_event_mux_ctrls, + pc_mm_event_mux_ctrls => pc_mm_event_mux_ctrls_iiu, + pc_xu_event_mux_ctrls => pc_xu_event_mux_ctrls, + pc_xu_lsu_event_mux_ctrls => pc_xu_lsu_event_mux_ctrls, + pc_fu_event_bus_enable => pc_fu_event_bus_enable, + pc_iu_event_bus_enable => pc_iu_event_bus_enable, + pc_rp_event_bus_enable => pc_rp_event_bus_enable, + pc_xu_event_bus_enable => pc_xu_event_bus_enable, + pc_fu_fce_3 => pc_fu_fce_3, + pc_fu_func_nsl_thold_3 => pc_fu_func_nsl_thold_3, + pc_fu_func_sl_thold_3 => pc_fu_func_sl_thold_3, + pc_fu_func_slp_nsl_thold_3 => pc_fu_func_slp_nsl_thold_3, + pc_fu_func_slp_sl_thold_3 => pc_fu_func_slp_sl_thold_3, + pc_fu_gptr_sl_thold_3 => pc_fu_gptr_sl_thold_3, + pc_fu_inj_regfile_parity => pc_fu_inj_regfile_parity, + pc_fu_instr_trace_mode => pc_fu_instr_trace_mode, + pc_fu_instr_trace_tid => pc_fu_instr_trace_tid, + pc_fu_ram_mode => pc_fu_ram_mode, + pc_fu_ram_thread => pc_fu_ram_thread, + pc_fu_repr_sl_thold_3 => pc_fu_repr_sl_thold_3, + pc_fu_sg_3 => pc_fu_sg_3, + slowspr_addr_out => pc_fu_slowspr_addr, + slowspr_data_out => pc_fu_slowspr_data, + slowspr_done_out => pc_fu_slowspr_done, + slowspr_etid_out => pc_fu_slowspr_etid, + slowspr_rw_out => pc_fu_slowspr_rw, + slowspr_val_out => pc_fu_slowspr_val, + pc_fu_time_sl_thold_3 => pc_fu_time_sl_thold_3, + pc_fu_trace_bus_enable => pc_fu_trace_bus_enable, + pc_iu_ccflush_dc => pc_iu_ccflush_dc, + pc_iu_gptr_sl_thold_4 => pc_iu_gptr_sl_thold_4, + pc_iu_time_sl_thold_4 => pc_iu_time_sl_thold_4, + pc_iu_repr_sl_thold_4 => pc_iu_repr_sl_thold_4, + pc_iu_abst_sl_thold_4 => pc_iu_abst_sl_thold_4, + pc_iu_abst_slp_sl_thold_4 => pc_iu_abst_slp_sl_thold_4, + pc_iu_bolt_sl_thold_4 => pc_iu_bolt_sl_thold_4, + pc_iu_regf_slp_sl_thold_4 => pc_iu_regf_slp_sl_thold_4, + pc_iu_func_sl_thold_4 => pc_iu_func_sl_thold_4, + pc_iu_func_slp_sl_thold_4 => pc_iu_func_slp_sl_thold_4, + pc_iu_cfg_sl_thold_4 => pc_iu_cfg_sl_thold_4, + pc_iu_cfg_slp_sl_thold_4 => pc_iu_cfg_slp_sl_thold_4, + pc_iu_func_nsl_thold_4 => pc_iu_func_nsl_thold_4, + pc_iu_func_slp_nsl_thold_4 => pc_iu_func_slp_nsl_thold_4, + pc_iu_ary_nsl_thold_4 => pc_iu_ary_nsl_thold_4, + pc_iu_ary_slp_nsl_thold_4 => pc_iu_ary_slp_nsl_thold_4, + pc_iu_sg_4 => pc_iu_sg_4, + pc_iu_fce_4 => pc_iu_fce_4, + pc_iu_debug_mux1_ctrls => pc_iu_debug_mux1_ctrls, + pc_iu_debug_mux2_ctrls => pc_iu_debug_mux2_ctrls, + pc_iu_event_count_mode => pc_iu_event_count_mode, + pc_iu_init_reset => pc_iu_init_reset, + pc_iu_inj_icache_parity => pc_iu_inj_icache_parity, + pc_iu_inj_icachedir_parity => pc_iu_inj_icachedir_parity, + pc_iu_inj_icachedir_multihit => pc_iu_inj_icachedir_multihit, + pc_iu_ram_force_cmplt => pc_iu_ram_force_cmplt, + pc_iu_ram_instr => pc_iu_ram_instr, + pc_iu_ram_instr_ext => pc_iu_ram_instr_ext, + pc_iu_ram_mode => pc_iu_ram_mode, + pc_iu_ram_thread => pc_iu_ram_thread, + pc_iu_trace_bus_enable => pc_iu_trace_bus_enable, + pc_mm_ccflush_dc => pc_mm_ccflush_dc_iiu, + pc_mm_debug_mux1_ctrls => pc_mm_debug_mux1_ctrls_iiu, + pc_mm_event_count_mode => pc_mm_event_count_mode_iiu, + pc_mm_trace_bus_enable => pc_mm_trace_bus_enable_iiu, + pc_xu_abst_sl_thold_3 => pc_xu_abst_sl_thold_3, + pc_xu_abst_slp_sl_thold_3 => pc_xu_abst_slp_sl_thold_3, + pc_xu_regf_sl_thold_3 => pc_xu_regf_sl_thold_3, + pc_xu_regf_slp_sl_thold_3 => pc_xu_regf_slp_sl_thold_3, + pc_xu_ary_nsl_thold_3 => pc_xu_ary_nsl_thold_3, + pc_xu_ary_slp_nsl_thold_3 => pc_xu_ary_slp_nsl_thold_3, + pc_xu_cache_par_err_event => pc_xu_cache_par_err_event, + pc_xu_ccflush_dc => pc_xu_ccflush_dc, + pc_xu_cfg_sl_thold_3 => pc_xu_cfg_sl_thold_3, + pc_xu_cfg_slp_sl_thold_3 => pc_xu_cfg_slp_sl_thold_3, + pc_xu_dbg_action => pc_xu_dbg_action, + pc_xu_debug_mux1_ctrls => pc_xu_debug_mux1_ctrls, + pc_xu_debug_mux2_ctrls => pc_xu_debug_mux2_ctrls, + pc_xu_debug_mux3_ctrls => pc_xu_debug_mux3_ctrls, + pc_xu_debug_mux4_ctrls => pc_xu_debug_mux4_ctrls, + pc_xu_decrem_dis_on_stop => pc_xu_decrem_dis_on_stop, + pc_xu_event_count_mode => pc_xu_event_count_mode, + pc_xu_extirpts_dis_on_stop => pc_xu_extirpts_dis_on_stop, + pc_xu_fce_3 => pc_xu_fce_3, + pc_xu_force_ude => pc_xu_force_ude, + pc_xu_func_nsl_thold_3 => pc_xu_func_nsl_thold_3, + pc_xu_func_sl_thold_3 => pc_xu_func_sl_thold_3, + pc_xu_func_slp_nsl_thold_3 => pc_xu_func_slp_nsl_thold_3, + pc_xu_func_slp_sl_thold_3 => pc_xu_func_slp_sl_thold_3, + pc_xu_gptr_sl_thold_3 => pc_xu_gptr_sl_thold_3, + pc_xu_init_reset => pc_xu_init_reset, + pc_xu_inj_dcache_parity => pc_xu_inj_dcache_parity, + pc_xu_inj_dcachedir_parity => pc_xu_inj_dcachedir_parity, + pc_xu_inj_llbust_attempt => pc_xu_inj_llbust_attempt, + pc_xu_inj_llbust_failed => pc_xu_inj_llbust_failed, + pc_xu_inj_sprg_ecc => pc_xu_inj_sprg_ecc, + pc_xu_inj_regfile_parity => pc_xu_inj_regfile_parity, + pc_xu_inj_wdt_reset => pc_xu_inj_wdt_reset, + pc_xu_inj_dcachedir_multihit => pc_xu_inj_dcachedir_multihit, + pc_xu_instr_trace_mode => pc_xu_instr_trace_mode, + pc_xu_instr_trace_tid => pc_xu_instr_trace_tid, + pc_xu_msrovride_de => pc_xu_msrovride_de, + pc_xu_msrovride_enab => pc_xu_msrovride_enab, + pc_xu_msrovride_gs => pc_xu_msrovride_gs, + pc_xu_msrovride_pr => pc_xu_msrovride_pr, + pc_xu_ram_execute => pc_xu_ram_execute, + pc_xu_ram_flush_thread => pc_xu_ram_flush_thread, + pc_xu_ram_mode => pc_xu_ram_mode, + pc_xu_ram_thread => pc_xu_ram_thread, + pc_xu_repr_sl_thold_3 => pc_xu_repr_sl_thold_3, + pc_xu_reset_1_cmplt => pc_xu_reset_1_complete, + pc_xu_reset_2_cmplt => pc_xu_reset_2_complete, + pc_xu_reset_3_cmplt => pc_xu_reset_3_complete, + pc_xu_reset_wd_cmplt => pc_xu_reset_wd_complete, + pc_xu_sg_3 => pc_xu_sg_3, + pc_xu_step => pc_xu_step, + pc_xu_stop => pc_xu_stop, + pc_xu_time_sl_thold_3 => pc_xu_time_sl_thold_3, + pc_xu_timebase_dis_on_stop => pc_xu_timebase_dis_on_stop, + pc_xu_trace_bus_enable => pc_xu_trace_bus_enable, + pc_bx_ccflush_dc => pc_bx_ccflush_dc, + pc_bx_sg_3 => pc_bx_sg_3, + pc_bx_func_sl_thold_3 => pc_bx_func_sl_thold_3, + pc_bx_func_slp_sl_thold_3 => pc_bx_func_slp_sl_thold_3, + pc_bx_gptr_sl_thold_3 => pc_bx_gptr_sl_thold_3, + pc_bx_time_sl_thold_3 => pc_bx_time_sl_thold_3, + pc_bx_repr_sl_thold_3 => pc_bx_repr_sl_thold_3, + pc_bx_abst_sl_thold_3 => pc_bx_abst_sl_thold_3, + pc_bx_ary_nsl_thold_3 => pc_bx_ary_nsl_thold_3, + pc_bx_ary_slp_nsl_thold_3 => pc_bx_ary_slp_nsl_thold_3, + + an_ac_scan_diag_dc_opc => an_ac_scan_diag_dc_opc, + an_ac_scan_dis_dc_b_opc => an_ac_scan_dis_dc_b_opc, + + xu_pc_err_mchk_disabled => xu_pc_err_mchk_disabled_ofu, + + gnd => gnd, + vdd => vdd + ); + + +bx: if include_boxes=1 generate begin + a_bxq: entity work.bxq + generic map(expand_type => expand_type, + real_data_add => xu_real_data_add, + regmode => regmode) + PORT map( + xu_bx_ccr2_en_ditc => xu_bx_ccr2_en_ditc, + xu_ex2_flush => xu_ex2_flush_ofu, + xu_ex3_flush => xu_ex3_flush_ofu, + xu_ex4_flush => xu_ex4_flush_ofu, + xu_ex5_flush => xu_ex5_flush_ofu, + xu_bx_ex1_mtdp_val => xu_bx_ex1_mtdp_val, + xu_bx_ex1_mfdp_val => xu_bx_ex1_mfdp_val, + xu_bx_ex1_ipc_thrd => xu_bx_ex1_ipc_thrd, + xu_bx_ex2_ipc_ba => xu_bx_ex2_ipc_ba, + xu_bx_ex2_ipc_sz => xu_bx_ex2_ipc_sz, + xu_bx_ex4_256st_data => xu_bx_ex4_256st_data(128 to 255) , + + bx_xu_ex4_mtdp_cr_status => bx_xu_ex4_mtdp_cr_status , + bx_xu_ex4_mfdp_cr_status => bx_xu_ex4_mfdp_cr_status , + bx_xu_ex5_dp_data => bx_xu_ex5_dp_data , + + bx_lsu_ob_pwr_tok => bx_lsu_ob_pwr_tok, + bx_lsu_ob_req_val => bx_lsu_ob_req_val, + bx_lsu_ob_ditc_val => bx_lsu_ob_ditc_val, + bx_lsu_ob_thrd => bx_lsu_ob_thrd, + bx_lsu_ob_qw => bx_lsu_ob_qw, + bx_lsu_ob_dest => bx_lsu_ob_dest, + bx_lsu_ob_data => bx_lsu_ob_data, + bx_lsu_ob_addr => bx_lsu_ob_addr, + + ac_an_reld_ditc_pop => ac_an_reld_ditc_pop_int, + + bx_ib_empty => bx_ib_empty_int, + bx_xu_quiesce => bx_xu_quiesce, + + lsu_bx_cmd_avail => lsu_bx_cmd_avail, + lsu_bx_cmd_sent => lsu_bx_cmd_sent, + lsu_bx_cmd_stall => lsu_bx_cmd_stall, + + lsu_reld_data_vld => lsu_reld_data_vld, + lsu_reld_core_tag => lsu_reld_core_tag(3 to 4), + lsu_reld_qw => lsu_reld_qw, + lsu_reld_ditc => lsu_reld_ditc, + lsu_reld_ecc_err => lsu_reld_ecc_err, + lsu_reld_data => lsu_reld_data, + + an_ac_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc_ofu, + + lsu_req_st_pop => lsu_req_st_pop , + lsu_req_st_pop_thrd => lsu_req_st_pop_thrd , + + slowspr_addr_in => fu_bx_slowspr_addr, + slowspr_data_in => fu_bx_slowspr_data, + slowspr_done_in => fu_bx_slowspr_done, + slowspr_etid_in => fu_bx_slowspr_etid, + slowspr_rw_in => fu_bx_slowspr_rw, + slowspr_val_in => fu_bx_slowspr_val, + slowspr_addr_out => bx_xu_slowspr_addr, + slowspr_data_out => bx_xu_slowspr_data, + slowspr_done_out => bx_xu_slowspr_done, + slowspr_etid_out => bx_xu_slowspr_etid, + slowspr_rw_out => bx_xu_slowspr_rw, + slowspr_val_out => bx_xu_slowspr_val, + + bx_pc_bo_fail => bx_pc_bo_fail, + bx_pc_bo_diagout => bx_pc_bo_diagout, + bx_pc_err_inbox_ecc => bx_pc_err_inbox_ecc, + bx_pc_err_outbox_ecc => bx_pc_err_outbox_ecc, + bx_pc_err_inbox_ue => bx_pc_err_inbox_ue, + bx_pc_err_outbox_ue => bx_pc_err_outbox_ue, + pc_bx_inj_inbox_ecc => pc_bx_inj_inbox_ecc_ofu, + pc_bx_inj_outbox_ecc => pc_bx_inj_outbox_ecc_ofu, + + pc_bx_trace_bus_enable => pc_bx_trace_bus_enable_ofu, + pc_bx_debug_mux1_ctrls => pc_bx_debug_mux1_ctrls_ofu, + trigger_data_in => trigger_start_tiedowns, + debug_data_in => debug_start_tiedowns, + debug_data_out => bx_fu_debug_data, + trigger_data_out => bx_fu_trigger_data, + + vdd => vdd, + gnd => gnd, + vcs => vcs, + nclk => a2_nclk, + + pc_bx_abist_di_0 => pc_bx_abist_di_0_ofu, + pc_bx_abist_ena_dc => pc_bx_abist_ena_dc_ofu, + pc_bx_abist_g8t1p_renb_0 => pc_bx_abist_g8t1p_renb_0_ofu, + pc_bx_abist_g8t_bw_0 => pc_bx_abist_g8t_bw_0_ofu, + pc_bx_abist_g8t_bw_1 => pc_bx_abist_g8t_bw_1_ofu, + pc_bx_abist_g8t_dcomp => pc_bx_abist_g8t_dcomp_ofu, + pc_bx_abist_g8t_wenb => pc_bx_abist_g8t_wenb_ofu, + pc_bx_abist_raddr_0 => pc_bx_abist_raddr_0_ofu(4 to 9), + pc_bx_abist_raw_dc_b => pc_bx_abist_raw_dc_b_ofu, + pc_bx_abist_waddr_0 => pc_bx_abist_waddr_0_ofu(4 to 9), + pc_bx_abist_wl64_comp_ena => pc_bx_abist_wl64_comp_ena_ofu, + pc_bx_bolt_sl_thold_3 => pc_bx_bolt_sl_thold_3_ofu, + pc_bx_bo_enable_3 => pc_bx_bo_enable_3_ofu, + pc_bx_bo_unload => pc_bx_bo_unload_ofu, + pc_bx_bo_repair => pc_bx_bo_repair_ofu, + pc_bx_bo_reset => pc_bx_bo_reset_ofu, + pc_bx_bo_shdata => pc_bx_bo_shdata_ofu, + pc_bx_bo_select => pc_bx_bo_select_ofu, + pc_bx_ccflush_dc => pc_bx_ccflush_dc_ofu, + pc_bx_sg_3 => pc_bx_sg_3_ofu, + pc_bx_func_sl_thold_3 => pc_bx_func_sl_thold_3_ofu, + pc_bx_func_slp_sl_thold_3 => pc_bx_func_slp_sl_thold_3_ofu, + pc_bx_gptr_sl_thold_3 => pc_bx_gptr_sl_thold_3_ofu, + pc_bx_abst_sl_thold_3 => pc_bx_abst_sl_thold_3_ofu, + pc_bx_time_sl_thold_3 => pc_bx_time_sl_thold_3_ofu, + pc_bx_ary_nsl_thold_3 => pc_bx_ary_nsl_thold_3_ofu, + pc_bx_ary_slp_nsl_thold_3 => pc_bx_ary_slp_nsl_thold_3_ofu, + pc_bx_repr_sl_thold_3 => pc_bx_repr_sl_thold_3_ofu, + an_ac_scan_diag_dc => an_ac_scan_diag_dc_ofu, + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b_ofu, + time_scan_in => fu_bx_time_scan_out, + repr_scan_in => fu_bx_repr_scan_out, + abst_scan_in => rp_fu_bx_abst_scan_in, + time_scan_out => bx_xu_time_scan_out, + repr_scan_out => bx_xu_repr_scan_out, + abst_scan_out => bx_fu_rp_abst_scan_out, + gptr_scan_in => fu_bx_gptr_scan_out, + gptr_scan_out => bx_xu_gptr_scan_out, + func_scan_in => rp_fu_bx_func_scan_in, + func_scan_out => bx_fu_rp_func_scan_out + ); +end generate; + + +nobx: if include_boxes=0 generate begin + bx_xu_ex5_dp_data <= (others=>'0'); + bx_xu_ex4_mtdp_cr_status <= '0'; + bx_xu_ex4_mfdp_cr_status <= '0'; + bx_lsu_ob_pwr_tok <= '0'; + bx_lsu_ob_req_val <= '0'; + bx_lsu_ob_ditc_val <= '0'; + bx_lsu_ob_thrd <= (others=>'0'); + bx_lsu_ob_qw <= (others=>'0'); + bx_lsu_ob_dest <= (others=>'0'); + bx_lsu_ob_data <= (others=>'0'); + bx_lsu_ob_addr <= (others=>'0'); + ac_an_reld_ditc_pop_int <= (others=>'0'); + bx_ib_empty_int <= (others=>'1'); + bx_xu_quiesce <= (others=>'1'); + bx_xu_slowspr_addr <= fu_bx_slowspr_addr; + bx_xu_slowspr_data <= fu_bx_slowspr_data; + bx_xu_slowspr_done <= fu_bx_slowspr_done; + bx_xu_slowspr_etid <= fu_bx_slowspr_etid; + bx_xu_slowspr_rw <= fu_bx_slowspr_rw; + bx_xu_slowspr_val <= fu_bx_slowspr_val; + bx_pc_err_inbox_ecc <= '0'; + bx_pc_err_outbox_ecc <= '0'; + bx_pc_err_inbox_ue <= '0'; + bx_pc_err_outbox_ue <= '0'; + bx_fu_debug_data <= debug_start_tiedowns; + bx_fu_trigger_data <= trigger_start_tiedowns; + bx_xu_time_scan_out <= fu_bx_time_scan_out; + bx_xu_repr_scan_out <= fu_bx_repr_scan_out; + bx_rp_abst_scan_out <= rp_bx_abst_scan_in_q; + fu_bx_gptr_scan_out <= fu_bx_gptr_scan_out; + bx_rp_func_scan_out <= rp_bx_func_scan_in_q; +end generate; + + +END acq_soft; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/bxq.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/bxq.vhdl new file mode 100644 index 0000000..abdd9a6 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/bxq.vhdl @@ -0,0 +1,6876 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +LIBRARY ieee; USE ieee.std_logic_1164.all ; + USE ieee.numeric_std.all; +LIBRARY ibm; + USE ibm.std_ulogic_support.all ; + USE ibm.std_ulogic_function_support.all; + USE ibm.std_ulogic_unsigned.all; +LIBRARY tri; USE tri.tri_latches_pkg.all; +LIBRARY support; + USE support.power_logic_pkg.all; +LIBRARY clib; + + +ENTITY bxq IS + generic(expand_type : integer := 2; + regmode : integer := 6; + real_data_add : integer := 42 ); + PORT ( + xu_bx_ccr2_en_ditc :in std_ulogic; + xu_ex2_flush :in std_ulogic_vector(0 to 3); + xu_ex3_flush :in std_ulogic_vector(0 to 3); + xu_ex4_flush :in std_ulogic_vector(0 to 3); + xu_ex5_flush :in std_ulogic_vector(0 to 3); + xu_bx_ex1_mtdp_val :in std_ulogic; + xu_bx_ex1_mfdp_val :in std_ulogic; + xu_bx_ex1_ipc_thrd :in std_ulogic_vector(0 to 1); + xu_bx_ex2_ipc_ba :in std_ulogic_vector(0 to 4); + xu_bx_ex2_ipc_sz :in std_ulogic_vector(0 to 1); + xu_bx_ex4_256st_data :in std_ulogic_vector(0 to 127); + + bx_xu_ex4_mtdp_cr_status :out std_ulogic; + bx_xu_ex4_mfdp_cr_status :out std_ulogic; + bx_xu_ex5_dp_data :out std_ulogic_vector(0 to 127); + + bx_lsu_ob_pwr_tok :out std_ulogic; + bx_lsu_ob_req_val :out std_ulogic; + bx_lsu_ob_ditc_val :out std_ulogic; + bx_lsu_ob_thrd :out std_ulogic_vector(0 to 1); + bx_lsu_ob_qw :out std_ulogic_vector(58 to 59); + bx_lsu_ob_dest :out std_ulogic_vector(0 to 14); + bx_lsu_ob_data :out std_ulogic_vector(0 to 127); + bx_lsu_ob_addr :out std_ulogic_vector(64-real_data_add to 57); + + ac_an_reld_ditc_pop :out std_ulogic_vector(0 to 3); + + bx_ib_empty :out std_ulogic_vector(0 to 3); + bx_xu_quiesce :out std_ulogic_vector(0 to 3); + + lsu_bx_cmd_avail :in std_ulogic; + lsu_bx_cmd_sent :in std_ulogic; + lsu_bx_cmd_stall :in std_ulogic; + + + lsu_reld_data_vld :in std_ulogic; + lsu_reld_core_tag :in std_ulogic_vector(3 to 4); + lsu_reld_qw :in std_ulogic_vector(58 to 59); + lsu_reld_ditc :in std_ulogic; + lsu_reld_data :in std_ulogic_vector(0 to 127); + lsu_reld_ecc_err :in std_ulogic; + + lsu_req_st_pop :in std_ulogic; + lsu_req_st_pop_thrd :in std_ulogic_vector(0 to 2); + + slowspr_val_in :in std_ulogic; + slowspr_rw_in :in std_ulogic; + slowspr_etid_in :in std_ulogic_vector(0 to 1); + slowspr_addr_in :in std_ulogic_vector(0 to 9); + slowspr_data_in :in std_ulogic_vector(64-(2**REGMODE) to 63); + slowspr_done_in :in std_ulogic; + slowspr_val_out :out std_ulogic; + slowspr_rw_out :out std_ulogic; + slowspr_etid_out :out std_ulogic_vector(0 to 1); + slowspr_addr_out :out std_ulogic_vector(0 to 9); + slowspr_data_out :out std_ulogic_vector(64-(2**REGMODE) to 63); + slowspr_done_out :out std_ulogic; + + bx_pc_err_inbox_ecc :out std_ulogic; + bx_pc_err_outbox_ecc :out std_ulogic; + bx_pc_err_inbox_ue :out std_ulogic; + bx_pc_err_outbox_ue :out std_ulogic; + pc_bx_inj_inbox_ecc :in std_ulogic; + pc_bx_inj_outbox_ecc :in std_ulogic; + + pc_bx_trace_bus_enable : in std_ulogic; + pc_bx_debug_mux1_ctrls : in std_ulogic_vector(0 to 15); + trigger_data_in : in std_ulogic_vector(0 to 11); + debug_data_in : in std_ulogic_vector(0 to 87); + trigger_data_out : out std_ulogic_vector(0 to 11); + debug_data_out : out std_ulogic_vector(0 to 87); + + + vdd : inout power_logic; + gnd : inout power_logic; + vcs : inout power_logic; + + pc_bx_abist_di_0 :in std_ulogic_vector(0 to 3); + pc_bx_abist_g8t_bw_1 :in std_ulogic; + pc_bx_abist_g8t_bw_0 :in std_ulogic; + pc_bx_abist_waddr_0 :in std_ulogic_vector(4 to 9); + pc_bx_abist_g8t_wenb :in std_ulogic; + pc_bx_abist_raddr_0 :in std_ulogic_vector(4 to 9); + pc_bx_abist_g8t1p_renb_0 :in std_ulogic; + an_ac_lbist_ary_wrt_thru_dc :in std_ulogic; + pc_bx_abist_ena_dc :in std_ulogic; + pc_bx_abist_wl64_comp_ena :in std_ulogic; + pc_bx_abist_raw_dc_b :in std_ulogic; + pc_bx_abist_g8t_dcomp :in std_ulogic_vector(0 to 3); + + nclk :in clk_logic; + pc_bx_ccflush_dc : in std_ulogic; + pc_bx_sg_3 : in std_ulogic; + pc_bx_func_sl_thold_3 : in std_ulogic; + pc_bx_func_slp_sl_thold_3 : in std_ulogic; + pc_bx_gptr_sl_thold_3 : in std_ulogic; + pc_bx_abst_sl_thold_3 : in std_ulogic; + pc_bx_time_sl_thold_3 : in std_ulogic; + pc_bx_ary_nsl_thold_3 : in std_ulogic; + pc_bx_ary_slp_nsl_thold_3 : in std_ulogic; + pc_bx_repr_sl_thold_3 : in std_ulogic; + pc_bx_bolt_sl_thold_3 : in std_ulogic; + an_ac_scan_diag_dc : in std_ulogic; + an_ac_scan_dis_dc_b : in std_ulogic; + + pc_bx_bo_enable_3 : in std_ulogic; + pc_bx_bo_unload : in std_ulogic; + pc_bx_bo_repair : in std_ulogic; + pc_bx_bo_reset : in std_ulogic; + pc_bx_bo_shdata : in std_ulogic; + pc_bx_bo_select : in std_ulogic_vector(0 to 3); + bx_pc_bo_fail : out std_ulogic_vector(0 to 3); + bx_pc_bo_diagout : out std_ulogic_vector(0 to 3); + + + time_scan_in : in std_ulogic; + repr_scan_in : in std_ulogic; + abst_scan_in : in std_ulogic; + time_scan_out : out std_ulogic; + repr_scan_out : out std_ulogic; + abst_scan_out : out std_ulogic; + gptr_scan_in : in std_ulogic; + gptr_scan_out : out std_ulogic; + func_scan_in :in std_ulogic_vector(0 to 1); + func_scan_out :out std_ulogic_vector(0 to 1) + ); + + + + + + +END ; + +ARCHITECTURE bxq OF bxq IS + +signal ex4_mtdp_val_gated :std_ulogic; + +signal ob0_wrt_entry_ptr_d :std_ulogic_vector(0 to 1); +signal ob0_wrt_entry_ptr_q :std_ulogic_vector(0 to 1); +signal ob0_set_val :std_ulogic; +signal ob1_wrt_entry_ptr_d :std_ulogic_vector(0 to 1); +signal ob1_wrt_entry_ptr_q :std_ulogic_vector(0 to 1); +signal ob1_set_val :std_ulogic; +signal ob2_wrt_entry_ptr_d :std_ulogic_vector(0 to 1); +signal ob2_wrt_entry_ptr_q :std_ulogic_vector(0 to 1); +signal ob2_set_val :std_ulogic; +signal ob3_wrt_entry_ptr_d :std_ulogic_vector(0 to 1); +signal ob3_wrt_entry_ptr_q :std_ulogic_vector(0 to 1); +signal ob3_set_val :std_ulogic; + +signal ob_status_reg_newdata :std_ulogic_vector(0 to 17); +signal ob0_buf0_status_d :std_ulogic_vector(0 to 17); +signal ob0_buf1_status_d :std_ulogic_vector(0 to 17); +signal ob0_buf2_status_d :std_ulogic_vector(0 to 17); +signal ob0_buf3_status_d :std_ulogic_vector(0 to 17); +signal ob1_buf0_status_d :std_ulogic_vector(0 to 17); +signal ob1_buf1_status_d :std_ulogic_vector(0 to 17); +signal ob1_buf2_status_d :std_ulogic_vector(0 to 17); +signal ob1_buf3_status_d :std_ulogic_vector(0 to 17); +signal ob2_buf0_status_d :std_ulogic_vector(0 to 17); +signal ob2_buf1_status_d :std_ulogic_vector(0 to 17); +signal ob2_buf2_status_d :std_ulogic_vector(0 to 17); +signal ob2_buf3_status_d :std_ulogic_vector(0 to 17); +signal ob3_buf0_status_d :std_ulogic_vector(0 to 17); +signal ob3_buf1_status_d :std_ulogic_vector(0 to 17); +signal ob3_buf2_status_d :std_ulogic_vector(0 to 17); +signal ob3_buf3_status_d :std_ulogic_vector(0 to 17); +signal ob0_buf0_status_q :std_ulogic_vector(0 to 17); +signal ob0_buf1_status_q :std_ulogic_vector(0 to 17); +signal ob0_buf2_status_q :std_ulogic_vector(0 to 17); +signal ob0_buf3_status_q :std_ulogic_vector(0 to 17); +signal ob1_buf0_status_q :std_ulogic_vector(0 to 17); +signal ob1_buf1_status_q :std_ulogic_vector(0 to 17); +signal ob1_buf2_status_q :std_ulogic_vector(0 to 17); +signal ob1_buf3_status_q :std_ulogic_vector(0 to 17); +signal ob2_buf0_status_q :std_ulogic_vector(0 to 17); +signal ob2_buf1_status_q :std_ulogic_vector(0 to 17); +signal ob2_buf2_status_q :std_ulogic_vector(0 to 17); +signal ob2_buf3_status_q :std_ulogic_vector(0 to 17); +signal ob3_buf0_status_q :std_ulogic_vector(0 to 17); +signal ob3_buf1_status_q :std_ulogic_vector(0 to 17); +signal ob3_buf2_status_q :std_ulogic_vector(0 to 17); +signal ob3_buf3_status_q :std_ulogic_vector(0 to 17); +signal wrt_ob0_buf0_status :std_ulogic; +signal wrt_ob0_buf1_status :std_ulogic; +signal wrt_ob0_buf2_status :std_ulogic; +signal wrt_ob0_buf3_status :std_ulogic; +signal wrt_ob1_buf0_status :std_ulogic; +signal wrt_ob1_buf1_status :std_ulogic; +signal wrt_ob1_buf2_status :std_ulogic; +signal wrt_ob1_buf3_status :std_ulogic; +signal wrt_ob2_buf0_status :std_ulogic; +signal wrt_ob2_buf1_status :std_ulogic; +signal wrt_ob2_buf2_status :std_ulogic; +signal wrt_ob2_buf3_status :std_ulogic; +signal wrt_ob3_buf0_status :std_ulogic; +signal wrt_ob3_buf1_status :std_ulogic; +signal wrt_ob3_buf2_status :std_ulogic; +signal wrt_ob3_buf3_status :std_ulogic; +signal ex4_wrt_ob_status :std_ulogic_vector(0 to 15); +signal ex5_wrt_ob_status_q :std_ulogic_vector(0 to 15); +signal ex5_wrt_ob_status_gated :std_ulogic_vector(0 to 15); +signal ex6_wrt_ob_status_q :std_ulogic_vector(0 to 15); +signal ex5_ob0_buf0_flushed :std_ulogic; +signal ex5_ob0_buf1_flushed :std_ulogic; +signal ex5_ob0_buf2_flushed :std_ulogic; +signal ex5_ob0_buf3_flushed :std_ulogic; +signal ex5_ob1_buf0_flushed :std_ulogic; +signal ex5_ob1_buf1_flushed :std_ulogic; +signal ex5_ob1_buf2_flushed :std_ulogic; +signal ex5_ob1_buf3_flushed :std_ulogic; +signal ex5_ob2_buf0_flushed :std_ulogic; +signal ex5_ob2_buf1_flushed :std_ulogic; +signal ex5_ob2_buf2_flushed :std_ulogic; +signal ex5_ob2_buf3_flushed :std_ulogic; +signal ex5_ob3_buf0_flushed :std_ulogic; +signal ex5_ob3_buf1_flushed :std_ulogic; +signal ex5_ob3_buf2_flushed :std_ulogic; +signal ex5_ob3_buf3_flushed :std_ulogic; +signal ex5_ob0_flushed :std_ulogic; +signal ex5_ob1_flushed :std_ulogic; +signal ex5_ob2_flushed :std_ulogic; +signal ex5_ob3_flushed :std_ulogic; +signal ex6_ob0_buf0_flushed :std_ulogic; +signal ex6_ob0_buf1_flushed :std_ulogic; +signal ex6_ob0_buf2_flushed :std_ulogic; +signal ex6_ob0_buf3_flushed :std_ulogic; +signal ex6_ob1_buf0_flushed :std_ulogic; +signal ex6_ob1_buf1_flushed :std_ulogic; +signal ex6_ob1_buf2_flushed :std_ulogic; +signal ex6_ob1_buf3_flushed :std_ulogic; +signal ex6_ob2_buf0_flushed :std_ulogic; +signal ex6_ob2_buf1_flushed :std_ulogic; +signal ex6_ob2_buf2_flushed :std_ulogic; +signal ex6_ob2_buf3_flushed :std_ulogic; +signal ex6_ob3_buf0_flushed :std_ulogic; +signal ex6_ob3_buf1_flushed :std_ulogic; +signal ex6_ob3_buf2_flushed :std_ulogic; +signal ex6_ob3_buf3_flushed :std_ulogic; +signal ex6_ob0_flushed :std_ulogic; +signal ex6_ob1_flushed :std_ulogic; +signal ex6_ob2_flushed :std_ulogic; +signal ex6_ob3_flushed :std_ulogic; +signal ob0_buf0_status_val :std_ulogic; +signal ob0_buf1_status_val :std_ulogic; +signal ob0_buf2_status_val :std_ulogic; +signal ob0_buf3_status_val :std_ulogic; +signal ob1_buf0_status_val :std_ulogic; +signal ob1_buf1_status_val :std_ulogic; +signal ob1_buf2_status_val :std_ulogic; +signal ob1_buf3_status_val :std_ulogic; +signal ob2_buf0_status_val :std_ulogic; +signal ob2_buf1_status_val :std_ulogic; +signal ob2_buf2_status_val :std_ulogic; +signal ob2_buf3_status_val :std_ulogic; +signal ob3_buf0_status_val :std_ulogic; +signal ob3_buf1_status_val :std_ulogic; +signal ob3_buf2_status_val :std_ulogic; +signal ob3_buf3_status_val :std_ulogic; + +signal ob_rd_data :std_ulogic_vector(0 to 127); +signal ob_rd_data1_l2 :std_ulogic_vector(0 to 127); +signal ob_rd_data_cor :std_ulogic_vector(0 to 127); +signal ob_rd_data_cor_l2 :std_ulogic_vector(0 to 127); +signal ob_rd_data_ecc0 :std_ulogic_vector(0 to 6); +signal ob_rd_data_ecc1 :std_ulogic_vector(0 to 6); +signal ob_rd_data_ecc2 :std_ulogic_vector(0 to 6); +signal ob_rd_data_ecc3 :std_ulogic_vector(0 to 6); +signal ob_rd_data_ecc0_l2 :std_ulogic_vector(0 to 6); +signal ob_rd_data_ecc1_l2 :std_ulogic_vector(0 to 6); +signal ob_rd_data_ecc2_l2 :std_ulogic_vector(0 to 6); +signal ob_rd_data_ecc3_l2 :std_ulogic_vector(0 to 6); +signal ob_rd_data_nsyn0 :std_ulogic_vector(0 to 6); +signal ob_rd_data_nsyn1 :std_ulogic_vector(0 to 6); +signal ob_rd_data_nsyn2 :std_ulogic_vector(0 to 6); +signal ob_rd_data_nsyn3 :std_ulogic_vector(0 to 6); +signal ob_ary_sbe :std_ulogic_vector(0 to 3); +signal ob_ary_sbe_q :std_ulogic_vector(0 to 3); +signal ob_ary_sbe_or :std_ulogic; +signal ob_ary_ue :std_ulogic_vector(0 to 3); +signal ob_ary_ue_q :std_ulogic_vector(0 to 3); +signal ob_ary_ue_or :std_ulogic; +signal ob_datain_ecc0 :std_ulogic_vector(0 to 6); +signal ob_datain_ecc1 :std_ulogic_vector(0 to 6); +signal ob_datain_ecc2 :std_ulogic_vector(0 to 6); +signal ob_datain_ecc3 :std_ulogic_vector(0 to 6); +signal ob_wrt_entry_ptr :std_ulogic_vector(0 to 1); +signal ob_wrt_addr :std_ulogic_vector(0 to 5); +signal ob_ary_wrt_addr_l2 :std_ulogic_vector(0 to 5); +signal ob_ary_rd_addr :std_ulogic_vector(0 to 5); +signal ob_buf_status_val :std_ulogic; +signal ex3_ob_buf_status_val :std_ulogic; +signal ob_wen :std_ulogic_vector(0 to 3); +signal ob_ary_wen_l2 :std_ulogic_vector(0 to 3); +signal ob_ary_wrt_data_l2 :std_ulogic_vector(0 to 127); + +signal ob0_rd_entry_ptr_d :std_ulogic_vector(0 to 1); +signal ob0_rd_entry_ptr_q :std_ulogic_vector(0 to 1); +signal ob1_rd_entry_ptr_d :std_ulogic_vector(0 to 1); +signal ob1_rd_entry_ptr_q :std_ulogic_vector(0 to 1); +signal ob2_rd_entry_ptr_d :std_ulogic_vector(0 to 1); +signal ob2_rd_entry_ptr_q :std_ulogic_vector(0 to 1); +signal ob3_rd_entry_ptr_d :std_ulogic_vector(0 to 1); +signal ob3_rd_entry_ptr_q :std_ulogic_vector(0 to 1); + +signal ob_to_node_status_reg :std_ulogic_vector(1 to 17); +signal ob0_to_nd_status_reg :std_ulogic_vector(0 to 17); +signal ob1_to_nd_status_reg :std_ulogic_vector(0 to 17); +signal ob2_to_nd_status_reg :std_ulogic_vector(0 to 17); +signal ob3_to_nd_status_reg :std_ulogic_vector(0 to 17); + +signal ob_to_node_sel_d :std_ulogic_vector(0 to 3); +signal ob_to_node_sel_q :std_ulogic_vector(0 to 3); +signal ob_to_node_sel_sav_d :std_ulogic_vector(0 to 3); +signal ob_to_node_sel_sav_q :std_ulogic_vector(0 to 3); +signal ob_to_nd_val_t0 :std_ulogic; +signal ob_to_nd_val_t1 :std_ulogic; +signal ob_to_nd_val_t2 :std_ulogic; +signal ob_to_nd_val_t3 :std_ulogic; +signal ob_to_nd_status_reg_vals :std_ulogic_vector(0 to 3); + +signal send_ob_idle :std_ulogic; +signal send_ob_data1 :std_ulogic; +signal send_ob_data2 :std_ulogic; +signal send_ob_data3 :std_ulogic; +signal send_ob_data4 :std_ulogic; +signal send_ob_ditc :std_ulogic; +signal send_ob_wait :std_ulogic; +signal send_ob_nxt_idle :std_ulogic; +signal send_ob_nxt_data1 :std_ulogic; +signal send_ob_nxt_data2 :std_ulogic; +signal send_ob_nxt_data3 :std_ulogic; +signal send_ob_nxt_data4 :std_ulogic; +signal send_ob_nxt_ditc :std_ulogic; +signal send_ob_nxt_wait :std_ulogic; +signal ob_to_nd_done_d :std_ulogic; +signal send_ob_nxt_state :std_ulogic_vector(0 to 6); +signal send_ob_state_q :std_ulogic_vector(0 to 6); + +signal ob0_buf_done :std_ulogic; +signal ob1_buf_done :std_ulogic; +signal ob2_buf_done :std_ulogic; +signal ob3_buf_done :std_ulogic; +signal ob0_buf0_done :std_ulogic; +signal ob0_buf1_done :std_ulogic; +signal ob0_buf2_done :std_ulogic; +signal ob0_buf3_done :std_ulogic; +signal ob1_buf0_done :std_ulogic; +signal ob1_buf1_done :std_ulogic; +signal ob1_buf2_done :std_ulogic; +signal ob1_buf3_done :std_ulogic; +signal ob2_buf0_done :std_ulogic; +signal ob2_buf1_done :std_ulogic; +signal ob2_buf2_done :std_ulogic; +signal ob2_buf3_done :std_ulogic; +signal ob3_buf0_done :std_ulogic; +signal ob3_buf1_done :std_ulogic; +signal ob3_buf2_done :std_ulogic; +signal ob3_buf3_done :std_ulogic; + +signal ob_to_node_selected_thrd :std_ulogic_vector(0 to 1); +signal ob_to_node_selected_rd_ptr :std_ulogic_vector(0 to 1); +signal ob_to_node_data_ptr :std_ulogic_vector(0 to 1); +signal send_ob_seq_ptr :std_ulogic_vector(0 to 1); + +signal dly_ob_cmd_val_q :std_ulogic_vector(0 to 1); +signal dly_ob_cmd_val_d :std_ulogic_vector(0 to 1); +signal bx_lsu_ob_req_val_d :std_ulogic; +signal bx_lsu_ob_req_val_int :std_ulogic; +signal send_ob_data_val :std_ulogic; +signal send_ob_ditc_val :std_ulogic; +signal dly_ob_ditc_val_q :std_ulogic_vector(0 to 1); +signal dly_ob_ditc_val_d :std_ulogic_vector(0 to 1); +signal dly_ob_qw :std_ulogic_vector(58 to 59); +signal dly1_ob_qw :std_ulogic_vector(58 to 59); +signal ob_addr_d :std_ulogic_vector(64-real_data_add to 57); + +signal lat_st_pop :std_ulogic; +signal lat_st_pop_thrd :std_ulogic_vector(0 to 2); +signal ob_pop :std_ulogic_vector(0 to 3); +signal ob_cmd_count_incr_t0 :std_ulogic_vector(0 to 1); +signal ob_cmd_count_decr_t0 :std_ulogic_vector(0 to 1); +signal ob_cmd_count_t0_d :std_ulogic_vector(0 to 1); +signal ob_cmd_count_t0_q :std_ulogic_vector(0 to 1); +signal ob_credit_t0 :std_ulogic; +signal ob_cmd_count_incr_t1 :std_ulogic_vector(0 to 1); +signal ob_cmd_count_decr_t1 :std_ulogic_vector(0 to 1); +signal ob_cmd_count_t1_d :std_ulogic_vector(0 to 1); +signal ob_cmd_count_t1_q :std_ulogic_vector(0 to 1); +signal ob_credit_t1 :std_ulogic; +signal ob_cmd_count_incr_t2 :std_ulogic_vector(0 to 1); +signal ob_cmd_count_decr_t2 :std_ulogic_vector(0 to 1); +signal ob_cmd_count_t2_d :std_ulogic_vector(0 to 1); +signal ob_cmd_count_t2_q :std_ulogic_vector(0 to 1); +signal ob_credit_t2 :std_ulogic; +signal ob_cmd_count_incr_t3 :std_ulogic_vector(0 to 1); +signal ob_cmd_count_decr_t3 :std_ulogic_vector(0 to 1); +signal ob_cmd_count_t3_d :std_ulogic_vector(0 to 1); +signal ob_cmd_count_t3_q :std_ulogic_vector(0 to 1); +signal ob_credit_t3 :std_ulogic; +signal ob_to_nd_ready :std_ulogic; +signal ob_lsu_complete :std_ulogic; +signal lsu_cmd_avail_q :std_ulogic; +signal lsu_cmd_sent_q :std_ulogic; +signal lsu_cmd_stall_q :std_ulogic; +signal ob_cmd_sent_count_d :std_ulogic_vector(0 to 2); +signal ob_cmd_sent_count_q :std_ulogic_vector(0 to 2); + +signal wrt_ib0_buf0_status :std_ulogic; +signal wrt_ib0_buf1_status :std_ulogic; +signal wrt_ib0_buf2_status :std_ulogic; +signal wrt_ib0_buf3_status :std_ulogic; +signal wrt_ib1_buf0_status :std_ulogic; +signal wrt_ib1_buf1_status :std_ulogic; +signal wrt_ib1_buf2_status :std_ulogic; +signal wrt_ib1_buf3_status :std_ulogic; +signal wrt_ib2_buf0_status :std_ulogic; +signal wrt_ib2_buf1_status :std_ulogic; +signal wrt_ib2_buf2_status :std_ulogic; +signal wrt_ib2_buf3_status :std_ulogic; +signal wrt_ib3_buf0_status :std_ulogic; +signal wrt_ib3_buf1_status :std_ulogic; +signal wrt_ib3_buf2_status :std_ulogic; +signal wrt_ib3_buf3_status :std_ulogic; +signal ib0_incr_ptr :std_ulogic; +signal ib1_incr_ptr :std_ulogic; +signal ib2_incr_ptr :std_ulogic; +signal ib3_incr_ptr :std_ulogic; +signal ib0_decr_ptr :std_ulogic; +signal ib1_decr_ptr :std_ulogic; +signal ib2_decr_ptr :std_ulogic; +signal ib3_decr_ptr :std_ulogic; +signal ib0_decr_ptr_by2 :std_ulogic; +signal ib1_decr_ptr_by2 :std_ulogic; +signal ib2_decr_ptr_by2 :std_ulogic; +signal ib3_decr_ptr_by2 :std_ulogic; +signal ib0_decr_ptr_by3 :std_ulogic; +signal ib1_decr_ptr_by3 :std_ulogic; +signal ib2_decr_ptr_by3 :std_ulogic; +signal ib3_decr_ptr_by3 :std_ulogic; +signal ex4_wrt_ib_status :std_ulogic_vector(0 to 15); +signal ex5_wrt_ib_status_q :std_ulogic_vector(0 to 15); +signal ex5_wrt_ib_status_gated :std_ulogic_vector(0 to 15); +signal ex6_wrt_ib_status_q :std_ulogic_vector(0 to 15); +signal ex5_ib0_buf0_flushed :std_ulogic; +signal ex5_ib0_buf1_flushed :std_ulogic; +signal ex5_ib0_buf2_flushed :std_ulogic; +signal ex5_ib0_buf3_flushed :std_ulogic; +signal ex5_ib1_buf0_flushed :std_ulogic; +signal ex5_ib1_buf1_flushed :std_ulogic; +signal ex5_ib1_buf2_flushed :std_ulogic; +signal ex5_ib1_buf3_flushed :std_ulogic; +signal ex5_ib2_buf0_flushed :std_ulogic; +signal ex5_ib2_buf1_flushed :std_ulogic; +signal ex5_ib2_buf2_flushed :std_ulogic; +signal ex5_ib2_buf3_flushed :std_ulogic; +signal ex5_ib3_buf0_flushed :std_ulogic; +signal ex5_ib3_buf1_flushed :std_ulogic; +signal ex5_ib3_buf2_flushed :std_ulogic; +signal ex5_ib3_buf3_flushed :std_ulogic; +signal ex4_ib0_flushed :std_ulogic; +signal ex4_ib1_flushed :std_ulogic; +signal ex4_ib2_flushed :std_ulogic; +signal ex4_ib3_flushed :std_ulogic; +signal ex5_ib0_flushed :std_ulogic; +signal ex5_ib1_flushed :std_ulogic; +signal ex5_ib2_flushed :std_ulogic; +signal ex5_ib3_flushed :std_ulogic; +signal ex6_ib0_buf0_flushed :std_ulogic; +signal ex6_ib0_buf1_flushed :std_ulogic; +signal ex6_ib0_buf2_flushed :std_ulogic; +signal ex6_ib0_buf3_flushed :std_ulogic; +signal ex6_ib1_buf0_flushed :std_ulogic; +signal ex6_ib1_buf1_flushed :std_ulogic; +signal ex6_ib1_buf2_flushed :std_ulogic; +signal ex6_ib1_buf3_flushed :std_ulogic; +signal ex6_ib2_buf0_flushed :std_ulogic; +signal ex6_ib2_buf1_flushed :std_ulogic; +signal ex6_ib2_buf2_flushed :std_ulogic; +signal ex6_ib2_buf3_flushed :std_ulogic; +signal ex6_ib3_buf0_flushed :std_ulogic; +signal ex6_ib3_buf1_flushed :std_ulogic; +signal ex6_ib3_buf2_flushed :std_ulogic; +signal ex6_ib3_buf3_flushed :std_ulogic; +signal ex6_ib0_flushed :std_ulogic; +signal ex6_ib1_flushed :std_ulogic; +signal ex6_ib2_flushed :std_ulogic; +signal ex6_ib3_flushed :std_ulogic; +signal ib_t0_pop_d :std_ulogic; +signal ib_t1_pop_d :std_ulogic; +signal ib_t2_pop_d :std_ulogic; +signal ib_t3_pop_d :std_ulogic; + +signal ib0_buf0_val_d :std_ulogic; +signal ib0_buf1_val_d :std_ulogic; +signal ib0_buf2_val_d :std_ulogic; +signal ib0_buf3_val_d :std_ulogic; +signal ib1_buf0_val_d :std_ulogic; +signal ib1_buf1_val_d :std_ulogic; +signal ib1_buf2_val_d :std_ulogic; +signal ib1_buf3_val_d :std_ulogic; +signal ib2_buf0_val_d :std_ulogic; +signal ib2_buf1_val_d :std_ulogic; +signal ib2_buf2_val_d :std_ulogic; +signal ib2_buf3_val_d :std_ulogic; +signal ib3_buf0_val_d :std_ulogic; +signal ib3_buf1_val_d :std_ulogic; +signal ib3_buf2_val_d :std_ulogic; +signal ib3_buf3_val_d :std_ulogic; +signal ib0_buf0_val_q :std_ulogic; +signal ib0_buf1_val_q :std_ulogic; +signal ib0_buf2_val_q :std_ulogic; +signal ib0_buf3_val_q :std_ulogic; +signal ib1_buf0_val_q :std_ulogic; +signal ib1_buf1_val_q :std_ulogic; +signal ib1_buf2_val_q :std_ulogic; +signal ib1_buf3_val_q :std_ulogic; +signal ib2_buf0_val_q :std_ulogic; +signal ib2_buf1_val_q :std_ulogic; +signal ib2_buf2_val_q :std_ulogic; +signal ib2_buf3_val_q :std_ulogic; +signal ib3_buf0_val_q :std_ulogic; +signal ib3_buf1_val_q :std_ulogic; +signal ib3_buf2_val_q :std_ulogic; +signal ib3_buf3_val_q :std_ulogic; +signal ib0_rd_val_reg :std_ulogic; +signal ib1_rd_val_reg :std_ulogic; +signal ib2_rd_val_reg :std_ulogic; +signal ib3_rd_val_reg :std_ulogic; +signal ex4_ib_rd_status_reg :std_ulogic; +signal ex4_ib_val_save :std_ulogic; +signal ex5_ib_val_save_q :std_ulogic; +signal ex6_ib_val_save_q :std_ulogic; +signal ib_empty_d :std_ulogic_vector(0 to 3); +signal quiesce_d :std_ulogic_vector(0 to 3); + +signal ex3_data_w0_sel :std_ulogic_vector(0 to 3); +signal ex3_data_w1_sel :std_ulogic_vector(0 to 3); +signal ex3_data_w2_sel :std_ulogic_vector(0 to 3); +signal ex3_data_w3_sel :std_ulogic_vector(0 to 3); +signal ex3_data_sel_status :std_ulogic; +signal ex3_inbox_data :std_ulogic_vector(0 to 127); +signal ex4_inbox_data :std_ulogic_vector(0 to 127); +signal ex5_inbox_data_cor :std_ulogic_vector(0 to 127); + +signal ib0_buf0_set_val :std_ulogic; +signal ib0_buf1_set_val :std_ulogic; +signal ib0_buf2_set_val :std_ulogic; +signal ib0_buf3_set_val :std_ulogic; +signal ib1_buf0_set_val :std_ulogic; +signal ib1_buf1_set_val :std_ulogic; +signal ib1_buf2_set_val :std_ulogic; +signal ib1_buf3_set_val :std_ulogic; +signal ib2_buf0_set_val :std_ulogic; +signal ib2_buf1_set_val :std_ulogic; +signal ib2_buf2_set_val :std_ulogic; +signal ib2_buf3_set_val :std_ulogic; +signal ib3_buf0_set_val :std_ulogic; +signal ib3_buf1_set_val :std_ulogic; +signal ib3_buf2_set_val :std_ulogic; +signal ib3_buf3_set_val :std_ulogic; +signal ib0_buf0_reset_val :std_ulogic; +signal ib0_buf1_reset_val :std_ulogic; +signal ib0_buf2_reset_val :std_ulogic; +signal ib0_buf3_reset_val :std_ulogic; +signal ib1_buf0_reset_val :std_ulogic; +signal ib1_buf1_reset_val :std_ulogic; +signal ib1_buf2_reset_val :std_ulogic; +signal ib1_buf3_reset_val :std_ulogic; +signal ib2_buf0_reset_val :std_ulogic; +signal ib2_buf1_reset_val :std_ulogic; +signal ib2_buf2_reset_val :std_ulogic; +signal ib2_buf3_reset_val :std_ulogic; +signal ib3_buf0_reset_val :std_ulogic; +signal ib3_buf1_reset_val :std_ulogic; +signal ib3_buf2_reset_val :std_ulogic; +signal ib3_buf3_reset_val :std_ulogic; + +signal ib0_rd_entry_ptr_d :std_ulogic_vector(0 to 1); +signal ib1_rd_entry_ptr_d :std_ulogic_vector(0 to 1); +signal ib2_rd_entry_ptr_d :std_ulogic_vector(0 to 1); +signal ib3_rd_entry_ptr_d :std_ulogic_vector(0 to 1); +signal ib0_rd_entry_ptr_q :std_ulogic_vector(0 to 1); +signal ib1_rd_entry_ptr_q :std_ulogic_vector(0 to 1); +signal ib2_rd_entry_ptr_q :std_ulogic_vector(0 to 1); +signal ib3_rd_entry_ptr_q :std_ulogic_vector(0 to 1); +signal ib0_rd_entry_ptr_dly_q :std_ulogic_vector(0 to 1); +signal ib1_rd_entry_ptr_dly_q :std_ulogic_vector(0 to 1); +signal ib2_rd_entry_ptr_dly_q :std_ulogic_vector(0 to 1); +signal ib3_rd_entry_ptr_dly_q :std_ulogic_vector(0 to 1); + signal ib_rd_entry_ptr :std_ulogic_vector(0 to 1); + +signal ib_ary_rd_addr :std_ulogic_vector(0 to 5); +signal ib_wen :std_ulogic; +signal ib_ary_wen :std_ulogic_vector(0 to 3); +signal ib_ary_wrt_addr :std_ulogic_vector(0 to 5); +signal ib_rd_data :std_ulogic_vector(0 to 127); +signal ib_rd_data_cor :std_ulogic_vector(0 to 127); +signal ib_rd_data_ecc0 :std_ulogic_vector(0 to 6); +signal ib_rd_data_ecc1 :std_ulogic_vector(0 to 6); +signal ib_rd_data_ecc2 :std_ulogic_vector(0 to 6); +signal ib_rd_data_ecc3 :std_ulogic_vector(0 to 6); +signal ex3_ib_data_ecc0 :std_ulogic_vector(0 to 6); +signal ex3_ib_data_ecc1 :std_ulogic_vector(0 to 6); +signal ex3_ib_data_ecc2 :std_ulogic_vector(0 to 6); +signal ex3_ib_data_ecc3 :std_ulogic_vector(0 to 6); +signal ex4_ib_data_ecc0 :std_ulogic_vector(0 to 6); +signal ex4_ib_data_ecc1 :std_ulogic_vector(0 to 6); +signal ex4_ib_data_ecc2 :std_ulogic_vector(0 to 6); +signal ex4_ib_data_ecc3 :std_ulogic_vector(0 to 6); +signal ib_rd_data_nsyn0 :std_ulogic_vector(0 to 6); +signal ib_rd_data_nsyn1 :std_ulogic_vector(0 to 6); +signal ib_rd_data_nsyn2 :std_ulogic_vector(0 to 6); +signal ib_rd_data_nsyn3 :std_ulogic_vector(0 to 6); +signal ib_datain_ecc0 :std_ulogic_vector(0 to 6); +signal ib_datain_ecc1 :std_ulogic_vector(0 to 6); +signal ib_datain_ecc2 :std_ulogic_vector(0 to 6); +signal ib_datain_ecc3 :std_ulogic_vector(0 to 6); +signal ex4_ib_ecc_val :std_ulogic; +signal ex5_ib_ecc_val :std_ulogic; +signal ib_ary_ue_or :std_ulogic; +signal ib_ary_ue :std_ulogic_vector(0 to 3); +signal ib_ary_ue_q :std_ulogic_vector(0 to 3); +signal ib_ary_sbe_or :std_ulogic; +signal ib_ary_sbe :std_ulogic_vector(0 to 3); +signal ib_ary_sbe_q :std_ulogic_vector(0 to 3); +signal ob_abst_scan_out :std_ulogic; +signal ib_abst_scan_out :std_ulogic; +signal ob_time_scan_out :std_ulogic; +signal ib_time_scan_out :std_ulogic; +signal ob_repr_scan_out :std_ulogic; + + +signal lat_reld_data_val :std_ulogic; +signal lat_reld_ditc :std_ulogic; +signal lat_reld_ecc_err :std_ulogic; +signal reld_data_val_dminus2 :std_ulogic; +signal reld_data_val_dminus1 :std_ulogic; +signal reld_data_val :std_ulogic; +signal reld_data_val_dplus1 :std_ulogic; +signal lat_reld_core_tag :std_ulogic_vector(3 to 4); +signal reld_core_tag_dminus1 :std_ulogic_vector(3 to 4); +signal reld_core_tag :std_ulogic_vector(3 to 4); +signal reld_core_tag_dplus1 :std_ulogic_vector(3 to 4); +signal lat_reld_qw :std_ulogic_vector(58 to 59); +signal reld_qw_dminus1 :std_ulogic_vector(58 to 59); +signal reld_qw :std_ulogic_vector(58 to 59); +signal lat_reld_data :std_ulogic_vector(0 to 127); + +signal ib0_wrt_entry_ptr_d :std_ulogic_vector(0 to 1); +signal ib1_wrt_entry_ptr_d :std_ulogic_vector(0 to 1); +signal ib2_wrt_entry_ptr_d :std_ulogic_vector(0 to 1); +signal ib3_wrt_entry_ptr_d :std_ulogic_vector(0 to 1); +signal ib0_wrt_entry_ptr_q :std_ulogic_vector(0 to 1); +signal ib1_wrt_entry_ptr_q :std_ulogic_vector(0 to 1); +signal ib2_wrt_entry_ptr_q :std_ulogic_vector(0 to 1); +signal ib3_wrt_entry_ptr_q :std_ulogic_vector(0 to 1); +signal ib0_wrt_entry_ptr :std_ulogic_vector(0 to 1); +signal ib1_wrt_entry_ptr :std_ulogic_vector(0 to 1); +signal ib2_wrt_entry_ptr :std_ulogic_vector(0 to 1); +signal ib3_wrt_entry_ptr :std_ulogic_vector(0 to 1); +signal ib0_wrt_entry_ptr_minus1 :std_ulogic_vector(0 to 1); +signal ib1_wrt_entry_ptr_minus1 :std_ulogic_vector(0 to 1); +signal ib2_wrt_entry_ptr_minus1 :std_ulogic_vector(0 to 1); +signal ib3_wrt_entry_ptr_minus1 :std_ulogic_vector(0 to 1); +signal dec_ib0_wrt_entry_ptr :std_ulogic; +signal dec_ib1_wrt_entry_ptr :std_ulogic; +signal dec_ib2_wrt_entry_ptr :std_ulogic; +signal dec_ib3_wrt_entry_ptr :std_ulogic; +signal ib0_wrt_data_ctr_d :std_ulogic_vector(0 to 1); +signal ib1_wrt_data_ctr_d :std_ulogic_vector(0 to 1); +signal ib2_wrt_data_ctr_d :std_ulogic_vector(0 to 1); +signal ib3_wrt_data_ctr_d :std_ulogic_vector(0 to 1); +signal ib0_wrt_data_ctr_q :std_ulogic_vector(0 to 1); +signal ib1_wrt_data_ctr_q :std_ulogic_vector(0 to 1); +signal ib2_wrt_data_ctr_q :std_ulogic_vector(0 to 1); +signal ib3_wrt_data_ctr_q :std_ulogic_vector(0 to 1); + + +signal ib_wrt_thrd :std_ulogic_vector(0 to 1); +signal ib_wrt_entry_pointer :std_ulogic_vector(0 to 1); + +signal ib0_set_val :std_ulogic; +signal ib1_set_val :std_ulogic; +signal ib2_set_val :std_ulogic; +signal ib3_set_val :std_ulogic; +signal ib0_set_val_q :std_ulogic; +signal ib1_set_val_q :std_ulogic; +signal ib2_set_val_q :std_ulogic; +signal ib3_set_val_q :std_ulogic; +signal ib0_ecc_err_d :std_ulogic; +signal ib1_ecc_err_d :std_ulogic; +signal ib2_ecc_err_d :std_ulogic; +signal ib3_ecc_err_d :std_ulogic; +signal ib0_ecc_err_q :std_ulogic; +signal ib1_ecc_err_q :std_ulogic; +signal ib2_ecc_err_q :std_ulogic; +signal ib3_ecc_err_q :std_ulogic; + +signal inbox_ecc_err_q :std_ulogic; +signal inbox_ue_q :std_ulogic; +signal outbox_ecc_err_q :std_ulogic; +signal outbox_ue_q :std_ulogic; + +signal ob0_buf0_clr :std_ulogic; +signal ob0_buf1_clr :std_ulogic; +signal ob0_buf2_clr :std_ulogic; +signal ob0_buf3_clr :std_ulogic; +signal ob1_buf0_clr :std_ulogic; +signal ob1_buf1_clr :std_ulogic; +signal ob1_buf2_clr :std_ulogic; +signal ob1_buf3_clr :std_ulogic; +signal ob2_buf0_clr :std_ulogic; +signal ob2_buf1_clr :std_ulogic; +signal ob2_buf2_clr :std_ulogic; +signal ob2_buf3_clr :std_ulogic; +signal ob3_buf0_clr :std_ulogic; +signal ob3_buf1_clr :std_ulogic; +signal ob3_buf2_clr :std_ulogic; +signal ob3_buf3_clr :std_ulogic; +signal ob0_buf0_status_avail :std_ulogic; +signal ob0_buf1_status_avail :std_ulogic; +signal ob0_buf2_status_avail :std_ulogic; +signal ob0_buf3_status_avail :std_ulogic; +signal ob1_buf0_status_avail :std_ulogic; +signal ob1_buf1_status_avail :std_ulogic; +signal ob1_buf2_status_avail :std_ulogic; +signal ob1_buf3_status_avail :std_ulogic; +signal ob2_buf0_status_avail :std_ulogic; +signal ob2_buf1_status_avail :std_ulogic; +signal ob2_buf2_status_avail :std_ulogic; +signal ob2_buf3_status_avail :std_ulogic; +signal ob3_buf0_status_avail :std_ulogic; +signal ob3_buf1_status_avail :std_ulogic; +signal ob3_buf2_status_avail :std_ulogic; +signal ob3_buf3_status_avail :std_ulogic; +signal ob_buf_status_avail_d :std_ulogic_vector(0 to 15); +signal ob_buf_status_avail_q :std_ulogic_vector(0 to 15); + +signal my_ccr2_en_ditc_q :std_ulogic; +signal my_ex3_flush :std_ulogic; +signal my_ex3_flush_q :std_ulogic_vector(0 to 3); +signal my_ex4_flush_q :std_ulogic_vector(0 to 3); +signal my_ex5_flush_q :std_ulogic_vector(0 to 3); +signal my_ex6_flush_q :std_ulogic_vector(0 to 3); +signal my_ex4_stg_flush :std_ulogic; +signal my_ex5_stg_flush :std_ulogic; +signal my_ex6_stg_flush :std_ulogic; +signal ex2_mfdp_val_q :std_ulogic; +signal ex3_mfdp_val_q :std_ulogic; +signal ex4_mfdp_val_q :std_ulogic; +signal ex5_mfdp_val_q :std_ulogic; +signal ex6_mfdp_val_q :std_ulogic; +signal ex3_mtdp_val :std_ulogic; +signal ex2_mtdp_val_q :std_ulogic; +signal ex3_mtdp_val_q :std_ulogic; +signal ex2_ipc_thrd_q :std_ulogic_vector(0 to 1); +signal ex3_ipc_thrd_q :std_ulogic_vector(0 to 1); +signal ex3_ipc_ba_q :std_ulogic_vector(0 to 4); +signal ex3_ipc_sz_q :std_ulogic_vector(0 to 1); +signal ex4_mtdp_val_q :std_ulogic; +signal ex5_mtdp_val_q :std_ulogic; +signal ex6_mtdp_val_q :std_ulogic; +signal ex7_mtdp_val_q :std_ulogic; +signal ex4_ipc_thrd_q :std_ulogic_vector(0 to 1); +signal ex5_ipc_thrd_q :std_ulogic_vector(0 to 1); +signal ex6_ipc_thrd_q :std_ulogic_vector(0 to 1); +signal ex4_ipc_ba_q :std_ulogic_vector(0 to 4); +signal ex4_ipc_sz_q :std_ulogic_vector(0 to 1); +signal ex3_mtdp_cr_status :std_ulogic; +signal ex4_mtdp_cr_status :std_ulogic; +signal ex3_mfdp_cr_status :std_ulogic; +signal ex4_mfdp_cr_status_i :std_ulogic; + +signal ditc_addr_sel :std_ulogic; +signal ditc_addr_wen :std_ulogic; +signal ditc_addr_t0_wen :std_ulogic; +signal ditc_addr_t1_wen :std_ulogic; +signal ditc_addr_t2_wen :std_ulogic; +signal ditc_addr_t3_wen :std_ulogic; +signal ditc_addr_t0_d :std_ulogic_vector(64-real_data_add to 57); +signal ditc_addr_t1_d :std_ulogic_vector(64-real_data_add to 57); +signal ditc_addr_t2_d :std_ulogic_vector(64-real_data_add to 57); +signal ditc_addr_t3_d :std_ulogic_vector(64-real_data_add to 57); +signal ditc_addr_t0_q :std_ulogic_vector(64-real_data_add to 57); +signal ditc_addr_t1_q :std_ulogic_vector(64-real_data_add to 57); +signal ditc_addr_t2_q :std_ulogic_vector(64-real_data_add to 57); +signal ditc_addr_t3_q :std_ulogic_vector(64-real_data_add to 57); +signal ditc_addr_reg :std_ulogic_vector(64-(2**REGMODE) to 63); +signal ditc_addr_rd_val :std_ulogic; +signal xu_slowspr_data_d :std_ulogic_vector(64-(2**REGMODE) to 63); +signal xu_slowspr_done_d :std_ulogic; +signal xu_slowspr_val_d :std_ulogic; +signal xu_slowspr_rw_d :std_ulogic; +signal xu_slowspr_etid_d :std_ulogic_vector(0 to 1); +signal xu_slowspr_addr_d :std_ulogic_vector(0 to 9); +signal bx_slowspr_val_q :std_ulogic; +signal bx_slowspr_rw_q :std_ulogic; +signal bx_slowspr_etid_q :std_ulogic_vector(0 to 1); +signal bx_slowspr_addr_q :std_ulogic_vector(0 to 9); +signal bx_slowspr_data_q :std_ulogic_vector(64-(2**REGMODE) to 63); +signal bx_slowspr_done_q :std_ulogic; + +signal ob_rd_logic_act :std_ulogic; +signal ob_rd_logic_act_d :std_ulogic; +signal ob_rd_logic_act_q :std_ulogic; +signal mtdp_ex3_to_7_val :std_ulogic; +signal ib_buf_val_act :std_ulogic; +signal dp_op_val :std_ulogic; + +signal abist_di_0 :std_ulogic_vector(0 to 3); +signal abist_g8t_bw_1 :std_ulogic; +signal abist_g8t_bw_0 :std_ulogic; +signal abist_waddr_0 :std_ulogic_vector(4 to 9); +signal abist_g8t_wenb :std_ulogic; +signal abist_raddr_0 :std_ulogic_vector(4 to 9); +signal abist_g8t1p_renb_0 :std_ulogic; +signal abist_wl64_comp_ena :std_ulogic; +signal abist_g8t_dcomp :std_ulogic_vector(0 to 3); + +signal dbg_group0_d :std_ulogic_vector(0 to 17); +signal dbg_group0_q :std_ulogic_vector(0 to 17); +signal dbg_group0 :std_ulogic_vector(0 to 87); +signal dbg_group1 :std_ulogic_vector(0 to 87); +signal dbg_group2 :std_ulogic_vector(0 to 87); +signal dbg_group3 :std_ulogic_vector(0 to 87); +signal trg_group0 :std_ulogic_vector(0 to 11); +signal trg_group1 :std_ulogic_vector(0 to 11); +signal trg_group2 :std_ulogic_vector(0 to 11); +signal trg_group3 :std_ulogic_vector(0 to 11); +signal debug_mux1_ctrls_q :std_ulogic_vector(0 to 15); +signal debug_mux_out_d :std_ulogic_vector(0 to 87); +signal trigger_mux_out_d :std_ulogic_vector(0 to 11); +signal trace_bus_enable_q :std_ulogic; +signal spare0_l2 :std_ulogic_vector(0 to 7); +signal spare1_l2 :std_ulogic_vector(0 to 3); + +signal sg_2 :std_ulogic; +signal func_sl_thold_2 :std_ulogic; +signal func_slp_sl_thold_2 :std_ulogic; +signal abst_sl_thold_2 :std_ulogic; +signal time_sl_thold_2 :std_ulogic; +signal ary_nsl_thold_2 :std_ulogic; +signal ary_slp_nsl_thold_2 :std_ulogic; +signal gptr_sl_thold_2 :std_ulogic; +signal repr_sl_thold_2 :std_ulogic; +signal bolt_sl_thold_2 :std_ulogic; +signal bolt_enable_2 :std_ulogic; +signal func_sl_thold_1 :std_ulogic; +signal func_slp_sl_thold_1 :std_ulogic; +signal abst_sl_thold_1 :std_ulogic; +signal time_sl_thold_1 :std_ulogic; +signal ary_nsl_thold_1 :std_ulogic; +signal ary_slp_nsl_thold_1 :std_ulogic; +signal gptr_sl_thold_1 :std_ulogic; +signal repr_sl_thold_1 :std_ulogic; +signal bolt_sl_thold_1 :std_ulogic; +signal func_sl_thold_0 :std_ulogic; +signal func_slp_sl_thold_0 :std_ulogic; +signal ary_nsl_thold_0 :std_ulogic; +signal ary_slp_nsl_thold_0 :std_ulogic; +signal abst_sl_thold_0 :std_ulogic; +signal time_sl_thold_0 :std_ulogic; +signal repr_sl_thold_0 :std_ulogic; +signal gptr_sl_thold_0 :std_ulogic; +signal bolt_sl_thold_0 :std_ulogic; +signal slat_force :std_ulogic; +signal time_slat_thold_b :std_ulogic; +signal time_slat_d2clk :std_ulogic; +signal time_slat_lclk :clk_logic; +signal time_scan_out_stg :std_ulogic; +signal repr_slat_thold_b :std_ulogic; +signal repr_slat_d2clk :std_ulogic; +signal repr_slat_lclk :clk_logic; + +signal clkoff_dc_b :std_ulogic; +signal d_mode_dc :std_ulogic; +signal delay_lclkr_dc :std_ulogic; +signal delay_lclkr_dc_v :std_ulogic_vector(0 to 4); +signal mpw1_dc_b :std_ulogic; +signal mpw1_dc_b_v :std_ulogic_vector(0 to 4); +signal mpw2_dc_b :std_ulogic; +signal ary0_clkoff_dc_b :std_ulogic; +signal ary0_d_mode_dc :std_ulogic; +signal ary0_delay_lclkr_dc_v :std_ulogic_vector(0 to 4); +signal ary0_mpw1_dc_b_v :std_ulogic_vector(0 to 4); +signal ary0_mpw2_dc_b :std_ulogic; +signal ary1_clkoff_dc_b :std_ulogic; +signal ary1_d_mode_dc :std_ulogic; +signal ary1_delay_lclkr_dc_v :std_ulogic_vector(0 to 4); +signal ary1_mpw1_dc_b_v :std_ulogic_vector(0 to 4); +signal ary1_mpw2_dc_b :std_ulogic; +signal int1_gptr_scan_out :std_ulogic; +signal int0_gptr_scan_out :std_ulogic; +signal int_repr_scan_out :std_ulogic; +signal repr_scan_out_q :std_ulogic; +signal repr_scan_in_q :std_ulogic; +signal int_gptr_scan_out :std_ulogic; +signal time_scan_in_q :std_ulogic; + +signal ob_err_inj_q :std_ulogic; +signal ib_err_inj_q :std_ulogic; +signal ob_ary_wrt_data_0 :std_ulogic; +signal lat_reld_data_0 :std_ulogic; + +signal sg_1 : std_ulogic; +signal sg_0 : std_ulogic; +signal func_sl_force : std_ulogic; +signal func_sl_thold_0_b : std_ulogic; +signal func_slp_sl_force : std_ulogic; +signal func_slp_sl_thold_0_b : std_ulogic; +signal abst_sl_force : std_ulogic; +signal abst_sl_thold_0_b : std_ulogic; + +signal tidn : std_ulogic; +signal unused :std_ulogic_vector(0 to 23); + +constant my_ex3_flush_offset : natural := 0; +constant my_ex4_flush_offset : natural :=my_ex3_flush_offset + my_ex3_flush_q'length; +constant my_ex5_flush_offset : natural :=my_ex4_flush_offset + my_ex4_flush_q'length; +constant my_ex6_flush_offset : natural :=my_ex5_flush_offset + my_ex5_flush_q'length; +constant my_ccr2_en_ditc_offset : natural :=my_ex6_flush_offset + my_ex6_flush_q'length; +constant ex2_mtdp_val_offset : natural :=my_ccr2_en_ditc_offset + 1; +constant ex3_mtdp_val_offset : natural :=ex2_mtdp_val_offset + 1; +constant ex4_mtdp_val_offset : natural :=ex3_mtdp_val_offset + 1; +constant ex5_mtdp_val_offset : natural :=ex4_mtdp_val_offset + 1; +constant ex6_mtdp_val_offset : natural :=ex5_mtdp_val_offset + 1; +constant ex7_mtdp_val_offset : natural :=ex6_mtdp_val_offset + 1; +constant ex2_mfdp_val_offset : natural :=ex7_mtdp_val_offset + 1; +constant ex3_mfdp_val_offset : natural :=ex2_mfdp_val_offset + 1; +constant ex4_mfdp_val_offset : natural :=ex3_mfdp_val_offset + 1; +constant ex5_mfdp_val_offset : natural :=ex4_mfdp_val_offset + 1; +constant ex6_mfdp_val_offset : natural :=ex5_mfdp_val_offset + 1; +constant ex2_ipc_thrd_offset : natural :=ex6_mfdp_val_offset + 1; +constant ex3_ipc_thrd_offset : natural :=ex2_ipc_thrd_offset + ex2_ipc_thrd_q'length; +constant ex3_ipc_ba_offset : natural :=ex3_ipc_thrd_offset + ex3_ipc_thrd_q'length; +constant ex3_ipc_sz_offset : natural :=ex3_ipc_ba_offset + ex3_ipc_ba_q'length; +constant bx_slowspr_val_offset : natural :=ex3_ipc_sz_offset + ex3_ipc_sz_q'length; +constant bx_slowspr_rw_offset : natural :=bx_slowspr_val_offset + 1; +constant bx_slowspr_etid_offset : natural :=bx_slowspr_rw_offset + 1; +constant bx_slowspr_addr_offset : natural :=bx_slowspr_etid_offset + bx_slowspr_etid_q'length; +constant bx_slowspr_data_offset : natural :=bx_slowspr_addr_offset + bx_slowspr_addr_q'length; +constant bx_slowspr_done_offset : natural :=bx_slowspr_data_offset + bx_slowspr_data_q'length; +constant xu_slowspr_val_offset : natural :=bx_slowspr_done_offset + 1; +constant xu_slowspr_rw_offset : natural :=xu_slowspr_val_offset + 1; +constant xu_slowspr_etid_offset : natural :=xu_slowspr_rw_offset + 1; +constant xu_slowspr_addr_offset : natural :=xu_slowspr_etid_offset + xu_slowspr_etid_d'length; +constant xu_slowspr_data_offset : natural :=xu_slowspr_addr_offset + xu_slowspr_addr_d'length; +constant xu_slowspr_done_offset : natural :=xu_slowspr_data_offset + xu_slowspr_data_d'length; +constant ditc_addr_t0_offset : natural :=xu_slowspr_done_offset + 1; +constant ditc_addr_t1_offset : natural :=ditc_addr_t0_offset + ditc_addr_t0_d'length; +constant ditc_addr_t2_offset : natural :=ditc_addr_t1_offset + ditc_addr_t1_d'length; +constant ditc_addr_t3_offset : natural :=ditc_addr_t2_offset + ditc_addr_t2_d'length; +constant ob0_wrt_entry_ptr_offset : natural :=ditc_addr_t3_offset + ditc_addr_t3_d'length; +constant ob1_wrt_entry_ptr_offset : natural :=ob0_wrt_entry_ptr_offset + ob0_wrt_entry_ptr_q'length; +constant ob2_wrt_entry_ptr_offset : natural :=ob1_wrt_entry_ptr_offset + ob1_wrt_entry_ptr_q'length; +constant ob3_wrt_entry_ptr_offset : natural :=ob2_wrt_entry_ptr_offset + ob2_wrt_entry_ptr_q'length; +constant ob_rd_logic_act_offset : natural :=ob3_wrt_entry_ptr_offset + ob3_wrt_entry_ptr_q'length; +constant ex5_wrt_ob_status_offset : natural :=ob_rd_logic_act_offset + 1; +constant ex6_wrt_ob_status_offset : natural :=ex5_wrt_ob_status_offset + ex5_wrt_ob_status_q'length; +constant ob0_buf0_status_offset : natural :=ex6_wrt_ob_status_offset + ex6_wrt_ob_status_q'length; +constant ob0_buf1_status_offset : natural :=ob0_buf0_status_offset + ob0_buf0_status_q'length; +constant ob0_buf2_status_offset : natural :=ob0_buf1_status_offset + ob0_buf1_status_q'length; +constant ob0_buf3_status_offset : natural :=ob0_buf2_status_offset + ob0_buf2_status_q'length; +constant ob1_buf0_status_offset : natural :=ob0_buf3_status_offset + ob0_buf3_status_q'length; +constant ob1_buf1_status_offset : natural :=ob1_buf0_status_offset + ob1_buf0_status_q'length; +constant ob1_buf2_status_offset : natural :=ob1_buf1_status_offset + ob1_buf1_status_q'length; +constant ob1_buf3_status_offset : natural :=ob1_buf2_status_offset + ob1_buf2_status_q'length; +constant ob2_buf0_status_offset : natural :=ob1_buf3_status_offset + ob1_buf3_status_q'length; +constant ob2_buf1_status_offset : natural :=ob2_buf0_status_offset + ob2_buf0_status_q'length; +constant ob2_buf2_status_offset : natural :=ob2_buf1_status_offset + ob2_buf1_status_q'length; +constant ob2_buf3_status_offset : natural :=ob2_buf2_status_offset + ob2_buf2_status_q'length; +constant ob3_buf0_status_offset : natural :=ob2_buf3_status_offset + ob2_buf3_status_q'length; +constant ob3_buf1_status_offset : natural :=ob3_buf0_status_offset + ob3_buf0_status_q'length; +constant ob3_buf2_status_offset : natural :=ob3_buf1_status_offset + ob3_buf1_status_q'length; +constant ob3_buf3_status_offset : natural :=ob3_buf2_status_offset + ob3_buf2_status_q'length; +constant spare0_offset : natural :=ob3_buf3_status_offset + ob3_buf3_status_q'length; +constant ob_buf_status_avail_offset : natural :=spare0_offset + spare0_l2'length; +constant ex4_mtdp_cr_status_offset : natural :=ob_buf_status_avail_offset + ob_buf_status_avail_q'length; +constant ob_wrt_data_offset : natural :=ex4_mtdp_cr_status_offset + 1; +constant ob_ary_wen_offset : natural :=ob_wrt_data_offset + ob_ary_wrt_data_l2'length; +constant ob_ary_wrt_addr_offset : natural :=ob_ary_wen_offset + ob_ary_wen_l2'length; +constant ob_err_inj_offset : natural :=ob_ary_wrt_addr_offset + ob_ary_wrt_addr_l2'length; +constant ob_rd_data1_offset : natural :=ob_err_inj_offset + 1; + + +constant ob_rd_data_ecc0_offset : natural :=ob_rd_data1_offset + ob_rd_data1_l2'length; +constant ob_rd_data_ecc1_offset : natural :=ob_rd_data_ecc0_offset + ob_rd_data_ecc0'length; +constant ob_rd_data_ecc2_offset : natural :=ob_rd_data_ecc1_offset + ob_rd_data_ecc1'length; +constant ob_rd_data_ecc3_offset : natural :=ob_rd_data_ecc2_offset + ob_rd_data_ecc2'length; + + +constant ob_ary_sbe_offset : natural :=ob_rd_data_ecc3_offset + ob_rd_data_ecc3'length; +constant ob_ary_ue_offset : natural :=ob_ary_sbe_offset + ob_ary_sbe_q'length; +constant ob_rd_data_cor_offset : natural :=ob_ary_ue_offset + ob_ary_ue_q'length; +constant outbox_ecc_err_offset : natural :=ob_rd_data_cor_offset + ob_rd_data_cor'length; +constant outbox_ue_offset : natural :=outbox_ecc_err_offset + 1; +constant ob0_rd_entry_ptr_offset : natural :=outbox_ue_offset + 1; +constant ob1_rd_entry_ptr_offset : natural :=ob0_rd_entry_ptr_offset + ob0_rd_entry_ptr_q'length; +constant ob2_rd_entry_ptr_offset : natural :=ob1_rd_entry_ptr_offset + ob1_rd_entry_ptr_q'length; +constant ob3_rd_entry_ptr_offset : natural :=ob2_rd_entry_ptr_offset + ob2_rd_entry_ptr_q'length; +constant ob_to_node_sel_offset : natural :=ob3_rd_entry_ptr_offset + ob3_rd_entry_ptr_q'length; + +constant scan_right0 : natural :=ob_to_node_sel_offset + ob_to_node_sel_q'length; + +constant ob_to_node_sel_sav_offset : natural :=ob_to_node_sel_offset + ob_to_node_sel_q'length; +constant lsu_cmd_avail_offset : natural :=ob_to_node_sel_sav_offset + ob_to_node_sel_sav_q'length; +constant lsu_cmd_sent_offset : natural :=lsu_cmd_avail_offset + 1; +constant lsu_cmd_stall_offset : natural :=lsu_cmd_sent_offset + 1; +constant ob_cmd_sent_count_offset : natural :=lsu_cmd_stall_offset + 1; +constant send_ob_state_offset : natural :=ob_cmd_sent_count_offset + ob_cmd_sent_count_q'length; +constant spare1_offset : natural :=send_ob_state_offset + send_ob_state_q'length; +constant dly_ob_cmd_val_offset : natural :=spare1_offset + spare1_l2'length; +constant bxlsu_ob_req_val_offset : natural :=dly_ob_cmd_val_offset + dly_ob_cmd_val_q'length; +constant dly_ob_ditc_val_offset : natural :=bxlsu_ob_req_val_offset + 1; +constant bxlsu_ob_ditc_val_offset : natural :=dly_ob_ditc_val_offset + dly_ob_ditc_val_q'length; +constant dly_ob_qw_offset : natural :=bxlsu_ob_ditc_val_offset + 1; +constant dly1_ob_qw_offset : natural :=dly_ob_qw_offset + dly_ob_qw'length; +constant bxlsu_ob_qw_offset : natural :=dly1_ob_qw_offset + dly1_ob_qw'length; +constant bxlsu_ob_thrd_offset : natural :=bxlsu_ob_qw_offset + bx_lsu_ob_qw'length; +constant bxlsu_ob_addr_offset : natural :=bxlsu_ob_thrd_offset + bx_lsu_ob_thrd'length; +constant bxlsu_ob_dest_offset : natural :=bxlsu_ob_addr_offset + bx_lsu_ob_addr'length; +constant st_pop_offset : natural :=bxlsu_ob_dest_offset + bx_lsu_ob_dest'length; +constant st_pop_thrd_offset : natural :=st_pop_offset + 1; +constant ob_cmd_count_t0_offset : natural :=st_pop_thrd_offset + lat_st_pop_thrd'length; +constant ob_cmd_count_t1_offset : natural :=ob_cmd_count_t0_offset + ob_cmd_count_t0_q'length; +constant ob_cmd_count_t2_offset : natural :=ob_cmd_count_t1_offset + ob_cmd_count_t1_q'length; +constant ob_cmd_count_t3_offset : natural :=ob_cmd_count_t2_offset + ob_cmd_count_t2_q'length; +constant ex5_wrt_ib_status_offset : natural :=ob_cmd_count_t3_offset + ob_cmd_count_t3_q'length; +constant ex6_wrt_ib_status_offset : natural :=ex5_wrt_ib_status_offset + ex5_wrt_ib_status_q'length; +constant ipc_ib_t0_pop_offset : natural :=ex6_wrt_ib_status_offset + ex6_wrt_ib_status_q'length; +constant ipc_ib_t1_pop_offset : natural :=ipc_ib_t0_pop_offset + 1; +constant ipc_ib_t2_pop_offset : natural :=ipc_ib_t1_pop_offset + 1; +constant ipc_ib_t3_pop_offset : natural :=ipc_ib_t2_pop_offset + 1; +constant ib0_buf0_val_offset : natural :=ipc_ib_t3_pop_offset + 1; +constant ib0_buf1_val_offset : natural :=ib0_buf0_val_offset + 1; +constant ib0_buf2_val_offset : natural :=ib0_buf1_val_offset + 1; +constant ib0_buf3_val_offset : natural :=ib0_buf2_val_offset + 1; +constant ib1_buf0_val_offset : natural :=ib0_buf3_val_offset + 1; +constant ib1_buf1_val_offset : natural :=ib1_buf0_val_offset + 1; +constant ib1_buf2_val_offset : natural :=ib1_buf1_val_offset + 1; +constant ib1_buf3_val_offset : natural :=ib1_buf2_val_offset + 1; +constant ib2_buf0_val_offset : natural :=ib1_buf3_val_offset + 1; +constant ib2_buf1_val_offset : natural :=ib2_buf0_val_offset + 1; +constant ib2_buf2_val_offset : natural :=ib2_buf1_val_offset + 1; +constant ib2_buf3_val_offset : natural :=ib2_buf2_val_offset + 1; +constant ib3_buf0_val_offset : natural :=ib2_buf3_val_offset + 1; +constant ib3_buf1_val_offset : natural :=ib3_buf0_val_offset + 1; +constant ib3_buf2_val_offset : natural :=ib3_buf1_val_offset + 1; +constant ib3_buf3_val_offset : natural :=ib3_buf2_val_offset + 1; +constant ex5_ib_val_save_offset : natural :=ib3_buf3_val_offset + 1; +constant ex6_ib_val_save_offset : natural :=ex5_ib_val_save_offset + 1; +constant ib_empty_offset : natural :=ex6_ib_val_save_offset + 1; +constant quiesce_offset : natural :=ib_empty_offset + ib_empty_d'length; +constant ib0_rd_entry_ptr_offset : natural :=quiesce_offset + quiesce_d'length; +constant ib1_rd_entry_ptr_offset : natural :=ib0_rd_entry_ptr_offset + ib0_rd_entry_ptr_q'length; +constant ib2_rd_entry_ptr_offset : natural :=ib1_rd_entry_ptr_offset + ib1_rd_entry_ptr_q'length; +constant ib3_rd_entry_ptr_offset : natural :=ib2_rd_entry_ptr_offset + ib2_rd_entry_ptr_q'length; +constant ib0_rd_entry_ptr_dly_offset : natural :=ib3_rd_entry_ptr_offset + ib3_rd_entry_ptr_q'length; +constant ib1_rd_entry_ptr_dly_offset : natural :=ib0_rd_entry_ptr_dly_offset + ib0_rd_entry_ptr_dly_q'length; +constant ib2_rd_entry_ptr_dly_offset : natural :=ib1_rd_entry_ptr_dly_offset + ib1_rd_entry_ptr_dly_q'length; +constant ib3_rd_entry_ptr_dly_offset : natural :=ib2_rd_entry_ptr_dly_offset + ib2_rd_entry_ptr_dly_q'length; + + + +constant ib_err_inj_offset : natural :=ib3_rd_entry_ptr_dly_offset + ib3_rd_entry_ptr_dly_q'length; +constant ex5_inbox_data_cor_offset : natural :=ib_err_inj_offset + 1; +constant ib_ary_sbe_offset : natural :=ex5_inbox_data_cor_offset + ex5_inbox_data_cor'length; +constant ib_ary_ue_offset : natural :=ib_ary_sbe_offset + ib_ary_sbe_q'length; +constant inbox_ecc_err_offset : natural :=ib_ary_ue_offset + ib_ary_ue_q'length; +constant inbox_ue_offset : natural :=inbox_ecc_err_offset + 1; +constant ex4_ipc_thrd_offset : natural :=inbox_ue_offset + 1; +constant ex5_ipc_thrd_offset : natural :=ex4_ipc_thrd_offset + ex4_ipc_thrd_q'length; +constant ex6_ipc_thrd_offset : natural :=ex5_ipc_thrd_offset + ex5_ipc_thrd_q'length; +constant ex4_ipc_ba_offset : natural :=ex6_ipc_thrd_offset + ex6_ipc_thrd_q'length; +constant ex4_ipc_sz_offset : natural :=ex4_ipc_ba_offset + ex4_ipc_ba_q'length; +constant ex4_dp_data_offset : natural :=ex4_ipc_sz_offset + ex4_ipc_sz_q'length; +constant ex4_ib_data_ecc0_offset : natural :=ex4_dp_data_offset + ex4_inbox_data'length; +constant ex4_ib_data_ecc1_offset : natural :=ex4_ib_data_ecc0_offset + ex4_ib_data_ecc0'length; +constant ex4_ib_data_ecc2_offset : natural :=ex4_ib_data_ecc1_offset + ex4_ib_data_ecc1'length; +constant ex4_ib_data_ecc3_offset : natural :=ex4_ib_data_ecc2_offset + ex4_ib_data_ecc2'length; +constant ex4_mfdp_cr_status_offset : natural :=ex4_ib_data_ecc3_offset + ex4_ib_data_ecc3'length; +constant ex5_ib_ecc_val_offset : natural :=ex4_mfdp_cr_status_offset + 1; +constant reld_data_val_offset : natural :=ex5_ib_ecc_val_offset + 1; +constant reld_data_val_dplus1_offset : natural :=reld_data_val_offset + 1; +constant reld_ditc_offset : natural :=reld_data_val_dplus1_offset + 1; +constant reld_ecc_err_offset : natural :=reld_ditc_offset + 1; +constant reld_data_val_dminus2_offset : natural :=reld_ecc_err_offset + 1; +constant reld_data_val_dminus1_offset : natural :=reld_data_val_dminus2_offset + 1; +constant reld_core_tag_dminus2_offset : natural :=reld_data_val_dminus1_offset + 1; +constant reld_core_tag_dminus1_offset : natural :=reld_core_tag_dminus2_offset + lat_reld_core_tag'length; +constant reld_core_tag_offset : natural :=reld_core_tag_dminus1_offset + reld_core_tag_dminus1'length; +constant reld_core_tag_dplus1_offset : natural :=reld_core_tag_offset + reld_core_tag'length; +constant reld_qw_dminus2_offset : natural :=reld_core_tag_dplus1_offset + reld_core_tag_dplus1'length; +constant reld_qw_dminus1_offset : natural :=reld_qw_dminus2_offset + lat_reld_qw'length; +constant reld_qw_offset : natural :=reld_qw_dminus1_offset + reld_qw_dminus1'length; +constant reld_data_offset : natural :=reld_qw_offset + reld_qw'length; +constant ib0_wrt_entry_ptr_offset : natural :=reld_data_offset + lat_reld_data'length; +constant ib1_wrt_entry_ptr_offset : natural :=ib0_wrt_entry_ptr_offset + ib0_wrt_entry_ptr_q'length; +constant ib2_wrt_entry_ptr_offset : natural :=ib1_wrt_entry_ptr_offset + ib1_wrt_entry_ptr_q'length; +constant ib3_wrt_entry_ptr_offset : natural :=ib2_wrt_entry_ptr_offset + ib2_wrt_entry_ptr_q'length; +constant ib0_wrt_data_ctr_offset : natural :=ib3_wrt_entry_ptr_offset + ib3_wrt_entry_ptr_q'length; +constant ib1_wrt_data_ctr_offset : natural :=ib0_wrt_data_ctr_offset + ib0_wrt_data_ctr_q'length; +constant ib2_wrt_data_ctr_offset : natural :=ib1_wrt_data_ctr_offset + ib1_wrt_data_ctr_q'length; +constant ib3_wrt_data_ctr_offset : natural :=ib2_wrt_data_ctr_offset + ib2_wrt_data_ctr_q'length; +constant ib0_ecc_err_offset : natural :=ib3_wrt_data_ctr_offset + ib3_wrt_data_ctr_q'length; +constant ib1_ecc_err_offset : natural :=ib0_ecc_err_offset + 1; +constant ib2_ecc_err_offset : natural :=ib1_ecc_err_offset + 1; +constant ib3_ecc_err_offset : natural :=ib2_ecc_err_offset + 1; +constant ib0_set_val_offset : natural :=ib3_ecc_err_offset + 1; +constant ib1_set_val_offset : natural :=ib0_set_val_offset + 1; +constant ib2_set_val_offset : natural :=ib1_set_val_offset + 1; +constant ib3_set_val_offset : natural :=ib2_set_val_offset + 1; +constant debug_dbg_group0_offset : natural :=ib3_set_val_offset + 1; +constant trace_bus_enable_offset : natural :=debug_dbg_group0_offset + dbg_group0_q'length; +constant debug_mux_ctrls_offset : natural :=trace_bus_enable_offset + 1; +constant debug_mux_out_offset : natural :=debug_mux_ctrls_offset + debug_mux1_ctrls_q'length; +constant trigger_mux_out_offset : natural :=debug_mux_out_offset + debug_mux_out_d'length; + +constant scan_right1 : natural :=trigger_mux_out_offset + trigger_mux_out_d'length; + +signal siv : std_ulogic_vector(0 to scan_right1-1); +signal sov : std_ulogic_vector(0 to scan_right1-1); +signal ab_reg_si : std_ulogic_vector(0 to 24); +signal ab_reg_so : std_ulogic_vector(0 to 24); + +signal unused_signals : std_ulogic; + +begin + + +tidn <= '0'; + +unused_signals <= or_reduce(unused & delay_lclkr_dc_v(1 to 4) & mpw1_dc_b_v(1 to 4)); + +dp_op_val <= mtdp_ex3_to_7_val or ex3_mfdp_val_q or ex4_mfdp_val_q or ex5_mfdp_val_q or ex6_mfdp_val_q; + + +latch_my_ex3_flush : tri_rlmreg_p + generic map (width => my_ex3_flush_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(my_ex3_flush_offset to my_ex3_flush_offset + my_ex3_flush_q'length-1), + scout => sov(my_ex3_flush_offset to my_ex3_flush_offset + my_ex3_flush_q'length-1), + din => xu_ex2_flush, + dout => my_ex3_flush_q ); + +my_ex3_flush <= (my_ex3_flush_q(0) and ex3_ipc_thrd_q="00") or + (my_ex3_flush_q(1) and ex3_ipc_thrd_q="01") or + (my_ex3_flush_q(2) and ex3_ipc_thrd_q="10") or + (my_ex3_flush_q(3) and ex3_ipc_thrd_q="11"); + +latch_my_ex4_flush : tri_rlmreg_p + generic map (width => my_ex4_flush_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dp_op_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(my_ex4_flush_offset to my_ex4_flush_offset + my_ex4_flush_q'length-1), + scout => sov(my_ex4_flush_offset to my_ex4_flush_offset + my_ex4_flush_q'length-1), + din => xu_ex3_flush, + dout => my_ex4_flush_q ); + +my_ex4_stg_flush <= (my_ex4_flush_q(0) and (ex4_ipc_thrd_q(0 to 1)="00")) or + (my_ex4_flush_q(1) and (ex4_ipc_thrd_q(0 to 1)="01")) or + (my_ex4_flush_q(2) and (ex4_ipc_thrd_q(0 to 1)="10")) or + (my_ex4_flush_q(3) and (ex4_ipc_thrd_q(0 to 1)="11")); + +latch_my_ex5_flush : tri_rlmreg_p + generic map (width => my_ex4_flush_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dp_op_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(my_ex5_flush_offset to my_ex5_flush_offset + my_ex5_flush_q'length-1), + scout => sov(my_ex5_flush_offset to my_ex5_flush_offset + my_ex5_flush_q'length-1), + din => xu_ex4_flush, + dout => my_ex5_flush_q ); + +my_ex5_stg_flush <= (my_ex5_flush_q(0) and (ex5_ipc_thrd_q(0 to 1)="00")) or + (my_ex5_flush_q(1) and (ex5_ipc_thrd_q(0 to 1)="01")) or + (my_ex5_flush_q(2) and (ex5_ipc_thrd_q(0 to 1)="10")) or + (my_ex5_flush_q(3) and (ex5_ipc_thrd_q(0 to 1)="11")); + +latch_my_ex6_flush : tri_rlmreg_p + generic map (width => my_ex4_flush_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dp_op_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(my_ex6_flush_offset to my_ex6_flush_offset + my_ex6_flush_q'length-1), + scout => sov(my_ex6_flush_offset to my_ex6_flush_offset + my_ex6_flush_q'length-1), + din => xu_ex5_flush, + dout => my_ex6_flush_q ); + +my_ex6_stg_flush <= (my_ex6_flush_q(0) and (ex6_ipc_thrd_q(0 to 1)="00")) or + (my_ex6_flush_q(1) and (ex6_ipc_thrd_q(0 to 1)="01")) or + (my_ex6_flush_q(2) and (ex6_ipc_thrd_q(0 to 1)="10")) or + (my_ex6_flush_q(3) and (ex6_ipc_thrd_q(0 to 1)="11")); + +latch_my_ccr2_en_ditc : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(my_ccr2_en_ditc_offset to my_ccr2_en_ditc_offset), + scout => sov(my_ccr2_en_ditc_offset to my_ccr2_en_ditc_offset), + din(0) => xu_bx_ccr2_en_ditc, + dout(0) => my_ccr2_en_ditc_q ); + +latch_ex2_mtdp_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex2_mtdp_val_offset to ex2_mtdp_val_offset), + scout => sov(ex2_mtdp_val_offset to ex2_mtdp_val_offset), + din(0) => xu_bx_ex1_mtdp_val, + dout(0) => ex2_mtdp_val_q ); + +latch_ex3_mtdp_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex3_mtdp_val_offset to ex3_mtdp_val_offset), + scout => sov(ex3_mtdp_val_offset to ex3_mtdp_val_offset), + din(0) => ex2_mtdp_val_q, + dout(0) => ex3_mtdp_val_q ); + +ex3_mtdp_val <= ex3_mtdp_val_q and not my_ex3_flush and my_ccr2_en_ditc_q; + +latch_ex4_mtdp_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => mtdp_ex3_to_7_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_mtdp_val_offset to ex4_mtdp_val_offset), + scout => sov(ex4_mtdp_val_offset to ex4_mtdp_val_offset), + din(0) => ex3_mtdp_val, + dout(0) => ex4_mtdp_val_q ); +latch_ex5_mtdp_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => mtdp_ex3_to_7_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex5_mtdp_val_offset to ex5_mtdp_val_offset), + scout => sov(ex5_mtdp_val_offset to ex5_mtdp_val_offset), + din(0) => ex4_mtdp_val_q, + dout(0) => ex5_mtdp_val_q ); +latch_ex6_mtdp_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => mtdp_ex3_to_7_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex6_mtdp_val_offset to ex6_mtdp_val_offset), + scout => sov(ex6_mtdp_val_offset to ex6_mtdp_val_offset), + din(0) => ex5_mtdp_val_q, + dout(0) => ex6_mtdp_val_q ); +latch_ex7_mtdp_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => mtdp_ex3_to_7_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex7_mtdp_val_offset to ex7_mtdp_val_offset), + scout => sov(ex7_mtdp_val_offset to ex7_mtdp_val_offset), + din(0) => ex6_mtdp_val_q, + dout(0) => ex7_mtdp_val_q ); + +mtdp_ex3_to_7_val <= ex3_mtdp_val_q or ex4_mtdp_val_q or ex5_mtdp_val_q or ex6_mtdp_val_q or ex7_mtdp_val_q; + +latch_ex2_mfdp_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex2_mfdp_val_offset to ex2_mfdp_val_offset), + scout => sov(ex2_mfdp_val_offset to ex2_mfdp_val_offset), + din(0) => xu_bx_ex1_mfdp_val, + dout(0) => ex2_mfdp_val_q ); +latch_ex3_mfdp_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex3_mfdp_val_offset to ex3_mfdp_val_offset), + scout => sov(ex3_mfdp_val_offset to ex3_mfdp_val_offset), + din(0) => ex2_mfdp_val_q, + dout(0) => ex3_mfdp_val_q ); +latch_ex4_mfdp_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dp_op_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_mfdp_val_offset to ex4_mfdp_val_offset), + scout => sov(ex4_mfdp_val_offset to ex4_mfdp_val_offset), + din(0) => ex3_mfdp_val_q, + dout(0) => ex4_mfdp_val_q ); +latch_ex5_mfdp_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dp_op_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex5_mfdp_val_offset to ex5_mfdp_val_offset), + scout => sov(ex5_mfdp_val_offset to ex5_mfdp_val_offset), + din(0) => ex4_mfdp_val_q, + dout(0) => ex5_mfdp_val_q ); +latch_ex6_mfdp_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dp_op_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex6_mfdp_val_offset to ex6_mfdp_val_offset), + scout => sov(ex6_mfdp_val_offset to ex6_mfdp_val_offset), + din(0) => ex5_mfdp_val_q, + dout(0) => ex6_mfdp_val_q ); +latch_ex2_ipc_thrd : tri_rlmreg_p + generic map (width => ex2_ipc_thrd_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex2_ipc_thrd_offset to ex2_ipc_thrd_offset + ex2_ipc_thrd_q'length-1), + scout => sov(ex2_ipc_thrd_offset to ex2_ipc_thrd_offset + ex2_ipc_thrd_q'length-1), + din => xu_bx_ex1_ipc_thrd(0 to 1), + dout => ex2_ipc_thrd_q(0 to 1) ); +latch_ex3_ipc_thrd : tri_rlmreg_p + generic map (width => ex3_ipc_thrd_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex3_ipc_thrd_offset to ex3_ipc_thrd_offset + ex3_ipc_thrd_q'length-1), + scout => sov(ex3_ipc_thrd_offset to ex3_ipc_thrd_offset + ex3_ipc_thrd_q'length-1), + din => ex2_ipc_thrd_q(0 to 1), + dout => ex3_ipc_thrd_q(0 to 1) ); +latch_ex3_ipc_ba : tri_rlmreg_p + generic map (width => ex3_ipc_ba_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex3_ipc_ba_offset to ex3_ipc_ba_offset + ex3_ipc_ba_q'length-1), + scout => sov(ex3_ipc_ba_offset to ex3_ipc_ba_offset + ex3_ipc_ba_q'length-1), + din => xu_bx_ex2_ipc_ba(0 to 4), + dout => ex3_ipc_ba_q(0 to 4) ); +latch_ex3_ipc_sz : tri_rlmreg_p + generic map (width => ex3_ipc_sz_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex3_ipc_sz_offset to ex3_ipc_sz_offset + ex3_ipc_sz_q'length-1), + scout => sov(ex3_ipc_sz_offset to ex3_ipc_sz_offset + ex3_ipc_sz_q'length-1), + din => xu_bx_ex2_ipc_sz(0 to 1), + dout => ex3_ipc_sz_q(0 to 1) ); + + + +ditc_addr_sel <= (bx_slowspr_addr_q = "11" & x"DF"); + +ditc_addr_wen <= bx_slowspr_val_q and ditc_addr_sel and not bx_slowspr_rw_q; + + +ditc_addr_t0_wen <= ditc_addr_wen and (bx_slowspr_etid_q = "00"); + +ditc_addr_t0_d <= bx_slowspr_data_q(64-real_data_add to 57) when ditc_addr_t0_wen='1' else + ditc_addr_t0_q; + +ditc_addr_t1_wen <= ditc_addr_wen and (bx_slowspr_etid_q = "01"); + +ditc_addr_t1_d <= bx_slowspr_data_q(64-real_data_add to 57) when ditc_addr_t1_wen='1' else + ditc_addr_t1_q; + +ditc_addr_t2_wen <= ditc_addr_wen and (bx_slowspr_etid_q = "10"); + +ditc_addr_t2_d <= bx_slowspr_data_q(64-real_data_add to 57) when ditc_addr_t2_wen='1' else + ditc_addr_t2_q; + +ditc_addr_t3_wen <= ditc_addr_wen and (bx_slowspr_etid_q = "11"); + +ditc_addr_t3_d <= bx_slowspr_data_q(64-real_data_add to 57) when ditc_addr_t3_wen='1' else + ditc_addr_t3_q; + + +with bx_slowspr_etid_q select + ditc_addr_reg(64-real_data_add to 57) <= ditc_addr_t0_q when "00", + ditc_addr_t1_q when "01", + ditc_addr_t2_q when "10", + ditc_addr_t3_q when others; + +ditc_addr_reg(64-(2**REGMODE) to 64-real_data_add-1) <= (others=>'0'); +ditc_addr_reg(58 to 63) <= (others=>'0'); + +ditc_addr_rd_val <= bx_slowspr_val_q and ditc_addr_sel and bx_slowspr_rw_q; + +xu_slowspr_data_d <= ditc_addr_reg when ditc_addr_rd_val='1' else + bx_slowspr_data_q; + +xu_slowspr_done_d <= (bx_slowspr_val_q and ditc_addr_sel) or bx_slowspr_done_q; + + +xu_slowspr_val_d <= bx_slowspr_val_q; +xu_slowspr_rw_d <= bx_slowspr_rw_q; +xu_slowspr_etid_d <= bx_slowspr_etid_q; +xu_slowspr_addr_d <= bx_slowspr_addr_q; + +latch_bx_slowspr_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(bx_slowspr_val_offset to bx_slowspr_val_offset), + scout => sov(bx_slowspr_val_offset to bx_slowspr_val_offset), + din(0) => slowspr_val_in, + dout(0) => bx_slowspr_val_q ); + +latch_bx_slowspr_rw : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => slowspr_val_in, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(bx_slowspr_rw_offset to bx_slowspr_rw_offset), + scout => sov(bx_slowspr_rw_offset to bx_slowspr_rw_offset), + din(0) => slowspr_rw_in, + dout(0) => bx_slowspr_rw_q ); + +latch_bx_slowspr_etid : tri_rlmreg_p + generic map (width => bx_slowspr_etid_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => slowspr_val_in, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(bx_slowspr_etid_offset to bx_slowspr_etid_offset + bx_slowspr_etid_q'length-1), + scout => sov(bx_slowspr_etid_offset to bx_slowspr_etid_offset + bx_slowspr_etid_q'length-1), + din => slowspr_etid_in, + dout => bx_slowspr_etid_q ); + +latch_bx_slowspr_addr : tri_rlmreg_p + generic map (width => bx_slowspr_addr_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => slowspr_val_in, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(bx_slowspr_addr_offset to bx_slowspr_addr_offset + bx_slowspr_addr_q'length-1), + scout => sov(bx_slowspr_addr_offset to bx_slowspr_addr_offset + bx_slowspr_addr_q'length-1), + din => slowspr_addr_in, + dout => bx_slowspr_addr_q ); + +latch_bx_slowspr_data : tri_rlmreg_p + generic map (width => bx_slowspr_data_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => slowspr_val_in, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(bx_slowspr_data_offset to bx_slowspr_data_offset + bx_slowspr_data_q'length-1), + scout => sov(bx_slowspr_data_offset to bx_slowspr_data_offset + bx_slowspr_data_q'length-1), + din => slowspr_data_in, + dout => bx_slowspr_data_q ); + +latch_bx_slowspr_done : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => slowspr_val_in, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(bx_slowspr_done_offset to bx_slowspr_done_offset), + scout => sov(bx_slowspr_done_offset to bx_slowspr_done_offset), + din(0) => slowspr_done_in, + dout(0) => bx_slowspr_done_q ); + +latch_xu_slowspr_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(xu_slowspr_val_offset to xu_slowspr_val_offset), + scout => sov(xu_slowspr_val_offset to xu_slowspr_val_offset), + din(0) => xu_slowspr_val_d, + dout(0) => slowspr_val_out ); + + +latch_xu_slowspr_rw : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => bx_slowspr_val_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(xu_slowspr_rw_offset to xu_slowspr_rw_offset), + scout => sov(xu_slowspr_rw_offset to xu_slowspr_rw_offset), + din(0) => xu_slowspr_rw_d, + dout(0) => slowspr_rw_out ); + +latch_xu_slowspr_etid : tri_rlmreg_p + generic map (width => xu_slowspr_etid_d'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => bx_slowspr_val_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(xu_slowspr_etid_offset to xu_slowspr_etid_offset + xu_slowspr_etid_d'length-1), + scout => sov(xu_slowspr_etid_offset to xu_slowspr_etid_offset + xu_slowspr_etid_d'length-1), + din => xu_slowspr_etid_d, + dout => slowspr_etid_out ); + +latch_xu_slowspr_addr : tri_rlmreg_p + generic map (width => xu_slowspr_addr_d'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => bx_slowspr_val_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(xu_slowspr_addr_offset to xu_slowspr_addr_offset + xu_slowspr_addr_d'length-1), + scout => sov(xu_slowspr_addr_offset to xu_slowspr_addr_offset + xu_slowspr_addr_d'length-1), + din => xu_slowspr_addr_d, + dout => slowspr_addr_out ); + +latch_xu_slowspr_data : tri_rlmreg_p + generic map (width => xu_slowspr_data_d'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => bx_slowspr_val_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(xu_slowspr_data_offset to xu_slowspr_data_offset + xu_slowspr_data_d'length-1), + scout => sov(xu_slowspr_data_offset to xu_slowspr_data_offset + xu_slowspr_data_d'length-1), + din => xu_slowspr_data_d, + dout => slowspr_data_out ); + +latch_xu_slowspr_done : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => bx_slowspr_val_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(xu_slowspr_done_offset to xu_slowspr_done_offset), + scout => sov(xu_slowspr_done_offset to xu_slowspr_done_offset), + din(0) => xu_slowspr_done_d, + dout(0) => slowspr_done_out ); + +latch_ditc_addr_t0 : tri_rlmreg_p + generic map (width => ditc_addr_t0_d'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ditc_addr_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ditc_addr_t0_offset to ditc_addr_t0_offset + ditc_addr_t0_d'length-1), + scout => sov(ditc_addr_t0_offset to ditc_addr_t0_offset + ditc_addr_t0_d'length-1), + din => ditc_addr_t0_d, + dout => ditc_addr_t0_q ); + +latch_ditc_addr_t1 : tri_rlmreg_p + generic map (width => ditc_addr_t1_d'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ditc_addr_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ditc_addr_t1_offset to ditc_addr_t1_offset + ditc_addr_t1_d'length-1), + scout => sov(ditc_addr_t1_offset to ditc_addr_t1_offset + ditc_addr_t1_d'length-1), + din => ditc_addr_t1_d, + dout => ditc_addr_t1_q ); + +latch_ditc_addr_t2 : tri_rlmreg_p + generic map (width => ditc_addr_t2_d'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ditc_addr_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ditc_addr_t2_offset to ditc_addr_t2_offset + ditc_addr_t2_d'length-1), + scout => sov(ditc_addr_t2_offset to ditc_addr_t2_offset + ditc_addr_t2_d'length-1), + din => ditc_addr_t2_d, + dout => ditc_addr_t2_q ); + +latch_ditc_addr_t3 : tri_rlmreg_p + generic map (width => ditc_addr_t3_d'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ditc_addr_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ditc_addr_t3_offset to ditc_addr_t3_offset + ditc_addr_t3_d'length-1), + scout => sov(ditc_addr_t3_offset to ditc_addr_t3_offset + ditc_addr_t3_d'length-1), + din => ditc_addr_t3_d, + dout => ditc_addr_t3_q ); + + + +ex4_mtdp_val_gated <= ex4_mtdp_val_q and not my_ex4_stg_flush; + + + +ob0_wrt_entry_ptr_d <= std_ulogic_vector(unsigned(ob0_wrt_entry_ptr_q) + 1) when ob0_set_val='1' else + std_ulogic_vector(unsigned(ob0_wrt_entry_ptr_q) - 1) when (ex5_ob0_flushed xor ex6_ob0_flushed)='1' else + std_ulogic_vector(unsigned(ob0_wrt_entry_ptr_q) - 2) when (ex5_ob0_flushed and ex6_ob0_flushed)='1' else + ob0_wrt_entry_ptr_q(0 to 1); + +ob1_wrt_entry_ptr_d <= std_ulogic_vector(unsigned(ob1_wrt_entry_ptr_q) + 1) when ob1_set_val='1' else + std_ulogic_vector(unsigned(ob1_wrt_entry_ptr_q) - 1) when (ex5_ob1_flushed xor ex6_ob1_flushed)='1' else + std_ulogic_vector(unsigned(ob1_wrt_entry_ptr_q) - 2) when (ex5_ob1_flushed and ex6_ob1_flushed)='1' else + ob1_wrt_entry_ptr_q(0 to 1); + +ob2_wrt_entry_ptr_d <= std_ulogic_vector(unsigned(ob2_wrt_entry_ptr_q) + 1) when ob2_set_val='1' else + std_ulogic_vector(unsigned(ob2_wrt_entry_ptr_q) - 1) when (ex5_ob2_flushed xor ex6_ob2_flushed)='1' else + std_ulogic_vector(unsigned(ob2_wrt_entry_ptr_q) - 2) when (ex5_ob2_flushed and ex6_ob2_flushed)='1' else + ob2_wrt_entry_ptr_q(0 to 1); + +ob3_wrt_entry_ptr_d <= std_ulogic_vector(unsigned(ob3_wrt_entry_ptr_q) + 1) when ob3_set_val='1' else + std_ulogic_vector(unsigned(ob3_wrt_entry_ptr_q) - 1) when (ex5_ob3_flushed xor ex6_ob3_flushed)='1' else + std_ulogic_vector(unsigned(ob3_wrt_entry_ptr_q) - 2) when (ex5_ob3_flushed and ex6_ob3_flushed)='1' else + ob3_wrt_entry_ptr_q(0 to 1); + + + +latch_ob0_wrt_entry_ptr : tri_rlmreg_p + generic map (width => ob0_wrt_entry_ptr_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => mtdp_ex3_to_7_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob0_wrt_entry_ptr_offset to ob0_wrt_entry_ptr_offset + ob0_wrt_entry_ptr_q'length-1), + scout => sov(ob0_wrt_entry_ptr_offset to ob0_wrt_entry_ptr_offset + ob0_wrt_entry_ptr_q'length-1), + din => ob0_wrt_entry_ptr_d(0 to 1), + dout => ob0_wrt_entry_ptr_q(0 to 1) ); + +latch_ob1_wrt_entry_ptr : tri_rlmreg_p + generic map (width => ob1_wrt_entry_ptr_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => mtdp_ex3_to_7_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob1_wrt_entry_ptr_offset to ob1_wrt_entry_ptr_offset + ob1_wrt_entry_ptr_q'length-1), + scout => sov(ob1_wrt_entry_ptr_offset to ob1_wrt_entry_ptr_offset + ob1_wrt_entry_ptr_q'length-1), + din => ob1_wrt_entry_ptr_d(0 to 1), + dout => ob1_wrt_entry_ptr_q(0 to 1) ); + +latch_ob2_wrt_entry_ptr : tri_rlmreg_p + generic map (width => ob2_wrt_entry_ptr_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => mtdp_ex3_to_7_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob2_wrt_entry_ptr_offset to ob2_wrt_entry_ptr_offset + ob2_wrt_entry_ptr_q'length-1), + scout => sov(ob2_wrt_entry_ptr_offset to ob2_wrt_entry_ptr_offset + ob2_wrt_entry_ptr_q'length-1), + din => ob2_wrt_entry_ptr_d(0 to 1), + dout => ob2_wrt_entry_ptr_q(0 to 1) ); + +latch_ob3_wrt_entry_ptr : tri_rlmreg_p + generic map (width => ob3_wrt_entry_ptr_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => mtdp_ex3_to_7_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob3_wrt_entry_ptr_offset to ob3_wrt_entry_ptr_offset + ob3_wrt_entry_ptr_q'length-1), + scout => sov(ob3_wrt_entry_ptr_offset to ob3_wrt_entry_ptr_offset + ob3_wrt_entry_ptr_q'length-1), + din => ob3_wrt_entry_ptr_d(0 to 1), + dout => ob3_wrt_entry_ptr_q(0 to 1) ); + + +ob_status_reg_newdata(0 to 17) <= xu_bx_ex4_256st_data(32) & + xu_bx_ex4_256st_data(33 to 34) & + xu_bx_ex4_256st_data(49 to 55) & + xu_bx_ex4_256st_data(56 to 63); + +wrt_ob0_buf0_status <= not ob0_buf0_status_avail and ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "00") and (ex4_ipc_ba_q = "10001") and (ob0_wrt_entry_ptr_q = "00"); +wrt_ob0_buf1_status <= not ob0_buf1_status_avail and ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "00") and (ex4_ipc_ba_q = "10001") and (ob0_wrt_entry_ptr_q = "01"); +wrt_ob0_buf2_status <= not ob0_buf2_status_avail and ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "00") and (ex4_ipc_ba_q = "10001") and (ob0_wrt_entry_ptr_q = "10"); +wrt_ob0_buf3_status <= not ob0_buf3_status_avail and ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "00") and (ex4_ipc_ba_q = "10001") and (ob0_wrt_entry_ptr_q = "11"); +wrt_ob1_buf0_status <= not ob1_buf0_status_avail and ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "01") and (ex4_ipc_ba_q = "10001") and (ob1_wrt_entry_ptr_q = "00"); +wrt_ob1_buf1_status <= not ob1_buf1_status_avail and ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "01") and (ex4_ipc_ba_q = "10001") and (ob1_wrt_entry_ptr_q = "01"); +wrt_ob1_buf2_status <= not ob1_buf2_status_avail and ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "01") and (ex4_ipc_ba_q = "10001") and (ob1_wrt_entry_ptr_q = "10"); +wrt_ob1_buf3_status <= not ob1_buf3_status_avail and ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "01") and (ex4_ipc_ba_q = "10001") and (ob1_wrt_entry_ptr_q = "11"); +wrt_ob2_buf0_status <= not ob2_buf0_status_avail and ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "10") and (ex4_ipc_ba_q = "10001") and (ob2_wrt_entry_ptr_q = "00"); +wrt_ob2_buf1_status <= not ob2_buf1_status_avail and ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "10") and (ex4_ipc_ba_q = "10001") and (ob2_wrt_entry_ptr_q = "01"); +wrt_ob2_buf2_status <= not ob2_buf2_status_avail and ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "10") and (ex4_ipc_ba_q = "10001") and (ob2_wrt_entry_ptr_q = "10"); +wrt_ob2_buf3_status <= not ob2_buf3_status_avail and ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "10") and (ex4_ipc_ba_q = "10001") and (ob2_wrt_entry_ptr_q = "11"); +wrt_ob3_buf0_status <= not ob3_buf0_status_avail and ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "11") and (ex4_ipc_ba_q = "10001") and (ob3_wrt_entry_ptr_q = "00"); +wrt_ob3_buf1_status <= not ob3_buf1_status_avail and ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "11") and (ex4_ipc_ba_q = "10001") and (ob3_wrt_entry_ptr_q = "01"); +wrt_ob3_buf2_status <= not ob3_buf2_status_avail and ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "11") and (ex4_ipc_ba_q = "10001") and (ob3_wrt_entry_ptr_q = "10"); +wrt_ob3_buf3_status <= not ob3_buf3_status_avail and ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "11") and (ex4_ipc_ba_q = "10001") and (ob3_wrt_entry_ptr_q = "11"); + +ob0_set_val <= wrt_ob0_buf0_status or wrt_ob0_buf1_status or wrt_ob0_buf2_status or wrt_ob0_buf3_status; +ob1_set_val <= wrt_ob1_buf0_status or wrt_ob1_buf1_status or wrt_ob1_buf2_status or wrt_ob1_buf3_status; +ob2_set_val <= wrt_ob2_buf0_status or wrt_ob2_buf1_status or wrt_ob2_buf2_status or wrt_ob2_buf3_status; +ob3_set_val <= wrt_ob3_buf0_status or wrt_ob3_buf1_status or wrt_ob3_buf2_status or wrt_ob3_buf3_status; + + +ex4_wrt_ob_status(0 to 15) <= wrt_ob0_buf0_status & wrt_ob0_buf1_status & wrt_ob0_buf2_status & wrt_ob0_buf3_status & + wrt_ob1_buf0_status & wrt_ob1_buf1_status & wrt_ob1_buf2_status & wrt_ob1_buf3_status & + wrt_ob2_buf0_status & wrt_ob2_buf1_status & wrt_ob2_buf2_status & wrt_ob2_buf3_status & + wrt_ob3_buf0_status & wrt_ob3_buf1_status & wrt_ob3_buf2_status & wrt_ob3_buf3_status; + +ob_rd_logic_act_d <= ex4_mtdp_val_q or + ob0_buf0_status_q(0) or ob0_buf1_status_q(0) or ob0_buf2_status_q(0) or ob0_buf3_status_q(0) or + ob1_buf0_status_q(0) or ob1_buf1_status_q(0) or ob1_buf2_status_q(0) or ob1_buf3_status_q(0) or + ob2_buf0_status_q(0) or ob2_buf1_status_q(0) or ob2_buf2_status_q(0) or ob2_buf3_status_q(0) or + ob3_buf0_status_q(0) or ob3_buf1_status_q(0) or ob3_buf2_status_q(0) or ob3_buf3_status_q(0); + +latch_ob_rd_logic_act : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_rd_logic_act_offset to ob_rd_logic_act_offset), + scout => sov(ob_rd_logic_act_offset to ob_rd_logic_act_offset), + din(0) => ob_rd_logic_act_d, + dout(0) => ob_rd_logic_act_q ); + +ob_rd_logic_act <= ob_rd_logic_act_q or ex4_mtdp_val_q or ex5_mtdp_val_q or ex6_mtdp_val_q; + +latch_ex5_wrt_ob_status : tri_rlmreg_p + generic map (width => ex5_wrt_ob_status_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex5_wrt_ob_status_offset to ex5_wrt_ob_status_offset + ex5_wrt_ob_status_q'length-1), + scout => sov(ex5_wrt_ob_status_offset to ex5_wrt_ob_status_offset + ex5_wrt_ob_status_q'length-1), + din => ex4_wrt_ob_status(0 to 15), + dout => ex5_wrt_ob_status_q(0 to 15) ); + +ex5_wrt_ob_status_gated(0 to 15) <= gate_and(not my_ex5_stg_flush, ex5_wrt_ob_status_q(0 to 15)); + +latch_ex6_wrt_ob_status : tri_rlmreg_p + generic map (width => ex6_wrt_ob_status_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex6_wrt_ob_status_offset to ex6_wrt_ob_status_offset + ex6_wrt_ob_status_q'length-1), + scout => sov(ex6_wrt_ob_status_offset to ex6_wrt_ob_status_offset + ex6_wrt_ob_status_q'length-1), + din => ex5_wrt_ob_status_gated(0 to 15), + dout => ex6_wrt_ob_status_q(0 to 15) ); + +ex5_ob0_buf0_flushed <= ex5_wrt_ob_status_q(0) and my_ex5_stg_flush; +ex5_ob0_buf1_flushed <= ex5_wrt_ob_status_q(1) and my_ex5_stg_flush; +ex5_ob0_buf2_flushed <= ex5_wrt_ob_status_q(2) and my_ex5_stg_flush; +ex5_ob0_buf3_flushed <= ex5_wrt_ob_status_q(3) and my_ex5_stg_flush; +ex5_ob1_buf0_flushed <= ex5_wrt_ob_status_q(4) and my_ex5_stg_flush; +ex5_ob1_buf1_flushed <= ex5_wrt_ob_status_q(5) and my_ex5_stg_flush; +ex5_ob1_buf2_flushed <= ex5_wrt_ob_status_q(6) and my_ex5_stg_flush; +ex5_ob1_buf3_flushed <= ex5_wrt_ob_status_q(7) and my_ex5_stg_flush; +ex5_ob2_buf0_flushed <= ex5_wrt_ob_status_q(8) and my_ex5_stg_flush; +ex5_ob2_buf1_flushed <= ex5_wrt_ob_status_q(9) and my_ex5_stg_flush; +ex5_ob2_buf2_flushed <= ex5_wrt_ob_status_q(10) and my_ex5_stg_flush; +ex5_ob2_buf3_flushed <= ex5_wrt_ob_status_q(11) and my_ex5_stg_flush; +ex5_ob3_buf0_flushed <= ex5_wrt_ob_status_q(12) and my_ex5_stg_flush; +ex5_ob3_buf1_flushed <= ex5_wrt_ob_status_q(13) and my_ex5_stg_flush; +ex5_ob3_buf2_flushed <= ex5_wrt_ob_status_q(14) and my_ex5_stg_flush; +ex5_ob3_buf3_flushed <= ex5_wrt_ob_status_q(15) and my_ex5_stg_flush; + +ex5_ob0_flushed <= ex5_ob0_buf0_flushed or ex5_ob0_buf1_flushed or ex5_ob0_buf2_flushed or ex5_ob0_buf3_flushed; +ex5_ob1_flushed <= ex5_ob1_buf0_flushed or ex5_ob1_buf1_flushed or ex5_ob1_buf2_flushed or ex5_ob1_buf3_flushed; +ex5_ob2_flushed <= ex5_ob2_buf0_flushed or ex5_ob2_buf1_flushed or ex5_ob2_buf2_flushed or ex5_ob2_buf3_flushed; +ex5_ob3_flushed <= ex5_ob3_buf0_flushed or ex5_ob3_buf1_flushed or ex5_ob3_buf2_flushed or ex5_ob3_buf3_flushed; + +ex6_ob0_buf0_flushed <= ex6_wrt_ob_status_q(0) and my_ex6_stg_flush; +ex6_ob0_buf1_flushed <= ex6_wrt_ob_status_q(1) and my_ex6_stg_flush; +ex6_ob0_buf2_flushed <= ex6_wrt_ob_status_q(2) and my_ex6_stg_flush; +ex6_ob0_buf3_flushed <= ex6_wrt_ob_status_q(3) and my_ex6_stg_flush; +ex6_ob1_buf0_flushed <= ex6_wrt_ob_status_q(4) and my_ex6_stg_flush; +ex6_ob1_buf1_flushed <= ex6_wrt_ob_status_q(5) and my_ex6_stg_flush; +ex6_ob1_buf2_flushed <= ex6_wrt_ob_status_q(6) and my_ex6_stg_flush; +ex6_ob1_buf3_flushed <= ex6_wrt_ob_status_q(7) and my_ex6_stg_flush; +ex6_ob2_buf0_flushed <= ex6_wrt_ob_status_q(8) and my_ex6_stg_flush; +ex6_ob2_buf1_flushed <= ex6_wrt_ob_status_q(9) and my_ex6_stg_flush; +ex6_ob2_buf2_flushed <= ex6_wrt_ob_status_q(10) and my_ex6_stg_flush; +ex6_ob2_buf3_flushed <= ex6_wrt_ob_status_q(11) and my_ex6_stg_flush; +ex6_ob3_buf0_flushed <= ex6_wrt_ob_status_q(12) and my_ex6_stg_flush; +ex6_ob3_buf1_flushed <= ex6_wrt_ob_status_q(13) and my_ex6_stg_flush; +ex6_ob3_buf2_flushed <= ex6_wrt_ob_status_q(14) and my_ex6_stg_flush; +ex6_ob3_buf3_flushed <= ex6_wrt_ob_status_q(15) and my_ex6_stg_flush; + +ex6_ob0_flushed <= ex6_ob0_buf0_flushed or ex6_ob0_buf1_flushed or ex6_ob0_buf2_flushed or ex6_ob0_buf3_flushed; +ex6_ob1_flushed <= ex6_ob1_buf0_flushed or ex6_ob1_buf1_flushed or ex6_ob1_buf2_flushed or ex6_ob1_buf3_flushed; +ex6_ob2_flushed <= ex6_ob2_buf0_flushed or ex6_ob2_buf1_flushed or ex6_ob2_buf2_flushed or ex6_ob2_buf3_flushed; +ex6_ob3_flushed <= ex6_ob3_buf0_flushed or ex6_ob3_buf1_flushed or ex6_ob3_buf2_flushed or ex6_ob3_buf3_flushed; + +ob0_buf0_clr <= ob0_buf0_done or ex5_ob0_buf0_flushed or ex6_ob0_buf0_flushed; + +ob0_buf0_status_avail <= ob0_buf0_status_q(0) and not ex5_ob0_buf0_flushed and not ex6_ob0_buf0_flushed; + +ob0_buf0_status_d(0 to 17) <= ob_status_reg_newdata(0 to 17) when wrt_ob0_buf0_status='1' else + (others => '0') when ob0_buf0_clr='1' else + ob0_buf0_status_q(0 to 17); + +ob0_buf1_clr <= ob0_buf1_done or ex5_ob0_buf1_flushed or ex6_ob0_buf1_flushed; + +ob0_buf1_status_avail <= ob0_buf1_status_q(0) and not ex5_ob0_buf1_flushed and not ex6_ob0_buf1_flushed; + +ob0_buf1_status_d(0 to 17) <= ob_status_reg_newdata(0 to 17) when wrt_ob0_buf1_status='1' else + (others => '0') when ob0_buf1_clr='1' else + ob0_buf1_status_q(0 to 17); + +ob0_buf2_clr <= ob0_buf2_done or ex5_ob0_buf2_flushed or ex6_ob0_buf2_flushed; + +ob0_buf2_status_avail <= ob0_buf2_status_q(0) and not ex5_ob0_buf2_flushed and not ex6_ob0_buf2_flushed; + +ob0_buf2_status_d(0 to 17) <= ob_status_reg_newdata(0 to 17) when wrt_ob0_buf2_status='1' else + (others => '0') when ob0_buf2_clr='1' else + ob0_buf2_status_q(0 to 17); + +ob0_buf3_clr <= ob0_buf3_done or ex5_ob0_buf3_flushed or ex6_ob0_buf3_flushed; + +ob0_buf3_status_avail <= ob0_buf3_status_q(0) and not ex5_ob0_buf3_flushed and not ex6_ob0_buf3_flushed; + +ob0_buf3_status_d(0 to 17) <= ob_status_reg_newdata(0 to 17) when wrt_ob0_buf3_status='1' else + (others => '0') when ob0_buf3_clr='1' else + ob0_buf3_status_q(0 to 17); + +ob1_buf0_clr <= ob1_buf0_done or ex5_ob1_buf0_flushed or ex6_ob1_buf0_flushed; + +ob1_buf0_status_avail <= ob1_buf0_status_q(0) and not ex5_ob1_buf0_flushed and not ex6_ob1_buf0_flushed; + +ob1_buf0_status_d(0 to 17) <= ob_status_reg_newdata(0 to 17) when wrt_ob1_buf0_status='1' else + (others => '0') when ob1_buf0_clr='1' else + ob1_buf0_status_q(0 to 17); + +ob1_buf1_clr <= ob1_buf1_done or ex5_ob1_buf1_flushed or ex6_ob1_buf1_flushed; + +ob1_buf1_status_avail <= ob1_buf1_status_q(0) and not ex5_ob1_buf1_flushed and not ex6_ob1_buf1_flushed; + +ob1_buf1_status_d(0 to 17) <= ob_status_reg_newdata(0 to 17) when wrt_ob1_buf1_status='1' else + (others => '0') when ob1_buf1_clr='1' else + ob1_buf1_status_q(0 to 17); + +ob1_buf2_clr <= ob1_buf2_done or ex5_ob1_buf2_flushed or ex6_ob1_buf2_flushed; + +ob1_buf2_status_avail <= ob1_buf2_status_q(0) and not ex5_ob1_buf2_flushed and not ex6_ob1_buf2_flushed; + +ob1_buf2_status_d(0 to 17) <= ob_status_reg_newdata(0 to 17) when wrt_ob1_buf2_status='1' else + (others => '0') when ob1_buf2_clr='1' else + ob1_buf2_status_q(0 to 17); + +ob1_buf3_clr <= ob1_buf3_done or ex5_ob1_buf3_flushed or ex6_ob1_buf3_flushed; + +ob1_buf3_status_avail <= ob1_buf3_status_q(0) and not ex5_ob1_buf3_flushed and not ex6_ob1_buf3_flushed; + +ob1_buf3_status_d(0 to 17) <= ob_status_reg_newdata(0 to 17) when wrt_ob1_buf3_status='1' else + (others => '0') when ob1_buf3_clr='1' else + ob1_buf3_status_q(0 to 17); + +ob2_buf0_clr <= ob2_buf0_done or ex5_ob2_buf0_flushed or ex6_ob2_buf0_flushed; + +ob2_buf0_status_avail <= ob2_buf0_status_q(0) and not ex5_ob2_buf0_flushed and not ex6_ob2_buf0_flushed; + +ob2_buf0_status_d(0 to 17) <= ob_status_reg_newdata(0 to 17) when wrt_ob2_buf0_status='1' else + (others => '0') when ob2_buf0_clr='1' else + ob2_buf0_status_q(0 to 17); + +ob2_buf1_clr <= ob2_buf1_done or ex5_ob2_buf1_flushed or ex6_ob2_buf1_flushed; + +ob2_buf1_status_avail <= ob2_buf1_status_q(0) and not ex5_ob2_buf1_flushed and not ex6_ob2_buf1_flushed; + +ob2_buf1_status_d(0 to 17) <= ob_status_reg_newdata(0 to 17) when wrt_ob2_buf1_status='1' else + (others => '0') when ob2_buf1_clr='1' else + ob2_buf1_status_q(0 to 17); + +ob2_buf2_clr <= ob2_buf2_done or ex5_ob2_buf2_flushed or ex6_ob2_buf2_flushed; + +ob2_buf2_status_avail <= ob2_buf2_status_q(0) and not ex5_ob2_buf2_flushed and not ex6_ob2_buf2_flushed; + +ob2_buf2_status_d(0 to 17) <= ob_status_reg_newdata(0 to 17) when wrt_ob2_buf2_status='1' else + (others => '0') when ob2_buf2_clr='1' else + ob2_buf2_status_q(0 to 17); + +ob2_buf3_clr <= ob2_buf3_done or ex5_ob2_buf3_flushed or ex6_ob2_buf3_flushed; + +ob2_buf3_status_avail <= ob2_buf3_status_q(0) and not ex5_ob2_buf3_flushed and not ex6_ob2_buf3_flushed; + +ob2_buf3_status_d(0 to 17) <= ob_status_reg_newdata(0 to 17) when wrt_ob2_buf3_status='1' else + (others => '0') when ob2_buf3_clr='1' else + ob2_buf3_status_q(0 to 17); + +ob3_buf0_clr <= ob3_buf0_done or ex5_ob3_buf0_flushed or ex6_ob3_buf0_flushed; + +ob3_buf0_status_avail <= ob3_buf0_status_q(0) and not ex5_ob3_buf0_flushed and not ex6_ob3_buf0_flushed; + +ob3_buf0_status_d(0 to 17) <= ob_status_reg_newdata(0 to 17) when wrt_ob3_buf0_status='1' else + (others => '0') when ob3_buf0_clr='1' else + ob3_buf0_status_q(0 to 17); + +ob3_buf1_clr <= ob3_buf1_done or ex5_ob3_buf1_flushed or ex6_ob3_buf1_flushed; + +ob3_buf1_status_avail <= ob3_buf1_status_q(0) and not ex5_ob3_buf1_flushed and not ex6_ob3_buf1_flushed; + +ob3_buf1_status_d(0 to 17) <= ob_status_reg_newdata(0 to 17) when wrt_ob3_buf1_status='1' else + (others => '0') when ob3_buf1_clr='1' else + ob3_buf1_status_q(0 to 17); + +ob3_buf2_clr <= ob3_buf2_done or ex5_ob3_buf2_flushed or ex6_ob3_buf2_flushed; + +ob3_buf2_status_avail <= ob3_buf2_status_q(0) and not ex5_ob3_buf2_flushed and not ex6_ob3_buf2_flushed; + +ob3_buf2_status_d(0 to 17) <= ob_status_reg_newdata(0 to 17) when wrt_ob3_buf2_status='1' else + (others => '0') when ob3_buf2_clr='1' else + ob3_buf2_status_q(0 to 17); + +ob3_buf3_clr <= ob3_buf3_done or ex5_ob3_buf3_flushed or ex6_ob3_buf3_flushed; + +ob3_buf3_status_avail <= ob3_buf3_status_q(0) and not ex5_ob3_buf3_flushed and not ex6_ob3_buf3_flushed; + +ob3_buf3_status_d(0 to 17) <= ob_status_reg_newdata(0 to 17) when wrt_ob3_buf3_status='1' else + (others => '0') when ob3_buf3_clr='1' else + ob3_buf3_status_q(0 to 17); + +latch_ob0_buf0_status : tri_rlmreg_p + generic map (width => ob0_buf0_status_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob0_buf0_status_offset to ob0_buf0_status_offset + ob0_buf0_status_q'length-1), + scout => sov(ob0_buf0_status_offset to ob0_buf0_status_offset + ob0_buf0_status_q'length-1), + din => ob0_buf0_status_d, + dout => ob0_buf0_status_q ); + + +latch_ob0_buf1_status : tri_rlmreg_p + generic map (width => ob0_buf1_status_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob0_buf1_status_offset to ob0_buf1_status_offset + ob0_buf1_status_q'length-1), + scout => sov(ob0_buf1_status_offset to ob0_buf1_status_offset + ob0_buf1_status_q'length-1), + din => ob0_buf1_status_d, + dout => ob0_buf1_status_q ); + +latch_ob0_buf2_status : tri_rlmreg_p + generic map (width => ob0_buf2_status_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob0_buf2_status_offset to ob0_buf2_status_offset + ob0_buf2_status_q'length-1), + scout => sov(ob0_buf2_status_offset to ob0_buf2_status_offset + ob0_buf2_status_q'length-1), + din => ob0_buf2_status_d, + dout => ob0_buf2_status_q ); + +latch_ob0_buf3_status : tri_rlmreg_p + generic map (width => ob0_buf3_status_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob0_buf3_status_offset to ob0_buf3_status_offset + ob0_buf3_status_q'length-1), + scout => sov(ob0_buf3_status_offset to ob0_buf3_status_offset + ob0_buf3_status_q'length-1), + din => ob0_buf3_status_d, + dout => ob0_buf3_status_q ); + +latch_ob1_buf0_status : tri_rlmreg_p + generic map (width => ob1_buf0_status_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob1_buf0_status_offset to ob1_buf0_status_offset + ob1_buf0_status_q'length-1), + scout => sov(ob1_buf0_status_offset to ob1_buf0_status_offset + ob1_buf0_status_q'length-1), + din => ob1_buf0_status_d, + dout => ob1_buf0_status_q ); + + +latch_ob1_buf1_status : tri_rlmreg_p + generic map (width => ob1_buf1_status_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob1_buf1_status_offset to ob1_buf1_status_offset + ob1_buf1_status_q'length-1), + scout => sov(ob1_buf1_status_offset to ob1_buf1_status_offset + ob1_buf1_status_q'length-1), + din => ob1_buf1_status_d, + dout => ob1_buf1_status_q ); + +latch_ob1_buf2_status : tri_rlmreg_p + generic map (width => ob1_buf2_status_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob1_buf2_status_offset to ob1_buf2_status_offset + ob1_buf2_status_q'length-1), + scout => sov(ob1_buf2_status_offset to ob1_buf2_status_offset + ob1_buf2_status_q'length-1), + din => ob1_buf2_status_d, + dout => ob1_buf2_status_q ); + +latch_ob1_buf3_status : tri_rlmreg_p + generic map (width => ob1_buf3_status_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob1_buf3_status_offset to ob1_buf3_status_offset + ob1_buf3_status_q'length-1), + scout => sov(ob1_buf3_status_offset to ob1_buf3_status_offset + ob1_buf3_status_q'length-1), + din => ob1_buf3_status_d, + dout => ob1_buf3_status_q ); + +latch_ob2_buf0_status : tri_rlmreg_p + generic map (width => ob2_buf0_status_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob2_buf0_status_offset to ob2_buf0_status_offset + ob2_buf0_status_q'length-1), + scout => sov(ob2_buf0_status_offset to ob2_buf0_status_offset + ob2_buf0_status_q'length-1), + din => ob2_buf0_status_d, + dout => ob2_buf0_status_q ); + + +latch_ob2_buf1_status : tri_rlmreg_p + generic map (width => ob2_buf1_status_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob2_buf1_status_offset to ob2_buf1_status_offset + ob2_buf1_status_q'length-1), + scout => sov(ob2_buf1_status_offset to ob2_buf1_status_offset + ob2_buf1_status_q'length-1), + din => ob2_buf1_status_d, + dout => ob2_buf1_status_q ); + +latch_ob2_buf2_status : tri_rlmreg_p + generic map (width => ob2_buf2_status_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob2_buf2_status_offset to ob2_buf2_status_offset + ob2_buf2_status_q'length-1), + scout => sov(ob2_buf2_status_offset to ob2_buf2_status_offset + ob2_buf2_status_q'length-1), + din => ob2_buf2_status_d, + dout => ob2_buf2_status_q ); + +latch_ob2_buf3_status : tri_rlmreg_p + generic map (width => ob2_buf3_status_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob2_buf3_status_offset to ob2_buf3_status_offset + ob2_buf3_status_q'length-1), + scout => sov(ob2_buf3_status_offset to ob2_buf3_status_offset + ob2_buf3_status_q'length-1), + din => ob2_buf3_status_d, + dout => ob2_buf3_status_q ); + +latch_ob3_buf0_status : tri_rlmreg_p + generic map (width => ob3_buf0_status_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob3_buf0_status_offset to ob3_buf0_status_offset + ob3_buf0_status_q'length-1), + scout => sov(ob3_buf0_status_offset to ob3_buf0_status_offset + ob3_buf0_status_q'length-1), + din => ob3_buf0_status_d, + dout => ob3_buf0_status_q ); + + +latch_ob3_buf1_status : tri_rlmreg_p + generic map (width => ob3_buf1_status_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob3_buf1_status_offset to ob3_buf1_status_offset + ob3_buf1_status_q'length-1), + scout => sov(ob3_buf1_status_offset to ob3_buf1_status_offset + ob3_buf1_status_q'length-1), + din => ob3_buf1_status_d, + dout => ob3_buf1_status_q ); + +latch_ob3_buf2_status : tri_rlmreg_p + generic map (width => ob3_buf2_status_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob3_buf2_status_offset to ob3_buf2_status_offset + ob3_buf2_status_q'length-1), + scout => sov(ob3_buf2_status_offset to ob3_buf2_status_offset + ob3_buf2_status_q'length-1), + din => ob3_buf2_status_d, + dout => ob3_buf2_status_q ); + +latch_ob3_buf3_status : tri_rlmreg_p + generic map (width => ob3_buf3_status_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob3_buf3_status_offset to ob3_buf3_status_offset + ob3_buf3_status_q'length-1), + scout => sov(ob3_buf3_status_offset to ob3_buf3_status_offset + ob3_buf3_status_q'length-1), + din => ob3_buf3_status_d, + dout => ob3_buf3_status_q ); + +ob_buf_status_avail_d <= ob0_buf0_status_avail & ob0_buf1_status_avail & ob0_buf2_status_avail & ob0_buf3_status_avail & + ob1_buf0_status_avail & ob1_buf1_status_avail & ob1_buf2_status_avail & ob1_buf3_status_avail & + ob2_buf0_status_avail & ob2_buf1_status_avail & ob2_buf2_status_avail & ob2_buf3_status_avail & + ob3_buf0_status_avail & ob3_buf1_status_avail & ob3_buf2_status_avail & ob3_buf3_status_avail; + +latch_ob_buf_status_avail : tri_rlmreg_p + generic map (width => ob_buf_status_avail_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_buf_status_avail_offset to ob_buf_status_avail_offset + ob_buf_status_avail_q'length-1), + scout => sov(ob_buf_status_avail_offset to ob_buf_status_avail_offset + ob_buf_status_avail_q'length-1), + din => ob_buf_status_avail_d, + dout => ob_buf_status_avail_q ); + +ob0_buf0_status_val <= ob_buf_status_avail_q(0) and not ex6_ob0_buf0_flushed; +ob0_buf1_status_val <= ob_buf_status_avail_q(1) and not ex6_ob0_buf1_flushed; +ob0_buf2_status_val <= ob_buf_status_avail_q(2) and not ex6_ob0_buf2_flushed; +ob0_buf3_status_val <= ob_buf_status_avail_q(3) and not ex6_ob0_buf3_flushed; +ob1_buf0_status_val <= ob_buf_status_avail_q(4) and not ex6_ob1_buf0_flushed; +ob1_buf1_status_val <= ob_buf_status_avail_q(5) and not ex6_ob1_buf1_flushed; +ob1_buf2_status_val <= ob_buf_status_avail_q(6) and not ex6_ob1_buf2_flushed; +ob1_buf3_status_val <= ob_buf_status_avail_q(7) and not ex6_ob1_buf3_flushed; +ob2_buf0_status_val <= ob_buf_status_avail_q(8) and not ex6_ob2_buf0_flushed; +ob2_buf1_status_val <= ob_buf_status_avail_q(9) and not ex6_ob2_buf1_flushed; +ob2_buf2_status_val <= ob_buf_status_avail_q(10) and not ex6_ob2_buf2_flushed; +ob2_buf3_status_val <= ob_buf_status_avail_q(11) and not ex6_ob2_buf3_flushed; +ob3_buf0_status_val <= ob_buf_status_avail_q(12) and not ex6_ob3_buf0_flushed; +ob3_buf1_status_val <= ob_buf_status_avail_q(13) and not ex6_ob3_buf1_flushed; +ob3_buf2_status_val <= ob_buf_status_avail_q(14) and not ex6_ob3_buf2_flushed; +ob3_buf3_status_val <= ob_buf_status_avail_q(15) and not ex6_ob3_buf3_flushed; + + + +with ex4_ipc_thrd_q(0 to 1) select + ob_wrt_entry_ptr(0 to 1) <= ob0_wrt_entry_ptr_q(0 to 1) when "00", + ob1_wrt_entry_ptr_q(0 to 1) when "01", + ob2_wrt_entry_ptr_q(0 to 1) when "10", + ob3_wrt_entry_ptr_q(0 to 1) when others; + +ob_wrt_addr(0 to 5) <= ex4_ipc_thrd_q(0 to 1) & ob_wrt_entry_ptr(0 to 1) & ex4_ipc_ba_q(1 to 2); + +ob_buf_status_val <= (ob0_buf0_status_avail and (ex4_ipc_thrd_q="00") and ob0_wrt_entry_ptr_q="00") or + (ob0_buf1_status_avail and (ex4_ipc_thrd_q="00") and ob0_wrt_entry_ptr_q="01") or + (ob0_buf2_status_avail and (ex4_ipc_thrd_q="00") and ob0_wrt_entry_ptr_q="10") or + (ob0_buf3_status_avail and (ex4_ipc_thrd_q="00") and ob0_wrt_entry_ptr_q="11") or + (ob1_buf0_status_avail and (ex4_ipc_thrd_q="01") and ob1_wrt_entry_ptr_q="00") or + (ob1_buf1_status_avail and (ex4_ipc_thrd_q="01") and ob1_wrt_entry_ptr_q="01") or + (ob1_buf2_status_avail and (ex4_ipc_thrd_q="01") and ob1_wrt_entry_ptr_q="10") or + (ob1_buf3_status_avail and (ex4_ipc_thrd_q="01") and ob1_wrt_entry_ptr_q="11") or + (ob2_buf0_status_avail and (ex4_ipc_thrd_q="10") and ob2_wrt_entry_ptr_q="00") or + (ob2_buf1_status_avail and (ex4_ipc_thrd_q="10") and ob2_wrt_entry_ptr_q="01") or + (ob2_buf2_status_avail and (ex4_ipc_thrd_q="10") and ob2_wrt_entry_ptr_q="10") or + (ob2_buf3_status_avail and (ex4_ipc_thrd_q="10") and ob2_wrt_entry_ptr_q="11") or + (ob3_buf0_status_avail and (ex4_ipc_thrd_q="11") and ob3_wrt_entry_ptr_q="00") or + (ob3_buf1_status_avail and (ex4_ipc_thrd_q="11") and ob3_wrt_entry_ptr_q="01") or + (ob3_buf2_status_avail and (ex4_ipc_thrd_q="11") and ob3_wrt_entry_ptr_q="10") or + (ob3_buf3_status_avail and (ex4_ipc_thrd_q="11") and ob3_wrt_entry_ptr_q="11"); + +ob_wen(0) <= ex4_mtdp_val_gated and not ob_buf_status_val and ex4_ipc_ba_q(0)='0' and + ( (ex4_ipc_ba_q(3 to 4)="00") or (ex4_ipc_sz_q="10") or + (ex4_ipc_ba_q(3 to 4)="11" and ex4_ipc_sz_q="01") ); +ob_wen(1) <= ex4_mtdp_val_gated and not ob_buf_status_val and ex4_ipc_ba_q(0)='0' and + ( (ex4_ipc_ba_q(3 to 4)="01") or (ex4_ipc_sz_q="10") or + (ex4_ipc_ba_q(3 to 4)="00" and ex4_ipc_sz_q="01") ); +ob_wen(2) <= ex4_mtdp_val_gated and not ob_buf_status_val and ex4_ipc_ba_q(0)='0' and + ( (ex4_ipc_ba_q(3 to 4)="10") or (ex4_ipc_sz_q="10") or + (ex4_ipc_ba_q(3 to 4)="01" and ex4_ipc_sz_q="01") ); +ob_wen(3) <= ex4_mtdp_val_gated and not ob_buf_status_val and ex4_ipc_ba_q(0)='0' and + ( (ex4_ipc_ba_q(3 to 4)="11") or (ex4_ipc_sz_q="10") or + (ex4_ipc_ba_q(3 to 4)="10" and ex4_ipc_sz_q="01") ); + + + +ex3_ob_buf_status_val <= (ob0_buf0_status_avail and (ex3_ipc_thrd_q="00") and ob0_wrt_entry_ptr_d="00") or + (ob0_buf1_status_avail and (ex3_ipc_thrd_q="00") and ob0_wrt_entry_ptr_d="01") or + (ob0_buf2_status_avail and (ex3_ipc_thrd_q="00") and ob0_wrt_entry_ptr_d="10") or + (ob0_buf3_status_avail and (ex3_ipc_thrd_q="00") and ob0_wrt_entry_ptr_d="11") or + (ob1_buf0_status_avail and (ex3_ipc_thrd_q="01") and ob1_wrt_entry_ptr_d="00") or + (ob1_buf1_status_avail and (ex3_ipc_thrd_q="01") and ob1_wrt_entry_ptr_d="01") or + (ob1_buf2_status_avail and (ex3_ipc_thrd_q="01") and ob1_wrt_entry_ptr_d="10") or + (ob1_buf3_status_avail and (ex3_ipc_thrd_q="01") and ob1_wrt_entry_ptr_d="11") or + (ob2_buf0_status_avail and (ex3_ipc_thrd_q="10") and ob2_wrt_entry_ptr_d="00") or + (ob2_buf1_status_avail and (ex3_ipc_thrd_q="10") and ob2_wrt_entry_ptr_d="01") or + (ob2_buf2_status_avail and (ex3_ipc_thrd_q="10") and ob2_wrt_entry_ptr_d="10") or + (ob2_buf3_status_avail and (ex3_ipc_thrd_q="10") and ob2_wrt_entry_ptr_d="11") or + (ob3_buf0_status_avail and (ex3_ipc_thrd_q="11") and ob3_wrt_entry_ptr_d="00") or + (ob3_buf1_status_avail and (ex3_ipc_thrd_q="11") and ob3_wrt_entry_ptr_d="01") or + (ob3_buf2_status_avail and (ex3_ipc_thrd_q="11") and ob3_wrt_entry_ptr_d="10") or + (ob3_buf3_status_avail and (ex3_ipc_thrd_q="11") and ob3_wrt_entry_ptr_d="11"); + + +ex3_mtdp_cr_status <= ex3_mtdp_val and (not ex3_ob_buf_status_val or (ex3_ipc_ba_q = "10000")); + +latch_ex4_mtdp_cr_status : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => mtdp_ex3_to_7_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_mtdp_cr_status_offset to ex4_mtdp_cr_status_offset), + scout => sov(ex4_mtdp_cr_status_offset to ex4_mtdp_cr_status_offset), + din(0) => ex3_mtdp_cr_status, + dout(0) => ex4_mtdp_cr_status ); + +bx_xu_ex4_mtdp_cr_status <= ex4_mtdp_cr_status; + + +latch_ob_wrt_data : tri_rlmreg_p + generic map (width => ob_ary_wrt_data_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ex4_mtdp_val_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_wrt_data_offset to ob_wrt_data_offset + ob_ary_wrt_data_l2'length-1), + scout => sov(ob_wrt_data_offset to ob_wrt_data_offset + ob_ary_wrt_data_l2'length-1), + din => xu_bx_ex4_256st_data, + dout => ob_ary_wrt_data_l2 ); + +latch_ob_ary_wen : tri_rlmreg_p + generic map (width => ob_ary_wen_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => mtdp_ex3_to_7_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_ary_wen_offset to ob_ary_wen_offset + ob_ary_wen_l2'length-1), + scout => sov(ob_ary_wen_offset to ob_ary_wen_offset + ob_ary_wen_l2'length-1), + din => ob_wen, + dout => ob_ary_wen_l2 ); + +latch_ob_ary_wrt_addr : tri_rlmreg_p + generic map (width => ob_ary_wrt_addr_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ex4_mtdp_val_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_ary_wrt_addr_offset to ob_ary_wrt_addr_offset + ob_ary_wrt_addr_l2'length-1), + scout => sov(ob_ary_wrt_addr_offset to ob_ary_wrt_addr_offset + ob_ary_wrt_addr_l2'length-1), + din => ob_wrt_addr, + dout => ob_ary_wrt_addr_l2 ); + +ob_di_eccgen0: entity work.xuq_eccgen(xuq_eccgen) + generic map ( regsize => 32 ) + port map(din(0 to 31) => ob_ary_wrt_data_l2(0 to 31), + din(32 to 38) => "1111111", + syn => ob_datain_ecc0 ); + +ob_di_eccgen1: entity work.xuq_eccgen(xuq_eccgen) + generic map ( regsize => 32 ) + port map(din(0 to 31) => ob_ary_wrt_data_l2(32 to 63), + din(32 to 38) => "1111111", + syn => ob_datain_ecc1 ); + +ob_di_eccgen2: entity work.xuq_eccgen(xuq_eccgen) + generic map ( regsize => 32 ) + port map(din(0 to 31) => ob_ary_wrt_data_l2(64 to 95), + din(32 to 38) => "1111111", + syn => ob_datain_ecc2 ); + +ob_di_eccgen3: entity work.xuq_eccgen(xuq_eccgen) + generic map ( regsize => 32 ) + port map(din(0 to 31) => ob_ary_wrt_data_l2(96 to 127), + din(32 to 38) => "1111111", + syn => ob_datain_ecc3 ); + + + +latch_ob_err_inj : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_err_inj_offset to ob_err_inj_offset), + scout => sov(ob_err_inj_offset to ob_err_inj_offset), + din(0) => pc_bx_inj_outbox_ecc, + dout(0) => ob_err_inj_q ); + +ob_ary_wrt_data_0 <= ob_ary_wrt_data_l2(0) xor ob_err_inj_q; + + +ob_array: entity tri.tri_64x42_4w_1r1w(tri_64x42_4w_1r1w) + generic map ( expand_type => expand_type ) + port map( + wr_way => ob_ary_wen_l2(0 to 3), + wr_adr => ob_ary_wrt_addr_l2(0 to 5), + + di(0) => ob_ary_wrt_data_0, + di(1 to 31) => ob_ary_wrt_data_l2(1 to 31), + di(32 to 38) => ob_datain_ecc0(0 to 6), + di(39 to 41) => "000", + + di(42 to 73) => ob_ary_wrt_data_l2(32 to 63), + di(74 to 80) => ob_datain_ecc1(0 to 6), + di(81 to 83) => "000", + + di(84 to 115) => ob_ary_wrt_data_l2(64 to 95), + di(116 to 122) => ob_datain_ecc2(0 to 6), + di(123 to 125) => "000", + + di(126 to 157) => ob_ary_wrt_data_l2(96 to 127), + di(158 to 164) => ob_datain_ecc3(0 to 6), + di(165 to 167) => "000", + + rd0_adr => ob_ary_rd_addr(0 to 5), + + do0(0 to 31) => ob_rd_data(0 to 31), + do0(32 to 38) => ob_rd_data_ecc0(0 to 6), + do0(39 to 41) => unused(0 to 2), + + do0(42 to 73) => ob_rd_data(32 to 63), + do0(74 to 80) => ob_rd_data_ecc1(0 to 6), + do0(81 to 83) => unused(3 to 5), + + do0(84 to 115) => ob_rd_data(64 to 95), + do0(116 to 122) => ob_rd_data_ecc2(0 to 6), + do0(123 to 125) => unused(6 to 8), + + do0(126 to 157) => ob_rd_data(96 to 127), + do0(158 to 164) => ob_rd_data_ecc3(0 to 6), + do0(165 to 167) => unused(9 to 11), + + abist_di => abist_di_0, + abist_bw_odd => abist_g8t_bw_1, + abist_bw_even => abist_g8t_bw_0, + abist_wr_adr => abist_waddr_0(4 to 9), + wr_abst_act => abist_g8t_wenb, + abist_rd0_adr => abist_raddr_0(4 to 9), + rd0_abst_act => abist_g8t1p_renb_0, + tc_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc, + abist_ena_1 => pc_bx_abist_ena_dc, + abist_g8t_rd0_comp_ena => abist_wl64_comp_ena, + abist_raw_dc_b => pc_bx_abist_raw_dc_b, + obs0_abist_cmp => abist_g8t_dcomp, + + lcb_bolt_sl_thold_0 => bolt_sl_thold_0, + pc_bo_enable_2 => bolt_enable_2, + pc_bo_reset => pc_bx_bo_reset, + pc_bo_unload => pc_bx_bo_unload, + pc_bo_repair => pc_bx_bo_repair, + pc_bo_shdata => pc_bx_bo_shdata, + pc_bo_select => pc_bx_bo_select(0 to 1), + bo_pc_failout => bx_pc_bo_fail(0 to 1), + bo_pc_diagloop => bx_pc_bo_diagout(0 to 1), + tri_lcb_mpw1_dc_b => mpw1_dc_b, + tri_lcb_mpw2_dc_b => mpw2_dc_b, + tri_lcb_delay_lclkr_dc => delay_lclkr_dc, + tri_lcb_clkoff_dc_b => clkoff_dc_b, + tri_lcb_act_dis_dc => tidn, + + gnd => gnd, + vdd => vdd, + vcs => vcs, + nclk => nclk, + rd0_act => ob_rd_logic_act, + wr_act => ex5_mtdp_val_q, + sg_0 => sg_0, + abst_sl_thold_0 => abst_sl_thold_0, + ary_nsl_thold_0 => ary_nsl_thold_0, + time_sl_thold_0 => time_sl_thold_0, + repr_sl_thold_0 => repr_sl_thold_0, + scan_dis_dc_b => an_ac_scan_dis_dc_b, + scan_diag_dc => an_ac_scan_diag_dc, + ccflush_dc => pc_bx_ccflush_dc, + + ary0_clkoff_dc_b => ary0_clkoff_dc_b, + ary0_d_mode_dc => ary0_d_mode_dc, + ary0_mpw1_dc_b => ary0_mpw1_dc_b_v, + ary0_mpw2_dc_b => ary0_mpw2_dc_b, + ary0_delay_lclkr_dc => ary0_delay_lclkr_dc_v, + + ary1_clkoff_dc_b => ary1_clkoff_dc_b, + ary1_d_mode_dc => ary1_d_mode_dc, + ary1_mpw1_dc_b => ary1_mpw1_dc_b_v, + ary1_mpw2_dc_b => ary1_mpw2_dc_b, + ary1_delay_lclkr_dc => ary1_delay_lclkr_dc_v, + + abst_scan_in => abst_scan_in, + time_scan_in => time_scan_in_q, + repr_scan_in => repr_scan_in_q, + abst_scan_out => ob_abst_scan_out, + time_scan_out => ob_time_scan_out, + repr_scan_out => ob_repr_scan_out +); + + + +latch_ob_rd_data1 : tri_rlmreg_p + generic map (width => ob_rd_data1_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_rd_data1_offset to ob_rd_data1_offset + ob_rd_data1_l2'length-1), + scout => sov(ob_rd_data1_offset to ob_rd_data1_offset + ob_rd_data1_l2'length-1), + din => ob_rd_data(0 to 127), + dout => ob_rd_data1_l2 ); + +latch_ob_rd_data_ecc0 : tri_rlmreg_p + generic map (width => ob_rd_data_ecc0'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_rd_data_ecc0_offset to ob_rd_data_ecc0_offset + ob_rd_data_ecc0'length-1), + scout => sov(ob_rd_data_ecc0_offset to ob_rd_data_ecc0_offset + ob_rd_data_ecc0'length-1), + din => ob_rd_data_ecc0(0 to 6), + dout => ob_rd_data_ecc0_l2 ); + +latch_ob_rd_data_ecc1 : tri_rlmreg_p + generic map (width => ob_rd_data_ecc1'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_rd_data_ecc1_offset to ob_rd_data_ecc1_offset + ob_rd_data_ecc1'length-1), + scout => sov(ob_rd_data_ecc1_offset to ob_rd_data_ecc1_offset + ob_rd_data_ecc1'length-1), + din => ob_rd_data_ecc1(0 to 6), + dout => ob_rd_data_ecc1_l2 ); + +latch_ob_rd_data_ecc2 : tri_rlmreg_p + generic map (width => ob_rd_data_ecc2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_rd_data_ecc2_offset to ob_rd_data_ecc2_offset + ob_rd_data_ecc2'length-1), + scout => sov(ob_rd_data_ecc2_offset to ob_rd_data_ecc2_offset + ob_rd_data_ecc2'length-1), + din => ob_rd_data_ecc2(0 to 6), + dout => ob_rd_data_ecc2_l2 ); + +latch_ob_rd_data_ecc3 : tri_rlmreg_p + generic map (width => ob_rd_data_ecc3'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_rd_data_ecc3_offset to ob_rd_data_ecc3_offset + ob_rd_data_ecc3'length-1), + scout => sov(ob_rd_data_ecc3_offset to ob_rd_data_ecc3_offset + ob_rd_data_ecc3'length-1), + din => ob_rd_data_ecc3(0 to 6), + dout => ob_rd_data_ecc3_l2 ); + + + + +ob_do_eccgen0: entity work.xuq_eccgen(xuq_eccgen) + generic map ( regsize => 32 ) + port map(din(0 to 31) => ob_rd_data1_l2(0 to 31), + din(32 to 38) => ob_rd_data_ecc0_l2, + syn => ob_rd_data_nsyn0 ); + +ob_do_eccgen1: entity work.xuq_eccgen(xuq_eccgen) + generic map ( regsize => 32 ) + port map(din(0 to 31) => ob_rd_data1_l2(32 to 63), + din(32 to 38) => ob_rd_data_ecc1_l2, + syn => ob_rd_data_nsyn1 ); + +ob_do_eccgen2: entity work.xuq_eccgen(xuq_eccgen) + generic map ( regsize => 32 ) + port map(din(0 to 31) => ob_rd_data1_l2(64 to 95), + din(32 to 38) => ob_rd_data_ecc2_l2, + syn => ob_rd_data_nsyn2 ); + +ob_do_eccgen3: entity work.xuq_eccgen(xuq_eccgen) + generic map ( regsize => 32 ) + port map(din(0 to 31) => ob_rd_data1_l2(96 to 127), + din(32 to 38) => ob_rd_data_ecc3_l2, + syn => ob_rd_data_nsyn3 ); + +ob_di_eccchk0: entity work.xuq_eccchk(xuq_eccchk) + generic map ( regsize => 32 ) + port map(din => ob_rd_data1_l2(0 to 31), + EnCorr => '1', + NSyn => ob_rd_data_nsyn0, + Corrd => ob_rd_data_cor(0 to 31), + sbe => ob_ary_sbe(0), + ue => ob_ary_ue(0) ); + + +ob_di_eccchk1: entity work.xuq_eccchk(xuq_eccchk) + generic map ( regsize => 32 ) + port map(din => ob_rd_data1_l2(32 to 63), + EnCorr => '1', + NSyn => ob_rd_data_nsyn1, + Corrd => ob_rd_data_cor(32 to 63), + sbe => ob_ary_sbe(1), + ue => ob_ary_ue(1) ); + +ob_di_eccchk2: entity work.xuq_eccchk(xuq_eccchk) + generic map ( regsize => 32 ) + port map(din => ob_rd_data1_l2(64 to 95), + EnCorr => '1', + NSyn => ob_rd_data_nsyn2, + Corrd => ob_rd_data_cor(64 to 95), + sbe => ob_ary_sbe(2), + ue => ob_ary_ue(2) ); + +ob_di_eccchk3: entity work.xuq_eccchk(xuq_eccchk) + generic map ( regsize => 32 ) + port map(din => ob_rd_data1_l2(96 to 127), + EnCorr => '1', + NSyn => ob_rd_data_nsyn3, + Corrd => ob_rd_data_cor(96 to 127), + sbe => ob_ary_sbe(3), + ue => ob_ary_ue(3) ); + +latch_ob_ary_sbe : tri_rlmreg_p + generic map (width => ob_ary_sbe_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_ary_sbe_offset to ob_ary_sbe_offset + ob_ary_sbe_q'length-1), + scout => sov(ob_ary_sbe_offset to ob_ary_sbe_offset + ob_ary_sbe_q'length-1), + din => ob_ary_sbe(0 to 3), + dout => ob_ary_sbe_q(0 to 3) ); + +latch_ob_ary_ue : tri_rlmreg_p + generic map (width => ob_ary_ue_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_ary_ue_offset to ob_ary_ue_offset + ob_ary_ue_q'length-1), + scout => sov(ob_ary_ue_offset to ob_ary_ue_offset + ob_ary_ue_q'length-1), + din => ob_ary_ue(0 to 3), + dout => ob_ary_ue_q(0 to 3) ); + +ob_ary_sbe_or <= (ob_ary_sbe_q(0) or ob_ary_sbe_q(1) or ob_ary_sbe_q(2) or ob_ary_sbe_q(3)) and bx_lsu_ob_req_val_int; + +ob_ary_ue_or <= (ob_ary_ue_q(0) or ob_ary_ue_q(1) or ob_ary_ue_q(2) or ob_ary_ue_q(3)) and bx_lsu_ob_req_val_int; + + + + +latch_ob_rd_data_cor : tri_rlmreg_p + generic map (width => ob_rd_data_cor'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_rd_data_cor_offset to ob_rd_data_cor_offset + ob_rd_data_cor'length-1), + scout => sov(ob_rd_data_cor_offset to ob_rd_data_cor_offset + ob_rd_data_cor'length-1), + din => ob_rd_data_cor(0 to 127), + dout => ob_rd_data_cor_l2 ); + + + +latch_outbox_ecc_err : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(outbox_ecc_err_offset to outbox_ecc_err_offset), + scout => sov(outbox_ecc_err_offset to outbox_ecc_err_offset), + din(0) => ob_ary_sbe_or, + dout(0) => outbox_ecc_err_q ); + +latch_outbox_ue : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(outbox_ue_offset to outbox_ue_offset), + scout => sov(outbox_ue_offset to outbox_ue_offset), + din(0) => ob_ary_ue_or, + dout(0) => outbox_ue_q ); + + outbox_err_rpt : entity tri.tri_direct_err_rpt + generic map + ( width => 2 + , expand_type => expand_type + ) + port map + ( vd => vdd + , gd => gnd + , err_in(0) => outbox_ecc_err_q + , err_in(1) => outbox_ue_q + , err_out(0) => bx_pc_err_outbox_ecc + , err_out(1) => bx_pc_err_outbox_ue + ); + + +ob0_rd_entry_ptr_d <= std_ulogic_vector(unsigned(ob0_rd_entry_ptr_q) + 1) when ob0_buf_done='1' else + ob0_rd_entry_ptr_q(0 to 1); + +ob1_rd_entry_ptr_d <= std_ulogic_vector(unsigned(ob1_rd_entry_ptr_q) + 1) when ob1_buf_done='1' else + ob1_rd_entry_ptr_q(0 to 1); + +ob2_rd_entry_ptr_d <= std_ulogic_vector(unsigned(ob2_rd_entry_ptr_q) + 1) when ob2_buf_done='1' else + ob2_rd_entry_ptr_q(0 to 1); + +ob3_rd_entry_ptr_d <= std_ulogic_vector(unsigned(ob3_rd_entry_ptr_q) + 1) when ob3_buf_done='1' else + ob3_rd_entry_ptr_q(0 to 1); + +latch_ob0_rd_entry_ptr : tri_rlmreg_p + generic map (width => ob0_rd_entry_ptr_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob0_rd_entry_ptr_offset to ob0_rd_entry_ptr_offset + ob0_rd_entry_ptr_q'length-1), + scout => sov(ob0_rd_entry_ptr_offset to ob0_rd_entry_ptr_offset + ob0_rd_entry_ptr_q'length-1), + din => ob0_rd_entry_ptr_d(0 to 1), + dout => ob0_rd_entry_ptr_q(0 to 1) ); + +latch_ob1_rd_entry_ptr : tri_rlmreg_p + generic map (width => ob1_rd_entry_ptr_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob1_rd_entry_ptr_offset to ob1_rd_entry_ptr_offset + ob1_rd_entry_ptr_q'length-1), + scout => sov(ob1_rd_entry_ptr_offset to ob1_rd_entry_ptr_offset + ob1_rd_entry_ptr_q'length-1), + din => ob1_rd_entry_ptr_d(0 to 1), + dout => ob1_rd_entry_ptr_q(0 to 1) ); + +latch_ob2_rd_entry_ptr : tri_rlmreg_p + generic map (width => ob2_rd_entry_ptr_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob2_rd_entry_ptr_offset to ob2_rd_entry_ptr_offset + ob2_rd_entry_ptr_q'length-1), + scout => sov(ob2_rd_entry_ptr_offset to ob2_rd_entry_ptr_offset + ob2_rd_entry_ptr_q'length-1), + din => ob2_rd_entry_ptr_d(0 to 1), + dout => ob2_rd_entry_ptr_q(0 to 1) ); + +latch_ob3_rd_entry_ptr : tri_rlmreg_p + generic map (width => ob3_rd_entry_ptr_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob3_rd_entry_ptr_offset to ob3_rd_entry_ptr_offset + ob3_rd_entry_ptr_q'length-1), + scout => sov(ob3_rd_entry_ptr_offset to ob3_rd_entry_ptr_offset + ob3_rd_entry_ptr_q'length-1), + din => ob3_rd_entry_ptr_d(0 to 1), + dout => ob3_rd_entry_ptr_q(0 to 1) ); + + +with ob0_rd_entry_ptr_q(0 to 1) select + ob0_to_nd_status_reg <= ob0_buf0_status_val & ob0_buf0_status_q(1 to 17) when "00", + ob0_buf1_status_val & ob0_buf1_status_q(1 to 17) when "01", + ob0_buf2_status_val & ob0_buf2_status_q(1 to 17) when "10", + ob0_buf3_status_val & ob0_buf3_status_q(1 to 17) when others; + +with ob1_rd_entry_ptr_q(0 to 1) select + ob1_to_nd_status_reg <= ob1_buf0_status_val & ob1_buf0_status_q(1 to 17) when "00", + ob1_buf1_status_val & ob1_buf1_status_q(1 to 17) when "01", + ob1_buf2_status_val & ob1_buf2_status_q(1 to 17) when "10", + ob1_buf3_status_val & ob1_buf3_status_q(1 to 17) when others; + +with ob2_rd_entry_ptr_q(0 to 1) select + ob2_to_nd_status_reg <= ob2_buf0_status_val & ob2_buf0_status_q(1 to 17) when "00", + ob2_buf1_status_val & ob2_buf1_status_q(1 to 17) when "01", + ob2_buf2_status_val & ob2_buf2_status_q(1 to 17) when "10", + ob2_buf3_status_val & ob2_buf3_status_q(1 to 17) when others; + +with ob3_rd_entry_ptr_q(0 to 1) select + ob3_to_nd_status_reg <= ob3_buf0_status_val & ob3_buf0_status_q(1 to 17) when "00", + ob3_buf1_status_val & ob3_buf1_status_q(1 to 17) when "01", + ob3_buf2_status_val & ob3_buf2_status_q(1 to 17) when "10", + ob3_buf3_status_val & ob3_buf3_status_q(1 to 17) when others; + + + +ob_to_nd_status_reg_vals(0 to 3) <= ob0_to_nd_status_reg(0) & + ob1_to_nd_status_reg(0) & + ob2_to_nd_status_reg(0) & + ob3_to_nd_status_reg(0); + + +ob_to_node_sel_d(0) <= (ob_to_nd_status_reg_vals(0) and ob_to_node_sel_q(3)) or + (ob_to_nd_status_reg_vals(0) and ob_to_node_sel_q(2) and ob_to_nd_status_reg_vals(3)='0' ) or + (ob_to_nd_status_reg_vals(0) and ob_to_node_sel_q(1) and ob_to_nd_status_reg_vals(2 to 3)="00" ) or + (ob_to_nd_status_reg_vals(0) and ob_to_node_sel_q(0) and ob_to_nd_status_reg_vals(1 to 3)="000" ) or + (ob_to_node_sel_q(0) and ob_to_nd_status_reg_vals(0 to 3)="0000" ); + +ob_to_node_sel_d(1) <= (ob_to_nd_status_reg_vals(1) and ob_to_node_sel_q(0)) or + (ob_to_nd_status_reg_vals(1) and ob_to_node_sel_q(3) and ob_to_nd_status_reg_vals(0)='0' ) or + (ob_to_nd_status_reg_vals(1) and ob_to_node_sel_q(2) and ob_to_nd_status_reg_vals(3)='0' and ob_to_nd_status_reg_vals(0)='0' ) or + (ob_to_nd_status_reg_vals(1) and ob_to_node_sel_q(1) and ob_to_nd_status_reg_vals(2 to 3)="00" and ob_to_nd_status_reg_vals(0)='0' ) or + (ob_to_node_sel_q(1) and ob_to_nd_status_reg_vals(0 to 3)="0000" ); + +ob_to_node_sel_d(2) <= (ob_to_nd_status_reg_vals(2) and ob_to_node_sel_q(1)) or + (ob_to_nd_status_reg_vals(2) and ob_to_node_sel_q(0) and ob_to_nd_status_reg_vals(1)='0' ) or + (ob_to_nd_status_reg_vals(2) and ob_to_node_sel_q(3) and ob_to_nd_status_reg_vals(0 to 1)="00" ) or + (ob_to_nd_status_reg_vals(2) and ob_to_node_sel_q(2) and ob_to_nd_status_reg_vals(3)='0' and ob_to_nd_status_reg_vals(0 to 1)="00" ) or + (ob_to_node_sel_q(2) and ob_to_nd_status_reg_vals(0 to 3)="0000" ); + +ob_to_node_sel_d(3) <= (ob_to_nd_status_reg_vals(3) and ob_to_node_sel_q(2)) or + (ob_to_nd_status_reg_vals(3) and ob_to_node_sel_q(1) and ob_to_nd_status_reg_vals(2)='0' ) or + (ob_to_nd_status_reg_vals(3) and ob_to_node_sel_q(0) and ob_to_nd_status_reg_vals(1 to 2)="00" ) or + (ob_to_nd_status_reg_vals(3) and ob_to_node_sel_q(3) and ob_to_nd_status_reg_vals(0 to 2)="000" ) or + (ob_to_node_sel_q(3) and ob_to_nd_status_reg_vals(0 to 3)="0000" ); + + + +latch_ob_to_node_sel : tri_rlmreg_p + generic map (width => ob_to_node_sel_q'length, init => 1, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_to_node_sel_offset to ob_to_node_sel_offset + ob_to_node_sel_q'length-1), + scout => sov(ob_to_node_sel_offset to ob_to_node_sel_offset + ob_to_node_sel_q'length-1), + din => ob_to_node_sel_d(0 to 3), + dout => ob_to_node_sel_q(0 to 3) ); + +ob_to_node_sel_sav_d(0 to 3) <= ob_to_node_sel_q(0 to 3) when send_ob_idle='1' else + ob_to_node_sel_sav_q(0 to 3); + +latch_ob_to_node_sel_sav : tri_rlmreg_p + generic map (width => ob_to_node_sel_sav_q'length, init => 1, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_to_node_sel_sav_offset to ob_to_node_sel_sav_offset + ob_to_node_sel_sav_q'length-1), + scout => sov(ob_to_node_sel_sav_offset to ob_to_node_sel_sav_offset + ob_to_node_sel_sav_q'length-1), + din => ob_to_node_sel_sav_d(0 to 3), + dout => ob_to_node_sel_sav_q(0 to 3) ); + +ob_to_node_status_reg(1 to 17) <= gate_and( ob_to_node_sel_sav_q(0), ob0_to_nd_status_reg(1 to 17) ) or + gate_and( ob_to_node_sel_sav_q(1), ob1_to_nd_status_reg(1 to 17) ) or + gate_and( ob_to_node_sel_sav_q(2), ob2_to_nd_status_reg(1 to 17) ) or + gate_and( ob_to_node_sel_sav_q(3), ob3_to_nd_status_reg(1 to 17) ); + + +ob_to_nd_val_t0 <= send_ob_idle and ob0_to_nd_status_reg(0) and ob_to_node_sel_q(0); +ob_to_nd_val_t1 <= send_ob_idle and ob1_to_nd_status_reg(0) and ob_to_node_sel_q(1); +ob_to_nd_val_t2 <= send_ob_idle and ob2_to_nd_status_reg(0) and ob_to_node_sel_q(2); +ob_to_nd_val_t3 <= send_ob_idle and ob3_to_nd_status_reg(0) and ob_to_node_sel_q(3); + + + + +latch_lsu_cmd_avail : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(lsu_cmd_avail_offset to lsu_cmd_avail_offset), + scout => sov(lsu_cmd_avail_offset to lsu_cmd_avail_offset), + din(0) => lsu_bx_cmd_avail, + dout(0) => lsu_cmd_avail_q ); + +latch_lsu_cmd_sent : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(lsu_cmd_sent_offset to lsu_cmd_sent_offset), + scout => sov(lsu_cmd_sent_offset to lsu_cmd_sent_offset), + din(0) => lsu_bx_cmd_sent, + dout(0) => lsu_cmd_sent_q ); + +latch_lsu_cmd_stall : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(lsu_cmd_stall_offset to lsu_cmd_stall_offset), + scout => sov(lsu_cmd_stall_offset to lsu_cmd_stall_offset), + din(0) => lsu_bx_cmd_stall, + dout(0) => lsu_cmd_stall_q ); + + + +ob_cmd_sent_count_d(0 to 2) <= "000" when ob_to_nd_done_d = '1' else + std_ulogic_vector(unsigned(ob_cmd_sent_count_q) + 1) when lsu_cmd_sent_q = '1' else + ob_cmd_sent_count_q(0 to 2); + + +latch_ob_cmd_sent_count : tri_rlmreg_p + generic map (width => ob_cmd_sent_count_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_cmd_sent_count_offset to ob_cmd_sent_count_offset + ob_cmd_sent_count_q'length-1), + scout => sov(ob_cmd_sent_count_offset to ob_cmd_sent_count_offset + ob_cmd_sent_count_q'length-1), + din => ob_cmd_sent_count_d(0 to 2), + dout => ob_cmd_sent_count_q(0 to 2) ); + + +ob_to_nd_ready <= ((ob_to_nd_val_t0 and ob_credit_t0) or + (ob_to_nd_val_t1 and ob_credit_t1) or + (ob_to_nd_val_t2 and ob_credit_t2) or + (ob_to_nd_val_t3 and ob_credit_t3)) and lsu_cmd_avail_q; + +ob_lsu_complete <= (((ob_cmd_sent_count_q = "100") and (ob_to_node_status_reg(1 to 2) = "11")) or + ((ob_cmd_sent_count_q = "011") and (ob_to_node_status_reg(1 to 2) = "10")) or + ((ob_cmd_sent_count_q = "010") and (ob_to_node_status_reg(1 to 2) = "01")) or + ((ob_cmd_sent_count_q = "001") and (ob_to_node_status_reg(1 to 2) = "00"))) and lsu_cmd_sent_q; + +send_ob_idle <= send_ob_state_q(6); +send_ob_data1 <= send_ob_state_q(0); +send_ob_data2 <= send_ob_state_q(1); +send_ob_data3 <= send_ob_state_q(2); +send_ob_data4 <= send_ob_state_q(3); +send_ob_ditc <= send_ob_state_q(4); +send_ob_wait <= send_ob_state_q(5); + +send_ob_state_mach: process(send_ob_idle, send_ob_data1, send_ob_data2, send_ob_data3, send_ob_data4, send_ob_ditc, send_ob_wait, ob_to_nd_ready, ob_to_node_status_reg(1 to 2), lsu_cmd_stall_q, ob_cmd_sent_count_q, ob_lsu_complete, ob_ary_ue_or) begin + + send_ob_nxt_idle <= '0'; + send_ob_nxt_data1 <= '0'; + send_ob_nxt_data2 <= '0'; + send_ob_nxt_data3 <= '0'; + send_ob_nxt_data4 <= '0'; + send_ob_nxt_ditc <= '0'; + send_ob_nxt_wait <= '0'; + ob_to_nd_done_d <= '0'; + + if send_ob_idle = '1' then + if ob_to_nd_ready = '1' then + send_ob_nxt_data1 <= '1'; + else + send_ob_nxt_idle <= '1'; + end if; + end if; + + if send_ob_data1 = '1' then + if ob_ary_ue_or = '1' then + send_ob_nxt_idle <= '1'; + ob_to_nd_done_d <= '1'; + elsif ob_to_node_status_reg(1 to 2) = "00" then + send_ob_nxt_ditc <= '1'; + else + send_ob_nxt_data2 <= '1'; + end if; + end if; + + if send_ob_data2 = '1' then + if ob_ary_ue_or = '1' then + send_ob_nxt_idle <= '1'; + ob_to_nd_done_d <= '1'; + elsif lsu_cmd_stall_q = '0' then + if ob_to_node_status_reg(1 to 2) = "01" then + send_ob_nxt_ditc <= '1'; + else + send_ob_nxt_data3 <= '1'; + end if; + else + send_ob_nxt_data2 <= '1'; + end if; + end if; + + if send_ob_data3 = '1' then + if ob_ary_ue_or = '1' then + send_ob_nxt_idle <= '1'; + ob_to_nd_done_d <= '1'; + elsif lsu_cmd_stall_q = '0' then + if ob_to_node_status_reg(1 to 2) = "10" then + send_ob_nxt_ditc <= '1'; + else + send_ob_nxt_data4 <= '1'; + end if; + else + send_ob_nxt_data3 <= '1'; + end if; + end if; + + if send_ob_data4 = '1' then + if ob_ary_ue_or = '1' then + send_ob_nxt_idle <= '1'; + ob_to_nd_done_d <= '1'; + elsif lsu_cmd_stall_q = '0' then + send_ob_nxt_ditc <= '1'; + else + send_ob_nxt_data4 <= '1'; + end if; + end if; + + if send_ob_ditc = '1' then + if ob_ary_ue_or = '1' then + send_ob_nxt_idle <= '1'; + ob_to_nd_done_d <= '1'; + elsif lsu_cmd_stall_q = '0' then + send_ob_nxt_wait <= '1'; + else + send_ob_nxt_ditc <= '1'; + end if; + end if; + + if send_ob_wait = '1' then + if ob_ary_ue_or = '1' then + send_ob_nxt_idle <= '1'; + ob_to_nd_done_d <= '1'; + elsif lsu_cmd_stall_q = '0' then + if (ob_lsu_complete = '1') then + send_ob_nxt_idle <= '1'; + ob_to_nd_done_d <= '1'; + else + send_ob_nxt_wait <= '1'; + end if; + else + if ob_cmd_sent_count_q = "000" then + send_ob_nxt_data2 <= '1'; + elsif ob_cmd_sent_count_q = "001" then + send_ob_nxt_data3 <= '1'; + elsif ob_cmd_sent_count_q = "010" then + send_ob_nxt_data4 <= '1'; + elsif ob_cmd_sent_count_q = "011" then + send_ob_nxt_ditc <= '1'; + else + send_ob_nxt_wait <= '1'; + end if; + end if; + end if; + +end process; + +send_ob_nxt_state(6) <= send_ob_nxt_idle; +send_ob_nxt_state(0) <= send_ob_nxt_data1; +send_ob_nxt_state(1) <= send_ob_nxt_data2; +send_ob_nxt_state(2) <= send_ob_nxt_data3; +send_ob_nxt_state(3) <= send_ob_nxt_data4; +send_ob_nxt_state(4) <= send_ob_nxt_ditc; +send_ob_nxt_state(5) <= send_ob_nxt_wait; + +latch_send_ob_state : tri_rlmreg_p + generic map (width => send_ob_state_q'length, init => 1, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(send_ob_state_offset to send_ob_state_offset + send_ob_state_q'length-1), + scout => sov(send_ob_state_offset to send_ob_state_offset + send_ob_state_q'length-1), + din => send_ob_nxt_state, + dout => send_ob_state_q ); + + + + +ob0_buf_done <= ob_to_nd_done_d and ob_to_node_sel_sav_q(0); +ob1_buf_done <= ob_to_nd_done_d and ob_to_node_sel_sav_q(1); +ob2_buf_done <= ob_to_nd_done_d and ob_to_node_sel_sav_q(2); +ob3_buf_done <= ob_to_nd_done_d and ob_to_node_sel_sav_q(3); + +ob0_buf0_done <= ob_to_nd_done_d and ob_to_node_sel_sav_q(0) and ob0_rd_entry_ptr_q(0 to 1)="00"; +ob0_buf1_done <= ob_to_nd_done_d and ob_to_node_sel_sav_q(0) and ob0_rd_entry_ptr_q(0 to 1)="01"; +ob0_buf2_done <= ob_to_nd_done_d and ob_to_node_sel_sav_q(0) and ob0_rd_entry_ptr_q(0 to 1)="10"; +ob0_buf3_done <= ob_to_nd_done_d and ob_to_node_sel_sav_q(0) and ob0_rd_entry_ptr_q(0 to 1)="11"; +ob1_buf0_done <= ob_to_nd_done_d and ob_to_node_sel_sav_q(1) and ob1_rd_entry_ptr_q(0 to 1)="00"; +ob1_buf1_done <= ob_to_nd_done_d and ob_to_node_sel_sav_q(1) and ob1_rd_entry_ptr_q(0 to 1)="01"; +ob1_buf2_done <= ob_to_nd_done_d and ob_to_node_sel_sav_q(1) and ob1_rd_entry_ptr_q(0 to 1)="10"; +ob1_buf3_done <= ob_to_nd_done_d and ob_to_node_sel_sav_q(1) and ob1_rd_entry_ptr_q(0 to 1)="11"; +ob2_buf0_done <= ob_to_nd_done_d and ob_to_node_sel_sav_q(2) and ob2_rd_entry_ptr_q(0 to 1)="00"; +ob2_buf1_done <= ob_to_nd_done_d and ob_to_node_sel_sav_q(2) and ob2_rd_entry_ptr_q(0 to 1)="01"; +ob2_buf2_done <= ob_to_nd_done_d and ob_to_node_sel_sav_q(2) and ob2_rd_entry_ptr_q(0 to 1)="10"; +ob2_buf3_done <= ob_to_nd_done_d and ob_to_node_sel_sav_q(2) and ob2_rd_entry_ptr_q(0 to 1)="11"; +ob3_buf0_done <= ob_to_nd_done_d and ob_to_node_sel_sav_q(3) and ob3_rd_entry_ptr_q(0 to 1)="00"; +ob3_buf1_done <= ob_to_nd_done_d and ob_to_node_sel_sav_q(3) and ob3_rd_entry_ptr_q(0 to 1)="01"; +ob3_buf2_done <= ob_to_nd_done_d and ob_to_node_sel_sav_q(3) and ob3_rd_entry_ptr_q(0 to 1)="10"; +ob3_buf3_done <= ob_to_nd_done_d and ob_to_node_sel_sav_q(3) and ob3_rd_entry_ptr_q(0 to 1)="11"; + + + +ob_to_node_selected_thrd(0) <= ob_to_node_sel_sav_q(2) or ob_to_node_sel_sav_q(3); +ob_to_node_selected_thrd(1) <= ob_to_node_sel_sav_q(1) or ob_to_node_sel_sav_q(3); + +ob_to_node_selected_rd_ptr(0 to 1) <= gate_and(ob_to_node_sel_sav_q(0) , ob0_rd_entry_ptr_q(0 to 1) ) or + gate_and(ob_to_node_sel_sav_q(1) , ob1_rd_entry_ptr_q(0 to 1) ) or + gate_and(ob_to_node_sel_sav_q(2) , ob2_rd_entry_ptr_q(0 to 1) ) or + gate_and(ob_to_node_sel_sav_q(3) , ob3_rd_entry_ptr_q(0 to 1) ); + +send_ob_seq_ptr(0) <= send_ob_data3 or send_ob_data4; +send_ob_seq_ptr(1) <= send_ob_data2 or send_ob_data4; + +ob_to_node_data_ptr(0 to 1) <= send_ob_seq_ptr(0 to 1) when lsu_cmd_stall_q = '0' else + "01" when ob_cmd_sent_count_q = "000" else + "10" when ob_cmd_sent_count_q = "001" else + "11"; + +ob_ary_rd_addr(0 to 5) <= ob_to_node_selected_thrd & ob_to_node_selected_rd_ptr & ob_to_node_data_ptr; + + + +send_ob_data_val <= ((send_ob_data1 or send_ob_data2 or send_ob_data3 or send_ob_data4) and not lsu_cmd_stall_q); + +dly_ob_cmd_val_d(0) <= send_ob_data_val and not ob_ary_ue_or; +dly_ob_cmd_val_d(1) <= dly_ob_cmd_val_q(0) and not ob_ary_ue_or; + +latch_dly_ob_cmd_val : tri_rlmreg_p + generic map (width => dly_ob_cmd_val_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(dly_ob_cmd_val_offset to dly_ob_cmd_val_offset + dly_ob_cmd_val_q'length-1), + scout => sov(dly_ob_cmd_val_offset to dly_ob_cmd_val_offset + dly_ob_cmd_val_q'length-1), + din => dly_ob_cmd_val_d(0 to 1), + dout => dly_ob_cmd_val_q(0 to 1) ); + +bx_lsu_ob_pwr_tok <= dly_ob_cmd_val_q(1) or dly_ob_ditc_val_q(1); + +bx_lsu_ob_req_val_d <= dly_ob_cmd_val_q(1) and not ob_ary_ue_or; + +latch_bxlsu_ob_req_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(bxlsu_ob_req_val_offset to bxlsu_ob_req_val_offset), + scout => sov(bxlsu_ob_req_val_offset to bxlsu_ob_req_val_offset), + din(0) => bx_lsu_ob_req_val_d, + dout(0) => bx_lsu_ob_req_val_int ); + +bx_lsu_ob_req_val <= bx_lsu_ob_req_val_int; + +send_ob_ditc_val <= (send_ob_ditc and not lsu_cmd_stall_q); + +dly_ob_ditc_val_d(0) <= send_ob_ditc_val and not ob_ary_ue_or; +dly_ob_ditc_val_d(1) <= dly_ob_ditc_val_q(0) and not ob_ary_ue_or; + +latch_dly_ob_ditc_val : tri_rlmreg_p + generic map (width => dly_ob_ditc_val_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(dly_ob_ditc_val_offset to dly_ob_ditc_val_offset + dly_ob_ditc_val_q'length-1), + scout => sov(dly_ob_ditc_val_offset to dly_ob_ditc_val_offset + dly_ob_ditc_val_q'length-1), + din => dly_ob_ditc_val_d(0 to 1), + dout => dly_ob_ditc_val_q(0 to 1) ); + +latch_bxlsu_ob_ditc_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(bxlsu_ob_ditc_val_offset to bxlsu_ob_ditc_val_offset), + scout => sov(bxlsu_ob_ditc_val_offset to bxlsu_ob_ditc_val_offset), + din(0) => dly_ob_ditc_val_q(1), + dout(0) => bx_lsu_ob_ditc_val ); + +latch_dly_ob_qw : tri_rlmreg_p + generic map (width => dly_ob_qw'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(dly_ob_qw_offset to dly_ob_qw_offset + dly_ob_qw'length-1), + scout => sov(dly_ob_qw_offset to dly_ob_qw_offset + dly_ob_qw'length-1), + din => ob_to_node_data_ptr(0 to 1), + dout => dly_ob_qw ); + +latch_dly1_ob_qw : tri_rlmreg_p + generic map (width => dly1_ob_qw'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(dly1_ob_qw_offset to dly1_ob_qw_offset + dly1_ob_qw'length-1), + scout => sov(dly1_ob_qw_offset to dly1_ob_qw_offset + dly1_ob_qw'length-1), + din => dly_ob_qw, + dout => dly1_ob_qw ); + + +latch_bxlsu_ob_qw : tri_rlmreg_p + generic map (width => bx_lsu_ob_qw'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(bxlsu_ob_qw_offset to bxlsu_ob_qw_offset + bx_lsu_ob_qw'length-1), + scout => sov(bxlsu_ob_qw_offset to bxlsu_ob_qw_offset + bx_lsu_ob_qw'length-1), + din => dly1_ob_qw, + dout => bx_lsu_ob_qw ); + + +latch_bxlsu_ob_thrd : tri_rlmreg_p + generic map (width => bx_lsu_ob_thrd'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(bxlsu_ob_thrd_offset to bxlsu_ob_thrd_offset + bx_lsu_ob_thrd'length-1), + scout => sov(bxlsu_ob_thrd_offset to bxlsu_ob_thrd_offset + bx_lsu_ob_thrd'length-1), + din => ob_to_node_selected_thrd(0 to 1), + dout => bx_lsu_ob_thrd ); + +with ob_to_node_selected_thrd(0 to 1) select + ob_addr_d <= ditc_addr_t0_q when "00", + ditc_addr_t1_q when "01", + ditc_addr_t2_q when "10", + ditc_addr_t3_q when others; + +latch_bxlsu_ob_addr : tri_rlmreg_p + generic map (width => bx_lsu_ob_addr'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(bxlsu_ob_addr_offset to bxlsu_ob_addr_offset + bx_lsu_ob_addr'length-1), + scout => sov(bxlsu_ob_addr_offset to bxlsu_ob_addr_offset + bx_lsu_ob_addr'length-1), + din => ob_addr_d, + dout => bx_lsu_ob_addr ); + + +latch_bxlsu_ob_dest : tri_rlmreg_p + generic map (width => bx_lsu_ob_dest'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(bxlsu_ob_dest_offset to bxlsu_ob_dest_offset + bx_lsu_ob_dest'length-1), + scout => sov(bxlsu_ob_dest_offset to bxlsu_ob_dest_offset + bx_lsu_ob_dest'length-1), + din => ob_to_node_status_reg(3 to 17), + dout => bx_lsu_ob_dest ); + + +bx_lsu_ob_data <= ob_rd_data_cor_l2; + + + +latch_st_pop : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(st_pop_offset to st_pop_offset), + scout => sov(st_pop_offset to st_pop_offset), + din(0) => lsu_req_st_pop, + dout(0) => lat_st_pop ); + +latch_st_pop_thrd : tri_rlmreg_p + generic map (width => lat_st_pop_thrd'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(st_pop_thrd_offset to st_pop_thrd_offset + lat_st_pop_thrd'length-1), + scout => sov(st_pop_thrd_offset to st_pop_thrd_offset + lat_st_pop_thrd'length-1), + din => lsu_req_st_pop_thrd(0 to 2), + dout => lat_st_pop_thrd(0 to 2) ); + +ob_cmd_count_incr_t0(0 to 1) <= std_ulogic_vector(unsigned(ob_cmd_count_t0_q) + 1); +ob_cmd_count_decr_t0(0 to 1) <= std_ulogic_vector(unsigned(ob_cmd_count_t0_q) - 1); + +ob_cmd_count_incr_t1(0 to 1) <= std_ulogic_vector(unsigned(ob_cmd_count_t1_q) + 1); +ob_cmd_count_decr_t1(0 to 1) <= std_ulogic_vector(unsigned(ob_cmd_count_t1_q) - 1); + +ob_cmd_count_incr_t2(0 to 1) <= std_ulogic_vector(unsigned(ob_cmd_count_t2_q) + 1); +ob_cmd_count_decr_t2(0 to 1) <= std_ulogic_vector(unsigned(ob_cmd_count_t2_q) - 1); + +ob_cmd_count_incr_t3(0 to 1) <= std_ulogic_vector(unsigned(ob_cmd_count_t3_q) + 1); +ob_cmd_count_decr_t3(0 to 1) <= std_ulogic_vector(unsigned(ob_cmd_count_t3_q) - 1); + +ob_pop(0) <= lat_st_pop and lat_st_pop_thrd(2) and lat_st_pop_thrd(0 to 1)="00"; +ob_pop(1) <= lat_st_pop and lat_st_pop_thrd(2) and lat_st_pop_thrd(0 to 1)="01"; +ob_pop(2) <= lat_st_pop and lat_st_pop_thrd(2) and lat_st_pop_thrd(0 to 1)="10"; +ob_pop(3) <= lat_st_pop and lat_st_pop_thrd(2) and lat_st_pop_thrd(0 to 1)="11"; + +ob_cmd_count_t0_d(0 to 1) <= ob_cmd_count_incr_t0(0 to 1) when ( (ob_to_nd_val_t0 and ob_credit_t0 and lsu_cmd_avail_q) and not ob_pop(0)) = '1' else + ob_cmd_count_decr_t0(0 to 1) when (not (ob_to_nd_val_t0 and ob_credit_t0 and lsu_cmd_avail_q) and ob_pop(0)) = '1' else + ob_cmd_count_t0_q; + +ob_cmd_count_t1_d(0 to 1) <= ob_cmd_count_incr_t1(0 to 1) when ( (ob_to_nd_val_t1 and ob_credit_t1 and lsu_cmd_avail_q) and not ob_pop(1)) = '1' else + ob_cmd_count_decr_t1(0 to 1) when (not (ob_to_nd_val_t1 and ob_credit_t1 and lsu_cmd_avail_q) and ob_pop(1)) = '1' else + ob_cmd_count_t1_q; + +ob_cmd_count_t2_d(0 to 1) <= ob_cmd_count_incr_t2(0 to 1) when ( (ob_to_nd_val_t2 and ob_credit_t2 and lsu_cmd_avail_q) and not ob_pop(2)) = '1' else + ob_cmd_count_decr_t2(0 to 1) when (not (ob_to_nd_val_t2 and ob_credit_t2 and lsu_cmd_avail_q) and ob_pop(2)) = '1' else + ob_cmd_count_t2_q; + +ob_cmd_count_t3_d(0 to 1) <= ob_cmd_count_incr_t3(0 to 1) when ( (ob_to_nd_val_t3 and ob_credit_t3 and lsu_cmd_avail_q) and not ob_pop(3)) = '1' else + ob_cmd_count_decr_t3(0 to 1) when (not (ob_to_nd_val_t3 and ob_credit_t3 and lsu_cmd_avail_q) and ob_pop(3)) = '1' else + ob_cmd_count_t3_q; + +latch_ob_cmd_count_t0 : tri_rlmreg_p + generic map (width => ob_cmd_count_t0_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_cmd_count_t0_offset to ob_cmd_count_t0_offset + ob_cmd_count_t0_q'length-1), + scout => sov(ob_cmd_count_t0_offset to ob_cmd_count_t0_offset + ob_cmd_count_t0_q'length-1), + din => ob_cmd_count_t0_d(0 to 1), + dout => ob_cmd_count_t0_q(0 to 1) ); + +latch_ob_cmd_count_t1 : tri_rlmreg_p + generic map (width => ob_cmd_count_t1_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_cmd_count_t1_offset to ob_cmd_count_t1_offset + ob_cmd_count_t1_q'length-1), + scout => sov(ob_cmd_count_t1_offset to ob_cmd_count_t1_offset + ob_cmd_count_t1_q'length-1), + din => ob_cmd_count_t1_d(0 to 1), + dout => ob_cmd_count_t1_q(0 to 1) ); + +latch_ob_cmd_count_t2 : tri_rlmreg_p + generic map (width => ob_cmd_count_t2_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_cmd_count_t2_offset to ob_cmd_count_t2_offset + ob_cmd_count_t2_q'length-1), + scout => sov(ob_cmd_count_t2_offset to ob_cmd_count_t2_offset + ob_cmd_count_t2_q'length-1), + din => ob_cmd_count_t2_d(0 to 1), + dout => ob_cmd_count_t2_q(0 to 1) ); + +latch_ob_cmd_count_t3 : tri_rlmreg_p + generic map (width => ob_cmd_count_t3_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_cmd_count_t3_offset to ob_cmd_count_t3_offset + ob_cmd_count_t3_q'length-1), + scout => sov(ob_cmd_count_t3_offset to ob_cmd_count_t3_offset + ob_cmd_count_t3_q'length-1), + din => ob_cmd_count_t3_d(0 to 1), + dout => ob_cmd_count_t3_q(0 to 1) ); + +ob_credit_t0 <= not ob_cmd_count_t0_q(0); +ob_credit_t1 <= not ob_cmd_count_t1_q(0); +ob_credit_t2 <= not ob_cmd_count_t2_q(0); +ob_credit_t3 <= not ob_cmd_count_t3_q(0); + + + + + +wrt_ib0_buf0_status <= ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "00") and (ex4_ipc_ba_q = "10000") and (ib0_rd_entry_ptr_dly_q = "00"); +wrt_ib0_buf1_status <= ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "00") and (ex4_ipc_ba_q = "10000") and (ib0_rd_entry_ptr_dly_q = "01"); +wrt_ib0_buf2_status <= ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "00") and (ex4_ipc_ba_q = "10000") and (ib0_rd_entry_ptr_dly_q = "10"); +wrt_ib0_buf3_status <= ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "00") and (ex4_ipc_ba_q = "10000") and (ib0_rd_entry_ptr_dly_q = "11"); +wrt_ib1_buf0_status <= ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "01") and (ex4_ipc_ba_q = "10000") and (ib1_rd_entry_ptr_dly_q = "00"); +wrt_ib1_buf1_status <= ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "01") and (ex4_ipc_ba_q = "10000") and (ib1_rd_entry_ptr_dly_q = "01"); +wrt_ib1_buf2_status <= ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "01") and (ex4_ipc_ba_q = "10000") and (ib1_rd_entry_ptr_dly_q = "10"); +wrt_ib1_buf3_status <= ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "01") and (ex4_ipc_ba_q = "10000") and (ib1_rd_entry_ptr_dly_q = "11"); +wrt_ib2_buf0_status <= ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "10") and (ex4_ipc_ba_q = "10000") and (ib2_rd_entry_ptr_dly_q = "00"); +wrt_ib2_buf1_status <= ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "10") and (ex4_ipc_ba_q = "10000") and (ib2_rd_entry_ptr_dly_q = "01"); +wrt_ib2_buf2_status <= ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "10") and (ex4_ipc_ba_q = "10000") and (ib2_rd_entry_ptr_dly_q = "10"); +wrt_ib2_buf3_status <= ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "10") and (ex4_ipc_ba_q = "10000") and (ib2_rd_entry_ptr_dly_q = "11"); +wrt_ib3_buf0_status <= ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "11") and (ex4_ipc_ba_q = "10000") and (ib3_rd_entry_ptr_dly_q = "00"); +wrt_ib3_buf1_status <= ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "11") and (ex4_ipc_ba_q = "10000") and (ib3_rd_entry_ptr_dly_q = "01"); +wrt_ib3_buf2_status <= ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "11") and (ex4_ipc_ba_q = "10000") and (ib3_rd_entry_ptr_dly_q = "10"); +wrt_ib3_buf3_status <= ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "11") and (ex4_ipc_ba_q = "10000") and (ib3_rd_entry_ptr_dly_q = "11"); + +ib0_incr_ptr <= ex3_mtdp_val and (ex3_ipc_thrd_q = "00") and (ex3_ipc_ba_q = "10000"); +ib1_incr_ptr <= ex3_mtdp_val and (ex3_ipc_thrd_q = "01") and (ex3_ipc_ba_q = "10000"); +ib2_incr_ptr <= ex3_mtdp_val and (ex3_ipc_thrd_q = "10") and (ex3_ipc_ba_q = "10000"); +ib3_incr_ptr <= ex3_mtdp_val and (ex3_ipc_thrd_q = "11") and (ex3_ipc_ba_q = "10000"); + + +ex4_wrt_ib_status(0 to 15) <= wrt_ib0_buf0_status & wrt_ib0_buf1_status & wrt_ib0_buf2_status & wrt_ib0_buf3_status & + wrt_ib1_buf0_status & wrt_ib1_buf1_status & wrt_ib1_buf2_status & wrt_ib1_buf3_status & + wrt_ib2_buf0_status & wrt_ib2_buf1_status & wrt_ib2_buf2_status & wrt_ib2_buf3_status & + wrt_ib3_buf0_status & wrt_ib3_buf1_status & wrt_ib3_buf2_status & wrt_ib3_buf3_status; + +ex4_ib0_flushed <= ex4_mtdp_val_q and (ex4_ipc_thrd_q = "00") and (ex4_ipc_ba_q = "10000") and my_ex4_stg_flush; +ex4_ib1_flushed <= ex4_mtdp_val_q and (ex4_ipc_thrd_q = "01") and (ex4_ipc_ba_q = "10000") and my_ex4_stg_flush; +ex4_ib2_flushed <= ex4_mtdp_val_q and (ex4_ipc_thrd_q = "10") and (ex4_ipc_ba_q = "10000") and my_ex4_stg_flush; +ex4_ib3_flushed <= ex4_mtdp_val_q and (ex4_ipc_thrd_q = "11") and (ex4_ipc_ba_q = "10000") and my_ex4_stg_flush; + +latch_ex5_wrt_ib_status : tri_rlmreg_p + generic map (width => ex5_wrt_ib_status_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => mtdp_ex3_to_7_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex5_wrt_ib_status_offset to ex5_wrt_ib_status_offset + ex5_wrt_ib_status_q'length-1), + scout => sov(ex5_wrt_ib_status_offset to ex5_wrt_ib_status_offset + ex5_wrt_ib_status_q'length-1), + din => ex4_wrt_ib_status(0 to 15), + dout => ex5_wrt_ib_status_q(0 to 15) ); + +ex5_wrt_ib_status_gated(0 to 15) <= gate_and(not my_ex5_stg_flush, ex5_wrt_ib_status_q(0 to 15)); + +latch_ex6_wrt_ib_status : tri_rlmreg_p + generic map (width => ex6_wrt_ib_status_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => mtdp_ex3_to_7_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex6_wrt_ib_status_offset to ex6_wrt_ib_status_offset + ex6_wrt_ib_status_q'length-1), + scout => sov(ex6_wrt_ib_status_offset to ex6_wrt_ib_status_offset + ex6_wrt_ib_status_q'length-1), + din => ex5_wrt_ib_status_gated(0 to 15), + dout => ex6_wrt_ib_status_q(0 to 15) ); + +ex5_ib0_buf0_flushed <= ex5_wrt_ib_status_q(0) and my_ex5_stg_flush; +ex5_ib0_buf1_flushed <= ex5_wrt_ib_status_q(1) and my_ex5_stg_flush; +ex5_ib0_buf2_flushed <= ex5_wrt_ib_status_q(2) and my_ex5_stg_flush; +ex5_ib0_buf3_flushed <= ex5_wrt_ib_status_q(3) and my_ex5_stg_flush; +ex5_ib1_buf0_flushed <= ex5_wrt_ib_status_q(4) and my_ex5_stg_flush; +ex5_ib1_buf1_flushed <= ex5_wrt_ib_status_q(5) and my_ex5_stg_flush; +ex5_ib1_buf2_flushed <= ex5_wrt_ib_status_q(6) and my_ex5_stg_flush; +ex5_ib1_buf3_flushed <= ex5_wrt_ib_status_q(7) and my_ex5_stg_flush; +ex5_ib2_buf0_flushed <= ex5_wrt_ib_status_q(8) and my_ex5_stg_flush; +ex5_ib2_buf1_flushed <= ex5_wrt_ib_status_q(9) and my_ex5_stg_flush; +ex5_ib2_buf2_flushed <= ex5_wrt_ib_status_q(10) and my_ex5_stg_flush; +ex5_ib2_buf3_flushed <= ex5_wrt_ib_status_q(11) and my_ex5_stg_flush; +ex5_ib3_buf0_flushed <= ex5_wrt_ib_status_q(12) and my_ex5_stg_flush; +ex5_ib3_buf1_flushed <= ex5_wrt_ib_status_q(13) and my_ex5_stg_flush; +ex5_ib3_buf2_flushed <= ex5_wrt_ib_status_q(14) and my_ex5_stg_flush; +ex5_ib3_buf3_flushed <= ex5_wrt_ib_status_q(15) and my_ex5_stg_flush; + +ex5_ib0_flushed <= ex5_ib0_buf0_flushed or ex5_ib0_buf1_flushed or ex5_ib0_buf2_flushed or ex5_ib0_buf3_flushed; +ex5_ib1_flushed <= ex5_ib1_buf0_flushed or ex5_ib1_buf1_flushed or ex5_ib1_buf2_flushed or ex5_ib1_buf3_flushed; +ex5_ib2_flushed <= ex5_ib2_buf0_flushed or ex5_ib2_buf1_flushed or ex5_ib2_buf2_flushed or ex5_ib2_buf3_flushed; +ex5_ib3_flushed <= ex5_ib3_buf0_flushed or ex5_ib3_buf1_flushed or ex5_ib3_buf2_flushed or ex5_ib3_buf3_flushed; + +ex6_ib0_buf0_flushed <= ex6_wrt_ib_status_q(0) and my_ex6_stg_flush; +ex6_ib0_buf1_flushed <= ex6_wrt_ib_status_q(1) and my_ex6_stg_flush; +ex6_ib0_buf2_flushed <= ex6_wrt_ib_status_q(2) and my_ex6_stg_flush; +ex6_ib0_buf3_flushed <= ex6_wrt_ib_status_q(3) and my_ex6_stg_flush; +ex6_ib1_buf0_flushed <= ex6_wrt_ib_status_q(4) and my_ex6_stg_flush; +ex6_ib1_buf1_flushed <= ex6_wrt_ib_status_q(5) and my_ex6_stg_flush; +ex6_ib1_buf2_flushed <= ex6_wrt_ib_status_q(6) and my_ex6_stg_flush; +ex6_ib1_buf3_flushed <= ex6_wrt_ib_status_q(7) and my_ex6_stg_flush; +ex6_ib2_buf0_flushed <= ex6_wrt_ib_status_q(8) and my_ex6_stg_flush; +ex6_ib2_buf1_flushed <= ex6_wrt_ib_status_q(9) and my_ex6_stg_flush; +ex6_ib2_buf2_flushed <= ex6_wrt_ib_status_q(10) and my_ex6_stg_flush; +ex6_ib2_buf3_flushed <= ex6_wrt_ib_status_q(11) and my_ex6_stg_flush; +ex6_ib3_buf0_flushed <= ex6_wrt_ib_status_q(12) and my_ex6_stg_flush; +ex6_ib3_buf1_flushed <= ex6_wrt_ib_status_q(13) and my_ex6_stg_flush; +ex6_ib3_buf2_flushed <= ex6_wrt_ib_status_q(14) and my_ex6_stg_flush; +ex6_ib3_buf3_flushed <= ex6_wrt_ib_status_q(15) and my_ex6_stg_flush; + +ex6_ib0_flushed <= ex6_ib0_buf0_flushed or ex6_ib0_buf1_flushed or ex6_ib0_buf2_flushed or ex6_ib0_buf3_flushed; +ex6_ib1_flushed <= ex6_ib1_buf0_flushed or ex6_ib1_buf1_flushed or ex6_ib1_buf2_flushed or ex6_ib1_buf3_flushed; +ex6_ib2_flushed <= ex6_ib2_buf0_flushed or ex6_ib2_buf1_flushed or ex6_ib2_buf2_flushed or ex6_ib2_buf3_flushed; +ex6_ib3_flushed <= ex6_ib3_buf0_flushed or ex6_ib3_buf1_flushed or ex6_ib3_buf2_flushed or ex6_ib3_buf3_flushed; + + +ib_t0_pop_d <= (ex6_wrt_ib_status_q(0) or ex6_wrt_ib_status_q(1) or ex6_wrt_ib_status_q(2) or ex6_wrt_ib_status_q(3)) and + not my_ex6_stg_flush; + +ib_t1_pop_d <= (ex6_wrt_ib_status_q(4) or ex6_wrt_ib_status_q(5) or ex6_wrt_ib_status_q(6) or ex6_wrt_ib_status_q(7)) and + not my_ex6_stg_flush; + +ib_t2_pop_d <= (ex6_wrt_ib_status_q(8) or ex6_wrt_ib_status_q(9) or ex6_wrt_ib_status_q(10) or ex6_wrt_ib_status_q(11)) and + not my_ex6_stg_flush; + +ib_t3_pop_d <= (ex6_wrt_ib_status_q(12) or ex6_wrt_ib_status_q(13) or ex6_wrt_ib_status_q(14) or ex6_wrt_ib_status_q(15)) and + not my_ex6_stg_flush; + +latch_ipc_ib_t0_pop : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => mtdp_ex3_to_7_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ipc_ib_t0_pop_offset to ipc_ib_t0_pop_offset), + scout => sov(ipc_ib_t0_pop_offset to ipc_ib_t0_pop_offset), + din(0) => ib_t0_pop_d, + dout(0) => ac_an_reld_ditc_pop(0) ); + +latch_ipc_ib_t1_pop : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => mtdp_ex3_to_7_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ipc_ib_t1_pop_offset to ipc_ib_t1_pop_offset), + scout => sov(ipc_ib_t1_pop_offset to ipc_ib_t1_pop_offset), + din(0) => ib_t1_pop_d, + dout(0) => ac_an_reld_ditc_pop(1) ); + +latch_ipc_ib_t2_pop : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => mtdp_ex3_to_7_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ipc_ib_t2_pop_offset to ipc_ib_t2_pop_offset), + scout => sov(ipc_ib_t2_pop_offset to ipc_ib_t2_pop_offset), + din(0) => ib_t2_pop_d, + dout(0) => ac_an_reld_ditc_pop(2) ); + +latch_ipc_ib_t3_pop : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => mtdp_ex3_to_7_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ipc_ib_t3_pop_offset to ipc_ib_t3_pop_offset), + scout => sov(ipc_ib_t3_pop_offset to ipc_ib_t3_pop_offset), + din(0) => ib_t3_pop_d, + dout(0) => ac_an_reld_ditc_pop(3) ); + + + + +ib0_buf0_val_d <= '0' when wrt_ib0_buf0_status='1' else + ex5_ib_val_save_q when ex5_ib0_buf0_flushed='1' else + ex6_ib_val_save_q when ex6_ib0_buf0_flushed='1' else + '1' when ib0_buf0_set_val='1' else + '0' when ib0_buf0_reset_val='1' else + ib0_buf0_val_q; + +ib0_buf1_val_d <= '0' when wrt_ib0_buf1_status='1' else + ex5_ib_val_save_q when ex5_ib0_buf1_flushed='1' else + ex6_ib_val_save_q when ex6_ib0_buf1_flushed='1' else + '1' when ib0_buf1_set_val='1' else + '0' when ib0_buf1_reset_val='1' else + ib0_buf1_val_q; + +ib0_buf2_val_d <= '0' when wrt_ib0_buf2_status='1' else + ex5_ib_val_save_q when ex5_ib0_buf2_flushed='1' else + ex6_ib_val_save_q when ex6_ib0_buf2_flushed='1' else + '1' when ib0_buf2_set_val='1' else + '0' when ib0_buf2_reset_val='1' else + ib0_buf2_val_q; + +ib0_buf3_val_d <= '0' when wrt_ib0_buf3_status='1' else + ex5_ib_val_save_q when ex5_ib0_buf3_flushed='1' else + ex6_ib_val_save_q when ex6_ib0_buf3_flushed='1' else + '1' when ib0_buf3_set_val='1' else + '0' when ib0_buf3_reset_val='1' else + ib0_buf3_val_q; + +ib1_buf0_val_d <= '0' when wrt_ib1_buf0_status='1' else + ex5_ib_val_save_q when ex5_ib1_buf0_flushed='1' else + ex6_ib_val_save_q when ex6_ib1_buf0_flushed='1' else + '1' when ib1_buf0_set_val='1' else + '0' when ib1_buf0_reset_val='1' else + ib1_buf0_val_q; + +ib1_buf1_val_d <= '0' when wrt_ib1_buf1_status='1' else + ex5_ib_val_save_q when ex5_ib1_buf1_flushed='1' else + ex6_ib_val_save_q when ex6_ib1_buf1_flushed='1' else + '1' when ib1_buf1_set_val='1' else + '0' when ib1_buf1_reset_val='1' else + ib1_buf1_val_q; + +ib1_buf2_val_d <= '0' when wrt_ib1_buf2_status='1' else + ex5_ib_val_save_q when ex5_ib1_buf2_flushed='1' else + ex6_ib_val_save_q when ex6_ib1_buf2_flushed='1' else + '1' when ib1_buf2_set_val='1' else + '0' when ib1_buf2_reset_val='1' else + ib1_buf2_val_q; + +ib1_buf3_val_d <= '0' when wrt_ib1_buf3_status='1' else + ex5_ib_val_save_q when ex5_ib1_buf3_flushed='1' else + ex6_ib_val_save_q when ex6_ib1_buf3_flushed='1' else + '1' when ib1_buf3_set_val='1' else + '0' when ib1_buf3_reset_val='1' else + ib1_buf3_val_q; + +ib2_buf0_val_d <= '0' when wrt_ib2_buf0_status='1' else + ex5_ib_val_save_q when ex5_ib2_buf0_flushed='1' else + ex6_ib_val_save_q when ex6_ib2_buf0_flushed='1' else + '1' when ib2_buf0_set_val='1' else + '0' when ib2_buf0_reset_val='1' else + ib2_buf0_val_q; + +ib2_buf1_val_d <= '0' when wrt_ib2_buf1_status='1' else + ex5_ib_val_save_q when ex5_ib2_buf1_flushed='1' else + ex6_ib_val_save_q when ex6_ib2_buf1_flushed='1' else + '1' when ib2_buf1_set_val='1' else + '0' when ib2_buf1_reset_val='1' else + ib2_buf1_val_q; + +ib2_buf2_val_d <= '0' when wrt_ib2_buf2_status='1' else + ex5_ib_val_save_q when ex5_ib2_buf2_flushed='1' else + ex6_ib_val_save_q when ex6_ib2_buf2_flushed='1' else + '1' when ib2_buf2_set_val='1' else + '0' when ib2_buf2_reset_val='1' else + ib2_buf2_val_q; + +ib2_buf3_val_d <= '0' when wrt_ib2_buf3_status='1' else + ex5_ib_val_save_q when ex5_ib2_buf3_flushed='1' else + ex6_ib_val_save_q when ex6_ib2_buf3_flushed='1' else + '1' when ib2_buf3_set_val='1' else + '0' when ib2_buf3_reset_val='1' else + ib2_buf3_val_q; + +ib3_buf0_val_d <= '0' when wrt_ib3_buf0_status='1' else + ex5_ib_val_save_q when ex5_ib3_buf0_flushed='1' else + ex6_ib_val_save_q when ex6_ib3_buf0_flushed='1' else + '1' when ib3_buf0_set_val='1' else + '0' when ib3_buf0_reset_val='1' else + ib3_buf0_val_q; + +ib3_buf1_val_d <= '0' when wrt_ib3_buf1_status='1' else + ex5_ib_val_save_q when ex5_ib3_buf1_flushed='1' else + ex6_ib_val_save_q when ex6_ib3_buf1_flushed='1' else + '1' when ib3_buf1_set_val='1' else + '0' when ib3_buf1_reset_val='1' else + ib3_buf1_val_q; + +ib3_buf2_val_d <= '0' when wrt_ib3_buf2_status='1' else + ex5_ib_val_save_q when ex5_ib3_buf2_flushed='1' else + ex6_ib_val_save_q when ex6_ib3_buf2_flushed='1' else + '1' when ib3_buf2_set_val='1' else + '0' when ib3_buf2_reset_val='1' else + ib3_buf2_val_q; + +ib3_buf3_val_d <= '0' when wrt_ib3_buf3_status='1' else + ex5_ib_val_save_q when ex5_ib3_buf3_flushed='1' else + ex6_ib_val_save_q when ex6_ib3_buf3_flushed='1' else + '1' when ib3_buf3_set_val='1' else + '0' when ib3_buf3_reset_val='1' else + ib3_buf3_val_q; + +ex4_ib_val_save <= gate_and(wrt_ib0_buf0_status, ib0_buf0_val_q) or + gate_and(wrt_ib0_buf1_status, ib0_buf1_val_q) or + gate_and(wrt_ib0_buf2_status, ib0_buf2_val_q) or + gate_and(wrt_ib0_buf3_status, ib0_buf3_val_q) or + gate_and(wrt_ib1_buf0_status, ib1_buf0_val_q) or + gate_and(wrt_ib1_buf1_status, ib1_buf1_val_q) or + gate_and(wrt_ib1_buf2_status, ib1_buf2_val_q) or + gate_and(wrt_ib1_buf3_status, ib1_buf3_val_q) or + gate_and(wrt_ib2_buf0_status, ib2_buf0_val_q) or + gate_and(wrt_ib2_buf1_status, ib2_buf1_val_q) or + gate_and(wrt_ib2_buf2_status, ib2_buf2_val_q) or + gate_and(wrt_ib2_buf3_status, ib2_buf3_val_q) or + gate_and(wrt_ib3_buf0_status, ib3_buf0_val_q) or + gate_and(wrt_ib3_buf1_status, ib3_buf1_val_q) or + gate_and(wrt_ib3_buf2_status, ib3_buf2_val_q) or + gate_and(wrt_ib3_buf3_status, ib3_buf3_val_q); + + +ib_buf_val_act <= reld_data_val or mtdp_ex3_to_7_val; + +latch_ib0_buf0_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ib_buf_val_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib0_buf0_val_offset to ib0_buf0_val_offset), + scout => sov(ib0_buf0_val_offset to ib0_buf0_val_offset), + din(0) => ib0_buf0_val_d, + dout(0) => ib0_buf0_val_q ); + + +latch_ib0_buf1_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ib_buf_val_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib0_buf1_val_offset to ib0_buf1_val_offset), + scout => sov(ib0_buf1_val_offset to ib0_buf1_val_offset), + din(0) => ib0_buf1_val_d, + dout(0) => ib0_buf1_val_q ); + +latch_ib0_buf2_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ib_buf_val_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib0_buf2_val_offset to ib0_buf2_val_offset), + scout => sov(ib0_buf2_val_offset to ib0_buf2_val_offset), + din(0) => ib0_buf2_val_d, + dout(0) => ib0_buf2_val_q ); + +latch_ib0_buf3_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ib_buf_val_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib0_buf3_val_offset to ib0_buf3_val_offset), + scout => sov(ib0_buf3_val_offset to ib0_buf3_val_offset), + din(0) => ib0_buf3_val_d, + dout(0) => ib0_buf3_val_q ); + +latch_ib1_buf0_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ib_buf_val_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib1_buf0_val_offset to ib1_buf0_val_offset), + scout => sov(ib1_buf0_val_offset to ib1_buf0_val_offset), + din(0) => ib1_buf0_val_d, + dout(0) => ib1_buf0_val_q ); + + +latch_ib1_buf1_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ib_buf_val_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib1_buf1_val_offset to ib1_buf1_val_offset), + scout => sov(ib1_buf1_val_offset to ib1_buf1_val_offset), + din(0) => ib1_buf1_val_d, + dout(0) => ib1_buf1_val_q ); + +latch_ib1_buf2_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ib_buf_val_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib1_buf2_val_offset to ib1_buf2_val_offset), + scout => sov(ib1_buf2_val_offset to ib1_buf2_val_offset), + din(0) => ib1_buf2_val_d, + dout(0) => ib1_buf2_val_q ); + +latch_ib1_buf3_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ib_buf_val_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib1_buf3_val_offset to ib1_buf3_val_offset), + scout => sov(ib1_buf3_val_offset to ib1_buf3_val_offset), + din(0) => ib1_buf3_val_d, + dout(0) => ib1_buf3_val_q ); + +latch_ib2_buf0_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ib_buf_val_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib2_buf0_val_offset to ib2_buf0_val_offset), + scout => sov(ib2_buf0_val_offset to ib2_buf0_val_offset), + din(0) => ib2_buf0_val_d, + dout(0) => ib2_buf0_val_q ); + + +latch_ib2_buf1_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ib_buf_val_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib2_buf1_val_offset to ib2_buf1_val_offset), + scout => sov(ib2_buf1_val_offset to ib2_buf1_val_offset), + din(0) => ib2_buf1_val_d, + dout(0) => ib2_buf1_val_q ); + +latch_ib2_buf2_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ib_buf_val_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib2_buf2_val_offset to ib2_buf2_val_offset), + scout => sov(ib2_buf2_val_offset to ib2_buf2_val_offset), + din(0) => ib2_buf2_val_d, + dout(0) => ib2_buf2_val_q ); + +latch_ib2_buf3_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ib_buf_val_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib2_buf3_val_offset to ib2_buf3_val_offset), + scout => sov(ib2_buf3_val_offset to ib2_buf3_val_offset), + din(0) => ib2_buf3_val_d, + dout(0) => ib2_buf3_val_q ); + +latch_ib3_buf0_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ib_buf_val_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib3_buf0_val_offset to ib3_buf0_val_offset), + scout => sov(ib3_buf0_val_offset to ib3_buf0_val_offset), + din(0) => ib3_buf0_val_d, + dout(0) => ib3_buf0_val_q ); + + +latch_ib3_buf1_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ib_buf_val_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib3_buf1_val_offset to ib3_buf1_val_offset), + scout => sov(ib3_buf1_val_offset to ib3_buf1_val_offset), + din(0) => ib3_buf1_val_d, + dout(0) => ib3_buf1_val_q ); + +latch_ib3_buf2_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ib_buf_val_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib3_buf2_val_offset to ib3_buf2_val_offset), + scout => sov(ib3_buf2_val_offset to ib3_buf2_val_offset), + din(0) => ib3_buf2_val_d, + dout(0) => ib3_buf2_val_q ); + +latch_ib3_buf3_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ib_buf_val_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib3_buf3_val_offset to ib3_buf3_val_offset), + scout => sov(ib3_buf3_val_offset to ib3_buf3_val_offset), + din(0) => ib3_buf3_val_d, + dout(0) => ib3_buf3_val_q ); + +latch_ex5_ib_val_save : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => mtdp_ex3_to_7_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex5_ib_val_save_offset to ex5_ib_val_save_offset), + scout => sov(ex5_ib_val_save_offset to ex5_ib_val_save_offset), + din(0) => ex4_ib_val_save, + dout(0) => ex5_ib_val_save_q ); + +latch_ex6_ib_val_save : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => mtdp_ex3_to_7_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex6_ib_val_save_offset to ex6_ib_val_save_offset), + scout => sov(ex6_ib_val_save_offset to ex6_ib_val_save_offset), + din(0) => ex5_ib_val_save_q, + dout(0) => ex6_ib_val_save_q ); + + +ib_empty_d(0) <= not (ib0_buf0_val_q or ib0_buf1_val_q or ib0_buf2_val_q or ib0_buf3_val_q); +ib_empty_d(1) <= not (ib1_buf0_val_q or ib1_buf1_val_q or ib1_buf2_val_q or ib1_buf3_val_q); +ib_empty_d(2) <= not (ib2_buf0_val_q or ib2_buf1_val_q or ib2_buf2_val_q or ib2_buf3_val_q); +ib_empty_d(3) <= not (ib3_buf0_val_q or ib3_buf1_val_q or ib3_buf2_val_q or ib3_buf3_val_q); + +quiesce_d(0) <= ib_empty_d(0) and not (ob0_buf0_status_q(0) or ob0_buf1_status_q(0) or ob0_buf2_status_q(0) or ob0_buf3_status_q(0)); +quiesce_d(1) <= ib_empty_d(1) and not (ob1_buf0_status_q(0) or ob1_buf1_status_q(0) or ob1_buf2_status_q(0) or ob1_buf3_status_q(0)); +quiesce_d(2) <= ib_empty_d(2) and not (ob2_buf0_status_q(0) or ob2_buf1_status_q(0) or ob2_buf2_status_q(0) or ob2_buf3_status_q(0)); +quiesce_d(3) <= ib_empty_d(3) and not (ob3_buf0_status_q(0) or ob3_buf1_status_q(0) or ob3_buf2_status_q(0) or ob3_buf3_status_q(0)); + +latch_ib_empty : tri_rlmreg_p + generic map (width => ib_empty_d'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib_empty_offset to ib_empty_offset + ib_empty_d'length-1), + scout => sov(ib_empty_offset to ib_empty_offset + ib_empty_d'length-1), + din => ib_empty_d(0 to 3), + dout => bx_ib_empty(0 to 3) ); + +latch_quiesce : tri_rlmreg_p + generic map (width => quiesce_d'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(quiesce_offset to quiesce_offset + quiesce_d'length-1), + scout => sov(quiesce_offset to quiesce_offset + quiesce_d'length-1), + din => quiesce_d(0 to 3), + dout => bx_xu_quiesce(0 to 3) ); + + + + +ib0_decr_ptr <= (ex4_ib0_flushed & ex5_ib0_flushed & ex6_ib0_flushed = "100") or + (ex4_ib0_flushed & ex5_ib0_flushed & ex6_ib0_flushed = "010") or + (ex4_ib0_flushed & ex5_ib0_flushed & ex6_ib0_flushed = "001"); + +ib0_decr_ptr_by2 <= (ex4_ib0_flushed & ex5_ib0_flushed & ex6_ib0_flushed = "110") or + (ex4_ib0_flushed & ex5_ib0_flushed & ex6_ib0_flushed = "101") or + (ex4_ib0_flushed & ex5_ib0_flushed & ex6_ib0_flushed = "011"); + +ib0_decr_ptr_by3 <= ex4_ib0_flushed & ex5_ib0_flushed & ex6_ib0_flushed = "111"; + +ib0_rd_entry_ptr_d <= std_ulogic_vector(unsigned(ib0_rd_entry_ptr_q) + 1) when ib0_incr_ptr='1' else + std_ulogic_vector(unsigned(ib0_rd_entry_ptr_q) - 1) when ib0_decr_ptr='1' else + std_ulogic_vector(unsigned(ib0_rd_entry_ptr_q) - 2) when ib0_decr_ptr_by2='1' else + std_ulogic_vector(unsigned(ib0_rd_entry_ptr_q) - 3) when ib0_decr_ptr_by3='1' else + ib0_rd_entry_ptr_q(0 to 1); + +ib1_decr_ptr <= (ex4_ib1_flushed & ex5_ib1_flushed & ex6_ib1_flushed = "100") or + (ex4_ib1_flushed & ex5_ib1_flushed & ex6_ib1_flushed = "010") or + (ex4_ib1_flushed & ex5_ib1_flushed & ex6_ib1_flushed = "001"); + +ib1_decr_ptr_by2 <= (ex4_ib1_flushed & ex5_ib1_flushed & ex6_ib1_flushed = "110") or + (ex4_ib1_flushed & ex5_ib1_flushed & ex6_ib1_flushed = "101") or + (ex4_ib1_flushed & ex5_ib1_flushed & ex6_ib1_flushed = "011"); + +ib1_decr_ptr_by3 <= ex4_ib1_flushed & ex5_ib1_flushed & ex6_ib1_flushed = "111"; + +ib1_rd_entry_ptr_d <= std_ulogic_vector(unsigned(ib1_rd_entry_ptr_q) + 1) when ib1_incr_ptr='1' else + std_ulogic_vector(unsigned(ib1_rd_entry_ptr_q) - 1) when ib1_decr_ptr='1' else + std_ulogic_vector(unsigned(ib1_rd_entry_ptr_q) - 2) when ib1_decr_ptr_by2='1' else + std_ulogic_vector(unsigned(ib1_rd_entry_ptr_q) - 3) when ib1_decr_ptr_by3='1' else + ib1_rd_entry_ptr_q(0 to 1); + +ib2_decr_ptr <= (ex4_ib2_flushed & ex5_ib2_flushed & ex6_ib2_flushed = "100") or + (ex4_ib2_flushed & ex5_ib2_flushed & ex6_ib2_flushed = "010") or + (ex4_ib2_flushed & ex5_ib2_flushed & ex6_ib2_flushed = "001"); + +ib2_decr_ptr_by2 <= (ex4_ib2_flushed & ex5_ib2_flushed & ex6_ib2_flushed = "110") or + (ex4_ib2_flushed & ex5_ib2_flushed & ex6_ib2_flushed = "101") or + (ex4_ib2_flushed & ex5_ib2_flushed & ex6_ib2_flushed = "011"); + +ib2_decr_ptr_by3 <= ex4_ib2_flushed & ex5_ib2_flushed & ex6_ib2_flushed = "111"; + +ib2_rd_entry_ptr_d <= std_ulogic_vector(unsigned(ib2_rd_entry_ptr_q) + 1) when ib2_incr_ptr='1' else + std_ulogic_vector(unsigned(ib2_rd_entry_ptr_q) - 1) when ib2_decr_ptr='1' else + std_ulogic_vector(unsigned(ib2_rd_entry_ptr_q) - 2) when ib2_decr_ptr_by2='1' else + std_ulogic_vector(unsigned(ib2_rd_entry_ptr_q) - 3) when ib2_decr_ptr_by3='1' else + ib2_rd_entry_ptr_q(0 to 1); + +ib3_decr_ptr <= (ex4_ib3_flushed & ex5_ib3_flushed & ex6_ib3_flushed = "100") or + (ex4_ib3_flushed & ex5_ib3_flushed & ex6_ib3_flushed = "010") or + (ex4_ib3_flushed & ex5_ib3_flushed & ex6_ib3_flushed = "001"); + +ib3_decr_ptr_by2 <= (ex4_ib3_flushed & ex5_ib3_flushed & ex6_ib3_flushed = "110") or + (ex4_ib3_flushed & ex5_ib3_flushed & ex6_ib3_flushed = "101") or + (ex4_ib3_flushed & ex5_ib3_flushed & ex6_ib3_flushed = "011"); + +ib3_decr_ptr_by3 <= ex4_ib3_flushed & ex5_ib3_flushed & ex6_ib3_flushed = "111"; + +ib3_rd_entry_ptr_d <= std_ulogic_vector(unsigned(ib3_rd_entry_ptr_q) + 1) when ib3_incr_ptr='1' else + std_ulogic_vector(unsigned(ib3_rd_entry_ptr_q) - 1) when ib3_decr_ptr='1' else + std_ulogic_vector(unsigned(ib3_rd_entry_ptr_q) - 2) when ib3_decr_ptr_by2='1' else + std_ulogic_vector(unsigned(ib3_rd_entry_ptr_q) - 3) when ib3_decr_ptr_by3='1' else + ib3_rd_entry_ptr_q(0 to 1); + +latch_ib0_rd_entry_ptr : tri_rlmreg_p + generic map (width => ib0_rd_entry_ptr_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => mtdp_ex3_to_7_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib0_rd_entry_ptr_offset to ib0_rd_entry_ptr_offset + ib0_rd_entry_ptr_q'length-1), + scout => sov(ib0_rd_entry_ptr_offset to ib0_rd_entry_ptr_offset + ib0_rd_entry_ptr_q'length-1), + din => ib0_rd_entry_ptr_d(0 to 1), + dout => ib0_rd_entry_ptr_q(0 to 1) ); + +latch_ib1_rd_entry_ptr : tri_rlmreg_p + generic map (width => ib1_rd_entry_ptr_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => mtdp_ex3_to_7_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib1_rd_entry_ptr_offset to ib1_rd_entry_ptr_offset + ib1_rd_entry_ptr_q'length-1), + scout => sov(ib1_rd_entry_ptr_offset to ib1_rd_entry_ptr_offset + ib1_rd_entry_ptr_q'length-1), + din => ib1_rd_entry_ptr_d(0 to 1), + dout => ib1_rd_entry_ptr_q(0 to 1) ); + +latch_ib2_rd_entry_ptr : tri_rlmreg_p + generic map (width => ib2_rd_entry_ptr_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => mtdp_ex3_to_7_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib2_rd_entry_ptr_offset to ib2_rd_entry_ptr_offset + ib2_rd_entry_ptr_q'length-1), + scout => sov(ib2_rd_entry_ptr_offset to ib2_rd_entry_ptr_offset + ib2_rd_entry_ptr_q'length-1), + din => ib2_rd_entry_ptr_d(0 to 1), + dout => ib2_rd_entry_ptr_q(0 to 1) ); + +latch_ib3_rd_entry_ptr : tri_rlmreg_p + generic map (width => ib3_rd_entry_ptr_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => mtdp_ex3_to_7_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib3_rd_entry_ptr_offset to ib3_rd_entry_ptr_offset + ib3_rd_entry_ptr_q'length-1), + scout => sov(ib3_rd_entry_ptr_offset to ib3_rd_entry_ptr_offset + ib3_rd_entry_ptr_q'length-1), + din => ib3_rd_entry_ptr_d(0 to 1), + dout => ib3_rd_entry_ptr_q(0 to 1) ); + +latch_ib0_rd_entry_ptr_dly : tri_rlmreg_p + generic map (width => ib0_rd_entry_ptr_dly_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => mtdp_ex3_to_7_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib0_rd_entry_ptr_dly_offset to ib0_rd_entry_ptr_dly_offset + ib0_rd_entry_ptr_dly_q'length-1), + scout => sov(ib0_rd_entry_ptr_dly_offset to ib0_rd_entry_ptr_dly_offset + ib0_rd_entry_ptr_dly_q'length-1), + din => ib0_rd_entry_ptr_q(0 to 1), + dout => ib0_rd_entry_ptr_dly_q(0 to 1) ); + +latch_ib1_rd_entry_ptr_dly : tri_rlmreg_p + generic map (width => ib1_rd_entry_ptr_dly_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => mtdp_ex3_to_7_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib1_rd_entry_ptr_dly_offset to ib1_rd_entry_ptr_dly_offset + ib1_rd_entry_ptr_dly_q'length-1), + scout => sov(ib1_rd_entry_ptr_dly_offset to ib1_rd_entry_ptr_dly_offset + ib1_rd_entry_ptr_dly_q'length-1), + din => ib1_rd_entry_ptr_q(0 to 1), + dout => ib1_rd_entry_ptr_dly_q(0 to 1) ); + +latch_ib2_rd_entry_ptr_dly : tri_rlmreg_p + generic map (width => ib2_rd_entry_ptr_dly_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => mtdp_ex3_to_7_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib2_rd_entry_ptr_dly_offset to ib2_rd_entry_ptr_dly_offset + ib2_rd_entry_ptr_dly_q'length-1), + scout => sov(ib2_rd_entry_ptr_dly_offset to ib2_rd_entry_ptr_dly_offset + ib2_rd_entry_ptr_dly_q'length-1), + din => ib2_rd_entry_ptr_q(0 to 1), + dout => ib2_rd_entry_ptr_dly_q(0 to 1) ); + +latch_ib3_rd_entry_ptr_dly : tri_rlmreg_p + generic map (width => ib3_rd_entry_ptr_dly_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => mtdp_ex3_to_7_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib3_rd_entry_ptr_dly_offset to ib3_rd_entry_ptr_dly_offset + ib3_rd_entry_ptr_dly_q'length-1), + scout => sov(ib3_rd_entry_ptr_dly_offset to ib3_rd_entry_ptr_dly_offset + ib3_rd_entry_ptr_dly_q'length-1), + din => ib3_rd_entry_ptr_q(0 to 1), + dout => ib3_rd_entry_ptr_dly_q(0 to 1) ); + + + +with ex2_ipc_thrd_q(0 to 1) select + ib_rd_entry_ptr(0 to 1) <= ib0_rd_entry_ptr_d(0 to 1) when "00", + ib1_rd_entry_ptr_d(0 to 1) when "01", + ib2_rd_entry_ptr_d(0 to 1) when "10", + ib3_rd_entry_ptr_d(0 to 1) when others; + +ib_ary_rd_addr(0 to 5) <= ex2_ipc_thrd_q(0 to 1) & ib_rd_entry_ptr(0 to 1) & xu_bx_ex2_ipc_ba(1 to 2); + + + +latch_ib_err_inj : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib_err_inj_offset to ib_err_inj_offset), + scout => sov(ib_err_inj_offset to ib_err_inj_offset), + din(0) => pc_bx_inj_inbox_ecc, + dout(0) => ib_err_inj_q ); + +lat_reld_data_0 <= lat_reld_data(0) xor ib_err_inj_q; + + +ib_array: entity tri.tri_64x42_4w_1r1w(tri_64x42_4w_1r1w) + generic map ( expand_type => expand_type ) + port map( + wr_way => ib_ary_wen(0 to 3), + wr_adr => ib_ary_wrt_addr(0 to 5), + + di(0) => lat_reld_data_0, + di(1 to 31) => lat_reld_data(1 to 31), + di(32 to 38) => ib_datain_ecc0(0 to 6), + di(39 to 41) => "000", + + di(42 to 73) => lat_reld_data(32 to 63), + di(74 to 80) => ib_datain_ecc1(0 to 6), + di(81 to 83) => "000", + + di(84 to 115) => lat_reld_data(64 to 95), + di(116 to 122) => ib_datain_ecc2(0 to 6), + di(123 to 125) => "000", + + di(126 to 157) => lat_reld_data(96 to 127), + di(158 to 164) => ib_datain_ecc3(0 to 6), + di(165 to 167) => "000", + + rd0_adr => ib_ary_rd_addr(0 to 5), + + do0(0 to 31) => ib_rd_data(0 to 31), + do0(32 to 38) => ib_rd_data_ecc0(0 to 6), + do0(39 to 41) => unused(12 to 14), + + do0(42 to 73) => ib_rd_data(32 to 63), + do0(74 to 80) => ib_rd_data_ecc1(0 to 6), + do0(81 to 83) => unused(15 to 17), + + do0(84 to 115) => ib_rd_data(64 to 95), + do0(116 to 122) => ib_rd_data_ecc2(0 to 6), + do0(123 to 125) => unused(18 to 20), + + do0(126 to 157) => ib_rd_data(96 to 127), + do0(158 to 164) => ib_rd_data_ecc3(0 to 6), + do0(165 to 167) => unused(21 to 23), + + abist_di => abist_di_0, + abist_bw_odd => abist_g8t_bw_1, + abist_bw_even => abist_g8t_bw_0, + abist_wr_adr => abist_waddr_0(4 to 9), + wr_abst_act => abist_g8t_wenb, + abist_rd0_adr => abist_raddr_0(4 to 9), + rd0_abst_act => abist_g8t1p_renb_0, + tc_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc, + abist_ena_1 => pc_bx_abist_ena_dc, + abist_g8t_rd0_comp_ena => abist_wl64_comp_ena, + abist_raw_dc_b => pc_bx_abist_raw_dc_b, + obs0_abist_cmp => abist_g8t_dcomp, + + lcb_bolt_sl_thold_0 => bolt_sl_thold_0, + pc_bo_enable_2 => bolt_enable_2, + pc_bo_reset => pc_bx_bo_reset, + pc_bo_unload => pc_bx_bo_unload, + pc_bo_repair => pc_bx_bo_repair, + pc_bo_shdata => pc_bx_bo_shdata, + pc_bo_select => pc_bx_bo_select(2 to 3), + bo_pc_failout => bx_pc_bo_fail(2 to 3), + bo_pc_diagloop => bx_pc_bo_diagout(2 to 3), + tri_lcb_mpw1_dc_b => mpw1_dc_b, + tri_lcb_mpw2_dc_b => mpw2_dc_b, + tri_lcb_delay_lclkr_dc => delay_lclkr_dc, + tri_lcb_clkoff_dc_b => clkoff_dc_b, + tri_lcb_act_dis_dc => tidn, + + gnd => gnd, + vdd => vdd, + vcs => vcs, + nclk => nclk, + rd0_act => ex2_mfdp_val_q, + wr_act => reld_data_val, + sg_0 => sg_0, + abst_sl_thold_0 => abst_sl_thold_0, + ary_nsl_thold_0 => ary_slp_nsl_thold_0, + time_sl_thold_0 => time_sl_thold_0, + repr_sl_thold_0 => repr_sl_thold_0, + scan_dis_dc_b => an_ac_scan_dis_dc_b, + scan_diag_dc => an_ac_scan_diag_dc, + ccflush_dc => pc_bx_ccflush_dc, + + ary0_clkoff_dc_b => ary0_clkoff_dc_b, + ary0_d_mode_dc => ary0_d_mode_dc, + ary0_mpw1_dc_b => ary0_mpw1_dc_b_v, + ary0_mpw2_dc_b => ary0_mpw2_dc_b, + ary0_delay_lclkr_dc => ary0_delay_lclkr_dc_v, + + ary1_clkoff_dc_b => ary1_clkoff_dc_b, + ary1_d_mode_dc => ary1_d_mode_dc, + ary1_mpw1_dc_b => ary1_mpw1_dc_b_v, + ary1_mpw2_dc_b => ary1_mpw2_dc_b, + ary1_delay_lclkr_dc => ary1_delay_lclkr_dc_v, + + abst_scan_in => ob_abst_scan_out, + time_scan_in => ob_time_scan_out, + repr_scan_in => ob_repr_scan_out, + abst_scan_out => ib_abst_scan_out, + time_scan_out => ib_time_scan_out, + repr_scan_out => int_repr_scan_out +); + + + + + + + + +ib_do_eccgen0: entity work.xuq_eccgen(xuq_eccgen) + generic map ( regsize => 32 ) + port map(din(0 to 31) => ex4_inbox_data(0 to 31), + din(32 to 38) => ex4_ib_data_ecc0, + syn => ib_rd_data_nsyn0 ); + +ib_do_eccgen1: entity work.xuq_eccgen(xuq_eccgen) + generic map ( regsize => 32 ) + port map(din(0 to 31) => ex4_inbox_data(32 to 63), + din(32 to 38) => ex4_ib_data_ecc1, + syn => ib_rd_data_nsyn1 ); + +ib_do_eccgen2: entity work.xuq_eccgen(xuq_eccgen) + generic map ( regsize => 32 ) + port map(din(0 to 31) => ex4_inbox_data(64 to 95), + din(32 to 38) => ex4_ib_data_ecc2, + syn => ib_rd_data_nsyn2 ); + +ib_do_eccgen3: entity work.xuq_eccgen(xuq_eccgen) + generic map ( regsize => 32 ) + port map(din(0 to 31) => ex4_inbox_data(96 to 127), + din(32 to 38) => ex4_ib_data_ecc3, + syn => ib_rd_data_nsyn3 ); + + + + + + + +ib_di_eccchk0: entity work.xuq_eccchk(xuq_eccchk) + generic map ( regsize => 32 ) + port map(din => ex4_inbox_data(0 to 31), + EnCorr => '1', + NSyn => ib_rd_data_nsyn0, + Corrd => ib_rd_data_cor(0 to 31), + sbe => ib_ary_sbe(0), + ue => ib_ary_ue(0) ); + +ib_di_eccchk1: entity work.xuq_eccchk(xuq_eccchk) + generic map ( regsize => 32 ) + port map(din => ex4_inbox_data(32 to 63), + EnCorr => '1', + NSyn => ib_rd_data_nsyn1, + Corrd => ib_rd_data_cor(32 to 63), + sbe => ib_ary_sbe(1), + ue => ib_ary_ue(1) ); + +ib_di_eccchk2: entity work.xuq_eccchk(xuq_eccchk) + generic map ( regsize => 32 ) + port map(din => ex4_inbox_data(64 to 95), + EnCorr => '1', + NSyn => ib_rd_data_nsyn2, + Corrd => ib_rd_data_cor(64 to 95), + sbe => ib_ary_sbe(2), + ue => ib_ary_ue(2) ); + +ib_di_eccchk3: entity work.xuq_eccchk(xuq_eccchk) + generic map ( regsize => 32 ) + port map(din => ex4_inbox_data(96 to 127), + EnCorr => '1', + NSyn => ib_rd_data_nsyn3, + Corrd => ib_rd_data_cor(96 to 127), + sbe => ib_ary_sbe(3), + ue => ib_ary_ue(3) ); + +latch_ex5_inbox_data_cor : tri_rlmreg_p + generic map (width => ex5_inbox_data_cor'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ex4_mfdp_val_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex5_inbox_data_cor_offset to ex5_inbox_data_cor_offset + ex5_inbox_data_cor'length-1), + scout => sov(ex5_inbox_data_cor_offset to ex5_inbox_data_cor_offset + ex5_inbox_data_cor'length-1), + din => ib_rd_data_cor(0 to 127), + dout => ex5_inbox_data_cor(0 to 127) ); + +latch_ib_ary_sbe : tri_rlmreg_p + generic map (width => ib_ary_sbe_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ex4_mfdp_val_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib_ary_sbe_offset to ib_ary_sbe_offset + ib_ary_sbe_q'length-1), + scout => sov(ib_ary_sbe_offset to ib_ary_sbe_offset + ib_ary_sbe_q'length-1), + din => ib_ary_sbe(0 to 3), + dout => ib_ary_sbe_q(0 to 3) ); + +latch_ib_ary_ue : tri_rlmreg_p + generic map (width => ib_ary_ue_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ex4_mfdp_val_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib_ary_ue_offset to ib_ary_ue_offset + ib_ary_ue_q'length-1), + scout => sov(ib_ary_ue_offset to ib_ary_ue_offset + ib_ary_ue_q'length-1), + din => ib_ary_ue(0 to 3), + dout => ib_ary_ue_q(0 to 3) ); + +ib_ary_sbe_or <= (ib_ary_sbe_q(0) or ib_ary_sbe_q(1) or ib_ary_sbe_q(2) or ib_ary_sbe_q(3)) and ex5_ib_ecc_val; + +ib_ary_ue_or <= (ib_ary_ue_q(0) or ib_ary_ue_q(1) or ib_ary_ue_q(2) or ib_ary_ue_q(3)) and ex5_ib_ecc_val; + + + + + +latch_inbox_ecc_err : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dp_op_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(inbox_ecc_err_offset to inbox_ecc_err_offset), + scout => sov(inbox_ecc_err_offset to inbox_ecc_err_offset), + din(0) => ib_ary_sbe_or, + dout(0) => inbox_ecc_err_q ); + +latch_inbox_ue : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dp_op_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(inbox_ue_offset to inbox_ue_offset), + scout => sov(inbox_ue_offset to inbox_ue_offset), + din(0) => ib_ary_ue_or, + dout(0) => inbox_ue_q ); + + inbox_err_rpt : entity tri.tri_direct_err_rpt + generic map + ( width => 2 + , expand_type => expand_type + ) + port map + ( vd => vdd + , gd => gnd + , err_in(0) => inbox_ecc_err_q + , err_in(1) => inbox_ue_q + , err_out(0) => bx_pc_err_inbox_ecc + , err_out(1) => bx_pc_err_inbox_ue + ); + + +with ib0_rd_entry_ptr_q(0 to 1) select + ib0_rd_val_reg <= (ib0_buf0_val_q and not ib0_buf0_reset_val) when "00", + (ib0_buf1_val_q and not ib0_buf1_reset_val) when "01", + (ib0_buf2_val_q and not ib0_buf2_reset_val) when "10", + (ib0_buf3_val_q and not ib0_buf3_reset_val) when others; + +with ib1_rd_entry_ptr_q(0 to 1) select + ib1_rd_val_reg <= (ib1_buf0_val_q and not ib1_buf0_reset_val) when "00", + (ib1_buf1_val_q and not ib1_buf1_reset_val) when "01", + (ib1_buf2_val_q and not ib1_buf2_reset_val) when "10", + (ib1_buf3_val_q and not ib1_buf3_reset_val) when others; + +with ib2_rd_entry_ptr_q(0 to 1) select + ib2_rd_val_reg <= (ib2_buf0_val_q and not ib2_buf0_reset_val) when "00", + (ib2_buf1_val_q and not ib2_buf1_reset_val) when "01", + (ib2_buf2_val_q and not ib2_buf2_reset_val) when "10", + (ib2_buf3_val_q and not ib2_buf3_reset_val) when others; + +with ib3_rd_entry_ptr_q(0 to 1) select + ib3_rd_val_reg <= (ib3_buf0_val_q and not ib3_buf0_reset_val) when "00", + (ib3_buf1_val_q and not ib3_buf1_reset_val) when "01", + (ib3_buf2_val_q and not ib3_buf2_reset_val) when "10", + (ib3_buf3_val_q and not ib3_buf3_reset_val) when others; + + + + +latch_ex4_ipc_thrd : tri_rlmreg_p + generic map (width => ex4_ipc_thrd_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dp_op_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_ipc_thrd_offset to ex4_ipc_thrd_offset + ex4_ipc_thrd_q'length-1), + scout => sov(ex4_ipc_thrd_offset to ex4_ipc_thrd_offset + ex4_ipc_thrd_q'length-1), + din => ex3_ipc_thrd_q(0 to 1), + dout => ex4_ipc_thrd_q(0 to 1) ); + +latch_ex5_ipc_thrd : tri_rlmreg_p + generic map (width => ex5_ipc_thrd_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dp_op_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex5_ipc_thrd_offset to ex5_ipc_thrd_offset + ex5_ipc_thrd_q'length-1), + scout => sov(ex5_ipc_thrd_offset to ex5_ipc_thrd_offset + ex5_ipc_thrd_q'length-1), + din => ex4_ipc_thrd_q(0 to 1), + dout => ex5_ipc_thrd_q(0 to 1) ); + +latch_ex6_ipc_thrd : tri_rlmreg_p + generic map (width => ex6_ipc_thrd_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dp_op_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex6_ipc_thrd_offset to ex6_ipc_thrd_offset + ex6_ipc_thrd_q'length-1), + scout => sov(ex6_ipc_thrd_offset to ex6_ipc_thrd_offset + ex6_ipc_thrd_q'length-1), + din => ex5_ipc_thrd_q(0 to 1), + dout => ex6_ipc_thrd_q(0 to 1) ); + +latch_ex4_ipc_ba : tri_rlmreg_p + generic map (width => ex4_ipc_ba_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dp_op_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_ipc_ba_offset to ex4_ipc_ba_offset + ex4_ipc_ba_q'length-1), + scout => sov(ex4_ipc_ba_offset to ex4_ipc_ba_offset + ex4_ipc_ba_q'length-1), + din => ex3_ipc_ba_q(0 to 4), + dout => ex4_ipc_ba_q(0 to 4) ); + +latch_ex4_ipc_sz : tri_rlmreg_p + generic map (width => ex4_ipc_sz_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dp_op_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_ipc_sz_offset to ex4_ipc_sz_offset + ex4_ipc_sz_q'length-1), + scout => sov(ex4_ipc_sz_offset to ex4_ipc_sz_offset + ex4_ipc_sz_q'length-1), + din => ex3_ipc_sz_q(0 to 1), + dout => ex4_ipc_sz_q(0 to 1) ); + + +with ex4_ipc_thrd_q(0 to 1) select + ex4_ib_rd_status_reg <= ib0_rd_val_reg when "00", + ib1_rd_val_reg when "01", + ib2_rd_val_reg when "10", + ib3_rd_val_reg when others; + + +ex3_data_w0_sel(0) <= (ex3_ipc_sz_q="00" and ex3_ipc_ba_q(3 to 4)="00" and ex3_ipc_ba_q(0)='0') or ex3_ipc_sz_q="10" or + (ex3_ipc_sz_q="01" and ex3_ipc_ba_q(3)='0'); +ex3_data_w0_sel(1) <= ex3_ipc_sz_q="00" and ex3_ipc_ba_q(3 to 4)="01"; +ex3_data_w0_sel(2) <= (ex3_ipc_sz_q="00" and ex3_ipc_ba_q(3 to 4)="10") or + (ex3_ipc_sz_q="01" and ex3_ipc_ba_q(3)='1'); +ex3_data_w0_sel(3) <= ex3_ipc_sz_q="00" and ex3_ipc_ba_q(3 to 4)="11"; +ex3_data_sel_status <= ex3_ipc_ba_q = "10000"; + +ex3_inbox_data(0 to 31) <= gate_and(ex3_data_w0_sel(0), ib_rd_data(0 to 31)) or + gate_and(ex3_data_w0_sel(1), ib_rd_data(32 to 63)) or + gate_and(ex3_data_w0_sel(2), ib_rd_data(64 to 95)) or + gate_and(ex3_data_w0_sel(3), ib_rd_data(96 to 127)) or + gate_and(ex3_data_sel_status, x"0000000" & "000" & ex4_ib_rd_status_reg); + +ex3_ib_data_ecc0(0 to 6)<= gate_and(ex3_data_w0_sel(0), ib_rd_data_ecc0(0 to 6)) or + gate_and(ex3_data_w0_sel(1), ib_rd_data_ecc1(0 to 6)) or + gate_and(ex3_data_w0_sel(2), ib_rd_data_ecc2(0 to 6)) or + gate_and(ex3_data_w0_sel(3), ib_rd_data_ecc3(0 to 6)); + +ex3_data_w1_sel(0) <= ex3_ipc_sz_q="00" and ex3_ipc_ba_q(3 to 4)="00" and ex3_ipc_ba_q(0)='0'; +ex3_data_w1_sel(1) <= (ex3_ipc_sz_q="00" and ex3_ipc_ba_q(3 to 4)="01") or ex3_ipc_sz_q="10" or + (ex3_ipc_sz_q="01" and ex3_ipc_ba_q(3)='0'); +ex3_data_w1_sel(2) <= ex3_ipc_sz_q="00" and ex3_ipc_ba_q(3 to 4)="10"; +ex3_data_w1_sel(3) <= (ex3_ipc_sz_q="00" and ex3_ipc_ba_q(3 to 4)="11") or + (ex3_ipc_sz_q="01" and ex3_ipc_ba_q(3)='1'); + +ex3_inbox_data(32 to 63) <= gate_and(ex3_data_w1_sel(0), ib_rd_data(0 to 31)) or + gate_and(ex3_data_w1_sel(1), ib_rd_data(32 to 63)) or + gate_and(ex3_data_w1_sel(2), ib_rd_data(64 to 95)) or + gate_and(ex3_data_w1_sel(3), ib_rd_data(96 to 127)) or + gate_and(ex3_data_sel_status, x"0000000" & "000" & ex4_ib_rd_status_reg); + +ex3_ib_data_ecc1(0 to 6)<= gate_and(ex3_data_w1_sel(0), ib_rd_data_ecc0(0 to 6)) or + gate_and(ex3_data_w1_sel(1), ib_rd_data_ecc1(0 to 6)) or + gate_and(ex3_data_w1_sel(2), ib_rd_data_ecc2(0 to 6)) or + gate_and(ex3_data_w1_sel(3), ib_rd_data_ecc3(0 to 6)); + +ex3_data_w2_sel(0) <= (ex3_ipc_sz_q="00" and ex3_ipc_ba_q(3 to 4)="00" and ex3_ipc_ba_q(0)='0') or + (ex3_ipc_sz_q="01" and ex3_ipc_ba_q(3)='0'); +ex3_data_w2_sel(1) <= ex3_ipc_sz_q="00" and ex3_ipc_ba_q(3 to 4)="01"; +ex3_data_w2_sel(2) <= (ex3_ipc_sz_q="00" and ex3_ipc_ba_q(3 to 4)="10") or ex3_ipc_sz_q="10" or + (ex3_ipc_sz_q="01" and ex3_ipc_ba_q(3)='1'); +ex3_data_w2_sel(3) <= ex3_ipc_sz_q="00" and ex3_ipc_ba_q(3 to 4)="11"; + +ex3_inbox_data(64 to 95) <= gate_and(ex3_data_w2_sel(0), ib_rd_data(0 to 31)) or + gate_and(ex3_data_w2_sel(1), ib_rd_data(32 to 63)) or + gate_and(ex3_data_w2_sel(2), ib_rd_data(64 to 95)) or + gate_and(ex3_data_w2_sel(3), ib_rd_data(96 to 127)) or + gate_and(ex3_data_sel_status, x"0000000" & "000" & ex4_ib_rd_status_reg); + +ex3_ib_data_ecc2(0 to 6)<= gate_and(ex3_data_w2_sel(0), ib_rd_data_ecc0(0 to 6)) or + gate_and(ex3_data_w2_sel(1), ib_rd_data_ecc1(0 to 6)) or + gate_and(ex3_data_w2_sel(2), ib_rd_data_ecc2(0 to 6)) or + gate_and(ex3_data_w2_sel(3), ib_rd_data_ecc3(0 to 6)); + +ex3_data_w3_sel(0) <= ex3_ipc_sz_q="00" and ex3_ipc_ba_q(3 to 4)="00" and ex3_ipc_ba_q(0)='0'; +ex3_data_w3_sel(1) <= (ex3_ipc_sz_q="00" and ex3_ipc_ba_q(3 to 4)="01") or + (ex3_ipc_sz_q="01" and ex3_ipc_ba_q(3)='0'); +ex3_data_w3_sel(2) <= ex3_ipc_sz_q="00" and ex3_ipc_ba_q(3 to 4)="10"; +ex3_data_w3_sel(3) <= (ex3_ipc_sz_q="00" and ex3_ipc_ba_q(3 to 4)="11") or ex3_ipc_sz_q="10" or + (ex3_ipc_sz_q="01" and ex3_ipc_ba_q(3)='1'); + +ex3_inbox_data(96 to 127) <= gate_and(ex3_data_w3_sel(0), ib_rd_data(0 to 31)) or + gate_and(ex3_data_w3_sel(1), ib_rd_data(32 to 63)) or + gate_and(ex3_data_w3_sel(2), ib_rd_data(64 to 95)) or + gate_and(ex3_data_w3_sel(3), ib_rd_data(96 to 127)) or + gate_and(ex3_data_sel_status, x"0000000" & "000" & ex4_ib_rd_status_reg); + +ex3_ib_data_ecc3(0 to 6)<= gate_and(ex3_data_w3_sel(0), ib_rd_data_ecc0(0 to 6)) or + gate_and(ex3_data_w3_sel(1), ib_rd_data_ecc1(0 to 6)) or + gate_and(ex3_data_w3_sel(2), ib_rd_data_ecc2(0 to 6)) or + gate_and(ex3_data_w3_sel(3), ib_rd_data_ecc3(0 to 6)); + + +latch_ex4_dp_data : tri_rlmreg_p + generic map (width => ex4_inbox_data'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ex3_mfdp_val_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_dp_data_offset to ex4_dp_data_offset + ex4_inbox_data'length-1), + scout => sov(ex4_dp_data_offset to ex4_dp_data_offset + ex4_inbox_data'length-1), + din => ex3_inbox_data(0 to 127), + dout => ex4_inbox_data(0 to 127) ); + + +latch_ex4_ib_data_ecc0 : tri_rlmreg_p + generic map (width => ex4_ib_data_ecc0'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ex3_mfdp_val_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_ib_data_ecc0_offset to ex4_ib_data_ecc0_offset + ex4_ib_data_ecc0'length-1), + scout => sov(ex4_ib_data_ecc0_offset to ex4_ib_data_ecc0_offset + ex4_ib_data_ecc0'length-1), + din => ex3_ib_data_ecc0(0 to 6), + dout => ex4_ib_data_ecc0(0 to 6) ); + +latch_ex4_ib_data_ecc1 : tri_rlmreg_p + generic map (width => ex4_ib_data_ecc1'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ex3_mfdp_val_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_ib_data_ecc1_offset to ex4_ib_data_ecc1_offset + ex4_ib_data_ecc1'length-1), + scout => sov(ex4_ib_data_ecc1_offset to ex4_ib_data_ecc1_offset + ex4_ib_data_ecc1'length-1), + din => ex3_ib_data_ecc1(0 to 6), + dout => ex4_ib_data_ecc1(0 to 6) ); + +latch_ex4_ib_data_ecc2 : tri_rlmreg_p + generic map (width => ex4_ib_data_ecc2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ex3_mfdp_val_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_ib_data_ecc2_offset to ex4_ib_data_ecc2_offset + ex4_ib_data_ecc2'length-1), + scout => sov(ex4_ib_data_ecc2_offset to ex4_ib_data_ecc2_offset + ex4_ib_data_ecc2'length-1), + din => ex3_ib_data_ecc2(0 to 6), + dout => ex4_ib_data_ecc2(0 to 6) ); + +latch_ex4_ib_data_ecc3 : tri_rlmreg_p + generic map (width => ex4_ib_data_ecc3'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ex3_mfdp_val_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_ib_data_ecc3_offset to ex4_ib_data_ecc3_offset + ex4_ib_data_ecc3'length-1), + scout => sov(ex4_ib_data_ecc3_offset to ex4_ib_data_ecc3_offset + ex4_ib_data_ecc3'length-1), + din => ex3_ib_data_ecc3(0 to 6), + dout => ex4_ib_data_ecc3(0 to 6) ); + +bx_xu_ex5_dp_data(0 to 127) <= ex5_inbox_data_cor(0 to 127); + +ex3_mfdp_cr_status <= ex3_mfdp_val_q and ( (ib0_rd_val_reg and ex3_ipc_thrd_q="00") or + (ib1_rd_val_reg and ex3_ipc_thrd_q="01") or + (ib2_rd_val_reg and ex3_ipc_thrd_q="10") or + (ib3_rd_val_reg and ex3_ipc_thrd_q="11")); + +latch_ex4_mfdp_cr_status : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dp_op_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_mfdp_cr_status_offset to ex4_mfdp_cr_status_offset), + scout => sov(ex4_mfdp_cr_status_offset to ex4_mfdp_cr_status_offset), + din(0) => ex3_mfdp_cr_status, + dout(0) => ex4_mfdp_cr_status_i ); + +bx_xu_ex4_mfdp_cr_status <= ex4_mfdp_cr_status_i; + + +ex4_ib_ecc_val <= ex4_mfdp_cr_status_i and not ex4_ipc_ba_q(0); + +latch_ex5_ib_ecc_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dp_op_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex5_ib_ecc_val_offset to ex5_ib_ecc_val_offset), + scout => sov(ex5_ib_ecc_val_offset to ex5_ib_ecc_val_offset), + din(0) => ex4_ib_ecc_val, + dout(0) => ex5_ib_ecc_val ); + + + +latch_reld_data_val_dminus2 : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(reld_data_val_dminus2_offset to reld_data_val_dminus2_offset), + scout => sov(reld_data_val_dminus2_offset to reld_data_val_dminus2_offset), + din(0) => lsu_reld_data_vld, + dout(0) => lat_reld_data_val ); + +latch_reld_ditc : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(reld_ditc_offset to reld_ditc_offset), + scout => sov(reld_ditc_offset to reld_ditc_offset), + din(0) => lsu_reld_ditc, + dout(0) => lat_reld_ditc ); + +latch_reld_ecc_err : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(reld_ecc_err_offset to reld_ecc_err_offset), + scout => sov(reld_ecc_err_offset to reld_ecc_err_offset), + din(0) => lsu_reld_ecc_err, + dout(0) => lat_reld_ecc_err ); + +reld_data_val_dminus2 <= lat_reld_data_val and lat_reld_ditc; + +latch_reld_data_val_dminus1 : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(reld_data_val_dminus1_offset to reld_data_val_dminus1_offset), + scout => sov(reld_data_val_dminus1_offset to reld_data_val_dminus1_offset), + din(0) => reld_data_val_dminus2, + dout(0) => reld_data_val_dminus1 ); + +latch_reld_data_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(reld_data_val_offset to reld_data_val_offset), + scout => sov(reld_data_val_offset to reld_data_val_offset), + din(0) => reld_data_val_dminus1, + dout(0) => reld_data_val ); + +latch_reld_data_val_dplus1 : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(reld_data_val_dplus1_offset to reld_data_val_dplus1_offset), + scout => sov(reld_data_val_dplus1_offset to reld_data_val_dplus1_offset), + din(0) => reld_data_val, + dout(0) => reld_data_val_dplus1 ); + +latch_reld_core_tag_dminus2 : tri_rlmreg_p + generic map (width => lat_reld_core_tag'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(reld_core_tag_dminus2_offset to reld_core_tag_dminus2_offset + lat_reld_core_tag'length-1), + scout => sov(reld_core_tag_dminus2_offset to reld_core_tag_dminus2_offset + lat_reld_core_tag'length-1), + din => lsu_reld_core_tag, + dout => lat_reld_core_tag ); + +latch_reld_core_tag_dminus1 : tri_rlmreg_p + generic map (width => reld_core_tag_dminus1'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(reld_core_tag_dminus1_offset to reld_core_tag_dminus1_offset + reld_core_tag_dminus1'length-1), + scout => sov(reld_core_tag_dminus1_offset to reld_core_tag_dminus1_offset + reld_core_tag_dminus1'length-1), + din => lat_reld_core_tag, + dout => reld_core_tag_dminus1 ); + +latch_reld_core_tag : tri_rlmreg_p + generic map (width => reld_core_tag'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(reld_core_tag_offset to reld_core_tag_offset + reld_core_tag'length-1), + scout => sov(reld_core_tag_offset to reld_core_tag_offset + reld_core_tag'length-1), + din => reld_core_tag_dminus1, + dout => reld_core_tag ); + +latch_reld_core_tag_dplus1 : tri_rlmreg_p + generic map (width => reld_core_tag_dplus1'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(reld_core_tag_dplus1_offset to reld_core_tag_dplus1_offset + reld_core_tag_dplus1'length-1), + scout => sov(reld_core_tag_dplus1_offset to reld_core_tag_dplus1_offset + reld_core_tag_dplus1'length-1), + din => reld_core_tag, + dout => reld_core_tag_dplus1 ); + +latch_reld_qw_dminus2 : tri_rlmreg_p + generic map (width => lat_reld_qw'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(reld_qw_dminus2_offset to reld_qw_dminus2_offset + lat_reld_qw'length-1), + scout => sov(reld_qw_dminus2_offset to reld_qw_dminus2_offset + lat_reld_qw'length-1), + din => lsu_reld_qw, + dout => lat_reld_qw ); + +latch_reld_qw_dminus1 : tri_rlmreg_p + generic map (width => reld_qw_dminus1'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(reld_qw_dminus1_offset to reld_qw_dminus1_offset + reld_qw_dminus1'length-1), + scout => sov(reld_qw_dminus1_offset to reld_qw_dminus1_offset + reld_qw_dminus1'length-1), + din => lat_reld_qw, + dout => reld_qw_dminus1 ); + +latch_reld_qw : tri_rlmreg_p + generic map (width => reld_qw'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(reld_qw_offset to reld_qw_offset + reld_qw'length-1), + scout => sov(reld_qw_offset to reld_qw_offset + reld_qw'length-1), + din => reld_qw_dminus1, + dout => reld_qw ); + +latch_reld_data : tri_rlmreg_p + generic map (width => lat_reld_data'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => reld_data_val_dminus1, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(reld_data_offset to reld_data_offset + lat_reld_data'length-1), + scout => sov(reld_data_offset to reld_data_offset + lat_reld_data'length-1), + din => lsu_reld_data, + dout => lat_reld_data ); + + + +ib_di_eccgen0: entity work.xuq_eccgen(xuq_eccgen) + generic map ( regsize => 32 ) + port map(din(0 to 31) => lat_reld_data(0 to 31), + din(32 to 38) => "1111111", + syn => ib_datain_ecc0 ); + +ib_di_eccgen1: entity work.xuq_eccgen(xuq_eccgen) + generic map ( regsize => 32 ) + port map(din(0 to 31) => lat_reld_data(32 to 63), + din(32 to 38) => "1111111", + syn => ib_datain_ecc1 ); + +ib_di_eccgen2: entity work.xuq_eccgen(xuq_eccgen) + generic map ( regsize => 32 ) + port map(din(0 to 31) => lat_reld_data(64 to 95), + din(32 to 38) => "1111111", + syn => ib_datain_ecc2 ); + +ib_di_eccgen3: entity work.xuq_eccgen(xuq_eccgen) + generic map ( regsize => 32 ) + port map(din(0 to 31) => lat_reld_data(96 to 127), + din(32 to 38) => "1111111", + syn => ib_datain_ecc3 ); + + +ib0_wrt_entry_ptr_minus1 <= std_ulogic_vector(unsigned(ib0_wrt_entry_ptr_q) - 1); +ib1_wrt_entry_ptr_minus1 <= std_ulogic_vector(unsigned(ib1_wrt_entry_ptr_q) - 1); +ib2_wrt_entry_ptr_minus1 <= std_ulogic_vector(unsigned(ib2_wrt_entry_ptr_q) - 1); +ib3_wrt_entry_ptr_minus1 <= std_ulogic_vector(unsigned(ib3_wrt_entry_ptr_q) - 1); + +dec_ib0_wrt_entry_ptr <= ib0_set_val_q and lat_reld_ecc_err; +dec_ib1_wrt_entry_ptr <= ib1_set_val_q and lat_reld_ecc_err; +dec_ib2_wrt_entry_ptr <= ib2_set_val_q and lat_reld_ecc_err; +dec_ib3_wrt_entry_ptr <= ib3_set_val_q and lat_reld_ecc_err; + +ib0_wrt_entry_ptr_d <= std_ulogic_vector(unsigned(ib0_wrt_entry_ptr_q) + 1) when ib0_set_val='1' else + std_ulogic_vector(unsigned(ib0_wrt_entry_ptr_q) - 1) when dec_ib0_wrt_entry_ptr='1' else + ib0_wrt_entry_ptr_q(0 to 1); + +ib1_wrt_entry_ptr_d <= std_ulogic_vector(unsigned(ib1_wrt_entry_ptr_q) + 1) when ib1_set_val='1' else + std_ulogic_vector(unsigned(ib1_wrt_entry_ptr_q) - 1) when dec_ib1_wrt_entry_ptr='1' else + ib1_wrt_entry_ptr_q(0 to 1); + +ib2_wrt_entry_ptr_d <= std_ulogic_vector(unsigned(ib2_wrt_entry_ptr_q) + 1) when ib2_set_val='1' else + std_ulogic_vector(unsigned(ib2_wrt_entry_ptr_q) - 1) when dec_ib2_wrt_entry_ptr='1' else + ib2_wrt_entry_ptr_q(0 to 1); + +ib3_wrt_entry_ptr_d <= std_ulogic_vector(unsigned(ib3_wrt_entry_ptr_q) + 1) when ib3_set_val='1' else + std_ulogic_vector(unsigned(ib3_wrt_entry_ptr_q) - 1) when dec_ib3_wrt_entry_ptr='1' else + ib3_wrt_entry_ptr_q(0 to 1); + + +latch_ib0_wrt_entry_ptr : tri_rlmreg_p + generic map (width => ib0_wrt_entry_ptr_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => reld_data_val, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib0_wrt_entry_ptr_offset to ib0_wrt_entry_ptr_offset + ib0_wrt_entry_ptr_q'length-1), + scout => sov(ib0_wrt_entry_ptr_offset to ib0_wrt_entry_ptr_offset + ib0_wrt_entry_ptr_q'length-1), + din => ib0_wrt_entry_ptr_d(0 to 1), + dout => ib0_wrt_entry_ptr_q(0 to 1) ); + +latch_ib1_wrt_entry_ptr : tri_rlmreg_p + generic map (width => ib1_wrt_entry_ptr_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => reld_data_val, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib1_wrt_entry_ptr_offset to ib1_wrt_entry_ptr_offset + ib1_wrt_entry_ptr_q'length-1), + scout => sov(ib1_wrt_entry_ptr_offset to ib1_wrt_entry_ptr_offset + ib1_wrt_entry_ptr_q'length-1), + din => ib1_wrt_entry_ptr_d(0 to 1), + dout => ib1_wrt_entry_ptr_q(0 to 1) ); + +latch_ib2_wrt_entry_ptr : tri_rlmreg_p + generic map (width => ib2_wrt_entry_ptr_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => reld_data_val, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib2_wrt_entry_ptr_offset to ib2_wrt_entry_ptr_offset + ib2_wrt_entry_ptr_q'length-1), + scout => sov(ib2_wrt_entry_ptr_offset to ib2_wrt_entry_ptr_offset + ib2_wrt_entry_ptr_q'length-1), + din => ib2_wrt_entry_ptr_d(0 to 1), + dout => ib2_wrt_entry_ptr_q(0 to 1) ); + +latch_ib3_wrt_entry_ptr : tri_rlmreg_p + generic map (width => ib3_wrt_entry_ptr_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => reld_data_val, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib3_wrt_entry_ptr_offset to ib3_wrt_entry_ptr_offset + ib3_wrt_entry_ptr_q'length-1), + scout => sov(ib3_wrt_entry_ptr_offset to ib3_wrt_entry_ptr_offset + ib3_wrt_entry_ptr_q'length-1), + din => ib3_wrt_entry_ptr_d(0 to 1), + dout => ib3_wrt_entry_ptr_q(0 to 1) ); + +ib0_wrt_entry_ptr <= ib0_wrt_entry_ptr_q when dec_ib0_wrt_entry_ptr='0' else + ib0_wrt_entry_ptr_minus1; + +ib1_wrt_entry_ptr <= ib1_wrt_entry_ptr_q when dec_ib1_wrt_entry_ptr='0' else + ib1_wrt_entry_ptr_minus1; + +ib2_wrt_entry_ptr <= ib2_wrt_entry_ptr_q when dec_ib2_wrt_entry_ptr='0' else + ib2_wrt_entry_ptr_minus1; + +ib3_wrt_entry_ptr <= ib3_wrt_entry_ptr_q when dec_ib3_wrt_entry_ptr='0' else + ib3_wrt_entry_ptr_minus1; + + +ib0_wrt_data_ctr_d(0 to 1) <= std_ulogic_vector(unsigned(ib0_wrt_data_ctr_q) + 1) when (reld_data_val_dminus1='1' and reld_core_tag_dminus1="00") else + ib0_wrt_data_ctr_q; + +ib1_wrt_data_ctr_d(0 to 1) <= std_ulogic_vector(unsigned(ib1_wrt_data_ctr_q) + 1) when (reld_data_val_dminus1='1' and reld_core_tag_dminus1="01") else + ib1_wrt_data_ctr_q; + +ib2_wrt_data_ctr_d(0 to 1) <= std_ulogic_vector(unsigned(ib2_wrt_data_ctr_q) + 1) when (reld_data_val_dminus1='1' and reld_core_tag_dminus1="10") else + ib2_wrt_data_ctr_q; + +ib3_wrt_data_ctr_d(0 to 1) <= std_ulogic_vector(unsigned(ib3_wrt_data_ctr_q) + 1) when (reld_data_val_dminus1='1' and reld_core_tag_dminus1="11") else + ib3_wrt_data_ctr_q; + +latch_ib0_wrt_data_ctr : tri_rlmreg_p + generic map (width => ib0_wrt_data_ctr_q'length, init => 3, expand_type => expand_type) + port map (nclk => nclk, + act => reld_data_val_dminus1, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib0_wrt_data_ctr_offset to ib0_wrt_data_ctr_offset + ib0_wrt_data_ctr_q'length-1), + scout => sov(ib0_wrt_data_ctr_offset to ib0_wrt_data_ctr_offset + ib0_wrt_data_ctr_q'length-1), + din => ib0_wrt_data_ctr_d(0 to 1), + dout => ib0_wrt_data_ctr_q(0 to 1)); + +latch_ib1_wrt_data_ctr : tri_rlmreg_p + generic map (width => ib1_wrt_data_ctr_q'length, init => 3, expand_type => expand_type) + port map (nclk => nclk, + act => reld_data_val_dminus1, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib1_wrt_data_ctr_offset to ib1_wrt_data_ctr_offset + ib1_wrt_data_ctr_q'length-1), + scout => sov(ib1_wrt_data_ctr_offset to ib1_wrt_data_ctr_offset + ib1_wrt_data_ctr_q'length-1), + din => ib1_wrt_data_ctr_d(0 to 1), + dout => ib1_wrt_data_ctr_q(0 to 1)); + +latch_ib2_wrt_data_ctr : tri_rlmreg_p + generic map (width => ib2_wrt_data_ctr_q'length, init => 3, expand_type => expand_type) + port map (nclk => nclk, + act => reld_data_val_dminus1, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib2_wrt_data_ctr_offset to ib2_wrt_data_ctr_offset + ib2_wrt_data_ctr_q'length-1), + scout => sov(ib2_wrt_data_ctr_offset to ib2_wrt_data_ctr_offset + ib2_wrt_data_ctr_q'length-1), + din => ib2_wrt_data_ctr_d(0 to 1), + dout => ib2_wrt_data_ctr_q(0 to 1)); + +latch_ib3_wrt_data_ctr : tri_rlmreg_p + generic map (width => ib3_wrt_data_ctr_q'length, init => 3, expand_type => expand_type) + port map (nclk => nclk, + act => reld_data_val_dminus1, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib3_wrt_data_ctr_offset to ib3_wrt_data_ctr_offset + ib3_wrt_data_ctr_q'length-1), + scout => sov(ib3_wrt_data_ctr_offset to ib3_wrt_data_ctr_offset + ib3_wrt_data_ctr_q'length-1), + din => ib3_wrt_data_ctr_d(0 to 1), + dout => ib3_wrt_data_ctr_q(0 to 1)); + + +ib_wrt_thrd(0 to 1) <= reld_core_tag(3 to 4); + +with ib_wrt_thrd select + ib_wrt_entry_pointer <= ib0_wrt_entry_ptr when "00", + ib1_wrt_entry_ptr when "01", + ib2_wrt_entry_ptr when "10", + ib3_wrt_entry_ptr when others; + + +ib_ary_wrt_addr(0 to 5) <= ib_wrt_thrd & ib_wrt_entry_pointer & reld_qw(58 to 59); + +ib_wen <= reld_data_val; +ib_ary_wen <= (others => ib_wen); + + +ib0_ecc_err_d <= (reld_data_val_dplus1 and lat_reld_ecc_err and not(ib0_wrt_data_ctr_q="11") and not ib0_set_val_q and reld_core_tag_dplus1="00") or + (ib0_ecc_err_q and not (ib0_wrt_data_ctr_q="11")); + +ib1_ecc_err_d <= (reld_data_val_dplus1 and lat_reld_ecc_err and not(ib1_wrt_data_ctr_q="11") and not ib1_set_val_q and reld_core_tag_dplus1="01") or + (ib1_ecc_err_q and not (ib1_wrt_data_ctr_q="11")); + +ib2_ecc_err_d <= (reld_data_val_dplus1 and lat_reld_ecc_err and not(ib2_wrt_data_ctr_q="11") and not ib2_set_val_q and reld_core_tag_dplus1="10") or + (ib2_ecc_err_q and not (ib2_wrt_data_ctr_q="11")); + +ib3_ecc_err_d <= (reld_data_val_dplus1 and lat_reld_ecc_err and not(ib3_wrt_data_ctr_q="11") and not ib3_set_val_q and reld_core_tag_dplus1="11") or + (ib3_ecc_err_q and not (ib3_wrt_data_ctr_q="11")); + +latch_ib0_ecc_err : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib0_ecc_err_offset to ib0_ecc_err_offset), + scout => sov(ib0_ecc_err_offset to ib0_ecc_err_offset), + din(0) => ib0_ecc_err_d, + dout(0) => ib0_ecc_err_q ); + +latch_ib1_ecc_err : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib1_ecc_err_offset to ib1_ecc_err_offset), + scout => sov(ib1_ecc_err_offset to ib1_ecc_err_offset), + din(0) => ib1_ecc_err_d, + dout(0) => ib1_ecc_err_q ); + +latch_ib2_ecc_err : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib2_ecc_err_offset to ib2_ecc_err_offset), + scout => sov(ib2_ecc_err_offset to ib2_ecc_err_offset), + din(0) => ib2_ecc_err_d, + dout(0) => ib2_ecc_err_q ); + +latch_ib3_ecc_err : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib3_ecc_err_offset to ib3_ecc_err_offset), + scout => sov(ib3_ecc_err_offset to ib3_ecc_err_offset), + din(0) => ib3_ecc_err_d, + dout(0) => ib3_ecc_err_q ); + +ib0_set_val <= ib0_wrt_data_ctr_q="11" and reld_data_val and ib_wrt_thrd="00" and not (ib0_ecc_err_q or (reld_data_val_dplus1 and lat_reld_ecc_err and reld_core_tag_dplus1="00")); +ib1_set_val <= ib1_wrt_data_ctr_q="11" and reld_data_val and ib_wrt_thrd="01" and not (ib1_ecc_err_q or (reld_data_val_dplus1 and lat_reld_ecc_err and reld_core_tag_dplus1="01")); +ib2_set_val <= ib2_wrt_data_ctr_q="11" and reld_data_val and ib_wrt_thrd="10" and not (ib2_ecc_err_q or (reld_data_val_dplus1 and lat_reld_ecc_err and reld_core_tag_dplus1="10")); +ib3_set_val <= ib3_wrt_data_ctr_q="11" and reld_data_val and ib_wrt_thrd="11" and not (ib3_ecc_err_q or (reld_data_val_dplus1 and lat_reld_ecc_err and reld_core_tag_dplus1="11")); + + +ib0_buf0_set_val <= ib0_set_val and ib0_wrt_entry_ptr_q="00"; +ib0_buf1_set_val <= ib0_set_val and ib0_wrt_entry_ptr_q="01"; +ib0_buf2_set_val <= ib0_set_val and ib0_wrt_entry_ptr_q="10"; +ib0_buf3_set_val <= ib0_set_val and ib0_wrt_entry_ptr_q="11"; +ib1_buf0_set_val <= ib1_set_val and ib1_wrt_entry_ptr_q="00"; +ib1_buf1_set_val <= ib1_set_val and ib1_wrt_entry_ptr_q="01"; +ib1_buf2_set_val <= ib1_set_val and ib1_wrt_entry_ptr_q="10"; +ib1_buf3_set_val <= ib1_set_val and ib1_wrt_entry_ptr_q="11"; +ib2_buf0_set_val <= ib2_set_val and ib2_wrt_entry_ptr_q="00"; +ib2_buf1_set_val <= ib2_set_val and ib2_wrt_entry_ptr_q="01"; +ib2_buf2_set_val <= ib2_set_val and ib2_wrt_entry_ptr_q="10"; +ib2_buf3_set_val <= ib2_set_val and ib2_wrt_entry_ptr_q="11"; +ib3_buf0_set_val <= ib3_set_val and ib3_wrt_entry_ptr_q="00"; +ib3_buf1_set_val <= ib3_set_val and ib3_wrt_entry_ptr_q="01"; +ib3_buf2_set_val <= ib3_set_val and ib3_wrt_entry_ptr_q="10"; +ib3_buf3_set_val <= ib3_set_val and ib3_wrt_entry_ptr_q="11"; + +ib0_buf0_reset_val <= ib0_set_val_q and lat_reld_ecc_err and ib0_wrt_entry_ptr="00"; +ib0_buf1_reset_val <= ib0_set_val_q and lat_reld_ecc_err and ib0_wrt_entry_ptr="01"; +ib0_buf2_reset_val <= ib0_set_val_q and lat_reld_ecc_err and ib0_wrt_entry_ptr="10"; +ib0_buf3_reset_val <= ib0_set_val_q and lat_reld_ecc_err and ib0_wrt_entry_ptr="11"; +ib1_buf0_reset_val <= ib1_set_val_q and lat_reld_ecc_err and ib1_wrt_entry_ptr="00"; +ib1_buf1_reset_val <= ib1_set_val_q and lat_reld_ecc_err and ib1_wrt_entry_ptr="01"; +ib1_buf2_reset_val <= ib1_set_val_q and lat_reld_ecc_err and ib1_wrt_entry_ptr="10"; +ib1_buf3_reset_val <= ib1_set_val_q and lat_reld_ecc_err and ib1_wrt_entry_ptr="11"; +ib2_buf0_reset_val <= ib2_set_val_q and lat_reld_ecc_err and ib2_wrt_entry_ptr="00"; +ib2_buf1_reset_val <= ib2_set_val_q and lat_reld_ecc_err and ib2_wrt_entry_ptr="01"; +ib2_buf2_reset_val <= ib2_set_val_q and lat_reld_ecc_err and ib2_wrt_entry_ptr="10"; +ib2_buf3_reset_val <= ib2_set_val_q and lat_reld_ecc_err and ib2_wrt_entry_ptr="11"; +ib3_buf0_reset_val <= ib3_set_val_q and lat_reld_ecc_err and ib3_wrt_entry_ptr="00"; +ib3_buf1_reset_val <= ib3_set_val_q and lat_reld_ecc_err and ib3_wrt_entry_ptr="01"; +ib3_buf2_reset_val <= ib3_set_val_q and lat_reld_ecc_err and ib3_wrt_entry_ptr="10"; +ib3_buf3_reset_val <= ib3_set_val_q and lat_reld_ecc_err and ib3_wrt_entry_ptr="11"; + +latch_ib0_set_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib0_set_val_offset to ib0_set_val_offset), + scout => sov(ib0_set_val_offset to ib0_set_val_offset), + din(0) => ib0_set_val, + dout(0) => ib0_set_val_q ); + +latch_ib1_set_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib1_set_val_offset to ib1_set_val_offset), + scout => sov(ib1_set_val_offset to ib1_set_val_offset), + din(0) => ib1_set_val, + dout(0) => ib1_set_val_q ); + +latch_ib2_set_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib2_set_val_offset to ib2_set_val_offset), + scout => sov(ib2_set_val_offset to ib2_set_val_offset), + din(0) => ib2_set_val, + dout(0) => ib2_set_val_q ); + +latch_ib3_set_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib3_set_val_offset to ib3_set_val_offset), + scout => sov(ib3_set_val_offset to ib3_set_val_offset), + din(0) => ib3_set_val, + dout(0) => ib3_set_val_q ); + + + +dbg_group0_d <= ob_status_reg_newdata; + +dbg_group0 <= my_ex3_flush & + my_ex4_stg_flush & + my_ex5_stg_flush & + my_ex6_stg_flush & + my_ccr2_en_ditc_q & + ex4_mtdp_val_q & + ex4_ipc_thrd_q & + ex4_ipc_ba_q & + ex4_ipc_sz_q & + ob0_wrt_entry_ptr_q & + ob1_wrt_entry_ptr_q & + ob2_wrt_entry_ptr_q & + ob3_wrt_entry_ptr_q & + dbg_group0_q & + ob0_buf0_status_q(0) & + ob0_buf1_status_q(0) & + ob0_buf2_status_q(0) & + ob0_buf3_status_q(0) & + ob1_buf0_status_q(0) & + ob1_buf1_status_q(0) & + ob1_buf2_status_q(0) & + ob1_buf3_status_q(0) & + ob2_buf0_status_q(0) & + ob2_buf1_status_q(0) & + ob2_buf2_status_q(0) & + ob2_buf3_status_q(0) & + ob3_buf0_status_q(0) & + ob3_buf1_status_q(0) & + ob3_buf2_status_q(0) & + ob3_buf3_status_q(0) & + ob_wen & + ex4_mtdp_cr_status & + outbox_ecc_err_q & + outbox_ue_q & + ob0_rd_entry_ptr_q & + ob1_rd_entry_ptr_q & + ob2_rd_entry_ptr_q & + ob3_rd_entry_ptr_q & + ob_to_node_data_ptr & + ob_to_node_sel_q & + ob_to_node_sel_sav_q & + bx_slowspr_val_q & + ditc_addr_sel & + bx_slowspr_rw_q & + bx_slowspr_etid_q & + ob_err_inj_q ; + +dbg_group1 <= ob_to_node_status_reg & + ob_to_nd_val_t0 & + ob_to_nd_val_t1 & + ob_to_nd_val_t2 & + ob_to_nd_val_t3 & + lsu_cmd_avail_q & + lsu_cmd_sent_q & + lsu_cmd_stall_q & + ob_cmd_sent_count_q & + ob_cmd_count_t0_q & + ob_cmd_count_t1_q & + ob_cmd_count_t2_q & + ob_cmd_count_t3_q & + send_ob_state_q & + dly_ob_cmd_val_q(1) & + dly_ob_ditc_val_q(1) & + dly1_ob_qw & + ob_to_node_selected_thrd(0 to 1) & + ob_addr_d & + lat_st_pop & + lat_st_pop_thrd(0 to 2); + +dbg_group2 <= my_ex3_flush & + my_ex4_stg_flush & + my_ex5_stg_flush & + my_ex6_stg_flush & + my_ccr2_en_ditc_q & + ex4_mfdp_val_q & + ex4_mtdp_val_q & + ex4_ipc_thrd_q & + ex4_ipc_ba_q & + ex4_ipc_sz_q & + ib0_rd_entry_ptr_q & + ib1_rd_entry_ptr_q & + ib2_rd_entry_ptr_q & + ib3_rd_entry_ptr_q & + ib_t0_pop_d & + ib_t1_pop_d & + ib_t2_pop_d & + ib_t3_pop_d & + ib0_buf0_val_q & + ib0_buf1_val_q & + ib0_buf2_val_q & + ib0_buf3_val_q & + ib1_buf0_val_q & + ib1_buf1_val_q & + ib1_buf2_val_q & + ib1_buf3_val_q & + ib2_buf0_val_q & + ib2_buf1_val_q & + ib2_buf2_val_q & + ib2_buf3_val_q & + ib3_buf0_val_q & + ib3_buf1_val_q & + ib3_buf2_val_q & + ib3_buf3_val_q & + ex5_ib_val_save_q & + ex6_ib_val_save_q & + inbox_ecc_err_q & + inbox_ue_q & + ex4_ib_rd_status_reg & + ex4_mfdp_cr_status_i & + lat_reld_data_val & + lat_reld_ditc & + lat_reld_core_tag & + lat_reld_qw & + ib0_wrt_entry_ptr_q & + ib1_wrt_entry_ptr_q & + ib2_wrt_entry_ptr_q & + ib3_wrt_entry_ptr_q & + ib0_wrt_data_ctr_q & + ib1_wrt_data_ctr_q & + ib2_wrt_data_ctr_q & + ib3_wrt_data_ctr_q & + lat_reld_data(24 to 31) & + ex5_inbox_data_cor(24 to 31); + +dbg_group3 <= lat_reld_data(56 to 63) & + lat_reld_data(88 to 95) & + ex5_inbox_data_cor(56 to 63) & + ex5_inbox_data_cor(88 to 95) & + ex5_inbox_data_cor(120 to 127) & + ob_ary_wrt_data_l2(24 to 31) & + ob_ary_wrt_data_l2(56 to 63) & + ob_ary_wrt_data_l2(88 to 95) & + ob_rd_data_cor_l2(24 to 31) & + ob_rd_data_cor_l2(56 to 63) & + ob_rd_data_cor_l2(120 to 127); + +trg_group0 <= ex4_mtdp_val_q & + ex4_mfdp_val_q & + my_ex4_stg_flush & + my_ex5_stg_flush & + my_ex6_stg_flush & + ob_to_nd_ready & + dly_ob_cmd_val_q(1) & + dly_ob_ditc_val_q(1) & + ob_credit_t0 & + ob_credit_t1 & + ob_credit_t2 & + ob_credit_t3; + +trg_group1 <= ex5_ob0_flushed & + ex5_ob1_flushed & + ex5_ob2_flushed & + ex5_ob3_flushed & + ex6_ob0_flushed & + ex6_ob1_flushed & + ex6_ob2_flushed & + ex6_ob3_flushed & + ex4_mtdp_cr_status & + ob_lsu_complete & + outbox_ecc_err_q & + outbox_ue_q ; + +trg_group2 <= ex4_ipc_thrd_q & + ex4_ipc_ba_q & + ex4_ib0_flushed & + ex4_ib1_flushed & + ex4_ib2_flushed & + ex4_ib3_flushed & + ex4_mfdp_cr_status_i; + +trg_group3 <= ex5_ib0_flushed & + ex5_ib1_flushed & + ex5_ib2_flushed & + ex5_ib3_flushed & + ex6_ib0_flushed & + ex6_ib1_flushed & + ex6_ib2_flushed & + ex6_ib3_flushed & + lat_reld_data_val & + lat_reld_ditc & + lat_reld_core_tag ; + +latch_debug_dbg_group0 : tri_rlmreg_p + generic map (width => dbg_group0_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => trace_bus_enable_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(debug_dbg_group0_offset to debug_dbg_group0_offset + dbg_group0_q'length-1), + scout => sov(debug_dbg_group0_offset to debug_dbg_group0_offset + dbg_group0_q'length-1), + din => dbg_group0_d, + dout => dbg_group0_q); + + +latch_trace_bus_enable : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(trace_bus_enable_offset to trace_bus_enable_offset), + scout => sov(trace_bus_enable_offset to trace_bus_enable_offset), + din(0) => pc_bx_trace_bus_enable, + dout(0) => trace_bus_enable_q ); + +latch_debug_mux_ctrls : tri_rlmreg_p + generic map (width => debug_mux1_ctrls_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => trace_bus_enable_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(debug_mux_ctrls_offset to debug_mux_ctrls_offset + debug_mux1_ctrls_q'length-1), + scout => sov(debug_mux_ctrls_offset to debug_mux_ctrls_offset + debug_mux1_ctrls_q'length-1), + din => pc_bx_debug_mux1_ctrls(0 to 15), + dout => debug_mux1_ctrls_q(0 to 15)); + +debug_mux : entity clib.c_debug_mux4(c_debug_mux4) + port map ( + vd => vdd, + gd => gnd, + select_bits => debug_mux1_ctrls_q, + trace_data_in => debug_data_in, + trigger_data_in => trigger_data_in, + + dbg_group0 => dbg_group0, + dbg_group1 => dbg_group1, + dbg_group2 => dbg_group2, + dbg_group3 => dbg_group3, + + trg_group0 => trg_group0, + trg_group1 => trg_group1, + trg_group2 => trg_group2, + trg_group3 => trg_group3, + + trace_data_out => debug_mux_out_d, + trigger_data_out => trigger_mux_out_d + ); + + +latch_debug_mux_out : tri_rlmreg_p + generic map (width => debug_mux_out_d'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => trace_bus_enable_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(debug_mux_out_offset to debug_mux_out_offset + debug_mux_out_d'length-1), + scout => sov(debug_mux_out_offset to debug_mux_out_offset + debug_mux_out_d'length-1), + din => debug_mux_out_d(0 to 87), + dout => debug_data_out(0 to 87)); + + +latch_trigger_mux_out : tri_rlmreg_p + generic map (width => trigger_mux_out_d'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => trace_bus_enable_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(trigger_mux_out_offset to trigger_mux_out_offset + trigger_mux_out_d'length-1), + scout => sov(trigger_mux_out_offset to trigger_mux_out_offset + trigger_mux_out_d'length-1), + din => trigger_mux_out_d(0 to 11), + dout => trigger_data_out(0 to 11)); + + +perv_3to2_reg: tri_plat + generic map (width => 11, expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_bx_ccflush_dc, + din(0) => pc_bx_func_sl_thold_3, + din(1) => pc_bx_gptr_sl_thold_3, + din(2) => pc_bx_sg_3, + din(3) => pc_bx_abst_sl_thold_3, + din(4) => pc_bx_time_sl_thold_3, + din(5) => pc_bx_ary_nsl_thold_3, + din(6) => pc_bx_repr_sl_thold_3, + din(7) => pc_bx_func_slp_sl_thold_3, + din(8) => pc_bx_ary_slp_nsl_thold_3, + din(9) => pc_bx_bolt_sl_thold_3, + din(10) => pc_bx_bo_enable_3, + q(0) => func_sl_thold_2, + q(1) => gptr_sl_thold_2, + q(2) => sg_2, + q(3) => abst_sl_thold_2, + q(4) => time_sl_thold_2, + q(5) => ary_nsl_thold_2, + q(6) => repr_sl_thold_2, + q(7) => func_slp_sl_thold_2, + q(8) => ary_slp_nsl_thold_2, + q(9) => bolt_sl_thold_2, + q(10) => bolt_enable_2); + + +perv_2to1_reg: tri_plat + generic map (width => 10, expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_bx_ccflush_dc, + din(0) => func_sl_thold_2, + din(1) => gptr_sl_thold_2, + din(2) => sg_2, + din(3) => abst_sl_thold_2, + din(4) => time_sl_thold_2, + din(5) => ary_nsl_thold_2, + din(6) => repr_sl_thold_2, + din(7) => func_slp_sl_thold_2, + din(8) => ary_slp_nsl_thold_2, + din(9) => bolt_sl_thold_2, + q(0) => func_sl_thold_1, + q(1) => gptr_sl_thold_1, + q(2) => sg_1, + q(3) => abst_sl_thold_1, + q(4) => time_sl_thold_1, + q(5) => ary_nsl_thold_1, + q(6) => repr_sl_thold_1, + q(7) => func_slp_sl_thold_1, + q(8) => ary_slp_nsl_thold_1, + q(9) => bolt_sl_thold_1); + +perv_1to0_reg: tri_plat + generic map (width => 10, expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_bx_ccflush_dc, + din(0) => func_sl_thold_1, + din(1) => gptr_sl_thold_1, + din(2) => sg_1, + din(3) => abst_sl_thold_1, + din(4) => time_sl_thold_1, + din(5) => ary_nsl_thold_1, + din(6) => repr_sl_thold_1, + din(7) => func_slp_sl_thold_1, + din(8) => ary_slp_nsl_thold_1, + din(9) => bolt_sl_thold_1, + q(0) => func_sl_thold_0, + q(1) => gptr_sl_thold_0, + q(2) => sg_0, + q(3) => abst_sl_thold_0, + q(4) => time_sl_thold_0, + q(5) => ary_nsl_thold_0, + q(6) => repr_sl_thold_0, + q(7) => func_slp_sl_thold_0, + q(8) => ary_slp_nsl_thold_0, + q(9) => bolt_sl_thold_0); + +perv_lcbor_func_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_dc_b, + thold => func_sl_thold_0, + sg => sg_0, + act_dis => tidn, + forcee => func_sl_force, + thold_b => func_sl_thold_0_b); + +perv_lcbor_func_slp_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_dc_b, + thold => func_slp_sl_thold_0, + sg => sg_0, + act_dis => tidn, + forcee => func_slp_sl_force, + thold_b => func_slp_sl_thold_0_b); + +ab_lcbor_func_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_dc_b, + thold => abst_sl_thold_0, + sg => sg_0, + act_dis => tidn, + forcee => abst_sl_force, + thold_b => abst_sl_thold_0_b); + +perv_lcbctrl_0: tri_lcbcntl_mac + generic map (expand_type => expand_type) +port map ( + vdd => vdd, + gnd => gnd, + sg => sg_0, + nclk => nclk, + scan_in => gptr_scan_in, + scan_diag_dc => an_ac_scan_diag_dc, + thold => gptr_sl_thold_0, + clkoff_dc_b => clkoff_dc_b, + delay_lclkr_dc => delay_lclkr_dc_v(0 to 4), + act_dis_dc => open, + d_mode_dc => d_mode_dc, + mpw1_dc_b => mpw1_dc_b_v(0 to 4), + mpw2_dc_b => mpw2_dc_b, + scan_out => int_gptr_scan_out); + +delay_lclkr_dc <= delay_lclkr_dc_v(0); +mpw1_dc_b <= mpw1_dc_b_v(0); + +perv_lcbctrl_ary_0: tri_lcbcntl_array_mac + generic map (expand_type => expand_type) +port map ( + vdd => vdd, + gnd => gnd, + sg => sg_0, + nclk => nclk, + scan_in => int_gptr_scan_out, + scan_diag_dc => an_ac_scan_diag_dc, + thold => gptr_sl_thold_0, + clkoff_dc_b => ary0_clkoff_dc_b, + delay_lclkr_dc => ary0_delay_lclkr_dc_v(0 to 4), + act_dis_dc => open, + d_mode_dc => ary0_d_mode_dc, + mpw1_dc_b => ary0_mpw1_dc_b_v(0 to 4), + mpw2_dc_b => ary0_mpw2_dc_b, + scan_out => int0_gptr_scan_out); + +perv_lcbctrl_ary_1: tri_lcbcntl_array_mac + generic map (expand_type => expand_type) +port map ( + vdd => vdd, + gnd => gnd, + sg => sg_0, + nclk => nclk, + scan_in => int0_gptr_scan_out, + scan_diag_dc => an_ac_scan_diag_dc, + thold => gptr_sl_thold_0, + clkoff_dc_b => ary1_clkoff_dc_b, + delay_lclkr_dc => ary1_delay_lclkr_dc_v(0 to 4), + act_dis_dc => open, + d_mode_dc => ary1_d_mode_dc, + mpw1_dc_b => ary1_mpw1_dc_b_v(0 to 4), + mpw2_dc_b => ary1_mpw2_dc_b, + scan_out => int1_gptr_scan_out); + +gptr_scan_out <= int1_gptr_scan_out and an_ac_scan_dis_dc_b; + +slat_force <= sg_0; +time_slat_thold_b <= NOT time_sl_thold_0; + +perv_lcbs_time: tri_lcbs + generic map (expand_type => expand_type ) + port map ( + vd => vdd, + gd => gnd, + delay_lclkr => delay_lclkr_dc, + nclk => nclk, + forcee => slat_force, + thold_b => time_slat_thold_b, + dclk => time_slat_d2clk, + lclk => time_slat_lclk ); + +perv_time_stg: tri_slat_scan + generic map (width => 2, init => "00", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => time_slat_d2clk, + lclk => time_slat_lclk, + scan_in(0) => time_scan_in, + scan_in(1) => ib_time_scan_out, + scan_out(0) => time_scan_in_q, + scan_out(1) => time_scan_out_stg ); + +time_scan_out <= time_scan_out_stg and an_ac_scan_dis_dc_b; + +repr_slat_thold_b <= NOT repr_sl_thold_0; + +perv_lcbs_repr: tri_lcbs + generic map (expand_type => expand_type ) + port map ( + vd => vdd, + gd => gnd, + delay_lclkr => delay_lclkr_dc, + nclk => nclk, + forcee => slat_force, + thold_b => repr_slat_thold_b, + dclk => repr_slat_d2clk, + lclk => repr_slat_lclk ); + +perv_repr_stg: tri_slat_scan + generic map (width => 2, init => "00", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => repr_slat_d2clk, + lclk => repr_slat_lclk, + scan_in(0) => repr_scan_in, + scan_in(1) => int_repr_scan_out, + scan_out(0) => repr_scan_in_q, + scan_out(1) => repr_scan_out_q ); + +repr_scan_out <= repr_scan_out_q and an_ac_scan_dis_dc_b; + +ab_reg: tri_rlmreg_p generic map (init => 0, expand_type => expand_type, width => 25, needs_sreset => 0) +port map (nclk => nclk, + act => pc_bx_abist_ena_dc, + forcee => abst_sl_force, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => abst_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => ab_reg_si(0 to 24), + scout => ab_reg_so(0 to 24), + din ( 0 to 3) => pc_bx_abist_di_0(0 to 3) , + din ( 4) => pc_bx_abist_g8t_bw_1 , + din ( 5) => pc_bx_abist_g8t_bw_0 , + din ( 6 to 11) => pc_bx_abist_waddr_0(4 to 9) , + din ( 12) => pc_bx_abist_g8t_wenb , + din (13 to 18) => pc_bx_abist_raddr_0(4 to 9), + din ( 19) => pc_bx_abist_g8t1p_renb_0, + din ( 20) => pc_bx_abist_wl64_comp_ena, + din (21 to 24) => pc_bx_abist_g8t_dcomp(0 to 3) , + dout( 0 to 3) => abist_di_0(0 to 3) , + dout( 4) => abist_g8t_bw_1 , + dout( 5) => abist_g8t_bw_0 , + dout( 6 to 11) => abist_waddr_0(4 to 9) , + dout( 12) => abist_g8t_wenb , + dout(13 to 18) => abist_raddr_0(4 to 9), + dout( 19) => abist_g8t1p_renb_0, + dout( 20) => abist_wl64_comp_ena, + dout(21 to 24) => abist_g8t_dcomp(0 to 3) ); + + + +latch_spare0 : tri_rlmreg_p + generic map (width => spare0_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(spare0_offset to spare0_offset + spare0_l2'length-1), + scout => sov(spare0_offset to spare0_offset + spare0_l2'length-1), + din => spare0_l2(0 to 7), + dout => spare0_l2(0 to 7) ); + +latch_spare1 : tri_rlmreg_p + generic map (width => spare1_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(spare1_offset to spare1_offset + spare1_l2'length-1), + scout => sov(spare1_offset to spare1_offset + spare1_l2'length-1), + din => spare1_l2, + dout => spare1_l2 ); + + +siv(0 to scan_right0-1) <= sov(1 to scan_right0-1) & func_scan_in(0); +func_scan_out(0) <= sov(0) and an_ac_scan_dis_dc_b; + +siv(scan_right0 to siv'right) <= sov(scan_right0+1 to siv'right) & func_scan_in(1); +func_scan_out(1) <= sov(scan_right0) and an_ac_scan_dis_dc_b; + +ab_reg_si(0 to 24) <= ab_reg_so(1 to 24) & ib_abst_scan_out; +abst_scan_out <= ab_reg_so(0) and an_ac_scan_dis_dc_b; + +end bxq; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq.vhdl new file mode 100644 index 0000000..8403692 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq.vhdl @@ -0,0 +1,1637 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + +entity fuq is +generic( + expand_type : integer := 2 ; + eff_ifar : integer := 62; + regmode : integer := 6); +port( + + pc_fu_ccflush_dc : in std_ulogic; + an_ac_scan_dis_dc_b : in std_ulogic; + an_ac_scan_diag_dc : in std_ulogic; + + pc_fu_gptr_sl_thold_3 : in std_ulogic; + pc_fu_time_sl_thold_3 : in std_ulogic; + pc_fu_repr_sl_thold_3 : in std_ulogic; + pc_fu_abst_sl_thold_3 : in std_ulogic; + pc_fu_abst_slp_sl_thold_3 : in std_ulogic; + pc_fu_func_sl_thold_3 : in std_ulogic_vector(0 to 1); + pc_fu_func_slp_sl_thold_3 : in std_ulogic_vector(0 to 1); + pc_fu_cfg_sl_thold_3 : in std_ulogic; + pc_fu_cfg_slp_sl_thold_3 : in std_ulogic; + pc_fu_func_nsl_thold_3 : in std_ulogic; + pc_fu_func_slp_nsl_thold_3 : in std_ulogic; + pc_fu_ary_nsl_thold_3 : in std_ulogic; + pc_fu_ary_slp_nsl_thold_3 : in std_ulogic; + pc_fu_sg_3 : in std_ulogic_vector(0 to 1); + pc_fu_fce_3 : in std_ulogic; + an_ac_lbist_en_dc : in std_ulogic; + an_ac_abist_mode_dc : in std_ulogic; + an_ac_lbist_ary_wrt_thru_dc : in std_ulogic; + + pc_fu_bolt_sl_thold_3 : in std_ulogic; + pc_fu_bo_enable_3 : in std_ulogic; + pc_fu_bo_unload : in std_ulogic; + pc_fu_bo_load : in std_ulogic; + pc_fu_bo_reset : in std_ulogic; + pc_fu_bo_shdata : in std_ulogic; + pc_fu_bo_select : in std_ulogic_vector(0 to 1); + fu_pc_bo_fail : out std_ulogic_vector(0 to 1); + fu_pc_bo_diagout : out std_ulogic_vector(0 to 1); + + nclk : in clk_logic; + vdd : inout power_logic; + gnd : inout power_logic; + + gptr_scan_in : in std_ulogic; + time_scan_in : in std_ulogic; + repr_scan_in : in std_ulogic; + abst_scan_in : in std_ulogic; + func_scan_in : in std_ulogic_vector(0 to 3); + ccfg_scan_in : in std_ulogic; + bcfg_scan_in : in std_ulogic; + dcfg_scan_in : in std_ulogic; + + gptr_scan_out : out std_ulogic; + time_scan_out : out std_ulogic; + repr_scan_out : out std_ulogic; + abst_scan_out : out std_ulogic; + func_scan_out : out std_ulogic_vector(0 to 3); + ccfg_scan_out : out std_ulogic; + bcfg_scan_out : out std_ulogic; + dcfg_scan_out : out std_ulogic; + + + bx_fu_rp_abst_scan_out : in std_ulogic; + bx_rp_abst_scan_out : out std_ulogic; + + rp_bx_abst_scan_in : in std_ulogic; + rp_fu_bx_abst_scan_in : out std_ulogic; + + rp_bx_func_scan_in : in std_ulogic_vector(0 to 1); + rp_fu_bx_func_scan_in : out std_ulogic_vector(0 to 1); + + bx_fu_rp_func_scan_out : in std_ulogic_vector(0 to 1); + bx_rp_func_scan_out : out std_ulogic_vector(0 to 1); + + bx_pc_err_inbox_ue_ifu : in std_ulogic; + bx_pc_err_outbox_ue_ifu : in std_ulogic; + bx_pc_err_inbox_ecc_ifu : in std_ulogic; + bx_pc_err_outbox_ecc_ifu : in std_ulogic; + pc_bx_bolt_sl_thold_3_ifu : in std_ulogic; + pc_bx_bo_enable_3_ifu : in std_ulogic; + pc_bx_bo_unload_ifu : in std_ulogic; + pc_bx_bo_repair_ifu : in std_ulogic; + pc_bx_bo_reset_ifu : in std_ulogic; + pc_bx_bo_shdata_ifu : in std_ulogic; + pc_bx_bo_select_ifu : in std_ulogic_vector(0 to 3); + bx_pc_bo_fail_ifu : in std_ulogic_vector(0 to 3); + bx_pc_bo_diagout_ifu : in std_ulogic_vector(0 to 3); + pc_bx_abist_di_0_ifu : in std_ulogic_vector(0 to 3); + pc_bx_abist_ena_dc_ifu : in std_ulogic; + pc_bx_abist_g8t1p_renb_0_ifu : in std_ulogic; + pc_bx_abist_g8t_bw_0_ifu : in std_ulogic; + pc_bx_abist_g8t_bw_1_ifu : in std_ulogic; + pc_bx_abist_g8t_dcomp_ifu : in std_ulogic_vector(0 to 3); + pc_bx_abist_g8t_wenb_ifu : in std_ulogic; + pc_bx_abist_raddr_0_ifu : in std_ulogic_vector(4 to 9); + pc_bx_abist_raw_dc_b_ifu : in std_ulogic; + pc_bx_abist_waddr_0_ifu : in std_ulogic_vector(4 to 9); + pc_bx_abist_wl64_comp_ena_ifu : in std_ulogic; + pc_bx_trace_bus_enable_ifu : in std_ulogic; + pc_bx_debug_mux1_ctrls_ifu : in std_ulogic_vector(0 to 15); + pc_bx_inj_inbox_ecc_ifu : in std_ulogic; + pc_bx_inj_outbox_ecc_ifu : in std_ulogic; + pc_bx_ccflush_dc_ifu : in std_ulogic; + pc_bx_sg_3_ifu : in std_ulogic; + pc_bx_func_sl_thold_3_ifu : in std_ulogic; + pc_bx_func_slp_sl_thold_3_ifu : in std_ulogic; + pc_bx_gptr_sl_thold_3_ifu : in std_ulogic; + pc_bx_time_sl_thold_3_ifu : in std_ulogic; + pc_bx_repr_sl_thold_3_ifu : in std_ulogic; + pc_bx_abst_sl_thold_3_ifu : in std_ulogic; + pc_bx_ary_nsl_thold_3_ifu : in std_ulogic; + pc_bx_ary_slp_nsl_thold_3_ifu : in std_ulogic; + + xu_pc_err_mcsr_summary_ifu : in std_ulogic_vector(0 to 3); + xu_pc_err_ierat_parity_ifu : in std_ulogic; + xu_pc_err_derat_parity_ifu : in std_ulogic; + xu_pc_err_tlb_parity_ifu : in std_ulogic; + xu_pc_err_tlb_lru_parity_ifu : in std_ulogic; + xu_pc_err_ierat_multihit_ifu : in std_ulogic; + xu_pc_err_derat_multihit_ifu : in std_ulogic; + xu_pc_err_tlb_multihit_ifu : in std_ulogic; + xu_pc_err_ext_mchk_ifu : in std_ulogic; + xu_pc_err_mchk_disabled_ifu : in std_ulogic; + xu_pc_err_ditc_overrun_ifu : in std_ulogic; + xu_pc_err_local_snoop_reject_ifu : in std_ulogic; + xu_pc_err_attention_instr_ifu : in std_ulogic_vector(0 to 3); + xu_pc_err_dcache_parity_ifu : in std_ulogic; + xu_pc_err_dcachedir_parity_ifu : in std_ulogic; + xu_pc_err_dcachedir_multihit_ifu : in std_ulogic; + xu_pc_err_debug_event_ifu : in std_ulogic_vector(0 to 3); + xu_pc_err_invld_reld_ifu : in std_ulogic; + xu_pc_err_l2intrf_ecc_ifu : in std_ulogic; + xu_pc_err_l2intrf_ue_ifu : in std_ulogic; + xu_pc_err_l2credit_overrun_ifu : in std_ulogic; + xu_pc_err_llbust_attempt_ifu : in std_ulogic_vector(0 to 3); + xu_pc_err_llbust_failed_ifu : in std_ulogic_vector(0 to 3); + xu_pc_err_nia_miscmpr_ifu : in std_ulogic_vector(0 to 3); + xu_pc_err_regfile_parity_ifu : in std_ulogic_vector(0 to 3); + xu_pc_err_regfile_ue_ifu : in std_ulogic_vector(0 to 3); + xu_pc_err_sprg_ecc_ifu : in std_ulogic_vector(0 to 3); + xu_pc_err_sprg_ue_ifu : in std_ulogic_vector(0 to 3); + xu_pc_err_wdt_reset_ifu : in std_ulogic_vector(0 to 3); + xu_pc_event_data_ifu : in std_ulogic_vector(0 to 7); + xu_pc_ram_data_ifu : in std_ulogic_vector(64-(2**regmode) to 63); + xu_pc_ram_done_ifu : in std_ulogic; + xu_pc_ram_interrupt_ifu : in std_ulogic; + xu_pc_running_ifu : in std_ulogic_vector(0 to 3); + xu_pc_spr_ccr0_pme_ifu : in std_ulogic_vector(0 to 1); + xu_pc_spr_ccr0_we_ifu : in std_ulogic_vector(0 to 3); + xu_pc_step_done_ifu : in std_ulogic_vector(0 to 3); + xu_pc_stop_dbg_event_ifu : in std_ulogic_vector(0 to 3); + xu_pc_lsu_event_data_ifu : in std_ulogic_vector(0 to 7); + pc_xu_bolt_sl_thold_3_ifu : in std_ulogic; + pc_xu_bo_enable_3_ifu : in std_ulogic; + pc_xu_bo_unload_ifu : in std_ulogic; + pc_xu_bo_load_ifu : in std_ulogic; + pc_xu_bo_repair_ifu : in std_ulogic; + pc_xu_bo_reset_ifu : in std_ulogic; + pc_xu_bo_shdata_ifu : in std_ulogic; + pc_xu_bo_select_ifu : in std_ulogic_vector(0 to 8); + xu_pc_bo_fail_ifu : in std_ulogic_vector(0 to 8); + xu_pc_bo_diagout_ifu : in std_ulogic_vector(0 to 8); + pc_xu_abist_dcomp_g6t_2r_ifu : in std_ulogic_vector(0 to 3); + pc_xu_abist_di_0_ifu : in std_ulogic_vector(0 to 3); + pc_xu_abist_di_1_ifu : in std_ulogic_vector(0 to 3); + pc_xu_abist_di_g6t_2r_ifu : in std_ulogic_vector(0 to 3); + pc_xu_abist_ena_dc_ifu : in std_ulogic; + pc_xu_abist_g6t_bw_ifu : in std_ulogic_vector(0 to 1); + pc_xu_abist_g6t_r_wb_ifu : in std_ulogic; + pc_xu_abist_g8t1p_renb_0_ifu : in std_ulogic; + pc_xu_abist_g8t_bw_0_ifu : in std_ulogic; + pc_xu_abist_g8t_bw_1_ifu : in std_ulogic; + pc_xu_abist_g8t_dcomp_ifu : in std_ulogic_vector(0 to 3); + pc_xu_abist_g8t_wenb_ifu : in std_ulogic; + pc_xu_abist_grf_renb_0_ifu : in std_ulogic; + pc_xu_abist_grf_renb_1_ifu : in std_ulogic; + pc_xu_abist_grf_wenb_0_ifu : in std_ulogic; + pc_xu_abist_grf_wenb_1_ifu : in std_ulogic; + pc_xu_abist_raddr_0_ifu : in std_ulogic_vector(0 to 9); + pc_xu_abist_raddr_1_ifu : in std_ulogic_vector(0 to 9); + pc_xu_abist_raw_dc_b_ifu : in std_ulogic; + pc_xu_abist_waddr_0_ifu : in std_ulogic_vector(0 to 9); + pc_xu_abist_waddr_1_ifu : in std_ulogic_vector(0 to 9); + pc_xu_abist_wl144_comp_ena_ifu : in std_ulogic; + pc_xu_abist_wl32_comp_ena_ifu : in std_ulogic; + pc_xu_abist_wl512_comp_ena_ifu : in std_ulogic; + pc_xu_event_mux_ctrls_ifu : in std_ulogic_vector(0 to 47); + pc_xu_lsu_event_mux_ctrls_ifu : in std_ulogic_vector(0 to 47); + pc_xu_event_bus_enable_ifu : in std_ulogic; + pc_xu_abst_sl_thold_3_ifu : in std_ulogic; + pc_xu_abst_slp_sl_thold_3_ifu : in std_ulogic; + pc_xu_regf_sl_thold_3_ifu : in std_ulogic; + pc_xu_regf_slp_sl_thold_3_ifu : in std_ulogic; + pc_xu_ary_nsl_thold_3_ifu : in std_ulogic; + pc_xu_ary_slp_nsl_thold_3_ifu : in std_ulogic; + pc_xu_cache_par_err_event_ifu : in std_ulogic; + pc_xu_ccflush_dc_ifu : in std_ulogic; + pc_xu_cfg_sl_thold_3_ifu : in std_ulogic; + pc_xu_cfg_slp_sl_thold_3_ifu : in std_ulogic; + pc_xu_dbg_action_ifu : in std_ulogic_vector(0 to 11); + pc_xu_debug_mux1_ctrls_ifu : in std_ulogic_vector(0 to 15); + pc_xu_debug_mux2_ctrls_ifu : in std_ulogic_vector(0 to 15); + pc_xu_debug_mux3_ctrls_ifu : in std_ulogic_vector(0 to 15); + pc_xu_debug_mux4_ctrls_ifu : in std_ulogic_vector(0 to 15); + pc_xu_decrem_dis_on_stop_ifu : in std_ulogic; + pc_xu_event_count_mode_ifu : in std_ulogic_vector(0 to 2); + pc_xu_extirpts_dis_on_stop_ifu : in std_ulogic; + pc_xu_fce_3_ifu : in std_ulogic_vector(0 to 1); + pc_xu_force_ude_ifu : in std_ulogic_vector(0 to 3); + pc_xu_func_nsl_thold_3_ifu : in std_ulogic; + pc_xu_func_sl_thold_3_ifu : in std_ulogic_vector(0 to 4); + pc_xu_func_slp_nsl_thold_3_ifu : in std_ulogic; + pc_xu_func_slp_sl_thold_3_ifu : in std_ulogic_vector(0 to 4); + pc_xu_gptr_sl_thold_3_ifu : in std_ulogic; + pc_xu_init_reset_ifu : in std_ulogic; + pc_xu_inj_dcache_parity_ifu : in std_ulogic; + pc_xu_inj_dcachedir_parity_ifu : in std_ulogic; + pc_xu_inj_llbust_attempt_ifu : in std_ulogic_vector(0 to 3); + pc_xu_inj_llbust_failed_ifu : in std_ulogic_vector(0 to 3); + pc_xu_inj_sprg_ecc_ifu : in std_ulogic_vector(0 to 3); + pc_xu_inj_regfile_parity_ifu : in std_ulogic_vector(0 to 3); + pc_xu_inj_wdt_reset_ifu : in std_ulogic_vector(0 to 3); + pc_xu_inj_dcachedir_multihit_ifu : in std_ulogic; + pc_xu_instr_trace_mode_ifu : in std_ulogic; + pc_xu_instr_trace_tid_ifu : in std_ulogic_vector(0 to 1); + pc_xu_msrovride_enab_ifu : in std_ulogic; + pc_xu_msrovride_gs_ifu : in std_ulogic; + pc_xu_msrovride_pr_ifu : in std_ulogic; + pc_xu_ram_execute_ifu : in std_ulogic; + pc_xu_ram_flush_thread_ifu : in std_ulogic; + pc_xu_ram_mode_ifu : in std_ulogic; + pc_xu_ram_thread_ifu : in std_ulogic_vector(0 to 1); + pc_xu_repr_sl_thold_3_ifu : in std_ulogic; + pc_xu_reset_1_cmplt_ifu : in std_ulogic; + pc_xu_reset_2_cmplt_ifu : in std_ulogic; + pc_xu_reset_3_cmplt_ifu : in std_ulogic; + pc_xu_reset_wd_cmplt_ifu : in std_ulogic; + pc_xu_sg_3_ifu : in std_ulogic_vector(0 to 4); + pc_xu_step_ifu : in std_ulogic_vector(0 to 3); + pc_xu_stop_ifu : in std_ulogic_vector(0 to 3); + pc_xu_time_sl_thold_3_ifu : in std_ulogic; + pc_xu_timebase_dis_on_stop_ifu : in std_ulogic; + pc_xu_trace_bus_enable_ifu : in std_ulogic; + + bx_pc_err_inbox_ue_ofu : out std_ulogic; + bx_pc_err_outbox_ue_ofu : out std_ulogic; + bx_pc_err_inbox_ecc_ofu : out std_ulogic; + bx_pc_err_outbox_ecc_ofu : out std_ulogic; + pc_bx_bolt_sl_thold_3_ofu : out std_ulogic; + pc_bx_bo_enable_3_ofu : out std_ulogic; + pc_bx_bo_unload_ofu : out std_ulogic; + pc_bx_bo_repair_ofu : out std_ulogic; + pc_bx_bo_reset_ofu : out std_ulogic; + pc_bx_bo_shdata_ofu : out std_ulogic; + pc_bx_bo_select_ofu : out std_ulogic_vector(0 to 3); + bx_pc_bo_fail_ofu : out std_ulogic_vector(0 to 3); + bx_pc_bo_diagout_ofu : out std_ulogic_vector(0 to 3); + pc_bx_abist_di_0_ofu : out std_ulogic_vector(0 to 3); + pc_bx_abist_ena_dc_ofu : out std_ulogic; + pc_bx_abist_g8t1p_renb_0_ofu : out std_ulogic; + pc_bx_abist_g8t_bw_0_ofu : out std_ulogic; + pc_bx_abist_g8t_bw_1_ofu : out std_ulogic; + pc_bx_abist_g8t_dcomp_ofu : out std_ulogic_vector(0 to 3); + pc_bx_abist_g8t_wenb_ofu : out std_ulogic; + pc_bx_abist_raddr_0_ofu : out std_ulogic_vector(4 to 9); + pc_bx_abist_raw_dc_b_ofu : out std_ulogic; + pc_bx_abist_waddr_0_ofu : out std_ulogic_vector(4 to 9); + pc_bx_abist_wl64_comp_ena_ofu : out std_ulogic; + pc_bx_trace_bus_enable_ofu : out std_ulogic; + pc_bx_debug_mux1_ctrls_ofu : out std_ulogic_vector(0 to 15); + pc_bx_inj_inbox_ecc_ofu : out std_ulogic; + pc_bx_inj_outbox_ecc_ofu : out std_ulogic; + pc_bx_ccflush_dc_ofu : out std_ulogic; + pc_bx_sg_3_ofu : out std_ulogic; + pc_bx_func_sl_thold_3_ofu : out std_ulogic; + pc_bx_func_slp_sl_thold_3_ofu : out std_ulogic; + pc_bx_gptr_sl_thold_3_ofu : out std_ulogic; + pc_bx_time_sl_thold_3_ofu : out std_ulogic; + pc_bx_repr_sl_thold_3_ofu : out std_ulogic; + pc_bx_abst_sl_thold_3_ofu : out std_ulogic; + pc_bx_ary_nsl_thold_3_ofu : out std_ulogic; + pc_bx_ary_slp_nsl_thold_3_ofu : out std_ulogic; + + xu_pc_err_mcsr_summary_ofu : out std_ulogic_vector(0 to 3); + xu_pc_err_ierat_parity_ofu : out std_ulogic; + xu_pc_err_derat_parity_ofu : out std_ulogic; + xu_pc_err_tlb_parity_ofu : out std_ulogic; + xu_pc_err_tlb_lru_parity_ofu : out std_ulogic; + xu_pc_err_ierat_multihit_ofu : out std_ulogic; + xu_pc_err_derat_multihit_ofu : out std_ulogic; + xu_pc_err_tlb_multihit_ofu : out std_ulogic; + xu_pc_err_ext_mchk_ofu : out std_ulogic; + xu_pc_err_mchk_disabled_ofu : out std_ulogic; + xu_pc_err_ditc_overrun_ofu : out std_ulogic; + xu_pc_err_local_snoop_reject_ofu : out std_ulogic; + xu_pc_err_attention_instr_ofu : out std_ulogic_vector(0 to 3); + xu_pc_err_dcache_parity_ofu : out std_ulogic; + xu_pc_err_dcachedir_parity_ofu : out std_ulogic; + xu_pc_err_dcachedir_multihit_ofu : out std_ulogic; + xu_pc_err_debug_event_ofu : out std_ulogic_vector(0 to 3); + xu_pc_err_invld_reld_ofu : out std_ulogic; + xu_pc_err_l2intrf_ecc_ofu : out std_ulogic; + xu_pc_err_l2intrf_ue_ofu : out std_ulogic; + xu_pc_err_l2credit_overrun_ofu : out std_ulogic; + xu_pc_err_llbust_attempt_ofu : out std_ulogic_vector(0 to 3); + xu_pc_err_llbust_failed_ofu : out std_ulogic_vector(0 to 3); + xu_pc_err_nia_miscmpr_ofu : out std_ulogic_vector(0 to 3); + xu_pc_err_regfile_parity_ofu : out std_ulogic_vector(0 to 3); + xu_pc_err_regfile_ue_ofu : out std_ulogic_vector(0 to 3); + xu_pc_err_sprg_ecc_ofu : out std_ulogic_vector(0 to 3); + xu_pc_err_sprg_ue_ofu : out std_ulogic_vector(0 to 3); + xu_pc_err_wdt_reset_ofu : out std_ulogic_vector(0 to 3); + xu_pc_event_data_ofu : out std_ulogic_vector(0 to 7); + xu_pc_ram_data_ofu : out std_ulogic_vector(64-(2**regmode) to 63); + xu_pc_ram_done_ofu : out std_ulogic; + xu_pc_ram_interrupt_ofu : out std_ulogic; + xu_pc_running_ofu : out std_ulogic_vector(0 to 3); + xu_pc_spr_ccr0_pme_ofu : out std_ulogic_vector(0 to 1); + xu_pc_spr_ccr0_we_ofu : out std_ulogic_vector(0 to 3); + xu_pc_step_done_ofu : out std_ulogic_vector(0 to 3); + xu_pc_stop_dbg_event_ofu : out std_ulogic_vector(0 to 3); + xu_pc_lsu_event_data_ofu : out std_ulogic_vector(0 to 7); + pc_xu_bolt_sl_thold_3_ofu : out std_ulogic; + pc_xu_bo_enable_3_ofu : out std_ulogic; + pc_xu_bo_unload_ofu : out std_ulogic; + pc_xu_bo_load_ofu : out std_ulogic; + pc_xu_bo_repair_ofu : out std_ulogic; + pc_xu_bo_reset_ofu : out std_ulogic; + pc_xu_bo_shdata_ofu : out std_ulogic; + pc_xu_bo_select_ofu : out std_ulogic_vector(0 to 8); + xu_pc_bo_fail_ofu : out std_ulogic_vector(0 to 8); + xu_pc_bo_diagout_ofu : out std_ulogic_vector(0 to 8); + pc_xu_abist_dcomp_g6t_2r_ofu : out std_ulogic_vector(0 to 3); + pc_xu_abist_di_0_ofu : out std_ulogic_vector(0 to 3); + pc_xu_abist_di_1_ofu : out std_ulogic_vector(0 to 3); + pc_xu_abist_di_g6t_2r_ofu : out std_ulogic_vector(0 to 3); + pc_xu_abist_ena_dc_ofu : out std_ulogic; + pc_xu_abist_g6t_bw_ofu : out std_ulogic_vector(0 to 1); + pc_xu_abist_g6t_r_wb_ofu : out std_ulogic; + pc_xu_abist_g8t1p_renb_0_ofu : out std_ulogic; + pc_xu_abist_g8t_bw_0_ofu : out std_ulogic; + pc_xu_abist_g8t_bw_1_ofu : out std_ulogic; + pc_xu_abist_g8t_dcomp_ofu : out std_ulogic_vector(0 to 3); + pc_xu_abist_g8t_wenb_ofu : out std_ulogic; + pc_xu_abist_grf_renb_0_ofu : out std_ulogic; + pc_xu_abist_grf_renb_1_ofu : out std_ulogic; + pc_xu_abist_grf_wenb_0_ofu : out std_ulogic; + pc_xu_abist_grf_wenb_1_ofu : out std_ulogic; + pc_xu_abist_raddr_0_ofu : out std_ulogic_vector(0 to 9); + pc_xu_abist_raddr_1_ofu : out std_ulogic_vector(0 to 9); + pc_xu_abist_raw_dc_b_ofu : out std_ulogic; + pc_xu_abist_waddr_0_ofu : out std_ulogic_vector(0 to 9); + pc_xu_abist_waddr_1_ofu : out std_ulogic_vector(0 to 9); + pc_xu_abist_wl144_comp_ena_ofu : out std_ulogic; + pc_xu_abist_wl32_comp_ena_ofu : out std_ulogic; + pc_xu_abist_wl512_comp_ena_ofu : out std_ulogic; + pc_xu_event_mux_ctrls_ofu : out std_ulogic_vector(0 to 47); + pc_xu_lsu_event_mux_ctrls_ofu : out std_ulogic_vector(0 to 47); + pc_xu_event_bus_enable_ofu : out std_ulogic; + pc_xu_abst_sl_thold_3_ofu : out std_ulogic; + pc_xu_abst_slp_sl_thold_3_ofu : out std_ulogic; + pc_xu_regf_sl_thold_3_ofu : out std_ulogic; + pc_xu_regf_slp_sl_thold_3_ofu : out std_ulogic; + pc_xu_ary_nsl_thold_3_ofu : out std_ulogic; + pc_xu_ary_slp_nsl_thold_3_ofu : out std_ulogic; + pc_xu_cache_par_err_event_ofu : out std_ulogic; + pc_xu_ccflush_dc_ofu : out std_ulogic; + pc_xu_cfg_sl_thold_3_ofu : out std_ulogic; + pc_xu_cfg_slp_sl_thold_3_ofu : out std_ulogic; + pc_xu_dbg_action_ofu : out std_ulogic_vector(0 to 11); + pc_xu_debug_mux1_ctrls_ofu : out std_ulogic_vector(0 to 15); + pc_xu_debug_mux2_ctrls_ofu : out std_ulogic_vector(0 to 15); + pc_xu_debug_mux3_ctrls_ofu : out std_ulogic_vector(0 to 15); + pc_xu_debug_mux4_ctrls_ofu : out std_ulogic_vector(0 to 15); + pc_xu_decrem_dis_on_stop_ofu : out std_ulogic; + pc_xu_event_count_mode_ofu : out std_ulogic_vector(0 to 2); + pc_xu_extirpts_dis_on_stop_ofu : out std_ulogic; + pc_xu_fce_3_ofu : out std_ulogic_vector(0 to 1); + pc_xu_force_ude_ofu : out std_ulogic_vector(0 to 3); + pc_xu_func_nsl_thold_3_ofu : out std_ulogic; + pc_xu_func_sl_thold_3_ofu : out std_ulogic_vector(0 to 4); + pc_xu_func_slp_nsl_thold_3_ofu : out std_ulogic; + pc_xu_func_slp_sl_thold_3_ofu : out std_ulogic_vector(0 to 4); + pc_xu_gptr_sl_thold_3_ofu : out std_ulogic; + pc_xu_init_reset_ofu : out std_ulogic; + pc_xu_inj_dcache_parity_ofu : out std_ulogic; + pc_xu_inj_dcachedir_parity_ofu : out std_ulogic; + pc_xu_inj_llbust_attempt_ofu : out std_ulogic_vector(0 to 3); + pc_xu_inj_llbust_failed_ofu : out std_ulogic_vector(0 to 3); + pc_xu_inj_sprg_ecc_ofu : out std_ulogic_vector(0 to 3); + pc_xu_inj_regfile_parity_ofu : out std_ulogic_vector(0 to 3); + pc_xu_inj_wdt_reset_ofu : out std_ulogic_vector(0 to 3); + pc_xu_inj_dcachedir_multihit_ofu : out std_ulogic; + pc_xu_instr_trace_mode_ofu : out std_ulogic; + pc_xu_instr_trace_tid_ofu : out std_ulogic_vector(0 to 1); + pc_xu_msrovride_enab_ofu : out std_ulogic; + pc_xu_msrovride_gs_ofu : out std_ulogic; + pc_xu_msrovride_pr_ofu : out std_ulogic; + pc_xu_ram_execute_ofu : out std_ulogic; + pc_xu_ram_flush_thread_ofu : out std_ulogic; + pc_xu_ram_mode_ofu : out std_ulogic; + pc_xu_ram_thread_ofu : out std_ulogic_vector(0 to 1); + pc_xu_repr_sl_thold_3_ofu : out std_ulogic; + pc_xu_reset_1_cmplt_ofu : out std_ulogic; + pc_xu_reset_2_cmplt_ofu : out std_ulogic; + pc_xu_reset_3_cmplt_ofu : out std_ulogic; + pc_xu_reset_wd_cmplt_ofu : out std_ulogic; + pc_xu_sg_3_ofu : out std_ulogic_vector(0 to 4); + pc_xu_step_ofu : out std_ulogic_vector(0 to 3); + pc_xu_stop_ofu : out std_ulogic_vector(0 to 3); + pc_xu_time_sl_thold_3_ofu : out std_ulogic; + pc_xu_timebase_dis_on_stop_ofu : out std_ulogic; + pc_xu_trace_bus_enable_ofu : out std_ulogic; + an_ac_scan_dis_dc_b_ofu : out std_ulogic; + an_ac_scan_diag_dc_ofu : out std_ulogic; + xu_ex2_flush_ofu : out std_ulogic_vector(0 to 3); + xu_ex3_flush_ofu : out std_ulogic_vector(0 to 3); + xu_ex4_flush_ofu : out std_ulogic_vector(0 to 3); + xu_ex5_flush_ofu : out std_ulogic_vector(0 to 3); + an_ac_lbist_ary_wrt_thru_dc_ofu : out std_ulogic; + + iu_fu_rf0_instr_v : in std_ulogic; + iu_fu_rf0_instr : in std_ulogic_vector(0 to 31); + iu_fu_rf0_fra_v : in std_ulogic; + iu_fu_rf0_frb_v : in std_ulogic; + iu_fu_rf0_frc_v : in std_ulogic; + iu_fu_rf0_tid : in std_ulogic_vector(0 to 1); + iu_fu_rf0_fra : in std_ulogic_vector(0 to 6); + iu_fu_rf0_frb : in std_ulogic_vector(0 to 6); + iu_fu_rf0_frc : in std_ulogic_vector(0 to 6); + iu_fu_rf0_frt : in std_ulogic_vector(0 to 6); + iu_fu_rf0_ifar : in std_ulogic_vector(62-eff_ifar to 61); + iu_fu_rf0_str_val : in std_ulogic; + iu_fu_rf0_ldst_val : in std_ulogic; + iu_fu_rf0_ldst_tid : in std_ulogic_vector(0 to 1); + iu_fu_rf0_ldst_tag : in std_ulogic_vector(0 to 8); + iu_fu_rf0_bypsel : in std_ulogic_vector(0 to 5); + iu_fu_rf0_instr_match : in std_ulogic; + iu_fu_rf0_is_ucode : in std_ulogic; + iu_fu_rf0_ucfmul : in std_ulogic; + iu_fu_is2_tid_decode : in std_ulogic_vector(0 to 3); + iu_fu_ex2_n_flush : in std_ulogic_vector(0 to 3); + xu_is2_flush : in std_ulogic_vector(0 to 3); + xu_rf0_flush : in std_ulogic_vector(0 to 3); + xu_rf1_flush : in std_ulogic_vector(0 to 3); + xu_ex1_flush : in std_ulogic_vector(0 to 3); + xu_ex2_flush : in std_ulogic_vector(0 to 3); + xu_ex3_flush : in std_ulogic_vector(0 to 3); + xu_ex4_flush : in std_ulogic_vector(0 to 3); + xu_ex5_flush : in std_ulogic_vector(0 to 3); + xu_fu_ex3_eff_addr : in std_ulogic_vector(59 to 63); + fu_xu_ex2_ifar_val : out std_ulogic_vector(0 to 3); + fu_xu_ex2_ifar_issued : out std_ulogic_vector(0 to 3); + fu_xu_ex1_ifar : out std_ulogic_vector(62-eff_ifar to 61); + fu_xu_ex3_n_flush : out std_ulogic_vector(0 to 3); + fu_xu_ex3_np1_flush : out std_ulogic_vector(0 to 3); + fu_xu_ex3_flush2ucode : out std_ulogic_vector(0 to 3); + fu_xu_ex2_instr_type : out std_ulogic_vector(0 to 11); + fu_xu_ex2_instr_match : out std_ulogic_vector(0 to 3); + fu_xu_ex2_is_ucode : out std_ulogic_vector(0 to 3); + fu_xu_ex3_trap : out std_ulogic_vector(0 to 3); + fu_xu_ex3_ap_int_req : out std_ulogic_vector(0 to 3); + slowspr_val_in : in std_ulogic; + slowspr_rw_in : in std_ulogic; + slowspr_etid_in : in std_ulogic_vector(0 to 1); + slowspr_addr_in : in std_ulogic_vector(0 to 9); + slowspr_data_in : in std_ulogic_vector(64-(2**regmode) to 63); + slowspr_done_in : in std_ulogic; + slowspr_val_out : out std_ulogic; + slowspr_rw_out : out std_ulogic; + slowspr_etid_out : out std_ulogic_vector(0 to 1); + slowspr_addr_out : out std_ulogic_vector(0 to 9); + slowspr_data_out : out std_ulogic_vector(64-(2**regmode) to 63); + slowspr_done_out : out std_ulogic; + pc_fu_ram_mode : in std_ulogic; + pc_fu_ram_thread : in std_ulogic_vector(0 to 1); + fu_pc_ram_done : out std_ulogic; + fu_pc_ram_data : out std_ulogic_vector(0 to 63); + pc_fu_trace_bus_enable : in std_ulogic; + pc_fu_event_bus_enable : in std_ulogic; + pc_fu_instr_trace_mode : in std_ulogic; + pc_fu_instr_trace_tid : in std_ulogic_vector(0 to 1); + pc_fu_debug_mux_ctrls : in std_ulogic_vector(0 to 15); + pc_fu_event_count_mode : in std_ulogic_vector(0 to 2); + pc_fu_event_mux_ctrls : in std_ulogic_vector(0 to 31); + debug_data_in : in std_ulogic_vector(0 to 87); + debug_data_out : out std_ulogic_vector(0 to 87); + trace_triggers_in : in std_ulogic_vector(0 to 11); + trace_triggers_out : out std_ulogic_vector(0 to 11); + fu_pc_event_data : out std_ulogic_vector(0 to 7); + pc_fu_abist_di_0 : in std_ulogic_vector(0 to 3); + pc_fu_abist_di_1 : in std_ulogic_vector(0 to 3); + pc_fu_abist_ena_dc : in std_ulogic; + pc_fu_abist_grf_renb_0 : in std_ulogic; + pc_fu_abist_grf_renb_1 : in std_ulogic; + pc_fu_abist_grf_wenb_0 : in std_ulogic; + pc_fu_abist_grf_wenb_1 : in std_ulogic; + pc_fu_abist_raddr_0 : in std_ulogic_vector(0 to 9); + pc_fu_abist_raddr_1 : in std_ulogic_vector(0 to 9); + pc_fu_abist_raw_dc_b : in std_ulogic; + pc_fu_abist_waddr_0 : in std_ulogic_vector(0 to 9); + pc_fu_abist_waddr_1 : in std_ulogic_vector(0 to 9); + pc_fu_abist_wl144_comp_ena : in std_ulogic; + fu_pc_err_regfile_parity : out std_ulogic_vector(0 to 3); + fu_pc_err_regfile_ue : out std_ulogic_vector(0 to 3); + pc_fu_inj_regfile_parity : in std_ulogic_vector(0 to 3); + fu_xu_ex3_regfile_err_det : out std_ulogic_vector(0 to 3); + xu_fu_regfile_seq_beg : in std_ulogic; + fu_xu_regfile_seq_end : out std_ulogic; + + fu_xu_ex2_store_data : out std_ulogic_vector(0 to 63); + fu_xu_ex2_store_data_val : out std_ulogic; + xu_fu_ex5_load_val : in std_ulogic_vector(0 to 3); + xu_fu_ex5_load_tag : in std_ulogic_vector(0 to 8); + xu_fu_ex5_load_le : in std_ulogic; + xu_fu_ex5_reload_val : in std_ulogic; + xu_fu_ex6_load_data : in std_ulogic_vector(192 to 255); + fu_xu_rf1_act : out std_ulogic_vector(0 to 3); + fu_xu_ex2_async_block : out std_ulogic_vector(0 to 3); + xu_fu_msr_fp : in std_ulogic_vector(0 to 3); + xu_fu_msr_pr : in std_ulogic_vector(0 to 3); + xu_fu_msr_gs : in std_ulogic_vector(0 to 3); + fu_iu_uc_special : out std_ulogic_vector(0 to 3); + fu_xu_ex4_cr_val : out std_ulogic_vector(0 to 3); + fu_xu_ex4_cr_noflush : out std_ulogic_vector(0 to 3); + fu_xu_ex4_cr_bf : out std_ulogic_vector(0 to 2); + fu_xu_ex4_cr : out std_ulogic_vector(0 to 3) +); + -- synopsys translate_off + -- synopsys translate_on + +end fuq; + +architecture fuq of fuq is + + + + + +signal f_dcd_msr_fp_act : std_ulogic; + +signal f_dcd_ex6_frt_addr : std_ulogic_vector(0 to 5); +signal f_dcd_ex6_frt_tid : std_ulogic_vector(0 to 1); +signal f_dcd_ex6_frt_wen : std_ulogic; +signal f_dcd_ex5_frt_tid : std_ulogic_vector(0 to 1); + + +signal f_dcd_rf1_mad_act : std_ulogic; +signal f_dcd_rf1_sto_act : std_ulogic; +signal f_dcd_ex6_cancel : std_ulogic; +signal f_dcd_rf1_bypsel_a_res0 : std_ulogic; +signal f_dcd_rf1_bypsel_a_load0 : std_ulogic; +signal f_dcd_rf1_bypsel_b_res0 : std_ulogic; +signal f_dcd_rf1_bypsel_b_load0 : std_ulogic; +signal f_dcd_rf1_bypsel_c_res0 : std_ulogic; +signal f_dcd_rf1_bypsel_c_load0 : std_ulogic; +signal f_dcd_rf1_bypsel_a_res1 : std_ulogic; +signal f_dcd_rf1_bypsel_a_load1 : std_ulogic; +signal f_dcd_rf1_bypsel_b_res1 : std_ulogic; +signal f_dcd_rf1_bypsel_b_load1 : std_ulogic; +signal f_dcd_rf1_bypsel_c_res1 : std_ulogic; +signal f_dcd_rf1_bypsel_c_load1 : std_ulogic; +signal f_dcd_rf0_bypsel_a_res1 : std_ulogic; +signal f_dcd_rf0_bypsel_a_load1 : std_ulogic; +signal f_dcd_rf0_bypsel_b_res1 : std_ulogic; +signal f_dcd_rf0_bypsel_b_load1 : std_ulogic; +signal f_dcd_rf0_bypsel_c_res1 : std_ulogic; +signal f_dcd_rf0_bypsel_c_load1 : std_ulogic; +signal f_dcd_rf0_bypsel_s_res1 : std_ulogic; +signal f_dcd_rf0_bypsel_s_load1 : std_ulogic; + +signal f_fpr_ex7_load_sign : std_ulogic; +signal f_fpr_ex7_load_expo : std_ulogic_vector(3 to 13); +signal f_fpr_ex7_load_frac : std_ulogic_vector(0 to 52); +signal f_fpr_ex7_load_addr : std_ulogic_vector(0 to 7); +signal f_fpr_ex7_load_v : std_ulogic; +signal f_fpr_rf1_a_sign : std_ulogic; +signal f_fpr_rf1_a_expo : std_ulogic_vector(1 to 13) ; +signal f_fpr_rf1_a_frac : std_ulogic_vector(0 to 52) ; +signal f_fpr_rf1_c_sign : std_ulogic; +signal f_fpr_rf1_c_expo : std_ulogic_vector(1 to 13) ; +signal f_fpr_rf1_c_frac : std_ulogic_vector(0 to 52) ; +signal f_fpr_rf1_b_sign : std_ulogic; +signal f_fpr_rf1_b_expo : std_ulogic_vector(1 to 13) ; +signal f_fpr_rf1_b_frac : std_ulogic_vector(0 to 52) ; +signal f_fpr_ex7_frt_sign : std_ulogic; +signal f_fpr_ex7_frt_expo : std_ulogic_vector(1 to 13); +signal f_fpr_ex7_frt_frac : std_ulogic_vector(0 to 52); +signal f_fpr_ex8_load_sign : std_ulogic; +signal f_fpr_ex8_load_expo : std_ulogic_vector(3 to 13); +signal f_fpr_ex8_load_frac : std_ulogic_vector(0 to 52); +signal f_dcd_rf1_aop_valid : std_ulogic; +signal f_dcd_rf1_cop_valid : std_ulogic; +signal f_dcd_rf1_bop_valid : std_ulogic; +signal f_dcd_rf1_sp : std_ulogic; +signal f_dcd_rf1_emin_dp : std_ulogic; +signal f_dcd_rf1_emin_sp : std_ulogic; +signal f_dcd_rf1_force_pass_b : std_ulogic; +signal f_dcd_rf1_fsel_b : std_ulogic; +signal f_dcd_rf1_from_integer_b : std_ulogic; +signal f_dcd_rf1_to_integer_b : std_ulogic; +signal f_dcd_rf1_rnd_to_int_b : std_ulogic; +signal f_dcd_rf1_math_b : std_ulogic; +signal f_dcd_rf1_est_recip_b : std_ulogic; +signal f_dcd_rf1_est_rsqrt_b : std_ulogic; +signal f_dcd_rf1_move_b : std_ulogic; +signal f_dcd_rf1_prenorm_b : std_ulogic; +signal f_dcd_rf1_frsp_b : std_ulogic; +signal f_dcd_rf1_compare_b : std_ulogic; +signal f_dcd_rf1_ordered_b : std_ulogic; +signal f_dcd_rf1_div_beg : std_ulogic; +signal f_dcd_rf1_sqrt_beg : std_ulogic; +signal f_dcd_rf1_force_excp_dis : std_ulogic; +signal f_dcd_rf1_nj_deni : std_ulogic; +signal f_dcd_rf1_nj_deno : std_ulogic; +signal f_dcd_rf1_sp_conv_b : std_ulogic; +signal f_dcd_rf1_word_b : std_ulogic; +signal f_dcd_rf1_uns_b : std_ulogic; +signal f_dcd_rf1_sub_op_b : std_ulogic; +signal f_dcd_rf1_op_rnd_v_b : std_ulogic; +signal f_dcd_rf1_op_rnd_b : std_ulogic_vector(0 to 1); +signal f_dcd_rf1_inv_sign_b : std_ulogic; +signal f_dcd_rf1_sign_ctl_b : std_ulogic_vector(0 to 1); +signal f_dcd_rf1_sgncpy_b : std_ulogic; +signal f_dcd_rf1_fpscr_bit_data_b : std_ulogic_vector(0 to 3); +signal f_dcd_rf1_fpscr_bit_mask_b : std_ulogic_vector(0 to 3); +signal f_dcd_rf1_fpscr_nib_mask_b : std_ulogic_vector(0 to 8); +signal f_dcd_rf1_mv_to_scr_b : std_ulogic; +signal f_dcd_rf1_mv_from_scr_b : std_ulogic; +signal f_dcd_rf1_mtfsbx_b : std_ulogic; +signal f_dcd_rf1_mcrfs_b : std_ulogic; +signal f_dcd_rf1_mtfsf_b : std_ulogic; +signal f_dcd_rf1_mtfsfi_b : std_ulogic; +signal f_scr_ex7_cr_fld : std_ulogic_vector (0 to 3) ; +signal f_add_ex4_fpcc_iu : std_ulogic_vector (0 to 3) ; +signal f_rnd_ex6_res_expo : std_ulogic_vector (1 to 13) ; +signal f_rnd_ex6_res_frac : std_ulogic_vector (0 to 52) ; +signal f_rnd_ex6_res_sign : std_ulogic ; +signal f_dcd_rf1_thread_b : std_ulogic_vector(0 to 3) ; +signal f_dcd_rf1_sto_dp : std_ulogic ; +signal f_dcd_rf1_sto_sp : std_ulogic ; +signal f_dcd_rf1_sto_wd : std_ulogic ; +signal f_dcd_rf1_log2e_b : std_ulogic ; +signal f_dcd_rf1_pow2e_b : std_ulogic ; +signal f_dcd_rf1_ftdiv : std_ulogic ; +signal f_dcd_rf1_ftsqrt : std_ulogic ; +signal f_ex2_b_den_flush : std_ulogic ; +signal f_scr_ex7_fx_thread0 : std_ulogic_vector (0 to 3) ; +signal f_scr_ex7_fx_thread1 : std_ulogic_vector (0 to 3) ; +signal f_scr_ex7_fx_thread2 : std_ulogic_vector (0 to 3) ; +signal f_scr_ex7_fx_thread3 : std_ulogic_vector (0 to 3) ; +signal f_dcd_rf0_tid : std_ulogic_vector(0 to 1) ; +signal f_dcd_rf0_fra : std_ulogic_vector(0 to 5); +signal f_dcd_rf0_frb : std_ulogic_vector(0 to 5); +signal f_dcd_rf0_frc : std_ulogic_vector(0 to 5); +signal f_dcd_rf1_uc_ft_pos : std_ulogic; +signal f_dcd_rf1_uc_ft_neg : std_ulogic; +signal f_dcd_rf1_uc_fa_pos : std_ulogic; +signal f_dcd_rf1_uc_fc_pos : std_ulogic; +signal f_dcd_rf1_uc_fb_pos : std_ulogic; +signal f_dcd_rf1_uc_fc_hulp : std_ulogic; +signal f_dcd_rf1_uc_fc_0_5 : std_ulogic; +signal f_dcd_rf1_uc_fc_1_0 : std_ulogic; +signal f_dcd_rf1_uc_fc_1_minus : std_ulogic; +signal f_dcd_rf1_uc_fb_1_0 : std_ulogic; +signal f_dcd_rf1_uc_fb_0_75 : std_ulogic; +signal f_dcd_rf1_uc_fb_0_5 : std_ulogic; +signal f_dcd_ex2_uc_inc_lsb : std_ulogic; +signal f_dcd_ex2_uc_gs_v : std_ulogic; +signal f_dcd_ex2_uc_gs : std_ulogic_vector(0 to 1); +signal f_dcd_perr_sm_running : std_ulogic; +signal f_dcd_ex1_perr_force_c : std_ulogic; +signal f_dcd_ex1_perr_fsel_ovrd : std_ulogic; + +signal f_pic_ex5_fpr_wr_dis_b : std_ulogic ; +signal f_fpr_rf1_s_sign : std_ulogic ; +signal f_fpr_rf1_s_expo : std_ulogic_vector(1 to 11) ; +signal f_fpr_rf1_s_frac : std_ulogic_vector(0 to 52) ; + +signal f_mad_si : std_ulogic_vector(0 to 17) ; +signal f_mad_so : std_ulogic_vector(0 to 17) ; +signal f_dcd_si : std_ulogic; +signal f_dcd_so : std_ulogic; +signal f_fpr_si : std_ulogic; +signal f_fpr_so : std_ulogic; +signal f_sto_si : std_ulogic; +signal f_sto_so : std_ulogic; +signal gptr_scan_io : std_ulogic; + +signal time_sl_thold_1 : std_ulogic; +signal abst_sl_thold_1 : std_ulogic; +signal func_sl_thold_1 : std_ulogic_vector(0 to 1); +signal ary_nsl_thold_1 : std_ulogic; +signal cfg_sl_thold_1 : std_ulogic; +signal func_slp_sl_thold_1 : std_ulogic; +signal gptr_sl_thold_0 : std_ulogic; + +signal fce_1 : std_ulogic; +signal sg_1 : std_ulogic_vector(0 to 1); +signal clkoff_dc_b : std_ulogic; +signal act_dis : std_ulogic; +signal delay_lclkr_dc : std_ulogic_vector(0 to 9); +signal mpw1_dc_b : std_ulogic_vector(0 to 9); +signal mpw2_dc_b : std_ulogic_vector(0 to 1); + +signal fpu_enable : std_ulogic; + +signal f_mad_ex6_uc_sign :std_ulogic; +signal f_mad_ex6_uc_zero :std_ulogic; +signal f_mad_ex3_uc_special :std_ulogic; +signal f_mad_ex3_uc_vxsqrt :std_ulogic; +signal f_mad_ex3_uc_vxsnan :std_ulogic; +signal f_mad_ex3_uc_zx :std_ulogic; +signal f_mad_ex3_uc_vxidi :std_ulogic; +signal f_mad_ex3_uc_vxzdz :std_ulogic; +signal f_mad_ex3_uc_res_sign :std_ulogic; +signal f_mad_ex3_uc_round_mode :std_ulogic_vector(0 to 1); + signal f_dcd_rf1_uc_mid :std_ulogic; + signal f_dcd_rf1_uc_end :std_ulogic; + signal f_dcd_rf1_uc_special :std_ulogic; + signal f_dcd_ex2_uc_vxsnan :std_ulogic; + signal f_dcd_ex2_uc_zx :std_ulogic; + signal f_dcd_ex2_uc_vxidi :std_ulogic; + signal f_dcd_ex2_uc_vxzdz :std_ulogic; + signal f_dcd_ex2_uc_vxsqrt :std_ulogic; + signal f_fpr_ex1_a_par :std_ulogic_vector(0 to 7); + signal f_fpr_ex1_b_par :std_ulogic_vector(0 to 7); + signal f_fpr_ex1_c_par :std_ulogic_vector(0 to 7); + signal f_fpr_ex1_s_par :std_ulogic_vector(0 to 7); + signal f_fpr_ex1_s_expo_extra :std_Ulogic; + signal f_sto_ex2_s_parity_check :std_ulogic; + signal f_mad_ex2_a_parity_check :std_ulogic; + signal f_mad_ex2_c_parity_check :std_ulogic; + signal f_mad_ex2_b_parity_check :std_ulogic; + + signal f_dcd_ex5_flush_int : std_ulogic_vector(0 to 3); + signal scan_dis_dc_b :std_ulogic; + signal scan_diag_dc :std_ulogic; + + signal spare_unused : std_ulogic_vector(0 to 5); + +begin + + + + + + + scan_dis_dc_b <= an_ac_scan_dis_dc_b; + scan_diag_dc <= an_ac_scan_diag_dc; + + prv: entity work.fuq_perv(fuq_perv) + generic map( + expand_type => expand_type) + port map( + vdd => vdd , + gnd => gnd , + nclk => nclk , + pc_fu_sg_3 => pc_fu_sg_3 , + pc_fu_abst_sl_thold_3 => pc_fu_abst_sl_thold_3 , + pc_fu_func_sl_thold_3 => pc_fu_func_sl_thold_3 , + pc_fu_func_slp_sl_thold_3 => pc_fu_func_slp_sl_thold_3 , + pc_fu_gptr_sl_thold_3 => pc_fu_gptr_sl_thold_3 , + pc_fu_time_sl_thold_3 => pc_fu_time_sl_thold_3 , + pc_fu_ary_nsl_thold_3 => pc_fu_ary_nsl_thold_3 , + pc_fu_cfg_sl_thold_3 => pc_fu_cfg_sl_thold_3 , + pc_fu_repr_sl_thold_3 => pc_fu_repr_sl_thold_3 , + pc_fu_fce_3 => pc_fu_fce_3 , + tc_ac_ccflush_dc => pc_fu_ccflush_dc , + tc_ac_scan_diag_dc => scan_diag_dc , + abst_sl_thold_1 => abst_sl_thold_1 , + func_sl_thold_1 => func_sl_thold_1 , + time_sl_thold_1 => time_sl_thold_1 , + ary_nsl_thold_1 => ary_nsl_thold_1 , + cfg_sl_thold_1 => cfg_sl_thold_1 , + func_slp_sl_thold_1 => func_slp_sl_thold_1 , + gptr_sl_thold_0 => gptr_sl_thold_0 , + fce_1 => fce_1 , + sg_1 => sg_1 , + clkoff_dc_b => clkoff_dc_b , + act_dis => act_dis , + delay_lclkr_dc => delay_lclkr_dc , + mpw1_dc_b => mpw1_dc_b , + mpw2_dc_b => mpw2_dc_b , + repr_scan_in => repr_scan_in , + repr_scan_out => repr_scan_out , + gptr_scan_in => gptr_scan_in , + gptr_scan_out => gptr_scan_io ); + + + fpr: entity work.fuq_fpr(fuq_fpr) + generic map( + expand_type => expand_type) + port map( + nclk => nclk , + clkoff_b => clkoff_dc_b , + act_dis => act_dis , + flush => pc_fu_ccflush_dc , + delay_lclkra(0 to 1) => delay_lclkr_dc(0 to 1) , + delay_lclkrb(6 to 7) => delay_lclkr_dc(6 to 7) , + mpw1_ba(0 to 1) => mpw1_dc_b(0 to 1) , + mpw1_bb(6 to 7) => mpw1_dc_b(6 to 7) , + mpw2_b => mpw2_dc_b , + sg_1 => sg_1(1) , + abst_sl_thold_1 => abst_sl_thold_1 , + time_sl_thold_1 => time_sl_thold_1 , + ary_nsl_thold_1 => ary_nsl_thold_1 , + gptr_sl_thold_0 => gptr_sl_thold_0 , + fce_1 => fce_1 , + thold_1 => func_sl_thold_1(1) , + scan_dis_dc_b => scan_dis_dc_b , + scan_diag_dc => scan_diag_dc , + lbist_en_dc => an_ac_lbist_en_dc , + an_ac_abist_mode_dc => an_ac_abist_mode_dc , + an_ac_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc , + f_dcd_msr_fp_act => f_dcd_msr_fp_act , + + bx_fu_rp_abst_scan_out => bx_fu_rp_abst_scan_out , + bx_rp_abst_scan_out => bx_rp_abst_scan_out , + rp_bx_abst_scan_in => rp_bx_abst_scan_in , + rp_fu_bx_abst_scan_in => rp_fu_bx_abst_scan_in , + rp_bx_func_scan_in => rp_bx_func_scan_in , + rp_fu_bx_func_scan_in => rp_fu_bx_func_scan_in , + bx_fu_rp_func_scan_out => bx_fu_rp_func_scan_out , + bx_rp_func_scan_out => bx_rp_func_scan_out , + + pc_fu_bolt_sl_thold_3 => pc_fu_bolt_sl_thold_3 , + pc_fu_bo_enable_3 => pc_fu_bo_enable_3 , + pc_fu_bo_unload => pc_fu_bo_unload , + pc_fu_bo_load => pc_fu_bo_load , + pc_fu_bo_reset => pc_fu_bo_reset , + pc_fu_bo_shdata => pc_fu_bo_shdata , + pc_fu_bo_select => pc_fu_bo_select , + fu_pc_bo_fail => fu_pc_bo_fail , + fu_pc_bo_diagout => fu_pc_bo_diagout , + + iu_fu_rf0_fra_v => iu_fu_rf0_fra_v , + iu_fu_rf0_frb_v => iu_fu_rf0_frb_v , + iu_fu_rf0_frc_v => iu_fu_rf0_frc_v , + iu_fu_rf0_str_v => iu_fu_rf0_str_val , + f_dcd_perr_sm_running => f_dcd_perr_sm_running , + + f_fpr_si => f_fpr_si , + f_fpr_so => f_fpr_so , + f_fpr_ab_si => abst_scan_in , + f_fpr_ab_so => abst_scan_out , + time_scan_in => time_scan_in , + time_scan_out => time_scan_out , + gptr_scan_in => gptr_scan_io , + gptr_scan_out => gptr_scan_out , + vdd => vdd , + gnd => gnd , + pc_fu_abist_di_0 => pc_fu_abist_di_0 , + pc_fu_abist_di_1 => pc_fu_abist_di_1 , + pc_fu_abist_ena_dc => pc_fu_abist_ena_dc , + pc_fu_abist_grf_renb_0 => pc_fu_abist_grf_renb_0 , + pc_fu_abist_grf_renb_1 => pc_fu_abist_grf_renb_1 , + pc_fu_abist_grf_wenb_0 => pc_fu_abist_grf_wenb_0 , + pc_fu_abist_grf_wenb_1 => pc_fu_abist_grf_wenb_1 , + pc_fu_abist_raddr_0 => pc_fu_abist_raddr_0 , + pc_fu_abist_raddr_1 => pc_fu_abist_raddr_1 , + pc_fu_abist_raw_dc_b => pc_fu_abist_raw_dc_b , + pc_fu_abist_waddr_0 => pc_fu_abist_waddr_0 , + pc_fu_abist_waddr_1 => pc_fu_abist_waddr_1 , + pc_fu_abist_wl144_comp_ena => pc_fu_abist_wl144_comp_ena , + pc_fu_inj_regfile_parity => pc_fu_inj_regfile_parity , + f_dcd_rf0_tid => f_dcd_rf0_tid , + f_dcd_rf0_fra => f_dcd_rf0_fra , + f_dcd_rf0_frb => f_dcd_rf0_frb , + f_dcd_rf0_frc => f_dcd_rf0_frc , + iu_fu_rf0_ldst_tid => iu_fu_rf0_ldst_tid , + iu_fu_rf0_ldst_tag => iu_fu_rf0_ldst_tag , + f_dcd_rf0_bypsel_a_res1 => f_dcd_rf0_bypsel_a_res1 , + f_dcd_rf0_bypsel_a_load1 => f_dcd_rf0_bypsel_a_load1 , + f_dcd_rf0_bypsel_b_res1 => f_dcd_rf0_bypsel_b_res1 , + f_dcd_rf0_bypsel_b_load1 => f_dcd_rf0_bypsel_b_load1 , + f_dcd_rf0_bypsel_c_res1 => f_dcd_rf0_bypsel_c_res1 , + f_dcd_rf0_bypsel_c_load1 => f_dcd_rf0_bypsel_c_load1 , + f_dcd_rf0_bypsel_s_res1 => f_dcd_rf0_bypsel_s_res1 , + f_dcd_rf0_bypsel_s_load1 => f_dcd_rf0_bypsel_s_load1 , + f_dcd_ex6_frt_addr => f_dcd_ex6_frt_addr , + f_dcd_ex5_frt_tid => f_dcd_ex5_frt_tid , + f_dcd_ex6_frt_tid => f_dcd_ex6_frt_tid , + f_dcd_ex6_frt_wen => f_dcd_ex6_frt_wen , + f_rnd_ex6_res_expo => f_rnd_ex6_res_expo , + f_rnd_ex6_res_frac => f_rnd_ex6_res_frac , + f_rnd_ex6_res_sign => f_rnd_ex6_res_sign , + f_dcd_ex5_flush_int => f_dcd_ex5_flush_int , + xu_fu_ex5_load_tag => xu_fu_ex5_load_tag , + xu_fu_ex5_load_val => xu_fu_ex5_load_val , + xu_fu_ex6_load_data => xu_fu_ex6_load_data , + f_fpr_ex7_load_addr => f_fpr_ex7_load_addr , + f_fpr_ex7_load_v => f_fpr_ex7_load_v , + f_fpr_ex7_load_sign => f_fpr_ex7_load_sign , + f_fpr_ex7_load_expo => f_fpr_ex7_load_expo , + f_fpr_ex7_load_frac => f_fpr_ex7_load_frac , + f_fpr_rf1_s_sign => f_fpr_rf1_s_sign , + f_fpr_rf1_s_expo => f_fpr_rf1_s_expo , + f_fpr_rf1_s_frac => f_fpr_rf1_s_frac , + f_fpr_rf1_a_sign => f_fpr_rf1_a_sign , + f_fpr_rf1_a_expo => f_fpr_rf1_a_expo , + f_fpr_rf1_a_frac => f_fpr_rf1_a_frac , + f_fpr_rf1_c_sign => f_fpr_rf1_c_sign , + f_fpr_rf1_c_expo => f_fpr_rf1_c_expo , + f_fpr_rf1_c_frac => f_fpr_rf1_c_frac , + f_fpr_rf1_b_sign => f_fpr_rf1_b_sign , + f_fpr_rf1_b_expo => f_fpr_rf1_b_expo , + f_fpr_rf1_b_frac => f_fpr_rf1_b_frac , + f_fpr_ex1_s_expo_extra => f_fpr_ex1_s_expo_extra , + f_fpr_ex1_s_par => f_fpr_ex1_s_par , + f_fpr_ex1_a_par => f_fpr_ex1_a_par , + f_fpr_ex1_b_par => f_fpr_ex1_b_par , + f_fpr_ex1_c_par => f_fpr_ex1_c_par ); + + + + sto: entity work.fuq_sto(fuq_sto) + generic map( + expand_type => expand_type) + port map( + vdd => vdd , + gnd => gnd , + clkoff_b => clkoff_dc_b , + act_dis => act_dis , + flush => pc_fu_ccflush_dc , + delay_lclkr => delay_lclkr_dc(1 to 2) , + mpw1_b => mpw1_dc_b(1 to 2) , + mpw2_b => mpw2_dc_b(0 to 0) , + sg_1 => sg_1(1) , + thold_1 => func_sl_thold_1(1) , + fpu_enable => fpu_enable , + nclk => nclk , + f_sto_si => f_sto_si , + f_sto_so => f_sto_so , + f_dcd_rf1_sto_act => f_dcd_rf1_sto_act , + + f_fpr_ex1_s_expo_extra => f_fpr_ex1_s_expo_extra , + f_fpr_ex1_s_par => f_fpr_ex1_s_par , + f_sto_ex2_s_parity_check => f_sto_ex2_s_parity_check , + f_dcd_rf1_sto_dp => f_dcd_rf1_sto_dp , + f_dcd_rf1_sto_sp => f_dcd_rf1_sto_sp , + f_dcd_rf1_sto_wd => f_dcd_rf1_sto_wd , + f_byp_rf1_s_sign => f_fpr_rf1_s_sign , + f_byp_rf1_s_expo => f_fpr_rf1_s_expo , + f_byp_rf1_s_frac => f_fpr_rf1_s_frac , + f_sto_ex2_sto_data => fu_xu_ex2_store_data ); + + + + + + fpu_enable <= f_dcd_msr_fp_act; + + f_dcd_rf1_bypsel_a_res1 <= '0' ; + f_dcd_rf1_bypsel_a_load1 <= '0' ; + f_dcd_rf1_bypsel_b_res1 <= '0' ; + f_dcd_rf1_bypsel_b_load1 <= '0' ; + f_dcd_rf1_bypsel_c_res1 <= '0' ; + f_dcd_rf1_bypsel_c_load1 <= '0' ; + f_fpr_ex8_load_sign <= '0'; + f_fpr_ex8_load_expo(3 to 13) <= (others => '0'); + f_fpr_ex8_load_frac(0 to 52) <= (others => '0'); + + f_fpr_ex7_frt_sign <= '0' ; + f_fpr_ex7_frt_expo(1 to 13) <= (others => '0'); + f_fpr_ex7_frt_frac(0 to 52) <= (others => '0'); + + + mad: entity work.fuq_mad(fuq_mad) + generic map( + expand_type => expand_type) + port map( + f_dcd_ex6_cancel => f_dcd_ex6_cancel , + f_dcd_rf1_bypsel_a_res0 => f_dcd_rf1_bypsel_a_res0 , + f_dcd_rf1_bypsel_a_res1 => f_dcd_rf1_bypsel_a_res1 , + f_dcd_rf1_bypsel_a_load0 => f_dcd_rf1_bypsel_a_load0 , + f_dcd_rf1_bypsel_a_load1 => f_dcd_rf1_bypsel_a_load1 , + f_dcd_rf1_bypsel_b_res0 => f_dcd_rf1_bypsel_b_res0 , + f_dcd_rf1_bypsel_b_res1 => f_dcd_rf1_bypsel_b_res1 , + f_dcd_rf1_bypsel_b_load0 => f_dcd_rf1_bypsel_b_load0 , + f_dcd_rf1_bypsel_b_load1 => f_dcd_rf1_bypsel_b_load1 , + f_dcd_rf1_bypsel_c_res0 => f_dcd_rf1_bypsel_c_res0 , + f_dcd_rf1_bypsel_c_res1 => f_dcd_rf1_bypsel_c_res1 , + f_dcd_rf1_bypsel_c_load0 => f_dcd_rf1_bypsel_c_load0 , + f_dcd_rf1_bypsel_c_load1 => f_dcd_rf1_bypsel_c_load1 , + f_dcd_rf1_force_excp_dis => f_dcd_rf1_force_excp_dis , + f_fpr_ex7_frt_sign => f_fpr_ex7_frt_sign , + f_fpr_ex7_frt_expo(1 to 13) => f_fpr_ex7_frt_expo(1 to 13) , + f_fpr_ex7_frt_frac(0 to 52) => f_fpr_ex7_frt_frac(0 to 52) , + f_fpr_ex7_load_sign => f_fpr_ex8_load_sign , + f_fpr_ex7_load_expo(3 to 13) => f_fpr_ex8_load_expo(3 to 13) , + f_fpr_ex7_load_frac(0 to 52) => f_fpr_ex8_load_frac(0 to 52) , + f_fpr_ex6_load_sign => f_fpr_ex7_load_sign , + f_fpr_ex6_load_expo => f_fpr_ex7_load_expo , + f_fpr_ex6_load_frac => f_fpr_ex7_load_frac , + f_fpr_rf1_a_sign => f_fpr_rf1_a_sign , + f_fpr_rf1_a_expo => f_fpr_rf1_a_expo , + f_fpr_rf1_a_frac => f_fpr_rf1_a_frac , + f_fpr_rf1_c_sign => f_fpr_rf1_c_sign , + f_fpr_rf1_c_expo => f_fpr_rf1_c_expo , + f_fpr_rf1_c_frac => f_fpr_rf1_c_frac , + f_fpr_rf1_b_sign => f_fpr_rf1_b_sign , + f_fpr_rf1_b_expo => f_fpr_rf1_b_expo , + f_fpr_rf1_b_frac => f_fpr_rf1_b_frac , + f_dcd_rf1_aop_valid => f_dcd_rf1_aop_valid , + f_dcd_rf1_cop_valid => f_dcd_rf1_cop_valid , + f_dcd_rf1_bop_valid => f_dcd_rf1_bop_valid , + f_dcd_rf1_sp => f_dcd_rf1_sp , + f_dcd_rf1_emin_dp => f_dcd_rf1_emin_dp , + f_dcd_rf1_emin_sp => f_dcd_rf1_emin_sp , + f_dcd_rf1_force_pass_b => f_dcd_rf1_force_pass_b , + f_dcd_rf1_fsel_b => f_dcd_rf1_fsel_b , + f_dcd_rf1_from_integer_b => f_dcd_rf1_from_integer_b , + f_dcd_rf1_to_integer_b => f_dcd_rf1_to_integer_b , + f_dcd_rf1_rnd_to_int_b => f_dcd_rf1_rnd_to_int_b , + f_dcd_rf1_math_b => f_dcd_rf1_math_b , + f_dcd_rf1_est_recip_b => f_dcd_rf1_est_recip_b , + f_dcd_rf1_est_rsqrt_b => f_dcd_rf1_est_rsqrt_b , + f_dcd_rf1_move_b => f_dcd_rf1_move_b , + f_dcd_rf1_prenorm_b => f_dcd_rf1_prenorm_b , + f_dcd_rf1_frsp_b => f_dcd_rf1_frsp_b , + f_dcd_rf1_compare_b => f_dcd_rf1_compare_b , + f_dcd_rf1_ordered_b => f_dcd_rf1_ordered_b , + f_dcd_rf1_nj_deni => f_dcd_rf1_nj_deni , + f_dcd_rf1_nj_deno => f_dcd_rf1_nj_deno , + f_dcd_rf1_sp_conv_b => f_dcd_rf1_sp_conv_b , + f_dcd_rf1_word_b => f_dcd_rf1_word_b , + f_dcd_rf1_uns_b => f_dcd_rf1_uns_b , + f_dcd_rf1_sub_op_b => f_dcd_rf1_sub_op_b , + f_dcd_rf1_op_rnd_v_b => f_dcd_rf1_op_rnd_v_b , + f_dcd_rf1_op_rnd_b => f_dcd_rf1_op_rnd_b , + f_dcd_rf1_inv_sign_b => f_dcd_rf1_inv_sign_b , + f_dcd_rf1_sign_ctl_b => f_dcd_rf1_sign_ctl_b , + f_dcd_rf1_sgncpy_b => f_dcd_rf1_sgncpy_b , + f_dcd_rf1_fpscr_bit_data_b => f_dcd_rf1_fpscr_bit_data_b , + f_dcd_rf1_fpscr_bit_mask_b => f_dcd_rf1_fpscr_bit_mask_b , + f_dcd_rf1_fpscr_nib_mask_b => f_dcd_rf1_fpscr_nib_mask_b , + f_dcd_rf1_mv_to_scr_b => f_dcd_rf1_mv_to_scr_b , + f_dcd_rf1_mv_from_scr_b => f_dcd_rf1_mv_from_scr_b , + f_dcd_rf1_mtfsbx_b => f_dcd_rf1_mtfsbx_b , + f_dcd_rf1_mcrfs_b => f_dcd_rf1_mcrfs_b , + f_dcd_rf1_mtfsf_b => f_dcd_rf1_mtfsf_b , + f_dcd_rf1_mtfsfi_b => f_dcd_rf1_mtfsfi_b , + f_dcd_rf1_log2e_b => f_dcd_rf1_log2e_b , + f_dcd_rf1_pow2e_b => f_dcd_rf1_pow2e_b , + f_dcd_rf1_ftdiv => f_dcd_rf1_ftdiv , + f_dcd_rf1_ftsqrt => f_dcd_rf1_ftsqrt , + f_dcd_ex1_perr_force_c => f_dcd_ex1_perr_force_c , + f_dcd_ex1_perr_fsel_ovrd => f_dcd_ex1_perr_fsel_ovrd , + f_add_ex4_fpcc_iu => f_add_ex4_fpcc_iu , + f_pic_ex5_fpr_wr_dis_b => f_pic_ex5_fpr_wr_dis_b , + f_scr_ex7_cr_fld => f_scr_ex7_cr_fld , + f_rnd_ex6_res_expo => f_rnd_ex6_res_expo , + f_rnd_ex6_res_frac => f_rnd_ex6_res_frac , + f_rnd_ex6_res_sign => f_rnd_ex6_res_sign , + f_ex2_b_den_flush => f_ex2_b_den_flush , + f_scr_ex7_fx_thread0 => f_scr_ex7_fx_thread0 , + f_scr_ex7_fx_thread1 => f_scr_ex7_fx_thread1 , + f_scr_ex7_fx_thread2 => f_scr_ex7_fx_thread2 , + f_scr_ex7_fx_thread3 => f_scr_ex7_fx_thread3 , + + f_dcd_rf1_uc_ft_pos => f_dcd_rf1_uc_ft_pos , + f_dcd_rf1_uc_ft_neg => f_dcd_rf1_uc_ft_neg , + f_dcd_rf1_uc_fa_pos => f_dcd_rf1_uc_fa_pos , + f_dcd_rf1_uc_fc_pos => f_dcd_rf1_uc_fc_pos , + f_dcd_rf1_uc_fb_pos => f_dcd_rf1_uc_fb_pos , + f_dcd_rf1_uc_fc_hulp => f_dcd_rf1_uc_fc_hulp , + f_dcd_rf1_uc_fc_0_5 => f_dcd_rf1_uc_fc_0_5 , + f_dcd_rf1_uc_fc_1_0 => f_dcd_rf1_uc_fc_1_0 , + f_dcd_rf1_uc_fc_1_minus => f_dcd_rf1_uc_fc_1_minus , + f_dcd_rf1_uc_fb_1_0 => f_dcd_rf1_uc_fb_1_0 , + f_dcd_rf1_uc_fb_0_75 => f_dcd_rf1_uc_fb_0_75 , + f_dcd_rf1_uc_fb_0_5 => f_dcd_rf1_uc_fb_0_5 , + f_dcd_ex2_uc_inc_lsb => f_dcd_ex2_uc_inc_lsb , + f_dcd_ex2_uc_gs_v => f_dcd_ex2_uc_gs_v , + f_dcd_ex2_uc_gs => f_dcd_ex2_uc_gs , + f_dcd_rf1_div_beg => f_dcd_rf1_div_beg , + f_dcd_rf1_sqrt_beg => f_dcd_rf1_sqrt_beg , + f_dcd_rf1_uc_mid => f_dcd_rf1_uc_mid , + f_dcd_rf1_uc_end => f_dcd_rf1_uc_end , + f_dcd_rf1_uc_special => f_dcd_rf1_uc_special , + f_dcd_ex2_uc_vxsnan => f_dcd_ex2_uc_vxsnan , + f_dcd_ex2_uc_zx => f_dcd_ex2_uc_zx , + f_dcd_ex2_uc_vxidi => f_dcd_ex2_uc_vxidi , + f_dcd_ex2_uc_vxzdz => f_dcd_ex2_uc_vxzdz , + f_dcd_ex2_uc_vxsqrt => f_dcd_ex2_uc_vxsqrt , + f_mad_ex6_uc_sign => f_mad_ex6_uc_sign , + f_mad_ex6_uc_zero => f_mad_ex6_uc_zero , + f_mad_ex3_uc_special => f_mad_ex3_uc_special , + f_mad_ex3_uc_vxsnan => f_mad_ex3_uc_vxsnan , + f_mad_ex3_uc_zx => f_mad_ex3_uc_zx , + f_mad_ex3_uc_vxsqrt => f_mad_ex3_uc_vxsqrt , + f_mad_ex3_uc_vxidi => f_mad_ex3_uc_vxidi , + f_mad_ex3_uc_vxzdz => f_mad_ex3_uc_vxzdz , + f_mad_ex3_uc_res_sign => f_mad_ex3_uc_res_sign , + f_mad_ex3_uc_round_mode(0 to 1) => f_mad_ex3_uc_round_mode(0 to 1) , + f_fpr_ex1_a_par => f_fpr_ex1_a_par , + f_fpr_ex1_b_par => f_fpr_ex1_b_par , + f_fpr_ex1_c_par => f_fpr_ex1_c_par , + f_mad_ex2_a_parity_check => f_mad_ex2_a_parity_check , + f_mad_ex2_c_parity_check => f_mad_ex2_c_parity_check , + f_mad_ex2_b_parity_check => f_mad_ex2_b_parity_check , + + rf1_thread_b => f_dcd_rf1_thread_b , + vdd => vdd , + gnd => gnd , + scan_in => f_mad_si(0 to 17) , + scan_out => f_mad_so(0 to 17) , + clkoff_b => clkoff_dc_b , + act_dis => act_dis , + flush => pc_fu_ccflush_dc , + delay_lclkr => delay_lclkr_dc(1 to 7) , + mpw1_b => mpw1_dc_b(1 to 7) , + mpw2_b => mpw2_dc_b , + sg_1 => sg_1(0) , + thold_1 => func_sl_thold_1(0) , + fpu_enable => fpu_enable , + f_dcd_rf1_act => f_dcd_rf1_mad_act , + nclk => nclk ); + + + + + + dcd: entity work.fuq_dcd(fuq_dcd) + generic map( + expand_type => expand_type , + eff_ifar => eff_ifar , + regmode => regmode ) + port map( + nclk => nclk , + clkoff_b => clkoff_dc_b , + act_dis => act_dis , + flush => pc_fu_ccflush_dc , + delay_lclkr => delay_lclkr_dc , + mpw1_b => mpw1_dc_b , + mpw2_b => mpw2_dc_b , + sg_1 => sg_1(1) , + thold_1 => func_sl_thold_1(1) , + cfg_sl_thold_1 => cfg_sl_thold_1 , + func_slp_sl_thold_1 => func_slp_sl_thold_1 , + f_dcd_si => f_dcd_si , + f_dcd_so => f_dcd_so , + dcfg_scan_in => dcfg_scan_in , + dcfg_scan_out => dcfg_scan_out , + bcfg_scan_in => bcfg_scan_in , + bcfg_scan_out => bcfg_scan_out , + ccfg_scan_in => ccfg_scan_in , + ccfg_scan_out => ccfg_scan_out , + vdd => vdd , + gnd => gnd , + f_dcd_msr_fp_act => f_dcd_msr_fp_act , + fu_xu_rf1_act => fu_xu_rf1_act , + fu_xu_ex2_async_block => fu_xu_ex2_async_block , + iu_fu_rf0_instr_v => iu_fu_rf0_instr_v , + iu_fu_rf0_instr => iu_fu_rf0_instr , + iu_fu_rf0_fra_v => iu_fu_rf0_fra_v , + iu_fu_rf0_frb_v => iu_fu_rf0_frb_v , + iu_fu_rf0_frc_v => iu_fu_rf0_frc_v , + iu_fu_rf0_fra => iu_fu_rf0_fra , + iu_fu_rf0_frb => iu_fu_rf0_frb , + iu_fu_rf0_frc => iu_fu_rf0_frc , + iu_fu_rf0_tid => iu_fu_rf0_tid , + iu_fu_rf0_frt => iu_fu_rf0_frt , + iu_fu_rf0_ifar => iu_fu_rf0_ifar , + iu_fu_rf0_str_val => iu_fu_rf0_str_val , + iu_fu_rf0_ldst_val => iu_fu_rf0_ldst_val , + iu_fu_rf0_ldst_tid => iu_fu_rf0_ldst_tid , + iu_fu_rf0_ldst_tag => iu_fu_rf0_ldst_tag , + iu_fu_rf0_bypsel => iu_fu_rf0_bypsel , + iu_fu_rf0_instr_match => iu_fu_rf0_instr_match , + iu_fu_rf0_is_ucode => iu_fu_rf0_is_ucode , + iu_fu_rf0_ucfmul => iu_fu_rf0_ucfmul , + iu_fu_is2_tid_decode => iu_fu_is2_tid_decode , + iu_fu_ex2_n_flush => iu_fu_ex2_n_flush , + f_fpr_ex7_load_addr => f_fpr_ex7_load_addr , + f_fpr_ex7_load_v => f_fpr_ex7_load_v , + xu_is2_flush => xu_is2_flush , + xu_rf0_flush => xu_rf0_flush , + xu_rf1_flush => xu_rf1_flush , + xu_ex1_flush => xu_ex1_flush , + xu_ex2_flush => xu_ex2_flush , + xu_ex3_flush => xu_ex3_flush , + xu_ex4_flush => xu_ex4_flush , + xu_ex5_flush => xu_ex5_flush , + f_dcd_ex5_flush_int => f_dcd_ex5_flush_int , + xu_fu_ex5_reload_val => xu_fu_ex5_reload_val , + xu_fu_ex5_load_val => xu_fu_ex5_load_val , + f_ex2_b_den_flush => f_ex2_b_den_flush , + f_scr_ex7_fx_thread0 => f_scr_ex7_fx_thread0 , + f_scr_ex7_fx_thread1 => f_scr_ex7_fx_thread1 , + f_scr_ex7_fx_thread2 => f_scr_ex7_fx_thread2 , + f_scr_ex7_fx_thread3 => f_scr_ex7_fx_thread3 , + f_dcd_ex1_perr_force_c => f_dcd_ex1_perr_force_c , + f_dcd_ex1_perr_fsel_ovrd => f_dcd_ex1_perr_fsel_ovrd , + f_dcd_perr_sm_running => f_dcd_perr_sm_running , + f_add_ex4_fpcc_iu => f_add_ex4_fpcc_iu , + f_pic_ex5_fpr_wr_dis_b => f_pic_ex5_fpr_wr_dis_b , + f_scr_ex7_cr_fld => f_scr_ex7_cr_fld , + f_dcd_rf1_aop_valid => f_dcd_rf1_aop_valid , + f_dcd_rf1_cop_valid => f_dcd_rf1_cop_valid , + f_dcd_rf1_bop_valid => f_dcd_rf1_bop_valid , + f_dcd_rf1_sp => f_dcd_rf1_sp , + f_dcd_rf1_emin_dp => f_dcd_rf1_emin_dp , + f_dcd_rf1_emin_sp => f_dcd_rf1_emin_sp , + f_dcd_rf1_force_pass_b => f_dcd_rf1_force_pass_b , + f_dcd_rf1_fsel_b => f_dcd_rf1_fsel_b , + f_dcd_rf1_from_integer_b => f_dcd_rf1_from_integer_b , + f_dcd_rf1_to_integer_b => f_dcd_rf1_to_integer_b , + f_dcd_rf1_rnd_to_int_b => f_dcd_rf1_rnd_to_int_b , + f_dcd_rf1_math_b => f_dcd_rf1_math_b , + f_dcd_rf1_est_recip_b => f_dcd_rf1_est_recip_b , + f_dcd_rf1_est_rsqrt_b => f_dcd_rf1_est_rsqrt_b , + f_dcd_rf1_move_b => f_dcd_rf1_move_b , + f_dcd_rf1_prenorm_b => f_dcd_rf1_prenorm_b , + f_dcd_rf1_frsp_b => f_dcd_rf1_frsp_b , + f_dcd_rf1_compare_b => f_dcd_rf1_compare_b , + f_dcd_rf1_ordered_b => f_dcd_rf1_ordered_b , + f_dcd_rf1_force_excp_dis => f_dcd_rf1_force_excp_dis , + f_dcd_rf1_nj_deni => f_dcd_rf1_nj_deni , + f_dcd_rf1_nj_deno => f_dcd_rf1_nj_deno , + f_dcd_rf1_sp_conv_b => f_dcd_rf1_sp_conv_b , + f_dcd_rf1_uns_b => f_dcd_rf1_uns_b , + f_dcd_rf1_word_b => f_dcd_rf1_word_b , + f_dcd_rf1_sub_op_b => f_dcd_rf1_sub_op_b , + f_dcd_rf1_op_rnd_v_b => f_dcd_rf1_op_rnd_v_b , + f_dcd_rf1_op_rnd_b => f_dcd_rf1_op_rnd_b , + f_dcd_rf1_inv_sign_b => f_dcd_rf1_inv_sign_b , + f_dcd_rf1_sign_ctl_b => f_dcd_rf1_sign_ctl_b , + f_dcd_rf1_sgncpy_b => f_dcd_rf1_sgncpy_b , + f_dcd_rf1_fpscr_bit_data_b => f_dcd_rf1_fpscr_bit_data_b , + f_dcd_rf1_fpscr_bit_mask_b => f_dcd_rf1_fpscr_bit_mask_b , + f_dcd_rf1_fpscr_nib_mask_b => f_dcd_rf1_fpscr_nib_mask_b , + f_dcd_rf1_mv_to_scr_b => f_dcd_rf1_mv_to_scr_b , + f_dcd_rf1_mv_from_scr_b => f_dcd_rf1_mv_from_scr_b , + f_dcd_rf1_mtfsbx_b => f_dcd_rf1_mtfsbx_b , + f_dcd_rf1_mcrfs_b => f_dcd_rf1_mcrfs_b , + f_dcd_rf1_mtfsf_b => f_dcd_rf1_mtfsf_b , + f_dcd_rf1_mtfsfi_b => f_dcd_rf1_mtfsfi_b , + f_dcd_rf1_thread_b => f_dcd_rf1_thread_b , + f_dcd_rf1_sto_dp => f_dcd_rf1_sto_dp , + f_dcd_rf1_sto_sp => f_dcd_rf1_sto_sp , + f_dcd_rf1_sto_wd => f_dcd_rf1_sto_wd , + f_dcd_rf1_log2e_b => f_dcd_rf1_log2e_b , + f_dcd_rf1_pow2e_b => f_dcd_rf1_pow2e_b , + f_dcd_rf1_ftdiv => f_dcd_rf1_ftdiv , + f_dcd_rf1_ftsqrt => f_dcd_rf1_ftsqrt , + f_dcd_ex6_cancel => f_dcd_ex6_cancel , + f_dcd_rf1_mad_act => f_dcd_rf1_mad_act , + f_dcd_rf1_sto_act => f_dcd_rf1_sto_act , + f_dcd_rf1_bypsel_a_res0 => f_dcd_rf1_bypsel_a_res0 , + f_dcd_rf1_bypsel_a_load0 => f_dcd_rf1_bypsel_a_load0 , + f_dcd_rf1_bypsel_b_res0 => f_dcd_rf1_bypsel_b_res0 , + f_dcd_rf1_bypsel_b_load0 => f_dcd_rf1_bypsel_b_load0 , + f_dcd_rf1_bypsel_c_res0 => f_dcd_rf1_bypsel_c_res0 , + f_dcd_rf1_bypsel_c_load0 => f_dcd_rf1_bypsel_c_load0 , + f_dcd_rf0_bypsel_a_res1 => f_dcd_rf0_bypsel_a_res1 , + f_dcd_rf0_bypsel_a_load1 => f_dcd_rf0_bypsel_a_load1 , + f_dcd_rf0_bypsel_b_res1 => f_dcd_rf0_bypsel_b_res1 , + f_dcd_rf0_bypsel_b_load1 => f_dcd_rf0_bypsel_b_load1 , + f_dcd_rf0_bypsel_c_res1 => f_dcd_rf0_bypsel_c_res1 , + f_dcd_rf0_bypsel_c_load1 => f_dcd_rf0_bypsel_c_load1 , + f_dcd_rf0_bypsel_s_res1 => f_dcd_rf0_bypsel_s_res1 , + f_dcd_rf0_bypsel_s_load1 => f_dcd_rf0_bypsel_s_load1 , + f_dcd_rf0_tid => f_dcd_rf0_tid , + f_dcd_rf0_fra => f_dcd_rf0_fra , + f_dcd_rf0_frb => f_dcd_rf0_frb , + f_dcd_rf0_frc => f_dcd_rf0_frc , + f_dcd_rf1_div_beg => f_dcd_rf1_div_beg , + f_dcd_rf1_sqrt_beg => f_dcd_rf1_sqrt_beg , + f_dcd_rf1_uc_ft_pos => f_dcd_rf1_uc_ft_pos , + f_dcd_rf1_uc_ft_neg => f_dcd_rf1_uc_ft_neg , + f_dcd_rf1_uc_fa_pos => f_dcd_rf1_uc_fa_pos , + f_dcd_rf1_uc_fc_pos => f_dcd_rf1_uc_fc_pos , + f_dcd_rf1_uc_fb_pos => f_dcd_rf1_uc_fb_pos , + f_dcd_rf1_uc_fc_hulp => f_dcd_rf1_uc_fc_hulp , + f_dcd_rf1_uc_fc_0_5 => f_dcd_rf1_uc_fc_0_5 , + f_dcd_rf1_uc_fc_1_0 => f_dcd_rf1_uc_fc_1_0 , + f_dcd_rf1_uc_fc_1_minus => f_dcd_rf1_uc_fc_1_minus , + f_dcd_rf1_uc_fb_1_0 => f_dcd_rf1_uc_fb_1_0 , + f_dcd_rf1_uc_fb_0_75 => f_dcd_rf1_uc_fb_0_75 , + f_dcd_rf1_uc_fb_0_5 => f_dcd_rf1_uc_fb_0_5 , + f_dcd_ex2_uc_inc_lsb => f_dcd_ex2_uc_inc_lsb , + f_dcd_rf1_uc_mid => f_dcd_rf1_uc_mid , + f_dcd_rf1_uc_end => f_dcd_rf1_uc_end , + fu_iu_uc_special => fu_iu_uc_special , + f_dcd_rf1_uc_special => f_dcd_rf1_uc_special , + f_dcd_ex2_uc_gs_v => f_dcd_ex2_uc_gs_v , + f_dcd_ex2_uc_gs => f_dcd_ex2_uc_gs , + f_dcd_ex2_uc_vxsnan => f_dcd_ex2_uc_vxsnan , + f_dcd_ex2_uc_zx => f_dcd_ex2_uc_zx , + f_dcd_ex2_uc_vxidi => f_dcd_ex2_uc_vxidi , + f_dcd_ex2_uc_vxzdz => f_dcd_ex2_uc_vxzdz , + f_dcd_ex2_uc_vxsqrt => f_dcd_ex2_uc_vxsqrt , + f_mad_ex6_uc_sign => f_mad_ex6_uc_sign , + f_mad_ex6_uc_zero => f_mad_ex6_uc_zero , + f_mad_ex3_uc_special => f_mad_ex3_uc_special , + f_mad_ex3_uc_vxsnan => f_mad_ex3_uc_vxsnan , + f_mad_ex3_uc_zx => f_mad_ex3_uc_zx , + f_mad_ex3_uc_vxidi => f_mad_ex3_uc_vxidi , + f_mad_ex3_uc_vxzdz => f_mad_ex3_uc_vxzdz , + f_mad_ex3_uc_vxsqrt => f_mad_ex3_uc_vxsqrt , + f_mad_ex3_uc_res_sign => f_mad_ex3_uc_res_sign , + f_mad_ex3_uc_round_mode => f_mad_ex3_uc_round_mode , + slowspr_val_in => slowspr_val_in , + slowspr_rw_in => slowspr_rw_in , + slowspr_etid_in => slowspr_etid_in , + slowspr_addr_in => slowspr_addr_in , + slowspr_data_in => slowspr_data_in , + slowspr_done_in => slowspr_done_in , + slowspr_val_out => slowspr_val_out , + slowspr_rw_out => slowspr_rw_out , + slowspr_etid_out => slowspr_etid_out , + slowspr_addr_out => slowspr_addr_out , + slowspr_data_out => slowspr_data_out , + slowspr_done_out => slowspr_done_out , + pc_fu_trace_bus_enable => pc_fu_trace_bus_enable , + pc_fu_event_bus_enable => pc_fu_event_bus_enable , + pc_fu_debug_mux_ctrls => pc_fu_debug_mux_ctrls , + pc_fu_event_count_mode => pc_fu_event_count_mode , + pc_fu_event_mux_ctrls => pc_fu_event_mux_ctrls , + debug_data_in => debug_data_in , + debug_data_out => debug_data_out , + trace_triggers_in => trace_triggers_in , + trace_triggers_out => trace_triggers_out , + fu_pc_event_data => fu_pc_event_data , + + xu_fu_msr_fp => xu_fu_msr_fp , + xu_fu_msr_pr => xu_fu_msr_pr , + xu_fu_msr_gs => xu_fu_msr_gs , + pc_fu_instr_trace_mode => pc_fu_instr_trace_mode , + pc_fu_instr_trace_tid => pc_fu_instr_trace_tid , + + f_rnd_ex6_res_expo => f_rnd_ex6_res_expo , + f_rnd_ex6_res_frac => f_rnd_ex6_res_frac , + f_rnd_ex6_res_sign => f_rnd_ex6_res_sign , + pc_fu_ram_mode => pc_fu_ram_mode , + pc_fu_ram_thread => pc_fu_ram_thread , + fu_pc_ram_done => fu_pc_ram_done , + fu_pc_ram_data => fu_pc_ram_data , + f_sto_ex2_s_parity_check => f_sto_ex2_s_parity_check , + f_mad_ex2_a_parity_check => f_mad_ex2_a_parity_check , + f_mad_ex2_b_parity_check => f_mad_ex2_b_parity_check , + f_mad_ex2_c_parity_check => f_mad_ex2_c_parity_check , + fu_pc_err_regfile_parity => fu_pc_err_regfile_parity , + fu_pc_err_regfile_ue => fu_pc_err_regfile_ue , + fu_xu_ex3_regfile_err_det => fu_xu_ex3_regfile_err_det , + xu_fu_regfile_seq_beg => xu_fu_regfile_seq_beg , + fu_xu_regfile_seq_end => fu_xu_regfile_seq_end , + f_dcd_ex6_frt_addr => f_dcd_ex6_frt_addr , + f_dcd_ex5_frt_tid => f_dcd_ex5_frt_tid , + f_dcd_ex6_frt_tid => f_dcd_ex6_frt_tid , + f_dcd_ex6_frt_wen => f_dcd_ex6_frt_wen , + fu_xu_ex2_store_data_val => fu_xu_ex2_store_data_val , + fu_xu_ex4_cr => fu_xu_ex4_cr , + fu_xu_ex4_cr_val => fu_xu_ex4_cr_val , + fu_xu_ex4_cr_bf => fu_xu_ex4_cr_bf , + fu_xu_ex4_cr_noflush => fu_xu_ex4_cr_noflush , + xu_fu_ex3_eff_addr => xu_fu_ex3_eff_addr , + fu_xu_ex3_n_flush => fu_xu_ex3_n_flush , + fu_xu_ex3_np1_flush => fu_xu_ex3_np1_flush , + fu_xu_ex3_ap_int_req => fu_xu_ex3_ap_int_req , + fu_xu_ex3_flush2ucode => fu_xu_ex3_flush2ucode , + fu_xu_ex2_instr_type => fu_xu_ex2_instr_type , + fu_xu_ex2_instr_match => fu_xu_ex2_instr_match , + fu_xu_ex2_is_ucode => fu_xu_ex2_is_ucode , + fu_xu_ex3_trap => fu_xu_ex3_trap , + fu_xu_ex2_ifar_val => fu_xu_ex2_ifar_val , + fu_xu_ex2_ifar_issued => fu_xu_ex2_ifar_issued , + fu_xu_ex1_ifar => fu_xu_ex1_ifar ); + + + + spare_unused(0) <= pc_fu_abst_slp_sl_thold_3; + spare_unused(1) <= pc_fu_cfg_slp_sl_thold_3; + spare_unused(2) <= pc_fu_func_nsl_thold_3; + spare_unused(3) <= pc_fu_func_slp_nsl_thold_3; + spare_unused(4) <= pc_fu_ary_slp_nsl_thold_3; + spare_unused(5) <= xu_fu_ex5_load_le; + + + + + f_fpr_si <= func_scan_in(0); + f_sto_si <= f_fpr_so; + f_dcd_si <= f_sto_so; + func_scan_out(0) <= scan_dis_dc_b and f_dcd_so; + + + f_mad_si(0) <= func_scan_in(1); + f_mad_si(1) <= f_mad_so(0); + f_mad_si(2) <= f_mad_so(1); + f_mad_si(3) <= f_mad_so(2); + f_mad_si(4) <= f_mad_so(3); + f_mad_si(5) <= f_mad_so(4); + func_scan_out(1) <= scan_dis_dc_b and f_mad_so(5); + + f_mad_si(6) <= func_scan_in(2); + f_mad_si(7) <= f_mad_so(6); + f_mad_si(8) <= f_mad_so(7); + f_mad_si(9) <= f_mad_so(8); + f_mad_si(10) <= f_mad_so(9); + f_mad_si(11) <= f_mad_so(10); + func_scan_out(2) <= scan_dis_dc_b and f_mad_so(11); + + f_mad_si(12) <= func_scan_in(3); + f_mad_si(13) <= f_mad_so(12); + f_mad_si(14) <= f_mad_so(13); + f_mad_si(15) <= f_mad_so(14); + f_mad_si(16) <= f_mad_so(15); + f_mad_si(17) <= f_mad_so(16); + func_scan_out(3) <= scan_dis_dc_b and f_mad_so(17); + + + bx_pc_err_inbox_ue_ofu <= bx_pc_err_inbox_ue_ifu ; + bx_pc_err_outbox_ue_ofu <= bx_pc_err_outbox_ue_ifu ; + bx_pc_err_inbox_ecc_ofu <= bx_pc_err_inbox_ecc_ifu ; + bx_pc_err_outbox_ecc_ofu <= bx_pc_err_outbox_ecc_ifu ; + pc_bx_bolt_sl_thold_3_ofu <= pc_bx_bolt_sl_thold_3_ifu ; + pc_bx_bo_enable_3_ofu <= pc_bx_bo_enable_3_ifu ; + pc_bx_bo_unload_ofu <= pc_bx_bo_unload_ifu ; + pc_bx_bo_repair_ofu <= pc_bx_bo_repair_ifu ; + pc_bx_bo_reset_ofu <= pc_bx_bo_reset_ifu ; + pc_bx_bo_shdata_ofu <= pc_bx_bo_shdata_ifu ; + pc_bx_bo_select_ofu <= pc_bx_bo_select_ifu ; + bx_pc_bo_fail_ofu <= bx_pc_bo_fail_ifu ; + bx_pc_bo_diagout_ofu <= bx_pc_bo_diagout_ifu ; + pc_bx_abist_di_0_ofu <= pc_bx_abist_di_0_ifu ; + pc_bx_abist_ena_dc_ofu <= pc_bx_abist_ena_dc_ifu ; + pc_bx_abist_g8t1p_renb_0_ofu <= pc_bx_abist_g8t1p_renb_0_ifu ; + pc_bx_abist_g8t_bw_0_ofu <= pc_bx_abist_g8t_bw_0_ifu ; + pc_bx_abist_g8t_bw_1_ofu <= pc_bx_abist_g8t_bw_1_ifu ; + pc_bx_abist_g8t_dcomp_ofu <= pc_bx_abist_g8t_dcomp_ifu ; + pc_bx_abist_g8t_wenb_ofu <= pc_bx_abist_g8t_wenb_ifu ; + pc_bx_abist_raddr_0_ofu <= pc_bx_abist_raddr_0_ifu ; + pc_bx_abist_raw_dc_b_ofu <= pc_bx_abist_raw_dc_b_ifu ; + pc_bx_abist_waddr_0_ofu <= pc_bx_abist_waddr_0_ifu ; + pc_bx_abist_wl64_comp_ena_ofu <= pc_bx_abist_wl64_comp_ena_ifu ; + pc_bx_trace_bus_enable_ofu <= pc_bx_trace_bus_enable_ifu ; + pc_bx_debug_mux1_ctrls_ofu <= pc_bx_debug_mux1_ctrls_ifu ; + pc_bx_inj_inbox_ecc_ofu <= pc_bx_inj_inbox_ecc_ifu ; + pc_bx_inj_outbox_ecc_ofu <= pc_bx_inj_outbox_ecc_ifu ; + pc_bx_ccflush_dc_ofu <= pc_bx_ccflush_dc_ifu ; + pc_bx_sg_3_ofu <= pc_bx_sg_3_ifu ; + pc_bx_func_sl_thold_3_ofu <= pc_bx_func_sl_thold_3_ifu ; + pc_bx_func_slp_sl_thold_3_ofu <= pc_bx_func_slp_sl_thold_3_ifu ; + pc_bx_gptr_sl_thold_3_ofu <= pc_bx_gptr_sl_thold_3_ifu ; + pc_bx_time_sl_thold_3_ofu <= pc_bx_time_sl_thold_3_ifu ; + pc_bx_repr_sl_thold_3_ofu <= pc_bx_repr_sl_thold_3_ifu ; + pc_bx_abst_sl_thold_3_ofu <= pc_bx_abst_sl_thold_3_ifu ; + pc_bx_ary_nsl_thold_3_ofu <= pc_bx_ary_nsl_thold_3_ifu ; + pc_bx_ary_slp_nsl_thold_3_ofu <= pc_bx_ary_slp_nsl_thold_3_ifu ; + + xu_pc_err_mcsr_summary_ofu <= xu_pc_err_mcsr_summary_ifu ; + xu_pc_err_ierat_parity_ofu <= xu_pc_err_ierat_parity_ifu ; + xu_pc_err_derat_parity_ofu <= xu_pc_err_derat_parity_ifu ; + xu_pc_err_tlb_parity_ofu <= xu_pc_err_tlb_parity_ifu ; + xu_pc_err_tlb_lru_parity_ofu <= xu_pc_err_tlb_lru_parity_ifu ; + xu_pc_err_ierat_multihit_ofu <= xu_pc_err_ierat_multihit_ifu ; + xu_pc_err_derat_multihit_ofu <= xu_pc_err_derat_multihit_ifu ; + xu_pc_err_tlb_multihit_ofu <= xu_pc_err_tlb_multihit_ifu ; + xu_pc_err_ext_mchk_ofu <= xu_pc_err_ext_mchk_ifu ; + xu_pc_err_mchk_disabled_ofu <= xu_pc_err_mchk_disabled_ifu ; + xu_pc_err_ditc_overrun_ofu <= xu_pc_err_ditc_overrun_ifu ; + xu_pc_err_local_snoop_reject_ofu <= xu_pc_err_local_snoop_reject_ifu ; + xu_pc_err_attention_instr_ofu <= xu_pc_err_attention_instr_ifu ; + xu_pc_err_dcache_parity_ofu <= xu_pc_err_dcache_parity_ifu ; + xu_pc_err_dcachedir_parity_ofu <= xu_pc_err_dcachedir_parity_ifu ; + xu_pc_err_dcachedir_multihit_ofu <= xu_pc_err_dcachedir_multihit_ifu ; + xu_pc_err_debug_event_ofu <= xu_pc_err_debug_event_ifu ; + xu_pc_err_invld_reld_ofu <= xu_pc_err_invld_reld_ifu ; + xu_pc_err_l2intrf_ecc_ofu <= xu_pc_err_l2intrf_ecc_ifu ; + xu_pc_err_l2intrf_ue_ofu <= xu_pc_err_l2intrf_ue_ifu ; + xu_pc_err_l2credit_overrun_ofu <= xu_pc_err_l2credit_overrun_ifu ; + xu_pc_err_llbust_attempt_ofu <= xu_pc_err_llbust_attempt_ifu ; + xu_pc_err_llbust_failed_ofu <= xu_pc_err_llbust_failed_ifu ; + xu_pc_err_nia_miscmpr_ofu <= xu_pc_err_nia_miscmpr_ifu ; + xu_pc_err_regfile_parity_ofu <= xu_pc_err_regfile_parity_ifu ; + xu_pc_err_regfile_ue_ofu <= xu_pc_err_regfile_ue_ifu ; + xu_pc_err_sprg_ecc_ofu <= xu_pc_err_sprg_ecc_ifu ; + xu_pc_err_sprg_ue_ofu <= xu_pc_err_sprg_ue_ifu ; + xu_pc_err_wdt_reset_ofu <= xu_pc_err_wdt_reset_ifu ; + xu_pc_event_data_ofu <= xu_pc_event_data_ifu ; + xu_pc_ram_data_ofu <= xu_pc_ram_data_ifu ; + xu_pc_ram_done_ofu <= xu_pc_ram_done_ifu ; + xu_pc_ram_interrupt_ofu <= xu_pc_ram_interrupt_ifu ; + xu_pc_running_ofu <= xu_pc_running_ifu ; + xu_pc_spr_ccr0_pme_ofu <= xu_pc_spr_ccr0_pme_ifu ; + xu_pc_spr_ccr0_we_ofu <= xu_pc_spr_ccr0_we_ifu ; + xu_pc_step_done_ofu <= xu_pc_step_done_ifu ; + xu_pc_stop_dbg_event_ofu <= xu_pc_stop_dbg_event_ifu ; + xu_pc_lsu_event_data_ofu <= xu_pc_lsu_event_data_ifu ; + pc_xu_bolt_sl_thold_3_ofu <= pc_xu_bolt_sl_thold_3_ifu ; + pc_xu_bo_enable_3_ofu <= pc_xu_bo_enable_3_ifu ; + pc_xu_bo_unload_ofu <= pc_xu_bo_unload_ifu ; + pc_xu_bo_load_ofu <= pc_xu_bo_load_ifu ; + pc_xu_bo_repair_ofu <= pc_xu_bo_repair_ifu ; + pc_xu_bo_reset_ofu <= pc_xu_bo_reset_ifu ; + pc_xu_bo_shdata_ofu <= pc_xu_bo_shdata_ifu ; + pc_xu_bo_select_ofu <= pc_xu_bo_select_ifu ; + xu_pc_bo_fail_ofu <= xu_pc_bo_fail_ifu ; + xu_pc_bo_diagout_ofu <= xu_pc_bo_diagout_ifu ; + pc_xu_abist_dcomp_g6t_2r_ofu <= pc_xu_abist_dcomp_g6t_2r_ifu ; + pc_xu_abist_di_0_ofu <= pc_xu_abist_di_0_ifu ; + pc_xu_abist_di_1_ofu <= pc_xu_abist_di_1_ifu ; + pc_xu_abist_di_g6t_2r_ofu <= pc_xu_abist_di_g6t_2r_ifu ; + pc_xu_abist_ena_dc_ofu <= pc_xu_abist_ena_dc_ifu ; + pc_xu_abist_g6t_bw_ofu <= pc_xu_abist_g6t_bw_ifu ; + pc_xu_abist_g6t_r_wb_ofu <= pc_xu_abist_g6t_r_wb_ifu ; + pc_xu_abist_g8t1p_renb_0_ofu <= pc_xu_abist_g8t1p_renb_0_ifu ; + pc_xu_abist_g8t_bw_0_ofu <= pc_xu_abist_g8t_bw_0_ifu ; + pc_xu_abist_g8t_bw_1_ofu <= pc_xu_abist_g8t_bw_1_ifu ; + pc_xu_abist_g8t_dcomp_ofu <= pc_xu_abist_g8t_dcomp_ifu ; + pc_xu_abist_g8t_wenb_ofu <= pc_xu_abist_g8t_wenb_ifu ; + pc_xu_abist_grf_renb_0_ofu <= pc_xu_abist_grf_renb_0_ifu ; + pc_xu_abist_grf_renb_1_ofu <= pc_xu_abist_grf_renb_1_ifu ; + pc_xu_abist_grf_wenb_0_ofu <= pc_xu_abist_grf_wenb_0_ifu ; + pc_xu_abist_grf_wenb_1_ofu <= pc_xu_abist_grf_wenb_1_ifu ; + pc_xu_abist_raddr_0_ofu <= pc_xu_abist_raddr_0_ifu ; + pc_xu_abist_raddr_1_ofu <= pc_xu_abist_raddr_1_ifu ; + pc_xu_abist_raw_dc_b_ofu <= pc_xu_abist_raw_dc_b_ifu ; + pc_xu_abist_waddr_0_ofu <= pc_xu_abist_waddr_0_ifu ; + pc_xu_abist_waddr_1_ofu <= pc_xu_abist_waddr_1_ifu ; + pc_xu_abist_wl144_comp_ena_ofu <= pc_xu_abist_wl144_comp_ena_ifu ; + pc_xu_abist_wl32_comp_ena_ofu <= pc_xu_abist_wl32_comp_ena_ifu ; + pc_xu_abist_wl512_comp_ena_ofu <= pc_xu_abist_wl512_comp_ena_ifu ; + pc_xu_event_mux_ctrls_ofu <= pc_xu_event_mux_ctrls_ifu ; + pc_xu_lsu_event_mux_ctrls_ofu <= pc_xu_lsu_event_mux_ctrls_ifu ; + pc_xu_event_bus_enable_ofu <= pc_xu_event_bus_enable_ifu ; + pc_xu_abst_sl_thold_3_ofu <= pc_xu_abst_sl_thold_3_ifu ; + pc_xu_abst_slp_sl_thold_3_ofu <= pc_xu_abst_slp_sl_thold_3_ifu ; + pc_xu_regf_sl_thold_3_ofu <= pc_xu_regf_sl_thold_3_ifu ; + pc_xu_regf_slp_sl_thold_3_ofu <= pc_xu_regf_slp_sl_thold_3_ifu ; + pc_xu_ary_nsl_thold_3_ofu <= pc_xu_ary_nsl_thold_3_ifu ; + pc_xu_ary_slp_nsl_thold_3_ofu <= pc_xu_ary_slp_nsl_thold_3_ifu ; + pc_xu_cache_par_err_event_ofu <= pc_xu_cache_par_err_event_ifu ; + pc_xu_ccflush_dc_ofu <= pc_xu_ccflush_dc_ifu ; + pc_xu_cfg_sl_thold_3_ofu <= pc_xu_cfg_sl_thold_3_ifu ; + pc_xu_cfg_slp_sl_thold_3_ofu <= pc_xu_cfg_slp_sl_thold_3_ifu ; + pc_xu_dbg_action_ofu <= pc_xu_dbg_action_ifu ; + pc_xu_debug_mux1_ctrls_ofu <= pc_xu_debug_mux1_ctrls_ifu ; + pc_xu_debug_mux2_ctrls_ofu <= pc_xu_debug_mux2_ctrls_ifu ; + pc_xu_debug_mux3_ctrls_ofu <= pc_xu_debug_mux3_ctrls_ifu ; + pc_xu_debug_mux4_ctrls_ofu <= pc_xu_debug_mux4_ctrls_ifu ; + pc_xu_decrem_dis_on_stop_ofu <= pc_xu_decrem_dis_on_stop_ifu ; + pc_xu_event_count_mode_ofu <= pc_xu_event_count_mode_ifu ; + pc_xu_extirpts_dis_on_stop_ofu <= pc_xu_extirpts_dis_on_stop_ifu ; + pc_xu_fce_3_ofu <= pc_xu_fce_3_ifu ; + pc_xu_force_ude_ofu <= pc_xu_force_ude_ifu ; + pc_xu_func_nsl_thold_3_ofu <= pc_xu_func_nsl_thold_3_ifu ; + pc_xu_func_sl_thold_3_ofu <= pc_xu_func_sl_thold_3_ifu ; + pc_xu_func_slp_nsl_thold_3_ofu <= pc_xu_func_slp_nsl_thold_3_ifu ; + pc_xu_func_slp_sl_thold_3_ofu <= pc_xu_func_slp_sl_thold_3_ifu ; + pc_xu_gptr_sl_thold_3_ofu <= pc_xu_gptr_sl_thold_3_ifu ; + pc_xu_init_reset_ofu <= pc_xu_init_reset_ifu ; + pc_xu_inj_dcache_parity_ofu <= pc_xu_inj_dcache_parity_ifu ; + pc_xu_inj_dcachedir_parity_ofu <= pc_xu_inj_dcachedir_parity_ifu ; + pc_xu_inj_llbust_attempt_ofu <= pc_xu_inj_llbust_attempt_ifu ; + pc_xu_inj_llbust_failed_ofu <= pc_xu_inj_llbust_failed_ifu ; + pc_xu_inj_sprg_ecc_ofu <= pc_xu_inj_sprg_ecc_ifu ; + pc_xu_inj_regfile_parity_ofu <= pc_xu_inj_regfile_parity_ifu ; + pc_xu_inj_wdt_reset_ofu <= pc_xu_inj_wdt_reset_ifu ; + pc_xu_inj_dcachedir_multihit_ofu <= pc_xu_inj_dcachedir_multihit_ifu ; + pc_xu_instr_trace_mode_ofu <= pc_xu_instr_trace_mode_ifu ; + pc_xu_instr_trace_tid_ofu <= pc_xu_instr_trace_tid_ifu ; + pc_xu_msrovride_enab_ofu <= pc_xu_msrovride_enab_ifu ; + pc_xu_msrovride_gs_ofu <= pc_xu_msrovride_gs_ifu ; + pc_xu_msrovride_pr_ofu <= pc_xu_msrovride_pr_ifu ; + pc_xu_ram_execute_ofu <= pc_xu_ram_execute_ifu ; + pc_xu_ram_flush_thread_ofu <= pc_xu_ram_flush_thread_ifu ; + pc_xu_ram_mode_ofu <= pc_xu_ram_mode_ifu ; + pc_xu_ram_thread_ofu <= pc_xu_ram_thread_ifu ; + pc_xu_repr_sl_thold_3_ofu <= pc_xu_repr_sl_thold_3_ifu ; + pc_xu_reset_1_cmplt_ofu <= pc_xu_reset_1_cmplt_ifu ; + pc_xu_reset_2_cmplt_ofu <= pc_xu_reset_2_cmplt_ifu ; + pc_xu_reset_3_cmplt_ofu <= pc_xu_reset_3_cmplt_ifu ; + pc_xu_reset_wd_cmplt_ofu <= pc_xu_reset_wd_cmplt_ifu ; + pc_xu_sg_3_ofu <= pc_xu_sg_3_ifu ; + pc_xu_step_ofu <= pc_xu_step_ifu ; + pc_xu_stop_ofu <= pc_xu_stop_ifu ; + pc_xu_time_sl_thold_3_ofu <= pc_xu_time_sl_thold_3_ifu ; + pc_xu_timebase_dis_on_stop_ofu <= pc_xu_timebase_dis_on_stop_ifu ; + pc_xu_trace_bus_enable_ofu <= pc_xu_trace_bus_enable_ifu ; + + an_ac_scan_dis_dc_b_ofu <= scan_dis_dc_b ; + an_ac_scan_diag_dc_ofu <= scan_diag_dc ; + + xu_ex2_flush_ofu <= xu_ex2_flush ; + xu_ex3_flush_ofu <= xu_ex3_flush ; + xu_ex4_flush_ofu <= xu_ex4_flush ; + xu_ex5_flush_ofu <= xu_ex5_flush ; + an_ac_lbist_ary_wrt_thru_dc_ofu <= an_ac_lbist_ary_wrt_thru_dc ; + + +end architecture fuq; + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_add.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_add.vhdl new file mode 100644 index 0000000..3a950e9 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_add.vhdl @@ -0,0 +1,580 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + +entity fuq_add is +generic( expand_type : integer := 2 ); +port( + + vdd :inout power_logic; + gnd :inout power_logic; + clkoff_b :in std_ulogic; + act_dis :in std_ulogic; + flush :in std_ulogic; + delay_lclkr :in std_ulogic_vector(3 to 4); + mpw1_b :in std_ulogic_vector(3 to 4); + mpw2_b :in std_ulogic_vector(0 to 0); + sg_1 :in std_ulogic; + thold_1 :in std_ulogic; + fpu_enable :in std_ulogic; + nclk :in clk_logic; + + f_add_si :in std_ulogic; + f_add_so :out std_ulogic; + ex1_act_b :in std_ulogic; + + f_sa3_ex3_s :in std_ulogic_vector(0 to 162); + f_sa3_ex3_c :in std_ulogic_vector(53 to 161); + + f_alg_ex3_frc_sel_p1 :in std_ulogic; + f_alg_ex3_sticky :in std_ulogic; + f_alg_ex2_effsub_eac_b :in std_ulogic; + f_alg_ex2_prod_z :in std_ulogic; + + f_pic_ex3_is_gt :in std_ulogic; + f_pic_ex3_is_lt :in std_ulogic; + f_pic_ex3_is_eq :in std_ulogic; + f_pic_ex3_is_nan :in std_ulogic; + f_pic_ex3_cmp_sgnpos :in std_ulogic; + f_pic_ex3_cmp_sgnneg :in std_ulogic; + + f_add_ex4_res :out std_ulogic_vector(0 to 162); + f_add_ex4_flag_nan :out std_ulogic; + f_add_ex4_flag_gt :out std_ulogic; + f_add_ex4_flag_lt :out std_ulogic; + f_add_ex4_flag_eq :out std_ulogic; + f_add_ex4_fpcc_iu :out std_ulogic_vector(0 to 3); + f_add_ex4_sign_carry :out std_ulogic; + f_add_ex4_to_int_ovf_wd :out std_ulogic_vector(0 to 1); + f_add_ex4_to_int_ovf_dw :out std_ulogic_vector(0 to 1); + f_add_ex4_sticky :out std_ulogic + +); + + + +end fuq_add; + +architecture fuq_add of fuq_add is + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + + signal thold_0_b, thold_0 :std_ulogic; + signal sg_0, forcee :std_ulogic; + + signal ex1_act :std_ulogic; + signal ex2_act :std_ulogic; + signal ex3_act :std_ulogic; + + signal act_si :std_ulogic_vector(0 to 8); + signal act_so :std_ulogic_vector(0 to 8); + signal ex4_res_so :std_ulogic_vector(0 to 162); + signal ex4_res_si :std_ulogic_vector(0 to 162); + signal ex4_cmp_so :std_ulogic_vector(0 to 9); + signal ex4_cmp_si :std_ulogic_vector(0 to 9); + + signal spare_unused :std_ulogic_vector(0 to 3); + + + signal ex3_s :std_ulogic_vector( 0 to 162); + signal ex3_c :std_ulogic_vector(53 to 161); + + signal ex3_flag_nan :std_ulogic; + signal ex3_flag_gt :std_ulogic; + signal ex3_flag_lt :std_ulogic; + signal ex3_flag_eq :std_ulogic; + signal ex3_sign_carry :std_ulogic; + + signal ex3_inc_all1 :std_ulogic; + signal ex3_inc_byt_c_glb :std_ulogic_vector(1 to 6); + signal ex3_inc_byt_c_glb_b :std_ulogic_vector(1 to 6); + signal ex3_inc_p1 :std_ulogic_vector(0 to 52); + signal ex3_inc_p0 :std_ulogic_vector(0 to 52); + + signal ex3_s_p0 :std_ulogic_vector(53 to 162); + signal ex3_s_p1 :std_ulogic_vector(53 to 162); + signal ex3_res :std_ulogic_vector(0 to 162); + + signal ex2_effsub :std_ulogic; + signal ex3_effsub :std_ulogic; + + signal ex2_effadd_npz :std_ulogic; + signal ex2_effsub_npz :std_ulogic; + signal ex3_effsub_npz :std_ulogic; + signal ex3_effadd_npz :std_ulogic; + signal ex3_flip_inc_p0 :std_ulogic; + signal ex3_flip_inc_p1 :std_ulogic; + signal ex3_inc_sel_p0 :std_ulogic; + signal ex3_inc_sel_p1 :std_ulogic; + + signal ex4_res, ex4_res_b , ex4_res_l2_b :std_ulogic_vector(0 to 162) ; + signal ex4_flag_nan_b :std_ulogic; + signal ex4_flag_gt_b :std_ulogic; + signal ex4_flag_lt_b :std_ulogic; + signal ex4_flag_eq_b :std_ulogic; + signal ex4_fpcc_iu_b :std_ulogic_vector(0 to 3) ; + signal ex4_sign_carry_b :std_ulogic; + signal ex4_sticky_b :std_ulogic; + + signal ex3_g16 :std_ulogic_vector(0 to 6); + signal ex3_t16 :std_ulogic_vector(0 to 6); + signal ex3_g128, ex3_t128, ex3_g128_b, ex3_t128_b :std_ulogic_vector(1 to 6); + signal ex3_inc_byt_c_b :std_ulogic_vector(0 to 6); + signal ex3_eac_sel_p0n, ex3_eac_sel_p0, ex3_eac_sel_p1 : std_ulogic_vector(0 to 6); + signal ex3_flag_nan_cp1, ex3_flag_gt_cp1, ex3_flag_lt_cp1, ex3_flag_eq_cp1 :std_ulogic; + signal add_ex4_d1clk , add_ex4_d2clk :std_ulogic ; + signal add_ex4_lclk :clk_logic ; + + signal ex3_s_p0n, ex3_res_p0n_b, ex3_res_p0_b, ex3_res_p1_b :std_ulogic_vector(53 to 162); + signal ex3_inc_p0_x, ex3_inc_p1_x, ex3_incx_p0_b, ex3_incx_p1_b :std_ulogic_vector(0 to 52); + signal ex3_sel_a1, ex3_sel_a2, ex3_sel_a3 :std_ulogic_vector(53 to 162); + + + + + + + + + + + +begin + + + thold_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => thold_1, + q(0) => thold_0 ); + + sg_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => sg_1 , + q(0) => sg_0 ); + + lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map ( + clkoff_b => clkoff_b, + thold => thold_0, + sg => sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => thold_0_b ); + + + ex1_act <= not ex1_act_b ; + ex2_effsub <= not f_alg_ex2_effsub_eac_b ; + ex2_effsub_npz <= not f_alg_ex2_effsub_eac_b and not f_alg_ex2_prod_z; + ex2_effadd_npz <= f_alg_ex2_effsub_eac_b and not f_alg_ex2_prod_z; + + act_lat: tri_rlmreg_p generic map (width=> 9, expand_type => expand_type, needs_sreset => 0) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(3) , + mpw1_b => mpw1_b(3) , + mpw2_b => mpw2_b(0) , + nclk => nclk, + act => fpu_enable, + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scout => act_so , + scin => act_si , + din(0) => spare_unused(0), + din(1) => spare_unused(1), + din(2) => ex1_act, + din(3) => ex2_act, + din(4) => ex2_effsub , + din(5) => ex2_effsub_npz, + din(6) => ex2_effadd_npz, + din(7) => spare_unused(2), + din(8) => spare_unused(3), + dout(0) => spare_unused(0), + dout(1) => spare_unused(1), + dout(2) => ex2_act, + dout(3) => ex3_act, + dout(4) => ex3_effsub , + dout(5) => ex3_effsub_npz, + dout(6) => ex3_effadd_npz, + dout(7) => spare_unused(2) , + dout(8) => spare_unused(3) ); + + add_ex4_lcb : tri_lcbnd generic map (expand_type => expand_type) port map( + delay_lclkr => delay_lclkr(4) , + mpw1_b => mpw1_b(4) , + mpw2_b => mpw2_b(0) , + forcee => forcee, + nclk => nclk , + vd => vdd , + gd => gnd , + act => ex3_act , + sg => sg_0 , + thold_b => thold_0_b , + d1clk => add_ex4_d1clk , + d2clk => add_ex4_d2clk , + lclk => add_ex4_lclk ); + + + + ex3_s(0 to 162) <= f_sa3_ex3_s(0 to 162); + ex3_c(53 to 161) <= f_sa3_ex3_c(53 to 161); + + + + all1: entity work.fuq_add_all1(fuq_add_all1) port map( + ex3_inc_byt_c_b(0 to 6) => ex3_inc_byt_c_b(0 to 6) , + ex3_inc_byt_c_glb(1 to 6) => ex3_inc_byt_c_glb(1 to 6) , + ex3_inc_byt_c_glb_b(1 to 6) => ex3_inc_byt_c_glb_b(1 to 6) , + ex3_inc_all1 => ex3_inc_all1 ); + + + inc8_6: entity work.fuq_loc8inc_lsb(fuq_loc8inc_lsb) port map( + co_b => ex3_inc_byt_c_b(6) , + x => ex3_s ( 48 to 52) , + s0 => ex3_inc_p0( 48 to 52) , + s1 => ex3_inc_p1( 48 to 52) ); + + inc8_5: entity work.fuq_loc8inc(fuq_loc8inc) port map( + ci => ex3_inc_byt_c_glb(6) , + ci_b => ex3_inc_byt_c_glb_b(6) , + co_b => ex3_inc_byt_c_b(5) , + x => ex3_s ( 40 to 47) , + s0 => ex3_inc_p0( 40 to 47) , + s1 => ex3_inc_p1( 40 to 47) ); + + inc8_4: entity work.fuq_loc8inc(fuq_loc8inc) port map( + ci => ex3_inc_byt_c_glb(5) , + ci_b => ex3_inc_byt_c_glb_b(5) , + co_b => ex3_inc_byt_c_b(4) , + x => ex3_s ( 32 to 39) , + s0 => ex3_inc_p0( 32 to 39) , + s1 => ex3_inc_p1( 32 to 39) ); + + inc8_3: entity work.fuq_loc8inc(fuq_loc8inc) port map( + ci => ex3_inc_byt_c_glb(4) , + ci_b => ex3_inc_byt_c_glb_b(4) , + co_b => ex3_inc_byt_c_b(3) , + x => ex3_s ( 24 to 31) , + s0 => ex3_inc_p0( 24 to 31) , + s1 => ex3_inc_p1( 24 to 31) ); + + inc8_2: entity work.fuq_loc8inc(fuq_loc8inc) port map( + ci => ex3_inc_byt_c_glb(3) , + ci_b => ex3_inc_byt_c_glb_b(3) , + co_b => ex3_inc_byt_c_b(2) , + x => ex3_s ( 16 to 23) , + s0 => ex3_inc_p0( 16 to 23) , + s1 => ex3_inc_p1( 16 to 23) ); + + inc8_1: entity work.fuq_loc8inc(fuq_loc8inc) port map( + ci => ex3_inc_byt_c_glb(2) , + ci_b => ex3_inc_byt_c_glb_b(2) , + co_b => ex3_inc_byt_c_b(1) , + x => ex3_s ( 8 to 15) , + s0 => ex3_inc_p0( 8 to 15) , + s1 => ex3_inc_p1( 8 to 15) ); + + inc8_0: entity work.fuq_loc8inc(fuq_loc8inc) port map( + ci => ex3_inc_byt_c_glb(1) , + ci_b => ex3_inc_byt_c_glb_b(1) , + co_b => ex3_inc_byt_c_b(0) , + x => ex3_s ( 0 to 7) , + s0 => ex3_inc_p0( 0 to 7) , + s1 => ex3_inc_p1( 0 to 7) ); + + + + + + + + hc16_0: entity work.fuq_hc16pp_msb(fuq_hc16pp_msb) port map( + x => ex3_s( 53 to 68) , + y => ex3_c( 53 to 68) , + ci0 => ex3_g128(1) , + ci0_b => ex3_g128_b(1) , + ci1 => ex3_t128(1) , + ci1_b => ex3_t128_b(1) , + s0 => ex3_s_p0( 53 to 68) , + s1 => ex3_s_p1( 53 to 68) , + g16 => ex3_g16(0) , + t16 => ex3_t16(0) ); + + hc16_1: entity work.fuq_hc16pp(fuq_hc16pp) port map( + x => ex3_s( 69 to 84) , + y => ex3_c( 69 to 84) , + ci0 => ex3_g128(2) , + ci0_b => ex3_g128_b(2) , + ci1 => ex3_t128(2) , + ci1_b => ex3_t128_b(2) , + s0 => ex3_s_p0( 69 to 84) , + s1 => ex3_s_p1( 69 to 84) , + g16 => ex3_g16(1) , + t16 => ex3_t16(1) ); + + hc16_2: entity work.fuq_hc16pp(fuq_hc16pp) port map( + x => ex3_s( 85 to 100) , + y => ex3_c( 85 to 100) , + ci0 => ex3_g128(3) , + ci0_b => ex3_g128_b(3) , + ci1 => ex3_t128(3) , + ci1_b => ex3_t128_b(3) , + s0 => ex3_s_p0( 85 to 100) , + s1 => ex3_s_p1( 85 to 100) , + g16 => ex3_g16(2) , + t16 => ex3_t16(2) ); + + hc16_3: entity work.fuq_hc16pp(fuq_hc16pp) port map( + x => ex3_s(101 to 116) , + y => ex3_c(101 to 116) , + ci0 => ex3_g128(4) , + ci0_b => ex3_g128_b(4) , + ci1 => ex3_t128(4) , + ci1_b => ex3_t128_b(4) , + s0 => ex3_s_p0(101 to 116) , + s1 => ex3_s_p1(101 to 116) , + g16 => ex3_g16(3) , + t16 => ex3_t16(3) ); + + hc16_4: entity work.fuq_hc16pp(fuq_hc16pp) port map( + x => ex3_s(117 to 132) , + y => ex3_c(117 to 132) , + ci0 => ex3_g128(5) , + ci0_b => ex3_g128_b(5) , + ci1 => ex3_t128(5) , + ci1_b => ex3_t128_b(5) , + s0 => ex3_s_p0(117 to 132) , + s1 => ex3_s_p1(117 to 132) , + g16 => ex3_g16(4) , + t16 => ex3_t16(4) ); + + hc16_5: entity work.fuq_hc16pp(fuq_hc16pp) port map( + x => ex3_s(133 to 148) , + y => ex3_c(133 to 148) , + ci0 => ex3_g128(6) , + ci0_b => ex3_g128_b(6) , + ci1 => ex3_t128(6) , + ci1_b => ex3_t128_b(6) , + s0 => ex3_s_p0(133 to 148) , + s1 => ex3_s_p1(133 to 148) , + g16 => ex3_g16(5) , + t16 => ex3_t16(5) ); + + hc16_6: entity work.fuq_hc16pp_lsb(fuq_hc16pp_lsb) port map( + x(0 to 13) => ex3_s(149 to 162) , + y(0 to 12) => ex3_c(149 to 161) , + s0 => ex3_s_p0(149 to 162) , + s1 => ex3_s_p1(149 to 162) , + g16 => ex3_g16(6) , + t16 => ex3_t16(6) ); + + + + + + u_incmx_p0x: ex3_inc_p0_x(0 to 52) <= ex3_inc_p0(0 to 52) xor (0 to 52=> ex3_flip_inc_p0); + u_incmx_p1x: ex3_inc_p1_x(0 to 52) <= ex3_inc_p1(0 to 52) xor (0 to 52=> ex3_flip_inc_p1); + + u_incmx_p0: ex3_incx_p0_b(0 to 52) <= not( (0 to 52=> ex3_inc_sel_p0) and ex3_inc_p0_x(0 to 52) ); + u_incmx_p1: ex3_incx_p1_b(0 to 52) <= not( (0 to 52=> ex3_inc_sel_p1) and ex3_inc_p1_x(0 to 52) ); + u_incmx: ex3_res (0 to 52) <= not( ex3_incx_p0_b(0 to 52) and ex3_incx_p1_b(0 to 52) ); + + + ex3_sel_a1(53 to 68) <= (53 to 68 => ex3_eac_sel_p0n(0) ); + ex3_sel_a1(69 to 84) <= (69 to 84 => ex3_eac_sel_p0n(1) ); + ex3_sel_a1(85 to 100) <= (85 to 100 => ex3_eac_sel_p0n(2) ); + ex3_sel_a1(101 to 116) <= (101 to 116 => ex3_eac_sel_p0n(3) ); + ex3_sel_a1(117 to 132) <= (117 to 132 => ex3_eac_sel_p0n(4) ); + ex3_sel_a1(133 to 148) <= (133 to 148 => ex3_eac_sel_p0n(5) ); + ex3_sel_a1(149 to 162) <= (149 to 162 => ex3_eac_sel_p0n(6) ); + + ex3_sel_a2(53 to 68) <= (53 to 68 => ex3_eac_sel_p0(0) ); + ex3_sel_a2(69 to 84) <= (69 to 84 => ex3_eac_sel_p0(1) ); + ex3_sel_a2(85 to 100) <= (85 to 100 => ex3_eac_sel_p0(2) ); + ex3_sel_a2(101 to 116) <= (101 to 116 => ex3_eac_sel_p0(3) ); + ex3_sel_a2(117 to 132) <= (117 to 132 => ex3_eac_sel_p0(4) ); + ex3_sel_a2(133 to 148) <= (133 to 148 => ex3_eac_sel_p0(5) ); + ex3_sel_a2(149 to 162) <= (149 to 162 => ex3_eac_sel_p0(6) ); + + ex3_sel_a3(53 to 68) <= (53 to 68 => ex3_eac_sel_p1(0) ); + ex3_sel_a3(69 to 84) <= (69 to 84 => ex3_eac_sel_p1(1) ); + ex3_sel_a3(85 to 100) <= (85 to 100 => ex3_eac_sel_p1(2) ); + ex3_sel_a3(101 to 116) <= (101 to 116 => ex3_eac_sel_p1(3) ); + ex3_sel_a3(117 to 132) <= (117 to 132 => ex3_eac_sel_p1(4) ); + ex3_sel_a3(133 to 148) <= (133 to 148 => ex3_eac_sel_p1(5) ); + ex3_sel_a3(149 to 162) <= (149 to 162 => ex3_eac_sel_p1(6) ); + + u_eacmx_i: ex3_s_p0n (53 to 162) <= not( ex3_s_p0(53 to 162) ); + u_eacmx_a1: ex3_res_p0n_b(53 to 162) <= not( ex3_sel_a1(53 to 162) and ex3_s_p0n(53 to 162) ); + u_eacmx_a2: ex3_res_p0_b (53 to 162) <= not( ex3_sel_a2(53 to 162) and ex3_s_p0(53 to 162) ); + u_eacmx_a3: ex3_res_p1_b (53 to 162) <= not( ex3_sel_a3(53 to 162) and ex3_s_p1(53 to 162) ); + u_eacmx: ex3_res (53 to 162) <= not( ex3_res_p0n_b(53 to 162) and ex3_res_p0_b(53 to 162) and ex3_res_p1_b(53 to 162) ); + + + + glbc: entity work.fuq_add_glbc(fuq_add_glbc) port map( + ex3_g16(0 to 6) => ex3_g16(0 to 6) , + ex3_t16(0 to 6) => ex3_t16(0 to 6) , + ex3_inc_all1 => ex3_inc_all1 , + ex3_effsub => ex3_effsub , + ex3_effsub_npz => ex3_effsub_npz , + ex3_effadd_npz => ex3_effadd_npz , + f_alg_ex3_frc_sel_p1 => f_alg_ex3_frc_sel_p1 , + f_alg_ex3_sticky => f_alg_ex3_sticky , + f_pic_ex3_is_nan => f_pic_ex3_is_nan , + f_pic_ex3_is_gt => f_pic_ex3_is_gt , + f_pic_ex3_is_lt => f_pic_ex3_is_lt , + f_pic_ex3_is_eq => f_pic_ex3_is_eq , + f_pic_ex3_cmp_sgnpos => f_pic_ex3_cmp_sgnpos , + f_pic_ex3_cmp_sgnneg => f_pic_ex3_cmp_sgnneg , + ex3_g128(1 to 6) => ex3_g128(1 to 6) , + ex3_g128_b(1 to 6) => ex3_g128_b(1 to 6) , + ex3_t128(1 to 6) => ex3_t128(1 to 6) , + ex3_t128_b(1 to 6) => ex3_t128_b(1 to 6) , + ex3_flip_inc_p0 => ex3_flip_inc_p0 , + ex3_flip_inc_p1 => ex3_flip_inc_p1 , + ex3_inc_sel_p0 => ex3_inc_sel_p0 , + ex3_inc_sel_p1 => ex3_inc_sel_p1 , + ex3_eac_sel_p0n(0 to 6) => ex3_eac_sel_p0n , + ex3_eac_sel_p0 (0 to 6) => ex3_eac_sel_p0 , + ex3_eac_sel_p1 (0 to 6) => ex3_eac_sel_p1 , + ex3_sign_carry => ex3_sign_carry , + ex3_flag_nan_cp1 => ex3_flag_nan_cp1 , + ex3_flag_gt_cp1 => ex3_flag_gt_cp1 , + ex3_flag_lt_cp1 => ex3_flag_lt_cp1 , + ex3_flag_eq_cp1 => ex3_flag_eq_cp1 , + ex3_flag_nan => ex3_flag_nan , + ex3_flag_gt => ex3_flag_gt , + ex3_flag_lt => ex3_flag_lt , + ex3_flag_eq => ex3_flag_eq ); + + + + + ex4_res_hi_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 53, btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd , + gd => gnd , + LCLK => add_ex4_lclk , + D1CLK => add_ex4_d1clk , + D2CLK => add_ex4_d2clk , + SCANIN => ex4_res_si(0 to 52) , + SCANOUT => ex4_res_so(0 to 52) , + D => ex3_res(0 to 52) , + QB => ex4_res_l2_b(0 to 52) ); + + + ex4_res_lo_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 110, btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd , + gd => gnd , + LCLK => add_ex4_lclk , + D1CLK => add_ex4_d1clk , + D2CLK => add_ex4_d2clk , + SCANIN => ex4_res_si(53 to 162) , + SCANOUT => ex4_res_so(53 to 162) , + D => ex3_res(53 to 162) , + QB => ex4_res_l2_b(53 to 162) ); + + ex4_res (0 to 162) <= not ex4_res_l2_b(0 to 162) ; +a_oinv: ex4_res_b(0 to 162) <= not ex4_res (0 to 162); +a_obuf: f_add_ex4_res (0 to 162) <= not ex4_res_b(0 to 162) ; + + ex4_cmp_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 10, btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd , + gd => gnd , + LCLK => add_ex4_lclk , + D1CLK => add_ex4_d1clk , + D2CLK => add_ex4_d2clk , + SCANIN => ex4_cmp_si , + SCANOUT => ex4_cmp_so , + D( 0) => ex3_flag_lt , + D( 1) => ex3_flag_lt_cp1 , + D( 2) => ex3_flag_gt , + D( 3) => ex3_flag_gt_cp1 , + D( 4) => ex3_flag_eq , + D( 5) => ex3_flag_eq_cp1 , + D( 6) => ex3_flag_nan , + D( 7) => ex3_flag_nan_cp1 , + D( 8) => ex3_sign_carry , + D( 9) => f_alg_ex3_sticky , + QB( 0) => ex4_flag_lt_b , + QB( 1) => ex4_fpcc_iu_b(0) , + QB( 2) => ex4_flag_gt_b , + QB( 3) => ex4_fpcc_iu_b(1) , + QB( 4) => ex4_flag_eq_b , + QB( 5) => ex4_fpcc_iu_b(2) , + QB( 6) => ex4_flag_nan_b , + QB( 7) => ex4_fpcc_iu_b(3) , + QB( 8) => ex4_sign_carry_b , + QB( 9) => ex4_sticky_b ); + + + f_add_ex4_flag_nan <= not ex4_flag_nan_b ; + f_add_ex4_flag_gt <= not ex4_flag_gt_b ; + f_add_ex4_flag_lt <= not ex4_flag_lt_b ; + f_add_ex4_flag_eq <= not ex4_flag_eq_b ; + f_add_ex4_fpcc_iu(0 to 3) <= not ex4_fpcc_iu_b(0 to 3) ; + f_add_ex4_sign_carry <= not ex4_sign_carry_b ; + f_add_ex4_sticky <= not ex4_sticky_b ; + + + f_add_ex4_to_int_ovf_wd(0) <= ex4_res(130) ; + f_add_ex4_to_int_ovf_wd(1) <= ex4_res(131) ; + f_add_ex4_to_int_ovf_dw(0) <= ex4_res(98) ; + f_add_ex4_to_int_ovf_dw(1) <= ex4_res(99) ; + + + + + + act_si (0 to 8) <= act_so (1 to 8) & f_add_si ; + ex4_res_si (0 to 162) <= ex4_res_so (1 to 162) & act_so(0); + ex4_cmp_si (0 to 9) <= ex4_cmp_so (1 to 9) & ex4_res_so(0); + f_add_so <= ex4_cmp_so (0) ; + +end; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_add_all1.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_add_all1.vhdl new file mode 100644 index 0000000..d59fea8 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_add_all1.vhdl @@ -0,0 +1,124 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; use ieee.std_logic_1164.all ; +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + +entity fuq_add_all1 is port( + ex3_inc_byt_c_b :in std_ulogic_vector(0 to 6); + ex3_inc_byt_c_glb :out std_ulogic_vector(1 to 6); + ex3_inc_byt_c_glb_b :out std_ulogic_vector(1 to 6); + ex3_inc_all1 :out std_ulogic + ); + + + +END fuq_add_all1; + + +ARCHITECTURE fuq_add_all1 OF fuq_add_all1 IS + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal ex3_inc_byt_g1 :std_ulogic_vector(0 to 6); + signal ex3_inc_byt_g2_b :std_ulogic_vector(0 to 6); + signal ex3_inc_byt_g4 :std_ulogic_vector(0 to 6); + signal ex3_inc_byt_g8_b :std_ulogic_vector(0 to 6); + signal ex3_inc_byt_g_glb_int :std_ulogic_vector(1 to 6); + + + + + + + + + +BEGIN + + ii: ex3_inc_byt_g1(0 to 6) <= not ex3_inc_byt_c_b(0 to 6); + + g26: ex3_inc_byt_g2_b(6) <= not( ex3_inc_byt_g1(6) ); + g25: ex3_inc_byt_g2_b(5) <= not( ex3_inc_byt_g1(5) and ex3_inc_byt_g1(6) ); + g24: ex3_inc_byt_g2_b(4) <= not( ex3_inc_byt_g1(4) and ex3_inc_byt_g1(5) ); + g23: ex3_inc_byt_g2_b(3) <= not( ex3_inc_byt_g1(3) and ex3_inc_byt_g1(4) ); + g22: ex3_inc_byt_g2_b(2) <= not( ex3_inc_byt_g1(2) and ex3_inc_byt_g1(3) ); + g21: ex3_inc_byt_g2_b(1) <= not( ex3_inc_byt_g1(1) and ex3_inc_byt_g1(2) ); + g20: ex3_inc_byt_g2_b(0) <= not( ex3_inc_byt_g1(0) and ex3_inc_byt_g1(1) ); + + g46: ex3_inc_byt_g4(6) <= not( ex3_inc_byt_g2_b(6) ); + g45: ex3_inc_byt_g4(5) <= not( ex3_inc_byt_g2_b(5) ); + g44: ex3_inc_byt_g4(4) <= not( ex3_inc_byt_g2_b(4) or ex3_inc_byt_g2_b(6) ); + g43: ex3_inc_byt_g4(3) <= not( ex3_inc_byt_g2_b(3) or ex3_inc_byt_g2_b(5) ); + g42: ex3_inc_byt_g4(2) <= not( ex3_inc_byt_g2_b(2) or ex3_inc_byt_g2_b(4) ); + g41: ex3_inc_byt_g4(1) <= not( ex3_inc_byt_g2_b(1) or ex3_inc_byt_g2_b(3) ); + g40: ex3_inc_byt_g4(0) <= not( ex3_inc_byt_g2_b(0) or ex3_inc_byt_g2_b(2) ); + + g86: ex3_inc_byt_g8_b(6) <= not( ex3_inc_byt_g4(6) ); + g85: ex3_inc_byt_g8_b(5) <= not( ex3_inc_byt_g4(5) ); + g84: ex3_inc_byt_g8_b(4) <= not( ex3_inc_byt_g4(4) ); + g83: ex3_inc_byt_g8_b(3) <= not( ex3_inc_byt_g4(3) ); + g82: ex3_inc_byt_g8_b(2) <= not( ex3_inc_byt_g4(2) and ex3_inc_byt_g4(6) ); + g81: ex3_inc_byt_g8_b(1) <= not( ex3_inc_byt_g4(1) and ex3_inc_byt_g4(5) ); + g80: ex3_inc_byt_g8_b(0) <= not( ex3_inc_byt_g4(0) and ex3_inc_byt_g4(4) ); + + all1: ex3_inc_all1 <= not ex3_inc_byt_g8_b(0); + iop1: ex3_inc_byt_c_glb(1) <= not ex3_inc_byt_g8_b(1); + iop2: ex3_inc_byt_c_glb(2) <= not ex3_inc_byt_g8_b(2); + iop3: ex3_inc_byt_c_glb(3) <= not ex3_inc_byt_g8_b(3); + iop4: ex3_inc_byt_c_glb(4) <= not ex3_inc_byt_g8_b(4); + iop5: ex3_inc_byt_c_glb(5) <= not ex3_inc_byt_g8_b(5); + iop6: ex3_inc_byt_c_glb(6) <= not ex3_inc_byt_g8_b(6); + + ionn1: ex3_inc_byt_g_glb_int(1) <= not ex3_inc_byt_g8_b(1); + ionn2: ex3_inc_byt_g_glb_int(2) <= not ex3_inc_byt_g8_b(2); + ionn3: ex3_inc_byt_g_glb_int(3) <= not ex3_inc_byt_g8_b(3); + ionn4: ex3_inc_byt_g_glb_int(4) <= not ex3_inc_byt_g8_b(4); + ionn5: ex3_inc_byt_g_glb_int(5) <= not ex3_inc_byt_g8_b(5); + ionn6: ex3_inc_byt_g_glb_int(6) <= not ex3_inc_byt_g8_b(6); + + ion1: ex3_inc_byt_c_glb_b(1) <= not ex3_inc_byt_g_glb_int(1) ; + ion2: ex3_inc_byt_c_glb_b(2) <= not ex3_inc_byt_g_glb_int(2) ; + ion3: ex3_inc_byt_c_glb_b(3) <= not ex3_inc_byt_g_glb_int(3) ; + ion4: ex3_inc_byt_c_glb_b(4) <= not ex3_inc_byt_g_glb_int(4) ; + ion5: ex3_inc_byt_c_glb_b(5) <= not ex3_inc_byt_g_glb_int(5) ; + ion6: ex3_inc_byt_c_glb_b(6) <= not ex3_inc_byt_g_glb_int(6) ; + + + +END; + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_add_glbc.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_add_glbc.vhdl new file mode 100644 index 0000000..f7bf417 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_add_glbc.vhdl @@ -0,0 +1,605 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; use ieee.std_logic_1164.all ; +library ibm; + + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + +entity fuq_add_glbc is port( + ex3_g16 :in std_ulogic_vector(0 to 6); + ex3_t16 :in std_ulogic_vector(0 to 6); + + ex3_inc_all1 :in std_ulogic; + ex3_effsub :in std_ulogic; + ex3_effsub_npz :in std_ulogic; + ex3_effadd_npz :in std_ulogic; + f_alg_ex3_frc_sel_p1 :in std_ulogic; + f_alg_ex3_sticky :in std_ulogic; + f_pic_ex3_is_nan :in std_ulogic; + f_pic_ex3_is_gt :in std_ulogic; + f_pic_ex3_is_lt :in std_ulogic; + f_pic_ex3_is_eq :in std_ulogic; + f_pic_ex3_cmp_sgnpos :in std_ulogic; + f_pic_ex3_cmp_sgnneg :in std_ulogic; + ex3_g128 :out std_ulogic_vector(1 to 6); + ex3_g128_b :out std_ulogic_vector(1 to 6); + ex3_t128 :out std_ulogic_vector(1 to 6); + ex3_t128_b :out std_ulogic_vector(1 to 6); + ex3_flip_inc_p0 :out std_ulogic; + ex3_flip_inc_p1 :out std_ulogic; + ex3_inc_sel_p0 :out std_ulogic; + ex3_inc_sel_p1 :out std_ulogic; + ex3_eac_sel_p0n :out std_ulogic_vector(0 to 6); + ex3_eac_sel_p0 :out std_ulogic_vector(0 to 6); + ex3_eac_sel_p1 :out std_ulogic_vector(0 to 6); + + ex3_sign_carry :out std_ulogic; + ex3_flag_nan_cp1 :out std_ulogic; + ex3_flag_gt_cp1 :out std_ulogic; + ex3_flag_lt_cp1 :out std_ulogic; + ex3_flag_eq_cp1 :out std_ulogic; + ex3_flag_nan :out std_ulogic; + ex3_flag_gt :out std_ulogic; + ex3_flag_lt :out std_ulogic; + ex3_flag_eq :out std_ulogic + ); + + + +END fuq_add_glbc; + + +ARCHITECTURE fuq_add_glbc OF fuq_add_glbc IS + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + + signal cp0_g32_01_b, cp0_g32_23_b, cp0_g32_45_b, cp0_g32_66_b :std_ulogic; + signal cp0_t32_01_b , cp0_t32_23_b, cp0_t32_45_b, cp0_t32_66_b :std_ulogic; + signal cp0_g64_03, cp0_g64_46, cp0_t64_03, cp0_t64_46 :std_ulogic; + signal cp0_g128_06_b, cp0_t128_06_b :std_ulogic; + signal cp0_all1_b, cp0_all1_p, cp0_co_p0, cp0_co_p1 :std_ulogic; + signal cp0_flip_inc_p1_b, ex3_inc_sel_p0_b, ex3_sign_carry_b :std_ulogic; + signal ex3_my_gt_b, ex3_my_lt , ex3_my_eq_b :std_ulogic; + signal ex3_my_gt , ex3_my_eq :std_ulogic; + signal ex3_gt_pos_b , ex3_gt_neg_b , ex3_lt_pos_b , ex3_lt_neg_b , ex3_eq_eq_b :std_ulogic; + signal ex3_is_gt_b, ex3_is_lt_b, ex3_is_eq_b, ex3_sgn_eq :std_ulogic; + + signal cp7_g32_00_b , cp7_g32_12_b , cp7_g32_34_b , cp7_g32_56_b :std_ulogic; + signal cp7_t32_00_b , cp7_t32_12_b , cp7_t32_34_b :std_ulogic; + signal cp7_g64_02 , cp7_g64_36 , cp7_t64_02 :std_ulogic; + signal cp7_g128_06_b :std_ulogic; + signal cp7_all1_b , cp7_all1_p , cp7_co_p0 :std_ulogic; + signal cp7_sel_p0n_x_b , cp7_sel_p0n_y_b :std_ulogic; + signal cp7_sel_p0_b , cp7_sel_p1_b :std_ulogic; + signal cp7_sub_sticky , cp7_sub_stickyn :std_ulogic; + signal cp7_add_frcp1_b , cp7_add_frcp0_b :std_ulogic; + + signal cp6_g32_00_b , cp6_g32_12_b , cp6_g32_34_b , cp6_g32_56_b :std_ulogic; + signal cp6_t32_00_b , cp6_t32_12_b , cp6_t32_34_b :std_ulogic; + signal cp6_g64_02 , cp6_g64_36 , cp6_t64_02 :std_ulogic; + signal cp6_g128_06_b :std_ulogic; + signal cp6_all1_b , cp6_all1_p , cp6_co_p0 :std_ulogic; + signal cp6_sel_p0n_x_b , cp6_sel_p0n_y_b :std_ulogic; + signal cp6_sel_p0_b , cp6_sel_p1_b :std_ulogic; + signal cp6_sub_sticky , cp6_sub_stickyn :std_ulogic; + signal cp6_add_frcp1_b , cp6_add_frcp0_b :std_ulogic; + + signal cp5_g32_00_b , cp5_g32_12_b , cp5_g32_34_b , cp5_g32_56_b :std_ulogic; + signal cp5_t32_00_b , cp5_t32_12_b , cp5_t32_34_b , cp5_t32_56_b :std_ulogic; + signal cp5_g64_02 , cp5_g64_36 , cp5_t64_02 :std_ulogic; + signal cp5_g128_06_b :std_ulogic; + signal cp5_all1_b , cp5_all1_p , cp5_co_p0 :std_ulogic; + signal cp5_sel_p0n_x_b , cp5_sel_p0n_y_b :std_ulogic; + signal cp5_sel_p0_b , cp5_sel_p1_b :std_ulogic; + signal cp5_sub_sticky , cp5_sub_stickyn :std_ulogic; + signal cp5_add_frcp1_b , cp5_add_frcp0_b :std_ulogic; + + + + signal cp4_g32_01_b, cp4_g32_23_b, cp4_g32_45_b, cp4_g32_66_b :std_ulogic; + signal cp4_t32_01_b , cp4_t32_23_b, cp4_t32_45_b, cp4_t32_66_b :std_ulogic; + signal cp4_g64_03, cp4_g64_46, cp4_t64_03, cp4_t64_46 :std_ulogic; + signal cp4_g128_06_b :std_ulogic; + signal cp4_all1_b , cp4_all1_p , cp4_co_p0 :std_ulogic; + signal cp4_sel_p0n_x_b , cp4_sel_p0n_y_b :std_ulogic; + signal cp4_sel_p0_b , cp4_sel_p1_b :std_ulogic; + signal cp4_sub_sticky , cp4_sub_stickyn :std_ulogic; + signal cp4_add_frcp1_b , cp4_add_frcp0_b :std_ulogic; + + + signal cp3_g32_00_b , cp3_g32_12_b , cp3_g32_34_b , cp3_g32_56_b :std_ulogic; + signal cp3_t32_00_b , cp3_t32_12_b , cp3_t32_34_b , cp3_t32_56_b :std_ulogic; + signal cp3_g64_02 , cp3_g64_36 , cp3_t64_02 , cp3_t64_36 :std_ulogic; + signal cp3_g128_06_b :std_ulogic; + signal cp3_all1_b , cp3_all1_p , cp3_co_p0 :std_ulogic; + signal cp3_sel_p0n_x_b , cp3_sel_p0n_y_b :std_ulogic; + signal cp3_sel_p0_b , cp3_sel_p1_b :std_ulogic; + signal cp3_sub_sticky , cp3_sub_stickyn :std_ulogic; + signal cp3_add_frcp1_b , cp3_add_frcp0_b :std_ulogic; + + signal cp2_g32_01_b, cp2_g32_23_b, cp2_g32_45_b, cp2_g32_66_b :std_ulogic; + signal cp2_t32_01_b , cp2_t32_23_b, cp2_t32_45_b, cp2_t32_66_b :std_ulogic; + signal cp2_g64_03, cp2_g64_46, cp2_t64_03, cp2_t64_46 :std_ulogic; + signal cp2_g128_06_b :std_ulogic; + signal cp2_all1_b , cp2_all1_p , cp2_co_p0 :std_ulogic; + signal cp2_sel_p0n_x_b , cp2_sel_p0n_y_b :std_ulogic; + signal cp2_sel_p0_b , cp2_sel_p1_b :std_ulogic; + signal cp2_sub_sticky , cp2_sub_stickyn :std_ulogic; + signal cp2_add_frcp1_b , cp2_add_frcp0_b :std_ulogic; + + signal cp1_g32_01_b, cp1_g32_23_b, cp1_g32_45_b, cp1_g32_66_b :std_ulogic; + signal cp1_t32_01_b , cp1_t32_23_b, cp1_t32_45_b, cp1_t32_66_b :std_ulogic; + signal cp1_g64_03, cp1_g64_46, cp1_t64_03, cp1_t64_46 :std_ulogic; + signal cp1_g128_06_b :std_ulogic; + signal cp1_all1_b , cp1_all1_p , cp1_co_p0 :std_ulogic; + signal cp1_sel_p0n_x_b , cp1_sel_p0n_y_b :std_ulogic; + signal cp1_sel_p0_b , cp1_sel_p1_b :std_ulogic; + signal cp1_sub_sticky , cp1_sub_stickyn :std_ulogic; + signal cp1_add_frcp1_b , cp1_add_frcp0_b :std_ulogic; + +signal cp1_g32_11_b, cp1_t32_11_b, cp1_g64_13, cp1_t64_13, cp1_g128_16_b, cp1_t128_16_b :std_ulogic; +signal cp2_g64_23, cp2_t64_23, cp2_g128_26_b, cp2_t128_26_b :std_ulogic; +signal cp3_g128_36_b, cp3_t128_36_b :std_ulogic; +signal cp4_g128_46_b, cp4_t128_46_b :std_ulogic; +signal cp5_g64_56, cp5_t64_56, cp5_g128_56_b, cp5_t128_56_b :std_ulogic; +signal cp6_g32_66_b, cp6_t32_66_b :std_ulogic; + +signal cp1_g128_16, cp1_t128_16 :std_ulogic; +signal cp2_g128_26, cp2_t128_26 :std_ulogic; +signal cp3_g128_36, cp3_t128_36 :std_ulogic; +signal cp4_g128_46, cp4_t128_46 :std_ulogic; +signal cp5_g128_56, cp5_t128_56 :std_ulogic; +signal cp6_g128_66, cp6_t128_66 :std_ulogic; + + + + + + + + + + + +BEGIN + + + + +ucp0_g32_01: cp0_g32_01_b <= not( ex3_g16(0) or ( ex3_t16(0) and ex3_g16(1) ) ); +ucp0_g32_23: cp0_g32_23_b <= not( ex3_g16(2) or ( ex3_t16(2) and ex3_g16(3) ) ); +ucp0_g32_45: cp0_g32_45_b <= not( ex3_g16(4) or ( ex3_t16(4) and ex3_g16(5) ) ); +ucp0_g32_66: cp0_g32_66_b <= not( ex3_g16(6) ); + +ucp0_t32_01: cp0_t32_01_b <= not( ex3_t16(0) and ex3_t16(1) ); +ucp0_t32_23: cp0_t32_23_b <= not( ex3_t16(2) and ex3_t16(3) ); +ucp0_t32_45: cp0_t32_45_b <= not( ex3_t16(4) and ex3_t16(5) ); +ucp0_t32_66: cp0_t32_66_b <= not( ex3_t16(6) ); + +ucp0_g64_03: cp0_g64_03 <= not( cp0_g32_01_b and (cp0_t32_01_b or cp0_g32_23_b) ); +ucp0_g64_46: cp0_g64_46 <= not( cp0_g32_45_b and (cp0_t32_45_b or cp0_g32_66_b) ); + +ucp0_t64_03: cp0_t64_03 <= not( cp0_t32_01_b or cp0_t32_23_b ); +ucp0_t64_46: cp0_t64_46 <= not( cp0_g32_45_b and (cp0_t32_45_b or cp0_t32_66_b) ); + +ucp0_g128_06: cp0_g128_06_b <= not( cp0_g64_03 or ( cp0_t64_03 and cp0_g64_46 ) ); +ucp0_t128_06: cp0_t128_06_b <= not( cp0_g64_03 or ( cp0_t64_03 and cp0_t64_46 ) ); + +ucp0_all1n: cp0_all1_b <= not ex3_inc_all1 ; +ucp0_all1p: cp0_all1_p <= not cp0_all1_b ; +ucp0_co_p0: cp0_co_p0 <= not( cp0_g128_06_b ) ; +ucp0_co_p1: cp0_co_p1 <= not( cp0_t128_06_b ) ; + + + + ex3_flip_inc_p0 <= ex3_effsub; +ucp0_f1in: cp0_flip_inc_p1_b <= not( ex3_effsub and cp0_all1_b ); +ucp0_f1i: ex3_flip_inc_p1 <= not( cp0_flip_inc_p1_b ); + +ucp0_s1i: ex3_inc_sel_p1 <= not cp0_g128_06_b ; +ucp0_s0in: ex3_inc_sel_p0_b <= not cp0_g128_06_b ; +ucp0_s0i: ex3_inc_sel_p0 <= not ex3_inc_sel_p0_b; + + +ucp0_sgn0: ex3_sign_carry_b <= not( ex3_effsub and cp0_all1_p and cp0_co_p0 ); +ucp0_sgn1: ex3_sign_carry <= not( ex3_sign_carry_b ); + + +ucp0_my_gtn: ex3_my_gt_b <= not( cp0_co_p0 and cp0_all1_p ); +ucp0_my_lt: ex3_my_lt <= not( cp0_co_p1 and cp0_all1_p ); +ucp0_my_eqb: ex3_my_eq_b <= not( cp0_co_p1 and cp0_all1_p and cp0_g128_06_b ); + +ucp0_my_gt: ex3_my_gt <= not ex3_my_gt_b ; +ucp0_my_eq: ex3_my_eq <= not ex3_my_eq_b ; + +ucp0_gt_pos: ex3_gt_pos_b <= not( ex3_my_gt and f_pic_ex3_cmp_sgnpos); +ucp0_gt_neg: ex3_gt_neg_b <= not( ex3_my_lt and f_pic_ex3_cmp_sgnneg); +ucp0_lt_pos: ex3_lt_pos_b <= not( ex3_my_lt and f_pic_ex3_cmp_sgnpos); +ucp0_lt_neg: ex3_lt_neg_b <= not( ex3_my_gt and f_pic_ex3_cmp_sgnneg); +ucp0_eq_eq: ex3_eq_eq_b <= not( ex3_my_eq and ex3_sgn_eq ); + +ucp0_flg_gt: ex3_flag_gt <= not( ex3_gt_pos_b and ex3_gt_neg_b and ex3_is_gt_b ); +ucp0_flg_gt1: ex3_flag_gt_cp1 <= not( ex3_gt_pos_b and ex3_gt_neg_b and ex3_is_gt_b ); +ucp0_flg_lt: ex3_flag_lt <= not( ex3_lt_pos_b and ex3_lt_neg_b and ex3_is_lt_b ); +ucp0_flg_lt1: ex3_flag_lt_cp1 <= not( ex3_lt_pos_b and ex3_lt_neg_b and ex3_is_lt_b ); +ucp0_flg_eq: ex3_flag_eq <= not( ex3_eq_eq_b and ex3_is_eq_b ); +ucp0_flg_eq1: ex3_flag_eq_cp1 <= not( ex3_eq_eq_b and ex3_is_eq_b ); + + ex3_flag_nan <= f_pic_ex3_is_nan; + ex3_flag_nan_cp1 <= f_pic_ex3_is_nan; + + ex3_is_gt_b <= not( f_pic_ex3_is_gt ); + ex3_is_lt_b <= not( f_pic_ex3_is_lt ); + ex3_is_eq_b <= not( f_pic_ex3_is_eq ); + ex3_sgn_eq <= f_pic_ex3_cmp_sgnpos or f_pic_ex3_cmp_sgnneg ; + + + +ucp1_g32_11: cp1_g32_11_b <= not( ex3_g16(1) ); +ucp1_g32_01: cp1_g32_01_b <= not( ex3_g16(0) or ( ex3_t16(0) and ex3_g16(1) ) ); +ucp1_g32_23: cp1_g32_23_b <= not( ex3_g16(2) or ( ex3_t16(2) and ex3_g16(3) ) ); +ucp1_g32_45: cp1_g32_45_b <= not( ex3_g16(4) or ( ex3_t16(4) and ex3_g16(5) ) ); +ucp1_g32_66: cp1_g32_66_b <= not( ex3_g16(6) ); + +ucp1_t32_11: cp1_t32_11_b <= not( ex3_t16(1) ); +ucp1_t32_01: cp1_t32_01_b <= not( ex3_t16(0) and ex3_t16(1) ); +ucp1_t32_23: cp1_t32_23_b <= not( ex3_t16(2) and ex3_t16(3) ); +ucp1_t32_45: cp1_t32_45_b <= not( ex3_t16(4) and ex3_t16(5) ); +ucp1_t32_66: cp1_t32_66_b <= not( ex3_t16(6) ); + +ucp1_g64_03: cp1_g64_03 <= not( cp1_g32_01_b and (cp1_t32_01_b or cp1_g32_23_b) ); +ucp1_g64_13: cp1_g64_13 <= not( cp1_g32_11_b and (cp1_t32_11_b or cp1_g32_23_b) ); +ucp1_g64_46: cp1_g64_46 <= not( cp1_g32_45_b and (cp1_t32_45_b or cp1_g32_66_b) ); + +ucp1_t64_03: cp1_t64_03 <= not( cp1_t32_01_b or cp1_t32_23_b ); +ucp1_t64_13: cp1_t64_13 <= not( cp1_t32_11_b or cp1_t32_23_b ); +ucp1_t64_46: cp1_t64_46 <= not( cp1_g32_45_b and (cp1_t32_45_b or cp1_t32_66_b) ); + +ucp1_g128_06: cp1_g128_06_b <= not( cp1_g64_03 or ( cp1_t64_03 and cp1_g64_46 ) ); +ucp1_g128_16: cp1_g128_16_b <= not( cp1_g64_13 or ( cp1_t64_13 and cp1_g64_46 ) ); +ucp1_t128_16: cp1_t128_16_b <= not( cp1_g64_13 or ( cp1_t64_13 and cp1_t64_46 ) ); + + +ucp1_cog: ex3_g128(1) <= not( cp1_g128_16_b); +ucp1_cogx: cp1_g128_16 <= not( cp1_g128_16_b); +ucp1_cogb: ex3_g128_b(1) <= not( cp1_g128_16 ); +ucp1_cot: ex3_t128(1) <= not( cp1_t128_16_b); +ucp1_cotx: cp1_t128_16 <= not( cp1_t128_16_b); +ucp1_cotb: ex3_t128_b(1) <= not( cp1_t128_16 ); + +ucp1_all1n: cp1_all1_b <= not ex3_inc_all1 ; +ucp1_all1p: cp1_all1_p <= not cp1_all1_b ; +ucp1_co_p0: cp1_co_p0 <= not( cp1_g128_06_b ) ; + +ucp1_espnx: cp1_sel_p0n_x_b <= not( cp1_all1_b and ex3_effsub_npz); +ucp1_espny: cp1_sel_p0n_y_b <= not( cp1_g128_06_b and ex3_effsub_npz); +ucp1_selp0: cp1_sel_p0_b <= not( cp1_co_p0 and cp1_all1_p and cp1_sub_sticky ); +ucp1_selp1: cp1_sel_p1_b <= not( cp1_co_p0 and cp1_all1_p and cp1_sub_stickyn ); + +ucp1_espn: ex3_eac_sel_p0n(0) <= not( cp1_sel_p0n_x_b and cp1_sel_p0n_y_b); +ucp1_esp0: ex3_eac_sel_p0(0) <= not( cp1_sel_p0_b and cp1_add_frcp0_b); +ucp1_esp1: ex3_eac_sel_p1(0) <= not( cp1_sel_p1_b and cp1_add_frcp1_b); + + cp1_sub_sticky <= ex3_effsub_npz and f_alg_ex3_sticky ; + cp1_sub_stickyn <= ex3_effsub_npz and not f_alg_ex3_sticky ; + cp1_add_frcp1_b <= not( ex3_effadd_npz and f_alg_ex3_frc_sel_p1 ); + cp1_add_frcp0_b <= not( ex3_effadd_npz and not f_alg_ex3_frc_sel_p1 ); + + + +ucp2_g32_01: cp2_g32_01_b <= not( ex3_g16(0) or ( ex3_t16(0) and ex3_g16(1) ) ); +ucp2_g32_23: cp2_g32_23_b <= not( ex3_g16(2) or ( ex3_t16(2) and ex3_g16(3) ) ); +ucp2_g32_45: cp2_g32_45_b <= not( ex3_g16(4) or ( ex3_t16(4) and ex3_g16(5) ) ); +ucp2_g32_66: cp2_g32_66_b <= not( ex3_g16(6) ); + +ucp2_t32_01: cp2_t32_01_b <= not( ex3_t16(0) and ex3_t16(1) ); +ucp2_t32_23: cp2_t32_23_b <= not( ex3_t16(2) and ex3_t16(3) ); +ucp2_t32_45: cp2_t32_45_b <= not( ex3_t16(4) and ex3_t16(5) ); +ucp2_t32_66: cp2_t32_66_b <= not( ex3_t16(6) ); + +ucp2_g64_23: cp2_g64_23 <= not( cp2_g32_23_b ); +ucp2_g64_03: cp2_g64_03 <= not( cp2_g32_01_b and (cp2_t32_01_b or cp2_g32_23_b) ); +ucp2_g64_46: cp2_g64_46 <= not( cp2_g32_45_b and (cp2_t32_45_b or cp2_g32_66_b) ); + +ucp2_t64_23: cp2_t64_23 <= not( cp2_t32_23_b ); +ucp2_t64_03: cp2_t64_03 <= not( cp2_t32_01_b or cp2_t32_23_b ); +ucp2_t64_46: cp2_t64_46 <= not( cp2_g32_45_b and (cp2_t32_45_b or cp2_t32_66_b) ); + +ucp2_g128_06: cp2_g128_06_b <= not( cp2_g64_03 or ( cp2_t64_03 and cp2_g64_46 ) ); +ucp2_g128_26: cp2_g128_26_b <= not( cp2_g64_23 or ( cp2_t64_23 and cp2_g64_46 ) ); +ucp2_t128_26: cp2_t128_26_b <= not( cp2_g64_23 or ( cp2_t64_23 and cp2_t64_46 ) ); + + +ucp2_cog: ex3_g128(2) <= not( cp2_g128_26_b); +ucp2_cogx: cp2_g128_26 <= not( cp2_g128_26_b); +ucp2_cogb: ex3_g128_b(2) <= not( cp2_g128_26 ); +ucp2_cot: ex3_t128(2) <= not( cp2_t128_26_b); +ucp2_cotx: cp2_t128_26 <= not( cp2_t128_26_b); +ucp2_cotb: ex3_t128_b(2) <= not( cp2_t128_26 ); + + +ucp2_all1n: cp2_all1_b <= not ex3_inc_all1 ; +ucp2_all1p: cp2_all1_p <= not cp2_all1_b ; +ucp2_co_p0: cp2_co_p0 <= not( cp2_g128_06_b ) ; + +ucp2_espnx: cp2_sel_p0n_x_b <= not( cp2_all1_b and ex3_effsub_npz); +ucp2_espny: cp2_sel_p0n_y_b <= not( cp2_g128_06_b and ex3_effsub_npz); +ucp2_selp0: cp2_sel_p0_b <= not( cp2_co_p0 and cp2_all1_p and cp2_sub_sticky ); +ucp2_selp1: cp2_sel_p1_b <= not( cp2_co_p0 and cp2_all1_p and cp2_sub_stickyn ); + +ucp2_espn: ex3_eac_sel_p0n(1) <= not( cp2_sel_p0n_x_b and cp2_sel_p0n_y_b); +ucp2_esp0: ex3_eac_sel_p0(1) <= not( cp2_sel_p0_b and cp2_add_frcp0_b); +ucp2_esp1: ex3_eac_sel_p1(1) <= not( cp2_sel_p1_b and cp2_add_frcp1_b); + + cp2_sub_sticky <= ex3_effsub_npz and f_alg_ex3_sticky ; + cp2_sub_stickyn <= ex3_effsub_npz and not f_alg_ex3_sticky ; + cp2_add_frcp1_b <= not( ex3_effadd_npz and f_alg_ex3_frc_sel_p1 ); + cp2_add_frcp0_b <= not( ex3_effadd_npz and not f_alg_ex3_frc_sel_p1 ); + + + +ucp3_g32_00: cp3_g32_00_b <= not( ex3_g16(0) ) ; +ucp3_g32_12: cp3_g32_12_b <= not( ex3_g16(1) or ( ex3_t16(1) and ex3_g16(2) ) ); +ucp3_g32_34: cp3_g32_34_b <= not( ex3_g16(3) or ( ex3_t16(3) and ex3_g16(4) ) ); +ucp3_g32_56: cp3_g32_56_b <= not( ex3_g16(5) or ( ex3_t16(5) and ex3_g16(6) ) ); + +ucp3_t32_00: cp3_t32_00_b <= not( ex3_t16(0) ); +ucp3_t32_12: cp3_t32_12_b <= not( ex3_t16(1) and ex3_t16(2) ); +ucp3_t32_34: cp3_t32_34_b <= not( ex3_t16(3) and ex3_t16(4) ); +ucp3_t32_56: cp3_t32_56_b <= not( ex3_g16(5) or ( ex3_t16(5) and ex3_t16(6) ) ); + +ucp3_g64_02: cp3_g64_02 <= not( cp3_g32_00_b and (cp3_t32_00_b or cp3_g32_12_b) ); +ucp3_g64_36: cp3_g64_36 <= not( cp3_g32_34_b and (cp3_t32_34_b or cp3_g32_56_b) ); + +ucp3_t64_02: cp3_t64_02 <= not( cp3_t32_00_b or cp3_t32_12_b ); +ucp3_t64_36: cp3_t64_36 <= not( cp3_g32_34_b and (cp3_t32_34_b or cp3_t32_56_b) ); + +ucp3_g128_06: cp3_g128_06_b <= not( cp3_g64_02 or ( cp3_t64_02 and cp3_g64_36 ) ); +ucp3_g128_36: cp3_g128_36_b <= not( cp3_g64_36 ); +ucp3_t128_36: cp3_t128_36_b <= not( cp3_t64_36 ); + + +ucp3_cog: ex3_g128(3) <= not( cp3_g128_36_b); +ucp3_cogx: cp3_g128_36 <= not( cp3_g128_36_b); +ucp3_cogb: ex3_g128_b(3) <= not( cp3_g128_36 ); +ucp3_cot: ex3_t128(3) <= not( cp3_t128_36_b); +ucp3_cotx: cp3_t128_36 <= not( cp3_t128_36_b); +ucp3_cotb: ex3_t128_b(3) <= not( cp3_t128_36 ); + + +ucp3_all1n: cp3_all1_b <= not ex3_inc_all1 ; +ucp3_all1p: cp3_all1_p <= not cp3_all1_b ; +ucp3_co_p0: cp3_co_p0 <= not( cp3_g128_06_b ) ; + +ucp3_espnx: cp3_sel_p0n_x_b <= not( cp3_all1_b and ex3_effsub_npz); +ucp3_espny: cp3_sel_p0n_y_b <= not( cp3_g128_06_b and ex3_effsub_npz); +ucp3_selp0: cp3_sel_p0_b <= not( cp3_co_p0 and cp3_all1_p and cp3_sub_sticky ); +ucp3_selp1: cp3_sel_p1_b <= not( cp3_co_p0 and cp3_all1_p and cp3_sub_stickyn ); + +ucp3_espn: ex3_eac_sel_p0n(2) <= not( cp3_sel_p0n_x_b and cp3_sel_p0n_y_b); +ucp3_esp0: ex3_eac_sel_p0(2) <= not( cp3_sel_p0_b and cp3_add_frcp0_b); +ucp3_esp1: ex3_eac_sel_p1(2) <= not( cp3_sel_p1_b and cp3_add_frcp1_b); + + cp3_sub_sticky <= ex3_effsub_npz and f_alg_ex3_sticky ; + cp3_sub_stickyn <= ex3_effsub_npz and not f_alg_ex3_sticky ; + cp3_add_frcp1_b <= not( ex3_effadd_npz and f_alg_ex3_frc_sel_p1 ); + cp3_add_frcp0_b <= not( ex3_effadd_npz and not f_alg_ex3_frc_sel_p1 ); + + + + +ucp4_g32_01: cp4_g32_01_b <= not( ex3_g16(0) or ( ex3_t16(0) and ex3_g16(1) ) ); +ucp4_g32_23: cp4_g32_23_b <= not( ex3_g16(2) or ( ex3_t16(2) and ex3_g16(3) ) ); +ucp4_g32_45: cp4_g32_45_b <= not( ex3_g16(4) or ( ex3_t16(4) and ex3_g16(5) ) ); +ucp4_g32_66: cp4_g32_66_b <= not( ex3_g16(6) ); + +ucp4_t32_01: cp4_t32_01_b <= not( ex3_t16(0) and ex3_t16(1) ); +ucp4_t32_23: cp4_t32_23_b <= not( ex3_t16(2) and ex3_t16(3) ); +ucp4_t32_45: cp4_t32_45_b <= not( ex3_t16(4) and ex3_t16(5) ); +ucp4_t32_66: cp4_t32_66_b <= not( ex3_t16(6) ); + +ucp4_g64_03: cp4_g64_03 <= not( cp4_g32_01_b and (cp4_t32_01_b or cp4_g32_23_b) ); +ucp4_g64_46: cp4_g64_46 <= not( cp4_g32_45_b and (cp4_t32_45_b or cp4_g32_66_b) ); + +ucp4_t64_03: cp4_t64_03 <= not( cp4_t32_01_b or cp4_t32_23_b ); +ucp4_t64_46: cp4_t64_46 <= not( cp4_g32_45_b and (cp4_t32_45_b or cp4_t32_66_b) ); + +ucp4_g128_06: cp4_g128_06_b <= not( cp4_g64_03 or ( cp4_t64_03 and cp4_g64_46 ) ); +ucp4_g128_46: cp4_g128_46_b <= not( cp4_g64_46 ); +ucp4_t128_46: cp4_t128_46_b <= not( cp4_t64_46 ); + +ucp4_cog: ex3_g128(4) <= not( cp4_g128_46_b); +ucp4_cogx: cp4_g128_46 <= not( cp4_g128_46_b); +ucp4_cogb: ex3_g128_b(4) <= not( cp4_g128_46 ); +ucp4_cot: ex3_t128(4) <= not( cp4_t128_46_b); +ucp4_cotx: cp4_t128_46 <= not( cp4_t128_46_b); +ucp4_cotb: ex3_t128_b(4) <= not( cp4_t128_46 ); + +ucp4_all1n: cp4_all1_b <= not ex3_inc_all1 ; +ucp4_all1p: cp4_all1_p <= not cp4_all1_b ; +ucp4_co_p0: cp4_co_p0 <= not( cp4_g128_06_b ) ; + +ucp4_espnx: cp4_sel_p0n_x_b <= not( cp4_all1_b and ex3_effsub_npz); +ucp4_espny: cp4_sel_p0n_y_b <= not( cp4_g128_06_b and ex3_effsub_npz); +ucp4_selp0: cp4_sel_p0_b <= not( cp4_co_p0 and cp4_all1_p and cp4_sub_sticky ); +ucp4_selp1: cp4_sel_p1_b <= not( cp4_co_p0 and cp4_all1_p and cp4_sub_stickyn ); + +ucp4_espn: ex3_eac_sel_p0n(3) <= not( cp4_sel_p0n_x_b and cp4_sel_p0n_y_b); +ucp4_esp0: ex3_eac_sel_p0(3) <= not( cp4_sel_p0_b and cp4_add_frcp0_b); +ucp4_esp1: ex3_eac_sel_p1(3) <= not( cp4_sel_p1_b and cp4_add_frcp1_b); + + cp4_sub_sticky <= ex3_effsub_npz and f_alg_ex3_sticky ; + cp4_sub_stickyn <= ex3_effsub_npz and not f_alg_ex3_sticky ; + cp4_add_frcp1_b <= not( ex3_effadd_npz and f_alg_ex3_frc_sel_p1 ); + cp4_add_frcp0_b <= not( ex3_effadd_npz and not f_alg_ex3_frc_sel_p1 ); + + + +ucp5_g32_00: cp5_g32_00_b <= not( ex3_g16(0) ); +ucp5_g32_12: cp5_g32_12_b <= not( ex3_g16(1) or ( ex3_t16(1) and ex3_g16(2) ) ); +ucp5_g32_34: cp5_g32_34_b <= not( ex3_g16(3) or ( ex3_t16(3) and ex3_g16(4) ) ); +ucp5_g32_56: cp5_g32_56_b <= not( ex3_g16(5) or ( ex3_t16(5) and ex3_g16(6) ) ); + +ucp5_t32_00: cp5_t32_00_b <= not( ex3_t16(0) ); +ucp5_t32_12: cp5_t32_12_b <= not( ex3_t16(1) and ex3_t16(2) ); +ucp5_t32_34: cp5_t32_34_b <= not( ex3_t16(3) and ex3_t16(4) ); +ucp5_t32_56: cp5_t32_56_b <= not( ex3_g16(5) or ( ex3_t16(5) and ex3_t16(6) ) ); + + +ucp5_g64_02: cp5_g64_02 <= not( cp5_g32_00_b and (cp5_t32_00_b or cp5_g32_12_b) ); +ucp5_g64_36: cp5_g64_36 <= not( cp5_g32_34_b and (cp5_t32_34_b or cp5_g32_56_b) ); +ucp5_g64_56: cp5_g64_56 <= not( cp5_g32_56_b ); + +ucp5_t64_02: cp5_t64_02 <= not( cp5_t32_00_b or cp5_t32_12_b ); +ucp5_t64_56: cp5_t64_56 <= not( cp5_t32_56_b ); + +ucp5_g128_06: cp5_g128_06_b <= not( cp5_g64_02 or ( cp5_t64_02 and cp5_g64_36 ) ); +ucp5_g128_56: cp5_g128_56_b <= not( cp5_g64_56 ); +ucp5_t128_56: cp5_t128_56_b <= not( cp5_t64_56 ); + + +ucp5_cog: ex3_g128(5) <= not( cp5_g128_56_b); +ucp5_cogx: cp5_g128_56 <= not( cp5_g128_56_b); +ucp5_cogb: ex3_g128_b(5) <= not( cp5_g128_56 ); +ucp5_cot: ex3_t128(5) <= not( cp5_t128_56_b); +ucp5_cotx: cp5_t128_56 <= not( cp5_t128_56_b); +ucp5_cotb: ex3_t128_b(5) <= not( cp5_t128_56 ); + +ucp5_all1n: cp5_all1_b <= not ex3_inc_all1 ; +ucp5_all1p: cp5_all1_p <= not cp5_all1_b ; +ucp5_co_p0: cp5_co_p0 <= not( cp5_g128_06_b ) ; + +ucp5_espnx: cp5_sel_p0n_x_b <= not( cp5_all1_b and ex3_effsub_npz); +ucp5_espny: cp5_sel_p0n_y_b <= not( cp5_g128_06_b and ex3_effsub_npz); +ucp5_selp0: cp5_sel_p0_b <= not( cp5_co_p0 and cp5_all1_p and cp5_sub_sticky ); +ucp5_selp1: cp5_sel_p1_b <= not( cp5_co_p0 and cp5_all1_p and cp5_sub_stickyn ); + +ucp5_espn: ex3_eac_sel_p0n(4) <= not( cp5_sel_p0n_x_b and cp5_sel_p0n_y_b); +ucp5_esp0: ex3_eac_sel_p0(4) <= not( cp5_sel_p0_b and cp5_add_frcp0_b); +ucp5_esp1: ex3_eac_sel_p1(4) <= not( cp5_sel_p1_b and cp5_add_frcp1_b); + + cp5_sub_sticky <= ex3_effsub_npz and f_alg_ex3_sticky ; + cp5_sub_stickyn <= ex3_effsub_npz and not f_alg_ex3_sticky ; + cp5_add_frcp1_b <= not( ex3_effadd_npz and f_alg_ex3_frc_sel_p1 ); + cp5_add_frcp0_b <= not( ex3_effadd_npz and not f_alg_ex3_frc_sel_p1 ); + + + +ucp6_g32_00: cp6_g32_00_b <= not( ex3_g16(0) ); +ucp6_g32_12: cp6_g32_12_b <= not( ex3_g16(1) or ( ex3_t16(1) and ex3_g16(2) ) ); +ucp6_g32_34: cp6_g32_34_b <= not( ex3_g16(3) or ( ex3_t16(3) and ex3_g16(4) ) ); +ucp6_g32_56: cp6_g32_56_b <= not( ex3_g16(5) or ( ex3_t16(5) and ex3_g16(6) ) ); +ucp6_g32_66: cp6_g32_66_b <= not( ex3_g16(6) ); + +ucp6_t32_00: cp6_t32_00_b <= not( ex3_t16(0) ); +ucp6_t32_12: cp6_t32_12_b <= not( ex3_t16(1) and ex3_t16(2) ); +ucp6_t32_34: cp6_t32_34_b <= not( ex3_t16(3) and ex3_t16(4) ); +ucp6_t32_66: cp6_t32_66_b <= not( ex3_t16(6) ); + +ucp6_g64_02: cp6_g64_02 <= not( cp6_g32_00_b and (cp6_t32_00_b or cp6_g32_12_b) ); +ucp6_g64_36: cp6_g64_36 <= not( cp6_g32_34_b and (cp6_t32_34_b or cp6_g32_56_b) ); + +ucp6_t64_02: cp6_t64_02 <= not( cp6_t32_00_b or cp6_t32_12_b ); + +ucp6_g128_06: cp6_g128_06_b <= not( cp6_g64_02 or ( cp6_t64_02 and cp6_g64_36 ) ); + + +ucp6_cog: ex3_g128(6) <= not( cp6_g32_66_b ); +ucp6_cogx: cp6_g128_66 <= not( cp6_g32_66_b ); +ucp6_cogb: ex3_g128_b(6) <= not( cp6_g128_66 ); +ucp6_cot: ex3_t128(6) <= not( cp6_t32_66_b ); +ucp6_cotx: cp6_t128_66 <= not( cp6_t32_66_b ); +ucp6_cotb: ex3_t128_b(6) <= not( cp6_t128_66 ); + + +ucp6_all1n: cp6_all1_b <= not ex3_inc_all1 ; +ucp6_all1p: cp6_all1_p <= not cp6_all1_b ; +ucp6_co_p0: cp6_co_p0 <= not( cp6_g128_06_b ) ; + +ucp6_espnx: cp6_sel_p0n_x_b <= not( cp6_all1_b and ex3_effsub_npz); +ucp6_espny: cp6_sel_p0n_y_b <= not( cp6_g128_06_b and ex3_effsub_npz); +ucp6_selp0: cp6_sel_p0_b <= not( cp6_co_p0 and cp6_all1_p and cp6_sub_sticky ); +ucp6_selp1: cp6_sel_p1_b <= not( cp6_co_p0 and cp6_all1_p and cp6_sub_stickyn ); + +ucp6_espn: ex3_eac_sel_p0n(5) <= not( cp6_sel_p0n_x_b and cp6_sel_p0n_y_b); +ucp6_esp0: ex3_eac_sel_p0(5) <= not( cp6_sel_p0_b and cp6_add_frcp0_b); +ucp6_esp1: ex3_eac_sel_p1(5) <= not( cp6_sel_p1_b and cp6_add_frcp1_b); + + cp6_sub_sticky <= ex3_effsub_npz and f_alg_ex3_sticky ; + cp6_sub_stickyn <= ex3_effsub_npz and not f_alg_ex3_sticky ; + cp6_add_frcp1_b <= not( ex3_effadd_npz and f_alg_ex3_frc_sel_p1 ); + cp6_add_frcp0_b <= not( ex3_effadd_npz and not f_alg_ex3_frc_sel_p1 ); + + + +ucp7_g32_00: cp7_g32_00_b <= not( ex3_g16(0) ) ; +ucp7_g32_12: cp7_g32_12_b <= not( ex3_g16(1) or ( ex3_t16(1) and ex3_g16(2) ) ); +ucp7_g32_34: cp7_g32_34_b <= not( ex3_g16(3) or ( ex3_t16(3) and ex3_g16(4) ) ); +ucp7_g32_56: cp7_g32_56_b <= not( ex3_g16(5) or ( ex3_t16(5) and ex3_g16(6) ) ); + +ucp7_t32_00: cp7_t32_00_b <= not( ex3_t16(0) ); +ucp7_t32_12: cp7_t32_12_b <= not( ex3_t16(1) and ex3_t16(2) ); +ucp7_t32_34: cp7_t32_34_b <= not( ex3_t16(3) and ex3_t16(4) ); + + +ucp7_g64_02: cp7_g64_02 <= not( cp7_g32_00_b and (cp7_t32_00_b or cp7_g32_12_b) ); +ucp7_g64_36: cp7_g64_36 <= not( cp7_g32_34_b and (cp7_t32_34_b or cp7_g32_56_b) ); + +ucp7_t64_02: cp7_t64_02 <= not( cp7_t32_00_b or cp7_t32_12_b ); + +ucp7_g128_06: cp7_g128_06_b <= not( cp7_g64_02 or ( cp7_t64_02 and cp7_g64_36 ) ); + +ucp7_all1n: cp7_all1_b <= not ex3_inc_all1 ; +ucp7_all1p: cp7_all1_p <= not cp7_all1_b ; +ucp7_co_p0: cp7_co_p0 <= not( cp7_g128_06_b ) ; + +ucp7_espnx: cp7_sel_p0n_x_b <= not( cp7_all1_b and ex3_effsub_npz); +ucp7_espny: cp7_sel_p0n_y_b <= not( cp7_g128_06_b and ex3_effsub_npz); +ucp7_selp0: cp7_sel_p0_b <= not( cp7_co_p0 and cp7_all1_p and cp7_sub_sticky ); +ucp7_selp1: cp7_sel_p1_b <= not( cp7_co_p0 and cp7_all1_p and cp7_sub_stickyn ); + +ucp7_espn: ex3_eac_sel_p0n(6) <= not( cp7_sel_p0n_x_b and cp7_sel_p0n_y_b); +ucp7_esp0: ex3_eac_sel_p0(6) <= not( cp7_sel_p0_b and cp7_add_frcp0_b); +ucp7_esp1: ex3_eac_sel_p1(6) <= not( cp7_sel_p1_b and cp7_add_frcp1_b); + + cp7_sub_sticky <= ex3_effsub_npz and f_alg_ex3_sticky ; + cp7_sub_stickyn <= ex3_effsub_npz and not f_alg_ex3_sticky ; + cp7_add_frcp1_b <= not( ex3_effadd_npz and f_alg_ex3_frc_sel_p1 ); + cp7_add_frcp0_b <= not( ex3_effadd_npz and not f_alg_ex3_frc_sel_p1 ); + +END; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_alg.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_alg.vhdl new file mode 100644 index 0000000..a05b48c --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_alg.vhdl @@ -0,0 +1,958 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + + +entity fuq_alg is +generic( expand_type : integer := 2 ); +port( + + vdd :inout power_logic; + gnd :inout power_logic; + clkoff_b :in std_ulogic; + act_dis :in std_ulogic; + flush :in std_ulogic; + delay_lclkr :in std_ulogic_vector(1 to 3); + mpw1_b :in std_ulogic_vector(1 to 3); + mpw2_b :in std_ulogic_vector(0 to 0); + sg_1 :in std_ulogic; + thold_1 :in std_ulogic; + fpu_enable :in std_ulogic; + nclk :in clk_logic; + + + f_alg_si :in std_ulogic; + f_alg_so :out std_ulogic; + rf1_act :in std_ulogic; + ex1_act :in std_ulogic; + + f_byp_alg_ex1_b_expo :in std_ulogic_vector(1 to 13); + f_byp_alg_ex1_a_expo :in std_ulogic_vector(1 to 13); + f_byp_alg_ex1_c_expo :in std_ulogic_vector(1 to 13); + f_byp_alg_ex1_b_frac :in std_ulogic_vector(0 to 52); + f_byp_alg_ex1_b_sign :in std_ulogic; + + f_fmt_ex1_prod_zero :in std_ulogic; + f_fmt_ex1_b_zero :in std_ulogic; + f_fmt_ex1_pass_sel :in std_ulogic; + f_fmt_ex2_pass_frac :in std_ulogic_vector(0 to 52); + + f_dcd_rf1_sp :in std_ulogic; + f_dcd_rf1_from_integer_b :in std_ulogic; + f_dcd_rf1_to_integer_b :in std_ulogic; + f_dcd_rf1_word_b :in std_ulogic; + f_dcd_rf1_uns_b :in std_ulogic; + + f_pic_ex1_rnd_to_int :in std_ulogic; + f_pic_ex1_frsp_ue1 :in std_ulogic; + f_pic_ex1_effsub_raw :in std_ulogic; + f_pic_ex1_sh_unf_ig_b :in std_ulogic; + f_pic_ex1_sh_unf_do :in std_ulogic; + f_pic_ex1_sh_ovf_ig_b :in std_ulogic; + f_pic_ex1_sh_ovf_do :in std_ulogic; + f_pic_ex2_rnd_nr :in std_ulogic; + f_pic_ex2_rnd_inf_ok :in std_ulogic; + + f_alg_ex1_sign_frmw :out std_ulogic; + f_alg_ex2_byp_nonflip :out std_ulogic; + f_alg_ex2_res :out std_ulogic_vector(0 to 162); + f_alg_ex2_sel_byp :out std_ulogic; + f_alg_ex2_effsub_eac_b :out std_ulogic; + f_alg_ex2_prod_z :out std_ulogic; + f_alg_ex2_sh_unf :out std_ulogic; + f_alg_ex2_sh_ovf :out std_ulogic; + f_alg_ex3_frc_sel_p1 :out std_ulogic; + f_alg_ex3_sticky :out std_ulogic; + f_alg_ex3_int_fr :out std_ulogic; + f_alg_ex3_int_fi :out std_ulogic +); + + + +end fuq_alg; + +architecture fuq_alg of fuq_alg is + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal thold_0_b, thold_0, forcee :std_ulogic; + signal sg_0 :std_ulogic; + signal ex2_act :std_ulogic; + signal spare_unused :std_ulogic_vector(0 to 3); + signal act_so :std_ulogic_vector(0 to 4); + signal act_si :std_ulogic_vector(0 to 4); + signal ex1_ctl_so :std_ulogic_vector(0 to 4); + signal ex1_ctl_si :std_ulogic_vector(0 to 4); + signal ex2_shd_so, ex2_shd_si :std_ulogic_vector(0 to 67); + signal ex2_shc_so, ex2_shc_si :std_ulogic_vector(0 to 24); + signal ex2_ctl_so :std_ulogic_vector(0 to 14); + signal ex2_ctl_si :std_ulogic_vector(0 to 14); + signal ex3_ctl_so :std_ulogic_vector(0 to 10); + signal ex3_ctl_si :std_ulogic_vector(0 to 10); + signal ex1_from_integer :std_ulogic; + signal ex2_from_integer :std_ulogic; + signal ex1_to_integer :std_ulogic; + signal ex1_sel_special, ex1_sel_special_b, ex2_sel_special_b :std_ulogic; + signal ex1_sh_ovf :std_ulogic; + signal ex1_sh_unf_x , ex2_sh_unf_x :std_ulogic; + signal ex1_sel_byp_nonflip :std_ulogic; + signal ex1_sel_byp_nonflip_lze :std_ulogic; + signal ex1_from_integer_neg :std_ulogic; + signal ex1_integer_op :std_ulogic; + signal ex1_to_integer_neg :std_ulogic; + signal ex1_negate :std_ulogic; + signal ex1_effsub_alg :std_ulogic; + signal ex2_sh_unf :std_ulogic; + signal ex2_sel_byp :std_ulogic; + signal ex2_effsub_alg :std_ulogic; + signal ex2_prd_sel_pos_hi :std_ulogic; + signal ex2_prd_sel_neg_hi :std_ulogic; + signal ex2_prd_sel_pos_lo :std_ulogic; + signal ex2_prd_sel_neg_lo :std_ulogic; + signal ex2_prd_sel_pos_lohi :std_ulogic; + signal ex2_prd_sel_neg_lohi :std_ulogic; + signal ex2_byp_sel_pos :std_ulogic; + signal ex2_byp_sel_neg :std_ulogic; + signal ex2_byp_sel_byp_pos :std_ulogic; + signal ex2_byp_sel_byp_neg :std_ulogic; + signal ex2_b_sign :std_ulogic; + signal ex2_to_integer :std_ulogic; + signal ex1_sh_lvl2 :std_ulogic_vector(0 to 67) ; + signal ex2_sh_lvl2, ex2_sh_lvl2_b :std_ulogic_vector(0 to 67) ; + signal ex2_bsha :std_ulogic_vector(6 to 9) ; + signal ex2_sticky_en16_x :std_ulogic_vector(0 to 4) ; + signal ex2_xthrm_6_ns_b :std_ulogic; + signal ex2_xthrm_7_ns_b :std_ulogic; + signal ex2_xthrm_8_b :std_ulogic; + signal ex2_xthrm_8a9_b :std_ulogic; + signal ex2_xthrm_8o9_b :std_ulogic; + signal ex2_xthrm7o8a9 :std_ulogic; + signal ex2_xthrm7o8 :std_ulogic; + signal ex2_xthrm7o8o9 :std_ulogic; + signal ex2_xthrm7a8a9 :std_ulogic; + signal ex2_xthrm_6_ns :std_ulogic; + signal ex2_ge176_b :std_ulogic; + signal ex2_ge160_b :std_ulogic; + signal ex2_ge144_b :std_ulogic; + signal ex2_ge128_b :std_ulogic; + signal ex2_ge112_b :std_ulogic; + signal ex1_bsha_6, ex1_bsha_7, ex1_bsha_8, ex1_bsha_9 :std_ulogic; + signal ex2_bsha_pos :std_ulogic; + signal ex2_sh_lvl3 :std_ulogic_vector(0 to 162) ; + signal ex2_sticky_or16 :std_ulogic_vector(0 to 4) ; + signal ex1_b_zero :std_ulogic ; + signal ex2_b_zero, ex2_b_zero_b :std_ulogic ; + + signal ex1_dp :std_ulogic; + + signal ex2_byp_nonflip_lze :std_ulogic; +signal ex2_sel_byp_nonflip :std_ulogic; +signal ex2_prod_zero :std_ulogic; +signal ex2_sh_ovf_en, ex2_sh_unf_en, ex2_sh_unf_do :std_ulogic; +signal ex2_sh_ovf :std_ulogic; +signal ex2_integer_op :std_ulogic; +signal ex2_negate :std_ulogic; +signal ex2_unf_bz :std_ulogic; +signal ex2_all1_x :std_ulogic; +signal ex2_ovf_pz :std_ulogic; +signal ex2_all1_y :std_ulogic; + signal ex2_sel_special :std_ulogic; + signal rf1_from_integer , rf1_to_integer , rf1_dp :std_ulogic; + signal rf1_uns, rf1_word, ex1_uns, ex1_word :std_ulogic; + signal ex1_word_from, ex2_word_from :std_ulogic; + signal ex2_rnd_to_int :std_ulogic; + signal ex1_sign_from :std_ulogic; + signal ex1_b_frac :std_ulogic_vector(0 to 52); + signal ex1_b_expo :std_ulogic_vector(1 to 13); + signal ex1_b_sign :std_ulogic; + signal ex1_bsha_neg, ex2_bsha_neg : std_ulogic ; + + + signal ex1_lvl1_shdcd000_b :std_ulogic; + signal ex1_lvl1_shdcd001_b :std_ulogic; + signal ex1_lvl1_shdcd002_b :std_ulogic; + signal ex1_lvl1_shdcd003_b :std_ulogic; + signal ex1_lvl2_shdcd000 :std_ulogic; + signal ex1_lvl2_shdcd004 :std_ulogic; + signal ex1_lvl2_shdcd008 :std_ulogic; + signal ex1_lvl2_shdcd012 :std_ulogic; + signal ex1_lvl3_shdcd000 :std_ulogic; + signal ex1_lvl3_shdcd016 :std_ulogic; + signal ex1_lvl3_shdcd032 :std_ulogic; + signal ex1_lvl3_shdcd048 :std_ulogic; + signal ex1_lvl3_shdcd064 :std_ulogic; + signal ex1_lvl3_shdcd080 :std_ulogic; + signal ex1_lvl3_shdcd096 :std_ulogic; + signal ex1_lvl3_shdcd112 :std_ulogic; + signal ex1_lvl3_shdcd128 :std_ulogic; + signal ex1_lvl3_shdcd144 :std_ulogic; + signal ex1_lvl3_shdcd160 :std_ulogic; + signal ex1_lvl3_shdcd176 :std_ulogic; + signal ex1_lvl3_shdcd192 :std_ulogic; + signal ex1_lvl3_shdcd208 :std_ulogic; + signal ex1_lvl3_shdcd224 :std_ulogic; + signal ex1_lvl3_shdcd240 :std_ulogic; + + signal ex2_lvl3_shdcd000 :std_ulogic; + signal ex2_lvl3_shdcd016 :std_ulogic; + signal ex2_lvl3_shdcd032 :std_ulogic; + signal ex2_lvl3_shdcd048 :std_ulogic; + signal ex2_lvl3_shdcd064 :std_ulogic; + signal ex2_lvl3_shdcd080 :std_ulogic; + signal ex2_lvl3_shdcd096 :std_ulogic; + signal ex2_lvl3_shdcd112 :std_ulogic; + signal ex2_lvl3_shdcd128 :std_ulogic; + signal ex2_lvl3_shdcd144 :std_ulogic; + signal ex2_lvl3_shdcd160 :std_ulogic; + signal ex2_lvl3_shdcd176 :std_ulogic; + signal ex2_lvl3_shdcd192 :std_ulogic; + signal ex2_lvl3_shdcd208 :std_ulogic; + signal ex2_lvl3_shdcd224 :std_ulogic; + signal ex2_lvl3_shdcd240 :std_ulogic; + + signal ex3_int_fr_nr1_b, ex3_int_fr_nr2_b, ex3_int_fr_ok_b :std_ulogic; + signal ex3_int_fr :std_ulogic; + signal ex3_sel_p1_0_b, ex3_sel_p1_1_b :std_ulogic; + signal ex3_sticky_math :std_ulogic; + signal ex3_sticky_toint :std_ulogic; + signal ex3_sticky_toint_nr :std_ulogic; + signal ex3_sticky_toint_ok :std_ulogic; + signal ex3_frmneg_o_toneg :std_ulogic; + signal ex3_frmneg_o_topos :std_ulogic; + signal ex3_lsb_toint_nr :std_ulogic; + signal ex3_g_math :std_ulogic; + signal ex3_g_toint :std_ulogic; + signal ex3_g_toint_nr :std_ulogic; + signal ex3_g_toint_ok :std_ulogic; + signal ex2_frmneg :std_ulogic; + signal ex2_toneg :std_ulogic; + signal ex2_topos :std_ulogic; + signal ex2_frmneg_o_toneg :std_ulogic; + signal ex2_frmneg_o_topos :std_ulogic; + signal ex2_toint_gate_x :std_ulogic; + signal ex2_toint_gate_g :std_ulogic; + signal ex2_toint_gt_nr_x :std_ulogic; + signal ex2_toint_gt_nr_g :std_ulogic; + signal ex2_toint_gt_ok_x :std_ulogic; + signal ex2_toint_gt_ok_g :std_ulogic; + signal ex2_math_gate_x :std_ulogic; + signal ex2_math_gate_g :std_ulogic; + signal ex2_sticky_eac_x :std_ulogic; + signal ex2_sticky_math :std_ulogic; + signal ex2_sticky_toint :std_ulogic; + signal ex2_sticky_toint_nr :std_ulogic; + signal ex2_sticky_toint_ok :std_ulogic; + signal ex2_lsb_toint_nr :std_ulogic; + signal ex2_g_math :std_ulogic; + signal ex2_g_toint :std_ulogic; + signal ex2_g_toint_nr :std_ulogic; + signal ex2_g_toint_ok :std_ulogic; + signal ex2_sh16_162, ex2_sh16_163 :std_ulogic; + signal alg_ex2_d1clk, alg_ex2_d2clk :std_ulogic; + + signal alg_ex2_lclk :clk_logic; + + signal ex2_bsha_b :std_ulogic_vector(6 to 9); + signal ex2_bsha_neg_b :std_ulogic; + signal ex2_sh_ovf_b :std_ulogic; + signal ex2_sh_unf_x_b :std_ulogic; + signal ex2_lvl3_shdcd000_b :std_ulogic; + signal ex2_lvl3_shdcd016_b :std_ulogic; + signal ex2_lvl3_shdcd032_b :std_ulogic; + signal ex2_lvl3_shdcd048_b :std_ulogic; + signal ex2_lvl3_shdcd064_b :std_ulogic; + signal ex2_lvl3_shdcd080_b :std_ulogic; + signal ex2_lvl3_shdcd096_b :std_ulogic; + signal ex2_lvl3_shdcd112_b :std_ulogic; + signal ex2_lvl3_shdcd128_b :std_ulogic; + signal ex2_lvl3_shdcd144_b :std_ulogic; + signal ex2_lvl3_shdcd160_b :std_ulogic; + signal ex2_lvl3_shdcd176_b :std_ulogic; + signal ex2_lvl3_shdcd192_b :std_ulogic; + signal ex2_lvl3_shdcd208_b :std_ulogic; + signal ex2_lvl3_shdcd224_b :std_ulogic; + signal ex2_lvl3_shdcd240_b :std_ulogic; + signal ex2_b_zero_l2_b :std_ulogic; + signal ex2_prod_zero_b :std_ulogic; + signal ex2_byp_nonflip_lze_b :std_ulogic; + signal ex2_sel_byp_nonflip_b :std_ulogic; + signal ex2_sh_unf_do_b :std_ulogic; + signal ex2_sh_unf_en_b :std_ulogic; + signal ex2_sh_ovf_en_b :std_ulogic; + signal ex2_effsub_alg_b :std_ulogic; + signal ex2_negate_b :std_ulogic; + signal ex2_b_sign_b :std_ulogic; + signal ex2_to_integer_b :std_ulogic; + signal ex2_from_integer_b :std_ulogic; + signal ex2_rnd_to_int_b :std_ulogic; + signal ex2_integer_op_b :std_ulogic; + signal ex2_word_from_b :std_ulogic; + + signal unused :std_ulogic; + + +begin + + unused <= ex1_b_expo(1) or ex1_b_expo(2) or + ex1_dp or + ex2_lvl3_shdcd176 ; + + ex1_b_frac(0 to 52) <= f_byp_alg_ex1_b_frac(0 to 52); + ex1_b_sign <= f_byp_alg_ex1_b_sign ; + ex1_b_expo(1 to 13) <= f_byp_alg_ex1_b_expo(1 to 13); + + + thold_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => thold_1, + q(0) => thold_0 ); + + sg_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => sg_1 , + q(0) => sg_0 ); + + + lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map ( + clkoff_b => clkoff_b, + thold => thold_0, + sg => sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => thold_0_b ); + + + + + + act_lat: tri_rlmreg_p generic map (width=> 5, expand_type => expand_type, needs_sreset => 0) port map ( + vd => vdd, + gd => gnd, + forcee => forcee, + delay_lclkr => delay_lclkr(2) , + mpw1_b => mpw1_b(2) , + mpw2_b => mpw2_b(0) , + nclk => nclk, + act => fpu_enable, + thold_b => thold_0_b, + sg => sg_0, + scout => act_so , + scin => act_si , + din(0) => spare_unused(0), + din(1) => spare_unused(1), + din(2) => ex1_act, + din(3) => spare_unused(2), + din(4) => spare_unused(3), + dout(0) => spare_unused(0), + dout(1) => spare_unused(1), + dout(2) => ex2_act, + dout(3) => spare_unused(2) , + dout(4) => spare_unused(3) ); + + + alg_ex2_lcb : tri_lcbnd generic map (expand_type => expand_type) port map( + delay_lclkr => delay_lclkr(2) , + mpw1_b => mpw1_b(2) , + mpw2_b => mpw2_b(0) , + forcee => forcee, + nclk => nclk , + vd => vdd , + gd => gnd , + act => ex1_act , + sg => sg_0 , + thold_b => thold_0_b , + d1clk => alg_ex2_d1clk , + d2clk => alg_ex2_d2clk , + lclk => alg_ex2_lclk ); + + + + + + + + + + + + rf1_from_integer <= not f_dcd_rf1_from_integer_b ; + rf1_to_integer <= not f_dcd_rf1_to_integer_b ; + rf1_dp <= not f_dcd_rf1_sp ; + rf1_word <= not f_dcd_rf1_word_b ; + rf1_uns <= not f_dcd_rf1_uns_b ; + + + ex1_ctl_lat: tri_rlmreg_p generic map (width=> 5, expand_type => expand_type, needs_sreset => 0) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(1) , + mpw1_b => mpw1_b(1) , + mpw2_b => mpw2_b(0) , + vd => vdd , + gd => gnd , + nclk => nclk , + thold_b => thold_0_b , + sg => sg_0 , + act => rf1_act , + scout => ex1_ctl_so , + scin => ex1_ctl_si , + din(0) => rf1_from_integer , + din(1) => rf1_to_integer , + din(2) => rf1_dp , + din(3) => rf1_word , + din(4) => rf1_uns , + dout(0) => ex1_from_integer , + dout(1) => ex1_to_integer , + dout(2) => ex1_dp , + dout(3) => ex1_word , + dout(4) => ex1_uns ); + + + + + sha: entity work.fuq_alg_add(fuq_alg_add) generic map (expand_type => expand_type) port map( + vdd => vdd, + gnd => gnd, + f_byp_alg_ex1_b_expo(1 to 13) => f_byp_alg_ex1_b_expo , + f_byp_alg_ex1_a_expo(1 to 13) => f_byp_alg_ex1_a_expo , + f_byp_alg_ex1_c_expo(1 to 13) => f_byp_alg_ex1_c_expo , + ex1_sel_special_b => ex1_sel_special_b , + ex1_bsha_6_o => ex1_bsha_6 , + ex1_bsha_7_o => ex1_bsha_7 , + ex1_bsha_8_o => ex1_bsha_8 , + ex1_bsha_9_o => ex1_bsha_9 , + ex1_bsha_neg_o => ex1_bsha_neg , + ex1_sh_ovf => ex1_sh_ovf , + ex1_sh_unf_x => ex1_sh_unf_x , + ex1_lvl1_shdcd000_b => ex1_lvl1_shdcd000_b , + ex1_lvl1_shdcd001_b => ex1_lvl1_shdcd001_b , + ex1_lvl1_shdcd002_b => ex1_lvl1_shdcd002_b , + ex1_lvl1_shdcd003_b => ex1_lvl1_shdcd003_b , + ex1_lvl2_shdcd000 => ex1_lvl2_shdcd000 , + ex1_lvl2_shdcd004 => ex1_lvl2_shdcd004 , + ex1_lvl2_shdcd008 => ex1_lvl2_shdcd008 , + ex1_lvl2_shdcd012 => ex1_lvl2_shdcd012 , + ex1_lvl3_shdcd000 => ex1_lvl3_shdcd000 , + ex1_lvl3_shdcd016 => ex1_lvl3_shdcd016 , + ex1_lvl3_shdcd032 => ex1_lvl3_shdcd032 , + ex1_lvl3_shdcd048 => ex1_lvl3_shdcd048 , + ex1_lvl3_shdcd064 => ex1_lvl3_shdcd064 , + ex1_lvl3_shdcd080 => ex1_lvl3_shdcd080 , + ex1_lvl3_shdcd096 => ex1_lvl3_shdcd096 , + ex1_lvl3_shdcd112 => ex1_lvl3_shdcd112 , + ex1_lvl3_shdcd128 => ex1_lvl3_shdcd128 , + ex1_lvl3_shdcd144 => ex1_lvl3_shdcd144 , + ex1_lvl3_shdcd160 => ex1_lvl3_shdcd160 , + ex1_lvl3_shdcd176 => ex1_lvl3_shdcd176 , + ex1_lvl3_shdcd192 => ex1_lvl3_shdcd192 , + ex1_lvl3_shdcd208 => ex1_lvl3_shdcd208 , + ex1_lvl3_shdcd224 => ex1_lvl3_shdcd224 , + ex1_lvl3_shdcd240 => ex1_lvl3_shdcd240 ); + + ex1_sel_special <= ex1_from_integer ; + ex1_sel_special_b <= not ex1_from_integer ; + + + + + ex1_sel_byp_nonflip_lze <= + ( f_fmt_ex1_pass_sel ) or + ( f_pic_ex1_sh_ovf_do ) ; + + ex1_sel_byp_nonflip <= + ( f_pic_ex1_frsp_ue1 ) or + ( f_fmt_ex1_pass_sel ) or + ( f_pic_ex1_sh_ovf_do ) ; + + ex1_integer_op <= ex1_from_integer or (ex1_to_integer and not f_pic_ex1_rnd_to_int); + + + f_alg_ex1_sign_frmw <= ex1_b_frac(21) ; + + ex1_sign_from <= + (ex1_from_integer and ex1_word and ex1_b_frac(21) ) or + (ex1_from_integer and not ex1_word and ex1_b_sign ); + + ex1_from_integer_neg <= ex1_from_integer and ex1_sign_from and not ex1_uns; + + ex1_word_from <= ex1_word and ex1_from_integer ; + + ex1_to_integer_neg <= ex1_to_integer and ex1_b_sign and not f_pic_ex1_rnd_to_int; + + ex1_negate <= f_pic_ex1_effsub_raw or + ex1_from_integer_neg or + ex1_to_integer_neg ; + + ex1_effsub_alg <= f_pic_ex1_effsub_raw and not f_fmt_ex1_pass_sel; + + ex1_b_zero <= f_fmt_ex1_b_zero; + + + + + + + sh4: entity work.fuq_alg_sh4(fuq_alg_sh4) generic map (expand_type => expand_type) port map( + ex1_lvl1_shdcd000_b => ex1_lvl1_shdcd000_b , + ex1_lvl1_shdcd001_b => ex1_lvl1_shdcd001_b , + ex1_lvl1_shdcd002_b => ex1_lvl1_shdcd002_b , + ex1_lvl1_shdcd003_b => ex1_lvl1_shdcd003_b , + ex1_lvl2_shdcd000 => ex1_lvl2_shdcd000 , + ex1_lvl2_shdcd004 => ex1_lvl2_shdcd004 , + ex1_lvl2_shdcd008 => ex1_lvl2_shdcd008 , + ex1_lvl2_shdcd012 => ex1_lvl2_shdcd012 , + ex1_sel_special => ex1_sel_special , + ex1_b_sign => ex1_b_sign , + ex1_b_expo(3 to 13) => ex1_b_expo(3 to 13) , + ex1_b_frac(0 to 52) => ex1_b_frac(0 to 52) , + ex1_sh_lvl2(0 to 67) => ex1_sh_lvl2(0 to 67) ); + + + ex2_shd_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 68, btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd , + gd => gnd , + LCLK => alg_ex2_lclk , + D1CLK => alg_ex2_d1clk , + D2CLK => alg_ex2_d2clk , + SCANIN => ex2_shd_si , + SCANOUT => ex2_shd_so , + D => ex1_sh_lvl2 (0 to 67) , + QB => ex2_sh_lvl2_b(0 to 67) ); + + ex2_sh_lvl2(0 to 67) <= not ex2_sh_lvl2_b(0 to 67) ; + + + ex2_shc_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 25, btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd , + gd => gnd , + LCLK => alg_ex2_lclk , + D1CLK => alg_ex2_d1clk , + D2CLK => alg_ex2_d2clk , + SCANIN => ex2_shc_si , + SCANOUT => ex2_shc_so , + D(0) => ex1_bsha_neg , + D(1) => ex1_sh_ovf , + D(2) => ex1_sh_unf_x , + D(3) => ex1_sel_special , + D(4) => ex1_sel_special_b, + D(5) => ex1_bsha_6 , + D(6) => ex1_bsha_7 , + D(7) => ex1_bsha_8 , + D(8) => ex1_bsha_9 , + D(9) => ex1_lvl3_shdcd000 , + D(10) => ex1_lvl3_shdcd016 , + D(11) => ex1_lvl3_shdcd032 , + D(12) => ex1_lvl3_shdcd048 , + D(13) => ex1_lvl3_shdcd064 , + D(14) => ex1_lvl3_shdcd080 , + D(15) => ex1_lvl3_shdcd096 , + D(16) => ex1_lvl3_shdcd112 , + D(17) => ex1_lvl3_shdcd128 , + D(18) => ex1_lvl3_shdcd144 , + D(19) => ex1_lvl3_shdcd160 , + D(20) => ex1_lvl3_shdcd176 , + D(21) => ex1_lvl3_shdcd192 , + D(22) => ex1_lvl3_shdcd208 , + D(23) => ex1_lvl3_shdcd224 , + D(24) => ex1_lvl3_shdcd240 , + QB(0) => ex2_bsha_neg_b , + QB(1) => ex2_sh_ovf_b , + QB(2) => ex2_sh_unf_x_b , + QB(3) => ex2_sel_special_b , + QB(4) => ex2_sel_special , + QB(5) => ex2_bsha_b(6) , + QB(6) => ex2_bsha_b(7) , + QB(7) => ex2_bsha_b(8) , + QB(8) => ex2_bsha_b(9) , + QB(9) => ex2_lvl3_shdcd000_b , + QB(10) => ex2_lvl3_shdcd016_b , + QB(11) => ex2_lvl3_shdcd032_b , + QB(12) => ex2_lvl3_shdcd048_b , + QB(13) => ex2_lvl3_shdcd064_b , + QB(14) => ex2_lvl3_shdcd080_b , + QB(15) => ex2_lvl3_shdcd096_b , + QB(16) => ex2_lvl3_shdcd112_b , + QB(17) => ex2_lvl3_shdcd128_b , + QB(18) => ex2_lvl3_shdcd144_b , + QB(19) => ex2_lvl3_shdcd160_b , + QB(20) => ex2_lvl3_shdcd176_b , + QB(21) => ex2_lvl3_shdcd192_b , + QB(22) => ex2_lvl3_shdcd208_b , + QB(23) => ex2_lvl3_shdcd224_b , + QB(24) => ex2_lvl3_shdcd240_b ); + + + ex2_bsha_neg <= not ex2_bsha_neg_b ; + ex2_sh_ovf <= not ex2_sh_ovf_b ; + ex2_sh_unf_x <= not ex2_sh_unf_x_b ; + ex2_bsha(6) <= not ex2_bsha_b(6) ; + ex2_bsha(7) <= not ex2_bsha_b(7) ; + ex2_bsha(8) <= not ex2_bsha_b(8) ; + ex2_bsha(9) <= not ex2_bsha_b(9) ; + ex2_lvl3_shdcd000 <= not ex2_lvl3_shdcd000_b ; + ex2_lvl3_shdcd016 <= not ex2_lvl3_shdcd016_b ; + ex2_lvl3_shdcd032 <= not ex2_lvl3_shdcd032_b ; + ex2_lvl3_shdcd048 <= not ex2_lvl3_shdcd048_b ; + ex2_lvl3_shdcd064 <= not ex2_lvl3_shdcd064_b ; + ex2_lvl3_shdcd080 <= not ex2_lvl3_shdcd080_b ; + ex2_lvl3_shdcd096 <= not ex2_lvl3_shdcd096_b ; + ex2_lvl3_shdcd112 <= not ex2_lvl3_shdcd112_b ; + ex2_lvl3_shdcd128 <= not ex2_lvl3_shdcd128_b ; + ex2_lvl3_shdcd144 <= not ex2_lvl3_shdcd144_b ; + ex2_lvl3_shdcd160 <= not ex2_lvl3_shdcd160_b ; + ex2_lvl3_shdcd176 <= not ex2_lvl3_shdcd176_b ; + ex2_lvl3_shdcd192 <= not ex2_lvl3_shdcd192_b ; + ex2_lvl3_shdcd208 <= not ex2_lvl3_shdcd208_b ; + ex2_lvl3_shdcd224 <= not ex2_lvl3_shdcd224_b ; + ex2_lvl3_shdcd240 <= not ex2_lvl3_shdcd240_b ; + + + + + ex2_ctl_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 15, btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd , + gd => gnd , + LCLK => alg_ex2_lclk , + D1CLK => alg_ex2_d1clk , + D2CLK => alg_ex2_d2clk , + SCANIN => ex2_ctl_si , + SCANOUT => ex2_ctl_so , + D(0) => ex1_b_zero , + D(1) => f_fmt_ex1_prod_zero , + D(2) => ex1_sel_byp_nonflip_lze , + D(3) => ex1_sel_byp_nonflip , + D(4) => f_pic_ex1_sh_unf_do , + D(5) => f_pic_ex1_sh_unf_ig_b , + D(6) => f_pic_ex1_sh_ovf_ig_b , + D(7) => ex1_effsub_alg , + D(8) => ex1_negate , + D(9) => ex1_b_sign , + D(10) => ex1_to_integer , + D(11) => ex1_from_integer , + D(12) => f_pic_ex1_rnd_to_int , + D(13) => ex1_integer_op , + D(14) => ex1_word_from , + QB(0) => ex2_b_zero_l2_b , + QB(1) => ex2_prod_zero_b , + QB(2) => ex2_byp_nonflip_lze_b , + QB(3) => ex2_sel_byp_nonflip_b , + QB(4) => ex2_sh_unf_do_b , + QB(5) => ex2_sh_unf_en_b , + QB(6) => ex2_sh_ovf_en_b , + QB(7) => ex2_effsub_alg_b , + QB(8) => ex2_negate_b , + QB(9) => ex2_b_sign_b , + QB(10) => ex2_to_integer_b , + QB(11) => ex2_from_integer_b , + QB(12) => ex2_rnd_to_int_b , + QB(13) => ex2_integer_op_b , + QB(14) => ex2_word_from_b ); + + + ex2_b_zero <= not ex2_b_zero_l2_b ; + ex2_prod_zero <= not ex2_prod_zero_b ; + ex2_byp_nonflip_lze <= not ex2_byp_nonflip_lze_b ; + ex2_sel_byp_nonflip <= not ex2_sel_byp_nonflip_b ; + ex2_sh_unf_do <= not ex2_sh_unf_do_b ; + ex2_sh_unf_en <= not ex2_sh_unf_en_b ; + ex2_sh_ovf_en <= not ex2_sh_ovf_en_b ; + ex2_effsub_alg <= not ex2_effsub_alg_b ; + ex2_negate <= not ex2_negate_b ; + ex2_b_sign <= not ex2_b_sign_b ; + ex2_to_integer <= not ex2_to_integer_b ; + ex2_from_integer <= not ex2_from_integer_b ; + ex2_rnd_to_int <= not ex2_rnd_to_int_b ; + ex2_integer_op <= not ex2_integer_op_b ; + ex2_word_from <= not ex2_word_from_b ; + + + + + + + ex2_xthrm_6_ns_b <= not( ex2_bsha(6) and ex2_sel_special_b ); + ex2_xthrm_7_ns_b <= not( ex2_bsha(7) and ex2_sel_special_b ); + ex2_xthrm_8_b <= not( ex2_bsha(8) ); + ex2_xthrm_8a9_b <= not( ex2_bsha(8) and ex2_bsha(9) ); + ex2_xthrm_8o9_b <= not( ex2_bsha(8) or ex2_bsha(9) ); + + ex2_xthrm7o8a9 <= not( ex2_xthrm_7_ns_b and ex2_xthrm_8a9_b ); + ex2_xthrm7o8 <= not( ex2_xthrm_7_ns_b and ex2_xthrm_8_b ); + ex2_xthrm7o8o9 <= not( ex2_xthrm_7_ns_b and ex2_xthrm_8o9_b ); + ex2_xthrm7a8a9 <= not( ex2_xthrm_7_ns_b or ex2_xthrm_8a9_b ); + ex2_xthrm_6_ns <= not( ex2_xthrm_6_ns_b ); + + ex2_ge176_b <= not( ex2_xthrm_6_ns and ex2_xthrm7o8a9 ); + ex2_ge160_b <= not( ex2_xthrm_6_ns and ex2_xthrm7o8 ); + ex2_ge144_b <= not( ex2_xthrm_6_ns and ex2_xthrm7o8o9 ); + ex2_ge128_b <= not( ex2_xthrm_6_ns ); + ex2_ge112_b <= not( ex2_xthrm_6_ns or ex2_xthrm7a8a9 ); + + ex2_sticky_en16_x(0) <= not ex2_ge176_b ; + ex2_sticky_en16_x(1) <= not ex2_ge160_b ; + ex2_sticky_en16_x(2) <= not ex2_ge144_b ; + ex2_sticky_en16_x(3) <= not ex2_ge128_b ; + ex2_sticky_en16_x(4) <= not ex2_ge112_b ; + + + + + + + ex2_b_zero_b <= not ex2_b_zero ; + + + f_alg_ex2_byp_nonflip <= ex2_byp_nonflip_lze ; + f_alg_ex2_sel_byp <= ex2_sel_byp ; + f_alg_ex2_effsub_eac_b <= not ex2_effsub_alg ; + f_alg_ex2_prod_z <= ex2_prod_zero ; + f_alg_ex2_sh_unf <= ex2_sh_unf ; + f_alg_ex2_sh_ovf <= ex2_ovf_pz ; + + + + + + + or16: entity work.fuq_alg_or16(fuq_alg_or16) generic map (expand_type => expand_type) port map ( + ex2_sh_lvl2(0 to 67) => ex2_sh_lvl2(0 to 67) , + ex2_sticky_or16(0 to 4) => ex2_sticky_or16(0 to 4) ); + + + sh16: entity work.fuq_alg_sh16(fuq_alg_sh16) generic map (expand_type => expand_type) port map ( + ex2_lvl3_shdcd000 => ex2_lvl3_shdcd000 , + ex2_lvl3_shdcd016 => ex2_lvl3_shdcd016 , + ex2_lvl3_shdcd032 => ex2_lvl3_shdcd032 , + ex2_lvl3_shdcd048 => ex2_lvl3_shdcd048 , + ex2_lvl3_shdcd064 => ex2_lvl3_shdcd064 , + ex2_lvl3_shdcd080 => ex2_lvl3_shdcd080 , + ex2_lvl3_shdcd096 => ex2_lvl3_shdcd096 , + ex2_lvl3_shdcd112 => ex2_lvl3_shdcd112 , + ex2_lvl3_shdcd128 => ex2_lvl3_shdcd128 , + ex2_lvl3_shdcd144 => ex2_lvl3_shdcd144 , + ex2_lvl3_shdcd160 => ex2_lvl3_shdcd160 , + ex2_lvl3_shdcd192 => ex2_lvl3_shdcd192 , + ex2_lvl3_shdcd208 => ex2_lvl3_shdcd208 , + ex2_lvl3_shdcd224 => ex2_lvl3_shdcd224 , + ex2_lvl3_shdcd240 => ex2_lvl3_shdcd240 , + ex2_sel_special => ex2_sel_special , + ex2_sh_lvl2(0 to 67) => ex2_sh_lvl2(0 to 67) , + ex2_sh16_162 => ex2_sh16_162 , + ex2_sh16_163 => ex2_sh16_163 , + ex2_sh_lvl3(0 to 162) => ex2_sh_lvl3(0 to 162) ); + + + + ex2_ovf_pz <= ex2_prod_zero or (ex2_sh_ovf and ex2_sh_ovf_en and not ex2_b_zero); + ex2_sel_byp <= ex2_sel_byp_nonflip or ex2_ovf_pz ; + ex2_all1_y <= ex2_negate and ex2_ovf_pz ; + ex2_all1_x <= ex2_negate and ex2_unf_bz ; + ex2_sh_unf <= ex2_sh_unf_do or ( ex2_sh_unf_en and ex2_sh_unf_x and not ex2_prod_zero); + ex2_unf_bz <= ex2_b_zero or ex2_sh_unf ; + + + + + ex2_byp_sel_byp_pos <= + ( ex2_sel_byp_nonflip ) or + ( ex2_ovf_pz and not ex2_integer_op and not ex2_negate and not ex2_unf_bz ) or + ( ex2_ovf_pz and not ex2_integer_op and ex2_all1_x ); + + ex2_byp_sel_byp_neg <= not ex2_sel_byp_nonflip and + ex2_ovf_pz and not ex2_integer_op and ex2_negate ; + + ex2_byp_sel_pos <= + ( not ex2_sel_byp and not ex2_integer_op and not ex2_negate and not ex2_unf_bz ) or + ( not ex2_sel_byp and not ex2_integer_op and ex2_all1_x ); + ex2_byp_sel_neg <= + ( not ex2_sel_byp and not ex2_integer_op and ex2_negate ); + + + ex2_prd_sel_pos_hi <= ex2_prd_sel_pos_lo and not ex2_integer_op ; + ex2_prd_sel_neg_hi <= ex2_prd_sel_neg_lo and not ex2_integer_op ; + + ex2_prd_sel_pos_lohi <= ex2_prd_sel_pos_lo and not ex2_word_from ; + ex2_prd_sel_neg_lohi <= ex2_prd_sel_neg_lo and not ex2_word_from ; + + + ex2_prd_sel_pos_lo <= + ( not ex2_sel_byp_nonflip and not ex2_ovf_pz and not ex2_unf_bz and not ex2_negate ) or + ( not ex2_sel_byp_nonflip and ex2_all1_x ) or + ( not ex2_sel_byp_nonflip and ex2_all1_y ) ; + ex2_prd_sel_neg_lo <= + ( not ex2_sel_byp_nonflip and ex2_negate ) ; + + + + bymx: entity work.fuq_alg_bypmux(fuq_alg_bypmux) generic map (expand_type => expand_type) port map ( + ex2_byp_sel_byp_neg => ex2_byp_sel_byp_neg , + ex2_byp_sel_byp_pos => ex2_byp_sel_byp_pos , + ex2_byp_sel_neg => ex2_byp_sel_neg , + ex2_byp_sel_pos => ex2_byp_sel_pos , + ex2_prd_sel_neg_hi => ex2_prd_sel_neg_hi , + ex2_prd_sel_neg_lo => ex2_prd_sel_neg_lo , + ex2_prd_sel_neg_lohi => ex2_prd_sel_neg_lohi , + ex2_prd_sel_pos_hi => ex2_prd_sel_pos_hi , + ex2_prd_sel_pos_lo => ex2_prd_sel_pos_lo , + ex2_prd_sel_pos_lohi => ex2_prd_sel_pos_lohi , + ex2_sh_lvl3(0 to 162) => ex2_sh_lvl3(0 to 162) , + f_fmt_ex2_pass_frac(0 to 52) => f_fmt_ex2_pass_frac(0 to 52) , + f_alg_ex2_res(0 to 162) => f_alg_ex2_res(0 to 162) ); + + + + ex2_frmneg <= ex2_from_integer and ex2_negate; + ex2_toneg <= (ex2_to_integer and not ex2_rnd_to_int and ex2_b_sign) ; + ex2_topos <= (ex2_to_integer and not ex2_rnd_to_int and not ex2_b_sign) or ex2_rnd_to_int; + ex2_frmneg_o_toneg <= ex2_frmneg or ex2_toneg; + ex2_frmneg_o_topos <= ex2_frmneg or ex2_topos; + + ex2_math_gate_x <= not ex2_sel_byp_nonflip and ex2_b_zero_b and not ex2_ovf_pz ; + ex2_toint_gate_x <= ex2_to_integer and ex2_b_zero_b ; + ex2_toint_gt_nr_x <= ex2_to_integer and ex2_b_zero_b and f_pic_ex2_rnd_nr ; + ex2_toint_gt_ok_x <= ex2_to_integer and ex2_b_zero_b and f_pic_ex2_rnd_inf_ok ; + + ex2_math_gate_g <= not ex2_sel_byp_nonflip and not ex2_ovf_pz and ex2_b_zero_b and (ex2_prd_sel_pos_lo or ex2_prd_sel_neg_lo); + ex2_toint_gate_g <= ex2_to_integer and not ex2_ovf_pz and not ex2_sh_unf and ex2_b_zero_b; + ex2_toint_gt_nr_g <= ex2_to_integer and not ex2_ovf_pz and not ex2_sh_unf and ex2_b_zero_b and f_pic_ex2_rnd_nr ; + ex2_toint_gt_ok_g <= ex2_to_integer and not ex2_ovf_pz and not ex2_sh_unf and ex2_b_zero_b and f_pic_ex2_rnd_inf_ok ; + + ex2_bsha_pos <= not ex2_bsha_neg ; + + ex2_sticky_eac_x <= + ( (ex2_sh_unf or ex2_sticky_en16_x(0)) and ex2_sticky_or16(0) and ex2_bsha_pos ) or + ( (ex2_sh_unf or ex2_sticky_en16_x(1)) and ex2_sticky_or16(1) and ex2_bsha_pos ) or + ( (ex2_sh_unf or ex2_sticky_en16_x(2)) and ex2_sticky_or16(2) and ex2_bsha_pos ) or + ( (ex2_sh_unf or ex2_sticky_en16_x(3)) and ex2_sticky_or16(3) and ex2_bsha_pos ) or + ( (ex2_sh_unf or ex2_sticky_en16_x(4)) and ex2_sticky_or16(4) and ex2_bsha_pos ) ; + + + ex2_sticky_math <= ex2_sticky_eac_x and ex2_math_gate_x ; + ex2_sticky_toint <= ex2_sticky_eac_x and ex2_toint_gate_x; + ex2_sticky_toint_nr <= ex2_sticky_eac_x and ex2_toint_gt_nr_x; + ex2_sticky_toint_ok <= ex2_sticky_eac_x and ex2_toint_gt_ok_x ; + + ex2_lsb_toint_nr <= (ex2_sh16_162 or ex2_rnd_to_int) and ex2_toint_gt_nr_g ; + + ex2_g_math <= ex2_sh16_163 and ex2_math_gate_g ; + ex2_g_toint <= ex2_sh16_163 and ex2_toint_gate_g; + ex2_g_toint_nr <= ex2_sh16_163 and ex2_toint_gt_nr_g ; + ex2_g_toint_ok <= ex2_sh16_163 and ex2_toint_gt_ok_g ; + + + + + + ex3_ctl_lat: tri_rlmreg_p generic map (width=> 11, expand_type => expand_type, needs_sreset => 0) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(3) , + mpw1_b => mpw1_b(3) , + mpw2_b => mpw2_b(0) , + vd => vdd , + gd => gnd , + nclk => nclk , + thold_b => thold_0_b , + sg => sg_0 , + act => ex2_act , + scout => ex3_ctl_so , + scin => ex3_ctl_si , + din(0) => ex2_sticky_math , + din(1) => ex2_sticky_toint , + din(2) => ex2_sticky_toint_nr , + din(3) => ex2_sticky_toint_ok , + din(4) => ex2_frmneg_o_toneg , + din(5) => ex2_frmneg_o_topos , + din(6) => ex2_lsb_toint_nr , + din(7) => ex2_g_math , + din(8) => ex2_g_toint , + din(9) => ex2_g_toint_nr , + din(10) => ex2_g_toint_ok , + dout(0) => ex3_sticky_math , + dout(1) => ex3_sticky_toint , + dout(2) => ex3_sticky_toint_nr , + dout(3) => ex3_sticky_toint_ok , + dout(4) => ex3_frmneg_o_toneg , + dout(5) => ex3_frmneg_o_topos , + dout(6) => ex3_lsb_toint_nr , + dout(7) => ex3_g_math , + dout(8) => ex3_g_toint , + dout(9) => ex3_g_toint_nr , + dout(10) => ex3_g_toint_ok ); + + + f_alg_ex3_sticky <= ex3_sticky_math or ex3_g_math ; + f_alg_ex3_int_fi <= ex3_sticky_toint or ex3_g_toint ; + + ex3_int_fr_nr1_b <= not( ex3_g_toint_nr and ex3_sticky_toint_nr ); + ex3_int_fr_nr2_b <= not( ex3_g_toint_nr and ex3_lsb_toint_nr ); + ex3_int_fr_ok_b <= not( ex3_g_toint_ok or ex3_sticky_toint_ok ); + ex3_int_fr <= not( ex3_int_fr_nr1_b and ex3_int_fr_nr2_b and ex3_int_fr_ok_b ); + f_alg_ex3_int_fr <= ex3_int_fr ; + + ex3_sel_p1_0_b <= not( not ex3_int_fr and ex3_frmneg_o_toneg); + ex3_sel_p1_1_b <= not( ex3_int_fr and ex3_frmneg_o_topos); + f_alg_ex3_frc_sel_p1 <= not(ex3_sel_p1_0_b and ex3_sel_p1_1_b ) ; + + + + ex1_ctl_si (0 to 4) <= ex1_ctl_so (1 to 4) & f_alg_si ; + ex2_shd_si (0 to 67) <= ex2_shd_so (1 to 67) & ex1_ctl_so (0) ; + ex2_shc_si (0 to 24) <= ex2_shc_so (1 to 24) & ex2_shd_so (0) ; + ex2_ctl_si (0 to 14) <= ex2_ctl_so (1 to 14) & ex2_shc_so (0) ; + ex3_ctl_si (0 to 10) <= ex3_ctl_so (1 to 10) & ex2_ctl_so (0) ; + act_si (0 to 4) <= act_so (1 to 4) & ex3_ctl_so (0) ; + f_alg_so <= act_so (0) ; + + +end; + + + + + + + + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_alg_add.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_alg_add.vhdl new file mode 100644 index 0000000..e007a83 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_alg_add.vhdl @@ -0,0 +1,670 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + library clib ; + +entity fuq_alg_add is +generic( expand_type : integer := 2 ); +port( + + vdd : inout power_logic; + gnd : inout power_logic; + + f_byp_alg_ex1_b_expo :in std_ulogic_vector(1 to 13); + f_byp_alg_ex1_a_expo :in std_ulogic_vector(1 to 13); + f_byp_alg_ex1_c_expo :in std_ulogic_vector(1 to 13); + + ex1_sel_special_b :in std_ulogic ; + + ex1_bsha_6_o :out std_ulogic ; + ex1_bsha_7_o :out std_ulogic ; + ex1_bsha_8_o :out std_ulogic ; + ex1_bsha_9_o :out std_ulogic ; + + ex1_bsha_neg_o :out std_ulogic ; + ex1_sh_ovf :out std_ulogic ; + ex1_sh_unf_x :out std_ulogic ; + + + ex1_lvl1_shdcd000_b :out std_ulogic ; + ex1_lvl1_shdcd001_b :out std_ulogic ; + ex1_lvl1_shdcd002_b :out std_ulogic ; + ex1_lvl1_shdcd003_b :out std_ulogic ; + + ex1_lvl2_shdcd000 :out std_ulogic ; + ex1_lvl2_shdcd004 :out std_ulogic ; + ex1_lvl2_shdcd008 :out std_ulogic ; + ex1_lvl2_shdcd012 :out std_ulogic ; + + ex1_lvl3_shdcd000 :out std_ulogic ; + ex1_lvl3_shdcd016 :out std_ulogic ; + ex1_lvl3_shdcd032 :out std_ulogic ; + ex1_lvl3_shdcd048 :out std_ulogic ; + ex1_lvl3_shdcd064 :out std_ulogic ; + ex1_lvl3_shdcd080 :out std_ulogic ; + ex1_lvl3_shdcd096 :out std_ulogic ; + ex1_lvl3_shdcd112 :out std_ulogic ; + ex1_lvl3_shdcd128 :out std_ulogic ; + ex1_lvl3_shdcd144 :out std_ulogic ; + ex1_lvl3_shdcd160 :out std_ulogic ; + ex1_lvl3_shdcd176 :out std_ulogic ; + ex1_lvl3_shdcd192 :out std_ulogic ; + ex1_lvl3_shdcd208 :out std_ulogic ; + ex1_lvl3_shdcd224 :out std_ulogic ; + ex1_lvl3_shdcd240 :out std_ulogic +); + + + +end fuq_alg_add; + +architecture fuq_alg_add of fuq_alg_add is + + constant tiup :std_ulogic := '1'; + constant tidn :std_ulogic := '0'; + signal ex1_bsha_sim_c :std_ulogic_vector(2 to 14); + signal ex1_bsha_sim_p :std_ulogic_vector(1 to 13); + signal ex1_bsha_sim_g :std_ulogic_vector(2 to 13); + signal ex1_bsha_sim :std_ulogic_vector(1 to 13); + + signal ex1_b_expo_b :std_ulogic_vector(1 to 13); + signal ex1_a_expo_b :std_ulogic_vector(2 to 13); + signal ex1_c_expo_b :std_ulogic_vector(2 to 13); + signal ex1_bsha_neg :std_ulogic; + signal ex1_sh_ovf_b :std_ulogic; + signal ex1_alg_sx :std_ulogic_vector(1 to 13) ; + signal ex1_alg_cx :std_ulogic_vector(0 to 12) ; + signal ex1_alg_add_p :std_ulogic_vector(1 to 12) ; + signal ex1_alg_add_g_b :std_ulogic_vector(2 to 12) ; + signal ex1_alg_add_t_b :std_ulogic_vector(2 to 11) ; + + signal ex1_bsha_6_b :std_ulogic; + signal ex1_bsha_7_b :std_ulogic; + signal ex1_bsha_8_b :std_ulogic; + signal ex1_bsha_9_b :std_ulogic; + signal ex1_67_dcd00_b :std_ulogic; + signal ex1_67_dcd01_b :std_ulogic; + signal ex1_67_dcd10_b :std_ulogic; + signal ex1_67_dcd11_b :std_ulogic; + signal ex1_89_dcd00_b :std_ulogic; + signal ex1_89_dcd01_b :std_ulogic; + signal ex1_89_dcd10_b :std_ulogic; + signal ex1_89_dcd11_b :std_ulogic; + + signal ex1_lv2_0pg0_b :std_ulogic; + signal ex1_lv2_0pg1_b :std_ulogic; + signal ex1_lv2_0pk0_b :std_ulogic; + signal ex1_lv2_0pk1_b :std_ulogic; + signal ex1_lv2_0pp0_b :std_ulogic; + signal ex1_lv2_0pp1_b :std_ulogic; + signal ex1_lv2_1pg0_b :std_ulogic; + signal ex1_lv2_1pg1_b :std_ulogic; + signal ex1_lv2_1pk0_b :std_ulogic; + signal ex1_lv2_1pk1_b :std_ulogic; + signal ex1_lv2_1pp0_b :std_ulogic; + signal ex1_lv2_1pp1_b :std_ulogic; + signal ex1_lv2_shdcd000 :std_ulogic; + signal ex1_lv2_shdcd004 :std_ulogic; + signal ex1_lv2_shdcd008 :std_ulogic; + signal ex1_lv2_shdcd012 :std_ulogic; + signal ex1_lvl2_shdcd000_b :std_ulogic; + signal ex1_lvl2_shdcd004_b :std_ulogic; + signal ex1_lvl2_shdcd008_b :std_ulogic; + signal ex1_lvl2_shdcd012_b :std_ulogic; + + signal ex1_alg_add_c_b :std_ulogic_vector(7 to 10); + signal ex1_g02_12 :std_ulogic; + signal ex1_g02_12_b :std_ulogic; + signal ex1_bsha_13_b :std_ulogic; + signal ex1_bsha_13 :std_ulogic; + signal ex1_bsha_12_b :std_ulogic; + signal ex1_bsha_12 :std_ulogic; + signal ex1_lv2_ci11n_en_b :std_ulogic; + signal ex1_lv2_ci11p_en_b :std_ulogic; + signal ex1_lv2_ci11n_en :std_ulogic; + signal ex1_lv2_ci11p_en :std_ulogic; + signal ex1_g02_10 :std_ulogic; + signal ex1_t02_10 :std_ulogic; + signal ex1_g04_10_b :std_ulogic; + signal ex1_lv2_g11_x :std_ulogic; + signal ex1_lv2_g11_b :std_ulogic; + signal ex1_lv2_g11 :std_ulogic; + signal ex1_lv2_k11_b :std_ulogic; + signal ex1_lv2_k11 :std_ulogic; + signal ex1_lv2_p11_b :std_ulogic; + signal ex1_lv2_p11 :std_ulogic; + signal ex1_lv2_p10_b :std_ulogic; + signal ex1_lv2_p10 :std_ulogic; + signal ex1_g04_10 :std_ulogic; + signal ex1_g02_6 :std_ulogic; + signal ex1_g02_7 :std_ulogic; + signal ex1_g02_8 :std_ulogic; + signal ex1_g02_9 :std_ulogic; + signal ex1_t02_6 :std_ulogic; + signal ex1_t02_7 :std_ulogic; + signal ex1_t02_8 :std_ulogic; + signal ex1_t02_9 :std_ulogic; + signal ex1_g04_6_b :std_ulogic; + signal ex1_g04_7_b :std_ulogic; + signal ex1_g04_8_b :std_ulogic; + signal ex1_g04_9_b :std_ulogic; + signal ex1_t04_6_b :std_ulogic; + signal ex1_t04_7_b :std_ulogic; + signal ex1_t04_8_b :std_ulogic; + signal ex1_t04_9_b :std_ulogic; + signal ex1_g08_6 :std_ulogic; + signal ex1_g04_7 :std_ulogic; + signal ex1_g04_8 :std_ulogic; + signal ex1_g04_9 :std_ulogic; + signal ex1_t04_7 :std_ulogic; + signal ex1_t04_8 :std_ulogic; + signal ex1_t04_9 :std_ulogic; + signal ex1_bsha_6 :std_ulogic; + signal ex1_bsha_7 :std_ulogic; + signal ex1_bsha_8 :std_ulogic; + signal ex1_bsha_9 :std_ulogic; + signal ex1_g02_4 :std_ulogic; + signal ex1_g02_2 :std_ulogic; + signal ex1_t02_4 :std_ulogic; + signal ex1_t02_2 :std_ulogic; + signal ex1_g04_2_b :std_ulogic; + signal ex1_t04_2_b :std_ulogic; + signal ex1_ones_2t3_b :std_ulogic; + signal ex1_ones_4t5_b :std_ulogic; + signal ex1_ones_2t5 :std_ulogic; + signal ex1_ones_2t5_b :std_ulogic; + signal ex1_zero_2_b :std_ulogic; + signal ex1_zero_3_b :std_ulogic; + signal ex1_zero_4_b :std_ulogic; + signal ex1_zero_5 :std_ulogic; + signal ex1_zero_5_b :std_ulogic; + signal ex1_zero_2t3 :std_ulogic; + signal ex1_zero_4t5 :std_ulogic; + signal ex1_zero_2t5_b :std_ulogic; + signal pos_if_pco6 :std_ulogic; + signal pos_if_nco6 :std_ulogic; + signal pos_if_pco6_b :std_ulogic; + signal pos_if_nco6_b :std_ulogic; + signal unf_if_nco6_b :std_ulogic; + signal unf_if_pco6_b :std_ulogic; + signal ex1_g08_6_b :std_ulogic; + signal ex1_bsha_pos :std_ulogic; + signal ex1_bsha_6_i :std_ulogic; + signal ex1_bsha_7_i :std_ulogic; + signal ex1_bsha_8_i :std_ulogic; + signal ex1_bsha_9_i :std_ulogic; + signal ex1_ack_s :std_ulogic_vector(1 to 13); + signal ex1_ack_c :std_ulogic_vector(1 to 12); + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +begin + + + + ex1_bsha_sim_p(1 to 12) <= ex1_alg_sx(1 to 12) xor ex1_alg_cx(1 to 12); + ex1_bsha_sim_p( 13) <= ex1_alg_sx( 13) ; + ex1_bsha_sim_g(2 to 12) <= ex1_alg_sx(2 to 12) and ex1_alg_cx(2 to 12); + ex1_bsha_sim_g(13) <= tidn; + ex1_bsha_sim (1 to 13) <= ex1_bsha_sim_p(1 to 13) xor ex1_bsha_sim_c(2 to 14); + + ex1_bsha_sim_c(14) <= tidn; + ex1_bsha_sim_c(13) <= ex1_bsha_sim_g(13) or (ex1_bsha_sim_p(13) and ex1_bsha_sim_c(14) ); + ex1_bsha_sim_c(12) <= ex1_bsha_sim_g(12) or (ex1_bsha_sim_p(12) and ex1_bsha_sim_c(13) ); + ex1_bsha_sim_c(11) <= ex1_bsha_sim_g(11) or (ex1_bsha_sim_p(11) and ex1_bsha_sim_c(12) ); + ex1_bsha_sim_c(10) <= ex1_bsha_sim_g(10) or (ex1_bsha_sim_p(10) and ex1_bsha_sim_c(11) ); + ex1_bsha_sim_c( 9) <= ex1_bsha_sim_g( 9) or (ex1_bsha_sim_p( 9) and ex1_bsha_sim_c(10) ); + ex1_bsha_sim_c( 8) <= ex1_bsha_sim_g( 8) or (ex1_bsha_sim_p( 8) and ex1_bsha_sim_c( 9) ); + ex1_bsha_sim_c( 7) <= ex1_bsha_sim_g( 7) or (ex1_bsha_sim_p( 7) and ex1_bsha_sim_c( 8) ); + ex1_bsha_sim_c( 6) <= ex1_bsha_sim_g( 6) or (ex1_bsha_sim_p( 6) and ex1_bsha_sim_c( 7) ); + ex1_bsha_sim_c( 5) <= ex1_bsha_sim_g( 5) or (ex1_bsha_sim_p( 5) and ex1_bsha_sim_c( 6) ); + ex1_bsha_sim_c( 4) <= ex1_bsha_sim_g( 4) or (ex1_bsha_sim_p( 4) and ex1_bsha_sim_c( 5) ); + ex1_bsha_sim_c( 3) <= ex1_bsha_sim_g( 3) or (ex1_bsha_sim_p( 3) and ex1_bsha_sim_c( 4) ); + ex1_bsha_sim_c( 2) <= ex1_bsha_sim_g( 2) or (ex1_bsha_sim_p( 2) and ex1_bsha_sim_c( 3) ); + + + + + a32_inv: ex1_a_expo_b(2 to 13) <= not f_byp_alg_ex1_a_expo(2 to 13); + c32_inv: ex1_c_expo_b(2 to 13) <= not f_byp_alg_ex1_c_expo(2 to 13); + b32_inv: ex1_b_expo_b(1 to 13) <= not f_byp_alg_ex1_b_expo(1 to 13); + +sx01: ex1_ack_s( 1) <= not( f_byp_alg_ex1_a_expo( 1) xor f_byp_alg_ex1_c_expo( 1) ); +sx02: ex1_ack_s( 2) <= not( f_byp_alg_ex1_a_expo( 2) xor f_byp_alg_ex1_c_expo( 2) ); +sx03: ex1_ack_s( 3) <= not( f_byp_alg_ex1_a_expo( 3) xor f_byp_alg_ex1_c_expo( 3) ); +sx04: ex1_ack_s( 4) <= ( f_byp_alg_ex1_a_expo( 4) xor f_byp_alg_ex1_c_expo( 4) ); +sx05: ex1_ack_s( 5) <= ( f_byp_alg_ex1_a_expo( 5) xor f_byp_alg_ex1_c_expo( 5) ); +sx06: ex1_ack_s( 6) <= ( f_byp_alg_ex1_a_expo( 6) xor f_byp_alg_ex1_c_expo( 6) ); +sx07: ex1_ack_s( 7) <= ( f_byp_alg_ex1_a_expo( 7) xor f_byp_alg_ex1_c_expo( 7) ); +sx08: ex1_ack_s( 8) <= not( f_byp_alg_ex1_a_expo( 8) xor f_byp_alg_ex1_c_expo( 8) ); +sx09: ex1_ack_s( 9) <= not( f_byp_alg_ex1_a_expo( 9) xor f_byp_alg_ex1_c_expo( 9) ); +sx10: ex1_ack_s(10) <= not( f_byp_alg_ex1_a_expo(10) xor f_byp_alg_ex1_c_expo(10) ); +sx11: ex1_ack_s(11) <= ( f_byp_alg_ex1_a_expo(11) xor f_byp_alg_ex1_c_expo(11) ); +sx12: ex1_ack_s(12) <= not( f_byp_alg_ex1_a_expo(12) xor f_byp_alg_ex1_c_expo(12) ); +sx13: ex1_ack_s(13) <= ( f_byp_alg_ex1_a_expo(13) xor f_byp_alg_ex1_c_expo(13) ); + + + + cx01: ex1_ack_c( 1) <= not( ex1_a_expo_b( 2) and ex1_c_expo_b( 2) ); + cx02: ex1_ack_c( 2) <= not( ex1_a_expo_b( 3) and ex1_c_expo_b( 3) ); + cx03: ex1_ack_c( 3) <= not( ex1_a_expo_b( 4) or ex1_c_expo_b( 4) ); + cx04: ex1_ack_c( 4) <= not( ex1_a_expo_b( 5) or ex1_c_expo_b( 5) ); + cx05: ex1_ack_c( 5) <= not( ex1_a_expo_b( 6) or ex1_c_expo_b( 6) ); + cx06: ex1_ack_c( 6) <= not( ex1_a_expo_b( 7) or ex1_c_expo_b( 7) ); + cx07: ex1_ack_c( 7) <= not( ex1_a_expo_b( 8) and ex1_c_expo_b( 8) ); + cx08: ex1_ack_c( 8) <= not( ex1_a_expo_b( 9) and ex1_c_expo_b( 9) ); + cx09: ex1_ack_c( 9) <= not( ex1_a_expo_b(10) and ex1_c_expo_b(10) ); + cx10: ex1_ack_c(10) <= not( ex1_a_expo_b(11) or ex1_c_expo_b(11) ); + cx11: ex1_ack_c(11) <= not( ex1_a_expo_b(12) and ex1_c_expo_b(12) ); + cx12: ex1_ack_c(12) <= not( ex1_a_expo_b(13) or ex1_c_expo_b(13) ); + + + + + + +sha32_01: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex1_b_expo_b(1) , + b => ex1_ack_s(1) , + c => ex1_ack_c(1) , + sum => ex1_alg_sx(1) , + car => ex1_alg_cx(0) ); +sha32_02: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex1_b_expo_b(2) , + b => ex1_ack_s(2) , + c => ex1_ack_c(2) , + sum => ex1_alg_sx(2) , + car => ex1_alg_cx(1) ); +sha32_03: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex1_b_expo_b(3) , + b => ex1_ack_s(3) , + c => ex1_ack_c(3) , + sum => ex1_alg_sx(3) , + car => ex1_alg_cx(2) ); +sha32_04: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex1_b_expo_b(4) , + b => ex1_ack_s(4) , + c => ex1_ack_c(4) , + sum => ex1_alg_sx(4) , + car => ex1_alg_cx(3) ); +sha32_05: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex1_b_expo_b(5) , + b => ex1_ack_s(5) , + c => ex1_ack_c(5) , + sum => ex1_alg_sx(5) , + car => ex1_alg_cx(4) ); +sha32_06: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex1_b_expo_b(6) , + b => ex1_ack_s(6) , + c => ex1_ack_c(6) , + sum => ex1_alg_sx(6) , + car => ex1_alg_cx(5) ); +sha32_07: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex1_b_expo_b(7) , + b => ex1_ack_s(7) , + c => ex1_ack_c(7) , + sum => ex1_alg_sx(7) , + car => ex1_alg_cx(6) ); +sha32_08: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex1_b_expo_b(8) , + b => ex1_ack_s(8) , + c => ex1_ack_c(8) , + sum => ex1_alg_sx(8) , + car => ex1_alg_cx(7) ); +sha32_09: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex1_b_expo_b(9) , + b => ex1_ack_s(9) , + c => ex1_ack_c(9) , + sum => ex1_alg_sx(9) , + car => ex1_alg_cx(8) ); +sha32_10: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex1_b_expo_b(10) , + b => ex1_ack_s(10) , + c => ex1_ack_c(10) , + sum => ex1_alg_sx(10) , + car => ex1_alg_cx(9) ); +sha32_11: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex1_b_expo_b(11) , + b => ex1_ack_s(11) , + c => ex1_ack_c(11) , + sum => ex1_alg_sx(11) , + car => ex1_alg_cx(10) ); +sha32_12: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex1_b_expo_b(12) , + b => ex1_ack_s(12) , + c => ex1_ack_c(12) , + sum => ex1_alg_sx(12) , + car => ex1_alg_cx(11) ); +sha32_13: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex1_b_expo_b(13) , + b => ex1_ack_s(13) , + c => tidn , + sum => ex1_alg_sx(13) , + car => ex1_alg_cx(12) ); + + + +p1_01: ex1_alg_add_p( 1) <= ex1_alg_sx( 1) xor ex1_alg_cx( 1); +p1_02: ex1_alg_add_p( 2) <= ex1_alg_sx( 2) xor ex1_alg_cx( 2); +p1_03: ex1_alg_add_p( 3) <= ex1_alg_sx( 3) xor ex1_alg_cx( 3); +p1_04: ex1_alg_add_p( 4) <= ex1_alg_sx( 4) xor ex1_alg_cx( 4); +p1_05: ex1_alg_add_p( 5) <= ex1_alg_sx( 5) xor ex1_alg_cx( 5); +p1_06: ex1_alg_add_p( 6) <= ex1_alg_sx( 6) xor ex1_alg_cx( 6); +p1_07: ex1_alg_add_p( 7) <= ex1_alg_sx( 7) xor ex1_alg_cx( 7); +p1_08: ex1_alg_add_p( 8) <= ex1_alg_sx( 8) xor ex1_alg_cx( 8); +p1_09: ex1_alg_add_p( 9) <= ex1_alg_sx( 9) xor ex1_alg_cx( 9); +p1_10: ex1_alg_add_p(10) <= ex1_alg_sx(10) xor ex1_alg_cx(10); +p1_11: ex1_alg_add_p(11) <= ex1_alg_sx(11) xor ex1_alg_cx(11); +p1_12: ex1_alg_add_p(12) <= ex1_alg_sx(12) xor ex1_alg_cx(12); + + +g1_02: ex1_alg_add_g_b( 2) <= not( ex1_alg_sx( 2) and ex1_alg_cx( 2) ); +g1_03: ex1_alg_add_g_b( 3) <= not( ex1_alg_sx( 3) and ex1_alg_cx( 3) ); +g1_04: ex1_alg_add_g_b( 4) <= not( ex1_alg_sx( 4) and ex1_alg_cx( 4) ); +g1_05: ex1_alg_add_g_b( 5) <= not( ex1_alg_sx( 5) and ex1_alg_cx( 5) ); +g1_06: ex1_alg_add_g_b( 6) <= not( ex1_alg_sx( 6) and ex1_alg_cx( 6) ); +g1_07: ex1_alg_add_g_b( 7) <= not( ex1_alg_sx( 7) and ex1_alg_cx( 7) ); +g1_08: ex1_alg_add_g_b( 8) <= not( ex1_alg_sx( 8) and ex1_alg_cx( 8) ); +g1_09: ex1_alg_add_g_b( 9) <= not( ex1_alg_sx( 9) and ex1_alg_cx( 9) ); +g1_10: ex1_alg_add_g_b(10) <= not( ex1_alg_sx(10) and ex1_alg_cx(10) ); +g1_11: ex1_alg_add_g_b(11) <= not( ex1_alg_sx(11) and ex1_alg_cx(11) ); +g1_12: ex1_alg_add_g_b(12) <= not( ex1_alg_sx(12) and ex1_alg_cx(12) ); + +t1_02: ex1_alg_add_t_b( 2) <= not( ex1_alg_sx( 2) or ex1_alg_cx( 2) ); +t1_03: ex1_alg_add_t_b( 3) <= not( ex1_alg_sx( 3) or ex1_alg_cx( 3) ); +t1_04: ex1_alg_add_t_b( 4) <= not( ex1_alg_sx( 4) or ex1_alg_cx( 4) ); +t1_05: ex1_alg_add_t_b( 5) <= not( ex1_alg_sx( 5) or ex1_alg_cx( 5) ); +t1_06: ex1_alg_add_t_b( 6) <= not( ex1_alg_sx( 6) or ex1_alg_cx( 6) ); +t1_07: ex1_alg_add_t_b( 7) <= not( ex1_alg_sx( 7) or ex1_alg_cx( 7) ); +t1_08: ex1_alg_add_t_b( 8) <= not( ex1_alg_sx( 8) or ex1_alg_cx( 8) ); +t1_09: ex1_alg_add_t_b( 9) <= not( ex1_alg_sx( 9) or ex1_alg_cx( 9) ); +t1_10: ex1_alg_add_t_b(10) <= not( ex1_alg_sx(10) or ex1_alg_cx(10) ); +t1_11: ex1_alg_add_t_b(11) <= not( ex1_alg_sx(11) or ex1_alg_cx(11) ); + + +g2_12: ex1_g02_12 <= not ex1_alg_add_g_b(12); +g2_12b: ex1_g02_12_b <= not ex1_g02_12 ; + +res_13b: ex1_bsha_13_b <= not ex1_alg_sx(13); +res_13: ex1_bsha_13 <= not ex1_bsha_13_b ; +res_12b: ex1_bsha_12_b <= not ex1_alg_add_p(12); +res_12: ex1_bsha_12 <= not ex1_bsha_12_b ; + +ci11nb: ex1_lv2_ci11n_en_b <= not( ex1_sel_special_b and ex1_g02_12_b ); +ci11pb: ex1_lv2_ci11p_en_b <= not( ex1_sel_special_b and ex1_g02_12 ); +ci11n: ex1_lv2_ci11n_en <= not( ex1_lv2_ci11n_en_b ); +ci11p: ex1_lv2_ci11p_en <= not( ex1_lv2_ci11p_en_b ); + + +g2_10: ex1_g02_10 <= not( ex1_alg_add_g_b(10) and (ex1_alg_add_t_b(10) or ex1_alg_add_g_b(11)) ); +t2_10: ex1_t02_10 <= not( ex1_alg_add_t_b(10) or ex1_alg_add_t_b(11) ); +g4_10: ex1_g04_10_b <= not( ex1_g02_10 or (ex1_t02_10 and ex1_g02_12 ) ); + +g11x: ex1_lv2_g11_x <= not( ex1_alg_add_g_b(11) ); +g11b: ex1_lv2_g11_b <= not( ex1_lv2_g11_x ); +g11: ex1_lv2_g11 <= not( ex1_lv2_g11_b ); +k11x: ex1_lv2_k11_b <= not( ex1_alg_add_t_b(11) ); +k11: ex1_lv2_k11 <= not( ex1_lv2_k11_b ); +p11b: ex1_lv2_p11_b <= not( ex1_alg_add_p(11) ); +p11: ex1_lv2_p11 <= not( ex1_lv2_p11_b ); +p10b: ex1_lv2_p10_b <= not( ex1_alg_add_p(10) ); +p10: ex1_lv2_p10 <= not( ex1_lv2_p10_b ); + + +g4x_10: ex1_g04_10 <= not ex1_g04_10_b ; + +g2_06: ex1_g02_6 <= not( ex1_alg_add_g_b(6) and (ex1_alg_add_t_b(6) or ex1_alg_add_g_b(7)) ); +g2_07: ex1_g02_7 <= not( ex1_alg_add_g_b(7) and (ex1_alg_add_t_b(7) or ex1_alg_add_g_b(8)) ); +g2_08: ex1_g02_8 <= not( ex1_alg_add_g_b(8) and (ex1_alg_add_t_b(8) or ex1_alg_add_g_b(9)) ); +g2_09: ex1_g02_9 <= not( ex1_alg_add_g_b(9) ); +t2_06: ex1_t02_6 <= not( ex1_alg_add_t_b(6) or ex1_alg_add_t_b(7) ); +t2_07: ex1_t02_7 <= not( ex1_alg_add_t_b(7) or ex1_alg_add_t_b(8) ); +t2_08: ex1_t02_8 <= not( ex1_alg_add_t_b(8) or ex1_alg_add_t_b(9) ); +t2_09: ex1_t02_9 <= not( ex1_alg_add_t_b(9) ); + +g4_06b: ex1_g04_6_b <= not( ex1_g02_6 or (ex1_t02_6 and ex1_g02_8 ) ); +g4_07b: ex1_g04_7_b <= not( ex1_g02_7 or (ex1_t02_7 and ex1_g02_9 ) ); +g4_08b: ex1_g04_8_b <= not( ex1_g02_8 ); +g4_09b: ex1_g04_9_b <= not( ex1_g02_9 ); +t4_06b: ex1_t04_6_b <= not( ex1_t02_6 and ex1_t02_8 ); +t4_07b: ex1_t04_7_b <= not( ex1_t02_7 and ex1_t02_9 ); +t4_08b: ex1_t04_8_b <= not( ex1_t02_8 ); +t4_09b: ex1_t04_9_b <= not( ex1_t02_9 ); + +g8_06: ex1_g08_6 <= not( ex1_g04_6_b and (ex1_t04_6_b or ex1_g04_10_b ) ); +g4_07: ex1_g04_7 <= not( ex1_g04_7_b ); +g4_08: ex1_g04_8 <= not( ex1_g04_8_b ); +g4_09: ex1_g04_9 <= not( ex1_g04_9_b ); +t4_07: ex1_t04_7 <= not( ex1_t04_7_b ); +t4_08: ex1_t04_8 <= not( ex1_t04_8_b ); +t4_09: ex1_t04_9 <= not( ex1_t04_9_b ); + +c07: ex1_alg_add_c_b(7) <= not( ex1_g04_7 or (ex1_t04_7 and ex1_g04_10) ); +c08: ex1_alg_add_c_b(8) <= not( ex1_g04_8 or (ex1_t04_8 and ex1_g04_10) ); +c09: ex1_alg_add_c_b(9) <= not( ex1_g04_9 or (ex1_t04_9 and ex1_g04_10) ); +c10: ex1_alg_add_c_b(10) <= not( ex1_g04_10 ); + +res_6: ex1_bsha_6 <= not( ex1_alg_add_p(6) xor ex1_alg_add_c_b(7) ); +res_7: ex1_bsha_7 <= not( ex1_alg_add_p(7) xor ex1_alg_add_c_b(8) ); +res_8: ex1_bsha_8 <= not( ex1_alg_add_p(8) xor ex1_alg_add_c_b(9) ); +res_9: ex1_bsha_9 <= not( ex1_alg_add_p(9) xor ex1_alg_add_c_b(10) ); + + +res_6i: ex1_bsha_6_i <= not ex1_bsha_6 ; +res_7i: ex1_bsha_7_i <= not ex1_bsha_7 ; +res_8i: ex1_bsha_8_i <= not ex1_bsha_8 ; +res_9i: ex1_bsha_9_i <= not ex1_bsha_9 ; + +res_6o: ex1_bsha_6_o <= not ex1_bsha_6_i ; +res_7o: ex1_bsha_7_o <= not ex1_bsha_7_i ; +res_8o: ex1_bsha_8_o <= not ex1_bsha_8_i ; +res_9o: ex1_bsha_9_o <= not ex1_bsha_9_i ; + + +g2_02: ex1_g02_2 <= not( ex1_alg_add_g_b(2) and (ex1_alg_add_t_b(2) or ex1_alg_add_g_b(3)) ); +g2_04: ex1_g02_4 <= not( ex1_alg_add_g_b(4) and (ex1_alg_add_t_b(4) or ex1_alg_add_g_b(5)) ); + +t2_02: ex1_t02_2 <= not( (ex1_alg_add_t_b(2) or ex1_alg_add_t_b(3)) ); +t2_04: ex1_t02_4 <= not( ex1_alg_add_g_b(4) and (ex1_alg_add_t_b(4) or ex1_alg_add_t_b(5)) ); + +g4_02: ex1_g04_2_b <= not( ex1_g02_2 or (ex1_t02_2 and ex1_g02_4 ) ); +t4_02: ex1_t04_2_b <= not( ex1_g02_2 or (ex1_t02_2 and ex1_t02_4 ) ); + + +ones23: ex1_ones_2t3_b <= not( ex1_alg_add_p(2) and ex1_alg_add_p(3) ); +ones45: ex1_ones_4t5_b <= not( ex1_alg_add_p(4) and ex1_alg_add_p(5) ); +ones25: ex1_ones_2t5 <= not( ex1_ones_2t3_b or ex1_ones_4t5_b ); +ones25_b: ex1_ones_2t5_b <= not( ex1_ones_2t5 ); + +z2b: ex1_zero_2_b <= not( ex1_alg_add_p(2) xor ex1_alg_add_t_b(3) ); +z3b: ex1_zero_3_b <= not( ex1_alg_add_p(3) xor ex1_alg_add_t_b(4) ); +z4b: ex1_zero_4_b <= not( ex1_alg_add_p(4) xor ex1_alg_add_t_b(5) ); +z5: ex1_zero_5 <= not( ex1_alg_add_p(5) ); +z5b: ex1_zero_5_b <= not( ex1_zero_5 ); +z23: ex1_zero_2t3 <= not( ex1_zero_2_b or ex1_zero_3_b ); +z45: ex1_zero_4t5 <= not( ex1_zero_4_b or ex1_zero_5_b ); +z25b: ex1_zero_2t5_b <= not( ex1_zero_2t3 and ex1_zero_4t5 ); + + +pco6: pos_if_pco6 <= ( ex1_alg_add_p(1) xor ex1_t04_2_b ); +nco6: pos_if_nco6 <= ( ex1_alg_add_p(1) xor ex1_g04_2_b ); +pco6b: pos_if_pco6_b <= not pos_if_pco6 ; +nco6b: pos_if_nco6_b <= not pos_if_nco6 ; + +unifnc: unf_if_nco6_b <= not( pos_if_nco6 and ex1_zero_2t5_b ); +unifpc: unf_if_pco6_b <= not( pos_if_pco6 and ex1_ones_2t5_b ); + +g8_06b: ex1_g08_6_b <= not ex1_g08_6 ; +shap: ex1_bsha_pos <= not( (pos_if_pco6_b and ex1_g08_6) or (pos_if_nco6_b and ex1_g08_6_b) ); +shovb: ex1_sh_ovf_b <= not( (pos_if_pco6_b and ex1_g08_6) or (pos_if_nco6_b and ex1_g08_6_b) ); +shun: ex1_sh_unf_x <= not( (unf_if_pco6_b and ex1_g08_6) or (unf_if_nco6_b and ex1_g08_6_b) ); +shan: ex1_bsha_neg <= not( ex1_bsha_pos ); +shan2: ex1_bsha_neg_o <= not( ex1_bsha_pos ); +shov: ex1_sh_ovf <= not( ex1_sh_ovf_b ); + + + +d1_0: ex1_lvl1_shdcd000_b <= not( ex1_bsha_12_b and ex1_bsha_13_b ); +d1_1: ex1_lvl1_shdcd001_b <= not( ex1_bsha_12_b and ex1_bsha_13 ); +d1_2: ex1_lvl1_shdcd002_b <= not( ex1_bsha_12 and ex1_bsha_13_b ); +d1_3: ex1_lvl1_shdcd003_b <= not( ex1_bsha_12 and ex1_bsha_13 ); + + +d2_0pg0: ex1_lv2_0pg0_b <= not( ex1_lv2_p10_b and ex1_lv2_g11 and ex1_lv2_ci11n_en ); +d2_0pg1: ex1_lv2_0pg1_b <= not( ex1_lv2_p10_b and ex1_lv2_g11 and ex1_lv2_ci11p_en ); +d2_0pk0: ex1_lv2_0pk0_b <= not( ex1_lv2_p10_b and ex1_lv2_k11 and ex1_lv2_ci11n_en ); +d2_0pk1: ex1_lv2_0pk1_b <= not( ex1_lv2_p10_b and ex1_lv2_k11 and ex1_lv2_ci11p_en ); +d2_0pp0: ex1_lv2_0pp0_b <= not( ex1_lv2_p10_b and ex1_lv2_p11 and ex1_lv2_ci11n_en ); +d2_0pp1: ex1_lv2_0pp1_b <= not( ex1_lv2_p10_b and ex1_lv2_p11 and ex1_lv2_ci11p_en ); +d2_1pg0: ex1_lv2_1pg0_b <= not( ex1_lv2_p10 and ex1_lv2_g11 and ex1_lv2_ci11n_en ); +d2_1pg1: ex1_lv2_1pg1_b <= not( ex1_lv2_p10 and ex1_lv2_g11 and ex1_lv2_ci11p_en ); +d2_1pk0: ex1_lv2_1pk0_b <= not( ex1_lv2_p10 and ex1_lv2_k11 and ex1_lv2_ci11n_en ); +d2_1pk1: ex1_lv2_1pk1_b <= not( ex1_lv2_p10 and ex1_lv2_k11 and ex1_lv2_ci11p_en ); +d2_1pp0: ex1_lv2_1pp0_b <= not( ex1_lv2_p10 and ex1_lv2_p11 and ex1_lv2_ci11n_en ); +d2_1pp1: ex1_lv2_1pp1_b <= not( ex1_lv2_p10 and ex1_lv2_p11 and ex1_lv2_ci11p_en ); + +d2_0: ex1_lv2_shdcd000 <= not( ex1_lv2_0pk0_b and ex1_lv2_1pg0_b and ex1_lv2_1pp1_b ); +d2_1: ex1_lv2_shdcd004 <= not( ex1_lv2_0pp0_b and ex1_lv2_0pk1_b and ex1_lv2_1pg1_b ); +d2_2: ex1_lv2_shdcd008 <= not( ex1_lv2_0pg0_b and ex1_lv2_1pk0_b and ex1_lv2_0pp1_b ); +d2_3: ex1_lv2_shdcd012 <= not( ex1_lv2_1pp0_b and ex1_lv2_0pg1_b and ex1_lv2_1pk1_b ); + +i2_0: ex1_lvl2_shdcd000_b <= not ex1_lv2_shdcd000; +i2_1: ex1_lvl2_shdcd004_b <= not ex1_lv2_shdcd004; +i2_2: ex1_lvl2_shdcd008_b <= not ex1_lv2_shdcd008; +i2_3: ex1_lvl2_shdcd012_b <= not ex1_lv2_shdcd012; + +ii2_0: ex1_lvl2_shdcd000 <= not ex1_lvl2_shdcd000_b; +ii2_1: ex1_lvl2_shdcd004 <= not ex1_lvl2_shdcd004_b; +ii2_2: ex1_lvl2_shdcd008 <= not ex1_lvl2_shdcd008_b; +ii2_3: ex1_lvl2_shdcd012 <= not ex1_lvl2_shdcd012_b; + + + + +i3_6: ex1_bsha_6_b <= not ex1_bsha_6 ; +i3_7: ex1_bsha_7_b <= not ex1_bsha_7 ; +i3_8: ex1_bsha_8_b <= not ex1_bsha_8 ; +i3_9: ex1_bsha_9_b <= not ex1_bsha_9 ; + +d67_0: ex1_67_dcd00_b <= not( ex1_bsha_6_b and ex1_bsha_7_b ); +d67_1: ex1_67_dcd01_b <= not( ex1_bsha_6_b and ex1_bsha_7 ); +d67_2: ex1_67_dcd10_b <= not( ex1_bsha_6 and ex1_bsha_7_b ); +d67_3: ex1_67_dcd11_b <= not( ex1_bsha_6 and ex1_bsha_7 and ex1_bsha_neg ); + +d89_0: ex1_89_dcd00_b <= not( ex1_bsha_8_b and ex1_bsha_9_b and ex1_sel_special_b ); +d89_1: ex1_89_dcd01_b <= not( ex1_bsha_8_b and ex1_bsha_9 and ex1_sel_special_b ); +d89_2: ex1_89_dcd10_b <= not( ex1_bsha_8 and ex1_bsha_9_b and ex1_sel_special_b ); +d89_3: ex1_89_dcd11_b <= not( ex1_bsha_8 and ex1_bsha_9 and ex1_sel_special_b ); + +d3_00: ex1_lvl3_shdcd000 <= not( ex1_67_dcd00_b or ex1_89_dcd00_b ); +d3_01: ex1_lvl3_shdcd016 <= not( ex1_67_dcd00_b or ex1_89_dcd01_b ); +d3_02: ex1_lvl3_shdcd032 <= not( ex1_67_dcd00_b or ex1_89_dcd10_b ); +d3_03: ex1_lvl3_shdcd048 <= not( ex1_67_dcd00_b or ex1_89_dcd11_b ); +d3_04: ex1_lvl3_shdcd064 <= not( ex1_67_dcd01_b or ex1_89_dcd00_b ); +d3_05: ex1_lvl3_shdcd080 <= not( ex1_67_dcd01_b or ex1_89_dcd01_b ); +d3_06: ex1_lvl3_shdcd096 <= not( ex1_67_dcd01_b or ex1_89_dcd10_b ); +d3_07: ex1_lvl3_shdcd112 <= not( ex1_67_dcd01_b or ex1_89_dcd11_b ); +d3_08: ex1_lvl3_shdcd128 <= not( ex1_67_dcd10_b or ex1_89_dcd00_b ); +d3_09: ex1_lvl3_shdcd144 <= not( ex1_67_dcd10_b or ex1_89_dcd01_b ); +d3_10: ex1_lvl3_shdcd160 <= not( ex1_67_dcd10_b or ex1_89_dcd10_b ); +d3_11: ex1_lvl3_shdcd176 <= not( ex1_67_dcd10_b or ex1_89_dcd11_b ); +d3_12: ex1_lvl3_shdcd192 <= not( ex1_67_dcd11_b or ex1_89_dcd00_b ); +d3_13: ex1_lvl3_shdcd208 <= not( ex1_67_dcd11_b or ex1_89_dcd01_b ); +d3_14: ex1_lvl3_shdcd224 <= not( ex1_67_dcd11_b or ex1_89_dcd10_b ); +d3_15: ex1_lvl3_shdcd240 <= not( ex1_67_dcd11_b or ex1_89_dcd11_b ); + + +end; + + + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_alg_bypmux.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_alg_bypmux.vhdl new file mode 100644 index 0000000..a641c57 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_alg_bypmux.vhdl @@ -0,0 +1,111 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + + +entity fuq_alg_bypmux is +generic( expand_type : integer := 2 ); +port( + ex2_byp_sel_byp_neg :in std_ulogic; + ex2_byp_sel_byp_pos :in std_ulogic; + ex2_byp_sel_neg :in std_ulogic; + ex2_byp_sel_pos :in std_ulogic; + ex2_prd_sel_neg_hi :in std_ulogic; + ex2_prd_sel_neg_lo :in std_ulogic; + ex2_prd_sel_neg_lohi :in std_ulogic; + ex2_prd_sel_pos_hi :in std_ulogic; + ex2_prd_sel_pos_lo :in std_ulogic; + ex2_prd_sel_pos_lohi :in std_ulogic; + + ex2_sh_lvl3 :in std_ulogic_vector(0 to 162); + f_fmt_ex2_pass_frac :in std_ulogic_vector(0 to 52); + + f_alg_ex2_res :out std_ulogic_vector(0 to 162) +); + + + +end fuq_alg_bypmux; + +architecture fuq_alg_bypmux of fuq_alg_bypmux is + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal m0_b, m1_b :std_ulogic_vector(0 to 162); + signal ex2_sh_lvl3_b :std_ulogic_vector(0 to 162); + signal f_fmt_ex2_pass_frac_b :std_ulogic_vector(0 to 52); + + + +begin + + + + +i0: ex2_sh_lvl3_b(0 to 162) <= not( ex2_sh_lvl3(0 to 162) ); +i1: f_fmt_ex2_pass_frac_b(0 to 52) <= not( f_fmt_ex2_pass_frac(0 to 52) ); + + +m0_000: m0_b(0 to 52) <= not( ( (0 to 52=> ex2_byp_sel_pos) and ex2_sh_lvl3 (0 to 52) ) or + ( (0 to 52=> ex2_byp_sel_neg) and ex2_sh_lvl3_b (0 to 52) ) ); + +m1_000: m1_b(0 to 52) <= not( ( (0 to 52=> ex2_byp_sel_byp_pos) and f_fmt_ex2_pass_frac (0 to 52) ) or + ( (0 to 52=> ex2_byp_sel_byp_neg) and f_fmt_ex2_pass_frac_b(0 to 52) ) ); + +m0_053: m0_b(53 to 98) <= not( (53 to 98=> ex2_prd_sel_pos_hi) and ex2_sh_lvl3 (53 to 98) ); +m1_053: m1_b(53 to 98) <= not( (53 to 98=> ex2_prd_sel_neg_hi) and ex2_sh_lvl3_b(53 to 98) ); + + +m0_099: m0_b(99 to 130) <= not( (99 to 130=> ex2_prd_sel_pos_lohi) and ex2_sh_lvl3 (99 to 130) ); +m1_099: m1_b(99 to 130) <= not( (99 to 130=> ex2_prd_sel_neg_lohi) and ex2_sh_lvl3_b(99 to 130) ); + + +m0_131: m0_b(131 to 162) <= not( (131 to 162=> ex2_prd_sel_pos_lo) and ex2_sh_lvl3 (131 to 162) ); +m1_131: m1_b(131 to 162) <= not( (131 to 162=> ex2_prd_sel_neg_lo) and ex2_sh_lvl3_b(131 to 162) ); + + +mx: f_alg_ex2_res(0 to 162) <= not( m0_b(0 to 162) and m1_b(0 to 162 ) ); + + + +end; + + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_alg_or16.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_alg_or16.vhdl new file mode 100644 index 0000000..e47b80b --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_alg_or16.vhdl @@ -0,0 +1,182 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + +entity fuq_alg_or16 is +generic( expand_type : integer := 2 ); +port( + ex2_sh_lvl2 :in std_ulogic_vector(0 to 67) ; + ex2_sticky_or16 :out std_ulogic_vector(0 to 4) +); + + + +end fuq_alg_or16; + +architecture fuq_alg_or16 of fuq_alg_or16 is + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + signal ex2_g1o2_b :std_ulogic_vector(0 to 7); + signal ex2_g2o2_b :std_ulogic_vector(0 to 7); + signal ex2_g3o2_b :std_ulogic_vector(0 to 7); + signal ex2_g4o2_b :std_ulogic_vector(0 to 7); + signal ex2_g1o4 :std_ulogic_vector(0 to 3); + signal ex2_g2o4 :std_ulogic_vector(0 to 3); + signal ex2_g3o4 :std_ulogic_vector(0 to 3); + signal ex2_g4o4 :std_ulogic_vector(0 to 3); + signal ex2_g0o8_b :std_ulogic_vector(0 to 1); + signal ex2_g1o8_b :std_ulogic_vector(0 to 1); + signal ex2_g2o8_b :std_ulogic_vector(0 to 1); + signal ex2_g3o8_b :std_ulogic_vector(0 to 1); + signal ex2_g4o8_b :std_ulogic_vector(0 to 1); + signal ex2_o16, ex2_o16_b :std_ulogic_vector(0 to 4); + + + + + + + + + + + +begin + + + +g1o2_0: ex2_g1o2_b(0) <= not( ex2_sh_lvl2( 4) or ex2_sh_lvl2( 5) ); +g1o2_1: ex2_g1o2_b(1) <= not( ex2_sh_lvl2( 6) or ex2_sh_lvl2( 7) ); +g1o2_2: ex2_g1o2_b(2) <= not( ex2_sh_lvl2( 8) or ex2_sh_lvl2( 9) ); +g1o2_3: ex2_g1o2_b(3) <= not( ex2_sh_lvl2(10) or ex2_sh_lvl2(11) ); +g1o2_4: ex2_g1o2_b(4) <= not( ex2_sh_lvl2(12) or ex2_sh_lvl2(13) ); +g1o2_5: ex2_g1o2_b(5) <= not( ex2_sh_lvl2(14) or ex2_sh_lvl2(15) ); +g1o2_6: ex2_g1o2_b(6) <= not( ex2_sh_lvl2(16) or ex2_sh_lvl2(17) ); +g1o2_7: ex2_g1o2_b(7) <= not( ex2_sh_lvl2(18) or ex2_sh_lvl2(19) ); + +g2o2_0: ex2_g2o2_b(0) <= not( ex2_sh_lvl2(20) or ex2_sh_lvl2(21) ); +g2o2_1: ex2_g2o2_b(1) <= not( ex2_sh_lvl2(22) or ex2_sh_lvl2(23) ); +g2o2_2: ex2_g2o2_b(2) <= not( ex2_sh_lvl2(24) or ex2_sh_lvl2(25) ); +g2o2_3: ex2_g2o2_b(3) <= not( ex2_sh_lvl2(26) or ex2_sh_lvl2(27) ); +g2o2_4: ex2_g2o2_b(4) <= not( ex2_sh_lvl2(28) or ex2_sh_lvl2(29) ); +g2o2_5: ex2_g2o2_b(5) <= not( ex2_sh_lvl2(30) or ex2_sh_lvl2(31) ); +g2o2_6: ex2_g2o2_b(6) <= not( ex2_sh_lvl2(32) or ex2_sh_lvl2(33) ); +g2o2_7: ex2_g2o2_b(7) <= not( ex2_sh_lvl2(34) or ex2_sh_lvl2(35) ); + +g3o2_0: ex2_g3o2_b(0) <= not( ex2_sh_lvl2(36) or ex2_sh_lvl2(37) ); +g3o2_1: ex2_g3o2_b(1) <= not( ex2_sh_lvl2(38) or ex2_sh_lvl2(39) ); +g3o2_2: ex2_g3o2_b(2) <= not( ex2_sh_lvl2(40) or ex2_sh_lvl2(41) ); +g3o2_3: ex2_g3o2_b(3) <= not( ex2_sh_lvl2(42) or ex2_sh_lvl2(43) ); +g3o2_4: ex2_g3o2_b(4) <= not( ex2_sh_lvl2(44) or ex2_sh_lvl2(45) ); +g3o2_5: ex2_g3o2_b(5) <= not( ex2_sh_lvl2(46) or ex2_sh_lvl2(47) ); +g3o2_6: ex2_g3o2_b(6) <= not( ex2_sh_lvl2(48) or ex2_sh_lvl2(49) ); +g3o2_7: ex2_g3o2_b(7) <= not( ex2_sh_lvl2(50) or ex2_sh_lvl2(51) ); + +g4o2_0: ex2_g4o2_b(0) <= not( ex2_sh_lvl2(52) or ex2_sh_lvl2(53) ); +g4o2_1: ex2_g4o2_b(1) <= not( ex2_sh_lvl2(54) or ex2_sh_lvl2(55) ); +g4o2_2: ex2_g4o2_b(2) <= not( ex2_sh_lvl2(56) or ex2_sh_lvl2(57) ); +g4o2_3: ex2_g4o2_b(3) <= not( ex2_sh_lvl2(58) or ex2_sh_lvl2(59) ); +g4o2_4: ex2_g4o2_b(4) <= not( ex2_sh_lvl2(60) or ex2_sh_lvl2(61) ); +g4o2_5: ex2_g4o2_b(5) <= not( ex2_sh_lvl2(62) or ex2_sh_lvl2(63) ); +g4o2_6: ex2_g4o2_b(6) <= not( ex2_sh_lvl2(64) or ex2_sh_lvl2(65) ); +g4o2_7: ex2_g4o2_b(7) <= not( ex2_sh_lvl2(66) or ex2_sh_lvl2(67) ); + + +g1o4_0: ex2_g1o4(0) <= not(ex2_g1o2_b(0) and ex2_g1o2_b(1) ); +g1o4_1: ex2_g1o4(1) <= not(ex2_g1o2_b(2) and ex2_g1o2_b(3) ); +g1o4_2: ex2_g1o4(2) <= not(ex2_g1o2_b(4) and ex2_g1o2_b(5) ); +g1o4_3: ex2_g1o4(3) <= not(ex2_g1o2_b(6) and ex2_g1o2_b(7) ); + +g2o4_0: ex2_g2o4(0) <= not(ex2_g2o2_b(0) and ex2_g2o2_b(1) ); +g2o4_1: ex2_g2o4(1) <= not(ex2_g2o2_b(2) and ex2_g2o2_b(3) ); +g2o4_2: ex2_g2o4(2) <= not(ex2_g2o2_b(4) and ex2_g2o2_b(5) ); +g2o4_3: ex2_g2o4(3) <= not(ex2_g2o2_b(6) and ex2_g2o2_b(7) ); + +g3o4_0: ex2_g3o4(0) <= not(ex2_g3o2_b(0) and ex2_g3o2_b(1) ); +g3o4_1: ex2_g3o4(1) <= not(ex2_g3o2_b(2) and ex2_g3o2_b(3) ); +g3o4_2: ex2_g3o4(2) <= not(ex2_g3o2_b(4) and ex2_g3o2_b(5) ); +g3o4_3: ex2_g3o4(3) <= not(ex2_g3o2_b(6) and ex2_g3o2_b(7) ); + +g4o4_0: ex2_g4o4(0) <= not(ex2_g4o2_b(0) and ex2_g4o2_b(1) ); +g4o4_1: ex2_g4o4(1) <= not(ex2_g4o2_b(2) and ex2_g4o2_b(3) ); +g4o4_2: ex2_g4o4(2) <= not(ex2_g4o2_b(4) and ex2_g4o2_b(5) ); +g4o4_3: ex2_g4o4(3) <= not(ex2_g4o2_b(6) and ex2_g4o2_b(7) ); + + +g0o8_0: ex2_g0o8_b(0) <= not( ex2_sh_lvl2( 0) or ex2_sh_lvl2( 1) ); +g0o8_1: ex2_g0o8_b(1) <= not( ex2_sh_lvl2( 2) or ex2_sh_lvl2( 3) ); + +g1o8_0: ex2_g1o8_b(0) <= not( ex2_g1o4(0) or ex2_g1o4(1) ); +g1o8_1: ex2_g1o8_b(1) <= not( ex2_g1o4(2) or ex2_g1o4(3) ); + +g2o8_0: ex2_g2o8_b(0) <= not( ex2_g2o4(0) or ex2_g2o4(1) ); +g2o8_1: ex2_g2o8_b(1) <= not( ex2_g2o4(2) or ex2_g2o4(3) ); + +g3o8_0: ex2_g3o8_b(0) <= not( ex2_g3o4(0) or ex2_g3o4(1) ); +g3o8_1: ex2_g3o8_b(1) <= not( ex2_g3o4(2) or ex2_g3o4(3) ); + +g4o8_0: ex2_g4o8_b(0) <= not( ex2_g4o4(0) or ex2_g4o4(1) ); +g4o8_1: ex2_g4o8_b(1) <= not( ex2_g4o4(2) or ex2_g4o4(3) ); + + +g0o16: ex2_o16(0) <= not(ex2_g0o8_b(0) and ex2_g0o8_b(1) ); +g1o16: ex2_o16(1) <= not(ex2_g1o8_b(0) and ex2_g1o8_b(1) ); +g2o16: ex2_o16(2) <= not(ex2_g2o8_b(0) and ex2_g2o8_b(1) ); +g3o16: ex2_o16(3) <= not(ex2_g3o8_b(0) and ex2_g3o8_b(1) ); +g4o16: ex2_o16(4) <= not(ex2_g4o8_b(0) and ex2_g4o8_b(1) ); + + +g0o16i: ex2_o16_b(0) <= not( ex2_o16(0) ); +g1o16i: ex2_o16_b(1) <= not( ex2_o16(1) ); +g2o16i: ex2_o16_b(2) <= not( ex2_o16(2) ); +g3o16i: ex2_o16_b(3) <= not( ex2_o16(3) ); +g4o16i: ex2_o16_b(4) <= not( ex2_o16(4) ); + + +g0o16ii: ex2_sticky_or16(0) <= not( ex2_o16_b(0) ); +g1o16ii: ex2_sticky_or16(1) <= not( ex2_o16_b(1) ); +g2o16ii: ex2_sticky_or16(2) <= not( ex2_o16_b(2) ); +g3o16ii: ex2_sticky_or16(3) <= not( ex2_o16_b(3) ); +g4o16ii: ex2_sticky_or16(4) <= not( ex2_o16_b(4) ); + +end; + + + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_alg_sh16.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_alg_sh16.vhdl new file mode 100644 index 0000000..d12ac69 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_alg_sh16.vhdl @@ -0,0 +1,976 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + + +entity fuq_alg_sh16 is +generic( expand_type : integer := 2 ); +port( + ex2_lvl3_shdcd000 :in std_ulogic; + ex2_lvl3_shdcd016 :in std_ulogic; + ex2_lvl3_shdcd032 :in std_ulogic; + ex2_lvl3_shdcd048 :in std_ulogic; + ex2_lvl3_shdcd064 :in std_ulogic; + ex2_lvl3_shdcd080 :in std_ulogic; + ex2_lvl3_shdcd096 :in std_ulogic; + ex2_lvl3_shdcd112 :in std_ulogic; + ex2_lvl3_shdcd128 :in std_ulogic; + ex2_lvl3_shdcd144 :in std_ulogic; + ex2_lvl3_shdcd160 :in std_ulogic; + ex2_lvl3_shdcd192 :in std_ulogic; + ex2_lvl3_shdcd208 :in std_ulogic; + ex2_lvl3_shdcd224 :in std_ulogic; + ex2_lvl3_shdcd240 :in std_ulogic; + ex2_sel_special :in std_ulogic; + + ex2_sh_lvl2 :in std_ulogic_vector(0 to 67) ; + + ex2_sh16_162 :out std_ulogic ; + ex2_sh16_163 :out std_ulogic ; + ex2_sh_lvl3 :out std_ulogic_vector(0 to 162) +); + + + +end fuq_alg_sh16; + +architecture fuq_alg_sh16 of fuq_alg_sh16 is + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal ex2_sh16_r1_b, ex2_sh16_r2_b, ex2_sh16_r3_b : std_ulogic_vector(0 to 162); + signal ex2_special :std_ulogic_vector(99 to 162); + + + signal cpx_spc_b :std_ulogic; + signal cpx_000_b :std_ulogic; + signal cpx_016_b :std_ulogic; + signal cpx_032_b :std_ulogic; + signal cpx_048_b :std_ulogic; + signal cpx_064_b :std_ulogic; + signal cpx_080_b :std_ulogic; + signal cpx_096_b :std_ulogic; + signal cpx_112_b :std_ulogic; + signal cpx_128_b :std_ulogic; + signal cpx_144_b :std_ulogic; + signal cpx_160_b :std_ulogic; + signal cpx_192_b :std_ulogic; + signal cpx_208_b :std_ulogic; + signal cpx_224_b :std_ulogic; + signal cpx_240_b :std_ulogic; + signal cp1_spc :std_ulogic; + signal cp1_000 :std_ulogic; + signal cp1_016 :std_ulogic; + signal cp1_032 :std_ulogic; + signal cp1_048 :std_ulogic; + signal cp1_064 :std_ulogic; + signal cp1_080 :std_ulogic; + signal cp1_096 :std_ulogic; + signal cp1_112 :std_ulogic; + signal cp1_128 :std_ulogic; + signal cp1_144 :std_ulogic; + signal cp1_160 :std_ulogic; + signal cp1_192 :std_ulogic; + signal cp1_208 :std_ulogic; + signal cp1_224 :std_ulogic; + signal cp1_240 :std_ulogic; + signal cp2_spc :std_ulogic; + signal cp2_000 :std_ulogic; + signal cp2_016 :std_ulogic; + signal cp2_032 :std_ulogic; + signal cp2_048 :std_ulogic; + signal cp2_064 :std_ulogic; + signal cp2_080 :std_ulogic; + signal cp2_096 :std_ulogic; + signal cp2_112 :std_ulogic; + signal cp2_128 :std_ulogic; + signal cp2_144 :std_ulogic; + signal cp2_208 :std_ulogic; + signal cp2_224 :std_ulogic; + signal cp2_240 :std_ulogic; + signal cp3_spc :std_ulogic; + signal cp3_000 :std_ulogic; + signal cp3_016 :std_ulogic; + signal cp3_032 :std_ulogic; + signal cp3_048 :std_ulogic; + signal cp3_064 :std_ulogic; + signal cp3_080 :std_ulogic; + signal cp3_096 :std_ulogic; + signal cp3_112 :std_ulogic; + signal cp3_128 :std_ulogic; + signal cp3_224 :std_ulogic; + signal cp3_240 :std_ulogic; + signal cp4_spc :std_ulogic; + signal cp4_000 :std_ulogic; + signal cp4_016 :std_ulogic; + signal cp4_032 :std_ulogic; + signal cp4_048 :std_ulogic; + signal cp4_064 :std_ulogic; + signal cp4_080 :std_ulogic; + signal cp4_096 :std_ulogic; + signal cp4_112 :std_ulogic; + signal cp4_240 :std_ulogic; + signal cp5_spc :std_ulogic; + signal cp5_000 :std_ulogic; + signal cp5_016 :std_ulogic; + signal cp5_032 :std_ulogic; + signal cp5_048 :std_ulogic; + signal cp5_064 :std_ulogic; + signal cp5_080 :std_ulogic; + signal cp5_096 :std_ulogic; +signal ex2_sh16_r1_162_b, ex2_sh16_r2_162_b, ex2_sh16_r3_162_b :std_ulogic; +signal ex2_sh16_r1_163_b, ex2_sh16_r2_163_b, ex2_sh16_r3_163_b :std_ulogic; + + + + + + + + + +begin + + + + + + ex2_special(99 to 162) <= ex2_sh_lvl2(0 to 63); + + + + + +cxspcb: cpx_spc_b <= not ex2_sel_special ; +cx000b: cpx_000_b <= not ex2_lvl3_shdcd000 ; +cx016b: cpx_016_b <= not ex2_lvl3_shdcd016 ; +cx032b: cpx_032_b <= not ex2_lvl3_shdcd032 ; +cx048b: cpx_048_b <= not ex2_lvl3_shdcd048 ; +cx064b: cpx_064_b <= not ex2_lvl3_shdcd064 ; +cx080b: cpx_080_b <= not ex2_lvl3_shdcd080 ; +cx096b: cpx_096_b <= not ex2_lvl3_shdcd096 ; +cx112b: cpx_112_b <= not ex2_lvl3_shdcd112 ; +cx128b: cpx_128_b <= not ex2_lvl3_shdcd128 ; +cx144b: cpx_144_b <= not ex2_lvl3_shdcd144 ; +cx160b: cpx_160_b <= not ex2_lvl3_shdcd160 ; +cx192b: cpx_192_b <= not ex2_lvl3_shdcd192 ; +cx208b: cpx_208_b <= not ex2_lvl3_shdcd208 ; +cx224b: cpx_224_b <= not ex2_lvl3_shdcd224 ; +cx240b: cpx_240_b <= not ex2_lvl3_shdcd240 ; + + +c1_spc: cp1_spc <= not cpx_spc_b ; +c1_000: cp1_000 <= not cpx_000_b ; +c1_016: cp1_016 <= not cpx_016_b ; +c1_032: cp1_032 <= not cpx_032_b ; +c1_048: cp1_048 <= not cpx_048_b ; +c1_064: cp1_064 <= not cpx_064_b ; +c1_080: cp1_080 <= not cpx_080_b ; +c1_096: cp1_096 <= not cpx_096_b ; +c1_112: cp1_112 <= not cpx_112_b ; +c1_128: cp1_128 <= not cpx_128_b ; +c1_144: cp1_144 <= not cpx_144_b ; +c1_160: cp1_160 <= not cpx_160_b ; +c1_192: cp1_192 <= not cpx_192_b ; +c1_208: cp1_208 <= not cpx_208_b ; +c1_224: cp1_224 <= not cpx_224_b ; +c1_240: cp1_240 <= not cpx_240_b ; + +c2_spc: cp2_spc <= not cpx_spc_b ; +c2_000: cp2_000 <= not cpx_000_b ; +c2_016: cp2_016 <= not cpx_016_b ; +c2_032: cp2_032 <= not cpx_032_b ; +c2_048: cp2_048 <= not cpx_048_b ; +c2_064: cp2_064 <= not cpx_064_b ; +c2_080: cp2_080 <= not cpx_080_b ; +c2_096: cp2_096 <= not cpx_096_b ; +c2_112: cp2_112 <= not cpx_112_b ; +c2_128: cp2_128 <= not cpx_128_b ; +c2_144: cp2_144 <= not cpx_144_b ; +c2_208: cp2_208 <= not cpx_208_b ; +c2_224: cp2_224 <= not cpx_224_b ; +c2_240: cp2_240 <= not cpx_240_b ; + +c3_spc: cp3_spc <= not cpx_spc_b ; +c3_000: cp3_000 <= not cpx_000_b ; +c3_016: cp3_016 <= not cpx_016_b ; +c3_032: cp3_032 <= not cpx_032_b ; +c3_048: cp3_048 <= not cpx_048_b ; +c3_064: cp3_064 <= not cpx_064_b ; +c3_080: cp3_080 <= not cpx_080_b ; +c3_096: cp3_096 <= not cpx_096_b ; +c3_112: cp3_112 <= not cpx_112_b ; +c3_128: cp3_128 <= not cpx_128_b ; +c3_224: cp3_224 <= not cpx_224_b ; +c3_240: cp3_240 <= not cpx_240_b ; + +c4_spc: cp4_spc <= not cpx_spc_b ; +c4_000: cp4_000 <= not cpx_000_b ; +c4_016: cp4_016 <= not cpx_016_b ; +c4_032: cp4_032 <= not cpx_032_b ; +c4_048: cp4_048 <= not cpx_048_b ; +c4_064: cp4_064 <= not cpx_064_b ; +c4_080: cp4_080 <= not cpx_080_b ; +c4_096: cp4_096 <= not cpx_096_b ; +c4_112: cp4_112 <= not cpx_112_b ; +c4_240: cp4_240 <= not cpx_240_b ; + +c5_spc: cp5_spc <= not cpx_spc_b ; +c5_000: cp5_000 <= not cpx_000_b ; +c5_016: cp5_016 <= not cpx_016_b ; +c5_032: cp5_032 <= not cpx_032_b ; +c5_048: cp5_048 <= not cpx_048_b ; +c5_064: cp5_064 <= not cpx_064_b ; +c5_080: cp5_080 <= not cpx_080_b ; +c5_096: cp5_096 <= not cpx_096_b ; + + + + + +r1_000: ex2_sh16_r1_b(0) <= not( (cp1_192 and ex2_sh_lvl2(64) ) or (cp1_208 and ex2_sh_lvl2(48) ) ); +r1_001: ex2_sh16_r1_b(1) <= not( (cp1_192 and ex2_sh_lvl2(65) ) or (cp1_208 and ex2_sh_lvl2(49) ) ); +r1_002: ex2_sh16_r1_b(2) <= not( (cp1_192 and ex2_sh_lvl2(66) ) or (cp1_208 and ex2_sh_lvl2(50) ) ); +r1_003: ex2_sh16_r1_b(3) <= not( (cp1_192 and ex2_sh_lvl2(67) ) or (cp1_208 and ex2_sh_lvl2(51) ) ); +r1_004: ex2_sh16_r1_b(4) <= not( cp1_208 and ex2_sh_lvl2(52) ); +r1_005: ex2_sh16_r1_b(5) <= not( cp1_208 and ex2_sh_lvl2(53) ); +r1_006: ex2_sh16_r1_b(6) <= not( cp1_208 and ex2_sh_lvl2(54) ); +r1_007: ex2_sh16_r1_b(7) <= not( cp1_208 and ex2_sh_lvl2(55) ); +r1_008: ex2_sh16_r1_b(8) <= not( cp1_208 and ex2_sh_lvl2(56) ); +r1_009: ex2_sh16_r1_b(9) <= not( cp1_208 and ex2_sh_lvl2(57) ); +r1_010: ex2_sh16_r1_b(10) <= not( cp1_208 and ex2_sh_lvl2(58) ); +r1_011: ex2_sh16_r1_b(11) <= not( cp1_208 and ex2_sh_lvl2(59) ); +r1_012: ex2_sh16_r1_b(12) <= not( cp1_208 and ex2_sh_lvl2(60) ); +r1_013: ex2_sh16_r1_b(13) <= not( cp1_208 and ex2_sh_lvl2(61) ); +r1_014: ex2_sh16_r1_b(14) <= not( cp1_208 and ex2_sh_lvl2(62) ); +r1_015: ex2_sh16_r1_b(15) <= not( cp1_208 and ex2_sh_lvl2(63) ); + +r1_016: ex2_sh16_r1_b(16) <= not( (cp2_208 and ex2_sh_lvl2(64) ) or (cp2_224 and ex2_sh_lvl2(48) ) ); +r1_017: ex2_sh16_r1_b(17) <= not( (cp2_208 and ex2_sh_lvl2(65) ) or (cp2_224 and ex2_sh_lvl2(49) ) ); +r1_018: ex2_sh16_r1_b(18) <= not( (cp2_208 and ex2_sh_lvl2(66) ) or (cp2_224 and ex2_sh_lvl2(50) ) ); +r1_019: ex2_sh16_r1_b(19) <= not( (cp2_208 and ex2_sh_lvl2(67) ) or (cp2_224 and ex2_sh_lvl2(51) ) ); +r1_020: ex2_sh16_r1_b(20) <= not( cp2_224 and ex2_sh_lvl2(52) ); +r1_021: ex2_sh16_r1_b(21) <= not( cp2_224 and ex2_sh_lvl2(53) ); +r1_022: ex2_sh16_r1_b(22) <= not( cp2_224 and ex2_sh_lvl2(54) ); +r1_023: ex2_sh16_r1_b(23) <= not( cp2_224 and ex2_sh_lvl2(55) ); +r1_024: ex2_sh16_r1_b(24) <= not( cp2_224 and ex2_sh_lvl2(56) ); +r1_025: ex2_sh16_r1_b(25) <= not( cp2_224 and ex2_sh_lvl2(57) ); +r1_026: ex2_sh16_r1_b(26) <= not( cp2_224 and ex2_sh_lvl2(58) ); +r1_027: ex2_sh16_r1_b(27) <= not( cp2_224 and ex2_sh_lvl2(59) ); +r1_028: ex2_sh16_r1_b(28) <= not( cp2_224 and ex2_sh_lvl2(60) ); +r1_029: ex2_sh16_r1_b(29) <= not( cp2_224 and ex2_sh_lvl2(61) ); +r1_030: ex2_sh16_r1_b(30) <= not( cp2_224 and ex2_sh_lvl2(62) ); +r1_031: ex2_sh16_r1_b(31) <= not( cp2_224 and ex2_sh_lvl2(63) ); + +r1_032: ex2_sh16_r1_b(32) <= not( (cp3_224 and ex2_sh_lvl2(64) ) or (cp3_240 and ex2_sh_lvl2(48) ) ); +r1_033: ex2_sh16_r1_b(33) <= not( (cp3_224 and ex2_sh_lvl2(65) ) or (cp3_240 and ex2_sh_lvl2(49) ) ); +r1_034: ex2_sh16_r1_b(34) <= not( (cp3_224 and ex2_sh_lvl2(66) ) or (cp3_240 and ex2_sh_lvl2(50) ) ); +r1_035: ex2_sh16_r1_b(35) <= not( (cp3_224 and ex2_sh_lvl2(67) ) or (cp3_240 and ex2_sh_lvl2(51) ) ); +r1_036: ex2_sh16_r1_b(36) <= not( cp3_240 and ex2_sh_lvl2(52) ); +r1_037: ex2_sh16_r1_b(37) <= not( cp3_240 and ex2_sh_lvl2(53) ); +r1_038: ex2_sh16_r1_b(38) <= not( cp3_240 and ex2_sh_lvl2(54) ); +r1_039: ex2_sh16_r1_b(39) <= not( cp3_240 and ex2_sh_lvl2(55) ); +r1_040: ex2_sh16_r1_b(40) <= not( cp3_240 and ex2_sh_lvl2(56) ); +r1_041: ex2_sh16_r1_b(41) <= not( cp3_240 and ex2_sh_lvl2(57) ); +r1_042: ex2_sh16_r1_b(42) <= not( cp3_240 and ex2_sh_lvl2(58) ); +r1_043: ex2_sh16_r1_b(43) <= not( cp3_240 and ex2_sh_lvl2(59) ); +r1_044: ex2_sh16_r1_b(44) <= not( cp3_240 and ex2_sh_lvl2(60) ); +r1_045: ex2_sh16_r1_b(45) <= not( cp3_240 and ex2_sh_lvl2(61) ); +r1_046: ex2_sh16_r1_b(46) <= not( cp3_240 and ex2_sh_lvl2(62) ); +r1_047: ex2_sh16_r1_b(47) <= not( cp3_240 and ex2_sh_lvl2(63) ); + +r1_048: ex2_sh16_r1_b(48) <= not( (cp4_240 and ex2_sh_lvl2(64) ) or (cp4_000 and ex2_sh_lvl2(48) ) ); +r1_049: ex2_sh16_r1_b(49) <= not( (cp4_240 and ex2_sh_lvl2(65) ) or (cp4_000 and ex2_sh_lvl2(49) ) ); +r1_050: ex2_sh16_r1_b(50) <= not( (cp4_240 and ex2_sh_lvl2(66) ) or (cp4_000 and ex2_sh_lvl2(50) ) ); +r1_051: ex2_sh16_r1_b(51) <= not( (cp4_240 and ex2_sh_lvl2(67) ) or (cp4_000 and ex2_sh_lvl2(51) ) ); +r1_052: ex2_sh16_r1_b(52) <= not( cp4_000 and ex2_sh_lvl2(52) ); +r1_053: ex2_sh16_r1_b(53) <= not( cp4_000 and ex2_sh_lvl2(53) ); +r1_054: ex2_sh16_r1_b(54) <= not( cp4_000 and ex2_sh_lvl2(54) ); +r1_055: ex2_sh16_r1_b(55) <= not( cp4_000 and ex2_sh_lvl2(55) ); +r1_056: ex2_sh16_r1_b(56) <= not( cp4_000 and ex2_sh_lvl2(56) ); +r1_057: ex2_sh16_r1_b(57) <= not( cp4_000 and ex2_sh_lvl2(57) ); +r1_058: ex2_sh16_r1_b(58) <= not( cp4_000 and ex2_sh_lvl2(58) ); +r1_059: ex2_sh16_r1_b(59) <= not( cp4_000 and ex2_sh_lvl2(59) ); +r1_060: ex2_sh16_r1_b(60) <= not( cp4_000 and ex2_sh_lvl2(60) ); +r1_061: ex2_sh16_r1_b(61) <= not( cp4_000 and ex2_sh_lvl2(61) ); +r1_062: ex2_sh16_r1_b(62) <= not( cp4_000 and ex2_sh_lvl2(62) ); +r1_063: ex2_sh16_r1_b(63) <= not( cp4_000 and ex2_sh_lvl2(63) ); + +r1_064: ex2_sh16_r1_b(64) <= not( (cp5_000 and ex2_sh_lvl2(64) ) or (cp4_016 and ex2_sh_lvl2(48) ) ); +r1_065: ex2_sh16_r1_b(65) <= not( (cp5_000 and ex2_sh_lvl2(65) ) or (cp4_016 and ex2_sh_lvl2(49) ) ); +r1_066: ex2_sh16_r1_b(66) <= not( (cp5_000 and ex2_sh_lvl2(66) ) or (cp4_016 and ex2_sh_lvl2(50) ) ); +r1_067: ex2_sh16_r1_b(67) <= not( (cp5_000 and ex2_sh_lvl2(67) ) or (cp4_016 and ex2_sh_lvl2(51) ) ); +r1_068: ex2_sh16_r1_b(68) <= not( cp4_016 and ex2_sh_lvl2(52) ); +r1_069: ex2_sh16_r1_b(69) <= not( cp4_016 and ex2_sh_lvl2(53) ); +r1_070: ex2_sh16_r1_b(70) <= not( cp4_016 and ex2_sh_lvl2(54) ); +r1_071: ex2_sh16_r1_b(71) <= not( cp4_016 and ex2_sh_lvl2(55) ); +r1_072: ex2_sh16_r1_b(72) <= not( cp4_016 and ex2_sh_lvl2(56) ); +r1_073: ex2_sh16_r1_b(73) <= not( cp4_016 and ex2_sh_lvl2(57) ); +r1_074: ex2_sh16_r1_b(74) <= not( cp4_016 and ex2_sh_lvl2(58) ); +r1_075: ex2_sh16_r1_b(75) <= not( cp4_016 and ex2_sh_lvl2(59) ); +r1_076: ex2_sh16_r1_b(76) <= not( cp4_016 and ex2_sh_lvl2(60) ); +r1_077: ex2_sh16_r1_b(77) <= not( cp4_016 and ex2_sh_lvl2(61) ); +r1_078: ex2_sh16_r1_b(78) <= not( cp4_016 and ex2_sh_lvl2(62) ); +r1_079: ex2_sh16_r1_b(79) <= not( cp4_016 and ex2_sh_lvl2(63) ); + +r1_080: ex2_sh16_r1_b(80) <= not( (cp5_016 and ex2_sh_lvl2(64) ) or (cp4_032 and ex2_sh_lvl2(48) ) ); +r1_081: ex2_sh16_r1_b(81) <= not( (cp5_016 and ex2_sh_lvl2(65) ) or (cp4_032 and ex2_sh_lvl2(49) ) ); +r1_082: ex2_sh16_r1_b(82) <= not( (cp5_016 and ex2_sh_lvl2(66) ) or (cp4_032 and ex2_sh_lvl2(50) ) ); +r1_083: ex2_sh16_r1_b(83) <= not( (cp5_016 and ex2_sh_lvl2(67) ) or (cp4_032 and ex2_sh_lvl2(51) ) ); +r1_084: ex2_sh16_r1_b(84) <= not( cp4_032 and ex2_sh_lvl2(52) ); +r1_085: ex2_sh16_r1_b(85) <= not( cp4_032 and ex2_sh_lvl2(53) ); +r1_086: ex2_sh16_r1_b(86) <= not( cp4_032 and ex2_sh_lvl2(54) ); +r1_087: ex2_sh16_r1_b(87) <= not( cp4_032 and ex2_sh_lvl2(55) ); +r1_088: ex2_sh16_r1_b(88) <= not( cp4_032 and ex2_sh_lvl2(56) ); +r1_089: ex2_sh16_r1_b(89) <= not( cp4_032 and ex2_sh_lvl2(57) ); +r1_090: ex2_sh16_r1_b(90) <= not( cp4_032 and ex2_sh_lvl2(58) ); +r1_091: ex2_sh16_r1_b(91) <= not( cp4_032 and ex2_sh_lvl2(59) ); +r1_092: ex2_sh16_r1_b(92) <= not( cp4_032 and ex2_sh_lvl2(60) ); +r1_093: ex2_sh16_r1_b(93) <= not( cp4_032 and ex2_sh_lvl2(61) ); +r1_094: ex2_sh16_r1_b(94) <= not( cp4_032 and ex2_sh_lvl2(62) ); +r1_095: ex2_sh16_r1_b(95) <= not( cp4_032 and ex2_sh_lvl2(63) ); + +r1_096: ex2_sh16_r1_b(96) <= not( (cp5_032 and ex2_sh_lvl2(64) ) or (cp4_048 and ex2_sh_lvl2(48) ) ); +r1_097: ex2_sh16_r1_b(97) <= not( (cp5_032 and ex2_sh_lvl2(65) ) or (cp4_048 and ex2_sh_lvl2(49) ) ); +r1_098: ex2_sh16_r1_b(98) <= not( (cp5_032 and ex2_sh_lvl2(66) ) or (cp4_048 and ex2_sh_lvl2(50) ) ); +r1_099: ex2_sh16_r1_b(99) <= not( (cp5_032 and ex2_sh_lvl2(67) ) or (cp4_048 and ex2_sh_lvl2(51) ) ); +r1_100: ex2_sh16_r1_b(100) <= not( cp4_048 and ex2_sh_lvl2(52) ); +r1_101: ex2_sh16_r1_b(101) <= not( cp4_048 and ex2_sh_lvl2(53) ); +r1_102: ex2_sh16_r1_b(102) <= not( cp4_048 and ex2_sh_lvl2(54) ); +r1_103: ex2_sh16_r1_b(103) <= not( cp4_048 and ex2_sh_lvl2(55) ); +r1_104: ex2_sh16_r1_b(104) <= not( cp4_048 and ex2_sh_lvl2(56) ); +r1_105: ex2_sh16_r1_b(105) <= not( cp4_048 and ex2_sh_lvl2(57) ); +r1_106: ex2_sh16_r1_b(106) <= not( cp4_048 and ex2_sh_lvl2(58) ); +r1_107: ex2_sh16_r1_b(107) <= not( cp4_048 and ex2_sh_lvl2(59) ); +r1_108: ex2_sh16_r1_b(108) <= not( cp4_048 and ex2_sh_lvl2(60) ); +r1_109: ex2_sh16_r1_b(109) <= not( cp4_048 and ex2_sh_lvl2(61) ); +r1_110: ex2_sh16_r1_b(110) <= not( cp4_048 and ex2_sh_lvl2(62) ); +r1_111: ex2_sh16_r1_b(111) <= not( cp4_048 and ex2_sh_lvl2(63) ); + +r1_112: ex2_sh16_r1_b(112) <= not( (cp5_048 and ex2_sh_lvl2(64) ) or (cp4_064 and ex2_sh_lvl2(48) ) ); +r1_113: ex2_sh16_r1_b(113) <= not( (cp5_048 and ex2_sh_lvl2(65) ) or (cp4_064 and ex2_sh_lvl2(49) ) ); +r1_114: ex2_sh16_r1_b(114) <= not( (cp5_048 and ex2_sh_lvl2(66) ) or (cp4_064 and ex2_sh_lvl2(50) ) ); +r1_115: ex2_sh16_r1_b(115) <= not( (cp5_048 and ex2_sh_lvl2(67) ) or (cp4_064 and ex2_sh_lvl2(51) ) ); +r1_116: ex2_sh16_r1_b(116) <= not( cp4_064 and ex2_sh_lvl2(52) ); +r1_117: ex2_sh16_r1_b(117) <= not( cp4_064 and ex2_sh_lvl2(53) ); +r1_118: ex2_sh16_r1_b(118) <= not( cp4_064 and ex2_sh_lvl2(54) ); +r1_119: ex2_sh16_r1_b(119) <= not( cp4_064 and ex2_sh_lvl2(55) ); +r1_120: ex2_sh16_r1_b(120) <= not( cp4_064 and ex2_sh_lvl2(56) ); +r1_121: ex2_sh16_r1_b(121) <= not( cp4_064 and ex2_sh_lvl2(57) ); +r1_122: ex2_sh16_r1_b(122) <= not( cp4_064 and ex2_sh_lvl2(58) ); +r1_123: ex2_sh16_r1_b(123) <= not( cp4_064 and ex2_sh_lvl2(59) ); +r1_124: ex2_sh16_r1_b(124) <= not( cp4_064 and ex2_sh_lvl2(60) ); +r1_125: ex2_sh16_r1_b(125) <= not( cp4_064 and ex2_sh_lvl2(61) ); +r1_126: ex2_sh16_r1_b(126) <= not( cp4_064 and ex2_sh_lvl2(62) ); +r1_127: ex2_sh16_r1_b(127) <= not( cp4_064 and ex2_sh_lvl2(63) ); + +r1_128: ex2_sh16_r1_b(128) <= not( (cp5_064 and ex2_sh_lvl2(64) ) or (cp4_080 and ex2_sh_lvl2(48) ) ); +r1_129: ex2_sh16_r1_b(129) <= not( (cp5_064 and ex2_sh_lvl2(65) ) or (cp4_080 and ex2_sh_lvl2(49) ) ); +r1_130: ex2_sh16_r1_b(130) <= not( (cp5_064 and ex2_sh_lvl2(66) ) or (cp4_080 and ex2_sh_lvl2(50) ) ); +r1_131: ex2_sh16_r1_b(131) <= not( (cp5_064 and ex2_sh_lvl2(67) ) or (cp4_080 and ex2_sh_lvl2(51) ) ); +r1_132: ex2_sh16_r1_b(132) <= not( cp4_080 and ex2_sh_lvl2(52) ); +r1_133: ex2_sh16_r1_b(133) <= not( cp4_080 and ex2_sh_lvl2(53) ); +r1_134: ex2_sh16_r1_b(134) <= not( cp4_080 and ex2_sh_lvl2(54) ); +r1_135: ex2_sh16_r1_b(135) <= not( cp4_080 and ex2_sh_lvl2(55) ); +r1_136: ex2_sh16_r1_b(136) <= not( cp4_080 and ex2_sh_lvl2(56) ); +r1_137: ex2_sh16_r1_b(137) <= not( cp4_080 and ex2_sh_lvl2(57) ); +r1_138: ex2_sh16_r1_b(138) <= not( cp4_080 and ex2_sh_lvl2(58) ); +r1_139: ex2_sh16_r1_b(139) <= not( cp4_080 and ex2_sh_lvl2(59) ); +r1_140: ex2_sh16_r1_b(140) <= not( cp4_080 and ex2_sh_lvl2(60) ); +r1_141: ex2_sh16_r1_b(141) <= not( cp4_080 and ex2_sh_lvl2(61) ); +r1_142: ex2_sh16_r1_b(142) <= not( cp4_080 and ex2_sh_lvl2(62) ); +r1_143: ex2_sh16_r1_b(143) <= not( cp4_080 and ex2_sh_lvl2(63) ); + +r1_144: ex2_sh16_r1_b(144) <= not( (cp5_080 and ex2_sh_lvl2(64) ) or (cp4_096 and ex2_sh_lvl2(48) ) ); +r1_145: ex2_sh16_r1_b(145) <= not( (cp5_080 and ex2_sh_lvl2(65) ) or (cp4_096 and ex2_sh_lvl2(49) ) ); +r1_146: ex2_sh16_r1_b(146) <= not( (cp5_080 and ex2_sh_lvl2(66) ) or (cp4_096 and ex2_sh_lvl2(50) ) ); +r1_147: ex2_sh16_r1_b(147) <= not( (cp5_080 and ex2_sh_lvl2(67) ) or (cp4_096 and ex2_sh_lvl2(51) ) ); +r1_148: ex2_sh16_r1_b(148) <= not( cp4_096 and ex2_sh_lvl2(52) ); +r1_149: ex2_sh16_r1_b(149) <= not( cp4_096 and ex2_sh_lvl2(53) ); +r1_150: ex2_sh16_r1_b(150) <= not( cp4_096 and ex2_sh_lvl2(54) ); +r1_151: ex2_sh16_r1_b(151) <= not( cp4_096 and ex2_sh_lvl2(55) ); +r1_152: ex2_sh16_r1_b(152) <= not( cp4_096 and ex2_sh_lvl2(56) ); +r1_153: ex2_sh16_r1_b(153) <= not( cp4_096 and ex2_sh_lvl2(57) ); +r1_154: ex2_sh16_r1_b(154) <= not( cp4_096 and ex2_sh_lvl2(58) ); +r1_155: ex2_sh16_r1_b(155) <= not( cp4_096 and ex2_sh_lvl2(59) ); +r1_156: ex2_sh16_r1_b(156) <= not( cp4_096 and ex2_sh_lvl2(60) ); +r1_157: ex2_sh16_r1_b(157) <= not( cp4_096 and ex2_sh_lvl2(61) ); +r1_158: ex2_sh16_r1_b(158) <= not( cp4_096 and ex2_sh_lvl2(62) ); +r1_159: ex2_sh16_r1_b(159) <= not( cp4_096 and ex2_sh_lvl2(63) ); + +r1_160: ex2_sh16_r1_b(160) <= not( (cp5_096 and ex2_sh_lvl2(64) ) or (cp4_112 and ex2_sh_lvl2(48) ) ); +r1_161: ex2_sh16_r1_b(161) <= not( (cp5_096 and ex2_sh_lvl2(65) ) or (cp4_112 and ex2_sh_lvl2(49) ) ); +r1_162: ex2_sh16_r1_b(162) <= not( (cp5_096 and ex2_sh_lvl2(66) ) or (cp4_112 and ex2_sh_lvl2(50) ) ); + +r2_000: ex2_sh16_r2_b(0) <= not( (cp1_224 and ex2_sh_lvl2(32) ) or (cp1_240 and ex2_sh_lvl2(16) ) ); +r2_001: ex2_sh16_r2_b(1) <= not( (cp1_224 and ex2_sh_lvl2(33) ) or (cp1_240 and ex2_sh_lvl2(17) ) ); +r2_002: ex2_sh16_r2_b(2) <= not( (cp1_224 and ex2_sh_lvl2(34) ) or (cp1_240 and ex2_sh_lvl2(18) ) ); +r2_003: ex2_sh16_r2_b(3) <= not( (cp1_224 and ex2_sh_lvl2(35) ) or (cp1_240 and ex2_sh_lvl2(19) ) ); +r2_004: ex2_sh16_r2_b(4) <= not( (cp1_224 and ex2_sh_lvl2(36) ) or (cp1_240 and ex2_sh_lvl2(20) ) ); +r2_005: ex2_sh16_r2_b(5) <= not( (cp1_224 and ex2_sh_lvl2(37) ) or (cp1_240 and ex2_sh_lvl2(21) ) ); +r2_006: ex2_sh16_r2_b(6) <= not( (cp1_224 and ex2_sh_lvl2(38) ) or (cp1_240 and ex2_sh_lvl2(22) ) ); +r2_007: ex2_sh16_r2_b(7) <= not( (cp1_224 and ex2_sh_lvl2(39) ) or (cp1_240 and ex2_sh_lvl2(23) ) ); +r2_008: ex2_sh16_r2_b(8) <= not( (cp1_224 and ex2_sh_lvl2(40) ) or (cp1_240 and ex2_sh_lvl2(24) ) ); +r2_009: ex2_sh16_r2_b(9) <= not( (cp1_224 and ex2_sh_lvl2(41) ) or (cp1_240 and ex2_sh_lvl2(25) ) ); +r2_010: ex2_sh16_r2_b(10) <= not( (cp1_224 and ex2_sh_lvl2(42) ) or (cp1_240 and ex2_sh_lvl2(26) ) ); +r2_011: ex2_sh16_r2_b(11) <= not( (cp1_224 and ex2_sh_lvl2(43) ) or (cp1_240 and ex2_sh_lvl2(27) ) ); +r2_012: ex2_sh16_r2_b(12) <= not( (cp1_224 and ex2_sh_lvl2(44) ) or (cp1_240 and ex2_sh_lvl2(28) ) ); +r2_013: ex2_sh16_r2_b(13) <= not( (cp1_224 and ex2_sh_lvl2(45) ) or (cp1_240 and ex2_sh_lvl2(29) ) ); +r2_014: ex2_sh16_r2_b(14) <= not( (cp1_224 and ex2_sh_lvl2(46) ) or (cp1_240 and ex2_sh_lvl2(30) ) ); +r2_015: ex2_sh16_r2_b(15) <= not( (cp1_224 and ex2_sh_lvl2(47) ) or (cp1_240 and ex2_sh_lvl2(31) ) ); + +r2_016: ex2_sh16_r2_b(16) <= not( (cp2_240 and ex2_sh_lvl2(32) ) or (cp2_000 and ex2_sh_lvl2(16) ) ); +r2_017: ex2_sh16_r2_b(17) <= not( (cp2_240 and ex2_sh_lvl2(33) ) or (cp2_000 and ex2_sh_lvl2(17) ) ); +r2_018: ex2_sh16_r2_b(18) <= not( (cp2_240 and ex2_sh_lvl2(34) ) or (cp2_000 and ex2_sh_lvl2(18) ) ); +r2_019: ex2_sh16_r2_b(19) <= not( (cp2_240 and ex2_sh_lvl2(35) ) or (cp2_000 and ex2_sh_lvl2(19) ) ); +r2_020: ex2_sh16_r2_b(20) <= not( (cp2_240 and ex2_sh_lvl2(36) ) or (cp2_000 and ex2_sh_lvl2(20) ) ); +r2_021: ex2_sh16_r2_b(21) <= not( (cp2_240 and ex2_sh_lvl2(37) ) or (cp2_000 and ex2_sh_lvl2(21) ) ); +r2_022: ex2_sh16_r2_b(22) <= not( (cp2_240 and ex2_sh_lvl2(38) ) or (cp2_000 and ex2_sh_lvl2(22) ) ); +r2_023: ex2_sh16_r2_b(23) <= not( (cp2_240 and ex2_sh_lvl2(39) ) or (cp2_000 and ex2_sh_lvl2(23) ) ); +r2_024: ex2_sh16_r2_b(24) <= not( (cp2_240 and ex2_sh_lvl2(40) ) or (cp2_000 and ex2_sh_lvl2(24) ) ); +r2_025: ex2_sh16_r2_b(25) <= not( (cp2_240 and ex2_sh_lvl2(41) ) or (cp2_000 and ex2_sh_lvl2(25) ) ); +r2_026: ex2_sh16_r2_b(26) <= not( (cp2_240 and ex2_sh_lvl2(42) ) or (cp2_000 and ex2_sh_lvl2(26) ) ); +r2_027: ex2_sh16_r2_b(27) <= not( (cp2_240 and ex2_sh_lvl2(43) ) or (cp2_000 and ex2_sh_lvl2(27) ) ); +r2_028: ex2_sh16_r2_b(28) <= not( (cp2_240 and ex2_sh_lvl2(44) ) or (cp2_000 and ex2_sh_lvl2(28) ) ); +r2_029: ex2_sh16_r2_b(29) <= not( (cp2_240 and ex2_sh_lvl2(45) ) or (cp2_000 and ex2_sh_lvl2(29) ) ); +r2_030: ex2_sh16_r2_b(30) <= not( (cp2_240 and ex2_sh_lvl2(46) ) or (cp2_000 and ex2_sh_lvl2(30) ) ); +r2_031: ex2_sh16_r2_b(31) <= not( (cp2_240 and ex2_sh_lvl2(47) ) or (cp2_000 and ex2_sh_lvl2(31) ) ); + +r2_032: ex2_sh16_r2_b(32) <= not( (cp3_000 and ex2_sh_lvl2(32) ) or (cp2_016 and ex2_sh_lvl2(16) ) ); +r2_033: ex2_sh16_r2_b(33) <= not( (cp3_000 and ex2_sh_lvl2(33) ) or (cp2_016 and ex2_sh_lvl2(17) ) ); +r2_034: ex2_sh16_r2_b(34) <= not( (cp3_000 and ex2_sh_lvl2(34) ) or (cp2_016 and ex2_sh_lvl2(18) ) ); +r2_035: ex2_sh16_r2_b(35) <= not( (cp3_000 and ex2_sh_lvl2(35) ) or (cp2_016 and ex2_sh_lvl2(19) ) ); +r2_036: ex2_sh16_r2_b(36) <= not( (cp3_000 and ex2_sh_lvl2(36) ) or (cp2_016 and ex2_sh_lvl2(20) ) ); +r2_037: ex2_sh16_r2_b(37) <= not( (cp3_000 and ex2_sh_lvl2(37) ) or (cp2_016 and ex2_sh_lvl2(21) ) ); +r2_038: ex2_sh16_r2_b(38) <= not( (cp3_000 and ex2_sh_lvl2(38) ) or (cp2_016 and ex2_sh_lvl2(22) ) ); +r2_039: ex2_sh16_r2_b(39) <= not( (cp3_000 and ex2_sh_lvl2(39) ) or (cp2_016 and ex2_sh_lvl2(23) ) ); +r2_040: ex2_sh16_r2_b(40) <= not( (cp3_000 and ex2_sh_lvl2(40) ) or (cp2_016 and ex2_sh_lvl2(24) ) ); +r2_041: ex2_sh16_r2_b(41) <= not( (cp3_000 and ex2_sh_lvl2(41) ) or (cp2_016 and ex2_sh_lvl2(25) ) ); +r2_042: ex2_sh16_r2_b(42) <= not( (cp3_000 and ex2_sh_lvl2(42) ) or (cp2_016 and ex2_sh_lvl2(26) ) ); +r2_043: ex2_sh16_r2_b(43) <= not( (cp3_000 and ex2_sh_lvl2(43) ) or (cp2_016 and ex2_sh_lvl2(27) ) ); +r2_044: ex2_sh16_r2_b(44) <= not( (cp3_000 and ex2_sh_lvl2(44) ) or (cp2_016 and ex2_sh_lvl2(28) ) ); +r2_045: ex2_sh16_r2_b(45) <= not( (cp3_000 and ex2_sh_lvl2(45) ) or (cp2_016 and ex2_sh_lvl2(29) ) ); +r2_046: ex2_sh16_r2_b(46) <= not( (cp3_000 and ex2_sh_lvl2(46) ) or (cp2_016 and ex2_sh_lvl2(30) ) ); +r2_047: ex2_sh16_r2_b(47) <= not( (cp3_000 and ex2_sh_lvl2(47) ) or (cp2_016 and ex2_sh_lvl2(31) ) ); + +r2_048: ex2_sh16_r2_b(48) <= not( (cp3_016 and ex2_sh_lvl2(32) ) or (cp2_032 and ex2_sh_lvl2(16) ) ); +r2_049: ex2_sh16_r2_b(49) <= not( (cp3_016 and ex2_sh_lvl2(33) ) or (cp2_032 and ex2_sh_lvl2(17) ) ); +r2_050: ex2_sh16_r2_b(50) <= not( (cp3_016 and ex2_sh_lvl2(34) ) or (cp2_032 and ex2_sh_lvl2(18) ) ); +r2_051: ex2_sh16_r2_b(51) <= not( (cp3_016 and ex2_sh_lvl2(35) ) or (cp2_032 and ex2_sh_lvl2(19) ) ); +r2_052: ex2_sh16_r2_b(52) <= not( (cp3_016 and ex2_sh_lvl2(36) ) or (cp2_032 and ex2_sh_lvl2(20) ) ); +r2_053: ex2_sh16_r2_b(53) <= not( (cp3_016 and ex2_sh_lvl2(37) ) or (cp2_032 and ex2_sh_lvl2(21) ) ); +r2_054: ex2_sh16_r2_b(54) <= not( (cp3_016 and ex2_sh_lvl2(38) ) or (cp2_032 and ex2_sh_lvl2(22) ) ); +r2_055: ex2_sh16_r2_b(55) <= not( (cp3_016 and ex2_sh_lvl2(39) ) or (cp2_032 and ex2_sh_lvl2(23) ) ); +r2_056: ex2_sh16_r2_b(56) <= not( (cp3_016 and ex2_sh_lvl2(40) ) or (cp2_032 and ex2_sh_lvl2(24) ) ); +r2_057: ex2_sh16_r2_b(57) <= not( (cp3_016 and ex2_sh_lvl2(41) ) or (cp2_032 and ex2_sh_lvl2(25) ) ); +r2_058: ex2_sh16_r2_b(58) <= not( (cp3_016 and ex2_sh_lvl2(42) ) or (cp2_032 and ex2_sh_lvl2(26) ) ); +r2_059: ex2_sh16_r2_b(59) <= not( (cp3_016 and ex2_sh_lvl2(43) ) or (cp2_032 and ex2_sh_lvl2(27) ) ); +r2_060: ex2_sh16_r2_b(60) <= not( (cp3_016 and ex2_sh_lvl2(44) ) or (cp2_032 and ex2_sh_lvl2(28) ) ); +r2_061: ex2_sh16_r2_b(61) <= not( (cp3_016 and ex2_sh_lvl2(45) ) or (cp2_032 and ex2_sh_lvl2(29) ) ); +r2_062: ex2_sh16_r2_b(62) <= not( (cp3_016 and ex2_sh_lvl2(46) ) or (cp2_032 and ex2_sh_lvl2(30) ) ); +r2_063: ex2_sh16_r2_b(63) <= not( (cp3_016 and ex2_sh_lvl2(47) ) or (cp2_032 and ex2_sh_lvl2(31) ) ); + +r2_064: ex2_sh16_r2_b(64) <= not( (cp3_032 and ex2_sh_lvl2(32) ) or (cp2_048 and ex2_sh_lvl2(16) ) ); +r2_065: ex2_sh16_r2_b(65) <= not( (cp3_032 and ex2_sh_lvl2(33) ) or (cp2_048 and ex2_sh_lvl2(17) ) ); +r2_066: ex2_sh16_r2_b(66) <= not( (cp3_032 and ex2_sh_lvl2(34) ) or (cp2_048 and ex2_sh_lvl2(18) ) ); +r2_067: ex2_sh16_r2_b(67) <= not( (cp3_032 and ex2_sh_lvl2(35) ) or (cp2_048 and ex2_sh_lvl2(19) ) ); +r2_068: ex2_sh16_r2_b(68) <= not( (cp3_032 and ex2_sh_lvl2(36) ) or (cp2_048 and ex2_sh_lvl2(20) ) ); +r2_069: ex2_sh16_r2_b(69) <= not( (cp3_032 and ex2_sh_lvl2(37) ) or (cp2_048 and ex2_sh_lvl2(21) ) ); +r2_070: ex2_sh16_r2_b(70) <= not( (cp3_032 and ex2_sh_lvl2(38) ) or (cp2_048 and ex2_sh_lvl2(22) ) ); +r2_071: ex2_sh16_r2_b(71) <= not( (cp3_032 and ex2_sh_lvl2(39) ) or (cp2_048 and ex2_sh_lvl2(23) ) ); +r2_072: ex2_sh16_r2_b(72) <= not( (cp3_032 and ex2_sh_lvl2(40) ) or (cp2_048 and ex2_sh_lvl2(24) ) ); +r2_073: ex2_sh16_r2_b(73) <= not( (cp3_032 and ex2_sh_lvl2(41) ) or (cp2_048 and ex2_sh_lvl2(25) ) ); +r2_074: ex2_sh16_r2_b(74) <= not( (cp3_032 and ex2_sh_lvl2(42) ) or (cp2_048 and ex2_sh_lvl2(26) ) ); +r2_075: ex2_sh16_r2_b(75) <= not( (cp3_032 and ex2_sh_lvl2(43) ) or (cp2_048 and ex2_sh_lvl2(27) ) ); +r2_076: ex2_sh16_r2_b(76) <= not( (cp3_032 and ex2_sh_lvl2(44) ) or (cp2_048 and ex2_sh_lvl2(28) ) ); +r2_077: ex2_sh16_r2_b(77) <= not( (cp3_032 and ex2_sh_lvl2(45) ) or (cp2_048 and ex2_sh_lvl2(29) ) ); +r2_078: ex2_sh16_r2_b(78) <= not( (cp3_032 and ex2_sh_lvl2(46) ) or (cp2_048 and ex2_sh_lvl2(30) ) ); +r2_079: ex2_sh16_r2_b(79) <= not( (cp3_032 and ex2_sh_lvl2(47) ) or (cp2_048 and ex2_sh_lvl2(31) ) ); + +r2_080: ex2_sh16_r2_b(80) <= not( (cp3_048 and ex2_sh_lvl2(32) ) or (cp2_064 and ex2_sh_lvl2(16) ) ); +r2_081: ex2_sh16_r2_b(81) <= not( (cp3_048 and ex2_sh_lvl2(33) ) or (cp2_064 and ex2_sh_lvl2(17) ) ); +r2_082: ex2_sh16_r2_b(82) <= not( (cp3_048 and ex2_sh_lvl2(34) ) or (cp2_064 and ex2_sh_lvl2(18) ) ); +r2_083: ex2_sh16_r2_b(83) <= not( (cp3_048 and ex2_sh_lvl2(35) ) or (cp2_064 and ex2_sh_lvl2(19) ) ); +r2_084: ex2_sh16_r2_b(84) <= not( (cp3_048 and ex2_sh_lvl2(36) ) or (cp2_064 and ex2_sh_lvl2(20) ) ); +r2_085: ex2_sh16_r2_b(85) <= not( (cp3_048 and ex2_sh_lvl2(37) ) or (cp2_064 and ex2_sh_lvl2(21) ) ); +r2_086: ex2_sh16_r2_b(86) <= not( (cp3_048 and ex2_sh_lvl2(38) ) or (cp2_064 and ex2_sh_lvl2(22) ) ); +r2_087: ex2_sh16_r2_b(87) <= not( (cp3_048 and ex2_sh_lvl2(39) ) or (cp2_064 and ex2_sh_lvl2(23) ) ); +r2_088: ex2_sh16_r2_b(88) <= not( (cp3_048 and ex2_sh_lvl2(40) ) or (cp2_064 and ex2_sh_lvl2(24) ) ); +r2_089: ex2_sh16_r2_b(89) <= not( (cp3_048 and ex2_sh_lvl2(41) ) or (cp2_064 and ex2_sh_lvl2(25) ) ); +r2_090: ex2_sh16_r2_b(90) <= not( (cp3_048 and ex2_sh_lvl2(42) ) or (cp2_064 and ex2_sh_lvl2(26) ) ); +r2_091: ex2_sh16_r2_b(91) <= not( (cp3_048 and ex2_sh_lvl2(43) ) or (cp2_064 and ex2_sh_lvl2(27) ) ); +r2_092: ex2_sh16_r2_b(92) <= not( (cp3_048 and ex2_sh_lvl2(44) ) or (cp2_064 and ex2_sh_lvl2(28) ) ); +r2_093: ex2_sh16_r2_b(93) <= not( (cp3_048 and ex2_sh_lvl2(45) ) or (cp2_064 and ex2_sh_lvl2(29) ) ); +r2_094: ex2_sh16_r2_b(94) <= not( (cp3_048 and ex2_sh_lvl2(46) ) or (cp2_064 and ex2_sh_lvl2(30) ) ); +r2_095: ex2_sh16_r2_b(95) <= not( (cp3_048 and ex2_sh_lvl2(47) ) or (cp2_064 and ex2_sh_lvl2(31) ) ); + +r2_096: ex2_sh16_r2_b(96) <= not( (cp3_064 and ex2_sh_lvl2(32) ) or (cp2_080 and ex2_sh_lvl2(16) ) ); +r2_097: ex2_sh16_r2_b(97) <= not( (cp3_064 and ex2_sh_lvl2(33) ) or (cp2_080 and ex2_sh_lvl2(17) ) ); +r2_098: ex2_sh16_r2_b(98) <= not( (cp3_064 and ex2_sh_lvl2(34) ) or (cp2_080 and ex2_sh_lvl2(18) ) ); +r2_099: ex2_sh16_r2_b(99) <= not( (cp3_064 and ex2_sh_lvl2(35) ) or (cp2_080 and ex2_sh_lvl2(19) ) ); +r2_100: ex2_sh16_r2_b(100) <= not( (cp3_064 and ex2_sh_lvl2(36) ) or (cp2_080 and ex2_sh_lvl2(20) ) ); +r2_101: ex2_sh16_r2_b(101) <= not( (cp3_064 and ex2_sh_lvl2(37) ) or (cp2_080 and ex2_sh_lvl2(21) ) ); +r2_102: ex2_sh16_r2_b(102) <= not( (cp3_064 and ex2_sh_lvl2(38) ) or (cp2_080 and ex2_sh_lvl2(22) ) ); +r2_103: ex2_sh16_r2_b(103) <= not( (cp3_064 and ex2_sh_lvl2(39) ) or (cp2_080 and ex2_sh_lvl2(23) ) ); +r2_104: ex2_sh16_r2_b(104) <= not( (cp3_064 and ex2_sh_lvl2(40) ) or (cp2_080 and ex2_sh_lvl2(24) ) ); +r2_105: ex2_sh16_r2_b(105) <= not( (cp3_064 and ex2_sh_lvl2(41) ) or (cp2_080 and ex2_sh_lvl2(25) ) ); +r2_106: ex2_sh16_r2_b(106) <= not( (cp3_064 and ex2_sh_lvl2(42) ) or (cp2_080 and ex2_sh_lvl2(26) ) ); +r2_107: ex2_sh16_r2_b(107) <= not( (cp3_064 and ex2_sh_lvl2(43) ) or (cp2_080 and ex2_sh_lvl2(27) ) ); +r2_108: ex2_sh16_r2_b(108) <= not( (cp3_064 and ex2_sh_lvl2(44) ) or (cp2_080 and ex2_sh_lvl2(28) ) ); +r2_109: ex2_sh16_r2_b(109) <= not( (cp3_064 and ex2_sh_lvl2(45) ) or (cp2_080 and ex2_sh_lvl2(29) ) ); +r2_110: ex2_sh16_r2_b(110) <= not( (cp3_064 and ex2_sh_lvl2(46) ) or (cp2_080 and ex2_sh_lvl2(30) ) ); +r2_111: ex2_sh16_r2_b(111) <= not( (cp3_064 and ex2_sh_lvl2(47) ) or (cp2_080 and ex2_sh_lvl2(31) ) ); + +r2_112: ex2_sh16_r2_b(112) <= not( (cp3_080 and ex2_sh_lvl2(32) ) or (cp2_096 and ex2_sh_lvl2(16) ) ); +r2_113: ex2_sh16_r2_b(113) <= not( (cp3_080 and ex2_sh_lvl2(33) ) or (cp2_096 and ex2_sh_lvl2(17) ) ); +r2_114: ex2_sh16_r2_b(114) <= not( (cp3_080 and ex2_sh_lvl2(34) ) or (cp2_096 and ex2_sh_lvl2(18) ) ); +r2_115: ex2_sh16_r2_b(115) <= not( (cp3_080 and ex2_sh_lvl2(35) ) or (cp2_096 and ex2_sh_lvl2(19) ) ); +r2_116: ex2_sh16_r2_b(116) <= not( (cp3_080 and ex2_sh_lvl2(36) ) or (cp2_096 and ex2_sh_lvl2(20) ) ); +r2_117: ex2_sh16_r2_b(117) <= not( (cp3_080 and ex2_sh_lvl2(37) ) or (cp2_096 and ex2_sh_lvl2(21) ) ); +r2_118: ex2_sh16_r2_b(118) <= not( (cp3_080 and ex2_sh_lvl2(38) ) or (cp2_096 and ex2_sh_lvl2(22) ) ); +r2_119: ex2_sh16_r2_b(119) <= not( (cp3_080 and ex2_sh_lvl2(39) ) or (cp2_096 and ex2_sh_lvl2(23) ) ); +r2_120: ex2_sh16_r2_b(120) <= not( (cp3_080 and ex2_sh_lvl2(40) ) or (cp2_096 and ex2_sh_lvl2(24) ) ); +r2_121: ex2_sh16_r2_b(121) <= not( (cp3_080 and ex2_sh_lvl2(41) ) or (cp2_096 and ex2_sh_lvl2(25) ) ); +r2_122: ex2_sh16_r2_b(122) <= not( (cp3_080 and ex2_sh_lvl2(42) ) or (cp2_096 and ex2_sh_lvl2(26) ) ); +r2_123: ex2_sh16_r2_b(123) <= not( (cp3_080 and ex2_sh_lvl2(43) ) or (cp2_096 and ex2_sh_lvl2(27) ) ); +r2_124: ex2_sh16_r2_b(124) <= not( (cp3_080 and ex2_sh_lvl2(44) ) or (cp2_096 and ex2_sh_lvl2(28) ) ); +r2_125: ex2_sh16_r2_b(125) <= not( (cp3_080 and ex2_sh_lvl2(45) ) or (cp2_096 and ex2_sh_lvl2(29) ) ); +r2_126: ex2_sh16_r2_b(126) <= not( (cp3_080 and ex2_sh_lvl2(46) ) or (cp2_096 and ex2_sh_lvl2(30) ) ); +r2_127: ex2_sh16_r2_b(127) <= not( (cp3_080 and ex2_sh_lvl2(47) ) or (cp2_096 and ex2_sh_lvl2(31) ) ); + +r2_128: ex2_sh16_r2_b(128) <= not( (cp3_096 and ex2_sh_lvl2(32) ) or (cp2_112 and ex2_sh_lvl2(16) ) ); +r2_129: ex2_sh16_r2_b(129) <= not( (cp3_096 and ex2_sh_lvl2(33) ) or (cp2_112 and ex2_sh_lvl2(17) ) ); +r2_130: ex2_sh16_r2_b(130) <= not( (cp3_096 and ex2_sh_lvl2(34) ) or (cp2_112 and ex2_sh_lvl2(18) ) ); +r2_131: ex2_sh16_r2_b(131) <= not( (cp3_096 and ex2_sh_lvl2(35) ) or (cp2_112 and ex2_sh_lvl2(19) ) ); +r2_132: ex2_sh16_r2_b(132) <= not( (cp3_096 and ex2_sh_lvl2(36) ) or (cp2_112 and ex2_sh_lvl2(20) ) ); +r2_133: ex2_sh16_r2_b(133) <= not( (cp3_096 and ex2_sh_lvl2(37) ) or (cp2_112 and ex2_sh_lvl2(21) ) ); +r2_134: ex2_sh16_r2_b(134) <= not( (cp3_096 and ex2_sh_lvl2(38) ) or (cp2_112 and ex2_sh_lvl2(22) ) ); +r2_135: ex2_sh16_r2_b(135) <= not( (cp3_096 and ex2_sh_lvl2(39) ) or (cp2_112 and ex2_sh_lvl2(23) ) ); +r2_136: ex2_sh16_r2_b(136) <= not( (cp3_096 and ex2_sh_lvl2(40) ) or (cp2_112 and ex2_sh_lvl2(24) ) ); +r2_137: ex2_sh16_r2_b(137) <= not( (cp3_096 and ex2_sh_lvl2(41) ) or (cp2_112 and ex2_sh_lvl2(25) ) ); +r2_138: ex2_sh16_r2_b(138) <= not( (cp3_096 and ex2_sh_lvl2(42) ) or (cp2_112 and ex2_sh_lvl2(26) ) ); +r2_139: ex2_sh16_r2_b(139) <= not( (cp3_096 and ex2_sh_lvl2(43) ) or (cp2_112 and ex2_sh_lvl2(27) ) ); +r2_140: ex2_sh16_r2_b(140) <= not( (cp3_096 and ex2_sh_lvl2(44) ) or (cp2_112 and ex2_sh_lvl2(28) ) ); +r2_141: ex2_sh16_r2_b(141) <= not( (cp3_096 and ex2_sh_lvl2(45) ) or (cp2_112 and ex2_sh_lvl2(29) ) ); +r2_142: ex2_sh16_r2_b(142) <= not( (cp3_096 and ex2_sh_lvl2(46) ) or (cp2_112 and ex2_sh_lvl2(30) ) ); +r2_143: ex2_sh16_r2_b(143) <= not( (cp3_096 and ex2_sh_lvl2(47) ) or (cp2_112 and ex2_sh_lvl2(31) ) ); + +r2_144: ex2_sh16_r2_b(144) <= not( (cp3_112 and ex2_sh_lvl2(32) ) or (cp2_128 and ex2_sh_lvl2(16) ) ); +r2_145: ex2_sh16_r2_b(145) <= not( (cp3_112 and ex2_sh_lvl2(33) ) or (cp2_128 and ex2_sh_lvl2(17) ) ); +r2_146: ex2_sh16_r2_b(146) <= not( (cp3_112 and ex2_sh_lvl2(34) ) or (cp2_128 and ex2_sh_lvl2(18) ) ); +r2_147: ex2_sh16_r2_b(147) <= not( (cp3_112 and ex2_sh_lvl2(35) ) or (cp2_128 and ex2_sh_lvl2(19) ) ); +r2_148: ex2_sh16_r2_b(148) <= not( (cp3_112 and ex2_sh_lvl2(36) ) or (cp2_128 and ex2_sh_lvl2(20) ) ); +r2_149: ex2_sh16_r2_b(149) <= not( (cp3_112 and ex2_sh_lvl2(37) ) or (cp2_128 and ex2_sh_lvl2(21) ) ); +r2_150: ex2_sh16_r2_b(150) <= not( (cp3_112 and ex2_sh_lvl2(38) ) or (cp2_128 and ex2_sh_lvl2(22) ) ); +r2_151: ex2_sh16_r2_b(151) <= not( (cp3_112 and ex2_sh_lvl2(39) ) or (cp2_128 and ex2_sh_lvl2(23) ) ); +r2_152: ex2_sh16_r2_b(152) <= not( (cp3_112 and ex2_sh_lvl2(40) ) or (cp2_128 and ex2_sh_lvl2(24) ) ); +r2_153: ex2_sh16_r2_b(153) <= not( (cp3_112 and ex2_sh_lvl2(41) ) or (cp2_128 and ex2_sh_lvl2(25) ) ); +r2_154: ex2_sh16_r2_b(154) <= not( (cp3_112 and ex2_sh_lvl2(42) ) or (cp2_128 and ex2_sh_lvl2(26) ) ); +r2_155: ex2_sh16_r2_b(155) <= not( (cp3_112 and ex2_sh_lvl2(43) ) or (cp2_128 and ex2_sh_lvl2(27) ) ); +r2_156: ex2_sh16_r2_b(156) <= not( (cp3_112 and ex2_sh_lvl2(44) ) or (cp2_128 and ex2_sh_lvl2(28) ) ); +r2_157: ex2_sh16_r2_b(157) <= not( (cp3_112 and ex2_sh_lvl2(45) ) or (cp2_128 and ex2_sh_lvl2(29) ) ); +r2_158: ex2_sh16_r2_b(158) <= not( (cp3_112 and ex2_sh_lvl2(46) ) or (cp2_128 and ex2_sh_lvl2(30) ) ); +r2_159: ex2_sh16_r2_b(159) <= not( (cp3_112 and ex2_sh_lvl2(47) ) or (cp2_128 and ex2_sh_lvl2(31) ) ); + +r2_160: ex2_sh16_r2_b(160) <= not( (cp3_128 and ex2_sh_lvl2(32) ) or (cp2_144 and ex2_sh_lvl2(16) ) ); +r2_161: ex2_sh16_r2_b(161) <= not( (cp3_128 and ex2_sh_lvl2(33) ) or (cp2_144 and ex2_sh_lvl2(17) ) ); +r2_162: ex2_sh16_r2_b(162) <= not( (cp3_128 and ex2_sh_lvl2(34) ) or (cp2_144 and ex2_sh_lvl2(18) ) ); + +r3_000: ex2_sh16_r3_b(0) <= not( cp1_000 and ex2_sh_lvl2(0) ); +r3_001: ex2_sh16_r3_b(1) <= not( cp1_000 and ex2_sh_lvl2(1) ); +r3_002: ex2_sh16_r3_b(2) <= not( cp1_000 and ex2_sh_lvl2(2) ); +r3_003: ex2_sh16_r3_b(3) <= not( cp1_000 and ex2_sh_lvl2(3) ); +r3_004: ex2_sh16_r3_b(4) <= not( cp1_000 and ex2_sh_lvl2(4) ); +r3_005: ex2_sh16_r3_b(5) <= not( cp1_000 and ex2_sh_lvl2(5) ); +r3_006: ex2_sh16_r3_b(6) <= not( cp1_000 and ex2_sh_lvl2(6) ); +r3_007: ex2_sh16_r3_b(7) <= not( cp1_000 and ex2_sh_lvl2(7) ); +r3_008: ex2_sh16_r3_b(8) <= not( cp1_000 and ex2_sh_lvl2(8) ); +r3_009: ex2_sh16_r3_b(9) <= not( cp1_000 and ex2_sh_lvl2(9) ); +r3_010: ex2_sh16_r3_b(10) <= not( cp1_000 and ex2_sh_lvl2(10) ); +r3_011: ex2_sh16_r3_b(11) <= not( cp1_000 and ex2_sh_lvl2(11) ); +r3_012: ex2_sh16_r3_b(12) <= not( cp1_000 and ex2_sh_lvl2(12) ); +r3_013: ex2_sh16_r3_b(13) <= not( cp1_000 and ex2_sh_lvl2(13) ); +r3_014: ex2_sh16_r3_b(14) <= not( cp1_000 and ex2_sh_lvl2(14) ); +r3_015: ex2_sh16_r3_b(15) <= not( cp1_000 and ex2_sh_lvl2(15) ); + +r3_016: ex2_sh16_r3_b(16) <= not( cp1_016 and ex2_sh_lvl2(0) ); +r3_017: ex2_sh16_r3_b(17) <= not( cp1_016 and ex2_sh_lvl2(1) ); +r3_018: ex2_sh16_r3_b(18) <= not( cp1_016 and ex2_sh_lvl2(2) ); +r3_019: ex2_sh16_r3_b(19) <= not( cp1_016 and ex2_sh_lvl2(3) ); +r3_020: ex2_sh16_r3_b(20) <= not( cp1_016 and ex2_sh_lvl2(4) ); +r3_021: ex2_sh16_r3_b(21) <= not( cp1_016 and ex2_sh_lvl2(5) ); +r3_022: ex2_sh16_r3_b(22) <= not( cp1_016 and ex2_sh_lvl2(6) ); +r3_023: ex2_sh16_r3_b(23) <= not( cp1_016 and ex2_sh_lvl2(7) ); +r3_024: ex2_sh16_r3_b(24) <= not( cp1_016 and ex2_sh_lvl2(8) ); +r3_025: ex2_sh16_r3_b(25) <= not( cp1_016 and ex2_sh_lvl2(9) ); +r3_026: ex2_sh16_r3_b(26) <= not( cp1_016 and ex2_sh_lvl2(10) ); +r3_027: ex2_sh16_r3_b(27) <= not( cp1_016 and ex2_sh_lvl2(11) ); +r3_028: ex2_sh16_r3_b(28) <= not( cp1_016 and ex2_sh_lvl2(12) ); +r3_029: ex2_sh16_r3_b(29) <= not( cp1_016 and ex2_sh_lvl2(13) ); +r3_030: ex2_sh16_r3_b(30) <= not( cp1_016 and ex2_sh_lvl2(14) ); +r3_031: ex2_sh16_r3_b(31) <= not( cp1_016 and ex2_sh_lvl2(15) ); + +r3_032: ex2_sh16_r3_b(32) <= not( cp1_032 and ex2_sh_lvl2(0) ); +r3_033: ex2_sh16_r3_b(33) <= not( cp1_032 and ex2_sh_lvl2(1) ); +r3_034: ex2_sh16_r3_b(34) <= not( cp1_032 and ex2_sh_lvl2(2) ); +r3_035: ex2_sh16_r3_b(35) <= not( cp1_032 and ex2_sh_lvl2(3) ); +r3_036: ex2_sh16_r3_b(36) <= not( cp1_032 and ex2_sh_lvl2(4) ); +r3_037: ex2_sh16_r3_b(37) <= not( cp1_032 and ex2_sh_lvl2(5) ); +r3_038: ex2_sh16_r3_b(38) <= not( cp1_032 and ex2_sh_lvl2(6) ); +r3_039: ex2_sh16_r3_b(39) <= not( cp1_032 and ex2_sh_lvl2(7) ); +r3_040: ex2_sh16_r3_b(40) <= not( cp1_032 and ex2_sh_lvl2(8) ); +r3_041: ex2_sh16_r3_b(41) <= not( cp1_032 and ex2_sh_lvl2(9) ); +r3_042: ex2_sh16_r3_b(42) <= not( cp1_032 and ex2_sh_lvl2(10) ); +r3_043: ex2_sh16_r3_b(43) <= not( cp1_032 and ex2_sh_lvl2(11) ); +r3_044: ex2_sh16_r3_b(44) <= not( cp1_032 and ex2_sh_lvl2(12) ); +r3_045: ex2_sh16_r3_b(45) <= not( cp1_032 and ex2_sh_lvl2(13) ); +r3_046: ex2_sh16_r3_b(46) <= not( cp1_032 and ex2_sh_lvl2(14) ); +r3_047: ex2_sh16_r3_b(47) <= not( cp1_032 and ex2_sh_lvl2(15) ); + +r3_048: ex2_sh16_r3_b(48) <= not( cp1_048 and ex2_sh_lvl2(0) ); +r3_049: ex2_sh16_r3_b(49) <= not( cp1_048 and ex2_sh_lvl2(1) ); +r3_050: ex2_sh16_r3_b(50) <= not( cp1_048 and ex2_sh_lvl2(2) ); +r3_051: ex2_sh16_r3_b(51) <= not( cp1_048 and ex2_sh_lvl2(3) ); +r3_052: ex2_sh16_r3_b(52) <= not( cp1_048 and ex2_sh_lvl2(4) ); +r3_053: ex2_sh16_r3_b(53) <= not( cp1_048 and ex2_sh_lvl2(5) ); +r3_054: ex2_sh16_r3_b(54) <= not( cp1_048 and ex2_sh_lvl2(6) ); +r3_055: ex2_sh16_r3_b(55) <= not( cp1_048 and ex2_sh_lvl2(7) ); +r3_056: ex2_sh16_r3_b(56) <= not( cp1_048 and ex2_sh_lvl2(8) ); +r3_057: ex2_sh16_r3_b(57) <= not( cp1_048 and ex2_sh_lvl2(9) ); +r3_058: ex2_sh16_r3_b(58) <= not( cp1_048 and ex2_sh_lvl2(10) ); +r3_059: ex2_sh16_r3_b(59) <= not( cp1_048 and ex2_sh_lvl2(11) ); +r3_060: ex2_sh16_r3_b(60) <= not( cp1_048 and ex2_sh_lvl2(12) ); +r3_061: ex2_sh16_r3_b(61) <= not( cp1_048 and ex2_sh_lvl2(13) ); +r3_062: ex2_sh16_r3_b(62) <= not( cp1_048 and ex2_sh_lvl2(14) ); +r3_063: ex2_sh16_r3_b(63) <= not( cp1_048 and ex2_sh_lvl2(15) ); + +r3_064: ex2_sh16_r3_b(64) <= not( cp1_064 and ex2_sh_lvl2(0) ); +r3_065: ex2_sh16_r3_b(65) <= not( cp1_064 and ex2_sh_lvl2(1) ); +r3_066: ex2_sh16_r3_b(66) <= not( cp1_064 and ex2_sh_lvl2(2) ); +r3_067: ex2_sh16_r3_b(67) <= not( cp1_064 and ex2_sh_lvl2(3) ); +r3_068: ex2_sh16_r3_b(68) <= not( cp1_064 and ex2_sh_lvl2(4) ); +r3_069: ex2_sh16_r3_b(69) <= not( cp1_064 and ex2_sh_lvl2(5) ); +r3_070: ex2_sh16_r3_b(70) <= not( cp1_064 and ex2_sh_lvl2(6) ); +r3_071: ex2_sh16_r3_b(71) <= not( cp1_064 and ex2_sh_lvl2(7) ); +r3_072: ex2_sh16_r3_b(72) <= not( cp1_064 and ex2_sh_lvl2(8) ); +r3_073: ex2_sh16_r3_b(73) <= not( cp1_064 and ex2_sh_lvl2(9) ); +r3_074: ex2_sh16_r3_b(74) <= not( cp1_064 and ex2_sh_lvl2(10) ); +r3_075: ex2_sh16_r3_b(75) <= not( cp1_064 and ex2_sh_lvl2(11) ); +r3_076: ex2_sh16_r3_b(76) <= not( cp1_064 and ex2_sh_lvl2(12) ); +r3_077: ex2_sh16_r3_b(77) <= not( cp1_064 and ex2_sh_lvl2(13) ); +r3_078: ex2_sh16_r3_b(78) <= not( cp1_064 and ex2_sh_lvl2(14) ); +r3_079: ex2_sh16_r3_b(79) <= not( cp1_064 and ex2_sh_lvl2(15) ); + +r3_080: ex2_sh16_r3_b(80) <= not( cp1_080 and ex2_sh_lvl2(0) ); +r3_081: ex2_sh16_r3_b(81) <= not( cp1_080 and ex2_sh_lvl2(1) ); +r3_082: ex2_sh16_r3_b(82) <= not( cp1_080 and ex2_sh_lvl2(2) ); +r3_083: ex2_sh16_r3_b(83) <= not( cp1_080 and ex2_sh_lvl2(3) ); +r3_084: ex2_sh16_r3_b(84) <= not( cp1_080 and ex2_sh_lvl2(4) ); +r3_085: ex2_sh16_r3_b(85) <= not( cp1_080 and ex2_sh_lvl2(5) ); +r3_086: ex2_sh16_r3_b(86) <= not( cp1_080 and ex2_sh_lvl2(6) ); +r3_087: ex2_sh16_r3_b(87) <= not( cp1_080 and ex2_sh_lvl2(7) ); +r3_088: ex2_sh16_r3_b(88) <= not( cp1_080 and ex2_sh_lvl2(8) ); +r3_089: ex2_sh16_r3_b(89) <= not( cp1_080 and ex2_sh_lvl2(9) ); +r3_090: ex2_sh16_r3_b(90) <= not( cp1_080 and ex2_sh_lvl2(10) ); +r3_091: ex2_sh16_r3_b(91) <= not( cp1_080 and ex2_sh_lvl2(11) ); +r3_092: ex2_sh16_r3_b(92) <= not( cp1_080 and ex2_sh_lvl2(12) ); +r3_093: ex2_sh16_r3_b(93) <= not( cp1_080 and ex2_sh_lvl2(13) ); +r3_094: ex2_sh16_r3_b(94) <= not( cp1_080 and ex2_sh_lvl2(14) ); +r3_095: ex2_sh16_r3_b(95) <= not( cp1_080 and ex2_sh_lvl2(15) ); + +r3_096: ex2_sh16_r3_b(96) <= not( cp1_096 and ex2_sh_lvl2(0) ) ; +r3_097: ex2_sh16_r3_b(97) <= not( cp1_096 and ex2_sh_lvl2(1) ) ; +r3_098: ex2_sh16_r3_b(98) <= not( cp1_096 and ex2_sh_lvl2(2) ) ; +r3_099: ex2_sh16_r3_b(99) <= not( (cp1_096 and ex2_sh_lvl2(3) ) or (cp1_spc and ex2_special(99) ) ); +r3_100: ex2_sh16_r3_b(100) <= not( (cp1_096 and ex2_sh_lvl2(4) ) or (cp1_spc and ex2_special(100) ) ); +r3_101: ex2_sh16_r3_b(101) <= not( (cp1_096 and ex2_sh_lvl2(5) ) or (cp1_spc and ex2_special(101) ) ); +r3_102: ex2_sh16_r3_b(102) <= not( (cp1_096 and ex2_sh_lvl2(6) ) or (cp1_spc and ex2_special(102) ) ); +r3_103: ex2_sh16_r3_b(103) <= not( (cp1_096 and ex2_sh_lvl2(7) ) or (cp1_spc and ex2_special(103) ) ); +r3_104: ex2_sh16_r3_b(104) <= not( (cp1_096 and ex2_sh_lvl2(8) ) or (cp1_spc and ex2_special(104) ) ); +r3_105: ex2_sh16_r3_b(105) <= not( (cp1_096 and ex2_sh_lvl2(9) ) or (cp1_spc and ex2_special(105) ) ); +r3_106: ex2_sh16_r3_b(106) <= not( (cp1_096 and ex2_sh_lvl2(10) ) or (cp1_spc and ex2_special(106) ) ); +r3_107: ex2_sh16_r3_b(107) <= not( (cp1_096 and ex2_sh_lvl2(11) ) or (cp1_spc and ex2_special(107) ) ); +r3_108: ex2_sh16_r3_b(108) <= not( (cp1_096 and ex2_sh_lvl2(12) ) or (cp1_spc and ex2_special(108) ) ); +r3_109: ex2_sh16_r3_b(109) <= not( (cp1_096 and ex2_sh_lvl2(13) ) or (cp1_spc and ex2_special(109) ) ); +r3_110: ex2_sh16_r3_b(110) <= not( (cp1_096 and ex2_sh_lvl2(14) ) or (cp1_spc and ex2_special(110) ) ); +r3_111: ex2_sh16_r3_b(111) <= not( (cp1_096 and ex2_sh_lvl2(15) ) or (cp1_spc and ex2_special(111) ) ); + +r3_112: ex2_sh16_r3_b(112) <= not( (cp1_112 and ex2_sh_lvl2(0) ) or (cp2_spc and ex2_special(112) ) ); +r3_113: ex2_sh16_r3_b(113) <= not( (cp1_112 and ex2_sh_lvl2(1) ) or (cp2_spc and ex2_special(113) ) ); +r3_114: ex2_sh16_r3_b(114) <= not( (cp1_112 and ex2_sh_lvl2(2) ) or (cp2_spc and ex2_special(114) ) ); +r3_115: ex2_sh16_r3_b(115) <= not( (cp1_112 and ex2_sh_lvl2(3) ) or (cp2_spc and ex2_special(115) ) ); +r3_116: ex2_sh16_r3_b(116) <= not( (cp1_112 and ex2_sh_lvl2(4) ) or (cp2_spc and ex2_special(116) ) ); +r3_117: ex2_sh16_r3_b(117) <= not( (cp1_112 and ex2_sh_lvl2(5) ) or (cp2_spc and ex2_special(117) ) ); +r3_118: ex2_sh16_r3_b(118) <= not( (cp1_112 and ex2_sh_lvl2(6) ) or (cp2_spc and ex2_special(118) ) ); +r3_119: ex2_sh16_r3_b(119) <= not( (cp1_112 and ex2_sh_lvl2(7) ) or (cp2_spc and ex2_special(119) ) ); +r3_120: ex2_sh16_r3_b(120) <= not( (cp1_112 and ex2_sh_lvl2(8) ) or (cp2_spc and ex2_special(120) ) ); +r3_121: ex2_sh16_r3_b(121) <= not( (cp1_112 and ex2_sh_lvl2(9) ) or (cp2_spc and ex2_special(121) ) ); +r3_122: ex2_sh16_r3_b(122) <= not( (cp1_112 and ex2_sh_lvl2(10) ) or (cp2_spc and ex2_special(122) ) ); +r3_123: ex2_sh16_r3_b(123) <= not( (cp1_112 and ex2_sh_lvl2(11) ) or (cp2_spc and ex2_special(123) ) ); +r3_124: ex2_sh16_r3_b(124) <= not( (cp1_112 and ex2_sh_lvl2(12) ) or (cp2_spc and ex2_special(124) ) ); +r3_125: ex2_sh16_r3_b(125) <= not( (cp1_112 and ex2_sh_lvl2(13) ) or (cp2_spc and ex2_special(125) ) ); +r3_126: ex2_sh16_r3_b(126) <= not( (cp1_112 and ex2_sh_lvl2(14) ) or (cp2_spc and ex2_special(126) ) ); +r3_127: ex2_sh16_r3_b(127) <= not( (cp1_112 and ex2_sh_lvl2(15) ) or (cp2_spc and ex2_special(127) ) ); + +r3_128: ex2_sh16_r3_b(128) <= not( (cp1_128 and ex2_sh_lvl2(0) ) or (cp3_spc and ex2_special(128) ) ); +r3_129: ex2_sh16_r3_b(129) <= not( (cp1_128 and ex2_sh_lvl2(1) ) or (cp3_spc and ex2_special(129) ) ); +r3_130: ex2_sh16_r3_b(130) <= not( (cp1_128 and ex2_sh_lvl2(2) ) or (cp3_spc and ex2_special(130) ) ); +r3_131: ex2_sh16_r3_b(131) <= not( (cp1_128 and ex2_sh_lvl2(3) ) or (cp3_spc and ex2_special(131) ) ); +r3_132: ex2_sh16_r3_b(132) <= not( (cp1_128 and ex2_sh_lvl2(4) ) or (cp3_spc and ex2_special(132) ) ); +r3_133: ex2_sh16_r3_b(133) <= not( (cp1_128 and ex2_sh_lvl2(5) ) or (cp3_spc and ex2_special(133) ) ); +r3_134: ex2_sh16_r3_b(134) <= not( (cp1_128 and ex2_sh_lvl2(6) ) or (cp3_spc and ex2_special(134) ) ); +r3_135: ex2_sh16_r3_b(135) <= not( (cp1_128 and ex2_sh_lvl2(7) ) or (cp3_spc and ex2_special(135) ) ); +r3_136: ex2_sh16_r3_b(136) <= not( (cp1_128 and ex2_sh_lvl2(8) ) or (cp3_spc and ex2_special(136) ) ); +r3_137: ex2_sh16_r3_b(137) <= not( (cp1_128 and ex2_sh_lvl2(9) ) or (cp3_spc and ex2_special(137) ) ); +r3_138: ex2_sh16_r3_b(138) <= not( (cp1_128 and ex2_sh_lvl2(10) ) or (cp3_spc and ex2_special(138) ) ); +r3_139: ex2_sh16_r3_b(139) <= not( (cp1_128 and ex2_sh_lvl2(11) ) or (cp3_spc and ex2_special(139) ) ); +r3_140: ex2_sh16_r3_b(140) <= not( (cp1_128 and ex2_sh_lvl2(12) ) or (cp3_spc and ex2_special(140) ) ); +r3_141: ex2_sh16_r3_b(141) <= not( (cp1_128 and ex2_sh_lvl2(13) ) or (cp3_spc and ex2_special(141) ) ); +r3_142: ex2_sh16_r3_b(142) <= not( (cp1_128 and ex2_sh_lvl2(14) ) or (cp3_spc and ex2_special(142) ) ); +r3_143: ex2_sh16_r3_b(143) <= not( (cp1_128 and ex2_sh_lvl2(15) ) or (cp3_spc and ex2_special(143) ) ); + +r3_144: ex2_sh16_r3_b(144) <= not( (cp1_144 and ex2_sh_lvl2(0) ) or (cp4_spc and ex2_special(144) ) ); +r3_145: ex2_sh16_r3_b(145) <= not( (cp1_144 and ex2_sh_lvl2(1) ) or (cp4_spc and ex2_special(145) ) ); +r3_146: ex2_sh16_r3_b(146) <= not( (cp1_144 and ex2_sh_lvl2(2) ) or (cp4_spc and ex2_special(146) ) ); +r3_147: ex2_sh16_r3_b(147) <= not( (cp1_144 and ex2_sh_lvl2(3) ) or (cp4_spc and ex2_special(147) ) ); +r3_148: ex2_sh16_r3_b(148) <= not( (cp1_144 and ex2_sh_lvl2(4) ) or (cp4_spc and ex2_special(148) ) ); +r3_149: ex2_sh16_r3_b(149) <= not( (cp1_144 and ex2_sh_lvl2(5) ) or (cp4_spc and ex2_special(149) ) ); +r3_150: ex2_sh16_r3_b(150) <= not( (cp1_144 and ex2_sh_lvl2(6) ) or (cp4_spc and ex2_special(150) ) ); +r3_151: ex2_sh16_r3_b(151) <= not( (cp1_144 and ex2_sh_lvl2(7) ) or (cp4_spc and ex2_special(151) ) ); +r3_152: ex2_sh16_r3_b(152) <= not( (cp1_144 and ex2_sh_lvl2(8) ) or (cp4_spc and ex2_special(152) ) ); +r3_153: ex2_sh16_r3_b(153) <= not( (cp1_144 and ex2_sh_lvl2(9) ) or (cp4_spc and ex2_special(153) ) ); +r3_154: ex2_sh16_r3_b(154) <= not( (cp1_144 and ex2_sh_lvl2(10) ) or (cp4_spc and ex2_special(154) ) ); +r3_155: ex2_sh16_r3_b(155) <= not( (cp1_144 and ex2_sh_lvl2(11) ) or (cp4_spc and ex2_special(155) ) ); +r3_156: ex2_sh16_r3_b(156) <= not( (cp1_144 and ex2_sh_lvl2(12) ) or (cp4_spc and ex2_special(156) ) ); +r3_157: ex2_sh16_r3_b(157) <= not( (cp1_144 and ex2_sh_lvl2(13) ) or (cp4_spc and ex2_special(157) ) ); +r3_158: ex2_sh16_r3_b(158) <= not( (cp1_144 and ex2_sh_lvl2(14) ) or (cp4_spc and ex2_special(158) ) ); +r3_159: ex2_sh16_r3_b(159) <= not( (cp1_144 and ex2_sh_lvl2(15) ) or (cp4_spc and ex2_special(159) ) ); + +r3_160: ex2_sh16_r3_b(160) <= not( (cp1_160 and ex2_sh_lvl2(0) ) or (cp5_spc and ex2_special(160) ) ); +r3_161: ex2_sh16_r3_b(161) <= not( (cp1_160 and ex2_sh_lvl2(1) ) or (cp5_spc and ex2_special(161) ) ); +r3_162: ex2_sh16_r3_b(162) <= not( (cp1_160 and ex2_sh_lvl2(2) ) or (cp5_spc and ex2_special(162) ) ); + + +o_000: ex2_sh_lvl3(0) <= not( ex2_sh16_r1_b(0) and ex2_sh16_r2_b(0) and ex2_sh16_r3_b(0) ); +o_001: ex2_sh_lvl3(1) <= not( ex2_sh16_r1_b(1) and ex2_sh16_r2_b(1) and ex2_sh16_r3_b(1) ); +o_002: ex2_sh_lvl3(2) <= not( ex2_sh16_r1_b(2) and ex2_sh16_r2_b(2) and ex2_sh16_r3_b(2) ); +o_003: ex2_sh_lvl3(3) <= not( ex2_sh16_r1_b(3) and ex2_sh16_r2_b(3) and ex2_sh16_r3_b(3) ); +o_004: ex2_sh_lvl3(4) <= not( ex2_sh16_r1_b(4) and ex2_sh16_r2_b(4) and ex2_sh16_r3_b(4) ); +o_005: ex2_sh_lvl3(5) <= not( ex2_sh16_r1_b(5) and ex2_sh16_r2_b(5) and ex2_sh16_r3_b(5) ); +o_006: ex2_sh_lvl3(6) <= not( ex2_sh16_r1_b(6) and ex2_sh16_r2_b(6) and ex2_sh16_r3_b(6) ); +o_007: ex2_sh_lvl3(7) <= not( ex2_sh16_r1_b(7) and ex2_sh16_r2_b(7) and ex2_sh16_r3_b(7) ); +o_008: ex2_sh_lvl3(8) <= not( ex2_sh16_r1_b(8) and ex2_sh16_r2_b(8) and ex2_sh16_r3_b(8) ); +o_009: ex2_sh_lvl3(9) <= not( ex2_sh16_r1_b(9) and ex2_sh16_r2_b(9) and ex2_sh16_r3_b(9) ); +o_010: ex2_sh_lvl3(10) <= not( ex2_sh16_r1_b(10) and ex2_sh16_r2_b(10) and ex2_sh16_r3_b(10) ); +o_011: ex2_sh_lvl3(11) <= not( ex2_sh16_r1_b(11) and ex2_sh16_r2_b(11) and ex2_sh16_r3_b(11) ); +o_012: ex2_sh_lvl3(12) <= not( ex2_sh16_r1_b(12) and ex2_sh16_r2_b(12) and ex2_sh16_r3_b(12) ); +o_013: ex2_sh_lvl3(13) <= not( ex2_sh16_r1_b(13) and ex2_sh16_r2_b(13) and ex2_sh16_r3_b(13) ); +o_014: ex2_sh_lvl3(14) <= not( ex2_sh16_r1_b(14) and ex2_sh16_r2_b(14) and ex2_sh16_r3_b(14) ); +o_015: ex2_sh_lvl3(15) <= not( ex2_sh16_r1_b(15) and ex2_sh16_r2_b(15) and ex2_sh16_r3_b(15) ); +o_016: ex2_sh_lvl3(16) <= not( ex2_sh16_r1_b(16) and ex2_sh16_r2_b(16) and ex2_sh16_r3_b(16) ); +o_017: ex2_sh_lvl3(17) <= not( ex2_sh16_r1_b(17) and ex2_sh16_r2_b(17) and ex2_sh16_r3_b(17) ); +o_018: ex2_sh_lvl3(18) <= not( ex2_sh16_r1_b(18) and ex2_sh16_r2_b(18) and ex2_sh16_r3_b(18) ); +o_019: ex2_sh_lvl3(19) <= not( ex2_sh16_r1_b(19) and ex2_sh16_r2_b(19) and ex2_sh16_r3_b(19) ); +o_020: ex2_sh_lvl3(20) <= not( ex2_sh16_r1_b(20) and ex2_sh16_r2_b(20) and ex2_sh16_r3_b(20) ); +o_021: ex2_sh_lvl3(21) <= not( ex2_sh16_r1_b(21) and ex2_sh16_r2_b(21) and ex2_sh16_r3_b(21) ); +o_022: ex2_sh_lvl3(22) <= not( ex2_sh16_r1_b(22) and ex2_sh16_r2_b(22) and ex2_sh16_r3_b(22) ); +o_023: ex2_sh_lvl3(23) <= not( ex2_sh16_r1_b(23) and ex2_sh16_r2_b(23) and ex2_sh16_r3_b(23) ); +o_024: ex2_sh_lvl3(24) <= not( ex2_sh16_r1_b(24) and ex2_sh16_r2_b(24) and ex2_sh16_r3_b(24) ); +o_025: ex2_sh_lvl3(25) <= not( ex2_sh16_r1_b(25) and ex2_sh16_r2_b(25) and ex2_sh16_r3_b(25) ); +o_026: ex2_sh_lvl3(26) <= not( ex2_sh16_r1_b(26) and ex2_sh16_r2_b(26) and ex2_sh16_r3_b(26) ); +o_027: ex2_sh_lvl3(27) <= not( ex2_sh16_r1_b(27) and ex2_sh16_r2_b(27) and ex2_sh16_r3_b(27) ); +o_028: ex2_sh_lvl3(28) <= not( ex2_sh16_r1_b(28) and ex2_sh16_r2_b(28) and ex2_sh16_r3_b(28) ); +o_029: ex2_sh_lvl3(29) <= not( ex2_sh16_r1_b(29) and ex2_sh16_r2_b(29) and ex2_sh16_r3_b(29) ); +o_030: ex2_sh_lvl3(30) <= not( ex2_sh16_r1_b(30) and ex2_sh16_r2_b(30) and ex2_sh16_r3_b(30) ); +o_031: ex2_sh_lvl3(31) <= not( ex2_sh16_r1_b(31) and ex2_sh16_r2_b(31) and ex2_sh16_r3_b(31) ); +o_032: ex2_sh_lvl3(32) <= not( ex2_sh16_r1_b(32) and ex2_sh16_r2_b(32) and ex2_sh16_r3_b(32) ); +o_033: ex2_sh_lvl3(33) <= not( ex2_sh16_r1_b(33) and ex2_sh16_r2_b(33) and ex2_sh16_r3_b(33) ); +o_034: ex2_sh_lvl3(34) <= not( ex2_sh16_r1_b(34) and ex2_sh16_r2_b(34) and ex2_sh16_r3_b(34) ); +o_035: ex2_sh_lvl3(35) <= not( ex2_sh16_r1_b(35) and ex2_sh16_r2_b(35) and ex2_sh16_r3_b(35) ); +o_036: ex2_sh_lvl3(36) <= not( ex2_sh16_r1_b(36) and ex2_sh16_r2_b(36) and ex2_sh16_r3_b(36) ); +o_037: ex2_sh_lvl3(37) <= not( ex2_sh16_r1_b(37) and ex2_sh16_r2_b(37) and ex2_sh16_r3_b(37) ); +o_038: ex2_sh_lvl3(38) <= not( ex2_sh16_r1_b(38) and ex2_sh16_r2_b(38) and ex2_sh16_r3_b(38) ); +o_039: ex2_sh_lvl3(39) <= not( ex2_sh16_r1_b(39) and ex2_sh16_r2_b(39) and ex2_sh16_r3_b(39) ); +o_040: ex2_sh_lvl3(40) <= not( ex2_sh16_r1_b(40) and ex2_sh16_r2_b(40) and ex2_sh16_r3_b(40) ); +o_041: ex2_sh_lvl3(41) <= not( ex2_sh16_r1_b(41) and ex2_sh16_r2_b(41) and ex2_sh16_r3_b(41) ); +o_042: ex2_sh_lvl3(42) <= not( ex2_sh16_r1_b(42) and ex2_sh16_r2_b(42) and ex2_sh16_r3_b(42) ); +o_043: ex2_sh_lvl3(43) <= not( ex2_sh16_r1_b(43) and ex2_sh16_r2_b(43) and ex2_sh16_r3_b(43) ); +o_044: ex2_sh_lvl3(44) <= not( ex2_sh16_r1_b(44) and ex2_sh16_r2_b(44) and ex2_sh16_r3_b(44) ); +o_045: ex2_sh_lvl3(45) <= not( ex2_sh16_r1_b(45) and ex2_sh16_r2_b(45) and ex2_sh16_r3_b(45) ); +o_046: ex2_sh_lvl3(46) <= not( ex2_sh16_r1_b(46) and ex2_sh16_r2_b(46) and ex2_sh16_r3_b(46) ); +o_047: ex2_sh_lvl3(47) <= not( ex2_sh16_r1_b(47) and ex2_sh16_r2_b(47) and ex2_sh16_r3_b(47) ); +o_048: ex2_sh_lvl3(48) <= not( ex2_sh16_r1_b(48) and ex2_sh16_r2_b(48) and ex2_sh16_r3_b(48) ); +o_049: ex2_sh_lvl3(49) <= not( ex2_sh16_r1_b(49) and ex2_sh16_r2_b(49) and ex2_sh16_r3_b(49) ); +o_050: ex2_sh_lvl3(50) <= not( ex2_sh16_r1_b(50) and ex2_sh16_r2_b(50) and ex2_sh16_r3_b(50) ); +o_051: ex2_sh_lvl3(51) <= not( ex2_sh16_r1_b(51) and ex2_sh16_r2_b(51) and ex2_sh16_r3_b(51) ); +o_052: ex2_sh_lvl3(52) <= not( ex2_sh16_r1_b(52) and ex2_sh16_r2_b(52) and ex2_sh16_r3_b(52) ); +o_053: ex2_sh_lvl3(53) <= not( ex2_sh16_r1_b(53) and ex2_sh16_r2_b(53) and ex2_sh16_r3_b(53) ); +o_054: ex2_sh_lvl3(54) <= not( ex2_sh16_r1_b(54) and ex2_sh16_r2_b(54) and ex2_sh16_r3_b(54) ); +o_055: ex2_sh_lvl3(55) <= not( ex2_sh16_r1_b(55) and ex2_sh16_r2_b(55) and ex2_sh16_r3_b(55) ); +o_056: ex2_sh_lvl3(56) <= not( ex2_sh16_r1_b(56) and ex2_sh16_r2_b(56) and ex2_sh16_r3_b(56) ); +o_057: ex2_sh_lvl3(57) <= not( ex2_sh16_r1_b(57) and ex2_sh16_r2_b(57) and ex2_sh16_r3_b(57) ); +o_058: ex2_sh_lvl3(58) <= not( ex2_sh16_r1_b(58) and ex2_sh16_r2_b(58) and ex2_sh16_r3_b(58) ); +o_059: ex2_sh_lvl3(59) <= not( ex2_sh16_r1_b(59) and ex2_sh16_r2_b(59) and ex2_sh16_r3_b(59) ); +o_060: ex2_sh_lvl3(60) <= not( ex2_sh16_r1_b(60) and ex2_sh16_r2_b(60) and ex2_sh16_r3_b(60) ); +o_061: ex2_sh_lvl3(61) <= not( ex2_sh16_r1_b(61) and ex2_sh16_r2_b(61) and ex2_sh16_r3_b(61) ); +o_062: ex2_sh_lvl3(62) <= not( ex2_sh16_r1_b(62) and ex2_sh16_r2_b(62) and ex2_sh16_r3_b(62) ); +o_063: ex2_sh_lvl3(63) <= not( ex2_sh16_r1_b(63) and ex2_sh16_r2_b(63) and ex2_sh16_r3_b(63) ); +o_064: ex2_sh_lvl3(64) <= not( ex2_sh16_r1_b(64) and ex2_sh16_r2_b(64) and ex2_sh16_r3_b(64) ); +o_065: ex2_sh_lvl3(65) <= not( ex2_sh16_r1_b(65) and ex2_sh16_r2_b(65) and ex2_sh16_r3_b(65) ); +o_066: ex2_sh_lvl3(66) <= not( ex2_sh16_r1_b(66) and ex2_sh16_r2_b(66) and ex2_sh16_r3_b(66) ); +o_067: ex2_sh_lvl3(67) <= not( ex2_sh16_r1_b(67) and ex2_sh16_r2_b(67) and ex2_sh16_r3_b(67) ); +o_068: ex2_sh_lvl3(68) <= not( ex2_sh16_r1_b(68) and ex2_sh16_r2_b(68) and ex2_sh16_r3_b(68) ); +o_069: ex2_sh_lvl3(69) <= not( ex2_sh16_r1_b(69) and ex2_sh16_r2_b(69) and ex2_sh16_r3_b(69) ); +o_070: ex2_sh_lvl3(70) <= not( ex2_sh16_r1_b(70) and ex2_sh16_r2_b(70) and ex2_sh16_r3_b(70) ); +o_071: ex2_sh_lvl3(71) <= not( ex2_sh16_r1_b(71) and ex2_sh16_r2_b(71) and ex2_sh16_r3_b(71) ); +o_072: ex2_sh_lvl3(72) <= not( ex2_sh16_r1_b(72) and ex2_sh16_r2_b(72) and ex2_sh16_r3_b(72) ); +o_073: ex2_sh_lvl3(73) <= not( ex2_sh16_r1_b(73) and ex2_sh16_r2_b(73) and ex2_sh16_r3_b(73) ); +o_074: ex2_sh_lvl3(74) <= not( ex2_sh16_r1_b(74) and ex2_sh16_r2_b(74) and ex2_sh16_r3_b(74) ); +o_075: ex2_sh_lvl3(75) <= not( ex2_sh16_r1_b(75) and ex2_sh16_r2_b(75) and ex2_sh16_r3_b(75) ); +o_076: ex2_sh_lvl3(76) <= not( ex2_sh16_r1_b(76) and ex2_sh16_r2_b(76) and ex2_sh16_r3_b(76) ); +o_077: ex2_sh_lvl3(77) <= not( ex2_sh16_r1_b(77) and ex2_sh16_r2_b(77) and ex2_sh16_r3_b(77) ); +o_078: ex2_sh_lvl3(78) <= not( ex2_sh16_r1_b(78) and ex2_sh16_r2_b(78) and ex2_sh16_r3_b(78) ); +o_079: ex2_sh_lvl3(79) <= not( ex2_sh16_r1_b(79) and ex2_sh16_r2_b(79) and ex2_sh16_r3_b(79) ); +o_080: ex2_sh_lvl3(80) <= not( ex2_sh16_r1_b(80) and ex2_sh16_r2_b(80) and ex2_sh16_r3_b(80) ); +o_081: ex2_sh_lvl3(81) <= not( ex2_sh16_r1_b(81) and ex2_sh16_r2_b(81) and ex2_sh16_r3_b(81) ); +o_082: ex2_sh_lvl3(82) <= not( ex2_sh16_r1_b(82) and ex2_sh16_r2_b(82) and ex2_sh16_r3_b(82) ); +o_083: ex2_sh_lvl3(83) <= not( ex2_sh16_r1_b(83) and ex2_sh16_r2_b(83) and ex2_sh16_r3_b(83) ); +o_084: ex2_sh_lvl3(84) <= not( ex2_sh16_r1_b(84) and ex2_sh16_r2_b(84) and ex2_sh16_r3_b(84) ); +o_085: ex2_sh_lvl3(85) <= not( ex2_sh16_r1_b(85) and ex2_sh16_r2_b(85) and ex2_sh16_r3_b(85) ); +o_086: ex2_sh_lvl3(86) <= not( ex2_sh16_r1_b(86) and ex2_sh16_r2_b(86) and ex2_sh16_r3_b(86) ); +o_087: ex2_sh_lvl3(87) <= not( ex2_sh16_r1_b(87) and ex2_sh16_r2_b(87) and ex2_sh16_r3_b(87) ); +o_088: ex2_sh_lvl3(88) <= not( ex2_sh16_r1_b(88) and ex2_sh16_r2_b(88) and ex2_sh16_r3_b(88) ); +o_089: ex2_sh_lvl3(89) <= not( ex2_sh16_r1_b(89) and ex2_sh16_r2_b(89) and ex2_sh16_r3_b(89) ); +o_090: ex2_sh_lvl3(90) <= not( ex2_sh16_r1_b(90) and ex2_sh16_r2_b(90) and ex2_sh16_r3_b(90) ); +o_091: ex2_sh_lvl3(91) <= not( ex2_sh16_r1_b(91) and ex2_sh16_r2_b(91) and ex2_sh16_r3_b(91) ); +o_092: ex2_sh_lvl3(92) <= not( ex2_sh16_r1_b(92) and ex2_sh16_r2_b(92) and ex2_sh16_r3_b(92) ); +o_093: ex2_sh_lvl3(93) <= not( ex2_sh16_r1_b(93) and ex2_sh16_r2_b(93) and ex2_sh16_r3_b(93) ); +o_094: ex2_sh_lvl3(94) <= not( ex2_sh16_r1_b(94) and ex2_sh16_r2_b(94) and ex2_sh16_r3_b(94) ); +o_095: ex2_sh_lvl3(95) <= not( ex2_sh16_r1_b(95) and ex2_sh16_r2_b(95) and ex2_sh16_r3_b(95) ); +o_096: ex2_sh_lvl3(96) <= not( ex2_sh16_r1_b(96) and ex2_sh16_r2_b(96) and ex2_sh16_r3_b(96) ); +o_097: ex2_sh_lvl3(97) <= not( ex2_sh16_r1_b(97) and ex2_sh16_r2_b(97) and ex2_sh16_r3_b(97) ); +o_098: ex2_sh_lvl3(98) <= not( ex2_sh16_r1_b(98) and ex2_sh16_r2_b(98) and ex2_sh16_r3_b(98) ); +o_099: ex2_sh_lvl3(99) <= not( ex2_sh16_r1_b(99) and ex2_sh16_r2_b(99) and ex2_sh16_r3_b(99) ); +o_100: ex2_sh_lvl3(100) <= not( ex2_sh16_r1_b(100) and ex2_sh16_r2_b(100) and ex2_sh16_r3_b(100) ); +o_101: ex2_sh_lvl3(101) <= not( ex2_sh16_r1_b(101) and ex2_sh16_r2_b(101) and ex2_sh16_r3_b(101) ); +o_102: ex2_sh_lvl3(102) <= not( ex2_sh16_r1_b(102) and ex2_sh16_r2_b(102) and ex2_sh16_r3_b(102) ); +o_103: ex2_sh_lvl3(103) <= not( ex2_sh16_r1_b(103) and ex2_sh16_r2_b(103) and ex2_sh16_r3_b(103) ); +o_104: ex2_sh_lvl3(104) <= not( ex2_sh16_r1_b(104) and ex2_sh16_r2_b(104) and ex2_sh16_r3_b(104) ); +o_105: ex2_sh_lvl3(105) <= not( ex2_sh16_r1_b(105) and ex2_sh16_r2_b(105) and ex2_sh16_r3_b(105) ); +o_106: ex2_sh_lvl3(106) <= not( ex2_sh16_r1_b(106) and ex2_sh16_r2_b(106) and ex2_sh16_r3_b(106) ); +o_107: ex2_sh_lvl3(107) <= not( ex2_sh16_r1_b(107) and ex2_sh16_r2_b(107) and ex2_sh16_r3_b(107) ); +o_108: ex2_sh_lvl3(108) <= not( ex2_sh16_r1_b(108) and ex2_sh16_r2_b(108) and ex2_sh16_r3_b(108) ); +o_109: ex2_sh_lvl3(109) <= not( ex2_sh16_r1_b(109) and ex2_sh16_r2_b(109) and ex2_sh16_r3_b(109) ); +o_110: ex2_sh_lvl3(110) <= not( ex2_sh16_r1_b(110) and ex2_sh16_r2_b(110) and ex2_sh16_r3_b(110) ); +o_111: ex2_sh_lvl3(111) <= not( ex2_sh16_r1_b(111) and ex2_sh16_r2_b(111) and ex2_sh16_r3_b(111) ); +o_112: ex2_sh_lvl3(112) <= not( ex2_sh16_r1_b(112) and ex2_sh16_r2_b(112) and ex2_sh16_r3_b(112) ); +o_113: ex2_sh_lvl3(113) <= not( ex2_sh16_r1_b(113) and ex2_sh16_r2_b(113) and ex2_sh16_r3_b(113) ); +o_114: ex2_sh_lvl3(114) <= not( ex2_sh16_r1_b(114) and ex2_sh16_r2_b(114) and ex2_sh16_r3_b(114) ); +o_115: ex2_sh_lvl3(115) <= not( ex2_sh16_r1_b(115) and ex2_sh16_r2_b(115) and ex2_sh16_r3_b(115) ); +o_116: ex2_sh_lvl3(116) <= not( ex2_sh16_r1_b(116) and ex2_sh16_r2_b(116) and ex2_sh16_r3_b(116) ); +o_117: ex2_sh_lvl3(117) <= not( ex2_sh16_r1_b(117) and ex2_sh16_r2_b(117) and ex2_sh16_r3_b(117) ); +o_118: ex2_sh_lvl3(118) <= not( ex2_sh16_r1_b(118) and ex2_sh16_r2_b(118) and ex2_sh16_r3_b(118) ); +o_119: ex2_sh_lvl3(119) <= not( ex2_sh16_r1_b(119) and ex2_sh16_r2_b(119) and ex2_sh16_r3_b(119) ); +o_120: ex2_sh_lvl3(120) <= not( ex2_sh16_r1_b(120) and ex2_sh16_r2_b(120) and ex2_sh16_r3_b(120) ); +o_121: ex2_sh_lvl3(121) <= not( ex2_sh16_r1_b(121) and ex2_sh16_r2_b(121) and ex2_sh16_r3_b(121) ); +o_122: ex2_sh_lvl3(122) <= not( ex2_sh16_r1_b(122) and ex2_sh16_r2_b(122) and ex2_sh16_r3_b(122) ); +o_123: ex2_sh_lvl3(123) <= not( ex2_sh16_r1_b(123) and ex2_sh16_r2_b(123) and ex2_sh16_r3_b(123) ); +o_124: ex2_sh_lvl3(124) <= not( ex2_sh16_r1_b(124) and ex2_sh16_r2_b(124) and ex2_sh16_r3_b(124) ); +o_125: ex2_sh_lvl3(125) <= not( ex2_sh16_r1_b(125) and ex2_sh16_r2_b(125) and ex2_sh16_r3_b(125) ); +o_126: ex2_sh_lvl3(126) <= not( ex2_sh16_r1_b(126) and ex2_sh16_r2_b(126) and ex2_sh16_r3_b(126) ); +o_127: ex2_sh_lvl3(127) <= not( ex2_sh16_r1_b(127) and ex2_sh16_r2_b(127) and ex2_sh16_r3_b(127) ); +o_128: ex2_sh_lvl3(128) <= not( ex2_sh16_r1_b(128) and ex2_sh16_r2_b(128) and ex2_sh16_r3_b(128) ); +o_129: ex2_sh_lvl3(129) <= not( ex2_sh16_r1_b(129) and ex2_sh16_r2_b(129) and ex2_sh16_r3_b(129) ); +o_130: ex2_sh_lvl3(130) <= not( ex2_sh16_r1_b(130) and ex2_sh16_r2_b(130) and ex2_sh16_r3_b(130) ); +o_131: ex2_sh_lvl3(131) <= not( ex2_sh16_r1_b(131) and ex2_sh16_r2_b(131) and ex2_sh16_r3_b(131) ); +o_132: ex2_sh_lvl3(132) <= not( ex2_sh16_r1_b(132) and ex2_sh16_r2_b(132) and ex2_sh16_r3_b(132) ); +o_133: ex2_sh_lvl3(133) <= not( ex2_sh16_r1_b(133) and ex2_sh16_r2_b(133) and ex2_sh16_r3_b(133) ); +o_134: ex2_sh_lvl3(134) <= not( ex2_sh16_r1_b(134) and ex2_sh16_r2_b(134) and ex2_sh16_r3_b(134) ); +o_135: ex2_sh_lvl3(135) <= not( ex2_sh16_r1_b(135) and ex2_sh16_r2_b(135) and ex2_sh16_r3_b(135) ); +o_136: ex2_sh_lvl3(136) <= not( ex2_sh16_r1_b(136) and ex2_sh16_r2_b(136) and ex2_sh16_r3_b(136) ); +o_137: ex2_sh_lvl3(137) <= not( ex2_sh16_r1_b(137) and ex2_sh16_r2_b(137) and ex2_sh16_r3_b(137) ); +o_138: ex2_sh_lvl3(138) <= not( ex2_sh16_r1_b(138) and ex2_sh16_r2_b(138) and ex2_sh16_r3_b(138) ); +o_139: ex2_sh_lvl3(139) <= not( ex2_sh16_r1_b(139) and ex2_sh16_r2_b(139) and ex2_sh16_r3_b(139) ); +o_140: ex2_sh_lvl3(140) <= not( ex2_sh16_r1_b(140) and ex2_sh16_r2_b(140) and ex2_sh16_r3_b(140) ); +o_141: ex2_sh_lvl3(141) <= not( ex2_sh16_r1_b(141) and ex2_sh16_r2_b(141) and ex2_sh16_r3_b(141) ); +o_142: ex2_sh_lvl3(142) <= not( ex2_sh16_r1_b(142) and ex2_sh16_r2_b(142) and ex2_sh16_r3_b(142) ); +o_143: ex2_sh_lvl3(143) <= not( ex2_sh16_r1_b(143) and ex2_sh16_r2_b(143) and ex2_sh16_r3_b(143) ); +o_144: ex2_sh_lvl3(144) <= not( ex2_sh16_r1_b(144) and ex2_sh16_r2_b(144) and ex2_sh16_r3_b(144) ); +o_145: ex2_sh_lvl3(145) <= not( ex2_sh16_r1_b(145) and ex2_sh16_r2_b(145) and ex2_sh16_r3_b(145) ); +o_146: ex2_sh_lvl3(146) <= not( ex2_sh16_r1_b(146) and ex2_sh16_r2_b(146) and ex2_sh16_r3_b(146) ); +o_147: ex2_sh_lvl3(147) <= not( ex2_sh16_r1_b(147) and ex2_sh16_r2_b(147) and ex2_sh16_r3_b(147) ); +o_148: ex2_sh_lvl3(148) <= not( ex2_sh16_r1_b(148) and ex2_sh16_r2_b(148) and ex2_sh16_r3_b(148) ); +o_149: ex2_sh_lvl3(149) <= not( ex2_sh16_r1_b(149) and ex2_sh16_r2_b(149) and ex2_sh16_r3_b(149) ); +o_150: ex2_sh_lvl3(150) <= not( ex2_sh16_r1_b(150) and ex2_sh16_r2_b(150) and ex2_sh16_r3_b(150) ); +o_151: ex2_sh_lvl3(151) <= not( ex2_sh16_r1_b(151) and ex2_sh16_r2_b(151) and ex2_sh16_r3_b(151) ); +o_152: ex2_sh_lvl3(152) <= not( ex2_sh16_r1_b(152) and ex2_sh16_r2_b(152) and ex2_sh16_r3_b(152) ); +o_153: ex2_sh_lvl3(153) <= not( ex2_sh16_r1_b(153) and ex2_sh16_r2_b(153) and ex2_sh16_r3_b(153) ); +o_154: ex2_sh_lvl3(154) <= not( ex2_sh16_r1_b(154) and ex2_sh16_r2_b(154) and ex2_sh16_r3_b(154) ); +o_155: ex2_sh_lvl3(155) <= not( ex2_sh16_r1_b(155) and ex2_sh16_r2_b(155) and ex2_sh16_r3_b(155) ); +o_156: ex2_sh_lvl3(156) <= not( ex2_sh16_r1_b(156) and ex2_sh16_r2_b(156) and ex2_sh16_r3_b(156) ); +o_157: ex2_sh_lvl3(157) <= not( ex2_sh16_r1_b(157) and ex2_sh16_r2_b(157) and ex2_sh16_r3_b(157) ); +o_158: ex2_sh_lvl3(158) <= not( ex2_sh16_r1_b(158) and ex2_sh16_r2_b(158) and ex2_sh16_r3_b(158) ); +o_159: ex2_sh_lvl3(159) <= not( ex2_sh16_r1_b(159) and ex2_sh16_r2_b(159) and ex2_sh16_r3_b(159) ); +o_160: ex2_sh_lvl3(160) <= not( ex2_sh16_r1_b(160) and ex2_sh16_r2_b(160) and ex2_sh16_r3_b(160) ); +o_161: ex2_sh_lvl3(161) <= not( ex2_sh16_r1_b(161) and ex2_sh16_r2_b(161) and ex2_sh16_r3_b(161) ); +o_162: ex2_sh_lvl3(162) <= not( ex2_sh16_r1_b(162) and ex2_sh16_r2_b(162) and ex2_sh16_r3_b(162) ); + + + + + +rr3_162: ex2_sh16_r3_162_b <= not( (ex2_lvl3_shdcd160 and ex2_sh_lvl2(2) ) or (ex2_sel_special and ex2_special(162) ) ); +rr3_163: ex2_sh16_r3_163_b <= not( ex2_lvl3_shdcd160 and ex2_sh_lvl2(3) ); + +rr2_162: ex2_sh16_r2_162_b <= not( (ex2_lvl3_shdcd128 and ex2_sh_lvl2(34) ) or (ex2_lvl3_shdcd144 and ex2_sh_lvl2(18) ) ); +rr2_163: ex2_sh16_r2_163_b <= not( (ex2_lvl3_shdcd128 and ex2_sh_lvl2(35) ) or (ex2_lvl3_shdcd144 and ex2_sh_lvl2(19) ) ); + +rr1_162: ex2_sh16_r1_162_b <= not( (ex2_lvl3_shdcd096 and ex2_sh_lvl2(66) ) or (ex2_lvl3_shdcd112 and ex2_sh_lvl2(50) ) ); +rr1_163: ex2_sh16_r1_163_b <= not( (ex2_lvl3_shdcd096 and ex2_sh_lvl2(67) ) or (ex2_lvl3_shdcd112 and ex2_sh_lvl2(51) ) ); + +ro_162: ex2_sh16_162 <= not( ex2_sh16_r1_162_b and ex2_sh16_r2_162_b and ex2_sh16_r3_162_b ); +ro_163: ex2_sh16_163 <= not( ex2_sh16_r1_163_b and ex2_sh16_r2_163_b and ex2_sh16_r3_163_b ); + + + +end; + + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_alg_sh4.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_alg_sh4.vhdl new file mode 100644 index 0000000..206fc1d --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_alg_sh4.vhdl @@ -0,0 +1,708 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + + +entity fuq_alg_sh4 is +generic( expand_type : integer := 2 ); +port( + ex1_lvl1_shdcd000_b :in std_ulogic; + ex1_lvl1_shdcd001_b :in std_ulogic; + ex1_lvl1_shdcd002_b :in std_ulogic; + ex1_lvl1_shdcd003_b :in std_ulogic; + ex1_lvl2_shdcd000 :in std_ulogic; + ex1_lvl2_shdcd004 :in std_ulogic; + ex1_lvl2_shdcd008 :in std_ulogic; + ex1_lvl2_shdcd012 :in std_ulogic; + ex1_sel_special :in std_ulogic; + + ex1_b_sign :in std_ulogic; + ex1_b_expo :in std_ulogic_vector(3 to 13) ; + ex1_b_frac :in std_ulogic_vector(0 to 52) ; + + ex1_sh_lvl2 :out std_ulogic_vector(0 to 67) +); + + + +end fuq_alg_sh4; + +architecture fuq_alg_sh4 of fuq_alg_sh4 is + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal ex1_special_fcfid :std_ulogic_vector(0 to 63); + signal ex1_sh_lv1 :std_ulogic_vector(0 to 55); + signal ex1_sh_lv1x_b :std_ulogic_vector(0 to 53); + signal ex1_sh_lv1y_b :std_ulogic_vector(2 to 55); + signal ex1_sh_lv2x_b :std_ulogic_vector(0 to 59); + signal ex1_sh_lv2y_b :std_ulogic_vector(8 to 67); + signal ex1_sh_lv2z_b :std_ulogic_vector(0 to 63); + + signal sh1v2dcd0_cp1 :std_ulogic; + signal sh1v3dcd0_cp1_b :std_ulogic; + signal sh1v3dcd0_cp2_b :std_ulogic; + signal sh1v4dcd0_cp1 :std_ulogic; + signal sh1v4dcd0_cp2 :std_ulogic; + signal sh1v4dcd0_cp3 :std_ulogic; + signal sh1v4dcd0_cp4 :std_ulogic; + signal sh1v2dcd1_cp1 :std_ulogic; + signal sh1v3dcd1_cp1_b :std_ulogic; + signal sh1v3dcd1_cp2_b :std_ulogic; + signal sh1v4dcd1_cp1 :std_ulogic; + signal sh1v4dcd1_cp2 :std_ulogic; + signal sh1v4dcd1_cp3 :std_ulogic; + signal sh1v4dcd1_cp4 :std_ulogic; + signal sh1v2dcd2_cp1 :std_ulogic; + signal sh1v3dcd2_cp1_b :std_ulogic; + signal sh1v3dcd2_cp2_b :std_ulogic; + signal sh1v4dcd2_cp1 :std_ulogic; + signal sh1v4dcd2_cp2 :std_ulogic; + signal sh1v4dcd2_cp3 :std_ulogic; + signal sh1v4dcd2_cp4 :std_ulogic; + signal sh1v2dcd3_cp1 :std_ulogic; + signal sh1v3dcd3_cp1_b :std_ulogic; + signal sh1v3dcd3_cp2_b :std_ulogic; + signal sh1v4dcd3_cp1 :std_ulogic; + signal sh1v4dcd3_cp2 :std_ulogic; + signal sh1v4dcd3_cp3 :std_ulogic; + signal sh1v4dcd3_cp4 :std_ulogic; + signal sh2v1dcd00_cp1_b :std_ulogic; + signal sh2v2dcd00_cp1 :std_ulogic; + signal sh2v3dcd00_cp1_b :std_ulogic; + signal sh2v3dcd00_cp2_b :std_ulogic; + signal sh2v4dcd00_cp1 :std_ulogic; + signal sh2v4dcd00_cp2 :std_ulogic; + signal sh2v4dcd00_cp3 :std_ulogic; + signal sh2v4dcd00_cp4 :std_ulogic; + signal sh2v1dcd04_cp1_b :std_ulogic; + signal sh2v2dcd04_cp1 :std_ulogic; + signal sh2v3dcd04_cp1_b :std_ulogic; + signal sh2v3dcd04_cp2_b :std_ulogic; + signal sh2v4dcd04_cp1 :std_ulogic; + signal sh2v4dcd04_cp2 :std_ulogic; + signal sh2v4dcd04_cp3 :std_ulogic; + signal sh2v4dcd04_cp4 :std_ulogic; + signal sh2v1dcd08_cp1_b :std_ulogic; + signal sh2v2dcd08_cp1 :std_ulogic; + signal sh2v3dcd08_cp1_b :std_ulogic; + signal sh2v3dcd08_cp2_b :std_ulogic; + signal sh2v4dcd08_cp1 :std_ulogic; + signal sh2v4dcd08_cp2 :std_ulogic; + signal sh2v4dcd08_cp3 :std_ulogic; + signal sh2v4dcd08_cp4 :std_ulogic; + signal sh2v1dcd12_cp1_b :std_ulogic; + signal sh2v2dcd12_cp1 :std_ulogic; + signal sh2v3dcd12_cp1_b :std_ulogic; + signal sh2v3dcd12_cp2_b :std_ulogic; + signal sh2v4dcd12_cp1 :std_ulogic; + signal sh2v4dcd12_cp2 :std_ulogic; + signal sh2v4dcd12_cp3 :std_ulogic; + signal sh2v4dcd12_cp4 :std_ulogic; + signal sh2v1dcdpp_cp1_b :std_ulogic; + signal sh2v2dcdpp_cp1 :std_ulogic; + signal sh2v3dcdpp_cp1_b :std_ulogic; + signal sh2v3dcdpp_cp2_b :std_ulogic; + signal sh2v4dcdpp_cp1 :std_ulogic; + signal sh2v4dcdpp_cp2 :std_ulogic; + signal sh2v4dcdpp_cp3 :std_ulogic; + signal sh2v4dcdpp_cp4 :std_ulogic; + + + + + + + + + + + + + + + + + + + + + + +begin + + + ex1_special_fcfid(0) <= ex1_b_sign ; + ex1_special_fcfid(1) <= ex1_b_expo( 3) ; + ex1_special_fcfid(2) <= ex1_b_expo( 4) and ex1_b_frac(0) ; + ex1_special_fcfid(3) <= ex1_b_expo( 5) and ex1_b_frac(0) ; + ex1_special_fcfid(4) <= ex1_b_expo( 6) and ex1_b_frac(0) ; + ex1_special_fcfid(5) <= ex1_b_expo( 7) ; + ex1_special_fcfid(6) <= ex1_b_expo( 8) ; + ex1_special_fcfid(7) <= ex1_b_expo( 9) ; + ex1_special_fcfid(8) <= ex1_b_expo(10) ; + ex1_special_fcfid(9) <= ex1_b_expo(11) ; + ex1_special_fcfid(10) <= ex1_b_expo(12) ; + ex1_special_fcfid(11) <= ex1_b_expo(13) and ex1_b_frac(0) ; + ex1_special_fcfid(12 to 63) <= ex1_b_frac(1 to 52); + + + + + s1v2d0c1: sh1v2dcd0_cp1 <= not ex1_lvl1_shdcd000_b; + s1v3d0c1: sh1v3dcd0_cp1_b <= not sh1v2dcd0_cp1 ; + s1v3d0c2: sh1v3dcd0_cp2_b <= not sh1v2dcd0_cp1 ; + s1v4d0c1: sh1v4dcd0_cp1 <= not sh1v3dcd0_cp1_b; + s1v4d0c2: sh1v4dcd0_cp2 <= not sh1v3dcd0_cp1_b; + s1v4d0c3: sh1v4dcd0_cp3 <= not sh1v3dcd0_cp2_b; + s1v4d0c4: sh1v4dcd0_cp4 <= not sh1v3dcd0_cp2_b; + + s1v2d1c1: sh1v2dcd1_cp1 <= not ex1_lvl1_shdcd001_b; + s1v3d1c1: sh1v3dcd1_cp1_b <= not sh1v2dcd1_cp1 ; + s1v3d1c2: sh1v3dcd1_cp2_b <= not sh1v2dcd1_cp1 ; + s1v4d1c1: sh1v4dcd1_cp1 <= not sh1v3dcd1_cp1_b; + s1v4d1c2: sh1v4dcd1_cp2 <= not sh1v3dcd1_cp1_b; + s1v4d1c3: sh1v4dcd1_cp3 <= not sh1v3dcd1_cp2_b; + s1v4d1c4: sh1v4dcd1_cp4 <= not sh1v3dcd1_cp2_b; + + s1v2d2c1: sh1v2dcd2_cp1 <= not ex1_lvl1_shdcd002_b; + s1v3d2c1: sh1v3dcd2_cp1_b <= not sh1v2dcd2_cp1 ; + s1v3d2c2: sh1v3dcd2_cp2_b <= not sh1v2dcd2_cp1 ; + s1v4d2c1: sh1v4dcd2_cp1 <= not sh1v3dcd2_cp1_b; + s1v4d2c2: sh1v4dcd2_cp2 <= not sh1v3dcd2_cp1_b; + s1v4d2c3: sh1v4dcd2_cp3 <= not sh1v3dcd2_cp2_b; + s1v4d2c4: sh1v4dcd2_cp4 <= not sh1v3dcd2_cp2_b; + + s1v2d3c1: sh1v2dcd3_cp1 <= not ex1_lvl1_shdcd003_b; + s1v3d3c1: sh1v3dcd3_cp1_b <= not sh1v2dcd3_cp1 ; + s1v3d3c2: sh1v3dcd3_cp2_b <= not sh1v2dcd3_cp1 ; + s1v4d3c1: sh1v4dcd3_cp1 <= not sh1v3dcd3_cp1_b; + s1v4d3c2: sh1v4dcd3_cp2 <= not sh1v3dcd3_cp1_b; + s1v4d3c3: sh1v4dcd3_cp3 <= not sh1v3dcd3_cp2_b; + s1v4d3c4: sh1v4dcd3_cp4 <= not sh1v3dcd3_cp2_b; + + + s2v1d00c1: sh2v1dcd00_cp1_b <= not ex1_lvl2_shdcd000; + s2v2d00c1: sh2v2dcd00_cp1 <= not sh2v1dcd00_cp1_b ; + s2v3d00c1: sh2v3dcd00_cp1_b <= not sh2v2dcd00_cp1 ; + s2v3d00c2: sh2v3dcd00_cp2_b <= not sh2v2dcd00_cp1 ; + s2v4d00c1: sh2v4dcd00_cp1 <= not sh2v3dcd00_cp1_b; + s2v4d00c2: sh2v4dcd00_cp2 <= not sh2v3dcd00_cp1_b; + s2v4d00c3: sh2v4dcd00_cp3 <= not sh2v3dcd00_cp2_b; + s2v4d00c4: sh2v4dcd00_cp4 <= not sh2v3dcd00_cp2_b; + + s2v1d04c1: sh2v1dcd04_cp1_b <= not ex1_lvl2_shdcd004; + s2v2d04c1: sh2v2dcd04_cp1 <= not sh2v1dcd04_cp1_b ; + s2v3d04c1: sh2v3dcd04_cp1_b <= not sh2v2dcd04_cp1 ; + s2v3d04c2: sh2v3dcd04_cp2_b <= not sh2v2dcd04_cp1 ; + s2v4d04c1: sh2v4dcd04_cp1 <= not sh2v3dcd04_cp1_b; + s2v4d04c2: sh2v4dcd04_cp2 <= not sh2v3dcd04_cp1_b; + s2v4d04c3: sh2v4dcd04_cp3 <= not sh2v3dcd04_cp2_b; + s2v4d04c4: sh2v4dcd04_cp4 <= not sh2v3dcd04_cp2_b; + + s2v1d08c1: sh2v1dcd08_cp1_b <= not ex1_lvl2_shdcd008; + s2v2d08c1: sh2v2dcd08_cp1 <= not sh2v1dcd08_cp1_b ; + s2v3d08c1: sh2v3dcd08_cp1_b <= not sh2v2dcd08_cp1 ; + s2v3d08c2: sh2v3dcd08_cp2_b <= not sh2v2dcd08_cp1 ; + s2v4d08c1: sh2v4dcd08_cp1 <= not sh2v3dcd08_cp1_b; + s2v4d08c2: sh2v4dcd08_cp2 <= not sh2v3dcd08_cp1_b; + s2v4d08c3: sh2v4dcd08_cp3 <= not sh2v3dcd08_cp2_b; + s2v4d08c4: sh2v4dcd08_cp4 <= not sh2v3dcd08_cp2_b; + + s2v1d12c1: sh2v1dcd12_cp1_b <= not ex1_lvl2_shdcd012; + s2v2d12c1: sh2v2dcd12_cp1 <= not sh2v1dcd12_cp1_b ; + s2v3d12c1: sh2v3dcd12_cp1_b <= not sh2v2dcd12_cp1 ; + s2v3d12c2: sh2v3dcd12_cp2_b <= not sh2v2dcd12_cp1 ; + s2v4d12c1: sh2v4dcd12_cp1 <= not sh2v3dcd12_cp1_b; + s2v4d12c2: sh2v4dcd12_cp2 <= not sh2v3dcd12_cp1_b; + s2v4d12c3: sh2v4dcd12_cp3 <= not sh2v3dcd12_cp2_b; + s2v4d12c4: sh2v4dcd12_cp4 <= not sh2v3dcd12_cp2_b; + + s2v1dppc1: sh2v1dcdpp_cp1_b <= not ex1_sel_special ; + s2v2dppc1: sh2v2dcdpp_cp1 <= not sh2v1dcdpp_cp1_b ; + s2v3dppc1: sh2v3dcdpp_cp1_b <= not sh2v2dcdpp_cp1 ; + s2v3dppc2: sh2v3dcdpp_cp2_b <= not sh2v2dcdpp_cp1 ; + s2v4dppc1: sh2v4dcdpp_cp1 <= not sh2v3dcdpp_cp1_b; + s2v4dppc2: sh2v4dcdpp_cp2 <= not sh2v3dcdpp_cp1_b; + s2v4dppc3: sh2v4dcdpp_cp3 <= not sh2v3dcdpp_cp2_b; + s2v4dppc4: sh2v4dcdpp_cp4 <= not sh2v3dcdpp_cp2_b; + + + + lv1x_00: ex1_sh_lv1x_b(0) <= not( sh1v4dcd0_cp1 and ex1_b_frac(0) ) ; + lv1x_01: ex1_sh_lv1x_b(1) <= not( (sh1v4dcd0_cp1 and ex1_b_frac(1) ) or (sh1v4dcd1_cp1 and ex1_b_frac(0) ) ); + lv1x_02: ex1_sh_lv1x_b(2) <= not( (sh1v4dcd0_cp1 and ex1_b_frac(2) ) or (sh1v4dcd1_cp1 and ex1_b_frac(1) ) ); + lv1x_03: ex1_sh_lv1x_b(3) <= not( (sh1v4dcd0_cp1 and ex1_b_frac(3) ) or (sh1v4dcd1_cp1 and ex1_b_frac(2) ) ); + lv1x_04: ex1_sh_lv1x_b(4) <= not( (sh1v4dcd0_cp1 and ex1_b_frac(4) ) or (sh1v4dcd1_cp1 and ex1_b_frac(3) ) ); + lv1x_05: ex1_sh_lv1x_b(5) <= not( (sh1v4dcd0_cp1 and ex1_b_frac(5) ) or (sh1v4dcd1_cp1 and ex1_b_frac(4) ) ); + lv1x_06: ex1_sh_lv1x_b(6) <= not( (sh1v4dcd0_cp1 and ex1_b_frac(6) ) or (sh1v4dcd1_cp1 and ex1_b_frac(5) ) ); + lv1x_07: ex1_sh_lv1x_b(7) <= not( (sh1v4dcd0_cp1 and ex1_b_frac(7) ) or (sh1v4dcd1_cp1 and ex1_b_frac(6) ) ); + lv1x_08: ex1_sh_lv1x_b(8) <= not( (sh1v4dcd0_cp1 and ex1_b_frac(8) ) or (sh1v4dcd1_cp1 and ex1_b_frac(7) ) ); + lv1x_09: ex1_sh_lv1x_b(9) <= not( (sh1v4dcd0_cp1 and ex1_b_frac(9) ) or (sh1v4dcd1_cp1 and ex1_b_frac(8) ) ); + lv1x_10: ex1_sh_lv1x_b(10) <= not( (sh1v4dcd0_cp1 and ex1_b_frac(10) ) or (sh1v4dcd1_cp1 and ex1_b_frac(9) ) ); + lv1x_11: ex1_sh_lv1x_b(11) <= not( (sh1v4dcd0_cp1 and ex1_b_frac(11) ) or (sh1v4dcd1_cp1 and ex1_b_frac(10) ) ); + lv1x_12: ex1_sh_lv1x_b(12) <= not( (sh1v4dcd0_cp1 and ex1_b_frac(12) ) or (sh1v4dcd1_cp1 and ex1_b_frac(11) ) ); + lv1x_13: ex1_sh_lv1x_b(13) <= not( (sh1v4dcd0_cp1 and ex1_b_frac(13) ) or (sh1v4dcd1_cp1 and ex1_b_frac(12) ) ); + lv1x_14: ex1_sh_lv1x_b(14) <= not( (sh1v4dcd0_cp2 and ex1_b_frac(14) ) or (sh1v4dcd1_cp2 and ex1_b_frac(13) ) ); + lv1x_15: ex1_sh_lv1x_b(15) <= not( (sh1v4dcd0_cp2 and ex1_b_frac(15) ) or (sh1v4dcd1_cp2 and ex1_b_frac(14) ) ); + lv1x_16: ex1_sh_lv1x_b(16) <= not( (sh1v4dcd0_cp2 and ex1_b_frac(16) ) or (sh1v4dcd1_cp2 and ex1_b_frac(15) ) ); + lv1x_17: ex1_sh_lv1x_b(17) <= not( (sh1v4dcd0_cp2 and ex1_b_frac(17) ) or (sh1v4dcd1_cp2 and ex1_b_frac(16) ) ); + lv1x_18: ex1_sh_lv1x_b(18) <= not( (sh1v4dcd0_cp2 and ex1_b_frac(18) ) or (sh1v4dcd1_cp2 and ex1_b_frac(17) ) ); + lv1x_19: ex1_sh_lv1x_b(19) <= not( (sh1v4dcd0_cp2 and ex1_b_frac(19) ) or (sh1v4dcd1_cp2 and ex1_b_frac(18) ) ); + lv1x_20: ex1_sh_lv1x_b(20) <= not( (sh1v4dcd0_cp2 and ex1_b_frac(20) ) or (sh1v4dcd1_cp2 and ex1_b_frac(19) ) ); + lv1x_21: ex1_sh_lv1x_b(21) <= not( (sh1v4dcd0_cp2 and ex1_b_frac(21) ) or (sh1v4dcd1_cp2 and ex1_b_frac(20) ) ); + lv1x_22: ex1_sh_lv1x_b(22) <= not( (sh1v4dcd0_cp2 and ex1_b_frac(22) ) or (sh1v4dcd1_cp2 and ex1_b_frac(21) ) ); + lv1x_23: ex1_sh_lv1x_b(23) <= not( (sh1v4dcd0_cp2 and ex1_b_frac(23) ) or (sh1v4dcd1_cp2 and ex1_b_frac(22) ) ); + lv1x_24: ex1_sh_lv1x_b(24) <= not( (sh1v4dcd0_cp2 and ex1_b_frac(24) ) or (sh1v4dcd1_cp2 and ex1_b_frac(23) ) ); + lv1x_25: ex1_sh_lv1x_b(25) <= not( (sh1v4dcd0_cp2 and ex1_b_frac(25) ) or (sh1v4dcd1_cp2 and ex1_b_frac(24) ) ); + lv1x_26: ex1_sh_lv1x_b(26) <= not( (sh1v4dcd0_cp2 and ex1_b_frac(26) ) or (sh1v4dcd1_cp2 and ex1_b_frac(25) ) ); + lv1x_27: ex1_sh_lv1x_b(27) <= not( (sh1v4dcd0_cp2 and ex1_b_frac(27) ) or (sh1v4dcd1_cp2 and ex1_b_frac(26) ) ); + lv1x_28: ex1_sh_lv1x_b(28) <= not( (sh1v4dcd0_cp3 and ex1_b_frac(28) ) or (sh1v4dcd1_cp3 and ex1_b_frac(27) ) ); + lv1x_29: ex1_sh_lv1x_b(29) <= not( (sh1v4dcd0_cp3 and ex1_b_frac(29) ) or (sh1v4dcd1_cp3 and ex1_b_frac(28) ) ); + lv1x_30: ex1_sh_lv1x_b(30) <= not( (sh1v4dcd0_cp3 and ex1_b_frac(30) ) or (sh1v4dcd1_cp3 and ex1_b_frac(29) ) ); + lv1x_31: ex1_sh_lv1x_b(31) <= not( (sh1v4dcd0_cp3 and ex1_b_frac(31) ) or (sh1v4dcd1_cp3 and ex1_b_frac(30) ) ); + lv1x_32: ex1_sh_lv1x_b(32) <= not( (sh1v4dcd0_cp3 and ex1_b_frac(32) ) or (sh1v4dcd1_cp3 and ex1_b_frac(31) ) ); + lv1x_33: ex1_sh_lv1x_b(33) <= not( (sh1v4dcd0_cp3 and ex1_b_frac(33) ) or (sh1v4dcd1_cp3 and ex1_b_frac(32) ) ); + lv1x_34: ex1_sh_lv1x_b(34) <= not( (sh1v4dcd0_cp3 and ex1_b_frac(34) ) or (sh1v4dcd1_cp3 and ex1_b_frac(33) ) ); + lv1x_35: ex1_sh_lv1x_b(35) <= not( (sh1v4dcd0_cp3 and ex1_b_frac(35) ) or (sh1v4dcd1_cp3 and ex1_b_frac(34) ) ); + lv1x_36: ex1_sh_lv1x_b(36) <= not( (sh1v4dcd0_cp3 and ex1_b_frac(36) ) or (sh1v4dcd1_cp3 and ex1_b_frac(35) ) ); + lv1x_37: ex1_sh_lv1x_b(37) <= not( (sh1v4dcd0_cp3 and ex1_b_frac(37) ) or (sh1v4dcd1_cp3 and ex1_b_frac(36) ) ); + lv1x_38: ex1_sh_lv1x_b(38) <= not( (sh1v4dcd0_cp3 and ex1_b_frac(38) ) or (sh1v4dcd1_cp3 and ex1_b_frac(37) ) ); + lv1x_39: ex1_sh_lv1x_b(39) <= not( (sh1v4dcd0_cp3 and ex1_b_frac(39) ) or (sh1v4dcd1_cp3 and ex1_b_frac(38) ) ); + lv1x_40: ex1_sh_lv1x_b(40) <= not( (sh1v4dcd0_cp3 and ex1_b_frac(40) ) or (sh1v4dcd1_cp3 and ex1_b_frac(39) ) ); + lv1x_41: ex1_sh_lv1x_b(41) <= not( (sh1v4dcd0_cp3 and ex1_b_frac(41) ) or (sh1v4dcd1_cp3 and ex1_b_frac(40) ) ); + lv1x_42: ex1_sh_lv1x_b(42) <= not( (sh1v4dcd0_cp4 and ex1_b_frac(42) ) or (sh1v4dcd1_cp4 and ex1_b_frac(41) ) ); + lv1x_43: ex1_sh_lv1x_b(43) <= not( (sh1v4dcd0_cp4 and ex1_b_frac(43) ) or (sh1v4dcd1_cp4 and ex1_b_frac(42) ) ); + lv1x_44: ex1_sh_lv1x_b(44) <= not( (sh1v4dcd0_cp4 and ex1_b_frac(44) ) or (sh1v4dcd1_cp4 and ex1_b_frac(43) ) ); + lv1x_45: ex1_sh_lv1x_b(45) <= not( (sh1v4dcd0_cp4 and ex1_b_frac(45) ) or (sh1v4dcd1_cp4 and ex1_b_frac(44) ) ); + lv1x_46: ex1_sh_lv1x_b(46) <= not( (sh1v4dcd0_cp4 and ex1_b_frac(46) ) or (sh1v4dcd1_cp4 and ex1_b_frac(45) ) ); + lv1x_47: ex1_sh_lv1x_b(47) <= not( (sh1v4dcd0_cp4 and ex1_b_frac(47) ) or (sh1v4dcd1_cp4 and ex1_b_frac(46) ) ); + lv1x_48: ex1_sh_lv1x_b(48) <= not( (sh1v4dcd0_cp4 and ex1_b_frac(48) ) or (sh1v4dcd1_cp4 and ex1_b_frac(47) ) ); + lv1x_49: ex1_sh_lv1x_b(49) <= not( (sh1v4dcd0_cp4 and ex1_b_frac(49) ) or (sh1v4dcd1_cp4 and ex1_b_frac(48) ) ); + lv1x_50: ex1_sh_lv1x_b(50) <= not( (sh1v4dcd0_cp4 and ex1_b_frac(50) ) or (sh1v4dcd1_cp4 and ex1_b_frac(49) ) ); + lv1x_51: ex1_sh_lv1x_b(51) <= not( (sh1v4dcd0_cp4 and ex1_b_frac(51) ) or (sh1v4dcd1_cp4 and ex1_b_frac(50) ) ); + lv1x_52: ex1_sh_lv1x_b(52) <= not( (sh1v4dcd0_cp4 and ex1_b_frac(52) ) or (sh1v4dcd1_cp4 and ex1_b_frac(51) ) ); + lv1x_53: ex1_sh_lv1x_b(53) <= not( sh1v4dcd1_cp4 and ex1_b_frac(52) ); + + + + lv1y_02: ex1_sh_lv1y_b(2) <= not( sh1v4dcd2_cp1 and ex1_b_frac(0) ) ; + lv1y_03: ex1_sh_lv1y_b(3) <= not( (sh1v4dcd2_cp1 and ex1_b_frac(1) ) or (sh1v4dcd3_cp1 and ex1_b_frac(0) ) ); + lv1y_04: ex1_sh_lv1y_b(4) <= not( (sh1v4dcd2_cp1 and ex1_b_frac(2) ) or (sh1v4dcd3_cp1 and ex1_b_frac(1) ) ); + lv1y_05: ex1_sh_lv1y_b(5) <= not( (sh1v4dcd2_cp1 and ex1_b_frac(3) ) or (sh1v4dcd3_cp1 and ex1_b_frac(2) ) ); + lv1y_06: ex1_sh_lv1y_b(6) <= not( (sh1v4dcd2_cp1 and ex1_b_frac(4) ) or (sh1v4dcd3_cp1 and ex1_b_frac(3) ) ); + lv1y_07: ex1_sh_lv1y_b(7) <= not( (sh1v4dcd2_cp1 and ex1_b_frac(5) ) or (sh1v4dcd3_cp1 and ex1_b_frac(4) ) ); + lv1y_08: ex1_sh_lv1y_b(8) <= not( (sh1v4dcd2_cp1 and ex1_b_frac(6) ) or (sh1v4dcd3_cp1 and ex1_b_frac(5) ) ); + lv1y_09: ex1_sh_lv1y_b(9) <= not( (sh1v4dcd2_cp1 and ex1_b_frac(7) ) or (sh1v4dcd3_cp1 and ex1_b_frac(6) ) ); + lv1y_10: ex1_sh_lv1y_b(10) <= not( (sh1v4dcd2_cp1 and ex1_b_frac(8) ) or (sh1v4dcd3_cp1 and ex1_b_frac(7) ) ); + lv1y_11: ex1_sh_lv1y_b(11) <= not( (sh1v4dcd2_cp1 and ex1_b_frac(9) ) or (sh1v4dcd3_cp1 and ex1_b_frac(8) ) ); + lv1y_12: ex1_sh_lv1y_b(12) <= not( (sh1v4dcd2_cp1 and ex1_b_frac(10) ) or (sh1v4dcd3_cp1 and ex1_b_frac(9) ) ); + lv1y_13: ex1_sh_lv1y_b(13) <= not( (sh1v4dcd2_cp1 and ex1_b_frac(11) ) or (sh1v4dcd3_cp1 and ex1_b_frac(10) ) ); + lv1y_14: ex1_sh_lv1y_b(14) <= not( (sh1v4dcd2_cp2 and ex1_b_frac(12) ) or (sh1v4dcd3_cp2 and ex1_b_frac(11) ) ); + lv1y_15: ex1_sh_lv1y_b(15) <= not( (sh1v4dcd2_cp2 and ex1_b_frac(13) ) or (sh1v4dcd3_cp2 and ex1_b_frac(12) ) ); + lv1y_16: ex1_sh_lv1y_b(16) <= not( (sh1v4dcd2_cp2 and ex1_b_frac(14) ) or (sh1v4dcd3_cp2 and ex1_b_frac(13) ) ); + lv1y_17: ex1_sh_lv1y_b(17) <= not( (sh1v4dcd2_cp2 and ex1_b_frac(15) ) or (sh1v4dcd3_cp2 and ex1_b_frac(14) ) ); + lv1y_18: ex1_sh_lv1y_b(18) <= not( (sh1v4dcd2_cp2 and ex1_b_frac(16) ) or (sh1v4dcd3_cp2 and ex1_b_frac(15) ) ); + lv1y_19: ex1_sh_lv1y_b(19) <= not( (sh1v4dcd2_cp2 and ex1_b_frac(17) ) or (sh1v4dcd3_cp2 and ex1_b_frac(16) ) ); + lv1y_20: ex1_sh_lv1y_b(20) <= not( (sh1v4dcd2_cp2 and ex1_b_frac(18) ) or (sh1v4dcd3_cp2 and ex1_b_frac(17) ) ); + lv1y_21: ex1_sh_lv1y_b(21) <= not( (sh1v4dcd2_cp2 and ex1_b_frac(19) ) or (sh1v4dcd3_cp2 and ex1_b_frac(18) ) ); + lv1y_22: ex1_sh_lv1y_b(22) <= not( (sh1v4dcd2_cp2 and ex1_b_frac(20) ) or (sh1v4dcd3_cp2 and ex1_b_frac(19) ) ); + lv1y_23: ex1_sh_lv1y_b(23) <= not( (sh1v4dcd2_cp2 and ex1_b_frac(21) ) or (sh1v4dcd3_cp2 and ex1_b_frac(20) ) ); + lv1y_24: ex1_sh_lv1y_b(24) <= not( (sh1v4dcd2_cp2 and ex1_b_frac(22) ) or (sh1v4dcd3_cp2 and ex1_b_frac(21) ) ); + lv1y_25: ex1_sh_lv1y_b(25) <= not( (sh1v4dcd2_cp2 and ex1_b_frac(23) ) or (sh1v4dcd3_cp2 and ex1_b_frac(22) ) ); + lv1y_26: ex1_sh_lv1y_b(26) <= not( (sh1v4dcd2_cp2 and ex1_b_frac(24) ) or (sh1v4dcd3_cp2 and ex1_b_frac(23) ) ); + lv1y_27: ex1_sh_lv1y_b(27) <= not( (sh1v4dcd2_cp2 and ex1_b_frac(25) ) or (sh1v4dcd3_cp2 and ex1_b_frac(24) ) ); + lv1y_28: ex1_sh_lv1y_b(28) <= not( (sh1v4dcd2_cp3 and ex1_b_frac(26) ) or (sh1v4dcd3_cp3 and ex1_b_frac(25) ) ); + lv1y_29: ex1_sh_lv1y_b(29) <= not( (sh1v4dcd2_cp3 and ex1_b_frac(27) ) or (sh1v4dcd3_cp3 and ex1_b_frac(26) ) ); + lv1y_30: ex1_sh_lv1y_b(30) <= not( (sh1v4dcd2_cp3 and ex1_b_frac(28) ) or (sh1v4dcd3_cp3 and ex1_b_frac(27) ) ); + lv1y_31: ex1_sh_lv1y_b(31) <= not( (sh1v4dcd2_cp3 and ex1_b_frac(29) ) or (sh1v4dcd3_cp3 and ex1_b_frac(28) ) ); + lv1y_32: ex1_sh_lv1y_b(32) <= not( (sh1v4dcd2_cp3 and ex1_b_frac(30) ) or (sh1v4dcd3_cp3 and ex1_b_frac(29) ) ); + lv1y_33: ex1_sh_lv1y_b(33) <= not( (sh1v4dcd2_cp3 and ex1_b_frac(31) ) or (sh1v4dcd3_cp3 and ex1_b_frac(30) ) ); + lv1y_34: ex1_sh_lv1y_b(34) <= not( (sh1v4dcd2_cp3 and ex1_b_frac(32) ) or (sh1v4dcd3_cp3 and ex1_b_frac(31) ) ); + lv1y_35: ex1_sh_lv1y_b(35) <= not( (sh1v4dcd2_cp3 and ex1_b_frac(33) ) or (sh1v4dcd3_cp3 and ex1_b_frac(32) ) ); + lv1y_36: ex1_sh_lv1y_b(36) <= not( (sh1v4dcd2_cp3 and ex1_b_frac(34) ) or (sh1v4dcd3_cp3 and ex1_b_frac(33) ) ); + lv1y_37: ex1_sh_lv1y_b(37) <= not( (sh1v4dcd2_cp3 and ex1_b_frac(35) ) or (sh1v4dcd3_cp3 and ex1_b_frac(34) ) ); + lv1y_38: ex1_sh_lv1y_b(38) <= not( (sh1v4dcd2_cp3 and ex1_b_frac(36) ) or (sh1v4dcd3_cp3 and ex1_b_frac(35) ) ); + lv1y_39: ex1_sh_lv1y_b(39) <= not( (sh1v4dcd2_cp3 and ex1_b_frac(37) ) or (sh1v4dcd3_cp3 and ex1_b_frac(36) ) ); + lv1y_40: ex1_sh_lv1y_b(40) <= not( (sh1v4dcd2_cp3 and ex1_b_frac(38) ) or (sh1v4dcd3_cp3 and ex1_b_frac(37) ) ); + lv1y_41: ex1_sh_lv1y_b(41) <= not( (sh1v4dcd2_cp4 and ex1_b_frac(39) ) or (sh1v4dcd3_cp4 and ex1_b_frac(38) ) ); + lv1y_42: ex1_sh_lv1y_b(42) <= not( (sh1v4dcd2_cp4 and ex1_b_frac(40) ) or (sh1v4dcd3_cp4 and ex1_b_frac(39) ) ); + lv1y_43: ex1_sh_lv1y_b(43) <= not( (sh1v4dcd2_cp4 and ex1_b_frac(41) ) or (sh1v4dcd3_cp4 and ex1_b_frac(40) ) ); + lv1y_44: ex1_sh_lv1y_b(44) <= not( (sh1v4dcd2_cp4 and ex1_b_frac(42) ) or (sh1v4dcd3_cp4 and ex1_b_frac(41) ) ); + lv1y_45: ex1_sh_lv1y_b(45) <= not( (sh1v4dcd2_cp4 and ex1_b_frac(43) ) or (sh1v4dcd3_cp4 and ex1_b_frac(42) ) ); + lv1y_46: ex1_sh_lv1y_b(46) <= not( (sh1v4dcd2_cp4 and ex1_b_frac(44) ) or (sh1v4dcd3_cp4 and ex1_b_frac(43) ) ); + lv1y_47: ex1_sh_lv1y_b(47) <= not( (sh1v4dcd2_cp4 and ex1_b_frac(45) ) or (sh1v4dcd3_cp4 and ex1_b_frac(44) ) ); + lv1y_48: ex1_sh_lv1y_b(48) <= not( (sh1v4dcd2_cp4 and ex1_b_frac(46) ) or (sh1v4dcd3_cp4 and ex1_b_frac(45) ) ); + lv1y_49: ex1_sh_lv1y_b(49) <= not( (sh1v4dcd2_cp4 and ex1_b_frac(47) ) or (sh1v4dcd3_cp4 and ex1_b_frac(46) ) ); + lv1y_50: ex1_sh_lv1y_b(50) <= not( (sh1v4dcd2_cp4 and ex1_b_frac(48) ) or (sh1v4dcd3_cp4 and ex1_b_frac(47) ) ); + lv1y_51: ex1_sh_lv1y_b(51) <= not( (sh1v4dcd2_cp4 and ex1_b_frac(49) ) or (sh1v4dcd3_cp4 and ex1_b_frac(48) ) ); + lv1y_52: ex1_sh_lv1y_b(52) <= not( (sh1v4dcd2_cp4 and ex1_b_frac(50) ) or (sh1v4dcd3_cp4 and ex1_b_frac(49) ) ); + lv1y_53: ex1_sh_lv1y_b(53) <= not( (sh1v4dcd2_cp4 and ex1_b_frac(51) ) or (sh1v4dcd3_cp4 and ex1_b_frac(50) ) ); + lv1y_54: ex1_sh_lv1y_b(54) <= not( (sh1v4dcd2_cp4 and ex1_b_frac(52) ) or (sh1v4dcd3_cp4 and ex1_b_frac(51) ) ); + lv1y_55: ex1_sh_lv1y_b(55) <= not( sh1v4dcd3_cp4 and ex1_b_frac(52) ); + + lv1_00: ex1_sh_lv1(0) <= not( ex1_sh_lv1x_b(0) ); + lv1_01: ex1_sh_lv1(1) <= not( ex1_sh_lv1x_b(1) ); + lv1_02: ex1_sh_lv1(2) <= not( ex1_sh_lv1x_b(2) and ex1_sh_lv1y_b(2) ); + lv1_03: ex1_sh_lv1(3) <= not( ex1_sh_lv1x_b(3) and ex1_sh_lv1y_b(3) ); + lv1_04: ex1_sh_lv1(4) <= not( ex1_sh_lv1x_b(4) and ex1_sh_lv1y_b(4) ); + lv1_05: ex1_sh_lv1(5) <= not( ex1_sh_lv1x_b(5) and ex1_sh_lv1y_b(5) ); + lv1_06: ex1_sh_lv1(6) <= not( ex1_sh_lv1x_b(6) and ex1_sh_lv1y_b(6) ); + lv1_07: ex1_sh_lv1(7) <= not( ex1_sh_lv1x_b(7) and ex1_sh_lv1y_b(7) ); + lv1_08: ex1_sh_lv1(8) <= not( ex1_sh_lv1x_b(8) and ex1_sh_lv1y_b(8) ); + lv1_09: ex1_sh_lv1(9) <= not( ex1_sh_lv1x_b(9) and ex1_sh_lv1y_b(9) ); + lv1_10: ex1_sh_lv1(10) <= not( ex1_sh_lv1x_b(10) and ex1_sh_lv1y_b(10) ); + lv1_11: ex1_sh_lv1(11) <= not( ex1_sh_lv1x_b(11) and ex1_sh_lv1y_b(11) ); + lv1_12: ex1_sh_lv1(12) <= not( ex1_sh_lv1x_b(12) and ex1_sh_lv1y_b(12) ); + lv1_13: ex1_sh_lv1(13) <= not( ex1_sh_lv1x_b(13) and ex1_sh_lv1y_b(13) ); + lv1_14: ex1_sh_lv1(14) <= not( ex1_sh_lv1x_b(14) and ex1_sh_lv1y_b(14) ); + lv1_15: ex1_sh_lv1(15) <= not( ex1_sh_lv1x_b(15) and ex1_sh_lv1y_b(15) ); + lv1_16: ex1_sh_lv1(16) <= not( ex1_sh_lv1x_b(16) and ex1_sh_lv1y_b(16) ); + lv1_17: ex1_sh_lv1(17) <= not( ex1_sh_lv1x_b(17) and ex1_sh_lv1y_b(17) ); + lv1_18: ex1_sh_lv1(18) <= not( ex1_sh_lv1x_b(18) and ex1_sh_lv1y_b(18) ); + lv1_19: ex1_sh_lv1(19) <= not( ex1_sh_lv1x_b(19) and ex1_sh_lv1y_b(19) ); + lv1_20: ex1_sh_lv1(20) <= not( ex1_sh_lv1x_b(20) and ex1_sh_lv1y_b(20) ); + lv1_21: ex1_sh_lv1(21) <= not( ex1_sh_lv1x_b(21) and ex1_sh_lv1y_b(21) ); + lv1_22: ex1_sh_lv1(22) <= not( ex1_sh_lv1x_b(22) and ex1_sh_lv1y_b(22) ); + lv1_23: ex1_sh_lv1(23) <= not( ex1_sh_lv1x_b(23) and ex1_sh_lv1y_b(23) ); + lv1_24: ex1_sh_lv1(24) <= not( ex1_sh_lv1x_b(24) and ex1_sh_lv1y_b(24) ); + lv1_25: ex1_sh_lv1(25) <= not( ex1_sh_lv1x_b(25) and ex1_sh_lv1y_b(25) ); + lv1_26: ex1_sh_lv1(26) <= not( ex1_sh_lv1x_b(26) and ex1_sh_lv1y_b(26) ); + lv1_27: ex1_sh_lv1(27) <= not( ex1_sh_lv1x_b(27) and ex1_sh_lv1y_b(27) ); + lv1_28: ex1_sh_lv1(28) <= not( ex1_sh_lv1x_b(28) and ex1_sh_lv1y_b(28) ); + lv1_29: ex1_sh_lv1(29) <= not( ex1_sh_lv1x_b(29) and ex1_sh_lv1y_b(29) ); + lv1_30: ex1_sh_lv1(30) <= not( ex1_sh_lv1x_b(30) and ex1_sh_lv1y_b(30) ); + lv1_31: ex1_sh_lv1(31) <= not( ex1_sh_lv1x_b(31) and ex1_sh_lv1y_b(31) ); + lv1_32: ex1_sh_lv1(32) <= not( ex1_sh_lv1x_b(32) and ex1_sh_lv1y_b(32) ); + lv1_33: ex1_sh_lv1(33) <= not( ex1_sh_lv1x_b(33) and ex1_sh_lv1y_b(33) ); + lv1_34: ex1_sh_lv1(34) <= not( ex1_sh_lv1x_b(34) and ex1_sh_lv1y_b(34) ); + lv1_35: ex1_sh_lv1(35) <= not( ex1_sh_lv1x_b(35) and ex1_sh_lv1y_b(35) ); + lv1_36: ex1_sh_lv1(36) <= not( ex1_sh_lv1x_b(36) and ex1_sh_lv1y_b(36) ); + lv1_37: ex1_sh_lv1(37) <= not( ex1_sh_lv1x_b(37) and ex1_sh_lv1y_b(37) ); + lv1_38: ex1_sh_lv1(38) <= not( ex1_sh_lv1x_b(38) and ex1_sh_lv1y_b(38) ); + lv1_39: ex1_sh_lv1(39) <= not( ex1_sh_lv1x_b(39) and ex1_sh_lv1y_b(39) ); + lv1_40: ex1_sh_lv1(40) <= not( ex1_sh_lv1x_b(40) and ex1_sh_lv1y_b(40) ); + lv1_41: ex1_sh_lv1(41) <= not( ex1_sh_lv1x_b(41) and ex1_sh_lv1y_b(41) ); + lv1_42: ex1_sh_lv1(42) <= not( ex1_sh_lv1x_b(42) and ex1_sh_lv1y_b(42) ); + lv1_43: ex1_sh_lv1(43) <= not( ex1_sh_lv1x_b(43) and ex1_sh_lv1y_b(43) ); + lv1_44: ex1_sh_lv1(44) <= not( ex1_sh_lv1x_b(44) and ex1_sh_lv1y_b(44) ); + lv1_45: ex1_sh_lv1(45) <= not( ex1_sh_lv1x_b(45) and ex1_sh_lv1y_b(45) ); + lv1_46: ex1_sh_lv1(46) <= not( ex1_sh_lv1x_b(46) and ex1_sh_lv1y_b(46) ); + lv1_47: ex1_sh_lv1(47) <= not( ex1_sh_lv1x_b(47) and ex1_sh_lv1y_b(47) ); + lv1_48: ex1_sh_lv1(48) <= not( ex1_sh_lv1x_b(48) and ex1_sh_lv1y_b(48) ); + lv1_49: ex1_sh_lv1(49) <= not( ex1_sh_lv1x_b(49) and ex1_sh_lv1y_b(49) ); + lv1_50: ex1_sh_lv1(50) <= not( ex1_sh_lv1x_b(50) and ex1_sh_lv1y_b(50) ); + lv1_51: ex1_sh_lv1(51) <= not( ex1_sh_lv1x_b(51) and ex1_sh_lv1y_b(51) ); + lv1_52: ex1_sh_lv1(52) <= not( ex1_sh_lv1x_b(52) and ex1_sh_lv1y_b(52) ); + lv1_53: ex1_sh_lv1(53) <= not( ex1_sh_lv1x_b(53) and ex1_sh_lv1y_b(53) ); + lv1_54: ex1_sh_lv1(54) <= not( ex1_sh_lv1y_b(54) ); + lv1_55: ex1_sh_lv1(55) <= not( ex1_sh_lv1y_b(55) ); + + + + lv2x_00: ex1_sh_lv2x_b(0) <= not( sh2v4dcd00_cp1 and ex1_sh_lv1(0) ); + lv2x_01: ex1_sh_lv2x_b(1) <= not( sh2v4dcd00_cp1 and ex1_sh_lv1(1) ); + lv2x_02: ex1_sh_lv2x_b(2) <= not( sh2v4dcd00_cp1 and ex1_sh_lv1(2) ); + lv2x_03: ex1_sh_lv2x_b(3) <= not( sh2v4dcd00_cp1 and ex1_sh_lv1(3) ); + lv2x_04: ex1_sh_lv2x_b(4) <= not( (sh2v4dcd00_cp1 and ex1_sh_lv1(4) ) or (sh2v4dcd04_cp1 and ex1_sh_lv1(0) ) ); + lv2x_05: ex1_sh_lv2x_b(5) <= not( (sh2v4dcd00_cp1 and ex1_sh_lv1(5) ) or (sh2v4dcd04_cp1 and ex1_sh_lv1(1) ) ); + lv2x_06: ex1_sh_lv2x_b(6) <= not( (sh2v4dcd00_cp1 and ex1_sh_lv1(6) ) or (sh2v4dcd04_cp1 and ex1_sh_lv1(2) ) ); + lv2x_07: ex1_sh_lv2x_b(7) <= not( (sh2v4dcd00_cp1 and ex1_sh_lv1(7) ) or (sh2v4dcd04_cp1 and ex1_sh_lv1(3) ) ); + lv2x_08: ex1_sh_lv2x_b(8) <= not( (sh2v4dcd00_cp1 and ex1_sh_lv1(8) ) or (sh2v4dcd04_cp1 and ex1_sh_lv1(4) ) ); + lv2x_09: ex1_sh_lv2x_b(9) <= not( (sh2v4dcd00_cp1 and ex1_sh_lv1(9) ) or (sh2v4dcd04_cp1 and ex1_sh_lv1(5) ) ); + lv2x_10: ex1_sh_lv2x_b(10) <= not( (sh2v4dcd00_cp1 and ex1_sh_lv1(10) ) or (sh2v4dcd04_cp1 and ex1_sh_lv1(6) ) ); + lv2x_11: ex1_sh_lv2x_b(11) <= not( (sh2v4dcd00_cp1 and ex1_sh_lv1(11) ) or (sh2v4dcd04_cp1 and ex1_sh_lv1(7) ) ); + lv2x_12: ex1_sh_lv2x_b(12) <= not( (sh2v4dcd00_cp1 and ex1_sh_lv1(12) ) or (sh2v4dcd04_cp1 and ex1_sh_lv1(8) ) ); + lv2x_13: ex1_sh_lv2x_b(13) <= not( (sh2v4dcd00_cp1 and ex1_sh_lv1(13) ) or (sh2v4dcd04_cp1 and ex1_sh_lv1(9) ) ); + lv2x_14: ex1_sh_lv2x_b(14) <= not( (sh2v4dcd00_cp1 and ex1_sh_lv1(14) ) or (sh2v4dcd04_cp1 and ex1_sh_lv1(10) ) ); + lv2x_15: ex1_sh_lv2x_b(15) <= not( (sh2v4dcd00_cp2 and ex1_sh_lv1(15) ) or (sh2v4dcd04_cp2 and ex1_sh_lv1(11) ) ); + lv2x_16: ex1_sh_lv2x_b(16) <= not( (sh2v4dcd00_cp2 and ex1_sh_lv1(16) ) or (sh2v4dcd04_cp2 and ex1_sh_lv1(12) ) ); + lv2x_17: ex1_sh_lv2x_b(17) <= not( (sh2v4dcd00_cp2 and ex1_sh_lv1(17) ) or (sh2v4dcd04_cp2 and ex1_sh_lv1(13) ) ); + lv2x_18: ex1_sh_lv2x_b(18) <= not( (sh2v4dcd00_cp2 and ex1_sh_lv1(18) ) or (sh2v4dcd04_cp2 and ex1_sh_lv1(14) ) ); + lv2x_19: ex1_sh_lv2x_b(19) <= not( (sh2v4dcd00_cp2 and ex1_sh_lv1(19) ) or (sh2v4dcd04_cp2 and ex1_sh_lv1(15) ) ); + lv2x_20: ex1_sh_lv2x_b(20) <= not( (sh2v4dcd00_cp2 and ex1_sh_lv1(20) ) or (sh2v4dcd04_cp2 and ex1_sh_lv1(16) ) ); + lv2x_21: ex1_sh_lv2x_b(21) <= not( (sh2v4dcd00_cp2 and ex1_sh_lv1(21) ) or (sh2v4dcd04_cp2 and ex1_sh_lv1(17) ) ); + lv2x_22: ex1_sh_lv2x_b(22) <= not( (sh2v4dcd00_cp2 and ex1_sh_lv1(22) ) or (sh2v4dcd04_cp2 and ex1_sh_lv1(18) ) ); + lv2x_23: ex1_sh_lv2x_b(23) <= not( (sh2v4dcd00_cp2 and ex1_sh_lv1(23) ) or (sh2v4dcd04_cp2 and ex1_sh_lv1(19) ) ); + lv2x_24: ex1_sh_lv2x_b(24) <= not( (sh2v4dcd00_cp2 and ex1_sh_lv1(24) ) or (sh2v4dcd04_cp2 and ex1_sh_lv1(20) ) ); + lv2x_25: ex1_sh_lv2x_b(25) <= not( (sh2v4dcd00_cp2 and ex1_sh_lv1(25) ) or (sh2v4dcd04_cp2 and ex1_sh_lv1(21) ) ); + lv2x_26: ex1_sh_lv2x_b(26) <= not( (sh2v4dcd00_cp2 and ex1_sh_lv1(26) ) or (sh2v4dcd04_cp2 and ex1_sh_lv1(22) ) ); + lv2x_27: ex1_sh_lv2x_b(27) <= not( (sh2v4dcd00_cp2 and ex1_sh_lv1(27) ) or (sh2v4dcd04_cp2 and ex1_sh_lv1(23) ) ); + lv2x_28: ex1_sh_lv2x_b(28) <= not( (sh2v4dcd00_cp2 and ex1_sh_lv1(28) ) or (sh2v4dcd04_cp2 and ex1_sh_lv1(24) ) ); + lv2x_29: ex1_sh_lv2x_b(29) <= not( (sh2v4dcd00_cp2 and ex1_sh_lv1(29) ) or (sh2v4dcd04_cp2 and ex1_sh_lv1(25) ) ); + lv2x_30: ex1_sh_lv2x_b(30) <= not( (sh2v4dcd00_cp3 and ex1_sh_lv1(30) ) or (sh2v4dcd04_cp3 and ex1_sh_lv1(26) ) ); + lv2x_31: ex1_sh_lv2x_b(31) <= not( (sh2v4dcd00_cp3 and ex1_sh_lv1(31) ) or (sh2v4dcd04_cp3 and ex1_sh_lv1(27) ) ); + lv2x_32: ex1_sh_lv2x_b(32) <= not( (sh2v4dcd00_cp3 and ex1_sh_lv1(32) ) or (sh2v4dcd04_cp3 and ex1_sh_lv1(28) ) ); + lv2x_33: ex1_sh_lv2x_b(33) <= not( (sh2v4dcd00_cp3 and ex1_sh_lv1(33) ) or (sh2v4dcd04_cp3 and ex1_sh_lv1(29) ) ); + lv2x_34: ex1_sh_lv2x_b(34) <= not( (sh2v4dcd00_cp3 and ex1_sh_lv1(34) ) or (sh2v4dcd04_cp3 and ex1_sh_lv1(30) ) ); + lv2x_35: ex1_sh_lv2x_b(35) <= not( (sh2v4dcd00_cp3 and ex1_sh_lv1(35) ) or (sh2v4dcd04_cp3 and ex1_sh_lv1(31) ) ); + lv2x_36: ex1_sh_lv2x_b(36) <= not( (sh2v4dcd00_cp3 and ex1_sh_lv1(36) ) or (sh2v4dcd04_cp3 and ex1_sh_lv1(32) ) ); + lv2x_37: ex1_sh_lv2x_b(37) <= not( (sh2v4dcd00_cp3 and ex1_sh_lv1(37) ) or (sh2v4dcd04_cp3 and ex1_sh_lv1(33) ) ); + lv2x_38: ex1_sh_lv2x_b(38) <= not( (sh2v4dcd00_cp3 and ex1_sh_lv1(38) ) or (sh2v4dcd04_cp3 and ex1_sh_lv1(34) ) ); + lv2x_39: ex1_sh_lv2x_b(39) <= not( (sh2v4dcd00_cp3 and ex1_sh_lv1(39) ) or (sh2v4dcd04_cp3 and ex1_sh_lv1(35) ) ); + lv2x_40: ex1_sh_lv2x_b(40) <= not( (sh2v4dcd00_cp3 and ex1_sh_lv1(40) ) or (sh2v4dcd04_cp3 and ex1_sh_lv1(36) ) ); + lv2x_41: ex1_sh_lv2x_b(41) <= not( (sh2v4dcd00_cp3 and ex1_sh_lv1(41) ) or (sh2v4dcd04_cp3 and ex1_sh_lv1(37) ) ); + lv2x_42: ex1_sh_lv2x_b(42) <= not( (sh2v4dcd00_cp3 and ex1_sh_lv1(42) ) or (sh2v4dcd04_cp3 and ex1_sh_lv1(38) ) ); + lv2x_43: ex1_sh_lv2x_b(43) <= not( (sh2v4dcd00_cp3 and ex1_sh_lv1(43) ) or (sh2v4dcd04_cp3 and ex1_sh_lv1(39) ) ); + lv2x_44: ex1_sh_lv2x_b(44) <= not( (sh2v4dcd00_cp3 and ex1_sh_lv1(44) ) or (sh2v4dcd04_cp3 and ex1_sh_lv1(40) ) ); + lv2x_45: ex1_sh_lv2x_b(45) <= not( (sh2v4dcd00_cp4 and ex1_sh_lv1(45) ) or (sh2v4dcd04_cp4 and ex1_sh_lv1(41) ) ); + lv2x_46: ex1_sh_lv2x_b(46) <= not( (sh2v4dcd00_cp4 and ex1_sh_lv1(46) ) or (sh2v4dcd04_cp4 and ex1_sh_lv1(42) ) ); + lv2x_47: ex1_sh_lv2x_b(47) <= not( (sh2v4dcd00_cp4 and ex1_sh_lv1(47) ) or (sh2v4dcd04_cp4 and ex1_sh_lv1(43) ) ); + lv2x_48: ex1_sh_lv2x_b(48) <= not( (sh2v4dcd00_cp4 and ex1_sh_lv1(48) ) or (sh2v4dcd04_cp4 and ex1_sh_lv1(44) ) ); + lv2x_49: ex1_sh_lv2x_b(49) <= not( (sh2v4dcd00_cp4 and ex1_sh_lv1(49) ) or (sh2v4dcd04_cp4 and ex1_sh_lv1(45) ) ); + lv2x_50: ex1_sh_lv2x_b(50) <= not( (sh2v4dcd00_cp4 and ex1_sh_lv1(50) ) or (sh2v4dcd04_cp4 and ex1_sh_lv1(46) ) ); + lv2x_51: ex1_sh_lv2x_b(51) <= not( (sh2v4dcd00_cp4 and ex1_sh_lv1(51) ) or (sh2v4dcd04_cp4 and ex1_sh_lv1(47) ) ); + lv2x_52: ex1_sh_lv2x_b(52) <= not( (sh2v4dcd00_cp4 and ex1_sh_lv1(52) ) or (sh2v4dcd04_cp4 and ex1_sh_lv1(48) ) ); + lv2x_53: ex1_sh_lv2x_b(53) <= not( (sh2v4dcd00_cp4 and ex1_sh_lv1(53) ) or (sh2v4dcd04_cp4 and ex1_sh_lv1(49) ) ); + lv2x_54: ex1_sh_lv2x_b(54) <= not( (sh2v4dcd00_cp4 and ex1_sh_lv1(54) ) or (sh2v4dcd04_cp4 and ex1_sh_lv1(50) ) ); + lv2x_55: ex1_sh_lv2x_b(55) <= not( (sh2v4dcd00_cp4 and ex1_sh_lv1(55) ) or (sh2v4dcd04_cp4 and ex1_sh_lv1(51) ) ); + lv2x_56: ex1_sh_lv2x_b(56) <= not( sh2v4dcd04_cp4 and ex1_sh_lv1(52) ); + lv2x_57: ex1_sh_lv2x_b(57) <= not( sh2v4dcd04_cp4 and ex1_sh_lv1(53) ); + lv2x_58: ex1_sh_lv2x_b(58) <= not( sh2v4dcd04_cp4 and ex1_sh_lv1(54) ); + lv2x_59: ex1_sh_lv2x_b(59) <= not( sh2v4dcd04_cp4 and ex1_sh_lv1(55) ); + + + + lv2y_08: ex1_sh_lv2y_b(8) <= not( sh2v4dcd08_cp1 and ex1_sh_lv1(0) ); + lv2y_09: ex1_sh_lv2y_b(9) <= not( sh2v4dcd08_cp1 and ex1_sh_lv1(1) ); + lv2y_10: ex1_sh_lv2y_b(10) <= not( sh2v4dcd08_cp1 and ex1_sh_lv1(2) ); + lv2y_11: ex1_sh_lv2y_b(11) <= not( sh2v4dcd08_cp1 and ex1_sh_lv1(3) ); + lv2y_12: ex1_sh_lv2y_b(12) <= not( (sh2v4dcd08_cp1 and ex1_sh_lv1(4) ) or (sh2v4dcd12_cp1 and ex1_sh_lv1(0) ) ); + lv2y_13: ex1_sh_lv2y_b(13) <= not( (sh2v4dcd08_cp1 and ex1_sh_lv1(5) ) or (sh2v4dcd12_cp1 and ex1_sh_lv1(1) ) ); + lv2y_14: ex1_sh_lv2y_b(14) <= not( (sh2v4dcd08_cp1 and ex1_sh_lv1(6) ) or (sh2v4dcd12_cp1 and ex1_sh_lv1(2) ) ); + lv2y_15: ex1_sh_lv2y_b(15) <= not( (sh2v4dcd08_cp1 and ex1_sh_lv1(7) ) or (sh2v4dcd12_cp1 and ex1_sh_lv1(3) ) ); + lv2y_16: ex1_sh_lv2y_b(16) <= not( (sh2v4dcd08_cp1 and ex1_sh_lv1(8) ) or (sh2v4dcd12_cp1 and ex1_sh_lv1(4) ) ); + lv2y_17: ex1_sh_lv2y_b(17) <= not( (sh2v4dcd08_cp1 and ex1_sh_lv1(9) ) or (sh2v4dcd12_cp1 and ex1_sh_lv1(5) ) ); + lv2y_18: ex1_sh_lv2y_b(18) <= not( (sh2v4dcd08_cp1 and ex1_sh_lv1(10) ) or (sh2v4dcd12_cp1 and ex1_sh_lv1(6) ) ); + lv2y_19: ex1_sh_lv2y_b(19) <= not( (sh2v4dcd08_cp1 and ex1_sh_lv1(11) ) or (sh2v4dcd12_cp1 and ex1_sh_lv1(7) ) ); + lv2y_20: ex1_sh_lv2y_b(20) <= not( (sh2v4dcd08_cp1 and ex1_sh_lv1(12) ) or (sh2v4dcd12_cp1 and ex1_sh_lv1(8) ) ); + lv2y_21: ex1_sh_lv2y_b(21) <= not( (sh2v4dcd08_cp1 and ex1_sh_lv1(13) ) or (sh2v4dcd12_cp1 and ex1_sh_lv1(9) ) ); + lv2y_22: ex1_sh_lv2y_b(22) <= not( (sh2v4dcd08_cp2 and ex1_sh_lv1(14) ) or (sh2v4dcd12_cp2 and ex1_sh_lv1(10) ) ); + lv2y_23: ex1_sh_lv2y_b(23) <= not( (sh2v4dcd08_cp2 and ex1_sh_lv1(15) ) or (sh2v4dcd12_cp2 and ex1_sh_lv1(11) ) ); + lv2y_24: ex1_sh_lv2y_b(24) <= not( (sh2v4dcd08_cp2 and ex1_sh_lv1(16) ) or (sh2v4dcd12_cp2 and ex1_sh_lv1(12) ) ); + lv2y_25: ex1_sh_lv2y_b(25) <= not( (sh2v4dcd08_cp2 and ex1_sh_lv1(17) ) or (sh2v4dcd12_cp2 and ex1_sh_lv1(13) ) ); + lv2y_26: ex1_sh_lv2y_b(26) <= not( (sh2v4dcd08_cp2 and ex1_sh_lv1(18) ) or (sh2v4dcd12_cp2 and ex1_sh_lv1(14) ) ); + lv2y_27: ex1_sh_lv2y_b(27) <= not( (sh2v4dcd08_cp2 and ex1_sh_lv1(19) ) or (sh2v4dcd12_cp2 and ex1_sh_lv1(15) ) ); + lv2y_28: ex1_sh_lv2y_b(28) <= not( (sh2v4dcd08_cp2 and ex1_sh_lv1(20) ) or (sh2v4dcd12_cp2 and ex1_sh_lv1(16) ) ); + lv2y_29: ex1_sh_lv2y_b(29) <= not( (sh2v4dcd08_cp2 and ex1_sh_lv1(21) ) or (sh2v4dcd12_cp2 and ex1_sh_lv1(17) ) ); + lv2y_30: ex1_sh_lv2y_b(30) <= not( (sh2v4dcd08_cp2 and ex1_sh_lv1(22) ) or (sh2v4dcd12_cp2 and ex1_sh_lv1(18) ) ); + lv2y_31: ex1_sh_lv2y_b(31) <= not( (sh2v4dcd08_cp2 and ex1_sh_lv1(23) ) or (sh2v4dcd12_cp2 and ex1_sh_lv1(19) ) ); + lv2y_32: ex1_sh_lv2y_b(32) <= not( (sh2v4dcd08_cp2 and ex1_sh_lv1(24) ) or (sh2v4dcd12_cp2 and ex1_sh_lv1(20) ) ); + lv2y_33: ex1_sh_lv2y_b(33) <= not( (sh2v4dcd08_cp2 and ex1_sh_lv1(25) ) or (sh2v4dcd12_cp2 and ex1_sh_lv1(21) ) ); + lv2y_34: ex1_sh_lv2y_b(34) <= not( (sh2v4dcd08_cp2 and ex1_sh_lv1(26) ) or (sh2v4dcd12_cp2 and ex1_sh_lv1(22) ) ); + lv2y_35: ex1_sh_lv2y_b(35) <= not( (sh2v4dcd08_cp2 and ex1_sh_lv1(27) ) or (sh2v4dcd12_cp2 and ex1_sh_lv1(23) ) ); + lv2y_36: ex1_sh_lv2y_b(36) <= not( (sh2v4dcd08_cp2 and ex1_sh_lv1(28) ) or (sh2v4dcd12_cp2 and ex1_sh_lv1(24) ) ); + lv2y_37: ex1_sh_lv2y_b(37) <= not( (sh2v4dcd08_cp3 and ex1_sh_lv1(29) ) or (sh2v4dcd12_cp3 and ex1_sh_lv1(25) ) ); + lv2y_38: ex1_sh_lv2y_b(38) <= not( (sh2v4dcd08_cp3 and ex1_sh_lv1(30) ) or (sh2v4dcd12_cp3 and ex1_sh_lv1(26) ) ); + lv2y_39: ex1_sh_lv2y_b(39) <= not( (sh2v4dcd08_cp3 and ex1_sh_lv1(31) ) or (sh2v4dcd12_cp3 and ex1_sh_lv1(27) ) ); + lv2y_40: ex1_sh_lv2y_b(40) <= not( (sh2v4dcd08_cp3 and ex1_sh_lv1(32) ) or (sh2v4dcd12_cp3 and ex1_sh_lv1(28) ) ); + lv2y_41: ex1_sh_lv2y_b(41) <= not( (sh2v4dcd08_cp3 and ex1_sh_lv1(33) ) or (sh2v4dcd12_cp3 and ex1_sh_lv1(29) ) ); + lv2y_42: ex1_sh_lv2y_b(42) <= not( (sh2v4dcd08_cp3 and ex1_sh_lv1(34) ) or (sh2v4dcd12_cp3 and ex1_sh_lv1(30) ) ); + lv2y_43: ex1_sh_lv2y_b(43) <= not( (sh2v4dcd08_cp3 and ex1_sh_lv1(35) ) or (sh2v4dcd12_cp3 and ex1_sh_lv1(31) ) ); + lv2y_44: ex1_sh_lv2y_b(44) <= not( (sh2v4dcd08_cp3 and ex1_sh_lv1(36) ) or (sh2v4dcd12_cp3 and ex1_sh_lv1(32) ) ); + lv2y_45: ex1_sh_lv2y_b(45) <= not( (sh2v4dcd08_cp3 and ex1_sh_lv1(37) ) or (sh2v4dcd12_cp3 and ex1_sh_lv1(33) ) ); + lv2y_46: ex1_sh_lv2y_b(46) <= not( (sh2v4dcd08_cp3 and ex1_sh_lv1(38) ) or (sh2v4dcd12_cp3 and ex1_sh_lv1(34) ) ); + lv2y_47: ex1_sh_lv2y_b(47) <= not( (sh2v4dcd08_cp3 and ex1_sh_lv1(39) ) or (sh2v4dcd12_cp3 and ex1_sh_lv1(35) ) ); + lv2y_48: ex1_sh_lv2y_b(48) <= not( (sh2v4dcd08_cp3 and ex1_sh_lv1(40) ) or (sh2v4dcd12_cp3 and ex1_sh_lv1(36) ) ); + lv2y_49: ex1_sh_lv2y_b(49) <= not( (sh2v4dcd08_cp3 and ex1_sh_lv1(41) ) or (sh2v4dcd12_cp3 and ex1_sh_lv1(37) ) ); + lv2y_50: ex1_sh_lv2y_b(50) <= not( (sh2v4dcd08_cp3 and ex1_sh_lv1(42) ) or (sh2v4dcd12_cp3 and ex1_sh_lv1(38) ) ); + lv2y_51: ex1_sh_lv2y_b(51) <= not( (sh2v4dcd08_cp3 and ex1_sh_lv1(43) ) or (sh2v4dcd12_cp3 and ex1_sh_lv1(39) ) ); + lv2y_52: ex1_sh_lv2y_b(52) <= not( (sh2v4dcd08_cp4 and ex1_sh_lv1(44) ) or (sh2v4dcd12_cp4 and ex1_sh_lv1(40) ) ); + lv2y_53: ex1_sh_lv2y_b(53) <= not( (sh2v4dcd08_cp4 and ex1_sh_lv1(45) ) or (sh2v4dcd12_cp4 and ex1_sh_lv1(41) ) ); + lv2y_54: ex1_sh_lv2y_b(54) <= not( (sh2v4dcd08_cp4 and ex1_sh_lv1(46) ) or (sh2v4dcd12_cp4 and ex1_sh_lv1(42) ) ); + lv2y_55: ex1_sh_lv2y_b(55) <= not( (sh2v4dcd08_cp4 and ex1_sh_lv1(47) ) or (sh2v4dcd12_cp4 and ex1_sh_lv1(43) ) ); + lv2y_56: ex1_sh_lv2y_b(56) <= not( (sh2v4dcd08_cp4 and ex1_sh_lv1(48) ) or (sh2v4dcd12_cp4 and ex1_sh_lv1(44) ) ); + lv2y_57: ex1_sh_lv2y_b(57) <= not( (sh2v4dcd08_cp4 and ex1_sh_lv1(49) ) or (sh2v4dcd12_cp4 and ex1_sh_lv1(45) ) ); + lv2y_58: ex1_sh_lv2y_b(58) <= not( (sh2v4dcd08_cp4 and ex1_sh_lv1(50) ) or (sh2v4dcd12_cp4 and ex1_sh_lv1(46) ) ); + lv2y_59: ex1_sh_lv2y_b(59) <= not( (sh2v4dcd08_cp4 and ex1_sh_lv1(51) ) or (sh2v4dcd12_cp4 and ex1_sh_lv1(47) ) ); + lv2y_60: ex1_sh_lv2y_b(60) <= not( (sh2v4dcd08_cp4 and ex1_sh_lv1(52) ) or (sh2v4dcd12_cp4 and ex1_sh_lv1(48) ) ); + lv2y_61: ex1_sh_lv2y_b(61) <= not( (sh2v4dcd08_cp4 and ex1_sh_lv1(53) ) or (sh2v4dcd12_cp4 and ex1_sh_lv1(49) ) ); + lv2y_62: ex1_sh_lv2y_b(62) <= not( (sh2v4dcd08_cp4 and ex1_sh_lv1(54) ) or (sh2v4dcd12_cp4 and ex1_sh_lv1(50) ) ); + lv2y_63: ex1_sh_lv2y_b(63) <= not( (sh2v4dcd08_cp4 and ex1_sh_lv1(55) ) or (sh2v4dcd12_cp4 and ex1_sh_lv1(51) ) ); + lv2y_64: ex1_sh_lv2y_b(64) <= not( sh2v4dcd12_cp4 and ex1_sh_lv1(52) ); + lv2y_65: ex1_sh_lv2y_b(65) <= not( sh2v4dcd12_cp4 and ex1_sh_lv1(53) ); + lv2y_66: ex1_sh_lv2y_b(66) <= not( sh2v4dcd12_cp4 and ex1_sh_lv1(54) ); + lv2y_67: ex1_sh_lv2y_b(67) <= not( sh2v4dcd12_cp4 and ex1_sh_lv1(55) ); + + + lv2z_00: ex1_sh_lv2z_b( 0) <= not( sh2v4dcdpp_cp1 and ex1_special_fcfid( 0) ); + lv2z_01: ex1_sh_lv2z_b( 1) <= not( sh2v4dcdpp_cp1 and ex1_special_fcfid( 1) ); + lv2z_02: ex1_sh_lv2z_b( 2) <= not( sh2v4dcdpp_cp1 and ex1_special_fcfid( 2) ); + lv2z_03: ex1_sh_lv2z_b( 3) <= not( sh2v4dcdpp_cp1 and ex1_special_fcfid( 3) ); + lv2z_04: ex1_sh_lv2z_b( 4) <= not( sh2v4dcdpp_cp1 and ex1_special_fcfid( 4) ); + lv2z_05: ex1_sh_lv2z_b( 5) <= not( sh2v4dcdpp_cp1 and ex1_special_fcfid( 5) ); + lv2z_06: ex1_sh_lv2z_b( 6) <= not( sh2v4dcdpp_cp1 and ex1_special_fcfid( 6) ); + lv2z_07: ex1_sh_lv2z_b( 7) <= not( sh2v4dcdpp_cp1 and ex1_special_fcfid( 7) ); + lv2z_08: ex1_sh_lv2z_b( 8) <= not( sh2v4dcdpp_cp1 and ex1_special_fcfid( 8) ); + lv2z_09: ex1_sh_lv2z_b( 9) <= not( sh2v4dcdpp_cp1 and ex1_special_fcfid( 9) ); + lv2z_10: ex1_sh_lv2z_b(10) <= not( sh2v4dcdpp_cp1 and ex1_special_fcfid(10) ); + lv2z_11: ex1_sh_lv2z_b(11) <= not( sh2v4dcdpp_cp1 and ex1_special_fcfid(11) ); + lv2z_12: ex1_sh_lv2z_b(12) <= not( sh2v4dcdpp_cp1 and ex1_special_fcfid(12) ); + lv2z_13: ex1_sh_lv2z_b(13) <= not( sh2v4dcdpp_cp1 and ex1_special_fcfid(13) ); + lv2z_14: ex1_sh_lv2z_b(14) <= not( sh2v4dcdpp_cp1 and ex1_special_fcfid(14) ); + lv2z_15: ex1_sh_lv2z_b(15) <= not( sh2v4dcdpp_cp1 and ex1_special_fcfid(15) ); + lv2z_16: ex1_sh_lv2z_b(16) <= not( sh2v4dcdpp_cp2 and ex1_special_fcfid(16) ); + lv2z_17: ex1_sh_lv2z_b(17) <= not( sh2v4dcdpp_cp2 and ex1_special_fcfid(17) ); + lv2z_18: ex1_sh_lv2z_b(18) <= not( sh2v4dcdpp_cp2 and ex1_special_fcfid(18) ); + lv2z_19: ex1_sh_lv2z_b(19) <= not( sh2v4dcdpp_cp2 and ex1_special_fcfid(19) ); + lv2z_20: ex1_sh_lv2z_b(20) <= not( sh2v4dcdpp_cp2 and ex1_special_fcfid(20) ); + lv2z_21: ex1_sh_lv2z_b(21) <= not( sh2v4dcdpp_cp2 and ex1_special_fcfid(21) ); + lv2z_22: ex1_sh_lv2z_b(22) <= not( sh2v4dcdpp_cp2 and ex1_special_fcfid(22) ); + lv2z_23: ex1_sh_lv2z_b(23) <= not( sh2v4dcdpp_cp2 and ex1_special_fcfid(23) ); + lv2z_24: ex1_sh_lv2z_b(24) <= not( sh2v4dcdpp_cp2 and ex1_special_fcfid(24) ); + lv2z_25: ex1_sh_lv2z_b(25) <= not( sh2v4dcdpp_cp2 and ex1_special_fcfid(25) ); + lv2z_26: ex1_sh_lv2z_b(26) <= not( sh2v4dcdpp_cp2 and ex1_special_fcfid(26) ); + lv2z_27: ex1_sh_lv2z_b(27) <= not( sh2v4dcdpp_cp2 and ex1_special_fcfid(27) ); + lv2z_28: ex1_sh_lv2z_b(28) <= not( sh2v4dcdpp_cp2 and ex1_special_fcfid(28) ); + lv2z_29: ex1_sh_lv2z_b(29) <= not( sh2v4dcdpp_cp2 and ex1_special_fcfid(29) ); + lv2z_30: ex1_sh_lv2z_b(30) <= not( sh2v4dcdpp_cp2 and ex1_special_fcfid(30) ); + lv2z_31: ex1_sh_lv2z_b(31) <= not( sh2v4dcdpp_cp2 and ex1_special_fcfid(31) ); + lv2z_32: ex1_sh_lv2z_b(32) <= not( sh2v4dcdpp_cp3 and ex1_special_fcfid(32) ); + lv2z_33: ex1_sh_lv2z_b(33) <= not( sh2v4dcdpp_cp3 and ex1_special_fcfid(33) ); + lv2z_34: ex1_sh_lv2z_b(34) <= not( sh2v4dcdpp_cp3 and ex1_special_fcfid(34) ); + lv2z_35: ex1_sh_lv2z_b(35) <= not( sh2v4dcdpp_cp3 and ex1_special_fcfid(35) ); + lv2z_36: ex1_sh_lv2z_b(36) <= not( sh2v4dcdpp_cp3 and ex1_special_fcfid(36) ); + lv2z_37: ex1_sh_lv2z_b(37) <= not( sh2v4dcdpp_cp3 and ex1_special_fcfid(37) ); + lv2z_38: ex1_sh_lv2z_b(38) <= not( sh2v4dcdpp_cp3 and ex1_special_fcfid(38) ); + lv2z_39: ex1_sh_lv2z_b(39) <= not( sh2v4dcdpp_cp3 and ex1_special_fcfid(39) ); + lv2z_40: ex1_sh_lv2z_b(40) <= not( sh2v4dcdpp_cp3 and ex1_special_fcfid(40) ); + lv2z_41: ex1_sh_lv2z_b(41) <= not( sh2v4dcdpp_cp3 and ex1_special_fcfid(41) ); + lv2z_42: ex1_sh_lv2z_b(42) <= not( sh2v4dcdpp_cp3 and ex1_special_fcfid(42) ); + lv2z_43: ex1_sh_lv2z_b(43) <= not( sh2v4dcdpp_cp3 and ex1_special_fcfid(43) ); + lv2z_44: ex1_sh_lv2z_b(44) <= not( sh2v4dcdpp_cp3 and ex1_special_fcfid(44) ); + lv2z_45: ex1_sh_lv2z_b(45) <= not( sh2v4dcdpp_cp3 and ex1_special_fcfid(45) ); + lv2z_46: ex1_sh_lv2z_b(46) <= not( sh2v4dcdpp_cp3 and ex1_special_fcfid(46) ); + lv2z_47: ex1_sh_lv2z_b(47) <= not( sh2v4dcdpp_cp3 and ex1_special_fcfid(47) ); + lv2z_48: ex1_sh_lv2z_b(48) <= not( sh2v4dcdpp_cp4 and ex1_special_fcfid(48) ); + lv2z_49: ex1_sh_lv2z_b(49) <= not( sh2v4dcdpp_cp4 and ex1_special_fcfid(49) ); + lv2z_50: ex1_sh_lv2z_b(50) <= not( sh2v4dcdpp_cp4 and ex1_special_fcfid(50) ); + lv2z_51: ex1_sh_lv2z_b(51) <= not( sh2v4dcdpp_cp4 and ex1_special_fcfid(51) ); + lv2z_52: ex1_sh_lv2z_b(52) <= not( sh2v4dcdpp_cp4 and ex1_special_fcfid(52) ); + lv2z_53: ex1_sh_lv2z_b(53) <= not( sh2v4dcdpp_cp4 and ex1_special_fcfid(53) ); + lv2z_54: ex1_sh_lv2z_b(54) <= not( sh2v4dcdpp_cp4 and ex1_special_fcfid(54) ); + lv2z_55: ex1_sh_lv2z_b(55) <= not( sh2v4dcdpp_cp4 and ex1_special_fcfid(55) ); + lv2z_56: ex1_sh_lv2z_b(56) <= not( sh2v4dcdpp_cp4 and ex1_special_fcfid(56) ); + lv2z_57: ex1_sh_lv2z_b(57) <= not( sh2v4dcdpp_cp4 and ex1_special_fcfid(57) ); + lv2z_58: ex1_sh_lv2z_b(58) <= not( sh2v4dcdpp_cp4 and ex1_special_fcfid(58) ); + lv2z_59: ex1_sh_lv2z_b(59) <= not( sh2v4dcdpp_cp4 and ex1_special_fcfid(59) ); + lv2z_60: ex1_sh_lv2z_b(60) <= not( sh2v4dcdpp_cp4 and ex1_special_fcfid(60) ); + lv2z_61: ex1_sh_lv2z_b(61) <= not( sh2v4dcdpp_cp4 and ex1_special_fcfid(61) ); + lv2z_62: ex1_sh_lv2z_b(62) <= not( sh2v4dcdpp_cp4 and ex1_special_fcfid(62) ); + lv2z_63: ex1_sh_lv2z_b(63) <= not( sh2v4dcdpp_cp4 and ex1_special_fcfid(63) ); + + + + lv2_00: ex1_sh_lvl2(00) <= not( ex1_sh_lv2x_b(00) and ex1_sh_lv2z_b(00) ) ; + lv2_01: ex1_sh_lvl2(01) <= not( ex1_sh_lv2x_b(01) and ex1_sh_lv2z_b(01) ) ; + lv2_02: ex1_sh_lvl2(02) <= not( ex1_sh_lv2x_b(02) and ex1_sh_lv2z_b(02) ) ; + lv2_03: ex1_sh_lvl2(03) <= not( ex1_sh_lv2x_b(03) and ex1_sh_lv2z_b(03) ) ; + lv2_04: ex1_sh_lvl2(04) <= not( ex1_sh_lv2x_b(04) and ex1_sh_lv2z_b(04) ) ; + lv2_05: ex1_sh_lvl2(05) <= not( ex1_sh_lv2x_b(05) and ex1_sh_lv2z_b(05) ) ; + lv2_06: ex1_sh_lvl2(06) <= not( ex1_sh_lv2x_b(06) and ex1_sh_lv2z_b(06) ) ; + lv2_07: ex1_sh_lvl2(07) <= not( ex1_sh_lv2x_b(07) and ex1_sh_lv2z_b(07) ) ; + lv2_08: ex1_sh_lvl2(08) <= not( ex1_sh_lv2x_b(08) and ex1_sh_lv2y_b(08) and ex1_sh_lv2z_b(08) ) ; + lv2_09: ex1_sh_lvl2(09) <= not( ex1_sh_lv2x_b(09) and ex1_sh_lv2y_b(09) and ex1_sh_lv2z_b(09) ) ; + lv2_10: ex1_sh_lvl2(10) <= not( ex1_sh_lv2x_b(10) and ex1_sh_lv2y_b(10) and ex1_sh_lv2z_b(10) ) ; + lv2_11: ex1_sh_lvl2(11) <= not( ex1_sh_lv2x_b(11) and ex1_sh_lv2y_b(11) and ex1_sh_lv2z_b(11) ) ; + lv2_12: ex1_sh_lvl2(12) <= not( ex1_sh_lv2x_b(12) and ex1_sh_lv2y_b(12) and ex1_sh_lv2z_b(12) ) ; + lv2_13: ex1_sh_lvl2(13) <= not( ex1_sh_lv2x_b(13) and ex1_sh_lv2y_b(13) and ex1_sh_lv2z_b(13) ) ; + lv2_14: ex1_sh_lvl2(14) <= not( ex1_sh_lv2x_b(14) and ex1_sh_lv2y_b(14) and ex1_sh_lv2z_b(14) ) ; + lv2_15: ex1_sh_lvl2(15) <= not( ex1_sh_lv2x_b(15) and ex1_sh_lv2y_b(15) and ex1_sh_lv2z_b(15) ) ; + lv2_16: ex1_sh_lvl2(16) <= not( ex1_sh_lv2x_b(16) and ex1_sh_lv2y_b(16) and ex1_sh_lv2z_b(16) ) ; + lv2_17: ex1_sh_lvl2(17) <= not( ex1_sh_lv2x_b(17) and ex1_sh_lv2y_b(17) and ex1_sh_lv2z_b(17) ) ; + lv2_18: ex1_sh_lvl2(18) <= not( ex1_sh_lv2x_b(18) and ex1_sh_lv2y_b(18) and ex1_sh_lv2z_b(18) ) ; + lv2_19: ex1_sh_lvl2(19) <= not( ex1_sh_lv2x_b(19) and ex1_sh_lv2y_b(19) and ex1_sh_lv2z_b(19) ) ; + lv2_20: ex1_sh_lvl2(20) <= not( ex1_sh_lv2x_b(20) and ex1_sh_lv2y_b(20) and ex1_sh_lv2z_b(20) ) ; + lv2_21: ex1_sh_lvl2(21) <= not( ex1_sh_lv2x_b(21) and ex1_sh_lv2y_b(21) and ex1_sh_lv2z_b(21) ) ; + lv2_22: ex1_sh_lvl2(22) <= not( ex1_sh_lv2x_b(22) and ex1_sh_lv2y_b(22) and ex1_sh_lv2z_b(22) ) ; + lv2_23: ex1_sh_lvl2(23) <= not( ex1_sh_lv2x_b(23) and ex1_sh_lv2y_b(23) and ex1_sh_lv2z_b(23) ) ; + lv2_24: ex1_sh_lvl2(24) <= not( ex1_sh_lv2x_b(24) and ex1_sh_lv2y_b(24) and ex1_sh_lv2z_b(24) ) ; + lv2_25: ex1_sh_lvl2(25) <= not( ex1_sh_lv2x_b(25) and ex1_sh_lv2y_b(25) and ex1_sh_lv2z_b(25) ) ; + lv2_26: ex1_sh_lvl2(26) <= not( ex1_sh_lv2x_b(26) and ex1_sh_lv2y_b(26) and ex1_sh_lv2z_b(26) ) ; + lv2_27: ex1_sh_lvl2(27) <= not( ex1_sh_lv2x_b(27) and ex1_sh_lv2y_b(27) and ex1_sh_lv2z_b(27) ) ; + lv2_28: ex1_sh_lvl2(28) <= not( ex1_sh_lv2x_b(28) and ex1_sh_lv2y_b(28) and ex1_sh_lv2z_b(28) ) ; + lv2_29: ex1_sh_lvl2(29) <= not( ex1_sh_lv2x_b(29) and ex1_sh_lv2y_b(29) and ex1_sh_lv2z_b(29) ) ; + lv2_30: ex1_sh_lvl2(30) <= not( ex1_sh_lv2x_b(30) and ex1_sh_lv2y_b(30) and ex1_sh_lv2z_b(30) ) ; + lv2_31: ex1_sh_lvl2(31) <= not( ex1_sh_lv2x_b(31) and ex1_sh_lv2y_b(31) and ex1_sh_lv2z_b(31) ) ; + lv2_32: ex1_sh_lvl2(32) <= not( ex1_sh_lv2x_b(32) and ex1_sh_lv2y_b(32) and ex1_sh_lv2z_b(32) ) ; + lv2_33: ex1_sh_lvl2(33) <= not( ex1_sh_lv2x_b(33) and ex1_sh_lv2y_b(33) and ex1_sh_lv2z_b(33) ) ; + lv2_34: ex1_sh_lvl2(34) <= not( ex1_sh_lv2x_b(34) and ex1_sh_lv2y_b(34) and ex1_sh_lv2z_b(34) ) ; + lv2_35: ex1_sh_lvl2(35) <= not( ex1_sh_lv2x_b(35) and ex1_sh_lv2y_b(35) and ex1_sh_lv2z_b(35) ) ; + lv2_36: ex1_sh_lvl2(36) <= not( ex1_sh_lv2x_b(36) and ex1_sh_lv2y_b(36) and ex1_sh_lv2z_b(36) ) ; + lv2_37: ex1_sh_lvl2(37) <= not( ex1_sh_lv2x_b(37) and ex1_sh_lv2y_b(37) and ex1_sh_lv2z_b(37) ) ; + lv2_38: ex1_sh_lvl2(38) <= not( ex1_sh_lv2x_b(38) and ex1_sh_lv2y_b(38) and ex1_sh_lv2z_b(38) ) ; + lv2_39: ex1_sh_lvl2(39) <= not( ex1_sh_lv2x_b(39) and ex1_sh_lv2y_b(39) and ex1_sh_lv2z_b(39) ) ; + lv2_40: ex1_sh_lvl2(40) <= not( ex1_sh_lv2x_b(40) and ex1_sh_lv2y_b(40) and ex1_sh_lv2z_b(40) ) ; + lv2_41: ex1_sh_lvl2(41) <= not( ex1_sh_lv2x_b(41) and ex1_sh_lv2y_b(41) and ex1_sh_lv2z_b(41) ) ; + lv2_42: ex1_sh_lvl2(42) <= not( ex1_sh_lv2x_b(42) and ex1_sh_lv2y_b(42) and ex1_sh_lv2z_b(42) ) ; + lv2_43: ex1_sh_lvl2(43) <= not( ex1_sh_lv2x_b(43) and ex1_sh_lv2y_b(43) and ex1_sh_lv2z_b(43) ) ; + lv2_44: ex1_sh_lvl2(44) <= not( ex1_sh_lv2x_b(44) and ex1_sh_lv2y_b(44) and ex1_sh_lv2z_b(44) ) ; + lv2_45: ex1_sh_lvl2(45) <= not( ex1_sh_lv2x_b(45) and ex1_sh_lv2y_b(45) and ex1_sh_lv2z_b(45) ) ; + lv2_46: ex1_sh_lvl2(46) <= not( ex1_sh_lv2x_b(46) and ex1_sh_lv2y_b(46) and ex1_sh_lv2z_b(46) ) ; + lv2_47: ex1_sh_lvl2(47) <= not( ex1_sh_lv2x_b(47) and ex1_sh_lv2y_b(47) and ex1_sh_lv2z_b(47) ) ; + lv2_48: ex1_sh_lvl2(48) <= not( ex1_sh_lv2x_b(48) and ex1_sh_lv2y_b(48) and ex1_sh_lv2z_b(48) ) ; + lv2_49: ex1_sh_lvl2(49) <= not( ex1_sh_lv2x_b(49) and ex1_sh_lv2y_b(49) and ex1_sh_lv2z_b(49) ) ; + lv2_50: ex1_sh_lvl2(50) <= not( ex1_sh_lv2x_b(50) and ex1_sh_lv2y_b(50) and ex1_sh_lv2z_b(50) ) ; + lv2_51: ex1_sh_lvl2(51) <= not( ex1_sh_lv2x_b(51) and ex1_sh_lv2y_b(51) and ex1_sh_lv2z_b(51) ) ; + lv2_52: ex1_sh_lvl2(52) <= not( ex1_sh_lv2x_b(52) and ex1_sh_lv2y_b(52) and ex1_sh_lv2z_b(52) ) ; + lv2_53: ex1_sh_lvl2(53) <= not( ex1_sh_lv2x_b(53) and ex1_sh_lv2y_b(53) and ex1_sh_lv2z_b(53) ) ; + lv2_54: ex1_sh_lvl2(54) <= not( ex1_sh_lv2x_b(54) and ex1_sh_lv2y_b(54) and ex1_sh_lv2z_b(54) ) ; + lv2_55: ex1_sh_lvl2(55) <= not( ex1_sh_lv2x_b(55) and ex1_sh_lv2y_b(55) and ex1_sh_lv2z_b(55) ) ; + lv2_56: ex1_sh_lvl2(56) <= not( ex1_sh_lv2x_b(56) and ex1_sh_lv2y_b(56) and ex1_sh_lv2z_b(56) ) ; + lv2_57: ex1_sh_lvl2(57) <= not( ex1_sh_lv2x_b(57) and ex1_sh_lv2y_b(57) and ex1_sh_lv2z_b(57) ) ; + lv2_58: ex1_sh_lvl2(58) <= not( ex1_sh_lv2x_b(58) and ex1_sh_lv2y_b(58) and ex1_sh_lv2z_b(58) ) ; + lv2_59: ex1_sh_lvl2(59) <= not( ex1_sh_lv2x_b(59) and ex1_sh_lv2y_b(59) and ex1_sh_lv2z_b(59) ) ; + lv2_60: ex1_sh_lvl2(60) <= not( ex1_sh_lv2y_b(60) and ex1_sh_lv2z_b(60) ) ; + lv2_61: ex1_sh_lvl2(61) <= not( ex1_sh_lv2y_b(61) and ex1_sh_lv2z_b(61) ) ; + lv2_62: ex1_sh_lvl2(62) <= not( ex1_sh_lv2y_b(62) and ex1_sh_lv2z_b(62) ) ; + lv2_63: ex1_sh_lvl2(63) <= not( ex1_sh_lv2y_b(63) and ex1_sh_lv2z_b(63) ) ; + lv2_64: ex1_sh_lvl2(64) <= not( ex1_sh_lv2y_b(64) ) ; + lv2_65: ex1_sh_lvl2(65) <= not( ex1_sh_lv2y_b(65) ) ; + lv2_66: ex1_sh_lvl2(66) <= not( ex1_sh_lv2y_b(66) ) ; + lv2_67: ex1_sh_lvl2(67) <= not( ex1_sh_lv2y_b(67) ) ; + + + +end; + + + + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_byp.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_byp.vhdl new file mode 100644 index 0000000..d732c43 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_byp.vhdl @@ -0,0 +1,1807 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Synopsys translate, Issues resolved: NONE + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + +ENTITY fuq_byp IS +generic( expand_type : integer := 2 ); +PORT( + vdd :inout power_logic; + gnd :inout power_logic; + clkoff_b :in std_ulogic; + act_dis :in std_ulogic; + flush :in std_ulogic; + delay_lclkr :in std_ulogic; + mpw1_b :in std_ulogic; + mpw2_b :in std_ulogic; + sg_1 :in std_ulogic; + thold_1 :in std_ulogic; + fpu_enable :in std_ulogic; + nclk :in clk_logic; + + f_byp_si :in std_ulogic; + f_byp_so :out std_ulogic; + rf1_act :in std_ulogic; + + f_dcd_rf1_bypsel_a_res0 :in std_ulogic; + f_dcd_rf1_bypsel_a_res1 :in std_ulogic; + f_dcd_rf1_bypsel_a_load0 :in std_ulogic; + f_dcd_rf1_bypsel_a_load1 :in std_ulogic; + f_dcd_rf1_bypsel_b_res0 :in std_ulogic; + f_dcd_rf1_bypsel_b_res1 :in std_ulogic; + f_dcd_rf1_bypsel_b_load0 :in std_ulogic; + f_dcd_rf1_bypsel_b_load1 :in std_ulogic; + f_dcd_rf1_bypsel_c_res0 :in std_ulogic; + f_dcd_rf1_bypsel_c_res1 :in std_ulogic; + f_dcd_rf1_bypsel_c_load0 :in std_ulogic; + f_dcd_rf1_bypsel_c_load1 :in std_ulogic; + + + f_rnd_ex6_res_sign :in std_ulogic; + f_rnd_ex6_res_expo :in std_ulogic_vector(1 to 13); + f_rnd_ex6_res_frac :in std_ulogic_vector(0 to 52); + f_dcd_rf1_uc_fc_hulp :in std_ulogic ; + + f_dcd_rf1_div_beg :in std_ulogic; + f_dcd_rf1_uc_fa_pos :in std_ulogic; + f_dcd_rf1_uc_fc_pos :in std_ulogic; + f_dcd_rf1_uc_fb_pos :in std_ulogic; + f_dcd_rf1_uc_fc_0_5 :in std_ulogic; + f_dcd_rf1_uc_fc_1_0 :in std_ulogic; + f_dcd_rf1_uc_fc_1_minus :in std_ulogic; + f_dcd_rf1_uc_fb_1_0 :in std_ulogic; + f_dcd_rf1_uc_fb_0_75 :in std_ulogic; + f_dcd_rf1_uc_fb_0_5 :in std_ulogic; + + + f_fpr_ex7_frt_sign :in std_ulogic ; + f_fpr_ex7_frt_expo :in std_ulogic_vector (1 to 13); + f_fpr_ex7_frt_frac :in std_ulogic_vector (0 to 52); + f_fpr_ex7_load_sign :in std_ulogic ; + f_fpr_ex7_load_expo :in std_ulogic_vector (3 to 13); + f_fpr_ex7_load_frac :in std_ulogic_vector (0 to 52); + + f_fpr_ex6_load_sign :in std_ulogic; + f_fpr_ex6_load_expo :in std_ulogic_vector(3 to 13); + f_fpr_ex6_load_frac :in std_ulogic_vector(0 to 52); + + f_fpr_rf1_a_sign :in std_ulogic; + f_fpr_rf1_a_expo :in std_ulogic_vector(1 to 13); + f_fpr_rf1_a_frac :in std_ulogic_vector(0 to 52); + + f_fpr_rf1_c_sign :in std_ulogic; + f_fpr_rf1_c_expo :in std_ulogic_vector(1 to 13); + f_fpr_rf1_c_frac :in std_ulogic_vector(0 to 52); + + f_fpr_rf1_b_sign :in std_ulogic; + f_fpr_rf1_b_expo :in std_ulogic_vector(1 to 13); + f_fpr_rf1_b_frac :in std_ulogic_vector(0 to 52); + + f_dcd_rf1_aop_valid :in std_ulogic; + f_dcd_rf1_cop_valid :in std_ulogic; + f_dcd_rf1_bop_valid :in std_ulogic; + f_dcd_rf1_sp :in std_ulogic; + f_dcd_rf1_to_integer_b :in std_ulogic; + f_dcd_rf1_emin_dp :in std_ulogic; + f_dcd_rf1_emin_sp :in std_ulogic; + + f_byp_fmt_ex1_a_expo :out std_ulogic_vector(1 to 13); + f_byp_fmt_ex1_c_expo :out std_ulogic_vector(1 to 13); + f_byp_fmt_ex1_b_expo :out std_ulogic_vector(1 to 13); + f_byp_eie_ex1_a_expo :out std_ulogic_vector(1 to 13); + f_byp_eie_ex1_c_expo :out std_ulogic_vector(1 to 13); + f_byp_eie_ex1_b_expo :out std_ulogic_vector(1 to 13); + f_byp_alg_ex1_a_expo :out std_ulogic_vector(1 to 13); + f_byp_alg_ex1_c_expo :out std_ulogic_vector(1 to 13); + f_byp_alg_ex1_b_expo :out std_ulogic_vector(1 to 13); + + f_byp_fmt_ex1_a_sign :out std_ulogic; + f_byp_fmt_ex1_c_sign :out std_ulogic; + f_byp_fmt_ex1_b_sign :out std_ulogic; + f_byp_pic_ex1_a_sign :out std_ulogic; + f_byp_pic_ex1_c_sign :out std_ulogic; + f_byp_pic_ex1_b_sign :out std_ulogic; + f_byp_alg_ex1_b_sign :out std_ulogic; + + f_byp_fmt_ex1_a_frac :out std_ulogic_vector(0 to 52); + f_byp_fmt_ex1_c_frac :out std_ulogic_vector(0 to 52); + f_byp_fmt_ex1_b_frac :out std_ulogic_vector(0 to 52); + f_byp_alg_ex1_b_frac :out std_ulogic_vector(0 to 52); + f_byp_mul_ex1_a_frac :out std_ulogic_vector(0 to 52) ; + f_byp_mul_ex1_a_frac_17 :out std_ulogic ; + f_byp_mul_ex1_a_frac_35 :out std_ulogic ; + f_byp_mul_ex1_c_frac :out std_ulogic_vector(0 to 53) + + +); + +-- synopsys translate_off + + + + + +-- synopsys translate_on + + +end fuq_byp; + +architecture fuq_byp of fuq_byp is + + constant tiup :std_ulogic := '1'; + constant tidn :std_ulogic := '0'; + constant k_emin_dp :std_ulogic_vector(1 to 13) := "0000000000001"; + constant k_emin_sp :std_ulogic_vector(1 to 13) := "0001110000001"; + constant k_toint :std_ulogic_vector(1 to 13) := "0010001101001"; + constant expo_zero :std_ulogic_vector(1 to 13) := "0000000000001"; + constant expo_bias :std_ulogic_vector(1 to 13) := "0001111111111"; + constant expo_bias_m1 :std_ulogic_vector(1 to 13) := "0001111111110"; + + signal rf1_c_k_expo :std_ulogic_vector(1 to 13); + signal rf1_b_k_expo :std_ulogic_vector(1 to 13); + signal rf1_a_k_expo :std_ulogic_vector(1 to 13); + signal rf1_a_k_frac :std_ulogic_vector(0 to 52); + signal rf1_c_k_frac :std_ulogic_vector(0 to 52); + signal rf1_b_k_frac :std_ulogic_vector(0 to 52); + + signal rf1_a_expo_prebyp :std_ulogic_vector(1 to 13); + signal rf1_c_expo_prebyp :std_ulogic_vector(1 to 13); + signal rf1_b_expo_prebyp :std_ulogic_vector(1 to 13); + signal rf1_a_frac_prebyp :std_ulogic_vector(0 to 52); + signal rf1_c_frac_prebyp :std_ulogic_vector(0 to 52); + signal rf1_b_frac_prebyp :std_ulogic_vector(0 to 52); + signal rf1_a_sign_prebyp :std_ulogic; + signal rf1_c_sign_prebyp :std_ulogic; + signal rf1_b_sign_prebyp :std_ulogic; + + + signal rf1_a_sign_pre1_b :std_ulogic; + signal rf1_a_sign_pre2_b :std_ulogic; + signal rf1_a_sign_pre :std_ulogic; + signal rf1_c_sign_pre1_b :std_ulogic; + signal rf1_c_sign_pre2_b :std_ulogic; + signal rf1_c_sign_pre :std_ulogic; + signal rf1_b_sign_pre1_b :std_ulogic; + signal rf1_b_sign_pre2_b :std_ulogic; + signal rf1_b_sign_pre :std_ulogic; + + signal aop_valid_sign , cop_valid_sign , bop_valid_sign :std_ulogic; + signal aop_valid_plus , cop_valid_plus , bop_valid_plus :std_ulogic; + + + signal spare_unused :std_ulogic_vector(0 to 3); + signal unused :std_ulogic; + signal thold_0, forcee, thold_0_b, sg_0 :std_ulogic ; + + + signal ex1_b_frac_si , ex1_b_frac_so :std_ulogic_vector(0 to 52); + signal ex1_frac_a_fmt_si , ex1_frac_a_fmt_so :std_ulogic_vector(0 to 52); + signal ex1_frac_c_fmt_si , ex1_frac_c_fmt_so :std_ulogic_vector(0 to 52); + signal ex1_frac_b_fmt_si , ex1_frac_b_fmt_so :std_ulogic_vector(0 to 52); + signal frac_mul_c_si , frac_mul_c_so :std_ulogic_vector(0 to 53); + signal frac_mul_a_si , frac_mul_a_so :std_ulogic_vector(0 to 54); + + signal ex1_expo_a_eie_si, ex1_expo_a_eie_so :std_ulogic_vector(0 to 13); + signal ex1_expo_b_eie_si, ex1_expo_b_eie_so :std_ulogic_vector(0 to 13); + signal ex1_expo_c_eie_si, ex1_expo_c_eie_so :std_ulogic_vector(0 to 13); + signal ex1_expo_a_fmt_si, ex1_expo_a_fmt_so :std_ulogic_vector(0 to 13); + signal ex1_expo_b_fmt_si, ex1_expo_b_fmt_so :std_ulogic_vector(0 to 13); + signal ex1_expo_c_fmt_si, ex1_expo_c_fmt_so :std_ulogic_vector(0 to 13); + signal ex1_expo_b_alg_si, ex1_expo_b_alg_so :std_ulogic_vector(0 to 13); + signal ex1_expo_a_alg_si, ex1_expo_a_alg_so :std_ulogic_vector(0 to 12); + signal ex1_expo_c_alg_si, ex1_expo_c_alg_so :std_ulogic_vector(0 to 12); + + signal act_si, act_so :std_ulogic_vector(0 to 3); + + + signal sel_a_no_byp_s :std_ulogic; + signal sel_c_no_byp_s :std_ulogic; + signal sel_b_no_byp_s :std_ulogic; + signal sel_a_res0_s :std_ulogic; + signal sel_a_res1_s :std_ulogic; + signal sel_a_load0_s :std_ulogic; + signal sel_a_load1_s :std_ulogic; + signal sel_c_res0_s :std_ulogic; + signal sel_c_res1_s :std_ulogic; + signal sel_c_load0_s :std_ulogic; + signal sel_c_load1_s :std_ulogic; + signal sel_b_res0_s :std_ulogic; + signal sel_b_res1_s :std_ulogic; + signal sel_b_load0_s :std_ulogic; + signal sel_b_load1_s :std_ulogic; + + signal sel_a_no_byp :std_ulogic; + signal sel_c_no_byp :std_ulogic; + signal sel_b_no_byp :std_ulogic; + + + signal sel_a_imm :std_ulogic; + signal sel_a_res0 :std_ulogic; + signal sel_a_res1 :std_ulogic; + signal sel_a_load0 :std_ulogic; + signal sel_a_load1 :std_ulogic; + signal sel_c_imm :std_ulogic; + signal sel_c_res0 :std_ulogic; + signal sel_c_res1 :std_ulogic; + signal sel_c_load0 :std_ulogic; + signal sel_c_load1 :std_ulogic; + signal sel_b_imm :std_ulogic; + signal sel_b_res0 :std_ulogic; + signal sel_b_res1 :std_ulogic; + signal sel_b_load0 :std_ulogic; + signal sel_b_load1 :std_ulogic; + + + signal ex6_load_expo :std_ulogic_vector(1 to 13); + + signal rf1_b_frac_alg_b, ex1_b_frac_alg_b :std_ulogic_vector(0 to 52); + signal rf1_a_frac_fmt_b, ex1_a_frac_fmt_b :std_ulogic_vector(0 to 52); + signal rf1_c_frac_fmt_b, ex1_c_frac_fmt_b :std_ulogic_vector(0 to 52); + signal rf1_b_frac_fmt_b, ex1_b_frac_fmt_b :std_ulogic_vector(0 to 52); + signal ex1_a_frac_mul_17_b, ex1_a_frac_mul_35_b :std_ulogic; + signal ex1_a_frac_mul_b :std_ulogic_vector(0 to 52); + signal ex1_c_frac_mul_b :std_ulogic_vector(0 to 53); + signal rf1_a_frac_mul_17_b, rf1_a_frac_mul_35_b :std_ulogic; + signal rf1_a_frac_mul_b :std_ulogic_vector(0 to 52); + signal rf1_c_frac_mul_b :std_ulogic_vector(0 to 53); + signal rf1_b_sign_alg_b, ex1_b_sign_alg_b :std_ulogic ; + signal rf1_b_expo_alg_b, ex1_b_expo_alg_b :std_ulogic_vector(1 to 13); + signal rf1_c_expo_alg_b, ex1_c_expo_alg_b :std_ulogic_vector(1 to 13); + signal rf1_a_expo_alg_b, ex1_a_expo_alg_b :std_ulogic_vector(1 to 13); + signal rf1_a_sign_fmt_b, ex1_a_sign_fmt_b :std_ulogic ; + signal rf1_a_expo_fmt_b, ex1_a_expo_fmt_b :std_ulogic_vector(1 to 13) ; + signal rf1_c_sign_fmt_b, ex1_c_sign_fmt_b :std_ulogic ; + signal rf1_c_expo_fmt_b, ex1_c_expo_fmt_b :std_ulogic_vector(1 to 13) ; + signal rf1_b_sign_fmt_b, ex1_b_sign_fmt_b :std_ulogic ; + signal rf1_b_expo_fmt_b, ex1_b_expo_fmt_b :std_ulogic_vector(1 to 13) ; + signal rf1_a_sign_pic_b, ex1_a_sign_pic_b :std_ulogic ; + signal rf1_a_expo_eie_b, ex1_a_expo_eie_b :std_ulogic_vector(1 to 13) ; + signal rf1_c_sign_pic_b, ex1_c_sign_pic_b :std_ulogic ; + signal rf1_c_expo_eie_b, ex1_c_expo_eie_b :std_ulogic_vector(1 to 13) ; + signal rf1_b_sign_pic_b, ex1_b_sign_pic_b :std_ulogic ; + signal rf1_b_expo_eie_b, ex1_b_expo_eie_b :std_ulogic_vector(1 to 13) ; + signal cop_uc_imm , bop_uc_imm :std_ulogic; + + signal rf1_a_sign_fpr :std_ulogic; + signal rf1_c_sign_fpr :std_ulogic; + signal rf1_b_sign_fpr :std_ulogic; + signal rf1_a_expo_fpr :std_ulogic_vector(1 to 13); + signal rf1_c_expo_fpr :std_ulogic_vector(1 to 13); + signal rf1_b_expo_fpr :std_ulogic_vector(1 to 13); + signal rf1_a_frac_fpr :std_ulogic_vector(0 to 52); + signal rf1_c_frac_fpr :std_ulogic_vector(0 to 52); + signal rf1_b_frac_fpr :std_ulogic_vector(0 to 52); + + signal ex6_sign_res_ear :std_ulogic; + signal ex6_sign_res_dly :std_ulogic; + signal ex6_sign_lod_ear :std_ulogic; + signal ex6_sign_lod_dly :std_ulogic; + signal ex6_expo_res_ear :std_ulogic_vector(1 to 13); + signal ex6_expo_res_dly :std_ulogic_vector(1 to 13); + signal ex6_expo_lod_ear :std_ulogic_vector(1 to 13); + signal ex6_expo_lod_dly :std_ulogic_vector(1 to 13); + signal ex6_frac_res_ear :std_ulogic_vector(0 to 52); + signal ex6_frac_res_dly :std_ulogic_vector(0 to 52); + signal ex6_frac_lod_ear :std_ulogic_vector(0 to 52); + signal ex6_frac_lod_dly :std_ulogic_vector(0 to 52); + signal rf1_a_expo_pre1_b :std_ulogic_vector(1 to 13); + signal rf1_c_expo_pre1_b :std_ulogic_vector(1 to 13); + signal rf1_b_expo_pre1_b :std_ulogic_vector(1 to 13); + signal rf1_a_expo_pre2_b :std_ulogic_vector(1 to 13); + signal rf1_c_expo_pre2_b :std_ulogic_vector(1 to 13); + signal rf1_b_expo_pre2_b :std_ulogic_vector(1 to 13); + signal rf1_a_expo_pre3_b :std_ulogic_vector(1 to 13); + signal rf1_c_expo_pre3_b :std_ulogic_vector(1 to 13); + signal rf1_b_expo_pre3_b :std_ulogic_vector(1 to 13); + signal rf1_a_expo_pre :std_ulogic_vector(1 to 13); + signal rf1_c_expo_pre :std_ulogic_vector(1 to 13); + signal rf1_b_expo_pre :std_ulogic_vector(1 to 13); + signal rf1_a_frac_pre :std_ulogic_vector(0 to 52); + signal rf1_c_frac_pre :std_ulogic_vector(0 to 52); + signal rf1_b_frac_pre :std_ulogic_vector(0 to 52); + signal rf1_a_frac_pre1_b :std_ulogic_vector(0 to 52); + signal rf1_a_frac_pre2_b :std_ulogic_vector(0 to 52); + signal rf1_c_frac_pre1_b :std_ulogic_vector(0 to 52); + signal rf1_c_frac_pre2_b :std_ulogic_vector(0 to 52); + signal rf1_c_frac_pre3_b :std_ulogic_vector(0 to 52); + signal rf1_b_frac_pre1_b :std_ulogic_vector(0 to 52); + signal rf1_b_frac_pre2_b :std_ulogic_vector(0 to 52); + signal rf1_b_frac_pre3_b :std_ulogic_vector(0 to 1); + + signal byp_ex1_d1clk, byp_ex1_d2clk :std_ulogic; + signal byp_ex1_lclk : clk_logic; + signal rf1_c_frac_pre3_hulp_b ,rf1_hulp_sp , rf1_c_frac_pre_hulp , rf1_c_frac_prebyp_hulp :std_ulogic ; + + signal temp_rf1_c_frac_mul :std_ulogic_vector(0 to 53); + signal temp_rf1_a_frac_mul :std_ulogic_vector(0 to 52); + signal temp_rf1_a_frac_mul_17 :std_ulogic; + signal temp_rf1_a_frac_mul_35 :std_ulogic; + +-- synopsys translate_off + + + + + + + + + + + + + + + + +-- synopsys translate_on + + signal ex1_b_frac_alg :std_ulogic_vector(0 to 52); + signal ex1_b_frac_fmt :std_ulogic_vector(0 to 52); + signal ex1_a_frac_fmt :std_ulogic_vector(0 to 52); + signal ex1_c_frac_fmt :std_ulogic_vector(0 to 52); + signal ex1_b_sign_alg :std_ulogic ; + signal ex1_b_sign_fmt :std_ulogic ; + signal ex1_a_sign_fmt :std_ulogic ; + signal ex1_c_sign_fmt :std_ulogic ; + signal ex1_b_sign_pic :std_ulogic ; + signal ex1_a_sign_pic :std_ulogic ; + signal ex1_c_sign_pic :std_ulogic ; + signal ex1_b_expo_alg :std_ulogic_vector(1 to 13) ; + signal ex1_a_expo_alg :std_ulogic_vector(1 to 13) ; + signal ex1_c_expo_alg :std_ulogic_vector(1 to 13) ; + signal ex1_b_expo_fmt :std_ulogic_vector(1 to 13) ; + signal ex1_a_expo_fmt :std_ulogic_vector(1 to 13) ; + signal ex1_c_expo_fmt :std_ulogic_vector(1 to 13) ; + signal ex1_b_expo_eie :std_ulogic_vector(1 to 13) ; + signal ex1_a_expo_eie :std_ulogic_vector(1 to 13) ; + signal ex1_c_expo_eie :std_ulogic_vector(1 to 13) ; + + + + +begin + + unused <= rf1_a_expo_pre3_b(1) or rf1_a_expo_pre3_b(2) or + rf1_c_expo_pre3_b(1) or rf1_c_expo_pre3_b(2) or rf1_c_expo_pre3_b(3) or + rf1_b_expo_pre3_b(1) or rf1_b_expo_pre3_b(2) or rf1_b_expo_pre3_b(3) or + rf1_a_k_expo(1) or rf1_a_k_expo(2) or + or_reduce( rf1_c_k_expo(1 to 12) ) or + or_reduce( rf1_b_k_expo(1 to 3) ) or + or_reduce( rf1_a_k_frac(0 to 52) ) or + or_reduce( rf1_b_k_frac(2 to 52) ) ; + + + + + thold_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => thold_1, + q(0) => thold_0 ); + + sg_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => sg_1 , + q(0) => sg_0 ); + + + lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map ( + clkoff_b => clkoff_b, + thold => thold_0, + sg => sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => thold_0_b ); + + + + + + act_lat: tri_rlmreg_p generic map (width=> 4, expand_type => expand_type, needs_sreset => 0 ) port map ( + delay_lclkr => delay_lclkr , + mpw1_b => mpw1_b , + mpw2_b => mpw2_b , + forcee => forcee, + + vd => vdd, + gd => gnd, + nclk => nclk, + act => fpu_enable, + thold_b => thold_0_b, + sg => sg_0, + scout => act_so , + scin => act_si , + din(0) => spare_unused(0), + din(1) => spare_unused(1), + din(2) => spare_unused(2), + din(3) => spare_unused(3), + dout(0) => spare_unused(0), + dout(1) => spare_unused(1), + dout(2) => spare_unused(2) , + dout(3) => spare_unused(3) ); + + + byp_ex1_lcb : tri_lcbnd generic map (expand_type => expand_type) port map( + delay_lclkr => delay_lclkr , + mpw1_b => mpw1_b , + mpw2_b => mpw2_b , + forcee => forcee, + nclk => nclk , + vd => vdd , + gd => gnd , + act => rf1_act , + sg => sg_0 , + thold_b => thold_0_b , + d1clk => byp_ex1_d1clk , + d2clk => byp_ex1_d2clk , + lclk => byp_ex1_lclk ); + + + + + + + + rf1_a_k_expo(1 to 2) <= tidn & tidn ; + rf1_a_k_expo(3 to 13) <= + ( (3 to 13=> not f_dcd_rf1_to_integer_b) and k_toint (3 to 13) ) or + ( (3 to 13=> f_dcd_rf1_emin_dp ) and k_emin_dp(3 to 13) ) or + ( (3 to 13=> f_dcd_rf1_emin_sp ) and k_emin_sp(3 to 13) ) ; + + + rf1_c_k_expo(1 to 3) <= tidn & tidn & tidn ; + rf1_c_k_expo(4 to 12) <= (4 to 12 => tiup); + rf1_c_k_expo(13) <= + ( not cop_uc_imm and expo_bias(13) ) or + ( f_dcd_rf1_uc_fc_1_0 and expo_bias(13) ) or + ( f_dcd_rf1_uc_fc_0_5 and expo_bias_m1(13) ) or + ( f_dcd_rf1_uc_fc_1_minus and expo_bias_m1(13) ) ; + + + rf1_b_k_expo(1 to 3) <= tidn & tidn & tidn ; + rf1_b_k_expo(4 to 13) <= + ( (4 to 13=> not bop_uc_imm ) and expo_zero(4 to 13) ) or + ( (4 to 13=> f_dcd_rf1_uc_fb_1_0 ) and expo_bias(4 to 13) ) or + ( (4 to 13=> f_dcd_rf1_uc_fb_0_5 ) and expo_bias_m1(4 to 13) ) or + ( (4 to 13=> f_dcd_rf1_uc_fb_0_75) and expo_bias_m1(4 to 13) ) ; + + + rf1_a_k_frac(0 to 52) <= tidn & (1 to 52 => tidn); + + rf1_c_k_frac(0) <= not f_dcd_rf1_div_beg ; + rf1_c_k_frac(1 to 52) <= (1 to 52 => f_dcd_rf1_uc_fc_1_minus); + + rf1_b_k_frac(0) <= bop_uc_imm ; + rf1_b_k_frac(1) <= f_dcd_rf1_uc_fb_0_75 ; + rf1_b_k_frac(2 to 52) <= (2 to 52 => tidn); + + + + + + cop_uc_imm <= f_dcd_rf1_uc_fc_0_5 or f_dcd_rf1_uc_fc_1_0 or f_dcd_rf1_uc_fc_1_minus ; + bop_uc_imm <= f_dcd_rf1_uc_fb_0_5 or f_dcd_rf1_uc_fb_1_0 or f_dcd_rf1_uc_fb_0_75 ; + + + aop_valid_sign <= (f_dcd_rf1_aop_valid and not f_dcd_rf1_uc_fa_pos) ; + cop_valid_sign <= (f_dcd_rf1_cop_valid and not f_dcd_rf1_uc_fc_pos and not cop_uc_imm) ; + bop_valid_sign <= (f_dcd_rf1_bop_valid and not f_dcd_rf1_uc_fb_pos and not bop_uc_imm) ; + + aop_valid_plus <= (f_dcd_rf1_aop_valid ); + cop_valid_plus <= (f_dcd_rf1_cop_valid and not cop_uc_imm); + bop_valid_plus <= (f_dcd_rf1_bop_valid and not bop_uc_imm); + + sel_a_no_byp_s <= not( f_dcd_rf1_bypsel_a_res0 or f_dcd_rf1_bypsel_a_res1 or f_dcd_rf1_bypsel_a_load0 or f_dcd_rf1_bypsel_a_load1 or not aop_valid_sign); + sel_c_no_byp_s <= not( f_dcd_rf1_bypsel_c_res0 or f_dcd_rf1_bypsel_c_res1 or f_dcd_rf1_bypsel_c_load0 or f_dcd_rf1_bypsel_c_load1 or not cop_valid_sign); + sel_b_no_byp_s <= not( f_dcd_rf1_bypsel_b_res0 or f_dcd_rf1_bypsel_b_res1 or f_dcd_rf1_bypsel_b_load0 or f_dcd_rf1_bypsel_b_load1 or not bop_valid_sign); + + sel_a_no_byp <= not( f_dcd_rf1_bypsel_a_res0 or f_dcd_rf1_bypsel_a_res1 or f_dcd_rf1_bypsel_a_load0 or f_dcd_rf1_bypsel_a_load1 or not aop_valid_plus); + sel_c_no_byp <= not( f_dcd_rf1_bypsel_c_res0 or f_dcd_rf1_bypsel_c_res1 or f_dcd_rf1_bypsel_c_load0 or f_dcd_rf1_bypsel_c_load1 or not cop_valid_plus); + sel_b_no_byp <= not( f_dcd_rf1_bypsel_b_res0 or f_dcd_rf1_bypsel_b_res1 or f_dcd_rf1_bypsel_b_load0 or f_dcd_rf1_bypsel_b_load1 or not bop_valid_plus); + + + sel_a_res0_s <= aop_valid_sign and f_dcd_rf1_bypsel_a_res0 ; + sel_a_res1_s <= aop_valid_sign and f_dcd_rf1_bypsel_a_res1 ; + sel_a_load0_s <= aop_valid_sign and f_dcd_rf1_bypsel_a_load0 ; + sel_a_load1_s <= aop_valid_sign and f_dcd_rf1_bypsel_a_load1 ; + + sel_c_res0_s <= cop_valid_sign and f_dcd_rf1_bypsel_c_res0 ; + sel_c_res1_s <= cop_valid_sign and f_dcd_rf1_bypsel_c_res1 ; + sel_c_load0_s <= cop_valid_sign and f_dcd_rf1_bypsel_c_load0 ; + sel_c_load1_s <= cop_valid_sign and f_dcd_rf1_bypsel_c_load1 ; + + sel_b_res0_s <= bop_valid_sign and f_dcd_rf1_bypsel_b_res0 ; + sel_b_res1_s <= bop_valid_sign and f_dcd_rf1_bypsel_b_res1 ; + sel_b_load0_s <= bop_valid_sign and f_dcd_rf1_bypsel_b_load0 ; + sel_b_load1_s <= bop_valid_sign and f_dcd_rf1_bypsel_b_load1 ; + + sel_a_imm <= not aop_valid_plus ; + sel_a_res0 <= aop_valid_plus and f_dcd_rf1_bypsel_a_res0 ; + sel_a_res1 <= aop_valid_plus and f_dcd_rf1_bypsel_a_res1 ; + sel_a_load0 <= aop_valid_plus and f_dcd_rf1_bypsel_a_load0 ; + sel_a_load1 <= aop_valid_plus and f_dcd_rf1_bypsel_a_load1 ; + + sel_c_imm <= not cop_valid_plus ; + sel_c_res0 <= cop_valid_plus and f_dcd_rf1_bypsel_c_res0 ; + sel_c_res1 <= cop_valid_plus and f_dcd_rf1_bypsel_c_res1 ; + sel_c_load0 <= cop_valid_plus and f_dcd_rf1_bypsel_c_load0 ; + sel_c_load1 <= cop_valid_plus and f_dcd_rf1_bypsel_c_load1 ; + + sel_b_imm <= not bop_valid_plus ; + sel_b_res0 <= bop_valid_plus and f_dcd_rf1_bypsel_b_res0 ; + sel_b_res1 <= bop_valid_plus and f_dcd_rf1_bypsel_b_res1 ; + sel_b_load0 <= bop_valid_plus and f_dcd_rf1_bypsel_b_load0 ; + sel_b_load1 <= bop_valid_plus and f_dcd_rf1_bypsel_b_load1 ; + + + + ex6_sign_res_ear <= f_rnd_ex6_res_sign; + ex6_sign_res_dly <= f_fpr_ex7_frt_sign; + ex6_sign_lod_ear <= f_fpr_ex6_load_sign; + ex6_sign_lod_dly <= f_fpr_ex7_load_sign; + +fwd_a_sign_pre1: rf1_a_sign_pre1_b <= not( ( sel_a_res0_s and ex6_sign_res_ear ) or ( sel_a_res1_s and ex6_sign_res_dly ) ); +fwd_a_sign_pre2: rf1_a_sign_pre2_b <= not( ( sel_a_load0_s and ex6_sign_lod_ear ) or ( sel_a_load1_s and ex6_sign_lod_dly ) ); +fwd_a_sign_pre: rf1_a_sign_pre <= not( rf1_a_sign_pre1_b and rf1_a_sign_pre2_b ); + +fwd_c_sign_pre1: rf1_c_sign_pre1_b <= not( ( sel_c_res0_s and ex6_sign_res_ear ) or ( sel_c_res1_s and ex6_sign_res_dly ) ); +fwd_c_sign_pre2: rf1_c_sign_pre2_b <= not( ( sel_c_load0_s and ex6_sign_lod_ear ) or ( sel_c_load1_s and ex6_sign_lod_dly ) ); +fwd_c_sign_pre: rf1_c_sign_pre <= not( rf1_c_sign_pre1_b and rf1_c_sign_pre2_b ); + +fwd_b_sign_pre1: rf1_b_sign_pre1_b <= not( ( sel_b_res0_s and ex6_sign_res_ear ) or ( sel_b_res1_s and ex6_sign_res_dly ) ); +fwd_b_sign_pre2: rf1_b_sign_pre2_b <= not( ( sel_b_load0_s and ex6_sign_lod_ear ) or ( sel_b_load1_s and ex6_sign_lod_dly ) ); +fwd_b_sign_pre: rf1_b_sign_pre <= not( rf1_b_sign_pre1_b and rf1_b_sign_pre2_b ); + + rf1_a_sign_prebyp <= rf1_a_sign_pre ; + rf1_c_sign_prebyp <= rf1_c_sign_pre ; + rf1_b_sign_prebyp <= rf1_b_sign_pre ; + + + ex6_load_expo(1 to 13) <= tidn & tidn & f_fpr_ex6_load_expo(3 to 13) ; + ex6_expo_res_ear(1 to 13) <= f_rnd_ex6_res_expo(1 to 13); + ex6_expo_res_dly(1 to 13) <= f_fpr_ex7_frt_expo(1 to 13); + ex6_expo_lod_ear(1 to 13) <= ex6_load_expo(1 to 13); + ex6_expo_lod_dly(1 to 13) <= tidn & tidn & f_fpr_ex7_load_expo(3 to 13) ; + + +fwd_a_expo_pre1_01: rf1_a_expo_pre1_b( 1) <= not( ( sel_a_res0 and ex6_expo_res_ear( 1) ) or ( sel_a_res1 and ex6_expo_res_dly( 1) ) ); +fwd_a_expo_pre1_02: rf1_a_expo_pre1_b( 2) <= not( ( sel_a_res0 and ex6_expo_res_ear( 2) ) or ( sel_a_res1 and ex6_expo_res_dly( 2) ) ); +fwd_a_expo_pre1_03: rf1_a_expo_pre1_b( 3) <= not( ( sel_a_res0 and ex6_expo_res_ear( 3) ) or ( sel_a_res1 and ex6_expo_res_dly( 3) ) ); +fwd_a_expo_pre1_04: rf1_a_expo_pre1_b( 4) <= not( ( sel_a_res0 and ex6_expo_res_ear( 4) ) or ( sel_a_res1 and ex6_expo_res_dly( 4) ) ); +fwd_a_expo_pre1_05: rf1_a_expo_pre1_b( 5) <= not( ( sel_a_res0 and ex6_expo_res_ear( 5) ) or ( sel_a_res1 and ex6_expo_res_dly( 5) ) ); +fwd_a_expo_pre1_06: rf1_a_expo_pre1_b( 6) <= not( ( sel_a_res0 and ex6_expo_res_ear( 6) ) or ( sel_a_res1 and ex6_expo_res_dly( 6) ) ); +fwd_a_expo_pre1_07: rf1_a_expo_pre1_b( 7) <= not( ( sel_a_res0 and ex6_expo_res_ear( 7) ) or ( sel_a_res1 and ex6_expo_res_dly( 7) ) ); +fwd_a_expo_pre1_08: rf1_a_expo_pre1_b( 8) <= not( ( sel_a_res0 and ex6_expo_res_ear( 8) ) or ( sel_a_res1 and ex6_expo_res_dly( 8) ) ); +fwd_a_expo_pre1_09: rf1_a_expo_pre1_b( 9) <= not( ( sel_a_res0 and ex6_expo_res_ear( 9) ) or ( sel_a_res1 and ex6_expo_res_dly( 9) ) ); +fwd_a_expo_pre1_10: rf1_a_expo_pre1_b(10) <= not( ( sel_a_res0 and ex6_expo_res_ear(10) ) or ( sel_a_res1 and ex6_expo_res_dly(10) ) ); +fwd_a_expo_pre1_11: rf1_a_expo_pre1_b(11) <= not( ( sel_a_res0 and ex6_expo_res_ear(11) ) or ( sel_a_res1 and ex6_expo_res_dly(11) ) ); +fwd_a_expo_pre1_12: rf1_a_expo_pre1_b(12) <= not( ( sel_a_res0 and ex6_expo_res_ear(12) ) or ( sel_a_res1 and ex6_expo_res_dly(12) ) ); +fwd_a_expo_pre1_13: rf1_a_expo_pre1_b(13) <= not( ( sel_a_res0 and ex6_expo_res_ear(13) ) or ( sel_a_res1 and ex6_expo_res_dly(13) ) ); + +fwd_c_expo_pre1_01: rf1_c_expo_pre1_b( 1) <= not( ( sel_c_res0 and ex6_expo_res_ear( 1) ) or ( sel_c_res1 and ex6_expo_res_dly( 1) ) ); +fwd_c_expo_pre1_02: rf1_c_expo_pre1_b( 2) <= not( ( sel_c_res0 and ex6_expo_res_ear( 2) ) or ( sel_c_res1 and ex6_expo_res_dly( 2) ) ); +fwd_c_expo_pre1_03: rf1_c_expo_pre1_b( 3) <= not( ( sel_c_res0 and ex6_expo_res_ear( 3) ) or ( sel_c_res1 and ex6_expo_res_dly( 3) ) ); +fwd_c_expo_pre1_04: rf1_c_expo_pre1_b( 4) <= not( ( sel_c_res0 and ex6_expo_res_ear( 4) ) or ( sel_c_res1 and ex6_expo_res_dly( 4) ) ); +fwd_c_expo_pre1_05: rf1_c_expo_pre1_b( 5) <= not( ( sel_c_res0 and ex6_expo_res_ear( 5) ) or ( sel_c_res1 and ex6_expo_res_dly( 5) ) ); +fwd_c_expo_pre1_06: rf1_c_expo_pre1_b( 6) <= not( ( sel_c_res0 and ex6_expo_res_ear( 6) ) or ( sel_c_res1 and ex6_expo_res_dly( 6) ) ); +fwd_c_expo_pre1_07: rf1_c_expo_pre1_b( 7) <= not( ( sel_c_res0 and ex6_expo_res_ear( 7) ) or ( sel_c_res1 and ex6_expo_res_dly( 7) ) ); +fwd_c_expo_pre1_08: rf1_c_expo_pre1_b( 8) <= not( ( sel_c_res0 and ex6_expo_res_ear( 8) ) or ( sel_c_res1 and ex6_expo_res_dly( 8) ) ); +fwd_c_expo_pre1_09: rf1_c_expo_pre1_b( 9) <= not( ( sel_c_res0 and ex6_expo_res_ear( 9) ) or ( sel_c_res1 and ex6_expo_res_dly( 9) ) ); +fwd_c_expo_pre1_10: rf1_c_expo_pre1_b(10) <= not( ( sel_c_res0 and ex6_expo_res_ear(10) ) or ( sel_c_res1 and ex6_expo_res_dly(10) ) ); +fwd_c_expo_pre1_11: rf1_c_expo_pre1_b(11) <= not( ( sel_c_res0 and ex6_expo_res_ear(11) ) or ( sel_c_res1 and ex6_expo_res_dly(11) ) ); +fwd_c_expo_pre1_12: rf1_c_expo_pre1_b(12) <= not( ( sel_c_res0 and ex6_expo_res_ear(12) ) or ( sel_c_res1 and ex6_expo_res_dly(12) ) ); +fwd_c_expo_pre1_13: rf1_c_expo_pre1_b(13) <= not( ( sel_c_res0 and ex6_expo_res_ear(13) ) or ( sel_c_res1 and ex6_expo_res_dly(13) ) ); + +fwd_b_expo_pre1_01: rf1_b_expo_pre1_b( 1) <= not( ( sel_b_res0 and ex6_expo_res_ear( 1) ) or ( sel_b_res1 and ex6_expo_res_dly( 1) ) ); +fwd_b_expo_pre1_02: rf1_b_expo_pre1_b( 2) <= not( ( sel_b_res0 and ex6_expo_res_ear( 2) ) or ( sel_b_res1 and ex6_expo_res_dly( 2) ) ); +fwd_b_expo_pre1_03: rf1_b_expo_pre1_b( 3) <= not( ( sel_b_res0 and ex6_expo_res_ear( 3) ) or ( sel_b_res1 and ex6_expo_res_dly( 3) ) ); +fwd_b_expo_pre1_04: rf1_b_expo_pre1_b( 4) <= not( ( sel_b_res0 and ex6_expo_res_ear( 4) ) or ( sel_b_res1 and ex6_expo_res_dly( 4) ) ); +fwd_b_expo_pre1_05: rf1_b_expo_pre1_b( 5) <= not( ( sel_b_res0 and ex6_expo_res_ear( 5) ) or ( sel_b_res1 and ex6_expo_res_dly( 5) ) ); +fwd_b_expo_pre1_06: rf1_b_expo_pre1_b( 6) <= not( ( sel_b_res0 and ex6_expo_res_ear( 6) ) or ( sel_b_res1 and ex6_expo_res_dly( 6) ) ); +fwd_b_expo_pre1_07: rf1_b_expo_pre1_b( 7) <= not( ( sel_b_res0 and ex6_expo_res_ear( 7) ) or ( sel_b_res1 and ex6_expo_res_dly( 7) ) ); +fwd_b_expo_pre1_08: rf1_b_expo_pre1_b( 8) <= not( ( sel_b_res0 and ex6_expo_res_ear( 8) ) or ( sel_b_res1 and ex6_expo_res_dly( 8) ) ); +fwd_b_expo_pre1_09: rf1_b_expo_pre1_b( 9) <= not( ( sel_b_res0 and ex6_expo_res_ear( 9) ) or ( sel_b_res1 and ex6_expo_res_dly( 9) ) ); +fwd_b_expo_pre1_10: rf1_b_expo_pre1_b(10) <= not( ( sel_b_res0 and ex6_expo_res_ear(10) ) or ( sel_b_res1 and ex6_expo_res_dly(10) ) ); +fwd_b_expo_pre1_11: rf1_b_expo_pre1_b(11) <= not( ( sel_b_res0 and ex6_expo_res_ear(11) ) or ( sel_b_res1 and ex6_expo_res_dly(11) ) ); +fwd_b_expo_pre1_12: rf1_b_expo_pre1_b(12) <= not( ( sel_b_res0 and ex6_expo_res_ear(12) ) or ( sel_b_res1 and ex6_expo_res_dly(12) ) ); +fwd_b_expo_pre1_13: rf1_b_expo_pre1_b(13) <= not( ( sel_b_res0 and ex6_expo_res_ear(13) ) or ( sel_b_res1 and ex6_expo_res_dly(13) ) ); + + +fwd_a_expo_pre2_01: rf1_a_expo_pre2_b( 1) <= not( (sel_a_load0 and ex6_expo_lod_ear( 1) ) or (sel_a_load1 and ex6_expo_lod_dly( 1) ) ); +fwd_a_expo_pre2_02: rf1_a_expo_pre2_b( 2) <= not( (sel_a_load0 and ex6_expo_lod_ear( 2) ) or (sel_a_load1 and ex6_expo_lod_dly( 2) ) ); +fwd_a_expo_pre2_03: rf1_a_expo_pre2_b( 3) <= not( (sel_a_load0 and ex6_expo_lod_ear( 3) ) or (sel_a_load1 and ex6_expo_lod_dly( 3) ) ); +fwd_a_expo_pre2_04: rf1_a_expo_pre2_b( 4) <= not( (sel_a_load0 and ex6_expo_lod_ear( 4) ) or (sel_a_load1 and ex6_expo_lod_dly( 4) ) ); +fwd_a_expo_pre2_05: rf1_a_expo_pre2_b( 5) <= not( (sel_a_load0 and ex6_expo_lod_ear( 5) ) or (sel_a_load1 and ex6_expo_lod_dly( 5) ) ); +fwd_a_expo_pre2_06: rf1_a_expo_pre2_b( 6) <= not( (sel_a_load0 and ex6_expo_lod_ear( 6) ) or (sel_a_load1 and ex6_expo_lod_dly( 6) ) ); +fwd_a_expo_pre2_07: rf1_a_expo_pre2_b( 7) <= not( (sel_a_load0 and ex6_expo_lod_ear( 7) ) or (sel_a_load1 and ex6_expo_lod_dly( 7) ) ); +fwd_a_expo_pre2_08: rf1_a_expo_pre2_b( 8) <= not( (sel_a_load0 and ex6_expo_lod_ear( 8) ) or (sel_a_load1 and ex6_expo_lod_dly( 8) ) ); +fwd_a_expo_pre2_09: rf1_a_expo_pre2_b( 9) <= not( (sel_a_load0 and ex6_expo_lod_ear( 9) ) or (sel_a_load1 and ex6_expo_lod_dly( 9) ) ); +fwd_a_expo_pre2_10: rf1_a_expo_pre2_b(10) <= not( (sel_a_load0 and ex6_expo_lod_ear(10) ) or (sel_a_load1 and ex6_expo_lod_dly(10) ) ); +fwd_a_expo_pre2_11: rf1_a_expo_pre2_b(11) <= not( (sel_a_load0 and ex6_expo_lod_ear(11) ) or (sel_a_load1 and ex6_expo_lod_dly(11) ) ); +fwd_a_expo_pre2_12: rf1_a_expo_pre2_b(12) <= not( (sel_a_load0 and ex6_expo_lod_ear(12) ) or (sel_a_load1 and ex6_expo_lod_dly(12) ) ); +fwd_a_expo_pre2_13: rf1_a_expo_pre2_b(13) <= not( (sel_a_load0 and ex6_expo_lod_ear(13) ) or (sel_a_load1 and ex6_expo_lod_dly(13) ) ); + +fwd_c_expo_pre2_01: rf1_c_expo_pre2_b( 1) <= not( (sel_c_load0 and ex6_expo_lod_ear( 1) ) or (sel_c_load1 and ex6_expo_lod_dly( 1) ) ); +fwd_c_expo_pre2_02: rf1_c_expo_pre2_b( 2) <= not( (sel_c_load0 and ex6_expo_lod_ear( 2) ) or (sel_c_load1 and ex6_expo_lod_dly( 2) ) ); +fwd_c_expo_pre2_03: rf1_c_expo_pre2_b( 3) <= not( (sel_c_load0 and ex6_expo_lod_ear( 3) ) or (sel_c_load1 and ex6_expo_lod_dly( 3) ) ); +fwd_c_expo_pre2_04: rf1_c_expo_pre2_b( 4) <= not( (sel_c_load0 and ex6_expo_lod_ear( 4) ) or (sel_c_load1 and ex6_expo_lod_dly( 4) ) ); +fwd_c_expo_pre2_05: rf1_c_expo_pre2_b( 5) <= not( (sel_c_load0 and ex6_expo_lod_ear( 5) ) or (sel_c_load1 and ex6_expo_lod_dly( 5) ) ); +fwd_c_expo_pre2_06: rf1_c_expo_pre2_b( 6) <= not( (sel_c_load0 and ex6_expo_lod_ear( 6) ) or (sel_c_load1 and ex6_expo_lod_dly( 6) ) ); +fwd_c_expo_pre2_07: rf1_c_expo_pre2_b( 7) <= not( (sel_c_load0 and ex6_expo_lod_ear( 7) ) or (sel_c_load1 and ex6_expo_lod_dly( 7) ) ); +fwd_c_expo_pre2_08: rf1_c_expo_pre2_b( 8) <= not( (sel_c_load0 and ex6_expo_lod_ear( 8) ) or (sel_c_load1 and ex6_expo_lod_dly( 8) ) ); +fwd_c_expo_pre2_09: rf1_c_expo_pre2_b( 9) <= not( (sel_c_load0 and ex6_expo_lod_ear( 9) ) or (sel_c_load1 and ex6_expo_lod_dly( 9) ) ); +fwd_c_expo_pre2_10: rf1_c_expo_pre2_b(10) <= not( (sel_c_load0 and ex6_expo_lod_ear(10) ) or (sel_c_load1 and ex6_expo_lod_dly(10) ) ); +fwd_c_expo_pre2_11: rf1_c_expo_pre2_b(11) <= not( (sel_c_load0 and ex6_expo_lod_ear(11) ) or (sel_c_load1 and ex6_expo_lod_dly(11) ) ); +fwd_c_expo_pre2_12: rf1_c_expo_pre2_b(12) <= not( (sel_c_load0 and ex6_expo_lod_ear(12) ) or (sel_c_load1 and ex6_expo_lod_dly(12) ) ); +fwd_c_expo_pre2_13: rf1_c_expo_pre2_b(13) <= not( (sel_c_load0 and ex6_expo_lod_ear(13) ) or (sel_c_load1 and ex6_expo_lod_dly(13) ) ); + +fwd_b_expo_pre2_01: rf1_b_expo_pre2_b( 1) <= not( (sel_b_load0 and ex6_expo_lod_ear( 1) ) or (sel_b_load1 and ex6_expo_lod_dly( 1) ) ); +fwd_b_expo_pre2_02: rf1_b_expo_pre2_b( 2) <= not( (sel_b_load0 and ex6_expo_lod_ear( 2) ) or (sel_b_load1 and ex6_expo_lod_dly( 2) ) ); +fwd_b_expo_pre2_03: rf1_b_expo_pre2_b( 3) <= not( (sel_b_load0 and ex6_expo_lod_ear( 3) ) or (sel_b_load1 and ex6_expo_lod_dly( 3) ) ); +fwd_b_expo_pre2_04: rf1_b_expo_pre2_b( 4) <= not( (sel_b_load0 and ex6_expo_lod_ear( 4) ) or (sel_b_load1 and ex6_expo_lod_dly( 4) ) ); +fwd_b_expo_pre2_05: rf1_b_expo_pre2_b( 5) <= not( (sel_b_load0 and ex6_expo_lod_ear( 5) ) or (sel_b_load1 and ex6_expo_lod_dly( 5) ) ); +fwd_b_expo_pre2_06: rf1_b_expo_pre2_b( 6) <= not( (sel_b_load0 and ex6_expo_lod_ear( 6) ) or (sel_b_load1 and ex6_expo_lod_dly( 6) ) ); +fwd_b_expo_pre2_07: rf1_b_expo_pre2_b( 7) <= not( (sel_b_load0 and ex6_expo_lod_ear( 7) ) or (sel_b_load1 and ex6_expo_lod_dly( 7) ) ); +fwd_b_expo_pre2_08: rf1_b_expo_pre2_b( 8) <= not( (sel_b_load0 and ex6_expo_lod_ear( 8) ) or (sel_b_load1 and ex6_expo_lod_dly( 8) ) ); +fwd_b_expo_pre2_09: rf1_b_expo_pre2_b( 9) <= not( (sel_b_load0 and ex6_expo_lod_ear( 9) ) or (sel_b_load1 and ex6_expo_lod_dly( 9) ) ); +fwd_b_expo_pre2_10: rf1_b_expo_pre2_b(10) <= not( (sel_b_load0 and ex6_expo_lod_ear(10) ) or (sel_b_load1 and ex6_expo_lod_dly(10) ) ); +fwd_b_expo_pre2_11: rf1_b_expo_pre2_b(11) <= not( (sel_b_load0 and ex6_expo_lod_ear(11) ) or (sel_b_load1 and ex6_expo_lod_dly(11) ) ); +fwd_b_expo_pre2_12: rf1_b_expo_pre2_b(12) <= not( (sel_b_load0 and ex6_expo_lod_ear(12) ) or (sel_b_load1 and ex6_expo_lod_dly(12) ) ); +fwd_b_expo_pre2_13: rf1_b_expo_pre2_b(13) <= not( (sel_b_load0 and ex6_expo_lod_ear(13) ) or (sel_b_load1 and ex6_expo_lod_dly(13) ) ); + + + + +fwd_a_expo_pre3_01: rf1_a_expo_pre3_b( 1) <= not( tidn ); +fwd_a_expo_pre3_02: rf1_a_expo_pre3_b( 2) <= not( tidn ); +fwd_a_expo_pre3_03: rf1_a_expo_pre3_b( 3) <= not( sel_a_imm and rf1_a_k_expo( 3) ); +fwd_a_expo_pre3_04: rf1_a_expo_pre3_b( 4) <= not( sel_a_imm and rf1_a_k_expo( 4) ); +fwd_a_expo_pre3_05: rf1_a_expo_pre3_b( 5) <= not( sel_a_imm and rf1_a_k_expo( 5) ); +fwd_a_expo_pre3_06: rf1_a_expo_pre3_b( 6) <= not( sel_a_imm and rf1_a_k_expo( 6) ); +fwd_a_expo_pre3_07: rf1_a_expo_pre3_b( 7) <= not( sel_a_imm and rf1_a_k_expo( 7) ); +fwd_a_expo_pre3_08: rf1_a_expo_pre3_b( 8) <= not( sel_a_imm and rf1_a_k_expo( 8) ); +fwd_a_expo_pre3_09: rf1_a_expo_pre3_b( 9) <= not( sel_a_imm and rf1_a_k_expo( 9) ); +fwd_a_expo_pre3_10: rf1_a_expo_pre3_b(10) <= not( sel_a_imm and rf1_a_k_expo(10) ); +fwd_a_expo_pre3_11: rf1_a_expo_pre3_b(11) <= not( sel_a_imm and rf1_a_k_expo(11) ); +fwd_a_expo_pre3_12: rf1_a_expo_pre3_b(12) <= not( sel_a_imm and rf1_a_k_expo(12) ); +fwd_a_expo_pre3_13: rf1_a_expo_pre3_b(13) <= not( sel_a_imm and rf1_a_k_expo(13) ); + +fwd_c_expo_pre3_01: rf1_c_expo_pre3_b( 1) <= not( tidn ); +fwd_c_expo_pre3_02: rf1_c_expo_pre3_b( 2) <= not( tidn ); +fwd_c_expo_pre3_03: rf1_c_expo_pre3_b( 3) <= not( tidn ); +fwd_c_expo_pre3_04: rf1_c_expo_pre3_b( 4) <= not( sel_c_imm ); +fwd_c_expo_pre3_05: rf1_c_expo_pre3_b( 5) <= not( sel_c_imm ); +fwd_c_expo_pre3_06: rf1_c_expo_pre3_b( 6) <= not( sel_c_imm ); +fwd_c_expo_pre3_07: rf1_c_expo_pre3_b( 7) <= not( sel_c_imm ); +fwd_c_expo_pre3_08: rf1_c_expo_pre3_b( 8) <= not( sel_c_imm ); +fwd_c_expo_pre3_09: rf1_c_expo_pre3_b( 9) <= not( sel_c_imm ); +fwd_c_expo_pre3_10: rf1_c_expo_pre3_b(10) <= not( sel_c_imm ); +fwd_c_expo_pre3_11: rf1_c_expo_pre3_b(11) <= not( sel_c_imm ); +fwd_c_expo_pre3_12: rf1_c_expo_pre3_b(12) <= not( sel_c_imm ); +fwd_c_expo_pre3_13: rf1_c_expo_pre3_b(13) <= not( sel_c_imm and rf1_c_k_expo(13) ); + +fwd_b_expo_pre3_01: rf1_b_expo_pre3_b( 1) <= not( tidn ); +fwd_b_expo_pre3_02: rf1_b_expo_pre3_b( 2) <= not( tidn ); +fwd_b_expo_pre3_03: rf1_b_expo_pre3_b( 3) <= not( tidn ); +fwd_b_expo_pre3_04: rf1_b_expo_pre3_b( 4) <= not( sel_b_imm and rf1_b_k_expo( 4) ); +fwd_b_expo_pre3_05: rf1_b_expo_pre3_b( 5) <= not( sel_b_imm and rf1_b_k_expo( 5) ); +fwd_b_expo_pre3_06: rf1_b_expo_pre3_b( 6) <= not( sel_b_imm and rf1_b_k_expo( 6) ); +fwd_b_expo_pre3_07: rf1_b_expo_pre3_b( 7) <= not( sel_b_imm and rf1_b_k_expo( 7) ); +fwd_b_expo_pre3_08: rf1_b_expo_pre3_b( 8) <= not( sel_b_imm and rf1_b_k_expo( 8) ); +fwd_b_expo_pre3_09: rf1_b_expo_pre3_b( 9) <= not( sel_b_imm and rf1_b_k_expo( 9) ); +fwd_b_expo_pre3_10: rf1_b_expo_pre3_b(10) <= not( sel_b_imm and rf1_b_k_expo(10) ); +fwd_b_expo_pre3_11: rf1_b_expo_pre3_b(11) <= not( sel_b_imm and rf1_b_k_expo(11) ); +fwd_b_expo_pre3_12: rf1_b_expo_pre3_b(12) <= not( sel_b_imm and rf1_b_k_expo(12) ); +fwd_b_expo_pre3_13: rf1_b_expo_pre3_b(13) <= not( sel_b_imm and rf1_b_k_expo(13) ); + + +fwd_a_expo_pre_01: rf1_a_expo_pre( 1) <= not( rf1_a_expo_pre1_b( 1) and rf1_a_expo_pre2_b( 1) ); +fwd_a_expo_pre_02: rf1_a_expo_pre( 2) <= not( rf1_a_expo_pre1_b( 2) and rf1_a_expo_pre2_b( 2) ); +fwd_a_expo_pre_03: rf1_a_expo_pre( 3) <= not( rf1_a_expo_pre1_b( 3) and rf1_a_expo_pre2_b( 3) and rf1_a_expo_pre3_b( 3) ); +fwd_a_expo_pre_04: rf1_a_expo_pre( 4) <= not( rf1_a_expo_pre1_b( 4) and rf1_a_expo_pre2_b( 4) and rf1_a_expo_pre3_b( 4) ); +fwd_a_expo_pre_05: rf1_a_expo_pre( 5) <= not( rf1_a_expo_pre1_b( 5) and rf1_a_expo_pre2_b( 5) and rf1_a_expo_pre3_b( 5) ); +fwd_a_expo_pre_06: rf1_a_expo_pre( 6) <= not( rf1_a_expo_pre1_b( 6) and rf1_a_expo_pre2_b( 6) and rf1_a_expo_pre3_b( 6) ); +fwd_a_expo_pre_07: rf1_a_expo_pre( 7) <= not( rf1_a_expo_pre1_b( 7) and rf1_a_expo_pre2_b( 7) and rf1_a_expo_pre3_b( 7) ); +fwd_a_expo_pre_08: rf1_a_expo_pre( 8) <= not( rf1_a_expo_pre1_b( 8) and rf1_a_expo_pre2_b( 8) and rf1_a_expo_pre3_b( 8) ); +fwd_a_expo_pre_09: rf1_a_expo_pre( 9) <= not( rf1_a_expo_pre1_b( 9) and rf1_a_expo_pre2_b( 9) and rf1_a_expo_pre3_b( 9) ); +fwd_a_expo_pre_10: rf1_a_expo_pre(10) <= not( rf1_a_expo_pre1_b(10) and rf1_a_expo_pre2_b(10) and rf1_a_expo_pre3_b(10) ); +fwd_a_expo_pre_11: rf1_a_expo_pre(11) <= not( rf1_a_expo_pre1_b(11) and rf1_a_expo_pre2_b(11) and rf1_a_expo_pre3_b(11) ); +fwd_a_expo_pre_12: rf1_a_expo_pre(12) <= not( rf1_a_expo_pre1_b(12) and rf1_a_expo_pre2_b(12) and rf1_a_expo_pre3_b(12) ); +fwd_a_expo_pre_13: rf1_a_expo_pre(13) <= not( rf1_a_expo_pre1_b(13) and rf1_a_expo_pre2_b(13) and rf1_a_expo_pre3_b(13) ); + +fwd_c_expo_pre_01: rf1_c_expo_pre( 1) <= not( rf1_c_expo_pre1_b( 1) and rf1_c_expo_pre2_b( 1) ); +fwd_c_expo_pre_02: rf1_c_expo_pre( 2) <= not( rf1_c_expo_pre1_b( 2) and rf1_c_expo_pre2_b( 2) ); +fwd_c_expo_pre_03: rf1_c_expo_pre( 3) <= not( rf1_c_expo_pre1_b( 3) and rf1_c_expo_pre2_b( 3) ); +fwd_c_expo_pre_04: rf1_c_expo_pre( 4) <= not( rf1_c_expo_pre1_b( 4) and rf1_c_expo_pre2_b( 4) and rf1_c_expo_pre3_b( 4) ); +fwd_c_expo_pre_05: rf1_c_expo_pre( 5) <= not( rf1_c_expo_pre1_b( 5) and rf1_c_expo_pre2_b( 5) and rf1_c_expo_pre3_b( 5) ); +fwd_c_expo_pre_06: rf1_c_expo_pre( 6) <= not( rf1_c_expo_pre1_b( 6) and rf1_c_expo_pre2_b( 6) and rf1_c_expo_pre3_b( 6) ); +fwd_c_expo_pre_07: rf1_c_expo_pre( 7) <= not( rf1_c_expo_pre1_b( 7) and rf1_c_expo_pre2_b( 7) and rf1_c_expo_pre3_b( 7) ); +fwd_c_expo_pre_08: rf1_c_expo_pre( 8) <= not( rf1_c_expo_pre1_b( 8) and rf1_c_expo_pre2_b( 8) and rf1_c_expo_pre3_b( 8) ); +fwd_c_expo_pre_09: rf1_c_expo_pre( 9) <= not( rf1_c_expo_pre1_b( 9) and rf1_c_expo_pre2_b( 9) and rf1_c_expo_pre3_b( 9) ); +fwd_c_expo_pre_10: rf1_c_expo_pre(10) <= not( rf1_c_expo_pre1_b(10) and rf1_c_expo_pre2_b(10) and rf1_c_expo_pre3_b(10) ); +fwd_c_expo_pre_11: rf1_c_expo_pre(11) <= not( rf1_c_expo_pre1_b(11) and rf1_c_expo_pre2_b(11) and rf1_c_expo_pre3_b(11) ); +fwd_c_expo_pre_12: rf1_c_expo_pre(12) <= not( rf1_c_expo_pre1_b(12) and rf1_c_expo_pre2_b(12) and rf1_c_expo_pre3_b(12) ); +fwd_c_expo_pre_13: rf1_c_expo_pre(13) <= not( rf1_c_expo_pre1_b(13) and rf1_c_expo_pre2_b(13) and rf1_c_expo_pre3_b(13) ); + +fwd_b_expo_pre_01: rf1_b_expo_pre( 1) <= not( rf1_b_expo_pre1_b( 1) and rf1_b_expo_pre2_b( 1) ); +fwd_b_expo_pre_02: rf1_b_expo_pre( 2) <= not( rf1_b_expo_pre1_b( 2) and rf1_b_expo_pre2_b( 2) ); +fwd_b_expo_pre_03: rf1_b_expo_pre( 3) <= not( rf1_b_expo_pre1_b( 3) and rf1_b_expo_pre2_b( 3) ); +fwd_b_expo_pre_04: rf1_b_expo_pre( 4) <= not( rf1_b_expo_pre1_b( 4) and rf1_b_expo_pre2_b( 4) and rf1_b_expo_pre3_b( 4) ); +fwd_b_expo_pre_05: rf1_b_expo_pre( 5) <= not( rf1_b_expo_pre1_b( 5) and rf1_b_expo_pre2_b( 5) and rf1_b_expo_pre3_b( 5) ); +fwd_b_expo_pre_06: rf1_b_expo_pre( 6) <= not( rf1_b_expo_pre1_b( 6) and rf1_b_expo_pre2_b( 6) and rf1_b_expo_pre3_b( 6) ); +fwd_b_expo_pre_07: rf1_b_expo_pre( 7) <= not( rf1_b_expo_pre1_b( 7) and rf1_b_expo_pre2_b( 7) and rf1_b_expo_pre3_b( 7) ); +fwd_b_expo_pre_08: rf1_b_expo_pre( 8) <= not( rf1_b_expo_pre1_b( 8) and rf1_b_expo_pre2_b( 8) and rf1_b_expo_pre3_b( 8) ); +fwd_b_expo_pre_09: rf1_b_expo_pre( 9) <= not( rf1_b_expo_pre1_b( 9) and rf1_b_expo_pre2_b( 9) and rf1_b_expo_pre3_b( 9) ); +fwd_b_expo_pre_10: rf1_b_expo_pre(10) <= not( rf1_b_expo_pre1_b(10) and rf1_b_expo_pre2_b(10) and rf1_b_expo_pre3_b(10) ); +fwd_b_expo_pre_11: rf1_b_expo_pre(11) <= not( rf1_b_expo_pre1_b(11) and rf1_b_expo_pre2_b(11) and rf1_b_expo_pre3_b(11) ); +fwd_b_expo_pre_12: rf1_b_expo_pre(12) <= not( rf1_b_expo_pre1_b(12) and rf1_b_expo_pre2_b(12) and rf1_b_expo_pre3_b(12) ); +fwd_b_expo_pre_13: rf1_b_expo_pre(13) <= not( rf1_b_expo_pre1_b(13) and rf1_b_expo_pre2_b(13) and rf1_b_expo_pre3_b(13) ); + + + rf1_a_expo_prebyp(1 to 13) <= rf1_a_expo_pre(1 to 13); + rf1_c_expo_prebyp(1 to 13) <= rf1_c_expo_pre(1 to 13); + rf1_b_expo_prebyp(1 to 13) <= rf1_b_expo_pre(1 to 13); + + + ex6_frac_res_ear(0 to 52) <= f_rnd_ex6_res_frac(0 to 52); + ex6_frac_res_dly(0 to 52) <= f_fpr_ex7_frt_frac(0 to 52); + ex6_frac_lod_ear(0 to 52) <= f_fpr_ex6_load_frac(0 to 52); + ex6_frac_lod_dly(0 to 52) <= f_fpr_ex7_load_frac(0 to 52); + + + + + +fwd_c_frac_pre3_00: rf1_c_frac_pre3_b( 0) <= not( sel_c_imm and rf1_c_k_frac( 0) ); +fwd_c_frac_pre3_01: rf1_c_frac_pre3_b( 1) <= not( sel_c_imm and rf1_c_k_frac( 1) ); +fwd_c_frac_pre3_02: rf1_c_frac_pre3_b( 2) <= not( sel_c_imm and rf1_c_k_frac( 2) ); +fwd_c_frac_pre3_03: rf1_c_frac_pre3_b( 3) <= not( sel_c_imm and rf1_c_k_frac( 3) ); +fwd_c_frac_pre3_04: rf1_c_frac_pre3_b( 4) <= not( sel_c_imm and rf1_c_k_frac( 4) ); +fwd_c_frac_pre3_05: rf1_c_frac_pre3_b( 5) <= not( sel_c_imm and rf1_c_k_frac( 5) ); +fwd_c_frac_pre3_06: rf1_c_frac_pre3_b( 6) <= not( sel_c_imm and rf1_c_k_frac( 6) ); +fwd_c_frac_pre3_07: rf1_c_frac_pre3_b( 7) <= not( sel_c_imm and rf1_c_k_frac( 7) ); +fwd_c_frac_pre3_08: rf1_c_frac_pre3_b( 8) <= not( sel_c_imm and rf1_c_k_frac( 8) ); +fwd_c_frac_pre3_09: rf1_c_frac_pre3_b( 9) <= not( sel_c_imm and rf1_c_k_frac( 9) ); +fwd_c_frac_pre3_10: rf1_c_frac_pre3_b(10) <= not( sel_c_imm and rf1_c_k_frac(10) ); +fwd_c_frac_pre3_11: rf1_c_frac_pre3_b(11) <= not( sel_c_imm and rf1_c_k_frac(11) ); +fwd_c_frac_pre3_12: rf1_c_frac_pre3_b(12) <= not( sel_c_imm and rf1_c_k_frac(12) ); +fwd_c_frac_pre3_13: rf1_c_frac_pre3_b(13) <= not( sel_c_imm and rf1_c_k_frac(13) ); +fwd_c_frac_pre3_14: rf1_c_frac_pre3_b(14) <= not( sel_c_imm and rf1_c_k_frac(14) ); +fwd_c_frac_pre3_15: rf1_c_frac_pre3_b(15) <= not( sel_c_imm and rf1_c_k_frac(15) ); +fwd_c_frac_pre3_16: rf1_c_frac_pre3_b(16) <= not( sel_c_imm and rf1_c_k_frac(16) ); +fwd_c_frac_pre3_17: rf1_c_frac_pre3_b(17) <= not( sel_c_imm and rf1_c_k_frac(17) ); +fwd_c_frac_pre3_18: rf1_c_frac_pre3_b(18) <= not( sel_c_imm and rf1_c_k_frac(18) ); +fwd_c_frac_pre3_19: rf1_c_frac_pre3_b(19) <= not( sel_c_imm and rf1_c_k_frac(19) ); +fwd_c_frac_pre3_20: rf1_c_frac_pre3_b(20) <= not( sel_c_imm and rf1_c_k_frac(20) ); +fwd_c_frac_pre3_21: rf1_c_frac_pre3_b(21) <= not( sel_c_imm and rf1_c_k_frac(21) ); +fwd_c_frac_pre3_22: rf1_c_frac_pre3_b(22) <= not( sel_c_imm and rf1_c_k_frac(22) ); +fwd_c_frac_pre3_23: rf1_c_frac_pre3_b(23) <= not( sel_c_imm and rf1_c_k_frac(23) ); +fwd_c_frac_pre3_24: rf1_c_frac_pre3_b(24) <= not( sel_c_imm and rf1_c_k_frac(24) ); +fwd_c_frac_pre3_25: rf1_c_frac_pre3_b(25) <= not( sel_c_imm and rf1_c_k_frac(25) ); +fwd_c_frac_pre3_26: rf1_c_frac_pre3_b(26) <= not( sel_c_imm and rf1_c_k_frac(26) ); +fwd_c_frac_pre3_27: rf1_c_frac_pre3_b(27) <= not( sel_c_imm and rf1_c_k_frac(27) ); +fwd_c_frac_pre3_28: rf1_c_frac_pre3_b(28) <= not( sel_c_imm and rf1_c_k_frac(28) ); +fwd_c_frac_pre3_29: rf1_c_frac_pre3_b(29) <= not( sel_c_imm and rf1_c_k_frac(29) ); +fwd_c_frac_pre3_30: rf1_c_frac_pre3_b(30) <= not( sel_c_imm and rf1_c_k_frac(30) ); +fwd_c_frac_pre3_31: rf1_c_frac_pre3_b(31) <= not( sel_c_imm and rf1_c_k_frac(31) ); +fwd_c_frac_pre3_32: rf1_c_frac_pre3_b(32) <= not( sel_c_imm and rf1_c_k_frac(32) ); +fwd_c_frac_pre3_33: rf1_c_frac_pre3_b(33) <= not( sel_c_imm and rf1_c_k_frac(33) ); +fwd_c_frac_pre3_34: rf1_c_frac_pre3_b(34) <= not( sel_c_imm and rf1_c_k_frac(34) ); +fwd_c_frac_pre3_35: rf1_c_frac_pre3_b(35) <= not( sel_c_imm and rf1_c_k_frac(35) ); +fwd_c_frac_pre3_36: rf1_c_frac_pre3_b(36) <= not( sel_c_imm and rf1_c_k_frac(36) ); +fwd_c_frac_pre3_37: rf1_c_frac_pre3_b(37) <= not( sel_c_imm and rf1_c_k_frac(37) ); +fwd_c_frac_pre3_38: rf1_c_frac_pre3_b(38) <= not( sel_c_imm and rf1_c_k_frac(38) ); +fwd_c_frac_pre3_39: rf1_c_frac_pre3_b(39) <= not( sel_c_imm and rf1_c_k_frac(39) ); +fwd_c_frac_pre3_40: rf1_c_frac_pre3_b(40) <= not( sel_c_imm and rf1_c_k_frac(40) ); +fwd_c_frac_pre3_41: rf1_c_frac_pre3_b(41) <= not( sel_c_imm and rf1_c_k_frac(41) ); +fwd_c_frac_pre3_42: rf1_c_frac_pre3_b(42) <= not( sel_c_imm and rf1_c_k_frac(42) ); +fwd_c_frac_pre3_43: rf1_c_frac_pre3_b(43) <= not( sel_c_imm and rf1_c_k_frac(43) ); +fwd_c_frac_pre3_44: rf1_c_frac_pre3_b(44) <= not( sel_c_imm and rf1_c_k_frac(44) ); +fwd_c_frac_pre3_45: rf1_c_frac_pre3_b(45) <= not( sel_c_imm and rf1_c_k_frac(45) ); +fwd_c_frac_pre3_46: rf1_c_frac_pre3_b(46) <= not( sel_c_imm and rf1_c_k_frac(46) ); +fwd_c_frac_pre3_47: rf1_c_frac_pre3_b(47) <= not( sel_c_imm and rf1_c_k_frac(47) ); +fwd_c_frac_pre3_48: rf1_c_frac_pre3_b(48) <= not( sel_c_imm and rf1_c_k_frac(48) ); +fwd_c_frac_pre3_49: rf1_c_frac_pre3_b(49) <= not( sel_c_imm and rf1_c_k_frac(49) ); +fwd_c_frac_pre3_50: rf1_c_frac_pre3_b(50) <= not( sel_c_imm and rf1_c_k_frac(50) ); +fwd_c_frac_pre3_51: rf1_c_frac_pre3_b(51) <= not( sel_c_imm and rf1_c_k_frac(51) ); +fwd_c_frac_pre3_52: rf1_c_frac_pre3_b(52) <= not( sel_c_imm and rf1_c_k_frac(52) ); + +fwd_c_frac_pre3_24h: rf1_c_frac_pre3_hulp_b <= not( (sel_c_imm and rf1_c_k_frac(24)) or rf1_hulp_sp ); + +rf1_hulp_sp <= f_dcd_rf1_sp and f_dcd_rf1_uc_fc_hulp ; + + +fwd_b_frac_pre3_00: rf1_b_frac_pre3_b( 0) <= not( sel_b_imm and rf1_b_k_frac( 0) ); +fwd_b_frac_pre3_01: rf1_b_frac_pre3_b( 1) <= not( sel_b_imm and rf1_b_k_frac( 1) ); + + + +fwd_a_frac_pre1_00: rf1_a_frac_pre1_b( 0) <= not( (sel_a_res0 and ex6_frac_res_ear( 0) ) or (sel_a_res1 and ex6_frac_res_dly( 0) ) ); +fwd_a_frac_pre1_01: rf1_a_frac_pre1_b( 1) <= not( (sel_a_res0 and ex6_frac_res_ear( 1) ) or (sel_a_res1 and ex6_frac_res_dly( 1) ) ); +fwd_a_frac_pre1_02: rf1_a_frac_pre1_b( 2) <= not( (sel_a_res0 and ex6_frac_res_ear( 2) ) or (sel_a_res1 and ex6_frac_res_dly( 2) ) ); +fwd_a_frac_pre1_03: rf1_a_frac_pre1_b( 3) <= not( (sel_a_res0 and ex6_frac_res_ear( 3) ) or (sel_a_res1 and ex6_frac_res_dly( 3) ) ); +fwd_a_frac_pre1_04: rf1_a_frac_pre1_b( 4) <= not( (sel_a_res0 and ex6_frac_res_ear( 4) ) or (sel_a_res1 and ex6_frac_res_dly( 4) ) ); +fwd_a_frac_pre1_05: rf1_a_frac_pre1_b( 5) <= not( (sel_a_res0 and ex6_frac_res_ear( 5) ) or (sel_a_res1 and ex6_frac_res_dly( 5) ) ); +fwd_a_frac_pre1_06: rf1_a_frac_pre1_b( 6) <= not( (sel_a_res0 and ex6_frac_res_ear( 6) ) or (sel_a_res1 and ex6_frac_res_dly( 6) ) ); +fwd_a_frac_pre1_07: rf1_a_frac_pre1_b( 7) <= not( (sel_a_res0 and ex6_frac_res_ear( 7) ) or (sel_a_res1 and ex6_frac_res_dly( 7) ) ); +fwd_a_frac_pre1_08: rf1_a_frac_pre1_b( 8) <= not( (sel_a_res0 and ex6_frac_res_ear( 8) ) or (sel_a_res1 and ex6_frac_res_dly( 8) ) ); +fwd_a_frac_pre1_09: rf1_a_frac_pre1_b( 9) <= not( (sel_a_res0 and ex6_frac_res_ear( 9) ) or (sel_a_res1 and ex6_frac_res_dly( 9) ) ); +fwd_a_frac_pre1_10: rf1_a_frac_pre1_b(10) <= not( (sel_a_res0 and ex6_frac_res_ear(10) ) or (sel_a_res1 and ex6_frac_res_dly(10) ) ); +fwd_a_frac_pre1_11: rf1_a_frac_pre1_b(11) <= not( (sel_a_res0 and ex6_frac_res_ear(11) ) or (sel_a_res1 and ex6_frac_res_dly(11) ) ); +fwd_a_frac_pre1_12: rf1_a_frac_pre1_b(12) <= not( (sel_a_res0 and ex6_frac_res_ear(12) ) or (sel_a_res1 and ex6_frac_res_dly(12) ) ); +fwd_a_frac_pre1_13: rf1_a_frac_pre1_b(13) <= not( (sel_a_res0 and ex6_frac_res_ear(13) ) or (sel_a_res1 and ex6_frac_res_dly(13) ) ); +fwd_a_frac_pre1_14: rf1_a_frac_pre1_b(14) <= not( (sel_a_res0 and ex6_frac_res_ear(14) ) or (sel_a_res1 and ex6_frac_res_dly(14) ) ); +fwd_a_frac_pre1_15: rf1_a_frac_pre1_b(15) <= not( (sel_a_res0 and ex6_frac_res_ear(15) ) or (sel_a_res1 and ex6_frac_res_dly(15) ) ); +fwd_a_frac_pre1_16: rf1_a_frac_pre1_b(16) <= not( (sel_a_res0 and ex6_frac_res_ear(16) ) or (sel_a_res1 and ex6_frac_res_dly(16) ) ); +fwd_a_frac_pre1_17: rf1_a_frac_pre1_b(17) <= not( (sel_a_res0 and ex6_frac_res_ear(17) ) or (sel_a_res1 and ex6_frac_res_dly(17) ) ); +fwd_a_frac_pre1_18: rf1_a_frac_pre1_b(18) <= not( (sel_a_res0 and ex6_frac_res_ear(18) ) or (sel_a_res1 and ex6_frac_res_dly(18) ) ); +fwd_a_frac_pre1_19: rf1_a_frac_pre1_b(19) <= not( (sel_a_res0 and ex6_frac_res_ear(19) ) or (sel_a_res1 and ex6_frac_res_dly(19) ) ); +fwd_a_frac_pre1_20: rf1_a_frac_pre1_b(20) <= not( (sel_a_res0 and ex6_frac_res_ear(20) ) or (sel_a_res1 and ex6_frac_res_dly(20) ) ); +fwd_a_frac_pre1_21: rf1_a_frac_pre1_b(21) <= not( (sel_a_res0 and ex6_frac_res_ear(21) ) or (sel_a_res1 and ex6_frac_res_dly(21) ) ); +fwd_a_frac_pre1_22: rf1_a_frac_pre1_b(22) <= not( (sel_a_res0 and ex6_frac_res_ear(22) ) or (sel_a_res1 and ex6_frac_res_dly(22) ) ); +fwd_a_frac_pre1_23: rf1_a_frac_pre1_b(23) <= not( (sel_a_res0 and ex6_frac_res_ear(23) ) or (sel_a_res1 and ex6_frac_res_dly(23) ) ); +fwd_a_frac_pre1_24: rf1_a_frac_pre1_b(24) <= not( (sel_a_res0 and ex6_frac_res_ear(24) ) or (sel_a_res1 and ex6_frac_res_dly(24) ) ); +fwd_a_frac_pre1_25: rf1_a_frac_pre1_b(25) <= not( (sel_a_res0 and ex6_frac_res_ear(25) ) or (sel_a_res1 and ex6_frac_res_dly(25) ) ); +fwd_a_frac_pre1_26: rf1_a_frac_pre1_b(26) <= not( (sel_a_res0 and ex6_frac_res_ear(26) ) or (sel_a_res1 and ex6_frac_res_dly(26) ) ); +fwd_a_frac_pre1_27: rf1_a_frac_pre1_b(27) <= not( (sel_a_res0 and ex6_frac_res_ear(27) ) or (sel_a_res1 and ex6_frac_res_dly(27) ) ); +fwd_a_frac_pre1_28: rf1_a_frac_pre1_b(28) <= not( (sel_a_res0 and ex6_frac_res_ear(28) ) or (sel_a_res1 and ex6_frac_res_dly(28) ) ); +fwd_a_frac_pre1_29: rf1_a_frac_pre1_b(29) <= not( (sel_a_res0 and ex6_frac_res_ear(29) ) or (sel_a_res1 and ex6_frac_res_dly(29) ) ); +fwd_a_frac_pre1_30: rf1_a_frac_pre1_b(30) <= not( (sel_a_res0 and ex6_frac_res_ear(30) ) or (sel_a_res1 and ex6_frac_res_dly(30) ) ); +fwd_a_frac_pre1_31: rf1_a_frac_pre1_b(31) <= not( (sel_a_res0 and ex6_frac_res_ear(31) ) or (sel_a_res1 and ex6_frac_res_dly(31) ) ); +fwd_a_frac_pre1_32: rf1_a_frac_pre1_b(32) <= not( (sel_a_res0 and ex6_frac_res_ear(32) ) or (sel_a_res1 and ex6_frac_res_dly(32) ) ); +fwd_a_frac_pre1_33: rf1_a_frac_pre1_b(33) <= not( (sel_a_res0 and ex6_frac_res_ear(33) ) or (sel_a_res1 and ex6_frac_res_dly(33) ) ); +fwd_a_frac_pre1_34: rf1_a_frac_pre1_b(34) <= not( (sel_a_res0 and ex6_frac_res_ear(34) ) or (sel_a_res1 and ex6_frac_res_dly(34) ) ); +fwd_a_frac_pre1_35: rf1_a_frac_pre1_b(35) <= not( (sel_a_res0 and ex6_frac_res_ear(35) ) or (sel_a_res1 and ex6_frac_res_dly(35) ) ); +fwd_a_frac_pre1_36: rf1_a_frac_pre1_b(36) <= not( (sel_a_res0 and ex6_frac_res_ear(36) ) or (sel_a_res1 and ex6_frac_res_dly(36) ) ); +fwd_a_frac_pre1_37: rf1_a_frac_pre1_b(37) <= not( (sel_a_res0 and ex6_frac_res_ear(37) ) or (sel_a_res1 and ex6_frac_res_dly(37) ) ); +fwd_a_frac_pre1_38: rf1_a_frac_pre1_b(38) <= not( (sel_a_res0 and ex6_frac_res_ear(38) ) or (sel_a_res1 and ex6_frac_res_dly(38) ) ); +fwd_a_frac_pre1_39: rf1_a_frac_pre1_b(39) <= not( (sel_a_res0 and ex6_frac_res_ear(39) ) or (sel_a_res1 and ex6_frac_res_dly(39) ) ); +fwd_a_frac_pre1_40: rf1_a_frac_pre1_b(40) <= not( (sel_a_res0 and ex6_frac_res_ear(40) ) or (sel_a_res1 and ex6_frac_res_dly(40) ) ); +fwd_a_frac_pre1_41: rf1_a_frac_pre1_b(41) <= not( (sel_a_res0 and ex6_frac_res_ear(41) ) or (sel_a_res1 and ex6_frac_res_dly(41) ) ); +fwd_a_frac_pre1_42: rf1_a_frac_pre1_b(42) <= not( (sel_a_res0 and ex6_frac_res_ear(42) ) or (sel_a_res1 and ex6_frac_res_dly(42) ) ); +fwd_a_frac_pre1_43: rf1_a_frac_pre1_b(43) <= not( (sel_a_res0 and ex6_frac_res_ear(43) ) or (sel_a_res1 and ex6_frac_res_dly(43) ) ); +fwd_a_frac_pre1_44: rf1_a_frac_pre1_b(44) <= not( (sel_a_res0 and ex6_frac_res_ear(44) ) or (sel_a_res1 and ex6_frac_res_dly(44) ) ); +fwd_a_frac_pre1_45: rf1_a_frac_pre1_b(45) <= not( (sel_a_res0 and ex6_frac_res_ear(45) ) or (sel_a_res1 and ex6_frac_res_dly(45) ) ); +fwd_a_frac_pre1_46: rf1_a_frac_pre1_b(46) <= not( (sel_a_res0 and ex6_frac_res_ear(46) ) or (sel_a_res1 and ex6_frac_res_dly(46) ) ); +fwd_a_frac_pre1_47: rf1_a_frac_pre1_b(47) <= not( (sel_a_res0 and ex6_frac_res_ear(47) ) or (sel_a_res1 and ex6_frac_res_dly(47) ) ); +fwd_a_frac_pre1_48: rf1_a_frac_pre1_b(48) <= not( (sel_a_res0 and ex6_frac_res_ear(48) ) or (sel_a_res1 and ex6_frac_res_dly(48) ) ); +fwd_a_frac_pre1_49: rf1_a_frac_pre1_b(49) <= not( (sel_a_res0 and ex6_frac_res_ear(49) ) or (sel_a_res1 and ex6_frac_res_dly(49) ) ); +fwd_a_frac_pre1_50: rf1_a_frac_pre1_b(50) <= not( (sel_a_res0 and ex6_frac_res_ear(50) ) or (sel_a_res1 and ex6_frac_res_dly(50) ) ); +fwd_a_frac_pre1_51: rf1_a_frac_pre1_b(51) <= not( (sel_a_res0 and ex6_frac_res_ear(51) ) or (sel_a_res1 and ex6_frac_res_dly(51) ) ); +fwd_a_frac_pre1_52: rf1_a_frac_pre1_b(52) <= not( (sel_a_res0 and ex6_frac_res_ear(52) ) or (sel_a_res1 and ex6_frac_res_dly(52) ) ); + + +fwd_c_frac_pre1_00: rf1_c_frac_pre1_b( 0) <= not( (sel_c_res0 and ex6_frac_res_ear( 0) ) or (sel_c_res1 and ex6_frac_res_dly( 0) ) ); +fwd_c_frac_pre1_01: rf1_c_frac_pre1_b( 1) <= not( (sel_c_res0 and ex6_frac_res_ear( 1) ) or (sel_c_res1 and ex6_frac_res_dly( 1) ) ); +fwd_c_frac_pre1_02: rf1_c_frac_pre1_b( 2) <= not( (sel_c_res0 and ex6_frac_res_ear( 2) ) or (sel_c_res1 and ex6_frac_res_dly( 2) ) ); +fwd_c_frac_pre1_03: rf1_c_frac_pre1_b( 3) <= not( (sel_c_res0 and ex6_frac_res_ear( 3) ) or (sel_c_res1 and ex6_frac_res_dly( 3) ) ); +fwd_c_frac_pre1_04: rf1_c_frac_pre1_b( 4) <= not( (sel_c_res0 and ex6_frac_res_ear( 4) ) or (sel_c_res1 and ex6_frac_res_dly( 4) ) ); +fwd_c_frac_pre1_05: rf1_c_frac_pre1_b( 5) <= not( (sel_c_res0 and ex6_frac_res_ear( 5) ) or (sel_c_res1 and ex6_frac_res_dly( 5) ) ); +fwd_c_frac_pre1_06: rf1_c_frac_pre1_b( 6) <= not( (sel_c_res0 and ex6_frac_res_ear( 6) ) or (sel_c_res1 and ex6_frac_res_dly( 6) ) ); +fwd_c_frac_pre1_07: rf1_c_frac_pre1_b( 7) <= not( (sel_c_res0 and ex6_frac_res_ear( 7) ) or (sel_c_res1 and ex6_frac_res_dly( 7) ) ); +fwd_c_frac_pre1_08: rf1_c_frac_pre1_b( 8) <= not( (sel_c_res0 and ex6_frac_res_ear( 8) ) or (sel_c_res1 and ex6_frac_res_dly( 8) ) ); +fwd_c_frac_pre1_09: rf1_c_frac_pre1_b( 9) <= not( (sel_c_res0 and ex6_frac_res_ear( 9) ) or (sel_c_res1 and ex6_frac_res_dly( 9) ) ); +fwd_c_frac_pre1_10: rf1_c_frac_pre1_b(10) <= not( (sel_c_res0 and ex6_frac_res_ear(10) ) or (sel_c_res1 and ex6_frac_res_dly(10) ) ); +fwd_c_frac_pre1_11: rf1_c_frac_pre1_b(11) <= not( (sel_c_res0 and ex6_frac_res_ear(11) ) or (sel_c_res1 and ex6_frac_res_dly(11) ) ); +fwd_c_frac_pre1_12: rf1_c_frac_pre1_b(12) <= not( (sel_c_res0 and ex6_frac_res_ear(12) ) or (sel_c_res1 and ex6_frac_res_dly(12) ) ); +fwd_c_frac_pre1_13: rf1_c_frac_pre1_b(13) <= not( (sel_c_res0 and ex6_frac_res_ear(13) ) or (sel_c_res1 and ex6_frac_res_dly(13) ) ); +fwd_c_frac_pre1_14: rf1_c_frac_pre1_b(14) <= not( (sel_c_res0 and ex6_frac_res_ear(14) ) or (sel_c_res1 and ex6_frac_res_dly(14) ) ); +fwd_c_frac_pre1_15: rf1_c_frac_pre1_b(15) <= not( (sel_c_res0 and ex6_frac_res_ear(15) ) or (sel_c_res1 and ex6_frac_res_dly(15) ) ); +fwd_c_frac_pre1_16: rf1_c_frac_pre1_b(16) <= not( (sel_c_res0 and ex6_frac_res_ear(16) ) or (sel_c_res1 and ex6_frac_res_dly(16) ) ); +fwd_c_frac_pre1_17: rf1_c_frac_pre1_b(17) <= not( (sel_c_res0 and ex6_frac_res_ear(17) ) or (sel_c_res1 and ex6_frac_res_dly(17) ) ); +fwd_c_frac_pre1_18: rf1_c_frac_pre1_b(18) <= not( (sel_c_res0 and ex6_frac_res_ear(18) ) or (sel_c_res1 and ex6_frac_res_dly(18) ) ); +fwd_c_frac_pre1_19: rf1_c_frac_pre1_b(19) <= not( (sel_c_res0 and ex6_frac_res_ear(19) ) or (sel_c_res1 and ex6_frac_res_dly(19) ) ); +fwd_c_frac_pre1_20: rf1_c_frac_pre1_b(20) <= not( (sel_c_res0 and ex6_frac_res_ear(20) ) or (sel_c_res1 and ex6_frac_res_dly(20) ) ); +fwd_c_frac_pre1_21: rf1_c_frac_pre1_b(21) <= not( (sel_c_res0 and ex6_frac_res_ear(21) ) or (sel_c_res1 and ex6_frac_res_dly(21) ) ); +fwd_c_frac_pre1_22: rf1_c_frac_pre1_b(22) <= not( (sel_c_res0 and ex6_frac_res_ear(22) ) or (sel_c_res1 and ex6_frac_res_dly(22) ) ); +fwd_c_frac_pre1_23: rf1_c_frac_pre1_b(23) <= not( (sel_c_res0 and ex6_frac_res_ear(23) ) or (sel_c_res1 and ex6_frac_res_dly(23) ) ); +fwd_c_frac_pre1_24: rf1_c_frac_pre1_b(24) <= not( (sel_c_res0 and ex6_frac_res_ear(24) ) or (sel_c_res1 and ex6_frac_res_dly(24) ) ); +fwd_c_frac_pre1_25: rf1_c_frac_pre1_b(25) <= not( (sel_c_res0 and ex6_frac_res_ear(25) ) or (sel_c_res1 and ex6_frac_res_dly(25) ) ); +fwd_c_frac_pre1_26: rf1_c_frac_pre1_b(26) <= not( (sel_c_res0 and ex6_frac_res_ear(26) ) or (sel_c_res1 and ex6_frac_res_dly(26) ) ); +fwd_c_frac_pre1_27: rf1_c_frac_pre1_b(27) <= not( (sel_c_res0 and ex6_frac_res_ear(27) ) or (sel_c_res1 and ex6_frac_res_dly(27) ) ); +fwd_c_frac_pre1_28: rf1_c_frac_pre1_b(28) <= not( (sel_c_res0 and ex6_frac_res_ear(28) ) or (sel_c_res1 and ex6_frac_res_dly(28) ) ); +fwd_c_frac_pre1_29: rf1_c_frac_pre1_b(29) <= not( (sel_c_res0 and ex6_frac_res_ear(29) ) or (sel_c_res1 and ex6_frac_res_dly(29) ) ); +fwd_c_frac_pre1_30: rf1_c_frac_pre1_b(30) <= not( (sel_c_res0 and ex6_frac_res_ear(30) ) or (sel_c_res1 and ex6_frac_res_dly(30) ) ); +fwd_c_frac_pre1_31: rf1_c_frac_pre1_b(31) <= not( (sel_c_res0 and ex6_frac_res_ear(31) ) or (sel_c_res1 and ex6_frac_res_dly(31) ) ); +fwd_c_frac_pre1_32: rf1_c_frac_pre1_b(32) <= not( (sel_c_res0 and ex6_frac_res_ear(32) ) or (sel_c_res1 and ex6_frac_res_dly(32) ) ); +fwd_c_frac_pre1_33: rf1_c_frac_pre1_b(33) <= not( (sel_c_res0 and ex6_frac_res_ear(33) ) or (sel_c_res1 and ex6_frac_res_dly(33) ) ); +fwd_c_frac_pre1_34: rf1_c_frac_pre1_b(34) <= not( (sel_c_res0 and ex6_frac_res_ear(34) ) or (sel_c_res1 and ex6_frac_res_dly(34) ) ); +fwd_c_frac_pre1_35: rf1_c_frac_pre1_b(35) <= not( (sel_c_res0 and ex6_frac_res_ear(35) ) or (sel_c_res1 and ex6_frac_res_dly(35) ) ); +fwd_c_frac_pre1_36: rf1_c_frac_pre1_b(36) <= not( (sel_c_res0 and ex6_frac_res_ear(36) ) or (sel_c_res1 and ex6_frac_res_dly(36) ) ); +fwd_c_frac_pre1_37: rf1_c_frac_pre1_b(37) <= not( (sel_c_res0 and ex6_frac_res_ear(37) ) or (sel_c_res1 and ex6_frac_res_dly(37) ) ); +fwd_c_frac_pre1_38: rf1_c_frac_pre1_b(38) <= not( (sel_c_res0 and ex6_frac_res_ear(38) ) or (sel_c_res1 and ex6_frac_res_dly(38) ) ); +fwd_c_frac_pre1_39: rf1_c_frac_pre1_b(39) <= not( (sel_c_res0 and ex6_frac_res_ear(39) ) or (sel_c_res1 and ex6_frac_res_dly(39) ) ); +fwd_c_frac_pre1_40: rf1_c_frac_pre1_b(40) <= not( (sel_c_res0 and ex6_frac_res_ear(40) ) or (sel_c_res1 and ex6_frac_res_dly(40) ) ); +fwd_c_frac_pre1_41: rf1_c_frac_pre1_b(41) <= not( (sel_c_res0 and ex6_frac_res_ear(41) ) or (sel_c_res1 and ex6_frac_res_dly(41) ) ); +fwd_c_frac_pre1_42: rf1_c_frac_pre1_b(42) <= not( (sel_c_res0 and ex6_frac_res_ear(42) ) or (sel_c_res1 and ex6_frac_res_dly(42) ) ); +fwd_c_frac_pre1_43: rf1_c_frac_pre1_b(43) <= not( (sel_c_res0 and ex6_frac_res_ear(43) ) or (sel_c_res1 and ex6_frac_res_dly(43) ) ); +fwd_c_frac_pre1_44: rf1_c_frac_pre1_b(44) <= not( (sel_c_res0 and ex6_frac_res_ear(44) ) or (sel_c_res1 and ex6_frac_res_dly(44) ) ); +fwd_c_frac_pre1_45: rf1_c_frac_pre1_b(45) <= not( (sel_c_res0 and ex6_frac_res_ear(45) ) or (sel_c_res1 and ex6_frac_res_dly(45) ) ); +fwd_c_frac_pre1_46: rf1_c_frac_pre1_b(46) <= not( (sel_c_res0 and ex6_frac_res_ear(46) ) or (sel_c_res1 and ex6_frac_res_dly(46) ) ); +fwd_c_frac_pre1_47: rf1_c_frac_pre1_b(47) <= not( (sel_c_res0 and ex6_frac_res_ear(47) ) or (sel_c_res1 and ex6_frac_res_dly(47) ) ); +fwd_c_frac_pre1_48: rf1_c_frac_pre1_b(48) <= not( (sel_c_res0 and ex6_frac_res_ear(48) ) or (sel_c_res1 and ex6_frac_res_dly(48) ) ); +fwd_c_frac_pre1_49: rf1_c_frac_pre1_b(49) <= not( (sel_c_res0 and ex6_frac_res_ear(49) ) or (sel_c_res1 and ex6_frac_res_dly(49) ) ); +fwd_c_frac_pre1_50: rf1_c_frac_pre1_b(50) <= not( (sel_c_res0 and ex6_frac_res_ear(50) ) or (sel_c_res1 and ex6_frac_res_dly(50) ) ); +fwd_c_frac_pre1_51: rf1_c_frac_pre1_b(51) <= not( (sel_c_res0 and ex6_frac_res_ear(51) ) or (sel_c_res1 and ex6_frac_res_dly(51) ) ); +fwd_c_frac_pre1_52: rf1_c_frac_pre1_b(52) <= not( (sel_c_res0 and ex6_frac_res_ear(52) ) or (sel_c_res1 and ex6_frac_res_dly(52) ) ); + + +fwd_b_frac_pre1_00: rf1_b_frac_pre1_b( 0) <= not( (sel_b_res0 and ex6_frac_res_ear( 0) ) or (sel_b_res1 and ex6_frac_res_dly( 0) ) ); +fwd_b_frac_pre1_01: rf1_b_frac_pre1_b( 1) <= not( (sel_b_res0 and ex6_frac_res_ear( 1) ) or (sel_b_res1 and ex6_frac_res_dly( 1) ) ); +fwd_b_frac_pre1_02: rf1_b_frac_pre1_b( 2) <= not( (sel_b_res0 and ex6_frac_res_ear( 2) ) or (sel_b_res1 and ex6_frac_res_dly( 2) ) ); +fwd_b_frac_pre1_03: rf1_b_frac_pre1_b( 3) <= not( (sel_b_res0 and ex6_frac_res_ear( 3) ) or (sel_b_res1 and ex6_frac_res_dly( 3) ) ); +fwd_b_frac_pre1_04: rf1_b_frac_pre1_b( 4) <= not( (sel_b_res0 and ex6_frac_res_ear( 4) ) or (sel_b_res1 and ex6_frac_res_dly( 4) ) ); +fwd_b_frac_pre1_05: rf1_b_frac_pre1_b( 5) <= not( (sel_b_res0 and ex6_frac_res_ear( 5) ) or (sel_b_res1 and ex6_frac_res_dly( 5) ) ); +fwd_b_frac_pre1_06: rf1_b_frac_pre1_b( 6) <= not( (sel_b_res0 and ex6_frac_res_ear( 6) ) or (sel_b_res1 and ex6_frac_res_dly( 6) ) ); +fwd_b_frac_pre1_07: rf1_b_frac_pre1_b( 7) <= not( (sel_b_res0 and ex6_frac_res_ear( 7) ) or (sel_b_res1 and ex6_frac_res_dly( 7) ) ); +fwd_b_frac_pre1_08: rf1_b_frac_pre1_b( 8) <= not( (sel_b_res0 and ex6_frac_res_ear( 8) ) or (sel_b_res1 and ex6_frac_res_dly( 8) ) ); +fwd_b_frac_pre1_09: rf1_b_frac_pre1_b( 9) <= not( (sel_b_res0 and ex6_frac_res_ear( 9) ) or (sel_b_res1 and ex6_frac_res_dly( 9) ) ); +fwd_b_frac_pre1_10: rf1_b_frac_pre1_b(10) <= not( (sel_b_res0 and ex6_frac_res_ear(10) ) or (sel_b_res1 and ex6_frac_res_dly(10) ) ); +fwd_b_frac_pre1_11: rf1_b_frac_pre1_b(11) <= not( (sel_b_res0 and ex6_frac_res_ear(11) ) or (sel_b_res1 and ex6_frac_res_dly(11) ) ); +fwd_b_frac_pre1_12: rf1_b_frac_pre1_b(12) <= not( (sel_b_res0 and ex6_frac_res_ear(12) ) or (sel_b_res1 and ex6_frac_res_dly(12) ) ); +fwd_b_frac_pre1_13: rf1_b_frac_pre1_b(13) <= not( (sel_b_res0 and ex6_frac_res_ear(13) ) or (sel_b_res1 and ex6_frac_res_dly(13) ) ); +fwd_b_frac_pre1_14: rf1_b_frac_pre1_b(14) <= not( (sel_b_res0 and ex6_frac_res_ear(14) ) or (sel_b_res1 and ex6_frac_res_dly(14) ) ); +fwd_b_frac_pre1_15: rf1_b_frac_pre1_b(15) <= not( (sel_b_res0 and ex6_frac_res_ear(15) ) or (sel_b_res1 and ex6_frac_res_dly(15) ) ); +fwd_b_frac_pre1_16: rf1_b_frac_pre1_b(16) <= not( (sel_b_res0 and ex6_frac_res_ear(16) ) or (sel_b_res1 and ex6_frac_res_dly(16) ) ); +fwd_b_frac_pre1_17: rf1_b_frac_pre1_b(17) <= not( (sel_b_res0 and ex6_frac_res_ear(17) ) or (sel_b_res1 and ex6_frac_res_dly(17) ) ); +fwd_b_frac_pre1_18: rf1_b_frac_pre1_b(18) <= not( (sel_b_res0 and ex6_frac_res_ear(18) ) or (sel_b_res1 and ex6_frac_res_dly(18) ) ); +fwd_b_frac_pre1_19: rf1_b_frac_pre1_b(19) <= not( (sel_b_res0 and ex6_frac_res_ear(19) ) or (sel_b_res1 and ex6_frac_res_dly(19) ) ); +fwd_b_frac_pre1_20: rf1_b_frac_pre1_b(20) <= not( (sel_b_res0 and ex6_frac_res_ear(20) ) or (sel_b_res1 and ex6_frac_res_dly(20) ) ); +fwd_b_frac_pre1_21: rf1_b_frac_pre1_b(21) <= not( (sel_b_res0 and ex6_frac_res_ear(21) ) or (sel_b_res1 and ex6_frac_res_dly(21) ) ); +fwd_b_frac_pre1_22: rf1_b_frac_pre1_b(22) <= not( (sel_b_res0 and ex6_frac_res_ear(22) ) or (sel_b_res1 and ex6_frac_res_dly(22) ) ); +fwd_b_frac_pre1_23: rf1_b_frac_pre1_b(23) <= not( (sel_b_res0 and ex6_frac_res_ear(23) ) or (sel_b_res1 and ex6_frac_res_dly(23) ) ); +fwd_b_frac_pre1_24: rf1_b_frac_pre1_b(24) <= not( (sel_b_res0 and ex6_frac_res_ear(24) ) or (sel_b_res1 and ex6_frac_res_dly(24) ) ); +fwd_b_frac_pre1_25: rf1_b_frac_pre1_b(25) <= not( (sel_b_res0 and ex6_frac_res_ear(25) ) or (sel_b_res1 and ex6_frac_res_dly(25) ) ); +fwd_b_frac_pre1_26: rf1_b_frac_pre1_b(26) <= not( (sel_b_res0 and ex6_frac_res_ear(26) ) or (sel_b_res1 and ex6_frac_res_dly(26) ) ); +fwd_b_frac_pre1_27: rf1_b_frac_pre1_b(27) <= not( (sel_b_res0 and ex6_frac_res_ear(27) ) or (sel_b_res1 and ex6_frac_res_dly(27) ) ); +fwd_b_frac_pre1_28: rf1_b_frac_pre1_b(28) <= not( (sel_b_res0 and ex6_frac_res_ear(28) ) or (sel_b_res1 and ex6_frac_res_dly(28) ) ); +fwd_b_frac_pre1_29: rf1_b_frac_pre1_b(29) <= not( (sel_b_res0 and ex6_frac_res_ear(29) ) or (sel_b_res1 and ex6_frac_res_dly(29) ) ); +fwd_b_frac_pre1_30: rf1_b_frac_pre1_b(30) <= not( (sel_b_res0 and ex6_frac_res_ear(30) ) or (sel_b_res1 and ex6_frac_res_dly(30) ) ); +fwd_b_frac_pre1_31: rf1_b_frac_pre1_b(31) <= not( (sel_b_res0 and ex6_frac_res_ear(31) ) or (sel_b_res1 and ex6_frac_res_dly(31) ) ); +fwd_b_frac_pre1_32: rf1_b_frac_pre1_b(32) <= not( (sel_b_res0 and ex6_frac_res_ear(32) ) or (sel_b_res1 and ex6_frac_res_dly(32) ) ); +fwd_b_frac_pre1_33: rf1_b_frac_pre1_b(33) <= not( (sel_b_res0 and ex6_frac_res_ear(33) ) or (sel_b_res1 and ex6_frac_res_dly(33) ) ); +fwd_b_frac_pre1_34: rf1_b_frac_pre1_b(34) <= not( (sel_b_res0 and ex6_frac_res_ear(34) ) or (sel_b_res1 and ex6_frac_res_dly(34) ) ); +fwd_b_frac_pre1_35: rf1_b_frac_pre1_b(35) <= not( (sel_b_res0 and ex6_frac_res_ear(35) ) or (sel_b_res1 and ex6_frac_res_dly(35) ) ); +fwd_b_frac_pre1_36: rf1_b_frac_pre1_b(36) <= not( (sel_b_res0 and ex6_frac_res_ear(36) ) or (sel_b_res1 and ex6_frac_res_dly(36) ) ); +fwd_b_frac_pre1_37: rf1_b_frac_pre1_b(37) <= not( (sel_b_res0 and ex6_frac_res_ear(37) ) or (sel_b_res1 and ex6_frac_res_dly(37) ) ); +fwd_b_frac_pre1_38: rf1_b_frac_pre1_b(38) <= not( (sel_b_res0 and ex6_frac_res_ear(38) ) or (sel_b_res1 and ex6_frac_res_dly(38) ) ); +fwd_b_frac_pre1_39: rf1_b_frac_pre1_b(39) <= not( (sel_b_res0 and ex6_frac_res_ear(39) ) or (sel_b_res1 and ex6_frac_res_dly(39) ) ); +fwd_b_frac_pre1_40: rf1_b_frac_pre1_b(40) <= not( (sel_b_res0 and ex6_frac_res_ear(40) ) or (sel_b_res1 and ex6_frac_res_dly(40) ) ); +fwd_b_frac_pre1_41: rf1_b_frac_pre1_b(41) <= not( (sel_b_res0 and ex6_frac_res_ear(41) ) or (sel_b_res1 and ex6_frac_res_dly(41) ) ); +fwd_b_frac_pre1_42: rf1_b_frac_pre1_b(42) <= not( (sel_b_res0 and ex6_frac_res_ear(42) ) or (sel_b_res1 and ex6_frac_res_dly(42) ) ); +fwd_b_frac_pre1_43: rf1_b_frac_pre1_b(43) <= not( (sel_b_res0 and ex6_frac_res_ear(43) ) or (sel_b_res1 and ex6_frac_res_dly(43) ) ); +fwd_b_frac_pre1_44: rf1_b_frac_pre1_b(44) <= not( (sel_b_res0 and ex6_frac_res_ear(44) ) or (sel_b_res1 and ex6_frac_res_dly(44) ) ); +fwd_b_frac_pre1_45: rf1_b_frac_pre1_b(45) <= not( (sel_b_res0 and ex6_frac_res_ear(45) ) or (sel_b_res1 and ex6_frac_res_dly(45) ) ); +fwd_b_frac_pre1_46: rf1_b_frac_pre1_b(46) <= not( (sel_b_res0 and ex6_frac_res_ear(46) ) or (sel_b_res1 and ex6_frac_res_dly(46) ) ); +fwd_b_frac_pre1_47: rf1_b_frac_pre1_b(47) <= not( (sel_b_res0 and ex6_frac_res_ear(47) ) or (sel_b_res1 and ex6_frac_res_dly(47) ) ); +fwd_b_frac_pre1_48: rf1_b_frac_pre1_b(48) <= not( (sel_b_res0 and ex6_frac_res_ear(48) ) or (sel_b_res1 and ex6_frac_res_dly(48) ) ); +fwd_b_frac_pre1_49: rf1_b_frac_pre1_b(49) <= not( (sel_b_res0 and ex6_frac_res_ear(49) ) or (sel_b_res1 and ex6_frac_res_dly(49) ) ); +fwd_b_frac_pre1_50: rf1_b_frac_pre1_b(50) <= not( (sel_b_res0 and ex6_frac_res_ear(50) ) or (sel_b_res1 and ex6_frac_res_dly(50) ) ); +fwd_b_frac_pre1_51: rf1_b_frac_pre1_b(51) <= not( (sel_b_res0 and ex6_frac_res_ear(51) ) or (sel_b_res1 and ex6_frac_res_dly(51) ) ); +fwd_b_frac_pre1_52: rf1_b_frac_pre1_b(52) <= not( (sel_b_res0 and ex6_frac_res_ear(52) ) or (sel_b_res1 and ex6_frac_res_dly(52) ) ); + + + + + +fwd_a_frac_pre2_00: rf1_a_frac_pre2_b( 0) <= not( (sel_a_load0 and ex6_frac_lod_ear( 0) ) or (sel_a_load1 and ex6_frac_lod_dly( 0) ) ); +fwd_a_frac_pre2_01: rf1_a_frac_pre2_b( 1) <= not( (sel_a_load0 and ex6_frac_lod_ear( 1) ) or (sel_a_load1 and ex6_frac_lod_dly( 1) ) ); +fwd_a_frac_pre2_02: rf1_a_frac_pre2_b( 2) <= not( (sel_a_load0 and ex6_frac_lod_ear( 2) ) or (sel_a_load1 and ex6_frac_lod_dly( 2) ) ); +fwd_a_frac_pre2_03: rf1_a_frac_pre2_b( 3) <= not( (sel_a_load0 and ex6_frac_lod_ear( 3) ) or (sel_a_load1 and ex6_frac_lod_dly( 3) ) ); +fwd_a_frac_pre2_04: rf1_a_frac_pre2_b( 4) <= not( (sel_a_load0 and ex6_frac_lod_ear( 4) ) or (sel_a_load1 and ex6_frac_lod_dly( 4) ) ); +fwd_a_frac_pre2_05: rf1_a_frac_pre2_b( 5) <= not( (sel_a_load0 and ex6_frac_lod_ear( 5) ) or (sel_a_load1 and ex6_frac_lod_dly( 5) ) ); +fwd_a_frac_pre2_06: rf1_a_frac_pre2_b( 6) <= not( (sel_a_load0 and ex6_frac_lod_ear( 6) ) or (sel_a_load1 and ex6_frac_lod_dly( 6) ) ); +fwd_a_frac_pre2_07: rf1_a_frac_pre2_b( 7) <= not( (sel_a_load0 and ex6_frac_lod_ear( 7) ) or (sel_a_load1 and ex6_frac_lod_dly( 7) ) ); +fwd_a_frac_pre2_08: rf1_a_frac_pre2_b( 8) <= not( (sel_a_load0 and ex6_frac_lod_ear( 8) ) or (sel_a_load1 and ex6_frac_lod_dly( 8) ) ); +fwd_a_frac_pre2_09: rf1_a_frac_pre2_b( 9) <= not( (sel_a_load0 and ex6_frac_lod_ear( 9) ) or (sel_a_load1 and ex6_frac_lod_dly( 9) ) ); +fwd_a_frac_pre2_10: rf1_a_frac_pre2_b(10) <= not( (sel_a_load0 and ex6_frac_lod_ear(10) ) or (sel_a_load1 and ex6_frac_lod_dly(10) ) ); +fwd_a_frac_pre2_11: rf1_a_frac_pre2_b(11) <= not( (sel_a_load0 and ex6_frac_lod_ear(11) ) or (sel_a_load1 and ex6_frac_lod_dly(11) ) ); +fwd_a_frac_pre2_12: rf1_a_frac_pre2_b(12) <= not( (sel_a_load0 and ex6_frac_lod_ear(12) ) or (sel_a_load1 and ex6_frac_lod_dly(12) ) ); +fwd_a_frac_pre2_13: rf1_a_frac_pre2_b(13) <= not( (sel_a_load0 and ex6_frac_lod_ear(13) ) or (sel_a_load1 and ex6_frac_lod_dly(13) ) ); +fwd_a_frac_pre2_14: rf1_a_frac_pre2_b(14) <= not( (sel_a_load0 and ex6_frac_lod_ear(14) ) or (sel_a_load1 and ex6_frac_lod_dly(14) ) ); +fwd_a_frac_pre2_15: rf1_a_frac_pre2_b(15) <= not( (sel_a_load0 and ex6_frac_lod_ear(15) ) or (sel_a_load1 and ex6_frac_lod_dly(15) ) ); +fwd_a_frac_pre2_16: rf1_a_frac_pre2_b(16) <= not( (sel_a_load0 and ex6_frac_lod_ear(16) ) or (sel_a_load1 and ex6_frac_lod_dly(16) ) ); +fwd_a_frac_pre2_17: rf1_a_frac_pre2_b(17) <= not( (sel_a_load0 and ex6_frac_lod_ear(17) ) or (sel_a_load1 and ex6_frac_lod_dly(17) ) ); +fwd_a_frac_pre2_18: rf1_a_frac_pre2_b(18) <= not( (sel_a_load0 and ex6_frac_lod_ear(18) ) or (sel_a_load1 and ex6_frac_lod_dly(18) ) ); +fwd_a_frac_pre2_19: rf1_a_frac_pre2_b(19) <= not( (sel_a_load0 and ex6_frac_lod_ear(19) ) or (sel_a_load1 and ex6_frac_lod_dly(19) ) ); +fwd_a_frac_pre2_20: rf1_a_frac_pre2_b(20) <= not( (sel_a_load0 and ex6_frac_lod_ear(20) ) or (sel_a_load1 and ex6_frac_lod_dly(20) ) ); +fwd_a_frac_pre2_21: rf1_a_frac_pre2_b(21) <= not( (sel_a_load0 and ex6_frac_lod_ear(21) ) or (sel_a_load1 and ex6_frac_lod_dly(21) ) ); +fwd_a_frac_pre2_22: rf1_a_frac_pre2_b(22) <= not( (sel_a_load0 and ex6_frac_lod_ear(22) ) or (sel_a_load1 and ex6_frac_lod_dly(22) ) ); +fwd_a_frac_pre2_23: rf1_a_frac_pre2_b(23) <= not( (sel_a_load0 and ex6_frac_lod_ear(23) ) or (sel_a_load1 and ex6_frac_lod_dly(23) ) ); +fwd_a_frac_pre2_24: rf1_a_frac_pre2_b(24) <= not( (sel_a_load0 and ex6_frac_lod_ear(24) ) or (sel_a_load1 and ex6_frac_lod_dly(24) ) ); +fwd_a_frac_pre2_25: rf1_a_frac_pre2_b(25) <= not( (sel_a_load0 and ex6_frac_lod_ear(25) ) or (sel_a_load1 and ex6_frac_lod_dly(25) ) ); +fwd_a_frac_pre2_26: rf1_a_frac_pre2_b(26) <= not( (sel_a_load0 and ex6_frac_lod_ear(26) ) or (sel_a_load1 and ex6_frac_lod_dly(26) ) ); +fwd_a_frac_pre2_27: rf1_a_frac_pre2_b(27) <= not( (sel_a_load0 and ex6_frac_lod_ear(27) ) or (sel_a_load1 and ex6_frac_lod_dly(27) ) ); +fwd_a_frac_pre2_28: rf1_a_frac_pre2_b(28) <= not( (sel_a_load0 and ex6_frac_lod_ear(28) ) or (sel_a_load1 and ex6_frac_lod_dly(28) ) ); +fwd_a_frac_pre2_29: rf1_a_frac_pre2_b(29) <= not( (sel_a_load0 and ex6_frac_lod_ear(29) ) or (sel_a_load1 and ex6_frac_lod_dly(29) ) ); +fwd_a_frac_pre2_30: rf1_a_frac_pre2_b(30) <= not( (sel_a_load0 and ex6_frac_lod_ear(30) ) or (sel_a_load1 and ex6_frac_lod_dly(30) ) ); +fwd_a_frac_pre2_31: rf1_a_frac_pre2_b(31) <= not( (sel_a_load0 and ex6_frac_lod_ear(31) ) or (sel_a_load1 and ex6_frac_lod_dly(31) ) ); +fwd_a_frac_pre2_32: rf1_a_frac_pre2_b(32) <= not( (sel_a_load0 and ex6_frac_lod_ear(32) ) or (sel_a_load1 and ex6_frac_lod_dly(32) ) ); +fwd_a_frac_pre2_33: rf1_a_frac_pre2_b(33) <= not( (sel_a_load0 and ex6_frac_lod_ear(33) ) or (sel_a_load1 and ex6_frac_lod_dly(33) ) ); +fwd_a_frac_pre2_34: rf1_a_frac_pre2_b(34) <= not( (sel_a_load0 and ex6_frac_lod_ear(34) ) or (sel_a_load1 and ex6_frac_lod_dly(34) ) ); +fwd_a_frac_pre2_35: rf1_a_frac_pre2_b(35) <= not( (sel_a_load0 and ex6_frac_lod_ear(35) ) or (sel_a_load1 and ex6_frac_lod_dly(35) ) ); +fwd_a_frac_pre2_36: rf1_a_frac_pre2_b(36) <= not( (sel_a_load0 and ex6_frac_lod_ear(36) ) or (sel_a_load1 and ex6_frac_lod_dly(36) ) ); +fwd_a_frac_pre2_37: rf1_a_frac_pre2_b(37) <= not( (sel_a_load0 and ex6_frac_lod_ear(37) ) or (sel_a_load1 and ex6_frac_lod_dly(37) ) ); +fwd_a_frac_pre2_38: rf1_a_frac_pre2_b(38) <= not( (sel_a_load0 and ex6_frac_lod_ear(38) ) or (sel_a_load1 and ex6_frac_lod_dly(38) ) ); +fwd_a_frac_pre2_39: rf1_a_frac_pre2_b(39) <= not( (sel_a_load0 and ex6_frac_lod_ear(39) ) or (sel_a_load1 and ex6_frac_lod_dly(39) ) ); +fwd_a_frac_pre2_40: rf1_a_frac_pre2_b(40) <= not( (sel_a_load0 and ex6_frac_lod_ear(40) ) or (sel_a_load1 and ex6_frac_lod_dly(40) ) ); +fwd_a_frac_pre2_41: rf1_a_frac_pre2_b(41) <= not( (sel_a_load0 and ex6_frac_lod_ear(41) ) or (sel_a_load1 and ex6_frac_lod_dly(41) ) ); +fwd_a_frac_pre2_42: rf1_a_frac_pre2_b(42) <= not( (sel_a_load0 and ex6_frac_lod_ear(42) ) or (sel_a_load1 and ex6_frac_lod_dly(42) ) ); +fwd_a_frac_pre2_43: rf1_a_frac_pre2_b(43) <= not( (sel_a_load0 and ex6_frac_lod_ear(43) ) or (sel_a_load1 and ex6_frac_lod_dly(43) ) ); +fwd_a_frac_pre2_44: rf1_a_frac_pre2_b(44) <= not( (sel_a_load0 and ex6_frac_lod_ear(44) ) or (sel_a_load1 and ex6_frac_lod_dly(44) ) ); +fwd_a_frac_pre2_45: rf1_a_frac_pre2_b(45) <= not( (sel_a_load0 and ex6_frac_lod_ear(45) ) or (sel_a_load1 and ex6_frac_lod_dly(45) ) ); +fwd_a_frac_pre2_46: rf1_a_frac_pre2_b(46) <= not( (sel_a_load0 and ex6_frac_lod_ear(46) ) or (sel_a_load1 and ex6_frac_lod_dly(46) ) ); +fwd_a_frac_pre2_47: rf1_a_frac_pre2_b(47) <= not( (sel_a_load0 and ex6_frac_lod_ear(47) ) or (sel_a_load1 and ex6_frac_lod_dly(47) ) ); +fwd_a_frac_pre2_48: rf1_a_frac_pre2_b(48) <= not( (sel_a_load0 and ex6_frac_lod_ear(48) ) or (sel_a_load1 and ex6_frac_lod_dly(48) ) ); +fwd_a_frac_pre2_49: rf1_a_frac_pre2_b(49) <= not( (sel_a_load0 and ex6_frac_lod_ear(49) ) or (sel_a_load1 and ex6_frac_lod_dly(49) ) ); +fwd_a_frac_pre2_50: rf1_a_frac_pre2_b(50) <= not( (sel_a_load0 and ex6_frac_lod_ear(50) ) or (sel_a_load1 and ex6_frac_lod_dly(50) ) ); +fwd_a_frac_pre2_51: rf1_a_frac_pre2_b(51) <= not( (sel_a_load0 and ex6_frac_lod_ear(51) ) or (sel_a_load1 and ex6_frac_lod_dly(51) ) ); +fwd_a_frac_pre2_52: rf1_a_frac_pre2_b(52) <= not( (sel_a_load0 and ex6_frac_lod_ear(52) ) or (sel_a_load1 and ex6_frac_lod_dly(52) ) ); + +fwd_c_frac_pre2_00: rf1_c_frac_pre2_b( 0) <= not( (sel_c_load0 and ex6_frac_lod_ear( 0) ) or (sel_c_load1 and ex6_frac_lod_dly( 0) ) ); +fwd_c_frac_pre2_01: rf1_c_frac_pre2_b( 1) <= not( (sel_c_load0 and ex6_frac_lod_ear( 1) ) or (sel_c_load1 and ex6_frac_lod_dly( 1) ) ); +fwd_c_frac_pre2_02: rf1_c_frac_pre2_b( 2) <= not( (sel_c_load0 and ex6_frac_lod_ear( 2) ) or (sel_c_load1 and ex6_frac_lod_dly( 2) ) ); +fwd_c_frac_pre2_03: rf1_c_frac_pre2_b( 3) <= not( (sel_c_load0 and ex6_frac_lod_ear( 3) ) or (sel_c_load1 and ex6_frac_lod_dly( 3) ) ); +fwd_c_frac_pre2_04: rf1_c_frac_pre2_b( 4) <= not( (sel_c_load0 and ex6_frac_lod_ear( 4) ) or (sel_c_load1 and ex6_frac_lod_dly( 4) ) ); +fwd_c_frac_pre2_05: rf1_c_frac_pre2_b( 5) <= not( (sel_c_load0 and ex6_frac_lod_ear( 5) ) or (sel_c_load1 and ex6_frac_lod_dly( 5) ) ); +fwd_c_frac_pre2_06: rf1_c_frac_pre2_b( 6) <= not( (sel_c_load0 and ex6_frac_lod_ear( 6) ) or (sel_c_load1 and ex6_frac_lod_dly( 6) ) ); +fwd_c_frac_pre2_07: rf1_c_frac_pre2_b( 7) <= not( (sel_c_load0 and ex6_frac_lod_ear( 7) ) or (sel_c_load1 and ex6_frac_lod_dly( 7) ) ); +fwd_c_frac_pre2_08: rf1_c_frac_pre2_b( 8) <= not( (sel_c_load0 and ex6_frac_lod_ear( 8) ) or (sel_c_load1 and ex6_frac_lod_dly( 8) ) ); +fwd_c_frac_pre2_09: rf1_c_frac_pre2_b( 9) <= not( (sel_c_load0 and ex6_frac_lod_ear( 9) ) or (sel_c_load1 and ex6_frac_lod_dly( 9) ) ); +fwd_c_frac_pre2_10: rf1_c_frac_pre2_b(10) <= not( (sel_c_load0 and ex6_frac_lod_ear(10) ) or (sel_c_load1 and ex6_frac_lod_dly(10) ) ); +fwd_c_frac_pre2_11: rf1_c_frac_pre2_b(11) <= not( (sel_c_load0 and ex6_frac_lod_ear(11) ) or (sel_c_load1 and ex6_frac_lod_dly(11) ) ); +fwd_c_frac_pre2_12: rf1_c_frac_pre2_b(12) <= not( (sel_c_load0 and ex6_frac_lod_ear(12) ) or (sel_c_load1 and ex6_frac_lod_dly(12) ) ); +fwd_c_frac_pre2_13: rf1_c_frac_pre2_b(13) <= not( (sel_c_load0 and ex6_frac_lod_ear(13) ) or (sel_c_load1 and ex6_frac_lod_dly(13) ) ); +fwd_c_frac_pre2_14: rf1_c_frac_pre2_b(14) <= not( (sel_c_load0 and ex6_frac_lod_ear(14) ) or (sel_c_load1 and ex6_frac_lod_dly(14) ) ); +fwd_c_frac_pre2_15: rf1_c_frac_pre2_b(15) <= not( (sel_c_load0 and ex6_frac_lod_ear(15) ) or (sel_c_load1 and ex6_frac_lod_dly(15) ) ); +fwd_c_frac_pre2_16: rf1_c_frac_pre2_b(16) <= not( (sel_c_load0 and ex6_frac_lod_ear(16) ) or (sel_c_load1 and ex6_frac_lod_dly(16) ) ); +fwd_c_frac_pre2_17: rf1_c_frac_pre2_b(17) <= not( (sel_c_load0 and ex6_frac_lod_ear(17) ) or (sel_c_load1 and ex6_frac_lod_dly(17) ) ); +fwd_c_frac_pre2_18: rf1_c_frac_pre2_b(18) <= not( (sel_c_load0 and ex6_frac_lod_ear(18) ) or (sel_c_load1 and ex6_frac_lod_dly(18) ) ); +fwd_c_frac_pre2_19: rf1_c_frac_pre2_b(19) <= not( (sel_c_load0 and ex6_frac_lod_ear(19) ) or (sel_c_load1 and ex6_frac_lod_dly(19) ) ); +fwd_c_frac_pre2_20: rf1_c_frac_pre2_b(20) <= not( (sel_c_load0 and ex6_frac_lod_ear(20) ) or (sel_c_load1 and ex6_frac_lod_dly(20) ) ); +fwd_c_frac_pre2_21: rf1_c_frac_pre2_b(21) <= not( (sel_c_load0 and ex6_frac_lod_ear(21) ) or (sel_c_load1 and ex6_frac_lod_dly(21) ) ); +fwd_c_frac_pre2_22: rf1_c_frac_pre2_b(22) <= not( (sel_c_load0 and ex6_frac_lod_ear(22) ) or (sel_c_load1 and ex6_frac_lod_dly(22) ) ); +fwd_c_frac_pre2_23: rf1_c_frac_pre2_b(23) <= not( (sel_c_load0 and ex6_frac_lod_ear(23) ) or (sel_c_load1 and ex6_frac_lod_dly(23) ) ); +fwd_c_frac_pre2_24: rf1_c_frac_pre2_b(24) <= not( (sel_c_load0 and ex6_frac_lod_ear(24) ) or (sel_c_load1 and ex6_frac_lod_dly(24) ) ); +fwd_c_frac_pre2_25: rf1_c_frac_pre2_b(25) <= not( (sel_c_load0 and ex6_frac_lod_ear(25) ) or (sel_c_load1 and ex6_frac_lod_dly(25) ) ); +fwd_c_frac_pre2_26: rf1_c_frac_pre2_b(26) <= not( (sel_c_load0 and ex6_frac_lod_ear(26) ) or (sel_c_load1 and ex6_frac_lod_dly(26) ) ); +fwd_c_frac_pre2_27: rf1_c_frac_pre2_b(27) <= not( (sel_c_load0 and ex6_frac_lod_ear(27) ) or (sel_c_load1 and ex6_frac_lod_dly(27) ) ); +fwd_c_frac_pre2_28: rf1_c_frac_pre2_b(28) <= not( (sel_c_load0 and ex6_frac_lod_ear(28) ) or (sel_c_load1 and ex6_frac_lod_dly(28) ) ); +fwd_c_frac_pre2_29: rf1_c_frac_pre2_b(29) <= not( (sel_c_load0 and ex6_frac_lod_ear(29) ) or (sel_c_load1 and ex6_frac_lod_dly(29) ) ); +fwd_c_frac_pre2_30: rf1_c_frac_pre2_b(30) <= not( (sel_c_load0 and ex6_frac_lod_ear(30) ) or (sel_c_load1 and ex6_frac_lod_dly(30) ) ); +fwd_c_frac_pre2_31: rf1_c_frac_pre2_b(31) <= not( (sel_c_load0 and ex6_frac_lod_ear(31) ) or (sel_c_load1 and ex6_frac_lod_dly(31) ) ); +fwd_c_frac_pre2_32: rf1_c_frac_pre2_b(32) <= not( (sel_c_load0 and ex6_frac_lod_ear(32) ) or (sel_c_load1 and ex6_frac_lod_dly(32) ) ); +fwd_c_frac_pre2_33: rf1_c_frac_pre2_b(33) <= not( (sel_c_load0 and ex6_frac_lod_ear(33) ) or (sel_c_load1 and ex6_frac_lod_dly(33) ) ); +fwd_c_frac_pre2_34: rf1_c_frac_pre2_b(34) <= not( (sel_c_load0 and ex6_frac_lod_ear(34) ) or (sel_c_load1 and ex6_frac_lod_dly(34) ) ); +fwd_c_frac_pre2_35: rf1_c_frac_pre2_b(35) <= not( (sel_c_load0 and ex6_frac_lod_ear(35) ) or (sel_c_load1 and ex6_frac_lod_dly(35) ) ); +fwd_c_frac_pre2_36: rf1_c_frac_pre2_b(36) <= not( (sel_c_load0 and ex6_frac_lod_ear(36) ) or (sel_c_load1 and ex6_frac_lod_dly(36) ) ); +fwd_c_frac_pre2_37: rf1_c_frac_pre2_b(37) <= not( (sel_c_load0 and ex6_frac_lod_ear(37) ) or (sel_c_load1 and ex6_frac_lod_dly(37) ) ); +fwd_c_frac_pre2_38: rf1_c_frac_pre2_b(38) <= not( (sel_c_load0 and ex6_frac_lod_ear(38) ) or (sel_c_load1 and ex6_frac_lod_dly(38) ) ); +fwd_c_frac_pre2_39: rf1_c_frac_pre2_b(39) <= not( (sel_c_load0 and ex6_frac_lod_ear(39) ) or (sel_c_load1 and ex6_frac_lod_dly(39) ) ); +fwd_c_frac_pre2_40: rf1_c_frac_pre2_b(40) <= not( (sel_c_load0 and ex6_frac_lod_ear(40) ) or (sel_c_load1 and ex6_frac_lod_dly(40) ) ); +fwd_c_frac_pre2_41: rf1_c_frac_pre2_b(41) <= not( (sel_c_load0 and ex6_frac_lod_ear(41) ) or (sel_c_load1 and ex6_frac_lod_dly(41) ) ); +fwd_c_frac_pre2_42: rf1_c_frac_pre2_b(42) <= not( (sel_c_load0 and ex6_frac_lod_ear(42) ) or (sel_c_load1 and ex6_frac_lod_dly(42) ) ); +fwd_c_frac_pre2_43: rf1_c_frac_pre2_b(43) <= not( (sel_c_load0 and ex6_frac_lod_ear(43) ) or (sel_c_load1 and ex6_frac_lod_dly(43) ) ); +fwd_c_frac_pre2_44: rf1_c_frac_pre2_b(44) <= not( (sel_c_load0 and ex6_frac_lod_ear(44) ) or (sel_c_load1 and ex6_frac_lod_dly(44) ) ); +fwd_c_frac_pre2_45: rf1_c_frac_pre2_b(45) <= not( (sel_c_load0 and ex6_frac_lod_ear(45) ) or (sel_c_load1 and ex6_frac_lod_dly(45) ) ); +fwd_c_frac_pre2_46: rf1_c_frac_pre2_b(46) <= not( (sel_c_load0 and ex6_frac_lod_ear(46) ) or (sel_c_load1 and ex6_frac_lod_dly(46) ) ); +fwd_c_frac_pre2_47: rf1_c_frac_pre2_b(47) <= not( (sel_c_load0 and ex6_frac_lod_ear(47) ) or (sel_c_load1 and ex6_frac_lod_dly(47) ) ); +fwd_c_frac_pre2_48: rf1_c_frac_pre2_b(48) <= not( (sel_c_load0 and ex6_frac_lod_ear(48) ) or (sel_c_load1 and ex6_frac_lod_dly(48) ) ); +fwd_c_frac_pre2_49: rf1_c_frac_pre2_b(49) <= not( (sel_c_load0 and ex6_frac_lod_ear(49) ) or (sel_c_load1 and ex6_frac_lod_dly(49) ) ); +fwd_c_frac_pre2_50: rf1_c_frac_pre2_b(50) <= not( (sel_c_load0 and ex6_frac_lod_ear(50) ) or (sel_c_load1 and ex6_frac_lod_dly(50) ) ); +fwd_c_frac_pre2_51: rf1_c_frac_pre2_b(51) <= not( (sel_c_load0 and ex6_frac_lod_ear(51) ) or (sel_c_load1 and ex6_frac_lod_dly(51) ) ); +fwd_c_frac_pre2_52: rf1_c_frac_pre2_b(52) <= not( (sel_c_load0 and ex6_frac_lod_ear(52) ) or (sel_c_load1 and ex6_frac_lod_dly(52) ) ); + +fwd_b_frac_pre2_00: rf1_b_frac_pre2_b( 0) <= not( (sel_b_load0 and ex6_frac_lod_ear( 0) ) or (sel_b_load1 and ex6_frac_lod_dly( 0) ) ); +fwd_b_frac_pre2_01: rf1_b_frac_pre2_b( 1) <= not( (sel_b_load0 and ex6_frac_lod_ear( 1) ) or (sel_b_load1 and ex6_frac_lod_dly( 1) ) ); +fwd_b_frac_pre2_02: rf1_b_frac_pre2_b( 2) <= not( (sel_b_load0 and ex6_frac_lod_ear( 2) ) or (sel_b_load1 and ex6_frac_lod_dly( 2) ) ); +fwd_b_frac_pre2_03: rf1_b_frac_pre2_b( 3) <= not( (sel_b_load0 and ex6_frac_lod_ear( 3) ) or (sel_b_load1 and ex6_frac_lod_dly( 3) ) ); +fwd_b_frac_pre2_04: rf1_b_frac_pre2_b( 4) <= not( (sel_b_load0 and ex6_frac_lod_ear( 4) ) or (sel_b_load1 and ex6_frac_lod_dly( 4) ) ); +fwd_b_frac_pre2_05: rf1_b_frac_pre2_b( 5) <= not( (sel_b_load0 and ex6_frac_lod_ear( 5) ) or (sel_b_load1 and ex6_frac_lod_dly( 5) ) ); +fwd_b_frac_pre2_06: rf1_b_frac_pre2_b( 6) <= not( (sel_b_load0 and ex6_frac_lod_ear( 6) ) or (sel_b_load1 and ex6_frac_lod_dly( 6) ) ); +fwd_b_frac_pre2_07: rf1_b_frac_pre2_b( 7) <= not( (sel_b_load0 and ex6_frac_lod_ear( 7) ) or (sel_b_load1 and ex6_frac_lod_dly( 7) ) ); +fwd_b_frac_pre2_08: rf1_b_frac_pre2_b( 8) <= not( (sel_b_load0 and ex6_frac_lod_ear( 8) ) or (sel_b_load1 and ex6_frac_lod_dly( 8) ) ); +fwd_b_frac_pre2_09: rf1_b_frac_pre2_b( 9) <= not( (sel_b_load0 and ex6_frac_lod_ear( 9) ) or (sel_b_load1 and ex6_frac_lod_dly( 9) ) ); +fwd_b_frac_pre2_10: rf1_b_frac_pre2_b(10) <= not( (sel_b_load0 and ex6_frac_lod_ear(10) ) or (sel_b_load1 and ex6_frac_lod_dly(10) ) ); +fwd_b_frac_pre2_11: rf1_b_frac_pre2_b(11) <= not( (sel_b_load0 and ex6_frac_lod_ear(11) ) or (sel_b_load1 and ex6_frac_lod_dly(11) ) ); +fwd_b_frac_pre2_12: rf1_b_frac_pre2_b(12) <= not( (sel_b_load0 and ex6_frac_lod_ear(12) ) or (sel_b_load1 and ex6_frac_lod_dly(12) ) ); +fwd_b_frac_pre2_13: rf1_b_frac_pre2_b(13) <= not( (sel_b_load0 and ex6_frac_lod_ear(13) ) or (sel_b_load1 and ex6_frac_lod_dly(13) ) ); +fwd_b_frac_pre2_14: rf1_b_frac_pre2_b(14) <= not( (sel_b_load0 and ex6_frac_lod_ear(14) ) or (sel_b_load1 and ex6_frac_lod_dly(14) ) ); +fwd_b_frac_pre2_15: rf1_b_frac_pre2_b(15) <= not( (sel_b_load0 and ex6_frac_lod_ear(15) ) or (sel_b_load1 and ex6_frac_lod_dly(15) ) ); +fwd_b_frac_pre2_16: rf1_b_frac_pre2_b(16) <= not( (sel_b_load0 and ex6_frac_lod_ear(16) ) or (sel_b_load1 and ex6_frac_lod_dly(16) ) ); +fwd_b_frac_pre2_17: rf1_b_frac_pre2_b(17) <= not( (sel_b_load0 and ex6_frac_lod_ear(17) ) or (sel_b_load1 and ex6_frac_lod_dly(17) ) ); +fwd_b_frac_pre2_18: rf1_b_frac_pre2_b(18) <= not( (sel_b_load0 and ex6_frac_lod_ear(18) ) or (sel_b_load1 and ex6_frac_lod_dly(18) ) ); +fwd_b_frac_pre2_19: rf1_b_frac_pre2_b(19) <= not( (sel_b_load0 and ex6_frac_lod_ear(19) ) or (sel_b_load1 and ex6_frac_lod_dly(19) ) ); +fwd_b_frac_pre2_20: rf1_b_frac_pre2_b(20) <= not( (sel_b_load0 and ex6_frac_lod_ear(20) ) or (sel_b_load1 and ex6_frac_lod_dly(20) ) ); +fwd_b_frac_pre2_21: rf1_b_frac_pre2_b(21) <= not( (sel_b_load0 and ex6_frac_lod_ear(21) ) or (sel_b_load1 and ex6_frac_lod_dly(21) ) ); +fwd_b_frac_pre2_22: rf1_b_frac_pre2_b(22) <= not( (sel_b_load0 and ex6_frac_lod_ear(22) ) or (sel_b_load1 and ex6_frac_lod_dly(22) ) ); +fwd_b_frac_pre2_23: rf1_b_frac_pre2_b(23) <= not( (sel_b_load0 and ex6_frac_lod_ear(23) ) or (sel_b_load1 and ex6_frac_lod_dly(23) ) ); +fwd_b_frac_pre2_24: rf1_b_frac_pre2_b(24) <= not( (sel_b_load0 and ex6_frac_lod_ear(24) ) or (sel_b_load1 and ex6_frac_lod_dly(24) ) ); +fwd_b_frac_pre2_25: rf1_b_frac_pre2_b(25) <= not( (sel_b_load0 and ex6_frac_lod_ear(25) ) or (sel_b_load1 and ex6_frac_lod_dly(25) ) ); +fwd_b_frac_pre2_26: rf1_b_frac_pre2_b(26) <= not( (sel_b_load0 and ex6_frac_lod_ear(26) ) or (sel_b_load1 and ex6_frac_lod_dly(26) ) ); +fwd_b_frac_pre2_27: rf1_b_frac_pre2_b(27) <= not( (sel_b_load0 and ex6_frac_lod_ear(27) ) or (sel_b_load1 and ex6_frac_lod_dly(27) ) ); +fwd_b_frac_pre2_28: rf1_b_frac_pre2_b(28) <= not( (sel_b_load0 and ex6_frac_lod_ear(28) ) or (sel_b_load1 and ex6_frac_lod_dly(28) ) ); +fwd_b_frac_pre2_29: rf1_b_frac_pre2_b(29) <= not( (sel_b_load0 and ex6_frac_lod_ear(29) ) or (sel_b_load1 and ex6_frac_lod_dly(29) ) ); +fwd_b_frac_pre2_30: rf1_b_frac_pre2_b(30) <= not( (sel_b_load0 and ex6_frac_lod_ear(30) ) or (sel_b_load1 and ex6_frac_lod_dly(30) ) ); +fwd_b_frac_pre2_31: rf1_b_frac_pre2_b(31) <= not( (sel_b_load0 and ex6_frac_lod_ear(31) ) or (sel_b_load1 and ex6_frac_lod_dly(31) ) ); +fwd_b_frac_pre2_32: rf1_b_frac_pre2_b(32) <= not( (sel_b_load0 and ex6_frac_lod_ear(32) ) or (sel_b_load1 and ex6_frac_lod_dly(32) ) ); +fwd_b_frac_pre2_33: rf1_b_frac_pre2_b(33) <= not( (sel_b_load0 and ex6_frac_lod_ear(33) ) or (sel_b_load1 and ex6_frac_lod_dly(33) ) ); +fwd_b_frac_pre2_34: rf1_b_frac_pre2_b(34) <= not( (sel_b_load0 and ex6_frac_lod_ear(34) ) or (sel_b_load1 and ex6_frac_lod_dly(34) ) ); +fwd_b_frac_pre2_35: rf1_b_frac_pre2_b(35) <= not( (sel_b_load0 and ex6_frac_lod_ear(35) ) or (sel_b_load1 and ex6_frac_lod_dly(35) ) ); +fwd_b_frac_pre2_36: rf1_b_frac_pre2_b(36) <= not( (sel_b_load0 and ex6_frac_lod_ear(36) ) or (sel_b_load1 and ex6_frac_lod_dly(36) ) ); +fwd_b_frac_pre2_37: rf1_b_frac_pre2_b(37) <= not( (sel_b_load0 and ex6_frac_lod_ear(37) ) or (sel_b_load1 and ex6_frac_lod_dly(37) ) ); +fwd_b_frac_pre2_38: rf1_b_frac_pre2_b(38) <= not( (sel_b_load0 and ex6_frac_lod_ear(38) ) or (sel_b_load1 and ex6_frac_lod_dly(38) ) ); +fwd_b_frac_pre2_39: rf1_b_frac_pre2_b(39) <= not( (sel_b_load0 and ex6_frac_lod_ear(39) ) or (sel_b_load1 and ex6_frac_lod_dly(39) ) ); +fwd_b_frac_pre2_40: rf1_b_frac_pre2_b(40) <= not( (sel_b_load0 and ex6_frac_lod_ear(40) ) or (sel_b_load1 and ex6_frac_lod_dly(40) ) ); +fwd_b_frac_pre2_41: rf1_b_frac_pre2_b(41) <= not( (sel_b_load0 and ex6_frac_lod_ear(41) ) or (sel_b_load1 and ex6_frac_lod_dly(41) ) ); +fwd_b_frac_pre2_42: rf1_b_frac_pre2_b(42) <= not( (sel_b_load0 and ex6_frac_lod_ear(42) ) or (sel_b_load1 and ex6_frac_lod_dly(42) ) ); +fwd_b_frac_pre2_43: rf1_b_frac_pre2_b(43) <= not( (sel_b_load0 and ex6_frac_lod_ear(43) ) or (sel_b_load1 and ex6_frac_lod_dly(43) ) ); +fwd_b_frac_pre2_44: rf1_b_frac_pre2_b(44) <= not( (sel_b_load0 and ex6_frac_lod_ear(44) ) or (sel_b_load1 and ex6_frac_lod_dly(44) ) ); +fwd_b_frac_pre2_45: rf1_b_frac_pre2_b(45) <= not( (sel_b_load0 and ex6_frac_lod_ear(45) ) or (sel_b_load1 and ex6_frac_lod_dly(45) ) ); +fwd_b_frac_pre2_46: rf1_b_frac_pre2_b(46) <= not( (sel_b_load0 and ex6_frac_lod_ear(46) ) or (sel_b_load1 and ex6_frac_lod_dly(46) ) ); +fwd_b_frac_pre2_47: rf1_b_frac_pre2_b(47) <= not( (sel_b_load0 and ex6_frac_lod_ear(47) ) or (sel_b_load1 and ex6_frac_lod_dly(47) ) ); +fwd_b_frac_pre2_48: rf1_b_frac_pre2_b(48) <= not( (sel_b_load0 and ex6_frac_lod_ear(48) ) or (sel_b_load1 and ex6_frac_lod_dly(48) ) ); +fwd_b_frac_pre2_49: rf1_b_frac_pre2_b(49) <= not( (sel_b_load0 and ex6_frac_lod_ear(49) ) or (sel_b_load1 and ex6_frac_lod_dly(49) ) ); +fwd_b_frac_pre2_50: rf1_b_frac_pre2_b(50) <= not( (sel_b_load0 and ex6_frac_lod_ear(50) ) or (sel_b_load1 and ex6_frac_lod_dly(50) ) ); +fwd_b_frac_pre2_51: rf1_b_frac_pre2_b(51) <= not( (sel_b_load0 and ex6_frac_lod_ear(51) ) or (sel_b_load1 and ex6_frac_lod_dly(51) ) ); +fwd_b_frac_pre2_52: rf1_b_frac_pre2_b(52) <= not( (sel_b_load0 and ex6_frac_lod_ear(52) ) or (sel_b_load1 and ex6_frac_lod_dly(52) ) ); + + +fwd_a_frac_pre_00: rf1_a_frac_pre( 0) <= not( rf1_a_frac_pre1_b( 0) and rf1_a_frac_pre2_b( 0) ); +fwd_a_frac_pre_01: rf1_a_frac_pre( 1) <= not( rf1_a_frac_pre1_b( 1) and rf1_a_frac_pre2_b( 1) ); +fwd_a_frac_pre_02: rf1_a_frac_pre( 2) <= not( rf1_a_frac_pre1_b( 2) and rf1_a_frac_pre2_b( 2) ); +fwd_a_frac_pre_03: rf1_a_frac_pre( 3) <= not( rf1_a_frac_pre1_b( 3) and rf1_a_frac_pre2_b( 3) ); +fwd_a_frac_pre_04: rf1_a_frac_pre( 4) <= not( rf1_a_frac_pre1_b( 4) and rf1_a_frac_pre2_b( 4) ); +fwd_a_frac_pre_05: rf1_a_frac_pre( 5) <= not( rf1_a_frac_pre1_b( 5) and rf1_a_frac_pre2_b( 5) ); +fwd_a_frac_pre_06: rf1_a_frac_pre( 6) <= not( rf1_a_frac_pre1_b( 6) and rf1_a_frac_pre2_b( 6) ); +fwd_a_frac_pre_07: rf1_a_frac_pre( 7) <= not( rf1_a_frac_pre1_b( 7) and rf1_a_frac_pre2_b( 7) ); +fwd_a_frac_pre_08: rf1_a_frac_pre( 8) <= not( rf1_a_frac_pre1_b( 8) and rf1_a_frac_pre2_b( 8) ); +fwd_a_frac_pre_09: rf1_a_frac_pre( 9) <= not( rf1_a_frac_pre1_b( 9) and rf1_a_frac_pre2_b( 9) ); +fwd_a_frac_pre_10: rf1_a_frac_pre(10) <= not( rf1_a_frac_pre1_b(10) and rf1_a_frac_pre2_b(10) ); +fwd_a_frac_pre_11: rf1_a_frac_pre(11) <= not( rf1_a_frac_pre1_b(11) and rf1_a_frac_pre2_b(11) ); +fwd_a_frac_pre_12: rf1_a_frac_pre(12) <= not( rf1_a_frac_pre1_b(12) and rf1_a_frac_pre2_b(12) ); +fwd_a_frac_pre_13: rf1_a_frac_pre(13) <= not( rf1_a_frac_pre1_b(13) and rf1_a_frac_pre2_b(13) ); +fwd_a_frac_pre_14: rf1_a_frac_pre(14) <= not( rf1_a_frac_pre1_b(14) and rf1_a_frac_pre2_b(14) ); +fwd_a_frac_pre_15: rf1_a_frac_pre(15) <= not( rf1_a_frac_pre1_b(15) and rf1_a_frac_pre2_b(15) ); +fwd_a_frac_pre_16: rf1_a_frac_pre(16) <= not( rf1_a_frac_pre1_b(16) and rf1_a_frac_pre2_b(16) ); +fwd_a_frac_pre_17: rf1_a_frac_pre(17) <= not( rf1_a_frac_pre1_b(17) and rf1_a_frac_pre2_b(17) ); +fwd_a_frac_pre_18: rf1_a_frac_pre(18) <= not( rf1_a_frac_pre1_b(18) and rf1_a_frac_pre2_b(18) ); +fwd_a_frac_pre_19: rf1_a_frac_pre(19) <= not( rf1_a_frac_pre1_b(19) and rf1_a_frac_pre2_b(19) ); +fwd_a_frac_pre_20: rf1_a_frac_pre(20) <= not( rf1_a_frac_pre1_b(20) and rf1_a_frac_pre2_b(20) ); +fwd_a_frac_pre_21: rf1_a_frac_pre(21) <= not( rf1_a_frac_pre1_b(21) and rf1_a_frac_pre2_b(21) ); +fwd_a_frac_pre_22: rf1_a_frac_pre(22) <= not( rf1_a_frac_pre1_b(22) and rf1_a_frac_pre2_b(22) ); +fwd_a_frac_pre_23: rf1_a_frac_pre(23) <= not( rf1_a_frac_pre1_b(23) and rf1_a_frac_pre2_b(23) ); +fwd_a_frac_pre_24: rf1_a_frac_pre(24) <= not( rf1_a_frac_pre1_b(24) and rf1_a_frac_pre2_b(24) ); +fwd_a_frac_pre_25: rf1_a_frac_pre(25) <= not( rf1_a_frac_pre1_b(25) and rf1_a_frac_pre2_b(25) ); +fwd_a_frac_pre_26: rf1_a_frac_pre(26) <= not( rf1_a_frac_pre1_b(26) and rf1_a_frac_pre2_b(26) ); +fwd_a_frac_pre_27: rf1_a_frac_pre(27) <= not( rf1_a_frac_pre1_b(27) and rf1_a_frac_pre2_b(27) ); +fwd_a_frac_pre_28: rf1_a_frac_pre(28) <= not( rf1_a_frac_pre1_b(28) and rf1_a_frac_pre2_b(28) ); +fwd_a_frac_pre_29: rf1_a_frac_pre(29) <= not( rf1_a_frac_pre1_b(29) and rf1_a_frac_pre2_b(29) ); +fwd_a_frac_pre_30: rf1_a_frac_pre(30) <= not( rf1_a_frac_pre1_b(30) and rf1_a_frac_pre2_b(30) ); +fwd_a_frac_pre_31: rf1_a_frac_pre(31) <= not( rf1_a_frac_pre1_b(31) and rf1_a_frac_pre2_b(31) ); +fwd_a_frac_pre_32: rf1_a_frac_pre(32) <= not( rf1_a_frac_pre1_b(32) and rf1_a_frac_pre2_b(32) ); +fwd_a_frac_pre_33: rf1_a_frac_pre(33) <= not( rf1_a_frac_pre1_b(33) and rf1_a_frac_pre2_b(33) ); +fwd_a_frac_pre_34: rf1_a_frac_pre(34) <= not( rf1_a_frac_pre1_b(34) and rf1_a_frac_pre2_b(34) ); +fwd_a_frac_pre_35: rf1_a_frac_pre(35) <= not( rf1_a_frac_pre1_b(35) and rf1_a_frac_pre2_b(35) ); +fwd_a_frac_pre_36: rf1_a_frac_pre(36) <= not( rf1_a_frac_pre1_b(36) and rf1_a_frac_pre2_b(36) ); +fwd_a_frac_pre_37: rf1_a_frac_pre(37) <= not( rf1_a_frac_pre1_b(37) and rf1_a_frac_pre2_b(37) ); +fwd_a_frac_pre_38: rf1_a_frac_pre(38) <= not( rf1_a_frac_pre1_b(38) and rf1_a_frac_pre2_b(38) ); +fwd_a_frac_pre_39: rf1_a_frac_pre(39) <= not( rf1_a_frac_pre1_b(39) and rf1_a_frac_pre2_b(39) ); +fwd_a_frac_pre_40: rf1_a_frac_pre(40) <= not( rf1_a_frac_pre1_b(40) and rf1_a_frac_pre2_b(40) ); +fwd_a_frac_pre_41: rf1_a_frac_pre(41) <= not( rf1_a_frac_pre1_b(41) and rf1_a_frac_pre2_b(41) ); +fwd_a_frac_pre_42: rf1_a_frac_pre(42) <= not( rf1_a_frac_pre1_b(42) and rf1_a_frac_pre2_b(42) ); +fwd_a_frac_pre_43: rf1_a_frac_pre(43) <= not( rf1_a_frac_pre1_b(43) and rf1_a_frac_pre2_b(43) ); +fwd_a_frac_pre_44: rf1_a_frac_pre(44) <= not( rf1_a_frac_pre1_b(44) and rf1_a_frac_pre2_b(44) ); +fwd_a_frac_pre_45: rf1_a_frac_pre(45) <= not( rf1_a_frac_pre1_b(45) and rf1_a_frac_pre2_b(45) ); +fwd_a_frac_pre_46: rf1_a_frac_pre(46) <= not( rf1_a_frac_pre1_b(46) and rf1_a_frac_pre2_b(46) ); +fwd_a_frac_pre_47: rf1_a_frac_pre(47) <= not( rf1_a_frac_pre1_b(47) and rf1_a_frac_pre2_b(47) ); +fwd_a_frac_pre_48: rf1_a_frac_pre(48) <= not( rf1_a_frac_pre1_b(48) and rf1_a_frac_pre2_b(48) ); +fwd_a_frac_pre_49: rf1_a_frac_pre(49) <= not( rf1_a_frac_pre1_b(49) and rf1_a_frac_pre2_b(49) ); +fwd_a_frac_pre_50: rf1_a_frac_pre(50) <= not( rf1_a_frac_pre1_b(50) and rf1_a_frac_pre2_b(50) ); +fwd_a_frac_pre_51: rf1_a_frac_pre(51) <= not( rf1_a_frac_pre1_b(51) and rf1_a_frac_pre2_b(51) ); +fwd_a_frac_pre_52: rf1_a_frac_pre(52) <= not( rf1_a_frac_pre1_b(52) and rf1_a_frac_pre2_b(52) ); + +fwd_c_frac_pre_00: rf1_c_frac_pre( 0) <= not( rf1_c_frac_pre1_b( 0) and rf1_c_frac_pre2_b( 0) and rf1_c_frac_pre3_b( 0) ); +fwd_c_frac_pre_01: rf1_c_frac_pre( 1) <= not( rf1_c_frac_pre1_b( 1) and rf1_c_frac_pre2_b( 1) and rf1_c_frac_pre3_b( 1) ); +fwd_c_frac_pre_02: rf1_c_frac_pre( 2) <= not( rf1_c_frac_pre1_b( 2) and rf1_c_frac_pre2_b( 2) and rf1_c_frac_pre3_b( 2) ); +fwd_c_frac_pre_03: rf1_c_frac_pre( 3) <= not( rf1_c_frac_pre1_b( 3) and rf1_c_frac_pre2_b( 3) and rf1_c_frac_pre3_b( 3) ); +fwd_c_frac_pre_04: rf1_c_frac_pre( 4) <= not( rf1_c_frac_pre1_b( 4) and rf1_c_frac_pre2_b( 4) and rf1_c_frac_pre3_b( 4) ); +fwd_c_frac_pre_05: rf1_c_frac_pre( 5) <= not( rf1_c_frac_pre1_b( 5) and rf1_c_frac_pre2_b( 5) and rf1_c_frac_pre3_b( 5) ); +fwd_c_frac_pre_06: rf1_c_frac_pre( 6) <= not( rf1_c_frac_pre1_b( 6) and rf1_c_frac_pre2_b( 6) and rf1_c_frac_pre3_b( 6) ); +fwd_c_frac_pre_07: rf1_c_frac_pre( 7) <= not( rf1_c_frac_pre1_b( 7) and rf1_c_frac_pre2_b( 7) and rf1_c_frac_pre3_b( 7) ); +fwd_c_frac_pre_08: rf1_c_frac_pre( 8) <= not( rf1_c_frac_pre1_b( 8) and rf1_c_frac_pre2_b( 8) and rf1_c_frac_pre3_b( 8) ); +fwd_c_frac_pre_09: rf1_c_frac_pre( 9) <= not( rf1_c_frac_pre1_b( 9) and rf1_c_frac_pre2_b( 9) and rf1_c_frac_pre3_b( 9) ); +fwd_c_frac_pre_10: rf1_c_frac_pre(10) <= not( rf1_c_frac_pre1_b(10) and rf1_c_frac_pre2_b(10) and rf1_c_frac_pre3_b(10) ); +fwd_c_frac_pre_11: rf1_c_frac_pre(11) <= not( rf1_c_frac_pre1_b(11) and rf1_c_frac_pre2_b(11) and rf1_c_frac_pre3_b(11) ); +fwd_c_frac_pre_12: rf1_c_frac_pre(12) <= not( rf1_c_frac_pre1_b(12) and rf1_c_frac_pre2_b(12) and rf1_c_frac_pre3_b(12) ); +fwd_c_frac_pre_13: rf1_c_frac_pre(13) <= not( rf1_c_frac_pre1_b(13) and rf1_c_frac_pre2_b(13) and rf1_c_frac_pre3_b(13) ); +fwd_c_frac_pre_14: rf1_c_frac_pre(14) <= not( rf1_c_frac_pre1_b(14) and rf1_c_frac_pre2_b(14) and rf1_c_frac_pre3_b(14) ); +fwd_c_frac_pre_15: rf1_c_frac_pre(15) <= not( rf1_c_frac_pre1_b(15) and rf1_c_frac_pre2_b(15) and rf1_c_frac_pre3_b(15) ); +fwd_c_frac_pre_16: rf1_c_frac_pre(16) <= not( rf1_c_frac_pre1_b(16) and rf1_c_frac_pre2_b(16) and rf1_c_frac_pre3_b(16) ); +fwd_c_frac_pre_17: rf1_c_frac_pre(17) <= not( rf1_c_frac_pre1_b(17) and rf1_c_frac_pre2_b(17) and rf1_c_frac_pre3_b(17) ); +fwd_c_frac_pre_18: rf1_c_frac_pre(18) <= not( rf1_c_frac_pre1_b(18) and rf1_c_frac_pre2_b(18) and rf1_c_frac_pre3_b(18) ); +fwd_c_frac_pre_19: rf1_c_frac_pre(19) <= not( rf1_c_frac_pre1_b(19) and rf1_c_frac_pre2_b(19) and rf1_c_frac_pre3_b(19) ); +fwd_c_frac_pre_20: rf1_c_frac_pre(20) <= not( rf1_c_frac_pre1_b(20) and rf1_c_frac_pre2_b(20) and rf1_c_frac_pre3_b(20) ); +fwd_c_frac_pre_21: rf1_c_frac_pre(21) <= not( rf1_c_frac_pre1_b(21) and rf1_c_frac_pre2_b(21) and rf1_c_frac_pre3_b(21) ); +fwd_c_frac_pre_22: rf1_c_frac_pre(22) <= not( rf1_c_frac_pre1_b(22) and rf1_c_frac_pre2_b(22) and rf1_c_frac_pre3_b(22) ); +fwd_c_frac_pre_23: rf1_c_frac_pre(23) <= not( rf1_c_frac_pre1_b(23) and rf1_c_frac_pre2_b(23) and rf1_c_frac_pre3_b(23) ); +fwd_c_frac_pre_24: rf1_c_frac_pre(24) <= not( rf1_c_frac_pre1_b(24) and rf1_c_frac_pre2_b(24) and rf1_c_frac_pre3_b(24) ); +fwd_c_frac_pre_25: rf1_c_frac_pre(25) <= not( rf1_c_frac_pre1_b(25) and rf1_c_frac_pre2_b(25) and rf1_c_frac_pre3_b(25) ); +fwd_c_frac_pre_26: rf1_c_frac_pre(26) <= not( rf1_c_frac_pre1_b(26) and rf1_c_frac_pre2_b(26) and rf1_c_frac_pre3_b(26) ); +fwd_c_frac_pre_27: rf1_c_frac_pre(27) <= not( rf1_c_frac_pre1_b(27) and rf1_c_frac_pre2_b(27) and rf1_c_frac_pre3_b(27) ); +fwd_c_frac_pre_28: rf1_c_frac_pre(28) <= not( rf1_c_frac_pre1_b(28) and rf1_c_frac_pre2_b(28) and rf1_c_frac_pre3_b(28) ); +fwd_c_frac_pre_29: rf1_c_frac_pre(29) <= not( rf1_c_frac_pre1_b(29) and rf1_c_frac_pre2_b(29) and rf1_c_frac_pre3_b(29) ); +fwd_c_frac_pre_30: rf1_c_frac_pre(30) <= not( rf1_c_frac_pre1_b(30) and rf1_c_frac_pre2_b(30) and rf1_c_frac_pre3_b(30) ); +fwd_c_frac_pre_31: rf1_c_frac_pre(31) <= not( rf1_c_frac_pre1_b(31) and rf1_c_frac_pre2_b(31) and rf1_c_frac_pre3_b(31) ); +fwd_c_frac_pre_32: rf1_c_frac_pre(32) <= not( rf1_c_frac_pre1_b(32) and rf1_c_frac_pre2_b(32) and rf1_c_frac_pre3_b(32) ); +fwd_c_frac_pre_33: rf1_c_frac_pre(33) <= not( rf1_c_frac_pre1_b(33) and rf1_c_frac_pre2_b(33) and rf1_c_frac_pre3_b(33) ); +fwd_c_frac_pre_34: rf1_c_frac_pre(34) <= not( rf1_c_frac_pre1_b(34) and rf1_c_frac_pre2_b(34) and rf1_c_frac_pre3_b(34) ); +fwd_c_frac_pre_35: rf1_c_frac_pre(35) <= not( rf1_c_frac_pre1_b(35) and rf1_c_frac_pre2_b(35) and rf1_c_frac_pre3_b(35) ); +fwd_c_frac_pre_36: rf1_c_frac_pre(36) <= not( rf1_c_frac_pre1_b(36) and rf1_c_frac_pre2_b(36) and rf1_c_frac_pre3_b(36) ); +fwd_c_frac_pre_37: rf1_c_frac_pre(37) <= not( rf1_c_frac_pre1_b(37) and rf1_c_frac_pre2_b(37) and rf1_c_frac_pre3_b(37) ); +fwd_c_frac_pre_38: rf1_c_frac_pre(38) <= not( rf1_c_frac_pre1_b(38) and rf1_c_frac_pre2_b(38) and rf1_c_frac_pre3_b(38) ); +fwd_c_frac_pre_39: rf1_c_frac_pre(39) <= not( rf1_c_frac_pre1_b(39) and rf1_c_frac_pre2_b(39) and rf1_c_frac_pre3_b(39) ); +fwd_c_frac_pre_40: rf1_c_frac_pre(40) <= not( rf1_c_frac_pre1_b(40) and rf1_c_frac_pre2_b(40) and rf1_c_frac_pre3_b(40) ); +fwd_c_frac_pre_41: rf1_c_frac_pre(41) <= not( rf1_c_frac_pre1_b(41) and rf1_c_frac_pre2_b(41) and rf1_c_frac_pre3_b(41) ); +fwd_c_frac_pre_42: rf1_c_frac_pre(42) <= not( rf1_c_frac_pre1_b(42) and rf1_c_frac_pre2_b(42) and rf1_c_frac_pre3_b(42) ); +fwd_c_frac_pre_43: rf1_c_frac_pre(43) <= not( rf1_c_frac_pre1_b(43) and rf1_c_frac_pre2_b(43) and rf1_c_frac_pre3_b(43) ); +fwd_c_frac_pre_44: rf1_c_frac_pre(44) <= not( rf1_c_frac_pre1_b(44) and rf1_c_frac_pre2_b(44) and rf1_c_frac_pre3_b(44) ); +fwd_c_frac_pre_45: rf1_c_frac_pre(45) <= not( rf1_c_frac_pre1_b(45) and rf1_c_frac_pre2_b(45) and rf1_c_frac_pre3_b(45) ); +fwd_c_frac_pre_46: rf1_c_frac_pre(46) <= not( rf1_c_frac_pre1_b(46) and rf1_c_frac_pre2_b(46) and rf1_c_frac_pre3_b(46) ); +fwd_c_frac_pre_47: rf1_c_frac_pre(47) <= not( rf1_c_frac_pre1_b(47) and rf1_c_frac_pre2_b(47) and rf1_c_frac_pre3_b(47) ); +fwd_c_frac_pre_48: rf1_c_frac_pre(48) <= not( rf1_c_frac_pre1_b(48) and rf1_c_frac_pre2_b(48) and rf1_c_frac_pre3_b(48) ); +fwd_c_frac_pre_49: rf1_c_frac_pre(49) <= not( rf1_c_frac_pre1_b(49) and rf1_c_frac_pre2_b(49) and rf1_c_frac_pre3_b(49) ); +fwd_c_frac_pre_50: rf1_c_frac_pre(50) <= not( rf1_c_frac_pre1_b(50) and rf1_c_frac_pre2_b(50) and rf1_c_frac_pre3_b(50) ); +fwd_c_frac_pre_51: rf1_c_frac_pre(51) <= not( rf1_c_frac_pre1_b(51) and rf1_c_frac_pre2_b(51) and rf1_c_frac_pre3_b(51) ); +fwd_c_frac_pre_52: rf1_c_frac_pre(52) <= not( rf1_c_frac_pre1_b(52) and rf1_c_frac_pre2_b(52) and rf1_c_frac_pre3_b(52) ); + +fwd_c_frac_pre_24h: rf1_c_frac_pre_hulp <= not( rf1_c_frac_pre1_b(24) and rf1_c_frac_pre2_b(24) and rf1_c_frac_pre3_hulp_b ); + + +fwd_b_frac_pre_00: rf1_b_frac_pre( 0) <= not( rf1_b_frac_pre1_b( 0) and rf1_b_frac_pre2_b( 0) and rf1_b_frac_pre3_b( 0) ); +fwd_b_frac_pre_01: rf1_b_frac_pre( 1) <= not( rf1_b_frac_pre1_b( 1) and rf1_b_frac_pre2_b( 1) and rf1_b_frac_pre3_b( 1) ); +fwd_b_frac_pre_02: rf1_b_frac_pre( 2) <= not( rf1_b_frac_pre1_b( 2) and rf1_b_frac_pre2_b( 2) ); +fwd_b_frac_pre_03: rf1_b_frac_pre( 3) <= not( rf1_b_frac_pre1_b( 3) and rf1_b_frac_pre2_b( 3) ); +fwd_b_frac_pre_04: rf1_b_frac_pre( 4) <= not( rf1_b_frac_pre1_b( 4) and rf1_b_frac_pre2_b( 4) ); +fwd_b_frac_pre_05: rf1_b_frac_pre( 5) <= not( rf1_b_frac_pre1_b( 5) and rf1_b_frac_pre2_b( 5) ); +fwd_b_frac_pre_06: rf1_b_frac_pre( 6) <= not( rf1_b_frac_pre1_b( 6) and rf1_b_frac_pre2_b( 6) ); +fwd_b_frac_pre_07: rf1_b_frac_pre( 7) <= not( rf1_b_frac_pre1_b( 7) and rf1_b_frac_pre2_b( 7) ); +fwd_b_frac_pre_08: rf1_b_frac_pre( 8) <= not( rf1_b_frac_pre1_b( 8) and rf1_b_frac_pre2_b( 8) ); +fwd_b_frac_pre_09: rf1_b_frac_pre( 9) <= not( rf1_b_frac_pre1_b( 9) and rf1_b_frac_pre2_b( 9) ); +fwd_b_frac_pre_10: rf1_b_frac_pre(10) <= not( rf1_b_frac_pre1_b(10) and rf1_b_frac_pre2_b(10) ); +fwd_b_frac_pre_11: rf1_b_frac_pre(11) <= not( rf1_b_frac_pre1_b(11) and rf1_b_frac_pre2_b(11) ); +fwd_b_frac_pre_12: rf1_b_frac_pre(12) <= not( rf1_b_frac_pre1_b(12) and rf1_b_frac_pre2_b(12) ); +fwd_b_frac_pre_13: rf1_b_frac_pre(13) <= not( rf1_b_frac_pre1_b(13) and rf1_b_frac_pre2_b(13) ); +fwd_b_frac_pre_14: rf1_b_frac_pre(14) <= not( rf1_b_frac_pre1_b(14) and rf1_b_frac_pre2_b(14) ); +fwd_b_frac_pre_15: rf1_b_frac_pre(15) <= not( rf1_b_frac_pre1_b(15) and rf1_b_frac_pre2_b(15) ); +fwd_b_frac_pre_16: rf1_b_frac_pre(16) <= not( rf1_b_frac_pre1_b(16) and rf1_b_frac_pre2_b(16) ); +fwd_b_frac_pre_17: rf1_b_frac_pre(17) <= not( rf1_b_frac_pre1_b(17) and rf1_b_frac_pre2_b(17) ); +fwd_b_frac_pre_18: rf1_b_frac_pre(18) <= not( rf1_b_frac_pre1_b(18) and rf1_b_frac_pre2_b(18) ); +fwd_b_frac_pre_19: rf1_b_frac_pre(19) <= not( rf1_b_frac_pre1_b(19) and rf1_b_frac_pre2_b(19) ); +fwd_b_frac_pre_20: rf1_b_frac_pre(20) <= not( rf1_b_frac_pre1_b(20) and rf1_b_frac_pre2_b(20) ); +fwd_b_frac_pre_21: rf1_b_frac_pre(21) <= not( rf1_b_frac_pre1_b(21) and rf1_b_frac_pre2_b(21) ); +fwd_b_frac_pre_22: rf1_b_frac_pre(22) <= not( rf1_b_frac_pre1_b(22) and rf1_b_frac_pre2_b(22) ); +fwd_b_frac_pre_23: rf1_b_frac_pre(23) <= not( rf1_b_frac_pre1_b(23) and rf1_b_frac_pre2_b(23) ); +fwd_b_frac_pre_24: rf1_b_frac_pre(24) <= not( rf1_b_frac_pre1_b(24) and rf1_b_frac_pre2_b(24) ); +fwd_b_frac_pre_25: rf1_b_frac_pre(25) <= not( rf1_b_frac_pre1_b(25) and rf1_b_frac_pre2_b(25) ); +fwd_b_frac_pre_26: rf1_b_frac_pre(26) <= not( rf1_b_frac_pre1_b(26) and rf1_b_frac_pre2_b(26) ); +fwd_b_frac_pre_27: rf1_b_frac_pre(27) <= not( rf1_b_frac_pre1_b(27) and rf1_b_frac_pre2_b(27) ); +fwd_b_frac_pre_28: rf1_b_frac_pre(28) <= not( rf1_b_frac_pre1_b(28) and rf1_b_frac_pre2_b(28) ); +fwd_b_frac_pre_29: rf1_b_frac_pre(29) <= not( rf1_b_frac_pre1_b(29) and rf1_b_frac_pre2_b(29) ); +fwd_b_frac_pre_30: rf1_b_frac_pre(30) <= not( rf1_b_frac_pre1_b(30) and rf1_b_frac_pre2_b(30) ); +fwd_b_frac_pre_31: rf1_b_frac_pre(31) <= not( rf1_b_frac_pre1_b(31) and rf1_b_frac_pre2_b(31) ); +fwd_b_frac_pre_32: rf1_b_frac_pre(32) <= not( rf1_b_frac_pre1_b(32) and rf1_b_frac_pre2_b(32) ); +fwd_b_frac_pre_33: rf1_b_frac_pre(33) <= not( rf1_b_frac_pre1_b(33) and rf1_b_frac_pre2_b(33) ); +fwd_b_frac_pre_34: rf1_b_frac_pre(34) <= not( rf1_b_frac_pre1_b(34) and rf1_b_frac_pre2_b(34) ); +fwd_b_frac_pre_35: rf1_b_frac_pre(35) <= not( rf1_b_frac_pre1_b(35) and rf1_b_frac_pre2_b(35) ); +fwd_b_frac_pre_36: rf1_b_frac_pre(36) <= not( rf1_b_frac_pre1_b(36) and rf1_b_frac_pre2_b(36) ); +fwd_b_frac_pre_37: rf1_b_frac_pre(37) <= not( rf1_b_frac_pre1_b(37) and rf1_b_frac_pre2_b(37) ); +fwd_b_frac_pre_38: rf1_b_frac_pre(38) <= not( rf1_b_frac_pre1_b(38) and rf1_b_frac_pre2_b(38) ); +fwd_b_frac_pre_39: rf1_b_frac_pre(39) <= not( rf1_b_frac_pre1_b(39) and rf1_b_frac_pre2_b(39) ); +fwd_b_frac_pre_40: rf1_b_frac_pre(40) <= not( rf1_b_frac_pre1_b(40) and rf1_b_frac_pre2_b(40) ); +fwd_b_frac_pre_41: rf1_b_frac_pre(41) <= not( rf1_b_frac_pre1_b(41) and rf1_b_frac_pre2_b(41) ); +fwd_b_frac_pre_42: rf1_b_frac_pre(42) <= not( rf1_b_frac_pre1_b(42) and rf1_b_frac_pre2_b(42) ); +fwd_b_frac_pre_43: rf1_b_frac_pre(43) <= not( rf1_b_frac_pre1_b(43) and rf1_b_frac_pre2_b(43) ); +fwd_b_frac_pre_44: rf1_b_frac_pre(44) <= not( rf1_b_frac_pre1_b(44) and rf1_b_frac_pre2_b(44) ); +fwd_b_frac_pre_45: rf1_b_frac_pre(45) <= not( rf1_b_frac_pre1_b(45) and rf1_b_frac_pre2_b(45) ); +fwd_b_frac_pre_46: rf1_b_frac_pre(46) <= not( rf1_b_frac_pre1_b(46) and rf1_b_frac_pre2_b(46) ); +fwd_b_frac_pre_47: rf1_b_frac_pre(47) <= not( rf1_b_frac_pre1_b(47) and rf1_b_frac_pre2_b(47) ); +fwd_b_frac_pre_48: rf1_b_frac_pre(48) <= not( rf1_b_frac_pre1_b(48) and rf1_b_frac_pre2_b(48) ); +fwd_b_frac_pre_49: rf1_b_frac_pre(49) <= not( rf1_b_frac_pre1_b(49) and rf1_b_frac_pre2_b(49) ); +fwd_b_frac_pre_50: rf1_b_frac_pre(50) <= not( rf1_b_frac_pre1_b(50) and rf1_b_frac_pre2_b(50) ); +fwd_b_frac_pre_51: rf1_b_frac_pre(51) <= not( rf1_b_frac_pre1_b(51) and rf1_b_frac_pre2_b(51) ); +fwd_b_frac_pre_52: rf1_b_frac_pre(52) <= not( rf1_b_frac_pre1_b(52) and rf1_b_frac_pre2_b(52) ); + + + + rf1_a_frac_prebyp(0 to 52) <= rf1_a_frac_pre(0 to 52); + rf1_c_frac_prebyp(0 to 52) <= rf1_c_frac_pre(0 to 52); + rf1_b_frac_prebyp(0 to 52) <= rf1_b_frac_pre(0 to 52); + rf1_c_frac_prebyp_hulp <= rf1_c_frac_pre_hulp ; + + rf1_a_sign_fpr <= f_fpr_rf1_a_sign ; + rf1_c_sign_fpr <= f_fpr_rf1_c_sign ; + rf1_b_sign_fpr <= f_fpr_rf1_b_sign ; + rf1_a_expo_fpr(1 to 13) <= f_fpr_rf1_a_expo(1 to 13) ; + rf1_c_expo_fpr(1 to 13) <= f_fpr_rf1_c_expo(1 to 13) ; + rf1_b_expo_fpr(1 to 13) <= f_fpr_rf1_b_expo(1 to 13) ; + rf1_a_frac_fpr(0 to 52) <= f_fpr_rf1_a_frac(0 to 52) ; + rf1_c_frac_fpr(0 to 52) <= f_fpr_rf1_c_frac(0 to 52) ; + rf1_b_frac_fpr(0 to 52) <= f_fpr_rf1_b_frac(0 to 52) ; + + +fwd_a_sign_fmt: rf1_a_sign_fmt_b <= not( ( sel_a_no_byp_s and rf1_a_sign_fpr ) or rf1_a_sign_prebyp ); +fwd_a_sign_pic: rf1_a_sign_pic_b <= not( ( sel_a_no_byp_s and rf1_a_sign_fpr ) or rf1_a_sign_prebyp ); +fwd_c_sign_fmt: rf1_c_sign_fmt_b <= not( ( sel_c_no_byp_s and rf1_c_sign_fpr ) or rf1_c_sign_prebyp ); +fwd_c_sign_pic: rf1_c_sign_pic_b <= not( ( sel_c_no_byp_s and rf1_c_sign_fpr ) or rf1_c_sign_prebyp ); +fwd_b_sign_fmt: rf1_b_sign_fmt_b <= not( ( sel_b_no_byp_s and rf1_b_sign_fpr ) or rf1_b_sign_prebyp ); +fwd_b_sign_pic: rf1_b_sign_pic_b <= not( ( sel_b_no_byp_s and rf1_b_sign_fpr ) or rf1_b_sign_prebyp ); +fwd_b_sign_alg: rf1_b_sign_alg_b <= not( ( sel_b_no_byp_s and rf1_b_sign_fpr ) or rf1_b_sign_prebyp ); + +fwd_a_expo_fmt: rf1_a_expo_fmt_b(1 to 13) <= not( ( (1 to 13 => sel_a_no_byp) and rf1_a_expo_fpr(1 to 13) ) or rf1_a_expo_prebyp(1 to 13) ); +fwd_a_expo_eie: rf1_a_expo_eie_b(1 to 13) <= not( ( (1 to 13 => sel_a_no_byp) and rf1_a_expo_fpr(1 to 13) ) or rf1_a_expo_prebyp(1 to 13) ); +fwd_a_expo_alg: rf1_a_expo_alg_b(1 to 13) <= not( ( (1 to 13 => sel_a_no_byp) and rf1_a_expo_fpr(1 to 13) ) or rf1_a_expo_prebyp(1 to 13) ); +fwd_c_expo_fmt: rf1_c_expo_fmt_b(1 to 13) <= not( ( (1 to 13 => sel_c_no_byp) and rf1_c_expo_fpr(1 to 13) ) or rf1_c_expo_prebyp(1 to 13) ); +fwd_c_expo_eie: rf1_c_expo_eie_b(1 to 13) <= not( ( (1 to 13 => sel_c_no_byp) and rf1_c_expo_fpr(1 to 13) ) or rf1_c_expo_prebyp(1 to 13) ); +fwd_c_expo_alg: rf1_c_expo_alg_b(1 to 13) <= not( ( (1 to 13 => sel_c_no_byp) and rf1_c_expo_fpr(1 to 13) ) or rf1_c_expo_prebyp(1 to 13) ); +fwd_b_expo_fmt: rf1_b_expo_fmt_b(1 to 13) <= not( ( (1 to 13 => sel_b_no_byp) and rf1_b_expo_fpr(1 to 13) ) or rf1_b_expo_prebyp(1 to 13) ); +fwd_b_expo_eie: rf1_b_expo_eie_b(1 to 13) <= not( ( (1 to 13 => sel_b_no_byp) and rf1_b_expo_fpr(1 to 13) ) or rf1_b_expo_prebyp(1 to 13) ); +fwd_b_expo_alg: rf1_b_expo_alg_b(1 to 13) <= not( ( (1 to 13 => sel_b_no_byp) and rf1_b_expo_fpr(1 to 13) ) or rf1_b_expo_prebyp(1 to 13) ); + +fwd_a_frac_fmt_00: rf1_a_frac_fmt_b(0 to 23) <= not( ( (0 to 23 => sel_a_no_byp) AND rf1_a_frac_fpr(0 to 23) ) or rf1_a_frac_prebyp(0 to 23) ); +fwd_a_frac_mul_00: rf1_a_frac_mul_b(0 to 23) <= not( ( (0 to 23 => sel_a_no_byp) AND rf1_a_frac_fpr(0 to 23) ) or rf1_a_frac_prebyp(0 to 23) ); +fwd_a_frac_mul_17: rf1_a_frac_mul_17_b <= not( ( sel_a_no_byp AND rf1_a_frac_fpr(17) ) or rf1_a_frac_prebyp(17) ); +fwd_a_frac_fmt_24: rf1_a_frac_fmt_b(24 to 52) <= not( ( (24 to 52 => sel_a_no_byp) AND rf1_a_frac_fpr(24 to 52) ) or rf1_a_frac_prebyp(24 to 52) ); +fwd_a_frac_mul_24: rf1_a_frac_mul_b(24 to 52) <= not( ( (24 to 52 => sel_a_no_byp) AND rf1_a_frac_fpr(24 to 52) ) or rf1_a_frac_prebyp(24 to 52) ); +fwd_a_frac_mul_35: rf1_a_frac_mul_35_b <= not( ( sel_a_no_byp AND rf1_a_frac_fpr(35) ) or rf1_a_frac_prebyp(35) ); + +fwd_c_frac_fmt_00: rf1_c_frac_fmt_b(0 to 23) <= not( ( (0 to 23 => sel_c_no_byp) AND rf1_c_frac_fpr(0 to 23) ) or rf1_c_frac_prebyp(0 to 23) ); +fwd_c_frac_mul_00: rf1_c_frac_mul_b(0 to 23) <= not( ( (0 to 23 => sel_c_no_byp) AND rf1_c_frac_fpr(0 to 23) ) or rf1_c_frac_prebyp(0 to 23) ); + +fwd_c_frac_fmt_24: rf1_c_frac_fmt_b(24) <= not( ( sel_c_no_byp AND rf1_c_frac_fpr(24) ) or rf1_c_frac_prebyp(24) ); +fwd_c_frac_mul_24: rf1_c_frac_mul_b(24) <= not( ( sel_c_no_byp AND rf1_c_frac_fpr(24) ) or rf1_c_frac_prebyp_hulp ); + +fwd_c_frac_fmt_25: rf1_c_frac_fmt_b(25 to 52) <= not( ( (25 to 52 => sel_c_no_byp) AND rf1_c_frac_fpr(25 to 52) ) or rf1_c_frac_prebyp(25 to 52) ); +fwd_c_frac_mul_25: rf1_c_frac_mul_b(25 to 52) <= not( ( (25 to 52 => sel_c_no_byp) AND rf1_c_frac_fpr(25 to 52) ) or rf1_c_frac_prebyp(25 to 52) ); + rf1_c_frac_mul_b(53) <= not( f_dcd_rf1_uc_fc_hulp and not f_dcd_rf1_sp ); + +fwd_b_frac_fmt_00: rf1_b_frac_fmt_b(0 to 23) <= not( ( (0 to 23 => sel_b_no_byp) AND rf1_b_frac_fpr(0 to 23) ) or rf1_b_frac_prebyp(0 to 23) ); +fwd_b_frac_alg_00: rf1_b_frac_alg_b(0 to 23) <= not( ( (0 to 23 => sel_b_no_byp) AND rf1_b_frac_fpr(0 to 23) ) or rf1_b_frac_prebyp(0 to 23) ); +fwd_b_frac_fmt_24: rf1_b_frac_fmt_b(24 to 52) <= not( ( (24 to 52 => sel_b_no_byp) AND rf1_b_frac_fpr(24 to 52) ) or rf1_b_frac_prebyp(24 to 52) ); +fwd_b_frac_alg_24: rf1_b_frac_alg_b(24 to 52) <= not( ( (24 to 52 => sel_b_no_byp) AND rf1_b_frac_fpr(24 to 52) ) or rf1_b_frac_prebyp(24 to 52) ); + + + + + + + + + + ex1_frac_b_alg_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 53, btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd , + gd => gnd , + LCLK => byp_ex1_lclk , + D1CLK => byp_ex1_d1clk , + D2CLK => byp_ex1_d2clk , + SCANIN => ex1_b_frac_si , + SCANOUT => ex1_b_frac_so , + D => rf1_b_frac_alg_b(0 to 52) , + QB => ex1_b_frac_alg (0 to 52) ); + + ex1_frac_a_fmt_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 53, btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd , + gd => gnd , + LCLK => byp_ex1_lclk , + D1CLK => byp_ex1_d1clk , + D2CLK => byp_ex1_d2clk , + SCANIN => ex1_frac_a_fmt_si , + SCANOUT => ex1_frac_a_fmt_so , + D(0 to 52) => rf1_a_frac_fmt_b(0 to 52) , + QB(0 to 52) => ex1_a_frac_fmt (0 to 52) ); + + ex1_frac_c_fmt_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 53, btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd , + gd => gnd , + LCLK => byp_ex1_lclk , + D1CLK => byp_ex1_d1clk , + D2CLK => byp_ex1_d2clk , + SCANIN => ex1_frac_c_fmt_si , + SCANOUT => ex1_frac_c_fmt_so , + D(0 to 52) => rf1_c_frac_fmt_b(0 to 52) , + QB(0 to 52) => ex1_c_frac_fmt (0 to 52) ); + + ex1_frac_b_fmt_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 53, btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd , + gd => gnd , + LCLK => byp_ex1_lclk , + D1CLK => byp_ex1_d1clk , + D2CLK => byp_ex1_d2clk , + SCANIN => ex1_frac_b_fmt_si , + SCANOUT => ex1_frac_b_fmt_so , + D(0 to 52) => rf1_b_frac_fmt_b(0 to 52) , + QB(0 to 52) => ex1_b_frac_fmt (0 to 52) ); + + + u_qi_bfa: ex1_b_frac_alg_b(0 to 52) <= not ex1_b_frac_alg(0 to 52) ; + u_qi_bff: ex1_b_frac_fmt_b(0 to 52) <= not ex1_b_frac_fmt(0 to 52) ; + u_qi_cff: ex1_c_frac_fmt_b(0 to 52) <= not ex1_c_frac_fmt(0 to 52) ; + u_qi_aff: ex1_a_frac_fmt_b(0 to 52) <= not ex1_a_frac_fmt(0 to 52) ; + + u_di_cfm: temp_rf1_c_frac_mul(0 to 53) <= not rf1_c_frac_mul_b(0 to 53) ; + u_di_afm: temp_rf1_a_frac_mul(0 to 52) <= not rf1_a_frac_mul_b(0 to 52) ; + u_di_afm_17: temp_rf1_a_frac_mul_17 <= not rf1_a_frac_mul_17_b ; + u_di_afm_35: temp_rf1_a_frac_mul_35 <= not rf1_a_frac_mul_35_b ; + + + ex1_frac_c_mul_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 54, btr => "NLI0001_X4_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd , + gd => gnd , + LCLK => byp_ex1_lclk , + D1CLK => byp_ex1_d1clk , + D2CLK => byp_ex1_d2clk , + SCANIN => frac_mul_c_si , + SCANOUT => frac_mul_c_so , + D(0 to 52) => temp_rf1_c_frac_mul(0 to 52) , + D(53) => temp_rf1_c_frac_mul(53) , + QB => ex1_c_frac_mul_b(0 to 53) ); + + ex1_frac_a_mul_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 55, btr => "NLI0001_X4_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd , + gd => gnd , + LCLK => byp_ex1_lclk , + D1CLK => byp_ex1_d1clk , + D2CLK => byp_ex1_d2clk , + SCANIN => frac_mul_a_si , + SCANOUT => frac_mul_a_so , + D( 0) => temp_rf1_a_frac_mul(0) , + D( 1) => temp_rf1_a_frac_mul(17) , + D( 2) => temp_rf1_a_frac_mul(35) , + D( 3) => temp_rf1_a_frac_mul(1) , + D( 4) => temp_rf1_a_frac_mul(18) , + D( 5) => temp_rf1_a_frac_mul(36) , + D( 6) => temp_rf1_a_frac_mul(2) , + D( 7) => temp_rf1_a_frac_mul(19) , + D( 8) => temp_rf1_a_frac_mul(37) , + D( 9) => temp_rf1_a_frac_mul(3) , + D(10) => temp_rf1_a_frac_mul(20) , + D(11) => temp_rf1_a_frac_mul(38) , + D(12) => temp_rf1_a_frac_mul(4) , + D(13) => temp_rf1_a_frac_mul(21) , + D(14) => temp_rf1_a_frac_mul(39) , + D(15) => temp_rf1_a_frac_mul(5) , + D(16) => temp_rf1_a_frac_mul(22) , + D(17) => temp_rf1_a_frac_mul(40) , + D(18) => temp_rf1_a_frac_mul(6) , + D(19) => temp_rf1_a_frac_mul(23) , + D(20) => temp_rf1_a_frac_mul(41) , + D(21) => temp_rf1_a_frac_mul(7) , + D(22) => temp_rf1_a_frac_mul(24) , + D(23) => temp_rf1_a_frac_mul(42) , + D(24) => temp_rf1_a_frac_mul(8) , + D(25) => temp_rf1_a_frac_mul(25) , + D(26) => temp_rf1_a_frac_mul(43) , + D(27) => temp_rf1_a_frac_mul(9) , + D(28) => temp_rf1_a_frac_mul(26) , + D(29) => temp_rf1_a_frac_mul(44) , + D(30) => temp_rf1_a_frac_mul(10) , + D(31) => temp_rf1_a_frac_mul(27) , + D(32) => temp_rf1_a_frac_mul(45) , + D(33) => temp_rf1_a_frac_mul(11) , + D(34) => temp_rf1_a_frac_mul(28) , + D(35) => temp_rf1_a_frac_mul(46) , + D(36) => temp_rf1_a_frac_mul(12) , + D(37) => temp_rf1_a_frac_mul(29) , + D(38) => temp_rf1_a_frac_mul(47) , + D(39) => temp_rf1_a_frac_mul(13) , + D(40) => temp_rf1_a_frac_mul(30) , + D(41) => temp_rf1_a_frac_mul(48) , + D(42) => temp_rf1_a_frac_mul(14) , + D(43) => temp_rf1_a_frac_mul(31) , + D(44) => temp_rf1_a_frac_mul(49) , + D(45) => temp_rf1_a_frac_mul(15) , + D(46) => temp_rf1_a_frac_mul(32) , + D(47) => temp_rf1_a_frac_mul(50) , + D(48) => temp_rf1_a_frac_mul(16) , + D(49) => temp_rf1_a_frac_mul(33) , + D(50) => temp_rf1_a_frac_mul(51) , + D(51) => temp_rf1_a_frac_mul_17 , + D(52) => temp_rf1_a_frac_mul(34) , + D(53) => temp_rf1_a_frac_mul(52) , + D(54) => temp_rf1_a_frac_mul_35 , + QB( 0) => ex1_a_frac_mul_b(0) , + QB( 1) => ex1_a_frac_mul_b(17) , + QB( 2) => ex1_a_frac_mul_b(35) , + QB( 3) => ex1_a_frac_mul_b(1) , + QB( 4) => ex1_a_frac_mul_b(18) , + QB( 5) => ex1_a_frac_mul_b(36) , + QB( 6) => ex1_a_frac_mul_b(2) , + QB( 7) => ex1_a_frac_mul_b(19) , + QB( 8) => ex1_a_frac_mul_b(37) , + QB( 9) => ex1_a_frac_mul_b(3) , + QB(10) => ex1_a_frac_mul_b(20) , + QB(11) => ex1_a_frac_mul_b(38) , + QB(12) => ex1_a_frac_mul_b(4) , + QB(13) => ex1_a_frac_mul_b(21) , + QB(14) => ex1_a_frac_mul_b(39) , + QB(15) => ex1_a_frac_mul_b(5) , + QB(16) => ex1_a_frac_mul_b(22) , + QB(17) => ex1_a_frac_mul_b(40) , + QB(18) => ex1_a_frac_mul_b(6) , + QB(19) => ex1_a_frac_mul_b(23) , + QB(20) => ex1_a_frac_mul_b(41) , + QB(21) => ex1_a_frac_mul_b(7) , + QB(22) => ex1_a_frac_mul_b(24) , + QB(23) => ex1_a_frac_mul_b(42) , + QB(24) => ex1_a_frac_mul_b(8) , + QB(25) => ex1_a_frac_mul_b(25) , + QB(26) => ex1_a_frac_mul_b(43) , + QB(27) => ex1_a_frac_mul_b(9) , + QB(28) => ex1_a_frac_mul_b(26) , + QB(29) => ex1_a_frac_mul_b(44) , + QB(30) => ex1_a_frac_mul_b(10) , + QB(31) => ex1_a_frac_mul_b(27) , + QB(32) => ex1_a_frac_mul_b(45) , + QB(33) => ex1_a_frac_mul_b(11) , + QB(34) => ex1_a_frac_mul_b(28) , + QB(35) => ex1_a_frac_mul_b(46) , + QB(36) => ex1_a_frac_mul_b(12) , + QB(37) => ex1_a_frac_mul_b(29) , + QB(38) => ex1_a_frac_mul_b(47) , + QB(39) => ex1_a_frac_mul_b(13) , + QB(40) => ex1_a_frac_mul_b(30) , + QB(41) => ex1_a_frac_mul_b(48) , + QB(42) => ex1_a_frac_mul_b(14) , + QB(43) => ex1_a_frac_mul_b(31) , + QB(44) => ex1_a_frac_mul_b(49) , + QB(45) => ex1_a_frac_mul_b(15) , + QB(46) => ex1_a_frac_mul_b(32) , + QB(47) => ex1_a_frac_mul_b(50) , + QB(48) => ex1_a_frac_mul_b(16) , + QB(49) => ex1_a_frac_mul_b(33) , + QB(50) => ex1_a_frac_mul_b(51) , + QB(51) => ex1_a_frac_mul_17_b , + QB(52) => ex1_a_frac_mul_b(34) , + QB(53) => ex1_a_frac_mul_b(52) , + QB(54) => ex1_a_frac_mul_35_b ); + + + bfa_oinv: f_byp_alg_ex1_b_frac(0 to 52) <= not ex1_b_frac_alg_b(0 to 52) ; + f_byp_fmt_ex1_a_frac(0 to 52) <= not ex1_a_frac_fmt_b(0 to 52); + f_byp_fmt_ex1_c_frac(0 to 52) <= not ex1_c_frac_fmt_b(0 to 52); + f_byp_fmt_ex1_b_frac(0 to 52) <= not ex1_b_frac_fmt_b(0 to 52); + afm_oinv: f_byp_mul_ex1_a_frac(0 to 52) <= not ex1_a_frac_mul_b(0 to 52); + afm_oinv_17: f_byp_mul_ex1_a_frac_17 <= not ex1_a_frac_mul_17_b ; + afm_oinv_35: f_byp_mul_ex1_a_frac_35 <= not ex1_a_frac_mul_35_b ; + cfm_oinv: f_byp_mul_ex1_c_frac(0 to 53) <= not ex1_c_frac_mul_b(0 to 53) ; + + + + ex1_expo_b_alg_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 14, btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd , + gd => gnd , + LCLK => byp_ex1_lclk , + D1CLK => byp_ex1_d1clk , + D2CLK => byp_ex1_d2clk , + SCANIN => ex1_expo_b_alg_si , + SCANOUT => ex1_expo_b_alg_so , + D(0) => rf1_b_sign_alg_b , + D(1 to 13) => rf1_b_expo_alg_b(1 to 13) , + QB(0) => ex1_b_sign_alg , + QB(1 to 13) => ex1_b_expo_alg (1 to 13) ); + + ex1_expo_c_alg_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 13, btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd , + gd => gnd , + LCLK => byp_ex1_lclk , + D1CLK => byp_ex1_d1clk , + D2CLK => byp_ex1_d2clk , + SCANIN => ex1_expo_c_alg_si , + SCANOUT => ex1_expo_c_alg_so , + D => rf1_c_expo_alg_b(1 to 13) , + QB => ex1_c_expo_alg (1 to 13) ); + + ex1_expo_a_alg_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 13, btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd , + gd => gnd , + LCLK => byp_ex1_lclk , + D1CLK => byp_ex1_d1clk , + D2CLK => byp_ex1_d2clk , + SCANIN => ex1_expo_a_alg_si , + SCANOUT => ex1_expo_a_alg_so , + D => rf1_a_expo_alg_b(1 to 13) , + QB => ex1_a_expo_alg (1 to 13) ); + + + ex1_expo_b_fmt_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 14, btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd , + gd => gnd , + LCLK => byp_ex1_lclk , + D1CLK => byp_ex1_d1clk , + D2CLK => byp_ex1_d2clk , + SCANIN => ex1_expo_b_fmt_si , + SCANOUT => ex1_expo_b_fmt_so , + D(0) => rf1_b_sign_fmt_b , + D(1 to 13) => rf1_b_expo_fmt_b(1 to 13) , + QB(0) => ex1_b_sign_fmt , + QB(1 to 13) => ex1_b_expo_fmt (1 to 13) ); + + ex1_expo_a_fmt_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 14, btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd , + gd => gnd , + LCLK => byp_ex1_lclk , + D1CLK => byp_ex1_d1clk , + D2CLK => byp_ex1_d2clk , + SCANIN => ex1_expo_a_fmt_si , + SCANOUT => ex1_expo_a_fmt_so , + D(0) => rf1_a_sign_fmt_b , + D(1 to 13) => rf1_a_expo_fmt_b(1 to 13) , + QB(0) => ex1_a_sign_fmt , + QB(1 to 13) => ex1_a_expo_fmt (1 to 13) ); + + ex1_expo_c_fmt_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 14, btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd , + gd => gnd , + LCLK => byp_ex1_lclk , + D1CLK => byp_ex1_d1clk , + D2CLK => byp_ex1_d2clk , + SCANIN => ex1_expo_c_fmt_si , + SCANOUT => ex1_expo_c_fmt_so , + D(0) => rf1_c_sign_fmt_b , + D(1 to 13) => rf1_c_expo_fmt_b(1 to 13) , + QB(0) => ex1_c_sign_fmt , + QB(1 to 13) => ex1_c_expo_fmt (1 to 13) ); + + ex1_expo_b_eie_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 14, btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd , + gd => gnd , + LCLK => byp_ex1_lclk , + D1CLK => byp_ex1_d1clk , + D2CLK => byp_ex1_d2clk , + SCANIN => ex1_expo_b_eie_si , + SCANOUT => ex1_expo_b_eie_so , + D(0) => rf1_b_sign_pic_b , + D(1 to 13) => rf1_b_expo_eie_b(1 to 13) , + QB(0) => ex1_b_sign_pic , + QB(1 to 13) => ex1_b_expo_eie (1 to 13) ); + + ex1_expo_a_eie_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 14, btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd , + gd => gnd , + LCLK => byp_ex1_lclk , + D1CLK => byp_ex1_d1clk , + D2CLK => byp_ex1_d2clk , + SCANIN => ex1_expo_a_eie_si , + SCANOUT => ex1_expo_a_eie_so , + D(0) => rf1_a_sign_pic_b , + D(1 to 13) => rf1_a_expo_eie_b(1 to 13) , + QB(0) => ex1_a_sign_pic , + QB(1 to 13) => ex1_a_expo_eie (1 to 13) ); + + ex1_expo_c_eie_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 14, btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd , + gd => gnd , + LCLK => byp_ex1_lclk , + D1CLK => byp_ex1_d1clk , + D2CLK => byp_ex1_d2clk , + SCANIN => ex1_expo_c_eie_si , + SCANOUT => ex1_expo_c_eie_so , + D(0) => rf1_c_sign_pic_b , + D(1 to 13) => rf1_c_expo_eie_b(1 to 13) , + QB(0) => ex1_c_sign_pic , + QB(1 to 13) => ex1_c_expo_eie (1 to 13) ); + + + + + + ex1_b_sign_alg_b <= not ex1_b_sign_alg ; + ex1_b_sign_fmt_b <= not ex1_b_sign_fmt ; + ex1_a_sign_fmt_b <= not ex1_a_sign_fmt ; + ex1_c_sign_fmt_b <= not ex1_c_sign_fmt ; + ex1_b_sign_pic_b <= not ex1_b_sign_pic ; + ex1_a_sign_pic_b <= not ex1_a_sign_pic ; + ex1_c_sign_pic_b <= not ex1_c_sign_pic ; + + ex1_b_expo_alg_b(1 to 13) <= not ex1_b_expo_alg(1 to 13); + ex1_c_expo_alg_b(1 to 13) <= not ex1_c_expo_alg(1 to 13); + ex1_a_expo_alg_b(1 to 13) <= not ex1_a_expo_alg(1 to 13); + ex1_b_expo_fmt_b(1 to 13) <= not ex1_b_expo_fmt(1 to 13); + ex1_c_expo_fmt_b(1 to 13) <= not ex1_c_expo_fmt(1 to 13); + ex1_a_expo_fmt_b(1 to 13) <= not ex1_a_expo_fmt(1 to 13); + ex1_b_expo_eie_b(1 to 13) <= not ex1_b_expo_eie(1 to 13); + ex1_c_expo_eie_b(1 to 13) <= not ex1_c_expo_eie(1 to 13); + ex1_a_expo_eie_b(1 to 13) <= not ex1_a_expo_eie(1 to 13); + + + f_byp_alg_ex1_b_sign <= not ex1_b_sign_alg_b; + f_byp_alg_ex1_b_expo(1 to 13) <= not ex1_b_expo_alg_b(1 to 13); + f_byp_alg_ex1_c_expo(1 to 13) <= not ex1_c_expo_alg_b(1 to 13); + f_byp_alg_ex1_a_expo(1 to 13) <= not ex1_a_expo_alg_b(1 to 13); + + f_byp_fmt_ex1_a_sign <= not ex1_a_sign_fmt_b ; + f_byp_fmt_ex1_a_expo(1 to 13) <= not ex1_a_expo_fmt_b(1 to 13) ; + f_byp_fmt_ex1_c_sign <= not ex1_c_sign_fmt_b ; + f_byp_fmt_ex1_c_expo(1 to 13) <= not ex1_c_expo_fmt_b(1 to 13) ; + f_byp_fmt_ex1_b_sign <= not ex1_b_sign_fmt_b ; + f_byp_fmt_ex1_b_expo(1 to 13) <= not ex1_b_expo_fmt_b(1 to 13) ; + + f_byp_pic_ex1_a_sign <= not ex1_a_sign_pic_b ; + f_byp_eie_ex1_a_expo(1 to 13) <= not ex1_a_expo_eie_b(1 to 13) ; + f_byp_pic_ex1_c_sign <= not ex1_c_sign_pic_b ; + f_byp_eie_ex1_c_expo(1 to 13) <= not ex1_c_expo_eie_b(1 to 13) ; + f_byp_pic_ex1_b_sign <= not ex1_b_sign_pic_b ; + f_byp_eie_ex1_b_expo(1 to 13) <= not ex1_b_expo_eie_b(1 to 13) ; + + + + + act_si(0 to 3) <= act_so(1 to 3) & f_byp_si ; + ex1_b_frac_si(0 to 52) <= ex1_b_frac_so(1 to 52) & act_so(0) ; + ex1_frac_a_fmt_si(0 to 52) <= ex1_frac_a_fmt_so(1 to 52) & ex1_b_frac_so(0) ; + ex1_frac_c_fmt_si(0 to 52) <= ex1_frac_c_fmt_so(1 to 52) & ex1_frac_a_fmt_so(0) ; + ex1_frac_b_fmt_si(0 to 52) <= ex1_frac_b_fmt_so(1 to 52) & ex1_frac_c_fmt_so(0) ; + frac_mul_c_si(0 to 53) <= frac_mul_c_so(1 to 53) & ex1_frac_b_fmt_so(0) ; + frac_mul_a_si(0 to 54) <= frac_mul_a_so(1 to 54) & frac_mul_c_so(0) ; + ex1_expo_a_eie_si(0 to 13) <= ex1_expo_a_eie_so(1 to 13) & frac_mul_a_so(0) ; + ex1_expo_c_eie_si(0 to 13) <= ex1_expo_c_eie_so(1 to 13) & ex1_expo_a_eie_so(0); + ex1_expo_b_eie_si(0 to 13) <= ex1_expo_b_eie_so(1 to 13) & ex1_expo_c_eie_so(0); + ex1_expo_a_fmt_si(0 to 13) <= ex1_expo_a_fmt_so(1 to 13) & ex1_expo_b_eie_so(0); + ex1_expo_c_fmt_si(0 to 13) <= ex1_expo_c_fmt_so(1 to 13) & ex1_expo_a_fmt_so(0); + ex1_expo_b_fmt_si(0 to 13) <= ex1_expo_b_fmt_so(1 to 13) & ex1_expo_c_fmt_so(0); + ex1_expo_b_alg_si(0 to 13) <= ex1_expo_b_alg_so(1 to 13) & ex1_expo_b_fmt_so(0); + ex1_expo_a_alg_si(0 to 12) <= ex1_expo_a_alg_so(1 to 12) & ex1_expo_b_alg_so(0); + ex1_expo_c_alg_si(0 to 12) <= ex1_expo_c_alg_so(1 to 12) & ex1_expo_a_alg_so(0); + f_byp_so <= ex1_expo_c_alg_so(0) ; + + + +end; + + + + + + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_cr2.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_cr2.vhdl new file mode 100644 index 0000000..3d06914 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_cr2.vhdl @@ -0,0 +1,751 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + + + + +entity fuq_cr2 is +generic( expand_type : integer := 2 ); +port( + + vdd :inout power_logic; + gnd :inout power_logic; + clkoff_b :in std_ulogic; + act_dis :in std_ulogic; + flush :in std_ulogic; + delay_lclkr :in std_ulogic_vector(1 to 7); + mpw1_b :in std_ulogic_vector(1 to 7); + mpw2_b :in std_ulogic_vector(0 to 1); + sg_1 :in std_ulogic; + thold_1 :in std_ulogic; + fpu_enable :in std_ulogic; + nclk :in clk_logic; + + + f_cr2_si :in std_ulogic ; + f_cr2_so :out std_ulogic ; + rf1_act :in std_ulogic ; + ex1_act :in std_ulogic ; + rf1_thread_b :in std_ulogic_vector(0 to 3) ; + f_dcd_ex6_cancel :in std_ulogic ; + + f_fmt_ex1_bop_byt :in std_ulogic_vector(45 to 52); + f_dcd_rf1_fpscr_bit_data_b :in std_ulogic_vector(0 to 3); + f_dcd_rf1_fpscr_bit_mask_b :in std_ulogic_vector(0 to 3); + f_dcd_rf1_fpscr_nib_mask_b :in std_ulogic_vector(0 to 8); + f_dcd_rf1_mtfsbx_b :in std_ulogic; + f_dcd_rf1_mcrfs_b :in std_ulogic; + f_dcd_rf1_mtfsf_b :in std_ulogic; + f_dcd_rf1_mtfsfi_b :in std_ulogic; + + f_cr2_ex3_thread_b :out std_ulogic_vector(0 to 3) ; + f_cr2_ex3_fpscr_bit_data_b :out std_ulogic_vector(0 to 3); + f_cr2_ex3_fpscr_bit_mask_b :out std_ulogic_vector(0 to 3); + f_cr2_ex3_fpscr_nib_mask_b :out std_ulogic_vector(0 to 8); + f_cr2_ex3_mtfsbx_b :out std_ulogic; + f_cr2_ex3_mcrfs_b :out std_ulogic; + f_cr2_ex3_mtfsf_b :out std_ulogic; + f_cr2_ex3_mtfsfi_b :out std_ulogic; + + f_cr2_ex5_fpscr_rd_dat :out std_ulogic_vector(24 to 31); + f_cr2_ex6_fpscr_rd_dat :out std_ulogic_vector(24 to 31); + f_cr2_ex1_fpscr_shadow :out std_ulogic_vector(0 to 7) + + +); + + + +end fuq_cr2; + + +architecture fuq_cr2 of fuq_cr2 is + + constant tiup :std_ulogic := '1'; + constant tidn :std_ulogic := '0'; + + signal sg_0 :std_ulogic ; + signal thold_0_b , thold_0, forcee :std_ulogic ; + signal ex6_th0_act :std_ulogic ; + signal ex6_th1_act :std_ulogic ; + signal ex6_th2_act :std_ulogic ; + signal ex6_th3_act :std_ulogic ; + signal ex2_act :std_ulogic ; + signal ex3_act :std_ulogic ; + signal ex4_act, ex5_act, ex6_act :std_ulogic ; + signal ex4_mv_to_op :std_ulogic ; + signal ex5_mv_to_op :std_ulogic ; + signal ex6_mv_to_op :std_ulogic ; + + signal ex1_thread :std_ulogic_vector(0 to 3) ; + signal ex2_thread :std_ulogic_vector(0 to 3) ; + signal ex3_thread :std_ulogic_vector(0 to 3) ; + signal ex4_thread :std_ulogic_vector(0 to 3) ; + signal ex5_thread :std_ulogic_vector(0 to 3) ; + signal ex6_thread :std_ulogic_vector(0 to 3) ; + signal act_spare_unused :std_ulogic_vector(0 to 2) ; + signal act_so , act_si :std_ulogic_vector(0 to 6) ; + signal ex1_ctl_so , ex1_ctl_si :std_ulogic_vector(0 to 33) ; + signal ex2_ctl_so , ex2_ctl_si :std_ulogic_vector(0 to 24) ; + signal ex3_ctl_so , ex3_ctl_si :std_ulogic_vector(0 to 24) ; + signal ex4_ctl_so , ex4_ctl_si :std_ulogic_vector(0 to 4) ; + signal ex5_ctl_so , ex5_ctl_si :std_ulogic_vector(0 to 4) ; + signal ex6_ctl_so , ex6_ctl_si :std_ulogic_vector(0 to 4) ; + signal shadow0_so , shadow0_si :std_ulogic_vector(0 to 7) ; + signal shadow1_so , shadow1_si :std_ulogic_vector(0 to 7) ; + signal shadow2_so , shadow2_si :std_ulogic_vector(0 to 7) ; + signal shadow3_so , shadow3_si :std_ulogic_vector(0 to 7) ; + signal shadow_byp2_so , shadow_byp2_si :std_ulogic_vector(0 to 7) ; + signal shadow_byp3_so , shadow_byp3_si :std_ulogic_vector(0 to 7) ; + signal shadow_byp4_so , shadow_byp4_si :std_ulogic_vector(0 to 7) ; + signal shadow_byp5_so , shadow_byp5_si :std_ulogic_vector(0 to 7) ; + signal shadow_byp6_so , shadow_byp6_si :std_ulogic_vector(0 to 7) ; + signal shadow0 :std_ulogic_vector(0 to 7) ; + signal shadow1 :std_ulogic_vector(0 to 7) ; + signal shadow2 :std_ulogic_vector(0 to 7) ; + signal shadow3 :std_ulogic_vector(0 to 7) ; + signal shadow_byp2 :std_ulogic_vector(0 to 7) ; + signal shadow_byp3 :std_ulogic_vector(0 to 7) ; + signal shadow_byp4 :std_ulogic_vector(0 to 7) ; + signal shadow_byp5 :std_ulogic_vector(0 to 7) ; + signal shadow_byp6 :std_ulogic_vector(0 to 7) ; + signal shadow_byp2_din :std_ulogic_vector(0 to 7) ; + + signal ex1_bit_sel :std_ulogic_vector(0 to 7) ; + signal ex1_fpscr_bit_data :std_ulogic_vector(0 to 3); + signal ex1_fpscr_bit_mask :std_ulogic_vector(0 to 3); + signal ex1_fpscr_nib_mask :std_ulogic_vector(0 to 8); + signal ex1_mtfsbx :std_ulogic; + signal ex1_mcrfs :std_ulogic; + signal ex1_mtfsf :std_ulogic; + signal ex1_mtfsfi :std_ulogic; + signal ex2_fpscr_bit_data :std_ulogic_vector(0 to 3); + signal ex2_fpscr_bit_mask :std_ulogic_vector(0 to 3); + signal ex2_fpscr_nib_mask :std_ulogic_vector(0 to 8); + signal ex2_mtfsbx :std_ulogic; + signal ex2_mcrfs :std_ulogic; + signal ex2_mtfsf :std_ulogic; + signal ex2_mtfsfi :std_ulogic; + + signal ex3_fpscr_bit_data :std_ulogic_vector(0 to 3); + signal ex3_fpscr_bit_mask :std_ulogic_vector(0 to 3); + signal ex3_fpscr_nib_mask :std_ulogic_vector(0 to 8); + signal ex3_mtfsbx :std_ulogic; + signal ex3_mcrfs :std_ulogic; + signal ex3_mtfsf :std_ulogic; + signal ex3_mtfsfi :std_ulogic; + signal ex1_mv_to_op :std_ulogic; + signal ex2_mv_to_op :std_ulogic; + signal ex3_mv_to_op :std_ulogic; + signal ex1_fpscr_data :std_ulogic_vector(0 to 7); + signal rf1_thread :std_ulogic_vector(0 to 3); + signal rf1_rd_sel_0 , ex1_rd_sel_0 :std_ulogic; + signal rf1_rd_sel_1 , ex1_rd_sel_1 :std_ulogic; + signal rf1_rd_sel_2 , ex1_rd_sel_2 :std_ulogic; + signal rf1_rd_sel_3 , ex1_rd_sel_3 :std_ulogic; + signal rf1_rd_sel_byp2, ex1_rd_sel_byp2 :std_ulogic; + signal rf1_rd_sel_byp3, ex1_rd_sel_byp3 :std_ulogic; + signal rf1_rd_sel_byp4, ex1_rd_sel_byp4 :std_ulogic; + signal rf1_rd_sel_byp5, ex1_rd_sel_byp5 :std_ulogic; + signal rf1_rd_sel_byp6, ex1_rd_sel_byp6 :std_ulogic; + + signal rf1_rd_sel_byp2_pri :std_ulogic; + signal rf1_rd_sel_byp3_pri :std_ulogic; + signal rf1_rd_sel_byp4_pri :std_ulogic; + signal rf1_rd_sel_byp5_pri :std_ulogic; + signal rf1_rd_sel_byp6_pri :std_ulogic; + + signal ex1_fpscr_shadow_mux :std_ulogic_vector(0 to 7); + signal rf1_thread_match_1 :std_ulogic; + signal rf1_thread_match_2 :std_ulogic; + signal rf1_thread_match_3 :std_ulogic; + signal rf1_thread_match_4 :std_ulogic; + signal rf1_thread_match_5 :std_ulogic; + signal rf1_fpscr_bit_data :std_ulogic_vector(0 to 3) ; + signal rf1_fpscr_bit_mask :std_ulogic_vector(0 to 3) ; + signal rf1_fpscr_nib_mask :std_ulogic_vector(0 to 8) ; + signal rf1_mtfsbx :std_ulogic ; + signal rf1_mcrfs :std_ulogic ; + signal rf1_mtfsf :std_ulogic ; + signal rf1_mtfsfi :std_ulogic ; + signal ex6_cancel :std_ulogic; + signal ex6_fpscr_rd_dat_no_byp :std_ulogic_vector(24 to 31); + + +begin + + + + thold_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => thold_1, + q(0) => thold_0 ); + + sg_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => sg_1 , + q(0) => sg_0 ); + + + lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map ( + clkoff_b => clkoff_b, + thold => thold_0, + sg => sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => thold_0_b ); + + + + + act_lat: tri_rlmreg_p generic map (width=> 7, expand_type => expand_type, needs_sreset => 0) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(6) , + mpw1_b => mpw1_b(6) , + mpw2_b => mpw2_b(1) , + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => fpu_enable, + scout => act_so , + scin => act_si , + din(0) => act_spare_unused(0), + din(1) => act_spare_unused(1), + din(2) => ex1_act, + din(3) => ex2_act, + din(4) => ex3_act, + din(5) => ex4_act, + din(6) => ex5_act, + dout(0) => act_spare_unused(0), + dout(1) => act_spare_unused(1), + dout(2) => ex2_act, + dout(3) => ex3_act, + dout(4) => ex4_act, + dout(5) => ex5_act , + dout(6) => ex6_act ); + + + act_spare_unused(2) <= rf1_act; + + + rf1_thread(0 to 3) <= not rf1_thread_b(0 to 3) ; + rf1_fpscr_bit_data(0 to 3) <= not f_dcd_rf1_fpscr_bit_data_b(0 to 3); + rf1_fpscr_bit_mask(0 to 3) <= not f_dcd_rf1_fpscr_bit_mask_b(0 to 3); + rf1_fpscr_nib_mask(0 to 8) <= not f_dcd_rf1_fpscr_nib_mask_b(0 to 8); + rf1_mtfsbx <= not f_dcd_rf1_mtfsbx_b ; + rf1_mcrfs <= not f_dcd_rf1_mcrfs_b ; + rf1_mtfsf <= not f_dcd_rf1_mtfsf_b ; + rf1_mtfsfi <= not f_dcd_rf1_mtfsfi_b ; + + + ex1_ctl_lat: tri_rlmreg_p generic map (width=> 34, expand_type => expand_type) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(1) , + mpw1_b => mpw1_b(1) , + mpw2_b => mpw2_b(0) , + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => fpu_enable, + scout => ex1_ctl_so , + scin => ex1_ctl_si , + din(0 to 3) => rf1_thread(0 to 3) , + din(4 to 7) => rf1_fpscr_bit_data(0 to 3), + din(8 to 11) => rf1_fpscr_bit_mask(0 to 3), + din(12 to 20) => rf1_fpscr_nib_mask(0 to 8), + din(21) => rf1_mtfsbx , + din(22) => rf1_mcrfs , + din(23) => rf1_mtfsf , + din(24) => rf1_mtfsfi , + din(25) => rf1_rd_sel_0 , + din(26) => rf1_rd_sel_1 , + din(27) => rf1_rd_sel_2 , + din(28) => rf1_rd_sel_3 , + din(29) => rf1_rd_sel_byp2_pri , + din(30) => rf1_rd_sel_byp3_pri , + din(31) => rf1_rd_sel_byp4_pri , + din(32) => rf1_rd_sel_byp5_pri , + din(33) => rf1_rd_sel_byp6_pri , + dout(0 to 3) => ex1_thread(0 to 3) , + dout(4 to 7) => ex1_fpscr_bit_data(0 to 3), + dout(8 to 11) => ex1_fpscr_bit_mask(0 to 3), + dout(12 to 20) => ex1_fpscr_nib_mask(0 to 8), + dout(21) => ex1_mtfsbx , + dout(22) => ex1_mcrfs , + dout(23) => ex1_mtfsf , + dout(24) => ex1_mtfsfi , + dout(25) => ex1_rd_sel_0 , + dout(26) => ex1_rd_sel_1 , + dout(27) => ex1_rd_sel_2 , + dout(28) => ex1_rd_sel_3 , + dout(29) => ex1_rd_sel_byp2 , + dout(30) => ex1_rd_sel_byp3 , + dout(31) => ex1_rd_sel_byp4 , + dout(32) => ex1_rd_sel_byp5 , + dout(33) => ex1_rd_sel_byp6 ); + + + + ex2_ctl_lat: tri_rlmreg_p generic map (width=> 25, expand_type => expand_type) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(2) , + mpw1_b => mpw1_b(2) , + mpw2_b => mpw2_b(0) , + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => fpu_enable, + scout => ex2_ctl_so , + scin => ex2_ctl_si , + din(0 to 3) => ex1_thread(0 to 3) , + din(4 to 7) => ex1_fpscr_bit_data(0 to 3) , + din(8 to 11) => ex1_fpscr_bit_mask(0 to 3) , + din(12 to 20) => ex1_fpscr_nib_mask(0 to 8) , + din(21) => ex1_mtfsbx , + din(22) => ex1_mcrfs , + din(23) => ex1_mtfsf , + din(24) => ex1_mtfsfi , + dout(0 to 3) => ex2_thread(0 to 3) , + dout(4 to 7) => ex2_fpscr_bit_data(0 to 3) , + dout(8 to 11) => ex2_fpscr_bit_mask(0 to 3) , + dout(12 to 20) => ex2_fpscr_nib_mask(0 to 8) , + dout(21) => ex2_mtfsbx , + dout(22) => ex2_mcrfs , + dout(23) => ex2_mtfsf , + dout(24) => ex2_mtfsfi ); + + + + ex3_ctl_lat: tri_rlmreg_p generic map (width=> 25, expand_type => expand_type) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(3) , + mpw1_b => mpw1_b(3) , + mpw2_b => mpw2_b(0) , + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => fpu_enable, + scout => ex3_ctl_so , + scin => ex3_ctl_si , + din(0 to 3) => ex2_thread(0 to 3) , + din(4 to 7) => ex2_fpscr_bit_data(0 to 3) , + din(8 to 11) => ex2_fpscr_bit_mask(0 to 3) , + din(12 to 20) => ex2_fpscr_nib_mask(0 to 8) , + din(21) => ex2_mtfsbx , + din(22) => ex2_mcrfs , + din(23) => ex2_mtfsf , + din(24) => ex2_mtfsfi , + dout(0 to 3) => ex3_thread(0 to 3) , + dout(4 to 7) => ex3_fpscr_bit_data(0 to 3) , + dout(8 to 11) => ex3_fpscr_bit_mask(0 to 3) , + dout(12 to 20) => ex3_fpscr_nib_mask(0 to 8) , + dout(21) => ex3_mtfsbx , + dout(22) => ex3_mcrfs , + dout(23) => ex3_mtfsf , + dout(24) => ex3_mtfsfi ); + + f_cr2_ex3_thread_b(0 to 3) <= not ex3_thread(0 to 3) ; + f_cr2_ex3_fpscr_bit_data_b(0 to 3) <= not ex3_fpscr_bit_data(0 to 3); + f_cr2_ex3_fpscr_bit_mask_b(0 to 3) <= not ex3_fpscr_bit_mask(0 to 3); + f_cr2_ex3_fpscr_nib_mask_b(0 to 8) <= not ex3_fpscr_nib_mask(0 to 8); + f_cr2_ex3_mtfsbx_b <= not ex3_mtfsbx ; + f_cr2_ex3_mcrfs_b <= not ex3_mcrfs ; + f_cr2_ex3_mtfsf_b <= not ex3_mtfsf ; + f_cr2_ex3_mtfsfi_b <= not ex3_mtfsfi ; + + + + ex4_ctl_lat: tri_rlmreg_p generic map (width=> 5, expand_type => expand_type) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(4) , + mpw1_b => mpw1_b(4) , + mpw2_b => mpw2_b(0) , + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => fpu_enable, + scout => ex4_ctl_so , + scin => ex4_ctl_si , + din(0 to 3) => ex3_thread(0 to 3) , + din(4) => ex3_mv_to_op , + dout(0 to 3) => ex4_thread(0 to 3) , + dout(4) => ex4_mv_to_op ); + + + ex5_ctl_lat: tri_rlmreg_p generic map (width=> 5, expand_type => expand_type) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(5) , + mpw1_b => mpw1_b(5) , + mpw2_b => mpw2_b(1) , + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => fpu_enable, + scout => ex5_ctl_so , + scin => ex5_ctl_si , + din(0 to 3) => ex4_thread(0 to 3) , + din(4) => ex4_mv_to_op, + dout(0 to 3) => ex5_thread(0 to 3) , + dout(4) => ex5_mv_to_op ); + + ex6_ctl_lat: tri_rlmreg_p generic map (width=> 5, expand_type => expand_type) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(6) , + mpw1_b => mpw1_b(6) , + mpw2_b => mpw2_b(1) , + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => fpu_enable, + scout => ex6_ctl_so , + scin => ex6_ctl_si , + din(0 to 3) => ex5_thread(0 to 3) , + din(4) => ex5_mv_to_op , + dout(0 to 3) => ex6_thread(0 to 3) , + dout(4) => ex6_mv_to_op ); + +ex6_cancel <= f_dcd_ex6_cancel; + + +f_cr2_ex5_fpscr_rd_dat(24 to 31) <= + ( (24 to 31 => ex5_thread(0)) and shadow0(0 to 7) ) or + ( (24 to 31 => ex5_thread(1)) and shadow1(0 to 7) ) or + ( (24 to 31 => ex5_thread(2)) and shadow2(0 to 7) ) or + ( (24 to 31 => ex5_thread(3)) and shadow3(0 to 7) ) ; + + +ex6_fpscr_rd_dat_no_byp(24 to 31) <= + ( (24 to 31 => ex6_thread(0)) and shadow0(0 to 7) ) or + ( (24 to 31 => ex6_thread(1)) and shadow1(0 to 7) ) or + ( (24 to 31 => ex6_thread(2)) and shadow2(0 to 7) ) or + ( (24 to 31 => ex6_thread(3)) and shadow3(0 to 7) ) ; + +f_cr2_ex6_fpscr_rd_dat(24 to 31) <= + ( (24 to 31 => ex6_mv_to_op) and shadow_byp6(0 to 7) ) or + ( (24 to 31 => not ex6_mv_to_op) and ex6_fpscr_rd_dat_no_byp(24 to 31) ) ; + + + + + ex1_bit_sel(0 to 3) <= ex1_fpscr_bit_mask(0 to 3) and (0 to 3 => ex1_mv_to_op and ex1_fpscr_nib_mask(6) ); + ex1_bit_sel(4 to 7) <= ex1_fpscr_bit_mask(0 to 3) and (0 to 3 => ex1_mv_to_op and ex1_fpscr_nib_mask(7) ); + + ex1_fpscr_data(0 to 3) <= + ( f_fmt_ex1_bop_byt(45 to 48) and (0 to 3=> ex1_mtfsf) ) or + ( ex1_fpscr_bit_data(0 to 3) and not (0 to 3=> ex1_mtfsf) ) ; + ex1_fpscr_data(4 to 7) <= + ( f_fmt_ex1_bop_byt(49 to 52) and (0 to 3=> ex1_mtfsf) ) or + ( ex1_fpscr_bit_data(0 to 3) and not (0 to 3=> ex1_mtfsf) ) ; + + shadow_byp2_din(0 to 7) <= + (ex1_fpscr_shadow_mux(0 to 7) and not ex1_bit_sel(0 to 7) ) or + (ex1_fpscr_data(0 to 7) and ex1_bit_sel(0 to 7) ) ; + + + + ex1_mv_to_op <= ex1_mtfsbx or ex1_mtfsf or ex1_mtfsfi ; + ex2_mv_to_op <= ex2_mtfsbx or ex2_mtfsf or ex2_mtfsfi ; + ex3_mv_to_op <= ex3_mtfsbx or ex3_mtfsf or ex3_mtfsfi ; + + + rf1_thread_match_1 <= + ( rf1_thread(0) and ex1_thread(0) ) or + ( rf1_thread(1) and ex1_thread(1) ) or + ( rf1_thread(2) and ex1_thread(2) ) or + ( rf1_thread(3) and ex1_thread(3) ) ; + + rf1_thread_match_2 <= + ( rf1_thread(0) and ex2_thread(0) ) or + ( rf1_thread(1) and ex2_thread(1) ) or + ( rf1_thread(2) and ex2_thread(2) ) or + ( rf1_thread(3) and ex2_thread(3) ) ; + + rf1_thread_match_3 <= + ( rf1_thread(0) and ex3_thread(0) ) or + ( rf1_thread(1) and ex3_thread(1) ) or + ( rf1_thread(2) and ex3_thread(2) ) or + ( rf1_thread(3) and ex3_thread(3) ) ; + + rf1_thread_match_4 <= + ( rf1_thread(0) and ex4_thread(0) ) or + ( rf1_thread(1) and ex4_thread(1) ) or + ( rf1_thread(2) and ex4_thread(2) ) or + ( rf1_thread(3) and ex4_thread(3) ) ; + + rf1_thread_match_5 <= + ( rf1_thread(0) and ex5_thread(0) ) or + ( rf1_thread(1) and ex5_thread(1) ) or + ( rf1_thread(2) and ex5_thread(2) ) or + ( rf1_thread(3) and ex5_thread(3) ) ; + + rf1_rd_sel_byp2 <= rf1_thread_match_1 and ex1_mv_to_op ; + rf1_rd_sel_byp3 <= rf1_thread_match_2 and ex2_mv_to_op ; + rf1_rd_sel_byp4 <= rf1_thread_match_3 and ex3_mv_to_op ; + rf1_rd_sel_byp5 <= rf1_thread_match_4 and ex4_mv_to_op ; + rf1_rd_sel_byp6 <= rf1_thread_match_5 and ex5_mv_to_op ; + + rf1_rd_sel_0 <= rf1_thread(0) and not rf1_rd_sel_byp2 and not rf1_rd_sel_byp3 and not rf1_rd_sel_byp4 and not rf1_rd_sel_byp5 and not rf1_rd_sel_byp6 ; + rf1_rd_sel_1 <= rf1_thread(1) and not rf1_rd_sel_byp2 and not rf1_rd_sel_byp3 and not rf1_rd_sel_byp4 and not rf1_rd_sel_byp5 and not rf1_rd_sel_byp6 ; + rf1_rd_sel_2 <= rf1_thread(2) and not rf1_rd_sel_byp2 and not rf1_rd_sel_byp3 and not rf1_rd_sel_byp4 and not rf1_rd_sel_byp5 and not rf1_rd_sel_byp6 ; + rf1_rd_sel_3 <= rf1_thread(3) and not rf1_rd_sel_byp2 and not rf1_rd_sel_byp3 and not rf1_rd_sel_byp4 and not rf1_rd_sel_byp5 and not rf1_rd_sel_byp6 ; + + + rf1_rd_sel_byp2_pri <= rf1_rd_sel_byp2; + rf1_rd_sel_byp3_pri <= not rf1_rd_sel_byp2 and rf1_rd_sel_byp3; + rf1_rd_sel_byp4_pri <= not rf1_rd_sel_byp2 and not rf1_rd_sel_byp3 and rf1_rd_sel_byp4; + rf1_rd_sel_byp5_pri <= not rf1_rd_sel_byp2 and not rf1_rd_sel_byp3 and not rf1_rd_sel_byp4 and rf1_rd_sel_byp5; + rf1_rd_sel_byp6_pri <= not rf1_rd_sel_byp2 and not rf1_rd_sel_byp3 and not rf1_rd_sel_byp4 and not rf1_rd_sel_byp5 and rf1_rd_sel_byp6 ; + + + + ex1_fpscr_shadow_mux(0 to 7) <= + ( (0 to 7 => ex1_rd_sel_0) and shadow0 (0 to 7) ) or + ( (0 to 7 => ex1_rd_sel_1) and shadow1 (0 to 7) ) or + ( (0 to 7 => ex1_rd_sel_2) and shadow2 (0 to 7) ) or + ( (0 to 7 => ex1_rd_sel_3) and shadow3 (0 to 7) ) or + ( (0 to 7 => ex1_rd_sel_byp2) and shadow_byp2(0 to 7) ) or + ( (0 to 7 => ex1_rd_sel_byp3) and shadow_byp3(0 to 7) ) or + ( (0 to 7 => ex1_rd_sel_byp4) and shadow_byp4(0 to 7) ) or + ( (0 to 7 => ex1_rd_sel_byp5) and shadow_byp5(0 to 7) ) or + ( (0 to 7 => ex1_rd_sel_byp6) and shadow_byp6(0 to 7) ) ; + + f_cr2_ex1_fpscr_shadow(0 to 7) <= ex1_fpscr_shadow_mux(0 to 7); + + + + shadow_byp2_lat: tri_rlmreg_p generic map (width=> 8, expand_type => expand_type) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(2) , + mpw1_b => mpw1_b(2) , + mpw2_b => mpw2_b(0) , + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => ex1_act, + scout => shadow_byp2_so , + scin => shadow_byp2_si , + din => shadow_byp2_din(0 to 7), + dout => shadow_byp2 (0 to 7) ); + + shadow_byp3_lat: tri_rlmreg_p generic map (width=> 8, expand_type => expand_type) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(3) , + mpw1_b => mpw1_b(3) , + mpw2_b => mpw2_b(0) , + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => ex2_act, + scout => shadow_byp3_so , + scin => shadow_byp3_si , + din => shadow_byp2(0 to 7), + dout => shadow_byp3(0 to 7) ); + + shadow_byp4_lat: tri_rlmreg_p generic map (width=> 8, expand_type => expand_type) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(4) , + mpw1_b => mpw1_b(4) , + mpw2_b => mpw2_b(0) , + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => ex3_act, + scout => shadow_byp4_so , + scin => shadow_byp4_si , + din => shadow_byp3(0 to 7), + dout => shadow_byp4(0 to 7) ); + + shadow_byp5_lat: tri_rlmreg_p generic map (width=> 8, expand_type => expand_type) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(5) , + mpw1_b => mpw1_b(5) , + mpw2_b => mpw2_b(1) , + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => ex4_act, + scout => shadow_byp5_so , + scin => shadow_byp5_si , + din => shadow_byp4(0 to 7), + dout => shadow_byp5(0 to 7) ); + + shadow_byp6_lat: tri_rlmreg_p generic map (width=> 8, expand_type => expand_type) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(6) , + mpw1_b => mpw1_b(6) , + mpw2_b => mpw2_b(1) , + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => ex5_act, + scout => shadow_byp6_so , + scin => shadow_byp6_si , + din => shadow_byp5(0 to 7), + dout => shadow_byp6(0 to 7) ); + + ex6_th0_act <= ex6_act and ex6_thread(0) and not ex6_cancel and ex6_mv_to_op ; + ex6_th1_act <= ex6_act and ex6_thread(1) and not ex6_cancel and ex6_mv_to_op ; + ex6_th2_act <= ex6_act and ex6_thread(2) and not ex6_cancel and ex6_mv_to_op ; + ex6_th3_act <= ex6_act and ex6_thread(3) and not ex6_cancel and ex6_mv_to_op ; + + + + shadow0_lat: tri_rlmreg_p generic map (width=> 8, expand_type => expand_type) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(7) , + mpw1_b => mpw1_b(7) , + mpw2_b => mpw2_b(1) , + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => ex6_th0_act, + scout => shadow0_so , + scin => shadow0_si , + din => shadow_byp6(0 to 7), + dout => shadow0(0 to 7) ); + + shadow1_lat: tri_rlmreg_p generic map (width=> 8, expand_type => expand_type) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(7) , + mpw1_b => mpw1_b(7) , + mpw2_b => mpw2_b(1) , + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => ex6_th1_act, + scout => shadow1_so , + scin => shadow1_si , + din => shadow_byp6(0 to 7), + dout => shadow1(0 to 7) ); + + shadow2_lat: tri_rlmreg_p generic map (width=> 8, expand_type => expand_type) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(7) , + mpw1_b => mpw1_b(7) , + mpw2_b => mpw2_b(1) , + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => ex6_th2_act, + scout => shadow2_so , + scin => shadow2_si , + din => shadow_byp6(0 to 7), + dout => shadow2(0 to 7) ); + + shadow3_lat: tri_rlmreg_p generic map (width=> 8, expand_type => expand_type) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(7) , + mpw1_b => mpw1_b(7) , + mpw2_b => mpw2_b(1) , + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => ex6_th3_act, + scout => shadow3_so , + scin => shadow3_si , + din => shadow_byp6(0 to 7), + dout => shadow3(0 to 7) ); + + + + + + ex1_ctl_si (0 to 33) <= ex1_ctl_so (1 to 33) & f_cr2_si ; + ex2_ctl_si (0 to 24) <= ex2_ctl_so (1 to 24) & ex1_ctl_so (0); + ex3_ctl_si (0 to 24) <= ex3_ctl_so (1 to 24) & ex2_ctl_so (0); + ex4_ctl_si (0 to 4) <= ex4_ctl_so (1 to 4) & ex3_ctl_so (0); + ex5_ctl_si (0 to 4) <= ex5_ctl_so (1 to 4) & ex4_ctl_so (0); + ex6_ctl_si (0 to 4) <= ex6_ctl_so (1 to 4) & ex5_ctl_so (0); + shadow0_si (0 to 7) <= shadow0_so (1 to 7) & ex6_ctl_so (0); + shadow1_si (0 to 7) <= shadow1_so (1 to 7) & shadow0_so (0); + shadow2_si (0 to 7) <= shadow2_so (1 to 7) & shadow1_so (0); + shadow3_si (0 to 7) <= shadow3_so (1 to 7) & shadow2_so (0); + shadow_byp2_si (0 to 7) <= shadow_byp2_so (1 to 7) & shadow3_so (0); + shadow_byp3_si (0 to 7) <= shadow_byp3_so (1 to 7) & shadow_byp2_so (0); + shadow_byp4_si (0 to 7) <= shadow_byp4_so (1 to 7) & shadow_byp3_so (0); + shadow_byp5_si (0 to 7) <= shadow_byp5_so (1 to 7) & shadow_byp4_so (0); + shadow_byp6_si (0 to 7) <= shadow_byp6_so (1 to 7) & shadow_byp5_so (0); + act_si (0 to 6) <= act_so (1 to 6) & shadow_byp6_so (0); + f_cr2_so <= act_so (0) ; + + + +end; + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_csa22_h2.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_csa22_h2.vhdl new file mode 100644 index 0000000..c35cf13 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_csa22_h2.vhdl @@ -0,0 +1,63 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee; use ieee.std_logic_1164.all ; +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + +ENTITY fuq_csa22_h2 IS + PORT( + a : IN std_ulogic; + b : IN std_ulogic; + car : OUT std_ulogic; + sum : OUT std_ulogic + ); +END fuq_csa22_h2; + +ARCHITECTURE fuq_csa22_h2 OF fuq_csa22_h2 IS + + signal car_b, sum_b : std_ulogic; + + + +BEGIN + + u_22nandc: car_b <= not( a and b ); + u_22nands: sum_b <= not( car_b and (a or b) ); + u_22invc: car <= not car_b; + u_22invs: sum <= not sum_b ; + +END; + + + + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_dcd.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_dcd.vhdl new file mode 100644 index 0000000..2443da3 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_dcd.vhdl @@ -0,0 +1,2636 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library IEEE,ibm,clib; +use IEEE.STD_LOGIC_1164.all; + +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_support.all; +library support; +use support.power_logic_pkg.all; + + +library tri; use tri.tri_latches_pkg.all; + +entity fuq_dcd is +generic( + expand_type : integer := 2 ; + eff_ifar : integer := 62; + regmode : integer := 6); +port( + nclk : in clk_logic; + clkoff_b : in std_ulogic; + act_dis : in std_ulogic; + flush : in std_ulogic; + delay_lclkr : in std_ulogic_vector(0 to 9); + mpw1_b : in std_ulogic_vector(0 to 9); + mpw2_b : in std_ulogic_vector(0 to 1); + thold_1 : in std_ulogic; + cfg_sl_thold_1 : in std_ulogic; + func_slp_sl_thold_1 : in std_ulogic; + + sg_1 : in std_ulogic; + f_dcd_si : in std_ulogic; + f_dcd_so : out std_ulogic; + dcfg_scan_in : in std_ulogic; + dcfg_scan_out : out std_ulogic; + bcfg_scan_in : in std_ulogic; + bcfg_scan_out : out std_ulogic; + ccfg_scan_in : in std_ulogic; + ccfg_scan_out : out std_ulogic; + vdd : inout power_logic; + gnd : inout power_logic; + f_dcd_msr_fp_act : out std_ulogic; + fu_xu_rf1_act : out std_ulogic_vector(0 to 3); + + iu_fu_rf0_instr_v : in std_ulogic; + iu_fu_rf0_instr : in std_ulogic_vector(0 to 31); + iu_fu_rf0_fra_v : in std_ulogic; + iu_fu_rf0_frb_v : in std_ulogic; + iu_fu_rf0_frc_v : in std_ulogic; + iu_fu_rf0_tid : in std_ulogic_vector(0 to 1); + iu_fu_rf0_fra : in std_ulogic_vector(0 to 6); + iu_fu_rf0_frb : in std_ulogic_vector(0 to 6); + iu_fu_rf0_frc : in std_ulogic_vector(0 to 6); + iu_fu_rf0_frt : in std_ulogic_vector(0 to 6); + iu_fu_rf0_ifar : in std_ulogic_vector(62-eff_ifar to 61); + iu_fu_rf0_str_val : in std_ulogic; + iu_fu_rf0_ldst_val : in std_ulogic; + iu_fu_rf0_ldst_tid : in std_ulogic_vector(0 to 1); + iu_fu_rf0_ldst_tag : in std_ulogic_vector(0 to 8); + iu_fu_rf0_bypsel : in std_ulogic_vector(0 to 5); + iu_fu_rf0_instr_match : in std_ulogic; + iu_fu_rf0_is_ucode : in std_ulogic; + iu_fu_rf0_ucfmul : in std_ulogic; + iu_fu_is2_tid_decode : in std_ulogic_vector(0 to 3); + iu_fu_ex2_n_flush : in std_ulogic_vector(0 to 3); + + f_fpr_ex7_load_addr : in std_ulogic_vector(0 to 7); + f_fpr_ex7_load_v : in std_ulogic; + xu_is2_flush : in std_ulogic_vector(0 to 3); + xu_rf0_flush : in std_ulogic_vector(0 to 3); + xu_rf1_flush : in std_ulogic_vector(0 to 3); + xu_ex1_flush : in std_ulogic_vector(0 to 3); + xu_ex2_flush : in std_ulogic_vector(0 to 3); + xu_ex3_flush : in std_ulogic_vector(0 to 3); + xu_ex4_flush : in std_ulogic_vector(0 to 3); + xu_ex5_flush : in std_ulogic_vector(0 to 3); + f_dcd_ex5_flush_int : out std_ulogic_vector(0 to 3); + xu_fu_ex5_reload_val : in std_ulogic; + xu_fu_ex5_load_val : in std_ulogic_vector(0 to 3); + + f_dcd_perr_sm_running : out std_ulogic; + + f_scr_ex7_cr_fld : in std_ulogic_vector (0 to 3) ; + f_add_ex4_fpcc_iu : in std_ulogic_vector (0 to 3) ; + f_pic_ex5_fpr_wr_dis_b : in std_ulogic ; + f_dcd_rf1_aop_valid : out std_ulogic; + f_dcd_rf1_cop_valid : out std_ulogic; + f_dcd_rf1_bop_valid : out std_ulogic; + f_dcd_rf1_sp : out std_ulogic; + f_dcd_rf1_emin_dp : out std_ulogic; + f_dcd_rf1_emin_sp : out std_ulogic; + f_dcd_rf1_force_pass_b : out std_ulogic; + + f_dcd_rf1_fsel_b : out std_ulogic; + f_dcd_rf1_from_integer_b : out std_ulogic; + f_dcd_rf1_to_integer_b : out std_ulogic; + f_dcd_rf1_rnd_to_int_b : out std_ulogic; + f_dcd_rf1_math_b : out std_ulogic; + f_dcd_rf1_est_recip_b : out std_ulogic; + f_dcd_rf1_est_rsqrt_b : out std_ulogic; + f_dcd_rf1_move_b : out std_ulogic; + f_dcd_rf1_prenorm_b : out std_ulogic; + f_dcd_rf1_frsp_b : out std_ulogic; + f_dcd_rf1_compare_b : out std_ulogic; + f_dcd_rf1_ordered_b : out std_ulogic; + + f_dcd_rf1_force_excp_dis : out std_ulogic; + f_dcd_rf1_nj_deni : out std_ulogic; + f_dcd_rf1_nj_deno : out std_ulogic; + f_dcd_rf1_sp_conv_b : out std_ulogic; + f_dcd_rf1_uns_b : out std_ulogic; + + f_dcd_rf1_word_b : out std_ulogic; + f_dcd_rf1_sub_op_b : out std_ulogic; + f_dcd_rf1_op_rnd_v_b : out std_ulogic; + f_dcd_rf1_op_rnd_b : out std_ulogic_vector(0 to 1); + f_dcd_rf1_inv_sign_b : out std_ulogic; + f_dcd_rf1_sign_ctl_b : out std_ulogic_vector(0 to 1); + f_dcd_rf1_sgncpy_b : out std_ulogic; + + f_dcd_rf1_fpscr_bit_data_b : out std_ulogic_vector(0 to 3); + f_dcd_rf1_fpscr_bit_mask_b : out std_ulogic_vector(0 to 3); + f_dcd_rf1_fpscr_nib_mask_b : out std_ulogic_vector(0 to 8); + f_dcd_rf1_mv_to_scr_b : out std_ulogic; + f_dcd_rf1_mv_from_scr_b : out std_ulogic; + f_dcd_rf1_mtfsbx_b : out std_ulogic; + f_dcd_rf1_mcrfs_b : out std_ulogic; + f_dcd_rf1_mtfsf_b : out std_ulogic; + f_dcd_rf1_mtfsfi_b : out std_ulogic; + f_dcd_rf1_thread_b : out std_ulogic_vector(0 to 3); + f_dcd_rf1_sto_dp : out std_ulogic ; + f_dcd_rf1_sto_sp : out std_ulogic ; + f_dcd_rf1_sto_wd : out std_ulogic ; + f_dcd_rf1_log2e_b : out std_ulogic ; + f_dcd_rf1_pow2e_b : out std_ulogic ; + f_dcd_rf1_ftdiv : out std_ulogic ; + f_dcd_rf1_ftsqrt : out std_ulogic ; + f_dcd_rf1_mad_act : out std_ulogic ; + f_dcd_rf1_sto_act : out std_ulogic ; + f_dcd_ex6_cancel : out std_ulogic ; + f_dcd_rf1_bypsel_a_res0 : out std_ulogic; + f_dcd_rf1_bypsel_a_load0 : out std_ulogic; + f_dcd_rf1_bypsel_b_res0 : out std_ulogic; + f_dcd_rf1_bypsel_b_load0 : out std_ulogic; + f_dcd_rf1_bypsel_c_res0 : out std_ulogic; + f_dcd_rf1_bypsel_c_load0 : out std_ulogic; + f_dcd_rf0_bypsel_a_res1 : out std_ulogic; + f_dcd_rf0_bypsel_b_res1 : out std_ulogic; + f_dcd_rf0_bypsel_c_res1 : out std_ulogic; + f_dcd_rf0_bypsel_s_res1 : out std_ulogic; + f_dcd_rf0_bypsel_a_load1 : out std_ulogic; + f_dcd_rf0_bypsel_b_load1 : out std_ulogic; + f_dcd_rf0_bypsel_c_load1 : out std_ulogic; + f_dcd_rf0_bypsel_s_load1 : out std_ulogic; + f_dcd_ex1_perr_force_c : out std_ulogic; + f_dcd_ex1_perr_fsel_ovrd : out std_ulogic; + + slowspr_val_in : in std_ulogic; + slowspr_rw_in : in std_ulogic; + slowspr_etid_in : in std_ulogic_vector(0 to 1); + slowspr_addr_in : in std_ulogic_vector(0 to 9); + slowspr_data_in : in std_ulogic_vector(64-(2**regmode) to 63); + slowspr_done_in : in std_ulogic; + slowspr_val_out : out std_ulogic; + slowspr_rw_out : out std_ulogic; + slowspr_etid_out : out std_ulogic_vector(0 to 1); + slowspr_addr_out : out std_ulogic_vector(0 to 9); + slowspr_data_out : out std_ulogic_vector(64-(2**regmode) to 63); + slowspr_done_out : out std_ulogic; + pc_fu_trace_bus_enable : in std_ulogic; + pc_fu_event_bus_enable : in std_ulogic; + pc_fu_debug_mux_ctrls : in std_ulogic_vector(0 to 15); + pc_fu_event_count_mode : in std_ulogic_vector(0 to 2); + pc_fu_event_mux_ctrls : in std_ulogic_vector(0 to 31); + debug_data_in : in std_ulogic_vector(0 to 87); + debug_data_out : out std_ulogic_vector(0 to 87); + trace_triggers_in : in std_ulogic_vector(0 to 11); + trace_triggers_out : out std_ulogic_vector(0 to 11); + fu_pc_event_data : out std_ulogic_vector(0 to 7); + f_rnd_ex6_res_expo : in std_ulogic_vector (1 to 13); + f_rnd_ex6_res_frac : in std_ulogic_vector (0 to 52); + f_rnd_ex6_res_sign : in std_ulogic ; + pc_fu_ram_mode : in std_ulogic; + pc_fu_ram_thread : in std_ulogic_vector(0 to 1); + fu_pc_ram_done : out std_ulogic; + fu_pc_ram_data : out std_ulogic_vector(0 to 63); + f_sto_ex2_s_parity_check : in std_ulogic; + f_mad_ex2_a_parity_check : in std_ulogic; + f_mad_ex2_b_parity_check : in std_ulogic; + f_mad_ex2_c_parity_check : in std_ulogic; + fu_pc_err_regfile_parity : out std_ulogic_vector(0 to 3); + fu_pc_err_regfile_ue : out std_ulogic_vector(0 to 3); + fu_xu_ex3_regfile_err_det : out std_ulogic_vector(0 to 3); + xu_fu_regfile_seq_beg : in std_ulogic; + fu_xu_regfile_seq_end : out std_ulogic; + fu_xu_ex2_async_block : out std_ulogic_vector(0 to 3); + + xu_fu_msr_fp : in std_ulogic_vector(0 to 3); + xu_fu_msr_pr : in std_ulogic_vector(0 to 3); + xu_fu_msr_gs : in std_ulogic_vector(0 to 3); + pc_fu_instr_trace_mode : in std_ulogic; + pc_fu_instr_trace_tid : in std_ulogic_vector(0 to 1); + + f_dcd_ex6_frt_addr : out std_ulogic_vector(0 to 5); + f_dcd_ex6_frt_tid : out std_ulogic_vector(0 to 1); + f_dcd_ex5_frt_tid : out std_ulogic_vector(0 to 1); + f_dcd_ex6_frt_wen : out std_ulogic; + fu_xu_ex2_store_data_val : out std_ulogic; + fu_xu_ex4_cr : out std_ulogic_vector(0 to 3); + fu_xu_ex4_cr_val : out std_ulogic_vector(0 to 3); + fu_xu_ex4_cr_bf : out std_ulogic_vector(0 to 2); + fu_xu_ex4_cr_noflush : out std_ulogic_vector(0 to 3); + f_scr_ex7_fx_thread0 : in std_ulogic_vector(0 to 3); + f_scr_ex7_fx_thread1 : in std_ulogic_vector(0 to 3); + f_scr_ex7_fx_thread2 : in std_ulogic_vector(0 to 3); + f_scr_ex7_fx_thread3 : in std_ulogic_vector(0 to 3); + f_dcd_rf0_tid : out std_ulogic_vector(0 to 1); + f_dcd_rf0_fra : out std_ulogic_vector(0 to 5); + f_dcd_rf0_frb : out std_ulogic_vector(0 to 5); + f_dcd_rf0_frc : out std_ulogic_vector(0 to 5); + f_dcd_rf1_div_beg : out std_ulogic; + f_dcd_rf1_sqrt_beg : out std_ulogic; + f_dcd_rf1_uc_ft_pos : out std_ulogic; + f_dcd_rf1_uc_ft_neg : out std_ulogic; + f_dcd_rf1_uc_fa_pos : out std_ulogic; + f_dcd_rf1_uc_fc_pos : out std_ulogic; + f_dcd_rf1_uc_fb_pos : out std_ulogic; + f_dcd_rf1_uc_fc_hulp : out std_ulogic; + f_dcd_rf1_uc_fc_0_5 : out std_ulogic; + f_dcd_rf1_uc_fc_1_0 : out std_ulogic; + f_dcd_rf1_uc_fc_1_minus : out std_ulogic; + f_dcd_rf1_uc_fb_1_0 : out std_ulogic; + f_dcd_rf1_uc_fb_0_75 : out std_ulogic; + f_dcd_rf1_uc_fb_0_5 : out std_ulogic; + f_dcd_ex2_uc_inc_lsb : out std_ulogic; + f_dcd_rf1_uc_mid : out std_ulogic; + f_dcd_rf1_uc_end : out std_ulogic; + fu_iu_uc_special : out std_ulogic_vector(0 to 3); + f_dcd_rf1_uc_special : out std_ulogic; + f_dcd_ex2_uc_gs_v : out std_ulogic; + f_dcd_ex2_uc_gs : out std_ulogic_vector(0 to 1); + f_dcd_ex2_uc_vxsnan : out std_ulogic; + f_dcd_ex2_uc_zx : out std_ulogic; + f_dcd_ex2_uc_vxidi : out std_ulogic; + f_dcd_ex2_uc_vxzdz : out std_ulogic; + f_dcd_ex2_uc_vxsqrt : out std_ulogic; + f_mad_ex6_uc_sign : in std_ulogic; + f_mad_ex6_uc_zero : in std_ulogic; + f_mad_ex3_uc_special : in std_ulogic; + f_mad_ex3_uc_vxsnan : in std_ulogic; + f_mad_ex3_uc_zx : in std_ulogic; + f_mad_ex3_uc_vxidi : in std_ulogic; + f_mad_ex3_uc_vxzdz : in std_ulogic; + f_mad_ex3_uc_vxsqrt : in std_ulogic; + f_mad_ex3_uc_res_sign : in std_ulogic; + f_mad_ex3_uc_round_mode : in std_ulogic_vector(0 to 1); + + f_ex2_b_den_flush : in std_ulogic; + xu_fu_ex3_eff_addr : in std_ulogic_vector(59 to 63); + fu_xu_ex3_n_flush : out std_ulogic_vector(0 to 3); + fu_xu_ex3_np1_flush : out std_ulogic_vector(0 to 3); + fu_xu_ex3_ap_int_req : out std_ulogic_vector(0 to 3); + fu_xu_ex3_flush2ucode : out std_ulogic_vector(0 to 3); + fu_xu_ex2_instr_type : out std_ulogic_vector(0 to 11); + fu_xu_ex2_instr_match : out std_ulogic_vector(0 to 3); + fu_xu_ex2_is_ucode : out std_ulogic_vector(0 to 3); + fu_xu_ex3_trap : out std_ulogic_vector(0 to 3); + fu_xu_ex2_ifar_val : out std_ulogic_vector(0 to 3); + fu_xu_ex2_ifar_issued : out std_ulogic_vector(0 to 3); + fu_xu_ex1_ifar : out std_ulogic_vector(62-eff_ifar to 61) +); + -- synopsys translate_off + + -- synopsys translate_on + +end fuq_dcd; + +architecture fuq_dcd of fuq_dcd is + + + + +signal tilo : std_ulogic; +signal tihi : std_ulogic; +signal tilo_out : std_ulogic; +signal tihi_out : std_ulogic; + +signal thold_0 : std_ulogic; +signal thold_0_b : std_ulogic; +signal sg_0 : std_ulogic; +signal forcee : std_ulogic; +signal cfg_sl_thold_0 : std_ulogic; +signal cfg_sl_thold_0_b : std_ulogic; +signal cfg_sl_force : std_ulogic; +signal func_slp_sl_thold_0 : std_ulogic; +signal func_slp_sl_force : std_ulogic; +signal func_slp_sl_thold_0_b : std_ulogic; + +signal rf0_str_v : std_ulogic; +signal rf0_ldst_valid : std_ulogic_vector(0 to 3); +signal rf0_str_tag : std_ulogic_vector(0 to 1); +signal rf0_instr_valid : std_ulogic_vector(0 to 3); +signal rf0_instr_fra : std_ulogic_vector(0 to 5); +signal rf0_instr_frb : std_ulogic_vector(0 to 5); +signal rf0_instr_frc : std_ulogic_vector(0 to 5); +signal rf0_instr_frs : std_ulogic_vector(0 to 5); +signal rf0_instr_frt : std_ulogic_vector(0 to 5); +signal rf0_instr_tid_1hot : std_ulogic_vector(0 to 3); +signal thread_id_rf0 : std_ulogic_vector(0 to 3); +signal rf0_thread_so, rf0_thread_si :std_ulogic_vector(0 to 3); +signal rf0_tid : std_ulogic_vector(0 to 1); +signal rf0_bypsel : std_ulogic_vector(0 to 5); +signal rf0_bypsel_a_res0 : std_ulogic; +signal rf0_bypsel_b_res0 : std_ulogic; +signal rf0_bypsel_c_res0 : std_ulogic; +signal rf0_bypsel_a_load0 : std_ulogic; +signal rf0_bypsel_b_load0 : std_ulogic; +signal rf0_bypsel_c_load0 : std_ulogic; +signal rf0_bypsel_a_res1 : std_ulogic; +signal rf0_bypsel_b_res1 : std_ulogic; +signal rf0_bypsel_s_res1 : std_ulogic; +signal rf0_bypsel_c_res1 : std_ulogic; +signal rf0_bypsel_a_load1 : std_ulogic; +signal rf0_bypsel_b_load1 : std_ulogic; +signal rf0_bypsel_c_load1 : std_ulogic; +signal rf0_bypsel_s_load1 : std_ulogic; +signal rf0_instr_match : std_ulogic; +signal rf0_is_ucode : std_ulogic; +signal rf0_frs_byp : std_ulogic; + +signal xu_ex5_flush_int : std_ulogic_vector(0 to 3); + +signal ex5_reload_val_b : std_ulogic_vector(0 to 3); + +signal rf1_v : std_ulogic; +signal rf1_axu_v : std_ulogic; +signal rf1_instr_v : std_ulogic_vector(0 to 3); +signal rf1_tid : std_ulogic_vector(0 to 1); +signal rf1_instr_valid : std_ulogic_vector(0 to 3); +signal rf1_instr : std_ulogic_vector(0 to 31); +signal rf1_instr_fra_v : std_ulogic; +signal rf1_instr_frb_v : std_ulogic; +signal rf1_instr_frc_v : std_ulogic; +signal rf1_instr_frt : std_ulogic_vector(0 to 5); +signal rf1_instr_fra : std_ulogic_vector(0 to 5); +signal rf1_instr_frb : std_ulogic_vector(0 to 5); +signal rf1_instr_frc : std_ulogic_vector(0 to 5); +signal rf1_instr_frs : std_ulogic_vector(0 to 5); +signal rf1_instr_ifar : std_ulogic_vector(62-eff_ifar to 61); +signal rf1_str_v : std_ulogic; +signal rf1_ldst_v : std_ulogic_vector(0 to 3); +signal rf1_ldst_valid : std_ulogic_vector(0 to 3); +signal rf1_str_tag : std_ulogic_vector(0 to 1); +signal rf1_bypsel_a_res0 : std_ulogic; +signal rf1_bypsel_b_res0 : std_ulogic; +signal rf1_bypsel_c_res0 : std_ulogic; +signal rf1_bypsel_a_load0 : std_ulogic; +signal rf1_bypsel_b_load0 : std_ulogic; +signal rf1_bypsel_c_load0 : std_ulogic; +signal rf1_bypsel_a_res1 : std_ulogic; +signal rf1_bypsel_b_res1 : std_ulogic; +signal rf1_bypsel_c_res1 : std_ulogic; +signal rf1_bypsel_a_load1 : std_ulogic; +signal rf1_bypsel_b_load1 : std_ulogic; +signal rf1_bypsel_c_load1 : std_ulogic; +signal rf1_frs_byp : std_ulogic; + +signal rf1_primary : std_ulogic_vector(0 to 5); +signal rf1_sec_xform : std_ulogic_vector(0 to 9); +signal rf1_sec_aform : std_ulogic_vector(0 to 4); +signal rf1_dp : std_ulogic; +signal rf1_sp : std_ulogic; +signal rf1_dporsp : std_ulogic; +signal rf1_fcfid : std_ulogic; +signal rf1_fcfidu : std_ulogic; +signal rf1_fcfids : std_ulogic; +signal rf1_fcfidus : std_ulogic; +signal rf1_fcfiwu : std_ulogic; +signal rf1_fcfiwus : std_ulogic; +signal rf1_fctid : std_ulogic; +signal rf1_fctidu : std_ulogic; +signal rf1_fctidz : std_ulogic; +signal rf1_fctiduz : std_ulogic; +signal rf1_frim : std_ulogic; +signal rf1_frin : std_ulogic; +signal rf1_frip : std_ulogic; +signal rf1_friz : std_ulogic; +signal rf1_frsp : std_ulogic; +signal rf1_fmr : std_ulogic; +signal rf1_fneg : std_ulogic; +signal rf1_fabs : std_ulogic; +signal rf1_fnabs : std_ulogic; +signal rf1_fsel : std_ulogic; +signal rf1_frsqrte : std_ulogic; +signal rf1_fres : std_ulogic; +signal rf1_fctiw : std_ulogic; +signal rf1_fctiwu : std_ulogic; +signal rf1_fctiwz : std_ulogic; +signal rf1_fctiwuz : std_ulogic; +signal rf1_fcmpu : std_ulogic; +signal rf1_fcmpo : std_ulogic; +signal rf1_fcpsgn : std_ulogic; +signal rf1_fadd : std_ulogic; +signal rf1_fsub : std_ulogic; +signal rf1_fmul : std_ulogic; +signal rf1_fmadd : std_ulogic; +signal rf1_fmsub : std_ulogic; +signal rf1_fnmadd : std_ulogic; +signal rf1_fnmsub : std_ulogic; +signal rf1_mffs : std_ulogic; +signal rf1_mcrfs : std_ulogic; +signal rf1_mtfsfi : std_ulogic; +signal rf1_mtfsf : std_ulogic; +signal rf1_mtfsb0 : std_ulogic; +signal rf1_mtfsb1 : std_ulogic; +signal rf1_cr_val : std_ulogic; +signal ex1_cr_val_din : std_ulogic; +signal rf1_record : std_ulogic; +signal rf1_moves : std_ulogic; +signal rf1_to_ints : std_ulogic; +signal rf1_from_ints : std_ulogic; +signal rf1_fpscr_moves : std_ulogic; +signal rf1_mtfsb_bt : std_ulogic_vector(0 to 3); +signal rf1_mtfs_bf : std_ulogic_vector(0 to 7); +signal rf1_mcrfs_bfa : std_ulogic_vector(0 to 7); +signal rf1_mtfsf_nib : std_ulogic_vector(0 to 7); +signal rf1_mtfsf_l : std_ulogic; +signal rf1_mtfsf_w : std_ulogic; +signal rf1_fpscr_bit_data : std_ulogic_vector(0 to 3); +signal rf1_fpscr_bit_mask : std_ulogic_vector(0 to 3); +signal rf1_fpscr_nib_mask : std_ulogic_vector(0 to 8); +signal rf1_loge : std_ulogic; +signal rf1_expte : std_ulogic; +signal rf1_ftdiv : std_ulogic; +signal rf1_ftsqrt : std_ulogic; +signal rf1_rnd0 : std_ulogic; +signal rf1_rnd1 : std_ulogic; +signal rf1_kill_wen : std_ulogic; +signal rf1_instr_match : std_ulogic; +signal rf1_is_ucode : std_ulogic; +signal rf1_prenorm : std_ulogic; +signal rf1_div_beg : std_ulogic; +signal rf1_sqrt_beg : std_ulogic; +signal rf1_divsqrt_beg : std_ulogic; +signal rf1_fra_v : std_ulogic; +signal rf1_frb_v : std_ulogic; +signal rf1_frc_v : std_ulogic; +signal rf1_byp_a : std_ulogic; +signal rf1_byp_b : std_ulogic; +signal rf1_byp_c : std_ulogic; +signal rf1_uc_end : std_ulogic; +signal f_dcd_rf1_uc_fa_dis_par : std_ulogic; +signal f_dcd_rf1_uc_fb_dis_par : std_ulogic; +signal f_dcd_rf1_uc_fc_dis_par : std_ulogic; + +signal ex1_v : std_ulogic; +signal ex1_axu_v : std_ulogic; +signal ex1_instr_v : std_ulogic_vector(0 to 3); +signal ex1_instr_valid : std_ulogic_vector(0 to 3); +signal ex1_instr_frt : std_ulogic_vector(0 to 5); +signal ex1_str_v : std_ulogic; +signal ex1_str_valid : std_ulogic; +signal ex1_ldst_v : std_ulogic_vector(0 to 3); +signal ex1_ldst_valid : std_ulogic_vector(0 to 3); +signal ex1_instr_ifar : std_ulogic_vector(62-eff_ifar to 61); +signal ex1_cr_val : std_ulogic; +signal ex1_record : std_ulogic; +signal ex1_kill_wen : std_ulogic; +signal ex1_mcrfs : std_ulogic; +signal ex1_instr_match : std_ulogic; +signal ex1_is_ucode : std_ulogic; +signal ex1_divsqrt_beg : std_ulogic; +signal ex1_ifar_val : std_ulogic_vector(0 to 3); +signal ex1_fra_v : std_ulogic; +signal ex1_frb_v : std_ulogic; +signal ex1_frc_v : std_ulogic; +signal ex1_fra_valid : std_ulogic; +signal ex1_frb_valid : std_ulogic; +signal ex1_frc_valid : std_ulogic; +signal ex1_frs_byp : std_ulogic; +signal ex1_async_block : std_ulogic_vector(0 to 3); + +signal ex2_axu_v : std_ulogic; +signal ex2_instr_v : std_ulogic_vector(0 to 3); +signal ex2_instr_valid : std_ulogic_vector(0 to 3); +signal ex2_instr_frt : std_ulogic_vector(0 to 5); +signal ex2_cr_val : std_ulogic; +signal ex2_record : std_ulogic; +signal ex2_kill_wen : std_ulogic; +signal ex2_mcrfs : std_ulogic; +signal ex2_instr_match : std_ulogic; +signal ex2_is_ucode : std_ulogic; +signal ex2_ifar_val : std_ulogic_vector(0 to 3); +signal ex2_iu_n_flush : std_ulogic_vector(0 to 3); +signal ex2_fra_v : std_ulogic; +signal ex2_frb_v : std_ulogic; +signal ex2_frc_v : std_ulogic; +signal ex2_sto_perr : std_ulogic_vector(0 to 3); +signal ex2_abc_perr : std_ulogic_vector(0 to 3); +signal ex2_fpr_perr : std_ulogic_vector(0 to 3); +signal ex2_ldst_v : std_ulogic_vector(0 to 3); +signal ex2_str_v : std_ulogic; +signal ex2_fu_or_ldst_v : std_ulogic_vector(0 to 3); +signal ex2_n_flush : std_ulogic_vector(0 to 3); +signal ex2_flush2ucode : std_ulogic_vector(0 to 3); +signal ex2_frs_byp : std_ulogic; +signal ex2_async_block : std_ulogic_vector(0 to 3); + +signal ex3_instr_v : std_ulogic_vector(0 to 3); +signal ex3_instr_valid : std_ulogic_vector(0 to 3); +signal ex3_instr_frt : std_ulogic_vector(0 to 5); +signal ex3_cr_val : std_ulogic; +signal ex3_record : std_ulogic; +signal ex3_b_den_flush : std_ulogic; +signal ex4_b_den_flush_din : std_ulogic; +signal ex3_kill_wen : std_ulogic; +signal ex3_mcrfs : std_ulogic; +signal ex3_instr_match : std_ulogic; +signal ex3_is_ucode : std_ulogic; +signal ex3_n_flush : std_ulogic_vector(0 to 3); +signal ex3_flush2ucode : std_ulogic_vector(0 to 3); + +signal ex4_instr_v : std_ulogic_vector(0 to 3); +signal ex4_instr_valid : std_ulogic_vector(0 to 3); +signal ex4_instr_tid : std_ulogic_vector(0 to 1); +signal ex4_instr_frt : std_ulogic_vector(0 to 5); +signal ex5_instr_frt_din : std_ulogic_vector(0 to 5); +signal ex4_cr_val, ex4_cr_val_cp, ex4_cr_val_cp_b : std_ulogic; +signal ex4_fpcc_x_b, ex7_cr_fld_x_b :std_ulogic_vector(0 to 3); +signal ex4_record : std_ulogic; +signal ex4_kill_wen : std_ulogic; +signal ex4_mcrfs : std_ulogic; +signal ex4_is_ucode : std_ulogic; +signal ex4_b_den_flush : std_ulogic; +signal ex4_uc_special : std_ulogic; + +signal ex5_instr_valid_din : std_ulogic_vector(0 to 3); +signal ex5_instr_v : std_ulogic_vector(0 to 3); +signal ex5_instr_valid : std_ulogic_vector(0 to 3); +signal ex5_instr_bypval : std_ulogic_vector(0 to 3); +signal ex5_instr_tid : std_ulogic_vector(0 to 1); +signal ex5_instr_frt : std_ulogic_vector(0 to 5); +signal ex5_record_din : std_ulogic; +signal ex5_mcrfs_din : std_ulogic; +signal ex5_record : std_ulogic; +signal ex5_mcrfs : std_ulogic; +signal ex5_is_ucode : std_ulogic; +signal ex5_instr_flush : std_ulogic; +signal ex5_cr_val_din : std_ulogic; +signal ex5_cr_val : std_ulogic; +signal ex5_kill_wen_din : std_ulogic; +signal ex5_kill_wen : std_ulogic; +signal ex6_instr_valid_din : std_ulogic_vector(0 to 3); + +signal ex6_instr_v : std_ulogic_vector(0 to 3); +signal ex6_instr_valid : std_ulogic; +signal ex6_instr_tid : std_ulogic_vector(0 to 1); +signal ex6_instr_frt : std_ulogic_vector(0 to 5); +signal ex6_record : std_ulogic; +signal ex6_record_v : std_ulogic_vector(0 to 3); +signal ex6_bf : std_ulogic_vector(0 to 2); +signal ex6_mcrfs : std_ulogic; +signal ex6_is_ucode : std_ulogic; +signal ex6_is_fixperr : std_ulogic; +signal ex6_record_din : std_ulogic; +signal ex6_mcrfs_din : std_ulogic; +signal ex6_cr_val_din : std_ulogic; +signal ex6_cr_val : std_ulogic; +signal ex6_kill_wen : std_ulogic; +signal ex6_kill_wen_din : std_ulogic; + +signal ex7_record_v : std_ulogic_vector(0 to 3); +signal ex7_bf : std_ulogic_vector(0 to 2); + +signal rf1_uc_op_rnd_v : std_ulogic; +signal rf1_uc_op_rnd : std_ulogic_vector(0 to 1); + +signal ex1_instr_frs : std_ulogic_vector(0 to 5); +signal ex1_instr_fra : std_ulogic_vector(0 to 5); +signal ex1_instr_frb : std_ulogic_vector(0 to 5); +signal ex1_instr_frc : std_ulogic_vector(0 to 5); +signal ex1_perr_si, ex1_perr_so : std_ulogic_vector(0 to 23); +signal ex2_instr_frs : std_ulogic_vector(0 to 5); +signal ex2_instr_fra : std_ulogic_vector(0 to 5); +signal ex2_instr_frb : std_ulogic_vector(0 to 5); +signal ex2_instr_frc : std_ulogic_vector(0 to 5); +signal ex2_perr_si, ex2_perr_so : std_ulogic_vector(0 to 23); +signal ex2_f0a_perr : std_ulogic; +signal ex2_f0c_perr : std_ulogic; +signal ex2_f1b_perr : std_ulogic; +signal ex2_f1s_perr : std_ulogic; +signal perr_sm_ns : std_ulogic_vector(0 to 2); +signal perr_sm_si, perr_sm_so : std_ulogic_vector(0 to 2); +signal perr_sm_din : std_ulogic_vector(0 to 2); +signal perr_sm_l2 : std_ulogic_vector(0 to 2); +signal perr_ctl_si, perr_ctl_so : std_ulogic_vector(0 to 24); +signal perr_addr_din : std_ulogic_vector(0 to 5); +signal perr_addr_l2 : std_ulogic_vector(0 to 5); +signal perr_tid_din : std_ulogic_vector(0 to 3); +signal perr_tid_l2 : std_ulogic_vector(0 to 3); +signal perr_tid_enc : std_ulogic_vector(0 to 1); +signal new_perr_sm_instr_v : std_ulogic; +signal rf0_perr_sm_instr_v : std_ulogic; +signal rf0_perr_sm_instr_v_b : std_ulogic; +signal rf0_frc_perr_x_b : std_ulogic_vector(0 to 5); +signal rf0_frc_iu_x_b : std_ulogic_vector(0 to 5); +signal rf0_frb_perr_x_b : std_ulogic_vector(0 to 5); +signal rf0_frb_iu_x_b : std_ulogic_vector(0 to 5); +signal rf0_tid_perr_x_b : std_ulogic_vector(0 to 1); +signal rf0_tid_iu_x_b : std_ulogic_vector(0 to 1); +signal rf1_perr_sm_instr_v : std_ulogic; +signal ex1_perr_sm_instr_v : std_ulogic; +signal ex2_perr_sm_instr_v : std_ulogic; +signal ex3_perr_sm_instr_v : std_ulogic; +signal ex4_perr_sm_instr_v : std_ulogic; +signal ex5_perr_sm_instr_v : std_ulogic; +signal perr_move_f0_to_f1 : std_ulogic; +signal perr_move_f1_to_f0 : std_ulogic; +signal perr_move_f0_to_f1_l2 : std_ulogic; +signal perr_move_f1_to_f0_l2 : std_ulogic; +signal rf0_perr_move_f0_to_f1 : std_ulogic; +signal rf0_perr_move_f1_to_f0 : std_ulogic; +signal rf0_perr_force_c : std_ulogic; +signal rf1_perr_force_c : std_ulogic; +signal ex1_perr_force_c : std_ulogic; +signal regfile_seq_beg : std_ulogic; +signal regfile_seq_end : std_ulogic; +signal ex2_regfile_err_det : std_ulogic; +signal ex3_regfile_err_det : std_ulogic_vector(0 to 3); +signal rf0_regfile_ue : std_ulogic; +signal rf0_regfile_ce : std_ulogic; +signal rf1_regfile_ue : std_ulogic; +signal rf1_regfile_ce : std_ulogic; +signal ex4_eff_addr : std_ulogic_vector(59 to 63); +signal err_regfile_parity : std_ulogic_vector(0 to 3); +signal err_regfile_ue : std_ulogic_vector(0 to 3); + +signal slowspr_in_val : std_ulogic; +signal slowspr_in_rw : std_ulogic; +signal slowspr_in_etid : std_ulogic_vector(0 to 1); +signal slowspr_in_addr : std_ulogic_vector(0 to 9); +signal slowspr_in_data : std_ulogic_vector(64-(2**regmode) to 63); +signal slowspr_in_done : std_ulogic; +signal slowspr_out_val : std_ulogic; +signal slowspr_out_rw : std_ulogic; +signal slowspr_out_etid : std_ulogic_vector(0 to 1); +signal slowspr_out_addr : std_ulogic_vector(0 to 9); +signal slowspr_out_data : std_ulogic_vector(64-(2**regmode) to 63); +signal slowspr_out_done : std_ulogic; +signal axucr0_dec : std_ulogic; +signal axucr0_rd : std_ulogic; +signal axucr0_wr : std_ulogic; +signal axucr0_din : std_ulogic_vector(61 to 63); +signal axucr0_q : std_ulogic_vector(61 to 63); +signal debug_data_d : std_ulogic_vector(0 to 87); +signal debug_data_q : std_ulogic_vector(0 to 87); +signal debug_trig_d : std_ulogic_vector(0 to 11); +signal debug_trig_q : std_ulogic_vector(0 to 11); +signal debug_mux_ctrls_q : std_ulogic_vector(0 to 15); +signal debug_mux_ctrls_muxed : std_ulogic_vector(0 to 15); + +signal trace_data_in : std_ulogic_vector(0 to 87); +signal trigger_data_in : std_ulogic_vector(0 to 11); +signal dbg_group0 : std_ulogic_vector(0 to 87); +signal dbg_group1 : std_ulogic_vector(0 to 87); +signal dbg_group2 : std_ulogic_vector(0 to 87); +signal dbg_group3 : std_ulogic_vector(0 to 87); +signal trg_group0 : std_ulogic_vector(0 to 11); +signal trg_group1 : std_ulogic_vector(0 to 11); +signal trg_group2 : std_ulogic_vector(0 to 11); +signal trg_group3 : std_ulogic_vector(0 to 11); +signal trigger_data_out : std_ulogic_vector(0 to 11); +signal trace_data_out : std_ulogic_vector(0 to 87); +signal uc_hooks_debug : std_ulogic_vector(0 to 55); + +signal t0_events : std_ulogic_vector(0 to 7); +signal t1_events : std_ulogic_vector(0 to 7); +signal t2_events : std_ulogic_vector(0 to 7); +signal t3_events : std_ulogic_vector(0 to 7); +signal t0_events_in : std_ulogic_vector(0 to 7); +signal t1_events_in : std_ulogic_vector(0 to 7); +signal t2_events_in : std_ulogic_vector(0 to 7); +signal t3_events_in : std_ulogic_vector(0 to 7); +signal evnt_axu_instr_cmt : std_ulogic_vector(0 to 3); +signal evnt_axu_cr_cmt : std_ulogic_vector(0 to 3); +signal evnt_axu_idle : std_ulogic_vector(0 to 3); +signal evnt_div_sqrt_ip : std_ulogic_vector(0 to 3); +signal evnt_denrm_flush : std_ulogic_vector(0 to 3); +signal evnt_uc_instr_cmt : std_ulogic_vector(0 to 3); +signal event_data_d : std_ulogic_vector(0 to 7); +signal event_data_q : std_ulogic_vector(0 to 7); +signal evnt_fpu_fex : std_ulogic_vector(0 to 3); +signal evnt_fpu_fx : std_ulogic_vector(0 to 3); +signal event_en_d : std_ulogic_vector(0 to 3); +signal event_en_q : std_ulogic_vector(0 to 3); +signal event_count_mode_q : std_ulogic_vector(0 to 2); +signal msr_pr_q : std_ulogic_vector(0 to 3); +signal msr_gs_q : std_ulogic_vector(0 to 3); +signal instr_trace_mode_q : std_ulogic; +signal instr_trace_tid_q : std_ulogic_vector(0 to 1); + +signal rf1_instr_iss : std_ulogic_vector(0 to 3); +signal ex1_instr_iss : std_ulogic_vector(0 to 3); +signal ex2_instr_iss : std_ulogic_vector(0 to 3); + +signal ex6_ram_sign : std_ulogic; +signal ex6_ram_frac : std_ulogic_vector(0 to 52); +signal ex6_ram_expo : std_ulogic_vector(3 to 13); +signal ex6_ram_done : std_ulogic; +signal ex7_ram_done : std_ulogic; +signal ex7_ram_sign : std_ulogic; +signal ex7_ram_frac : std_ulogic_vector(0 to 52); +signal ex7_ram_expo : std_ulogic_vector(3 to 13); +signal ex7_ram_data : std_ulogic_vector(0 to 63); + +signal rf1_iu_si, rf1_iu_so : std_ulogic_vector(0 to 14); +signal rf1_frt_si, rf1_frt_so : std_ulogic_vector(0 to 31); +signal uc_hooks_rc_rf0 : std_ulogic; +signal dbg0_act : std_ulogic; +signal event_act : std_ulogic; + +signal SPARE_L2 : std_ulogic_vector(0 to 23); + +signal act_lat_si, act_lat_so : std_ulogic_vector(0 to 2); +signal rf1_ifr_si, rf1_ifr_so : std_ulogic_vector(62-eff_ifar to 61); +signal rf1_instl_si, rf1_instl_so : std_ulogic_vector(0 to 31); +signal rf1_byp_si, rf1_byp_so : std_ulogic_vector(0 to 11); +signal ex1_ctl_si, ex1_ctl_so : std_ulogic_vector(0 to 7); +signal ex1_frt_si, ex1_frt_so : std_ulogic_vector(0 to 17); +signal ex1_ifar_si, ex1_ifar_so : std_ulogic_vector(62-eff_ifar to 61); +signal ex2_ctl_si, ex2_ctl_so : std_ulogic_vector(0 to 15); +signal ex2_ctlng_si, ex2_ctlng_so : std_ulogic_vector(0 to 16); +signal ex3_ctlng_si, ex3_ctlng_so : std_ulogic_vector(0 to 15); +signal ex3_ctl_si, ex3_ctl_so : std_ulogic_vector(0 to 12); +signal ex4_ctl_si, ex4_ctl_so : std_ulogic_vector(0 to 15); +signal ex5_ctl_si, ex5_ctl_so : std_ulogic_vector(0 to 14); +signal ex6_ctl_si, ex6_ctl_so : std_ulogic_vector(0 to 15); +signal ex7_ctl_si, ex7_ctl_so : std_ulogic_vector(0 to 6); +signal spr_ctl_si, spr_ctl_so : std_ulogic_vector(0 to 14); +signal spr_data_si, spr_data_so : std_ulogic_vector(64-(2**regmode) to 63); +signal ram_data_si, ram_data_so : std_ulogic_vector(0 to 64); +signal ram_datav_si, ram_datav_so : std_ulogic_vector(0 to 0); +signal perf_data_si, perf_data_so : std_ulogic_vector(0 to 38); +signal dbg0_data_si, dbg0_data_so : std_ulogic_vector(0 to 115); +signal dbg1_data_si, dbg1_data_so : std_ulogic_vector(0 to 4); +signal spare_si, spare_so : std_ulogic_vector(0 to 23); +signal f_ucode_si, f_ucode_so : std_ulogic; +signal axucr0_lat_si, axucr0_lat_so : std_ulogic_vector(0 to 2); + +signal cfg_slat_d2clk : std_ulogic; +signal cfg_slat_lclk : clk_logic; + + +signal ex2_store_valid , ex2_stdv_si, ex2_stdv_so : std_ulogic; +signal msr_fp : std_ulogic; +signal msr_fp_raw : std_ulogic; +signal msr_fp_act : std_ulogic; + +signal perr_sm_running : std_ulogic; + +signal spare_unused : std_ulogic_vector(0 to 10); + + + + + signal ex5_iflush_int_b, ex5_iflush_b :std_ulogic_vector(0 to 3); + signal ex5_iflush_01, ex5_iflush_23, ex5_instr_flush_b :std_ulogic; + + + +begin + + + tilo <= '0'; + tihi <= '1'; + fu_buf_up: tihi_out <= tihi; + fu_buf_dn: tilo_out <= tilo; + + + thold_reg_0: tri_plat generic map (expand_type => expand_type, width => 3) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => thold_1, + din(1) => cfg_sl_thold_1, + din(2) => func_slp_sl_thold_1, + q(0) => thold_0, + q(1) => cfg_sl_thold_0, + q(2) => func_slp_sl_thold_0 ); + + sg_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => sg_1 , + q(0) => sg_0 ); + + + lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map ( + clkoff_b => clkoff_b, + thold => thold_0, + sg => sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => thold_0_b ); + + cfg_sl_lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map ( + clkoff_b => clkoff_b, + thold => cfg_sl_thold_0, + sg => sg_0, + act_dis => act_dis, + forcee => cfg_sl_force, + thold_b => cfg_sl_thold_0_b ); + + func_slp_sl_lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map ( + clkoff_b => clkoff_b, + thold => func_slp_sl_thold_0, + sg => sg_0, + act_dis => act_dis, + forcee => func_slp_sl_force, + thold_b => func_slp_sl_thold_0_b ); + + + msr_fp <= or_reduce(xu_fu_msr_fp(0 to 3)); + + act_lat: tri_rlmreg_p generic map (init => 0, expand_type => expand_type, width => 3) port map ( + nclk => nclk, + act => tihi, + forcee => forcee, + delay_lclkr => delay_lclkr(9), + mpw1_b => mpw1_b(9), + mpw2_b => mpw2_b(1), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => act_lat_si(0 to 2), + scout => act_lat_so(0 to 2), + din(0) => pc_fu_trace_bus_enable, + din(1) => pc_fu_event_bus_enable, + din(2) => msr_fp, + dout(0) => dbg0_act , + dout(1) => event_act , + dout(2) => msr_fp_raw); + + msr_fp_act <= msr_fp_raw or not axucr0_q(63); + + f_dcd_msr_fp_act <= msr_fp_act; + + + + rf0_str_tag(0 to 1) <= iu_fu_rf0_ldst_tag(0 to 1); + + rf0_ldst_valid(0) <= iu_fu_rf0_ldst_val and not xu_rf0_flush(0) and iu_fu_rf0_ldst_tid(0 to 1) = "00"; + rf0_ldst_valid(1) <= iu_fu_rf0_ldst_val and not xu_rf0_flush(1) and iu_fu_rf0_ldst_tid(0 to 1) = "01"; + rf0_ldst_valid(2) <= iu_fu_rf0_ldst_val and not xu_rf0_flush(2) and iu_fu_rf0_ldst_tid(0 to 1) = "10"; + rf0_ldst_valid(3) <= iu_fu_rf0_ldst_val and not xu_rf0_flush(3) and iu_fu_rf0_ldst_tid(0 to 1) = "11"; + + rf0_str_v <= iu_fu_rf0_str_val; + + rf0_instr_match <= iu_fu_rf0_instr_match; + rf0_is_ucode <= iu_fu_rf0_is_ucode; + + rf0_tid(0 to 1) <= iu_fu_rf0_tid(0 to 1); + rf0_instr_tid_1hot(0) <= (rf0_tid(0 to 1) = "00") and iu_fu_rf0_instr_v; + rf0_instr_tid_1hot(1) <= (rf0_tid(0 to 1) = "01") and iu_fu_rf0_instr_v; + rf0_instr_tid_1hot(2) <= (rf0_tid(0 to 1) = "10") and iu_fu_rf0_instr_v; + rf0_instr_tid_1hot(3) <= (rf0_tid(0 to 1) = "11") and iu_fu_rf0_instr_v; + + rf0_instr_valid(0 to 3) <= rf0_instr_tid_1hot(0 to 3) and not xu_rf0_flush(0 to 3); + + rf0_thread_lat: tri_rlmreg_p generic map (init => 0, expand_type => expand_type, width => 4) port map ( + nclk => nclk, + act => msr_fp_act, + forcee => forcee, + delay_lclkr => delay_lclkr(8), + mpw1_b => mpw1_b(8), + mpw2_b => mpw2_b(1), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => rf0_thread_si(0 to 3), + scout => rf0_thread_so(0 to 3), + din(0 to 3) => iu_fu_is2_tid_decode(0 to 3), + dout(0 to 3) => thread_id_rf0(0 to 3) ) ; + + + rf0_instr_frt(0 to 5) <= iu_fu_rf0_frt(1 to 6); + rf0_instr_fra(0 to 5) <= iu_fu_rf0_fra(1 to 6); + rf0_instr_frb(0 to 5) <= iu_fu_rf0_frb(1 to 6); + rf0_instr_frc(0 to 5) <= iu_fu_rf0_frc(1 to 6); + rf0_instr_frs(0 to 5) <= iu_fu_rf0_ldst_tag(3 to 8); + + + + rf0_bypsel(0 to 5) <= iu_fu_rf0_bypsel(0 to 5); + + rf0_bypsel_a_res0 <= rf0_bypsel(3) and or_reduce(ex5_instr_bypval(0 to 3)); + rf0_bypsel_c_res0 <= rf0_bypsel(4) and or_reduce(ex5_instr_bypval(0 to 3)); + rf0_bypsel_b_res0 <= rf0_bypsel(5) and or_reduce(ex5_instr_bypval(0 to 3)); + + rf0_bypsel_a_res1 <= (ex6_instr_tid(0 to 1) & ex6_instr_frt(0 to 5)) = (rf0_tid(0 to 1) & rf0_instr_fra(0 to 5)) and + (ex6_instr_valid and not ex6_kill_wen) and iu_fu_rf0_fra_v and not rf0_bypsel_a_res0 and not rf0_bypsel_a_load0; + rf0_bypsel_c_res1 <= (ex6_instr_tid(0 to 1) & ex6_instr_frt(0 to 5)) = (rf0_tid(0 to 1) & rf0_instr_frc(0 to 5)) and + (ex6_instr_valid and not ex6_kill_wen) and iu_fu_rf0_frc_v and not rf0_bypsel_c_res0 and not rf0_bypsel_c_load0; + rf0_bypsel_b_res1 <= (ex6_instr_tid(0 to 1) & ex6_instr_frt(0 to 5)) = (rf0_tid(0 to 1) & rf0_instr_frb(0 to 5)) and + (ex6_instr_valid and not ex6_kill_wen) and iu_fu_rf0_frb_v and not rf0_bypsel_b_res0 and not rf0_bypsel_b_load0; + + rf0_bypsel_s_res1 <= (ex6_instr_tid(0 to 1) & ex6_instr_frt(0 to 5)) = (iu_fu_rf0_ldst_tid(0 to 1) & rf0_instr_frs(0 to 5)) and + (ex6_instr_valid and not ex6_kill_wen) and rf0_str_v; + + rf0_bypsel_a_load0 <= rf0_bypsel(0); + rf0_bypsel_c_load0 <= rf0_bypsel(1); + rf0_bypsel_b_load0 <= rf0_bypsel(2); + + rf0_bypsel_a_load1 <= (f_fpr_ex7_load_addr(0 to 7) ) = (rf0_tid(0 to 1) & rf0_instr_fra(0 to 5)) and f_fpr_ex7_load_v and iu_fu_rf0_fra_v and not rf0_bypsel_a_load0 and not rf0_bypsel_a_res0; + rf0_bypsel_c_load1 <= (f_fpr_ex7_load_addr(0 to 7) ) = (rf0_tid(0 to 1) & rf0_instr_frc(0 to 5)) and f_fpr_ex7_load_v and iu_fu_rf0_frc_v and not rf0_bypsel_c_load0 and not rf0_bypsel_c_res0; + rf0_bypsel_b_load1 <= (f_fpr_ex7_load_addr(0 to 7) ) = (rf0_tid(0 to 1) & rf0_instr_frb(0 to 5)) and f_fpr_ex7_load_v and iu_fu_rf0_frb_v and not rf0_bypsel_b_load0 and not rf0_bypsel_b_res0; + rf0_bypsel_s_load1 <= (f_fpr_ex7_load_addr(0 to 7) ) = (iu_fu_rf0_ldst_tid(0 to 1) & rf0_instr_frs(0 to 5)) and f_fpr_ex7_load_v and rf0_str_v; + + f_dcd_rf0_bypsel_a_res1 <= rf0_bypsel_a_res1; + f_dcd_rf0_bypsel_b_res1 <= rf0_bypsel_b_res1; + f_dcd_rf0_bypsel_c_res1 <= rf0_bypsel_c_res1; + f_dcd_rf0_bypsel_a_load1 <= rf0_bypsel_a_load1; + f_dcd_rf0_bypsel_b_load1 <= rf0_bypsel_b_load1; + f_dcd_rf0_bypsel_c_load1 <= rf0_bypsel_c_load1; + + f_dcd_rf0_bypsel_s_res1 <= rf0_bypsel_s_res1; + f_dcd_rf0_bypsel_s_load1 <= rf0_bypsel_s_load1; + + rf0_frs_byp <= rf0_bypsel_s_res1 or rf0_bypsel_s_load1; + + + rf1_iu: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 15) + port map (nclk => nclk, + act => tihi, + forcee => forcee, + delay_lclkr => delay_lclkr(0), + mpw1_b => mpw1_b(0), + mpw2_b => mpw2_b(0), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => rf1_iu_si(0 to 14), + scout => rf1_iu_so(0 to 14), + din(0) => iu_fu_rf0_fra_v, + din(1) => iu_fu_rf0_frb_v, + din(2) => iu_fu_rf0_frc_v, + din(3 to 6) => rf0_instr_valid(0 to 3), + din(7 to 10) => rf0_ldst_valid(0 to 3), + din(11 to 12) => rf0_str_tag(0 to 1), + din(13) => rf0_str_v, + din(14) => rf0_frs_byp, + dout(0) => rf1_instr_fra_v, + dout(1) => rf1_instr_frb_v, + dout(2) => rf1_instr_frc_v, + dout(3 to 6) => rf1_instr_v(0 to 3), + dout(7 to 10) => rf1_ldst_v(0 to 3), + dout(11 to 12) => rf1_str_tag(0 to 1), + dout(13) => rf1_str_v, + dout(14) => rf1_frs_byp + ); + rf1_frt: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 32) + port map (nclk => nclk, + act => msr_fp_act, + forcee => forcee, + delay_lclkr => delay_lclkr(0), + mpw1_b => mpw1_b(0), + mpw2_b => mpw2_b(0), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => rf1_frt_si(0 to 31), + scout => rf1_frt_so(0 to 31), + din( 0 to 5) => rf0_instr_frt(0 to 5) , + din( 6 to 11) => rf0_instr_fra(0 to 5) , + din(12 to 17) => rf0_instr_frb(0 to 5) , + din(18 to 23) => rf0_instr_frc(0 to 5) , + din(24 to 29) => rf0_instr_frs(0 to 5) , + din(30) => rf0_instr_match , + din(31) => rf0_is_ucode , + dout( 0 to 5) => rf1_instr_frt(0 to 5) , + dout( 6 to 11) => rf1_instr_fra(0 to 5) , + dout(12 to 17) => rf1_instr_frb(0 to 5) , + dout(18 to 23) => rf1_instr_frc(0 to 5) , + dout(24 to 29) => rf1_instr_frs(0 to 5) , + dout(30) => rf1_instr_match , + dout(31) => rf1_is_ucode + ); + rf1_ifr: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => eff_ifar) + port map (nclk => nclk, + act => tihi, + forcee => forcee, + delay_lclkr => delay_lclkr(0), + mpw1_b => mpw1_b(0), + mpw2_b => mpw2_b(0), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => rf1_ifr_si, + scout => rf1_ifr_so, + din => iu_fu_rf0_ifar, + dout => rf1_instr_ifar ); + rf1_instl: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 32) + port map (nclk => nclk, + act => msr_fp_act, + forcee => forcee, + delay_lclkr => delay_lclkr(0), + mpw1_b => mpw1_b(0), + mpw2_b => mpw2_b(0), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => rf1_instl_si(0 to 31), + scout => rf1_instl_so(0 to 31), + din(0 to 30) => iu_fu_rf0_instr(0 to 30), + din(31) => uc_hooks_rc_rf0, + dout => rf1_instr(0 to 31) ); + rf1_byp: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 12) + port map (nclk => nclk, + act => msr_fp_act, + forcee => forcee, + delay_lclkr => delay_lclkr(0), + mpw1_b => mpw1_b(0), + mpw2_b => mpw2_b(0), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => rf1_byp_si(0 to 11), + scout => rf1_byp_so(0 to 11), + din(0) => rf0_bypsel_a_res0, + din(1) => rf0_bypsel_c_res0, + din(2) => rf0_bypsel_b_res0, + din(3) => rf0_bypsel_a_res1, + din(4) => rf0_bypsel_c_res1, + din(5) => rf0_bypsel_b_res1, + din(6) => rf0_bypsel_a_load0, + din(7) => rf0_bypsel_c_load0, + din(8) => rf0_bypsel_b_load0, + din(9) => rf0_bypsel_a_load1, + din(10) => rf0_bypsel_c_load1, + din(11) => rf0_bypsel_b_load1, + dout(0) => rf1_bypsel_a_res0, + dout(1) => rf1_bypsel_c_res0, + dout(2) => rf1_bypsel_b_res0, + dout(3) => rf1_bypsel_a_res1, + dout(4) => rf1_bypsel_c_res1, + dout(5) => rf1_bypsel_b_res1, + dout(6) => rf1_bypsel_a_load0, + dout(7) => rf1_bypsel_c_load0, + dout(8) => rf1_bypsel_b_load0, + dout(9) => rf1_bypsel_a_load1, + dout(10) => rf1_bypsel_c_load1, + dout(11) => rf1_bypsel_b_load1 + ); + + rf1_instr_valid(0 to 3) <= rf1_instr_v(0 to 3) and not xu_rf1_flush(0 to 3); + rf1_ldst_valid(0 to 3) <= rf1_ldst_v(0 to 3) and not xu_rf1_flush(0 to 3); + + fu_xu_rf1_act(0 to 3) <= rf1_instr_v(0 to 3); + + rf1_tid(0) <= rf1_instr_v(2) or rf1_instr_v(3); + rf1_tid(1) <= rf1_instr_v(1) or rf1_instr_v(3); + + + rf1_primary(0 to 5) <= rf1_instr(0 to 5); + rf1_sec_xform(0 to 9) <= rf1_instr(21 to 30); + rf1_sec_aform(0 to 4) <= rf1_instr(26 to 30); + rf1_v <= rf1_instr_v(0) or rf1_instr_v(1) or rf1_instr_v(2) or rf1_instr_v(3); + rf1_axu_v <= rf1_v or rf1_ldst_v(0) or rf1_ldst_v(1) or rf1_ldst_v(2) or rf1_ldst_v(3) or rf1_perr_sm_instr_v; + rf1_dp <= (rf1_primary(0 to 5) = "111111") and rf1_v and not rf1_perr_sm_instr_v; + rf1_sp <= (rf1_primary(0 to 5) = "111011") and rf1_v and not rf1_perr_sm_instr_v; + rf1_dporsp <= rf1_dp or rf1_sp; + + rf1_fabs <= rf1_dp and (rf1_sec_xform(0 to 9) = "0100001000"); + rf1_fadd <= rf1_dporsp and (rf1_sec_aform(0 to 4) = "10101"); + rf1_fcfid <= rf1_dp and (rf1_sec_xform(0 to 9) = "1101001110"); + rf1_fcfidu <= rf1_dp and (rf1_sec_xform(0 to 9) = "1111001110"); + rf1_fcfids <= rf1_sp and (rf1_sec_xform(0 to 9) = "1101001110"); + rf1_fcfidus <= rf1_sp and (rf1_sec_xform(0 to 9) = "1111001110"); + rf1_fcfiwu <= rf1_dp and (rf1_sec_xform(0 to 9) = "0011001110"); + rf1_fcfiwus <= rf1_sp and (rf1_sec_xform(0 to 9) = "0011001110"); + rf1_fcmpo <= rf1_dp and (rf1_sec_xform(0 to 9) = "0000100000"); + rf1_fcmpu <= rf1_dp and (rf1_sec_xform(0 to 9) = "0000000000"); + rf1_fcpsgn <= rf1_dp and (rf1_sec_xform(0 to 9) = "0000001000"); + rf1_fctid <= rf1_dp and (rf1_sec_xform(0 to 9) = "1100101110"); + rf1_fctidu <= rf1_dp and (rf1_sec_xform(0 to 9) = "1110101110"); + rf1_fctidz <= rf1_dp and (rf1_sec_xform(0 to 9) = "1100101111"); + rf1_fctiduz <= rf1_dp and (rf1_sec_xform(0 to 9) = "1110101111"); + rf1_fctiw <= rf1_dp and (rf1_sec_xform(0 to 9) = "0000001110"); + rf1_fctiwu <= rf1_dp and (rf1_sec_xform(0 to 9) = "0010001110"); + rf1_fctiwz <= rf1_dp and (rf1_sec_xform(0 to 9) = "0000001111"); + rf1_fctiwuz <= rf1_dp and (rf1_sec_xform(0 to 9) = "0010001111"); + rf1_fmadd <= rf1_dporsp and (rf1_sec_aform(0 to 4) = "11101"); + rf1_fmr <= rf1_dp and (rf1_sec_xform(0 to 9) = "0001001000"); + rf1_fmsub <= rf1_dporsp and (rf1_sec_aform(0 to 4) = "11100"); + rf1_fmul <= rf1_dporsp and ((rf1_sec_aform(0 to 4) = "11001") or + (rf1_sec_aform(0 to 4) = "10001")); + rf1_fnabs <= rf1_dp and (rf1_sec_xform(0 to 9) = "0010001000"); + rf1_fneg <= rf1_dp and (rf1_sec_xform(0 to 9) = "0000101000"); + rf1_fnmadd <= rf1_dporsp and (rf1_sec_aform(0 to 4) = "11111"); + rf1_fnmsub <= rf1_dporsp and (rf1_sec_aform(0 to 4) = "11110"); + rf1_fres <= rf1_dporsp and (rf1_sec_aform(0 to 4) = "11000"); + rf1_frim <= rf1_dp and (rf1_sec_xform(0 to 9) = "0111101000"); + rf1_frin <= rf1_dp and (rf1_sec_xform(0 to 9) = "0110001000"); + rf1_frip <= rf1_dp and (rf1_sec_xform(0 to 9) = "0111001000"); + rf1_friz <= rf1_dp and (rf1_sec_xform(0 to 9) = "0110101000"); + rf1_frsp <= rf1_dp and (rf1_sec_xform(0 to 9) = "0000001100"); + rf1_frsqrte <= rf1_dporsp and (rf1_sec_aform(0 to 4) = "11010"); + rf1_fsel <= (rf1_dp and (rf1_sec_aform(0 to 4) = "10111")) + or (not perr_sm_l2(0)); + + rf1_fsub <= rf1_dporsp and (rf1_sec_aform(0 to 4) = "10100"); + rf1_mcrfs <= rf1_dp and (rf1_sec_xform(0 to 9) = "0001000000"); + rf1_mffs <= rf1_dp and (rf1_sec_xform(0 to 9) = "1001000111"); + rf1_mtfsb0 <= rf1_dp and (rf1_sec_xform(0 to 9) = "0001000110"); + rf1_mtfsb1 <= rf1_dp and (rf1_sec_xform(0 to 9) = "0000100110"); + rf1_mtfsf <= rf1_dp and (rf1_sec_xform(0 to 9) = "1011000111"); + rf1_mtfsfi <= rf1_dp and (rf1_sec_xform(0 to 9) = "0010000110"); + rf1_loge <= rf1_dporsp and (rf1_sec_xform(0 to 9) = "0011100101"); + rf1_expte <= rf1_dporsp and (rf1_sec_xform(0 to 9) = "0011000101"); + rf1_prenorm <= rf1_dporsp and (rf1_sec_xform(5 to 9) = "10000"); + + rf1_ftdiv <= rf1_dp and (rf1_sec_xform(0 to 9) = "0010000000"); + rf1_ftsqrt <= rf1_dp and (rf1_sec_xform(0 to 9) = "0010100000"); + + rf1_cr_val <= rf1_fcmpu or rf1_fcmpo; + rf1_record <= (rf1_dporsp and rf1_instr(31)) and not rf1_cr_val and not rf1_mcrfs + and not rf1_ftdiv and not rf1_ftsqrt; + + rf1_moves <= rf1_fmr or rf1_fabs or rf1_fnabs or rf1_fneg or rf1_fcpsgn ; + + rf1_to_ints <= rf1_fctid or rf1_fctidu or rf1_fctidz or rf1_fctiduz or + rf1_fctiw or rf1_fctiwu or rf1_fctiwz or rf1_fctiwuz; + rf1_from_ints <= rf1_fcfid or rf1_fcfidu or rf1_fcfids or rf1_fcfidus or + rf1_fcfiwu or rf1_fcfiwus; + rf1_fpscr_moves <= rf1_mtfsb0 or rf1_mtfsb1 or rf1_mtfsf or rf1_mtfsfi or rf1_mcrfs; + + rf1_kill_wen <= rf1_cr_val or rf1_fpscr_moves or rf1_ftdiv or rf1_ftsqrt; + + + rf1_mtfsb_bt(0) <= not rf1_instr(9) and not rf1_instr(10); + rf1_mtfsb_bt(1) <= not rf1_instr(9) and rf1_instr(10); + rf1_mtfsb_bt(2) <= rf1_instr(9) and not rf1_instr(10); + rf1_mtfsb_bt(3) <= rf1_instr(9) and rf1_instr(10); + + rf1_mtfs_bf(0) <= not rf1_instr(6) and not rf1_instr(7) and not rf1_instr(8); + rf1_mtfs_bf(1) <= not rf1_instr(6) and not rf1_instr(7) and rf1_instr(8); + rf1_mtfs_bf(2) <= not rf1_instr(6) and rf1_instr(7) and not rf1_instr(8); + rf1_mtfs_bf(3) <= not rf1_instr(6) and rf1_instr(7) and rf1_instr(8); + rf1_mtfs_bf(4) <= rf1_instr(6) and not rf1_instr(7) and not rf1_instr(8); + rf1_mtfs_bf(5) <= rf1_instr(6) and not rf1_instr(7) and rf1_instr(8); + rf1_mtfs_bf(6) <= rf1_instr(6) and rf1_instr(7) and not rf1_instr(8); + rf1_mtfs_bf(7) <= rf1_instr(6) and rf1_instr(7) and rf1_instr(8); + + rf1_mcrfs_bfa(0) <= not rf1_instr(11) and not rf1_instr(12) and not rf1_instr(13); + rf1_mcrfs_bfa(1) <= not rf1_instr(11) and not rf1_instr(12) and rf1_instr(13); + rf1_mcrfs_bfa(2) <= not rf1_instr(11) and rf1_instr(12) and not rf1_instr(13); + rf1_mcrfs_bfa(3) <= not rf1_instr(11) and rf1_instr(12) and rf1_instr(13); + rf1_mcrfs_bfa(4) <= rf1_instr(11) and not rf1_instr(12) and not rf1_instr(13); + rf1_mcrfs_bfa(5) <= rf1_instr(11) and not rf1_instr(12) and rf1_instr(13); + rf1_mcrfs_bfa(6) <= rf1_instr(11) and rf1_instr(12) and not rf1_instr(13); + rf1_mcrfs_bfa(7) <= rf1_instr(11) and rf1_instr(12) and rf1_instr(13); + + rf1_mtfsf_l <= rf1_instr(6); + rf1_mtfsf_w <= rf1_instr(15); + + + rf1_fpscr_bit_data(0 to 3) <= (rf1_instr(16 to 19) or (0 to 3 => rf1_mtfsb1)) and not + (0 to 3 => rf1_mtfsb0 or rf1_mtfsf or rf1_mcrfs); + + rf1_fpscr_bit_mask(0 to 3) <= rf1_mtfsb_bt(0 to 3) or + (0 to 3 => rf1_mtfsfi or rf1_mtfsf or rf1_mcrfs); + + rf1_fpscr_nib_mask(0 to 7) <= (rf1_mtfs_bf (0 to 7) and (0 to 7 => rf1_mtfsb1 or rf1_mtfsb0) ) or + (rf1_mtfs_bf (0 to 7) and (0 to 7 => rf1_mtfsfi and not rf1_mtfsf_w)) or + (rf1_mtfsf_nib(0 to 7) and (0 to 7 => rf1_mtfsf) ) or + (rf1_mcrfs_bfa(0 to 7) and (0 to 7 => rf1_mcrfs) ); + + + + rf1_mtfsf_nib(0 to 7) <= (rf1_instr(7 to 14) or (7 to 14 => rf1_mtfsf_l)) and not (0 to 7 => not rf1_mtfsf_l and rf1_mtfsf_w); + + rf1_fpscr_nib_mask(8) <= (rf1_mtfsfi and rf1_mtfsf_w and rf1_mtfs_bf(7)) or + (rf1_mtfsf and rf1_mtfsf_l ) or + (rf1_mtfsf and not rf1_mtfsf_l and rf1_mtfsf_w and rf1_instr(14)); + + f_dcd_rf1_fpscr_bit_data_b(0 to 3) <= not rf1_fpscr_bit_data(0 to 3); + f_dcd_rf1_fpscr_bit_mask_b(0 to 3) <= not rf1_fpscr_bit_mask(0 to 3); + f_dcd_rf1_fpscr_nib_mask_b(0 to 8) <= not rf1_fpscr_nib_mask(0 to 8); + + + f_dcd_rf1_aop_valid <= rf1_instr_fra_v; + f_dcd_rf1_cop_valid <= rf1_instr_frc_v or + (not perr_sm_l2(0) and rf1_perr_sm_instr_v); + f_dcd_rf1_bop_valid <= rf1_instr_frb_v or + (not perr_sm_l2(0) and rf1_perr_sm_instr_v); + + f_dcd_rf1_sp <= rf1_sp and not (rf1_fcfids or rf1_fcfiwus or rf1_fcfidus); + f_dcd_rf1_emin_dp <= tilo; + f_dcd_rf1_emin_sp <= rf1_frsp; + f_dcd_rf1_force_pass_b <= not (rf1_fmr or rf1_fabs or rf1_fnabs or rf1_fneg or rf1_mtfsf or rf1_fcpsgn); + f_dcd_rf1_fsel_b <= not rf1_fsel; + f_dcd_rf1_from_integer_b <= not rf1_from_ints; + f_dcd_rf1_to_integer_b <= not (rf1_to_ints or rf1_frim or rf1_frin or rf1_frip or rf1_friz); + f_dcd_rf1_rnd_to_int_b <= not (rf1_frim or rf1_frin or rf1_frip or rf1_friz); + f_dcd_rf1_math_b <= not (rf1_fmul or rf1_fmadd or rf1_fmsub or rf1_fadd or rf1_fsub or rf1_fnmsub or rf1_fnmadd); + f_dcd_rf1_est_recip_b <= not rf1_fres; + f_dcd_rf1_est_rsqrt_b <= not rf1_frsqrte; + f_dcd_rf1_move_b <= not (rf1_moves); + f_dcd_rf1_prenorm_b <= not (rf1_prenorm); + f_dcd_rf1_frsp_b <= not rf1_frsp; + f_dcd_rf1_compare_b <= not rf1_cr_val; + f_dcd_rf1_ordered_b <= not rf1_fcmpo; + f_dcd_rf1_sp_conv_b <= not (rf1_fcfids or rf1_fcfidus or rf1_fcfiwus); + f_dcd_rf1_uns_b <= not (rf1_fcfidu or rf1_fcfidus or rf1_fcfiwu or rf1_fcfiwus or + rf1_fctidu or rf1_fctiduz or rf1_fctiwu or rf1_fctiwuz); + f_dcd_rf1_word_b <= not (rf1_fctiw or rf1_fctiwu or rf1_fctiwz or rf1_fctiwuz or + rf1_fcfiwu or rf1_fcfiwus); + f_dcd_rf1_sub_op_b <= not (rf1_fsub or rf1_fmsub or rf1_fnmsub or rf1_cr_val); + f_dcd_rf1_inv_sign_b <= not (rf1_fnmadd or rf1_fnmsub); + f_dcd_rf1_sign_ctl_b(0) <= not (rf1_fmr or rf1_fnabs); + f_dcd_rf1_sign_ctl_b(1) <= not (rf1_fneg or rf1_fnabs); + f_dcd_rf1_sgncpy_b <= not rf1_fcpsgn; + f_dcd_rf1_mv_to_scr_b <= not (rf1_mcrfs or rf1_mtfsf or rf1_mtfsfi or rf1_mtfsb0 or rf1_mtfsb1); + f_dcd_rf1_mv_from_scr_b <= not rf1_mffs; + f_dcd_rf1_mtfsbx_b <= not (rf1_mtfsb0 or rf1_mtfsb1); + f_dcd_rf1_mcrfs_b <= not rf1_mcrfs; + f_dcd_rf1_mtfsf_b <= not rf1_mtfsf; + f_dcd_rf1_mtfsfi_b <= not rf1_mtfsfi; + + f_dcd_rf1_mad_act <= rf1_v or rf1_perr_sm_instr_v; + + f_dcd_rf1_sto_act <= (rf1_ldst_v(0) or rf1_ldst_v(1) or rf1_ldst_v(2) or rf1_ldst_v(3)) and rf1_str_v; + + rf1_rnd0 <= ((rf1_frim or rf1_frip) and not rf1_uc_op_rnd_v) or + (rf1_uc_op_rnd(0) and rf1_uc_op_rnd_v); + + rf1_rnd1 <= ((rf1_fctidz or rf1_fctiwz or rf1_fctiduz or rf1_fctiwuz or rf1_friz or rf1_frim) and not rf1_uc_op_rnd_v) or + (rf1_uc_op_rnd(1) and rf1_uc_op_rnd_v); + + + f_dcd_rf1_op_rnd_v_b <= not (rf1_fctidz or rf1_fctiwz or rf1_fctiduz or rf1_fctiwuz or + rf1_frim or rf1_frin or rf1_frip or rf1_friz or rf1_uc_op_rnd_v); + f_dcd_rf1_op_rnd_b(0 to 1) <= not (rf1_rnd0 & rf1_rnd1); + + f_dcd_rf1_thread_b(0 to 3) <= not rf1_instr_v(0 to 3); + + f_dcd_rf1_sto_dp <= not rf1_str_tag(0); + f_dcd_rf1_sto_sp <= rf1_str_tag(0) and not rf1_str_tag(1); + f_dcd_rf1_sto_wd <= rf1_str_tag(0) and rf1_str_tag(1); + + f_dcd_rf1_log2e_b <= not rf1_loge; + f_dcd_rf1_pow2e_b <= not rf1_expte; + + f_dcd_rf1_ftdiv <= rf1_ftdiv; + f_dcd_rf1_ftsqrt <= rf1_ftsqrt; + + + f_dcd_rf1_bypsel_a_res0 <= rf1_bypsel_a_res0 ; + f_dcd_rf1_bypsel_a_load0 <= rf1_bypsel_a_load0 ; + f_dcd_rf1_bypsel_b_res0 <= rf1_bypsel_b_res0 ; + f_dcd_rf1_bypsel_b_load0 <= rf1_bypsel_b_load0 ; + f_dcd_rf1_bypsel_c_res0 <= rf1_bypsel_c_res0 ; + f_dcd_rf1_bypsel_c_load0 <= rf1_bypsel_c_load0 ; + + + rf1_byp_a <= rf1_bypsel_a_res0 or rf1_bypsel_a_res1 or rf1_bypsel_a_load0 or rf1_bypsel_a_load1; + rf1_byp_b <= rf1_bypsel_b_res0 or rf1_bypsel_b_res1 or rf1_bypsel_b_load0 or rf1_bypsel_b_load1; + rf1_byp_c <= rf1_bypsel_c_res0 or rf1_bypsel_c_res1 or rf1_bypsel_c_load0 or rf1_bypsel_c_load1; + rf1_fra_v <= rf1_instr_fra_v and not rf1_byp_a and not f_dcd_rf1_uc_fa_dis_par; + rf1_frb_v <= rf1_instr_frb_v and not rf1_byp_b and not f_dcd_rf1_uc_fb_dis_par; + rf1_frc_v <= rf1_instr_frc_v and not rf1_byp_c and not f_dcd_rf1_uc_fc_dis_par and not rf1_uc_end; + + + ex1_cr_val_din <= rf1_cr_val or rf1_ftdiv or rf1_ftsqrt; + + ex1_ctl: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 8) + port map (nclk => nclk, + act => tihi, + forcee => forcee, + delay_lclkr => delay_lclkr(1), + mpw1_b => mpw1_b(1), + mpw2_b => mpw2_b(0), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => ex1_ctl_si(0 to 7), + scout => ex1_ctl_so(0 to 7), + din(0 to 3) => rf1_instr_valid(0 to 3), + din(4 to 7) => rf1_ldst_valid(0 to 3), + dout(0 to 3) => ex1_instr_v(0 to 3), + dout(4 to 7) => ex1_ldst_v(0 to 3) + ); + + ex1_frt: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 18) + port map (nclk => nclk, + act => rf1_axu_v, + forcee => forcee, + delay_lclkr => delay_lclkr(1), + mpw1_b => mpw1_b(1), + mpw2_b => mpw2_b(0), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => ex1_frt_si(0 to 17), + scout => ex1_frt_so(0 to 17), + din(0 to 5) => rf1_instr_frt(0 to 5), + din( 6) => ex1_cr_val_din, + din( 7) => rf1_record, + din( 8) => rf1_kill_wen, + din( 9) => rf1_mcrfs, + din(10) => rf1_instr_match, + din(11) => rf1_is_ucode, + din(12) => rf1_divsqrt_beg, + din(13) => rf1_fra_v, + din(14) => rf1_frb_v, + din(15) => rf1_frc_v, + din(16) => rf1_str_v, + din(17) => rf1_frs_byp, + dout(0 to 5) => ex1_instr_frt(0 to 5), + dout(6) => ex1_cr_val, + dout(7) => ex1_record, + dout(8) => ex1_kill_wen, + dout(9) => ex1_mcrfs, + dout(10) => ex1_instr_match, + dout(11) => ex1_is_ucode, + dout(12) => ex1_divsqrt_beg, + dout(13) => ex1_fra_v, + dout(14) => ex1_frb_v, + dout(15) => ex1_frc_v, + dout(16) => ex1_str_v, + dout(17) => ex1_frs_byp + ); + ex1_ifar: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => eff_ifar) + port map (nclk => nclk, + act => rf1_v, + forcee => forcee, + delay_lclkr => delay_lclkr(1), + mpw1_b => mpw1_b(1), + mpw2_b => mpw2_b(0), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => ex1_ifar_si, + scout => ex1_ifar_so, + din => rf1_instr_ifar, + dout => ex1_instr_ifar + ); + + ex1_perr: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 24) + port map (nclk => nclk, + act => rf1_axu_v, + forcee => forcee, + delay_lclkr => delay_lclkr(1), + mpw1_b => mpw1_b(1), + mpw2_b => mpw2_b(0), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => ex1_perr_si(0 to 23), + scout => ex1_perr_so(0 to 23), + din( 0 to 5) => rf1_instr_frs(0 to 5) , + din( 6 to 11) => rf1_instr_fra(0 to 5) , + din(12 to 17) => rf1_instr_frb(0 to 5) , + din(18 to 23) => rf1_instr_frc(0 to 5) , + dout( 0 to 5) => ex1_instr_frs(0 to 5) , + dout( 6 to 11) => ex1_instr_fra(0 to 5) , + dout(12 to 17) => ex1_instr_frb(0 to 5) , + dout(18 to 23) => ex1_instr_frc(0 to 5) + ); + + ex1_instr_valid(0 to 3) <= ex1_instr_v(0 to 3) and not xu_ex1_flush(0 to 3); + ex1_v <= ex1_instr_v(0) or ex1_instr_v(1) or ex1_instr_v(2) or ex1_instr_v(3); + ex1_axu_v <= ex1_v or ex1_ldst_v(0) or ex1_ldst_v(1) or ex1_ldst_v(2) or ex1_ldst_v(3); + + ex1_ldst_valid <= ex1_ldst_v(0 to 3) and not xu_ex1_flush(0 to 3); + + ex1_str_valid <= ex1_str_v and or_reduce(ex1_ldst_valid(0 to 3)); + ex1_fra_valid <= ex1_fra_v and or_reduce(ex1_instr_valid(0 to 3)); + ex1_frb_valid <= ex1_frb_v and or_reduce(ex1_instr_valid(0 to 3)); + ex1_frc_valid <= ex1_frc_v and or_reduce(ex1_instr_valid(0 to 3)); + + ex1_ifar_val(0 to 3) <= ex1_instr_valid(0 to 3) and not (0 to 3 => ex1_divsqrt_beg); + + fu_xu_ex1_ifar <= ex1_instr_ifar; + + + + ex1_async_block(0 to 3) <= ex1_instr_v(0 to 3) or + ex2_instr_v(0 to 3) or + ex3_instr_v(0 to 3) or + ex4_instr_v(0 to 3) or + ex5_instr_v(0 to 3) ; + + + ex2_ctlng_lat: tri_rlmreg_p generic map (init => 0, expand_type => expand_type, width => 17) port map ( + nclk => nclk, + act => tihi, + forcee => forcee, + delay_lclkr => delay_lclkr(2), + mpw1_b => mpw1_b(2), + mpw2_b => mpw2_b(0), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => ex2_ctlng_si(0 to 16), + scout => ex2_ctlng_so(0 to 16), + din( 0 to 3) => ex1_instr_valid(0 to 3), + din( 4 to 7) => ex1_ifar_val(0 to 3), + din( 8 to 11) => ex1_ldst_valid(0 to 3), + din(12 to 15) => ex1_async_block(0 to 3), + din(16) => ex1_str_valid, + dout( 0 to 3) => ex2_instr_v(0 to 3), + dout( 4 to 7) => ex2_ifar_val(0 to 3), + dout( 8 to 11) => ex2_ldst_v(0 to 3), + dout(12 to 15) => ex2_async_block(0 to 3), + dout(16) => ex2_str_v + ); + + ex2_ctl_lat: tri_rlmreg_p generic map (init => 0, expand_type => expand_type, width => 16) port map ( + nclk => nclk, + act => ex1_axu_v, + forcee => forcee, + delay_lclkr => delay_lclkr(2), + mpw1_b => mpw1_b(2), + mpw2_b => mpw2_b(0), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => ex2_ctl_si(0 to 15), + scout => ex2_ctl_so(0 to 15), + din(0 to 5) => ex1_instr_frt(0 to 5), + din(6) => ex1_cr_val, + din(7) => ex1_record, + din(8) => ex1_kill_wen, + din(9) => ex1_mcrfs, + din(10) => ex1_instr_match, + din(11) => ex1_is_ucode, + din(12) => ex1_fra_valid, + din(13) => ex1_frb_valid, + din(14) => ex1_frc_valid, + din(15) => ex1_frs_byp, + dout(0 to 5) => ex2_instr_frt(0 to 5), + dout(6) => ex2_cr_val, + dout(7) => ex2_record, + dout(8) => ex2_kill_wen, + dout(9) => ex2_mcrfs, + dout(10) => ex2_instr_match, + dout(11) => ex2_is_ucode, + dout(12) => ex2_fra_v, + dout(13) => ex2_frb_v, + dout(14) => ex2_frc_v, + dout(15) => ex2_frs_byp + ); + + + ex2_stdv_lat: tri_rlmreg_p generic map (init => 0, expand_type => expand_type, width => 1) port map ( + nclk => nclk, + act => tihi, + forcee => forcee, + delay_lclkr => delay_lclkr(2), + mpw1_b => mpw1_b(2), + mpw2_b => mpw2_b(0), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin(0) => ex2_stdv_si, + scout(0) => ex2_stdv_so, + din(0) => ex1_str_valid, + dout(0) => ex2_store_valid ); + + + + ex2_perr: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 24) + port map (nclk => nclk, + act => ex1_axu_v, + forcee => forcee, + delay_lclkr => delay_lclkr(2), + mpw1_b => mpw1_b(2), + mpw2_b => mpw2_b(0), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => ex2_perr_si(0 to 23), + scout => ex2_perr_so(0 to 23), + din( 0 to 5) => ex1_instr_frs(0 to 5) , + din( 6 to 11) => ex1_instr_fra(0 to 5) , + din(12 to 17) => ex1_instr_frb(0 to 5) , + din(18 to 23) => ex1_instr_frc(0 to 5) , + dout( 0 to 5) => ex2_instr_frs(0 to 5) , + dout( 6 to 11) => ex2_instr_fra(0 to 5) , + dout(12 to 17) => ex2_instr_frb(0 to 5) , + dout(18 to 23) => ex2_instr_frc(0 to 5) + ); + + + ex2_sto_perr(0 to 3) <= (0 to 3 => f_sto_ex2_s_parity_check and ex2_str_v and not ex2_frs_byp) and ex2_ldst_v(0 to 3); + + ex2_abc_perr(0 to 3) <= (0 to 3 => (f_mad_ex2_a_parity_check and ex2_fra_v) or + (f_mad_ex2_b_parity_check and ex2_frb_v) or + (f_mad_ex2_c_parity_check and ex2_frc_v) ) and ex2_instr_v(0 to 3); + + ex2_fpr_perr(0 to 3) <= (ex2_sto_perr(0 to 3) or ex2_abc_perr(0 to 3)) and not xu_ex2_flush(0 to 3) and (0 to 3 => msr_fp_act); + + ex2_regfile_err_det <= or_reduce((ex2_sto_perr(0 to 3) or ex2_abc_perr(0 to 3)) and not xu_ex2_flush(0 to 3)) and msr_fp_act; + + ex2_f0a_perr <= f_mad_ex2_a_parity_check and ex2_fra_v ; + ex2_f0c_perr <= f_mad_ex2_c_parity_check and (ex2_frc_v or (perr_sm_l2(1) and ex2_perr_sm_instr_v) ); + ex2_f1b_perr <= f_mad_ex2_b_parity_check and (ex2_frb_v or (perr_sm_l2(1) and ex2_perr_sm_instr_v) ); + ex2_f1s_perr <= f_sto_ex2_s_parity_check and ex2_str_v ; + + ex2_instr_valid(0 to 3) <= ex2_instr_v(0 to 3) and not xu_ex2_flush(0 to 3); + + fu_xu_ex2_store_data_val <= ex2_store_valid; + + fu_xu_ex2_ifar_val(0 to 3) <= ex2_ifar_val(0 to 3); + fu_xu_ex2_ifar_issued(0 to 3) <= ex2_instr_iss(0 to 3); + + fu_xu_ex2_instr_type(0 to 11) <= tilo_out & tilo_out & tihi_out & + tilo_out & tilo_out & tihi_out & + tilo_out & tilo_out & tihi_out & + tilo_out & tilo_out & tihi_out ; + + fu_xu_ex2_instr_match(0 to 3) <= (0 to 3 => ex2_instr_match); + fu_xu_ex2_is_ucode(0 to 3) <= (0 to 3 => ex2_is_ucode); + + fu_xu_ex2_async_block(0 to 3) <= ex2_async_block(0 to 3); + + ex2_fu_or_ldst_v(0 to 3) <= (ex2_instr_v(0 to 3) or ex2_ldst_v(0 to 3)) and not xu_ex2_flush(0 to 3); + + ex2_iu_n_flush(0 to 3) <= iu_fu_ex2_n_flush(0 to 3) and ex2_fu_or_ldst_v(0 to 3); + + ex2_n_flush(0 to 3) <= (ex2_instr_valid(0 to 3) and (0 to 3 => f_ex2_b_den_flush)) or + ex2_iu_n_flush(0 to 3) ; + + ex2_axu_v <= or_reduce(ex2_instr_v(0 to 3) or ex2_ldst_v(0 to 3)); + + ex2_flush2ucode(0 to 3) <= ex2_instr_v(0 to 3) and (0 to 3 => f_ex2_b_den_flush) and not ex2_iu_n_flush(0 to 3) and not xu_ex2_flush(0 to 3); + + + + ex3_ctlng: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 16) + port map (nclk => nclk, + act => tihi, + forcee => forcee, + delay_lclkr => delay_lclkr(3), + mpw1_b => mpw1_b(3), + mpw2_b => mpw2_b(0), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => ex3_ctlng_si(0 to 15), + scout => ex3_ctlng_so(0 to 15), + din( 0 to 3) => ex2_instr_valid(0 to 3), + din( 4 to 7) => ex2_n_flush(0 to 3), + din( 8 to 11) => ex2_flush2ucode(0 to 3), + din(12 to 15) => ex2_fpr_perr(0 to 3), + dout( 0 to 3) => ex3_instr_v(0 to 3), + dout( 4 to 7) => ex3_n_flush(0 to 3), + dout( 8 to 11) => ex3_flush2ucode(0 to 3), + dout(12 to 15) => ex3_regfile_err_det(0 to 3) + ); + + ex3_ctl: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 13) + port map (nclk => nclk, + act => ex2_axu_v, + forcee => forcee, + delay_lclkr => delay_lclkr(3), + mpw1_b => mpw1_b(3), + mpw2_b => mpw2_b(0), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => ex3_ctl_si(0 to 12), + scout => ex3_ctl_so(0 to 12), + din(0 to 5) => ex2_instr_frt(0 to 5), + din(6) => ex2_cr_val, + din(7) => ex2_record, + din(8) => f_ex2_b_den_flush, + din(9) => ex2_kill_wen, + din(10) => ex2_mcrfs, + din(11) => ex2_instr_match, + din(12) => ex2_is_ucode, + dout(0 to 5) => ex3_instr_frt(0 to 5), + dout(6) => ex3_cr_val, + dout(7) => ex3_record, + dout(8) => ex3_b_den_flush, + dout(9) => ex3_kill_wen, + dout(10) => ex3_mcrfs, + dout(11) => ex3_instr_match, + dout(12) => ex3_is_ucode + ); + + + ex3_instr_valid(0 to 3) <= ex3_instr_v(0 to 3) and not xu_ex3_flush(0 to 3) and (0 to 3 => msr_fp_act); + + + + fu_xu_ex3_n_flush(0 to 3) <= ex3_n_flush(0 to 3) ; + + + fu_xu_ex3_np1_flush(0 to 3) <= tilo_out & tilo_out & tilo_out & tilo_out; + fu_xu_ex3_ap_int_req(0 to 3) <= tilo_out & tilo_out & tilo_out & tilo_out; + + fu_xu_ex3_flush2ucode(0 to 3) <= ex3_flush2ucode; + + + fu_xu_ex3_trap(0 to 3) <= (f_scr_ex7_fx_thread0(1) & f_scr_ex7_fx_thread1(1) & + f_scr_ex7_fx_thread2(1) & f_scr_ex7_fx_thread3(1) ) ; + + fu_xu_ex3_regfile_err_det(0 to 3) <= ex3_regfile_err_det(0 to 3); + + + ex4_ctl_lat: tri_rlmreg_p generic map (init => 0, expand_type => expand_type, width => 16) port map ( + nclk => nclk, + act => tihi, + forcee => forcee, + delay_lclkr => delay_lclkr(4), + mpw1_b => mpw1_b(4), + mpw2_b => mpw2_b(0), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => ex4_ctl_si, + scout => ex4_ctl_so, + din(0 to 3) => ex3_instr_valid(0 to 3), + din(4 to 9) => ex3_instr_frt(0 to 5), + din(10) => ex3_cr_val, + din(11) => ex3_cr_val, + din(12) => ex3_record, + din(13) => ex3_kill_wen, + din(14) => ex3_mcrfs, + din(15) => ex3_is_ucode, + dout(0 to 3) => ex4_instr_v(0 to 3), + dout(4 to 9) => ex4_instr_frt(0 to 5), + dout(10) => ex4_cr_val, + dout(11) => ex4_cr_val_cp, + dout(12) => ex4_record, + dout(13) => ex4_kill_wen, + dout(14) => ex4_mcrfs, + dout(15) => ex4_is_ucode + ); + + + + ex4_cr_val_cp_b <= not( ex4_cr_val_cp) ; + + u_cr_o1: ex7_cr_fld_x_b(0 to 3) <= not( f_scr_ex7_cr_fld (0 to 3) and (0 to 3 => ex4_cr_val_cp_b) ); + u_cr_o2: ex4_fpcc_x_b(0 to 3) <= not( f_add_ex4_fpcc_iu(0 to 3) and (0 to 3 => ex4_cr_val_cp) ); + u_cr_o: fu_xu_ex4_cr(0 to 3) <= not( ex4_fpcc_x_b(0 to 3) and ex7_cr_fld_x_b(0 to 3) ); + + + + + ex4_instr_valid(0 to 3) <= ex4_instr_v(0 to 3) and not xu_ex4_flush(0 to 3); + + fu_xu_ex4_cr_val <= (ex4_instr_v (0 to 3) and (0 to 3 => ex4_cr_val)) or + ex7_record_v(0 to 3); + + fu_xu_ex4_cr_bf(0 to 2) <= (ex4_instr_frt(1 to 3) and (0 to 2 => ex4_cr_val)) or + (ex7_bf(0 to 2) and not (0 to 2 => ex4_cr_val)) ; + + fu_xu_ex4_cr_noflush(0 to 3) <= ex7_record_v(0 to 3); + + + + ex5_record_din <= ex4_record and or_reduce(ex4_instr_valid(0 to 3)); + ex5_mcrfs_din <= ex4_mcrfs and or_reduce(ex4_instr_valid(0 to 3)); + ex5_cr_val_din <= ex4_cr_val and or_reduce(ex4_instr_valid(0 to 3)); + + ex4_instr_tid(0) <= ex4_instr_v(2) or ex4_instr_v(3); + ex4_instr_tid(1) <= ex4_instr_v(1) or ex4_instr_v(3); + + ex5_kill_wen_din <= ex4_kill_wen or (ex4_uc_special and ex4_is_ucode); + + + ex5_instr_valid_din(0) <= ex4_instr_valid(0); + ex5_instr_valid_din(1) <= ex4_instr_valid(1); + ex5_instr_valid_din(2) <= ex4_instr_valid(2); + ex5_instr_valid_din(3) <= ex4_instr_valid(3); + + ex5_instr_frt_din(0 to 5) <= (ex4_instr_frt(0 to 5) and not (0 to 5 => perr_sm_l2(2))) or + (perr_addr_l2 (0 to 5) and (0 to 5 => perr_sm_l2(2))) ; + + + ex5_ctl: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 15) + port map (nclk => nclk, + act => tihi, + forcee => forcee, + delay_lclkr => delay_lclkr(5), + mpw1_b => mpw1_b(5), + mpw2_b => mpw2_b(1), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => ex5_ctl_si(0 to 14), + scout => ex5_ctl_so(0 to 14), + din(0 to 3) => ex5_instr_valid_din(0 to 3), + din(4 to 9) => ex5_instr_frt_din(0 to 5), + din(10) => ex5_record_din, + din(11) => ex5_mcrfs_din, + din(12) => ex4_is_ucode, + din(13) => ex5_cr_val_din, + din(14) => ex5_kill_wen_din, + dout(0 to 3) => ex5_instr_v(0 to 3), + dout(4 to 9) => ex5_instr_frt(0 to 5), + dout(10) => ex5_record, + dout(11) => ex5_mcrfs, + dout(12) => ex5_is_ucode, + dout(13) => ex5_cr_val, + dout(14) => ex5_kill_wen + ); + + ex5_instr_tid(0) <= ex5_instr_v(2) or ex5_instr_v(3); + ex5_instr_tid(1) <= ex5_instr_v(1) or ex5_instr_v(3); + + + + +ex5_reload_val_b(0) <= not (xu_fu_ex5_load_val(0) and xu_fu_ex5_reload_val); +ex5_reload_val_b(1) <= not (xu_fu_ex5_load_val(1) and xu_fu_ex5_reload_val); +ex5_reload_val_b(2) <= not (xu_fu_ex5_load_val(2) and xu_fu_ex5_reload_val); +ex5_reload_val_b(3) <= not (xu_fu_ex5_load_val(3) and xu_fu_ex5_reload_val); + + + u5_iflsh_int0b: ex5_iflush_int_b(0) <= not( xu_ex5_flush(0) and ex5_reload_val_b(0) ); + u5_iflsh_int1b: ex5_iflush_int_b(1) <= not( xu_ex5_flush(1) and ex5_reload_val_b(1) ); + u5_iflsh_int2b: ex5_iflush_int_b(2) <= not( xu_ex5_flush(2) and ex5_reload_val_b(2) ); + u5_iflsh_int3b: ex5_iflush_int_b(3) <= not( xu_ex5_flush(3) and ex5_reload_val_b(3) ); + + u5_iflsh_int0: xu_ex5_flush_int(0) <= not( ex5_iflush_int_b(0) ); + u5_iflsh_int1: xu_ex5_flush_int(1) <= not( ex5_iflush_int_b(1) ); + u5_iflsh_int2: xu_ex5_flush_int(2) <= not( ex5_iflush_int_b(2) ); + u5_iflsh_int3: xu_ex5_flush_int(3) <= not( ex5_iflush_int_b(3) ); + +f_dcd_ex5_flush_int <= xu_ex5_flush_int(0 to 3) ; + + + + u5_iflsh0: ex5_iflush_b(0) <= not( xu_ex5_flush(0) and ex5_instr_v(0) ); + u5_iflsh1: ex5_iflush_b(1) <= not( xu_ex5_flush(1) and ex5_instr_v(1) ); + u5_iflsh2: ex5_iflush_b(2) <= not( xu_ex5_flush(2) and ex5_instr_v(2) ); + u5_iflsh3: ex5_iflush_b(3) <= not( xu_ex5_flush(3) and ex5_instr_v(3) ); + + u5_iflsh_01: ex5_iflush_01 <= not( ex5_iflush_b(0) and ex5_iflush_b(1) ); + u5_iflsh_23: ex5_iflush_23 <= not( ex5_iflush_b(2) and ex5_iflush_b(3) ); + + u5_iflsh_b: ex5_instr_flush_b <= not( ex5_iflush_01 or ex5_iflush_23 ) ; + + u5_iflsh: ex5_instr_flush <= not ex5_instr_flush_b ; + + + + + + ex5_instr_valid(0) <= ex5_instr_v(0) and not xu_ex5_flush(0); + ex5_instr_valid(1) <= ex5_instr_v(1) and not xu_ex5_flush(1); + ex5_instr_valid(2) <= ex5_instr_v(2) and not xu_ex5_flush(2); + ex5_instr_valid(3) <= ex5_instr_v(3) and not xu_ex5_flush(3); + + ex6_instr_valid_din(0) <= ex5_instr_valid(0) or (perr_sm_l2(2) and ex5_perr_sm_instr_v and perr_tid_enc(0 to 1)="00"); + ex6_instr_valid_din(1) <= ex5_instr_valid(1) or (perr_sm_l2(2) and ex5_perr_sm_instr_v and perr_tid_enc(0 to 1)="01"); + ex6_instr_valid_din(2) <= ex5_instr_valid(2) or (perr_sm_l2(2) and ex5_perr_sm_instr_v and perr_tid_enc(0 to 1)="10"); + ex6_instr_valid_din(3) <= ex5_instr_valid(3) or (perr_sm_l2(2) and ex5_perr_sm_instr_v and perr_tid_enc(0 to 1)="11"); + + ex6_kill_wen_din <= (ex5_kill_wen or not f_pic_ex5_fpr_wr_dis_b) and not (perr_sm_l2(2) and ex5_perr_sm_instr_v); + + + ex5_instr_bypval(0) <= ex5_instr_v(0) and f_pic_ex5_fpr_wr_dis_b and not ex5_kill_wen; + ex5_instr_bypval(1) <= ex5_instr_v(1) and f_pic_ex5_fpr_wr_dis_b and not ex5_kill_wen; + ex5_instr_bypval(2) <= ex5_instr_v(2) and f_pic_ex5_fpr_wr_dis_b and not ex5_kill_wen; + ex5_instr_bypval(3) <= ex5_instr_v(3) and f_pic_ex5_fpr_wr_dis_b and not ex5_kill_wen; + + + f_dcd_ex5_frt_tid(0 to 1) <= ex5_instr_tid(0 to 1); + + ex6_record_din <= ex5_record and not ex5_instr_flush; + ex6_mcrfs_din <= ex5_mcrfs and not ex5_instr_flush; + ex6_cr_val_din <= ex5_cr_val and not ex5_instr_flush; + + + + ex6_ctl: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 16) + port map (nclk => nclk, + act => tihi, + forcee => forcee, + delay_lclkr => delay_lclkr(6), + mpw1_b => mpw1_b(6), + mpw2_b => mpw2_b(1), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => ex6_ctl_si(0 to 15), + scout => ex6_ctl_so(0 to 15), + din(0 to 3) => ex6_instr_valid_din(0 to 3), + din(4 to 9) => ex5_instr_frt(0 to 5), + din(10) => ex6_record_din, + din(11) => ex6_mcrfs_din, + din(12) => ex5_is_ucode, + din(13) => ex6_cr_val_din, + din(14) => ex6_kill_wen_din, + din(15) => ex5_perr_sm_instr_v, + dout(0 to 3) => ex6_instr_v(0 to 3), + dout(4 to 9) => ex6_instr_frt(0 to 5), + dout(10) => ex6_record, + dout(11) => ex6_mcrfs, + dout(12) => ex6_is_ucode, + dout(13) => ex6_cr_val, + dout(14) => ex6_kill_wen, + dout(15) => ex6_is_fixperr + ); + + ex6_instr_tid(0) <= ex6_instr_v(2) or ex6_instr_v(3); + ex6_instr_tid(1) <= ex6_instr_v(1) or ex6_instr_v(3); + + ex6_instr_valid <= or_reduce(ex6_instr_v(0 to 3)) ; + + f_dcd_ex6_frt_addr(0 to 5) <= ex6_instr_frt(0 to 5); + f_dcd_ex6_frt_tid(0 to 1) <= ex6_instr_tid(0 to 1); + f_dcd_ex6_frt_wen <= ex6_instr_valid and not ex6_kill_wen; + + f_dcd_ex6_cancel <= not ex6_instr_valid; + + ex6_record_v(0) <= ex6_instr_v(0) and (ex6_record or ex6_mcrfs); + ex6_record_v(1) <= ex6_instr_v(1) and (ex6_record or ex6_mcrfs); + ex6_record_v(2) <= ex6_instr_v(2) and (ex6_record or ex6_mcrfs); + ex6_record_v(3) <= ex6_instr_v(3) and (ex6_record or ex6_mcrfs); + + + ex6_bf(0 to 2) <= (ex6_instr_frt(1 to 3) and (1 to 3 => ex6_mcrfs)) or + ( "001" and not (1 to 3 => ex6_mcrfs)); + + + + ex7_ctl: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 7) + port map (nclk => nclk, + act => tihi, + forcee => forcee, + delay_lclkr => delay_lclkr(7), + mpw1_b => mpw1_b(7), + mpw2_b => mpw2_b(1), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => ex7_ctl_si(0 to 6), + scout => ex7_ctl_so(0 to 6), + din(0 to 3) => ex6_record_v(0 to 3), + din(4 to 6) => ex6_bf(0 to 2), + dout(0 to 3) => ex7_record_v(0 to 3), + dout(4 to 6) => ex7_bf(0 to 2) + ); + + + perr_sm: tri_rlmreg_p + generic map (init => 4, expand_type => expand_type, width => 3) + port map (nclk => nclk, + act => tihi, + forcee => forcee, + delay_lclkr => delay_lclkr(9), + mpw1_b => mpw1_b(9), + mpw2_b => mpw2_b(1), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => perr_sm_si(0 to 2), + scout => perr_sm_so(0 to 2), + din( 0 to 2) => perr_sm_din(0 to 2) , + dout( 0 to 2) => perr_sm_l2(0 to 2) + ); + perr_ctl: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 25) + port map (nclk => nclk, + act => msr_fp_act, + forcee => forcee, + delay_lclkr => delay_lclkr(9), + mpw1_b => mpw1_b(9), + mpw2_b => mpw2_b(1), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => perr_ctl_si(0 to 24), + scout => perr_ctl_so(0 to 24), + din( 0 to 5) => perr_addr_din(0 to 5), + din( 6 to 9) => perr_tid_din(0 to 3), + din(10) => perr_move_f0_to_f1, + din(11) => perr_move_f1_to_f0, + din(12) => rf0_perr_force_c, + din(13) => rf1_perr_force_c, + din(14) => new_perr_sm_instr_v, + din(15) => rf0_perr_sm_instr_v, + din(16) => rf1_perr_sm_instr_v, + din(17) => ex1_perr_sm_instr_v, + din(18) => ex2_perr_sm_instr_v, + din(19) => ex3_perr_sm_instr_v, + din(20) => ex4_perr_sm_instr_v, + din(21) => xu_fu_regfile_seq_beg, + din(22) => regfile_seq_end, + din(23) => rf0_regfile_ue, + din(24) => rf0_regfile_ce, + dout( 0 to 5) => perr_addr_l2(0 to 5) , + dout( 6 to 9) => perr_tid_l2(0 to 3), + dout(10) => perr_move_f0_to_f1_l2, + dout(11) => perr_move_f1_to_f0_l2, + dout(12) => rf1_perr_force_c, + dout(13) => ex1_perr_force_c, + dout(14) => rf0_perr_sm_instr_v, + dout(15) => rf1_perr_sm_instr_v, + dout(16) => ex1_perr_sm_instr_v, + dout(17) => ex2_perr_sm_instr_v, + dout(18) => ex3_perr_sm_instr_v, + dout(19) => ex4_perr_sm_instr_v, + dout(20) => ex5_perr_sm_instr_v, + dout(21) => regfile_seq_beg, + dout(22) => fu_xu_regfile_seq_end, + dout(23) => rf1_regfile_ue, + dout(24) => rf1_regfile_ce + ); + + rf0_perr_sm_instr_v_b <= not rf0_perr_sm_instr_v; + + perr_tid_enc(0) <= perr_tid_l2(2) or perr_tid_l2(3); + perr_tid_enc(1) <= perr_tid_l2(1) or perr_tid_l2(3); + + + perr_sm_running <= not perr_sm_l2(0); + f_dcd_perr_sm_running <= perr_sm_running; + + perr_sm_ns(0) <= (perr_sm_l2(2) and rf0_regfile_ue) or (perr_sm_l2(2) and ex5_perr_sm_instr_v); + regfile_seq_end <= perr_sm_ns(0) ; + + perr_sm_ns(1) <= perr_sm_l2(0) and regfile_seq_beg; + + perr_sm_ns(2) <= perr_sm_l2(1) and ex5_perr_sm_instr_v; + + perr_move_f0_to_f1 <= ex2_f1b_perr when (perr_sm_l2(1) and ex2_perr_sm_instr_v) = '1' else + perr_move_f0_to_f1_l2 ; + perr_move_f1_to_f0 <= ex2_f0c_perr when (perr_sm_l2(1) and ex2_perr_sm_instr_v) = '1' else + perr_move_f1_to_f0_l2 ; + + + rf0_perr_move_f0_to_f1 <= perr_move_f0_to_f1_l2 and (perr_sm_l2(2) and rf0_perr_sm_instr_v); + rf0_perr_move_f1_to_f0 <= perr_move_f1_to_f0_l2 and (perr_sm_l2(2) and rf0_perr_sm_instr_v); + + rf0_perr_force_c <= rf0_perr_move_f0_to_f1 and not rf0_perr_move_f1_to_f0; + + f_dcd_ex1_perr_force_c <= ex1_perr_force_c; + f_dcd_ex1_perr_fsel_ovrd <= ex1_perr_sm_instr_v and perr_sm_l2(2); + + perr_sm_din(0 to 2) <= ("100" and (0 to 2 => perr_sm_ns(0))) or + ("010" and (0 to 2 => perr_sm_ns(1))) or + ("001" and (0 to 2 => perr_sm_ns(2))) or + (perr_sm_l2 and (0 to 2 => not (or_reduce(perr_sm_ns(0 to 2))))); + + new_perr_sm_instr_v <= perr_sm_ns(1) or perr_sm_ns(2); + + + perr_addr_din(0 to 5) <= ex2_instr_fra(0 to 5) when (ex2_f0a_perr and ex2_regfile_err_det and perr_sm_l2(0)) = '1' else + ex2_instr_frb(0 to 5) when (ex2_f1b_perr and ex2_regfile_err_det and perr_sm_l2(0)) = '1' else + ex2_instr_frc(0 to 5) when (ex2_f0c_perr and ex2_regfile_err_det and perr_sm_l2(0)) = '1' else + ex2_instr_frs(0 to 5) when (ex2_f1s_perr and ex2_regfile_err_det and perr_sm_l2(0)) = '1' else + perr_addr_l2(0 to 5); + + + perr_tid_din(0 to 3) <= (ex2_fpr_perr(0 to 3) and (0 to 3 => ex2_regfile_err_det and perr_sm_l2(0))) or + (perr_tid_l2(0 to 3) and not (0 to 3 => ex2_regfile_err_det and perr_sm_l2(0))); + + u_pc_o1: rf0_frc_perr_x_b(0 to 5) <= not( perr_addr_l2 (0 to 5) and (0 to 5 => rf0_perr_sm_instr_v ) ); + u_pc_o2: rf0_frc_iu_x_b(0 to 5) <= not( rf0_instr_frc (0 to 5) and (0 to 5 => rf0_perr_sm_instr_v_b) ); + u_pc_o: f_dcd_rf0_frc(0 to 5) <= not( rf0_frc_perr_x_b(0 to 5) and rf0_frc_iu_x_b(0 to 5) ); + + u_pb_o1: rf0_frb_perr_x_b(0 to 5) <= not( perr_addr_l2 (0 to 5) and (0 to 5 => rf0_perr_sm_instr_v ) ); + u_pb_o2: rf0_frb_iu_x_b(0 to 5) <= not( rf0_instr_frb (0 to 5) and (0 to 5 => rf0_perr_sm_instr_v_b) ); + u_pb_o: f_dcd_rf0_frb(0 to 5) <= not( rf0_frb_perr_x_b(0 to 5) and rf0_frb_iu_x_b(0 to 5) ); + + u_pt_o1: rf0_tid_perr_x_b(0 to 1) <= not( perr_tid_enc (0 to 1) and (0 to 1 => rf0_perr_sm_instr_v ) ); + u_pt_o2: rf0_tid_iu_x_b(0 to 1) <= not( rf0_tid (0 to 1) and (0 to 1 => rf0_perr_sm_instr_v_b) ); + u_pt_o: f_dcd_rf0_tid(0 to 1) <= not( rf0_tid_perr_x_b(0 to 1) and rf0_tid_iu_x_b(0 to 1) ); + + rf0_regfile_ce <= (rf0_perr_move_f0_to_f1 or rf0_perr_move_f1_to_f0) and not (rf0_perr_move_f0_to_f1 and rf0_perr_move_f1_to_f0); + rf0_regfile_ue <= rf0_perr_move_f0_to_f1 and rf0_perr_move_f1_to_f0; + + err_regfile_parity(0 to 3) <= perr_tid_l2(0 to 3) and (0 to 3 => rf1_regfile_ce); + err_regfile_ue(0 to 3) <= perr_tid_l2(0 to 3) and (0 to 3 => rf1_regfile_ue); + + + fu_err_rpt : entity tri.tri_direct_err_rpt(tri_direct_err_rpt) + generic map (width => 8, expand_type => expand_type) + port map (vd => vdd, gd => gnd, + err_in(0) => err_regfile_parity(0), + err_in(1) => err_regfile_parity(1), + err_in(2) => err_regfile_parity(2), + err_in(3) => err_regfile_parity(3), + err_in(4) => err_regfile_ue(0), + err_in(5) => err_regfile_ue(1), + err_in(6) => err_regfile_ue(2), + err_in(7) => err_regfile_ue(3), + err_out(0) => fu_pc_err_regfile_parity(0), + err_out(1) => fu_pc_err_regfile_parity(1), + err_out(2) => fu_pc_err_regfile_parity(2), + err_out(3) => fu_pc_err_regfile_parity(3), + err_out(4) => fu_pc_err_regfile_ue(0), + err_out(5) => fu_pc_err_regfile_ue(1), + err_out(6) => fu_pc_err_regfile_ue(2), + err_out(7) => fu_pc_err_regfile_ue(3) ); + + + + + ucode_hooks : entity work.fuq_dcd_uc_hooks + generic map(expand_type => expand_type) + port map( + nclk => nclk, + thold_0_b => thold_0_b, + sg_0 => sg_0, + f_ucode_si => f_ucode_si, + forcee => forcee, + delay_lclkr => delay_lclkr(9), + mpw1_b => mpw1_b(9), + mpw2_b => mpw2_b(1), + vdd => vdd, + gnd => gnd, + msr_fp_act => msr_fp_act, + perr_sm_running => perr_sm_running, + iu_fu_rf0_instr_v => iu_fu_rf0_instr_v, + iu_fu_rf0_instr => iu_fu_rf0_instr, + ucode_mode_rf0 => iu_fu_rf0_is_ucode, + iu_fu_rf0_ucfmul => iu_fu_rf0_ucfmul, + f_mad_ex3_uc_round_mode => f_mad_ex3_uc_round_mode, + rf0_instr_fra => rf0_instr_fra, + f_dcd_rf0_fra => f_dcd_rf0_fra, + iu_fu_rf0_ifar => iu_fu_rf0_ifar(58 to 61), + thread_id_rf0 => thread_id_rf0, + xu_rf0_flush => xu_rf0_flush, + xu_rf1_flush => xu_rf1_flush, + xu_ex1_flush => xu_ex1_flush, + xu_ex2_flush => xu_ex2_flush, + xu_ex3_flush => xu_ex3_flush, + xu_ex4_flush => xu_ex4_flush, + xu_ex5_flush => xu_ex5_flush, + f_mad_ex3_uc_res_sign => f_mad_ex3_uc_res_sign, + f_mad_ex6_uc_sign => f_mad_ex6_uc_sign, + f_mad_ex6_uc_zero => f_mad_ex6_uc_zero, + f_mad_ex3_uc_special => f_mad_ex3_uc_special, + f_mad_ex3_uc_vxsnan => f_mad_ex3_uc_vxsnan, + f_mad_ex3_uc_zx => f_mad_ex3_uc_zx, + f_mad_ex3_uc_vxidi => f_mad_ex3_uc_vxidi, + f_mad_ex3_uc_vxzdz => f_mad_ex3_uc_vxzdz, + f_mad_ex3_uc_vxsqrt => f_mad_ex3_uc_vxsqrt, + f_dcd_rf1_div_beg => rf1_div_beg, + f_dcd_rf1_sqrt_beg => rf1_sqrt_beg, + f_dcd_rf1_uc_mid => f_dcd_rf1_uc_mid, + f_dcd_rf1_uc_end => rf1_uc_end, + ex4_uc_special => ex4_uc_special, + f_dcd_rf1_uc_special => f_dcd_rf1_uc_special, + f_dcd_rf1_uc_ft_pos => f_dcd_rf1_uc_ft_pos, + f_dcd_rf1_uc_ft_neg => f_dcd_rf1_uc_ft_neg, + f_dcd_rf1_uc_fa_pos => f_dcd_rf1_uc_fa_pos, + f_dcd_rf1_uc_fc_pos => f_dcd_rf1_uc_fc_pos, + f_dcd_rf1_uc_fb_pos => f_dcd_rf1_uc_fb_pos, + f_dcd_rf1_uc_fc_hulp => f_dcd_rf1_uc_fc_hulp, + f_dcd_rf1_uc_fc_0_5 => f_dcd_rf1_uc_fc_0_5, + f_dcd_rf1_uc_fc_1_0 => f_dcd_rf1_uc_fc_1_0, + f_dcd_rf1_uc_fc_1_minus => f_dcd_rf1_uc_fc_1_minus, + f_dcd_rf1_uc_fb_1_0 => f_dcd_rf1_uc_fb_1_0, + f_dcd_rf1_uc_fb_0_75 => f_dcd_rf1_uc_fb_0_75, + f_dcd_rf1_uc_fb_0_5 => f_dcd_rf1_uc_fb_0_5 , + f_dcd_rf1_uc_fa_dis_par => f_dcd_rf1_uc_fa_dis_par, + f_dcd_rf1_uc_fb_dis_par => f_dcd_rf1_uc_fb_dis_par, + f_dcd_rf1_uc_fc_dis_par => f_dcd_rf1_uc_fc_dis_par, + uc_op_rnd_v_rf1 => rf1_uc_op_rnd_v, + uc_op_rnd_rf1 => rf1_uc_op_rnd, + f_dcd_ex2_uc_inc_lsb => f_dcd_ex2_uc_inc_lsb, + f_dcd_ex2_uc_gs_v => f_dcd_ex2_uc_gs_v , + f_dcd_ex2_uc_gs => f_dcd_ex2_uc_gs , + f_dcd_ex2_uc_vxsnan => f_dcd_ex2_uc_vxsnan, + f_dcd_ex2_uc_zx => f_dcd_ex2_uc_zx , + f_dcd_ex2_uc_vxidi => f_dcd_ex2_uc_vxidi , + f_dcd_ex2_uc_vxzdz => f_dcd_ex2_uc_vxzdz , + f_dcd_ex2_uc_vxsqrt => f_dcd_ex2_uc_vxsqrt , + uc_hooks_rc_rf0 => uc_hooks_rc_rf0, + evnt_div_sqrt_ip => evnt_div_sqrt_ip, + uc_hooks_debug => uc_hooks_debug, + f_ucode_so => f_ucode_so + ); + + rf1_divsqrt_beg <= rf1_div_beg or rf1_sqrt_beg; + + f_dcd_rf1_div_beg <= rf1_div_beg; + f_dcd_rf1_sqrt_beg <= rf1_sqrt_beg; + f_dcd_rf1_uc_end <= rf1_uc_end; + + fu_iu_uc_special(0 to 3) <= (0 to 3 => tilo); + + + spr_ctl: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 15) + port map (nclk => nclk, + act => tihi, + forcee => forcee, + delay_lclkr => delay_lclkr(9), + mpw1_b => mpw1_b(9), + mpw2_b => mpw2_b(1), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => spr_ctl_si(0 to 14), + scout => spr_ctl_so(0 to 14), + din(0) => slowspr_in_val, + din(1) => slowspr_in_rw, + din(2 to 3) => slowspr_in_etid(0 to 1), + din(4 to 13) => slowspr_in_addr(0 to 9), + din(14) => slowspr_in_done, + dout(0) => slowspr_out_val, + dout(1) => slowspr_out_rw, + dout(2 to 3) => slowspr_out_etid(0 to 1), + dout(4 to 13) => slowspr_out_addr(0 to 9), + dout(14) => slowspr_out_done + ); + spr_data: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 2**regmode) + port map (nclk => nclk, + act => tihi, + forcee => forcee, + delay_lclkr => delay_lclkr(9), + mpw1_b => mpw1_b(9), + mpw2_b => mpw2_b(1), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => spr_data_si(64-(2**regmode) to 63), + scout => spr_data_so(64-(2**regmode) to 63), + din => slowspr_in_data, + dout => slowspr_out_data + ); + + axucr0_lat: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 3) + port map (nclk => nclk, + act => tihi, + forcee => cfg_sl_force, + delay_lclkr => delay_lclkr(9), + mpw1_b => mpw1_b(9), + mpw2_b => mpw2_b(1), + thold_b => cfg_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => axucr0_lat_si(0 to 2), + scout => axucr0_lat_so(0 to 2), + din(0 to 2) => axucr0_din(61 to 63), + dout(0 to 2) => axucr0_q(61 to 63) + ); + lcbs_cfg: tri_lcbs + generic map (expand_type => expand_type ) + port map ( + vd => vdd, + gd => gnd, + delay_lclkr => delay_lclkr(9), + nclk => nclk, + forcee => cfg_sl_force, + thold_b => cfg_sl_thold_0_b, + dclk => cfg_slat_d2clk, + lclk => cfg_slat_lclk ); + + cfg_stg: tri_slat_scan + generic map (width => 2, init => "00", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => cfg_slat_d2clk, + lclk => cfg_slat_lclk, + scan_in(0) => ccfg_scan_in, + scan_in(1) => bcfg_scan_in, + scan_out(0) => ccfg_scan_out, + scan_out(1) => bcfg_scan_out ); + + + f_dcd_rf1_force_excp_dis <= axucr0_q(61); + f_dcd_rf1_nj_deni <= axucr0_q(62); + f_dcd_rf1_nj_deno <= axucr0_q(63); + + slowspr_in_val <= slowspr_val_in ; + slowspr_in_rw <= slowspr_rw_in ; + slowspr_in_etid <= slowspr_etid_in ; + slowspr_in_addr <= slowspr_addr_in ; + slowspr_in_data <= slowspr_data_in ; + slowspr_in_done <= slowspr_done_in ; + + axucr0_dec <= slowspr_out_addr(0 to 9) = "1111010000"; + axucr0_rd <= slowspr_out_val and axucr0_dec and slowspr_out_rw; + axucr0_wr <= slowspr_out_val and axucr0_dec and not slowspr_out_rw; + + axucr0_din(61 to 63) <= (slowspr_out_data(61 to 63) and (61 to 63 => axucr0_wr)) or + (axucr0_q(61 to 63) and not (61 to 63 => axucr0_wr)); + + slowspr_data_out(64-(2**regmode) to 60) <= slowspr_out_data(64-(2**regmode) to 60); + + slowspr_data_out(61 to 63) <= (axucr0_q(61 to 63) and (61 to 63 => axucr0_rd)) or + (slowspr_out_data(61 to 63) and not (61 to 63 => axucr0_rd)); + + slowspr_val_out <= slowspr_out_val ; + slowspr_rw_out <= slowspr_out_rw ; + slowspr_etid_out <= slowspr_out_etid ; + slowspr_addr_out <= slowspr_out_addr ; + slowspr_done_out <= slowspr_out_done or axucr0_rd or axucr0_wr ; + + + + ex6_ram_sign <= f_rnd_ex6_res_sign; + ex6_ram_frac(0 to 52) <= f_rnd_ex6_res_frac(0 to 52); + ex6_ram_expo(3 to 13) <= f_rnd_ex6_res_expo(3 to 13); + + ex6_ram_done <= pc_fu_ram_mode and ex6_instr_valid and (pc_fu_ram_thread(0 to 1) = ex6_instr_tid(0 to 1)) + and not ex6_is_ucode + and not ex6_is_fixperr; + + ex7_ram_lat: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 65) + port map (nclk => nclk, + act => ex6_instr_valid, + forcee => forcee, + delay_lclkr => delay_lclkr(9), + mpw1_b => mpw1_b(9), + mpw2_b => mpw2_b(1), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => ram_data_si(0 to 64), + scout => ram_data_so(0 to 64), + din(0) => ex6_ram_sign, + din(1 to 11) => ex6_ram_expo(3 to 13), + din(12 to 64) => ex6_ram_frac(0 to 52), + dout(0) => ex7_ram_sign, + dout(1 to 11) => ex7_ram_expo(3 to 13), + dout(12 to 64) => ex7_ram_frac(0 to 52) + ); + ex7_ramv_lat: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 1) + port map (nclk => nclk, + act => tihi, + forcee => forcee, + delay_lclkr => delay_lclkr(9), + mpw1_b => mpw1_b(9), + mpw2_b => mpw2_b(1), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin(0) => ram_datav_si(0), + scout(0) => ram_datav_so(0), + din(0) => ex6_ram_done, + dout(0) => ex7_ram_done + ); + + ex7_ram_data( 0) <= ex7_ram_sign; + ex7_ram_data( 1 to 11) <= ex7_ram_expo(3 to 13) and (3 to 13 => ex7_ram_frac(0)); + ex7_ram_data(12 to 63) <= ex7_ram_frac(1 to 52); + + fu_pc_ram_done <= ex7_ram_done; + fu_pc_ram_data(0 to 63) <= ex7_ram_data(0 to 63); + + + evnt_axu_instr_cmt(0) <= ex6_instr_valid and (ex6_instr_tid(0 to 1) = "00") and not ex6_is_ucode and not ex6_is_fixperr; + evnt_axu_instr_cmt(1) <= ex6_instr_valid and (ex6_instr_tid(0 to 1) = "01") and not ex6_is_ucode and not ex6_is_fixperr; + evnt_axu_instr_cmt(2) <= ex6_instr_valid and (ex6_instr_tid(0 to 1) = "10") and not ex6_is_ucode and not ex6_is_fixperr; + evnt_axu_instr_cmt(3) <= ex6_instr_valid and (ex6_instr_tid(0 to 1) = "11") and not ex6_is_ucode and not ex6_is_fixperr; + + evnt_axu_cr_cmt(0) <= ex6_instr_valid and (ex6_instr_tid(0 to 1) = "00") and (ex6_cr_val or ex6_record or ex6_mcrfs); + evnt_axu_cr_cmt(1) <= ex6_instr_valid and (ex6_instr_tid(0 to 1) = "01") and (ex6_cr_val or ex6_record or ex6_mcrfs); + evnt_axu_cr_cmt(2) <= ex6_instr_valid and (ex6_instr_tid(0 to 1) = "10") and (ex6_cr_val or ex6_record or ex6_mcrfs); + evnt_axu_cr_cmt(3) <= ex6_instr_valid and (ex6_instr_tid(0 to 1) = "11") and (ex6_cr_val or ex6_record or ex6_mcrfs); + + evnt_axu_idle(0) <= (ex6_instr_tid(0 to 1) = "00") and not (ex6_instr_valid or ex6_cr_val or ex6_record or ex6_mcrfs); + evnt_axu_idle(1) <= (ex6_instr_tid(0 to 1) = "01") and not (ex6_instr_valid or ex6_cr_val or ex6_record or ex6_mcrfs); + evnt_axu_idle(2) <= (ex6_instr_tid(0 to 1) = "10") and not (ex6_instr_valid or ex6_cr_val or ex6_record or ex6_mcrfs); + evnt_axu_idle(3) <= (ex6_instr_tid(0 to 1) = "11") and not (ex6_instr_valid or ex6_cr_val or ex6_record or ex6_mcrfs); + + evnt_denrm_flush(0) <= (ex4_instr_tid(0 to 1) = "00") and ex4_b_den_flush; + evnt_denrm_flush(1) <= (ex4_instr_tid(0 to 1) = "01") and ex4_b_den_flush; + evnt_denrm_flush(2) <= (ex4_instr_tid(0 to 1) = "10") and ex4_b_den_flush; + evnt_denrm_flush(3) <= (ex4_instr_tid(0 to 1) = "11") and ex4_b_den_flush; + + evnt_uc_instr_cmt(0) <= ex6_instr_valid and (ex6_instr_tid(0 to 1) = "00") and ex6_is_ucode; + evnt_uc_instr_cmt(1) <= ex6_instr_valid and (ex6_instr_tid(0 to 1) = "01") and ex6_is_ucode; + evnt_uc_instr_cmt(2) <= ex6_instr_valid and (ex6_instr_tid(0 to 1) = "10") and ex6_is_ucode; + evnt_uc_instr_cmt(3) <= ex6_instr_valid and (ex6_instr_tid(0 to 1) = "11") and ex6_is_ucode; + + evnt_fpu_fx(0 to 3) <= f_scr_ex7_fx_thread0(0) & f_scr_ex7_fx_thread1(0) & f_scr_ex7_fx_thread2(0) & f_scr_ex7_fx_thread3(0) ; + evnt_fpu_fex(0 to 3) <= f_scr_ex7_fx_thread0(1) & f_scr_ex7_fx_thread1(1) & f_scr_ex7_fx_thread2(1) & f_scr_ex7_fx_thread3(1) ; + + t0_events_in(0 to 7) <= evnt_axu_instr_cmt(0) & evnt_axu_cr_cmt(0) & evnt_axu_idle(0) & evnt_div_sqrt_ip(0) & + evnt_denrm_flush(0) & evnt_uc_instr_cmt(0) & evnt_fpu_fx(0) & evnt_fpu_fex(0); + t1_events_in(0 to 7) <= evnt_axu_instr_cmt(1) & evnt_axu_cr_cmt(1) & evnt_axu_idle(1) & evnt_div_sqrt_ip(1) & + evnt_denrm_flush(1) & evnt_uc_instr_cmt(1) & evnt_fpu_fx(1) & evnt_fpu_fex(1); + t2_events_in(0 to 7) <= evnt_axu_instr_cmt(2) & evnt_axu_cr_cmt(2) & evnt_axu_idle(2) & evnt_div_sqrt_ip(2) & + evnt_denrm_flush(2) & evnt_uc_instr_cmt(2) & evnt_fpu_fx(2) & evnt_fpu_fex(2); + t3_events_in(0 to 7) <= evnt_axu_instr_cmt(3) & evnt_axu_cr_cmt(3) & evnt_axu_idle(3) & evnt_div_sqrt_ip(3) & + evnt_denrm_flush(3) & evnt_uc_instr_cmt(3) & evnt_fpu_fx(3) & evnt_fpu_fex(3); + + event_en_d <= ( msr_pr_q and (0 to 3=> event_count_mode_q(0))) or + (not msr_pr_q and msr_gs_q and (0 to 3=> event_count_mode_q(1))) or + (not msr_pr_q and not msr_gs_q and (0 to 3=> event_count_mode_q(2))); + + t0_events <= t0_events_in and (0 to 7 =>event_en_q(0)); + t1_events <= t1_events_in and (0 to 7 =>event_en_q(1)); + t2_events <= t2_events_in and (0 to 7 =>event_en_q(2)); + t3_events <= t3_events_in and (0 to 7 =>event_en_q(3)); + + + event_mux: entity clib.c_event_mux + generic map ( events_in => 32 ) + port map( + vd => vdd , + gd => gnd , + t0_events => t0_events, + t1_events => t1_events, + t2_events => t2_events, + t3_events => t3_events, + + select_bits => pc_fu_event_mux_ctrls, + event_bits => event_data_d + ); + + perf_data: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 39) + port map (nclk => nclk, + act => event_act, + forcee => func_slp_sl_force, + delay_lclkr => delay_lclkr(9), + mpw1_b => mpw1_b(9), + mpw2_b => mpw2_b(1), + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => perf_data_si(0 to 38), + scout => perf_data_so(0 to 38), + din( 0 to 7) => event_data_d(0 to 7), + din( 8 to 11) => event_en_d(0 to 3), + din(12) => ex4_b_den_flush_din, + din(13 to 15) => pc_fu_event_count_mode(0 to 2), + din(16 to 19) => xu_fu_msr_pr(0 to 3), + din(20 to 23) => xu_fu_msr_gs(0 to 3), + din(24) => pc_fu_instr_trace_mode, + din(25 to 26) => pc_fu_instr_trace_tid(0 to 1), + din(27 to 30) => rf0_instr_tid_1hot(0 to 3), + din(31 to 34) => rf1_instr_iss(0 to 3), + din(35 to 38) => ex1_instr_iss(0 to 3), + + dout( 0 to 7) => event_data_q(0 to 7), + dout( 8 to 11) => event_en_q(0 to 3), + dout(12) => ex4_b_den_flush, + dout(13 to 15) => event_count_mode_q(0 to 2), + dout(16 to 19) => msr_pr_q(0 to 3), + dout(20 to 23) => msr_gs_q(0 to 3), + dout(24) => instr_trace_mode_q, + dout(25 to 26) => instr_trace_tid_q(0 to 1), + dout(27 to 30) => rf1_instr_iss(0 to 3), + dout(31 to 34) => ex1_instr_iss(0 to 3), + dout(35 to 38) => ex2_instr_iss(0 to 3) + ); + + + + trace_data_in(0 to 87) <= debug_data_in(0 to 87); + trigger_data_in(0 to 11) <= trace_triggers_in(0 to 11); + + dbg_group0 ( 0 to 63) <= ex7_ram_data(0 to 63); + dbg_group0 (64 to 87) <= ex7_ram_expo(3 to 13) & ex7_ram_frac(0) & ex7_ram_done & (0 to 10 => '0'); + + dbg_group1 (0 to 87) <= uc_hooks_debug(0 to 55) & (56 to 87 => '0'); + + dbg_group2 (0 to 31) <= rf1_instr(0 to 31) and not (0 to 31 => instr_trace_mode_q and (instr_trace_tid_q(0 to 1) /= rf1_tid(0 to 1))); + + dbg_group2 (32 to 35) <= (f_scr_ex7_fx_thread0(0 to 3) and not (0 to 3 => instr_trace_mode_q)); + dbg_group2 (36 to 39) <= (f_scr_ex7_fx_thread1(0 to 3) and not (0 to 3 => instr_trace_mode_q)) or ("1010" and (0 to 3 => instr_trace_mode_q)); + dbg_group2 (40 to 43) <= (f_scr_ex7_fx_thread2(0 to 3) and not (0 to 3 => instr_trace_mode_q)) or ("1011" and (0 to 3 => instr_trace_mode_q)); + dbg_group2 (44 to 47) <= (f_scr_ex7_fx_thread3(0 to 3) and not (0 to 3 => instr_trace_mode_q)) or ("1100" and (0 to 3 => instr_trace_mode_q)); + dbg_group2 (48 to 51) <= (ex4_eff_addr(59 to 62) and not (0 to 3 => instr_trace_mode_q)) or ("1101" and (0 to 3 => instr_trace_mode_q)); + dbg_group2 (52 to 55) <= ((ex4_eff_addr(63) &perr_sm_l2(0 to 2)) and not (0 to 3 => instr_trace_mode_q)) or ("1110" and (0 to 3 => instr_trace_mode_q)); + dbg_group2 (56 to 61) <= perr_addr_l2(0 to 5) and not (0 to 5 => instr_trace_mode_q); + dbg_group2 (62 to 65) <= perr_tid_l2(0 to 3) and not (0 to 3 => instr_trace_mode_q); + dbg_group2 (66) <= rf0_perr_move_f0_to_f1 and not instr_trace_mode_q ; + dbg_group2 (67) <= rf0_perr_move_f1_to_f0 and not instr_trace_mode_q ; + dbg_group2 (68) <= rf1_regfile_ce and not instr_trace_mode_q ; + dbg_group2 (69) <= rf1_regfile_ue and not instr_trace_mode_q ; + dbg_group2 (70 to 87) <= (70 to 87=> tilo); + + dbg_group3 (0) <= rf1_regfile_ce; + dbg_group3 (1) <= rf1_regfile_ue; + dbg_group3 (2) <= rf1_bypsel_a_res0; + dbg_group3 (3) <= rf1_bypsel_c_res0; + dbg_group3 (4) <= rf1_bypsel_b_res0; + dbg_group3 (5) <= rf1_bypsel_a_res1; + dbg_group3 (6) <= rf1_bypsel_c_res1; + dbg_group3 (7) <= rf1_bypsel_b_res1; + dbg_group3 (8) <= rf1_bypsel_a_load0; + dbg_group3 (9) <= rf1_bypsel_c_load0; + dbg_group3 (10) <= rf1_bypsel_b_load0; + dbg_group3 (11) <= rf1_bypsel_a_load1; + dbg_group3 (12) <= rf1_bypsel_c_load1; + dbg_group3 (13) <= rf1_bypsel_b_load1; + dbg_group3 (14) <= rf1_frs_byp; + dbg_group3 (15) <= rf1_v; + dbg_group3 (16 to 31) <= (16 to 31 => '0'); + dbg_group3 (32 to 63) <= t0_events(0 to 7) & t1_events(0 to 7) & t2_events(0 to 7) & t3_events(0 to 7) ; + dbg_group3 (64 to 87) <= (64 to 87=> tilo); + + trg_group0 ( 0 to 3) <= evnt_fpu_fx(0 to 3); + trg_group0 ( 4 to 7) <= evnt_fpu_fex(0 to 3); + trg_group0 ( 8) <= ex6_instr_valid; + trg_group0 ( 9) <= ex6_is_ucode; + trg_group0 (10 to 11) <= ex6_instr_tid(0 to 1); + + trg_group1 ( 0 to 2) <= perr_sm_l2(0 to 2); + trg_group1 ( 3) <= rf1_regfile_ce; + trg_group1 ( 4) <= rf1_regfile_ue; + trg_group1 ( 5) <= ex6_instr_valid; + trg_group1 ( 6 to 7) <= ex6_instr_tid(0 to 1); + trg_group1 ( 8) <= ex3_instr_match; + trg_group1 ( 9) <= ex6_record; + trg_group1 (10) <= ex6_mcrfs; + trg_group1 (11) <= ex4_b_den_flush; + + trg_group2 ( 0 to 11) <= uc_hooks_debug( 0 to 11); + trg_group3 ( 0 to 11) <= uc_hooks_debug(16 to 27); + + + debug_mux_ctrls_muxed(0 to 15) <= debug_mux_ctrls_q(0 to 15) when instr_trace_mode_q = '0' else + ("10" & "000" & "00" & "1111" & "00" & '0' & "11"); + + dbgmux: entity clib.c_debug_mux4 + port map( + vd => vdd , + gd => gnd , + select_bits => debug_mux_ctrls_muxed , + trace_data_in => trace_data_in , + trigger_data_in => trigger_data_in , + dbg_group0 => dbg_group0 , + dbg_group1 => dbg_group1 , + dbg_group2 => dbg_group2 , + dbg_group3 => dbg_group3 , + trg_group0 => trg_group0 , + trg_group1 => trg_group1 , + trg_group2 => trg_group2 , + trg_group3 => trg_group3 , + trace_data_out => trace_data_out , + trigger_data_out => trigger_data_out ); + + + + debug_data_d(0 to 87) <= trace_data_out(0 to 87); + debug_trig_d(0 to 11) <= trigger_data_out(0 to 11); + ex4_b_den_flush_din <= ex3_b_den_flush and or_reduce(ex3_instr_v(0 to 3)); + + dbg0_data: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 116) + port map (nclk => nclk, + act => dbg0_act, + forcee => func_slp_sl_force, + delay_lclkr => delay_lclkr(9), + mpw1_b => mpw1_b(9), + mpw2_b => mpw2_b(1), + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => dbg0_data_si(0 to 115), + scout => dbg0_data_so(0 to 115), + din(0 to 87) => debug_data_d(0 to 87), + din(88 to 99) => debug_trig_d(0 to 11), + din(100 to 115) => pc_fu_debug_mux_ctrls(0 to 15), + dout( 0 to 87) => debug_data_q(0 to 87), + dout(88 to 99) => debug_trig_q(0 to 11), + dout(100 to 115) => debug_mux_ctrls_q(0 to 15) + ); + dbg1_data: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 5) + port map (nclk => nclk, + act => tihi, + forcee => forcee, + delay_lclkr => delay_lclkr(9), + mpw1_b => mpw1_b(9), + mpw2_b => mpw2_b(1), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => dbg1_data_si(0 to 4), + scout => dbg1_data_so(0 to 4), + din( 0 to 4) => xu_fu_ex3_eff_addr(59 to 63), + dout( 0 to 4) => ex4_eff_addr(59 to 63) + ); + + debug_data_out(0 to 87) <= debug_data_q(0 to 87); + trace_triggers_out(0 to 11) <= debug_trig_q(0 to 11); + fu_pc_event_data(0 to 7) <= event_data_q(0 to 7); + + + + spare_lat: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 24) + port map (nclk => nclk, + act => tihi, + forcee => forcee, + delay_lclkr => delay_lclkr(9), + mpw1_b => mpw1_b(9), + mpw2_b => mpw2_b(1), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => spare_si(0 to 23), + scout => spare_so(0 to 23), + din( 0 to 23) => SPARE_L2(0 to 23) , + dout( 0 to 23) => SPARE_L2(0 to 23) + ); + + + spare_unused( 0) <= iu_fu_rf0_ldst_tag(2); + spare_unused( 1) <= iu_fu_rf0_frt(0); + spare_unused( 2) <= iu_fu_rf0_fra(0); + spare_unused( 3) <= iu_fu_rf0_frb(0); + spare_unused( 4) <= iu_fu_rf0_frc(0); + spare_unused( 5 to 8) <= xu_is2_flush(0 to 3); + spare_unused( 9 to 10) <= f_rnd_ex6_res_expo(1 to 2); + + + rf1_iu_si (0 to 14) <= rf1_iu_so (1 to 14) & f_dcd_si; + act_lat_si (0 to 2) <= act_lat_so (1 to 2) & rf1_iu_so (0); + rf0_thread_si(0 to 3) <= rf0_thread_so(1 to 3) & act_lat_so (0); + rf1_frt_si (0 to 31) <= rf1_frt_so (1 to 31) & rf0_thread_so(0); + rf1_ifr_si (62-eff_ifar to 61) <= rf1_ifr_so(63-eff_ifar to 61) & rf1_frt_so (0); + rf1_instl_si (0 to 31) <= rf1_instl_so (1 to 31) & rf1_ifr_so (62-eff_ifar); + rf1_byp_si (0 to 11) <= rf1_byp_so (1 to 11) & rf1_instl_so(0); + ex1_ctl_si (0 to 7) <= ex1_ctl_so (1 to 7) & rf1_byp_so (0); + ex1_frt_si (0 to 17) <= ex1_frt_so (1 to 17) & ex1_ctl_so (0); + ex1_perr_si (0 to 23) <= ex1_perr_so (1 to 23) & ex1_frt_so (0); + ex1_ifar_si (62-eff_ifar to 61) <= ex1_ifar_so(63-eff_ifar to 61) & ex1_perr_so (0); + ex2_ctl_si (0 to 15) <= ex2_ctl_so (1 to 15) & ex1_ifar_so(62-eff_ifar); + ex2_ctlng_si (0 to 16) <= ex2_ctlng_so (1 to 16) & ex2_ctl_so (0); + ex2_perr_si (0 to 23) <= ex2_perr_so (1 to 23) & ex2_ctlng_so(0); + ex2_stdv_si <= ex2_perr_so (0) ; + ex3_ctlng_si (0 to 15) <= ex3_ctlng_so(1 to 15) & ex2_stdv_so; + ex3_ctl_si (0 to 12) <= ex3_ctl_so (1 to 12) & ex3_ctlng_so(0); + ex4_ctl_si (0 to 15) <= ex4_ctl_so (1 to 15) & ex3_ctl_so (0); + ex5_ctl_si (0 to 14) <= ex5_ctl_so (1 to 14) & ex4_ctl_so (0); + ex6_ctl_si (0 to 15) <= ex6_ctl_so (1 to 15) & ex5_ctl_so (0); + ex7_ctl_si (0 to 6) <= ex7_ctl_so (1 to 6) & ex6_ctl_so (0); + perr_sm_si (0 to 2) <= perr_sm_so (1 to 2) & ex7_ctl_so (0); + perr_ctl_si (0 to 24) <= perr_ctl_so (1 to 24) & perr_sm_so (0); + spr_ctl_si (0 to 14) <= spr_ctl_so (1 to 14) & perr_ctl_so(0); + spr_data_si (64-(2**regmode) to 63) <= spr_data_so(65-(2**regmode) to 63) & spr_ctl_so (0); + ram_data_si (0 to 64) <= ram_data_so (1 to 64) & spr_data_so(64-(2**regmode)); + ram_datav_si(0) <= ram_data_so(0); + perf_data_si (0 to 38) <= perf_data_so(1 to 38) & ram_datav_so(0); + dbg0_data_si (0 to 115) <= dbg0_data_so(1 to 115) & perf_data_so(0); + dbg1_data_si (0 to 4) <= dbg1_data_so(1 to 4) & dbg0_data_so(0); + f_ucode_si <= dbg1_data_so(0); + spare_si (0 to 23) <= spare_so(1 to 23) & f_ucode_so; + f_dcd_so <= spare_so(0); + + axucr0_lat_si(0 to 2) <= axucr0_lat_so(1 to 2) & dcfg_scan_in; + dcfg_scan_out <= axucr0_lat_so(0); + +end architecture fuq_dcd; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_dcd_uc_hooks.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_dcd_uc_hooks.vhdl new file mode 100644 index 0000000..fca207a --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_dcd_uc_hooks.vhdl @@ -0,0 +1,1570 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + + +entity fuq_dcd_uc_hooks is +generic(expand_type : integer := 2 ); +port( + nclk : in clk_logic; + thold_0_b : in std_ulogic; + sg_0 : in std_ulogic; + f_ucode_si : in std_ulogic; + forcee : in std_ulogic; + delay_lclkr : in std_ulogic; + mpw1_b : in std_ulogic; + mpw2_b : in std_ulogic; + vdd : inout power_logic; + gnd : inout power_logic; + msr_fp_act : in std_ulogic; + perr_sm_running : in std_ulogic; + iu_fu_rf0_instr_v : in std_ulogic; + iu_fu_rf0_instr : in std_ulogic_vector(0 to 31); + iu_fu_rf0_ucfmul : in std_ulogic; + ucode_mode_rf0 : in std_ulogic; + f_mad_ex3_uc_round_mode : in std_ulogic_vector(0 to 1); + rf0_instr_fra : in std_ulogic_vector(0 to 5); + f_dcd_rf0_fra : out std_ulogic_vector(0 to 5); + iu_fu_rf0_ifar : in std_ulogic_vector(58 to 61); + thread_id_rf0 : in std_ulogic_vector(0 to 3); + xu_rf0_flush : in std_ulogic_vector(0 to 3); + xu_rf1_flush : in std_ulogic_vector(0 to 3); + xu_ex1_flush : in std_ulogic_vector(0 to 3); + xu_ex2_flush : in std_ulogic_vector(0 to 3); + xu_ex3_flush : in std_ulogic_vector(0 to 3); + xu_ex4_flush : in std_ulogic_vector(0 to 3); + xu_ex5_flush : in std_ulogic_vector(0 to 3); + f_mad_ex6_uc_sign, f_mad_ex6_uc_zero : in std_ulogic; + f_mad_ex3_uc_special : in std_ulogic; + f_mad_ex3_uc_vxsnan : in std_ulogic; + f_mad_ex3_uc_zx : in std_ulogic; + f_mad_ex3_uc_vxidi : in std_ulogic; + f_mad_ex3_uc_vxzdz : in std_ulogic; + f_mad_ex3_uc_vxsqrt : in std_ulogic; + f_mad_ex3_uc_res_sign : in std_ulogic; + uc_ignore_flush_rf1 : out std_ulogic; + f_dcd_rf1_div_beg : out std_ulogic; + f_dcd_rf1_sqrt_beg : out std_ulogic; + f_dcd_rf1_uc_mid : out std_ulogic; + f_dcd_rf1_uc_end : out std_ulogic; + ex4_uc_special : out std_ulogic; + f_dcd_rf1_uc_special : out std_ulogic; + f_dcd_rf1_uc_ft_pos : out std_ulogic; + f_dcd_rf1_uc_ft_neg : out std_ulogic; + f_dcd_rf1_uc_fa_pos : out std_ulogic; + f_dcd_rf1_uc_fc_pos : out std_ulogic; + f_dcd_rf1_uc_fb_pos : out std_ulogic; + f_dcd_rf1_uc_fc_hulp : out std_ulogic; + f_dcd_rf1_uc_fc_0_5 : out std_ulogic; + f_dcd_rf1_uc_fc_1_0 : out std_ulogic; + f_dcd_rf1_uc_fc_1_minus : out std_ulogic; + f_dcd_rf1_uc_fb_1_0 : out std_ulogic; + f_dcd_rf1_uc_fb_0_75 : out std_ulogic; + f_dcd_rf1_uc_fb_0_5 : out std_ulogic; + f_dcd_rf1_uc_fa_dis_par : out std_ulogic; + f_dcd_rf1_uc_fb_dis_par : out std_ulogic; + f_dcd_rf1_uc_fc_dis_par : out std_ulogic; + uc_op_rnd_v_rf1 : out std_ulogic; + uc_op_rnd_rf1 : out std_ulogic_vector(0 to 1); + f_dcd_ex2_uc_inc_lsb : out std_ulogic; + f_dcd_ex2_uc_gs_v : out std_ulogic; + f_dcd_ex2_uc_gs : out std_ulogic_vector(0 to 1); + f_dcd_ex2_uc_vxsnan : out std_ulogic; + f_dcd_ex2_uc_zx : out std_ulogic; + f_dcd_ex2_uc_vxidi : out std_ulogic; + f_dcd_ex2_uc_vxzdz : out std_ulogic; + f_dcd_ex2_uc_vxsqrt : out std_ulogic; + uc_hooks_rc_rf0 : out std_ulogic; + uc_hooks_debug : out std_ulogic_vector(0 to 55); + evnt_div_sqrt_ip : out std_ulogic_vector(0 to 3); + f_ucode_so : out std_ulogic + +); + + -- synopsys translate_off + + + + -- synopsys translate_on + +end fuq_dcd_uc_hooks; + + +architecture fuq_dcd_uc_hooks of fuq_dcd_uc_hooks is + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + + +signal uc_sign_zero_t0, uc_scr_t0_ld, uc_scr_t0_l2, uc_scr_t0_scin, uc_scr_t0_scout : std_ulogic_vector(0 to 11); +signal uc_sign_zero_t1, uc_scr_t1_ld, uc_scr_t1_l2, uc_scr_t1_scin, uc_scr_t1_scout : std_ulogic_vector(0 to 11); +signal uc_sign_zero_t2, uc_scr_t2_ld, uc_scr_t2_l2, uc_scr_t2_scin, uc_scr_t2_scout : std_ulogic_vector(0 to 11); +signal uc_sign_zero_t3, uc_scr_t3_ld, uc_scr_t3_l2, uc_scr_t3_scin, uc_scr_t3_scout : std_ulogic_vector(0 to 11); +signal uc_scr_t0_upd, uc_scr_t1_upd, uc_scr_t2_upd, uc_scr_t3_upd : std_ulogic_vector(0 to 4); + +signal uc_scr_wr, uc_scr_wr_rf0 : std_ulogic; +signal uc_scr_sel, uc_scr_thread_rf0 : std_ulogic_vector(0 to 1); + +signal uc_scr_wr_pipe_rf1_scin, uc_scr_wr_pipe_rf1_scout : std_ulogic_vector(0 to 7); +signal uc_scr_wr_rf1 : std_ulogic; +signal uc_scr_sel_rf1, uc_scr_thread_rf1 : std_ulogic_vector(0 to 1); + +signal uc_scr_wr_pipe_ex1_scin, uc_scr_wr_pipe_ex1_scout : std_ulogic_vector(0 to 8); +signal uc_scr_wr_ex1 : std_ulogic; +signal uc_scr_sel_ex1, uc_scr_thread_ex1 : std_ulogic_vector(0 to 1); + +signal uc_scr_wr_pipe_ex2_scin, uc_scr_wr_pipe_ex2_scout : std_ulogic_vector(0 to 8); +signal uc_scr_wr_ex2 : std_ulogic; +signal uc_scr_sel_ex2, uc_scr_thread_ex2 : std_ulogic_vector(0 to 1); + +signal uc_scr_wr_pipe_ex3_scin, uc_scr_wr_pipe_ex3_scout : std_ulogic_vector(0 to 6); +signal uc_scr_wr_ex3 : std_ulogic; +signal uc_scr_sel_ex3, uc_scr_thread_ex3 : std_ulogic_vector(0 to 1); + +signal uc_scr_wr_pipe_ex4_scin, uc_scr_wr_pipe_ex4_scout : std_ulogic_vector(0 to 6); +signal uc_scr_wr_ex4 : std_ulogic; +signal uc_scr_sel_ex4, uc_scr_thread_ex4 : std_ulogic_vector(0 to 1); + +signal uc_scr_wr_pipe_ex5_scin, uc_scr_wr_pipe_ex5_scout : std_ulogic_vector(0 to 5); +signal uc_scr_wr_ex5 : std_ulogic; +signal uc_scr_sel_ex5, uc_scr_thread_ex5 : std_ulogic_vector(0 to 1); + +signal uc_scr_wr_pipe_ex6_scin, uc_scr_wr_pipe_ex6_scout : std_ulogic_vector(0 to 5); +signal uc_scr_wr_ex6 : std_ulogic; +signal uc_scr_sel_ex6, uc_scr_thread_ex6 : std_ulogic_vector(0 to 1); + +signal uc_scr_wr_rf1_l2 : std_ulogic; +signal uc_scr_wr_ex1_l2 : std_ulogic; +signal uc_scr_wr_ex2_l2 : std_ulogic; +signal uc_scr_wr_ex3_l2 : std_ulogic; +signal uc_scr_wr_ex4_l2 : std_ulogic; +signal uc_scr_wr_ex5_l2 : std_ulogic; + +signal q1r_sign_rf0, q1r_zero_rf0 : std_ulogic; +signal q1ulpr_zero_rf0 : std_ulogic; +signal q1_m_ulp_rf0 : std_ulogic; +signal uc_beg_rf0, uc_beg_rf0_v : std_ulogic; +signal uc_beg_rf1 : std_ulogic; +signal uc_beg_ex1 : std_ulogic; +signal uc_beg_ex2 : std_ulogic; +signal uc_beg_ex3 : std_ulogic; +signal uc_beg_ex4 : std_ulogic; +signal uc_end_rf0, uc_end_rf0_v, uc_end_rf0_vf : std_ulogic; +signal uc_normal_end_rf0, uc_normal_end_rf0_part : std_ulogic; +signal uc_fa_pos : std_ulogic; +signal uc_fc_pos : std_ulogic; +signal uc_fc_pos_rf0 : std_ulogic; +signal uc_fb_pos : std_ulogic; +signal uc_fc_hulp : std_ulogic; +signal uc_fc_0_5 : std_ulogic; +signal uc_fc_1_0 : std_ulogic; +signal uc_fc_1_minus : std_ulogic; +signal uc_fb_1_0 : std_ulogic; +signal uc_fb_0_75 : std_ulogic; +signal uc_fb_0_5 : std_ulogic; +signal uc_op_rnd_v : std_ulogic; +signal uc_op_rnd : std_ulogic_vector(0 to 1); +signal uc_inc_lsb : std_ulogic; +signal uc_gs_v_rf0 : std_ulogic; +signal uc_1st_instr_ld : std_ulogic_vector(0 to 3); +signal uc_1st_instr_l2 : std_ulogic_vector(0 to 3); +signal uc_1st_instr_scin : std_ulogic_vector(0 to 3); +signal uc_1st_instr_scout : std_ulogic_vector(0 to 3); +signal uc_div_beg_rf0 : std_ulogic; +signal uc_sqrt_beg_rf0 : std_ulogic; +signal uc_mid_rf0 : std_ulogic; +signal uc_div_beg_rf1 : std_ulogic; +signal uc_sqrt_beg_rf1 : std_ulogic; +signal pipe_rf1_scin : std_ulogic_vector(0 to 21); +signal pipe_rf1_scout : std_ulogic_vector(0 to 21); +signal fp_operation_rf0 : std_ulogic; +signal uc_special_cases_ex3 : std_ulogic_vector(0 to 7); +signal uc_special_cases_t0_ex3 : std_ulogic_vector(8 to 11); +signal uc_special_cases_t1_ex3 : std_ulogic_vector(8 to 11); +signal uc_special_cases_t2_ex3 : std_ulogic_vector(8 to 11); +signal uc_special_cases_t3_ex3 : std_ulogic_vector(8 to 11); +signal uc_round_mode_ld : std_ulogic_vector(0 to 7); +signal uc_round_mode_l2 : std_ulogic_vector(0 to 7); +signal uc_round_mode_scin : std_ulogic_vector(0 to 7); +signal uc_round_mode_scout : std_ulogic_vector(0 to 7); +signal uc_mid_rf1 : std_ulogic; +signal uc_end_rf1 : std_ulogic; +signal uc_end_rf1_v : std_ulogic; +signal uc_end_ex1 : std_ulogic; +signal uc_end_ex2 : std_ulogic; +signal uc_end_ex3 : std_ulogic; +signal uc_end_ex4 : std_ulogic; +signal uc_end_ex5 : std_ulogic; +signal uc_end_rf1_l2 : std_ulogic; +signal uc_end_ex1_l2 : std_ulogic; +signal uc_end_ex2_l2 : std_ulogic; +signal uc_end_ex3_l2 : std_ulogic; +signal uc_end_ex4_l2 : std_ulogic; +signal uc_end_ex5_l2 : std_ulogic; +signal uc_end_ex6_l2 : std_ulogic; +signal uc_fa_pos_rf1 : std_ulogic; +signal uc_fc_pos_rf1 : std_ulogic; +signal uc_fb_pos_rf1 : std_ulogic; +signal uc_fc_hulp_rf1 : std_ulogic; +signal uc_fc_0_5_rf1 : std_ulogic; +signal uc_fc_1_0_rf1 : std_ulogic; +signal uc_fc_1_minus_rf1 : std_ulogic; +signal uc_fb_1_0_rf1 : std_ulogic; +signal uc_fb_0_75_rf1 : std_ulogic; +signal uc_fb_0_5_rf1 : std_ulogic; +signal uc_fa_dis_par_rf0, uc_fa_dis_par_rf1 : std_ulogic; +signal uc_fb_dis_par_rf0, uc_fb_dis_par_rf1 : std_ulogic; +signal uc_fc_dis_par_rf0, uc_fc_dis_par_rf1 : std_ulogic; +signal uc_op_rnd_v_rf1_l2 : std_ulogic; +signal uc_op_rnd_rf1_l2 : std_ulogic_vector(0 to 1); + +signal uc_inc_lsb_rf1 : std_ulogic; +signal uc_gs_v_rf1 : std_ulogic; +signal special_rf1 : std_ulogic; +signal spare : std_ulogic; +signal q1r_zero_ex2 : std_ulogic; +signal q1r_sign_ex2 : std_ulogic; +signal q1ulpr_sign_ex2 : std_ulogic; +signal q1ulpr_zero_ex2 : std_ulogic; +signal q1hulpr_sign_ex2 : std_ulogic; +signal uc_gs_ex2 : std_ulogic_vector(0 to 1); +signal uc_round_mode_ex2 : std_ulogic_vector(0 to 1); +signal uc_gs_v_ex1 : std_ulogic; +signal uc_gs_v_ex2 : std_ulogic; +signal uc_inc_lsb_ex1 : std_ulogic; +signal uc_inc_lsb_ex2 : std_ulogic; +signal res_sign_rf1 : std_ulogic; +signal uc_scr_wr_ex4_ld : std_ulogic; +signal rf0_i : std_ulogic_vector(0 to 31); +signal uc_fdiv_beg_rf0 : std_ulogic; +signal uc_fdivs_beg_rf0 : std_ulogic; +signal uc_fsqrt_beg_rf0 : std_ulogic; +signal uc_fsqrts_beg_rf0 : std_ulogic; +signal uc_op_rf0 : std_ulogic_vector(0 to 3); +signal q1_p_ulp_early_ld, q1_p_ulp_early_l2 : std_ulogic_vector(0 to 3); +signal q1_p_ulp_early_scin, q1_p_ulp_early_scout : std_ulogic_vector(0 to 3); + +signal rf1_ucfmul : std_ulogic; + +signal fmulx_uc_rf0, uc_dvsq_beg_rf0 : std_ulogic; +signal uc_abort_rf0 : std_ulogic_vector(0 to 3); +signal rf0_instr_flush : std_ulogic; +signal rf1_instr_flush : std_ulogic; +signal ex1_instr_flush : std_ulogic; +signal ex2_instr_flush : std_ulogic; +signal ex3_instr_flush : std_ulogic; +signal ex3_instr_flush_th : std_ulogic_vector(0 to 3); +signal ex4_instr_flush : std_ulogic; +signal ex5_instr_flush : std_ulogic; + + signal uc_scr_t0_fbk_x , uc_scr_t1_fbk_x , uc_scr_t2_fbk_x , uc_scr_t3_fbk_x :std_ulogic; + signal uc_scr_t0_ld_x , uc_scr_t1_ld_x , uc_scr_t2_ld_x , uc_scr_t3_ld_x :std_ulogic_vector(0 to 11); + + signal uc_scr_t0_ld_x0_b :std_ulogic_vector(0 to 11); + signal uc_scr_t1_ld_x0_b :std_ulogic_vector(0 to 11); + signal uc_scr_t2_ld_x0_b :std_ulogic_vector(0 to 11); + signal uc_scr_t3_ld_x0_b :std_ulogic_vector(0 to 11); + signal uc_scr_t0_ld_x1_b :std_ulogic_vector(0 to 11); + signal uc_scr_t1_ld_x1_b :std_ulogic_vector(0 to 11); + signal uc_scr_t2_ld_x1_b :std_ulogic_vector(0 to 11); + signal uc_scr_t3_ld_x1_b :std_ulogic_vector(0 to 11); + signal uc_scr_t0_ld_x2_b :std_ulogic_vector(0 to 11); + signal uc_scr_t1_ld_x2_b :std_ulogic_vector(0 to 11); + signal uc_scr_t2_ld_x2_b :std_ulogic_vector(0 to 11); + signal uc_scr_t3_ld_x2_b :std_ulogic_vector(0 to 11); + signal uc_scr_t0_ld_x3_b :std_ulogic_vector(0 to 11); + signal uc_scr_t1_ld_x3_b :std_ulogic_vector(0 to 11); + signal uc_scr_t2_ld_x3_b :std_ulogic_vector(0 to 11); + signal uc_scr_t3_ld_x3_b :std_ulogic_vector(0 to 11); + signal uc_scr_t0_ld_x4_b :std_ulogic_vector(0 to 11); + signal uc_scr_t1_ld_x4_b :std_ulogic_vector(0 to 11); + signal uc_scr_t2_ld_x4_b :std_ulogic_vector(0 to 11); + signal uc_scr_t3_ld_x4_b :std_ulogic_vector(0 to 11); + signal uc_scr_t0_ld_xf_b :std_ulogic_vector(0 to 11); + signal uc_scr_t1_ld_xf_b :std_ulogic_vector(0 to 11); + signal uc_scr_t2_ld_xf_b :std_ulogic_vector(0 to 11); + signal uc_scr_t3_ld_xf_b :std_ulogic_vector(0 to 11); + signal uc_scr_t0_oth_b :std_ulogic_vector(0 to 11); + signal uc_scr_t1_oth_b :std_ulogic_vector(0 to 11); + signal uc_scr_t2_oth_b :std_ulogic_vector(0 to 11); + signal uc_scr_t3_oth_b :std_ulogic_vector(0 to 11); + + + + +signal uc_1st_v_th_b :std_ulogic_vector(0 to 3); +signal fdiving_n1st_th :std_ulogic_vector(0 to 3); +signal fdivsing_n1st_th :std_ulogic_vector(0 to 3); +signal fsqrting_n1st_th :std_ulogic_vector(0 to 3); +signal fsqrtsing_n1st_th :std_ulogic_vector(0 to 3); +signal uc_mode_rf0_th :std_ulogic_vector(0 to 3); +signal rf0_n1st_fdiving :std_ulogic; +signal rf0_n1st_fdivsing :std_ulogic; +signal rf0_n1st_fsqrting :std_ulogic; +signal rf0_n1st_fsqrtsing :std_ulogic; +signal rf0_ifar_dcd :std_ulogic_vector(1 to 12); +signal rf0_ifar_89 :std_ulogic; +signal rf0_ifar_45 :std_ulogic; +signal rf0_ifar_34 :std_ulogic; +signal rf0_ifar_78 :std_ulogic; +signal rf0_ifar_bc :std_ulogic; +signal rf0_ifar_67 :std_ulogic; +signal rf0_ifar_ab :std_ulogic; +signal rf0_ifar_ac :std_ulogic; +signal rf0_ifar_57 :std_ulogic; +signal rf0_ifar_9b :std_ulogic; +signal rf0_ifar_68 :std_ulogic; +signal rf0_ifar_abc :std_ulogic; +signal rf0_ifar_567 :std_ulogic; +signal rf0_ifar_9ab :std_ulogic; +signal rf0_ifar_678 :std_ulogic; +signal rf0_ifar_1245abc :std_ulogic; +signal rf0_ifar_13456abc :std_ulogic; +signal rf0_ifar_134567 :std_ulogic; +signal rf0_ifar_123c :std_ulogic; +signal rf0_ifar_12 :std_ulogic; +signal rf0_ifar_13 :std_ulogic; + + signal q1_p_ulp_th :std_ulogic_vector(0 to 3); + signal iu_fu_rf0_ucfmul_b :std_ulogic; +signal rf0_q1_p_ulp_mux0_b, rf0_q1_p_ulp_mux1_b, rf0_q1_p_ulp_mux :std_ulogic; +signal rf0_fra_fast_mux0_b, rf0_fra_fast_mux1_b, rf0_fra_fast_mux :std_ulogic_vector(4 to 4); +signal rf0_fra_fast_b, rf0_fra_fast :std_ulogic_vector(4 to 4); + signal rf0_fra_fast_i_b, rf0_fra_fast_ii :std_ulogic_vector(4 to 4); + +signal rf0_f2_dvsq , rf0_f2_dv , rf0_f2_sq , rf0_f2_mul :std_ulogic ; + + signal spare_unused : std_ulogic_vector(0 to 21); + + + + + + + + +begin + +uc_mid_rf0 <= (uc_scr_t0_l2(7) and thread_id_rf0(0) and ucode_mode_rf0) or + (uc_scr_t1_l2(7) and thread_id_rf0(1) and ucode_mode_rf0) or + (uc_scr_t2_l2(7) and thread_id_rf0(2) and ucode_mode_rf0) or + (uc_scr_t3_l2(7) and thread_id_rf0(3) and ucode_mode_rf0); + + + + + + + + + + + + + + + + + +uc_1st_v_th_b(0) <= not( iu_fu_rf0_instr_v and uc_1st_instr_l2(0) ); +uc_1st_v_th_b(1) <= not( iu_fu_rf0_instr_v and uc_1st_instr_l2(1) ); +uc_1st_v_th_b(2) <= not( iu_fu_rf0_instr_v and uc_1st_instr_l2(2) ); +uc_1st_v_th_b(3) <= not( iu_fu_rf0_instr_v and uc_1st_instr_l2(3) ); + + +fdiving_n1st_th(0) <= uc_scr_t0_l2(8) and uc_1st_v_th_b(0) ; +fdiving_n1st_th(1) <= uc_scr_t1_l2(8) and uc_1st_v_th_b(1) ; +fdiving_n1st_th(2) <= uc_scr_t2_l2(8) and uc_1st_v_th_b(2) ; +fdiving_n1st_th(3) <= uc_scr_t3_l2(8) and uc_1st_v_th_b(3) ; + +fdivsing_n1st_th(0) <= uc_scr_t0_l2(9) and uc_1st_v_th_b(0) ; +fdivsing_n1st_th(1) <= uc_scr_t1_l2(9) and uc_1st_v_th_b(1) ; +fdivsing_n1st_th(2) <= uc_scr_t2_l2(9) and uc_1st_v_th_b(2) ; +fdivsing_n1st_th(3) <= uc_scr_t3_l2(9) and uc_1st_v_th_b(3) ; + +fsqrting_n1st_th(0) <= uc_scr_t0_l2(10) and uc_1st_v_th_b(0) ; +fsqrting_n1st_th(1) <= uc_scr_t1_l2(10) and uc_1st_v_th_b(1) ; +fsqrting_n1st_th(2) <= uc_scr_t2_l2(10) and uc_1st_v_th_b(2) ; +fsqrting_n1st_th(3) <= uc_scr_t3_l2(10) and uc_1st_v_th_b(3) ; + +fsqrtsing_n1st_th(0) <= uc_scr_t0_l2(11) and uc_1st_v_th_b(0) ; +fsqrtsing_n1st_th(1) <= uc_scr_t1_l2(11) and uc_1st_v_th_b(1) ; +fsqrtsing_n1st_th(2) <= uc_scr_t2_l2(11) and uc_1st_v_th_b(2) ; +fsqrtsing_n1st_th(3) <= uc_scr_t3_l2(11) and uc_1st_v_th_b(3) ; + +uc_mode_rf0_th(0 to 3) <= thread_id_rf0(0 to 3) and (0 to 3=> ucode_mode_rf0 ); + + +rf0_n1st_fdiving <= (uc_mode_rf0_th(0) and fdiving_n1st_th(0) ) or + (uc_mode_rf0_th(1) and fdiving_n1st_th(1) ) or + (uc_mode_rf0_th(2) and fdiving_n1st_th(2) ) or + (uc_mode_rf0_th(3) and fdiving_n1st_th(3) ) ; + +rf0_n1st_fdivsing <= (uc_mode_rf0_th(0) and fdivsing_n1st_th(0) ) or + (uc_mode_rf0_th(1) and fdivsing_n1st_th(1) ) or + (uc_mode_rf0_th(2) and fdivsing_n1st_th(2) ) or + (uc_mode_rf0_th(3) and fdivsing_n1st_th(3) ) ; + +rf0_n1st_fsqrting <= (uc_mode_rf0_th(0) and fsqrting_n1st_th(0) ) or + (uc_mode_rf0_th(1) and fsqrting_n1st_th(1) ) or + (uc_mode_rf0_th(2) and fsqrting_n1st_th(2) ) or + (uc_mode_rf0_th(3) and fsqrting_n1st_th(3) ) ; + +rf0_n1st_fsqrtsing <= (uc_mode_rf0_th(0) and fsqrtsing_n1st_th(0) ) or + (uc_mode_rf0_th(1) and fsqrtsing_n1st_th(1) ) or + (uc_mode_rf0_th(2) and fsqrtsing_n1st_th(2) ) or + (uc_mode_rf0_th(3) and fsqrtsing_n1st_th(3) ) ; + + + + rf0_ifar_dcd(1) <= not iu_fu_rf0_ifar(58) and not iu_fu_rf0_ifar(59) and not iu_fu_rf0_ifar(60) and iu_fu_rf0_ifar(61) ; + rf0_ifar_dcd(2) <= not iu_fu_rf0_ifar(58) and not iu_fu_rf0_ifar(59) and iu_fu_rf0_ifar(60) and not iu_fu_rf0_ifar(61) ; + rf0_ifar_dcd(3) <= not iu_fu_rf0_ifar(58) and not iu_fu_rf0_ifar(59) and iu_fu_rf0_ifar(60) and iu_fu_rf0_ifar(61) ; + rf0_ifar_dcd(4) <= not iu_fu_rf0_ifar(58) and iu_fu_rf0_ifar(59) and not iu_fu_rf0_ifar(60) and not iu_fu_rf0_ifar(61) ; + rf0_ifar_dcd(5) <= not iu_fu_rf0_ifar(58) and iu_fu_rf0_ifar(59) and not iu_fu_rf0_ifar(60) and iu_fu_rf0_ifar(61) ; + rf0_ifar_dcd(6) <= not iu_fu_rf0_ifar(58) and iu_fu_rf0_ifar(59) and iu_fu_rf0_ifar(60) and not iu_fu_rf0_ifar(61) ; + rf0_ifar_dcd(7) <= not iu_fu_rf0_ifar(58) and iu_fu_rf0_ifar(59) and iu_fu_rf0_ifar(60) and iu_fu_rf0_ifar(61) ; + rf0_ifar_dcd(8) <= iu_fu_rf0_ifar(58) and not iu_fu_rf0_ifar(59) and not iu_fu_rf0_ifar(60) and not iu_fu_rf0_ifar(61) ; + rf0_ifar_dcd(9) <= iu_fu_rf0_ifar(58) and not iu_fu_rf0_ifar(59) and not iu_fu_rf0_ifar(60) and iu_fu_rf0_ifar(61) ; + rf0_ifar_dcd(10) <= iu_fu_rf0_ifar(58) and not iu_fu_rf0_ifar(59) and iu_fu_rf0_ifar(60) and not iu_fu_rf0_ifar(61) ; + rf0_ifar_dcd(11) <= iu_fu_rf0_ifar(58) and not iu_fu_rf0_ifar(59) and iu_fu_rf0_ifar(60) and iu_fu_rf0_ifar(61) ; + rf0_ifar_dcd(12) <= iu_fu_rf0_ifar(58) and iu_fu_rf0_ifar(59) and not iu_fu_rf0_ifar(60) and not iu_fu_rf0_ifar(61) ; + + rf0_ifar_89 <= rf0_ifar_dcd(8) or rf0_ifar_dcd(9) ; + rf0_ifar_45 <= rf0_ifar_dcd(4) or rf0_ifar_dcd(5) ; + rf0_ifar_34 <= rf0_ifar_dcd(3) or rf0_ifar_dcd(4) ; + rf0_ifar_78 <= rf0_ifar_dcd(7) or rf0_ifar_dcd(8) ; + rf0_ifar_bc <= rf0_ifar_dcd(11) or rf0_ifar_dcd(12) ; + rf0_ifar_67 <= rf0_ifar_dcd(6) or rf0_ifar_dcd(7) ; + rf0_ifar_ab <= rf0_ifar_dcd(10) or rf0_ifar_dcd(11) ; + rf0_ifar_ac <= rf0_ifar_dcd(10) or rf0_ifar_dcd(12) ; + rf0_ifar_57 <= rf0_ifar_dcd(5) or rf0_ifar_dcd(7) ; + rf0_ifar_9b <= rf0_ifar_dcd(9) or rf0_ifar_dcd(11) ; + rf0_ifar_68 <= rf0_ifar_dcd(6) or rf0_ifar_dcd(8) ; + rf0_ifar_abc <= rf0_ifar_dcd(10) or rf0_ifar_dcd(11) or rf0_ifar_dcd(12) ; + rf0_ifar_567 <= rf0_ifar_dcd(5) or rf0_ifar_dcd(6) or rf0_ifar_dcd(7) ; + rf0_ifar_9ab <= rf0_ifar_dcd(9) or rf0_ifar_dcd(10) or rf0_ifar_dcd(11) ; + rf0_ifar_678 <= rf0_ifar_dcd(6) or rf0_ifar_dcd(7) or rf0_ifar_dcd(8) ; + rf0_ifar_1245abc <= rf0_ifar_dcd(1) or rf0_ifar_dcd(2) or rf0_ifar_dcd(4) or rf0_ifar_dcd(5) or rf0_ifar_dcd(10) or rf0_ifar_dcd(11) or rf0_ifar_dcd(12); + rf0_ifar_13456abc <= rf0_ifar_dcd(1) or rf0_ifar_dcd(3) or rf0_ifar_dcd(4) or rf0_ifar_dcd(5) or rf0_ifar_dcd(6) or rf0_ifar_dcd(10) or rf0_ifar_dcd(11) or rf0_ifar_dcd(12); + rf0_ifar_134567 <= rf0_ifar_dcd(1) or rf0_ifar_dcd(3) or rf0_ifar_dcd(4) or rf0_ifar_dcd(5) or rf0_ifar_dcd(6) or rf0_ifar_dcd(7); + rf0_ifar_123c <= rf0_ifar_dcd(1) or rf0_ifar_dcd(2) or rf0_ifar_dcd(12) ; + rf0_ifar_12 <= rf0_ifar_dcd(1) or rf0_ifar_dcd(2) ; + rf0_ifar_13 <= rf0_ifar_dcd(1) or rf0_ifar_dcd(3) ; + + + uc_op_rnd_v <= + (rf0_n1st_fdiving and tiup ) or + (rf0_n1st_fdivsing and tiup ) or + (rf0_n1st_fsqrting and tiup ) or + (rf0_n1st_fsqrtsing and tiup ) ; + + uc_op_rnd(0) <= '0'; + + uc_op_rnd(1) <= + (rf0_n1st_fdiving and rf0_ifar_89 ) or + (rf0_n1st_fdivsing and rf0_ifar_34 ) or + (rf0_n1st_fsqrting and rf0_ifar_78 ) or + (rf0_n1st_fsqrtsing and rf0_ifar_45 ) ; + + uc_inc_lsb <= + (rf0_n1st_fdiving and rf0_ifar_dcd(9) ) or + (rf0_n1st_fdivsing and rf0_ifar_dcd(4) ) or + (rf0_n1st_fsqrting and rf0_ifar_dcd(8) ) or + (rf0_n1st_fsqrtsing and rf0_ifar_dcd(5) ) ; + + uc_scr_sel(0) <= + (rf0_n1st_fdiving and rf0_ifar_bc ) or + (rf0_n1st_fdivsing and rf0_ifar_67 ) or + (rf0_n1st_fsqrting and rf0_ifar_ab ) or + (rf0_n1st_fsqrtsing and rf0_ifar_78 ) ; + + uc_scr_sel(1) <= + (rf0_n1st_fdiving and rf0_ifar_ac ) or + (rf0_n1st_fdivsing and rf0_ifar_57 ) or + (rf0_n1st_fsqrting and rf0_ifar_9b ) or + (rf0_n1st_fsqrtsing and rf0_ifar_68 ) ; + + uc_scr_wr <= + (rf0_n1st_fdiving and rf0_ifar_abc ) or + (rf0_n1st_fdivsing and rf0_ifar_567 ) or + (rf0_n1st_fsqrting and rf0_ifar_9ab ) or + (rf0_n1st_fsqrtsing and rf0_ifar_678 ) ; + + uc_fa_dis_par_rf0 <= + (rf0_n1st_fdiving and rf0_ifar_1245abc ) or + (rf0_n1st_fdivsing and tiup ) or + (rf0_n1st_fsqrting and tidn ) or + (rf0_n1st_fsqrtsing and tidn ) ; + + uc_fb_dis_par_rf0 <= + (rf0_n1st_fdiving and rf0_ifar_13456abc ) or + (rf0_n1st_fdivsing and rf0_ifar_134567 ) or + (rf0_n1st_fsqrting and rf0_ifar_dcd(3) ) or + (rf0_n1st_fsqrtsing and tidn ) ; + + uc_fc_dis_par_rf0 <= + (rf0_n1st_fdiving and rf0_ifar_123c ) or + (rf0_n1st_fdivsing and rf0_ifar_12 ) or + (rf0_n1st_fsqrting and rf0_ifar_13 ) or + (rf0_n1st_fsqrtsing and rf0_ifar_dcd(1) ) ; + + uc_fa_pos <= + (rf0_n1st_fdiving and rf0_ifar_1245abc ) or + (rf0_n1st_fdivsing and tiup ) or + (rf0_n1st_fsqrting and tidn ) or + (rf0_n1st_fsqrtsing and tidn ) ; + + uc_fc_pos <= + (rf0_n1st_fdiving and rf0_ifar_12 ) or + (rf0_n1st_fdivsing and rf0_ifar_12 ) or + (rf0_n1st_fsqrting and rf0_ifar_dcd(1) ) or + (rf0_n1st_fsqrtsing and rf0_ifar_dcd(1) ) ; + + uc_fb_pos <= + (rf0_n1st_fdiving and rf0_ifar_13456abc) or + (rf0_n1st_fdivsing and rf0_ifar_134567 ) or + (rf0_n1st_fsqrting and rf0_ifar_dcd(3) ) or + (rf0_n1st_fsqrtsing and tidn ) ; + + uc_fc_0_5 <= + (rf0_n1st_fdiving and tidn ) or + (rf0_n1st_fdivsing and tidn ) or + (rf0_n1st_fsqrting and rf0_ifar_dcd(1) ) or + (rf0_n1st_fsqrtsing and rf0_ifar_dcd(1) ) ; + + uc_fc_hulp <= + (rf0_n1st_fdiving and rf0_ifar_dcd(12) ) or + (rf0_n1st_fdivsing and rf0_ifar_dcd(7) ) or + (rf0_n1st_fsqrting and tidn ) or + (rf0_n1st_fsqrtsing and tidn ) ; + + uc_fb_1_0 <= + (rf0_n1st_fdiving and rf0_ifar_dcd(1) ) or + (rf0_n1st_fdivsing and rf0_ifar_dcd(1) ) or + (rf0_n1st_fsqrting and tidn ) or + (rf0_n1st_fsqrtsing and tidn ) ; + + uc_fb_0_75 <= + (rf0_n1st_fdiving and rf0_ifar_dcd(6) ) or + (rf0_n1st_fdivsing and tidn ) or + (rf0_n1st_fsqrting and tidn ) or + (rf0_n1st_fsqrtsing and tidn ) ; + + uc_fb_0_5 <= + (rf0_n1st_fdiving and rf0_ifar_dcd(3) ) or + (rf0_n1st_fdivsing and tidn ) or + (rf0_n1st_fsqrting and rf0_ifar_dcd(3) ) or + (rf0_n1st_fsqrtsing and tidn ) ; + + + + + + + + + + + + + + +uc_1st_instr_ld(0) <= uc_beg_rf0 when iu_fu_rf0_instr_v='1' and uc_scr_thread_rf0 = "00" else + uc_1st_instr_l2(0); + +uc_1st_instr_ld(1) <= uc_beg_rf0 when iu_fu_rf0_instr_v='1' and uc_scr_thread_rf0 = "01" else + uc_1st_instr_l2(1); + +uc_1st_instr_ld(2) <= uc_beg_rf0 when iu_fu_rf0_instr_v='1' and uc_scr_thread_rf0 = "10" else + uc_1st_instr_l2(2); + +uc_1st_instr_ld(3) <= uc_beg_rf0 when iu_fu_rf0_instr_v='1' and uc_scr_thread_rf0 = "11" else + uc_1st_instr_l2(3); + + + + + + + uc_1st_instr_reg: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 4) + port map ( + nclk => nclk, act => msr_fp_act, + vd => vdd, gd => gnd, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + thold_b => thold_0_b, sg => sg_0, + scin => uc_1st_instr_scin, + scout => uc_1st_instr_scout, + din(0 to 3) => uc_1st_instr_ld, + + dout(0 to 3) => uc_1st_instr_l2 + + ); + + + + + +uc_abort_rf0(0) <= uc_1st_instr_l2(0) and not((iu_fu_rf0_instr(26 to 28) = "110") and iu_fu_rf0_instr(30) = '0'); +uc_abort_rf0(1) <= uc_1st_instr_l2(1) and not((iu_fu_rf0_instr(26 to 28) = "110") and iu_fu_rf0_instr(30) = '0'); +uc_abort_rf0(2) <= uc_1st_instr_l2(2) and not((iu_fu_rf0_instr(26 to 28) = "110") and iu_fu_rf0_instr(30) = '0'); +uc_abort_rf0(3) <= uc_1st_instr_l2(3) and not((iu_fu_rf0_instr(26 to 28) = "110") and iu_fu_rf0_instr(30) = '0'); + + + + + + + + + + + + + + + + +uc_normal_end_rf0_part <= ((not uc_scr_t0_l2(0) and thread_id_rf0(0)) or + (not uc_scr_t1_l2(0) and thread_id_rf0(1)) or + (not uc_scr_t2_l2(0) and thread_id_rf0(2)) or + (not uc_scr_t3_l2(0) and thread_id_rf0(3))); + +uc_normal_end_rf0 <= uc_end_rf0_v and uc_normal_end_rf0_part; + + + +uc_gs_v_rf0 <= uc_normal_end_rf0; + + + + + + +uc_round_mode_ld(0 to 1) <= f_mad_ex3_uc_round_mode when uc_scr_wr_ex3 = '1' and uc_scr_sel_ex3 = "00" and uc_scr_thread_ex3 = "00" else + uc_round_mode_l2(0 to 1); + +uc_round_mode_ld(2 to 3) <= f_mad_ex3_uc_round_mode when uc_scr_wr_ex3 = '1' and uc_scr_sel_ex3 = "00" and uc_scr_thread_ex3 = "01" else + uc_round_mode_l2(2 to 3); + +uc_round_mode_ld(4 to 5) <= f_mad_ex3_uc_round_mode when uc_scr_wr_ex3 = '1' and uc_scr_sel_ex3 = "00" and uc_scr_thread_ex3 = "10" else + uc_round_mode_l2(4 to 5); + +uc_round_mode_ld(6 to 7) <= f_mad_ex3_uc_round_mode when uc_scr_wr_ex3 = '1' and uc_scr_sel_ex3 = "00" and uc_scr_thread_ex3 = "11" else + uc_round_mode_l2(6 to 7); + + uc_round_mode_reg: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 8) + port map ( + nclk => nclk, act => msr_fp_act, + vd => vdd, gd => gnd, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + thold_b => thold_0_b, sg => sg_0, + scin => uc_round_mode_scin, + scout => uc_round_mode_scout, + din(0 to 7) => uc_round_mode_ld, + + dout(0 to 7) => uc_round_mode_l2 + + ); + + + +uc_special_cases_ex3(0) <= f_mad_ex3_uc_special; +uc_special_cases_ex3(1) <= f_mad_ex3_uc_res_sign; +uc_special_cases_ex3(2 to 7) <= f_mad_ex3_uc_vxsnan & f_mad_ex3_uc_zx & f_mad_ex3_uc_vxidi & f_mad_ex3_uc_vxzdz & f_mad_ex3_uc_vxsqrt & '1'; + +uc_special_cases_t0_ex3(8 to 11) <= "0000" when f_mad_ex3_uc_special='1' else + uc_scr_t0_l2(8 to 11); +uc_special_cases_t1_ex3(8 to 11) <= "0000" when f_mad_ex3_uc_special='1' else + uc_scr_t1_l2(8 to 11); +uc_special_cases_t2_ex3(8 to 11) <= "0000" when f_mad_ex3_uc_special='1' else + uc_scr_t2_l2(8 to 11); +uc_special_cases_t3_ex3(8 to 11) <= "0000" when f_mad_ex3_uc_special='1' else + uc_scr_t3_l2(8 to 11); + + + + + + + + + + + + +uc_hooks_rc_rf0 <= '0' when uc_beg_rf0_v ='1' and perr_sm_running='0' else + iu_fu_rf0_instr(31); + + + +q1_p_ulp_th(0) <= q1_p_ulp_early_l2(0) and not uc_scr_t0_l2(0) ; +q1_p_ulp_th(1) <= q1_p_ulp_early_l2(1) and not uc_scr_t1_l2(0) ; +q1_p_ulp_th(2) <= q1_p_ulp_early_l2(2) and not uc_scr_t2_l2(0) ; +q1_p_ulp_th(3) <= q1_p_ulp_early_l2(3) and not uc_scr_t3_l2(0) ; + +iu_fu_rf0_ucfmul_b <= not iu_fu_rf0_ucfmul ; + + + +u_q1pm0: rf0_q1_p_ulp_mux0_b <= not( (thread_id_rf0(0) and q1_p_ulp_th(0)) or (thread_id_rf0(1) and q1_p_ulp_th(1)) ); +u_q1pm1: rf0_q1_p_ulp_mux1_b <= not( (thread_id_rf0(2) and q1_p_ulp_th(2)) or (thread_id_rf0(3) and q1_p_ulp_th(3)) ); + +u_q1pm: rf0_q1_p_ulp_mux <= not( rf0_q1_p_ulp_mux0_b and rf0_q1_p_ulp_mux1_b ) ; + +u_afm0: rf0_fra_fast_mux0_b(4) <= not( rf0_q1_p_ulp_mux and iu_fu_rf0_ucfmul ); +u_afm1: rf0_fra_fast_mux1_b(4) <= not( rf0_instr_fra(4) and iu_fu_rf0_ucfmul_b ); + +u_afm: rf0_fra_fast_mux(4) <= not( rf0_fra_fast_mux0_b(4) and rf0_fra_fast_mux1_b(4) ); + +u_afb: rf0_fra_fast_b(4) <= not( rf0_fra_fast_mux(4) ); +u_af: rf0_fra_fast(4) <= not( rf0_fra_fast_b(4) ); +u_afi: rf0_fra_fast_i_b(4) <= not rf0_fra_fast(4) ; +u_afii: rf0_fra_fast_ii(4) <= not rf0_fra_fast_i_b(4); + + + + f_dcd_rf0_fra(0) <= rf0_instr_fra(0) ; + f_dcd_rf0_fra(1) <= rf0_instr_fra(1) ; + f_dcd_rf0_fra(2) <= rf0_instr_fra(2) ; + f_dcd_rf0_fra(3) <= rf0_instr_fra(3) ; + f_dcd_rf0_fra(4) <= rf0_fra_fast_ii(4); + f_dcd_rf0_fra(5) <= rf0_instr_fra(5) ; + + + + + + + + + + +rf0_i(0 to 31) <= iu_fu_rf0_instr(0 to 31); + +fp_operation_rf0 <= rf0_i(0) and rf0_i(1) and rf0_i(2) and rf0_i(4) and rf0_i(5) ; + +rf0_f2_dvsq <= rf0_i(26) and not rf0_i(27) and rf0_i(29) and not rf0_i(30) ; +rf0_f2_dv <= rf0_i(26) and not rf0_i(27) and not rf0_i(28) and rf0_i(29) and not rf0_i(30) ; +rf0_f2_sq <= rf0_i(26) and not rf0_i(27) and rf0_i(28) and rf0_i(29) and not rf0_i(30) ; +rf0_f2_mul <= rf0_i(26) and not rf0_i(27) and not rf0_i(28) and not rf0_i(29) and rf0_i(30) ; + + + +uc_div_beg_rf0 <= fp_operation_rf0 and rf0_f2_dv and iu_fu_rf0_instr_v ; +uc_sqrt_beg_rf0 <= fp_operation_rf0 and rf0_f2_sq and iu_fu_rf0_instr_v ; +uc_fdiv_beg_rf0 <= fp_operation_rf0 and rf0_i(3) and rf0_f2_dv ; +uc_fdivs_beg_rf0 <= fp_operation_rf0 and not rf0_i(3) and rf0_f2_dv ; +uc_fsqrt_beg_rf0 <= fp_operation_rf0 and rf0_i(3) and rf0_f2_sq ; +uc_fsqrts_beg_rf0 <= fp_operation_rf0 and not rf0_i(3) and rf0_f2_sq ; +uc_dvsq_beg_rf0 <= fp_operation_rf0 and rf0_f2_dvsq ; +fmulx_uc_rf0 <= fp_operation_rf0 and rf0_f2_mul ; + + + +uc_beg_rf0 <= uc_dvsq_beg_rf0 ; +uc_beg_rf0_v <= uc_dvsq_beg_rf0 and iu_fu_rf0_instr_v ; +uc_end_rf0 <= fmulx_uc_rf0 ; +uc_end_rf0_v <= fmulx_uc_rf0 and iu_fu_rf0_instr_v ; +uc_end_rf0_vf <= fmulx_uc_rf0 and iu_fu_rf0_instr_v and not rf0_instr_flush ; + + +uc_op_rf0(0) <= uc_fdiv_beg_rf0 ; +uc_op_rf0(1) <= uc_fdivs_beg_rf0 ; +uc_op_rf0(2) <= uc_fsqrt_beg_rf0 ; +uc_op_rf0(3) <= uc_fsqrts_beg_rf0; + + + + uc_sign_zero_t0(0 to 11) <= uc_scr_t0_l2(0 to 1) & f_mad_ex6_uc_sign & f_mad_ex6_uc_zero & uc_scr_t0_l2(4 to 11) when uc_scr_sel_ex6 = "01" else + uc_scr_t0_l2(0 to 3) & f_mad_ex6_uc_sign & f_mad_ex6_uc_zero & uc_scr_t0_l2(6 to 11) when uc_scr_sel_ex6 = "10" else + uc_scr_t0_l2(0 to 5) & f_mad_ex6_uc_sign & "00000"; + + uc_sign_zero_t1(0 to 11) <= uc_scr_t1_l2(0 to 1) & f_mad_ex6_uc_sign & f_mad_ex6_uc_zero & uc_scr_t1_l2(4 to 11) when uc_scr_sel_ex6 = "01" else + uc_scr_t1_l2(0 to 3) & f_mad_ex6_uc_sign & f_mad_ex6_uc_zero & uc_scr_t1_l2(6 to 11) when uc_scr_sel_ex6 = "10" else + uc_scr_t1_l2(0 to 5) & f_mad_ex6_uc_sign & "00000"; + + uc_sign_zero_t2(0 to 11) <= uc_scr_t2_l2(0 to 1) & f_mad_ex6_uc_sign & f_mad_ex6_uc_zero & uc_scr_t2_l2(4 to 11) when uc_scr_sel_ex6 = "01" else + uc_scr_t2_l2(0 to 3) & f_mad_ex6_uc_sign & f_mad_ex6_uc_zero & uc_scr_t2_l2(6 to 11) when uc_scr_sel_ex6 = "10" else + uc_scr_t2_l2(0 to 5) & f_mad_ex6_uc_sign & "00000"; + + uc_sign_zero_t3(0 to 11) <= uc_scr_t3_l2(0 to 1) & f_mad_ex6_uc_sign & f_mad_ex6_uc_zero & uc_scr_t3_l2(4 to 11) when uc_scr_sel_ex6 = "01" else + uc_scr_t3_l2(0 to 3) & f_mad_ex6_uc_sign & f_mad_ex6_uc_zero & uc_scr_t3_l2(6 to 11) when uc_scr_sel_ex6 = "10" else + uc_scr_t3_l2(0 to 5) & f_mad_ex6_uc_sign & "00000"; + + + + + + uc_scr_t0_upd(0) <= uc_1st_instr_l2(0) = '1' and uc_scr_t0_l2(7) = '0' and uc_scr_thread_rf1 = "00" ; + uc_scr_t1_upd(0) <= uc_1st_instr_l2(1) = '1' and uc_scr_t1_l2(7) = '0' and uc_scr_thread_rf1 = "01" ; + uc_scr_t2_upd(0) <= uc_1st_instr_l2(2) = '1' and uc_scr_t2_l2(7) = '0' and uc_scr_thread_rf1 = "10" ; + uc_scr_t3_upd(0) <= uc_1st_instr_l2(3) = '1' and uc_scr_t3_l2(7) = '0' and uc_scr_thread_rf1 = "11" ; + + uc_scr_t0_upd(1) <= uc_end_ex6_l2 and uc_scr_thread_ex6 = "00" ; + uc_scr_t1_upd(1) <= uc_end_ex6_l2 and uc_scr_thread_ex6 = "01" ; + uc_scr_t2_upd(1) <= uc_end_ex6_l2 and uc_scr_thread_ex6 = "10" ; + uc_scr_t3_upd(1) <= uc_end_ex6_l2 and uc_scr_thread_ex6 = "11" ; + + uc_scr_t0_upd(2) <= ((not ucode_mode_rf0 and not uc_end_rf0) or uc_abort_rf0(0) ) and iu_fu_rf0_instr_v and thread_id_rf0(0) ; + uc_scr_t1_upd(2) <= ((not ucode_mode_rf0 and not uc_end_rf0) or uc_abort_rf0(1) ) and iu_fu_rf0_instr_v and thread_id_rf0(1) ; + uc_scr_t2_upd(2) <= ((not ucode_mode_rf0 and not uc_end_rf0) or uc_abort_rf0(2) ) and iu_fu_rf0_instr_v and thread_id_rf0(2) ; + uc_scr_t3_upd(2) <= ((not ucode_mode_rf0 and not uc_end_rf0) or uc_abort_rf0(3) ) and iu_fu_rf0_instr_v and thread_id_rf0(3) ; + + uc_scr_t0_upd(3) <= uc_scr_wr_ex3_l2 and uc_scr_sel_ex3 = "00" and uc_scr_t0_l2(7) = '1' and uc_scr_thread_ex3 = "00" ; + uc_scr_t1_upd(3) <= uc_scr_wr_ex3_l2 and uc_scr_sel_ex3 = "00" and uc_scr_t1_l2(7) = '1' and uc_scr_thread_ex3 = "01" ; + uc_scr_t2_upd(3) <= uc_scr_wr_ex3_l2 and uc_scr_sel_ex3 = "00" and uc_scr_t2_l2(7) = '1' and uc_scr_thread_ex3 = "10" ; + uc_scr_t3_upd(3) <= uc_scr_wr_ex3_l2 and uc_scr_sel_ex3 = "00" and uc_scr_t3_l2(7) = '1' and uc_scr_thread_ex3 = "11" ; + + uc_scr_t0_upd(4) <= uc_scr_wr_ex6 = '1' and uc_scr_t0_l2(0) = '0' and uc_scr_t0_l2(7) = '1' and uc_scr_thread_ex6 = "00" ; + uc_scr_t1_upd(4) <= uc_scr_wr_ex6 = '1' and uc_scr_t1_l2(0) = '0' and uc_scr_t1_l2(7) = '1' and uc_scr_thread_ex6 = "01" ; + uc_scr_t2_upd(4) <= uc_scr_wr_ex6 = '1' and uc_scr_t2_l2(0) = '0' and uc_scr_t2_l2(7) = '1' and uc_scr_thread_ex6 = "10" ; + uc_scr_t3_upd(4) <= uc_scr_wr_ex6 = '1' and uc_scr_t3_l2(0) = '0' and uc_scr_t3_l2(7) = '1' and uc_scr_thread_ex6 = "11" ; + + + uc_scr_t0_fbk_x <= not( uc_scr_t0_upd(0) or uc_scr_t0_upd(1) or uc_scr_t0_upd(3) or uc_scr_t0_upd(4) ); + uc_scr_t1_fbk_x <= not( uc_scr_t1_upd(0) or uc_scr_t1_upd(1) or uc_scr_t1_upd(3) or uc_scr_t1_upd(4) ); + uc_scr_t2_fbk_x <= not( uc_scr_t2_upd(0) or uc_scr_t2_upd(1) or uc_scr_t2_upd(3) or uc_scr_t2_upd(4) ); + uc_scr_t3_fbk_x <= not( uc_scr_t3_upd(0) or uc_scr_t3_upd(1) or uc_scr_t3_upd(3) or uc_scr_t3_upd(4) ); + + + uc_scr_t0_ld_x(0 to 11) <= not( uc_scr_t0_ld_x0_b(0 to 11) and uc_scr_t0_ld_x1_b(0 to 11) and uc_scr_t0_ld_x3_b(0 to 11) and uc_scr_t0_ld_x4_b(0 to 11) and uc_scr_t0_ld_xf_b(0 to 11) ); + uc_scr_t1_ld_x(0 to 11) <= not( uc_scr_t1_ld_x0_b(0 to 11) and uc_scr_t1_ld_x1_b(0 to 11) and uc_scr_t1_ld_x3_b(0 to 11) and uc_scr_t1_ld_x4_b(0 to 11) and uc_scr_t1_ld_xf_b(0 to 11) ); + uc_scr_t2_ld_x(0 to 11) <= not( uc_scr_t2_ld_x0_b(0 to 11) and uc_scr_t2_ld_x1_b(0 to 11) and uc_scr_t2_ld_x3_b(0 to 11) and uc_scr_t2_ld_x4_b(0 to 11) and uc_scr_t2_ld_xf_b(0 to 11) ); + uc_scr_t3_ld_x(0 to 11) <= not( uc_scr_t3_ld_x0_b(0 to 11) and uc_scr_t3_ld_x1_b(0 to 11) and uc_scr_t3_ld_x3_b(0 to 11) and uc_scr_t3_ld_x4_b(0 to 11) and uc_scr_t3_ld_xf_b(0 to 11) ); + + + uc_scr_t0_ld_x0_b(0 to 11) <= not("00000001" & uc_scr_t0_l2(8 to 11) and (0 to 11 => uc_scr_t0_upd(0))) ; + uc_scr_t1_ld_x0_b(0 to 11) <= not("00000001" & uc_scr_t1_l2(8 to 11) and (0 to 11 => uc_scr_t1_upd(0))) ; + uc_scr_t2_ld_x0_b(0 to 11) <= not("00000001" & uc_scr_t2_l2(8 to 11) and (0 to 11 => uc_scr_t2_upd(0))) ; + uc_scr_t3_ld_x0_b(0 to 11) <= not("00000001" & uc_scr_t3_l2(8 to 11) and (0 to 11 => uc_scr_t3_upd(0))) ; + + uc_scr_t0_ld_x1_b(0 to 11) <= not("000000000000" and (0 to 11 => uc_scr_t0_upd(1))) ; + uc_scr_t1_ld_x1_b(0 to 11) <= not("000000000000" and (0 to 11 => uc_scr_t1_upd(1))) ; + uc_scr_t2_ld_x1_b(0 to 11) <= not("000000000000" and (0 to 11 => uc_scr_t2_upd(1))) ; + uc_scr_t3_ld_x1_b(0 to 11) <= not("000000000000" and (0 to 11 => uc_scr_t3_upd(1))) ; + + uc_scr_t0_ld_x2_b(0 to 11) <= not("00000000" & uc_op_rf0(0 to 3) and (0 to 11 => uc_scr_t0_upd(2))) ; + uc_scr_t1_ld_x2_b(0 to 11) <= not("00000000" & uc_op_rf0(0 to 3) and (0 to 11 => uc_scr_t1_upd(2))) ; + uc_scr_t2_ld_x2_b(0 to 11) <= not("00000000" & uc_op_rf0(0 to 3) and (0 to 11 => uc_scr_t2_upd(2))) ; + uc_scr_t3_ld_x2_b(0 to 11) <= not("00000000" & uc_op_rf0(0 to 3) and (0 to 11 => uc_scr_t3_upd(2))) ; + + uc_scr_t0_ld_x3_b(0 to 11) <= not(uc_special_cases_ex3(0 to 7) & uc_special_cases_t0_ex3(8 to 11) and (0 to 11 => uc_scr_t0_upd(3))) ; + uc_scr_t1_ld_x3_b(0 to 11) <= not(uc_special_cases_ex3(0 to 7) & uc_special_cases_t1_ex3(8 to 11) and (0 to 11 => uc_scr_t1_upd(3))) ; + uc_scr_t2_ld_x3_b(0 to 11) <= not(uc_special_cases_ex3(0 to 7) & uc_special_cases_t2_ex3(8 to 11) and (0 to 11 => uc_scr_t2_upd(3))) ; + uc_scr_t3_ld_x3_b(0 to 11) <= not(uc_special_cases_ex3(0 to 7) & uc_special_cases_t3_ex3(8 to 11) and (0 to 11 => uc_scr_t3_upd(3))) ; + + uc_scr_t0_ld_x4_b(0 to 11) <= not(uc_sign_zero_t0(0 to 11) and (0 to 11 => uc_scr_t0_upd(4))) ; + uc_scr_t1_ld_x4_b(0 to 11) <= not(uc_sign_zero_t1(0 to 11) and (0 to 11 => uc_scr_t1_upd(4))) ; + uc_scr_t2_ld_x4_b(0 to 11) <= not(uc_sign_zero_t2(0 to 11) and (0 to 11 => uc_scr_t2_upd(4))) ; + uc_scr_t3_ld_x4_b(0 to 11) <= not(uc_sign_zero_t3(0 to 11) and (0 to 11 => uc_scr_t3_upd(4))) ; + + uc_scr_t0_ld_xf_b(0 to 11) <= not(uc_scr_t0_l2(0 to 11) and (0 to 11 => uc_scr_t0_fbk_x )) ; + uc_scr_t1_ld_xf_b(0 to 11) <= not(uc_scr_t1_l2(0 to 11) and (0 to 11 => uc_scr_t1_fbk_x )) ; + uc_scr_t2_ld_xf_b(0 to 11) <= not(uc_scr_t2_l2(0 to 11) and (0 to 11 => uc_scr_t2_fbk_x )) ; + uc_scr_t3_ld_xf_b(0 to 11) <= not(uc_scr_t3_l2(0 to 11) and (0 to 11 => uc_scr_t3_fbk_x )) ; + + uc_scr_t0_oth_b(0 to 11) <= not( (0 to 11 => not uc_scr_t0_upd(2) ) and uc_scr_t0_ld_x(0 to 11) ); + uc_scr_t1_oth_b(0 to 11) <= not( (0 to 11 => not uc_scr_t1_upd(2) ) and uc_scr_t1_ld_x(0 to 11) ); + uc_scr_t2_oth_b(0 to 11) <= not( (0 to 11 => not uc_scr_t2_upd(2) ) and uc_scr_t2_ld_x(0 to 11) ); + uc_scr_t3_oth_b(0 to 11) <= not( (0 to 11 => not uc_scr_t3_upd(2) ) and uc_scr_t3_ld_x(0 to 11) ); + + uc_scr_t0_ld(0 to 11) <= not( uc_scr_t0_ld_x2_b(0 to 11) and uc_scr_t0_oth_b(0 to 11) ); + uc_scr_t1_ld(0 to 11) <= not( uc_scr_t1_ld_x2_b(0 to 11) and uc_scr_t1_oth_b(0 to 11) ); + uc_scr_t2_ld(0 to 11) <= not( uc_scr_t2_ld_x2_b(0 to 11) and uc_scr_t2_oth_b(0 to 11) ); + uc_scr_t3_ld(0 to 11) <= not( uc_scr_t3_ld_x2_b(0 to 11) and uc_scr_t3_oth_b(0 to 11) ); + + + + + + uc_scr_t0_is2: tri_rlmreg_p generic map (init => 0, expand_type => expand_type, width => 12) port map ( + nclk => nclk, act => msr_fp_act, + vd => vdd, gd => gnd, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + thold_b => thold_0_b, sg => sg_0, + scin => uc_scr_t0_scin, + scout => uc_scr_t0_scout, + din(0 to 11) => uc_scr_t0_ld, + dout(0 to 11) => uc_scr_t0_l2 ); + + uc_scr_t1_is2: tri_rlmreg_p generic map (init => 0, expand_type => expand_type, width => 12) port map ( + nclk => nclk, act => msr_fp_act, + vd => vdd, gd => gnd, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + thold_b => thold_0_b, sg => sg_0, + scin => uc_scr_t1_scin, + scout => uc_scr_t1_scout, + din(0 to 11) => uc_scr_t1_ld, + dout(0 to 11) => uc_scr_t1_l2 ); + + uc_scr_t2_is2: tri_rlmreg_p generic map (init => 0, expand_type => expand_type, width => 12) port map ( + nclk => nclk, act => msr_fp_act, + vd => vdd, gd => gnd, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + thold_b => thold_0_b, sg => sg_0, + scin => uc_scr_t2_scin, + scout => uc_scr_t2_scout, + din(0 to 11) => uc_scr_t2_ld, + dout(0 to 11) => uc_scr_t2_l2 ); + + uc_scr_t3_is2: tri_rlmreg_p generic map (init => 0, expand_type => expand_type, width => 12) port map ( + nclk => nclk, act => msr_fp_act, + vd => vdd, gd => gnd, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + thold_b => thold_0_b, sg => sg_0, + scin => uc_scr_t3_scin, + scout => uc_scr_t3_scout, + din(0 to 11) => uc_scr_t3_ld, + dout(0 to 11) => uc_scr_t3_l2 ); + + + +q1r_sign_rf0 <= (uc_scr_t0_l2(2) and thread_id_rf0(0)) or + (uc_scr_t1_l2(2) and thread_id_rf0(1)) or + (uc_scr_t2_l2(2) and thread_id_rf0(2)) or + (uc_scr_t3_l2(2) and thread_id_rf0(3)); + +q1r_zero_rf0 <= (uc_scr_t0_l2(3) and thread_id_rf0(0)) or + (uc_scr_t1_l2(3) and thread_id_rf0(1)) or + (uc_scr_t2_l2(3) and thread_id_rf0(2)) or + (uc_scr_t3_l2(3) and thread_id_rf0(3)); + + +q1ulpr_zero_rf0 <= (uc_scr_t0_l2(5) and thread_id_rf0(0)) or + (uc_scr_t1_l2(5) and thread_id_rf0(1)) or + (uc_scr_t2_l2(5) and thread_id_rf0(2)) or + (uc_scr_t3_l2(5) and thread_id_rf0(3)); + +ex4_uc_special <= ((uc_scr_t0_l2(0) and uc_scr_thread_ex4 = "00") or + (uc_scr_t1_l2(0) and uc_scr_thread_ex4 = "01") or + (uc_scr_t2_l2(0) and uc_scr_thread_ex4 = "10") or + (uc_scr_t3_l2(0) and uc_scr_thread_ex4 = "11") ) and not uc_end_ex4_l2 and not uc_beg_ex4 and not perr_sm_running ; + + +special_rf1 <= (uc_scr_t0_l2(0) and uc_scr_thread_rf1 = "00") or + (uc_scr_t1_l2(0) and uc_scr_thread_rf1 = "01") or + (uc_scr_t2_l2(0) and uc_scr_thread_rf1 = "10") or + (uc_scr_t3_l2(0) and uc_scr_thread_rf1 = "11"); + +f_dcd_ex2_uc_vxsnan <= ((uc_scr_t0_l2(0) and uc_scr_t0_l2(2) and uc_scr_thread_ex2 = "00") or + (uc_scr_t1_l2(0) and uc_scr_t1_l2(2) and uc_scr_thread_ex2 = "01") or + (uc_scr_t2_l2(0) and uc_scr_t2_l2(2) and uc_scr_thread_ex2 = "10") or + (uc_scr_t3_l2(0) and uc_scr_t3_l2(2) and uc_scr_thread_ex2 = "11")) and not perr_sm_running ; + + +f_dcd_ex2_uc_zx <= ((uc_scr_t0_l2(0) and uc_scr_t0_l2(3) and uc_scr_thread_ex2 = "00") or + (uc_scr_t1_l2(0) and uc_scr_t1_l2(3) and uc_scr_thread_ex2 = "01") or + (uc_scr_t2_l2(0) and uc_scr_t2_l2(3) and uc_scr_thread_ex2 = "10") or + (uc_scr_t3_l2(0) and uc_scr_t3_l2(3) and uc_scr_thread_ex2 = "11")) and not perr_sm_running ; + + +f_dcd_ex2_uc_vxidi <= ((uc_scr_t0_l2(0) and uc_scr_t0_l2(4) and uc_scr_thread_ex2 = "00") or + (uc_scr_t1_l2(0) and uc_scr_t1_l2(4) and uc_scr_thread_ex2 = "01") or + (uc_scr_t2_l2(0) and uc_scr_t2_l2(4) and uc_scr_thread_ex2 = "10") or + (uc_scr_t3_l2(0) and uc_scr_t3_l2(4) and uc_scr_thread_ex2 = "11")) and not perr_sm_running ; + + +f_dcd_ex2_uc_vxzdz <= ((uc_scr_t0_l2(0) and uc_scr_t0_l2(5) and uc_scr_thread_ex2 = "00") or + (uc_scr_t1_l2(0) and uc_scr_t1_l2(5) and uc_scr_thread_ex2 = "01") or + (uc_scr_t2_l2(0) and uc_scr_t2_l2(5) and uc_scr_thread_ex2 = "10") or + (uc_scr_t3_l2(0) and uc_scr_t3_l2(5) and uc_scr_thread_ex2 = "11")) and not perr_sm_running ; + + +f_dcd_ex2_uc_vxsqrt <= ((uc_scr_t0_l2(0) and uc_scr_t0_l2(6) and uc_scr_thread_ex2 = "00") or + (uc_scr_t1_l2(0) and uc_scr_t1_l2(6) and uc_scr_thread_ex2 = "01") or + (uc_scr_t2_l2(0) and uc_scr_t2_l2(6) and uc_scr_thread_ex2 = "10") or + (uc_scr_t3_l2(0) and uc_scr_t3_l2(6) and uc_scr_thread_ex2 = "11")) and not perr_sm_running ; + + +uc_scr_thread_rf0(0) <= thread_id_rf0(2) or thread_id_rf0(3); +uc_scr_thread_rf0(1) <= thread_id_rf0(1) or thread_id_rf0(3); + +uc_fc_pos_rf0 <= uc_fc_pos or uc_end_rf0_v; + + + pipe_rf1: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 22) + port map ( + nclk => nclk, act => tiup, + vd => vdd, gd => gnd, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + thold_b => thold_0_b, sg => sg_0, + scin => pipe_rf1_scin, + scout => pipe_rf1_scout, + din(00) => uc_div_beg_rf0, + din(01) => uc_sqrt_beg_rf0, + din(02) => uc_mid_rf0, + din(03) => uc_end_rf0_vf, + din(04) => '0', + din(05) => uc_fa_pos, + din(06) => uc_fc_pos_rf0, + din(07) => uc_fb_pos, + din(08) => uc_fc_hulp, + din(09) => uc_fc_0_5, + din(10) => uc_fc_1_0, + din(11) => uc_fc_1_minus, + din(12) => uc_fb_1_0, + din(13) => uc_fb_0_75, + din(14) => uc_fb_0_5, + din(15) => uc_fa_dis_par_rf0, + din(16) => uc_fb_dis_par_rf0, + din(17) => uc_fc_dis_par_rf0, + din(18) => uc_op_rnd_v, + din(19 to 20) => uc_op_rnd(0 to 1), + din(21) => iu_fu_rf0_ucfmul, + dout(00) => uc_div_beg_rf1, + dout(01) => uc_sqrt_beg_rf1, + dout(02) => uc_mid_rf1, + dout(03) => uc_end_rf1_l2, + dout(04) => spare, + dout(05) => uc_fa_pos_rf1, + dout(06) => uc_fc_pos_rf1, + dout(07) => uc_fb_pos_rf1, + dout(08) => uc_fc_hulp_rf1, + dout(09) => uc_fc_0_5_rf1, + dout(10) => uc_fc_1_0_rf1, + dout(11) => uc_fc_1_minus_rf1, + dout(12) => uc_fb_1_0_rf1, + dout(13) => uc_fb_0_75_rf1, + dout(14) => uc_fb_0_5_rf1, + dout(15) => uc_fa_dis_par_rf1, + dout(16) => uc_fb_dis_par_rf1, + dout(17) => uc_fc_dis_par_rf1, + dout(18) => uc_op_rnd_v_rf1_l2, + dout(19 to 20) => uc_op_rnd_rf1_l2(0 to 1), + dout(21) => rf1_ucfmul + ); + + +rf0_instr_flush <= ((thread_id_rf0(0) and xu_rf0_flush(0)) or + (thread_id_rf0(1) and xu_rf0_flush(1)) or + (thread_id_rf0(2) and xu_rf0_flush(2)) or + (thread_id_rf0(3) and xu_rf0_flush(3)) ); + +uc_scr_wr_rf0 <= (uc_scr_wr or uc_beg_rf0) and iu_fu_rf0_instr_v and not rf0_instr_flush; + + uc_scr_wr_pipe_rf1: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 8) + port map ( + nclk => nclk, act => msr_fp_act, + vd => vdd, gd => gnd, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + thold_b => thold_0_b, sg => sg_0, + scin => uc_scr_wr_pipe_rf1_scin, + scout => uc_scr_wr_pipe_rf1_scout, + din(0) => uc_scr_wr_rf0, + din(1 to 2) => uc_scr_sel(0 to 1), + din(3 to 4) => uc_scr_thread_rf0(0 to 1), + din(5) => uc_gs_v_rf0, + din(6) => uc_inc_lsb, + din(7) => uc_beg_rf0_v, + dout(0) => uc_scr_wr_rf1_l2, + dout(1 to 2) => uc_scr_sel_rf1(0 to 1), + dout(3 to 4) => uc_scr_thread_rf1(0 to 1), + dout(5) => uc_gs_v_rf1, + dout(6) => uc_inc_lsb_rf1, + dout(7) => uc_beg_rf1 + ); + +rf1_instr_flush <= ((uc_scr_thread_rf1(0 to 1) = "00" and xu_rf1_flush(0)) or + (uc_scr_thread_rf1(0 to 1) = "01" and xu_rf1_flush(1)) or + (uc_scr_thread_rf1(0 to 1) = "10" and xu_rf1_flush(2)) or + (uc_scr_thread_rf1(0 to 1) = "11" and xu_rf1_flush(3)) ); + +uc_scr_wr_rf1 <= uc_scr_wr_rf1_l2 and not rf1_instr_flush; + +uc_end_rf1_v <= uc_end_rf1_l2 and not rf1_instr_flush; +uc_end_rf1 <= uc_end_rf1_l2; + + uc_scr_wr_pipe_ex1: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 9) + port map ( + nclk => nclk, act => msr_fp_act, + vd => vdd, gd => gnd, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + thold_b => thold_0_b, sg => sg_0, + scin => uc_scr_wr_pipe_ex1_scin, + scout => uc_scr_wr_pipe_ex1_scout, + din(0) => uc_scr_wr_rf1, + din(1 to 2) => uc_scr_sel_rf1(0 to 1), + din(3 to 4) => uc_scr_thread_rf1(0 to 1), + din(5) => uc_gs_v_rf1, + din(6) => uc_inc_lsb_rf1, + din(7) => uc_end_rf1_v, + din(8) => uc_beg_rf1, + dout(0) => uc_scr_wr_ex1_l2, + dout(1 to 2) => uc_scr_sel_ex1(0 to 1), + dout(3 to 4) => uc_scr_thread_ex1(0 to 1), + dout(5) => uc_gs_v_ex1, + dout(6) => uc_inc_lsb_ex1, + dout(7) => uc_end_ex1_l2, + dout(8) => uc_beg_ex1 + ); + +ex1_instr_flush <= ((uc_scr_thread_ex1(0 to 1) = "00" and xu_ex1_flush(0)) or + (uc_scr_thread_ex1(0 to 1) = "01" and xu_ex1_flush(1)) or + (uc_scr_thread_ex1(0 to 1) = "10" and xu_ex1_flush(2)) or + (uc_scr_thread_ex1(0 to 1) = "11" and xu_ex1_flush(3)) ); + +uc_scr_wr_ex1 <= uc_scr_wr_ex1_l2 and not ex1_instr_flush; + +uc_end_ex1 <= uc_end_ex1_l2 and not ex1_instr_flush; + + uc_scr_wr_pipe_ex2: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 9) + port map ( + nclk => nclk, act => msr_fp_act, + vd => vdd, gd => gnd, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + thold_b => thold_0_b, sg => sg_0, + scin => uc_scr_wr_pipe_ex2_scin, + scout => uc_scr_wr_pipe_ex2_scout, + din(0) => uc_scr_wr_ex1, + din(1 to 2) => uc_scr_sel_ex1(0 to 1), + din(3 to 4) => uc_scr_thread_ex1(0 to 1), + din(5) => uc_gs_v_ex1, + din(6) => uc_inc_lsb_ex1, + din(7) => uc_end_ex1, + din(8) => uc_beg_ex1, + dout(0) => uc_scr_wr_ex2_l2, + dout(1 to 2) => uc_scr_sel_ex2(0 to 1), + dout(3 to 4) => uc_scr_thread_ex2(0 to 1), + dout(5) => uc_gs_v_ex2, + dout(6) => uc_inc_lsb_ex2, + dout(7) => uc_end_ex2_l2, + dout(8) => uc_beg_ex2 + ); + +ex2_instr_flush <= ((uc_scr_thread_ex2(0 to 1) = "00" and xu_ex2_flush(0)) or + (uc_scr_thread_ex2(0 to 1) = "01" and xu_ex2_flush(1)) or + (uc_scr_thread_ex2(0 to 1) = "10" and xu_ex2_flush(2)) or + (uc_scr_thread_ex2(0 to 1) = "11" and xu_ex2_flush(3)) ); + +uc_scr_wr_ex2 <= uc_scr_wr_ex2_l2 and not ex2_instr_flush; + +uc_end_ex2 <= uc_end_ex2_l2 and not ex2_instr_flush; + + uc_scr_wr_pipe_ex3: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 7) + port map ( + nclk => nclk, act => msr_fp_act, + vd => vdd, gd => gnd, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + thold_b => thold_0_b, sg => sg_0, + scin => uc_scr_wr_pipe_ex3_scin, + scout => uc_scr_wr_pipe_ex3_scout, + din(0) => uc_scr_wr_ex2, + din(1 to 2) => uc_scr_sel_ex2(0 to 1), + din(3 to 4) => uc_scr_thread_ex2(0 to 1), + din(5) => uc_end_ex2, + din(6) => uc_beg_ex2, + dout(0) => uc_scr_wr_ex3_l2, + dout(1 to 2) => uc_scr_sel_ex3(0 to 1), + dout(3 to 4) => uc_scr_thread_ex3(0 to 1), + dout(5) => uc_end_ex3_l2, + dout(6) => uc_beg_ex3 + ); + + +ex3_instr_flush_th(0) <= uc_scr_thread_ex3(0 to 1) = "00" and xu_ex3_flush(0) ; +ex3_instr_flush_th(1) <= uc_scr_thread_ex3(0 to 1) = "01" and xu_ex3_flush(1) ; +ex3_instr_flush_th(2) <= uc_scr_thread_ex3(0 to 1) = "10" and xu_ex3_flush(2) ; +ex3_instr_flush_th(3) <= uc_scr_thread_ex3(0 to 1) = "11" and xu_ex3_flush(3) ; + +ex3_instr_flush <= ex3_instr_flush_th(0) or + ex3_instr_flush_th(1) or + ex3_instr_flush_th(2) or + ex3_instr_flush_th(3) ; + +uc_scr_wr_ex3 <= uc_scr_wr_ex3_l2 and not ex3_instr_flush ; + +uc_end_ex3 <= uc_end_ex3_l2 and not ex3_instr_flush; + +uc_scr_wr_ex4_ld <= uc_scr_wr_ex3 and (uc_scr_sel_ex3(0) or uc_scr_sel_ex3(1)); + + uc_scr_wr_pipe_ex4: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 7) + port map ( + nclk => nclk, act => msr_fp_act, + vd => vdd, gd => gnd, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + thold_b => thold_0_b, sg => sg_0, + scin => uc_scr_wr_pipe_ex4_scin, + scout => uc_scr_wr_pipe_ex4_scout, + din(0) => uc_scr_wr_ex4_ld, + din(1 to 2) => uc_scr_sel_ex3(0 to 1), + din(3 to 4) => uc_scr_thread_ex3(0 to 1), + din(5) => uc_end_ex3, + din(6) => uc_beg_ex3, + dout(0) => uc_scr_wr_ex4_l2, + dout(1 to 2) => uc_scr_sel_ex4(0 to 1), + dout(3 to 4) => uc_scr_thread_ex4(0 to 1), + dout(5) => uc_end_ex4_l2, + dout(6) => uc_beg_ex4 + ); + +ex4_instr_flush <= ((uc_scr_thread_ex4(0 to 1) = "00" and xu_ex4_flush(0)) or + (uc_scr_thread_ex4(0 to 1) = "01" and xu_ex4_flush(1)) or + (uc_scr_thread_ex4(0 to 1) = "10" and xu_ex4_flush(2)) or + (uc_scr_thread_ex4(0 to 1) = "11" and xu_ex4_flush(3)) ); + +uc_scr_wr_ex4 <= uc_scr_wr_ex4_l2 and not ex4_instr_flush; + +uc_end_ex4 <= uc_end_ex4_l2 and not ex4_instr_flush; + + uc_scr_wr_pipe_ex5: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 6) + port map ( + nclk => nclk, act => msr_fp_act, + vd => vdd, gd => gnd, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + thold_b => thold_0_b, sg => sg_0, + scin => uc_scr_wr_pipe_ex5_scin, + scout => uc_scr_wr_pipe_ex5_scout, + din(0) => uc_scr_wr_ex4, + din(1 to 2) => uc_scr_sel_ex4(0 to 1), + din(3 to 4) => uc_scr_thread_ex4(0 to 1), + din(5) => uc_end_ex4, + dout(0) => uc_scr_wr_ex5_l2, + dout(1 to 2) => uc_scr_sel_ex5(0 to 1), + dout(3 to 4) => uc_scr_thread_ex5(0 to 1), + dout(5) => uc_end_ex5_l2 + ); + +ex5_instr_flush <= ((uc_scr_thread_ex5(0 to 1) = "00" and xu_ex5_flush(0)) or + (uc_scr_thread_ex5(0 to 1) = "01" and xu_ex5_flush(1)) or + (uc_scr_thread_ex5(0 to 1) = "10" and xu_ex5_flush(2)) or + (uc_scr_thread_ex5(0 to 1) = "11" and xu_ex5_flush(3)) ); + +uc_scr_wr_ex5 <= uc_scr_wr_ex5_l2 and not ex5_instr_flush; + +uc_end_ex5 <= uc_end_ex5_l2 and not ex5_instr_flush; + + uc_scr_wr_pipe_ex6: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 6) + port map ( + nclk => nclk, act => msr_fp_act, + vd => vdd, gd => gnd, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + thold_b => thold_0_b, sg => sg_0, + scin => uc_scr_wr_pipe_ex6_scin, + scout => uc_scr_wr_pipe_ex6_scout, + din(0) => uc_scr_wr_ex5, + din(1 to 2) => uc_scr_sel_ex5(0 to 1), + din(3 to 4) => uc_scr_thread_ex5(0 to 1), + din(5) => uc_end_ex5, + dout(0) => uc_scr_wr_ex6, + dout(1 to 2) => uc_scr_sel_ex6(0 to 1), + dout(3 to 4) => uc_scr_thread_ex6(0 to 1), + dout(5) => uc_end_ex6_l2 + ); + + + +q1_p_ulp_early_ld(0) <= (not uc_scr_t0_l2(3) and not uc_scr_t0_l2(4)) or uc_scr_t0_l2(5); + +q1_p_ulp_early_ld(1) <= (not uc_scr_t1_l2(3) and not uc_scr_t1_l2(4)) or uc_scr_t1_l2(5); + +q1_p_ulp_early_ld(2) <= (not uc_scr_t2_l2(3) and not uc_scr_t2_l2(4)) or uc_scr_t2_l2(5); + +q1_p_ulp_early_ld(3) <= (not uc_scr_t3_l2(3) and not uc_scr_t3_l2(4)) or uc_scr_t3_l2(5); + + + q1_p_ulp_early: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 4) + port map ( + nclk => nclk, act => msr_fp_act, + vd => vdd, gd => gnd, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + thold_b => thold_0_b, sg => sg_0, + scin => q1_p_ulp_early_scin, + scout => q1_p_ulp_early_scout, + din(0 to 3) => q1_p_ulp_early_ld(0 to 3), + + dout(0 to 3) => q1_p_ulp_early_l2(0 to 3) + + ); + + + + + + + + + + + + + + +q1_m_ulp_rf0 <= (not q1r_zero_rf0 and not q1ulpr_zero_rf0 and q1r_sign_rf0); + + + + + +uc_fc_1_minus <= q1_m_ulp_rf0 and uc_normal_end_rf0 ; +uc_fc_1_0 <= not q1_m_ulp_rf0 and uc_end_rf0_v ; + + + + + f_dcd_rf1_div_beg <= uc_div_beg_rf1 and not perr_sm_running ; + f_dcd_rf1_sqrt_beg <= uc_sqrt_beg_rf1 and not perr_sm_running ; + f_dcd_rf1_uc_mid <= uc_mid_rf1 and not rf1_ucfmul and not perr_sm_running ; + f_dcd_rf1_uc_end <= uc_end_rf1 and not perr_sm_running ; + f_dcd_rf1_uc_special <= special_rf1 and not perr_sm_running ; + f_dcd_rf1_uc_fa_pos <= uc_fa_pos_rf1 and not perr_sm_running ; + f_dcd_rf1_uc_fc_pos <= uc_fc_pos_rf1 and not perr_sm_running ; + f_dcd_rf1_uc_fb_pos <= uc_fb_pos_rf1 and not perr_sm_running ; + f_dcd_rf1_uc_fc_hulp <= uc_fc_hulp_rf1 and not perr_sm_running ; + f_dcd_rf1_uc_fc_0_5 <= uc_fc_0_5_rf1 and not perr_sm_running ; + f_dcd_rf1_uc_fc_1_0 <= uc_fc_1_0_rf1 and not perr_sm_running ; + f_dcd_rf1_uc_fc_1_minus <= uc_fc_1_minus_rf1 and not perr_sm_running ; + f_dcd_rf1_uc_fb_1_0 <= uc_fb_1_0_rf1 and not perr_sm_running ; + f_dcd_rf1_uc_fb_0_75 <= uc_fb_0_75_rf1 and not perr_sm_running ; + f_dcd_rf1_uc_fb_0_5 <= uc_fb_0_5_rf1 and not perr_sm_running ; + + f_dcd_rf1_uc_fa_dis_par <= uc_fa_dis_par_rf1 and not perr_sm_running ; + f_dcd_rf1_uc_fb_dis_par <= uc_fb_dis_par_rf1 and not perr_sm_running ; + f_dcd_rf1_uc_fc_dis_par <= uc_fc_dis_par_rf1 and not perr_sm_running ; + + uc_op_rnd_v_rf1 <= uc_op_rnd_v_rf1_l2 and not perr_sm_running ; + uc_op_rnd_rf1 <= uc_op_rnd_rf1_l2 ; + + + + + f_dcd_rf1_uc_ft_pos <= + not res_sign_rf1 and not perr_sm_running when uc_end_rf1='1' and special_rf1='0' else + '0'; + + f_dcd_rf1_uc_ft_neg <= + res_sign_rf1 and not perr_sm_running when uc_end_rf1='1' and special_rf1='0' else + '0'; + + + +res_sign_rf1 <= (uc_scr_t0_l2(1) and uc_scr_thread_rf1 = "00") or + (uc_scr_t1_l2(1) and uc_scr_thread_rf1 = "01") or + (uc_scr_t2_l2(1) and uc_scr_thread_rf1 = "10") or + (uc_scr_t3_l2(1) and uc_scr_thread_rf1 = "11"); + + + +q1r_sign_ex2 <= (uc_scr_t0_l2(2) and uc_scr_thread_ex2 = "00") or + (uc_scr_t1_l2(2) and uc_scr_thread_ex2 = "01") or + (uc_scr_t2_l2(2) and uc_scr_thread_ex2 = "10") or + (uc_scr_t3_l2(2) and uc_scr_thread_ex2 = "11"); + +q1r_zero_ex2 <= (uc_scr_t0_l2(3) and uc_scr_thread_ex2 = "00") or + (uc_scr_t1_l2(3) and uc_scr_thread_ex2 = "01") or + (uc_scr_t2_l2(3) and uc_scr_thread_ex2 = "10") or + (uc_scr_t3_l2(3) and uc_scr_thread_ex2 = "11"); + +q1ulpr_sign_ex2 <= (uc_scr_t0_l2(4) and uc_scr_thread_ex2 = "00") or + (uc_scr_t1_l2(4) and uc_scr_thread_ex2 = "01") or + (uc_scr_t2_l2(4) and uc_scr_thread_ex2 = "10") or + (uc_scr_t3_l2(4) and uc_scr_thread_ex2 = "11"); + +q1ulpr_zero_ex2 <= (uc_scr_t0_l2(5) and uc_scr_thread_ex2 = "00") or + (uc_scr_t1_l2(5) and uc_scr_thread_ex2 = "01") or + (uc_scr_t2_l2(5) and uc_scr_thread_ex2 = "10") or + (uc_scr_t3_l2(5) and uc_scr_thread_ex2 = "11"); + +q1hulpr_sign_ex2 <= (uc_scr_t0_l2(6) and uc_scr_thread_ex2 = "00") or + (uc_scr_t1_l2(6) and uc_scr_thread_ex2 = "01") or + (uc_scr_t2_l2(6) and uc_scr_thread_ex2 = "10") or + (uc_scr_t3_l2(6) and uc_scr_thread_ex2 = "11"); + +uc_round_mode_ex2(0) <= (uc_round_mode_l2(0) and uc_scr_thread_ex2 = "00") or + (uc_round_mode_l2(2) and uc_scr_thread_ex2 = "01") or + (uc_round_mode_l2(4) and uc_scr_thread_ex2 = "10") or + (uc_round_mode_l2(6) and uc_scr_thread_ex2 = "11"); + +uc_round_mode_ex2(1) <= (uc_round_mode_l2(1) and uc_scr_thread_ex2 = "00") or + (uc_round_mode_l2(3) and uc_scr_thread_ex2 = "01") or + (uc_round_mode_l2(5) and uc_scr_thread_ex2 = "10") or + (uc_round_mode_l2(7) and uc_scr_thread_ex2 = "11"); + + + + +uc_gs_ex2(0) <= (not q1r_zero_ex2 and not q1ulpr_zero_ex2 and not uc_round_mode_ex2(0) + and not uc_round_mode_ex2(1) and q1ulpr_sign_ex2 + and not q1hulpr_sign_ex2) or + (not q1r_zero_ex2 and not q1ulpr_zero_ex2 + and not uc_round_mode_ex2(0) and not uc_round_mode_ex2(1) + and q1r_sign_ex2); + +uc_gs_ex2(1) <= (not q1r_zero_ex2 and not q1ulpr_zero_ex2); + + + + + + f_dcd_ex2_uc_gs_v <= uc_gs_v_ex2 and not perr_sm_running ; + f_dcd_ex2_uc_gs <= uc_gs_ex2(0 to 1); + f_dcd_ex2_uc_inc_lsb <= uc_inc_lsb_ex2 and not perr_sm_running ; + + +uc_ignore_flush_rf1 <= uc_div_beg_rf1 or uc_sqrt_beg_rf1; + + + + + + + + + + + + +evnt_div_sqrt_ip(0 to 3) <= uc_scr_t0_l2(7) & uc_scr_t1_l2(7) & uc_scr_t2_l2(7) & uc_scr_t3_l2(7); + + +uc_hooks_debug( 0 to 7) <= uc_scr_t0_l2(0 to 7); +uc_hooks_debug( 8 to 15) <= uc_scr_t1_l2(0 to 7); +uc_hooks_debug(16 to 23) <= uc_scr_t2_l2(0 to 7); +uc_hooks_debug(24 to 31) <= uc_scr_t3_l2(0 to 7); + +uc_hooks_debug(32 to 35) <= uc_1st_instr_l2(0 to 3); +uc_hooks_debug(36) <= uc_div_beg_rf1 ; +uc_hooks_debug(37) <= uc_sqrt_beg_rf1 ; +uc_hooks_debug(38) <= uc_mid_rf1 ; +uc_hooks_debug(39) <= uc_end_rf1 ; +uc_hooks_debug(40) <= uc_fa_pos_rf1 ; +uc_hooks_debug(41) <= uc_fc_pos_rf1 ; +uc_hooks_debug(42) <= uc_fb_pos_rf1 ; +uc_hooks_debug(43) <= uc_fc_hulp_rf1 ; +uc_hooks_debug(44) <= uc_fc_0_5_rf1 ; +uc_hooks_debug(45) <= uc_fc_1_0_rf1 ; +uc_hooks_debug(46) <= uc_fc_1_minus_rf1 ; +uc_hooks_debug(47) <= uc_fb_1_0_rf1 ; +uc_hooks_debug(48) <= uc_fb_0_75_rf1 ; +uc_hooks_debug(49) <= uc_fb_0_5_rf1 ; +uc_hooks_debug(50) <= uc_op_rnd_v_rf1_l2 ; +uc_hooks_debug(51) <= uc_op_rnd_rf1_l2(0) ; +uc_hooks_debug(52) <= uc_op_rnd_rf1_l2(1) ; + +uc_hooks_debug(53) <= uc_end_rf1_l2 ; +uc_hooks_debug(54 to 55) <= uc_scr_thread_ex1(0 to 1) ; + + +spare_unused(0 to 19) <= rf0_i(6 to 25); +spare_unused(20) <= rf0_i(31); +spare_unused(21) <= spare; + + + uc_1st_instr_scin <= f_ucode_si & uc_1st_instr_scout(0 to 2); + uc_round_mode_scin <= uc_1st_instr_scout(3) & uc_round_mode_scout(0 to 6); + uc_scr_t0_scin <= uc_round_mode_scout(7) & uc_scr_t0_scout(0 to 10); + uc_scr_t1_scin <= uc_scr_t0_scout(11) & uc_scr_t1_scout(0 to 10); + uc_scr_t2_scin <= uc_scr_t1_scout(11) & uc_scr_t2_scout(0 to 10); + uc_scr_t3_scin <= uc_scr_t2_scout(11) & uc_scr_t3_scout(0 to 10); + uc_scr_wr_pipe_rf1_scin <= uc_scr_t3_scout(11) & uc_scr_wr_pipe_rf1_scout(0 to 6); + uc_scr_wr_pipe_ex1_scin <= uc_scr_wr_pipe_rf1_scout(7) & uc_scr_wr_pipe_ex1_scout(0 to 7); + uc_scr_wr_pipe_ex2_scin <= uc_scr_wr_pipe_ex1_scout(8) & uc_scr_wr_pipe_ex2_scout(0 to 7); + uc_scr_wr_pipe_ex3_scin <= uc_scr_wr_pipe_ex2_scout(8) & uc_scr_wr_pipe_ex3_scout(0 to 5); + uc_scr_wr_pipe_ex4_scin <= uc_scr_wr_pipe_ex3_scout(6) & uc_scr_wr_pipe_ex4_scout(0 to 5); + uc_scr_wr_pipe_ex5_scin <= uc_scr_wr_pipe_ex4_scout(6) & uc_scr_wr_pipe_ex5_scout(0 to 4); + uc_scr_wr_pipe_ex6_scin <= uc_scr_wr_pipe_ex5_scout(5) & uc_scr_wr_pipe_ex6_scout(0 to 4); + q1_p_ulp_early_scin <= uc_scr_wr_pipe_ex6_scout(5) & q1_p_ulp_early_scout(0 to 2); + pipe_rf1_scin <= q1_p_ulp_early_scout(3) & pipe_rf1_scout(0 to 20); + f_ucode_so <= pipe_rf1_scout(21); + + + +end fuq_dcd_uc_hooks; + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_eie.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_eie.vhdl new file mode 100644 index 0000000..ccf1338 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_eie.vhdl @@ -0,0 +1,599 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + + + + +entity fuq_eie is +generic( expand_type : integer := 2 ); +port( + + vdd :inout power_logic; + gnd :inout power_logic; + clkoff_b :in std_ulogic; + act_dis :in std_ulogic; + flush :in std_ulogic; + delay_lclkr :in std_ulogic_vector(2 to 3); + mpw1_b :in std_ulogic_vector(2 to 3); + mpw2_b :in std_ulogic_vector(0 to 0); + sg_1 :in std_ulogic; + thold_1 :in std_ulogic; + fpu_enable :in std_ulogic; + nclk :in clk_logic; + + f_eie_si :in std_ulogic ; + f_eie_so :out std_ulogic ; + ex1_act :in std_ulogic ; + + f_byp_eie_ex1_a_expo :in std_ulogic_vector(1 to 13) ; + f_byp_eie_ex1_c_expo :in std_ulogic_vector(1 to 13) ; + f_byp_eie_ex1_b_expo :in std_ulogic_vector(1 to 13) ; + + f_pic_ex1_from_integer :in std_ulogic ; + f_pic_ex1_fsel :in std_ulogic ; + f_pic_ex2_frsp_ue1 :in std_ulogic ; + + f_alg_ex2_sel_byp :in std_ulogic ; + f_fmt_ex2_fsel_bsel :in std_ulogic ; + f_pic_ex2_force_sel_bexp :in std_ulogic ; + f_pic_ex2_sp_b :in std_ulogic ; + f_pic_ex2_math_bzer_b :in std_ulogic ; + + f_eie_ex2_tbl_expo :out std_ulogic_vector(1 to 13) ; + + f_eie_ex2_lt_bias :out std_ulogic ; + f_eie_ex2_eq_bias_m1 :out std_ulogic ; + f_eie_ex2_wd_ov :out std_ulogic ; + f_eie_ex2_dw_ov :out std_ulogic ; + f_eie_ex2_wd_ov_if :out std_ulogic ; + f_eie_ex2_dw_ov_if :out std_ulogic ; + f_eie_ex2_lzo_expo :out std_ulogic_vector(1 to 13) ; + f_eie_ex2_b_expo :out std_ulogic_vector(1 to 13) ; + f_eie_ex2_use_bexp :out std_ulogic; + f_eie_ex3_iexp :out std_ulogic_vector(1 to 13) + +); + + + +end fuq_eie; + + +architecture fuq_eie of fuq_eie is + + constant tiup :std_ulogic := '1'; + constant tidn :std_ulogic := '0'; + + signal sg_0 :std_ulogic ; + signal thold_0_b , thold_0, forcee :std_ulogic ; + + signal ex2_act :std_ulogic ; + signal act_spare_unused :std_ulogic_vector(0 to 3) ; + signal act_so :std_ulogic_vector(0 to 4) ; + signal act_si :std_ulogic_vector(0 to 4) ; + signal ex2_bop_so :std_ulogic_vector(0 to 12) ; + signal ex2_bop_si :std_ulogic_vector(0 to 12) ; + signal ex2_pop_so :std_ulogic_vector(0 to 12) ; + signal ex2_pop_si :std_ulogic_vector(0 to 12) ; + signal ex2_ctl_so :std_ulogic_vector(0 to 6) ; + signal ex2_ctl_si :std_ulogic_vector(0 to 6) ; + signal ex3_iexp_so :std_ulogic_vector(0 to 13) ; + signal ex3_iexp_si :std_ulogic_vector(0 to 13) ; + signal ex1_a_expo :std_ulogic_vector(1 to 13) ; + signal ex1_c_expo :std_ulogic_vector(1 to 13) ; + signal ex1_b_expo :std_ulogic_vector(1 to 13) ; + signal ex1_ep56_sum :std_ulogic_vector(1 to 13) ; + signal ex1_ep56_car :std_ulogic_vector(1 to 12) ; + signal ex1_ep56_p :std_ulogic_vector(1 to 13) ; + signal ex1_ep56_g :std_ulogic_vector(2 to 12) ; + signal ex1_ep56_t :std_ulogic_vector(2 to 11) ; + signal ex1_ep56_s :std_ulogic_vector(1 to 13) ; + signal ex1_ep56_c :std_ulogic_vector(2 to 12) ; + signal ex1_p_expo_adj :std_ulogic_vector(1 to 13) ; + signal ex1_from_k :std_ulogic_vector(1 to 13) ; + signal ex1_b_expo_adj :std_ulogic_vector(1 to 13) ; + signal ex2_p_expo :std_ulogic_vector(1 to 13) ; + signal ex2_b_expo :std_ulogic_vector(1 to 13) ; + signal ex2_iexp :std_ulogic_vector(1 to 13) ; + signal ex2_b_expo_adj :std_ulogic_vector(1 to 13) ; + signal ex2_p_expo_adj :std_ulogic_vector(1 to 13) ; + signal ex3_iexp :std_ulogic_vector(1 to 13) ; + signal ex1_wd_ge_bot :std_ulogic ; + signal ex1_dw_ge_bot :std_ulogic ; + signal ex1_ge_2048 :std_ulogic ; + signal ex1_ge_1024 :std_ulogic ; + signal ex1_dw_ge_mid :std_ulogic ; + signal ex1_wd_ge_mid :std_ulogic ; + signal ex1_dw_ge :std_ulogic ; + signal ex1_wd_ge :std_ulogic ; + signal ex1_dw_eq_top :std_ulogic ; + signal ex1_wd_eq_bot :std_ulogic ; + signal ex1_wd_eq :std_ulogic ; + signal ex1_dw_eq :std_ulogic ; + signal ex2_iexp_b_sel :std_ulogic ; + signal ex2_dw_ge :std_ulogic ; + signal ex2_wd_ge :std_ulogic ; + signal ex2_wd_eq :std_ulogic ; + signal ex2_dw_eq :std_ulogic ; + signal ex2_fsel :std_ulogic ; + signal ex3_sp_b :std_ulogic ; + + + signal ex2_b_expo_fixed :std_ulogic_vector(1 to 13); + signal ex1_ge_bias, ex1_lt_bias, ex1_eq_bias_m1 :std_ulogic; + signal ex2_lt_bias, ex2_eq_bias_m1 :std_ulogic; + signal ex1_ep56_g2 :std_ulogic_vector( 2 to 12); + signal ex1_ep56_t2 :std_ulogic_vector( 2 to 10); + signal ex1_ep56_g4 :std_ulogic_vector( 2 to 12); + signal ex1_ep56_t4 :std_ulogic_vector( 2 to 8); + signal ex1_ep56_g8 :std_ulogic_vector( 2 to 12); + signal ex1_ep56_t8 :std_ulogic_vector( 2 to 4); + + + +begin + + + + thold_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => thold_1, + q(0) => thold_0 ); + + sg_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => sg_1 , + q(0) => sg_0 ); + + + lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map ( + clkoff_b => clkoff_b, + thold => thold_0, + sg => sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => thold_0_b ); + + + + + + + act_lat: tri_rlmreg_p generic map (width=> 5, expand_type => expand_type, needs_sreset => 0) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(2) , + mpw1_b => mpw1_b(2) , + mpw2_b => mpw2_b(0) , + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => fpu_enable, + scout => act_so , + scin => act_si , + din(0) => act_spare_unused(0), + din(1) => act_spare_unused(1), + din(2) => ex1_act, + din(3) => act_spare_unused(2), + din(4) => act_spare_unused(3), + dout(0) => act_spare_unused(0), + dout(1) => act_spare_unused(1), + dout(2) => ex2_act, + dout(3) => act_spare_unused(2), + dout(4) => act_spare_unused(3) ); + + + + ex1_a_expo(1 to 13) <= f_byp_eie_ex1_a_expo(1 to 13); + ex1_c_expo(1 to 13) <= f_byp_eie_ex1_c_expo(1 to 13); + ex1_b_expo(1 to 13) <= f_byp_eie_ex1_b_expo(1 to 13); + + + + + ex1_ep56_sum( 1) <= not( ex1_a_expo( 1) xor ex1_c_expo( 1) ); + ex1_ep56_sum( 2) <= not( ex1_a_expo( 2) xor ex1_c_expo( 2) ); + ex1_ep56_sum( 3) <= not( ex1_a_expo( 3) xor ex1_c_expo( 3) ); + ex1_ep56_sum( 4) <= ( ex1_a_expo( 4) xor ex1_c_expo( 4) ); + ex1_ep56_sum( 5) <= ( ex1_a_expo( 5) xor ex1_c_expo( 5) ); + ex1_ep56_sum( 6) <= ( ex1_a_expo( 6) xor ex1_c_expo( 6) ); + ex1_ep56_sum( 7) <= ( ex1_a_expo( 7) xor ex1_c_expo( 7) ); + ex1_ep56_sum( 8) <= not( ex1_a_expo( 8) xor ex1_c_expo( 8) ); + ex1_ep56_sum( 9) <= not( ex1_a_expo( 9) xor ex1_c_expo( 9) ); + ex1_ep56_sum(10) <= not( ex1_a_expo(10) xor ex1_c_expo(10) ); + ex1_ep56_sum(11) <= ( ex1_a_expo(11) xor ex1_c_expo(11) ); + ex1_ep56_sum(12) <= ( ex1_a_expo(12) xor ex1_c_expo(12) ); + ex1_ep56_sum(13) <= not( ex1_a_expo(13) xor ex1_c_expo(13) ); + + ex1_ep56_car( 1) <= ( ex1_a_expo( 2) or ex1_c_expo( 2) ); + ex1_ep56_car( 2) <= ( ex1_a_expo( 3) or ex1_c_expo( 3) ); + ex1_ep56_car( 3) <= ( ex1_a_expo( 4) and ex1_c_expo( 4) ); + ex1_ep56_car( 4) <= ( ex1_a_expo( 5) and ex1_c_expo( 5) ); + ex1_ep56_car( 5) <= ( ex1_a_expo( 6) and ex1_c_expo( 6) ); + ex1_ep56_car( 6) <= ( ex1_a_expo( 7) and ex1_c_expo( 7) ); + ex1_ep56_car( 7) <= ( ex1_a_expo( 8) or ex1_c_expo( 8) ); + ex1_ep56_car( 8) <= ( ex1_a_expo( 9) or ex1_c_expo( 9) ); + ex1_ep56_car( 9) <= ( ex1_a_expo(10) or ex1_c_expo(10) ); + ex1_ep56_car(10) <= ( ex1_a_expo(11) and ex1_c_expo(11) ); + ex1_ep56_car(11) <= ( ex1_a_expo(12) and ex1_c_expo(12) ); + ex1_ep56_car(12) <= ( ex1_a_expo(13) or ex1_c_expo(13) ); + + ex1_ep56_p(1 to 12) <= ex1_ep56_sum(1 to 12) xor ex1_ep56_car(1 to 12); + ex1_ep56_p(13) <= ex1_ep56_sum(13); + ex1_ep56_g(2 to 12) <= ex1_ep56_sum(2 to 12) and ex1_ep56_car(2 to 12); + ex1_ep56_t(2 to 11) <= ex1_ep56_sum(2 to 11) or ex1_ep56_car(2 to 11); + + ex1_ep56_s(1 to 11) <= ex1_ep56_p(1 to 11) xor ex1_ep56_c(2 to 12); + ex1_ep56_s(12) <= ex1_ep56_p(12); + ex1_ep56_s(13) <= ex1_ep56_p(13); + + + ex1_ep56_g2(12) <= ex1_ep56_g(12) ; + ex1_ep56_g2(11) <= ex1_ep56_g(11) or (ex1_ep56_t(11) and ex1_ep56_g(12)) ; + ex1_ep56_g2(10) <= ex1_ep56_g(10) or (ex1_ep56_t(10) and ex1_ep56_g(11)) ; + ex1_ep56_g2( 9) <= ex1_ep56_g( 9) or (ex1_ep56_t( 9) and ex1_ep56_g(10)) ; + ex1_ep56_g2( 8) <= ex1_ep56_g( 8) or (ex1_ep56_t( 8) and ex1_ep56_g( 9)) ; + ex1_ep56_g2( 7) <= ex1_ep56_g( 7) or (ex1_ep56_t( 7) and ex1_ep56_g( 8)) ; + ex1_ep56_g2( 6) <= ex1_ep56_g( 6) or (ex1_ep56_t( 6) and ex1_ep56_g( 7)) ; + ex1_ep56_g2( 5) <= ex1_ep56_g( 5) or (ex1_ep56_t( 5) and ex1_ep56_g( 6)) ; + ex1_ep56_g2( 4) <= ex1_ep56_g( 4) or (ex1_ep56_t( 4) and ex1_ep56_g( 5)) ; + ex1_ep56_g2( 3) <= ex1_ep56_g( 3) or (ex1_ep56_t( 3) and ex1_ep56_g( 4)) ; + ex1_ep56_g2( 2) <= ex1_ep56_g( 2) or (ex1_ep56_t( 2) and ex1_ep56_g( 3)) ; + + ex1_ep56_t2(10) <= (ex1_ep56_t(10) and ex1_ep56_t(11)) ; + ex1_ep56_t2( 9) <= (ex1_ep56_t( 9) and ex1_ep56_t(10)) ; + ex1_ep56_t2( 8) <= (ex1_ep56_t( 8) and ex1_ep56_t( 9)) ; + ex1_ep56_t2( 7) <= (ex1_ep56_t( 7) and ex1_ep56_t( 8)) ; + ex1_ep56_t2( 6) <= (ex1_ep56_t( 6) and ex1_ep56_t( 7)) ; + ex1_ep56_t2( 5) <= (ex1_ep56_t( 5) and ex1_ep56_t( 6)) ; + ex1_ep56_t2( 4) <= (ex1_ep56_t( 4) and ex1_ep56_t( 5)) ; + ex1_ep56_t2( 3) <= (ex1_ep56_t( 3) and ex1_ep56_t( 4)) ; + ex1_ep56_t2( 2) <= (ex1_ep56_t( 2) and ex1_ep56_t( 3)) ; + + ex1_ep56_g4(12) <= ex1_ep56_g2(12) ; + ex1_ep56_g4(11) <= ex1_ep56_g2(11) ; + ex1_ep56_g4(10) <= ex1_ep56_g2(10) or (ex1_ep56_t2(10) and ex1_ep56_g2(12)) ; + ex1_ep56_g4( 9) <= ex1_ep56_g2( 9) or (ex1_ep56_t2( 9) and ex1_ep56_g2(11)) ; + ex1_ep56_g4( 8) <= ex1_ep56_g2( 8) or (ex1_ep56_t2( 8) and ex1_ep56_g2(10)) ; + ex1_ep56_g4( 7) <= ex1_ep56_g2( 7) or (ex1_ep56_t2( 7) and ex1_ep56_g2( 9)) ; + ex1_ep56_g4( 6) <= ex1_ep56_g2( 6) or (ex1_ep56_t2( 6) and ex1_ep56_g2( 8)) ; + ex1_ep56_g4( 5) <= ex1_ep56_g2( 5) or (ex1_ep56_t2( 5) and ex1_ep56_g2( 7)) ; + ex1_ep56_g4( 4) <= ex1_ep56_g2( 4) or (ex1_ep56_t2( 4) and ex1_ep56_g2( 6)) ; + ex1_ep56_g4( 3) <= ex1_ep56_g2( 3) or (ex1_ep56_t2( 3) and ex1_ep56_g2( 5)) ; + ex1_ep56_g4( 2) <= ex1_ep56_g2( 2) or (ex1_ep56_t2( 2) and ex1_ep56_g2( 4)) ; + + ex1_ep56_t4( 8) <= (ex1_ep56_t2( 8) and ex1_ep56_t2(10)) ; + ex1_ep56_t4( 7) <= (ex1_ep56_t2( 7) and ex1_ep56_t2( 9)) ; + ex1_ep56_t4( 6) <= (ex1_ep56_t2( 6) and ex1_ep56_t2( 8)) ; + ex1_ep56_t4( 5) <= (ex1_ep56_t2( 5) and ex1_ep56_t2( 7)) ; + ex1_ep56_t4( 4) <= (ex1_ep56_t2( 4) and ex1_ep56_t2( 6)) ; + ex1_ep56_t4( 3) <= (ex1_ep56_t2( 3) and ex1_ep56_t2( 5)) ; + ex1_ep56_t4( 2) <= (ex1_ep56_t2( 2) and ex1_ep56_t2( 4)) ; + + ex1_ep56_g8(12) <= ex1_ep56_g4(12) ; + ex1_ep56_g8(11) <= ex1_ep56_g4(11) ; + ex1_ep56_g8(10) <= ex1_ep56_g4(10) ; + ex1_ep56_g8( 9) <= ex1_ep56_g4( 9) ; + ex1_ep56_g8( 8) <= ex1_ep56_g4( 8) or (ex1_ep56_t4( 8) and ex1_ep56_g4(12)) ; + ex1_ep56_g8( 7) <= ex1_ep56_g4( 7) or (ex1_ep56_t4( 7) and ex1_ep56_g4(11)) ; + ex1_ep56_g8( 6) <= ex1_ep56_g4( 6) or (ex1_ep56_t4( 6) and ex1_ep56_g4(10)) ; + ex1_ep56_g8( 5) <= ex1_ep56_g4( 5) or (ex1_ep56_t4( 5) and ex1_ep56_g4( 9)) ; + ex1_ep56_g8( 4) <= ex1_ep56_g4( 4) or (ex1_ep56_t4( 4) and ex1_ep56_g4( 8)) ; + ex1_ep56_g8( 3) <= ex1_ep56_g4( 3) or (ex1_ep56_t4( 3) and ex1_ep56_g4( 7)) ; + ex1_ep56_g8( 2) <= ex1_ep56_g4( 2) or (ex1_ep56_t4( 2) and ex1_ep56_g4( 6)) ; + + ex1_ep56_t8( 4) <= (ex1_ep56_t4( 4) and ex1_ep56_t4( 8)) ; + ex1_ep56_t8( 3) <= (ex1_ep56_t4( 3) and ex1_ep56_t4( 7)) ; + ex1_ep56_t8( 2) <= (ex1_ep56_t4( 2) and ex1_ep56_t4( 6)) ; + + ex1_ep56_c(12) <= ex1_ep56_g8(12) ; + ex1_ep56_c(11) <= ex1_ep56_g8(11) ; + ex1_ep56_c(10) <= ex1_ep56_g8(10) ; + ex1_ep56_c( 9) <= ex1_ep56_g8( 9) ; + ex1_ep56_c( 8) <= ex1_ep56_g8( 8) ; + ex1_ep56_c( 7) <= ex1_ep56_g8( 7) ; + ex1_ep56_c( 6) <= ex1_ep56_g8( 6) ; + ex1_ep56_c( 5) <= ex1_ep56_g8( 5) ; + ex1_ep56_c( 4) <= ex1_ep56_g8( 4) or (ex1_ep56_t8( 4) and ex1_ep56_g8(12)) ; + ex1_ep56_c( 3) <= ex1_ep56_g8( 3) or (ex1_ep56_t8( 3) and ex1_ep56_g8(11)) ; + ex1_ep56_c( 2) <= ex1_ep56_g8( 2) or (ex1_ep56_t8( 2) and ex1_ep56_g8(10)) ; + + + + + + ex1_p_expo_adj(1 to 13) <= + ( ex1_ep56_s(1 to 13) and (1 to 13 => not f_pic_ex1_fsel) ) or + ( ex1_c_expo(1 to 13) and (1 to 13 => f_pic_ex1_fsel) ); + + + + + ex1_from_k( 1) <= tidn; + ex1_from_k( 2) <= tidn; + ex1_from_k( 3) <= tiup; + ex1_from_k( 4) <= tidn; + ex1_from_k( 5) <= tidn; + ex1_from_k( 6) <= tiup; + ex1_from_k( 7) <= tidn; + ex1_from_k( 8) <= tiup; + ex1_from_k( 9) <= tidn; + ex1_from_k(10) <= tidn; + ex1_from_k(11) <= tidn; + ex1_from_k(12) <= tidn; + ex1_from_k(13) <= tiup; + + ex1_b_expo_adj(1 to 13) <= + ( ex1_from_k (1 to 13) and (1 to 13=> f_pic_ex1_from_integer ) ) or + ( ex1_b_expo (1 to 13) and (1 to 13=> not f_pic_ex1_from_integer ) ) ; + + + + + + + + ex1_wd_ge_bot <= ex1_b_expo( 9) and + ex1_b_expo(10) and + ex1_b_expo(11) and + ex1_b_expo(12) and + ex1_b_expo(13) ; + + ex1_dw_ge_bot <= ex1_b_expo( 8) and + ex1_wd_ge_bot ; + + ex1_ge_2048 <= not ex1_b_expo( 1) and ex1_b_expo( 2) ; + ex1_ge_1024 <= not ex1_b_expo( 1) and ex1_b_expo( 3) ; + + ex1_dw_ge_mid <= ex1_b_expo( 4) or + ex1_b_expo( 5) or + ex1_b_expo( 6) or + ex1_b_expo( 7) ; + + ex1_wd_ge_mid <= ex1_b_expo( 8) or + ex1_dw_ge_mid ; + + ex1_dw_ge <= ( ex1_ge_2048 ) or + ( ex1_ge_1024 and ex1_dw_ge_mid ) or + ( ex1_ge_1024 and ex1_dw_ge_bot ) ; + + ex1_wd_ge <= ( ex1_ge_2048 ) or + ( ex1_ge_1024 and ex1_wd_ge_mid ) or + ( ex1_ge_1024 and ex1_wd_ge_bot ) ; + + ex1_dw_eq_top <= not ex1_b_expo( 1) and + not ex1_b_expo( 2) and + ex1_b_expo( 3) and + not ex1_b_expo( 4) and + not ex1_b_expo( 5) and + not ex1_b_expo( 6) and + not ex1_b_expo( 7) ; + + ex1_wd_eq_bot <= ex1_b_expo( 9) and + ex1_b_expo(10) and + ex1_b_expo(11) and + ex1_b_expo(12) and + not ex1_b_expo(13) ; + + ex1_wd_eq <= ex1_dw_eq_top and + not ex1_b_expo( 8) and + ex1_wd_eq_bot ; + + ex1_dw_eq <= ex1_dw_eq_top and + ex1_b_expo( 8) and + ex1_wd_eq_bot ; + + + + + ex1_ge_bias <= + (not ex1_b_expo(1) and ex1_b_expo(2) ) or + (not ex1_b_expo(1) and ex1_b_expo(3) ) or + (not ex1_b_expo(1) and ex1_b_expo(4) and + ex1_b_expo(5) and + ex1_b_expo(6) and + ex1_b_expo(7) and + ex1_b_expo(8) and + ex1_b_expo(9) and + ex1_b_expo(10) and + ex1_b_expo(11) and + ex1_b_expo(12) and + ex1_b_expo(13) ); + + ex1_lt_bias <= not ex1_ge_bias; + ex1_eq_bias_m1 <= + not ex1_b_expo(1) and + not ex1_b_expo(2) and + not ex1_b_expo(3) and + ex1_b_expo(4) and + ex1_b_expo(5) and + ex1_b_expo(6) and + ex1_b_expo(7) and + ex1_b_expo(8) and + ex1_b_expo(9) and + ex1_b_expo(10) and + ex1_b_expo(11) and + ex1_b_expo(12) and + not ex1_b_expo(13) ; + + + + ex2_bop_lat: tri_rlmreg_p generic map (width=> 13, expand_type => expand_type, needs_sreset => 0) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(2) , + mpw1_b => mpw1_b(2) , + mpw2_b => mpw2_b(0) , + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => ex1_act, + scout => ex2_bop_so , + scin => ex2_bop_si , + din(0 to 12) => ex1_b_expo_adj (1 to 13) , + dout(0 to 12) => ex2_b_expo_adj (1 to 13) ); + + ex2_pop_lat: tri_rlmreg_p generic map (width=> 13, expand_type => expand_type, needs_sreset => 0) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(2) , + mpw1_b => mpw1_b(2) , + mpw2_b => mpw2_b(0) , + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => ex1_act, + scout => ex2_pop_so , + scin => ex2_pop_si , + din(0 to 12) => ex1_p_expo_adj (1 to 13) , + dout(0 to 12) => ex2_p_expo_adj (1 to 13) ); + + ex2_ctl_lat: tri_rlmreg_p generic map (width=> 7, expand_type => expand_type, needs_sreset => 0) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(2) , + mpw1_b => mpw1_b(2) , + mpw2_b => mpw2_b(0) , + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => ex1_act, + scout => ex2_ctl_so , + scin => ex2_ctl_si , + din(0) => ex1_dw_ge , + din(1) => ex1_wd_ge , + din(2) => ex1_wd_eq , + din(3) => ex1_dw_eq , + din(4) => f_pic_ex1_fsel, + din(5) => ex1_lt_bias , + din(6) => ex1_eq_bias_m1, + dout(0) => ex2_dw_ge , + dout(1) => ex2_wd_ge , + dout(2) => ex2_wd_eq , + dout(3) => ex2_dw_eq , + dout(4) => ex2_fsel , + dout(5) => ex2_lt_bias , + dout(6) => ex2_eq_bias_m1 ); + + f_eie_ex2_lt_bias <= ex2_lt_bias; + f_eie_ex2_eq_bias_m1 <= ex2_eq_bias_m1; + + ex2_p_expo(1 to 13) <= ex2_p_expo_adj (1 to 13); + ex2_b_expo(1 to 13) <= ex2_b_expo_adj (1 to 13); + + f_eie_ex2_wd_ov <= ex2_wd_ge ; + f_eie_ex2_dw_ov <= ex2_dw_ge ; + f_eie_ex2_wd_ov_if <= ex2_wd_eq ; + f_eie_ex2_dw_ov_if <= ex2_dw_eq ; + + f_eie_ex2_lzo_expo(1 to 13) <= ex2_p_expo_adj (1 to 13) ; + f_eie_ex2_b_expo(1 to 13) <= ex2_b_expo(1 to 13); + f_eie_ex2_tbl_expo(1 to 13) <= ex2_b_expo(1 to 13); + + + ex2_b_expo_fixed(1 to 13) <= ex2_b_expo(1 to 13) ; + + f_eie_ex2_use_bexp <= ex2_iexp_b_sel ; + + ex2_iexp_b_sel <= + (f_alg_ex2_sel_byp and not ex2_fsel and f_pic_ex2_math_bzer_b ) or + f_fmt_ex2_fsel_bsel or + f_pic_ex2_force_sel_bexp or + f_pic_ex2_frsp_ue1 ; + + ex2_iexp(1 to 13) <= + ( ex2_b_expo_fixed(1 to 13) and (1 to 13 => ex2_iexp_b_sel) ) or + ( ex2_p_expo(1 to 13) and (1 to 13 => not ex2_iexp_b_sel) ) ; + + + ex3_iexp_lat: tri_rlmreg_p generic map (width=> 14, expand_type => expand_type, needs_sreset => 0) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(3) , + mpw1_b => mpw1_b(3) , + mpw2_b => mpw2_b(0) , + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => ex2_act, + scout => ex3_iexp_so , + scin => ex3_iexp_si , + din(0) => f_pic_ex2_sp_b , + din(1 to 13) => ex2_iexp (1 to 13) , + dout(0) => ex3_sp_b , + dout(1 to 13) => ex3_iexp (1 to 13) ); + + + + + f_eie_ex3_iexp(1 to 13) <= ex3_iexp(1 to 13) ; + + + + + + ex2_bop_si (0 to 12) <= ex2_bop_so (1 to 12) & f_eie_si; + ex2_pop_si (0 to 12) <= ex2_pop_so (1 to 12) & ex2_bop_so (0); + ex2_ctl_si (0 to 6) <= ex2_ctl_so (1 to 6) & ex2_pop_so (0); + ex3_iexp_si (0 to 13) <= ex3_iexp_so (1 to 13) & ex2_ctl_so (0); + act_si (0 to 4) <= act_so (1 to 4) & ex3_iexp_so (0); + f_eie_so <= act_so (0); + + +end; + + + + + + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_eov.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_eov.vhdl new file mode 100644 index 0000000..80b1699 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_eov.vhdl @@ -0,0 +1,996 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + + +entity fuq_eov is +generic( expand_type : integer := 2 ); +port( + + + vdd :inout power_logic; + gnd :inout power_logic; + clkoff_b :in std_ulogic; + act_dis :in std_ulogic; + flush :in std_ulogic; + delay_lclkr :in std_ulogic_vector(4 to 5); + mpw1_b :in std_ulogic_vector(4 to 5); + mpw2_b :in std_ulogic_vector(0 to 1); + sg_1 :in std_ulogic; + thold_1 :in std_ulogic; + fpu_enable :in std_ulogic; + nclk :in clk_logic; + + + + f_eov_si :in std_ulogic ; + f_eov_so :out std_ulogic ; + ex2_act_b :in std_ulogic ; + + f_tbl_ex4_unf_expo :in std_ulogic ; + f_tbe_ex3_may_ov :in std_ulogic; + f_tbe_ex3_expo :in std_ulogic_vector(1 to 13) ; + f_pic_ex3_sel_est :in std_ulogic; + f_eie_ex3_iexp :in std_ulogic_vector(1 to 13) ; + + f_pic_ex3_sp_b :in std_ulogic ; + f_pic_ex4_oe :in std_ulogic ; + f_pic_ex4_ue :in std_ulogic ; + f_pic_ex4_ov_en :in std_ulogic ; + f_pic_ex4_uf_en :in std_ulogic ; + f_pic_ex4_spec_sel_k_e :in std_ulogic ; + f_pic_ex4_spec_sel_k_f :in std_ulogic ; + f_pic_ex4_sel_ov_spec :in std_ulogic ; + f_pic_ex4_to_int_ov_all :in std_ulogic ; + + f_lza_ex4_sh_rgt_en_eov :in std_ulogic; + f_lza_ex4_lza_amt_eov :in std_ulogic_vector(0 to 7) ; + f_lza_ex4_no_lza_edge :in std_ulogic ; + f_nrm_ex4_extra_shift :in std_ulogic ; + f_eov_ex4_may_ovf :out std_ulogic ; + + f_eov_ex5_sel_k_f :out std_ulogic ; + f_eov_ex5_sel_k_e :out std_ulogic ; + f_eov_ex5_sel_kif_f :out std_ulogic ; + f_eov_ex5_sel_kif_e :out std_ulogic ; + f_eov_ex5_unf_expo :out std_ulogic ; + f_eov_ex5_ovf_expo :out std_ulogic ; + f_eov_ex5_ovf_if_expo :out std_ulogic ; + f_eov_ex5_expo_p0 :out std_ulogic_vector(1 to 13) ; + f_eov_ex5_expo_p1 :out std_ulogic_vector(1 to 13) ; + f_eov_ex5_expo_p0_ue1oe1 :out std_ulogic_vector(3 to 7) ; + f_eov_ex5_expo_p1_ue1oe1 :out std_ulogic_vector(3 to 7) + +); + +-- synopsys translate_off + + + +-- synopsys translate_on + +end fuq_eov; + + +architecture fuq_eov of fuq_eov is + + constant tiup :std_ulogic := '1'; + constant tidn :std_ulogic := '0'; + + signal sg_0 :std_ulogic ; + signal thold_0_b, thold_0, forcee :std_ulogic ; + signal ex3_act :std_ulogic ; + signal ex2_act :std_ulogic ; + signal ex4_act :std_ulogic ; + signal act_spare_unused :std_ulogic_vector(0 to 2) ; + signal act_so :std_ulogic_vector(0 to 4) ; + signal act_si :std_ulogic_vector(0 to 4) ; + signal ex4_iexp_so :std_ulogic_vector(0 to 15) ; + signal ex4_iexp_si :std_ulogic_vector(0 to 15) ; + signal ex5_ovctl_so :std_ulogic_vector(0 to 2) ; + signal ex5_ovctl_si :std_ulogic_vector(0 to 2) ; + signal ex5_misc_so :std_ulogic_vector(0 to 12) ; + signal ex5_misc_si :std_ulogic_vector(0 to 12) ; + signal ex5_urnd0_so :std_ulogic_vector(0 to 12) ; + signal ex5_urnd0_si :std_ulogic_vector(0 to 12) ; + signal ex5_urnd1_so :std_ulogic_vector(0 to 12) ; + signal ex5_urnd1_si :std_ulogic_vector(0 to 12) ; + signal ex4_sp :std_ulogic ; + signal ex4_unf_m1_co12 :std_ulogic ; + signal ex4_unf_p0_co12 :std_ulogic ; + signal ex4_ovf_m1_co12 :std_ulogic ; + signal ex4_ovf_p0_co12 :std_ulogic ; + signal ex4_ovf_p1_co12 :std_ulogic ; + signal ex4_ovf_m1 :std_ulogic ; + signal ex4_ovf_p0 :std_ulogic ; + signal ex4_ovf_p1 :std_ulogic ; + signal ex4_unf_m1 :std_ulogic ; + signal ex4_unf_p0 :std_ulogic ; + + + signal ex4_i_exp :std_ulogic_vector(1 to 13) ; + signal ex4_ue1oe1_k :std_ulogic_vector(3 to 7) ; + signal ex4_lzasub_sum :std_ulogic_vector(1 to 13) ; + signal ex4_lzasub_car :std_ulogic_vector(1 to 12) ; + signal ex4_lzasub_p :std_ulogic_vector(1 to 12) ; + signal ex4_lzasub_t :std_ulogic_vector(2 to 12) ; + signal ex4_lzasub_g :std_ulogic_vector(2 to 12) ; + signal ex4_lzasub_m1 :std_ulogic_vector(1 to 13) ; + signal ex4_lzasub_p0 :std_ulogic_vector(1 to 13) ; + signal ex4_lzasub_p1 :std_ulogic_vector(1 to 13) ; + signal ex4_lzasub_c0 :std_ulogic_vector(2 to 11) ; + signal ex4_lzasub_c1 :std_ulogic_vector(2 to 11) ; + signal ex4_lzasub_s0 :std_ulogic_vector(1 to 11) ; + signal ex4_lzasub_s1 :std_ulogic_vector(1 to 11) ; + signal ex4_ovf_sum :std_ulogic_vector(1 to 13) ; + signal ex4_ovf_car :std_ulogic_vector(1 to 12) ; + signal ex4_ovf_g :std_ulogic_vector(2 to 12) ; + signal ex4_ovf_t :std_ulogic_vector(2 to 12) ; + signal ex4_ovf_p :std_ulogic_vector(1 to 1) ; + signal ex4_unf_sum :std_ulogic_vector(1 to 13) ; + signal ex4_unf_car :std_ulogic_vector(1 to 12) ; + signal ex4_unf_g :std_ulogic_vector(2 to 12) ; + signal ex4_unf_t :std_ulogic_vector(2 to 12) ; + signal ex4_unf_p :std_ulogic_vector(1 to 1) ; + signal ex4_unf_ci0_02t11 :std_ulogic; + signal ex4_unf_ci1_02t11 :std_ulogic; + signal ex4_expo_p0 :std_ulogic_vector(1 to 13) ; + signal ex4_expo_p1 :std_ulogic_vector(1 to 13) ; + signal ex5_expo_p0 :std_ulogic_vector(1 to 13) ; + signal ex5_expo_p1 :std_ulogic_vector(1 to 13) ; + signal ex5_ue1oe1_k :std_ulogic_vector(3 to 7) ; + signal ex5_ue1oe1_p0_p :std_ulogic_vector(3 to 7) ; + signal ex5_ue1oe1_p0_t :std_ulogic_vector(4 to 6) ; + signal ex5_ue1oe1_p0_g :std_ulogic_vector(4 to 7) ; + signal ex5_ue1oe1_p0_c :std_ulogic_vector(4 to 7) ; + signal ex5_ue1oe1_p1_p :std_ulogic_vector(3 to 7) ; + signal ex5_ue1oe1_p1_t :std_ulogic_vector(4 to 6) ; + signal ex5_ue1oe1_p1_g :std_ulogic_vector(4 to 7) ; + signal ex5_ue1oe1_p1_c :std_ulogic_vector(4 to 7) ; + signal ex4_lzasub_m1_c12 :std_ulogic ; + signal ex4_lzasub_p0_c12 :std_ulogic ; + signal ex4_lzasub_p1_c12 :std_ulogic ; + signal ex4_may_ovf :std_ulogic ; + signal ex4_lza_amt_b :std_ulogic_vector(0 to 7) ; + signal ex4_lza_amt :std_ulogic_vector(0 to 7) ; + signal ex3_iexp :std_ulogic_vector(1 to 13) ; + signal ex3_sp :std_ulogic ; + signal ex3_may_ovf :std_ulogic ; + signal ex4_unf_c2_m1 :std_ulogic; + signal ex4_unf_c2_p0 :std_ulogic; + signal ex4_c2_m1 :std_ulogic; + signal ex4_c2_p0 :std_ulogic; + signal ex4_c2_p1 :std_ulogic; + signal ex5_ue1oe1_p0_g2_b :std_ulogic_vector(4 to 7); + signal ex5_ue1oe1_p0_t2_b :std_ulogic_vector(4 to 5); + signal ex5_ue1oe1_p1_g2_b :std_ulogic_vector(4 to 7); + signal ex5_ue1oe1_p1_t2_b :std_ulogic_vector(4 to 5); + signal ex4_unf_g2_02t03 :std_ulogic; + signal ex4_unf_g2_04t05 :std_ulogic; + signal ex4_unf_g2_06t07 :std_ulogic; + signal ex4_unf_g2_08t09 :std_ulogic; + signal ex4_unf_g2_10t11 :std_ulogic; + signal ex4_unf_ci0_g2 :std_ulogic; + signal ex4_unf_ci1_g2 :std_ulogic; + signal ex4_unf_t2_02t03 :std_ulogic; + signal ex4_unf_t2_04t05 :std_ulogic; + signal ex4_unf_t2_06t07 :std_ulogic; + signal ex4_unf_t2_08t09 :std_ulogic; + signal ex4_unf_t2_10t11 :std_ulogic; + signal ex4_unf_g4_02t05 :std_ulogic; + signal ex4_unf_g4_06t09 :std_ulogic; + signal ex4_unf_ci0_g4 :std_ulogic; + signal ex4_unf_ci1_g4 :std_ulogic; + signal ex4_unf_t4_02t05 :std_ulogic; + signal ex4_unf_t4_06t09 :std_ulogic; + signal ex4_unf_g8_02t09 :std_ulogic; + signal ex4_unf_ci0_g8 :std_ulogic; + signal ex4_unf_ci1_g8 :std_ulogic; + signal ex4_unf_t8_02t09 :std_ulogic; + + signal ex4_ovf_ci0_02t11 :std_ulogic; + signal ex4_ovf_ci1_02t11 :std_ulogic; + + signal ex4_ovf_g2_02t03 :std_ulogic; + signal ex4_ovf_g2_04t05 :std_ulogic; + signal ex4_ovf_g2_06t07 :std_ulogic; + signal ex4_ovf_g2_08t09 :std_ulogic; + signal ex4_ovf_g2_ci0 :std_ulogic; + signal ex4_ovf_g2_ci1 :std_ulogic; + signal ex4_ovf_t2_02t03 :std_ulogic; + signal ex4_ovf_t2_04t05 :std_ulogic; + signal ex4_ovf_t2_06t07 :std_ulogic; + signal ex4_ovf_t2_08t09 :std_ulogic; + signal ex4_ovf_g4_02t05 :std_ulogic; + signal ex4_ovf_g4_06t09 :std_ulogic; + signal ex4_ovf_g4_ci0 :std_ulogic; + signal ex4_ovf_g4_ci1 :std_ulogic; + signal ex4_ovf_t4_02t05 :std_ulogic; + signal ex4_ovf_t4_06t09 :std_ulogic; + signal ex4_ovf_g8_02t09 :std_ulogic; + signal ex4_ovf_g8_ci0 :std_ulogic; + signal ex4_ovf_g8_ci1 :std_ulogic; + signal ex4_ovf_t8_02t09 :std_ulogic; + + signal ex4_lzasub_gg02 :std_ulogic_vector(2 to 11); + signal ex4_lzasub_gt02 :std_ulogic_vector(2 to 11); + signal ex4_lzasub_gg04 :std_ulogic_vector(2 to 11); + signal ex4_lzasub_gt04 :std_ulogic_vector(2 to 11); + signal ex4_lzasub_gg08 :std_ulogic_vector(2 to 11); + signal ex4_lzasub_gt08 :std_ulogic_vector(2 to 11); + signal ex4_sh_rgt_en_b :std_ulogic; + + signal ex3_may_ov_usual :std_ulogic; + + + + signal ex4_ovf_calc :std_ulogic; + signal ex4_ovf_if_calc :std_ulogic; + signal ex4_unf_calc :std_ulogic; + signal ex4_unf_tbl :std_ulogic; + signal ex4_unf_tbl_spec_e :std_ulogic; + signal ex4_ov_en :std_ulogic; + signal ex4_ov_en_oe0 :std_ulogic; + signal ex4_sel_ov_spec :std_ulogic; + signal ex4_unf_en_nedge :std_ulogic; + signal ex4_unf_ue0_nestsp :std_ulogic; + signal ex4_sel_k_part_f :std_ulogic; + signal ex4_sel_k_part_e :std_ulogic; + signal ex5_ovf_calc :std_ulogic; + signal ex5_ovf_if_calc :std_ulogic; + signal ex5_unf_calc :std_ulogic; + signal ex5_unf_tbl :std_ulogic; + signal ex5_unf_tbl_b :std_ulogic; + signal ex5_unf_tbl_spec_e :std_ulogic; + signal ex5_ov_en :std_ulogic; + signal ex5_ov_en_oe0 :std_ulogic; + signal ex5_sel_ov_spec :std_ulogic; + signal ex5_unf_en_nedge :std_ulogic; + signal ex5_unf_ue0_nestsp :std_ulogic; + signal ex5_sel_k_part_f :std_ulogic; + signal ex5_sel_ov_spec_b :std_ulogic; + signal ex5_ovf_b :std_ulogic; + signal ex5_ovf_if_b :std_ulogic; + signal ex5_ovf_oe0_b :std_ulogic; + signal ex5_ovf_if_oe0_b :std_ulogic; + signal ex5_unf_b :std_ulogic; + signal ex5_unf_ue0_b :std_ulogic; + signal ex5_sel_k_part_f_b :std_ulogic; + signal ex5_unf_tbl_spec_e_b :std_ulogic; + signal ex4_sel_est :std_ulogic; + signal ex4_est_sp :std_ulogic; + +signal ex4_expo_p0_0_b, ex4_expo_p0_1_b, ex4_expo_p1_0_b, ex4_expo_p1_1_b :std_ulogic_vector(1 to 13) ; +signal ex4_ovf_calc_0_b, ex4_ovf_calc_1_b, ex4_ovf_if_calc_0_b, ex4_ovf_if_calc_1_b, ex4_unf_calc_0_b, ex4_unf_calc_1_b :std_ulogic ; + signal ex5_d1clk, ex5_d2clk :std_ulogic ; + signal ex5_lclk :clk_logic; + signal unused :std_ulogic ; + +-- synopsys translate_off + +-- synopsys translate_on + + +begin + +unused <= + or_reduce( ex4_expo_p0(1 to 13) ) or + or_reduce( ex4_expo_p1(1 to 13) ) or + ex4_ovf_calc or + ex4_ovf_if_calc or + ex4_unf_calc ; + + + thold_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => thold_1, + q(0) => thold_0 ); + + sg_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => sg_1 , + q(0) => sg_0 ); + + + lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map ( + clkoff_b => clkoff_b, + thold => thold_0, + sg => sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => thold_0_b ); + + ex5_lcb : tri_lcbnd generic map (expand_type => expand_type) port map( + delay_lclkr => delay_lclkr(5) , + mpw1_b => mpw1_b(5) , + mpw2_b => mpw2_b(1) , + forcee => forcee, + nclk => nclk , + vd => vdd , + gd => gnd , + act => ex4_act , + sg => sg_0 , + thold_b => thold_0_b , + d1clk => ex5_d1clk , + d2clk => ex5_d2clk , + lclk => ex5_lclk ); + + + + + ex2_act <= not ex2_act_b; + + act_lat: tri_rlmreg_p generic map (width=> 5, expand_type => expand_type, needs_sreset => 0) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(4) , + mpw1_b => mpw1_b(4) , + mpw2_b => mpw2_b(0) , + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => fpu_enable, + scout => act_so , + scin => act_si , + din(0) => act_spare_unused(0), + din(1) => act_spare_unused(1), + din(2) => ex2_act, + din(3) => ex3_act, + din(4) => act_spare_unused(2), + dout(0) => act_spare_unused(0), + dout(1) => act_spare_unused(1), + dout(2) => ex3_act, + dout(3) => ex4_act, + dout(4) => act_spare_unused(2) ); + + + + ex3_iexp(1 to 13) <= + ( (1 to 13=> not f_pic_ex3_sel_est) and f_eie_ex3_iexp(1 to 13) ) or + ( (1 to 13=> f_pic_ex3_sel_est) and f_tbe_ex3_expo(1 to 13) ) ; + + ex3_sp <= not f_pic_ex3_sp_b; + + + + + ex3_may_ovf <= + ( ex3_may_ov_usual and not f_pic_ex3_sel_est) or + ( f_tbe_ex3_may_ov and f_pic_ex3_sel_est); + + ex3_may_ov_usual <= + (not f_eie_ex3_iexp(1) and f_eie_ex3_iexp(2) ) or + (not f_eie_ex3_iexp(1) and f_eie_ex3_iexp(3) and f_eie_ex3_iexp(4) ) or + (not f_eie_ex3_iexp(1) and f_eie_ex3_iexp(3) and f_eie_ex3_iexp(5) ) or + (not f_eie_ex3_iexp(1) and f_eie_ex3_iexp(3) and f_eie_ex3_iexp(6) ) or + (not f_eie_ex3_iexp(1) and f_eie_ex3_iexp(3) and f_eie_ex3_iexp(7) ) or + (not f_eie_ex3_iexp(1) and f_eie_ex3_iexp(3) and f_eie_ex3_iexp(8) and f_eie_ex3_iexp(9) ); + + + ex4_iexp_lat: tri_rlmreg_p generic map (width=> 16, expand_type => expand_type, needs_sreset => 0) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(4) , + mpw1_b => mpw1_b(4) , + mpw2_b => mpw2_b(0) , + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => ex3_act, + scout => ex4_iexp_so , + scin => ex4_iexp_si , + din(0) => ex3_sp , + din(1 to 13) => ex3_iexp(1 to 13) , + din(14) => ex3_may_ovf , + din(15) => f_pic_ex3_sel_est, + dout(0) => ex4_sp , + dout(1 to 13) => ex4_i_exp(1 to 13) , + dout(14) => ex4_may_ovf , + dout(15) => ex4_sel_est ); + + f_eov_ex4_may_ovf <= ex4_may_ovf; + + + + ex4_ue1oe1_k(3) <= (not ex4_may_ovf and not ex4_sp) or + ( ex4_may_ovf and ex4_sp) ; + + ex4_ue1oe1_k(4) <= ( not ex4_sp) or + ( ex4_may_ovf and ex4_sp) ; + + ex4_ue1oe1_k(5) <= ( ex4_may_ovf and ex4_sp) ; + + ex4_ue1oe1_k(6) <= (not ex4_may_ovf and ex4_sp) ; + ex4_ue1oe1_k(7) <= ( ex4_sp) ; + + + + + ex4_lza_amt_b(0 to 7) <= not f_lza_ex4_lza_amt_eov(0 to 7); + ex4_lza_amt (0 to 7) <= f_lza_ex4_lza_amt_eov(0 to 7); + ex4_sh_rgt_en_b <= not f_lza_ex4_sh_rgt_en_eov; + + ex4_lzasub_sum( 1) <= ex4_sh_rgt_en_b xor ex4_i_exp( 1); + ex4_lzasub_sum( 2) <= ex4_sh_rgt_en_b xor ex4_i_exp( 2); + ex4_lzasub_sum( 3) <= ex4_sh_rgt_en_b xor ex4_i_exp( 3); + ex4_lzasub_sum( 4) <= ex4_sh_rgt_en_b xor ex4_i_exp( 4); + ex4_lzasub_sum( 5) <= ex4_sh_rgt_en_b xor ex4_i_exp( 5); + ex4_lzasub_sum( 6) <= ex4_lza_amt_b(0) xor ex4_i_exp( 6); + ex4_lzasub_sum( 7) <= ex4_lza_amt_b(1) xor ex4_i_exp( 7); + ex4_lzasub_sum( 8) <= ex4_lza_amt_b(2) xor ex4_i_exp( 8); + ex4_lzasub_sum( 9) <= ex4_lza_amt_b(3) xor ex4_i_exp( 9); + ex4_lzasub_sum(10) <= ex4_lza_amt_b(4) xor ex4_i_exp(10); + ex4_lzasub_sum(11) <= ex4_lza_amt_b(5) xor ex4_i_exp(11); + ex4_lzasub_sum(12) <= ex4_lza_amt_b(6) xor ex4_i_exp(12); + ex4_lzasub_sum(13) <= not( ex4_lza_amt_b(7) xor ex4_i_exp(13) ); + + ex4_lzasub_car( 1) <= ex4_sh_rgt_en_b and ex4_i_exp( 2); + ex4_lzasub_car( 2) <= ex4_sh_rgt_en_b and ex4_i_exp( 3); + ex4_lzasub_car( 3) <= ex4_sh_rgt_en_b and ex4_i_exp( 4); + ex4_lzasub_car( 4) <= ex4_sh_rgt_en_b and ex4_i_exp( 5); + ex4_lzasub_car( 5) <= ex4_lza_amt_b(0) and ex4_i_exp( 6); + ex4_lzasub_car( 6) <= ex4_lza_amt_b(1) and ex4_i_exp( 7); + ex4_lzasub_car( 7) <= ex4_lza_amt_b(2) and ex4_i_exp( 8); + ex4_lzasub_car( 8) <= ex4_lza_amt_b(3) and ex4_i_exp( 9); + ex4_lzasub_car( 9) <= ex4_lza_amt_b(4) and ex4_i_exp(10); + ex4_lzasub_car(10) <= ex4_lza_amt_b(5) and ex4_i_exp(11); + ex4_lzasub_car(11) <= ex4_lza_amt_b(6) and ex4_i_exp(12); + ex4_lzasub_car(12) <= ex4_lza_amt_b(7) or ex4_i_exp(13); + + ex4_lzasub_p(1 to 12) <= ex4_lzasub_car(1 to 12) xor ex4_lzasub_sum(1 to 12); + ex4_lzasub_t(2 to 12) <= ex4_lzasub_car(2 to 12) or ex4_lzasub_sum(2 to 12); + ex4_lzasub_g(2 to 12) <= ex4_lzasub_car(2 to 12) and ex4_lzasub_sum(2 to 12); + + + + ex4_lzasub_m1_c12 <= ex4_lzasub_g(12); + ex4_lzasub_p0_c12 <= ex4_lzasub_g(12) or (ex4_lzasub_t(12) and ex4_lzasub_sum(13) ); + ex4_lzasub_p1_c12 <= ex4_lzasub_t(12); + + ex4_lzasub_m1(13) <= ex4_lzasub_sum(13); + ex4_lzasub_p0(13) <= not ex4_lzasub_sum(13); + ex4_lzasub_p1(13) <= ex4_lzasub_sum(13); + + ex4_lzasub_m1(12) <= ex4_lzasub_p(12); + ex4_lzasub_p0(12) <= ex4_lzasub_p(12) xor ex4_lzasub_sum(13); + ex4_lzasub_p1(12) <= not ex4_lzasub_p(12); + + + + + ex4_lzasub_gg02(11) <= ex4_lzasub_g(11) ; + ex4_lzasub_gg02(10) <= ex4_lzasub_g(10) or ( ex4_lzasub_t(10) and ex4_lzasub_g(11) ); + ex4_lzasub_gg02( 9) <= ex4_lzasub_g( 9) or ( ex4_lzasub_t( 9) and ex4_lzasub_g(10) ); + ex4_lzasub_gg02( 8) <= ex4_lzasub_g( 8) or ( ex4_lzasub_t( 8) and ex4_lzasub_g( 9) ); + ex4_lzasub_gg02( 7) <= ex4_lzasub_g( 7) or ( ex4_lzasub_t( 7) and ex4_lzasub_g( 8) ); + ex4_lzasub_gg02( 6) <= ex4_lzasub_g( 6) or ( ex4_lzasub_t( 6) and ex4_lzasub_g( 7) ); + ex4_lzasub_gg02( 5) <= ex4_lzasub_g( 5) or ( ex4_lzasub_t( 5) and ex4_lzasub_g( 6) ); + ex4_lzasub_gg02( 4) <= ex4_lzasub_g( 4) or ( ex4_lzasub_t( 4) and ex4_lzasub_g( 5) ); + ex4_lzasub_gg02( 3) <= ex4_lzasub_g( 3) or ( ex4_lzasub_t( 3) and ex4_lzasub_g( 4) ); + ex4_lzasub_gg02( 2) <= ex4_lzasub_g( 2) or ( ex4_lzasub_t( 2) and ex4_lzasub_g( 3) ); + + ex4_lzasub_gt02(11) <= ex4_lzasub_t(11) ; + ex4_lzasub_gt02(10) <= ex4_lzasub_g(10) or ( ex4_lzasub_t(10) and ex4_lzasub_t(11) ); + ex4_lzasub_gt02( 9) <= ( ex4_lzasub_t( 9) and ex4_lzasub_t(10) ); + ex4_lzasub_gt02( 8) <= ( ex4_lzasub_t( 8) and ex4_lzasub_t( 9) ); + ex4_lzasub_gt02( 7) <= ( ex4_lzasub_t( 7) and ex4_lzasub_t( 8) ); + ex4_lzasub_gt02( 6) <= ( ex4_lzasub_t( 6) and ex4_lzasub_t( 7) ); + ex4_lzasub_gt02( 5) <= ( ex4_lzasub_t( 5) and ex4_lzasub_t( 6) ); + ex4_lzasub_gt02( 4) <= ( ex4_lzasub_t( 4) and ex4_lzasub_t( 5) ); + ex4_lzasub_gt02( 3) <= ( ex4_lzasub_t( 3) and ex4_lzasub_t( 4) ); + ex4_lzasub_gt02( 2) <= ( ex4_lzasub_t( 2) and ex4_lzasub_t( 3) ); + + ex4_lzasub_gg04(11) <= ex4_lzasub_gg02(11) ; + ex4_lzasub_gg04(10) <= ex4_lzasub_gg02(10) ; + ex4_lzasub_gg04( 9) <= ex4_lzasub_gg02( 9) or ( ex4_lzasub_gt02( 9) and ex4_lzasub_gg02(11) ); + ex4_lzasub_gg04( 8) <= ex4_lzasub_gg02( 8) or ( ex4_lzasub_gt02( 8) and ex4_lzasub_gg02(10) ); + ex4_lzasub_gg04( 7) <= ex4_lzasub_gg02( 7) or ( ex4_lzasub_gt02( 7) and ex4_lzasub_gg02( 9) ); + ex4_lzasub_gg04( 6) <= ex4_lzasub_gg02( 6) or ( ex4_lzasub_gt02( 6) and ex4_lzasub_gg02( 8) ); + ex4_lzasub_gg04( 5) <= ex4_lzasub_gg02( 5) or ( ex4_lzasub_gt02( 5) and ex4_lzasub_gg02( 7) ); + ex4_lzasub_gg04( 4) <= ex4_lzasub_gg02( 4) or ( ex4_lzasub_gt02( 4) and ex4_lzasub_gg02( 6) ); + ex4_lzasub_gg04( 3) <= ex4_lzasub_gg02( 3) or ( ex4_lzasub_gt02( 3) and ex4_lzasub_gg02( 5) ); + ex4_lzasub_gg04( 2) <= ex4_lzasub_gg02( 2) or ( ex4_lzasub_gt02( 2) and ex4_lzasub_gg02( 4) ); + + ex4_lzasub_gt04(11) <= ex4_lzasub_gt02(11) ; + ex4_lzasub_gt04(10) <= ex4_lzasub_gt02(10) ; + ex4_lzasub_gt04( 9) <= ex4_lzasub_gg02( 9) or ( ex4_lzasub_gt02( 9) and ex4_lzasub_gt02(11) ); + ex4_lzasub_gt04( 8) <= ex4_lzasub_gg02( 8) or ( ex4_lzasub_gt02( 8) and ex4_lzasub_gt02(10) ); + ex4_lzasub_gt04( 7) <= ( ex4_lzasub_gt02( 7) and ex4_lzasub_gt02( 9) ); + ex4_lzasub_gt04( 6) <= ( ex4_lzasub_gt02( 6) and ex4_lzasub_gt02( 8) ); + ex4_lzasub_gt04( 5) <= ( ex4_lzasub_gt02( 5) and ex4_lzasub_gt02( 7) ); + ex4_lzasub_gt04( 4) <= ( ex4_lzasub_gt02( 4) and ex4_lzasub_gt02( 6) ); + ex4_lzasub_gt04( 3) <= ( ex4_lzasub_gt02( 3) and ex4_lzasub_gt02( 5) ); + ex4_lzasub_gt04( 2) <= ( ex4_lzasub_gt02( 2) and ex4_lzasub_gt02( 4) ); + + + ex4_lzasub_gg08(11) <= ex4_lzasub_gg04(11) ; + ex4_lzasub_gg08(10) <= ex4_lzasub_gg04(10) ; + ex4_lzasub_gg08( 9) <= ex4_lzasub_gg04( 9) ; + ex4_lzasub_gg08( 8) <= ex4_lzasub_gg04( 8) ; + ex4_lzasub_gg08( 7) <= ex4_lzasub_gg04( 7) or ( ex4_lzasub_gt04( 7) and ex4_lzasub_gg04(11) ); + ex4_lzasub_gg08( 6) <= ex4_lzasub_gg04( 6) or ( ex4_lzasub_gt04( 6) and ex4_lzasub_gg04(10) ); + ex4_lzasub_gg08( 5) <= ex4_lzasub_gg04( 5) or ( ex4_lzasub_gt04( 5) and ex4_lzasub_gg04( 9) ); + ex4_lzasub_gg08( 4) <= ex4_lzasub_gg04( 4) or ( ex4_lzasub_gt04( 4) and ex4_lzasub_gg04( 8) ); + ex4_lzasub_gg08( 3) <= ex4_lzasub_gg04( 3) or ( ex4_lzasub_gt04( 3) and ex4_lzasub_gg04( 7) ); + ex4_lzasub_gg08( 2) <= ex4_lzasub_gg04( 2) or ( ex4_lzasub_gt04( 2) and ex4_lzasub_gg04( 6) ); + + ex4_lzasub_gt08(11) <= ex4_lzasub_gt04(11) ; + ex4_lzasub_gt08(10) <= ex4_lzasub_gt04(10) ; + ex4_lzasub_gt08( 9) <= ex4_lzasub_gt04( 9) ; + ex4_lzasub_gt08( 8) <= ex4_lzasub_gt04( 8) ; + ex4_lzasub_gt08( 7) <= ex4_lzasub_gg04( 7) or ( ex4_lzasub_gt04( 7) and ex4_lzasub_gt04(11) ); + ex4_lzasub_gt08( 6) <= ex4_lzasub_gg04( 6) or ( ex4_lzasub_gt04( 6) and ex4_lzasub_gt04(10) ); + ex4_lzasub_gt08( 5) <= ex4_lzasub_gg04( 5) or ( ex4_lzasub_gt04( 5) and ex4_lzasub_gt04( 9) ); + ex4_lzasub_gt08( 4) <= ex4_lzasub_gg04( 4) or ( ex4_lzasub_gt04( 4) and ex4_lzasub_gt04( 8) ); + ex4_lzasub_gt08( 3) <= ( ex4_lzasub_gt04( 3) and ex4_lzasub_gt04( 7) ); + ex4_lzasub_gt08( 2) <= ( ex4_lzasub_gt04( 2) and ex4_lzasub_gt04( 6) ); + + + ex4_lzasub_c0(11) <= ex4_lzasub_gg08(11) ; + ex4_lzasub_c0(10) <= ex4_lzasub_gg08(10) ; + ex4_lzasub_c0( 9) <= ex4_lzasub_gg08( 9) ; + ex4_lzasub_c0( 8) <= ex4_lzasub_gg08( 8) ; + ex4_lzasub_c0( 7) <= ex4_lzasub_gg08( 7) ; + ex4_lzasub_c0( 6) <= ex4_lzasub_gg08( 6) ; + ex4_lzasub_c0( 5) <= ex4_lzasub_gg08( 5) ; + ex4_lzasub_c0( 4) <= ex4_lzasub_gg08( 4) ; + ex4_lzasub_c0( 3) <= ex4_lzasub_gg08( 3) or ( ex4_lzasub_gt08( 3) and ex4_lzasub_gg08(11) ); + ex4_lzasub_c0( 2) <= ex4_lzasub_gg08( 2) or ( ex4_lzasub_gt08( 2) and ex4_lzasub_gg08(10) ); + + ex4_lzasub_c1(11) <= ex4_lzasub_gt08(11) ; + ex4_lzasub_c1(10) <= ex4_lzasub_gt08(10) ; + ex4_lzasub_c1( 9) <= ex4_lzasub_gt08( 9) ; + ex4_lzasub_c1( 8) <= ex4_lzasub_gt08( 8) ; + ex4_lzasub_c1( 7) <= ex4_lzasub_gt08( 7) ; + ex4_lzasub_c1( 6) <= ex4_lzasub_gt08( 6) ; + ex4_lzasub_c1( 5) <= ex4_lzasub_gt08( 5) ; + ex4_lzasub_c1( 4) <= ex4_lzasub_gt08( 4) ; + ex4_lzasub_c1( 3) <= ex4_lzasub_gg08( 3) or ( ex4_lzasub_gt08( 3) and ex4_lzasub_gt08(11) ); + ex4_lzasub_c1( 2) <= ex4_lzasub_gg08( 2) or ( ex4_lzasub_gt08( 2) and ex4_lzasub_gt08(10) ); + + + + + + ex4_lzasub_s0(1 to 11) <= ex4_lzasub_p(1 to 11) xor (ex4_lzasub_c0(2 to 11) & tidn) ; + ex4_lzasub_s1(1 to 11) <= ex4_lzasub_p(1 to 11) xor (ex4_lzasub_c1(2 to 11) & tiup) ; + + ex4_lzasub_m1(1 to 11) <= + (ex4_lzasub_s0(1 to 11) and (1 to 11 => not ex4_lzasub_m1_c12) ) or + (ex4_lzasub_s1(1 to 11) and (1 to 11 => ex4_lzasub_m1_c12) ); + + ex4_lzasub_p0(1 to 11) <= + (ex4_lzasub_s0(1 to 11) and (1 to 11 => not ex4_lzasub_p0_c12) ) or + (ex4_lzasub_s1(1 to 11) and (1 to 11 => ex4_lzasub_p0_c12) ); + + ex4_lzasub_p1(1 to 11) <= + (ex4_lzasub_s0(1 to 11) and (1 to 11 => not ex4_lzasub_p1_c12) ) or + (ex4_lzasub_s1(1 to 11) and (1 to 11 => ex4_lzasub_p1_c12) ); + + + + ex4_ovf_sum( 1) <= ex4_sh_rgt_en_b xor not ex4_i_exp( 1); + ex4_ovf_sum( 2) <= ex4_sh_rgt_en_b xor not ex4_i_exp( 2); + ex4_ovf_sum( 3) <= ex4_sh_rgt_en_b xor ex4_i_exp( 3); + ex4_ovf_sum( 4) <= ex4_sh_rgt_en_b xor ex4_i_exp( 4) xor ex4_sp; + ex4_ovf_sum( 5) <= ex4_sh_rgt_en_b xor ex4_i_exp( 5) xor ex4_sp; + ex4_ovf_sum( 6) <= not ex4_lza_amt(0) xor ex4_i_exp( 6) xor ex4_sp; + ex4_ovf_sum( 7) <= not ex4_lza_amt(1) xor ex4_i_exp( 7); + ex4_ovf_sum( 8) <= not ex4_lza_amt(2) xor ex4_i_exp( 8); + ex4_ovf_sum( 9) <= not ex4_lza_amt(3) xor ex4_i_exp( 9); + ex4_ovf_sum(10) <= not ex4_lza_amt(4) xor ex4_i_exp(10); + ex4_ovf_sum(11) <= not ex4_lza_amt(5) xor ex4_i_exp(11); + ex4_ovf_sum(12) <= not ex4_lza_amt(6) xor not ex4_i_exp(12); + ex4_ovf_sum(13) <= not ex4_lza_amt(7) xor ex4_i_exp(13); + + ex4_ovf_car( 1) <= ex4_sh_rgt_en_b or ex4_i_exp( 2); + ex4_ovf_car( 2) <= ex4_sh_rgt_en_b and ex4_i_exp( 3); + + ex4_ovf_car( 3) <= ( ex4_sp and ex4_i_exp( 4) ) or + ( ex4_sh_rgt_en_b and ex4_i_exp( 4) ) or + ( ex4_sh_rgt_en_b and ex4_sp ) ; + + ex4_ovf_car( 4) <= ( ex4_sp and ex4_i_exp( 5) ) or + ( ex4_sh_rgt_en_b and ex4_i_exp( 5) ) or + ( ex4_sh_rgt_en_b and ex4_sp ) ; + + ex4_ovf_car( 5) <= (not ex4_lza_amt(0) and ex4_i_exp( 6) ) or + (not ex4_lza_amt(0) and ex4_sp ) or + ( ex4_sp and ex4_i_exp( 6) ) ; + ex4_ovf_car( 6) <= not ex4_lza_amt(1) and ex4_i_exp( 7); + ex4_ovf_car( 7) <= not ex4_lza_amt(2) and ex4_i_exp( 8); + ex4_ovf_car( 8) <= not ex4_lza_amt(3) and ex4_i_exp( 9); + ex4_ovf_car( 9) <= not ex4_lza_amt(4) and ex4_i_exp(10); + ex4_ovf_car(10) <= not ex4_lza_amt(5) and ex4_i_exp(11); + ex4_ovf_car(11) <= not ex4_lza_amt(6) or ex4_i_exp(12); + ex4_ovf_car(12) <= not ex4_lza_amt(7) and ex4_i_exp(13); + + + + ex4_ovf_g(2 to 12) <= ex4_ovf_car(2 to 12) and ex4_ovf_sum(2 to 12); + ex4_ovf_t(2 to 12) <= ex4_ovf_car(2 to 12) or ex4_ovf_sum(2 to 12); + ex4_ovf_p(1) <= ex4_ovf_car(1) xor ex4_ovf_sum(1) ; + + + ex4_ovf_m1_co12 <= ex4_ovf_g(12); + ex4_ovf_p0_co12 <= ex4_ovf_g(12) or (ex4_ovf_t(12) and ex4_ovf_sum(13) ); + ex4_ovf_p1_co12 <= ex4_ovf_t(12); + + + + ex4_ovf_g2_02t03 <= ex4_ovf_g( 2) or (ex4_ovf_t( 2) and ex4_ovf_g( 3) ); + ex4_ovf_g2_04t05 <= ex4_ovf_g( 4) or (ex4_ovf_t( 4) and ex4_ovf_g( 5) ); + ex4_ovf_g2_06t07 <= ex4_ovf_g( 6) or (ex4_ovf_t( 6) and ex4_ovf_g( 7) ); + ex4_ovf_g2_08t09 <= ex4_ovf_g( 8) or (ex4_ovf_t( 8) and ex4_ovf_g( 9) ); + ex4_ovf_g2_ci0 <= ex4_ovf_g(10) or (ex4_ovf_t(10) and ex4_ovf_g(11) ); + ex4_ovf_g2_ci1 <= ex4_ovf_g(10) or (ex4_ovf_t(10) and ex4_ovf_t(11) ); + + ex4_ovf_t2_02t03 <= (ex4_ovf_t( 2) and ex4_ovf_t( 3) ); + ex4_ovf_t2_04t05 <= (ex4_ovf_t( 4) and ex4_ovf_t( 5) ); + ex4_ovf_t2_06t07 <= (ex4_ovf_t( 6) and ex4_ovf_t( 7) ); + ex4_ovf_t2_08t09 <= (ex4_ovf_t( 8) and ex4_ovf_t( 9) ); + + ex4_ovf_g4_02t05 <= ex4_ovf_g2_02t03 or ( ex4_ovf_t2_02t03 and ex4_ovf_g2_04t05 ); + ex4_ovf_g4_06t09 <= ex4_ovf_g2_06t07 or ( ex4_ovf_t2_06t07 and ex4_ovf_g2_08t09 ); + ex4_ovf_g4_ci0 <= ex4_ovf_g2_ci0; + ex4_ovf_g4_ci1 <= ex4_ovf_g2_ci1; + + ex4_ovf_t4_02t05 <= ( ex4_ovf_t2_02t03 and ex4_ovf_t2_04t05 ); + ex4_ovf_t4_06t09 <= ( ex4_ovf_t2_06t07 and ex4_ovf_t2_08t09 ); + + ex4_ovf_g8_02t09 <= ex4_ovf_g4_02t05 or ( ex4_ovf_t4_02t05 and ex4_ovf_g4_06t09 ); + ex4_ovf_g8_ci0 <= ex4_ovf_g4_ci0; + ex4_ovf_g8_ci1 <= ex4_ovf_g4_ci1; + + ex4_ovf_t8_02t09 <= ( ex4_ovf_t4_02t05 and ex4_ovf_t4_06t09 ); + + + ex4_ovf_ci0_02t11 <= ex4_ovf_g8_02t09 or (ex4_ovf_t8_02t09 and ex4_ovf_g8_ci0 ); + ex4_ovf_ci1_02t11 <= ex4_ovf_g8_02t09 or (ex4_ovf_t8_02t09 and ex4_ovf_g8_ci1 ); + + + ex4_c2_m1 <= (ex4_ovf_ci0_02t11 or (ex4_ovf_ci1_02t11 and ex4_ovf_m1_co12) ) ; + ex4_c2_p0 <= (ex4_ovf_ci0_02t11 or (ex4_ovf_ci1_02t11 and ex4_ovf_p0_co12) ) ; + ex4_c2_p1 <= (ex4_ovf_ci0_02t11 or (ex4_ovf_ci1_02t11 and ex4_ovf_p1_co12) ) ; + + ex4_ovf_m1 <= not ex4_ovf_p(1) xor ex4_c2_m1; + ex4_ovf_p0 <= not ex4_ovf_p(1) xor ex4_c2_p0; + ex4_ovf_p1 <= not ex4_ovf_p(1) xor ex4_c2_p1; + + + + + ex4_unf_sum( 1) <= ex4_sh_rgt_en_b xor ex4_i_exp( 1) xor ex4_sp; + ex4_unf_sum( 2) <= ex4_sh_rgt_en_b xor ex4_i_exp( 2) xor ex4_sp; + ex4_unf_sum( 3) <= ex4_sh_rgt_en_b xor ex4_i_exp( 3) xor ex4_sp; + ex4_unf_sum( 4) <= ex4_sh_rgt_en_b xor ex4_i_exp( 4); + ex4_unf_sum( 5) <= ex4_sh_rgt_en_b xor ex4_i_exp( 5); + ex4_unf_sum( 6) <= not ex4_lza_amt(0) xor ex4_i_exp( 6) xor ex4_sp; + ex4_unf_sum( 7) <= not ex4_lza_amt(1) xor ex4_i_exp( 7); + ex4_unf_sum( 8) <= not ex4_lza_amt(2) xor ex4_i_exp( 8); + ex4_unf_sum( 9) <= not ex4_lza_amt(3) xor ex4_i_exp( 9); + ex4_unf_sum(10) <= not ex4_lza_amt(4) xor ex4_i_exp(10); + ex4_unf_sum(11) <= not ex4_lza_amt(5) xor ex4_i_exp(11); + ex4_unf_sum(12) <= not ex4_lza_amt(6) xor ex4_i_exp(12); + ex4_unf_sum(13) <= not ex4_lza_amt(7) xor ex4_i_exp(13); + + ex4_unf_car( 1) <= ( ex4_sp and ex4_i_exp( 2) ) or + ( ex4_sh_rgt_en_b and ex4_i_exp( 2) ) or + ( ex4_sh_rgt_en_b and ex4_sp ) ; + ex4_unf_car( 2) <= ( ex4_sp and ex4_i_exp( 3) ) or + ( ex4_sh_rgt_en_b and ex4_i_exp( 3) ) or + ( ex4_sh_rgt_en_b and ex4_sp ) ; + ex4_unf_car( 3) <= ex4_sh_rgt_en_b and ex4_i_exp( 4) ; + ex4_unf_car( 4) <= ex4_sh_rgt_en_b and ex4_i_exp( 5) ; + ex4_unf_car( 5) <= (not ex4_lza_amt(0) and ex4_i_exp( 6) ) or + (not ex4_lza_amt(0) and ex4_sp ) or + ( ex4_sp and ex4_i_exp( 6) ) ; + ex4_unf_car( 6) <= not ex4_lza_amt(1) and ex4_i_exp( 7); + ex4_unf_car( 7) <= not ex4_lza_amt(2) and ex4_i_exp( 8); + ex4_unf_car( 8) <= not ex4_lza_amt(3) and ex4_i_exp( 9); + ex4_unf_car( 9) <= not ex4_lza_amt(4) and ex4_i_exp(10); + ex4_unf_car(10) <= not ex4_lza_amt(5) and ex4_i_exp(11); + ex4_unf_car(11) <= not ex4_lza_amt(6) and ex4_i_exp(12); + ex4_unf_car(12) <= not ex4_lza_amt(7) and ex4_i_exp(13); + + + + ex4_unf_g(2 to 12) <= ex4_unf_car(2 to 12) and ex4_unf_sum(2 to 12); + ex4_unf_t(2 to 12) <= ex4_unf_car(2 to 12) or ex4_unf_sum(2 to 12); + ex4_unf_p(1) <= ex4_unf_car(1) xor ex4_unf_sum(1) ; + + + ex4_unf_m1_co12 <= ex4_unf_g(12); + ex4_unf_p0_co12 <= ex4_unf_g(12) or (ex4_unf_t(12) and ex4_unf_sum(13) ); + + + + + ex4_unf_g2_02t03 <= ex4_unf_g( 2) or (ex4_unf_t( 2) and ex4_unf_g( 3) ); + ex4_unf_g2_04t05 <= ex4_unf_g( 4) or (ex4_unf_t( 4) and ex4_unf_g( 5) ); + ex4_unf_g2_06t07 <= ex4_unf_g( 6) or (ex4_unf_t( 6) and ex4_unf_g( 7) ); + ex4_unf_g2_08t09 <= ex4_unf_g( 8) or (ex4_unf_t( 8) and ex4_unf_g( 9) ); + ex4_unf_g2_10t11 <= ex4_unf_g(10) or (ex4_unf_t(10) and ex4_unf_g(11) ); + ex4_unf_ci0_g2 <= ex4_unf_g(12) ; + ex4_unf_ci1_g2 <= ex4_unf_t(12) ; + + ex4_unf_t2_02t03 <= (ex4_unf_t( 2) and ex4_unf_t( 3) ); + ex4_unf_t2_04t05 <= (ex4_unf_t( 4) and ex4_unf_t( 5) ); + ex4_unf_t2_06t07 <= (ex4_unf_t( 6) and ex4_unf_t( 7) ); + ex4_unf_t2_08t09 <= (ex4_unf_t( 8) and ex4_unf_t( 9) ); + ex4_unf_t2_10t11 <= (ex4_unf_t(10) and ex4_unf_t(11) ); + + ex4_unf_g4_02t05 <= ex4_unf_g2_02t03 or (ex4_unf_t2_02t03 and ex4_unf_g2_04t05 ); + ex4_unf_g4_06t09 <= ex4_unf_g2_06t07 or (ex4_unf_t2_06t07 and ex4_unf_g2_08t09 ); + ex4_unf_ci0_g4 <= ex4_unf_g2_10t11 or (ex4_unf_t2_10t11 and ex4_unf_ci0_g2 ); + ex4_unf_ci1_g4 <= ex4_unf_g2_10t11 or (ex4_unf_t2_10t11 and ex4_unf_ci1_g2 ); + + ex4_unf_t4_02t05 <= (ex4_unf_t2_02t03 and ex4_unf_t2_04t05 ); + ex4_unf_t4_06t09 <= (ex4_unf_t2_06t07 and ex4_unf_t2_08t09 ); + + + ex4_unf_g8_02t09 <= ex4_unf_g4_02t05 or (ex4_unf_t4_02t05 and ex4_unf_g4_06t09 ); + ex4_unf_ci0_g8 <= ex4_unf_ci0_g4; + ex4_unf_ci1_g8 <= ex4_unf_ci1_g4; + + ex4_unf_t8_02t09 <= (ex4_unf_t4_02t05 and ex4_unf_t4_06t09 ); + + ex4_unf_ci0_02t11 <= ex4_unf_g8_02t09 or ( ex4_unf_t8_02t09 and ex4_unf_ci0_g8); + ex4_unf_ci1_02t11 <= ex4_unf_g8_02t09 or ( ex4_unf_t8_02t09 and ex4_unf_ci1_g8); + + + ex4_unf_c2_m1 <= (ex4_unf_ci0_02t11 or (ex4_unf_ci1_02t11 and ex4_unf_m1_co12) ) ; + ex4_unf_c2_p0 <= (ex4_unf_ci0_02t11 or (ex4_unf_ci1_02t11 and ex4_unf_p0_co12) ) ; + + ex4_unf_m1 <= ex4_unf_p(1) xor ex4_unf_c2_m1; + ex4_unf_p0 <= ex4_unf_p(1) xor ex4_unf_c2_p0; + + + + u_expo_p0_0: ex4_expo_p0_0_b(1 to 13) <= not(ex4_lzasub_m1(1 to 13) and (1 to 13 => f_nrm_ex4_extra_shift) ); + u_expo_p0_1: ex4_expo_p0_1_b(1 to 13) <= not(ex4_lzasub_p0(1 to 13) and (1 to 13 => not f_nrm_ex4_extra_shift) ) ; + u_expo_p0: ex4_expo_p0(1 to 13) <= not(ex4_expo_p0_0_b(1 to 13) and ex4_expo_p0_1_b(1 to 13)); + + u_expo_p1_0: ex4_expo_p1_0_b(1 to 13) <= not(ex4_lzasub_p0(1 to 13) and (1 to 13 => f_nrm_ex4_extra_shift) ); + u_expo_p1_1: ex4_expo_p1_1_b(1 to 13) <= not(ex4_lzasub_p1(1 to 13) and (1 to 13 => not f_nrm_ex4_extra_shift) ) ; + u_expo_p1: ex4_expo_p1(1 to 13) <= not(ex4_expo_p1_0_b(1 to 13) and ex4_expo_p1_1_b(1 to 13)); + + u_ovf_calc_0: ex4_ovf_calc_0_b <= not(ex4_ovf_m1 and f_nrm_ex4_extra_shift ) ; + u_ovf_calc_1: ex4_ovf_calc_1_b <= not(ex4_ovf_p0 and not f_nrm_ex4_extra_shift ) ; + u_ovf_calc: ex4_ovf_calc <= not(ex4_ovf_calc_0_b and ex4_ovf_calc_1_b ) ; + + u_ovf_if_calc_0: ex4_ovf_if_calc_0_b <= not(ex4_ovf_p0 and f_nrm_ex4_extra_shift ) ; + u_ovf_if_calc_1: ex4_ovf_if_calc_1_b <= not(ex4_ovf_p1 and not f_nrm_ex4_extra_shift ) ; + u_ovf_if_calc: ex4_ovf_if_calc <= not(ex4_ovf_if_calc_0_b and ex4_ovf_if_calc_1_b ) ; + + u_unf_calc_0: ex4_unf_calc_0_b <= not(ex4_unf_m1 and f_nrm_ex4_extra_shift ) ; + u_unf_calc_1: ex4_unf_calc_1_b <= not(ex4_unf_p0 and not f_nrm_ex4_extra_shift ) ; + u_unf_calc: ex4_unf_calc <= not(ex4_unf_calc_0_b and ex4_unf_calc_1_b ) ; + + + + + ex4_est_sp <= ex4_sel_est and ex4_sp; + + ex4_unf_tbl <= f_pic_ex4_uf_en and f_tbl_ex4_unf_expo ; + ex4_unf_tbl_spec_e <= (ex4_unf_tbl and not ex4_est_sp and not f_pic_ex4_ue) or ex4_sel_k_part_e; + ex4_ov_en <= f_pic_ex4_ov_en ; + ex4_ov_en_oe0 <= f_pic_ex4_ov_en and not f_pic_ex4_oe; + ex4_sel_ov_spec <= f_pic_ex4_sel_ov_spec; + ex4_unf_en_nedge <= f_pic_ex4_uf_en and not f_lza_ex4_no_lza_edge; + ex4_unf_ue0_nestsp <= f_pic_ex4_uf_en and not f_lza_ex4_no_lza_edge and not f_pic_ex4_ue and not(ex4_est_sp); + ex4_sel_k_part_e <= f_pic_ex4_spec_sel_k_e or f_pic_ex4_to_int_ov_all ; + ex4_sel_k_part_f <= f_pic_ex4_spec_sel_k_f or f_pic_ex4_to_int_ov_all ; + + + + + ex5_urnd0_lat: entity tri.tri_nand2_nlats(tri_nand2_nlats) generic map (width=> 13, btr => "NLA0001_X1_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd , + gd => gnd , + LCLK => ex5_lclk , + D1CLK => ex5_d1clk , + D2CLK => ex5_d2clk , + SCANIN => ex5_urnd0_si , + SCANOUT => ex5_urnd0_so , + A1 => ex4_expo_p0_0_b(1 to 13) , + A2 => ex4_expo_p0_1_b(1 to 13) , + QB(0 to 12) => ex5_expo_p0(1 to 13) ); + + ex5_urnd1_lat: entity tri.tri_nand2_nlats(tri_nand2_nlats) generic map (width=> 13, btr => "NLA0001_X1_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd , + gd => gnd , + LCLK => ex5_lclk , + D1CLK => ex5_d1clk , + D2CLK => ex5_d2clk , + SCANIN => ex5_urnd1_si , + SCANOUT => ex5_urnd1_so , + A1 => ex4_expo_p1_0_b(1 to 13) , + A2 => ex4_expo_p1_1_b(1 to 13) , + QB(0 to 12) => ex5_expo_p1(1 to 13) ); + + ex5_ovctl_lat: entity tri.tri_nand2_nlats(tri_nand2_nlats) generic map (width=> 3, btr => "NLA0001_X1_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd , + gd => gnd , + LCLK => ex5_lclk , + D1CLK => ex5_d1clk , + D2CLK => ex5_d2clk , + SCANIN => ex5_ovctl_si , + SCANOUT => ex5_ovctl_so , + A1(0) => ex4_ovf_calc_0_b , + A1(1) => ex4_ovf_if_calc_0_b , + A1(2) => ex4_unf_calc_0_b , + A2(0) => ex4_ovf_calc_1_b , + A2(1) => ex4_ovf_if_calc_1_b , + A2(2) => ex4_unf_calc_1_b , + QB(0) => ex5_ovf_calc , + QB(1) => ex5_ovf_if_calc , + QB(2) => ex5_unf_calc ); + + ex5_misc_lat: tri_rlmreg_p generic map (width=> 13, expand_type => expand_type, needs_sreset => 0) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(5) , + mpw1_b => mpw1_b(5) , + mpw2_b => mpw2_b(1) , + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => ex4_act, + scout => ex5_misc_so , + scin => ex5_misc_si , + din(0) => ex4_unf_tbl , + din(1) => ex4_unf_tbl_spec_e , + din(2) => ex4_ov_en , + din(3) => ex4_ov_en_oe0 , + din(4) => ex4_sel_ov_spec , + din(5) => ex4_unf_en_nedge , + din(6) => ex4_unf_ue0_nestsp , + din(7) => ex4_sel_k_part_f , + din(8 to 12) => ex4_ue1oe1_k(3 to 7) , + dout(0) => ex5_unf_tbl , + dout(1) => ex5_unf_tbl_spec_e , + dout(2) => ex5_ov_en , + dout(3) => ex5_ov_en_oe0 , + dout(4) => ex5_sel_ov_spec , + dout(5) => ex5_unf_en_nedge , + dout(6) => ex5_unf_ue0_nestsp , + dout(7) => ex5_sel_k_part_f , + dout(8 to 12) => ex5_ue1oe1_k(3 to 7) ); + + + + f_eov_ex5_expo_p0(1 to 13) <= ex5_expo_p0(1 to 13) ; + f_eov_ex5_expo_p1(1 to 13) <= ex5_expo_p1(1 to 13) ; + + + + + ex5_sel_ov_spec_b <= not( ex5_sel_ov_spec ); + ex5_ovf_b <= not( ex5_ovf_calc and ex5_ov_en ); + ex5_ovf_if_b <= not( ex5_ovf_if_calc and ex5_ov_en ); + ex5_ovf_oe0_b <= not( ex5_ovf_calc and ex5_ov_en_oe0 ); + ex5_ovf_if_oe0_b <= not( ex5_ovf_if_calc and ex5_ov_en_oe0 ); + ex5_unf_b <= not( ex5_unf_calc and ex5_unf_en_nedge ); + ex5_unf_ue0_b <= not( ex5_unf_calc and ex5_unf_ue0_nestsp ); + ex5_sel_k_part_f_b <= not( ex5_sel_k_part_f ); + ex5_unf_tbl_spec_e_b <= not( ex5_unf_tbl_spec_e ); + ex5_unf_tbl_b <= not( ex5_unf_tbl ); + + + f_eov_ex5_ovf_expo <= not( ex5_ovf_b and ex5_sel_ov_spec_b ); + f_eov_ex5_ovf_if_expo <= not( ex5_ovf_if_b and ex5_sel_ov_spec_b ); + f_eov_ex5_sel_k_f <= not( ex5_ovf_oe0_b and ex5_sel_k_part_f_b ); + f_eov_ex5_sel_kif_f <= not( ex5_ovf_if_oe0_b and ex5_sel_k_part_f_b ); + f_eov_ex5_unf_expo <= not( ex5_unf_b and ex5_unf_tbl_b ); + f_eov_ex5_sel_k_e <= not( ex5_unf_ue0_b and ex5_unf_tbl_spec_e_b and ex5_ovf_oe0_b ); + f_eov_ex5_sel_kif_e <= not( ex5_unf_ue0_b and ex5_unf_tbl_spec_e_b and ex5_ovf_if_oe0_b ); + + + f_eov_ex5_expo_p0_ue1oe1(3 to 6) <= ex5_ue1oe1_p0_p(3 to 6) xor ex5_ue1oe1_p0_c(4 to 7); + f_eov_ex5_expo_p0_ue1oe1(7) <= ex5_ue1oe1_p0_p(7); + + ex5_ue1oe1_p0_p(3 to 7) <= ex5_expo_p0(3 to 7) xor ex5_ue1oe1_k(3 to 7); + ex5_ue1oe1_p0_g(4 to 7) <= ex5_expo_p0(4 to 7) and ex5_ue1oe1_k(4 to 7); + ex5_ue1oe1_p0_t(4 to 6) <= ex5_expo_p0(4 to 6) or ex5_ue1oe1_k(4 to 6); + + + ex5_ue1oe1_p0_g2_b(7) <= not( ex5_ue1oe1_p0_g(7) ) ; + ex5_ue1oe1_p0_g2_b(6) <= not( ex5_ue1oe1_p0_g(6) or (ex5_ue1oe1_p0_t(6) and ex5_ue1oe1_p0_g(7) ) ); + ex5_ue1oe1_p0_g2_b(5) <= not( ex5_ue1oe1_p0_g(5) ) ; + ex5_ue1oe1_p0_g2_b(4) <= not( ex5_ue1oe1_p0_g(4) or (ex5_ue1oe1_p0_t(4) and ex5_ue1oe1_p0_g(5) ) ); + + ex5_ue1oe1_p0_t2_b(5) <= not( ex5_ue1oe1_p0_t(5) ) ; + ex5_ue1oe1_p0_t2_b(4) <= not( (ex5_ue1oe1_p0_t(4) and ex5_ue1oe1_p0_t(5) ) ); + + ex5_ue1oe1_p0_c(7) <= not( ex5_ue1oe1_p0_g2_b(7) ); + ex5_ue1oe1_p0_c(6) <= not( ex5_ue1oe1_p0_g2_b(6) ); + ex5_ue1oe1_p0_c(5) <= not( ex5_ue1oe1_p0_g2_b(5) and (ex5_ue1oe1_p0_t2_b(5) or ex5_ue1oe1_p0_g2_b(6) ) ); + ex5_ue1oe1_p0_c(4) <= not( ex5_ue1oe1_p0_g2_b(4) and (ex5_ue1oe1_p0_t2_b(4) or ex5_ue1oe1_p0_g2_b(6) ) ); + + + f_eov_ex5_expo_p1_ue1oe1(3 to 6) <= ex5_ue1oe1_p1_p(3 to 6) xor ex5_ue1oe1_p1_c(4 to 7); + f_eov_ex5_expo_p1_ue1oe1(7) <= ex5_ue1oe1_p1_p(7); + + ex5_ue1oe1_p1_p(3 to 7) <= ex5_expo_p1(3 to 7) xor ex5_ue1oe1_k(3 to 7); + ex5_ue1oe1_p1_g(4 to 7) <= ex5_expo_p1(4 to 7) and ex5_ue1oe1_k(4 to 7); + ex5_ue1oe1_p1_t(4 to 6) <= ex5_expo_p1(4 to 6) or ex5_ue1oe1_k(4 to 6); + + + ex5_ue1oe1_p1_g2_b(7) <= not( ex5_ue1oe1_p1_g(7) ) ; + ex5_ue1oe1_p1_g2_b(6) <= not( ex5_ue1oe1_p1_g(6) or (ex5_ue1oe1_p1_t(6) and ex5_ue1oe1_p1_g(7) ) ); + ex5_ue1oe1_p1_g2_b(5) <= not( ex5_ue1oe1_p1_g(5) ) ; + ex5_ue1oe1_p1_g2_b(4) <= not( ex5_ue1oe1_p1_g(4) or (ex5_ue1oe1_p1_t(4) and ex5_ue1oe1_p1_g(5) ) ); + + ex5_ue1oe1_p1_t2_b(5) <= not( ex5_ue1oe1_p1_t(5) ) ; + ex5_ue1oe1_p1_t2_b(4) <= not( (ex5_ue1oe1_p1_t(4) and ex5_ue1oe1_p1_t(5) ) ); + + ex5_ue1oe1_p1_c(7) <= not( ex5_ue1oe1_p1_g2_b(7) ); + ex5_ue1oe1_p1_c(6) <= not( ex5_ue1oe1_p1_g2_b(6) ); + ex5_ue1oe1_p1_c(5) <= not( ex5_ue1oe1_p1_g2_b(5) and (ex5_ue1oe1_p1_t2_b(5) or ex5_ue1oe1_p1_g2_b(6) ) ); + ex5_ue1oe1_p1_c(4) <= not( ex5_ue1oe1_p1_g2_b(4) and (ex5_ue1oe1_p1_t2_b(4) or ex5_ue1oe1_p1_g2_b(6) ) ); + + + + + act_si (0 to 4) <= act_so (1 to 4) & f_eov_si ; + ex4_iexp_si (0 to 15) <= ex4_iexp_so (1 to 15) & act_so (0); + ex5_ovctl_si (0 to 2) <= ex5_ovctl_so (1 to 2) & ex4_iexp_so (0); + ex5_misc_si (0 to 12) <= ex5_misc_so (1 to 12) & ex5_ovctl_so (0); + ex5_urnd0_si (0 to 12) <= ex5_urnd0_so (1 to 12) & ex5_misc_so (0); + ex5_urnd1_si (0 to 12) <= ex5_urnd1_so (1 to 12) & ex5_urnd0_so (0); + f_eov_so <= ex5_urnd1_so (0); + +end; + + + + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_fmt.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_fmt.vhdl new file mode 100644 index 0000000..2140ccb --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_fmt.vhdl @@ -0,0 +1,1597 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + + +entity fuq_fmt is +generic( expand_type : integer := 2 ); +port( + vdd :inout power_logic; + gnd :inout power_logic; + clkoff_b :in std_ulogic; + act_dis :in std_ulogic; + flush :in std_ulogic; + delay_lclkr :in std_ulogic_vector(1 to 2); + mpw1_b :in std_ulogic_vector(1 to 2); + mpw2_b :in std_ulogic_vector(0 to 0); + sg_1 :in std_ulogic; + thold_1 :in std_ulogic; + fpu_enable :in std_ulogic; + nclk :in clk_logic; + + + f_fmt_si :in std_ulogic; + f_fmt_so :out std_ulogic; + rf1_act :in std_ulogic; + ex1_act :in std_ulogic; + + f_byp_fmt_ex1_a_sign :in std_ulogic; + f_byp_fmt_ex1_c_sign :in std_ulogic; + f_byp_fmt_ex1_b_sign :in std_ulogic; + f_byp_fmt_ex1_a_expo :in std_ulogic_vector(1 to 13); + f_byp_fmt_ex1_c_expo :in std_ulogic_vector(1 to 13); + f_byp_fmt_ex1_b_expo :in std_ulogic_vector(1 to 13); + f_byp_fmt_ex1_a_frac :in std_ulogic_vector(0 to 52); + f_byp_fmt_ex1_c_frac :in std_ulogic_vector(0 to 52); + f_byp_fmt_ex1_b_frac :in std_ulogic_vector(0 to 52); + + f_dcd_rf1_aop_valid :in std_ulogic ; + f_dcd_rf1_cop_valid :in std_ulogic ; + f_dcd_rf1_bop_valid :in std_ulogic ; + f_dcd_rf1_from_integer_b :in std_ulogic ; + f_dcd_rf1_fsel_b :in std_ulogic ; + f_dcd_rf1_force_pass_b :in std_ulogic ; + + f_dcd_rf1_sp :in std_ulogic ; + + f_dcd_ex1_perr_force_c :in std_ulogic; + f_dcd_ex1_perr_fsel_ovrd :in std_ulogic; + + + f_pic_ex1_ftdiv :in std_ulogic; + f_pic_ex1_flush_en_sp :in std_ulogic; + f_pic_ex1_flush_en_dp :in std_ulogic; + + f_pic_ex1_nj_deni :in std_ulogic ; + f_dcd_rf1_uc_end :in std_ulogic; + f_dcd_rf1_uc_mid :in std_ulogic; + f_dcd_rf1_uc_special :in std_ulogic; + f_dcd_rf1_sgncpy_b :in std_ulogic; + + f_fmt_ex2_lu_den_recip :out std_ulogic ; + f_fmt_ex2_lu_den_rsqrto :out std_ulogic ; + + f_fmt_ex1_bop_byt :out std_ulogic_vector(45 to 52) ; + + f_fmt_ex1_a_zero :out std_ulogic ; + f_fmt_ex1_a_expo_max :out std_ulogic ; + f_fmt_ex1_a_frac_zero :out std_ulogic ; + f_fmt_ex1_a_frac_msb :out std_ulogic ; + + f_fmt_ex1_c_zero :out std_ulogic ; + f_fmt_ex1_c_expo_max :out std_ulogic ; + f_fmt_ex1_c_frac_zero :out std_ulogic ; + f_fmt_ex1_c_frac_msb :out std_ulogic ; + + f_fmt_ex1_b_zero :out std_ulogic ; + f_fmt_ex1_b_expo_max :out std_ulogic ; + f_fmt_ex1_b_frac_zero :out std_ulogic ; + f_fmt_ex1_b_frac_msb :out std_ulogic ; + f_fmt_ex1_b_imp :out std_ulogic ; + f_fmt_ex1_b_frac_z32 :out std_ulogic ; + + f_fmt_ex1_prod_zero :out std_ulogic ; + f_fmt_ex1_pass_sel :out std_ulogic ; + + f_fmt_ex1_sp_invalid :out std_ulogic ; + f_fmt_ex1_bexpu_le126 :out std_ulogic ; + f_fmt_ex1_gt126 :out std_ulogic ; + f_fmt_ex1_ge128 :out std_ulogic ; + f_fmt_ex1_inf_and_beyond_sp :out std_ulogic ; + + f_mad_ex2_uc_a_expo_den :out std_ulogic ; + f_mad_ex2_uc_a_expo_den_sp :out std_ulogic ; + + f_ex2_b_den_flush :out std_ulogic ; + + f_fmt_ex2_fsel_bsel :out std_ulogic ; + f_fmt_ex2_pass_sign :out std_ulogic ; + f_fmt_ex2_pass_msb :out std_ulogic ; + f_fmt_ex1_b_frac :out std_ulogic_vector(1 to 19) ; + f_fmt_ex1_b_sign_gst :out std_ulogic ; + f_fmt_ex1_b_expo_gst_b :out std_ulogic_vector(1 to 13); + + f_fpr_ex1_a_par :in std_ulogic_vector(0 to 7) ; + f_fpr_ex1_c_par :in std_ulogic_vector(0 to 7) ; + f_fpr_ex1_b_par :in std_ulogic_vector(0 to 7) ; + f_mad_ex2_a_parity_check :out std_ulogic ; + f_mad_ex2_c_parity_check :out std_ulogic ; + f_mad_ex2_b_parity_check :out std_ulogic ; + + f_fmt_ex2_ae_ge_54 :out std_ulogic ; + f_fmt_ex2_be_ge_54 :out std_ulogic ; + f_fmt_ex2_be_ge_2 :out std_ulogic ; + f_fmt_ex2_be_ge_2044 :out std_ulogic ; + f_fmt_ex2_tdiv_rng_chk :out std_ulogic ; + f_fmt_ex2_be_den :out std_ulogic ; + f_fmt_ex2_pass_frac :out std_ulogic_vector(0 to 52) + +); + + + +end fuq_fmt; + +architecture fuq_fmt of fuq_fmt is + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal thold_0_b, thold_0, forcee :std_ulogic; + signal sg_0 :std_ulogic; + signal spare_unused :std_ulogic_vector(0 to 3); + signal act_si :std_ulogic_vector(0 to 6); + signal act_so :std_ulogic_vector(0 to 6); + + signal ex1_ctl_si :std_ulogic_vector(0 to 8); + signal ex1_ctl_so :std_ulogic_vector(0 to 8); + signal ex2_pass_si :std_ulogic_vector(0 to 79); + signal ex2_pass_so :std_ulogic_vector(0 to 79); + signal ex2_pass_frac :std_ulogic_vector(0 to 52); + signal ex1_from_integer :std_ulogic; + signal ex1_fsel :std_ulogic; + signal ex1_force_pass :std_ulogic; + signal ex1_a_sign :std_ulogic; + signal ex1_c_sign :std_ulogic; + signal ex1_b_sign :std_ulogic; + signal ex2_fsel_bsel :std_ulogic; + signal ex2_pass_sign :std_ulogic; + signal ex1_a_frac :std_ulogic_vector(0 to 52); + signal ex1_c_frac :std_ulogic_vector(0 to 52); + signal ex1_b_frac :std_ulogic_vector(0 to 52); + signal ex1_pass_frac_ac :std_ulogic_vector(0 to 52); + signal ex1_pass_frac :std_ulogic_vector(0 to 52); + signal ex1_a_frac_msb :std_ulogic; + signal ex1_a_expo_min :std_ulogic; + signal ex1_a_expo_max :std_ulogic; + signal ex1_a_frac_zero :std_ulogic; + signal ex1_c_frac_msb :std_ulogic; + signal ex1_c_expo_min :std_ulogic; + signal ex1_c_expo_max :std_ulogic; + signal ex1_c_frac_zero :std_ulogic; + signal ex1_b_frac_msb :std_ulogic; + signal ex1_b_expo_min :std_ulogic; + signal ex1_b_expo_max :std_ulogic; + signal ex1_b_frac_zero :std_ulogic; + signal ex1_b_frac_z32 :std_ulogic; + signal ex1_a_nan :std_ulogic; + signal ex1_c_nan :std_ulogic; + signal ex1_b_nan :std_ulogic; + signal ex1_nan_pass :std_ulogic; + signal ex1_pass_sel :std_ulogic; + signal ex1_fsel_cif :std_ulogic; + signal ex1_fsel_bsel :std_ulogic; + signal ex1_mux_a_sel :std_ulogic; + signal ex1_mux_c_sel :std_ulogic; + signal ex1_pass_sign_ac :std_ulogic; + signal ex1_pass_sign :std_ulogic; + signal ex1_a_expo :std_ulogic_vector(1 to 13); + signal ex1_b_expo :std_ulogic_vector(1 to 13); + signal ex1_c_expo :std_ulogic_vector(1 to 13); + signal ex1_a_expo_b :std_ulogic_vector(1 to 13); + signal ex1_c_expo_b :std_ulogic_vector(1 to 13); + signal ex1_b_expo_b :std_ulogic_vector(1 to 13); + signal rf1_aop_valid_b :std_ulogic; + signal rf1_cop_valid_b :std_ulogic; + signal rf1_bop_valid_b :std_ulogic; + signal ex1_aop_valid :std_ulogic; + signal ex1_cop_valid :std_ulogic; + signal ex1_bop_valid :std_ulogic; + signal ex1_a_zero :std_ulogic; + signal ex1_c_zero :std_ulogic; + signal ex1_b_zero :std_ulogic; + signal ex1_a_zero_x :std_ulogic; + signal ex1_c_zero_x :std_ulogic; + signal ex1_b_zero_x :std_ulogic; + signal ex1_a_sp_expo_ok_1 :std_ulogic; + signal ex1_c_sp_expo_ok_1 :std_ulogic; + signal ex1_b_sp_expo_ok_1 :std_ulogic; + signal ex1_a_sp_expo_ok_2 :std_ulogic; + signal ex1_c_sp_expo_ok_2 :std_ulogic; + signal ex1_b_sp_expo_ok_2 :std_ulogic; + signal ex1_a_sp_expo_ok_3 :std_ulogic; + signal ex1_c_sp_expo_ok_3 :std_ulogic; + signal ex1_b_sp_expo_ok_3 :std_ulogic; + signal ex1_a_sp_expo_ok_4 :std_ulogic; + signal ex1_c_sp_expo_ok_4 :std_ulogic; + signal ex1_b_sp_expo_ok_4 :std_ulogic; + signal ex2_pass_dp :std_ulogic_vector(0 to 52); + signal ex1_from_integer_b :std_ulogic; + signal ex1_fsel_b :std_ulogic; + signal ex1_aop_valid_b :std_ulogic; + signal ex1_cop_valid_b :std_ulogic; + signal ex1_bop_valid_b :std_ulogic; + signal ex1_b_den_flush, ex1_b_den_sp , ex1_a_den_sp , ex1_b_den_dp , ex2_b_den_flush :std_ulogic; + signal ex1_lu_den_part, ex1_lu_den_recip, ex1_lu_den_rsqrto :std_ulogic; + signal ex2_lu_den_recip, ex2_lu_den_rsqrto :std_ulogic; + signal ex1_recip_lo , ex1_rsqrt_lo :std_ulogic; + signal ex1_bfrac_eq_126, ex1_bfrac_126_nz :std_ulogic; + signal ex1_bexpo_ge897_hi :std_ulogic; + signal ex1_bexpo_ge897_mid1 :std_ulogic; + signal ex1_bexpo_ge897_mid2 :std_ulogic; + signal ex1_bexpo_ge897_lo :std_ulogic; + signal ex1_bexpo_ge897 :std_ulogic; + signal ex1_bexpu_eq6 :std_ulogic ; + signal ex1_bexpu_ge7 :std_ulogic ; + signal ex1_bexpu_ge7_lo :std_ulogic ; + signal ex1_bexpu_ge7_mid :std_ulogic ; + signal ex1_a_sp, ex1_c_sp , ex1_b_sp :std_ulogic ; + signal ex1_b_frac_zero_sp, ex1_b_frac_zero_dp :std_ulogic ; + signal ex1_a_denz , ex1_c_denz , ex1_b_denz :std_ulogic ; + signal ex1_a_frac_chop, ex1_c_frac_chop, ex1_b_frac_chop :std_ulogic_vector(0 to 52); + + signal rf1_sgncpy, ex1_sgncpy , ex1_uc_mid :std_ulogic; + signal rf1_force_pass :std_ulogic; + signal rf1_uc_end_nspec, rf1_uc_end_spec, ex1_uc_end_nspec :std_ulogic; + signal ex1_uc_a_expo_den , ex2_uc_a_expo_den :std_ulogic ; + signal ex1_uc_a_expo_den_sp , ex2_uc_a_expo_den_sp :std_ulogic ; + + signal ex1_a_expo_ltx381_sp, ex1_a_expo_ltx381, ex1_a_expo_00xx_xxxx_xxxx, ex1_a_expo_xx11_1xxx_xxxx, ex1_a_expo_xxxx_x000_0000 :std_ulogic; + signal ex1_c_expo_ltx381_sp, ex1_c_expo_ltx381, ex1_c_expo_00xx_xxxx_xxxx, ex1_c_expo_xx11_1xxx_xxxx, ex1_c_expo_xxxx_x000_0000 :std_ulogic; + signal ex1_b_expo_ltx381_sp, ex1_b_expo_ltx381, ex1_b_expo_00xx_xxxx_xxxx, ex1_b_expo_xx11_1xxx_xxxx, ex1_b_expo_xxxx_x000_0000 :std_ulogic; + signal ex1_a_sp_inf_alias_tail, ex1_c_sp_inf_alias_tail, ex1_b_sp_inf_alias_tail :std_ulogic; + signal ex2_a_party_chick , ex2_c_party_chick , ex2_b_party_chick :std_ulogic ; + signal ex1_a_party_chick , ex1_c_party_chick , ex1_b_party_chick :std_ulogic ; + signal ex1_a_party, ex1_c_party, ex1_b_party :std_ulogic_vector(0 to 7); + signal ex1_b_expo_ge1151 :std_ulogic ; + signal ex1_ae_234567, ex1_ae_89, ex1_ae_abc, ex1_ae_ge_54, ex2_ae_ge_54 :std_ulogic ; + signal ex1_be_234567, ex1_be_89, ex1_be_abc, ex1_be_ge_54, ex2_be_ge_54 :std_ulogic ; +signal ex1_be_ge_2, ex2_be_ge_2, ex1_be_or_23456789abc :std_ulogic; +signal ex1_be_ge_2044, ex2_be_ge_2044, ex1_be_and_3456789ab :std_ulogic; + signal ex1_aembex_car_b, ex1_aembey_car_b :std_ulogic_vector(0 to 12) ; + signal ex1_aembex_sum_b, ex1_aembey_sum_b :std_ulogic_vector(1 to 13) ; + signal ex1_aembex_g1, ex1_aembey_g1 :std_ulogic_vector(2 to 12) ; + signal ex1_aembex_t1, ex1_aembey_t1 :std_ulogic_vector(2 to 12) ; + signal ex1_aembex_g2, ex1_aembey_g2 :std_ulogic_vector(0 to 5) ; + signal ex1_aembex_t2, ex1_aembey_t2 :std_ulogic_vector(0 to 4) ; + signal ex1_aembex_g4, ex1_aembey_g4 :std_ulogic_vector(0 to 2) ; + signal ex1_aembex_t4, ex1_aembey_t4 :std_ulogic_vector(0 to 1) ; + signal ex2_aembex_g4, ex2_aembey_g4 :std_ulogic_vector(0 to 2) ; + signal ex2_aembex_t4, ex2_aembey_t4 :std_ulogic_vector(0 to 1) ; + signal ex2_aembex_g8, ex2_aembey_g8 :std_ulogic_vector(0 to 1); + signal ex2_aembex_t8, ex2_aembey_t8 :std_ulogic_vector(0 to 0); + signal ex2_aembex_c2, ex2_aembey_c2 :std_ulogic; + signal ex1_aembex_sgn, ex1_aembey_sgn :std_ulogic; + signal ex2_aembex_sgn, ex2_aembey_sgn :std_ulogic; + signal ex2_aembex_res_sgn, ex2_aembey_res_sgn :std_ulogic; + signal unused :std_ulogic; + signal ex1_be_den, ex2_be_den :std_ulogic; + + + + +begin + +unused <= ex1_aembex_car_b(0) or + ex1_aembex_sum_b(13) or + ex1_aembex_t1(12) or + ex1_aembey_car_b(0) or + ex1_aembey_sum_b(13) or + ex1_aembey_t1(12) ; + + + + thold_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => thold_1, + q(0) => thold_0 ); + + sg_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => sg_1 , + q(0) => sg_0 ); + + + lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map ( + clkoff_b => clkoff_b, + thold => thold_0, + sg => sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => thold_0_b ); + + + + + act_lat: tri_rlmreg_p generic map (width=> 7, expand_type => expand_type, needs_sreset => 0) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(1) , + mpw1_b => mpw1_b(1) , + mpw2_b => mpw2_b(0) , + vd => vdd, + gd => gnd, + nclk => nclk, + act => fpu_enable, + thold_b => thold_0_b, + sg => sg_0, + scout => act_so , + scin => act_si , + din(0) => spare_unused(0), + din(1) => spare_unused(1), + din(2) => f_dcd_rf1_sp , + din(3) => f_dcd_rf1_sp , + din(4) => f_dcd_rf1_sp , + din(5) => spare_unused(2), + din(6) => spare_unused(3), + dout(0) => spare_unused(0), + dout(1) => spare_unused(1), + dout(2) => ex1_a_sp , + dout(3) => ex1_c_sp , + dout(4) => ex1_b_sp , + dout(5) => spare_unused(2) , + dout(6) => spare_unused(3) ); + + + + + rf1_aop_valid_b <= not f_dcd_rf1_aop_valid; + rf1_cop_valid_b <= not f_dcd_rf1_cop_valid; + rf1_bop_valid_b <= not f_dcd_rf1_bop_valid; + + + + ex1_a_frac(0 to 52) <= f_byp_fmt_ex1_a_frac(0 to 52); + ex1_c_frac(0 to 52) <= f_byp_fmt_ex1_c_frac(0 to 52); + ex1_b_frac(0 to 52) <= f_byp_fmt_ex1_b_frac(0 to 52); + + + ex1_a_sign <= f_byp_fmt_ex1_a_sign ; + ex1_c_sign <= f_byp_fmt_ex1_c_sign ; + ex1_b_sign <= f_byp_fmt_ex1_b_sign ; + + ex1_a_expo(1 to 13) <= f_byp_fmt_ex1_a_expo(1 to 13); + ex1_c_expo(1 to 13) <= f_byp_fmt_ex1_c_expo(1 to 13); + ex1_b_expo(1 to 13) <= f_byp_fmt_ex1_b_expo(1 to 13); + + ex1_a_expo_b(1 to 13) <= not ex1_a_expo(1 to 13); + ex1_c_expo_b(1 to 13) <= not ex1_c_expo(1 to 13) ; + ex1_b_expo_b(1 to 13) <= not ex1_b_expo(1 to 13) ; + + f_fmt_ex1_b_sign_gst <= ex1_b_sign ; + rf1_sgncpy <= not f_dcd_rf1_sgncpy_b; + rf1_uc_end_nspec <= f_dcd_rf1_uc_end and not f_dcd_rf1_uc_special ; + rf1_uc_end_spec <= f_dcd_rf1_uc_end and f_dcd_rf1_uc_special ; + rf1_force_pass <= (not f_dcd_rf1_force_pass_b) or rf1_uc_end_spec; + + + ex1_ctl_lat: tri_rlmreg_p generic map (width=> 9, expand_type => expand_type, needs_sreset => 0) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(1) , + mpw1_b => mpw1_b(1) , + mpw2_b => mpw2_b(0) , + vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_act, + thold_b => thold_0_b, + sg => sg_0, + scout => ex1_ctl_so , + scin => ex1_ctl_si , + din(0) => f_dcd_rf1_from_integer_b , + din(1) => f_dcd_rf1_fsel_b , + din(2) => rf1_force_pass , + din(3) => rf1_aop_valid_b, + din(4) => rf1_cop_valid_b, + din(5) => rf1_bop_valid_b, + din(6) => rf1_sgncpy , + din(7) => rf1_uc_end_nspec, + din(8) => f_dcd_rf1_uc_mid, + dout(0) => ex1_from_integer_b , + dout(1) => ex1_fsel_b , + dout(2) => ex1_force_pass , + dout(3) => ex1_aop_valid_b, + dout(4) => ex1_cop_valid_b, + dout(5) => ex1_bop_valid_b, + dout(6) => ex1_sgncpy , + dout(7) => ex1_uc_end_nspec , + dout(8) => ex1_uc_mid ); + + ex1_from_integer <= not ex1_from_integer_b ; + ex1_fsel <= not ex1_fsel_b ; + ex1_aop_valid <= not ex1_aop_valid_b ; + ex1_cop_valid <= not ex1_cop_valid_b ; + ex1_bop_valid <= not ex1_bop_valid_b ; + + + f_fmt_ex1_bop_byt(45 to 52) <= ex1_b_frac(45 to 52); + + + f_fmt_ex1_b_expo_gst_b(1 to 13) <= not ex1_b_expo(1 to 13) ; + + + ex1_bexpo_ge897_hi <= not ex1_b_expo(1) and + ex1_b_frac(0); + ex1_bexpo_ge897_mid1 <= ex1_b_expo(2) or ex1_b_expo(3) ; + ex1_bexpo_ge897_mid2 <= ex1_b_expo(4) and ex1_b_expo(5) and ex1_b_expo(6) ; + ex1_bexpo_ge897_lo <= ex1_b_expo(7) or ex1_b_expo(8) or ex1_b_expo(9) or + ex1_b_expo(10) or ex1_b_expo(11) or ex1_b_expo(12) or + ex1_b_expo(13) ; + + ex1_bexpo_ge897 <= + ( ex1_bexpo_ge897_hi and ex1_bexpo_ge897_mid1 ) or + ( ex1_bexpo_ge897_hi and ex1_bexpo_ge897_mid2 and ex1_bexpo_ge897_lo ) ; + + ex1_bexpu_ge7_mid <= ex1_b_expo(4) or ex1_b_expo(5) or ex1_b_expo(6) or + ex1_b_expo(7) or ex1_b_expo(8) or ex1_b_expo(9) or ex1_b_expo(10); + ex1_bexpu_ge7_lo <= ex1_b_expo(11) and ex1_b_expo(12) ; + + ex1_bexpu_ge7 <= + ( not ex1_b_expo(1) and ex1_b_expo(2) ) or + ( not ex1_b_expo(1) and ex1_b_expo(3) and ex1_bexpu_ge7_mid ) or + ( not ex1_b_expo(1) and ex1_b_expo(3) and ex1_bexpu_ge7_lo ) ; + + ex1_bexpu_eq6 <= + not ex1_b_expo(1) and + not ex1_b_expo(2) and + ex1_b_expo(3) and + not ex1_b_expo(4) and + not ex1_b_expo(5) and + not ex1_b_expo(6) and + not ex1_b_expo(7) and + not ex1_b_expo(8) and + not ex1_b_expo(9) and + not ex1_b_expo(10) and + ex1_b_expo(11) and + not ex1_b_expo(12) and + ex1_b_expo(13) ; + + + f_fmt_ex1_bexpu_le126 <= not ex1_bexpo_ge897; + f_fmt_ex1_gt126 <= ex1_bexpu_ge7 or + (ex1_bexpu_eq6 and ex1_bfrac_eq_126 and ex1_bfrac_126_nz ) ; + f_fmt_ex1_ge128 <= ex1_bexpu_ge7 ; + + ex1_b_expo_ge1151 <= + ( ex1_b_expo_b(1) and not ex1_b_expo_b(2) ) or + ( ex1_b_expo_b(1) and not ex1_b_expo_b(3) and not ex1_b_expo_b(4) ) or + ( ex1_b_expo_b(1) and not ex1_b_expo_b(3) and not ex1_b_expo_b(5) ) or + ( ex1_b_expo_b(1) and not ex1_b_expo_b(3) and not ex1_b_expo_b(6) ) or + ( ex1_b_expo_b(1) and not ex1_b_expo_b(3) and not ex1_b_expo_b(7) + and not ex1_b_expo_b(8) + and not ex1_b_expo_b(9) + and not ex1_b_expo_b(10) + and not ex1_b_expo_b(11) + and not ex1_b_expo_b(12) + and not ex1_b_expo_b(13) ); + + + f_fmt_ex1_inf_and_beyond_sp <= ex1_b_expo_max or ex1_b_expo_ge1151 ; + + + + + ex1_bfrac_eq_126 <= ex1_b_frac(0) and + ex1_b_frac(1) and + ex1_b_frac(2) and + ex1_b_frac(3) and + ex1_b_frac(4) and + ex1_b_frac(5) ; + + + ex1_bfrac_126_nz <= ex1_b_frac(6) or + ex1_b_frac(7) or + ex1_b_frac(8) or + ex1_b_frac(9) or + ex1_b_frac(10) or + ex1_b_frac(11) or + ex1_b_frac(12) or + ex1_b_frac(13) or + ex1_b_frac(14) or + ex1_b_frac(15) or + ex1_b_frac(16) or + ex1_b_frac(17) or + ex1_b_frac(18) or + ex1_b_frac(19) or + ex1_b_frac(20) or + ex1_b_frac(21) or + ex1_b_frac(22) or + ex1_b_frac(23) ; + + + + ex1_a_frac_msb <= ex1_a_frac(1); + ex1_c_frac_msb <= ex1_c_frac(1); + ex1_b_frac_msb <= ex1_b_frac(1); + + ex1_a_expo_min <= not ex1_a_frac(0) ; + ex1_c_expo_min <= not ex1_c_frac(0) ; + ex1_b_expo_min <= not ex1_b_frac(0) ; + + ex1_a_expo_max <= ex1_a_expo_b(1) and + ex1_a_expo_b(2) and + not ex1_a_expo_b(3) and + not ex1_a_expo_b(4) and + not ex1_a_expo_b(5) and + not ex1_a_expo_b(6) and + not ex1_a_expo_b(7) and + not ex1_a_expo_b(8) and + not ex1_a_expo_b(9) and + not ex1_a_expo_b(10) and + not ex1_a_expo_b(11) and + not ex1_a_expo_b(12) and + not ex1_a_expo_b(13) ; + + ex1_c_expo_max <= ex1_c_expo_b(1) and + ex1_c_expo_b(2) and + not ex1_c_expo_b(3) and + not ex1_c_expo_b(4) and + not ex1_c_expo_b(5) and + not ex1_c_expo_b(6) and + not ex1_c_expo_b(7) and + not ex1_c_expo_b(8) and + not ex1_c_expo_b(9) and + not ex1_c_expo_b(10) and + not ex1_c_expo_b(11) and + not ex1_c_expo_b(12) and + not ex1_c_expo_b(13) ; + + ex1_b_expo_max <= ex1_b_expo_b(1) and + ex1_b_expo_b(2) and + not ex1_b_expo_b(3) and + not ex1_b_expo_b(4) and + not ex1_b_expo_b(5) and + not ex1_b_expo_b(6) and + not ex1_b_expo_b(7) and + not ex1_b_expo_b(8) and + not ex1_b_expo_b(9) and + not ex1_b_expo_b(10) and + not ex1_b_expo_b(11) and + not ex1_b_expo_b(12) and + not ex1_b_expo_b(13) ; + + + ex1_a_frac_zero <= + not ex1_a_frac( 1) and + not ex1_a_frac( 2) and + not ex1_a_frac( 3) and + not ex1_a_frac( 4) and + not ex1_a_frac( 5) and + not ex1_a_frac( 6) and + not ex1_a_frac( 7) and + not ex1_a_frac( 8) and + not ex1_a_frac( 9) and + not ex1_a_frac(10) and + not ex1_a_frac(11) and + not ex1_a_frac(12) and + not ex1_a_frac(13) and + not ex1_a_frac(14) and + not ex1_a_frac(15) and + not ex1_a_frac(16) and + not ex1_a_frac(17) and + not ex1_a_frac(18) and + not ex1_a_frac(19) and + not ex1_a_frac(20) and + not ex1_a_frac(21) and + not ex1_a_frac(22) and + not ex1_a_frac(23) and + not ex1_a_frac(24) and + not ex1_a_frac(25) and + not ex1_a_frac(26) and + not ex1_a_frac(27) and + not ex1_a_frac(28) and + not ex1_a_frac(29) and + not ex1_a_frac(30) and + not ex1_a_frac(31) and + not ex1_a_frac(32) and + not ex1_a_frac(33) and + not ex1_a_frac(34) and + not ex1_a_frac(35) and + not ex1_a_frac(36) and + not ex1_a_frac(37) and + not ex1_a_frac(38) and + not ex1_a_frac(39) and + not ex1_a_frac(40) and + not ex1_a_frac(41) and + not ex1_a_frac(42) and + not ex1_a_frac(43) and + not ex1_a_frac(44) and + not ex1_a_frac(45) and + not ex1_a_frac(46) and + not ex1_a_frac(47) and + not ex1_a_frac(48) and + not ex1_a_frac(49) and + not ex1_a_frac(50) and + not ex1_a_frac(51) and + not ex1_a_frac(52) ; + + ex1_c_frac_zero <= + not ex1_c_frac( 1) and + not ex1_c_frac( 2) and + not ex1_c_frac( 3) and + not ex1_c_frac( 4) and + not ex1_c_frac( 5) and + not ex1_c_frac( 6) and + not ex1_c_frac( 7) and + not ex1_c_frac( 8) and + not ex1_c_frac( 9) and + not ex1_c_frac(10) and + not ex1_c_frac(11) and + not ex1_c_frac(12) and + not ex1_c_frac(13) and + not ex1_c_frac(14) and + not ex1_c_frac(15) and + not ex1_c_frac(16) and + not ex1_c_frac(17) and + not ex1_c_frac(18) and + not ex1_c_frac(19) and + not ex1_c_frac(20) and + not ex1_c_frac(21) and + not ex1_c_frac(22) and + not ex1_c_frac(23) and + not ex1_c_frac(24) and + not ex1_c_frac(25) and + not ex1_c_frac(26) and + not ex1_c_frac(27) and + not ex1_c_frac(28) and + not ex1_c_frac(29) and + not ex1_c_frac(30) and + not ex1_c_frac(31) and + not ex1_c_frac(32) and + not ex1_c_frac(33) and + not ex1_c_frac(34) and + not ex1_c_frac(35) and + not ex1_c_frac(36) and + not ex1_c_frac(37) and + not ex1_c_frac(38) and + not ex1_c_frac(39) and + not ex1_c_frac(40) and + not ex1_c_frac(41) and + not ex1_c_frac(42) and + not ex1_c_frac(43) and + not ex1_c_frac(44) and + not ex1_c_frac(45) and + not ex1_c_frac(46) and + not ex1_c_frac(47) and + not ex1_c_frac(48) and + not ex1_c_frac(49) and + not ex1_c_frac(50) and + not ex1_c_frac(51) and + not ex1_c_frac(52) ; + + + ex1_b_frac_zero_sp <= + not ex1_b_frac( 1) and + not ex1_b_frac( 2) and + not ex1_b_frac( 3) and + not ex1_b_frac( 4) and + not ex1_b_frac( 5) and + not ex1_b_frac( 6) and + not ex1_b_frac( 7) and + not ex1_b_frac( 8) and + not ex1_b_frac( 9) and + not ex1_b_frac(10) and + not ex1_b_frac(11) and + not ex1_b_frac(12) and + not ex1_b_frac(13) and + not ex1_b_frac(14) and + not ex1_b_frac(15) and + not ex1_b_frac(16) and + not ex1_b_frac(17) and + not ex1_b_frac(18) and + not ex1_b_frac(19) and + not ex1_b_frac(20) and + not ex1_b_frac(21) and + not ex1_b_frac(22) and + not ex1_b_frac(23) ; + + ex1_b_frac_zero <= ex1_b_frac_zero_sp and ex1_b_frac_zero_dp ; + + ex1_b_frac_z32 <= + not ex1_b_frac(24) and + not ex1_b_frac(25) and + not ex1_b_frac(26) and + not ex1_b_frac(27) and + not ex1_b_frac(28) and + not ex1_b_frac(29) and + not ex1_b_frac(30) and + not ex1_b_frac(31) ; + f_fmt_ex1_b_frac_z32 <= ex1_b_frac_zero_sp and ex1_b_frac_z32; + ex1_b_frac_zero_dp <= ex1_b_frac_z32 and + not ex1_b_frac(32) and + not ex1_b_frac(33) and + not ex1_b_frac(34) and + not ex1_b_frac(35) and + not ex1_b_frac(36) and + not ex1_b_frac(37) and + not ex1_b_frac(38) and + not ex1_b_frac(39) and + not ex1_b_frac(40) and + not ex1_b_frac(41) and + not ex1_b_frac(42) and + not ex1_b_frac(43) and + not ex1_b_frac(44) and + not ex1_b_frac(45) and + not ex1_b_frac(46) and + not ex1_b_frac(47) and + not ex1_b_frac(48) and + not ex1_b_frac(49) and + not ex1_b_frac(50) and + not ex1_b_frac(51) and + not ex1_b_frac(52) ; + + + f_fmt_ex1_b_frac(1 to 19) <= ex1_b_frac(1 to 19) ; + + ex1_a_denz <= (not ex1_a_frac(0) or ex1_a_expo_ltx381_sp) and f_pic_ex1_nj_deni ; + ex1_c_denz <= (not ex1_c_frac(0) or ex1_c_expo_ltx381_sp) and f_pic_ex1_nj_deni ; + ex1_b_denz <= (not ex1_b_frac(0) or ex1_b_expo_ltx381_sp) and f_pic_ex1_nj_deni and not ex1_from_integer; + + ex1_a_zero_x <= ( ex1_a_denz or (ex1_a_expo_min and ex1_a_frac_zero) ); + ex1_c_zero_x <= ( ex1_c_denz or (ex1_c_expo_min and ex1_c_frac_zero) ); + ex1_b_zero_x <= ( ex1_b_denz or (ex1_b_expo_min and ex1_b_frac_zero) ) and (not ex1_from_integer or not ex1_b_sign ); + + + + ex1_b_den_flush <= ex1_b_den_sp or ex1_b_den_dp or ex1_a_den_sp; + + ex1_b_den_dp <= f_pic_ex1_flush_en_dp and + ex1_bop_valid and + ex1_b_expo_min and + not ex1_b_frac_zero and + not f_pic_ex1_nj_deni and + not ex1_b_expo(5) ; + + ex1_b_den_sp <= f_pic_ex1_flush_en_sp and + ex1_bop_valid and + ex1_b_expo_min and + not ex1_b_frac_zero and + not(f_pic_ex1_nj_deni and not ex1_from_integer) and + ex1_b_expo(5) ; + + ex1_a_den_sp <= f_pic_ex1_ftdiv and + ex1_aop_valid and + ex1_a_expo_min and + not ex1_a_frac_zero and + not f_pic_ex1_nj_deni and + ex1_a_expo(5) ; + + + + ex1_lu_den_part <= ex1_b_frac(1) and + ex1_b_frac(2) and + ex1_b_frac(3) and + ex1_b_frac(4) and + ex1_b_frac(5) and + ex1_b_frac(6) and + ex1_b_frac(7) and + ex1_b_frac(8) and + ex1_b_frac(9) and + ex1_b_frac(10) and + ex1_b_frac(11) and + ex1_b_frac(12) ; + + ex1_recip_lo <= + ex1_b_frac(14) or + ex1_b_frac(15) or + ex1_b_frac(16) or + ex1_b_frac(17) or + ( ex1_b_frac(18) and ex1_b_frac(19) ) or + ( ex1_b_frac(18) and ex1_b_frac(20) ) ; + + + + + ex1_rsqrt_lo <= + ex1_b_frac(13) or + ex1_b_frac(14) or + ex1_b_frac(15) or + ex1_b_frac(16) or + ( ex1_b_frac(17) and ex1_b_frac(18) ) or + ( ex1_b_frac(17) and ex1_b_frac(19) ) or + ( ex1_b_frac(17) and ex1_b_frac(20) and ex1_b_frac(21) ) ; + + + + ex1_lu_den_recip <= + (ex1_lu_den_part and ex1_b_frac(13) and ex1_recip_lo ); + + ex1_lu_den_rsqrto <= + (ex1_lu_den_part and ex1_rsqrt_lo ); + + f_fmt_ex2_lu_den_recip <= ex2_lu_den_recip; + f_fmt_ex2_lu_den_rsqrto <= ex2_lu_den_rsqrto; + + + + + ex1_a_zero <= ex1_aop_valid and ex1_a_zero_x ; + ex1_c_zero <= ex1_cop_valid and ex1_c_zero_x ; + ex1_b_zero <= ex1_bop_valid and ex1_b_zero_x ; + + + + f_fmt_ex1_a_zero <= ex1_a_zero ; + f_fmt_ex1_a_expo_max <= ex1_aop_valid and ex1_a_expo_max ; + f_fmt_ex1_a_frac_zero <= ex1_a_frac_zero ; + f_fmt_ex1_a_frac_msb <= ex1_a_frac_msb ; + + f_fmt_ex1_c_zero <= ex1_c_zero ; + f_fmt_ex1_c_expo_max <= ex1_cop_valid and ex1_c_expo_max ; + f_fmt_ex1_c_frac_zero <= ex1_c_frac_zero ; + f_fmt_ex1_c_frac_msb <= ex1_c_frac_msb ; + + f_fmt_ex1_b_zero <= ex1_b_zero ; + f_fmt_ex1_b_expo_max <= ex1_bop_valid and ex1_b_expo_max ; + f_fmt_ex1_b_frac_zero <= ex1_b_frac_zero ; + f_fmt_ex1_b_frac_msb <= ex1_b_frac_msb ; + f_fmt_ex1_b_imp <= ex1_b_frac(0) ; + + f_fmt_ex1_prod_zero <= ex1_a_zero or ex1_c_zero ; + + + ex1_a_nan <= ex1_a_expo_max and not ex1_a_frac_zero and not ex1_from_integer and not ex1_sgncpy and not ex1_uc_end_nspec and not ex1_uc_mid and not f_dcd_ex1_perr_fsel_ovrd; + ex1_c_nan <= ex1_c_expo_max and not ex1_c_frac_zero and not ex1_from_integer and not ex1_fsel and not ex1_uc_end_nspec and not ex1_uc_mid; + ex1_b_nan <= ex1_b_expo_max and not ex1_b_frac_zero and not ex1_from_integer and not ex1_fsel and not ex1_uc_end_nspec and not ex1_uc_mid; + + ex1_nan_pass <= ex1_a_nan or ex1_c_nan or ex1_b_nan ; + ex1_pass_sel <= ex1_nan_pass or ex1_fsel or ex1_force_pass ; + + f_fmt_ex1_pass_sel <= ex1_pass_sel ; + + ex1_fsel_cif <= ( ex1_fsel and not ex1_a_sign and not f_dcd_ex1_perr_fsel_ovrd ) or + ( ex1_fsel and ex1_a_zero and not f_dcd_ex1_perr_fsel_ovrd ) or + ( f_dcd_ex1_perr_force_c and f_dcd_ex1_perr_fsel_ovrd ); + + ex1_fsel_bsel <= ex1_fsel and ( ex1_a_nan or not ex1_fsel_cif ); + + ex1_mux_a_sel <= ex1_a_nan and not ex1_fsel; + + ex1_mux_c_sel <= + ( not ex1_a_nan and not ex1_b_nan and ex1_c_nan ) or + ( ex1_a_nan and not ex1_fsel ) or + ( not ex1_a_nan and ex1_fsel and ex1_fsel_cif ); + + ex1_pass_sign_ac <= + ( ex1_mux_a_sel and ex1_a_sign ) or + ( not ex1_mux_a_sel and ex1_c_sign ) ; + ex1_pass_sign <= + ( ex1_mux_c_sel and ex1_pass_sign_ac ) or + ( not ex1_mux_c_sel and ex1_b_sign ) ; + + + ex1_a_frac_chop(0 to 23) <= ex1_a_frac(0 to 23); + ex1_c_frac_chop(0 to 23) <= ex1_c_frac(0 to 23); + ex1_b_frac_chop(0 to 23) <= ex1_b_frac(0 to 23); + + ex1_a_frac_chop(24 to 52) <= ex1_a_frac(24 to 52); + ex1_c_frac_chop(24 to 52) <= ex1_c_frac(24 to 52); + ex1_b_frac_chop(24 to 52) <= ex1_b_frac(24 to 52); + + + ex1_a_expo_ltx381_sp <= ex1_a_expo_ltx381 and ex1_a_sp ; + ex1_c_expo_ltx381_sp <= ex1_c_expo_ltx381 and ex1_c_sp ; + ex1_b_expo_ltx381_sp <= ex1_b_expo_ltx381 and ex1_b_sp ; + + ex1_a_expo_ltx381 <= + ( not ex1_a_expo_b(1) ) or + ( ex1_a_expo_00xx_xxxx_xxxx and not ex1_a_expo_xx11_1xxx_xxxx ) or + ( ex1_a_expo_00xx_xxxx_xxxx and ex1_a_expo_xx11_1xxx_xxxx and ex1_a_expo_xxxx_x000_0000 ) ; + + + ex1_a_expo_00xx_xxxx_xxxx <= ex1_a_expo_b(2) and + ex1_a_expo_b(3) ; + ex1_a_expo_xx11_1xxx_xxxx <= not ex1_a_expo_b(4) and + not ex1_a_expo_b(5) and + not ex1_a_expo_b(6) ; + ex1_a_expo_xxxx_x000_0000 <= ex1_a_expo_b(7) and + ex1_a_expo_b(8) and + ex1_a_expo_b(9) and + ex1_a_expo_b(10) and + ex1_a_expo_b(11) and + ex1_a_expo_b(12) and + ex1_a_expo_b(13) ; + + ex1_c_expo_ltx381 <= + ( not ex1_c_expo_b(1) ) or + ( ex1_c_expo_00xx_xxxx_xxxx and not ex1_c_expo_xx11_1xxx_xxxx ) or + ( ex1_c_expo_00xx_xxxx_xxxx and ex1_c_expo_xx11_1xxx_xxxx and ex1_c_expo_xxxx_x000_0000 ) ; + + + ex1_c_expo_00xx_xxxx_xxxx <= ex1_c_expo_b(2) and + ex1_c_expo_b(3) ; + ex1_c_expo_xx11_1xxx_xxxx <= not ex1_c_expo_b(4) and + not ex1_c_expo_b(5) and + not ex1_c_expo_b(6) ; + ex1_c_expo_xxxx_x000_0000 <= ex1_c_expo_b(7) and + ex1_c_expo_b(8) and + ex1_c_expo_b(9) and + ex1_c_expo_b(10) and + ex1_c_expo_b(11) and + ex1_c_expo_b(12) and + ex1_c_expo_b(13) ; + + + ex1_b_expo_ltx381 <= + ( not ex1_b_expo_b(1) ) or + ( ex1_b_expo_00xx_xxxx_xxxx and not ex1_b_expo_xx11_1xxx_xxxx ) or + ( ex1_b_expo_00xx_xxxx_xxxx and ex1_b_expo_xx11_1xxx_xxxx and ex1_b_expo_xxxx_x000_0000 ) ; + + + ex1_b_expo_00xx_xxxx_xxxx <= ex1_b_expo_b(2) and + ex1_b_expo_b(3) ; + ex1_b_expo_xx11_1xxx_xxxx <= not ex1_b_expo_b(4) and + not ex1_b_expo_b(5) and + not ex1_b_expo_b(6) ; + ex1_b_expo_xxxx_x000_0000 <= ex1_b_expo_b(7) and + ex1_b_expo_b(8) and + ex1_b_expo_b(9) and + ex1_b_expo_b(10) and + ex1_b_expo_b(11) and + ex1_b_expo_b(12) and + ex1_b_expo_b(13) ; + + ex1_pass_frac_ac(0 to 52) <= + ( (0 to 52 => ex1_mux_a_sel) and ex1_a_frac_chop(0 to 52) ) or + ( (0 to 52 => not ex1_mux_a_sel) and ex1_c_frac_chop(0 to 52) ); + ex1_pass_frac(0 to 52) <= + ( (0 to 52 => ex1_mux_c_sel) and ex1_pass_frac_ac(0 to 52) ) or + ( (0 to 52 => not ex1_mux_c_sel) and ex1_b_frac_chop(0 to 52) ); + + + ex1_uc_a_expo_den <= + ( not ex1_a_expo_b(1) ) or + ( ex1_a_expo_b(2) and + ex1_a_expo_b(3) and + ex1_a_expo_b(4) and + ex1_a_expo_b(5) and + ex1_a_expo_b(6) and + ex1_a_expo_b(7) and + ex1_a_expo_b(8) and + ex1_a_expo_b(9) and + ex1_a_expo_b(10) and + ex1_a_expo_b(11) and + ex1_a_expo_b(12) and + ex1_a_expo_b(13) ); + + + + ex1_uc_a_expo_den_sp <= ex1_a_expo_ltx381 ; + + ex1_a_sp_inf_alias_tail <= + not ex1_a_expo_b(7) and + not ex1_a_expo_b(8) and + not ex1_a_expo_b(9) and + not ex1_a_expo_b(10) and + not ex1_a_expo_b(11) and + not ex1_a_expo_b(12) and + not ex1_a_expo_b(13) ; + ex1_c_sp_inf_alias_tail <= + not ex1_c_expo_b(7) and + not ex1_c_expo_b(8) and + not ex1_c_expo_b(9) and + not ex1_c_expo_b(10) and + not ex1_c_expo_b(11) and + not ex1_c_expo_b(12) and + not ex1_c_expo_b(13) ; + ex1_b_sp_inf_alias_tail <= + not ex1_b_expo_b(7) and + not ex1_b_expo_b(8) and + not ex1_b_expo_b(9) and + not ex1_b_expo_b(10) and + not ex1_b_expo_b(11) and + not ex1_b_expo_b(12) and + not ex1_b_expo_b(13) ; + + + ex1_a_sp_expo_ok_1 <= + ex1_a_expo_b(1) and + ex1_a_expo_b(2) and + not ex1_a_expo_b(3) and + ex1_a_expo_b(4) and + ex1_a_expo_b(5) and + ex1_a_expo_b(6) and + not ex1_a_sp_inf_alias_tail ; + + ex1_c_sp_expo_ok_1 <= + ex1_c_expo_b(1) and + ex1_c_expo_b(2) and + not ex1_c_expo_b(3) and + ex1_c_expo_b(4) and + ex1_c_expo_b(5) and + ex1_c_expo_b(6) and + not ex1_c_sp_inf_alias_tail ; + + ex1_b_sp_expo_ok_1 <= + ex1_b_expo_b(1) and + ex1_b_expo_b(2) and + not ex1_b_expo_b(3) and + ex1_b_expo_b(4) and + ex1_b_expo_b(5) and + ex1_b_expo_b(6) and + not ex1_b_sp_inf_alias_tail ; + + ex1_a_sp_expo_ok_2 <= + ex1_a_expo_b(1) and + ex1_a_expo_b(2) and + ex1_a_expo_b(3) and + not ex1_a_expo_b(4) and + not ex1_a_expo_b(5) and + not ex1_a_expo_b(6) ; + + ex1_c_sp_expo_ok_2 <= + ex1_c_expo_b(1) and + ex1_c_expo_b(2) and + ex1_c_expo_b(3) and + not ex1_c_expo_b(4) and + not ex1_c_expo_b(5) and + not ex1_c_expo_b(6) ; + + ex1_b_sp_expo_ok_2 <= + ex1_b_expo_b(1) and + ex1_b_expo_b(2) and + ex1_b_expo_b(3) and + not ex1_b_expo_b(4) and + not ex1_b_expo_b(5) and + not ex1_b_expo_b(6) ; + + + + + + ex1_a_sp_expo_ok_3 <= + ex1_a_expo_b(1) and + ex1_a_expo_b(2) and + ex1_a_expo_b(3) and + not ex1_a_expo_b(4) and + not ex1_a_expo_b(5) and + ex1_a_expo_b(6) and + not ex1_a_expo_b(7) and + not ex1_a_expo_b(8) and + not ex1_a_expo_b(9) ; + + ex1_c_sp_expo_ok_3 <= + ex1_c_expo_b(1) and + ex1_c_expo_b(2) and + ex1_c_expo_b(3) and + not ex1_c_expo_b(4) and + not ex1_c_expo_b(5) and + ex1_c_expo_b(6) and + not ex1_c_expo_b(7) and + not ex1_c_expo_b(8) and + not ex1_c_expo_b(9) ; + + ex1_b_sp_expo_ok_3 <= + ex1_b_expo_b(1) and + ex1_b_expo_b(2) and + ex1_b_expo_b(3) and + not ex1_b_expo_b(4) and + not ex1_b_expo_b(5) and + ex1_b_expo_b(6) and + not ex1_b_expo_b(7) and + not ex1_b_expo_b(8) and + not ex1_b_expo_b(9) ; + + + ex1_a_sp_expo_ok_4 <= + ex1_a_expo_b(1) and + ex1_a_expo_b(2) and + ex1_a_expo_b(3) and + not ex1_a_expo_b(4) and + not ex1_a_expo_b(5) and + ex1_a_expo_b(6) and + not ex1_a_expo_b(7) and + not ex1_a_expo_b(8) and + ex1_a_expo_b(9) and + ( ( not ex1_a_expo_b(10) and not ex1_a_expo_b(11) ) or + ( not ex1_a_expo_b(10) and not ex1_a_expo_b(12) ) ) ; + + + ex1_c_sp_expo_ok_4 <= + ex1_c_expo_b(1) and + ex1_c_expo_b(2) and + ex1_c_expo_b(3) and + not ex1_c_expo_b(4) and + not ex1_c_expo_b(5) and + ex1_c_expo_b(6) and + not ex1_c_expo_b(7) and + not ex1_c_expo_b(8) and + ex1_c_expo_b(9) and + ( ( not ex1_c_expo_b(10) and not ex1_c_expo_b(11) ) or + ( not ex1_c_expo_b(10) and not ex1_c_expo_b(12) ) ) ; + + ex1_b_sp_expo_ok_4 <= + ex1_b_expo_b(1) and + ex1_b_expo_b(2) and + ex1_b_expo_b(3) and + not ex1_b_expo_b(4) and + not ex1_b_expo_b(5) and + ex1_b_expo_b(6) and + not ex1_b_expo_b(7) and + not ex1_b_expo_b(8) and + ex1_b_expo_b(9) and + ( ( not ex1_b_expo_b(10) and not ex1_b_expo_b(11) ) or + ( not ex1_b_expo_b(10) and not ex1_b_expo_b(12) ) ) ; + + + + + + + + + + f_fmt_ex1_sp_invalid <= + ( not ex1_a_sp_expo_ok_1 and + not ex1_a_sp_expo_ok_2 and + not ex1_a_sp_expo_ok_3 and + not ex1_a_sp_expo_ok_4 and + not ex1_a_expo_max and + not ex1_a_zero_x ) or + ( not ex1_c_sp_expo_ok_1 and + not ex1_c_sp_expo_ok_2 and + not ex1_c_sp_expo_ok_3 and + not ex1_c_sp_expo_ok_4 and + not ex1_c_expo_max and + not ex1_c_zero_x ) or + ( not ex1_b_sp_expo_ok_1 and + not ex1_b_sp_expo_ok_2 and + not ex1_b_sp_expo_ok_3 and + not ex1_b_sp_expo_ok_4 and + not ex1_b_expo_max and + not ex1_b_zero_x ) ; + + + + + + ex1_a_party(0) <= ex1_a_sign xor ex1_a_expo(2) xor ex1_a_expo(3) xor ex1_a_expo(4) xor ex1_a_expo(5) xor + ex1_a_expo(6) xor ex1_a_expo(7) xor ex1_a_expo(8) xor ex1_a_expo(9) ; + ex1_a_party(1) <= ex1_a_expo(10) xor ex1_a_expo(11) xor ex1_a_expo(12) xor ex1_a_expo(13) xor ex1_a_frac(0) xor + ex1_a_frac(1) xor ex1_a_frac(2) xor ex1_a_frac(3) xor ex1_a_frac(4) ; + ex1_a_party(2) <= ex1_a_frac(5) xor ex1_a_frac(6) xor ex1_a_frac(7) xor ex1_a_frac(8) xor + ex1_a_frac(9) xor ex1_a_frac(10) xor ex1_a_frac(11) xor ex1_a_frac(12) ; + ex1_a_party(3) <= ex1_a_frac(13) xor ex1_a_frac(14) xor ex1_a_frac(15) xor ex1_a_frac(16) xor + ex1_a_frac(17) xor ex1_a_frac(18) xor ex1_a_frac(19) xor ex1_a_frac(20) ; + ex1_a_party(4) <= ex1_a_frac(21) xor ex1_a_frac(22) xor ex1_a_frac(23) xor ex1_a_frac(24) xor + ex1_a_frac(25) xor ex1_a_frac(26) xor ex1_a_frac(27) xor ex1_a_frac(28) ; + ex1_a_party(5) <= ex1_a_frac(29) xor ex1_a_frac(30) xor ex1_a_frac(31) xor ex1_a_frac(32) xor + ex1_a_frac(33) xor ex1_a_frac(34) xor ex1_a_frac(35) xor ex1_a_frac(36) ; + ex1_a_party(6) <= ex1_a_frac(37) xor ex1_a_frac(38) xor ex1_a_frac(39) xor ex1_a_frac(40) xor + ex1_a_frac(41) xor ex1_a_frac(42) xor ex1_a_frac(43) xor ex1_a_frac(44) ; + ex1_a_party(7) <= ex1_a_frac(45) xor ex1_a_frac(46) xor ex1_a_frac(47) xor ex1_a_frac(48) xor + ex1_a_frac(49) xor ex1_a_frac(50) xor ex1_a_frac(51) xor ex1_a_frac(52) ; + + ex1_c_party(0) <= ex1_c_sign xor ex1_c_expo(2) xor ex1_c_expo(3) xor ex1_c_expo(4) xor ex1_c_expo(5) xor + ex1_c_expo(6) xor ex1_c_expo(7) xor ex1_c_expo(8) xor ex1_c_expo(9) ; + ex1_c_party(1) <= ex1_c_expo(10) xor ex1_c_expo(11) xor ex1_c_expo(12) xor ex1_c_expo(13) xor ex1_c_frac(0) xor + ex1_c_frac(1) xor ex1_c_frac(2) xor ex1_c_frac(3) xor ex1_c_frac(4) ; + ex1_c_party(2) <= ex1_c_frac(5) xor ex1_c_frac(6) xor ex1_c_frac(7) xor ex1_c_frac(8) xor + ex1_c_frac(9) xor ex1_c_frac(10) xor ex1_c_frac(11) xor ex1_c_frac(12) ; + ex1_c_party(3) <= ex1_c_frac(13) xor ex1_c_frac(14) xor ex1_c_frac(15) xor ex1_c_frac(16) xor + ex1_c_frac(17) xor ex1_c_frac(18) xor ex1_c_frac(19) xor ex1_c_frac(20) ; + ex1_c_party(4) <= ex1_c_frac(21) xor ex1_c_frac(22) xor ex1_c_frac(23) xor ex1_c_frac(24) xor + ex1_c_frac(25) xor ex1_c_frac(26) xor ex1_c_frac(27) xor ex1_c_frac(28) ; + ex1_c_party(5) <= ex1_c_frac(29) xor ex1_c_frac(30) xor ex1_c_frac(31) xor ex1_c_frac(32) xor + ex1_c_frac(33) xor ex1_c_frac(34) xor ex1_c_frac(35) xor ex1_c_frac(36) ; + ex1_c_party(6) <= ex1_c_frac(37) xor ex1_c_frac(38) xor ex1_c_frac(39) xor ex1_c_frac(40) xor + ex1_c_frac(41) xor ex1_c_frac(42) xor ex1_c_frac(43) xor ex1_c_frac(44) ; + ex1_c_party(7) <= ex1_c_frac(45) xor ex1_c_frac(46) xor ex1_c_frac(47) xor ex1_c_frac(48) xor + ex1_c_frac(49) xor ex1_c_frac(50) xor ex1_c_frac(51) xor ex1_c_frac(52) ; + + + ex1_b_party(0) <= ex1_b_sign xor ex1_b_expo(2) xor ex1_b_expo(3) xor ex1_b_expo(4) xor ex1_b_expo(5) xor + ex1_b_expo(6) xor ex1_b_expo(7) xor ex1_b_expo(8) xor ex1_b_expo(9) ; + ex1_b_party(1) <= ex1_b_expo(10) xor ex1_b_expo(11) xor ex1_b_expo(12) xor ex1_b_expo(13) xor ex1_b_frac(0) xor + ex1_b_frac(1) xor ex1_b_frac(2) xor ex1_b_frac(3) xor ex1_b_frac(4) ; + ex1_b_party(2) <= ex1_b_frac(5) xor ex1_b_frac(6) xor ex1_b_frac(7) xor ex1_b_frac(8) xor + ex1_b_frac(9) xor ex1_b_frac(10) xor ex1_b_frac(11) xor ex1_b_frac(12) ; + ex1_b_party(3) <= ex1_b_frac(13) xor ex1_b_frac(14) xor ex1_b_frac(15) xor ex1_b_frac(16) xor + ex1_b_frac(17) xor ex1_b_frac(18) xor ex1_b_frac(19) xor ex1_b_frac(20) ; + ex1_b_party(4) <= ex1_b_frac(21) xor ex1_b_frac(22) xor ex1_b_frac(23) xor ex1_b_frac(24) xor + ex1_b_frac(25) xor ex1_b_frac(26) xor ex1_b_frac(27) xor ex1_b_frac(28) ; + ex1_b_party(5) <= ex1_b_frac(29) xor ex1_b_frac(30) xor ex1_b_frac(31) xor ex1_b_frac(32) xor + ex1_b_frac(33) xor ex1_b_frac(34) xor ex1_b_frac(35) xor ex1_b_frac(36) ; + ex1_b_party(6) <= ex1_b_frac(37) xor ex1_b_frac(38) xor ex1_b_frac(39) xor ex1_b_frac(40) xor + ex1_b_frac(41) xor ex1_b_frac(42) xor ex1_b_frac(43) xor ex1_b_frac(44) ; + ex1_b_party(7) <= ex1_b_frac(45) xor ex1_b_frac(46) xor ex1_b_frac(47) xor ex1_b_frac(48) xor + ex1_b_frac(49) xor ex1_b_frac(50) xor ex1_b_frac(51) xor ex1_b_frac(52) ; + + + ex1_a_party_chick <= (ex1_a_party(0) xor f_fpr_ex1_a_par(0) ) or + (ex1_a_party(1) xor f_fpr_ex1_a_par(1) ) or + (ex1_a_party(2) xor f_fpr_ex1_a_par(2) ) or + (ex1_a_party(3) xor f_fpr_ex1_a_par(3) ) or + (ex1_a_party(4) xor f_fpr_ex1_a_par(4) ) or + (ex1_a_party(5) xor f_fpr_ex1_a_par(5) ) or + (ex1_a_party(6) xor f_fpr_ex1_a_par(6) ) or + (ex1_a_party(7) xor f_fpr_ex1_a_par(7) ) ; + + ex1_c_party_chick <= (ex1_c_party(0) xor f_fpr_ex1_c_par(0) ) or + (ex1_c_party(1) xor f_fpr_ex1_c_par(1) ) or + (ex1_c_party(2) xor f_fpr_ex1_c_par(2) ) or + (ex1_c_party(3) xor f_fpr_ex1_c_par(3) ) or + (ex1_c_party(4) xor f_fpr_ex1_c_par(4) ) or + (ex1_c_party(5) xor f_fpr_ex1_c_par(5) ) or + (ex1_c_party(6) xor f_fpr_ex1_c_par(6) ) or + (ex1_c_party(7) xor f_fpr_ex1_c_par(7) ) ; + + ex1_b_party_chick <= (ex1_b_party(0) xor f_fpr_ex1_b_par(0) ) or + (ex1_b_party(1) xor f_fpr_ex1_b_par(1) ) or + (ex1_b_party(2) xor f_fpr_ex1_b_par(2) ) or + (ex1_b_party(3) xor f_fpr_ex1_b_par(3) ) or + (ex1_b_party(4) xor f_fpr_ex1_b_par(4) ) or + (ex1_b_party(5) xor f_fpr_ex1_b_par(5) ) or + (ex1_b_party(6) xor f_fpr_ex1_b_par(6) ) or + (ex1_b_party(7) xor f_fpr_ex1_b_par(7) ) ; + + + + + + ex1_be_den <= + ( ex1_b_expo(1) ) or + ( not ex1_b_expo(2) and + not ex1_b_expo(3) and + not ex1_b_expo(4) and + not ex1_b_expo(5) and + not ex1_b_expo(6) and + not ex1_b_expo(7) and + not ex1_b_expo(8) and + not ex1_b_expo(9) and + not ex1_b_expo(10) and + not ex1_b_expo(11) and + not ex1_b_expo(12) and + not ex1_b_expo(13) ); + + + + ex1_ae_234567 <= ex1_a_expo(2) or ex1_a_expo(3) or ex1_a_expo(4) or + ex1_a_expo(5) or ex1_a_expo(6) or ex1_a_expo(7) ; + ex1_ae_89 <= ex1_a_expo(8) and ex1_a_expo(9) ; + ex1_ae_abc <= ex1_a_expo(10) or (ex1_a_expo(11) and ex1_a_expo(12) ) ; + + ex1_ae_ge_54 <= + (not ex1_a_expo(1) and ex1_ae_234567 ) or + (not ex1_a_expo(1) and ex1_ae_89 and ex1_ae_abc ) ; + + ex1_be_234567 <= ex1_b_expo(2) or ex1_b_expo(3) or ex1_b_expo(4) or + ex1_b_expo(5) or ex1_b_expo(6) or ex1_b_expo(7) ; + ex1_be_89 <= ex1_b_expo(8) and ex1_b_expo(9) ; + ex1_be_abc <= ex1_b_expo(10) or (ex1_b_expo(11) and ex1_b_expo(12) ) ; + + ex1_be_ge_54 <= + (not ex1_b_expo(1) and ex1_be_234567 ) or + (not ex1_b_expo(1) and ex1_be_89 and ex1_be_abc ) ; + + + ex1_be_or_23456789abc <= + ex1_b_expo(2) or + ex1_b_expo(3) or + ex1_b_expo(4) or + ex1_b_expo(5) or + ex1_b_expo(6) or + ex1_b_expo(7) or + ex1_b_expo(8) or + ex1_b_expo(9) or + ex1_b_expo(10) or + ex1_b_expo(11) or + ex1_b_expo(12) ; + + ex1_be_and_3456789ab <= + ex1_b_expo(3) and + ex1_b_expo(4) and + ex1_b_expo(5) and + ex1_b_expo(6) and + ex1_b_expo(7) and + ex1_b_expo(8) and + ex1_b_expo(9) and + ex1_b_expo(10) and + ex1_b_expo(11) ; + + ex1_be_ge_2 <= not ex1_b_expo(1) and ex1_be_or_23456789abc ; + ex1_be_ge_2044 <= ( not ex1_b_expo(1) and ex1_be_and_3456789ab ) or + ( not ex1_b_expo(1) and ex1_b_expo(2) ) ; + + + + + + ex1_aembex_car_b( 0) <= not( ex1_a_expo( 1) or ex1_b_expo_b( 1) ) ; + ex1_aembex_car_b( 1) <= not( ex1_a_expo( 2) or ex1_b_expo_b( 2) ) ; + ex1_aembex_car_b( 2) <= not( ex1_a_expo( 3) or ex1_b_expo_b( 3) ) ; + ex1_aembex_car_b( 3) <= not( ex1_a_expo( 4) and ex1_b_expo_b( 4) ) ; + ex1_aembex_car_b( 4) <= not( ex1_a_expo( 5) and ex1_b_expo_b( 5) ) ; + ex1_aembex_car_b( 5) <= not( ex1_a_expo( 6) and ex1_b_expo_b( 6) ) ; + ex1_aembex_car_b( 6) <= not( ex1_a_expo( 7) and ex1_b_expo_b( 7) ) ; + ex1_aembex_car_b( 7) <= not( ex1_a_expo( 8) and ex1_b_expo_b( 8) ) ; + ex1_aembex_car_b( 8) <= not( ex1_a_expo( 9) and ex1_b_expo_b( 9) ) ; + ex1_aembex_car_b( 9) <= not( ex1_a_expo(10) and ex1_b_expo_b(10) ) ; + ex1_aembex_car_b(10) <= not( ex1_a_expo(11) and ex1_b_expo_b(11) ) ; + ex1_aembex_car_b(11) <= not( ex1_a_expo(12) or ex1_b_expo_b(12) ) ; + ex1_aembex_car_b(12) <= not( ex1_a_expo(13) and ex1_b_expo_b(13) ) ; + + ex1_aembex_sum_b( 1) <= ( ex1_a_expo( 1) xor ex1_b_expo_b( 1) ) ; + ex1_aembex_sum_b( 2) <= ( ex1_a_expo( 2) xor ex1_b_expo_b( 2) ) ; + ex1_aembex_sum_b( 3) <= ( ex1_a_expo( 3) xor ex1_b_expo_b( 3) ) ; + ex1_aembex_sum_b( 4) <= not( ex1_a_expo( 4) xor ex1_b_expo_b( 4) ) ; + ex1_aembex_sum_b( 5) <= not( ex1_a_expo( 5) xor ex1_b_expo_b( 5) ) ; + ex1_aembex_sum_b( 6) <= not( ex1_a_expo( 6) xor ex1_b_expo_b( 6) ) ; + ex1_aembex_sum_b( 7) <= not( ex1_a_expo( 7) xor ex1_b_expo_b( 7) ) ; + ex1_aembex_sum_b( 8) <= not( ex1_a_expo( 8) xor ex1_b_expo_b( 8) ) ; + ex1_aembex_sum_b( 9) <= not( ex1_a_expo( 9) xor ex1_b_expo_b( 9) ) ; + ex1_aembex_sum_b(10) <= not( ex1_a_expo(10) xor ex1_b_expo_b(10) ) ; + ex1_aembex_sum_b(11) <= not( ex1_a_expo(11) xor ex1_b_expo_b(11) ) ; + ex1_aembex_sum_b(12) <= ( ex1_a_expo(12) xor ex1_b_expo_b(12) ) ; + ex1_aembex_sum_b(13) <= not( ex1_a_expo(13) xor ex1_b_expo_b(13) ) ; + + + ex1_aembex_sgn <= ex1_aembex_sum_b(1) xor ex1_aembex_car_b(1) ; + + ex1_aembex_g1(2 to 12) <= not(ex1_aembex_sum_b(2 to 12) or ex1_aembex_car_b(2 to 12) ); + ex1_aembex_t1(2 to 12) <= not(ex1_aembex_sum_b(2 to 12) and ex1_aembex_car_b(2 to 12) ); + + + ex1_aembex_g2(0) <= ex1_aembex_g1( 2) or ( ex1_aembex_t1( 2) and ex1_aembex_g1( 3) ); + ex1_aembex_g2(1) <= ex1_aembex_g1( 4) or ( ex1_aembex_t1( 4) and ex1_aembex_g1( 5) ); + ex1_aembex_g2(2) <= ex1_aembex_g1( 6) or ( ex1_aembex_t1( 6) and ex1_aembex_g1( 7) ); + ex1_aembex_g2(3) <= ex1_aembex_g1( 8) or ( ex1_aembex_t1( 8) and ex1_aembex_g1( 9) ); + ex1_aembex_g2(4) <= ex1_aembex_g1(10) or ( ex1_aembex_t1(10) and ex1_aembex_g1(11) ); + ex1_aembex_g2(5) <= ex1_aembex_g1(12) ; + + ex1_aembex_t2(0) <= ( ex1_aembex_t1( 2) and ex1_aembex_t1( 3) ); + ex1_aembex_t2(1) <= ( ex1_aembex_t1( 4) and ex1_aembex_t1( 5) ); + ex1_aembex_t2(2) <= ( ex1_aembex_t1( 6) and ex1_aembex_t1( 7) ); + ex1_aembex_t2(3) <= ( ex1_aembex_t1( 8) and ex1_aembex_t1( 9) ); + ex1_aembex_t2(4) <= ( ex1_aembex_t1(10) and ex1_aembex_t1(11) ); + + + ex1_aembex_g4(0) <= ex1_aembex_g2( 0) or ( ex1_aembex_t2( 0) and ex1_aembex_g2( 1) ); + ex1_aembex_g4(1) <= ex1_aembex_g2( 2) or ( ex1_aembex_t2( 2) and ex1_aembex_g2( 3) ); + ex1_aembex_g4(2) <= ex1_aembex_g2( 4) or ( ex1_aembex_t2( 4) and ex1_aembex_g2( 5) ); + + ex1_aembex_t4(0) <= ( ex1_aembex_t2( 0) and ex1_aembex_t2( 1) ); + ex1_aembex_t4(1) <= ( ex1_aembex_t2( 2) and ex1_aembex_t2( 3) ); + + + + ex1_aembey_car_b( 0) <= not( ex1_a_expo( 1) and ex1_b_expo_b( 1) ) ; + ex1_aembey_car_b( 1) <= not( ex1_a_expo( 2) and ex1_b_expo_b( 2) ) ; + ex1_aembey_car_b( 2) <= not( ex1_a_expo( 3) and ex1_b_expo_b( 3) ) ; + ex1_aembey_car_b( 3) <= not( ex1_a_expo( 4) or ex1_b_expo_b( 4) ) ; + ex1_aembey_car_b( 4) <= not( ex1_a_expo( 5) or ex1_b_expo_b( 5) ) ; + ex1_aembey_car_b( 5) <= not( ex1_a_expo( 6) or ex1_b_expo_b( 6) ) ; + ex1_aembey_car_b( 6) <= not( ex1_a_expo( 7) or ex1_b_expo_b( 7) ) ; + ex1_aembey_car_b( 7) <= not( ex1_a_expo( 8) or ex1_b_expo_b( 8) ) ; + ex1_aembey_car_b( 8) <= not( ex1_a_expo( 9) or ex1_b_expo_b( 9) ) ; + ex1_aembey_car_b( 9) <= not( ex1_a_expo(10) or ex1_b_expo_b(10) ) ; + ex1_aembey_car_b(10) <= not( ex1_a_expo(11) or ex1_b_expo_b(11) ) ; + ex1_aembey_car_b(11) <= not( ex1_a_expo(12) and ex1_b_expo_b(12) ) ; + ex1_aembey_car_b(12) <= not( ex1_a_expo(13) or ex1_b_expo_b(13) ) ; + + ex1_aembey_sum_b( 1) <= not( ex1_a_expo( 1) xor ex1_b_expo_b( 1) ) ; + ex1_aembey_sum_b( 2) <= not( ex1_a_expo( 2) xor ex1_b_expo_b( 2) ) ; + ex1_aembey_sum_b( 3) <= not( ex1_a_expo( 3) xor ex1_b_expo_b( 3) ) ; + ex1_aembey_sum_b( 4) <= ( ex1_a_expo( 4) xor ex1_b_expo_b( 4) ) ; + ex1_aembey_sum_b( 5) <= ( ex1_a_expo( 5) xor ex1_b_expo_b( 5) ) ; + ex1_aembey_sum_b( 6) <= ( ex1_a_expo( 6) xor ex1_b_expo_b( 6) ) ; + ex1_aembey_sum_b( 7) <= ( ex1_a_expo( 7) xor ex1_b_expo_b( 7) ) ; + ex1_aembey_sum_b( 8) <= ( ex1_a_expo( 8) xor ex1_b_expo_b( 8) ) ; + ex1_aembey_sum_b( 9) <= ( ex1_a_expo( 9) xor ex1_b_expo_b( 9) ) ; + ex1_aembey_sum_b(10) <= ( ex1_a_expo(10) xor ex1_b_expo_b(10) ) ; + ex1_aembey_sum_b(11) <= ( ex1_a_expo(11) xor ex1_b_expo_b(11) ) ; + ex1_aembey_sum_b(12) <= not( ex1_a_expo(12) xor ex1_b_expo_b(12) ) ; + ex1_aembey_sum_b(13) <= ( ex1_a_expo(13) xor ex1_b_expo_b(13) ) ; + + + ex1_aembey_sgn <= ex1_aembey_sum_b(1) xor ex1_aembey_car_b(1) ; + + ex1_aembey_g1(2 to 12) <= not(ex1_aembey_sum_b(2 to 12) or ex1_aembey_car_b(2 to 12) ); + ex1_aembey_t1(2 to 12) <= not(ex1_aembey_sum_b(2 to 12) and ex1_aembey_car_b(2 to 12) ); + + + ex1_aembey_g2(0) <= ex1_aembey_g1( 2) or ( ex1_aembey_t1( 2) and ex1_aembey_g1( 3) ); + ex1_aembey_g2(1) <= ex1_aembey_g1( 4) or ( ex1_aembey_t1( 4) and ex1_aembey_g1( 5) ); + ex1_aembey_g2(2) <= ex1_aembey_g1( 6) or ( ex1_aembey_t1( 6) and ex1_aembey_g1( 7) ); + ex1_aembey_g2(3) <= ex1_aembey_g1( 8) or ( ex1_aembey_t1( 8) and ex1_aembey_g1( 9) ); + ex1_aembey_g2(4) <= ex1_aembey_g1(10) or ( ex1_aembey_t1(10) and ex1_aembey_g1(11) ); + ex1_aembey_g2(5) <= ex1_aembey_g1(12) ; + + ex1_aembey_t2(0) <= ( ex1_aembey_t1( 2) and ex1_aembey_t1( 3) ); + ex1_aembey_t2(1) <= ( ex1_aembey_t1( 4) and ex1_aembey_t1( 5) ); + ex1_aembey_t2(2) <= ( ex1_aembey_t1( 6) and ex1_aembey_t1( 7) ); + ex1_aembey_t2(3) <= ( ex1_aembey_t1( 8) and ex1_aembey_t1( 9) ); + ex1_aembey_t2(4) <= ( ex1_aembey_t1(10) and ex1_aembey_t1(11) ); + + + ex1_aembey_g4(0) <= ex1_aembey_g2( 0) or ( ex1_aembey_t2( 0) and ex1_aembey_g2( 1) ); + ex1_aembey_g4(1) <= ex1_aembey_g2( 2) or ( ex1_aembey_t2( 2) and ex1_aembey_g2( 3) ); + ex1_aembey_g4(2) <= ex1_aembey_g2( 4) or ( ex1_aembey_t2( 4) and ex1_aembey_g2( 5) ); + + ex1_aembey_t4(0) <= ( ex1_aembey_t2( 0) and ex1_aembey_t2( 1) ); + ex1_aembey_t4(1) <= ( ex1_aembey_t2( 2) and ex1_aembey_t2( 3) ); + + + + + + + + ex2_pass_lat: tri_rlmreg_p generic map (width=> 80, expand_type => expand_type, ibuf => true, needs_sreset => 0) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(2) , + mpw1_b => mpw1_b(2) , + mpw2_b => mpw2_b(0) , + vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_act, + thold_b => thold_0_b, + sg => sg_0, + scout => ex2_pass_so , + scin => ex2_pass_si , + din(0) => ex1_fsel_bsel , + din(1) => ex1_pass_sign , + din(2 to 54) => ex1_pass_frac(0 to 52) , + din(55) => ex1_b_den_flush, + din(56) => ex1_lu_den_recip, + din(57) => ex1_lu_den_rsqrto , + din(58) => ex1_uc_a_expo_den , + din(59) => ex1_uc_a_expo_den_sp , + din(60) => ex1_a_party_chick , + din(61) => ex1_c_party_chick , + din(62) => ex1_b_party_chick , + din(63) => ex1_ae_ge_54 , + din(64) => ex1_be_ge_54 , + din(65) => ex1_be_ge_2 , + din(66) => ex1_be_ge_2044 , + din(67) => ex1_aembex_g4(0) , + din(68) => ex1_aembex_t4(0) , + din(69) => ex1_aembex_g4(1) , + din(70) => ex1_aembex_t4(1) , + din(71) => ex1_aembex_g4(2) , + din(72) => ex1_aembey_g4(0) , + din(73) => ex1_aembey_t4(0) , + din(74) => ex1_aembey_g4(1) , + din(75) => ex1_aembey_t4(1) , + din(76) => ex1_aembey_g4(2) , + din(77) => ex1_aembex_sgn , + din(78) => ex1_aembey_sgn , + din(79) => ex1_be_den , + dout(0) => ex2_fsel_bsel , + dout(1) => ex2_pass_sign , + dout(2 to 54) => ex2_pass_frac (0 to 52), + dout(55) => ex2_b_den_flush , + dout(56) => ex2_lu_den_recip, + dout(57) => ex2_lu_den_rsqrto, + dout(58) => ex2_uc_a_expo_den , + dout(59) => ex2_uc_a_expo_den_sp , + dout(60) => ex2_a_party_chick , + dout(61) => ex2_c_party_chick , + dout(62) => ex2_b_party_chick , + dout(63) => ex2_ae_ge_54 , + dout(64) => ex2_be_ge_54 , + dout(65) => ex2_be_ge_2 , + dout(66) => ex2_be_ge_2044 , + dout(67) => ex2_aembex_g4(0) , + dout(68) => ex2_aembex_t4(0) , + dout(69) => ex2_aembex_g4(1) , + dout(70) => ex2_aembex_t4(1) , + dout(71) => ex2_aembex_g4(2) , + dout(72) => ex2_aembey_g4(0) , + dout(73) => ex2_aembey_t4(0) , + dout(74) => ex2_aembey_g4(1) , + dout(75) => ex2_aembey_t4(1) , + dout(76) => ex2_aembey_g4(2) , + dout(77) => ex2_aembex_sgn , + dout(78) => ex2_aembey_sgn , + dout(79) => ex2_be_den ); + + + f_mad_ex2_a_parity_check <= ex2_a_party_chick ; + f_mad_ex2_c_parity_check <= ex2_c_party_chick ; + f_mad_ex2_b_parity_check <= ex2_b_party_chick ; + + + f_mad_ex2_uc_a_expo_den <= ex2_uc_a_expo_den ; + f_mad_ex2_uc_a_expo_den_sp <= ex2_uc_a_expo_den_sp ; + f_ex2_b_den_flush <= ex2_b_den_flush ; + + f_fmt_ex2_fsel_bsel <= ex2_fsel_bsel ; + f_fmt_ex2_pass_sign <= ex2_pass_sign ; + f_fmt_ex2_pass_msb <= ex2_pass_frac(1) ; + + ex2_pass_dp( 0 to 52) <= ex2_pass_frac(0 to 52) ; + f_fmt_ex2_pass_frac(0 to 52) <= ex2_pass_dp(0 to 52) ; + + + + ex2_aembex_g8(0) <= ex2_aembex_g4(0) or ( ex2_aembex_t4(0) and ex2_aembex_g4(1) ); + ex2_aembex_g8(1) <= ex2_aembex_g4(2) ; + ex2_aembex_t8(0) <= ( ex2_aembex_t4(0) and ex2_aembex_t4(1) ); + ex2_aembex_c2 <= ex2_aembex_g8(0) or ( ex2_aembex_t8(0) and ex2_aembex_g8(1) ); + + ex2_aembey_g8(0) <= ex2_aembey_g4(0) or ( ex2_aembey_t4(0) and ex2_aembey_g4(1) ); + ex2_aembey_g8(1) <= ex2_aembey_g4(2) ; + ex2_aembey_t8(0) <= ( ex2_aembey_t4(0) and ex2_aembey_t4(1) ); + ex2_aembey_c2 <= ex2_aembey_g8(0) or ( ex2_aembey_t8(0) and ex2_aembey_g8(1) ); + + ex2_aembex_res_sgn <= ex2_aembex_c2 xor ex2_aembex_sgn ; + ex2_aembey_res_sgn <= ex2_aembey_c2 xor ex2_aembey_sgn ; + + + f_fmt_ex2_tdiv_rng_chk <= + ( not ex2_aembex_res_sgn ) or + ( ex2_aembey_res_sgn ) ; + + f_fmt_ex2_be_den <= ex2_be_den ; + + f_fmt_ex2_ae_ge_54 <= ex2_ae_ge_54 ; + f_fmt_ex2_be_ge_54 <= ex2_be_ge_54 ; + f_fmt_ex2_be_ge_2 <= ex2_be_ge_2 ; + f_fmt_ex2_be_ge_2044 <= ex2_be_ge_2044 ; + + + + + + + + ex1_ctl_si (0 to 8) <= ex1_ctl_so (1 to 8) & f_fmt_si ; + ex2_pass_si (0 to 79) <= ex2_pass_so (1 to 79) & ex1_ctl_so (0); + act_si (0 to 6) <= act_so (1 to 6) & ex2_pass_so (0); + f_fmt_so <= act_so (0); + + + +end; + + + + + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_fpr.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_fpr.vhdl new file mode 100644 index 0000000..457a52a --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_fpr.vhdl @@ -0,0 +1,1386 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library IEEE,ibm; +use IEEE.STD_LOGIC_1164.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_support.all; + +library support; +use support.power_logic_pkg.all; + +library tri; use tri.tri_latches_pkg.all; + +entity fuq_fpr is +generic( + expand_type : integer := 2 ); +port( + + + nclk : in clk_logic; + clkoff_b : in std_ulogic; + act_dis : in std_ulogic; + flush : in std_ulogic; + delay_lclkra : in std_ulogic_vector(0 to 1); + delay_lclkrb : in std_ulogic_vector(6 to 7); + mpw1_ba : in std_ulogic_vector(0 to 1); + mpw1_bb : in std_ulogic_vector(6 to 7); + mpw2_b : in std_ulogic_vector(0 to 1); + abst_sl_thold_1 : in std_ulogic; + time_sl_thold_1 : in std_ulogic; + ary_nsl_thold_1 : in std_ulogic; + gptr_sl_thold_0 : in std_ulogic; + fce_1 : in std_ulogic; + thold_1 : in std_ulogic; + sg_1 : in std_ulogic; + scan_dis_dc_b : in std_ulogic; + scan_diag_dc : in std_ulogic; + lbist_en_dc : in std_ulogic; + an_ac_abist_mode_dc : in std_ulogic; + an_ac_lbist_ary_wrt_thru_dc : in std_ulogic; + f_dcd_msr_fp_act : in std_ulogic; + + iu_fu_rf0_fra_v : in std_ulogic; + iu_fu_rf0_frb_v : in std_ulogic; + iu_fu_rf0_frc_v : in std_ulogic; + iu_fu_rf0_str_v : in std_ulogic; + f_dcd_perr_sm_running : in std_ulogic; + + pc_fu_bolt_sl_thold_3 : in std_ulogic; + pc_fu_bo_enable_3 : in std_ulogic; + pc_fu_bo_unload : in std_ulogic; + pc_fu_bo_load : in std_ulogic; + pc_fu_bo_reset : in std_ulogic; + pc_fu_bo_shdata : in std_ulogic; + pc_fu_bo_select : in std_ulogic_vector(0 to 1); + fu_pc_bo_fail : out std_ulogic_vector(0 to 1); + fu_pc_bo_diagout : out std_ulogic_vector(0 to 1); + + bx_fu_rp_abst_scan_out : in std_ulogic; + bx_rp_abst_scan_out : out std_ulogic; + rp_bx_abst_scan_in : in std_ulogic; + rp_fu_bx_abst_scan_in : out std_ulogic; + rp_bx_func_scan_in : in std_ulogic_vector(0 to 1); + rp_fu_bx_func_scan_in : out std_ulogic_vector(0 to 1); + bx_fu_rp_func_scan_out : in std_ulogic_vector(0 to 1); + bx_rp_func_scan_out : out std_ulogic_vector(0 to 1); + + f_fpr_si : in std_ulogic; + f_fpr_so : out std_ulogic; + f_fpr_ab_si : in std_ulogic; + f_fpr_ab_so : out std_ulogic; + time_scan_in : in std_ulogic; + time_scan_out : out std_ulogic; + gptr_scan_in : in std_ulogic; + gptr_scan_out : out std_ulogic; + vdd : inout power_logic; + gnd : inout power_logic; + pc_fu_abist_di_0 : in std_ulogic_vector(0 to 3); + pc_fu_abist_di_1 : in std_ulogic_vector(0 to 3); + pc_fu_abist_ena_dc : in std_ulogic; + pc_fu_abist_grf_renb_0 : in std_ulogic; + pc_fu_abist_grf_renb_1 : in std_ulogic; + pc_fu_abist_grf_wenb_0 : in std_ulogic; + pc_fu_abist_grf_wenb_1 : in std_ulogic; + pc_fu_abist_raddr_0 : in std_ulogic_vector(0 to 9); + pc_fu_abist_raddr_1 : in std_ulogic_vector(0 to 9); + pc_fu_abist_raw_dc_b : in std_ulogic; + pc_fu_abist_waddr_0 : in std_ulogic_vector(0 to 9); + pc_fu_abist_waddr_1 : in std_ulogic_vector(0 to 9); + pc_fu_abist_wl144_comp_ena : in std_ulogic; + pc_fu_inj_regfile_parity : in std_ulogic_vector(0 to 3); + + f_dcd_rf0_tid : in std_ulogic_vector(0 to 1); + f_dcd_rf0_fra : in std_ulogic_vector(0 to 5); + f_dcd_rf0_frb : in std_ulogic_vector(0 to 5); + f_dcd_rf0_frc : in std_ulogic_vector(0 to 5); + iu_fu_rf0_ldst_tid : in std_ulogic_vector(0 to 1); + iu_fu_rf0_ldst_tag : in std_ulogic_vector(0 to 8); + f_dcd_rf0_bypsel_a_res1 : in std_ulogic; + f_dcd_rf0_bypsel_b_res1 : in std_ulogic; + f_dcd_rf0_bypsel_c_res1 : in std_ulogic; + f_dcd_rf0_bypsel_s_res1 : in std_ulogic; + f_dcd_rf0_bypsel_a_load1 : in std_ulogic; + f_dcd_rf0_bypsel_b_load1 : in std_ulogic; + f_dcd_rf0_bypsel_c_load1 : in std_ulogic; + f_dcd_rf0_bypsel_s_load1 : in std_ulogic; + f_dcd_ex5_frt_tid : in std_ulogic_vector(0 to 1); + f_dcd_ex5_flush_int : in std_ulogic_vector(0 to 3); + f_dcd_ex6_frt_addr : in std_ulogic_vector(0 to 5); + f_dcd_ex6_frt_tid : in std_ulogic_vector(0 to 1); + f_dcd_ex6_frt_wen : in std_ulogic; + f_rnd_ex6_res_expo : in std_ulogic_vector (1 to 13); + f_rnd_ex6_res_frac : in std_ulogic_vector (0 to 52); + f_rnd_ex6_res_sign : in std_ulogic ; + xu_fu_ex5_load_val : in std_ulogic_vector(0 to 3); + xu_fu_ex5_load_tag : in std_ulogic_vector(0 to 8); + xu_fu_ex6_load_data : in std_ulogic_vector(192 to 255); + f_fpr_ex7_load_addr : out std_ulogic_vector(0 to 7); + f_fpr_ex7_load_v : out std_ulogic; + f_fpr_ex7_load_sign : out std_ulogic; + f_fpr_ex7_load_expo : out std_ulogic_vector(3 to 13); + f_fpr_ex7_load_frac : out std_ulogic_vector(0 to 52); + f_fpr_rf1_s_sign : out std_ulogic; + f_fpr_rf1_s_expo : out std_ulogic_vector(1 to 11) ; + f_fpr_rf1_s_frac : out std_ulogic_vector(0 to 52) ; + f_fpr_rf1_a_sign : out std_ulogic; + f_fpr_rf1_a_expo : out std_ulogic_vector(1 to 13) ; + f_fpr_rf1_a_frac : out std_ulogic_vector(0 to 52) ; + f_fpr_rf1_c_sign : out std_ulogic; + f_fpr_rf1_c_expo : out std_ulogic_vector(1 to 13) ; + f_fpr_rf1_c_frac : out std_ulogic_vector(0 to 52) ; + f_fpr_rf1_b_sign : out std_ulogic; + f_fpr_rf1_b_expo : out std_ulogic_vector(1 to 13) ; + f_fpr_rf1_b_frac : out std_ulogic_vector(0 to 52); + f_fpr_ex1_s_expo_extra : out std_ulogic; + f_fpr_ex1_a_par : out std_ulogic_vector(0 to 7); + f_fpr_ex1_b_par : out std_ulogic_vector(0 to 7); + f_fpr_ex1_c_par : out std_ulogic_vector(0 to 7); + f_fpr_ex1_s_par : out std_ulogic_vector(0 to 7) +); + -- synopsys translate_off + -- synopsys translate_on + +end fuq_fpr; + +architecture fuq_fpr of fuq_fpr is + + +signal tilo : std_ulogic; +signal tihi : std_ulogic; + +signal thold_0 : std_ulogic; +signal thold_0_b : std_ulogic; +signal sg_0 : std_ulogic; +signal forcee : std_ulogic; +signal ab_thold_0 : std_ulogic; +signal ab_thold_0_b : std_ulogic; +signal ab_force : std_ulogic; +signal time_force : std_ulogic; +signal time_sl_thold_0 : std_ulogic; +signal time_sl_thold_0_b : std_ulogic; + +signal lcb_obs0_sg_0 : std_ulogic; +signal lcb_obs1_sg_0 : std_ulogic; +signal lcb_obs0_sl_thold_0 : std_ulogic; +signal lcb_obs1_sl_thold_0 : std_ulogic; + +signal load_tid_enc : std_ulogic_vector(0 to 1); +signal load_addr : std_ulogic_vector(0 to 7); +signal load_wen : std_ulogic; +signal ex7_load_data_raw : std_ulogic_vector(0 to 63); +signal ex7_load_sp_data_raw : std_ulogic_vector(0 to 31); +signal ex7_load_data : std_ulogic_vector(0 to 65); +signal ex6_load_val : std_ulogic_vector(0 to 3); +signal ex6_load_v : std_ulogic; +signal ex6_load_tag : std_ulogic_vector(0 to 8); +signal ex7_load_val : std_ulogic_vector(0 to 3); +signal ex7_load_tag : std_ulogic_vector(0 to 8); +signal perr_inject : std_ulogic_vector(0 to 3); +signal ex6_ld_perr_inj : std_ulogic; +signal ex7_ld_perr_inj : std_ulogic; +signal ex5_targ_perr_inj : std_ulogic; +signal ex6_targ_perr_inj : std_ulogic; + +signal load_data : std_ulogic_vector(0 to 65); +signal load_data_parity : std_ulogic_vector(0 to 7); +signal load_data_parity_inj : std_ulogic_vector(0 to 7); +signal load_sp : std_ulogic; +signal load_int : std_ulogic; +signal load_sign_ext : std_ulogic; +signal load_int_1up : std_ulogic; +signal load_dp_exp_zero : std_ulogic; +signal load_sp_exp_zero : std_ulogic; +signal load_sp_exp_ones : std_ulogic; +signal load_sp_data : std_ulogic_vector(0 to 65); +signal load_dp_data : std_ulogic_vector(0 to 65); + +signal rf0_fra_addr : std_ulogic_vector(0 to 7); +signal rf0_frb_addr : std_ulogic_vector(0 to 7); +signal rf0_frc_addr : std_ulogic_vector(0 to 7); +signal rf0_frs_addr : std_ulogic_vector(0 to 7); + +signal frt_addr : std_ulogic_vector(0 to 7); +signal frt_wen : std_ulogic; +signal frt_data_parity : std_ulogic_vector(0 to 7); + + + +signal rf1_fra : std_ulogic_vector(0 to 77); +signal rf1_frb : std_ulogic_vector(0 to 77); +signal rf1_frc : std_ulogic_vector(0 to 77); +signal rf1_frs : std_ulogic_vector(0 to 77); +signal rf1_bypsel_a_res1 : std_ulogic; +signal rf1_bypsel_b_res1 : std_ulogic; +signal rf1_bypsel_c_res1 : std_ulogic; +signal rf1_bypsel_s_res1 : std_ulogic; + +signal rf1_bypsel_a_res1_nlb : std_ulogic; +signal rf1_bypsel_b_res1_nlb : std_ulogic; +signal rf1_bypsel_c_res1_nlb : std_ulogic; +signal rf1_bypsel_s_res1_nlb : std_ulogic; +signal rf1_bypsel_a_load1_nlb : std_ulogic; +signal rf1_bypsel_b_load1_nlb : std_ulogic; +signal rf1_bypsel_c_load1_nlb : std_ulogic; +signal rf1_bypsel_s_load1_nlb : std_ulogic; + +signal rf1_a_r0e_byp_r : std_ulogic; +signal rf1_c_r1e_byp_r : std_ulogic; +signal rf1_b_r0e_byp_r : std_ulogic; +signal rf1_s_r1e_byp_r : std_ulogic; +signal r0e_sel_lbist : std_ulogic; +signal r1e_sel_lbist : std_ulogic; + +signal rf1_bypsel_a_load1 : std_ulogic; +signal rf1_bypsel_b_load1 : std_ulogic; +signal rf1_bypsel_c_load1 : std_ulogic; +signal rf1_bypsel_s_load1 : std_ulogic; +signal ex1_dcd_si, ex1_dcd_so : std_ulogic_vector(0 to 7); + +signal abist_raddr_0 : std_ulogic_vector(0 to 9); +signal abist_raddr_1 : std_ulogic_vector(0 to 9); +signal abist_waddr_0 : std_ulogic_vector(0 to 9); +signal abist_waddr_1 : std_ulogic_vector(0 to 9); +signal ab_reg_si, ab_reg_so : std_ulogic_vector(0 to 52); + +signal abist_comp_en : std_ulogic; +signal r0e_abist_comp_en : std_ulogic; +signal r1e_abist_comp_en : std_ulogic; +signal Alcb_act_dis_dc : std_ulogic; + +signal lcb_clkoff_dc_b : std_ulogic_vector(0 to 1); + +signal Alcb_d_mode_dc : std_ulogic; + +signal Alcb_delay_lclkr_dc : std_ulogic_vector(0 to 4); + +signal lcb_delay_lclkr_dc : std_ulogic_vector(0 to 9); + +signal fce_0 : std_ulogic; +signal Alcb_mpw1_dc_b : std_ulogic_vector(0 to 4); +signal Alcb_mpw2_dc_b : std_ulogic; + +signal lcb_mpw1_dc_b : std_ulogic_vector(1 to 9); +signal lcb_mpw2_dc_b : std_ulogic; + +signal lcb_sg_0 : std_ulogic; +signal lcb_abst_sl_thold_0 : std_ulogic; +signal ary_nsl_thold_0 : std_ulogic; +signal Aclkoff_dc_b : std_ulogic; +signal Ad_mode_dc : std_ulogic; + + +signal r_scan_in_0 : std_ulogic; +signal r_scan_out_0 : std_ulogic; +signal w_scan_in_0 : std_ulogic; +signal w_scan_out_0 : std_ulogic; +signal r_scan_in_1 : std_ulogic; +signal r_scan_out_1 : std_ulogic; +signal w_scan_in_1 : std_ulogic; +signal w_scan_out_1 : std_ulogic; +signal r0e_fra_act : std_ulogic; +signal r0e_fra_en_func : std_ulogic; +signal r0e_frb_act : std_ulogic; +signal r0e_frb_en_func : std_ulogic; +signal r0e_en_abist : std_ulogic; +signal r0e_addr_abist : std_ulogic_vector(0 to 7); +signal r1e_frc_act : std_ulogic; +signal r1e_frc_en_func : std_ulogic; +signal r1e_frs_act : std_ulogic; +signal r1e_frs_en_func : std_ulogic; +signal r1e_en_abist : std_ulogic; +signal r1e_addr_abist : std_ulogic_vector(0 to 7); +signal w0e_act : std_ulogic; +signal w0e_en_func : std_ulogic; +signal w0e_en_abist : std_ulogic; +signal w0e_addr_func : std_ulogic_vector(0 to 7); +signal w0e_addr_abist : std_ulogic_vector(0 to 7); +signal w0e_data_func_f0 : std_ulogic_vector(0 to 77); +signal w0e_data_func_f1 : std_ulogic_vector(0 to 77); +signal w0e_data_abist : std_ulogic_vector(0 to 3); +signal w0l_act : std_ulogic; +signal w0l_en_func : std_ulogic; +signal w0l_en_abist : std_ulogic; +signal w0l_addr_func : std_ulogic_vector(0 to 7); +signal w0l_addr_abist : std_ulogic_vector(0 to 7); +signal w0l_data_func_f0 : std_ulogic_vector(0 to 77); +signal w0l_data_func_f1 : std_ulogic_vector(0 to 77); +signal w0l_data_abist : std_ulogic_vector(0 to 3); + +signal fra_data_out : std_ulogic_vector(0 to 77); +signal frb_data_out : std_ulogic_vector(0 to 77); +signal frc_data_out : std_ulogic_vector(0 to 77); +signal frs_data_out : std_ulogic_vector(0 to 77); +signal ex1_fra_par : std_ulogic_vector(0 to 7); +signal ex1_frb_par : std_ulogic_vector(0 to 7); +signal ex1_frc_par : std_ulogic_vector(0 to 7); +signal ex1_frs_par : std_ulogic_vector(0 to 7); +signal ex1_s_expo_extra : std_ulogic; + +signal ex7_ldat_si , ex7_ldat_so : std_ulogic_vector(0 to 63); +signal ex7_lctl_si , ex7_lctl_so : std_ulogic_vector(0 to 9); +signal ex7_ldv_si , ex7_ldv_so : std_ulogic_vector(0 to 3); +signal ex6_ldv_si , ex6_ldv_so : std_ulogic_vector(0 to 3); +signal ex6_lctl_si , ex6_lctl_so : std_ulogic_vector(0 to 13); +signal ex1_par_si , ex1_par_so : std_ulogic_vector(0 to 32); + signal ld_par3239, ld_par3239_inj, ld_par4047, ld_par4855, ld_par5663, ld_par6163, ld_par6163_inj :std_ulogic; + signal ld_par0007 , ld_par0815 , ld_par1623 , ld_par2431 :std_ulogic; + signal ld_par32_3436 , ld_par3744 , ld_par4552 , ld_par5360 :std_ulogic; + signal load_dp_nint, load_dp_int , load_sp_all1 , load_sp_nall1 :std_ulogic; + + signal xu_fu_ex5_load_val_din : std_ulogic_vector(0 to 3); + +signal lcb_bolt_sl_thold_2 : std_ulogic; +signal lcb_bolt_sl_thold_1 : std_ulogic; +signal lcb_bolt_sl_thold_0 : std_ulogic; +signal pc_bo_enable_2 : std_ulogic; + +signal SPARE_L2 : std_ulogic_vector(0 to 7); +signal spare_si, spare_so : std_ulogic_vector(0 to 7); +signal time_SPARE_L2 : std_ulogic_vector(0 to 1); +signal time_spare_si, time_spare_so : std_ulogic_vector(0 to 1); + +signal fpr_time_si,fpr_time_so : std_ulogic_vector(0 to 1); +signal obs0_scan_in,obs0_scan_out : std_ulogic_vector(0 to 1); +signal obs1_scan_in,obs1_scan_out : std_ulogic_vector(0 to 1); + +signal spare_unused : std_ulogic_vector(0 to 26); + + +signal abst_slat_d2clk : std_ulogic; +signal abst_slat_lclk : clk_logic; +signal func_slat_d2clk : std_ulogic; +signal func_slat_lclk : clk_logic; + +begin + + + thold_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => thold_1, + q(0) => thold_0 ); + + sg_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => sg_1 , + q(0) => sg_0 ); + + + lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map ( + clkoff_b => clkoff_b, + thold => thold_0, + sg => sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => thold_0_b ); + + ab_thold_reg_0: tri_plat generic map (width => 4, expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => abst_sl_thold_1, + din(1) => time_sl_thold_1, + din(2) => ary_nsl_thold_1, + din(3) => fce_1, + q(0) => ab_thold_0, + q(1) => time_sl_thold_0, + q(2) => ary_nsl_thold_0, + q(3) => fce_0 ); + + ab_lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map ( + clkoff_b => clkoff_b, + thold => ab_thold_0, + sg => sg_0, + act_dis => act_dis, + forcee => ab_force, + thold_b => ab_thold_0_b ); + + time_lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map ( + clkoff_b => clkoff_b, + thold => time_sl_thold_0, + sg => sg_0, + act_dis => act_dis, + forcee => time_force, + thold_b => time_sl_thold_0_b ); + + bo_thold_reg_0: tri_plat generic map (width => 4, expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => pc_fu_bolt_sl_thold_3, + din(1) => lcb_bolt_sl_thold_2, + din(2) => lcb_bolt_sl_thold_1, + din(3) => pc_fu_bo_enable_3, + q(0) => lcb_bolt_sl_thold_2, + q(1) => lcb_bolt_sl_thold_1, + q(2) => lcb_bolt_sl_thold_0, + q(3) => pc_bo_enable_2 ); + + + + tilo <= '0'; + tihi <= '1'; + + + +xu_fu_ex5_load_val_din(0 to 3) <= xu_fu_ex5_load_val(0 to 3) and not f_dcd_ex5_flush_int(0 to 3); + + ex6_ldv: tri_rlmreg_p generic map (init => 0, expand_type => expand_type, width => 4) + port map (nclk => nclk, + act => tihi, + forcee => forcee, + delay_lclkr => delay_lclkrb(6), + mpw1_b => mpw1_bb(6), + mpw2_b => mpw2_b(1), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => ex6_ldv_si(0 to 3), + scout => ex6_ldv_so(0 to 3), + din(0 to 3) => xu_fu_ex5_load_val_din(0 to 3) , + dout(0 to 3) => ex6_load_val(0 to 3) ); + + ex6_lctl: tri_rlmreg_p generic map (init => 0, expand_type => expand_type, width => 14) + port map (nclk => nclk, + act => tihi, + forcee => forcee, + delay_lclkr => delay_lclkrb(6), + mpw1_b => mpw1_bb(6), + mpw2_b => mpw2_b(1), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => ex6_lctl_si(0 to 13), + scout => ex6_lctl_so(0 to 13), + din(0 to 8) => xu_fu_ex5_load_tag(0 to 8) , + din(9 to 12) => pc_fu_inj_regfile_parity(0 to 3), + din(13) => ex5_targ_perr_inj , + dout(0 to 8) => ex6_load_tag(0 to 8) , + dout(9 to 12) => perr_inject(0 to 3) , + dout(13) => ex6_targ_perr_inj ); + + ex6_load_v <= ex6_load_val(0) or ex6_load_val(1) or ex6_load_val(2) or ex6_load_val(3); + ex6_ld_perr_inj <= or_reduce(perr_inject(0 to 3) and ex6_load_val(0 to 3)); + + ex5_targ_perr_inj <= (f_dcd_ex5_frt_tid="00" and perr_inject(0)) or + (f_dcd_ex5_frt_tid="01" and perr_inject(1)) or + (f_dcd_ex5_frt_tid="10" and perr_inject(2)) or + (f_dcd_ex5_frt_tid="11" and perr_inject(3)); + + ex7_ldv: tri_rlmreg_p generic map (init => 0, expand_type => expand_type, width => 4) + port map (nclk => nclk, + act => tihi, + forcee => forcee, + delay_lclkr => delay_lclkrb(7), + mpw1_b => mpw1_bb(7), + mpw2_b => mpw2_b(1), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => ex7_ldv_si(0 to 3), + scout => ex7_ldv_so(0 to 3), + din(0 to 3) => ex6_load_val(0 to 3) , + dout(0 to 3) => ex7_load_val(0 to 3) ); + + ex7_lctl: tri_rlmreg_p generic map (init => 0, expand_type => expand_type, width => 10) + port map (nclk => nclk, + act => ex6_load_v, + forcee => forcee, + delay_lclkr => delay_lclkrb(7), + mpw1_b => mpw1_bb(7), + mpw2_b => mpw2_b(1), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => ex7_lctl_si(0 to 9), + scout => ex7_lctl_so(0 to 9), + din(0 to 8) => ex6_load_tag(0 to 8) , + din(9) => ex6_ld_perr_inj , + dout(0 to 8) => ex7_load_tag(0 to 8) , + dout(9) => ex7_ld_perr_inj ); + + ex7_ldat: tri_rlmreg_p generic map (init => 0, expand_type => expand_type, width => 64, needs_sreset => 0) + port map (nclk => nclk, + act => ex6_load_v, + forcee => forcee, + delay_lclkr => delay_lclkrb(7), + mpw1_b => mpw1_bb(7), + mpw2_b => mpw2_b(1), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => ex7_ldat_si(0 to 63), + scout => ex7_ldat_so(0 to 63), + din => xu_fu_ex6_load_data(192 to 255) , + dout => ex7_load_data_raw(0 to 63) ); + + + load_tid_enc(0) <= ex7_load_val(2) or ex7_load_val(3); + load_tid_enc(1) <= ex7_load_val(1) or ex7_load_val(3); + + load_addr(1 to 7) <= ex7_load_tag(4 to 8) & load_tid_enc(0 to 1); + + load_sp <= ex7_load_tag(0); + load_int <= ex7_load_tag(1); + load_sign_ext <= ex7_load_tag(2); + + load_wen <= ex7_load_val(0) or ex7_load_val(1) or + ex7_load_val(2) or ex7_load_val(3) ; + + + load_int_1up <= load_int and load_sign_ext and load_sp_data(0); + + ex7_load_sp_data_raw(0 to 31) <= ex7_load_data_raw(32 to 63); + + load_dp_exp_zero <= ex7_load_data_raw( 1 to 11) = "00000000000"; + load_sp_exp_zero <= ex7_load_sp_data_raw( 1 to 8) = "00000000"; + load_sp_exp_ones <= ex7_load_sp_data_raw( 1 to 8) = "11111111"; + + load_sp_data(0) <= ex7_load_sp_data_raw( 0); + load_sp_data(1) <= tilo; + load_sp_data(2) <= ex7_load_sp_data_raw( 1); + load_sp_data(3) <= not ex7_load_sp_data_raw( 1) or load_sp_exp_ones; + load_sp_data(4) <= not ex7_load_sp_data_raw( 1) or load_sp_exp_ones; + load_sp_data(5) <= not ex7_load_sp_data_raw( 1) or load_sp_exp_ones; + load_sp_data(6 to 11) <= ex7_load_sp_data_raw( 2 to 7); + load_sp_data(12) <= ex7_load_sp_data_raw( 8) or load_sp_exp_zero; + load_sp_data(13) <= not load_sp_exp_zero; + load_sp_data(14 to 36) <= ex7_load_sp_data_raw( 9 to 31); + load_sp_data(37 to 65) <= (37 to 65 => tilo); + + + load_dp_data( 0) <= (ex7_load_data_raw( 0) and not load_int) or load_int_1up; + load_dp_data( 1) <= tilo; + load_dp_data( 2 to 11) <= (ex7_load_data_raw( 1 to 10) and not (1 to 10 => load_int)) or (1 to 10 => load_int_1up); + load_dp_data(12) <= (ex7_load_data_raw(11) or load_dp_exp_zero) or load_int or load_int_1up; + load_dp_data(13) <= ( not load_dp_exp_zero and not load_int) or load_int_1up; + load_dp_data(14 to 33) <= (ex7_load_data_raw(12 to 31) and not (14 to 33 => load_int)) or (14 to 33 => load_int_1up); + load_dp_data(34 to 65) <= ex7_load_data_raw(32 to 63); + + + ex7_load_data(0 to 65) <= (load_dp_data(0 to 65) and not (0 to 65 => load_sp)) or + (load_sp_data(0 to 65) and (0 to 65 => load_sp)) ; + + + load_data(0 to 65) <= ex7_load_data(0 to 65); + + + + ld_par0007 <= + ex7_load_data_raw( 0) xor + ex7_load_data_raw( 1) xor + ex7_load_data_raw( 2) xor + ex7_load_data_raw( 3) xor + ex7_load_data_raw( 4) xor + ex7_load_data_raw( 5) xor + ex7_load_data_raw( 6) xor + ex7_load_data_raw( 7) ; + ld_par32_3436 <= + ex7_load_data_raw(32) xor + ex7_load_data_raw(34) xor + ex7_load_data_raw(35) xor + ex7_load_data_raw(36) ; + ld_par0815 <= + ex7_load_data_raw( 8) xor + ex7_load_data_raw( 9) xor + ex7_load_data_raw(10) xor + ex7_load_data_raw(11) xor + ex7_load_data_raw(12) xor + ex7_load_data_raw(13) xor + ex7_load_data_raw(14) xor + ex7_load_data_raw(15) ; + ld_par3744 <= + ex7_load_data_raw(37) xor + ex7_load_data_raw(38) xor + ex7_load_data_raw(39) xor + ex7_load_data_raw(40) xor + ex7_load_data_raw(41) xor + ex7_load_data_raw(42) xor + ex7_load_data_raw(43) xor + ex7_load_data_raw(44) ; + ld_par1623 <= + ex7_load_data_raw(16) xor + ex7_load_data_raw(17) xor + ex7_load_data_raw(18) xor + ex7_load_data_raw(19) xor + ex7_load_data_raw(20) xor + ex7_load_data_raw(21) xor + ex7_load_data_raw(22) xor + ex7_load_data_raw(23) ; + ld_par4552 <= + ex7_load_data_raw(45) xor + ex7_load_data_raw(46) xor + ex7_load_data_raw(47) xor + ex7_load_data_raw(48) xor + ex7_load_data_raw(49) xor + ex7_load_data_raw(50) xor + ex7_load_data_raw(51) xor + ex7_load_data_raw(52) ; + ld_par2431 <= + ex7_load_data_raw(24) xor + ex7_load_data_raw(25) xor + ex7_load_data_raw(26) xor + ex7_load_data_raw(27) xor + ex7_load_data_raw(28) xor + ex7_load_data_raw(29) xor + ex7_load_data_raw(30) xor + ex7_load_data_raw(31) ; + ld_par5360 <= + ex7_load_data_raw(53) xor + ex7_load_data_raw(54) xor + ex7_load_data_raw(55) xor + ex7_load_data_raw(56) xor + ex7_load_data_raw(57) xor + ex7_load_data_raw(58) xor + ex7_load_data_raw(59) xor + ex7_load_data_raw(60) ; + ld_par3239 <= + ex7_load_data_raw(32) xor + ex7_load_data_raw(33) xor + ex7_load_data_raw(34) xor + ex7_load_data_raw(35) xor + ex7_load_data_raw(36) xor + ex7_load_data_raw(37) xor + ex7_load_data_raw(38) xor + ex7_load_data_raw(39) ; + ld_par3239_inj <= + ex7_load_data_raw(32) xor + ex7_load_data_raw(33) xor + ex7_load_data_raw(34) xor + ex7_load_data_raw(35) xor + ex7_load_data_raw(36) xor + ex7_load_data_raw(37) xor + ex7_load_data_raw(38) xor + ex7_load_data_raw(39) xor + ex7_ld_perr_inj ; + ld_par4047 <= + ex7_load_data_raw(40) xor + ex7_load_data_raw(41) xor + ex7_load_data_raw(42) xor + ex7_load_data_raw(43) xor + ex7_load_data_raw(44) xor + ex7_load_data_raw(45) xor + ex7_load_data_raw(46) xor + ex7_load_data_raw(47) ; + ld_par4855 <= + ex7_load_data_raw(48) xor + ex7_load_data_raw(49) xor + ex7_load_data_raw(50) xor + ex7_load_data_raw(51) xor + ex7_load_data_raw(52) xor + ex7_load_data_raw(53) xor + ex7_load_data_raw(54) xor + ex7_load_data_raw(55) ; + ld_par5663 <= + ex7_load_data_raw(56) xor + ex7_load_data_raw(57) xor + ex7_load_data_raw(58) xor + ex7_load_data_raw(59) xor + ex7_load_data_raw(60) xor + ex7_load_data_raw(61) xor + ex7_load_data_raw(62) xor + ex7_load_data_raw(63) ; + ld_par6163 <= + ex7_load_data_raw(61) xor + ex7_load_data_raw(62) xor + ex7_load_data_raw(63) ; + ld_par6163_inj <= + ex7_load_data_raw(61) xor + ex7_load_data_raw(62) xor + ex7_load_data_raw(63) xor + ex7_ld_perr_inj ; + + load_dp_nint <= not load_sp and not load_int ; + load_dp_int <= not load_sp and load_int ; + load_sp_all1 <= load_sp and load_sp_exp_ones ; + load_sp_nall1 <= load_sp and not load_sp_exp_ones ; + + load_data_parity(0) <= ( ld_par0007 and load_dp_nint) or ( ld_par32_3436 and load_sp_all1) or + (not ld_par32_3436 and load_sp_nall1) ; + load_data_parity(1) <= (not ld_par0815 and load_dp_nint) or (not ld_par3744 and load_sp) or load_dp_int; + load_data_parity(2) <= ( ld_par1623 and load_dp_nint) or ( ld_par4552 and load_sp); + load_data_parity(3) <= ( ld_par2431 and load_dp_nint) or ( ld_par5360 and load_sp); + load_data_parity(4) <= ( ld_par3239 and not load_sp ) or ( ld_par6163 and load_sp); + load_data_parity(5) <= ( ld_par4047 and not load_sp ) ; + load_data_parity(6) <= ( ld_par4855 and not load_sp ) ; + load_data_parity(7) <= ( ld_par5663 and not load_sp ) ; + + load_data_parity_inj(0) <= ( ld_par0007 and load_dp_nint) or ( ld_par32_3436 and load_sp_all1) or + (not ld_par32_3436 and load_sp_nall1) ; + load_data_parity_inj(1) <= (not ld_par0815 and load_dp_nint) or (not ld_par3744 and load_sp) or load_dp_int; + load_data_parity_inj(2) <= ( ld_par1623 and load_dp_nint) or ( ld_par4552 and load_sp); + load_data_parity_inj(3) <= ( ld_par2431 and load_dp_nint) or ( ld_par5360 and load_sp); + load_data_parity_inj(4) <= ( ld_par3239_inj and not load_sp ) or ( ld_par6163_inj and load_sp); + load_data_parity_inj(5) <= ( ld_par4047 and not load_sp ) ; + load_data_parity_inj(6) <= ( ld_par4855 and not load_sp ) ; + load_data_parity_inj(7) <= ( ld_par5663 and not load_sp ) ; + + + + + + f_fpr_ex7_load_sign <= load_data(0); + f_fpr_ex7_load_expo(3 to 13) <= load_data(2 to 12); + f_fpr_ex7_load_frac(0 to 52) <= load_data(13 to 65); + + + frt_addr(1 to 7) <= f_dcd_ex6_frt_addr(1 to 5) & f_dcd_ex6_frt_tid(0 to 1); + frt_wen <= f_dcd_ex6_frt_wen; + + frt_data_parity(0) <= f_rnd_ex6_res_sign xor f_rnd_ex6_res_expo(2) xor f_rnd_ex6_res_expo(3) xor f_rnd_ex6_res_expo(4) xor f_rnd_ex6_res_expo(5) xor + f_rnd_ex6_res_expo(6) xor f_rnd_ex6_res_expo(7) xor f_rnd_ex6_res_expo(8) xor f_rnd_ex6_res_expo(9) ; + frt_data_parity(1) <= f_rnd_ex6_res_expo(10) xor f_rnd_ex6_res_expo(11) xor f_rnd_ex6_res_expo(12) xor f_rnd_ex6_res_expo(13) xor f_rnd_ex6_res_frac(0) xor + f_rnd_ex6_res_frac(1) xor f_rnd_ex6_res_frac(2) xor f_rnd_ex6_res_frac(3) xor f_rnd_ex6_res_frac(4) ; + frt_data_parity(2) <= f_rnd_ex6_res_frac(5) xor f_rnd_ex6_res_frac(6) xor f_rnd_ex6_res_frac(7) xor f_rnd_ex6_res_frac(8) xor + f_rnd_ex6_res_frac(9) xor f_rnd_ex6_res_frac(10) xor f_rnd_ex6_res_frac(11) xor f_rnd_ex6_res_frac(12) ; + frt_data_parity(3) <= f_rnd_ex6_res_frac(13) xor f_rnd_ex6_res_frac(14) xor f_rnd_ex6_res_frac(15) xor f_rnd_ex6_res_frac(16) xor + f_rnd_ex6_res_frac(17) xor f_rnd_ex6_res_frac(18) xor f_rnd_ex6_res_frac(19) xor f_rnd_ex6_res_frac(20) ; + frt_data_parity(4) <= f_rnd_ex6_res_frac(21) xor f_rnd_ex6_res_frac(22) xor f_rnd_ex6_res_frac(23) xor f_rnd_ex6_res_frac(24) xor + f_rnd_ex6_res_frac(25) xor f_rnd_ex6_res_frac(26) xor f_rnd_ex6_res_frac(27) xor f_rnd_ex6_res_frac(28) ; + frt_data_parity(5) <= f_rnd_ex6_res_frac(29) xor f_rnd_ex6_res_frac(30) xor f_rnd_ex6_res_frac(31) xor f_rnd_ex6_res_frac(32) xor + f_rnd_ex6_res_frac(33) xor f_rnd_ex6_res_frac(34) xor f_rnd_ex6_res_frac(35) xor f_rnd_ex6_res_frac(36) ; + frt_data_parity(6) <= f_rnd_ex6_res_frac(37) xor f_rnd_ex6_res_frac(38) xor f_rnd_ex6_res_frac(39) xor f_rnd_ex6_res_frac(40) xor + f_rnd_ex6_res_frac(41) xor f_rnd_ex6_res_frac(42) xor f_rnd_ex6_res_frac(43) xor f_rnd_ex6_res_frac(44) ; + frt_data_parity(7) <= f_rnd_ex6_res_frac(45) xor f_rnd_ex6_res_frac(46) xor f_rnd_ex6_res_frac(47) xor f_rnd_ex6_res_frac(48) xor + f_rnd_ex6_res_frac(49) xor f_rnd_ex6_res_frac(50) xor f_rnd_ex6_res_frac(51) xor f_rnd_ex6_res_frac(52); + + + + rf0_fra_addr(1 to 7) <= f_dcd_rf0_fra(1 to 5) & f_dcd_rf0_tid(0 to 1); + rf0_frb_addr(1 to 7) <= f_dcd_rf0_frb(1 to 5) & f_dcd_rf0_tid(0 to 1); + rf0_frc_addr(1 to 7) <= f_dcd_rf0_frc(1 to 5) & f_dcd_rf0_tid(0 to 1); + + rf0_frs_addr(1 to 7) <= iu_fu_rf0_ldst_tag(4 to 8) & iu_fu_rf0_ldst_tid(0 to 1); + + rf0_fra_addr(0) <= f_dcd_rf0_fra(0); + rf0_frb_addr(0) <= f_dcd_rf0_frb(0); + rf0_frc_addr(0) <= f_dcd_rf0_frc(0); + + frt_addr(0) <= f_dcd_ex6_frt_addr(0); + + rf0_frs_addr(0) <= iu_fu_rf0_ldst_tag(3); + load_addr(0) <= ex7_load_tag(3); + + f_fpr_ex7_load_addr(0 to 7) <= load_tid_enc(0 to 1) & load_addr(0) & ex7_load_tag(4 to 8); + f_fpr_ex7_load_v <= load_wen; + + + + + + + w0e_act <= load_wen; + w0e_en_func <= load_wen; + w0e_addr_func(0 to 7) <= load_addr(0 to 7); + + w0l_act <= frt_wen; + w0l_en_func <= frt_wen; + w0l_addr_func(0 to 7) <= frt_addr (0 to 7); + + + w0e_data_func_f0(0 to 77) <= load_data_parity_inj(0 to 7) & "000" & load_data(0) & '0' & load_data(1 to 65); + w0e_data_func_f1(0 to 77) <= load_data_parity(0 to 7) & "000" & load_data(0) & '0' & load_data(1 to 65); + + w0l_data_func_f0(0 to 77) <= frt_data_parity(0 to 7) & "000" & f_rnd_ex6_res_sign & f_rnd_ex6_res_expo(1 to 13) & f_rnd_ex6_res_frac(0 to 52); + w0l_data_func_f1(0 to 77) <= frt_data_parity(0 to 6) & (frt_data_parity(7) xor ex6_targ_perr_inj) & "000" & f_rnd_ex6_res_sign & f_rnd_ex6_res_expo(1 to 13) & f_rnd_ex6_res_frac(0 to 52); + + rf1_fra(0 to 77) <= fra_data_out( 0 to 77); + rf1_frb(0 to 77) <= frb_data_out( 0 to 77); + rf1_frc(0 to 77) <= frc_data_out( 0 to 77); + rf1_frs(0 to 77) <= frs_data_out( 0 to 77); + + + + + + + + + + + + + + rf1_byp: tri_rlmreg_p generic map (init => 0, expand_type => expand_type, width => 8, needs_sreset => 0) + port map (nclk => nclk, + act => f_dcd_msr_fp_act, + forcee => forcee, + delay_lclkr => delay_lclkra(0), + mpw1_b => mpw1_ba(0), + mpw2_b => mpw2_b(0), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => ex1_dcd_si(0 to 7), + scout => ex1_dcd_so(0 to 7), + din ( 0) => f_dcd_rf0_bypsel_a_res1 , + din ( 1) => f_dcd_rf0_bypsel_b_res1 , + din ( 2) => f_dcd_rf0_bypsel_c_res1 , + din ( 3) => f_dcd_rf0_bypsel_s_res1 , + din ( 4) => f_dcd_rf0_bypsel_a_load1 , + din ( 5) => f_dcd_rf0_bypsel_b_load1 , + din ( 6) => f_dcd_rf0_bypsel_c_load1 , + din ( 7) => f_dcd_rf0_bypsel_s_load1 , + + dout( 0) => rf1_bypsel_a_res1 , + dout( 1) => rf1_bypsel_b_res1 , + dout( 2) => rf1_bypsel_c_res1 , + dout( 3) => rf1_bypsel_s_res1 , + dout( 4) => rf1_bypsel_a_load1 , + dout( 5) => rf1_bypsel_b_load1 , + dout( 6) => rf1_bypsel_c_load1 , + dout( 7) => rf1_bypsel_s_load1 ); + + rf1_bypsel_a_res1_nlb <= rf1_bypsel_a_res1 ; + rf1_bypsel_b_res1_nlb <= rf1_bypsel_b_res1 ; + rf1_bypsel_c_res1_nlb <= rf1_bypsel_c_res1 ; + rf1_bypsel_s_res1_nlb <= rf1_bypsel_s_res1 ; + rf1_bypsel_a_load1_nlb <= rf1_bypsel_a_load1 ; + rf1_bypsel_b_load1_nlb <= rf1_bypsel_b_load1 ; + rf1_bypsel_c_load1_nlb <= rf1_bypsel_c_load1 ; + rf1_bypsel_s_load1_nlb <= rf1_bypsel_s_load1 ; + + rf1_a_r0e_byp_r <= not(rf1_bypsel_a_load1 or rf1_bypsel_a_res1) ; + rf1_c_r1e_byp_r <= not(rf1_bypsel_c_load1 or rf1_bypsel_c_res1) ; + + rf1_b_r0e_byp_r <= not(rf1_bypsel_b_load1 or rf1_bypsel_b_res1) ; + rf1_s_r1e_byp_r <= not(rf1_bypsel_s_load1 or rf1_bypsel_s_res1) ; + + + + + f0 : entity tri.tri_144x78_2r2w + generic map (expand_type => expand_type) + port map( + vdd => vdd , + gnd => gnd , + nclk => nclk , + + lcb_bolt_sl_thold_0 => lcb_bolt_sl_thold_0 , + pc_bo_enable_2 => pc_bo_enable_2 , + pc_bo_reset => pc_fu_bo_reset , + pc_bo_unload => pc_fu_bo_unload , + pc_bo_load => pc_fu_bo_load , + pc_bo_shdata => pc_fu_bo_shdata , + pc_bo_select => pc_fu_bo_select(0) , + bo_pc_failout => fu_pc_bo_fail(0) , + bo_pc_diagloop => fu_pc_bo_diagout(0) , + + tri_lcb_mpw1_dc_b => mpw1_ba(0), + tri_lcb_mpw2_dc_b => mpw2_b(0), + tri_lcb_delay_lclkr_dc => delay_lclkra(0), + tri_lcb_clkoff_dc_b => clkoff_b, + tri_lcb_act_dis_dc => tilo, + + abist_en => pc_fu_abist_ena_dc , + abist_raw_dc_b => pc_fu_abist_raw_dc_b , + r0e_abist_comp_en => r0e_abist_comp_en , + r1e_abist_comp_en => r1e_abist_comp_en , + lbist_en => an_ac_lbist_ary_wrt_thru_dc , + lcb_act_dis_dc => Alcb_act_dis_dc , + lcb_clkoff_dc_b => lcb_clkoff_dc_b , + lcb_d_mode_dc => Alcb_d_mode_dc , + lcb_delay_lclkr_dc => lcb_delay_lclkr_dc , + lcb_fce_0 => fce_0 , + lcb_mpw1_dc_b => lcb_mpw1_dc_b , + lcb_mpw2_dc_b => lcb_mpw2_dc_b , + lcb_scan_diag_dc => scan_diag_dc , + lcb_scan_dis_dc_b => scan_dis_dc_b , + lcb_sg_0 => lcb_sg_0 , + lcb_time_sg_0 => lcb_sg_0 , + lcb_abst_sl_thold_0 => lcb_abst_sl_thold_0 , + lcb_time_sl_thold_0 => time_sl_thold_0 , + lcb_obs0_sg_0 => lcb_obs0_sg_0 , + lcb_obs1_sg_0 => lcb_obs1_sg_0 , + lcb_obs0_sl_thold_0 => lcb_obs0_sl_thold_0 , + lcb_obs1_sl_thold_0 => lcb_obs1_sl_thold_0 , + lcb_ary_nsl_thold_0 => ary_nsl_thold_0 , + r_scan_in => r_scan_in_0 , + r_scan_out => r_scan_out_0 , + w_scan_in => w_scan_in_0 , + w_scan_out => w_scan_out_0 , + time_scan_in => fpr_time_si(0) , + time_scan_out => fpr_time_so(0) , + obs0_scan_in => obs0_scan_in(0) , + obs0_scan_out => obs0_scan_out(0) , + obs1_scan_in => obs1_scan_in(0) , + obs1_scan_out => obs1_scan_out(0) , + r0e_act => r0e_fra_act , + r0e_en_func => r0e_fra_en_func , + r0e_en_abist => r0e_en_abist , + r0e_addr_func => rf0_fra_addr , + r0e_addr_abist => r0e_addr_abist , + r0e_data_out => fra_data_out , + r0e_byp_e => rf1_bypsel_a_load1_nlb , + r0e_byp_l => rf1_bypsel_a_res1_nlb , + r0e_byp_r => rf1_a_r0e_byp_r, + r0e_sel_lbist => r0e_sel_lbist , + r1e_act => r1e_frc_act , + r1e_en_func => r1e_frc_en_func , + r1e_en_abist => r1e_en_abist , + r1e_addr_func => rf0_frc_addr , + r1e_addr_abist => r1e_addr_abist , + r1e_data_out => frc_data_out , + r1e_byp_e => rf1_bypsel_c_load1_nlb , + r1e_byp_l => rf1_bypsel_c_res1_nlb , + r1e_byp_r => rf1_c_r1e_byp_r, + r1e_sel_lbist => r1e_sel_lbist , + w0e_act => w0e_act , + w0e_en_func => w0e_en_func , + w0e_en_abist => w0e_en_abist , + w0e_addr_func => w0e_addr_func , + w0e_addr_abist => w0e_addr_abist , + w0e_data_func => w0e_data_func_f0 , + w0e_data_abist => w0e_data_abist , + w0l_act => w0l_act , + w0l_en_func => w0l_en_func , + w0l_en_abist => w0l_en_abist , + w0l_addr_func => w0l_addr_func , + w0l_addr_abist => w0l_addr_abist , + w0l_data_func => w0l_data_func_f0 , + w0l_data_abist => w0l_data_abist + ); + + f1 : entity tri.tri_144x78_2r2w + generic map (expand_type => expand_type) + port map( + vdd => vdd , + gnd => gnd , + nclk => nclk , + + lcb_bolt_sl_thold_0 => lcb_bolt_sl_thold_0 , + pc_bo_enable_2 => pc_bo_enable_2 , + pc_bo_reset => pc_fu_bo_reset , + pc_bo_unload => pc_fu_bo_unload , + pc_bo_load => pc_fu_bo_load , + pc_bo_shdata => pc_fu_bo_shdata , + pc_bo_select => pc_fu_bo_select(1) , + bo_pc_failout => fu_pc_bo_fail(1) , + bo_pc_diagloop => fu_pc_bo_diagout(1) , + + tri_lcb_mpw1_dc_b => mpw1_ba(0), + tri_lcb_mpw2_dc_b => mpw2_b(0), + tri_lcb_delay_lclkr_dc => delay_lclkra(0), + tri_lcb_clkoff_dc_b => clkoff_b, + tri_lcb_act_dis_dc => tilo, + + abist_en => pc_fu_abist_ena_dc , + abist_raw_dc_b => pc_fu_abist_raw_dc_b , + r0e_abist_comp_en => r0e_abist_comp_en , + r1e_abist_comp_en => r1e_abist_comp_en , + lbist_en => an_ac_lbist_ary_wrt_thru_dc , + lcb_act_dis_dc => Alcb_act_dis_dc , + lcb_clkoff_dc_b => lcb_clkoff_dc_b , + lcb_d_mode_dc => Alcb_d_mode_dc , + lcb_delay_lclkr_dc => lcb_delay_lclkr_dc , + lcb_fce_0 => fce_0 , + lcb_mpw1_dc_b => lcb_mpw1_dc_b , + lcb_mpw2_dc_b => lcb_mpw2_dc_b , + lcb_scan_diag_dc => scan_diag_dc , + lcb_scan_dis_dc_b => scan_dis_dc_b , + lcb_sg_0 => lcb_sg_0 , + lcb_time_sg_0 => lcb_sg_0 , + lcb_abst_sl_thold_0 => lcb_abst_sl_thold_0 , + lcb_time_sl_thold_0 => time_sl_thold_0 , + lcb_obs0_sg_0 => lcb_obs0_sg_0 , + lcb_obs1_sg_0 => lcb_obs1_sg_0 , + lcb_obs0_sl_thold_0 => lcb_obs0_sl_thold_0 , + lcb_obs1_sl_thold_0 => lcb_obs1_sl_thold_0 , + lcb_ary_nsl_thold_0 => ary_nsl_thold_0 , + r_scan_in => r_scan_in_1 , + r_scan_out => r_scan_out_1 , + w_scan_in => w_scan_in_1 , + w_scan_out => w_scan_out_1 , + time_scan_in => fpr_time_si(1) , + time_scan_out => fpr_time_so(1) , + obs0_scan_in => obs0_scan_in(1) , + obs0_scan_out => obs0_scan_out(1) , + obs1_scan_in => obs1_scan_in(1) , + obs1_scan_out => obs1_scan_out(1) , + r0e_act => r0e_frb_act , + r0e_en_func => r0e_frb_en_func , + r0e_en_abist => r0e_en_abist , + r0e_addr_func => rf0_frb_addr , + r0e_addr_abist => r0e_addr_abist , + r0e_data_out => frb_data_out , + r0e_byp_e => rf1_bypsel_b_load1_nlb , + r0e_byp_l => rf1_bypsel_b_res1_nlb , + r0e_byp_r => rf1_b_r0e_byp_r, + r0e_sel_lbist => r0e_sel_lbist , + r1e_act => r1e_frs_act , + r1e_en_func => r1e_frs_en_func , + r1e_en_abist => r1e_en_abist , + r1e_addr_func => rf0_frs_addr , + r1e_addr_abist => r1e_addr_abist , + r1e_data_out => frs_data_out , + r1e_byp_e => rf1_bypsel_s_load1_nlb , + r1e_byp_l => rf1_bypsel_s_res1_nlb , + r1e_byp_r => rf1_s_r1e_byp_r, + r1e_sel_lbist => r1e_sel_lbist , + w0e_act => w0e_act , + w0e_en_func => w0e_en_func , + w0e_en_abist => w0e_en_abist , + w0e_addr_func => w0e_addr_func , + w0e_addr_abist => w0e_addr_abist , + w0e_data_func => w0e_data_func_f1 , + w0e_data_abist => w0e_data_abist , + w0l_act => w0l_act , + w0l_en_func => w0l_en_func , + w0l_en_abist => w0l_en_abist , + w0l_addr_func => w0l_addr_func , + w0l_addr_abist => w0l_addr_abist , + w0l_data_func => w0l_data_func_f1 , + w0l_data_abist => w0l_data_abist + ); + + ab_reg: tri_rlmreg_p generic map (init => 0, expand_type => expand_type, width => 53, needs_sreset => 0) + port map (nclk => nclk, + act => pc_fu_abist_ena_dc, + forcee => ab_force, + delay_lclkr => delay_lclkra(0), + mpw1_b => mpw1_ba(0), + mpw2_b => mpw2_b(0), + thold_b => ab_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => ab_reg_si(0 to 52), + scout => ab_reg_so(0 to 52), + din ( 0 to 3) => pc_fu_abist_di_0(0 to 3) , + din ( 4 to 7) => pc_fu_abist_di_1(0 to 3) , + din ( 8) => pc_fu_abist_grf_renb_0 , + din ( 9) => pc_fu_abist_grf_renb_1 , + din ( 10) => pc_fu_abist_grf_wenb_0 , + din ( 11) => pc_fu_abist_grf_wenb_1 , + din (12 to 21) => pc_fu_abist_raddr_0(0 to 9), + din (22 to 31) => pc_fu_abist_raddr_1(0 to 9), + din (32 to 41) => pc_fu_abist_waddr_0(0 to 9), + din (42 to 51) => pc_fu_abist_waddr_1(0 to 9), + din ( 52) => pc_fu_abist_wl144_comp_ena , + dout( 0 to 3) => w0e_data_abist(0 to 3) , + dout( 4 to 7) => w0l_data_abist(0 to 3) , + dout( 8) => r0e_en_abist , + dout( 9) => r1e_en_abist , + dout( 10) => w0e_en_abist , + dout( 11) => w0l_en_abist , + dout(12 to 21) => abist_raddr_0(0 to 9), + dout(22 to 31) => abist_raddr_1(0 to 9), + dout(32 to 41) => abist_waddr_0(0 to 9), + dout(42 to 51) => abist_waddr_1(0 to 9), + dout( 52) => abist_comp_en ); + +lcbctrlA : entity tri.tri_lcbcntl_array_mac + generic map( expand_type => expand_type ) + port map( + vdd => vdd, + gnd => gnd, + sg => sg_0, + nclk => nclk, + scan_in => gptr_scan_in, + scan_diag_dc => scan_diag_dc, + thold => gptr_sl_thold_0, + clkoff_dc_b => Aclkoff_dc_b, + delay_lclkr_dc => Alcb_delay_lclkr_dc(0 to 4), + act_dis_dc => Alcb_act_dis_dc, + d_mode_dc => Ad_mode_dc, + mpw1_dc_b => Alcb_mpw1_dc_b(0 to 4), + mpw2_dc_b => Alcb_mpw2_dc_b, + scan_out => gptr_scan_out + ); + + + + lcb_mpw2_dc_b <= Alcb_mpw2_dc_b; + + + lcb_delay_lclkr_dc(0) <= Alcb_delay_lclkr_dc(0) ; + lcb_delay_lclkr_dc(1) <= Alcb_delay_lclkr_dc(1) ; + lcb_delay_lclkr_dc(2) <= Alcb_delay_lclkr_dc(0) ; + lcb_delay_lclkr_dc(3) <= Alcb_delay_lclkr_dc(1) ; + lcb_delay_lclkr_dc(4) <= Alcb_delay_lclkr_dc(2) ; + lcb_delay_lclkr_dc(5) <= Alcb_delay_lclkr_dc(3) ; + lcb_delay_lclkr_dc(6) <= Alcb_delay_lclkr_dc(4) ; + lcb_delay_lclkr_dc(7) <= Alcb_delay_lclkr_dc(4) ; + lcb_delay_lclkr_dc(8) <= Alcb_delay_lclkr_dc(3) ; + lcb_delay_lclkr_dc(9) <= Alcb_delay_lclkr_dc(3) ; + + lcb_mpw1_dc_b(1) <= Alcb_mpw1_dc_b (1) ; + lcb_mpw1_dc_b(2) <= Alcb_mpw1_dc_b (0) ; + lcb_mpw1_dc_b(3) <= Alcb_mpw1_dc_b (1) ; + lcb_mpw1_dc_b(4) <= Alcb_mpw1_dc_b (2) ; + lcb_mpw1_dc_b(5) <= Alcb_mpw1_dc_b (3) ; + lcb_mpw1_dc_b(6) <= Alcb_mpw1_dc_b (4) ; + lcb_mpw1_dc_b(7) <= Alcb_mpw1_dc_b (4) ; + lcb_mpw1_dc_b(8) <= Alcb_mpw1_dc_b (3) ; + lcb_mpw1_dc_b(9) <= Alcb_mpw1_dc_b (3) ; + + lcb_obs0_sg_0 <= sg_0 ; + lcb_obs1_sg_0 <= sg_0 ; + lcb_obs0_sl_thold_0 <= ab_thold_0 ; + lcb_obs1_sl_thold_0 <= ab_thold_0 ; + + r0e_abist_comp_en <= abist_comp_en; + r1e_abist_comp_en <= abist_comp_en; + + lcb_sg_0 <= sg_0; + lcb_abst_sl_thold_0 <= ab_thold_0; + + Alcb_d_mode_dc <= Ad_mode_dc; + + lcb_clkoff_dc_b <= Aclkoff_dc_b & Aclkoff_dc_b; + + r0e_frb_act <= iu_fu_rf0_frb_v or f_dcd_perr_sm_running or lbist_en_dc; + r0e_frb_en_func <= iu_fu_rf0_frb_v or f_dcd_perr_sm_running or lbist_en_dc; + r0e_fra_act <= iu_fu_rf0_fra_v or lbist_en_dc; + r0e_fra_en_func <= iu_fu_rf0_fra_v or lbist_en_dc; + + r1e_frs_act <= iu_fu_rf0_str_v or lbist_en_dc; + r1e_frs_en_func <= iu_fu_rf0_str_v or lbist_en_dc; + r1e_frc_act <= iu_fu_rf0_frc_v or f_dcd_perr_sm_running or lbist_en_dc; + r1e_frc_en_func <= iu_fu_rf0_frc_v or f_dcd_perr_sm_running or lbist_en_dc; + + r0e_addr_abist(0 to 7) <= abist_raddr_0(2 to 9); + r1e_addr_abist(0 to 7) <= abist_raddr_1(2 to 9); + + w0e_addr_abist(0 to 7) <= abist_waddr_0(2 to 9); + w0l_addr_abist(0 to 7) <= abist_waddr_1(2 to 9); + + r0e_sel_lbist <= an_ac_lbist_ary_wrt_thru_dc; + r1e_sel_lbist <= an_ac_lbist_ary_wrt_thru_dc; + + + + + + + + + ex1_par: tri_rlmreg_p generic map (init => 0, expand_type => expand_type, width => 33, needs_sreset => 0) + port map (nclk => nclk, + act => f_dcd_msr_fp_act, + forcee => forcee, + delay_lclkr => delay_lclkra(1), + mpw1_b => mpw1_ba(1), + mpw2_b => mpw2_b(0), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => ex1_par_si(0 to 32), + scout => ex1_par_so(0 to 32), + din ( 0 to 7) => rf1_fra(0 to 7) , + din ( 8 to 15) => rf1_frb(0 to 7) , + din (16 to 23) => rf1_frc(0 to 7) , + din (24 to 31) => rf1_frs(0 to 7) , + din (32) => rf1_frs(13) , + + dout( 0 to 7) => ex1_fra_par(0 to 7) , + dout( 8 to 15) => ex1_frb_par(0 to 7) , + dout(16 to 23) => ex1_frc_par(0 to 7) , + dout(24 to 31) => ex1_frs_par(0 to 7) , + dout(32) => ex1_s_expo_extra ); + + + f_fpr_ex1_a_par(0 to 7) <= ex1_fra_par(0 to 7); + f_fpr_ex1_b_par(0 to 7) <= ex1_frb_par(0 to 7); + f_fpr_ex1_c_par(0 to 7) <= ex1_frc_par(0 to 7); + f_fpr_ex1_s_par(0 to 7) <= ex1_frs_par(0 to 7); + + + + + f_fpr_rf1_a_sign <= rf1_fra(11); + f_fpr_rf1_a_expo(1 to 13) <= rf1_fra(12 to 24); + f_fpr_rf1_a_frac(0 to 52) <= rf1_fra(25 to 77); + f_fpr_rf1_c_sign <= rf1_frc(11); + f_fpr_rf1_c_expo(1 to 13) <= rf1_frc(12 to 24); + f_fpr_rf1_c_frac(0 to 52) <= rf1_frc(25 to 77); + f_fpr_rf1_b_sign <= rf1_frb(11); + f_fpr_rf1_b_expo(1 to 13) <= rf1_frb(12 to 24); + f_fpr_rf1_b_frac(0 to 52) <= rf1_frb(25 to 77); + + f_fpr_rf1_s_sign <= rf1_frs(11); + f_fpr_rf1_s_expo(1 to 11) <= rf1_frs(14 to 24); + f_fpr_rf1_s_frac(0 to 52) <= rf1_frs(25 to 77); + f_fpr_ex1_s_expo_extra <= ex1_s_expo_extra; + + + + + + spare_lat: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 8) + port map (nclk => nclk, + act => f_dcd_msr_fp_act, + forcee => forcee, + delay_lclkr => delay_lclkra(0), + mpw1_b => mpw1_ba(0), + mpw2_b => mpw2_b(0), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => spare_si(0 to 7), + scout => spare_so(0 to 7), + din( 0 to 7) => SPARE_L2(0 to 7) , + dout( 0 to 7) => SPARE_L2(0 to 7) + ); + + spare_lat_time: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 2) + port map (nclk => nclk, + act => tihi, + forcee => time_force, + delay_lclkr => delay_lclkra(0), + mpw1_b => mpw1_ba(0), + mpw2_b => mpw2_b(0), + thold_b => time_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => time_spare_si(0 to 1), + scout => time_spare_so(0 to 1), + din( 0 to 1) => time_SPARE_L2(0 to 1) , + dout( 0 to 1) => time_SPARE_L2(0 to 1) + ); + + + +lcbs_abst: tri_lcbs + generic map (expand_type => expand_type ) + port map ( + vd => vdd, + gd => gnd, + delay_lclkr => delay_lclkra(0), + nclk => nclk, + forcee => ab_force, + thold_b => ab_thold_0_b, + dclk => abst_slat_d2clk, + lclk => abst_slat_lclk ); +bx_abst_stg: tri_slat_scan + generic map (width => 2, init => "00", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => abst_slat_d2clk, + lclk => abst_slat_lclk, + scan_in(0) => bx_fu_rp_abst_scan_out, + scan_in(1) => rp_bx_abst_scan_in, + scan_out(0) => bx_rp_abst_scan_out, + scan_out(1) => rp_fu_bx_abst_scan_in ); + + +lcbs_func: tri_lcbs + generic map (expand_type => expand_type ) + port map ( + vd => vdd, + gd => gnd, + delay_lclkr => delay_lclkra(0), + nclk => nclk, + forcee => forcee, + thold_b => thold_0_b, + dclk => func_slat_d2clk, + lclk => func_slat_lclk ); +bx_func_stg: tri_slat_scan + generic map (width => 4, init => "0000", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => func_slat_d2clk, + lclk => func_slat_lclk, + scan_in(0 to 1) => bx_fu_rp_func_scan_out, + scan_in(2 to 3) => rp_bx_func_scan_in, + scan_out(0 to 1) => bx_rp_func_scan_out, + scan_out(2 to 3) => rp_fu_bx_func_scan_in ); + + + + + ex7_ldat_si (0 to 63) <= ex7_ldat_so (1 to 63) & f_fpr_si; + ex7_ldv_si (0 to 3) <= ex7_ldv_so (1 to 3) & ex7_ldat_so (0); + ex7_lctl_si (0 to 9) <= ex7_lctl_so (1 to 9) & ex7_ldv_so (0); + ex6_ldv_si (0 to 3) <= ex6_ldv_so (1 to 3) & ex7_lctl_so (0); + ex6_lctl_si (0 to 13) <= ex6_lctl_so (1 to 13) & ex6_ldv_so (0); + ex1_par_si (0 to 32) <= ex1_par_so (1 to 32) & ex6_lctl_so(0); + ex1_dcd_si(0 to 7) <= ex1_dcd_so (1 to 7) & ex1_par_so (0); + spare_si (0 to 7) <= spare_so(1 to 7) & ex1_dcd_so (0); + f_fpr_so <= spare_so (0); + + ab_reg_si (0 to 7) <= ab_reg_so (1 to 7) & f_fpr_ab_si; + r_scan_in_0 <= ab_reg_so(0); + w_scan_in_0 <= r_scan_out_0; + r_scan_in_1 <= w_scan_out_0; + w_scan_in_1 <= r_scan_out_1; + obs0_scan_in(0 to 1) <= obs0_scan_out(1) & w_scan_out_1; + obs1_scan_in(0 to 1) <= obs1_scan_out(1) & obs0_scan_out(0); + + ab_reg_si (8 to 52) <= ab_reg_so (9 to 52) & obs1_scan_out(0); + f_fpr_ab_so <= ab_reg_so(8); + + time_spare_si(0) <= time_scan_in; + fpr_time_si(0 to 1) <= fpr_time_so(1) & time_spare_so(0); + time_spare_si(1) <= fpr_time_so(0); + time_scan_out <= time_spare_so(1); + + + spare_unused( 0 to 2) <= iu_fu_rf0_ldst_tag(0 to 2); + spare_unused( 3 to 5) <= rf1_fra(8 to 10); + spare_unused( 6 to 8) <= rf1_frb(8 to 10); + spare_unused( 9 to 11) <= rf1_frc(8 to 10); + spare_unused(12 to 14) <= rf1_frs(8 to 10); + + spare_unused(15 to 16) <= abist_raddr_0(0 to 1); + spare_unused(17 to 18) <= abist_raddr_1(0 to 1); + spare_unused(19 to 20) <= abist_waddr_0(0 to 1); + spare_unused(21 to 22) <= abist_waddr_1(0 to 1); + + spare_unused(23) <= Alcb_mpw1_dc_b(4); + spare_unused(24) <= Alcb_delay_lclkr_dc(4); + spare_unused(25) <= rf1_frs(12); + spare_unused(26) <= an_ac_abist_mode_dc; + + + + +end architecture fuq_fpr; + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_gst.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_gst.vhdl new file mode 100644 index 0000000..83dc27e --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_gst.vhdl @@ -0,0 +1,1294 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + +entity fuq_gst is + +generic ( + expand_type : integer := 2 ); +port ( + vdd :inout power_logic; + gnd :inout power_logic; + clkoff_b :in std_ulogic; + act_dis :in std_ulogic; + flush :in std_ulogic; + delay_lclkr :in std_ulogic_vector(2 to 5); + mpw1_b :in std_ulogic_vector(2 to 5); + mpw2_b :in std_ulogic_vector(0 to 1); + sg_1 :in std_ulogic; + thold_1 :in std_ulogic; + fpu_enable :in std_ulogic; + nclk :in clk_logic; + f_gst_si :in std_ulogic; + f_gst_so :out std_ulogic; + rf1_act :in std_ulogic; + f_fmt_ex1_b_sign_gst :in std_ulogic; + f_fmt_ex1_b_expo_gst_b :in std_ulogic_vector(01 to 13); + f_fmt_ex1_b_frac_gst :in std_ulogic_vector(01 to 19); + f_pic_ex1_floges :in std_ulogic; + f_pic_ex1_fexptes :in std_ulogic; + f_gst_ex5_logexp_v :out std_ulogic; + f_gst_ex5_logexp_sign :out std_ulogic; + f_gst_ex5_logexp_exp :out std_ulogic_vector(01 to 11); + f_gst_ex5_logexp_fract :out std_ulogic_vector(00 to 19) +); + + + + + + +end fuq_gst; + +architecture fuq_gst of fuq_gst is + +constant tiup : std_ulogic := '1'; +constant tidn : std_ulogic := '0'; + +signal sg_0 :std_ulogic; +signal thold_0_b , thold_0, forcee :std_ulogic; + + + + +signal ex2_gst_ctrl_lat_scout :std_ulogic_vector(0 to 1); +signal ex2_gst_ctrl_lat_scin :std_ulogic_vector(0 to 1); +signal ex3_gst_ctrl_lat_scout :std_ulogic_vector(0 to 1); +signal ex3_gst_ctrl_lat_scin :std_ulogic_vector(0 to 1); +signal ex4_gst_ctrl_lat_scout :std_ulogic_vector(0 to 3); +signal ex4_gst_ctrl_lat_scin :std_ulogic_vector(0 to 3); +signal ex5_gst_ctrl_lat_scout :std_ulogic_vector(0 to 1); +signal ex5_gst_ctrl_lat_scin :std_ulogic_vector(0 to 1); +signal ex2_gst_stage_lat_scout :std_ulogic_vector(0 to 32); +signal ex2_gst_stage_lat_scin :std_ulogic_vector(0 to 32); +signal ex3_gst_stage_lat_scout :std_ulogic_vector(0 to 19); +signal ex3_gst_stage_lat_scin :std_ulogic_vector(0 to 19); +signal ex4_gst_stage_lat_scout :std_ulogic_vector(0 to 23); +signal ex4_gst_stage_lat_scin :std_ulogic_vector(0 to 23); +signal ex5_gst_stage_lat_scout :std_ulogic_vector(0 to 31); +signal ex5_gst_stage_lat_scin :std_ulogic_vector(0 to 31); + +signal ex4_log_dp_bias :std_ulogic_vector(1 to 11); +signal ex4_logof1_specialcase : std_ulogic; +signal ex3_logof1_specialcase : std_ulogic; + +signal ex4_signbit_din, ex5_signbit : std_ulogic; +signal ex4_log_signbit : std_ulogic; + +signal f1, f2, f3, f4, f5 : std_ulogic; +signal f6, f7, f8, f9, f10 : std_ulogic; +signal s1, s2, s3 : std_ulogic; +signal c4, c5, c6, c7 : std_ulogic; +signal a4, a5, a6 : std_ulogic; +signal a7, a8, a9, a10, a11 : std_ulogic; + +signal ex2_f :std_ulogic_vector(1 to 11); +signal ex2_a :std_ulogic_vector(4 to 11); +signal ex2_c :std_ulogic_vector(4 to 11); + +signal ex2_log_fsum :std_ulogic_vector(4 to 7) ; +signal ex2_log_fcarryin :std_ulogic_vector(3 to 6); + +signal ex2_b_sign :std_ulogic ; +signal ex2_b_biased_13exp :std_ulogic_vector(1 to 13); +signal ex2_b_biased_11exp :std_ulogic_vector(1 to 11); + +signal ex2_b_ubexp_sum :std_ulogic_vector(1 to 11); +signal ex2_b_ubexp_cout :std_ulogic_vector(2 to 11); +signal ex2_b_ubexp :std_ulogic_vector(1 to 11); + +signal ex2_b_fract :std_ulogic_vector(1 to 19); + +signal f_fmt_ex1_b_expo_gst :std_ulogic_vector(1 to 13); + +signal ex1_floges : std_ulogic; +signal ex1_fexptes : std_ulogic; +signal ex2_floges : std_ulogic; +signal ex2_fexptes : std_ulogic; +signal ex3_floges : std_ulogic; +signal ex3_fexptes : std_ulogic; +signal ex4_floges : std_ulogic; +signal ex4_fexptes : std_ulogic; +signal ex5_floges : std_ulogic; +signal ex5_fexptes : std_ulogic; + +signal ex2_log_a_addend_b, ex2_log_b_addend_b :std_ulogic_vector(1 to 11); + +signal ex3_mantissa, ex4_mantissa, ex3_mantissa_precomp,ex3_mantissa_precomp_b :std_ulogic_vector(1 to 19); +signal ex2_log_mantissa_precomp, ex3_mantissa_neg, ex2_mantissa_din :std_ulogic_vector(1 to 19); +signal ex2_shamt,ex3_shamt, ex4_shamt :std_ulogic_vector(0 to 4); +signal ex3_negate,ex4_negate, ex3_b_sign : std_ulogic; + +signal ex2_mantissa_shlev0 :std_ulogic_vector(00 to 19); +signal ex2_mantissa_shlev1 :std_ulogic_vector(00 to 22); +signal ex2_mantissa_shlev2 :std_ulogic_vector(00 to 34); +signal ex2_mantissa_shlev3 :std_ulogic_vector(00 to 50); + +signal ex2_pow_int :std_ulogic_vector(1 to 8) ; +signal ex2_pow_frac :std_ulogic_vector(1 to 11) ; + + + +signal ex4_mantissa_shlev0 :std_ulogic_vector(01 to 19); +signal ex4_mantissa_shlev1 :std_ulogic_vector(01 to 22); +signal ex4_mantissa_shlev2 :std_ulogic_vector(01 to 34); +signal ex4_mantissa_shlev3 :std_ulogic_vector(01 to 50); + +signal ex4_exponent_a_addend_b :std_ulogic_vector(01 to 11); +signal ex4_exponent_b_addend_b :std_ulogic_vector(01 to 11); + +signal ex4_log_a_addend_b :std_ulogic_vector(01 to 11); +signal ex4_log_b_addend_b :std_ulogic_vector(01 to 11); +signal ex4_pow_a_addend_b :std_ulogic_vector(01 to 11); +signal ex4_pow_b_addend_b :std_ulogic_vector(01 to 11); + +signal ex4_biased_exponent_result :std_ulogic_vector(01 to 11); +signal ex5_biased_exponent_result :std_ulogic_vector(01 to 11); + +signal ex4_log_mantissa_postsh :std_ulogic_vector(01 to 19); +signal ex4_log_fract :std_ulogic_vector(01 to 19); +signal ex4_pow_fract, ex4_pow_fract_b :std_ulogic_vector(01 to 11); +signal ex4_fract_din :std_ulogic_vector(00 to 19); +signal ex5_fract :std_ulogic_vector(00 to 19); + +signal l1_enc00, l1_enc01, l1_enc10, l1_enc11 :std_ulogic; +signal l2_enc00, l2_enc01, l2_enc10, l2_enc11 :std_ulogic; +signal l3_enc00, l3_enc01 :std_ulogic; +signal l1_e00, l1_e01, l1_e10, l1_e11 :std_ulogic; +signal l2_e00, l2_e01, l2_e10, l2_e11 :std_ulogic; +signal l3_e00, l3_e01 :std_ulogic; + + +signal ex4_f,ex4_f_b :std_ulogic_vector(01 to 11); + +signal eb1, eb2, eb3, eb4, eb5, eb6, eb7, eb8, eb9, eb10 : std_ulogic; + +signal ea4, ea5, ea6, ea7, ea8, ea9, ea10, ea11 : std_ulogic; +signal ec4, ec5, ec6, ec7 : std_ulogic; +signal es1, es2, es3 : std_ulogic; +signal ex4_ea, ex4_ec : std_ulogic_vector(4 to 11); + + +signal ex4_addend1, ex4_addend2, ex4_addend3 : std_ulogic_vector(1 to 11); +signal ex4_fsum : std_ulogic_vector(1 to 11); +signal ex4_fcarryin : std_ulogic_vector(1 to 11); +signal ex4_powf_a_addend_b : std_ulogic_vector(1 to 11); +signal ex4_powf_b_addend_b : std_ulogic_vector(1 to 11); + +signal zeros :std_ulogic_vector(01 to 16); +signal ex2_powsh_no_sat_lft, ex2_powsh_no_sat_rgt :std_ulogic ; + +signal ex1_act, ex2_act, ex3_act, ex4_act :std_ulogic; +signal act_so, act_si :std_ulogic_vector(0 to 7); +signal act_spare_unused :std_ulogic_vector(0 to 3); +signal unused :std_ulogic; +signal ex2_ube_g2_b , ex2_ube_g4, ex2_ube_g8_b :std_ulogic_vector(2 to 11) ; + + + +signal s2_0, s2_1, s3_0, s3_1, sx :std_ulogic; +signal s7_if_s1, s7_if_s20, s7_if_s30, s7_if_sx, s7_if_s31, s7_if_s21 :std_ulogic; +signal c6_if_s1, c6_if_s20, c6_if_s30, c6_if_sx, c6_if_s31, c6_if_s21 :std_ulogic; + +signal s6_if_s1, s6_if_s20, s6_if_s30, s6_if_sx, s6_if_s31, s6_if_s21 :std_ulogic; +signal c5_if_s1, c5_if_s20, c5_if_s30, c5_if_sx, c5_if_s31, c5_if_s21 :std_ulogic; + +signal s5_if_s1, s5_if_s20, s5_if_s30, s5_if_sx, s5_if_s31, s5_if_s21 :std_ulogic; +signal c4_if_s1, c4_if_s20, c4_if_s30, c4_if_sx, c4_if_s31, c4_if_s21 :std_ulogic; + +signal s4_if_s1, s4_if_s20, s4_if_s30, s4_if_sx, s4_if_s31, s4_if_s21 :std_ulogic; +signal c3_if_s1, c3_if_s20, c3_if_s30, c3_if_sx, c3_if_s31, c3_if_s21 :std_ulogic; + +signal es4_if_s1, es4_if_s20, es4_if_s30, es4_if_sx, es4_if_s31, es4_if_s21 :std_ulogic; +signal ec3_if_s1, ec3_if_s20, ec3_if_s30, ec3_if_sx, ec3_if_s31, ec3_if_s21 :std_ulogic; + +signal es5_if_s1, es5_if_s20, es5_if_s30, es5_if_sx, es5_if_s31, es5_if_s21 :std_ulogic; +signal ec4_if_s1, ec4_if_s20, ec4_if_s30, ec4_if_sx, ec4_if_s31, ec4_if_s21 :std_ulogic; + +signal es6_if_s1, es6_if_s20, es6_if_s30, es6_if_sx, es6_if_s31, es6_if_s21 :std_ulogic; +signal ec5_if_s1, ec5_if_s20, ec5_if_s30, ec5_if_sx, ec5_if_s31, ec5_if_s21 :std_ulogic; + +signal es7_if_s1, es7_if_s20, es7_if_s30, es7_if_sx, es7_if_s31, es7_if_s21 :std_ulogic; +signal ec6_if_s1, ec6_if_s20, ec6_if_s30, ec6_if_sx, ec6_if_s31, ec6_if_s21 :std_ulogic; + + signal es2_0, es2_1, esx, es3_0, es3_1 :std_ulogic ; + + + + +begin + + +unused <= ex2_b_biased_13exp(1) or ex2_b_biased_13exp(2) or + ex2_b_ubexp(2) or ex2_b_ubexp(3) or + ex2_mantissa_shlev3(0) or + ex2_mantissa_shlev3(1) or + ex2_mantissa_shlev3(2) or + ex2_mantissa_shlev3(3) or + ex2_mantissa_shlev3(4) or + ex2_mantissa_shlev3(5) or + ex2_mantissa_shlev3(6) or + ex2_mantissa_shlev3(7) or + ex2_mantissa_shlev3(27) or + ex2_mantissa_shlev3(28) or + ex2_mantissa_shlev3(29) or + ex2_mantissa_shlev3(30) or + ex2_mantissa_shlev3(31) or + ex2_mantissa_shlev3(32) or + ex2_mantissa_shlev3(33) or + ex2_mantissa_shlev3(34) or + ex2_mantissa_shlev3(35) or + ex2_mantissa_shlev3(36) or + ex2_mantissa_shlev3(37) or + ex2_mantissa_shlev3(38) or + ex2_mantissa_shlev3(39) or + ex2_mantissa_shlev3(40) or + ex2_mantissa_shlev3(41) or + ex2_mantissa_shlev3(42) or + ex2_mantissa_shlev3(43) or + ex2_mantissa_shlev3(44) or + ex2_mantissa_shlev3(45) or + ex2_mantissa_shlev3(46) or + ex2_mantissa_shlev3(47) or + ex2_mantissa_shlev3(48) or + ex2_mantissa_shlev3(49) or + ex2_mantissa_shlev3(50) or + or_reduce( ex4_mantissa_shlev3(1 to 31) ) or + or_reduce( ex2_a(4 to 7) ) or + or_reduce( ex2_c(4 to 11) ) or + or_reduce( ex4_addend1(1 to 11) ) or + or_reduce( ex4_addend2(1 to 11) ) or + or_reduce( ex4_addend3(1 to 11) ) or + s2 or + s3 or + es2 or + es3 ; + + + thold_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => thold_1, + q(0) => thold_0 ); + + sg_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => sg_1 , + q(0) => sg_0 ); + + + lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map ( + clkoff_b => clkoff_b, + thold => thold_0, + sg => sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => thold_0_b ); + + + + + + act_lat: tri_rlmreg_p generic map (width=> 8, expand_type => expand_type, needs_sreset => 0) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(4), + mpw1_b => mpw1_b(4), + mpw2_b => mpw2_b(0), + vd => vdd, + gd => gnd, + nclk => nclk, + act => fpu_enable, + thold_b => thold_0_b, + sg => sg_0, + scout => act_so , + scin => act_si , + din(0) => act_spare_unused(0), + din(1) => act_spare_unused(1), + din(2) => rf1_act, + din(3) => ex1_act, + din(4) => ex2_act, + din(5) => ex3_act, + din(6) => act_spare_unused(2), + din(7) => act_spare_unused(3), + dout(0) => act_spare_unused(0), + dout(1) => act_spare_unused(1), + dout(2) => ex1_act, + dout(3) => ex2_act, + dout(4) => ex3_act, + dout(5) => ex4_act, + dout(6) => act_spare_unused(2) , + dout(7) => act_spare_unused(3) ); + + + + +zeros <= (1 to 16 => tidn); + + + + + + + + + ex1_floges <= f_pic_ex1_floges; + ex1_fexptes <= f_pic_ex1_fexptes; + + + + ex2_gst_ctrl_lat : tri_rlmreg_p generic map (expand_type => expand_type, width=> 2, needs_sreset => 0) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(2), + mpw1_b => mpw1_b(2), + mpw2_b => mpw2_b(0), + vd => vdd, gd => gnd, + nclk => nclk, thold_b => thold_0_b, sg => sg_0, + act => ex1_act, + scout => ex2_gst_ctrl_lat_scout, + scin => ex2_gst_ctrl_lat_scin, + din(00) => ex1_floges, + din(01) => ex1_fexptes, + dout(00) => ex2_floges, + dout(01) => ex2_fexptes + ); + + + + + +f_fmt_ex1_b_expo_gst <= not f_fmt_ex1_b_expo_gst_b; + + ex2_gst_stage_lat: tri_rlmreg_p generic map (expand_type => expand_type, width=> 33, needs_sreset => 0) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(2), + mpw1_b => mpw1_b(2), + mpw2_b => mpw2_b(0), + vd => vdd, gd => gnd, + nclk => nclk, thold_b => thold_0_b, sg => sg_0, + act => ex1_act, + scout => ex2_gst_stage_lat_scout, + scin => ex2_gst_stage_lat_scin, + din(00) => f_fmt_ex1_b_sign_gst, + din(01 to 13) => f_fmt_ex1_b_expo_gst, + din(14 to 32) => f_fmt_ex1_b_frac_gst, + + dout(00) => ex2_b_sign, + dout(01 to 13) => ex2_b_biased_13exp, + dout(14 to 32) => ex2_b_fract + + ); + + + +ex2_f(1 to 11) <= ex2_b_fract(1 to 11); + + +f1 <= ex2_f(1); +f2 <= ex2_f(2); +f3 <= ex2_f(3); +f4 <= ex2_f(4); +f5 <= ex2_f(5); +f6 <= ex2_f(6); +f7 <= ex2_f(7); +f8 <= ex2_f(8); +f9 <= ex2_f(9); +f10 <= ex2_f(10); + +s1 <= (not f1 and not f2 and not f3 and not f4 ); +s2_0 <= (not f1 and not f2 and not f3 and f4 ) or + (not f1 and not f2 and f3 and not f4 ); +s3_0 <= (not f1 and not f2 and f3 and f4 ) or + (not f1 and f2 and not f3 ); +sx <= (not f1 and f2 and f3 )or + ( f1 and not f2 and not f3 and not f4 ); +s3_1 <= ( f1 and not f2 and not f3 and f4 ) or + ( f1 and not f2 and f3 ); +s2_1 <= ( f1 and f2 ); + +s2 <= s2_0 or s2_1 ; +s3 <= s3_0 or s3_1 ; + + + +c4 <= sx ; +c5 <= s3_0 or s3_1 ; +c6 <= sx or s2_0; +c7 <= sx or s3_0 ; + + + + + + + +a4 <= (s1 and f3) or + (s2_0 and f2) or + (s2_1 and not f2); + +a5 <= (s1 and f4) or + (s2_0 and f3) or + (s2_1 and not f3) or + (s3_0 and f2) or + (s3_1 and not f2); + +a6 <= (s1 and f5) or + (s2_0 and f4) or + (s2_1 and not f4) or + (s3_0 and f3) or + (s3_1 and not f3); + +a7 <= (s1 and f6) or + (s2_0 and f5) or + (s2_1 and not f5) or + (s3_0 and f4) or + (s3_1 and not f4); + + +a8 <= (s1 and f7) or + (s2_0 and f6) or + (s2_1 and not f6) or + (s3_0 and f5) or + (s3_1 and not f5); + +a9 <= (s1 and f8) or + (s2_0 and f7) or + (s2_1 and not f7) or + (s3_0 and f6) or + (s3_1 and not f6); + +a10 <= (s1 and f9) or + (s2_0 and f8) or + (s2_1 and not f8) or + (s3_0 and f7) or + (s3_1 and not f7); + +a11 <= (s1 and f10) or + (s2_0 and f9) or + (s2_1 and not f9) or + (s3_0 and f8) or + (s3_1 and not f8); + + +ex2_a(4 to 11) <= a4 & a5 & a6 & a7 & a8 & a9 & a10 & a11; +ex2_c(4 to 11) <= c4 & c5 & c6 & c7 & tidn & tidn & tidn & tidn; + + + + + + + c3_if_s1 <= f4 and f3 ; + c3_if_s20 <= f4 and f2 ; + c3_if_s30 <= tidn ; + c3_if_sx <= f4 ; + c3_if_s31 <= tidn ; + c3_if_s21 <= f4 and not f2 ; + + s4_if_s1 <= f4 xor f3 ; + s4_if_s20 <= f4 xor f2 ; + s4_if_s30 <= f4 ; + s4_if_sx <= not f4 ; + s4_if_s31 <= f4 ; + s4_if_s21 <= f4 xor not f2 ; + + + c4_if_s1 <= f5 and f4 ; + c4_if_s20 <= f5 and f3 ; + c4_if_s30 <= f5 or f2 ; + c4_if_sx <= tidn ; + c4_if_s31 <= f5 or not f2 ; + c4_if_s21 <= f5 and not f3 ; + + s5_if_s1 <= f5 xor f4 ; + s5_if_s20 <= f5 xor f3 ; + s5_if_s30 <= f5 xor not f2 ; + s5_if_sx <= f5 ; + s5_if_s31 <= f5 xor f2 ; + s5_if_s21 <= f5 xor not f3 ; + + + c5_if_s1 <= f6 and f5 ; + c5_if_s20 <= f6 or f4 ; + c5_if_s30 <= f6 and f3 ; + c5_if_sx <= f6 ; + c5_if_s31 <= f6 and not f3 ; + c5_if_s21 <= f6 and not f4 ; + + s6_if_s1 <= f6 xor f5 ; + s6_if_s20 <= f6 xor not f4 ; + s6_if_s30 <= f6 xor f3 ; + s6_if_sx <= not f6 ; + s6_if_s31 <= f6 xor not f3 ; + s6_if_s21 <= f6 xor not f4 ; + + + c6_if_s1 <= f7 and f6 ; + c6_if_s20 <= f7 and f5 ; + c6_if_s30 <= f7 or f4 ; + c6_if_sx <= f7 ; + c6_if_s31 <= f7 and not f4 ; + c6_if_s21 <= f7 and not f5 ; + + s7_if_s1 <= f7 xor f6 ; + s7_if_s20 <= f7 xor f5 ; + s7_if_s30 <= f7 xor not f4 ; + s7_if_sx <= not f7 ; + s7_if_s31 <= f7 xor not f4 ; + s7_if_s21 <= f7 xor not f5 ; + + + + ex2_log_fsum(4) <= + ( s1 and s4_if_s1 ) or + ( s2_0 and s4_if_s20 ) or + ( s3_0 and s4_if_s30 ) or + ( sx and s4_if_sx ) or + ( s3_1 and s4_if_s31 ) or + ( s2_1 and s4_if_s21 ) ; + + ex2_log_fcarryin(3) <= + ( s1 and c3_if_s1 ) or + ( s2_0 and c3_if_s20 ) or + ( s3_0 and c3_if_s30 ) or + ( sx and c3_if_sx ) or + ( s3_1 and c3_if_s31 ) or + ( s2_1 and c3_if_s21 ) ; + + + + ex2_log_fsum(5) <= + ( s1 and s5_if_s1 ) or + ( s2_0 and s5_if_s20 ) or + ( s3_0 and s5_if_s30 ) or + ( sx and s5_if_sx ) or + ( s3_1 and s5_if_s31 ) or + ( s2_1 and s5_if_s21 ) ; + + ex2_log_fcarryin(4) <= + ( s1 and c4_if_s1 ) or + ( s2_0 and c4_if_s20 ) or + ( s3_0 and c4_if_s30 ) or + ( sx and c4_if_sx ) or + ( s3_1 and c4_if_s31 ) or + ( s2_1 and c4_if_s21 ) ; + + + + ex2_log_fsum(6) <= + ( s1 and s6_if_s1 ) or + ( s2_0 and s6_if_s20 ) or + ( s3_0 and s6_if_s30 ) or + ( sx and s6_if_sx ) or + ( s3_1 and s6_if_s31 ) or + ( s2_1 and s6_if_s21 ) ; + + ex2_log_fcarryin(5) <= + ( s1 and c5_if_s1 ) or + ( s2_0 and c5_if_s20 ) or + ( s3_0 and c5_if_s30 ) or + ( sx and c5_if_sx ) or + ( s3_1 and c5_if_s31 ) or + ( s2_1 and c5_if_s21 ) ; + + + + + ex2_log_fsum(7) <= + ( s1 and s7_if_s1 ) or + ( s2_0 and s7_if_s20 ) or + ( s3_0 and s7_if_s30 ) or + ( sx and s7_if_sx ) or + ( s3_1 and s7_if_s31 ) or + ( s2_1 and s7_if_s21 ) ; + + ex2_log_fcarryin(6) <= + ( s1 and c6_if_s1 ) or + ( s2_0 and c6_if_s20 ) or + ( s3_0 and c6_if_s30 ) or + ( sx and c6_if_sx ) or + ( s3_1 and c6_if_s31 ) or + ( s2_1 and c6_if_s21 ) ; + + ex2_log_a_addend_b(1) <= not( ex2_f(1) ) ; + ex2_log_a_addend_b(2) <= not( ex2_f(2) ) ; + ex2_log_a_addend_b(3) <= not( ex2_f(3) ) ; + ex2_log_a_addend_b(4) <= not( ex2_log_fsum(4) ); + ex2_log_a_addend_b(5) <= not( ex2_log_fsum(5) ); + ex2_log_a_addend_b(6) <= not( ex2_log_fsum(6) ); + ex2_log_a_addend_b(7) <= not( ex2_log_fsum(7) ); + ex2_log_a_addend_b(8) <= not( ex2_f(8) ); + ex2_log_a_addend_b(9) <= not( ex2_f(9) ); + ex2_log_a_addend_b(10) <= not( ex2_f(10)); + ex2_log_a_addend_b(11) <= not( ex2_f(11)); + + ex2_log_b_addend_b(1) <= not( tidn ) ; + ex2_log_b_addend_b(2) <= not( tidn ) ; + ex2_log_b_addend_b(3) <= not( ex2_log_fcarryin(3) ); + ex2_log_b_addend_b(4) <= not( ex2_log_fcarryin(4) ); + ex2_log_b_addend_b(5) <= not( ex2_log_fcarryin(5) ); + ex2_log_b_addend_b(6) <= not( ex2_log_fcarryin(6) ); + ex2_log_b_addend_b(7) <= not( tidn ); + ex2_log_b_addend_b(8) <= not( ex2_a(8) ); + ex2_log_b_addend_b(9) <= not( ex2_a(9) ); + ex2_log_b_addend_b(10) <= not( ex2_a(10) ); + ex2_log_b_addend_b(11) <= not( ex2_a(11) ); + + + + + +ex2_b_biased_11exp(1 to 11) <= ex2_b_biased_13exp(3 to 13); + + +ex2_b_ubexp_sum(01) <= not ex2_b_biased_11exp(01); +ex2_b_ubexp_sum(02 to 10) <= ex2_b_biased_11exp(02 to 10); +ex2_b_ubexp_sum(11) <= not ex2_b_biased_11exp(11); + + +ex2_ube_g2_b(11) <= not( ex2_b_biased_11exp(11) ); +ex2_ube_g2_b(10) <= not( ex2_b_biased_11exp(10) and ex2_b_biased_11exp(11) ); +ex2_ube_g2_b( 9) <= not( ex2_b_biased_11exp( 9) and ex2_b_biased_11exp(10) ); +ex2_ube_g2_b( 8) <= not( ex2_b_biased_11exp( 8) and ex2_b_biased_11exp( 9) ); +ex2_ube_g2_b( 7) <= not( ex2_b_biased_11exp( 7) and ex2_b_biased_11exp( 8) ); +ex2_ube_g2_b( 6) <= not( ex2_b_biased_11exp( 6) and ex2_b_biased_11exp( 7) ); +ex2_ube_g2_b( 5) <= not( ex2_b_biased_11exp( 5) and ex2_b_biased_11exp( 6) ); +ex2_ube_g2_b( 4) <= not( ex2_b_biased_11exp( 4) and ex2_b_biased_11exp( 5) ); +ex2_ube_g2_b( 3) <= not( ex2_b_biased_11exp( 3) and ex2_b_biased_11exp( 4) ); +ex2_ube_g2_b( 2) <= not( ex2_b_biased_11exp( 2) and ex2_b_biased_11exp( 3) ); + + +ex2_ube_g4 (11) <= not( ex2_ube_g2_b(11) ); +ex2_ube_g4 (10) <= not( ex2_ube_g2_b(10) ); +ex2_ube_g4 ( 9) <= not( ex2_ube_g2_b( 9) or ex2_ube_g2_b(11) ); +ex2_ube_g4 ( 8) <= not( ex2_ube_g2_b( 8) or ex2_ube_g2_b(10) ); +ex2_ube_g4 ( 7) <= not( ex2_ube_g2_b( 7) or ex2_ube_g2_b( 9) ); +ex2_ube_g4 ( 6) <= not( ex2_ube_g2_b( 6) or ex2_ube_g2_b( 8) ); +ex2_ube_g4 ( 5) <= not( ex2_ube_g2_b( 5) or ex2_ube_g2_b( 7) ); +ex2_ube_g4 ( 4) <= not( ex2_ube_g2_b( 4) or ex2_ube_g2_b( 6) ); +ex2_ube_g4 ( 3) <= not( ex2_ube_g2_b( 3) or ex2_ube_g2_b( 5) ); +ex2_ube_g4 ( 2) <= not( ex2_ube_g2_b( 2) or ex2_ube_g2_b( 4) ); + +ex2_ube_g8_b(11) <= not( ex2_ube_g4(11) ); +ex2_ube_g8_b(10) <= not( ex2_ube_g4(10) ); +ex2_ube_g8_b( 9) <= not( ex2_ube_g4( 9) ); +ex2_ube_g8_b( 8) <= not( ex2_ube_g4( 8) ); +ex2_ube_g8_b( 7) <= not( ex2_ube_g4( 7) and ex2_ube_g4(11) ); +ex2_ube_g8_b( 6) <= not( ex2_ube_g4( 6) and ex2_ube_g4(10) ); +ex2_ube_g8_b( 5) <= not( ex2_ube_g4( 5) and ex2_ube_g4( 9) ); +ex2_ube_g8_b( 4) <= not( ex2_ube_g4( 4) and ex2_ube_g4( 8) ); +ex2_ube_g8_b( 3) <= not( ex2_ube_g4( 3) and ex2_ube_g4( 7) ); +ex2_ube_g8_b( 2) <= not( ex2_ube_g4( 2) and ex2_ube_g4( 6) ); + +ex2_b_ubexp_cout(11) <= not( ex2_ube_g8_b(11) ) ; +ex2_b_ubexp_cout(10) <= not( ex2_ube_g8_b(10) ) ; +ex2_b_ubexp_cout( 9) <= not( ex2_ube_g8_b( 9) ) ; +ex2_b_ubexp_cout( 8) <= not( ex2_ube_g8_b( 8) ) ; +ex2_b_ubexp_cout( 7) <= not( ex2_ube_g8_b( 7) ) ; +ex2_b_ubexp_cout( 6) <= not( ex2_ube_g8_b( 6) ) ; +ex2_b_ubexp_cout( 5) <= not( ex2_ube_g8_b( 5) ) ; +ex2_b_ubexp_cout( 4) <= not( ex2_ube_g8_b( 4) ) ; +ex2_b_ubexp_cout( 3) <= not( ex2_ube_g8_b( 3) or ex2_ube_g8_b(11) ); +ex2_b_ubexp_cout( 2) <= not( ex2_ube_g8_b( 2) or ex2_ube_g8_b(10) ); + +ex2_b_ubexp(01 to 10) <= ex2_b_ubexp_sum(01 to 10) xor ex2_b_ubexp_cout(02 to 11); +ex2_b_ubexp(11) <= ex2_b_ubexp_sum(11); + + +ex2_logadd11: entity work.fuq_gst_add11(fuq_gst_add11) port map( + a_b(0 to 10) => ex2_log_a_addend_b(1 to 11), + b_b(0 to 10) => ex2_log_b_addend_b(1 to 11), + s0(0 to 10) => ex2_log_mantissa_precomp(9 to 19) + ); + + + ex2_log_mantissa_precomp(1 to 8) <= ex2_b_ubexp(4 to 11); + + +ex2_mantissa_shlev0(00 to 19) <= tiup & ex2_b_fract(01 to 19); + +ex2_shamt(0 to 4) <= ex2_b_ubexp(1) & ex2_b_ubexp(08 to 11); + + + +ex2_powsh_no_sat_lft <= not ex2_b_ubexp(2) and + not ex2_b_ubexp(3) and + not ex2_b_ubexp(4) and + not ex2_b_ubexp(5) and + not ex2_b_ubexp(6) and + not ex2_b_ubexp(7) ; + +ex2_powsh_no_sat_rgt <= ex2_b_ubexp(2) and + ex2_b_ubexp(3) and + ex2_b_ubexp(4) and + ex2_b_ubexp(5) and + ex2_b_ubexp(6) and + ex2_b_ubexp(7) ; + + +l1_e00 <= not ex2_shamt(3) and not ex2_shamt(4); +l1_e01 <= not ex2_shamt(3) and ex2_shamt(4); +l1_e10 <= ex2_shamt(3) and not ex2_shamt(4); +l1_e11 <= ex2_shamt(3) and ex2_shamt(4); + +l2_e00 <= not ex2_shamt(1) and not ex2_shamt(2); +l2_e01 <= not ex2_shamt(1) and ex2_shamt(2); +l2_e10 <= ex2_shamt(1) and not ex2_shamt(2); +l2_e11 <= ex2_shamt(1) and ex2_shamt(2); + + + l3_e00 <= not ex2_shamt(0) and ex2_powsh_no_sat_lft; + l3_e01 <= ex2_shamt(0) and ex2_powsh_no_sat_rgt; + + +ex2_mantissa_shlev1(00 to 22) <= (zeros(01 to 03) & (ex2_mantissa_shlev0(00 to 19) ) and (00 to 22 => l1_e00)) or + (zeros(01 to 02) & (ex2_mantissa_shlev0(00 to 19) & zeros(01) ) and (00 to 22 => l1_e01)) or + (zeros(01 ) & (ex2_mantissa_shlev0(00 to 19) & zeros(01 to 02)) and (00 to 22 => l1_e10)) or + ( (ex2_mantissa_shlev0(00 to 19) & zeros(01 to 03)) and (00 to 22 => l1_e11)) ; + + +ex2_mantissa_shlev2(00 to 34) <= (zeros(01 to 12) & (ex2_mantissa_shlev1(00 to 22) ) and (00 to 34 => l2_e00)) or + (zeros(01 to 08) & (ex2_mantissa_shlev1(00 to 22) & zeros(01 to 04)) and (00 to 34 => l2_e01)) or + (zeros(01 to 04) & (ex2_mantissa_shlev1(00 to 22) & zeros(01 to 08)) and (00 to 34 => l2_e10)) or + ( (ex2_mantissa_shlev1(00 to 22) & zeros(01 to 12)) and (00 to 34 => l2_e11)) ; + + +ex2_mantissa_shlev3(00 to 50) <= ( (ex2_mantissa_shlev2(00 to 34) & zeros(01 to 16)) and (00 to 50 => l3_e00)) or + (zeros(01 to 16) & (ex2_mantissa_shlev2(00 to 34) ) and (00 to 50 => l3_e01)) ; + + +ex2_pow_int(1 to 8) <= ex2_mantissa_shlev3(08 to 15); +ex2_pow_frac(1 to 11) <= ex2_mantissa_shlev3(16 to 26); + + + +ex2_mantissa_din(1 to 19) <= ((ex2_pow_int(1 to 8) & ex2_pow_frac(1 to 11)) and (1 to 19 => ex2_fexptes)) or + (ex2_log_mantissa_precomp(1 to 19) and (1 to 19 => ex2_floges )); + + ex3_gst_ctrl_lat : tri_rlmreg_p generic map (expand_type => expand_type, width=> 2, needs_sreset => 0) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(3), + mpw1_b => mpw1_b(3), + mpw2_b => mpw2_b(0), + vd => vdd, gd => gnd, + nclk => nclk, thold_b => thold_0_b, sg => sg_0, + act => ex2_act, + scout => ex3_gst_ctrl_lat_scout, + scin => ex3_gst_ctrl_lat_scin, + din(00) => ex2_floges, + din(01) => ex2_fexptes, + dout(00) => ex3_floges, + dout(01) => ex3_fexptes + ); + + ex3_gst_stage_lat: tri_rlmreg_p generic map (expand_type => expand_type, width => 20, needs_sreset => 0 ) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(3), + mpw1_b => mpw1_b(3), + mpw2_b => mpw2_b(0), + vd => vdd, gd => gnd, + nclk => nclk, thold_b => thold_0_b, sg => sg_0, + act => ex2_act, + scout => ex3_gst_stage_lat_scout, + scin => ex3_gst_stage_lat_scin, + din(00 to 18) => ex2_mantissa_din, + din(19) => ex2_b_sign, + dout(00 to 18) => ex3_mantissa_precomp, + dout(19) => ex3_b_sign + + ); + + +ex3_mantissa_precomp_b <= not ex3_mantissa_precomp(1 to 19); + +ex3_log_inc: entity work.fuq_gst_inc19(fuq_gst_inc19) port map( + a(1 to 19) => ex3_mantissa_precomp_b(1 to 19), + o(1 to 19) => ex3_mantissa_neg(1 to 19) + ); + +ex3_negate <= (ex3_mantissa_precomp(1) and ex3_floges) or (ex3_fexptes and ex3_b_sign); + + ex3_mantissa(1 to 19) <= ( ex3_mantissa_neg(1 to 19) and (1 to 19 => ex3_negate)) or + ( ex3_mantissa_precomp(1 to 19) and not (1 to 19 => ex3_negate)); + + + +ex3_log_loa: entity work.fuq_gst_loa(fuq_gst_loa) port map( + a(1 to 19) => ex3_mantissa, + shamt(0 to 4) => ex3_shamt(0 to 4) + ); + +ex3_logof1_specialcase <= not or_reduce(ex3_shamt(0 to 4)); + + ex4_gst_ctrl_lat : tri_rlmreg_p generic map (expand_type => expand_type, width=> 4, needs_sreset => 0) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(4), + mpw1_b => mpw1_b(4), + mpw2_b => mpw2_b(0), + vd => vdd, gd => gnd, + nclk => nclk, thold_b => thold_0_b, sg => sg_0, + act => ex3_act, + scout => ex4_gst_ctrl_lat_scout, + scin => ex4_gst_ctrl_lat_scin, + din(00) => ex3_floges, + din(01) => ex3_fexptes, + din(02) => ex3_negate, + din(03) => ex3_logof1_specialcase, + dout(00) => ex4_floges, + dout(01) => ex4_fexptes, + dout(02) => ex4_negate, + dout(03) => ex4_logof1_specialcase + ); + + + ex4_gst_stage_lat: tri_rlmreg_p generic map (expand_type => expand_type, width => 24, needs_sreset => 0 ) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(4), + mpw1_b => mpw1_b(4), + mpw2_b => mpw2_b(0), + vd => vdd, gd => gnd, + nclk => nclk, thold_b => thold_0_b, sg => sg_0, + act => ex3_act, + scout => ex4_gst_stage_lat_scout, + scin => ex4_gst_stage_lat_scin, + din(00 to 18) => ex3_mantissa, + din(19 to 23) => ex3_shamt, + dout(00 to 18) => ex4_mantissa, + dout(19 to 23) => ex4_shamt + ); + + + + +ex4_mantissa_shlev0(01 to 19) <= ex4_mantissa(01 to 19); + + +l1_enc00 <= not ex4_shamt(3) and not ex4_shamt(4); +l1_enc01 <= not ex4_shamt(3) and ex4_shamt(4); +l1_enc10 <= ex4_shamt(3) and not ex4_shamt(4); +l1_enc11 <= ex4_shamt(3) and ex4_shamt(4); + +l2_enc00 <= not ex4_shamt(1) and not ex4_shamt(2); +l2_enc01 <= not ex4_shamt(1) and ex4_shamt(2); +l2_enc10 <= ex4_shamt(1) and not ex4_shamt(2); +l2_enc11 <= ex4_shamt(1) and ex4_shamt(2); + +l3_enc00 <= not ex4_shamt(0); +l3_enc01 <= ex4_shamt(0); + + + + + + +ex4_mantissa_shlev1(01 to 22) <= (zeros(01 to 03) & (ex4_mantissa_shlev0(01 to 19) ) and (01 to 22 => l1_enc00)) or + (zeros(01 to 02) & (ex4_mantissa_shlev0(01 to 19) & zeros(01) ) and (01 to 22 => l1_enc01)) or + (zeros(01 ) & (ex4_mantissa_shlev0(01 to 19) & zeros(01 to 02)) and (01 to 22 => l1_enc10)) or + ( (ex4_mantissa_shlev0(01 to 19) & zeros(01 to 03)) and (01 to 22 => l1_enc11)) ; + + + +ex4_mantissa_shlev2(01 to 34) <= (zeros(01 to 12) & (ex4_mantissa_shlev1(01 to 22) ) and (01 to 34 => l2_enc00)) or + (zeros(01 to 08) & (ex4_mantissa_shlev1(01 to 22) & zeros(01 to 04)) and (01 to 34 => l2_enc01)) or + (zeros(01 to 04) & (ex4_mantissa_shlev1(01 to 22) & zeros(01 to 08)) and (01 to 34 => l2_enc10)) or + ( (ex4_mantissa_shlev1(01 to 22) & zeros(01 to 12)) and (01 to 34 => l2_enc11)) ; + + +ex4_mantissa_shlev3(01 to 50) <= (zeros(01 to 16) & (ex4_mantissa_shlev2(01 to 34) ) and (01 to 50 => l3_enc00)) or + ( (ex4_mantissa_shlev2(01 to 34) & zeros(01 to 16)) and (01 to 50 => l3_enc01)) ; + + + + +ex4_log_mantissa_postsh(01 to 19) <= ex4_mantissa_shlev3(32 to 50); + + +ex4_f(1 to 11) <= ex4_mantissa(9 to 19); + + eb1 <= ex4_f(1); + eb2 <= ex4_f(2); + eb3 <= ex4_f(3); + eb4 <= ex4_f(4); + eb5 <= ex4_f(5); + eb6 <= ex4_f(6); + eb7 <= ex4_f(7); + eb8 <= ex4_f(8); + eb9 <= ex4_f(9); + eb10 <= ex4_f(10); + + ex4_f_b(1 to 11) <= not ex4_f(1 to 11); + + + es2_0 <= ( not eb1 and not eb2 ) ; + es3_0 <= ( not eb1 and eb2 and not eb3 ) or + ( not eb1 and eb2 and eb3 and not eb4 ) ; + esx <= ( not eb1 and eb2 and eb3 and eb4 ) or + ( eb1 and not eb2 and not eb3 ) ; + es3_1 <= ( eb1 and not eb2 and eb3 ) or + ( eb1 and eb2 and not eb3 and not eb4 ) ; + es2_1 <= ( eb1 and eb2 and not eb3 and eb4 ) or + ( eb1 and eb2 and eb3 and not eb4 ) ; + es1 <= ( eb1 and eb2 and eb3 and eb4 ) ; + + es2 <= es2_0 or es2_1; + es3 <= es3_0 or es3_1; + + ec4 <= esx ; + ec5 <= es3_0 or es3_1; + ec6 <= esx or es2_1; + ec7 <= esx or es3_1; + + + + + ec3_if_s20 <= not eb4 and eb2 ; + ec3_if_s30 <= tidn ; + ec3_if_sx <= not eb4 ; + ec3_if_s31 <= tidn ; + ec3_if_s21 <= not eb4 and not eb2 ; + ec3_if_s1 <= not eb4 and not eb3 ; + + es4_if_s20 <= not eb4 xor eb2 ; + es4_if_s30 <= not eb4 ; + es4_if_sx <= eb4 ; + es4_if_s31 <= not eb4 ; + es4_if_s21 <= not eb4 xor not eb2 ; + es4_if_s1 <= not eb4 xor not eb3 ; + + + ec4_if_s20 <= not eb5 and eb3 ; + ec4_if_s30 <= not eb5 or eb2 ; + ec4_if_sx <= tidn ; + ec4_if_s31 <= not eb5 or not eb2 ; + ec4_if_s21 <= not eb5 and not eb3 ; + ec4_if_s1 <= not eb5 and not eb4 ; + + es5_if_s20 <= not eb5 xor eb3 ; + es5_if_s30 <= not eb5 xor not eb2 ; + es5_if_sx <= not eb5 ; + es5_if_s31 <= not eb5 xor eb2 ; + es5_if_s21 <= not eb5 xor not eb3 ; + es5_if_s1 <= not eb5 xor not eb4 ; + + + ec5_if_s20 <= not eb6 and eb4 ; + ec5_if_s30 <= not eb6 and eb3 ; + ec5_if_sx <= not eb6 ; + ec5_if_s31 <= not eb6 and not eb3 ; + ec5_if_s21 <= not eb6 or not eb4 ; + ec5_if_s1 <= not eb6 and not eb5 ; + + es6_if_s20 <= not eb6 xor eb4 ; + es6_if_s30 <= not eb6 xor eb3 ; + es6_if_sx <= eb6 ; + es6_if_s31 <= not eb6 xor not eb3 ; + es6_if_s21 <= not eb6 xor eb4 ; + es6_if_s1 <= not eb6 xor not eb5 ; + + ec6_if_s20 <= not eb7 and eb5 ; + ec6_if_s30 <= not eb7 and eb4 ; + ec6_if_sx <= not eb7 ; + ec6_if_s31 <= not eb7 or not eb4 ; + ec6_if_s21 <= not eb7 and not eb5 ; + ec6_if_s1 <= not eb7 and not eb6 ; + + es7_if_s20 <= not eb7 xor eb5 ; + es7_if_s30 <= not eb7 xor eb4 ; + es7_if_sx <= eb7 ; + es7_if_s31 <= not eb7 xor eb4 ; + es7_if_s21 <= not eb7 xor not eb5 ; + es7_if_s1 <= not eb7 xor not eb6 ; + + + + + + + + + ea4 <= (es1 and not eb3) or + (es2_0 and eb2) or + (es2_1 and not eb2); + + ea5 <= (es1 and not eb4) or + (es2_0 and eb3) or + (es2_1 and not eb3) or + (es3_0 and eb2) or + (es3_1 and not eb2); + + ea6 <= (es1 and not eb5) or + (es2_0 and eb4) or + (es2_1 and not eb4) or + (es3_0 and eb3) or + (es3_1 and not eb3); + + ea7 <= (es1 and not eb6) or + (es2_0 and eb5) or + (es2_1 and not eb5) or + (es3_0 and eb4) or + (es3_1 and not eb4); + + ea8 <= (es1 and not eb7) or + (es2_0 and eb6) or + (es2_1 and not eb6) or + (es3_0 and eb5) or + (es3_1 and not eb5); + + ea9 <= (es1 and not eb8) or + (es2_0 and eb7) or + (es2_1 and not eb7) or + (es3_0 and eb6) or + (es3_1 and not eb6); + + ea10 <= (es1 and not eb9) or + (es2_0 and eb8) or + (es2_1 and not eb8) or + (es3_0 and eb7) or + (es3_1 and not eb7); + + ea11 <= (es1 and not eb10) or + (es2_0 and eb9) or + (es2_1 and not eb9) or + (es3_0 and eb8) or + (es3_1 and not eb8); + + + + + +ex4_ea(4 to 11) <= ea4 & ea5 & ea6 & ea7 & ea8 & ea9 & ea10 & ea11; +ex4_ec(4 to 11) <= ec4 & ec5 & ec6 & ec7 & zeros(1 to 4); + +ex4_addend1(1 to 11) <= ex4_f_b(1 to 11); +ex4_addend2(1 to 11) <= zeros(1 to 3) & ex4_ea(4 to 11); +ex4_addend3(1 to 11) <= zeros(1 to 3) & ex4_ec(4 to 11); + + ex4_fsum(1) <= ex4_f_b(1) ; + ex4_fsum(2) <= ex4_f_b(2) ; + ex4_fsum(3) <= ex4_f_b(3) ; + ex4_fsum(4) <= + ( es1 and es4_if_s1 ) or + ( es2_0 and es4_if_s20 ) or + ( es3_0 and es4_if_s30 ) or + ( esx and es4_if_sx ) or + ( es3_1 and es4_if_s31 ) or + ( es2_1 and es4_if_s21 ) ; + ex4_fsum(5) <= + ( es1 and es5_if_s1 ) or + ( es2_0 and es5_if_s20 ) or + ( es3_0 and es5_if_s30 ) or + ( esx and es5_if_sx ) or + ( es3_1 and es5_if_s31 ) or + ( es2_1 and es5_if_s21 ) ; + ex4_fsum(6) <= + ( es1 and es6_if_s1 ) or + ( es2_0 and es6_if_s20 ) or + ( es3_0 and es6_if_s30 ) or + ( esx and es6_if_sx ) or + ( es3_1 and es6_if_s31 ) or + ( es2_1 and es6_if_s21 ) ; + ex4_fsum(7) <= + ( es1 and es7_if_s1 ) or + ( es2_0 and es7_if_s20 ) or + ( es3_0 and es7_if_s30 ) or + ( esx and es7_if_sx ) or + ( es3_1 and es7_if_s31 ) or + ( es2_1 and es7_if_s21 ) ; + ex4_fsum(8) <= ex4_f_b(8) ; + ex4_fsum(9) <= ex4_f_b(9) ; + ex4_fsum(10) <= ex4_f_b(10) ; + ex4_fsum(11) <= ex4_f_b(11) ; + + + + ex4_fcarryin(1) <= tidn; + ex4_fcarryin(2) <= tidn; + ex4_fcarryin(3) <= + ( es1 and ec3_if_s1 ) or + ( es2_0 and ec3_if_s20 ) or + ( es3_0 and ec3_if_s30 ) or + ( esx and ec3_if_sx ) or + ( es3_1 and ec3_if_s31 ) or + ( es2_1 and ec3_if_s21 ) ; + ex4_fcarryin(4) <= + ( es1 and ec4_if_s1 ) or + ( es2_0 and ec4_if_s20 ) or + ( es3_0 and ec4_if_s30 ) or + ( esx and ec4_if_sx ) or + ( es3_1 and ec4_if_s31 ) or + ( es2_1 and ec4_if_s21 ) ; + ex4_fcarryin(5) <= + ( es1 and ec5_if_s1 ) or + ( es2_0 and ec5_if_s20 ) or + ( es3_0 and ec5_if_s30 ) or + ( esx and ec5_if_sx ) or + ( es3_1 and ec5_if_s31 ) or + ( es2_1 and ec5_if_s21 ) ; + ex4_fcarryin(6) <= + ( es1 and ec6_if_s1 ) or + ( es2_0 and ec6_if_s20 ) or + ( es3_0 and ec6_if_s30 ) or + ( esx and ec6_if_sx ) or + ( es3_1 and ec6_if_s31 ) or + ( es2_1 and ec6_if_s21 ) ; + ex4_fcarryin(7) <= tidn ; + ex4_fcarryin(8) <= ea8 ; + ex4_fcarryin(9) <= ea9 ; + ex4_fcarryin(10) <= ea10 ; + ex4_fcarryin(11) <= ea11 ; + +ex4_powf_a_addend_b <= not ex4_fsum(1 to 11); +ex4_powf_b_addend_b <= not (ex4_fcarryin(1 to 11) ); + +ex4_powfractadd11: entity work.fuq_gst_add11(fuq_gst_add11) port map( + a_b(0 to 10) => ex4_powf_a_addend_b, + b_b(0 to 10) => ex4_powf_b_addend_b, + s0(0 to 10) => ex4_pow_fract_b + ); + +ex4_pow_fract <= not ex4_pow_fract_b; + + +ex4_log_dp_bias <= ("01111110111" and (1 to 11 => not ex4_logof1_specialcase)) or + ("11111111101" and (1 to 11 => ex4_logof1_specialcase)); + +ex4_log_a_addend_b(1 to 11) <= zeros(1 to 6) & ex4_shamt(0 to 4); +ex4_log_b_addend_b(1 to 11) <= ex4_log_dp_bias; + +ex4_pow_a_addend_b(1 to 11) <= not (ex4_mantissa(1) & ex4_mantissa(1) & ex4_mantissa(1) & ex4_mantissa(1 to 8)); +ex4_pow_b_addend_b(1 to 11) <= "10000000000"; + + +ex4_exponent_a_addend_b <= (ex4_log_a_addend_b and (1 to 11 => ex4_floges )) or + (ex4_pow_a_addend_b and (1 to 11 => ex4_fexptes)) ; + +ex4_exponent_b_addend_b <= (ex4_log_b_addend_b and (1 to 11 => ex4_floges )) or + (ex4_pow_b_addend_b and (1 to 11 => ex4_fexptes)) ; + + +ex4_explogadd11: entity work.fuq_gst_add11(fuq_gst_add11) port map( + a_b(0 to 10) => ex4_exponent_a_addend_b, + b_b(0 to 10) => ex4_exponent_b_addend_b, + s0(0 to 10) => ex4_biased_exponent_result + ); + + + + + ex4_log_fract <= ex4_log_mantissa_postsh(01 to 19); + ex4_log_signbit <= ex4_negate; + + + ex4_signbit_din <= ex4_log_signbit and ex4_floges; + + + ex4_fract_din <= (((not ex4_logof1_specialcase) & ex4_log_fract(1 to 19)) and (0 to 19 => ex4_floges )) or + ((tiup & ex4_pow_fract(1 to 11) & zeros(1 to 8)) and (0 to 19 => ex4_fexptes)) ; + + ex5_gst_ctrl_lat : tri_rlmreg_p generic map (expand_type => expand_type, width=> 2, needs_sreset => 0) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(5), + mpw1_b => mpw1_b(5), + mpw2_b => mpw2_b(1), + vd => vdd, gd => gnd, + nclk => nclk, thold_b => thold_0_b, sg => sg_0, + act => ex4_act, + scout => ex5_gst_ctrl_lat_scout, + scin => ex5_gst_ctrl_lat_scin, + din(00) => ex4_floges, + din(01) => ex4_fexptes, + dout(00) => ex5_floges, + dout(01) => ex5_fexptes + ); + + + + ex5_gst_stage_lat: tri_rlmreg_p generic map (expand_type => expand_type, width => 32, needs_sreset => 0 ) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(5), + mpw1_b => mpw1_b(5), + mpw2_b => mpw2_b(1), + vd => vdd, gd => gnd, + nclk => nclk, thold_b => thold_0_b, sg => sg_0, + act => ex4_act, + scout => ex5_gst_stage_lat_scout, + scin => ex5_gst_stage_lat_scin, + din(00) => ex4_signbit_din, + din(01 to 11) => ex4_biased_exponent_result, + din(12 to 31) => ex4_fract_din, + dout(00) => ex5_signbit, + dout(01 to 11) => ex5_biased_exponent_result, + dout(12 to 31) => ex5_fract + + ); + + + + + f_gst_ex5_logexp_sign <= ex5_signbit; + f_gst_ex5_logexp_exp <= ex5_biased_exponent_result; + f_gst_ex5_logexp_fract <= ex5_fract; + f_gst_ex5_logexp_v <= ex5_floges or ex5_fexptes; + + + +ex2_gst_ctrl_lat_scin(0 to 1) <= f_gst_si & ex2_gst_ctrl_lat_scout(0); +ex3_gst_ctrl_lat_scin(0 to 1) <= ex2_gst_ctrl_lat_scout(1) & ex3_gst_ctrl_lat_scout(0); +ex4_gst_ctrl_lat_scin(0 to 3) <= ex3_gst_ctrl_lat_scout(1) & ex4_gst_ctrl_lat_scout(0 to 2); +ex5_gst_ctrl_lat_scin(0 to 1) <= ex4_gst_ctrl_lat_scout(3) & ex5_gst_ctrl_lat_scout(0); +ex2_gst_stage_lat_scin(0 to 32) <= ex5_gst_ctrl_lat_scout(1) & ex2_gst_stage_lat_scout(0 to 31); +ex3_gst_stage_lat_scin(0 to 19) <= ex2_gst_stage_lat_scout(32) & ex3_gst_stage_lat_scout(0 to 18); +ex4_gst_stage_lat_scin(0 to 23) <= ex3_gst_stage_lat_scout(19) & ex4_gst_stage_lat_scout(0 to 22); +ex5_gst_stage_lat_scin(0 to 31) <= ex4_gst_stage_lat_scout(23) & ex5_gst_stage_lat_scout(0 to 30); + + +act_si(0 to 7) <= act_so(1 to 7) & ex5_gst_stage_lat_scout(31); + +f_gst_so <= act_so(0); + + + +end fuq_gst; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_gst_add11.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_gst_add11.vhdl new file mode 100644 index 0000000..a0c9d96 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_gst_add11.vhdl @@ -0,0 +1,159 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + + +library ieee; + use ieee.std_logic_1164.all ; +library ibm; + + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; +library support; +use support.power_logic_pkg.all; +library tri; use tri.tri_latches_pkg.all; + +entity fuq_gst_add11 is + port( + a_b :in std_ulogic_vector(0 to 10); + b_b :in std_ulogic_vector(0 to 10); + s0 :out std_ulogic_vector(0 to 10) + + ); + + + + +end fuq_gst_add11; + +architecture fuq_gst_add11 of fuq_gst_add11 is + + signal p1 :std_ulogic_vector(0 to 10); + signal g1 :std_ulogic_vector(1 to 10); + signal t1 :std_ulogic_vector(1 to 9); + signal g2_b :std_ulogic_vector(1 to 10); + signal g4 :std_ulogic_vector(1 to 10); + signal g8_b :std_ulogic_vector(1 to 10); + signal c16 :std_ulogic_vector(1 to 10); + signal t2_b :std_ulogic_vector(1 to 8); + signal t4 :std_ulogic_vector(1 to 6); + signal t8_b :std_ulogic_vector(1 to 2); + + + + + + +begin + + +u_p1: p1(0 to 10) <= ( a_b(0 to 10) xor b_b(0 to 10) ); +u_g1: g1(1 to 10) <= not( a_b(1 to 10) or b_b(1 to 10) ); +u_t1: t1(1 to 9) <= not( a_b(1 to 9) and b_b(1 to 9) ); + + + u_g2_01: g2_b(1) <= not( g1(1) or ( t1(1) and g1(2) ) ); + u_g2_02: g2_b(2) <= not( g1(2) or ( t1(2) and g1(3) ) ); + u_g2_03: g2_b(3) <= not( g1(3) or ( t1(3) and g1(4) ) ); + u_g2_04: g2_b(4) <= not( g1(4) or ( t1(4) and g1(5) ) ); + u_g2_05: g2_b(5) <= not( g1(5) or ( t1(5) and g1(6) ) ); + u_g2_06: g2_b(6) <= not( g1(6) or ( t1(6) and g1(7) ) ); + u_g2_07: g2_b(7) <= not( g1(7) or ( t1(7) and g1(8) ) ); + u_g2_08: g2_b(8) <= not( g1(8) or ( t1(8) and g1(9) ) ); + u_g2_09: g2_b(9) <= not( g1(9) or ( t1(9) and g1(10) ) ); + u_g2_10: g2_b(10) <= not( g1(10) ); + + u_t2_01: t2_b(1) <= not( t1(1) and t1(2) ); + u_t2_02: t2_b(2) <= not( t1(2) and t1(3) ); + u_t2_03: t2_b(3) <= not( t1(3) and t1(4) ); + u_t2_04: t2_b(4) <= not( t1(4) and t1(5) ); + u_t2_05: t2_b(5) <= not( t1(5) and t1(6) ); + u_t2_06: t2_b(6) <= not( t1(6) and t1(7) ); + u_t2_07: t2_b(7) <= not( t1(7) and t1(8) ); + u_t2_08: t2_b(8) <= not( t1(8) and t1(9) ); + + + + u_g4_01: g4(1) <= not( g2_b(1) and ( t2_b(1) or g2_b(3) ) ); + u_g4_02: g4(2) <= not( g2_b(2) and ( t2_b(2) or g2_b(4) ) ); + u_g4_03: g4(3) <= not( g2_b(3) and ( t2_b(3) or g2_b(5) ) ); + u_g4_04: g4(4) <= not( g2_b(4) and ( t2_b(4) or g2_b(6) ) ); + u_g4_05: g4(5) <= not( g2_b(5) and ( t2_b(5) or g2_b(7) ) ); + u_g4_06: g4(6) <= not( g2_b(6) and ( t2_b(6) or g2_b(8) ) ); + u_g4_07: g4(7) <= not( g2_b(7) and ( t2_b(7) or g2_b(9) ) ); + u_g4_08: g4(8) <= not( g2_b(8) and ( t2_b(8) or g2_b(10) ) ); + u_g4_09: g4(9) <= not( g2_b(9) ); + u_g4_10: g4(10) <= not( g2_b(10) ); + + u_t4_01: t4(1) <= not( t2_b(1) or t2_b(3) ); + u_t4_02: t4(2) <= not( t2_b(2) or t2_b(4) ); + u_t4_03: t4(3) <= not( t2_b(3) or t2_b(5) ); + u_t4_04: t4(4) <= not( t2_b(4) or t2_b(6) ); + u_t4_05: t4(5) <= not( t2_b(5) or t2_b(7) ); + u_t4_06: t4(6) <= not( t2_b(6) or t2_b(8) ); + + + + u_g8_01: g8_b(1) <= not( g4(1) or ( t4(1) and g4(5) ) ); + u_g8_02: g8_b(2) <= not( g4(2) or ( t4(2) and g4(6) ) ); + u_g8_03: g8_b(3) <= not( g4(3) or ( t4(3) and g4(7) ) ); + u_g8_04: g8_b(4) <= not( g4(4) or ( t4(4) and g4(8) ) ); + u_g8_05: g8_b(5) <= not( g4(5) or ( t4(5) and g4(9) ) ); + u_g8_06: g8_b(6) <= not( g4(6) or ( t4(6) and g4(10) ) ); + u_g8_07: g8_b(7) <= not( g4(7) ); + u_g8_08: g8_b(8) <= not( g4(8) ); + u_g8_09: g8_b(9) <= not( g4(9) ); + u_g8_10: g8_b(10) <= not( g4(10) ); + + u_t8_01: t8_b(1) <= not( t4(1) and t4(5) ); + u_t8_02: t8_b(2) <= not( t4(2) and t4(6) ); + + u_c16_01: c16(1) <= not( g8_b(1) and ( t8_b(1) or g8_b(9) ) ); + u_c16_02: c16(2) <= not( g8_b(2) and ( t8_b(2) or g8_b(10) ) ); + u_c16_03: c16(3) <= not( g8_b(3) ); + u_c16_04: c16(4) <= not( g8_b(4) ); + u_c16_05: c16(5) <= not( g8_b(5) ); + u_c16_06: c16(6) <= not( g8_b(6) ); + u_c16_07: c16(7) <= not( g8_b(7) ); + u_c16_08: c16(8) <= not( g8_b(8) ); + u_c16_09: c16(9) <= not( g8_b(9) ); + u_c16_10: c16(10) <= not( g8_b(10) ); + + + + + s0(0 to 9) <= p1(0 to 9) xor c16(1 to 10); + s0(10) <= p1(10) ; + + +end fuq_gst_add11 ; + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_gst_inc19.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_gst_inc19.vhdl new file mode 100644 index 0000000..dfa8578 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_gst_inc19.vhdl @@ -0,0 +1,178 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + + +library ieee; + use ieee.std_logic_1164.all ; +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; +library support; +use support.power_logic_pkg.all; + +library tri; use tri.tri_latches_pkg.all; + + +entity fuq_gst_inc19 is + port( + a :in std_ulogic_vector(1 to 19); + + o :out std_ulogic_vector(1 to 19) + + ); + + + + +end fuq_gst_inc19; + +architecture fuq_gst_inc19 of fuq_gst_inc19 is + + signal a_sum :std_ulogic_vector(01 to 19); + signal a_cout_b :std_ulogic_vector(02 to 19); + signal g2_b, g4, g8_b, g16 :std_ulogic_vector(02 to 19); + + + +begin + + + +g2_b(19) <= not( a(19) ); +g2_b(18) <= not( a(18) and a(19) ); +g2_b(17) <= not( a(17) and a(18) ); +g2_b(16) <= not( a(16) and a(17) ); +g2_b(15) <= not( a(15) and a(16) ); +g2_b(14) <= not( a(14) and a(15) ); +g2_b(13) <= not( a(13) and a(14) ); +g2_b(12) <= not( a(12) and a(13) ); +g2_b(11) <= not( a(11) and a(12) ); +g2_b(10) <= not( a(10) and a(11) ); +g2_b( 9) <= not( a( 9) and a(10) ); +g2_b( 8) <= not( a( 8) and a( 9) ); +g2_b( 7) <= not( a( 7) and a( 8) ); +g2_b( 6) <= not( a( 6) and a( 7) ); +g2_b( 5) <= not( a( 5) and a( 6) ); +g2_b( 4) <= not( a( 4) and a( 5) ); +g2_b( 3) <= not( a( 3) and a( 4) ); +g2_b( 2) <= not( a( 2) and a( 3) ); + + +g4(19) <= not( g2_b(19) ) ; +g4(18) <= not( g2_b(18) ) ; +g4(17) <= not( g2_b(17) or g2_b(19) ) ; +g4(16) <= not( g2_b(16) or g2_b(18) ) ; +g4(15) <= not( g2_b(15) or g2_b(17) ) ; +g4(14) <= not( g2_b(14) or g2_b(16) ) ; +g4(13) <= not( g2_b(13) or g2_b(15) ) ; +g4(12) <= not( g2_b(12) or g2_b(14) ) ; +g4(11) <= not( g2_b(11) or g2_b(13) ) ; +g4(10) <= not( g2_b(10) or g2_b(12) ) ; +g4( 9) <= not( g2_b( 9) or g2_b(11) ) ; +g4( 8) <= not( g2_b( 8) or g2_b(10) ) ; +g4( 7) <= not( g2_b( 7) or g2_b( 9) ) ; +g4( 6) <= not( g2_b( 6) or g2_b( 8) ) ; +g4( 5) <= not( g2_b( 5) or g2_b( 7) ) ; +g4( 4) <= not( g2_b( 4) or g2_b( 6) ) ; +g4( 3) <= not( g2_b( 3) or g2_b( 5) ) ; +g4( 2) <= not( g2_b( 2) or g2_b( 4) ) ; + + +g8_b(19) <= not( g4(19) ) ; +g8_b(18) <= not( g4(18) ) ; +g8_b(17) <= not( g4(17) ) ; +g8_b(16) <= not( g4(16) ) ; +g8_b(15) <= not( g4(15) and g4(19) ) ; +g8_b(14) <= not( g4(14) and g4(18) ) ; +g8_b(13) <= not( g4(13) and g4(17) ) ; +g8_b(12) <= not( g4(12) and g4(16) ) ; +g8_b(11) <= not( g4(11) and g4(15) ) ; +g8_b(10) <= not( g4(10) and g4(14) ) ; +g8_b( 9) <= not( g4( 9) and g4(13) ) ; +g8_b( 8) <= not( g4( 8) and g4(12) ) ; +g8_b( 7) <= not( g4( 7) and g4(11) ) ; +g8_b( 6) <= not( g4( 6) and g4(10) ) ; +g8_b( 5) <= not( g4( 5) and g4( 9) ) ; +g8_b( 4) <= not( g4( 4) and g4( 8) ) ; +g8_b( 3) <= not( g4( 3) and g4( 7) ) ; +g8_b( 2) <= not( g4( 2) and g4( 6) ) ; + +g16(19) <= not( g8_b(19) ); +g16(18) <= not( g8_b(18) ); +g16(17) <= not( g8_b(17) ); +g16(16) <= not( g8_b(16) ); +g16(15) <= not( g8_b(15) ); +g16(14) <= not( g8_b(14) ); +g16(13) <= not( g8_b(13) ); +g16(12) <= not( g8_b(12) ); +g16(11) <= not( g8_b(11) or g8_b(19) ) ; +g16(10) <= not( g8_b(10) or g8_b(18) ) ; +g16( 9) <= not( g8_b( 9) or g8_b(17) ) ; +g16( 8) <= not( g8_b( 8) or g8_b(16) ) ; +g16( 7) <= not( g8_b( 7) or g8_b(15) ) ; +g16( 6) <= not( g8_b( 6) or g8_b(14) ) ; +g16( 5) <= not( g8_b( 5) or g8_b(13) ) ; +g16( 4) <= not( g8_b( 4) or g8_b(12) ) ; +g16( 3) <= not( g8_b( 3) or g8_b(11) ) ; +g16( 2) <= not( g8_b( 2) or g8_b(10) ) ; + +a_cout_b(19) <= not( g16(19) ); +a_cout_b(18) <= not( g16(18) ); +a_cout_b(17) <= not( g16(17) ); +a_cout_b(16) <= not( g16(16) ); +a_cout_b(15) <= not( g16(15) ); +a_cout_b(14) <= not( g16(14) ); +a_cout_b(13) <= not( g16(13) ); +a_cout_b(12) <= not( g16(12) ); +a_cout_b(11) <= not( g16(11) ); +a_cout_b(10) <= not( g16(10) ); +a_cout_b( 9) <= not( g16( 9) ); +a_cout_b( 8) <= not( g16( 8) ); +a_cout_b( 7) <= not( g16( 7) ); +a_cout_b( 6) <= not( g16( 6) ); +a_cout_b( 5) <= not( g16( 5) ); +a_cout_b( 4) <= not( g16( 4) ); +a_cout_b( 3) <= not( g16( 3) and g16(19) ); +a_cout_b( 2) <= not( g16( 2) and g16(18) ); + + + +a_sum(1 to 18) <= a(1 to 18); +a_sum(19) <= not a(19); + + +o(01 to 18) <= not( a_sum(01 to 18) xor a_cout_b(02 to 19) ); +o(19) <= a_sum(19); + + +end fuq_gst_inc19; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_gst_loa.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_gst_loa.vhdl new file mode 100644 index 0000000..c0928ba --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_gst_loa.vhdl @@ -0,0 +1,153 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + + +library ieee; + use ieee.std_logic_1164.all ; +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; +library support; +use support.power_logic_pkg.all; + +library tri; use tri.tri_latches_pkg.all; + + +entity fuq_gst_loa is + port( + a :in std_ulogic_vector(1 to 19); + + shamt :out std_ulogic_vector(0 to 4) + + ); + + + +end fuq_gst_loa; + +architecture fuq_gst_loa of fuq_gst_loa is + + signal unused :std_ulogic; + +begin + + unused <= a(19) ; + + + + + + +shamt(0) <= (not a(01) and not a(02) and not a(03) and not a(04) and not a(05) and not a(06) and not a(07) + and not a(08) and not a(09) and not a(10) and not a(11) and not a(12) and not a(13) + and not a(14) and not a(15) and a(19)) or + (not a(01) and not a(02) and not a(03) and not a(04) and not a(05) and not a(06) and not a(07) + and not a(08) and not a(09) and not a(10) and not a(11) and not a(12) and not a(13) and not a(14) + and not a(15) and a(18)) or + (not a(01) and not a(02) and not a(03) and not a(04) and not a(05) and not a(06) and not a(07) + and not a(08) and not a(09) and not a(10) and not a(11) and not a(12) and not a(13) and not a(14) + and not a(15) and a(17)) or + (not a(01) and not a(02) and not a(03) and not a(04) and not a(05) and not a(06) and not a(07) + and not a(08) and not a(09) and not a(10) and not a(11) and not a(12) and not a(13) and not a(14) + and not a(15) and a(16)); + +shamt(1) <= (not a(01) and not a(02) and not a(03) and not a(04) and not a(05) and not a(06) and not a(07) + and a(15)) or + (not a(01) and not a(02) and not a(03) and not a(04) and not a(05) and not a(06) and not a(07) + and a(14)) or + (not a(01) and not a(02) and not a(03) and not a(04) and not a(05) and not a(06) and not a(07) + and a(13)) or + (not a(01) and not a(02) and not a(03) and not a(04) and not a(05) and not a(06) and not a(07) + and a(12)) or + (not a(01) and not a(02) and not a(03) and not a(04) and not a(05) and not a(06) and not a(07) + and a(11)) or + (not a(01) and not a(02) and not a(03) and not a(04) and not a(05) and not a(06) and not a(07) + and a(10)) or + (not a(01) and not a(02) and not a(03) and not a(04) and not a(05) and not a(06) and not a(07) + and a(09)) or + (not a(01) and not a(02) and not a(03) and not a(04) and not a(05) and not a(06) and not a(07) + and a(08)); + +shamt(2) <= (not a(01) and not a(02) and not a(03) and not a(08) and not a(09) and not a(10) and not a(11) + and a(15)) or + (not a(01) and not a(02) and not a(03) and not a(08) and not a(09) and not a(10) and not a(11) + and a(14)) or + (not a(01) and not a(02) and not a(03) and not a(08) and not a(09) and not a(10) and not a(11) + and a(13)) or + (not a(01) and not a(02) and not a(03) and not a(08) and not a(09) and not a(10) and not a(11) + and a(12)) or + (not a(01) and not a(02) and not a(03) and a(07)) or + (not a(01) and not a(02) and not a(03) and a(06)) or + (not a(01) and not a(02) and not a(03) and a(05)) or + (not a(01) and not a(02) and not a(03) and a(04)); + +shamt(3) <= (not a(01) and not a(04) and not a(05) and not a(08) and not a(09) and not a(12) and not a(13) + and not a(16) and not a(17) and a(19)) or + (not a(01) and not a(04) and not a(05) and not a(08) and not a(09) and not a(12) and not a(13) + and not a(16) and not a(17) and a(18)) or + (not a(01) and not a(04) and not a(05) and not a(08) and not a(09) and not a(12) and not a(13) + and a(15)) or + (not a(01) and not a(04) and not a(05) and not a(08) and not a(09) and not a(12) and not a(13) + and a(14)) or + (not a(01) and not a(04) and not a(05) and not a(08) and not a(09) and a(11)) or + (not a(01) and not a(04) and not a(05) and not a(08) and not a(09) and a(10)) or + (not a(01) and not a(04) and not a(05) and a(07)) or + (not a(01) and not a(04) and not a(05) and a(06)) or + (not a(01) and a(03)) or + (not a(01) and a(02)); + +shamt(4) <= (not a(02) and not a(04) and not a(06) and not a(08) and not a(10) and not a(12) and not a(14) + and not a(16) and not a(18) and a(19)) or + (not a(02) and not a(04) and not a(06) and not a(08) and not a(10) and not a(12) and not a(14) + and not a(16) and a(17)) or + (not a(02) and not a(04) and not a(06) and not a(08) and not a(10) and not a(12) and not a(14) + and a(15)) or + (not a(02) and not a(04) and not a(06) and not a(08) and not a(10) and not a(12) and a(13)) or + (not a(02) and not a(04) and not a(06) and not a(08) and not a(10) and a(11)) or + (not a(02) and not a(04) and not a(06) and not a(08) and a(09)) or + (not a(02) and not a(04) and not a(06) and a(07)) or + (not a(02) and not a(04) and a(05)) or + (not a(02) and a(03)) or + ( a(01)); + + + + + + + + + + + +end fuq_gst_loa; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_hc16pp.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_hc16pp.vhdl new file mode 100644 index 0000000..c2eadea --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_hc16pp.vhdl @@ -0,0 +1,482 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; use ieee.std_logic_1164.all ; + +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + +ENTITY fuq_hc16pp IS PORT( + x : IN std_ulogic_vector(0 to 15); + y : IN std_ulogic_vector(0 to 15); + ci0 : IN std_ulogic; + ci0_b : IN std_ulogic; + ci1 : IN std_ulogic; + ci1_b : IN std_ulogic; + s0 : OUT std_ulogic_vector(0 to 15); + s1 : OUT std_ulogic_vector(0 to 15); + g16 : out std_ulogic; + t16 : out std_ulogic +); + + + +END fuq_hc16pp; + +ARCHITECTURE fuq_hc16pp OF fuq_hc16pp IS + + signal g01_b, t01_b, p01_b, p01 :std_ulogic_vector(0 to 15); + signal g01od, t01od :std_ulogic_vector(0 to 7); + signal g02ev , t02ev :std_ulogic_vector(0 to 7); + signal g02ev_b , t02ev_b :std_ulogic_vector(1 to 7); + signal g04ev, t04ev :std_ulogic_vector(1 to 7); + signal g08ev_b, t08ev_b :std_ulogic_vector(1 to 7); + signal g16ev, t16ev :std_ulogic_vector(1 to 7); + signal c0_b , c1_b :std_ulogic_vector(1 to 15); + signal s0_raw, s1_raw :std_ulogic_vector(0 to 15); + signal s0_x_b, s0_y_b :std_ulogic_vector(0 to 15); + signal s1_x_b, s1_y_b :std_ulogic_vector(0 to 15); + + signal glb_g04_e01_b, glb_g04_e23_b, glb_g04_e45_b, glb_g04_e67_b :std_ulogic; + signal glb_t04_e01_b, glb_t04_e23_b, glb_t04_e45_b, glb_t04_e67_b :std_ulogic; + signal glb_g08_e03 , glb_g08_e47 , glb_t08_e03 , glb_t08_e47 :std_ulogic; + signal glb_g16_e07_b, glb_t16_e07_b :std_ulogic; + + + + + + + + + + + +BEGIN + + + hc00_g01: g01_b( 0) <= not( x( 0) and y( 0) ); + hc01_g01: g01_b( 1) <= not( x( 1) and y( 1) ); + hc02_g01: g01_b( 2) <= not( x( 2) and y( 2) ); + hc03_g01: g01_b( 3) <= not( x( 3) and y( 3) ); + hc04_g01: g01_b( 4) <= not( x( 4) and y( 4) ); + hc05_g01: g01_b( 5) <= not( x( 5) and y( 5) ); + hc06_g01: g01_b( 6) <= not( x( 6) and y( 6) ); + hc07_g01: g01_b( 7) <= not( x( 7) and y( 7) ); + hc08_g01: g01_b( 8) <= not( x( 8) and y( 8) ); + hc09_g01: g01_b( 9) <= not( x( 9) and y( 9) ); + hc10_g01: g01_b(10) <= not( x(10) and y(10) ); + hc11_g01: g01_b(11) <= not( x(11) and y(11) ); + hc12_g01: g01_b(12) <= not( x(12) and y(12) ); + hc13_g01: g01_b(13) <= not( x(13) and y(13) ); + hc14_g01: g01_b(14) <= not( x(14) and y(14) ); + hc15_g01: g01_b(15) <= not( x(15) and y(15) ); + + hc00_t01: t01_b( 0) <= not( x( 0) or y( 0) ); + hc01_t01: t01_b( 1) <= not( x( 1) or y( 1) ); + hc02_t01: t01_b( 2) <= not( x( 2) or y( 2) ); + hc03_t01: t01_b( 3) <= not( x( 3) or y( 3) ); + hc04_t01: t01_b( 4) <= not( x( 4) or y( 4) ); + hc05_t01: t01_b( 5) <= not( x( 5) or y( 5) ); + hc06_t01: t01_b( 6) <= not( x( 6) or y( 6) ); + hc07_t01: t01_b( 7) <= not( x( 7) or y( 7) ); + hc08_t01: t01_b( 8) <= not( x( 8) or y( 8) ); + hc09_t01: t01_b( 9) <= not( x( 9) or y( 9) ); + hc10_t01: t01_b(10) <= not( x(10) or y(10) ); + hc11_t01: t01_b(11) <= not( x(11) or y(11) ); + hc12_t01: t01_b(12) <= not( x(12) or y(12) ); + hc13_t01: t01_b(13) <= not( x(13) or y(13) ); + hc14_t01: t01_b(14) <= not( x(14) or y(14) ); + hc15_t01: t01_b(15) <= not( x(15) or y(15) ); + + hc00_p01: p01( 0) <= ( x( 0) xor y( 0) ); + hc01_p01: p01( 1) <= ( x( 1) xor y( 1) ); + hc02_p01: p01( 2) <= ( x( 2) xor y( 2) ); + hc03_p01: p01( 3) <= ( x( 3) xor y( 3) ); + hc04_p01: p01( 4) <= ( x( 4) xor y( 4) ); + hc05_p01: p01( 5) <= ( x( 5) xor y( 5) ); + hc06_p01: p01( 6) <= ( x( 6) xor y( 6) ); + hc07_p01: p01( 7) <= ( x( 7) xor y( 7) ); + hc08_p01: p01( 8) <= ( x( 8) xor y( 8) ); + hc09_p01: p01( 9) <= ( x( 9) xor y( 9) ); + hc10_p01: p01(10) <= ( x(10) xor y(10) ); + hc11_p01: p01(11) <= ( x(11) xor y(11) ); + hc12_p01: p01(12) <= ( x(12) xor y(12) ); + hc13_p01: p01(13) <= ( x(13) xor y(13) ); + hc14_p01: p01(14) <= ( x(14) xor y(14) ); + hc15_p01: p01(15) <= ( x(15) xor y(15) ); + + hc00_p01b: p01_b( 0) <= not( p01( 0) ); + hc01_p01b: p01_b( 1) <= not( p01( 1) ); + hc02_p01b: p01_b( 2) <= not( p01( 2) ); + hc03_p01b: p01_b( 3) <= not( p01( 3) ); + hc04_p01b: p01_b( 4) <= not( p01( 4) ); + hc05_p01b: p01_b( 5) <= not( p01( 5) ); + hc06_p01b: p01_b( 6) <= not( p01( 6) ); + hc07_p01b: p01_b( 7) <= not( p01( 7) ); + hc08_p01b: p01_b( 8) <= not( p01( 8) ); + hc09_p01b: p01_b( 9) <= not( p01( 9) ); + hc10_p01b: p01_b(10) <= not( p01(10) ); + hc11_p01b: p01_b(11) <= not( p01(11) ); + hc12_p01b: p01_b(12) <= not( p01(12) ); + hc13_p01b: p01_b(13) <= not( p01(13) ); + hc14_p01b: p01_b(14) <= not( p01(14) ); + hc15_p01b: p01_b(15) <= not( p01(15) ); + + + hc01_g01o: g01od(0) <= not g01_b( 1); + hc03_g01o: g01od(1) <= not g01_b( 3); + hc05_g01o: g01od(2) <= not g01_b( 5); + hc07_g01o: g01od(3) <= not g01_b( 7); + hc09_g01o: g01od(4) <= not g01_b( 9); + hc11_g01o: g01od(5) <= not g01_b(11); + hc13_g01o: g01od(6) <= not g01_b(13); + hc15_g01o: g01od(7) <= not g01_b(15); + + hc01_t01o: t01od(0) <= not t01_b( 1); + hc03_t01o: t01od(1) <= not t01_b( 3); + hc05_t01o: t01od(2) <= not t01_b( 5); + hc07_t01o: t01od(3) <= not t01_b( 7); + hc09_t01o: t01od(4) <= not t01_b( 9); + hc11_t01o: t01od(5) <= not t01_b(11); + hc13_t01o: t01od(6) <= not t01_b(13); + hc15_t01o: t01od(7) <= not t01_b(15); + + + + + + hc14_g02: g02ev(7) <= not( ( t01_b(14) or g01_b(15) ) and g01_b(14) ); + hc12_g02: g02ev(6) <= not( ( t01_b(12) or g01_b(13) ) and g01_b(12) ); + hc10_g02: g02ev(5) <= not( ( t01_b(10) or g01_b(11) ) and g01_b(10) ); + hc08_g02: g02ev(4) <= not( ( t01_b( 8) or g01_b( 9) ) and g01_b( 8) ); + hc06_g02: g02ev(3) <= not( ( t01_b( 6) or g01_b( 7) ) and g01_b( 6) ); + hc04_g02: g02ev(2) <= not( ( t01_b( 4) or g01_b( 5) ) and g01_b( 4) ); + hc02_g02: g02ev(1) <= not( ( t01_b( 2) or g01_b( 3) ) and g01_b( 2) ); + hc00_g02: g02ev(0) <= not( ( t01_b( 0) or g01_b( 1) ) and g01_b( 0) ); + + hc14_t02: t02ev(7) <= not( ( t01_b(14) or t01_b(15) ) and g01_b(14) ); + hc12_t02: t02ev(6) <= not( t01_b(12) or t01_b(13) ); + hc10_t02: t02ev(5) <= not( t01_b(10) or t01_b(11) ); + hc08_t02: t02ev(4) <= not( t01_b( 8) or t01_b( 9) ); + hc06_t02: t02ev(3) <= not( t01_b( 6) or t01_b( 7) ); + hc04_t02: t02ev(2) <= not( t01_b( 4) or t01_b( 5) ); + hc02_t02: t02ev(1) <= not( t01_b( 2) or t01_b( 3) ); + hc00_t02: t02ev(0) <= not( t01_b( 0) or t01_b( 1) ); + + hc14_g02b: g02ev_b(7) <= not( g02ev(7) ); + hc12_g02b: g02ev_b(6) <= not( g02ev(6) ); + hc10_g02b: g02ev_b(5) <= not( g02ev(5) ); + hc08_g02b: g02ev_b(4) <= not( g02ev(4) ); + hc06_g02b: g02ev_b(3) <= not( g02ev(3) ); + hc04_g02b: g02ev_b(2) <= not( g02ev(2) ); + hc02_g02b: g02ev_b(1) <= not( g02ev(1) ); + + hc14_t02b: t02ev_b(7) <= not( t02ev(7) ); + hc12_t02b: t02ev_b(6) <= not( t02ev(6) ); + hc10_t02b: t02ev_b(5) <= not( t02ev(5) ); + hc08_t02b: t02ev_b(4) <= not( t02ev(4) ); + hc06_t02b: t02ev_b(3) <= not( t02ev(3) ); + hc04_t02b: t02ev_b(2) <= not( t02ev(2) ); + hc02_t02b: t02ev_b(1) <= not( t02ev(1) ); + + + u_glb_g04_e01: glb_g04_e01_b <= not( g02ev(0) or ( t02ev(0) and g02ev(1) ) ); + u_glb_g04_e23: glb_g04_e23_b <= not( g02ev(2) or ( t02ev(2) and g02ev(3) ) ); + u_glb_g04_e45: glb_g04_e45_b <= not( g02ev(4) or ( t02ev(4) and g02ev(5) ) ); + u_glb_g04_e67: glb_g04_e67_b <= not( g02ev(6) or ( t02ev(6) and g02ev(7) ) ); + u_glb_t04_e01: glb_t04_e01_b <= not( t02ev(0) and t02ev(1) ); + u_glb_t04_e23: glb_t04_e23_b <= not( t02ev(2) and t02ev(3) ); + u_glb_t04_e45: glb_t04_e45_b <= not( t02ev(4) and t02ev(5) ); + u_glb_t04_e67: glb_t04_e67_b <= not( g02ev(6) or ( t02ev(6) and t02ev(7) ) ); + + u_glb_g08_e03: glb_g08_e03 <= not( glb_g04_e01_b and ( glb_t04_e01_b or glb_g04_e23_b ) ); + u_glb_g08_e47: glb_g08_e47 <= not( glb_g04_e45_b and ( glb_t04_e45_b or glb_g04_e67_b ) ); + u_glb_t08_e03: glb_t08_e03 <= not( glb_t04_e01_b or glb_t04_e23_b ); + u_glb_t08_e47: glb_t08_e47 <= not( glb_g04_e45_b and ( glb_t04_e45_b or glb_t04_e67_b ) ); + + u_glb_g16_e07: glb_g16_e07_b <= not( glb_g08_e03 or ( glb_t08_e03 and glb_g08_e47 ) ); + u_glb_t16_e07: glb_t16_e07_b <= not( glb_g08_e03 or ( glb_t08_e03 and glb_t08_e47 ) ); + + u_g16o: g16 <= not( glb_g16_e07_b ); + u_t16o: t16 <= not( glb_t16_e07_b ); + + + + hc14_g04: g04ev(7) <= not( g02ev_b(7) ); + hc12_g04: g04ev(6) <= not( g02ev_b(6) and (t02ev_b(6) or g02ev_b(7)) ); + hc10_g04: g04ev(5) <= not( g02ev_b(5) and (t02ev_b(5) or g02ev_b(6)) ); + hc08_g04: g04ev(4) <= not( g02ev_b(4) and (t02ev_b(4) or g02ev_b(5)) ); + hc06_g04: g04ev(3) <= not( g02ev_b(3) and (t02ev_b(3) or g02ev_b(4)) ); + hc04_g04: g04ev(2) <= not( g02ev_b(2) and (t02ev_b(2) or g02ev_b(3)) ); + hc02_g04: g04ev(1) <= not( g02ev_b(1) and (t02ev_b(1) or g02ev_b(2)) ); + + + hc14_t04: t04ev(7) <= not( t02ev_b(7) ); + hc12_t04: t04ev(6) <= not( g02ev_b(6) and (t02ev_b(6) or t02ev_b(7)) ); + hc10_t04: t04ev(5) <= not( t02ev_b(5) or t02ev_b(6) ); + hc08_t04: t04ev(4) <= not( t02ev_b(4) or t02ev_b(5) ); + hc06_t04: t04ev(3) <= not( t02ev_b(3) or t02ev_b(4) ); + hc04_t04: t04ev(2) <= not( t02ev_b(2) or t02ev_b(3) ); + hc02_t04: t04ev(1) <= not( t02ev_b(1) or t02ev_b(2) ); + + + + hc14_g08: g08ev_b(7) <= not( g04ev(7) ); + hc12_g08: g08ev_b(6) <= not( g04ev(6) ); + hc10_g08: g08ev_b(5) <= not( g04ev(5) or (t04ev(5) and g04ev(7)) ); + hc08_g08: g08ev_b(4) <= not( g04ev(4) or (t04ev(4) and g04ev(6)) ); + hc06_g08: g08ev_b(3) <= not( g04ev(3) or (t04ev(3) and g04ev(5)) ); + hc04_g08: g08ev_b(2) <= not( g04ev(2) or (t04ev(2) and g04ev(4)) ); + hc02_g08: g08ev_b(1) <= not( g04ev(1) or (t04ev(1) and g04ev(3)) ); + + + hc14_t08: t08ev_b(7) <= not( t04ev(7) ); + hc12_t08: t08ev_b(6) <= not( t04ev(6) ); + hc10_t08: t08ev_b(5) <= not( g04ev(5) or (t04ev(5) and t04ev(7)) ); + hc08_t08: t08ev_b(4) <= not( g04ev(4) or (t04ev(4) and t04ev(6)) ); + hc06_t08: t08ev_b(3) <= not( t04ev(3) and t04ev(5) ); + hc04_t08: t08ev_b(2) <= not( t04ev(2) and t04ev(4) ); + hc02_t08: t08ev_b(1) <= not( t04ev(1) and t04ev(3) ); + + + + hc14_g16: g16ev(7) <= not( g08ev_b(7) ); + hc12_g16: g16ev(6) <= not( g08ev_b(6) ); + hc10_g16: g16ev(5) <= not( g08ev_b(5) ); + hc08_g16: g16ev(4) <= not( g08ev_b(4) ); + hc06_g16: g16ev(3) <= not( g08ev_b(3) and (t08ev_b(3) or g08ev_b(7)) ); + hc04_g16: g16ev(2) <= not( g08ev_b(2) and (t08ev_b(2) or g08ev_b(6)) ); + hc02_g16: g16ev(1) <= not( g08ev_b(1) and (t08ev_b(1) or g08ev_b(5)) ); + + hc14_t16: t16ev(7) <= not( t08ev_b(7) ); + hc12_t16: t16ev(6) <= not( t08ev_b(6) ); + hc10_t16: t16ev(5) <= not( t08ev_b(5) ); + hc08_t16: t16ev(4) <= not( t08ev_b(4) ); + hc06_t16: t16ev(3) <= not( g08ev_b(3) and (t08ev_b(3) or t08ev_b(7)) ); + hc04_t16: t16ev(2) <= not( g08ev_b(2) and (t08ev_b(2) or t08ev_b(6)) ); + hc02_t16: t16ev(1) <= not( g08ev_b(1) and (t08ev_b(1) or t08ev_b(5)) ); + + + + hc14_c0: c0_b(14) <= not( g16ev(7) ); + hc12_c0: c0_b(12) <= not( g16ev(6) ); + hc10_c0: c0_b(10) <= not( g16ev(5) ); + hc08_c0: c0_b( 8) <= not( g16ev(4) ); + hc06_c0: c0_b( 6) <= not( g16ev(3) ); + hc04_c0: c0_b( 4) <= not( g16ev(2) ); + hc02_c0: c0_b( 2) <= not( g16ev(1) ); + + hc14_c1: c1_b(14) <= not( t16ev(7) ); + hc12_c1: c1_b(12) <= not( t16ev(6) ); + hc10_c1: c1_b(10) <= not( t16ev(5) ); + hc08_c1: c1_b( 8) <= not( t16ev(4) ); + hc06_c1: c1_b( 6) <= not( t16ev(3) ); + hc04_c1: c1_b( 4) <= not( t16ev(2) ); + hc02_c1: c1_b( 2) <= not( t16ev(1) ); + + hc15_c0: c0_b(15) <= not( g01od(7)); + hc13_c0: c0_b(13) <= not( (t01od(6) and g16ev(7)) or g01od(6)); + hc11_c0: c0_b(11) <= not( (t01od(5) and g16ev(6)) or g01od(5)); + hc09_c0: c0_b( 9) <= not( (t01od(4) and g16ev(5)) or g01od(4)); + hc07_c0: c0_b( 7) <= not( (t01od(3) and g16ev(4)) or g01od(3)); + hc05_c0: c0_b( 5) <= not( (t01od(2) and g16ev(3)) or g01od(2)); + hc03_c0: c0_b( 3) <= not( (t01od(1) and g16ev(2)) or g01od(1)); + hc01_c0: c0_b( 1) <= not( (t01od(0) and g16ev(1)) or g01od(0)); + + hc15_c1: c1_b(15) <= not( t01od(7) ); + hc13_c1: c1_b(13) <= not( (t01od(6) and t16ev(7)) or g01od(6) ); + hc11_c1: c1_b(11) <= not( (t01od(5) and t16ev(6)) or g01od(5) ); + hc09_c1: c1_b( 9) <= not( (t01od(4) and t16ev(5)) or g01od(4) ); + hc07_c1: c1_b( 7) <= not( (t01od(3) and t16ev(4)) or g01od(3) ); + hc05_c1: c1_b( 5) <= not( (t01od(2) and t16ev(3)) or g01od(2) ); + hc03_c1: c1_b( 3) <= not( (t01od(1) and t16ev(2)) or g01od(1) ); + hc01_c1: c1_b( 1) <= not( (t01od(0) and t16ev(1)) or g01od(0) ); + + + hc00_s0r: s0_raw( 0) <= ( p01_b( 0) xor c0_b( 1) ); + hc01_s0r: s0_raw( 1) <= ( p01_b( 1) xor c0_b( 2) ); + hc02_s0r: s0_raw( 2) <= ( p01_b( 2) xor c0_b( 3) ); + hc03_s0r: s0_raw( 3) <= ( p01_b( 3) xor c0_b( 4) ); + hc04_s0r: s0_raw( 4) <= ( p01_b( 4) xor c0_b( 5) ); + hc05_s0r: s0_raw( 5) <= ( p01_b( 5) xor c0_b( 6) ); + hc06_s0r: s0_raw( 6) <= ( p01_b( 6) xor c0_b( 7) ); + hc07_s0r: s0_raw( 7) <= ( p01_b( 7) xor c0_b( 8) ); + hc08_s0r: s0_raw( 8) <= ( p01_b( 8) xor c0_b( 9) ); + hc09_s0r: s0_raw( 9) <= ( p01_b( 9) xor c0_b(10) ); + hc10_s0r: s0_raw(10) <= ( p01_b(10) xor c0_b(11) ); + hc11_s0r: s0_raw(11) <= ( p01_b(11) xor c0_b(12) ); + hc12_s0r: s0_raw(12) <= ( p01_b(12) xor c0_b(13) ); + hc13_s0r: s0_raw(13) <= ( p01_b(13) xor c0_b(14) ); + hc14_s0r: s0_raw(14) <= ( p01_b(14) xor c0_b(15) ); + hc15_s0r: s0_raw(15) <= not p01_b(15); + + hc00_s1r: s1_raw( 0) <= ( p01_b( 0) xor c1_b( 1) ); + hc01_s1r: s1_raw( 1) <= ( p01_b( 1) xor c1_b( 2) ); + hc02_s1r: s1_raw( 2) <= ( p01_b( 2) xor c1_b( 3) ); + hc03_s1r: s1_raw( 3) <= ( p01_b( 3) xor c1_b( 4) ); + hc04_s1r: s1_raw( 4) <= ( p01_b( 4) xor c1_b( 5) ); + hc05_s1r: s1_raw( 5) <= ( p01_b( 5) xor c1_b( 6) ); + hc06_s1r: s1_raw( 6) <= ( p01_b( 6) xor c1_b( 7) ); + hc07_s1r: s1_raw( 7) <= ( p01_b( 7) xor c1_b( 8) ); + hc08_s1r: s1_raw( 8) <= ( p01_b( 8) xor c1_b( 9) ); + hc09_s1r: s1_raw( 9) <= ( p01_b( 9) xor c1_b(10) ); + hc10_s1r: s1_raw(10) <= ( p01_b(10) xor c1_b(11) ); + hc11_s1r: s1_raw(11) <= ( p01_b(11) xor c1_b(12) ); + hc12_s1r: s1_raw(12) <= ( p01_b(12) xor c1_b(13) ); + hc13_s1r: s1_raw(13) <= ( p01_b(13) xor c1_b(14) ); + hc14_s1r: s1_raw(14) <= ( p01_b(14) xor c1_b(15) ); + hc15_s1r: s1_raw(15) <= not s0_raw(15); + + + + + hc00_s0x: s0_x_b( 0) <= not( s0_raw( 0) and ci0_b ); + hc00_s0y: s0_y_b( 0) <= not( s1_raw( 0) and ci0 ); + hc00_s1x: s1_x_b( 0) <= not( s0_raw( 0) and ci1_b ); + hc00_s1y: s1_y_b( 0) <= not( s1_raw( 0) and ci1 ); + hc00_s0: s0 ( 0) <= not( s0_x_b( 0) and s0_y_b( 0) ); + hc00_s1: s1 ( 0) <= not( s1_x_b( 0) and s1_y_b( 0) ); + + hc01_s0x: s0_x_b( 1) <= not( s0_raw( 1) and ci0_b ); + hc01_s0y: s0_y_b( 1) <= not( s1_raw( 1) and ci0 ); + hc01_s1x: s1_x_b( 1) <= not( s0_raw( 1) and ci1_b ); + hc01_s1y: s1_y_b( 1) <= not( s1_raw( 1) and ci1 ); + hc01_s0: s0 ( 1) <= not( s0_x_b( 1) and s0_y_b( 1) ); + hc01_s1: s1 ( 1) <= not( s1_x_b( 1) and s1_y_b( 1) ); + + hc02_s0x: s0_x_b( 2) <= not( s0_raw( 2) and ci0_b ); + hc02_s0y: s0_y_b( 2) <= not( s1_raw( 2) and ci0 ); + hc02_s1x: s1_x_b( 2) <= not( s0_raw( 2) and ci1_b ); + hc02_s1y: s1_y_b( 2) <= not( s1_raw( 2) and ci1 ); + hc02_s0: s0 ( 2) <= not( s0_x_b( 2) and s0_y_b( 2) ); + hc02_s1: s1 ( 2) <= not( s1_x_b( 2) and s1_y_b( 2) ); + + hc03_s0x: s0_x_b( 3) <= not( s0_raw( 3) and ci0_b ); + hc03_s0y: s0_y_b( 3) <= not( s1_raw( 3) and ci0 ); + hc03_s1x: s1_x_b( 3) <= not( s0_raw( 3) and ci1_b ); + hc03_s1y: s1_y_b( 3) <= not( s1_raw( 3) and ci1 ); + hc03_s0: s0 ( 3) <= not( s0_x_b( 3) and s0_y_b( 3) ); + hc03_s1: s1 ( 3) <= not( s1_x_b( 3) and s1_y_b( 3) ); + + hc04_s0x: s0_x_b( 4) <= not( s0_raw( 4) and ci0_b ); + hc04_s0y: s0_y_b( 4) <= not( s1_raw( 4) and ci0 ); + hc04_s1x: s1_x_b( 4) <= not( s0_raw( 4) and ci1_b ); + hc04_s1y: s1_y_b( 4) <= not( s1_raw( 4) and ci1 ); + hc04_s0: s0 ( 4) <= not( s0_x_b( 4) and s0_y_b( 4) ); + hc04_s1: s1 ( 4) <= not( s1_x_b( 4) and s1_y_b( 4) ); + + hc05_s0x: s0_x_b( 5) <= not( s0_raw( 5) and ci0_b ); + hc05_s0y: s0_y_b( 5) <= not( s1_raw( 5) and ci0 ); + hc05_s1x: s1_x_b( 5) <= not( s0_raw( 5) and ci1_b ); + hc05_s1y: s1_y_b( 5) <= not( s1_raw( 5) and ci1 ); + hc05_s0: s0 ( 5) <= not( s0_x_b( 5) and s0_y_b( 5) ); + hc05_s1: s1 ( 5) <= not( s1_x_b( 5) and s1_y_b( 5) ); + + hc06_s0x: s0_x_b( 6) <= not( s0_raw( 6) and ci0_b ); + hc06_s0y: s0_y_b( 6) <= not( s1_raw( 6) and ci0 ); + hc06_s1x: s1_x_b( 6) <= not( s0_raw( 6) and ci1_b ); + hc06_s1y: s1_y_b( 6) <= not( s1_raw( 6) and ci1 ); + hc06_s0: s0 ( 6) <= not( s0_x_b( 6) and s0_y_b( 6) ); + hc06_s1: s1 ( 6) <= not( s1_x_b( 6) and s1_y_b( 6) ); + + hc07_s0x: s0_x_b( 7) <= not( s0_raw( 7) and ci0_b ); + hc07_s0y: s0_y_b( 7) <= not( s1_raw( 7) and ci0 ); + hc07_s1x: s1_x_b( 7) <= not( s0_raw( 7) and ci1_b ); + hc07_s1y: s1_y_b( 7) <= not( s1_raw( 7) and ci1 ); + hc07_s0: s0 ( 7) <= not( s0_x_b( 7) and s0_y_b( 7) ); + hc07_s1: s1 ( 7) <= not( s1_x_b( 7) and s1_y_b( 7) ); + + hc08_s0x: s0_x_b( 8) <= not( s0_raw( 8) and ci0_b ); + hc08_s0y: s0_y_b( 8) <= not( s1_raw( 8) and ci0 ); + hc08_s1x: s1_x_b( 8) <= not( s0_raw( 8) and ci1_b ); + hc08_s1y: s1_y_b( 8) <= not( s1_raw( 8) and ci1 ); + hc08_s0: s0 ( 8) <= not( s0_x_b( 8) and s0_y_b( 8) ); + hc08_s1: s1 ( 8) <= not( s1_x_b( 8) and s1_y_b( 8) ); + + hc09_s0x: s0_x_b( 9) <= not( s0_raw( 9) and ci0_b ); + hc09_s0y: s0_y_b( 9) <= not( s1_raw( 9) and ci0 ); + hc09_s1x: s1_x_b( 9) <= not( s0_raw( 9) and ci1_b ); + hc09_s1y: s1_y_b( 9) <= not( s1_raw( 9) and ci1 ); + hc09_s0: s0 ( 9) <= not( s0_x_b( 9) and s0_y_b( 9) ); + hc09_s1: s1 ( 9) <= not( s1_x_b( 9) and s1_y_b( 9) ); + + hc10_s0x: s0_x_b(10) <= not( s0_raw(10) and ci0_b ); + hc10_s0y: s0_y_b(10) <= not( s1_raw(10) and ci0 ); + hc10_s1x: s1_x_b(10) <= not( s0_raw(10) and ci1_b ); + hc10_s1y: s1_y_b(10) <= not( s1_raw(10) and ci1 ); + hc10_s0: s0 (10) <= not( s0_x_b(10) and s0_y_b(10) ); + hc10_s1: s1 (10) <= not( s1_x_b(10) and s1_y_b(10) ); + + hc11_s0x: s0_x_b(11) <= not( s0_raw(11) and ci0_b ); + hc11_s0y: s0_y_b(11) <= not( s1_raw(11) and ci0 ); + hc11_s1x: s1_x_b(11) <= not( s0_raw(11) and ci1_b ); + hc11_s1y: s1_y_b(11) <= not( s1_raw(11) and ci1 ); + hc11_s0: s0 (11) <= not( s0_x_b(11) and s0_y_b(11) ); + hc11_s1: s1 (11) <= not( s1_x_b(11) and s1_y_b(11) ); + + hc12_s0x: s0_x_b(12) <= not( s0_raw(12) and ci0_b ); + hc12_s0y: s0_y_b(12) <= not( s1_raw(12) and ci0 ); + hc12_s1x: s1_x_b(12) <= not( s0_raw(12) and ci1_b ); + hc12_s1y: s1_y_b(12) <= not( s1_raw(12) and ci1 ); + hc12_s0: s0 (12) <= not( s0_x_b(12) and s0_y_b(12) ); + hc12_s1: s1 (12) <= not( s1_x_b(12) and s1_y_b(12) ); + + hc13_s0x: s0_x_b(13) <= not( s0_raw(13) and ci0_b ); + hc13_s0y: s0_y_b(13) <= not( s1_raw(13) and ci0 ); + hc13_s1x: s1_x_b(13) <= not( s0_raw(13) and ci1_b ); + hc13_s1y: s1_y_b(13) <= not( s1_raw(13) and ci1 ); + hc13_s0: s0 (13) <= not( s0_x_b(13) and s0_y_b(13) ); + hc13_s1: s1 (13) <= not( s1_x_b(13) and s1_y_b(13) ); + + hc14_s0x: s0_x_b(14) <= not( s0_raw(14) and ci0_b ); + hc14_s0y: s0_y_b(14) <= not( s1_raw(14) and ci0 ); + hc14_s1x: s1_x_b(14) <= not( s0_raw(14) and ci1_b ); + hc14_s1y: s1_y_b(14) <= not( s1_raw(14) and ci1 ); + hc14_s0: s0 (14) <= not( s0_x_b(14) and s0_y_b(14) ); + hc14_s1: s1 (14) <= not( s1_x_b(14) and s1_y_b(14) ); + + hc15_s0x: s0_x_b(15) <= not( s0_raw(15) and ci0_b ); + hc15_s0y: s0_y_b(15) <= not( s1_raw(15) and ci0 ); + hc15_s1x: s1_x_b(15) <= not( s0_raw(15) and ci1_b ); + hc15_s1y: s1_y_b(15) <= not( s1_raw(15) and ci1 ); + hc15_s0: s0 (15) <= not( s0_x_b(15) and s0_y_b(15) ); + hc15_s1: s1 (15) <= not( s1_x_b(15) and s1_y_b(15) ); + + +END; + + + + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_hc16pp_lsb.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_hc16pp_lsb.vhdl new file mode 100644 index 0000000..a72321a --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_hc16pp_lsb.vhdl @@ -0,0 +1,325 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; use ieee.std_logic_1164.all ; +library ibm; +library support; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + +ENTITY fuq_hc16pp_lsb IS PORT( + x : IN std_ulogic_vector(0 to 13); + y : IN std_ulogic_vector(0 to 12); + s0 : OUT std_ulogic_vector(0 to 13); + s1 : OUT std_ulogic_vector(0 to 13); + g16 : out std_ulogic; + t16 : out std_ulogic +); + + +END fuq_hc16pp_lsb; + +ARCHITECTURE fuq_hc16pp_lsb OF fuq_hc16pp_lsb IS + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + + signal g01_b :std_ulogic_vector(0 to 12); + signal t01_b, p01_b, p01 :std_ulogic_vector(0 to 13); + + signal g01od :std_ulogic_vector(0 to 5); + signal t01od :std_ulogic_vector(0 to 6); + + + signal g02ev , t02ev :std_ulogic_vector(0 to 6); + signal g02ev_b, t02ev_b :std_ulogic_vector(1 to 6); + signal g04ev , t04ev :std_ulogic_vector(1 to 6); + signal g08ev_b, t08ev_b :std_ulogic_vector(1 to 6); + signal g16ev , t16ev :std_ulogic_vector(1 to 6); + signal c0_b :std_ulogic_vector(1 to 12); + signal c1_b :std_ulogic_vector(1 to 13); + + signal glb_g04_e01_b, glb_g04_e23_b, glb_g04_e45_b, glb_g04_e67_b :std_ulogic; + signal glb_t04_e01_b, glb_t04_e23_b, glb_t04_e45_b, glb_t04_e67_b :std_ulogic; + signal glb_g08_e03 , glb_g08_e47 , glb_t08_e03 , glb_t08_e47 :std_ulogic; + signal glb_g16_e07_b, glb_t16_e07_b :std_ulogic; + + + + +BEGIN + + + hc00_g01: g01_b( 0) <= not( x( 0) and y( 0) ); + hc01_g01: g01_b( 1) <= not( x( 1) and y( 1) ); + hc02_g01: g01_b( 2) <= not( x( 2) and y( 2) ); + hc03_g01: g01_b( 3) <= not( x( 3) and y( 3) ); + hc04_g01: g01_b( 4) <= not( x( 4) and y( 4) ); + hc05_g01: g01_b( 5) <= not( x( 5) and y( 5) ); + hc06_g01: g01_b( 6) <= not( x( 6) and y( 6) ); + hc07_g01: g01_b( 7) <= not( x( 7) and y( 7) ); + hc08_g01: g01_b( 8) <= not( x( 8) and y( 8) ); + hc09_g01: g01_b( 9) <= not( x( 9) and y( 9) ); + hc10_g01: g01_b(10) <= not( x(10) and y(10) ); + hc11_g01: g01_b(11) <= not( x(11) and y(11) ); + hc12_g01: g01_b(12) <= not( x(12) and y(12) ); + + hc00_t01: t01_b( 0) <= not( x( 0) or y( 0) ); + hc01_t01: t01_b( 1) <= not( x( 1) or y( 1) ); + hc02_t01: t01_b( 2) <= not( x( 2) or y( 2) ); + hc03_t01: t01_b( 3) <= not( x( 3) or y( 3) ); + hc04_t01: t01_b( 4) <= not( x( 4) or y( 4) ); + hc05_t01: t01_b( 5) <= not( x( 5) or y( 5) ); + hc06_t01: t01_b( 6) <= not( x( 6) or y( 6) ); + hc07_t01: t01_b( 7) <= not( x( 7) or y( 7) ); + hc08_t01: t01_b( 8) <= not( x( 8) or y( 8) ); + hc09_t01: t01_b( 9) <= not( x( 9) or y( 9) ); + hc10_t01: t01_b(10) <= not( x(10) or y(10) ); + hc11_t01: t01_b(11) <= not( x(11) or y(11) ); + hc12_t01: t01_b(12) <= not( x(12) or y(12) ); + hc13_t01: t01_b(13) <= not( x(13) ); + + hc00_p01: p01( 0) <= ( x( 0) xor y( 0) ); + hc01_p01: p01( 1) <= ( x( 1) xor y( 1) ); + hc02_p01: p01( 2) <= ( x( 2) xor y( 2) ); + hc03_p01: p01( 3) <= ( x( 3) xor y( 3) ); + hc04_p01: p01( 4) <= ( x( 4) xor y( 4) ); + hc05_p01: p01( 5) <= ( x( 5) xor y( 5) ); + hc06_p01: p01( 6) <= ( x( 6) xor y( 6) ); + hc07_p01: p01( 7) <= ( x( 7) xor y( 7) ); + hc08_p01: p01( 8) <= ( x( 8) xor y( 8) ); + hc09_p01: p01( 9) <= ( x( 9) xor y( 9) ); + hc10_p01: p01(10) <= ( x(10) xor y(10) ); + hc11_p01: p01(11) <= ( x(11) xor y(11) ); + hc12_p01: p01(12) <= ( x(12) xor y(12) ); + hc13_p01: p01(13) <= not p01_b(13) ; + + hc00_p01b: p01_b( 0) <= not( p01( 0) ); + hc01_p01b: p01_b( 1) <= not( p01( 1) ); + hc02_p01b: p01_b( 2) <= not( p01( 2) ); + hc03_p01b: p01_b( 3) <= not( p01( 3) ); + hc04_p01b: p01_b( 4) <= not( p01( 4) ); + hc05_p01b: p01_b( 5) <= not( p01( 5) ); + hc06_p01b: p01_b( 6) <= not( p01( 6) ); + hc07_p01b: p01_b( 7) <= not( p01( 7) ); + hc08_p01b: p01_b( 8) <= not( p01( 8) ); + hc09_p01b: p01_b( 9) <= not( p01( 9) ); + hc10_p01b: p01_b(10) <= not( p01(10) ); + hc11_p01b: p01_b(11) <= not( p01(11) ); + hc12_p01b: p01_b(12) <= not( p01(12) ); + hc13_p01b: p01_b(13) <= not( x(13) ); + + hc01_g01o: g01od(0) <= not g01_b( 1); + hc03_g01o: g01od(1) <= not g01_b( 3); + hc05_g01o: g01od(2) <= not g01_b( 5); + hc07_g01o: g01od(3) <= not g01_b( 7); + hc09_g01o: g01od(4) <= not g01_b( 9); + hc11_g01o: g01od(5) <= not g01_b(11); + + hc01_t01o: t01od(0) <= not t01_b( 1); + hc03_t01o: t01od(1) <= not t01_b( 3); + hc05_t01o: t01od(2) <= not t01_b( 5); + hc07_t01o: t01od(3) <= not t01_b( 7); + hc09_t01o: t01od(4) <= not t01_b( 9); + hc11_t01o: t01od(5) <= not t01_b(11); + hc13_t01o: t01od(6) <= not t01_b(13); + + + + hc12_g02: g02ev(6) <= not( g01_b(12) ); + hc10_g02: g02ev(5) <= not( ( t01_b(10) or g01_b(11) ) and g01_b(10) ); + hc08_g02: g02ev(4) <= not( ( t01_b( 8) or g01_b( 9) ) and g01_b( 8) ); + hc06_g02: g02ev(3) <= not( ( t01_b( 6) or g01_b( 7) ) and g01_b( 6) ); + hc04_g02: g02ev(2) <= not( ( t01_b( 4) or g01_b( 5) ) and g01_b( 4) ); + hc02_g02: g02ev(1) <= not( ( t01_b( 2) or g01_b( 3) ) and g01_b( 2) ); + hc00_g02: g02ev(0) <= not( ( t01_b( 0) or g01_b( 1) ) and g01_b( 0) ); + + hc12_t02: t02ev(6) <= not( ( t01_b(12) or t01_b(13) ) and g01_b(12) ); + hc10_t02: t02ev(5) <= not( ( t01_b(10) or t01_b(11) ) ); + hc08_t02: t02ev(4) <= not( ( t01_b( 8) or t01_b( 9) ) ); + hc06_t02: t02ev(3) <= not( ( t01_b( 6) or t01_b( 7) ) ); + hc04_t02: t02ev(2) <= not( ( t01_b( 4) or t01_b( 5) ) ); + hc02_t02: t02ev(1) <= not( ( t01_b( 2) or t01_b( 3) ) ); + hc00_t02: t02ev(0) <= not( ( t01_b( 0) or t01_b( 1) ) ); + + hc12_g02b: g02ev_b(6) <= not( g02ev(6) ); + hc10_g02b: g02ev_b(5) <= not( g02ev(5) ); + hc08_g02b: g02ev_b(4) <= not( g02ev(4) ); + hc06_g02b: g02ev_b(3) <= not( g02ev(3) ); + hc04_g02b: g02ev_b(2) <= not( g02ev(2) ); + hc02_g02b: g02ev_b(1) <= not( g02ev(1) ); + + hc12_t02b: t02ev_b(6) <= not( t02ev(6) ); + hc10_t02b: t02ev_b(5) <= not( t02ev(5) ); + hc08_t02b: t02ev_b(4) <= not( t02ev(4) ); + hc06_t02b: t02ev_b(3) <= not( t02ev(3) ); + hc04_t02b: t02ev_b(2) <= not( t02ev(2) ); + hc02_t02b: t02ev_b(1) <= not( t02ev(1) ); + + + u_glb_g04_e01: glb_g04_e01_b <= not( g02ev(0) or ( t02ev(0) and g02ev(1) ) ); + u_glb_g04_e23: glb_g04_e23_b <= not( g02ev(2) or ( t02ev(2) and g02ev(3) ) ); + u_glb_g04_e45: glb_g04_e45_b <= not( g02ev(4) or ( t02ev(4) and g02ev(5) ) ); + u_glb_g04_e67: glb_g04_e67_b <= not( g02ev(6) ); + u_glb_t04_e01: glb_t04_e01_b <= not( t02ev(0) and t02ev(1) ); + u_glb_t04_e23: glb_t04_e23_b <= not( t02ev(2) and t02ev(3) ); + u_glb_t04_e45: glb_t04_e45_b <= not( t02ev(4) and t02ev(5) ); + u_glb_t04_e67: glb_t04_e67_b <= not( t02ev(6) ); + + u_glb_g08_e03: glb_g08_e03 <= not( glb_g04_e01_b and ( glb_t04_e01_b or glb_g04_e23_b ) ); + u_glb_g08_e47: glb_g08_e47 <= not( glb_g04_e45_b and ( glb_t04_e45_b or glb_g04_e67_b ) ); + u_glb_t08_e03: glb_t08_e03 <= not( glb_t04_e01_b or glb_t04_e23_b ); + u_glb_t08_e47: glb_t08_e47 <= not( glb_g04_e45_b and ( glb_t04_e45_b or glb_t04_e67_b ) ); + + u_glb_g16_e07: glb_g16_e07_b <= not( glb_g08_e03 or ( glb_t08_e03 and glb_g08_e47 ) ); + u_glb_t16_e07: glb_t16_e07_b <= not( glb_g08_e03 or ( glb_t08_e03 and glb_t08_e47 ) ); + + u_g16o: g16 <= not( glb_g16_e07_b ); + u_t16o: t16 <= not( glb_t16_e07_b ); + + + hc12_g04: g04ev (6) <= not( g02ev_b(6) ); + hc10_g04: g04ev (5) <= not( (t02ev_b(5) or g02ev_b(6)) and g02ev_b(5) ); + hc08_g04: g04ev (4) <= not( (t02ev_b(4) or g02ev_b(5)) and g02ev_b(4) ); + hc06_g04: g04ev (3) <= not( (t02ev_b(3) or g02ev_b(4)) and g02ev_b(3) ); + hc04_g04: g04ev (2) <= not( (t02ev_b(2) or g02ev_b(3)) and g02ev_b(2) ); + hc02_g04: g04ev (1) <= not( (t02ev_b(1) or g02ev_b(2)) and g02ev_b(1) ); + + + hc12_t04: t04ev (6) <= not( t02ev_b(6) ); + hc10_t04: t04ev (5) <= not( (t02ev_b(5) or t02ev_b(6)) and g02ev_b(5) ); + hc08_t04: t04ev (4) <= not( t02ev_b(4) or t02ev_b(5) ); + hc06_t04: t04ev (3) <= not( t02ev_b(3) or t02ev_b(4) ); + hc04_t04: t04ev (2) <= not( t02ev_b(2) or t02ev_b(3) ); + hc02_t04: t04ev (1) <= not( t02ev_b(1) or t02ev_b(2) ); + + + + hc12_g08: g08ev_b(6) <= not( g04ev (6) ); + hc10_g08: g08ev_b(5) <= not( g04ev (5) ); + hc08_g08: g08ev_b(4) <= not( g04ev (4) or (t04ev (4) and g04ev (6)) ); + hc06_g08: g08ev_b(3) <= not( g04ev (3) or (t04ev (3) and g04ev (5)) ); + hc04_g08: g08ev_b(2) <= not( g04ev (2) or (t04ev (2) and g04ev (4)) ); + hc02_g08: g08ev_b(1) <= not( g04ev (1) or (t04ev (1) and g04ev (3)) ); + + + hc12_t08: t08ev_b(6) <= not( t04ev (6) ); + hc10_t08: t08ev_b(5) <= not( t04ev (5) ); + hc08_t08: t08ev_b(4) <= not( g04ev (4) or (t04ev (4) and t04ev (6)) ); + hc06_t08: t08ev_b(3) <= not( g04ev (3) or (t04ev (3) and t04ev (5)) ); + hc04_t08: t08ev_b(2) <= not( t04ev (2) and t04ev (4) ); + hc02_t08: t08ev_b(1) <= not( t04ev (1) and t04ev (3) ); + + + + hc12_g16: g16ev (6) <= not( g08ev_b(6) ); + hc10_g16: g16ev (5) <= not( g08ev_b(5) ); + hc08_g16: g16ev (4) <= not( g08ev_b(4) ); + hc06_g16: g16ev (3) <= not( g08ev_b(3) ); + hc04_g16: g16ev (2) <= not( (t08ev_b(2) or g08ev_b(6)) and g08ev_b(2) ); + hc02_g16: g16ev (1) <= not( (t08ev_b(1) or g08ev_b(5)) and g08ev_b(1) ); + + + hc12_t16: t16ev (6) <= not( t08ev_b(6) ); + hc10_t16: t16ev (5) <= not( t08ev_b(5) ); + hc08_t16: t16ev (4) <= not( t08ev_b(4) ); + hc06_t16: t16ev (3) <= not( t08ev_b(3) ); + hc04_t16: t16ev (2) <= not( (t08ev_b(2) or t08ev_b(6)) and g08ev_b(2) ); + hc02_t16: t16ev (1) <= not( (t08ev_b(1) or t08ev_b(5)) and g08ev_b(1) ); + + + + hc12_c0: c0_b(12) <= not( g16ev (6) ); + hc10_c0: c0_b(10) <= not( g16ev (5) ); + hc08_c0: c0_b( 8) <= not( g16ev (4) ); + hc06_c0: c0_b( 6) <= not( g16ev (3) ); + hc04_c0: c0_b( 4) <= not( g16ev (2) ); + hc02_c0: c0_b( 2) <= not( g16ev (1) ); + + hc12_c1: c1_b(12) <= not( t16ev (6) ); + hc10_c1: c1_b(10) <= not( t16ev (5) ); + hc08_c1: c1_b( 8) <= not( t16ev (4) ); + hc06_c1: c1_b( 6) <= not( t16ev (3) ); + hc04_c1: c1_b( 4) <= not( t16ev (2) ); + hc02_c1: c1_b( 2) <= not( t16ev (1) ); + + hc11_c0: c0_b(11) <= not( (t01od(5) and g16ev (6)) or g01od(5)); + hc09_c0: c0_b( 9) <= not( (t01od(4) and g16ev (5)) or g01od(4)); + hc07_c0: c0_b( 7) <= not( (t01od(3) and g16ev (4)) or g01od(3)); + hc05_c0: c0_b( 5) <= not( (t01od(2) and g16ev (3)) or g01od(2)); + hc03_c0: c0_b( 3) <= not( (t01od(1) and g16ev (2)) or g01od(1)); + hc01_c0: c0_b( 1) <= not( (t01od(0) and g16ev (1)) or g01od(0)); + + hc13_c1: c1_b(13) <= not( t01od(6)); + hc11_c1: c1_b(11) <= not( (t01od(5) and t16ev (6)) or g01od(5)); + hc09_c1: c1_b( 9) <= not( (t01od(4) and t16ev (5)) or g01od(4)); + hc07_c1: c1_b( 7) <= not( (t01od(3) and t16ev (4)) or g01od(3)); + hc05_c1: c1_b( 5) <= not( (t01od(2) and t16ev (3)) or g01od(2)); + hc03_c1: c1_b( 3) <= not( (t01od(1) and t16ev (2)) or g01od(1)); + hc01_c1: c1_b( 1) <= not( (t01od(0) and t16ev (1)) or g01od(0)); + + + hc00_s0: s0( 0) <= ( p01_b( 0) xor c0_b( 1) ); + hc01_s0: s0( 1) <= ( p01_b( 1) xor c0_b( 2) ); + hc02_s0: s0( 2) <= ( p01_b( 2) xor c0_b( 3) ); + hc03_s0: s0( 3) <= ( p01_b( 3) xor c0_b( 4) ); + hc04_s0: s0( 4) <= ( p01_b( 4) xor c0_b( 5) ); + hc05_s0: s0( 5) <= ( p01_b( 5) xor c0_b( 6) ); + hc06_s0: s0( 6) <= ( p01_b( 6) xor c0_b( 7) ); + hc07_s0: s0( 7) <= ( p01_b( 7) xor c0_b( 8) ); + hc08_s0: s0( 8) <= ( p01_b( 8) xor c0_b( 9) ); + hc09_s0: s0( 9) <= ( p01_b( 9) xor c0_b(10) ); + hc10_s0: s0(10) <= ( p01_b(10) xor c0_b(11) ); + hc11_s0: s0(11) <= ( p01_b(11) xor c0_b(12) ); + hc12_s0: s0(12) <= not( p01_b(12) ); + hc13_s0: s0(13) <= not( p01_b(13) ); + + hc00_s1: s1( 0) <= ( p01_b( 0) xor c1_b( 1) ); + hc01_s1: s1( 1) <= ( p01_b( 1) xor c1_b( 2) ); + hc02_s1: s1( 2) <= ( p01_b( 2) xor c1_b( 3) ); + hc03_s1: s1( 3) <= ( p01_b( 3) xor c1_b( 4) ); + hc04_s1: s1( 4) <= ( p01_b( 4) xor c1_b( 5) ); + hc05_s1: s1( 5) <= ( p01_b( 5) xor c1_b( 6) ); + hc06_s1: s1( 6) <= ( p01_b( 6) xor c1_b( 7) ); + hc07_s1: s1( 7) <= ( p01_b( 7) xor c1_b( 8) ); + hc08_s1: s1( 8) <= ( p01_b( 8) xor c1_b( 9) ); + hc09_s1: s1( 9) <= ( p01_b( 9) xor c1_b(10) ); + hc10_s1: s1(10) <= ( p01_b(10) xor c1_b(11) ); + hc11_s1: s1(11) <= ( p01_b(11) xor c1_b(12) ); + hc12_s1: s1(12) <= ( p01_b(12) xor c1_b(13) ); + hc13_s1: s1(13) <= not( p01(13) ); + + +END; + + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_hc16pp_msb.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_hc16pp_msb.vhdl new file mode 100644 index 0000000..dee0165 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_hc16pp_msb.vhdl @@ -0,0 +1,483 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + + +library ieee; use ieee.std_logic_1164.all ; +library ibm; +library support; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + +ENTITY fuq_hc16pp_msb IS PORT( + x : IN std_ulogic_vector(0 to 15); + y : IN std_ulogic_vector(0 to 15); + ci0 : IN std_ulogic; + ci0_b : IN std_ulogic; + ci1 : IN std_ulogic; + ci1_b : IN std_ulogic; + s0 : OUT std_ulogic_vector(0 to 15); + s1 : OUT std_ulogic_vector(0 to 15); + g16 : out std_ulogic; + t16 : out std_ulogic +); + + +END fuq_hc16pp_msb; + +ARCHITECTURE fuq_hc16pp_msb OF fuq_hc16pp_msb IS + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal g01_b :std_ulogic_vector(1 to 15); + signal t01_b, p01_b, p01 :std_ulogic_vector(0 to 15); + signal g01od, t01od :std_ulogic_vector(0 to 7); + signal g02ev , t02ev :std_ulogic_vector(0 to 7); + signal g02ev_b , t02ev_b :std_ulogic_vector(1 to 7); + signal g04ev, t04ev :std_ulogic_vector(1 to 7); + signal g08ev_b, t08ev_b :std_ulogic_vector(1 to 7); + signal g16ev, t16ev :std_ulogic_vector(1 to 7); + signal c0_b , c1_b :std_ulogic_vector(1 to 15); + signal s0_raw, s1_raw :std_ulogic_vector(0 to 15); + signal s0_x_b, s0_y_b :std_ulogic_vector(0 to 15); + signal s1_x_b, s1_y_b :std_ulogic_vector(0 to 15); + + signal glb_g04_e01_b, glb_g04_e23_b, glb_g04_e45_b, glb_g04_e67_b :std_ulogic; + signal glb_t04_e01_b, glb_t04_e23_b, glb_t04_e45_b, glb_t04_e67_b :std_ulogic; + signal glb_g08_e03 , glb_g08_e47 , glb_t08_e03 , glb_t08_e47 :std_ulogic; + signal glb_g16_e07_b, glb_t16_e07_b :std_ulogic; + + + + + + + + + + +BEGIN + + + hc01_g01: g01_b( 1) <= not( x( 1) and y( 1) ); + hc02_g01: g01_b( 2) <= not( x( 2) and y( 2) ); + hc03_g01: g01_b( 3) <= not( x( 3) and y( 3) ); + hc04_g01: g01_b( 4) <= not( x( 4) and y( 4) ); + hc05_g01: g01_b( 5) <= not( x( 5) and y( 5) ); + hc06_g01: g01_b( 6) <= not( x( 6) and y( 6) ); + hc07_g01: g01_b( 7) <= not( x( 7) and y( 7) ); + hc08_g01: g01_b( 8) <= not( x( 8) and y( 8) ); + hc09_g01: g01_b( 9) <= not( x( 9) and y( 9) ); + hc10_g01: g01_b(10) <= not( x(10) and y(10) ); + hc11_g01: g01_b(11) <= not( x(11) and y(11) ); + hc12_g01: g01_b(12) <= not( x(12) and y(12) ); + hc13_g01: g01_b(13) <= not( x(13) and y(13) ); + hc14_g01: g01_b(14) <= not( x(14) and y(14) ); + hc15_g01: g01_b(15) <= not( x(15) and y(15) ); + + + hc00_t01: t01_b( 0) <= not( x( 0) and y( 0) ); + hc01_t01: t01_b( 1) <= not( x( 1) or y( 1) ); + hc02_t01: t01_b( 2) <= not( x( 2) or y( 2) ); + hc03_t01: t01_b( 3) <= not( x( 3) or y( 3) ); + hc04_t01: t01_b( 4) <= not( x( 4) or y( 4) ); + hc05_t01: t01_b( 5) <= not( x( 5) or y( 5) ); + hc06_t01: t01_b( 6) <= not( x( 6) or y( 6) ); + hc07_t01: t01_b( 7) <= not( x( 7) or y( 7) ); + hc08_t01: t01_b( 8) <= not( x( 8) or y( 8) ); + hc09_t01: t01_b( 9) <= not( x( 9) or y( 9) ); + hc10_t01: t01_b(10) <= not( x(10) or y(10) ); + hc11_t01: t01_b(11) <= not( x(11) or y(11) ); + hc12_t01: t01_b(12) <= not( x(12) or y(12) ); + hc13_t01: t01_b(13) <= not( x(13) or y(13) ); + hc14_t01: t01_b(14) <= not( x(14) or y(14) ); + hc15_t01: t01_b(15) <= not( x(15) or y(15) ); + + + hc00_p01: p01( 0) <= not( x( 0) xor y( 0) ); + hc01_p01: p01( 1) <= ( x( 1) xor y( 1) ); + hc02_p01: p01( 2) <= ( x( 2) xor y( 2) ); + hc03_p01: p01( 3) <= ( x( 3) xor y( 3) ); + hc04_p01: p01( 4) <= ( x( 4) xor y( 4) ); + hc05_p01: p01( 5) <= ( x( 5) xor y( 5) ); + hc06_p01: p01( 6) <= ( x( 6) xor y( 6) ); + hc07_p01: p01( 7) <= ( x( 7) xor y( 7) ); + hc08_p01: p01( 8) <= ( x( 8) xor y( 8) ); + hc09_p01: p01( 9) <= ( x( 9) xor y( 9) ); + hc10_p01: p01(10) <= ( x(10) xor y(10) ); + hc11_p01: p01(11) <= ( x(11) xor y(11) ); + hc12_p01: p01(12) <= ( x(12) xor y(12) ); + hc13_p01: p01(13) <= ( x(13) xor y(13) ); + hc14_p01: p01(14) <= ( x(14) xor y(14) ); + hc15_p01: p01(15) <= ( x(15) xor y(15) ); + + hc00_p01b: p01_b( 0) <= not( p01( 0) ); + hc01_p01b: p01_b( 1) <= not( p01( 1) ); + hc02_p01b: p01_b( 2) <= not( p01( 2) ); + hc03_p01b: p01_b( 3) <= not( p01( 3) ); + hc04_p01b: p01_b( 4) <= not( p01( 4) ); + hc05_p01b: p01_b( 5) <= not( p01( 5) ); + hc06_p01b: p01_b( 6) <= not( p01( 6) ); + hc07_p01b: p01_b( 7) <= not( p01( 7) ); + hc08_p01b: p01_b( 8) <= not( p01( 8) ); + hc09_p01b: p01_b( 9) <= not( p01( 9) ); + hc10_p01b: p01_b(10) <= not( p01(10) ); + hc11_p01b: p01_b(11) <= not( p01(11) ); + hc12_p01b: p01_b(12) <= not( p01(12) ); + hc13_p01b: p01_b(13) <= not( p01(13) ); + hc14_p01b: p01_b(14) <= not( p01(14) ); + hc15_p01b: p01_b(15) <= not( p01(15) ); + + + hc01_g01o: g01od(0) <= not g01_b( 1); + hc03_g01o: g01od(1) <= not g01_b( 3); + hc05_g01o: g01od(2) <= not g01_b( 5); + hc07_g01o: g01od(3) <= not g01_b( 7); + hc09_g01o: g01od(4) <= not g01_b( 9); + hc11_g01o: g01od(5) <= not g01_b(11); + hc13_g01o: g01od(6) <= not g01_b(13); + hc15_g01o: g01od(7) <= not g01_b(15); + + hc01_t01o: t01od(0) <= not t01_b( 1); + hc03_t01o: t01od(1) <= not t01_b( 3); + hc05_t01o: t01od(2) <= not t01_b( 5); + hc07_t01o: t01od(3) <= not t01_b( 7); + hc09_t01o: t01od(4) <= not t01_b( 9); + hc11_t01o: t01od(5) <= not t01_b(11); + hc13_t01o: t01od(6) <= not t01_b(13); + hc15_t01o: t01od(7) <= not t01_b(15); + + + hc14_g02: g02ev(7) <= not( ( t01_b(14) or g01_b(15) ) and g01_b(14) ); + hc12_g02: g02ev(6) <= not( ( t01_b(12) or g01_b(13) ) and g01_b(12) ); + hc10_g02: g02ev(5) <= not( ( t01_b(10) or g01_b(11) ) and g01_b(10) ); + hc08_g02: g02ev(4) <= not( ( t01_b( 8) or g01_b( 9) ) and g01_b( 8) ); + hc06_g02: g02ev(3) <= not( ( t01_b( 6) or g01_b( 7) ) and g01_b( 6) ); + hc04_g02: g02ev(2) <= not( ( t01_b( 4) or g01_b( 5) ) and g01_b( 4) ); + hc02_g02: g02ev(1) <= not( ( t01_b( 2) or g01_b( 3) ) and g01_b( 2) ); + hc00_g02: g02ev(0) <= not( t01_b( 0) or g01_b( 1) ); + + hc14_t02: t02ev(7) <= not( ( t01_b(14) or t01_b(15) ) and g01_b(14) ); + hc12_t02: t02ev(6) <= not( t01_b(12) or t01_b(13) ); + hc10_t02: t02ev(5) <= not( t01_b(10) or t01_b(11) ); + hc08_t02: t02ev(4) <= not( t01_b( 8) or t01_b( 9) ); + hc06_t02: t02ev(3) <= not( t01_b( 6) or t01_b( 7) ); + hc04_t02: t02ev(2) <= not( t01_b( 4) or t01_b( 5) ); + hc02_t02: t02ev(1) <= not( t01_b( 2) or t01_b( 3) ); + hc00_t02: t02ev(0) <= not( t01_b( 0) or t01_b( 1) ); + + hc14_g02b: g02ev_b(7) <= not( g02ev(7) ); + hc12_g02b: g02ev_b(6) <= not( g02ev(6) ); + hc10_g02b: g02ev_b(5) <= not( g02ev(5) ); + hc08_g02b: g02ev_b(4) <= not( g02ev(4) ); + hc06_g02b: g02ev_b(3) <= not( g02ev(3) ); + hc04_g02b: g02ev_b(2) <= not( g02ev(2) ); + hc02_g02b: g02ev_b(1) <= not( g02ev(1) ); + + hc14_t02b: t02ev_b(7) <= not( t02ev(7) ); + hc12_t02b: t02ev_b(6) <= not( t02ev(6) ); + hc10_t02b: t02ev_b(5) <= not( t02ev(5) ); + hc08_t02b: t02ev_b(4) <= not( t02ev(4) ); + hc06_t02b: t02ev_b(3) <= not( t02ev(3) ); + hc04_t02b: t02ev_b(2) <= not( t02ev(2) ); + hc02_t02b: t02ev_b(1) <= not( t02ev(1) ); + + + u_glb_g04_e01: glb_g04_e01_b <= not( g02ev(0) or ( t02ev(0) and g02ev(1) ) ); + u_glb_g04_e23: glb_g04_e23_b <= not( g02ev(2) or ( t02ev(2) and g02ev(3) ) ); + u_glb_g04_e45: glb_g04_e45_b <= not( g02ev(4) or ( t02ev(4) and g02ev(5) ) ); + u_glb_g04_e67: glb_g04_e67_b <= not( g02ev(6) or ( t02ev(6) and g02ev(7) ) ); + u_glb_t04_e01: glb_t04_e01_b <= not( t02ev(0) and t02ev(1) ); + u_glb_t04_e23: glb_t04_e23_b <= not( t02ev(2) and t02ev(3) ); + u_glb_t04_e45: glb_t04_e45_b <= not( t02ev(4) and t02ev(5) ); + u_glb_t04_e67: glb_t04_e67_b <= not( g02ev(6) or ( t02ev(6) and t02ev(7) ) ); + + u_glb_g08_e03: glb_g08_e03 <= not( glb_g04_e01_b and ( glb_t04_e01_b or glb_g04_e23_b ) ); + u_glb_g08_e47: glb_g08_e47 <= not( glb_g04_e45_b and ( glb_t04_e45_b or glb_g04_e67_b ) ); + u_glb_t08_e03: glb_t08_e03 <= not( glb_t04_e01_b or glb_t04_e23_b ); + u_glb_t08_e47: glb_t08_e47 <= not( glb_g04_e45_b and ( glb_t04_e45_b or glb_t04_e67_b ) ); + + u_glb_g16_e07: glb_g16_e07_b <= not( glb_g08_e03 or ( glb_t08_e03 and glb_g08_e47 ) ); + u_glb_t16_e07: glb_t16_e07_b <= not( glb_g08_e03 or ( glb_t08_e03 and glb_t08_e47 ) ); + + u_g16o: g16 <= not( glb_g16_e07_b ); + u_t16o: t16 <= not( glb_t16_e07_b ); + + + + hc14_g04: g04ev(7) <= not( g02ev_b(7) ); + hc12_g04: g04ev(6) <= not( g02ev_b(6) and (t02ev_b(6) or g02ev_b(7)) ); + hc10_g04: g04ev(5) <= not( g02ev_b(5) and (t02ev_b(5) or g02ev_b(6)) ); + hc08_g04: g04ev(4) <= not( g02ev_b(4) and (t02ev_b(4) or g02ev_b(5)) ); + hc06_g04: g04ev(3) <= not( g02ev_b(3) and (t02ev_b(3) or g02ev_b(4)) ); + hc04_g04: g04ev(2) <= not( g02ev_b(2) and (t02ev_b(2) or g02ev_b(3)) ); + hc02_g04: g04ev(1) <= not( g02ev_b(1) and (t02ev_b(1) or g02ev_b(2)) ); + + + hc14_t04: t04ev(7) <= not( t02ev_b(7) ); + hc12_t04: t04ev(6) <= not( g02ev_b(6) and (t02ev_b(6) or t02ev_b(7)) ); + hc10_t04: t04ev(5) <= not( t02ev_b(5) or t02ev_b(6) ); + hc08_t04: t04ev(4) <= not( t02ev_b(4) or t02ev_b(5) ); + hc06_t04: t04ev(3) <= not( t02ev_b(3) or t02ev_b(4) ); + hc04_t04: t04ev(2) <= not( t02ev_b(2) or t02ev_b(3) ); + hc02_t04: t04ev(1) <= not( t02ev_b(1) or t02ev_b(2) ); + + + hc14_g08: g08ev_b(7) <= not( g04ev(7) ); + hc12_g08: g08ev_b(6) <= not( g04ev(6) ); + hc10_g08: g08ev_b(5) <= not( g04ev(5) or (t04ev(5) and g04ev(7)) ); + hc08_g08: g08ev_b(4) <= not( g04ev(4) or (t04ev(4) and g04ev(6)) ); + hc06_g08: g08ev_b(3) <= not( g04ev(3) or (t04ev(3) and g04ev(5)) ); + hc04_g08: g08ev_b(2) <= not( g04ev(2) or (t04ev(2) and g04ev(4)) ); + hc02_g08: g08ev_b(1) <= not( g04ev(1) or (t04ev(1) and g04ev(3)) ); + + + hc14_t08: t08ev_b(7) <= not( t04ev(7) ); + hc12_t08: t08ev_b(6) <= not( t04ev(6) ); + hc10_t08: t08ev_b(5) <= not( g04ev(5) or (t04ev(5) and t04ev(7)) ); + hc08_t08: t08ev_b(4) <= not( g04ev(4) or (t04ev(4) and t04ev(6)) ); + hc06_t08: t08ev_b(3) <= not( t04ev(3) and t04ev(5) ); + hc04_t08: t08ev_b(2) <= not( t04ev(2) and t04ev(4) ); + hc02_t08: t08ev_b(1) <= not( t04ev(1) and t04ev(3) ); + + + + hc14_g16: g16ev(7) <= not( g08ev_b(7) ); + hc12_g16: g16ev(6) <= not( g08ev_b(6) ); + hc10_g16: g16ev(5) <= not( g08ev_b(5) ); + hc08_g16: g16ev(4) <= not( g08ev_b(4) ); + hc06_g16: g16ev(3) <= not( g08ev_b(3) and (t08ev_b(3) or g08ev_b(7)) ); + hc04_g16: g16ev(2) <= not( g08ev_b(2) and (t08ev_b(2) or g08ev_b(6)) ); + hc02_g16: g16ev(1) <= not( g08ev_b(1) and (t08ev_b(1) or g08ev_b(5)) ); + + hc14_t16: t16ev(7) <= not( t08ev_b(7) ); + hc12_t16: t16ev(6) <= not( t08ev_b(6) ); + hc10_t16: t16ev(5) <= not( t08ev_b(5) ); + hc08_t16: t16ev(4) <= not( t08ev_b(4) ); + hc06_t16: t16ev(3) <= not( g08ev_b(3) and (t08ev_b(3) or t08ev_b(7)) ); + hc04_t16: t16ev(2) <= not( g08ev_b(2) and (t08ev_b(2) or t08ev_b(6)) ); + hc02_t16: t16ev(1) <= not( g08ev_b(1) and (t08ev_b(1) or t08ev_b(5)) ); + + + hc14_c0: c0_b(14) <= not( g16ev(7) ); + hc12_c0: c0_b(12) <= not( g16ev(6) ); + hc10_c0: c0_b(10) <= not( g16ev(5) ); + hc08_c0: c0_b( 8) <= not( g16ev(4) ); + hc06_c0: c0_b( 6) <= not( g16ev(3) ); + hc04_c0: c0_b( 4) <= not( g16ev(2) ); + hc02_c0: c0_b( 2) <= not( g16ev(1) ); + + hc14_c1: c1_b(14) <= not( t16ev(7) ); + hc12_c1: c1_b(12) <= not( t16ev(6) ); + hc10_c1: c1_b(10) <= not( t16ev(5) ); + hc08_c1: c1_b( 8) <= not( t16ev(4) ); + hc06_c1: c1_b( 6) <= not( t16ev(3) ); + hc04_c1: c1_b( 4) <= not( t16ev(2) ); + hc02_c1: c1_b( 2) <= not( t16ev(1) ); + + hc15_c0: c0_b(15) <= not( g01od(7)); + hc13_c0: c0_b(13) <= not( (t01od(6) and g16ev(7)) or g01od(6)); + hc11_c0: c0_b(11) <= not( (t01od(5) and g16ev(6)) or g01od(5)); + hc09_c0: c0_b( 9) <= not( (t01od(4) and g16ev(5)) or g01od(4)); + hc07_c0: c0_b( 7) <= not( (t01od(3) and g16ev(4)) or g01od(3)); + hc05_c0: c0_b( 5) <= not( (t01od(2) and g16ev(3)) or g01od(2)); + hc03_c0: c0_b( 3) <= not( (t01od(1) and g16ev(2)) or g01od(1)); + hc01_c0: c0_b( 1) <= not( (t01od(0) and g16ev(1)) or g01od(0)); + + hc15_c1: c1_b(15) <= not( t01od(7) ); + hc13_c1: c1_b(13) <= not( (t01od(6) and t16ev(7)) or g01od(6) ); + hc11_c1: c1_b(11) <= not( (t01od(5) and t16ev(6)) or g01od(5) ); + hc09_c1: c1_b( 9) <= not( (t01od(4) and t16ev(5)) or g01od(4) ); + hc07_c1: c1_b( 7) <= not( (t01od(3) and t16ev(4)) or g01od(3) ); + hc05_c1: c1_b( 5) <= not( (t01od(2) and t16ev(3)) or g01od(2) ); + hc03_c1: c1_b( 3) <= not( (t01od(1) and t16ev(2)) or g01od(1) ); + hc01_c1: c1_b( 1) <= not( (t01od(0) and t16ev(1)) or g01od(0) ); + + + + hc00_s0r: s0_raw( 0) <= ( p01_b( 0) xor c0_b( 1) ); + hc01_s0r: s0_raw( 1) <= ( p01_b( 1) xor c0_b( 2) ); + hc02_s0r: s0_raw( 2) <= ( p01_b( 2) xor c0_b( 3) ); + hc03_s0r: s0_raw( 3) <= ( p01_b( 3) xor c0_b( 4) ); + hc04_s0r: s0_raw( 4) <= ( p01_b( 4) xor c0_b( 5) ); + hc05_s0r: s0_raw( 5) <= ( p01_b( 5) xor c0_b( 6) ); + hc06_s0r: s0_raw( 6) <= ( p01_b( 6) xor c0_b( 7) ); + hc07_s0r: s0_raw( 7) <= ( p01_b( 7) xor c0_b( 8) ); + hc08_s0r: s0_raw( 8) <= ( p01_b( 8) xor c0_b( 9) ); + hc09_s0r: s0_raw( 9) <= ( p01_b( 9) xor c0_b(10) ); + hc10_s0r: s0_raw(10) <= ( p01_b(10) xor c0_b(11) ); + hc11_s0r: s0_raw(11) <= ( p01_b(11) xor c0_b(12) ); + hc12_s0r: s0_raw(12) <= ( p01_b(12) xor c0_b(13) ); + hc13_s0r: s0_raw(13) <= ( p01_b(13) xor c0_b(14) ); + hc14_s0r: s0_raw(14) <= ( p01_b(14) xor c0_b(15) ); + hc15_s0r: s0_raw(15) <= not p01_b(15); + + hc00_s1r: s1_raw( 0) <= ( p01_b( 0) xor c1_b( 1) ); + hc01_s1r: s1_raw( 1) <= ( p01_b( 1) xor c1_b( 2) ); + hc02_s1r: s1_raw( 2) <= ( p01_b( 2) xor c1_b( 3) ); + hc03_s1r: s1_raw( 3) <= ( p01_b( 3) xor c1_b( 4) ); + hc04_s1r: s1_raw( 4) <= ( p01_b( 4) xor c1_b( 5) ); + hc05_s1r: s1_raw( 5) <= ( p01_b( 5) xor c1_b( 6) ); + hc06_s1r: s1_raw( 6) <= ( p01_b( 6) xor c1_b( 7) ); + hc07_s1r: s1_raw( 7) <= ( p01_b( 7) xor c1_b( 8) ); + hc08_s1r: s1_raw( 8) <= ( p01_b( 8) xor c1_b( 9) ); + hc09_s1r: s1_raw( 9) <= ( p01_b( 9) xor c1_b(10) ); + hc10_s1r: s1_raw(10) <= ( p01_b(10) xor c1_b(11) ); + hc11_s1r: s1_raw(11) <= ( p01_b(11) xor c1_b(12) ); + hc12_s1r: s1_raw(12) <= ( p01_b(12) xor c1_b(13) ); + hc13_s1r: s1_raw(13) <= ( p01_b(13) xor c1_b(14) ); + hc14_s1r: s1_raw(14) <= ( p01_b(14) xor c1_b(15) ); + hc15_s1r: s1_raw(15) <= not s0_raw(15); + + + + hc00_s0x: s0_x_b( 0) <= not( s0_raw( 0) and ci0_b ); + hc00_s0y: s0_y_b( 0) <= not( s1_raw( 0) and ci0 ); + hc00_s1x: s1_x_b( 0) <= not( s0_raw( 0) and ci1_b ); + hc00_s1y: s1_y_b( 0) <= not( s1_raw( 0) and ci1 ); + hc00_s0: s0 ( 0) <= not( s0_x_b( 0) and s0_y_b( 0) ); + hc00_s1: s1 ( 0) <= not( s1_x_b( 0) and s1_y_b( 0) ); + + hc01_s0x: s0_x_b( 1) <= not( s0_raw( 1) and ci0_b ); + hc01_s0y: s0_y_b( 1) <= not( s1_raw( 1) and ci0 ); + hc01_s1x: s1_x_b( 1) <= not( s0_raw( 1) and ci1_b ); + hc01_s1y: s1_y_b( 1) <= not( s1_raw( 1) and ci1 ); + hc01_s0: s0 ( 1) <= not( s0_x_b( 1) and s0_y_b( 1) ); + hc01_s1: s1 ( 1) <= not( s1_x_b( 1) and s1_y_b( 1) ); + + hc02_s0x: s0_x_b( 2) <= not( s0_raw( 2) and ci0_b ); + hc02_s0y: s0_y_b( 2) <= not( s1_raw( 2) and ci0 ); + hc02_s1x: s1_x_b( 2) <= not( s0_raw( 2) and ci1_b ); + hc02_s1y: s1_y_b( 2) <= not( s1_raw( 2) and ci1 ); + hc02_s0: s0 ( 2) <= not( s0_x_b( 2) and s0_y_b( 2) ); + hc02_s1: s1 ( 2) <= not( s1_x_b( 2) and s1_y_b( 2) ); + + hc03_s0x: s0_x_b( 3) <= not( s0_raw( 3) and ci0_b ); + hc03_s0y: s0_y_b( 3) <= not( s1_raw( 3) and ci0 ); + hc03_s1x: s1_x_b( 3) <= not( s0_raw( 3) and ci1_b ); + hc03_s1y: s1_y_b( 3) <= not( s1_raw( 3) and ci1 ); + hc03_s0: s0 ( 3) <= not( s0_x_b( 3) and s0_y_b( 3) ); + hc03_s1: s1 ( 3) <= not( s1_x_b( 3) and s1_y_b( 3) ); + + hc04_s0x: s0_x_b( 4) <= not( s0_raw( 4) and ci0_b ); + hc04_s0y: s0_y_b( 4) <= not( s1_raw( 4) and ci0 ); + hc04_s1x: s1_x_b( 4) <= not( s0_raw( 4) and ci1_b ); + hc04_s1y: s1_y_b( 4) <= not( s1_raw( 4) and ci1 ); + hc04_s0: s0 ( 4) <= not( s0_x_b( 4) and s0_y_b( 4) ); + hc04_s1: s1 ( 4) <= not( s1_x_b( 4) and s1_y_b( 4) ); + + hc05_s0x: s0_x_b( 5) <= not( s0_raw( 5) and ci0_b ); + hc05_s0y: s0_y_b( 5) <= not( s1_raw( 5) and ci0 ); + hc05_s1x: s1_x_b( 5) <= not( s0_raw( 5) and ci1_b ); + hc05_s1y: s1_y_b( 5) <= not( s1_raw( 5) and ci1 ); + hc05_s0: s0 ( 5) <= not( s0_x_b( 5) and s0_y_b( 5) ); + hc05_s1: s1 ( 5) <= not( s1_x_b( 5) and s1_y_b( 5) ); + + hc06_s0x: s0_x_b( 6) <= not( s0_raw( 6) and ci0_b ); + hc06_s0y: s0_y_b( 6) <= not( s1_raw( 6) and ci0 ); + hc06_s1x: s1_x_b( 6) <= not( s0_raw( 6) and ci1_b ); + hc06_s1y: s1_y_b( 6) <= not( s1_raw( 6) and ci1 ); + hc06_s0: s0 ( 6) <= not( s0_x_b( 6) and s0_y_b( 6) ); + hc06_s1: s1 ( 6) <= not( s1_x_b( 6) and s1_y_b( 6) ); + + hc07_s0x: s0_x_b( 7) <= not( s0_raw( 7) and ci0_b ); + hc07_s0y: s0_y_b( 7) <= not( s1_raw( 7) and ci0 ); + hc07_s1x: s1_x_b( 7) <= not( s0_raw( 7) and ci1_b ); + hc07_s1y: s1_y_b( 7) <= not( s1_raw( 7) and ci1 ); + hc07_s0: s0 ( 7) <= not( s0_x_b( 7) and s0_y_b( 7) ); + hc07_s1: s1 ( 7) <= not( s1_x_b( 7) and s1_y_b( 7) ); + + hc08_s0x: s0_x_b( 8) <= not( s0_raw( 8) and ci0_b ); + hc08_s0y: s0_y_b( 8) <= not( s1_raw( 8) and ci0 ); + hc08_s1x: s1_x_b( 8) <= not( s0_raw( 8) and ci1_b ); + hc08_s1y: s1_y_b( 8) <= not( s1_raw( 8) and ci1 ); + hc08_s0: s0 ( 8) <= not( s0_x_b( 8) and s0_y_b( 8) ); + hc08_s1: s1 ( 8) <= not( s1_x_b( 8) and s1_y_b( 8) ); + + hc09_s0x: s0_x_b( 9) <= not( s0_raw( 9) and ci0_b ); + hc09_s0y: s0_y_b( 9) <= not( s1_raw( 9) and ci0 ); + hc09_s1x: s1_x_b( 9) <= not( s0_raw( 9) and ci1_b ); + hc09_s1y: s1_y_b( 9) <= not( s1_raw( 9) and ci1 ); + hc09_s0: s0 ( 9) <= not( s0_x_b( 9) and s0_y_b( 9) ); + hc09_s1: s1 ( 9) <= not( s1_x_b( 9) and s1_y_b( 9) ); + + hc10_s0x: s0_x_b(10) <= not( s0_raw(10) and ci0_b ); + hc10_s0y: s0_y_b(10) <= not( s1_raw(10) and ci0 ); + hc10_s1x: s1_x_b(10) <= not( s0_raw(10) and ci1_b ); + hc10_s1y: s1_y_b(10) <= not( s1_raw(10) and ci1 ); + hc10_s0: s0 (10) <= not( s0_x_b(10) and s0_y_b(10) ); + hc10_s1: s1 (10) <= not( s1_x_b(10) and s1_y_b(10) ); + + hc11_s0x: s0_x_b(11) <= not( s0_raw(11) and ci0_b ); + hc11_s0y: s0_y_b(11) <= not( s1_raw(11) and ci0 ); + hc11_s1x: s1_x_b(11) <= not( s0_raw(11) and ci1_b ); + hc11_s1y: s1_y_b(11) <= not( s1_raw(11) and ci1 ); + hc11_s0: s0 (11) <= not( s0_x_b(11) and s0_y_b(11) ); + hc11_s1: s1 (11) <= not( s1_x_b(11) and s1_y_b(11) ); + + hc12_s0x: s0_x_b(12) <= not( s0_raw(12) and ci0_b ); + hc12_s0y: s0_y_b(12) <= not( s1_raw(12) and ci0 ); + hc12_s1x: s1_x_b(12) <= not( s0_raw(12) and ci1_b ); + hc12_s1y: s1_y_b(12) <= not( s1_raw(12) and ci1 ); + hc12_s0: s0 (12) <= not( s0_x_b(12) and s0_y_b(12) ); + hc12_s1: s1 (12) <= not( s1_x_b(12) and s1_y_b(12) ); + + hc13_s0x: s0_x_b(13) <= not( s0_raw(13) and ci0_b ); + hc13_s0y: s0_y_b(13) <= not( s1_raw(13) and ci0 ); + hc13_s1x: s1_x_b(13) <= not( s0_raw(13) and ci1_b ); + hc13_s1y: s1_y_b(13) <= not( s1_raw(13) and ci1 ); + hc13_s0: s0 (13) <= not( s0_x_b(13) and s0_y_b(13) ); + hc13_s1: s1 (13) <= not( s1_x_b(13) and s1_y_b(13) ); + + hc14_s0x: s0_x_b(14) <= not( s0_raw(14) and ci0_b ); + hc14_s0y: s0_y_b(14) <= not( s1_raw(14) and ci0 ); + hc14_s1x: s1_x_b(14) <= not( s0_raw(14) and ci1_b ); + hc14_s1y: s1_y_b(14) <= not( s1_raw(14) and ci1 ); + hc14_s0: s0 (14) <= not( s0_x_b(14) and s0_y_b(14) ); + hc14_s1: s1 (14) <= not( s1_x_b(14) and s1_y_b(14) ); + + hc15_s0x: s0_x_b(15) <= not( s0_raw(15) and ci0_b ); + hc15_s0y: s0_y_b(15) <= not( s1_raw(15) and ci0 ); + hc15_s1x: s1_x_b(15) <= not( s0_raw(15) and ci1_b ); + hc15_s1y: s1_y_b(15) <= not( s1_raw(15) and ci1 ); + hc15_s0: s0 (15) <= not( s0_x_b(15) and s0_y_b(15) ); + hc15_s1: s1 (15) <= not( s1_x_b(15) and s1_y_b(15) ); + + + + +END; + + + + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_loc8inc.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_loc8inc.vhdl new file mode 100644 index 0000000..ec1d328 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_loc8inc.vhdl @@ -0,0 +1,212 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; use ieee.std_logic_1164.all ; +library ibm; + + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + +entity fuq_loc8inc is port( + x :in std_ulogic_vector(0 to 7); + ci :in std_ulogic; + ci_b :in std_ulogic; + co_b :out std_ulogic; + s0 :out std_ulogic_vector(0 to 7); + s1 :out std_ulogic_vector(0 to 7) +); +END fuq_loc8inc; + +ARCHITECTURE fuq_loc8inc OF fuq_loc8inc IS + + + signal x_if_ci, x_b, x_p :std_ulogic_vector(0 to 7); + signal g2_6t7_b :std_ulogic; + signal g2_4t5_b :std_ulogic; + signal g2_2t3_b :std_ulogic; + signal g2_0t1_b :std_ulogic; + signal g4_4t7 :std_ulogic; + signal g4_0t3 :std_ulogic; + signal t2_6t7 :std_ulogic; + signal t2_4t5 :std_ulogic; + signal t2_2t3 :std_ulogic; + signal t4_6t7_b :std_ulogic; + signal t4_4t7_b :std_ulogic; + signal t4_2t5_b :std_ulogic; + signal t8_6t7 :std_ulogic; + signal t8_4t7 :std_ulogic; + signal t8_2t7 :std_ulogic; + signal t8_7t7_b :std_ulogic; + signal t8_6t7_b :std_ulogic; + signal t8_5t7_b :std_ulogic; + signal t8_4t7_b :std_ulogic; + signal t8_3t7_b :std_ulogic; + signal t8_2t7_b :std_ulogic; + signal t8_1t7_b :std_ulogic; + signal s1x_b, s1y_b, s0_b :std_ulogic_vector(0 to 7); + + + + + + + + + + + + +BEGIN + + i0_b0: x_b(0) <= not x(0); + i1_b0: x_b(1) <= not x(1); + i2_b0: x_b(2) <= not x(2); + i3_b0: x_b(3) <= not x(3); + i4_b0: x_b(4) <= not x(4); + i5_b0: x_b(5) <= not x(5); + i6_b0: x_b(6) <= not x(6); + i7_b0: x_b(7) <= not x(7); + + i0_b1: x_p(0) <= not x_b(0); + i1_b1: x_p(1) <= not x_b(1); + i2_b1: x_p(2) <= not x_b(2); + i3_b1: x_p(3) <= not x_b(3); + i4_b1: x_p(4) <= not x_b(4); + i5_b1: x_p(5) <= not x_b(5); + i6_b1: x_p(6) <= not x_b(6); + i7_b1: x_p(7) <= not x_b(7); + + + i0_g2: g2_0t1_b <= not( x(0) and x(1) ); + i2_g2: g2_2t3_b <= not( x(2) and x(3) ); + i4_g2: g2_4t5_b <= not( x(4) and x(5) ); + i6_g2: g2_6t7_b <= not( x(6) and x(7) ); + + i0_g4: g4_0t3 <= not( g2_0t1_b or g2_2t3_b ); + i4_g4: g4_4t7 <= not( g2_4t5_b or g2_6t7_b ); + + i0_g8: co_b <= not( g4_0t3 and g4_4t7 ); + + + i2_t2: t2_2t3 <= not( x_b(2) or x_b(3) ); + i4_t2: t2_4t5 <= not( x_b(4) or x_b(5) ); + i6_t2: t2_6t7 <= not( x_b(6) or x_b(7) ); + + i2_t4: t4_2t5_b <= not( t2_2t3 and t2_4t5 ); + i4_t4: t4_4t7_b <= not( t2_4t5 and t2_6t7 ); + i6_t4: t4_6t7_b <= not( t2_6t7 ); + + i2_t8x: t8_2t7 <= not( t4_2t5_b or t4_6t7_b ); + i4_t8x: t8_4t7 <= not( t4_4t7_b ); + i6_t8x: t8_6t7 <= not( t4_6t7_b ); + + + i1_t8: t8_1t7_b <= not( t8_2t7 and x_p(1) ); + i2_t8: t8_2t7_b <= not( t8_2t7 ); + i3_t8: t8_3t7_b <= not( t8_4t7 and x_p(3) ); + i4_t8: t8_4t7_b <= not( t8_4t7 ); + i5_t8: t8_5t7_b <= not( t8_6t7 and x_p(5) ); + i6_t8: t8_6t7_b <= not( t8_6t7 ); + i7_t8: t8_7t7_b <= not( x_p(7) ); + + + + i0_if: x_if_ci(0) <= not (x_p(0) xor t8_1t7_b) ; + i1_if: x_if_ci(1) <= not (x_p(1) xor t8_2t7_b) ; + i2_if: x_if_ci(2) <= not (x_p(2) xor t8_3t7_b) ; + i3_if: x_if_ci(3) <= not (x_p(3) xor t8_4t7_b) ; + i4_if: x_if_ci(4) <= not (x_p(4) xor t8_5t7_b) ; + i5_if: x_if_ci(5) <= not (x_p(5) xor t8_6t7_b) ; + i6_if: x_if_ci(6) <= not (x_p(6) xor t8_7t7_b) ; + i7_if: x_if_ci(7) <= not (x_p(7) ) ; + + + + i0_s1x: s1x_b(0) <= not( x_p(0) and ci_b ) ; + i1_s1x: s1x_b(1) <= not( x_p(1) and ci_b ) ; + i2_s1x: s1x_b(2) <= not( x_p(2) and ci_b ) ; + i3_s1x: s1x_b(3) <= not( x_p(3) and ci_b ) ; + i4_s1x: s1x_b(4) <= not( x_p(4) and ci_b ) ; + i5_s1x: s1x_b(5) <= not( x_p(5) and ci_b ) ; + i6_s1x: s1x_b(6) <= not( x_p(6) and ci_b ) ; + i7_s1x: s1x_b(7) <= not( x_p(7) and ci_b ) ; + + i0_s1y: s1y_b(0) <= not( x_if_ci(0) and ci ) ; + i1_s1y: s1y_b(1) <= not( x_if_ci(1) and ci ) ; + i2_s1y: s1y_b(2) <= not( x_if_ci(2) and ci ) ; + i3_s1y: s1y_b(3) <= not( x_if_ci(3) and ci ) ; + i4_s1y: s1y_b(4) <= not( x_if_ci(4) and ci ) ; + i5_s1y: s1y_b(5) <= not( x_if_ci(5) and ci ) ; + i6_s1y: s1y_b(6) <= not( x_if_ci(6) and ci ) ; + i7_s1y: s1y_b(7) <= not( x_if_ci(7) and ci ) ; + + i0_s1: s1(0) <= not( s1x_b(0) and s1y_b(0) ); + i1_s1: s1(1) <= not( s1x_b(1) and s1y_b(1) ); + i2_s1: s1(2) <= not( s1x_b(2) and s1y_b(2) ); + i3_s1: s1(3) <= not( s1x_b(3) and s1y_b(3) ); + i4_s1: s1(4) <= not( s1x_b(4) and s1y_b(4) ); + i5_s1: s1(5) <= not( s1x_b(5) and s1y_b(5) ); + i6_s1: s1(6) <= not( s1x_b(6) and s1y_b(6) ); + i7_s1: s1(7) <= not( s1x_b(7) and s1y_b(7) ); + + i0_s0b: s0_b(0) <= not x_p(0) ; + i1_s0b: s0_b(1) <= not x_p(1) ; + i2_s0b: s0_b(2) <= not x_p(2) ; + i3_s0b: s0_b(3) <= not x_p(3) ; + i4_s0b: s0_b(4) <= not x_p(4) ; + i5_s0b: s0_b(5) <= not x_p(5) ; + i6_s0b: s0_b(6) <= not x_p(6) ; + i7_s0b: s0_b(7) <= not x_p(7) ; + + i0_s0: s0(0) <= not s0_b(0) ; + i1_s0: s0(1) <= not s0_b(1) ; + i2_s0: s0(2) <= not s0_b(2) ; + i3_s0: s0(3) <= not s0_b(3) ; + i4_s0: s0(4) <= not s0_b(4) ; + i5_s0: s0(5) <= not s0_b(5) ; + i6_s0: s0(6) <= not s0_b(6) ; + i7_s0: s0(7) <= not s0_b(7) ; + + + +END; + + + + + + + + + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_loc8inc_lsb.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_loc8inc_lsb.vhdl new file mode 100644 index 0000000..e84d37b --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_loc8inc_lsb.vhdl @@ -0,0 +1,103 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; use ieee.std_logic_1164.all ; +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + +entity fuq_loc8inc_lsb is port( + x :in std_ulogic_vector(0 to 4); + co_b :out std_ulogic; + s0 :out std_ulogic_vector(0 to 4); + s1 :out std_ulogic_vector(0 to 4) +); +END fuq_loc8inc_lsb; + +ARCHITECTURE fuq_loc8inc_lsb OF fuq_loc8inc_lsb IS + + signal x_b, t2_b, t4 :std_ulogic_vector(0 to 4); + + + + + + + + + +BEGIN + + + i0_xb: x_b(0) <= not x(0) ; + i1_xb: x_b(1) <= not x(1) ; + i2_xb: x_b(2) <= not x(2) ; + i3_xb: x_b(3) <= not x(3) ; + i4_xb: x_b(4) <= not x(4) ; + + + i0_t2: t2_b(0) <= not( x(0) ); + i1_t2: t2_b(1) <= not( x(1) and x(2) ); + i2_t2: t2_b(2) <= not( x(2) and x(3) ); + i3_t2: t2_b(3) <= not( x(3) and x(4) ); + i4_t2: t2_b(4) <= not( x(4) ); + + i0_t4: t4(0) <= not( t2_b(0) ); + i1_t4: t4(1) <= not( t2_b(1) or t2_b(3) ); + i2_t4: t4(2) <= not( t2_b(2) or t2_b(4) ); + i3_t4: t4(3) <= not( t2_b(3) ); + i4_t4: t4(4) <= not( t2_b(4) ); + + i0_t8: co_b <= not( t4(0) and t4(1) ); + + + i0_s0: s0(0) <= not( x_b(0) ); + i1_s0: s0(1) <= not( x_b(1) ); + i2_s0: s0(2) <= not( x_b(2) ); + i3_s0: s0(3) <= not( x_b(3) ); + i4_s0: s0(4) <= not( x_b(4) ); + + i0_s1: s1(0) <= not( x_b(0) xor t4(1) ); + i1_s1: s1(1) <= not( x_b(1) xor t4(2) ); + i2_s1: s1(2) <= not( x_b(2) xor t4(3) ); + i3_s1: s1(3) <= not( x_b(3) xor t4(4) ); + i4_s1: s1(4) <= not( t4(4) ); + + + + +END; + + + + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_lza.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_lza.vhdl new file mode 100644 index 0000000..b7e4de2 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_lza.vhdl @@ -0,0 +1,428 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + + +entity fuq_lza is +generic( expand_type: integer := 2 ); +port( + + vdd :inout power_logic; + gnd :inout power_logic; + clkoff_b :in std_ulogic; + act_dis :in std_ulogic; + flush :in std_ulogic; + delay_lclkr :in std_ulogic_vector(3 to 4); + mpw1_b :in std_ulogic_vector(3 to 4); + mpw2_b :in std_ulogic_vector(0 to 0); + sg_1 :in std_ulogic; + thold_1 :in std_ulogic; + fpu_enable :in std_ulogic; + nclk :in clk_logic; + + f_lza_si :in std_ulogic; + f_lza_so :out std_ulogic; + ex1_act_b :in std_ulogic; + + f_sa3_ex3_s :in std_ulogic_vector( 0 to 162); + f_sa3_ex3_c :in std_ulogic_vector(53 to 161); + f_alg_ex2_effsub_eac_b :in std_ulogic; + + f_lze_ex2_lzo_din :in std_ulogic_vector(0 to 162); + f_lze_ex3_sh_rgt_amt :in std_ulogic_vector(0 to 7); + f_lze_ex3_sh_rgt_en :in std_ulogic ; + + + f_lza_ex4_no_lza_edge :out std_ulogic; + f_lza_ex4_lza_amt :out std_ulogic_vector(0 to 7); + f_lza_ex4_lza_dcd64_cp1 :out std_ulogic_vector(0 to 2); + f_lza_ex4_lza_dcd64_cp2 :out std_ulogic_vector(0 to 1); + f_lza_ex4_lza_dcd64_cp3 :out std_ulogic_vector(0 to 0); + f_lza_ex4_sh_rgt_en :out std_ulogic; + f_lza_ex4_sh_rgt_en_eov :out std_ulogic; + f_lza_ex4_lza_amt_eov :out std_ulogic_vector(0 to 7) +); + + + +end fuq_lza; + +architecture fuq_lza of fuq_lza is + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal thold_0_b, thold_0, forcee :std_ulogic; + signal sg_0 :std_ulogic; + signal ex2_act :std_ulogic; + signal ex3_act :std_ulogic; + signal ex1_act :std_ulogic; + signal act_spare_unused :std_ulogic_vector(0 to 3); + signal act_so :std_ulogic_vector(0 to 5); + signal act_si :std_ulogic_vector(0 to 5); + signal ex3_lzo_so :std_ulogic_vector(0 to 162); + signal ex3_lzo_si :std_ulogic_vector(0 to 162); + signal ex3_sub_so :std_ulogic_vector(0 to 0); + signal ex3_sub_si :std_ulogic_vector(0 to 0); + signal ex4_amt_so :std_ulogic_vector(0 to 15); + signal ex4_amt_si :std_ulogic_vector(0 to 15); + signal ex4_dcd_so :std_ulogic_vector(0 to 8); + signal ex4_dcd_si :std_ulogic_vector(0 to 8); + signal ex3_lza_any_b :std_ulogic; + signal ex3_effsub :std_ulogic; + signal ex4_no_edge :std_ulogic; + signal ex3_no_edge_b :std_ulogic; + signal ex3_lzo :std_ulogic_vector(0 to 162); + signal ex3_lza_amt_b :std_ulogic_vector(0 to 7); + signal ex4_amt_eov :std_ulogic_vector(0 to 7); + signal ex4_amt :std_ulogic_vector(0 to 7); + signal ex3_sum :std_ulogic_vector(0 to 162); + signal ex3_car :std_ulogic_vector(53 to 162); + signal ex3_lv0_or :std_ulogic_vector(0 to 162); + signal ex3_sh_rgt_en_b :std_ulogic; + signal ex3_lv6_or_0_b , ex3_lv6_or_1_b , ex3_lv6_or_0_t , ex3_lv6_or_1_t :std_ulogic; + signal ex3_lza_dcd64_0_b , ex3_lza_dcd64_1_b , ex3_lza_dcd64_2_b :std_ulogic; + signal ex4_lza_dcd64_cp1 :std_ulogic_vector(0 to 2); + signal ex4_lza_dcd64_cp2 :std_ulogic_vector(0 to 1); + signal ex4_lza_dcd64_cp3 :std_ulogic_vector(0 to 0); + signal ex4_sh_rgt_en :std_ulogic; + signal ex4_sh_rgt_en_eov :std_ulogic; + signal ex2_effsub_eac, ex2_effsub_eac_b :std_ulogic; + signal ex3_lzo_b, ex3_lzo_l2_b :std_ulogic_vector(0 to 162); + signal ex3_lv6_or_0, ex3_lv6_or_1 :std_ulogic; + signal ex3_rgt_amt_b :std_ulogic_vector(0 to 7); + signal lza_ex4_d1clk , lza_ex4_d2clk :std_ulogic ; + signal lza_ex3_d1clk , lza_ex3_d2clk :std_ulogic ; + signal lza_ex4_lclk :clk_logic ; + signal lza_ex3_lclk :clk_logic ; + + + + + + + + +begin + + + + thold_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => thold_1, + q(0) => thold_0 ); + + sg_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => sg_1 , + q(0) => sg_0 ); + + + lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map ( + clkoff_b => clkoff_b, + thold => thold_0, + sg => sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => thold_0_b ); + + + + + ex1_act <= not ex1_act_b; + + act_lat: tri_rlmreg_p generic map (width=> 6, expand_type => expand_type, needs_sreset => 0) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(3) , + mpw1_b => mpw1_b(3) , + mpw2_b => mpw2_b(0) , + vd => vdd, + gd => gnd, + nclk => nclk, + act => fpu_enable, + thold_b => thold_0_b, + sg => sg_0, + scout => act_so , + scin => act_si , + din(0) => act_spare_unused(0), + din(1) => act_spare_unused(1), + din(2) => ex1_act, + din(3) => ex2_act, + din(4) => act_spare_unused(2), + din(5) => act_spare_unused(3), + dout(0) => act_spare_unused(0), + dout(1) => act_spare_unused(1), + dout(2) => ex2_act, + dout(3) => ex3_act, + dout(4) => act_spare_unused(2) , + dout(5) => act_spare_unused(3) ); + + + lza_ex3_lcb : tri_lcbnd generic map (expand_type => expand_type) port map( + delay_lclkr => delay_lclkr(3) , + mpw1_b => mpw1_b(3) , + mpw2_b => mpw2_b(0) , + forcee => forcee, + nclk => nclk , + vd => vdd , + gd => gnd , + act => ex2_act , + sg => sg_0 , + thold_b => thold_0_b , + d1clk => lza_ex3_d1clk , + d2clk => lza_ex3_d2clk , + lclk => lza_ex3_lclk ); + + lza_ex4_lcb : tri_lcbnd generic map (expand_type => expand_type) port map( + delay_lclkr => delay_lclkr(4) , + mpw1_b => mpw1_b(4) , + mpw2_b => mpw2_b(0) , + forcee => forcee, + nclk => nclk , + vd => vdd , + gd => gnd , + act => ex3_act , + sg => sg_0 , + thold_b => thold_0_b , + d1clk => lza_ex4_d1clk , + d2clk => lza_ex4_d2clk , + lclk => lza_ex4_lclk ); + + + + ex3_lzo_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 163, btr => "NLI0001_X1_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd , + gd => gnd , + LCLK => lza_ex3_lclk , + D1CLK => lza_ex3_d1clk , + D2CLK => lza_ex3_d2clk , + SCANIN => ex3_lzo_si , + SCANOUT => ex3_lzo_so , + D => f_lze_ex2_lzo_din(0 to 162), + QB => ex3_lzo_l2_b(0 to 162) ); + + + zobx: ex3_lzo (0 to 162) <= not ex3_lzo_l2_b(0 to 162); + zob: ex3_lzo_b(0 to 162) <= not ex3_lzo (0 to 162); + + ex2_effsub_eac <= not f_alg_ex2_effsub_eac_b ; + ex2_effsub_eac_b <= not ex2_effsub_eac ; + + ex3_sub_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 1, btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd , + gd => gnd , + LCLK => lza_ex3_lclk , + D1CLK => lza_ex3_d1clk , + D2CLK => lza_ex3_d2clk , + SCANIN(0) => ex3_sub_si(0) , + SCANOUT(0) => ex3_sub_so(0) , + D(0) => ex2_effsub_eac_b , + QB(0) => ex3_effsub ); + + + ex3_sum(0 to 52) <= f_sa3_ex3_s(0 to 52) ; + + + ex3_sum(53 to 162) <= f_sa3_ex3_s(53 to 162); + ex3_car(53 to 162) <= f_sa3_ex3_c(53 to 161) & tidn; + + + lzaej: entity work.fuq_lza_ej(fuq_lza_ej) port map( + effsub => ex3_effsub , + sum(0 to 162) => ex3_sum(0 to 162) , + car(53 to 162) => ex3_car(53 to 162) , + lzo_b(0 to 162) => ex3_lzo_b(0 to 162) , + edge(0 to 162) => ex3_lv0_or(0 to 162) ); + + + lzaclz: entity work.fuq_lza_clz(fuq_lza_clz) port map( + lv0_or(0 to 162) => ex3_lv0_or(0 to 162) , + lv6_or_0 => ex3_lv6_or_0 , + lv6_or_1 => ex3_lv6_or_1 , + lza_any_b => ex3_lza_any_b , + lza_amt_b(0 to 7) => ex3_lza_amt_b(0 to 7) ); + + + ex3_no_edge_b <= not ex3_lza_any_b ; + + + ex3_rgt_amt_b(0 to 7) <= not f_lze_ex3_sh_rgt_amt(0 to 7); + + + + ex3_sh_rgt_en_b <= not f_lze_ex3_sh_rgt_en ; + + +lzdz0b: ex3_lv6_or_0_b <= not ex3_lv6_or_0 ; +lzdz1b: ex3_lv6_or_1_b <= not ex3_lv6_or_1 ; +lzdz0t: ex3_lv6_or_0_t <= not ex3_lv6_or_0_b ; +lzdz1t: ex3_lv6_or_1_t <= not ex3_lv6_or_1_b ; + +lzd0b: ex3_lza_dcd64_0_b <= not(ex3_lv6_or_0_t and ex3_sh_rgt_en_b); +lzd1b: ex3_lza_dcd64_1_b <= not(ex3_lv6_or_0_b and ex3_lv6_or_1_t and ex3_sh_rgt_en_b); +lzd2b: ex3_lza_dcd64_2_b <= not(ex3_lv6_or_0_b and ex3_lv6_or_1_b and ex3_sh_rgt_en_b); + + + + + + + ex4_dcd_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 9, btr => "NLI0001_X2_A12TH" , expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd , + gd => gnd , + LCLK => lza_ex4_lclk , + D1CLK => lza_ex4_d1clk , + D2CLK => lza_ex4_d2clk , + SCANIN => ex4_dcd_si(0 to 8) , + SCANOUT => ex4_dcd_so(0 to 8) , + D( 0) => ex3_lza_dcd64_0_b , + D( 1) => ex3_lza_dcd64_0_b , + D( 2) => ex3_lza_dcd64_0_b , + D( 3) => ex3_lza_dcd64_1_b , + D( 4) => ex3_lza_dcd64_1_b , + D( 5) => ex3_lza_dcd64_2_b , + D( 6) => ex3_sh_rgt_en_b , + D( 7) => ex3_sh_rgt_en_b , + D( 8) => ex3_no_edge_b , + QB( 0) => ex4_lza_dcd64_cp1(0), + QB( 1) => ex4_lza_dcd64_cp2(0), + QB( 2) => ex4_lza_dcd64_cp3(0), + QB( 3) => ex4_lza_dcd64_cp1(1), + QB( 4) => ex4_lza_dcd64_cp2(1), + QB( 5) => ex4_lza_dcd64_cp1(2), + QB( 6) => ex4_sh_rgt_en , + QB( 7) => ex4_sh_rgt_en_eov , + QB( 8) => ex4_no_edge ); + + + ex4_amt_lat: entity tri.tri_nand2_nlats(tri_nand2_nlats) generic map (width=> 16, btr => "NLA0001_X1_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd , + gd => gnd , + LCLK => lza_ex4_lclk , + D1CLK => lza_ex4_d1clk , + D2CLK => lza_ex4_d2clk , + SCANIN => ex4_amt_si(0 to 15) , + SCANOUT => ex4_amt_so(0 to 15) , + A1( 0) => ex3_lza_amt_b(0) , + A1( 1) => ex3_lza_amt_b(0) , + A1( 2) => ex3_lza_amt_b(1) , + A1( 3) => ex3_lza_amt_b(1) , + A1( 4) => ex3_lza_amt_b(2) , + A1( 5) => ex3_lza_amt_b(2) , + A1( 6) => ex3_lza_amt_b(3) , + A1( 7) => ex3_lza_amt_b(3) , + A1( 8) => ex3_lza_amt_b(4) , + A1( 9) => ex3_lza_amt_b(4) , + A1(10) => ex3_lza_amt_b(5) , + A1(11) => ex3_lza_amt_b(5) , + A1(12) => ex3_lza_amt_b(6) , + A1(13) => ex3_lza_amt_b(6) , + A1(14) => ex3_lza_amt_b(7) , + A1(15) => ex3_lza_amt_b(7) , + + A2( 0) => ex3_rgt_amt_b(0) , + A2( 1) => ex3_rgt_amt_b(0) , + A2( 2) => ex3_rgt_amt_b(1) , + A2( 3) => ex3_rgt_amt_b(1) , + A2( 4) => ex3_rgt_amt_b(2) , + A2( 5) => ex3_rgt_amt_b(2) , + A2( 6) => ex3_rgt_amt_b(3) , + A2( 7) => ex3_rgt_amt_b(3) , + A2( 8) => ex3_rgt_amt_b(4) , + A2( 9) => ex3_rgt_amt_b(4) , + A2(10) => ex3_rgt_amt_b(5) , + A2(11) => ex3_rgt_amt_b(5) , + A2(12) => ex3_rgt_amt_b(6) , + A2(13) => ex3_rgt_amt_b(6) , + A2(14) => ex3_rgt_amt_b(7) , + A2(15) => ex3_rgt_amt_b(7) , + + QB( 0) => ex4_amt(0) , + QB( 1) => ex4_amt_eov(0) , + QB( 2) => ex4_amt(1) , + QB( 3) => ex4_amt_eov(1) , + QB( 4) => ex4_amt(2) , + QB( 5) => ex4_amt_eov(2) , + QB( 6) => ex4_amt(3) , + QB( 7) => ex4_amt_eov(3) , + QB( 8) => ex4_amt(4) , + QB( 9) => ex4_amt_eov(4) , + QB(10) => ex4_amt(5) , + QB(11) => ex4_amt_eov(5) , + QB(12) => ex4_amt(6) , + QB(13) => ex4_amt_eov(6) , + QB(14) => ex4_amt(7) , + QB(15) => ex4_amt_eov(7) ); + + + + + f_lza_ex4_sh_rgt_en <= ex4_sh_rgt_en ; + f_lza_ex4_sh_rgt_en_eov <= ex4_sh_rgt_en_eov ; + + f_lza_ex4_lza_amt <= ex4_amt(0 to 7) ; + + f_lza_ex4_lza_dcd64_cp1(0 to 2) <= ex4_lza_dcd64_cp1(0 to 2); + f_lza_ex4_lza_dcd64_cp2(0 to 1) <= ex4_lza_dcd64_cp2(0 to 1); + f_lza_ex4_lza_dcd64_cp3(0) <= ex4_lza_dcd64_cp3(0) ; + + + f_lza_ex4_lza_amt_eov <= ex4_amt_eov(0 to 7) ; + f_lza_ex4_no_lza_edge <= ex4_no_edge ; + + + ex3_lzo_si (0 to 162) <= ex3_lzo_so (1 to 162) & f_lza_si ; + ex3_sub_si (0) <= ex3_lzo_so (0); + ex4_amt_si (0 to 15) <= ex4_amt_so (1 to 15) & ex3_sub_so (0); + ex4_dcd_si (0 to 8) <= ex4_dcd_so (1 to 8) & ex4_amt_so (0); + act_si (0 to 5) <= act_so (1 to 5) & ex4_dcd_so (0); + f_lza_so <= act_so (0); + + + +end; + + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_lza_clz.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_lza_clz.vhdl new file mode 100644 index 0000000..9ad1640 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_lza_clz.vhdl @@ -0,0 +1,979 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; use ieee.std_logic_1164.all ; +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + +entity fuq_lza_clz is port( + lv0_or :in std_ulogic_vector(0 to 162); + lv6_or_0 :out std_ulogic; + lv6_or_1 :out std_ulogic; + lza_any_b :out std_ulogic ; + lza_amt_b :out std_ulogic_vector(0 to 7) + ); +END fuq_lza_clz; + + +ARCHITECTURE fuq_lza_clz OF fuq_lza_clz IS + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal lv1_or_b :std_ulogic_vector(0 to 81); + signal lv1_inv_b :std_ulogic_vector(0 to 81); + signal lv1_enc7_b :std_ulogic_vector(0 to 81); + + signal lv2_or :std_ulogic_vector(0 to 40); + signal lv2_inv :std_ulogic_vector(0 to 40); + signal lv2_enc6 :std_ulogic_vector(0 to 40); + signal lv2_enc7 :std_ulogic_vector(0 to 40); + + signal lv3_or_b :std_ulogic_vector(0 to 20); + signal lv3_inv_b :std_ulogic_vector(0 to 20); + signal lv3_enc5_b :std_ulogic_vector(0 to 20); + signal lv3_enc6_b :std_ulogic_vector(0 to 20); + signal lv3_enc7_b :std_ulogic_vector(0 to 20); + + signal lv4_or :std_ulogic_vector(0 to 10); + signal lv4_inv :std_ulogic_vector(0 to 10); + signal lv4_enc4 :std_ulogic_vector(0 to 10); + signal lv4_enc5 :std_ulogic_vector(0 to 10); + signal lv4_enc6 :std_ulogic_vector(0 to 10); + signal lv4_enc7 :std_ulogic_vector(0 to 10); + + signal lv4_or_b :std_ulogic_vector(0 to 10); + signal lv4_enc4_b :std_ulogic_vector(0 to 10); + signal lv4_enc5_b :std_ulogic_vector(0 to 10); + signal lv4_enc6_b :std_ulogic_vector(0 to 10); + signal lv4_enc7_b :std_ulogic_vector(0 to 10); + + + signal lv5_or :std_ulogic_vector(0 to 5); + signal lv5_inv :std_ulogic_vector(0 to 5); + signal lv5_enc3 :std_ulogic_vector(0 to 5); + signal lv5_enc4 :std_ulogic_vector(0 to 5); + signal lv5_enc5 :std_ulogic_vector(0 to 5); + signal lv5_enc6 :std_ulogic_vector(0 to 5); + signal lv5_enc7 :std_ulogic_vector(0 to 5); + + signal lv6_or_b :std_ulogic_vector(0 to 2); + signal lv6_inv_b :std_ulogic_vector(0 to 2); + signal lv6_enc2_b :std_ulogic_vector(0 to 2); + signal lv6_enc3_b :std_ulogic_vector(0 to 2); + signal lv6_enc4_b :std_ulogic_vector(0 to 2); + signal lv6_enc5_b :std_ulogic_vector(0 to 2); + signal lv6_enc6_b :std_ulogic_vector(0 to 2); + signal lv6_enc7_b :std_ulogic_vector(0 to 2); + + signal lv7_or :std_ulogic_vector(0 to 1); + signal lv7_inv :std_ulogic_vector(0 to 1); + signal lv7_enc1 :std_ulogic_vector(0 to 1); + signal lv7_enc2 :std_ulogic_vector(0 to 1); + signal lv7_enc3 :std_ulogic_vector(0 to 1); + signal lv7_enc4 :std_ulogic_vector(0 to 1); + signal lv7_enc5 :std_ulogic_vector(0 to 1); + signal lv7_enc6 :std_ulogic_vector(0 to 1); + signal lv7_enc7 :std_ulogic_vector(0 to 1); + + signal lv8_or_b :std_ulogic_vector(0 to 0); + signal lv8_inv_b :std_ulogic_vector(0 to 0); + signal lv8_enc0_b :std_ulogic_vector(0 to 0); + signal lv8_enc1_b :std_ulogic_vector(0 to 0); + signal lv8_enc2_b :std_ulogic_vector(0 to 0); + signal lv8_enc3_b :std_ulogic_vector(0 to 0); + signal lv8_enc4_b :std_ulogic_vector(0 to 0); + signal lv8_enc5_b :std_ulogic_vector(0 to 0); + signal lv8_enc6_b :std_ulogic_vector(0 to 0); + signal lv8_enc7_b :std_ulogic_vector(0 to 0); + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +BEGIN + + + b000_002_any: lv1_or_b(0) <= not( lv0_or(0) or lv0_or(1) ); + b001_002_any: lv1_or_b(1) <= not( lv0_or(2) or lv0_or(3) ); + b002_002_any: lv1_or_b(2) <= not( lv0_or(4) or lv0_or(5) ); + b003_002_any: lv1_or_b(3) <= not( lv0_or(6) or lv0_or(7) ); + b004_002_any: lv1_or_b(4) <= not( lv0_or(8) or lv0_or(9) ); + b005_002_any: lv1_or_b(5) <= not( lv0_or(10) or lv0_or(11) ); + b006_002_any: lv1_or_b(6) <= not( lv0_or(12) or lv0_or(13) ); + b007_002_any: lv1_or_b(7) <= not( lv0_or(14) or lv0_or(15) ); + b008_002_any: lv1_or_b(8) <= not( lv0_or(16) or lv0_or(17) ); + b009_002_any: lv1_or_b(9) <= not( lv0_or(18) or lv0_or(19) ); + b010_002_any: lv1_or_b(10) <= not( lv0_or(20) or lv0_or(21) ); + b011_002_any: lv1_or_b(11) <= not( lv0_or(22) or lv0_or(23) ); + b012_002_any: lv1_or_b(12) <= not( lv0_or(24) or lv0_or(25) ); + b013_002_any: lv1_or_b(13) <= not( lv0_or(26) or lv0_or(27) ); + b014_002_any: lv1_or_b(14) <= not( lv0_or(28) or lv0_or(29) ); + b015_002_any: lv1_or_b(15) <= not( lv0_or(30) or lv0_or(31) ); + b016_002_any: lv1_or_b(16) <= not( lv0_or(32) or lv0_or(33) ); + b017_002_any: lv1_or_b(17) <= not( lv0_or(34) or lv0_or(35) ); + b018_002_any: lv1_or_b(18) <= not( lv0_or(36) or lv0_or(37) ); + b019_002_any: lv1_or_b(19) <= not( lv0_or(38) or lv0_or(39) ); + b020_002_any: lv1_or_b(20) <= not( lv0_or(40) or lv0_or(41) ); + b021_002_any: lv1_or_b(21) <= not( lv0_or(42) or lv0_or(43) ); + b022_002_any: lv1_or_b(22) <= not( lv0_or(44) or lv0_or(45) ); + b023_002_any: lv1_or_b(23) <= not( lv0_or(46) or lv0_or(47) ); + b024_002_any: lv1_or_b(24) <= not( lv0_or(48) or lv0_or(49) ); + b025_002_any: lv1_or_b(25) <= not( lv0_or(50) or lv0_or(51) ); + b026_002_any: lv1_or_b(26) <= not( lv0_or(52) or lv0_or(53) ); + b027_002_any: lv1_or_b(27) <= not( lv0_or(54) or lv0_or(55) ); + b028_002_any: lv1_or_b(28) <= not( lv0_or(56) or lv0_or(57) ); + b029_002_any: lv1_or_b(29) <= not( lv0_or(58) or lv0_or(59) ); + b030_002_any: lv1_or_b(30) <= not( lv0_or(60) or lv0_or(61) ); + b031_002_any: lv1_or_b(31) <= not( lv0_or(62) or lv0_or(63) ); + b032_002_any: lv1_or_b(32) <= not( lv0_or(64) or lv0_or(65) ); + b033_002_any: lv1_or_b(33) <= not( lv0_or(66) or lv0_or(67) ); + b034_002_any: lv1_or_b(34) <= not( lv0_or(68) or lv0_or(69) ); + b035_002_any: lv1_or_b(35) <= not( lv0_or(70) or lv0_or(71) ); + b036_002_any: lv1_or_b(36) <= not( lv0_or(72) or lv0_or(73) ); + b037_002_any: lv1_or_b(37) <= not( lv0_or(74) or lv0_or(75) ); + b038_002_any: lv1_or_b(38) <= not( lv0_or(76) or lv0_or(77) ); + b039_002_any: lv1_or_b(39) <= not( lv0_or(78) or lv0_or(79) ); + b040_002_any: lv1_or_b(40) <= not( lv0_or(80) or lv0_or(81) ); + b041_002_any: lv1_or_b(41) <= not( lv0_or(82) or lv0_or(83) ); + b042_002_any: lv1_or_b(42) <= not( lv0_or(84) or lv0_or(85) ); + b043_002_any: lv1_or_b(43) <= not( lv0_or(86) or lv0_or(87) ); + b044_002_any: lv1_or_b(44) <= not( lv0_or(88) or lv0_or(89) ); + b045_002_any: lv1_or_b(45) <= not( lv0_or(90) or lv0_or(91) ); + b046_002_any: lv1_or_b(46) <= not( lv0_or(92) or lv0_or(93) ); + b047_002_any: lv1_or_b(47) <= not( lv0_or(94) or lv0_or(95) ); + b048_002_any: lv1_or_b(48) <= not( lv0_or(96) or lv0_or(97) ); + b049_002_any: lv1_or_b(49) <= not( lv0_or(98) or lv0_or(99) ); + b050_002_any: lv1_or_b(50) <= not( lv0_or(100) or lv0_or(101) ); + b051_002_any: lv1_or_b(51) <= not( lv0_or(102) or lv0_or(103) ); + b052_002_any: lv1_or_b(52) <= not( lv0_or(104) or lv0_or(105) ); + b053_002_any: lv1_or_b(53) <= not( lv0_or(106) or lv0_or(107) ); + b054_002_any: lv1_or_b(54) <= not( lv0_or(108) or lv0_or(109) ); + b055_002_any: lv1_or_b(55) <= not( lv0_or(110) or lv0_or(111) ); + b056_002_any: lv1_or_b(56) <= not( lv0_or(112) or lv0_or(113) ); + b057_002_any: lv1_or_b(57) <= not( lv0_or(114) or lv0_or(115) ); + b058_002_any: lv1_or_b(58) <= not( lv0_or(116) or lv0_or(117) ); + b059_002_any: lv1_or_b(59) <= not( lv0_or(118) or lv0_or(119) ); + b060_002_any: lv1_or_b(60) <= not( lv0_or(120) or lv0_or(121) ); + b061_002_any: lv1_or_b(61) <= not( lv0_or(122) or lv0_or(123) ); + b062_002_any: lv1_or_b(62) <= not( lv0_or(124) or lv0_or(125) ); + b063_002_any: lv1_or_b(63) <= not( lv0_or(126) or lv0_or(127) ); + b064_002_any: lv1_or_b(64) <= not( lv0_or(128) or lv0_or(129) ); + b065_002_any: lv1_or_b(65) <= not( lv0_or(130) or lv0_or(131) ); + b066_002_any: lv1_or_b(66) <= not( lv0_or(132) or lv0_or(133) ); + b067_002_any: lv1_or_b(67) <= not( lv0_or(134) or lv0_or(135) ); + b068_002_any: lv1_or_b(68) <= not( lv0_or(136) or lv0_or(137) ); + b069_002_any: lv1_or_b(69) <= not( lv0_or(138) or lv0_or(139) ); + b070_002_any: lv1_or_b(70) <= not( lv0_or(140) or lv0_or(141) ); + b071_002_any: lv1_or_b(71) <= not( lv0_or(142) or lv0_or(143) ); + b072_002_any: lv1_or_b(72) <= not( lv0_or(144) or lv0_or(145) ); + b073_002_any: lv1_or_b(73) <= not( lv0_or(146) or lv0_or(147) ); + b074_002_any: lv1_or_b(74) <= not( lv0_or(148) or lv0_or(149) ); + b075_002_any: lv1_or_b(75) <= not( lv0_or(150) or lv0_or(151) ); + b076_002_any: lv1_or_b(76) <= not( lv0_or(152) or lv0_or(153) ); + b077_002_any: lv1_or_b(77) <= not( lv0_or(154) or lv0_or(155) ); + b078_002_any: lv1_or_b(78) <= not( lv0_or(156) or lv0_or(157) ); + b079_002_any: lv1_or_b(79) <= not( lv0_or(158) or lv0_or(159) ); + b080_002_any: lv1_or_b(80) <= not( lv0_or(160) or lv0_or(161) ); + b081_002_any: lv1_or_b(81) <= not( lv0_or(162) ); + + b000_002_inv: lv1_inv_b(0) <= not( lv0_or(0) ); + b001_002_inv: lv1_inv_b(1) <= not( lv0_or(2) ); + b002_002_inv: lv1_inv_b(2) <= not( lv0_or(4) ); + b003_002_inv: lv1_inv_b(3) <= not( lv0_or(6) ); + b004_002_inv: lv1_inv_b(4) <= not( lv0_or(8) ); + b005_002_inv: lv1_inv_b(5) <= not( lv0_or(10) ); + b006_002_inv: lv1_inv_b(6) <= not( lv0_or(12) ); + b007_002_inv: lv1_inv_b(7) <= not( lv0_or(14) ); + b008_002_inv: lv1_inv_b(8) <= not( lv0_or(16) ); + b009_002_inv: lv1_inv_b(9) <= not( lv0_or(18) ); + b010_002_inv: lv1_inv_b(10) <= not( lv0_or(20) ); + b011_002_inv: lv1_inv_b(11) <= not( lv0_or(22) ); + b012_002_inv: lv1_inv_b(12) <= not( lv0_or(24) ); + b013_002_inv: lv1_inv_b(13) <= not( lv0_or(26) ); + b014_002_inv: lv1_inv_b(14) <= not( lv0_or(28) ); + b015_002_inv: lv1_inv_b(15) <= not( lv0_or(30) ); + b016_002_inv: lv1_inv_b(16) <= not( lv0_or(32) ); + b017_002_inv: lv1_inv_b(17) <= not( lv0_or(34) ); + b018_002_inv: lv1_inv_b(18) <= not( lv0_or(36) ); + b019_002_inv: lv1_inv_b(19) <= not( lv0_or(38) ); + b020_002_inv: lv1_inv_b(20) <= not( lv0_or(40) ); + b021_002_inv: lv1_inv_b(21) <= not( lv0_or(42) ); + b022_002_inv: lv1_inv_b(22) <= not( lv0_or(44) ); + b023_002_inv: lv1_inv_b(23) <= not( lv0_or(46) ); + b024_002_inv: lv1_inv_b(24) <= not( lv0_or(48) ); + b025_002_inv: lv1_inv_b(25) <= not( lv0_or(50) ); + b026_002_inv: lv1_inv_b(26) <= not( lv0_or(52) ); + b027_002_inv: lv1_inv_b(27) <= not( lv0_or(54) ); + b028_002_inv: lv1_inv_b(28) <= not( lv0_or(56) ); + b029_002_inv: lv1_inv_b(29) <= not( lv0_or(58) ); + b030_002_inv: lv1_inv_b(30) <= not( lv0_or(60) ); + b031_002_inv: lv1_inv_b(31) <= not( lv0_or(62) ); + b032_002_inv: lv1_inv_b(32) <= not( lv0_or(64) ); + b033_002_inv: lv1_inv_b(33) <= not( lv0_or(66) ); + b034_002_inv: lv1_inv_b(34) <= not( lv0_or(68) ); + b035_002_inv: lv1_inv_b(35) <= not( lv0_or(70) ); + b036_002_inv: lv1_inv_b(36) <= not( lv0_or(72) ); + b037_002_inv: lv1_inv_b(37) <= not( lv0_or(74) ); + b038_002_inv: lv1_inv_b(38) <= not( lv0_or(76) ); + b039_002_inv: lv1_inv_b(39) <= not( lv0_or(78) ); + b040_002_inv: lv1_inv_b(40) <= not( lv0_or(80) ); + b041_002_inv: lv1_inv_b(41) <= not( lv0_or(82) ); + b042_002_inv: lv1_inv_b(42) <= not( lv0_or(84) ); + b043_002_inv: lv1_inv_b(43) <= not( lv0_or(86) ); + b044_002_inv: lv1_inv_b(44) <= not( lv0_or(88) ); + b045_002_inv: lv1_inv_b(45) <= not( lv0_or(90) ); + b046_002_inv: lv1_inv_b(46) <= not( lv0_or(92) ); + b047_002_inv: lv1_inv_b(47) <= not( lv0_or(94) ); + b048_002_inv: lv1_inv_b(48) <= not( lv0_or(96) ); + b049_002_inv: lv1_inv_b(49) <= not( lv0_or(98) ); + b050_002_inv: lv1_inv_b(50) <= not( lv0_or(100) ); + b051_002_inv: lv1_inv_b(51) <= not( lv0_or(102) ); + b052_002_inv: lv1_inv_b(52) <= not( lv0_or(104) ); + b053_002_inv: lv1_inv_b(53) <= not( lv0_or(106) ); + b054_002_inv: lv1_inv_b(54) <= not( lv0_or(108) ); + b055_002_inv: lv1_inv_b(55) <= not( lv0_or(110) ); + b056_002_inv: lv1_inv_b(56) <= not( lv0_or(112) ); + b057_002_inv: lv1_inv_b(57) <= not( lv0_or(114) ); + b058_002_inv: lv1_inv_b(58) <= not( lv0_or(116) ); + b059_002_inv: lv1_inv_b(59) <= not( lv0_or(118) ); + b060_002_inv: lv1_inv_b(60) <= not( lv0_or(120) ); + b061_002_inv: lv1_inv_b(61) <= not( lv0_or(122) ); + b062_002_inv: lv1_inv_b(62) <= not( lv0_or(124) ); + b063_002_inv: lv1_inv_b(63) <= not( lv0_or(126) ); + b064_002_inv: lv1_inv_b(64) <= not( lv0_or(128) ); + b065_002_inv: lv1_inv_b(65) <= not( lv0_or(130) ); + b066_002_inv: lv1_inv_b(66) <= not( lv0_or(132) ); + b067_002_inv: lv1_inv_b(67) <= not( lv0_or(134) ); + b068_002_inv: lv1_inv_b(68) <= not( lv0_or(136) ); + b069_002_inv: lv1_inv_b(69) <= not( lv0_or(138) ); + b070_002_inv: lv1_inv_b(70) <= not( lv0_or(140) ); + b071_002_inv: lv1_inv_b(71) <= not( lv0_or(142) ); + b072_002_inv: lv1_inv_b(72) <= not( lv0_or(144) ); + b073_002_inv: lv1_inv_b(73) <= not( lv0_or(146) ); + b074_002_inv: lv1_inv_b(74) <= not( lv0_or(148) ); + b075_002_inv: lv1_inv_b(75) <= not( lv0_or(150) ); + b076_002_inv: lv1_inv_b(76) <= not( lv0_or(152) ); + b077_002_inv: lv1_inv_b(77) <= not( lv0_or(154) ); + b078_002_inv: lv1_inv_b(78) <= not( lv0_or(156) ); + b079_002_inv: lv1_inv_b(79) <= not( lv0_or(158) ); + b080_002_inv: lv1_inv_b(80) <= not( lv0_or(160) ); + b081_002_inv: lv1_inv_b(81) <= not( lv0_or(162) ); + + b000_002_enc7: lv1_enc7_b(0) <= not( lv1_inv_b(0) and lv0_or(1) ); + b001_002_enc7: lv1_enc7_b(1) <= not( lv1_inv_b(1) and lv0_or(3) ); + b002_002_enc7: lv1_enc7_b(2) <= not( lv1_inv_b(2) and lv0_or(5) ); + b003_002_enc7: lv1_enc7_b(3) <= not( lv1_inv_b(3) and lv0_or(7) ); + b004_002_enc7: lv1_enc7_b(4) <= not( lv1_inv_b(4) and lv0_or(9) ); + b005_002_enc7: lv1_enc7_b(5) <= not( lv1_inv_b(5) and lv0_or(11) ); + b006_002_enc7: lv1_enc7_b(6) <= not( lv1_inv_b(6) and lv0_or(13) ); + b007_002_enc7: lv1_enc7_b(7) <= not( lv1_inv_b(7) and lv0_or(15) ); + b008_002_enc7: lv1_enc7_b(8) <= not( lv1_inv_b(8) and lv0_or(17) ); + b009_002_enc7: lv1_enc7_b(9) <= not( lv1_inv_b(9) and lv0_or(19) ); + b010_002_enc7: lv1_enc7_b(10) <= not( lv1_inv_b(10) and lv0_or(21) ); + b011_002_enc7: lv1_enc7_b(11) <= not( lv1_inv_b(11) and lv0_or(23) ); + b012_002_enc7: lv1_enc7_b(12) <= not( lv1_inv_b(12) and lv0_or(25) ); + b013_002_enc7: lv1_enc7_b(13) <= not( lv1_inv_b(13) and lv0_or(27) ); + b014_002_enc7: lv1_enc7_b(14) <= not( lv1_inv_b(14) and lv0_or(29) ); + b015_002_enc7: lv1_enc7_b(15) <= not( lv1_inv_b(15) and lv0_or(31) ); + b016_002_enc7: lv1_enc7_b(16) <= not( lv1_inv_b(16) and lv0_or(33) ); + b017_002_enc7: lv1_enc7_b(17) <= not( lv1_inv_b(17) and lv0_or(35) ); + b018_002_enc7: lv1_enc7_b(18) <= not( lv1_inv_b(18) and lv0_or(37) ); + b019_002_enc7: lv1_enc7_b(19) <= not( lv1_inv_b(19) and lv0_or(39) ); + b020_002_enc7: lv1_enc7_b(20) <= not( lv1_inv_b(20) and lv0_or(41) ); + b021_002_enc7: lv1_enc7_b(21) <= not( lv1_inv_b(21) and lv0_or(43) ); + b022_002_enc7: lv1_enc7_b(22) <= not( lv1_inv_b(22) and lv0_or(45) ); + b023_002_enc7: lv1_enc7_b(23) <= not( lv1_inv_b(23) and lv0_or(47) ); + b024_002_enc7: lv1_enc7_b(24) <= not( lv1_inv_b(24) and lv0_or(49) ); + b025_002_enc7: lv1_enc7_b(25) <= not( lv1_inv_b(25) and lv0_or(51) ); + b026_002_enc7: lv1_enc7_b(26) <= not( lv1_inv_b(26) and lv0_or(53) ); + b027_002_enc7: lv1_enc7_b(27) <= not( lv1_inv_b(27) and lv0_or(55) ); + b028_002_enc7: lv1_enc7_b(28) <= not( lv1_inv_b(28) and lv0_or(57) ); + b029_002_enc7: lv1_enc7_b(29) <= not( lv1_inv_b(29) and lv0_or(59) ); + b030_002_enc7: lv1_enc7_b(30) <= not( lv1_inv_b(30) and lv0_or(61) ); + b031_002_enc7: lv1_enc7_b(31) <= not( lv1_inv_b(31) and lv0_or(63) ); + b032_002_enc7: lv1_enc7_b(32) <= not( lv1_inv_b(32) and lv0_or(65) ); + b033_002_enc7: lv1_enc7_b(33) <= not( lv1_inv_b(33) and lv0_or(67) ); + b034_002_enc7: lv1_enc7_b(34) <= not( lv1_inv_b(34) and lv0_or(69) ); + b035_002_enc7: lv1_enc7_b(35) <= not( lv1_inv_b(35) and lv0_or(71) ); + b036_002_enc7: lv1_enc7_b(36) <= not( lv1_inv_b(36) and lv0_or(73) ); + b037_002_enc7: lv1_enc7_b(37) <= not( lv1_inv_b(37) and lv0_or(75) ); + b038_002_enc7: lv1_enc7_b(38) <= not( lv1_inv_b(38) and lv0_or(77) ); + b039_002_enc7: lv1_enc7_b(39) <= not( lv1_inv_b(39) and lv0_or(79) ); + b040_002_enc7: lv1_enc7_b(40) <= not( lv1_inv_b(40) and lv0_or(81) ); + b041_002_enc7: lv1_enc7_b(41) <= not( lv1_inv_b(41) and lv0_or(83) ); + b042_002_enc7: lv1_enc7_b(42) <= not( lv1_inv_b(42) and lv0_or(85) ); + b043_002_enc7: lv1_enc7_b(43) <= not( lv1_inv_b(43) and lv0_or(87) ); + b044_002_enc7: lv1_enc7_b(44) <= not( lv1_inv_b(44) and lv0_or(89) ); + b045_002_enc7: lv1_enc7_b(45) <= not( lv1_inv_b(45) and lv0_or(91) ); + b046_002_enc7: lv1_enc7_b(46) <= not( lv1_inv_b(46) and lv0_or(93) ); + b047_002_enc7: lv1_enc7_b(47) <= not( lv1_inv_b(47) and lv0_or(95) ); + b048_002_enc7: lv1_enc7_b(48) <= not( lv1_inv_b(48) and lv0_or(97) ); + b049_002_enc7: lv1_enc7_b(49) <= not( lv1_inv_b(49) and lv0_or(99) ); + b050_002_enc7: lv1_enc7_b(50) <= not( lv1_inv_b(50) and lv0_or(101) ); + b051_002_enc7: lv1_enc7_b(51) <= not( lv1_inv_b(51) and lv0_or(103) ); + b052_002_enc7: lv1_enc7_b(52) <= not( lv1_inv_b(52) and lv0_or(105) ); + b053_002_enc7: lv1_enc7_b(53) <= not( lv1_inv_b(53) and lv0_or(107) ); + b054_002_enc7: lv1_enc7_b(54) <= not( lv1_inv_b(54) and lv0_or(109) ); + b055_002_enc7: lv1_enc7_b(55) <= not( lv1_inv_b(55) and lv0_or(111) ); + b056_002_enc7: lv1_enc7_b(56) <= not( lv1_inv_b(56) and lv0_or(113) ); + b057_002_enc7: lv1_enc7_b(57) <= not( lv1_inv_b(57) and lv0_or(115) ); + b058_002_enc7: lv1_enc7_b(58) <= not( lv1_inv_b(58) and lv0_or(117) ); + b059_002_enc7: lv1_enc7_b(59) <= not( lv1_inv_b(59) and lv0_or(119) ); + b060_002_enc7: lv1_enc7_b(60) <= not( lv1_inv_b(60) and lv0_or(121) ); + b061_002_enc7: lv1_enc7_b(61) <= not( lv1_inv_b(61) and lv0_or(123) ); + b062_002_enc7: lv1_enc7_b(62) <= not( lv1_inv_b(62) and lv0_or(125) ); + b063_002_enc7: lv1_enc7_b(63) <= not( lv1_inv_b(63) and lv0_or(127) ); + b064_002_enc7: lv1_enc7_b(64) <= not( lv1_inv_b(64) and lv0_or(129) ); + b065_002_enc7: lv1_enc7_b(65) <= not( lv1_inv_b(65) and lv0_or(131) ); + b066_002_enc7: lv1_enc7_b(66) <= not( lv1_inv_b(66) and lv0_or(133) ); + b067_002_enc7: lv1_enc7_b(67) <= not( lv1_inv_b(67) and lv0_or(135) ); + b068_002_enc7: lv1_enc7_b(68) <= not( lv1_inv_b(68) and lv0_or(137) ); + b069_002_enc7: lv1_enc7_b(69) <= not( lv1_inv_b(69) and lv0_or(139) ); + b070_002_enc7: lv1_enc7_b(70) <= not( lv1_inv_b(70) and lv0_or(141) ); + b071_002_enc7: lv1_enc7_b(71) <= not( lv1_inv_b(71) and lv0_or(143) ); + b072_002_enc7: lv1_enc7_b(72) <= not( lv1_inv_b(72) and lv0_or(145) ); + b073_002_enc7: lv1_enc7_b(73) <= not( lv1_inv_b(73) and lv0_or(147) ); + b074_002_enc7: lv1_enc7_b(74) <= not( lv1_inv_b(74) and lv0_or(149) ); + b075_002_enc7: lv1_enc7_b(75) <= not( lv1_inv_b(75) and lv0_or(151) ); + b076_002_enc7: lv1_enc7_b(76) <= not( lv1_inv_b(76) and lv0_or(153) ); + b077_002_enc7: lv1_enc7_b(77) <= not( lv1_inv_b(77) and lv0_or(155) ); + b078_002_enc7: lv1_enc7_b(78) <= not( lv1_inv_b(78) and lv0_or(157) ); + b079_002_enc7: lv1_enc7_b(79) <= not( lv1_inv_b(79) and lv0_or(159) ); + b080_002_enc7: lv1_enc7_b(80) <= not( lv1_inv_b(80) and lv0_or(161) ); + b081_002_enc7: lv1_enc7_b(81) <= not( lv1_inv_b(81) ); + + + + b000_004_any: lv2_or(0) <= not( lv1_or_b(0) and lv1_or_b(1) ); + b001_004_any: lv2_or(1) <= not( lv1_or_b(2) and lv1_or_b(3) ); + b002_004_any: lv2_or(2) <= not( lv1_or_b(4) and lv1_or_b(5) ); + b003_004_any: lv2_or(3) <= not( lv1_or_b(6) and lv1_or_b(7) ); + b004_004_any: lv2_or(4) <= not( lv1_or_b(8) and lv1_or_b(9) ); + b005_004_any: lv2_or(5) <= not( lv1_or_b(10) and lv1_or_b(11) ); + b006_004_any: lv2_or(6) <= not( lv1_or_b(12) and lv1_or_b(13) ); + b007_004_any: lv2_or(7) <= not( lv1_or_b(14) and lv1_or_b(15) ); + b008_004_any: lv2_or(8) <= not( lv1_or_b(16) and lv1_or_b(17) ); + b009_004_any: lv2_or(9) <= not( lv1_or_b(18) and lv1_or_b(19) ); + b010_004_any: lv2_or(10) <= not( lv1_or_b(20) and lv1_or_b(21) ); + b011_004_any: lv2_or(11) <= not( lv1_or_b(22) and lv1_or_b(23) ); + b012_004_any: lv2_or(12) <= not( lv1_or_b(24) and lv1_or_b(25) ); + b013_004_any: lv2_or(13) <= not( lv1_or_b(26) and lv1_or_b(27) ); + b014_004_any: lv2_or(14) <= not( lv1_or_b(28) and lv1_or_b(29) ); + b015_004_any: lv2_or(15) <= not( lv1_or_b(30) and lv1_or_b(31) ); + b016_004_any: lv2_or(16) <= not( lv1_or_b(32) and lv1_or_b(33) ); + b017_004_any: lv2_or(17) <= not( lv1_or_b(34) and lv1_or_b(35) ); + b018_004_any: lv2_or(18) <= not( lv1_or_b(36) and lv1_or_b(37) ); + b019_004_any: lv2_or(19) <= not( lv1_or_b(38) and lv1_or_b(39) ); + b020_004_any: lv2_or(20) <= not( lv1_or_b(40) and lv1_or_b(41) ); + b021_004_any: lv2_or(21) <= not( lv1_or_b(42) and lv1_or_b(43) ); + b022_004_any: lv2_or(22) <= not( lv1_or_b(44) and lv1_or_b(45) ); + b023_004_any: lv2_or(23) <= not( lv1_or_b(46) and lv1_or_b(47) ); + b024_004_any: lv2_or(24) <= not( lv1_or_b(48) and lv1_or_b(49) ); + b025_004_any: lv2_or(25) <= not( lv1_or_b(50) and lv1_or_b(51) ); + b026_004_any: lv2_or(26) <= not( lv1_or_b(52) and lv1_or_b(53) ); + b027_004_any: lv2_or(27) <= not( lv1_or_b(54) and lv1_or_b(55) ); + b028_004_any: lv2_or(28) <= not( lv1_or_b(56) and lv1_or_b(57) ); + b029_004_any: lv2_or(29) <= not( lv1_or_b(58) and lv1_or_b(59) ); + b030_004_any: lv2_or(30) <= not( lv1_or_b(60) and lv1_or_b(61) ); + b031_004_any: lv2_or(31) <= not( lv1_or_b(62) and lv1_or_b(63) ); + b032_004_any: lv2_or(32) <= not( lv1_or_b(64) and lv1_or_b(65) ); + b033_004_any: lv2_or(33) <= not( lv1_or_b(66) and lv1_or_b(67) ); + b034_004_any: lv2_or(34) <= not( lv1_or_b(68) and lv1_or_b(69) ); + b035_004_any: lv2_or(35) <= not( lv1_or_b(70) and lv1_or_b(71) ); + b036_004_any: lv2_or(36) <= not( lv1_or_b(72) and lv1_or_b(73) ); + b037_004_any: lv2_or(37) <= not( lv1_or_b(74) and lv1_or_b(75) ); + b038_004_any: lv2_or(38) <= not( lv1_or_b(76) and lv1_or_b(77) ); + b039_004_any: lv2_or(39) <= not( lv1_or_b(78) and lv1_or_b(79) ); + b040_004_any: lv2_or(40) <= not( lv1_or_b(80) and lv1_or_b(81) ); + + b000_004_inv: lv2_inv(0) <= not( lv1_or_b(0) ); + b001_004_inv: lv2_inv(1) <= not( lv1_or_b(2) ); + b002_004_inv: lv2_inv(2) <= not( lv1_or_b(4) ); + b003_004_inv: lv2_inv(3) <= not( lv1_or_b(6) ); + b004_004_inv: lv2_inv(4) <= not( lv1_or_b(8) ); + b005_004_inv: lv2_inv(5) <= not( lv1_or_b(10) ); + b006_004_inv: lv2_inv(6) <= not( lv1_or_b(12) ); + b007_004_inv: lv2_inv(7) <= not( lv1_or_b(14) ); + b008_004_inv: lv2_inv(8) <= not( lv1_or_b(16) ); + b009_004_inv: lv2_inv(9) <= not( lv1_or_b(18) ); + b010_004_inv: lv2_inv(10) <= not( lv1_or_b(20) ); + b011_004_inv: lv2_inv(11) <= not( lv1_or_b(22) ); + b012_004_inv: lv2_inv(12) <= not( lv1_or_b(24) ); + b013_004_inv: lv2_inv(13) <= not( lv1_or_b(26) ); + b014_004_inv: lv2_inv(14) <= not( lv1_or_b(28) ); + b015_004_inv: lv2_inv(15) <= not( lv1_or_b(30) ); + b016_004_inv: lv2_inv(16) <= not( lv1_or_b(32) ); + b017_004_inv: lv2_inv(17) <= not( lv1_or_b(34) ); + b018_004_inv: lv2_inv(18) <= not( lv1_or_b(36) ); + b019_004_inv: lv2_inv(19) <= not( lv1_or_b(38) ); + b020_004_inv: lv2_inv(20) <= not( lv1_or_b(40) ); + b021_004_inv: lv2_inv(21) <= not( lv1_or_b(42) ); + b022_004_inv: lv2_inv(22) <= not( lv1_or_b(44) ); + b023_004_inv: lv2_inv(23) <= not( lv1_or_b(46) ); + b024_004_inv: lv2_inv(24) <= not( lv1_or_b(48) ); + b025_004_inv: lv2_inv(25) <= not( lv1_or_b(50) ); + b026_004_inv: lv2_inv(26) <= not( lv1_or_b(52) ); + b027_004_inv: lv2_inv(27) <= not( lv1_or_b(54) ); + b028_004_inv: lv2_inv(28) <= not( lv1_or_b(56) ); + b029_004_inv: lv2_inv(29) <= not( lv1_or_b(58) ); + b030_004_inv: lv2_inv(30) <= not( lv1_or_b(60) ); + b031_004_inv: lv2_inv(31) <= not( lv1_or_b(62) ); + b032_004_inv: lv2_inv(32) <= not( lv1_or_b(64) ); + b033_004_inv: lv2_inv(33) <= not( lv1_or_b(66) ); + b034_004_inv: lv2_inv(34) <= not( lv1_or_b(68) ); + b035_004_inv: lv2_inv(35) <= not( lv1_or_b(70) ); + b036_004_inv: lv2_inv(36) <= not( lv1_or_b(72) ); + b037_004_inv: lv2_inv(37) <= not( lv1_or_b(74) ); + b038_004_inv: lv2_inv(38) <= not( lv1_or_b(76) ); + b039_004_inv: lv2_inv(39) <= not( lv1_or_b(78) ); + b040_004_inv: lv2_inv(40) <= not( lv1_or_b(80) ); + + b000_004_enc6: lv2_enc6(0) <= not( lv2_inv(0) or lv1_or_b(1) ); + b001_004_enc6: lv2_enc6(1) <= not( lv2_inv(1) or lv1_or_b(3) ); + b002_004_enc6: lv2_enc6(2) <= not( lv2_inv(2) or lv1_or_b(5) ); + b003_004_enc6: lv2_enc6(3) <= not( lv2_inv(3) or lv1_or_b(7) ); + b004_004_enc6: lv2_enc6(4) <= not( lv2_inv(4) or lv1_or_b(9) ); + b005_004_enc6: lv2_enc6(5) <= not( lv2_inv(5) or lv1_or_b(11) ); + b006_004_enc6: lv2_enc6(6) <= not( lv2_inv(6) or lv1_or_b(13) ); + b007_004_enc6: lv2_enc6(7) <= not( lv2_inv(7) or lv1_or_b(15) ); + b008_004_enc6: lv2_enc6(8) <= not( lv2_inv(8) or lv1_or_b(17) ); + b009_004_enc6: lv2_enc6(9) <= not( lv2_inv(9) or lv1_or_b(19) ); + b010_004_enc6: lv2_enc6(10) <= not( lv2_inv(10) or lv1_or_b(21) ); + b011_004_enc6: lv2_enc6(11) <= not( lv2_inv(11) or lv1_or_b(23) ); + b012_004_enc6: lv2_enc6(12) <= not( lv2_inv(12) or lv1_or_b(25) ); + b013_004_enc6: lv2_enc6(13) <= not( lv2_inv(13) or lv1_or_b(27) ); + b014_004_enc6: lv2_enc6(14) <= not( lv2_inv(14) or lv1_or_b(29) ); + b015_004_enc6: lv2_enc6(15) <= not( lv2_inv(15) or lv1_or_b(31) ); + b016_004_enc6: lv2_enc6(16) <= not( lv2_inv(16) or lv1_or_b(33) ); + b017_004_enc6: lv2_enc6(17) <= not( lv2_inv(17) or lv1_or_b(35) ); + b018_004_enc6: lv2_enc6(18) <= not( lv2_inv(18) or lv1_or_b(37) ); + b019_004_enc6: lv2_enc6(19) <= not( lv2_inv(19) or lv1_or_b(39) ); + b020_004_enc6: lv2_enc6(20) <= not( lv2_inv(20) or lv1_or_b(41) ); + b021_004_enc6: lv2_enc6(21) <= not( lv2_inv(21) or lv1_or_b(43) ); + b022_004_enc6: lv2_enc6(22) <= not( lv2_inv(22) or lv1_or_b(45) ); + b023_004_enc6: lv2_enc6(23) <= not( lv2_inv(23) or lv1_or_b(47) ); + b024_004_enc6: lv2_enc6(24) <= not( lv2_inv(24) or lv1_or_b(49) ); + b025_004_enc6: lv2_enc6(25) <= not( lv2_inv(25) or lv1_or_b(51) ); + b026_004_enc6: lv2_enc6(26) <= not( lv2_inv(26) or lv1_or_b(53) ); + b027_004_enc6: lv2_enc6(27) <= not( lv2_inv(27) or lv1_or_b(55) ); + b028_004_enc6: lv2_enc6(28) <= not( lv2_inv(28) or lv1_or_b(57) ); + b029_004_enc6: lv2_enc6(29) <= not( lv2_inv(29) or lv1_or_b(59) ); + b030_004_enc6: lv2_enc6(30) <= not( lv2_inv(30) or lv1_or_b(61) ); + b031_004_enc6: lv2_enc6(31) <= not( lv2_inv(31) or lv1_or_b(63) ); + b032_004_enc6: lv2_enc6(32) <= not( lv2_inv(32) or lv1_or_b(65) ); + b033_004_enc6: lv2_enc6(33) <= not( lv2_inv(33) or lv1_or_b(67) ); + b034_004_enc6: lv2_enc6(34) <= not( lv2_inv(34) or lv1_or_b(69) ); + b035_004_enc6: lv2_enc6(35) <= not( lv2_inv(35) or lv1_or_b(71) ); + b036_004_enc6: lv2_enc6(36) <= not( lv2_inv(36) or lv1_or_b(73) ); + b037_004_enc6: lv2_enc6(37) <= not( lv2_inv(37) or lv1_or_b(75) ); + b038_004_enc6: lv2_enc6(38) <= not( lv2_inv(38) or lv1_or_b(77) ); + b039_004_enc6: lv2_enc6(39) <= not( lv2_inv(39) or lv1_or_b(79) ); + b040_004_enc6: lv2_enc6(40) <= not( lv2_inv(40) ); + + b000_004_enc7: lv2_enc7(0) <= not( lv1_enc7_b(0) and (lv1_enc7_b(1) or lv2_inv(0)) ); + b001_004_enc7: lv2_enc7(1) <= not( lv1_enc7_b(2) and (lv1_enc7_b(3) or lv2_inv(1)) ); + b002_004_enc7: lv2_enc7(2) <= not( lv1_enc7_b(4) and (lv1_enc7_b(5) or lv2_inv(2)) ); + b003_004_enc7: lv2_enc7(3) <= not( lv1_enc7_b(6) and (lv1_enc7_b(7) or lv2_inv(3)) ); + b004_004_enc7: lv2_enc7(4) <= not( lv1_enc7_b(8) and (lv1_enc7_b(9) or lv2_inv(4)) ); + b005_004_enc7: lv2_enc7(5) <= not( lv1_enc7_b(10) and (lv1_enc7_b(11) or lv2_inv(5)) ); + b006_004_enc7: lv2_enc7(6) <= not( lv1_enc7_b(12) and (lv1_enc7_b(13) or lv2_inv(6)) ); + b007_004_enc7: lv2_enc7(7) <= not( lv1_enc7_b(14) and (lv1_enc7_b(15) or lv2_inv(7)) ); + b008_004_enc7: lv2_enc7(8) <= not( lv1_enc7_b(16) and (lv1_enc7_b(17) or lv2_inv(8)) ); + b009_004_enc7: lv2_enc7(9) <= not( lv1_enc7_b(18) and (lv1_enc7_b(19) or lv2_inv(9)) ); + b010_004_enc7: lv2_enc7(10) <= not( lv1_enc7_b(20) and (lv1_enc7_b(21) or lv2_inv(10)) ); + b011_004_enc7: lv2_enc7(11) <= not( lv1_enc7_b(22) and (lv1_enc7_b(23) or lv2_inv(11)) ); + b012_004_enc7: lv2_enc7(12) <= not( lv1_enc7_b(24) and (lv1_enc7_b(25) or lv2_inv(12)) ); + b013_004_enc7: lv2_enc7(13) <= not( lv1_enc7_b(26) and (lv1_enc7_b(27) or lv2_inv(13)) ); + b014_004_enc7: lv2_enc7(14) <= not( lv1_enc7_b(28) and (lv1_enc7_b(29) or lv2_inv(14)) ); + b015_004_enc7: lv2_enc7(15) <= not( lv1_enc7_b(30) and (lv1_enc7_b(31) or lv2_inv(15)) ); + b016_004_enc7: lv2_enc7(16) <= not( lv1_enc7_b(32) and (lv1_enc7_b(33) or lv2_inv(16)) ); + b017_004_enc7: lv2_enc7(17) <= not( lv1_enc7_b(34) and (lv1_enc7_b(35) or lv2_inv(17)) ); + b018_004_enc7: lv2_enc7(18) <= not( lv1_enc7_b(36) and (lv1_enc7_b(37) or lv2_inv(18)) ); + b019_004_enc7: lv2_enc7(19) <= not( lv1_enc7_b(38) and (lv1_enc7_b(39) or lv2_inv(19)) ); + b020_004_enc7: lv2_enc7(20) <= not( lv1_enc7_b(40) and (lv1_enc7_b(41) or lv2_inv(20)) ); + b021_004_enc7: lv2_enc7(21) <= not( lv1_enc7_b(42) and (lv1_enc7_b(43) or lv2_inv(21)) ); + b022_004_enc7: lv2_enc7(22) <= not( lv1_enc7_b(44) and (lv1_enc7_b(45) or lv2_inv(22)) ); + b023_004_enc7: lv2_enc7(23) <= not( lv1_enc7_b(46) and (lv1_enc7_b(47) or lv2_inv(23)) ); + b024_004_enc7: lv2_enc7(24) <= not( lv1_enc7_b(48) and (lv1_enc7_b(49) or lv2_inv(24)) ); + b025_004_enc7: lv2_enc7(25) <= not( lv1_enc7_b(50) and (lv1_enc7_b(51) or lv2_inv(25)) ); + b026_004_enc7: lv2_enc7(26) <= not( lv1_enc7_b(52) and (lv1_enc7_b(53) or lv2_inv(26)) ); + b027_004_enc7: lv2_enc7(27) <= not( lv1_enc7_b(54) and (lv1_enc7_b(55) or lv2_inv(27)) ); + b028_004_enc7: lv2_enc7(28) <= not( lv1_enc7_b(56) and (lv1_enc7_b(57) or lv2_inv(28)) ); + b029_004_enc7: lv2_enc7(29) <= not( lv1_enc7_b(58) and (lv1_enc7_b(59) or lv2_inv(29)) ); + b030_004_enc7: lv2_enc7(30) <= not( lv1_enc7_b(60) and (lv1_enc7_b(61) or lv2_inv(30)) ); + b031_004_enc7: lv2_enc7(31) <= not( lv1_enc7_b(62) and (lv1_enc7_b(63) or lv2_inv(31)) ); + b032_004_enc7: lv2_enc7(32) <= not( lv1_enc7_b(64) and (lv1_enc7_b(65) or lv2_inv(32)) ); + b033_004_enc7: lv2_enc7(33) <= not( lv1_enc7_b(66) and (lv1_enc7_b(67) or lv2_inv(33)) ); + b034_004_enc7: lv2_enc7(34) <= not( lv1_enc7_b(68) and (lv1_enc7_b(69) or lv2_inv(34)) ); + b035_004_enc7: lv2_enc7(35) <= not( lv1_enc7_b(70) and (lv1_enc7_b(71) or lv2_inv(35)) ); + b036_004_enc7: lv2_enc7(36) <= not( lv1_enc7_b(72) and (lv1_enc7_b(73) or lv2_inv(36)) ); + b037_004_enc7: lv2_enc7(37) <= not( lv1_enc7_b(74) and (lv1_enc7_b(75) or lv2_inv(37)) ); + b038_004_enc7: lv2_enc7(38) <= not( lv1_enc7_b(76) and (lv1_enc7_b(77) or lv2_inv(38)) ); + b039_004_enc7: lv2_enc7(39) <= not( lv1_enc7_b(78) and (lv1_enc7_b(79) or lv2_inv(39)) ); + b040_004_enc7: lv2_enc7(40) <= not( lv1_enc7_b(80) and (lv1_enc7_b(81) or lv2_inv(40)) ); + + + + b000_008_any: lv3_or_b(0) <= not( lv2_or(0) or lv2_or(1) ); + b001_008_any: lv3_or_b(1) <= not( lv2_or(2) or lv2_or(3) ); + b002_008_any: lv3_or_b(2) <= not( lv2_or(4) or lv2_or(5) ); + b003_008_any: lv3_or_b(3) <= not( lv2_or(6) or lv2_or(7) ); + b004_008_any: lv3_or_b(4) <= not( lv2_or(8) or lv2_or(9) ); + b005_008_any: lv3_or_b(5) <= not( lv2_or(10) or lv2_or(11) ); + b006_008_any: lv3_or_b(6) <= not( lv2_or(12) or lv2_or(13) ); + b007_008_any: lv3_or_b(7) <= not( lv2_or(14) or lv2_or(15) ); + b008_008_any: lv3_or_b(8) <= not( lv2_or(16) or lv2_or(17) ); + b009_008_any: lv3_or_b(9) <= not( lv2_or(18) or lv2_or(19) ); + b010_008_any: lv3_or_b(10) <= not( lv2_or(20) or lv2_or(21) ); + b011_008_any: lv3_or_b(11) <= not( lv2_or(22) or lv2_or(23) ); + b012_008_any: lv3_or_b(12) <= not( lv2_or(24) or lv2_or(25) ); + b013_008_any: lv3_or_b(13) <= not( lv2_or(26) or lv2_or(27) ); + b014_008_any: lv3_or_b(14) <= not( lv2_or(28) or lv2_or(29) ); + b015_008_any: lv3_or_b(15) <= not( lv2_or(30) or lv2_or(31) ); + b016_008_any: lv3_or_b(16) <= not( lv2_or(32) or lv2_or(33) ); + b017_008_any: lv3_or_b(17) <= not( lv2_or(34) or lv2_or(35) ); + b018_008_any: lv3_or_b(18) <= not( lv2_or(36) or lv2_or(37) ); + b019_008_any: lv3_or_b(19) <= not( lv2_or(38) or lv2_or(39) ); + b020_008_any: lv3_or_b(20) <= not( lv2_or(40) ); + + b000_008_inv: lv3_inv_b(0) <= not( lv2_or(0) ); + b001_008_inv: lv3_inv_b(1) <= not( lv2_or(2) ); + b002_008_inv: lv3_inv_b(2) <= not( lv2_or(4) ); + b003_008_inv: lv3_inv_b(3) <= not( lv2_or(6) ); + b004_008_inv: lv3_inv_b(4) <= not( lv2_or(8) ); + b005_008_inv: lv3_inv_b(5) <= not( lv2_or(10) ); + b006_008_inv: lv3_inv_b(6) <= not( lv2_or(12) ); + b007_008_inv: lv3_inv_b(7) <= not( lv2_or(14) ); + b008_008_inv: lv3_inv_b(8) <= not( lv2_or(16) ); + b009_008_inv: lv3_inv_b(9) <= not( lv2_or(18) ); + b010_008_inv: lv3_inv_b(10) <= not( lv2_or(20) ); + b011_008_inv: lv3_inv_b(11) <= not( lv2_or(22) ); + b012_008_inv: lv3_inv_b(12) <= not( lv2_or(24) ); + b013_008_inv: lv3_inv_b(13) <= not( lv2_or(26) ); + b014_008_inv: lv3_inv_b(14) <= not( lv2_or(28) ); + b015_008_inv: lv3_inv_b(15) <= not( lv2_or(30) ); + b016_008_inv: lv3_inv_b(16) <= not( lv2_or(32) ); + b017_008_inv: lv3_inv_b(17) <= not( lv2_or(34) ); + b018_008_inv: lv3_inv_b(18) <= not( lv2_or(36) ); + b019_008_inv: lv3_inv_b(19) <= not( lv2_or(38) ); + b020_008_inv: lv3_inv_b(20) <= not( lv2_or(40) ); + + b000_008_enc5: lv3_enc5_b(0) <= not( lv3_inv_b(0) and lv2_or(1) ); + b001_008_enc5: lv3_enc5_b(1) <= not( lv3_inv_b(1) and lv2_or(3) ); + b002_008_enc5: lv3_enc5_b(2) <= not( lv3_inv_b(2) and lv2_or(5) ); + b003_008_enc5: lv3_enc5_b(3) <= not( lv3_inv_b(3) and lv2_or(7) ); + b004_008_enc5: lv3_enc5_b(4) <= not( lv3_inv_b(4) and lv2_or(9) ); + b005_008_enc5: lv3_enc5_b(5) <= not( lv3_inv_b(5) and lv2_or(11) ); + b006_008_enc5: lv3_enc5_b(6) <= not( lv3_inv_b(6) and lv2_or(13) ); + b007_008_enc5: lv3_enc5_b(7) <= not( lv3_inv_b(7) and lv2_or(15) ); + b008_008_enc5: lv3_enc5_b(8) <= not( lv3_inv_b(8) and lv2_or(17) ); + b009_008_enc5: lv3_enc5_b(9) <= not( lv3_inv_b(9) and lv2_or(19) ); + b010_008_enc5: lv3_enc5_b(10) <= not( lv3_inv_b(10) and lv2_or(21) ); + b011_008_enc5: lv3_enc5_b(11) <= not( lv3_inv_b(11) and lv2_or(23) ); + b012_008_enc5: lv3_enc5_b(12) <= not( lv3_inv_b(12) and lv2_or(25) ); + b013_008_enc5: lv3_enc5_b(13) <= not( lv3_inv_b(13) and lv2_or(27) ); + b014_008_enc5: lv3_enc5_b(14) <= not( lv3_inv_b(14) and lv2_or(29) ); + b015_008_enc5: lv3_enc5_b(15) <= not( lv3_inv_b(15) and lv2_or(31) ); + b016_008_enc5: lv3_enc5_b(16) <= not( lv3_inv_b(16) and lv2_or(33) ); + b017_008_enc5: lv3_enc5_b(17) <= not( lv3_inv_b(17) and lv2_or(35) ); + b018_008_enc5: lv3_enc5_b(18) <= not( lv3_inv_b(18) and lv2_or(37) ); + b019_008_enc5: lv3_enc5_b(19) <= not( lv3_inv_b(19) and lv2_or(39) ); + lv3_enc5_b(20) <= tiup ; + + b000_008_enc6: lv3_enc6_b(0) <= not( lv2_enc6(0) or (lv2_enc6(1) and lv3_inv_b(0)) ); + b001_008_enc6: lv3_enc6_b(1) <= not( lv2_enc6(2) or (lv2_enc6(3) and lv3_inv_b(1)) ); + b002_008_enc6: lv3_enc6_b(2) <= not( lv2_enc6(4) or (lv2_enc6(5) and lv3_inv_b(2)) ); + b003_008_enc6: lv3_enc6_b(3) <= not( lv2_enc6(6) or (lv2_enc6(7) and lv3_inv_b(3)) ); + b004_008_enc6: lv3_enc6_b(4) <= not( lv2_enc6(8) or (lv2_enc6(9) and lv3_inv_b(4)) ); + b005_008_enc6: lv3_enc6_b(5) <= not( lv2_enc6(10) or (lv2_enc6(11) and lv3_inv_b(5)) ); + b006_008_enc6: lv3_enc6_b(6) <= not( lv2_enc6(12) or (lv2_enc6(13) and lv3_inv_b(6)) ); + b007_008_enc6: lv3_enc6_b(7) <= not( lv2_enc6(14) or (lv2_enc6(15) and lv3_inv_b(7)) ); + b008_008_enc6: lv3_enc6_b(8) <= not( lv2_enc6(16) or (lv2_enc6(17) and lv3_inv_b(8)) ); + b009_008_enc6: lv3_enc6_b(9) <= not( lv2_enc6(18) or (lv2_enc6(19) and lv3_inv_b(9)) ); + b010_008_enc6: lv3_enc6_b(10) <= not( lv2_enc6(20) or (lv2_enc6(21) and lv3_inv_b(10)) ); + b011_008_enc6: lv3_enc6_b(11) <= not( lv2_enc6(22) or (lv2_enc6(23) and lv3_inv_b(11)) ); + b012_008_enc6: lv3_enc6_b(12) <= not( lv2_enc6(24) or (lv2_enc6(25) and lv3_inv_b(12)) ); + b013_008_enc6: lv3_enc6_b(13) <= not( lv2_enc6(26) or (lv2_enc6(27) and lv3_inv_b(13)) ); + b014_008_enc6: lv3_enc6_b(14) <= not( lv2_enc6(28) or (lv2_enc6(29) and lv3_inv_b(14)) ); + b015_008_enc6: lv3_enc6_b(15) <= not( lv2_enc6(30) or (lv2_enc6(31) and lv3_inv_b(15)) ); + b016_008_enc6: lv3_enc6_b(16) <= not( lv2_enc6(32) or (lv2_enc6(33) and lv3_inv_b(16)) ); + b017_008_enc6: lv3_enc6_b(17) <= not( lv2_enc6(34) or (lv2_enc6(35) and lv3_inv_b(17)) ); + b018_008_enc6: lv3_enc6_b(18) <= not( lv2_enc6(36) or (lv2_enc6(37) and lv3_inv_b(18)) ); + b019_008_enc6: lv3_enc6_b(19) <= not( lv2_enc6(38) or (lv2_enc6(39) and lv3_inv_b(19)) ); + b020_008_enc6: lv3_enc6_b(20) <= not( lv2_enc6(40) or lv3_inv_b(20) ); + + b000_008_enc7: lv3_enc7_b(0) <= not( lv2_enc7(0) or (lv2_enc7(1) and lv3_inv_b(0)) ); + b001_008_enc7: lv3_enc7_b(1) <= not( lv2_enc7(2) or (lv2_enc7(3) and lv3_inv_b(1)) ); + b002_008_enc7: lv3_enc7_b(2) <= not( lv2_enc7(4) or (lv2_enc7(5) and lv3_inv_b(2)) ); + b003_008_enc7: lv3_enc7_b(3) <= not( lv2_enc7(6) or (lv2_enc7(7) and lv3_inv_b(3)) ); + b004_008_enc7: lv3_enc7_b(4) <= not( lv2_enc7(8) or (lv2_enc7(9) and lv3_inv_b(4)) ); + b005_008_enc7: lv3_enc7_b(5) <= not( lv2_enc7(10) or (lv2_enc7(11) and lv3_inv_b(5)) ); + b006_008_enc7: lv3_enc7_b(6) <= not( lv2_enc7(12) or (lv2_enc7(13) and lv3_inv_b(6)) ); + b007_008_enc7: lv3_enc7_b(7) <= not( lv2_enc7(14) or (lv2_enc7(15) and lv3_inv_b(7)) ); + b008_008_enc7: lv3_enc7_b(8) <= not( lv2_enc7(16) or (lv2_enc7(17) and lv3_inv_b(8)) ); + b009_008_enc7: lv3_enc7_b(9) <= not( lv2_enc7(18) or (lv2_enc7(19) and lv3_inv_b(9)) ); + b010_008_enc7: lv3_enc7_b(10) <= not( lv2_enc7(20) or (lv2_enc7(21) and lv3_inv_b(10)) ); + b011_008_enc7: lv3_enc7_b(11) <= not( lv2_enc7(22) or (lv2_enc7(23) and lv3_inv_b(11)) ); + b012_008_enc7: lv3_enc7_b(12) <= not( lv2_enc7(24) or (lv2_enc7(25) and lv3_inv_b(12)) ); + b013_008_enc7: lv3_enc7_b(13) <= not( lv2_enc7(26) or (lv2_enc7(27) and lv3_inv_b(13)) ); + b014_008_enc7: lv3_enc7_b(14) <= not( lv2_enc7(28) or (lv2_enc7(29) and lv3_inv_b(14)) ); + b015_008_enc7: lv3_enc7_b(15) <= not( lv2_enc7(30) or (lv2_enc7(31) and lv3_inv_b(15)) ); + b016_008_enc7: lv3_enc7_b(16) <= not( lv2_enc7(32) or (lv2_enc7(33) and lv3_inv_b(16)) ); + b017_008_enc7: lv3_enc7_b(17) <= not( lv2_enc7(34) or (lv2_enc7(35) and lv3_inv_b(17)) ); + b018_008_enc7: lv3_enc7_b(18) <= not( lv2_enc7(36) or (lv2_enc7(37) and lv3_inv_b(18)) ); + b019_008_enc7: lv3_enc7_b(19) <= not( lv2_enc7(38) or (lv2_enc7(39) and lv3_inv_b(19)) ); + b020_008_enc7: lv3_enc7_b(20) <= not( lv2_enc7(40) or lv3_inv_b(20) ); + + + + b000_016_any: lv4_or(0) <= not( lv3_or_b(0) and lv3_or_b(1) ); + b001_016_any: lv4_or(1) <= not( lv3_or_b(2) and lv3_or_b(3) ); + b002_016_any: lv4_or(2) <= not( lv3_or_b(4) and lv3_or_b(5) ); + b003_016_any: lv4_or(3) <= not( lv3_or_b(6) and lv3_or_b(7) ); + b004_016_any: lv4_or(4) <= not( lv3_or_b(8) and lv3_or_b(9) ); + b005_016_any: lv4_or(5) <= not( lv3_or_b(10) and lv3_or_b(11) ); + b006_016_any: lv4_or(6) <= not( lv3_or_b(12) and lv3_or_b(13) ); + b007_016_any: lv4_or(7) <= not( lv3_or_b(14) and lv3_or_b(15) ); + b008_016_any: lv4_or(8) <= not( lv3_or_b(16) and lv3_or_b(17) ); + b009_016_any: lv4_or(9) <= not( lv3_or_b(18) and lv3_or_b(19) ); + b010_016_any: lv4_or(10) <= not( lv3_or_b(20) ); + + b000_016_inv: lv4_inv(0) <= not( lv3_or_b(0) ); + b001_016_inv: lv4_inv(1) <= not( lv3_or_b(2) ); + b002_016_inv: lv4_inv(2) <= not( lv3_or_b(4) ); + b003_016_inv: lv4_inv(3) <= not( lv3_or_b(6) ); + b004_016_inv: lv4_inv(4) <= not( lv3_or_b(8) ); + b005_016_inv: lv4_inv(5) <= not( lv3_or_b(10) ); + b006_016_inv: lv4_inv(6) <= not( lv3_or_b(12) ); + b007_016_inv: lv4_inv(7) <= not( lv3_or_b(14) ); + b008_016_inv: lv4_inv(8) <= not( lv3_or_b(16) ); + b009_016_inv: lv4_inv(9) <= not( lv3_or_b(18) ); + b010_016_inv: lv4_inv(10) <= not( lv3_or_b(20) ); + + b000_016_enc4: lv4_enc4(0) <= not( lv4_inv(0) or lv3_or_b(1) ); + b001_016_enc4: lv4_enc4(1) <= not( lv4_inv(1) or lv3_or_b(3) ); + b002_016_enc4: lv4_enc4(2) <= not( lv4_inv(2) or lv3_or_b(5) ); + b003_016_enc4: lv4_enc4(3) <= not( lv4_inv(3) or lv3_or_b(7) ); + b004_016_enc4: lv4_enc4(4) <= not( lv4_inv(4) or lv3_or_b(9) ); + b005_016_enc4: lv4_enc4(5) <= not( lv4_inv(5) or lv3_or_b(11) ); + b006_016_enc4: lv4_enc4(6) <= not( lv4_inv(6) or lv3_or_b(13) ); + b007_016_enc4: lv4_enc4(7) <= not( lv4_inv(7) or lv3_or_b(15) ); + b008_016_enc4: lv4_enc4(8) <= not( lv4_inv(8) or lv3_or_b(17) ); + b009_016_enc4: lv4_enc4(9) <= not( lv4_inv(9) or lv3_or_b(19) ); + lv4_enc4(10) <= tidn ; + + b000_016_enc5: lv4_enc5(0) <= not( lv3_enc5_b(0) and (lv3_enc5_b(1) or lv4_inv(0)) ); + b001_016_enc5: lv4_enc5(1) <= not( lv3_enc5_b(2) and (lv3_enc5_b(3) or lv4_inv(1)) ); + b002_016_enc5: lv4_enc5(2) <= not( lv3_enc5_b(4) and (lv3_enc5_b(5) or lv4_inv(2)) ); + b003_016_enc5: lv4_enc5(3) <= not( lv3_enc5_b(6) and (lv3_enc5_b(7) or lv4_inv(3)) ); + b004_016_enc5: lv4_enc5(4) <= not( lv3_enc5_b(8) and (lv3_enc5_b(9) or lv4_inv(4)) ); + b005_016_enc5: lv4_enc5(5) <= not( lv3_enc5_b(10) and (lv3_enc5_b(11) or lv4_inv(5)) ); + b006_016_enc5: lv4_enc5(6) <= not( lv3_enc5_b(12) and (lv3_enc5_b(13) or lv4_inv(6)) ); + b007_016_enc5: lv4_enc5(7) <= not( lv3_enc5_b(14) and (lv3_enc5_b(15) or lv4_inv(7)) ); + b008_016_enc5: lv4_enc5(8) <= not( lv3_enc5_b(16) and (lv3_enc5_b(17) or lv4_inv(8)) ); + b009_016_enc5: lv4_enc5(9) <= not( lv3_enc5_b(18) and (lv3_enc5_b(19) or lv4_inv(9)) ); + b010_016_enc5: lv4_enc5(10) <= not( lv3_enc5_b(20) ); + + + b000_016_enc6: lv4_enc6(0) <= not( lv3_enc6_b(0) and (lv3_enc6_b(1) or lv4_inv(0)) ); + b001_016_enc6: lv4_enc6(1) <= not( lv3_enc6_b(2) and (lv3_enc6_b(3) or lv4_inv(1)) ); + b002_016_enc6: lv4_enc6(2) <= not( lv3_enc6_b(4) and (lv3_enc6_b(5) or lv4_inv(2)) ); + b003_016_enc6: lv4_enc6(3) <= not( lv3_enc6_b(6) and (lv3_enc6_b(7) or lv4_inv(3)) ); + b004_016_enc6: lv4_enc6(4) <= not( lv3_enc6_b(8) and (lv3_enc6_b(9) or lv4_inv(4)) ); + b005_016_enc6: lv4_enc6(5) <= not( lv3_enc6_b(10) and (lv3_enc6_b(11) or lv4_inv(5)) ); + b006_016_enc6: lv4_enc6(6) <= not( lv3_enc6_b(12) and (lv3_enc6_b(13) or lv4_inv(6)) ); + b007_016_enc6: lv4_enc6(7) <= not( lv3_enc6_b(14) and (lv3_enc6_b(15) or lv4_inv(7)) ); + b008_016_enc6: lv4_enc6(8) <= not( lv3_enc6_b(16) and (lv3_enc6_b(17) or lv4_inv(8)) ); + b009_016_enc6: lv4_enc6(9) <= not( lv3_enc6_b(18) and (lv3_enc6_b(19) or lv4_inv(9)) ); + b010_016_enc6: lv4_enc6(10) <= not( lv3_enc6_b(20) and lv4_inv(10) ); + + b000_016_enc7: lv4_enc7(0) <= not( lv3_enc7_b(0) and (lv3_enc7_b(1) or lv4_inv(0)) ); + b001_016_enc7: lv4_enc7(1) <= not( lv3_enc7_b(2) and (lv3_enc7_b(3) or lv4_inv(1)) ); + b002_016_enc7: lv4_enc7(2) <= not( lv3_enc7_b(4) and (lv3_enc7_b(5) or lv4_inv(2)) ); + b003_016_enc7: lv4_enc7(3) <= not( lv3_enc7_b(6) and (lv3_enc7_b(7) or lv4_inv(3)) ); + b004_016_enc7: lv4_enc7(4) <= not( lv3_enc7_b(8) and (lv3_enc7_b(9) or lv4_inv(4)) ); + b005_016_enc7: lv4_enc7(5) <= not( lv3_enc7_b(10) and (lv3_enc7_b(11) or lv4_inv(5)) ); + b006_016_enc7: lv4_enc7(6) <= not( lv3_enc7_b(12) and (lv3_enc7_b(13) or lv4_inv(6)) ); + b007_016_enc7: lv4_enc7(7) <= not( lv3_enc7_b(14) and (lv3_enc7_b(15) or lv4_inv(7)) ); + b008_016_enc7: lv4_enc7(8) <= not( lv3_enc7_b(16) and (lv3_enc7_b(17) or lv4_inv(8)) ); + b009_016_enc7: lv4_enc7(9) <= not( lv3_enc7_b(18) and (lv3_enc7_b(19) or lv4_inv(9)) ); + b010_016_enc7: lv4_enc7(10) <= not( lv3_enc7_b(20) and lv4_inv(10) ); + + + r000_004_or: lv4_or_b(0) <= not( lv4_or(0) ); + r001_004_or: lv4_or_b(1) <= not( lv4_or(1) ); + r002_004_or: lv4_or_b(2) <= not( lv4_or(2) ); + r003_004_or: lv4_or_b(3) <= not( lv4_or(3) ); + r004_004_or: lv4_or_b(4) <= not( lv4_or(4) ); + r005_004_or: lv4_or_b(5) <= not( lv4_or(5) ); + r006_004_or: lv4_or_b(6) <= not( lv4_or(6) ); + r007_004_or: lv4_or_b(7) <= not( lv4_or(7) ); + r008_004_or: lv4_or_b(8) <= not( lv4_or(8) ); + r009_004_or: lv4_or_b(9) <= not( lv4_or(9) ); + r010_004_or: lv4_or_b(10) <= not( lv4_or(10) ); + r000_004_enc4: lv4_enc4_b(0) <= not( lv4_enc4(0) ); + r001_004_enc4: lv4_enc4_b(1) <= not( lv4_enc4(1) ); + r002_004_enc4: lv4_enc4_b(2) <= not( lv4_enc4(2) ); + r003_004_enc4: lv4_enc4_b(3) <= not( lv4_enc4(3) ); + r004_004_enc4: lv4_enc4_b(4) <= not( lv4_enc4(4) ); + r005_004_enc4: lv4_enc4_b(5) <= not( lv4_enc4(5) ); + r006_004_enc4: lv4_enc4_b(6) <= not( lv4_enc4(6) ); + r007_004_enc4: lv4_enc4_b(7) <= not( lv4_enc4(7) ); + r008_004_enc4: lv4_enc4_b(8) <= not( lv4_enc4(8) ); + r009_004_enc4: lv4_enc4_b(9) <= not( lv4_enc4(9) ); + r010_004_enc4: lv4_enc4_b(10) <= not( lv4_enc4(10) ); + r000_004_enc5: lv4_enc5_b(0) <= not( lv4_enc5(0) ); + r001_004_enc5: lv4_enc5_b(1) <= not( lv4_enc5(1) ); + r002_004_enc5: lv4_enc5_b(2) <= not( lv4_enc5(2) ); + r003_004_enc5: lv4_enc5_b(3) <= not( lv4_enc5(3) ); + r004_004_enc5: lv4_enc5_b(4) <= not( lv4_enc5(4) ); + r005_004_enc5: lv4_enc5_b(5) <= not( lv4_enc5(5) ); + r006_004_enc5: lv4_enc5_b(6) <= not( lv4_enc5(6) ); + r007_004_enc5: lv4_enc5_b(7) <= not( lv4_enc5(7) ); + r008_004_enc5: lv4_enc5_b(8) <= not( lv4_enc5(8) ); + r009_004_enc5: lv4_enc5_b(9) <= not( lv4_enc5(9) ); + r010_004_enc5: lv4_enc5_b(10) <= not( lv4_enc5(10) ); + r000_004_enc6: lv4_enc6_b(0) <= not( lv4_enc6(0) ); + r001_004_enc6: lv4_enc6_b(1) <= not( lv4_enc6(1) ); + r002_004_enc6: lv4_enc6_b(2) <= not( lv4_enc6(2) ); + r003_004_enc6: lv4_enc6_b(3) <= not( lv4_enc6(3) ); + r004_004_enc6: lv4_enc6_b(4) <= not( lv4_enc6(4) ); + r005_004_enc6: lv4_enc6_b(5) <= not( lv4_enc6(5) ); + r006_004_enc6: lv4_enc6_b(6) <= not( lv4_enc6(6) ); + r007_004_enc6: lv4_enc6_b(7) <= not( lv4_enc6(7) ); + r008_004_enc6: lv4_enc6_b(8) <= not( lv4_enc6(8) ); + r009_004_enc6: lv4_enc6_b(9) <= not( lv4_enc6(9) ); + r010_004_enc6: lv4_enc6_b(10) <= not( lv4_enc6(10) ); + r000_004_enc7: lv4_enc7_b(0) <= not( lv4_enc7(0) ); + r001_004_enc7: lv4_enc7_b(1) <= not( lv4_enc7(1) ); + r002_004_enc7: lv4_enc7_b(2) <= not( lv4_enc7(2) ); + r003_004_enc7: lv4_enc7_b(3) <= not( lv4_enc7(3) ); + r004_004_enc7: lv4_enc7_b(4) <= not( lv4_enc7(4) ); + r005_004_enc7: lv4_enc7_b(5) <= not( lv4_enc7(5) ); + r006_004_enc7: lv4_enc7_b(6) <= not( lv4_enc7(6) ); + r007_004_enc7: lv4_enc7_b(7) <= not( lv4_enc7(7) ); + r008_004_enc7: lv4_enc7_b(8) <= not( lv4_enc7(8) ); + r009_004_enc7: lv4_enc7_b(9) <= not( lv4_enc7(9) ); + r010_004_enc7: lv4_enc7_b(10) <= not( lv4_enc7(10) ); + + + + b000_032_any: lv5_or(0) <= not( lv4_or_b(0) and lv4_or_b(1) ); + b001_032_any: lv5_or(1) <= not( lv4_or_b(2) and lv4_or_b(3) ); + b002_032_any: lv5_or(2) <= not( lv4_or_b(4) and lv4_or_b(5) ); + b003_032_any: lv5_or(3) <= not( lv4_or_b(6) and lv4_or_b(7) ); + b004_032_any: lv5_or(4) <= not( lv4_or_b(8) and lv4_or_b(9) ); + b005_032_any: lv5_or(5) <= not( lv4_or_b(10) ); + + b000_032_inv: lv5_inv(0) <= not( lv4_or_b(0) ); + b001_032_inv: lv5_inv(1) <= not( lv4_or_b(2) ); + b002_032_inv: lv5_inv(2) <= not( lv4_or_b(4) ); + b003_032_inv: lv5_inv(3) <= not( lv4_or_b(6) ); + b004_032_inv: lv5_inv(4) <= not( lv4_or_b(8) ); + b005_032_inv: lv5_inv(5) <= not( lv4_or_b(10) ); + + b000_032_enc3: lv5_enc3(0) <= not( lv5_inv(0) or lv4_or_b(1) ); + b001_032_enc3: lv5_enc3(1) <= not( lv5_inv(1) or lv4_or_b(3) ); + b002_032_enc3: lv5_enc3(2) <= not( lv5_inv(2) or lv4_or_b(5) ); + b003_032_enc3: lv5_enc3(3) <= not( lv5_inv(3) or lv4_or_b(7) ); + b004_032_enc3: lv5_enc3(4) <= not( lv5_inv(4) or lv4_or_b(9) ); + lv5_enc3(5) <= tidn ; + + b000_032_enc4: lv5_enc4(0) <= not( lv4_enc4_b(0) and (lv4_enc4_b(1) or lv5_inv(0)) ); + b001_032_enc4: lv5_enc4(1) <= not( lv4_enc4_b(2) and (lv4_enc4_b(3) or lv5_inv(1)) ); + b002_032_enc4: lv5_enc4(2) <= not( lv4_enc4_b(4) and (lv4_enc4_b(5) or lv5_inv(2)) ); + b003_032_enc4: lv5_enc4(3) <= not( lv4_enc4_b(6) and (lv4_enc4_b(7) or lv5_inv(3)) ); + b004_032_enc4: lv5_enc4(4) <= not( lv4_enc4_b(8) and (lv4_enc4_b(9) or lv5_inv(4)) ); + b005_032_enc4: lv5_enc4(5) <= not( lv4_enc4_b(10) ); + + b000_032_enc5: lv5_enc5(0) <= not( lv4_enc5_b(0) and (lv4_enc5_b(1) or lv5_inv(0)) ); + b001_032_enc5: lv5_enc5(1) <= not( lv4_enc5_b(2) and (lv4_enc5_b(3) or lv5_inv(1)) ); + b002_032_enc5: lv5_enc5(2) <= not( lv4_enc5_b(4) and (lv4_enc5_b(5) or lv5_inv(2)) ); + b003_032_enc5: lv5_enc5(3) <= not( lv4_enc5_b(6) and (lv4_enc5_b(7) or lv5_inv(3)) ); + b004_032_enc5: lv5_enc5(4) <= not( lv4_enc5_b(8) and (lv4_enc5_b(9) or lv5_inv(4)) ); + b005_032_enc5: lv5_enc5(5) <= not( lv4_enc5_b(10) ); + + b000_032_enc6: lv5_enc6(0) <= not( lv4_enc6_b(0) and (lv4_enc6_b(1) or lv5_inv(0)) ); + b001_032_enc6: lv5_enc6(1) <= not( lv4_enc6_b(2) and (lv4_enc6_b(3) or lv5_inv(1)) ); + b002_032_enc6: lv5_enc6(2) <= not( lv4_enc6_b(4) and (lv4_enc6_b(5) or lv5_inv(2)) ); + b003_032_enc6: lv5_enc6(3) <= not( lv4_enc6_b(6) and (lv4_enc6_b(7) or lv5_inv(3)) ); + b004_032_enc6: lv5_enc6(4) <= not( lv4_enc6_b(8) and (lv4_enc6_b(9) or lv5_inv(4)) ); + b005_032_enc6: lv5_enc6(5) <= not( lv4_enc6_b(10) and lv5_inv(5) ); + + b000_032_enc7: lv5_enc7(0) <= not( lv4_enc7_b(0) and (lv4_enc7_b(1) or lv5_inv(0)) ); + b001_032_enc7: lv5_enc7(1) <= not( lv4_enc7_b(2) and (lv4_enc7_b(3) or lv5_inv(1)) ); + b002_032_enc7: lv5_enc7(2) <= not( lv4_enc7_b(4) and (lv4_enc7_b(5) or lv5_inv(2)) ); + b003_032_enc7: lv5_enc7(3) <= not( lv4_enc7_b(6) and (lv4_enc7_b(7) or lv5_inv(3)) ); + b004_032_enc7: lv5_enc7(4) <= not( lv4_enc7_b(8) and (lv4_enc7_b(9) or lv5_inv(4)) ); + b005_032_enc7: lv5_enc7(5) <= not( lv4_enc7_b(10) and lv5_inv(5) ); + + + + lv6_or_0 <= not lv6_or_b(0) ; + lv6_or_1 <= not lv6_or_b(1) ; + + + b000_064_any: lv6_or_b(0) <= not( lv5_or(0) or lv5_or(1) ); + b001_064_any: lv6_or_b(1) <= not( lv5_or(2) or lv5_or(3) ); + b002_064_any: lv6_or_b(2) <= not( lv5_or(4) or lv5_or(5) ); + + b000_064_inv: lv6_inv_b(0) <= not( lv5_or(0) ); + b001_064_inv: lv6_inv_b(1) <= not( lv5_or(2) ); + b002_064_inv: lv6_inv_b(2) <= not( lv5_or(4) ); + + b000_064_enc2: lv6_enc2_b(0) <= not( lv6_inv_b(0) and lv5_or(1) ); + b001_064_enc2: lv6_enc2_b(1) <= not( lv6_inv_b(1) and lv5_or(3) ); + b002_064_enc2: lv6_enc2_b(2) <= not( lv6_inv_b(2) ); + + b000_064_enc3: lv6_enc3_b(0) <= not( lv5_enc3(0) or (lv5_enc3(1) and lv6_inv_b(0)) ); + b001_064_enc3: lv6_enc3_b(1) <= not( lv5_enc3(2) or (lv5_enc3(3) and lv6_inv_b(1)) ); + b002_064_enc3: lv6_enc3_b(2) <= not( lv5_enc3(4) or (lv5_enc3(5) and lv6_inv_b(2)) ); + + b000_064_enc4: lv6_enc4_b(0) <= not( lv5_enc4(0) or (lv5_enc4(1) and lv6_inv_b(0)) ); + b001_064_enc4: lv6_enc4_b(1) <= not( lv5_enc4(2) or (lv5_enc4(3) and lv6_inv_b(1)) ); + b002_064_enc4: lv6_enc4_b(2) <= not( lv5_enc4(4) or (lv5_enc4(5) and lv6_inv_b(2)) ); + + b000_064_enc5: lv6_enc5_b(0) <= not( lv5_enc5(0) or (lv5_enc5(1) and lv6_inv_b(0)) ); + b001_064_enc5: lv6_enc5_b(1) <= not( lv5_enc5(2) or (lv5_enc5(3) and lv6_inv_b(1)) ); + b002_064_enc5: lv6_enc5_b(2) <= not( lv5_enc5(4) or (lv5_enc5(5) and lv6_inv_b(2)) ); + + b000_064_enc6: lv6_enc6_b(0) <= not( lv5_enc6(0) or (lv5_enc6(1) and lv6_inv_b(0)) ); + b001_064_enc6: lv6_enc6_b(1) <= not( lv5_enc6(2) or (lv5_enc6(3) and lv6_inv_b(1)) ); + b002_064_enc6: lv6_enc6_b(2) <= not( lv5_enc6(4) or (lv5_enc6(5) and lv6_inv_b(2)) ); + + b000_064_enc7: lv6_enc7_b(0) <= not( lv5_enc7(0) or (lv5_enc7(1) and lv6_inv_b(0)) ); + b001_064_enc7: lv6_enc7_b(1) <= not( lv5_enc7(2) or (lv5_enc7(3) and lv6_inv_b(1)) ); + b002_064_enc7: lv6_enc7_b(2) <= not( lv5_enc7(4) or (lv5_enc7(5) and lv6_inv_b(2)) ); + + + + b000_128_any: lv7_or(0) <= not( lv6_or_b(0) and lv6_or_b(1) ); + b001_128_any: lv7_or(1) <= not( lv6_or_b(2) ); + + b000_128_inv: lv7_inv(0) <= not( lv6_or_b(0) ); + b001_128_inv: lv7_inv(1) <= not( lv6_or_b(2) ); + + b000_128_enc1: lv7_enc1(0) <= not( lv7_inv(0) or lv6_or_b(1) ); + lv7_enc1(1) <= tidn ; + + b000_128_enc2: lv7_enc2(0) <= not( lv6_enc2_b(0) and (lv6_enc2_b(1) or lv7_inv(0)) ); + b001_128_enc2: lv7_enc2(1) <= not( lv6_enc2_b(2) and lv7_inv(1) ); + + b000_128_enc3: lv7_enc3(0) <= not( lv6_enc3_b(0) and (lv6_enc3_b(1) or lv7_inv(0)) ); + b001_128_enc3: lv7_enc3(1) <= not( lv6_enc3_b(2) ); + + b000_128_enc4: lv7_enc4(0) <= not( lv6_enc4_b(0) and (lv6_enc4_b(1) or lv7_inv(0)) ); + b001_128_enc4: lv7_enc4(1) <= not( lv6_enc4_b(2) ); + + b000_128_enc5: lv7_enc5(0) <= not( lv6_enc5_b(0) and (lv6_enc5_b(1) or lv7_inv(0)) ); + b001_128_enc5: lv7_enc5(1) <= not( lv6_enc5_b(2) ); + + b000_128_enc6: lv7_enc6(0) <= not( lv6_enc6_b(0) and (lv6_enc6_b(1) or lv7_inv(0)) ); + b001_128_enc6: lv7_enc6(1) <= not( lv6_enc6_b(2) and lv7_inv(1) ); + + b000_128_enc7: lv7_enc7(0) <= not( lv6_enc7_b(0) and (lv6_enc7_b(1) or lv7_inv(0)) ); + b001_128_enc7: lv7_enc7(1) <= not( lv6_enc7_b(2) and lv7_inv(1) ); + + + + b000_256_any: lv8_or_b(0) <= not( lv7_or(0) or lv7_or(1) ); + + b000_256_inv: lv8_inv_b(0) <= not( lv7_or(0) ); + + b000_256_enc0: lv8_enc0_b(0) <= not( lv8_inv_b(0) ); + + b000_256_enc1: lv8_enc1_b(0) <= not( lv7_enc1(0) or (lv7_enc1(1) and lv8_inv_b(0)) ); + + b000_256_enc2: lv8_enc2_b(0) <= not( lv7_enc2(0) or (lv7_enc2(1) and lv8_inv_b(0)) ); + + b000_256_enc3: lv8_enc3_b(0) <= not( lv7_enc3(0) or (lv7_enc3(1) and lv8_inv_b(0)) ); + + b000_256_enc4: lv8_enc4_b(0) <= not( lv7_enc4(0) or (lv7_enc4(1) and lv8_inv_b(0)) ); + + b000_256_enc5: lv8_enc5_b(0) <= not( lv7_enc5(0) or (lv7_enc5(1) and lv8_inv_b(0)) ); + + b000_256_enc6: lv8_enc6_b(0) <= not( lv7_enc6(0) or (lv7_enc6(1) and lv8_inv_b(0)) ); + + b000_256_enc7: lv8_enc7_b(0) <= not( lv7_enc7(0) or (lv7_enc7(1) and lv8_inv_b(0)) ); + + + o_any: lza_any_b <= ( lv8_or_b(0) ); + o_enc0: lza_amt_b(0) <= ( lv8_enc0_b(0) ); + o_enc1: lza_amt_b(1) <= ( lv8_enc1_b(0) ); + o_enc2: lza_amt_b(2) <= ( lv8_enc2_b(0) ); + o_enc3: lza_amt_b(3) <= ( lv8_enc3_b(0) ); + o_enc4: lza_amt_b(4) <= ( lv8_enc4_b(0) ); + o_enc5: lza_amt_b(5) <= ( lv8_enc5_b(0) ); + o_enc6: lza_amt_b(6) <= ( lv8_enc6_b(0) ); + o_enc7: lza_amt_b(7) <= ( lv8_enc7_b(0) ); + + + + + + + + +END; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_lza_ej.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_lza_ej.vhdl new file mode 100644 index 0000000..ffc4786 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_lza_ej.vhdl @@ -0,0 +1,159 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; use ieee.std_logic_1164.all ; +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + +entity fuq_lza_ej is port( + effsub :in std_ulogic; + sum :in std_ulogic_vector(0 to 162); + car :in std_ulogic_vector(53 to 162); + lzo_b :in std_ulogic_vector(0 to 162); + edge :out std_ulogic_vector(0 to 162) + ); +END fuq_lza_ej; + + +ARCHITECTURE fuq_lza_ej OF fuq_lza_ej IS + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal x0, x1, x2 :std_ulogic_vector(0 to 52); + signal x1_b, ej_b :std_ulogic_vector(0 to 52); + signal g_b, z, p, g, z_b, p_b :std_ulogic_vector(53 to 162); + signal sum_52_b :std_ulogic; + signal lzo_54 :std_ulogic; + signal gz, zg, gg, zz :std_ulogic_vector(55 to 162); + signal e0_b, e1_b :std_ulogic_vector(53 to 162); + signal e2_b : std_ulogic_vector(54 to 54); + signal unused :std_ulogic ; + + + + + + + +BEGIN + +unused <= g(54) or z_b(53) or z_b(162) or p_b(161) or p_b(162) ; + + + x0(0 to 52) <= tidn & effsub & sum(0 to 50); + x1(0 to 52) <= effsub & sum(0 to 51); + x2(0 to 52) <= sum(0 to 52); + + + xb_00: x1_b(0 to 52) <= not x1(0 to 52) ; + ejx_00: ej_b(0 to 52) <= not( x1_b(0 to 52) and ( x0(0 to 52) or x2(0 to 52) ) ); + ej_00: edge(0 to 52) <= not( ej_b(0 to 52) and lzo_b(0 to 52) ); + + + glo_53: g_b(53) <= not( sum(53) and car(53) ); + zhi_53: z (53) <= not( sum(53) or car(53) ); + phi_53: p (53) <= ( sum(53) xor car(53) ); + + ghi_53: g (53) <= not( g_b(53) ); + zlo_53: z_b(53) <= not( z (53) ); + plo_53: p_b(53) <= not( p (53) ); + s52_53: sum_52_b <= not( sum(52) ); + + e0_53: e0_b(53) <= not( sum(51) and sum_52_b ); + e1_53: e1_b(53) <= not( sum_52_b and g(53) ); + ej_53: edge(53) <= not( lzo_b(53) and e0_b(53) and e1_b(53) ); + + + + glo_54: g_b(54) <= not( sum(54) and car(54) ); + zhi_54: z (54) <= not( sum(54) or car(54) ); + phi_54: p (54) <= ( sum(54) xor car(54) ); + + ghi_54: g (54) <= not( g_b(54) ); + zlo_54: z_b(54) <= not( z (54) ); + plo_54: p_b(54) <= not( p (54) ); + + zb_54: lzo_54 <= not lzo_b(54); + + e0_54: e0_b(54) <= not( sum_52_b and p(53) and z_b(54) ); + e1_54: e1_b(54) <= not( sum(52) and p(53) and g_b(54) ); + e2_54: e2_b(54) <= not( (sum(52) and z(53) ) or lzo_54 ); + ej_54: edge(54) <= not( e0_b(54) and e1_b(54) and e2_b(54) ); + + + glo_55: g_b(55) <= not( sum(55) and car(55) ); + zhi_55: z (55) <= not( sum(55) or car(55) ); + phi_55: p (55) <= ( sum(55) xor car(55) ); + + ghi_55: g (55) <= not( g_b(55) ); + zlo_55: z_b(55) <= not( z (55) ); + plo_55: p_b(55) <= not( p (55) ); + + gz_55: gz(55) <= not( g_b(54) or z(55) ); + zg_55: zg(55) <= not( z_b(54) or g(55) ); + gg_55: gg(55) <= not( g_b(54) or g(55) ); + zz_55: zz(55) <= not( z_b(54) or z(55) ); + + e1_55: e1_b(55) <= not( p_b(53) and ( gz(55) or zg(55) ) ); + e0_55: e0_b(55) <= not( p (53) and ( gg(55) or zz(55) ) ); + ej_55: edge(55) <= not( e0_b(55) and e1_b(55) and lzo_b(55) ); + + + glo_56: g_b(56 to 162) <= not( sum(56 to 162) and car(56 to 162) ); + zhi_56: z (56 to 162) <= not( sum(56 to 162) or car(56 to 162) ); + phi_56: p (56 to 162) <= ( sum(56 to 162) xor car(56 to 162) ); + + ghi_56: g (56 to 162) <= not( g_b(56 to 162) ); + zlo_56: z_b(56 to 162) <= not( z (56 to 162) ); + plo_56: p_b(56 to 162) <= not( p (56 to 162) ); + + gz_56: gz(56 to 162) <= not( g_b(55 to 161) or z(56 to 162) ); + zg_56: zg(56 to 162) <= not( z_b(55 to 161) or g(56 to 162) ); + gg_56: gg(56 to 162) <= not( g_b(55 to 161) or g(56 to 162) ); + zz_56: zz(56 to 162) <= not( z_b(55 to 161) or z(56 to 162) ); + + e1_56: e1_b(56 to 162) <= not( p (54 to 160) and ( gz(56 to 162) or zg(56 to 162) ) ); + e0_56: e0_b(56 to 162) <= not( p_b(54 to 160) and ( gg(56 to 162) or zz(56 to 162) ) ); + ej_56: edge(56 to 162) <= not( e0_b(56 to 162) and e1_b(56 to 162) and lzo_b(56 to 162) ); + + +END; + + + + + + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_lze.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_lze.vhdl new file mode 100644 index 0000000..293f088 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_lze.vhdl @@ -0,0 +1,859 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + +entity fuq_lze is +generic( expand_type: integer := 2 ); +port( + vdd :inout power_logic; + gnd :inout power_logic; + clkoff_b :in std_ulogic; + act_dis :in std_ulogic; + flush :in std_ulogic; + delay_lclkr :in std_ulogic_vector(2 to 3); + mpw1_b :in std_ulogic_vector(2 to 3); + mpw2_b :in std_ulogic_vector(0 to 0); + sg_1 :in std_ulogic; + thold_1 :in std_ulogic; + fpu_enable :in std_ulogic; + nclk :in clk_logic; + + f_lze_si :in std_ulogic; + f_lze_so :out std_ulogic; + ex1_act_b :in std_ulogic; + + f_eie_ex2_lzo_expo :in std_ulogic_vector(1 to 13) ; + f_eie_ex2_b_expo :in std_ulogic_vector(1 to 13) ; + f_eie_ex2_use_bexp :in std_ulogic; + f_pic_ex2_lzo_dis_prod :in std_ulogic; + f_pic_ex2_sp_lzo :in std_ulogic; + f_pic_ex2_est_recip :in std_ulogic; + f_pic_ex2_est_rsqrt :in std_ulogic; + f_fmt_ex2_pass_msb_dp :in std_ulogic; + f_pic_ex2_frsp_ue1 :in std_ulogic; + f_alg_ex2_byp_nonflip :in std_ulogic; + f_pic_ex2_b_valid :in std_ulogic; + f_alg_ex2_sel_byp :in std_ulogic; + f_pic_ex2_to_integer :in std_ulogic; + f_pic_ex2_prenorm :in std_ulogic; + + f_lze_ex2_lzo_din :out std_ulogic_vector(0 to 162); + f_lze_ex3_sh_rgt_amt :out std_ulogic_vector(0 to 7); + f_lze_ex3_sh_rgt_en :out std_ulogic + +); + + + + + + + +end fuq_lze; + +architecture fuq_lze of fuq_lze is + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal thold_0_b, thold_0, forcee, sg_0 :std_ulogic; + signal ex1_act, ex2_act :std_ulogic; + signal spare_unused :std_ulogic_vector(0 to 3); + signal ex2_dp_001_by :std_ulogic; + signal ex2_sp_001_by :std_ulogic; + signal ex2_addr_dp_by :std_ulogic; + signal ex2_addr_sp_by :std_ulogic; + signal ex2_en_addr_dp_by :std_ulogic; + signal ex2_en_addr_sp_by :std_ulogic; + signal ex2_lzo_en, ex2_lzo_en_rapsp :std_ulogic; + signal ex2_lzo_en_by :std_ulogic; + signal ex2_expo_neg_dp_by :std_ulogic; + signal ex2_expo_neg_sp_by :std_ulogic; + signal ex2_expo_6_adj_by :std_ulogic; + signal ex2_addr_dp :std_ulogic; + signal ex2_addr_sp, ex2_addr_sp_rap :std_ulogic; + signal ex2_en_addr_dp :std_ulogic; + signal ex2_en_addr_sp, ex2_en_addr_sp_rap :std_ulogic; + signal ex2_lzo_cont :std_ulogic; + signal ex2_lzo_cont_dp :std_ulogic; + signal ex2_lzo_cont_sp :std_ulogic; + signal ex2_expo_neg_dp :std_ulogic; + signal ex2_expo_neg_sp :std_ulogic; + signal ex2_expo_6_adj :std_ulogic; + signal ex2_ins_est :std_ulogic; + signal ex2_sh_rgt_en_by :std_ulogic; + signal ex2_sh_rgt_en_p :std_ulogic; + signal ex2_sh_rgt_en :std_ulogic; + signal ex2_lzo_forbyp_0 :std_ulogic; + signal ex2_lzo_nonbyp_0 :std_ulogic; + signal ex3_sh_rgt_en :std_ulogic; + signal ex2_expo_by :std_ulogic_vector(1 to 13) ; + signal ex2_lzo_dcd_hi_by :std_ulogic_vector( 0 to 0) ; + signal ex2_lzo_dcd_lo_by :std_ulogic_vector( 0 to 0); + signal ex2_expo :std_ulogic_vector(1 to 13) ; + signal ex2_lzo_dcd_hi :std_ulogic_vector( 0 to 10); + signal ex2_lzo_dcd_lo :std_ulogic_vector( 0 to 15); + signal ex2_expo_p_sim_p :std_ulogic_vector(8 to 13); + signal ex2_expo_p_sim_g :std_ulogic_vector(9 to 13); + signal ex2_expo_p_sim :std_ulogic_vector(8 to 13) ; + signal ex2_expo_sim_p :std_ulogic_vector(8 to 13) ; + signal ex2_expo_sim_g :std_ulogic_vector(9 to 13) ; + signal ex2_expo_sim :std_ulogic_vector(8 to 13) ; + signal ex2_sh_rgt_amt :std_ulogic_vector(0 to 7); + signal ex3_shr_so, ex3_shr_si :std_ulogic_vector(0 to 8); + signal act_so, act_si :std_ulogic_vector(0 to 4); + signal ex3_sh_rgt_amt :std_ulogic_vector(0 to 7); + signal ex2_lzo_dcd_0 :std_ulogic; + signal ex2_lzo_dcd_b :std_ulogic_vector(0 to 162); +signal unused :std_ulogic; +signal f_alg_ex2_sel_byp_b , ex2_lzo_nonbyp_0_b , ex2_lzo_forbyp_0_b :std_ulogic ; + + + + + + +begin + + unused <= ex2_lzo_dcd_b(0) ; + + + + thold_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => thold_1, + q(0) => thold_0 ); + + sg_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => sg_1 , + q(0) => sg_0 ); + + + lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map ( + clkoff_b => clkoff_b, + thold => thold_0, + sg => sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => thold_0_b ); + + + + ex1_act <= not ex1_act_b; + + act_lat: tri_rlmreg_p generic map (width=> 5, expand_type => expand_type, needs_sreset => 0) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(2) , + mpw1_b => mpw1_b(2) , + mpw2_b => mpw2_b(0) , + vd => vdd, + gd => gnd, + nclk => nclk, + act => fpu_enable, + thold_b => thold_0_b, + sg => sg_0, + scout => act_so , + scin => act_si , + din(0) => spare_unused(0), + din(1) => spare_unused(1), + din(2) => ex1_act, + din(3) => spare_unused(2), + din(4) => spare_unused(3), + dout(0) => spare_unused(0), + dout(1) => spare_unused(1), + dout(2) => ex2_act, + dout(3) => spare_unused(2) , + dout(4) => spare_unused(3) ); + + + +ex2_dp_001_by <= + not ex2_expo_by(1) and + not ex2_expo_by(2) and + not ex2_expo_by(3) and + not ex2_expo_by(4) and + not ex2_expo_by(5) and + not ex2_expo_by(6) and + not ex2_expo_by(7) and + not ex2_expo_by(8) and + not ex2_expo_by(9) and + not ex2_expo_by(10) and + not ex2_expo_by(11) and + not ex2_expo_by(12) and + ex2_expo_by(13) ; + +ex2_sp_001_by <= + not ex2_expo_by(1) and + not ex2_expo_by(2) and + not ex2_expo_by(3) and + ex2_expo_by(4) and + ex2_expo_by(5) and + ex2_expo_by(6) and + not ex2_expo_by(7) and + not ex2_expo_by(8) and + not ex2_expo_by(9) and + not ex2_expo_by(10) and + not ex2_expo_by(11) and + not ex2_expo_by(12) and + ex2_expo_by(13) ; + + + + +ex2_expo_by(1 to 13) <= f_eie_ex2_b_expo(1 to 13); + + + + + + ex2_addr_dp_by <= not ex2_expo_by(1) and + not ex2_expo_by(2) and + not ex2_expo_by(3) and + not ex2_expo_by(4) and + not ex2_expo_by(5) ; + + ex2_addr_sp_by <= not ex2_expo_by(1) and + not ex2_expo_by(2) and + not ex2_expo_by(3) and + ex2_expo_by(4) and + ex2_expo_by(5) ; + + ex2_en_addr_dp_by <= ex2_addr_dp_by and ex2_lzo_cont_dp ; + ex2_en_addr_sp_by <= ex2_addr_sp_by and ex2_lzo_cont_sp ; + + + + + ex2_lzo_en_by <= (ex2_en_addr_dp_by or ex2_en_addr_sp_by) and ex2_lzo_cont ; + + ex2_expo_neg_dp_by <= + (ex2_lzo_en_by and ex2_lzo_dcd_hi_by( 0) and ex2_lzo_dcd_lo_by( 0) ) or + (ex2_expo_by(1) ) ; + + + ex2_expo_neg_sp_by <= + ( ex2_expo_by(1)) or + (not ex2_expo_by(2) and not ex2_expo_by(3) and not ex2_expo_by(4) ) or + (not ex2_expo_by(2) and not ex2_expo_by(3) and not ex2_expo_by(5) ) or + (not ex2_expo_by(2) and not ex2_expo_by(3) and not ex2_expo_by(6) ) or + (not ex2_expo_by(2) and not ex2_expo_by(3) and ex2_expo_by(4) and ex2_expo_by(5) and ex2_expo_by(6) and + not(ex2_expo_by(7) or ex2_expo_by(8) or ex2_expo_by(9) or ex2_expo_by(10) or ex2_expo_by(11) or ex2_expo_by(12) or ex2_expo_by(13) ) ); + + + + ex2_expo_6_adj_by <= (not ex2_expo_by(6) and f_pic_ex2_sp_lzo) or + ( ex2_expo_by(6) and not f_pic_ex2_sp_lzo) ; + + + ex2_lzo_dcd_0 <= ex2_lzo_dcd_hi( 0) and ex2_lzo_dcd_lo(1) ; + + + ex2_lzo_dcd_hi_by( 0) <= not ex2_expo_6_adj_by and not ex2_expo_by( 7) and not ex2_expo_by( 8) and not ex2_expo_by( 9) and ex2_lzo_en_by; + + ex2_lzo_dcd_lo_by( 0) <= not ex2_expo_by(10) and not ex2_expo_by(11) and not ex2_expo_by(12) and not ex2_expo_by(13) ; + + + + + + ex2_expo(1 to 13) <= f_eie_ex2_lzo_expo(1 to 13); + ex2_addr_dp <= not ex2_expo(1) and + not ex2_expo(2) and + not ex2_expo(3) and + not ex2_expo(4) and + not ex2_expo(5) ; + + ex2_addr_sp <= not ex2_expo(1) and + not ex2_expo(2) and + not ex2_expo(3) and + ex2_expo(4) and + ex2_expo(5) ; + + ex2_addr_sp_rap <= not ex2_expo(1) and + not ex2_expo(2) and + ex2_expo(3) and + not ex2_expo(4) and + not ex2_expo(5) ; + + ex2_en_addr_dp <= ex2_addr_dp and ex2_lzo_cont_dp ; + ex2_en_addr_sp <= ex2_addr_sp and ex2_lzo_cont_sp ; + ex2_en_addr_sp_rap <= ex2_addr_sp_rap and ex2_lzo_cont_sp ; + + ex2_lzo_cont <= not f_pic_ex2_lzo_dis_prod ; + ex2_lzo_cont_dp <= not f_pic_ex2_lzo_dis_prod and not f_pic_ex2_sp_lzo ; + ex2_lzo_cont_sp <= not f_pic_ex2_lzo_dis_prod and f_pic_ex2_sp_lzo ; + + + + + + ex2_lzo_en <= (ex2_en_addr_dp or ex2_en_addr_sp) and ex2_lzo_cont ; + ex2_lzo_en_rapsp <= (ex2_en_addr_dp or ex2_en_addr_sp_rap) and ex2_lzo_cont ; + + ex2_expo_neg_dp <= + (ex2_lzo_en and ex2_lzo_dcd_hi( 0) and ex2_lzo_dcd_lo( 0) ) or + (ex2_expo(1) ) ; + + + + ex2_expo_neg_sp <= + ( ex2_expo(1)) or + (not ex2_expo(2) and not ex2_expo(3) and not ex2_expo(4) ) or + (not ex2_expo(2) and not ex2_expo(3) and not ex2_expo(5) ) or + (not ex2_expo(2) and not ex2_expo(3) and not ex2_expo(6) ) or + (not ex2_expo(2) and not ex2_expo(3) and ex2_expo(4) and ex2_expo(5) and ex2_expo(6) and + not(ex2_expo(7) or ex2_expo(8) or ex2_expo(9) or ex2_expo(10) or ex2_expo(11) or ex2_expo(12) or ex2_expo(13)) ); + + + + ex2_expo_6_adj <= (not ex2_expo(6) and f_pic_ex2_sp_lzo) or + ( ex2_expo(6) and not f_pic_ex2_sp_lzo) ; + + + ex2_lzo_dcd_hi( 0) <= not ex2_expo_6_adj and not ex2_expo( 7) and not ex2_expo( 8) and not ex2_expo( 9) and ex2_lzo_en; + ex2_lzo_dcd_hi( 1) <= not ex2_expo_6_adj and not ex2_expo( 7) and not ex2_expo( 8) and ex2_expo( 9) and ex2_lzo_en; + ex2_lzo_dcd_hi( 2) <= not ex2_expo_6_adj and not ex2_expo( 7) and ex2_expo( 8) and not ex2_expo( 9) and ex2_lzo_en; + ex2_lzo_dcd_hi( 3) <= not ex2_expo_6_adj and not ex2_expo( 7) and ex2_expo( 8) and ex2_expo( 9) and ex2_lzo_en; + ex2_lzo_dcd_hi( 4) <= not ex2_expo_6_adj and ex2_expo( 7) and not ex2_expo( 8) and not ex2_expo( 9) and ex2_lzo_en; + ex2_lzo_dcd_hi( 5) <= not ex2_expo_6_adj and ex2_expo( 7) and not ex2_expo( 8) and ex2_expo( 9) and ex2_lzo_en; + ex2_lzo_dcd_hi( 6) <= not ex2_expo_6_adj and ex2_expo( 7) and ex2_expo( 8) and not ex2_expo( 9) and ex2_lzo_en; + ex2_lzo_dcd_hi( 7) <= not ex2_expo_6_adj and ex2_expo( 7) and ex2_expo( 8) and ex2_expo( 9) and ex2_lzo_en; + ex2_lzo_dcd_hi( 8) <= ex2_expo_6_adj and not ex2_expo( 7) and not ex2_expo( 8) and not ex2_expo( 9) and ex2_lzo_en_rapsp; + ex2_lzo_dcd_hi( 9) <= ex2_expo_6_adj and not ex2_expo( 7) and not ex2_expo( 8) and ex2_expo( 9) and ex2_lzo_en_rapsp; + ex2_lzo_dcd_hi(10) <= ex2_expo_6_adj and not ex2_expo( 7) and ex2_expo( 8) and not ex2_expo( 9) and ex2_lzo_en_rapsp; + + ex2_lzo_dcd_lo( 0) <= not ex2_expo(10) and not ex2_expo(11) and not ex2_expo(12) and not ex2_expo(13) ; + ex2_lzo_dcd_lo( 1) <= not ex2_expo(10) and not ex2_expo(11) and not ex2_expo(12) and ex2_expo(13) ; + ex2_lzo_dcd_lo( 2) <= not ex2_expo(10) and not ex2_expo(11) and ex2_expo(12) and not ex2_expo(13) ; + ex2_lzo_dcd_lo( 3) <= not ex2_expo(10) and not ex2_expo(11) and ex2_expo(12) and ex2_expo(13) ; + ex2_lzo_dcd_lo( 4) <= not ex2_expo(10) and ex2_expo(11) and not ex2_expo(12) and not ex2_expo(13) ; + ex2_lzo_dcd_lo( 5) <= not ex2_expo(10) and ex2_expo(11) and not ex2_expo(12) and ex2_expo(13) ; + ex2_lzo_dcd_lo( 6) <= not ex2_expo(10) and ex2_expo(11) and ex2_expo(12) and not ex2_expo(13) ; + ex2_lzo_dcd_lo( 7) <= not ex2_expo(10) and ex2_expo(11) and ex2_expo(12) and ex2_expo(13) ; + ex2_lzo_dcd_lo( 8) <= ex2_expo(10) and not ex2_expo(11) and not ex2_expo(12) and not ex2_expo(13) ; + ex2_lzo_dcd_lo( 9) <= ex2_expo(10) and not ex2_expo(11) and not ex2_expo(12) and ex2_expo(13) ; + ex2_lzo_dcd_lo(10) <= ex2_expo(10) and not ex2_expo(11) and ex2_expo(12) and not ex2_expo(13) ; + ex2_lzo_dcd_lo(11) <= ex2_expo(10) and not ex2_expo(11) and ex2_expo(12) and ex2_expo(13) ; + ex2_lzo_dcd_lo(12) <= ex2_expo(10) and ex2_expo(11) and not ex2_expo(12) and not ex2_expo(13) ; + ex2_lzo_dcd_lo(13) <= ex2_expo(10) and ex2_expo(11) and not ex2_expo(12) and ex2_expo(13) ; + ex2_lzo_dcd_lo(14) <= ex2_expo(10) and ex2_expo(11) and ex2_expo(12) and not ex2_expo(13) ; + ex2_lzo_dcd_lo(15) <= ex2_expo(10) and ex2_expo(11) and ex2_expo(12) and ex2_expo(13) ; + + + + + +u_lzo_dcd_0: ex2_lzo_dcd_b( 0) <= not( ex2_lzo_dcd_hi(0) and ex2_lzo_dcd_lo(1) ); +u_lzo_dcd_1: ex2_lzo_dcd_b( 1) <= not( ex2_lzo_dcd_hi(0) and ex2_lzo_dcd_lo(2) ); +u_lzo_dcd_2: ex2_lzo_dcd_b( 2) <= not( ex2_lzo_dcd_hi(0) and ex2_lzo_dcd_lo(3) ); +u_lzo_dcd_3: ex2_lzo_dcd_b( 3) <= not( ex2_lzo_dcd_hi(0) and ex2_lzo_dcd_lo(4) ); +u_lzo_dcd_4: ex2_lzo_dcd_b( 4) <= not( ex2_lzo_dcd_hi(0) and ex2_lzo_dcd_lo(5) ); +u_lzo_dcd_5: ex2_lzo_dcd_b( 5) <= not( ex2_lzo_dcd_hi(0) and ex2_lzo_dcd_lo(6) ); +u_lzo_dcd_6: ex2_lzo_dcd_b( 6) <= not( ex2_lzo_dcd_hi(0) and ex2_lzo_dcd_lo(7) ); +u_lzo_dcd_7: ex2_lzo_dcd_b( 7) <= not( ex2_lzo_dcd_hi(0) and ex2_lzo_dcd_lo(8) ); +u_lzo_dcd_8: ex2_lzo_dcd_b( 8) <= not( ex2_lzo_dcd_hi(0) and ex2_lzo_dcd_lo(9) ); +u_lzo_dcd_9: ex2_lzo_dcd_b( 9) <= not( ex2_lzo_dcd_hi(0) and ex2_lzo_dcd_lo(10) ); +u_lzo_dcd_10: ex2_lzo_dcd_b( 10) <= not( ex2_lzo_dcd_hi(0) and ex2_lzo_dcd_lo(11) ); +u_lzo_dcd_11: ex2_lzo_dcd_b( 11) <= not( ex2_lzo_dcd_hi(0) and ex2_lzo_dcd_lo(12) ); +u_lzo_dcd_12: ex2_lzo_dcd_b( 12) <= not( ex2_lzo_dcd_hi(0) and ex2_lzo_dcd_lo(13) ); +u_lzo_dcd_13: ex2_lzo_dcd_b( 13) <= not( ex2_lzo_dcd_hi(0) and ex2_lzo_dcd_lo(14) ); +u_lzo_dcd_14: ex2_lzo_dcd_b( 14) <= not( ex2_lzo_dcd_hi(0) and ex2_lzo_dcd_lo(15) ); + +u_lzo_dcd_15: ex2_lzo_dcd_b( 15) <= not( ex2_lzo_dcd_hi(1) and ex2_lzo_dcd_lo(0) ); +u_lzo_dcd_16: ex2_lzo_dcd_b( 16) <= not( ex2_lzo_dcd_hi(1) and ex2_lzo_dcd_lo(1) ); +u_lzo_dcd_17: ex2_lzo_dcd_b( 17) <= not( ex2_lzo_dcd_hi(1) and ex2_lzo_dcd_lo(2) ); +u_lzo_dcd_18: ex2_lzo_dcd_b( 18) <= not( ex2_lzo_dcd_hi(1) and ex2_lzo_dcd_lo(3) ); +u_lzo_dcd_19: ex2_lzo_dcd_b( 19) <= not( ex2_lzo_dcd_hi(1) and ex2_lzo_dcd_lo(4) ); +u_lzo_dcd_20: ex2_lzo_dcd_b( 20) <= not( ex2_lzo_dcd_hi(1) and ex2_lzo_dcd_lo(5) ); +u_lzo_dcd_21: ex2_lzo_dcd_b( 21) <= not( ex2_lzo_dcd_hi(1) and ex2_lzo_dcd_lo(6) ); +u_lzo_dcd_22: ex2_lzo_dcd_b( 22) <= not( ex2_lzo_dcd_hi(1) and ex2_lzo_dcd_lo(7) ); +u_lzo_dcd_23: ex2_lzo_dcd_b( 23) <= not( ex2_lzo_dcd_hi(1) and ex2_lzo_dcd_lo(8) ); +u_lzo_dcd_24: ex2_lzo_dcd_b( 24) <= not( ex2_lzo_dcd_hi(1) and ex2_lzo_dcd_lo(9) ); +u_lzo_dcd_25: ex2_lzo_dcd_b( 25) <= not( ex2_lzo_dcd_hi(1) and ex2_lzo_dcd_lo(10) ); +u_lzo_dcd_26: ex2_lzo_dcd_b( 26) <= not( ex2_lzo_dcd_hi(1) and ex2_lzo_dcd_lo(11) ); +u_lzo_dcd_27: ex2_lzo_dcd_b( 27) <= not( ex2_lzo_dcd_hi(1) and ex2_lzo_dcd_lo(12) ); +u_lzo_dcd_28: ex2_lzo_dcd_b( 28) <= not( ex2_lzo_dcd_hi(1) and ex2_lzo_dcd_lo(13) ); +u_lzo_dcd_29: ex2_lzo_dcd_b( 29) <= not( ex2_lzo_dcd_hi(1) and ex2_lzo_dcd_lo(14) ); +u_lzo_dcd_30: ex2_lzo_dcd_b( 30) <= not( ex2_lzo_dcd_hi(1) and ex2_lzo_dcd_lo(15) ); + +u_lzo_dcd_31: ex2_lzo_dcd_b( 31) <= not( ex2_lzo_dcd_hi(2) and ex2_lzo_dcd_lo(0 ) ); +u_lzo_dcd_32: ex2_lzo_dcd_b( 32) <= not( ex2_lzo_dcd_hi(2) and ex2_lzo_dcd_lo(1 ) ); +u_lzo_dcd_33: ex2_lzo_dcd_b( 33) <= not( ex2_lzo_dcd_hi(2) and ex2_lzo_dcd_lo(2 ) ); +u_lzo_dcd_34: ex2_lzo_dcd_b( 34) <= not( ex2_lzo_dcd_hi(2) and ex2_lzo_dcd_lo(3 ) ); +u_lzo_dcd_35: ex2_lzo_dcd_b( 35) <= not( ex2_lzo_dcd_hi(2) and ex2_lzo_dcd_lo(4 ) ); +u_lzo_dcd_36: ex2_lzo_dcd_b( 36) <= not( ex2_lzo_dcd_hi(2) and ex2_lzo_dcd_lo(5 ) ); +u_lzo_dcd_37: ex2_lzo_dcd_b( 37) <= not( ex2_lzo_dcd_hi(2) and ex2_lzo_dcd_lo(6 ) ); +u_lzo_dcd_38: ex2_lzo_dcd_b( 38) <= not( ex2_lzo_dcd_hi(2) and ex2_lzo_dcd_lo(7 ) ); +u_lzo_dcd_39: ex2_lzo_dcd_b( 39) <= not( ex2_lzo_dcd_hi(2) and ex2_lzo_dcd_lo(8 ) ); +u_lzo_dcd_40: ex2_lzo_dcd_b( 40) <= not( ex2_lzo_dcd_hi(2) and ex2_lzo_dcd_lo(9 ) ); +u_lzo_dcd_41: ex2_lzo_dcd_b( 41) <= not( ex2_lzo_dcd_hi(2) and ex2_lzo_dcd_lo(10) ); +u_lzo_dcd_42: ex2_lzo_dcd_b( 42) <= not( ex2_lzo_dcd_hi(2) and ex2_lzo_dcd_lo(11) ); +u_lzo_dcd_43: ex2_lzo_dcd_b( 43) <= not( ex2_lzo_dcd_hi(2) and ex2_lzo_dcd_lo(12) ); +u_lzo_dcd_44: ex2_lzo_dcd_b( 44) <= not( ex2_lzo_dcd_hi(2) and ex2_lzo_dcd_lo(13) ); +u_lzo_dcd_45: ex2_lzo_dcd_b( 45) <= not( ex2_lzo_dcd_hi(2) and ex2_lzo_dcd_lo(14) ); +u_lzo_dcd_46: ex2_lzo_dcd_b( 46) <= not( ex2_lzo_dcd_hi(2) and ex2_lzo_dcd_lo(15) ); + +u_lzo_dcd_47: ex2_lzo_dcd_b( 47) <= not( ex2_lzo_dcd_hi(3) and ex2_lzo_dcd_lo(0 ) ); +u_lzo_dcd_48: ex2_lzo_dcd_b( 48) <= not( ex2_lzo_dcd_hi(3) and ex2_lzo_dcd_lo(1 ) ); +u_lzo_dcd_49: ex2_lzo_dcd_b( 49) <= not( ex2_lzo_dcd_hi(3) and ex2_lzo_dcd_lo(2 ) ); +u_lzo_dcd_50: ex2_lzo_dcd_b( 50) <= not( ex2_lzo_dcd_hi(3) and ex2_lzo_dcd_lo(3 ) ); +u_lzo_dcd_51: ex2_lzo_dcd_b( 51) <= not( ex2_lzo_dcd_hi(3) and ex2_lzo_dcd_lo(4 ) ); +u_lzo_dcd_52: ex2_lzo_dcd_b( 52) <= not( ex2_lzo_dcd_hi(3) and ex2_lzo_dcd_lo(5 ) ); +u_lzo_dcd_53: ex2_lzo_dcd_b( 53) <= not( ex2_lzo_dcd_hi(3) and ex2_lzo_dcd_lo(6 ) ); +u_lzo_dcd_54: ex2_lzo_dcd_b( 54) <= not( ex2_lzo_dcd_hi(3) and ex2_lzo_dcd_lo(7 ) ); +u_lzo_dcd_55: ex2_lzo_dcd_b( 55) <= not( ex2_lzo_dcd_hi(3) and ex2_lzo_dcd_lo(8 ) ); +u_lzo_dcd_56: ex2_lzo_dcd_b( 56) <= not( ex2_lzo_dcd_hi(3) and ex2_lzo_dcd_lo(9 ) ); +u_lzo_dcd_57: ex2_lzo_dcd_b( 57) <= not( ex2_lzo_dcd_hi(3) and ex2_lzo_dcd_lo(10) ); +u_lzo_dcd_58: ex2_lzo_dcd_b( 58) <= not( ex2_lzo_dcd_hi(3) and ex2_lzo_dcd_lo(11) ); +u_lzo_dcd_59: ex2_lzo_dcd_b( 59) <= not( ex2_lzo_dcd_hi(3) and ex2_lzo_dcd_lo(12) ); +u_lzo_dcd_60: ex2_lzo_dcd_b( 60) <= not( ex2_lzo_dcd_hi(3) and ex2_lzo_dcd_lo(13) ); +u_lzo_dcd_61: ex2_lzo_dcd_b( 61) <= not( ex2_lzo_dcd_hi(3) and ex2_lzo_dcd_lo(14) ); +u_lzo_dcd_62: ex2_lzo_dcd_b( 62) <= not( ex2_lzo_dcd_hi(3) and ex2_lzo_dcd_lo(15) ); + +u_lzo_dcd_63: ex2_lzo_dcd_b( 63) <= not( ex2_lzo_dcd_hi(4) and ex2_lzo_dcd_lo(0 ) ); +u_lzo_dcd_64: ex2_lzo_dcd_b( 64) <= not( ex2_lzo_dcd_hi(4) and ex2_lzo_dcd_lo(1 ) ); +u_lzo_dcd_65: ex2_lzo_dcd_b( 65) <= not( ex2_lzo_dcd_hi(4) and ex2_lzo_dcd_lo(2 ) ); +u_lzo_dcd_66: ex2_lzo_dcd_b( 66) <= not( ex2_lzo_dcd_hi(4) and ex2_lzo_dcd_lo(3 ) ); +u_lzo_dcd_67: ex2_lzo_dcd_b( 67) <= not( ex2_lzo_dcd_hi(4) and ex2_lzo_dcd_lo(4 ) ); +u_lzo_dcd_68: ex2_lzo_dcd_b( 68) <= not( ex2_lzo_dcd_hi(4) and ex2_lzo_dcd_lo(5 ) ); +u_lzo_dcd_69: ex2_lzo_dcd_b( 69) <= not( ex2_lzo_dcd_hi(4) and ex2_lzo_dcd_lo(6 ) ); +u_lzo_dcd_70: ex2_lzo_dcd_b( 70) <= not( ex2_lzo_dcd_hi(4) and ex2_lzo_dcd_lo(7 ) ); +u_lzo_dcd_71: ex2_lzo_dcd_b( 71) <= not( ex2_lzo_dcd_hi(4) and ex2_lzo_dcd_lo(8 ) ); +u_lzo_dcd_72: ex2_lzo_dcd_b( 72) <= not( ex2_lzo_dcd_hi(4) and ex2_lzo_dcd_lo(9 ) ); +u_lzo_dcd_73: ex2_lzo_dcd_b( 73) <= not( ex2_lzo_dcd_hi(4) and ex2_lzo_dcd_lo(10) ); +u_lzo_dcd_74: ex2_lzo_dcd_b( 74) <= not( ex2_lzo_dcd_hi(4) and ex2_lzo_dcd_lo(11) ); +u_lzo_dcd_75: ex2_lzo_dcd_b( 75) <= not( ex2_lzo_dcd_hi(4) and ex2_lzo_dcd_lo(12) ); +u_lzo_dcd_76: ex2_lzo_dcd_b( 76) <= not( ex2_lzo_dcd_hi(4) and ex2_lzo_dcd_lo(13) ); +u_lzo_dcd_77: ex2_lzo_dcd_b( 77) <= not( ex2_lzo_dcd_hi(4) and ex2_lzo_dcd_lo(14) ); +u_lzo_dcd_78: ex2_lzo_dcd_b( 78) <= not( ex2_lzo_dcd_hi(4) and ex2_lzo_dcd_lo(15) ); + +u_lzo_dcd_79: ex2_lzo_dcd_b( 79) <= not( ex2_lzo_dcd_hi(5) and ex2_lzo_dcd_lo(0 ) ); +u_lzo_dcd_80: ex2_lzo_dcd_b( 80) <= not( ex2_lzo_dcd_hi(5) and ex2_lzo_dcd_lo(1 ) ); +u_lzo_dcd_81: ex2_lzo_dcd_b( 81) <= not( ex2_lzo_dcd_hi(5) and ex2_lzo_dcd_lo(2 ) ); +u_lzo_dcd_82: ex2_lzo_dcd_b( 82) <= not( ex2_lzo_dcd_hi(5) and ex2_lzo_dcd_lo(3 ) ); +u_lzo_dcd_83: ex2_lzo_dcd_b( 83) <= not( ex2_lzo_dcd_hi(5) and ex2_lzo_dcd_lo(4 ) ); +u_lzo_dcd_84: ex2_lzo_dcd_b( 84) <= not( ex2_lzo_dcd_hi(5) and ex2_lzo_dcd_lo(5 ) ); +u_lzo_dcd_85: ex2_lzo_dcd_b( 85) <= not( ex2_lzo_dcd_hi(5) and ex2_lzo_dcd_lo(6 ) ); +u_lzo_dcd_86: ex2_lzo_dcd_b( 86) <= not( ex2_lzo_dcd_hi(5) and ex2_lzo_dcd_lo(7 ) ); +u_lzo_dcd_87: ex2_lzo_dcd_b( 87) <= not( ex2_lzo_dcd_hi(5) and ex2_lzo_dcd_lo(8 ) ); +u_lzo_dcd_88: ex2_lzo_dcd_b( 88) <= not( ex2_lzo_dcd_hi(5) and ex2_lzo_dcd_lo(9 ) ); +u_lzo_dcd_89: ex2_lzo_dcd_b( 89) <= not( ex2_lzo_dcd_hi(5) and ex2_lzo_dcd_lo(10) ); +u_lzo_dcd_90: ex2_lzo_dcd_b( 90) <= not( ex2_lzo_dcd_hi(5) and ex2_lzo_dcd_lo(11) ); +u_lzo_dcd_91: ex2_lzo_dcd_b( 91) <= not( ex2_lzo_dcd_hi(5) and ex2_lzo_dcd_lo(12) ); +u_lzo_dcd_92: ex2_lzo_dcd_b( 92) <= not( ex2_lzo_dcd_hi(5) and ex2_lzo_dcd_lo(13) ); +u_lzo_dcd_93: ex2_lzo_dcd_b( 93) <= not( ex2_lzo_dcd_hi(5) and ex2_lzo_dcd_lo(14) ); +u_lzo_dcd_94: ex2_lzo_dcd_b( 94) <= not( ex2_lzo_dcd_hi(5) and ex2_lzo_dcd_lo(15) ); + +u_lzo_dcd_95: ex2_lzo_dcd_b( 95) <= not( ex2_lzo_dcd_hi(6) and ex2_lzo_dcd_lo(0 ) ); +u_lzo_dcd_96: ex2_lzo_dcd_b( 96) <= not( ex2_lzo_dcd_hi(6) and ex2_lzo_dcd_lo(1 ) ); +u_lzo_dcd_97: ex2_lzo_dcd_b( 97) <= not( ex2_lzo_dcd_hi(6) and ex2_lzo_dcd_lo(2 ) ); +u_lzo_dcd_98: ex2_lzo_dcd_b( 98) <= not( ex2_lzo_dcd_hi(6) and ex2_lzo_dcd_lo(3 ) ); +u_lzo_dcd_99: ex2_lzo_dcd_b( 99) <= not( ex2_lzo_dcd_hi(6) and ex2_lzo_dcd_lo(4 ) ); +u_lzo_dcd_100: ex2_lzo_dcd_b(100) <= not( ex2_lzo_dcd_hi(6) and ex2_lzo_dcd_lo(5 ) ); +u_lzo_dcd_101: ex2_lzo_dcd_b(101) <= not( ex2_lzo_dcd_hi(6) and ex2_lzo_dcd_lo(6 ) ); +u_lzo_dcd_102: ex2_lzo_dcd_b(102) <= not( ex2_lzo_dcd_hi(6) and ex2_lzo_dcd_lo(7 ) ); +u_lzo_dcd_103: ex2_lzo_dcd_b(103) <= not( ex2_lzo_dcd_hi(6) and ex2_lzo_dcd_lo(8 ) ); +u_lzo_dcd_104: ex2_lzo_dcd_b(104) <= not( ex2_lzo_dcd_hi(6) and ex2_lzo_dcd_lo(9 ) ); +u_lzo_dcd_105: ex2_lzo_dcd_b(105) <= not( ex2_lzo_dcd_hi(6) and ex2_lzo_dcd_lo(10) ); +u_lzo_dcd_106: ex2_lzo_dcd_b(106) <= not( ex2_lzo_dcd_hi(6) and ex2_lzo_dcd_lo(11) ); +u_lzo_dcd_107: ex2_lzo_dcd_b(107) <= not( ex2_lzo_dcd_hi(6) and ex2_lzo_dcd_lo(12) ); +u_lzo_dcd_108: ex2_lzo_dcd_b(108) <= not( ex2_lzo_dcd_hi(6) and ex2_lzo_dcd_lo(13) ); +u_lzo_dcd_109: ex2_lzo_dcd_b(109) <= not( ex2_lzo_dcd_hi(6) and ex2_lzo_dcd_lo(14) ); +u_lzo_dcd_110: ex2_lzo_dcd_b(110) <= not( ex2_lzo_dcd_hi(6) and ex2_lzo_dcd_lo(15) ); + +u_lzo_dcd_111: ex2_lzo_dcd_b(111) <= not( ex2_lzo_dcd_hi(7) and ex2_lzo_dcd_lo(0 ) ); +u_lzo_dcd_112: ex2_lzo_dcd_b(112) <= not( ex2_lzo_dcd_hi(7) and ex2_lzo_dcd_lo(1 ) ); +u_lzo_dcd_113: ex2_lzo_dcd_b(113) <= not( ex2_lzo_dcd_hi(7) and ex2_lzo_dcd_lo(2 ) ); +u_lzo_dcd_114: ex2_lzo_dcd_b(114) <= not( ex2_lzo_dcd_hi(7) and ex2_lzo_dcd_lo(3 ) ); +u_lzo_dcd_115: ex2_lzo_dcd_b(115) <= not( ex2_lzo_dcd_hi(7) and ex2_lzo_dcd_lo(4 ) ); +u_lzo_dcd_116: ex2_lzo_dcd_b(116) <= not( ex2_lzo_dcd_hi(7) and ex2_lzo_dcd_lo(5 ) ); +u_lzo_dcd_117: ex2_lzo_dcd_b(117) <= not( ex2_lzo_dcd_hi(7) and ex2_lzo_dcd_lo(6 ) ); +u_lzo_dcd_118: ex2_lzo_dcd_b(118) <= not( ex2_lzo_dcd_hi(7) and ex2_lzo_dcd_lo(7 ) ); +u_lzo_dcd_119: ex2_lzo_dcd_b(119) <= not( ex2_lzo_dcd_hi(7) and ex2_lzo_dcd_lo(8 ) ); +u_lzo_dcd_120: ex2_lzo_dcd_b(120) <= not( ex2_lzo_dcd_hi(7) and ex2_lzo_dcd_lo(9 ) ); +u_lzo_dcd_121: ex2_lzo_dcd_b(121) <= not( ex2_lzo_dcd_hi(7) and ex2_lzo_dcd_lo(10) ); +u_lzo_dcd_122: ex2_lzo_dcd_b(122) <= not( ex2_lzo_dcd_hi(7) and ex2_lzo_dcd_lo(11) ); +u_lzo_dcd_123: ex2_lzo_dcd_b(123) <= not( ex2_lzo_dcd_hi(7) and ex2_lzo_dcd_lo(12) ); +u_lzo_dcd_124: ex2_lzo_dcd_b(124) <= not( ex2_lzo_dcd_hi(7) and ex2_lzo_dcd_lo(13) ); +u_lzo_dcd_125: ex2_lzo_dcd_b(125) <= not( ex2_lzo_dcd_hi(7) and ex2_lzo_dcd_lo(14) ); +u_lzo_dcd_126: ex2_lzo_dcd_b(126) <= not( ex2_lzo_dcd_hi(7) and ex2_lzo_dcd_lo(15) ); + +u_lzo_dcd_127: ex2_lzo_dcd_b(127) <= not( ex2_lzo_dcd_hi(8) and ex2_lzo_dcd_lo(0 ) ); +u_lzo_dcd_128: ex2_lzo_dcd_b(128) <= not( ex2_lzo_dcd_hi(8) and ex2_lzo_dcd_lo(1 ) ); +u_lzo_dcd_129: ex2_lzo_dcd_b(129) <= not( ex2_lzo_dcd_hi(8) and ex2_lzo_dcd_lo(2 ) ); +u_lzo_dcd_130: ex2_lzo_dcd_b(130) <= not( ex2_lzo_dcd_hi(8) and ex2_lzo_dcd_lo(3 ) ); +u_lzo_dcd_131: ex2_lzo_dcd_b(131) <= not( ex2_lzo_dcd_hi(8) and ex2_lzo_dcd_lo(4 ) ); +u_lzo_dcd_132: ex2_lzo_dcd_b(132) <= not( ex2_lzo_dcd_hi(8) and ex2_lzo_dcd_lo(5 ) ); +u_lzo_dcd_133: ex2_lzo_dcd_b(133) <= not( ex2_lzo_dcd_hi(8) and ex2_lzo_dcd_lo(6 ) ); +u_lzo_dcd_134: ex2_lzo_dcd_b(134) <= not( ex2_lzo_dcd_hi(8) and ex2_lzo_dcd_lo(7 ) ); +u_lzo_dcd_135: ex2_lzo_dcd_b(135) <= not( ex2_lzo_dcd_hi(8) and ex2_lzo_dcd_lo(8 ) ); +u_lzo_dcd_136: ex2_lzo_dcd_b(136) <= not( ex2_lzo_dcd_hi(8) and ex2_lzo_dcd_lo(9 ) ); +u_lzo_dcd_137: ex2_lzo_dcd_b(137) <= not( ex2_lzo_dcd_hi(8) and ex2_lzo_dcd_lo(10) ); +u_lzo_dcd_138: ex2_lzo_dcd_b(138) <= not( ex2_lzo_dcd_hi(8) and ex2_lzo_dcd_lo(11) ); +u_lzo_dcd_139: ex2_lzo_dcd_b(139) <= not( ex2_lzo_dcd_hi(8) and ex2_lzo_dcd_lo(12) ); +u_lzo_dcd_140: ex2_lzo_dcd_b(140) <= not( ex2_lzo_dcd_hi(8) and ex2_lzo_dcd_lo(13) ); +u_lzo_dcd_141: ex2_lzo_dcd_b(141) <= not( ex2_lzo_dcd_hi(8) and ex2_lzo_dcd_lo(14) ); +u_lzo_dcd_142: ex2_lzo_dcd_b(142) <= not( ex2_lzo_dcd_hi(8) and ex2_lzo_dcd_lo(15) ); + +u_lzo_dcd_143: ex2_lzo_dcd_b(143) <= not( ex2_lzo_dcd_hi(9) and ex2_lzo_dcd_lo(0 ) ); +u_lzo_dcd_144: ex2_lzo_dcd_b(144) <= not( ex2_lzo_dcd_hi(9) and ex2_lzo_dcd_lo(1 ) ); +u_lzo_dcd_145: ex2_lzo_dcd_b(145) <= not( ex2_lzo_dcd_hi(9) and ex2_lzo_dcd_lo(2 ) ); +u_lzo_dcd_146: ex2_lzo_dcd_b(146) <= not( ex2_lzo_dcd_hi(9) and ex2_lzo_dcd_lo(3 ) ); +u_lzo_dcd_147: ex2_lzo_dcd_b(147) <= not( ex2_lzo_dcd_hi(9) and ex2_lzo_dcd_lo(4 ) ); +u_lzo_dcd_148: ex2_lzo_dcd_b(148) <= not( ex2_lzo_dcd_hi(9) and ex2_lzo_dcd_lo(5 ) ); +u_lzo_dcd_149: ex2_lzo_dcd_b(149) <= not( ex2_lzo_dcd_hi(9) and ex2_lzo_dcd_lo(6 ) ); +u_lzo_dcd_150: ex2_lzo_dcd_b(150) <= not( ex2_lzo_dcd_hi(9) and ex2_lzo_dcd_lo(7 ) ); +u_lzo_dcd_151: ex2_lzo_dcd_b(151) <= not( ex2_lzo_dcd_hi(9) and ex2_lzo_dcd_lo(8 ) ); +u_lzo_dcd_152: ex2_lzo_dcd_b(152) <= not( ex2_lzo_dcd_hi(9) and ex2_lzo_dcd_lo(9 ) ); +u_lzo_dcd_153: ex2_lzo_dcd_b(153) <= not( ex2_lzo_dcd_hi(9) and ex2_lzo_dcd_lo(10) ); +u_lzo_dcd_154: ex2_lzo_dcd_b(154) <= not( ex2_lzo_dcd_hi(9) and ex2_lzo_dcd_lo(11) ); +u_lzo_dcd_155: ex2_lzo_dcd_b(155) <= not( ex2_lzo_dcd_hi(9) and ex2_lzo_dcd_lo(12) ); +u_lzo_dcd_156: ex2_lzo_dcd_b(156) <= not( ex2_lzo_dcd_hi(9) and ex2_lzo_dcd_lo(13) ); +u_lzo_dcd_157: ex2_lzo_dcd_b(157) <= not( ex2_lzo_dcd_hi(9) and ex2_lzo_dcd_lo(14) ); +u_lzo_dcd_158: ex2_lzo_dcd_b(158) <= not( ex2_lzo_dcd_hi(9) and ex2_lzo_dcd_lo(15) ); + +u_lzo_dcd_159: ex2_lzo_dcd_b(159) <= not( ex2_lzo_dcd_hi(10) and ex2_lzo_dcd_lo(0) ); +u_lzo_dcd_160: ex2_lzo_dcd_b(160) <= not( ex2_lzo_dcd_hi(10) and ex2_lzo_dcd_lo(1) ); +u_lzo_dcd_161: ex2_lzo_dcd_b(161) <= not( ex2_lzo_dcd_hi(10) and ex2_lzo_dcd_lo(2) ); +u_lzo_dcd_162: ex2_lzo_dcd_b(162) <= not( ex2_lzo_dcd_hi(10) and ex2_lzo_dcd_lo(3) ); + + + +f_alg_ex2_sel_byp_b <= not( f_alg_ex2_sel_byp ); +ex2_lzo_nonbyp_0_b <= not( ex2_lzo_nonbyp_0 ); +ex2_lzo_forbyp_0_b <= not( ex2_lzo_forbyp_0 ); + + +u_lzo_din_0: f_lze_ex2_lzo_din( 0) <= not( ( f_alg_ex2_sel_byp or ex2_lzo_nonbyp_0_b ) and + ( f_alg_ex2_sel_byp_b or ex2_lzo_forbyp_0_b ) ); +u_lzo_din_1: f_lze_ex2_lzo_din( 1) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(1) ); +u_lzo_din_2: f_lze_ex2_lzo_din( 2) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(2) ); +u_lzo_din_3: f_lze_ex2_lzo_din( 3) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(3) ); +u_lzo_din_4: f_lze_ex2_lzo_din( 4) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(4) ); +u_lzo_din_5: f_lze_ex2_lzo_din( 5) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(5) ); +u_lzo_din_6: f_lze_ex2_lzo_din( 6) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(6) ); +u_lzo_din_7: f_lze_ex2_lzo_din( 7) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(7) ); +u_lzo_din_8: f_lze_ex2_lzo_din( 8) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(8) ); +u_lzo_din_9: f_lze_ex2_lzo_din( 9) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(9) ); +u_lzo_din_10: f_lze_ex2_lzo_din( 10) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(10) ); +u_lzo_din_11: f_lze_ex2_lzo_din( 11) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(11) ); +u_lzo_din_12: f_lze_ex2_lzo_din( 12) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(12) ); +u_lzo_din_13: f_lze_ex2_lzo_din( 13) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(13) ); +u_lzo_din_14: f_lze_ex2_lzo_din( 14) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(14) ); +u_lzo_din_15: f_lze_ex2_lzo_din( 15) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(15) ); +u_lzo_din_16: f_lze_ex2_lzo_din( 16) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(16) ); +u_lzo_din_17: f_lze_ex2_lzo_din( 17) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(17) ); +u_lzo_din_18: f_lze_ex2_lzo_din( 18) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(18) ); +u_lzo_din_19: f_lze_ex2_lzo_din( 19) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(19) ); +u_lzo_din_20: f_lze_ex2_lzo_din( 20) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(20) ); +u_lzo_din_21: f_lze_ex2_lzo_din( 21) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(21) ); +u_lzo_din_22: f_lze_ex2_lzo_din( 22) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(22) ); +u_lzo_din_23: f_lze_ex2_lzo_din( 23) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(23) ); +u_lzo_din_24: f_lze_ex2_lzo_din( 24) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(24) ); +u_lzo_din_25: f_lze_ex2_lzo_din( 25) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(25) ); +u_lzo_din_26: f_lze_ex2_lzo_din( 26) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(26) ); +u_lzo_din_27: f_lze_ex2_lzo_din( 27) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(27) ); +u_lzo_din_28: f_lze_ex2_lzo_din( 28) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(28) ); +u_lzo_din_29: f_lze_ex2_lzo_din( 29) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(29) ); +u_lzo_din_30: f_lze_ex2_lzo_din( 30) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(30) ); +u_lzo_din_31: f_lze_ex2_lzo_din( 31) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(31) ); +u_lzo_din_32: f_lze_ex2_lzo_din( 32) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(32) ); +u_lzo_din_33: f_lze_ex2_lzo_din( 33) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(33) ); +u_lzo_din_34: f_lze_ex2_lzo_din( 34) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(34) ); +u_lzo_din_35: f_lze_ex2_lzo_din( 35) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(35) ); +u_lzo_din_36: f_lze_ex2_lzo_din( 36) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(36) ); +u_lzo_din_37: f_lze_ex2_lzo_din( 37) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(37) ); +u_lzo_din_38: f_lze_ex2_lzo_din( 38) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(38) ); +u_lzo_din_39: f_lze_ex2_lzo_din( 39) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(39) ); +u_lzo_din_40: f_lze_ex2_lzo_din( 40) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(40) ); +u_lzo_din_41: f_lze_ex2_lzo_din( 41) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(41) ); +u_lzo_din_42: f_lze_ex2_lzo_din( 42) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(42) ); +u_lzo_din_43: f_lze_ex2_lzo_din( 43) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(43) ); +u_lzo_din_44: f_lze_ex2_lzo_din( 44) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(44) ); +u_lzo_din_45: f_lze_ex2_lzo_din( 45) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(45) ); +u_lzo_din_46: f_lze_ex2_lzo_din( 46) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(46) ); +u_lzo_din_47: f_lze_ex2_lzo_din( 47) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(47) ); +u_lzo_din_48: f_lze_ex2_lzo_din( 48) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(48) ); +u_lzo_din_49: f_lze_ex2_lzo_din( 49) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(49) ); +u_lzo_din_50: f_lze_ex2_lzo_din( 50) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(50) ); +u_lzo_din_51: f_lze_ex2_lzo_din( 51) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(51) ); +u_lzo_din_52: f_lze_ex2_lzo_din( 52) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(52) ); +u_lzo_din_53: f_lze_ex2_lzo_din( 53) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(53) ); +u_lzo_din_54: f_lze_ex2_lzo_din( 54) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(54) ); +u_lzo_din_55: f_lze_ex2_lzo_din( 55) <= not ex2_lzo_dcd_b(55) ; +u_lzo_din_56: f_lze_ex2_lzo_din( 56) <= not ex2_lzo_dcd_b(56) ; +u_lzo_din_57: f_lze_ex2_lzo_din( 57) <= not ex2_lzo_dcd_b(57) ; +u_lzo_din_58: f_lze_ex2_lzo_din( 58) <= not ex2_lzo_dcd_b(58) ; +u_lzo_din_59: f_lze_ex2_lzo_din( 59) <= not ex2_lzo_dcd_b(59) ; +u_lzo_din_60: f_lze_ex2_lzo_din( 60) <= not ex2_lzo_dcd_b(60) ; +u_lzo_din_61: f_lze_ex2_lzo_din( 61) <= not ex2_lzo_dcd_b(61) ; +u_lzo_din_62: f_lze_ex2_lzo_din( 62) <= not ex2_lzo_dcd_b(62) ; +u_lzo_din_63: f_lze_ex2_lzo_din( 63) <= not ex2_lzo_dcd_b(63) ; +u_lzo_din_64: f_lze_ex2_lzo_din( 64) <= not ex2_lzo_dcd_b(64) ; +u_lzo_din_65: f_lze_ex2_lzo_din( 65) <= not ex2_lzo_dcd_b(65) ; +u_lzo_din_66: f_lze_ex2_lzo_din( 66) <= not ex2_lzo_dcd_b(66) ; +u_lzo_din_67: f_lze_ex2_lzo_din( 67) <= not ex2_lzo_dcd_b(67) ; +u_lzo_din_68: f_lze_ex2_lzo_din( 68) <= not ex2_lzo_dcd_b(68) ; +u_lzo_din_69: f_lze_ex2_lzo_din( 69) <= not ex2_lzo_dcd_b(69) ; +u_lzo_din_70: f_lze_ex2_lzo_din( 70) <= not ex2_lzo_dcd_b(70) ; +u_lzo_din_71: f_lze_ex2_lzo_din( 71) <= not ex2_lzo_dcd_b(71) ; +u_lzo_din_72: f_lze_ex2_lzo_din( 72) <= not ex2_lzo_dcd_b(72) ; +u_lzo_din_73: f_lze_ex2_lzo_din( 73) <= not ex2_lzo_dcd_b(73) ; +u_lzo_din_74: f_lze_ex2_lzo_din( 74) <= not ex2_lzo_dcd_b(74) ; +u_lzo_din_75: f_lze_ex2_lzo_din( 75) <= not ex2_lzo_dcd_b(75) ; +u_lzo_din_76: f_lze_ex2_lzo_din( 76) <= not ex2_lzo_dcd_b(76) ; +u_lzo_din_77: f_lze_ex2_lzo_din( 77) <= not ex2_lzo_dcd_b(77) ; +u_lzo_din_78: f_lze_ex2_lzo_din( 78) <= not ex2_lzo_dcd_b(78) ; +u_lzo_din_79: f_lze_ex2_lzo_din( 79) <= not ex2_lzo_dcd_b(79) ; +u_lzo_din_80: f_lze_ex2_lzo_din( 80) <= not ex2_lzo_dcd_b(80) ; +u_lzo_din_81: f_lze_ex2_lzo_din( 81) <= not ex2_lzo_dcd_b(81) ; +u_lzo_din_82: f_lze_ex2_lzo_din( 82) <= not ex2_lzo_dcd_b(82) ; +u_lzo_din_83: f_lze_ex2_lzo_din( 83) <= not ex2_lzo_dcd_b(83) ; +u_lzo_din_84: f_lze_ex2_lzo_din( 84) <= not ex2_lzo_dcd_b(84) ; +u_lzo_din_85: f_lze_ex2_lzo_din( 85) <= not ex2_lzo_dcd_b(85) ; +u_lzo_din_86: f_lze_ex2_lzo_din( 86) <= not ex2_lzo_dcd_b(86) ; +u_lzo_din_87: f_lze_ex2_lzo_din( 87) <= not ex2_lzo_dcd_b(87) ; +u_lzo_din_88: f_lze_ex2_lzo_din( 88) <= not ex2_lzo_dcd_b(88) ; +u_lzo_din_89: f_lze_ex2_lzo_din( 89) <= not ex2_lzo_dcd_b(89) ; +u_lzo_din_90: f_lze_ex2_lzo_din( 90) <= not ex2_lzo_dcd_b(90) ; +u_lzo_din_91: f_lze_ex2_lzo_din( 91) <= not ex2_lzo_dcd_b(91) ; +u_lzo_din_92: f_lze_ex2_lzo_din( 92) <= not ex2_lzo_dcd_b(92) ; +u_lzo_din_93: f_lze_ex2_lzo_din( 93) <= not ex2_lzo_dcd_b(93) ; +u_lzo_din_94: f_lze_ex2_lzo_din( 94) <= not ex2_lzo_dcd_b(94) ; +u_lzo_din_95: f_lze_ex2_lzo_din( 95) <= not ex2_lzo_dcd_b(95) ; +u_lzo_din_96: f_lze_ex2_lzo_din( 96) <= not ex2_lzo_dcd_b(96) ; +u_lzo_din_97: f_lze_ex2_lzo_din( 97) <= not ex2_lzo_dcd_b(97) ; +u_lzo_din_98: f_lze_ex2_lzo_din( 98) <= not ex2_lzo_dcd_b(98) ; +u_lzo_din_99: f_lze_ex2_lzo_din( 99) <= not(ex2_lzo_dcd_b(99) and not f_pic_ex2_to_integer ); +u_lzo_din_100: f_lze_ex2_lzo_din(100) <= not ex2_lzo_dcd_b(100) ; +u_lzo_din_101: f_lze_ex2_lzo_din(101) <= not ex2_lzo_dcd_b(101) ; +u_lzo_din_102: f_lze_ex2_lzo_din(102) <= not ex2_lzo_dcd_b(102) ; +u_lzo_din_103: f_lze_ex2_lzo_din(103) <= not ex2_lzo_dcd_b(103) ; +u_lzo_din_104: f_lze_ex2_lzo_din(104) <= not ex2_lzo_dcd_b(104) ; +u_lzo_din_105: f_lze_ex2_lzo_din(105) <= not ex2_lzo_dcd_b(105) ; +u_lzo_din_106: f_lze_ex2_lzo_din(106) <= not ex2_lzo_dcd_b(106) ; +u_lzo_din_107: f_lze_ex2_lzo_din(107) <= not ex2_lzo_dcd_b(107) ; +u_lzo_din_108: f_lze_ex2_lzo_din(108) <= not ex2_lzo_dcd_b(108) ; +u_lzo_din_109: f_lze_ex2_lzo_din(109) <= not ex2_lzo_dcd_b(109) ; +u_lzo_din_110: f_lze_ex2_lzo_din(110) <= not ex2_lzo_dcd_b(110) ; +u_lzo_din_111: f_lze_ex2_lzo_din(111) <= not ex2_lzo_dcd_b(111) ; +u_lzo_din_112: f_lze_ex2_lzo_din(112) <= not ex2_lzo_dcd_b(112) ; +u_lzo_din_113: f_lze_ex2_lzo_din(113) <= not ex2_lzo_dcd_b(113) ; +u_lzo_din_114: f_lze_ex2_lzo_din(114) <= not ex2_lzo_dcd_b(114) ; +u_lzo_din_115: f_lze_ex2_lzo_din(115) <= not ex2_lzo_dcd_b(115) ; +u_lzo_din_116: f_lze_ex2_lzo_din(116) <= not ex2_lzo_dcd_b(116) ; +u_lzo_din_117: f_lze_ex2_lzo_din(117) <= not ex2_lzo_dcd_b(117) ; +u_lzo_din_118: f_lze_ex2_lzo_din(118) <= not ex2_lzo_dcd_b(118) ; +u_lzo_din_119: f_lze_ex2_lzo_din(119) <= not ex2_lzo_dcd_b(119) ; +u_lzo_din_120: f_lze_ex2_lzo_din(120) <= not ex2_lzo_dcd_b(120) ; +u_lzo_din_121: f_lze_ex2_lzo_din(121) <= not ex2_lzo_dcd_b(121) ; +u_lzo_din_122: f_lze_ex2_lzo_din(122) <= not ex2_lzo_dcd_b(122) ; +u_lzo_din_123: f_lze_ex2_lzo_din(123) <= not ex2_lzo_dcd_b(123) ; +u_lzo_din_124: f_lze_ex2_lzo_din(124) <= not ex2_lzo_dcd_b(124) ; +u_lzo_din_125: f_lze_ex2_lzo_din(125) <= not ex2_lzo_dcd_b(125) ; +u_lzo_din_126: f_lze_ex2_lzo_din(126) <= not ex2_lzo_dcd_b(126) ; +u_lzo_din_127: f_lze_ex2_lzo_din(127) <= not ex2_lzo_dcd_b(127) ; +u_lzo_din_128: f_lze_ex2_lzo_din(128) <= not ex2_lzo_dcd_b(128) ; +u_lzo_din_129: f_lze_ex2_lzo_din(129) <= not ex2_lzo_dcd_b(129) ; +u_lzo_din_130: f_lze_ex2_lzo_din(130) <= not ex2_lzo_dcd_b(130) ; +u_lzo_din_131: f_lze_ex2_lzo_din(131) <= not ex2_lzo_dcd_b(131) ; +u_lzo_din_132: f_lze_ex2_lzo_din(132) <= not ex2_lzo_dcd_b(132) ; +u_lzo_din_133: f_lze_ex2_lzo_din(133) <= not ex2_lzo_dcd_b(133) ; +u_lzo_din_134: f_lze_ex2_lzo_din(134) <= not ex2_lzo_dcd_b(134) ; +u_lzo_din_135: f_lze_ex2_lzo_din(135) <= not ex2_lzo_dcd_b(135) ; +u_lzo_din_136: f_lze_ex2_lzo_din(136) <= not ex2_lzo_dcd_b(136) ; +u_lzo_din_137: f_lze_ex2_lzo_din(137) <= not ex2_lzo_dcd_b(137) ; +u_lzo_din_138: f_lze_ex2_lzo_din(138) <= not ex2_lzo_dcd_b(138) ; +u_lzo_din_139: f_lze_ex2_lzo_din(139) <= not ex2_lzo_dcd_b(139) ; +u_lzo_din_140: f_lze_ex2_lzo_din(140) <= not ex2_lzo_dcd_b(140) ; +u_lzo_din_141: f_lze_ex2_lzo_din(141) <= not ex2_lzo_dcd_b(141) ; +u_lzo_din_142: f_lze_ex2_lzo_din(142) <= not ex2_lzo_dcd_b(142) ; +u_lzo_din_143: f_lze_ex2_lzo_din(143) <= not ex2_lzo_dcd_b(143) ; +u_lzo_din_144: f_lze_ex2_lzo_din(144) <= not ex2_lzo_dcd_b(144) ; +u_lzo_din_145: f_lze_ex2_lzo_din(145) <= not ex2_lzo_dcd_b(145) ; +u_lzo_din_146: f_lze_ex2_lzo_din(146) <= not ex2_lzo_dcd_b(146) ; +u_lzo_din_147: f_lze_ex2_lzo_din(147) <= not ex2_lzo_dcd_b(147) ; +u_lzo_din_148: f_lze_ex2_lzo_din(148) <= not ex2_lzo_dcd_b(148) ; +u_lzo_din_149: f_lze_ex2_lzo_din(149) <= not ex2_lzo_dcd_b(149) ; +u_lzo_din_150: f_lze_ex2_lzo_din(150) <= not ex2_lzo_dcd_b(150) ; +u_lzo_din_151: f_lze_ex2_lzo_din(151) <= not ex2_lzo_dcd_b(151) ; +u_lzo_din_152: f_lze_ex2_lzo_din(152) <= not ex2_lzo_dcd_b(152) ; +u_lzo_din_153: f_lze_ex2_lzo_din(153) <= not ex2_lzo_dcd_b(153) ; +u_lzo_din_154: f_lze_ex2_lzo_din(154) <= not ex2_lzo_dcd_b(154) ; +u_lzo_din_155: f_lze_ex2_lzo_din(155) <= not ex2_lzo_dcd_b(155) ; +u_lzo_din_156: f_lze_ex2_lzo_din(156) <= not ex2_lzo_dcd_b(156) ; +u_lzo_din_157: f_lze_ex2_lzo_din(157) <= not ex2_lzo_dcd_b(157) ; +u_lzo_din_158: f_lze_ex2_lzo_din(158) <= not ex2_lzo_dcd_b(158) ; +u_lzo_din_159: f_lze_ex2_lzo_din(159) <= not ex2_lzo_dcd_b(159) ; +u_lzo_din_160: f_lze_ex2_lzo_din(160) <= not ex2_lzo_dcd_b(160) ; +u_lzo_din_161: f_lze_ex2_lzo_din(161) <= not ex2_lzo_dcd_b(161) ; +u_lzo_din_162: f_lze_ex2_lzo_din(162) <= not ex2_lzo_dcd_b(162) ; + + + + + + ex2_ins_est <= f_pic_ex2_est_recip or f_pic_ex2_est_rsqrt ; + + ex2_sh_rgt_en_by <= + ( f_eie_ex2_use_bexp and ex2_expo_neg_sp_by and ex2_lzo_cont_sp and not f_alg_ex2_byp_nonflip and not ex2_ins_est) or + ( f_eie_ex2_use_bexp and ex2_expo_neg_dp_by and ex2_lzo_cont_dp and not f_alg_ex2_byp_nonflip and not ex2_ins_est) ; + ex2_sh_rgt_en_p <= + (not f_eie_ex2_use_bexp and ex2_expo_neg_sp and ex2_lzo_cont_sp and not f_alg_ex2_byp_nonflip) or + (not f_eie_ex2_use_bexp and ex2_expo_neg_dp and ex2_lzo_cont_dp and not f_alg_ex2_byp_nonflip) ; + + ex2_sh_rgt_en <= ex2_sh_rgt_en_by or ex2_sh_rgt_en_p; + + + + + + + + + + ex2_expo_p_sim_p(8 to 13) <= not ex2_expo(8 to 13); + + ex2_expo_p_sim_g(13) <= ex2_expo(13) ; + ex2_expo_p_sim_g(12) <= ex2_expo(13) or ex2_expo(12) ; + ex2_expo_p_sim_g(11) <= ex2_expo(13) or ex2_expo(12) or ex2_expo(11) ; + ex2_expo_p_sim_g(10) <= ex2_expo(13) or ex2_expo(12) or ex2_expo(11) or ex2_expo(10) ; + ex2_expo_p_sim_g( 9) <= ex2_expo(13) or ex2_expo(12) or ex2_expo(11) or ex2_expo(10) or ex2_expo( 9) ; + + ex2_expo_p_sim(13) <= ex2_expo_p_sim_p(13) ; + ex2_expo_p_sim(12) <= ex2_expo_p_sim_p(12) xor ( ex2_expo_p_sim_g(13) ) ; + ex2_expo_p_sim(11) <= ex2_expo_p_sim_p(11) xor ( ex2_expo_p_sim_g(12) ) ; + ex2_expo_p_sim(10) <= ex2_expo_p_sim_p(10) xor ( ex2_expo_p_sim_g(11) ) ; + ex2_expo_p_sim( 9) <= ex2_expo_p_sim_p( 9) xor ( ex2_expo_p_sim_g(10) ) ; + ex2_expo_p_sim( 8) <= ex2_expo_p_sim_p( 8) xor ( ex2_expo_p_sim_g( 9) ); + + + + + ex2_expo_sim_p(8 to 13) <= not ex2_expo_by(8 to 13); + + ex2_expo_sim_g(13) <= ex2_expo_by(13) ; + ex2_expo_sim_g(12) <= ex2_expo_by(13) or ex2_expo_by(12) ; + ex2_expo_sim_g(11) <= ex2_expo_by(13) or ex2_expo_by(12) or ex2_expo_by(11) ; + ex2_expo_sim_g(10) <= ex2_expo_by(13) or ex2_expo_by(12) or ex2_expo_by(11) or ex2_expo_by(10) ; + ex2_expo_sim_g( 9) <= ex2_expo_by(13) or ex2_expo_by(12) or ex2_expo_by(11) or ex2_expo_by(10) or ex2_expo_by( 9) ; + + ex2_expo_sim(13) <= ex2_expo_sim_p(13) ; + ex2_expo_sim(12) <= ex2_expo_sim_p(12) xor ( ex2_expo_sim_g(13) ) ; + ex2_expo_sim(11) <= ex2_expo_sim_p(11) xor ( ex2_expo_sim_g(12) ) ; + ex2_expo_sim(10) <= ex2_expo_sim_p(10) xor ( ex2_expo_sim_g(11) ) ; + ex2_expo_sim( 9) <= ex2_expo_sim_p( 9) xor ( ex2_expo_sim_g(10) ) ; + ex2_expo_sim( 8) <= ex2_expo_sim_p( 8) xor ( ex2_expo_sim_g( 9) ); + + + + ex2_lzo_forbyp_0 <= + ( f_pic_ex2_est_recip ) or + ( f_pic_ex2_est_rsqrt ) or + ( f_alg_ex2_byp_nonflip and not f_pic_ex2_prenorm ) or + (not f_fmt_ex2_pass_msb_dp and not f_pic_ex2_lzo_dis_prod ) or + ( (ex2_expo_neg_dp_by or ex2_dp_001_by) and ex2_lzo_cont_dp ) or + ( (ex2_expo_neg_sp_by or ex2_sp_001_by) and ex2_lzo_cont_sp ) ; + + + + + + ex2_lzo_nonbyp_0 <= ( ex2_lzo_dcd_0 ) or + ( ex2_expo_neg_dp and ex2_lzo_cont_dp) or + ( ex2_expo_neg_sp and ex2_lzo_cont_sp) or + ( f_pic_ex2_est_recip ) or + ( f_pic_ex2_est_rsqrt ) ; + + + + ex2_sh_rgt_amt(0) <= ex2_sh_rgt_en ; + ex2_sh_rgt_amt(1) <= ex2_sh_rgt_en ; + ex2_sh_rgt_amt(2) <= (ex2_sh_rgt_en_p and ex2_expo_p_sim( 8)) or (ex2_sh_rgt_en_by and ex2_expo_sim( 8)); + ex2_sh_rgt_amt(3) <= (ex2_sh_rgt_en_p and ex2_expo_p_sim( 9)) or (ex2_sh_rgt_en_by and ex2_expo_sim( 9)); + ex2_sh_rgt_amt(4) <= (ex2_sh_rgt_en_p and ex2_expo_p_sim(10)) or (ex2_sh_rgt_en_by and ex2_expo_sim(10)); + ex2_sh_rgt_amt(5) <= (ex2_sh_rgt_en_p and ex2_expo_p_sim(11)) or (ex2_sh_rgt_en_by and ex2_expo_sim(11)); + ex2_sh_rgt_amt(6) <= (ex2_sh_rgt_en_p and ex2_expo_p_sim(12)) or (ex2_sh_rgt_en_by and ex2_expo_sim(12)); + ex2_sh_rgt_amt(7) <= (ex2_sh_rgt_en_p and ex2_expo_p_sim(13)) or (ex2_sh_rgt_en_by and ex2_expo_sim(13)); + + + + + ex3_shr_lat: tri_rlmreg_p generic map (width=> 9, expand_type => expand_type, needs_sreset => 0) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(3) , + mpw1_b => mpw1_b(3) , + mpw2_b => mpw2_b(0) , + vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_act, + thold_b => thold_0_b, + sg => sg_0, + scout => ex3_shr_so , + scin => ex3_shr_si , + din(0 to 7) => ex2_sh_rgt_amt(0 to 7), + din(8) => ex2_sh_rgt_en , + dout(0 to 7) => ex3_sh_rgt_amt(0 to 7), + dout(8) => ex3_sh_rgt_en ); + + + + f_lze_ex3_sh_rgt_amt(0 to 7) <= ex3_sh_rgt_amt(0 to 7) ; + f_lze_ex3_sh_rgt_en <= ex3_sh_rgt_en ; + + + + ex3_shr_si(0 to 8) <= ex3_shr_so(1 to 8) & f_lze_si ; + act_si (0 to 4) <= act_so (1 to 4) & ex3_shr_so(0); + f_lze_so <= act_so(0); + + + +end; + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_mad.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_mad.vhdl new file mode 100644 index 0000000..8044340 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_mad.vhdl @@ -0,0 +1,1746 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + + + library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + +entity fuq_mad is +generic( + expand_type : integer := 2 ); +port ( + f_dcd_ex6_cancel :in std_ulogic; + + f_dcd_rf1_bypsel_a_res0 :in std_ulogic; + f_dcd_rf1_bypsel_a_res1 :in std_ulogic; + f_dcd_rf1_bypsel_a_load0 :in std_ulogic; + f_dcd_rf1_bypsel_a_load1 :in std_ulogic; + f_dcd_rf1_bypsel_b_res0 :in std_ulogic; + f_dcd_rf1_bypsel_b_res1 :in std_ulogic; + f_dcd_rf1_bypsel_b_load0 :in std_ulogic; + f_dcd_rf1_bypsel_b_load1 :in std_ulogic; + f_dcd_rf1_bypsel_c_res0 :in std_ulogic; + f_dcd_rf1_bypsel_c_res1 :in std_ulogic; + f_dcd_rf1_bypsel_c_load0 :in std_ulogic; + f_dcd_rf1_bypsel_c_load1 :in std_ulogic; + f_fpr_ex7_frt_sign :in std_ulogic ; + f_fpr_ex7_frt_expo :in std_ulogic_vector (1 to 13); + f_fpr_ex7_frt_frac :in std_ulogic_vector (0 to 52); + f_fpr_ex7_load_sign :in std_ulogic ; + f_fpr_ex7_load_expo :in std_ulogic_vector (3 to 13); + f_fpr_ex7_load_frac :in std_ulogic_vector (0 to 52); + f_fpr_ex6_load_sign :in std_ulogic; + f_fpr_ex6_load_expo :in std_ulogic_vector(3 to 13); + f_fpr_ex6_load_frac :in std_ulogic_vector(0 to 52); + f_fpr_rf1_a_sign :in std_ulogic; + f_fpr_rf1_a_expo :in std_ulogic_vector(1 to 13) ; + f_fpr_rf1_a_frac :in std_ulogic_vector(0 to 52) ; + f_fpr_ex1_a_par :in std_ulogic_vector(0 to 7); + + f_fpr_rf1_c_sign :in std_ulogic; + f_fpr_rf1_c_expo :in std_ulogic_vector(1 to 13) ; + f_fpr_rf1_c_frac :in std_ulogic_vector(0 to 52) ; + f_fpr_ex1_c_par :in std_ulogic_vector(0 to 7); + + f_fpr_rf1_b_sign :in std_ulogic; + f_fpr_rf1_b_expo :in std_ulogic_vector(1 to 13) ; + f_fpr_rf1_b_frac :in std_ulogic_vector(0 to 52) ; + f_fpr_ex1_b_par :in std_ulogic_vector(0 to 7); + + f_dcd_rf1_aop_valid :in std_ulogic; + f_dcd_rf1_cop_valid :in std_ulogic; + f_dcd_rf1_bop_valid :in std_ulogic; + f_dcd_rf1_sp :in std_ulogic; + f_dcd_rf1_emin_dp :in std_ulogic; + f_dcd_rf1_emin_sp :in std_ulogic; + f_dcd_rf1_force_pass_b :in std_ulogic; + + f_dcd_rf1_fsel_b :in std_ulogic; + f_dcd_rf1_from_integer_b :in std_ulogic; + f_dcd_rf1_to_integer_b :in std_ulogic; + f_dcd_rf1_rnd_to_int_b :in std_ulogic; + f_dcd_rf1_math_b :in std_ulogic; + f_dcd_rf1_est_recip_b :in std_ulogic; + f_dcd_rf1_est_rsqrt_b :in std_ulogic; + f_dcd_rf1_move_b :in std_ulogic; + f_dcd_rf1_prenorm_b :in std_ulogic; + f_dcd_rf1_frsp_b :in std_ulogic; + f_dcd_rf1_compare_b :in std_ulogic; + f_dcd_rf1_ordered_b :in std_ulogic; + + f_dcd_rf1_pow2e_b :in std_ulogic; + f_dcd_rf1_log2e_b :in std_ulogic; + + f_dcd_rf1_ftdiv :in std_ulogic; + f_dcd_rf1_ftsqrt :in std_ulogic; + + + f_dcd_rf1_nj_deno :in std_ulogic; + f_dcd_rf1_nj_deni :in std_ulogic; + + f_dcd_rf1_sp_conv_b :in std_ulogic; + f_dcd_rf1_word_b :in std_ulogic; + f_dcd_rf1_uns_b :in std_ulogic; + f_dcd_rf1_sub_op_b :in std_ulogic; + + f_dcd_rf1_force_excp_dis :in std_ulogic; + + f_dcd_rf1_op_rnd_v_b :in std_ulogic; + f_dcd_rf1_op_rnd_b :in std_ulogic_vector(0 to 1); + f_dcd_rf1_inv_sign_b :in std_ulogic; + f_dcd_rf1_sign_ctl_b :in std_ulogic_vector(0 to 1); + f_dcd_rf1_sgncpy_b :in std_ulogic; + + f_dcd_rf1_fpscr_bit_data_b :in std_ulogic_vector(0 to 3); + f_dcd_rf1_fpscr_bit_mask_b :in std_ulogic_vector(0 to 3); + f_dcd_rf1_fpscr_nib_mask_b :in std_ulogic_vector(0 to 8); + + f_dcd_rf1_mv_to_scr_b :in std_ulogic; + f_dcd_rf1_mv_from_scr_b :in std_ulogic; + f_dcd_rf1_mtfsbx_b :in std_ulogic; + f_dcd_rf1_mcrfs_b :in std_ulogic; + f_dcd_rf1_mtfsf_b :in std_ulogic; + f_dcd_rf1_mtfsfi_b :in std_ulogic; + + f_dcd_ex1_perr_force_c :in std_ulogic; + f_dcd_ex1_perr_fsel_ovrd :in std_ulogic; + + f_dcd_rf1_uc_fc_hulp :in std_ulogic; + f_dcd_rf1_uc_fa_pos :in std_ulogic; + f_dcd_rf1_uc_fc_pos :in std_ulogic; + f_dcd_rf1_uc_fb_pos :in std_ulogic; + f_dcd_rf1_uc_fc_0_5 :in std_ulogic; + f_dcd_rf1_uc_fc_1_0 :in std_ulogic; + f_dcd_rf1_uc_fc_1_minus :in std_ulogic; + f_dcd_rf1_uc_fb_1_0 :in std_ulogic; + f_dcd_rf1_uc_fb_0_75 :in std_ulogic; + f_dcd_rf1_uc_fb_0_5 :in std_ulogic; + f_dcd_rf1_uc_ft_pos :in std_ulogic; + f_dcd_rf1_uc_ft_neg :in std_ulogic; + + f_dcd_rf1_div_beg :in std_ulogic; + f_dcd_rf1_sqrt_beg :in std_ulogic; + f_dcd_rf1_uc_mid :in std_ulogic; + f_dcd_rf1_uc_end :in std_ulogic; + f_dcd_rf1_uc_special :in std_ulogic; + f_dcd_ex2_uc_zx :in std_ulogic; + f_dcd_ex2_uc_vxidi :in std_ulogic; + f_dcd_ex2_uc_vxzdz :in std_ulogic; + f_dcd_ex2_uc_vxsqrt :in std_ulogic; + f_dcd_ex2_uc_vxsnan :in std_ulogic; + + f_dcd_ex2_uc_inc_lsb :in std_ulogic; + f_dcd_ex2_uc_gs_v :in std_ulogic; + f_dcd_ex2_uc_gs :in std_ulogic_vector(0 to 1); + + f_mad_ex6_uc_sign :out std_ulogic; + f_mad_ex6_uc_zero :out std_ulogic; + f_mad_ex3_uc_special :out std_ulogic; + f_mad_ex3_uc_zx :out std_ulogic; + f_mad_ex3_uc_vxidi :out std_ulogic; + f_mad_ex3_uc_vxzdz :out std_ulogic; + f_mad_ex3_uc_vxsqrt :out std_ulogic; + f_mad_ex3_uc_vxsnan :out std_ulogic; + f_mad_ex3_uc_res_sign :out std_ulogic; + f_mad_ex3_uc_round_mode :out std_ulogic_vector(0 to 1); + + f_mad_ex2_a_parity_check :out std_ulogic; + f_mad_ex2_c_parity_check :out std_ulogic; + f_mad_ex2_b_parity_check :out std_ulogic; + + + f_ex2_b_den_flush :out std_ulogic ; + + f_scr_ex7_cr_fld :out std_ulogic_vector (0 to 3) ; + f_add_ex4_fpcc_iu :out std_ulogic_vector (0 to 3) ; + f_pic_ex5_fpr_wr_dis_b :out std_ulogic ; + f_rnd_ex6_res_expo :out std_ulogic_vector (1 to 13) ; + f_rnd_ex6_res_frac :out std_ulogic_vector (0 to 52) ; + f_rnd_ex6_res_sign :out std_ulogic ; + f_scr_ex7_fx_thread0 :out std_ulogic_vector (0 to 3) ; + f_scr_ex7_fx_thread1 :out std_ulogic_vector (0 to 3) ; + f_scr_ex7_fx_thread2 :out std_ulogic_vector (0 to 3) ; + f_scr_ex7_fx_thread3 :out std_ulogic_vector (0 to 3) ; + + rf1_thread_b :in std_ulogic_vector(0 to 3) ; + f_dcd_rf1_act :in std_ulogic; + vdd : inout power_logic; + gnd : inout power_logic; + scan_in :in std_ulogic_vector(0 to 17); + scan_out :out std_ulogic_vector(0 to 17); + + clkoff_b :in std_ulogic; + act_dis :in std_ulogic; + flush :in std_ulogic; + delay_lclkr :in std_ulogic_vector(1 to 7); + mpw1_b :in std_ulogic_vector(1 to 7); + mpw2_b :in std_ulogic_vector(0 to 1); + thold_1 :in std_ulogic; + sg_1 :in std_ulogic; + fpu_enable :in std_ulogic; + nclk :in clk_logic +); + +end fuq_mad; + + +architecture fuq_mad of fuq_mad is + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal f_fmt_ex1_inf_and_beyond_sp :std_ulogic ; + signal perv_eie_sg_1 :std_ulogic; + signal perv_eov_sg_1 :std_ulogic; + signal perv_fmt_sg_1 :std_ulogic; + signal perv_mul_sg_1 :std_ulogic; + signal perv_alg_sg_1 :std_ulogic; + signal perv_add_sg_1 :std_ulogic; + signal perv_lza_sg_1 :std_ulogic; + signal perv_nrm_sg_1 :std_ulogic; + signal perv_rnd_sg_1 :std_ulogic; + signal perv_scr_sg_1 :std_ulogic; + signal perv_pic_sg_1 :std_ulogic; + signal perv_cr2_sg_1 :std_ulogic; + signal perv_eie_thold_1 :std_ulogic; + signal perv_eov_thold_1 :std_ulogic; + signal perv_fmt_thold_1 :std_ulogic; + signal perv_mul_thold_1 :std_ulogic; + signal perv_alg_thold_1 :std_ulogic; + signal perv_add_thold_1 :std_ulogic; + signal perv_lza_thold_1 :std_ulogic; + signal perv_nrm_thold_1 :std_ulogic; + signal perv_rnd_thold_1 :std_ulogic; + signal perv_scr_thold_1 :std_ulogic; + signal perv_pic_thold_1 :std_ulogic; + signal perv_cr2_thold_1 :std_ulogic; + signal perv_eie_fpu_enable :std_ulogic; + signal perv_eov_fpu_enable :std_ulogic; + signal perv_fmt_fpu_enable :std_ulogic; + signal perv_mul_fpu_enable :std_ulogic; + signal perv_alg_fpu_enable :std_ulogic; + signal perv_add_fpu_enable :std_ulogic; + signal perv_lza_fpu_enable :std_ulogic; + signal perv_nrm_fpu_enable :std_ulogic; + signal perv_rnd_fpu_enable :std_ulogic; + signal perv_scr_fpu_enable :std_ulogic; + signal perv_pic_fpu_enable :std_ulogic; + signal perv_cr2_fpu_enable :std_ulogic; + + + + signal f_eov_ex4_may_ovf :std_ulogic ; + signal f_add_ex4_flag_eq :std_ulogic ; + signal f_add_ex4_flag_gt :std_ulogic ; + signal f_add_ex4_flag_lt :std_ulogic ; + signal f_add_ex4_flag_nan :std_ulogic ; + signal f_add_ex4_res :std_ulogic_vector (0 to 162) ; + signal f_add_ex4_sign_carry :std_ulogic ; + signal f_add_ex4_sticky :std_ulogic ; + signal f_add_ex4_to_int_ovf_dw :std_ulogic_vector(0 to 1) ; + signal f_add_ex4_to_int_ovf_wd :std_ulogic_vector(0 to 1) ; + signal f_alg_ex2_effsub_eac_b :std_ulogic ; + signal f_alg_ex2_prod_z :std_ulogic ; + signal f_alg_ex2_res :std_ulogic_vector (0 to 162) ; + signal f_alg_ex2_sel_byp :std_ulogic ; + signal f_alg_ex2_sh_ovf :std_ulogic ; + signal f_alg_ex2_sh_unf :std_ulogic ; + signal f_alg_ex3_frc_sel_p1 :std_ulogic ; + signal f_alg_ex3_int_fi :std_ulogic ; + signal f_alg_ex3_int_fr :std_ulogic ; + signal f_alg_ex3_sticky :std_ulogic ; + + signal f_byp_fmt_ex1_a_expo :std_ulogic_vector (1 to 13) ; + signal f_byp_eie_ex1_a_expo :std_ulogic_vector (1 to 13) ; + signal f_byp_alg_ex1_a_expo :std_ulogic_vector (1 to 13) ; + signal f_byp_fmt_ex1_b_expo :std_ulogic_vector (1 to 13) ; + signal f_byp_eie_ex1_b_expo :std_ulogic_vector (1 to 13) ; + signal f_byp_alg_ex1_b_expo :std_ulogic_vector (1 to 13) ; + signal f_byp_fmt_ex1_c_expo :std_ulogic_vector (1 to 13) ; + signal f_byp_eie_ex1_c_expo :std_ulogic_vector (1 to 13) ; + signal f_byp_alg_ex1_c_expo :std_ulogic_vector (1 to 13) ; + signal f_byp_fmt_ex1_a_frac :std_ulogic_vector (0 to 52) ; + signal f_byp_fmt_ex1_c_frac :std_ulogic_vector (0 to 52) ; + signal f_byp_fmt_ex1_b_frac :std_ulogic_vector (0 to 52) ; + signal f_byp_mul_ex1_a_frac :std_ulogic_vector (0 to 52) ; + signal f_byp_mul_ex1_a_frac_17 :std_ulogic ; + signal f_byp_mul_ex1_a_frac_35 :std_ulogic ; + signal f_byp_mul_ex1_c_frac :std_ulogic_vector (0 to 53) ; + signal f_byp_alg_ex1_b_frac :std_ulogic_vector (0 to 52) ; + signal f_byp_fmt_ex1_a_sign :std_ulogic ; + signal f_byp_fmt_ex1_b_sign :std_ulogic ; + signal f_byp_fmt_ex1_c_sign :std_ulogic ; + signal f_byp_pic_ex1_a_sign :std_ulogic ; + signal f_byp_pic_ex1_b_sign :std_ulogic ; + signal f_byp_pic_ex1_c_sign :std_ulogic ; + signal f_byp_alg_ex1_b_sign :std_ulogic ; + + signal f_cr2_ex1_fpscr_shadow :std_ulogic_vector(0 to 7) ; + signal f_pic_ex2_rnd_inf_ok :std_ulogic ; + signal f_pic_ex2_rnd_nr :std_ulogic ; + signal f_cr2_ex3_fpscr_bit_data_b :std_ulogic_vector(0 to 3); + signal f_cr2_ex3_fpscr_bit_mask_b :std_ulogic_vector(0 to 3); + signal f_cr2_ex3_fpscr_nib_mask_b :std_ulogic_vector(0 to 8); + signal f_cr2_ex3_mcrfs_b :std_ulogic ; + signal f_cr2_ex3_mtfsbx_b :std_ulogic ; + signal f_cr2_ex3_mtfsf_b :std_ulogic ; + signal f_cr2_ex3_mtfsfi_b :std_ulogic ; + signal f_cr2_ex3_thread_b :std_ulogic_vector(0 to 3); + signal f_pic_add_ex1_act_b :std_ulogic ; + signal f_pic_alg_ex1_act :std_ulogic ; + signal f_pic_cr2_ex1_act :std_ulogic ; + signal f_pic_eie_ex1_act :std_ulogic ; + signal f_pic_eov_ex2_act_b :std_ulogic ; + signal f_pic_ex1_effsub_raw :std_ulogic ; + signal f_pic_ex1_from_integer :std_ulogic ; + signal f_pic_ex1_fsel :std_ulogic ; + signal f_pic_ex1_sh_ovf_do :std_ulogic ; + signal f_pic_ex1_sh_ovf_ig_b :std_ulogic ; + signal f_pic_ex1_sh_unf_do :std_ulogic ; + signal f_pic_ex1_sh_unf_ig_b :std_ulogic ; + signal f_pic_ex2_force_sel_bexp :std_ulogic ; + signal f_pic_ex2_lzo_dis_prod :std_ulogic ; + signal f_pic_ex2_sp_b :std_ulogic ; + signal f_pic_ex2_sp_lzo :std_ulogic ; + signal f_pic_ex2_to_integer :std_ulogic ; + signal f_pic_ex2_prenorm :std_ulogic ; + signal f_pic_ex3_cmp_sgnneg :std_ulogic ; + signal f_pic_ex3_cmp_sgnpos :std_ulogic ; + signal f_pic_ex3_is_eq :std_ulogic ; + signal f_pic_ex3_is_gt :std_ulogic ; + signal f_pic_ex3_is_lt :std_ulogic ; + signal f_pic_ex3_is_nan :std_ulogic ; + signal f_pic_ex3_sel_est :std_ulogic ; + signal f_pic_ex3_sp_b :std_ulogic ; + signal f_pic_ex4_nj_deno :std_ulogic ; + signal f_pic_ex4_oe :std_ulogic ; + signal f_pic_ex4_ov_en :std_ulogic ; + signal f_pic_ex4_ovf_en_oe0_b :std_ulogic ; + signal f_pic_ex4_ovf_en_oe1_b :std_ulogic ; + signal f_pic_ex4_quiet_b :std_ulogic ; + signal f_pic_ex5_uc_inc_lsb :std_ulogic ; + signal f_pic_ex5_uc_guard :std_ulogic ; + signal f_pic_ex5_uc_sticky :std_ulogic ; + signal f_pic_ex5_uc_g_v :std_ulogic ; + signal f_pic_ex5_uc_s_v :std_ulogic ; + signal f_pic_ex4_rnd_inf_ok_b :std_ulogic ; + signal f_pic_ex4_rnd_ni_b :std_ulogic ; + signal f_pic_ex4_rnd_nr_b :std_ulogic ; + signal f_pic_ex4_sel_est_b :std_ulogic ; + signal f_pic_ex4_sel_fpscr_b :std_ulogic ; + signal f_pic_ex4_sp_b :std_ulogic ; + signal f_pic_ex4_spec_inf_b :std_ulogic ; + signal f_pic_ex4_spec_sel_k_e :std_ulogic ; + signal f_pic_ex4_spec_sel_k_f :std_ulogic ; + signal f_pic_ex4_to_int_ov_all :std_ulogic ; + signal f_pic_ex4_to_integer_b :std_ulogic ; + signal f_pic_ex4_word_b :std_ulogic ; + signal f_pic_ex4_uns_b :std_ulogic ; + signal f_pic_ex4_ue :std_ulogic ; + signal f_pic_ex4_uf_en :std_ulogic ; + signal f_pic_ex4_unf_en_ue0_b :std_ulogic ; + signal f_pic_ex4_unf_en_ue1_b :std_ulogic ; + signal f_pic_ex5_en_exact_zero :std_ulogic ; + signal f_pic_ex5_compare_b :std_ulogic ; + signal f_pic_ex2_ue1 :std_ulogic ; + signal f_pic_ex2_frsp_ue1 :std_ulogic ; + signal f_pic_ex1_frsp_ue1 :std_ulogic ; + signal f_pic_ex5_frsp :std_ulogic ; + signal f_pic_ex5_fi_pipe_v_b :std_ulogic ; + signal f_pic_ex5_fi_spec_b :std_ulogic ; + signal f_pic_ex5_flag_vxcvi_b :std_ulogic ; + signal f_pic_ex5_flag_vxidi_b :std_ulogic ; + signal f_pic_ex5_flag_vximz_b :std_ulogic ; + signal f_pic_ex5_flag_vxisi_b :std_ulogic ; + signal f_pic_ex5_flag_vxsnan_b :std_ulogic ; + signal f_pic_ex5_flag_vxsqrt_b :std_ulogic ; + signal f_pic_ex5_flag_vxvc_b :std_ulogic ; + signal f_pic_ex5_flag_vxzdz_b :std_ulogic ; + signal f_pic_ex5_flag_zx_b :std_ulogic ; + signal f_pic_ex5_fprf_hold_b :std_ulogic ; + signal f_pic_ex5_fprf_pipe_v_b :std_ulogic ; + signal f_pic_ex5_fprf_spec_b :std_ulogic_vector (0 to 4) ; + signal f_pic_ex5_fr_pipe_v_b :std_ulogic ; + signal f_pic_ex5_fr_spec_b :std_ulogic ; + signal f_pic_ex5_invert_sign :std_ulogic ; + signal f_pic_ex4_byp_prod_nz :std_ulogic ; + signal f_pic_ex5_k_nan :std_ulogic ; + signal f_pic_ex5_k_inf :std_ulogic ; + signal f_pic_ex5_k_max :std_ulogic ; + signal f_pic_ex5_k_zer :std_ulogic ; + signal f_pic_ex5_k_one :std_ulogic ; + signal f_pic_ex5_k_int_maxpos :std_ulogic ; + signal f_pic_ex5_k_int_maxneg :std_ulogic ; + signal f_pic_ex5_k_int_zer :std_ulogic ; + signal f_pic_ex5_ox_pipe_v_b :std_ulogic ; + signal f_pic_ex5_round_sign :std_ulogic ; + signal f_pic_ex5_scr_upd_move_b :std_ulogic ; + signal f_pic_ex5_scr_upd_pipe_b :std_ulogic ; + signal f_pic_ex5_ux_pipe_v_b :std_ulogic ; + signal f_pic_fmt_ex1_act :std_ulogic ; + signal f_pic_lza_ex1_act_b :std_ulogic ; + signal f_pic_mul_ex1_act :std_ulogic ; + signal f_pic_nrm_ex3_act_b :std_ulogic ; + signal f_pic_rnd_ex3_act_b :std_ulogic ; + signal f_pic_scr_ex2_act_b :std_ulogic ; + signal f_eie_ex2_dw_ov :std_ulogic ; + signal f_eie_ex2_dw_ov_if :std_ulogic ; + signal f_eie_ex2_lzo_expo :std_ulogic_vector (1 to 13) ; + signal f_eie_ex2_b_expo :std_ulogic_vector (1 to 13) ; + signal f_eie_ex2_tbl_expo :std_ulogic_vector (1 to 13) ; + signal f_eie_ex2_wd_ov :std_ulogic ; + signal f_eie_ex2_wd_ov_if :std_ulogic ; + signal f_eie_ex3_iexp :std_ulogic_vector (1 to 13) ; + signal f_eov_ex5_expo_p0 :std_ulogic_vector (1 to 13) ; + signal f_eov_ex5_expo_p0_ue1oe1 :std_ulogic_vector (3 to 7) ; + signal f_eov_ex5_expo_p1 :std_ulogic_vector (1 to 13) ; + signal f_eov_ex5_expo_p1_ue1oe1 :std_ulogic_vector (3 to 7) ; + signal f_eov_ex5_ovf_expo :std_ulogic ; + signal f_eov_ex5_ovf_if_expo :std_ulogic ; + signal f_eov_ex5_sel_k_e :std_ulogic ; + signal f_eov_ex5_sel_k_f :std_ulogic ; + signal f_eov_ex5_sel_kif_e :std_ulogic ; + signal f_eov_ex5_sel_kif_f :std_ulogic ; + signal f_eov_ex5_unf_expo :std_ulogic ; + signal f_fmt_ex1_a_expo_max :std_ulogic ; + signal f_fmt_ex1_a_zero :std_ulogic ; + signal f_fmt_ex1_a_frac_msb :std_ulogic ; + signal f_fmt_ex1_a_frac_zero :std_ulogic ; + signal f_fmt_ex1_b_expo_max :std_ulogic ; + signal f_fmt_ex1_b_zero :std_ulogic ; + signal f_fmt_ex1_b_frac_msb :std_ulogic ; + signal f_fmt_ex1_b_frac_z32 :std_ulogic; + signal f_fmt_ex1_b_frac_zero :std_ulogic ; + signal f_fmt_ex1_bop_byt :std_ulogic_vector(45 to 52) ; + signal f_fmt_ex1_c_expo_max :std_ulogic ; + signal f_fmt_ex1_c_zero :std_ulogic ; + signal f_fmt_ex1_c_frac_msb :std_ulogic ; + signal f_fmt_ex1_c_frac_zero :std_ulogic ; + signal f_fmt_ex1_sp_invalid :std_ulogic ; + signal f_fmt_ex1_pass_sel :std_ulogic ; + signal f_fmt_ex1_prod_zero :std_ulogic ; + signal f_fmt_ex2_fsel_bsel :std_ulogic ; + signal f_fmt_ex2_pass_frac :std_ulogic_vector (0 to 52) ; + signal f_fmt_ex2_pass_sign :std_ulogic ; + signal f_fmt_ex2_pass_msb :std_ulogic ; + signal f_fmt_ex1_b_imp :std_ulogic ; + signal f_lza_ex4_lza_amt :std_ulogic_vector (0 to 7) ; + signal f_lza_ex4_lza_dcd64_cp1 :std_ulogic_vector(0 to 2); + signal f_lza_ex4_lza_dcd64_cp2 :std_ulogic_vector(0 to 1); + signal f_lza_ex4_lza_dcd64_cp3 :std_ulogic_vector(0 to 0); + signal f_lza_ex4_sh_rgt_en :std_ulogic; + signal f_lza_ex4_sh_rgt_en_eov :std_ulogic; + signal f_lza_ex4_lza_amt_eov :std_ulogic_vector (0 to 7) ; + signal f_lza_ex4_no_lza_edge :std_ulogic ; + signal f_mul_ex2_car :std_ulogic_vector (1 to 108) ; + signal f_mul_ex2_sum :std_ulogic_vector (1 to 108) ; + signal f_nrm_ex4_extra_shift :std_ulogic ; + signal f_nrm_ex5_exact_zero :std_ulogic ; + signal f_nrm_ex5_fpscr_wr_dat :std_ulogic_vector (0 to 31) ; + signal f_nrm_ex5_fpscr_wr_dat_dfp :std_ulogic_vector (0 to 3) ; + signal f_nrm_ex5_int_lsbs :std_ulogic_vector (1 to 12) ; + signal f_nrm_ex5_int_sign :std_ulogic; + signal f_nrm_ex5_nrm_guard_dp :std_ulogic ; + signal f_nrm_ex5_nrm_guard_sp :std_ulogic ; + signal f_nrm_ex5_nrm_lsb_dp :std_ulogic ; + signal f_nrm_ex5_nrm_lsb_sp :std_ulogic ; + signal f_nrm_ex5_nrm_sticky_dp :std_ulogic ; + signal f_nrm_ex5_nrm_sticky_sp :std_ulogic ; + signal f_nrm_ex5_res :std_ulogic_vector (0 to 52) ; + signal f_rnd_ex6_flag_den :std_ulogic ; + signal f_rnd_ex6_flag_fi :std_ulogic ; + signal f_rnd_ex6_flag_inf :std_ulogic ; + signal f_rnd_ex6_flag_ox :std_ulogic ; + signal f_rnd_ex6_flag_sgn :std_ulogic ; + signal f_rnd_ex6_flag_up :std_ulogic ; + signal f_rnd_ex6_flag_ux :std_ulogic ; + signal f_rnd_ex6_flag_zer :std_ulogic ; + signal f_sa3_ex3_c_lza :std_ulogic_vector (53 to 161) ; + signal f_sa3_ex3_s_lza :std_ulogic_vector (0 to 162) ; + signal f_sa3_ex3_c_add :std_ulogic_vector (53 to 161) ; + signal f_sa3_ex3_s_add :std_ulogic_vector (0 to 162) ; + signal f_scr_ex5_fpscr_rd_dat_dfp :std_ulogic_vector (0 to 3) ; + signal f_scr_ex5_fpscr_rd_dat :std_ulogic_vector (0 to 31) ; + signal f_cr2_ex5_fpscr_rd_dat :std_ulogic_vector (24 to 31) ; + signal f_cr2_ex6_fpscr_rd_dat :std_ulogic_vector (24 to 31) ; + signal f_pic_tbl_ex1_act :std_ulogic; + + + signal f_pic_ex2_math_bzer_b :std_ulogic; + signal perv_sa3_thold_1 :std_ulogic; + signal perv_sa3_sg_1 :std_ulogic; + signal perv_sa3_fpu_enable :std_ulogic; + signal f_pic_ex2_b_valid :std_ulogic; + signal f_alg_ex2_byp_nonflip :std_ulogic; + signal f_pic_ex1_rnd_to_int :std_ulogic; + signal f_eie_ex2_lt_bias :std_ulogic; + signal f_eie_ex2_eq_bias_m1 :std_ulogic; + signal f_pic_ex2_est_recip :std_ulogic; + signal f_pic_ex2_est_rsqrt :std_ulogic; +signal f_tbe_ex3_may_ov :std_ulogic; +signal f_tbe_ex3_res_expo :std_ulogic_vector(1 to 13); +signal perv_tbe_sg_1, perv_tbe_thold_1, perv_tbe_fpu_enable :std_ulogic; +signal perv_tbl_sg_1, perv_tbl_thold_1, perv_tbl_fpu_enable :std_ulogic; +signal f_tbe_ex3_recip_2046 :std_ulogic; +signal f_tbe_ex3_recip_2045 :std_ulogic; +signal f_fmt_ex1_b_frac :std_ulogic_vector(1 to 19); +signal f_tbl_ex5_est_frac :std_ulogic_vector(0 to 26); +signal f_tbl_ex5_recip_den :std_ulogic; +signal f_eie_ex2_use_bexp :std_ulogic; +signal rnd_ex6_res_sign :std_ulogic; +signal rnd_ex6_res_expo :std_ulogic_vector(1 to 13); +signal rnd_ex6_res_frac :std_ulogic_vector(0 to 52); +signal f_pic_ex1_flush_en_dp, f_pic_ex1_flush_en_sp, f_pic_ex1_ftdiv :std_ulogic; +signal f_fmt_ex2_lu_den_recip , f_fmt_ex2_lu_den_rsqrto :std_ulogic; +signal f_tbe_ex3_recip_2044, f_tbe_ex3_lu_sh :std_ulogic; + +signal f_lze_ex2_lzo_din :std_ulogic_vector(0 to 162); +signal f_lze_ex3_sh_rgt_amt :std_ulogic_vector(0 to 7) ; +signal f_lze_ex3_sh_rgt_en :std_ulogic; +signal f_alg_ex1_sign_frmw :std_ulogic; +signal f_tbe_ex3_match_en_sp , f_tbe_ex3_match_en_dp :std_ulogic; +signal f_tbl_ex4_unf_expo :std_ulogic; +signal f_tbe_ex3_recip_ue1 :std_ulogic ; +signal f_fmt_ex1_bexpu_le126 :std_ulogic ; +signal f_fmt_ex1_gt126 :std_ulogic ; +signal f_fmt_ex1_ge128 :std_ulogic ; +signal f_gst_ex5_logexp_v :std_ulogic ; +signal f_gst_ex5_logexp_sign :std_ulogic ; +signal f_gst_ex5_logexp_exp :std_ulogic_vector(1 to 11); +signal f_gst_ex5_logexp_fract :std_ulogic_vector(0 to 19); +signal f_fmt_ex1_b_sign_gst :std_ulogic; +signal f_fmt_ex1_b_expo_gst_b :std_ulogic_vector(1 to 13); +signal f_pic_ex1_log2e :std_ulogic; +signal f_pic_ex1_pow2e :std_ulogic; +signal f_mad_ex2_uc_a_expo_den , f_mad_ex2_uc_a_expo_den_sp :std_ulogic; +signal f_pic_ex1_nj_deni :std_ulogic; +signal f_fmt_ex2_ae_ge_54, f_fmt_ex2_be_ge_54, f_fmt_ex2_be_ge_2, f_fmt_ex2_be_ge_2044, f_fmt_ex2_tdiv_rng_chk :std_ulogic ; +signal f_fmt_ex2_be_den :std_ulogic; + + +begin + + + + + +fbyp : entity WORK.fuq_byp(fuq_byp) generic map( expand_type => expand_type) port map( + vdd => vdd , + gnd => gnd , + nclk => nclk , + clkoff_b => clkoff_b , + act_dis => act_dis , + flush => flush , + delay_lclkr => delay_lclkr(1) , + mpw1_b => mpw1_b(1) , + mpw2_b => mpw2_b(0) , + thold_1 => perv_fmt_thold_1 , + sg_1 => perv_fmt_sg_1 , + fpu_enable => perv_fmt_fpu_enable , + + f_byp_si => scan_in(0) , + f_byp_so => scan_out(0) , + rf1_act => f_dcd_rf1_act , + + f_fpr_ex7_frt_sign => f_fpr_ex7_frt_sign , + f_fpr_ex7_frt_expo(1 to 13) => f_fpr_ex7_frt_expo(1 to 13) , + f_fpr_ex7_frt_frac(0 to 52) => f_fpr_ex7_frt_frac(0 to 52) , + f_fpr_ex7_load_sign => f_fpr_ex7_load_sign , + f_fpr_ex7_load_expo(3 to 13) => f_fpr_ex7_load_expo(3 to 13) , + f_fpr_ex7_load_frac(0 to 52) => f_fpr_ex7_load_frac(0 to 52) , + + f_dcd_rf1_div_beg => f_dcd_rf1_div_beg , + f_dcd_rf1_uc_fa_pos => f_dcd_rf1_uc_fa_pos , + f_dcd_rf1_uc_fc_pos => f_dcd_rf1_uc_fc_pos , + f_dcd_rf1_uc_fb_pos => f_dcd_rf1_uc_fb_pos , + f_dcd_rf1_uc_fc_0_5 => f_dcd_rf1_uc_fc_0_5 , + f_dcd_rf1_uc_fc_1_0 => f_dcd_rf1_uc_fc_1_0 , + f_dcd_rf1_uc_fc_1_minus => f_dcd_rf1_uc_fc_1_minus , + f_dcd_rf1_uc_fb_1_0 => f_dcd_rf1_uc_fb_1_0 , + f_dcd_rf1_uc_fb_0_75 => f_dcd_rf1_uc_fb_0_75 , + f_dcd_rf1_uc_fb_0_5 => f_dcd_rf1_uc_fb_0_5 , + + f_dcd_rf1_uc_fc_hulp => f_dcd_rf1_uc_fc_hulp , + f_dcd_rf1_bypsel_a_res0 => f_dcd_rf1_bypsel_a_res0 , + f_dcd_rf1_bypsel_a_res1 => f_dcd_rf1_bypsel_a_res1 , + f_dcd_rf1_bypsel_a_load0 => f_dcd_rf1_bypsel_a_load0 , + f_dcd_rf1_bypsel_a_load1 => f_dcd_rf1_bypsel_a_load1 , + f_dcd_rf1_bypsel_b_res0 => f_dcd_rf1_bypsel_b_res0 , + f_dcd_rf1_bypsel_b_res1 => f_dcd_rf1_bypsel_b_res1 , + f_dcd_rf1_bypsel_b_load0 => f_dcd_rf1_bypsel_b_load0 , + f_dcd_rf1_bypsel_b_load1 => f_dcd_rf1_bypsel_b_load1 , + f_dcd_rf1_bypsel_c_res0 => f_dcd_rf1_bypsel_c_res0 , + f_dcd_rf1_bypsel_c_res1 => f_dcd_rf1_bypsel_c_res1 , + f_dcd_rf1_bypsel_c_load0 => f_dcd_rf1_bypsel_c_load0 , + f_dcd_rf1_bypsel_c_load1 => f_dcd_rf1_bypsel_c_load1 , + + f_rnd_ex6_res_sign => rnd_ex6_res_sign , + f_rnd_ex6_res_expo(1 to 13) => rnd_ex6_res_expo(1 to 13) , + f_rnd_ex6_res_frac(0 to 52) => rnd_ex6_res_frac(0 to 52) , + f_fpr_ex6_load_sign => f_fpr_ex6_load_sign , + f_fpr_ex6_load_expo(3 to 13) => f_fpr_ex6_load_expo(3 to 13) , + f_fpr_ex6_load_frac(0 to 52) => f_fpr_ex6_load_frac(0 to 52) , + f_fpr_rf1_a_sign => f_fpr_rf1_a_sign , + f_fpr_rf1_a_expo(1 to 13) => f_fpr_rf1_a_expo(1 to 13) , + f_fpr_rf1_a_frac(0 to 52) => f_fpr_rf1_a_frac(0 to 52) , + f_fpr_rf1_c_sign => f_fpr_rf1_c_sign , + f_fpr_rf1_c_expo(1 to 13) => f_fpr_rf1_c_expo(1 to 13) , + f_fpr_rf1_c_frac(0 to 52) => f_fpr_rf1_c_frac(0 to 52) , + f_fpr_rf1_b_sign => f_fpr_rf1_b_sign , + f_fpr_rf1_b_expo(1 to 13) => f_fpr_rf1_b_expo(1 to 13) , + f_fpr_rf1_b_frac(0 to 52) => f_fpr_rf1_b_frac(0 to 52) , + f_dcd_rf1_aop_valid => f_dcd_rf1_aop_valid , + f_dcd_rf1_cop_valid => f_dcd_rf1_cop_valid , + f_dcd_rf1_bop_valid => f_dcd_rf1_bop_valid , + f_dcd_rf1_sp => f_dcd_rf1_sp , + f_dcd_rf1_to_integer_b => f_dcd_rf1_to_integer_b , + f_dcd_rf1_emin_dp => f_dcd_rf1_emin_dp , + f_dcd_rf1_emin_sp => f_dcd_rf1_emin_sp , + + f_byp_fmt_ex1_a_expo(1 to 13) => f_byp_fmt_ex1_a_expo(1 to 13) , + f_byp_eie_ex1_a_expo(1 to 13) => f_byp_eie_ex1_a_expo(1 to 13) , + f_byp_alg_ex1_a_expo(1 to 13) => f_byp_alg_ex1_a_expo(1 to 13) , + f_byp_fmt_ex1_c_expo(1 to 13) => f_byp_fmt_ex1_c_expo(1 to 13) , + f_byp_eie_ex1_c_expo(1 to 13) => f_byp_eie_ex1_c_expo(1 to 13) , + f_byp_alg_ex1_c_expo(1 to 13) => f_byp_alg_ex1_c_expo(1 to 13) , + f_byp_fmt_ex1_b_expo(1 to 13) => f_byp_fmt_ex1_b_expo(1 to 13) , + f_byp_eie_ex1_b_expo(1 to 13) => f_byp_eie_ex1_b_expo(1 to 13) , + f_byp_alg_ex1_b_expo(1 to 13) => f_byp_alg_ex1_b_expo(1 to 13) , + f_byp_fmt_ex1_a_sign => f_byp_fmt_ex1_a_sign , + f_byp_fmt_ex1_c_sign => f_byp_fmt_ex1_c_sign , + f_byp_fmt_ex1_b_sign => f_byp_fmt_ex1_b_sign , + f_byp_pic_ex1_a_sign => f_byp_pic_ex1_a_sign , + f_byp_pic_ex1_c_sign => f_byp_pic_ex1_c_sign , + f_byp_pic_ex1_b_sign => f_byp_pic_ex1_b_sign , + f_byp_alg_ex1_b_sign => f_byp_alg_ex1_b_sign , + f_byp_mul_ex1_a_frac_17 => f_byp_mul_ex1_a_frac_17 , + f_byp_mul_ex1_a_frac_35 => f_byp_mul_ex1_a_frac_35 , + f_byp_mul_ex1_a_frac(0 to 52) => f_byp_mul_ex1_a_frac(0 to 52) , + f_byp_fmt_ex1_a_frac(0 to 52) => f_byp_fmt_ex1_a_frac(0 to 52) , + f_byp_mul_ex1_c_frac(0 to 52) => f_byp_mul_ex1_c_frac(0 to 52) , + f_byp_mul_ex1_c_frac(53) => f_byp_mul_ex1_c_frac(53) , + f_byp_fmt_ex1_c_frac(0 to 52) => f_byp_fmt_ex1_c_frac(0 to 52) , + f_byp_alg_ex1_b_frac(0 to 52) => f_byp_alg_ex1_b_frac(0 to 52) , + f_byp_fmt_ex1_b_frac(0 to 52) => f_byp_fmt_ex1_b_frac(0 to 52) ); + + + +ffmt : entity WORK.fuq_fmt(fuq_fmt) generic map( expand_type => expand_type) port map( + vdd => vdd , + gnd => gnd , + nclk => nclk , + clkoff_b => clkoff_b , + act_dis => act_dis , + flush => flush , + delay_lclkr => delay_lclkr(1 to 2) , + mpw1_b => mpw1_b(1 to 2) , + mpw2_b => mpw2_b(0 to 0) , + thold_1 => perv_fmt_thold_1 , + sg_1 => perv_fmt_sg_1 , + fpu_enable => perv_fmt_fpu_enable , + + f_fmt_si => scan_in(1) , + f_fmt_so => scan_out(1) , + rf1_act => f_dcd_rf1_act , + ex1_act => f_pic_fmt_ex1_act , + + f_fpr_ex1_a_par(0 to 7) => f_fpr_ex1_a_par(0 to 7) , + f_fpr_ex1_c_par(0 to 7) => f_fpr_ex1_c_par(0 to 7) , + f_fpr_ex1_b_par(0 to 7) => f_fpr_ex1_b_par(0 to 7) , + + f_mad_ex2_a_parity_check => f_mad_ex2_a_parity_check , + f_mad_ex2_c_parity_check => f_mad_ex2_c_parity_check , + f_mad_ex2_b_parity_check => f_mad_ex2_b_parity_check , + f_fmt_ex2_ae_ge_54 => f_fmt_ex2_ae_ge_54 , + f_fmt_ex2_be_ge_54 => f_fmt_ex2_be_ge_54 , + f_fmt_ex2_be_ge_2 => f_fmt_ex2_be_ge_2 , + f_fmt_ex2_be_ge_2044 => f_fmt_ex2_be_ge_2044 , + f_fmt_ex2_tdiv_rng_chk => f_fmt_ex2_tdiv_rng_chk , + f_fmt_ex2_be_den => f_fmt_ex2_be_den , + f_byp_fmt_ex1_a_sign => f_byp_fmt_ex1_a_sign , + f_byp_fmt_ex1_c_sign => f_byp_fmt_ex1_c_sign , + f_byp_fmt_ex1_b_sign => f_byp_fmt_ex1_b_sign , + f_byp_fmt_ex1_a_expo(1 to 13) => f_byp_fmt_ex1_a_expo(1 to 13) , + f_byp_fmt_ex1_c_expo(1 to 13) => f_byp_fmt_ex1_c_expo(1 to 13) , + f_byp_fmt_ex1_b_expo(1 to 13) => f_byp_fmt_ex1_b_expo(1 to 13) , + + f_byp_fmt_ex1_a_frac(0 to 52) => f_byp_fmt_ex1_a_frac(0 to 52) , + f_byp_fmt_ex1_c_frac(0 to 52) => f_byp_fmt_ex1_c_frac(0 to 52) , + f_byp_fmt_ex1_b_frac(0 to 52) => f_byp_fmt_ex1_b_frac(0 to 52) , + + f_dcd_rf1_sp => f_dcd_rf1_sp , + f_dcd_rf1_from_integer_b => f_dcd_rf1_from_integer_b , + f_dcd_rf1_sgncpy_b => f_dcd_rf1_sgncpy_b , + f_dcd_rf1_uc_mid => f_dcd_rf1_uc_mid , + f_dcd_rf1_uc_end => f_dcd_rf1_uc_end , + f_dcd_rf1_uc_special => f_dcd_rf1_uc_special , + f_dcd_rf1_aop_valid => f_dcd_rf1_aop_valid , + f_dcd_rf1_cop_valid => f_dcd_rf1_cop_valid , + f_dcd_rf1_bop_valid => f_dcd_rf1_bop_valid , + f_dcd_rf1_fsel_b => f_dcd_rf1_fsel_b , + f_dcd_rf1_force_pass_b => f_dcd_rf1_force_pass_b , + f_dcd_ex1_perr_force_c => f_dcd_ex1_perr_force_c , + f_dcd_ex1_perr_fsel_ovrd => f_dcd_ex1_perr_fsel_ovrd , + f_pic_ex1_ftdiv => f_pic_ex1_ftdiv , + f_pic_ex1_flush_en_sp => f_pic_ex1_flush_en_sp , + f_pic_ex1_flush_en_dp => f_pic_ex1_flush_en_dp , + f_pic_ex1_nj_deni => f_pic_ex1_nj_deni , + f_fmt_ex2_lu_den_recip => f_fmt_ex2_lu_den_recip , + f_fmt_ex2_lu_den_rsqrto => f_fmt_ex2_lu_den_rsqrto , + f_fmt_ex1_bop_byt(45 to 52) => f_fmt_ex1_bop_byt(45 to 52) , + f_fmt_ex1_b_frac(1 to 19) => f_fmt_ex1_b_frac(1 to 19) , + f_fmt_ex1_bexpu_le126 => f_fmt_ex1_bexpu_le126 , + f_fmt_ex1_gt126 => f_fmt_ex1_gt126 , + f_fmt_ex1_ge128 => f_fmt_ex1_ge128 , + f_fmt_ex1_inf_and_beyond_sp => f_fmt_ex1_inf_and_beyond_sp , + + f_fmt_ex1_b_sign_gst => f_fmt_ex1_b_sign_gst , + f_fmt_ex1_b_expo_gst_b(1 to 13) => f_fmt_ex1_b_expo_gst_b(1 to 13) , + f_mad_ex2_uc_a_expo_den => f_mad_ex2_uc_a_expo_den , + f_mad_ex2_uc_a_expo_den_sp => f_mad_ex2_uc_a_expo_den_sp , + f_fmt_ex1_a_zero => f_fmt_ex1_a_zero , + f_fmt_ex1_a_expo_max => f_fmt_ex1_a_expo_max , + f_fmt_ex1_a_frac_zero => f_fmt_ex1_a_frac_zero , + f_fmt_ex1_a_frac_msb => f_fmt_ex1_a_frac_msb , + f_fmt_ex1_c_zero => f_fmt_ex1_c_zero , + f_fmt_ex1_c_expo_max => f_fmt_ex1_c_expo_max , + f_fmt_ex1_c_frac_zero => f_fmt_ex1_c_frac_zero , + f_fmt_ex1_c_frac_msb => f_fmt_ex1_c_frac_msb , + f_fmt_ex1_b_zero => f_fmt_ex1_b_zero , + f_fmt_ex1_b_expo_max => f_fmt_ex1_b_expo_max , + f_fmt_ex1_b_frac_zero => f_fmt_ex1_b_frac_zero , + f_fmt_ex1_b_frac_msb => f_fmt_ex1_b_frac_msb , + f_fmt_ex1_b_frac_z32 => f_fmt_ex1_b_frac_z32 , + f_fmt_ex1_prod_zero => f_fmt_ex1_prod_zero , + f_fmt_ex1_pass_sel => f_fmt_ex1_pass_sel , + f_fmt_ex1_sp_invalid => f_fmt_ex1_sp_invalid , + f_ex2_b_den_flush => f_ex2_b_den_flush , + f_fmt_ex2_fsel_bsel => f_fmt_ex2_fsel_bsel , + f_fmt_ex2_pass_sign => f_fmt_ex2_pass_sign , + f_fmt_ex2_pass_msb => f_fmt_ex2_pass_msb , + f_fmt_ex1_b_imp => f_fmt_ex1_b_imp , + f_fmt_ex2_pass_frac(0 to 52) => f_fmt_ex2_pass_frac(0 to 52) ); + + + + + +feie : entity WORK.fuq_eie(fuq_eie) generic map( expand_type => expand_type) port map( + vdd => vdd , + gnd => gnd , + nclk => nclk , + clkoff_b => clkoff_b , + act_dis => act_dis , + flush => flush , + delay_lclkr => delay_lclkr(2 to 3) , + mpw1_b => mpw1_b(2 to 3) , + mpw2_b => mpw2_b(0 to 0) , + thold_1 => perv_eie_thold_1 , + sg_1 => perv_eie_sg_1 , + fpu_enable => perv_eie_fpu_enable , + + f_eie_si => scan_in(2) , + f_eie_so => scan_out(2) , + ex1_act => f_pic_eie_ex1_act , + f_byp_eie_ex1_a_expo(1 to 13) => f_byp_eie_ex1_a_expo(1 to 13) , + f_byp_eie_ex1_c_expo(1 to 13) => f_byp_eie_ex1_c_expo(1 to 13) , + f_byp_eie_ex1_b_expo(1 to 13) => f_byp_eie_ex1_b_expo(1 to 13) , + f_pic_ex1_from_integer => f_pic_ex1_from_integer , + f_pic_ex1_fsel => f_pic_ex1_fsel , + f_pic_ex2_frsp_ue1 => f_pic_ex2_frsp_ue1 , + f_alg_ex2_sel_byp => f_alg_ex2_sel_byp , + f_fmt_ex2_fsel_bsel => f_fmt_ex2_fsel_bsel , + f_pic_ex2_force_sel_bexp => f_pic_ex2_force_sel_bexp , + f_pic_ex2_sp_b => f_pic_ex2_sp_b , + f_pic_ex2_math_bzer_b => f_pic_ex2_math_bzer_b , + f_eie_ex2_lt_bias => f_eie_ex2_lt_bias , + f_eie_ex2_eq_bias_m1 => f_eie_ex2_eq_bias_m1 , + f_eie_ex2_wd_ov => f_eie_ex2_wd_ov , + f_eie_ex2_dw_ov => f_eie_ex2_dw_ov , + f_eie_ex2_wd_ov_if => f_eie_ex2_wd_ov_if , + f_eie_ex2_dw_ov_if => f_eie_ex2_dw_ov_if , + f_eie_ex2_lzo_expo(1 to 13) => f_eie_ex2_lzo_expo(1 to 13) , + f_eie_ex2_b_expo(1 to 13) => f_eie_ex2_b_expo(1 to 13) , + f_eie_ex2_use_bexp => f_eie_ex2_use_bexp , + f_eie_ex2_tbl_expo(1 to 13) => f_eie_ex2_tbl_expo(1 to 13) , + f_eie_ex3_iexp(1 to 13) => f_eie_ex3_iexp(1 to 13) ); + + + +feov : entity WORK.fuq_eov(fuq_eov) generic map( expand_type => expand_type) port map( + vdd => vdd , + gnd => gnd , + nclk => nclk , + clkoff_b => clkoff_b , + act_dis => act_dis , + flush => flush , + delay_lclkr => delay_lclkr(4 to 5) , + mpw1_b => mpw1_b(4 to 5) , + mpw2_b => mpw2_b(0 to 1) , + thold_1 => perv_eov_thold_1 , + sg_1 => perv_eov_sg_1 , + fpu_enable => perv_eov_fpu_enable , + + f_eov_si => scan_in(3) , + f_eov_so => scan_out(3) , + ex2_act_b => f_pic_eov_ex2_act_b , + f_tbl_ex4_unf_expo => f_tbl_ex4_unf_expo , + f_tbe_ex3_may_ov => f_tbe_ex3_may_ov , + f_tbe_ex3_expo(1 to 13) => f_tbe_ex3_res_expo(1 to 13) , + f_pic_ex3_sel_est => f_pic_ex3_sel_est , + f_eie_ex3_iexp(1 to 13) => f_eie_ex3_iexp(1 to 13) , + f_pic_ex3_sp_b => f_pic_ex3_sp_b , + f_lza_ex4_sh_rgt_en_eov => f_lza_ex4_sh_rgt_en_eov , + f_pic_ex4_oe => f_pic_ex4_oe , + f_pic_ex4_ue => f_pic_ex4_ue , + f_pic_ex4_ov_en => f_pic_ex4_ov_en , + f_pic_ex4_uf_en => f_pic_ex4_uf_en , + f_pic_ex4_spec_sel_k_e => f_pic_ex4_spec_sel_k_e , + f_pic_ex4_spec_sel_k_f => f_pic_ex4_spec_sel_k_f , + f_pic_ex4_sel_ov_spec => tidn , + + f_pic_ex4_to_int_ov_all => f_pic_ex4_to_int_ov_all , + + f_lza_ex4_no_lza_edge => f_lza_ex4_no_lza_edge , + f_lza_ex4_lza_amt_eov(0 to 7) => f_lza_ex4_lza_amt_eov(0 to 7) , + f_nrm_ex4_extra_shift => f_nrm_ex4_extra_shift , + f_eov_ex4_may_ovf => f_eov_ex4_may_ovf , + f_eov_ex5_sel_k_f => f_eov_ex5_sel_k_f , + f_eov_ex5_sel_k_e => f_eov_ex5_sel_k_e , + f_eov_ex5_sel_kif_f => f_eov_ex5_sel_kif_f , + f_eov_ex5_sel_kif_e => f_eov_ex5_sel_kif_e , + f_eov_ex5_unf_expo => f_eov_ex5_unf_expo , + f_eov_ex5_ovf_expo => f_eov_ex5_ovf_expo , + f_eov_ex5_ovf_if_expo => f_eov_ex5_ovf_if_expo , + f_eov_ex5_expo_p0(1 to 13) => f_eov_ex5_expo_p0(1 to 13) , + f_eov_ex5_expo_p1(1 to 13) => f_eov_ex5_expo_p1(1 to 13) , + f_eov_ex5_expo_p0_ue1oe1(3 to 7) => f_eov_ex5_expo_p0_ue1oe1(3 to 7) , + f_eov_ex5_expo_p1_ue1oe1(3 to 7) => f_eov_ex5_expo_p1_ue1oe1(3 to 7) ); + + +fmul : entity WORK.fuq_mul(fuq_mul) generic map( expand_type => expand_type) port map( + vdd => vdd , + gnd => gnd , + nclk => nclk , + clkoff_b => clkoff_b , + act_dis => act_dis , + flush => flush , + delay_lclkr => delay_lclkr(2) , + mpw1_b => mpw1_b(2) , + mpw2_b => mpw2_b(0) , + thold_1 => perv_mul_thold_1 , + sg_1 => perv_mul_sg_1 , + fpu_enable => perv_mul_fpu_enable , + + f_mul_si => scan_in(4) , + f_mul_so => scan_out(4) , + ex1_act => f_pic_mul_ex1_act , + f_fmt_ex1_a_frac(0 to 52) => f_byp_mul_ex1_a_frac(0 to 52) , + f_fmt_ex1_a_frac_17 => f_byp_mul_ex1_a_frac_17 , + f_fmt_ex1_a_frac_35 => f_byp_mul_ex1_a_frac_35 , + f_fmt_ex1_c_frac(0 to 53) => f_byp_mul_ex1_c_frac(0 to 53) , + f_mul_ex2_sum(1 to 108) => f_mul_ex2_sum(1 to 108) , + f_mul_ex2_car(1 to 108) => f_mul_ex2_car(1 to 108) ); + + +falg : entity WORK.fuq_alg(fuq_alg) generic map( expand_type => expand_type) port map( + vdd => vdd , + gnd => gnd , + nclk => nclk , + clkoff_b => clkoff_b , + act_dis => act_dis , + flush => flush , + delay_lclkr => delay_lclkr(1 to 3) , + mpw1_b => mpw1_b(1 to 3) , + mpw2_b => mpw2_b(0 to 0) , + thold_1 => perv_alg_thold_1 , + sg_1 => perv_alg_sg_1 , + fpu_enable => perv_alg_fpu_enable , + + f_alg_si => scan_in(5) , + f_alg_so => scan_out(5) , + rf1_act => f_dcd_rf1_act , + ex1_act => f_pic_alg_ex1_act , + f_dcd_rf1_sp => f_dcd_rf1_sp , + + f_pic_ex1_frsp_ue1 => f_pic_ex1_frsp_ue1 , + + f_byp_alg_ex1_b_frac(0 to 52) => f_byp_alg_ex1_b_frac(0 to 52) , + f_byp_alg_ex1_b_sign => f_byp_alg_ex1_b_sign , + f_byp_alg_ex1_b_expo(1 to 13) => f_byp_alg_ex1_b_expo(1 to 13) , + f_byp_alg_ex1_a_expo(1 to 13) => f_byp_alg_ex1_a_expo(1 to 13) , + f_byp_alg_ex1_c_expo(1 to 13) => f_byp_alg_ex1_c_expo(1 to 13) , + + f_fmt_ex1_prod_zero => f_fmt_ex1_prod_zero , + f_fmt_ex1_b_zero => f_fmt_ex1_b_zero , + f_fmt_ex1_pass_sel => f_fmt_ex1_pass_sel , + f_fmt_ex2_pass_frac(0 to 52) => f_fmt_ex2_pass_frac(0 to 52) , + f_dcd_rf1_word_b => f_dcd_rf1_word_b , + f_dcd_rf1_uns_b => f_dcd_rf1_uns_b , + f_dcd_rf1_from_integer_b => f_dcd_rf1_from_integer_b , + f_dcd_rf1_to_integer_b => f_dcd_rf1_to_integer_b , + f_pic_ex1_rnd_to_int => f_pic_ex1_rnd_to_int , + f_pic_ex1_effsub_raw => f_pic_ex1_effsub_raw , + f_pic_ex1_sh_unf_ig_b => f_pic_ex1_sh_unf_ig_b , + f_pic_ex1_sh_unf_do => f_pic_ex1_sh_unf_do , + f_pic_ex1_sh_ovf_ig_b => f_pic_ex1_sh_ovf_ig_b , + f_pic_ex1_sh_ovf_do => f_pic_ex1_sh_ovf_do , + f_pic_ex2_rnd_nr => f_pic_ex2_rnd_nr , + f_pic_ex2_rnd_inf_ok => f_pic_ex2_rnd_inf_ok , + f_alg_ex1_sign_frmw => f_alg_ex1_sign_frmw , + f_alg_ex2_res(0 to 162) => f_alg_ex2_res(0 to 162) , + f_alg_ex2_sel_byp => f_alg_ex2_sel_byp , + f_alg_ex2_effsub_eac_b => f_alg_ex2_effsub_eac_b , + f_alg_ex2_prod_z => f_alg_ex2_prod_z , + f_alg_ex2_sh_unf => f_alg_ex2_sh_unf , + f_alg_ex2_sh_ovf => f_alg_ex2_sh_ovf , + f_alg_ex2_byp_nonflip => f_alg_ex2_byp_nonflip , + f_alg_ex3_frc_sel_p1 => f_alg_ex3_frc_sel_p1 , + f_alg_ex3_sticky => f_alg_ex3_sticky , + f_alg_ex3_int_fr => f_alg_ex3_int_fr , + f_alg_ex3_int_fi => f_alg_ex3_int_fi ); + + + +fsa3 : entity WORK.fuq_sa3(fuq_sa3) generic map( expand_type => expand_type) port map( + vdd => vdd , + gnd => gnd , + nclk => nclk , + clkoff_b => clkoff_b , + act_dis => act_dis , + flush => flush , + delay_lclkr => delay_lclkr(2 to 3) , + mpw1_b => mpw1_b(2 to 3) , + mpw2_b => mpw2_b(0 to 0) , + thold_1 => perv_sa3_thold_1 , + sg_1 => perv_sa3_sg_1 , + fpu_enable => perv_sa3_fpu_enable , + + f_sa3_si => scan_in(6) , + f_sa3_so => scan_out(6) , + ex1_act_b => f_pic_add_ex1_act_b , + f_mul_ex2_sum(54 to 161) => f_mul_ex2_sum(1 to 108) , + f_mul_ex2_car(54 to 161) => f_mul_ex2_car(1 to 108) , + f_alg_ex2_res(0 to 162) => f_alg_ex2_res(0 to 162) , + f_sa3_ex3_s_lza(0 to 162) => f_sa3_ex3_s_lza(0 to 162) , + f_sa3_ex3_c_lza(53 to 161) => f_sa3_ex3_c_lza(53 to 161) , + f_sa3_ex3_s_add(0 to 162) => f_sa3_ex3_s_add(0 to 162) , + f_sa3_ex3_c_add(53 to 161) => f_sa3_ex3_c_add(53 to 161) ); + + + +fadd : entity WORK.fuq_add(fuq_add) generic map( expand_type => expand_type) port map( + vdd => vdd , + gnd => gnd , + nclk => nclk , + clkoff_b => clkoff_b , + act_dis => act_dis , + flush => flush , + delay_lclkr => delay_lclkr(3 to 4) , + mpw1_b => mpw1_b(3 to 4) , + mpw2_b => mpw2_b(0 to 0) , + thold_1 => perv_add_thold_1 , + sg_1 => perv_add_sg_1 , + fpu_enable => perv_add_fpu_enable , + + f_add_si => scan_in(7) , + f_add_so => scan_out(7) , + ex1_act_b => f_pic_add_ex1_act_b , + f_sa3_ex3_s(0 to 162) => f_sa3_ex3_s_add(0 to 162) , + f_sa3_ex3_c(53 to 161) => f_sa3_ex3_c_add(53 to 161) , + f_alg_ex3_frc_sel_p1 => f_alg_ex3_frc_sel_p1 , + f_alg_ex3_sticky => f_alg_ex3_sticky , + f_alg_ex2_effsub_eac_b => f_alg_ex2_effsub_eac_b , + f_alg_ex2_prod_z => f_alg_ex2_prod_z , + f_pic_ex3_is_gt => f_pic_ex3_is_gt , + f_pic_ex3_is_lt => f_pic_ex3_is_lt , + f_pic_ex3_is_eq => f_pic_ex3_is_eq , + f_pic_ex3_is_nan => f_pic_ex3_is_nan , + f_pic_ex3_cmp_sgnpos => f_pic_ex3_cmp_sgnpos , + f_pic_ex3_cmp_sgnneg => f_pic_ex3_cmp_sgnneg , + f_add_ex4_res(0 to 162) => f_add_ex4_res(0 to 162) , + f_add_ex4_flag_nan => f_add_ex4_flag_nan , + f_add_ex4_flag_gt => f_add_ex4_flag_gt , + f_add_ex4_flag_lt => f_add_ex4_flag_lt , + f_add_ex4_flag_eq => f_add_ex4_flag_eq , + f_add_ex4_fpcc_iu(0 to 3) => f_add_ex4_fpcc_iu(0 to 3) , + f_add_ex4_sign_carry => f_add_ex4_sign_carry , + f_add_ex4_to_int_ovf_wd(0 to 1) => f_add_ex4_to_int_ovf_wd(0 to 1) , + f_add_ex4_to_int_ovf_dw(0 to 1) => f_add_ex4_to_int_ovf_dw(0 to 1) , + f_add_ex4_sticky => f_add_ex4_sticky ); + + + +flze : entity WORK.fuq_lze(fuq_lze) generic map( expand_type => expand_type) port map( + vdd => vdd , + gnd => gnd , + nclk => nclk , + clkoff_b => clkoff_b , + act_dis => act_dis , + flush => flush , + delay_lclkr => delay_lclkr(2 to 3) , + mpw1_b => mpw1_b(2 to 3) , + mpw2_b => mpw2_b(0 to 0) , + thold_1 => perv_lza_thold_1 , + sg_1 => perv_lza_sg_1 , + fpu_enable => perv_lza_fpu_enable , + + f_lze_si => scan_in(8) , + f_lze_so => scan_out(8) , + ex1_act_b => f_pic_lza_ex1_act_b , + f_eie_ex2_lzo_expo(1 to 13) => f_eie_ex2_lzo_expo(1 to 13) , + f_eie_ex2_b_expo(1 to 13) => f_eie_ex2_b_expo(1 to 13) , + f_pic_ex2_est_recip => f_pic_ex2_est_recip , + f_pic_ex2_est_rsqrt => f_pic_ex2_est_rsqrt , + f_alg_ex2_byp_nonflip => f_alg_ex2_byp_nonflip , + f_eie_ex2_use_bexp => f_eie_ex2_use_bexp , + f_pic_ex2_b_valid => f_pic_ex2_b_valid , + f_pic_ex2_lzo_dis_prod => f_pic_ex2_lzo_dis_prod , + f_pic_ex2_sp_lzo => f_pic_ex2_sp_lzo , + f_pic_ex2_frsp_ue1 => f_pic_ex2_frsp_ue1 , + f_fmt_ex2_pass_msb_dp => f_fmt_ex2_pass_frac(0) , + f_alg_ex2_sel_byp => f_alg_ex2_sel_byp , + f_pic_ex2_to_integer => f_pic_ex2_to_integer , + f_pic_ex2_prenorm => f_pic_ex2_prenorm , + + + f_lze_ex2_lzo_din(0 to 162) => f_lze_ex2_lzo_din(0 to 162) , + f_lze_ex3_sh_rgt_amt(0 to 7) => f_lze_ex3_sh_rgt_amt(0 to 7) , + f_lze_ex3_sh_rgt_en => f_lze_ex3_sh_rgt_en ); + + + +flza : entity WORK.fuq_lza(fuq_lza) generic map( expand_type => expand_type) port map( + vdd => vdd , + gnd => gnd , + nclk => nclk , + clkoff_b => clkoff_b , + act_dis => act_dis , + flush => flush , + delay_lclkr => delay_lclkr(3 to 4) , + mpw1_b => mpw1_b(3 to 4) , + mpw2_b => mpw2_b(0 to 0) , + thold_1 => perv_lza_thold_1 , + sg_1 => perv_lza_sg_1 , + fpu_enable => perv_lza_fpu_enable , + + f_lza_si => scan_in(9) , + f_lza_so => scan_out(9) , + ex1_act_b => f_pic_lza_ex1_act_b , + f_sa3_ex3_s(0 to 162) => f_sa3_ex3_s_lza(0 to 162) , + f_sa3_ex3_c(53 to 161) => f_sa3_ex3_c_lza(53 to 161) , + f_alg_ex2_effsub_eac_b => f_alg_ex2_effsub_eac_b , + + f_lze_ex2_lzo_din(0 to 162) => f_lze_ex2_lzo_din(0 to 162) , + f_lze_ex3_sh_rgt_amt(0 to 7) => f_lze_ex3_sh_rgt_amt(0 to 7) , + f_lze_ex3_sh_rgt_en => f_lze_ex3_sh_rgt_en , + + f_lza_ex4_no_lza_edge => f_lza_ex4_no_lza_edge , + f_lza_ex4_lza_amt(0 to 7) => f_lza_ex4_lza_amt(0 to 7) , + f_lza_ex4_sh_rgt_en => f_lza_ex4_sh_rgt_en , + f_lza_ex4_sh_rgt_en_eov => f_lza_ex4_sh_rgt_en_eov , + f_lza_ex4_lza_dcd64_cp1(0 to 2) => f_lza_ex4_lza_dcd64_cp1(0 to 2) , + f_lza_ex4_lza_dcd64_cp2(0 to 1) => f_lza_ex4_lza_dcd64_cp2(0 to 1) , + f_lza_ex4_lza_dcd64_cp3(0) => f_lza_ex4_lza_dcd64_cp3(0) , + + f_lza_ex4_lza_amt_eov(0 to 7) => f_lza_ex4_lza_amt_eov(0 to 7) ); + + +fnrm : entity WORK.fuq_nrm(fuq_nrm) generic map( expand_type => expand_type) port map( + vdd => vdd , + gnd => gnd , + nclk => nclk , + clkoff_b => clkoff_b , + act_dis => act_dis , + flush => flush , + delay_lclkr => delay_lclkr(4 to 5) , + mpw1_b => mpw1_b(4 to 5) , + mpw2_b => mpw2_b(0 to 1) , + thold_1 => perv_nrm_thold_1 , + sg_1 => perv_nrm_sg_1 , + fpu_enable => perv_nrm_fpu_enable , + + f_nrm_si => scan_in(10) , + f_nrm_so => scan_out(10) , + ex3_act_b => f_pic_nrm_ex3_act_b , + + f_lza_ex4_sh_rgt_en => f_lza_ex4_sh_rgt_en , + f_lza_ex4_lza_amt_cp1 => f_lza_ex4_lza_amt(0 to 7) , + f_lza_ex4_lza_dcd64_cp1(0 to 2) => f_lza_ex4_lza_dcd64_cp1(0 to 2) , + f_lza_ex4_lza_dcd64_cp2(0 to 1) => f_lza_ex4_lza_dcd64_cp2(0 to 1) , + f_lza_ex4_lza_dcd64_cp3(0) => f_lza_ex4_lza_dcd64_cp3(0) , + + f_add_ex4_res(0 to 162) => f_add_ex4_res(0 to 162) , + f_add_ex4_sticky => f_add_ex4_sticky , + f_pic_ex4_byp_prod_nz => f_pic_ex4_byp_prod_nz , + f_nrm_ex5_res(0 to 52) => f_nrm_ex5_res(0 to 52) , + f_nrm_ex5_int_lsbs(1 to 12) => f_nrm_ex5_int_lsbs(1 to 12) , + f_nrm_ex5_int_sign => f_nrm_ex5_int_sign , + f_nrm_ex5_nrm_sticky_dp => f_nrm_ex5_nrm_sticky_dp , + f_nrm_ex5_nrm_guard_dp => f_nrm_ex5_nrm_guard_dp , + f_nrm_ex5_nrm_lsb_dp => f_nrm_ex5_nrm_lsb_dp , + f_nrm_ex5_nrm_sticky_sp => f_nrm_ex5_nrm_sticky_sp , + f_nrm_ex5_nrm_guard_sp => f_nrm_ex5_nrm_guard_sp , + f_nrm_ex5_nrm_lsb_sp => f_nrm_ex5_nrm_lsb_sp , + f_nrm_ex5_exact_zero => f_nrm_ex5_exact_zero , + f_nrm_ex4_extra_shift => f_nrm_ex4_extra_shift , + f_nrm_ex5_fpscr_wr_dat_dfp(0 to 3) => f_nrm_ex5_fpscr_wr_dat_dfp(0 to 3) , + f_nrm_ex5_fpscr_wr_dat(0 to 31) => f_nrm_ex5_fpscr_wr_dat(0 to 31) ); + + + +frnd : entity WORK.fuq_rnd(fuq_rnd) generic map( expand_type => expand_type) port map( + vdd => vdd , + gnd => gnd , + nclk => nclk , + clkoff_b => clkoff_b , + act_dis => act_dis , + flush => flush , + delay_lclkr => delay_lclkr(5 to 6) , + mpw1_b => mpw1_b(5 to 6) , + mpw2_b => mpw2_b(1 to 1) , + thold_1 => perv_rnd_thold_1 , + sg_1 => perv_rnd_sg_1 , + fpu_enable => perv_rnd_fpu_enable , + + f_rnd_si => scan_in(11) , + f_rnd_so => scan_out(11) , + ex3_act_b => f_pic_rnd_ex3_act_b , + f_pic_ex4_sel_est_b => f_pic_ex4_sel_est_b , + f_tbl_ex5_est_frac(0 to 26) => f_tbl_ex5_est_frac(0 to 26) , + f_nrm_ex5_res(0 to 52) => f_nrm_ex5_res(0 to 52) , + f_nrm_ex5_int_lsbs(1 to 12) => f_nrm_ex5_int_lsbs(1 to 12) , + f_nrm_ex5_int_sign => f_nrm_ex5_int_sign , + f_nrm_ex5_nrm_sticky_dp => f_nrm_ex5_nrm_sticky_dp , + f_nrm_ex5_nrm_guard_dp => f_nrm_ex5_nrm_guard_dp , + f_nrm_ex5_nrm_lsb_dp => f_nrm_ex5_nrm_lsb_dp , + f_nrm_ex5_nrm_sticky_sp => f_nrm_ex5_nrm_sticky_sp , + f_nrm_ex5_nrm_guard_sp => f_nrm_ex5_nrm_guard_sp , + f_nrm_ex5_nrm_lsb_sp => f_nrm_ex5_nrm_lsb_sp , + f_nrm_ex5_exact_zero => f_nrm_ex5_exact_zero , + f_pic_ex5_invert_sign => f_pic_ex5_invert_sign , + f_pic_ex5_en_exact_zero => f_pic_ex5_en_exact_zero , + f_pic_ex5_k_nan => f_pic_ex5_k_nan , + f_pic_ex5_k_inf => f_pic_ex5_k_inf , + f_pic_ex5_k_max => f_pic_ex5_k_max , + f_pic_ex5_k_zer => f_pic_ex5_k_zer , + f_pic_ex5_k_one => f_pic_ex5_k_one , + f_pic_ex5_k_int_maxpos => f_pic_ex5_k_int_maxpos , + f_pic_ex5_k_int_maxneg => f_pic_ex5_k_int_maxneg , + f_pic_ex5_k_int_zer => f_pic_ex5_k_int_zer , + f_tbl_ex5_recip_den => f_tbl_ex5_recip_den , + f_pic_ex4_rnd_ni_b => f_pic_ex4_rnd_ni_b , + f_pic_ex4_rnd_nr_b => f_pic_ex4_rnd_nr_b , + f_pic_ex4_rnd_inf_ok_b => f_pic_ex4_rnd_inf_ok_b , + f_pic_ex5_uc_inc_lsb => f_pic_ex5_uc_inc_lsb , + f_pic_ex5_uc_guard => f_pic_ex5_uc_guard , + f_pic_ex5_uc_sticky => f_pic_ex5_uc_sticky , + f_pic_ex5_uc_g_v => f_pic_ex5_uc_g_v , + f_pic_ex5_uc_s_v => f_pic_ex5_uc_s_v , + f_pic_ex4_sel_fpscr_b => f_pic_ex4_sel_fpscr_b , + f_pic_ex4_to_integer_b => f_pic_ex4_to_integer_b , + f_pic_ex4_word_b => f_pic_ex4_word_b , + f_pic_ex4_uns_b => f_pic_ex4_uns_b , + f_pic_ex4_sp_b => f_pic_ex4_sp_b , + f_pic_ex4_spec_inf_b => f_pic_ex4_spec_inf_b , + f_pic_ex4_quiet_b => f_pic_ex4_quiet_b , + f_pic_ex4_nj_deno => f_pic_ex4_nj_deno , + f_pic_ex4_unf_en_ue0_b => f_pic_ex4_unf_en_ue0_b , + f_pic_ex4_unf_en_ue1_b => f_pic_ex4_unf_en_ue1_b , + f_pic_ex4_ovf_en_oe0_b => f_pic_ex4_ovf_en_oe0_b , + f_pic_ex4_ovf_en_oe1_b => f_pic_ex4_ovf_en_oe1_b , + f_pic_ex5_round_sign => f_pic_ex5_round_sign , + f_scr_ex5_fpscr_rd_dat_dfp(0 to 3) => f_scr_ex5_fpscr_rd_dat_dfp(0 to 3) , + f_scr_ex5_fpscr_rd_dat(0 to 31) => f_scr_ex5_fpscr_rd_dat(0 to 31) , + f_eov_ex5_sel_k_f => f_eov_ex5_sel_k_f , + f_eov_ex5_sel_k_e => f_eov_ex5_sel_k_e , + f_eov_ex5_sel_kif_f => f_eov_ex5_sel_kif_f , + f_eov_ex5_sel_kif_e => f_eov_ex5_sel_kif_e , + f_eov_ex5_ovf_expo => f_eov_ex5_ovf_expo , + f_eov_ex5_ovf_if_expo => f_eov_ex5_ovf_if_expo , + f_eov_ex5_unf_expo => f_eov_ex5_unf_expo , + f_pic_ex5_frsp => f_pic_ex5_frsp , + f_eov_ex5_expo_p0(1 to 13) => f_eov_ex5_expo_p0(1 to 13) , + f_eov_ex5_expo_p1(1 to 13) => f_eov_ex5_expo_p1(1 to 13) , + f_eov_ex5_expo_p0_ue1oe1(3 to 7) => f_eov_ex5_expo_p0_ue1oe1(3 to 7) , + f_eov_ex5_expo_p1_ue1oe1(3 to 7) => f_eov_ex5_expo_p1_ue1oe1(3 to 7) , + f_gst_ex5_logexp_v => f_gst_ex5_logexp_v , + f_gst_ex5_logexp_sign => f_gst_ex5_logexp_sign , + f_gst_ex5_logexp_exp(1 to 11) => f_gst_ex5_logexp_exp(1 to 11) , + f_gst_ex5_logexp_fract(0 to 19) => f_gst_ex5_logexp_fract(0 to 19) , + f_mad_ex6_uc_sign => f_mad_ex6_uc_sign , + f_mad_ex6_uc_zero => f_mad_ex6_uc_zero , + f_rnd_ex6_res_sign => rnd_ex6_res_sign , + f_rnd_ex6_res_expo(1 to 13) => rnd_ex6_res_expo(1 to 13) , + f_rnd_ex6_res_frac(0 to 52) => rnd_ex6_res_frac(0 to 52) , + f_rnd_ex6_flag_up => f_rnd_ex6_flag_up , + f_rnd_ex6_flag_fi => f_rnd_ex6_flag_fi , + f_rnd_ex6_flag_ox => f_rnd_ex6_flag_ox , + f_rnd_ex6_flag_den => f_rnd_ex6_flag_den , + f_rnd_ex6_flag_sgn => f_rnd_ex6_flag_sgn , + f_rnd_ex6_flag_inf => f_rnd_ex6_flag_inf , + f_rnd_ex6_flag_zer => f_rnd_ex6_flag_zer , + f_rnd_ex6_flag_ux => f_rnd_ex6_flag_ux ); + + + + f_rnd_ex6_res_sign <= rnd_ex6_res_sign ; + f_rnd_ex6_res_expo(1 to 13) <= rnd_ex6_res_expo(1 to 13) ; + f_rnd_ex6_res_frac(0 to 52) <= rnd_ex6_res_frac(0 to 52) ; + + +fgst : entity WORK.fuq_gst(fuq_gst) generic map( expand_type => expand_type) port map( + vdd => vdd , + gnd => gnd , + nclk => nclk , + clkoff_b => clkoff_b , + act_dis => act_dis , + flush => flush , + delay_lclkr => delay_lclkr(2 to 5) , + mpw1_b => mpw1_b(2 to 5) , + mpw2_b => mpw2_b(0 to 1) , + thold_1 => perv_rnd_thold_1 , + sg_1 => perv_rnd_sg_1 , + fpu_enable => perv_rnd_fpu_enable , + + f_gst_si => scan_in(12) , + f_gst_so => scan_out(12) , + rf1_act => f_dcd_rf1_act , + f_fmt_ex1_b_sign_gst => f_fmt_ex1_b_sign_gst , + f_fmt_ex1_b_expo_gst_b(1 to 13) => f_fmt_ex1_b_expo_gst_b(1 to 13) , + f_fmt_ex1_b_frac_gst(1 to 19) => f_fmt_ex1_b_frac(1 to 19) , + f_pic_ex1_floges => f_pic_ex1_log2e , + f_pic_ex1_fexptes => f_pic_ex1_pow2e , + f_gst_ex5_logexp_v => f_gst_ex5_logexp_v , + f_gst_ex5_logexp_sign => f_gst_ex5_logexp_sign , + f_gst_ex5_logexp_exp(1 to 11) => f_gst_ex5_logexp_exp(1 to 11) , + f_gst_ex5_logexp_fract(0 to 19) => f_gst_ex5_logexp_fract(0 to 19) ); + + + + +fpic : entity WORK.fuq_pic(fuq_pic) generic map( expand_type => expand_type) port map( + vdd => vdd , + gnd => gnd , + nclk => nclk , + clkoff_b => clkoff_b , + act_dis => act_dis , + flush => flush , + delay_lclkr => delay_lclkr(1 to 5) , + mpw1_b => mpw1_b(1 to 5) , + mpw2_b => mpw2_b(0 to 1) , + thold_1 => perv_pic_thold_1 , + sg_1 => perv_pic_sg_1 , + fpu_enable => perv_pic_fpu_enable , + + f_pic_si => scan_in(13) , + f_pic_so => scan_out(13) , + f_dcd_rf1_act => f_dcd_rf1_act , + f_cr2_ex1_fpscr_shadow(0 to 7) => f_cr2_ex1_fpscr_shadow(0 to 7) , + f_dcd_rf1_pow2e_b => f_dcd_rf1_pow2e_b , + f_dcd_rf1_log2e_b => f_dcd_rf1_log2e_b , + f_byp_pic_ex1_a_sign => f_byp_pic_ex1_a_sign , + f_byp_pic_ex1_c_sign => f_byp_pic_ex1_c_sign , + f_byp_pic_ex1_b_sign => f_byp_pic_ex1_b_sign , + f_dcd_rf1_aop_valid => f_dcd_rf1_aop_valid , + f_dcd_rf1_cop_valid => f_dcd_rf1_cop_valid , + f_dcd_rf1_bop_valid => f_dcd_rf1_bop_valid , + f_dcd_rf1_uc_ft_neg => f_dcd_rf1_uc_ft_neg , + f_dcd_rf1_uc_ft_pos => f_dcd_rf1_uc_ft_pos , + f_dcd_rf1_fsel_b => f_dcd_rf1_fsel_b , + f_dcd_rf1_from_integer_b => f_dcd_rf1_from_integer_b , + f_dcd_rf1_to_integer_b => f_dcd_rf1_to_integer_b , + f_dcd_rf1_rnd_to_int_b => f_dcd_rf1_rnd_to_int_b , + f_dcd_rf1_math_b => f_dcd_rf1_math_b , + f_dcd_rf1_est_recip_b => f_dcd_rf1_est_recip_b , + f_dcd_rf1_ftdiv => f_dcd_rf1_ftdiv , + f_dcd_rf1_ftsqrt => f_dcd_rf1_ftsqrt , + f_fmt_ex2_ae_ge_54 => f_fmt_ex2_ae_ge_54 , + f_fmt_ex2_be_ge_54 => f_fmt_ex2_be_ge_54 , + f_fmt_ex2_be_ge_2 => f_fmt_ex2_be_ge_2 , + f_fmt_ex2_be_ge_2044 => f_fmt_ex2_be_ge_2044 , + f_fmt_ex2_tdiv_rng_chk => f_fmt_ex2_tdiv_rng_chk , + f_fmt_ex2_be_den => f_fmt_ex2_be_den , + + f_dcd_rf1_est_rsqrt_b => f_dcd_rf1_est_rsqrt_b , + f_dcd_rf1_move_b => f_dcd_rf1_move_b , + f_dcd_rf1_prenorm_b => f_dcd_rf1_prenorm_b , + f_dcd_rf1_frsp_b => f_dcd_rf1_frsp_b , + f_dcd_rf1_sp => f_dcd_rf1_sp , + f_dcd_rf1_sp_conv_b => f_dcd_rf1_sp_conv_b , + f_dcd_rf1_word_b => f_dcd_rf1_word_b , + f_dcd_rf1_uns_b => f_dcd_rf1_uns_b , + f_dcd_rf1_sub_op_b => f_dcd_rf1_sub_op_b , + f_dcd_rf1_op_rnd_v_b => f_dcd_rf1_op_rnd_v_b , + f_dcd_rf1_op_rnd_b(0 to 1) => f_dcd_rf1_op_rnd_b(0 to 1) , + f_dcd_rf1_inv_sign_b => f_dcd_rf1_inv_sign_b , + f_dcd_rf1_sign_ctl_b(0 to 1) => f_dcd_rf1_sign_ctl_b(0 to 1) , + f_dcd_rf1_sgncpy_b => f_dcd_rf1_sgncpy_b , + f_dcd_rf1_nj_deno => f_dcd_rf1_nj_deno , + f_dcd_rf1_mv_to_scr_b => f_dcd_rf1_mv_to_scr_b , + f_dcd_rf1_mv_from_scr_b => f_dcd_rf1_mv_from_scr_b , + f_dcd_rf1_compare_b => f_dcd_rf1_compare_b , + f_dcd_rf1_ordered_b => f_dcd_rf1_ordered_b , + f_alg_ex1_sign_frmw => f_alg_ex1_sign_frmw , + f_dcd_rf1_force_excp_dis => f_dcd_rf1_force_excp_dis , + f_pic_ex1_log2e => f_pic_ex1_log2e , + f_pic_ex1_pow2e => f_pic_ex1_pow2e , + f_fmt_ex1_bexpu_le126 => f_fmt_ex1_bexpu_le126 , + f_fmt_ex1_gt126 => f_fmt_ex1_gt126 , + f_fmt_ex1_ge128 => f_fmt_ex1_ge128 , + f_fmt_ex1_inf_and_beyond_sp => f_fmt_ex1_inf_and_beyond_sp , + f_fmt_ex1_sp_invalid => f_fmt_ex1_sp_invalid , + f_fmt_ex1_a_zero => f_fmt_ex1_a_zero , + f_fmt_ex1_a_expo_max => f_fmt_ex1_a_expo_max , + f_fmt_ex1_a_frac_zero => f_fmt_ex1_a_frac_zero , + f_fmt_ex1_a_frac_msb => f_fmt_ex1_a_frac_msb , + f_fmt_ex1_c_zero => f_fmt_ex1_c_zero , + f_fmt_ex1_c_expo_max => f_fmt_ex1_c_expo_max , + f_fmt_ex1_c_frac_zero => f_fmt_ex1_c_frac_zero , + f_fmt_ex1_c_frac_msb => f_fmt_ex1_c_frac_msb , + f_fmt_ex1_b_zero => f_fmt_ex1_b_zero , + f_fmt_ex1_b_expo_max => f_fmt_ex1_b_expo_max , + f_fmt_ex1_b_frac_zero => f_fmt_ex1_b_frac_zero , + f_fmt_ex1_b_frac_msb => f_fmt_ex1_b_frac_msb , + f_fmt_ex1_prod_zero => f_fmt_ex1_prod_zero , + f_fmt_ex2_pass_sign => f_fmt_ex2_pass_sign , + f_fmt_ex2_pass_msb => f_fmt_ex2_pass_msb , + f_fmt_ex1_b_frac_z32 => f_fmt_ex1_b_frac_z32 , + f_fmt_ex1_b_imp => f_fmt_ex1_b_imp , + f_eie_ex2_wd_ov => f_eie_ex2_wd_ov , + f_eie_ex2_dw_ov => f_eie_ex2_dw_ov , + f_eie_ex2_wd_ov_if => f_eie_ex2_wd_ov_if , + f_eie_ex2_dw_ov_if => f_eie_ex2_dw_ov_if , + f_eie_ex2_lt_bias => f_eie_ex2_lt_bias , + f_eie_ex2_eq_bias_m1 => f_eie_ex2_eq_bias_m1 , + f_alg_ex2_sel_byp => f_alg_ex2_sel_byp , + f_alg_ex2_effsub_eac_b => f_alg_ex2_effsub_eac_b , + f_alg_ex2_sh_unf => f_alg_ex2_sh_unf , + f_alg_ex2_sh_ovf => f_alg_ex2_sh_ovf , + f_alg_ex3_int_fr => f_alg_ex3_int_fr , + f_alg_ex3_int_fi => f_alg_ex3_int_fi , + f_eov_ex4_may_ovf => f_eov_ex4_may_ovf , + f_add_ex4_fpcc_iu(0) => f_add_ex4_flag_lt , + f_add_ex4_fpcc_iu(1) => f_add_ex4_flag_gt , + f_add_ex4_fpcc_iu(2) => f_add_ex4_flag_eq , + f_add_ex4_fpcc_iu(3) => f_add_ex4_flag_nan , + f_add_ex4_sign_carry => f_add_ex4_sign_carry , + f_dcd_rf1_div_beg => f_dcd_rf1_div_beg , + f_dcd_rf1_sqrt_beg => f_dcd_rf1_sqrt_beg , + f_pic_ex5_fpr_wr_dis_b => f_pic_ex5_fpr_wr_dis_b , + f_add_ex4_to_int_ovf_wd(0 to 1) => f_add_ex4_to_int_ovf_wd(0 to 1) , + f_add_ex4_to_int_ovf_dw(0 to 1) => f_add_ex4_to_int_ovf_dw(0 to 1) , + f_pic_ex1_ftdiv => f_pic_ex1_ftdiv , + f_pic_ex1_flush_en_sp => f_pic_ex1_flush_en_sp , + f_pic_ex1_flush_en_dp => f_pic_ex1_flush_en_dp , + f_pic_ex1_rnd_to_int => f_pic_ex1_rnd_to_int , + + f_pic_fmt_ex1_act => f_pic_fmt_ex1_act , + f_pic_eie_ex1_act => f_pic_eie_ex1_act , + f_pic_mul_ex1_act => f_pic_mul_ex1_act , + f_pic_alg_ex1_act => f_pic_alg_ex1_act , + f_pic_cr2_ex1_act => f_pic_cr2_ex1_act , + f_pic_tbl_ex1_act => f_pic_tbl_ex1_act , + + f_pic_add_ex1_act_b => f_pic_add_ex1_act_b , + f_pic_lza_ex1_act_b => f_pic_lza_ex1_act_b , + f_pic_eov_ex2_act_b => f_pic_eov_ex2_act_b , + f_pic_nrm_ex3_act_b => f_pic_nrm_ex3_act_b , + f_pic_rnd_ex3_act_b => f_pic_rnd_ex3_act_b , + f_pic_scr_ex2_act_b => f_pic_scr_ex2_act_b , + f_pic_ex1_effsub_raw => f_pic_ex1_effsub_raw , + f_pic_ex3_sel_est => f_pic_ex3_sel_est , + f_pic_ex1_from_integer => f_pic_ex1_from_integer , + f_pic_ex2_ue1 => f_pic_ex2_ue1 , + f_pic_ex2_frsp_ue1 => f_pic_ex2_frsp_ue1 , + f_pic_ex1_frsp_ue1 => f_pic_ex1_frsp_ue1 , + f_pic_ex1_fsel => f_pic_ex1_fsel , + f_pic_ex1_sh_ovf_do => f_pic_ex1_sh_ovf_do , + f_pic_ex1_sh_ovf_ig_b => f_pic_ex1_sh_ovf_ig_b , + f_pic_ex1_sh_unf_do => f_pic_ex1_sh_unf_do , + f_pic_ex1_sh_unf_ig_b => f_pic_ex1_sh_unf_ig_b , + f_pic_ex2_est_recip => f_pic_ex2_est_recip , + f_pic_ex2_est_rsqrt => f_pic_ex2_est_rsqrt , + f_pic_ex2_force_sel_bexp => f_pic_ex2_force_sel_bexp , + f_pic_ex2_lzo_dis_prod => f_pic_ex2_lzo_dis_prod , + f_pic_ex2_sp_b => f_pic_ex2_sp_b , + f_pic_ex2_sp_lzo => f_pic_ex2_sp_lzo , + f_pic_ex2_to_integer => f_pic_ex2_to_integer , + f_pic_ex2_prenorm => f_pic_ex2_prenorm , + f_pic_ex2_b_valid => f_pic_ex2_b_valid , + f_pic_ex2_rnd_nr => f_pic_ex2_rnd_nr , + f_pic_ex2_rnd_inf_ok => f_pic_ex2_rnd_inf_ok , + f_pic_ex2_math_bzer_b => f_pic_ex2_math_bzer_b , + f_pic_ex3_cmp_sgnneg => f_pic_ex3_cmp_sgnneg , + f_pic_ex3_cmp_sgnpos => f_pic_ex3_cmp_sgnpos , + f_pic_ex3_is_eq => f_pic_ex3_is_eq , + f_pic_ex3_is_gt => f_pic_ex3_is_gt , + f_pic_ex3_is_lt => f_pic_ex3_is_lt , + f_pic_ex3_is_nan => f_pic_ex3_is_nan , + f_pic_ex3_sp_b => f_pic_ex3_sp_b , + f_dcd_rf1_uc_mid => f_dcd_rf1_uc_mid , + f_dcd_rf1_uc_end => f_dcd_rf1_uc_end , + f_dcd_rf1_uc_special => f_dcd_rf1_uc_special , + f_mad_ex2_uc_a_expo_den_sp => f_mad_ex2_uc_a_expo_den_sp , + f_mad_ex2_uc_a_expo_den => f_mad_ex2_uc_a_expo_den , + f_dcd_ex2_uc_zx => f_dcd_ex2_uc_zx , + f_dcd_ex2_uc_vxidi => f_dcd_ex2_uc_vxidi , + f_dcd_ex2_uc_vxzdz => f_dcd_ex2_uc_vxzdz , + f_dcd_ex2_uc_vxsqrt => f_dcd_ex2_uc_vxsqrt , + f_dcd_ex2_uc_vxsnan => f_dcd_ex2_uc_vxsnan , + f_mad_ex3_uc_special => f_mad_ex3_uc_special , + f_mad_ex3_uc_zx => f_mad_ex3_uc_zx , + f_mad_ex3_uc_vxidi => f_mad_ex3_uc_vxidi , + f_mad_ex3_uc_vxzdz => f_mad_ex3_uc_vxzdz , + f_mad_ex3_uc_vxsqrt => f_mad_ex3_uc_vxsqrt , + f_mad_ex3_uc_vxsnan => f_mad_ex3_uc_vxsnan , + f_mad_ex3_uc_res_sign => f_mad_ex3_uc_res_sign , + f_mad_ex3_uc_round_mode(0 to 1) => f_mad_ex3_uc_round_mode(0 to 1) , + f_pic_ex4_byp_prod_nz => f_pic_ex4_byp_prod_nz , + f_pic_ex4_sel_est_b => f_pic_ex4_sel_est_b , + f_pic_ex4_nj_deno => f_pic_ex4_nj_deno , + f_pic_ex4_oe => f_pic_ex4_oe , + f_pic_ex4_ov_en => f_pic_ex4_ov_en , + f_pic_ex4_ovf_en_oe0_b => f_pic_ex4_ovf_en_oe0_b , + f_pic_ex4_ovf_en_oe1_b => f_pic_ex4_ovf_en_oe1_b , + f_pic_ex4_quiet_b => f_pic_ex4_quiet_b , + f_pic_ex4_rnd_inf_ok_b => f_pic_ex4_rnd_inf_ok_b , + f_pic_ex4_rnd_ni_b => f_pic_ex4_rnd_ni_b , + f_pic_ex4_rnd_nr_b => f_pic_ex4_rnd_nr_b , + f_pic_ex4_sel_fpscr_b => f_pic_ex4_sel_fpscr_b , + f_pic_ex4_sp_b => f_pic_ex4_sp_b , + f_pic_ex4_spec_inf_b => f_pic_ex4_spec_inf_b , + f_pic_ex4_spec_sel_k_e => f_pic_ex4_spec_sel_k_e , + f_pic_ex4_spec_sel_k_f => f_pic_ex4_spec_sel_k_f , + f_dcd_ex2_uc_inc_lsb => f_dcd_ex2_uc_inc_lsb , + f_dcd_ex2_uc_guard => f_dcd_ex2_uc_gs(0) , + f_dcd_ex2_uc_sticky => f_dcd_ex2_uc_gs(1) , + f_dcd_ex2_uc_gs_v => f_dcd_ex2_uc_gs_v , + f_pic_ex5_uc_inc_lsb => f_pic_ex5_uc_inc_lsb , + f_pic_ex5_uc_guard => f_pic_ex5_uc_guard , + f_pic_ex5_uc_sticky => f_pic_ex5_uc_sticky , + f_pic_ex5_uc_g_v => f_pic_ex5_uc_g_v , + f_pic_ex5_uc_s_v => f_pic_ex5_uc_s_v , + f_pic_ex4_to_int_ov_all => f_pic_ex4_to_int_ov_all , + f_pic_ex4_to_integer_b => f_pic_ex4_to_integer_b , + f_pic_ex4_word_b => f_pic_ex4_word_b , + f_pic_ex4_uns_b => f_pic_ex4_uns_b , + f_pic_ex4_ue => f_pic_ex4_ue , + f_pic_ex4_uf_en => f_pic_ex4_uf_en , + f_pic_ex4_unf_en_ue0_b => f_pic_ex4_unf_en_ue0_b , + f_pic_ex4_unf_en_ue1_b => f_pic_ex4_unf_en_ue1_b , + f_pic_ex5_en_exact_zero => f_pic_ex5_en_exact_zero , + f_pic_ex5_compare_b => f_pic_ex5_compare_b , + f_pic_ex5_frsp => f_pic_ex5_frsp , + f_pic_ex5_fi_pipe_v_b => f_pic_ex5_fi_pipe_v_b , + f_pic_ex5_fi_spec_b => f_pic_ex5_fi_spec_b , + f_pic_ex5_flag_vxcvi_b => f_pic_ex5_flag_vxcvi_b , + f_pic_ex5_flag_vxidi_b => f_pic_ex5_flag_vxidi_b , + f_pic_ex5_flag_vximz_b => f_pic_ex5_flag_vximz_b , + f_pic_ex5_flag_vxisi_b => f_pic_ex5_flag_vxisi_b , + f_pic_ex5_flag_vxsnan_b => f_pic_ex5_flag_vxsnan_b , + f_pic_ex5_flag_vxsqrt_b => f_pic_ex5_flag_vxsqrt_b , + f_pic_ex5_flag_vxvc_b => f_pic_ex5_flag_vxvc_b , + f_pic_ex5_flag_vxzdz_b => f_pic_ex5_flag_vxzdz_b , + f_pic_ex5_flag_zx_b => f_pic_ex5_flag_zx_b , + f_pic_ex5_fprf_hold_b => f_pic_ex5_fprf_hold_b , + f_pic_ex5_fprf_pipe_v_b => f_pic_ex5_fprf_pipe_v_b , + f_pic_ex5_fprf_spec_b(0 to 4) => f_pic_ex5_fprf_spec_b(0 to 4) , + f_pic_ex5_fr_pipe_v_b => f_pic_ex5_fr_pipe_v_b , + f_pic_ex5_fr_spec_b => f_pic_ex5_fr_spec_b , + f_pic_ex5_invert_sign => f_pic_ex5_invert_sign , + f_pic_ex5_k_nan => f_pic_ex5_k_nan , + f_pic_ex5_k_inf => f_pic_ex5_k_inf , + f_pic_ex5_k_max => f_pic_ex5_k_max , + f_pic_ex5_k_zer => f_pic_ex5_k_zer , + f_pic_ex5_k_one => f_pic_ex5_k_one , + f_pic_ex5_k_int_maxpos => f_pic_ex5_k_int_maxpos , + f_pic_ex5_k_int_maxneg => f_pic_ex5_k_int_maxneg , + f_pic_ex5_k_int_zer => f_pic_ex5_k_int_zer , + f_pic_ex5_ox_pipe_v_b => f_pic_ex5_ox_pipe_v_b , + f_pic_ex5_round_sign => f_pic_ex5_round_sign , + f_pic_ex5_scr_upd_move_b => f_pic_ex5_scr_upd_move_b , + f_pic_ex5_scr_upd_pipe_b => f_pic_ex5_scr_upd_pipe_b , + f_pic_ex1_nj_deni => f_pic_ex1_nj_deni , + f_dcd_rf1_nj_deni => f_dcd_rf1_nj_deni , + f_pic_ex5_ux_pipe_v_b => f_pic_ex5_ux_pipe_v_b ); + +fcr2 : entity WORK.fuq_cr2(fuq_cr2) generic map( expand_type => expand_type) port map( + vdd => vdd , + gnd => gnd , + nclk => nclk , + clkoff_b => clkoff_b , + act_dis => act_dis , + flush => flush , + delay_lclkr => delay_lclkr(1 to 7) , + mpw1_b => mpw1_b(1 to 7) , + mpw2_b => mpw2_b(0 to 1) , + thold_1 => perv_cr2_thold_1 , + sg_1 => perv_cr2_sg_1 , + fpu_enable => perv_cr2_fpu_enable , + + + f_cr2_si => scan_in(14) , + f_cr2_so => scan_out(14) , + rf1_act => f_dcd_rf1_act , + ex1_act => f_pic_cr2_ex1_act , + rf1_thread_b(0 to 3) => rf1_thread_b(0 to 3) , + f_dcd_ex6_cancel => f_dcd_ex6_cancel , + f_fmt_ex1_bop_byt(45 to 52) => f_fmt_ex1_bop_byt(45 to 52) , + f_dcd_rf1_fpscr_bit_data_b(0 to 3) => f_dcd_rf1_fpscr_bit_data_b(0 to 3) , + f_dcd_rf1_fpscr_bit_mask_b(0 to 3) => f_dcd_rf1_fpscr_bit_mask_b(0 to 3) , + f_dcd_rf1_fpscr_nib_mask_b(0 to 8) => f_dcd_rf1_fpscr_nib_mask_b(0 to 8) , + f_dcd_rf1_mtfsbx_b => f_dcd_rf1_mtfsbx_b , + f_dcd_rf1_mcrfs_b => f_dcd_rf1_mcrfs_b , + f_dcd_rf1_mtfsf_b => f_dcd_rf1_mtfsf_b , + f_dcd_rf1_mtfsfi_b => f_dcd_rf1_mtfsfi_b , + f_cr2_ex3_thread_b(0 to 3) => f_cr2_ex3_thread_b(0 to 3) , + f_cr2_ex3_fpscr_bit_data_b(0 to 3) => f_cr2_ex3_fpscr_bit_data_b(0 to 3) , + f_cr2_ex3_fpscr_bit_mask_b(0 to 3) => f_cr2_ex3_fpscr_bit_mask_b(0 to 3) , + f_cr2_ex3_fpscr_nib_mask_b(0 to 8) => f_cr2_ex3_fpscr_nib_mask_b(0 to 8) , + f_cr2_ex3_mtfsbx_b => f_cr2_ex3_mtfsbx_b , + f_cr2_ex3_mcrfs_b => f_cr2_ex3_mcrfs_b , + f_cr2_ex3_mtfsf_b => f_cr2_ex3_mtfsf_b , + f_cr2_ex3_mtfsfi_b => f_cr2_ex3_mtfsfi_b , + f_cr2_ex5_fpscr_rd_dat(24 to 31) => f_cr2_ex5_fpscr_rd_dat(24 to 31) , + f_cr2_ex6_fpscr_rd_dat(24 to 31) => f_cr2_ex6_fpscr_rd_dat(24 to 31) , + f_cr2_ex1_fpscr_shadow(0 to 7) => f_cr2_ex1_fpscr_shadow(0 to 7) ); + + + +fscr : entity WORK.fuq_scr(fuq_scr) generic map( expand_type => expand_type) port map( + vdd => vdd , + gnd => gnd , + nclk => nclk , + clkoff_b => clkoff_b , + act_dis => act_dis , + flush => flush , + delay_lclkr => delay_lclkr(4 to 7) , + mpw1_b => mpw1_b(4 to 7) , + mpw2_b => mpw2_b(0 to 1) , + thold_1 => perv_scr_thold_1 , + sg_1 => perv_scr_sg_1 , + fpu_enable => perv_scr_fpu_enable , + + f_scr_si => scan_in(15) , + f_scr_so => scan_out(15) , + ex2_act_b => f_pic_scr_ex2_act_b , + f_cr2_ex3_thread_b(0 to 3) => f_cr2_ex3_thread_b(0 to 3) , + + f_dcd_ex6_cancel => f_dcd_ex6_cancel , + + f_pic_ex5_scr_upd_move_b => f_pic_ex5_scr_upd_move_b , + f_pic_ex5_scr_upd_pipe_b => f_pic_ex5_scr_upd_pipe_b , + f_pic_ex5_fprf_spec_b(0 to 4) => f_pic_ex5_fprf_spec_b(0 to 4) , + f_pic_ex5_compare_b => f_pic_ex5_compare_b , + f_pic_ex5_fprf_pipe_v_b => f_pic_ex5_fprf_pipe_v_b , + f_pic_ex5_fprf_hold_b => f_pic_ex5_fprf_hold_b , + f_pic_ex5_fi_spec_b => f_pic_ex5_fi_spec_b , + f_pic_ex5_fi_pipe_v_b => f_pic_ex5_fi_pipe_v_b , + f_pic_ex5_fr_spec_b => f_pic_ex5_fr_spec_b , + f_pic_ex5_fr_pipe_v_b => f_pic_ex5_fr_pipe_v_b , + f_pic_ex5_ox_spec_b => tiup , + f_pic_ex5_ox_pipe_v_b => f_pic_ex5_ox_pipe_v_b , + f_pic_ex5_ux_spec_b => tiup , + f_pic_ex5_ux_pipe_v_b => f_pic_ex5_ux_pipe_v_b , + f_pic_ex5_flag_vxsnan_b => f_pic_ex5_flag_vxsnan_b , + f_pic_ex5_flag_vxisi_b => f_pic_ex5_flag_vxisi_b , + f_pic_ex5_flag_vxidi_b => f_pic_ex5_flag_vxidi_b , + f_pic_ex5_flag_vxzdz_b => f_pic_ex5_flag_vxzdz_b , + f_pic_ex5_flag_vximz_b => f_pic_ex5_flag_vximz_b , + f_pic_ex5_flag_vxvc_b => f_pic_ex5_flag_vxvc_b , + f_pic_ex5_flag_vxsqrt_b => f_pic_ex5_flag_vxsqrt_b , + f_pic_ex5_flag_vxcvi_b => f_pic_ex5_flag_vxcvi_b , + f_pic_ex5_flag_zx_b => f_pic_ex5_flag_zx_b , + f_nrm_ex5_fpscr_wr_dat_dfp(0 to 3) => f_nrm_ex5_fpscr_wr_dat_dfp(0 to 3) , + f_nrm_ex5_fpscr_wr_dat(0 to 31) => f_nrm_ex5_fpscr_wr_dat(0 to 31) , + f_cr2_ex3_fpscr_bit_data_b(0 to 3) => f_cr2_ex3_fpscr_bit_data_b(0 to 3) , + f_cr2_ex3_fpscr_bit_mask_b(0 to 3) => f_cr2_ex3_fpscr_bit_mask_b(0 to 3) , + f_cr2_ex3_fpscr_nib_mask_b(0 to 8) => f_cr2_ex3_fpscr_nib_mask_b(0 to 8) , + f_cr2_ex3_mtfsbx_b => f_cr2_ex3_mtfsbx_b , + f_cr2_ex3_mcrfs_b => f_cr2_ex3_mcrfs_b , + f_cr2_ex3_mtfsf_b => f_cr2_ex3_mtfsf_b , + f_cr2_ex3_mtfsfi_b => f_cr2_ex3_mtfsfi_b , + f_rnd_ex6_flag_up => f_rnd_ex6_flag_up , + f_rnd_ex6_flag_fi => f_rnd_ex6_flag_fi , + f_rnd_ex6_flag_ox => f_rnd_ex6_flag_ox , + f_rnd_ex6_flag_den => f_rnd_ex6_flag_den , + f_rnd_ex6_flag_sgn => f_rnd_ex6_flag_sgn , + f_rnd_ex6_flag_inf => f_rnd_ex6_flag_inf , + f_rnd_ex6_flag_zer => f_rnd_ex6_flag_zer , + f_rnd_ex6_flag_ux => f_rnd_ex6_flag_ux , + f_cr2_ex6_fpscr_rd_dat(24 to 31) => f_cr2_ex6_fpscr_rd_dat(24 to 31) , + f_cr2_ex5_fpscr_rd_dat(24 to 31) => f_cr2_ex5_fpscr_rd_dat(24 to 31) , + f_scr_ex5_fpscr_rd_dat(0 to 31) => f_scr_ex5_fpscr_rd_dat(0 to 31) , + f_scr_ex5_fpscr_rd_dat_dfp(0 to 3) => f_scr_ex5_fpscr_rd_dat_dfp(0 to 3) , + f_scr_ex7_cr_fld(0 to 3) => f_scr_ex7_cr_fld(0 to 3) , + f_scr_ex7_fx_thread0(0 to 3) => f_scr_ex7_fx_thread0(0 to 3) , + f_scr_ex7_fx_thread1(0 to 3) => f_scr_ex7_fx_thread1(0 to 3) , + f_scr_ex7_fx_thread2(0 to 3) => f_scr_ex7_fx_thread2(0 to 3) , + f_scr_ex7_fx_thread3(0 to 3) => f_scr_ex7_fx_thread3(0 to 3) ); + + +ftbe : entity WORK.fuq_tblexp(fuq_tblexp) generic map( expand_type => expand_type) port map( + vdd => vdd , + gnd => gnd , + nclk => nclk , + clkoff_b => clkoff_b , + act_dis => act_dis , + flush => flush , + delay_lclkr => delay_lclkr(2 to 3) , + mpw1_b => mpw1_b(2 to 3) , + mpw2_b => mpw2_b(0 to 0) , + thold_1 => perv_tbe_thold_1 , + sg_1 => perv_tbe_sg_1 , + fpu_enable => perv_tbe_fpu_enable , + + si => scan_in(16) , + so => scan_out(16) , + ex1_act_b => f_pic_lza_ex1_act_b , + f_pic_ex2_ue1 => f_pic_ex2_ue1 , + f_pic_ex2_sp_b => f_pic_ex2_sp_b , + f_pic_ex2_est_recip => f_pic_ex2_est_recip , + f_pic_ex2_est_rsqrt => f_pic_ex2_est_rsqrt , + f_eie_ex2_tbl_expo(1 to 13) => f_eie_ex2_tbl_expo(1 to 13) , + f_fmt_ex2_lu_den_recip => f_fmt_ex2_lu_den_recip , + f_fmt_ex2_lu_den_rsqrto => f_fmt_ex2_lu_den_rsqrto , + f_tbe_ex3_match_en_sp => f_tbe_ex3_match_en_sp , + f_tbe_ex3_match_en_dp => f_tbe_ex3_match_en_dp , + f_tbe_ex3_recip_2046 => f_tbe_ex3_recip_2046 , + f_tbe_ex3_recip_2045 => f_tbe_ex3_recip_2045 , + f_tbe_ex3_recip_2044 => f_tbe_ex3_recip_2044 , + f_tbe_ex3_lu_sh => f_tbe_ex3_lu_sh , + f_tbe_ex3_recip_ue1 => f_tbe_ex3_recip_ue1 , + f_tbe_ex3_may_ov => f_tbe_ex3_may_ov , + f_tbe_ex3_res_expo(1 to 13) => f_tbe_ex3_res_expo(1 to 13) ); + +ftbl : entity WORK.fuq_tbllut(fuq_tbllut) generic map( expand_type => expand_type) port map( + vdd => vdd , + gnd => gnd , + nclk => nclk , + clkoff_b => clkoff_b , + act_dis => act_dis , + flush => flush , + delay_lclkr => delay_lclkr(2 to 5) , + mpw1_b => mpw1_b(2 to 5) , + mpw2_b => mpw2_b(0 to 1) , + thold_1 => perv_tbl_thold_1 , + sg_1 => perv_tbl_sg_1 , + fpu_enable => perv_tbl_fpu_enable , + + si => scan_in(17) , + so => scan_out(17) , + ex1_act => f_pic_tbl_ex1_act , + f_fmt_ex1_b_frac(1 to 6) => f_fmt_ex1_b_frac(1 to 6) , + f_fmt_ex2_b_frac(7 to 22) => f_fmt_ex2_pass_frac(7 to 22) , + f_tbe_ex2_expo_lsb => f_eie_ex2_tbl_expo(13) , + f_tbe_ex2_est_recip => f_pic_ex2_est_recip , + f_tbe_ex2_est_rsqrt => f_pic_ex2_est_rsqrt , + f_tbe_ex3_recip_ue1 => f_tbe_ex3_recip_ue1 , + f_tbe_ex3_lu_sh => f_tbe_ex3_lu_sh , + f_tbe_ex3_match_en_sp => f_tbe_ex3_match_en_sp , + f_tbe_ex3_match_en_dp => f_tbe_ex3_match_en_dp , + f_tbe_ex3_recip_2046 => f_tbe_ex3_recip_2046 , + f_tbe_ex3_recip_2045 => f_tbe_ex3_recip_2045 , + f_tbe_ex3_recip_2044 => f_tbe_ex3_recip_2044 , + f_tbl_ex5_est_frac(0 to 26) => f_tbl_ex5_est_frac(0 to 26) , + f_tbl_ex4_unf_expo => f_tbl_ex4_unf_expo , + f_tbl_ex5_recip_den => f_tbl_ex5_recip_den ); + + + + + + + + perv_tbl_sg_1 <= sg_1 ; + perv_tbe_sg_1 <= sg_1 ; + perv_eie_sg_1 <= sg_1 ; + perv_eov_sg_1 <= sg_1 ; + perv_fmt_sg_1 <= sg_1 ; + perv_mul_sg_1 <= sg_1 ; + perv_alg_sg_1 <= sg_1 ; + perv_sa3_sg_1 <= sg_1 ; + perv_add_sg_1 <= sg_1 ; + perv_lza_sg_1 <= sg_1 ; + perv_nrm_sg_1 <= sg_1 ; + perv_rnd_sg_1 <= sg_1 ; + perv_scr_sg_1 <= sg_1 ; + perv_pic_sg_1 <= sg_1 ; + perv_cr2_sg_1 <= sg_1 ; + + perv_tbl_thold_1 <= thold_1 ; + perv_tbe_thold_1 <= thold_1 ; + perv_eie_thold_1 <= thold_1 ; + perv_eov_thold_1 <= thold_1 ; + perv_fmt_thold_1 <= thold_1 ; + perv_mul_thold_1 <= thold_1 ; + perv_alg_thold_1 <= thold_1 ; + perv_sa3_thold_1 <= thold_1 ; + perv_add_thold_1 <= thold_1 ; + perv_lza_thold_1 <= thold_1 ; + perv_nrm_thold_1 <= thold_1 ; + perv_rnd_thold_1 <= thold_1 ; + perv_scr_thold_1 <= thold_1 ; + perv_pic_thold_1 <= thold_1 ; + perv_cr2_thold_1 <= thold_1 ; + + perv_tbl_fpu_enable <= fpu_enable ; + perv_tbe_fpu_enable <= fpu_enable ; + perv_eie_fpu_enable <= fpu_enable ; + perv_eov_fpu_enable <= fpu_enable ; + perv_fmt_fpu_enable <= fpu_enable ; + perv_mul_fpu_enable <= fpu_enable ; + perv_alg_fpu_enable <= fpu_enable ; + perv_sa3_fpu_enable <= fpu_enable ; + perv_add_fpu_enable <= fpu_enable ; + perv_lza_fpu_enable <= fpu_enable ; + perv_nrm_fpu_enable <= fpu_enable ; + perv_rnd_fpu_enable <= fpu_enable ; + perv_scr_fpu_enable <= fpu_enable ; + perv_pic_fpu_enable <= fpu_enable ; + perv_cr2_fpu_enable <= fpu_enable ; + + + + + +end fuq_mad; + + + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_mul.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_mul.vhdl new file mode 100644 index 0000000..ed1bcb8 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_mul.vhdl @@ -0,0 +1,272 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; +library clib ; + + + +entity fuq_mul is +generic( expand_type : integer := 2 ); +port( + + vdd :inout power_logic; + gnd :inout power_logic; + clkoff_b :in std_ulogic; + act_dis :in std_ulogic; + flush :in std_ulogic; + delay_lclkr :in std_ulogic; + mpw1_b :in std_ulogic; + mpw2_b :in std_ulogic; + sg_1 :in std_ulogic; + thold_1 :in std_ulogic; + fpu_enable :in std_ulogic; + nclk :in clk_logic; + + f_mul_si :in std_ulogic; + f_mul_so :out std_ulogic; + ex1_act :in std_ulogic; + + f_fmt_ex1_a_frac :in std_ulogic_vector(0 to 52) ; + f_fmt_ex1_a_frac_17 :in std_ulogic; + f_fmt_ex1_a_frac_35 :in std_ulogic; + f_fmt_ex1_c_frac :in std_ulogic_vector(0 to 53) ; + + f_mul_ex2_sum :out std_ulogic_vector(1 to 108); + f_mul_ex2_car :out std_ulogic_vector(1 to 108) +); + + + +end fuq_mul; + +architecture fuq_mul of fuq_mul is + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal thold_0_b, thold_0, forcee :std_ulogic; + signal sg_0 :std_ulogic; + signal spare_unused :std_ulogic_vector(0 to 3); + signal act_so , act_si :std_ulogic_vector(0 to 3); + signal m92_0_so, m92_1_so, m92_2_so :std_ulogic; + signal pp3_05 :std_ulogic_vector(36 to 108) ; + signal pp3_04 :std_ulogic_vector(35 to 108) ; + signal pp3_03 :std_ulogic_vector(18 to 90) ; + signal pp3_02 :std_ulogic_vector(17 to 90) ; + signal pp3_01 :std_ulogic_vector(0 to 72) ; + signal pp3_00 :std_ulogic_vector(0 to 72) ; + + + signal hot_one_msb_unused :std_ulogic; + signal hot_one_74 :std_ulogic; + signal hot_one_92 :std_ulogic; + signal xtd_unused :std_ulogic; + + + signal pp5_00 :std_ulogic_vector(1 to 108); + signal pp5_01 :std_ulogic_vector(1 to 108); + + +begin + + + thold_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => thold_1, + q(0) => thold_0 ); + + sg_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => sg_1 , + q(0) => sg_0 ); + + + lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map ( + clkoff_b => clkoff_b, + thold => thold_0, + sg => sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => thold_0_b ); + + + + + act_lat: tri_rlmreg_p generic map (width=> 4, expand_type => expand_type, needs_sreset => 0) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr , + mpw1_b => mpw1_b , + mpw2_b => mpw2_b , + vd => vdd, + gd => gnd, + nclk => nclk, + act => fpu_enable, + thold_b => thold_0_b, + sg => sg_0, + scout => act_so, + scin => act_si, + din(0) => spare_unused(0), + din(1) => spare_unused(1), + din(2) => spare_unused(2), + din(3) => spare_unused(3), + dout(0) => spare_unused(0), + dout(1) => spare_unused(1), + dout(2) => spare_unused(2) , + dout(3) => spare_unused(3) ); + +act_si(0 to 3) <= act_so(1 to 3) & m92_2_so; + +f_mul_so <= act_so(0) ; + + + + + + + + + + + +m92_2: entity work.fuq_mul_92(fuq_mul_92) generic map(inst=> 2, expand_type => expand_type) port map( + vdd => vdd , + gnd => gnd , + nclk => nclk , + forcee => forcee, + lcb_delay_lclkr => delay_lclkr , + lcb_mpw1_b => mpw1_b , + lcb_mpw2_b => mpw2_b , + thold_b => thold_0_b , + lcb_sg => sg_0 , + si => f_mul_si , + so => m92_0_so , + ex1_act => ex1_act , + c_frac(0 to 53) => f_fmt_ex1_c_frac(0 to 53) , + a_frac(17 to 34) => f_fmt_ex1_a_frac(35 to 52) , + a_frac(35) => tidn , + hot_one_out => hot_one_92 , + sum92(2 to 74) => pp3_05(36 to 108) , + car92(1 to 74) => pp3_04(35 to 108) ); + +m92_1: entity work.fuq_mul_92(fuq_mul_92) generic map(inst=> 1, expand_type => expand_type) port map( + vdd => vdd , + gnd => gnd , + nclk => nclk , + forcee => forcee, + lcb_delay_lclkr => delay_lclkr , + lcb_mpw1_b => mpw1_b , + lcb_mpw2_b => mpw2_b , + thold_b => thold_0_b , + lcb_sg => sg_0 , + si => m92_0_so , + so => m92_1_so , + ex1_act => ex1_act , + c_frac(0 to 53) => f_fmt_ex1_c_frac(0 to 53) , + a_frac(17 to 34) => f_fmt_ex1_a_frac(17 to 34) , + a_frac(35) => f_fmt_ex1_a_frac_35 , + hot_one_out => hot_one_74 , + sum92(2 to 74) => pp3_03(18 to 90) , + car92(1 to 74) => pp3_02(17 to 90) ); + +m92_0: entity work.fuq_mul_92(fuq_mul_92) generic map(inst=> 0, expand_type => expand_type) port map( + vdd => vdd , + gnd => gnd , + nclk => nclk , + forcee => forcee, + lcb_delay_lclkr => delay_lclkr , + lcb_mpw1_b => mpw1_b , + lcb_mpw2_b => mpw2_b , + thold_b => thold_0_b , + lcb_sg => sg_0 , + si => m92_1_so , + so => m92_2_so , + ex1_act => ex1_act , + c_frac(0 to 53) => f_fmt_ex1_c_frac(0 to 53) , + a_frac(17) => tidn , + a_frac(18 to 34) => f_fmt_ex1_a_frac(0 to 16) , + a_frac(35) => f_fmt_ex1_a_frac_17 , + hot_one_out => hot_one_msb_unused , + sum92(2 to 74) => pp3_01(0 to 72) , + car92(1) => xtd_unused , + car92(2 to 74) => pp3_00(0 to 72) ); + + + + + m62: entity work.fuq_mul_62(fuq_mul_62) port map( + vdd => vdd, + gnd => gnd, + hot_one_92 => hot_one_92 , + hot_one_74 => hot_one_74 , + pp3_05(36 to 108) => pp3_05(36 to 108) , + pp3_04(35 to 108) => pp3_04(35 to 108) , + pp3_03(18 to 90) => pp3_03(18 to 90) , + pp3_02(17 to 90) => pp3_02(17 to 90) , + pp3_01( 0 to 72) => pp3_01( 0 to 72) , + pp3_00( 0 to 72) => pp3_00( 0 to 72) , + + sum62(1 to 108) => pp5_01(1 to 108) , + car62(1 to 108) => pp5_00(1 to 108) ); + + + + f_mul_ex2_sum(1 to 108) <= pp5_01(1 to 108); + f_mul_ex2_car(1 to 108) <= pp5_00(1 to 108); + + + +end; + + + + + + + + + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_mul_62.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_mul_62.vhdl new file mode 100644 index 0000000..395e75e --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_mul_62.vhdl @@ -0,0 +1,2012 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee,ibm,support,tri, work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; +library clib ; + + +entity fuq_mul_62 is +port( + + vdd : inout power_logic; + gnd : inout power_logic; + hot_one_92 :in std_ulogic; + hot_one_74 :in std_ulogic; + pp3_05 :in std_ulogic_vector(36 to 108); + pp3_04 :in std_ulogic_vector(35 to 108); + pp3_03 :in std_ulogic_vector(18 to 90); + pp3_02 :in std_ulogic_vector(17 to 90); + pp3_01 :in std_ulogic_vector( 0 to 72); + pp3_00 :in std_ulogic_vector( 0 to 72); + + sum62 :out std_ulogic_vector(1 to 108); + car62 :out std_ulogic_vector(1 to 108) + +); + + + + +end fuq_mul_62; + +architecture fuq_mul_62 of fuq_mul_62 is + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + + signal pp4_03 :std_ulogic_vector( 18 to 108); + signal pp4_02 :std_ulogic_vector( 34 to 108); + signal pp4_01 :std_ulogic_vector( 1 to 90); + signal pp4_00 :std_ulogic_vector( 0 to 74); + signal pp5_00 :std_ulogic_vector( 0 to 108); + signal pp5_01 :std_ulogic_vector( 1 to 108); + signal pp5_00_ko :std_ulogic_vector( 17 to 73); + + signal pp3_05_inv, pp3_05_buf :std_ulogic_vector(36 to 108); + signal pp3_04_inv, pp3_04_buf :std_ulogic_vector(35 to 108); + signal pp3_03_inv, pp3_03_buf :std_ulogic_vector(18 to 90); + signal pp3_02_inv, pp3_02_buf :std_ulogic_vector(17 to 90); + signal pp3_01_inv :std_ulogic_vector( 1 to 72); + signal pp3_01_buf :std_ulogic_vector( 1 to 72); + signal pp3_00_inv :std_ulogic_vector( 1 to 72); + signal pp3_00_buf :std_ulogic_vector( 1 to 72); + signal hot_one_92_inv, hot_one_92_buf :std_ulogic; + signal hot_one_74_inv, hot_one_74_buf :std_ulogic; + signal unused :std_ulogic; + + + + + + + + + + + + + + + + + + +begin + +unused <= pp4_02(92) or pp4_00(72) or pp4_00(73) or pp4_00(0) or pp5_00(0) or + pp3_00(0) or pp3_01(0) ; + + + + + + + + + + inv_p3_05: pp3_05_inv(36 to 108) <= not pp3_05(36 to 108); + inv_p3_04: pp3_04_inv(35 to 108) <= not pp3_04(35 to 108); + inv_p3_03: pp3_03_inv(18 to 90) <= not pp3_03(18 to 90); + inv_p3_02: pp3_02_inv(17 to 90) <= not pp3_02(17 to 90); + inv_p3_01: pp3_01_inv( 1 to 72) <= not pp3_01( 1 to 72); + inv_p3_00: pp3_00_inv( 1 to 72) <= not pp3_00( 1 to 72); + inv_hot_one_92: hot_one_92_inv <= not hot_one_92 ; + inv_hot_one_74: hot_one_74_inv <= not hot_one_74 ; + + buf_pp3_05: pp3_05_buf(36 to 108) <= not pp3_05_inv(36 to 108); + buf_pp3_04: pp3_04_buf(35 to 108) <= not pp3_04_inv(35 to 108); + buf_pp3_03: pp3_03_buf(18 to 90) <= not pp3_03_inv(18 to 90); + buf_pp3_02: pp3_02_buf(17 to 90) <= not pp3_02_inv(17 to 90); + buf_pp3_01: pp3_01_buf( 1 to 72) <= not pp3_01_inv( 1 to 72); + buf_pp3_00: pp3_00_buf( 1 to 72) <= not pp3_00_inv( 1 to 72); + buf_hot_one_92: hot_one_92_buf <= not hot_one_92_inv ; + buf_hot_one_74: hot_one_74_buf <= not hot_one_74_inv ; + + + + pp4_03(93 to 108) <= pp3_05_buf(93 to 108) ; + pp4_02(93 to 108) <= pp3_04_buf(93 to 108) ; + pp4_02(92) <= tidn ; + +pp4_01_csa_92: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(92) , + b => pp3_04_buf(92) , + c => hot_one_92_buf , + sum => pp4_03(92) , + car => pp4_02(91) ); +pp4_01_csa_91: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp3_05_buf(91) , + b => pp3_04_buf(91) , + sum => pp4_03(91) , + car => pp4_02(90) ); +pp4_01_csa_90: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(90) , + b => pp3_04_buf(90) , + c => pp3_03_buf(90) , + sum => pp4_03(90) , + car => pp4_02(89) ); +pp4_01_csa_89: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(89) , + b => pp3_04_buf(89) , + c => pp3_03_buf(89) , + sum => pp4_03(89) , + car => pp4_02(88) ); +pp4_01_csa_88: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(88) , + b => pp3_04_buf(88) , + c => pp3_03_buf(88) , + sum => pp4_03(88) , + car => pp4_02(87) ); +pp4_01_csa_87: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(87) , + b => pp3_04_buf(87) , + c => pp3_03_buf(87) , + sum => pp4_03(87) , + car => pp4_02(86) ); +pp4_01_csa_86: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(86) , + b => pp3_04_buf(86) , + c => pp3_03_buf(86) , + sum => pp4_03(86) , + car => pp4_02(85) ); +pp4_01_csa_85: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(85) , + b => pp3_04_buf(85) , + c => pp3_03_buf(85) , + sum => pp4_03(85) , + car => pp4_02(84) ); +pp4_01_csa_84: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(84) , + b => pp3_04_buf(84) , + c => pp3_03_buf(84) , + sum => pp4_03(84) , + car => pp4_02(83) ); +pp4_01_csa_83: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(83) , + b => pp3_04_buf(83) , + c => pp3_03_buf(83) , + sum => pp4_03(83) , + car => pp4_02(82) ); +pp4_01_csa_82: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(82) , + b => pp3_04_buf(82) , + c => pp3_03_buf(82) , + sum => pp4_03(82) , + car => pp4_02(81) ); +pp4_01_csa_81: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(81) , + b => pp3_04_buf(81) , + c => pp3_03_buf(81) , + sum => pp4_03(81) , + car => pp4_02(80) ); +pp4_01_csa_80: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(80) , + b => pp3_04_buf(80) , + c => pp3_03_buf(80) , + sum => pp4_03(80) , + car => pp4_02(79) ); +pp4_01_csa_79: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(79) , + b => pp3_04_buf(79) , + c => pp3_03_buf(79) , + sum => pp4_03(79) , + car => pp4_02(78) ); +pp4_01_csa_78: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(78) , + b => pp3_04_buf(78) , + c => pp3_03_buf(78) , + sum => pp4_03(78) , + car => pp4_02(77) ); +pp4_01_csa_77: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(77) , + b => pp3_04_buf(77) , + c => pp3_03_buf(77) , + sum => pp4_03(77) , + car => pp4_02(76) ); +pp4_01_csa_76: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(76) , + b => pp3_04_buf(76) , + c => pp3_03_buf(76) , + sum => pp4_03(76) , + car => pp4_02(75) ); +pp4_01_csa_75: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(75) , + b => pp3_04_buf(75) , + c => pp3_03_buf(75) , + sum => pp4_03(75) , + car => pp4_02(74) ); +pp4_01_csa_74: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(74) , + b => pp3_04_buf(74) , + c => pp3_03_buf(74) , + sum => pp4_03(74) , + car => pp4_02(73) ); +pp4_01_csa_73: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(73) , + b => pp3_04_buf(73) , + c => pp3_03_buf(73) , + sum => pp4_03(73) , + car => pp4_02(72) ); +pp4_01_csa_72: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(72) , + b => pp3_04_buf(72) , + c => pp3_03_buf(72) , + sum => pp4_03(72) , + car => pp4_02(71) ); +pp4_01_csa_71: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(71) , + b => pp3_04_buf(71) , + c => pp3_03_buf(71) , + sum => pp4_03(71) , + car => pp4_02(70) ); +pp4_01_csa_70: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(70) , + b => pp3_04_buf(70) , + c => pp3_03_buf(70) , + sum => pp4_03(70) , + car => pp4_02(69) ); +pp4_01_csa_69: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(69) , + b => pp3_04_buf(69) , + c => pp3_03_buf(69) , + sum => pp4_03(69) , + car => pp4_02(68) ); +pp4_01_csa_68: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(68) , + b => pp3_04_buf(68) , + c => pp3_03_buf(68) , + sum => pp4_03(68) , + car => pp4_02(67) ); +pp4_01_csa_67: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(67) , + b => pp3_04_buf(67) , + c => pp3_03_buf(67) , + sum => pp4_03(67) , + car => pp4_02(66) ); +pp4_01_csa_66: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(66) , + b => pp3_04_buf(66) , + c => pp3_03_buf(66) , + sum => pp4_03(66) , + car => pp4_02(65) ); +pp4_01_csa_65: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(65) , + b => pp3_04_buf(65) , + c => pp3_03_buf(65) , + sum => pp4_03(65) , + car => pp4_02(64) ); +pp4_01_csa_64: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(64) , + b => pp3_04_buf(64) , + c => pp3_03_buf(64) , + sum => pp4_03(64) , + car => pp4_02(63) ); +pp4_01_csa_63: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(63) , + b => pp3_04_buf(63) , + c => pp3_03_buf(63) , + sum => pp4_03(63) , + car => pp4_02(62) ); +pp4_01_csa_62: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(62) , + b => pp3_04_buf(62) , + c => pp3_03_buf(62) , + sum => pp4_03(62) , + car => pp4_02(61) ); +pp4_01_csa_61: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(61) , + b => pp3_04_buf(61) , + c => pp3_03_buf(61) , + sum => pp4_03(61) , + car => pp4_02(60) ); +pp4_01_csa_60: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(60) , + b => pp3_04_buf(60) , + c => pp3_03_buf(60) , + sum => pp4_03(60) , + car => pp4_02(59) ); +pp4_01_csa_59: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(59) , + b => pp3_04_buf(59) , + c => pp3_03_buf(59) , + sum => pp4_03(59) , + car => pp4_02(58) ); +pp4_01_csa_58: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(58) , + b => pp3_04_buf(58) , + c => pp3_03_buf(58) , + sum => pp4_03(58) , + car => pp4_02(57) ); +pp4_01_csa_57: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(57) , + b => pp3_04_buf(57) , + c => pp3_03_buf(57) , + sum => pp4_03(57) , + car => pp4_02(56) ); +pp4_01_csa_56: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(56) , + b => pp3_04_buf(56) , + c => pp3_03_buf(56) , + sum => pp4_03(56) , + car => pp4_02(55) ); +pp4_01_csa_55: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(55) , + b => pp3_04_buf(55) , + c => pp3_03_buf(55) , + sum => pp4_03(55) , + car => pp4_02(54) ); +pp4_01_csa_54: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(54) , + b => pp3_04_buf(54) , + c => pp3_03_buf(54) , + sum => pp4_03(54) , + car => pp4_02(53) ); +pp4_01_csa_53: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(53) , + b => pp3_04_buf(53) , + c => pp3_03_buf(53) , + sum => pp4_03(53) , + car => pp4_02(52) ); +pp4_01_csa_52: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(52) , + b => pp3_04_buf(52) , + c => pp3_03_buf(52) , + sum => pp4_03(52) , + car => pp4_02(51) ); +pp4_01_csa_51: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(51) , + b => pp3_04_buf(51) , + c => pp3_03_buf(51) , + sum => pp4_03(51) , + car => pp4_02(50) ); +pp4_01_csa_50: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(50) , + b => pp3_04_buf(50) , + c => pp3_03_buf(50) , + sum => pp4_03(50) , + car => pp4_02(49) ); +pp4_01_csa_49: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(49) , + b => pp3_04_buf(49) , + c => pp3_03_buf(49) , + sum => pp4_03(49) , + car => pp4_02(48) ); +pp4_01_csa_48: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(48) , + b => pp3_04_buf(48) , + c => pp3_03_buf(48) , + sum => pp4_03(48) , + car => pp4_02(47) ); +pp4_01_csa_47: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(47) , + b => pp3_04_buf(47) , + c => pp3_03_buf(47) , + sum => pp4_03(47) , + car => pp4_02(46) ); +pp4_01_csa_46: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(46) , + b => pp3_04_buf(46) , + c => pp3_03_buf(46) , + sum => pp4_03(46) , + car => pp4_02(45) ); +pp4_01_csa_45: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(45) , + b => pp3_04_buf(45) , + c => pp3_03_buf(45) , + sum => pp4_03(45) , + car => pp4_02(44) ); +pp4_01_csa_44: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(44) , + b => pp3_04_buf(44) , + c => pp3_03_buf(44) , + sum => pp4_03(44) , + car => pp4_02(43) ); +pp4_01_csa_43: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(43) , + b => pp3_04_buf(43) , + c => pp3_03_buf(43) , + sum => pp4_03(43) , + car => pp4_02(42) ); +pp4_01_csa_42: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(42) , + b => pp3_04_buf(42) , + c => pp3_03_buf(42) , + sum => pp4_03(42) , + car => pp4_02(41) ); +pp4_01_csa_41: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(41) , + b => pp3_04_buf(41) , + c => pp3_03_buf(41) , + sum => pp4_03(41) , + car => pp4_02(40) ); +pp4_01_csa_40: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(40) , + b => pp3_04_buf(40) , + c => pp3_03_buf(40) , + sum => pp4_03(40) , + car => pp4_02(39) ); +pp4_01_csa_39: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(39) , + b => pp3_04_buf(39) , + c => pp3_03_buf(39) , + sum => pp4_03(39) , + car => pp4_02(38) ); +pp4_01_csa_38: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(38) , + b => pp3_04_buf(38) , + c => pp3_03_buf(38) , + sum => pp4_03(38) , + car => pp4_02(37) ); +pp4_01_csa_37: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(37) , + b => pp3_04_buf(37) , + c => pp3_03_buf(37) , + sum => pp4_03(37) , + car => pp4_02(36) ); +pp4_01_csa_36: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(36) , + b => pp3_04_buf(36) , + c => pp3_03_buf(36) , + sum => pp4_03(36) , + car => pp4_02(35) ); +pp4_01_csa_35: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp3_04_buf(35) , + b => pp3_03_buf(35) , + sum => pp4_03(35) , + car => pp4_02(34) ); + + pp4_03(18 to 34) <= pp3_03_buf(18 to 34) ; + + + + + + + pp4_01(73 to 90) <= pp3_02_buf(73 to 90) ; + pp4_00(74) <= hot_one_74_buf ; + pp4_00(73) <= tidn ; + pp4_00(72) <= tidn ; + +pp4_00_csa_72: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(72) , + b => pp3_01_buf(72) , + c => pp3_00_buf(72) , + sum => pp4_01(72) , + car => pp4_00(71) ); +pp4_00_csa_71: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(71) , + b => pp3_01_buf(71) , + c => pp3_00_buf(71) , + sum => pp4_01(71) , + car => pp4_00(70) ); +pp4_00_csa_70: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(70) , + b => pp3_01_buf(70) , + c => pp3_00_buf(70) , + sum => pp4_01(70) , + car => pp4_00(69) ); +pp4_00_csa_69: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(69) , + b => pp3_01_buf(69) , + c => pp3_00_buf(69) , + sum => pp4_01(69) , + car => pp4_00(68) ); +pp4_00_csa_68: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(68) , + b => pp3_01_buf(68) , + c => pp3_00_buf(68) , + sum => pp4_01(68) , + car => pp4_00(67) ); +pp4_00_csa_67: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(67) , + b => pp3_01_buf(67) , + c => pp3_00_buf(67) , + sum => pp4_01(67) , + car => pp4_00(66) ); +pp4_00_csa_66: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(66) , + b => pp3_01_buf(66) , + c => pp3_00_buf(66) , + sum => pp4_01(66) , + car => pp4_00(65) ); +pp4_00_csa_65: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(65) , + b => pp3_01_buf(65) , + c => pp3_00_buf(65) , + sum => pp4_01(65) , + car => pp4_00(64) ); +pp4_00_csa_64: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(64) , + b => pp3_01_buf(64) , + c => pp3_00_buf(64) , + sum => pp4_01(64) , + car => pp4_00(63) ); +pp4_00_csa_63: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(63) , + b => pp3_01_buf(63) , + c => pp3_00_buf(63) , + sum => pp4_01(63) , + car => pp4_00(62) ); +pp4_00_csa_62: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(62) , + b => pp3_01_buf(62) , + c => pp3_00_buf(62) , + sum => pp4_01(62) , + car => pp4_00(61) ); +pp4_00_csa_61: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(61) , + b => pp3_01_buf(61) , + c => pp3_00_buf(61) , + sum => pp4_01(61) , + car => pp4_00(60) ); +pp4_00_csa_60: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(60) , + b => pp3_01_buf(60) , + c => pp3_00_buf(60) , + sum => pp4_01(60) , + car => pp4_00(59) ); +pp4_00_csa_59: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(59) , + b => pp3_01_buf(59) , + c => pp3_00_buf(59) , + sum => pp4_01(59) , + car => pp4_00(58) ); +pp4_00_csa_58: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(58) , + b => pp3_01_buf(58) , + c => pp3_00_buf(58) , + sum => pp4_01(58) , + car => pp4_00(57) ); +pp4_00_csa_57: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(57) , + b => pp3_01_buf(57) , + c => pp3_00_buf(57) , + sum => pp4_01(57) , + car => pp4_00(56) ); +pp4_00_csa_56: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(56) , + b => pp3_01_buf(56) , + c => pp3_00_buf(56) , + sum => pp4_01(56) , + car => pp4_00(55) ); +pp4_00_csa_55: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(55) , + b => pp3_01_buf(55) , + c => pp3_00_buf(55) , + sum => pp4_01(55) , + car => pp4_00(54) ); +pp4_00_csa_54: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(54) , + b => pp3_01_buf(54) , + c => pp3_00_buf(54) , + sum => pp4_01(54) , + car => pp4_00(53) ); +pp4_00_csa_53: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(53) , + b => pp3_01_buf(53) , + c => pp3_00_buf(53) , + sum => pp4_01(53) , + car => pp4_00(52) ); +pp4_00_csa_52: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(52) , + b => pp3_01_buf(52) , + c => pp3_00_buf(52) , + sum => pp4_01(52) , + car => pp4_00(51) ); +pp4_00_csa_51: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(51) , + b => pp3_01_buf(51) , + c => pp3_00_buf(51) , + sum => pp4_01(51) , + car => pp4_00(50) ); +pp4_00_csa_50: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(50) , + b => pp3_01_buf(50) , + c => pp3_00_buf(50) , + sum => pp4_01(50) , + car => pp4_00(49) ); +pp4_00_csa_49: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(49) , + b => pp3_01_buf(49) , + c => pp3_00_buf(49) , + sum => pp4_01(49) , + car => pp4_00(48) ); +pp4_00_csa_48: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(48) , + b => pp3_01_buf(48) , + c => pp3_00_buf(48) , + sum => pp4_01(48) , + car => pp4_00(47) ); +pp4_00_csa_47: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(47) , + b => pp3_01_buf(47) , + c => pp3_00_buf(47) , + sum => pp4_01(47) , + car => pp4_00(46) ); +pp4_00_csa_46: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(46) , + b => pp3_01_buf(46) , + c => pp3_00_buf(46) , + sum => pp4_01(46) , + car => pp4_00(45) ); +pp4_00_csa_45: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(45) , + b => pp3_01_buf(45) , + c => pp3_00_buf(45) , + sum => pp4_01(45) , + car => pp4_00(44) ); +pp4_00_csa_44: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(44) , + b => pp3_01_buf(44) , + c => pp3_00_buf(44) , + sum => pp4_01(44) , + car => pp4_00(43) ); +pp4_00_csa_43: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(43) , + b => pp3_01_buf(43) , + c => pp3_00_buf(43) , + sum => pp4_01(43) , + car => pp4_00(42) ); +pp4_00_csa_42: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(42) , + b => pp3_01_buf(42) , + c => pp3_00_buf(42) , + sum => pp4_01(42) , + car => pp4_00(41) ); +pp4_00_csa_41: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(41) , + b => pp3_01_buf(41) , + c => pp3_00_buf(41) , + sum => pp4_01(41) , + car => pp4_00(40) ); +pp4_00_csa_40: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(40) , + b => pp3_01_buf(40) , + c => pp3_00_buf(40) , + sum => pp4_01(40) , + car => pp4_00(39) ); +pp4_00_csa_39: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(39) , + b => pp3_01_buf(39) , + c => pp3_00_buf(39) , + sum => pp4_01(39) , + car => pp4_00(38) ); +pp4_00_csa_38: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(38) , + b => pp3_01_buf(38) , + c => pp3_00_buf(38) , + sum => pp4_01(38) , + car => pp4_00(37) ); +pp4_00_csa_37: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(37) , + b => pp3_01_buf(37) , + c => pp3_00_buf(37) , + sum => pp4_01(37) , + car => pp4_00(36) ); +pp4_00_csa_36: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(36) , + b => pp3_01_buf(36) , + c => pp3_00_buf(36) , + sum => pp4_01(36) , + car => pp4_00(35) ); +pp4_00_csa_35: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(35) , + b => pp3_01_buf(35) , + c => pp3_00_buf(35) , + sum => pp4_01(35) , + car => pp4_00(34) ); +pp4_00_csa_34: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(34) , + b => pp3_01_buf(34) , + c => pp3_00_buf(34) , + sum => pp4_01(34) , + car => pp4_00(33) ); +pp4_00_csa_33: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(33) , + b => pp3_01_buf(33) , + c => pp3_00_buf(33) , + sum => pp4_01(33) , + car => pp4_00(32) ); +pp4_00_csa_32: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(32) , + b => pp3_01_buf(32) , + c => pp3_00_buf(32) , + sum => pp4_01(32) , + car => pp4_00(31) ); +pp4_00_csa_31: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(31) , + b => pp3_01_buf(31) , + c => pp3_00_buf(31) , + sum => pp4_01(31) , + car => pp4_00(30) ); +pp4_00_csa_30: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(30) , + b => pp3_01_buf(30) , + c => pp3_00_buf(30) , + sum => pp4_01(30) , + car => pp4_00(29) ); +pp4_00_csa_29: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(29) , + b => pp3_01_buf(29) , + c => pp3_00_buf(29) , + sum => pp4_01(29) , + car => pp4_00(28) ); +pp4_00_csa_28: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(28) , + b => pp3_01_buf(28) , + c => pp3_00_buf(28) , + sum => pp4_01(28) , + car => pp4_00(27) ); +pp4_00_csa_27: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(27) , + b => pp3_01_buf(27) , + c => pp3_00_buf(27) , + sum => pp4_01(27) , + car => pp4_00(26) ); +pp4_00_csa_26: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(26) , + b => pp3_01_buf(26) , + c => pp3_00_buf(26) , + sum => pp4_01(26) , + car => pp4_00(25) ); +pp4_00_csa_25: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(25) , + b => pp3_01_buf(25) , + c => pp3_00_buf(25) , + sum => pp4_01(25) , + car => pp4_00(24) ); +pp4_00_csa_24: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(24) , + b => pp3_01_buf(24) , + c => pp3_00_buf(24) , + sum => pp4_01(24) , + car => pp4_00(23) ); +pp4_00_csa_23: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(23) , + b => pp3_01_buf(23) , + c => pp3_00_buf(23) , + sum => pp4_01(23) , + car => pp4_00(22) ); +pp4_00_csa_22: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(22) , + b => pp3_01_buf(22) , + c => pp3_00_buf(22) , + sum => pp4_01(22) , + car => pp4_00(21) ); +pp4_00_csa_21: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(21) , + b => pp3_01_buf(21) , + c => pp3_00_buf(21) , + sum => pp4_01(21) , + car => pp4_00(20) ); +pp4_00_csa_20: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(20) , + b => pp3_01_buf(20) , + c => pp3_00_buf(20) , + sum => pp4_01(20) , + car => pp4_00(19) ); +pp4_00_csa_19: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(19) , + b => pp3_01_buf(19) , + c => pp3_00_buf(19) , + sum => pp4_01(19) , + car => pp4_00(18) ); +pp4_00_csa_18: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(18) , + b => pp3_01_buf(18) , + c => pp3_00_buf(18) , + sum => pp4_01(18) , + car => pp4_00(17) ); +pp4_00_csa_17: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(17) , + b => pp3_01_buf(17) , + c => pp3_00_buf(17) , + sum => pp4_01(17) , + car => pp4_00(16) ); +pp4_00_csa_16: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp3_01_buf(16) , + b => pp3_00_buf(16) , + sum => pp4_01(16) , + car => pp4_00(15) ); +pp4_00_csa_15: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp3_01_buf(15) , + b => pp3_00_buf(15) , + sum => pp4_01(15) , + car => pp4_00(14) ); +pp4_00_csa_14: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp3_01_buf(14) , + b => pp3_00_buf(14) , + sum => pp4_01(14) , + car => pp4_00(13) ); +pp4_00_csa_13: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp3_01_buf(13) , + b => pp3_00_buf(13) , + sum => pp4_01(13) , + car => pp4_00(12) ); +pp4_00_csa_12: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp3_01_buf(12) , + b => pp3_00_buf(12) , + sum => pp4_01(12) , + car => pp4_00(11) ); +pp4_00_csa_11: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp3_01_buf(11) , + b => pp3_00_buf(11) , + sum => pp4_01(11) , + car => pp4_00(10) ); +pp4_00_csa_10: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp3_01_buf(10) , + b => pp3_00_buf(10) , + sum => pp4_01(10) , + car => pp4_00(9) ); +pp4_00_csa_09: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp3_01_buf(9) , + b => pp3_00_buf(9) , + sum => pp4_01(9) , + car => pp4_00(8) ); +pp4_00_csa_08: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp3_01_buf(8) , + b => pp3_00_buf(8) , + sum => pp4_01(8) , + car => pp4_00(7) ); +pp4_00_csa_07: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp3_01_buf(7) , + b => pp3_00_buf(7) , + sum => pp4_01(7) , + car => pp4_00(6) ); +pp4_00_csa_06: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp3_01_buf(6) , + b => pp3_00_buf(6) , + sum => pp4_01(6) , + car => pp4_00(5) ); +pp4_00_csa_05: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp3_01_buf(5) , + b => pp3_00_buf(5) , + sum => pp4_01(5) , + car => pp4_00(4) ); +pp4_00_csa_04: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp3_01_buf(4) , + b => pp3_00_buf(4) , + sum => pp4_01(4) , + car => pp4_00(3) ); +pp4_00_csa_03: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp3_01_buf(3) , + b => pp3_00_buf(3) , + sum => pp4_01(3) , + car => pp4_00(2) ); +pp4_00_csa_02: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp3_01_buf(2) , + b => pp3_00_buf(2) , + sum => pp4_01(2) , + car => pp4_00(1) ); +pp4_00_csa_01: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp3_01_buf(1) , + b => pp3_00_buf(1) , + sum => pp4_01(1) , + car => pp4_00(0) ); + + + + + + + + pp5_01(91 to 108) <= pp4_03(91 to 108) ; + pp5_00(93 to 108) <= pp4_02(93 to 108) ; + pp5_00(92) <= tidn ; + pp5_00(91) <= pp4_02(91); + pp5_00(90) <= tidn; + +pp5_00_csa_90: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp4_03(90) , + b => pp4_02(90) , + c => pp4_01(90) , + sum => pp5_01(90) , + car => pp5_00(89) ); +pp5_00_csa_89: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp4_03(89) , + b => pp4_02(89) , + c => pp4_01(89) , + sum => pp5_01(89) , + car => pp5_00(88) ); +pp5_00_csa_88: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp4_03(88) , + b => pp4_02(88) , + c => pp4_01(88) , + sum => pp5_01(88) , + car => pp5_00(87) ); +pp5_00_csa_87: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp4_03(87) , + b => pp4_02(87) , + c => pp4_01(87) , + sum => pp5_01(87) , + car => pp5_00(86) ); +pp5_00_csa_86: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp4_03(86) , + b => pp4_02(86) , + c => pp4_01(86) , + sum => pp5_01(86) , + car => pp5_00(85) ); +pp5_00_csa_85: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp4_03(85) , + b => pp4_02(85) , + c => pp4_01(85) , + sum => pp5_01(85) , + car => pp5_00(84) ); +pp5_00_csa_84: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp4_03(84) , + b => pp4_02(84) , + c => pp4_01(84) , + sum => pp5_01(84) , + car => pp5_00(83) ); +pp5_00_csa_83: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp4_03(83) , + b => pp4_02(83) , + c => pp4_01(83) , + sum => pp5_01(83) , + car => pp5_00(82) ); +pp5_00_csa_82: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp4_03(82) , + b => pp4_02(82) , + c => pp4_01(82) , + sum => pp5_01(82) , + car => pp5_00(81) ); +pp5_00_csa_81: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp4_03(81) , + b => pp4_02(81) , + c => pp4_01(81) , + sum => pp5_01(81) , + car => pp5_00(80) ); +pp5_00_csa_80: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp4_03(80) , + b => pp4_02(80) , + c => pp4_01(80) , + sum => pp5_01(80) , + car => pp5_00(79) ); +pp5_00_csa_79: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp4_03(79) , + b => pp4_02(79) , + c => pp4_01(79) , + sum => pp5_01(79) , + car => pp5_00(78) ); +pp5_00_csa_78: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp4_03(78) , + b => pp4_02(78) , + c => pp4_01(78) , + sum => pp5_01(78) , + car => pp5_00(77) ); +pp5_00_csa_77: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp4_03(77) , + b => pp4_02(77) , + c => pp4_01(77) , + sum => pp5_01(77) , + car => pp5_00(76) ); +pp5_00_csa_76: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp4_03(76) , + b => pp4_02(76) , + c => pp4_01(76) , + sum => pp5_01(76) , + car => pp5_00(75) ); +pp5_00_csa_75: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp4_03(75) , + b => pp4_02(75) , + c => pp4_01(75) , + sum => pp5_01(75) , + car => pp5_00(74) ); +pp5_00_csa_74: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(74) , + b => pp4_02(74) , + c => pp4_01(74) , + d => pp4_00(74) , + ki => tidn , + ko => pp5_00_ko(73) , + sum => pp5_01(74) , + car => pp5_00(73) ); +pp5_00_csa_73: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(73) , + b => pp4_02(73) , + c => pp4_01(73) , + d => tidn , + ki => pp5_00_ko(73) , + ko => pp5_00_ko(72) , + sum => pp5_01(73) , + car => pp5_00(72) ); +pp5_00_csa_72: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(72) , + b => pp4_02(72) , + c => pp4_01(72) , + d => tidn , + ki => pp5_00_ko(72) , + ko => pp5_00_ko(71) , + sum => pp5_01(72) , + car => pp5_00(71) ); +pp5_00_csa_71: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(71) , + b => pp4_02(71) , + c => pp4_01(71) , + d => pp4_00(71) , + ki => pp5_00_ko(71) , + ko => pp5_00_ko(70) , + sum => pp5_01(71) , + car => pp5_00(70) ); +pp5_00_csa_70: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(70) , + b => pp4_02(70) , + c => pp4_01(70) , + d => pp4_00(70) , + ki => pp5_00_ko(70) , + ko => pp5_00_ko(69) , + sum => pp5_01(70) , + car => pp5_00(69) ); +pp5_00_csa_69: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(69) , + b => pp4_02(69) , + c => pp4_01(69) , + d => pp4_00(69) , + ki => pp5_00_ko(69) , + ko => pp5_00_ko(68) , + sum => pp5_01(69) , + car => pp5_00(68) ); +pp5_00_csa_68: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(68) , + b => pp4_02(68) , + c => pp4_01(68) , + d => pp4_00(68) , + ki => pp5_00_ko(68) , + ko => pp5_00_ko(67) , + sum => pp5_01(68) , + car => pp5_00(67) ); +pp5_00_csa_67: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(67) , + b => pp4_02(67) , + c => pp4_01(67) , + d => pp4_00(67) , + ki => pp5_00_ko(67) , + ko => pp5_00_ko(66) , + sum => pp5_01(67) , + car => pp5_00(66) ); +pp5_00_csa_66: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(66) , + b => pp4_02(66) , + c => pp4_01(66) , + d => pp4_00(66) , + ki => pp5_00_ko(66) , + ko => pp5_00_ko(65) , + sum => pp5_01(66) , + car => pp5_00(65) ); +pp5_00_csa_65: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(65) , + b => pp4_02(65) , + c => pp4_01(65) , + d => pp4_00(65) , + ki => pp5_00_ko(65) , + ko => pp5_00_ko(64) , + sum => pp5_01(65) , + car => pp5_00(64) ); +pp5_00_csa_64: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(64) , + b => pp4_02(64) , + c => pp4_01(64) , + d => pp4_00(64) , + ki => pp5_00_ko(64) , + ko => pp5_00_ko(63) , + sum => pp5_01(64) , + car => pp5_00(63) ); +pp5_00_csa_63: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(63) , + b => pp4_02(63) , + c => pp4_01(63) , + d => pp4_00(63) , + ki => pp5_00_ko(63) , + ko => pp5_00_ko(62) , + sum => pp5_01(63) , + car => pp5_00(62) ); +pp5_00_csa_62: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(62) , + b => pp4_02(62) , + c => pp4_01(62) , + d => pp4_00(62) , + ki => pp5_00_ko(62) , + ko => pp5_00_ko(61) , + sum => pp5_01(62) , + car => pp5_00(61) ); +pp5_00_csa_61: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(61) , + b => pp4_02(61) , + c => pp4_01(61) , + d => pp4_00(61) , + ki => pp5_00_ko(61) , + ko => pp5_00_ko(60) , + sum => pp5_01(61) , + car => pp5_00(60) ); +pp5_00_csa_60: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(60) , + b => pp4_02(60) , + c => pp4_01(60) , + d => pp4_00(60) , + ki => pp5_00_ko(60) , + ko => pp5_00_ko(59) , + sum => pp5_01(60) , + car => pp5_00(59) ); +pp5_00_csa_59: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(59) , + b => pp4_02(59) , + c => pp4_01(59) , + d => pp4_00(59) , + ki => pp5_00_ko(59) , + ko => pp5_00_ko(58) , + sum => pp5_01(59) , + car => pp5_00(58) ); +pp5_00_csa_58: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(58) , + b => pp4_02(58) , + c => pp4_01(58) , + d => pp4_00(58) , + ki => pp5_00_ko(58) , + ko => pp5_00_ko(57) , + sum => pp5_01(58) , + car => pp5_00(57) ); +pp5_00_csa_57: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(57) , + b => pp4_02(57) , + c => pp4_01(57) , + d => pp4_00(57) , + ki => pp5_00_ko(57) , + ko => pp5_00_ko(56) , + sum => pp5_01(57) , + car => pp5_00(56) ); +pp5_00_csa_56: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(56) , + b => pp4_02(56) , + c => pp4_01(56) , + d => pp4_00(56) , + ki => pp5_00_ko(56) , + ko => pp5_00_ko(55) , + sum => pp5_01(56) , + car => pp5_00(55) ); +pp5_00_csa_55: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(55) , + b => pp4_02(55) , + c => pp4_01(55) , + d => pp4_00(55) , + ki => pp5_00_ko(55) , + ko => pp5_00_ko(54) , + sum => pp5_01(55) , + car => pp5_00(54) ); +pp5_00_csa_54: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(54) , + b => pp4_02(54) , + c => pp4_01(54) , + d => pp4_00(54) , + ki => pp5_00_ko(54) , + ko => pp5_00_ko(53) , + sum => pp5_01(54) , + car => pp5_00(53) ); +pp5_00_csa_53: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(53) , + b => pp4_02(53) , + c => pp4_01(53) , + d => pp4_00(53) , + ki => pp5_00_ko(53) , + ko => pp5_00_ko(52) , + sum => pp5_01(53) , + car => pp5_00(52) ); +pp5_00_csa_52: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(52) , + b => pp4_02(52) , + c => pp4_01(52) , + d => pp4_00(52) , + ki => pp5_00_ko(52) , + ko => pp5_00_ko(51) , + sum => pp5_01(52) , + car => pp5_00(51) ); +pp5_00_csa_51: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(51) , + b => pp4_02(51) , + c => pp4_01(51) , + d => pp4_00(51) , + ki => pp5_00_ko(51) , + ko => pp5_00_ko(50) , + sum => pp5_01(51) , + car => pp5_00(50) ); +pp5_00_csa_50: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(50) , + b => pp4_02(50) , + c => pp4_01(50) , + d => pp4_00(50) , + ki => pp5_00_ko(50) , + ko => pp5_00_ko(49) , + sum => pp5_01(50) , + car => pp5_00(49) ); +pp5_00_csa_49: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(49) , + b => pp4_02(49) , + c => pp4_01(49) , + d => pp4_00(49) , + ki => pp5_00_ko(49) , + ko => pp5_00_ko(48) , + sum => pp5_01(49) , + car => pp5_00(48) ); +pp5_00_csa_48: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(48) , + b => pp4_02(48) , + c => pp4_01(48) , + d => pp4_00(48) , + ki => pp5_00_ko(48) , + ko => pp5_00_ko(47) , + sum => pp5_01(48) , + car => pp5_00(47) ); +pp5_00_csa_47: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(47) , + b => pp4_02(47) , + c => pp4_01(47) , + d => pp4_00(47) , + ki => pp5_00_ko(47) , + ko => pp5_00_ko(46) , + sum => pp5_01(47) , + car => pp5_00(46) ); +pp5_00_csa_46: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(46) , + b => pp4_02(46) , + c => pp4_01(46) , + d => pp4_00(46) , + ki => pp5_00_ko(46) , + ko => pp5_00_ko(45) , + sum => pp5_01(46) , + car => pp5_00(45) ); +pp5_00_csa_45: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(45) , + b => pp4_02(45) , + c => pp4_01(45) , + d => pp4_00(45) , + ki => pp5_00_ko(45) , + ko => pp5_00_ko(44) , + sum => pp5_01(45) , + car => pp5_00(44) ); +pp5_00_csa_44: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(44) , + b => pp4_02(44) , + c => pp4_01(44) , + d => pp4_00(44) , + ki => pp5_00_ko(44) , + ko => pp5_00_ko(43) , + sum => pp5_01(44) , + car => pp5_00(43) ); +pp5_00_csa_43: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(43) , + b => pp4_02(43) , + c => pp4_01(43) , + d => pp4_00(43) , + ki => pp5_00_ko(43) , + ko => pp5_00_ko(42) , + sum => pp5_01(43) , + car => pp5_00(42) ); +pp5_00_csa_42: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(42) , + b => pp4_02(42) , + c => pp4_01(42) , + d => pp4_00(42) , + ki => pp5_00_ko(42) , + ko => pp5_00_ko(41) , + sum => pp5_01(42) , + car => pp5_00(41) ); +pp5_00_csa_41: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(41) , + b => pp4_02(41) , + c => pp4_01(41) , + d => pp4_00(41) , + ki => pp5_00_ko(41) , + ko => pp5_00_ko(40) , + sum => pp5_01(41) , + car => pp5_00(40) ); +pp5_00_csa_40: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(40) , + b => pp4_02(40) , + c => pp4_01(40) , + d => pp4_00(40) , + ki => pp5_00_ko(40) , + ko => pp5_00_ko(39) , + sum => pp5_01(40) , + car => pp5_00(39) ); +pp5_00_csa_39: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(39) , + b => pp4_02(39) , + c => pp4_01(39) , + d => pp4_00(39) , + ki => pp5_00_ko(39) , + ko => pp5_00_ko(38) , + sum => pp5_01(39) , + car => pp5_00(38) ); +pp5_00_csa_38: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(38) , + b => pp4_02(38) , + c => pp4_01(38) , + d => pp4_00(38) , + ki => pp5_00_ko(38) , + ko => pp5_00_ko(37) , + sum => pp5_01(38) , + car => pp5_00(37) ); +pp5_00_csa_37: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(37) , + b => pp4_02(37) , + c => pp4_01(37) , + d => pp4_00(37) , + ki => pp5_00_ko(37) , + ko => pp5_00_ko(36) , + sum => pp5_01(37) , + car => pp5_00(36) ); +pp5_00_csa_36: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(36) , + b => pp4_02(36) , + c => pp4_01(36) , + d => pp4_00(36) , + ki => pp5_00_ko(36) , + ko => pp5_00_ko(35) , + sum => pp5_01(36) , + car => pp5_00(35) ); +pp5_00_csa_35: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(35) , + b => pp4_02(35) , + c => pp4_01(35) , + d => pp4_00(35) , + ki => pp5_00_ko(35) , + ko => pp5_00_ko(34) , + sum => pp5_01(35) , + car => pp5_00(34) ); +pp5_00_csa_34: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(34) , + b => pp4_02(34) , + c => pp4_01(34) , + d => pp4_00(34) , + ki => pp5_00_ko(34) , + ko => pp5_00_ko(33) , + sum => pp5_01(34) , + car => pp5_00(33) ); +pp5_00_csa_33: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(33) , + b => pp4_01(33) , + c => pp4_00(33) , + d => tidn , + ki => pp5_00_ko(33) , + ko => pp5_00_ko(32) , + sum => pp5_01(33) , + car => pp5_00(32) ); +pp5_00_csa_32: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(32) , + b => pp4_01(32) , + c => pp4_00(32) , + d => tidn , + ki => pp5_00_ko(32) , + ko => pp5_00_ko(31) , + sum => pp5_01(32) , + car => pp5_00(31) ); +pp5_00_csa_31: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(31) , + b => pp4_01(31) , + c => pp4_00(31) , + d => tidn , + ki => pp5_00_ko(31) , + ko => pp5_00_ko(30) , + sum => pp5_01(31) , + car => pp5_00(30) ); +pp5_00_csa_30: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(30) , + b => pp4_01(30) , + c => pp4_00(30) , + d => tidn , + ki => pp5_00_ko(30) , + ko => pp5_00_ko(29) , + sum => pp5_01(30) , + car => pp5_00(29) ); +pp5_00_csa_29: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(29) , + b => pp4_01(29) , + c => pp4_00(29) , + d => tidn , + ki => pp5_00_ko(29) , + ko => pp5_00_ko(28) , + sum => pp5_01(29) , + car => pp5_00(28) ); +pp5_00_csa_28: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(28) , + b => pp4_01(28) , + c => pp4_00(28) , + d => tidn , + ki => pp5_00_ko(28) , + ko => pp5_00_ko(27) , + sum => pp5_01(28) , + car => pp5_00(27) ); +pp5_00_csa_27: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(27) , + b => pp4_01(27) , + c => pp4_00(27) , + d => tidn , + ki => pp5_00_ko(27) , + ko => pp5_00_ko(26) , + sum => pp5_01(27) , + car => pp5_00(26) ); +pp5_00_csa_26: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(26) , + b => pp4_01(26) , + c => pp4_00(26) , + d => tidn , + ki => pp5_00_ko(26) , + ko => pp5_00_ko(25) , + sum => pp5_01(26) , + car => pp5_00(25) ); +pp5_00_csa_25: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(25) , + b => pp4_01(25) , + c => pp4_00(25) , + d => tidn , + ki => pp5_00_ko(25) , + ko => pp5_00_ko(24) , + sum => pp5_01(25) , + car => pp5_00(24) ); +pp5_00_csa_24: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(24) , + b => pp4_01(24) , + c => pp4_00(24) , + d => tidn , + ki => pp5_00_ko(24) , + ko => pp5_00_ko(23) , + sum => pp5_01(24) , + car => pp5_00(23) ); +pp5_00_csa_23: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(23) , + b => pp4_01(23) , + c => pp4_00(23) , + d => tidn , + ki => pp5_00_ko(23) , + ko => pp5_00_ko(22) , + sum => pp5_01(23) , + car => pp5_00(22) ); +pp5_00_csa_22: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(22) , + b => pp4_01(22) , + c => pp4_00(22) , + d => tidn , + ki => pp5_00_ko(22) , + ko => pp5_00_ko(21) , + sum => pp5_01(22) , + car => pp5_00(21) ); +pp5_00_csa_21: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(21) , + b => pp4_01(21) , + c => pp4_00(21) , + d => tidn , + ki => pp5_00_ko(21) , + ko => pp5_00_ko(20) , + sum => pp5_01(21) , + car => pp5_00(20) ); +pp5_00_csa_20: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(20) , + b => pp4_01(20) , + c => pp4_00(20) , + d => tidn , + ki => pp5_00_ko(20) , + ko => pp5_00_ko(19) , + sum => pp5_01(20) , + car => pp5_00(19) ); +pp5_00_csa_19: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(19) , + b => pp4_01(19) , + c => pp4_00(19) , + d => tidn , + ki => pp5_00_ko(19) , + ko => pp5_00_ko(18) , + sum => pp5_01(19) , + car => pp5_00(18) ); +pp5_00_csa_18: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(18) , + b => pp4_01(18) , + c => pp4_00(18) , + d => tidn , + ki => pp5_00_ko(18) , + ko => pp5_00_ko(17) , + sum => pp5_01(18) , + car => pp5_00(17) ); +pp5_00_csa_17: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp4_01(17) , + b => pp4_00(17) , + c => pp5_00_ko(17) , + sum => pp5_01(17) , + car => pp5_00(16) ); +pp5_00_csa_16: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp4_01(16) , + b => pp4_00(16) , + sum => pp5_01(16) , + car => pp5_00(15) ); +pp5_00_csa_15: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp4_01(15) , + b => pp4_00(15) , + sum => pp5_01(15) , + car => pp5_00(14) ); +pp5_00_csa_14: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp4_01(14) , + b => pp4_00(14) , + sum => pp5_01(14) , + car => pp5_00(13) ); +pp5_00_csa_13: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp4_01(13) , + b => pp4_00(13) , + sum => pp5_01(13) , + car => pp5_00(12) ); +pp5_00_csa_12: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp4_01(12) , + b => pp4_00(12) , + sum => pp5_01(12) , + car => pp5_00(11) ); +pp5_00_csa_11: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp4_01(11) , + b => pp4_00(11) , + sum => pp5_01(11) , + car => pp5_00(10) ); +pp5_00_csa_10: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp4_01(10) , + b => pp4_00(10) , + sum => pp5_01(10) , + car => pp5_00(9) ); +pp5_00_csa_09: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp4_01(9) , + b => pp4_00(9) , + sum => pp5_01(9) , + car => pp5_00(8) ); +pp5_00_csa_08: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp4_01(8) , + b => pp4_00(8) , + sum => pp5_01(8) , + car => pp5_00(7) ); +pp5_00_csa_07: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp4_01(7) , + b => pp4_00(7) , + sum => pp5_01(7) , + car => pp5_00(6) ); +pp5_00_csa_06: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp4_01(6) , + b => pp4_00(6) , + sum => pp5_01(6) , + car => pp5_00(5) ); +pp5_00_csa_05: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp4_01(5) , + b => pp4_00(5) , + sum => pp5_01(5) , + car => pp5_00(4) ); +pp5_00_csa_04: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp4_01(4) , + b => pp4_00(4) , + sum => pp5_01(4) , + car => pp5_00(3) ); +pp5_00_csa_03: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp4_01(3) , + b => pp4_00(3) , + sum => pp5_01(3) , + car => pp5_00(2) ); +pp5_00_csa_02: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp4_01(2) , + b => pp4_00(2) , + sum => pp5_01(2) , + car => pp5_00(1) ); +pp5_00_csa_01: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp4_01(1) , + b => pp4_00(1) , + sum => pp5_01(1) , + car => pp5_00(0) ); + + + + sum62(1 to 108) <= pp5_01(1 to 108); + car62(1 to 108) <= pp5_00(1 to 108); + + +end; + + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_mul_92.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_mul_92.vhdl new file mode 100644 index 0000000..ce676eb --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_mul_92.vhdl @@ -0,0 +1,3516 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; +library clib ; + + +entity fuq_mul_92 is + generic(expand_type : integer := 2; + inst : natural := 0 ); + port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + si : in std_ulogic; + so : out std_ulogic; + ex1_act : in std_ulogic; + lcb_delay_lclkr : in std_ulogic; + lcb_mpw1_b : in std_ulogic; + lcb_mpw2_b : in std_ulogic; + thold_b : in std_ulogic; + forcee : in std_ulogic; + lcb_sg : in std_ulogic; + c_frac : in std_ulogic_vector(0 to 53); + a_frac : in std_ulogic_vector(17 to 35); + hot_one_out : out std_ulogic; + sum92 : out std_ulogic_vector(2 to 74); + car92 : out std_ulogic_vector(1 to 74) + ); + +-- synopsys translate_off + + + + + + + +-- synopsys translate_on +end fuq_mul_92; + +architecture fuq_mul_92 of fuq_mul_92 is + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal s_neg : std_ulogic_vector(0 to 8); + signal s_x : std_ulogic_vector(0 to 8); + signal s_x2 : std_ulogic_vector(0 to 8); + signal xtd_2_add : std_ulogic_vector(0 to 7); + signal hot_one_din, hot_one_out_b : std_ulogic; + + signal pp0_00 : std_ulogic_vector(2 to 60); + signal pp0_01 : std_ulogic_vector(4 to 62); + signal pp0_02 : std_ulogic_vector(6 to 64); + signal pp0_03 : std_ulogic_vector(8 to 66); + signal pp0_04 : std_ulogic_vector(10 to 68); + signal pp0_05 : std_ulogic_vector(12 to 70); + signal pp0_06 : std_ulogic_vector(14 to 72); + signal pp0_07 : std_ulogic_vector(16 to 74); + signal pp0_08 : std_ulogic_vector(17 to 74); + signal pp1_05 : std_ulogic_vector(14 to 74); + signal pp1_04 : std_ulogic_vector(15 to 74); + signal pp1_03 : std_ulogic_vector(8 to 70); + signal pp1_02 : std_ulogic_vector(9 to 68); + signal pp1_01 : std_ulogic_vector(2 to 64); + signal pp1_00 : std_ulogic_vector(3 to 62); + signal pp2_03 : std_ulogic_vector(8 to 74); + signal pp2_02 : std_ulogic_vector(13 to 74); + signal pp2_01 : std_ulogic_vector(2 to 68); + signal pp2_00 : std_ulogic_vector(2 to 64); + signal pp3_01 : std_ulogic_vector(2 to 74); + signal pp3_00 : std_ulogic_vector(1 to 74); + signal pp3_00_ko : std_ulogic_vector(7 to 63); + signal pp3_01_q_b : std_ulogic_vector(2 to 74); + signal pp3_00_q_b : std_ulogic_vector(1 to 74); + + signal pp3_lat_sum_so :std_ulogic_vector(0 to 72); + signal pp3_lat_car_so :std_ulogic_vector(0 to 70); + signal mul92_d1clk, mul92_d2clk :std_ulogic ; + signal mul92_lclk :clk_logic ; + + signal unused :std_ulogic ; + + + + + + + + + + + + +begin + +unused <= + pp0_00(2) or + pp0_00(3) or + pp0_00(59) or + pp0_01(4) or pp0_01(61) or + pp0_02(63) or pp0_02(6) or + pp0_03(65) or pp0_03(8) or + pp0_04(10) or pp0_04(67) or + pp0_05(12) or pp0_05(69) or + pp0_06(14) or pp0_06(71) or + pp0_07(16) or pp0_07(73) or + pp1_00(60) or pp1_00(61) or + pp1_01(63) or + pp1_02(66) or pp1_02(67) or + pp1_03(69) or pp1_03(8) or + pp1_04(72) or pp1_04(73) or + pp1_05(14) or + pp2_00(62) or pp2_00(63) or + pp2_01(66) or pp2_01(67) or + pp2_02(70) or pp2_02(72) or pp2_02(73) or + pp2_03(8) or + pp3_00(68) or pp3_00(70) or pp3_00(72) or pp3_00(73) ; + + + bd_00: entity work.fuq_mul_bthdcd(fuq_mul_bthdcd) port map ( + i0 => a_frac(17) , + i1 => a_frac(18) , + i2 => a_frac(19) , + s_neg => s_neg(0) , + s_x => s_x(0) , + s_x2 => s_x2(0)); + + bd_01: entity work.fuq_mul_bthdcd(fuq_mul_bthdcd) port map ( + i0 => a_frac(19) , + i1 => a_frac(20) , + i2 => a_frac(21) , + s_neg => s_neg(1) , + s_x => s_x(1) , + s_x2 => s_x2(1)); + + bd_02: entity work.fuq_mul_bthdcd(fuq_mul_bthdcd) port map ( + i0 => a_frac(21) , + i1 => a_frac(22) , + i2 => a_frac(23) , + s_neg => s_neg(2) , + s_x => s_x(2) , + s_x2 => s_x2(2)); + + bd_03: entity work.fuq_mul_bthdcd(fuq_mul_bthdcd) port map ( + i0 => a_frac(23) , + i1 => a_frac(24) , + i2 => a_frac(25) , + s_neg => s_neg(3) , + s_x => s_x(3) , + s_x2 => s_x2(3)); + + bd_04: entity work.fuq_mul_bthdcd(fuq_mul_bthdcd) port map ( + i0 => a_frac(25) , + i1 => a_frac(26) , + i2 => a_frac(27) , + s_neg => s_neg(4) , + s_x => s_x(4) , + s_x2 => s_x2(4)); + + bd_05: entity work.fuq_mul_bthdcd(fuq_mul_bthdcd) port map ( + i0 => a_frac(27) , + i1 => a_frac(28) , + i2 => a_frac(29) , + s_neg => s_neg(5) , + s_x => s_x(5) , + s_x2 => s_x2(5)); + + bd_06: entity work.fuq_mul_bthdcd(fuq_mul_bthdcd) port map ( + i0 => a_frac(29) , + i1 => a_frac(30) , + i2 => a_frac(31) , + s_neg => s_neg(6) , + s_x => s_x(6) , + s_x2 => s_x2(6)); + + bd_07: entity work.fuq_mul_bthdcd(fuq_mul_bthdcd) port map ( + i0 => a_frac(31) , + i1 => a_frac(32) , + i2 => a_frac(33) , + s_neg => s_neg(7) , + s_x => s_x(7) , + s_x2 => s_x2(7)); + + bd_08: entity work.fuq_mul_bthdcd(fuq_mul_bthdcd) port map ( + i0 => a_frac(33) , + i1 => a_frac(34) , + i2 => a_frac(35) , + s_neg => s_neg(8) , + s_x => s_x(8) , + s_x2 => s_x2(8)); + + + + + + + + pp0_00(2) <= tiup; + pp0_00(3) <= xtd_2_add(0); + + sx_00_2: xtd_2_add(0) <= not(s_neg(0) and (s_x(0) or s_x2(0)) ); + + bm_00: entity work.fuq_mul_bthrow(fuq_mul_bthrow) port map ( + s_neg => s_neg(0) , + s_x => s_x(0) , + s_x2 => s_x2(0) , + x => c_frac(0 to 53) , + q => pp0_00(4 to 58) , + hot_one => hot_one_din); + + + pp0_01(4) <= tiup; + pp0_01(5) <= xtd_2_add(1); + + sx_01_2: xtd_2_add(1) <= not(s_neg(1) and (s_x(1) or s_x2(1)) ); + + bm_01: entity work.fuq_mul_bthrow(fuq_mul_bthrow) port map ( + s_neg => s_neg(1) , + s_x => s_x(1) , + s_x2 => s_x2(1) , + x => c_frac(0 to 53) , + q => pp0_01(6 to 60) , + hot_one => pp0_00(60)); + pp0_00(59) <= tidn; + + + pp0_02(6) <= tiup; + pp0_02(7) <= xtd_2_add(2); + + sx_02_2: xtd_2_add(2) <= not(s_neg(2) and (s_x(2) or s_x2(2)) ); + + bm_02: entity work.fuq_mul_bthrow(fuq_mul_bthrow) port map ( + s_neg => s_neg(2) , + s_x => s_x(2) , + s_x2 => s_x2(2) , + x => c_frac(0 to 53) , + q => pp0_02(8 to 62) , + hot_one => pp0_01(62)); + pp0_01(61) <= tidn; + + + pp0_03(8) <= tiup; + pp0_03(9) <= xtd_2_add(3); + + sx_03_2: xtd_2_add(3) <= not(s_neg(3) and (s_x(3) or s_x2(3)) ); + + bm_03: entity work.fuq_mul_bthrow(fuq_mul_bthrow) port map ( + s_neg => s_neg(3) , + s_x => s_x(3) , + s_x2 => s_x2(3) , + x => c_frac(0 to 53) , + q => pp0_03(10 to 64) , + hot_one => pp0_02(64)); + pp0_02(63) <= tidn; + + + pp0_04(10) <= tiup; + pp0_04(11) <= xtd_2_add(4); + + sx_04_2: xtd_2_add(4) <= not(s_neg(4) and (s_x(4) or s_x2(4)) ); + + bm_04: entity work.fuq_mul_bthrow(fuq_mul_bthrow) port map ( + s_neg => s_neg(4) , + s_x => s_x(4) , + s_x2 => s_x2(4) , + x => c_frac(0 to 53) , + q => pp0_04(12 to 66) , + hot_one => pp0_03(66)); + pp0_03(65) <= tidn; + + + pp0_05(12) <= tiup; + pp0_05(13) <= xtd_2_add(5); + + sx_05_2: xtd_2_add(5) <= not(s_neg(5) and (s_x(5) or s_x2(5)) ); + + bm_05: entity work.fuq_mul_bthrow(fuq_mul_bthrow) port map ( + s_neg => s_neg(5) , + s_x => s_x(5) , + s_x2 => s_x2(5) , + x => c_frac(0 to 53) , + q => pp0_05(14 to 68) , + hot_one => pp0_04(68)); + pp0_04(67) <= tidn; + + + pp0_06(14) <= tiup; + pp0_06(15) <= xtd_2_add(6); + + sx_06_2: xtd_2_add(6) <= not(s_neg(6) and (s_x(6) or s_x2(6)) ); + + bm_06: entity work.fuq_mul_bthrow(fuq_mul_bthrow) port map ( + s_neg => s_neg(6) , + s_x => s_x(6) , + s_x2 => s_x2(6) , + x => c_frac(0 to 53) , + q => pp0_06(16 to 70) , + hot_one => pp0_05(70)); + pp0_05(69) <= tidn; + + + pp0_07(16) <= tiup; + pp0_07(17) <= xtd_2_add(7); + + sx_07_2: xtd_2_add(7) <= not(s_neg(7) and (s_x(7) or s_x2(7)) ); + + bm_07: entity work.fuq_mul_bthrow(fuq_mul_bthrow) port map ( + s_neg => s_neg(7) , + s_x => s_x(7) , + s_x2 => s_x2(7) , + x => c_frac(0 to 53) , + q => pp0_07(18 to 72) , + hot_one => pp0_06(72)); + pp0_06(71) <= tidn; + + + + + + + + + g0: if (inst = 0) generate + begin + pp0_08(17) <= tidn ; + pp0_08(18) <= tiup ; + sx_08_2: pp0_08(19) <= not( s_neg(8) and ( s_x(8) or s_x2(8)) ); + end generate ; + + g1: if (inst = 1) generate + begin + pp0_08(17) <= tidn ; + pp0_08(18) <= tiup ; + sx_08_2: pp0_08(19) <= not( s_neg(8) and ( s_x(8) or s_x2(8)) ); + end generate ; + + + g2: if (inst = 2) generate + begin + sx_08_0: pp0_08(17) <= not( s_neg(8) and ( s_x(8) or s_x2(8)) ); + sx_08_1: pp0_08(18) <= ( s_neg(8) and ( s_x(8) or s_x2(8)) ); + sx_08_2: pp0_08(19) <= ( s_neg(8) and ( s_x(8) or s_x2(8)) ); + end generate ; + + + + bm_08: entity work.fuq_mul_bthrow(fuq_mul_bthrow) port map ( + s_neg => s_neg(8) , + s_x => s_x(8) , + s_x2 => s_x2(8) , + x => c_frac(0 to 53) , + q => pp0_08(20 to 74) , + hot_one => pp0_07(74)); + pp0_07(73) <= tidn; + + + + + + + + + + + + pp1_05(74) <= pp0_08(74); + pp1_05(73) <= pp0_08(73); + + pp1_04(74) <= pp0_07(74); + pp1_04(73) <= tidn; + pp1_04(72) <= tidn; + + pp1_02_csa_72: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(72) , + b => pp0_07(72) , + c => pp0_06(72) , + sum => pp1_05(72) , + car => pp1_04(71)); + pp1_02_csa_71: entity work.fuq_csa22_h2(fuq_csa22_h2) port map ( + a => pp0_08(71) , + b => pp0_07(71) , + sum => pp1_05(71) , + car => pp1_04(70)); + pp1_02_csa_70: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(70) , + b => pp0_07(70) , + c => pp0_06(70) , + sum => pp1_05(70) , + car => pp1_04(69)); + pp1_02_csa_69: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(69) , + b => pp0_07(69) , + c => pp0_06(69) , + sum => pp1_05(69) , + car => pp1_04(68)); + pp1_02_csa_68: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(68) , + b => pp0_07(68) , + c => pp0_06(68) , + sum => pp1_05(68) , + car => pp1_04(67)); + pp1_02_csa_67: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(67) , + b => pp0_07(67) , + c => pp0_06(67) , + sum => pp1_05(67) , + car => pp1_04(66)); + pp1_02_csa_66: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(66) , + b => pp0_07(66) , + c => pp0_06(66) , + sum => pp1_05(66) , + car => pp1_04(65)); + pp1_02_csa_65: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(65) , + b => pp0_07(65) , + c => pp0_06(65) , + sum => pp1_05(65) , + car => pp1_04(64)); + pp1_02_csa_64: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(64) , + b => pp0_07(64) , + c => pp0_06(64) , + sum => pp1_05(64) , + car => pp1_04(63)); + pp1_02_csa_63: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(63) , + b => pp0_07(63) , + c => pp0_06(63) , + sum => pp1_05(63) , + car => pp1_04(62)); + pp1_02_csa_62: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(62) , + b => pp0_07(62) , + c => pp0_06(62) , + sum => pp1_05(62) , + car => pp1_04(61)); + pp1_02_csa_61: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(61) , + b => pp0_07(61) , + c => pp0_06(61) , + sum => pp1_05(61) , + car => pp1_04(60)); + pp1_02_csa_60: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(60) , + b => pp0_07(60) , + c => pp0_06(60) , + sum => pp1_05(60) , + car => pp1_04(59)); + pp1_02_csa_59: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(59) , + b => pp0_07(59) , + c => pp0_06(59) , + sum => pp1_05(59) , + car => pp1_04(58)); + pp1_02_csa_58: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(58) , + b => pp0_07(58) , + c => pp0_06(58) , + sum => pp1_05(58) , + car => pp1_04(57)); + pp1_02_csa_57: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(57) , + b => pp0_07(57) , + c => pp0_06(57) , + sum => pp1_05(57) , + car => pp1_04(56)); + pp1_02_csa_56: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(56) , + b => pp0_07(56) , + c => pp0_06(56) , + sum => pp1_05(56) , + car => pp1_04(55)); + pp1_02_csa_55: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(55) , + b => pp0_07(55) , + c => pp0_06(55) , + sum => pp1_05(55) , + car => pp1_04(54)); + pp1_02_csa_54: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(54) , + b => pp0_07(54) , + c => pp0_06(54) , + sum => pp1_05(54) , + car => pp1_04(53)); + pp1_02_csa_53: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(53) , + b => pp0_07(53) , + c => pp0_06(53) , + sum => pp1_05(53) , + car => pp1_04(52)); + pp1_02_csa_52: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(52) , + b => pp0_07(52) , + c => pp0_06(52) , + sum => pp1_05(52) , + car => pp1_04(51)); + pp1_02_csa_51: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(51) , + b => pp0_07(51) , + c => pp0_06(51) , + sum => pp1_05(51) , + car => pp1_04(50)); + pp1_02_csa_50: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(50) , + b => pp0_07(50) , + c => pp0_06(50) , + sum => pp1_05(50) , + car => pp1_04(49)); + pp1_02_csa_49: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(49) , + b => pp0_07(49) , + c => pp0_06(49) , + sum => pp1_05(49) , + car => pp1_04(48)); + pp1_02_csa_48: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(48) , + b => pp0_07(48) , + c => pp0_06(48) , + sum => pp1_05(48) , + car => pp1_04(47)); + pp1_02_csa_47: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(47) , + b => pp0_07(47) , + c => pp0_06(47) , + sum => pp1_05(47) , + car => pp1_04(46)); + pp1_02_csa_46: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(46) , + b => pp0_07(46) , + c => pp0_06(46) , + sum => pp1_05(46) , + car => pp1_04(45)); + pp1_02_csa_45: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(45) , + b => pp0_07(45) , + c => pp0_06(45) , + sum => pp1_05(45) , + car => pp1_04(44)); + pp1_02_csa_44: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(44) , + b => pp0_07(44) , + c => pp0_06(44) , + sum => pp1_05(44) , + car => pp1_04(43)); + pp1_02_csa_43: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(43) , + b => pp0_07(43) , + c => pp0_06(43) , + sum => pp1_05(43) , + car => pp1_04(42)); + pp1_02_csa_42: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(42) , + b => pp0_07(42) , + c => pp0_06(42) , + sum => pp1_05(42) , + car => pp1_04(41)); + pp1_02_csa_41: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(41) , + b => pp0_07(41) , + c => pp0_06(41) , + sum => pp1_05(41) , + car => pp1_04(40)); + pp1_02_csa_40: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(40) , + b => pp0_07(40) , + c => pp0_06(40) , + sum => pp1_05(40) , + car => pp1_04(39)); + pp1_02_csa_39: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(39) , + b => pp0_07(39) , + c => pp0_06(39) , + sum => pp1_05(39) , + car => pp1_04(38)); + pp1_02_csa_38: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(38) , + b => pp0_07(38) , + c => pp0_06(38) , + sum => pp1_05(38) , + car => pp1_04(37)); + pp1_02_csa_37: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(37) , + b => pp0_07(37) , + c => pp0_06(37) , + sum => pp1_05(37) , + car => pp1_04(36)); + pp1_02_csa_36: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(36) , + b => pp0_07(36) , + c => pp0_06(36) , + sum => pp1_05(36) , + car => pp1_04(35)); + pp1_02_csa_35: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(35) , + b => pp0_07(35) , + c => pp0_06(35) , + sum => pp1_05(35) , + car => pp1_04(34)); + pp1_02_csa_34: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(34) , + b => pp0_07(34) , + c => pp0_06(34) , + sum => pp1_05(34) , + car => pp1_04(33)); + pp1_02_csa_33: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(33) , + b => pp0_07(33) , + c => pp0_06(33) , + sum => pp1_05(33) , + car => pp1_04(32)); + pp1_02_csa_32: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(32) , + b => pp0_07(32) , + c => pp0_06(32) , + sum => pp1_05(32) , + car => pp1_04(31)); + pp1_02_csa_31: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(31) , + b => pp0_07(31) , + c => pp0_06(31) , + sum => pp1_05(31) , + car => pp1_04(30)); + pp1_02_csa_30: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(30) , + b => pp0_07(30) , + c => pp0_06(30) , + sum => pp1_05(30) , + car => pp1_04(29)); + pp1_02_csa_29: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(29) , + b => pp0_07(29) , + c => pp0_06(29) , + sum => pp1_05(29) , + car => pp1_04(28)); + pp1_02_csa_28: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(28) , + b => pp0_07(28) , + c => pp0_06(28) , + sum => pp1_05(28) , + car => pp1_04(27)); + pp1_02_csa_27: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(27) , + b => pp0_07(27) , + c => pp0_06(27) , + sum => pp1_05(27) , + car => pp1_04(26)); + pp1_02_csa_26: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(26) , + b => pp0_07(26) , + c => pp0_06(26) , + sum => pp1_05(26) , + car => pp1_04(25)); + pp1_02_csa_25: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(25) , + b => pp0_07(25) , + c => pp0_06(25) , + sum => pp1_05(25) , + car => pp1_04(24)); + pp1_02_csa_24: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(24) , + b => pp0_07(24) , + c => pp0_06(24) , + sum => pp1_05(24) , + car => pp1_04(23)); + pp1_02_csa_23: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(23) , + b => pp0_07(23) , + c => pp0_06(23) , + sum => pp1_05(23) , + car => pp1_04(22)); + pp1_02_csa_22: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(22) , + b => pp0_07(22) , + c => pp0_06(22) , + sum => pp1_05(22) , + car => pp1_04(21)); + pp1_02_csa_21: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(21) , + b => pp0_07(21) , + c => pp0_06(21) , + sum => pp1_05(21) , + car => pp1_04(20)); + pp1_02_csa_20: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(20) , + b => pp0_07(20) , + c => pp0_06(20) , + sum => pp1_05(20) , + car => pp1_04(19)); + pp1_02_csa_19: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(19) , + b => pp0_07(19) , + c => pp0_06(19) , + sum => pp1_05(19) , + car => pp1_04(18)); + pp1_02_csa_18: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(18) , + b => pp0_07(18) , + c => pp0_06(18) , + sum => pp1_05(18) , + car => pp1_04(17)); + pp1_02_csa_17: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(17) , + b => pp0_07(17) , + c => pp0_06(17) , + sum => pp1_05(17) , + car => pp1_04(16)); + pp1_02_csa_16: entity work.fuq_csa22_h2(fuq_csa22_h2) port map ( + a => tiup , + b => pp0_06(16) , + sum => pp1_05(16) , + car => pp1_04(15)); + pp1_05(15) <= pp0_06(15); + pp1_05(14) <= tiup; + + + pp1_03(70) <= pp0_05(70); + pp1_03(69) <= tidn; + pp1_03(68) <= pp0_05(68); + pp1_03(67) <= pp0_05(67); + + pp1_02(68) <= pp0_04(68); + pp1_02(67) <= tidn; + pp1_02(66) <= tidn; + + pp1_01_csa_66: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(66) , + b => pp0_04(66) , + c => pp0_03(66) , + sum => pp1_03(66) , + car => pp1_02(65)); + pp1_01_csa_65: entity work.fuq_csa22_h2(fuq_csa22_h2) port map ( + a => pp0_05(65) , + b => pp0_04(65) , + sum => pp1_03(65) , + car => pp1_02(64)); + pp1_01_csa_64: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(64) , + b => pp0_04(64) , + c => pp0_03(64) , + sum => pp1_03(64) , + car => pp1_02(63)); + pp1_01_csa_63: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(63) , + b => pp0_04(63) , + c => pp0_03(63) , + sum => pp1_03(63) , + car => pp1_02(62)); + pp1_01_csa_62: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(62) , + b => pp0_04(62) , + c => pp0_03(62) , + sum => pp1_03(62) , + car => pp1_02(61)); + pp1_01_csa_61: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(61) , + b => pp0_04(61) , + c => pp0_03(61) , + sum => pp1_03(61) , + car => pp1_02(60)); + pp1_01_csa_60: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(60) , + b => pp0_04(60) , + c => pp0_03(60) , + sum => pp1_03(60) , + car => pp1_02(59)); + pp1_01_csa_59: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(59) , + b => pp0_04(59) , + c => pp0_03(59) , + sum => pp1_03(59) , + car => pp1_02(58)); + pp1_01_csa_58: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(58) , + b => pp0_04(58) , + c => pp0_03(58) , + sum => pp1_03(58) , + car => pp1_02(57)); + pp1_01_csa_57: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(57) , + b => pp0_04(57) , + c => pp0_03(57) , + sum => pp1_03(57) , + car => pp1_02(56)); + pp1_01_csa_56: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(56) , + b => pp0_04(56) , + c => pp0_03(56) , + sum => pp1_03(56) , + car => pp1_02(55)); + pp1_01_csa_55: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(55) , + b => pp0_04(55) , + c => pp0_03(55) , + sum => pp1_03(55) , + car => pp1_02(54)); + pp1_01_csa_54: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(54) , + b => pp0_04(54) , + c => pp0_03(54) , + sum => pp1_03(54) , + car => pp1_02(53)); + pp1_01_csa_53: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(53) , + b => pp0_04(53) , + c => pp0_03(53) , + sum => pp1_03(53) , + car => pp1_02(52)); + pp1_01_csa_52: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(52) , + b => pp0_04(52) , + c => pp0_03(52) , + sum => pp1_03(52) , + car => pp1_02(51)); + pp1_01_csa_51: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(51) , + b => pp0_04(51) , + c => pp0_03(51) , + sum => pp1_03(51) , + car => pp1_02(50)); + pp1_01_csa_50: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(50) , + b => pp0_04(50) , + c => pp0_03(50) , + sum => pp1_03(50) , + car => pp1_02(49)); + pp1_01_csa_49: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(49) , + b => pp0_04(49) , + c => pp0_03(49) , + sum => pp1_03(49) , + car => pp1_02(48)); + pp1_01_csa_48: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(48) , + b => pp0_04(48) , + c => pp0_03(48) , + sum => pp1_03(48) , + car => pp1_02(47)); + pp1_01_csa_47: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(47) , + b => pp0_04(47) , + c => pp0_03(47) , + sum => pp1_03(47) , + car => pp1_02(46)); + pp1_01_csa_46: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(46) , + b => pp0_04(46) , + c => pp0_03(46) , + sum => pp1_03(46) , + car => pp1_02(45)); + pp1_01_csa_45: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(45) , + b => pp0_04(45) , + c => pp0_03(45) , + sum => pp1_03(45) , + car => pp1_02(44)); + pp1_01_csa_44: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(44) , + b => pp0_04(44) , + c => pp0_03(44) , + sum => pp1_03(44) , + car => pp1_02(43)); + pp1_01_csa_43: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(43) , + b => pp0_04(43) , + c => pp0_03(43) , + sum => pp1_03(43) , + car => pp1_02(42)); + pp1_01_csa_42: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(42) , + b => pp0_04(42) , + c => pp0_03(42) , + sum => pp1_03(42) , + car => pp1_02(41)); + pp1_01_csa_41: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(41) , + b => pp0_04(41) , + c => pp0_03(41) , + sum => pp1_03(41) , + car => pp1_02(40)); + pp1_01_csa_40: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(40) , + b => pp0_04(40) , + c => pp0_03(40) , + sum => pp1_03(40) , + car => pp1_02(39)); + pp1_01_csa_39: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(39) , + b => pp0_04(39) , + c => pp0_03(39) , + sum => pp1_03(39) , + car => pp1_02(38)); + pp1_01_csa_38: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(38) , + b => pp0_04(38) , + c => pp0_03(38) , + sum => pp1_03(38) , + car => pp1_02(37)); + pp1_01_csa_37: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(37) , + b => pp0_04(37) , + c => pp0_03(37) , + sum => pp1_03(37) , + car => pp1_02(36)); + pp1_01_csa_36: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(36) , + b => pp0_04(36) , + c => pp0_03(36) , + sum => pp1_03(36) , + car => pp1_02(35)); + pp1_01_csa_35: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(35) , + b => pp0_04(35) , + c => pp0_03(35) , + sum => pp1_03(35) , + car => pp1_02(34)); + pp1_01_csa_34: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(34) , + b => pp0_04(34) , + c => pp0_03(34) , + sum => pp1_03(34) , + car => pp1_02(33)); + pp1_01_csa_33: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(33) , + b => pp0_04(33) , + c => pp0_03(33) , + sum => pp1_03(33) , + car => pp1_02(32)); + pp1_01_csa_32: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(32) , + b => pp0_04(32) , + c => pp0_03(32) , + sum => pp1_03(32) , + car => pp1_02(31)); + pp1_01_csa_31: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(31) , + b => pp0_04(31) , + c => pp0_03(31) , + sum => pp1_03(31) , + car => pp1_02(30)); + pp1_01_csa_30: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(30) , + b => pp0_04(30) , + c => pp0_03(30) , + sum => pp1_03(30) , + car => pp1_02(29)); + pp1_01_csa_29: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(29) , + b => pp0_04(29) , + c => pp0_03(29) , + sum => pp1_03(29) , + car => pp1_02(28)); + pp1_01_csa_28: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(28) , + b => pp0_04(28) , + c => pp0_03(28) , + sum => pp1_03(28) , + car => pp1_02(27)); + pp1_01_csa_27: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(27) , + b => pp0_04(27) , + c => pp0_03(27) , + sum => pp1_03(27) , + car => pp1_02(26)); + pp1_01_csa_26: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(26) , + b => pp0_04(26) , + c => pp0_03(26) , + sum => pp1_03(26) , + car => pp1_02(25)); + pp1_01_csa_25: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(25) , + b => pp0_04(25) , + c => pp0_03(25) , + sum => pp1_03(25) , + car => pp1_02(24)); + pp1_01_csa_24: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(24) , + b => pp0_04(24) , + c => pp0_03(24) , + sum => pp1_03(24) , + car => pp1_02(23)); + pp1_01_csa_23: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(23) , + b => pp0_04(23) , + c => pp0_03(23) , + sum => pp1_03(23) , + car => pp1_02(22)); + pp1_01_csa_22: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(22) , + b => pp0_04(22) , + c => pp0_03(22) , + sum => pp1_03(22) , + car => pp1_02(21)); + pp1_01_csa_21: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(21) , + b => pp0_04(21) , + c => pp0_03(21) , + sum => pp1_03(21) , + car => pp1_02(20)); + pp1_01_csa_20: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(20) , + b => pp0_04(20) , + c => pp0_03(20) , + sum => pp1_03(20) , + car => pp1_02(19)); + pp1_01_csa_19: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(19) , + b => pp0_04(19) , + c => pp0_03(19) , + sum => pp1_03(19) , + car => pp1_02(18)); + pp1_01_csa_18: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(18) , + b => pp0_04(18) , + c => pp0_03(18) , + sum => pp1_03(18) , + car => pp1_02(17)); + pp1_01_csa_17: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(17) , + b => pp0_04(17) , + c => pp0_03(17) , + sum => pp1_03(17) , + car => pp1_02(16)); + pp1_01_csa_16: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(16) , + b => pp0_04(16) , + c => pp0_03(16) , + sum => pp1_03(16) , + car => pp1_02(15)); + pp1_01_csa_15: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(15) , + b => pp0_04(15) , + c => pp0_03(15) , + sum => pp1_03(15) , + car => pp1_02(14)); + pp1_01_csa_14: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(14) , + b => pp0_04(14) , + c => pp0_03(14) , + sum => pp1_03(14) , + car => pp1_02(13)); + pp1_01_csa_13: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(13) , + b => pp0_04(13) , + c => pp0_03(13) , + sum => pp1_03(13) , + car => pp1_02(12)); + pp1_01_csa_12: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => tiup , + b => pp0_04(12) , + c => pp0_03(12) , + sum => pp1_03(12) , + car => pp1_02(11)); + pp1_01_csa_11: entity work.fuq_csa22_h2(fuq_csa22_h2) port map ( + a => pp0_04(11) , + b => pp0_03(11) , + sum => pp1_03(11) , + car => pp1_02(10)); + pp1_01_csa_10: entity work.fuq_csa22_h2(fuq_csa22_h2) port map ( + a => tiup , + b => pp0_03(10) , + sum => pp1_03(10) , + car => pp1_02(9)); + pp1_03(9) <= pp0_03(9); + pp1_03(8) <= tiup; + + + + + pp1_01(64) <= pp0_02(64); + pp1_01(63) <= tidn; + pp1_01(62) <= pp0_02(62); + pp1_01(61) <= pp0_02(61); + + pp1_00(62) <= pp0_01(62); + pp1_00(61) <= tidn; + pp1_00(60) <= tidn; + + pp1_00_csa_60: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(60) , + b => pp0_01(60) , + c => pp0_00(60) , + sum => pp1_01(60) , + car => pp1_00(59)); + pp1_00_csa_59: entity work.fuq_csa22_h2(fuq_csa22_h2) port map ( + a => pp0_02(59) , + b => pp0_01(59) , + sum => pp1_01(59) , + car => pp1_00(58)); + pp1_00_csa_58: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(58) , + b => pp0_01(58) , + c => pp0_00(58) , + sum => pp1_01(58) , + car => pp1_00(57)); + pp1_00_csa_57: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(57) , + b => pp0_01(57) , + c => pp0_00(57) , + sum => pp1_01(57) , + car => pp1_00(56)); + pp1_00_csa_56: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(56) , + b => pp0_01(56) , + c => pp0_00(56) , + sum => pp1_01(56) , + car => pp1_00(55)); + pp1_00_csa_55: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(55) , + b => pp0_01(55) , + c => pp0_00(55) , + sum => pp1_01(55) , + car => pp1_00(54)); + pp1_00_csa_54: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(54) , + b => pp0_01(54) , + c => pp0_00(54) , + sum => pp1_01(54) , + car => pp1_00(53)); + pp1_00_csa_53: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(53) , + b => pp0_01(53) , + c => pp0_00(53) , + sum => pp1_01(53) , + car => pp1_00(52)); + pp1_00_csa_52: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(52) , + b => pp0_01(52) , + c => pp0_00(52) , + sum => pp1_01(52) , + car => pp1_00(51)); + pp1_00_csa_51: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(51) , + b => pp0_01(51) , + c => pp0_00(51) , + sum => pp1_01(51) , + car => pp1_00(50)); + pp1_00_csa_50: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(50) , + b => pp0_01(50) , + c => pp0_00(50) , + sum => pp1_01(50) , + car => pp1_00(49)); + pp1_00_csa_49: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(49) , + b => pp0_01(49) , + c => pp0_00(49) , + sum => pp1_01(49) , + car => pp1_00(48)); + pp1_00_csa_48: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(48) , + b => pp0_01(48) , + c => pp0_00(48) , + sum => pp1_01(48) , + car => pp1_00(47)); + pp1_00_csa_47: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(47) , + b => pp0_01(47) , + c => pp0_00(47) , + sum => pp1_01(47) , + car => pp1_00(46)); + pp1_00_csa_46: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(46) , + b => pp0_01(46) , + c => pp0_00(46) , + sum => pp1_01(46) , + car => pp1_00(45)); + pp1_00_csa_45: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(45) , + b => pp0_01(45) , + c => pp0_00(45) , + sum => pp1_01(45) , + car => pp1_00(44)); + pp1_00_csa_44: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(44) , + b => pp0_01(44) , + c => pp0_00(44) , + sum => pp1_01(44) , + car => pp1_00(43)); + pp1_00_csa_43: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(43) , + b => pp0_01(43) , + c => pp0_00(43) , + sum => pp1_01(43) , + car => pp1_00(42)); + pp1_00_csa_42: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(42) , + b => pp0_01(42) , + c => pp0_00(42) , + sum => pp1_01(42) , + car => pp1_00(41)); + pp1_00_csa_41: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(41) , + b => pp0_01(41) , + c => pp0_00(41) , + sum => pp1_01(41) , + car => pp1_00(40)); + pp1_00_csa_40: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(40) , + b => pp0_01(40) , + c => pp0_00(40) , + sum => pp1_01(40) , + car => pp1_00(39)); + pp1_00_csa_39: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(39) , + b => pp0_01(39) , + c => pp0_00(39) , + sum => pp1_01(39) , + car => pp1_00(38)); + pp1_00_csa_38: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(38) , + b => pp0_01(38) , + c => pp0_00(38) , + sum => pp1_01(38) , + car => pp1_00(37)); + pp1_00_csa_37: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(37) , + b => pp0_01(37) , + c => pp0_00(37) , + sum => pp1_01(37) , + car => pp1_00(36)); + pp1_00_csa_36: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(36) , + b => pp0_01(36) , + c => pp0_00(36) , + sum => pp1_01(36) , + car => pp1_00(35)); + pp1_00_csa_35: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(35) , + b => pp0_01(35) , + c => pp0_00(35) , + sum => pp1_01(35) , + car => pp1_00(34)); + pp1_00_csa_34: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(34) , + b => pp0_01(34) , + c => pp0_00(34) , + sum => pp1_01(34) , + car => pp1_00(33)); + pp1_00_csa_33: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(33) , + b => pp0_01(33) , + c => pp0_00(33) , + sum => pp1_01(33) , + car => pp1_00(32)); + pp1_00_csa_32: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(32) , + b => pp0_01(32) , + c => pp0_00(32) , + sum => pp1_01(32) , + car => pp1_00(31)); + pp1_00_csa_31: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(31) , + b => pp0_01(31) , + c => pp0_00(31) , + sum => pp1_01(31) , + car => pp1_00(30)); + pp1_00_csa_30: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(30) , + b => pp0_01(30) , + c => pp0_00(30) , + sum => pp1_01(30) , + car => pp1_00(29)); + pp1_00_csa_29: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(29) , + b => pp0_01(29) , + c => pp0_00(29) , + sum => pp1_01(29) , + car => pp1_00(28)); + pp1_00_csa_28: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(28) , + b => pp0_01(28) , + c => pp0_00(28) , + sum => pp1_01(28) , + car => pp1_00(27)); + pp1_00_csa_27: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(27) , + b => pp0_01(27) , + c => pp0_00(27) , + sum => pp1_01(27) , + car => pp1_00(26)); + pp1_00_csa_26: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(26) , + b => pp0_01(26) , + c => pp0_00(26) , + sum => pp1_01(26) , + car => pp1_00(25)); + pp1_00_csa_25: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(25) , + b => pp0_01(25) , + c => pp0_00(25) , + sum => pp1_01(25) , + car => pp1_00(24)); + pp1_00_csa_24: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(24) , + b => pp0_01(24) , + c => pp0_00(24) , + sum => pp1_01(24) , + car => pp1_00(23)); + pp1_00_csa_23: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(23) , + b => pp0_01(23) , + c => pp0_00(23) , + sum => pp1_01(23) , + car => pp1_00(22)); + pp1_00_csa_22: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(22) , + b => pp0_01(22) , + c => pp0_00(22) , + sum => pp1_01(22) , + car => pp1_00(21)); + pp1_00_csa_21: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(21) , + b => pp0_01(21) , + c => pp0_00(21) , + sum => pp1_01(21) , + car => pp1_00(20)); + pp1_00_csa_20: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(20) , + b => pp0_01(20) , + c => pp0_00(20) , + sum => pp1_01(20) , + car => pp1_00(19)); + pp1_00_csa_19: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(19) , + b => pp0_01(19) , + c => pp0_00(19) , + sum => pp1_01(19) , + car => pp1_00(18)); + pp1_00_csa_18: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(18) , + b => pp0_01(18) , + c => pp0_00(18) , + sum => pp1_01(18) , + car => pp1_00(17)); + pp1_00_csa_17: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(17) , + b => pp0_01(17) , + c => pp0_00(17) , + sum => pp1_01(17) , + car => pp1_00(16)); + pp1_00_csa_16: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(16) , + b => pp0_01(16) , + c => pp0_00(16) , + sum => pp1_01(16) , + car => pp1_00(15)); + pp1_00_csa_15: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(15) , + b => pp0_01(15) , + c => pp0_00(15) , + sum => pp1_01(15) , + car => pp1_00(14)); + pp1_00_csa_14: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(14) , + b => pp0_01(14) , + c => pp0_00(14) , + sum => pp1_01(14) , + car => pp1_00(13)); + pp1_00_csa_13: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(13) , + b => pp0_01(13) , + c => pp0_00(13) , + sum => pp1_01(13) , + car => pp1_00(12)); + pp1_00_csa_12: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(12) , + b => pp0_01(12) , + c => pp0_00(12) , + sum => pp1_01(12) , + car => pp1_00(11)); + pp1_00_csa_11: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(11) , + b => pp0_01(11) , + c => pp0_00(11) , + sum => pp1_01(11) , + car => pp1_00(10)); + pp1_00_csa_10: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(10) , + b => pp0_01(10) , + c => pp0_00(10) , + sum => pp1_01(10) , + car => pp1_00(9)); + pp1_00_csa_09: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(9) , + b => pp0_01(9) , + c => pp0_00(9) , + sum => pp1_01(9) , + car => pp1_00(8)); + pp1_00_csa_08: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(8) , + b => pp0_01(8) , + c => pp0_00(8) , + sum => pp1_01(8) , + car => pp1_00(7)); + pp1_00_csa_07: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(7) , + b => pp0_01(7) , + c => pp0_00(7) , + sum => pp1_01(7) , + car => pp1_00(6)); + pp1_00_csa_06: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => tiup , + b => pp0_01(6) , + c => pp0_00(6) , + sum => pp1_01(6) , + car => pp1_00(5)); + pp1_00_csa_05: entity work.fuq_csa22_h2(fuq_csa22_h2) port map ( + a => pp0_01(5) , + b => pp0_00(5) , + sum => pp1_01(5) , + car => pp1_00(4)); + pp1_00_csa_04: entity work.fuq_csa22_h2(fuq_csa22_h2) port map ( + a => tiup , + b => pp0_00(4) , + sum => pp1_01(4) , + car => pp1_00(3)); + + gg0: if (inst = 0) generate + pp1_01(3) <= tidn ; + pp1_01(2) <= tidn ; + end generate ; + + gg1: if (inst = 1) generate + pp1_01(3) <= pp0_00(3) ; + pp1_01(2) <= pp0_00(2) ; + end generate ; + + gg2: if (inst = 2) generate + pp1_01(3) <= pp0_00(3) ; + pp1_01(2) <= pp0_00(2) ; + end generate ; + + + + + + + pp2_03(74) <= pp1_05(74); + pp2_03(73) <= pp1_05(73); + pp2_03(72) <= pp1_05(72); + pp2_03(71) <= pp1_05(71); + + pp2_02(74) <= pp1_04(74); + pp2_02(73) <= tidn; + pp2_02(72) <= tidn; + pp2_02(71) <= pp1_04(71); + pp2_02(70) <= tidn; + + pp2_01_csa_70: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(70) , + b => pp1_04(70) , + c => pp1_03(70) , + sum => pp2_03(70) , + car => pp2_02(69)); + pp2_01_csa_69: entity work.fuq_csa22_h2(fuq_csa22_h2) port map ( + a => pp1_05(69) , + b => pp1_04(69) , + sum => pp2_03(69) , + car => pp2_02(68)); + pp2_01_csa_68: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(68) , + b => pp1_04(68) , + c => pp1_03(68) , + sum => pp2_03(68) , + car => pp2_02(67)); + pp2_01_csa_67: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(67) , + b => pp1_04(67) , + c => pp1_03(67) , + sum => pp2_03(67) , + car => pp2_02(66)); + pp2_01_csa_66: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(66) , + b => pp1_04(66) , + c => pp1_03(66) , + sum => pp2_03(66) , + car => pp2_02(65)); + pp2_01_csa_65: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(65) , + b => pp1_04(65) , + c => pp1_03(65) , + sum => pp2_03(65) , + car => pp2_02(64)); + pp2_01_csa_64: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(64) , + b => pp1_04(64) , + c => pp1_03(64) , + sum => pp2_03(64) , + car => pp2_02(63)); + pp2_01_csa_63: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(63) , + b => pp1_04(63) , + c => pp1_03(63) , + sum => pp2_03(63) , + car => pp2_02(62)); + pp2_01_csa_62: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(62) , + b => pp1_04(62) , + c => pp1_03(62) , + sum => pp2_03(62) , + car => pp2_02(61)); + pp2_01_csa_61: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(61) , + b => pp1_04(61) , + c => pp1_03(61) , + sum => pp2_03(61) , + car => pp2_02(60)); + pp2_01_csa_60: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(60) , + b => pp1_04(60) , + c => pp1_03(60) , + sum => pp2_03(60) , + car => pp2_02(59)); + pp2_01_csa_59: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(59) , + b => pp1_04(59) , + c => pp1_03(59) , + sum => pp2_03(59) , + car => pp2_02(58)); + pp2_01_csa_58: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(58) , + b => pp1_04(58) , + c => pp1_03(58) , + sum => pp2_03(58) , + car => pp2_02(57)); + pp2_01_csa_57: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(57) , + b => pp1_04(57) , + c => pp1_03(57) , + sum => pp2_03(57) , + car => pp2_02(56)); + pp2_01_csa_56: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(56) , + b => pp1_04(56) , + c => pp1_03(56) , + sum => pp2_03(56) , + car => pp2_02(55)); + pp2_01_csa_55: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(55) , + b => pp1_04(55) , + c => pp1_03(55) , + sum => pp2_03(55) , + car => pp2_02(54)); + pp2_01_csa_54: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(54) , + b => pp1_04(54) , + c => pp1_03(54) , + sum => pp2_03(54) , + car => pp2_02(53)); + pp2_01_csa_53: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(53) , + b => pp1_04(53) , + c => pp1_03(53) , + sum => pp2_03(53) , + car => pp2_02(52)); + pp2_01_csa_52: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(52) , + b => pp1_04(52) , + c => pp1_03(52) , + sum => pp2_03(52) , + car => pp2_02(51)); + pp2_01_csa_51: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(51) , + b => pp1_04(51) , + c => pp1_03(51) , + sum => pp2_03(51) , + car => pp2_02(50)); + pp2_01_csa_50: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(50) , + b => pp1_04(50) , + c => pp1_03(50) , + sum => pp2_03(50) , + car => pp2_02(49)); + pp2_01_csa_49: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(49) , + b => pp1_04(49) , + c => pp1_03(49) , + sum => pp2_03(49) , + car => pp2_02(48)); + pp2_01_csa_48: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(48) , + b => pp1_04(48) , + c => pp1_03(48) , + sum => pp2_03(48) , + car => pp2_02(47)); + pp2_01_csa_47: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(47) , + b => pp1_04(47) , + c => pp1_03(47) , + sum => pp2_03(47) , + car => pp2_02(46)); + pp2_01_csa_46: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(46) , + b => pp1_04(46) , + c => pp1_03(46) , + sum => pp2_03(46) , + car => pp2_02(45)); + pp2_01_csa_45: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(45) , + b => pp1_04(45) , + c => pp1_03(45) , + sum => pp2_03(45) , + car => pp2_02(44)); + pp2_01_csa_44: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(44) , + b => pp1_04(44) , + c => pp1_03(44) , + sum => pp2_03(44) , + car => pp2_02(43)); + pp2_01_csa_43: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(43) , + b => pp1_04(43) , + c => pp1_03(43) , + sum => pp2_03(43) , + car => pp2_02(42)); + pp2_01_csa_42: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(42) , + b => pp1_04(42) , + c => pp1_03(42) , + sum => pp2_03(42) , + car => pp2_02(41)); + pp2_01_csa_41: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(41) , + b => pp1_04(41) , + c => pp1_03(41) , + sum => pp2_03(41) , + car => pp2_02(40)); + pp2_01_csa_40: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(40) , + b => pp1_04(40) , + c => pp1_03(40) , + sum => pp2_03(40) , + car => pp2_02(39)); + pp2_01_csa_39: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(39) , + b => pp1_04(39) , + c => pp1_03(39) , + sum => pp2_03(39) , + car => pp2_02(38)); + pp2_01_csa_38: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(38) , + b => pp1_04(38) , + c => pp1_03(38) , + sum => pp2_03(38) , + car => pp2_02(37)); + pp2_01_csa_37: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(37) , + b => pp1_04(37) , + c => pp1_03(37) , + sum => pp2_03(37) , + car => pp2_02(36)); + pp2_01_csa_36: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(36) , + b => pp1_04(36) , + c => pp1_03(36) , + sum => pp2_03(36) , + car => pp2_02(35)); + pp2_01_csa_35: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(35) , + b => pp1_04(35) , + c => pp1_03(35) , + sum => pp2_03(35) , + car => pp2_02(34)); + pp2_01_csa_34: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(34) , + b => pp1_04(34) , + c => pp1_03(34) , + sum => pp2_03(34) , + car => pp2_02(33)); + pp2_01_csa_33: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(33) , + b => pp1_04(33) , + c => pp1_03(33) , + sum => pp2_03(33) , + car => pp2_02(32)); + pp2_01_csa_32: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(32) , + b => pp1_04(32) , + c => pp1_03(32) , + sum => pp2_03(32) , + car => pp2_02(31)); + pp2_01_csa_31: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(31) , + b => pp1_04(31) , + c => pp1_03(31) , + sum => pp2_03(31) , + car => pp2_02(30)); + pp2_01_csa_30: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(30) , + b => pp1_04(30) , + c => pp1_03(30) , + sum => pp2_03(30) , + car => pp2_02(29)); + pp2_01_csa_29: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(29) , + b => pp1_04(29) , + c => pp1_03(29) , + sum => pp2_03(29) , + car => pp2_02(28)); + pp2_01_csa_28: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(28) , + b => pp1_04(28) , + c => pp1_03(28) , + sum => pp2_03(28) , + car => pp2_02(27)); + pp2_01_csa_27: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(27) , + b => pp1_04(27) , + c => pp1_03(27) , + sum => pp2_03(27) , + car => pp2_02(26)); + pp2_01_csa_26: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(26) , + b => pp1_04(26) , + c => pp1_03(26) , + sum => pp2_03(26) , + car => pp2_02(25)); + pp2_01_csa_25: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(25) , + b => pp1_04(25) , + c => pp1_03(25) , + sum => pp2_03(25) , + car => pp2_02(24)); + pp2_01_csa_24: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(24) , + b => pp1_04(24) , + c => pp1_03(24) , + sum => pp2_03(24) , + car => pp2_02(23)); + pp2_01_csa_23: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(23) , + b => pp1_04(23) , + c => pp1_03(23) , + sum => pp2_03(23) , + car => pp2_02(22)); + pp2_01_csa_22: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(22) , + b => pp1_04(22) , + c => pp1_03(22) , + sum => pp2_03(22) , + car => pp2_02(21)); + pp2_01_csa_21: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(21) , + b => pp1_04(21) , + c => pp1_03(21) , + sum => pp2_03(21) , + car => pp2_02(20)); + pp2_01_csa_20: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(20) , + b => pp1_04(20) , + c => pp1_03(20) , + sum => pp2_03(20) , + car => pp2_02(19)); + pp2_01_csa_19: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(19) , + b => pp1_04(19) , + c => pp1_03(19) , + sum => pp2_03(19) , + car => pp2_02(18)); + pp2_01_csa_18: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(18) , + b => pp1_04(18) , + c => pp1_03(18) , + sum => pp2_03(18) , + car => pp2_02(17)); + pp2_01_csa_17: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(17) , + b => pp1_04(17) , + c => pp1_03(17) , + sum => pp2_03(17) , + car => pp2_02(16)); + pp2_01_csa_16: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(16) , + b => pp1_04(16) , + c => pp1_03(16) , + sum => pp2_03(16) , + car => pp2_02(15)); + pp2_01_csa_15: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(15) , + b => pp1_04(15) , + c => pp1_03(15) , + sum => pp2_03(15) , + car => pp2_02(14)); + pp2_01_csa_14: entity work.fuq_csa22_h2(fuq_csa22_h2) port map ( + a => tiup , + b => pp1_03(14) , + sum => pp2_03(14) , + car => pp2_02(13)); + pp2_03(13) <= pp1_03(13); + pp2_03(12) <= pp1_03(12); + pp2_03(11) <= pp1_03(11); + pp2_03(10) <= pp1_03(10); + pp2_03(9) <= pp1_03(9); + pp2_03(8) <= tiup; + + + + pp2_01(68) <= pp1_02(68); + pp2_01(67) <= tidn; + pp2_01(66) <= tidn; + pp2_01(65) <= pp1_02(65); + pp2_01(64) <= pp1_02(64); + pp2_01(63) <= pp1_02(63); + + pp2_00(64) <= pp1_01(64); + pp2_00(63) <= tidn; + pp2_00(62) <= tidn; + + pp2_00_csa_62: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(62) , + b => pp1_01(62) , + c => pp1_00(62) , + sum => pp2_01(62) , + car => pp2_00(61)); + pp2_00_csa_61: entity work.fuq_csa22_h2(fuq_csa22_h2) port map ( + a => pp1_02(61) , + b => pp1_01(61) , + sum => pp2_01(61) , + car => pp2_00(60)); + pp2_00_csa_60: entity work.fuq_csa22_h2(fuq_csa22_h2) port map ( + a => pp1_02(60) , + b => pp1_01(60) , + sum => pp2_01(60) , + car => pp2_00(59)); + pp2_00_csa_59: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(59) , + b => pp1_01(59) , + c => pp1_00(59) , + sum => pp2_01(59) , + car => pp2_00(58)); + pp2_00_csa_58: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(58) , + b => pp1_01(58) , + c => pp1_00(58) , + sum => pp2_01(58) , + car => pp2_00(57)); + pp2_00_csa_57: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(57) , + b => pp1_01(57) , + c => pp1_00(57) , + sum => pp2_01(57) , + car => pp2_00(56)); + pp2_00_csa_56: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(56) , + b => pp1_01(56) , + c => pp1_00(56) , + sum => pp2_01(56) , + car => pp2_00(55)); + pp2_00_csa_55: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(55) , + b => pp1_01(55) , + c => pp1_00(55) , + sum => pp2_01(55) , + car => pp2_00(54)); + pp2_00_csa_54: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(54) , + b => pp1_01(54) , + c => pp1_00(54) , + sum => pp2_01(54) , + car => pp2_00(53)); + pp2_00_csa_53: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(53) , + b => pp1_01(53) , + c => pp1_00(53) , + sum => pp2_01(53) , + car => pp2_00(52)); + pp2_00_csa_52: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(52) , + b => pp1_01(52) , + c => pp1_00(52) , + sum => pp2_01(52) , + car => pp2_00(51)); + pp2_00_csa_51: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(51) , + b => pp1_01(51) , + c => pp1_00(51) , + sum => pp2_01(51) , + car => pp2_00(50)); + pp2_00_csa_50: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(50) , + b => pp1_01(50) , + c => pp1_00(50) , + sum => pp2_01(50) , + car => pp2_00(49)); + pp2_00_csa_49: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(49) , + b => pp1_01(49) , + c => pp1_00(49) , + sum => pp2_01(49) , + car => pp2_00(48)); + pp2_00_csa_48: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(48) , + b => pp1_01(48) , + c => pp1_00(48) , + sum => pp2_01(48) , + car => pp2_00(47)); + pp2_00_csa_47: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(47) , + b => pp1_01(47) , + c => pp1_00(47) , + sum => pp2_01(47) , + car => pp2_00(46)); + pp2_00_csa_46: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(46) , + b => pp1_01(46) , + c => pp1_00(46) , + sum => pp2_01(46) , + car => pp2_00(45)); + pp2_00_csa_45: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(45) , + b => pp1_01(45) , + c => pp1_00(45) , + sum => pp2_01(45) , + car => pp2_00(44)); + pp2_00_csa_44: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(44) , + b => pp1_01(44) , + c => pp1_00(44) , + sum => pp2_01(44) , + car => pp2_00(43)); + pp2_00_csa_43: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(43) , + b => pp1_01(43) , + c => pp1_00(43) , + sum => pp2_01(43) , + car => pp2_00(42)); + pp2_00_csa_42: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(42) , + b => pp1_01(42) , + c => pp1_00(42) , + sum => pp2_01(42) , + car => pp2_00(41)); + pp2_00_csa_41: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(41) , + b => pp1_01(41) , + c => pp1_00(41) , + sum => pp2_01(41) , + car => pp2_00(40)); + pp2_00_csa_40: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(40) , + b => pp1_01(40) , + c => pp1_00(40) , + sum => pp2_01(40) , + car => pp2_00(39)); + pp2_00_csa_39: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(39) , + b => pp1_01(39) , + c => pp1_00(39) , + sum => pp2_01(39) , + car => pp2_00(38)); + pp2_00_csa_38: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(38) , + b => pp1_01(38) , + c => pp1_00(38) , + sum => pp2_01(38) , + car => pp2_00(37)); + pp2_00_csa_37: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(37) , + b => pp1_01(37) , + c => pp1_00(37) , + sum => pp2_01(37) , + car => pp2_00(36)); + pp2_00_csa_36: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(36) , + b => pp1_01(36) , + c => pp1_00(36) , + sum => pp2_01(36) , + car => pp2_00(35)); + pp2_00_csa_35: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(35) , + b => pp1_01(35) , + c => pp1_00(35) , + sum => pp2_01(35) , + car => pp2_00(34)); + pp2_00_csa_34: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(34) , + b => pp1_01(34) , + c => pp1_00(34) , + sum => pp2_01(34) , + car => pp2_00(33)); + pp2_00_csa_33: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(33) , + b => pp1_01(33) , + c => pp1_00(33) , + sum => pp2_01(33) , + car => pp2_00(32)); + pp2_00_csa_32: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(32) , + b => pp1_01(32) , + c => pp1_00(32) , + sum => pp2_01(32) , + car => pp2_00(31)); + pp2_00_csa_31: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(31) , + b => pp1_01(31) , + c => pp1_00(31) , + sum => pp2_01(31) , + car => pp2_00(30)); + pp2_00_csa_30: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(30) , + b => pp1_01(30) , + c => pp1_00(30) , + sum => pp2_01(30) , + car => pp2_00(29)); + pp2_00_csa_29: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(29) , + b => pp1_01(29) , + c => pp1_00(29) , + sum => pp2_01(29) , + car => pp2_00(28)); + pp2_00_csa_28: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(28) , + b => pp1_01(28) , + c => pp1_00(28) , + sum => pp2_01(28) , + car => pp2_00(27)); + pp2_00_csa_27: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(27) , + b => pp1_01(27) , + c => pp1_00(27) , + sum => pp2_01(27) , + car => pp2_00(26)); + pp2_00_csa_26: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(26) , + b => pp1_01(26) , + c => pp1_00(26) , + sum => pp2_01(26) , + car => pp2_00(25)); + pp2_00_csa_25: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(25) , + b => pp1_01(25) , + c => pp1_00(25) , + sum => pp2_01(25) , + car => pp2_00(24)); + pp2_00_csa_24: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(24) , + b => pp1_01(24) , + c => pp1_00(24) , + sum => pp2_01(24) , + car => pp2_00(23)); + pp2_00_csa_23: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(23) , + b => pp1_01(23) , + c => pp1_00(23) , + sum => pp2_01(23) , + car => pp2_00(22)); + pp2_00_csa_22: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(22) , + b => pp1_01(22) , + c => pp1_00(22) , + sum => pp2_01(22) , + car => pp2_00(21)); + pp2_00_csa_21: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(21) , + b => pp1_01(21) , + c => pp1_00(21) , + sum => pp2_01(21) , + car => pp2_00(20)); + pp2_00_csa_20: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(20) , + b => pp1_01(20) , + c => pp1_00(20) , + sum => pp2_01(20) , + car => pp2_00(19)); + pp2_00_csa_19: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(19) , + b => pp1_01(19) , + c => pp1_00(19) , + sum => pp2_01(19) , + car => pp2_00(18)); + pp2_00_csa_18: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(18) , + b => pp1_01(18) , + c => pp1_00(18) , + sum => pp2_01(18) , + car => pp2_00(17)); + pp2_00_csa_17: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(17) , + b => pp1_01(17) , + c => pp1_00(17) , + sum => pp2_01(17) , + car => pp2_00(16)); + pp2_00_csa_16: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(16) , + b => pp1_01(16) , + c => pp1_00(16) , + sum => pp2_01(16) , + car => pp2_00(15)); + pp2_00_csa_15: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(15) , + b => pp1_01(15) , + c => pp1_00(15) , + sum => pp2_01(15) , + car => pp2_00(14)); + pp2_00_csa_14: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(14) , + b => pp1_01(14) , + c => pp1_00(14) , + sum => pp2_01(14) , + car => pp2_00(13)); + pp2_00_csa_13: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(13) , + b => pp1_01(13) , + c => pp1_00(13) , + sum => pp2_01(13) , + car => pp2_00(12)); + pp2_00_csa_12: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(12) , + b => pp1_01(12) , + c => pp1_00(12) , + sum => pp2_01(12) , + car => pp2_00(11)); + pp2_00_csa_11: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(11) , + b => pp1_01(11) , + c => pp1_00(11) , + sum => pp2_01(11) , + car => pp2_00(10)); + pp2_00_csa_10: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(10) , + b => pp1_01(10) , + c => pp1_00(10) , + sum => pp2_01(10) , + car => pp2_00(9)); + pp2_00_csa_09: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(9) , + b => pp1_01(9) , + c => pp1_00(9) , + sum => pp2_01(9) , + car => pp2_00(8)); + pp2_00_csa_08: entity work.fuq_csa22_h2(fuq_csa22_h2) port map ( + a => pp1_01(8) , + b => pp1_00(8) , + sum => pp2_01(8) , + car => pp2_00(7)); + pp2_00_csa_07: entity work.fuq_csa22_h2(fuq_csa22_h2) port map ( + a => pp1_01(7) , + b => pp1_00(7) , + sum => pp2_01(7) , + car => pp2_00(6)); + pp2_00_csa_06: entity work.fuq_csa22_h2(fuq_csa22_h2) port map ( + a => pp1_01(6) , + b => pp1_00(6) , + sum => pp2_01(6) , + car => pp2_00(5)); + pp2_00_csa_05: entity work.fuq_csa22_h2(fuq_csa22_h2) port map ( + a => pp1_01(5) , + b => pp1_00(5) , + sum => pp2_01(5) , + car => pp2_00(4)); + pp2_00_csa_04: entity work.fuq_csa22_h2(fuq_csa22_h2) port map ( + a => pp1_01(4) , + b => pp1_00(4) , + sum => pp2_01(4) , + car => pp2_00(3)); + pp2_00_csa_03: entity work.fuq_csa22_h2(fuq_csa22_h2) port map ( + a => pp1_01(3) , + b => pp1_00(3) , + sum => pp2_01(3) , + car => pp2_00(2)); + pp2_01(2) <= pp1_01(2); + + + + + + + + + pp3_01(74) <= pp2_03(74); + pp3_01(73) <= pp2_03(73); + pp3_01(72) <= pp2_03(72); + pp3_01(71) <= pp2_03(71); + pp3_01(70) <= pp2_03(70); + pp3_01(69) <= pp2_03(69); + + pp3_00(74) <= pp2_02(74); + pp3_00(73) <= tidn; + pp3_00(72) <= tidn; + pp3_00(71) <= pp2_02(71); + pp3_00(70) <= tidn; + pp3_00(69) <= pp2_02(69); + pp3_00(68) <= tidn; + + pp3_00_csa_68: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(68) , + b => pp2_02(68) , + c => pp2_01(68) , + sum => pp3_01(68) , + car => pp3_00(67)); + pp3_00_csa_67: entity work.fuq_csa22_h2(fuq_csa22_h2) port map ( + a => pp2_03(67) , + b => pp2_02(67) , + sum => pp3_01(67) , + car => pp3_00(66)); + pp3_00_csa_66: entity work.fuq_csa22_h2(fuq_csa22_h2) port map ( + a => pp2_03(66) , + b => pp2_02(66) , + sum => pp3_01(66) , + car => pp3_00(65)); + pp3_00_csa_65: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(65) , + b => pp2_02(65) , + c => pp2_01(65) , + sum => pp3_01(65) , + car => pp3_00(64)); + pp3_00_csa_64: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(64) , + b => pp2_02(64) , + c => pp2_01(64) , + d => pp2_00(64) , + ki => tidn , + ko => pp3_00_ko(63) , + sum => pp3_01(64) , + car => pp3_00(63)); + pp3_00_csa_63: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(63) , + b => pp2_02(63) , + c => pp2_01(63) , + d => tidn , + ki => pp3_00_ko(63) , + ko => pp3_00_ko(62) , + sum => pp3_01(63) , + car => pp3_00(62)); + pp3_00_csa_62: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(62) , + b => pp2_02(62) , + c => pp2_01(62) , + d => tidn , + ki => pp3_00_ko(62) , + ko => pp3_00_ko(61) , + sum => pp3_01(62) , + car => pp3_00(61)); + pp3_00_csa_61: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(61) , + b => pp2_02(61) , + c => pp2_01(61) , + d => pp2_00(61) , + ki => pp3_00_ko(61) , + ko => pp3_00_ko(60) , + sum => pp3_01(61) , + car => pp3_00(60)); + pp3_00_csa_60: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(60) , + b => pp2_02(60) , + c => pp2_01(60) , + d => pp2_00(60) , + ki => pp3_00_ko(60) , + ko => pp3_00_ko(59) , + sum => pp3_01(60) , + car => pp3_00(59)); + pp3_00_csa_59: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(59) , + b => pp2_02(59) , + c => pp2_01(59) , + d => pp2_00(59) , + ki => pp3_00_ko(59) , + ko => pp3_00_ko(58) , + sum => pp3_01(59) , + car => pp3_00(58)); + pp3_00_csa_58: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(58) , + b => pp2_02(58) , + c => pp2_01(58) , + d => pp2_00(58) , + ki => pp3_00_ko(58) , + ko => pp3_00_ko(57) , + sum => pp3_01(58) , + car => pp3_00(57)); + pp3_00_csa_57: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(57) , + b => pp2_02(57) , + c => pp2_01(57) , + d => pp2_00(57) , + ki => pp3_00_ko(57) , + ko => pp3_00_ko(56) , + sum => pp3_01(57) , + car => pp3_00(56)); + pp3_00_csa_56: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(56) , + b => pp2_02(56) , + c => pp2_01(56) , + d => pp2_00(56) , + ki => pp3_00_ko(56) , + ko => pp3_00_ko(55) , + sum => pp3_01(56) , + car => pp3_00(55)); + pp3_00_csa_55: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(55) , + b => pp2_02(55) , + c => pp2_01(55) , + d => pp2_00(55) , + ki => pp3_00_ko(55) , + ko => pp3_00_ko(54) , + sum => pp3_01(55) , + car => pp3_00(54)); + pp3_00_csa_54: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(54) , + b => pp2_02(54) , + c => pp2_01(54) , + d => pp2_00(54) , + ki => pp3_00_ko(54) , + ko => pp3_00_ko(53) , + sum => pp3_01(54) , + car => pp3_00(53)); + pp3_00_csa_53: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(53) , + b => pp2_02(53) , + c => pp2_01(53) , + d => pp2_00(53) , + ki => pp3_00_ko(53) , + ko => pp3_00_ko(52) , + sum => pp3_01(53) , + car => pp3_00(52)); + pp3_00_csa_52: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(52) , + b => pp2_02(52) , + c => pp2_01(52) , + d => pp2_00(52) , + ki => pp3_00_ko(52) , + ko => pp3_00_ko(51) , + sum => pp3_01(52) , + car => pp3_00(51)); + pp3_00_csa_51: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(51) , + b => pp2_02(51) , + c => pp2_01(51) , + d => pp2_00(51) , + ki => pp3_00_ko(51) , + ko => pp3_00_ko(50) , + sum => pp3_01(51) , + car => pp3_00(50)); + pp3_00_csa_50: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(50) , + b => pp2_02(50) , + c => pp2_01(50) , + d => pp2_00(50) , + ki => pp3_00_ko(50) , + ko => pp3_00_ko(49) , + sum => pp3_01(50) , + car => pp3_00(49)); + pp3_00_csa_49: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(49) , + b => pp2_02(49) , + c => pp2_01(49) , + d => pp2_00(49) , + ki => pp3_00_ko(49) , + ko => pp3_00_ko(48) , + sum => pp3_01(49) , + car => pp3_00(48)); + pp3_00_csa_48: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(48) , + b => pp2_02(48) , + c => pp2_01(48) , + d => pp2_00(48) , + ki => pp3_00_ko(48) , + ko => pp3_00_ko(47) , + sum => pp3_01(48) , + car => pp3_00(47)); + pp3_00_csa_47: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(47) , + b => pp2_02(47) , + c => pp2_01(47) , + d => pp2_00(47) , + ki => pp3_00_ko(47) , + ko => pp3_00_ko(46) , + sum => pp3_01(47) , + car => pp3_00(46)); + pp3_00_csa_46: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(46) , + b => pp2_02(46) , + c => pp2_01(46) , + d => pp2_00(46) , + ki => pp3_00_ko(46) , + ko => pp3_00_ko(45) , + sum => pp3_01(46) , + car => pp3_00(45)); + pp3_00_csa_45: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(45) , + b => pp2_02(45) , + c => pp2_01(45) , + d => pp2_00(45) , + ki => pp3_00_ko(45) , + ko => pp3_00_ko(44) , + sum => pp3_01(45) , + car => pp3_00(44)); + pp3_00_csa_44: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(44) , + b => pp2_02(44) , + c => pp2_01(44) , + d => pp2_00(44) , + ki => pp3_00_ko(44) , + ko => pp3_00_ko(43) , + sum => pp3_01(44) , + car => pp3_00(43)); + pp3_00_csa_43: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(43) , + b => pp2_02(43) , + c => pp2_01(43) , + d => pp2_00(43) , + ki => pp3_00_ko(43) , + ko => pp3_00_ko(42) , + sum => pp3_01(43) , + car => pp3_00(42)); + pp3_00_csa_42: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(42) , + b => pp2_02(42) , + c => pp2_01(42) , + d => pp2_00(42) , + ki => pp3_00_ko(42) , + ko => pp3_00_ko(41) , + sum => pp3_01(42) , + car => pp3_00(41)); + pp3_00_csa_41: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(41) , + b => pp2_02(41) , + c => pp2_01(41) , + d => pp2_00(41) , + ki => pp3_00_ko(41) , + ko => pp3_00_ko(40) , + sum => pp3_01(41) , + car => pp3_00(40)); + pp3_00_csa_40: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(40) , + b => pp2_02(40) , + c => pp2_01(40) , + d => pp2_00(40) , + ki => pp3_00_ko(40) , + ko => pp3_00_ko(39) , + sum => pp3_01(40) , + car => pp3_00(39)); + pp3_00_csa_39: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(39) , + b => pp2_02(39) , + c => pp2_01(39) , + d => pp2_00(39) , + ki => pp3_00_ko(39) , + ko => pp3_00_ko(38) , + sum => pp3_01(39) , + car => pp3_00(38)); + pp3_00_csa_38: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(38) , + b => pp2_02(38) , + c => pp2_01(38) , + d => pp2_00(38) , + ki => pp3_00_ko(38) , + ko => pp3_00_ko(37) , + sum => pp3_01(38) , + car => pp3_00(37)); + pp3_00_csa_37: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(37) , + b => pp2_02(37) , + c => pp2_01(37) , + d => pp2_00(37) , + ki => pp3_00_ko(37) , + ko => pp3_00_ko(36) , + sum => pp3_01(37) , + car => pp3_00(36)); + pp3_00_csa_36: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(36) , + b => pp2_02(36) , + c => pp2_01(36) , + d => pp2_00(36) , + ki => pp3_00_ko(36) , + ko => pp3_00_ko(35) , + sum => pp3_01(36) , + car => pp3_00(35)); + pp3_00_csa_35: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(35) , + b => pp2_02(35) , + c => pp2_01(35) , + d => pp2_00(35) , + ki => pp3_00_ko(35) , + ko => pp3_00_ko(34) , + sum => pp3_01(35) , + car => pp3_00(34)); + pp3_00_csa_34: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(34) , + b => pp2_02(34) , + c => pp2_01(34) , + d => pp2_00(34) , + ki => pp3_00_ko(34) , + ko => pp3_00_ko(33) , + sum => pp3_01(34) , + car => pp3_00(33)); + pp3_00_csa_33: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(33) , + b => pp2_02(33) , + c => pp2_01(33) , + d => pp2_00(33) , + ki => pp3_00_ko(33) , + ko => pp3_00_ko(32) , + sum => pp3_01(33) , + car => pp3_00(32)); + pp3_00_csa_32: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(32) , + b => pp2_02(32) , + c => pp2_01(32) , + d => pp2_00(32) , + ki => pp3_00_ko(32) , + ko => pp3_00_ko(31) , + sum => pp3_01(32) , + car => pp3_00(31)); + pp3_00_csa_31: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(31) , + b => pp2_02(31) , + c => pp2_01(31) , + d => pp2_00(31) , + ki => pp3_00_ko(31) , + ko => pp3_00_ko(30) , + sum => pp3_01(31) , + car => pp3_00(30)); + pp3_00_csa_30: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(30) , + b => pp2_02(30) , + c => pp2_01(30) , + d => pp2_00(30) , + ki => pp3_00_ko(30) , + ko => pp3_00_ko(29) , + sum => pp3_01(30) , + car => pp3_00(29)); + pp3_00_csa_29: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(29) , + b => pp2_02(29) , + c => pp2_01(29) , + d => pp2_00(29) , + ki => pp3_00_ko(29) , + ko => pp3_00_ko(28) , + sum => pp3_01(29) , + car => pp3_00(28)); + pp3_00_csa_28: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(28) , + b => pp2_02(28) , + c => pp2_01(28) , + d => pp2_00(28) , + ki => pp3_00_ko(28) , + ko => pp3_00_ko(27) , + sum => pp3_01(28) , + car => pp3_00(27)); + pp3_00_csa_27: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(27) , + b => pp2_02(27) , + c => pp2_01(27) , + d => pp2_00(27) , + ki => pp3_00_ko(27) , + ko => pp3_00_ko(26) , + sum => pp3_01(27) , + car => pp3_00(26)); + pp3_00_csa_26: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(26) , + b => pp2_02(26) , + c => pp2_01(26) , + d => pp2_00(26) , + ki => pp3_00_ko(26) , + ko => pp3_00_ko(25) , + sum => pp3_01(26) , + car => pp3_00(25)); + pp3_00_csa_25: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(25) , + b => pp2_02(25) , + c => pp2_01(25) , + d => pp2_00(25) , + ki => pp3_00_ko(25) , + ko => pp3_00_ko(24) , + sum => pp3_01(25) , + car => pp3_00(24)); + pp3_00_csa_24: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(24) , + b => pp2_02(24) , + c => pp2_01(24) , + d => pp2_00(24) , + ki => pp3_00_ko(24) , + ko => pp3_00_ko(23) , + sum => pp3_01(24) , + car => pp3_00(23)); + pp3_00_csa_23: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(23) , + b => pp2_02(23) , + c => pp2_01(23) , + d => pp2_00(23) , + ki => pp3_00_ko(23) , + ko => pp3_00_ko(22) , + sum => pp3_01(23) , + car => pp3_00(22)); + pp3_00_csa_22: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(22) , + b => pp2_02(22) , + c => pp2_01(22) , + d => pp2_00(22) , + ki => pp3_00_ko(22) , + ko => pp3_00_ko(21) , + sum => pp3_01(22) , + car => pp3_00(21)); + pp3_00_csa_21: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(21) , + b => pp2_02(21) , + c => pp2_01(21) , + d => pp2_00(21) , + ki => pp3_00_ko(21) , + ko => pp3_00_ko(20) , + sum => pp3_01(21) , + car => pp3_00(20)); + pp3_00_csa_20: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(20) , + b => pp2_02(20) , + c => pp2_01(20) , + d => pp2_00(20) , + ki => pp3_00_ko(20) , + ko => pp3_00_ko(19) , + sum => pp3_01(20) , + car => pp3_00(19)); + pp3_00_csa_19: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(19) , + b => pp2_02(19) , + c => pp2_01(19) , + d => pp2_00(19) , + ki => pp3_00_ko(19) , + ko => pp3_00_ko(18) , + sum => pp3_01(19) , + car => pp3_00(18)); + pp3_00_csa_18: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(18) , + b => pp2_02(18) , + c => pp2_01(18) , + d => pp2_00(18) , + ki => pp3_00_ko(18) , + ko => pp3_00_ko(17) , + sum => pp3_01(18) , + car => pp3_00(17)); + pp3_00_csa_17: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(17) , + b => pp2_02(17) , + c => pp2_01(17) , + d => pp2_00(17) , + ki => pp3_00_ko(17) , + ko => pp3_00_ko(16) , + sum => pp3_01(17) , + car => pp3_00(16)); + pp3_00_csa_16: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(16) , + b => pp2_02(16) , + c => pp2_01(16) , + d => pp2_00(16) , + ki => pp3_00_ko(16) , + ko => pp3_00_ko(15) , + sum => pp3_01(16) , + car => pp3_00(15)); + pp3_00_csa_15: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(15) , + b => pp2_02(15) , + c => pp2_01(15) , + d => pp2_00(15) , + ki => pp3_00_ko(15) , + ko => pp3_00_ko(14) , + sum => pp3_01(15) , + car => pp3_00(14)); + pp3_00_csa_14: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(14) , + b => pp2_02(14) , + c => pp2_01(14) , + d => pp2_00(14) , + ki => pp3_00_ko(14) , + ko => pp3_00_ko(13) , + sum => pp3_01(14) , + car => pp3_00(13)); + pp3_00_csa_13: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(13) , + b => pp2_02(13) , + c => pp2_01(13) , + d => pp2_00(13) , + ki => pp3_00_ko(13) , + ko => pp3_00_ko(12) , + sum => pp3_01(13) , + car => pp3_00(12)); + pp3_00_csa_12: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(12) , + b => pp2_01(12) , + c => pp2_00(12) , + d => tidn , + ki => pp3_00_ko(12) , + ko => pp3_00_ko(11) , + sum => pp3_01(12) , + car => pp3_00(11)); + pp3_00_csa_11: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(11) , + b => pp2_01(11) , + c => pp2_00(11) , + d => tidn , + ki => pp3_00_ko(11) , + ko => pp3_00_ko(10) , + sum => pp3_01(11) , + car => pp3_00(10)); + pp3_00_csa_10: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(10) , + b => pp2_01(10) , + c => pp2_00(10) , + d => tidn , + ki => pp3_00_ko(10) , + ko => pp3_00_ko(9) , + sum => pp3_01(10) , + car => pp3_00(9)); + pp3_00_csa_09: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(9) , + b => pp2_01(9) , + c => pp2_00(9) , + d => tidn , + ki => pp3_00_ko(9) , + ko => pp3_00_ko(8) , + sum => pp3_01(9) , + car => pp3_00(8)); + pp3_00_csa_08: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => tiup , + b => pp2_01(8) , + c => pp2_00(8) , + d => tidn , + ki => pp3_00_ko(8) , + ko => pp3_00_ko(7) , + sum => pp3_01(8) , + car => pp3_00(7)); + pp3_00_csa_07: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp2_01(7) , + b => pp2_00(7) , + c => pp3_00_ko(7) , + sum => pp3_01(7) , + car => pp3_00(6)); + pp3_00_csa_06: entity work.fuq_csa22_h2(fuq_csa22_h2) port map ( + a => pp2_01(6) , + b => pp2_00(6) , + sum => pp3_01(6) , + car => pp3_00(5)); + pp3_00_csa_05: entity work.fuq_csa22_h2(fuq_csa22_h2) port map ( + a => pp2_01(5) , + b => pp2_00(5) , + sum => pp3_01(5) , + car => pp3_00(4)); + pp3_00_csa_04: entity work.fuq_csa22_h2(fuq_csa22_h2) port map ( + a => pp2_01(4) , + b => pp2_00(4) , + sum => pp3_01(4) , + car => pp3_00(3)); + pp3_00_csa_03: entity work.fuq_csa22_h2(fuq_csa22_h2) port map ( + a => pp2_01(3) , + b => pp2_00(3) , + sum => pp3_01(3) , + car => pp3_00(2)); + pp3_00_csa_02: entity work.fuq_csa22_h2(fuq_csa22_h2) port map ( + a => pp2_01(2) , + b => pp2_00(2) , + sum => pp3_01(2) , + car => pp3_00(1)); + + + + + mul92_lcb: tri_lcbnd generic map (expand_type => expand_type) port map ( + delay_lclkr => lcb_delay_lclkr , + mpw1_b => lcb_mpw1_b , + mpw2_b => lcb_mpw2_b , + forcee => forcee, + nclk => nclk , + vd => vdd , + gd => gnd , + act => ex1_act , + sg => lcb_sg , + thold_b => thold_b , + d1clk => mul92_d1clk , + d2clk => mul92_d2clk , + lclk => mul92_lclk ); + + + pp3_lat_sum: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 73, btr => "NLI0001_X1_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd, + gd => gnd, + LCLK => mul92_lclk , + D1CLK => mul92_d1clk , + D2CLK => mul92_d2clk , + SCANIN(0) => si , + SCANIN(1 to 72) => pp3_lat_sum_so(0 to 71) , + SCANOUT => pp3_lat_sum_so(0 to 72) , + D(0 to 72) => pp3_01(2 to 74) , + QB(0 to 72) => pp3_01_q_b(2 to 74) ); + + pp3_lat_car: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 71, btr => "NLI0001_X1_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd, + gd => gnd, + LCLK => mul92_lclk , + D1CLK => mul92_d1clk , + D2CLK => mul92_d2clk , + SCANIN(0 to 69) => pp3_lat_car_so(1 to 70) , + SCANIN(70) => pp3_lat_sum_so(72) , + SCANOUT => pp3_lat_car_so(0 to 70) , + D(0 to 66) => pp3_00(1 to 67) , + D(67) => pp3_00(69) , + D(68) => hot_one_din , + D(69) => pp3_00(71) , + D(70) => pp3_00(74) , + QB(0 to 66) => pp3_00_q_b(1 to 67) , + QB(67) => pp3_00_q_b(69) , + QB(68) => hot_one_out_b , + QB(69) => pp3_00_q_b(71) , + QB(70) => pp3_00_q_b(74) ) ; + + + + pp3_00_q_b(68) <= tiup; + pp3_00_q_b(70) <= tiup; + pp3_00_q_b(72) <= tiup; + pp3_00_q_b(73) <= tiup; + hot_one_out <= not hot_one_out_b ; + + invo_s: sum92(2 to 74) <= not pp3_01_q_b(2 to 74); + invo_c: car92(1 to 74) <= not pp3_00_q_b(1 to 74); + + + so <= pp3_lat_car_so(0); + +end; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_mul_bthdcd.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_mul_bthdcd.vhdl new file mode 100644 index 0000000..408676b --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_mul_bthdcd.vhdl @@ -0,0 +1,105 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; +use ieee.std_logic_1164.all; +library ibm; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_ao_support.all; +use ibm.std_ulogic_mux_support.all; + +entity fuq_mul_bthdcd is + port( + i0 : in std_ulogic; + i1 : in std_ulogic; + i2 : in std_ulogic; + s_neg : out std_ulogic; + s_x : out std_ulogic; + s_x2 : out std_ulogic); + + + + + +end fuq_mul_bthdcd; + +architecture fuq_mul_bthdcd of fuq_mul_bthdcd is + + + signal s_add :std_ulogic; + signal sx1_a0_b :std_ulogic; + signal sx1_a1_b :std_ulogic; + signal sx1_t :std_ulogic; + signal sx1_i :std_ulogic; + signal sx2_a0_b :std_ulogic; + signal sx2_a1_b :std_ulogic; + signal sx2_t :std_ulogic; + signal sx2_i :std_ulogic; + signal i0_b, i1_b, i2_b :std_ulogic; + + + + + + + + + +begin + + + +u_0i: i0_b <= not( i0 ); +u_1i: i1_b <= not( i1 ); +u_2i: i2_b <= not( i2 ); + + +u_add: s_add <= not( i0 ); +u_sub: s_neg <= not( s_add ); + +u_sx1_a0: sx1_a0_b <= not( i1_b and i2 ) ; +u_sx1_a1: sx1_a1_b <= not( i1 and i2_b ) ; +u_sx1_t: sx1_t <= not( sx1_a0_b and sx1_a1_b ) ; +u_sx1_i: sx1_i <= not( sx1_t ); +u_sx1_ii: s_x <= not( sx1_i ); + +u_sx2_a0: sx2_a0_b <= not( i0 and i1_b and i2_b ) ; +u_sx2_a1: sx2_a1_b <= not( i0_b and i1 and i2 ) ; +u_sx2_t: sx2_t <= not( sx2_a0_b and sx2_a1_b ) ; +u_sx2_i: sx2_i <= not( sx2_t ); +u_sx2_ii: s_x2 <= not( sx2_i ); + + + + + +end; + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_mul_bthmux.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_mul_bthmux.vhdl new file mode 100644 index 0000000..2c9ae39 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_mul_bthmux.vhdl @@ -0,0 +1,74 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; +use ieee.std_logic_1164.all; +library ibm; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_ao_support.all; +use ibm.std_ulogic_mux_support.all; + +entity fuq_mul_bthmux is port( + X : IN STD_ULOGIC; + SNEG : IN STD_ULOGIC; + SX : IN STD_ULOGIC; + SX2 : IN STD_ULOGIC; + RIGHT : IN STD_ULOGIC; + LEFT : OUT STD_ULOGIC; + Q : OUT STD_ULOGIC +); + + + + +end fuq_mul_bthmux; + +architecture fuq_mul_bthmux of fuq_mul_bthmux is + + signal center, q_b :std_ulogic ; + + + +begin + + u_bmx_xor: center <= x xor sneg ; + + left <= center ; + + u_bmx_aoi: q_b <= not( ( sx and center ) or + ( sx2 and right ) ); + + u_bmx_inv: q <= not q_b ; + + + +end; + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_mul_bthrow.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_mul_bthrow.vhdl new file mode 100644 index 0000000..eefb807 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_mul_bthrow.vhdl @@ -0,0 +1,577 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; +use ieee.std_logic_1164.all; +library ibm; + +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_ao_support.all; +use ibm.std_ulogic_mux_support.all; + + +entity fuq_mul_bthrow is + port( + x : in std_ulogic_vector(0 to 53); + s_neg : in std_ulogic; + s_x : in std_ulogic; + s_x2 : in std_ulogic; + hot_one : out std_ulogic; + q : out std_ulogic_vector(0 to 54)); + + +end fuq_mul_bthrow; + +architecture fuq_mul_bthrow of fuq_mul_bthrow is + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal left : std_ulogic_vector(0 to 54); + signal unused : std_ulogic; + + + + + +begin + + unused <= left(0) ; + + u00 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => tidn , + RIGHT => left(1) , + LEFT => left(0) , + Q => q(0)); + + u01 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(0) , + RIGHT => left(2) , + LEFT => left(1) , + Q => q(1)); + + u02 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(1) , + RIGHT => left(3) , + LEFT => left(2) , + Q => q(2)); + + u03 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(2) , + RIGHT => left(4) , + LEFT => left(3) , + Q => q(3)); + + u04 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(3) , + RIGHT => left(5) , + LEFT => left(4) , + Q => q(4)); + + u05 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(4) , + RIGHT => left(6) , + LEFT => left(5) , + Q => q(5)); + + u06 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(5) , + RIGHT => left(7) , + LEFT => left(6) , + Q => q(6)); + + u07 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(6) , + RIGHT => left(8) , + LEFT => left(7) , + Q => q(7)); + + u08 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(7) , + RIGHT => left(9) , + LEFT => left(8) , + Q => q(8)); + + u09 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(8) , + RIGHT => left(10) , + LEFT => left(9) , + Q => q(9)); + + u10 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(9) , + RIGHT => left(11) , + LEFT => left(10) , + Q => q(10)); + + u11 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(10) , + RIGHT => left(12) , + LEFT => left(11) , + Q => q(11)); + + u12 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(11) , + RIGHT => left(13) , + LEFT => left(12) , + Q => q(12)); + + u13 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(12) , + RIGHT => left(14) , + LEFT => left(13) , + Q => q(13)); + + u14 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(13) , + RIGHT => left(15) , + LEFT => left(14) , + Q => q(14)); + + u15 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(14) , + RIGHT => left(16) , + LEFT => left(15) , + Q => q(15)); + + u16 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(15) , + RIGHT => left(17) , + LEFT => left(16) , + Q => q(16)); + + u17 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(16) , + RIGHT => left(18) , + LEFT => left(17) , + Q => q(17)); + + u18 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(17) , + RIGHT => left(19) , + LEFT => left(18) , + Q => q(18)); + + u19 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(18) , + RIGHT => left(20) , + LEFT => left(19) , + Q => q(19)); + + u20 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(19) , + RIGHT => left(21) , + LEFT => left(20) , + Q => q(20)); + + u21 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(20) , + RIGHT => left(22) , + LEFT => left(21) , + Q => q(21)); + + u22 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(21) , + RIGHT => left(23) , + LEFT => left(22) , + Q => q(22)); + + u23 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(22) , + RIGHT => left(24) , + LEFT => left(23) , + Q => q(23)); + + u24 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(23) , + RIGHT => left(25) , + LEFT => left(24) , + Q => q(24)); + + u25 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(24) , + RIGHT => left(26) , + LEFT => left(25) , + Q => q(25)); + + u26 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(25) , + RIGHT => left(27) , + LEFT => left(26) , + Q => q(26)); + + u27 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(26) , + RIGHT => left(28) , + LEFT => left(27) , + Q => q(27)); + + u28 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(27) , + RIGHT => left(29) , + LEFT => left(28) , + Q => q(28)); + + u29 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(28) , + RIGHT => left(30) , + LEFT => left(29) , + Q => q(29)); + + u30 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(29) , + RIGHT => left(31) , + LEFT => left(30) , + Q => q(30)); + + u31 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(30) , + RIGHT => left(32) , + LEFT => left(31) , + Q => q(31)); + + u32 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(31) , + RIGHT => left(33) , + LEFT => left(32) , + Q => q(32)); + + u33 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(32) , + RIGHT => left(34) , + LEFT => left(33) , + Q => q(33)); + + u34 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(33) , + RIGHT => left(35) , + LEFT => left(34) , + Q => q(34)); + + u35 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(34) , + RIGHT => left(36) , + LEFT => left(35) , + Q => q(35)); + + u36 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(35) , + RIGHT => left(37) , + LEFT => left(36) , + Q => q(36)); + + u37 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(36) , + RIGHT => left(38) , + LEFT => left(37) , + Q => q(37)); + + u38 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(37) , + RIGHT => left(39) , + LEFT => left(38) , + Q => q(38)); + + u39 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(38) , + RIGHT => left(40) , + LEFT => left(39) , + Q => q(39)); + + u40 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(39) , + RIGHT => left(41) , + LEFT => left(40) , + Q => q(40)); + + u41 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(40) , + RIGHT => left(42) , + LEFT => left(41) , + Q => q(41)); + + u42 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(41) , + RIGHT => left(43) , + LEFT => left(42) , + Q => q(42)); + + u43 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(42) , + RIGHT => left(44) , + LEFT => left(43) , + Q => q(43)); + + u44 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(43) , + RIGHT => left(45) , + LEFT => left(44) , + Q => q(44)); + + u45 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(44) , + RIGHT => left(46) , + LEFT => left(45) , + Q => q(45)); + + u46 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(45) , + RIGHT => left(47) , + LEFT => left(46) , + Q => q(46)); + + u47 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(46) , + RIGHT => left(48) , + LEFT => left(47) , + Q => q(47)); + + u48 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(47) , + RIGHT => left(49) , + LEFT => left(48) , + Q => q(48)); + + u49 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(48) , + RIGHT => left(50) , + LEFT => left(49) , + Q => q(49)); + + u50 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(49) , + RIGHT => left(51) , + LEFT => left(50) , + Q => q(50)); + + u51 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(50) , + RIGHT => left(52) , + LEFT => left(51) , + Q => q(51)); + + u52 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(51) , + RIGHT => left(53) , + LEFT => left(52) , + Q => q(52)); + + u53 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(52) , + RIGHT => left(54) , + LEFT => left(53) , + Q => q(53)); + + u54 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(53) , + RIGHT => s_neg , + LEFT => left(54) , + Q => q(54)); + + + + u55: hot_one <= ( s_neg and (s_x or s_x2) ); + +end; + + + + + + + + + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_nrm.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_nrm.vhdl new file mode 100644 index 0000000..7f24edc --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_nrm.vhdl @@ -0,0 +1,560 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + +entity fuq_nrm is +generic( expand_type : integer := 2 ); +port( + + vdd :inout power_logic; + gnd :inout power_logic; + clkoff_b :in std_ulogic; + act_dis :in std_ulogic; + flush :in std_ulogic; + delay_lclkr :in std_ulogic_vector(4 to 5); + mpw1_b :in std_ulogic_vector(4 to 5); + mpw2_b :in std_ulogic_vector(0 to 1); + sg_1 :in std_ulogic; + thold_1 :in std_ulogic; + fpu_enable :in std_ulogic; + nclk :in clk_logic; + + f_nrm_si :in std_ulogic ; + f_nrm_so :out std_ulogic ; + ex3_act_b :in std_ulogic ; + + f_lza_ex4_lza_amt_cp1 :in std_ulogic_vector(0 to 7) ; + + f_lza_ex4_lza_dcd64_cp1 :in std_ulogic_vector(0 to 2); + f_lza_ex4_lza_dcd64_cp2 :in std_ulogic_vector(0 to 1); + f_lza_ex4_lza_dcd64_cp3 :in std_ulogic_vector(0 to 0); + f_lza_ex4_sh_rgt_en :in std_ulogic; + + f_add_ex4_res :in std_ulogic_vector(0 to 162) ; + f_add_ex4_sticky :in std_ulogic ; + f_pic_ex4_byp_prod_nz :in std_ulogic ; + f_nrm_ex5_res :out std_ulogic_vector(0 to 52) ; + f_nrm_ex5_int_sign :out std_ulogic ; + f_nrm_ex5_int_lsbs :out std_ulogic_vector(1 to 12) ; + f_nrm_ex5_nrm_sticky_dp :out std_ulogic ; + f_nrm_ex5_nrm_guard_dp :out std_ulogic ; + f_nrm_ex5_nrm_lsb_dp :out std_ulogic ; + f_nrm_ex5_nrm_sticky_sp :out std_ulogic ; + f_nrm_ex5_nrm_guard_sp :out std_ulogic ; + f_nrm_ex5_nrm_lsb_sp :out std_ulogic ; + f_nrm_ex5_exact_zero :out std_ulogic ; + f_nrm_ex4_extra_shift :out std_ulogic ; + f_nrm_ex5_fpscr_wr_dat_dfp :out std_ulogic_vector(0 to 3) ; + f_nrm_ex5_fpscr_wr_dat :out std_ulogic_vector(0 to 31) + + +); + + + + +end fuq_nrm; + + +architecture fuq_nrm of fuq_nrm is + + constant tiup :std_ulogic := '1'; + constant tidn :std_ulogic := '0'; + + signal sg_0 :std_ulogic ; + signal thold_0_b, thold_0, forcee :std_ulogic ; + signal ex3_act :std_ulogic ; + signal ex4_act :std_ulogic ; + signal act_spare_unused :std_ulogic_vector(0 to 2) ; + signal act_so :std_ulogic_vector(0 to 3) ; + signal act_si :std_ulogic_vector(0 to 3) ; + signal ex5_res_so :std_ulogic_vector(0 to 52) ; + signal ex5_res_si :std_ulogic_vector(0 to 52) ; + signal ex5_nrm_lg_so :std_ulogic_vector(0 to 3) ; + signal ex5_nrm_lg_si :std_ulogic_vector(0 to 3) ; + signal ex5_nrm_x_so :std_ulogic_vector(0 to 2) ; + signal ex5_nrm_x_si :std_ulogic_vector(0 to 2) ; + signal ex5_nrm_pass_so :std_ulogic_vector(0 to 12) ; + signal ex5_nrm_pass_si :std_ulogic_vector(0 to 12) ; + signal ex5_fmv_so :std_ulogic_vector(0 to 35) ; + signal ex5_fmv_si :std_ulogic_vector(0 to 35) ; + signal ex4_sh2 :std_ulogic_vector(26 to 72) ; + signal ex4_sh4_25 :std_ulogic ; + signal ex4_sh4_54 :std_ulogic ; + signal ex4_nrm_res , ex4_sh5_x_b, ex4_sh5_y_b :std_ulogic_vector(0 to 53) ; + signal ex4_lt064_x :std_ulogic ; + signal ex4_lt128_x :std_ulogic ; + signal ex4_lt016_x :std_ulogic ; + signal ex4_lt032_x :std_ulogic ; + signal ex4_lt048_x :std_ulogic ; + signal ex4_lt016 :std_ulogic ; + signal ex4_lt032 :std_ulogic ; + signal ex4_lt048 :std_ulogic ; + signal ex4_lt064 :std_ulogic ; + signal ex4_lt080 :std_ulogic ; + signal ex4_lt096 :std_ulogic ; + signal ex4_lt112 :std_ulogic ; + signal ex4_lt128 :std_ulogic ; + signal ex4_lt04_x :std_ulogic ; + signal ex4_lt08_x :std_ulogic ; + signal ex4_lt12_x :std_ulogic ; + signal ex4_lt01_x :std_ulogic ; + signal ex4_lt02_x :std_ulogic ; + signal ex4_lt03_x :std_ulogic ; + signal ex4_sticky_sp :std_ulogic ; + signal ex4_sticky_dp :std_ulogic ; + signal ex4_sticky16_dp :std_ulogic ; + signal ex4_sticky16_sp :std_ulogic ; + signal ex4_or_grp16 :std_ulogic_vector(0 to 10) ; + signal ex4_lt :std_ulogic_vector(0 to 14) ; + signal ex4_exact_zero :std_ulogic ; + signal ex4_exact_zero_b :std_ulogic ; + signal ex5_res :std_ulogic_vector(0 to 52); + signal ex5_nrm_sticky_dp :std_ulogic; + signal ex5_nrm_guard_dp :std_ulogic; + signal ex5_nrm_lsb_dp :std_ulogic; + signal ex5_nrm_sticky_sp :std_ulogic; + signal ex5_nrm_guard_sp :std_ulogic; + signal ex5_nrm_lsb_sp :std_ulogic; + signal ex5_exact_zero :std_ulogic; + signal ex5_int_sign :std_ulogic; + signal ex5_int_lsbs :std_ulogic_vector(1 to 12); + signal ex5_fpscr_wr_dat :std_ulogic_vector(0 to 31); + signal ex5_fpscr_wr_dat_dfp :std_ulogic_vector(0 to 3); + signal ex4_rgt_4more, ex4_rgt_3more, ex4_rgt_2more :std_ulogic; + signal ex4_shift_extra_cp2 :std_ulogic; + signal unused :std_ulogic; + + signal ex4_sticky_dp_x2_b, ex4_sticky_dp_x1_b, ex4_sticky_dp_x1 :std_ulogic; + signal ex4_sticky_sp_x2_b, ex4_sticky_sp_x1_b, ex4_sticky_sp_x1 :std_ulogic; + signal ex5_d1clk, ex5_d2clk :std_ulogic ; + signal ex5_lclk :clk_logic; + signal ex4_sticky_stuff :std_ulogic ; + + + + +begin + + unused <= or_reduce( ex4_sh2(41 to 54) ) or + or_reduce( ex4_nrm_res(0 to 53) ) or + ex4_sticky_sp or + ex4_sticky_dp or + ex4_exact_zero ; + + + + thold_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => thold_1, + q(0) => thold_0 ); + + sg_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => sg_1 , + q(0) => sg_0 ); + + + lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map ( + clkoff_b => clkoff_b, + thold => thold_0, + sg => sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => thold_0_b ); + + ex5_lcb : tri_lcbnd generic map (expand_type => expand_type) port map( + delay_lclkr => delay_lclkr(5) , + mpw1_b => mpw1_b(5) , + mpw2_b => mpw2_b(1) , + forcee => forcee, + nclk => nclk , + vd => vdd , + gd => gnd , + act => ex4_act , + sg => sg_0 , + thold_b => thold_0_b , + d1clk => ex5_d1clk , + d2clk => ex5_d2clk , + lclk => ex5_lclk ); + + + + + + ex3_act <= not ex3_act_b ; + + act_lat: tri_rlmreg_p generic map (width=> 4, expand_type => expand_type, needs_sreset => 0) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(4) , + mpw1_b => mpw1_b(4) , + mpw2_b => mpw2_b(0) , + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => fpu_enable, + scout => act_so (0 to 3), + scin => act_si (0 to 3), + din(0) => act_spare_unused(0), + din(1) => act_spare_unused(1), + din(2) => ex3_act, + din(3) => act_spare_unused(2), + dout(0) => act_spare_unused(0), + dout(1) => act_spare_unused(1), + dout(2) => ex4_act, + dout(3) => act_spare_unused(2) ); + + + sh: entity work.fuq_nrm_sh(fuq_nrm_sh) generic map (expand_type => expand_type) port map( + f_lza_ex4_sh_rgt_en => f_lza_ex4_sh_rgt_en , + f_lza_ex4_lza_amt_cp1(2 to 7) => f_lza_ex4_lza_amt_cp1(2 to 7) , + f_lza_ex4_lza_dcd64_cp1(0 to 2) => f_lza_ex4_lza_dcd64_cp1(0 to 2) , + f_lza_ex4_lza_dcd64_cp2(0 to 1) => f_lza_ex4_lza_dcd64_cp2(0 to 1) , + f_lza_ex4_lza_dcd64_cp3(0 to 0) => f_lza_ex4_lza_dcd64_cp3(0 to 0) , + f_add_ex4_res(0 to 162) => f_add_ex4_res(0 to 162) , + ex4_shift_extra_cp1 => f_nrm_ex4_extra_shift , + ex4_shift_extra_cp2 => ex4_shift_extra_cp2 , + ex4_sh4_25 => ex4_sh4_25 , + ex4_sh4_54 => ex4_sh4_54 , + ex4_sh2_o(26 to 72) => ex4_sh2(26 to 72) , + ex4_sh5_x_b(0 to 53) => ex4_sh5_x_b(0 to 53) , + ex4_sh5_y_b(0 to 53) => ex4_sh5_y_b(0 to 53) ); + + ex4_nrm_res(0 to 53) <= not( ex4_sh5_x_b(0 to 53) and ex4_sh5_y_b(0 to 53) ) ; + + + + ex4_lt064_x <= not( f_lza_ex4_lza_amt_cp1(0) or f_lza_ex4_lza_amt_cp1(1) ); + ex4_lt128_x <= not( f_lza_ex4_lza_amt_cp1(0) ); + + ex4_lt016_x <= not( f_lza_ex4_lza_amt_cp1(2) or f_lza_ex4_lza_amt_cp1(3) ); + ex4_lt032_x <= not( f_lza_ex4_lza_amt_cp1(2) ); + ex4_lt048_x <= not( f_lza_ex4_lza_amt_cp1(2) and f_lza_ex4_lza_amt_cp1(3) ); + + ex4_lt016 <= ex4_lt064_x and ex4_lt016_x ; + ex4_lt032 <= ex4_lt064_x and ex4_lt032_x ; + ex4_lt048 <= ex4_lt064_x and ex4_lt048_x ; + ex4_lt064 <= ex4_lt064_x ; + ex4_lt080 <= ex4_lt064_x or (ex4_lt128_x and ex4_lt016_x); + ex4_lt096 <= ex4_lt064_x or (ex4_lt128_x and ex4_lt032_x); + ex4_lt112 <= ex4_lt064_x or (ex4_lt128_x and ex4_lt048_x); + ex4_lt128 <= ex4_lt128_x ; + + + + + + + ex4_rgt_2more <= f_lza_ex4_sh_rgt_en and ( not f_lza_ex4_lza_amt_cp1(2) or not f_lza_ex4_lza_amt_cp1(3) ); + ex4_rgt_3more <= f_lza_ex4_sh_rgt_en and ( not f_lza_ex4_lza_amt_cp1(2) ); + ex4_rgt_4more <= f_lza_ex4_sh_rgt_en and ( not f_lza_ex4_lza_amt_cp1(2) and not f_lza_ex4_lza_amt_cp1(3) ); + + + + + or16: entity work.fuq_nrm_or16(fuq_nrm_or16) generic map (expand_type => expand_type) port map( + f_add_ex4_res(0 to 162) => f_add_ex4_res(0 to 162) , + ex4_or_grp16(0 to 10) => ex4_or_grp16(0 to 10) ); + + + + + ex4_sticky_stuff <= + ( f_pic_ex4_byp_prod_nz ) or + ( f_add_ex4_sticky ) ; + + ex4_sticky16_dp <= + ( ex4_or_grp16(1) and ex4_rgt_4more ) or + ( ex4_or_grp16(2) and ex4_rgt_3more ) or + ( ex4_or_grp16(3) and ex4_rgt_2more ) or + ( ex4_or_grp16(4) and f_lza_ex4_sh_rgt_en ) or + ( ex4_or_grp16(5) and (ex4_lt016 or f_lza_ex4_sh_rgt_en) ) or + ( ex4_or_grp16(6) and (ex4_lt032 or f_lza_ex4_sh_rgt_en) ) or + ( ex4_or_grp16(7) and (ex4_lt048 or f_lza_ex4_sh_rgt_en) ) or + ( ex4_or_grp16(8) and (ex4_lt064 or f_lza_ex4_sh_rgt_en) ) or + ( ex4_or_grp16(9) and (ex4_lt080 or f_lza_ex4_sh_rgt_en) ) or + ( ex4_or_grp16(10) and (ex4_lt096 or f_lza_ex4_sh_rgt_en) ) or + ( ex4_sh2(70) ) or + ( ex4_sh2(71) ) or + ( ex4_sh2(72) ) or + ( ex4_sticky_stuff ) ; + + ex4_sticky16_sp <= + ( ex4_or_grp16(0) and ex4_rgt_3more ) or + ( ex4_or_grp16(1) and ex4_rgt_2more ) or + ( ex4_or_grp16(2) and f_lza_ex4_sh_rgt_en ) or + ( ex4_or_grp16(3) and (ex4_lt016 or f_lza_ex4_sh_rgt_en) ) or + ( ex4_or_grp16(4) and (ex4_lt032 or f_lza_ex4_sh_rgt_en) ) or + ( ex4_or_grp16(5) and (ex4_lt048 or f_lza_ex4_sh_rgt_en) ) or + ( ex4_or_grp16(6) and (ex4_lt064 or f_lza_ex4_sh_rgt_en) ) or + ( ex4_or_grp16(7) and (ex4_lt080 or f_lza_ex4_sh_rgt_en) ) or + ( ex4_or_grp16(8) and (ex4_lt096 or f_lza_ex4_sh_rgt_en) ) or + ( ex4_or_grp16(9) and (ex4_lt112 or f_lza_ex4_sh_rgt_en) ) or + ( ex4_or_grp16(10) and (ex4_lt128 or f_lza_ex4_sh_rgt_en) ) or + ( ex4_sticky_stuff ) ; + + ex4_exact_zero_b <= + ex4_or_grp16(0) or + ex4_or_grp16(1) or + ex4_or_grp16(2) or + ex4_or_grp16(3) or + ex4_or_grp16(4) or + ex4_or_grp16(5) or + ex4_or_grp16(6) or + ex4_or_grp16(7) or + ex4_or_grp16(8) or + ex4_or_grp16(9) or + ex4_or_grp16(10) or + ( ex4_sticky_stuff ) ; + + + ex4_exact_zero <= not ex4_exact_zero_b ; + + + ex4_lt04_x <= not( f_lza_ex4_lza_amt_cp1(4) or f_lza_ex4_lza_amt_cp1(5) ); + ex4_lt08_x <= not( f_lza_ex4_lza_amt_cp1(4) ); + ex4_lt12_x <= not( f_lza_ex4_lza_amt_cp1(4) and f_lza_ex4_lza_amt_cp1(5) ); + + ex4_lt01_x <= not( f_lza_ex4_lza_amt_cp1(6) or f_lza_ex4_lza_amt_cp1(7) ); + ex4_lt02_x <= not( f_lza_ex4_lza_amt_cp1(6) ); + ex4_lt03_x <= not( f_lza_ex4_lza_amt_cp1(6) and f_lza_ex4_lza_amt_cp1(7) ); + + ex4_lt(0) <= ex4_lt04_x and ex4_lt01_x ; + ex4_lt(1) <= ex4_lt04_x and ex4_lt02_x ; + ex4_lt(2) <= ex4_lt04_x and ex4_lt03_x ; + ex4_lt(3) <= ex4_lt04_x ; + + ex4_lt(4) <= ex4_lt04_x or (ex4_lt08_x and ex4_lt01_x); + ex4_lt(5) <= ex4_lt04_x or (ex4_lt08_x and ex4_lt02_x); + ex4_lt(6) <= ex4_lt04_x or (ex4_lt08_x and ex4_lt03_x); + ex4_lt(7) <= (ex4_lt08_x ); + + ex4_lt(8) <= ex4_lt08_x or (ex4_lt12_x and ex4_lt01_x); + ex4_lt(9) <= ex4_lt08_x or (ex4_lt12_x and ex4_lt02_x); + ex4_lt(10) <= ex4_lt08_x or (ex4_lt12_x and ex4_lt03_x); + ex4_lt(11) <= (ex4_lt12_x ); + + ex4_lt(12) <= ex4_lt12_x or ex4_lt01_x ; + ex4_lt(13) <= ex4_lt12_x or ex4_lt02_x ; + ex4_lt(14) <= ex4_lt12_x or ex4_lt03_x ; + + + ex4_sticky_sp_x1 <= + (ex4_lt(14) and ex4_sh2(40) ) or + (ex4_lt(13) and ex4_sh2(39) ) or + (ex4_lt(12) and ex4_sh2(38) ) or + (ex4_lt(11) and ex4_sh2(37) ) or + (ex4_lt(10) and ex4_sh2(36) ) or + (ex4_lt(9) and ex4_sh2(35) ) or + (ex4_lt(8) and ex4_sh2(34) ) or + (ex4_lt(7) and ex4_sh2(33) ) or + (ex4_lt(6) and ex4_sh2(32) ) or + (ex4_lt(5) and ex4_sh2(31) ) or + (ex4_lt(4) and ex4_sh2(30) ) or + (ex4_lt(3) and ex4_sh2(29) ) or + (ex4_lt(2) and ex4_sh2(28) ) or + (ex4_lt(1) and ex4_sh2(27) ) or + (ex4_lt(0) and ex4_sh2(26) ) or + (ex4_sticky16_sp ) ; + + + ex4_sticky_sp_x2_b <= not(not ex4_shift_extra_cp2 and ex4_sh4_25 ); + ex4_sticky_sp_x1_b <= not ex4_sticky_sp_x1 ; + ex4_sticky_sp <= not( ex4_sticky_sp_x1_b and ex4_sticky_sp_x2_b ); + + + + + ex4_sticky_dp_x1 <= + (ex4_lt(14) and ex4_sh2(69) ) or + (ex4_lt(13) and ex4_sh2(68) ) or + (ex4_lt(12) and ex4_sh2(67) ) or + (ex4_lt(11) and ex4_sh2(66) ) or + (ex4_lt(10) and ex4_sh2(65) ) or + (ex4_lt(9) and ex4_sh2(64) ) or + (ex4_lt(8) and ex4_sh2(63) ) or + (ex4_lt(7) and ex4_sh2(62) ) or + (ex4_lt(6) and ex4_sh2(61) ) or + (ex4_lt(5) and ex4_sh2(60) ) or + (ex4_lt(4) and ex4_sh2(59) ) or + (ex4_lt(3) and ex4_sh2(58) ) or + (ex4_lt(2) and ex4_sh2(57) ) or + (ex4_lt(1) and ex4_sh2(56) ) or + (ex4_lt(0) and ex4_sh2(55) ) or + (ex4_sticky16_dp ) ; + + ex4_sticky_dp_x2_b <= not(not ex4_shift_extra_cp2 and ex4_sh4_54 ) ; + ex4_sticky_dp_x1_b <= not ex4_sticky_dp_x1 ; + ex4_sticky_dp <= not( ex4_sticky_dp_x1_b and ex4_sticky_dp_x2_b ); + + + + + + ex5_res_lat: entity tri.tri_nand2_nlats(tri_nand2_nlats) generic map (width=> 53, btr => "NLA0001_X1_A12TH", expand_type => expand_type, needs_sreset => 0) port map ( + vd => vdd, + gd => gnd, + LCLK => ex5_lclk , + D1CLK => ex5_d1clk , + D2CLK => ex5_d2clk , + SCANIN => ex5_res_si , + SCANOUT => ex5_res_so , + A1 => ex4_sh5_x_b(0 to 52) , + A2 => ex4_sh5_y_b(0 to 52) , + QB => ex5_res(0 to 52) ); + + ex5_nrm_lg_lat: entity tri.tri_nand2_nlats(tri_nand2_nlats) generic map (width=> 4, btr => "NLA0001_X1_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd, + gd => gnd, + LCLK => ex5_lclk , + D1CLK => ex5_d1clk , + D2CLK => ex5_d2clk , + SCANIN => ex5_nrm_lg_si , + SCANOUT => ex5_nrm_lg_so , + A1(0) => ex4_sh5_x_b(23) , + A1(1) => ex4_sh5_x_b(24) , + A1(2) => ex4_sh5_x_b(52) , + A1(3) => ex4_sh5_x_b(53) , + A2(0) => ex4_sh5_y_b(23) , + A2(1) => ex4_sh5_y_b(24) , + A2(2) => ex4_sh5_y_b(52) , + A2(3) => ex4_sh5_y_b(53) , + QB(0) => ex5_nrm_lsb_sp , + QB(1) => ex5_nrm_guard_sp , + QB(2) => ex5_nrm_lsb_dp , + QB(3) => ex5_nrm_guard_dp ); + + + + + + ex5_nrm_x_lat: entity tri.tri_nand2_nlats(tri_nand2_nlats) generic map (width=> 3, btr => "NLA0001_X1_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd, + gd => gnd, + LCLK => ex5_lclk , + D1CLK => ex5_d1clk , + D2CLK => ex5_d2clk , + SCANIN => ex5_nrm_x_si , + SCANOUT => ex5_nrm_x_so , + A1(0) => ex4_sticky_sp_x2_b , + A1(1) => ex4_sticky_dp_x2_b , + A1(2) => ex4_exact_zero_b , + A2(0) => ex4_sticky_sp_x1_b , + A2(1) => ex4_sticky_dp_x1_b , + A2(2) => tiup , + QB(0) => ex5_nrm_sticky_sp , + QB(1) => ex5_nrm_sticky_dp , + QB(2) => ex5_exact_zero ); + + ex5_nrm_pass_lat: tri_rlmreg_p generic map (width=> 13, expand_type => expand_type, ibuf => true, needs_sreset => 0) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(5) , + mpw1_b => mpw1_b(5) , + mpw2_b => mpw2_b(1) , + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => ex4_act, + scout => ex5_nrm_pass_so, + scin => ex5_nrm_pass_si, + din(0) => f_add_ex4_res(99) , + din(1 to 12) => f_add_ex4_res(151 to 162) , + dout(0) => ex5_int_sign , + dout(1 to 12) => ex5_int_lsbs (1 to 12) ); + + ex5_fmv_lat: tri_rlmreg_p generic map (width=> 36, expand_type => expand_type, ibuf => true, needs_sreset => 1) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(5) , + mpw1_b => mpw1_b(5) , + mpw2_b => mpw2_b(1) , + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => ex4_act, + scout => ex5_fmv_so , + scin => ex5_fmv_si , + din => f_add_ex4_res(17 to 52) , + dout(0 to 3) => ex5_fpscr_wr_dat_dfp(0 to 3) , + dout(4 to 35) => ex5_fpscr_wr_dat(0 to 31) ); + + + + f_nrm_ex5_res <= ex5_res(0 to 52) ; + f_nrm_ex5_nrm_lsb_sp <= ex5_nrm_lsb_sp ; + f_nrm_ex5_nrm_guard_sp <= ex5_nrm_guard_sp ; + f_nrm_ex5_nrm_sticky_sp <= ex5_nrm_sticky_sp ; + f_nrm_ex5_nrm_lsb_dp <= ex5_nrm_lsb_dp ; + f_nrm_ex5_nrm_guard_dp <= ex5_nrm_guard_dp ; + f_nrm_ex5_nrm_sticky_dp <= ex5_nrm_sticky_dp ; + f_nrm_ex5_exact_zero <= ex5_exact_zero ; + f_nrm_ex5_int_lsbs <= ex5_int_lsbs (1 to 12) ; + f_nrm_ex5_fpscr_wr_dat <= ex5_fpscr_wr_dat(0 to 31) ; + f_nrm_ex5_fpscr_wr_dat_dfp <= ex5_fpscr_wr_dat_dfp(0 to 3) ; + f_nrm_ex5_int_sign <= ex5_int_sign ; + + + + act_si (0 to 3) <= act_so (1 to 3) & f_nrm_si; + ex5_res_si (0 to 52) <= ex5_res_so (1 to 52) & act_so(0) ; + ex5_nrm_lg_si(0 to 3) <= ex5_nrm_lg_so(1 to 3) & ex5_res_so(0); + ex5_nrm_x_si(0 to 2) <= ex5_nrm_x_so(1 to 2) & ex5_nrm_lg_so(0); + ex5_nrm_pass_si(0 to 12) <= ex5_nrm_pass_so(1 to 12) & ex5_nrm_x_so(0); + ex5_fmv_si (0 to 35) <= ex5_fmv_so (1 to 35) & ex5_nrm_pass_so(0); + f_nrm_so <= ex5_fmv_so (0) ; + + + +end; + + + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_nrm_or16.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_nrm_or16.vhdl new file mode 100644 index 0000000..a3891c3 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_nrm_or16.vhdl @@ -0,0 +1,327 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + + +entity fuq_nrm_or16 is +generic( expand_type : integer := 2 ); +port( + f_add_ex4_res :in std_ulogic_vector(0 to 162) ; + ex4_or_grp16 :out std_ulogic_vector(0 to 10) +); + + + +end fuq_nrm_or16; + +architecture fuq_nrm_or16 of fuq_nrm_or16 is + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + +signal ex4_res_b :std_ulogic_vector(0 to 162); +signal g00_or02 :std_ulogic_vector(0 to 3); +signal g01_or02, g02_or02, g03_or02, g04_or02, g05_or02, g06_or02, g07_or02, g08_or02, g09_or02 :std_ulogic_vector(0 to 7); +signal g10_or02 :std_ulogic_vector(0 to 5); + +signal g00_or04_b :std_ulogic_vector(0 to 1); +signal g01_or04_b :std_ulogic_vector(0 to 3); +signal g02_or04_b :std_ulogic_vector(0 to 3); +signal g03_or04_b :std_ulogic_vector(0 to 3); +signal g04_or04_b :std_ulogic_vector(0 to 3); +signal g05_or04_b :std_ulogic_vector(0 to 3); +signal g06_or04_b :std_ulogic_vector(0 to 3); +signal g07_or04_b :std_ulogic_vector(0 to 3); +signal g08_or04_b :std_ulogic_vector(0 to 3); +signal g09_or04_b :std_ulogic_vector(0 to 3); +signal g10_or04_b :std_ulogic_vector(0 to 2); + + +signal g00_or08 :std_ulogic_vector(0 to 0); +signal g01_or08 :std_ulogic_vector(0 to 1); +signal g02_or08 :std_ulogic_vector(0 to 1); +signal g03_or08 :std_ulogic_vector(0 to 1); +signal g04_or08 :std_ulogic_vector(0 to 1); +signal g05_or08 :std_ulogic_vector(0 to 1); +signal g06_or08 :std_ulogic_vector(0 to 1); +signal g07_or08 :std_ulogic_vector(0 to 1); +signal g08_or08 :std_ulogic_vector(0 to 1); +signal g09_or08 :std_ulogic_vector(0 to 1); +signal g10_or08 :std_ulogic_vector(0 to 1); + +signal g00_or16_b :std_ulogic ; +signal g01_or16_b :std_ulogic ; +signal g02_or16_b :std_ulogic ; +signal g03_or16_b :std_ulogic ; +signal g04_or16_b :std_ulogic ; +signal g05_or16_b :std_ulogic ; +signal g06_or16_b :std_ulogic ; +signal g07_or16_b :std_ulogic ; +signal g08_or16_b :std_ulogic ; +signal g09_or16_b :std_ulogic ; +signal g10_or16_b :std_ulogic ; + + + + + + + + + +begin + + + +u_or_inv: ex4_res_b(0 to 162) <= not f_add_ex4_res(0 to 162); + + + +u_g00_or02_0: g00_or02(0) <= not( ex4_res_b( 0) and ex4_res_b( 1) ); +u_g00_or02_1: g00_or02(1) <= not( ex4_res_b( 2) and ex4_res_b( 3) ); +u_g00_or02_2: g00_or02(2) <= not( ex4_res_b( 4) and ex4_res_b( 5) ); +u_g00_or02_3: g00_or02(3) <= not( ex4_res_b( 6) and ex4_res_b( 7) ); + +u_g01_or02_0: g01_or02(0) <= not( ex4_res_b( 8) and ex4_res_b( 9) ); +u_g01_or02_1: g01_or02(1) <= not( ex4_res_b( 10) and ex4_res_b( 11) ); +u_g01_or02_2: g01_or02(2) <= not( ex4_res_b( 12) and ex4_res_b( 13) ); +u_g01_or02_3: g01_or02(3) <= not( ex4_res_b( 14) and ex4_res_b( 15) ); +u_g01_or02_4: g01_or02(4) <= not( ex4_res_b( 16) and ex4_res_b( 17) ); +u_g01_or02_5: g01_or02(5) <= not( ex4_res_b( 18) and ex4_res_b( 19) ); +u_g01_or02_6: g01_or02(6) <= not( ex4_res_b( 20) and ex4_res_b( 21) ); +u_g01_or02_7: g01_or02(7) <= not( ex4_res_b( 22) and ex4_res_b( 23) ); + +u_g02_or02_0: g02_or02(0) <= not( ex4_res_b( 24) and ex4_res_b( 25) ); +u_g02_or02_1: g02_or02(1) <= not( ex4_res_b( 26) and ex4_res_b( 27) ); +u_g02_or02_2: g02_or02(2) <= not( ex4_res_b( 28) and ex4_res_b( 29) ); +u_g02_or02_3: g02_or02(3) <= not( ex4_res_b( 30) and ex4_res_b( 31) ); +u_g02_or02_4: g02_or02(4) <= not( ex4_res_b( 32) and ex4_res_b( 33) ); +u_g02_or02_5: g02_or02(5) <= not( ex4_res_b( 34) and ex4_res_b( 35) ); +u_g02_or02_6: g02_or02(6) <= not( ex4_res_b( 36) and ex4_res_b( 37) ); +u_g02_or02_7: g02_or02(7) <= not( ex4_res_b( 38) and ex4_res_b( 39) ); + +u_g03_or02_0: g03_or02(0) <= not( ex4_res_b( 40) and ex4_res_b( 41) ); +u_g03_or02_1: g03_or02(1) <= not( ex4_res_b( 42) and ex4_res_b( 43) ); +u_g03_or02_2: g03_or02(2) <= not( ex4_res_b( 44) and ex4_res_b( 45) ); +u_g03_or02_3: g03_or02(3) <= not( ex4_res_b( 46) and ex4_res_b( 47) ); +u_g03_or02_4: g03_or02(4) <= not( ex4_res_b( 48) and ex4_res_b( 49) ); +u_g03_or02_5: g03_or02(5) <= not( ex4_res_b( 50) and ex4_res_b( 51) ); +u_g03_or02_6: g03_or02(6) <= not( ex4_res_b( 52) and ex4_res_b( 53) ); +u_g03_or02_7: g03_or02(7) <= not( ex4_res_b( 54) and ex4_res_b( 55) ); + +u_g04_or02_0: g04_or02(0) <= not( ex4_res_b( 56) and ex4_res_b( 57) ); +u_g04_or02_1: g04_or02(1) <= not( ex4_res_b( 58) and ex4_res_b( 59) ); +u_g04_or02_2: g04_or02(2) <= not( ex4_res_b( 60) and ex4_res_b( 61) ); +u_g04_or02_3: g04_or02(3) <= not( ex4_res_b( 62) and ex4_res_b( 63) ); +u_g04_or02_4: g04_or02(4) <= not( ex4_res_b( 64) and ex4_res_b( 65) ); +u_g04_or02_5: g04_or02(5) <= not( ex4_res_b( 66) and ex4_res_b( 67) ); +u_g04_or02_6: g04_or02(6) <= not( ex4_res_b( 68) and ex4_res_b( 69) ); +u_g04_or02_7: g04_or02(7) <= not( ex4_res_b( 70) and ex4_res_b( 71) ); + +u_g05_or02_0: g05_or02(0) <= not( ex4_res_b( 72) and ex4_res_b( 73) ); +u_g05_or02_1: g05_or02(1) <= not( ex4_res_b( 74) and ex4_res_b( 75) ); +u_g05_or02_2: g05_or02(2) <= not( ex4_res_b( 76) and ex4_res_b( 77) ); +u_g05_or02_3: g05_or02(3) <= not( ex4_res_b( 78) and ex4_res_b( 79) ); +u_g05_or02_4: g05_or02(4) <= not( ex4_res_b( 80) and ex4_res_b( 81) ); +u_g05_or02_5: g05_or02(5) <= not( ex4_res_b( 82) and ex4_res_b( 83) ); +u_g05_or02_6: g05_or02(6) <= not( ex4_res_b( 84) and ex4_res_b( 85) ); +u_g05_or02_7: g05_or02(7) <= not( ex4_res_b( 86) and ex4_res_b( 87) ); + +u_g06_or02_0: g06_or02(0) <= not( ex4_res_b( 88) and ex4_res_b( 89) ); +u_g06_or02_1: g06_or02(1) <= not( ex4_res_b( 90) and ex4_res_b( 91) ); +u_g06_or02_2: g06_or02(2) <= not( ex4_res_b( 92) and ex4_res_b( 93) ); +u_g06_or02_3: g06_or02(3) <= not( ex4_res_b( 94) and ex4_res_b( 95) ); +u_g06_or02_4: g06_or02(4) <= not( ex4_res_b( 96) and ex4_res_b( 97) ); +u_g06_or02_5: g06_or02(5) <= not( ex4_res_b( 98) and ex4_res_b( 99) ); +u_g06_or02_6: g06_or02(6) <= not( ex4_res_b(100) and ex4_res_b(101) ); +u_g06_or02_7: g06_or02(7) <= not( ex4_res_b(102) and ex4_res_b(103) ); + +u_g07_or02_0: g07_or02(0) <= not( ex4_res_b(104) and ex4_res_b(105) ); +u_g07_or02_1: g07_or02(1) <= not( ex4_res_b(106) and ex4_res_b(107) ); +u_g07_or02_2: g07_or02(2) <= not( ex4_res_b(108) and ex4_res_b(109) ); +u_g07_or02_3: g07_or02(3) <= not( ex4_res_b(110) and ex4_res_b(111) ); +u_g07_or02_4: g07_or02(4) <= not( ex4_res_b(112) and ex4_res_b(113) ); +u_g07_or02_5: g07_or02(5) <= not( ex4_res_b(114) and ex4_res_b(115) ); +u_g07_or02_6: g07_or02(6) <= not( ex4_res_b(116) and ex4_res_b(117) ); +u_g07_or02_7: g07_or02(7) <= not( ex4_res_b(118) and ex4_res_b(119) ); + +u_g08_or02_0: g08_or02(0) <= not( ex4_res_b(120) and ex4_res_b(121) ); +u_g08_or02_1: g08_or02(1) <= not( ex4_res_b(122) and ex4_res_b(123) ); +u_g08_or02_2: g08_or02(2) <= not( ex4_res_b(124) and ex4_res_b(125) ); +u_g08_or02_3: g08_or02(3) <= not( ex4_res_b(126) and ex4_res_b(127) ); +u_g08_or02_4: g08_or02(4) <= not( ex4_res_b(128) and ex4_res_b(129) ); +u_g08_or02_5: g08_or02(5) <= not( ex4_res_b(130) and ex4_res_b(131) ); +u_g08_or02_6: g08_or02(6) <= not( ex4_res_b(132) and ex4_res_b(133) ); +u_g08_or02_7: g08_or02(7) <= not( ex4_res_b(134) and ex4_res_b(135) ); + +u_g09_or02_0: g09_or02(0) <= not( ex4_res_b(136) and ex4_res_b(137) ); +u_g09_or02_1: g09_or02(1) <= not( ex4_res_b(138) and ex4_res_b(139) ); +u_g09_or02_2: g09_or02(2) <= not( ex4_res_b(140) and ex4_res_b(141) ); +u_g09_or02_3: g09_or02(3) <= not( ex4_res_b(142) and ex4_res_b(143) ); +u_g09_or02_4: g09_or02(4) <= not( ex4_res_b(144) and ex4_res_b(145) ); +u_g09_or02_5: g09_or02(5) <= not( ex4_res_b(146) and ex4_res_b(147) ); +u_g09_or02_6: g09_or02(6) <= not( ex4_res_b(148) and ex4_res_b(149) ); +u_g09_or02_7: g09_or02(7) <= not( ex4_res_b(150) and ex4_res_b(151) ); + +u_g10_or02_0: g10_or02(0) <= not( ex4_res_b(152) and ex4_res_b(153) ); +u_g10_or02_1: g10_or02(1) <= not( ex4_res_b(154) and ex4_res_b(155) ); +u_g10_or02_2: g10_or02(2) <= not( ex4_res_b(156) and ex4_res_b(157) ); +u_g10_or02_3: g10_or02(3) <= not( ex4_res_b(158) and ex4_res_b(159) ); +u_g10_or02_4: g10_or02(4) <= not( ex4_res_b(160) and ex4_res_b(161) ); +u_g10_or02_5: g10_or02(5) <= not( ex4_res_b(162) ); + + +u_g00_or04_0: g00_or04_b(0) <= not( g00_or02(0) or g00_or02(1) ); +u_g00_or04_1: g00_or04_b(1) <= not( g00_or02(2) or g00_or02(3) ); + +u_g01_or04_0: g01_or04_b(0) <= not( g01_or02(0) or g01_or02(1) ); +u_g01_or04_1: g01_or04_b(1) <= not( g01_or02(2) or g01_or02(3) ); +u_g01_or04_2: g01_or04_b(2) <= not( g01_or02(4) or g01_or02(5) ); +u_g01_or04_3: g01_or04_b(3) <= not( g01_or02(6) or g01_or02(7) ); + +u_g02_or04_0: g02_or04_b(0) <= not( g02_or02(0) or g02_or02(1) ); +u_g02_or04_1: g02_or04_b(1) <= not( g02_or02(2) or g02_or02(3) ); +u_g02_or04_2: g02_or04_b(2) <= not( g02_or02(4) or g02_or02(5) ); +u_g02_or04_3: g02_or04_b(3) <= not( g02_or02(6) or g02_or02(7) ); + +u_g03_or04_0: g03_or04_b(0) <= not( g03_or02(0) or g03_or02(1) ); +u_g03_or04_1: g03_or04_b(1) <= not( g03_or02(2) or g03_or02(3) ); +u_g03_or04_2: g03_or04_b(2) <= not( g03_or02(4) or g03_or02(5) ); +u_g03_or04_3: g03_or04_b(3) <= not( g03_or02(6) or g03_or02(7) ); + +u_g04_or04_0: g04_or04_b(0) <= not( g04_or02(0) or g04_or02(1) ); +u_g04_or04_1: g04_or04_b(1) <= not( g04_or02(2) or g04_or02(3) ); +u_g04_or04_2: g04_or04_b(2) <= not( g04_or02(4) or g04_or02(5) ); +u_g04_or04_3: g04_or04_b(3) <= not( g04_or02(6) or g04_or02(7) ); + +u_g05_or04_0: g05_or04_b(0) <= not( g05_or02(0) or g05_or02(1) ); +u_g05_or04_1: g05_or04_b(1) <= not( g05_or02(2) or g05_or02(3) ); +u_g05_or04_2: g05_or04_b(2) <= not( g05_or02(4) or g05_or02(5) ); +u_g05_or04_3: g05_or04_b(3) <= not( g05_or02(6) or g05_or02(7) ); + +u_g06_or04_0: g06_or04_b(0) <= not( g06_or02(0) or g06_or02(1) ); +u_g06_or04_1: g06_or04_b(1) <= not( g06_or02(2) or g06_or02(3) ); +u_g06_or04_2: g06_or04_b(2) <= not( g06_or02(4) or g06_or02(5) ); +u_g06_or04_3: g06_or04_b(3) <= not( g06_or02(6) or g06_or02(7) ); + +u_g07_or04_0: g07_or04_b(0) <= not( g07_or02(0) or g07_or02(1) ); +u_g07_or04_1: g07_or04_b(1) <= not( g07_or02(2) or g07_or02(3) ); +u_g07_or04_2: g07_or04_b(2) <= not( g07_or02(4) or g07_or02(5) ); +u_g07_or04_3: g07_or04_b(3) <= not( g07_or02(6) or g07_or02(7) ); + +u_g08_or04_0: g08_or04_b(0) <= not( g08_or02(0) or g08_or02(1) ); +u_g08_or04_1: g08_or04_b(1) <= not( g08_or02(2) or g08_or02(3) ); +u_g08_or04_2: g08_or04_b(2) <= not( g08_or02(4) or g08_or02(5) ); +u_g08_or04_3: g08_or04_b(3) <= not( g08_or02(6) or g08_or02(7) ); + +u_g09_or04_0: g09_or04_b(0) <= not( g09_or02(0) or g09_or02(1) ); +u_g09_or04_1: g09_or04_b(1) <= not( g09_or02(2) or g09_or02(3) ); +u_g09_or04_2: g09_or04_b(2) <= not( g09_or02(4) or g09_or02(5) ); +u_g09_or04_3: g09_or04_b(3) <= not( g09_or02(6) or g09_or02(7) ); + +u_g10_or04_0: g10_or04_b(0) <= not( g10_or02(0) or g10_or02(1) ); +u_g10_or04_1: g10_or04_b(1) <= not( g10_or02(2) or g10_or02(3) ); +u_g10_or04_2: g10_or04_b(2) <= not( g10_or02(4) or g10_or02(5) ); + + + +u_g00_or08_0: g00_or08(0) <= not( g00_or04_b(0) and g00_or04_b(1) ); + +u_g01_or08_0: g01_or08(0) <= not( g01_or04_b(0) and g01_or04_b(1) ); +u_g01_or08_1: g01_or08(1) <= not( g01_or04_b(2) and g01_or04_b(3) ); + +u_g02_or08_0: g02_or08(0) <= not( g02_or04_b(0) and g02_or04_b(1) ); +u_g02_or08_1: g02_or08(1) <= not( g02_or04_b(2) and g02_or04_b(3) ); + +u_g03_or08_0: g03_or08(0) <= not( g03_or04_b(0) and g03_or04_b(1) ); +u_g03_or08_1: g03_or08(1) <= not( g03_or04_b(2) and g03_or04_b(3) ); + +u_g04_or08_0: g04_or08(0) <= not( g04_or04_b(0) and g04_or04_b(1) ); +u_g04_or08_1: g04_or08(1) <= not( g04_or04_b(2) and g04_or04_b(3) ); + +u_g05_or08_0: g05_or08(0) <= not( g05_or04_b(0) and g05_or04_b(1) ); +u_g05_or08_1: g05_or08(1) <= not( g05_or04_b(2) and g05_or04_b(3) ); + +u_g06_or08_0: g06_or08(0) <= not( g06_or04_b(0) and g06_or04_b(1) ); +u_g06_or08_1: g06_or08(1) <= not( g06_or04_b(2) and g06_or04_b(3) ); + +u_g07_or08_0: g07_or08(0) <= not( g07_or04_b(0) and g07_or04_b(1) ); +u_g07_or08_1: g07_or08(1) <= not( g07_or04_b(2) and g07_or04_b(3) ); + +u_g08_or08_0: g08_or08(0) <= not( g08_or04_b(0) and g08_or04_b(1) ); +u_g08_or08_1: g08_or08(1) <= not( g08_or04_b(2) and g08_or04_b(3) ); + +u_g09_or08_0: g09_or08(0) <= not( g09_or04_b(0) and g09_or04_b(1) ); +u_g09_or08_1: g09_or08(1) <= not( g09_or04_b(2) and g09_or04_b(3) ); + +u_g10_or08_0: g10_or08(0) <= not( g10_or04_b(0) and g10_or04_b(1) ); +u_g10_or08_1: g10_or08(1) <= not( g10_or04_b(2) ); + + + +u_g00_or16_0: g00_or16_b <= not( g00_or08(0) ); +u_g01_or16_0: g01_or16_b <= not( g01_or08(0) or g01_or08(1) ); +u_g02_or16_0: g02_or16_b <= not( g02_or08(0) or g02_or08(1) ); +u_g03_or16_0: g03_or16_b <= not( g03_or08(0) or g03_or08(1) ); +u_g04_or16_0: g04_or16_b <= not( g04_or08(0) or g04_or08(1) ); +u_g05_or16_0: g05_or16_b <= not( g05_or08(0) or g05_or08(1) ); +u_g06_or16_0: g06_or16_b <= not( g06_or08(0) or g06_or08(1) ); +u_g07_or16_0: g07_or16_b <= not( g07_or08(0) or g07_or08(1) ); +u_g08_or16_0: g08_or16_b <= not( g08_or08(0) or g08_or08(1) ); +u_g09_or16_0: g09_or16_b <= not( g09_or08(0) or g09_or08(1) ); +u_g10_or16_0: g10_or16_b <= not( g10_or08(0) or g10_or08(1) ); + + + + +u_g00_drv: ex4_or_grp16(0) <= not( g00_or16_b ); +u_g01_drv: ex4_or_grp16(1) <= not( g01_or16_b ); +u_g02_drv: ex4_or_grp16(2) <= not( g02_or16_b ); +u_g03_drv: ex4_or_grp16(3) <= not( g03_or16_b ); +u_g04_drv: ex4_or_grp16(4) <= not( g04_or16_b ); +u_g05_drv: ex4_or_grp16(5) <= not( g05_or16_b ); +u_g06_drv: ex4_or_grp16(6) <= not( g06_or16_b ); +u_g07_drv: ex4_or_grp16(7) <= not( g07_or16_b ); +u_g08_drv: ex4_or_grp16(8) <= not( g08_or16_b ); +u_g09_drv: ex4_or_grp16(9) <= not( g09_or16_b ); +u_g10_drv: ex4_or_grp16(10) <= not( g10_or16_b ); + +end; + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_nrm_sh.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_nrm_sh.vhdl new file mode 100644 index 0000000..e3493e8 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_nrm_sh.vhdl @@ -0,0 +1,1346 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + + +entity fuq_nrm_sh is +generic( expand_type : integer := 2 ); +port( + f_lza_ex4_sh_rgt_en :in std_ulogic; + f_lza_ex4_lza_amt_cp1 :in std_ulogic_vector(2 to 7) ; + f_lza_ex4_lza_dcd64_cp1 :in std_ulogic_vector(0 to 2) ; + f_lza_ex4_lza_dcd64_cp2 :in std_ulogic_vector(0 to 1) ; + f_lza_ex4_lza_dcd64_cp3 :in std_ulogic_vector(0 to 0) ; + + f_add_ex4_res :in std_ulogic_vector(0 to 162) ; + + ex4_sh2_o :out std_ulogic_vector(26 to 72); + ex4_sh4_25 :out std_ulogic; + ex4_sh4_54 :out std_ulogic; + ex4_shift_extra_cp1 :out std_ulogic ; + ex4_shift_extra_cp2 :out std_ulogic ; + ex4_sh5_x_b :out std_ulogic_vector(0 to 53); + ex4_sh5_y_b :out std_ulogic_vector(0 to 53) +); + + + + + +end fuq_nrm_sh; + +architecture fuq_nrm_sh of fuq_nrm_sh is + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal ex4_sh1_x_b :std_ulogic_vector(0 to 120); + signal ex4_sh1_y_b :std_ulogic_vector(0 to 99); + signal ex4_sh1_u_b :std_ulogic_vector(0 to 35); + signal ex4_sh1_z_b :std_ulogic_vector(65 to 118); + signal ex4_sh2_x_b, ex4_sh2_y_b :std_ulogic_vector(0 to 72); + signal ex4_sh3_x_b, ex4_sh3_y_b :std_ulogic_vector(0 to 57); + signal ex4_sh4_x_b, ex4_sh4_y_b :std_ulogic_vector(0 to 54); + signal ex4_sh4_x_00_b, ex4_sh4_y_00_b :std_ulogic; + signal ex4_shift_extra_cp1_b :std_ulogic ; + signal ex4_shift_extra_cp2_b :std_ulogic ; + signal ex4_shift_extra_cp3_b :std_ulogic ; + signal ex4_shift_extra_cp4_b :std_ulogic ; + signal ex4_shift_extra_cp3 :std_ulogic ; + signal ex4_shift_extra_cp4 :std_ulogic ; + signal ex4_sh4 :std_ulogic_vector(0 to 54); + signal ex4_sh3 :std_ulogic_vector(0 to 57); + signal ex4_sh2 :std_ulogic_vector(0 to 72); + signal ex4_sh1 :std_ulogic_vector(0 to 120); + signal ex4_shctl_64 :std_ulogic_vector(0 to 2); + signal ex4_shctl_64_cp2 :std_ulogic_vector(0 to 1); + signal ex4_shctl_64_cp3 :std_ulogic_vector(0 to 0); + signal ex4_shctl_16 :std_ulogic_vector(0 to 3); + signal ex4_shctl_04 :std_ulogic_vector(0 to 3); + signal ex4_shctl_01 :std_ulogic_vector(0 to 3); + signal ex4_shift_extra_10_cp3 :std_ulogic; + signal ex4_shift_extra_20_cp3_b :std_ulogic; + signal ex4_shift_extra_11_cp3 :std_ulogic; + signal ex4_shift_extra_21_cp3_b :std_ulogic; + signal ex4_shift_extra_31_cp3 :std_ulogic; + signal ex4_shift_extra_10_cp4 :std_ulogic; + signal ex4_shift_extra_20_cp4_b :std_ulogic; + signal ex4_shift_extra_11_cp4 :std_ulogic; + signal ex4_shift_extra_21_cp4_b :std_ulogic; + signal ex4_shift_extra_31_cp4 :std_ulogic; + signal ex4_shift_extra_00_cp3_b :std_ulogic; + signal ex4_shift_extra_00_cp4_b :std_ulogic; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +begin + + + + ex4_shctl_64(0 to 2) <= f_lza_ex4_lza_dcd64_cp1(0 to 2) ; + ex4_shctl_64_cp2(0 to 1) <= f_lza_ex4_lza_dcd64_cp2(0 to 1) ; + ex4_shctl_64_cp3(0) <= f_lza_ex4_lza_dcd64_cp3(0) ; + + ex4_shctl_16(0) <= not f_lza_ex4_lza_amt_cp1(2) and not f_lza_ex4_lza_amt_cp1(3) ; + ex4_shctl_16(1) <= not f_lza_ex4_lza_amt_cp1(2) and f_lza_ex4_lza_amt_cp1(3) ; + ex4_shctl_16(2) <= f_lza_ex4_lza_amt_cp1(2) and not f_lza_ex4_lza_amt_cp1(3) ; + ex4_shctl_16(3) <= f_lza_ex4_lza_amt_cp1(2) and f_lza_ex4_lza_amt_cp1(3) ; + + ex4_shctl_04(0) <= not f_lza_ex4_lza_amt_cp1(4) and not f_lza_ex4_lza_amt_cp1(5) ; + ex4_shctl_04(1) <= not f_lza_ex4_lza_amt_cp1(4) and f_lza_ex4_lza_amt_cp1(5) ; + ex4_shctl_04(2) <= f_lza_ex4_lza_amt_cp1(4) and not f_lza_ex4_lza_amt_cp1(5) ; + ex4_shctl_04(3) <= f_lza_ex4_lza_amt_cp1(4) and f_lza_ex4_lza_amt_cp1(5) ; + + ex4_shctl_01(0) <= not f_lza_ex4_lza_amt_cp1(6) and not f_lza_ex4_lza_amt_cp1(7) ; + ex4_shctl_01(1) <= not f_lza_ex4_lza_amt_cp1(6) and f_lza_ex4_lza_amt_cp1(7) ; + ex4_shctl_01(2) <= f_lza_ex4_lza_amt_cp1(6) and not f_lza_ex4_lza_amt_cp1(7) ; + ex4_shctl_01(3) <= f_lza_ex4_lza_amt_cp1(6) and f_lza_ex4_lza_amt_cp1(7) ; + + + ex4_sh2_o(26 to 72) <= ex4_sh2(26 to 72); + + + ex4_sh4_25 <= ex4_sh4(25) ; + ex4_sh4_54 <= ex4_sh4(54) ; + + + + +u_sh1x_000: ex4_sh1_x_b( 0) <= not( tidn and ex4_shctl_64(0) ); +u_sh1x_001: ex4_sh1_x_b( 1) <= not( f_add_ex4_res( 0) and ex4_shctl_64(0) ); +u_sh1x_002: ex4_sh1_x_b( 2) <= not( f_add_ex4_res( 1) and ex4_shctl_64(0) ); +u_sh1x_003: ex4_sh1_x_b( 3) <= not( f_add_ex4_res( 2) and ex4_shctl_64(0) ); +u_sh1x_004: ex4_sh1_x_b( 4) <= not( f_add_ex4_res( 3) and ex4_shctl_64(0) ); +u_sh1x_005: ex4_sh1_x_b( 5) <= not( f_add_ex4_res( 4) and ex4_shctl_64(0) ); +u_sh1x_006: ex4_sh1_x_b( 6) <= not( f_add_ex4_res( 5) and ex4_shctl_64(0) ); +u_sh1x_007: ex4_sh1_x_b( 7) <= not( f_add_ex4_res( 6) and ex4_shctl_64(0) ); +u_sh1x_008: ex4_sh1_x_b( 8) <= not( f_add_ex4_res( 7) and ex4_shctl_64(0) ); +u_sh1x_009: ex4_sh1_x_b( 9) <= not( f_add_ex4_res( 8) and ex4_shctl_64(0) ); +u_sh1x_010: ex4_sh1_x_b( 10) <= not( f_add_ex4_res( 9) and ex4_shctl_64(0) ); +u_sh1x_011: ex4_sh1_x_b( 11) <= not( f_add_ex4_res( 10) and ex4_shctl_64(0) ); +u_sh1x_012: ex4_sh1_x_b( 12) <= not( f_add_ex4_res( 11) and ex4_shctl_64(0) ); +u_sh1x_013: ex4_sh1_x_b( 13) <= not( f_add_ex4_res( 12) and ex4_shctl_64(0) ); +u_sh1x_014: ex4_sh1_x_b( 14) <= not( f_add_ex4_res( 13) and ex4_shctl_64(0) ); +u_sh1x_015: ex4_sh1_x_b( 15) <= not( f_add_ex4_res( 14) and ex4_shctl_64(0) ); +u_sh1x_016: ex4_sh1_x_b( 16) <= not( f_add_ex4_res( 15) and ex4_shctl_64(0) ); +u_sh1x_017: ex4_sh1_x_b( 17) <= not( f_add_ex4_res( 16) and ex4_shctl_64(0) ); +u_sh1x_018: ex4_sh1_x_b( 18) <= not( f_add_ex4_res( 17) and ex4_shctl_64(0) ); +u_sh1x_019: ex4_sh1_x_b( 19) <= not( f_add_ex4_res( 18) and ex4_shctl_64(0) ); +u_sh1x_020: ex4_sh1_x_b( 20) <= not( f_add_ex4_res( 19) and ex4_shctl_64(0) ); +u_sh1x_021: ex4_sh1_x_b( 21) <= not( f_add_ex4_res( 20) and ex4_shctl_64(0) ); +u_sh1x_022: ex4_sh1_x_b( 22) <= not( f_add_ex4_res( 21) and ex4_shctl_64(0) ); +u_sh1x_023: ex4_sh1_x_b( 23) <= not( f_add_ex4_res( 22) and ex4_shctl_64(0) ); +u_sh1x_024: ex4_sh1_x_b( 24) <= not( f_add_ex4_res( 23) and ex4_shctl_64(0) ); +u_sh1x_025: ex4_sh1_x_b( 25) <= not( f_add_ex4_res( 24) and ex4_shctl_64(0) ); +u_sh1x_026: ex4_sh1_x_b( 26) <= not( f_add_ex4_res( 25) and ex4_shctl_64(0) ); +u_sh1x_027: ex4_sh1_x_b( 27) <= not( f_add_ex4_res( 26) and ex4_shctl_64(0) ); +u_sh1x_028: ex4_sh1_x_b( 28) <= not( f_add_ex4_res( 27) and ex4_shctl_64(0) ); +u_sh1x_029: ex4_sh1_x_b( 29) <= not( f_add_ex4_res( 28) and ex4_shctl_64(0) ); +u_sh1x_030: ex4_sh1_x_b( 30) <= not( f_add_ex4_res( 29) and ex4_shctl_64(0) ); +u_sh1x_031: ex4_sh1_x_b( 31) <= not( f_add_ex4_res( 30) and ex4_shctl_64(0) ); +u_sh1x_032: ex4_sh1_x_b( 32) <= not( f_add_ex4_res( 31) and ex4_shctl_64(0) ); +u_sh1x_033: ex4_sh1_x_b( 33) <= not( f_add_ex4_res( 32) and ex4_shctl_64(0) ); +u_sh1x_034: ex4_sh1_x_b( 34) <= not( f_add_ex4_res( 33) and ex4_shctl_64(0) ); +u_sh1x_035: ex4_sh1_x_b( 35) <= not( f_add_ex4_res( 34) and ex4_shctl_64(0) ); +u_sh1x_036: ex4_sh1_x_b( 36) <= not( f_add_ex4_res( 35) and ex4_shctl_64(0) ); +u_sh1x_037: ex4_sh1_x_b( 37) <= not( f_add_ex4_res( 36) and ex4_shctl_64(0) ); +u_sh1x_038: ex4_sh1_x_b( 38) <= not( f_add_ex4_res( 37) and ex4_shctl_64(0) ); +u_sh1x_039: ex4_sh1_x_b( 39) <= not( f_add_ex4_res( 38) and ex4_shctl_64(0) ); +u_sh1x_040: ex4_sh1_x_b( 40) <= not( f_add_ex4_res( 39) and ex4_shctl_64_cp2(0) ); +u_sh1x_041: ex4_sh1_x_b( 41) <= not( f_add_ex4_res( 40) and ex4_shctl_64_cp2(0) ); +u_sh1x_042: ex4_sh1_x_b( 42) <= not( f_add_ex4_res( 41) and ex4_shctl_64_cp2(0) ); +u_sh1x_043: ex4_sh1_x_b( 43) <= not( f_add_ex4_res( 42) and ex4_shctl_64_cp2(0) ); +u_sh1x_044: ex4_sh1_x_b( 44) <= not( f_add_ex4_res( 43) and ex4_shctl_64_cp2(0) ); +u_sh1x_045: ex4_sh1_x_b( 45) <= not( f_add_ex4_res( 44) and ex4_shctl_64_cp2(0) ); +u_sh1x_046: ex4_sh1_x_b( 46) <= not( f_add_ex4_res( 45) and ex4_shctl_64_cp2(0) ); +u_sh1x_047: ex4_sh1_x_b( 47) <= not( f_add_ex4_res( 46) and ex4_shctl_64_cp2(0) ); +u_sh1x_048: ex4_sh1_x_b( 48) <= not( f_add_ex4_res( 47) and ex4_shctl_64_cp2(0) ); +u_sh1x_049: ex4_sh1_x_b( 49) <= not( f_add_ex4_res( 48) and ex4_shctl_64_cp2(0) ); +u_sh1x_050: ex4_sh1_x_b( 50) <= not( f_add_ex4_res( 49) and ex4_shctl_64_cp2(0) ); +u_sh1x_051: ex4_sh1_x_b( 51) <= not( f_add_ex4_res( 50) and ex4_shctl_64_cp2(0) ); +u_sh1x_052: ex4_sh1_x_b( 52) <= not( f_add_ex4_res( 51) and ex4_shctl_64_cp2(0) ); +u_sh1x_053: ex4_sh1_x_b( 53) <= not( f_add_ex4_res( 52) and ex4_shctl_64_cp2(0) ); +u_sh1x_054: ex4_sh1_x_b( 54) <= not( f_add_ex4_res( 53) and ex4_shctl_64_cp2(0) ); +u_sh1x_055: ex4_sh1_x_b( 55) <= not( f_add_ex4_res( 54) and ex4_shctl_64_cp2(0) ); +u_sh1x_056: ex4_sh1_x_b( 56) <= not( f_add_ex4_res( 55) and ex4_shctl_64_cp2(0) ); +u_sh1x_057: ex4_sh1_x_b( 57) <= not( f_add_ex4_res( 56) and ex4_shctl_64_cp2(0) ); +u_sh1x_058: ex4_sh1_x_b( 58) <= not( f_add_ex4_res( 57) and ex4_shctl_64_cp2(0) ); +u_sh1x_059: ex4_sh1_x_b( 59) <= not( f_add_ex4_res( 58) and ex4_shctl_64_cp2(0) ); +u_sh1x_060: ex4_sh1_x_b( 60) <= not( f_add_ex4_res( 59) and ex4_shctl_64_cp2(0) ); +u_sh1x_061: ex4_sh1_x_b( 61) <= not( f_add_ex4_res( 60) and ex4_shctl_64_cp2(0) ); +u_sh1x_062: ex4_sh1_x_b( 62) <= not( f_add_ex4_res( 61) and ex4_shctl_64_cp2(0) ); +u_sh1x_063: ex4_sh1_x_b( 63) <= not( f_add_ex4_res( 62) and ex4_shctl_64_cp2(0) ); +u_sh1x_064: ex4_sh1_x_b( 64) <= not( f_add_ex4_res( 63) and ex4_shctl_64_cp2(0) ); +u_sh1x_065: ex4_sh1_x_b( 65) <= not( f_add_ex4_res( 64) and ex4_shctl_64_cp2(0) ); +u_sh1x_066: ex4_sh1_x_b( 66) <= not( f_add_ex4_res( 65) and ex4_shctl_64_cp2(0) ); +u_sh1x_067: ex4_sh1_x_b( 67) <= not( f_add_ex4_res( 66) and ex4_shctl_64_cp2(0) ); +u_sh1x_068: ex4_sh1_x_b( 68) <= not( f_add_ex4_res( 67) and ex4_shctl_64_cp2(0) ); +u_sh1x_069: ex4_sh1_x_b( 69) <= not( f_add_ex4_res( 68) and ex4_shctl_64_cp2(0) ); +u_sh1x_070: ex4_sh1_x_b( 70) <= not( f_add_ex4_res( 69) and ex4_shctl_64_cp2(0) ); +u_sh1x_071: ex4_sh1_x_b( 71) <= not( f_add_ex4_res( 70) and ex4_shctl_64_cp2(0) ); +u_sh1x_072: ex4_sh1_x_b( 72) <= not( f_add_ex4_res( 71) and ex4_shctl_64_cp2(0) ); +u_sh1x_073: ex4_sh1_x_b( 73) <= not( f_add_ex4_res( 72) and ex4_shctl_64_cp2(0) ); +u_sh1x_074: ex4_sh1_x_b( 74) <= not( f_add_ex4_res( 73) and ex4_shctl_64_cp2(0) ); +u_sh1x_075: ex4_sh1_x_b( 75) <= not( f_add_ex4_res( 74) and ex4_shctl_64_cp2(0) ); +u_sh1x_076: ex4_sh1_x_b( 76) <= not( f_add_ex4_res( 75) and ex4_shctl_64_cp2(0) ); +u_sh1x_077: ex4_sh1_x_b( 77) <= not( f_add_ex4_res( 76) and ex4_shctl_64_cp2(0) ); +u_sh1x_078: ex4_sh1_x_b( 78) <= not( f_add_ex4_res( 77) and ex4_shctl_64_cp2(0) ); +u_sh1x_079: ex4_sh1_x_b( 79) <= not( f_add_ex4_res( 78) and ex4_shctl_64_cp2(0) ); +u_sh1x_080: ex4_sh1_x_b( 80) <= not( f_add_ex4_res( 79) and ex4_shctl_64_cp2(0) ); +u_sh1x_081: ex4_sh1_x_b( 81) <= not( f_add_ex4_res( 80) and ex4_shctl_64_cp3(0) ); +u_sh1x_082: ex4_sh1_x_b( 82) <= not( f_add_ex4_res( 81) and ex4_shctl_64_cp3(0) ); +u_sh1x_083: ex4_sh1_x_b( 83) <= not( f_add_ex4_res( 82) and ex4_shctl_64_cp3(0) ); +u_sh1x_084: ex4_sh1_x_b( 84) <= not( f_add_ex4_res( 83) and ex4_shctl_64_cp3(0) ); +u_sh1x_085: ex4_sh1_x_b( 85) <= not( f_add_ex4_res( 84) and ex4_shctl_64_cp3(0) ); +u_sh1x_086: ex4_sh1_x_b( 86) <= not( f_add_ex4_res( 85) and ex4_shctl_64_cp3(0) ); +u_sh1x_087: ex4_sh1_x_b( 87) <= not( f_add_ex4_res( 86) and ex4_shctl_64_cp3(0) ); +u_sh1x_088: ex4_sh1_x_b( 88) <= not( f_add_ex4_res( 87) and ex4_shctl_64_cp3(0) ); +u_sh1x_089: ex4_sh1_x_b( 89) <= not( f_add_ex4_res( 88) and ex4_shctl_64_cp3(0) ); +u_sh1x_090: ex4_sh1_x_b( 90) <= not( f_add_ex4_res( 89) and ex4_shctl_64_cp3(0) ); +u_sh1x_091: ex4_sh1_x_b( 91) <= not( f_add_ex4_res( 90) and ex4_shctl_64_cp3(0) ); +u_sh1x_092: ex4_sh1_x_b( 92) <= not( f_add_ex4_res( 91) and ex4_shctl_64_cp3(0) ); +u_sh1x_093: ex4_sh1_x_b( 93) <= not( f_add_ex4_res( 92) and ex4_shctl_64_cp3(0) ); +u_sh1x_094: ex4_sh1_x_b( 94) <= not( f_add_ex4_res( 93) and ex4_shctl_64_cp3(0) ); +u_sh1x_095: ex4_sh1_x_b( 95) <= not( f_add_ex4_res( 94) and ex4_shctl_64_cp3(0) ); +u_sh1x_096: ex4_sh1_x_b( 96) <= not( f_add_ex4_res( 95) and ex4_shctl_64_cp3(0) ); +u_sh1x_097: ex4_sh1_x_b( 97) <= not( f_add_ex4_res( 96) and ex4_shctl_64_cp3(0) ); +u_sh1x_098: ex4_sh1_x_b( 98) <= not( f_add_ex4_res( 97) and ex4_shctl_64_cp3(0) ); +u_sh1x_099: ex4_sh1_x_b( 99) <= not( f_add_ex4_res( 98) and ex4_shctl_64_cp3(0) ); +u_sh1x_100: ex4_sh1_x_b(100) <= not( f_add_ex4_res( 99) and ex4_shctl_64_cp3(0) ); +u_sh1x_101: ex4_sh1_x_b(101) <= not( f_add_ex4_res(100) and ex4_shctl_64_cp3(0) ); +u_sh1x_102: ex4_sh1_x_b(102) <= not( f_add_ex4_res(101) and ex4_shctl_64_cp3(0) ); +u_sh1x_103: ex4_sh1_x_b(103) <= not( f_add_ex4_res(102) and ex4_shctl_64_cp3(0) ); +u_sh1x_104: ex4_sh1_x_b(104) <= not( f_add_ex4_res(103) and ex4_shctl_64_cp3(0) ); +u_sh1x_105: ex4_sh1_x_b(105) <= not( f_add_ex4_res(104) and ex4_shctl_64_cp3(0) ); +u_sh1x_106: ex4_sh1_x_b(106) <= not( f_add_ex4_res(105) and ex4_shctl_64_cp3(0) ); +u_sh1x_107: ex4_sh1_x_b(107) <= not( f_add_ex4_res(106) and ex4_shctl_64_cp3(0) ); +u_sh1x_108: ex4_sh1_x_b(108) <= not( f_add_ex4_res(107) and ex4_shctl_64_cp3(0) ); +u_sh1x_109: ex4_sh1_x_b(109) <= not( f_add_ex4_res(108) and ex4_shctl_64_cp3(0) ); +u_sh1x_110: ex4_sh1_x_b(110) <= not( f_add_ex4_res(109) and ex4_shctl_64_cp3(0) ); +u_sh1x_111: ex4_sh1_x_b(111) <= not( f_add_ex4_res(110) and ex4_shctl_64_cp3(0) ); +u_sh1x_112: ex4_sh1_x_b(112) <= not( f_add_ex4_res(111) and ex4_shctl_64_cp3(0) ); +u_sh1x_113: ex4_sh1_x_b(113) <= not( f_add_ex4_res(112) and ex4_shctl_64_cp3(0) ); +u_sh1x_114: ex4_sh1_x_b(114) <= not( f_add_ex4_res(113) and ex4_shctl_64_cp3(0) ); +u_sh1x_115: ex4_sh1_x_b(115) <= not( f_add_ex4_res(114) and ex4_shctl_64_cp3(0) ); +u_sh1x_116: ex4_sh1_x_b(116) <= not( f_add_ex4_res(115) and ex4_shctl_64_cp3(0) ); +u_sh1x_117: ex4_sh1_x_b(117) <= not( f_add_ex4_res(116) and ex4_shctl_64_cp3(0) ); +u_sh1x_118: ex4_sh1_x_b(118) <= not( f_add_ex4_res(117) and ex4_shctl_64_cp3(0) ); +u_sh1x_119: ex4_sh1_x_b(119) <= not( f_add_ex4_res(118) and ex4_shctl_64_cp3(0) ); +u_sh1x_120: ex4_sh1_x_b(120) <= not( f_add_ex4_res(119) and ex4_shctl_64_cp3(0) ); + + +u_sh1y_000: ex4_sh1_y_b( 0) <= not( f_add_ex4_res( 63) and ex4_shctl_64(1) ); +u_sh1y_001: ex4_sh1_y_b( 1) <= not( f_add_ex4_res( 64) and ex4_shctl_64(1) ); +u_sh1y_002: ex4_sh1_y_b( 2) <= not( f_add_ex4_res( 65) and ex4_shctl_64(1) ); +u_sh1y_003: ex4_sh1_y_b( 3) <= not( f_add_ex4_res( 66) and ex4_shctl_64(1) ); +u_sh1y_004: ex4_sh1_y_b( 4) <= not( f_add_ex4_res( 67) and ex4_shctl_64(1) ); +u_sh1y_005: ex4_sh1_y_b( 5) <= not( f_add_ex4_res( 68) and ex4_shctl_64(1) ); +u_sh1y_006: ex4_sh1_y_b( 6) <= not( f_add_ex4_res( 69) and ex4_shctl_64(1) ); +u_sh1y_007: ex4_sh1_y_b( 7) <= not( f_add_ex4_res( 70) and ex4_shctl_64(1) ); +u_sh1y_008: ex4_sh1_y_b( 8) <= not( f_add_ex4_res( 71) and ex4_shctl_64(1) ); +u_sh1y_009: ex4_sh1_y_b( 9) <= not( f_add_ex4_res( 72) and ex4_shctl_64(1) ); +u_sh1y_010: ex4_sh1_y_b( 10) <= not( f_add_ex4_res( 73) and ex4_shctl_64(1) ); +u_sh1y_011: ex4_sh1_y_b( 11) <= not( f_add_ex4_res( 74) and ex4_shctl_64(1) ); +u_sh1y_012: ex4_sh1_y_b( 12) <= not( f_add_ex4_res( 75) and ex4_shctl_64(1) ); +u_sh1y_013: ex4_sh1_y_b( 13) <= not( f_add_ex4_res( 76) and ex4_shctl_64(1) ); +u_sh1y_014: ex4_sh1_y_b( 14) <= not( f_add_ex4_res( 77) and ex4_shctl_64(1) ); +u_sh1y_015: ex4_sh1_y_b( 15) <= not( f_add_ex4_res( 78) and ex4_shctl_64(1) ); +u_sh1y_016: ex4_sh1_y_b( 16) <= not( f_add_ex4_res( 79) and ex4_shctl_64(1) ); +u_sh1y_017: ex4_sh1_y_b( 17) <= not( f_add_ex4_res( 80) and ex4_shctl_64(1) ); +u_sh1y_018: ex4_sh1_y_b( 18) <= not( f_add_ex4_res( 81) and ex4_shctl_64(1) ); +u_sh1y_019: ex4_sh1_y_b( 19) <= not( f_add_ex4_res( 82) and ex4_shctl_64(1) ); +u_sh1y_020: ex4_sh1_y_b( 20) <= not( f_add_ex4_res( 83) and ex4_shctl_64(1) ); +u_sh1y_021: ex4_sh1_y_b( 21) <= not( f_add_ex4_res( 84) and ex4_shctl_64(1) ); +u_sh1y_022: ex4_sh1_y_b( 22) <= not( f_add_ex4_res( 85) and ex4_shctl_64(1) ); +u_sh1y_023: ex4_sh1_y_b( 23) <= not( f_add_ex4_res( 86) and ex4_shctl_64(1) ); +u_sh1y_024: ex4_sh1_y_b( 24) <= not( f_add_ex4_res( 87) and ex4_shctl_64(1) ); +u_sh1y_025: ex4_sh1_y_b( 25) <= not( f_add_ex4_res( 88) and ex4_shctl_64(1) ); +u_sh1y_026: ex4_sh1_y_b( 26) <= not( f_add_ex4_res( 89) and ex4_shctl_64(1) ); +u_sh1y_027: ex4_sh1_y_b( 27) <= not( f_add_ex4_res( 90) and ex4_shctl_64(1) ); +u_sh1y_028: ex4_sh1_y_b( 28) <= not( f_add_ex4_res( 91) and ex4_shctl_64(1) ); +u_sh1y_029: ex4_sh1_y_b( 29) <= not( f_add_ex4_res( 92) and ex4_shctl_64(1) ); +u_sh1y_030: ex4_sh1_y_b( 30) <= not( f_add_ex4_res( 93) and ex4_shctl_64(1) ); +u_sh1y_031: ex4_sh1_y_b( 31) <= not( f_add_ex4_res( 94) and ex4_shctl_64(1) ); +u_sh1y_032: ex4_sh1_y_b( 32) <= not( f_add_ex4_res( 95) and ex4_shctl_64(1) ); +u_sh1y_033: ex4_sh1_y_b( 33) <= not( f_add_ex4_res( 96) and ex4_shctl_64(1) ); +u_sh1y_034: ex4_sh1_y_b( 34) <= not( f_add_ex4_res( 97) and ex4_shctl_64(1) ); +u_sh1y_035: ex4_sh1_y_b( 35) <= not( f_add_ex4_res( 98) and ex4_shctl_64(1) ); +u_sh1y_036: ex4_sh1_y_b( 36) <= not( f_add_ex4_res( 99) and ex4_shctl_64(1) ); +u_sh1y_037: ex4_sh1_y_b( 37) <= not( f_add_ex4_res(100) and ex4_shctl_64(1) ); +u_sh1y_038: ex4_sh1_y_b( 38) <= not( f_add_ex4_res(101) and ex4_shctl_64(1) ); +u_sh1y_039: ex4_sh1_y_b( 39) <= not( f_add_ex4_res(102) and ex4_shctl_64(1) ); +u_sh1y_040: ex4_sh1_y_b( 40) <= not( f_add_ex4_res(103) and ex4_shctl_64(1) ); +u_sh1y_041: ex4_sh1_y_b( 41) <= not( f_add_ex4_res(104) and ex4_shctl_64(1) ); +u_sh1y_042: ex4_sh1_y_b( 42) <= not( f_add_ex4_res(105) and ex4_shctl_64(1) ); +u_sh1y_043: ex4_sh1_y_b( 43) <= not( f_add_ex4_res(106) and ex4_shctl_64(1) ); +u_sh1y_044: ex4_sh1_y_b( 44) <= not( f_add_ex4_res(107) and ex4_shctl_64(1) ); +u_sh1y_045: ex4_sh1_y_b( 45) <= not( f_add_ex4_res(108) and ex4_shctl_64(1) ); +u_sh1y_046: ex4_sh1_y_b( 46) <= not( f_add_ex4_res(109) and ex4_shctl_64(1) ); +u_sh1y_047: ex4_sh1_y_b( 47) <= not( f_add_ex4_res(110) and ex4_shctl_64(1) ); +u_sh1y_048: ex4_sh1_y_b( 48) <= not( f_add_ex4_res(111) and ex4_shctl_64(1) ); +u_sh1y_049: ex4_sh1_y_b( 49) <= not( f_add_ex4_res(112) and ex4_shctl_64(1) ); +u_sh1y_050: ex4_sh1_y_b( 50) <= not( f_add_ex4_res(113) and ex4_shctl_64(1) ); +u_sh1y_051: ex4_sh1_y_b( 51) <= not( f_add_ex4_res(114) and ex4_shctl_64(1) ); +u_sh1y_052: ex4_sh1_y_b( 52) <= not( f_add_ex4_res(115) and ex4_shctl_64(1) ); +u_sh1y_053: ex4_sh1_y_b( 53) <= not( f_add_ex4_res(116) and ex4_shctl_64(1) ); +u_sh1y_054: ex4_sh1_y_b( 54) <= not( f_add_ex4_res(117) and ex4_shctl_64(1) ); +u_sh1y_055: ex4_sh1_y_b( 55) <= not( f_add_ex4_res(118) and ex4_shctl_64_cp2(1) ); +u_sh1y_056: ex4_sh1_y_b( 56) <= not( f_add_ex4_res(119) and ex4_shctl_64_cp2(1) ); +u_sh1y_057: ex4_sh1_y_b( 57) <= not( f_add_ex4_res(120) and ex4_shctl_64_cp2(1) ); +u_sh1y_058: ex4_sh1_y_b( 58) <= not( f_add_ex4_res(121) and ex4_shctl_64_cp2(1) ); +u_sh1y_059: ex4_sh1_y_b( 59) <= not( f_add_ex4_res(122) and ex4_shctl_64_cp2(1) ); +u_sh1y_060: ex4_sh1_y_b( 60) <= not( f_add_ex4_res(123) and ex4_shctl_64_cp2(1) ); +u_sh1y_061: ex4_sh1_y_b( 61) <= not( f_add_ex4_res(124) and ex4_shctl_64_cp2(1) ); +u_sh1y_062: ex4_sh1_y_b( 62) <= not( f_add_ex4_res(125) and ex4_shctl_64_cp2(1) ); +u_sh1y_063: ex4_sh1_y_b( 63) <= not( f_add_ex4_res(126) and ex4_shctl_64_cp2(1) ); +u_sh1y_064: ex4_sh1_y_b( 64) <= not( f_add_ex4_res(127) and ex4_shctl_64_cp2(1) ); +u_sh1y_065: ex4_sh1_y_b( 65) <= not( f_add_ex4_res(128) and ex4_shctl_64_cp2(1) ); +u_sh1y_066: ex4_sh1_y_b( 66) <= not( f_add_ex4_res(129) and ex4_shctl_64_cp2(1) ); +u_sh1y_067: ex4_sh1_y_b( 67) <= not( f_add_ex4_res(130) and ex4_shctl_64_cp2(1) ); +u_sh1y_068: ex4_sh1_y_b( 68) <= not( f_add_ex4_res(131) and ex4_shctl_64_cp2(1) ); +u_sh1y_069: ex4_sh1_y_b( 69) <= not( f_add_ex4_res(132) and ex4_shctl_64_cp2(1) ); +u_sh1y_070: ex4_sh1_y_b( 70) <= not( f_add_ex4_res(133) and ex4_shctl_64_cp2(1) ); +u_sh1y_071: ex4_sh1_y_b( 71) <= not( f_add_ex4_res(134) and ex4_shctl_64_cp2(1) ); +u_sh1y_072: ex4_sh1_y_b( 72) <= not( f_add_ex4_res(135) and ex4_shctl_64_cp2(1) ); +u_sh1y_073: ex4_sh1_y_b( 73) <= not( f_add_ex4_res(136) and ex4_shctl_64_cp2(1) ); +u_sh1y_074: ex4_sh1_y_b( 74) <= not( f_add_ex4_res(137) and ex4_shctl_64_cp2(1) ); +u_sh1y_075: ex4_sh1_y_b( 75) <= not( f_add_ex4_res(138) and ex4_shctl_64_cp2(1) ); +u_sh1y_076: ex4_sh1_y_b( 76) <= not( f_add_ex4_res(139) and ex4_shctl_64_cp2(1) ); +u_sh1y_077: ex4_sh1_y_b( 77) <= not( f_add_ex4_res(140) and ex4_shctl_64_cp2(1) ); +u_sh1y_078: ex4_sh1_y_b( 78) <= not( f_add_ex4_res(141) and ex4_shctl_64_cp2(1) ); +u_sh1y_079: ex4_sh1_y_b( 79) <= not( f_add_ex4_res(142) and ex4_shctl_64_cp2(1) ); +u_sh1y_080: ex4_sh1_y_b( 80) <= not( f_add_ex4_res(143) and ex4_shctl_64_cp2(1) ); +u_sh1y_081: ex4_sh1_y_b( 81) <= not( f_add_ex4_res(144) and ex4_shctl_64_cp2(1) ); +u_sh1y_082: ex4_sh1_y_b( 82) <= not( f_add_ex4_res(145) and ex4_shctl_64_cp2(1) ); +u_sh1y_083: ex4_sh1_y_b( 83) <= not( f_add_ex4_res(146) and ex4_shctl_64_cp2(1) ); +u_sh1y_084: ex4_sh1_y_b( 84) <= not( f_add_ex4_res(147) and ex4_shctl_64_cp2(1) ); +u_sh1y_085: ex4_sh1_y_b( 85) <= not( f_add_ex4_res(148) and ex4_shctl_64_cp2(1) ); +u_sh1y_086: ex4_sh1_y_b( 86) <= not( f_add_ex4_res(149) and ex4_shctl_64_cp2(1) ); +u_sh1y_087: ex4_sh1_y_b( 87) <= not( f_add_ex4_res(150) and ex4_shctl_64_cp2(1) ); +u_sh1y_088: ex4_sh1_y_b( 88) <= not( f_add_ex4_res(151) and ex4_shctl_64_cp2(1) ); +u_sh1y_089: ex4_sh1_y_b( 89) <= not( f_add_ex4_res(152) and ex4_shctl_64_cp2(1) ); +u_sh1y_090: ex4_sh1_y_b( 90) <= not( f_add_ex4_res(153) and ex4_shctl_64_cp2(1) ); +u_sh1y_091: ex4_sh1_y_b( 91) <= not( f_add_ex4_res(154) and ex4_shctl_64_cp2(1) ); +u_sh1y_092: ex4_sh1_y_b( 92) <= not( f_add_ex4_res(155) and ex4_shctl_64_cp2(1) ); +u_sh1y_093: ex4_sh1_y_b( 93) <= not( f_add_ex4_res(156) and ex4_shctl_64_cp2(1) ); +u_sh1y_094: ex4_sh1_y_b( 94) <= not( f_add_ex4_res(157) and ex4_shctl_64_cp2(1) ); +u_sh1y_095: ex4_sh1_y_b( 95) <= not( f_add_ex4_res(158) and ex4_shctl_64_cp2(1) ); +u_sh1y_096: ex4_sh1_y_b( 96) <= not( f_add_ex4_res(159) and ex4_shctl_64_cp2(1) ); +u_sh1y_097: ex4_sh1_y_b( 97) <= not( f_add_ex4_res(160) and ex4_shctl_64_cp2(1) ); +u_sh1y_098: ex4_sh1_y_b( 98) <= not( f_add_ex4_res(161) and ex4_shctl_64_cp2(1) ); +u_sh1y_099: ex4_sh1_y_b( 99) <= not( f_add_ex4_res(162) and ex4_shctl_64_cp2(1) ); + +u_sh1u_000: ex4_sh1_u_b( 0) <= not( f_add_ex4_res(127) and ex4_shctl_64(2) ); +u_sh1u_001: ex4_sh1_u_b( 1) <= not( f_add_ex4_res(128) and ex4_shctl_64(2) ); +u_sh1u_002: ex4_sh1_u_b( 2) <= not( f_add_ex4_res(129) and ex4_shctl_64(2) ); +u_sh1u_003: ex4_sh1_u_b( 3) <= not( f_add_ex4_res(130) and ex4_shctl_64(2) ); +u_sh1u_004: ex4_sh1_u_b( 4) <= not( f_add_ex4_res(131) and ex4_shctl_64(2) ); +u_sh1u_005: ex4_sh1_u_b( 5) <= not( f_add_ex4_res(132) and ex4_shctl_64(2) ); +u_sh1u_006: ex4_sh1_u_b( 6) <= not( f_add_ex4_res(133) and ex4_shctl_64(2) ); +u_sh1u_007: ex4_sh1_u_b( 7) <= not( f_add_ex4_res(134) and ex4_shctl_64(2) ); +u_sh1u_008: ex4_sh1_u_b( 8) <= not( f_add_ex4_res(135) and ex4_shctl_64(2) ); +u_sh1u_009: ex4_sh1_u_b( 9) <= not( f_add_ex4_res(136) and ex4_shctl_64(2) ); +u_sh1u_010: ex4_sh1_u_b( 10) <= not( f_add_ex4_res(137) and ex4_shctl_64(2) ); +u_sh1u_011: ex4_sh1_u_b( 11) <= not( f_add_ex4_res(138) and ex4_shctl_64(2) ); +u_sh1u_012: ex4_sh1_u_b( 12) <= not( f_add_ex4_res(139) and ex4_shctl_64(2) ); +u_sh1u_013: ex4_sh1_u_b( 13) <= not( f_add_ex4_res(140) and ex4_shctl_64(2) ); +u_sh1u_014: ex4_sh1_u_b( 14) <= not( f_add_ex4_res(141) and ex4_shctl_64(2) ); +u_sh1u_015: ex4_sh1_u_b( 15) <= not( f_add_ex4_res(142) and ex4_shctl_64(2) ); +u_sh1u_016: ex4_sh1_u_b( 16) <= not( f_add_ex4_res(143) and ex4_shctl_64(2) ); +u_sh1u_017: ex4_sh1_u_b( 17) <= not( f_add_ex4_res(144) and ex4_shctl_64(2) ); +u_sh1u_018: ex4_sh1_u_b( 18) <= not( f_add_ex4_res(145) and ex4_shctl_64(2) ); +u_sh1u_019: ex4_sh1_u_b( 19) <= not( f_add_ex4_res(146) and ex4_shctl_64(2) ); +u_sh1u_020: ex4_sh1_u_b( 20) <= not( f_add_ex4_res(147) and ex4_shctl_64(2) ); +u_sh1u_021: ex4_sh1_u_b( 21) <= not( f_add_ex4_res(148) and ex4_shctl_64(2) ); +u_sh1u_022: ex4_sh1_u_b( 22) <= not( f_add_ex4_res(149) and ex4_shctl_64(2) ); +u_sh1u_023: ex4_sh1_u_b( 23) <= not( f_add_ex4_res(150) and ex4_shctl_64(2) ); +u_sh1u_024: ex4_sh1_u_b( 24) <= not( f_add_ex4_res(151) and ex4_shctl_64(2) ); +u_sh1u_025: ex4_sh1_u_b( 25) <= not( f_add_ex4_res(152) and ex4_shctl_64(2) ); +u_sh1u_026: ex4_sh1_u_b( 26) <= not( f_add_ex4_res(153) and ex4_shctl_64(2) ); +u_sh1u_027: ex4_sh1_u_b( 27) <= not( f_add_ex4_res(154) and ex4_shctl_64(2) ); +u_sh1u_028: ex4_sh1_u_b( 28) <= not( f_add_ex4_res(155) and ex4_shctl_64(2) ); +u_sh1u_029: ex4_sh1_u_b( 29) <= not( f_add_ex4_res(156) and ex4_shctl_64(2) ); +u_sh1u_030: ex4_sh1_u_b( 30) <= not( f_add_ex4_res(157) and ex4_shctl_64(2) ); +u_sh1u_031: ex4_sh1_u_b( 31) <= not( f_add_ex4_res(158) and ex4_shctl_64(2) ); +u_sh1u_032: ex4_sh1_u_b( 32) <= not( f_add_ex4_res(159) and ex4_shctl_64(2) ); +u_sh1u_033: ex4_sh1_u_b( 33) <= not( f_add_ex4_res(160) and ex4_shctl_64(2) ); +u_sh1u_034: ex4_sh1_u_b( 34) <= not( f_add_ex4_res(161) and ex4_shctl_64(2) ); +u_sh1u_035: ex4_sh1_u_b( 35) <= not( f_add_ex4_res(162) and ex4_shctl_64(2) ); + +u_sh1z_065: ex4_sh1_z_b( 65) <= not( f_add_ex4_res( 0) and f_lza_ex4_sh_rgt_en ); +u_sh1z_066: ex4_sh1_z_b( 66) <= not( f_add_ex4_res( 1) and f_lza_ex4_sh_rgt_en ); +u_sh1z_067: ex4_sh1_z_b( 67) <= not( f_add_ex4_res( 2) and f_lza_ex4_sh_rgt_en ); +u_sh1z_068: ex4_sh1_z_b( 68) <= not( f_add_ex4_res( 3) and f_lza_ex4_sh_rgt_en ); +u_sh1z_069: ex4_sh1_z_b( 69) <= not( f_add_ex4_res( 4) and f_lza_ex4_sh_rgt_en ); +u_sh1z_070: ex4_sh1_z_b( 70) <= not( f_add_ex4_res( 5) and f_lza_ex4_sh_rgt_en ); +u_sh1z_071: ex4_sh1_z_b( 71) <= not( f_add_ex4_res( 6) and f_lza_ex4_sh_rgt_en ); +u_sh1z_072: ex4_sh1_z_b( 72) <= not( f_add_ex4_res( 7) and f_lza_ex4_sh_rgt_en ); +u_sh1z_073: ex4_sh1_z_b( 73) <= not( f_add_ex4_res( 8) and f_lza_ex4_sh_rgt_en ); +u_sh1z_074: ex4_sh1_z_b( 74) <= not( f_add_ex4_res( 9) and f_lza_ex4_sh_rgt_en ); +u_sh1z_075: ex4_sh1_z_b( 75) <= not( f_add_ex4_res( 10) and f_lza_ex4_sh_rgt_en ); +u_sh1z_076: ex4_sh1_z_b( 76) <= not( f_add_ex4_res( 11) and f_lza_ex4_sh_rgt_en ); +u_sh1z_077: ex4_sh1_z_b( 77) <= not( f_add_ex4_res( 12) and f_lza_ex4_sh_rgt_en ); +u_sh1z_078: ex4_sh1_z_b( 78) <= not( f_add_ex4_res( 13) and f_lza_ex4_sh_rgt_en ); +u_sh1z_079: ex4_sh1_z_b( 79) <= not( f_add_ex4_res( 14) and f_lza_ex4_sh_rgt_en ); +u_sh1z_080: ex4_sh1_z_b( 80) <= not( f_add_ex4_res( 15) and f_lza_ex4_sh_rgt_en ); +u_sh1z_081: ex4_sh1_z_b( 81) <= not( f_add_ex4_res( 16) and f_lza_ex4_sh_rgt_en ); +u_sh1z_082: ex4_sh1_z_b( 82) <= not( f_add_ex4_res( 17) and f_lza_ex4_sh_rgt_en ); +u_sh1z_083: ex4_sh1_z_b( 83) <= not( f_add_ex4_res( 18) and f_lza_ex4_sh_rgt_en ); +u_sh1z_084: ex4_sh1_z_b( 84) <= not( f_add_ex4_res( 19) and f_lza_ex4_sh_rgt_en ); +u_sh1z_085: ex4_sh1_z_b( 85) <= not( f_add_ex4_res( 20) and f_lza_ex4_sh_rgt_en ); +u_sh1z_086: ex4_sh1_z_b( 86) <= not( f_add_ex4_res( 21) and f_lza_ex4_sh_rgt_en ); +u_sh1z_087: ex4_sh1_z_b( 87) <= not( f_add_ex4_res( 22) and f_lza_ex4_sh_rgt_en ); +u_sh1z_088: ex4_sh1_z_b( 88) <= not( f_add_ex4_res( 23) and f_lza_ex4_sh_rgt_en ); +u_sh1z_089: ex4_sh1_z_b( 89) <= not( f_add_ex4_res( 24) and f_lza_ex4_sh_rgt_en ); +u_sh1z_090: ex4_sh1_z_b( 90) <= not( f_add_ex4_res( 25) and f_lza_ex4_sh_rgt_en ); +u_sh1z_091: ex4_sh1_z_b( 91) <= not( f_add_ex4_res( 26) and f_lza_ex4_sh_rgt_en ); +u_sh1z_092: ex4_sh1_z_b( 92) <= not( f_add_ex4_res( 27) and f_lza_ex4_sh_rgt_en ); +u_sh1z_093: ex4_sh1_z_b( 93) <= not( f_add_ex4_res( 28) and f_lza_ex4_sh_rgt_en ); +u_sh1z_094: ex4_sh1_z_b( 94) <= not( f_add_ex4_res( 29) and f_lza_ex4_sh_rgt_en ); +u_sh1z_095: ex4_sh1_z_b( 95) <= not( f_add_ex4_res( 30) and f_lza_ex4_sh_rgt_en ); +u_sh1z_096: ex4_sh1_z_b( 96) <= not( f_add_ex4_res( 31) and f_lza_ex4_sh_rgt_en ); +u_sh1z_097: ex4_sh1_z_b( 97) <= not( f_add_ex4_res( 32) and f_lza_ex4_sh_rgt_en ); +u_sh1z_098: ex4_sh1_z_b( 98) <= not( f_add_ex4_res( 33) and f_lza_ex4_sh_rgt_en ); +u_sh1z_099: ex4_sh1_z_b( 99) <= not( f_add_ex4_res( 34) and f_lza_ex4_sh_rgt_en ); +u_sh1z_100: ex4_sh1_z_b(100) <= not( f_add_ex4_res( 35) and f_lza_ex4_sh_rgt_en ); +u_sh1z_101: ex4_sh1_z_b(101) <= not( f_add_ex4_res( 36) and f_lza_ex4_sh_rgt_en ); +u_sh1z_102: ex4_sh1_z_b(102) <= not( f_add_ex4_res( 37) and f_lza_ex4_sh_rgt_en ); +u_sh1z_103: ex4_sh1_z_b(103) <= not( f_add_ex4_res( 38) and f_lza_ex4_sh_rgt_en ); +u_sh1z_104: ex4_sh1_z_b(104) <= not( f_add_ex4_res( 39) and f_lza_ex4_sh_rgt_en ); +u_sh1z_105: ex4_sh1_z_b(105) <= not( f_add_ex4_res( 40) and f_lza_ex4_sh_rgt_en ); +u_sh1z_106: ex4_sh1_z_b(106) <= not( f_add_ex4_res( 41) and f_lza_ex4_sh_rgt_en ); +u_sh1z_107: ex4_sh1_z_b(107) <= not( f_add_ex4_res( 42) and f_lza_ex4_sh_rgt_en ); +u_sh1z_108: ex4_sh1_z_b(108) <= not( f_add_ex4_res( 43) and f_lza_ex4_sh_rgt_en ); +u_sh1z_109: ex4_sh1_z_b(109) <= not( f_add_ex4_res( 44) and f_lza_ex4_sh_rgt_en ); +u_sh1z_110: ex4_sh1_z_b(110) <= not( f_add_ex4_res( 45) and f_lza_ex4_sh_rgt_en ); +u_sh1z_111: ex4_sh1_z_b(111) <= not( f_add_ex4_res( 46) and f_lza_ex4_sh_rgt_en ); +u_sh1z_112: ex4_sh1_z_b(112) <= not( f_add_ex4_res( 47) and f_lza_ex4_sh_rgt_en ); +u_sh1z_113: ex4_sh1_z_b(113) <= not( f_add_ex4_res( 48) and f_lza_ex4_sh_rgt_en ); +u_sh1z_114: ex4_sh1_z_b(114) <= not( f_add_ex4_res( 49) and f_lza_ex4_sh_rgt_en ); +u_sh1z_115: ex4_sh1_z_b(115) <= not( f_add_ex4_res( 50) and f_lza_ex4_sh_rgt_en ); +u_sh1z_116: ex4_sh1_z_b(116) <= not( f_add_ex4_res( 51) and f_lza_ex4_sh_rgt_en ); +u_sh1z_117: ex4_sh1_z_b(117) <= not( f_add_ex4_res( 52) and f_lza_ex4_sh_rgt_en ); +u_sh1z_118: ex4_sh1_z_b(118) <= not( f_add_ex4_res( 53) and f_lza_ex4_sh_rgt_en ); + + + + +u_sh1_000: ex4_sh1( 0) <= not( ex4_sh1_x_b( 0) and ex4_sh1_y_b( 0) and ex4_sh1_u_b( 0) ); +u_sh1_001: ex4_sh1( 1) <= not( ex4_sh1_x_b( 1) and ex4_sh1_y_b( 1) and ex4_sh1_u_b( 1) ); +u_sh1_002: ex4_sh1( 2) <= not( ex4_sh1_x_b( 2) and ex4_sh1_y_b( 2) and ex4_sh1_u_b( 2) ); +u_sh1_003: ex4_sh1( 3) <= not( ex4_sh1_x_b( 3) and ex4_sh1_y_b( 3) and ex4_sh1_u_b( 3) ); +u_sh1_004: ex4_sh1( 4) <= not( ex4_sh1_x_b( 4) and ex4_sh1_y_b( 4) and ex4_sh1_u_b( 4) ); +u_sh1_005: ex4_sh1( 5) <= not( ex4_sh1_x_b( 5) and ex4_sh1_y_b( 5) and ex4_sh1_u_b( 5) ); +u_sh1_006: ex4_sh1( 6) <= not( ex4_sh1_x_b( 6) and ex4_sh1_y_b( 6) and ex4_sh1_u_b( 6) ); +u_sh1_007: ex4_sh1( 7) <= not( ex4_sh1_x_b( 7) and ex4_sh1_y_b( 7) and ex4_sh1_u_b( 7) ); +u_sh1_008: ex4_sh1( 8) <= not( ex4_sh1_x_b( 8) and ex4_sh1_y_b( 8) and ex4_sh1_u_b( 8) ); +u_sh1_009: ex4_sh1( 9) <= not( ex4_sh1_x_b( 9) and ex4_sh1_y_b( 9) and ex4_sh1_u_b( 9) ); +u_sh1_010: ex4_sh1( 10) <= not( ex4_sh1_x_b( 10) and ex4_sh1_y_b( 10) and ex4_sh1_u_b( 10) ); +u_sh1_011: ex4_sh1( 11) <= not( ex4_sh1_x_b( 11) and ex4_sh1_y_b( 11) and ex4_sh1_u_b( 11) ); +u_sh1_012: ex4_sh1( 12) <= not( ex4_sh1_x_b( 12) and ex4_sh1_y_b( 12) and ex4_sh1_u_b( 12) ); +u_sh1_013: ex4_sh1( 13) <= not( ex4_sh1_x_b( 13) and ex4_sh1_y_b( 13) and ex4_sh1_u_b( 13) ); +u_sh1_014: ex4_sh1( 14) <= not( ex4_sh1_x_b( 14) and ex4_sh1_y_b( 14) and ex4_sh1_u_b( 14) ); +u_sh1_015: ex4_sh1( 15) <= not( ex4_sh1_x_b( 15) and ex4_sh1_y_b( 15) and ex4_sh1_u_b( 15) ); +u_sh1_016: ex4_sh1( 16) <= not( ex4_sh1_x_b( 16) and ex4_sh1_y_b( 16) and ex4_sh1_u_b( 16) ); +u_sh1_017: ex4_sh1( 17) <= not( ex4_sh1_x_b( 17) and ex4_sh1_y_b( 17) and ex4_sh1_u_b( 17) ); +u_sh1_018: ex4_sh1( 18) <= not( ex4_sh1_x_b( 18) and ex4_sh1_y_b( 18) and ex4_sh1_u_b( 18) ); +u_sh1_019: ex4_sh1( 19) <= not( ex4_sh1_x_b( 19) and ex4_sh1_y_b( 19) and ex4_sh1_u_b( 19) ); +u_sh1_020: ex4_sh1( 20) <= not( ex4_sh1_x_b( 20) and ex4_sh1_y_b( 20) and ex4_sh1_u_b( 20) ); +u_sh1_021: ex4_sh1( 21) <= not( ex4_sh1_x_b( 21) and ex4_sh1_y_b( 21) and ex4_sh1_u_b( 21) ); +u_sh1_022: ex4_sh1( 22) <= not( ex4_sh1_x_b( 22) and ex4_sh1_y_b( 22) and ex4_sh1_u_b( 22) ); +u_sh1_023: ex4_sh1( 23) <= not( ex4_sh1_x_b( 23) and ex4_sh1_y_b( 23) and ex4_sh1_u_b( 23) ); +u_sh1_024: ex4_sh1( 24) <= not( ex4_sh1_x_b( 24) and ex4_sh1_y_b( 24) and ex4_sh1_u_b( 24) ); +u_sh1_025: ex4_sh1( 25) <= not( ex4_sh1_x_b( 25) and ex4_sh1_y_b( 25) and ex4_sh1_u_b( 25) ); +u_sh1_026: ex4_sh1( 26) <= not( ex4_sh1_x_b( 26) and ex4_sh1_y_b( 26) and ex4_sh1_u_b( 26) ); +u_sh1_027: ex4_sh1( 27) <= not( ex4_sh1_x_b( 27) and ex4_sh1_y_b( 27) and ex4_sh1_u_b( 27) ); +u_sh1_028: ex4_sh1( 28) <= not( ex4_sh1_x_b( 28) and ex4_sh1_y_b( 28) and ex4_sh1_u_b( 28) ); +u_sh1_029: ex4_sh1( 29) <= not( ex4_sh1_x_b( 29) and ex4_sh1_y_b( 29) and ex4_sh1_u_b( 29) ); +u_sh1_030: ex4_sh1( 30) <= not( ex4_sh1_x_b( 30) and ex4_sh1_y_b( 30) and ex4_sh1_u_b( 30) ); +u_sh1_031: ex4_sh1( 31) <= not( ex4_sh1_x_b( 31) and ex4_sh1_y_b( 31) and ex4_sh1_u_b( 31) ); +u_sh1_032: ex4_sh1( 32) <= not( ex4_sh1_x_b( 32) and ex4_sh1_y_b( 32) and ex4_sh1_u_b( 32) ); +u_sh1_033: ex4_sh1( 33) <= not( ex4_sh1_x_b( 33) and ex4_sh1_y_b( 33) and ex4_sh1_u_b( 33) ); +u_sh1_034: ex4_sh1( 34) <= not( ex4_sh1_x_b( 34) and ex4_sh1_y_b( 34) and ex4_sh1_u_b( 34) ); +u_sh1_035: ex4_sh1( 35) <= not( ex4_sh1_x_b( 35) and ex4_sh1_y_b( 35) and ex4_sh1_u_b( 35) ); +u_sh1_036: ex4_sh1( 36) <= not( ex4_sh1_x_b( 36) and ex4_sh1_y_b( 36) ); +u_sh1_037: ex4_sh1( 37) <= not( ex4_sh1_x_b( 37) and ex4_sh1_y_b( 37) ); +u_sh1_038: ex4_sh1( 38) <= not( ex4_sh1_x_b( 38) and ex4_sh1_y_b( 38) ); +u_sh1_039: ex4_sh1( 39) <= not( ex4_sh1_x_b( 39) and ex4_sh1_y_b( 39) ); +u_sh1_040: ex4_sh1( 40) <= not( ex4_sh1_x_b( 40) and ex4_sh1_y_b( 40) ); +u_sh1_041: ex4_sh1( 41) <= not( ex4_sh1_x_b( 41) and ex4_sh1_y_b( 41) ); +u_sh1_042: ex4_sh1( 42) <= not( ex4_sh1_x_b( 42) and ex4_sh1_y_b( 42) ); +u_sh1_043: ex4_sh1( 43) <= not( ex4_sh1_x_b( 43) and ex4_sh1_y_b( 43) ); +u_sh1_044: ex4_sh1( 44) <= not( ex4_sh1_x_b( 44) and ex4_sh1_y_b( 44) ); +u_sh1_045: ex4_sh1( 45) <= not( ex4_sh1_x_b( 45) and ex4_sh1_y_b( 45) ); +u_sh1_046: ex4_sh1( 46) <= not( ex4_sh1_x_b( 46) and ex4_sh1_y_b( 46) ); +u_sh1_047: ex4_sh1( 47) <= not( ex4_sh1_x_b( 47) and ex4_sh1_y_b( 47) ); +u_sh1_048: ex4_sh1( 48) <= not( ex4_sh1_x_b( 48) and ex4_sh1_y_b( 48) ); +u_sh1_049: ex4_sh1( 49) <= not( ex4_sh1_x_b( 49) and ex4_sh1_y_b( 49) ); +u_sh1_050: ex4_sh1( 50) <= not( ex4_sh1_x_b( 50) and ex4_sh1_y_b( 50) ); +u_sh1_051: ex4_sh1( 51) <= not( ex4_sh1_x_b( 51) and ex4_sh1_y_b( 51) ); +u_sh1_052: ex4_sh1( 52) <= not( ex4_sh1_x_b( 52) and ex4_sh1_y_b( 52) ); +u_sh1_053: ex4_sh1( 53) <= not( ex4_sh1_x_b( 53) and ex4_sh1_y_b( 53) ); +u_sh1_054: ex4_sh1( 54) <= not( ex4_sh1_x_b( 54) and ex4_sh1_y_b( 54) ); +u_sh1_055: ex4_sh1( 55) <= not( ex4_sh1_x_b( 55) and ex4_sh1_y_b( 55) ); +u_sh1_056: ex4_sh1( 56) <= not( ex4_sh1_x_b( 56) and ex4_sh1_y_b( 56) ); +u_sh1_057: ex4_sh1( 57) <= not( ex4_sh1_x_b( 57) and ex4_sh1_y_b( 57) ); +u_sh1_058: ex4_sh1( 58) <= not( ex4_sh1_x_b( 58) and ex4_sh1_y_b( 58) ); +u_sh1_059: ex4_sh1( 59) <= not( ex4_sh1_x_b( 59) and ex4_sh1_y_b( 59) ); +u_sh1_060: ex4_sh1( 60) <= not( ex4_sh1_x_b( 60) and ex4_sh1_y_b( 60) ); +u_sh1_061: ex4_sh1( 61) <= not( ex4_sh1_x_b( 61) and ex4_sh1_y_b( 61) ); +u_sh1_062: ex4_sh1( 62) <= not( ex4_sh1_x_b( 62) and ex4_sh1_y_b( 62) ); +u_sh1_063: ex4_sh1( 63) <= not( ex4_sh1_x_b( 63) and ex4_sh1_y_b( 63) ); +u_sh1_064: ex4_sh1( 64) <= not( ex4_sh1_x_b( 64) and ex4_sh1_y_b( 64) ); +u_sh1_065: ex4_sh1( 65) <= not( ex4_sh1_x_b( 65) and ex4_sh1_y_b( 65) and ex4_sh1_z_b( 65) ); +u_sh1_066: ex4_sh1( 66) <= not( ex4_sh1_x_b( 66) and ex4_sh1_y_b( 66) and ex4_sh1_z_b( 66) ); +u_sh1_067: ex4_sh1( 67) <= not( ex4_sh1_x_b( 67) and ex4_sh1_y_b( 67) and ex4_sh1_z_b( 67) ); +u_sh1_068: ex4_sh1( 68) <= not( ex4_sh1_x_b( 68) and ex4_sh1_y_b( 68) and ex4_sh1_z_b( 68) ); +u_sh1_069: ex4_sh1( 69) <= not( ex4_sh1_x_b( 69) and ex4_sh1_y_b( 69) and ex4_sh1_z_b( 69) ); +u_sh1_070: ex4_sh1( 70) <= not( ex4_sh1_x_b( 70) and ex4_sh1_y_b( 70) and ex4_sh1_z_b( 70) ); +u_sh1_071: ex4_sh1( 71) <= not( ex4_sh1_x_b( 71) and ex4_sh1_y_b( 71) and ex4_sh1_z_b( 71) ); +u_sh1_072: ex4_sh1( 72) <= not( ex4_sh1_x_b( 72) and ex4_sh1_y_b( 72) and ex4_sh1_z_b( 72) ); +u_sh1_073: ex4_sh1( 73) <= not( ex4_sh1_x_b( 73) and ex4_sh1_y_b( 73) and ex4_sh1_z_b( 73) ); +u_sh1_074: ex4_sh1( 74) <= not( ex4_sh1_x_b( 74) and ex4_sh1_y_b( 74) and ex4_sh1_z_b( 74) ); +u_sh1_075: ex4_sh1( 75) <= not( ex4_sh1_x_b( 75) and ex4_sh1_y_b( 75) and ex4_sh1_z_b( 75) ); +u_sh1_076: ex4_sh1( 76) <= not( ex4_sh1_x_b( 76) and ex4_sh1_y_b( 76) and ex4_sh1_z_b( 76) ); +u_sh1_077: ex4_sh1( 77) <= not( ex4_sh1_x_b( 77) and ex4_sh1_y_b( 77) and ex4_sh1_z_b( 77) ); +u_sh1_078: ex4_sh1( 78) <= not( ex4_sh1_x_b( 78) and ex4_sh1_y_b( 78) and ex4_sh1_z_b( 78) ); +u_sh1_079: ex4_sh1( 79) <= not( ex4_sh1_x_b( 79) and ex4_sh1_y_b( 79) and ex4_sh1_z_b( 79) ); +u_sh1_080: ex4_sh1( 80) <= not( ex4_sh1_x_b( 80) and ex4_sh1_y_b( 80) and ex4_sh1_z_b( 80) ); +u_sh1_081: ex4_sh1( 81) <= not( ex4_sh1_x_b( 81) and ex4_sh1_y_b( 81) and ex4_sh1_z_b( 81) ); +u_sh1_082: ex4_sh1( 82) <= not( ex4_sh1_x_b( 82) and ex4_sh1_y_b( 82) and ex4_sh1_z_b( 82) ); +u_sh1_083: ex4_sh1( 83) <= not( ex4_sh1_x_b( 83) and ex4_sh1_y_b( 83) and ex4_sh1_z_b( 83) ); +u_sh1_084: ex4_sh1( 84) <= not( ex4_sh1_x_b( 84) and ex4_sh1_y_b( 84) and ex4_sh1_z_b( 84) ); +u_sh1_085: ex4_sh1( 85) <= not( ex4_sh1_x_b( 85) and ex4_sh1_y_b( 85) and ex4_sh1_z_b( 85) ); +u_sh1_086: ex4_sh1( 86) <= not( ex4_sh1_x_b( 86) and ex4_sh1_y_b( 86) and ex4_sh1_z_b( 86) ); +u_sh1_087: ex4_sh1( 87) <= not( ex4_sh1_x_b( 87) and ex4_sh1_y_b( 87) and ex4_sh1_z_b( 87) ); +u_sh1_088: ex4_sh1( 88) <= not( ex4_sh1_x_b( 88) and ex4_sh1_y_b( 88) and ex4_sh1_z_b( 88) ); +u_sh1_089: ex4_sh1( 89) <= not( ex4_sh1_x_b( 89) and ex4_sh1_y_b( 89) and ex4_sh1_z_b( 89) ); +u_sh1_090: ex4_sh1( 90) <= not( ex4_sh1_x_b( 90) and ex4_sh1_y_b( 90) and ex4_sh1_z_b( 90) ); +u_sh1_091: ex4_sh1( 91) <= not( ex4_sh1_x_b( 91) and ex4_sh1_y_b( 91) and ex4_sh1_z_b( 91) ); +u_sh1_092: ex4_sh1( 92) <= not( ex4_sh1_x_b( 92) and ex4_sh1_y_b( 92) and ex4_sh1_z_b( 92) ); +u_sh1_093: ex4_sh1( 93) <= not( ex4_sh1_x_b( 93) and ex4_sh1_y_b( 93) and ex4_sh1_z_b( 93) ); +u_sh1_094: ex4_sh1( 94) <= not( ex4_sh1_x_b( 94) and ex4_sh1_y_b( 94) and ex4_sh1_z_b( 94) ); +u_sh1_095: ex4_sh1( 95) <= not( ex4_sh1_x_b( 95) and ex4_sh1_y_b( 95) and ex4_sh1_z_b( 95) ); +u_sh1_096: ex4_sh1( 96) <= not( ex4_sh1_x_b( 96) and ex4_sh1_y_b( 96) and ex4_sh1_z_b( 96) ); +u_sh1_097: ex4_sh1( 97) <= not( ex4_sh1_x_b( 97) and ex4_sh1_y_b( 97) and ex4_sh1_z_b( 97) ); +u_sh1_098: ex4_sh1( 98) <= not( ex4_sh1_x_b( 98) and ex4_sh1_y_b( 98) and ex4_sh1_z_b( 98) ); +u_sh1_099: ex4_sh1( 99) <= not( ex4_sh1_x_b( 99) and ex4_sh1_y_b( 99) and ex4_sh1_z_b( 99) ); +u_sh1_100: ex4_sh1(100) <= not( ex4_sh1_x_b(100) and ex4_sh1_z_b(100) ); +u_sh1_101: ex4_sh1(101) <= not( ex4_sh1_x_b(101) and ex4_sh1_z_b(101) ); +u_sh1_102: ex4_sh1(102) <= not( ex4_sh1_x_b(102) and ex4_sh1_z_b(102) ); +u_sh1_103: ex4_sh1(103) <= not( ex4_sh1_x_b(103) and ex4_sh1_z_b(103) ); +u_sh1_104: ex4_sh1(104) <= not( ex4_sh1_x_b(104) and ex4_sh1_z_b(104) ); +u_sh1_105: ex4_sh1(105) <= not( ex4_sh1_x_b(105) and ex4_sh1_z_b(105) ); +u_sh1_106: ex4_sh1(106) <= not( ex4_sh1_x_b(106) and ex4_sh1_z_b(106) ); +u_sh1_107: ex4_sh1(107) <= not( ex4_sh1_x_b(107) and ex4_sh1_z_b(107) ); +u_sh1_108: ex4_sh1(108) <= not( ex4_sh1_x_b(108) and ex4_sh1_z_b(108) ); +u_sh1_109: ex4_sh1(109) <= not( ex4_sh1_x_b(109) and ex4_sh1_z_b(109) ); +u_sh1_110: ex4_sh1(110) <= not( ex4_sh1_x_b(110) and ex4_sh1_z_b(110) ); +u_sh1_111: ex4_sh1(111) <= not( ex4_sh1_x_b(111) and ex4_sh1_z_b(111) ); +u_sh1_112: ex4_sh1(112) <= not( ex4_sh1_x_b(112) and ex4_sh1_z_b(112) ); +u_sh1_113: ex4_sh1(113) <= not( ex4_sh1_x_b(113) and ex4_sh1_z_b(113) ); +u_sh1_114: ex4_sh1(114) <= not( ex4_sh1_x_b(114) and ex4_sh1_z_b(114) ); +u_sh1_115: ex4_sh1(115) <= not( ex4_sh1_x_b(115) and ex4_sh1_z_b(115) ); +u_sh1_116: ex4_sh1(116) <= not( ex4_sh1_x_b(116) and ex4_sh1_z_b(116) ); +u_sh1_117: ex4_sh1(117) <= not( ex4_sh1_x_b(117) and ex4_sh1_z_b(117) ); +u_sh1_118: ex4_sh1(118) <= not( ex4_sh1_x_b(118) and ex4_sh1_z_b(118) ); +u_sh1_119: ex4_sh1(119) <= not( ex4_sh1_x_b(119) ); +u_sh1_120: ex4_sh1(120) <= not( ex4_sh1_x_b(120) ); + + + +u_sh2x_00: ex4_sh2_x_b( 0) <= not( (ex4_sh1( 0) and ex4_shctl_16(0) ) or ( ex4_sh1( 16) and ex4_shctl_16(1) ) ); +u_sh2x_01: ex4_sh2_x_b( 1) <= not( (ex4_sh1( 1) and ex4_shctl_16(0) ) or ( ex4_sh1( 17) and ex4_shctl_16(1) ) ); +u_sh2x_02: ex4_sh2_x_b( 2) <= not( (ex4_sh1( 2) and ex4_shctl_16(0) ) or ( ex4_sh1( 18) and ex4_shctl_16(1) ) ); +u_sh2x_03: ex4_sh2_x_b( 3) <= not( (ex4_sh1( 3) and ex4_shctl_16(0) ) or ( ex4_sh1( 19) and ex4_shctl_16(1) ) ); +u_sh2x_04: ex4_sh2_x_b( 4) <= not( (ex4_sh1( 4) and ex4_shctl_16(0) ) or ( ex4_sh1( 20) and ex4_shctl_16(1) ) ); +u_sh2x_05: ex4_sh2_x_b( 5) <= not( (ex4_sh1( 5) and ex4_shctl_16(0) ) or ( ex4_sh1( 21) and ex4_shctl_16(1) ) ); +u_sh2x_06: ex4_sh2_x_b( 6) <= not( (ex4_sh1( 6) and ex4_shctl_16(0) ) or ( ex4_sh1( 22) and ex4_shctl_16(1) ) ); +u_sh2x_07: ex4_sh2_x_b( 7) <= not( (ex4_sh1( 7) and ex4_shctl_16(0) ) or ( ex4_sh1( 23) and ex4_shctl_16(1) ) ); +u_sh2x_08: ex4_sh2_x_b( 8) <= not( (ex4_sh1( 8) and ex4_shctl_16(0) ) or ( ex4_sh1( 24) and ex4_shctl_16(1) ) ); +u_sh2x_09: ex4_sh2_x_b( 9) <= not( (ex4_sh1( 9) and ex4_shctl_16(0) ) or ( ex4_sh1( 25) and ex4_shctl_16(1) ) ); +u_sh2x_10: ex4_sh2_x_b(10) <= not( (ex4_sh1( 10) and ex4_shctl_16(0) ) or ( ex4_sh1( 26) and ex4_shctl_16(1) ) ); +u_sh2x_11: ex4_sh2_x_b(11) <= not( (ex4_sh1( 11) and ex4_shctl_16(0) ) or ( ex4_sh1( 27) and ex4_shctl_16(1) ) ); +u_sh2x_12: ex4_sh2_x_b(12) <= not( (ex4_sh1( 12) and ex4_shctl_16(0) ) or ( ex4_sh1( 28) and ex4_shctl_16(1) ) ); +u_sh2x_13: ex4_sh2_x_b(13) <= not( (ex4_sh1( 13) and ex4_shctl_16(0) ) or ( ex4_sh1( 29) and ex4_shctl_16(1) ) ); +u_sh2x_14: ex4_sh2_x_b(14) <= not( (ex4_sh1( 14) and ex4_shctl_16(0) ) or ( ex4_sh1( 30) and ex4_shctl_16(1) ) ); +u_sh2x_15: ex4_sh2_x_b(15) <= not( (ex4_sh1( 15) and ex4_shctl_16(0) ) or ( ex4_sh1( 31) and ex4_shctl_16(1) ) ); +u_sh2x_16: ex4_sh2_x_b(16) <= not( (ex4_sh1( 16) and ex4_shctl_16(0) ) or ( ex4_sh1( 32) and ex4_shctl_16(1) ) ); +u_sh2x_17: ex4_sh2_x_b(17) <= not( (ex4_sh1( 17) and ex4_shctl_16(0) ) or ( ex4_sh1( 33) and ex4_shctl_16(1) ) ); +u_sh2x_18: ex4_sh2_x_b(18) <= not( (ex4_sh1( 18) and ex4_shctl_16(0) ) or ( ex4_sh1( 34) and ex4_shctl_16(1) ) ); +u_sh2x_19: ex4_sh2_x_b(19) <= not( (ex4_sh1( 19) and ex4_shctl_16(0) ) or ( ex4_sh1( 35) and ex4_shctl_16(1) ) ); +u_sh2x_20: ex4_sh2_x_b(20) <= not( (ex4_sh1( 20) and ex4_shctl_16(0) ) or ( ex4_sh1( 36) and ex4_shctl_16(1) ) ); +u_sh2x_21: ex4_sh2_x_b(21) <= not( (ex4_sh1( 21) and ex4_shctl_16(0) ) or ( ex4_sh1( 37) and ex4_shctl_16(1) ) ); +u_sh2x_22: ex4_sh2_x_b(22) <= not( (ex4_sh1( 22) and ex4_shctl_16(0) ) or ( ex4_sh1( 38) and ex4_shctl_16(1) ) ); +u_sh2x_23: ex4_sh2_x_b(23) <= not( (ex4_sh1( 23) and ex4_shctl_16(0) ) or ( ex4_sh1( 39) and ex4_shctl_16(1) ) ); +u_sh2x_24: ex4_sh2_x_b(24) <= not( (ex4_sh1( 24) and ex4_shctl_16(0) ) or ( ex4_sh1( 40) and ex4_shctl_16(1) ) ); +u_sh2x_25: ex4_sh2_x_b(25) <= not( (ex4_sh1( 25) and ex4_shctl_16(0) ) or ( ex4_sh1( 41) and ex4_shctl_16(1) ) ); +u_sh2x_26: ex4_sh2_x_b(26) <= not( (ex4_sh1( 26) and ex4_shctl_16(0) ) or ( ex4_sh1( 42) and ex4_shctl_16(1) ) ); +u_sh2x_27: ex4_sh2_x_b(27) <= not( (ex4_sh1( 27) and ex4_shctl_16(0) ) or ( ex4_sh1( 43) and ex4_shctl_16(1) ) ); +u_sh2x_28: ex4_sh2_x_b(28) <= not( (ex4_sh1( 28) and ex4_shctl_16(0) ) or ( ex4_sh1( 44) and ex4_shctl_16(1) ) ); +u_sh2x_29: ex4_sh2_x_b(29) <= not( (ex4_sh1( 29) and ex4_shctl_16(0) ) or ( ex4_sh1( 45) and ex4_shctl_16(1) ) ); +u_sh2x_30: ex4_sh2_x_b(30) <= not( (ex4_sh1( 30) and ex4_shctl_16(0) ) or ( ex4_sh1( 46) and ex4_shctl_16(1) ) ); +u_sh2x_31: ex4_sh2_x_b(31) <= not( (ex4_sh1( 31) and ex4_shctl_16(0) ) or ( ex4_sh1( 47) and ex4_shctl_16(1) ) ); +u_sh2x_32: ex4_sh2_x_b(32) <= not( (ex4_sh1( 32) and ex4_shctl_16(0) ) or ( ex4_sh1( 48) and ex4_shctl_16(1) ) ); +u_sh2x_33: ex4_sh2_x_b(33) <= not( (ex4_sh1( 33) and ex4_shctl_16(0) ) or ( ex4_sh1( 49) and ex4_shctl_16(1) ) ); +u_sh2x_34: ex4_sh2_x_b(34) <= not( (ex4_sh1( 34) and ex4_shctl_16(0) ) or ( ex4_sh1( 50) and ex4_shctl_16(1) ) ); +u_sh2x_35: ex4_sh2_x_b(35) <= not( (ex4_sh1( 35) and ex4_shctl_16(0) ) or ( ex4_sh1( 51) and ex4_shctl_16(1) ) ); +u_sh2x_36: ex4_sh2_x_b(36) <= not( (ex4_sh1( 36) and ex4_shctl_16(0) ) or ( ex4_sh1( 52) and ex4_shctl_16(1) ) ); +u_sh2x_37: ex4_sh2_x_b(37) <= not( (ex4_sh1( 37) and ex4_shctl_16(0) ) or ( ex4_sh1( 53) and ex4_shctl_16(1) ) ); +u_sh2x_38: ex4_sh2_x_b(38) <= not( (ex4_sh1( 38) and ex4_shctl_16(0) ) or ( ex4_sh1( 54) and ex4_shctl_16(1) ) ); +u_sh2x_39: ex4_sh2_x_b(39) <= not( (ex4_sh1( 39) and ex4_shctl_16(0) ) or ( ex4_sh1( 55) and ex4_shctl_16(1) ) ); +u_sh2x_40: ex4_sh2_x_b(40) <= not( (ex4_sh1( 40) and ex4_shctl_16(0) ) or ( ex4_sh1( 56) and ex4_shctl_16(1) ) ); +u_sh2x_41: ex4_sh2_x_b(41) <= not( (ex4_sh1( 41) and ex4_shctl_16(0) ) or ( ex4_sh1( 57) and ex4_shctl_16(1) ) ); +u_sh2x_42: ex4_sh2_x_b(42) <= not( (ex4_sh1( 42) and ex4_shctl_16(0) ) or ( ex4_sh1( 58) and ex4_shctl_16(1) ) ); +u_sh2x_43: ex4_sh2_x_b(43) <= not( (ex4_sh1( 43) and ex4_shctl_16(0) ) or ( ex4_sh1( 59) and ex4_shctl_16(1) ) ); +u_sh2x_44: ex4_sh2_x_b(44) <= not( (ex4_sh1( 44) and ex4_shctl_16(0) ) or ( ex4_sh1( 60) and ex4_shctl_16(1) ) ); +u_sh2x_45: ex4_sh2_x_b(45) <= not( (ex4_sh1( 45) and ex4_shctl_16(0) ) or ( ex4_sh1( 61) and ex4_shctl_16(1) ) ); +u_sh2x_46: ex4_sh2_x_b(46) <= not( (ex4_sh1( 46) and ex4_shctl_16(0) ) or ( ex4_sh1( 62) and ex4_shctl_16(1) ) ); +u_sh2x_47: ex4_sh2_x_b(47) <= not( (ex4_sh1( 47) and ex4_shctl_16(0) ) or ( ex4_sh1( 63) and ex4_shctl_16(1) ) ); +u_sh2x_48: ex4_sh2_x_b(48) <= not( (ex4_sh1( 48) and ex4_shctl_16(0) ) or ( ex4_sh1( 64) and ex4_shctl_16(1) ) ); +u_sh2x_49: ex4_sh2_x_b(49) <= not( (ex4_sh1( 49) and ex4_shctl_16(0) ) or ( ex4_sh1( 65) and ex4_shctl_16(1) ) ); +u_sh2x_50: ex4_sh2_x_b(50) <= not( (ex4_sh1( 50) and ex4_shctl_16(0) ) or ( ex4_sh1( 66) and ex4_shctl_16(1) ) ); +u_sh2x_51: ex4_sh2_x_b(51) <= not( (ex4_sh1( 51) and ex4_shctl_16(0) ) or ( ex4_sh1( 67) and ex4_shctl_16(1) ) ); +u_sh2x_52: ex4_sh2_x_b(52) <= not( (ex4_sh1( 52) and ex4_shctl_16(0) ) or ( ex4_sh1( 68) and ex4_shctl_16(1) ) ); +u_sh2x_53: ex4_sh2_x_b(53) <= not( (ex4_sh1( 53) and ex4_shctl_16(0) ) or ( ex4_sh1( 69) and ex4_shctl_16(1) ) ); +u_sh2x_54: ex4_sh2_x_b(54) <= not( (ex4_sh1( 54) and ex4_shctl_16(0) ) or ( ex4_sh1( 70) and ex4_shctl_16(1) ) ); +u_sh2x_55: ex4_sh2_x_b(55) <= not( (ex4_sh1( 55) and ex4_shctl_16(0) ) or ( ex4_sh1( 71) and ex4_shctl_16(1) ) ); +u_sh2x_56: ex4_sh2_x_b(56) <= not( (ex4_sh1( 56) and ex4_shctl_16(0) ) or ( ex4_sh1( 72) and ex4_shctl_16(1) ) ); +u_sh2x_57: ex4_sh2_x_b(57) <= not( (ex4_sh1( 57) and ex4_shctl_16(0) ) or ( ex4_sh1( 73) and ex4_shctl_16(1) ) ); +u_sh2x_58: ex4_sh2_x_b(58) <= not( (ex4_sh1( 58) and ex4_shctl_16(0) ) or ( ex4_sh1( 74) and ex4_shctl_16(1) ) ); +u_sh2x_59: ex4_sh2_x_b(59) <= not( (ex4_sh1( 59) and ex4_shctl_16(0) ) or ( ex4_sh1( 75) and ex4_shctl_16(1) ) ); +u_sh2x_60: ex4_sh2_x_b(60) <= not( (ex4_sh1( 60) and ex4_shctl_16(0) ) or ( ex4_sh1( 76) and ex4_shctl_16(1) ) ); +u_sh2x_61: ex4_sh2_x_b(61) <= not( (ex4_sh1( 61) and ex4_shctl_16(0) ) or ( ex4_sh1( 77) and ex4_shctl_16(1) ) ); +u_sh2x_62: ex4_sh2_x_b(62) <= not( (ex4_sh1( 62) and ex4_shctl_16(0) ) or ( ex4_sh1( 78) and ex4_shctl_16(1) ) ); +u_sh2x_63: ex4_sh2_x_b(63) <= not( (ex4_sh1( 63) and ex4_shctl_16(0) ) or ( ex4_sh1( 79) and ex4_shctl_16(1) ) ); +u_sh2x_64: ex4_sh2_x_b(64) <= not( (ex4_sh1( 64) and ex4_shctl_16(0) ) or ( ex4_sh1( 80) and ex4_shctl_16(1) ) ); +u_sh2x_65: ex4_sh2_x_b(65) <= not( (ex4_sh1( 65) and ex4_shctl_16(0) ) or ( ex4_sh1( 81) and ex4_shctl_16(1) ) ); +u_sh2x_66: ex4_sh2_x_b(66) <= not( (ex4_sh1( 66) and ex4_shctl_16(0) ) or ( ex4_sh1( 82) and ex4_shctl_16(1) ) ); +u_sh2x_67: ex4_sh2_x_b(67) <= not( (ex4_sh1( 67) and ex4_shctl_16(0) ) or ( ex4_sh1( 83) and ex4_shctl_16(1) ) ); +u_sh2x_68: ex4_sh2_x_b(68) <= not( (ex4_sh1( 68) and ex4_shctl_16(0) ) or ( ex4_sh1( 84) and ex4_shctl_16(1) ) ); +u_sh2x_69: ex4_sh2_x_b(69) <= not( (ex4_sh1( 69) and ex4_shctl_16(0) ) or ( ex4_sh1( 85) and ex4_shctl_16(1) ) ); +u_sh2x_70: ex4_sh2_x_b(70) <= not( (ex4_sh1( 70) and ex4_shctl_16(0) ) or ( ex4_sh1( 86) and ex4_shctl_16(1) ) ); +u_sh2x_71: ex4_sh2_x_b(71) <= not( (ex4_sh1( 71) and ex4_shctl_16(0) ) or ( ex4_sh1( 87) and ex4_shctl_16(1) ) ); +u_sh2x_72: ex4_sh2_x_b(72) <= not( (ex4_sh1( 72) and ex4_shctl_16(0) ) or ( ex4_sh1( 88) and ex4_shctl_16(1) ) ); + +u_sh2y_00: ex4_sh2_y_b( 0) <= not( (ex4_sh1( 32) and ex4_shctl_16(2) ) or ( ex4_sh1( 48) and ex4_shctl_16(3) ) ); +u_sh2y_01: ex4_sh2_y_b( 1) <= not( (ex4_sh1( 33) and ex4_shctl_16(2) ) or ( ex4_sh1( 49) and ex4_shctl_16(3) ) ); +u_sh2y_02: ex4_sh2_y_b( 2) <= not( (ex4_sh1( 34) and ex4_shctl_16(2) ) or ( ex4_sh1( 50) and ex4_shctl_16(3) ) ); +u_sh2y_03: ex4_sh2_y_b( 3) <= not( (ex4_sh1( 35) and ex4_shctl_16(2) ) or ( ex4_sh1( 51) and ex4_shctl_16(3) ) ); +u_sh2y_04: ex4_sh2_y_b( 4) <= not( (ex4_sh1( 36) and ex4_shctl_16(2) ) or ( ex4_sh1( 52) and ex4_shctl_16(3) ) ); +u_sh2y_05: ex4_sh2_y_b( 5) <= not( (ex4_sh1( 37) and ex4_shctl_16(2) ) or ( ex4_sh1( 53) and ex4_shctl_16(3) ) ); +u_sh2y_06: ex4_sh2_y_b( 6) <= not( (ex4_sh1( 38) and ex4_shctl_16(2) ) or ( ex4_sh1( 54) and ex4_shctl_16(3) ) ); +u_sh2y_07: ex4_sh2_y_b( 7) <= not( (ex4_sh1( 39) and ex4_shctl_16(2) ) or ( ex4_sh1( 55) and ex4_shctl_16(3) ) ); +u_sh2y_08: ex4_sh2_y_b( 8) <= not( (ex4_sh1( 40) and ex4_shctl_16(2) ) or ( ex4_sh1( 56) and ex4_shctl_16(3) ) ); +u_sh2y_09: ex4_sh2_y_b( 9) <= not( (ex4_sh1( 41) and ex4_shctl_16(2) ) or ( ex4_sh1( 57) and ex4_shctl_16(3) ) ); +u_sh2y_10: ex4_sh2_y_b(10) <= not( (ex4_sh1( 42) and ex4_shctl_16(2) ) or ( ex4_sh1( 58) and ex4_shctl_16(3) ) ); +u_sh2y_11: ex4_sh2_y_b(11) <= not( (ex4_sh1( 43) and ex4_shctl_16(2) ) or ( ex4_sh1( 59) and ex4_shctl_16(3) ) ); +u_sh2y_12: ex4_sh2_y_b(12) <= not( (ex4_sh1( 44) and ex4_shctl_16(2) ) or ( ex4_sh1( 60) and ex4_shctl_16(3) ) ); +u_sh2y_13: ex4_sh2_y_b(13) <= not( (ex4_sh1( 45) and ex4_shctl_16(2) ) or ( ex4_sh1( 61) and ex4_shctl_16(3) ) ); +u_sh2y_14: ex4_sh2_y_b(14) <= not( (ex4_sh1( 46) and ex4_shctl_16(2) ) or ( ex4_sh1( 62) and ex4_shctl_16(3) ) ); +u_sh2y_15: ex4_sh2_y_b(15) <= not( (ex4_sh1( 47) and ex4_shctl_16(2) ) or ( ex4_sh1( 63) and ex4_shctl_16(3) ) ); +u_sh2y_16: ex4_sh2_y_b(16) <= not( (ex4_sh1( 48) and ex4_shctl_16(2) ) or ( ex4_sh1( 64) and ex4_shctl_16(3) ) ); +u_sh2y_17: ex4_sh2_y_b(17) <= not( (ex4_sh1( 49) and ex4_shctl_16(2) ) or ( ex4_sh1( 65) and ex4_shctl_16(3) ) ); +u_sh2y_18: ex4_sh2_y_b(18) <= not( (ex4_sh1( 50) and ex4_shctl_16(2) ) or ( ex4_sh1( 66) and ex4_shctl_16(3) ) ); +u_sh2y_19: ex4_sh2_y_b(19) <= not( (ex4_sh1( 51) and ex4_shctl_16(2) ) or ( ex4_sh1( 67) and ex4_shctl_16(3) ) ); +u_sh2y_20: ex4_sh2_y_b(20) <= not( (ex4_sh1( 52) and ex4_shctl_16(2) ) or ( ex4_sh1( 68) and ex4_shctl_16(3) ) ); +u_sh2y_21: ex4_sh2_y_b(21) <= not( (ex4_sh1( 53) and ex4_shctl_16(2) ) or ( ex4_sh1( 69) and ex4_shctl_16(3) ) ); +u_sh2y_22: ex4_sh2_y_b(22) <= not( (ex4_sh1( 54) and ex4_shctl_16(2) ) or ( ex4_sh1( 70) and ex4_shctl_16(3) ) ); +u_sh2y_23: ex4_sh2_y_b(23) <= not( (ex4_sh1( 55) and ex4_shctl_16(2) ) or ( ex4_sh1( 71) and ex4_shctl_16(3) ) ); +u_sh2y_24: ex4_sh2_y_b(24) <= not( (ex4_sh1( 56) and ex4_shctl_16(2) ) or ( ex4_sh1( 72) and ex4_shctl_16(3) ) ); +u_sh2y_25: ex4_sh2_y_b(25) <= not( (ex4_sh1( 57) and ex4_shctl_16(2) ) or ( ex4_sh1( 73) and ex4_shctl_16(3) ) ); +u_sh2y_26: ex4_sh2_y_b(26) <= not( (ex4_sh1( 58) and ex4_shctl_16(2) ) or ( ex4_sh1( 74) and ex4_shctl_16(3) ) ); +u_sh2y_27: ex4_sh2_y_b(27) <= not( (ex4_sh1( 59) and ex4_shctl_16(2) ) or ( ex4_sh1( 75) and ex4_shctl_16(3) ) ); +u_sh2y_28: ex4_sh2_y_b(28) <= not( (ex4_sh1( 60) and ex4_shctl_16(2) ) or ( ex4_sh1( 76) and ex4_shctl_16(3) ) ); +u_sh2y_29: ex4_sh2_y_b(29) <= not( (ex4_sh1( 61) and ex4_shctl_16(2) ) or ( ex4_sh1( 77) and ex4_shctl_16(3) ) ); +u_sh2y_30: ex4_sh2_y_b(30) <= not( (ex4_sh1( 62) and ex4_shctl_16(2) ) or ( ex4_sh1( 78) and ex4_shctl_16(3) ) ); +u_sh2y_31: ex4_sh2_y_b(31) <= not( (ex4_sh1( 63) and ex4_shctl_16(2) ) or ( ex4_sh1( 79) and ex4_shctl_16(3) ) ); +u_sh2y_32: ex4_sh2_y_b(32) <= not( (ex4_sh1( 64) and ex4_shctl_16(2) ) or ( ex4_sh1( 80) and ex4_shctl_16(3) ) ); +u_sh2y_33: ex4_sh2_y_b(33) <= not( (ex4_sh1( 65) and ex4_shctl_16(2) ) or ( ex4_sh1( 81) and ex4_shctl_16(3) ) ); +u_sh2y_34: ex4_sh2_y_b(34) <= not( (ex4_sh1( 66) and ex4_shctl_16(2) ) or ( ex4_sh1( 82) and ex4_shctl_16(3) ) ); +u_sh2y_35: ex4_sh2_y_b(35) <= not( (ex4_sh1( 67) and ex4_shctl_16(2) ) or ( ex4_sh1( 83) and ex4_shctl_16(3) ) ); +u_sh2y_36: ex4_sh2_y_b(36) <= not( (ex4_sh1( 68) and ex4_shctl_16(2) ) or ( ex4_sh1( 84) and ex4_shctl_16(3) ) ); +u_sh2y_37: ex4_sh2_y_b(37) <= not( (ex4_sh1( 69) and ex4_shctl_16(2) ) or ( ex4_sh1( 85) and ex4_shctl_16(3) ) ); +u_sh2y_38: ex4_sh2_y_b(38) <= not( (ex4_sh1( 70) and ex4_shctl_16(2) ) or ( ex4_sh1( 86) and ex4_shctl_16(3) ) ); +u_sh2y_39: ex4_sh2_y_b(39) <= not( (ex4_sh1( 71) and ex4_shctl_16(2) ) or ( ex4_sh1( 87) and ex4_shctl_16(3) ) ); +u_sh2y_40: ex4_sh2_y_b(40) <= not( (ex4_sh1( 72) and ex4_shctl_16(2) ) or ( ex4_sh1( 88) and ex4_shctl_16(3) ) ); +u_sh2y_41: ex4_sh2_y_b(41) <= not( (ex4_sh1( 73) and ex4_shctl_16(2) ) or ( ex4_sh1( 89) and ex4_shctl_16(3) ) ); +u_sh2y_42: ex4_sh2_y_b(42) <= not( (ex4_sh1( 74) and ex4_shctl_16(2) ) or ( ex4_sh1( 90) and ex4_shctl_16(3) ) ); +u_sh2y_43: ex4_sh2_y_b(43) <= not( (ex4_sh1( 75) and ex4_shctl_16(2) ) or ( ex4_sh1( 91) and ex4_shctl_16(3) ) ); +u_sh2y_44: ex4_sh2_y_b(44) <= not( (ex4_sh1( 76) and ex4_shctl_16(2) ) or ( ex4_sh1( 92) and ex4_shctl_16(3) ) ); +u_sh2y_45: ex4_sh2_y_b(45) <= not( (ex4_sh1( 77) and ex4_shctl_16(2) ) or ( ex4_sh1( 93) and ex4_shctl_16(3) ) ); +u_sh2y_46: ex4_sh2_y_b(46) <= not( (ex4_sh1( 78) and ex4_shctl_16(2) ) or ( ex4_sh1( 94) and ex4_shctl_16(3) ) ); +u_sh2y_47: ex4_sh2_y_b(47) <= not( (ex4_sh1( 79) and ex4_shctl_16(2) ) or ( ex4_sh1( 95) and ex4_shctl_16(3) ) ); +u_sh2y_48: ex4_sh2_y_b(48) <= not( (ex4_sh1( 80) and ex4_shctl_16(2) ) or ( ex4_sh1( 96) and ex4_shctl_16(3) ) ); +u_sh2y_49: ex4_sh2_y_b(49) <= not( (ex4_sh1( 81) and ex4_shctl_16(2) ) or ( ex4_sh1( 97) and ex4_shctl_16(3) ) ); +u_sh2y_50: ex4_sh2_y_b(50) <= not( (ex4_sh1( 82) and ex4_shctl_16(2) ) or ( ex4_sh1( 98) and ex4_shctl_16(3) ) ); +u_sh2y_51: ex4_sh2_y_b(51) <= not( (ex4_sh1( 83) and ex4_shctl_16(2) ) or ( ex4_sh1( 99) and ex4_shctl_16(3) ) ); +u_sh2y_52: ex4_sh2_y_b(52) <= not( (ex4_sh1( 84) and ex4_shctl_16(2) ) or ( ex4_sh1(100) and ex4_shctl_16(3) ) ); +u_sh2y_53: ex4_sh2_y_b(53) <= not( (ex4_sh1( 85) and ex4_shctl_16(2) ) or ( ex4_sh1(101) and ex4_shctl_16(3) ) ); +u_sh2y_54: ex4_sh2_y_b(54) <= not( (ex4_sh1( 86) and ex4_shctl_16(2) ) or ( ex4_sh1(102) and ex4_shctl_16(3) ) ); +u_sh2y_55: ex4_sh2_y_b(55) <= not( (ex4_sh1( 87) and ex4_shctl_16(2) ) or ( ex4_sh1(103) and ex4_shctl_16(3) ) ); +u_sh2y_56: ex4_sh2_y_b(56) <= not( (ex4_sh1( 88) and ex4_shctl_16(2) ) or ( ex4_sh1(104) and ex4_shctl_16(3) ) ); +u_sh2y_57: ex4_sh2_y_b(57) <= not( (ex4_sh1( 89) and ex4_shctl_16(2) ) or ( ex4_sh1(105) and ex4_shctl_16(3) ) ); +u_sh2y_58: ex4_sh2_y_b(58) <= not( (ex4_sh1( 90) and ex4_shctl_16(2) ) or ( ex4_sh1(106) and ex4_shctl_16(3) ) ); +u_sh2y_59: ex4_sh2_y_b(59) <= not( (ex4_sh1( 91) and ex4_shctl_16(2) ) or ( ex4_sh1(107) and ex4_shctl_16(3) ) ); +u_sh2y_60: ex4_sh2_y_b(60) <= not( (ex4_sh1( 92) and ex4_shctl_16(2) ) or ( ex4_sh1(108) and ex4_shctl_16(3) ) ); +u_sh2y_61: ex4_sh2_y_b(61) <= not( (ex4_sh1( 93) and ex4_shctl_16(2) ) or ( ex4_sh1(109) and ex4_shctl_16(3) ) ); +u_sh2y_62: ex4_sh2_y_b(62) <= not( (ex4_sh1( 94) and ex4_shctl_16(2) ) or ( ex4_sh1(110) and ex4_shctl_16(3) ) ); +u_sh2y_63: ex4_sh2_y_b(63) <= not( (ex4_sh1( 95) and ex4_shctl_16(2) ) or ( ex4_sh1(111) and ex4_shctl_16(3) ) ); +u_sh2y_64: ex4_sh2_y_b(64) <= not( (ex4_sh1( 96) and ex4_shctl_16(2) ) or ( ex4_sh1(112) and ex4_shctl_16(3) ) ); +u_sh2y_65: ex4_sh2_y_b(65) <= not( (ex4_sh1( 97) and ex4_shctl_16(2) ) or ( ex4_sh1(113) and ex4_shctl_16(3) ) ); +u_sh2y_66: ex4_sh2_y_b(66) <= not( (ex4_sh1( 98) and ex4_shctl_16(2) ) or ( ex4_sh1(114) and ex4_shctl_16(3) ) ); +u_sh2y_67: ex4_sh2_y_b(67) <= not( (ex4_sh1( 99) and ex4_shctl_16(2) ) or ( ex4_sh1(115) and ex4_shctl_16(3) ) ); +u_sh2y_68: ex4_sh2_y_b(68) <= not( (ex4_sh1(100) and ex4_shctl_16(2) ) or ( ex4_sh1(116) and ex4_shctl_16(3) ) ); +u_sh2y_69: ex4_sh2_y_b(69) <= not( (ex4_sh1(101) and ex4_shctl_16(2) ) or ( ex4_sh1(117) and ex4_shctl_16(3) ) ); +u_sh2y_70: ex4_sh2_y_b(70) <= not( (ex4_sh1(102) and ex4_shctl_16(2) ) or ( ex4_sh1(118) and ex4_shctl_16(3) ) ); +u_sh2y_71: ex4_sh2_y_b(71) <= not( (ex4_sh1(103) and ex4_shctl_16(2) ) or ( ex4_sh1(119) and ex4_shctl_16(3) ) ); +u_sh2y_72: ex4_sh2_y_b(72) <= not( (ex4_sh1(104) and ex4_shctl_16(2) ) or ( ex4_sh1(120) and ex4_shctl_16(3) ) ); + + + +u_sh2_00: ex4_sh2( 0) <= not( ex4_sh2_x_b( 0) and ex4_sh2_y_b( 0) ); +u_sh2_01: ex4_sh2( 1) <= not( ex4_sh2_x_b( 1) and ex4_sh2_y_b( 1) ); +u_sh2_02: ex4_sh2( 2) <= not( ex4_sh2_x_b( 2) and ex4_sh2_y_b( 2) ); +u_sh2_03: ex4_sh2( 3) <= not( ex4_sh2_x_b( 3) and ex4_sh2_y_b( 3) ); +u_sh2_04: ex4_sh2( 4) <= not( ex4_sh2_x_b( 4) and ex4_sh2_y_b( 4) ); +u_sh2_05: ex4_sh2( 5) <= not( ex4_sh2_x_b( 5) and ex4_sh2_y_b( 5) ); +u_sh2_06: ex4_sh2( 6) <= not( ex4_sh2_x_b( 6) and ex4_sh2_y_b( 6) ); +u_sh2_07: ex4_sh2( 7) <= not( ex4_sh2_x_b( 7) and ex4_sh2_y_b( 7) ); +u_sh2_08: ex4_sh2( 8) <= not( ex4_sh2_x_b( 8) and ex4_sh2_y_b( 8) ); +u_sh2_09: ex4_sh2( 9) <= not( ex4_sh2_x_b( 9) and ex4_sh2_y_b( 9) ); +u_sh2_10: ex4_sh2(10) <= not( ex4_sh2_x_b(10) and ex4_sh2_y_b(10) ); +u_sh2_11: ex4_sh2(11) <= not( ex4_sh2_x_b(11) and ex4_sh2_y_b(11) ); +u_sh2_12: ex4_sh2(12) <= not( ex4_sh2_x_b(12) and ex4_sh2_y_b(12) ); +u_sh2_13: ex4_sh2(13) <= not( ex4_sh2_x_b(13) and ex4_sh2_y_b(13) ); +u_sh2_14: ex4_sh2(14) <= not( ex4_sh2_x_b(14) and ex4_sh2_y_b(14) ); +u_sh2_15: ex4_sh2(15) <= not( ex4_sh2_x_b(15) and ex4_sh2_y_b(15) ); +u_sh2_16: ex4_sh2(16) <= not( ex4_sh2_x_b(16) and ex4_sh2_y_b(16) ); +u_sh2_17: ex4_sh2(17) <= not( ex4_sh2_x_b(17) and ex4_sh2_y_b(17) ); +u_sh2_18: ex4_sh2(18) <= not( ex4_sh2_x_b(18) and ex4_sh2_y_b(18) ); +u_sh2_19: ex4_sh2(19) <= not( ex4_sh2_x_b(19) and ex4_sh2_y_b(19) ); +u_sh2_20: ex4_sh2(20) <= not( ex4_sh2_x_b(20) and ex4_sh2_y_b(20) ); +u_sh2_21: ex4_sh2(21) <= not( ex4_sh2_x_b(21) and ex4_sh2_y_b(21) ); +u_sh2_22: ex4_sh2(22) <= not( ex4_sh2_x_b(22) and ex4_sh2_y_b(22) ); +u_sh2_23: ex4_sh2(23) <= not( ex4_sh2_x_b(23) and ex4_sh2_y_b(23) ); +u_sh2_24: ex4_sh2(24) <= not( ex4_sh2_x_b(24) and ex4_sh2_y_b(24) ); +u_sh2_25: ex4_sh2(25) <= not( ex4_sh2_x_b(25) and ex4_sh2_y_b(25) ); +u_sh2_26: ex4_sh2(26) <= not( ex4_sh2_x_b(26) and ex4_sh2_y_b(26) ); +u_sh2_27: ex4_sh2(27) <= not( ex4_sh2_x_b(27) and ex4_sh2_y_b(27) ); +u_sh2_28: ex4_sh2(28) <= not( ex4_sh2_x_b(28) and ex4_sh2_y_b(28) ); +u_sh2_29: ex4_sh2(29) <= not( ex4_sh2_x_b(29) and ex4_sh2_y_b(29) ); +u_sh2_30: ex4_sh2(30) <= not( ex4_sh2_x_b(30) and ex4_sh2_y_b(30) ); +u_sh2_31: ex4_sh2(31) <= not( ex4_sh2_x_b(31) and ex4_sh2_y_b(31) ); +u_sh2_32: ex4_sh2(32) <= not( ex4_sh2_x_b(32) and ex4_sh2_y_b(32) ); +u_sh2_33: ex4_sh2(33) <= not( ex4_sh2_x_b(33) and ex4_sh2_y_b(33) ); +u_sh2_34: ex4_sh2(34) <= not( ex4_sh2_x_b(34) and ex4_sh2_y_b(34) ); +u_sh2_35: ex4_sh2(35) <= not( ex4_sh2_x_b(35) and ex4_sh2_y_b(35) ); +u_sh2_36: ex4_sh2(36) <= not( ex4_sh2_x_b(36) and ex4_sh2_y_b(36) ); +u_sh2_37: ex4_sh2(37) <= not( ex4_sh2_x_b(37) and ex4_sh2_y_b(37) ); +u_sh2_38: ex4_sh2(38) <= not( ex4_sh2_x_b(38) and ex4_sh2_y_b(38) ); +u_sh2_39: ex4_sh2(39) <= not( ex4_sh2_x_b(39) and ex4_sh2_y_b(39) ); +u_sh2_40: ex4_sh2(40) <= not( ex4_sh2_x_b(40) and ex4_sh2_y_b(40) ); +u_sh2_41: ex4_sh2(41) <= not( ex4_sh2_x_b(41) and ex4_sh2_y_b(41) ); +u_sh2_42: ex4_sh2(42) <= not( ex4_sh2_x_b(42) and ex4_sh2_y_b(42) ); +u_sh2_43: ex4_sh2(43) <= not( ex4_sh2_x_b(43) and ex4_sh2_y_b(43) ); +u_sh2_44: ex4_sh2(44) <= not( ex4_sh2_x_b(44) and ex4_sh2_y_b(44) ); +u_sh2_45: ex4_sh2(45) <= not( ex4_sh2_x_b(45) and ex4_sh2_y_b(45) ); +u_sh2_46: ex4_sh2(46) <= not( ex4_sh2_x_b(46) and ex4_sh2_y_b(46) ); +u_sh2_47: ex4_sh2(47) <= not( ex4_sh2_x_b(47) and ex4_sh2_y_b(47) ); +u_sh2_48: ex4_sh2(48) <= not( ex4_sh2_x_b(48) and ex4_sh2_y_b(48) ); +u_sh2_49: ex4_sh2(49) <= not( ex4_sh2_x_b(49) and ex4_sh2_y_b(49) ); +u_sh2_50: ex4_sh2(50) <= not( ex4_sh2_x_b(50) and ex4_sh2_y_b(50) ); +u_sh2_51: ex4_sh2(51) <= not( ex4_sh2_x_b(51) and ex4_sh2_y_b(51) ); +u_sh2_52: ex4_sh2(52) <= not( ex4_sh2_x_b(52) and ex4_sh2_y_b(52) ); +u_sh2_53: ex4_sh2(53) <= not( ex4_sh2_x_b(53) and ex4_sh2_y_b(53) ); +u_sh2_54: ex4_sh2(54) <= not( ex4_sh2_x_b(54) and ex4_sh2_y_b(54) ); +u_sh2_55: ex4_sh2(55) <= not( ex4_sh2_x_b(55) and ex4_sh2_y_b(55) ); +u_sh2_56: ex4_sh2(56) <= not( ex4_sh2_x_b(56) and ex4_sh2_y_b(56) ); +u_sh2_57: ex4_sh2(57) <= not( ex4_sh2_x_b(57) and ex4_sh2_y_b(57) ); +u_sh2_58: ex4_sh2(58) <= not( ex4_sh2_x_b(58) and ex4_sh2_y_b(58) ); +u_sh2_59: ex4_sh2(59) <= not( ex4_sh2_x_b(59) and ex4_sh2_y_b(59) ); +u_sh2_60: ex4_sh2(60) <= not( ex4_sh2_x_b(60) and ex4_sh2_y_b(60) ); +u_sh2_61: ex4_sh2(61) <= not( ex4_sh2_x_b(61) and ex4_sh2_y_b(61) ); +u_sh2_62: ex4_sh2(62) <= not( ex4_sh2_x_b(62) and ex4_sh2_y_b(62) ); +u_sh2_63: ex4_sh2(63) <= not( ex4_sh2_x_b(63) and ex4_sh2_y_b(63) ); +u_sh2_64: ex4_sh2(64) <= not( ex4_sh2_x_b(64) and ex4_sh2_y_b(64) ); +u_sh2_65: ex4_sh2(65) <= not( ex4_sh2_x_b(65) and ex4_sh2_y_b(65) ); +u_sh2_66: ex4_sh2(66) <= not( ex4_sh2_x_b(66) and ex4_sh2_y_b(66) ); +u_sh2_67: ex4_sh2(67) <= not( ex4_sh2_x_b(67) and ex4_sh2_y_b(67) ); +u_sh2_68: ex4_sh2(68) <= not( ex4_sh2_x_b(68) and ex4_sh2_y_b(68) ); +u_sh2_69: ex4_sh2(69) <= not( ex4_sh2_x_b(69) and ex4_sh2_y_b(69) ); +u_sh2_70: ex4_sh2(70) <= not( ex4_sh2_x_b(70) and ex4_sh2_y_b(70) ); +u_sh2_71: ex4_sh2(71) <= not( ex4_sh2_x_b(71) and ex4_sh2_y_b(71) ); +u_sh2_72: ex4_sh2(72) <= not( ex4_sh2_x_b(72) and ex4_sh2_y_b(72) ); + + + +u_sh3x_00: ex4_sh3_x_b( 0) <= not( (ex4_sh2( 0) and ex4_shctl_04(0) ) or ( ex4_sh2( 4) and ex4_shctl_04(1) ) ); +u_sh3x_01: ex4_sh3_x_b( 1) <= not( (ex4_sh2( 1) and ex4_shctl_04(0) ) or ( ex4_sh2( 5) and ex4_shctl_04(1) ) ); +u_sh3x_02: ex4_sh3_x_b( 2) <= not( (ex4_sh2( 2) and ex4_shctl_04(0) ) or ( ex4_sh2( 6) and ex4_shctl_04(1) ) ); +u_sh3x_03: ex4_sh3_x_b( 3) <= not( (ex4_sh2( 3) and ex4_shctl_04(0) ) or ( ex4_sh2( 7) and ex4_shctl_04(1) ) ); +u_sh3x_04: ex4_sh3_x_b( 4) <= not( (ex4_sh2( 4) and ex4_shctl_04(0) ) or ( ex4_sh2( 8) and ex4_shctl_04(1) ) ); +u_sh3x_05: ex4_sh3_x_b( 5) <= not( (ex4_sh2( 5) and ex4_shctl_04(0) ) or ( ex4_sh2( 9) and ex4_shctl_04(1) ) ); +u_sh3x_06: ex4_sh3_x_b( 6) <= not( (ex4_sh2( 6) and ex4_shctl_04(0) ) or ( ex4_sh2(10) and ex4_shctl_04(1) ) ); +u_sh3x_07: ex4_sh3_x_b( 7) <= not( (ex4_sh2( 7) and ex4_shctl_04(0) ) or ( ex4_sh2(11) and ex4_shctl_04(1) ) ); +u_sh3x_08: ex4_sh3_x_b( 8) <= not( (ex4_sh2( 8) and ex4_shctl_04(0) ) or ( ex4_sh2(12) and ex4_shctl_04(1) ) ); +u_sh3x_09: ex4_sh3_x_b( 9) <= not( (ex4_sh2( 9) and ex4_shctl_04(0) ) or ( ex4_sh2(13) and ex4_shctl_04(1) ) ); +u_sh3x_10: ex4_sh3_x_b(10) <= not( (ex4_sh2(10) and ex4_shctl_04(0) ) or ( ex4_sh2(14) and ex4_shctl_04(1) ) ); +u_sh3x_11: ex4_sh3_x_b(11) <= not( (ex4_sh2(11) and ex4_shctl_04(0) ) or ( ex4_sh2(15) and ex4_shctl_04(1) ) ); +u_sh3x_12: ex4_sh3_x_b(12) <= not( (ex4_sh2(12) and ex4_shctl_04(0) ) or ( ex4_sh2(16) and ex4_shctl_04(1) ) ); +u_sh3x_13: ex4_sh3_x_b(13) <= not( (ex4_sh2(13) and ex4_shctl_04(0) ) or ( ex4_sh2(17) and ex4_shctl_04(1) ) ); +u_sh3x_14: ex4_sh3_x_b(14) <= not( (ex4_sh2(14) and ex4_shctl_04(0) ) or ( ex4_sh2(18) and ex4_shctl_04(1) ) ); +u_sh3x_15: ex4_sh3_x_b(15) <= not( (ex4_sh2(15) and ex4_shctl_04(0) ) or ( ex4_sh2(19) and ex4_shctl_04(1) ) ); +u_sh3x_16: ex4_sh3_x_b(16) <= not( (ex4_sh2(16) and ex4_shctl_04(0) ) or ( ex4_sh2(20) and ex4_shctl_04(1) ) ); +u_sh3x_17: ex4_sh3_x_b(17) <= not( (ex4_sh2(17) and ex4_shctl_04(0) ) or ( ex4_sh2(21) and ex4_shctl_04(1) ) ); +u_sh3x_18: ex4_sh3_x_b(18) <= not( (ex4_sh2(18) and ex4_shctl_04(0) ) or ( ex4_sh2(22) and ex4_shctl_04(1) ) ); +u_sh3x_19: ex4_sh3_x_b(19) <= not( (ex4_sh2(19) and ex4_shctl_04(0) ) or ( ex4_sh2(23) and ex4_shctl_04(1) ) ); +u_sh3x_20: ex4_sh3_x_b(20) <= not( (ex4_sh2(20) and ex4_shctl_04(0) ) or ( ex4_sh2(24) and ex4_shctl_04(1) ) ); +u_sh3x_21: ex4_sh3_x_b(21) <= not( (ex4_sh2(21) and ex4_shctl_04(0) ) or ( ex4_sh2(25) and ex4_shctl_04(1) ) ); +u_sh3x_22: ex4_sh3_x_b(22) <= not( (ex4_sh2(22) and ex4_shctl_04(0) ) or ( ex4_sh2(26) and ex4_shctl_04(1) ) ); +u_sh3x_23: ex4_sh3_x_b(23) <= not( (ex4_sh2(23) and ex4_shctl_04(0) ) or ( ex4_sh2(27) and ex4_shctl_04(1) ) ); +u_sh3x_24: ex4_sh3_x_b(24) <= not( (ex4_sh2(24) and ex4_shctl_04(0) ) or ( ex4_sh2(28) and ex4_shctl_04(1) ) ); +u_sh3x_25: ex4_sh3_x_b(25) <= not( (ex4_sh2(25) and ex4_shctl_04(0) ) or ( ex4_sh2(29) and ex4_shctl_04(1) ) ); +u_sh3x_26: ex4_sh3_x_b(26) <= not( (ex4_sh2(26) and ex4_shctl_04(0) ) or ( ex4_sh2(30) and ex4_shctl_04(1) ) ); +u_sh3x_27: ex4_sh3_x_b(27) <= not( (ex4_sh2(27) and ex4_shctl_04(0) ) or ( ex4_sh2(31) and ex4_shctl_04(1) ) ); +u_sh3x_28: ex4_sh3_x_b(28) <= not( (ex4_sh2(28) and ex4_shctl_04(0) ) or ( ex4_sh2(32) and ex4_shctl_04(1) ) ); +u_sh3x_29: ex4_sh3_x_b(29) <= not( (ex4_sh2(29) and ex4_shctl_04(0) ) or ( ex4_sh2(33) and ex4_shctl_04(1) ) ); +u_sh3x_30: ex4_sh3_x_b(30) <= not( (ex4_sh2(30) and ex4_shctl_04(0) ) or ( ex4_sh2(34) and ex4_shctl_04(1) ) ); +u_sh3x_31: ex4_sh3_x_b(31) <= not( (ex4_sh2(31) and ex4_shctl_04(0) ) or ( ex4_sh2(35) and ex4_shctl_04(1) ) ); +u_sh3x_32: ex4_sh3_x_b(32) <= not( (ex4_sh2(32) and ex4_shctl_04(0) ) or ( ex4_sh2(36) and ex4_shctl_04(1) ) ); +u_sh3x_33: ex4_sh3_x_b(33) <= not( (ex4_sh2(33) and ex4_shctl_04(0) ) or ( ex4_sh2(37) and ex4_shctl_04(1) ) ); +u_sh3x_34: ex4_sh3_x_b(34) <= not( (ex4_sh2(34) and ex4_shctl_04(0) ) or ( ex4_sh2(38) and ex4_shctl_04(1) ) ); +u_sh3x_35: ex4_sh3_x_b(35) <= not( (ex4_sh2(35) and ex4_shctl_04(0) ) or ( ex4_sh2(39) and ex4_shctl_04(1) ) ); +u_sh3x_36: ex4_sh3_x_b(36) <= not( (ex4_sh2(36) and ex4_shctl_04(0) ) or ( ex4_sh2(40) and ex4_shctl_04(1) ) ); +u_sh3x_37: ex4_sh3_x_b(37) <= not( (ex4_sh2(37) and ex4_shctl_04(0) ) or ( ex4_sh2(41) and ex4_shctl_04(1) ) ); +u_sh3x_38: ex4_sh3_x_b(38) <= not( (ex4_sh2(38) and ex4_shctl_04(0) ) or ( ex4_sh2(42) and ex4_shctl_04(1) ) ); +u_sh3x_39: ex4_sh3_x_b(39) <= not( (ex4_sh2(39) and ex4_shctl_04(0) ) or ( ex4_sh2(43) and ex4_shctl_04(1) ) ); +u_sh3x_40: ex4_sh3_x_b(40) <= not( (ex4_sh2(40) and ex4_shctl_04(0) ) or ( ex4_sh2(44) and ex4_shctl_04(1) ) ); +u_sh3x_41: ex4_sh3_x_b(41) <= not( (ex4_sh2(41) and ex4_shctl_04(0) ) or ( ex4_sh2(45) and ex4_shctl_04(1) ) ); +u_sh3x_42: ex4_sh3_x_b(42) <= not( (ex4_sh2(42) and ex4_shctl_04(0) ) or ( ex4_sh2(46) and ex4_shctl_04(1) ) ); +u_sh3x_43: ex4_sh3_x_b(43) <= not( (ex4_sh2(43) and ex4_shctl_04(0) ) or ( ex4_sh2(47) and ex4_shctl_04(1) ) ); +u_sh3x_44: ex4_sh3_x_b(44) <= not( (ex4_sh2(44) and ex4_shctl_04(0) ) or ( ex4_sh2(48) and ex4_shctl_04(1) ) ); +u_sh3x_45: ex4_sh3_x_b(45) <= not( (ex4_sh2(45) and ex4_shctl_04(0) ) or ( ex4_sh2(49) and ex4_shctl_04(1) ) ); +u_sh3x_46: ex4_sh3_x_b(46) <= not( (ex4_sh2(46) and ex4_shctl_04(0) ) or ( ex4_sh2(50) and ex4_shctl_04(1) ) ); +u_sh3x_47: ex4_sh3_x_b(47) <= not( (ex4_sh2(47) and ex4_shctl_04(0) ) or ( ex4_sh2(51) and ex4_shctl_04(1) ) ); +u_sh3x_48: ex4_sh3_x_b(48) <= not( (ex4_sh2(48) and ex4_shctl_04(0) ) or ( ex4_sh2(52) and ex4_shctl_04(1) ) ); +u_sh3x_49: ex4_sh3_x_b(49) <= not( (ex4_sh2(49) and ex4_shctl_04(0) ) or ( ex4_sh2(53) and ex4_shctl_04(1) ) ); +u_sh3x_50: ex4_sh3_x_b(50) <= not( (ex4_sh2(50) and ex4_shctl_04(0) ) or ( ex4_sh2(54) and ex4_shctl_04(1) ) ); +u_sh3x_51: ex4_sh3_x_b(51) <= not( (ex4_sh2(51) and ex4_shctl_04(0) ) or ( ex4_sh2(55) and ex4_shctl_04(1) ) ); +u_sh3x_52: ex4_sh3_x_b(52) <= not( (ex4_sh2(52) and ex4_shctl_04(0) ) or ( ex4_sh2(56) and ex4_shctl_04(1) ) ); +u_sh3x_53: ex4_sh3_x_b(53) <= not( (ex4_sh2(53) and ex4_shctl_04(0) ) or ( ex4_sh2(57) and ex4_shctl_04(1) ) ); +u_sh3x_54: ex4_sh3_x_b(54) <= not( (ex4_sh2(54) and ex4_shctl_04(0) ) or ( ex4_sh2(58) and ex4_shctl_04(1) ) ); +u_sh3x_55: ex4_sh3_x_b(55) <= not( (ex4_sh2(55) and ex4_shctl_04(0) ) or ( ex4_sh2(59) and ex4_shctl_04(1) ) ); +u_sh3x_56: ex4_sh3_x_b(56) <= not( (ex4_sh2(56) and ex4_shctl_04(0) ) or ( ex4_sh2(60) and ex4_shctl_04(1) ) ); +u_sh3x_57: ex4_sh3_x_b(57) <= not( (ex4_sh2(57) and ex4_shctl_04(0) ) or ( ex4_sh2(61) and ex4_shctl_04(1) ) ); + +u_sh3y_00: ex4_sh3_y_b( 0) <= not( (ex4_sh2( 8) and ex4_shctl_04(2) ) or ( ex4_sh2(12) and ex4_shctl_04(3) ) ); +u_sh3y_01: ex4_sh3_y_b( 1) <= not( (ex4_sh2( 9) and ex4_shctl_04(2) ) or ( ex4_sh2(13) and ex4_shctl_04(3) ) ); +u_sh3y_02: ex4_sh3_y_b( 2) <= not( (ex4_sh2(10) and ex4_shctl_04(2) ) or ( ex4_sh2(14) and ex4_shctl_04(3) ) ); +u_sh3y_03: ex4_sh3_y_b( 3) <= not( (ex4_sh2(11) and ex4_shctl_04(2) ) or ( ex4_sh2(15) and ex4_shctl_04(3) ) ); +u_sh3y_04: ex4_sh3_y_b( 4) <= not( (ex4_sh2(12) and ex4_shctl_04(2) ) or ( ex4_sh2(16) and ex4_shctl_04(3) ) ); +u_sh3y_05: ex4_sh3_y_b( 5) <= not( (ex4_sh2(13) and ex4_shctl_04(2) ) or ( ex4_sh2(17) and ex4_shctl_04(3) ) ); +u_sh3y_06: ex4_sh3_y_b( 6) <= not( (ex4_sh2(14) and ex4_shctl_04(2) ) or ( ex4_sh2(18) and ex4_shctl_04(3) ) ); +u_sh3y_07: ex4_sh3_y_b( 7) <= not( (ex4_sh2(15) and ex4_shctl_04(2) ) or ( ex4_sh2(19) and ex4_shctl_04(3) ) ); +u_sh3y_08: ex4_sh3_y_b( 8) <= not( (ex4_sh2(16) and ex4_shctl_04(2) ) or ( ex4_sh2(20) and ex4_shctl_04(3) ) ); +u_sh3y_09: ex4_sh3_y_b( 9) <= not( (ex4_sh2(17) and ex4_shctl_04(2) ) or ( ex4_sh2(21) and ex4_shctl_04(3) ) ); +u_sh3y_10: ex4_sh3_y_b(10) <= not( (ex4_sh2(18) and ex4_shctl_04(2) ) or ( ex4_sh2(22) and ex4_shctl_04(3) ) ); +u_sh3y_11: ex4_sh3_y_b(11) <= not( (ex4_sh2(19) and ex4_shctl_04(2) ) or ( ex4_sh2(23) and ex4_shctl_04(3) ) ); +u_sh3y_12: ex4_sh3_y_b(12) <= not( (ex4_sh2(20) and ex4_shctl_04(2) ) or ( ex4_sh2(24) and ex4_shctl_04(3) ) ); +u_sh3y_13: ex4_sh3_y_b(13) <= not( (ex4_sh2(21) and ex4_shctl_04(2) ) or ( ex4_sh2(25) and ex4_shctl_04(3) ) ); +u_sh3y_14: ex4_sh3_y_b(14) <= not( (ex4_sh2(22) and ex4_shctl_04(2) ) or ( ex4_sh2(26) and ex4_shctl_04(3) ) ); +u_sh3y_15: ex4_sh3_y_b(15) <= not( (ex4_sh2(23) and ex4_shctl_04(2) ) or ( ex4_sh2(27) and ex4_shctl_04(3) ) ); +u_sh3y_16: ex4_sh3_y_b(16) <= not( (ex4_sh2(24) and ex4_shctl_04(2) ) or ( ex4_sh2(28) and ex4_shctl_04(3) ) ); +u_sh3y_17: ex4_sh3_y_b(17) <= not( (ex4_sh2(25) and ex4_shctl_04(2) ) or ( ex4_sh2(29) and ex4_shctl_04(3) ) ); +u_sh3y_18: ex4_sh3_y_b(18) <= not( (ex4_sh2(26) and ex4_shctl_04(2) ) or ( ex4_sh2(30) and ex4_shctl_04(3) ) ); +u_sh3y_19: ex4_sh3_y_b(19) <= not( (ex4_sh2(27) and ex4_shctl_04(2) ) or ( ex4_sh2(31) and ex4_shctl_04(3) ) ); +u_sh3y_20: ex4_sh3_y_b(20) <= not( (ex4_sh2(28) and ex4_shctl_04(2) ) or ( ex4_sh2(32) and ex4_shctl_04(3) ) ); +u_sh3y_21: ex4_sh3_y_b(21) <= not( (ex4_sh2(29) and ex4_shctl_04(2) ) or ( ex4_sh2(33) and ex4_shctl_04(3) ) ); +u_sh3y_22: ex4_sh3_y_b(22) <= not( (ex4_sh2(30) and ex4_shctl_04(2) ) or ( ex4_sh2(34) and ex4_shctl_04(3) ) ); +u_sh3y_23: ex4_sh3_y_b(23) <= not( (ex4_sh2(31) and ex4_shctl_04(2) ) or ( ex4_sh2(35) and ex4_shctl_04(3) ) ); +u_sh3y_24: ex4_sh3_y_b(24) <= not( (ex4_sh2(32) and ex4_shctl_04(2) ) or ( ex4_sh2(36) and ex4_shctl_04(3) ) ); +u_sh3y_25: ex4_sh3_y_b(25) <= not( (ex4_sh2(33) and ex4_shctl_04(2) ) or ( ex4_sh2(37) and ex4_shctl_04(3) ) ); +u_sh3y_26: ex4_sh3_y_b(26) <= not( (ex4_sh2(34) and ex4_shctl_04(2) ) or ( ex4_sh2(38) and ex4_shctl_04(3) ) ); +u_sh3y_27: ex4_sh3_y_b(27) <= not( (ex4_sh2(35) and ex4_shctl_04(2) ) or ( ex4_sh2(39) and ex4_shctl_04(3) ) ); +u_sh3y_28: ex4_sh3_y_b(28) <= not( (ex4_sh2(36) and ex4_shctl_04(2) ) or ( ex4_sh2(40) and ex4_shctl_04(3) ) ); +u_sh3y_29: ex4_sh3_y_b(29) <= not( (ex4_sh2(37) and ex4_shctl_04(2) ) or ( ex4_sh2(41) and ex4_shctl_04(3) ) ); +u_sh3y_30: ex4_sh3_y_b(30) <= not( (ex4_sh2(38) and ex4_shctl_04(2) ) or ( ex4_sh2(42) and ex4_shctl_04(3) ) ); +u_sh3y_31: ex4_sh3_y_b(31) <= not( (ex4_sh2(39) and ex4_shctl_04(2) ) or ( ex4_sh2(43) and ex4_shctl_04(3) ) ); +u_sh3y_32: ex4_sh3_y_b(32) <= not( (ex4_sh2(40) and ex4_shctl_04(2) ) or ( ex4_sh2(44) and ex4_shctl_04(3) ) ); +u_sh3y_33: ex4_sh3_y_b(33) <= not( (ex4_sh2(41) and ex4_shctl_04(2) ) or ( ex4_sh2(45) and ex4_shctl_04(3) ) ); +u_sh3y_34: ex4_sh3_y_b(34) <= not( (ex4_sh2(42) and ex4_shctl_04(2) ) or ( ex4_sh2(46) and ex4_shctl_04(3) ) ); +u_sh3y_35: ex4_sh3_y_b(35) <= not( (ex4_sh2(43) and ex4_shctl_04(2) ) or ( ex4_sh2(47) and ex4_shctl_04(3) ) ); +u_sh3y_36: ex4_sh3_y_b(36) <= not( (ex4_sh2(44) and ex4_shctl_04(2) ) or ( ex4_sh2(48) and ex4_shctl_04(3) ) ); +u_sh3y_37: ex4_sh3_y_b(37) <= not( (ex4_sh2(45) and ex4_shctl_04(2) ) or ( ex4_sh2(49) and ex4_shctl_04(3) ) ); +u_sh3y_38: ex4_sh3_y_b(38) <= not( (ex4_sh2(46) and ex4_shctl_04(2) ) or ( ex4_sh2(50) and ex4_shctl_04(3) ) ); +u_sh3y_39: ex4_sh3_y_b(39) <= not( (ex4_sh2(47) and ex4_shctl_04(2) ) or ( ex4_sh2(51) and ex4_shctl_04(3) ) ); +u_sh3y_40: ex4_sh3_y_b(40) <= not( (ex4_sh2(48) and ex4_shctl_04(2) ) or ( ex4_sh2(52) and ex4_shctl_04(3) ) ); +u_sh3y_41: ex4_sh3_y_b(41) <= not( (ex4_sh2(49) and ex4_shctl_04(2) ) or ( ex4_sh2(53) and ex4_shctl_04(3) ) ); +u_sh3y_42: ex4_sh3_y_b(42) <= not( (ex4_sh2(50) and ex4_shctl_04(2) ) or ( ex4_sh2(54) and ex4_shctl_04(3) ) ); +u_sh3y_43: ex4_sh3_y_b(43) <= not( (ex4_sh2(51) and ex4_shctl_04(2) ) or ( ex4_sh2(55) and ex4_shctl_04(3) ) ); +u_sh3y_44: ex4_sh3_y_b(44) <= not( (ex4_sh2(52) and ex4_shctl_04(2) ) or ( ex4_sh2(56) and ex4_shctl_04(3) ) ); +u_sh3y_45: ex4_sh3_y_b(45) <= not( (ex4_sh2(53) and ex4_shctl_04(2) ) or ( ex4_sh2(57) and ex4_shctl_04(3) ) ); +u_sh3y_46: ex4_sh3_y_b(46) <= not( (ex4_sh2(54) and ex4_shctl_04(2) ) or ( ex4_sh2(58) and ex4_shctl_04(3) ) ); +u_sh3y_47: ex4_sh3_y_b(47) <= not( (ex4_sh2(55) and ex4_shctl_04(2) ) or ( ex4_sh2(59) and ex4_shctl_04(3) ) ); +u_sh3y_48: ex4_sh3_y_b(48) <= not( (ex4_sh2(56) and ex4_shctl_04(2) ) or ( ex4_sh2(60) and ex4_shctl_04(3) ) ); +u_sh3y_49: ex4_sh3_y_b(49) <= not( (ex4_sh2(57) and ex4_shctl_04(2) ) or ( ex4_sh2(61) and ex4_shctl_04(3) ) ); +u_sh3y_50: ex4_sh3_y_b(50) <= not( (ex4_sh2(58) and ex4_shctl_04(2) ) or ( ex4_sh2(62) and ex4_shctl_04(3) ) ); +u_sh3y_51: ex4_sh3_y_b(51) <= not( (ex4_sh2(59) and ex4_shctl_04(2) ) or ( ex4_sh2(63) and ex4_shctl_04(3) ) ); +u_sh3y_52: ex4_sh3_y_b(52) <= not( (ex4_sh2(60) and ex4_shctl_04(2) ) or ( ex4_sh2(64) and ex4_shctl_04(3) ) ); +u_sh3y_53: ex4_sh3_y_b(53) <= not( (ex4_sh2(61) and ex4_shctl_04(2) ) or ( ex4_sh2(65) and ex4_shctl_04(3) ) ); +u_sh3y_54: ex4_sh3_y_b(54) <= not( (ex4_sh2(62) and ex4_shctl_04(2) ) or ( ex4_sh2(66) and ex4_shctl_04(3) ) ); +u_sh3y_55: ex4_sh3_y_b(55) <= not( (ex4_sh2(63) and ex4_shctl_04(2) ) or ( ex4_sh2(67) and ex4_shctl_04(3) ) ); +u_sh3y_56: ex4_sh3_y_b(56) <= not( (ex4_sh2(64) and ex4_shctl_04(2) ) or ( ex4_sh2(68) and ex4_shctl_04(3) ) ); +u_sh3y_57: ex4_sh3_y_b(57) <= not( (ex4_sh2(65) and ex4_shctl_04(2) ) or ( ex4_sh2(69) and ex4_shctl_04(3) ) ); + +u_sh3_00: ex4_sh3( 0) <= not( ex4_sh3_x_b( 0) and ex4_sh3_y_b( 0) ); +u_sh3_01: ex4_sh3( 1) <= not( ex4_sh3_x_b( 1) and ex4_sh3_y_b( 1) ); +u_sh3_02: ex4_sh3( 2) <= not( ex4_sh3_x_b( 2) and ex4_sh3_y_b( 2) ); +u_sh3_03: ex4_sh3( 3) <= not( ex4_sh3_x_b( 3) and ex4_sh3_y_b( 3) ); +u_sh3_04: ex4_sh3( 4) <= not( ex4_sh3_x_b( 4) and ex4_sh3_y_b( 4) ); +u_sh3_05: ex4_sh3( 5) <= not( ex4_sh3_x_b( 5) and ex4_sh3_y_b( 5) ); +u_sh3_06: ex4_sh3( 6) <= not( ex4_sh3_x_b( 6) and ex4_sh3_y_b( 6) ); +u_sh3_07: ex4_sh3( 7) <= not( ex4_sh3_x_b( 7) and ex4_sh3_y_b( 7) ); +u_sh3_08: ex4_sh3( 8) <= not( ex4_sh3_x_b( 8) and ex4_sh3_y_b( 8) ); +u_sh3_09: ex4_sh3( 9) <= not( ex4_sh3_x_b( 9) and ex4_sh3_y_b( 9) ); +u_sh3_10: ex4_sh3(10) <= not( ex4_sh3_x_b(10) and ex4_sh3_y_b(10) ); +u_sh3_11: ex4_sh3(11) <= not( ex4_sh3_x_b(11) and ex4_sh3_y_b(11) ); +u_sh3_12: ex4_sh3(12) <= not( ex4_sh3_x_b(12) and ex4_sh3_y_b(12) ); +u_sh3_13: ex4_sh3(13) <= not( ex4_sh3_x_b(13) and ex4_sh3_y_b(13) ); +u_sh3_14: ex4_sh3(14) <= not( ex4_sh3_x_b(14) and ex4_sh3_y_b(14) ); +u_sh3_15: ex4_sh3(15) <= not( ex4_sh3_x_b(15) and ex4_sh3_y_b(15) ); +u_sh3_16: ex4_sh3(16) <= not( ex4_sh3_x_b(16) and ex4_sh3_y_b(16) ); +u_sh3_17: ex4_sh3(17) <= not( ex4_sh3_x_b(17) and ex4_sh3_y_b(17) ); +u_sh3_18: ex4_sh3(18) <= not( ex4_sh3_x_b(18) and ex4_sh3_y_b(18) ); +u_sh3_19: ex4_sh3(19) <= not( ex4_sh3_x_b(19) and ex4_sh3_y_b(19) ); +u_sh3_20: ex4_sh3(20) <= not( ex4_sh3_x_b(20) and ex4_sh3_y_b(20) ); +u_sh3_21: ex4_sh3(21) <= not( ex4_sh3_x_b(21) and ex4_sh3_y_b(21) ); +u_sh3_22: ex4_sh3(22) <= not( ex4_sh3_x_b(22) and ex4_sh3_y_b(22) ); +u_sh3_23: ex4_sh3(23) <= not( ex4_sh3_x_b(23) and ex4_sh3_y_b(23) ); +u_sh3_24: ex4_sh3(24) <= not( ex4_sh3_x_b(24) and ex4_sh3_y_b(24) ); +u_sh3_25: ex4_sh3(25) <= not( ex4_sh3_x_b(25) and ex4_sh3_y_b(25) ); +u_sh3_26: ex4_sh3(26) <= not( ex4_sh3_x_b(26) and ex4_sh3_y_b(26) ); +u_sh3_27: ex4_sh3(27) <= not( ex4_sh3_x_b(27) and ex4_sh3_y_b(27) ); +u_sh3_28: ex4_sh3(28) <= not( ex4_sh3_x_b(28) and ex4_sh3_y_b(28) ); +u_sh3_29: ex4_sh3(29) <= not( ex4_sh3_x_b(29) and ex4_sh3_y_b(29) ); +u_sh3_30: ex4_sh3(30) <= not( ex4_sh3_x_b(30) and ex4_sh3_y_b(30) ); +u_sh3_31: ex4_sh3(31) <= not( ex4_sh3_x_b(31) and ex4_sh3_y_b(31) ); +u_sh3_32: ex4_sh3(32) <= not( ex4_sh3_x_b(32) and ex4_sh3_y_b(32) ); +u_sh3_33: ex4_sh3(33) <= not( ex4_sh3_x_b(33) and ex4_sh3_y_b(33) ); +u_sh3_34: ex4_sh3(34) <= not( ex4_sh3_x_b(34) and ex4_sh3_y_b(34) ); +u_sh3_35: ex4_sh3(35) <= not( ex4_sh3_x_b(35) and ex4_sh3_y_b(35) ); +u_sh3_36: ex4_sh3(36) <= not( ex4_sh3_x_b(36) and ex4_sh3_y_b(36) ); +u_sh3_37: ex4_sh3(37) <= not( ex4_sh3_x_b(37) and ex4_sh3_y_b(37) ); +u_sh3_38: ex4_sh3(38) <= not( ex4_sh3_x_b(38) and ex4_sh3_y_b(38) ); +u_sh3_39: ex4_sh3(39) <= not( ex4_sh3_x_b(39) and ex4_sh3_y_b(39) ); +u_sh3_40: ex4_sh3(40) <= not( ex4_sh3_x_b(40) and ex4_sh3_y_b(40) ); +u_sh3_41: ex4_sh3(41) <= not( ex4_sh3_x_b(41) and ex4_sh3_y_b(41) ); +u_sh3_42: ex4_sh3(42) <= not( ex4_sh3_x_b(42) and ex4_sh3_y_b(42) ); +u_sh3_43: ex4_sh3(43) <= not( ex4_sh3_x_b(43) and ex4_sh3_y_b(43) ); +u_sh3_44: ex4_sh3(44) <= not( ex4_sh3_x_b(44) and ex4_sh3_y_b(44) ); +u_sh3_45: ex4_sh3(45) <= not( ex4_sh3_x_b(45) and ex4_sh3_y_b(45) ); +u_sh3_46: ex4_sh3(46) <= not( ex4_sh3_x_b(46) and ex4_sh3_y_b(46) ); +u_sh3_47: ex4_sh3(47) <= not( ex4_sh3_x_b(47) and ex4_sh3_y_b(47) ); +u_sh3_48: ex4_sh3(48) <= not( ex4_sh3_x_b(48) and ex4_sh3_y_b(48) ); +u_sh3_49: ex4_sh3(49) <= not( ex4_sh3_x_b(49) and ex4_sh3_y_b(49) ); +u_sh3_50: ex4_sh3(50) <= not( ex4_sh3_x_b(50) and ex4_sh3_y_b(50) ); +u_sh3_51: ex4_sh3(51) <= not( ex4_sh3_x_b(51) and ex4_sh3_y_b(51) ); +u_sh3_52: ex4_sh3(52) <= not( ex4_sh3_x_b(52) and ex4_sh3_y_b(52) ); +u_sh3_53: ex4_sh3(53) <= not( ex4_sh3_x_b(53) and ex4_sh3_y_b(53) ); +u_sh3_54: ex4_sh3(54) <= not( ex4_sh3_x_b(54) and ex4_sh3_y_b(54) ); +u_sh3_55: ex4_sh3(55) <= not( ex4_sh3_x_b(55) and ex4_sh3_y_b(55) ); +u_sh3_56: ex4_sh3(56) <= not( ex4_sh3_x_b(56) and ex4_sh3_y_b(56) ); +u_sh3_57: ex4_sh3(57) <= not( ex4_sh3_x_b(57) and ex4_sh3_y_b(57) ); + + +u_sh4x_00cp1: ex4_sh4_x_00_b <= not( (ex4_sh3( 0) and ex4_shctl_01(0) ) or ( ex4_sh3( 1) and ex4_shctl_01(1) ) ); +u_sh4x_00: ex4_sh4_x_b( 0) <= not( (ex4_sh3( 0) and ex4_shctl_01(0) ) or ( ex4_sh3( 1) and ex4_shctl_01(1) ) ); +u_sh4x_01: ex4_sh4_x_b( 1) <= not( (ex4_sh3( 1) and ex4_shctl_01(0) ) or ( ex4_sh3( 2) and ex4_shctl_01(1) ) ); +u_sh4x_02: ex4_sh4_x_b( 2) <= not( (ex4_sh3( 2) and ex4_shctl_01(0) ) or ( ex4_sh3( 3) and ex4_shctl_01(1) ) ); +u_sh4x_03: ex4_sh4_x_b( 3) <= not( (ex4_sh3( 3) and ex4_shctl_01(0) ) or ( ex4_sh3( 4) and ex4_shctl_01(1) ) ); +u_sh4x_04: ex4_sh4_x_b( 4) <= not( (ex4_sh3( 4) and ex4_shctl_01(0) ) or ( ex4_sh3( 5) and ex4_shctl_01(1) ) ); +u_sh4x_05: ex4_sh4_x_b( 5) <= not( (ex4_sh3( 5) and ex4_shctl_01(0) ) or ( ex4_sh3( 6) and ex4_shctl_01(1) ) ); +u_sh4x_06: ex4_sh4_x_b( 6) <= not( (ex4_sh3( 6) and ex4_shctl_01(0) ) or ( ex4_sh3( 7) and ex4_shctl_01(1) ) ); +u_sh4x_07: ex4_sh4_x_b( 7) <= not( (ex4_sh3( 7) and ex4_shctl_01(0) ) or ( ex4_sh3( 8) and ex4_shctl_01(1) ) ); +u_sh4x_08: ex4_sh4_x_b( 8) <= not( (ex4_sh3( 8) and ex4_shctl_01(0) ) or ( ex4_sh3( 9) and ex4_shctl_01(1) ) ); +u_sh4x_09: ex4_sh4_x_b( 9) <= not( (ex4_sh3( 9) and ex4_shctl_01(0) ) or ( ex4_sh3(10) and ex4_shctl_01(1) ) ); +u_sh4x_10: ex4_sh4_x_b(10) <= not( (ex4_sh3(10) and ex4_shctl_01(0) ) or ( ex4_sh3(11) and ex4_shctl_01(1) ) ); +u_sh4x_11: ex4_sh4_x_b(11) <= not( (ex4_sh3(11) and ex4_shctl_01(0) ) or ( ex4_sh3(12) and ex4_shctl_01(1) ) ); +u_sh4x_12: ex4_sh4_x_b(12) <= not( (ex4_sh3(12) and ex4_shctl_01(0) ) or ( ex4_sh3(13) and ex4_shctl_01(1) ) ); +u_sh4x_13: ex4_sh4_x_b(13) <= not( (ex4_sh3(13) and ex4_shctl_01(0) ) or ( ex4_sh3(14) and ex4_shctl_01(1) ) ); +u_sh4x_14: ex4_sh4_x_b(14) <= not( (ex4_sh3(14) and ex4_shctl_01(0) ) or ( ex4_sh3(15) and ex4_shctl_01(1) ) ); +u_sh4x_15: ex4_sh4_x_b(15) <= not( (ex4_sh3(15) and ex4_shctl_01(0) ) or ( ex4_sh3(16) and ex4_shctl_01(1) ) ); +u_sh4x_16: ex4_sh4_x_b(16) <= not( (ex4_sh3(16) and ex4_shctl_01(0) ) or ( ex4_sh3(17) and ex4_shctl_01(1) ) ); +u_sh4x_17: ex4_sh4_x_b(17) <= not( (ex4_sh3(17) and ex4_shctl_01(0) ) or ( ex4_sh3(18) and ex4_shctl_01(1) ) ); +u_sh4x_18: ex4_sh4_x_b(18) <= not( (ex4_sh3(18) and ex4_shctl_01(0) ) or ( ex4_sh3(19) and ex4_shctl_01(1) ) ); +u_sh4x_19: ex4_sh4_x_b(19) <= not( (ex4_sh3(19) and ex4_shctl_01(0) ) or ( ex4_sh3(20) and ex4_shctl_01(1) ) ); +u_sh4x_20: ex4_sh4_x_b(20) <= not( (ex4_sh3(20) and ex4_shctl_01(0) ) or ( ex4_sh3(21) and ex4_shctl_01(1) ) ); +u_sh4x_21: ex4_sh4_x_b(21) <= not( (ex4_sh3(21) and ex4_shctl_01(0) ) or ( ex4_sh3(22) and ex4_shctl_01(1) ) ); +u_sh4x_22: ex4_sh4_x_b(22) <= not( (ex4_sh3(22) and ex4_shctl_01(0) ) or ( ex4_sh3(23) and ex4_shctl_01(1) ) ); +u_sh4x_23: ex4_sh4_x_b(23) <= not( (ex4_sh3(23) and ex4_shctl_01(0) ) or ( ex4_sh3(24) and ex4_shctl_01(1) ) ); +u_sh4x_24: ex4_sh4_x_b(24) <= not( (ex4_sh3(24) and ex4_shctl_01(0) ) or ( ex4_sh3(25) and ex4_shctl_01(1) ) ); +u_sh4x_25: ex4_sh4_x_b(25) <= not( (ex4_sh3(25) and ex4_shctl_01(0) ) or ( ex4_sh3(26) and ex4_shctl_01(1) ) ); +u_sh4x_26: ex4_sh4_x_b(26) <= not( (ex4_sh3(26) and ex4_shctl_01(0) ) or ( ex4_sh3(27) and ex4_shctl_01(1) ) ); +u_sh4x_27: ex4_sh4_x_b(27) <= not( (ex4_sh3(27) and ex4_shctl_01(0) ) or ( ex4_sh3(28) and ex4_shctl_01(1) ) ); +u_sh4x_28: ex4_sh4_x_b(28) <= not( (ex4_sh3(28) and ex4_shctl_01(0) ) or ( ex4_sh3(29) and ex4_shctl_01(1) ) ); +u_sh4x_29: ex4_sh4_x_b(29) <= not( (ex4_sh3(29) and ex4_shctl_01(0) ) or ( ex4_sh3(30) and ex4_shctl_01(1) ) ); +u_sh4x_30: ex4_sh4_x_b(30) <= not( (ex4_sh3(30) and ex4_shctl_01(0) ) or ( ex4_sh3(31) and ex4_shctl_01(1) ) ); +u_sh4x_31: ex4_sh4_x_b(31) <= not( (ex4_sh3(31) and ex4_shctl_01(0) ) or ( ex4_sh3(32) and ex4_shctl_01(1) ) ); +u_sh4x_32: ex4_sh4_x_b(32) <= not( (ex4_sh3(32) and ex4_shctl_01(0) ) or ( ex4_sh3(33) and ex4_shctl_01(1) ) ); +u_sh4x_33: ex4_sh4_x_b(33) <= not( (ex4_sh3(33) and ex4_shctl_01(0) ) or ( ex4_sh3(34) and ex4_shctl_01(1) ) ); +u_sh4x_34: ex4_sh4_x_b(34) <= not( (ex4_sh3(34) and ex4_shctl_01(0) ) or ( ex4_sh3(35) and ex4_shctl_01(1) ) ); +u_sh4x_35: ex4_sh4_x_b(35) <= not( (ex4_sh3(35) and ex4_shctl_01(0) ) or ( ex4_sh3(36) and ex4_shctl_01(1) ) ); +u_sh4x_36: ex4_sh4_x_b(36) <= not( (ex4_sh3(36) and ex4_shctl_01(0) ) or ( ex4_sh3(37) and ex4_shctl_01(1) ) ); +u_sh4x_37: ex4_sh4_x_b(37) <= not( (ex4_sh3(37) and ex4_shctl_01(0) ) or ( ex4_sh3(38) and ex4_shctl_01(1) ) ); +u_sh4x_38: ex4_sh4_x_b(38) <= not( (ex4_sh3(38) and ex4_shctl_01(0) ) or ( ex4_sh3(39) and ex4_shctl_01(1) ) ); +u_sh4x_39: ex4_sh4_x_b(39) <= not( (ex4_sh3(39) and ex4_shctl_01(0) ) or ( ex4_sh3(40) and ex4_shctl_01(1) ) ); +u_sh4x_40: ex4_sh4_x_b(40) <= not( (ex4_sh3(40) and ex4_shctl_01(0) ) or ( ex4_sh3(41) and ex4_shctl_01(1) ) ); +u_sh4x_41: ex4_sh4_x_b(41) <= not( (ex4_sh3(41) and ex4_shctl_01(0) ) or ( ex4_sh3(42) and ex4_shctl_01(1) ) ); +u_sh4x_42: ex4_sh4_x_b(42) <= not( (ex4_sh3(42) and ex4_shctl_01(0) ) or ( ex4_sh3(43) and ex4_shctl_01(1) ) ); +u_sh4x_43: ex4_sh4_x_b(43) <= not( (ex4_sh3(43) and ex4_shctl_01(0) ) or ( ex4_sh3(44) and ex4_shctl_01(1) ) ); +u_sh4x_44: ex4_sh4_x_b(44) <= not( (ex4_sh3(44) and ex4_shctl_01(0) ) or ( ex4_sh3(45) and ex4_shctl_01(1) ) ); +u_sh4x_45: ex4_sh4_x_b(45) <= not( (ex4_sh3(45) and ex4_shctl_01(0) ) or ( ex4_sh3(46) and ex4_shctl_01(1) ) ); +u_sh4x_46: ex4_sh4_x_b(46) <= not( (ex4_sh3(46) and ex4_shctl_01(0) ) or ( ex4_sh3(47) and ex4_shctl_01(1) ) ); +u_sh4x_47: ex4_sh4_x_b(47) <= not( (ex4_sh3(47) and ex4_shctl_01(0) ) or ( ex4_sh3(48) and ex4_shctl_01(1) ) ); +u_sh4x_48: ex4_sh4_x_b(48) <= not( (ex4_sh3(48) and ex4_shctl_01(0) ) or ( ex4_sh3(49) and ex4_shctl_01(1) ) ); +u_sh4x_49: ex4_sh4_x_b(49) <= not( (ex4_sh3(49) and ex4_shctl_01(0) ) or ( ex4_sh3(50) and ex4_shctl_01(1) ) ); +u_sh4x_50: ex4_sh4_x_b(50) <= not( (ex4_sh3(50) and ex4_shctl_01(0) ) or ( ex4_sh3(51) and ex4_shctl_01(1) ) ); +u_sh4x_51: ex4_sh4_x_b(51) <= not( (ex4_sh3(51) and ex4_shctl_01(0) ) or ( ex4_sh3(52) and ex4_shctl_01(1) ) ); +u_sh4x_52: ex4_sh4_x_b(52) <= not( (ex4_sh3(52) and ex4_shctl_01(0) ) or ( ex4_sh3(53) and ex4_shctl_01(1) ) ); +u_sh4x_53: ex4_sh4_x_b(53) <= not( (ex4_sh3(53) and ex4_shctl_01(0) ) or ( ex4_sh3(54) and ex4_shctl_01(1) ) ); +u_sh4x_54: ex4_sh4_x_b(54) <= not( (ex4_sh3(54) and ex4_shctl_01(0) ) or ( ex4_sh3(55) and ex4_shctl_01(1) ) ); + +u_sh4y_00cp1: ex4_sh4_y_00_b <= not( (ex4_sh3( 2) and ex4_shctl_01(2) ) or ( ex4_sh3( 3) and ex4_shctl_01(3) ) ); +u_sh4y_00: ex4_sh4_y_b( 0) <= not( (ex4_sh3( 2) and ex4_shctl_01(2) ) or ( ex4_sh3( 3) and ex4_shctl_01(3) ) ); +u_sh4y_01: ex4_sh4_y_b( 1) <= not( (ex4_sh3( 3) and ex4_shctl_01(2) ) or ( ex4_sh3( 4) and ex4_shctl_01(3) ) ); +u_sh4y_02: ex4_sh4_y_b( 2) <= not( (ex4_sh3( 4) and ex4_shctl_01(2) ) or ( ex4_sh3( 5) and ex4_shctl_01(3) ) ); +u_sh4y_03: ex4_sh4_y_b( 3) <= not( (ex4_sh3( 5) and ex4_shctl_01(2) ) or ( ex4_sh3( 6) and ex4_shctl_01(3) ) ); +u_sh4y_04: ex4_sh4_y_b( 4) <= not( (ex4_sh3( 6) and ex4_shctl_01(2) ) or ( ex4_sh3( 7) and ex4_shctl_01(3) ) ); +u_sh4y_05: ex4_sh4_y_b( 5) <= not( (ex4_sh3( 7) and ex4_shctl_01(2) ) or ( ex4_sh3( 8) and ex4_shctl_01(3) ) ); +u_sh4y_06: ex4_sh4_y_b( 6) <= not( (ex4_sh3( 8) and ex4_shctl_01(2) ) or ( ex4_sh3( 9) and ex4_shctl_01(3) ) ); +u_sh4y_07: ex4_sh4_y_b( 7) <= not( (ex4_sh3( 9) and ex4_shctl_01(2) ) or ( ex4_sh3(10) and ex4_shctl_01(3) ) ); +u_sh4y_08: ex4_sh4_y_b( 8) <= not( (ex4_sh3(10) and ex4_shctl_01(2) ) or ( ex4_sh3(11) and ex4_shctl_01(3) ) ); +u_sh4y_09: ex4_sh4_y_b( 9) <= not( (ex4_sh3(11) and ex4_shctl_01(2) ) or ( ex4_sh3(12) and ex4_shctl_01(3) ) ); +u_sh4y_10: ex4_sh4_y_b(10) <= not( (ex4_sh3(12) and ex4_shctl_01(2) ) or ( ex4_sh3(13) and ex4_shctl_01(3) ) ); +u_sh4y_11: ex4_sh4_y_b(11) <= not( (ex4_sh3(13) and ex4_shctl_01(2) ) or ( ex4_sh3(14) and ex4_shctl_01(3) ) ); +u_sh4y_12: ex4_sh4_y_b(12) <= not( (ex4_sh3(14) and ex4_shctl_01(2) ) or ( ex4_sh3(15) and ex4_shctl_01(3) ) ); +u_sh4y_13: ex4_sh4_y_b(13) <= not( (ex4_sh3(15) and ex4_shctl_01(2) ) or ( ex4_sh3(16) and ex4_shctl_01(3) ) ); +u_sh4y_14: ex4_sh4_y_b(14) <= not( (ex4_sh3(16) and ex4_shctl_01(2) ) or ( ex4_sh3(17) and ex4_shctl_01(3) ) ); +u_sh4y_15: ex4_sh4_y_b(15) <= not( (ex4_sh3(17) and ex4_shctl_01(2) ) or ( ex4_sh3(18) and ex4_shctl_01(3) ) ); +u_sh4y_16: ex4_sh4_y_b(16) <= not( (ex4_sh3(18) and ex4_shctl_01(2) ) or ( ex4_sh3(19) and ex4_shctl_01(3) ) ); +u_sh4y_17: ex4_sh4_y_b(17) <= not( (ex4_sh3(19) and ex4_shctl_01(2) ) or ( ex4_sh3(20) and ex4_shctl_01(3) ) ); +u_sh4y_18: ex4_sh4_y_b(18) <= not( (ex4_sh3(20) and ex4_shctl_01(2) ) or ( ex4_sh3(21) and ex4_shctl_01(3) ) ); +u_sh4y_19: ex4_sh4_y_b(19) <= not( (ex4_sh3(21) and ex4_shctl_01(2) ) or ( ex4_sh3(22) and ex4_shctl_01(3) ) ); +u_sh4y_20: ex4_sh4_y_b(20) <= not( (ex4_sh3(22) and ex4_shctl_01(2) ) or ( ex4_sh3(23) and ex4_shctl_01(3) ) ); +u_sh4y_21: ex4_sh4_y_b(21) <= not( (ex4_sh3(23) and ex4_shctl_01(2) ) or ( ex4_sh3(24) and ex4_shctl_01(3) ) ); +u_sh4y_22: ex4_sh4_y_b(22) <= not( (ex4_sh3(24) and ex4_shctl_01(2) ) or ( ex4_sh3(25) and ex4_shctl_01(3) ) ); +u_sh4y_23: ex4_sh4_y_b(23) <= not( (ex4_sh3(25) and ex4_shctl_01(2) ) or ( ex4_sh3(26) and ex4_shctl_01(3) ) ); +u_sh4y_24: ex4_sh4_y_b(24) <= not( (ex4_sh3(26) and ex4_shctl_01(2) ) or ( ex4_sh3(27) and ex4_shctl_01(3) ) ); +u_sh4y_25: ex4_sh4_y_b(25) <= not( (ex4_sh3(27) and ex4_shctl_01(2) ) or ( ex4_sh3(28) and ex4_shctl_01(3) ) ); +u_sh4y_26: ex4_sh4_y_b(26) <= not( (ex4_sh3(28) and ex4_shctl_01(2) ) or ( ex4_sh3(29) and ex4_shctl_01(3) ) ); +u_sh4y_27: ex4_sh4_y_b(27) <= not( (ex4_sh3(29) and ex4_shctl_01(2) ) or ( ex4_sh3(30) and ex4_shctl_01(3) ) ); +u_sh4y_28: ex4_sh4_y_b(28) <= not( (ex4_sh3(30) and ex4_shctl_01(2) ) or ( ex4_sh3(31) and ex4_shctl_01(3) ) ); +u_sh4y_29: ex4_sh4_y_b(29) <= not( (ex4_sh3(31) and ex4_shctl_01(2) ) or ( ex4_sh3(32) and ex4_shctl_01(3) ) ); +u_sh4y_30: ex4_sh4_y_b(30) <= not( (ex4_sh3(32) and ex4_shctl_01(2) ) or ( ex4_sh3(33) and ex4_shctl_01(3) ) ); +u_sh4y_31: ex4_sh4_y_b(31) <= not( (ex4_sh3(33) and ex4_shctl_01(2) ) or ( ex4_sh3(34) and ex4_shctl_01(3) ) ); +u_sh4y_32: ex4_sh4_y_b(32) <= not( (ex4_sh3(34) and ex4_shctl_01(2) ) or ( ex4_sh3(35) and ex4_shctl_01(3) ) ); +u_sh4y_33: ex4_sh4_y_b(33) <= not( (ex4_sh3(35) and ex4_shctl_01(2) ) or ( ex4_sh3(36) and ex4_shctl_01(3) ) ); +u_sh4y_34: ex4_sh4_y_b(34) <= not( (ex4_sh3(36) and ex4_shctl_01(2) ) or ( ex4_sh3(37) and ex4_shctl_01(3) ) ); +u_sh4y_35: ex4_sh4_y_b(35) <= not( (ex4_sh3(37) and ex4_shctl_01(2) ) or ( ex4_sh3(38) and ex4_shctl_01(3) ) ); +u_sh4y_36: ex4_sh4_y_b(36) <= not( (ex4_sh3(38) and ex4_shctl_01(2) ) or ( ex4_sh3(39) and ex4_shctl_01(3) ) ); +u_sh4y_37: ex4_sh4_y_b(37) <= not( (ex4_sh3(39) and ex4_shctl_01(2) ) or ( ex4_sh3(40) and ex4_shctl_01(3) ) ); +u_sh4y_38: ex4_sh4_y_b(38) <= not( (ex4_sh3(40) and ex4_shctl_01(2) ) or ( ex4_sh3(41) and ex4_shctl_01(3) ) ); +u_sh4y_39: ex4_sh4_y_b(39) <= not( (ex4_sh3(41) and ex4_shctl_01(2) ) or ( ex4_sh3(42) and ex4_shctl_01(3) ) ); +u_sh4y_40: ex4_sh4_y_b(40) <= not( (ex4_sh3(42) and ex4_shctl_01(2) ) or ( ex4_sh3(43) and ex4_shctl_01(3) ) ); +u_sh4y_41: ex4_sh4_y_b(41) <= not( (ex4_sh3(43) and ex4_shctl_01(2) ) or ( ex4_sh3(44) and ex4_shctl_01(3) ) ); +u_sh4y_42: ex4_sh4_y_b(42) <= not( (ex4_sh3(44) and ex4_shctl_01(2) ) or ( ex4_sh3(45) and ex4_shctl_01(3) ) ); +u_sh4y_43: ex4_sh4_y_b(43) <= not( (ex4_sh3(45) and ex4_shctl_01(2) ) or ( ex4_sh3(46) and ex4_shctl_01(3) ) ); +u_sh4y_44: ex4_sh4_y_b(44) <= not( (ex4_sh3(46) and ex4_shctl_01(2) ) or ( ex4_sh3(47) and ex4_shctl_01(3) ) ); +u_sh4y_45: ex4_sh4_y_b(45) <= not( (ex4_sh3(47) and ex4_shctl_01(2) ) or ( ex4_sh3(48) and ex4_shctl_01(3) ) ); +u_sh4y_46: ex4_sh4_y_b(46) <= not( (ex4_sh3(48) and ex4_shctl_01(2) ) or ( ex4_sh3(49) and ex4_shctl_01(3) ) ); +u_sh4y_47: ex4_sh4_y_b(47) <= not( (ex4_sh3(49) and ex4_shctl_01(2) ) or ( ex4_sh3(50) and ex4_shctl_01(3) ) ); +u_sh4y_48: ex4_sh4_y_b(48) <= not( (ex4_sh3(50) and ex4_shctl_01(2) ) or ( ex4_sh3(51) and ex4_shctl_01(3) ) ); +u_sh4y_49: ex4_sh4_y_b(49) <= not( (ex4_sh3(51) and ex4_shctl_01(2) ) or ( ex4_sh3(52) and ex4_shctl_01(3) ) ); +u_sh4y_50: ex4_sh4_y_b(50) <= not( (ex4_sh3(52) and ex4_shctl_01(2) ) or ( ex4_sh3(53) and ex4_shctl_01(3) ) ); +u_sh4y_51: ex4_sh4_y_b(51) <= not( (ex4_sh3(53) and ex4_shctl_01(2) ) or ( ex4_sh3(54) and ex4_shctl_01(3) ) ); +u_sh4y_52: ex4_sh4_y_b(52) <= not( (ex4_sh3(54) and ex4_shctl_01(2) ) or ( ex4_sh3(55) and ex4_shctl_01(3) ) ); +u_sh4y_53: ex4_sh4_y_b(53) <= not( (ex4_sh3(55) and ex4_shctl_01(2) ) or ( ex4_sh3(56) and ex4_shctl_01(3) ) ); +u_sh4y_54: ex4_sh4_y_b(54) <= not( (ex4_sh3(56) and ex4_shctl_01(2) ) or ( ex4_sh3(57) and ex4_shctl_01(3) ) ); + +u_extra_cp1: ex4_shift_extra_cp1_b <= not(ex4_sh4_x_00_b and ex4_sh4_y_00_b ); +u_extra_cp2: ex4_shift_extra_cp2_b <= not(ex4_sh4_x_00_b and ex4_sh4_y_00_b ); +u_extra_cp3: ex4_shift_extra_00_cp3_b <= not(ex4_sh4_x_b(0) and ex4_sh4_y_b(0) ); +u_extra_cp4: ex4_shift_extra_00_cp4_b <= not(ex4_sh4_x_b(0) and ex4_sh4_y_b(0) ); + + ex4_shift_extra_cp1 <= not ex4_shift_extra_cp1_b ; + ex4_shift_extra_cp2 <= not ex4_shift_extra_cp2_b ; + + +u_extra_10_cp3: ex4_shift_extra_10_cp3 <= not ex4_shift_extra_00_cp3_b ; +u_extra_20_cp3: ex4_shift_extra_20_cp3_b <= not ex4_shift_extra_10_cp3 ; +u_extra_30_cp3: ex4_shift_extra_cp3 <= not ex4_shift_extra_20_cp3_b ; + +u_extra_11_cp3: ex4_shift_extra_11_cp3 <= not ex4_shift_extra_00_cp3_b ; +u_extra_21_cp3: ex4_shift_extra_21_cp3_b <= not ex4_shift_extra_11_cp3 ; +u_extra_31_cp3: ex4_shift_extra_31_cp3 <= not ex4_shift_extra_21_cp3_b ; +u_extra_41_cp3: ex4_shift_extra_cp3_b <= not ex4_shift_extra_31_cp3 ; + +u_extra_10_cp4: ex4_shift_extra_10_cp4 <= not ex4_shift_extra_00_cp4_b ; +u_extra_20_cp4: ex4_shift_extra_20_cp4_b <= not ex4_shift_extra_10_cp4 ; +u_extra_30_cp4: ex4_shift_extra_cp4 <= not ex4_shift_extra_20_cp4_b ; + +u_extra_11_cp4: ex4_shift_extra_11_cp4 <= not ex4_shift_extra_00_cp4_b ; +u_extra_21_cp4: ex4_shift_extra_21_cp4_b <= not ex4_shift_extra_11_cp4 ; +u_extra_31_cp4: ex4_shift_extra_31_cp4 <= not ex4_shift_extra_21_cp4_b ; +u_extra_41_cp4: ex4_shift_extra_cp4_b <= not ex4_shift_extra_31_cp4 ; + + + + + + +u_sh4_00: ex4_sh4( 0) <= not( ex4_sh4_x_b( 0) and ex4_sh4_y_b( 0) ); +u_sh4_01: ex4_sh4( 1) <= not( ex4_sh4_x_b( 1) and ex4_sh4_y_b( 1) ); +u_sh4_02: ex4_sh4( 2) <= not( ex4_sh4_x_b( 2) and ex4_sh4_y_b( 2) ); +u_sh4_03: ex4_sh4( 3) <= not( ex4_sh4_x_b( 3) and ex4_sh4_y_b( 3) ); +u_sh4_04: ex4_sh4( 4) <= not( ex4_sh4_x_b( 4) and ex4_sh4_y_b( 4) ); +u_sh4_05: ex4_sh4( 5) <= not( ex4_sh4_x_b( 5) and ex4_sh4_y_b( 5) ); +u_sh4_06: ex4_sh4( 6) <= not( ex4_sh4_x_b( 6) and ex4_sh4_y_b( 6) ); +u_sh4_07: ex4_sh4( 7) <= not( ex4_sh4_x_b( 7) and ex4_sh4_y_b( 7) ); +u_sh4_08: ex4_sh4( 8) <= not( ex4_sh4_x_b( 8) and ex4_sh4_y_b( 8) ); +u_sh4_09: ex4_sh4( 9) <= not( ex4_sh4_x_b( 9) and ex4_sh4_y_b( 9) ); +u_sh4_10: ex4_sh4(10) <= not( ex4_sh4_x_b(10) and ex4_sh4_y_b(10) ); +u_sh4_11: ex4_sh4(11) <= not( ex4_sh4_x_b(11) and ex4_sh4_y_b(11) ); +u_sh4_12: ex4_sh4(12) <= not( ex4_sh4_x_b(12) and ex4_sh4_y_b(12) ); +u_sh4_13: ex4_sh4(13) <= not( ex4_sh4_x_b(13) and ex4_sh4_y_b(13) ); +u_sh4_14: ex4_sh4(14) <= not( ex4_sh4_x_b(14) and ex4_sh4_y_b(14) ); +u_sh4_15: ex4_sh4(15) <= not( ex4_sh4_x_b(15) and ex4_sh4_y_b(15) ); +u_sh4_16: ex4_sh4(16) <= not( ex4_sh4_x_b(16) and ex4_sh4_y_b(16) ); +u_sh4_17: ex4_sh4(17) <= not( ex4_sh4_x_b(17) and ex4_sh4_y_b(17) ); +u_sh4_18: ex4_sh4(18) <= not( ex4_sh4_x_b(18) and ex4_sh4_y_b(18) ); +u_sh4_19: ex4_sh4(19) <= not( ex4_sh4_x_b(19) and ex4_sh4_y_b(19) ); +u_sh4_20: ex4_sh4(20) <= not( ex4_sh4_x_b(20) and ex4_sh4_y_b(20) ); +u_sh4_21: ex4_sh4(21) <= not( ex4_sh4_x_b(21) and ex4_sh4_y_b(21) ); +u_sh4_22: ex4_sh4(22) <= not( ex4_sh4_x_b(22) and ex4_sh4_y_b(22) ); +u_sh4_23: ex4_sh4(23) <= not( ex4_sh4_x_b(23) and ex4_sh4_y_b(23) ); +u_sh4_24: ex4_sh4(24) <= not( ex4_sh4_x_b(24) and ex4_sh4_y_b(24) ); +u_sh4_25: ex4_sh4(25) <= not( ex4_sh4_x_b(25) and ex4_sh4_y_b(25) ); +u_sh4_26: ex4_sh4(26) <= not( ex4_sh4_x_b(26) and ex4_sh4_y_b(26) ); +u_sh4_27: ex4_sh4(27) <= not( ex4_sh4_x_b(27) and ex4_sh4_y_b(27) ); +u_sh4_28: ex4_sh4(28) <= not( ex4_sh4_x_b(28) and ex4_sh4_y_b(28) ); +u_sh4_29: ex4_sh4(29) <= not( ex4_sh4_x_b(29) and ex4_sh4_y_b(29) ); +u_sh4_30: ex4_sh4(30) <= not( ex4_sh4_x_b(30) and ex4_sh4_y_b(30) ); +u_sh4_31: ex4_sh4(31) <= not( ex4_sh4_x_b(31) and ex4_sh4_y_b(31) ); +u_sh4_32: ex4_sh4(32) <= not( ex4_sh4_x_b(32) and ex4_sh4_y_b(32) ); +u_sh4_33: ex4_sh4(33) <= not( ex4_sh4_x_b(33) and ex4_sh4_y_b(33) ); +u_sh4_34: ex4_sh4(34) <= not( ex4_sh4_x_b(34) and ex4_sh4_y_b(34) ); +u_sh4_35: ex4_sh4(35) <= not( ex4_sh4_x_b(35) and ex4_sh4_y_b(35) ); +u_sh4_36: ex4_sh4(36) <= not( ex4_sh4_x_b(36) and ex4_sh4_y_b(36) ); +u_sh4_37: ex4_sh4(37) <= not( ex4_sh4_x_b(37) and ex4_sh4_y_b(37) ); +u_sh4_38: ex4_sh4(38) <= not( ex4_sh4_x_b(38) and ex4_sh4_y_b(38) ); +u_sh4_39: ex4_sh4(39) <= not( ex4_sh4_x_b(39) and ex4_sh4_y_b(39) ); +u_sh4_40: ex4_sh4(40) <= not( ex4_sh4_x_b(40) and ex4_sh4_y_b(40) ); +u_sh4_41: ex4_sh4(41) <= not( ex4_sh4_x_b(41) and ex4_sh4_y_b(41) ); +u_sh4_42: ex4_sh4(42) <= not( ex4_sh4_x_b(42) and ex4_sh4_y_b(42) ); +u_sh4_43: ex4_sh4(43) <= not( ex4_sh4_x_b(43) and ex4_sh4_y_b(43) ); +u_sh4_44: ex4_sh4(44) <= not( ex4_sh4_x_b(44) and ex4_sh4_y_b(44) ); +u_sh4_45: ex4_sh4(45) <= not( ex4_sh4_x_b(45) and ex4_sh4_y_b(45) ); +u_sh4_46: ex4_sh4(46) <= not( ex4_sh4_x_b(46) and ex4_sh4_y_b(46) ); +u_sh4_47: ex4_sh4(47) <= not( ex4_sh4_x_b(47) and ex4_sh4_y_b(47) ); +u_sh4_48: ex4_sh4(48) <= not( ex4_sh4_x_b(48) and ex4_sh4_y_b(48) ); +u_sh4_49: ex4_sh4(49) <= not( ex4_sh4_x_b(49) and ex4_sh4_y_b(49) ); +u_sh4_50: ex4_sh4(50) <= not( ex4_sh4_x_b(50) and ex4_sh4_y_b(50) ); +u_sh4_51: ex4_sh4(51) <= not( ex4_sh4_x_b(51) and ex4_sh4_y_b(51) ); +u_sh4_52: ex4_sh4(52) <= not( ex4_sh4_x_b(52) and ex4_sh4_y_b(52) ); +u_sh4_53: ex4_sh4(53) <= not( ex4_sh4_x_b(53) and ex4_sh4_y_b(53) ); +u_sh4_54: ex4_sh4(54) <= not( ex4_sh4_x_b(54) and ex4_sh4_y_b(54) ); + + + +u_nrm_sh5x_00: ex4_sh5_x_b( 0) <= not( ex4_sh4( 0) and ex4_shift_extra_cp3_b ); +u_nrm_sh5x_01: ex4_sh5_x_b( 1) <= not( ex4_sh4( 1) and ex4_shift_extra_cp3_b ); +u_nrm_sh5x_02: ex4_sh5_x_b( 2) <= not( ex4_sh4( 2) and ex4_shift_extra_cp3_b ); +u_nrm_sh5x_03: ex4_sh5_x_b( 3) <= not( ex4_sh4( 3) and ex4_shift_extra_cp3_b ); +u_nrm_sh5x_04: ex4_sh5_x_b( 4) <= not( ex4_sh4( 4) and ex4_shift_extra_cp3_b ); +u_nrm_sh5x_05: ex4_sh5_x_b( 5) <= not( ex4_sh4( 5) and ex4_shift_extra_cp3_b ); +u_nrm_sh5x_06: ex4_sh5_x_b( 6) <= not( ex4_sh4( 6) and ex4_shift_extra_cp3_b ); +u_nrm_sh5x_07: ex4_sh5_x_b( 7) <= not( ex4_sh4( 7) and ex4_shift_extra_cp3_b ); +u_nrm_sh5x_08: ex4_sh5_x_b( 8) <= not( ex4_sh4( 8) and ex4_shift_extra_cp3_b ); +u_nrm_sh5x_09: ex4_sh5_x_b( 9) <= not( ex4_sh4( 9) and ex4_shift_extra_cp3_b ); +u_nrm_sh5x_10: ex4_sh5_x_b(10) <= not( ex4_sh4(10) and ex4_shift_extra_cp3_b ); +u_nrm_sh5x_11: ex4_sh5_x_b(11) <= not( ex4_sh4(11) and ex4_shift_extra_cp3_b ); +u_nrm_sh5x_12: ex4_sh5_x_b(12) <= not( ex4_sh4(12) and ex4_shift_extra_cp3_b ); +u_nrm_sh5x_13: ex4_sh5_x_b(13) <= not( ex4_sh4(13) and ex4_shift_extra_cp3_b ); +u_nrm_sh5x_14: ex4_sh5_x_b(14) <= not( ex4_sh4(14) and ex4_shift_extra_cp3_b ); +u_nrm_sh5x_15: ex4_sh5_x_b(15) <= not( ex4_sh4(15) and ex4_shift_extra_cp3_b ); +u_nrm_sh5x_16: ex4_sh5_x_b(16) <= not( ex4_sh4(16) and ex4_shift_extra_cp3_b ); +u_nrm_sh5x_17: ex4_sh5_x_b(17) <= not( ex4_sh4(17) and ex4_shift_extra_cp3_b ); +u_nrm_sh5x_18: ex4_sh5_x_b(18) <= not( ex4_sh4(18) and ex4_shift_extra_cp3_b ); +u_nrm_sh5x_19: ex4_sh5_x_b(19) <= not( ex4_sh4(19) and ex4_shift_extra_cp3_b ); +u_nrm_sh5x_20: ex4_sh5_x_b(20) <= not( ex4_sh4(20) and ex4_shift_extra_cp3_b ); +u_nrm_sh5x_21: ex4_sh5_x_b(21) <= not( ex4_sh4(21) and ex4_shift_extra_cp3_b ); +u_nrm_sh5x_22: ex4_sh5_x_b(22) <= not( ex4_sh4(22) and ex4_shift_extra_cp3_b ); +u_nrm_sh5x_23: ex4_sh5_x_b(23) <= not( ex4_sh4(23) and ex4_shift_extra_cp3_b ); +u_nrm_sh5x_24: ex4_sh5_x_b(24) <= not( ex4_sh4(24) and ex4_shift_extra_cp3_b ); +u_nrm_sh5x_25: ex4_sh5_x_b(25) <= not( ex4_sh4(25) and ex4_shift_extra_cp3_b ); +u_nrm_sh5x_26: ex4_sh5_x_b(26) <= not( ex4_sh4(26) and ex4_shift_extra_cp4_b ); +u_nrm_sh5x_27: ex4_sh5_x_b(27) <= not( ex4_sh4(27) and ex4_shift_extra_cp4_b ); +u_nrm_sh5x_28: ex4_sh5_x_b(28) <= not( ex4_sh4(28) and ex4_shift_extra_cp4_b ); +u_nrm_sh5x_29: ex4_sh5_x_b(29) <= not( ex4_sh4(29) and ex4_shift_extra_cp4_b ); +u_nrm_sh5x_30: ex4_sh5_x_b(30) <= not( ex4_sh4(30) and ex4_shift_extra_cp4_b ); +u_nrm_sh5x_31: ex4_sh5_x_b(31) <= not( ex4_sh4(31) and ex4_shift_extra_cp4_b ); +u_nrm_sh5x_32: ex4_sh5_x_b(32) <= not( ex4_sh4(32) and ex4_shift_extra_cp4_b ); +u_nrm_sh5x_33: ex4_sh5_x_b(33) <= not( ex4_sh4(33) and ex4_shift_extra_cp4_b ); +u_nrm_sh5x_34: ex4_sh5_x_b(34) <= not( ex4_sh4(34) and ex4_shift_extra_cp4_b ); +u_nrm_sh5x_35: ex4_sh5_x_b(35) <= not( ex4_sh4(35) and ex4_shift_extra_cp4_b ); +u_nrm_sh5x_36: ex4_sh5_x_b(36) <= not( ex4_sh4(36) and ex4_shift_extra_cp4_b ); +u_nrm_sh5x_37: ex4_sh5_x_b(37) <= not( ex4_sh4(37) and ex4_shift_extra_cp4_b ); +u_nrm_sh5x_38: ex4_sh5_x_b(38) <= not( ex4_sh4(38) and ex4_shift_extra_cp4_b ); +u_nrm_sh5x_39: ex4_sh5_x_b(39) <= not( ex4_sh4(39) and ex4_shift_extra_cp4_b ); +u_nrm_sh5x_40: ex4_sh5_x_b(40) <= not( ex4_sh4(40) and ex4_shift_extra_cp4_b ); +u_nrm_sh5x_41: ex4_sh5_x_b(41) <= not( ex4_sh4(41) and ex4_shift_extra_cp4_b ); +u_nrm_sh5x_42: ex4_sh5_x_b(42) <= not( ex4_sh4(42) and ex4_shift_extra_cp4_b ); +u_nrm_sh5x_43: ex4_sh5_x_b(43) <= not( ex4_sh4(43) and ex4_shift_extra_cp4_b ); +u_nrm_sh5x_44: ex4_sh5_x_b(44) <= not( ex4_sh4(44) and ex4_shift_extra_cp4_b ); +u_nrm_sh5x_45: ex4_sh5_x_b(45) <= not( ex4_sh4(45) and ex4_shift_extra_cp4_b ); +u_nrm_sh5x_46: ex4_sh5_x_b(46) <= not( ex4_sh4(46) and ex4_shift_extra_cp4_b ); +u_nrm_sh5x_47: ex4_sh5_x_b(47) <= not( ex4_sh4(47) and ex4_shift_extra_cp4_b ); +u_nrm_sh5x_48: ex4_sh5_x_b(48) <= not( ex4_sh4(48) and ex4_shift_extra_cp4_b ); +u_nrm_sh5x_49: ex4_sh5_x_b(49) <= not( ex4_sh4(49) and ex4_shift_extra_cp4_b ); +u_nrm_sh5x_50: ex4_sh5_x_b(50) <= not( ex4_sh4(50) and ex4_shift_extra_cp4_b ); +u_nrm_sh5x_51: ex4_sh5_x_b(51) <= not( ex4_sh4(51) and ex4_shift_extra_cp4_b ); +u_nrm_sh5x_52: ex4_sh5_x_b(52) <= not( ex4_sh4(52) and ex4_shift_extra_cp4_b ); +u_nrm_sh5x_53: ex4_sh5_x_b(53) <= not( ex4_sh4(53) and ex4_shift_extra_cp4_b ); + + +u_nrm_sh5y_00: ex4_sh5_y_b( 0) <= not( ex4_sh4( 1) and ex4_shift_extra_cp3 ); +u_nrm_sh5y_01: ex4_sh5_y_b( 1) <= not( ex4_sh4( 2) and ex4_shift_extra_cp3 ); +u_nrm_sh5y_02: ex4_sh5_y_b( 2) <= not( ex4_sh4( 3) and ex4_shift_extra_cp3 ); +u_nrm_sh5y_03: ex4_sh5_y_b( 3) <= not( ex4_sh4( 4) and ex4_shift_extra_cp3 ); +u_nrm_sh5y_04: ex4_sh5_y_b( 4) <= not( ex4_sh4( 5) and ex4_shift_extra_cp3 ); +u_nrm_sh5y_05: ex4_sh5_y_b( 5) <= not( ex4_sh4( 6) and ex4_shift_extra_cp3 ); +u_nrm_sh5y_06: ex4_sh5_y_b( 6) <= not( ex4_sh4( 7) and ex4_shift_extra_cp3 ); +u_nrm_sh5y_07: ex4_sh5_y_b( 7) <= not( ex4_sh4( 8) and ex4_shift_extra_cp3 ); +u_nrm_sh5y_08: ex4_sh5_y_b( 8) <= not( ex4_sh4( 9) and ex4_shift_extra_cp3 ); +u_nrm_sh5y_09: ex4_sh5_y_b( 9) <= not( ex4_sh4(10) and ex4_shift_extra_cp3 ); +u_nrm_sh5y_10: ex4_sh5_y_b(10) <= not( ex4_sh4(11) and ex4_shift_extra_cp3 ); +u_nrm_sh5y_11: ex4_sh5_y_b(11) <= not( ex4_sh4(12) and ex4_shift_extra_cp3 ); +u_nrm_sh5y_12: ex4_sh5_y_b(12) <= not( ex4_sh4(13) and ex4_shift_extra_cp3 ); +u_nrm_sh5y_13: ex4_sh5_y_b(13) <= not( ex4_sh4(14) and ex4_shift_extra_cp3 ); +u_nrm_sh5y_14: ex4_sh5_y_b(14) <= not( ex4_sh4(15) and ex4_shift_extra_cp3 ); +u_nrm_sh5y_15: ex4_sh5_y_b(15) <= not( ex4_sh4(16) and ex4_shift_extra_cp3 ); +u_nrm_sh5y_16: ex4_sh5_y_b(16) <= not( ex4_sh4(17) and ex4_shift_extra_cp3 ); +u_nrm_sh5y_17: ex4_sh5_y_b(17) <= not( ex4_sh4(18) and ex4_shift_extra_cp3 ); +u_nrm_sh5y_18: ex4_sh5_y_b(18) <= not( ex4_sh4(19) and ex4_shift_extra_cp3 ); +u_nrm_sh5y_19: ex4_sh5_y_b(19) <= not( ex4_sh4(20) and ex4_shift_extra_cp3 ); +u_nrm_sh5y_20: ex4_sh5_y_b(20) <= not( ex4_sh4(21) and ex4_shift_extra_cp3 ); +u_nrm_sh5y_21: ex4_sh5_y_b(21) <= not( ex4_sh4(22) and ex4_shift_extra_cp3 ); +u_nrm_sh5y_22: ex4_sh5_y_b(22) <= not( ex4_sh4(23) and ex4_shift_extra_cp3 ); +u_nrm_sh5y_23: ex4_sh5_y_b(23) <= not( ex4_sh4(24) and ex4_shift_extra_cp3 ); +u_nrm_sh5y_24: ex4_sh5_y_b(24) <= not( ex4_sh4(25) and ex4_shift_extra_cp3 ); +u_nrm_sh5y_25: ex4_sh5_y_b(25) <= not( ex4_sh4(26) and ex4_shift_extra_cp3 ); +u_nrm_sh5y_26: ex4_sh5_y_b(26) <= not( ex4_sh4(27) and ex4_shift_extra_cp4 ); +u_nrm_sh5y_27: ex4_sh5_y_b(27) <= not( ex4_sh4(28) and ex4_shift_extra_cp4 ); +u_nrm_sh5y_28: ex4_sh5_y_b(28) <= not( ex4_sh4(29) and ex4_shift_extra_cp4 ); +u_nrm_sh5y_29: ex4_sh5_y_b(29) <= not( ex4_sh4(30) and ex4_shift_extra_cp4 ); +u_nrm_sh5y_30: ex4_sh5_y_b(30) <= not( ex4_sh4(31) and ex4_shift_extra_cp4 ); +u_nrm_sh5y_31: ex4_sh5_y_b(31) <= not( ex4_sh4(32) and ex4_shift_extra_cp4 ); +u_nrm_sh5y_32: ex4_sh5_y_b(32) <= not( ex4_sh4(33) and ex4_shift_extra_cp4 ); +u_nrm_sh5y_33: ex4_sh5_y_b(33) <= not( ex4_sh4(34) and ex4_shift_extra_cp4 ); +u_nrm_sh5y_34: ex4_sh5_y_b(34) <= not( ex4_sh4(35) and ex4_shift_extra_cp4 ); +u_nrm_sh5y_35: ex4_sh5_y_b(35) <= not( ex4_sh4(36) and ex4_shift_extra_cp4 ); +u_nrm_sh5y_36: ex4_sh5_y_b(36) <= not( ex4_sh4(37) and ex4_shift_extra_cp4 ); +u_nrm_sh5y_37: ex4_sh5_y_b(37) <= not( ex4_sh4(38) and ex4_shift_extra_cp4 ); +u_nrm_sh5y_38: ex4_sh5_y_b(38) <= not( ex4_sh4(39) and ex4_shift_extra_cp4 ); +u_nrm_sh5y_39: ex4_sh5_y_b(39) <= not( ex4_sh4(40) and ex4_shift_extra_cp4 ); +u_nrm_sh5y_40: ex4_sh5_y_b(40) <= not( ex4_sh4(41) and ex4_shift_extra_cp4 ); +u_nrm_sh5y_41: ex4_sh5_y_b(41) <= not( ex4_sh4(42) and ex4_shift_extra_cp4 ); +u_nrm_sh5y_42: ex4_sh5_y_b(42) <= not( ex4_sh4(43) and ex4_shift_extra_cp4 ); +u_nrm_sh5y_43: ex4_sh5_y_b(43) <= not( ex4_sh4(44) and ex4_shift_extra_cp4 ); +u_nrm_sh5y_44: ex4_sh5_y_b(44) <= not( ex4_sh4(45) and ex4_shift_extra_cp4 ); +u_nrm_sh5y_45: ex4_sh5_y_b(45) <= not( ex4_sh4(46) and ex4_shift_extra_cp4 ); +u_nrm_sh5y_46: ex4_sh5_y_b(46) <= not( ex4_sh4(47) and ex4_shift_extra_cp4 ); +u_nrm_sh5y_47: ex4_sh5_y_b(47) <= not( ex4_sh4(48) and ex4_shift_extra_cp4 ); +u_nrm_sh5y_48: ex4_sh5_y_b(48) <= not( ex4_sh4(49) and ex4_shift_extra_cp4 ); +u_nrm_sh5y_49: ex4_sh5_y_b(49) <= not( ex4_sh4(50) and ex4_shift_extra_cp4 ); +u_nrm_sh5y_50: ex4_sh5_y_b(50) <= not( ex4_sh4(51) and ex4_shift_extra_cp4 ); +u_nrm_sh5y_51: ex4_sh5_y_b(51) <= not( ex4_sh4(52) and ex4_shift_extra_cp4 ); +u_nrm_sh5y_52: ex4_sh5_y_b(52) <= not( ex4_sh4(53) and ex4_shift_extra_cp4 ); +u_nrm_sh5y_53: ex4_sh5_y_b(53) <= not( ex4_sh4(54) and ex4_shift_extra_cp4 ); + + + +end; + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_perv.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_perv.vhdl new file mode 100644 index 0000000..ba4490b --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_perv.vhdl @@ -0,0 +1,281 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + + +library ieee; +use ieee.std_logic_1164.all; + +library ibm; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; + +library support; +use support.power_logic_pkg.all; + +library tri; +use tri.tri_latches_pkg.all; + +entity fuq_perv is +generic(expand_type : integer := 2 ); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + pc_fu_sg_3 : in std_ulogic_vector(0 to 1); + pc_fu_abst_sl_thold_3 : in std_ulogic; + pc_fu_func_sl_thold_3 : in std_ulogic_vector(0 to 1); + pc_fu_func_slp_sl_thold_3 : in std_ulogic_vector(0 to 1); + pc_fu_gptr_sl_thold_3 : in std_ulogic; + pc_fu_time_sl_thold_3 : in std_ulogic; + pc_fu_ary_nsl_thold_3 : in std_ulogic; + pc_fu_cfg_sl_thold_3 : in std_ulogic; + pc_fu_repr_sl_thold_3 : in std_ulogic; + pc_fu_fce_3 : in std_ulogic; + tc_ac_ccflush_dc : in std_ulogic; + tc_ac_scan_diag_dc : in std_ulogic; + abst_sl_thold_1 : out std_ulogic; + func_sl_thold_1 : out std_ulogic_vector(0 to 1); + time_sl_thold_1 : out std_ulogic; + ary_nsl_thold_1 : out std_ulogic; + gptr_sl_thold_0 : out std_ulogic; + cfg_sl_thold_1 : out std_ulogic; + func_slp_sl_thold_1 : out std_ulogic; + + fce_1 : out std_ulogic; + sg_1 : out std_ulogic_vector(0 to 1); + clkoff_dc_b : out std_ulogic; + act_dis : out std_ulogic; + delay_lclkr_dc : out std_ulogic_vector(0 to 9); + mpw1_dc_b : out std_ulogic_vector(0 to 9); + mpw2_dc_b : out std_ulogic_vector(0 to 1); + repr_scan_in : in std_ulogic; + repr_scan_out : out std_ulogic; + gptr_scan_in : in std_ulogic; + gptr_scan_out : out std_ulogic +); + +-- synopsys translate_off + + +-- synopsys translate_on + +end fuq_perv; +architecture fuq_perv of fuq_perv is + + +signal abst_sl_thold_2 : std_ulogic; +signal time_sl_thold_2 : std_ulogic; +signal func_sl_thold_2 : std_ulogic_vector(0 to 1); +signal gptr_sl_thold_2 : std_ulogic; +signal ary_nsl_thold_2 : std_ulogic; +signal cfg_sl_thold_2 : std_ulogic; +signal repr_sl_thold_2 : std_ulogic; +signal func_slp_sl_thold_2 : std_ulogic; + +signal sg_2 : std_ulogic_vector(0 to 1); +signal fce_2 : std_ulogic; + +signal gptr_sl_thold_1 : std_ulogic; +signal repr_sl_thold_1 : std_ulogic; +signal sg_1_int : std_ulogic_vector(0 to 1); + +signal gptr_sl_thold_0_int : std_ulogic; +signal repr_sl_thold_0 : std_ulogic; +signal repr_sl_force : std_ulogic; +signal repr_sl_thold_0_b : std_ulogic; +signal repr_in : std_ulogic; +signal repr_UNUSED : std_ulogic; + +signal spare_unused : std_ulogic; + +signal sg_0 : std_ulogic; +signal gptr_sio : std_ulogic; +signal prv_delay_lclkr_dc : std_ulogic_vector(0 to 9); +signal prv_mpw1_dc_b : std_ulogic_vector(0 to 9); +signal prv_mpw2_dc_b : std_ulogic_vector(0 to 1); +signal prv_act_dis : std_ulogic; +signal prv_clkoff_dc_b : std_ulogic; +signal tihi : std_ulogic; + +begin + +tihi <= '1'; + +perv_3to2_reg: tri_plat + generic map (width => 12, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + + din(0 to 1) => pc_fu_func_sl_thold_3(0 to 1), + din(2) => pc_fu_gptr_sl_thold_3, + din(3) => pc_fu_abst_sl_thold_3, + din(4 to 5) => pc_fu_sg_3(0 to 1), + din(6) => pc_fu_time_sl_thold_3, + din(7) => pc_fu_fce_3, + din(8) => pc_fu_ary_nsl_thold_3, + din(9) => pc_fu_cfg_sl_thold_3, + din(10) => pc_fu_repr_sl_thold_3, + din(11) => pc_fu_func_slp_sl_thold_3(0), + + q(0 to 1) => func_sl_thold_2(0 to 1), + q(2) => gptr_sl_thold_2, + q(3) => abst_sl_thold_2, + q(4 to 5) => sg_2(0 to 1), + q(6) => time_sl_thold_2, + q(7) => fce_2, + q(8) => ary_nsl_thold_2, + q(9) => cfg_sl_thold_2, + q(10) => repr_sl_thold_2, + q(11) => func_slp_sl_thold_2 ); + + +perv_2to1_reg: tri_plat + generic map (width => 12, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + + din(0 to 1) => func_sl_thold_2(0 to 1), + din(2) => gptr_sl_thold_2, + din(3) => abst_sl_thold_2, + din(4 to 5) => sg_2(0 to 1), + din(6) => time_sl_thold_2, + din(7) => fce_2, + din(8) => ary_nsl_thold_2, + din(9) => cfg_sl_thold_2, + din(10) => repr_sl_thold_2, + din(11) => func_slp_sl_thold_2, + + q(0 to 1) => func_sl_thold_1(0 to 1), + q(2) => gptr_sl_thold_1, + q(3) => abst_sl_thold_1, + q(4 to 5) => sg_1_int(0 to 1), + q(6) => time_sl_thold_1, + q(7) => fce_1, + q(8) => ary_nsl_thold_1, + q(9) => cfg_sl_thold_1, + q(10) => repr_sl_thold_1, + q(11) => func_slp_sl_thold_1 ); + +sg_1(0 to 1) <= sg_1_int(0 to 1); + +perv_1to0_reg: tri_plat + generic map (width => 3, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => gptr_sl_thold_1, + din(1) => sg_1_int(0), + din(2) => repr_sl_thold_1, + + q(0) => gptr_sl_thold_0_int, + q(1) => sg_0, + q(2) => repr_sl_thold_0 ); + + gptr_sl_thold_0 <= gptr_sl_thold_0_int; + +perv_lcbctrl0: tri_lcbcntl_mac + generic map (expand_type => expand_type) + port map ( + vdd => vdd, + gnd => gnd, + sg => sg_0, + nclk => nclk, + scan_in => gptr_scan_in, + scan_diag_dc => tc_ac_scan_diag_dc, + thold => gptr_sl_thold_0_int, + clkoff_dc_b => prv_clkoff_dc_b, + delay_lclkr_dc => prv_delay_lclkr_dc(0 to 4), + act_dis_dc => open, + mpw1_dc_b => prv_mpw1_dc_b(0 to 4), + mpw2_dc_b => prv_mpw2_dc_b(0), + scan_out => gptr_sio); + +perv_lcbctrl1: tri_lcbcntl_mac + generic map (expand_type => expand_type) + port map ( + vdd => vdd, + gnd => gnd, + sg => sg_0, + nclk => nclk, + scan_in => gptr_sio, + scan_diag_dc => tc_ac_scan_diag_dc, + thold => gptr_sl_thold_0_int, + clkoff_dc_b => open, + delay_lclkr_dc => prv_delay_lclkr_dc(5 to 9), + act_dis_dc => open, + mpw1_dc_b => prv_mpw1_dc_b(5 to 9), + mpw2_dc_b => prv_mpw2_dc_b(1), + scan_out => gptr_scan_out); + + delay_lclkr_dc(0 to 9) <= prv_delay_lclkr_dc(0 to 9); + mpw1_dc_b(0 to 9) <= prv_mpw1_dc_b(0 to 9); + mpw2_dc_b(0 to 1) <= prv_mpw2_dc_b(0 to 1); + + prv_act_dis <= '0'; + act_dis <= prv_act_dis; + clkoff_dc_b <= prv_clkoff_dc_b; + + repr_sl_lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map ( + clkoff_b => prv_clkoff_dc_b, + thold => repr_sl_thold_0, + sg => sg_0, + act_dis => prv_act_dis, + forcee => repr_sl_force, + thold_b => repr_sl_thold_0_b ); + + repr_in <= '0'; + repr_rpwr_lat: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 1) + port map (nclk => nclk, + act => tihi, + forcee => repr_sl_force, + delay_lclkr => prv_delay_lclkr_dc(9), + mpw1_b => prv_mpw1_dc_b(9), + mpw2_b => prv_mpw2_dc_b(1), + thold_b => repr_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin(0) => repr_scan_in, + scout(0) => repr_scan_out, + din(0) => repr_in, + dout(0) => repr_UNUSED + ); + + spare_unused <= pc_fu_func_slp_sl_thold_3(1); + +end fuq_perv; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_pic.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_pic.vhdl new file mode 100644 index 0000000..0b60853 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_pic.vhdl @@ -0,0 +1,2718 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + + +entity fuq_pic is +generic( expand_type : integer := 2 ); +port( + vdd :inout power_logic; + gnd :inout power_logic; + clkoff_b :in std_ulogic; + act_dis :in std_ulogic; + flush :in std_ulogic; + delay_lclkr :in std_ulogic_vector(1 to 5); + mpw1_b :in std_ulogic_vector(1 to 5); + mpw2_b :in std_ulogic_vector(0 to 1); + sg_1 :in std_ulogic; + thold_1 :in std_ulogic; + fpu_enable :in std_ulogic; + nclk :in clk_logic; + + f_pic_si :in std_ulogic; + f_pic_so :out std_ulogic; + f_dcd_rf1_act :in std_ulogic; + f_dcd_rf1_aop_valid :in std_ulogic; + f_dcd_rf1_cop_valid :in std_ulogic; + f_dcd_rf1_bop_valid :in std_ulogic; + + f_dcd_rf1_fsel_b :in std_ulogic; + f_dcd_rf1_from_integer_b :in std_ulogic; + f_dcd_rf1_to_integer_b :in std_ulogic; + f_dcd_rf1_rnd_to_int_b :in std_ulogic; + f_dcd_rf1_math_b :in std_ulogic; + f_dcd_rf1_est_recip_b :in std_ulogic; + f_dcd_rf1_est_rsqrt_b :in std_ulogic; + f_dcd_rf1_move_b :in std_ulogic; + f_dcd_rf1_compare_b :in std_ulogic; + f_dcd_rf1_prenorm_b :in std_ulogic; + f_dcd_rf1_frsp_b :in std_ulogic; + f_dcd_rf1_mv_to_scr_b :in std_ulogic; + f_dcd_rf1_mv_from_scr_b :in std_ulogic; + f_dcd_rf1_div_beg :in std_ulogic; + f_dcd_rf1_sqrt_beg :in std_ulogic; + f_dcd_rf1_force_excp_dis :in std_ulogic; + f_dcd_rf1_ftdiv :in std_ulogic; + f_dcd_rf1_ftsqrt :in std_ulogic; + f_fmt_ex2_ae_ge_54 :in std_ulogic; + f_fmt_ex2_be_ge_54 :in std_ulogic; + f_fmt_ex2_be_ge_2 :in std_ulogic; + f_fmt_ex2_be_ge_2044 :in std_ulogic; + f_fmt_ex2_tdiv_rng_chk :in std_ulogic; + f_fmt_ex2_be_den :in std_ulogic; + f_dcd_rf1_sp :in std_ulogic; + f_dcd_rf1_uns_b :in std_ulogic; + f_dcd_rf1_word_b :in std_ulogic; + f_dcd_rf1_sp_conv_b :in std_ulogic; + f_dcd_rf1_pow2e_b :in std_ulogic; + f_dcd_rf1_log2e_b :in std_ulogic; + f_dcd_rf1_ordered_b :in std_ulogic; + f_dcd_rf1_sub_op_b :in std_ulogic; + f_dcd_rf1_op_rnd_v_b :in std_ulogic; + f_dcd_rf1_op_rnd_b :in std_ulogic_vector(0 to 1); + f_dcd_rf1_inv_sign_b :in std_ulogic; + f_dcd_rf1_sign_ctl_b :in std_ulogic_vector(0 to 1); + f_dcd_rf1_sgncpy_b :in std_ulogic; + + f_byp_pic_ex1_a_sign :in std_ulogic; + f_byp_pic_ex1_c_sign :in std_ulogic; + f_byp_pic_ex1_b_sign :in std_ulogic; + + + f_dcd_rf1_nj_deno :in std_ulogic; + f_dcd_rf1_nj_deni :in std_ulogic; + + f_cr2_ex1_fpscr_shadow :in std_ulogic_vector(0 to 7); + + f_fmt_ex1_sp_invalid :in std_ulogic; + f_fmt_ex1_a_zero :in std_ulogic; + f_fmt_ex1_a_expo_max :in std_ulogic; + f_fmt_ex1_a_frac_zero :in std_ulogic; + f_fmt_ex1_a_frac_msb :in std_ulogic; + f_fmt_ex1_c_zero :in std_ulogic; + f_fmt_ex1_c_expo_max :in std_ulogic; + f_fmt_ex1_c_frac_zero :in std_ulogic; + f_fmt_ex1_c_frac_msb :in std_ulogic; + f_fmt_ex1_b_zero :in std_ulogic; + f_fmt_ex1_b_expo_max :in std_ulogic; + f_fmt_ex1_b_frac_zero :in std_ulogic; + f_fmt_ex1_b_frac_msb :in std_ulogic; + f_fmt_ex1_prod_zero :in std_ulogic; + f_fmt_ex1_bexpu_le126 :in std_ulogic; + f_fmt_ex1_gt126 :in std_ulogic; + f_fmt_ex1_ge128 :in std_ulogic; + f_fmt_ex1_inf_and_beyond_sp :in std_ulogic; + f_alg_ex1_sign_frmw :in std_ulogic; + + f_fmt_ex2_pass_sign :in std_ulogic; + f_fmt_ex2_pass_msb :in std_ulogic; + f_fmt_ex1_b_imp :in std_ulogic; + f_fmt_ex1_b_frac_z32 :in std_ulogic; + + f_eie_ex2_wd_ov :in std_ulogic; + f_eie_ex2_dw_ov :in std_ulogic; + f_eie_ex2_wd_ov_if :in std_ulogic; + f_eie_ex2_dw_ov_if :in std_ulogic; + f_eie_ex2_lt_bias :in std_ulogic; + f_eie_ex2_eq_bias_m1 :in std_ulogic; + + f_alg_ex2_sel_byp :in std_ulogic; + f_alg_ex2_effsub_eac_b :in std_ulogic; + f_alg_ex2_sh_unf :in std_ulogic; + f_alg_ex2_sh_ovf :in std_ulogic; + + f_mad_ex2_uc_a_expo_den :in std_ulogic; + f_mad_ex2_uc_a_expo_den_sp :in std_ulogic; + + f_alg_ex3_int_fr :in std_ulogic; + f_alg_ex3_int_fi :in std_ulogic; + + f_eov_ex4_may_ovf :in std_ulogic; + f_add_ex4_fpcc_iu :in std_ulogic_vector(0 to 3); + f_add_ex4_sign_carry :in std_ulogic; + f_add_ex4_to_int_ovf_wd :in std_ulogic_vector(0 to 1); + f_add_ex4_to_int_ovf_dw :in std_ulogic_vector(0 to 1); + + + f_pic_fmt_ex1_act :out std_ulogic; + f_pic_eie_ex1_act :out std_ulogic; + f_pic_mul_ex1_act :out std_ulogic; + f_pic_alg_ex1_act :out std_ulogic; + f_pic_cr2_ex1_act :out std_ulogic; + f_pic_tbl_ex1_act :out std_ulogic; + f_pic_add_ex1_act_b :out std_ulogic; + f_pic_lza_ex1_act_b :out std_ulogic; + f_pic_eov_ex2_act_b :out std_ulogic; + f_pic_nrm_ex3_act_b :out std_ulogic; + f_pic_rnd_ex3_act_b :out std_ulogic; + f_pic_scr_ex2_act_b :out std_ulogic; + + + + f_pic_ex1_rnd_to_int :out std_ulogic; + f_pic_ex1_fsel :out std_ulogic; + f_pic_ex1_frsp_ue1 :out std_ulogic; + f_pic_ex2_frsp_ue1 :out std_ulogic; + f_pic_ex2_ue1 :out std_ulogic; + f_pic_ex1_effsub_raw :out std_ulogic; + f_pic_ex1_from_integer :out std_ulogic; + f_pic_ex1_sh_ovf_do :out std_ulogic; + f_pic_ex1_sh_ovf_ig_b :out std_ulogic; + f_pic_ex1_sh_unf_do :out std_ulogic; + f_pic_ex1_sh_unf_ig_b :out std_ulogic; + + f_pic_ex1_log2e :out std_ulogic; + f_pic_ex1_pow2e :out std_ulogic; + + f_pic_ex1_ftdiv :out std_ulogic; + f_pic_ex1_flush_en_sp :out std_ulogic; + f_pic_ex1_flush_en_dp :out std_ulogic; + + f_pic_ex2_est_recip :out std_ulogic; + f_pic_ex2_est_rsqrt :out std_ulogic; + + f_pic_ex2_force_sel_bexp :out std_ulogic; + f_pic_ex2_lzo_dis_prod :out std_ulogic; + f_pic_ex2_sp_b :out std_ulogic; + f_pic_ex2_sp_lzo :out std_ulogic; + f_pic_ex2_to_integer :out std_ulogic; + f_pic_ex2_prenorm :out std_ulogic; + f_pic_ex2_math_bzer_b :out std_ulogic; + f_pic_ex2_b_valid :out std_ulogic; + f_pic_ex2_rnd_nr :out std_ulogic; + f_pic_ex2_rnd_inf_ok :out std_ulogic; + + f_pic_ex3_cmp_sgnneg :out std_ulogic; + f_pic_ex3_cmp_sgnpos :out std_ulogic; + f_pic_ex3_is_eq :out std_ulogic; + f_pic_ex3_is_gt :out std_ulogic; + f_pic_ex3_is_lt :out std_ulogic; + f_pic_ex3_is_nan :out std_ulogic; + f_pic_ex3_sp_b :out std_ulogic; + f_pic_ex3_sel_est :out std_ulogic; + + + f_dcd_rf1_uc_ft_pos :in std_ulogic; + f_dcd_rf1_uc_ft_neg :in std_ulogic; + f_dcd_rf1_uc_mid :in std_ulogic; + f_dcd_rf1_uc_end :in std_ulogic; + f_dcd_rf1_uc_special :in std_ulogic; + f_dcd_ex2_uc_zx :in std_ulogic; + f_dcd_ex2_uc_vxidi :in std_ulogic; + f_dcd_ex2_uc_vxzdz :in std_ulogic; + f_dcd_ex2_uc_vxsqrt :in std_ulogic; + f_dcd_ex2_uc_vxsnan :in std_ulogic; + + f_mad_ex3_uc_special :out std_ulogic; + f_mad_ex3_uc_zx :out std_ulogic; + f_mad_ex3_uc_vxidi :out std_ulogic; + f_mad_ex3_uc_vxzdz :out std_ulogic; + f_mad_ex3_uc_vxsqrt :out std_ulogic; + f_mad_ex3_uc_vxsnan :out std_ulogic; + f_mad_ex3_uc_res_sign :out std_ulogic; + f_mad_ex3_uc_round_mode :out std_ulogic_vector(0 to 1); + + + + + + f_pic_ex4_byp_prod_nz :out std_ulogic; + f_pic_ex4_sel_est_b :out std_ulogic; + f_pic_ex1_nj_deni :out std_ulogic; + f_pic_ex4_nj_deno :out std_ulogic; + f_pic_ex4_oe :out std_ulogic; + f_pic_ex4_ov_en :out std_ulogic; + f_pic_ex4_ovf_en_oe0_b :out std_ulogic; + f_pic_ex4_ovf_en_oe1_b :out std_ulogic; + f_pic_ex4_quiet_b :out std_ulogic; + + f_dcd_ex2_uc_inc_lsb :in std_ulogic; + f_dcd_ex2_uc_guard :in std_ulogic; + f_dcd_ex2_uc_sticky :in std_ulogic; + f_dcd_ex2_uc_gs_v :in std_ulogic; + + f_pic_ex5_uc_inc_lsb :out std_ulogic; + f_pic_ex5_uc_guard :out std_ulogic; + f_pic_ex5_uc_sticky :out std_ulogic; + f_pic_ex5_uc_g_v :out std_ulogic; + f_pic_ex5_uc_s_v :out std_ulogic; + + f_pic_ex4_rnd_inf_ok_b :out std_ulogic; + f_pic_ex4_rnd_ni_b :out std_ulogic; + f_pic_ex4_rnd_nr_b :out std_ulogic; + f_pic_ex4_sel_fpscr_b :out std_ulogic; + f_pic_ex4_sp_b :out std_ulogic; + f_pic_ex4_spec_inf_b :out std_ulogic; + f_pic_ex4_spec_sel_k_e :out std_ulogic; + f_pic_ex4_spec_sel_k_f :out std_ulogic; + + f_pic_ex4_to_int_ov_all :out std_ulogic; + + f_pic_ex4_to_integer_b :out std_ulogic; + f_pic_ex4_word_b :out std_ulogic; + f_pic_ex4_uns_b :out std_ulogic; + f_pic_ex4_ue :out std_ulogic; + f_pic_ex4_uf_en :out std_ulogic; + f_pic_ex4_unf_en_ue0_b :out std_ulogic; + f_pic_ex4_unf_en_ue1_b :out std_ulogic; + + f_pic_ex5_en_exact_zero :out std_ulogic; + f_pic_ex5_frsp :out std_ulogic; + f_pic_ex5_compare_b :out std_ulogic; + f_pic_ex5_fi_pipe_v_b :out std_ulogic; + f_pic_ex5_fi_spec_b :out std_ulogic; + f_pic_ex5_flag_vxcvi_b :out std_ulogic; + f_pic_ex5_flag_vxidi_b :out std_ulogic; + f_pic_ex5_flag_vximz_b :out std_ulogic; + f_pic_ex5_flag_vxisi_b :out std_ulogic; + f_pic_ex5_flag_vxsnan_b :out std_ulogic; + f_pic_ex5_flag_vxsqrt_b :out std_ulogic; + f_pic_ex5_flag_vxvc_b :out std_ulogic; + f_pic_ex5_flag_vxzdz_b :out std_ulogic; + f_pic_ex5_flag_zx_b :out std_ulogic; + f_pic_ex5_fprf_hold_b :out std_ulogic; + f_pic_ex5_fprf_pipe_v_b :out std_ulogic; + f_pic_ex5_fprf_spec_b :out std_ulogic_vector(0 to 4); + f_pic_ex5_fr_pipe_v_b :out std_ulogic; + f_pic_ex5_fr_spec_b :out std_ulogic; + f_pic_ex5_invert_sign :out std_ulogic; + + f_pic_ex5_k_nan :out std_ulogic; + f_pic_ex5_k_inf :out std_ulogic; + f_pic_ex5_k_max :out std_ulogic; + f_pic_ex5_k_zer :out std_ulogic; + f_pic_ex5_k_one :out std_ulogic; + f_pic_ex5_k_int_maxpos :out std_ulogic; + f_pic_ex5_k_int_maxneg :out std_ulogic; + f_pic_ex5_k_int_zer :out std_ulogic; + f_pic_ex5_ox_pipe_v_b :out std_ulogic; + f_pic_ex5_round_sign :out std_ulogic; + f_pic_ex5_ux_pipe_v_b :out std_ulogic; + f_pic_ex5_scr_upd_move_b :out std_ulogic; + f_pic_ex5_scr_upd_pipe_b :out std_ulogic; + f_pic_ex5_fpr_wr_dis_b :out std_ulogic + +); + + + + +end fuq_pic; + +architecture fuq_pic of fuq_pic is + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal thold_0_b , thold_0, forcee, sg_0 :std_ulogic; + signal rf1_act , ex1_act , ex2_act , ex3_act , ex4_act :std_ulogic; + signal ex1_act_add :std_ulogic; + signal ex1_act_lza :std_ulogic; + signal ex2_act_eov :std_ulogic; + signal ex2_act_scr :std_ulogic; + signal ex3_act_nrm :std_ulogic; + signal ex3_act_rnd :std_ulogic; + signal spare_unused :std_ulogic_vector(0 to 3); + signal act_so , act_si :std_ulogic_vector(0 to 20); + + signal ex1_ctl_so , ex1_ctl_si :std_ulogic_vector(0 to 42); + signal ex2_ctl_so , ex2_ctl_si :std_ulogic_vector(0 to 56); + signal ex3_ctl_so , ex3_ctl_si :std_ulogic_vector(0 to 33); + signal ex4_ctl_so , ex4_ctl_si :std_ulogic_vector(0 to 28); + signal ex2_flg_so , ex2_flg_si :std_ulogic_vector(0 to 17); + signal ex3_scr_so , ex3_scr_si :std_ulogic_vector(0 to 7); + signal ex3_flg_so , ex3_flg_si :std_ulogic_vector(0 to 46); + signal ex4_scr_so , ex4_scr_si :std_ulogic_vector(0 to 7); + signal ex4_flg_so , ex4_flg_si :std_ulogic_vector(0 to 37); + signal ex5_flg_so , ex5_flg_si :std_ulogic_vector(0 to 41); + + signal ex4_may_ovf :std_ulogic; + signal ex5_unused :std_ulogic; + signal ex2_a_sign :std_ulogic; + signal ex3_pass_nan :std_ulogic; + signal ex2_pass_x :std_ulogic; + + signal ex1_rnd_fpscr, ex2_rnd_fpscr, ex3_rnd_fpscr :std_ulogic_vector(0 to 1); + signal ex1_div_sign, ex2_div_sign, ex3_div_sign :std_ulogic ; + + signal ex3_ve :std_ulogic ; + signal ex3_oe :std_ulogic ; + signal ex3_ue :std_ulogic ; + signal ex3_ze :std_ulogic ; + signal ex3_xe :std_ulogic ; + signal ex3_nonieee :std_ulogic ; + signal ex3_rnd0 :std_ulogic ; + signal ex3_rnd1 :std_ulogic ; + signal ex4_ve :std_ulogic ; + signal ex4_oe :std_ulogic ; + signal ex4_ue :std_ulogic ; + signal ex4_ze :std_ulogic ; + signal ex4_xe :std_ulogic ; + signal ex4_nonieee :std_ulogic ; + signal ex4_rnd0 :std_ulogic ; + signal ex4_rnd1 :std_ulogic ; + signal ex2_toint_nan_sign :std_ulogic ; + + signal ex1_uc_ft_neg, ex2_uc_ft_neg, ex3_uc_ft_neg :std_ulogic; + signal ex1_uc_ft_pos, ex2_uc_ft_pos, ex3_uc_ft_pos :std_ulogic; + signal ex1_a_inf :std_ulogic; + signal ex1_a_nan :std_ulogic; + signal ex1_a_sign :std_ulogic; + signal ex1_b_inf :std_ulogic; + signal ex1_b_nan :std_ulogic; + signal ex1_b_sign :std_ulogic; + signal ex1_b_sign_adj :std_ulogic; + signal ex1_b_sign_adj_x :std_ulogic; + signal ex1_b_sign_alt :std_ulogic; + signal ex1_a_valid :std_ulogic; + signal ex1_c_valid :std_ulogic; + signal ex1_b_valid :std_ulogic; + signal ex1_c_inf :std_ulogic; + signal ex1_sp_invalid :std_ulogic; + signal ex2_sp_invalid :std_ulogic; + signal ex1_c_nan :std_ulogic; + signal ex1_c_sign :std_ulogic; + signal ex1_compare :std_ulogic; + signal ex1_div_beg :std_ulogic; + signal ex1_est_recip :std_ulogic; + signal ex1_est_rsqrt :std_ulogic; + signal ex1_op_rnd_v :std_ulogic; + signal ex1_op_rnd :std_ulogic_vector(0 to 1); + signal ex1_from_integer :std_ulogic; + signal ex1_frsp :std_ulogic; + signal ex1_fsel :std_ulogic; + signal ex1_inv_sign :std_ulogic; + signal ex1_lzo_dis :std_ulogic; + signal ex1_uc_mid, ex2_uc_mid, ex3_uc_mid, ex4_uc_mid :std_ulogic; + signal ex1_math :std_ulogic; + signal ex1_move :std_ulogic; + signal ex1_mv_from_scr :std_ulogic; + signal ex1_mv_to_scr :std_ulogic; + signal ex1_p_sign :std_ulogic; + signal ex1_prenorm :std_ulogic; + signal ex1_sign_ctl :std_ulogic_vector(0 to 1); + signal ex1_sp :std_ulogic; + signal ex1_sp_b :std_ulogic; + signal ex1_sqrt_beg :std_ulogic; + signal ex1_sub_op :std_ulogic; + signal ex1_to_integer :std_ulogic; + signal ex1_ordered :std_ulogic; + signal ex1_word :std_ulogic; + signal rf1_uns :std_ulogic; + signal rf1_sp_conv :std_ulogic; + signal ex1_uns :std_ulogic; + signal ex2_uns :std_ulogic; + signal ex3_uns :std_ulogic; + signal ex4_uns :std_ulogic; + signal ex1_sp_conv :std_ulogic; + signal ex2_a_frac_msb :std_ulogic; + signal ex2_a_inf :std_ulogic; + signal ex2_a_nan :std_ulogic; + signal ex2_a_zero :std_ulogic; + signal ex2_any_inf :std_ulogic; + signal ex2_b_frac_msb :std_ulogic; + signal ex2_b_inf :std_ulogic; + signal ex2_b_nan :std_ulogic; + signal ex2_b_sign_adj :std_ulogic; + signal ex2_to_int_uns_neg :std_ulogic; + signal ex3_to_int_uns_neg :std_ulogic; + signal ex4_to_int_uns_neg :std_ulogic; + signal ex2_wd_ov_x :std_ulogic; + signal ex2_dw_ov_x :std_ulogic; + signal ex2_b_sign_alt :std_ulogic; + signal ex2_b_zero :std_ulogic; + signal ex3_b_zero :std_ulogic; + signal ex2_c_frac_msb :std_ulogic; + signal ex2_c_inf :std_ulogic; + signal ex2_c_nan :std_ulogic; + signal ex2_c_zero :std_ulogic; + signal ex2_cmp_sgnneg :std_ulogic; + signal ex2_cmp_sgnpos :std_ulogic; + signal ex2_cmp_zero :std_ulogic; + signal ex2_compare :std_ulogic; + signal ex2_div_beg :std_ulogic; + signal ex3_div_beg :std_ulogic; + signal ex4_div_beg :std_ulogic; + signal ex2_est_recip :std_ulogic; + signal ex2_est_rsqrt :std_ulogic; + signal ex2_rnd_dis :std_ulogic; + signal ex2_op_rnd :std_ulogic_vector(0 to 1); + signal ex2_from_integer :std_ulogic; + signal ex2_frsp :std_ulogic; + signal ex2_fsel :std_ulogic; + signal ex2_gen_inf :std_ulogic; + signal ex2_gen_max :std_ulogic; + signal ex2_gen_nan :std_ulogic; + signal ex2_gen_zero :std_ulogic; + signal ex2_inf_sign :std_ulogic; + signal ex2_inv_sign :std_ulogic; + signal ex2_is_eq :std_ulogic; + signal ex2_is_gt :std_ulogic; + signal ex2_is_lt :std_ulogic; + signal ex2_is_nan :std_ulogic; + signal ex2_lzo_dis :std_ulogic; + signal ex2_math :std_ulogic; + signal ex2_move :std_ulogic; + signal ex2_mv_from_scr :std_ulogic; + signal ex2_mv_to_scr :std_ulogic; + signal ex2_neg_sqrt_nz :std_ulogic; + signal ex2_p_inf :std_ulogic; + signal ex2_p_sign :std_ulogic; + signal ex2_p_zero :std_ulogic; + signal ex2_pass_en :std_ulogic; + signal ex2_pass_nan :std_ulogic; + signal ex2_prenorm :std_ulogic; + signal ex2_quiet :std_ulogic; + signal ex2_rnd0 :std_ulogic; + signal ex2_rnd1 :std_ulogic; + signal ex2_rnd_inf_ok :std_ulogic; + signal ex2_rnd_nr :std_ulogic; + signal ex2_sp :std_ulogic; + signal ex2_sp_notrunc :std_ulogic; + signal ex2_sp_o_frsp :std_ulogic; + signal ex2_spec_sign :std_ulogic; + signal ex2_sqrt_beg :std_ulogic; + signal ex3_sqrt_beg :std_ulogic; + signal ex4_sqrt_beg :std_ulogic; + signal ex2_sub_op :std_ulogic; + signal ex2_to_integer :std_ulogic; + signal ex2_ue :std_ulogic; + signal ex2_ordered :std_ulogic; + signal ex2_nonieee :std_ulogic; + signal ex2_ze :std_ulogic; + signal ex2_ve :std_ulogic; + signal ex2_oe :std_ulogic; + signal ex2_xe :std_ulogic; + signal ex2_vxcvi :std_ulogic; + signal ex2_vxidi :std_ulogic; + signal ex2_vximz :std_ulogic; + signal ex2_vxisi :std_ulogic; + signal ex2_vxsnan :std_ulogic; + signal ex2_vxsqrt :std_ulogic; + signal ex2_vxvc :std_ulogic; + signal ex2_vxzdz :std_ulogic; + signal ex2_word :std_ulogic; + signal ex2_zx :std_ulogic; + signal ex3_b_sign_adj :std_ulogic; + signal ex3_b_sign_alt :std_ulogic; + signal ex3_cmp_sgnneg :std_ulogic; + signal ex3_cmp_sgnpos :std_ulogic; + signal ex3_compare :std_ulogic; + signal ex3_dw_ov :std_ulogic; + signal ex3_dw_ov_if :std_ulogic; + signal ex3_effsub_eac :std_ulogic; + signal ex4_effsub_eac :std_ulogic; + signal ex3_est_recip :std_ulogic; + signal ex3_est_rsqrt :std_ulogic; + signal ex3_rnd_dis :std_ulogic; + signal ex3_from_integer :std_ulogic; + signal ex3_frsp :std_ulogic; + signal ex3_fsel :std_ulogic; + signal ex3_gen_inf :std_ulogic; + signal ex3_gen_inf_mutex :std_ulogic; + signal ex3_gen_max_mutex :std_ulogic; + signal ex3_gen_max :std_ulogic; + signal ex3_gen_nan :std_ulogic; + signal ex3_gen_nan_mutex :std_ulogic; + signal ex3_gen_zer_mutex :std_ulogic; + signal ex3_gen_zero :std_ulogic; + signal ex3_inv_sign :std_ulogic; + signal ex3_is_eq :std_ulogic; + signal ex3_is_gt :std_ulogic; + signal ex3_is_lt :std_ulogic; + signal ex3_is_nan :std_ulogic; + signal ex3_math :std_ulogic; + signal ex3_move :std_ulogic; + signal ex3_mv_from_scr :std_ulogic; + signal ex3_mv_to_scr :std_ulogic; + signal ex3_oe_x :std_ulogic; + signal ex3_ov_en :std_ulogic; + signal ex3_ovf_en_oe0 :std_ulogic; + signal ex3_ovf_en_oe1 :std_ulogic; + signal ex3_p_sign :std_ulogic; + signal ex3_p_sign_may :std_ulogic; + signal ex3_prenorm :std_ulogic; + signal ex3_quiet :std_ulogic; + signal ex3_sel_byp :std_ulogic; + signal ex3_sh_ovf :std_ulogic; + signal ex3_sh_unf :std_ulogic; + signal ex3_sign_nco :std_ulogic; + signal ex3_sign_pco :std_ulogic; + signal ex3_sp :std_ulogic; + signal ex3_sp_x :std_ulogic; + signal ex3_sp_conv :std_ulogic; + signal ex2_sp_conv :std_ulogic; + signal ex3_spec_sel_e :std_ulogic; + signal ex3_spec_sel_f :std_ulogic; + signal ex3_spec_sign :std_ulogic; + signal ex3_spec_sign_x :std_ulogic; + signal ex3_spec_sign_sel :std_ulogic; + signal ex3_sub_op :std_ulogic; + signal ex3_to_int_dw :std_ulogic; + signal ex3_to_int_ov :std_ulogic; + signal ex3_to_int_ov_if :std_ulogic; + signal ex3_to_int_wd :std_ulogic; + signal ex3_to_integer :std_ulogic; + signal ex3_ue_x :std_ulogic; + signal ex3_uf_en :std_ulogic; + signal ex3_unf_en_oe0 :std_ulogic; + signal ex3_unf_en_oe1 :std_ulogic; + signal ex3_vxcvi :std_ulogic; + signal ex3_vxidi :std_ulogic; + signal ex3_vximz :std_ulogic; + signal ex3_vxisi :std_ulogic; + signal ex3_vxsnan :std_ulogic; + signal ex3_vxsqrt :std_ulogic; + signal ex3_vxvc :std_ulogic; + signal ex3_vxzdz :std_ulogic; + signal ex3_wd_ov :std_ulogic; + signal ex3_wd_ov_if :std_ulogic; + signal ex3_word :std_ulogic; + signal ex3_word_to :std_ulogic; + signal ex3_zx :std_ulogic; + signal ex4_compare :std_ulogic; + signal ex5_compare :std_ulogic; + signal ex4_en_exact_zero :std_ulogic; + signal ex4_est_recip :std_ulogic; + signal ex4_est_rsqrt :std_ulogic; + signal ex4_rnd_dis :std_ulogic; + signal ex4_fpr_wr_dis :std_ulogic; + signal ex4_fprf_pipe_v :std_ulogic; + signal ex4_fprf_spec :std_ulogic_vector(0 to 4); + signal ex4_fprf_spec_x :std_ulogic_vector(0 to 4); + signal ex4_fr_pipe_v :std_ulogic; + signal ex4_from_integer :std_ulogic; + signal ex4_frsp :std_ulogic; + signal ex5_frsp :std_ulogic; + signal ex4_fsel :std_ulogic; + signal ex4_gen_inf :std_ulogic; + signal ex4_gen_inf_sign :std_ulogic; + signal ex4_gen_max :std_ulogic; + signal ex4_gen_nan :std_ulogic; + signal ex4_pass_nan :std_ulogic; + signal ex4_gen_zero :std_ulogic; + signal ex4_inv_sign :std_ulogic; + signal ex4_invert_sign :std_ulogic; + signal ex4_k_max_fp :std_ulogic; + signal ex4_math :std_ulogic; + signal ex4_move :std_ulogic; + signal ex4_mv_from_scr :std_ulogic; + signal ex4_mv_to_scr :std_ulogic; + signal ex4_ov_en :std_ulogic; + signal ex4_ovf_en_oe0 :std_ulogic; + signal ex4_ovf_en_oe1 :std_ulogic; + signal ex4_ox_pipe_v :std_ulogic; + signal ex4_prenorm :std_ulogic; + signal ex4_quiet :std_ulogic; + signal ex4_rnd_en :std_ulogic; + signal ex4_rnd_inf_ok :std_ulogic; + signal ex4_rnd_pi :std_ulogic; + signal ex4_rnd_ni :std_ulogic; + signal ex4_rnd_nr :std_ulogic; + signal ex4_rnd_zr :std_ulogic; + signal ex4_rnd_nr_ok :std_ulogic; + signal ex4_round_sign :std_ulogic; + signal ex4_round_sign_x :std_ulogic; + signal ex4_scr_upd_move :std_ulogic; + signal ex4_scr_upd_pipe :std_ulogic; + signal ex4_sel_spec_e :std_ulogic; + signal ex4_sel_spec_f :std_ulogic; + signal ex4_sel_spec_fr :std_ulogic; + signal ex4_sign_nco :std_ulogic; + signal ex4_sign_pco :std_ulogic; + signal ex4_sign_nco_x :std_ulogic; + signal ex4_sign_pco_x :std_ulogic; + signal ex4_sign_nco_xx :std_ulogic; + signal ex4_sign_pco_xx :std_ulogic; + signal ex4_sp :std_ulogic; + signal ex4_spec_sel_e :std_ulogic; + signal ex4_spec_sel_f :std_ulogic; + signal ex4_sub_op :std_ulogic; + signal ex4_to_int_dw :std_ulogic; + signal ex4_to_int_ov :std_ulogic; + signal ex4_to_int_ov_if :std_ulogic; + signal ex4_to_int_wd :std_ulogic; + signal ex4_to_integer :std_ulogic; + signal ex4_uf_en :std_ulogic; + signal ex4_unf_en_oe0 :std_ulogic; + signal ex4_unf_en_oe1 :std_ulogic; + signal ex4_upd_fpscr_ops :std_ulogic; + signal ex4_vx :std_ulogic; + signal ex4_vxidi :std_ulogic; + signal ex4_vximz :std_ulogic; + signal ex4_vxisi :std_ulogic; + signal ex4_vxsnan :std_ulogic; + signal ex4_vxsqrt :std_ulogic; + signal ex4_vxvc :std_ulogic; + signal ex4_vxcvi :std_ulogic; + signal ex4_vxcvi_ov :std_ulogic; + signal ex4_to_int_ov_all_x :std_ulogic; + signal ex4_to_int_ov_all :std_ulogic; + signal ex4_to_int_ov_all_gt :std_ulogic; + signal ex4_to_int_k_sign :std_ulogic; + signal ex4_vxzdz :std_ulogic; + signal ex4_word :std_ulogic; + signal ex4_zx :std_ulogic; + signal ex5_en_exact_zero :std_ulogic; + signal ex5_fpr_wr_dis :std_ulogic; + signal ex5_fprf_pipe_v :std_ulogic; + signal ex5_fprf_spec :std_ulogic_vector(0 to 4); + signal ex5_fr_pipe_v :std_ulogic; + signal ex5_invert_sign :std_ulogic; + signal ex5_ox_pipe_v :std_ulogic; + signal ex5_round_sign :std_ulogic; + signal ex5_scr_upd_move :std_ulogic; + signal ex5_scr_upd_pipe :std_ulogic; + signal ex5_vxcvi :std_ulogic; + signal ex5_vxidi :std_ulogic; + signal ex5_vximz :std_ulogic; + signal ex5_vxisi :std_ulogic; + signal ex5_vxsnan :std_ulogic; + signal ex5_vxsqrt :std_ulogic; + signal ex5_vxvc :std_ulogic; + signal ex5_vxzdz :std_ulogic; + signal ex5_zx :std_ulogic; + signal ex5_k_nan :std_ulogic; + signal ex5_k_inf :std_ulogic; + signal ex5_k_max :std_ulogic; + signal ex5_k_zer :std_ulogic; + signal ex5_k_int_maxpos :std_ulogic; + signal ex5_k_int_maxneg :std_ulogic; + signal ex5_k_int_zer :std_ulogic; + signal ex4_gen_any :std_ulogic; + signal ex4_k_nan :std_ulogic; + signal ex4_k_inf :std_ulogic; + signal ex4_k_max :std_ulogic; + signal ex4_k_zer :std_ulogic; + signal ex4_k_int_maxpos :std_ulogic; + signal ex4_k_int_maxneg :std_ulogic; + signal ex4_k_int_zer :std_ulogic; + signal ex4_k_nan_x :std_ulogic; + signal ex4_k_inf_x :std_ulogic; + signal ex4_k_max_x :std_ulogic; + signal ex4_k_zer_x :std_ulogic; + signal ex2_a_valid :std_ulogic; + signal ex2_c_valid :std_ulogic; + signal ex2_b_valid :std_ulogic; + signal ex2_prod_zero :std_ulogic; + signal ex4_byp_prod_nz :std_ulogic ; + signal ex3_byp_prod_nz :std_ulogic ; + signal ex3_byp_prod_nz_sub :std_ulogic ; + signal ex3_a_valid :std_ulogic ; + signal ex3_c_valid :std_ulogic ; + signal ex3_b_valid :std_ulogic ; + signal ex3_prod_zero :std_ulogic ; + signal ex4_int_fr :std_ulogic ; + signal ex4_int_fi :std_ulogic ; + signal ex4_fi_spec :std_ulogic; + signal ex4_fr_spec :std_ulogic; + signal ex5_fi_spec :std_ulogic; + signal ex5_fr_spec :std_ulogic; + signal ex2_toint_genz :std_ulogic; + signal ex2_a_snan :std_ulogic; + signal ex2_b_snan :std_ulogic; + signal ex2_c_snan :std_ulogic; + signal ex2_a_qnan :std_ulogic; + signal ex2_b_qnan :std_ulogic; + signal ex2_nan_op_grp1 :std_ulogic; + signal ex2_nan_op_grp2 :std_ulogic; + signal ex2_compo :std_ulogic; + signal ex5_fprf_hold :std_ulogic; + signal ex4_fprf_hold :std_ulogic; + signal ex4_fprf_hold_ops :std_ulogic; + signal ex1_bf_10000 :std_ulogic; + signal ex2_bf_10000 :std_ulogic; + signal ex3_bf_10000 :std_ulogic; + + signal ex1_rnd_to_int :std_ulogic; + signal ex2_rnd_to_int :std_ulogic; + signal ex3_rnd_to_int :std_ulogic; + signal ex4_rnd_to_int :std_ulogic; + signal ex3_lt_bias :std_ulogic; + signal ex3_eq_bias_m1 :std_ulogic; +signal ex3_gen_rnd2int :std_ulogic; +signal ex3_gen_one_rnd2int :std_ulogic; +signal ex3_gen_zer_rnd2int :std_ulogic; +signal ex2_gen_one, ex3_gen_one, ex3_gen_one_mutex :std_ulogic; +signal ex4_gen_one :std_ulogic; +signal ex4_k_one :std_ulogic; +signal ex5_k_one :std_ulogic; +signal ex4_k_one_x :std_ulogic; +signal ex3_rnd2int_up :std_ulogic; +signal ex4_sel_est :std_ulogic; +signal ex1_ve :std_ulogic; +signal ex1_oe :std_ulogic; +signal ex1_ue :std_ulogic; +signal ex1_ze :std_ulogic; +signal ex1_xe :std_ulogic; +signal ex1_nonieee :std_ulogic; +signal ex1_rnd0 :std_ulogic; +signal ex1_rnd1 :std_ulogic; +signal ex1_rnd_dis :std_ulogic; + signal rf1_fsel :std_ulogic; + signal rf1_from_integer :std_ulogic; + signal rf1_to_integer :std_ulogic; + signal rf1_math :std_ulogic; + signal rf1_est_recip :std_ulogic; + signal rf1_est_rsqrt :std_ulogic; + signal rf1_move :std_ulogic; + signal rf1_compare :std_ulogic; + signal rf1_prenorm :std_ulogic; + signal rf1_frsp :std_ulogic; + signal rf1_mv_to_scr :std_ulogic; + signal rf1_mv_from_scr :std_ulogic; + signal rf1_div_beg :std_ulogic; + signal rf1_sqrt_beg :std_ulogic; + signal rf1_sp :std_ulogic; + signal rf1_word :std_ulogic; + signal rf1_ordered :std_ulogic; + signal rf1_sub_op :std_ulogic; + signal rf1_op_rnd_v :std_ulogic; + signal rf1_inv_sign :std_ulogic; + signal rf1_sign_ctl :std_ulogic_vector(0 to 1); + signal rf1_sgncpy, ex1_sgncpy :std_ulogic; + signal rf1_op_rnd :std_ulogic_vector(0 to 1); + signal rf1_rnd_to_int :std_ulogic; + signal ex2_effsub_eac :std_ulogic; + signal ex1_flush_dis_dp, ex1_flush_dis_sp :std_ulogic; + signal ex4_to_integer_ken :std_ulogic; + signal rf1_log2e, rf1_pow2e :std_ulogic; + signal ex1_log2e, ex1_pow2e :std_ulogic; + signal ex2_log2e, ex2_pow2e :std_ulogic; + signal ex3_log2e, ex3_pow2e :std_ulogic; + signal ex4_log2e, ex4_pow2e :std_ulogic; + signal ex2_log_ofzero :std_ulogic ; + signal ex2_bexpu_le126 , ex2_gt126 , ex2_ge128 :std_ulogic; + signal ex2_gen_nan_log :std_ulogic ; + signal ex2_gen_inf_log :std_ulogic ; + signal ex2_gen_inf_pow :std_ulogic ; + signal ex2_gen_zero_pow :std_ulogic ; + signal ex1_ovf_unf_dis, ex2_ovf_unf_dis, ex3_ovf_unf_dis, ex4_ovf_unf_dis :std_ulogic; + signal ex2_exact_zero_sign :std_ulogic ; + signal ex2_rnd_ni :std_ulogic ; + signal ex2_gen_inf_sq :std_ulogic; + signal ex2_gen_inf_dv :std_ulogic; + signal ex2_gen_zer_sq :std_ulogic; + signal ex2_gen_zer_dv :std_ulogic; + signal ex2_gen_nan_sq :std_ulogic; + signal ex2_gen_nan_dv :std_ulogic; + signal ex2_prenorm_special :std_ulogic ; + signal ex2_prenorm_sign :std_ulogic ; + + signal ex3_uc_inc_lsb , ex4_uc_inc_lsb , ex5_uc_inc_lsb :std_ulogic; + signal ex3_uc_guard , ex4_uc_guard , ex5_uc_guard :std_ulogic; + signal ex3_uc_sticky , ex4_uc_sticky , ex5_uc_sticky :std_ulogic; + signal ex3_uc_gs_v , ex4_uc_gs_v , ex4_uc_s_v , ex4_uc_g_v, ex5_uc_s_v , ex5_uc_g_v :std_ulogic; + signal ex2_uc_g_ig ,ex3_uc_g_ig , ex4_uc_g_ig :std_ulogic; + signal ex1_force_excp_dis :std_ulogic ; + signal rf1_uc_end_nspec, ex1_uc_end_nspec :std_ulogic; + signal rf1_uc_end_spec, ex1_uc_end_spec, ex2_uc_end_spec, ex3_uc_end_spec, ex4_uc_end_spec :std_ulogic; + signal unused :std_ulogic; + signal rf1_nj_deno_x, ex1_nj_deno, ex2_nj_deno, ex3_nj_deno, ex3_nj_deno_x, ex4_nj_deno : std_ulogic; + signal rf1_nj_deni_x, ex1_nj_deni, rf1_den_ok :std_ulogic; + signal ex2_gen_nan_pow :std_ulogic ; + signal ex2_inf_and_beyond_sp :std_ulogic ; + signal ex1_ftdiv, ex1_ftsqrt, ex2_ftdiv, ex2_ftsqrt, ex2_accuracy , ex2_b_imp :std_ulogic ; + + +begin + + unused <= ex3_byp_prod_nz_sub or ex4_sel_spec_f or + rf1_act or + ex2_op_rnd(0) or + ex2_op_rnd(1) or + ex3_b_sign_adj or + ex3_b_valid or + ex3_gen_max or + ex3_sh_unf or + ex3_sh_ovf or + ex4_nonieee or + ex4_xe or + ex4_fsel or + ex4_move or + ex4_prenorm or + ex4_div_beg or + ex4_sqrt_beg or + ex4_sub_op or + ex4_log2e or + ex4_pow2e or + ex5_unused; + + + + thold_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => thold_1, + q(0) => thold_0 ); + + sg_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => sg_1 , + q(0) => sg_0 ); + + + lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map ( + clkoff_b => clkoff_b, + thold => thold_0, + sg => sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => thold_0_b ); + + + + + + + act_lat: tri_rlmreg_p generic map (width=> 21, expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + forcee => forcee, + delay_lclkr => delay_lclkr(4), + mpw1_b => mpw1_b(4), + mpw2_b => mpw2_b(0), + act => fpu_enable, + thold_b => thold_0_b, + sg => sg_0, + scout => act_so , + scin => act_si , + din(0) => spare_unused(0), + din(1) => spare_unused(1), + din(2) => tiup, + din(3) => f_dcd_rf1_act, + din(4) => f_dcd_rf1_act, + din(5) => f_dcd_rf1_act, + din(6) => f_dcd_rf1_act, + din(7) => tiup, + din(8) => f_dcd_rf1_act , + din(9) => f_dcd_rf1_act, + din(10) => f_dcd_rf1_act, + din(11) => f_dcd_rf1_act, + din(12) => ex1_act, + din(13) => ex1_act, + din(14) => ex1_act, + din(15) => ex2_act, + din(16) => ex2_act, + din(17) => ex2_act, + din(18) => ex3_act, + din(19) => spare_unused(2), + din(20) => spare_unused(3), + dout(0) => spare_unused(0), + dout(1) => spare_unused(1), + dout(2) => f_pic_fmt_ex1_act , + dout(3) => f_pic_eie_ex1_act , + dout(4) => f_pic_mul_ex1_act , + dout(5) => f_pic_alg_ex1_act , + dout(6) => f_pic_cr2_ex1_act , + dout(7) => rf1_act, + dout(8) => f_pic_tbl_ex1_act , + dout(9) => ex1_act, + dout(10) => ex1_act_add , + dout(11) => ex1_act_lza , + dout(12) => ex2_act, + dout(13) => ex2_act_eov , + dout(14) => ex2_act_scr , + dout(15) => ex3_act, + dout(16) => ex3_act_nrm , + dout(17) => ex3_act_rnd , + dout(18) => ex4_act, + dout(19) => spare_unused(2) , + dout(20) => spare_unused(3) ); + + + + f_pic_add_ex1_act_b <= not ex1_act_add ; + f_pic_lza_ex1_act_b <= not ex1_act_lza ; + f_pic_eov_ex2_act_b <= not ex2_act_eov ; + f_pic_scr_ex2_act_b <= not ex2_act_scr ; + f_pic_nrm_ex3_act_b <= not ex3_act_nrm ; + f_pic_rnd_ex3_act_b <= not ex3_act_rnd ; + + + + + + rf1_fsel <= not f_dcd_rf1_fsel_b ; + rf1_from_integer <= not f_dcd_rf1_from_integer_b ; + rf1_to_integer <= not f_dcd_rf1_to_integer_b ; + rf1_math <= not f_dcd_rf1_math_b ; + rf1_est_recip <= not f_dcd_rf1_est_recip_b ; + rf1_est_rsqrt <= not f_dcd_rf1_est_rsqrt_b ; + rf1_move <= not f_dcd_rf1_move_b ; + rf1_compare <= not f_dcd_rf1_compare_b ; + rf1_prenorm <= not(f_dcd_rf1_prenorm_b) or f_dcd_rf1_div_beg or f_dcd_rf1_sqrt_beg ; + rf1_frsp <= not f_dcd_rf1_frsp_b ; + rf1_mv_to_scr <= not f_dcd_rf1_mv_to_scr_b ; + rf1_mv_from_scr <= not f_dcd_rf1_mv_from_scr_b ; + rf1_div_beg <= f_dcd_rf1_div_beg ; + rf1_sqrt_beg <= f_dcd_rf1_sqrt_beg ; + rf1_sp <= not f_dcd_rf1_sp ; + rf1_word <= not f_dcd_rf1_word_b ; + rf1_uns <= not f_dcd_rf1_uns_b ; + rf1_sp_conv <= not f_dcd_rf1_sp_conv_b ; + rf1_ordered <= not f_dcd_rf1_ordered_b ; + rf1_sub_op <= not f_dcd_rf1_sub_op_b ; + rf1_op_rnd_v <= not f_dcd_rf1_op_rnd_v_b ; + rf1_inv_sign <= not f_dcd_rf1_inv_sign_b ; + rf1_sign_ctl(0) <= not f_dcd_rf1_sign_ctl_b(0) ; + rf1_sign_ctl(1) <= not f_dcd_rf1_sign_ctl_b(1) ; + rf1_sgncpy <= not f_dcd_rf1_sgncpy_b ; + rf1_op_rnd(0) <= not f_dcd_rf1_op_rnd_b(0) ; + rf1_op_rnd(1) <= not f_dcd_rf1_op_rnd_b(1) ; + rf1_rnd_to_int <= not f_dcd_rf1_rnd_to_int_b ; + rf1_log2e <= not f_dcd_rf1_log2e_b ; + rf1_pow2e <= not f_dcd_rf1_pow2e_b ; + rf1_uc_end_nspec <= f_dcd_rf1_uc_end and not f_dcd_rf1_uc_special ; + rf1_uc_end_spec <= f_dcd_rf1_uc_end and f_dcd_rf1_uc_special ; + + + rf1_den_ok <= rf1_move or rf1_mv_to_scr or rf1_mv_from_scr or rf1_fsel or f_dcd_rf1_uc_mid ; + + + rf1_nj_deno_x <= f_dcd_rf1_nj_deno and + not f_dcd_rf1_div_beg and + not f_dcd_rf1_sqrt_beg and + not rf1_to_integer and + not rf1_den_ok ; + + rf1_nj_deni_x <= f_dcd_rf1_nj_deni and + not rf1_den_ok ; + + + + ex1_ctl_lat: tri_rlmreg_p generic map (width=> 43, expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + forcee => forcee, + delay_lclkr => delay_lclkr(1), + mpw1_b => mpw1_b(1), + mpw2_b => mpw2_b(0), + nclk => nclk, + act => f_dcd_rf1_act, + thold_b => thold_0_b, + sg => sg_0, + scout => ex1_ctl_so , + scin => ex1_ctl_si , + din( 0) => rf1_fsel , + din( 1) => rf1_from_integer , + din( 2) => rf1_to_integer , + din( 3) => rf1_math , + din( 4) => rf1_est_recip , + din( 5) => rf1_est_rsqrt , + din( 6) => rf1_move , + din( 7) => rf1_compare , + din( 8) => rf1_prenorm , + din( 9) => rf1_frsp , + din(10) => rf1_mv_to_scr , + din(11) => rf1_mv_from_scr , + din(12) => rf1_div_beg , + din(13) => rf1_sqrt_beg , + din(14) => rf1_sp , + din(15) => rf1_word , + din(16) => rf1_ordered , + din(17) => rf1_sub_op , + din(18) => f_dcd_rf1_uc_mid , + din(19) => rf1_op_rnd_v , + din(20) => rf1_inv_sign , + din(21) => rf1_sign_ctl(0) , + din(22) => rf1_sign_ctl(1) , + din(23) => f_dcd_rf1_aop_valid , + din(24) => f_dcd_rf1_cop_valid , + din(25) => f_dcd_rf1_bop_valid , + din(26) => rf1_op_rnd(0) , + din(27) => rf1_op_rnd(1) , + din(28) => rf1_rnd_to_int , + din(29) => rf1_uns , + din(30) => rf1_sp_conv , + din(31) => rf1_sgncpy , + din(32) => rf1_log2e , + din(33) => rf1_pow2e , + din(34) => f_dcd_rf1_uc_ft_pos , + din(35) => f_dcd_rf1_uc_ft_neg , + din(36) => f_dcd_rf1_force_excp_dis , + din(37) => rf1_uc_end_nspec , + din(38) => rf1_uc_end_spec , + din(39) => rf1_nj_deno_x , + din(40) => rf1_nj_deni_x , + din(41) => f_dcd_rf1_ftdiv , + din(42) => f_dcd_rf1_ftsqrt , + + dout( 0) => ex1_fsel , + dout( 1) => ex1_from_integer , + dout( 2) => ex1_to_integer , + dout( 3) => ex1_math , + dout( 4) => ex1_est_recip , + dout( 5) => ex1_est_rsqrt , + dout( 6) => ex1_move , + dout( 7) => ex1_compare , + dout( 8) => ex1_prenorm , + dout( 9) => ex1_frsp , + dout(10) => ex1_mv_to_scr , + dout(11) => ex1_mv_from_scr , + dout(12) => ex1_div_beg , + dout(13) => ex1_sqrt_beg , + dout(14) => ex1_sp_b , + dout(15) => ex1_word , + dout(16) => ex1_ordered , + dout(17) => ex1_sub_op , + dout(18) => ex1_uc_mid , + dout(19) => ex1_op_rnd_v , + dout(20) => ex1_inv_sign , + dout(21) => ex1_sign_ctl (0) , + dout(22) => ex1_sign_ctl (1) , + dout(23) => ex1_a_valid , + dout(24) => ex1_c_valid , + dout(25) => ex1_b_valid , + dout(26) => ex1_op_rnd(0) , + dout(27) => ex1_op_rnd(1) , + dout(28) => ex1_rnd_to_int , + dout(29) => ex1_uns , + dout(30) => ex1_sp_conv , + dout(31) => ex1_sgncpy , + dout(32) => ex1_log2e , + dout(33) => ex1_pow2e , + dout(34) => ex1_uc_ft_pos , + dout(35) => ex1_uc_ft_neg , + dout(36) => ex1_force_excp_dis , + dout(37) => ex1_uc_end_nspec , + dout(38) => ex1_uc_end_spec , + dout(39) => ex1_nj_deno , + dout(40) => ex1_nj_deni , + dout(41) => ex1_ftdiv , + dout(42) => ex1_ftsqrt ); + + f_pic_ex1_ftdiv <= ex1_ftdiv ; + + f_pic_ex1_nj_deni <= ex1_nj_deni ; + + ex1_ovf_unf_dis <= ex1_uc_mid or + ex1_prenorm or + ex1_move or + ex1_fsel or + ex1_mv_to_scr or + ex1_mv_from_scr ; + + ex1_ve <= f_cr2_ex1_fpscr_shadow(0) and not ex1_force_excp_dis; + ex1_oe <= f_cr2_ex1_fpscr_shadow(1) and not ex1_force_excp_dis; + ex1_ue <= f_cr2_ex1_fpscr_shadow(2) and not ex1_force_excp_dis; + ex1_ze <= f_cr2_ex1_fpscr_shadow(3) and not ex1_force_excp_dis; + ex1_xe <= f_cr2_ex1_fpscr_shadow(4) and not ex1_force_excp_dis; + ex1_nonieee <= f_cr2_ex1_fpscr_shadow(5); + + ex1_rnd_fpscr(0 to 1) <= f_cr2_ex1_fpscr_shadow(6 to 7); + + + + ex1_rnd0 <= ( f_cr2_ex1_fpscr_shadow(6) and not ex1_op_rnd_v ) or + ( ex1_op_rnd(0) and ex1_op_rnd_v ); + ex1_rnd1 <= ( f_cr2_ex1_fpscr_shadow(7) and not ex1_op_rnd_v ) or + ( ex1_op_rnd(1) and ex1_op_rnd_v ) ; + ex1_rnd_dis <= tidn and f_fmt_ex1_prod_zero and ex1_nj_deni ; + + f_pic_ex1_rnd_to_int <= ex1_rnd_to_int ; + + + + ex1_flush_dis_sp <= ex1_uc_mid or + ex1_fsel or + ex1_log2e or + ex1_pow2e or + ex1_prenorm or + ex1_move or + ex1_to_integer or + ex1_frsp ; + + ex1_flush_dis_dp <= ex1_flush_dis_sp or + ex1_from_integer or + ex1_ftdiv or + ex1_ftsqrt or + ex1_mv_to_scr ; + + f_pic_ex1_flush_en_sp <= not ex1_flush_dis_sp ; + f_pic_ex1_flush_en_dp <= not ex1_flush_dis_dp ; + + f_pic_ex1_log2e <= ex1_log2e; + f_pic_ex1_pow2e <= ex1_pow2e; + + + + f_pic_ex1_from_integer <= ex1_from_integer ; + f_pic_ex1_fsel <= ex1_fsel ; + + f_pic_ex1_sh_ovf_do <= ex1_fsel or + ex1_move or + ex1_prenorm or + ex1_mv_to_scr or + ex1_mv_from_scr ; + + f_pic_ex1_sh_ovf_ig_b <= not( ex1_from_integer or not ex1_b_valid ); + + f_pic_ex1_sh_unf_do <= not ex1_b_valid + or ex1_est_recip + or ex1_est_rsqrt ; + + f_pic_ex1_sh_unf_ig_b <= not ex1_from_integer ; + + +ex1_a_sign <= f_byp_pic_ex1_a_sign ; +ex1_c_sign <= f_byp_pic_ex1_c_sign ; +ex1_b_sign <= f_byp_pic_ex1_b_sign ; + + ex1_b_sign_adj_x <= ex1_b_sign xor ex1_sub_op ; + ex1_p_sign <= ex1_a_sign xor ex1_c_sign ; + + ex1_b_sign_adj <= + (ex1_b_sign_adj_x and ex1_b_valid ) or + (ex1_p_sign and not ex1_b_valid ) ; + + ex1_div_sign <= (ex1_a_sign xor ex1_b_sign) and ex1_div_beg ; + + + f_pic_ex1_effsub_raw <= + (ex1_math or ex1_compare) and ( ex1_b_sign_adj xor ex1_p_sign ); + + + ex1_b_sign_alt <= + ( ex1_a_sign and ex1_move and ex1_sgncpy and ex1_b_valid ) or + ( ex1_b_sign and ex1_move and ex1_sign_ctl(0) and ex1_b_valid and not ex1_sgncpy ) or + (not ex1_b_sign and ex1_move and ex1_sign_ctl(1) and ex1_b_valid and not ex1_sgncpy ) or + ( f_alg_ex1_sign_frmw and ex1_from_integer and not ex1_uns and ex1_word ) or + ( ex1_b_sign and ex1_from_integer and not ex1_uns and not ex1_word ) or + ( ex1_b_sign_adj and (ex1_math or ex1_compare) ) or + ( ex1_b_sign and not ex1_move + and not (ex1_math or ex1_compare) + and ex1_b_valid + and not ex1_from_integer ) ; + + + + + ex1_lzo_dis <= + ( ex1_uc_mid ) or + ( ex1_prenorm ) or + ( ex1_fsel ) or + ( ex1_move ) or + ( ex1_from_integer ) or + ( ex1_est_recip ) or + ( ex1_est_rsqrt ) or + ( ex1_to_integer and not ex1_rnd_to_int); + + + + ex1_a_nan <= f_fmt_ex1_a_expo_max and not f_fmt_ex1_a_frac_zero and not ex1_uc_end_nspec and not ex1_uc_mid; + ex1_c_nan <= f_fmt_ex1_c_expo_max and not f_fmt_ex1_c_frac_zero and not ex1_uc_end_nspec and not ex1_uc_mid; + ex1_b_nan <= f_fmt_ex1_b_expo_max and not f_fmt_ex1_b_frac_zero and not ex1_uc_end_nspec and not ex1_uc_mid; + + ex1_a_inf <= f_fmt_ex1_a_expo_max and f_fmt_ex1_a_frac_zero and not ex1_uc_end_nspec and not ex1_uc_mid; + ex1_c_inf <= f_fmt_ex1_c_expo_max and f_fmt_ex1_c_frac_zero and not ex1_uc_end_nspec and not ex1_uc_mid; + ex1_b_inf <= f_fmt_ex1_b_expo_max and f_fmt_ex1_b_frac_zero and not ex1_uc_end_nspec and not ex1_uc_mid; + + ex1_bf_10000 <= ( f_fmt_ex1_b_imp and f_fmt_ex1_b_frac_zero ) or + ( f_fmt_ex1_b_imp and f_fmt_ex1_b_frac_z32 and ex1_word ); + + + f_pic_ex1_frsp_ue1 <= ex1_frsp and ex1_ue ; + + + ex1_sp <= not ex1_sp_b ; + + + ex2_ctl_lat: tri_rlmreg_p generic map (width=> 57, expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + forcee => forcee, + delay_lclkr => delay_lclkr(2), + mpw1_b => mpw1_b(2), + mpw2_b => mpw2_b(0), + nclk => nclk, + act => ex1_act, + thold_b => thold_0_b, + sg => sg_0, + scout => ex2_ctl_so , + scin => ex2_ctl_si , + din( 0) => ex1_fsel , + din( 1) => ex1_from_integer , + din( 2) => ex1_to_integer , + din( 3) => ex1_math , + din( 4) => ex1_est_recip , + din( 5) => ex1_est_rsqrt , + din( 6) => ex1_move , + din( 7) => ex1_compare , + din( 8) => ex1_prenorm , + din( 9) => ex1_frsp , + din(10) => ex1_mv_to_scr , + din(11) => ex1_mv_from_scr , + din(12) => ex1_div_beg , + din(13) => ex1_sqrt_beg , + din(14) => ex1_sp , + din(15) => ex1_word , + din(16) => ex1_ordered , + din(17) => ex1_sub_op , + din(18) => ex1_lzo_dis , + din(19) => ex1_rnd_dis , + din(20) => ex1_inv_sign , + din(21) => ex1_p_sign , + din(22) => ex1_b_sign_adj , + din(23) => ex1_b_sign_alt , + din(24) => ex1_a_sign , + din(25) => ex1_a_valid , + din(26) => ex1_c_valid , + din(27) => ex1_b_valid , + din(28) => f_fmt_ex1_prod_zero , + din(29) => ex1_rnd0 , + din(30) => ex1_rnd1 , + din(31) => ex1_rnd_to_int , + din(32) => ex1_ve , + din(33) => ex1_oe , + din(34) => ex1_ue , + din(35) => ex1_ze , + din(36) => ex1_xe , + din(37) => ex1_nonieee , + din(38) => ex1_rnd0 , + din(39) => ex1_rnd1 , + din(40) => ex1_sp_conv , + din(41) => ex1_uns , + din(42) => ex1_log2e , + din(43) => ex1_pow2e , + din(44) => ex1_ovf_unf_dis , + din(45) => ex1_rnd_fpscr(0) , + din(46) => ex1_rnd_fpscr(1) , + din(47) => ex1_div_sign , + din(48) => ex1_uc_ft_pos , + din(49) => ex1_uc_ft_neg , + din(50) => ex1_uc_mid , + din(51) => ex1_uc_end_spec , + din(52) => ex1_nj_deno , + din(53) => ex1_ftdiv , + din(54) => ex1_ftsqrt , + din(55) => tiup , + din(56) => f_fmt_ex1_b_imp , + dout( 0) => ex2_fsel , + dout( 1) => ex2_from_integer , + dout( 2) => ex2_to_integer , + dout( 3) => ex2_math , + dout( 4) => ex2_est_recip , + dout( 5) => ex2_est_rsqrt , + dout( 6) => ex2_move , + dout( 7) => ex2_compare , + dout( 8) => ex2_prenorm , + dout( 9) => ex2_frsp , + dout(10) => ex2_mv_to_scr , + dout(11) => ex2_mv_from_scr , + dout(12) => ex2_div_beg , + dout(13) => ex2_sqrt_beg , + dout(14) => ex2_sp , + dout(15) => ex2_word , + dout(16) => ex2_ordered , + dout(17) => ex2_sub_op , + dout(18) => ex2_lzo_dis , + dout(19) => ex2_rnd_dis , + dout(20) => ex2_inv_sign , + dout(21) => ex2_p_sign , + dout(22) => ex2_b_sign_adj , + dout(23) => ex2_b_sign_alt , + dout(24) => ex2_a_sign , + dout(25) => ex2_a_valid , + dout(26) => ex2_c_valid , + dout(27) => ex2_b_valid , + dout(28) => ex2_prod_zero , + dout(29) => ex2_op_rnd(0) , + dout(30) => ex2_op_rnd(1) , + dout(31) => ex2_rnd_to_int , + dout(32) => ex2_ve , + dout(33) => ex2_oe , + dout(34) => ex2_ue , + dout(35) => ex2_ze , + dout(36) => ex2_xe , + dout(37) => ex2_nonieee , + dout(38) => ex2_rnd0 , + dout(39) => ex2_rnd1 , + dout(40) => ex2_sp_conv , + dout(41) => ex2_uns , + dout(42) => ex2_log2e , + dout(43) => ex2_pow2e , + dout(44) => ex2_ovf_unf_dis , + dout(45) => ex2_rnd_fpscr(0) , + dout(46) => ex2_rnd_fpscr(1) , + dout(47) => ex2_div_sign , + dout(48) => ex2_uc_ft_pos , + dout(49) => ex2_uc_ft_neg , + dout(50) => ex2_uc_mid , + dout(51) => ex2_uc_end_spec , + dout(52) => ex2_nj_deno , + dout(53) => ex2_ftdiv , + dout(54) => ex2_ftsqrt , + dout(55) => ex2_accuracy , + dout(56) => ex2_b_imp ); + + + ex2_to_int_uns_neg <= ex2_to_integer and not ex2_rnd_to_int and ex2_uns and ex2_b_sign_alt; + ex2_wd_ov_x <= f_eie_ex2_wd_ov; + ex2_dw_ov_x <= f_eie_ex2_dw_ov; + + + f_pic_ex2_frsp_ue1 <= ex2_frsp and ex2_ue; + f_pic_ex2_b_valid <= ex2_b_valid; + f_pic_ex2_ue1 <= ex2_ue or ex2_ovf_unf_dis ; + + + ex1_sp_invalid <= ( f_fmt_ex1_sp_invalid and ex1_sp and not ex1_from_integer + and not ex1_uc_mid and not ex1_uc_end_nspec); + + + ex2_flg_lat: tri_rlmreg_p generic map (width=> 18, expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + forcee => forcee, + delay_lclkr => delay_lclkr(2), + mpw1_b => mpw1_b(2), + mpw2_b => mpw2_b(0), + nclk => nclk, + act => ex1_act, + thold_b => thold_0_b, + sg => sg_0, + scout => ex2_flg_so , + scin => ex2_flg_si , + din( 0) => f_fmt_ex1_a_frac_msb , + din( 1) => f_fmt_ex1_c_frac_msb , + din( 2) => f_fmt_ex1_b_frac_msb , + din( 3) => f_fmt_ex1_a_zero , + din( 4) => f_fmt_ex1_c_zero , + din( 5) => f_fmt_ex1_b_zero , + din( 6) => ex1_a_nan , + din( 7) => ex1_c_nan , + din( 8) => ex1_b_nan , + din( 9) => ex1_a_inf , + din(10) => ex1_b_inf , + din(11) => ex1_c_inf , + din(12) => ex1_sp_invalid , + din(13) => ex1_bf_10000 , + din(14) => f_fmt_ex1_bexpu_le126 , + din(15) => f_fmt_ex1_gt126 , + din(16) => f_fmt_ex1_ge128 , + din(17) => f_fmt_ex1_inf_and_beyond_sp , + dout( 0) => ex2_a_frac_msb , + dout( 1) => ex2_c_frac_msb , + dout( 2) => ex2_b_frac_msb , + dout( 3) => ex2_a_zero , + dout( 4) => ex2_c_zero , + dout( 5) => ex2_b_zero , + dout( 6) => ex2_a_nan , + dout( 7) => ex2_c_nan , + dout( 8) => ex2_b_nan , + dout( 9) => ex2_a_inf , + dout(10) => ex2_b_inf , + dout(11) => ex2_c_inf , + dout(12) => ex2_sp_invalid , + dout(13) => ex2_bf_10000 , + dout(14) => ex2_bexpu_le126 , + dout(15) => ex2_gt126 , + dout(16) => ex2_ge128 , + dout(17) => ex2_inf_and_beyond_sp ); + + + + + f_pic_ex2_sp_b <= not ex2_sp; + f_pic_ex2_to_integer <= ex2_to_integer and not ex2_rnd_to_int; + f_pic_ex2_prenorm <= ex2_prenorm ; + + + f_pic_ex2_force_sel_bexp <= + (ex2_from_integer ) or + (ex2_move ) or + (ex2_mv_to_scr ) or + (ex2_mv_from_scr ) or + (ex2_prenorm ) or + (ex2_est_recip ) or + (ex2_est_rsqrt ) ; + + f_pic_ex2_est_recip <= ex2_est_recip; + f_pic_ex2_est_rsqrt <= ex2_est_rsqrt; + + f_pic_ex2_sp_lzo <= + (ex2_frsp ) or + (ex2_math and ex2_sp ); + + f_pic_ex2_lzo_dis_prod <= + (ex2_math and ex2_ue ) or + (ex2_frsp and ex2_ue ) or + (ex2_lzo_dis ); + + f_pic_ex2_math_bzer_b <= not( ex2_math and ex2_b_zero ); + + + ex2_rnd_nr <= not ex2_rnd_dis and not ex2_rnd0 and not ex2_rnd1 ; + ex2_rnd_inf_ok <= not ex2_rnd_dis and ex2_rnd0 and not (ex2_rnd1 xor ex2_b_sign_alt) ; + + f_pic_ex2_rnd_nr <= ex2_rnd_nr ; + f_pic_ex2_rnd_inf_ok <= ex2_rnd_inf_ok ; + + + + ex2_a_snan <= ex2_a_nan and not ex2_a_frac_msb; + ex2_b_snan <= ex2_b_nan and not ex2_b_frac_msb; + ex2_c_snan <= ex2_c_nan and not ex2_c_frac_msb; + ex2_a_qnan <= ex2_a_nan and ex2_a_frac_msb; + ex2_b_qnan <= ex2_b_nan and ex2_b_frac_msb; + ex2_nan_op_grp1 <= ex2_math or ex2_est_recip or ex2_est_rsqrt or ex2_frsp or ex2_compare + or ex2_rnd_to_int or ex2_div_beg or ex2_sqrt_beg ; + ex2_nan_op_grp2 <= ex2_nan_op_grp1 or ex2_to_integer or ex2_div_beg; + ex2_compo <= ex2_compare and ex2_ordered ; + + ex2_pass_en <= (ex2_a_nan or ex2_c_nan or ex2_b_nan ); + ex2_pass_nan <= ex2_nan_op_grp1 and ex2_pass_en ; + + + ex2_vxsnan <= + (ex2_a_snan and ex2_nan_op_grp1 ) or + (ex2_c_snan and ex2_nan_op_grp1 ) or + (ex2_b_snan and ex2_nan_op_grp2 ) or + (f_dcd_ex2_uc_vxsnan ) ; + + ex2_vxvc <= + (ex2_compo and ex2_a_qnan and not ex2_b_snan ) or + (ex2_compo and ex2_b_qnan and not ex2_a_snan ) or + (ex2_compo and ex2_a_snan and not ex2_ve ) or + (ex2_compo and ex2_b_snan and not ex2_ve ) ; + + ex2_vxcvi <= + (ex2_to_integer and ex2_b_nan and not ex2_rnd_to_int) and not ex2_sp_invalid; + + ex2_vxzdz <= f_dcd_ex2_uc_vxzdz or + (ex2_a_zero and ex2_b_zero and ex2_div_beg and not ex2_sp_invalid) ; + + ex2_vxidi <= f_dcd_ex2_uc_vxidi or + (ex2_a_inf and ex2_b_inf and ex2_div_beg and not ex2_sp_invalid) ; + + + + + ex2_p_inf <= ex2_a_inf or ex2_c_inf; + ex2_p_zero <= ex2_a_zero or ex2_c_zero; + + + ex2_vximz <= + (ex2_math and ex2_p_inf and ex2_p_zero) and not ex2_sp_invalid; + + ex2_vxisi <= + (ex2_math and ex2_b_inf and ex2_p_inf and not ex2_p_zero and not f_alg_ex2_effsub_eac_b ) and not ex2_sp_invalid; + + ex2_vxsqrt <= f_dcd_ex2_uc_vxsqrt or + ( (ex2_est_rsqrt or ex2_sqrt_beg) and ex2_b_sign_alt and not ex2_b_zero and not ex2_b_nan and not ex2_sp_invalid) ; + + ex2_gen_nan_dv <= (ex2_a_zero and ex2_b_zero and ex2_div_beg ) or + ( (ex2_vxidi or ex2_sp_invalid) and ex2_div_beg ); + + ex2_gen_nan_sq <= (ex2_vxsqrt or ex2_sp_invalid) and ex2_sqrt_beg ; + + ex2_gen_nan <= (ex2_b_nan and ex2_to_integer and not ex2_rnd_to_int) or + ex2_gen_nan_log or + ex2_gen_nan_pow or + ex2_vxisi or + ex2_vximz or + (ex2_a_zero and ex2_b_zero and ex2_div_beg ) or + ex2_vxsqrt or + ex2_vxidi or + (ex2_sp_invalid and not ex2_pow2e and not ex2_log2e ) ; + + + + + + + ex2_log_ofzero <= (ex2_log2e and ex2_b_zero ) or + (ex2_log2e and ex2_bexpu_le126 ); + + ex2_gen_one <= (ex2_pow2e and ex2_b_zero) or + (ex2_pow2e and ex2_bexpu_le126 ); + + ex2_gen_nan_log <= ( ex2_log2e and ex2_b_sign_alt and not ex2_b_zero and not ex2_bexpu_le126 ) or + ( ex2_log2e and ex2_b_nan ); + + ex2_gen_inf_log <= ex2_log_ofzero or + (ex2_log2e and not ex2_b_sign_alt and ex2_b_inf ) or + (ex2_log2e and not ex2_b_sign_alt and ex2_inf_and_beyond_sp ) ; + + ex2_gen_inf_pow <= (ex2_pow2e and not ex2_b_sign_alt and ex2_b_inf ) or + (ex2_pow2e and not ex2_b_sign_alt and ex2_ge128 ); + + ex2_gen_zero_pow <= (ex2_pow2e and ex2_b_sign_alt and ex2_b_inf) or + (ex2_pow2e and ex2_b_sign_alt and ex2_gt126); + + ex2_gen_nan_pow <= ( ex2_pow2e and ex2_b_nan ) ; + + + ex2_zx <= f_dcd_ex2_uc_zx or + (ex2_b_zero and not ex2_a_zero + and not ex2_a_inf + and not ex2_a_nan + and not ex2_sp_invalid + and ( ex2_est_recip or ex2_est_rsqrt or ex2_div_beg ) ); + + ex2_gen_inf_sq <= ex2_sqrt_beg and ex2_b_inf and not ex2_b_sign_alt ; + ex2_gen_inf_dv <= (ex2_div_beg and ex2_a_inf and not ex2_b_inf and not ex2_b_nan ) or + (ex2_div_beg and ex2_zx and not ex2_a_inf and not ex2_a_nan ); + + ex2_gen_inf <= + (ex2_gen_inf_log ) or + (ex2_gen_inf_pow ) or + (ex2_to_integer and ex2_b_inf ) or + (ex2_zx ) or + (ex2_frsp and ex2_b_inf ) or + (ex2_math and ex2_any_inf ) or + (ex2_gen_inf_sq ) or + (ex2_gen_inf_dv ); + + ex2_inf_sign <= + ( ex2_p_inf and ex2_p_sign ) or + ( not ex2_p_inf and ex2_b_inf and ex2_b_sign_adj ); + + + ex2_any_inf <= ex2_a_inf or ex2_c_inf or ex2_b_inf ; + + + ex2_gen_max <= + (ex2_to_integer and ex2_b_inf and not ex2_rnd_to_int); + + + ex2_gen_zer_sq <= ex2_sqrt_beg and ex2_b_zero ; + ex2_gen_zer_dv <= ex2_div_beg and ex2_b_inf and not ex2_a_nan and not ex2_a_inf ; + + ex2_gen_zero <= + ( ex2_gen_zero_pow ) or + ( ex2_math and (ex2_a_zero or ex2_c_zero) and ex2_b_zero ) or + ( ex2_to_integer and ex2_b_zero ) or + ( ex2_from_integer and not ex2_b_sign_alt and ex2_b_zero ) or + ( ex2_frsp and ex2_b_zero ) or + ( ex2_prenorm and not ex2_div_beg and ex2_b_zero ) or + ( ex2_est_recip and ex2_b_inf ) or + ( ex2_est_rsqrt and not ex2_b_sign_alt and ex2_b_inf ) or + ( ex2_gen_zer_sq ) or + ( ex2_gen_zer_dv ); + + + ex2_neg_sqrt_nz <= + ( ex2_est_rsqrt and ex2_b_sign_alt and not ex2_b_zero) ; + + ex2_toint_genz <= ex2_to_integer and ex2_b_zero ; + + ex2_toint_nan_sign <= ex2_to_integer and not ex2_rnd_to_int and (ex2_pass_nan or ex2_gen_nan) and not ex2_uns; + + ex2_pass_x <= ex2_pass_nan or ex2_fsel ; + + ex2_rnd_ni <= ex2_rnd0 and ex2_rnd1 ; + ex2_exact_zero_sign <= + ( ex2_effsub_eac and (ex2_rnd_ni xor ex2_inv_sign) ) or + (not ex2_effsub_eac and (ex2_p_sign ) ); + + + ex2_prenorm_special <= ex2_gen_zer_dv or ex2_gen_inf_dv or ex2_gen_nan_dv or + ex2_gen_zer_sq or ex2_gen_inf_sq or ex2_gen_nan_sq ; + + ex2_prenorm_sign <= + (ex2_div_sign and ex2_gen_zer_dv ) or + (ex2_div_sign and ex2_gen_inf_dv ) or + (tidn and ex2_gen_inf_sq ) or + (tidn and ex2_gen_nan_sq ) or + (tidn and ex2_gen_nan_dv ) or + (ex2_b_sign_alt and ex2_gen_zer_sq ) or + (ex2_b_sign_alt and not ex2_prenorm_special ) ; + + ex2_spec_sign <= + ( ex2_pass_x and f_fmt_ex2_pass_sign ) or + ( not ex2_pass_x and ex2_prenorm and ex2_prenorm_sign and not ex2_gen_nan ) or + ( not ex2_pass_x and ex2_math and (ex2_a_zero or ex2_c_zero) and ex2_b_zero and ex2_exact_zero_sign and not ex2_inf_sign and not ex2_gen_nan) or + ( not ex2_pass_x and ex2_log_ofzero and not ex2_gen_nan ) or + ( not ex2_pass_x and not ex2_math and ex2_b_sign_alt and not ex2_neg_sqrt_nz + and not ex2_prenorm + and not ex2_log2e + and not ex2_pow2e + and not ex2_toint_genz and not ex2_gen_nan ) or + ( not ex2_pass_x and ex2_math and ex2_inf_sign and not ex2_gen_nan ) or + ( ex2_toint_nan_sign ) or + ( ex2_b_sign_alt and ex2_rnd_to_int and not ex2_gen_nan ) ; + + ex2_quiet <= + ex2_pass_nan and not f_fmt_ex2_pass_msb and (ex2_math or + ex2_frsp or + ex2_rnd_to_int or + ex2_est_recip or + ex2_est_rsqrt ); + + + + ex2_cmp_zero <= ex2_a_zero and ex2_b_zero; + + ex2_is_nan <= ( ex2_compare and ex2_pass_nan ) ; + + ex2_is_eq <= ( ex2_compare and not ex2_pass_nan and ex2_cmp_zero ) or + ( (ex2_ftsqrt or ex2_ftdiv) and ex2_b_zero ) or + ( (ex2_ftsqrt or ex2_ftdiv) and ex2_b_inf ) or + ( (ex2_ftsqrt or ex2_ftdiv) and ex2_b_nan ) or + ( ex2_ftdiv and ex2_a_inf ) or + ( ex2_ftdiv and ex2_a_nan ) or + ( ex2_ftsqrt and ex2_b_sign_alt ) or + ( ex2_ftsqrt and not f_fmt_ex2_be_ge_54 ) or + ( ex2_ftdiv and not f_fmt_ex2_ae_ge_54 and not ex2_a_zero ) or + ( ex2_ftdiv and not f_fmt_ex2_be_ge_2 ) or + ( ex2_ftdiv and f_fmt_ex2_be_ge_2044 ) or + ( ex2_ftdiv and f_fmt_ex2_tdiv_rng_chk and not ex2_a_zero ); + + ex2_is_gt <= ( ex2_compare and not ex2_pass_nan and not ex2_cmp_zero and not ex2_a_sign and not ex2_b_sign_alt ) or + ( (ex2_ftsqrt or ex2_ftdiv) and not ex2_b_imp ) or + ( (ex2_ftsqrt or ex2_ftdiv) and f_fmt_ex2_be_den ) or + ( (ex2_ftsqrt or ex2_ftdiv) and ex2_b_zero ) or + ( (ex2_ftsqrt or ex2_ftdiv) and ex2_b_inf ) or + ( ex2_ftdiv and ex2_a_inf ) ; + + + ex2_is_lt <= ( ex2_compare and not ex2_pass_nan and not ex2_cmp_zero and ex2_a_sign and ex2_b_sign_alt ) or + ( ex2_ftdiv and ex2_accuracy ) or + ( ex2_ftsqrt and ex2_accuracy ) ; + ex2_cmp_sgnneg <= ( ex2_compare and not ex2_pass_nan and not ex2_cmp_zero and ex2_a_sign and not ex2_b_sign_alt ) ; + ex2_cmp_sgnpos <= ( ex2_compare and not ex2_pass_nan and not ex2_cmp_zero and not ex2_a_sign and ex2_b_sign_alt ) ; + + + + + + ex3_scr_lat: tri_rlmreg_p generic map (width=> 8, expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + forcee => forcee, + delay_lclkr => delay_lclkr(3), + mpw1_b => mpw1_b(3), + mpw2_b => mpw2_b(0) , + nclk => nclk, + act => ex2_act, + thold_b => thold_0_b, + sg => sg_0, + scout => ex3_scr_so , + scin => ex3_scr_si , + din(0) => ex2_ve , + din(1) => ex2_oe , + din(2) => ex2_ue , + din(3) => ex2_ze , + din(4) => ex2_xe , + din(5) => ex2_nonieee , + din(6) => ex2_rnd0 , + din(7) => ex2_rnd1 , + dout(0) => ex3_ve , + dout(1) => ex3_oe , + dout(2) => ex3_ue , + dout(3) => ex3_ze , + dout(4) => ex3_xe , + dout(5) => ex3_nonieee , + dout(6) => ex3_rnd0 , + dout(7) => ex3_rnd1 ); + + + + ex2_sp_notrunc <= ex2_sp and not ( + ( ex2_div_beg and (ex2_a_nan or ex2_b_nan)) or + ( ex2_sqrt_beg and ex2_b_nan) ); + + + + ex2_sp_o_frsp <= ex2_sp_notrunc or ex2_frsp; + + + ex3_ctl_lat: tri_rlmreg_p generic map (width=> 34, expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + forcee => forcee, + delay_lclkr => delay_lclkr(3), + mpw1_b => mpw1_b(3), + mpw2_b => mpw2_b(0), + nclk => nclk, + act => ex2_act, + thold_b => thold_0_b, + sg => sg_0, + scout => ex3_ctl_so , + scin => ex3_ctl_si , + din( 0) => ex2_fsel , + din( 1) => ex2_from_integer , + din( 2) => ex2_to_integer , + din( 3) => ex2_math , + din( 4) => ex2_est_recip , + din( 5) => ex2_est_rsqrt , + din( 6) => ex2_move , + din( 7) => ex2_compare , + din( 8) => ex2_prenorm , + din( 9) => ex2_frsp , + din(10) => ex2_mv_to_scr , + din(11) => ex2_mv_from_scr , + din(12) => ex2_div_beg , + din(13) => ex2_sqrt_beg , + din(14) => ex2_sp_o_frsp , + din(15) => ex2_word , + din(16) => ex2_sub_op , + din(17) => ex2_rnd_dis , + din(18) => ex2_inv_sign , + din(19) => ex2_p_sign , + din(20) => ex2_b_sign_adj , + din(21) => ex2_b_sign_alt , + din(22) => ex2_a_valid , + din(23) => ex2_c_valid , + din(24) => ex2_b_valid , + din(25) => ex2_prod_zero , + din(26) => ex2_b_zero , + din(27) => ex2_rnd_to_int , + din(28) => ex2_sp_conv , + din(29) => ex2_uns , + din(30) => ex2_log2e , + din(31) => ex2_pow2e , + din(32) => ex2_ovf_unf_dis , + din(33) => ex2_nj_deno , + dout( 0) => ex3_fsel , + dout( 1) => ex3_from_integer , + dout( 2) => ex3_to_integer , + dout( 3) => ex3_math , + dout( 4) => ex3_est_recip , + dout( 5) => ex3_est_rsqrt , + dout( 6) => ex3_move , + dout( 7) => ex3_compare , + dout( 8) => ex3_prenorm , + dout( 9) => ex3_frsp , + dout(10) => ex3_mv_to_scr , + dout(11) => ex3_mv_from_scr , + dout(12) => ex3_div_beg , + dout(13) => ex3_sqrt_beg , + dout(14) => ex3_sp , + dout(15) => ex3_word , + dout(16) => ex3_sub_op , + dout(17) => ex3_rnd_dis , + dout(18) => ex3_inv_sign , + dout(19) => ex3_p_sign , + dout(20) => ex3_b_sign_adj , + dout(21) => ex3_b_sign_alt , + dout(22) => ex3_a_valid , + dout(23) => ex3_c_valid , + dout(24) => ex3_b_valid , + dout(25) => ex3_prod_zero , + dout(26) => ex3_b_zero , + dout(27) => ex3_rnd_to_int , + dout(28) => ex3_sp_conv , + dout(29) => ex3_uns , + dout(30) => ex3_log2e , + dout(31) => ex3_pow2e , + dout(32) => ex3_ovf_unf_dis , + dout(33) => ex3_nj_deno ); + + ex3_nj_deno_x <= ex3_nj_deno and not ex3_ue ; + + ex3_byp_prod_nz <= ( ex3_math and + not ex3_b_zero and + not ex3_prod_zero and + (ex3_a_valid or ex3_c_valid) and + ex3_sel_byp ); + + ex3_byp_prod_nz_sub <= ( ex3_math and + ex3_effsub_eac and + not ex3_b_zero and + not ex3_prod_zero and + (ex3_a_valid or ex3_c_valid) and + ex3_sel_byp ); + + + ex2_uc_g_ig <= (f_mad_ex2_uc_a_expo_den and not ex2_ue ) or + (f_mad_ex2_uc_a_expo_den_sp and not ex2_ue and ex2_sp ) ; + + ex2_effsub_eac <= not f_alg_ex2_effsub_eac_b ; + + ex3_flg_lat: tri_rlmreg_p generic map (width=> 47, expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + forcee => forcee, + delay_lclkr => delay_lclkr(3), + mpw1_b => mpw1_b(3) , + mpw2_b => mpw2_b(0), + nclk => nclk, + act => ex2_act, + thold_b => thold_0_b, + sg => sg_0, + scout => ex3_flg_so, + scin => ex3_flg_si , + din( 0) => ex2_vxsnan , + din( 1) => ex2_vxvc , + din( 2) => ex2_vxcvi , + din( 3) => ex2_vxzdz , + din( 4) => ex2_vxidi , + din( 5) => ex2_vximz , + din( 6) => ex2_vxisi , + din( 7) => ex2_vxsqrt , + din( 8) => ex2_zx , + din( 9) => ex2_gen_nan , + din(10) => ex2_gen_inf , + din(11) => ex2_gen_max , + din(12) => ex2_gen_zero , + din(13) => ex2_spec_sign , + din(14) => ex2_quiet , + din(15) => ex2_is_nan , + din(16) => ex2_is_eq , + din(17) => ex2_is_gt , + din(18) => ex2_is_lt , + din(19) => ex2_cmp_sgnneg , + din(20) => ex2_cmp_sgnpos , + din(21) => ex2_wd_ov_x , + din(22) => ex2_dw_ov_x , + din(23) => f_eie_ex2_wd_ov_if , + din(24) => f_eie_ex2_dw_ov_if , + din(25) => ex2_to_int_uns_neg , + din(26) => f_alg_ex2_sel_byp , + din(27) => ex2_effsub_eac , + din(28) => f_alg_ex2_sh_unf , + din(29) => f_alg_ex2_sh_ovf , + din(30) => ex2_pass_nan , + din(31) => ex2_bf_10000 , + din(32) => f_eie_ex2_lt_bias , + din(33) => f_eie_ex2_eq_bias_m1 , + din(34) => ex2_gen_one , + din(35) => ex2_rnd_fpscr(0) , + din(36) => ex2_rnd_fpscr(1) , + din(37) => ex2_div_sign , + din(38) => ex2_uc_ft_pos , + din(39) => ex2_uc_ft_neg , + din(40) => f_dcd_ex2_uc_inc_lsb , + din(41) => f_dcd_ex2_uc_guard , + din(42) => f_dcd_ex2_uc_sticky , + din(43) => f_dcd_ex2_uc_gs_v , + din(44) => ex2_uc_g_ig , + din(45) => ex2_uc_mid , + din(46) => ex2_uc_end_spec , + dout( 0) => ex3_vxsnan , + dout( 1) => ex3_vxvc , + dout( 2) => ex3_vxcvi , + dout( 3) => ex3_vxzdz , + dout( 4) => ex3_vxidi , + dout( 5) => ex3_vximz , + dout( 6) => ex3_vxisi , + dout( 7) => ex3_vxsqrt , + dout( 8) => ex3_zx , + dout( 9) => ex3_gen_nan , + dout(10) => ex3_gen_inf , + dout(11) => ex3_gen_max , + dout(12) => ex3_gen_zero , + dout(13) => ex3_spec_sign , + dout(14) => ex3_quiet , + dout(15) => ex3_is_nan , + dout(16) => ex3_is_eq , + dout(17) => ex3_is_gt , + dout(18) => ex3_is_lt , + dout(19) => ex3_cmp_sgnneg , + dout(20) => ex3_cmp_sgnpos , + dout(21) => ex3_wd_ov , + dout(22) => ex3_dw_ov , + dout(23) => ex3_wd_ov_if , + dout(24) => ex3_dw_ov_if , + dout(25) => ex3_to_int_uns_neg , + dout(26) => ex3_sel_byp , + dout(27) => ex3_effsub_eac , + dout(28) => ex3_sh_unf , + dout(29) => ex3_sh_ovf , + dout(30) => ex3_pass_nan , + dout(31) => ex3_bf_10000 , + dout(32) => ex3_lt_bias , + dout(33) => ex3_eq_bias_m1 , + dout(34) => ex3_gen_one , + dout(35) => ex3_rnd_fpscr(0) , + dout(36) => ex3_rnd_fpscr(1) , + dout(37) => ex3_div_sign , + dout(38) => ex3_uc_ft_pos , + dout(39) => ex3_uc_ft_neg , + dout(40) => ex3_uc_inc_lsb , + dout(41) => ex3_uc_guard , + dout(42) => ex3_uc_sticky , + dout(43) => ex3_uc_gs_v , + dout(44) => ex3_uc_g_ig , + dout(45) => ex3_uc_mid , + dout(46) => ex3_uc_end_spec ); + + + f_mad_ex3_uc_round_mode(0 to 1) <= ex3_rnd_fpscr(0 to 1); + f_mad_ex3_uc_res_sign <= ex3_div_sign ; + f_mad_ex3_uc_zx <= ex3_zx and not ex3_pass_nan ; + f_mad_ex3_uc_special <= ex3_pass_nan or + ex3_gen_nan or + ex3_gen_zero or + ex3_gen_inf ; + + f_mad_ex3_uc_vxidi <= ex3_vxidi ; + f_mad_ex3_uc_vxzdz <= ex3_vxzdz ; + f_mad_ex3_uc_vxsqrt <= ex3_vxsqrt ; + f_mad_ex3_uc_vxsnan <= ex3_vxsnan ; + + f_pic_ex3_cmp_sgnneg <= ex3_cmp_sgnneg; + f_pic_ex3_cmp_sgnpos <= ex3_cmp_sgnpos; + f_pic_ex3_is_eq <= ex3_is_eq ; + f_pic_ex3_is_gt <= ex3_is_gt ; + f_pic_ex3_is_lt <= ex3_is_lt ; + f_pic_ex3_is_nan <= ex3_is_nan ; + + f_pic_ex3_sel_est <= ex3_est_recip or ex3_est_rsqrt; + f_pic_ex3_sp_b <= not ex3_sp ; + + + + + + + ex3_gen_rnd2int <= ex3_rnd_to_int and ex3_lt_bias ; + ex3_gen_one_rnd2int <= ex3_gen_rnd2int and ex3_rnd2int_up ; + ex3_gen_zer_rnd2int <= ex3_gen_rnd2int and not ex3_rnd2int_up ; + + + ex3_rnd2int_up <= + (not ex3_rnd0 and not ex3_rnd1 and ex3_eq_bias_m1 and not ex3_b_zero ) or + ( ex3_rnd0 and not ex3_rnd1 and not ex3_b_sign_alt and not ex3_b_zero ) or + ( ex3_rnd0 and ex3_rnd1 and ex3_b_sign_alt and not ex3_b_zero ); + + + + + ex3_gen_nan_mutex <= ex3_gen_nan and not ex3_pass_nan ; + ex3_gen_inf_mutex <= ex3_gen_inf and not ex3_pass_nan and not ex3_gen_nan ; + ex3_gen_max_mutex <= ex3_gen_inf and not ex3_pass_nan and not ex3_gen_nan and not ex3_gen_inf; + ex3_gen_zer_mutex <= (ex3_gen_zero or ex3_gen_zer_rnd2int) and not ex3_pass_nan and not ex3_gen_nan and not ex3_gen_one_rnd2int; + ex3_gen_one_mutex <= (ex3_gen_one or ex3_gen_one_rnd2int) and not ex3_pass_nan and not ex3_gen_nan ; + + + + + + ex3_word_to <= ex3_word and ex3_to_integer; + ex3_to_int_wd <= ex3_to_integer and ex3_word and not ex3_rnd_to_int; + ex3_to_int_dw <= ex3_to_integer and not ex3_word and not ex3_rnd_to_int; + ex3_to_int_ov <= + ( ex3_to_int_wd and ex3_wd_ov ) or + ( ex3_to_int_dw and ex3_dw_ov ) or + ( ex3_to_int_wd and ex3_wd_ov_if and not ex3_b_sign_alt and not ex3_uns ) or + ( ex3_to_int_dw and ex3_dw_ov_if and not ex3_b_sign_alt and not ex3_uns ) or + ( ex3_to_int_wd and ex3_wd_ov_if and ex3_b_sign_alt and not(ex3_bf_10000 and not f_alg_ex3_int_fr) and not ex3_uns ) or + ( ex3_to_int_dw and ex3_dw_ov_if and ex3_b_sign_alt and not(ex3_bf_10000 and not f_alg_ex3_int_fr) and not ex3_uns ) ; + + ex3_to_int_ov_if <= ex3_to_integer and not ex3_b_sign_alt; + + + ex3_spec_sel_e <= + ex3_gen_rnd2int or + ex3_pass_nan or + ex3_gen_nan or + ex3_gen_inf or + ex3_gen_zero or + ex3_mv_from_scr ; + + ex3_spec_sel_f <= + (ex3_gen_rnd2int and not ex3_pass_nan) or + (ex3_gen_nan and not ex3_pass_nan) or + (ex3_gen_inf and not ex3_pass_nan) or + (ex3_gen_zero and not ex3_pass_nan) ; + + + ex3_ov_en <= (ex3_math or ex3_frsp or ex3_est_recip) and not ex3_ovf_unf_dis ; + ex3_uf_en <= ex3_ov_en ; + + ex3_oe_x <= ex3_oe and ex3_ov_en; + ex3_ue_x <= ex3_ue and ex3_uf_en; + + ex3_ovf_en_oe0 <= ex3_ov_en and not ex3_oe ; + ex3_ovf_en_oe1 <= ex3_ov_en and ex3_oe ; + ex3_unf_en_oe0 <= ex3_uf_en and not ex3_ue ; + ex3_unf_en_oe1 <= ex3_uf_en and ex3_ue ; + + + + ex3_spec_sign_sel <= ex3_spec_sel_e or + ex3_prenorm or + ex3_fsel or + ex3_mv_from_scr or + ex3_rnd_to_int or + ex3_log2e or + ex3_pow2e or + ex3_uc_ft_pos or + ex3_uc_ft_neg; + + ex3_p_sign_may <= ex3_math and ex3_effsub_eac ; + + ex3_spec_sign_x <= (ex3_spec_sign and not ex3_uc_ft_pos) or ex3_uc_ft_neg; + + + ex3_sign_pco <= + ( ex3_spec_sign_sel and ex3_spec_sign_x ) or + ( not ex3_spec_sign_sel and ex3_b_sign_alt and not ex3_p_sign_may ) or + ( not ex3_spec_sign_sel and ex3_p_sign and ex3_p_sign_may and not (ex3_prod_zero and ex3_math) ) or + ( not ex3_spec_sign_sel and ex3_b_sign_alt and ex3_p_sign_may and (ex3_prod_zero and ex3_math) ); + + ex3_sign_nco <= + ( ex3_spec_sign_sel and ex3_spec_sign_x ) or + ( not ex3_spec_sign_sel and ex3_b_sign_alt and not(ex3_b_zero and ex3_math) ) or + ( not ex3_spec_sign_sel and ex3_p_sign and (ex3_b_zero and ex3_math) ); + + + + + + ex4_scr_lat: tri_rlmreg_p generic map (width=> 8, expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + forcee => forcee, + delay_lclkr => delay_lclkr(4), + mpw1_b => mpw1_b(4) , + mpw2_b => mpw2_b(0) , + nclk => nclk, + act => ex3_act, + thold_b => thold_0_b, + sg => sg_0, + scout => ex4_scr_so , + scin => ex4_scr_si , + din(0) => ex3_ve , + din(1) => ex3_oe_x , + din(2) => ex3_ue_x , + din(3) => ex3_ze , + din(4) => ex3_xe , + din(5) => ex3_nonieee , + din(6) => ex3_rnd0 , + din(7) => ex3_rnd1 , + dout(0) => ex4_ve , + dout(1) => ex4_oe , + dout(2) => ex4_ue , + dout(3) => ex4_ze , + dout(4) => ex4_xe , + dout(5) => ex4_nonieee , + dout(6) => ex4_rnd0 , + dout(7) => ex4_rnd1 ); + + ex3_sp_x <= ex3_sp or ex3_sp_conv ; + + ex4_ctl_lat: tri_rlmreg_p generic map (width=> 29, expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + forcee => forcee, + delay_lclkr => delay_lclkr(4), + mpw1_b => mpw1_b(4) , + mpw2_b => mpw2_b(0) , + nclk => nclk, + act => ex3_act, + thold_b => thold_0_b, + sg => sg_0, + scout => ex4_ctl_so , + scin => ex4_ctl_si , + din( 0) => ex3_fsel , + din( 1) => ex3_from_integer , + din( 2) => ex3_to_integer , + din( 3) => ex3_math , + din( 4) => ex3_est_recip , + din( 5) => ex3_est_rsqrt , + din( 6) => ex3_move , + din( 7) => ex3_compare , + din( 8) => ex3_prenorm , + din( 9) => ex3_frsp , + din(10) => ex3_mv_to_scr , + din(11) => ex3_mv_from_scr , + din(12) => ex3_div_beg , + din(13) => ex3_sqrt_beg , + din(14) => ex3_sp_x , + din(15) => ex3_word_to , + din(16) => ex3_sub_op , + din(17) => ex3_rnd_dis , + din(18) => ex3_inv_sign , + din(19) => ex3_sign_pco , + din(20) => ex3_sign_nco , + din(21) => ex3_byp_prod_nz , + din(22) => ex3_effsub_eac , + din(23) => ex3_rnd_to_int , + din(24) => ex3_uns , + din(25) => ex3_log2e , + din(26) => ex3_pow2e , + din(27) => ex3_ovf_unf_dis , + din(28) => ex3_nj_deno_x , + dout( 0) => ex4_fsel , + dout( 1) => ex4_from_integer , + dout( 2) => ex4_to_integer , + dout( 3) => ex4_math , + dout( 4) => ex4_est_recip , + dout( 5) => ex4_est_rsqrt , + dout( 6) => ex4_move , + dout( 7) => ex4_compare , + dout( 8) => ex4_prenorm , + dout( 9) => ex4_frsp , + dout(10) => ex4_mv_to_scr , + dout(11) => ex4_mv_from_scr , + dout(12) => ex4_div_beg , + dout(13) => ex4_sqrt_beg , + dout(14) => ex4_sp , + dout(15) => ex4_word , + dout(16) => ex4_sub_op , + dout(17) => ex4_rnd_dis , + dout(18) => ex4_inv_sign , + dout(19) => ex4_sign_pco , + dout(20) => ex4_sign_nco , + dout(21) => ex4_byp_prod_nz , + dout(22) => ex4_effsub_eac , + dout(23) => ex4_rnd_to_int , + dout(24) => ex4_uns , + dout(25) => ex4_log2e , + dout(26) => ex4_pow2e , + dout(27) => ex4_ovf_unf_dis , + dout(28) => ex4_nj_deno ); + + + f_pic_ex4_byp_prod_nz <= ex4_byp_prod_nz ; + + + ex4_flg_lat: tri_rlmreg_p generic map (width=> 38, expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + forcee => forcee, + delay_lclkr => delay_lclkr(4), + mpw1_b => mpw1_b(4) , + mpw2_b => mpw2_b(0) , + nclk => nclk, + act => ex3_act, + thold_b => thold_0_b, + sg => sg_0, + scout => ex4_flg_so , + scin => ex4_flg_si , + din( 0) => ex3_vxsnan , + din( 1) => ex3_vxvc , + din( 2) => ex3_vxcvi , + din( 3) => ex3_vxzdz , + din( 4) => ex3_vxidi , + din( 5) => ex3_vximz , + din( 6) => ex3_vxisi , + din( 7) => ex3_vxsqrt , + din( 8) => ex3_zx , + din( 9) => ex3_gen_nan_mutex , + din(10) => ex3_gen_inf_mutex , + din(11) => ex3_gen_max_mutex , + din(12) => ex3_gen_zer_mutex , + din(13) => ex3_gen_one_mutex , + din(14) => ex3_quiet , + din(15) => ex3_to_int_wd , + din(16) => ex3_to_int_dw , + din(17) => ex3_to_int_ov , + din(18) => ex3_to_int_ov_if , + din(19) => ex3_to_int_uns_neg , + din(20) => ex3_spec_sel_e , + din(21) => ex3_spec_sel_f , + din(22) => ex3_ov_en , + din(23) => ex3_uf_en , + din(24) => ex3_ovf_en_oe0, + din(25) => ex3_ovf_en_oe1, + din(26) => ex3_unf_en_oe0, + din(27) => ex3_unf_en_oe1, + din(28) => ex3_pass_nan , + din(29) => f_alg_ex3_int_fr , + din(30) => f_alg_ex3_int_fi , + din(31) => ex3_uc_inc_lsb , + din(32) => ex3_uc_guard , + din(33) => ex3_uc_sticky , + din(34) => ex3_uc_gs_v , + din(35) => ex3_uc_g_ig , + din(36) => ex3_uc_mid , + din(37) => ex3_uc_end_spec , + dout( 0) => ex4_vxsnan , + dout( 1) => ex4_vxvc , + dout( 2) => ex4_vxcvi , + dout( 3) => ex4_vxzdz , + dout( 4) => ex4_vxidi , + dout( 5) => ex4_vximz , + dout( 6) => ex4_vxisi , + dout( 7) => ex4_vxsqrt , + dout( 8) => ex4_zx , + dout( 9) => ex4_gen_nan , + dout(10) => ex4_gen_inf , + dout(11) => ex4_gen_max , + dout(12) => ex4_gen_zero , + dout(13) => ex4_gen_one , + dout(14) => ex4_quiet , + dout(15) => ex4_to_int_wd , + dout(16) => ex4_to_int_dw , + dout(17) => ex4_to_int_ov , + dout(18) => ex4_to_int_ov_if , + dout(19) => ex4_to_int_uns_neg , + dout(20) => ex4_spec_sel_e , + dout(21) => ex4_spec_sel_f , + dout(22) => ex4_ov_en , + dout(23) => ex4_uf_en , + dout(24) => ex4_ovf_en_oe0 , + dout(25) => ex4_ovf_en_oe1 , + dout(26) => ex4_unf_en_oe0 , + dout(27) => ex4_unf_en_oe1 , + dout(28) => ex4_pass_nan , + dout(29) => ex4_int_fr , + dout(30) => ex4_int_fi , + dout(31) => ex4_uc_inc_lsb , + dout(32) => ex4_uc_guard , + dout(33) => ex4_uc_sticky , + dout(34) => ex4_uc_gs_v , + dout(35) => ex4_uc_g_ig , + dout(36) => ex4_uc_mid , + dout(37) => ex4_uc_end_spec ); + + + ex4_to_int_ov_all_x <= + ( ex4_to_int_ov ) or + ( f_add_ex4_to_int_ovf_wd(0) and ex4_to_int_wd and ex4_uns and not ex4_to_int_uns_neg ) or + ( f_add_ex4_to_int_ovf_dw(0) and ex4_to_int_dw and ex4_uns and not ex4_to_int_uns_neg ) or + ( f_add_ex4_to_int_ovf_wd(1) and ex4_to_int_wd and not ex4_uns and ex4_to_int_ov_if ) or + ( f_add_ex4_to_int_ovf_dw(1) and ex4_to_int_dw and not ex4_uns and ex4_to_int_ov_if ) ; + + ex4_to_int_ov_all <= + ex4_to_int_uns_neg or + ex4_to_int_ov_all_x ; + + + + ex4_vxcvi_ov <= ex4_vxcvi or + ex4_to_int_ov_all_x or + (ex4_to_int_uns_neg and not f_add_ex4_to_int_ovf_dw(0) and ex4_to_int_dw) or + (ex4_to_int_uns_neg and not f_add_ex4_to_int_ovf_dw(0) and ex4_to_int_wd) ; + + + ex4_fr_spec <= ( ex4_int_fr and ex4_to_integer and not ex4_rnd_to_int and not ex4_vxcvi_ov ); + ex4_fi_spec <= ( ex4_int_fi and ex4_to_integer and not ex4_rnd_to_int and not ex4_vxcvi_ov ); + + ex4_sel_est <= (ex4_est_recip or ex4_est_rsqrt) and + not (ex4_pass_nan ); + + f_pic_ex4_quiet_b <= not ex4_quiet ; + f_pic_ex4_sp_b <= not ex4_sp ; + f_pic_ex4_sel_est_b <= not ex4_sel_est ; + + f_pic_ex4_to_int_ov_all <= ex4_to_int_ov_all ; + + f_pic_ex4_to_integer_b <= not( ex4_to_integer and not ex4_rnd_to_int ) ; + f_pic_ex4_word_b <= not ex4_word ; + f_pic_ex4_uns_b <= not ex4_uns ; + + f_pic_ex4_spec_sel_k_e <= ex4_spec_sel_e ; + f_pic_ex4_spec_sel_k_f <= ex4_spec_sel_f ; + + f_pic_ex4_sel_fpscr_b <= not ex4_mv_from_scr ; + f_pic_ex4_spec_inf_b <= not ex4_gen_inf ; + + + f_pic_ex4_oe <= ex4_oe ; + f_pic_ex4_ue <= ex4_ue ; + f_pic_ex4_ov_en <= ex4_ov_en and not ex4_spec_sel_e ; + f_pic_ex4_uf_en <= ex4_uf_en and not ex4_spec_sel_e ; + f_pic_ex4_ovf_en_oe0_b <= not ex4_ovf_en_oe0 ; + f_pic_ex4_unf_en_ue0_b <= not ex4_unf_en_oe0 ; + + f_pic_ex4_ovf_en_oe1_b <= not( ex4_ovf_en_oe1 and not ex4_uc_mid ); + f_pic_ex4_unf_en_ue1_b <= not( ex4_unf_en_oe1 and not ex4_uc_mid ); + + + ex4_rnd_nr <= not ex4_rnd0 and not ex4_rnd1; + ex4_rnd_zr <= not ex4_rnd0 and ex4_rnd1; + ex4_rnd_pi <= ex4_rnd0 and not ex4_rnd1; + ex4_rnd_ni <= ex4_rnd0 and ex4_rnd1; + + ex4_rnd_en <= not ex4_rnd_dis and + not ex4_sel_spec_e and + ( ex4_math or ex4_frsp or ex4_from_integer); + ex4_rnd_inf_ok <= ( ex4_rnd_en and ex4_rnd_pi and not ex4_round_sign ) or + ( ex4_rnd_en and ex4_rnd_ni and ex4_round_sign ) ; + ex4_rnd_nr_ok <= ex4_rnd_en and ex4_rnd_nr ; + f_pic_ex4_rnd_inf_ok_b <= not ex4_rnd_inf_ok ; + f_pic_ex4_rnd_ni_b <= not ex4_rnd_ni ; + f_pic_ex4_rnd_nr_b <= not ex4_rnd_nr_ok ; + + + + ex4_uc_g_v <= ex4_uc_gs_v and not ex4_uc_g_ig ; + ex4_uc_s_v <= ex4_uc_gs_v ; + + f_pic_ex4_nj_deno <= ex4_nj_deno ; + f_pic_ex5_uc_inc_lsb <= ex5_uc_inc_lsb ; + f_pic_ex5_uc_guard <= ex5_uc_guard ; + f_pic_ex5_uc_sticky <= ex5_uc_sticky ; + f_pic_ex5_uc_g_v <= ex5_uc_g_v ; + f_pic_ex5_uc_s_v <= ex5_uc_s_v ; + + ex4_vx <= ex4_vxsnan or + ex4_vxisi or + ex4_vxidi or + ex4_vxzdz or + ex4_vximz or + ex4_vxvc or + ex4_vxsqrt or + ex4_vxcvi_ov ; + + ex4_upd_fpscr_ops <= + ( ex4_math and not ex4_uc_mid ) or + ex4_est_recip or + ex4_est_rsqrt or + ex4_to_integer or + ex4_from_integer or + ex4_frsp or + ex4_rnd_to_int or + ex4_compare ; + + + ex4_scr_upd_pipe <= ex4_upd_fpscr_ops and not ex4_ovf_unf_dis; + ex4_scr_upd_move <= ex4_mv_to_scr ; + + + ex4_fpr_wr_dis <= + (ex4_fprf_hold ) ; + + + + ex4_sel_spec_e <= + ex4_gen_one or + ex4_pass_nan or + ex4_gen_nan or + ex4_gen_inf or + ex4_gen_zero ; + + ex4_sel_spec_f <= + ex4_gen_one or + ex4_gen_nan or + ex4_gen_inf or + ex4_gen_zero ; + + ex4_sel_spec_fr <= + ex4_gen_one or + ex4_sel_spec_e or + ex4_est_recip or + ex4_est_rsqrt or + ex4_rnd_to_int ; + + + ex4_ox_pipe_v <= not ex4_sel_spec_e and not ex4_compare and not ex4_to_integer and not ex4_from_integer and not ex4_rnd_to_int and not ex4_uc_end_spec; + ex4_fr_pipe_v <= not ex4_sel_spec_fr and not ex4_compare and not ex4_to_integer and not ex4_rnd_to_int and not ex4_uc_end_spec; + + + ex4_fprf_pipe_v <= not ex4_sel_spec_e and not ex4_compare and not( ex4_to_integer and not ex4_rnd_to_int) and not ex4_fprf_hold; + + ex4_fprf_hold_ops <= ex4_to_integer or + ex4_frsp or + ex4_rnd_to_int or + (ex4_math and not ex4_uc_mid) or + (ex4_est_recip and not ex4_uc_mid) or + (ex4_est_rsqrt and not ex4_uc_mid) ; + + ex4_fprf_hold <= + (ex4_ve and ex4_vx and ex4_fprf_hold_ops ) or + (ex4_ze and ex4_zx and ex4_fprf_hold_ops ); + + + ex4_gen_inf_sign <= ex4_round_sign xor (ex4_inv_sign and not ex4_pass_nan and not ex4_gen_nan) ; + + + ex4_fprf_spec_x(0) <= + ex4_pass_nan or + ex4_gen_nan or + ( ex4_gen_zero and (ex4_math and ex4_effsub_eac) and (ex4_rnd_ni xor ex4_inv_sign) ) or + ( ex4_gen_zero and not(ex4_math and ex4_effsub_eac) and (ex4_round_sign xor ex4_inv_sign) ); + + ex4_fprf_spec_x(1) <= ( ex4_gen_inf and ex4_gen_inf_sign ) or + ( ex4_gen_one and ex4_round_sign ); + ex4_fprf_spec_x(2) <= ( ex4_gen_inf and not ex4_gen_inf_sign ) or + ( ex4_gen_one and not ex4_round_sign ); + ex4_fprf_spec_x(3) <= ex4_gen_zero ; + ex4_fprf_spec_x(4) <= ex4_pass_nan or ex4_gen_nan or ex4_gen_inf ; + + ex4_fprf_spec(0 to 4) <= + ( (tidn & f_add_ex4_fpcc_iu(0 to 3)) and (0 to 4 => ex4_compare ) ) or + ( ex4_fprf_spec_x(0 to 4) and not (0 to 4 => ex4_to_integer_ken ) and not (0 to 4 => ex4_compare or ex4_fprf_hold) ) ; + + + + ex4_may_ovf <= f_eov_ex4_may_ovf; + + ex4_k_max_fp <= + ( ex4_may_ovf and ex4_rnd_zr ) or + ( ex4_may_ovf and ex4_rnd_pi and ex4_round_sign ) or + ( ex4_may_ovf and ex4_rnd_ni and not ex4_round_sign ) ; + + + + ex4_gen_any <= ex4_gen_nan or + ex4_gen_inf or + ex4_gen_zero or + ex4_gen_one ; + + ex4_k_nan <= (ex4_gen_nan or ex4_pass_nan) and not ex4_to_integer_ken ; + + ex4_k_inf <= ( ex4_gen_inf and not ex4_to_integer_ken ) or + ( not ex4_gen_any and not ex4_to_integer_ken and ex4_may_ovf and not ex4_k_max_fp ); + + ex4_k_max <= ( ex4_gen_max and not ex4_to_integer_ken ) or + ( not ex4_gen_any and not ex4_to_integer_ken and ex4_may_ovf and ex4_k_max_fp ); + + ex4_k_zer <= ( ex4_gen_zero and not ex4_to_integer_ken ) or + (not ex4_gen_any and not ex4_to_integer_ken and not ex4_may_ovf ); + + ex4_k_one <= ex4_gen_one ; + + + ex4_to_integer_ken <= ex4_to_integer and not ex4_rnd_to_int ; + + + ex4_k_int_zer <= + (ex4_to_integer_ken and ex4_uns and ex4_gen_zero ) or + (ex4_to_integer_ken and ex4_uns and ex4_gen_nan ) or + (ex4_to_integer_ken and ex4_uns and ex4_sign_nco ) or + (ex4_to_integer_ken and not ex4_uns and ex4_gen_zero ) ; + + ex4_k_int_maxpos <= + ( ex4_to_integer_ken and ex4_uns and not ex4_gen_zero and not ex4_gen_nan and not ex4_sign_nco ) or + ( ex4_to_integer_ken and not ex4_uns and not ex4_gen_zero and not ex4_gen_nan and not ex4_sign_nco ); + + ex4_k_int_maxneg <= + ( ex4_to_integer_ken and not ex4_uns and not ex4_gen_zero and ex4_gen_nan ) or + ( ex4_to_integer_ken and not ex4_uns and not ex4_gen_zero and ex4_sign_nco ); + + + + + + + + ex4_en_exact_zero <= ex4_math and + ex4_effsub_eac and + not ex4_sel_spec_e ; + + ex4_invert_sign <= ex4_inv_sign and + not ex4_pass_nan and + not ex4_gen_nan and + not (ex4_gen_zero and ex4_effsub_eac) ; + + + ex4_sign_pco_x <= (not (ex4_gen_zero and ex4_math and ex4_effsub_eac) and ex4_sign_pco ) or + ( (ex4_gen_zero and ex4_math and ex4_effsub_eac) and (ex4_rnd_ni xor ex4_inv_sign) ); + ex4_sign_nco_x <= (not (ex4_gen_zero and ex4_math and ex4_effsub_eac) and ex4_sign_nco ) or + ( (ex4_gen_zero and ex4_math and ex4_effsub_eac) and (ex4_rnd_ni xor ex4_inv_sign) ); + + ex4_round_sign <= + ( f_add_ex4_sign_carry and ex4_sign_pco ) or + ( not f_add_ex4_sign_carry and ex4_sign_nco ); + + + ex4_to_int_k_sign <= + ( not ex4_word and not ex4_k_int_zer and ex4_uns and not ex4_sign_nco ) or + ( not ex4_word and not ex4_k_int_zer and not ex4_uns and ex4_sign_nco ) ; + + ex4_to_int_ov_all_gt <= ex4_to_int_ov_all or ex4_k_int_zer ; + + ex4_sign_pco_xx <= (ex4_sign_pco_x and not ex4_to_int_ov_all_gt ) or (ex4_to_int_k_sign and ex4_to_int_ov_all_gt) ; + ex4_sign_nco_xx <= (ex4_sign_nco_x and not ex4_to_int_ov_all_gt ) or (ex4_to_int_k_sign and ex4_to_int_ov_all_gt) ; + + + ex4_round_sign_x <= + ( f_add_ex4_sign_carry and ex4_sign_pco_xx ) or + ( not f_add_ex4_sign_carry and ex4_sign_nco_xx ); + + + + ex4_k_nan_x <= ( ex4_k_nan and not ex4_mv_from_scr ); + ex4_k_inf_x <= ( ex4_k_inf and not ex4_mv_from_scr ); + ex4_k_max_x <= ( ex4_k_max and not ex4_mv_from_scr ); + ex4_k_zer_x <= ( ex4_k_zer or ex4_mv_from_scr ); + ex4_k_one_x <= ( ex4_k_one and not ex4_mv_from_scr ); + + ex5_flg_lat: tri_rlmreg_p generic map (width=> 42, expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + forcee => forcee, + delay_lclkr => delay_lclkr(5), + mpw1_b => mpw1_b(5), + mpw2_b => mpw2_b(1), + nclk => nclk, + act => ex4_act, + thold_b => thold_0_b, + sg => sg_0, + scout => ex5_flg_so , + scin => ex5_flg_si , + din( 0) => ex4_zx , + din( 1) => ex4_vxsnan , + din( 2) => ex4_vxisi , + din( 3) => ex4_vxidi , + din( 4) => ex4_vxzdz , + din( 5) => ex4_vximz , + din( 6) => ex4_vxvc , + din( 7) => ex4_vxsqrt , + din( 8) => ex4_vxcvi_ov , + din( 9) => ex4_scr_upd_move , + din(10) => ex4_scr_upd_pipe , + din(11) => ex4_fpr_wr_dis , + din(12) => ex4_ox_pipe_v , + din(13) => ex4_fr_pipe_v , + din(14) => ex4_fprf_pipe_v , + din(15 to 19) => ex4_fprf_spec(0 to 4) , + din(20) => ex4_k_nan_x , + din(21) => ex4_k_inf_x , + din(22) => ex4_k_max_x , + din(23) => ex4_k_zer_x , + din(24) => ex4_k_one_x , + din(25) => ex4_k_int_maxpos , + din(26) => ex4_k_int_maxneg , + din(27) => ex4_k_int_zer , + din(28) => ex4_en_exact_zero , + din(29) => ex4_invert_sign , + + din(30) => ex4_round_sign_x , + + din(31) => tidn , + din(32) => ex4_compare , + din(33) => ex4_frsp , + din(34) => ex4_fr_spec , + din(35) => ex4_fi_spec , + din(36) => ex4_fprf_hold , + din(37) => ex4_uc_inc_lsb , + din(38) => ex4_uc_guard , + din(39) => ex4_uc_sticky , + din(40) => ex4_uc_g_v , + din(41) => ex4_uc_s_v , + dout( 0) => ex5_zx , + dout( 1) => ex5_vxsnan , + dout( 2) => ex5_vxisi , + dout( 3) => ex5_vxidi , + dout( 4) => ex5_vxzdz , + dout( 5) => ex5_vximz , + dout( 6) => ex5_vxvc , + dout( 7) => ex5_vxsqrt , + dout( 8) => ex5_vxcvi , + dout( 9) => ex5_scr_upd_move , + dout(10) => ex5_scr_upd_pipe , + dout(11) => ex5_fpr_wr_dis , + dout(12) => ex5_ox_pipe_v , + dout(13) => ex5_fr_pipe_v , + dout(14) => ex5_fprf_pipe_v , + dout(15 to 19) => ex5_fprf_spec(0 to 4) , + dout(20) => ex5_k_nan , + dout(21) => ex5_k_inf , + dout(22) => ex5_k_max , + dout(23) => ex5_k_zer , + dout(24) => ex5_k_one , + dout(25) => ex5_k_int_maxpos , + dout(26) => ex5_k_int_maxneg , + dout(27) => ex5_k_int_zer , + dout(28) => ex5_en_exact_zero , + dout(29) => ex5_invert_sign , + dout(30) => ex5_round_sign , + dout(31) => ex5_unused , + dout(32) => ex5_compare , + dout(33) => ex5_frsp , + dout(34) => ex5_fr_spec , + dout(35) => ex5_fi_spec , + dout(36) => ex5_fprf_hold , + dout(37) => ex5_uc_inc_lsb , + dout(38) => ex5_uc_guard , + dout(39) => ex5_uc_sticky , + dout(40) => ex5_uc_g_v , + dout(41) => ex5_uc_s_v ); + + + f_pic_ex5_frsp <= ex5_frsp ; + + + + f_pic_ex5_flag_zx_b <= not ex5_zx ; + f_pic_ex5_flag_vxsnan_b <= not ex5_vxsnan ; + f_pic_ex5_flag_vxisi_b <= not ex5_vxisi ; + f_pic_ex5_flag_vxidi_b <= not ex5_vxidi ; + f_pic_ex5_flag_vxzdz_b <= not ex5_vxzdz ; + f_pic_ex5_flag_vximz_b <= not ex5_vximz ; + f_pic_ex5_flag_vxvc_b <= not ex5_vxvc ; + f_pic_ex5_flag_vxsqrt_b <= not ex5_vxsqrt ; + f_pic_ex5_flag_vxcvi_b <= not ex5_vxcvi ; + + f_pic_ex5_scr_upd_move_b <= not ex5_scr_upd_move ; + f_pic_ex5_scr_upd_pipe_b <= not ex5_scr_upd_pipe ; + f_pic_ex5_fpr_wr_dis_b <= not ex5_fpr_wr_dis ; + f_pic_ex5_compare_b <= not ex5_compare ; + + f_pic_ex5_ox_pipe_v_b <= not ex5_ox_pipe_v; + f_pic_ex5_fr_pipe_v_b <= not ex5_fr_pipe_v; + f_pic_ex5_fprf_pipe_v_b <= not ex5_fprf_pipe_v; + + f_pic_ex5_fprf_spec_b(0 to 4) <= not ex5_fprf_spec(0 to 4); + + f_pic_ex5_k_nan <= ex5_k_nan ; + f_pic_ex5_k_inf <= ex5_k_inf ; + f_pic_ex5_k_max <= ex5_k_max ; + f_pic_ex5_k_zer <= ex5_k_zer ; + f_pic_ex5_k_one <= ex5_k_one ; + f_pic_ex5_k_int_maxpos <= ex5_k_int_maxpos ; + f_pic_ex5_k_int_maxneg <= ex5_k_int_maxneg ; + f_pic_ex5_k_int_zer <= ex5_k_int_zer ; + + f_pic_ex5_en_exact_zero <= ex5_en_exact_zero; + f_pic_ex5_invert_sign <= ex5_invert_sign; + f_pic_ex5_round_sign <= ex5_round_sign; + + + + f_pic_ex5_fi_pipe_v_b <= not ex5_fr_pipe_v ; + f_pic_ex5_ux_pipe_v_b <= not ex5_ox_pipe_v ; + f_pic_ex5_fprf_hold_b <= not ex5_fprf_hold ; + f_pic_ex5_fi_spec_b <= not ex5_fi_spec; + f_pic_ex5_fr_spec_b <= not ex5_fr_spec; + + + + + + + ex1_ctl_si (0 to 42) <= ex1_ctl_so (1 to 42) & f_pic_si ; + ex2_ctl_si (0 to 56) <= ex2_ctl_so (1 to 56) & ex1_ctl_so (0); + ex2_flg_si (0 to 17) <= ex2_flg_so (1 to 17) & ex2_ctl_so (0); + ex3_scr_si (0 to 7) <= ex3_scr_so (1 to 7) & ex2_flg_so (0); + ex3_ctl_si (0 to 33) <= ex3_ctl_so (1 to 33) & ex3_scr_so (0); + ex3_flg_si (0 to 46) <= ex3_flg_so (1 to 46) & ex3_ctl_so (0); + ex4_scr_si (0 to 7) <= ex4_scr_so (1 to 7) & ex3_flg_so (0); + ex4_ctl_si (0 to 28) <= ex4_ctl_so (1 to 28) & ex4_scr_so (0); + ex4_flg_si (0 to 37) <= ex4_flg_so (1 to 37) & ex4_ctl_so (0); + ex5_flg_si (0 to 41) <= ex5_flg_so (1 to 41) & ex4_flg_so (0); + act_si (0 to 20) <= act_so (1 to 20) & ex5_flg_so (0); + f_pic_so <= act_so (0) ; + + + + +end; + + + + + + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_rnd.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_rnd.vhdl new file mode 100644 index 0000000..bb7168f --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_rnd.vhdl @@ -0,0 +1,1175 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + +entity fuq_rnd is +generic( expand_type : integer := 2 ); +port( + vdd :inout power_logic; + gnd :inout power_logic; + clkoff_b :in std_ulogic; + act_dis :in std_ulogic; + flush :in std_ulogic; + delay_lclkr :in std_ulogic_vector(5 to 6); + mpw1_b :in std_ulogic_vector(5 to 6); + mpw2_b :in std_ulogic_vector(1 to 1); + sg_1 :in std_ulogic; + thold_1 :in std_ulogic; + fpu_enable :in std_ulogic; + nclk :in clk_logic; + + f_rnd_si :in std_ulogic ; + f_rnd_so :out std_ulogic ; + ex3_act_b :in std_ulogic ; + + f_nrm_ex5_res :in std_ulogic_vector(0 to 52) ; + f_nrm_ex5_int_lsbs :in std_ulogic_vector(1 to 12) ; + f_nrm_ex5_int_sign :in std_ulogic ; + f_nrm_ex5_nrm_sticky_dp :in std_ulogic ; + f_nrm_ex5_nrm_guard_dp :in std_ulogic ; + f_nrm_ex5_nrm_lsb_dp :in std_ulogic ; + f_nrm_ex5_nrm_sticky_sp :in std_ulogic ; + f_nrm_ex5_nrm_guard_sp :in std_ulogic ; + f_nrm_ex5_nrm_lsb_sp :in std_ulogic ; + f_nrm_ex5_exact_zero :in std_ulogic ; + f_tbl_ex5_recip_den :in std_ulogic ; + + f_pic_ex5_invert_sign :in std_ulogic ; + f_pic_ex5_en_exact_zero :in std_ulogic ; + + + f_pic_ex5_k_nan :in std_ulogic ; + f_pic_ex5_k_inf :in std_ulogic ; + f_pic_ex5_k_max :in std_ulogic ; + f_pic_ex5_k_zer :in std_ulogic ; + f_pic_ex5_k_one :in std_ulogic ; + f_pic_ex5_k_int_maxpos :in std_ulogic ; + f_pic_ex5_k_int_maxneg :in std_ulogic ; + f_pic_ex5_k_int_zer :in std_ulogic ; + + f_pic_ex4_sel_est_b :in std_ulogic ; + f_tbl_ex5_est_frac :in std_ulogic_vector(0 to 26) ; + + f_pic_ex4_rnd_ni_b :in std_ulogic ; + f_pic_ex4_rnd_nr_b :in std_ulogic ; + f_pic_ex4_rnd_inf_ok_b :in std_ulogic ; + f_pic_ex5_uc_inc_lsb :in std_ulogic ; + f_pic_ex5_uc_guard :in std_ulogic ; + f_pic_ex5_uc_sticky :in std_ulogic ; + f_pic_ex5_uc_g_v :in std_ulogic ; + f_pic_ex5_uc_s_v :in std_ulogic ; + + f_pic_ex4_sel_fpscr_b :in std_ulogic ; + f_pic_ex4_to_integer_b :in std_ulogic ; + f_pic_ex4_word_b :in std_ulogic ; + f_pic_ex4_uns_b :in std_ulogic ; + f_pic_ex4_sp_b :in std_ulogic ; + f_pic_ex4_spec_inf_b :in std_ulogic ; + f_pic_ex4_quiet_b :in std_ulogic ; + f_pic_ex4_nj_deno :in std_ulogic ; + f_pic_ex4_unf_en_ue0_b :in std_ulogic ; + f_pic_ex4_unf_en_ue1_b :in std_ulogic ; + f_pic_ex4_ovf_en_oe0_b :in std_ulogic ; + f_pic_ex4_ovf_en_oe1_b :in std_ulogic ; + f_pic_ex5_round_sign :in std_ulogic ; + f_scr_ex5_fpscr_rd_dat_dfp :in std_ulogic_vector(0 to 3) ; + f_scr_ex5_fpscr_rd_dat :in std_ulogic_vector(0 to 31) ; + + f_eov_ex5_sel_k_f :in std_ulogic ; + f_eov_ex5_sel_k_e :in std_ulogic ; + f_eov_ex5_sel_kif_f :in std_ulogic ; + f_eov_ex5_sel_kif_e :in std_ulogic ; + f_eov_ex5_ovf_expo :in std_ulogic ; + f_eov_ex5_ovf_if_expo :in std_ulogic ; + f_eov_ex5_unf_expo :in std_ulogic ; + f_eov_ex5_expo_p0 :in std_ulogic_vector(1 to 13) ; + f_eov_ex5_expo_p1 :in std_ulogic_vector(1 to 13) ; + f_eov_ex5_expo_p0_ue1oe1 :in std_ulogic_vector(3 to 7) ; + f_eov_ex5_expo_p1_ue1oe1 :in std_ulogic_vector(3 to 7) ; + f_pic_ex5_frsp :in std_ulogic ; + + f_gst_ex5_logexp_v :in std_ulogic; + f_gst_ex5_logexp_sign :in std_ulogic; + f_gst_ex5_logexp_exp :in std_ulogic_vector(1 to 11); + f_gst_ex5_logexp_fract :in std_ulogic_vector(0 to 19); + + f_rnd_ex6_res_sign :out std_ulogic ; + f_rnd_ex6_res_expo :out std_ulogic_vector(1 to 13) ; + f_rnd_ex6_res_frac :out std_ulogic_vector(0 to 52) ; + + f_rnd_ex6_flag_up :out std_ulogic ; + f_rnd_ex6_flag_fi :out std_ulogic ; + f_rnd_ex6_flag_ox :out std_ulogic ; + f_rnd_ex6_flag_den :out std_ulogic ; + f_rnd_ex6_flag_sgn :out std_ulogic ; + f_rnd_ex6_flag_inf :out std_ulogic ; + f_rnd_ex6_flag_zer :out std_ulogic ; + f_rnd_ex6_flag_ux :out std_ulogic ; + + f_mad_ex6_uc_sign :out std_ulogic ; + f_mad_ex6_uc_zero :out std_ulogic + +); + + + +end fuq_rnd; + + +architecture fuq_rnd of fuq_rnd is + + constant tiup :std_ulogic := '1'; + constant tidn :std_ulogic := '0'; + + signal sg_0 :std_ulogic ; + signal thold_0_b, thold_0, forcee :std_ulogic ; + signal ex4_act :std_ulogic ; + signal ex3_act :std_ulogic ; + signal ex5_act :std_ulogic ; + signal act_spare_unused :std_ulogic_vector(0 to 2) ; + signal flag_spare_unused :std_ulogic ; + signal act_so :std_ulogic_vector(0 to 4) ; + signal act_si :std_ulogic_vector(0 to 4) ; + signal ex5_ctl_so :std_ulogic_vector(0 to 15) ; + signal ex5_ctl_si :std_ulogic_vector(0 to 15) ; + signal ex6_frac_so :std_ulogic_vector(0 to 52) ; + signal ex6_frac_si :std_ulogic_vector(0 to 52) ; + signal ex6_expo_so :std_ulogic_vector(0 to 13) ; + signal ex6_expo_si :std_ulogic_vector(0 to 13) ; + signal ex6_flag_so :std_ulogic_vector(0 to 9) ; + signal ex6_flag_si :std_ulogic_vector(0 to 9) ; + signal ex5_quiet :std_ulogic ; + signal ex5_rnd_ni :std_ulogic ; + signal ex5_rnd_nr :std_ulogic ; + signal ex5_rnd_inf_ok :std_ulogic ; + signal ex5_rnd_frc_up :std_ulogic ; + signal ex5_sel_fpscr :std_ulogic ; + signal ex5_to_integer :std_ulogic ; + signal ex5_word :std_ulogic ; + signal ex5_sp :std_ulogic ; + signal ex5_spec_inf :std_ulogic ; + signal ex5_flag_den :std_ulogic ; + signal ex5_flag_inf :std_ulogic ; + signal ex5_flag_zer :std_ulogic ; + signal ex5_flag_ux :std_ulogic ; + signal ex5_flag_up :std_ulogic ; + signal ex5_flag_fi :std_ulogic ; + signal ex5_flag_ox :std_ulogic ; + signal ex5_all0_lo :std_ulogic ; + signal ex5_all0_sp :std_ulogic ; + signal ex5_all0 :std_ulogic ; + signal ex5_all1 :std_ulogic ; + signal ex5_frac_c :std_ulogic_vector(0 to 52) ; + signal ex5_frac_p1 :std_ulogic_vector(0 to 52) ; + signal ex5_frac_p0 :std_ulogic_vector(0 to 52) ; + signal ex5_frac_px :std_ulogic_vector(0 to 52) ; + signal ex5_frac_k :std_ulogic_vector(0 to 52) ; + signal ex5_frac_misc :std_ulogic_vector(0 to 52); + signal ex5_to_int_data :std_ulogic_vector(0 to 63); + signal ex5_to_int_imp :std_ulogic ; + signal ex5_p0_sel_dflt :std_ulogic ; + + signal ex5_up :std_ulogic ; + signal ex5_up_sp :std_ulogic ; + signal ex5_up_dp :std_ulogic ; + signal ex5_res_frac :std_ulogic_vector(0 to 52) ; + signal ex5_res_sign :std_ulogic ; + signal ex5_res_expo :std_ulogic_vector(1 to 13) ; + signal ex6_res_frac :std_ulogic_vector(0 to 52) ; + signal ex6_res_sign :std_ulogic ; + signal ex6_res_expo :std_ulogic_vector(1 to 13) ; + signal ex6_flag_sgn :std_ulogic ; + signal ex6_flag_den :std_ulogic ; + signal ex6_flag_inf :std_ulogic ; + signal ex6_flag_zer :std_ulogic ; + signal ex6_flag_ux :std_ulogic ; + signal ex6_flag_up :std_ulogic ; + signal ex6_flag_fi :std_ulogic ; + signal ex6_flag_ox :std_ulogic ; + + signal ex5_sel_up :std_ulogic ; + signal ex5_sel_up_b :std_ulogic ; + signal ex5_sel_up_dp :std_ulogic ; + signal ex5_sel_up_dp_b :std_ulogic ; + signal ex5_gox :std_ulogic ; + + signal ex5_sgn_result_fp :std_ulogic; + signal ex5_res_sign_prez :std_ulogic; + signal ex5_exact_sgn_rst :std_ulogic; + signal ex5_exact_sgn_set :std_ulogic; + signal ex5_res_sel_k_f :std_ulogic; + signal ex5_res_sel_p1_e :std_ulogic; + signal ex5_res_clip_e :std_ulogic; + signal ex5_expo_sel_k :std_ulogic; + signal ex5_expo_sel_k_both :std_ulogic; + signal ex5_expo_p0_sel_k :std_ulogic; + signal ex5_expo_p0_sel_int :std_ulogic; + signal ex5_expo_p0_sel_gst :std_ulogic; + signal ex5_expo_p0_sel_dflt :std_ulogic; + signal ex5_expo_p1_sel_k :std_ulogic; + signal ex5_expo_p1_sel_dflt :std_ulogic; + signal ex5_sel_p0_joke :std_ulogic; + signal ex5_sel_p1_joke :std_ulogic; + signal ex5_expo_k :std_ulogic_vector(1 to 13); + signal ex5_expo_p0k :std_ulogic_vector(1 to 13); + signal ex5_expo_p1k :std_ulogic_vector(1 to 13); + signal ex5_expo_p0kx :std_ulogic_vector(1 to 13); + signal ex5_expo_p1kx :std_ulogic_vector(1 to 13); + signal ex5_unf_en_ue0 :std_ulogic; + signal ex5_unf_en_ue1 :std_ulogic; + signal ex5_ovf_en_oe0 :std_ulogic; + signal ex5_ovf_en_oe1 :std_ulogic; + signal ex5_ov_oe0 :std_ulogic; + signal ex5_k_zero :std_ulogic; + signal ex5_sel_est :std_ulogic; + signal ex5_k_inf_nan_maxdp :std_ulogic; + signal ex5_k_inf_nan_max :std_ulogic; + signal ex5_k_inf_nan_zer :std_ulogic; + signal ex5_k_zer_sp :std_ulogic; + signal ex5_k_notzer :std_ulogic; + signal ex5_k_max_intmax_nan :std_ulogic; + signal ex5_k_max_intmax :std_ulogic; + signal ex5_k_max_intsgn :std_ulogic; + signal ex5_k_max_intmax_nsp :std_ulogic; + signal ex5_pwr4_spec_frsp :std_ulogic; + signal ex5_exact_zero_rnd :std_ulogic; + signal ex5_rnd_ni_adj :std_ulogic; + signal ex5_nrm_res_b :std_ulogic_vector(0 to 52); + signal ex5_all0_gp2 :std_ulogic_vector(0 to 27); + signal ex5_all0_gp4 :std_ulogic_vector(0 to 13); + signal ex5_all0_gp8 :std_ulogic_vector(0 to 6); + signal ex5_all0_gp16 :std_ulogic_vector(0 to 3); + + signal ex5_frac_c_gp2 :std_ulogic_vector(0 to 52); + signal ex5_frac_c_gp4 :std_ulogic_vector(0 to 52); + signal ex5_frac_c_gp8 :std_ulogic_vector(0 to 52); + signal ex5_frac_g16 :std_ulogic_vector(0 to 6); + signal ex5_frac_g32 :std_ulogic_vector(0 to 6); + signal ex5_frac_g :std_ulogic_vector(1 to 6); + signal ex4_quiet :std_ulogic; + signal ex4_rnd_ni :std_ulogic; + signal ex4_rnd_nr :std_ulogic; + signal ex4_rnd_inf_ok :std_ulogic; + signal ex4_sel_fpscr :std_ulogic; + signal ex4_to_integer :std_ulogic; + signal ex4_word :std_ulogic; + signal ex4_uns :std_ulogic; + signal ex5_uns :std_ulogic; + signal ex4_sp :std_ulogic; + signal ex4_spec_inf :std_ulogic; + signal ex4_nj_deno :std_ulogic; + signal ex4_unf_en_ue0 :std_ulogic; + signal ex4_unf_en_ue1 :std_ulogic; + signal ex4_ovf_en_oe0 :std_ulogic; + signal ex4_ovf_en_oe1 :std_ulogic; + signal ex4_sel_est :std_ulogic; + signal ex5_guard_dp, ex5_guard_sp, ex5_sticky_dp, ex5_sticky_sp :std_ulogic; + signal unused :std_ulogic; + signal ex5_nj_deno, ex6_nj_deno :std_ulogic; + signal ex5_clip_deno :std_ulogic; + signal ex5_est_log_pow :std_ulogic ; + + +begin + + + unused <= ex5_frac_c(0) or + f_nrm_ex5_int_lsbs(1) ; + + + + thold_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => thold_1, + q(0) => thold_0 ); + + sg_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => sg_1 , + q(0) => sg_0 ); + + + lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map ( + clkoff_b => clkoff_b, + thold => thold_0, + sg => sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => thold_0_b ); + + + + ex3_act <= not ex3_act_b ; + + act_lat: tri_rlmreg_p generic map (width=> 5, expand_type => expand_type, needs_sreset => 0) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(5) , + mpw1_b => mpw1_b(5) , + mpw2_b => mpw2_b(1) , + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => fpu_enable, + scout => act_so , + scin => act_si , + din(0) => act_spare_unused(0), + din(1) => act_spare_unused(1), + din(2) => ex3_act, + din(3) => ex4_act, + din(4) => act_spare_unused(2), + dout(0) => act_spare_unused(0), + dout(1) => act_spare_unused(1), + dout(2) => ex4_act, + dout(3) => ex5_act, + dout(4) => act_spare_unused(2) ); + + + + ex4_quiet <= not f_pic_ex4_quiet_b ; + ex4_rnd_ni <= not f_pic_ex4_rnd_ni_b ; + ex4_rnd_nr <= not f_pic_ex4_rnd_nr_b ; + ex4_rnd_inf_ok <= not f_pic_ex4_rnd_inf_ok_b ; + ex4_sel_fpscr <= not f_pic_ex4_sel_fpscr_b ; + ex4_to_integer <= not f_pic_ex4_to_integer_b ; + ex4_word <= not f_pic_ex4_word_b ; + ex4_uns <= not f_pic_ex4_uns_b ; + ex4_sp <= not f_pic_ex4_sp_b ; + ex4_spec_inf <= not f_pic_ex4_spec_inf_b ; + ex4_nj_deno <= f_pic_ex4_nj_deno ; + ex4_unf_en_ue0 <= not f_pic_ex4_unf_en_ue0_b ; + ex4_unf_en_ue1 <= not f_pic_ex4_unf_en_ue1_b ; + ex4_ovf_en_oe0 <= not f_pic_ex4_ovf_en_oe0_b ; + ex4_ovf_en_oe1 <= not f_pic_ex4_ovf_en_oe1_b ; + ex4_sel_est <= not f_pic_ex4_sel_est_b ; + + + ex5_ctl_lat: tri_rlmreg_p generic map (width=> 16, expand_type => expand_type, needs_sreset => 0) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(5) , + mpw1_b => mpw1_b(5) , + mpw2_b => mpw2_b(1) , + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => ex4_act, + scout => ex5_ctl_so , + scin => ex5_ctl_si , + din( 0) => ex4_quiet , + din( 1) => ex4_rnd_ni , + din( 2) => ex4_rnd_nr , + din( 3) => ex4_rnd_inf_ok , + din( 4) => ex4_sel_fpscr , + din( 5) => ex4_to_integer , + din( 6) => ex4_word , + din( 7) => ex4_sp , + din( 8) => ex4_spec_inf , + din( 9) => ex4_nj_deno , + din(10) => ex4_unf_en_ue0 , + din(11) => ex4_unf_en_ue1 , + din(12) => ex4_ovf_en_oe0 , + din(13) => ex4_ovf_en_oe1 , + din(14) => ex4_sel_est , + din(15) => ex4_uns , + dout( 0) => ex5_quiet , + dout( 1) => ex5_rnd_ni , + dout( 2) => ex5_rnd_nr , + dout( 3) => ex5_rnd_inf_ok , + dout( 4) => ex5_sel_fpscr , + dout( 5) => ex5_to_integer , + dout( 6) => ex5_word , + dout( 7) => ex5_sp , + dout( 8) => ex5_spec_inf , + dout( 9) => ex5_nj_deno , + dout(10) => ex5_unf_en_ue0 , + dout(11) => ex5_unf_en_ue1 , + dout(12) => ex5_ovf_en_oe0 , + dout(13) => ex5_ovf_en_oe1 , + dout(14) => ex5_sel_est , + dout(15) => ex5_uns ); + + ex5_rnd_frc_up <= f_pic_ex5_uc_inc_lsb ; + + + + + + ex5_guard_dp <= ( f_nrm_ex5_nrm_guard_dp and not f_pic_ex5_uc_g_v ) or + ( f_pic_ex5_uc_guard and f_pic_ex5_uc_g_v ) ; + + ex5_guard_sp <= ( f_nrm_ex5_nrm_guard_sp and not f_pic_ex5_uc_g_v ) or + ( f_pic_ex5_uc_guard and f_pic_ex5_uc_g_v ) ; + + ex5_sticky_dp <= ( f_nrm_ex5_nrm_sticky_dp ) or + ( f_pic_ex5_uc_sticky and f_pic_ex5_uc_s_v ) ; + + ex5_sticky_sp <= ( f_nrm_ex5_nrm_sticky_sp ) or + ( f_pic_ex5_uc_sticky and f_pic_ex5_uc_s_v ) ; + + + + ex5_up_sp <= + ( ex5_rnd_frc_up ) or + ( ex5_rnd_nr and ex5_guard_sp and ex5_sticky_sp ) or + ( ex5_rnd_nr and ex5_guard_sp and f_nrm_ex5_nrm_lsb_sp ) or + ( ex5_rnd_inf_ok and ex5_guard_sp ) or + ( ex5_rnd_inf_ok and ex5_sticky_sp ) ; + + ex5_up_dp <= + ( ex5_rnd_frc_up ) or + ( ex5_rnd_nr and ex5_guard_dp and ex5_sticky_dp ) or + ( ex5_rnd_nr and ex5_guard_dp and f_nrm_ex5_nrm_lsb_dp ) or + ( ex5_rnd_inf_ok and ex5_guard_dp ) or + ( ex5_rnd_inf_ok and ex5_sticky_dp ) ; + + ex5_up <= + (ex5_up_sp and ex5_sp) or + (ex5_up_dp and not ex5_sp); + + ex5_sel_up <= ex5_up; + ex5_sel_up_b <= not ex5_up; + ex5_sel_up_dp <= ex5_up_dp and not ex5_sp; + ex5_sel_up_dp_b <= not ex5_up_dp and not ex5_sp; + + ex5_gox <= + ( ex5_sp and ex5_guard_sp ) or + ( ex5_sp and ex5_sticky_sp ) or + (not ex5_sp and ex5_guard_dp ) or + (not ex5_sp and ex5_sticky_dp ) ; + + + ex5_nrm_res_b(0 to 52) <= not f_nrm_ex5_res(0 to 52); + + ex5_all0_gp2( 0) <= ex5_nrm_res_b( 0) and ex5_nrm_res_b( 1); + ex5_all0_gp2( 1) <= ex5_nrm_res_b( 2) and ex5_nrm_res_b( 3); + ex5_all0_gp2( 2) <= ex5_nrm_res_b( 4) and ex5_nrm_res_b( 5); + ex5_all0_gp2( 3) <= ex5_nrm_res_b( 6) and ex5_nrm_res_b( 7); + ex5_all0_gp2( 4) <= ex5_nrm_res_b( 8) and ex5_nrm_res_b( 9); + ex5_all0_gp2( 5) <= ex5_nrm_res_b(10) and ex5_nrm_res_b(11); + ex5_all0_gp2( 6) <= ex5_nrm_res_b(12) and ex5_nrm_res_b(13); + ex5_all0_gp2( 7) <= ex5_nrm_res_b(14) and ex5_nrm_res_b(15); + ex5_all0_gp2( 8) <= ex5_nrm_res_b(16) and ex5_nrm_res_b(17); + ex5_all0_gp2( 9) <= ex5_nrm_res_b(18) and ex5_nrm_res_b(19); + ex5_all0_gp2(10) <= ex5_nrm_res_b(20) and ex5_nrm_res_b(21); + ex5_all0_gp2(11) <= ex5_nrm_res_b(22) and ex5_nrm_res_b(23); + ex5_all0_gp2(12) <= ex5_nrm_res_b(24) and ex5_nrm_res_b(25); + ex5_all0_gp2(13) <= ex5_nrm_res_b(26) and ex5_nrm_res_b(27); + ex5_all0_gp2(14) <= ex5_nrm_res_b(28) and ex5_nrm_res_b(29); + ex5_all0_gp2(15) <= ex5_nrm_res_b(30) and ex5_nrm_res_b(31); + ex5_all0_gp2(16) <= ex5_nrm_res_b(32) and ex5_nrm_res_b(33); + ex5_all0_gp2(17) <= ex5_nrm_res_b(34) and ex5_nrm_res_b(35); + ex5_all0_gp2(18) <= ex5_nrm_res_b(36) and ex5_nrm_res_b(37); + ex5_all0_gp2(19) <= ex5_nrm_res_b(38) and ex5_nrm_res_b(39); + ex5_all0_gp2(20) <= ex5_nrm_res_b(40) and ex5_nrm_res_b(41); + ex5_all0_gp2(21) <= ex5_nrm_res_b(40) and ex5_nrm_res_b(41); + ex5_all0_gp2(22) <= ex5_nrm_res_b(42) and ex5_nrm_res_b(43); + ex5_all0_gp2(23) <= ex5_nrm_res_b(44) and ex5_nrm_res_b(45); + ex5_all0_gp2(24) <= ex5_nrm_res_b(46) and ex5_nrm_res_b(47); + ex5_all0_gp2(25) <= ex5_nrm_res_b(48) and ex5_nrm_res_b(49); + ex5_all0_gp2(26) <= ex5_nrm_res_b(50) and ex5_nrm_res_b(51); + ex5_all0_gp2(27) <= ex5_nrm_res_b(52) ; + + ex5_all0_gp4( 0) <= ex5_all0_gp2( 0) and ex5_all0_gp2( 1); + ex5_all0_gp4( 1) <= ex5_all0_gp2( 2) and ex5_all0_gp2( 3); + ex5_all0_gp4( 2) <= ex5_all0_gp2( 4) and ex5_all0_gp2( 5); + ex5_all0_gp4( 3) <= ex5_all0_gp2( 6) and ex5_all0_gp2( 7); + ex5_all0_gp4( 4) <= ex5_all0_gp2( 8) and ex5_all0_gp2( 9); + ex5_all0_gp4( 5) <= ex5_all0_gp2(10) and ex5_all0_gp2(11); + ex5_all0_gp4( 6) <= ex5_all0_gp2(12) and ex5_all0_gp2(13); + ex5_all0_gp4( 7) <= ex5_all0_gp2(14) and ex5_all0_gp2(15); + ex5_all0_gp4( 8) <= ex5_all0_gp2(16) and ex5_all0_gp2(17); + ex5_all0_gp4( 9) <= ex5_all0_gp2(18) and ex5_all0_gp2(19); + ex5_all0_gp4(10) <= ex5_all0_gp2(20) and ex5_all0_gp2(21); + ex5_all0_gp4(11) <= ex5_all0_gp2(22) and ex5_all0_gp2(23); + ex5_all0_gp4(12) <= ex5_all0_gp2(24) and ex5_all0_gp2(25); + ex5_all0_gp4(13) <= ex5_all0_gp2(26) and ex5_all0_gp2(27); + + ex5_all0_gp8( 0) <= ex5_all0_gp4( 0) and ex5_all0_gp4( 1); + ex5_all0_gp8( 1) <= ex5_all0_gp4( 2) and ex5_all0_gp4( 3); + ex5_all0_gp8( 2) <= ex5_all0_gp4( 4) and ex5_all0_gp4( 5); + ex5_all0_gp8( 3) <= ex5_all0_gp4( 6) and ex5_all0_gp4( 7); + ex5_all0_gp8( 4) <= ex5_all0_gp4( 8) and ex5_all0_gp4( 9); + ex5_all0_gp8( 5) <= ex5_all0_gp4(10) and ex5_all0_gp4(11); + ex5_all0_gp8( 6) <= ex5_all0_gp4(12) and ex5_all0_gp4(13); + + + ex5_all0_gp16( 0) <= ex5_all0_gp8( 0) and ex5_all0_gp8( 1); + ex5_all0_gp16( 1) <= ex5_all0_gp8( 2) ; + ex5_all0_gp16( 2) <= ex5_all0_gp8( 3) and ex5_all0_gp8( 4); + ex5_all0_gp16( 3) <= ex5_all0_gp8( 5) and ex5_all0_gp8( 6); + + ex5_all0_sp <= ex5_all0_gp16( 0) and ex5_all0_gp16( 1); + ex5_all0_lo <= ex5_all0_gp16( 2) and ex5_all0_gp16( 3); + + + ex5_all0 <= ex5_all0_sp and (ex5_sp or ex5_all0_lo ); + + + + + ex5_frac_c_gp2( 0) <= f_nrm_ex5_res( 0) and f_nrm_ex5_res( 1); + ex5_frac_c_gp2( 1) <= f_nrm_ex5_res( 1) and f_nrm_ex5_res( 2); + ex5_frac_c_gp2( 2) <= f_nrm_ex5_res( 2) and f_nrm_ex5_res( 3); + ex5_frac_c_gp2( 3) <= f_nrm_ex5_res( 3) and f_nrm_ex5_res( 4); + ex5_frac_c_gp2( 4) <= f_nrm_ex5_res( 4) and f_nrm_ex5_res( 5); + ex5_frac_c_gp2( 5) <= f_nrm_ex5_res( 5) and f_nrm_ex5_res( 6); + ex5_frac_c_gp2( 6) <= f_nrm_ex5_res( 6) and f_nrm_ex5_res( 7); + ex5_frac_c_gp2( 7) <= f_nrm_ex5_res( 7) ; + ex5_frac_c_gp2( 8) <= f_nrm_ex5_res( 8) and f_nrm_ex5_res( 9); + ex5_frac_c_gp2( 9) <= f_nrm_ex5_res( 9) and f_nrm_ex5_res(10); + ex5_frac_c_gp2(10) <= f_nrm_ex5_res(10) and f_nrm_ex5_res(11); + ex5_frac_c_gp2(11) <= f_nrm_ex5_res(11) and f_nrm_ex5_res(12); + ex5_frac_c_gp2(12) <= f_nrm_ex5_res(12) and f_nrm_ex5_res(13); + ex5_frac_c_gp2(13) <= f_nrm_ex5_res(13) and f_nrm_ex5_res(14); + ex5_frac_c_gp2(14) <= f_nrm_ex5_res(14) and f_nrm_ex5_res(15); + ex5_frac_c_gp2(15) <= f_nrm_ex5_res(15) ; + ex5_frac_c_gp2(16) <= f_nrm_ex5_res(16) and f_nrm_ex5_res(17); + ex5_frac_c_gp2(17) <= f_nrm_ex5_res(17) and f_nrm_ex5_res(18); + ex5_frac_c_gp2(18) <= f_nrm_ex5_res(18) and f_nrm_ex5_res(19); + ex5_frac_c_gp2(19) <= f_nrm_ex5_res(19) and f_nrm_ex5_res(20); + ex5_frac_c_gp2(20) <= f_nrm_ex5_res(20) and f_nrm_ex5_res(21); + ex5_frac_c_gp2(21) <= f_nrm_ex5_res(21) and f_nrm_ex5_res(22); + ex5_frac_c_gp2(22) <= f_nrm_ex5_res(22) and f_nrm_ex5_res(23); + ex5_frac_c_gp2(23) <= f_nrm_ex5_res(23) ; + ex5_frac_c_gp2(24) <= f_nrm_ex5_res(24) and f_nrm_ex5_res(25); + ex5_frac_c_gp2(25) <= f_nrm_ex5_res(25) and f_nrm_ex5_res(26); + ex5_frac_c_gp2(26) <= f_nrm_ex5_res(26) and f_nrm_ex5_res(27); + ex5_frac_c_gp2(27) <= f_nrm_ex5_res(27) and f_nrm_ex5_res(28); + ex5_frac_c_gp2(28) <= f_nrm_ex5_res(28) and f_nrm_ex5_res(29); + ex5_frac_c_gp2(29) <= f_nrm_ex5_res(29) and f_nrm_ex5_res(30); + ex5_frac_c_gp2(30) <= f_nrm_ex5_res(30) and f_nrm_ex5_res(31); + ex5_frac_c_gp2(31) <= f_nrm_ex5_res(31) ; + ex5_frac_c_gp2(32) <= f_nrm_ex5_res(32) and f_nrm_ex5_res(33); + ex5_frac_c_gp2(33) <= f_nrm_ex5_res(33) and f_nrm_ex5_res(34); + ex5_frac_c_gp2(34) <= f_nrm_ex5_res(34) and f_nrm_ex5_res(35); + ex5_frac_c_gp2(35) <= f_nrm_ex5_res(35) and f_nrm_ex5_res(36); + ex5_frac_c_gp2(36) <= f_nrm_ex5_res(36) and f_nrm_ex5_res(37); + ex5_frac_c_gp2(37) <= f_nrm_ex5_res(37) and f_nrm_ex5_res(38); + ex5_frac_c_gp2(38) <= f_nrm_ex5_res(38) and f_nrm_ex5_res(39); + ex5_frac_c_gp2(39) <= f_nrm_ex5_res(39) ; + ex5_frac_c_gp2(40) <= f_nrm_ex5_res(40) and f_nrm_ex5_res(41); + ex5_frac_c_gp2(41) <= f_nrm_ex5_res(41) and f_nrm_ex5_res(42); + ex5_frac_c_gp2(42) <= f_nrm_ex5_res(42) and f_nrm_ex5_res(43); + ex5_frac_c_gp2(43) <= f_nrm_ex5_res(43) and f_nrm_ex5_res(44); + ex5_frac_c_gp2(44) <= f_nrm_ex5_res(44) and f_nrm_ex5_res(45); + ex5_frac_c_gp2(45) <= f_nrm_ex5_res(45) and f_nrm_ex5_res(46); + ex5_frac_c_gp2(46) <= f_nrm_ex5_res(46) and f_nrm_ex5_res(47); + ex5_frac_c_gp2(47) <= f_nrm_ex5_res(47) ; + ex5_frac_c_gp2(48) <= f_nrm_ex5_res(48) and f_nrm_ex5_res(49); + ex5_frac_c_gp2(49) <= f_nrm_ex5_res(49) and f_nrm_ex5_res(50); + ex5_frac_c_gp2(50) <= f_nrm_ex5_res(50) and f_nrm_ex5_res(51); + ex5_frac_c_gp2(51) <= f_nrm_ex5_res(51) and f_nrm_ex5_res(52); + ex5_frac_c_gp2(52) <= f_nrm_ex5_res(52) ; + + ex5_frac_c_gp4( 0) <= ex5_frac_c_gp2( 0) and ex5_frac_c_gp2( 2); + ex5_frac_c_gp4( 1) <= ex5_frac_c_gp2( 1) and ex5_frac_c_gp2( 3); + ex5_frac_c_gp4( 2) <= ex5_frac_c_gp2( 2) and ex5_frac_c_gp2( 4); + ex5_frac_c_gp4( 3) <= ex5_frac_c_gp2( 3) and ex5_frac_c_gp2( 5); + ex5_frac_c_gp4( 4) <= ex5_frac_c_gp2( 4) and ex5_frac_c_gp2( 6); + ex5_frac_c_gp4( 5) <= ex5_frac_c_gp2( 5) and ex5_frac_c_gp2( 7); + ex5_frac_c_gp4( 6) <= ex5_frac_c_gp2( 6) ; + ex5_frac_c_gp4( 7) <= ex5_frac_c_gp2( 7) ; + ex5_frac_c_gp4( 8) <= ex5_frac_c_gp2( 8) and ex5_frac_c_gp2(10); + ex5_frac_c_gp4( 9) <= ex5_frac_c_gp2( 9) and ex5_frac_c_gp2(11); + ex5_frac_c_gp4(10) <= ex5_frac_c_gp2(10) and ex5_frac_c_gp2(12); + ex5_frac_c_gp4(11) <= ex5_frac_c_gp2(11) and ex5_frac_c_gp2(13); + ex5_frac_c_gp4(12) <= ex5_frac_c_gp2(12) and ex5_frac_c_gp2(14); + ex5_frac_c_gp4(13) <= ex5_frac_c_gp2(13) and ex5_frac_c_gp2(15); + ex5_frac_c_gp4(14) <= ex5_frac_c_gp2(14) ; + ex5_frac_c_gp4(15) <= ex5_frac_c_gp2(15) ; + ex5_frac_c_gp4(16) <= ex5_frac_c_gp2(16) and ex5_frac_c_gp2(18); + ex5_frac_c_gp4(17) <= ex5_frac_c_gp2(17) and ex5_frac_c_gp2(19); + ex5_frac_c_gp4(18) <= ex5_frac_c_gp2(18) and ex5_frac_c_gp2(20); + ex5_frac_c_gp4(19) <= ex5_frac_c_gp2(19) and ex5_frac_c_gp2(21); + ex5_frac_c_gp4(20) <= ex5_frac_c_gp2(20) and ex5_frac_c_gp2(22); + ex5_frac_c_gp4(21) <= ex5_frac_c_gp2(21) and ex5_frac_c_gp2(23); + ex5_frac_c_gp4(22) <= ex5_frac_c_gp2(22) ; + ex5_frac_c_gp4(23) <= ex5_frac_c_gp2(23) ; + ex5_frac_c_gp4(24) <= ex5_frac_c_gp2(24) and ex5_frac_c_gp2(26); + ex5_frac_c_gp4(25) <= ex5_frac_c_gp2(25) and ex5_frac_c_gp2(27); + ex5_frac_c_gp4(26) <= ex5_frac_c_gp2(26) and ex5_frac_c_gp2(28); + ex5_frac_c_gp4(27) <= ex5_frac_c_gp2(27) and ex5_frac_c_gp2(29); + ex5_frac_c_gp4(28) <= ex5_frac_c_gp2(28) and ex5_frac_c_gp2(30); + ex5_frac_c_gp4(29) <= ex5_frac_c_gp2(29) and ex5_frac_c_gp2(31); + ex5_frac_c_gp4(30) <= ex5_frac_c_gp2(30) ; + ex5_frac_c_gp4(31) <= ex5_frac_c_gp2(31) ; + ex5_frac_c_gp4(32) <= ex5_frac_c_gp2(32) and ex5_frac_c_gp2(34); + ex5_frac_c_gp4(33) <= ex5_frac_c_gp2(33) and ex5_frac_c_gp2(35); + ex5_frac_c_gp4(34) <= ex5_frac_c_gp2(34) and ex5_frac_c_gp2(36); + ex5_frac_c_gp4(35) <= ex5_frac_c_gp2(35) and ex5_frac_c_gp2(37); + ex5_frac_c_gp4(36) <= ex5_frac_c_gp2(36) and ex5_frac_c_gp2(38); + ex5_frac_c_gp4(37) <= ex5_frac_c_gp2(37) and ex5_frac_c_gp2(39); + ex5_frac_c_gp4(38) <= ex5_frac_c_gp2(38) ; + ex5_frac_c_gp4(39) <= ex5_frac_c_gp2(39) ; + ex5_frac_c_gp4(40) <= ex5_frac_c_gp2(40) and ex5_frac_c_gp2(42); + ex5_frac_c_gp4(41) <= ex5_frac_c_gp2(41) and ex5_frac_c_gp2(43); + ex5_frac_c_gp4(42) <= ex5_frac_c_gp2(42) and ex5_frac_c_gp2(44); + ex5_frac_c_gp4(43) <= ex5_frac_c_gp2(43) and ex5_frac_c_gp2(45); + ex5_frac_c_gp4(44) <= ex5_frac_c_gp2(44) and ex5_frac_c_gp2(46); + ex5_frac_c_gp4(45) <= ex5_frac_c_gp2(45) and ex5_frac_c_gp2(47); + ex5_frac_c_gp4(46) <= ex5_frac_c_gp2(46) ; + ex5_frac_c_gp4(47) <= ex5_frac_c_gp2(47) ; + ex5_frac_c_gp4(48) <= ex5_frac_c_gp2(48) and ex5_frac_c_gp2(50); + ex5_frac_c_gp4(49) <= ex5_frac_c_gp2(49) and ex5_frac_c_gp2(51); + ex5_frac_c_gp4(50) <= ex5_frac_c_gp2(50) and ex5_frac_c_gp2(52); + ex5_frac_c_gp4(51) <= ex5_frac_c_gp2(51) ; + ex5_frac_c_gp4(52) <= ex5_frac_c_gp2(52) ; + + + ex5_frac_c_gp8( 0) <= ex5_frac_c_gp4( 0) and ex5_frac_c_gp4( 4); + ex5_frac_c_gp8( 1) <= ex5_frac_c_gp4( 1) and ex5_frac_c_gp4( 5); + ex5_frac_c_gp8( 2) <= ex5_frac_c_gp4( 2) and ex5_frac_c_gp4( 6); + ex5_frac_c_gp8( 3) <= ex5_frac_c_gp4( 3) and ex5_frac_c_gp4( 7); + ex5_frac_c_gp8( 4) <= ex5_frac_c_gp4( 4) ; + ex5_frac_c_gp8( 5) <= ex5_frac_c_gp4( 5) ; + ex5_frac_c_gp8( 6) <= ex5_frac_c_gp4( 6) ; + ex5_frac_c_gp8( 7) <= ex5_frac_c_gp4( 7) ; + ex5_frac_c_gp8( 8) <= ex5_frac_c_gp4( 8) and ex5_frac_c_gp4(12); + ex5_frac_c_gp8( 9) <= ex5_frac_c_gp4( 9) and ex5_frac_c_gp4(13); + ex5_frac_c_gp8(10) <= ex5_frac_c_gp4(10) and ex5_frac_c_gp4(14); + ex5_frac_c_gp8(11) <= ex5_frac_c_gp4(11) and ex5_frac_c_gp4(15); + ex5_frac_c_gp8(12) <= ex5_frac_c_gp4(12) ; + ex5_frac_c_gp8(13) <= ex5_frac_c_gp4(13) ; + ex5_frac_c_gp8(14) <= ex5_frac_c_gp4(14) ; + ex5_frac_c_gp8(15) <= ex5_frac_c_gp4(15) ; + ex5_frac_c_gp8(16) <= ex5_frac_c_gp4(16) and ex5_frac_c_gp4(20); + ex5_frac_c_gp8(17) <= ex5_frac_c_gp4(17) and ex5_frac_c_gp4(21); + ex5_frac_c_gp8(18) <= ex5_frac_c_gp4(18) and ex5_frac_c_gp4(22); + ex5_frac_c_gp8(19) <= ex5_frac_c_gp4(19) and ex5_frac_c_gp4(23); + ex5_frac_c_gp8(20) <= ex5_frac_c_gp4(20) ; + ex5_frac_c_gp8(21) <= ex5_frac_c_gp4(21) ; + ex5_frac_c_gp8(22) <= ex5_frac_c_gp4(22) ; + ex5_frac_c_gp8(23) <= ex5_frac_c_gp4(23) ; + ex5_frac_c_gp8(24) <= ex5_frac_c_gp4(24) and ex5_frac_c_gp4(28); + ex5_frac_c_gp8(25) <= ex5_frac_c_gp4(25) and ex5_frac_c_gp4(29); + ex5_frac_c_gp8(26) <= ex5_frac_c_gp4(26) and ex5_frac_c_gp4(30); + ex5_frac_c_gp8(27) <= ex5_frac_c_gp4(27) and ex5_frac_c_gp4(31); + ex5_frac_c_gp8(28) <= ex5_frac_c_gp4(28) ; + ex5_frac_c_gp8(29) <= ex5_frac_c_gp4(29) ; + ex5_frac_c_gp8(30) <= ex5_frac_c_gp4(30) ; + ex5_frac_c_gp8(31) <= ex5_frac_c_gp4(31) ; + ex5_frac_c_gp8(32) <= ex5_frac_c_gp4(32) and ex5_frac_c_gp4(36); + ex5_frac_c_gp8(33) <= ex5_frac_c_gp4(33) and ex5_frac_c_gp4(37); + ex5_frac_c_gp8(34) <= ex5_frac_c_gp4(34) and ex5_frac_c_gp4(38); + ex5_frac_c_gp8(35) <= ex5_frac_c_gp4(35) and ex5_frac_c_gp4(39); + ex5_frac_c_gp8(36) <= ex5_frac_c_gp4(36) ; + ex5_frac_c_gp8(37) <= ex5_frac_c_gp4(37) ; + ex5_frac_c_gp8(38) <= ex5_frac_c_gp4(38) ; + ex5_frac_c_gp8(39) <= ex5_frac_c_gp4(39) ; + ex5_frac_c_gp8(40) <= ex5_frac_c_gp4(40) and ex5_frac_c_gp4(44); + ex5_frac_c_gp8(41) <= ex5_frac_c_gp4(41) and ex5_frac_c_gp4(45); + ex5_frac_c_gp8(42) <= ex5_frac_c_gp4(42) and ex5_frac_c_gp4(46); + ex5_frac_c_gp8(43) <= ex5_frac_c_gp4(43) and ex5_frac_c_gp4(47); + ex5_frac_c_gp8(44) <= ex5_frac_c_gp4(44) ; + ex5_frac_c_gp8(45) <= ex5_frac_c_gp4(45) ; + ex5_frac_c_gp8(46) <= ex5_frac_c_gp4(46) ; + ex5_frac_c_gp8(47) <= ex5_frac_c_gp4(47) ; + ex5_frac_c_gp8(48) <= ex5_frac_c_gp4(48) and ex5_frac_c_gp4(52); + ex5_frac_c_gp8(49) <= ex5_frac_c_gp4(49) ; + ex5_frac_c_gp8(50) <= ex5_frac_c_gp4(50) ; + ex5_frac_c_gp8(51) <= ex5_frac_c_gp4(51) ; + ex5_frac_c_gp8(52) <= ex5_frac_c_gp4(52) ; + + ex5_frac_c( 0 to 7) <= ex5_frac_c_gp8( 0 to 7) and ( 0 to 7 => ex5_frac_g( 1) ); + ex5_frac_c( 8 to 15) <= ex5_frac_c_gp8( 8 to 15) and ( 8 to 15 => ex5_frac_g( 2) ); + ex5_frac_c(16 to 23) <= ex5_frac_c_gp8(16 to 23) and (16 to 23 => ex5_frac_g( 3) ); + ex5_frac_c(24) <= (ex5_frac_c_gp8(24) and ex5_frac_g( 4) ) or ex5_sp ; + ex5_frac_c(25 to 31) <= ex5_frac_c_gp8(25 to 31) and (25 to 31 => ex5_frac_g( 4) ); + ex5_frac_c(32 to 39) <= ex5_frac_c_gp8(32 to 39) and (32 to 39 => ex5_frac_g( 5) ); + ex5_frac_c(40 to 47) <= ex5_frac_c_gp8(40 to 47) and (40 to 47 => ex5_frac_g( 6) ); + ex5_frac_c(48 to 52) <= ex5_frac_c_gp8(48 to 52) ; + + + ex5_frac_g16(0) <= ex5_frac_c_gp8( 0) and ex5_frac_c_gp8( 8); + ex5_frac_g16(1) <= ex5_frac_c_gp8( 8) and ex5_frac_c_gp8(16); + ex5_frac_g16(2) <= ex5_frac_c_gp8(16) ; + ex5_frac_g16(3) <= ex5_frac_c_gp8(24) and ex5_frac_c_gp8(32) ; + ex5_frac_g16(4) <= ex5_frac_c_gp8(32) and ex5_frac_c_gp8(40) ; + ex5_frac_g16(5) <= ex5_frac_c_gp8(40) and ex5_frac_c_gp8(48) ; + ex5_frac_g16(6) <= ex5_frac_c_gp8(48) ; + + ex5_frac_g32(0) <= ex5_frac_g16(0) and ex5_frac_g16(2); + ex5_frac_g32(1) <= ex5_frac_g16(1) ; + ex5_frac_g32(2) <= ex5_frac_g16(2) ; + ex5_frac_g32(3) <= ex5_frac_g16(3) and ex5_frac_g16(5); + ex5_frac_g32(4) <= ex5_frac_g16(4) and ex5_frac_g16(6); + ex5_frac_g32(5) <= ex5_frac_g16(5) ; + ex5_frac_g32(6) <= ex5_frac_g16(6) ; + + ex5_all1 <= ex5_frac_g32(0) and (ex5_sp or ex5_frac_g32(3) ); + ex5_frac_g(1) <= ex5_frac_g32(1) and (ex5_sp or ex5_frac_g32(3) ); + ex5_frac_g(2) <= ex5_frac_g32(2) and (ex5_sp or ex5_frac_g32(3) ); + ex5_frac_g(3) <= ex5_frac_g32(3) or ex5_sp ; + ex5_frac_g(4) <= ex5_frac_g32(4) ; + ex5_frac_g(5) <= ex5_frac_g32(5) ; + ex5_frac_g(6) <= ex5_frac_g32(6) ; + + + ex5_frac_p1(0) <= f_nrm_ex5_res(0) or ex5_frac_c(1); + ex5_frac_p1(1 to 51) <= f_nrm_ex5_res(1 to 51) xor ex5_frac_c(2 to 52); + ex5_frac_p1(52) <= not f_nrm_ex5_res(52); + + + + ex5_to_int_data( 0) <= f_nrm_ex5_int_sign ; + ex5_to_int_data( 1 to 10) <= f_nrm_ex5_res( 1 to 10) or ( 1 to 10 => ex5_word) ; + ex5_to_int_data( 11) <= f_nrm_ex5_res(11) or not ex5_to_int_imp or ex5_word ; + ex5_to_int_imp <= + f_nrm_ex5_res(1) or + f_nrm_ex5_res(2) or + f_nrm_ex5_res(3) or + f_nrm_ex5_res(4) or + f_nrm_ex5_res(5) or + f_nrm_ex5_res(6) or + f_nrm_ex5_res(7) or + f_nrm_ex5_res(8) or + f_nrm_ex5_res(9) or + f_nrm_ex5_res(10) or + f_nrm_ex5_res(11) or + ex5_word ; + ex5_to_int_data(12) <= f_nrm_ex5_res(12) or ex5_word ; + ex5_to_int_data(13 to 31) <= f_nrm_ex5_res(13 to 31) and (13 to 31 => not ex5_word) ; + ex5_to_int_data(32 to 52) <= f_nrm_ex5_res(32 to 52) ; + ex5_to_int_data(53 to 63) <= f_nrm_ex5_int_lsbs(2 to 12) ; + + + + ex5_p0_sel_dflt <= not ex5_to_integer and + not ex5_sel_est and + not f_gst_ex5_logexp_v and + not ex5_sel_fpscr ; + + ex5_frac_misc( 0) <= ( ex5_sel_est and f_tbl_ex5_est_frac(0) ) or + ( f_gst_ex5_logexp_v and f_gst_ex5_logexp_fract(0) ) ; + + + ex5_frac_misc( 1 to 16) <= ( ( 1 to 16 => ex5_sel_est ) and f_tbl_ex5_est_frac(1 to 16) ) or + ( ( 1 to 16 => f_gst_ex5_logexp_v) and f_gst_ex5_logexp_fract(1 to 16) ); + + ex5_frac_misc(17 to 19) <= ( (17 to 19 => ex5_sel_est ) and f_tbl_ex5_est_frac(17 to 19) ) or + ( (17 to 19 => ex5_sel_fpscr) and f_scr_ex5_fpscr_rd_dat_dfp(0 to 2) ) or + ( (17 to 19 => f_gst_ex5_logexp_v) and f_gst_ex5_logexp_fract(17 to 19) ); + + ex5_frac_misc( 20) <= ( ( ex5_sel_est ) and f_tbl_ex5_est_frac(20) ) or + ( ( ex5_sel_fpscr) and f_scr_ex5_fpscr_rd_dat_dfp(3) ) ; + + + ex5_frac_misc(21 to 26) <= ( (21 to 26 => ex5_sel_est ) and f_tbl_ex5_est_frac(21 to 26) ) or + ( (21 to 26 => ex5_sel_fpscr) and f_scr_ex5_fpscr_rd_dat(0 to 5) ) ; + ex5_frac_misc(27 to 52) <= (27 to 52 => ex5_sel_fpscr) and f_scr_ex5_fpscr_rd_dat(6 to 31); + + + ex5_frac_p0(0) <= + ( ex5_p0_sel_dflt and f_nrm_ex5_res(0) ) or + ( ex5_to_integer and ex5_to_int_imp ) or + ( ex5_frac_misc(0) ) ; + ex5_frac_p0(1) <= + ( ex5_p0_sel_dflt and f_nrm_ex5_res(1) ) or + ( ex5_to_integer and ex5_to_int_data(12) ) or + ( ex5_frac_misc(1) ) or + ( ex5_quiet ) ; + ex5_frac_p0(2 to 19) <= + ( (2 to 19 => ex5_p0_sel_dflt) and f_nrm_ex5_res( 2 to 19) ) or + ( (2 to 19 => ex5_to_integer ) and ex5_to_int_data(13 to 30) ) or + ( ex5_frac_misc(2 to 19) ) ; + ex5_frac_p0(20 to 52) <= + ( (20 to 52 => ex5_p0_sel_dflt) and f_nrm_ex5_res( 20 to 52) ) or + ( (20 to 52 => ex5_to_integer ) and ex5_to_int_data(31 to 63) ) or + ( ex5_frac_misc(20 to 52) ) ; + + + ex5_frac_px(0 to 23) <= + ( (0 to 23 => ex5_sel_up_b) and ex5_frac_p0(0 to 23) ) or + ( (0 to 23 => ex5_sel_up ) and ex5_frac_p1(0 to 23) ) ; + ex5_frac_px(24 to 52) <= + ( (24 to 52 => ex5_sel_up_dp_b) and ex5_frac_p0(24 to 52) ) or + ( (24 to 52 => ex5_sel_up_dp ) and ex5_frac_p1(24 to 52) ) ; + + + + ex5_frac_k(0) <= ex5_k_notzer or ex5_word ; + ex5_frac_k(1) <= ex5_k_max_intmax_nan or ex5_word; + ex5_frac_k( 2 to 20) <= ( 2 to 20 => ex5_k_max_intmax and not ex5_word ); + ex5_frac_k(21) <= ex5_k_max_intsgn ; + ex5_frac_k(22) <= ex5_k_max_intmax ; + ex5_frac_k(23) <= ex5_k_max_intmax ; + ex5_frac_k(24 to 52) <= (24 to 52 => ex5_k_max_intmax_nsp ); + + ex5_k_notzer <= not (f_pic_ex5_k_zer or f_pic_ex5_k_int_zer or f_pic_ex5_k_int_maxneg ); + ex5_k_max_intmax_nan <= f_pic_ex5_k_max or f_pic_ex5_k_int_maxpos or f_pic_ex5_k_nan ; + ex5_k_max_intmax <= f_pic_ex5_k_max or f_pic_ex5_k_int_maxpos ; + ex5_k_max_intmax_nsp <= (f_pic_ex5_k_max or f_pic_ex5_k_int_maxpos )and not ex5_sp; + + ex5_k_max_intsgn <= ( f_pic_ex5_k_max ) or + ( f_pic_ex5_k_int_maxpos and not ex5_word ) or + ( f_pic_ex5_k_int_maxneg and ex5_word and not ex5_uns ) or + ( f_pic_ex5_k_int_maxpos and ex5_word and ex5_uns ) ; + + + + ex5_res_frac(0) <= + (ex5_frac_k(0) and ex5_res_sel_k_f ) or + (ex5_frac_px(0) and not ex5_res_sel_k_f ) ; + + ex5_res_frac(1 to 52) <= + (ex5_frac_k (1 to 52) and (1 to 52=> ex5_res_sel_k_f) ) or + (ex5_frac_px (1 to 52) and (1 to 52=> not ex5_res_sel_k_f) ) ; + + + + + ex5_k_inf_nan_max <= f_pic_ex5_k_nan or + f_pic_ex5_k_inf or + f_pic_ex5_k_max ; + + ex5_k_inf_nan_maxdp <= f_pic_ex5_k_nan or + f_pic_ex5_k_inf or + ( f_pic_ex5_k_max and not ex5_sp) ; + + ex5_k_inf_nan_zer <= f_pic_ex5_k_nan or + f_pic_ex5_k_inf or + f_pic_ex5_k_zer ; + + ex5_k_zer_sp <= f_pic_ex5_k_zer and ex5_sp ; + + + ex5_expo_k( 1) <= tidn ; + ex5_expo_k( 2) <= tidn ; + ex5_expo_k( 3) <= ex5_k_inf_nan_max or f_pic_ex5_k_int_maxpos or ex5_word ; + ex5_expo_k( 4) <= ex5_k_inf_nan_maxdp or f_pic_ex5_k_int_maxpos or ex5_k_zer_sp or ex5_word or f_pic_ex5_k_one ; + ex5_expo_k( 5) <= ex5_k_inf_nan_maxdp or f_pic_ex5_k_int_maxpos or ex5_k_zer_sp or ex5_word or f_pic_ex5_k_one ; + ex5_expo_k( 6) <= ex5_k_inf_nan_maxdp or f_pic_ex5_k_int_maxpos or ex5_k_zer_sp or ex5_word or f_pic_ex5_k_one ; + ex5_expo_k( 7) <= ex5_k_inf_nan_max or f_pic_ex5_k_int_maxpos or ex5_word or f_pic_ex5_k_one ; + ex5_expo_k( 8) <= ex5_k_inf_nan_max or f_pic_ex5_k_int_maxpos or ex5_word or f_pic_ex5_k_one ; + ex5_expo_k( 9) <= ex5_k_inf_nan_max or f_pic_ex5_k_int_maxpos or ex5_word or f_pic_ex5_k_one ; + ex5_expo_k(10) <= ex5_k_inf_nan_max or f_pic_ex5_k_int_maxpos or ex5_word or f_pic_ex5_k_one ; + ex5_expo_k(11) <= ex5_k_inf_nan_max or f_pic_ex5_k_int_maxpos or ex5_word or f_pic_ex5_k_one ; + ex5_expo_k(12) <= ex5_k_inf_nan_max or f_pic_ex5_k_int_maxpos or ex5_word or f_pic_ex5_k_one ; + ex5_expo_k(13) <= ex5_k_inf_nan_zer or f_pic_ex5_k_int_maxpos or ex5_k_zero + or f_pic_ex5_k_int_maxneg or ex5_word or f_pic_ex5_k_one ; + + + + ex5_expo_p0k(1 to 13) <= + ( ex5_expo_k(1 to 13) and (1 to 13 => ex5_expo_p0_sel_k ) ) or + ( (tidn & tidn & ex5_to_int_data(1 to 11)) and (1 to 13 => ex5_expo_p0_sel_int ) ) or + ( (tidn & tidn & f_gst_ex5_logexp_exp(1 to 11)) and (1 to 13 => ex5_expo_p0_sel_gst ) ) or + ( ((1 to 12=>tidn) & tiup) and (1 to 13 => ex5_sel_fpscr ) ) or + ( f_eov_ex5_expo_p0(1 to 13) and (1 to 13 => ex5_expo_p0_sel_dflt) ) ; + + ex5_expo_p1k(1 to 13) <= + ( ex5_expo_k (1 to 13) and (1 to 13 => ex5_expo_p1_sel_k ) ) or + ( f_eov_ex5_expo_p1 (1 to 13) and (1 to 13 => ex5_expo_p1_sel_dflt) ) ; + + ex5_expo_p0kx(1 to 7) <= + ( ex5_expo_p0k(1 to 7) and (1 to 7 => not ex5_sel_p0_joke) ) or + ( (tidn & tidn & f_eov_ex5_expo_p0_ue1oe1(3 to 7) ) + and (1 to 7 => ex5_sel_p0_joke) ) ; + + ex5_expo_p1kx(1 to 7) <= + ( ex5_expo_p1k(1 to 7) and (1 to 7 => not ex5_sel_p1_joke) ) or + ( (tidn & tidn & f_eov_ex5_expo_p1_ue1oe1(3 to 7) ) + and (1 to 7 => ex5_sel_p1_joke) ) ; + + + ex5_expo_p0kx(8 to 12) <= ex5_expo_p0k(8 to 12); + ex5_expo_p1kx(8 to 12) <= ex5_expo_p1k(8 to 12); + + + + ex5_expo_p0kx(13) <= ex5_expo_p0k(13); + ex5_expo_p1kx(13) <= ex5_expo_p1k(13) ; + + + ex5_res_expo( 1) <= ( ex5_expo_p0kx( 1) and not ex5_res_sel_p1_e and not ex5_res_clip_e ) or + ( ex5_expo_p1kx( 1) and ex5_res_sel_p1_e ); + ex5_res_expo( 2) <= ( ex5_expo_p0kx( 2) and not ex5_res_sel_p1_e and not ex5_res_clip_e ) or + ( ex5_expo_p1kx( 2) and ex5_res_sel_p1_e ); + ex5_res_expo( 3) <= ( ex5_expo_p0kx( 3) and not ex5_res_sel_p1_e and not ex5_res_clip_e ) or + ( ex5_expo_p1kx( 3) and ex5_res_sel_p1_e ); + + ex5_res_expo( 4) <= ( ex5_expo_p0kx( 4) and not ex5_res_sel_p1_e and not ex5_res_clip_e ) or + ( ex5_sp and not ex5_res_sel_p1_e and ex5_res_clip_e ) or + ( ex5_expo_p1kx( 4) and ex5_res_sel_p1_e ); + ex5_res_expo( 5) <= ( ex5_expo_p0kx( 5) and not ex5_res_sel_p1_e and not ex5_res_clip_e ) or + ( ex5_sp and not ex5_res_sel_p1_e and ex5_res_clip_e ) or + ( ex5_expo_p1kx( 5) and ex5_res_sel_p1_e ); + ex5_res_expo( 6) <= ( ex5_expo_p0kx( 6) and not ex5_res_sel_p1_e and not ex5_res_clip_e ) or + ( ex5_sp and not ex5_res_sel_p1_e and ex5_res_clip_e ) or + ( ex5_expo_p1kx( 6) and ex5_res_sel_p1_e ); + + ex5_res_expo( 7) <= ( ex5_expo_p0kx( 7) and not ex5_res_sel_p1_e and not ex5_res_clip_e ) or + ( ex5_expo_p1kx( 7) and ex5_res_sel_p1_e ); + ex5_res_expo( 8) <= ( ex5_expo_p0kx( 8) and not ex5_res_sel_p1_e and not ex5_res_clip_e ) or + ( ex5_expo_p1kx( 8) and ex5_res_sel_p1_e ); + ex5_res_expo( 9) <= ( ex5_expo_p0kx( 9) and not ex5_res_sel_p1_e and not ex5_res_clip_e ) or + ( ex5_expo_p1kx( 9) and ex5_res_sel_p1_e ); + ex5_res_expo(10) <= ( ex5_expo_p0kx(10) and not ex5_res_sel_p1_e and not ex5_res_clip_e ) or + ( ex5_expo_p1kx(10) and ex5_res_sel_p1_e ); + ex5_res_expo(11) <= ( ex5_expo_p0kx(11) and not ex5_res_sel_p1_e and not ex5_res_clip_e ) or + ( ex5_expo_p1kx(11) and ex5_res_sel_p1_e ); + ex5_res_expo(12) <= ( ex5_expo_p0kx(12) and not ex5_res_sel_p1_e and not ex5_res_clip_e ) or + ( ex5_expo_p1kx(12) and ex5_res_sel_p1_e ); + ex5_res_expo(13) <= ( ex5_expo_p0kx(13) and not ex5_res_sel_p1_e ) or + ( not ex5_res_sel_p1_e and ex5_res_clip_e ) or + ( ex5_expo_p1kx(13) and ex5_res_sel_p1_e ); + + + ex5_sgn_result_fp <= f_pic_ex5_round_sign xor f_pic_ex5_invert_sign; + + ex5_res_sign_prez <= + ( ex5_sgn_result_fp and not ( (ex5_to_integer or f_gst_ex5_logexp_v) and not ex5_expo_sel_k) ) or + ( ex5_to_int_data(0) and ( ex5_to_integer and not ex5_expo_sel_k) and not ex5_word ) or + ( f_gst_ex5_logexp_sign and ( f_gst_ex5_logexp_v and not ex5_expo_sel_k) ) ; + + + ex5_exact_zero_rnd <= f_nrm_ex5_exact_zero and + not f_nrm_ex5_nrm_sticky_dp ; + + + ex5_rnd_ni_adj <= ex5_rnd_ni xor f_pic_ex5_invert_sign; + + ex5_exact_sgn_rst <= f_pic_ex5_en_exact_zero and ex5_exact_zero_rnd and not ex5_rnd_ni_adj ; + ex5_exact_sgn_set <= f_pic_ex5_en_exact_zero and ex5_exact_zero_rnd and ex5_rnd_ni_adj ; + + ex5_res_sign <= (ex5_res_sign_prez and not ex5_exact_sgn_rst) or ex5_exact_sgn_set; + + + + ex5_res_sel_k_f <= + ( f_eov_ex5_sel_kif_f and ex5_all1 and ex5_up ) or + ( f_eov_ex5_sel_k_f ) or + ( ex5_clip_deno ) or + ( ex5_sel_est and f_tbl_ex5_recip_den and ex5_nj_deno ) ; + + + ex5_res_sel_p1_e <= ex5_all1 and ex5_up ; + + + ex5_est_log_pow <= f_gst_ex5_logexp_v or ex5_sel_est ; + + ex5_res_clip_e <= + ( ex5_unf_en_ue0 and not f_nrm_ex5_res(0) and not ex5_expo_sel_k and not ex5_est_log_pow) or + ( ex5_unf_en_ue0 and f_eov_ex5_unf_expo and not ex5_expo_sel_k and not ex5_est_log_pow) or + ( ex5_all0 and not ex5_to_integer and not ex5_expo_sel_k and not ex5_est_log_pow) or + ( ex5_nj_deno and not f_nrm_ex5_res(0) and not ex5_expo_sel_k and not ex5_est_log_pow) ; + + ex5_clip_deno <= ( ex5_nj_deno and not f_nrm_ex5_res(0) and not ex5_expo_sel_k and not ex5_est_log_pow) ; + + ex5_expo_sel_k <= f_eov_ex5_sel_k_e; + ex5_expo_sel_k_both <= f_eov_ex5_sel_k_e or f_eov_ex5_sel_kif_e; + + + ex5_expo_p0_sel_k <= ex5_expo_sel_k ; + ex5_expo_p0_sel_gst <= not ex5_expo_sel_k and f_gst_ex5_logexp_v; + ex5_expo_p0_sel_int <= not ex5_expo_sel_k and ex5_to_integer; + ex5_expo_p0_sel_dflt <= not ex5_expo_sel_k and not ex5_to_integer and not f_gst_ex5_logexp_v; + + + ex5_expo_p1_sel_k <= ex5_expo_sel_k_both; + ex5_expo_p1_sel_dflt <= not ex5_expo_sel_k_both; + + ex5_sel_p0_joke <= + ( ex5_unf_en_ue1 and f_eov_ex5_unf_expo ) or + ( ex5_ovf_en_oe1 and f_eov_ex5_ovf_expo ); + + ex5_sel_p1_joke <= + ( ex5_unf_en_ue1 and f_eov_ex5_unf_expo ) or + ( ex5_ovf_en_oe1 and f_eov_ex5_ovf_expo ) or + ( ex5_ovf_en_oe1 and f_eov_ex5_ovf_if_expo ); + + + + + + ex5_pwr4_spec_frsp <= ex5_unf_en_ue1 and not f_nrm_ex5_res(0) and f_pic_ex5_frsp ; + + ex5_flag_ox <= + ( f_eov_ex5_ovf_expo ) or + ( f_eov_ex5_ovf_if_expo and ex5_all1 and ex5_up ) ; + + ex5_ov_oe0 <= ex5_flag_ox and ex5_ovf_en_oe0; + + ex5_flag_inf <= + ( ex5_spec_inf ) or + ( ex5_ov_oe0 and not f_pic_ex5_k_max ); + + + ex5_flag_up <= ex5_ov_oe0 or ex5_up; + ex5_flag_fi <= ex5_ov_oe0 or ex5_gox; + + + + ex5_flag_ux <= + ( ex5_unf_en_ue0 and not f_nrm_ex5_res(0) and not ex5_exact_zero_rnd and ex5_gox and not ex5_sel_est ) or + ( ex5_unf_en_ue0 and f_eov_ex5_unf_expo and not ex5_exact_zero_rnd and ex5_gox ) or + ( ex5_unf_en_ue1 and f_eov_ex5_unf_expo and not ex5_exact_zero_rnd ) or + ( ex5_unf_en_ue1 and f_eov_ex5_unf_expo and ex5_sel_est ) or + ( ex5_unf_en_ue0 and f_eov_ex5_unf_expo and ex5_sel_est ) or + ( ex5_pwr4_spec_frsp ); + + + + ex5_k_zero <= f_pic_ex5_k_zer or f_pic_ex5_k_int_zer ; + + ex5_flag_zer <= + ( not ex5_sel_est and not ex5_res_sel_k_f and ex5_all0 and not ex5_up ) or + ( ex5_res_sel_k_f and ex5_k_zero ) ; + + ex5_flag_den <= + ( not ex5_sel_est and not ex5_res_frac(0) ) or + ( ex5_sel_est and f_tbl_ex5_recip_den ) or + ( ex5_sel_est and ex5_unf_en_ue0 and f_eov_ex5_unf_expo ) ; + + + + + ex6_frac_lat: tri_rlmreg_p generic map (width=> 53, expand_type => expand_type, needs_sreset => 0) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(6) , + mpw1_b => mpw1_b(6) , + mpw2_b => mpw2_b(1) , + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => ex5_act, + scout => ex6_frac_so , + scin => ex6_frac_si , + din => ex5_res_frac(0 to 52), + dout => ex6_res_frac(0 to 52) ); + + ex6_expo_lat: tri_rlmreg_p generic map (width=> 14, expand_type => expand_type, needs_sreset => 0) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(6) , + mpw1_b => mpw1_b(6) , + mpw2_b => mpw2_b(1) , + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => ex5_act, + scout => ex6_expo_so , + scin => ex6_expo_si , + din(0) => ex5_res_sign , + din(1 to 13) => ex5_res_expo(1 to 13) , + dout(0) => ex6_res_sign , + dout(1 to 13) => ex6_res_expo(1 to 13) ); + + ex6_flag_lat: tri_rlmreg_p generic map (width=> 10, expand_type => expand_type, needs_sreset => 1) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(6) , + mpw1_b => mpw1_b(6) , + mpw2_b => mpw2_b(1) , + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => ex5_act, + scout => ex6_flag_so , + scin => ex6_flag_si , + din(0) => flag_spare_unused , + din(1) => ex5_res_sign , + din(2) => ex5_flag_den , + din(3) => ex5_flag_inf , + din(4) => ex5_flag_zer , + din(5) => ex5_flag_ux , + din(6) => ex5_flag_up , + din(7) => ex5_flag_fi , + din(8) => ex5_flag_ox , + din(9) => ex5_nj_deno , + dout(0) => flag_spare_unused , + dout(1) => ex6_flag_sgn , + dout(2) => ex6_flag_den , + dout(3) => ex6_flag_inf , + dout(4) => ex6_flag_zer , + dout(5) => ex6_flag_ux , + dout(6) => ex6_flag_up , + dout(7) => ex6_flag_fi , + dout(8) => ex6_flag_ox , + dout(9) => ex6_nj_deno ); + + + f_rnd_ex6_res_sign <= ex6_res_sign ; + f_rnd_ex6_res_expo(1 to 13) <= ex6_res_expo(1 to 13) ; + f_rnd_ex6_res_frac(0 to 52) <= ex6_res_frac(0 to 52) ; + + f_rnd_ex6_flag_sgn <= ex6_flag_sgn ; + f_rnd_ex6_flag_den <= ex6_flag_den and not ex6_nj_deno ; + f_rnd_ex6_flag_inf <= ex6_flag_inf ; + f_rnd_ex6_flag_zer <= ex6_flag_zer or (ex6_flag_den and ex6_nj_deno) ; + f_rnd_ex6_flag_ux <= ex6_flag_ux and not(ex6_flag_den and ex6_nj_deno) ; + f_rnd_ex6_flag_up <= ex6_flag_up and not(ex6_flag_den and ex6_nj_deno) ; + f_rnd_ex6_flag_fi <= ex6_flag_fi and not(ex6_flag_den and ex6_nj_deno) ; + f_rnd_ex6_flag_ox <= ex6_flag_ox ; + + + f_mad_ex6_uc_sign <= ex6_res_sign; + f_mad_ex6_uc_zero <= ex6_flag_zer and not ex6_flag_fi; + + + act_si (0 to 4) <= act_so (1 to 4) & f_rnd_si ; + ex5_ctl_si (0 to 15) <= ex5_ctl_so (1 to 15) & act_so (0) ; + ex6_frac_si (0 to 52) <= ex6_frac_so (1 to 52) & ex5_ctl_so (0) ; + ex6_expo_si (0 to 13) <= ex6_expo_so (1 to 13) & ex6_frac_so (0) ; + ex6_flag_si (0 to 9) <= ex6_flag_so (1 to 9) & ex6_expo_so (0) ; + f_rnd_so <= ex6_flag_so (0); + + +end; + + + + + + + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_sa3.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_sa3.vhdl new file mode 100644 index 0000000..ee0651b --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_sa3.vhdl @@ -0,0 +1,1137 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee,ibm,support,tri, work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; +library clib ; + +entity fuq_sa3 is +generic(expand_type: integer := 2 ); +port( + vdd :inout power_logic; + gnd :inout power_logic; + clkoff_b :in std_ulogic; + act_dis :in std_ulogic; + flush :in std_ulogic; + delay_lclkr :in std_ulogic_vector(2 to 3); + mpw1_b :in std_ulogic_vector(2 to 3); + mpw2_b :in std_ulogic_vector(0 to 0); + sg_1 :in std_ulogic; + thold_1 :in std_ulogic; + fpu_enable :in std_ulogic; + nclk :in clk_logic; + + + + f_sa3_si :in std_ulogic; + f_sa3_so :out std_ulogic; + ex1_act_b :in std_ulogic; + + f_mul_ex2_sum :in std_ulogic_vector(54 to 161); + f_mul_ex2_car :in std_ulogic_vector(54 to 161); + f_alg_ex2_res :in std_ulogic_vector(0 to 162); + + f_sa3_ex3_s_lza :out std_ulogic_vector(0 to 162); + f_sa3_ex3_c_lza :out std_ulogic_vector(53 to 161); + + f_sa3_ex3_s_add :out std_ulogic_vector(0 to 162); + f_sa3_ex3_c_add :out std_ulogic_vector(53 to 161) +); + + + +end fuq_sa3; + +architecture fuq_sa3 of fuq_sa3 is + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal thold_0_b, thold_0, forcee , sg_0 :std_ulogic; + signal act_spare_unused :std_ulogic_vector(0 to 3); + signal ex2_act :std_ulogic; + signal act_so , act_si :std_ulogic_vector(0 to 4); + signal ex3_sum :std_ulogic_vector(0 to 162); + signal ex3_car :std_ulogic_vector(53 to 161); + signal ex1_act :std_ulogic; + signal ex3_053_sum_si, ex3_053_sum_so :std_ulogic_vector(0 to 109); + signal ex3_053_car_si, ex3_053_car_so :std_ulogic_vector(0 to 108); + signal ex3_000_si, ex3_000_so :std_ulogic_vector(0 to 52); + signal ex3_sum_lza_b, ex3_sum_add_b :std_ulogic_vector(0 to 162); + signal ex3_car_lza_b, ex3_car_add_b :std_ulogic_vector(53 to 161); + signal sa3_ex3_d2clk , sa3_ex3_d1clk :std_ulogic; + signal sa3_ex3_lclk : clk_logic; + + signal ex2_alg_b :std_ulogic_vector(0 to 52) ; + signal ex2_sum_b :std_ulogic_vector(53 to 162) ; + signal ex2_car_b :std_ulogic_vector(53 to 161) ; + + signal f_alg_ex2_res_b, f_mul_ex2_sum_b, f_mul_ex2_car_b :std_ulogic_vector(55 to 161); + + + + + + + + + + + + + + + + + + +begin + + + + + + + + ex2_sum_b(54) <= not( not(f_mul_ex2_sum(54) or f_mul_ex2_car(54)) xor f_alg_ex2_res(54) ); + ex2_car_b(53) <= not( (f_mul_ex2_sum(54) or f_mul_ex2_car(54)) or f_alg_ex2_res(54) ); + + + + + u_algi: ex2_alg_b(0 to 52) <= not f_alg_ex2_res(0 to 52) ; + + + + u_pre_a: f_alg_ex2_res_b(55 to 161) <= not( f_alg_ex2_res(55 to 161) ); + u_pre_s: f_mul_ex2_sum_b(55 to 161) <= not( f_mul_ex2_sum(55 to 161) ); + u_pre_c: f_mul_ex2_car_b(55 to 161) <= not( f_mul_ex2_car(55 to 161) ); + + + res_csa_55: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(55), + b => f_mul_ex2_sum_b(55), + c => f_mul_ex2_car_b(55), + sum => ex2_sum_b(55) , + car => ex2_car_b(54) ); + res_csa_56: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(56), + b => f_mul_ex2_sum_b(56), + c => f_mul_ex2_car_b(56), + sum => ex2_sum_b(56) , + car => ex2_car_b(55) ); + res_csa_57: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(57), + b => f_mul_ex2_sum_b(57), + c => f_mul_ex2_car_b(57), + sum => ex2_sum_b(57) , + car => ex2_car_b(56) ); + res_csa_58: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(58), + b => f_mul_ex2_sum_b(58), + c => f_mul_ex2_car_b(58), + sum => ex2_sum_b(58) , + car => ex2_car_b(57) ); + res_csa_59: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(59), + b => f_mul_ex2_sum_b(59), + c => f_mul_ex2_car_b(59), + sum => ex2_sum_b(59) , + car => ex2_car_b(58) ); + res_csa_60: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(60), + b => f_mul_ex2_sum_b(60), + c => f_mul_ex2_car_b(60), + sum => ex2_sum_b(60) , + car => ex2_car_b(59) ); + res_csa_61: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(61), + b => f_mul_ex2_sum_b(61), + c => f_mul_ex2_car_b(61), + sum => ex2_sum_b(61) , + car => ex2_car_b(60) ); + res_csa_62: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(62), + b => f_mul_ex2_sum_b(62), + c => f_mul_ex2_car_b(62), + sum => ex2_sum_b(62) , + car => ex2_car_b(61) ); + res_csa_63: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(63), + b => f_mul_ex2_sum_b(63), + c => f_mul_ex2_car_b(63), + sum => ex2_sum_b(63) , + car => ex2_car_b(62) ); + res_csa_64: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(64), + b => f_mul_ex2_sum_b(64), + c => f_mul_ex2_car_b(64), + sum => ex2_sum_b(64) , + car => ex2_car_b(63) ); + res_csa_65: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(65), + b => f_mul_ex2_sum_b(65), + c => f_mul_ex2_car_b(65), + sum => ex2_sum_b(65) , + car => ex2_car_b(64) ); + res_csa_66: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(66), + b => f_mul_ex2_sum_b(66), + c => f_mul_ex2_car_b(66), + sum => ex2_sum_b(66) , + car => ex2_car_b(65) ); + res_csa_67: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(67), + b => f_mul_ex2_sum_b(67), + c => f_mul_ex2_car_b(67), + sum => ex2_sum_b(67) , + car => ex2_car_b(66) ); + res_csa_68: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(68), + b => f_mul_ex2_sum_b(68), + c => f_mul_ex2_car_b(68), + sum => ex2_sum_b(68) , + car => ex2_car_b(67) ); + res_csa_69: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(69), + b => f_mul_ex2_sum_b(69), + c => f_mul_ex2_car_b(69), + sum => ex2_sum_b(69) , + car => ex2_car_b(68) ); + res_csa_70: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(70), + b => f_mul_ex2_sum_b(70), + c => f_mul_ex2_car_b(70), + sum => ex2_sum_b(70) , + car => ex2_car_b(69) ); + res_csa_71: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(71), + b => f_mul_ex2_sum_b(71), + c => f_mul_ex2_car_b(71), + sum => ex2_sum_b(71) , + car => ex2_car_b(70) ); + res_csa_72: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(72), + b => f_mul_ex2_sum_b(72), + c => f_mul_ex2_car_b(72), + sum => ex2_sum_b(72) , + car => ex2_car_b(71) ); + res_csa_73: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(73), + b => f_mul_ex2_sum_b(73), + c => f_mul_ex2_car_b(73), + sum => ex2_sum_b(73) , + car => ex2_car_b(72) ); + res_csa_74: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(74), + b => f_mul_ex2_sum_b(74), + c => f_mul_ex2_car_b(74), + sum => ex2_sum_b(74) , + car => ex2_car_b(73) ); + res_csa_75: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(75), + b => f_mul_ex2_sum_b(75), + c => f_mul_ex2_car_b(75), + sum => ex2_sum_b(75) , + car => ex2_car_b(74) ); + res_csa_76: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(76), + b => f_mul_ex2_sum_b(76), + c => f_mul_ex2_car_b(76), + sum => ex2_sum_b(76) , + car => ex2_car_b(75) ); + res_csa_77: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(77), + b => f_mul_ex2_sum_b(77), + c => f_mul_ex2_car_b(77), + sum => ex2_sum_b(77) , + car => ex2_car_b(76) ); + res_csa_78: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(78), + b => f_mul_ex2_sum_b(78), + c => f_mul_ex2_car_b(78), + sum => ex2_sum_b(78) , + car => ex2_car_b(77) ); + res_csa_79: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(79), + b => f_mul_ex2_sum_b(79), + c => f_mul_ex2_car_b(79), + sum => ex2_sum_b(79) , + car => ex2_car_b(78) ); + res_csa_80: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(80), + b => f_mul_ex2_sum_b(80), + c => f_mul_ex2_car_b(80), + sum => ex2_sum_b(80) , + car => ex2_car_b(79) ); + res_csa_81: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(81), + b => f_mul_ex2_sum_b(81), + c => f_mul_ex2_car_b(81), + sum => ex2_sum_b(81) , + car => ex2_car_b(80) ); + res_csa_82: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(82), + b => f_mul_ex2_sum_b(82), + c => f_mul_ex2_car_b(82), + sum => ex2_sum_b(82) , + car => ex2_car_b(81) ); + res_csa_83: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(83), + b => f_mul_ex2_sum_b(83), + c => f_mul_ex2_car_b(83), + sum => ex2_sum_b(83) , + car => ex2_car_b(82) ); + res_csa_84: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(84), + b => f_mul_ex2_sum_b(84), + c => f_mul_ex2_car_b(84), + sum => ex2_sum_b(84) , + car => ex2_car_b(83) ); + res_csa_85: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(85), + b => f_mul_ex2_sum_b(85), + c => f_mul_ex2_car_b(85), + sum => ex2_sum_b(85) , + car => ex2_car_b(84) ); + res_csa_86: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(86), + b => f_mul_ex2_sum_b(86), + c => f_mul_ex2_car_b(86), + sum => ex2_sum_b(86) , + car => ex2_car_b(85) ); + res_csa_87: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(87), + b => f_mul_ex2_sum_b(87), + c => f_mul_ex2_car_b(87), + sum => ex2_sum_b(87) , + car => ex2_car_b(86) ); + res_csa_88: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(88), + b => f_mul_ex2_sum_b(88), + c => f_mul_ex2_car_b(88), + sum => ex2_sum_b(88) , + car => ex2_car_b(87) ); + res_csa_89: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(89), + b => f_mul_ex2_sum_b(89), + c => f_mul_ex2_car_b(89), + sum => ex2_sum_b(89) , + car => ex2_car_b(88) ); + res_csa_90: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(90), + b => f_mul_ex2_sum_b(90), + c => f_mul_ex2_car_b(90), + sum => ex2_sum_b(90) , + car => ex2_car_b(89) ); + res_csa_91: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(91), + b => f_mul_ex2_sum_b(91), + c => f_mul_ex2_car_b(91), + sum => ex2_sum_b(91) , + car => ex2_car_b(90) ); + res_csa_92: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(92), + b => f_mul_ex2_sum_b(92), + c => f_mul_ex2_car_b(92), + sum => ex2_sum_b(92) , + car => ex2_car_b(91) ); + res_csa_93: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(93), + b => f_mul_ex2_sum_b(93), + c => f_mul_ex2_car_b(93), + sum => ex2_sum_b(93) , + car => ex2_car_b(92) ); + res_csa_94: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(94), + b => f_mul_ex2_sum_b(94), + c => f_mul_ex2_car_b(94), + sum => ex2_sum_b(94) , + car => ex2_car_b(93) ); + res_csa_95: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(95), + b => f_mul_ex2_sum_b(95), + c => f_mul_ex2_car_b(95), + sum => ex2_sum_b(95) , + car => ex2_car_b(94) ); + res_csa_96: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(96), + b => f_mul_ex2_sum_b(96), + c => f_mul_ex2_car_b(96), + sum => ex2_sum_b(96) , + car => ex2_car_b(95) ); + res_csa_97: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(97), + b => f_mul_ex2_sum_b(97), + c => f_mul_ex2_car_b(97), + sum => ex2_sum_b(97) , + car => ex2_car_b(96) ); + res_csa_98: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(98), + b => f_mul_ex2_sum_b(98), + c => f_mul_ex2_car_b(98), + sum => ex2_sum_b(98) , + car => ex2_car_b(97) ); + res_csa_99: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(99), + b => f_mul_ex2_sum_b(99), + c => f_mul_ex2_car_b(99), + sum => ex2_sum_b(99) , + car => ex2_car_b(98) ); + res_csa_100: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(100), + b => f_mul_ex2_sum_b(100), + c => f_mul_ex2_car_b(100), + sum => ex2_sum_b(100) , + car => ex2_car_b(99) ); + res_csa_101: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(101), + b => f_mul_ex2_sum_b(101), + c => f_mul_ex2_car_b(101), + sum => ex2_sum_b(101) , + car => ex2_car_b(100) ); + res_csa_102: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(102), + b => f_mul_ex2_sum_b(102), + c => f_mul_ex2_car_b(102), + sum => ex2_sum_b(102) , + car => ex2_car_b(101) ); + res_csa_103: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(103), + b => f_mul_ex2_sum_b(103), + c => f_mul_ex2_car_b(103), + sum => ex2_sum_b(103) , + car => ex2_car_b(102) ); + res_csa_104: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(104), + b => f_mul_ex2_sum_b(104), + c => f_mul_ex2_car_b(104), + sum => ex2_sum_b(104) , + car => ex2_car_b(103) ); + res_csa_105: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(105), + b => f_mul_ex2_sum_b(105), + c => f_mul_ex2_car_b(105), + sum => ex2_sum_b(105) , + car => ex2_car_b(104) ); + res_csa_106: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(106), + b => f_mul_ex2_sum_b(106), + c => f_mul_ex2_car_b(106), + sum => ex2_sum_b(106) , + car => ex2_car_b(105) ); + res_csa_107: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(107), + b => f_mul_ex2_sum_b(107), + c => f_mul_ex2_car_b(107), + sum => ex2_sum_b(107) , + car => ex2_car_b(106) ); + res_csa_108: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(108), + b => f_mul_ex2_sum_b(108), + c => f_mul_ex2_car_b(108), + sum => ex2_sum_b(108) , + car => ex2_car_b(107) ); + res_csa_109: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(109), + b => f_mul_ex2_sum_b(109), + c => f_mul_ex2_car_b(109), + sum => ex2_sum_b(109) , + car => ex2_car_b(108) ); + res_csa_110: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(110), + b => f_mul_ex2_sum_b(110), + c => f_mul_ex2_car_b(110), + sum => ex2_sum_b(110) , + car => ex2_car_b(109) ); + res_csa_111: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(111), + b => f_mul_ex2_sum_b(111), + c => f_mul_ex2_car_b(111), + sum => ex2_sum_b(111) , + car => ex2_car_b(110) ); + res_csa_112: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(112), + b => f_mul_ex2_sum_b(112), + c => f_mul_ex2_car_b(112), + sum => ex2_sum_b(112) , + car => ex2_car_b(111) ); + res_csa_113: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(113), + b => f_mul_ex2_sum_b(113), + c => f_mul_ex2_car_b(113), + sum => ex2_sum_b(113) , + car => ex2_car_b(112) ); + res_csa_114: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(114), + b => f_mul_ex2_sum_b(114), + c => f_mul_ex2_car_b(114), + sum => ex2_sum_b(114) , + car => ex2_car_b(113) ); + res_csa_115: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(115), + b => f_mul_ex2_sum_b(115), + c => f_mul_ex2_car_b(115), + sum => ex2_sum_b(115) , + car => ex2_car_b(114) ); + res_csa_116: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(116), + b => f_mul_ex2_sum_b(116), + c => f_mul_ex2_car_b(116), + sum => ex2_sum_b(116) , + car => ex2_car_b(115) ); + res_csa_117: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(117), + b => f_mul_ex2_sum_b(117), + c => f_mul_ex2_car_b(117), + sum => ex2_sum_b(117) , + car => ex2_car_b(116) ); + res_csa_118: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(118), + b => f_mul_ex2_sum_b(118), + c => f_mul_ex2_car_b(118), + sum => ex2_sum_b(118) , + car => ex2_car_b(117) ); + res_csa_119: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(119), + b => f_mul_ex2_sum_b(119), + c => f_mul_ex2_car_b(119), + sum => ex2_sum_b(119) , + car => ex2_car_b(118) ); + res_csa_120: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(120), + b => f_mul_ex2_sum_b(120), + c => f_mul_ex2_car_b(120), + sum => ex2_sum_b(120) , + car => ex2_car_b(119) ); + res_csa_121: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(121), + b => f_mul_ex2_sum_b(121), + c => f_mul_ex2_car_b(121), + sum => ex2_sum_b(121) , + car => ex2_car_b(120) ); + res_csa_122: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(122), + b => f_mul_ex2_sum_b(122), + c => f_mul_ex2_car_b(122), + sum => ex2_sum_b(122) , + car => ex2_car_b(121) ); + res_csa_123: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(123), + b => f_mul_ex2_sum_b(123), + c => f_mul_ex2_car_b(123), + sum => ex2_sum_b(123) , + car => ex2_car_b(122) ); + res_csa_124: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(124), + b => f_mul_ex2_sum_b(124), + c => f_mul_ex2_car_b(124), + sum => ex2_sum_b(124) , + car => ex2_car_b(123) ); + res_csa_125: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(125), + b => f_mul_ex2_sum_b(125), + c => f_mul_ex2_car_b(125), + sum => ex2_sum_b(125) , + car => ex2_car_b(124) ); + res_csa_126: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(126), + b => f_mul_ex2_sum_b(126), + c => f_mul_ex2_car_b(126), + sum => ex2_sum_b(126) , + car => ex2_car_b(125) ); + res_csa_127: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(127), + b => f_mul_ex2_sum_b(127), + c => f_mul_ex2_car_b(127), + sum => ex2_sum_b(127) , + car => ex2_car_b(126) ); + res_csa_128: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(128), + b => f_mul_ex2_sum_b(128), + c => f_mul_ex2_car_b(128), + sum => ex2_sum_b(128) , + car => ex2_car_b(127) ); + res_csa_129: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(129), + b => f_mul_ex2_sum_b(129), + c => f_mul_ex2_car_b(129), + sum => ex2_sum_b(129) , + car => ex2_car_b(128) ); + res_csa_130: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(130), + b => f_mul_ex2_sum_b(130), + c => f_mul_ex2_car_b(130), + sum => ex2_sum_b(130) , + car => ex2_car_b(129) ); + res_csa_131: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(131), + b => f_mul_ex2_sum_b(131), + c => f_mul_ex2_car_b(131), + sum => ex2_sum_b(131) , + car => ex2_car_b(130) ); + res_csa_132: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(132), + b => f_mul_ex2_sum_b(132), + c => f_mul_ex2_car_b(132), + sum => ex2_sum_b(132) , + car => ex2_car_b(131) ); + res_csa_133: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(133), + b => f_mul_ex2_sum_b(133), + c => f_mul_ex2_car_b(133), + sum => ex2_sum_b(133) , + car => ex2_car_b(132) ); + res_csa_134: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(134), + b => f_mul_ex2_sum_b(134), + c => f_mul_ex2_car_b(134), + sum => ex2_sum_b(134) , + car => ex2_car_b(133) ); + res_csa_135: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(135), + b => f_mul_ex2_sum_b(135), + c => f_mul_ex2_car_b(135), + sum => ex2_sum_b(135) , + car => ex2_car_b(134) ); + res_csa_136: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(136), + b => f_mul_ex2_sum_b(136), + c => f_mul_ex2_car_b(136), + sum => ex2_sum_b(136) , + car => ex2_car_b(135) ); + res_csa_137: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(137), + b => f_mul_ex2_sum_b(137), + c => f_mul_ex2_car_b(137), + sum => ex2_sum_b(137) , + car => ex2_car_b(136) ); + res_csa_138: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(138), + b => f_mul_ex2_sum_b(138), + c => f_mul_ex2_car_b(138), + sum => ex2_sum_b(138) , + car => ex2_car_b(137) ); + res_csa_139: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(139), + b => f_mul_ex2_sum_b(139), + c => f_mul_ex2_car_b(139), + sum => ex2_sum_b(139) , + car => ex2_car_b(138) ); + res_csa_140: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(140), + b => f_mul_ex2_sum_b(140), + c => f_mul_ex2_car_b(140), + sum => ex2_sum_b(140) , + car => ex2_car_b(139) ); + res_csa_141: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(141), + b => f_mul_ex2_sum_b(141), + c => f_mul_ex2_car_b(141), + sum => ex2_sum_b(141) , + car => ex2_car_b(140) ); + res_csa_142: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(142), + b => f_mul_ex2_sum_b(142), + c => f_mul_ex2_car_b(142), + sum => ex2_sum_b(142) , + car => ex2_car_b(141) ); + res_csa_143: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(143), + b => f_mul_ex2_sum_b(143), + c => f_mul_ex2_car_b(143), + sum => ex2_sum_b(143) , + car => ex2_car_b(142) ); + res_csa_144: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(144), + b => f_mul_ex2_sum_b(144), + c => f_mul_ex2_car_b(144), + sum => ex2_sum_b(144) , + car => ex2_car_b(143) ); + res_csa_145: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(145), + b => f_mul_ex2_sum_b(145), + c => f_mul_ex2_car_b(145), + sum => ex2_sum_b(145) , + car => ex2_car_b(144) ); + res_csa_146: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(146), + b => f_mul_ex2_sum_b(146), + c => f_mul_ex2_car_b(146), + sum => ex2_sum_b(146) , + car => ex2_car_b(145) ); + res_csa_147: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(147), + b => f_mul_ex2_sum_b(147), + c => f_mul_ex2_car_b(147), + sum => ex2_sum_b(147) , + car => ex2_car_b(146) ); + res_csa_148: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(148), + b => f_mul_ex2_sum_b(148), + c => f_mul_ex2_car_b(148), + sum => ex2_sum_b(148) , + car => ex2_car_b(147) ); + res_csa_149: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(149), + b => f_mul_ex2_sum_b(149), + c => f_mul_ex2_car_b(149), + sum => ex2_sum_b(149) , + car => ex2_car_b(148) ); + res_csa_150: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(150), + b => f_mul_ex2_sum_b(150), + c => f_mul_ex2_car_b(150), + sum => ex2_sum_b(150) , + car => ex2_car_b(149) ); + res_csa_151: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(151), + b => f_mul_ex2_sum_b(151), + c => f_mul_ex2_car_b(151), + sum => ex2_sum_b(151) , + car => ex2_car_b(150) ); + res_csa_152: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(152), + b => f_mul_ex2_sum_b(152), + c => f_mul_ex2_car_b(152), + sum => ex2_sum_b(152) , + car => ex2_car_b(151) ); + res_csa_153: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(153), + b => f_mul_ex2_sum_b(153), + c => f_mul_ex2_car_b(153), + sum => ex2_sum_b(153) , + car => ex2_car_b(152) ); + res_csa_154: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(154), + b => f_mul_ex2_sum_b(154), + c => f_mul_ex2_car_b(154), + sum => ex2_sum_b(154) , + car => ex2_car_b(153) ); + res_csa_155: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(155), + b => f_mul_ex2_sum_b(155), + c => f_mul_ex2_car_b(155), + sum => ex2_sum_b(155) , + car => ex2_car_b(154) ); + res_csa_156: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(156), + b => f_mul_ex2_sum_b(156), + c => f_mul_ex2_car_b(156), + sum => ex2_sum_b(156) , + car => ex2_car_b(155) ); + res_csa_157: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(157), + b => f_mul_ex2_sum_b(157), + c => f_mul_ex2_car_b(157), + sum => ex2_sum_b(157) , + car => ex2_car_b(156) ); + res_csa_158: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(158), + b => f_mul_ex2_sum_b(158), + c => f_mul_ex2_car_b(158), + sum => ex2_sum_b(158) , + car => ex2_car_b(157) ); + res_csa_159: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(159), + b => f_mul_ex2_sum_b(159), + c => f_mul_ex2_car_b(159), + sum => ex2_sum_b(159) , + car => ex2_car_b(158) ); + res_csa_160: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(160), + b => f_mul_ex2_sum_b(160), + c => f_mul_ex2_car_b(160), + sum => ex2_sum_b(160) , + car => ex2_car_b(159) ); + res_csa_161: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(161), + b => f_mul_ex2_sum_b(161), + c => f_mul_ex2_car_b(161), + sum => ex2_sum_b(161) , + car => ex2_car_b(160) ); + + ex2_sum_b(53) <= not f_alg_ex2_res(53) ; + ex2_sum_b(162) <= not f_alg_ex2_res(162) ; + ex2_car_b(161) <= tiup; + + + + + + ex3_000_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 53, btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd, + gd => gnd, + LCLK => sa3_ex3_lclk , + D1CLK => sa3_ex3_d1clk , + D2CLK => sa3_ex3_d2clk , + SCANIN => ex3_000_si , + SCANOUT => ex3_000_so , + D => ex2_alg_b(0 to 52) , + QB => ex3_sum(0 to 52) ); + + ex3_053_sum_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 110, btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd, + gd => gnd, + LCLK => sa3_ex3_lclk , + D1CLK => sa3_ex3_d1clk , + D2CLK => sa3_ex3_d2clk , + SCANIN => ex3_053_sum_si , + SCANOUT => ex3_053_sum_so , + D => ex2_sum_b(53 to 162) , + QB => ex3_sum(53 to 162) ); + + ex3_053_car_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 109, btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd, + gd => gnd, + LCLK => sa3_ex3_lclk , + D1CLK => sa3_ex3_d1clk , + D2CLK => sa3_ex3_d2clk , + SCANIN => ex3_053_car_si , + SCANOUT => ex3_053_car_so , + D => ex2_car_b(53 to 161) , + QB => ex3_car(53 to 161) ); + + + + + + inv_sum_lza: ex3_sum_lza_b(0 to 162) <= not ex3_sum(0 to 162) ; + inv_car_lza: ex3_car_lza_b(53 to 161) <= not ex3_car(53 to 161) ; + inv_sum_add: ex3_sum_add_b(0 to 162) <= not ex3_sum(0 to 162) ; + inv_car_add: ex3_car_add_b(53 to 161) <= not ex3_car(53 to 161) ; + + buf_sum_lza: f_sa3_ex3_s_lza(0 to 162) <= not ex3_sum_lza_b(0 to 162) ; + buf_car_lza: f_sa3_ex3_c_lza(53 to 161) <= not ex3_car_lza_b(53 to 161) ; + buf_sum_add: f_sa3_ex3_s_add(0 to 162) <= not ex3_sum_add_b(0 to 162) ; + buf_car_add: f_sa3_ex3_c_add(53 to 161) <= not ex3_car_add_b(53 to 161) ; + + + + + + + thold_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => thold_1, + q(0) => thold_0 ); + + sg_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => sg_1 , + q(0) => sg_0 ); + + + lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map ( + clkoff_b => clkoff_b, + thold => thold_0, + sg => sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => thold_0_b ); + + + ex1_act <= not ex1_act_b ; + + act_lat: tri_rlmreg_p generic map (width=> 5, expand_type => expand_type, needs_sreset => 0) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(2) , + mpw1_b => mpw1_b(2) , + mpw2_b => mpw2_b(0) , + vd => vdd, + gd => gnd, + nclk => nclk, + act => fpu_enable, + thold_b => thold_0_b, + sg => sg_0, + scout => act_so , + scin => act_si , + din(0) => act_spare_unused(0), + din(1) => act_spare_unused(1), + din(2) => ex1_act, + din(3) => act_spare_unused(2), + din(4) => act_spare_unused(3), + dout(0) => act_spare_unused(0), + dout(1) => act_spare_unused(1), + dout(2) => ex2_act, + dout(3) => act_spare_unused(2) , + dout(4) => act_spare_unused(3) ); + + sa3_ex3_lcb : tri_lcbnd generic map (expand_type => expand_type) port map( + delay_lclkr => delay_lclkr(3) , + mpw1_b => mpw1_b(3) , + mpw2_b => mpw2_b(0) , + forcee => forcee, + nclk => nclk , + vd => vdd , + gd => gnd , + act => ex2_act , + sg => sg_0 , + thold_b => thold_0_b , + d1clk => sa3_ex3_d1clk , + d2clk => sa3_ex3_d2clk , + lclk => sa3_ex3_lclk ); + + + + ex3_053_car_si(0 to 108) <= ex3_053_car_so(1 to 108) & f_sa3_si ; + ex3_053_sum_si(0 to 109) <= ex3_053_sum_so(1 to 109) & ex3_053_car_so(0); + ex3_000_si(0 to 52) <= ex3_000_so(1 to 52) & ex3_053_sum_so(0) ; + act_si(0 to 4) <= act_so (1 to 4) & ex3_000_so(0); + f_sa3_so <= act_so(0); + + +end; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_scr.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_scr.vhdl new file mode 100644 index 0000000..d105017 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_scr.vhdl @@ -0,0 +1,991 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + + + + + +ENTITY fuq_scr IS +generic( expand_type : integer := 2 ); +PORT( + + vdd :inout power_logic; + gnd :inout power_logic; + clkoff_b :in std_ulogic; + act_dis :in std_ulogic; + flush :in std_ulogic; + delay_lclkr :in std_ulogic_vector(4 to 7); + mpw1_b :in std_ulogic_vector(4 to 7); + mpw2_b :in std_ulogic_vector(0 to 1); + sg_1 :in std_ulogic; + thold_1 :in std_ulogic; + fpu_enable :in std_ulogic; + nclk :in clk_logic; + + + f_scr_si :in std_ulogic ; + f_scr_so :out std_ulogic ; + ex2_act_b :in std_ulogic ; + f_cr2_ex3_thread_b :in std_ulogic_vector(0 to 3) ; + f_pic_ex5_scr_upd_move_b :in std_ulogic ; + f_pic_ex5_scr_upd_pipe_b :in std_ulogic ; + f_dcd_ex6_cancel :in std_ulogic ; + + f_pic_ex5_fprf_spec_b :in std_ulogic_vector(0 to 4) ; + f_pic_ex5_compare_b :in std_ulogic ; + f_pic_ex5_fprf_pipe_v_b :in std_ulogic ; + f_pic_ex5_fprf_hold_b :in std_ulogic ; + f_pic_ex5_fi_spec_b :in std_ulogic ; + f_pic_ex5_fi_pipe_v_b :in std_ulogic ; + f_pic_ex5_fr_spec_b :in std_ulogic ; + f_pic_ex5_fr_pipe_v_b :in std_ulogic ; + f_pic_ex5_ox_spec_b :in std_ulogic ; + f_pic_ex5_ox_pipe_v_b :in std_ulogic ; + f_pic_ex5_ux_spec_b :in std_ulogic ; + f_pic_ex5_ux_pipe_v_b :in std_ulogic ; + + f_pic_ex5_flag_vxsnan_b :in std_ulogic ; + f_pic_ex5_flag_vxisi_b :in std_ulogic ; + f_pic_ex5_flag_vxidi_b :in std_ulogic ; + f_pic_ex5_flag_vxzdz_b :in std_ulogic ; + f_pic_ex5_flag_vximz_b :in std_ulogic ; + f_pic_ex5_flag_vxvc_b :in std_ulogic ; + f_pic_ex5_flag_vxsqrt_b :in std_ulogic ; + f_pic_ex5_flag_vxcvi_b :in std_ulogic ; + f_pic_ex5_flag_zx_b :in std_ulogic ; + + f_cr2_ex3_fpscr_bit_data_b :in std_ulogic_vector(0 to 3) ; + f_cr2_ex3_fpscr_bit_mask_b :in std_ulogic_vector(0 to 3) ; + f_cr2_ex3_fpscr_nib_mask_b :in std_ulogic_vector(0 to 8) ; + f_cr2_ex3_mcrfs_b :in std_ulogic ; + f_cr2_ex3_mtfsf_b :in std_ulogic ; + f_cr2_ex3_mtfsfi_b :in std_ulogic ; + f_cr2_ex3_mtfsbx_b :in std_ulogic ; + + + f_nrm_ex5_fpscr_wr_dat_dfp :in std_ulogic_vector(0 to 3) ; + f_scr_ex5_fpscr_rd_dat_dfp :out std_ulogic_vector(0 to 3) ; + + f_nrm_ex5_fpscr_wr_dat :in std_ulogic_vector(0 to 31) ; + + f_cr2_ex6_fpscr_rd_dat :in std_ulogic_vector(24 to 31) ; + f_cr2_ex5_fpscr_rd_dat :in std_ulogic_vector(24 to 31) ; + f_scr_ex5_fpscr_rd_dat :out std_ulogic_vector(0 to 31) ; + + f_rnd_ex6_flag_up :in std_ulogic ; + f_rnd_ex6_flag_fi :in std_ulogic ; + f_rnd_ex6_flag_ox :in std_ulogic ; + f_rnd_ex6_flag_den :in std_ulogic ; + f_rnd_ex6_flag_sgn :in std_ulogic ; + f_rnd_ex6_flag_inf :in std_ulogic ; + f_rnd_ex6_flag_zer :in std_ulogic ; + f_rnd_ex6_flag_ux :in std_ulogic ; + + f_scr_ex7_cr_fld :out std_ulogic_vector(0 to 3) ; + f_scr_ex7_fx_thread0 :out std_ulogic_vector(0 to 3) ; + f_scr_ex7_fx_thread1 :out std_ulogic_vector(0 to 3) ; + f_scr_ex7_fx_thread2 :out std_ulogic_vector(0 to 3) ; + f_scr_ex7_fx_thread3 :out std_ulogic_vector(0 to 3) + + +); + + + +end fuq_scr; + + +architecture fuq_scr of fuq_scr is + + constant tiup :std_ulogic := '1'; + constant tidn :std_ulogic := '0'; + + signal sg_0 :std_ulogic ; + signal thold_0_b , thold_0, forcee :std_ulogic ; + signal ex3_act :std_ulogic ; + signal ex2_act :std_ulogic ; + signal ex4_act :std_ulogic ; + signal ex5_act :std_ulogic ; + signal ex6_act :std_ulogic ; + signal ex6_th0_act :std_ulogic ; + signal ex6_th1_act :std_ulogic ; + signal ex6_th2_act :std_ulogic ; + signal ex6_th3_act :std_ulogic ; + signal ex6_th0_act_wocan :std_ulogic ; + signal ex6_th1_act_wocan :std_ulogic ; + signal ex6_th2_act_wocan :std_ulogic ; + signal ex6_th3_act_wocan :std_ulogic ; + signal act_spare_unused :std_ulogic_vector(0 to 3) ; + signal act_so :std_ulogic_vector(0 to 13) ; + signal act_si :std_ulogic_vector(0 to 13) ; + + signal ex4_ctl_so :std_ulogic_vector(0 to 24) ; + signal ex4_ctl_si :std_ulogic_vector(0 to 24) ; + signal ex5_ctl_so :std_ulogic_vector(0 to 24) ; + signal ex5_ctl_si :std_ulogic_vector(0 to 24) ; + signal ex6_ctl_so :std_ulogic_vector(0 to 24) ; + signal ex6_ctl_si :std_ulogic_vector(0 to 24) ; + + signal ex6_flag_so :std_ulogic_vector(0 to 24) ; + signal ex6_flag_si :std_ulogic_vector(0 to 24) ; + signal ex6_mvdat_so :std_ulogic_vector(0 to 27) ; + signal ex6_mvdat_si :std_ulogic_vector(0 to 27) ; + + signal fpscr_th0_so :std_ulogic_vector(0 to 27) ; + signal fpscr_th0_si :std_ulogic_vector(0 to 27) ; + signal fpscr_th1_so :std_ulogic_vector(0 to 27) ; + signal fpscr_th1_si :std_ulogic_vector(0 to 27) ; + signal fpscr_th2_so :std_ulogic_vector(0 to 27) ; + signal fpscr_th2_si :std_ulogic_vector(0 to 27) ; + signal fpscr_th3_so :std_ulogic_vector(0 to 27) ; + signal fpscr_th3_si :std_ulogic_vector(0 to 27) ; + + signal ex7_crf_so :std_ulogic_vector(0 to 3) ; + signal ex7_crf_si :std_ulogic_vector(0 to 3) ; + signal ex6_mrg :std_ulogic_vector(0 to 23) ; + signal ex6_mrg_dfp :std_ulogic_vector(0 to 3) ; + signal ex6_fpscr_dfp_din :std_ulogic_vector(0 to 3) ; + signal ex6_fpscr_din :std_ulogic_vector(0 to 23) ; + signal ex6_cr_fld , ex6_cr_fld_x :std_ulogic_vector(0 to 3) ; + signal ex6_fpscr_move :std_ulogic_vector(0 to 23) ; + signal ex6_fpscr_pipe :std_ulogic_vector(0 to 23) ; + signal ex6_fpscr_move_dfp :std_ulogic_vector(0 to 3) ; + signal ex6_fpscr_pipe_dfp :std_ulogic_vector(0 to 3) ; + + signal fpscr_dfp_th0 :std_ulogic_vector(0 to 3) ; + signal fpscr_dfp_th1 :std_ulogic_vector(0 to 3) ; + signal fpscr_dfp_th2 :std_ulogic_vector(0 to 3) ; + signal fpscr_dfp_th3 :std_ulogic_vector(0 to 3) ; + + signal fpscr_th0 :std_ulogic_vector(0 to 23) ; + signal fpscr_th1 :std_ulogic_vector(0 to 23) ; + signal fpscr_th2 :std_ulogic_vector(0 to 23) ; + signal fpscr_th3 :std_ulogic_vector(0 to 23) ; + + signal fpscr_rd_dat :std_ulogic_vector(0 to 31) ; + signal fpscr_rd_dat_dfp :std_ulogic_vector(0 to 3) ; + signal ex7_cr_fld :std_ulogic_vector(0 to 3) ; + signal ex6_fprf_pipe :std_ulogic_vector(0 to 4) ; + + signal ex4_thread :std_ulogic_vector(0 to 3) ; + signal ex5_thread :std_ulogic_vector(0 to 3) ; + signal ex6_thread :std_ulogic_vector(0 to 3) ; + + signal ex5_th0_act :std_ulogic ; + signal ex5_th1_act :std_ulogic ; + signal ex5_th2_act :std_ulogic ; + signal ex5_th3_act :std_ulogic ; + signal ex6_upd_move :std_ulogic ; + signal ex6_upd_pipe :std_ulogic ; + + signal ex6_fprf_spec :std_ulogic_vector(0 to 4) ; + signal ex6_compare :std_ulogic ; + signal ex6_fprf_pipe_v :std_ulogic ; + signal ex6_fprf_hold :std_ulogic ; + signal ex6_fi_spec :std_ulogic ; + signal ex6_fi_pipe_v :std_ulogic ; + signal ex6_fr_spec :std_ulogic ; + signal ex6_fr_pipe_v :std_ulogic ; + signal ex6_ox_spec :std_ulogic ; + signal ex6_ox_pipe_v :std_ulogic ; + signal ex6_ux_spec :std_ulogic ; + signal ex6_ux_pipe_v :std_ulogic ; + signal ex6_mv_data :std_ulogic_vector(0 to 23) ; + signal ex6_mv_data_dfp :std_ulogic_vector(0 to 3) ; + signal ex6_mv_sel :std_ulogic_vector(0 to 23) ; + signal ex6_mv_sel_dfp :std_ulogic_vector(0 to 3) ; + + signal ex6_flag_vxsnan :std_ulogic ; + signal ex6_flag_vxisi :std_ulogic ; + signal ex6_flag_vxidi :std_ulogic ; + signal ex6_flag_vxzdz :std_ulogic ; + signal ex6_flag_vximz :std_ulogic ; + signal ex6_flag_vxvc :std_ulogic ; + signal ex6_flag_vxsqrt :std_ulogic ; + signal ex6_flag_vxcvi :std_ulogic ; + signal ex6_flag_zx :std_ulogic ; + signal ex6_fpscr_wr_dat :std_ulogic_vector(0 to 23) ; + signal ex6_fpscr_wr_dat_dfp :std_ulogic_vector(0 to 3) ; + signal ex6_new_excp :std_ulogic ; + signal ex4_bit_data :std_ulogic_vector(0 to 3); + signal ex4_bit_mask :std_ulogic_vector(0 to 3); + signal ex4_nib_mask :std_ulogic_vector(0 to 8); + signal ex4_mcrfs :std_ulogic; + signal ex4_mtfsf :std_ulogic; + signal ex4_mtfsfi :std_ulogic; + signal ex4_mtfsbx :std_ulogic; + signal ex5_bit_data :std_ulogic_vector(0 to 3); + signal ex5_bit_mask :std_ulogic_vector(0 to 3); + signal ex5_nib_mask :std_ulogic_vector(0 to 8); + signal ex5_mcrfs :std_ulogic; + signal ex5_mtfsf :std_ulogic; + signal ex5_mtfsfi :std_ulogic; + signal ex5_mtfsbx :std_ulogic; + signal ex6_bit_data :std_ulogic_vector(0 to 3); + signal ex6_bit_mask :std_ulogic_vector(0 to 3); + signal ex6_nib_mask :std_ulogic_vector(0 to 8); + signal ex6_mcrfs :std_ulogic; + signal ex6_mtfsf :std_ulogic; + signal ex6_mtfsfi :std_ulogic; + signal ex6_mtfsbx :std_ulogic; + signal unused_stuff :std_ulogic; + signal ex5_scr_upd_move, ex5_scr_upd_pipe :std_ulogic ; + signal ex3_thread :std_ulogic_vector(0 to 3); + signal ex3_fpscr_bit_data :std_ulogic_vector(0 to 3); + signal ex3_fpscr_bit_mask :std_ulogic_vector(0 to 3); + signal ex3_fpscr_nib_mask :std_ulogic_vector(0 to 8); + signal ex3_mcrfs :std_ulogic ; + signal ex3_mtfsf :std_ulogic ; + signal ex3_mtfsfi :std_ulogic ; + signal ex3_mtfsbx :std_ulogic ; + signal ex5_flag_vxsnan :std_ulogic; + signal ex5_flag_vxisi :std_ulogic; + signal ex5_flag_vxidi :std_ulogic; + signal ex5_flag_vxzdz :std_ulogic; + signal ex5_flag_vximz :std_ulogic; + signal ex5_flag_vxvc :std_ulogic; + signal ex5_flag_vxsqrt :std_ulogic; + signal ex5_flag_vxcvi :std_ulogic; + signal ex5_flag_zx :std_ulogic; + signal ex5_fprf_spec :std_ulogic_vector(0 to 4); + signal ex5_compare :std_ulogic; + signal ex5_fprf_pipe_v :std_ulogic; + signal ex5_fprf_hold :std_ulogic; + signal ex5_fi_spec :std_ulogic; + signal ex5_fi_pipe_v :std_ulogic; + signal ex5_fr_spec :std_ulogic; + signal ex5_fr_pipe_v :std_ulogic; + signal ex5_ox_spec :std_ulogic; + signal ex5_ox_pipe_v :std_ulogic; + signal ex5_ux_spec :std_ulogic; + signal ex5_ux_pipe_v :std_ulogic; + signal ex6_upd_move_nmcrfs :std_ulogic; + + +begin + + + + thold_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => thold_1, + q(0) => thold_0 ); + + sg_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => sg_1 , + q(0) => sg_0 ); + + + lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map ( + clkoff_b => clkoff_b, + thold => thold_0, + sg => sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => thold_0_b ); + + + + + ex2_act <= not ex2_act_b ; + ex5_scr_upd_move <= not f_pic_ex5_scr_upd_move_b ; + ex5_scr_upd_pipe <= not f_pic_ex5_scr_upd_pipe_b ; + + + act_lat: tri_rlmreg_p generic map (width=> 14, expand_type => expand_type) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(6) , + mpw1_b => mpw1_b(6) , + mpw2_b => mpw2_b(1) , + vd => vdd, + gd => gnd, + nclk => nclk, + act => fpu_enable, + thold_b => thold_0_b, + sg => sg_0, + scout => act_so , + scin => act_si , + din(0) => act_spare_unused(0), + din(1) => act_spare_unused(1), + din(2) => ex2_act, + din(3) => ex3_act, + din(4) => ex4_act, + din(5) => ex5_act, + din(6) => ex5_th0_act , + din(7) => ex5_th1_act , + din(8) => ex5_th2_act , + din(9) => ex5_th3_act , + din(10) => ex5_scr_upd_move , + din(11) => ex5_scr_upd_pipe , + din(12) => act_spare_unused(2), + din(13) => act_spare_unused(3), + dout(0) => act_spare_unused(0), + dout(1) => act_spare_unused(1), + dout(2) => ex3_act, + dout(3) => ex4_act, + dout(4) => ex5_act, + dout(5) => ex6_act, + dout(6) => ex6_th0_act_wocan , + dout(7) => ex6_th1_act_wocan , + dout(8) => ex6_th2_act_wocan , + dout(9) => ex6_th3_act_wocan , + dout(10) => ex6_upd_move , + dout(11) => ex6_upd_pipe , + dout(12) => act_spare_unused(2) , + dout(13) => act_spare_unused(3) ); + + + ex5_th0_act <= ( ex5_thread(0) and ex5_act and ( ex5_scr_upd_move or ex5_scr_upd_pipe) ) ; + ex5_th1_act <= ( ex5_thread(1) and ex5_act and ( ex5_scr_upd_move or ex5_scr_upd_pipe) ) ; + ex5_th2_act <= ( ex5_thread(2) and ex5_act and ( ex5_scr_upd_move or ex5_scr_upd_pipe) ) ; + ex5_th3_act <= ( ex5_thread(3) and ex5_act and ( ex5_scr_upd_move or ex5_scr_upd_pipe) ) ; + + ex6_th0_act <= ex6_th0_act_wocan and not f_dcd_ex6_cancel; + ex6_th1_act <= ex6_th1_act_wocan and not f_dcd_ex6_cancel; + ex6_th2_act <= ex6_th2_act_wocan and not f_dcd_ex6_cancel; + ex6_th3_act <= ex6_th3_act_wocan and not f_dcd_ex6_cancel; + + + ex3_thread(0 to 3) <= not f_cr2_ex3_thread_b(0 to 3) ; + ex3_fpscr_bit_data(0 to 3) <= not f_cr2_ex3_fpscr_bit_data_b(0 to 3) ; + ex3_fpscr_bit_mask(0 to 3) <= not f_cr2_ex3_fpscr_bit_mask_b(0 to 3) ; + ex3_fpscr_nib_mask(0 to 8) <= not f_cr2_ex3_fpscr_nib_mask_b(0 to 8) ; + ex3_mcrfs <= not f_cr2_ex3_mcrfs_b ; + ex3_mtfsf <= not f_cr2_ex3_mtfsf_b ; + ex3_mtfsfi <= not f_cr2_ex3_mtfsfi_b ; + ex3_mtfsbx <= not f_cr2_ex3_mtfsbx_b ; + + + + ex4_ctl_lat: tri_rlmreg_p generic map (width=> 25, expand_type => expand_type) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(4) , + mpw1_b => mpw1_b(4) , + mpw2_b => mpw2_b(0) , + vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_act , + thold_b => thold_0_b, + sg => sg_0, + scout => ex4_ctl_so , + scin => ex4_ctl_si , + din(0 to 3) => ex3_thread(0 to 3) , + din(4 to 7) => ex3_fpscr_bit_data(0 to 3) , + din(8 to 11) => ex3_fpscr_bit_mask(0 to 3) , + din(12 to 20) => ex3_fpscr_nib_mask(0 to 8) , + din(21) => ex3_mcrfs , + din(22) => ex3_mtfsf , + din(23) => ex3_mtfsfi , + din(24) => ex3_mtfsbx , + dout(0 to 3) => ex4_thread(0 to 3) , + dout(4 to 7) => ex4_bit_data(0 to 3) , + dout(8 to 11) => ex4_bit_mask(0 to 3) , + dout(12 to 20) => ex4_nib_mask(0 to 8) , + dout(21) => ex4_mcrfs , + dout(22) => ex4_mtfsf , + dout(23) => ex4_mtfsfi , + dout(24) => ex4_mtfsbx ); + + + + + ex5_ctl_lat: tri_rlmreg_p generic map (width=> 25, expand_type => expand_type) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(5) , + mpw1_b => mpw1_b(5) , + mpw2_b => mpw2_b(1) , + vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_act , + thold_b => thold_0_b, + sg => sg_0, + scout => ex5_ctl_so , + scin => ex5_ctl_si , + din(0 to 3) => ex4_thread(0 to 3) , + din(4 to 7) => ex4_bit_data(0 to 3), + din(8 to 11) => ex4_bit_mask(0 to 3), + din(12 to 20) => ex4_nib_mask(0 to 8), + din(21) => ex4_mcrfs , + din(22) => ex4_mtfsf , + din(23) => ex4_mtfsfi , + din(24) => ex4_mtfsbx , + dout(0 to 3) => ex5_thread(0 to 3) , + dout(4 to 7) => ex5_bit_data(0 to 3) , + dout(8 to 11) => ex5_bit_mask(0 to 3) , + dout(12 to 20) => ex5_nib_mask(0 to 8) , + dout(21) => ex5_mcrfs , + dout(22) => ex5_mtfsf , + dout(23) => ex5_mtfsfi , + dout(24) => ex5_mtfsbx ); + + + + ex6_ctl_lat: tri_rlmreg_p generic map (width=> 25, expand_type => expand_type) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(6) , + mpw1_b => mpw1_b(6) , + mpw2_b => mpw2_b(1) , + vd => vdd, + gd => gnd, + nclk => nclk, + act => ex5_act, + thold_b => thold_0_b, + sg => sg_0, + scout => ex6_ctl_so , + scin => ex6_ctl_si , + din(0 to 3) => ex5_thread(0 to 3), + din(4 to 7) => ex5_bit_data(0 to 3), + din(8 to 11) => ex5_bit_mask(0 to 3), + din(12 to 20) => ex5_nib_mask(0 to 8), + din(21) => ex5_mcrfs , + din(22) => ex5_mtfsf , + din(23) => ex5_mtfsfi , + din(24) => ex5_mtfsbx , + dout(0 to 3) => ex6_thread(0 to 3) , + dout(4 to 7) => ex6_bit_data(0 to 3) , + dout(8 to 11) => ex6_bit_mask(0 to 3) , + dout(12 to 20) => ex6_nib_mask(0 to 8) , + dout(21) => ex6_mcrfs , + dout(22) => ex6_mtfsf , + dout(23) => ex6_mtfsfi , + dout(24) => ex6_mtfsbx ); + + + ex5_flag_vxsnan <= not f_pic_ex5_flag_vxsnan_b ; + ex5_flag_vxisi <= not f_pic_ex5_flag_vxisi_b ; + ex5_flag_vxidi <= not f_pic_ex5_flag_vxidi_b ; + ex5_flag_vxzdz <= not f_pic_ex5_flag_vxzdz_b ; + ex5_flag_vximz <= not f_pic_ex5_flag_vximz_b ; + ex5_flag_vxvc <= not f_pic_ex5_flag_vxvc_b ; + ex5_flag_vxsqrt <= not f_pic_ex5_flag_vxsqrt_b ; + ex5_flag_vxcvi <= not f_pic_ex5_flag_vxcvi_b ; + ex5_flag_zx <= not f_pic_ex5_flag_zx_b ; + ex5_fprf_spec(0 to 4) <= not f_pic_ex5_fprf_spec_b(0 to 4) ; + ex5_compare <= not f_pic_ex5_compare_b ; + ex5_fprf_pipe_v <= not f_pic_ex5_fprf_pipe_v_b ; + ex5_fprf_hold <= not f_pic_ex5_fprf_hold_b ; + ex5_fi_spec <= not f_pic_ex5_fi_spec_b ; + ex5_fi_pipe_v <= not f_pic_ex5_fi_pipe_v_b ; + ex5_fr_spec <= not f_pic_ex5_fr_spec_b ; + ex5_fr_pipe_v <= not f_pic_ex5_fr_pipe_v_b ; + ex5_ox_spec <= not f_pic_ex5_ox_spec_b ; + ex5_ox_pipe_v <= not f_pic_ex5_ox_pipe_v_b ; + ex5_ux_spec <= not f_pic_ex5_ux_spec_b ; + ex5_ux_pipe_v <= not f_pic_ex5_ux_pipe_v_b ; + + + ex6_flag_lat: tri_rlmreg_p generic map (width=> 25, expand_type => expand_type) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(6) , + mpw1_b => mpw1_b(6) , + mpw2_b => mpw2_b(1) , + vd => vdd, + gd => gnd, + nclk => nclk, + act => ex5_act, + thold_b => thold_0_b, + sg => sg_0, + scout => ex6_flag_so , + scin => ex6_flag_si , + din(0) => ex5_flag_vxsnan , + din(1) => ex5_flag_vxisi , + din(2) => ex5_flag_vxidi , + din(3) => ex5_flag_vxzdz , + din(4) => ex5_flag_vximz , + din(5) => ex5_flag_vxvc , + din(6) => ex5_flag_vxsqrt , + din(7) => ex5_flag_vxcvi , + din(8) => ex5_flag_zx , + din(9 to 13) => ex5_fprf_spec(0 to 4) , + din(14) => ex5_compare , + din(15) => ex5_fprf_pipe_v , + din(16) => ex5_fprf_hold , + din(17) => ex5_fi_spec , + din(18) => ex5_fi_pipe_v , + din(19) => ex5_fr_spec , + din(20) => ex5_fr_pipe_v , + din(21) => ex5_ox_spec , + din(22) => ex5_ox_pipe_v , + din(23) => ex5_ux_spec , + din(24) => ex5_ux_pipe_v , + dout(0) => ex6_flag_vxsnan , + dout(1) => ex6_flag_vxisi , + dout(2) => ex6_flag_vxidi , + dout(3) => ex6_flag_vxzdz , + dout(4) => ex6_flag_vximz , + dout(5) => ex6_flag_vxvc , + dout(6) => ex6_flag_vxsqrt , + dout(7) => ex6_flag_vxcvi , + dout(8) => ex6_flag_zx , + dout(9 to 13) => ex6_fprf_spec (0 to 4) , + dout(14) => ex6_compare , + dout(15) => ex6_fprf_pipe_v , + dout(16) => ex6_fprf_hold , + dout(17) => ex6_fi_spec , + dout(18) => ex6_fi_pipe_v , + dout(19) => ex6_fr_spec , + dout(20) => ex6_fr_pipe_v , + dout(21) => ex6_ox_spec , + dout(22) => ex6_ox_pipe_v , + dout(23) => ex6_ux_spec , + dout(24) => ex6_ux_pipe_v ); + + + ex6_mvdat_lat: tri_rlmreg_p generic map (width=> 28, expand_type => expand_type) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(6) , + mpw1_b => mpw1_b(6) , + mpw2_b => mpw2_b(1) , + vd => vdd, + gd => gnd, + nclk => nclk, + act => ex5_act, + thold_b => thold_0_b, + sg => sg_0, + scout => ex6_mvdat_so , + scin => ex6_mvdat_si , + din(0 to 3) => f_nrm_ex5_fpscr_wr_dat_dfp(0 to 3) , + din(4 to 27) => f_nrm_ex5_fpscr_wr_dat(0 to 23) , + dout(0 to 3) => ex6_fpscr_wr_dat_dfp(0 to 3) , + dout(4 to 27) => ex6_fpscr_wr_dat(0 to 23) ); + + + + + + + + ex6_cr_fld_x(0 to 3) <= + ( ex6_mrg( 0 to 3) and (0 to 3=> ex6_nib_mask(0) ) ) or + ( ex6_mrg( 4 to 7) and (0 to 3=> ex6_nib_mask(1) ) ) or + ( ex6_mrg( 8 to 11) and (0 to 3=> ex6_nib_mask(2) ) ) or + ( ex6_mrg(12 to 15) and (0 to 3=> ex6_nib_mask(3) ) ) or + ( ex6_mrg(16 to 19) and (0 to 3=> ex6_nib_mask(4) ) ) or + ( (tidn & ex6_mrg(21 to 23)) and (0 to 3=> ex6_nib_mask(5) ) ) or + ( f_cr2_ex6_fpscr_rd_dat(24 to 27) and (0 to 3=> ex6_nib_mask(6) ) ) or + ( f_cr2_ex6_fpscr_rd_dat(28 to 31) and (0 to 3=> ex6_nib_mask(7) ) ); + + ex6_upd_move_nmcrfs <= ex6_upd_move and not ex6_mcrfs ; + + ex6_cr_fld(0 to 3) <= + ( ex6_mrg(0 to 3) and (0 to 3 => not ex6_upd_move and not ex6_upd_pipe) ) or + ( ex6_cr_fld_x(0 to 3) and (0 to 3 => ex6_mcrfs ) ) or + ( ex6_fpscr_din(0 to 3) and (0 to 3 => ex6_upd_pipe ) ) or + ( ex6_fpscr_din(0 to 3) and (0 to 3 => ex6_upd_move_nmcrfs ) ) ; + + + + + ex6_mv_data_dfp(0 to 3) <= ( ex6_bit_data(0 to 3) and (0 to 3 => not ex6_mtfsf) ) or (ex6_fpscr_wr_dat_dfp(0 to 3) and (0 to 3 => ex6_mtfsf) ); + + ex6_mv_data( 0 to 3) <= ( ex6_bit_data(0 to 3) and (0 to 3 => not ex6_mtfsf) ) or (ex6_fpscr_wr_dat( 0 to 3) and (0 to 3 => ex6_mtfsf) ); + ex6_mv_data( 4 to 7) <= ( ex6_bit_data(0 to 3) and (0 to 3 => not ex6_mtfsf) ) or (ex6_fpscr_wr_dat( 4 to 7) and (0 to 3 => ex6_mtfsf) ); + ex6_mv_data( 8 to 11) <= ( ex6_bit_data(0 to 3) and (0 to 3 => not ex6_mtfsf) ) or (ex6_fpscr_wr_dat( 8 to 11) and (0 to 3 => ex6_mtfsf) ); + ex6_mv_data(12 to 15) <= ( ex6_bit_data(0 to 3) and (0 to 3 => not ex6_mtfsf) ) or (ex6_fpscr_wr_dat(12 to 15) and (0 to 3 => ex6_mtfsf) ); + ex6_mv_data(16 to 19) <= ( ex6_bit_data(0 to 3) and (0 to 3 => not ex6_mtfsf) ) or (ex6_fpscr_wr_dat(16 to 19) and (0 to 3 => ex6_mtfsf) ); + ex6_mv_data(20 to 23) <= ( ex6_bit_data(0 to 3) and (0 to 3 => not ex6_mtfsf) ) or (ex6_fpscr_wr_dat(20 to 23) and (0 to 3 => ex6_mtfsf) ); + + + ex6_mv_sel_dfp(0) <= ex6_bit_mask(0) and ex6_nib_mask(8) ; + ex6_mv_sel_dfp(1) <= ex6_bit_mask(1) and ex6_nib_mask(8) ; + ex6_mv_sel_dfp(2) <= ex6_bit_mask(2) and ex6_nib_mask(8) ; + ex6_mv_sel_dfp(3) <= ex6_bit_mask(3) and ex6_nib_mask(8) ; + + ex6_mv_sel( 0) <= ex6_bit_mask(0) and ex6_nib_mask(0) ; + ex6_mv_sel( 1) <= tidn; + ex6_mv_sel( 2) <= tidn; + ex6_mv_sel( 3) <= ex6_bit_mask(3) and ex6_nib_mask(0) ; + ex6_mv_sel( 4) <= ex6_bit_mask(0) and ex6_nib_mask(1) ; + ex6_mv_sel( 5) <= ex6_bit_mask(1) and ex6_nib_mask(1) ; + ex6_mv_sel( 6) <= ex6_bit_mask(2) and ex6_nib_mask(1) ; + ex6_mv_sel( 7) <= ex6_bit_mask(3) and ex6_nib_mask(1) ; + ex6_mv_sel( 8) <= ex6_bit_mask(0) and ex6_nib_mask(2) ; + ex6_mv_sel( 9) <= ex6_bit_mask(1) and ex6_nib_mask(2) ; + ex6_mv_sel(10) <= ex6_bit_mask(2) and ex6_nib_mask(2) ; + ex6_mv_sel(11) <= ex6_bit_mask(3) and ex6_nib_mask(2) ; + ex6_mv_sel(12) <= ex6_bit_mask(0) and ex6_nib_mask(3) ; + ex6_mv_sel(13) <= ex6_bit_mask(1) and ex6_nib_mask(3) and not ex6_mcrfs; + ex6_mv_sel(14) <= ex6_bit_mask(2) and ex6_nib_mask(3) and not ex6_mcrfs; + ex6_mv_sel(15) <= ex6_bit_mask(3) and ex6_nib_mask(3) and not ex6_mcrfs; + ex6_mv_sel(16) <= ex6_bit_mask(0) and ex6_nib_mask(4) and not ex6_mcrfs; + ex6_mv_sel(17) <= ex6_bit_mask(1) and ex6_nib_mask(4) and not ex6_mcrfs; + ex6_mv_sel(18) <= ex6_bit_mask(2) and ex6_nib_mask(4) and not ex6_mcrfs; + ex6_mv_sel(19) <= ex6_bit_mask(3) and ex6_nib_mask(4) and not ex6_mcrfs; + ex6_mv_sel(20) <= ex6_bit_mask(0) and ex6_nib_mask(5) and not ex6_mcrfs; + ex6_mv_sel(21) <= ex6_bit_mask(1) and ex6_nib_mask(5) ; + ex6_mv_sel(22) <= ex6_bit_mask(2) and ex6_nib_mask(5) ; + ex6_mv_sel(23) <= ex6_bit_mask(3) and ex6_nib_mask(5) ; + + ex6_fpscr_move( 0) <= (ex6_mrg( 0) and not ex6_mv_sel( 0)) or (ex6_mv_data(0) and ex6_mv_sel( 0) ); + ex6_fpscr_move( 1) <= tidn; + ex6_fpscr_move( 2) <= tidn; + ex6_fpscr_move( 3 to 23) <= + ( ex6_mrg(3 to 23) and not ex6_mv_sel(3 to 23) ) or + ( ex6_mv_data(3 to 23) and ex6_mv_sel(3 to 23) ) ; + + ex6_fpscr_move_dfp(0 to 3) <= + ( ex6_mrg_dfp(0 to 3) and not ex6_mv_sel_dfp(0 to 3) ) or + ( ex6_mv_data_dfp(0 to 3) and ex6_mv_sel_dfp(0 to 3) ) ; + + + ex6_fprf_pipe(0) <= ( f_rnd_ex6_flag_sgn and f_rnd_ex6_flag_zer) or + ( f_rnd_ex6_flag_den and not f_rnd_ex6_flag_zer) ; + + ex6_fprf_pipe(1) <= ( f_rnd_ex6_flag_sgn and not f_rnd_ex6_flag_zer); + ex6_fprf_pipe(2) <= (not f_rnd_ex6_flag_sgn and not f_rnd_ex6_flag_zer); + ex6_fprf_pipe(3) <= f_rnd_ex6_flag_zer; + ex6_fprf_pipe(4) <= f_rnd_ex6_flag_inf ; + + + ex6_fpscr_pipe( 0) <= ex6_mrg( 0) ; + ex6_fpscr_pipe( 1) <= tidn ; + ex6_fpscr_pipe( 2) <= tidn ; + ex6_fpscr_pipe( 3) <= ex6_mrg( 3) or + ex6_ox_spec or + (ex6_ox_pipe_v and f_rnd_ex6_flag_ox ); + ex6_fpscr_pipe( 4) <= ex6_mrg( 4) or + ex6_ux_spec or + (ex6_ux_pipe_v and f_rnd_ex6_flag_ux ); + ex6_fpscr_pipe( 5) <= ex6_mrg( 5) or ex6_flag_zx ; + + ex6_fpscr_pipe( 6) <= (ex6_mrg( 6) ) or + (ex6_fi_spec ) or + (ex6_fi_pipe_v and f_rnd_ex6_flag_fi ); + + ex6_fpscr_pipe( 7) <= ex6_mrg( 7) or ex6_flag_vxsnan ; + ex6_fpscr_pipe( 8) <= ex6_mrg( 8) or ex6_flag_vxisi ; + ex6_fpscr_pipe( 9) <= ex6_mrg( 9) or ex6_flag_vxidi ; + ex6_fpscr_pipe(10) <= ex6_mrg(10) or ex6_flag_vxzdz ; + ex6_fpscr_pipe(11) <= ex6_mrg(11) or ex6_flag_vximz ; + ex6_fpscr_pipe(12) <= ex6_mrg(12) or ex6_flag_vxvc ; + + + ex6_fpscr_pipe(13) <= + (ex6_mrg(13) and ex6_compare ) or + (ex6_fr_spec ) or + (ex6_fr_pipe_v and f_rnd_ex6_flag_up ); + ex6_fpscr_pipe(14) <= + (ex6_mrg(14) and ex6_compare ) or + (ex6_fi_spec ) or + (ex6_fi_pipe_v and f_rnd_ex6_flag_fi ); + + + + ex6_fpscr_pipe(15) <= + (ex6_mrg(15) and ex6_fprf_hold ) or + (ex6_mrg(15) and ex6_compare ) or + (ex6_fprf_spec(0) ) or + (ex6_fprf_pipe_v and ex6_fprf_pipe(0) ) ; + + + ex6_fpscr_pipe(16) <= + (ex6_mrg(16) and ex6_fprf_hold ) or + (ex6_fprf_spec(1) ) or + (ex6_fprf_pipe_v and ex6_fprf_pipe(1) ) ; + ex6_fpscr_pipe(17) <= + (ex6_mrg(17) and ex6_fprf_hold ) or + (ex6_fprf_spec(2) ) or + (ex6_fprf_pipe_v and ex6_fprf_pipe(2) ) ; + ex6_fpscr_pipe(18) <= + (ex6_mrg(18) and ex6_fprf_hold ) or + (ex6_fprf_spec(3) ) or + (ex6_fprf_pipe_v and ex6_fprf_pipe(3) ) ; + ex6_fpscr_pipe(19) <= + (ex6_mrg(19) and ex6_fprf_hold ) or + (ex6_fprf_spec(4) ) or + (ex6_fprf_pipe_v and ex6_fprf_pipe(4) ) ; + + ex6_fpscr_pipe(20) <= tidn ; + ex6_fpscr_pipe(21) <= ex6_mrg(21) ; + ex6_fpscr_pipe(22) <= ex6_mrg(22) or ex6_flag_vxsqrt ; + ex6_fpscr_pipe(23) <= ex6_mrg(23) or ex6_flag_vxcvi ; + + ex6_fpscr_pipe_dfp(0 to 3) <= ex6_mrg_dfp(0 to 3); + + + + + ex6_fpscr_dfp_din(0) <= (ex6_fpscr_move_dfp(0) and ex6_upd_move) or (ex6_fpscr_pipe_dfp(0) and ex6_upd_pipe) ; + ex6_fpscr_dfp_din(1) <= (ex6_fpscr_move_dfp(1) and ex6_upd_move) or (ex6_fpscr_pipe_dfp(1) and ex6_upd_pipe) ; + ex6_fpscr_dfp_din(2) <= (ex6_fpscr_move_dfp(2) and ex6_upd_move) or (ex6_fpscr_pipe_dfp(2) and ex6_upd_pipe) ; + ex6_fpscr_dfp_din(3) <= (ex6_fpscr_move_dfp(3) and ex6_upd_move) or (ex6_fpscr_pipe_dfp(3) and ex6_upd_pipe) ; + + + ex6_fpscr_din(23) <= (ex6_fpscr_move(23) and ex6_upd_move) or (ex6_fpscr_pipe(23) and ex6_upd_pipe) ; + ex6_fpscr_din(22) <= (ex6_fpscr_move(22) and ex6_upd_move) or (ex6_fpscr_pipe(22) and ex6_upd_pipe) ; + ex6_fpscr_din(21) <= (ex6_fpscr_move(21) and ex6_upd_move) or (ex6_fpscr_pipe(21) and ex6_upd_pipe) ; + ex6_fpscr_din(20) <= tidn; + ex6_fpscr_din(19) <= (ex6_fpscr_move(19) and ex6_upd_move) or (ex6_fpscr_pipe(19) and ex6_upd_pipe) ; + ex6_fpscr_din(18) <= (ex6_fpscr_move(18) and ex6_upd_move) or (ex6_fpscr_pipe(18) and ex6_upd_pipe) ; + ex6_fpscr_din(17) <= (ex6_fpscr_move(17) and ex6_upd_move) or (ex6_fpscr_pipe(17) and ex6_upd_pipe) ; + ex6_fpscr_din(16) <= (ex6_fpscr_move(16) and ex6_upd_move) or (ex6_fpscr_pipe(16) and ex6_upd_pipe) ; + ex6_fpscr_din(15) <= (ex6_fpscr_move(15) and ex6_upd_move) or (ex6_fpscr_pipe(15) and ex6_upd_pipe) ; + ex6_fpscr_din(14) <= (ex6_fpscr_move(14) and ex6_upd_move) or (ex6_fpscr_pipe(14) and ex6_upd_pipe) ; + ex6_fpscr_din(13) <= (ex6_fpscr_move(13) and ex6_upd_move) or (ex6_fpscr_pipe(13) and ex6_upd_pipe) ; + ex6_fpscr_din(12) <= (ex6_fpscr_move(12) and ex6_upd_move) or (ex6_fpscr_pipe(12) and ex6_upd_pipe) ; + ex6_fpscr_din(11) <= (ex6_fpscr_move(11) and ex6_upd_move) or (ex6_fpscr_pipe(11) and ex6_upd_pipe) ; + ex6_fpscr_din(10) <= (ex6_fpscr_move(10) and ex6_upd_move) or (ex6_fpscr_pipe(10) and ex6_upd_pipe) ; + ex6_fpscr_din( 9) <= (ex6_fpscr_move( 9) and ex6_upd_move) or (ex6_fpscr_pipe( 9) and ex6_upd_pipe) ; + ex6_fpscr_din( 8) <= (ex6_fpscr_move( 8) and ex6_upd_move) or (ex6_fpscr_pipe( 8) and ex6_upd_pipe) ; + ex6_fpscr_din( 7) <= (ex6_fpscr_move( 7) and ex6_upd_move) or (ex6_fpscr_pipe( 7) and ex6_upd_pipe) ; + ex6_fpscr_din( 6) <= (ex6_fpscr_move( 6) and ex6_upd_move) or (ex6_fpscr_pipe( 6) and ex6_upd_pipe) ; + ex6_fpscr_din( 5) <= (ex6_fpscr_move( 5) and ex6_upd_move) or (ex6_fpscr_pipe( 5) and ex6_upd_pipe) ; + ex6_fpscr_din( 4) <= (ex6_fpscr_move( 4) and ex6_upd_move) or (ex6_fpscr_pipe( 4) and ex6_upd_pipe) ; + ex6_fpscr_din( 3) <= (ex6_fpscr_move( 3) and ex6_upd_move) or (ex6_fpscr_pipe( 3) and ex6_upd_pipe) ; + + ex6_fpscr_din(2) <= + ex6_fpscr_din(7) or + ex6_fpscr_din(8) or + ex6_fpscr_din(9) or + ex6_fpscr_din(10) or + ex6_fpscr_din(11) or + ex6_fpscr_din(12) or + ex6_fpscr_din(21) or + ex6_fpscr_din(22) or + ex6_fpscr_din(23) ; + + ex6_fpscr_din(1) <= + ( ex6_fpscr_din(2) and f_cr2_ex6_fpscr_rd_dat(24) ) or + ( ex6_fpscr_din(3) and f_cr2_ex6_fpscr_rd_dat(25) ) or + ( ex6_fpscr_din(4) and f_cr2_ex6_fpscr_rd_dat(26) ) or + ( ex6_fpscr_din(5) and f_cr2_ex6_fpscr_rd_dat(27) ) or + ( ex6_fpscr_din(6) and f_cr2_ex6_fpscr_rd_dat(28) ) ; + + ex6_fpscr_din( 0) <= + (ex6_fpscr_move( 0) and ex6_upd_move) or + (ex6_fpscr_pipe( 0) and ex6_upd_pipe) or + (ex6_new_excp and not ex6_mtfsf and not ex6_mtfsfi ); + + ex6_new_excp <= + (not ex6_mrg( 3) and ex6_fpscr_din( 3) ) or + (not ex6_mrg( 4) and ex6_fpscr_din( 4) ) or + (not ex6_mrg( 5) and ex6_fpscr_din( 5) ) or + (not ex6_mrg( 6) and ex6_fpscr_din( 6) ) or + (not ex6_mrg( 7) and ex6_fpscr_din( 7) ) or + (not ex6_mrg( 8) and ex6_fpscr_din( 8) ) or + (not ex6_mrg( 9) and ex6_fpscr_din( 9) ) or + (not ex6_mrg(10) and ex6_fpscr_din(10) ) or + (not ex6_mrg(11) and ex6_fpscr_din(11) ) or + (not ex6_mrg(12) and ex6_fpscr_din(12) ) or + (not ex6_mrg(21) and ex6_fpscr_din(21) ) or + (not ex6_mrg(22) and ex6_fpscr_din(22) ) or + (not ex6_mrg(23) and ex6_fpscr_din(23) ) ; + + + + + + fpscr_th0_lat: tri_rlmreg_p generic map (width=> 28, expand_type => expand_type) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(7) , + mpw1_b => mpw1_b(7) , + mpw2_b => mpw2_b(1) , + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => ex6_th0_act, + scout => fpscr_th0_so , + scin => fpscr_th0_si , + din(0 to 3) => ex6_fpscr_dfp_din(0 to 3), + din(4 to 27) => ex6_fpscr_din(0 to 23), + dout(0 to 3) => fpscr_dfp_th0(0 to 3) , + dout(4 to 27) => fpscr_th0(0 to 23) ); + + fpscr_th1_lat: tri_rlmreg_p generic map (width=> 28, expand_type => expand_type) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(7) , + mpw1_b => mpw1_b(7) , + mpw2_b => mpw2_b(1) , + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => ex6_th1_act, + scout => fpscr_th1_so , + scin => fpscr_th1_si , + din(0 to 3) => ex6_fpscr_dfp_din(0 to 3), + din(4 to 27) => ex6_fpscr_din(0 to 23), + dout(0 to 3) => fpscr_dfp_th1(0 to 3) , + dout(4 to 27) => fpscr_th1(0 to 23) ); + + fpscr_th2_lat: tri_rlmreg_p generic map (width=> 28, expand_type => expand_type) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(7) , + mpw1_b => mpw1_b(7) , + mpw2_b => mpw2_b(1) , + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => ex6_th2_act, + scout => fpscr_th2_so , + scin => fpscr_th2_si , + din(0 to 3) => ex6_fpscr_dfp_din(0 to 3), + din(4 to 27) => ex6_fpscr_din(0 to 23), + dout(0 to 3) => fpscr_dfp_th2(0 to 3) , + dout(4 to 27) => fpscr_th2(0 to 23) ); + + fpscr_th3_lat: tri_rlmreg_p generic map (width=> 28, expand_type => expand_type) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(7) , + mpw1_b => mpw1_b(7) , + mpw2_b => mpw2_b(1) , + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => ex6_th3_act, + scout => fpscr_th3_so , + scin => fpscr_th3_si , + din(0 to 3) => ex6_fpscr_dfp_din(0 to 3), + din(4 to 27) => ex6_fpscr_din(0 to 23), + dout(0 to 3) => fpscr_dfp_th3(0 to 3) , + dout(4 to 27) => fpscr_th3(0 to 23) ); + + + ex7_crf_lat: tri_rlmreg_p generic map (width=> 4, expand_type => expand_type) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(7) , + mpw1_b => mpw1_b(7) , + mpw2_b => mpw2_b(1) , + vd => vdd, + gd => gnd, + nclk => nclk, + act => ex6_act, + thold_b => thold_0_b, + sg => sg_0, + scout => ex7_crf_so , + scin => ex7_crf_si , + din => ex6_cr_fld(0 to 3), + dout => ex7_cr_fld(0 to 3) ); + + + f_scr_ex7_cr_fld(0 to 3) <= ex7_cr_fld(0 to 3) ; + f_scr_ex7_fx_thread0(0 to 3) <= fpscr_th0(0 to 3) ; + f_scr_ex7_fx_thread1(0 to 3) <= fpscr_th1(0 to 3) ; + f_scr_ex7_fx_thread2(0 to 3) <= fpscr_th2(0 to 3) ; + f_scr_ex7_fx_thread3(0 to 3) <= fpscr_th3(0 to 3) ; + + + fpscr_rd_dat_dfp(0 to 3) <= + ( fpscr_dfp_th0(0 to 3) and (0 to 3 => ex5_thread(0) ) ) or + ( fpscr_dfp_th1(0 to 3) and (0 to 3 => ex5_thread(1) ) ) or + ( fpscr_dfp_th2(0 to 3) and (0 to 3 => ex5_thread(2) ) ) or + ( fpscr_dfp_th3(0 to 3) and (0 to 3 => ex5_thread(3) ) ) ; + + fpscr_rd_dat(0 to 23) <= + ( fpscr_th0(0 to 23) and (0 to 23 => ex5_thread(0) ) ) or + ( fpscr_th1(0 to 23) and (0 to 23 => ex5_thread(1) ) ) or + ( fpscr_th2(0 to 23) and (0 to 23 => ex5_thread(2) ) ) or + ( fpscr_th3(0 to 23) and (0 to 23 => ex5_thread(3) ) ) ; + + ex6_mrg_dfp(0 to 3) <= + ( fpscr_dfp_th0(0 to 3) and (0 to 3 => ex6_thread(0) ) ) or + ( fpscr_dfp_th1(0 to 3) and (0 to 3 => ex6_thread(1) ) ) or + ( fpscr_dfp_th2(0 to 3) and (0 to 3 => ex6_thread(2) ) ) or + ( fpscr_dfp_th3(0 to 3) and (0 to 3 => ex6_thread(3) ) ) ; + + ex6_mrg(0 to 23) <= + ( fpscr_th0(0 to 23) and (0 to 23 => ex6_thread(0) ) ) or + ( fpscr_th1(0 to 23) and (0 to 23 => ex6_thread(1) ) ) or + ( fpscr_th2(0 to 23) and (0 to 23 => ex6_thread(2) ) ) or + ( fpscr_th3(0 to 23) and (0 to 23 => ex6_thread(3) ) ) ; + + + + fpscr_rd_dat (24 to 31) <= f_cr2_ex5_fpscr_rd_dat(24 to 31) ; + f_scr_ex5_fpscr_rd_dat(0 to 31) <= fpscr_rd_dat(0 to 31) ; + f_scr_ex5_fpscr_rd_dat_dfp(0 to 3) <= fpscr_rd_dat_dfp(0 to 3) ; + + + + ex4_ctl_si (0 to 24) <= ex4_ctl_so (1 to 24) & f_scr_si; + ex5_ctl_si (0 to 24) <= ex5_ctl_so (1 to 24) & ex4_ctl_so (0); + ex6_ctl_si (0 to 24) <= ex6_ctl_so (1 to 24) & ex5_ctl_so (0); + ex6_flag_si (0 to 24) <= ex6_flag_so (1 to 24) & ex6_ctl_so (0); + ex6_mvdat_si (0 to 27) <= ex6_mvdat_so (1 to 27) & ex6_flag_so (0) ; + fpscr_th0_si (0 to 27) <= fpscr_th0_so (1 to 27) & ex6_mvdat_so (0) ; + fpscr_th1_si (0 to 27) <= fpscr_th1_so (1 to 27) & fpscr_th0_so (0) ; + fpscr_th2_si (0 to 27) <= fpscr_th2_so (1 to 27) & fpscr_th1_so (0) ; + fpscr_th3_si (0 to 27) <= fpscr_th3_so (1 to 27) & fpscr_th2_so (0) ; + ex7_crf_si (0 to 3) <= ex7_crf_so (1 to 3) & fpscr_th3_so (0) ; + act_si (0 to 13) <= act_so (1 to 13) & ex7_crf_so (0) ; + f_scr_so <= act_so (0) ; + + + unused_stuff <= + or_reduce( f_nrm_ex5_fpscr_wr_dat(24 to 31) ) or + ex6_mtfsbx or + ex6_fpscr_move(1) or + ex6_fpscr_move(2) or + ex6_fpscr_move(20) or + ex6_fpscr_pipe(1) or + ex6_fpscr_pipe(2) or + ex6_fpscr_pipe(20) or + ex6_mv_data(1) or + ex6_mv_data(2) or + ex6_mv_sel(1) or + ex6_mv_sel(2) ; + +end; + + + + + + + + + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_sto.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_sto.vhdl new file mode 100644 index 0000000..d6c55eb --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_sto.vhdl @@ -0,0 +1,765 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + + + + +ENTITY fuq_sto IS +generic( + expand_type : integer := 2 ); +PORT( + vdd :inout power_logic; + gnd :inout power_logic; + clkoff_b :in std_ulogic; + act_dis :in std_ulogic; + flush :in std_ulogic; + delay_lclkr :in std_ulogic_vector(1 to 2); + mpw1_b :in std_ulogic_vector(1 to 2); + mpw2_b :in std_ulogic_vector(0 to 0); + sg_1 :in std_ulogic; + thold_1 :in std_ulogic; + fpu_enable :in std_ulogic; + nclk :in clk_logic; + + f_sto_si :in std_ulogic; + f_sto_so :out std_ulogic; + f_dcd_rf1_sto_act :in std_ulogic; + + f_fpr_ex1_s_expo_extra :in std_ulogic ; + f_fpr_ex1_s_par :in std_ulogic_vector(0 to 7) ; + f_sto_ex2_s_parity_check :out std_ulogic ; + + f_dcd_rf1_sto_dp :in std_ulogic ; + f_dcd_rf1_sto_sp :in std_ulogic ; + f_dcd_rf1_sto_wd :in std_ulogic ; + + f_byp_rf1_s_sign :in std_ulogic ; + f_byp_rf1_s_expo :in std_ulogic_vector(1 to 11) ; + f_byp_rf1_s_frac :in std_ulogic_vector(0 to 52) ; + + f_sto_ex2_sto_data :out std_ulogic_vector(0 to 63) + +); + + + +end fuq_sto; + + +architecture fuq_sto of fuq_sto is + + constant tiup :std_ulogic := '1'; + constant tidn :std_ulogic := '0'; + + signal sg_0 :std_ulogic ; + signal thold_0_b, thold_0 :std_ulogic ; + + signal rf1_act :std_ulogic ; + signal ex1_act :std_ulogic ; + signal spare_unused :std_ulogic_vector(0 to 2) ; + signal act_so :std_ulogic_vector(0 to 3) ; + signal act_si :std_ulogic_vector(0 to 3) ; + signal ex1_sins_so :std_ulogic_vector(0 to 2) ; + signal ex1_sins_si :std_ulogic_vector(0 to 2) ; + signal ex1_sop_so :std_ulogic_vector(0 to 64) ; + signal ex1_sop_si :std_ulogic_vector(0 to 64) ; + signal ex2_sto_so :std_ulogic_vector(0 to 72) ; + signal ex2_sto_si :std_ulogic_vector(0 to 72) ; + signal ex1_s_sign :std_ulogic; + signal ex1_s_expo :std_ulogic_vector(1 to 11); + signal ex1_s_frac :std_ulogic_vector(0 to 52); + signal ex1_sto_data :std_ulogic_vector(0 to 63) ; + signal ex2_sto_data :std_ulogic_vector(0 to 63) ; + signal ex1_sto_dp :std_ulogic ; + signal ex1_sto_sp :std_ulogic ; + signal ex1_sto_wd :std_ulogic ; + signal ex1_den_ramt8_02 :std_ulogic; + signal ex1_den_ramt8_18 :std_ulogic; + signal ex1_den_ramt4_12 :std_ulogic; + signal ex1_den_ramt4_08 :std_ulogic; + signal ex1_den_ramt4_04 :std_ulogic; + signal ex1_den_ramt4_00 :std_ulogic; + signal ex1_den_ramt1_03 :std_ulogic; + signal ex1_den_ramt1_02 :std_ulogic; + signal ex1_den_ramt1_01 :std_ulogic; + signal ex1_den_ramt1_00 :std_ulogic; + signal ex1_expo_eq896 :std_ulogic; + signal ex1_expo_ge896 :std_ulogic; + signal ex1_expo_lt896 :std_ulogic; + signal ex1_sts_lt896 :std_ulogic; + signal ex1_sts_ge896 :std_ulogic; + signal ex1_sts_expo_nz :std_ulogic; + signal ex1_fixden :std_ulogic; + signal ex1_fixden_small :std_ulogic; + signal ex1_fixden_big :std_ulogic; + signal ex1_std_nonden :std_ulogic; + signal ex1_std_fixden_big :std_ulogic; + signal ex1_std_fixden_small :std_ulogic; + signal ex1_std_nonbig :std_ulogic; + signal ex1_std_nonden_wd :std_ulogic; + signal ex1_std_lamt8_02 :std_ulogic; + signal ex1_std_lamt8_10 :std_ulogic; + signal ex1_std_lamt8_18 :std_ulogic; + signal ex1_std_lamt2_0 :std_ulogic; + signal ex1_std_lamt2_2 :std_ulogic; + signal ex1_std_lamt2_4 :std_ulogic; + signal ex1_std_lamt2_6 :std_ulogic; + signal ex1_std_lamt1_0 :std_ulogic; + signal ex1_std_lamt1_1 :std_ulogic; + signal ex1_sts_sh8 :std_ulogic_vector(0 to 23) ; + signal ex1_sts_sh4 :std_ulogic_vector(0 to 23) ; + signal ex1_sts_sh1 :std_ulogic_vector(0 to 23) ; + signal ex1_sts_nrm :std_ulogic_vector(0 to 23) ; + signal ex1_sts_frac :std_ulogic_vector(1 to 23) ; + signal ex1_sts_expo :std_ulogic_vector(1 to 8) ; + signal ex1_clz02_or :std_ulogic_vector(0 to 10) ; + signal ex1_clz02_enc4 :std_ulogic_vector(0 to 10) ; + signal ex1_clz04_or :std_ulogic_vector(0 to 5) ; + signal ex1_clz04_enc3 :std_ulogic_vector(0 to 5) ; + signal ex1_clz04_enc4 :std_ulogic_vector(0 to 5) ; + signal ex1_clz08_or :std_ulogic_vector(0 to 2) ; + signal ex1_clz08_enc2 :std_ulogic_vector(0 to 2) ; + signal ex1_clz08_enc3 :std_ulogic_vector(0 to 2) ; + signal ex1_clz08_enc4 :std_ulogic_vector(0 to 2) ; + signal ex1_clz16_or :std_ulogic_vector(0 to 1) ; + signal ex1_clz16_enc1 :std_ulogic_vector(0 to 1) ; + signal ex1_clz16_enc2 :std_ulogic_vector(0 to 1) ; + signal ex1_clz16_enc3 :std_ulogic_vector(0 to 1) ; + signal ex1_clz16_enc4 :std_ulogic_vector(0 to 1) ; + signal ex1_sto_clz :std_ulogic_vector(0 to 4) ; + signal ex1_expo_nonden :std_ulogic_vector(1 to 11) ; + signal ex1_expo_fixden :std_ulogic_vector(1 to 11) ; + signal ex1_std_expo :std_ulogic_vector(1 to 11) ; + signal ex1_std_frac_nrm :std_ulogic_vector(1 to 52) ; + signal ex1_std_sh8 :std_ulogic_vector(0 to 23) ; + signal ex1_std_sh2 :std_ulogic_vector(0 to 23) ; + signal ex1_std_frac_den :std_ulogic_vector(1 to 23) ; + signal ex1_ge874 :std_ulogic; + signal ex1_any_edge :std_ulogic; + signal ex2_sto_data_rot0_b , ex2_sto_data_rot1_b :std_ulogic_vector(0 to 63); + + signal ex2_sto_wd, ex2_sto_sp :std_ulogic_vector(0 to 3); + signal forcee :std_ulogic; + + + signal ex1_s_party_chick, ex2_s_party_chick :std_ulogic ; + signal ex1_s_party : std_ulogic_vector(0 to 7); + signal unused :std_ulogic; + + + + + +begin + + + + + unused <= ex1_sts_sh1(0) or ex1_sts_nrm(0) or ex1_std_sh2(0) ; + + thold_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => thold_1, + q(0) => thold_0 ); + + sg_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => sg_1 , + q(0) => sg_0 ); + + + lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map ( + clkoff_b => clkoff_b, + thold => thold_0, + sg => sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => thold_0_b ); + + + + + rf1_act <= f_dcd_rf1_sto_act; + + act_lat: tri_rlmreg_p generic map (width=> 4, expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + forcee => forcee, + delay_lclkr => delay_lclkr(1), + mpw1_b => mpw1_b(1), + mpw2_b => mpw2_b(0), + act => fpu_enable, + thold_b => thold_0_b, + sg => sg_0, + scout => act_so , + scin => act_si , + din(0) => rf1_act, + din(1 to 3) => spare_unused(0 to 2) , + dout(0) => ex1_act , + dout(1 to 3) => spare_unused(0 to 2) ); + + + + ex1_sins_lat: entity tri.tri_rlmreg_p generic map (width=> 3, expand_type => expand_type, ibuf => true ) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(1) , + mpw1_b => mpw1_b(1) , + mpw2_b => mpw2_b(0) , + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => rf1_act, + vd => vdd, + gd => gnd, + scout => ex1_sins_so , + scin => ex1_sins_si , + din(0) => f_dcd_rf1_sto_dp , + din(1) => f_dcd_rf1_sto_sp , + din(2) => f_dcd_rf1_sto_wd , + dout(0) => ex1_sto_dp , + dout(1) => ex1_sto_sp , + dout(2) => ex1_sto_wd ); + + ex1_sop_lat: entity tri.tri_rlmreg_p generic map (width=> 65, expand_type => expand_type, needs_sreset => 0, ibuf => true) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(1) , + mpw1_b => mpw1_b(1) , + mpw2_b => mpw2_b(0) , + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => rf1_act, + vd => vdd, + gd => gnd, + scout => ex1_sop_so , + scin => ex1_sop_si , + din(0) => f_byp_rf1_s_sign , + din(1 to 11) => f_byp_rf1_s_expo(1 to 11) , + din(12 to 64) => f_byp_rf1_s_frac(0 to 52) , + dout(0) => ex1_s_sign , + dout(1 to 11) => ex1_s_expo(1 to 11), + dout(12 to 64) => ex1_s_frac(0 to 52) ); + + + + + + + ex1_den_ramt8_02 <= ex1_s_expo(6) and ex1_s_expo(7); + ex1_den_ramt8_18 <= ex1_s_expo(6) and not ex1_s_expo(7); + + ex1_den_ramt4_12 <= not ex1_s_expo(8) and not ex1_s_expo(9); + ex1_den_ramt4_08 <= not ex1_s_expo(8) and ex1_s_expo(9); + ex1_den_ramt4_04 <= ex1_s_expo(8) and not ex1_s_expo(9); + ex1_den_ramt4_00 <= ex1_s_expo(8) and ex1_s_expo(9); + + ex1_den_ramt1_03 <= not ex1_s_expo(10) and not ex1_s_expo(11); + ex1_den_ramt1_02 <= not ex1_s_expo(10) and ex1_s_expo(11); + ex1_den_ramt1_01 <= ex1_s_expo(10) and not ex1_s_expo(11); + ex1_den_ramt1_00 <= ex1_s_expo(10) and ex1_s_expo(11); + + ex1_expo_eq896 <= not ex1_s_expo(1) and + ex1_s_expo(2) and + ex1_s_expo(3) and + ex1_s_expo(4) and + not ex1_s_expo(5) and + not ex1_s_expo(6) and + not ex1_s_expo(7) and + not ex1_s_expo(8) and + not ex1_s_expo(9) and + not ex1_s_expo(10) and + not ex1_s_expo(11) ; + + ex1_expo_ge896 <= + ( ex1_s_expo(1) ) or + ( ex1_s_expo(2) and ex1_s_expo(3) and ex1_s_expo(4) ) ; + + + ex1_ge874 <= + ( ex1_s_expo(1) ) or + ( ex1_s_expo(2) and ex1_s_expo(3) and ex1_s_expo(4) ) or + ( ex1_s_expo(2) and ex1_s_expo(3) and ex1_s_expo(5) and ex1_s_expo(6) ); + + + ex1_expo_lt896 <= not ex1_expo_ge896; + ex1_sts_lt896 <= ex1_sto_sp and ex1_expo_lt896 and ex1_ge874 ; + ex1_sts_ge896 <= ex1_sto_sp and ex1_expo_ge896 ; + + ex1_sts_sh8(0 to 23) <= + ( (0 to 23 => ex1_den_ramt8_02) and ( (0 to 1 => tidn) & ex1_s_frac(0 to 21) ) ) or + ( (0 to 23 => ex1_den_ramt8_18) and ( (0 to 17 => tidn) & ex1_s_frac(0 to 5) ) ) ; + + ex1_sts_sh4(0 to 23) <= + ( (0 to 23 => ex1_den_ramt4_12) and ( (0 to 11 => tidn) & ex1_sts_sh8(0 to 11) ) ) or + ( (0 to 23 => ex1_den_ramt4_08) and ( (0 to 7 => tidn) & ex1_sts_sh8(0 to 15) ) ) or + ( (0 to 23 => ex1_den_ramt4_04) and ( (0 to 3 => tidn) & ex1_sts_sh8(0 to 19) ) ) or + ( (0 to 23 => ex1_den_ramt4_00) and ( ex1_sts_sh8(0 to 23) ) ) ; + + ex1_sts_sh1(0 to 23) <= + ( (0 to 23 => ex1_den_ramt1_03) and ( (0 to 2 => tidn) & ex1_sts_sh4(0 to 20) ) ) or + ( (0 to 23 => ex1_den_ramt1_02) and ( (0 to 1 => tidn) & ex1_sts_sh4(0 to 21) ) ) or + ( (0 to 23 => ex1_den_ramt1_01) and ( tidn & ex1_sts_sh4(0 to 22) ) ) or + ( (0 to 23 => ex1_den_ramt1_00) and ( ex1_sts_sh4(0 to 23) ) ) ; + + ex1_sts_nrm(0 to 23) <= + ( (0 to 23 => ex1_expo_eq896) and ( tidn & ex1_s_frac(0 to 22) ) ) or + ( (0 to 23 => not ex1_expo_eq896) and ( ex1_s_frac(0 to 23) ) ) ; + + ex1_sts_frac(1 to 23) <= + ( (1 to 23 => ex1_sts_lt896) and ex1_sts_sh1(1 to 23) ) or + ( (1 to 23 => ex1_sts_ge896) and ex1_sts_nrm(1 to 23) ) ; + + + ex1_sts_expo_nz <= ex1_sto_sp and ex1_expo_ge896 ; + ex1_sts_expo(1) <= ex1_s_expo(1) and ex1_sts_expo_nz ; + ex1_sts_expo(2 to 7) <= ex1_s_expo(5 to 10) and (2 to 7=> ex1_sts_expo_nz); + ex1_sts_expo(8) <= ex1_s_expo(11) and ex1_s_frac(0) and ex1_sts_expo_nz ; + + + + + ex1_clz02_or ( 0) <= ex1_s_frac( 2) or ex1_s_frac( 3); + ex1_clz02_enc4( 0) <= not ex1_s_frac( 2) and ex1_s_frac( 3); + + ex1_clz02_or ( 1) <= ex1_s_frac( 4) or ex1_s_frac( 5); + ex1_clz02_enc4( 1) <= not ex1_s_frac( 4) and ex1_s_frac( 5); + + ex1_clz02_or ( 2) <= ex1_s_frac( 6) or ex1_s_frac( 7); + ex1_clz02_enc4( 2) <= not ex1_s_frac( 6) and ex1_s_frac( 7); + + ex1_clz02_or ( 3) <= ex1_s_frac( 8) or ex1_s_frac( 9); + ex1_clz02_enc4( 3) <= not ex1_s_frac( 8) and ex1_s_frac( 9); + + ex1_clz02_or ( 4) <= ex1_s_frac(10) or ex1_s_frac(11); + ex1_clz02_enc4( 4) <= not ex1_s_frac(10) and ex1_s_frac(11); + + ex1_clz02_or ( 5) <= ex1_s_frac(12) or ex1_s_frac(13); + ex1_clz02_enc4( 5) <= not ex1_s_frac(12) and ex1_s_frac(13); + + ex1_clz02_or ( 6) <= ex1_s_frac(14) or ex1_s_frac(15); + ex1_clz02_enc4( 6) <= not ex1_s_frac(14) and ex1_s_frac(15); + + ex1_clz02_or ( 7) <= ex1_s_frac(16) or ex1_s_frac(17); + ex1_clz02_enc4( 7) <= not ex1_s_frac(16) and ex1_s_frac(17); + + ex1_clz02_or ( 8) <= ex1_s_frac(18) or ex1_s_frac(19); + ex1_clz02_enc4( 8) <= not ex1_s_frac(18) and ex1_s_frac(19); + + ex1_clz02_or ( 9) <= ex1_s_frac(20) or ex1_s_frac(21); + ex1_clz02_enc4( 9) <= not ex1_s_frac(20) and ex1_s_frac(21); + + ex1_clz02_or (10) <= ex1_s_frac(22) or ex1_s_frac(23); + ex1_clz02_enc4(10) <= not ex1_s_frac(22) and ex1_s_frac(23); + + + ex1_clz04_or ( 0) <= ex1_clz02_or( 0) or ex1_clz02_or ( 1) ; + ex1_clz04_enc3( 0) <= not ex1_clz02_or( 0) and ex1_clz02_or ( 1) ; + ex1_clz04_enc4( 0) <= ex1_clz02_enc4( 0) or (not ex1_clz02_or( 0) and ex1_clz02_enc4( 1) ); + + ex1_clz04_or ( 1) <= ex1_clz02_or( 2) or ex1_clz02_or ( 3) ; + ex1_clz04_enc3( 1) <= not ex1_clz02_or( 2) and ex1_clz02_or ( 3) ; + ex1_clz04_enc4( 1) <= ex1_clz02_enc4( 2) or (not ex1_clz02_or( 2) and ex1_clz02_enc4( 3) ); + + ex1_clz04_or ( 2) <= ex1_clz02_or( 4) or ex1_clz02_or ( 5) ; + ex1_clz04_enc3( 2) <= not ex1_clz02_or( 4) and ex1_clz02_or ( 5) ; + ex1_clz04_enc4( 2) <= ex1_clz02_enc4( 4) or (not ex1_clz02_or( 4) and ex1_clz02_enc4( 5) ); + + ex1_clz04_or ( 3) <= ex1_clz02_or( 6) or ex1_clz02_or ( 7) ; + ex1_clz04_enc3( 3) <= not ex1_clz02_or( 6) and ex1_clz02_or ( 7) ; + ex1_clz04_enc4( 3) <= ex1_clz02_enc4( 6) or (not ex1_clz02_or( 6) and ex1_clz02_enc4( 7) ); + + ex1_clz04_or ( 4) <= ex1_clz02_or( 8) or ex1_clz02_or ( 9) ; + ex1_clz04_enc3( 4) <= not ex1_clz02_or( 8) and ex1_clz02_or ( 9) ; + ex1_clz04_enc4( 4) <= ex1_clz02_enc4( 8) or (not ex1_clz02_or( 8) and ex1_clz02_enc4( 9) ); + + ex1_clz04_or ( 5) <= ex1_clz02_or(10) ; + ex1_clz04_enc3( 5) <= tidn; + ex1_clz04_enc4( 5) <= ex1_clz02_enc4(10); + + + ex1_clz08_or ( 0) <= ex1_clz04_or( 0) or ex1_clz04_or ( 1) ; + ex1_clz08_enc2( 0) <= not ex1_clz04_or( 0) and ex1_clz04_or ( 1) ; + ex1_clz08_enc3( 0) <= ex1_clz04_enc3( 0) or (not ex1_clz04_or( 0) and ex1_clz04_enc3( 1) ); + ex1_clz08_enc4( 0) <= ex1_clz04_enc4( 0) or (not ex1_clz04_or( 0) and ex1_clz04_enc4( 1) ); + + ex1_clz08_or ( 1) <= ex1_clz04_or( 2) or ex1_clz04_or ( 3) ; + ex1_clz08_enc2( 1) <= not ex1_clz04_or( 2) and ex1_clz04_or ( 3) ; + ex1_clz08_enc3( 1) <= ex1_clz04_enc3( 2) or (not ex1_clz04_or( 2) and ex1_clz04_enc3( 3) ); + ex1_clz08_enc4( 1) <= ex1_clz04_enc4( 2) or (not ex1_clz04_or( 2) and ex1_clz04_enc4( 3) ); + + ex1_clz08_or ( 2) <= ex1_clz04_or( 4) or ex1_clz04_or ( 5) ; + ex1_clz08_enc2( 2) <= not ex1_clz04_or( 4) and ex1_clz04_or ( 5) ; + ex1_clz08_enc3( 2) <= ex1_clz04_enc3( 4) or (not ex1_clz04_or( 4) and ex1_clz04_enc3( 5) ); + ex1_clz08_enc4( 2) <= ex1_clz04_enc4( 4) or (not ex1_clz04_or( 4) and ex1_clz04_enc4( 5) ); + + + ex1_clz16_or ( 0) <= ex1_clz08_or( 0) or ex1_clz08_or ( 1) ; + ex1_clz16_enc1( 0) <= not ex1_clz08_or( 0) and ex1_clz08_or ( 1) ; + ex1_clz16_enc2( 0) <= ex1_clz08_enc2( 0) or (not ex1_clz08_or( 0) and ex1_clz08_enc2( 1) ); + ex1_clz16_enc3( 0) <= ex1_clz08_enc3( 0) or (not ex1_clz08_or( 0) and ex1_clz08_enc3( 1) ); + ex1_clz16_enc4( 0) <= ex1_clz08_enc4( 0) or (not ex1_clz08_or( 0) and ex1_clz08_enc4( 1) ); + + ex1_clz16_or ( 1) <= ex1_clz08_or( 2) ; + ex1_clz16_enc1( 1) <= tidn; + ex1_clz16_enc2( 1) <= ex1_clz08_enc2( 2) ; + ex1_clz16_enc3( 1) <= ex1_clz08_enc3( 2) ; + ex1_clz16_enc4( 1) <= ex1_clz08_enc4( 2) ; + + + ex1_sto_clz( 0) <= not ex1_clz16_or( 0) and ex1_clz16_or ( 1) ; + ex1_sto_clz( 1) <= ex1_clz16_enc1( 0) or (not ex1_clz16_or( 0) and ex1_clz16_enc1( 1) ); + ex1_sto_clz( 2) <= ex1_clz16_enc2( 0) or (not ex1_clz16_or( 0) and ex1_clz16_enc2( 1) ); + ex1_sto_clz( 3) <= ex1_clz16_enc3( 0) or (not ex1_clz16_or( 0) and ex1_clz16_enc3( 1) ); + ex1_sto_clz( 4) <= ex1_clz16_enc4( 0) or (not ex1_clz16_or( 0) and ex1_clz16_enc4( 1) ); + + ex1_any_edge <= ( ex1_clz16_or( 0) or ex1_clz16_or ( 1) ); + + + + ex1_fixden <= ex1_s_expo(2) and not ex1_s_frac(0); + ex1_fixden_small <= ex1_s_expo(2) and not ex1_s_frac(0) and ex1_s_frac(1); + ex1_fixden_big <= ex1_s_expo(2) and not ex1_s_frac(0) and not ex1_s_frac(1); + + ex1_std_nonden <= ex1_sto_dp and not ex1_fixden ; + ex1_std_fixden_big <= ex1_sto_dp and ex1_fixden_big ; + ex1_std_fixden_small <= ex1_sto_dp and ex1_fixden_small ; + ex1_std_nonbig <= ex1_sto_dp and not ex1_fixden_big; + + ex1_expo_nonden(1 to 10) <= ex1_s_expo(1 to 10) and (1 to 10=> ex1_std_nonbig ); + ex1_expo_nonden(11) <= ex1_s_expo(11) and ex1_s_frac(0) and ex1_std_nonden ; + + ex1_expo_fixden(1) <= tidn ; + ex1_expo_fixden(2) <= ex1_any_edge; + ex1_expo_fixden(3) <= ex1_any_edge; + ex1_expo_fixden(4) <= tidn ; + ex1_expo_fixden(5) <= ex1_any_edge; + ex1_expo_fixden(6) <= ex1_any_edge; + ex1_expo_fixden(7 to 11) <= not ex1_sto_clz(0 to 4) and (0 to 4 => ex1_any_edge) ; + + ex1_std_expo(1 to 11) <= + ( ex1_expo_nonden(1 to 11) ) or + ( ex1_expo_fixden(1 to 11) and (1 to 11=> ex1_std_fixden_big) ); + + + ex1_std_nonden_wd <= ex1_std_nonden or ex1_sto_wd; + + ex1_std_frac_nrm(1 to 20) <= + ( ex1_s_frac( 2 to 21) and ( 1 to 20=> ex1_std_fixden_small) ) or + ( ex1_s_frac( 1 to 20) and ( 1 to 20=> ex1_std_nonden) ) ; + ex1_std_frac_nrm(21 to 52) <= + ( (ex1_s_frac(22 to 52) & tidn) and (21 to 52=> ex1_std_fixden_small) ) or + ( ex1_s_frac(21 to 52) and (21 to 52=> ex1_std_nonden_wd) ) ; + + + ex1_std_lamt8_02 <= not ex1_sto_clz(0) and not ex1_sto_clz(1) ; + ex1_std_lamt8_10 <= not ex1_sto_clz(0) and ex1_sto_clz(1) ; + ex1_std_lamt8_18 <= ex1_sto_clz(0) and not ex1_sto_clz(1) ; + + ex1_std_lamt2_0 <= not ex1_sto_clz(2) and not ex1_sto_clz(3) ; + ex1_std_lamt2_2 <= not ex1_sto_clz(2) and ex1_sto_clz(3) ; + ex1_std_lamt2_4 <= ex1_sto_clz(2) and not ex1_sto_clz(3) ; + ex1_std_lamt2_6 <= ex1_sto_clz(2) and ex1_sto_clz(3) ; + + ex1_std_lamt1_0 <= ex1_std_fixden_big and not ex1_sto_clz(4) ; + ex1_std_lamt1_1 <= ex1_std_fixden_big and ex1_sto_clz(4) ; + + + ex1_std_sh8(0 to 23) <= + ( ( ex1_s_frac( 2 to 23) & (0 to 1=> tidn) ) and (0 to 23=> ex1_std_lamt8_02 ) ) or + ( ( ex1_s_frac(10 to 23) & (0 to 9=> tidn) ) and (0 to 23=> ex1_std_lamt8_10 ) ) or + ( ( ex1_s_frac(18 to 23) & (0 to 17=> tidn) ) and (0 to 23=> ex1_std_lamt8_18 ) ) ; + ex1_std_sh2(0 to 23) <= + ( ex1_std_sh8(0 to 23) and (0 to 23=> ex1_std_lamt2_0) ) or + ( (ex1_std_sh8(2 to 23) & (0 to 1=> tidn) ) and (0 to 23=> ex1_std_lamt2_2) ) or + ( (ex1_std_sh8(4 to 23) & (0 to 3=> tidn) ) and (0 to 23=> ex1_std_lamt2_4) ) or + ( (ex1_std_sh8(6 to 23) & (0 to 5=> tidn) ) and (0 to 23=> ex1_std_lamt2_6) ) ; + ex1_std_frac_den(1 to 23) <= + ( ex1_std_sh2(1 to 23) and (1 to 23=> ex1_std_lamt1_0) ) or + ( (ex1_std_sh2(2 to 23) & tidn) and (1 to 23=> ex1_std_lamt1_1) ) ; + + + + + ex1_sto_data(0) <= ex1_s_sign and not ex1_sto_wd; + + ex1_sto_data(1 to 8) <= ex1_sts_expo(1 to 8) or + ex1_std_expo(1 to 8); + + ex1_sto_data(9 to 11) <= ex1_sts_frac(1 to 3) or + ex1_std_expo(9 to 11); + + ex1_sto_data(12 to 31) <= ex1_sts_frac(4 to 23) or + ex1_std_frac_nrm(1 to 20) or + ex1_std_frac_den(1 to 20) ; + + ex1_sto_data(32 to 34) <= ex1_std_frac_nrm(21 to 23) or + ex1_std_frac_den(21 to 23) ; + + ex1_sto_data(35 to 63) <= ex1_std_frac_nrm(24 to 52) ; + + + ex2_sto_lat: entity tri.tri_rlmreg_p generic map (width=> 73, expand_type => expand_type, needs_sreset => 0, ibuf => true) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(2) , + mpw1_b => mpw1_b(2) , + mpw2_b => mpw2_b(0) , + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => ex1_act, + vd => vdd, + gd => gnd, + scout => ex2_sto_so , + scin => ex2_sto_si , + din(0 to 63) => ex1_sto_data(0 to 63) , + din(64) => ex1_sto_sp , + din(65) => ex1_sto_sp , + din(66) => ex1_sto_sp , + din(67) => ex1_sto_sp , + din(68) => ex1_sto_wd , + din(69) => ex1_sto_wd , + din(70) => ex1_sto_wd , + din(71) => ex1_sto_wd , + din(72) => ex1_s_party_chick , + + dout(0 to 63) => ex2_sto_data(0 to 63) , + dout(64) => ex2_sto_sp(0) , + dout(65) => ex2_sto_sp(1) , + dout(66) => ex2_sto_sp(2) , + dout(67) => ex2_sto_sp(3) , + dout(68) => ex2_sto_wd(0) , + dout(69) => ex2_sto_wd(1) , + dout(70) => ex2_sto_wd(2) , + dout(71) => ex2_sto_wd(3) , + dout(72) => ex2_s_party_chick ); + + f_sto_ex2_s_parity_check <= ex2_s_party_chick ; + + + + + + ex1_s_party(0) <= ex1_s_sign xor f_fpr_ex1_s_expo_extra xor ex1_s_expo(1) xor ex1_s_expo(2) xor ex1_s_expo(3) xor + ex1_s_expo(4) xor ex1_s_expo(5) xor ex1_s_expo(6) xor ex1_s_expo(7) ; + ex1_s_party(1) <= ex1_s_expo(8) xor ex1_s_expo(9) xor ex1_s_expo(10) xor ex1_s_expo(11) xor ex1_s_frac(0) xor + ex1_s_frac(1) xor ex1_s_frac(2) xor ex1_s_frac(3) xor ex1_s_frac(4) ; + ex1_s_party(2) <= ex1_s_frac(5) xor ex1_s_frac(6) xor ex1_s_frac(7) xor ex1_s_frac(8) xor + ex1_s_frac(9) xor ex1_s_frac(10) xor ex1_s_frac(11) xor ex1_s_frac(12) ; + ex1_s_party(3) <= ex1_s_frac(13) xor ex1_s_frac(14) xor ex1_s_frac(15) xor ex1_s_frac(16) xor + ex1_s_frac(17) xor ex1_s_frac(18) xor ex1_s_frac(19) xor ex1_s_frac(20) ; + ex1_s_party(4) <= ex1_s_frac(21) xor ex1_s_frac(22) xor ex1_s_frac(23) xor ex1_s_frac(24) xor + ex1_s_frac(25) xor ex1_s_frac(26) xor ex1_s_frac(27) xor ex1_s_frac(28) ; + ex1_s_party(5) <= ex1_s_frac(29) xor ex1_s_frac(30) xor ex1_s_frac(31) xor ex1_s_frac(32) xor + ex1_s_frac(33) xor ex1_s_frac(34) xor ex1_s_frac(35) xor ex1_s_frac(36) ; + ex1_s_party(6) <= ex1_s_frac(37) xor ex1_s_frac(38) xor ex1_s_frac(39) xor ex1_s_frac(40) xor + ex1_s_frac(41) xor ex1_s_frac(42) xor ex1_s_frac(43) xor ex1_s_frac(44) ; + ex1_s_party(7) <= ex1_s_frac(45) xor ex1_s_frac(46) xor ex1_s_frac(47) xor ex1_s_frac(48) xor + ex1_s_frac(49) xor ex1_s_frac(50) xor ex1_s_frac(51) xor ex1_s_frac(52) ; + + + ex1_s_party_chick <= (ex1_s_party(0) xor f_fpr_ex1_s_par(0) ) or + (ex1_s_party(1) xor f_fpr_ex1_s_par(1) ) or + (ex1_s_party(2) xor f_fpr_ex1_s_par(2) ) or + (ex1_s_party(3) xor f_fpr_ex1_s_par(3) ) or + (ex1_s_party(4) xor f_fpr_ex1_s_par(4) ) or + (ex1_s_party(5) xor f_fpr_ex1_s_par(5) ) or + (ex1_s_party(6) xor f_fpr_ex1_s_par(6) ) or + (ex1_s_party(7) xor f_fpr_ex1_s_par(7) ) ; + + + +u_rot0_0: ex2_sto_data_rot0_b(0) <= not( ex2_sto_data(0) and not ex2_sto_wd(0) ); +u_rot0_1: ex2_sto_data_rot0_b(1) <= not( ex2_sto_data(1) and not ex2_sto_wd(0) ); +u_rot0_2: ex2_sto_data_rot0_b(2) <= not( ex2_sto_data(2) and not ex2_sto_wd(0) ); +u_rot0_3: ex2_sto_data_rot0_b(3) <= not( ex2_sto_data(3) and not ex2_sto_wd(0) ); +u_rot0_4: ex2_sto_data_rot0_b(4) <= not( ex2_sto_data(4) and not ex2_sto_wd(0) ); +u_rot0_5: ex2_sto_data_rot0_b(5) <= not( ex2_sto_data(5) and not ex2_sto_wd(0) ); +u_rot0_6: ex2_sto_data_rot0_b(6) <= not( ex2_sto_data(6) and not ex2_sto_wd(0) ); +u_rot0_7: ex2_sto_data_rot0_b(7) <= not( ex2_sto_data(7) and not ex2_sto_wd(0) ); +u_rot0_8: ex2_sto_data_rot0_b(8) <= not( ex2_sto_data(8) and not ex2_sto_wd(1) ); +u_rot0_9: ex2_sto_data_rot0_b(9) <= not( ex2_sto_data(9) and not ex2_sto_wd(1) ); +u_rot0_10: ex2_sto_data_rot0_b(10) <= not( ex2_sto_data(10) and not ex2_sto_wd(1) ); +u_rot0_11: ex2_sto_data_rot0_b(11) <= not( ex2_sto_data(11) and not ex2_sto_wd(1) ); +u_rot0_12: ex2_sto_data_rot0_b(12) <= not( ex2_sto_data(12) and not ex2_sto_wd(1) ); +u_rot0_13: ex2_sto_data_rot0_b(13) <= not( ex2_sto_data(13) and not ex2_sto_wd(1) ); +u_rot0_14: ex2_sto_data_rot0_b(14) <= not( ex2_sto_data(14) and not ex2_sto_wd(1) ); +u_rot0_15: ex2_sto_data_rot0_b(15) <= not( ex2_sto_data(15) and not ex2_sto_wd(1) ); +u_rot0_16: ex2_sto_data_rot0_b(16) <= not( ex2_sto_data(16) and not ex2_sto_wd(2) ); +u_rot0_17: ex2_sto_data_rot0_b(17) <= not( ex2_sto_data(17) and not ex2_sto_wd(2) ); +u_rot0_18: ex2_sto_data_rot0_b(18) <= not( ex2_sto_data(18) and not ex2_sto_wd(2) ); +u_rot0_19: ex2_sto_data_rot0_b(19) <= not( ex2_sto_data(19) and not ex2_sto_wd(2) ); +u_rot0_20: ex2_sto_data_rot0_b(20) <= not( ex2_sto_data(20) and not ex2_sto_wd(2) ); +u_rot0_21: ex2_sto_data_rot0_b(21) <= not( ex2_sto_data(21) and not ex2_sto_wd(2) ); +u_rot0_22: ex2_sto_data_rot0_b(22) <= not( ex2_sto_data(22) and not ex2_sto_wd(2) ); +u_rot0_23: ex2_sto_data_rot0_b(23) <= not( ex2_sto_data(23) and not ex2_sto_wd(2) ); +u_rot0_24: ex2_sto_data_rot0_b(24) <= not( ex2_sto_data(24) and not ex2_sto_wd(3) ); +u_rot0_25: ex2_sto_data_rot0_b(25) <= not( ex2_sto_data(25) and not ex2_sto_wd(3) ); +u_rot0_26: ex2_sto_data_rot0_b(26) <= not( ex2_sto_data(26) and not ex2_sto_wd(3) ); +u_rot0_27: ex2_sto_data_rot0_b(27) <= not( ex2_sto_data(27) and not ex2_sto_wd(3) ); +u_rot0_28: ex2_sto_data_rot0_b(28) <= not( ex2_sto_data(28) and not ex2_sto_wd(3) ); +u_rot0_29: ex2_sto_data_rot0_b(29) <= not( ex2_sto_data(29) and not ex2_sto_wd(3) ); +u_rot0_30: ex2_sto_data_rot0_b(30) <= not( ex2_sto_data(30) and not ex2_sto_wd(3) ); +u_rot0_31: ex2_sto_data_rot0_b(31) <= not( ex2_sto_data(31) and not ex2_sto_wd(3) ); +u_rot0_32: ex2_sto_data_rot0_b(32) <= not( ex2_sto_data(0) and ex2_sto_sp(0) ); +u_rot0_33: ex2_sto_data_rot0_b(33) <= not( ex2_sto_data(1) and ex2_sto_sp(0) ); +u_rot0_34: ex2_sto_data_rot0_b(34) <= not( ex2_sto_data(2) and ex2_sto_sp(0) ); +u_rot0_35: ex2_sto_data_rot0_b(35) <= not( ex2_sto_data(3) and ex2_sto_sp(0) ); +u_rot0_36: ex2_sto_data_rot0_b(36) <= not( ex2_sto_data(4) and ex2_sto_sp(0) ); +u_rot0_37: ex2_sto_data_rot0_b(37) <= not( ex2_sto_data(5) and ex2_sto_sp(0) ); +u_rot0_38: ex2_sto_data_rot0_b(38) <= not( ex2_sto_data(6) and ex2_sto_sp(0) ); +u_rot0_39: ex2_sto_data_rot0_b(39) <= not( ex2_sto_data(7) and ex2_sto_sp(0) ); +u_rot0_40: ex2_sto_data_rot0_b(40) <= not( ex2_sto_data(8) and ex2_sto_sp(1) ); +u_rot0_41: ex2_sto_data_rot0_b(41) <= not( ex2_sto_data(9) and ex2_sto_sp(1) ); +u_rot0_42: ex2_sto_data_rot0_b(42) <= not( ex2_sto_data(10) and ex2_sto_sp(1) ); +u_rot0_43: ex2_sto_data_rot0_b(43) <= not( ex2_sto_data(11) and ex2_sto_sp(1) ); +u_rot0_44: ex2_sto_data_rot0_b(44) <= not( ex2_sto_data(12) and ex2_sto_sp(1) ); +u_rot0_45: ex2_sto_data_rot0_b(45) <= not( ex2_sto_data(13) and ex2_sto_sp(1) ); +u_rot0_46: ex2_sto_data_rot0_b(46) <= not( ex2_sto_data(14) and ex2_sto_sp(1) ); +u_rot0_47: ex2_sto_data_rot0_b(47) <= not( ex2_sto_data(15) and ex2_sto_sp(1) ); +u_rot0_48: ex2_sto_data_rot0_b(48) <= not( ex2_sto_data(16) and ex2_sto_sp(2) ); +u_rot0_49: ex2_sto_data_rot0_b(49) <= not( ex2_sto_data(17) and ex2_sto_sp(2) ); +u_rot0_50: ex2_sto_data_rot0_b(50) <= not( ex2_sto_data(18) and ex2_sto_sp(2) ); +u_rot0_51: ex2_sto_data_rot0_b(51) <= not( ex2_sto_data(19) and ex2_sto_sp(2) ); +u_rot0_52: ex2_sto_data_rot0_b(52) <= not( ex2_sto_data(20) and ex2_sto_sp(2) ); +u_rot0_53: ex2_sto_data_rot0_b(53) <= not( ex2_sto_data(21) and ex2_sto_sp(2) ); +u_rot0_54: ex2_sto_data_rot0_b(54) <= not( ex2_sto_data(22) and ex2_sto_sp(2) ); +u_rot0_55: ex2_sto_data_rot0_b(55) <= not( ex2_sto_data(23) and ex2_sto_sp(2) ); +u_rot0_56: ex2_sto_data_rot0_b(56) <= not( ex2_sto_data(24) and ex2_sto_sp(3) ); +u_rot0_57: ex2_sto_data_rot0_b(57) <= not( ex2_sto_data(25) and ex2_sto_sp(3) ); +u_rot0_58: ex2_sto_data_rot0_b(58) <= not( ex2_sto_data(26) and ex2_sto_sp(3) ); +u_rot0_59: ex2_sto_data_rot0_b(59) <= not( ex2_sto_data(27) and ex2_sto_sp(3) ); +u_rot0_60: ex2_sto_data_rot0_b(60) <= not( ex2_sto_data(28) and ex2_sto_sp(3) ); +u_rot0_61: ex2_sto_data_rot0_b(61) <= not( ex2_sto_data(29) and ex2_sto_sp(3) ); +u_rot0_62: ex2_sto_data_rot0_b(62) <= not( ex2_sto_data(30) and ex2_sto_sp(3) ); +u_rot0_63: ex2_sto_data_rot0_b(63) <= not( ex2_sto_data(31) and ex2_sto_sp(3) ); + + +u_rot1_0: ex2_sto_data_rot1_b(0) <= not( ex2_sto_data(32) and ex2_sto_wd(0) ); +u_rot1_1: ex2_sto_data_rot1_b(1) <= not( ex2_sto_data(33) and ex2_sto_wd(0) ); +u_rot1_2: ex2_sto_data_rot1_b(2) <= not( ex2_sto_data(34) and ex2_sto_wd(0) ); +u_rot1_3: ex2_sto_data_rot1_b(3) <= not( ex2_sto_data(35) and ex2_sto_wd(0) ); +u_rot1_4: ex2_sto_data_rot1_b(4) <= not( ex2_sto_data(36) and ex2_sto_wd(0) ); +u_rot1_5: ex2_sto_data_rot1_b(5) <= not( ex2_sto_data(37) and ex2_sto_wd(0) ); +u_rot1_6: ex2_sto_data_rot1_b(6) <= not( ex2_sto_data(38) and ex2_sto_wd(0) ); +u_rot1_7: ex2_sto_data_rot1_b(7) <= not( ex2_sto_data(39) and ex2_sto_wd(0) ); +u_rot1_8: ex2_sto_data_rot1_b(8) <= not( ex2_sto_data(40) and ex2_sto_wd(1) ); +u_rot1_9: ex2_sto_data_rot1_b(9) <= not( ex2_sto_data(41) and ex2_sto_wd(1) ); +u_rot1_10: ex2_sto_data_rot1_b(10) <= not( ex2_sto_data(42) and ex2_sto_wd(1) ); +u_rot1_11: ex2_sto_data_rot1_b(11) <= not( ex2_sto_data(43) and ex2_sto_wd(1) ); +u_rot1_12: ex2_sto_data_rot1_b(12) <= not( ex2_sto_data(44) and ex2_sto_wd(1) ); +u_rot1_13: ex2_sto_data_rot1_b(13) <= not( ex2_sto_data(45) and ex2_sto_wd(1) ); +u_rot1_14: ex2_sto_data_rot1_b(14) <= not( ex2_sto_data(46) and ex2_sto_wd(1) ); +u_rot1_15: ex2_sto_data_rot1_b(15) <= not( ex2_sto_data(47) and ex2_sto_wd(1) ); +u_rot1_16: ex2_sto_data_rot1_b(16) <= not( ex2_sto_data(48) and ex2_sto_wd(2) ); +u_rot1_17: ex2_sto_data_rot1_b(17) <= not( ex2_sto_data(49) and ex2_sto_wd(2) ); +u_rot1_18: ex2_sto_data_rot1_b(18) <= not( ex2_sto_data(50) and ex2_sto_wd(2) ); +u_rot1_19: ex2_sto_data_rot1_b(19) <= not( ex2_sto_data(51) and ex2_sto_wd(2) ); +u_rot1_20: ex2_sto_data_rot1_b(20) <= not( ex2_sto_data(52) and ex2_sto_wd(2) ); +u_rot1_21: ex2_sto_data_rot1_b(21) <= not( ex2_sto_data(53) and ex2_sto_wd(2) ); +u_rot1_22: ex2_sto_data_rot1_b(22) <= not( ex2_sto_data(54) and ex2_sto_wd(2) ); +u_rot1_23: ex2_sto_data_rot1_b(23) <= not( ex2_sto_data(55) and ex2_sto_wd(2) ); +u_rot1_24: ex2_sto_data_rot1_b(24) <= not( ex2_sto_data(56) and ex2_sto_wd(3) ); +u_rot1_25: ex2_sto_data_rot1_b(25) <= not( ex2_sto_data(57) and ex2_sto_wd(3) ); +u_rot1_26: ex2_sto_data_rot1_b(26) <= not( ex2_sto_data(58) and ex2_sto_wd(3) ); +u_rot1_27: ex2_sto_data_rot1_b(27) <= not( ex2_sto_data(59) and ex2_sto_wd(3) ); +u_rot1_28: ex2_sto_data_rot1_b(28) <= not( ex2_sto_data(60) and ex2_sto_wd(3) ); +u_rot1_29: ex2_sto_data_rot1_b(29) <= not( ex2_sto_data(61) and ex2_sto_wd(3) ); +u_rot1_30: ex2_sto_data_rot1_b(30) <= not( ex2_sto_data(62) and ex2_sto_wd(3) ); +u_rot1_31: ex2_sto_data_rot1_b(31) <= not( ex2_sto_data(63) and ex2_sto_wd(3) ); +u_rot1_32: ex2_sto_data_rot1_b(32) <= not( ex2_sto_data(32) and not ex2_sto_sp(0) ); +u_rot1_33: ex2_sto_data_rot1_b(33) <= not( ex2_sto_data(33) and not ex2_sto_sp(0) ); +u_rot1_34: ex2_sto_data_rot1_b(34) <= not( ex2_sto_data(34) and not ex2_sto_sp(0) ); +u_rot1_35: ex2_sto_data_rot1_b(35) <= not( ex2_sto_data(35) and not ex2_sto_sp(0) ); +u_rot1_36: ex2_sto_data_rot1_b(36) <= not( ex2_sto_data(36) and not ex2_sto_sp(0) ); +u_rot1_37: ex2_sto_data_rot1_b(37) <= not( ex2_sto_data(37) and not ex2_sto_sp(0) ); +u_rot1_38: ex2_sto_data_rot1_b(38) <= not( ex2_sto_data(38) and not ex2_sto_sp(0) ); +u_rot1_39: ex2_sto_data_rot1_b(39) <= not( ex2_sto_data(39) and not ex2_sto_sp(0) ); +u_rot1_40: ex2_sto_data_rot1_b(40) <= not( ex2_sto_data(40) and not ex2_sto_sp(1) ); +u_rot1_41: ex2_sto_data_rot1_b(41) <= not( ex2_sto_data(41) and not ex2_sto_sp(1) ); +u_rot1_42: ex2_sto_data_rot1_b(42) <= not( ex2_sto_data(42) and not ex2_sto_sp(1) ); +u_rot1_43: ex2_sto_data_rot1_b(43) <= not( ex2_sto_data(43) and not ex2_sto_sp(1) ); +u_rot1_44: ex2_sto_data_rot1_b(44) <= not( ex2_sto_data(44) and not ex2_sto_sp(1) ); +u_rot1_45: ex2_sto_data_rot1_b(45) <= not( ex2_sto_data(45) and not ex2_sto_sp(1) ); +u_rot1_46: ex2_sto_data_rot1_b(46) <= not( ex2_sto_data(46) and not ex2_sto_sp(1) ); +u_rot1_47: ex2_sto_data_rot1_b(47) <= not( ex2_sto_data(47) and not ex2_sto_sp(1) ); +u_rot1_48: ex2_sto_data_rot1_b(48) <= not( ex2_sto_data(48) and not ex2_sto_sp(2) ); +u_rot1_49: ex2_sto_data_rot1_b(49) <= not( ex2_sto_data(49) and not ex2_sto_sp(2) ); +u_rot1_50: ex2_sto_data_rot1_b(50) <= not( ex2_sto_data(50) and not ex2_sto_sp(2) ); +u_rot1_51: ex2_sto_data_rot1_b(51) <= not( ex2_sto_data(51) and not ex2_sto_sp(2) ); +u_rot1_52: ex2_sto_data_rot1_b(52) <= not( ex2_sto_data(52) and not ex2_sto_sp(2) ); +u_rot1_53: ex2_sto_data_rot1_b(53) <= not( ex2_sto_data(53) and not ex2_sto_sp(2) ); +u_rot1_54: ex2_sto_data_rot1_b(54) <= not( ex2_sto_data(54) and not ex2_sto_sp(2) ); +u_rot1_55: ex2_sto_data_rot1_b(55) <= not( ex2_sto_data(55) and not ex2_sto_sp(2) ); +u_rot1_56: ex2_sto_data_rot1_b(56) <= not( ex2_sto_data(56) and not ex2_sto_sp(3) ); +u_rot1_57: ex2_sto_data_rot1_b(57) <= not( ex2_sto_data(57) and not ex2_sto_sp(3) ); +u_rot1_58: ex2_sto_data_rot1_b(58) <= not( ex2_sto_data(58) and not ex2_sto_sp(3) ); +u_rot1_59: ex2_sto_data_rot1_b(59) <= not( ex2_sto_data(59) and not ex2_sto_sp(3) ); +u_rot1_60: ex2_sto_data_rot1_b(60) <= not( ex2_sto_data(60) and not ex2_sto_sp(3) ); +u_rot1_61: ex2_sto_data_rot1_b(61) <= not( ex2_sto_data(61) and not ex2_sto_sp(3) ); +u_rot1_62: ex2_sto_data_rot1_b(62) <= not( ex2_sto_data(62) and not ex2_sto_sp(3) ); +u_rot1_63: ex2_sto_data_rot1_b(63) <= not( ex2_sto_data(63) and not ex2_sto_sp(3) ); + + +u_rot: f_sto_ex2_sto_data(0 to 63) <= not( ex2_sto_data_rot0_b(0 to 63) and ex2_sto_data_rot1_b(0 to 63) ); + + + + + + ex1_sins_si (0 to 2) <= ex1_sins_so (1 to 2) & f_sto_si ; + ex1_sop_si (0 to 64) <= ex1_sop_so (1 to 64) & ex1_sins_so (0) ; + ex2_sto_si (0 to 72) <= ex2_sto_so (1 to 72) & ex1_sop_so (0) ; + act_si (0 to 3 ) <= act_so ( 1 to 3) & ex2_sto_so (0); + f_sto_so <= act_so (0) ; + + +end; + + + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_tblexp.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_tblexp.vhdl new file mode 100644 index 0000000..c52a494 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_tblexp.vhdl @@ -0,0 +1,615 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + + +ENTITY fuq_tblexp IS +generic( + expand_type : integer := 2 ); +PORT( + vdd :inout power_logic; + gnd :inout power_logic; + clkoff_b :in std_ulogic; + act_dis :in std_ulogic; + flush :in std_ulogic; + delay_lclkr :in std_ulogic_vector(2 to 3); + mpw1_b :in std_ulogic_vector(2 to 3); + mpw2_b :in std_ulogic_vector(0 to 0); + sg_1 :in std_ulogic; + thold_1 :in std_ulogic; + fpu_enable :in std_ulogic; + nclk :in clk_logic; + + si :in std_ulogic ; + so :out std_ulogic ; + ex1_act_b :in std_ulogic ; + + f_pic_ex2_ue1 :in std_ulogic; + f_pic_ex2_sp_b :in std_ulogic; + f_pic_ex2_est_recip :in std_ulogic; + f_pic_ex2_est_rsqrt :in std_ulogic; + f_eie_ex2_tbl_expo :in std_ulogic_vector(1 to 13); + f_fmt_ex2_lu_den_recip :in std_ulogic ; + f_fmt_ex2_lu_den_rsqrto :in std_ulogic ; + + f_tbe_ex3_recip_ue1 :out std_ulogic ; + f_tbe_ex3_lu_sh :out std_ulogic ; + f_tbe_ex3_match_en_sp :out std_ulogic ; + f_tbe_ex3_match_en_dp :out std_ulogic ; + f_tbe_ex3_recip_2046 :out std_ulogic ; + f_tbe_ex3_recip_2045 :out std_ulogic ; + f_tbe_ex3_recip_2044 :out std_ulogic ; + f_tbe_ex3_may_ov :out std_ulogic ; + f_tbe_ex3_res_expo :out std_ulogic_vector(1 to 13) + +); + + + +end fuq_tblexp; + + +architecture fuq_tblexp of fuq_tblexp is + + constant tiup :std_ulogic := '1'; + constant tidn :std_ulogic := '0'; + + signal thold_0_b, thold_0, forcee, sg_0 : std_ulogic; + signal act_spare_unused :std_ulogic_vector(0 to 3); + signal ex2_act :std_ulogic; + signal act_so , act_si :std_ulogic_vector(0 to 4); + signal ex3_expo_so , ex3_expo_si :std_ulogic_vector(0 to 19); + signal ex2_res_expo :std_ulogic_vector(1 to 13); + signal ex3_res_expo :std_ulogic_vector(1 to 13); + signal ex3_recip_2044, ex2_recip_2044, ex2_recip_ue1 :std_ulogic; + signal ex3_recip_2045, ex2_recip_2045, ex3_recip_ue1 :std_ulogic; + signal ex3_recip_2046, ex2_recip_2046 :std_ulogic; + signal ex3_force_expo_den :std_ulogic; + + signal ex2_b_expo_adj_b :std_ulogic_vector(1 to 13); + signal ex2_b_expo_adj :std_ulogic_vector(1 to 13); + signal ex2_recip_k :std_ulogic_vector(1 to 13); + signal ex2_recip_p :std_ulogic_vector(1 to 13); + signal ex2_recip_g :std_ulogic_vector(2 to 13); + signal ex2_recip_t :std_ulogic_vector(2 to 12); + signal ex2_recip_c :std_ulogic_vector(2 to 13); + signal ex2_recip_expo :std_ulogic_vector(1 to 13); + signal ex2_rsqrt_k :std_ulogic_vector(1 to 13); + signal ex2_rsqrt_p :std_ulogic_vector(1 to 13); + signal ex2_rsqrt_g :std_ulogic_vector(2 to 13); + signal ex2_rsqrt_t :std_ulogic_vector(2 to 12); + signal ex2_rsqrt_c :std_ulogic_vector(2 to 13); + signal ex2_rsqrt_expo :std_ulogic_vector(1 to 13); + signal ex2_rsqrt_bsh_b :std_ulogic_vector(1 to 13); + + signal ex2_recip_g2 :std_ulogic_vector(2 to 13); + signal ex2_recip_t2 :std_ulogic_vector(2 to 11); + signal ex2_recip_g4 :std_ulogic_vector(2 to 13); + signal ex2_recip_t4 :std_ulogic_vector(2 to 9); + signal ex2_recip_g8 :std_ulogic_vector(2 to 13); + signal ex2_recip_t8 :std_ulogic_vector(2 to 5); + + signal ex2_rsqrt_g2 :std_ulogic_vector(2 to 13); + signal ex2_rsqrt_t2 :std_ulogic_vector(2 to 11); + signal ex2_rsqrt_g4 :std_ulogic_vector(2 to 13); + signal ex2_rsqrt_t4 :std_ulogic_vector(2 to 9); + signal ex2_rsqrt_g8 :std_ulogic_vector(2 to 13); + signal ex2_rsqrt_t8 :std_ulogic_vector(2 to 5); + signal ex1_act :std_ulogic; + + signal ex2_lu_sh, ex3_lu_sh :std_ulogic; + signal ex3_res_expo_c, ex3_res_expo_g8_b, ex3_res_expo_g4, ex3_res_expo_g2_b :std_ulogic_vector(2 to 13); + signal ex3_res_decr, ex3_res_expo_b :std_ulogic_vector(1 to 13); + signal ex3_decr_expo :std_ulogic; + + signal ex2_mid_match_ifsp, ex2_mid_match_ifdp :std_ulogic; + signal ex2_match_en_dp, ex2_match_en_sp :std_ulogic; + signal ex3_match_en_dp, ex3_match_en_sp :std_ulogic; + signal ex2_com_match :std_ulogic; + signal ex3_recip_2044_dp, ex3_recip_2045_dp, ex3_recip_2046_dp :std_ulogic; + + + + +begin + + + thold_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => thold_1, + q(0) => thold_0 ); + + sg_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => sg_1 , + q(0) => sg_0 ); + + + lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map ( + clkoff_b => clkoff_b, + thold => thold_0, + sg => sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => thold_0_b ); + + + + + + + ex1_act <= not ex1_act_b ; + + act_lat: tri_rlmreg_p generic map (width=> 5, expand_type => expand_type) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(2) , + mpw1_b => mpw1_b(2) , + mpw2_b => mpw2_b(0) , + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => fpu_enable, + scout => act_so , + scin => act_si , + din(0) => act_spare_unused(0), + din(1) => act_spare_unused(1), + din(2) => ex1_act, + din(3) => act_spare_unused(2), + din(4) => act_spare_unused(3), + dout(0) => act_spare_unused(0), + dout(1) => act_spare_unused(1), + dout(2) => ex2_act, + dout(3) => act_spare_unused(2), + dout(4) => act_spare_unused(3) ); + + + + + + ex2_b_expo_adj(1 to 13) <= f_eie_ex2_tbl_expo(1 to 13); + ex2_b_expo_adj_b(1 to 13) <= not ex2_b_expo_adj(1 to 13); + + + + ex2_recip_k(1 to 13) <= (1 to 2=> tidn) & (3 to 12=> tiup) & tidn ; + + ex2_recip_p(1 to 13) <= ex2_recip_k(1 to 13) xor ex2_b_expo_adj_b(1 to 13) ; + ex2_recip_g(2 to 13) <= ex2_recip_k(2 to 13) and ex2_b_expo_adj_b(2 to 13) ; + ex2_recip_t(2 to 12) <= ex2_recip_k(2 to 12) or ex2_b_expo_adj_b(2 to 12) ; + + ex2_recip_g2(13) <= ex2_recip_g(13); + ex2_recip_g2(12) <= ex2_recip_g(12) or (ex2_recip_t(12) and ex2_recip_g(13) ); + ex2_recip_g2(11) <= ex2_recip_g(11) or (ex2_recip_t(11) and ex2_recip_g(12) ); + ex2_recip_g2(10) <= ex2_recip_g(10) or (ex2_recip_t(10) and ex2_recip_g(11) ); + ex2_recip_g2( 9) <= ex2_recip_g( 9) or (ex2_recip_t( 9) and ex2_recip_g(10) ); + ex2_recip_g2( 8) <= ex2_recip_g( 8) or (ex2_recip_t( 8) and ex2_recip_g( 9) ); + ex2_recip_g2( 7) <= ex2_recip_g( 7) or (ex2_recip_t( 7) and ex2_recip_g( 8) ); + ex2_recip_g2( 6) <= ex2_recip_g( 6) or (ex2_recip_t( 6) and ex2_recip_g( 7) ); + ex2_recip_g2( 5) <= ex2_recip_g( 5) or (ex2_recip_t( 5) and ex2_recip_g( 6) ); + ex2_recip_g2( 4) <= ex2_recip_g( 4) or (ex2_recip_t( 4) and ex2_recip_g( 5) ); + ex2_recip_g2( 3) <= ex2_recip_g( 3) or (ex2_recip_t( 3) and ex2_recip_g( 4) ); + ex2_recip_g2( 2) <= ex2_recip_g( 2) or (ex2_recip_t( 2) and ex2_recip_g( 3) ); + + ex2_recip_t2(11) <= (ex2_recip_t(11) and ex2_recip_t(12) ); + ex2_recip_t2(10) <= (ex2_recip_t(10) and ex2_recip_t(11) ); + ex2_recip_t2( 9) <= (ex2_recip_t( 9) and ex2_recip_t(10) ); + ex2_recip_t2( 8) <= (ex2_recip_t( 8) and ex2_recip_t( 9) ); + ex2_recip_t2( 7) <= (ex2_recip_t( 7) and ex2_recip_t( 8) ); + ex2_recip_t2( 6) <= (ex2_recip_t( 6) and ex2_recip_t( 7) ); + ex2_recip_t2( 5) <= (ex2_recip_t( 5) and ex2_recip_t( 6) ); + ex2_recip_t2( 4) <= (ex2_recip_t( 4) and ex2_recip_t( 5) ); + ex2_recip_t2( 3) <= (ex2_recip_t( 3) and ex2_recip_t( 4) ); + ex2_recip_t2( 2) <= (ex2_recip_t( 2) and ex2_recip_t( 3) ); + + ex2_recip_g4(13) <= ex2_recip_g2(13); + ex2_recip_g4(12) <= ex2_recip_g2(12); + ex2_recip_g4(11) <= ex2_recip_g2(11) or (ex2_recip_t2(11) and ex2_recip_g2(13) ); + ex2_recip_g4(10) <= ex2_recip_g2(10) or (ex2_recip_t2(10) and ex2_recip_g2(12) ); + ex2_recip_g4( 9) <= ex2_recip_g2( 9) or (ex2_recip_t2( 9) and ex2_recip_g2(11) ); + ex2_recip_g4( 8) <= ex2_recip_g2( 8) or (ex2_recip_t2( 8) and ex2_recip_g2(10) ); + ex2_recip_g4( 7) <= ex2_recip_g2( 7) or (ex2_recip_t2( 7) and ex2_recip_g2( 9) ); + ex2_recip_g4( 6) <= ex2_recip_g2( 6) or (ex2_recip_t2( 6) and ex2_recip_g2( 8) ); + ex2_recip_g4( 5) <= ex2_recip_g2( 5) or (ex2_recip_t2( 5) and ex2_recip_g2( 7) ); + ex2_recip_g4( 4) <= ex2_recip_g2( 4) or (ex2_recip_t2( 4) and ex2_recip_g2( 6) ); + ex2_recip_g4( 3) <= ex2_recip_g2( 3) or (ex2_recip_t2( 3) and ex2_recip_g2( 5) ); + ex2_recip_g4( 2) <= ex2_recip_g2( 2) or (ex2_recip_t2( 2) and ex2_recip_g2( 4) ); + + ex2_recip_t4( 9) <= (ex2_recip_t2( 9) and ex2_recip_t2(11) ); + ex2_recip_t4( 8) <= (ex2_recip_t2( 8) and ex2_recip_t2(10) ); + ex2_recip_t4( 7) <= (ex2_recip_t2( 7) and ex2_recip_t2( 9) ); + ex2_recip_t4( 6) <= (ex2_recip_t2( 6) and ex2_recip_t2( 8) ); + ex2_recip_t4( 5) <= (ex2_recip_t2( 5) and ex2_recip_t2( 7) ); + ex2_recip_t4( 4) <= (ex2_recip_t2( 4) and ex2_recip_t2( 6) ); + ex2_recip_t4( 3) <= (ex2_recip_t2( 3) and ex2_recip_t2( 5) ); + ex2_recip_t4( 2) <= (ex2_recip_t2( 2) and ex2_recip_t2( 4) ); + + ex2_recip_g8(13) <= ex2_recip_g4(13); + ex2_recip_g8(12) <= ex2_recip_g4(12); + ex2_recip_g8(11) <= ex2_recip_g4(11); + ex2_recip_g8(10) <= ex2_recip_g4(10); + ex2_recip_g8( 9) <= ex2_recip_g4( 9) or (ex2_recip_t4( 9) and ex2_recip_g4(13) ); + ex2_recip_g8( 8) <= ex2_recip_g4( 8) or (ex2_recip_t4( 8) and ex2_recip_g4(12) ); + ex2_recip_g8( 7) <= ex2_recip_g4( 7) or (ex2_recip_t4( 7) and ex2_recip_g4(11) ); + ex2_recip_g8( 6) <= ex2_recip_g4( 6) or (ex2_recip_t4( 6) and ex2_recip_g4(10) ); + ex2_recip_g8( 5) <= ex2_recip_g4( 5) or (ex2_recip_t4( 5) and ex2_recip_g4( 9) ); + ex2_recip_g8( 4) <= ex2_recip_g4( 4) or (ex2_recip_t4( 4) and ex2_recip_g4( 8) ); + ex2_recip_g8( 3) <= ex2_recip_g4( 3) or (ex2_recip_t4( 3) and ex2_recip_g4( 7) ); + ex2_recip_g8( 2) <= ex2_recip_g4( 2) or (ex2_recip_t4( 2) and ex2_recip_g4( 6) ); + + ex2_recip_t8( 5) <= (ex2_recip_t4( 5) and ex2_recip_t4( 9) ); + ex2_recip_t8( 4) <= (ex2_recip_t4( 4) and ex2_recip_t4( 8) ); + ex2_recip_t8( 3) <= (ex2_recip_t4( 3) and ex2_recip_t4( 7) ); + ex2_recip_t8( 2) <= (ex2_recip_t4( 2) and ex2_recip_t4( 6) ); + + ex2_recip_c(13) <= ex2_recip_g8(13); + ex2_recip_c(12) <= ex2_recip_g8(12); + ex2_recip_c(11) <= ex2_recip_g8(11); + ex2_recip_c(10) <= ex2_recip_g8(10); + ex2_recip_c( 9) <= ex2_recip_g8( 9); + ex2_recip_c( 8) <= ex2_recip_g8( 8); + ex2_recip_c( 7) <= ex2_recip_g8( 7); + ex2_recip_c( 6) <= ex2_recip_g8( 6); + ex2_recip_c( 5) <= ex2_recip_g8( 5) or (ex2_recip_t8( 5) and ex2_recip_g8(13) ); + ex2_recip_c( 4) <= ex2_recip_g8( 4) or (ex2_recip_t8( 4) and ex2_recip_g8(12) ); + ex2_recip_c( 3) <= ex2_recip_g8( 3) or (ex2_recip_t8( 3) and ex2_recip_g8(11) ); + ex2_recip_c( 2) <= ex2_recip_g8( 2) or (ex2_recip_t8( 2) and ex2_recip_g8(10) ); + + + ex2_recip_expo(1 to 12) <= ex2_recip_p(1 to 12) xor ex2_recip_c(2 to 13); + ex2_recip_expo(13) <= ex2_recip_p(13); + + + + ex2_rsqrt_k(1 to 13) <= tidn & tidn & tiup & tidn & (5 to 12=> tiup) & ex2_b_expo_adj_b(13); + ex2_rsqrt_bsh_b(1 to 13) <= ex2_b_expo_adj_b(1) & ex2_b_expo_adj_b(1 to 12); + + ex2_rsqrt_p(1 to 13) <= ex2_rsqrt_k(1 to 13) xor ex2_rsqrt_bsh_b(1 to 13) ; + ex2_rsqrt_g(2 to 13) <= ex2_rsqrt_k(2 to 13) and ex2_rsqrt_bsh_b(2 to 13) ; + ex2_rsqrt_t(2 to 12) <= ex2_rsqrt_k(2 to 12) or ex2_rsqrt_bsh_b(2 to 12) ; + + + + ex2_rsqrt_g2(13) <= ex2_rsqrt_g(13); + ex2_rsqrt_g2(12) <= ex2_rsqrt_g(12) or (ex2_rsqrt_t(12) and ex2_rsqrt_g(13) ); + ex2_rsqrt_g2(11) <= ex2_rsqrt_g(11) or (ex2_rsqrt_t(11) and ex2_rsqrt_g(12) ); + ex2_rsqrt_g2(10) <= ex2_rsqrt_g(10) or (ex2_rsqrt_t(10) and ex2_rsqrt_g(11) ); + ex2_rsqrt_g2( 9) <= ex2_rsqrt_g( 9) or (ex2_rsqrt_t( 9) and ex2_rsqrt_g(10) ); + ex2_rsqrt_g2( 8) <= ex2_rsqrt_g( 8) or (ex2_rsqrt_t( 8) and ex2_rsqrt_g( 9) ); + ex2_rsqrt_g2( 7) <= ex2_rsqrt_g( 7) or (ex2_rsqrt_t( 7) and ex2_rsqrt_g( 8) ); + ex2_rsqrt_g2( 6) <= ex2_rsqrt_g( 6) or (ex2_rsqrt_t( 6) and ex2_rsqrt_g( 7) ); + ex2_rsqrt_g2( 5) <= ex2_rsqrt_g( 5) or (ex2_rsqrt_t( 5) and ex2_rsqrt_g( 6) ); + ex2_rsqrt_g2( 4) <= ex2_rsqrt_g( 4) or (ex2_rsqrt_t( 4) and ex2_rsqrt_g( 5) ); + ex2_rsqrt_g2( 3) <= ex2_rsqrt_g( 3) or (ex2_rsqrt_t( 3) and ex2_rsqrt_g( 4) ); + ex2_rsqrt_g2( 2) <= ex2_rsqrt_g( 2) or (ex2_rsqrt_t( 2) and ex2_rsqrt_g( 3) ); + + ex2_rsqrt_t2(11) <= (ex2_rsqrt_t(11) and ex2_rsqrt_t(12) ); + ex2_rsqrt_t2(10) <= (ex2_rsqrt_t(10) and ex2_rsqrt_t(11) ); + ex2_rsqrt_t2( 9) <= (ex2_rsqrt_t( 9) and ex2_rsqrt_t(10) ); + ex2_rsqrt_t2( 8) <= (ex2_rsqrt_t( 8) and ex2_rsqrt_t( 9) ); + ex2_rsqrt_t2( 7) <= (ex2_rsqrt_t( 7) and ex2_rsqrt_t( 8) ); + ex2_rsqrt_t2( 6) <= (ex2_rsqrt_t( 6) and ex2_rsqrt_t( 7) ); + ex2_rsqrt_t2( 5) <= (ex2_rsqrt_t( 5) and ex2_rsqrt_t( 6) ); + ex2_rsqrt_t2( 4) <= (ex2_rsqrt_t( 4) and ex2_rsqrt_t( 5) ); + ex2_rsqrt_t2( 3) <= (ex2_rsqrt_t( 3) and ex2_rsqrt_t( 4) ); + ex2_rsqrt_t2( 2) <= (ex2_rsqrt_t( 2) and ex2_rsqrt_t( 3) ); + + ex2_rsqrt_g4(13) <= ex2_rsqrt_g2(13); + ex2_rsqrt_g4(12) <= ex2_rsqrt_g2(12); + ex2_rsqrt_g4(11) <= ex2_rsqrt_g2(11) or (ex2_rsqrt_t2(11) and ex2_rsqrt_g2(13) ); + ex2_rsqrt_g4(10) <= ex2_rsqrt_g2(10) or (ex2_rsqrt_t2(10) and ex2_rsqrt_g2(12) ); + ex2_rsqrt_g4( 9) <= ex2_rsqrt_g2( 9) or (ex2_rsqrt_t2( 9) and ex2_rsqrt_g2(11) ); + ex2_rsqrt_g4( 8) <= ex2_rsqrt_g2( 8) or (ex2_rsqrt_t2( 8) and ex2_rsqrt_g2(10) ); + ex2_rsqrt_g4( 7) <= ex2_rsqrt_g2( 7) or (ex2_rsqrt_t2( 7) and ex2_rsqrt_g2( 9) ); + ex2_rsqrt_g4( 6) <= ex2_rsqrt_g2( 6) or (ex2_rsqrt_t2( 6) and ex2_rsqrt_g2( 8) ); + ex2_rsqrt_g4( 5) <= ex2_rsqrt_g2( 5) or (ex2_rsqrt_t2( 5) and ex2_rsqrt_g2( 7) ); + ex2_rsqrt_g4( 4) <= ex2_rsqrt_g2( 4) or (ex2_rsqrt_t2( 4) and ex2_rsqrt_g2( 6) ); + ex2_rsqrt_g4( 3) <= ex2_rsqrt_g2( 3) or (ex2_rsqrt_t2( 3) and ex2_rsqrt_g2( 5) ); + ex2_rsqrt_g4( 2) <= ex2_rsqrt_g2( 2) or (ex2_rsqrt_t2( 2) and ex2_rsqrt_g2( 4) ); + + ex2_rsqrt_t4( 9) <= (ex2_rsqrt_t2( 9) and ex2_rsqrt_t2(11) ); + ex2_rsqrt_t4( 8) <= (ex2_rsqrt_t2( 8) and ex2_rsqrt_t2(10) ); + ex2_rsqrt_t4( 7) <= (ex2_rsqrt_t2( 7) and ex2_rsqrt_t2( 9) ); + ex2_rsqrt_t4( 6) <= (ex2_rsqrt_t2( 6) and ex2_rsqrt_t2( 8) ); + ex2_rsqrt_t4( 5) <= (ex2_rsqrt_t2( 5) and ex2_rsqrt_t2( 7) ); + ex2_rsqrt_t4( 4) <= (ex2_rsqrt_t2( 4) and ex2_rsqrt_t2( 6) ); + ex2_rsqrt_t4( 3) <= (ex2_rsqrt_t2( 3) and ex2_rsqrt_t2( 5) ); + ex2_rsqrt_t4( 2) <= (ex2_rsqrt_t2( 2) and ex2_rsqrt_t2( 4) ); + + ex2_rsqrt_g8(13) <= ex2_rsqrt_g4(13); + ex2_rsqrt_g8(12) <= ex2_rsqrt_g4(12); + ex2_rsqrt_g8(11) <= ex2_rsqrt_g4(11); + ex2_rsqrt_g8(10) <= ex2_rsqrt_g4(10); + ex2_rsqrt_g8( 9) <= ex2_rsqrt_g4( 9) or (ex2_rsqrt_t4( 9) and ex2_rsqrt_g4(13) ); + ex2_rsqrt_g8( 8) <= ex2_rsqrt_g4( 8) or (ex2_rsqrt_t4( 8) and ex2_rsqrt_g4(12) ); + ex2_rsqrt_g8( 7) <= ex2_rsqrt_g4( 7) or (ex2_rsqrt_t4( 7) and ex2_rsqrt_g4(11) ); + ex2_rsqrt_g8( 6) <= ex2_rsqrt_g4( 6) or (ex2_rsqrt_t4( 6) and ex2_rsqrt_g4(10) ); + ex2_rsqrt_g8( 5) <= ex2_rsqrt_g4( 5) or (ex2_rsqrt_t4( 5) and ex2_rsqrt_g4( 9) ); + ex2_rsqrt_g8( 4) <= ex2_rsqrt_g4( 4) or (ex2_rsqrt_t4( 4) and ex2_rsqrt_g4( 8) ); + ex2_rsqrt_g8( 3) <= ex2_rsqrt_g4( 3) or (ex2_rsqrt_t4( 3) and ex2_rsqrt_g4( 7) ); + ex2_rsqrt_g8( 2) <= ex2_rsqrt_g4( 2) or (ex2_rsqrt_t4( 2) and ex2_rsqrt_g4( 6) ); + + ex2_rsqrt_t8( 5) <= (ex2_rsqrt_t4( 5) and ex2_rsqrt_t4( 9) ); + ex2_rsqrt_t8( 4) <= (ex2_rsqrt_t4( 4) and ex2_rsqrt_t4( 8) ); + ex2_rsqrt_t8( 3) <= (ex2_rsqrt_t4( 3) and ex2_rsqrt_t4( 7) ); + ex2_rsqrt_t8( 2) <= (ex2_rsqrt_t4( 2) and ex2_rsqrt_t4( 6) ); + + ex2_rsqrt_c(13) <= ex2_rsqrt_g8(13); + ex2_rsqrt_c(12) <= ex2_rsqrt_g8(12); + ex2_rsqrt_c(11) <= ex2_rsqrt_g8(11); + ex2_rsqrt_c(10) <= ex2_rsqrt_g8(10); + ex2_rsqrt_c( 9) <= ex2_rsqrt_g8( 9); + ex2_rsqrt_c( 8) <= ex2_rsqrt_g8( 8); + ex2_rsqrt_c( 7) <= ex2_rsqrt_g8( 7); + ex2_rsqrt_c( 6) <= ex2_rsqrt_g8( 6); + ex2_rsqrt_c( 5) <= ex2_rsqrt_g8( 5) or (ex2_rsqrt_t8( 5) and ex2_rsqrt_g8(13) ); + ex2_rsqrt_c( 4) <= ex2_rsqrt_g8( 4) or (ex2_rsqrt_t8( 4) and ex2_rsqrt_g8(12) ); + ex2_rsqrt_c( 3) <= ex2_rsqrt_g8( 3) or (ex2_rsqrt_t8( 3) and ex2_rsqrt_g8(11) ); + ex2_rsqrt_c( 2) <= ex2_rsqrt_g8( 2) or (ex2_rsqrt_t8( 2) and ex2_rsqrt_g8(10) ); + + + + ex2_rsqrt_expo(1 to 12) <= ex2_rsqrt_p(1 to 12) xor ex2_rsqrt_c(2 to 13); + ex2_rsqrt_expo(13) <= ex2_rsqrt_p(13); + + + ex2_res_expo(1 to 13) <= + ( (1 to 13=> f_pic_ex2_est_rsqrt) and ex2_rsqrt_expo(1 to 13) ) or + ( (1 to 13=> f_pic_ex2_est_recip) and ex2_recip_expo(1 to 13) ) ; + + + + + + ex2_mid_match_ifsp <= not f_eie_ex2_tbl_expo( 4) and + not f_eie_ex2_tbl_expo( 5) and + not f_eie_ex2_tbl_expo( 6) ; + + ex2_mid_match_ifdp <= f_eie_ex2_tbl_expo( 4) and + f_eie_ex2_tbl_expo( 5) and + f_eie_ex2_tbl_expo( 6) ; + + ex2_com_match <= not f_eie_ex2_tbl_expo( 1) and + not f_eie_ex2_tbl_expo( 2) and + f_eie_ex2_tbl_expo( 3) and + f_eie_ex2_tbl_expo( 7) and + f_eie_ex2_tbl_expo( 8) and + f_eie_ex2_tbl_expo( 9) and + f_eie_ex2_tbl_expo(10) and + f_eie_ex2_tbl_expo(11) ; + + ex2_match_en_dp <= ex2_com_match and f_pic_ex2_sp_b and ex2_mid_match_ifdp ; + ex2_match_en_sp <= ex2_com_match and not f_pic_ex2_sp_b and ex2_mid_match_ifsp ; + + ex2_recip_2046 <= f_pic_ex2_est_recip and + f_eie_ex2_tbl_expo(12) and + not f_eie_ex2_tbl_expo(13) ; + + ex2_recip_2045 <= f_pic_ex2_est_recip and + not f_eie_ex2_tbl_expo(12) and + f_eie_ex2_tbl_expo(13) ; + + ex2_recip_2044 <= f_pic_ex2_est_recip and + not f_eie_ex2_tbl_expo(12) and + not f_eie_ex2_tbl_expo(13) ; + + ex2_recip_ue1 <= f_pic_ex2_est_recip and f_pic_ex2_ue1 ; + + + + ex2_lu_sh <= (f_fmt_ex2_lu_den_recip and f_pic_ex2_est_recip ) or + (f_fmt_ex2_lu_den_rsqrto and f_pic_ex2_est_rsqrt and not f_eie_ex2_tbl_expo(13) ); + + ex3_expo_lat: tri_rlmreg_p generic map (width=> 20, expand_type => expand_type) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(3) , + mpw1_b => mpw1_b(3) , + mpw2_b => mpw2_b(0) , + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => ex2_act, + scout => ex3_expo_so , + scin => ex3_expo_si , + + din(0 to 12) => ex2_res_expo(1 to 13) , + din(13) => ex2_match_en_dp , + din(14) => ex2_match_en_sp , + din(15) => ex2_recip_2046 , + din(16) => ex2_recip_2045 , + din(17) => ex2_recip_2044 , + din(18) => ex2_lu_sh , + din(19) => ex2_recip_ue1 , + dout(0 to 12) => ex3_res_expo(1 to 13) , + dout(13) => ex3_match_en_dp , + dout(14) => ex3_match_en_sp , + dout(15) => ex3_recip_2046 , + dout(16) => ex3_recip_2045 , + dout(17) => ex3_recip_2044 , + dout(18) => ex3_lu_sh , + dout(19) => ex3_recip_ue1 ); + + + + + + f_tbe_ex3_match_en_sp <= ex3_match_en_sp ; + f_tbe_ex3_match_en_dp <= ex3_match_en_dp ; + f_tbe_ex3_recip_2046 <= ex3_recip_2046 ; + f_tbe_ex3_recip_2045 <= ex3_recip_2045 ; + f_tbe_ex3_recip_2044 <= ex3_recip_2044 ; + f_tbe_ex3_lu_sh <= ex3_lu_sh ; + f_tbe_ex3_recip_ue1 <= ex3_recip_ue1 ; + + ex3_recip_2046_dp <= ex3_recip_2046 and ex3_match_en_dp and not ex3_recip_ue1 ; + ex3_recip_2045_dp <= ex3_recip_2045 and ex3_match_en_dp and not ex3_recip_ue1 ; + ex3_recip_2044_dp <= ex3_recip_2044 and ex3_match_en_dp and not ex3_recip_ue1 ; + ex3_force_expo_den <= ex3_recip_2046_dp or ex3_recip_2045_dp; + + ex3_decr_expo <= + ( ex3_lu_sh and ex3_recip_ue1 ) or + ( ex3_lu_sh and not ex3_recip_ue1 and not ex3_recip_2046_dp + and not ex3_recip_2045_dp + and not ex3_recip_2044_dp ); + + + + ex3_res_expo_b(1 to 13) <= not ex3_res_expo(1 to 13); + + ex3_res_expo_g2_b(13) <= not( ex3_res_expo (13) ); + ex3_res_expo_g2_b(12) <= not( ex3_res_expo (12) or ex3_res_expo (13) ); + ex3_res_expo_g2_b(11) <= not( ex3_res_expo (11) or ex3_res_expo (12) ); + ex3_res_expo_g2_b(10) <= not( ex3_res_expo (10) or ex3_res_expo (11) ); + ex3_res_expo_g2_b( 9) <= not( ex3_res_expo ( 9) or ex3_res_expo (10) ); + ex3_res_expo_g2_b( 8) <= not( ex3_res_expo ( 8) or ex3_res_expo ( 9) ); + ex3_res_expo_g2_b( 7) <= not( ex3_res_expo ( 7) or ex3_res_expo ( 8) ); + ex3_res_expo_g2_b( 6) <= not( ex3_res_expo ( 6) or ex3_res_expo ( 7) ); + ex3_res_expo_g2_b( 5) <= not( ex3_res_expo ( 5) or ex3_res_expo ( 6) ); + ex3_res_expo_g2_b( 4) <= not( ex3_res_expo ( 4) or ex3_res_expo ( 5) ); + ex3_res_expo_g2_b( 3) <= not( ex3_res_expo ( 3) or ex3_res_expo ( 4) ); + ex3_res_expo_g2_b( 2) <= not( ex3_res_expo ( 2) or ex3_res_expo ( 3) ); + + ex3_res_expo_g4 (13) <= not( ex3_res_expo_g2_b(13) ); + ex3_res_expo_g4 (12) <= not( ex3_res_expo_g2_b(12) ); + ex3_res_expo_g4 (11) <= not( ex3_res_expo_g2_b(11) and ex3_res_expo_g2_b(13) ); + ex3_res_expo_g4 (10) <= not( ex3_res_expo_g2_b(10) and ex3_res_expo_g2_b(12) ); + ex3_res_expo_g4 ( 9) <= not( ex3_res_expo_g2_b( 9) and ex3_res_expo_g2_b(11) ); + ex3_res_expo_g4 ( 8) <= not( ex3_res_expo_g2_b( 8) and ex3_res_expo_g2_b(10) ); + ex3_res_expo_g4 ( 7) <= not( ex3_res_expo_g2_b( 7) and ex3_res_expo_g2_b( 9) ); + ex3_res_expo_g4 ( 6) <= not( ex3_res_expo_g2_b( 6) and ex3_res_expo_g2_b( 8) ); + ex3_res_expo_g4 ( 5) <= not( ex3_res_expo_g2_b( 5) and ex3_res_expo_g2_b( 7) ); + ex3_res_expo_g4 ( 4) <= not( ex3_res_expo_g2_b( 4) and ex3_res_expo_g2_b( 6) ); + ex3_res_expo_g4 ( 3) <= not( ex3_res_expo_g2_b( 3) and ex3_res_expo_g2_b( 5) ); + ex3_res_expo_g4 ( 2) <= not( ex3_res_expo_g2_b( 2) and ex3_res_expo_g2_b( 4) ); + + ex3_res_expo_g8_b(13) <= not( ex3_res_expo_g4 (13) ); + ex3_res_expo_g8_b(12) <= not( ex3_res_expo_g4 (12) ); + ex3_res_expo_g8_b(11) <= not( ex3_res_expo_g4 (11) ); + ex3_res_expo_g8_b(10) <= not( ex3_res_expo_g4 (10) ); + ex3_res_expo_g8_b( 9) <= not( ex3_res_expo_g4 ( 9) or ex3_res_expo_g4 (13) ); + ex3_res_expo_g8_b( 8) <= not( ex3_res_expo_g4 ( 8) or ex3_res_expo_g4 (12) ); + ex3_res_expo_g8_b( 7) <= not( ex3_res_expo_g4 ( 7) or ex3_res_expo_g4 (11) ); + ex3_res_expo_g8_b( 6) <= not( ex3_res_expo_g4 ( 6) or ex3_res_expo_g4 (10) ); + ex3_res_expo_g8_b( 5) <= not( ex3_res_expo_g4 ( 5) or ex3_res_expo_g4 ( 9) ); + ex3_res_expo_g8_b( 4) <= not( ex3_res_expo_g4 ( 4) or ex3_res_expo_g4 ( 8) ); + ex3_res_expo_g8_b( 3) <= not( ex3_res_expo_g4 ( 3) or ex3_res_expo_g4 ( 7) ); + ex3_res_expo_g8_b( 2) <= not( ex3_res_expo_g4 ( 2) or ex3_res_expo_g4 ( 6) ); + + ex3_res_expo_c (13) <= not( ex3_res_expo_g8_b(13) ); + ex3_res_expo_c (12) <= not( ex3_res_expo_g8_b(12) ); + ex3_res_expo_c (11) <= not( ex3_res_expo_g8_b(11) ); + ex3_res_expo_c (10) <= not( ex3_res_expo_g8_b(10) ); + ex3_res_expo_c ( 9) <= not( ex3_res_expo_g8_b( 9) ); + ex3_res_expo_c ( 8) <= not( ex3_res_expo_g8_b( 8) ); + ex3_res_expo_c ( 7) <= not( ex3_res_expo_g8_b( 7) ); + ex3_res_expo_c ( 6) <= not( ex3_res_expo_g8_b( 6) ); + ex3_res_expo_c ( 5) <= not( ex3_res_expo_g8_b( 5) and ex3_res_expo_g8_b(13) ); + ex3_res_expo_c ( 4) <= not( ex3_res_expo_g8_b( 4) and ex3_res_expo_g8_b(12) ); + ex3_res_expo_c ( 3) <= not( ex3_res_expo_g8_b( 3) and ex3_res_expo_g8_b(11) ); + ex3_res_expo_c ( 2) <= not( ex3_res_expo_g8_b( 2) and ex3_res_expo_g8_b(10) ); + + + ex3_res_decr(1 to 12) <= ex3_res_expo_b(1 to 12) xor ex3_res_expo_c(2 to 13); + ex3_res_decr(13) <= ex3_res_expo_b(13) ; + + + f_tbe_ex3_res_expo( 1) <= ( ex3_res_expo( 1) and not ex3_decr_expo and not ex3_force_expo_den ) or + ( ex3_res_decr( 1) and ex3_decr_expo ); + f_tbe_ex3_res_expo( 2) <= ( ex3_res_expo( 2) and not ex3_decr_expo and not ex3_force_expo_den ) or + ( ex3_res_decr( 2) and ex3_decr_expo ); + f_tbe_ex3_res_expo( 3) <= ( ex3_res_expo( 3) and not ex3_decr_expo and not ex3_force_expo_den ) or + ( ex3_res_decr( 3) and ex3_decr_expo ); + f_tbe_ex3_res_expo( 4) <= ( ex3_res_expo( 4) and not ex3_decr_expo and not ex3_force_expo_den ) or + ( ex3_res_decr( 4) and ex3_decr_expo ); + f_tbe_ex3_res_expo( 5) <= ( ex3_res_expo( 5) and not ex3_decr_expo and not ex3_force_expo_den ) or + ( ex3_res_decr( 5) and ex3_decr_expo ); + f_tbe_ex3_res_expo( 6) <= ( ex3_res_expo( 6) and not ex3_decr_expo and not ex3_force_expo_den ) or + ( ex3_res_decr( 6) and ex3_decr_expo ); + f_tbe_ex3_res_expo( 7) <= ( ex3_res_expo( 7) and not ex3_decr_expo and not ex3_force_expo_den ) or + ( ex3_res_decr( 7) and ex3_decr_expo ); + f_tbe_ex3_res_expo( 8) <= ( ex3_res_expo( 8) and not ex3_decr_expo and not ex3_force_expo_den ) or + ( ex3_res_decr( 8) and ex3_decr_expo ); + f_tbe_ex3_res_expo( 9) <= ( ex3_res_expo( 9) and not ex3_decr_expo and not ex3_force_expo_den ) or + ( ex3_res_decr( 9) and ex3_decr_expo ); + f_tbe_ex3_res_expo(10) <= ( ex3_res_expo(10) and not ex3_decr_expo and not ex3_force_expo_den ) or + ( ex3_res_decr(10) and ex3_decr_expo ); + f_tbe_ex3_res_expo(11) <= ( ex3_res_expo(11) and not ex3_decr_expo and not ex3_force_expo_den ) or + ( ex3_res_decr(11) and ex3_decr_expo ); + f_tbe_ex3_res_expo(12) <= ( ex3_res_expo(12) and not ex3_decr_expo and not ex3_force_expo_den ) or + ( ex3_res_decr(12) and ex3_decr_expo ); + f_tbe_ex3_res_expo(13) <= ( ex3_res_expo(13) and not ex3_decr_expo ) or + ( ex3_res_decr(13) and ex3_decr_expo ) or + ( ex3_force_expo_den ); + + + + + f_tbe_ex3_may_ov <= + (not ex3_res_expo(1) and ex3_res_expo(2) ) or + (not ex3_res_expo(1) and ex3_res_expo(3) and ex3_res_expo(4) ) or + (not ex3_res_expo(1) and ex3_res_expo(3) and ex3_res_expo(5) ) or + (not ex3_res_expo(1) and ex3_res_expo(3) and ex3_res_expo(6) ) or + (not ex3_res_expo(1) and ex3_res_expo(3) and ex3_res_expo(7) ) or + (not ex3_res_expo(1) and ex3_res_expo(3) and ex3_res_expo(8) and ex3_res_expo(9) ); + + + + + + ex3_expo_si (0 to 19) <= ex3_expo_so (1 to 19) & si; + act_si (0 to 4) <= act_so (1 to 4) & ex3_expo_so (0); + so <= act_so (0); + + +end; + + + + + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_tbllut.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_tbllut.vhdl new file mode 100644 index 0000000..8e2cda1 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_tbllut.vhdl @@ -0,0 +1,790 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + + +entity fuq_tbllut is +generic( expand_type : integer := 2 ); +port( + vdd :inout power_logic; + gnd :inout power_logic; + clkoff_b :in std_ulogic; + act_dis :in std_ulogic; + flush :in std_ulogic; + delay_lclkr :in std_ulogic_vector(2 to 5); + mpw1_b :in std_ulogic_vector(2 to 5); + mpw2_b :in std_ulogic_vector(0 to 1); + sg_1 :in std_ulogic; + thold_1 :in std_ulogic; + fpu_enable :in std_ulogic; + nclk :in clk_logic; + + + si :in std_ulogic; + so :out std_ulogic; + ex1_act :in std_ulogic; + f_fmt_ex1_b_frac :in std_ulogic_vector(1 to 6); + f_fmt_ex2_b_frac :in std_ulogic_vector(7 to 22); + f_tbe_ex2_expo_lsb :in std_ulogic; + f_tbe_ex2_est_recip :in std_ulogic; + f_tbe_ex2_est_rsqrt :in std_ulogic; + f_tbe_ex3_recip_ue1 :in std_ulogic ; + f_tbe_ex3_lu_sh :in std_ulogic; + f_tbe_ex3_match_en_sp :in std_ulogic; + f_tbe_ex3_match_en_dp :in std_ulogic; + f_tbe_ex3_recip_2046 :in std_ulogic; + f_tbe_ex3_recip_2045 :in std_ulogic; + f_tbe_ex3_recip_2044 :in std_ulogic; + f_tbl_ex5_est_frac :out std_ulogic_vector(0 to 26); + f_tbl_ex4_unf_expo :out std_ulogic ; + f_tbl_ex5_recip_den :out std_ulogic +); + + + +end fuq_tbllut; + +architecture fuq_tbllut of fuq_tbllut is + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal ex4_unf_expo :std_ulogic ; + signal ex2_f :std_ulogic_vector(1 to 6); + signal ex2_sel_recip, ex2_sel_rsqte, ex2_sel_rsqto : std_ulogic; + signal ex2_est, ex2_est_recip, ex2_est_rsqte, ex2_est_rsqto :std_ulogic_vector(1 to 20); + signal ex2_rng :std_ulogic_vector(6 to 20); + signal ex2_rng_recip, ex2_rng_rsqte, ex2_rng_rsqto :std_ulogic_vector(6 to 20); + + signal thold_0_b, thold_0, forcee, sg_0 :std_ulogic ; + signal ex2_act, ex3_act, ex4_act :std_ulogic; + signal spare_unused :std_ulogic_vector(0 to 3); + + signal ex2_lut_so, ex2_lut_si :std_ulogic_vector(0 to 5); + signal act_so, act_si :std_ulogic_vector(0 to 6); + signal ex3_lut_e_so, ex3_lut_e_si :std_ulogic_vector(0 to 19); + signal ex3_lut_r_so, ex3_lut_r_si :std_ulogic_vector(0 to 14); + signal ex3_lut_b_so, ex3_lut_b_si :std_ulogic_vector(0 to 15); + + + signal ex3_rng, ex3_rng_b :std_ulogic_vector(6 to 20); + signal ex3_est, ex3_est_b :std_ulogic_vector(1 to 20); + signal ex3_bop, ex3_bop_b :std_ulogic_vector(7 to 22); + signal ex3_tbl_sum :std_ulogic_vector(0 to 36) ; + signal ex3_tbl_car :std_ulogic_vector(0 to 35) ; + signal ex4_tbl_sum :std_ulogic_vector(0 to 38) ; + signal ex4_tbl_car :std_ulogic_vector(0 to 38) ; + + signal ex4_lut_so , ex4_lut_si :std_ulogic_vector(0 to 79); + + signal ex5_lut_so , ex5_lut_si :std_ulogic_vector(0 to 27) ; + signal ex4_lu , ex4_lux :std_ulogic_vector(0 to 27) ; + signal ex4_lu_nrm :std_ulogic_vector(0 to 26) ; + signal ex5_lu :std_ulogic_vector(0 to 26); + + signal lua_p :std_ulogic_vector(0 to 27); + signal lua_t :std_ulogic_vector(1 to 37); + signal lua_g :std_ulogic_vector(1 to 38); + signal lua_g2 :std_ulogic_vector(1 to 38); + signal lua_g4 :std_ulogic_vector(1 to 36); + signal lua_g8 :std_ulogic_vector(1 to 32); + signal lua_t2 :std_ulogic_vector(1 to 36); + signal lua_t4 :std_ulogic_vector(1 to 32); + signal lua_t8 :std_ulogic_vector(1 to 28); + signal lua_gt8 :std_ulogic_vector(1 to 28); + signal lua_s0_b :std_ulogic_vector(0 to 27); + signal lua_s1_b :std_ulogic_vector(0 to 27); + signal lua_g16 : std_ulogic_vector(0 to 3); + signal lua_t16 : std_ulogic_vector(0 to 1); + signal lua_c32 , lua_c24 , lua_c16 , lua_c08 :std_ulogic; + signal ex4_recip_den, ex5_recip_den :std_ulogic ; + signal ex4_lu_sh , ex4_recip_ue1, ex4_recip_2044, ex4_recip_2046 , ex4_recip_2045 :std_ulogic; + signal ex4_recip_2044_dp, ex4_recip_2046_dp , ex4_recip_2045_dp :std_ulogic; + signal ex4_recip_2044_sp, ex4_recip_2046_sp , ex4_recip_2045_sp :std_ulogic; + + signal ex4_shlft_1, ex4_shlft_0, ex4_shrgt_1, ex4_shrgt_2 :std_ulogic; + signal ex4_match_en_sp , ex4_match_en_dp :std_ulogic; + signal tbl_ex3_d1clk, tbl_ex3_d2clk :std_ulogic; + signal tbl_ex4_d1clk, tbl_ex4_d2clk :std_ulogic; + signal tbl_ex3_lclk :clk_logic; + signal tbl_ex4_lclk :clk_logic; + signal unused :std_ulogic; + signal ex4_tbl_sum_b :std_ulogic_vector(0 to 36) ; + signal ex4_tbl_car_b :std_ulogic_vector(0 to 35) ; + signal ex4_match_en_sp_b :std_ulogic; + signal ex4_match_en_dp_b :std_ulogic; + signal ex4_recip_2046_b :std_ulogic; + signal ex4_recip_2045_b :std_ulogic; + signal ex4_recip_2044_b :std_ulogic; + signal ex4_lu_sh_b :std_ulogic; + signal ex4_recip_ue1_b :std_ulogic; + + signal ex4_sp_chop_24, ex4_sp_chop_23, ex4_sp_chop_22, ex4_sp_chop_21 :std_ulogic; + + + +begin + + unused <= or_reduce(lua_g8(29 to 31) ) or or_reduce(lua_g4(33 to 35) ) ; + + + ex2_lut_lat: tri_rlmreg_p generic map (width=> 6, expand_type => expand_type) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(2) , + mpw1_b => mpw1_b(2) , + mpw2_b => mpw2_b(0) , + vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_act, + thold_b => thold_0_b, + sg => sg_0, + scout => ex2_lut_so , + scin => ex2_lut_si , + din => f_fmt_ex1_b_frac(1 to 6), + dout => ex2_f(1 to 6) ); + + + +ftbe: entity WORK.fuq_tblsqe(fuq_tblsqe) generic map( expand_type => expand_type) port map( + f(1 to 6) => ex2_f(1 to 6) , + est(1 to 20) => ex2_est_rsqte(1 to 20) , + rng(6 to 20) => ex2_rng_rsqte(6 to 20) ); + + +ftbo: entity WORK.fuq_tblsqo(fuq_tblsqo) generic map( expand_type => expand_type) port map( + f(1 to 6) => ex2_f(1 to 6) , + est(1 to 20) => ex2_est_rsqto(1 to 20) , + rng(6 to 20) => ex2_rng_rsqto(6 to 20) ); + + +ftbr: entity WORK.fuq_tblres(fuq_tblres) generic map( expand_type => expand_type) port map( + f(1 to 6) => ex2_f(1 to 6) , + est(1 to 20) => ex2_est_recip(1 to 20) , + rng(6 to 20) => ex2_rng_recip(6 to 20) ); + + + + + ex2_sel_recip <= f_tbe_ex2_est_recip; + ex2_sel_rsqte <= f_tbe_ex2_est_rsqrt and not f_tbe_ex2_expo_lsb ; + ex2_sel_rsqto <= f_tbe_ex2_est_rsqrt and f_tbe_ex2_expo_lsb ; + + ex2_est(1 to 20) <= + ( (1 to 20=> ex2_sel_recip) and ex2_est_recip(1 to 20) ) or + ( (1 to 20=> ex2_sel_rsqte) and ex2_est_rsqte(1 to 20) ) or + ( (1 to 20=> ex2_sel_rsqto) and ex2_est_rsqto(1 to 20) ) ; + + + ex2_rng(6 to 20) <= + ( (6 to 20=> ex2_sel_recip ) and ( ex2_rng_recip(6 to 20)) ) or + ( (6 to 20=> ex2_sel_rsqte ) and ( ex2_rng_rsqte(6 to 20)) ) or + ( (6 to 20=> ex2_sel_rsqto ) and ( ex2_rng_rsqto(6 to 20)) ) ; + + + + ex3_lut_e_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 20, btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd, + gd => gnd, + LCLK => tbl_ex3_lclk , + D1CLK => tbl_ex3_d1clk , + D2CLK => tbl_ex3_d2clk , + SCANIN => ex3_lut_e_si , + SCANOUT => ex3_lut_e_so , + D(0 to 19) => ex2_est(1 to 20) , + QB(0 to 19) => ex3_est_b(1 to 20) ); + + ex3_lut_r_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 15, btr => "NLI0001_X4_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd, + gd => gnd, + LCLK => tbl_ex3_lclk , + D1CLK => tbl_ex3_d1clk , + D2CLK => tbl_ex3_d2clk , + SCANIN => ex3_lut_r_si , + SCANOUT => ex3_lut_r_so , + D(0 to 14) => ex2_rng(6 to 20) , + QB(0 to 14) => ex3_rng_b(6 to 20) ); + + ex3_lut_b_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 16, btr => "NLI0001_X1_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd, + gd => gnd, + LCLK => tbl_ex3_lclk , + D1CLK => tbl_ex3_d1clk , + D2CLK => tbl_ex3_d2clk , + SCANIN => ex3_lut_b_si , + SCANOUT => ex3_lut_b_so , + D(0 to 15) => f_fmt_ex2_b_frac(7 to 22) , + QB(0 to 15) => ex3_bop_b(7 to 22) ); + + ex3_est(1 to 20) <= not ex3_est_b(1 to 20); + ex3_rng(6 to 20) <= not ex3_rng_b(6 to 20); + ex3_bop(7 to 22) <= not ex3_bop_b(7 to 22); + + + +ftbm: entity WORK.fuq_tblmul(fuq_tblmul) generic map( expand_type => expand_type) port map( + vdd => vdd, + gnd => gnd, + x(1 to 15) => ex3_rng(6 to 20) , + y(7 to 22) => ex3_bop(7 to 22) , + z(0) => tiup , + z(1 to 20) => ex3_est(1 to 20) , + tbl_sum(0 to 36) => ex3_tbl_sum(0 to 36) , + tbl_car(0 to 35) => ex3_tbl_car(0 to 35) ); + + + + + ex4_lut_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 80, btr => "NLI0001_X2_A12TH", expand_type => expand_type , needs_sreset => 0 ) port map ( + vd => vdd, + gd => gnd, + LCLK => tbl_ex4_lclk , + D1CLK => tbl_ex4_d1clk , + D2CLK => tbl_ex4_d2clk , + SCANIN => ex4_lut_si , + SCANOUT => ex4_lut_so , + D(0 to 36) => ex3_tbl_sum(0 to 36) , + D(37 to 72) => ex3_tbl_car(0 to 35) , + D(73) => f_tbe_ex3_match_en_sp , + D(74) => f_tbe_ex3_match_en_dp , + D(75) => f_tbe_ex3_recip_2046 , + D(76) => f_tbe_ex3_recip_2045 , + D(77) => f_tbe_ex3_recip_2044 , + D(78) => f_tbe_ex3_lu_sh , + D(79) => f_tbe_ex3_recip_ue1 , + QB(0 to 36) => ex4_tbl_sum_b(0 to 36) , + QB(37 to 72) => ex4_tbl_car_b(0 to 35) , + QB(73) => ex4_match_en_sp_b , + QB(74) => ex4_match_en_dp_b , + QB(75) => ex4_recip_2046_b , + QB(76) => ex4_recip_2045_b , + QB(77) => ex4_recip_2044_b , + QB(78) => ex4_lu_sh_b , + QB(79) => ex4_recip_ue1_b ); + + + ex4_tbl_sum (0 to 36) <= not ex4_tbl_sum_b(0 to 36) ; + ex4_tbl_car (0 to 35) <= not ex4_tbl_car_b(0 to 35) ; + ex4_match_en_sp <= not ex4_match_en_sp_b ; + ex4_match_en_dp <= not ex4_match_en_dp_b ; + ex4_recip_2046 <= not ex4_recip_2046_b ; + ex4_recip_2045 <= not ex4_recip_2045_b ; + ex4_recip_2044 <= not ex4_recip_2044_b ; + ex4_lu_sh <= not ex4_lu_sh_b ; + ex4_recip_ue1 <= not ex4_recip_ue1_b ; + + + + + ex4_tbl_sum(37) <= tidn; + ex4_tbl_sum(38) <= tidn; + + ex4_tbl_car(36) <= tidn; + ex4_tbl_car(37) <= tidn; + ex4_tbl_car(38) <= tidn; + + + lua_p(0 to 27) <= ex4_tbl_sum(0 to 27) xor ex4_tbl_car(0 to 27); + lua_t(1 to 37) <= ex4_tbl_sum(1 to 37) or ex4_tbl_car(1 to 37); + lua_g(1 to 38) <= ex4_tbl_sum(1 to 38) and ex4_tbl_car(1 to 38); + + + + lua_g2(38) <= lua_g(38) ; + lua_g2(37) <= lua_g(37) or (lua_t(37) and lua_g(38) ); + lua_g2(36) <= lua_g(36) or (lua_t(36) and lua_g(37) ); + lua_g2(35) <= lua_g(35) or (lua_t(35) and lua_g(36) ); + lua_g2(34) <= lua_g(34) or (lua_t(34) and lua_g(35) ); + lua_g2(33) <= lua_g(33) or (lua_t(33) and lua_g(34) ); + lua_g2(32) <= lua_g(32) or (lua_t(32) and lua_g(33) ); + lua_t2(36) <= lua_t(36) and lua_t(37) ; + lua_t2(35) <= lua_t(35) and lua_t(36) ; + lua_t2(34) <= lua_t(34) and lua_t(35) ; + lua_t2(33) <= lua_t(33) and lua_t(34) ; + lua_t2(32) <= lua_t(32) and lua_t(33) ; + lua_g4(36) <= lua_g2(36) or (lua_t2(36) and lua_g2(38) ); + lua_g4(35) <= lua_g2(35) or (lua_t2(35) and lua_g2(37) ); + lua_g4(34) <= lua_g2(34) or (lua_t2(34) and lua_g2(36) ); + lua_g4(33) <= lua_g2(33) or (lua_t2(33) and lua_g2(35) ); + lua_g4(32) <= lua_g2(32) or (lua_t2(32) and lua_g2(34) ); + lua_t4(32) <= lua_t2(32) and lua_t2(34) ; + lua_g8(32) <= lua_g4(32) or (lua_t4(32) and lua_g4(36) ); + + + + + lua_g2(31) <= lua_g(31) ; + lua_g2(30) <= lua_g(30) or (lua_t(30) and lua_g(31) ); + lua_g2(29) <= lua_g(29) or (lua_t(29) and lua_g(30) ); + lua_g2(28) <= lua_g(28) or (lua_t(28) and lua_g(29) ); + lua_g2(27) <= lua_g(27) or (lua_t(27) and lua_g(28) ); + lua_g2(26) <= lua_g(26) or (lua_t(26) and lua_g(27) ); + lua_g2(25) <= lua_g(25) or (lua_t(25) and lua_g(26) ); + lua_g2(24) <= lua_g(24) or (lua_t(24) and lua_g(25) ); + lua_t2(31) <= lua_t(31) ; + lua_t2(30) <= lua_t(30) and lua_t(31) ; + lua_t2(29) <= lua_t(29) and lua_t(30) ; + lua_t2(28) <= lua_t(28) and lua_t(29) ; + lua_t2(27) <= lua_t(27) and lua_t(28) ; + lua_t2(26) <= lua_t(26) and lua_t(27) ; + lua_t2(25) <= lua_t(25) and lua_t(26) ; + lua_t2(24) <= lua_t(24) and lua_t(25) ; + lua_g4(31) <= lua_g2(31) ; + lua_g4(30) <= lua_g2(30) ; + lua_g4(29) <= lua_g2(29) or (lua_t2(29) and lua_g2(31) ); + lua_g4(28) <= lua_g2(28) or (lua_t2(28) and lua_g2(30) ); + lua_g4(27) <= lua_g2(27) or (lua_t2(27) and lua_g2(29) ); + lua_g4(26) <= lua_g2(26) or (lua_t2(26) and lua_g2(28) ); + lua_g4(25) <= lua_g2(25) or (lua_t2(25) and lua_g2(27) ); + lua_g4(24) <= lua_g2(24) or (lua_t2(24) and lua_g2(26) ); + lua_t4(31) <= lua_t2(31) ; + lua_t4(30) <= lua_t2(30) ; + lua_t4(29) <= lua_t2(29) and lua_t2(31) ; + lua_t4(28) <= lua_t2(28) and lua_t2(30) ; + lua_t4(27) <= lua_t2(27) and lua_t2(29) ; + lua_t4(26) <= lua_t2(26) and lua_t2(28) ; + lua_t4(25) <= lua_t2(25) and lua_t2(27) ; + lua_t4(24) <= lua_t2(24) and lua_t2(26) ; + lua_g8(31) <= lua_g4(31) ; + lua_g8(30) <= lua_g4(30) ; + lua_g8(29) <= lua_g4(29) ; + lua_g8(28) <= lua_g4(28) ; + lua_g8(27) <= lua_g4(27) or (lua_t4(27) and lua_g4(31) ); + lua_g8(26) <= lua_g4(26) or (lua_t4(26) and lua_g4(30) ); + lua_g8(25) <= lua_g4(25) or (lua_t4(25) and lua_g4(29) ); + lua_g8(24) <= lua_g4(24) or (lua_t4(24) and lua_g4(28) ); + lua_t8(28) <= lua_t4(28) ; + lua_t8(27) <= lua_t4(27) and lua_t4(31) ; + lua_t8(26) <= lua_t4(26) and lua_t4(30) ; + lua_t8(25) <= lua_t4(25) and lua_t4(29) ; + lua_t8(24) <= lua_t4(24) and lua_t4(28) ; + + + + + lua_g2(23) <= lua_g(23) ; + lua_g2(22) <= lua_g(22) or (lua_t(22) and lua_g(23) ); + lua_g2(21) <= lua_g(21) or (lua_t(21) and lua_g(22) ); + lua_g2(20) <= lua_g(20) or (lua_t(20) and lua_g(21) ); + lua_g2(19) <= lua_g(19) or (lua_t(19) and lua_g(20) ); + lua_g2(18) <= lua_g(18) or (lua_t(18) and lua_g(19) ); + lua_g2(17) <= lua_g(17) or (lua_t(17) and lua_g(18) ); + lua_g2(16) <= lua_g(16) or (lua_t(16) and lua_g(17) ); + lua_t2(23) <= lua_t(23) ; + lua_t2(22) <= lua_t(22) and lua_t(23) ; + lua_t2(21) <= lua_t(21) and lua_t(22) ; + lua_t2(20) <= lua_t(20) and lua_t(21) ; + lua_t2(19) <= lua_t(19) and lua_t(20) ; + lua_t2(18) <= lua_t(18) and lua_t(19) ; + lua_t2(17) <= lua_t(17) and lua_t(18) ; + lua_t2(16) <= lua_t(16) and lua_t(17) ; + lua_g4(23) <= lua_g2(23) ; + lua_g4(22) <= lua_g2(22) ; + lua_g4(21) <= lua_g2(21) or (lua_t2(21) and lua_g2(23) ); + lua_g4(20) <= lua_g2(20) or (lua_t2(20) and lua_g2(22) ); + lua_g4(19) <= lua_g2(19) or (lua_t2(19) and lua_g2(21) ); + lua_g4(18) <= lua_g2(18) or (lua_t2(18) and lua_g2(20) ); + lua_g4(17) <= lua_g2(17) or (lua_t2(17) and lua_g2(19) ); + lua_g4(16) <= lua_g2(16) or (lua_t2(16) and lua_g2(18) ); + lua_t4(23) <= lua_t2(23) ; + lua_t4(22) <= lua_t2(22) ; + lua_t4(21) <= lua_t2(21) and lua_t2(23) ; + lua_t4(20) <= lua_t2(20) and lua_t2(22) ; + lua_t4(19) <= lua_t2(19) and lua_t2(21) ; + lua_t4(18) <= lua_t2(18) and lua_t2(20) ; + lua_t4(17) <= lua_t2(17) and lua_t2(19) ; + lua_t4(16) <= lua_t2(16) and lua_t2(18) ; + lua_g8(23) <= lua_g4(23) ; + lua_g8(22) <= lua_g4(22) ; + lua_g8(21) <= lua_g4(21) ; + lua_g8(20) <= lua_g4(20) ; + lua_g8(19) <= lua_g4(19) or (lua_t4(19) and lua_g4(23) ); + lua_g8(18) <= lua_g4(18) or (lua_t4(18) and lua_g4(22) ); + lua_g8(17) <= lua_g4(17) or (lua_t4(17) and lua_g4(21) ); + lua_g8(16) <= lua_g4(16) or (lua_t4(16) and lua_g4(20) ); + lua_t8(23) <= lua_t4(23) ; + lua_t8(22) <= lua_t4(22) ; + lua_t8(21) <= lua_t4(21) ; + lua_t8(20) <= lua_t4(20) ; + lua_t8(19) <= lua_t4(19) and lua_t4(23) ; + lua_t8(18) <= lua_t4(18) and lua_t4(22) ; + lua_t8(17) <= lua_t4(17) and lua_t4(21) ; + lua_t8(16) <= lua_t4(16) and lua_t4(20) ; + + + + + lua_g2(15) <= lua_g(15) ; + lua_g2(14) <= lua_g(14) or (lua_t(14) and lua_g(15) ); + lua_g2(13) <= lua_g(13) or (lua_t(13) and lua_g(14) ); + lua_g2(12) <= lua_g(12) or (lua_t(12) and lua_g(13) ); + lua_g2(11) <= lua_g(11) or (lua_t(11) and lua_g(12) ); + lua_g2(10) <= lua_g(10) or (lua_t(10) and lua_g(11) ); + lua_g2(9) <= lua_g(9) or (lua_t(9) and lua_g(10) ); + lua_g2(8) <= lua_g(8) or (lua_t(8) and lua_g(9) ); + lua_t2(15) <= lua_t(15) ; + lua_t2(14) <= lua_t(14) and lua_t(15) ; + lua_t2(13) <= lua_t(13) and lua_t(14) ; + lua_t2(12) <= lua_t(12) and lua_t(13) ; + lua_t2(11) <= lua_t(11) and lua_t(12) ; + lua_t2(10) <= lua_t(10) and lua_t(11) ; + lua_t2(9) <= lua_t(9) and lua_t(10) ; + lua_t2(8) <= lua_t(8) and lua_t(9) ; + lua_g4(15) <= lua_g2(15) ; + lua_g4(14) <= lua_g2(14) ; + lua_g4(13) <= lua_g2(13) or (lua_t2(13) and lua_g2(15) ); + lua_g4(12) <= lua_g2(12) or (lua_t2(12) and lua_g2(14) ); + lua_g4(11) <= lua_g2(11) or (lua_t2(11) and lua_g2(13) ); + lua_g4(10) <= lua_g2(10) or (lua_t2(10) and lua_g2(12) ); + lua_g4(9) <= lua_g2(9) or (lua_t2(9) and lua_g2(11) ); + lua_g4(8) <= lua_g2(8) or (lua_t2(8) and lua_g2(10) ); + lua_t4(15) <= lua_t2(15) ; + lua_t4(14) <= lua_t2(14) ; + lua_t4(13) <= lua_t2(13) and lua_t2(15) ; + lua_t4(12) <= lua_t2(12) and lua_t2(14) ; + lua_t4(11) <= lua_t2(11) and lua_t2(13) ; + lua_t4(10) <= lua_t2(10) and lua_t2(12) ; + lua_t4(9) <= lua_t2(9) and lua_t2(11) ; + lua_t4(8) <= lua_t2(8) and lua_t2(10) ; + lua_g8(15) <= lua_g4(15) ; + lua_g8(14) <= lua_g4(14) ; + lua_g8(13) <= lua_g4(13) ; + lua_g8(12) <= lua_g4(12) ; + lua_g8(11) <= lua_g4(11) or (lua_t4(11) and lua_g4(15) ); + lua_g8(10) <= lua_g4(10) or (lua_t4(10) and lua_g4(14) ); + lua_g8(9) <= lua_g4(9) or (lua_t4(9) and lua_g4(13) ); + lua_g8(8) <= lua_g4(8) or (lua_t4(8) and lua_g4(12) ); + lua_t8(15) <= lua_t4(15) ; + lua_t8(14) <= lua_t4(14) ; + lua_t8(13) <= lua_t4(13) ; + lua_t8(12) <= lua_t4(12) ; + lua_t8(11) <= lua_t4(11) and lua_t4(15) ; + lua_t8(10) <= lua_t4(10) and lua_t4(14) ; + lua_t8(9) <= lua_t4(9) and lua_t4(13) ; + lua_t8(8) <= lua_t4(8) and lua_t4(12) ; + + + + + lua_g2(7) <= lua_g(7) ; + lua_g2(6) <= lua_g(6) or (lua_t(6) and lua_g(7) ); + lua_g2(5) <= lua_g(5) or (lua_t(5) and lua_g(6) ); + lua_g2(4) <= lua_g(4) or (lua_t(4) and lua_g(5) ); + lua_g2(3) <= lua_g(3) or (lua_t(3) and lua_g(4) ); + lua_g2(2) <= lua_g(2) or (lua_t(2) and lua_g(3) ); + lua_g2(1) <= lua_g(1) or (lua_t(1) and lua_g(2) ); + lua_t2(7) <= lua_t(7) ; + lua_t2(6) <= lua_t(6) and lua_t(7) ; + lua_t2(5) <= lua_t(5) and lua_t(6) ; + lua_t2(4) <= lua_t(4) and lua_t(5) ; + lua_t2(3) <= lua_t(3) and lua_t(4) ; + lua_t2(2) <= lua_t(2) and lua_t(3) ; + lua_t2(1) <= lua_t(1) and lua_t(2) ; + lua_g4(7) <= lua_g2(7) ; + lua_g4(6) <= lua_g2(6) ; + lua_g4(5) <= lua_g2(5) or (lua_t2(5) and lua_g2(7) ); + lua_g4(4) <= lua_g2(4) or (lua_t2(4) and lua_g2(6) ); + lua_g4(3) <= lua_g2(3) or (lua_t2(3) and lua_g2(5) ); + lua_g4(2) <= lua_g2(2) or (lua_t2(2) and lua_g2(4) ); + lua_g4(1) <= lua_g2(1) or (lua_t2(1) and lua_g2(3) ); + lua_t4(7) <= lua_t2(7) ; + lua_t4(6) <= lua_t2(6) ; + lua_t4(5) <= lua_t2(5) and lua_t2(7) ; + lua_t4(4) <= lua_t2(4) and lua_t2(6) ; + lua_t4(3) <= lua_t2(3) and lua_t2(5) ; + lua_t4(2) <= lua_t2(2) and lua_t2(4) ; + lua_t4(1) <= lua_t2(1) and lua_t2(3) ; + lua_g8(7) <= lua_g4(7) ; + lua_g8(6) <= lua_g4(6) ; + lua_g8(5) <= lua_g4(5) ; + lua_g8(4) <= lua_g4(4) ; + lua_g8(3) <= lua_g4(3) or (lua_t4(3) and lua_g4(7) ); + lua_g8(2) <= lua_g4(2) or (lua_t4(2) and lua_g4(6) ); + lua_g8(1) <= lua_g4(1) or (lua_t4(1) and lua_g4(5) ); + lua_t8(7) <= lua_t4(7) ; + lua_t8(6) <= lua_t4(6) ; + lua_t8(5) <= lua_t4(5) ; + lua_t8(4) <= lua_t4(4) ; + lua_t8(3) <= lua_t4(3) and lua_t4(7) ; + lua_t8(2) <= lua_t4(2) and lua_t4(6) ; + lua_t8(1) <= lua_t4(1) and lua_t4(5) ; + + + + + lua_gt8(1 to 28) <= lua_g8(1 to 28) or lua_t8(1 to 28); + + lua_s1_b(0 to 27) <= not( lua_p(0 to 27) xor lua_gt8(1 to 28) ); + lua_s0_b(0 to 27) <= not( lua_p(0 to 27) xor lua_g8(1 to 28) ); + + + + ex4_lu( 0) <= ( lua_s0_b( 0) and not lua_c08 ) or ( lua_s1_b( 0) and lua_c08 ) ; + ex4_lu( 1) <= ( lua_s0_b( 1) and not lua_c08 ) or ( lua_s1_b( 1) and lua_c08 ) ; + ex4_lu( 2) <= ( lua_s0_b( 2) and not lua_c08 ) or ( lua_s1_b( 2) and lua_c08 ) ; + ex4_lu( 3) <= ( lua_s0_b( 3) and not lua_c08 ) or ( lua_s1_b( 3) and lua_c08 ) ; + ex4_lu( 4) <= ( lua_s0_b( 4) and not lua_c08 ) or ( lua_s1_b( 4) and lua_c08 ) ; + ex4_lu( 5) <= ( lua_s0_b( 5) and not lua_c08 ) or ( lua_s1_b( 5) and lua_c08 ) ; + ex4_lu( 6) <= ( lua_s0_b( 6) and not lua_c08 ) or ( lua_s1_b( 6) and lua_c08 ) ; + ex4_lu( 7) <= ( lua_s0_b( 7) and not lua_c08 ) or ( lua_s1_b( 7) and lua_c08 ) ; + + ex4_lu( 8) <= ( lua_s0_b( 8) and not lua_c16 ) or ( lua_s1_b( 8) and lua_c16 ) ; + ex4_lu( 9) <= ( lua_s0_b( 9) and not lua_c16 ) or ( lua_s1_b( 9) and lua_c16 ) ; + ex4_lu(10) <= ( lua_s0_b(10) and not lua_c16 ) or ( lua_s1_b(10) and lua_c16 ) ; + ex4_lu(11) <= ( lua_s0_b(11) and not lua_c16 ) or ( lua_s1_b(11) and lua_c16 ) ; + ex4_lu(12) <= ( lua_s0_b(12) and not lua_c16 ) or ( lua_s1_b(12) and lua_c16 ) ; + ex4_lu(13) <= ( lua_s0_b(13) and not lua_c16 ) or ( lua_s1_b(13) and lua_c16 ) ; + ex4_lu(14) <= ( lua_s0_b(14) and not lua_c16 ) or ( lua_s1_b(14) and lua_c16 ) ; + ex4_lu(15) <= ( lua_s0_b(15) and not lua_c16 ) or ( lua_s1_b(15) and lua_c16 ) ; + + ex4_lu(16) <= ( lua_s0_b(16) and not lua_c24 ) or ( lua_s1_b(16) and lua_c24 ) ; + ex4_lu(17) <= ( lua_s0_b(17) and not lua_c24 ) or ( lua_s1_b(17) and lua_c24 ) ; + ex4_lu(18) <= ( lua_s0_b(18) and not lua_c24 ) or ( lua_s1_b(18) and lua_c24 ) ; + ex4_lu(19) <= ( lua_s0_b(19) and not lua_c24 ) or ( lua_s1_b(19) and lua_c24 ) ; + ex4_lu(20) <= ( lua_s0_b(20) and not lua_c24 ) or ( lua_s1_b(20) and lua_c24 ) ; + ex4_lu(21) <= ( lua_s0_b(21) and not lua_c24 ) or ( lua_s1_b(21) and lua_c24 ) ; + ex4_lu(22) <= ( lua_s0_b(22) and not lua_c24 ) or ( lua_s1_b(22) and lua_c24 ) ; + ex4_lu(23) <= ( lua_s0_b(23) and not lua_c24 ) or ( lua_s1_b(23) and lua_c24 ) ; + + ex4_lu(24) <= ( lua_s0_b(24) and not lua_c32 ) or ( lua_s1_b(24) and lua_c32 ) ; + ex4_lu(25) <= ( lua_s0_b(25) and not lua_c32 ) or ( lua_s1_b(25) and lua_c32 ) ; + ex4_lu(26) <= ( lua_s0_b(26) and not lua_c32 ) or ( lua_s1_b(26) and lua_c32 ) ; + ex4_lu(27) <= ( lua_s0_b(27) and not lua_c32 ) or ( lua_s1_b(27) and lua_c32 ) ; + + + + lua_g16(3) <= lua_g8(32); + lua_g16(2) <= lua_g8(24) or ( lua_t8(24) and lua_g8(32) ); + lua_g16(1) <= lua_g8(16) or ( lua_t8(16) and lua_g8(24) ); + lua_g16(0) <= lua_g8( 8) or ( lua_t8( 8) and lua_g8(16) ); + + lua_t16(1) <= lua_t8(16) and lua_t8(24) ; + lua_t16(0) <= lua_t8( 8) and lua_t8(16) ; + + lua_c32 <= lua_g16(3); + lua_c24 <= lua_g16(2); + lua_c16 <= lua_g16(1) or ( lua_t16(1) and lua_g16(3) ); + lua_c08 <= lua_g16(0) or ( lua_t16(0) and lua_g16(2) ); + + ex4_recip_2044_dp <= ex4_recip_2044 and ex4_match_en_dp and not ex4_recip_ue1; + ex4_recip_2045_dp <= ex4_recip_2045 and ex4_match_en_dp and not ex4_recip_ue1; + ex4_recip_2046_dp <= ex4_recip_2046 and ex4_match_en_dp and not ex4_recip_ue1; + + ex4_recip_2044_sp <= ex4_recip_2044 and ex4_match_en_sp and not ex4_recip_ue1; + ex4_recip_2045_sp <= ex4_recip_2045 and ex4_match_en_sp and not ex4_recip_ue1; + ex4_recip_2046_sp <= ex4_recip_2046 and ex4_match_en_sp and not ex4_recip_ue1; + + + + + ex4_recip_den <= + ex4_recip_2046_sp or + ex4_recip_2045_sp or + (ex4_lu_sh and ex4_recip_2044_sp) or + ex4_recip_2046_dp or + ex4_recip_2045_dp or + (ex4_lu_sh and ex4_recip_2044_dp); + + + + + ex4_unf_expo <= + (ex4_match_en_sp or ex4_match_en_dp) and + (ex4_recip_2046 or ex4_recip_2045 or ( ex4_recip_2044 and ex4_lu_sh ) ); + + f_tbl_ex4_unf_expo <= ex4_unf_expo ; + + ex4_shlft_1 <= not ex4_recip_2046_dp and not ex4_recip_2045_dp and (ex4_lu_sh and not ex4_recip_2044_dp); + ex4_shlft_0 <= not ex4_recip_2046_dp and not ex4_recip_2045_dp and not(ex4_lu_sh and not ex4_recip_2044_dp); + ex4_shrgt_1 <= ex4_recip_2045_dp ; + ex4_shrgt_2 <= ex4_recip_2046_dp ; + + + + + ex4_sp_chop_24 <= ex4_recip_2046_sp or ex4_recip_2045_sp or ex4_recip_2044_sp ; + ex4_sp_chop_23 <= ex4_recip_2046_sp or ex4_recip_2045_sp ; + ex4_sp_chop_22 <= ex4_recip_2046_sp ; + ex4_sp_chop_21 <= tidn ; + + + ex4_lux(0 to 20) <= ex4_lu(0 to 20); + ex4_lux(21) <= ex4_lu(21) and not ex4_sp_chop_21; + ex4_lux(22) <= ex4_lu(22) and not ex4_sp_chop_22; + ex4_lux(23) <= ex4_lu(23) and not ex4_sp_chop_23; + ex4_lux(24) <= ex4_lu(24) and not ex4_sp_chop_24; + ex4_lux(25 to 27) <= ex4_lu(25 to 27) ; + + + + ex4_lu_nrm(0 to 26) <= + ( (0 to 26=> ex4_shlft_1) and ( ex4_lux(1 to 27) ) ) or + ( (0 to 26=> ex4_shlft_0) and ( ex4_lux(0 to 26) ) ) or + ( (0 to 26=> ex4_shrgt_1) and ( tidn & ex4_lux(0 to 25) ) ) or + ( (0 to 26=> ex4_shrgt_2) and (tidn & tidn & ex4_lux(0 to 24) ) ) ; + + + + + + + ex5_lut_lat: tri_rlmreg_p generic map (width=> 28, expand_type => expand_type) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(5) , + mpw1_b => mpw1_b(5) , + mpw2_b => mpw2_b(1) , + vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_act, + thold_b => thold_0_b, + sg => sg_0, + scout => ex5_lut_so , + scin => ex5_lut_si , + din(0 to 26) => ex4_lu_nrm(0 to 26) , + din(27) => ex4_recip_den , + dout(0 to 26) => ex5_lu(0 to 26) , + dout(27) => ex5_recip_den ); + + f_tbl_ex5_est_frac(0 to 26) <= ex5_lu(0 to 26); + f_tbl_ex5_recip_den <= ex5_recip_den ; + + + + thold_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => thold_1, + q(0) => thold_0 ); + + sg_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => sg_1 , + q(0) => sg_0 ); + + + lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map ( + clkoff_b => clkoff_b, + thold => thold_0, + sg => sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => thold_0_b ); + + + + act_lat: tri_rlmreg_p generic map (width=> 7, expand_type => expand_type) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(4) , + mpw1_b => mpw1_b(4) , + mpw2_b => mpw2_b(0) , + vd => vdd, + gd => gnd, + nclk => nclk, + act => fpu_enable, + thold_b => thold_0_b, + sg => sg_0, + scout => act_so , + scin => act_si , + din(0) => spare_unused(0), + din(1) => spare_unused(1), + din(2) => ex1_act, + din(3) => ex2_act, + din(4) => ex3_act, + din(5) => spare_unused(2), + din(6) => spare_unused(3), + dout(0) => spare_unused(0), + dout(1) => spare_unused(1), + dout(2) => ex2_act, + dout(3) => ex3_act, + dout(4) => ex4_act, + dout(5) => spare_unused(2) , + dout(6) => spare_unused(3) ); + + + tbl_ex3_lcb : tri_lcbnd generic map (expand_type => expand_type) port map( + delay_lclkr => delay_lclkr(3) , + mpw1_b => mpw1_b(3) , + mpw2_b => mpw2_b(0) , + forcee => forcee, + nclk => nclk , + vd => vdd , + gd => gnd , + act => ex2_act , + sg => sg_0 , + thold_b => thold_0_b , + d1clk => tbl_ex3_d1clk , + d2clk => tbl_ex3_d2clk , + lclk => tbl_ex3_lclk ); + + tbl_ex4_lcb : tri_lcbnd generic map (expand_type => expand_type) port map( + delay_lclkr => delay_lclkr(4) , + mpw1_b => mpw1_b(4) , + mpw2_b => mpw2_b(0) , + forcee => forcee, + nclk => nclk , + vd => vdd , + gd => gnd , + act => ex3_act , + sg => sg_0 , + thold_b => thold_0_b , + d1clk => tbl_ex4_d1clk , + d2clk => tbl_ex4_d2clk , + lclk => tbl_ex4_lclk ); + + + + + ex2_lut_si(0 to 5) <= ex2_lut_so(1 to 5) & si; + ex3_lut_e_si(0 to 19) <= ex3_lut_e_so(1 to 19) & ex2_lut_so(0); + ex3_lut_r_si(0 to 14) <= ex3_lut_r_so(1 to 14) & ex3_lut_e_so(0); + ex3_lut_b_si(0 to 15) <= ex3_lut_b_so(1 to 15) & ex3_lut_r_so(0); + ex4_lut_si(0 to 79) <= ex4_lut_so(1 to 79) & ex3_lut_b_so(0); + ex5_lut_si(0 to 27) <= ex5_lut_so(1 to 27) & ex4_lut_so(0); + act_si(0 to 6) <= act_so(1 to 6) & ex5_lut_so(0); + so <= act_so (0) ; + + +end; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_tblmul.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_tblmul.vhdl new file mode 100644 index 0000000..8643297 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_tblmul.vhdl @@ -0,0 +1,1477 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; + use ieee.std_logic_1164.all ; +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; +library support; + use support.power_logic_pkg.all; +library tri; use tri.tri_latches_pkg.all; +library clib; + +entity fuq_tblmul is + generic( expand_type : integer := 2 ); +port( + vdd :inout power_logic; + gnd :inout power_logic; + x :in std_ulogic_vector(1 to 15); + y :in std_ulogic_vector(7 to 22); + z :in std_ulogic_vector(0 to 20); + + + tbl_sum :out std_ulogic_vector(0 to 36); + tbl_car :out std_ulogic_vector(0 to 35) +); + + + +end fuq_tblmul; + +architecture fuq_tblmul of fuq_tblmul is + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal sub_adj_lsb, sub_adj_lsb_b :std_ulogic_vector(1 to 7); + signal sub_adj_msb_b :std_ulogic_vector(1 to 7); + signal sub_adj_msb_7x_b, sub_adj_msb_7x, sub_adj_msb_7y :std_ulogic; + signal s_x, s_x2, s_neg :std_ulogic_vector(0 to 7); + + signal pp0_0 :std_ulogic_vector( 6 to 24); + signal pp0_1 :std_ulogic_vector( 6 to 26); + signal pp0_2 :std_ulogic_vector( 8 to 28); + signal pp0_3 :std_ulogic_vector(10 to 30); + signal pp0_4 :std_ulogic_vector(12 to 32); + signal pp0_5 :std_ulogic_vector(14 to 34); + signal pp0_6 :std_ulogic_vector(16 to 36); + signal pp0_7 :std_ulogic_vector(17 to 36); + + + signal pp1_0_sum :std_ulogic_vector(0 to 26); + signal pp1_0_car :std_ulogic_vector(0 to 24); + signal pp1_1_sum :std_ulogic_vector(8 to 32); + signal pp1_1_car :std_ulogic_vector(9 to 30); + signal pp1_2_sum :std_ulogic_vector(14 to 36); + signal pp1_2_car :std_ulogic_vector(15 to 36); + signal pp1_0_car_unused :std_ulogic; + + + signal pp2_0_sum :std_ulogic_vector(0 to 32); + signal pp2_0_car :std_ulogic_vector(0 to 26); + signal pp2_1_sum :std_ulogic_vector(9 to 36); + signal pp2_1_car :std_ulogic_vector(13 to 36); + signal pp2_0_car_unused :std_ulogic; + + + signal pp3_0_sum :std_ulogic_vector(0 to 36); + signal pp3_0_ko :std_ulogic_vector(8 to 25); + signal pp3_0_car :std_ulogic_vector(0 to 35); + signal pp3_0_car_unused :std_ulogic; + signal z_b :std_ulogic_vector(0 to 20); + signal unused :std_ulogic; + + + + + + + + +begin + + unused <= pp1_0_car_unused or + pp2_0_car_unused or + pp3_0_car_unused or + pp0_0(23) or + pp0_1(25) or + pp0_2(27) or + pp0_3(29) or + pp0_4(31) or + pp0_5(33) or + pp0_6(35) or + pp1_0_car(23) or + pp1_0_sum(25) or + pp1_1_car(28) or + pp1_1_sum(31) or + pp1_2_car(34) or + pp2_0_car(24) or + pp2_0_sum(31) or + pp2_1_car(30) or + pp2_1_car(34) or + s_neg(0) or + pp1_1_car(29) or + pp1_2_car(35) or + pp2_0_car(25) or + pp2_1_car(35) ; + + + + + bd0: entity work.fuq_tblmul_bthdcd(fuq_tblmul_bthdcd) port map( + i0 => tidn , + i1 => x(1) , + i2 => x(2) , + s_neg => s_neg(0) , + s_x => s_x(0) , + s_x2 => s_x2(0) ); + + bd1: entity work.fuq_tblmul_bthdcd(fuq_tblmul_bthdcd) port map( + i0 => x(2) , + i1 => x(3) , + i2 => x(4) , + s_neg => s_neg(1) , + s_x => s_x(1) , + s_x2 => s_x2(1) ); + + bd2: entity work.fuq_tblmul_bthdcd(fuq_tblmul_bthdcd) port map( + i0 => x(4) , + i1 => x(5) , + i2 => x(6) , + s_neg => s_neg(2) , + s_x => s_x(2) , + s_x2 => s_x2(2) ); + + bd3: entity work.fuq_tblmul_bthdcd(fuq_tblmul_bthdcd) port map( + i0 => x(6) , + i1 => x(7) , + i2 => x(8) , + s_neg => s_neg(3) , + s_x => s_x(3) , + s_x2 => s_x2(3) ); + + bd4: entity work.fuq_tblmul_bthdcd(fuq_tblmul_bthdcd) port map( + i0 => x(8) , + i1 => x(9) , + i2 => x(10) , + s_neg => s_neg(4) , + s_x => s_x(4) , + s_x2 => s_x2(4) ); + + bd5: entity work.fuq_tblmul_bthdcd(fuq_tblmul_bthdcd) port map( + i0 => x(10) , + i1 => x(11) , + i2 => x(12) , + s_neg => s_neg(5) , + s_x => s_x(5) , + s_x2 => s_x2(5) ); + + bd6: entity work.fuq_tblmul_bthdcd(fuq_tblmul_bthdcd) port map( + i0 => x(12) , + i1 => x(13) , + i2 => x(14) , + s_neg => s_neg(6) , + s_x => s_x(6) , + s_x2 => s_x2(6) ); + + bd7: entity work.fuq_tblmul_bthdcd(fuq_tblmul_bthdcd) port map( + i0 => x(14) , + i1 => x(15) , + i2 => tidn , + s_neg => s_neg(7) , + s_x => s_x(7) , + s_x2 => s_x2(7) ); + + + + + + + sa1_1_lsb: sub_adj_lsb_b(1) <= not( s_neg(1) and ( s_x(1) or s_x2(1) ) ); + sa2_1_lsb: sub_adj_lsb_b(2) <= not( s_neg(2) and ( s_x(2) or s_x2(2) ) ); + sa3_1_lsb: sub_adj_lsb_b(3) <= not( s_neg(3) and ( s_x(3) or s_x2(3) ) ); + sa4_1_lsb: sub_adj_lsb_b(4) <= not( s_neg(4) and ( s_x(4) or s_x2(4) ) ); + sa5_1_lsb: sub_adj_lsb_b(5) <= not( s_neg(5) and ( s_x(5) or s_x2(5) ) ); + sa6_1_lsb: sub_adj_lsb_b(6) <= not( s_neg(6) and ( s_x(6) or s_x2(6) ) ); + sa7_1_lsb: sub_adj_lsb_b(7) <= not( s_neg(7) and ( s_x(7) or s_x2(7) ) ); + + sa1_2_lsb: sub_adj_lsb (1) <= not sub_adj_lsb_b(1); + sa2_2_lsb: sub_adj_lsb (2) <= not sub_adj_lsb_b(2); + sa3_2_lsb: sub_adj_lsb (3) <= not sub_adj_lsb_b(3); + sa4_2_lsb: sub_adj_lsb (4) <= not sub_adj_lsb_b(4); + sa5_2_lsb: sub_adj_lsb (5) <= not sub_adj_lsb_b(5); + sa6_2_lsb: sub_adj_lsb (6) <= not sub_adj_lsb_b(6); + sa7_2_lsb: sub_adj_lsb (7) <= not sub_adj_lsb_b(7); + + sa1_1_msb: sub_adj_msb_b(1) <= not( s_neg(1) and ( s_x(1) or s_x2(1) ) ); + sa2_1_msb: sub_adj_msb_b(2) <= not( s_neg(2) and ( s_x(2) or s_x2(2) ) ); + sa3_1_msb: sub_adj_msb_b(3) <= not( s_neg(3) and ( s_x(3) or s_x2(3) ) ); + sa4_1_msb: sub_adj_msb_b(4) <= not( s_neg(4) and ( s_x(4) or s_x2(4) ) ); + sa5_1_msb: sub_adj_msb_b(5) <= not( s_neg(5) and ( s_x(5) or s_x2(5) ) ); + sa6_1_msb: sub_adj_msb_b(6) <= not( s_neg(6) and ( s_x(6) or s_x2(6) ) ); + sa7_1_msb: sub_adj_msb_b(7) <= not( s_neg(7) and ( s_x(7) or s_x2(7) ) ); + sa7x_1_msb: sub_adj_msb_7x_b <= not( s_neg(7) and ( s_x(7) or s_x2(7) ) ); + + sa7x_2_msb: sub_adj_msb_7x <= not sub_adj_msb_7x_b ; + sa7y_2_msb: sub_adj_msb_7y <= not sub_adj_msb_7x_b ; + + + bm0: entity work.fuq_tblmul_bthrow(fuq_tblmul_bthrow) port map( + s_neg => tidn , + s_x => s_x(0) , + s_x2 => s_x2(0) , + x => y(7 to 22) , + q => pp0_0(6 to 22) ); + pp0_0(23) <= tidn; + pp0_0(24) <= sub_adj_lsb(1); + + pp0_1(6) <= tiup; + pp0_1(7) <= sub_adj_msb_b(1); + bm1: entity work.fuq_tblmul_bthrow(fuq_tblmul_bthrow) port map( + s_neg => s_neg(1) , + s_x => s_x(1) , + s_x2 => s_x2(1) , + x => y(7 to 22) , + q => pp0_1(8 to 24) ); + pp0_1(25) <= tidn; + pp0_1(26) <= sub_adj_lsb(2); + + pp0_2(8) <= tiup; + pp0_2(9) <= sub_adj_msb_b(2); + bm2: entity work.fuq_tblmul_bthrow(fuq_tblmul_bthrow) port map( + s_neg => s_neg(2) , + s_x => s_x(2) , + s_x2 => s_x2(2) , + x => y(7 to 22) , + q => pp0_2(10 to 26) ); + pp0_2(27) <= tidn; + pp0_2(28) <= sub_adj_lsb(3); + + pp0_3(10) <= tiup; + pp0_3(11) <= sub_adj_msb_b(3); + bm3: entity work.fuq_tblmul_bthrow(fuq_tblmul_bthrow) port map( + s_neg => s_neg(3) , + s_x => s_x(3) , + s_x2 => s_x2(3) , + x => y(7 to 22) , + q => pp0_3(12 to 28) ); + pp0_3(29) <= tidn; + pp0_3(30) <= sub_adj_lsb(4); + + pp0_4(12) <= tiup; + pp0_4(13) <= sub_adj_msb_b(4); + bm4: entity work.fuq_tblmul_bthrow(fuq_tblmul_bthrow) port map( + s_neg => s_neg(4) , + s_x => s_x(4) , + s_x2 => s_x2(4) , + x => y(7 to 22) , + q => pp0_4(14 to 30) ); + pp0_4(31) <= tidn; + pp0_4(32) <= sub_adj_lsb(5); + + pp0_5(14) <= tiup; + pp0_5(15) <= sub_adj_msb_b(5); + bm5: entity work.fuq_tblmul_bthrow(fuq_tblmul_bthrow) port map( + s_neg => s_neg(5) , + s_x => s_x(5) , + s_x2 => s_x2(5) , + x => y(7 to 22) , + q => pp0_5(16 to 32) ); + pp0_5(33) <= tidn; + pp0_5(34) <= sub_adj_lsb(6); + + pp0_6(16) <= tiup; + pp0_6(17) <= sub_adj_msb_b(6); + bm6: entity work.fuq_tblmul_bthrow(fuq_tblmul_bthrow) port map( + s_neg => s_neg(6) , + s_x => s_x(6) , + s_x2 => s_x2(6) , + x => y(7 to 22) , + q => pp0_6(18 to 34) ); + pp0_6(35) <= tidn; + pp0_6(36) <= sub_adj_lsb(7); + + pp0_7(17) <= sub_adj_msb_b(7); + pp0_7(18) <= sub_adj_msb_7x; + pp0_7(19) <= sub_adj_msb_7y; + bm7: entity work.fuq_tblmul_bthrow(fuq_tblmul_bthrow) port map( + s_neg => s_neg(7) , + s_x => s_x(7) , + s_x2 => s_x2(7) , + x => y(7 to 22) , + q => pp0_7(20 to 36) ); + + + + + + + + + + z_b(0 to 20) <= not z(0 to 20); + + + pp1_0_sum(26) <= pp0_1(26) ; + pp1_0_sum(25) <= tidn ; + pp1_0_sum(24) <= pp0_0(24) ; + pp1_0_car(24) <= pp0_1(24) ; + pp1_0_sum(23) <= pp0_1(23) ; + pp1_0_car(23) <= tidn ; + pp1_0_sum(22) <= pp0_0(22) ; + pp1_0_car(22) <= pp0_1(22) ; + pp1_0_sum(21) <= pp0_0(21) ; + pp1_0_car(21) <= pp0_1(21) ; + pp1_0_car(20) <= tidn ; + pp1_0_csa_20: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => z_b(20) , + b => pp0_0(20) , + c => pp0_1(20) , + sum => pp1_0_sum(20) , + car => pp1_0_car(19) ); + pp1_0_csa_19: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => z_b(19) , + b => pp0_0(19) , + c => pp0_1(19) , + sum => pp1_0_sum(19) , + car => pp1_0_car(18) ); + pp1_0_csa_18: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => z_b(18) , + b => pp0_0(18) , + c => pp0_1(18) , + sum => pp1_0_sum(18) , + car => pp1_0_car(17) ); + pp1_0_csa_17: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => z_b(17) , + b => pp0_0(17) , + c => pp0_1(17) , + sum => pp1_0_sum(17) , + car => pp1_0_car(16) ); + pp1_0_csa_16: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => z_b(16) , + b => pp0_0(16) , + c => pp0_1(16) , + sum => pp1_0_sum(16) , + car => pp1_0_car(15) ); + pp1_0_csa_15: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => z_b(15) , + b => pp0_0(15) , + c => pp0_1(15) , + sum => pp1_0_sum(15) , + car => pp1_0_car(14) ); + pp1_0_csa_14: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => z_b(14) , + b => pp0_0(14) , + c => pp0_1(14) , + sum => pp1_0_sum(14) , + car => pp1_0_car(13) ); + pp1_0_csa_13: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => z_b(13) , + b => pp0_0(13) , + c => pp0_1(13) , + sum => pp1_0_sum(13) , + car => pp1_0_car(12) ); + pp1_0_csa_12: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => z_b(12) , + b => pp0_0(12) , + c => pp0_1(12) , + sum => pp1_0_sum(12) , + car => pp1_0_car(11) ); + pp1_0_csa_11: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => z_b(11) , + b => pp0_0(11) , + c => pp0_1(11) , + sum => pp1_0_sum(11) , + car => pp1_0_car(10) ); + pp1_0_csa_10: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => z_b(10) , + b => pp0_0(10) , + c => pp0_1(10) , + sum => pp1_0_sum(10) , + car => pp1_0_car(9) ); + pp1_0_csa_9: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => z_b(9) , + b => pp0_0(9) , + c => pp0_1(9) , + sum => pp1_0_sum(9) , + car => pp1_0_car(8) ); + pp1_0_csa_8: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => z_b(8) , + b => pp0_0(8) , + c => pp0_1(8) , + sum => pp1_0_sum(8) , + car => pp1_0_car(7) ); + pp1_0_csa_7: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => z_b(7) , + b => pp0_0(7) , + c => pp0_1(7) , + sum => pp1_0_sum(7) , + car => pp1_0_car(6) ); + pp1_0_csa_6: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => z_b(6) , + b => pp0_0(6) , + c => pp0_1(6) , + sum => pp1_0_sum(6) , + car => pp1_0_car(5) ); + pp1_0_csa_5: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => z_b(5) , + b => tiup , + sum => pp1_0_sum(5) , + car => pp1_0_car(4) ); + pp1_0_csa_4: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => z_b(4) , + b => tiup , + sum => pp1_0_sum(4) , + car => pp1_0_car(3) ); + pp1_0_csa_3: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => z_b(3) , + b => tiup , + sum => pp1_0_sum(3) , + car => pp1_0_car(2) ); + pp1_0_csa_2: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => z_b(2) , + b => tiup , + sum => pp1_0_sum(2) , + car => pp1_0_car(1) ); + pp1_0_csa_1: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => z_b(1) , + b => tiup , + sum => pp1_0_sum(1) , + car => pp1_0_car(0) ); + pp1_0_csa_0: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => z_b(0) , + b => tiup , + sum => pp1_0_sum(0) , + car => pp1_0_car_unused ); + + + + pp1_1_sum(32) <= pp0_4(32) ; + pp1_1_sum(31) <= tidn ; + pp1_1_sum(30) <= pp0_3(30) ; + pp1_1_car(30) <= pp0_4(30) ; + pp1_1_sum(29) <= pp0_4(29) ; + pp1_1_car(29) <= tidn ; + pp1_1_car(28) <= tidn ; + pp1_1_csa_28: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_2(28) , + b => pp0_3(28) , + c => pp0_4(28) , + sum => pp1_1_sum(28) , + car => pp1_1_car(27) ); + pp1_1_csa_27: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp0_3(27) , + b => pp0_4(27) , + sum => pp1_1_sum(27) , + car => pp1_1_car(26) ); + pp1_1_csa_26: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_2(26) , + b => pp0_3(26) , + c => pp0_4(26) , + sum => pp1_1_sum(26) , + car => pp1_1_car(25) ); + pp1_1_csa_25: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_2(25) , + b => pp0_3(25) , + c => pp0_4(25) , + sum => pp1_1_sum(25) , + car => pp1_1_car(24) ); + pp1_1_csa_24: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_2(24) , + b => pp0_3(24) , + c => pp0_4(24) , + sum => pp1_1_sum(24) , + car => pp1_1_car(23) ); + pp1_1_csa_23: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_2(23) , + b => pp0_3(23) , + c => pp0_4(23) , + sum => pp1_1_sum(23) , + car => pp1_1_car(22) ); + pp1_1_csa_22: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_2(22) , + b => pp0_3(22) , + c => pp0_4(22) , + sum => pp1_1_sum(22) , + car => pp1_1_car(21) ); + pp1_1_csa_21: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_2(21) , + b => pp0_3(21) , + c => pp0_4(21) , + sum => pp1_1_sum(21) , + car => pp1_1_car(20) ); + pp1_1_csa_20: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_2(20) , + b => pp0_3(20) , + c => pp0_4(20) , + sum => pp1_1_sum(20) , + car => pp1_1_car(19) ); + pp1_1_csa_19: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_2(19) , + b => pp0_3(19) , + c => pp0_4(19) , + sum => pp1_1_sum(19) , + car => pp1_1_car(18) ); + pp1_1_csa_18: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_2(18) , + b => pp0_3(18) , + c => pp0_4(18) , + sum => pp1_1_sum(18) , + car => pp1_1_car(17) ); + pp1_1_csa_17: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_2(17) , + b => pp0_3(17) , + c => pp0_4(17) , + sum => pp1_1_sum(17) , + car => pp1_1_car(16) ); + pp1_1_csa_16: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_2(16) , + b => pp0_3(16) , + c => pp0_4(16) , + sum => pp1_1_sum(16) , + car => pp1_1_car(15) ); + pp1_1_csa_15: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_2(15) , + b => pp0_3(15) , + c => pp0_4(15) , + sum => pp1_1_sum(15) , + car => pp1_1_car(14) ); + pp1_1_csa_14: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_2(14) , + b => pp0_3(14) , + c => pp0_4(14) , + sum => pp1_1_sum(14) , + car => pp1_1_car(13) ); + pp1_1_csa_13: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_2(13) , + b => pp0_3(13) , + c => pp0_4(13) , + sum => pp1_1_sum(13) , + car => pp1_1_car(12) ); + pp1_1_csa_12: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_2(12) , + b => pp0_3(12) , + c => pp0_4(12) , + sum => pp1_1_sum(12) , + car => pp1_1_car(11) ); + pp1_1_csa_11: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp0_2(11) , + b => pp0_3(11) , + sum => pp1_1_sum(11) , + car => pp1_1_car(10) ); + pp1_1_csa_10: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp0_2(10) , + b => pp0_3(10) , + sum => pp1_1_sum(10) , + car => pp1_1_car(9) ); + pp1_1_sum(9) <= pp0_2(9) ; + pp1_1_sum(8) <= pp0_2(8) ; + + + + pp1_2_sum(36) <= pp0_6(36) ; + pp1_2_car(36) <= pp0_7(36) ; + pp1_2_sum(35) <= pp0_7(35) ; + pp1_2_car(35) <= tidn ; + pp1_2_car(34) <= tidn ; + pp1_2_csa_34: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_5(34) , + b => pp0_6(34) , + c => pp0_7(34) , + sum => pp1_2_sum(34) , + car => pp1_2_car(33) ); + pp1_2_csa_33: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp0_6(33) , + b => pp0_7(33) , + sum => pp1_2_sum(33) , + car => pp1_2_car(32) ); + pp1_2_csa_32: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_5(32) , + b => pp0_6(32) , + c => pp0_7(32) , + sum => pp1_2_sum(32) , + car => pp1_2_car(31) ); + pp1_2_csa_31: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_5(31) , + b => pp0_6(31) , + c => pp0_7(31) , + sum => pp1_2_sum(31) , + car => pp1_2_car(30) ); + pp1_2_csa_30: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_5(30) , + b => pp0_6(30) , + c => pp0_7(30) , + sum => pp1_2_sum(30) , + car => pp1_2_car(29) ); + pp1_2_csa_29: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_5(29) , + b => pp0_6(29) , + c => pp0_7(29) , + sum => pp1_2_sum(29) , + car => pp1_2_car(28) ); + pp1_2_csa_28: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_5(28) , + b => pp0_6(28) , + c => pp0_7(28) , + sum => pp1_2_sum(28) , + car => pp1_2_car(27) ); + pp1_2_csa_27: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_5(27) , + b => pp0_6(27) , + c => pp0_7(27) , + sum => pp1_2_sum(27) , + car => pp1_2_car(26) ); + pp1_2_csa_26: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_5(26) , + b => pp0_6(26) , + c => pp0_7(26) , + sum => pp1_2_sum(26) , + car => pp1_2_car(25) ); + pp1_2_csa_25: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_5(25) , + b => pp0_6(25) , + c => pp0_7(25) , + sum => pp1_2_sum(25) , + car => pp1_2_car(24) ); + pp1_2_csa_24: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_5(24) , + b => pp0_6(24) , + c => pp0_7(24) , + sum => pp1_2_sum(24) , + car => pp1_2_car(23) ); + pp1_2_csa_23: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_5(23) , + b => pp0_6(23) , + c => pp0_7(23) , + sum => pp1_2_sum(23) , + car => pp1_2_car(22) ); + pp1_2_csa_22: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_5(22) , + b => pp0_6(22) , + c => pp0_7(22) , + sum => pp1_2_sum(22) , + car => pp1_2_car(21) ); + pp1_2_csa_21: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_5(21) , + b => pp0_6(21) , + c => pp0_7(21) , + sum => pp1_2_sum(21) , + car => pp1_2_car(20) ); + pp1_2_csa_20: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_5(20) , + b => pp0_6(20) , + c => pp0_7(20) , + sum => pp1_2_sum(20) , + car => pp1_2_car(19) ); + pp1_2_csa_19: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_5(19) , + b => pp0_6(19) , + c => pp0_7(19) , + sum => pp1_2_sum(19) , + car => pp1_2_car(18) ); + pp1_2_csa_18: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_5(18) , + b => pp0_6(18) , + c => pp0_7(18) , + sum => pp1_2_sum(18) , + car => pp1_2_car(17) ); + pp1_2_csa_17: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_5(17) , + b => pp0_6(17) , + c => pp0_7(17) , + sum => pp1_2_sum(17) , + car => pp1_2_car(16) ); + pp1_2_csa_16: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp0_5(16) , + b => pp0_6(16) , + sum => pp1_2_sum(16) , + car => pp1_2_car(15) ); + pp1_2_sum(15) <= pp0_5(15) ; + pp1_2_sum(14) <= pp0_5(14) ; + + + + + + + + + + pp2_0_sum(32) <= pp1_1_sum(32) ; + pp2_0_sum(31) <= tidn ; + pp2_0_sum(30) <= pp1_1_sum(30) ; + pp2_0_sum(29) <= pp1_1_sum(29) ; + pp2_0_sum(28) <= pp1_1_sum(28) ; + pp2_0_sum(27) <= pp1_1_sum(27) ; + pp2_0_sum(26) <= pp1_0_sum(26) ; + pp2_0_car(26) <= pp1_1_sum(26) ; + pp2_0_sum(25) <= pp1_1_sum(25) ; + pp2_0_car(25) <= tidn ; + pp2_0_car(24) <= tidn ; + pp2_0_csa_24: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp1_0_sum(24) , + b => pp1_0_car(24) , + c => pp1_1_sum(24) , + sum => pp2_0_sum(24) , + car => pp2_0_car(23) ); + pp2_0_csa_23: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp1_0_sum(23) , + b => pp1_1_sum(23) , + sum => pp2_0_sum(23) , + car => pp2_0_car(22) ); + pp2_0_csa_22: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp1_0_sum(22) , + b => pp1_0_car(22) , + c => pp1_1_sum(22) , + sum => pp2_0_sum(22) , + car => pp2_0_car(21) ); + pp2_0_csa_21: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp1_0_sum(21) , + b => pp1_0_car(21) , + c => pp1_1_sum(21) , + sum => pp2_0_sum(21) , + car => pp2_0_car(20) ); + pp2_0_csa_20: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp1_0_sum(20) , + b => pp1_0_car(20) , + c => pp1_1_sum(20) , + sum => pp2_0_sum(20) , + car => pp2_0_car(19) ); + pp2_0_csa_19: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp1_0_sum(19) , + b => pp1_0_car(19) , + c => pp1_1_sum(19) , + sum => pp2_0_sum(19) , + car => pp2_0_car(18) ); + pp2_0_csa_18: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp1_0_sum(18) , + b => pp1_0_car(18) , + c => pp1_1_sum(18) , + sum => pp2_0_sum(18) , + car => pp2_0_car(17) ); + pp2_0_csa_17: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp1_0_sum(17) , + b => pp1_0_car(17) , + c => pp1_1_sum(17) , + sum => pp2_0_sum(17) , + car => pp2_0_car(16) ); + pp2_0_csa_16: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp1_0_sum(16) , + b => pp1_0_car(16) , + c => pp1_1_sum(16) , + sum => pp2_0_sum(16) , + car => pp2_0_car(15) ); + pp2_0_csa_15: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp1_0_sum(15) , + b => pp1_0_car(15) , + c => pp1_1_sum(15) , + sum => pp2_0_sum(15) , + car => pp2_0_car(14) ); + pp2_0_csa_14: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp1_0_sum(14) , + b => pp1_0_car(14) , + c => pp1_1_sum(14) , + sum => pp2_0_sum(14) , + car => pp2_0_car(13) ); + pp2_0_csa_13: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp1_0_sum(13) , + b => pp1_0_car(13) , + c => pp1_1_sum(13) , + sum => pp2_0_sum(13) , + car => pp2_0_car(12) ); + pp2_0_csa_12: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp1_0_sum(12) , + b => pp1_0_car(12) , + c => pp1_1_sum(12) , + sum => pp2_0_sum(12) , + car => pp2_0_car(11) ); + pp2_0_csa_11: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp1_0_sum(11) , + b => pp1_0_car(11) , + c => pp1_1_sum(11) , + sum => pp2_0_sum(11) , + car => pp2_0_car(10) ); + pp2_0_csa_10: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp1_0_sum(10) , + b => pp1_0_car(10) , + c => pp1_1_sum(10) , + sum => pp2_0_sum(10) , + car => pp2_0_car(9) ); + pp2_0_csa_9: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp1_0_sum(9) , + b => pp1_0_car(9) , + c => pp1_1_sum(9) , + sum => pp2_0_sum(9) , + car => pp2_0_car(8) ); + pp2_0_csa_8: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp1_0_sum(8) , + b => pp1_0_car(8) , + c => pp1_1_sum(8) , + sum => pp2_0_sum(8) , + car => pp2_0_car(7) ); + pp2_0_csa_7: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp1_0_sum(7) , + b => pp1_0_car(7) , + sum => pp2_0_sum(7) , + car => pp2_0_car(6) ); + pp2_0_csa_6: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp1_0_sum(6) , + b => pp1_0_car(6) , + sum => pp2_0_sum(6) , + car => pp2_0_car(5) ); + pp2_0_csa_5: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp1_0_sum(5) , + b => pp1_0_car(5) , + sum => pp2_0_sum(5) , + car => pp2_0_car(4) ); + pp2_0_csa_4: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp1_0_sum(4) , + b => pp1_0_car(4) , + sum => pp2_0_sum(4) , + car => pp2_0_car(3) ); + pp2_0_csa_3: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp1_0_sum(3) , + b => pp1_0_car(3) , + sum => pp2_0_sum(3) , + car => pp2_0_car(2) ); + pp2_0_csa_2: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp1_0_sum(2) , + b => pp1_0_car(2) , + sum => pp2_0_sum(2) , + car => pp2_0_car(1) ); + pp2_0_csa_1: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp1_0_sum(1) , + b => pp1_0_car(1) , + sum => pp2_0_sum(1) , + car => pp2_0_car(0) ); + pp2_0_csa_0: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp1_0_sum(0) , + b => pp1_0_car(0) , + sum => pp2_0_sum(0) , + car => pp2_0_car_unused ); + + + + pp2_1_sum(36) <= pp1_2_sum(36) ; + pp2_1_car(36) <= pp1_2_car(36) ; + pp2_1_sum(35) <= pp1_2_sum(35) ; + pp2_1_car(35) <= tidn ; + pp2_1_sum(34) <= pp1_2_sum(34) ; + pp2_1_car(34) <= tidn ; + pp2_1_sum(33) <= pp1_2_sum(33) ; + pp2_1_car(33) <= pp1_2_car(33) ; + pp2_1_sum(32) <= pp1_2_sum(32) ; + pp2_1_car(32) <= pp1_2_car(32) ; + pp2_1_sum(31) <= pp1_2_sum(31) ; + pp2_1_car(31) <= pp1_2_car(31) ; + pp2_1_car(30) <= tidn ; + pp2_1_csa_30: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp1_1_car(30) , + b => pp1_2_sum(30) , + c => pp1_2_car(30) , + sum => pp2_1_sum(30) , + car => pp2_1_car(29) ); + pp2_1_csa_29: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp1_2_sum(29) , + b => pp1_2_car(29) , + sum => pp2_1_sum(29) , + car => pp2_1_car(28) ); + pp2_1_csa_28: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp1_2_sum(28) , + b => pp1_2_car(28) , + sum => pp2_1_sum(28) , + car => pp2_1_car(27) ); + pp2_1_csa_27: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp1_1_car(27) , + b => pp1_2_sum(27) , + c => pp1_2_car(27) , + sum => pp2_1_sum(27) , + car => pp2_1_car(26) ); + pp2_1_csa_26: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp1_1_car(26) , + b => pp1_2_sum(26) , + c => pp1_2_car(26) , + sum => pp2_1_sum(26) , + car => pp2_1_car(25) ); + pp2_1_csa_25: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp1_1_car(25) , + b => pp1_2_sum(25) , + c => pp1_2_car(25) , + sum => pp2_1_sum(25) , + car => pp2_1_car(24) ); + pp2_1_csa_24: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp1_1_car(24) , + b => pp1_2_sum(24) , + c => pp1_2_car(24) , + sum => pp2_1_sum(24) , + car => pp2_1_car(23) ); + pp2_1_csa_23: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp1_1_car(23) , + b => pp1_2_sum(23) , + c => pp1_2_car(23) , + sum => pp2_1_sum(23) , + car => pp2_1_car(22) ); + pp2_1_csa_22: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp1_1_car(22) , + b => pp1_2_sum(22) , + c => pp1_2_car(22) , + sum => pp2_1_sum(22) , + car => pp2_1_car(21) ); + pp2_1_csa_21: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp1_1_car(21) , + b => pp1_2_sum(21) , + c => pp1_2_car(21) , + sum => pp2_1_sum(21) , + car => pp2_1_car(20) ); + pp2_1_csa_20: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp1_1_car(20) , + b => pp1_2_sum(20) , + c => pp1_2_car(20) , + sum => pp2_1_sum(20) , + car => pp2_1_car(19) ); + pp2_1_csa_19: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp1_1_car(19) , + b => pp1_2_sum(19) , + c => pp1_2_car(19) , + sum => pp2_1_sum(19) , + car => pp2_1_car(18) ); + pp2_1_csa_18: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp1_1_car(18) , + b => pp1_2_sum(18) , + c => pp1_2_car(18) , + sum => pp2_1_sum(18) , + car => pp2_1_car(17) ); + pp2_1_csa_17: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp1_1_car(17) , + b => pp1_2_sum(17) , + c => pp1_2_car(17) , + sum => pp2_1_sum(17) , + car => pp2_1_car(16) ); + pp2_1_csa_16: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp1_1_car(16) , + b => pp1_2_sum(16) , + c => pp1_2_car(16) , + sum => pp2_1_sum(16) , + car => pp2_1_car(15) ); + pp2_1_csa_15: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp1_1_car(15) , + b => pp1_2_sum(15) , + c => pp1_2_car(15) , + sum => pp2_1_sum(15) , + car => pp2_1_car(14) ); + pp2_1_csa_14: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp1_1_car(14) , + b => pp1_2_sum(14) , + sum => pp2_1_sum(14) , + car => pp2_1_car(13) ); + pp2_1_sum(13) <= pp1_1_car(13) ; + pp2_1_sum(12) <= pp1_1_car(12) ; + pp2_1_sum(11) <= pp1_1_car(11) ; + pp2_1_sum(10) <= pp1_1_car(10) ; + pp2_1_sum(9) <= pp1_1_car(9) ; + + + + + + + + + pp3_0_csa_36: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp2_1_sum(36) , + b => pp2_1_car(36) , + sum => pp3_0_sum(36) , + car => pp3_0_car(35) ); + pp3_0_sum(35) <= pp2_1_sum(35) ; + pp3_0_sum(34) <= pp2_1_sum(34) ; + pp3_0_car(34) <= tidn ; + pp3_0_sum(33) <= pp2_1_sum(33) ; + pp3_0_car(33) <= pp2_1_car(33) ; + pp3_0_car(32) <= tidn ; + pp3_0_csa_32: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp2_0_sum(32) , + b => pp2_1_sum(32) , + c => pp2_1_car(32) , + sum => pp3_0_sum(32) , + car => pp3_0_car(31) ); + pp3_0_csa_31: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp2_1_sum(31) , + b => pp2_1_car(31) , + sum => pp3_0_sum(31) , + car => pp3_0_car(30) ); + pp3_0_csa_30: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp2_0_sum(30) , + b => pp2_1_sum(30) , + sum => pp3_0_sum(30) , + car => pp3_0_car(29) ); + pp3_0_csa_29: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp2_0_sum(29) , + b => pp2_1_sum(29) , + c => pp2_1_car(29) , + sum => pp3_0_sum(29) , + car => pp3_0_car(28) ); + pp3_0_csa_28: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp2_0_sum(28) , + b => pp2_1_sum(28) , + c => pp2_1_car(28) , + sum => pp3_0_sum(28) , + car => pp3_0_car(27) ); + pp3_0_csa_27: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp2_0_sum(27) , + b => pp2_1_sum(27) , + c => pp2_1_car(27) , + sum => pp3_0_sum(27) , + car => pp3_0_car(26) ); + pp3_0_csa_26: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp2_0_sum(26) , + b => pp2_0_car(26) , + c => pp2_1_sum(26) , + d => pp2_1_car(26) , + ki => tidn , + ko => pp3_0_ko(25) , + sum => pp3_0_sum(26) , + car => pp3_0_car(25) ); + pp3_0_csa_25: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp2_0_sum(25) , + b => tidn , + c => pp2_1_sum(25) , + d => pp2_1_car(25) , + ki => pp3_0_ko(25) , + ko => pp3_0_ko(24) , + sum => pp3_0_sum(25) , + car => pp3_0_car(24) ); + pp3_0_csa_24: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp2_0_sum(24) , + b => tidn , + c => pp2_1_sum(24) , + d => pp2_1_car(24) , + ki => pp3_0_ko(24) , + ko => pp3_0_ko(23) , + sum => pp3_0_sum(24) , + car => pp3_0_car(23) ); + pp3_0_csa_23: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp2_0_sum(23) , + b => pp2_0_car(23) , + c => pp2_1_sum(23) , + d => pp2_1_car(23) , + ki => pp3_0_ko(23) , + ko => pp3_0_ko(22) , + sum => pp3_0_sum(23) , + car => pp3_0_car(22) ); + pp3_0_csa_22: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp2_0_sum(22) , + b => pp2_0_car(22) , + c => pp2_1_sum(22) , + d => pp2_1_car(22) , + ki => pp3_0_ko(22) , + ko => pp3_0_ko(21) , + sum => pp3_0_sum(22) , + car => pp3_0_car(21) ); + pp3_0_csa_21: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp2_0_sum(21) , + b => pp2_0_car(21) , + c => pp2_1_sum(21) , + d => pp2_1_car(21) , + ki => pp3_0_ko(21) , + ko => pp3_0_ko(20) , + sum => pp3_0_sum(21) , + car => pp3_0_car(20) ); + pp3_0_csa_20: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp2_0_sum(20) , + b => pp2_0_car(20) , + c => pp2_1_sum(20) , + d => pp2_1_car(20) , + ki => pp3_0_ko(20) , + ko => pp3_0_ko(19) , + sum => pp3_0_sum(20) , + car => pp3_0_car(19) ); + pp3_0_csa_19: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp2_0_sum(19) , + b => pp2_0_car(19) , + c => pp2_1_sum(19) , + d => pp2_1_car(19) , + ki => pp3_0_ko(19) , + ko => pp3_0_ko(18) , + sum => pp3_0_sum(19) , + car => pp3_0_car(18) ); + pp3_0_csa_18: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp2_0_sum(18) , + b => pp2_0_car(18) , + c => pp2_1_sum(18) , + d => pp2_1_car(18) , + ki => pp3_0_ko(18) , + ko => pp3_0_ko(17) , + sum => pp3_0_sum(18) , + car => pp3_0_car(17) ); + pp3_0_csa_17: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp2_0_sum(17) , + b => pp2_0_car(17) , + c => pp2_1_sum(17) , + d => pp2_1_car(17) , + ki => pp3_0_ko(17) , + ko => pp3_0_ko(16) , + sum => pp3_0_sum(17) , + car => pp3_0_car(16) ); + pp3_0_csa_16: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp2_0_sum(16) , + b => pp2_0_car(16) , + c => pp2_1_sum(16) , + d => pp2_1_car(16) , + ki => pp3_0_ko(16) , + ko => pp3_0_ko(15) , + sum => pp3_0_sum(16) , + car => pp3_0_car(15) ); + pp3_0_csa_15: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp2_0_sum(15) , + b => pp2_0_car(15) , + c => pp2_1_sum(15) , + d => pp2_1_car(15) , + ki => pp3_0_ko(15) , + ko => pp3_0_ko(14) , + sum => pp3_0_sum(15) , + car => pp3_0_car(14) ); + pp3_0_csa_14: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp2_0_sum(14) , + b => pp2_0_car(14) , + c => pp2_1_sum(14) , + d => pp2_1_car(14) , + ki => pp3_0_ko(14) , + ko => pp3_0_ko(13) , + sum => pp3_0_sum(14) , + car => pp3_0_car(13) ); + pp3_0_csa_13: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp2_0_sum(13) , + b => pp2_0_car(13) , + c => pp2_1_sum(13) , + d => pp2_1_car(13) , + ki => pp3_0_ko(13) , + ko => pp3_0_ko(12) , + sum => pp3_0_sum(13) , + car => pp3_0_car(12) ); + pp3_0_csa_12: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp2_0_sum(12) , + b => pp2_0_car(12) , + c => pp2_1_sum(12) , + d => tidn , + ki => pp3_0_ko(12) , + ko => pp3_0_ko(11) , + sum => pp3_0_sum(12) , + car => pp3_0_car(11) ); + pp3_0_csa_11: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp2_0_sum(11) , + b => pp2_0_car(11) , + c => pp2_1_sum(11) , + d => tidn , + ki => pp3_0_ko(11) , + ko => pp3_0_ko(10) , + sum => pp3_0_sum(11) , + car => pp3_0_car(10) ); + pp3_0_csa_10: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp2_0_sum(10) , + b => pp2_0_car(10) , + c => pp2_1_sum(10) , + d => tidn , + ki => pp3_0_ko(10) , + ko => pp3_0_ko(9) , + sum => pp3_0_sum(10) , + car => pp3_0_car(9) ); + pp3_0_csa_9: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp2_0_sum(9) , + b => pp2_0_car(9) , + c => pp2_1_sum(9) , + d => tidn , + ki => pp3_0_ko(9) , + ko => pp3_0_ko(8) , + sum => pp3_0_sum(9) , + car => pp3_0_car(8) ); + pp3_0_csa_8: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp2_0_sum(8) , + b => pp2_0_car(8) , + c => pp3_0_ko(8) , + sum => pp3_0_sum(8) , + car => pp3_0_car(7) ); + pp3_0_csa_7: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp2_0_sum(7) , + b => pp2_0_car(7) , + sum => pp3_0_sum(7) , + car => pp3_0_car(6) ); + pp3_0_csa_6: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp2_0_sum(6) , + b => pp2_0_car(6) , + sum => pp3_0_sum(6) , + car => pp3_0_car(5) ); + pp3_0_csa_5: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp2_0_sum(5) , + b => pp2_0_car(5) , + sum => pp3_0_sum(5) , + car => pp3_0_car(4) ); + pp3_0_csa_4: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp2_0_sum(4) , + b => pp2_0_car(4) , + sum => pp3_0_sum(4) , + car => pp3_0_car(3) ); + pp3_0_csa_3: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp2_0_sum(3) , + b => pp2_0_car(3) , + sum => pp3_0_sum(3) , + car => pp3_0_car(2) ); + pp3_0_csa_2: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp2_0_sum(2) , + b => pp2_0_car(2) , + sum => pp3_0_sum(2) , + car => pp3_0_car(1) ); + pp3_0_csa_1: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp2_0_sum(1) , + b => pp2_0_car(1) , + sum => pp3_0_sum(1) , + car => pp3_0_car(0) ); + pp3_0_csa_0: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp2_0_sum(0) , + b => pp2_0_car(0) , + sum => pp3_0_sum(0) , + car => pp3_0_car_unused ); + + + + + tbl_sum(0 to 36) <= pp3_0_sum(0 to 36); + tbl_car(0 to 35) <= pp3_0_car(0 to 35); + + + + + + +end; + + + + + + + + + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_tblmul_bthdcd.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_tblmul_bthdcd.vhdl new file mode 100644 index 0000000..28d74cc --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_tblmul_bthdcd.vhdl @@ -0,0 +1,104 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; +use ieee.std_logic_1164.all; +library ibm; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_ao_support.all; + + +ENTITY fuq_tblmul_bthdcd IS + PORT( + i0 :in std_ulogic; + i1 :in std_ulogic; + i2 :in std_ulogic; + s_neg :out std_ulogic; + s_x :out std_ulogic; + s_x2 :out std_ulogic + ); + + + + +END fuq_tblmul_bthdcd; + +ARCHITECTURE fuq_tblmul_bthdcd OF fuq_tblmul_bthdcd IS + + signal s_add :std_ulogic; + signal sx1_a0_b :std_ulogic; + signal sx1_a1_b :std_ulogic; + signal sx1_t :std_ulogic; + signal sx1_i :std_ulogic; + signal sx2_a0_b :std_ulogic; + signal sx2_a1_b :std_ulogic; + signal sx2_t :std_ulogic; + signal sx2_i :std_ulogic; + signal i0_b, i1_b, i2_b :std_ulogic; + + + + + + + + +BEGIN + + + + +u_0i: i0_b <= not( i0 ); +u_1i: i1_b <= not( i1 ); +u_2i: i2_b <= not( i2 ); + + +u_add: s_add <= not( i0 ); +u_sub: s_neg <= not( s_add ); + +u_sx1_a0: sx1_a0_b <= not( i1_b and i2 ) ; +u_sx1_a1: sx1_a1_b <= not( i1 and i2_b ) ; +u_sx1_t: sx1_t <= not( sx1_a0_b and sx1_a1_b ) ; +u_sx1_i: sx1_i <= not( sx1_t ); +u_sx1_ii: s_x <= not( sx1_i ); + +u_sx2_a0: sx2_a0_b <= not( i0 and i1_b and i2_b ) ; +u_sx2_a1: sx2_a1_b <= not( i0_b and i1 and i2 ) ; +u_sx2_t: sx2_t <= not( sx2_a0_b and sx2_a1_b ) ; +u_sx2_i: sx2_i <= not( sx2_t ); +u_sx2_ii: s_x2 <= not( sx2_i ); + + +END; + + + + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_tblmul_bthrow.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_tblmul_bthrow.vhdl new file mode 100644 index 0000000..1f657ce --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_tblmul_bthrow.vhdl @@ -0,0 +1,233 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; + use ieee.std_logic_1164.all ; +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + +ENTITY fuq_tblmul_bthrow IS +PORT( + + x :in std_ulogic_vector(0 to 15); + s_neg :in std_ulogic; + s_x :in std_ulogic; + s_x2 :in std_ulogic; + q :out std_ulogic_vector(0 to 16) + +); + + +end fuq_tblmul_bthrow; + +architecture fuq_tblmul_bthrow of fuq_tblmul_bthrow is + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal left :std_ulogic_vector( 0 to 16); + signal unused :std_ulogic; +begin + + + unused <= left(0); + + u00: entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => tidn , + LEFT => left(0) , + RIGHT => left(1) , + Q => q(0) ); + + u01: entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(0) , + LEFT => left(1) , + RIGHT => left(2) , + Q => q(1) ); + + u02: entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(1) , + LEFT => left(2) , + RIGHT => left(3) , + Q => q(2) ); + + u03: entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(2) , + LEFT => left(3) , + RIGHT => left(4) , + Q => q(3) ); + + u04: entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(3) , + LEFT => left(4) , + RIGHT => left(5) , + Q => q(4) ); + + u05: entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(4) , + LEFT => left(5) , + RIGHT => left(6) , + Q => q(5) ); + + u06: entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(5) , + LEFT => left(6) , + RIGHT => left(7) , + Q => q(6) ); + + u07: entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(6) , + LEFT => left(7) , + RIGHT => left(8) , + Q => q(7) ); + + u08: entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(7) , + LEFT => left(8) , + RIGHT => left(9) , + Q => q(8) ); + + u09: entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(8) , + LEFT => left(9) , + RIGHT => left(10) , + Q => q(9) ); + + u10: entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(9) , + LEFT => left(10) , + RIGHT => left(11) , + Q => q(10) ); + + u11: entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(10) , + LEFT => left(11) , + RIGHT => left(12) , + Q => q(11) ); + + u12: entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(11) , + LEFT => left(12) , + RIGHT => left(13) , + Q => q(12) ); + + u13: entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(12) , + LEFT => left(13) , + RIGHT => left(14) , + Q => q(13) ); + + u14: entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(13) , + LEFT => left(14) , + RIGHT => left(15) , + Q => q(14) ); + + u15: entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(14) , + LEFT => left(15) , + RIGHT => left(16) , + Q => q(15) ); + + u16: entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , + SX => s_x , + SX2 => s_x2 , + X => x(15) , + LEFT => left(16) , + RIGHT => s_neg , + Q => q(16) ); + + + + + + +end; + + + + + + + + + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_tblres.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_tblres.vhdl new file mode 100644 index 0000000..6efa373 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_tblres.vhdl @@ -0,0 +1,1160 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; + use ieee.std_logic_1164.all ; +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + + + +entity fuq_tblres is +generic( expand_type : integer := 2 ); +port( + f :in std_ulogic_vector(1 to 6); + est :out std_ulogic_vector(1 to 20); + rng :out std_ulogic_vector(6 to 20) + +); + + + +end fuq_tblres; + + +architecture fuq_tblres of fuq_tblres is + + constant tiup :std_ulogic := '1'; + constant tidn :std_ulogic := '0'; + + + signal dcd_00x :std_ulogic; + signal dcd_01x :std_ulogic; + signal dcd_10x :std_ulogic; + signal dcd_11x :std_ulogic; + signal dcd_000 :std_ulogic; + signal dcd_001 :std_ulogic; + signal dcd_010 :std_ulogic; + signal dcd_011 :std_ulogic; + signal dcd_100 :std_ulogic; + signal dcd_101 :std_ulogic; + signal dcd_110 :std_ulogic; + signal dcd_111 :std_ulogic; + signal combo2_1000 :std_ulogic; + signal combo2_0100 :std_ulogic; + signal combo2_1100 :std_ulogic; + signal combo2_0010 :std_ulogic; + signal combo2_1010 :std_ulogic; + signal combo2_0110 :std_ulogic; + signal combo2_1110 :std_ulogic; + signal combo2_0001 :std_ulogic; + signal combo2_1001 :std_ulogic; + signal combo2_0101 :std_ulogic; + signal combo2_1101 :std_ulogic; + signal combo2_0011 :std_ulogic; + signal combo2_1011 :std_ulogic; + signal combo2_0111 :std_ulogic; + signal combo2_1000_xxxx_b :std_ulogic; + signal combo2_0100_xxxx_b :std_ulogic; + signal combo2_1100_xxxx_b :std_ulogic; + signal combo2_0010_xxxx_b :std_ulogic; + signal combo2_1010_xxxx_b :std_ulogic; + signal combo2_0110_xxxx_b :std_ulogic; + signal combo2_1110_xxxx_b :std_ulogic; + signal combo2_0001_xxxx_b :std_ulogic; + signal combo2_1001_xxxx_b :std_ulogic; + signal combo2_0101_xxxx_b :std_ulogic; + signal combo2_1101_xxxx_b :std_ulogic; + signal combo2_0011_xxxx_b :std_ulogic; + signal combo2_1011_xxxx_b :std_ulogic; + signal combo2_0111_xxxx_b :std_ulogic; + signal combo2_xxxx_1000_b :std_ulogic; + signal combo2_xxxx_0100_b :std_ulogic; + signal combo2_xxxx_1100_b :std_ulogic; + signal combo2_xxxx_0010_b :std_ulogic; + signal combo2_xxxx_1010_b :std_ulogic; + signal combo2_xxxx_0110_b :std_ulogic; + signal combo2_xxxx_1110_b :std_ulogic; + signal combo2_xxxx_0001_b :std_ulogic; + signal combo2_xxxx_1001_b :std_ulogic; + signal combo2_xxxx_0101_b :std_ulogic; + signal combo2_xxxx_1101_b :std_ulogic; + signal combo2_xxxx_0011_b :std_ulogic; + signal combo2_xxxx_1011_b :std_ulogic; + signal combo2_xxxx_0111_b :std_ulogic; + signal combo3_0000_0001 :std_ulogic; + signal combo3_0000_0010 :std_ulogic; + signal combo3_0000_0011 :std_ulogic; + signal combo3_0000_0100 :std_ulogic; + signal combo3_0000_0101 :std_ulogic; + signal combo3_0000_0110 :std_ulogic; + signal combo3_0000_1001 :std_ulogic; + signal combo3_0000_1010 :std_ulogic; + signal combo3_0000_1011 :std_ulogic; + signal combo3_0000_1110 :std_ulogic; + signal combo3_0000_1111 :std_ulogic; + signal combo3_0001_0001 :std_ulogic; + signal combo3_0001_0010 :std_ulogic; + signal combo3_0001_0100 :std_ulogic; + signal combo3_0001_0101 :std_ulogic; + signal combo3_0001_0111 :std_ulogic; + signal combo3_0001_1000 :std_ulogic; + signal combo3_0001_1010 :std_ulogic; + signal combo3_0001_1011 :std_ulogic; + signal combo3_0001_1100 :std_ulogic; + signal combo3_0001_1110 :std_ulogic; + signal combo3_0001_1111 :std_ulogic; + signal combo3_0010_0000 :std_ulogic; + signal combo3_0010_0100 :std_ulogic; + signal combo3_0010_0101 :std_ulogic; + signal combo3_0010_0110 :std_ulogic; + signal combo3_0010_0111 :std_ulogic; + signal combo3_0010_1000 :std_ulogic; + signal combo3_0010_1001 :std_ulogic; + signal combo3_0010_1101 :std_ulogic; + signal combo3_0011_0000 :std_ulogic; + signal combo3_0011_0001 :std_ulogic; + signal combo3_0011_0011 :std_ulogic; + signal combo3_0011_0101 :std_ulogic; + signal combo3_0011_1000 :std_ulogic; + signal combo3_0011_1001 :std_ulogic; + signal combo3_0011_1010 :std_ulogic; + signal combo3_0011_1011 :std_ulogic; + signal combo3_0011_1100 :std_ulogic; + signal combo3_0011_1110 :std_ulogic; + signal combo3_0011_1111 :std_ulogic; + signal combo3_0100_0000 :std_ulogic; + signal combo3_0100_0011 :std_ulogic; + signal combo3_0100_0110 :std_ulogic; + signal combo3_0100_1000 :std_ulogic; + signal combo3_0100_1001 :std_ulogic; + signal combo3_0100_1010 :std_ulogic; + signal combo3_0100_1100 :std_ulogic; + signal combo3_0100_1101 :std_ulogic; + signal combo3_0100_1110 :std_ulogic; + signal combo3_0101_0000 :std_ulogic; + signal combo3_0101_0001 :std_ulogic; + signal combo3_0101_0010 :std_ulogic; + signal combo3_0101_0100 :std_ulogic; + signal combo3_0101_0101 :std_ulogic; + signal combo3_0101_0110 :std_ulogic; + signal combo3_0101_1000 :std_ulogic; + signal combo3_0101_1011 :std_ulogic; + signal combo3_0101_1111 :std_ulogic; + signal combo3_0110_0000 :std_ulogic; + signal combo3_0110_0010 :std_ulogic; + signal combo3_0110_0011 :std_ulogic; + signal combo3_0110_0110 :std_ulogic; + signal combo3_0110_0111 :std_ulogic; + signal combo3_0110_1000 :std_ulogic; + signal combo3_0110_1010 :std_ulogic; + signal combo3_0110_1011 :std_ulogic; + signal combo3_0110_1100 :std_ulogic; + signal combo3_0110_1101 :std_ulogic; + signal combo3_0111_0000 :std_ulogic; + signal combo3_0111_0001 :std_ulogic; + signal combo3_0111_0101 :std_ulogic; + signal combo3_0111_0110 :std_ulogic; + signal combo3_0111_1000 :std_ulogic; + signal combo3_0111_1001 :std_ulogic; + signal combo3_0111_1010 :std_ulogic; + signal combo3_0111_1011 :std_ulogic; + signal combo3_0111_1101 :std_ulogic; + signal combo3_0111_1111 :std_ulogic; + signal combo3_1000_0000 :std_ulogic; + signal combo3_1000_0001 :std_ulogic; + signal combo3_1000_0011 :std_ulogic; + signal combo3_1000_0100 :std_ulogic; + signal combo3_1000_0101 :std_ulogic; + signal combo3_1000_1010 :std_ulogic; + signal combo3_1000_1100 :std_ulogic; + signal combo3_1000_1101 :std_ulogic; + signal combo3_1001_0100 :std_ulogic; + signal combo3_1001_0110 :std_ulogic; + signal combo3_1001_0111 :std_ulogic; + signal combo3_1001_1000 :std_ulogic; + signal combo3_1001_1001 :std_ulogic; + signal combo3_1001_1010 :std_ulogic; + signal combo3_1001_1011 :std_ulogic; + signal combo3_1001_1111 :std_ulogic; + signal combo3_1010_0100 :std_ulogic; + signal combo3_1010_0110 :std_ulogic; + signal combo3_1010_1000 :std_ulogic; + signal combo3_1010_1001 :std_ulogic; + signal combo3_1010_1010 :std_ulogic; + signal combo3_1010_1011 :std_ulogic; + signal combo3_1010_1100 :std_ulogic; + signal combo3_1010_1101 :std_ulogic; + signal combo3_1011_0010 :std_ulogic; + signal combo3_1011_0011 :std_ulogic; + signal combo3_1011_0100 :std_ulogic; + signal combo3_1011_0101 :std_ulogic; + signal combo3_1011_0110 :std_ulogic; + signal combo3_1011_0111 :std_ulogic; + signal combo3_1100_0000 :std_ulogic; + signal combo3_1100_0001 :std_ulogic; + signal combo3_1100_0010 :std_ulogic; + signal combo3_1100_0011 :std_ulogic; + signal combo3_1100_0100 :std_ulogic; + signal combo3_1100_0111 :std_ulogic; + signal combo3_1100_1000 :std_ulogic; + signal combo3_1100_1001 :std_ulogic; + signal combo3_1100_1010 :std_ulogic; + signal combo3_1100_1101 :std_ulogic; + signal combo3_1100_1110 :std_ulogic; + signal combo3_1100_1111 :std_ulogic; + signal combo3_1101_0010 :std_ulogic; + signal combo3_1101_0011 :std_ulogic; + signal combo3_1101_0100 :std_ulogic; + signal combo3_1101_0101 :std_ulogic; + signal combo3_1101_0110 :std_ulogic; + signal combo3_1101_0111 :std_ulogic; + signal combo3_1101_1100 :std_ulogic; + signal combo3_1101_1101 :std_ulogic; + signal combo3_1101_1110 :std_ulogic; + signal combo3_1110_0000 :std_ulogic; + signal combo3_1110_0100 :std_ulogic; + signal combo3_1110_0101 :std_ulogic; + signal combo3_1110_0110 :std_ulogic; + signal combo3_1110_1000 :std_ulogic; + signal combo3_1110_1010 :std_ulogic; + signal combo3_1110_1101 :std_ulogic; + signal combo3_1111_0000 :std_ulogic; + signal combo3_1111_0001 :std_ulogic; + signal combo3_1111_0010 :std_ulogic; + signal combo3_1111_0100 :std_ulogic; + signal combo3_1111_1000 :std_ulogic; + signal combo3_1111_1001 :std_ulogic; + signal combo3_1111_1010 :std_ulogic; + signal combo3_1111_1100 :std_ulogic; + signal combo3_1111_1110 :std_ulogic; + signal e_00_b :std_ulogic_vector(0 to 7); + signal e_01_b :std_ulogic_vector(0 to 7); + signal e_02_b :std_ulogic_vector(0 to 7); + signal e_03_b :std_ulogic_vector(0 to 7); + signal e_04_b :std_ulogic_vector(0 to 7); + signal e_05_b :std_ulogic_vector(0 to 7); + signal e_06_b :std_ulogic_vector(0 to 7); + signal e_07_b :std_ulogic_vector(0 to 7); + signal e_08_b :std_ulogic_vector(0 to 7); + signal e_09_b :std_ulogic_vector(0 to 7); + signal e_10_b :std_ulogic_vector(0 to 7); + signal e_11_b :std_ulogic_vector(0 to 7); + signal e_12_b :std_ulogic_vector(0 to 7); + signal e_13_b :std_ulogic_vector(0 to 7); + signal e_14_b :std_ulogic_vector(0 to 7); + signal e_15_b :std_ulogic_vector(0 to 7); + signal e_16_b :std_ulogic_vector(0 to 7); + signal e_17_b :std_ulogic_vector(0 to 7); + signal e_18_b :std_ulogic_vector(0 to 7); + signal e_19_b :std_ulogic_vector(0 to 7); + signal e :std_ulogic_vector(0 to 19); + signal r_00_b :std_ulogic_vector(0 to 7); + signal r_01_b :std_ulogic_vector(0 to 7); + signal r_02_b :std_ulogic_vector(0 to 7); + signal r_03_b :std_ulogic_vector(0 to 7); + signal r_04_b :std_ulogic_vector(0 to 7); + signal r_05_b :std_ulogic_vector(0 to 7); + signal r_06_b :std_ulogic_vector(0 to 7); + signal r_07_b :std_ulogic_vector(0 to 7); + signal r_08_b :std_ulogic_vector(0 to 7); + signal r_09_b :std_ulogic_vector(0 to 7); + signal r_10_b :std_ulogic_vector(0 to 7); + signal r_11_b :std_ulogic_vector(0 to 7); + signal r_12_b :std_ulogic_vector(0 to 7); + signal r_13_b :std_ulogic_vector(0 to 7); + signal r_14_b :std_ulogic_vector(0 to 7); + signal r :std_ulogic_vector(0 to 14); + + +begin + + + + dcd_00x <= not f(1) and not f(2) ; + dcd_01x <= not f(1) and f(2) ; + dcd_10x <= f(1) and not f(2) ; + dcd_11x <= f(1) and f(2) ; + + dcd_000 <= not f(3) and dcd_00x ; + dcd_001 <= f(3) and dcd_00x ; + dcd_010 <= not f(3) and dcd_01x ; + dcd_011 <= f(3) and dcd_01x ; + dcd_100 <= not f(3) and dcd_10x ; + dcd_101 <= f(3) and dcd_10x ; + dcd_110 <= not f(3) and dcd_11x ; + dcd_111 <= f(3) and dcd_11x ; + + + + combo2_1000 <= not f(5) and not f(6) ; + combo2_0100 <= not f(5) and f(6) ; + combo2_1100 <= not f(5) ; + combo2_0010 <= f(5) and not f(6) ; + combo2_1010 <= not f(6) ; + combo2_0110 <= f(5) xor f(6) ; + combo2_1110 <= not( f(5) and f(6) ) ; + combo2_0001 <= f(5) and f(6) ; + combo2_1001 <= not( f(5) xor f(6) ) ; + combo2_0101 <= f(6) ; + combo2_1101 <= not( f(5) and not f(6) ) ; + combo2_0011 <= f(5) ; + combo2_1011 <= not( not f(5) and f(6) ) ; + combo2_0111 <= not( not f(5) and not f(6) ) ; + + + + combo2_1000_xxxx_b <= not( not f(4) and combo2_1000 ); + combo2_0100_xxxx_b <= not( not f(4) and combo2_0100 ); + combo2_1100_xxxx_b <= not( not f(4) and combo2_1100 ); + combo2_0010_xxxx_b <= not( not f(4) and combo2_0010 ); + combo2_1010_xxxx_b <= not( not f(4) and combo2_1010 ); + combo2_0110_xxxx_b <= not( not f(4) and combo2_0110 ); + combo2_1110_xxxx_b <= not( not f(4) and combo2_1110 ); + combo2_0001_xxxx_b <= not( not f(4) and combo2_0001 ); + combo2_1001_xxxx_b <= not( not f(4) and combo2_1001 ); + combo2_0101_xxxx_b <= not( not f(4) and combo2_0101 ); + combo2_1101_xxxx_b <= not( not f(4) and combo2_1101 ); + combo2_0011_xxxx_b <= not( not f(4) and combo2_0011 ); + combo2_1011_xxxx_b <= not( not f(4) and combo2_1011 ); + combo2_0111_xxxx_b <= not( not f(4) and combo2_0111 ); + + + combo2_xxxx_1000_b <= not( f(4) and combo2_1000 ); + combo2_xxxx_0100_b <= not( f(4) and combo2_0100 ); + combo2_xxxx_1100_b <= not( f(4) and combo2_1100 ); + combo2_xxxx_0010_b <= not( f(4) and combo2_0010 ); + combo2_xxxx_1010_b <= not( f(4) and combo2_1010 ); + combo2_xxxx_0110_b <= not( f(4) and combo2_0110 ); + combo2_xxxx_1110_b <= not( f(4) and combo2_1110 ); + combo2_xxxx_0001_b <= not( f(4) and combo2_0001 ); + combo2_xxxx_1001_b <= not( f(4) and combo2_1001 ); + combo2_xxxx_0101_b <= not( f(4) and combo2_0101 ); + combo2_xxxx_1101_b <= not( f(4) and combo2_1101 ); + combo2_xxxx_0011_b <= not( f(4) and combo2_0011 ); + combo2_xxxx_1011_b <= not( f(4) and combo2_1011 ); + combo2_xxxx_0111_b <= not( f(4) and combo2_0111 ); + + + combo3_0000_0001 <= not( combo2_xxxx_0001_b ); + combo3_0000_0010 <= not( combo2_xxxx_0010_b ); + combo3_0000_0011 <= not( combo2_xxxx_0011_b ); + combo3_0000_0100 <= not( combo2_xxxx_0100_b ); + combo3_0000_0101 <= not( combo2_xxxx_0101_b ); + combo3_0000_0110 <= not( combo2_xxxx_0110_b ); + combo3_0000_1001 <= not( combo2_xxxx_1001_b ); + combo3_0000_1010 <= not( combo2_xxxx_1010_b ); + combo3_0000_1011 <= not( combo2_xxxx_1011_b ); + combo3_0000_1110 <= not( combo2_xxxx_1110_b ); + combo3_0000_1111 <= not( not f(4) ); + combo3_0001_0001 <= not( not combo2_0001 ); + combo3_0001_0010 <= not( combo2_0001_xxxx_b and combo2_xxxx_0010_b ); + combo3_0001_0100 <= not( combo2_0001_xxxx_b and combo2_xxxx_0100_b ); + combo3_0001_0101 <= not( combo2_0001_xxxx_b and combo2_xxxx_0101_b ); + combo3_0001_0111 <= not( combo2_0001_xxxx_b and combo2_xxxx_0111_b ); + combo3_0001_1000 <= not( combo2_0001_xxxx_b and combo2_xxxx_1000_b ); + combo3_0001_1010 <= not( combo2_0001_xxxx_b and combo2_xxxx_1010_b ); + combo3_0001_1011 <= not( combo2_0001_xxxx_b and combo2_xxxx_1011_b ); + combo3_0001_1100 <= not( combo2_0001_xxxx_b and combo2_xxxx_1100_b ); + combo3_0001_1110 <= not( combo2_0001_xxxx_b and combo2_xxxx_1110_b ); + combo3_0001_1111 <= not( combo2_0001_xxxx_b and not f(4) ); + combo3_0010_0000 <= not( combo2_0010_xxxx_b ); + combo3_0010_0100 <= not( combo2_0010_xxxx_b and combo2_xxxx_0100_b ); + combo3_0010_0101 <= not( combo2_0010_xxxx_b and combo2_xxxx_0101_b ); + combo3_0010_0110 <= not( combo2_0010_xxxx_b and combo2_xxxx_0110_b ); + combo3_0010_0111 <= not( combo2_0010_xxxx_b and combo2_xxxx_0111_b ); + combo3_0010_1000 <= not( combo2_0010_xxxx_b and combo2_xxxx_1000_b ); + combo3_0010_1001 <= not( combo2_0010_xxxx_b and combo2_xxxx_1001_b ); + combo3_0010_1101 <= not( combo2_0010_xxxx_b and combo2_xxxx_1101_b ); + combo3_0011_0000 <= not( combo2_0011_xxxx_b ); + combo3_0011_0001 <= not( combo2_0011_xxxx_b and combo2_xxxx_0001_b ); + combo3_0011_0011 <= not( not combo2_0011 ); + combo3_0011_0101 <= not( combo2_0011_xxxx_b and combo2_xxxx_0101_b ); + combo3_0011_1000 <= not( combo2_0011_xxxx_b and combo2_xxxx_1000_b ); + combo3_0011_1001 <= not( combo2_0011_xxxx_b and combo2_xxxx_1001_b ); + combo3_0011_1010 <= not( combo2_0011_xxxx_b and combo2_xxxx_1010_b ); + combo3_0011_1011 <= not( combo2_0011_xxxx_b and combo2_xxxx_1011_b ); + combo3_0011_1100 <= not( combo2_0011_xxxx_b and combo2_xxxx_1100_b ); + combo3_0011_1110 <= not( combo2_0011_xxxx_b and combo2_xxxx_1110_b ); + combo3_0011_1111 <= not( combo2_0011_xxxx_b and not f(4) ); + combo3_0100_0000 <= not( combo2_0100_xxxx_b ); + combo3_0100_0011 <= not( combo2_0100_xxxx_b and combo2_xxxx_0011_b ); + combo3_0100_0110 <= not( combo2_0100_xxxx_b and combo2_xxxx_0110_b ); + combo3_0100_1000 <= not( combo2_0100_xxxx_b and combo2_xxxx_1000_b ); + combo3_0100_1001 <= not( combo2_0100_xxxx_b and combo2_xxxx_1001_b ); + combo3_0100_1010 <= not( combo2_0100_xxxx_b and combo2_xxxx_1010_b ); + combo3_0100_1100 <= not( combo2_0100_xxxx_b and combo2_xxxx_1100_b ); + combo3_0100_1101 <= not( combo2_0100_xxxx_b and combo2_xxxx_1101_b ); + combo3_0100_1110 <= not( combo2_0100_xxxx_b and combo2_xxxx_1110_b ); + combo3_0101_0000 <= not( combo2_0101_xxxx_b ); + combo3_0101_0001 <= not( combo2_0101_xxxx_b and combo2_xxxx_0001_b ); + combo3_0101_0010 <= not( combo2_0101_xxxx_b and combo2_xxxx_0010_b ); + combo3_0101_0100 <= not( combo2_0101_xxxx_b and combo2_xxxx_0100_b ); + combo3_0101_0101 <= not( not combo2_0101 ); + combo3_0101_0110 <= not( combo2_0101_xxxx_b and combo2_xxxx_0110_b ); + combo3_0101_1000 <= not( combo2_0101_xxxx_b and combo2_xxxx_1000_b ); + combo3_0101_1011 <= not( combo2_0101_xxxx_b and combo2_xxxx_1011_b ); + combo3_0101_1111 <= not( combo2_0101_xxxx_b and not f(4) ); + combo3_0110_0000 <= not( combo2_0110_xxxx_b ); + combo3_0110_0010 <= not( combo2_0110_xxxx_b and combo2_xxxx_0010_b ); + combo3_0110_0011 <= not( combo2_0110_xxxx_b and combo2_xxxx_0011_b ); + combo3_0110_0110 <= not( not combo2_0110 ); + combo3_0110_0111 <= not( combo2_0110_xxxx_b and combo2_xxxx_0111_b ); + combo3_0110_1000 <= not( combo2_0110_xxxx_b and combo2_xxxx_1000_b ); + combo3_0110_1010 <= not( combo2_0110_xxxx_b and combo2_xxxx_1010_b ); + combo3_0110_1011 <= not( combo2_0110_xxxx_b and combo2_xxxx_1011_b ); + combo3_0110_1100 <= not( combo2_0110_xxxx_b and combo2_xxxx_1100_b ); + combo3_0110_1101 <= not( combo2_0110_xxxx_b and combo2_xxxx_1101_b ); + combo3_0111_0000 <= not( combo2_0111_xxxx_b ); + combo3_0111_0001 <= not( combo2_0111_xxxx_b and combo2_xxxx_0001_b ); + combo3_0111_0101 <= not( combo2_0111_xxxx_b and combo2_xxxx_0101_b ); + combo3_0111_0110 <= not( combo2_0111_xxxx_b and combo2_xxxx_0110_b ); + combo3_0111_1000 <= not( combo2_0111_xxxx_b and combo2_xxxx_1000_b ); + combo3_0111_1001 <= not( combo2_0111_xxxx_b and combo2_xxxx_1001_b ); + combo3_0111_1010 <= not( combo2_0111_xxxx_b and combo2_xxxx_1010_b ); + combo3_0111_1011 <= not( combo2_0111_xxxx_b and combo2_xxxx_1011_b ); + combo3_0111_1101 <= not( combo2_0111_xxxx_b and combo2_xxxx_1101_b ); + combo3_0111_1111 <= not( combo2_0111_xxxx_b and not f(4) ); + combo3_1000_0000 <= not( combo2_1000_xxxx_b ); + combo3_1000_0001 <= not( combo2_1000_xxxx_b and combo2_xxxx_0001_b ); + combo3_1000_0011 <= not( combo2_1000_xxxx_b and combo2_xxxx_0011_b ); + combo3_1000_0100 <= not( combo2_1000_xxxx_b and combo2_xxxx_0100_b ); + combo3_1000_0101 <= not( combo2_1000_xxxx_b and combo2_xxxx_0101_b ); + combo3_1000_1010 <= not( combo2_1000_xxxx_b and combo2_xxxx_1010_b ); + combo3_1000_1100 <= not( combo2_1000_xxxx_b and combo2_xxxx_1100_b ); + combo3_1000_1101 <= not( combo2_1000_xxxx_b and combo2_xxxx_1101_b ); + combo3_1001_0100 <= not( combo2_1001_xxxx_b and combo2_xxxx_0100_b ); + combo3_1001_0110 <= not( combo2_1001_xxxx_b and combo2_xxxx_0110_b ); + combo3_1001_0111 <= not( combo2_1001_xxxx_b and combo2_xxxx_0111_b ); + combo3_1001_1000 <= not( combo2_1001_xxxx_b and combo2_xxxx_1000_b ); + combo3_1001_1001 <= not( not combo2_1001 ); + combo3_1001_1010 <= not( combo2_1001_xxxx_b and combo2_xxxx_1010_b ); + combo3_1001_1011 <= not( combo2_1001_xxxx_b and combo2_xxxx_1011_b ); + combo3_1001_1111 <= not( combo2_1001_xxxx_b and not f(4) ); + combo3_1010_0100 <= not( combo2_1010_xxxx_b and combo2_xxxx_0100_b ); + combo3_1010_0110 <= not( combo2_1010_xxxx_b and combo2_xxxx_0110_b ); + combo3_1010_1000 <= not( combo2_1010_xxxx_b and combo2_xxxx_1000_b ); + combo3_1010_1001 <= not( combo2_1010_xxxx_b and combo2_xxxx_1001_b ); + combo3_1010_1010 <= not( not combo2_1010 ); + combo3_1010_1011 <= not( combo2_1010_xxxx_b and combo2_xxxx_1011_b ); + combo3_1010_1100 <= not( combo2_1010_xxxx_b and combo2_xxxx_1100_b ); + combo3_1010_1101 <= not( combo2_1010_xxxx_b and combo2_xxxx_1101_b ); + combo3_1011_0010 <= not( combo2_1011_xxxx_b and combo2_xxxx_0010_b ); + combo3_1011_0011 <= not( combo2_1011_xxxx_b and combo2_xxxx_0011_b ); + combo3_1011_0100 <= not( combo2_1011_xxxx_b and combo2_xxxx_0100_b ); + combo3_1011_0101 <= not( combo2_1011_xxxx_b and combo2_xxxx_0101_b ); + combo3_1011_0110 <= not( combo2_1011_xxxx_b and combo2_xxxx_0110_b ); + combo3_1011_0111 <= not( combo2_1011_xxxx_b and combo2_xxxx_0111_b ); + combo3_1100_0000 <= not( combo2_1100_xxxx_b ); + combo3_1100_0001 <= not( combo2_1100_xxxx_b and combo2_xxxx_0001_b ); + combo3_1100_0010 <= not( combo2_1100_xxxx_b and combo2_xxxx_0010_b ); + combo3_1100_0011 <= not( combo2_1100_xxxx_b and combo2_xxxx_0011_b ); + combo3_1100_0100 <= not( combo2_1100_xxxx_b and combo2_xxxx_0100_b ); + combo3_1100_0111 <= not( combo2_1100_xxxx_b and combo2_xxxx_0111_b ); + combo3_1100_1000 <= not( combo2_1100_xxxx_b and combo2_xxxx_1000_b ); + combo3_1100_1001 <= not( combo2_1100_xxxx_b and combo2_xxxx_1001_b ); + combo3_1100_1010 <= not( combo2_1100_xxxx_b and combo2_xxxx_1010_b ); + combo3_1100_1101 <= not( combo2_1100_xxxx_b and combo2_xxxx_1101_b ); + combo3_1100_1110 <= not( combo2_1100_xxxx_b and combo2_xxxx_1110_b ); + combo3_1100_1111 <= not( combo2_1100_xxxx_b and not f(4) ); + combo3_1101_0010 <= not( combo2_1101_xxxx_b and combo2_xxxx_0010_b ); + combo3_1101_0011 <= not( combo2_1101_xxxx_b and combo2_xxxx_0011_b ); + combo3_1101_0100 <= not( combo2_1101_xxxx_b and combo2_xxxx_0100_b ); + combo3_1101_0101 <= not( combo2_1101_xxxx_b and combo2_xxxx_0101_b ); + combo3_1101_0110 <= not( combo2_1101_xxxx_b and combo2_xxxx_0110_b ); + combo3_1101_0111 <= not( combo2_1101_xxxx_b and combo2_xxxx_0111_b ); + combo3_1101_1100 <= not( combo2_1101_xxxx_b and combo2_xxxx_1100_b ); + combo3_1101_1101 <= not( not combo2_1101 ); + combo3_1101_1110 <= not( combo2_1101_xxxx_b and combo2_xxxx_1110_b ); + combo3_1110_0000 <= not( combo2_1110_xxxx_b ); + combo3_1110_0100 <= not( combo2_1110_xxxx_b and combo2_xxxx_0100_b ); + combo3_1110_0101 <= not( combo2_1110_xxxx_b and combo2_xxxx_0101_b ); + combo3_1110_0110 <= not( combo2_1110_xxxx_b and combo2_xxxx_0110_b ); + combo3_1110_1000 <= not( combo2_1110_xxxx_b and combo2_xxxx_1000_b ); + combo3_1110_1010 <= not( combo2_1110_xxxx_b and combo2_xxxx_1010_b ); + combo3_1110_1101 <= not( combo2_1110_xxxx_b and combo2_xxxx_1101_b ); + combo3_1111_0000 <= not( f(4) ); + combo3_1111_0001 <= not( f(4) and combo2_xxxx_0001_b ); + combo3_1111_0010 <= not( f(4) and combo2_xxxx_0010_b ); + combo3_1111_0100 <= not( f(4) and combo2_xxxx_0100_b ); + combo3_1111_1000 <= not( f(4) and combo2_xxxx_1000_b ); + combo3_1111_1001 <= not( f(4) and combo2_xxxx_1001_b ); + combo3_1111_1010 <= not( f(4) and combo2_xxxx_1010_b ); + combo3_1111_1100 <= not( f(4) and combo2_xxxx_1100_b ); + combo3_1111_1110 <= not( f(4) and combo2_xxxx_1110_b ); + + + + e_00_b(0) <= not( dcd_000 and tiup ); + e_00_b(1) <= not( dcd_001 and tiup ); + e_00_b(2) <= not( dcd_010 and combo3_1111_1100 ); + e_00_b(3) <= not( dcd_011 and tidn ); + e_00_b(4) <= not( dcd_100 and tidn ); + e_00_b(5) <= not( dcd_101 and tidn ); + e_00_b(6) <= not( dcd_110 and tidn ); + e_00_b(7) <= not( dcd_111 and tidn ); + + e( 0) <= not( e_00_b(0) and + e_00_b(1) and + e_00_b(2) and + e_00_b(3) and + e_00_b(4) and + e_00_b(5) and + e_00_b(6) and + e_00_b(7) ); + + e_01_b(0) <= not( dcd_000 and tiup ); + e_01_b(1) <= not( dcd_001 and combo3_1100_0000 ); + e_01_b(2) <= not( dcd_010 and combo3_0000_0011 ); + e_01_b(3) <= not( dcd_011 and tiup ); + e_01_b(4) <= not( dcd_100 and combo3_1111_1110 ); + e_01_b(5) <= not( dcd_101 and tidn ); + e_01_b(6) <= not( dcd_110 and tidn ); + e_01_b(7) <= not( dcd_111 and tidn ); + + e( 1) <= not( e_01_b(0) and + e_01_b(1) and + e_01_b(2) and + e_01_b(3) and + e_01_b(4) and + e_01_b(5) and + e_01_b(6) and + e_01_b(7) ); + + e_02_b(0) <= not( dcd_000 and combo3_1111_1000 ); + e_02_b(1) <= not( dcd_001 and combo3_0011_1110 ); + e_02_b(2) <= not( dcd_010 and combo3_0000_0011 ); + e_02_b(3) <= not( dcd_011 and combo3_1111_1100 ); + e_02_b(4) <= not( dcd_100 and combo3_0000_0001 ); + e_02_b(5) <= not( dcd_101 and tiup ); + e_02_b(6) <= not( dcd_110 and combo3_1100_0000 ); + e_02_b(7) <= not( dcd_111 and tidn ); + + e( 2) <= not( e_02_b(0) and + e_02_b(1) and + e_02_b(2) and + e_02_b(3) and + e_02_b(4) and + e_02_b(5) and + e_02_b(6) and + e_02_b(7) ); + + e_03_b(0) <= not( dcd_000 and combo3_1110_0110 ); + e_03_b(1) <= not( dcd_001 and combo3_0011_0001 ); + e_03_b(2) <= not( dcd_010 and combo3_1100_0011 ); + e_03_b(3) <= not( dcd_011 and combo3_1100_0011 ); + e_03_b(4) <= not( dcd_100 and combo3_1100_0001 ); + e_03_b(5) <= not( dcd_101 and combo3_1111_0000 ); + e_03_b(6) <= not( dcd_110 and combo3_0011_1111 ); + e_03_b(7) <= not( dcd_111 and combo3_1000_0000 ); + + e( 3) <= not( e_03_b(0) and + e_03_b(1) and + e_03_b(2) and + e_03_b(3) and + e_03_b(4) and + e_03_b(5) and + e_03_b(6) and + e_03_b(7) ); + + e_04_b(0) <= not( dcd_000 and combo3_1101_0101 ); + e_04_b(1) <= not( dcd_001 and combo3_0010_1101 ); + e_04_b(2) <= not( dcd_010 and combo3_1011_0011 ); + e_04_b(3) <= not( dcd_011 and combo3_0011_0011 ); + e_04_b(4) <= not( dcd_100 and combo3_0011_0001 ); + e_04_b(5) <= not( dcd_101 and combo3_1100_1110 ); + e_04_b(6) <= not( dcd_110 and combo3_0011_1100 ); + e_04_b(7) <= not( dcd_111 and combo3_0111_1000 ); + + e( 4) <= not( e_04_b(0) and + e_04_b(1) and + e_04_b(2) and + e_04_b(3) and + e_04_b(4) and + e_04_b(5) and + e_04_b(6) and + e_04_b(7) ); + + e_05_b(0) <= not( dcd_000 and combo3_1000_0011 ); + e_05_b(1) <= not( dcd_001 and combo3_1001_1011 ); + e_05_b(2) <= not( dcd_010 and combo3_0110_1010 ); + e_05_b(3) <= not( dcd_011 and combo3_1010_1010 ); + e_05_b(4) <= not( dcd_100 and combo3_1010_1101 ); + e_05_b(5) <= not( dcd_101 and combo3_0010_1101 ); + e_05_b(6) <= not( dcd_110 and combo3_1011_0010 ); + e_05_b(7) <= not( dcd_111 and combo3_0110_0110 ); + + e( 5) <= not( e_05_b(0) and + e_05_b(1) and + e_05_b(2) and + e_05_b(3) and + e_05_b(4) and + e_05_b(5) and + e_05_b(6) and + e_05_b(7) ); + + e_06_b(0) <= not( dcd_000 and combo3_1000_0100 ); + e_06_b(1) <= not( dcd_001 and combo3_1010_1001 ); + e_06_b(2) <= not( dcd_010 and combo3_0011_1000 ); + e_06_b(3) <= not( dcd_011 and tidn ); + e_06_b(4) <= not( dcd_100 and combo3_0011_1001 ); + e_06_b(5) <= not( dcd_101 and combo3_1001_1001 ); + e_06_b(6) <= not( dcd_110 and combo3_0010_1001 ); + e_06_b(7) <= not( dcd_111 and combo3_0101_0101 ); + + e( 6) <= not( e_06_b(0) and + e_06_b(1) and + e_06_b(2) and + e_06_b(3) and + e_06_b(4) and + e_06_b(5) and + e_06_b(6) and + e_06_b(7) ); + + e_07_b(0) <= not( dcd_000 and combo3_1001_1001 ); + e_07_b(1) <= not( dcd_001 and combo3_1000_1100 ); + e_07_b(2) <= not( dcd_010 and combo3_1010_0110 ); + e_07_b(3) <= not( dcd_011 and tidn ); + e_07_b(4) <= not( dcd_100 and combo3_1100_1010 ); + e_07_b(5) <= not( dcd_101 and combo3_1010_1011 ); + e_07_b(6) <= not( dcd_110 and combo3_0110_0011 ); + e_07_b(7) <= not( dcd_111 and combo3_1000_0000 ); + + e( 7) <= not( e_07_b(0) and + e_07_b(1) and + e_07_b(2) and + e_07_b(3) and + e_07_b(4) and + e_07_b(5) and + e_07_b(6) and + e_07_b(7) ); + + e_08_b(0) <= not( dcd_000 and combo3_1000_1101 ); + e_08_b(1) <= not( dcd_001 and combo3_0111_0101 ); + e_08_b(2) <= not( dcd_010 and combo3_1111_0001 ); + e_08_b(3) <= not( dcd_011 and combo3_0000_0011 ); + e_08_b(4) <= not( dcd_100 and combo3_0101_1000 ); + e_08_b(5) <= not( dcd_101 and combo3_0000_0110 ); + e_08_b(6) <= not( dcd_110 and combo3_1101_0010 ); + e_08_b(7) <= not( dcd_111 and combo3_0110_0000 ); + + e( 8) <= not( e_08_b(0) and + e_08_b(1) and + e_08_b(2) and + e_08_b(3) and + e_08_b(4) and + e_08_b(5) and + e_08_b(6) and + e_08_b(7) ); + + e_09_b(0) <= not( dcd_000 and combo3_1010_1100 ); + e_09_b(1) <= not( dcd_001 and combo3_0111_0001 ); + e_09_b(2) <= not( dcd_010 and combo3_0001_0100 ); + e_09_b(3) <= not( dcd_011 and combo3_1000_0101 ); + e_09_b(4) <= not( dcd_100 and combo3_1111_0100 ); + e_09_b(5) <= not( dcd_101 and combo3_0000_1010 ); + e_09_b(6) <= not( dcd_110 and combo3_0111_1001 ); + e_09_b(7) <= not( dcd_111 and combo3_0101_0000 ); + + e( 9) <= not( e_09_b(0) and + e_09_b(1) and + e_09_b(2) and + e_09_b(3) and + e_09_b(4) and + e_09_b(5) and + e_09_b(6) and + e_09_b(7) ); + + e_10_b(0) <= not( dcd_000 and combo3_1010_0100 ); + e_10_b(1) <= not( dcd_001 and combo3_0001_1000 ); + e_10_b(2) <= not( dcd_010 and combo3_0000_0101 ); + e_10_b(3) <= not( dcd_011 and combo3_0100_1001 ); + e_10_b(4) <= not( dcd_100 and combo3_0001_1110 ); + e_10_b(5) <= not( dcd_101 and combo3_0001_1011 ); + e_10_b(6) <= not( dcd_110 and combo3_0111_1010 ); + e_10_b(7) <= not( dcd_111 and combo3_0001_1100 ); + + e(10) <= not( e_10_b(0) and + e_10_b(1) and + e_10_b(2) and + e_10_b(3) and + e_10_b(4) and + e_10_b(5) and + e_10_b(6) and + e_10_b(7) ); + + e_11_b(0) <= not( dcd_000 and combo3_1110_1010 ); + e_11_b(1) <= not( dcd_001 and combo3_1100_0010 ); + e_11_b(2) <= not( dcd_010 and combo3_1010_1100 ); + e_11_b(3) <= not( dcd_011 and combo3_1011_0110 ); + e_11_b(4) <= not( dcd_100 and combo3_1011_0011 ); + e_11_b(5) <= not( dcd_101 and combo3_0011_0101 ); + e_11_b(6) <= not( dcd_110 and combo3_0100_1001 ); + e_11_b(7) <= not( dcd_111 and combo3_0010_1000 ); + + e(11) <= not( e_11_b(0) and + e_11_b(1) and + e_11_b(2) and + e_11_b(3) and + e_11_b(4) and + e_11_b(5) and + e_11_b(6) and + e_11_b(7) ); + + e_12_b(0) <= not( dcd_000 and combo3_1111_1010 ); + e_12_b(1) <= not( dcd_001 and combo3_1110_0100 ); + e_12_b(2) <= not( dcd_010 and combo3_0010_0100 ); + e_12_b(3) <= not( dcd_011 and combo3_1100_1001 ); + e_12_b(4) <= not( dcd_100 and combo3_0111_1111 ); + e_12_b(5) <= not( dcd_101 and combo3_1111_0100 ); + e_12_b(6) <= not( dcd_110 and combo3_1011_0111 ); + e_12_b(7) <= not( dcd_111 and combo3_1100_1010 ); + + e(12) <= not( e_12_b(0) and + e_12_b(1) and + e_12_b(2) and + e_12_b(3) and + e_12_b(4) and + e_12_b(5) and + e_12_b(6) and + e_12_b(7) ); + + e_13_b(0) <= not( dcd_000 and combo3_1001_1000 ); + e_13_b(1) <= not( dcd_001 and combo3_0101_1011 ); + e_13_b(2) <= not( dcd_010 and combo3_1101_1100 ); + e_13_b(3) <= not( dcd_011 and combo3_0000_0110 ); + e_13_b(4) <= not( dcd_100 and combo3_0100_0011 ); + e_13_b(5) <= not( dcd_101 and combo3_1110_1000 ); + e_13_b(6) <= not( dcd_110 and combo3_1111_1110 ); + e_13_b(7) <= not( dcd_111 and combo3_1001_1010 ); + + e(13) <= not( e_13_b(0) and + e_13_b(1) and + e_13_b(2) and + e_13_b(3) and + e_13_b(4) and + e_13_b(5) and + e_13_b(6) and + e_13_b(7) ); + + e_14_b(0) <= not( dcd_000 and combo3_0101_0100 ); + e_14_b(1) <= not( dcd_001 and combo3_0010_0110 ); + e_14_b(2) <= not( dcd_010 and combo3_0101_0000 ); + e_14_b(3) <= not( dcd_011 and combo3_0111_0000 ); + e_14_b(4) <= not( dcd_100 and combo3_0010_1101 ); + e_14_b(5) <= not( dcd_101 and combo3_1101_0100 ); + e_14_b(6) <= not( dcd_110 and combo3_1100_1000 ); + e_14_b(7) <= not( dcd_111 and combo3_0110_1000 ); + + e(14) <= not( e_14_b(0) and + e_14_b(1) and + e_14_b(2) and + e_14_b(3) and + e_14_b(4) and + e_14_b(5) and + e_14_b(6) and + e_14_b(7) ); + + e_15_b(0) <= not( dcd_000 and combo3_0101_1011 ); + e_15_b(1) <= not( dcd_001 and combo3_0010_0000 ); + e_15_b(2) <= not( dcd_010 and combo3_1101_0110 ); + e_15_b(3) <= not( dcd_011 and combo3_1000_0001 ); + e_15_b(4) <= not( dcd_100 and combo3_1001_0110 ); + e_15_b(5) <= not( dcd_101 and combo3_1110_0101 ); + e_15_b(6) <= not( dcd_110 and combo3_0100_1110 ); + e_15_b(7) <= not( dcd_111 and combo3_1110_0000 ); + + e(15) <= not( e_15_b(0) and + e_15_b(1) and + e_15_b(2) and + e_15_b(3) and + e_15_b(4) and + e_15_b(5) and + e_15_b(6) and + e_15_b(7) ); + + e_16_b(0) <= not( dcd_000 and combo3_0100_1000 ); + e_16_b(1) <= not( dcd_001 and combo3_0010_0101 ); + e_16_b(2) <= not( dcd_010 and combo3_1001_0111 ); + e_16_b(3) <= not( dcd_011 and combo3_0011_1010 ); + e_16_b(4) <= not( dcd_100 and combo3_0000_0101 ); + e_16_b(5) <= not( dcd_101 and combo3_1110_0100 ); + e_16_b(6) <= not( dcd_110 and combo3_0000_1111 ); + e_16_b(7) <= not( dcd_111 and combo3_0000_0100 ); + + e(16) <= not( e_16_b(0) and + e_16_b(1) and + e_16_b(2) and + e_16_b(3) and + e_16_b(4) and + e_16_b(5) and + e_16_b(6) and + e_16_b(7) ); + + e_17_b(0) <= not( dcd_000 and combo3_0000_1011 ); + e_17_b(1) <= not( dcd_001 and combo3_1100_1111 ); + e_17_b(2) <= not( dcd_010 and combo3_0000_1011 ); + e_17_b(3) <= not( dcd_011 and combo3_0010_0000 ); + e_17_b(4) <= not( dcd_100 and combo3_1101_0011 ); + e_17_b(5) <= not( dcd_101 and combo3_0010_1000 ); + e_17_b(6) <= not( dcd_110 and combo3_1111_0010 ); + e_17_b(7) <= not( dcd_111 and combo3_0100_0110 ); + + e(17) <= not( e_17_b(0) and + e_17_b(1) and + e_17_b(2) and + e_17_b(3) and + e_17_b(4) and + e_17_b(5) and + e_17_b(6) and + e_17_b(7) ); + + e_18_b(0) <= not( dcd_000 and combo3_0000_1001 ); + e_18_b(1) <= not( dcd_001 and combo3_1100_1101 ); + e_18_b(2) <= not( dcd_010 and combo3_0000_1010 ); + e_18_b(3) <= not( dcd_011 and combo3_0000_0001 ); + e_18_b(4) <= not( dcd_100 and combo3_0101_0000 ); + e_18_b(5) <= not( dcd_101 and combo3_1001_0100 ); + e_18_b(6) <= not( dcd_110 and combo3_0101_0010 ); + e_18_b(7) <= not( dcd_111 and tidn ); + + e(18) <= not( e_18_b(0) and + e_18_b(1) and + e_18_b(2) and + e_18_b(3) and + e_18_b(4) and + e_18_b(5) and + e_18_b(6) and + e_18_b(7) ); + + e_19_b(0) <= not( dcd_000 and combo3_0111_1111 ); + e_19_b(1) <= not( dcd_001 and tiup ); + e_19_b(2) <= not( dcd_010 and tiup ); + e_19_b(3) <= not( dcd_011 and tiup ); + e_19_b(4) <= not( dcd_100 and tiup ); + e_19_b(5) <= not( dcd_101 and tiup ); + e_19_b(6) <= not( dcd_110 and tiup ); + e_19_b(7) <= not( dcd_111 and tiup ); + + e(19) <= not( e_19_b(0) and + e_19_b(1) and + e_19_b(2) and + e_19_b(3) and + e_19_b(4) and + e_19_b(5) and + e_19_b(6) and + e_19_b(7) ); + + + + + r_00_b(0) <= not( dcd_000 and tiup ); + r_00_b(1) <= not( dcd_001 and tiup ); + r_00_b(2) <= not( dcd_010 and tiup ); + r_00_b(3) <= not( dcd_011 and combo3_1110_0000 ); + r_00_b(4) <= not( dcd_100 and tidn ); + r_00_b(5) <= not( dcd_101 and tidn ); + r_00_b(6) <= not( dcd_110 and tidn ); + r_00_b(7) <= not( dcd_111 and tidn ); + + r( 0) <= not( r_00_b(0) and + r_00_b(1) and + r_00_b(2) and + r_00_b(3) and + r_00_b(4) and + r_00_b(5) and + r_00_b(6) and + r_00_b(7) ); + + r_01_b(0) <= not( dcd_000 and tiup ); + r_01_b(1) <= not( dcd_001 and combo3_1100_0000 ); + r_01_b(2) <= not( dcd_010 and tidn ); + r_01_b(3) <= not( dcd_011 and combo3_0001_1111 ); + r_01_b(4) <= not( dcd_100 and tiup ); + r_01_b(5) <= not( dcd_101 and tiup ); + r_01_b(6) <= not( dcd_110 and tiup ); + r_01_b(7) <= not( dcd_111 and tiup ); + + r( 1) <= not( r_01_b(0) and + r_01_b(1) and + r_01_b(2) and + r_01_b(3) and + r_01_b(4) and + r_01_b(5) and + r_01_b(6) and + r_01_b(7) ); + + r_02_b(0) <= not( dcd_000 and combo3_1111_0000 ); + r_02_b(1) <= not( dcd_001 and combo3_0011_1111 ); + r_02_b(2) <= not( dcd_010 and combo3_1000_0000 ); + r_02_b(3) <= not( dcd_011 and combo3_0001_1111 ); + r_02_b(4) <= not( dcd_100 and tiup ); + r_02_b(5) <= not( dcd_101 and combo3_1000_0000 ); + r_02_b(6) <= not( dcd_110 and tidn ); + r_02_b(7) <= not( dcd_111 and tidn ); + + r( 2) <= not( r_02_b(0) and + r_02_b(1) and + r_02_b(2) and + r_02_b(3) and + r_02_b(4) and + r_02_b(5) and + r_02_b(6) and + r_02_b(7) ); + + r_03_b(0) <= not( dcd_000 and combo3_1100_1110 ); + r_03_b(1) <= not( dcd_001 and combo3_0011_1000 ); + r_03_b(2) <= not( dcd_010 and combo3_0111_1000 ); + r_03_b(3) <= not( dcd_011 and combo3_0001_1111 ); + r_03_b(4) <= not( dcd_100 and combo3_1000_0000 ); + r_03_b(5) <= not( dcd_101 and combo3_0111_1111 ); + r_03_b(6) <= not( dcd_110 and combo3_1100_0000 ); + r_03_b(7) <= not( dcd_111 and tidn ); + + r( 3) <= not( r_03_b(0) and + r_03_b(1) and + r_03_b(2) and + r_03_b(3) and + r_03_b(4) and + r_03_b(5) and + r_03_b(6) and + r_03_b(7) ); + + r_04_b(0) <= not( dcd_000 and combo3_1010_1101 ); + r_04_b(1) <= not( dcd_001 and combo3_0010_0110 ); + r_04_b(2) <= not( dcd_010 and combo3_0110_0111 ); + r_04_b(3) <= not( dcd_011 and combo3_0001_1000 ); + r_04_b(4) <= not( dcd_100 and combo3_0111_0000 ); + r_04_b(5) <= not( dcd_101 and combo3_0111_1000 ); + r_04_b(6) <= not( dcd_110 and combo3_0011_1111 ); + r_04_b(7) <= not( dcd_111 and combo3_1000_0000 ); + + r( 4) <= not( r_04_b(0) and + r_04_b(1) and + r_04_b(2) and + r_04_b(3) and + r_04_b(4) and + r_04_b(5) and + r_04_b(6) and + r_04_b(7) ); + + r_05_b(0) <= not( dcd_000 and combo3_1111_1001 ); + r_05_b(1) <= not( dcd_001 and combo3_1011_0101 ); + r_05_b(2) <= not( dcd_010 and combo3_0101_0110 ); + r_05_b(3) <= not( dcd_011 and combo3_1001_0110 ); + r_05_b(4) <= not( dcd_100 and combo3_0110_1100 ); + r_05_b(5) <= not( dcd_101 and combo3_0110_0111 ); + r_05_b(6) <= not( dcd_110 and combo3_0011_1000 ); + r_05_b(7) <= not( dcd_111 and combo3_0111_0000 ); + + r( 5) <= not( r_05_b(0) and + r_05_b(1) and + r_05_b(2) and + r_05_b(3) and + r_05_b(4) and + r_05_b(5) and + r_05_b(6) and + r_05_b(7) ); + + r_06_b(0) <= not( dcd_000 and combo3_0001_1010 ); + r_06_b(1) <= not( dcd_001 and combo3_1101_1110 ); + r_06_b(2) <= not( dcd_010 and combo3_0011_1100 ); + r_06_b(3) <= not( dcd_011 and combo3_0100_1101 ); + r_06_b(4) <= not( dcd_100 and combo3_0100_1010 ); + r_06_b(5) <= not( dcd_101 and combo3_0101_0100 ); + r_06_b(6) <= not( dcd_110 and combo3_1011_0110 ); + r_06_b(7) <= not( dcd_111 and combo3_0100_1100 ); + + r( 6) <= not( r_06_b(0) and + r_06_b(1) and + r_06_b(2) and + r_06_b(3) and + r_06_b(4) and + r_06_b(5) and + r_06_b(6) and + r_06_b(7) ); + + r_07_b(0) <= not( dcd_000 and combo3_0010_1101 ); + r_07_b(1) <= not( dcd_001 and combo3_1001_1001 ); + r_07_b(2) <= not( dcd_010 and combo3_1100_0100 ); + r_07_b(3) <= not( dcd_011 and combo3_1001_0110 ); + r_07_b(4) <= not( dcd_100 and combo3_0001_1111 ); + r_07_b(5) <= not( dcd_101 and combo3_0000_1110 ); + r_07_b(6) <= not( dcd_110 and combo3_0110_1101 ); + r_07_b(7) <= not( dcd_111 and combo3_0110_1010 ); + + r( 7) <= not( r_07_b(0) and + r_07_b(1) and + r_07_b(2) and + r_07_b(3) and + r_07_b(4) and + r_07_b(5) and + r_07_b(6) and + r_07_b(7) ); + + r_08_b(0) <= not( dcd_000 and combo3_0000_0010 ); + r_08_b(1) <= not( dcd_001 and combo3_1011_0101 ); + r_08_b(2) <= not( dcd_010 and combo3_1100_1001 ); + r_08_b(3) <= not( dcd_011 and combo3_1100_1101 ); + r_08_b(4) <= not( dcd_100 and combo3_1001_1111 ); + r_08_b(5) <= not( dcd_101 and combo3_0001_0010 ); + r_08_b(6) <= not( dcd_110 and combo3_1011_0110 ); + r_08_b(7) <= not( dcd_111 and combo3_0011_1111 ); + + r( 8) <= not( r_08_b(0) and + r_08_b(1) and + r_08_b(2) and + r_08_b(3) and + r_08_b(4) and + r_08_b(5) and + r_08_b(6) and + r_08_b(7) ); + + r_09_b(0) <= not( dcd_000 and combo3_0100_1010 ); + r_09_b(1) <= not( dcd_001 and combo3_0011_0001 ); + r_09_b(2) <= not( dcd_010 and combo3_1101_1101 ); + r_09_b(3) <= not( dcd_011 and combo3_1100_0111 ); + r_09_b(4) <= not( dcd_100 and combo3_0101_1111 ); + r_09_b(5) <= not( dcd_101 and combo3_0010_0111 ); + r_09_b(6) <= not( dcd_110 and combo3_1110_1101 ); + r_09_b(7) <= not( dcd_111 and combo3_0011_0000 ); + + r( 9) <= not( r_09_b(0) and + r_09_b(1) and + r_09_b(2) and + r_09_b(3) and + r_09_b(4) and + r_09_b(5) and + r_09_b(6) and + r_09_b(7) ); + + r_10_b(0) <= not( dcd_000 and combo3_0111_1010 ); + r_10_b(1) <= not( dcd_001 and combo3_0011_1011 ); + r_10_b(2) <= not( dcd_010 and combo3_0001_0111 ); + r_10_b(3) <= not( dcd_011 and combo3_1101_0111 ); + r_10_b(4) <= not( dcd_100 and combo3_0001_0001 ); + r_10_b(5) <= not( dcd_101 and combo3_0111_0110 ); + r_10_b(6) <= not( dcd_110 and combo3_0110_0111 ); + r_10_b(7) <= not( dcd_111 and combo3_1010_1000 ); + + r(10) <= not( r_10_b(0) and + r_10_b(1) and + r_10_b(2) and + r_10_b(3) and + r_10_b(4) and + r_10_b(5) and + r_10_b(6) and + r_10_b(7) ); + + r_11_b(0) <= not( dcd_000 and combo3_0000_1111 ); + r_11_b(1) <= not( dcd_001 and combo3_0101_0100 ); + r_11_b(2) <= not( dcd_010 and combo3_1110_1101 ); + r_11_b(3) <= not( dcd_011 and combo3_0001_0101 ); + r_11_b(4) <= not( dcd_100 and combo3_1010_1000 ); + r_11_b(5) <= not( dcd_101 and combo3_0111_1101 ); + r_11_b(6) <= not( dcd_110 and combo3_1011_0100 ); + r_11_b(7) <= not( dcd_111 and combo3_1000_0100 ); + + r(11) <= not( r_11_b(0) and + r_11_b(1) and + r_11_b(2) and + r_11_b(3) and + r_11_b(4) and + r_11_b(5) and + r_11_b(6) and + r_11_b(7) ); + + r_12_b(0) <= not( dcd_000 and combo3_1100_1111 ); + r_12_b(1) <= not( dcd_001 and combo3_0110_1011 ); + r_12_b(2) <= not( dcd_010 and combo3_0100_1000 ); + r_12_b(3) <= not( dcd_011 and combo3_0111_1011 ); + r_12_b(4) <= not( dcd_100 and combo3_1101_0110 ); + r_12_b(5) <= not( dcd_101 and combo3_0001_0001 ); + r_12_b(6) <= not( dcd_110 and combo3_1011_0011 ); + r_12_b(7) <= not( dcd_111 and combo3_0100_0000 ); + + r(12) <= not( r_12_b(0) and + r_12_b(1) and + r_12_b(2) and + r_12_b(3) and + r_12_b(4) and + r_12_b(5) and + r_12_b(6) and + r_12_b(7) ); + + r_13_b(0) <= not( dcd_000 and combo3_0101_0001 ); + r_13_b(1) <= not( dcd_001 and combo3_0011_1100 ); + r_13_b(2) <= not( dcd_010 and combo3_0101_1011 ); + r_13_b(3) <= not( dcd_011 and combo3_0001_1000 ); + r_13_b(4) <= not( dcd_100 and combo3_0110_0010 ); + r_13_b(5) <= not( dcd_101 and combo3_1101_0100 ); + r_13_b(6) <= not( dcd_110 and combo3_0100_0011 ); + r_13_b(7) <= not( dcd_111 and combo3_1000_1010 ); + + r(13) <= not( r_13_b(0) and + r_13_b(1) and + r_13_b(2) and + r_13_b(3) and + r_13_b(4) and + r_13_b(5) and + r_13_b(6) and + r_13_b(7) ); + + r_14_b(0) <= not( dcd_000 and combo3_1000_0000 ); + r_14_b(1) <= not( dcd_001 and tidn ); + r_14_b(2) <= not( dcd_010 and tidn ); + r_14_b(3) <= not( dcd_011 and tidn ); + r_14_b(4) <= not( dcd_100 and tidn ); + r_14_b(5) <= not( dcd_101 and tidn ); + r_14_b(6) <= not( dcd_110 and tidn ); + r_14_b(7) <= not( dcd_111 and tidn ); + + r(14) <= not( r_14_b(0) and + r_14_b(1) and + r_14_b(2) and + r_14_b(3) and + r_14_b(4) and + r_14_b(5) and + r_14_b(6) and + r_14_b(7) ); + + + + + + est(1 to 20) <= e(0 to 19); + rng(6 to 20) <= r(0 to 14); + + +end; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_tblsqe.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_tblsqe.vhdl new file mode 100644 index 0000000..9042324 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_tblsqe.vhdl @@ -0,0 +1,1138 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; + use ieee.std_logic_1164.all ; +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + + +entity fuq_tblsqe is +generic( expand_type : integer := 2 ); +port( + f :in std_ulogic_vector(1 to 6); + est :out std_ulogic_vector(1 to 20); + rng :out std_ulogic_vector(6 to 20) + +); + + + +end fuq_tblsqe; + + +architecture fuq_tblsqe of fuq_tblsqe is + + constant tiup :std_ulogic := '1'; + constant tidn :std_ulogic := '0'; + + signal dcd_00x :std_ulogic; + signal dcd_01x :std_ulogic; + signal dcd_10x :std_ulogic; + signal dcd_11x :std_ulogic; + signal dcd_000 :std_ulogic; + signal dcd_001 :std_ulogic; + signal dcd_010 :std_ulogic; + signal dcd_011 :std_ulogic; + signal dcd_100 :std_ulogic; + signal dcd_101 :std_ulogic; + signal dcd_110 :std_ulogic; + signal dcd_111 :std_ulogic; + signal combo2_1000 :std_ulogic; + signal combo2_0100 :std_ulogic; + signal combo2_1100 :std_ulogic; + signal combo2_0010 :std_ulogic; + signal combo2_1010 :std_ulogic; + signal combo2_0110 :std_ulogic; + signal combo2_1110 :std_ulogic; + signal combo2_0001 :std_ulogic; + signal combo2_1001 :std_ulogic; + signal combo2_0101 :std_ulogic; + signal combo2_1101 :std_ulogic; + signal combo2_0011 :std_ulogic; + signal combo2_1011 :std_ulogic; + signal combo2_0111 :std_ulogic; + signal combo2_1000_xxxx_b :std_ulogic; + signal combo2_0100_xxxx_b :std_ulogic; + signal combo2_1100_xxxx_b :std_ulogic; + signal combo2_0010_xxxx_b :std_ulogic; + signal combo2_1010_xxxx_b :std_ulogic; + signal combo2_0110_xxxx_b :std_ulogic; + signal combo2_1110_xxxx_b :std_ulogic; + signal combo2_0001_xxxx_b :std_ulogic; + signal combo2_1001_xxxx_b :std_ulogic; + signal combo2_0101_xxxx_b :std_ulogic; + signal combo2_1101_xxxx_b :std_ulogic; + signal combo2_0011_xxxx_b :std_ulogic; + signal combo2_1011_xxxx_b :std_ulogic; + signal combo2_0111_xxxx_b :std_ulogic; + signal combo2_xxxx_1000_b :std_ulogic; + signal combo2_xxxx_0100_b :std_ulogic; + signal combo2_xxxx_1100_b :std_ulogic; + signal combo2_xxxx_0010_b :std_ulogic; + signal combo2_xxxx_1010_b :std_ulogic; + signal combo2_xxxx_0110_b :std_ulogic; + signal combo2_xxxx_1110_b :std_ulogic; + signal combo2_xxxx_0001_b :std_ulogic; + signal combo2_xxxx_1001_b :std_ulogic; + signal combo2_xxxx_0101_b :std_ulogic; + signal combo2_xxxx_1101_b :std_ulogic; + signal combo2_xxxx_0011_b :std_ulogic; + signal combo2_xxxx_1011_b :std_ulogic; + signal combo2_xxxx_0111_b :std_ulogic; + signal combo3_0000_0001 :std_ulogic; + signal combo3_0000_0011 :std_ulogic; + signal combo3_0000_0100 :std_ulogic; + signal combo3_0000_0111 :std_ulogic; + signal combo3_0000_1001 :std_ulogic; + signal combo3_0000_1010 :std_ulogic; + signal combo3_0000_1011 :std_ulogic; + signal combo3_0000_1101 :std_ulogic; + signal combo3_0000_1111 :std_ulogic; + signal combo3_0001_0001 :std_ulogic; + signal combo3_0001_0010 :std_ulogic; + signal combo3_0001_0100 :std_ulogic; + signal combo3_0001_0101 :std_ulogic; + signal combo3_0001_0111 :std_ulogic; + signal combo3_0001_1000 :std_ulogic; + signal combo3_0001_1100 :std_ulogic; + signal combo3_0001_1101 :std_ulogic; + signal combo3_0001_1110 :std_ulogic; + signal combo3_0001_1111 :std_ulogic; + signal combo3_0010_0001 :std_ulogic; + signal combo3_0010_0011 :std_ulogic; + signal combo3_0010_0100 :std_ulogic; + signal combo3_0010_0101 :std_ulogic; + signal combo3_0010_1000 :std_ulogic; + signal combo3_0010_1001 :std_ulogic; + signal combo3_0010_1010 :std_ulogic; + signal combo3_0010_1100 :std_ulogic; + signal combo3_0010_1101 :std_ulogic; + signal combo3_0010_1110 :std_ulogic; + signal combo3_0010_1111 :std_ulogic; + signal combo3_0011_0000 :std_ulogic; + signal combo3_0011_0001 :std_ulogic; + signal combo3_0011_0011 :std_ulogic; + signal combo3_0011_0101 :std_ulogic; + signal combo3_0011_0110 :std_ulogic; + signal combo3_0011_1000 :std_ulogic; + signal combo3_0011_1001 :std_ulogic; + signal combo3_0011_1110 :std_ulogic; + signal combo3_0011_1111 :std_ulogic; + signal combo3_0100_0000 :std_ulogic; + signal combo3_0100_0010 :std_ulogic; + signal combo3_0100_0100 :std_ulogic; + signal combo3_0100_0101 :std_ulogic; + signal combo3_0100_1001 :std_ulogic; + signal combo3_0100_1100 :std_ulogic; + signal combo3_0100_1110 :std_ulogic; + signal combo3_0100_1111 :std_ulogic; + signal combo3_0101_0010 :std_ulogic; + signal combo3_0101_0100 :std_ulogic; + signal combo3_0101_0110 :std_ulogic; + signal combo3_0101_1001 :std_ulogic; + signal combo3_0101_1100 :std_ulogic; + signal combo3_0101_1111 :std_ulogic; + signal combo3_0110_0000 :std_ulogic; + signal combo3_0110_0011 :std_ulogic; + signal combo3_0110_0110 :std_ulogic; + signal combo3_0110_0111 :std_ulogic; + signal combo3_0110_1100 :std_ulogic; + signal combo3_0110_1101 :std_ulogic; + signal combo3_0110_1111 :std_ulogic; + signal combo3_0111_0000 :std_ulogic; + signal combo3_0111_0101 :std_ulogic; + signal combo3_0111_0111 :std_ulogic; + signal combo3_0111_1000 :std_ulogic; + signal combo3_0111_1001 :std_ulogic; + signal combo3_0111_1010 :std_ulogic; + signal combo3_0111_1111 :std_ulogic; + signal combo3_1000_0000 :std_ulogic; + signal combo3_1000_0011 :std_ulogic; + signal combo3_1000_0110 :std_ulogic; + signal combo3_1000_0111 :std_ulogic; + signal combo3_1000_1010 :std_ulogic; + signal combo3_1000_1110 :std_ulogic; + signal combo3_1001_0000 :std_ulogic; + signal combo3_1001_0001 :std_ulogic; + signal combo3_1001_0010 :std_ulogic; + signal combo3_1001_0100 :std_ulogic; + signal combo3_1001_0110 :std_ulogic; + signal combo3_1001_0111 :std_ulogic; + signal combo3_1001_1000 :std_ulogic; + signal combo3_1001_1001 :std_ulogic; + signal combo3_1001_1010 :std_ulogic; + signal combo3_1001_1011 :std_ulogic; + signal combo3_1001_1100 :std_ulogic; + signal combo3_1010_0000 :std_ulogic; + signal combo3_1010_0001 :std_ulogic; + signal combo3_1010_0010 :std_ulogic; + signal combo3_1010_0100 :std_ulogic; + signal combo3_1010_0101 :std_ulogic; + signal combo3_1010_0110 :std_ulogic; + signal combo3_1010_0111 :std_ulogic; + signal combo3_1010_1001 :std_ulogic; + signal combo3_1010_1010 :std_ulogic; + signal combo3_1010_1100 :std_ulogic; + signal combo3_1010_1101 :std_ulogic; + signal combo3_1010_1111 :std_ulogic; + signal combo3_1011_0001 :std_ulogic; + signal combo3_1011_0010 :std_ulogic; + signal combo3_1011_0100 :std_ulogic; + signal combo3_1011_0101 :std_ulogic; + signal combo3_1011_1000 :std_ulogic; + signal combo3_1011_1010 :std_ulogic; + signal combo3_1011_1100 :std_ulogic; + signal combo3_1100_0000 :std_ulogic; + signal combo3_1100_0001 :std_ulogic; + signal combo3_1100_0011 :std_ulogic; + signal combo3_1100_0101 :std_ulogic; + signal combo3_1100_0110 :std_ulogic; + signal combo3_1100_0111 :std_ulogic; + signal combo3_1100_1001 :std_ulogic; + signal combo3_1100_1010 :std_ulogic; + signal combo3_1100_1011 :std_ulogic; + signal combo3_1100_1101 :std_ulogic; + signal combo3_1100_1111 :std_ulogic; + signal combo3_1101_0010 :std_ulogic; + signal combo3_1101_0011 :std_ulogic; + signal combo3_1101_1000 :std_ulogic; + signal combo3_1101_1001 :std_ulogic; + signal combo3_1101_1010 :std_ulogic; + signal combo3_1101_1100 :std_ulogic; + signal combo3_1101_1110 :std_ulogic; + signal combo3_1101_1111 :std_ulogic; + signal combo3_1110_0000 :std_ulogic; + signal combo3_1110_0001 :std_ulogic; + signal combo3_1110_0011 :std_ulogic; + signal combo3_1110_0110 :std_ulogic; + signal combo3_1110_1000 :std_ulogic; + signal combo3_1110_1010 :std_ulogic; + signal combo3_1110_1101 :std_ulogic; + signal combo3_1111_0000 :std_ulogic; + signal combo3_1111_0001 :std_ulogic; + signal combo3_1111_0010 :std_ulogic; + signal combo3_1111_1000 :std_ulogic; + signal combo3_1111_1001 :std_ulogic; + signal combo3_1111_1010 :std_ulogic; + signal combo3_1111_1100 :std_ulogic; + signal e_00_b :std_ulogic_vector(0 to 7); + signal e_01_b :std_ulogic_vector(0 to 7); + signal e_02_b :std_ulogic_vector(0 to 7); + signal e_03_b :std_ulogic_vector(0 to 7); + signal e_04_b :std_ulogic_vector(0 to 7); + signal e_05_b :std_ulogic_vector(0 to 7); + signal e_06_b :std_ulogic_vector(0 to 7); + signal e_07_b :std_ulogic_vector(0 to 7); + signal e_08_b :std_ulogic_vector(0 to 7); + signal e_09_b :std_ulogic_vector(0 to 7); + signal e_10_b :std_ulogic_vector(0 to 7); + signal e_11_b :std_ulogic_vector(0 to 7); + signal e_12_b :std_ulogic_vector(0 to 7); + signal e_13_b :std_ulogic_vector(0 to 7); + signal e_14_b :std_ulogic_vector(0 to 7); + signal e_15_b :std_ulogic_vector(0 to 7); + signal e_16_b :std_ulogic_vector(0 to 7); + signal e_17_b :std_ulogic_vector(0 to 7); + signal e_18_b :std_ulogic_vector(0 to 7); + signal e_19_b :std_ulogic_vector(0 to 7); + signal e :std_ulogic_vector(0 to 19); + signal r_00_b :std_ulogic_vector(0 to 7); + signal r_01_b :std_ulogic_vector(0 to 7); + signal r_02_b :std_ulogic_vector(0 to 7); + signal r_03_b :std_ulogic_vector(0 to 7); + signal r_04_b :std_ulogic_vector(0 to 7); + signal r_05_b :std_ulogic_vector(0 to 7); + signal r_06_b :std_ulogic_vector(0 to 7); + signal r_07_b :std_ulogic_vector(0 to 7); + signal r_08_b :std_ulogic_vector(0 to 7); + signal r_09_b :std_ulogic_vector(0 to 7); + signal r_10_b :std_ulogic_vector(0 to 7); + signal r_11_b :std_ulogic_vector(0 to 7); + signal r_12_b :std_ulogic_vector(0 to 7); + signal r_13_b :std_ulogic_vector(0 to 7); + signal r_14_b :std_ulogic_vector(0 to 7); + signal r :std_ulogic_vector(0 to 14); + + +begin + + + + dcd_00x <= not f(1) and not f(2) ; + dcd_01x <= not f(1) and f(2) ; + dcd_10x <= f(1) and not f(2) ; + dcd_11x <= f(1) and f(2) ; + + dcd_000 <= not f(3) and dcd_00x ; + dcd_001 <= f(3) and dcd_00x ; + dcd_010 <= not f(3) and dcd_01x ; + dcd_011 <= f(3) and dcd_01x ; + dcd_100 <= not f(3) and dcd_10x ; + dcd_101 <= f(3) and dcd_10x ; + dcd_110 <= not f(3) and dcd_11x ; + dcd_111 <= f(3) and dcd_11x ; + + + + combo2_1000 <= not f(5) and not f(6) ; + combo2_0100 <= not f(5) and f(6) ; + combo2_1100 <= not f(5) ; + combo2_0010 <= f(5) and not f(6) ; + combo2_1010 <= not f(6) ; + combo2_0110 <= f(5) xor f(6) ; + combo2_1110 <= not( f(5) and f(6) ) ; + combo2_0001 <= f(5) and f(6) ; + combo2_1001 <= not( f(5) xor f(6) ) ; + combo2_0101 <= f(6) ; + combo2_1101 <= not( f(5) and not f(6) ) ; + combo2_0011 <= f(5) ; + combo2_1011 <= not( not f(5) and f(6) ) ; + combo2_0111 <= not( not f(5) and not f(6) ) ; + + + + combo2_1000_xxxx_b <= not( not f(4) and combo2_1000 ); + combo2_0100_xxxx_b <= not( not f(4) and combo2_0100 ); + combo2_1100_xxxx_b <= not( not f(4) and combo2_1100 ); + combo2_0010_xxxx_b <= not( not f(4) and combo2_0010 ); + combo2_1010_xxxx_b <= not( not f(4) and combo2_1010 ); + combo2_0110_xxxx_b <= not( not f(4) and combo2_0110 ); + combo2_1110_xxxx_b <= not( not f(4) and combo2_1110 ); + combo2_0001_xxxx_b <= not( not f(4) and combo2_0001 ); + combo2_1001_xxxx_b <= not( not f(4) and combo2_1001 ); + combo2_0101_xxxx_b <= not( not f(4) and combo2_0101 ); + combo2_1101_xxxx_b <= not( not f(4) and combo2_1101 ); + combo2_0011_xxxx_b <= not( not f(4) and combo2_0011 ); + combo2_1011_xxxx_b <= not( not f(4) and combo2_1011 ); + combo2_0111_xxxx_b <= not( not f(4) and combo2_0111 ); + + + combo2_xxxx_1000_b <= not( f(4) and combo2_1000 ); + combo2_xxxx_0100_b <= not( f(4) and combo2_0100 ); + combo2_xxxx_1100_b <= not( f(4) and combo2_1100 ); + combo2_xxxx_0010_b <= not( f(4) and combo2_0010 ); + combo2_xxxx_1010_b <= not( f(4) and combo2_1010 ); + combo2_xxxx_0110_b <= not( f(4) and combo2_0110 ); + combo2_xxxx_1110_b <= not( f(4) and combo2_1110 ); + combo2_xxxx_0001_b <= not( f(4) and combo2_0001 ); + combo2_xxxx_1001_b <= not( f(4) and combo2_1001 ); + combo2_xxxx_0101_b <= not( f(4) and combo2_0101 ); + combo2_xxxx_1101_b <= not( f(4) and combo2_1101 ); + combo2_xxxx_0011_b <= not( f(4) and combo2_0011 ); + combo2_xxxx_1011_b <= not( f(4) and combo2_1011 ); + combo2_xxxx_0111_b <= not( f(4) and combo2_0111 ); + + + combo3_0000_0001 <= not( combo2_xxxx_0001_b ); + combo3_0000_0011 <= not( combo2_xxxx_0011_b ); + combo3_0000_0100 <= not( combo2_xxxx_0100_b ); + combo3_0000_0111 <= not( combo2_xxxx_0111_b ); + combo3_0000_1001 <= not( combo2_xxxx_1001_b ); + combo3_0000_1010 <= not( combo2_xxxx_1010_b ); + combo3_0000_1011 <= not( combo2_xxxx_1011_b ); + combo3_0000_1101 <= not( combo2_xxxx_1101_b ); + combo3_0000_1111 <= not( not f(4) ); + combo3_0001_0001 <= not( not combo2_0001 ); + combo3_0001_0010 <= not( combo2_0001_xxxx_b and combo2_xxxx_0010_b ); + combo3_0001_0100 <= not( combo2_0001_xxxx_b and combo2_xxxx_0100_b ); + combo3_0001_0101 <= not( combo2_0001_xxxx_b and combo2_xxxx_0101_b ); + combo3_0001_0111 <= not( combo2_0001_xxxx_b and combo2_xxxx_0111_b ); + combo3_0001_1000 <= not( combo2_0001_xxxx_b and combo2_xxxx_1000_b ); + combo3_0001_1100 <= not( combo2_0001_xxxx_b and combo2_xxxx_1100_b ); + combo3_0001_1101 <= not( combo2_0001_xxxx_b and combo2_xxxx_1101_b ); + combo3_0001_1110 <= not( combo2_0001_xxxx_b and combo2_xxxx_1110_b ); + combo3_0001_1111 <= not( combo2_0001_xxxx_b and not f(4) ); + combo3_0010_0001 <= not( combo2_0010_xxxx_b and combo2_xxxx_0001_b ); + combo3_0010_0011 <= not( combo2_0010_xxxx_b and combo2_xxxx_0011_b ); + combo3_0010_0100 <= not( combo2_0010_xxxx_b and combo2_xxxx_0100_b ); + combo3_0010_0101 <= not( combo2_0010_xxxx_b and combo2_xxxx_0101_b ); + combo3_0010_1000 <= not( combo2_0010_xxxx_b and combo2_xxxx_1000_b ); + combo3_0010_1001 <= not( combo2_0010_xxxx_b and combo2_xxxx_1001_b ); + combo3_0010_1010 <= not( combo2_0010_xxxx_b and combo2_xxxx_1010_b ); + combo3_0010_1100 <= not( combo2_0010_xxxx_b and combo2_xxxx_1100_b ); + combo3_0010_1101 <= not( combo2_0010_xxxx_b and combo2_xxxx_1101_b ); + combo3_0010_1110 <= not( combo2_0010_xxxx_b and combo2_xxxx_1110_b ); + combo3_0010_1111 <= not( combo2_0010_xxxx_b and not f(4) ); + combo3_0011_0000 <= not( combo2_0011_xxxx_b ); + combo3_0011_0001 <= not( combo2_0011_xxxx_b and combo2_xxxx_0001_b ); + combo3_0011_0011 <= not( not combo2_0011 ); + combo3_0011_0101 <= not( combo2_0011_xxxx_b and combo2_xxxx_0101_b ); + combo3_0011_0110 <= not( combo2_0011_xxxx_b and combo2_xxxx_0110_b ); + combo3_0011_1000 <= not( combo2_0011_xxxx_b and combo2_xxxx_1000_b ); + combo3_0011_1001 <= not( combo2_0011_xxxx_b and combo2_xxxx_1001_b ); + combo3_0011_1110 <= not( combo2_0011_xxxx_b and combo2_xxxx_1110_b ); + combo3_0011_1111 <= not( combo2_0011_xxxx_b and not f(4) ); + combo3_0100_0000 <= not( combo2_0100_xxxx_b ); + combo3_0100_0010 <= not( combo2_0100_xxxx_b and combo2_xxxx_0010_b ); + combo3_0100_0100 <= not( not combo2_0100 ); + combo3_0100_0101 <= not( combo2_0100_xxxx_b and combo2_xxxx_0101_b ); + combo3_0100_1001 <= not( combo2_0100_xxxx_b and combo2_xxxx_1001_b ); + combo3_0100_1100 <= not( combo2_0100_xxxx_b and combo2_xxxx_1100_b ); + combo3_0100_1110 <= not( combo2_0100_xxxx_b and combo2_xxxx_1110_b ); + combo3_0100_1111 <= not( combo2_0100_xxxx_b and not f(4) ); + combo3_0101_0010 <= not( combo2_0101_xxxx_b and combo2_xxxx_0010_b ); + combo3_0101_0100 <= not( combo2_0101_xxxx_b and combo2_xxxx_0100_b ); + combo3_0101_0110 <= not( combo2_0101_xxxx_b and combo2_xxxx_0110_b ); + combo3_0101_1001 <= not( combo2_0101_xxxx_b and combo2_xxxx_1001_b ); + combo3_0101_1100 <= not( combo2_0101_xxxx_b and combo2_xxxx_1100_b ); + combo3_0101_1111 <= not( combo2_0101_xxxx_b and not f(4) ); + combo3_0110_0000 <= not( combo2_0110_xxxx_b ); + combo3_0110_0011 <= not( combo2_0110_xxxx_b and combo2_xxxx_0011_b ); + combo3_0110_0110 <= not( not combo2_0110 ); + combo3_0110_0111 <= not( combo2_0110_xxxx_b and combo2_xxxx_0111_b ); + combo3_0110_1100 <= not( combo2_0110_xxxx_b and combo2_xxxx_1100_b ); + combo3_0110_1101 <= not( combo2_0110_xxxx_b and combo2_xxxx_1101_b ); + combo3_0110_1111 <= not( combo2_0110_xxxx_b and not f(4) ); + combo3_0111_0000 <= not( combo2_0111_xxxx_b ); + combo3_0111_0101 <= not( combo2_0111_xxxx_b and combo2_xxxx_0101_b ); + combo3_0111_0111 <= not( not combo2_0111 ); + combo3_0111_1000 <= not( combo2_0111_xxxx_b and combo2_xxxx_1000_b ); + combo3_0111_1001 <= not( combo2_0111_xxxx_b and combo2_xxxx_1001_b ); + combo3_0111_1010 <= not( combo2_0111_xxxx_b and combo2_xxxx_1010_b ); + combo3_0111_1111 <= not( combo2_0111_xxxx_b and not f(4) ); + combo3_1000_0000 <= not( combo2_1000_xxxx_b ); + combo3_1000_0011 <= not( combo2_1000_xxxx_b and combo2_xxxx_0011_b ); + combo3_1000_0110 <= not( combo2_1000_xxxx_b and combo2_xxxx_0110_b ); + combo3_1000_0111 <= not( combo2_1000_xxxx_b and combo2_xxxx_0111_b ); + combo3_1000_1010 <= not( combo2_1000_xxxx_b and combo2_xxxx_1010_b ); + combo3_1000_1110 <= not( combo2_1000_xxxx_b and combo2_xxxx_1110_b ); + combo3_1001_0000 <= not( combo2_1001_xxxx_b ); + combo3_1001_0001 <= not( combo2_1001_xxxx_b and combo2_xxxx_0001_b ); + combo3_1001_0010 <= not( combo2_1001_xxxx_b and combo2_xxxx_0010_b ); + combo3_1001_0100 <= not( combo2_1001_xxxx_b and combo2_xxxx_0100_b ); + combo3_1001_0110 <= not( combo2_1001_xxxx_b and combo2_xxxx_0110_b ); + combo3_1001_0111 <= not( combo2_1001_xxxx_b and combo2_xxxx_0111_b ); + combo3_1001_1000 <= not( combo2_1001_xxxx_b and combo2_xxxx_1000_b ); + combo3_1001_1001 <= not( not combo2_1001 ); + combo3_1001_1010 <= not( combo2_1001_xxxx_b and combo2_xxxx_1010_b ); + combo3_1001_1011 <= not( combo2_1001_xxxx_b and combo2_xxxx_1011_b ); + combo3_1001_1100 <= not( combo2_1001_xxxx_b and combo2_xxxx_1100_b ); + combo3_1010_0000 <= not( combo2_1010_xxxx_b ); + combo3_1010_0001 <= not( combo2_1010_xxxx_b and combo2_xxxx_0001_b ); + combo3_1010_0010 <= not( combo2_1010_xxxx_b and combo2_xxxx_0010_b ); + combo3_1010_0100 <= not( combo2_1010_xxxx_b and combo2_xxxx_0100_b ); + combo3_1010_0101 <= not( combo2_1010_xxxx_b and combo2_xxxx_0101_b ); + combo3_1010_0110 <= not( combo2_1010_xxxx_b and combo2_xxxx_0110_b ); + combo3_1010_0111 <= not( combo2_1010_xxxx_b and combo2_xxxx_0111_b ); + combo3_1010_1001 <= not( combo2_1010_xxxx_b and combo2_xxxx_1001_b ); + combo3_1010_1010 <= not( not combo2_1010 ); + combo3_1010_1100 <= not( combo2_1010_xxxx_b and combo2_xxxx_1100_b ); + combo3_1010_1101 <= not( combo2_1010_xxxx_b and combo2_xxxx_1101_b ); + combo3_1010_1111 <= not( combo2_1010_xxxx_b and not f(4) ); + combo3_1011_0001 <= not( combo2_1011_xxxx_b and combo2_xxxx_0001_b ); + combo3_1011_0010 <= not( combo2_1011_xxxx_b and combo2_xxxx_0010_b ); + combo3_1011_0100 <= not( combo2_1011_xxxx_b and combo2_xxxx_0100_b ); + combo3_1011_0101 <= not( combo2_1011_xxxx_b and combo2_xxxx_0101_b ); + combo3_1011_1000 <= not( combo2_1011_xxxx_b and combo2_xxxx_1000_b ); + combo3_1011_1010 <= not( combo2_1011_xxxx_b and combo2_xxxx_1010_b ); + combo3_1011_1100 <= not( combo2_1011_xxxx_b and combo2_xxxx_1100_b ); + combo3_1100_0000 <= not( combo2_1100_xxxx_b ); + combo3_1100_0001 <= not( combo2_1100_xxxx_b and combo2_xxxx_0001_b ); + combo3_1100_0011 <= not( combo2_1100_xxxx_b and combo2_xxxx_0011_b ); + combo3_1100_0101 <= not( combo2_1100_xxxx_b and combo2_xxxx_0101_b ); + combo3_1100_0110 <= not( combo2_1100_xxxx_b and combo2_xxxx_0110_b ); + combo3_1100_0111 <= not( combo2_1100_xxxx_b and combo2_xxxx_0111_b ); + combo3_1100_1001 <= not( combo2_1100_xxxx_b and combo2_xxxx_1001_b ); + combo3_1100_1010 <= not( combo2_1100_xxxx_b and combo2_xxxx_1010_b ); + combo3_1100_1011 <= not( combo2_1100_xxxx_b and combo2_xxxx_1011_b ); + combo3_1100_1101 <= not( combo2_1100_xxxx_b and combo2_xxxx_1101_b ); + combo3_1100_1111 <= not( combo2_1100_xxxx_b and not f(4) ); + combo3_1101_0010 <= not( combo2_1101_xxxx_b and combo2_xxxx_0010_b ); + combo3_1101_0011 <= not( combo2_1101_xxxx_b and combo2_xxxx_0011_b ); + combo3_1101_1000 <= not( combo2_1101_xxxx_b and combo2_xxxx_1000_b ); + combo3_1101_1001 <= not( combo2_1101_xxxx_b and combo2_xxxx_1001_b ); + combo3_1101_1010 <= not( combo2_1101_xxxx_b and combo2_xxxx_1010_b ); + combo3_1101_1100 <= not( combo2_1101_xxxx_b and combo2_xxxx_1100_b ); + combo3_1101_1110 <= not( combo2_1101_xxxx_b and combo2_xxxx_1110_b ); + combo3_1101_1111 <= not( combo2_1101_xxxx_b and not f(4) ); + combo3_1110_0000 <= not( combo2_1110_xxxx_b ); + combo3_1110_0001 <= not( combo2_1110_xxxx_b and combo2_xxxx_0001_b ); + combo3_1110_0011 <= not( combo2_1110_xxxx_b and combo2_xxxx_0011_b ); + combo3_1110_0110 <= not( combo2_1110_xxxx_b and combo2_xxxx_0110_b ); + combo3_1110_1000 <= not( combo2_1110_xxxx_b and combo2_xxxx_1000_b ); + combo3_1110_1010 <= not( combo2_1110_xxxx_b and combo2_xxxx_1010_b ); + combo3_1110_1101 <= not( combo2_1110_xxxx_b and combo2_xxxx_1101_b ); + combo3_1111_0000 <= not( f(4) ); + combo3_1111_0001 <= not( f(4) and combo2_xxxx_0001_b ); + combo3_1111_0010 <= not( f(4) and combo2_xxxx_0010_b ); + combo3_1111_1000 <= not( f(4) and combo2_xxxx_1000_b ); + combo3_1111_1001 <= not( f(4) and combo2_xxxx_1001_b ); + combo3_1111_1010 <= not( f(4) and combo2_xxxx_1010_b ); + combo3_1111_1100 <= not( f(4) and combo2_xxxx_1100_b ); + + + + e_00_b(0) <= not( dcd_000 and tidn ); + e_00_b(1) <= not( dcd_001 and tidn ); + e_00_b(2) <= not( dcd_010 and tidn ); + e_00_b(3) <= not( dcd_011 and tidn ); + e_00_b(4) <= not( dcd_100 and tidn ); + e_00_b(5) <= not( dcd_101 and tidn ); + e_00_b(6) <= not( dcd_110 and tidn ); + e_00_b(7) <= not( dcd_111 and tidn ); + + e( 0) <= not( e_00_b(0) and + e_00_b(1) and + e_00_b(2) and + e_00_b(3) and + e_00_b(4) and + e_00_b(5) and + e_00_b(6) and + e_00_b(7) ); + + e_01_b(0) <= not( dcd_000 and tiup ); + e_01_b(1) <= not( dcd_001 and tiup ); + e_01_b(2) <= not( dcd_010 and combo3_1100_0000 ); + e_01_b(3) <= not( dcd_011 and tidn ); + e_01_b(4) <= not( dcd_100 and tidn ); + e_01_b(5) <= not( dcd_101 and tidn ); + e_01_b(6) <= not( dcd_110 and tidn ); + e_01_b(7) <= not( dcd_111 and tidn ); + + e( 1) <= not( e_01_b(0) and + e_01_b(1) and + e_01_b(2) and + e_01_b(3) and + e_01_b(4) and + e_01_b(5) and + e_01_b(6) and + e_01_b(7) ); + + e_02_b(0) <= not( dcd_000 and combo3_1111_0000 ); + e_02_b(1) <= not( dcd_001 and tidn ); + e_02_b(2) <= not( dcd_010 and combo3_0011_1111 ); + e_02_b(3) <= not( dcd_011 and tiup ); + e_02_b(4) <= not( dcd_100 and combo3_1111_1100 ); + e_02_b(5) <= not( dcd_101 and tidn ); + e_02_b(6) <= not( dcd_110 and tidn ); + e_02_b(7) <= not( dcd_111 and tidn ); + + e( 2) <= not( e_02_b(0) and + e_02_b(1) and + e_02_b(2) and + e_02_b(3) and + e_02_b(4) and + e_02_b(5) and + e_02_b(6) and + e_02_b(7) ); + + e_03_b(0) <= not( dcd_000 and combo3_0000_1111 ); + e_03_b(1) <= not( dcd_001 and combo3_1110_0000 ); + e_03_b(2) <= not( dcd_010 and combo3_0011_1111 ); + e_03_b(3) <= not( dcd_011 and combo3_1110_0000 ); + e_03_b(4) <= not( dcd_100 and combo3_0000_0011 ); + e_03_b(5) <= not( dcd_101 and tiup ); + e_03_b(6) <= not( dcd_110 and combo3_1100_0000 ); + e_03_b(7) <= not( dcd_111 and tidn ); + + e( 3) <= not( e_03_b(0) and + e_03_b(1) and + e_03_b(2) and + e_03_b(3) and + e_03_b(4) and + e_03_b(5) and + e_03_b(6) and + e_03_b(7) ); + + e_04_b(0) <= not( dcd_000 and combo3_1000_1110 ); + e_04_b(1) <= not( dcd_001 and combo3_0001_1100 ); + e_04_b(2) <= not( dcd_010 and combo3_0011_1110 ); + e_04_b(3) <= not( dcd_011 and combo3_0001_1111 ); + e_04_b(4) <= not( dcd_100 and combo3_0000_0011 ); + e_04_b(5) <= not( dcd_101 and combo3_1110_0000 ); + e_04_b(6) <= not( dcd_110 and combo3_0011_1111 ); + e_04_b(7) <= not( dcd_111 and combo3_1000_0000 ); + + e( 4) <= not( e_04_b(0) and + e_04_b(1) and + e_04_b(2) and + e_04_b(3) and + e_04_b(4) and + e_04_b(5) and + e_04_b(6) and + e_04_b(7) ); + + e_05_b(0) <= not( dcd_000 and combo3_0110_1101 ); + e_05_b(1) <= not( dcd_001 and combo3_1001_1011 ); + e_05_b(2) <= not( dcd_010 and combo3_0011_0001 ); + e_05_b(3) <= not( dcd_011 and combo3_1001_1100 ); + e_05_b(4) <= not( dcd_100 and combo3_1110_0011 ); + e_05_b(5) <= not( dcd_101 and combo3_0001_1110 ); + e_05_b(6) <= not( dcd_110 and combo3_0011_1000 ); + e_05_b(7) <= not( dcd_111 and combo3_0111_1000 ); + + e( 5) <= not( e_05_b(0) and + e_05_b(1) and + e_05_b(2) and + e_05_b(3) and + e_05_b(4) and + e_05_b(5) and + e_05_b(6) and + e_05_b(7) ); + + e_06_b(0) <= not( dcd_000 and combo3_1100_1011 ); + e_06_b(1) <= not( dcd_001 and combo3_0101_0110 ); + e_06_b(2) <= not( dcd_010 and combo3_1010_1101 ); + e_06_b(3) <= not( dcd_011 and combo3_0101_0010 ); + e_06_b(4) <= not( dcd_100 and combo3_1101_0010 ); + e_06_b(5) <= not( dcd_101 and combo3_1101_1001 ); + e_06_b(6) <= not( dcd_110 and combo3_0011_0110 ); + e_06_b(7) <= not( dcd_111 and combo3_0110_0110 ); + + e( 6) <= not( e_06_b(0) and + e_06_b(1) and + e_06_b(2) and + e_06_b(3) and + e_06_b(4) and + e_06_b(5) and + e_06_b(6) and + e_06_b(7) ); + + e_07_b(0) <= not( dcd_000 and combo3_0101_1001 ); + e_07_b(1) <= not( dcd_001 and combo3_1000_0011 ); + e_07_b(2) <= not( dcd_010 and combo3_1111_1000 ); + e_07_b(3) <= not( dcd_011 and combo3_0011_1001 ); + e_07_b(4) <= not( dcd_100 and combo3_1001_1001 ); + e_07_b(5) <= not( dcd_101 and combo3_1011_0100 ); + e_07_b(6) <= not( dcd_110 and combo3_1010_0101 ); + e_07_b(7) <= not( dcd_111 and combo3_0101_0100 ); + + e( 7) <= not( e_07_b(0) and + e_07_b(1) and + e_07_b(2) and + e_07_b(3) and + e_07_b(4) and + e_07_b(5) and + e_07_b(6) and + e_07_b(7) ); + + e_08_b(0) <= not( dcd_000 and combo3_0001_0101 ); + e_08_b(1) <= not( dcd_001 and combo3_0110_0011 ); + e_08_b(2) <= not( dcd_010 and combo3_1111_1001 ); + e_08_b(3) <= not( dcd_011 and combo3_1101_1010 ); + e_08_b(4) <= not( dcd_100 and combo3_1010_1010 ); + e_08_b(5) <= not( dcd_101 and combo3_1101_1001 ); + e_08_b(6) <= not( dcd_110 and combo3_1000_1110 ); + e_08_b(7) <= not( dcd_111 and combo3_0000_0001 ); + + e( 8) <= not( e_08_b(0) and + e_08_b(1) and + e_08_b(2) and + e_08_b(3) and + e_08_b(4) and + e_08_b(5) and + e_08_b(6) and + e_08_b(7) ); + + e_09_b(0) <= not( dcd_000 and combo3_0011_0000 ); + e_09_b(1) <= not( dcd_001 and combo3_1101_0011 ); + e_09_b(2) <= not( dcd_010 and combo3_1111_1010 ); + e_09_b(3) <= not( dcd_011 and combo3_0110_1100 ); + e_09_b(4) <= not( dcd_100 and combo3_0000_0011 ); + e_09_b(5) <= not( dcd_101 and combo3_1011_0101 ); + e_09_b(6) <= not( dcd_110 and combo3_0100_1001 ); + e_09_b(7) <= not( dcd_111 and combo3_1100_0001 ); + + e( 9) <= not( e_09_b(0) and + e_09_b(1) and + e_09_b(2) and + e_09_b(3) and + e_09_b(4) and + e_09_b(5) and + e_09_b(6) and + e_09_b(7) ); + + e_10_b(0) <= not( dcd_000 and combo3_0110_1111 ); + e_10_b(1) <= not( dcd_001 and combo3_0111_1010 ); + e_10_b(2) <= not( dcd_010 and combo3_0001_1100 ); + e_10_b(3) <= not( dcd_011 and combo3_1100_1011 ); + e_10_b(4) <= not( dcd_100 and combo3_0000_0100 ); + e_10_b(5) <= not( dcd_101 and combo3_1101_1111 ); + e_10_b(6) <= not( dcd_110 and combo3_1110_1101 ); + e_10_b(7) <= not( dcd_111 and combo3_1011_0001 ); + + e(10) <= not( e_10_b(0) and + e_10_b(1) and + e_10_b(2) and + e_10_b(3) and + e_10_b(4) and + e_10_b(5) and + e_10_b(6) and + e_10_b(7) ); + + e_11_b(0) <= not( dcd_000 and combo3_0111_1001 ); + e_11_b(1) <= not( dcd_001 and combo3_1100_1001 ); + e_11_b(2) <= not( dcd_010 and combo3_0010_1000 ); + e_11_b(3) <= not( dcd_011 and combo3_1101_1110 ); + e_11_b(4) <= not( dcd_100 and combo3_1001_1001 ); + e_11_b(5) <= not( dcd_101 and combo3_1001_0000 ); + e_11_b(6) <= not( dcd_110 and combo3_0111_0111 ); + e_11_b(7) <= not( dcd_111 and combo3_0010_1001 ); + + e(11) <= not( e_11_b(0) and + e_11_b(1) and + e_11_b(2) and + e_11_b(3) and + e_11_b(4) and + e_11_b(5) and + e_11_b(6) and + e_11_b(7) ); + + e_12_b(0) <= not( dcd_000 and combo3_0110_0110 ); + e_12_b(1) <= not( dcd_001 and combo3_0111_0111 ); + e_12_b(2) <= not( dcd_010 and combo3_1100_1010 ); + e_12_b(3) <= not( dcd_011 and combo3_1111_0000 ); + e_12_b(4) <= not( dcd_100 and combo3_0110_1101 ); + e_12_b(5) <= not( dcd_101 and combo3_1011_1000 ); + e_12_b(6) <= not( dcd_110 and combo3_1010_0111 ); + e_12_b(7) <= not( dcd_111 and combo3_0100_0101 ); + + e(12) <= not( e_12_b(0) and + e_12_b(1) and + e_12_b(2) and + e_12_b(3) and + e_12_b(4) and + e_12_b(5) and + e_12_b(6) and + e_12_b(7) ); + + e_13_b(0) <= not( dcd_000 and combo3_1010_1001 ); + e_13_b(1) <= not( dcd_001 and combo3_0010_1110 ); + e_13_b(2) <= not( dcd_010 and combo3_1011_1010 ); + e_13_b(3) <= not( dcd_011 and combo3_0100_0010 ); + e_13_b(4) <= not( dcd_100 and combo3_1110_1101 ); + e_13_b(5) <= not( dcd_101 and combo3_1010_1100 ); + e_13_b(6) <= not( dcd_110 and combo3_0010_1111 ); + e_13_b(7) <= not( dcd_111 and combo3_0010_1001 ); + + e(13) <= not( e_13_b(0) and + e_13_b(1) and + e_13_b(2) and + e_13_b(3) and + e_13_b(4) and + e_13_b(5) and + e_13_b(6) and + e_13_b(7) ); + + e_14_b(0) <= not( dcd_000 and combo3_0111_1001 ); + e_14_b(1) <= not( dcd_001 and combo3_0001_1000 ); + e_14_b(2) <= not( dcd_010 and combo3_0100_1100 ); + e_14_b(3) <= not( dcd_011 and combo3_1100_1011 ); + e_14_b(4) <= not( dcd_100 and combo3_1111_0010 ); + e_14_b(5) <= not( dcd_101 and combo3_0101_1111 ); + e_14_b(6) <= not( dcd_110 and combo3_0110_1100 ); + e_14_b(7) <= not( dcd_111 and combo3_0001_0010 ); + + e(14) <= not( e_14_b(0) and + e_14_b(1) and + e_14_b(2) and + e_14_b(3) and + e_14_b(4) and + e_14_b(5) and + e_14_b(6) and + e_14_b(7) ); + + e_15_b(0) <= not( dcd_000 and combo3_1001_0000 ); + e_15_b(1) <= not( dcd_001 and combo3_1001_0010 ); + e_15_b(2) <= not( dcd_010 and combo3_1101_1010 ); + e_15_b(3) <= not( dcd_011 and combo3_1001_0111 ); + e_15_b(4) <= not( dcd_100 and combo3_0101_1111 ); + e_15_b(5) <= not( dcd_101 and combo3_1001_0001 ); + e_15_b(6) <= not( dcd_110 and combo3_0011_0101 ); + e_15_b(7) <= not( dcd_111 and combo3_1100_0101 ); + + e(15) <= not( e_15_b(0) and + e_15_b(1) and + e_15_b(2) and + e_15_b(3) and + e_15_b(4) and + e_15_b(5) and + e_15_b(6) and + e_15_b(7) ); + + e_16_b(0) <= not( dcd_000 and combo3_1010_1111 ); + e_16_b(1) <= not( dcd_001 and combo3_0101_1100 ); + e_16_b(2) <= not( dcd_010 and combo3_0100_0000 ); + e_16_b(3) <= not( dcd_011 and combo3_0001_0001 ); + e_16_b(4) <= not( dcd_100 and combo3_0000_1101 ); + e_16_b(5) <= not( dcd_101 and combo3_1100_1111 ); + e_16_b(6) <= not( dcd_110 and combo3_1010_0100 ); + e_16_b(7) <= not( dcd_111 and combo3_0001_1101 ); + + e(16) <= not( e_16_b(0) and + e_16_b(1) and + e_16_b(2) and + e_16_b(3) and + e_16_b(4) and + e_16_b(5) and + e_16_b(6) and + e_16_b(7) ); + + e_17_b(0) <= not( dcd_000 and combo3_1010_0010 ); + e_17_b(1) <= not( dcd_001 and combo3_1111_0010 ); + e_17_b(2) <= not( dcd_010 and combo3_0101_1001 ); + e_17_b(3) <= not( dcd_011 and combo3_1000_0110 ); + e_17_b(4) <= not( dcd_100 and combo3_1110_0001 ); + e_17_b(5) <= not( dcd_101 and combo3_0010_0011 ); + e_17_b(6) <= not( dcd_110 and combo3_1000_1010 ); + e_17_b(7) <= not( dcd_111 and combo3_1001_0100 ); + + e(17) <= not( e_17_b(0) and + e_17_b(1) and + e_17_b(2) and + e_17_b(3) and + e_17_b(4) and + e_17_b(5) and + e_17_b(6) and + e_17_b(7) ); + + e_18_b(0) <= not( dcd_000 and combo3_1101_1100 ); + e_18_b(1) <= not( dcd_001 and combo3_0010_1101 ); + e_18_b(2) <= not( dcd_010 and combo3_1100_1010 ); + e_18_b(3) <= not( dcd_011 and combo3_1010_0001 ); + e_18_b(4) <= not( dcd_100 and combo3_1000_0000 ); + e_18_b(5) <= not( dcd_101 and combo3_1011_0010 ); + e_18_b(6) <= not( dcd_110 and combo3_1110_1010 ); + e_18_b(7) <= not( dcd_111 and combo3_0010_1000 ); + + e(18) <= not( e_18_b(0) and + e_18_b(1) and + e_18_b(2) and + e_18_b(3) and + e_18_b(4) and + e_18_b(5) and + e_18_b(6) and + e_18_b(7) ); + + e_19_b(0) <= not( dcd_000 and tiup ); + e_19_b(1) <= not( dcd_001 and tiup ); + e_19_b(2) <= not( dcd_010 and tiup ); + e_19_b(3) <= not( dcd_011 and tiup ); + e_19_b(4) <= not( dcd_100 and tiup ); + e_19_b(5) <= not( dcd_101 and tiup ); + e_19_b(6) <= not( dcd_110 and tiup ); + e_19_b(7) <= not( dcd_111 and tiup ); + + e(19) <= not( e_19_b(0) and + e_19_b(1) and + e_19_b(2) and + e_19_b(3) and + e_19_b(4) and + e_19_b(5) and + e_19_b(6) and + e_19_b(7) ); + + + + + r_00_b(0) <= not( dcd_000 and tidn ); + r_00_b(1) <= not( dcd_001 and tidn ); + r_00_b(2) <= not( dcd_010 and tidn ); + r_00_b(3) <= not( dcd_011 and tidn ); + r_00_b(4) <= not( dcd_100 and tidn ); + r_00_b(5) <= not( dcd_101 and tidn ); + r_00_b(6) <= not( dcd_110 and tidn ); + r_00_b(7) <= not( dcd_111 and tidn ); + + r( 0) <= not( r_00_b(0) and + r_00_b(1) and + r_00_b(2) and + r_00_b(3) and + r_00_b(4) and + r_00_b(5) and + r_00_b(6) and + r_00_b(7) ); + + r_01_b(0) <= not( dcd_000 and tiup ); + r_01_b(1) <= not( dcd_001 and tiup ); + r_01_b(2) <= not( dcd_010 and combo3_1000_0000 ); + r_01_b(3) <= not( dcd_011 and tidn ); + r_01_b(4) <= not( dcd_100 and tidn ); + r_01_b(5) <= not( dcd_101 and tidn ); + r_01_b(6) <= not( dcd_110 and tidn ); + r_01_b(7) <= not( dcd_111 and tidn ); + + r( 1) <= not( r_01_b(0) and + r_01_b(1) and + r_01_b(2) and + r_01_b(3) and + r_01_b(4) and + r_01_b(5) and + r_01_b(6) and + r_01_b(7) ); + + r_02_b(0) <= not( dcd_000 and tidn ); + r_02_b(1) <= not( dcd_001 and tidn ); + r_02_b(2) <= not( dcd_010 and combo3_0111_1111 ); + r_02_b(3) <= not( dcd_011 and tiup ); + r_02_b(4) <= not( dcd_100 and tiup ); + r_02_b(5) <= not( dcd_101 and tiup ); + r_02_b(6) <= not( dcd_110 and tiup ); + r_02_b(7) <= not( dcd_111 and tiup ); + + r( 2) <= not( r_02_b(0) and + r_02_b(1) and + r_02_b(2) and + r_02_b(3) and + r_02_b(4) and + r_02_b(5) and + r_02_b(6) and + r_02_b(7) ); + + r_03_b(0) <= not( dcd_000 and combo3_1111_1000 ); + r_03_b(1) <= not( dcd_001 and tidn ); + r_03_b(2) <= not( dcd_010 and combo3_0111_1111 ); + r_03_b(3) <= not( dcd_011 and tiup ); + r_03_b(4) <= not( dcd_100 and combo3_1100_0000 ); + r_03_b(5) <= not( dcd_101 and tidn ); + r_03_b(6) <= not( dcd_110 and tidn ); + r_03_b(7) <= not( dcd_111 and tidn ); + + r( 3) <= not( r_03_b(0) and + r_03_b(1) and + r_03_b(2) and + r_03_b(3) and + r_03_b(4) and + r_03_b(5) and + r_03_b(6) and + r_03_b(7) ); + + r_04_b(0) <= not( dcd_000 and combo3_1000_0111 ); + r_04_b(1) <= not( dcd_001 and combo3_1110_0000 ); + r_04_b(2) <= not( dcd_010 and combo3_0111_1111 ); + r_04_b(3) <= not( dcd_011 and tidn ); + r_04_b(4) <= not( dcd_100 and combo3_0011_1111 ); + r_04_b(5) <= not( dcd_101 and combo3_1111_1100 ); + r_04_b(6) <= not( dcd_110 and tidn ); + r_04_b(7) <= not( dcd_111 and tidn ); + + r( 4) <= not( r_04_b(0) and + r_04_b(1) and + r_04_b(2) and + r_04_b(3) and + r_04_b(4) and + r_04_b(5) and + r_04_b(6) and + r_04_b(7) ); + + r_05_b(0) <= not( dcd_000 and combo3_0110_0111 ); + r_05_b(1) <= not( dcd_001 and combo3_0001_1000 ); + r_05_b(2) <= not( dcd_010 and combo3_0111_0000 ); + r_05_b(3) <= not( dcd_011 and combo3_1111_1000 ); + r_05_b(4) <= not( dcd_100 and combo3_0011_1111 ); + r_05_b(5) <= not( dcd_101 and combo3_0000_0011 ); + r_05_b(6) <= not( dcd_110 and combo3_1111_1100 ); + r_05_b(7) <= not( dcd_111 and tidn ); + + r( 5) <= not( r_05_b(0) and + r_05_b(1) and + r_05_b(2) and + r_05_b(3) and + r_05_b(4) and + r_05_b(5) and + r_05_b(6) and + r_05_b(7) ); + + r_06_b(0) <= not( dcd_000 and combo3_0101_0110 ); + r_06_b(1) <= not( dcd_001 and combo3_1001_0110 ); + r_06_b(2) <= not( dcd_010 and combo3_0100_1100 ); + r_06_b(3) <= not( dcd_011 and combo3_1100_0110 ); + r_06_b(4) <= not( dcd_100 and combo3_0011_0000 ); + r_06_b(5) <= not( dcd_101 and combo3_1110_0011 ); + r_06_b(6) <= not( dcd_110 and combo3_1100_0011 ); + r_06_b(7) <= not( dcd_111 and combo3_1110_0000 ); + + r( 6) <= not( r_06_b(0) and + r_06_b(1) and + r_06_b(2) and + r_06_b(3) and + r_06_b(4) and + r_06_b(5) and + r_06_b(6) and + r_06_b(7) ); + + r_07_b(0) <= not( dcd_000 and combo3_1111_1100 ); + r_07_b(1) <= not( dcd_001 and combo3_1100_1101 ); + r_07_b(2) <= not( dcd_010 and combo3_0010_1010 ); + r_07_b(3) <= not( dcd_011 and combo3_1010_0101 ); + r_07_b(4) <= not( dcd_100 and combo3_0010_1100 ); + r_07_b(5) <= not( dcd_101 and combo3_1001_1011 ); + r_07_b(6) <= not( dcd_110 and combo3_0011_0011 ); + r_07_b(7) <= not( dcd_111 and combo3_1001_1000 ); + + r( 7) <= not( r_07_b(0) and + r_07_b(1) and + r_07_b(2) and + r_07_b(3) and + r_07_b(4) and + r_07_b(5) and + r_07_b(6) and + r_07_b(7) ); + + r_08_b(0) <= not( dcd_000 and combo3_0001_1101 ); + r_08_b(1) <= not( dcd_001 and combo3_0101_0110 ); + r_08_b(2) <= not( dcd_010 and combo3_0111_1111 ); + r_08_b(3) <= not( dcd_011 and combo3_1111_0001 ); + r_08_b(4) <= not( dcd_100 and combo3_1001_1010 ); + r_08_b(5) <= not( dcd_101 and combo3_0101_0010 ); + r_08_b(6) <= not( dcd_110 and combo3_1010_1010 ); + r_08_b(7) <= not( dcd_111 and combo3_0101_0110 ); + + r( 8) <= not( r_08_b(0) and + r_08_b(1) and + r_08_b(2) and + r_08_b(3) and + r_08_b(4) and + r_08_b(5) and + r_08_b(6) and + r_08_b(7) ); + + r_09_b(0) <= not( dcd_000 and combo3_1110_0110 ); + r_09_b(1) <= not( dcd_001 and combo3_0000_1101 ); + r_09_b(2) <= not( dcd_010 and combo3_0110_0000 ); + r_09_b(3) <= not( dcd_011 and combo3_0011_0110 ); + r_09_b(4) <= not( dcd_100 and combo3_1010_1100 ); + r_09_b(5) <= not( dcd_101 and combo3_1100_0111 ); + r_09_b(6) <= not( dcd_110 and tiup ); + r_09_b(7) <= not( dcd_111 and combo3_0001_1100 ); + + r( 9) <= not( r_09_b(0) and + r_09_b(1) and + r_09_b(2) and + r_09_b(3) and + r_09_b(4) and + r_09_b(5) and + r_09_b(6) and + r_09_b(7) ); + + r_10_b(0) <= not( dcd_000 and combo3_1110_1101 ); + r_10_b(1) <= not( dcd_001 and combo3_0001_0111 ); + r_10_b(2) <= not( dcd_010 and combo3_1101_1000 ); + r_10_b(3) <= not( dcd_011 and combo3_1101_0011 ); + r_10_b(4) <= not( dcd_100 and combo3_1111_1010 ); + r_10_b(5) <= not( dcd_101 and combo3_1010_0110 ); + r_10_b(6) <= not( dcd_110 and combo3_0000_0111 ); + r_10_b(7) <= not( dcd_111 and combo3_0010_0101 ); + + r(10) <= not( r_10_b(0) and + r_10_b(1) and + r_10_b(2) and + r_10_b(3) and + r_10_b(4) and + r_10_b(5) and + r_10_b(6) and + r_10_b(7) ); + + r_11_b(0) <= not( dcd_000 and combo3_1011_1100 ); + r_11_b(1) <= not( dcd_001 and combo3_1010_0000 ); + r_11_b(2) <= not( dcd_010 and combo3_0111_0111 ); + r_11_b(3) <= not( dcd_011 and combo3_0111_1010 ); + r_11_b(4) <= not( dcd_100 and combo3_0001_1100 ); + r_11_b(5) <= not( dcd_101 and combo3_0001_0101 ); + r_11_b(6) <= not( dcd_110 and combo3_1111_1001 ); + r_11_b(7) <= not( dcd_111 and combo3_0100_1111 ); + + r(11) <= not( r_11_b(0) and + r_11_b(1) and + r_11_b(2) and + r_11_b(3) and + r_11_b(4) and + r_11_b(5) and + r_11_b(6) and + r_11_b(7) ); + + r_12_b(0) <= not( dcd_000 and combo3_0100_1110 ); + r_12_b(1) <= not( dcd_001 and combo3_0100_0100 ); + r_12_b(2) <= not( dcd_010 and combo3_1101_1111 ); + r_12_b(3) <= not( dcd_011 and combo3_1100_0000 ); + r_12_b(4) <= not( dcd_100 and combo3_0000_1010 ); + r_12_b(5) <= not( dcd_101 and combo3_0010_0001 ); + r_12_b(6) <= not( dcd_110 and combo3_0000_1011 ); + r_12_b(7) <= not( dcd_111 and combo3_1110_1000 ); + + r(12) <= not( r_12_b(0) and + r_12_b(1) and + r_12_b(2) and + r_12_b(3) and + r_12_b(4) and + r_12_b(5) and + r_12_b(6) and + r_12_b(7) ); + + r_13_b(0) <= not( dcd_000 and combo3_1010_1001 ); + r_13_b(1) <= not( dcd_001 and combo3_0001_0100 ); + r_13_b(2) <= not( dcd_010 and combo3_0111_0101 ); + r_13_b(3) <= not( dcd_011 and combo3_0000_1001 ); + r_13_b(4) <= not( dcd_100 and combo3_0010_1000 ); + r_13_b(5) <= not( dcd_101 and combo3_0000_0011 ); + r_13_b(6) <= not( dcd_110 and combo3_1001_0010 ); + r_13_b(7) <= not( dcd_111 and combo3_0010_0100 ); + + r(13) <= not( r_13_b(0) and + r_13_b(1) and + r_13_b(2) and + r_13_b(3) and + r_13_b(4) and + r_13_b(5) and + r_13_b(6) and + r_13_b(7) ); + + r_14_b(0) <= not( dcd_000 and tidn ); + r_14_b(1) <= not( dcd_001 and tidn ); + r_14_b(2) <= not( dcd_010 and tidn ); + r_14_b(3) <= not( dcd_011 and tidn ); + r_14_b(4) <= not( dcd_100 and tidn ); + r_14_b(5) <= not( dcd_101 and tidn ); + r_14_b(6) <= not( dcd_110 and tidn ); + r_14_b(7) <= not( dcd_111 and tidn ); + + r(14) <= not( r_14_b(0) and + r_14_b(1) and + r_14_b(2) and + r_14_b(3) and + r_14_b(4) and + r_14_b(5) and + r_14_b(6) and + r_14_b(7) ); + + + + + + est(1 to 20) <= e(0 to 19); + rng(6 to 20) <= r(0 to 14); + + +end; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_tblsqo.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_tblsqo.vhdl new file mode 100644 index 0000000..52a1887 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_tblsqo.vhdl @@ -0,0 +1,1154 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; + use ieee.std_logic_1164.all ; +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + + + + +entity fuq_tblsqo is +generic( expand_type : integer := 2 ); +port( + f :in std_ulogic_vector(1 to 6); + est :out std_ulogic_vector(1 to 20); + rng :out std_ulogic_vector(6 to 20) + +); + + + +end fuq_tblsqo; + + +architecture fuq_tblsqo of fuq_tblsqo is + + constant tiup :std_ulogic := '1'; + constant tidn :std_ulogic := '0'; + + + signal dcd_00x :std_ulogic; + signal dcd_01x :std_ulogic; + signal dcd_10x :std_ulogic; + signal dcd_11x :std_ulogic; + signal dcd_000 :std_ulogic; + signal dcd_001 :std_ulogic; + signal dcd_010 :std_ulogic; + signal dcd_011 :std_ulogic; + signal dcd_100 :std_ulogic; + signal dcd_101 :std_ulogic; + signal dcd_110 :std_ulogic; + signal dcd_111 :std_ulogic; + signal combo2_1000 :std_ulogic; + signal combo2_0100 :std_ulogic; + signal combo2_1100 :std_ulogic; + signal combo2_0010 :std_ulogic; + signal combo2_1010 :std_ulogic; + signal combo2_0110 :std_ulogic; + signal combo2_1110 :std_ulogic; + signal combo2_0001 :std_ulogic; + signal combo2_1001 :std_ulogic; + signal combo2_0101 :std_ulogic; + signal combo2_1101 :std_ulogic; + signal combo2_0011 :std_ulogic; + signal combo2_1011 :std_ulogic; + signal combo2_0111 :std_ulogic; + signal combo2_1000_xxxx_b :std_ulogic; + signal combo2_0100_xxxx_b :std_ulogic; + signal combo2_1100_xxxx_b :std_ulogic; + signal combo2_0010_xxxx_b :std_ulogic; + signal combo2_1010_xxxx_b :std_ulogic; + signal combo2_0110_xxxx_b :std_ulogic; + signal combo2_1110_xxxx_b :std_ulogic; + signal combo2_0001_xxxx_b :std_ulogic; + signal combo2_1001_xxxx_b :std_ulogic; + signal combo2_0101_xxxx_b :std_ulogic; + signal combo2_1101_xxxx_b :std_ulogic; + signal combo2_0011_xxxx_b :std_ulogic; + signal combo2_1011_xxxx_b :std_ulogic; + signal combo2_0111_xxxx_b :std_ulogic; + signal combo2_xxxx_1000_b :std_ulogic; + signal combo2_xxxx_0100_b :std_ulogic; + signal combo2_xxxx_1100_b :std_ulogic; + signal combo2_xxxx_0010_b :std_ulogic; + signal combo2_xxxx_1010_b :std_ulogic; + signal combo2_xxxx_0110_b :std_ulogic; + signal combo2_xxxx_1110_b :std_ulogic; + signal combo2_xxxx_0001_b :std_ulogic; + signal combo2_xxxx_1001_b :std_ulogic; + signal combo2_xxxx_0101_b :std_ulogic; + signal combo2_xxxx_1101_b :std_ulogic; + signal combo2_xxxx_0011_b :std_ulogic; + signal combo2_xxxx_1011_b :std_ulogic; + signal combo2_xxxx_0111_b :std_ulogic; + signal combo3_0000_0001 :std_ulogic; + signal combo3_0000_0011 :std_ulogic; + signal combo3_0000_0100 :std_ulogic; + signal combo3_0000_1011 :std_ulogic; + signal combo3_0000_1100 :std_ulogic; + signal combo3_0000_1101 :std_ulogic; + signal combo3_0000_1111 :std_ulogic; + signal combo3_0001_0001 :std_ulogic; + signal combo3_0001_0010 :std_ulogic; + signal combo3_0001_0100 :std_ulogic; + signal combo3_0001_0101 :std_ulogic; + signal combo3_0001_0111 :std_ulogic; + signal combo3_0001_1000 :std_ulogic; + signal combo3_0001_1110 :std_ulogic; + signal combo3_0001_1111 :std_ulogic; + signal combo3_0010_0001 :std_ulogic; + signal combo3_0010_0010 :std_ulogic; + signal combo3_0010_0011 :std_ulogic; + signal combo3_0010_0100 :std_ulogic; + signal combo3_0010_0110 :std_ulogic; + signal combo3_0010_1001 :std_ulogic; + signal combo3_0010_1101 :std_ulogic; + signal combo3_0010_1110 :std_ulogic; + signal combo3_0011_0000 :std_ulogic; + signal combo3_0011_0001 :std_ulogic; + signal combo3_0011_0011 :std_ulogic; + signal combo3_0011_0100 :std_ulogic; + signal combo3_0011_0101 :std_ulogic; + signal combo3_0011_1000 :std_ulogic; + signal combo3_0011_1001 :std_ulogic; + signal combo3_0011_1010 :std_ulogic; + signal combo3_0011_1100 :std_ulogic; + signal combo3_0011_1110 :std_ulogic; + signal combo3_0011_1111 :std_ulogic; + signal combo3_0100_0000 :std_ulogic; + signal combo3_0100_0101 :std_ulogic; + signal combo3_0100_0110 :std_ulogic; + signal combo3_0100_1000 :std_ulogic; + signal combo3_0100_1001 :std_ulogic; + signal combo3_0100_1010 :std_ulogic; + signal combo3_0100_1100 :std_ulogic; + signal combo3_0100_1101 :std_ulogic; + signal combo3_0101_0000 :std_ulogic; + signal combo3_0101_0001 :std_ulogic; + signal combo3_0101_0011 :std_ulogic; + signal combo3_0101_0101 :std_ulogic; + signal combo3_0101_0110 :std_ulogic; + signal combo3_0101_1001 :std_ulogic; + signal combo3_0101_1010 :std_ulogic; + signal combo3_0101_1110 :std_ulogic; + signal combo3_0101_1111 :std_ulogic; + signal combo3_0110_0011 :std_ulogic; + signal combo3_0110_0110 :std_ulogic; + signal combo3_0110_0111 :std_ulogic; + signal combo3_0110_1001 :std_ulogic; + signal combo3_0110_1010 :std_ulogic; + signal combo3_0110_1011 :std_ulogic; + signal combo3_0110_1100 :std_ulogic; + signal combo3_0110_1101 :std_ulogic; + signal combo3_0110_1110 :std_ulogic; + signal combo3_0110_1111 :std_ulogic; + signal combo3_0111_0000 :std_ulogic; + signal combo3_0111_0010 :std_ulogic; + signal combo3_0111_0011 :std_ulogic; + signal combo3_0111_0110 :std_ulogic; + signal combo3_0111_1000 :std_ulogic; + signal combo3_0111_1001 :std_ulogic; + signal combo3_0111_1100 :std_ulogic; + signal combo3_0111_1110 :std_ulogic; + signal combo3_0111_1111 :std_ulogic; + signal combo3_1000_0000 :std_ulogic; + signal combo3_1000_0001 :std_ulogic; + signal combo3_1000_0011 :std_ulogic; + signal combo3_1000_0110 :std_ulogic; + signal combo3_1000_1000 :std_ulogic; + signal combo3_1000_1010 :std_ulogic; + signal combo3_1000_1101 :std_ulogic; + signal combo3_1000_1110 :std_ulogic; + signal combo3_1000_1111 :std_ulogic; + signal combo3_1001_0000 :std_ulogic; + signal combo3_1001_0010 :std_ulogic; + signal combo3_1001_0011 :std_ulogic; + signal combo3_1001_0100 :std_ulogic; + signal combo3_1001_0111 :std_ulogic; + signal combo3_1001_1000 :std_ulogic; + signal combo3_1001_1001 :std_ulogic; + signal combo3_1001_1010 :std_ulogic; + signal combo3_1001_1100 :std_ulogic; + signal combo3_1001_1101 :std_ulogic; + signal combo3_1001_1110 :std_ulogic; + signal combo3_1001_1111 :std_ulogic; + signal combo3_1010_0010 :std_ulogic; + signal combo3_1010_0100 :std_ulogic; + signal combo3_1010_0101 :std_ulogic; + signal combo3_1010_0110 :std_ulogic; + signal combo3_1010_0111 :std_ulogic; + signal combo3_1010_1010 :std_ulogic; + signal combo3_1010_1100 :std_ulogic; + signal combo3_1010_1101 :std_ulogic; + signal combo3_1010_1110 :std_ulogic; + signal combo3_1011_0011 :std_ulogic; + signal combo3_1011_0110 :std_ulogic; + signal combo3_1011_0111 :std_ulogic; + signal combo3_1011_1000 :std_ulogic; + signal combo3_1011_1001 :std_ulogic; + signal combo3_1011_1010 :std_ulogic; + signal combo3_1011_1011 :std_ulogic; + signal combo3_1011_1110 :std_ulogic; + signal combo3_1100_0000 :std_ulogic; + signal combo3_1100_0001 :std_ulogic; + signal combo3_1100_0011 :std_ulogic; + signal combo3_1100_0110 :std_ulogic; + signal combo3_1100_0111 :std_ulogic; + signal combo3_1100_1010 :std_ulogic; + signal combo3_1100_1100 :std_ulogic; + signal combo3_1100_1110 :std_ulogic; + signal combo3_1101_0000 :std_ulogic; + signal combo3_1101_0011 :std_ulogic; + signal combo3_1101_0101 :std_ulogic; + signal combo3_1101_1000 :std_ulogic; + signal combo3_1101_1010 :std_ulogic; + signal combo3_1101_1011 :std_ulogic; + signal combo3_1101_1101 :std_ulogic; + signal combo3_1110_0000 :std_ulogic; + signal combo3_1110_0001 :std_ulogic; + signal combo3_1110_0010 :std_ulogic; + signal combo3_1110_0011 :std_ulogic; + signal combo3_1110_0100 :std_ulogic; + signal combo3_1110_0101 :std_ulogic; + signal combo3_1110_0110 :std_ulogic; + signal combo3_1110_1010 :std_ulogic; + signal combo3_1110_1011 :std_ulogic; + signal combo3_1111_0000 :std_ulogic; + signal combo3_1111_0011 :std_ulogic; + signal combo3_1111_0101 :std_ulogic; + signal combo3_1111_1000 :std_ulogic; + signal combo3_1111_1001 :std_ulogic; + signal combo3_1111_1011 :std_ulogic; + signal combo3_1111_1100 :std_ulogic; + signal combo3_1111_1110 :std_ulogic; + signal e_00_b :std_ulogic_vector(0 to 7); + signal e_01_b :std_ulogic_vector(0 to 7); + signal e_02_b :std_ulogic_vector(0 to 7); + signal e_03_b :std_ulogic_vector(0 to 7); + signal e_04_b :std_ulogic_vector(0 to 7); + signal e_05_b :std_ulogic_vector(0 to 7); + signal e_06_b :std_ulogic_vector(0 to 7); + signal e_07_b :std_ulogic_vector(0 to 7); + signal e_08_b :std_ulogic_vector(0 to 7); + signal e_09_b :std_ulogic_vector(0 to 7); + signal e_10_b :std_ulogic_vector(0 to 7); + signal e_11_b :std_ulogic_vector(0 to 7); + signal e_12_b :std_ulogic_vector(0 to 7); + signal e_13_b :std_ulogic_vector(0 to 7); + signal e_14_b :std_ulogic_vector(0 to 7); + signal e_15_b :std_ulogic_vector(0 to 7); + signal e_16_b :std_ulogic_vector(0 to 7); + signal e_17_b :std_ulogic_vector(0 to 7); + signal e_18_b :std_ulogic_vector(0 to 7); + signal e_19_b :std_ulogic_vector(0 to 7); + signal e :std_ulogic_vector(0 to 19); + signal r_00_b :std_ulogic_vector(0 to 7); + signal r_01_b :std_ulogic_vector(0 to 7); + signal r_02_b :std_ulogic_vector(0 to 7); + signal r_03_b :std_ulogic_vector(0 to 7); + signal r_04_b :std_ulogic_vector(0 to 7); + signal r_05_b :std_ulogic_vector(0 to 7); + signal r_06_b :std_ulogic_vector(0 to 7); + signal r_07_b :std_ulogic_vector(0 to 7); + signal r_08_b :std_ulogic_vector(0 to 7); + signal r_09_b :std_ulogic_vector(0 to 7); + signal r_10_b :std_ulogic_vector(0 to 7); + signal r_11_b :std_ulogic_vector(0 to 7); + signal r_12_b :std_ulogic_vector(0 to 7); + signal r_13_b :std_ulogic_vector(0 to 7); + signal r_14_b :std_ulogic_vector(0 to 7); + signal r :std_ulogic_vector(0 to 14); + + + +begin + + + + + + dcd_00x <= not f(1) and not f(2) ; + dcd_01x <= not f(1) and f(2) ; + dcd_10x <= f(1) and not f(2) ; + dcd_11x <= f(1) and f(2) ; + + dcd_000 <= not f(3) and dcd_00x ; + dcd_001 <= f(3) and dcd_00x ; + dcd_010 <= not f(3) and dcd_01x ; + dcd_011 <= f(3) and dcd_01x ; + dcd_100 <= not f(3) and dcd_10x ; + dcd_101 <= f(3) and dcd_10x ; + dcd_110 <= not f(3) and dcd_11x ; + dcd_111 <= f(3) and dcd_11x ; + + + + + + combo2_1000 <= not f(5) and not f(6) ; + combo2_0100 <= not f(5) and f(6) ; + combo2_1100 <= not f(5) ; + combo2_0010 <= f(5) and not f(6) ; + combo2_1010 <= not f(6) ; + combo2_0110 <= f(5) xor f(6) ; + combo2_1110 <= not( f(5) and f(6) ) ; + combo2_0001 <= f(5) and f(6) ; + combo2_1001 <= not( f(5) xor f(6) ) ; + combo2_0101 <= f(6) ; + combo2_1101 <= not( f(5) and not f(6) ) ; + combo2_0011 <= f(5) ; + combo2_1011 <= not( not f(5) and f(6) ) ; + combo2_0111 <= not( not f(5) and not f(6) ) ; + + + + combo2_1000_xxxx_b <= not( not f(4) and combo2_1000 ); + combo2_0100_xxxx_b <= not( not f(4) and combo2_0100 ); + combo2_1100_xxxx_b <= not( not f(4) and combo2_1100 ); + combo2_0010_xxxx_b <= not( not f(4) and combo2_0010 ); + combo2_1010_xxxx_b <= not( not f(4) and combo2_1010 ); + combo2_0110_xxxx_b <= not( not f(4) and combo2_0110 ); + combo2_1110_xxxx_b <= not( not f(4) and combo2_1110 ); + combo2_0001_xxxx_b <= not( not f(4) and combo2_0001 ); + combo2_1001_xxxx_b <= not( not f(4) and combo2_1001 ); + combo2_0101_xxxx_b <= not( not f(4) and combo2_0101 ); + combo2_1101_xxxx_b <= not( not f(4) and combo2_1101 ); + combo2_0011_xxxx_b <= not( not f(4) and combo2_0011 ); + combo2_1011_xxxx_b <= not( not f(4) and combo2_1011 ); + combo2_0111_xxxx_b <= not( not f(4) and combo2_0111 ); + + + combo2_xxxx_1000_b <= not( f(4) and combo2_1000 ); + combo2_xxxx_0100_b <= not( f(4) and combo2_0100 ); + combo2_xxxx_1100_b <= not( f(4) and combo2_1100 ); + combo2_xxxx_0010_b <= not( f(4) and combo2_0010 ); + combo2_xxxx_1010_b <= not( f(4) and combo2_1010 ); + combo2_xxxx_0110_b <= not( f(4) and combo2_0110 ); + combo2_xxxx_1110_b <= not( f(4) and combo2_1110 ); + combo2_xxxx_0001_b <= not( f(4) and combo2_0001 ); + combo2_xxxx_1001_b <= not( f(4) and combo2_1001 ); + combo2_xxxx_0101_b <= not( f(4) and combo2_0101 ); + combo2_xxxx_1101_b <= not( f(4) and combo2_1101 ); + combo2_xxxx_0011_b <= not( f(4) and combo2_0011 ); + combo2_xxxx_1011_b <= not( f(4) and combo2_1011 ); + combo2_xxxx_0111_b <= not( f(4) and combo2_0111 ); + + + combo3_0000_0001 <= not( combo2_xxxx_0001_b ); + combo3_0000_0011 <= not( combo2_xxxx_0011_b ); + combo3_0000_0100 <= not( combo2_xxxx_0100_b ); + combo3_0000_1011 <= not( combo2_xxxx_1011_b ); + combo3_0000_1100 <= not( combo2_xxxx_1100_b ); + combo3_0000_1101 <= not( combo2_xxxx_1101_b ); + combo3_0000_1111 <= not( not f(4) ); + combo3_0001_0001 <= not( not combo2_0001 ); + combo3_0001_0010 <= not( combo2_0001_xxxx_b and combo2_xxxx_0010_b ); + combo3_0001_0100 <= not( combo2_0001_xxxx_b and combo2_xxxx_0100_b ); + combo3_0001_0101 <= not( combo2_0001_xxxx_b and combo2_xxxx_0101_b ); + combo3_0001_0111 <= not( combo2_0001_xxxx_b and combo2_xxxx_0111_b ); + combo3_0001_1000 <= not( combo2_0001_xxxx_b and combo2_xxxx_1000_b ); + combo3_0001_1110 <= not( combo2_0001_xxxx_b and combo2_xxxx_1110_b ); + combo3_0001_1111 <= not( combo2_0001_xxxx_b and not f(4) ); + combo3_0010_0001 <= not( combo2_0010_xxxx_b and combo2_xxxx_0001_b ); + combo3_0010_0010 <= not( not combo2_0010 ); + combo3_0010_0011 <= not( combo2_0010_xxxx_b and combo2_xxxx_0011_b ); + combo3_0010_0100 <= not( combo2_0010_xxxx_b and combo2_xxxx_0100_b ); + combo3_0010_0110 <= not( combo2_0010_xxxx_b and combo2_xxxx_0110_b ); + combo3_0010_1001 <= not( combo2_0010_xxxx_b and combo2_xxxx_1001_b ); + combo3_0010_1101 <= not( combo2_0010_xxxx_b and combo2_xxxx_1101_b ); + combo3_0010_1110 <= not( combo2_0010_xxxx_b and combo2_xxxx_1110_b ); + combo3_0011_0000 <= not( combo2_0011_xxxx_b ); + combo3_0011_0001 <= not( combo2_0011_xxxx_b and combo2_xxxx_0001_b ); + combo3_0011_0011 <= not( not combo2_0011 ); + combo3_0011_0100 <= not( combo2_0011_xxxx_b and combo2_xxxx_0100_b ); + combo3_0011_0101 <= not( combo2_0011_xxxx_b and combo2_xxxx_0101_b ); + combo3_0011_1000 <= not( combo2_0011_xxxx_b and combo2_xxxx_1000_b ); + combo3_0011_1001 <= not( combo2_0011_xxxx_b and combo2_xxxx_1001_b ); + combo3_0011_1010 <= not( combo2_0011_xxxx_b and combo2_xxxx_1010_b ); + combo3_0011_1100 <= not( combo2_0011_xxxx_b and combo2_xxxx_1100_b ); + combo3_0011_1110 <= not( combo2_0011_xxxx_b and combo2_xxxx_1110_b ); + combo3_0011_1111 <= not( combo2_0011_xxxx_b and not f(4) ); + combo3_0100_0000 <= not( combo2_0100_xxxx_b ); + combo3_0100_0101 <= not( combo2_0100_xxxx_b and combo2_xxxx_0101_b ); + combo3_0100_0110 <= not( combo2_0100_xxxx_b and combo2_xxxx_0110_b ); + combo3_0100_1000 <= not( combo2_0100_xxxx_b and combo2_xxxx_1000_b ); + combo3_0100_1001 <= not( combo2_0100_xxxx_b and combo2_xxxx_1001_b ); + combo3_0100_1010 <= not( combo2_0100_xxxx_b and combo2_xxxx_1010_b ); + combo3_0100_1100 <= not( combo2_0100_xxxx_b and combo2_xxxx_1100_b ); + combo3_0100_1101 <= not( combo2_0100_xxxx_b and combo2_xxxx_1101_b ); + combo3_0101_0000 <= not( combo2_0101_xxxx_b ); + combo3_0101_0001 <= not( combo2_0101_xxxx_b and combo2_xxxx_0001_b ); + combo3_0101_0011 <= not( combo2_0101_xxxx_b and combo2_xxxx_0011_b ); + combo3_0101_0101 <= not( not combo2_0101 ); + combo3_0101_0110 <= not( combo2_0101_xxxx_b and combo2_xxxx_0110_b ); + combo3_0101_1001 <= not( combo2_0101_xxxx_b and combo2_xxxx_1001_b ); + combo3_0101_1010 <= not( combo2_0101_xxxx_b and combo2_xxxx_1010_b ); + combo3_0101_1110 <= not( combo2_0101_xxxx_b and combo2_xxxx_1110_b ); + combo3_0101_1111 <= not( combo2_0101_xxxx_b and not f(4) ); + combo3_0110_0011 <= not( combo2_0110_xxxx_b and combo2_xxxx_0011_b ); + combo3_0110_0110 <= not( not combo2_0110 ); + combo3_0110_0111 <= not( combo2_0110_xxxx_b and combo2_xxxx_0111_b ); + combo3_0110_1001 <= not( combo2_0110_xxxx_b and combo2_xxxx_1001_b ); + combo3_0110_1010 <= not( combo2_0110_xxxx_b and combo2_xxxx_1010_b ); + combo3_0110_1011 <= not( combo2_0110_xxxx_b and combo2_xxxx_1011_b ); + combo3_0110_1100 <= not( combo2_0110_xxxx_b and combo2_xxxx_1100_b ); + combo3_0110_1101 <= not( combo2_0110_xxxx_b and combo2_xxxx_1101_b ); + combo3_0110_1110 <= not( combo2_0110_xxxx_b and combo2_xxxx_1110_b ); + combo3_0110_1111 <= not( combo2_0110_xxxx_b and not f(4) ); + combo3_0111_0000 <= not( combo2_0111_xxxx_b ); + combo3_0111_0010 <= not( combo2_0111_xxxx_b and combo2_xxxx_0010_b ); + combo3_0111_0011 <= not( combo2_0111_xxxx_b and combo2_xxxx_0011_b ); + combo3_0111_0110 <= not( combo2_0111_xxxx_b and combo2_xxxx_0110_b ); + combo3_0111_1000 <= not( combo2_0111_xxxx_b and combo2_xxxx_1000_b ); + combo3_0111_1001 <= not( combo2_0111_xxxx_b and combo2_xxxx_1001_b ); + combo3_0111_1100 <= not( combo2_0111_xxxx_b and combo2_xxxx_1100_b ); + combo3_0111_1110 <= not( combo2_0111_xxxx_b and combo2_xxxx_1110_b ); + combo3_0111_1111 <= not( combo2_0111_xxxx_b and not f(4) ); + combo3_1000_0000 <= not( combo2_1000_xxxx_b ); + combo3_1000_0001 <= not( combo2_1000_xxxx_b and combo2_xxxx_0001_b ); + combo3_1000_0011 <= not( combo2_1000_xxxx_b and combo2_xxxx_0011_b ); + combo3_1000_0110 <= not( combo2_1000_xxxx_b and combo2_xxxx_0110_b ); + combo3_1000_1000 <= not( not combo2_1000 ); + combo3_1000_1010 <= not( combo2_1000_xxxx_b and combo2_xxxx_1010_b ); + combo3_1000_1101 <= not( combo2_1000_xxxx_b and combo2_xxxx_1101_b ); + combo3_1000_1110 <= not( combo2_1000_xxxx_b and combo2_xxxx_1110_b ); + combo3_1000_1111 <= not( combo2_1000_xxxx_b and not f(4) ); + combo3_1001_0000 <= not( combo2_1001_xxxx_b ); + combo3_1001_0010 <= not( combo2_1001_xxxx_b and combo2_xxxx_0010_b ); + combo3_1001_0011 <= not( combo2_1001_xxxx_b and combo2_xxxx_0011_b ); + combo3_1001_0100 <= not( combo2_1001_xxxx_b and combo2_xxxx_0100_b ); + combo3_1001_0111 <= not( combo2_1001_xxxx_b and combo2_xxxx_0111_b ); + combo3_1001_1000 <= not( combo2_1001_xxxx_b and combo2_xxxx_1000_b ); + combo3_1001_1001 <= not( not combo2_1001 ); + combo3_1001_1010 <= not( combo2_1001_xxxx_b and combo2_xxxx_1010_b ); + combo3_1001_1100 <= not( combo2_1001_xxxx_b and combo2_xxxx_1100_b ); + combo3_1001_1101 <= not( combo2_1001_xxxx_b and combo2_xxxx_1101_b ); + combo3_1001_1110 <= not( combo2_1001_xxxx_b and combo2_xxxx_1110_b ); + combo3_1001_1111 <= not( combo2_1001_xxxx_b and not f(4) ); + combo3_1010_0010 <= not( combo2_1010_xxxx_b and combo2_xxxx_0010_b ); + combo3_1010_0100 <= not( combo2_1010_xxxx_b and combo2_xxxx_0100_b ); + combo3_1010_0101 <= not( combo2_1010_xxxx_b and combo2_xxxx_0101_b ); + combo3_1010_0110 <= not( combo2_1010_xxxx_b and combo2_xxxx_0110_b ); + combo3_1010_0111 <= not( combo2_1010_xxxx_b and combo2_xxxx_0111_b ); + combo3_1010_1010 <= not( not combo2_1010 ); + combo3_1010_1100 <= not( combo2_1010_xxxx_b and combo2_xxxx_1100_b ); + combo3_1010_1101 <= not( combo2_1010_xxxx_b and combo2_xxxx_1101_b ); + combo3_1010_1110 <= not( combo2_1010_xxxx_b and combo2_xxxx_1110_b ); + combo3_1011_0011 <= not( combo2_1011_xxxx_b and combo2_xxxx_0011_b ); + combo3_1011_0110 <= not( combo2_1011_xxxx_b and combo2_xxxx_0110_b ); + combo3_1011_0111 <= not( combo2_1011_xxxx_b and combo2_xxxx_0111_b ); + combo3_1011_1000 <= not( combo2_1011_xxxx_b and combo2_xxxx_1000_b ); + combo3_1011_1001 <= not( combo2_1011_xxxx_b and combo2_xxxx_1001_b ); + combo3_1011_1010 <= not( combo2_1011_xxxx_b and combo2_xxxx_1010_b ); + combo3_1011_1011 <= not( not combo2_1011 ); + combo3_1011_1110 <= not( combo2_1011_xxxx_b and combo2_xxxx_1110_b ); + combo3_1100_0000 <= not( combo2_1100_xxxx_b ); + combo3_1100_0001 <= not( combo2_1100_xxxx_b and combo2_xxxx_0001_b ); + combo3_1100_0011 <= not( combo2_1100_xxxx_b and combo2_xxxx_0011_b ); + combo3_1100_0110 <= not( combo2_1100_xxxx_b and combo2_xxxx_0110_b ); + combo3_1100_0111 <= not( combo2_1100_xxxx_b and combo2_xxxx_0111_b ); + combo3_1100_1010 <= not( combo2_1100_xxxx_b and combo2_xxxx_1010_b ); + combo3_1100_1100 <= not( not combo2_1100 ); + combo3_1100_1110 <= not( combo2_1100_xxxx_b and combo2_xxxx_1110_b ); + combo3_1101_0000 <= not( combo2_1101_xxxx_b ); + combo3_1101_0011 <= not( combo2_1101_xxxx_b and combo2_xxxx_0011_b ); + combo3_1101_0101 <= not( combo2_1101_xxxx_b and combo2_xxxx_0101_b ); + combo3_1101_1000 <= not( combo2_1101_xxxx_b and combo2_xxxx_1000_b ); + combo3_1101_1010 <= not( combo2_1101_xxxx_b and combo2_xxxx_1010_b ); + combo3_1101_1011 <= not( combo2_1101_xxxx_b and combo2_xxxx_1011_b ); + combo3_1101_1101 <= not( not combo2_1101 ); + combo3_1110_0000 <= not( combo2_1110_xxxx_b ); + combo3_1110_0001 <= not( combo2_1110_xxxx_b and combo2_xxxx_0001_b ); + combo3_1110_0010 <= not( combo2_1110_xxxx_b and combo2_xxxx_0010_b ); + combo3_1110_0011 <= not( combo2_1110_xxxx_b and combo2_xxxx_0011_b ); + combo3_1110_0100 <= not( combo2_1110_xxxx_b and combo2_xxxx_0100_b ); + combo3_1110_0101 <= not( combo2_1110_xxxx_b and combo2_xxxx_0101_b ); + combo3_1110_0110 <= not( combo2_1110_xxxx_b and combo2_xxxx_0110_b ); + combo3_1110_1010 <= not( combo2_1110_xxxx_b and combo2_xxxx_1010_b ); + combo3_1110_1011 <= not( combo2_1110_xxxx_b and combo2_xxxx_1011_b ); + combo3_1111_0000 <= not( f(4) ); + combo3_1111_0011 <= not( f(4) and combo2_xxxx_0011_b ); + combo3_1111_0101 <= not( f(4) and combo2_xxxx_0101_b ); + combo3_1111_1000 <= not( f(4) and combo2_xxxx_1000_b ); + combo3_1111_1001 <= not( f(4) and combo2_xxxx_1001_b ); + combo3_1111_1011 <= not( f(4) and combo2_xxxx_1011_b ); + combo3_1111_1100 <= not( f(4) and combo2_xxxx_1100_b ); + combo3_1111_1110 <= not( f(4) and combo2_xxxx_1110_b ); + + + + e_00_b(0) <= not( dcd_000 and tiup ); + e_00_b(1) <= not( dcd_001 and tiup ); + e_00_b(2) <= not( dcd_010 and tiup ); + e_00_b(3) <= not( dcd_011 and tiup ); + e_00_b(4) <= not( dcd_100 and tiup ); + e_00_b(5) <= not( dcd_101 and tiup ); + e_00_b(6) <= not( dcd_110 and combo3_1100_0000 ); + e_00_b(7) <= not( dcd_111 and tidn ); + + e( 0) <= not( e_00_b(0) and + e_00_b(1) and + e_00_b(2) and + e_00_b(3) and + e_00_b(4) and + e_00_b(5) and + e_00_b(6) and + e_00_b(7) ); + + e_01_b(0) <= not( dcd_000 and tiup ); + e_01_b(1) <= not( dcd_001 and tiup ); + e_01_b(2) <= not( dcd_010 and combo3_1111_0000 ); + e_01_b(3) <= not( dcd_011 and tidn ); + e_01_b(4) <= not( dcd_100 and tidn ); + e_01_b(5) <= not( dcd_101 and tidn ); + e_01_b(6) <= not( dcd_110 and combo3_0011_1111 ); + e_01_b(7) <= not( dcd_111 and tiup ); + + e( 1) <= not( e_01_b(0) and + e_01_b(1) and + e_01_b(2) and + e_01_b(3) and + e_01_b(4) and + e_01_b(5) and + e_01_b(6) and + e_01_b(7) ); + + e_02_b(0) <= not( dcd_000 and tiup ); + e_02_b(1) <= not( dcd_001 and combo3_1000_0000 ); + e_02_b(2) <= not( dcd_010 and combo3_0000_1111 ); + e_02_b(3) <= not( dcd_011 and tiup ); + e_02_b(4) <= not( dcd_100 and combo3_1000_0000 ); + e_02_b(5) <= not( dcd_101 and tidn ); + e_02_b(6) <= not( dcd_110 and combo3_0011_1111 ); + e_02_b(7) <= not( dcd_111 and tiup ); + + e( 2) <= not( e_02_b(0) and + e_02_b(1) and + e_02_b(2) and + e_02_b(3) and + e_02_b(4) and + e_02_b(5) and + e_02_b(6) and + e_02_b(7) ); + + e_03_b(0) <= not( dcd_000 and combo3_1111_1000 ); + e_03_b(1) <= not( dcd_001 and combo3_0111_1100 ); + e_03_b(2) <= not( dcd_010 and combo3_0000_1111 ); + e_03_b(3) <= not( dcd_011 and combo3_1100_0000 ); + e_03_b(4) <= not( dcd_100 and combo3_0111_1111 ); + e_03_b(5) <= not( dcd_101 and combo3_1000_0000 ); + e_03_b(6) <= not( dcd_110 and combo3_0011_1111 ); + e_03_b(7) <= not( dcd_111 and combo3_1111_0000 ); + + e( 3) <= not( e_03_b(0) and + e_03_b(1) and + e_03_b(2) and + e_03_b(3) and + e_03_b(4) and + e_03_b(5) and + e_03_b(6) and + e_03_b(7) ); + + e_04_b(0) <= not( dcd_000 and combo3_1110_0110 ); + e_04_b(1) <= not( dcd_001 and combo3_0111_0011 ); + e_04_b(2) <= not( dcd_010 and combo3_1000_1110 ); + e_04_b(3) <= not( dcd_011 and combo3_0011_1100 ); + e_04_b(4) <= not( dcd_100 and combo3_0111_1000 ); + e_04_b(5) <= not( dcd_101 and combo3_0111_1100 ); + e_04_b(6) <= not( dcd_110 and combo3_0011_1110 ); + e_04_b(7) <= not( dcd_111 and combo3_0000_1111 ); + + e( 4) <= not( e_04_b(0) and + e_04_b(1) and + e_04_b(2) and + e_04_b(3) and + e_04_b(4) and + e_04_b(5) and + e_04_b(6) and + e_04_b(7) ); + + e_05_b(0) <= not( dcd_000 and combo3_1101_0101 ); + e_05_b(1) <= not( dcd_001 and combo3_0110_1011 ); + e_05_b(2) <= not( dcd_010 and combo3_0110_1101 ); + e_05_b(3) <= not( dcd_011 and combo3_1011_0011 ); + e_05_b(4) <= not( dcd_100 and combo3_0110_0110 ); + e_05_b(5) <= not( dcd_101 and combo3_0110_0011 ); + e_05_b(6) <= not( dcd_110 and combo3_0011_1001 ); + e_05_b(7) <= not( dcd_111 and combo3_1100_1110 ); + + e( 5) <= not( e_05_b(0) and + e_05_b(1) and + e_05_b(2) and + e_05_b(3) and + e_05_b(4) and + e_05_b(5) and + e_05_b(6) and + e_05_b(7) ); + + e_06_b(0) <= not( dcd_000 and combo3_1000_0001 ); + e_06_b(1) <= not( dcd_001 and combo3_1100_0110 ); + e_06_b(2) <= not( dcd_010 and combo3_0100_1001 ); + e_06_b(3) <= not( dcd_011 and combo3_0110_1010 ); + e_06_b(4) <= not( dcd_100 and combo3_1101_0101 ); + e_06_b(5) <= not( dcd_101 and combo3_0101_1010 ); + e_06_b(6) <= not( dcd_110 and combo3_1010_0101 ); + e_06_b(7) <= not( dcd_111 and combo3_0010_1101 ); + + e( 6) <= not( e_06_b(0) and + e_06_b(1) and + e_06_b(2) and + e_06_b(3) and + e_06_b(4) and + e_06_b(5) and + e_06_b(6) and + e_06_b(7) ); + + e_07_b(0) <= not( dcd_000 and combo3_1000_0110 ); + e_07_b(1) <= not( dcd_001 and combo3_0100_1010 ); + e_07_b(2) <= not( dcd_010 and combo3_1101_0011 ); + e_07_b(3) <= not( dcd_011 and combo3_0011_1000 ); + e_07_b(4) <= not( dcd_100 and combo3_0111_1111 ); + e_07_b(5) <= not( dcd_101 and combo3_1111_0000 ); + e_07_b(6) <= not( dcd_110 and combo3_1111_0011 ); + e_07_b(7) <= not( dcd_111 and combo3_1001_1001 ); + + e( 7) <= not( e_07_b(0) and + e_07_b(1) and + e_07_b(2) and + e_07_b(3) and + e_07_b(4) and + e_07_b(5) and + e_07_b(6) and + e_07_b(7) ); + + e_08_b(0) <= not( dcd_000 and combo3_1000_1010 ); + e_08_b(1) <= not( dcd_001 and combo3_1001_1111 ); + e_08_b(2) <= not( dcd_010 and combo3_1001_1010 ); + e_08_b(3) <= not( dcd_011 and combo3_1010_0100 ); + e_08_b(4) <= not( dcd_100 and combo3_0111_1111 ); + e_08_b(5) <= not( dcd_101 and combo3_1111_0011 ); + e_08_b(6) <= not( dcd_110 and combo3_0011_0100 ); + e_08_b(7) <= not( dcd_111 and combo3_1010_1010 ); + + e( 8) <= not( e_08_b(0) and + e_08_b(1) and + e_08_b(2) and + e_08_b(3) and + e_08_b(4) and + e_08_b(5) and + e_08_b(6) and + e_08_b(7) ); + + e_09_b(0) <= not( dcd_000 and combo3_1001_0000 ); + e_09_b(1) <= not( dcd_001 and combo3_0101_1111 ); + e_09_b(2) <= not( dcd_010 and combo3_1010_1100 ); + e_09_b(3) <= not( dcd_011 and combo3_0001_0010 ); + e_09_b(4) <= not( dcd_100 and combo3_0100_0000 ); + e_09_b(5) <= not( dcd_101 and combo3_0011_0101 ); + e_09_b(6) <= not( dcd_110 and combo3_0101_1001 ); + e_09_b(7) <= not( dcd_111 and tiup ); + + e( 9) <= not( e_09_b(0) and + e_09_b(1) and + e_09_b(2) and + e_09_b(3) and + e_09_b(4) and + e_09_b(5) and + e_09_b(6) and + e_09_b(7) ); + + e_10_b(0) <= not( dcd_000 and combo3_1011_1000 ); + e_10_b(1) <= not( dcd_001 and combo3_1111_0000 ); + e_10_b(2) <= not( dcd_010 and combo3_1000_1010 ); + e_10_b(3) <= not( dcd_011 and combo3_0110_0111 ); + e_10_b(4) <= not( dcd_100 and combo3_0011_0000 ); + e_10_b(5) <= not( dcd_101 and combo3_1101_0000 ); + e_10_b(6) <= not( dcd_110 and combo3_0001_0101 ); + e_10_b(7) <= not( dcd_111 and combo3_1000_0011 ); + + e(10) <= not( e_10_b(0) and + e_10_b(1) and + e_10_b(2) and + e_10_b(3) and + e_10_b(4) and + e_10_b(5) and + e_10_b(6) and + e_10_b(7) ); + + e_11_b(0) <= not( dcd_000 and combo3_1000_1101 ); + e_11_b(1) <= not( dcd_001 and combo3_1001_1001 ); + e_11_b(2) <= not( dcd_010 and combo3_0101_0001 ); + e_11_b(3) <= not( dcd_011 and combo3_1011_0111 ); + e_11_b(4) <= not( dcd_100 and combo3_0110_1001 ); + e_11_b(5) <= not( dcd_101 and combo3_0111_1000 ); + e_11_b(6) <= not( dcd_110 and combo3_0011_0001 ); + e_11_b(7) <= not( dcd_111 and combo3_0110_1101 ); + + e(11) <= not( e_11_b(0) and + e_11_b(1) and + e_11_b(2) and + e_11_b(3) and + e_11_b(4) and + e_11_b(5) and + e_11_b(6) and + e_11_b(7) ); + + e_12_b(0) <= not( dcd_000 and combo3_1010_0010 ); + e_12_b(1) <= not( dcd_001 and tidn ); + e_12_b(2) <= not( dcd_010 and combo3_1110_0011 ); + e_12_b(3) <= not( dcd_011 and combo3_1111_0101 ); + e_12_b(4) <= not( dcd_100 and combo3_0110_0110 ); + e_12_b(5) <= not( dcd_101 and combo3_0000_1100 ); + e_12_b(6) <= not( dcd_110 and combo3_0110_1110 ); + e_12_b(7) <= not( dcd_111 and combo3_0101_0000 ); + + e(12) <= not( e_12_b(0) and + e_12_b(1) and + e_12_b(2) and + e_12_b(3) and + e_12_b(4) and + e_12_b(5) and + e_12_b(6) and + e_12_b(7) ); + + e_13_b(0) <= not( dcd_000 and combo3_1100_0111 ); + e_13_b(1) <= not( dcd_001 and combo3_0000_0100 ); + e_13_b(2) <= not( dcd_010 and combo3_1011_1001 ); + e_13_b(3) <= not( dcd_011 and combo3_1011_1010 ); + e_13_b(4) <= not( dcd_100 and combo3_1111_1110 ); + e_13_b(5) <= not( dcd_101 and combo3_0101_1110 ); + e_13_b(6) <= not( dcd_110 and combo3_1110_0011 ); + e_13_b(7) <= not( dcd_111 and combo3_1001_0100 ); + + e(13) <= not( e_13_b(0) and + e_13_b(1) and + e_13_b(2) and + e_13_b(3) and + e_13_b(4) and + e_13_b(5) and + e_13_b(6) and + e_13_b(7) ); + + e_14_b(0) <= not( dcd_000 and combo3_0111_1001 ); + e_14_b(1) <= not( dcd_001 and combo3_1111_1011 ); + e_14_b(2) <= not( dcd_010 and combo3_1010_0111 ); + e_14_b(3) <= not( dcd_011 and combo3_1000_0000 ); + e_14_b(4) <= not( dcd_100 and combo3_1110_0001 ); + e_14_b(5) <= not( dcd_101 and combo3_0110_1101 ); + e_14_b(6) <= not( dcd_110 and combo3_0000_0001 ); + e_14_b(7) <= not( dcd_111 and combo3_0001_0111 ); + + e(14) <= not( e_14_b(0) and + e_14_b(1) and + e_14_b(2) and + e_14_b(3) and + e_14_b(4) and + e_14_b(5) and + e_14_b(6) and + e_14_b(7) ); + + e_15_b(0) <= not( dcd_000 and combo3_0101_0101 ); + e_15_b(1) <= not( dcd_001 and combo3_1001_1010 ); + e_15_b(2) <= not( dcd_010 and combo3_0010_1001 ); + e_15_b(3) <= not( dcd_011 and combo3_0010_1001 ); + e_15_b(4) <= not( dcd_100 and combo3_1001_1101 ); + e_15_b(5) <= not( dcd_101 and combo3_1001_1110 ); + e_15_b(6) <= not( dcd_110 and combo3_1100_1010 ); + e_15_b(7) <= not( dcd_111 and combo3_1110_0100 ); + + e(15) <= not( e_15_b(0) and + e_15_b(1) and + e_15_b(2) and + e_15_b(3) and + e_15_b(4) and + e_15_b(5) and + e_15_b(6) and + e_15_b(7) ); + + e_16_b(0) <= not( dcd_000 and combo3_0111_1110 ); + e_16_b(1) <= not( dcd_001 and combo3_1100_1010 ); + e_16_b(2) <= not( dcd_010 and combo3_0010_0010 ); + e_16_b(3) <= not( dcd_011 and combo3_1111_1001 ); + e_16_b(4) <= not( dcd_100 and combo3_1101_1000 ); + e_16_b(5) <= not( dcd_101 and combo3_0111_0010 ); + e_16_b(6) <= not( dcd_110 and combo3_0100_1101 ); + e_16_b(7) <= not( dcd_111 and combo3_0011_1010 ); + + e(16) <= not( e_16_b(0) and + e_16_b(1) and + e_16_b(2) and + e_16_b(3) and + e_16_b(4) and + e_16_b(5) and + e_16_b(6) and + e_16_b(7) ); + + e_17_b(0) <= not( dcd_000 and combo3_0111_0010 ); + e_17_b(1) <= not( dcd_001 and combo3_1010_1110 ); + e_17_b(2) <= not( dcd_010 and combo3_1110_0010 ); + e_17_b(3) <= not( dcd_011 and combo3_0100_0110 ); + e_17_b(4) <= not( dcd_100 and combo3_1101_0011 ); + e_17_b(5) <= not( dcd_101 and combo3_1000_1111 ); + e_17_b(6) <= not( dcd_110 and combo3_0000_1101 ); + e_17_b(7) <= not( dcd_111 and combo3_1001_1100 ); + + e(17) <= not( e_17_b(0) and + e_17_b(1) and + e_17_b(2) and + e_17_b(3) and + e_17_b(4) and + e_17_b(5) and + e_17_b(6) and + e_17_b(7) ); + + e_18_b(0) <= not( dcd_000 and combo3_0001_0100 ); + e_18_b(1) <= not( dcd_001 and combo3_0011_1000 ); + e_18_b(2) <= not( dcd_010 and combo3_0101_0001 ); + e_18_b(3) <= not( dcd_011 and combo3_0001_0001 ); + e_18_b(4) <= not( dcd_100 and combo3_0010_0110 ); + e_18_b(5) <= not( dcd_101 and combo3_0011_0001 ); + e_18_b(6) <= not( dcd_110 and combo3_0111_0110 ); + e_18_b(7) <= not( dcd_111 and combo3_1001_1100 ); + + e(18) <= not( e_18_b(0) and + e_18_b(1) and + e_18_b(2) and + e_18_b(3) and + e_18_b(4) and + e_18_b(5) and + e_18_b(6) and + e_18_b(7) ); + + e_19_b(0) <= not( dcd_000 and tiup ); + e_19_b(1) <= not( dcd_001 and tiup ); + e_19_b(2) <= not( dcd_010 and tiup ); + e_19_b(3) <= not( dcd_011 and tiup ); + e_19_b(4) <= not( dcd_100 and tiup ); + e_19_b(5) <= not( dcd_101 and tiup ); + e_19_b(6) <= not( dcd_110 and tiup ); + e_19_b(7) <= not( dcd_111 and tiup ); + + e(19) <= not( e_19_b(0) and + e_19_b(1) and + e_19_b(2) and + e_19_b(3) and + e_19_b(4) and + e_19_b(5) and + e_19_b(6) and + e_19_b(7) ); + + + + + r_00_b(0) <= not( dcd_000 and tidn ); + r_00_b(1) <= not( dcd_001 and tidn ); + r_00_b(2) <= not( dcd_010 and tidn ); + r_00_b(3) <= not( dcd_011 and tidn ); + r_00_b(4) <= not( dcd_100 and tidn ); + r_00_b(5) <= not( dcd_101 and tidn ); + r_00_b(6) <= not( dcd_110 and tidn ); + r_00_b(7) <= not( dcd_111 and tidn ); + + r( 0) <= not( r_00_b(0) and + r_00_b(1) and + r_00_b(2) and + r_00_b(3) and + r_00_b(4) and + r_00_b(5) and + r_00_b(6) and + r_00_b(7) ); + + r_01_b(0) <= not( dcd_000 and tiup ); + r_01_b(1) <= not( dcd_001 and tiup ); + r_01_b(2) <= not( dcd_010 and tiup ); + r_01_b(3) <= not( dcd_011 and tiup ); + r_01_b(4) <= not( dcd_100 and combo3_1111_1100 ); + r_01_b(5) <= not( dcd_101 and tidn ); + r_01_b(6) <= not( dcd_110 and tidn ); + r_01_b(7) <= not( dcd_111 and tidn ); + + r( 1) <= not( r_01_b(0) and + r_01_b(1) and + r_01_b(2) and + r_01_b(3) and + r_01_b(4) and + r_01_b(5) and + r_01_b(6) and + r_01_b(7) ); + + r_02_b(0) <= not( dcd_000 and tiup ); + r_02_b(1) <= not( dcd_001 and combo3_1111_1100 ); + r_02_b(2) <= not( dcd_010 and tidn ); + r_02_b(3) <= not( dcd_011 and tidn ); + r_02_b(4) <= not( dcd_100 and combo3_0000_0011 ); + r_02_b(5) <= not( dcd_101 and tiup ); + r_02_b(6) <= not( dcd_110 and tiup ); + r_02_b(7) <= not( dcd_111 and tiup ); + + r( 2) <= not( r_02_b(0) and + r_02_b(1) and + r_02_b(2) and + r_02_b(3) and + r_02_b(4) and + r_02_b(5) and + r_02_b(6) and + r_02_b(7) ); + + r_03_b(0) <= not( dcd_000 and combo3_1111_1100 ); + r_03_b(1) <= not( dcd_001 and combo3_0000_0011 ); + r_03_b(2) <= not( dcd_010 and tiup ); + r_03_b(3) <= not( dcd_011 and tidn ); + r_03_b(4) <= not( dcd_100 and combo3_0000_0011 ); + r_03_b(5) <= not( dcd_101 and tiup ); + r_03_b(6) <= not( dcd_110 and tiup ); + r_03_b(7) <= not( dcd_111 and combo3_1110_0000 ); + + r( 3) <= not( r_03_b(0) and + r_03_b(1) and + r_03_b(2) and + r_03_b(3) and + r_03_b(4) and + r_03_b(5) and + r_03_b(6) and + r_03_b(7) ); + + r_04_b(0) <= not( dcd_000 and combo3_1110_0011 ); + r_04_b(1) <= not( dcd_001 and combo3_1100_0011 ); + r_04_b(2) <= not( dcd_010 and combo3_1100_0000 ); + r_04_b(3) <= not( dcd_011 and combo3_1111_1100 ); + r_04_b(4) <= not( dcd_100 and combo3_0000_0011 ); + r_04_b(5) <= not( dcd_101 and combo3_1111_1110 ); + r_04_b(6) <= not( dcd_110 and tidn ); + r_04_b(7) <= not( dcd_111 and combo3_0001_1111 ); + + r( 4) <= not( r_04_b(0) and + r_04_b(1) and + r_04_b(2) and + r_04_b(3) and + r_04_b(4) and + r_04_b(5) and + r_04_b(6) and + r_04_b(7) ); + + r_05_b(0) <= not( dcd_000 and combo3_1001_0011 ); + r_05_b(1) <= not( dcd_001 and combo3_0010_0011 ); + r_05_b(2) <= not( dcd_010 and combo3_0011_1000 ); + r_05_b(3) <= not( dcd_011 and combo3_1110_0011 ); + r_05_b(4) <= not( dcd_100 and combo3_1100_0011 ); + r_05_b(5) <= not( dcd_101 and combo3_1100_0001 ); + r_05_b(6) <= not( dcd_110 and combo3_1111_1000 ); + r_05_b(7) <= not( dcd_111 and combo3_0001_1111 ); + + r( 5) <= not( r_05_b(0) and + r_05_b(1) and + r_05_b(2) and + r_05_b(3) and + r_05_b(4) and + r_05_b(5) and + r_05_b(6) and + r_05_b(7) ); + + r_06_b(0) <= not( dcd_000 and combo3_1101_1010 ); + r_06_b(1) <= not( dcd_001 and combo3_1001_0010 ); + r_06_b(2) <= not( dcd_010 and combo3_1010_0100 ); + r_06_b(3) <= not( dcd_011 and combo3_1001_0011 ); + r_06_b(4) <= not( dcd_100 and combo3_0011_0011 ); + r_06_b(5) <= not( dcd_101 and combo3_0011_0001 ); + r_06_b(6) <= not( dcd_110 and combo3_1100_0111 ); + r_06_b(7) <= not( dcd_111 and combo3_0001_1110 ); + + r( 6) <= not( r_06_b(0) and + r_06_b(1) and + r_06_b(2) and + r_06_b(3) and + r_06_b(4) and + r_06_b(5) and + r_06_b(6) and + r_06_b(7) ); + + r_07_b(0) <= not( dcd_000 and combo3_0100_1100 ); + r_07_b(1) <= not( dcd_001 and combo3_0011_1000 ); + r_07_b(2) <= not( dcd_010 and combo3_0111_0010 ); + r_07_b(3) <= not( dcd_011 and combo3_0100_1010 ); + r_07_b(4) <= not( dcd_100 and combo3_1010_1010 ); + r_07_b(5) <= not( dcd_101 and combo3_1010_1101 ); + r_07_b(6) <= not( dcd_110 and combo3_0010_0100 ); + r_07_b(7) <= not( dcd_111 and combo3_1001_1001 ); + + r( 7) <= not( r_07_b(0) and + r_07_b(1) and + r_07_b(2) and + r_07_b(3) and + r_07_b(4) and + r_07_b(5) and + r_07_b(6) and + r_07_b(7) ); + + r_08_b(0) <= not( dcd_000 and combo3_1110_1010 ); + r_08_b(1) <= not( dcd_001 and combo3_0011_1000 ); + r_08_b(2) <= not( dcd_010 and combo3_1001_0100 ); + r_08_b(3) <= not( dcd_011 and combo3_1001_1000 ); + r_08_b(4) <= not( dcd_100 and tidn ); + r_08_b(5) <= not( dcd_101 and combo3_0011_1001 ); + r_08_b(6) <= not( dcd_110 and combo3_1001_0010 ); + r_08_b(7) <= not( dcd_111 and combo3_1101_0101 ); + + r( 8) <= not( r_08_b(0) and + r_08_b(1) and + r_08_b(2) and + r_08_b(3) and + r_08_b(4) and + r_08_b(5) and + r_08_b(6) and + r_08_b(7) ); + + r_09_b(0) <= not( dcd_000 and combo3_0010_0001 ); + r_09_b(1) <= not( dcd_001 and combo3_0011_1001 ); + r_09_b(2) <= not( dcd_010 and combo3_0011_1110 ); + r_09_b(3) <= not( dcd_011 and combo3_0101_0110 ); + r_09_b(4) <= not( dcd_100 and tidn ); + r_09_b(5) <= not( dcd_101 and combo3_1101_1010 ); + r_09_b(6) <= not( dcd_110 and combo3_1011_0110 ); + r_09_b(7) <= not( dcd_111 and combo3_0111_0000 ); + + r( 9) <= not( r_09_b(0) and + r_09_b(1) and + r_09_b(2) and + r_09_b(3) and + r_09_b(4) and + r_09_b(5) and + r_09_b(6) and + r_09_b(7) ); + + r_10_b(0) <= not( dcd_000 and combo3_0101_0011 ); + r_10_b(1) <= not( dcd_001 and combo3_1011_1011 ); + r_10_b(2) <= not( dcd_010 and combo3_1011_0110 ); + r_10_b(3) <= not( dcd_011 and combo3_1101_1101 ); + r_10_b(4) <= not( dcd_100 and combo3_1000_0011 ); + r_10_b(5) <= not( dcd_101 and combo3_0110_1111 ); + r_10_b(6) <= not( dcd_110 and combo3_1110_0101 ); + r_10_b(7) <= not( dcd_111 and combo3_0100_1000 ); + + r(10) <= not( r_10_b(0) and + r_10_b(1) and + r_10_b(2) and + r_10_b(3) and + r_10_b(4) and + r_10_b(5) and + r_10_b(6) and + r_10_b(7) ); + + r_11_b(0) <= not( dcd_000 and combo3_0010_1110 ); + r_11_b(1) <= not( dcd_001 and combo3_0000_1011 ); + r_11_b(2) <= not( dcd_010 and combo3_1110_1011 ); + r_11_b(3) <= not( dcd_011 and combo3_1010_0111 ); + r_11_b(4) <= not( dcd_100 and combo3_0100_0101 ); + r_11_b(5) <= not( dcd_101 and combo3_1100_1100 ); + r_11_b(6) <= not( dcd_110 and combo3_0110_1100 ); + r_11_b(7) <= not( dcd_111 and combo3_0010_0110 ); + + r(11) <= not( r_11_b(0) and + r_11_b(1) and + r_11_b(2) and + r_11_b(3) and + r_11_b(4) and + r_11_b(5) and + r_11_b(6) and + r_11_b(7) ); + + r_12_b(0) <= not( dcd_000 and combo3_0011_1100 ); + r_12_b(1) <= not( dcd_001 and combo3_1010_0110 ); + r_12_b(2) <= not( dcd_010 and combo3_1000_1000 ); + r_12_b(3) <= not( dcd_011 and combo3_0010_1101 ); + r_12_b(4) <= not( dcd_100 and combo3_0011_1001 ); + r_12_b(5) <= not( dcd_101 and combo3_1101_1011 ); + r_12_b(6) <= not( dcd_110 and combo3_1011_1011 ); + r_12_b(7) <= not( dcd_111 and combo3_1100_1100 ); + + r(12) <= not( r_12_b(0) and + r_12_b(1) and + r_12_b(2) and + r_12_b(3) and + r_12_b(4) and + r_12_b(5) and + r_12_b(6) and + r_12_b(7) ); + + r_13_b(0) <= not( dcd_000 and combo3_1001_0111 ); + r_13_b(1) <= not( dcd_001 and combo3_0001_0101 ); + r_13_b(2) <= not( dcd_010 and combo3_1011_1110 ); + r_13_b(3) <= not( dcd_011 and combo3_1110_0110 ); + r_13_b(4) <= not( dcd_100 and combo3_0000_1111 ); + r_13_b(5) <= not( dcd_101 and combo3_0001_1000 ); + r_13_b(6) <= not( dcd_110 and combo3_1011_1110 ); + r_13_b(7) <= not( dcd_111 and combo3_0110_1101 ); + + r(13) <= not( r_13_b(0) and + r_13_b(1) and + r_13_b(2) and + r_13_b(3) and + r_13_b(4) and + r_13_b(5) and + r_13_b(6) and + r_13_b(7) ); + + r_14_b(0) <= not( dcd_000 and tidn ); + r_14_b(1) <= not( dcd_001 and tidn ); + r_14_b(2) <= not( dcd_010 and tidn ); + r_14_b(3) <= not( dcd_011 and tidn ); + r_14_b(4) <= not( dcd_100 and tidn ); + r_14_b(5) <= not( dcd_101 and tidn ); + r_14_b(6) <= not( dcd_110 and tidn ); + r_14_b(7) <= not( dcd_111 and tidn ); + + r(14) <= not( r_14_b(0) and + r_14_b(1) and + r_14_b(2) and + r_14_b(3) and + r_14_b(4) and + r_14_b(5) and + r_14_b(6) and + r_14_b(7) ); + + + + + est(1 to 20) <= e(0 to 19); + rng(6 to 20) <= r(0 to 14); + + +end; + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq.vhdl new file mode 100644 index 0000000..1261ce9 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq.vhdl @@ -0,0 +1,1858 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; +use ieee.std_logic_1164.all; +library support; +use support.power_logic_pkg.all; +library work; +use work.iuq_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity iuq is + generic(expand_type : integer := 2; + a2mode : integer := 1; + lmq_entries : integer := 8; + fpr_addr_width : integer := 5; + regmode : integer := 6; + threads : integer := 4; + ucode_mode : integer := 1; + bcfg_epn_0to15 : integer := 0; + bcfg_epn_16to31 : integer := 0; + bcfg_epn_32to47 : integer := (2**16)-1; + bcfg_epn_48to51 : integer := (2**4)-1; + bcfg_rpn_22to31 : integer := (2**10)-1; + bcfg_rpn_32to47 : integer := (2**16)-1; + bcfg_rpn_48to51 : integer := (2**4)-1; + uc_ifar : integer := 21); +port( + vcs : inout power_logic; + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + + tc_ac_ccflush_dc : in std_ulogic; + an_ac_scan_dis_dc_b : in std_ulogic; + an_ac_scan_diag_dc : in std_ulogic; + + pc_iu_gptr_sl_thold_4 : in std_ulogic; + pc_iu_time_sl_thold_4 : in std_ulogic; + pc_iu_repr_sl_thold_4 : in std_ulogic; + pc_iu_abst_sl_thold_4 : in std_ulogic; + pc_iu_abst_slp_sl_thold_4 : in std_ulogic; + pc_iu_bolt_sl_thold_4 : in std_ulogic; + pc_iu_regf_slp_sl_thold_4 : in std_ulogic; + pc_iu_func_sl_thold_4 : in std_ulogic; + pc_iu_func_slp_sl_thold_4 : in std_ulogic; + pc_iu_cfg_sl_thold_4 : in std_ulogic; + pc_iu_cfg_slp_sl_thold_4 : in std_ulogic; + pc_iu_func_nsl_thold_4 : in std_ulogic; + pc_iu_func_slp_nsl_thold_4 : in std_ulogic; + pc_iu_ary_nsl_thold_4 : in std_ulogic; + pc_iu_ary_slp_nsl_thold_4 : in std_ulogic; + pc_iu_sg_4 : in std_ulogic; + pc_iu_fce_4 : in std_ulogic; + + pc_iu_abist_dcomp_g6t_2r : in std_ulogic_vector(0 to 3); + pc_iu_abist_di_0 : in std_ulogic_vector(0 to 3); + pc_iu_abist_di_g6t_2r : in std_ulogic_vector(0 to 3); + pc_iu_abist_ena_dc : in std_ulogic; + pc_iu_abist_g6t_bw : in std_ulogic_vector(0 to 1); + pc_iu_abist_g6t_r_wb : in std_ulogic; + pc_iu_abist_g8t1p_renb_0 : in std_ulogic; + pc_iu_abist_g8t_bw_0 : in std_ulogic; + pc_iu_abist_g8t_bw_1 : in std_ulogic; + pc_iu_abist_g8t_dcomp : in std_ulogic_vector(0 to 3); + pc_iu_abist_g8t_wenb : in std_ulogic; + pc_iu_abist_raddr_0 : in std_ulogic_vector(0 to 9); + pc_iu_abist_raw_dc_b : in std_ulogic; + pc_iu_abist_waddr_0 : in std_ulogic_vector(0 to 9); + pc_iu_abist_wl256_comp_ena : in std_ulogic; + pc_iu_abist_wl64_comp_ena : in std_ulogic; + pc_iu_abist_wl128_comp_ena : in std_ulogic; + an_ac_lbist_ary_wrt_thru_dc: in std_ulogic; + an_ac_lbist_en_dc : in std_ulogic; + an_ac_atpg_en_dc : in std_ulogic; + an_ac_grffence_en_dc : in std_ulogic; + + pc_iu_bo_enable_4 : in std_ulogic; + pc_iu_bo_reset : in std_ulogic; + pc_iu_bo_unload : in std_ulogic; + pc_iu_bo_repair : in std_ulogic; + pc_iu_bo_shdata : in std_ulogic; + pc_iu_bo_select : in std_ulogic_vector(0 to 4); + iu_pc_bo_fail : out std_ulogic_vector(0 to 4); + iu_pc_bo_diagout : out std_ulogic_vector(0 to 4); + + + iu_pc_err_icache_parity : out std_ulogic; + iu_pc_err_icachedir_parity : out std_ulogic; + iu_pc_err_icachedir_multihit : out std_ulogic; + + iu_pc_err_ucode_illegal : out std_ulogic_vector(0 to 3); + + pc_iu_inj_icache_parity : in std_ulogic; + pc_iu_inj_icachedir_parity : in std_ulogic; + pc_iu_inj_icachedir_multihit : in std_ulogic; + + pc_iu_trace_bus_enable : in std_ulogic; + pc_iu_debug_mux1_ctrls : in std_ulogic_vector(0 to 15); + pc_iu_debug_mux2_ctrls : in std_ulogic_vector(0 to 15); + debug_data_in : in std_ulogic_vector(0 to 87); + trace_triggers_in : in std_ulogic_vector(0 to 11); + debug_data_out : out std_ulogic_vector(0 to 87); + trace_triggers_out : out std_ulogic_vector(0 to 11); + pc_iu_event_mux_ctrls : in std_ulogic_vector(0 to 47); + pc_iu_event_count_mode : in std_ulogic_vector(0 to 2); + pc_iu_event_bus_enable : in std_ulogic; + iu_pc_event_data : out std_ulogic_vector(0 to 7); + + pc_iu_init_reset : in std_ulogic; + + gptr_scan_in : in std_ulogic; + time_scan_in : in std_ulogic; + repr_scan_in : in std_ulogic; + abst_scan_in : in std_ulogic_vector(0 to 2); + func_scan_in : in std_ulogic_vector(0 to 13); + ccfg_scan_in : in std_ulogic; + bcfg_scan_in : in std_ulogic; + dcfg_scan_in : in std_ulogic; + regf_scan_in : in std_ulogic_vector(0 to 4); + + gptr_scan_out : out std_ulogic; + time_scan_out : out std_ulogic; + repr_scan_out : out std_ulogic; + abst_scan_out : out std_ulogic_vector(0 to 2); + func_scan_out : out std_ulogic_vector(0 to 13); + ccfg_scan_out : out std_ulogic; + bcfg_scan_out : out std_ulogic; + dcfg_scan_out : out std_ulogic; + regf_scan_out : out std_ulogic_vector(0 to 4); + + slowspr_val_in : in std_ulogic; + slowspr_rw_in : in std_ulogic; + slowspr_etid_in : in std_ulogic_vector(0 to 1); + slowspr_addr_in : in std_ulogic_vector(0 to 9); + slowspr_data_in : in std_ulogic_vector(64-(2**regmode) to 63); + slowspr_done_in : in std_ulogic; + + slowspr_val_out : out std_ulogic; + slowspr_rw_out : out std_ulogic; + slowspr_etid_out : out std_ulogic_vector(0 to 1); + slowspr_addr_out : out std_ulogic_vector(0 to 9); + slowspr_data_out : out std_ulogic_vector(64-(2**regmode) to 63); + slowspr_done_out : out std_ulogic; + + xu_iu_run_thread : in std_ulogic_vector(0 to 3); + xu_iu_l_flush : in std_ulogic_vector(0 to 3); + xu_iu_u_flush : in std_ulogic_vector(0 to 3); + xu_iu_iu0_flush_ifar0 : in EFF_IFAR; + xu_iu_iu0_flush_ifar1 : in EFF_IFAR; + xu_iu_iu0_flush_ifar2 : in EFF_IFAR; + xu_iu_iu0_flush_ifar3 : in EFF_IFAR; + xu_iu_flush_2ucode : in std_ulogic_vector(0 to 3); + xu_iu_flush_2ucode_type : in std_ulogic_vector(0 to 3); + xu_iu_membar_tid : in std_ulogic_vector(0 to 3); + xu_iu_set_barr_tid : in std_ulogic_vector(0 to 3); + xu_iu_larx_done_tid : in std_ulogic_vector(0 to 3); + xu_iu_msr_cm : in std_ulogic_vector(0 to threads-1); + xu_iu_ex6_icbi_val : in std_ulogic_vector(0 to threads-1); + xu_iu_ex6_icbi_addr : in std_ulogic_vector(REAL_IFAR'left to 57); + xu_iu_ici : in std_ulogic; + iu_xu_request : out std_ulogic; + iu_xu_thread : out std_ulogic_vector(0 to 3); + iu_xu_ra : out std_ulogic_vector(REAL_IFAR'left to 59); + iu_xu_wimge : out std_ulogic_vector(0 to 4); + iu_xu_userdef : out std_ulogic_vector(0 to 3); + + an_ac_reld_data_vld : in std_ulogic; + an_ac_reld_data_vld_clone : in std_ulogic; + an_ac_reld_ditc_clone : in std_ulogic; + an_ac_reld_data_coming_clone: in std_ulogic; + an_ac_reld_core_tag : in std_ulogic_vector(0 to 4); + an_ac_reld_core_tag_clone : in std_ulogic_vector(1 to 4); + an_ac_reld_qw : in std_ulogic_vector(57 to 59); + an_ac_reld_data : in std_ulogic_vector(0 to 127); + an_ac_reld_ecc_err : in std_ulogic; + an_ac_reld_ecc_err_ue : in std_ulogic; + an_ac_back_inv : in std_ulogic; + an_ac_back_inv_addr : in std_ulogic_vector(REAL_IFAR'left to 63); + an_ac_back_inv_target_iiu_a: in std_ulogic_vector(0 to 1); + an_ac_back_inv_target_iiu_b: in std_ulogic_vector(3 to 4); + an_ac_sync_ack : in std_ulogic_vector(0 to 3); + an_ac_stcx_complete : in std_ulogic_vector(0 to 3); + an_ac_icbi_ack : in std_ulogic; + an_ac_icbi_ack_thread : in std_ulogic_vector(0 to 1); + + iu_mm_ierat_req : out std_ulogic; + iu_mm_ierat_epn : out std_ulogic_vector(0 to 51); + iu_mm_ierat_thdid : out std_ulogic_vector(0 to 3); + iu_mm_ierat_state : out std_ulogic_vector(0 to 3); + iu_mm_ierat_tid : out std_ulogic_vector(0 to 13); + iu_mm_ierat_flush : out std_ulogic_vector(0 to 3); + mm_iu_ierat_rel_val : in std_ulogic_vector(0 to 4); + mm_iu_ierat_rel_data : in std_ulogic_vector(0 to 131); + mm_iu_ierat_snoop_coming : in std_ulogic; + mm_iu_ierat_snoop_val : in std_ulogic; + mm_iu_ierat_snoop_attr : in std_ulogic_vector(0 to 25); + mm_iu_ierat_snoop_vpn : in std_ulogic_vector(EFF_IFAR'left to 51); + iu_mm_ierat_snoop_ack : out std_ulogic; + mm_iu_ierat_pid0 : in std_ulogic_vector(0 to 13); + mm_iu_ierat_pid1 : in std_ulogic_vector(0 to 13); + mm_iu_ierat_pid2 : in std_ulogic_vector(0 to 13); + mm_iu_ierat_pid3 : in std_ulogic_vector(0 to 13); + mm_iu_ierat_mmucr0_0 : in std_ulogic_vector(0 to 19); + mm_iu_ierat_mmucr0_1 : in std_ulogic_vector(0 to 19); + mm_iu_ierat_mmucr0_2 : in std_ulogic_vector(0 to 19); + mm_iu_ierat_mmucr0_3 : in std_ulogic_vector(0 to 19); + iu_mm_ierat_mmucr0 : out std_ulogic_vector(0 to 17); + iu_mm_ierat_mmucr0_we : out std_ulogic_vector(0 to 3); + mm_iu_ierat_mmucr1 : in std_ulogic_vector(0 to 8); + iu_mm_ierat_mmucr1 : out std_ulogic_vector(0 to 3); + iu_mm_ierat_mmucr1_we : out std_ulogic; + mm_iu_barrier_done : in std_ulogic_vector(0 to 3); + iu_mm_lmq_empty : out std_ulogic; + + xu_iu_ex1_rb : in std_ulogic_vector(64-(2**regmode) to 51); + xu_wl_rf1_flush : in std_ulogic_vector(0 to 3); + xu_wl_ex1_flush : in std_ulogic_vector(0 to 3); + xu_wl_ex2_flush : in std_ulogic_vector(0 to 3); + xu_wl_ex3_flush : in std_ulogic_vector(0 to 3); + xu_wl_ex4_flush : in std_ulogic_vector(0 to 3); + xu_wl_ex5_flush : in std_ulogic_vector(0 to 3); + xu_wu_rf1_flush : in std_ulogic_vector(0 to 3); + xu_wu_ex1_flush : in std_ulogic_vector(0 to 3); + xu_wu_ex2_flush : in std_ulogic_vector(0 to 3); + xu_wu_ex3_flush : in std_ulogic_vector(0 to 3); + xu_wu_ex4_flush : in std_ulogic_vector(0 to 3); + xu_wu_ex5_flush : in std_ulogic_vector(0 to 3); + xu_iu_ex4_rs_data : in std_ulogic_vector(64-(2**regmode) to 63); + xu_iu_hid_mmu_mode : in std_ulogic; + xu_iu_msr_hv : in std_ulogic_vector(0 to threads-1); + xu_iu_msr_is : in std_ulogic_vector(0 to threads-1); + xu_iu_msr_pr : in std_ulogic_vector(0 to threads-1); + xu_iu_spr_ccr2_ifratsc : in std_ulogic_vector(0 to 8); + xu_iu_spr_ccr2_ifrat : in std_ulogic; + xu_iu_xucr4_mmu_mchk : in std_ulogic; + xu_iu_rf1_val : in std_ulogic_vector(0 to 3); + xu_iu_rf1_is_eratre : in std_ulogic; + xu_iu_rf1_is_eratsx : in std_ulogic; + xu_iu_rf1_is_eratwe : in std_ulogic; + xu_iu_rf1_is_eratilx : in std_ulogic; + xu_iu_ex1_is_isync : in std_ulogic; + xu_iu_ex1_is_csync : in std_ulogic; + xu_iu_rf1_ws : in std_ulogic_vector(0 to 1); + xu_iu_rf1_t : in std_ulogic_vector(0 to 2); + xu_iu_ex1_ra_entry : in std_ulogic_vector(8 to 11); + xu_iu_ex1_rs_is : in std_ulogic_vector(0 to 8); + iu_xu_ex4_tlb_data : out std_ulogic_vector(64-(2**regmode) to 63); + iu_xu_ierat_ex3_par_err : out std_ulogic_vector(0 to threads-1); + iu_xu_ierat_ex4_par_err : out std_ulogic_vector(0 to threads-1); + iu_xu_ierat_ex2_flush_req : out std_ulogic_vector(0 to threads-1); + + xu_iu_ex5_ifar : in EFF_IFAR; + xu_iu_ex5_tid : in std_ulogic_vector(0 to 3); + xu_iu_ex5_val : in std_ulogic; + xu_iu_ex5_br_update : in std_ulogic; + xu_iu_ex5_br_hist : in std_ulogic_vector(0 to 1); + xu_iu_ex5_br_taken : in std_ulogic; + xu_iu_ex5_bclr : in std_ulogic; + xu_iu_ex5_getNIA : in std_ulogic; + xu_iu_ex5_lk : in std_ulogic; + xu_iu_ex5_bh : in std_ulogic_vector(0 to 1); + xu_iu_ex5_gshare : in std_ulogic_vector(0 to 3); + + pc_iu_ram_instr : in std_ulogic_vector(0 to 31); + pc_iu_ram_instr_ext : in std_ulogic_vector(0 to 3); + pc_iu_ram_force_cmplt : in std_ulogic; + pc_iu_ram_mode : in std_ulogic; + pc_iu_ram_thread : in std_ulogic_vector(0 to 1); + xu_iu_ram_issue : in std_ulogic_vector(0 to 3); + + xu_iu_ex6_pri : in std_ulogic_vector(0 to 2); + xu_iu_ex6_pri_val : in std_ulogic_vector(0 to 3); + xu_iu_raise_iss_pri : in std_ulogic_vector(0 to 3); + xu_iu_msr_gs : in std_ulogic_vector(0 to 3); + + xu_iu_ucode_restart : in std_ulogic_vector(0 to 3); + xu_iu_spr_xer0 : in std_ulogic_vector(57 to 63); + xu_iu_spr_xer1 : in std_ulogic_vector(57 to 63); + xu_iu_spr_xer2 : in std_ulogic_vector(57 to 63); + xu_iu_spr_xer3 : in std_ulogic_vector(57 to 63); + xu_iu_uc_flush_ifar0 : in std_ulogic_vector(62-uc_ifar to 61); + xu_iu_uc_flush_ifar1 : in std_ulogic_vector(62-uc_ifar to 61); + xu_iu_uc_flush_ifar2 : in std_ulogic_vector(62-uc_ifar to 61); + xu_iu_uc_flush_ifar3 : in std_ulogic_vector(62-uc_ifar to 61); + + xu_iu_slowspr_done : in std_ulogic_vector(0 to 3); + + xu_iu_ex4_loadmiss_tid : in std_ulogic_vector(0 to 3); + xu_iu_ex4_loadmiss_qentry : in std_ulogic_vector(0 to lmq_entries-1); + xu_iu_ex4_loadmiss_target : in std_ulogic_vector(0 to 8); + xu_iu_ex4_loadmiss_target_type : in std_ulogic_vector(0 to 1); + xu_iu_ex5_loadmiss_tid : in std_ulogic_vector(0 to 3); + xu_iu_ex5_loadmiss_qentry : in std_ulogic_vector(0 to lmq_entries-1); + xu_iu_ex5_loadmiss_target : in std_ulogic_vector(0 to 8); + xu_iu_ex5_loadmiss_target_type : in std_ulogic_vector(0 to 1); + + xu_iu_complete_tid : in std_ulogic_vector(0 to 3); + xu_iu_complete_qentry : in std_ulogic_vector(0 to lmq_entries-1); + xu_iu_complete_target_type : in std_ulogic_vector(0 to 1); + iu_xu_quiesce : out std_ulogic_vector(0 to 3); + xu_iu_single_instr_mode : in std_ulogic_vector(0 to 3); + xu_iu_need_hole : in std_ulogic; + xu_iu_xucr0_rel : in std_ulogic; + xu_iu_spr_ccr2_en_dcr : in std_ulogic; + + xu_iu_ex5_ppc_cpl : in std_ulogic_vector(0 to 3); + xu_iu_multdiv_done : in std_ulogic_vector(0 to 3); + iu_xu_is2_ucode_vld : out std_ulogic; + iu_xu_is2_vld : out std_ulogic; + iu_xu_is2_tid : out std_ulogic_vector(0 to 3); + iu_xu_is2_instr : out std_ulogic_vector(0 to 31); + iu_xu_is2_ta_vld : out std_ulogic; + iu_xu_is2_ta : out std_ulogic_vector(0 to 5); + iu_xu_is2_s1_vld : out std_ulogic; + iu_xu_is2_s1 : out std_ulogic_vector(0 to 5); + iu_xu_is2_s2_vld : out std_ulogic; + iu_xu_is2_s2 : out std_ulogic_vector(0 to 5); + iu_xu_is2_s3_vld : out std_ulogic; + iu_xu_is2_s3 : out std_ulogic_vector(0 to 5); + iu_xu_is2_pred_update : out std_ulogic; + iu_xu_is2_pred_taken_cnt : out std_ulogic_vector(0 to 1); + iu_xu_is2_gshare : out std_ulogic_vector(0 to 3); + iu_xu_is2_ifar : out eff_ifar; + iu_xu_is2_axu_ld_or_st : out std_ulogic; + iu_xu_is2_axu_store : out std_ulogic; + iu_xu_is2_axu_ldst_size : out std_ulogic_vector(0 to 5); + iu_xu_is2_axu_ldst_tag : out std_ulogic_vector(0 to 8); + iu_xu_is2_axu_ldst_indexed : out std_ulogic; + iu_xu_is2_axu_ldst_update : out std_ulogic; + iu_xu_is2_axu_ldst_extpid : out std_ulogic; + iu_xu_is2_axu_ldst_forcealign : out std_ulogic; + iu_xu_is2_axu_ldst_forceexcept : out std_ulogic; + iu_xu_is2_axu_mftgpr : out std_ulogic; + iu_xu_is2_axu_mffgpr : out std_ulogic; + iu_xu_is2_axu_movedp : out std_ulogic; + iu_xu_is2_axu_instr_type : out std_ulogic_vector(0 to 2); + iu_xu_is2_error : out std_ulogic_vector(0 to 2); + iu_xu_is2_is_ucode : out std_ulogic; + iu_xu_is2_match : out std_ulogic; + + iu_fu_is2_tid_decode : out std_ulogic_vector(0 to 3); + iu_fu_rf0_ucfmul : out std_ulogic; + iu_fu_rf0_instr : out std_ulogic_vector(0 to 31); + iu_fu_rf0_instr_v : out std_ulogic; + iu_fu_rf0_instr_match : out std_ulogic; + iu_fu_rf0_is_ucode : out std_ulogic; + iu_fu_rf0_fra : out std_ulogic_vector(0 to 6); + iu_fu_rf0_frb : out std_ulogic_vector(0 to 6); + iu_fu_rf0_frc : out std_ulogic_vector(0 to 6); + iu_fu_rf0_frt : out std_ulogic_vector(0 to 6); + iu_fu_rf0_fra_v : out std_ulogic; + iu_fu_rf0_frb_v : out std_ulogic; + iu_fu_rf0_frc_v : out std_ulogic; + iu_fu_rf0_tid : out std_ulogic_vector(0 to 1); + iu_fu_rf0_bypsel : out std_ulogic_vector(0 to 5); + iu_fu_rf0_ifar : out EFF_IFAR; + iu_fu_rf0_str_val : out std_ulogic; + iu_fu_rf0_ldst_val : out std_ulogic; + iu_fu_rf0_ldst_tid : out std_ulogic_vector(0 to 1); + iu_fu_rf0_ldst_tag : out std_ulogic_vector(0 to 8); + + fu_iu_uc_special : in std_ulogic_vector(0 to 3); + iu_fu_ex2_n_flush : out std_ulogic_vector(0 to 3); + + rtim_sl_thold_7 : in std_ulogic; + func_sl_thold_7 : in std_ulogic; + func_nsl_thold_7 : in std_ulogic; + ary_nsl_thold_7 : in std_ulogic; + sg_7 : in std_ulogic; + fce_7 : in std_ulogic; + rtim_sl_thold_6 : out std_ulogic; + func_sl_thold_6 : out std_ulogic; + func_nsl_thold_6 : out std_ulogic; + ary_nsl_thold_6 : out std_ulogic; + sg_6 : out std_ulogic; + fce_6 : out std_ulogic; + an_ac_scom_dch : in std_ulogic; + an_ac_scom_cch : in std_ulogic; + an_ac_checkstop : in std_ulogic; + an_ac_debug_stop : in std_ulogic; + an_ac_pm_thread_stop : in std_ulogic_vector(0 to 3); + an_ac_reset_1_complete : in std_ulogic; + an_ac_reset_2_complete : in std_ulogic; + an_ac_reset_3_complete : in std_ulogic; + an_ac_reset_wd_complete : in std_ulogic; + an_ac_abist_start_test : in std_ulogic; + ac_rp_trace_to_perfcntr : in std_ulogic_vector(0 to 7); + rp_pc_scom_dch_q : out std_ulogic; + rp_pc_scom_cch_q : out std_ulogic; + rp_pc_checkstop_q : out std_ulogic; + rp_pc_debug_stop_q : out std_ulogic; + rp_pc_pm_thread_stop_q : out std_ulogic_vector(0 to 3); + rp_pc_reset_1_complete_q : out std_ulogic; + rp_pc_reset_2_complete_q : out std_ulogic; + rp_pc_reset_3_complete_q : out std_ulogic; + rp_pc_reset_wd_complete_q : out std_ulogic; + rp_pc_abist_start_test_q : out std_ulogic; + rp_pc_trace_to_perfcntr_q : out std_ulogic_vector(0 to 7); + pc_rp_scom_dch : in std_ulogic; + pc_rp_scom_cch : in std_ulogic; + pc_rp_special_attn : in std_ulogic_vector(0 to 3); + pc_rp_checkstop : in std_ulogic_vector(0 to 2); + pc_rp_local_checkstop : in std_ulogic_vector(0 to 2); + pc_rp_recov_err : in std_ulogic_vector(0 to 2); + pc_rp_trace_error : in std_ulogic; + pc_rp_event_bus_enable : in std_ulogic; + pc_rp_event_bus : in std_ulogic_vector(0 to 7); + pc_rp_fu_bypass_events : in std_ulogic_vector(0 to 7); + pc_rp_iu_bypass_events : in std_ulogic_vector(0 to 7); + pc_rp_mm_bypass_events : in std_ulogic_vector(0 to 7); + pc_rp_lsu_bypass_events : in std_ulogic_vector(0 to 7); + pc_rp_pm_thread_running : in std_ulogic_vector(0 to 3); + pc_rp_power_managed : in std_ulogic; + pc_rp_rvwinkle_mode : in std_ulogic; + ac_an_scom_dch_q : out std_ulogic; + ac_an_scom_cch_q : out std_ulogic; + ac_an_special_attn_q : out std_ulogic_vector(0 to 3); + ac_an_checkstop_q : out std_ulogic_vector(0 to 2); + ac_an_local_checkstop_q : out std_ulogic_vector(0 to 2); + ac_an_recov_err_q : out std_ulogic_vector(0 to 2); + ac_an_trace_error_q : out std_ulogic; + rp_mm_event_bus_enable_q : out std_ulogic; + ac_an_event_bus_q : out std_ulogic_vector(0 to 7); + ac_an_fu_bypass_events_q : out std_ulogic_vector(0 to 7); + ac_an_iu_bypass_events_q : out std_ulogic_vector(0 to 7); + ac_an_mm_bypass_events_q : out std_ulogic_vector(0 to 7); + ac_an_lsu_bypass_events_q : out std_ulogic_vector(0 to 7); + ac_an_pm_thread_running_q : out std_ulogic_vector(0 to 3); + ac_an_power_managed_q : out std_ulogic; + ac_an_rvwinkle_mode_q : out std_ulogic; + + pc_func_scan_in : in std_ulogic_vector(0 to 1); + pc_func_scan_in_q : out std_ulogic_vector(0 to 1); + pc_func_scan_out : in std_ulogic; + pc_func_scan_out_q : out std_ulogic; + pc_bcfg_scan_in : in std_ulogic; + pc_bcfg_scan_in_q : out std_ulogic; + pc_dcfg_scan_in : in std_ulogic; + pc_dcfg_scan_in_q : out std_ulogic; + pc_bcfg_scan_out : in std_ulogic; + pc_bcfg_scan_out_q : out std_ulogic; + pc_ccfg_scan_out : in std_ulogic; + pc_ccfg_scan_out_q : out std_ulogic; + pc_dcfg_scan_out : in std_ulogic; + pc_dcfg_scan_out_q : out std_ulogic; + fu_abst_scan_in : in std_ulogic; + fu_abst_scan_in_q : out std_ulogic; + fu_abst_scan_out : in std_ulogic; + fu_abst_scan_out_q : out std_ulogic; + fu_ccfg_scan_out : in std_ulogic; + fu_ccfg_scan_out_q : out std_ulogic; + fu_bcfg_scan_out : in std_ulogic; + fu_bcfg_scan_out_q : out std_ulogic; + fu_dcfg_scan_out : in std_ulogic; + fu_dcfg_scan_out_q : out std_ulogic; + fu_func_scan_in : in std_ulogic_vector(0 to 3); + fu_func_scan_in_q : out std_ulogic_vector(0 to 3); + fu_func_scan_out : in std_ulogic_vector(0 to 3); + fu_func_scan_out_q : out std_ulogic_vector(0 to 3); + bx_abst_scan_in : in std_ulogic; + bx_abst_scan_in_q : out std_ulogic; + bx_abst_scan_out : in std_ulogic; + bx_abst_scan_out_q : out std_ulogic; + bx_func_scan_in : in std_ulogic_vector(0 to 1); + bx_func_scan_in_q : out std_ulogic_vector(0 to 1); + bx_func_scan_out : in std_ulogic_vector(0 to 1); + bx_func_scan_out_q : out std_ulogic_vector(0 to 1); + spare_func_scan_in : in std_ulogic_vector(0 to 3); + spare_func_scan_out_q : out std_ulogic_vector(0 to 3); + rp_abst_scan_in : in std_ulogic; + rp_func_scan_in : in std_ulogic; + rp_abst_scan_out : out std_ulogic; + rp_func_scan_out : out std_ulogic; + + bg_an_ac_func_scan_sn : in std_ulogic_vector(60 to 69); + bg_an_ac_abst_scan_sn : in std_ulogic_vector(10 to 11); + bg_an_ac_func_scan_sn_q : out std_ulogic_vector(60 to 69); + bg_an_ac_abst_scan_sn_q : out std_ulogic_vector(10 to 11); + + bg_ac_an_func_scan_ns : in std_ulogic_vector(60 to 69); + bg_ac_an_abst_scan_ns : in std_ulogic_vector(10 to 11); + bg_ac_an_func_scan_ns_q : out std_ulogic_vector(60 to 69); + bg_ac_an_abst_scan_ns_q : out std_ulogic_vector(10 to 11); + + bg_pc_l1p_abist_di_0 : in std_ulogic_vector(0 to 3); + bg_pc_l1p_abist_g8t1p_renb_0 : in std_ulogic; + bg_pc_l1p_abist_g8t_bw_0 : in std_ulogic; + bg_pc_l1p_abist_g8t_bw_1 : in std_ulogic; + bg_pc_l1p_abist_g8t_dcomp : in std_ulogic_vector(0 to 3); + bg_pc_l1p_abist_g8t_wenb : in std_ulogic; + bg_pc_l1p_abist_raddr_0 : in std_ulogic_vector(0 to 9); + bg_pc_l1p_abist_waddr_0 : in std_ulogic_vector(0 to 9); + bg_pc_l1p_abist_wl128_comp_ena : in std_ulogic; + bg_pc_l1p_abist_wl32_comp_ena : in std_ulogic; + bg_pc_l1p_abist_di_0_q : out std_ulogic_vector(0 to 3); + bg_pc_l1p_abist_g8t1p_renb_0_q : out std_ulogic; + bg_pc_l1p_abist_g8t_bw_0_q : out std_ulogic; + bg_pc_l1p_abist_g8t_bw_1_q : out std_ulogic; + bg_pc_l1p_abist_g8t_dcomp_q: out std_ulogic_vector(0 to 3); + bg_pc_l1p_abist_g8t_wenb_q : out std_ulogic; + bg_pc_l1p_abist_raddr_0_q : out std_ulogic_vector(0 to 9); + bg_pc_l1p_abist_waddr_0_q : out std_ulogic_vector(0 to 9); + bg_pc_l1p_abist_wl128_comp_ena_q : out std_ulogic; + bg_pc_l1p_abist_wl32_comp_ena_q : out std_ulogic; + + bg_pc_l1p_gptr_sl_thold_3 : in std_ulogic; + bg_pc_l1p_time_sl_thold_3 : in std_ulogic; + bg_pc_l1p_repr_sl_thold_3 : in std_ulogic; + bg_pc_l1p_abst_sl_thold_3 : in std_ulogic; + bg_pc_l1p_func_sl_thold_3 : in std_ulogic_vector(0 to 1); + bg_pc_l1p_func_slp_sl_thold_3 : in std_ulogic; + bg_pc_l1p_bolt_sl_thold_3 : in std_ulogic; + bg_pc_l1p_ary_nsl_thold_3 : in std_ulogic; + bg_pc_l1p_sg_3 : in std_ulogic_vector(0 to 1); + bg_pc_l1p_fce_3 : in std_ulogic; + bg_pc_l1p_bo_enable_3 : in std_ulogic; + bg_pc_l1p_gptr_sl_thold_2 : out std_ulogic; + bg_pc_l1p_time_sl_thold_2 : out std_ulogic; + bg_pc_l1p_repr_sl_thold_2 : out std_ulogic; + bg_pc_l1p_abst_sl_thold_2 : out std_ulogic; + bg_pc_l1p_func_sl_thold_2 : out std_ulogic_vector(0 to 1); + bg_pc_l1p_func_slp_sl_thold_2 : out std_ulogic; + bg_pc_l1p_bolt_sl_thold_2 : out std_ulogic; + bg_pc_l1p_ary_nsl_thold_2 : out std_ulogic; + bg_pc_l1p_sg_2 : out std_ulogic_vector(0 to 1); + bg_pc_l1p_fce_2 : out std_ulogic; + bg_pc_l1p_bo_enable_2 : out std_ulogic; + + + bg_pc_bo_unload_iiu : in std_ulogic; + bg_pc_bo_load_iiu : in std_ulogic; + bg_pc_bo_repair_iiu : in std_ulogic; + bg_pc_bo_reset_iiu : in std_ulogic; + bg_pc_bo_shdata_iiu : in std_ulogic; + bg_pc_bo_select_iiu : in std_ulogic_vector(0 to 10); + bg_pc_l1p_ccflush_dc_iiu : in std_ulogic; + bg_pc_l1p_abist_ena_dc_iiu : in std_ulogic; + bg_pc_l1p_abist_raw_dc_b_iiu : in std_ulogic; + + bg_pc_bo_unload_oiu : out std_ulogic; + bg_pc_bo_load_oiu : out std_ulogic; + bg_pc_bo_repair_oiu : out std_ulogic; + bg_pc_bo_reset_oiu : out std_ulogic; + bg_pc_bo_shdata_oiu : out std_ulogic; + bg_pc_bo_select_oiu : out std_ulogic_vector(0 to 10); + bg_pc_l1p_ccflush_dc_oiu : out std_ulogic; + bg_pc_l1p_abist_ena_dc_oiu : out std_ulogic; + bg_pc_l1p_abist_raw_dc_b_oiu : out std_ulogic; + + ac_an_abist_done_dc_iiu : in std_ulogic; + ac_an_psro_ringsig_iiu : in std_ulogic; + mm_pc_bo_fail_iiu : in std_ulogic_vector(0 to 4); + mm_pc_bo_diagout_iiu : in std_ulogic_vector(0 to 4); + mm_pc_event_data_iiu : in std_ulogic_vector(0 to 7); + + ac_an_abist_done_dc_oiu : out std_ulogic; + ac_an_psro_ringsig_oiu : out std_ulogic; + mm_pc_bo_fail_oiu : out std_ulogic_vector(0 to 4); + mm_pc_bo_diagout_oiu : out std_ulogic_vector(0 to 4); + mm_pc_event_data_oiu : out std_ulogic_vector(0 to 7); + + bg_pc_bo_fail_iiu : in std_ulogic_vector(0 to 10); + bg_pc_bo_diagout_iiu : in std_ulogic_vector(0 to 10); + + bg_pc_bo_fail_oiu : out std_ulogic_vector(0 to 10); + bg_pc_bo_diagout_oiu : out std_ulogic_vector(0 to 10); + + an_ac_abist_mode_dc_iiu : in std_ulogic; + an_ac_ccenable_dc_iiu : in std_ulogic; + an_ac_ccflush_dc_iiu : in std_ulogic; + an_ac_gsd_test_enable_dc_iiu : in std_ulogic; + an_ac_gsd_test_acmode_dc_iiu : in std_ulogic; + an_ac_lbist_ip_dc_iiu : in std_ulogic; + an_ac_lbist_ac_mode_dc_iiu : in std_ulogic; + an_ac_malf_alert_iiu : in std_ulogic; + an_ac_psro_enable_dc_iiu : in std_ulogic_vector(0 to 2); + an_ac_scan_type_dc_iiu : in std_ulogic_vector(0 to 8); + an_ac_scom_sat_id_iiu : in std_ulogic_vector(0 to 3); + + pc_mm_abist_dcomp_g6t_2r_iiu : in std_ulogic_vector(0 to 3); + pc_mm_abist_di_g6t_2r_iiu : in std_ulogic_vector(0 to 3); + pc_mm_abist_di_0_iiu : in std_ulogic_vector(0 to 3); + pc_mm_abist_ena_dc_iiu : in std_ulogic; + pc_mm_abist_g6t_r_wb_iiu : in std_ulogic; + pc_mm_abist_g8t_bw_0_iiu : in std_ulogic; + pc_mm_abist_g8t_bw_1_iiu : in std_ulogic; + pc_mm_abist_g8t_dcomp_iiu : in std_ulogic_vector(0 to 3); + pc_mm_abist_g8t_wenb_iiu : in std_ulogic; + pc_mm_abist_g8t1p_renb_0_iiu : in std_ulogic; + pc_mm_abist_raddr_0_iiu : in std_ulogic_vector(0 to 9); + pc_mm_abist_raw_dc_b_iiu : in std_ulogic; + pc_mm_abist_waddr_0_iiu : in std_ulogic_vector(0 to 9); + pc_mm_abist_wl128_comp_ena_iiu : in std_ulogic; + pc_mm_bo_enable_4_iiu : in std_ulogic; + pc_mm_bo_repair_iiu : in std_ulogic; + pc_mm_bo_reset_iiu : in std_ulogic; + pc_mm_bo_select_iiu : in std_ulogic_vector(0 to 4); + pc_mm_bo_shdata_iiu : in std_ulogic; + pc_mm_bo_unload_iiu : in std_ulogic; + pc_mm_ccflush_dc_iiu : in std_ulogic; + pc_mm_debug_mux1_ctrls_iiu : in std_ulogic_vector(0 to 15); + pc_mm_event_count_mode_iiu : in std_ulogic_vector(0 to 2); + pc_mm_event_mux_ctrls_iiu : in std_ulogic_vector(0 to 39); + pc_mm_trace_bus_enable_iiu : in std_ulogic; + + an_ac_abist_mode_dc_oiu : out std_ulogic; + an_ac_ccenable_dc_oiu : out std_ulogic; + an_ac_ccflush_dc_oiu : out std_ulogic; + an_ac_gsd_test_enable_dc_oiu : out std_ulogic; + an_ac_gsd_test_acmode_dc_oiu : out std_ulogic; + an_ac_lbist_ip_dc_oiu : out std_ulogic; + an_ac_lbist_ac_mode_dc_oiu : out std_ulogic; + an_ac_malf_alert_oiu : out std_ulogic; + an_ac_psro_enable_dc_oiu : out std_ulogic_vector(0 to 2); + an_ac_scan_type_dc_oiu : out std_ulogic_vector(0 to 8); + an_ac_scom_sat_id_oiu : out std_ulogic_vector(0 to 3); + + pc_mm_abist_dcomp_g6t_2r_oiu : out std_ulogic_vector(0 to 3); + pc_mm_abist_di_g6t_2r_oiu : out std_ulogic_vector(0 to 3); + pc_mm_abist_di_0_oiu : out std_ulogic_vector(0 to 3); + pc_mm_abist_ena_dc_oiu : out std_ulogic; + pc_mm_abist_g6t_r_wb_oiu : out std_ulogic; + pc_mm_abist_g8t_bw_0_oiu : out std_ulogic; + pc_mm_abist_g8t_bw_1_oiu : out std_ulogic; + pc_mm_abist_g8t_dcomp_oiu : out std_ulogic_vector(0 to 3); + pc_mm_abist_g8t_wenb_oiu : out std_ulogic; + pc_mm_abist_g8t1p_renb_0_oiu : out std_ulogic; + pc_mm_abist_raddr_0_oiu : out std_ulogic_vector(0 to 9); + pc_mm_abist_raw_dc_b_oiu : out std_ulogic; + pc_mm_abist_waddr_0_oiu : out std_ulogic_vector(0 to 9); + pc_mm_abist_wl128_comp_ena_oiu : out std_ulogic; + pc_mm_abst_sl_thold_3_oiu : out std_ulogic; + pc_mm_abst_slp_sl_thold_3_oiu : out std_ulogic; + pc_mm_ary_nsl_thold_3_oiu : out std_ulogic; + pc_mm_ary_slp_nsl_thold_3_oiu : out std_ulogic; + pc_mm_bo_enable_3_oiu : out std_ulogic; + pc_mm_bo_repair_oiu : out std_ulogic; + pc_mm_bo_reset_oiu : out std_ulogic; + pc_mm_bo_select_oiu : out std_ulogic_vector(0 to 4); + pc_mm_bo_shdata_oiu : out std_ulogic; + pc_mm_bo_unload_oiu : out std_ulogic; + pc_mm_bolt_sl_thold_3_oiu : out std_ulogic; + pc_mm_ccflush_dc_oiu : out std_ulogic; + pc_mm_cfg_sl_thold_3_oiu : out std_ulogic; + pc_mm_cfg_slp_sl_thold_3_oiu : out std_ulogic; + pc_mm_debug_mux1_ctrls_oiu : out std_ulogic_vector(0 to 15); + pc_mm_event_count_mode_oiu : out std_ulogic_vector(0 to 2); + pc_mm_event_mux_ctrls_oiu : out std_ulogic_vector(0 to 39); + pc_mm_fce_3_oiu : out std_ulogic; + pc_mm_func_nsl_thold_3_oiu : out std_ulogic; + pc_mm_func_sl_thold_3_oiu : out std_ulogic_vector(0 to 1); + pc_mm_func_slp_nsl_thold_3_oiu : out std_ulogic; + pc_mm_func_slp_sl_thold_3_oiu : out std_ulogic_vector(0 to 1); + pc_mm_gptr_sl_thold_3_oiu : out std_ulogic; + pc_mm_repr_sl_thold_3_oiu : out std_ulogic; + pc_mm_sg_3_oiu : out std_ulogic_vector(0 to 1); + pc_mm_time_sl_thold_3_oiu : out std_ulogic; + pc_mm_trace_bus_enable_oiu : out std_ulogic; + + an_ac_back_inv_oiu : out std_ulogic; + an_ac_back_inv_addr_oiu : out std_ulogic_vector(REAL_IFAR'left to 63); + an_ac_back_inv_target_bit1_oiu : out std_ulogic; + an_ac_back_inv_target_bit3_oiu : out std_ulogic; + an_ac_back_inv_target_bit4_oiu : out std_ulogic; + an_ac_atpg_en_dc_oiu : out std_ulogic; + an_ac_lbist_ary_wrt_thru_dc_oiu : out std_ulogic; + an_ac_lbist_en_dc_oiu : out std_ulogic; + an_ac_scan_diag_dc_oiu : out std_ulogic; + an_ac_scan_dis_dc_b_oiu : out std_ulogic; + an_ac_grffence_en_dc_oiu : out std_ulogic + +); +-- synopsys translate_off +-- synopsys translate_on +end iuq; +architecture iuq of iuq is +signal clkoff_b : std_ulogic_vector(0 to 3); +signal delay_lclkr : std_ulogic_vector(5 to 14); +signal mpw1_b : std_ulogic_vector(5 to 14); +signal pc_iu_sg_2 : std_ulogic_vector(0 to 3); +signal pc_iu_func_sl_thold_2 : std_ulogic_vector(0 to 3); +signal bp_ib_iu4_t0_val : std_ulogic_vector(0 to 3); +signal bp_ib_iu4_t1_val : std_ulogic_vector(0 to 3); +signal bp_ib_iu4_t2_val : std_ulogic_vector(0 to 3); +signal bp_ib_iu4_t3_val : std_ulogic_vector(0 to 3); +signal bp_ib_iu4_ifar_t0 : EFF_IFAR; +signal bp_ib_iu3_0_instr_t0 : std_ulogic_vector(0 to 31); +signal bp_ib_iu4_0_instr_t0 : std_ulogic_vector(32 to 43); +signal bp_ib_iu4_1_instr_t0 : std_ulogic_vector(0 to 43); +signal bp_ib_iu4_2_instr_t0 : std_ulogic_vector(0 to 43); +signal bp_ib_iu4_3_instr_t0 : std_ulogic_vector(0 to 43); +signal bp_ib_iu4_ifar_t1 : EFF_IFAR; +signal bp_ib_iu3_0_instr_t1 : std_ulogic_vector(0 to 31); +signal bp_ib_iu4_0_instr_t1 : std_ulogic_vector(32 to 43); +signal bp_ib_iu4_1_instr_t1 : std_ulogic_vector(0 to 43); +signal bp_ib_iu4_2_instr_t1 : std_ulogic_vector(0 to 43); +signal bp_ib_iu4_3_instr_t1 : std_ulogic_vector(0 to 43); +signal bp_ib_iu4_ifar_t2 : EFF_IFAR; +signal bp_ib_iu3_0_instr_t2 : std_ulogic_vector(0 to 31); +signal bp_ib_iu4_0_instr_t2 : std_ulogic_vector(32 to 43); +signal bp_ib_iu4_1_instr_t2 : std_ulogic_vector(0 to 43); +signal bp_ib_iu4_2_instr_t2 : std_ulogic_vector(0 to 43); +signal bp_ib_iu4_3_instr_t2 : std_ulogic_vector(0 to 43); +signal bp_ib_iu4_ifar_t3 : EFF_IFAR; +signal bp_ib_iu3_0_instr_t3 : std_ulogic_vector(0 to 31); +signal bp_ib_iu4_0_instr_t3 : std_ulogic_vector(32 to 43); +signal bp_ib_iu4_1_instr_t3 : std_ulogic_vector(0 to 43); +signal bp_ib_iu4_2_instr_t3 : std_ulogic_vector(0 to 43); +signal bp_ib_iu4_3_instr_t3 : std_ulogic_vector(0 to 43); +signal uc_ib_iu4_val : std_ulogic_vector(0 to 3); +signal uc_ib_iu4_ifar_t0 : std_ulogic_vector(62-uc_ifar to 61); +signal uc_ib_iu4_instr_t0 : std_ulogic_vector(0 to 36); +signal uc_ib_iu4_ifar_t1 : std_ulogic_vector(62-uc_ifar to 61); +signal uc_ib_iu4_instr_t1 : std_ulogic_vector(0 to 36); +signal uc_ib_iu4_ifar_t2 : std_ulogic_vector(62-uc_ifar to 61); +signal uc_ib_iu4_instr_t2 : std_ulogic_vector(0 to 36); +signal uc_ib_iu4_ifar_t3 : std_ulogic_vector(62-uc_ifar to 61); +signal uc_ib_iu4_instr_t3 : std_ulogic_vector(0 to 36); +signal uc_flush_tid : std_ulogic_vector(0 to 3); +signal rm_ib_iu4_val : std_ulogic_vector(0 to 3); +signal rm_ib_iu4_force_ram_t0 : std_ulogic; +signal rm_ib_iu4_instr_t0 : std_ulogic_vector(0 to 35); +signal rm_ib_iu4_force_ram_t1 : std_ulogic; +signal rm_ib_iu4_instr_t1 : std_ulogic_vector(0 to 35); +signal rm_ib_iu4_force_ram_t2 : std_ulogic; +signal rm_ib_iu4_instr_t2 : std_ulogic_vector(0 to 35); +signal rm_ib_iu4_force_ram_t3 : std_ulogic; +signal rm_ib_iu4_instr_t3 : std_ulogic_vector(0 to 35); +signal iu_au_ib1_instr_vld_t0 : std_ulogic; +signal iu_au_ib1_ifar_t0 : EFF_IFAR; +signal iu_au_ib1_data_t0 : std_ulogic_vector(0 to 49); +signal iu_au_ib1_instr_vld_t1 : std_ulogic; +signal iu_au_ib1_ifar_t1 : EFF_IFAR; +signal iu_au_ib1_data_t1 : std_ulogic_vector(0 to 49); +signal iu_au_ib1_instr_vld_t2 : std_ulogic; +signal iu_au_ib1_ifar_t2 : EFF_IFAR; +signal iu_au_ib1_data_t2 : std_ulogic_vector(0 to 49); +signal iu_au_ib1_instr_vld_t3 : std_ulogic; +signal iu_au_ib1_ifar_t3 : EFF_IFAR; +signal iu_au_ib1_data_t3 : std_ulogic_vector(0 to 49); +signal ib_ic_empty : std_ulogic_vector(0 to 3); +signal ib_ic_below_water : std_ulogic_vector(0 to 3); +signal ib_ic_iu5_redirect_tid : std_ulogic_vector(0 to 3); +signal iu_au_config_iucr_t0 : std_ulogic_vector(0 to 7); +signal iu_au_config_iucr_t1 : std_ulogic_vector(0 to 7); +signal iu_au_config_iucr_t2 : std_ulogic_vector(0 to 7); +signal iu_au_config_iucr_t3 : std_ulogic_vector(0 to 7); +signal spr_fiss_pri_rand : std_ulogic_vector(0 to 4); +signal spr_fiss_pri_rand_always : std_ulogic; +signal spr_fiss_pri_rand_flush : std_ulogic; +signal spr_fdep_ll_hold_t0 : std_ulogic; +signal spr_fdep_ll_hold_t1 : std_ulogic; +signal spr_fdep_ll_hold_t2 : std_ulogic; +signal spr_fdep_ll_hold_t3 : std_ulogic; +signal spr_issue_high_mask : std_ulogic_vector(0 to 3); +signal spr_issue_med_mask : std_ulogic_vector(0 to 3); +signal spr_fiss_count0_max : std_ulogic_vector(0 to 5); +signal spr_fiss_count1_max : std_ulogic_vector(0 to 5); +signal spr_fiss_count2_max : std_ulogic_vector(0 to 5); +signal spr_fiss_count3_max : std_ulogic_vector(0 to 5); +signal spr_dec_mask_pt_in_t0 : std_ulogic_vector(0 to 31); +signal spr_dec_mask_pt_in_t1 : std_ulogic_vector(0 to 31); +signal spr_dec_mask_pt_in_t2 : std_ulogic_vector(0 to 31); +signal spr_dec_mask_pt_in_t3 : std_ulogic_vector(0 to 31); +signal spr_dec_mask_pt_out_t0 : std_ulogic_vector(0 to 31); +signal spr_dec_mask_pt_out_t1 : std_ulogic_vector(0 to 31); +signal spr_dec_mask_pt_out_t2 : std_ulogic_vector(0 to 31); +signal spr_dec_mask_pt_out_t3 : std_ulogic_vector(0 to 31); +signal spr_dec_match_t0 : std_ulogic_vector(0 to 31); +signal spr_dec_match_t1 : std_ulogic_vector(0 to 31); +signal spr_dec_match_t2 : std_ulogic_vector(0 to 31); +signal spr_dec_match_t3 : std_ulogic_vector(0 to 31); +signal ic_fdep_load_quiesce : std_ulogic_vector(0 to 3); +signal ic_fdep_icbi_ack : std_ulogic_vector(0 to 3); +signal iu_xu_is2_vld_internal : std_ulogic; +signal iu_xu_is2_tid_internal : std_ulogic_vector(0 to 3); +signal iu_xu_is2_instr_internal : std_ulogic_vector(0 to 31); +signal iu_xu_is2_error_internal : std_ulogic_vector(0 to 2); +signal iu_xu_is2_pred_update_internal : std_ulogic; +signal iu_xu_is2_pred_taken_cnt_internal : std_ulogic_vector(0 to 1); +signal iu_xu_is2_ifar_internal : EFF_IFAR; +signal iu_xu_is2_axu_store_internal : std_ulogic; +signal fiss_uc_is2_ucode_vld : std_ulogic; +signal fiss_uc_is2_tid : std_ulogic_vector(0 to 3); +signal fiss_uc_is2_instr : std_ulogic_vector(0 to 31); +signal fiss_uc_is2_2ucode : std_ulogic; +signal fiss_uc_is2_2ucode_type : std_ulogic; +signal iuq_mi_scan_out : std_ulogic_vector(0 to 1); +signal iuq_bp_scan_out : std_ulogic; +signal iuq_b0_scan_in : std_ulogic; +signal iuq_b0_scan_out : std_ulogic; +signal iuq_b1_scan_in : std_ulogic; +signal iuq_b1_scan_out : std_ulogic; +signal iuq_b2_scan_in : std_ulogic; +signal iuq_b2_scan_out : std_ulogic; +signal iuq_b3_scan_in : std_ulogic; +signal iuq_b3_scan_out : std_ulogic; +signal iuq_s0_scan_in : std_ulogic; +signal iuq_s0_scan_out : std_ulogic; +signal iuq_s1_scan_in : std_ulogic; +signal iuq_s1_scan_out : std_ulogic; +signal iuq_s2_scan_in : std_ulogic; +signal iuq_s2_scan_out : std_ulogic; +signal iuq_s3_scan_in : std_ulogic; +signal iuq_s3_scan_out : std_ulogic; +signal iuq_fi_scan_in : std_ulogic; +signal iuq_fi_scan_out : std_ulogic; +signal iuq_ai_scan_in : std_ulogic; +signal iuq_ai_scan_out : std_ulogic; +signal ib_perf_event_t0 : std_ulogic_vector(0 to 1); +signal ib_perf_event_t1 : std_ulogic_vector(0 to 1); +signal ib_perf_event_t2 : std_ulogic_vector(0 to 1); +signal ib_perf_event_t3 : std_ulogic_vector(0 to 1); +signal fdep_perf_event_pt_in_t0 : std_ulogic_vector(0 to 11); +signal fdep_perf_event_pt_in_t1 : std_ulogic_vector(0 to 11); +signal fdep_perf_event_pt_in_t2 : std_ulogic_vector(0 to 11); +signal fdep_perf_event_pt_in_t3 : std_ulogic_vector(0 to 11); +signal fdep_perf_event_pt_out_t0: std_ulogic_vector(0 to 11); +signal fdep_perf_event_pt_out_t1: std_ulogic_vector(0 to 11); +signal fdep_perf_event_pt_out_t2: std_ulogic_vector(0 to 11); +signal fdep_perf_event_pt_out_t3: std_ulogic_vector(0 to 11); +signal fiss_perf_event_t0 : std_ulogic_vector(0 to 7); +signal fiss_perf_event_t1 : std_ulogic_vector(0 to 7); +signal fiss_perf_event_t2 : std_ulogic_vector(0 to 7); +signal fiss_perf_event_t3 : std_ulogic_vector(0 to 7); +signal fdec_ibuf_stall_t0 : std_ulogic; +signal fdec_ibuf_stall_t1 : std_ulogic; +signal fdec_ibuf_stall_t2 : std_ulogic; +signal fdec_ibuf_stall_t3 : std_ulogic; +signal fiss_dbg_data : std_ulogic_vector(0 to 87); +signal fdep_dbg_data_pt_in : std_ulogic_vector(0 to 87); +signal fdep_dbg_data_pt_out : std_ulogic_vector(0 to 87); +signal ib_dbg_data : std_ulogic_vector(0 to 63); +signal fu_iss_dbg_data : std_ulogic_vector(0 to 23); +signal axu_dbg_data_t0 : std_ulogic_vector(0 to 37); +signal axu_dbg_data_t1 : std_ulogic_vector(0 to 37); +signal axu_dbg_data_t2 : std_ulogic_vector(0 to 37); +signal axu_dbg_data_t3 : std_ulogic_vector(0 to 37); +signal an_ac_scan_dis_dc_b_oif : std_ulogic_vector(0 to 3); +signal an_ac_back_inv_oif : std_ulogic; +signal an_ac_back_inv_target_oif: std_ulogic_vector(1 to 1); +signal an_ac_sync_ack_oif : std_ulogic_vector(0 to 3); +signal mm_iu_barrier_done_oif : std_ulogic_vector(0 to 3); +signal iu_func_scan_in_q : std_ulogic_vector(0 to 4); +signal iu_func_scan_out : std_ulogic_vector(0 to 7); +signal unused : std_ulogic_vector(6 to 14); +-- synopsys translate_off +-- synopsys translate_on +begin +unused(6 to 8) <= pc_iu_abist_waddr_0(0 to 2); +unused(9 to 10) <= pc_iu_abist_raddr_0(0 to 1); +unused(11) <= xu_iu_ex5_loadmiss_target(0); +unused(12 to 13)<= xu_iu_ex5_loadmiss_target(7 to 8); +unused(14) <= xu_iu_ex5_loadmiss_target_type(1); +iuq_ifetch0 : entity work.iuq_ifetch +generic map(expand_type => expand_type, + a2mode => a2mode, + regmode => regmode, + threads => threads, + ucode_mode => ucode_mode, + bcfg_epn_0to15 => bcfg_epn_0to15, + bcfg_epn_16to31 => bcfg_epn_16to31, + bcfg_epn_32to47 => bcfg_epn_32to47, + bcfg_epn_48to51 => bcfg_epn_48to51, + bcfg_rpn_22to31 => bcfg_rpn_22to31, + bcfg_rpn_32to47 => bcfg_rpn_32to47, + bcfg_rpn_48to51 => bcfg_rpn_48to51, + uc_ifar => uc_ifar) +port map( + vcs => vcs, + vdd => vdd, + gnd => gnd, + nclk => nclk, + tc_ac_ccflush_dc => tc_ac_ccflush_dc, + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b, + an_ac_scan_diag_dc => an_ac_scan_diag_dc, + pc_iu_gptr_sl_thold_4 => pc_iu_gptr_sl_thold_4, + pc_iu_time_sl_thold_4 => pc_iu_time_sl_thold_4, + pc_iu_repr_sl_thold_4 => pc_iu_repr_sl_thold_4, + pc_iu_abst_sl_thold_4 => pc_iu_abst_sl_thold_4, + pc_iu_abst_slp_sl_thold_4 => pc_iu_abst_slp_sl_thold_4, + pc_iu_bolt_sl_thold_4 => pc_iu_bolt_sl_thold_4, + pc_iu_regf_slp_sl_thold_4 => pc_iu_regf_slp_sl_thold_4, + pc_iu_func_sl_thold_4 => pc_iu_func_sl_thold_4, + pc_iu_func_slp_sl_thold_4 => pc_iu_func_slp_sl_thold_4, + pc_iu_cfg_sl_thold_4 => pc_iu_cfg_sl_thold_4, + pc_iu_cfg_slp_sl_thold_4 => pc_iu_cfg_slp_sl_thold_4, + pc_iu_func_nsl_thold_4 => pc_iu_func_nsl_thold_4, + pc_iu_func_slp_nsl_thold_4 => pc_iu_func_slp_nsl_thold_4, + pc_iu_ary_nsl_thold_4 => pc_iu_ary_nsl_thold_4, + pc_iu_ary_slp_nsl_thold_4 => pc_iu_ary_slp_nsl_thold_4, + pc_iu_sg_4 => pc_iu_sg_4, + pc_iu_fce_4 => pc_iu_fce_4, + pc_iu_abist_dcomp_g6t_2r => pc_iu_abist_dcomp_g6t_2r, + pc_iu_abist_di_0 => pc_iu_abist_di_0, + pc_iu_abist_di_g6t_2r => pc_iu_abist_di_g6t_2r, + pc_iu_abist_ena_dc => pc_iu_abist_ena_dc, + pc_iu_abist_g6t_bw => pc_iu_abist_g6t_bw, + pc_iu_abist_g6t_r_wb => pc_iu_abist_g6t_r_wb, + pc_iu_abist_g8t1p_renb_0 => pc_iu_abist_g8t1p_renb_0, + pc_iu_abist_g8t_bw_0 => pc_iu_abist_g8t_bw_0, + pc_iu_abist_g8t_bw_1 => pc_iu_abist_g8t_bw_1, + pc_iu_abist_g8t_dcomp => pc_iu_abist_g8t_dcomp, + pc_iu_abist_g8t_wenb => pc_iu_abist_g8t_wenb, + pc_iu_abist_raddr_0 => pc_iu_abist_raddr_0(2 to 9), + pc_iu_abist_raw_dc_b => pc_iu_abist_raw_dc_b, + pc_iu_abist_waddr_0 => pc_iu_abist_waddr_0(3 to 9), + pc_iu_abist_wl256_comp_ena => pc_iu_abist_wl256_comp_ena, + pc_iu_abist_wl64_comp_ena => pc_iu_abist_wl64_comp_ena, + pc_iu_abist_wl128_comp_ena => pc_iu_abist_wl128_comp_ena, + an_ac_lbist_ary_wrt_thru_dc=> an_ac_lbist_ary_wrt_thru_dc, + an_ac_lbist_en_dc => an_ac_lbist_en_dc, + an_ac_atpg_en_dc => an_ac_atpg_en_dc, + an_ac_grffence_en_dc => an_ac_grffence_en_dc, + pc_iu_bo_enable_4 => pc_iu_bo_enable_4, + pc_iu_bo_reset => pc_iu_bo_reset, + pc_iu_bo_unload => pc_iu_bo_unload, + pc_iu_bo_repair => pc_iu_bo_repair, + pc_iu_bo_shdata => pc_iu_bo_shdata, + pc_iu_bo_select => pc_iu_bo_select, + iu_pc_bo_fail => iu_pc_bo_fail, + iu_pc_bo_diagout => iu_pc_bo_diagout, + iu_pc_err_icache_parity => iu_pc_err_icache_parity, + iu_pc_err_icachedir_parity => iu_pc_err_icachedir_parity, + iu_pc_err_icachedir_multihit => iu_pc_err_icachedir_multihit, + iu_pc_err_ucode_illegal => iu_pc_err_ucode_illegal, + pc_iu_inj_icache_parity => pc_iu_inj_icache_parity, + pc_iu_inj_icachedir_parity => pc_iu_inj_icachedir_parity, + pc_iu_inj_icachedir_multihit => pc_iu_inj_icachedir_multihit, + pc_iu_trace_bus_enable => pc_iu_trace_bus_enable, + pc_iu_debug_mux1_ctrls => pc_iu_debug_mux1_ctrls, + pc_iu_debug_mux2_ctrls => pc_iu_debug_mux2_ctrls, + debug_data_in => debug_data_in, + trace_triggers_in => trace_triggers_in, + debug_data_out => debug_data_out, + trace_triggers_out => trace_triggers_out, + pc_iu_event_mux_ctrls => pc_iu_event_mux_ctrls, + pc_iu_event_count_mode => pc_iu_event_count_mode, + pc_iu_event_bus_enable => pc_iu_event_bus_enable, + iu_pc_event_data => iu_pc_event_data, + pc_iu_init_reset => pc_iu_init_reset, + gptr_scan_in => gptr_scan_in, + time_scan_in => time_scan_in, + repr_scan_in => repr_scan_in, + abst_scan_in => abst_scan_in, + func_scan_in => func_scan_in, + ccfg_scan_in => ccfg_scan_in, + bcfg_scan_in => bcfg_scan_in, + dcfg_scan_in => dcfg_scan_in, + regf_scan_in => regf_scan_in, + gptr_scan_out => gptr_scan_out, + time_scan_out => time_scan_out, + repr_scan_out => repr_scan_out, + abst_scan_out => abst_scan_out, + func_scan_out => func_scan_out, + ccfg_scan_out => ccfg_scan_out, + bcfg_scan_out => bcfg_scan_out, + dcfg_scan_out => dcfg_scan_out, + regf_scan_out => regf_scan_out, + iuq_mi_scan_out => iuq_mi_scan_out, + iuq_bp_scan_out => iuq_bp_scan_out, + slowspr_val_in => slowspr_val_in, + slowspr_rw_in => slowspr_rw_in, + slowspr_etid_in => slowspr_etid_in, + slowspr_addr_in => slowspr_addr_in, + slowspr_data_in => slowspr_data_in, + slowspr_done_in => slowspr_done_in, + slowspr_val_out => slowspr_val_out, + slowspr_rw_out => slowspr_rw_out, + slowspr_etid_out => slowspr_etid_out, + slowspr_addr_out => slowspr_addr_out, + slowspr_data_out => slowspr_data_out, + slowspr_done_out => slowspr_done_out, + xu_iu_run_thread => xu_iu_run_thread, + xu_iu_flush => xu_iu_l_flush, + xu_iu_iu0_flush_ifar0 => xu_iu_iu0_flush_ifar0, + xu_iu_iu0_flush_ifar1 => xu_iu_iu0_flush_ifar1, + xu_iu_iu0_flush_ifar2 => xu_iu_iu0_flush_ifar2, + xu_iu_iu0_flush_ifar3 => xu_iu_iu0_flush_ifar3, + xu_iu_flush_2ucode => xu_iu_flush_2ucode, + xu_iu_flush_2ucode_type => xu_iu_flush_2ucode_type, + xu_iu_msr_cm => xu_iu_msr_cm, + xu_iu_ex6_icbi_val => xu_iu_ex6_icbi_val, + xu_iu_ex6_icbi_addr => xu_iu_ex6_icbi_addr, + xu_iu_ici => xu_iu_ici, + iu_xu_request => iu_xu_request, + iu_xu_thread => iu_xu_thread, + iu_xu_ra => iu_xu_ra, + iu_xu_wimge => iu_xu_wimge, + iu_xu_userdef => iu_xu_userdef, + an_ac_reld_data_vld => an_ac_reld_data_vld, + an_ac_reld_core_tag => an_ac_reld_core_tag, + an_ac_reld_qw => an_ac_reld_qw, + an_ac_reld_data => an_ac_reld_data, + an_ac_reld_ecc_err => an_ac_reld_ecc_err, + an_ac_reld_ecc_err_ue => an_ac_reld_ecc_err_ue, + an_ac_back_inv => an_ac_back_inv, + an_ac_back_inv_addr => an_ac_back_inv_addr, + an_ac_back_inv_target_iiu_a=> an_ac_back_inv_target_iiu_a, + an_ac_back_inv_target_iiu_b=> an_ac_back_inv_target_iiu_b, + an_ac_icbi_ack => an_ac_icbi_ack, + an_ac_icbi_ack_thread => an_ac_icbi_ack_thread, + iu_mm_ierat_req => iu_mm_ierat_req, + iu_mm_ierat_epn => iu_mm_ierat_epn, + iu_mm_ierat_thdid => iu_mm_ierat_thdid, + iu_mm_ierat_state => iu_mm_ierat_state, + iu_mm_ierat_tid => iu_mm_ierat_tid, + iu_mm_ierat_flush => iu_mm_ierat_flush, + mm_iu_ierat_rel_val => mm_iu_ierat_rel_val, + mm_iu_ierat_rel_data => mm_iu_ierat_rel_data, + mm_iu_ierat_snoop_coming => mm_iu_ierat_snoop_coming, + mm_iu_ierat_snoop_val => mm_iu_ierat_snoop_val, + mm_iu_ierat_snoop_attr => mm_iu_ierat_snoop_attr, + mm_iu_ierat_snoop_vpn => mm_iu_ierat_snoop_vpn, + iu_mm_ierat_snoop_ack => iu_mm_ierat_snoop_ack, + mm_iu_ierat_pid0 => mm_iu_ierat_pid0, + mm_iu_ierat_pid1 => mm_iu_ierat_pid1, + mm_iu_ierat_pid2 => mm_iu_ierat_pid2, + mm_iu_ierat_pid3 => mm_iu_ierat_pid3, + mm_iu_ierat_mmucr0_0 => mm_iu_ierat_mmucr0_0, + mm_iu_ierat_mmucr0_1 => mm_iu_ierat_mmucr0_1, + mm_iu_ierat_mmucr0_2 => mm_iu_ierat_mmucr0_2, + mm_iu_ierat_mmucr0_3 => mm_iu_ierat_mmucr0_3, + iu_mm_ierat_mmucr0 => iu_mm_ierat_mmucr0, + iu_mm_ierat_mmucr0_we => iu_mm_ierat_mmucr0_we, + mm_iu_ierat_mmucr1 => mm_iu_ierat_mmucr1, + iu_mm_ierat_mmucr1 => iu_mm_ierat_mmucr1, + iu_mm_ierat_mmucr1_we => iu_mm_ierat_mmucr1_we, + iu_mm_lmq_empty => iu_mm_lmq_empty, + xu_iu_ex1_rb => xu_iu_ex1_rb, + xu_rf1_flush => xu_wl_rf1_flush, + xu_ex1_flush => xu_wl_ex1_flush, + xu_ex2_flush => xu_wl_ex2_flush, + xu_ex3_flush => xu_wl_ex3_flush, + xu_ex4_flush => xu_wl_ex4_flush, + xu_ex5_flush => xu_wl_ex5_flush, + xu_iu_ex4_rs_data => xu_iu_ex4_rs_data, + xu_iu_hid_mmu_mode => xu_iu_hid_mmu_mode, + xu_iu_msr_hv => xu_iu_msr_hv, + xu_iu_msr_is => xu_iu_msr_is, + xu_iu_msr_pr => xu_iu_msr_pr, + xu_iu_spr_ccr2_ifratsc => xu_iu_spr_ccr2_ifratsc, + xu_iu_spr_ccr2_ifrat => xu_iu_spr_ccr2_ifrat, + xu_iu_xucr4_mmu_mchk => xu_iu_xucr4_mmu_mchk, + xu_iu_rf1_val => xu_iu_rf1_val, + xu_iu_rf1_is_eratre => xu_iu_rf1_is_eratre, + xu_iu_rf1_is_eratsx => xu_iu_rf1_is_eratsx, + xu_iu_rf1_is_eratwe => xu_iu_rf1_is_eratwe, + xu_iu_rf1_is_eratilx => xu_iu_rf1_is_eratilx, + xu_iu_ex1_is_isync => xu_iu_ex1_is_isync, + xu_iu_ex1_is_csync => xu_iu_ex1_is_csync, + xu_iu_rf1_ws => xu_iu_rf1_ws, + xu_iu_rf1_t => xu_iu_rf1_t, + xu_iu_ex1_ra_entry => xu_iu_ex1_ra_entry, + xu_iu_ex1_rs_is => xu_iu_ex1_rs_is, + iu_xu_ex4_tlb_data => iu_xu_ex4_tlb_data, + iu_xu_ierat_ex3_par_err => iu_xu_ierat_ex3_par_err, + iu_xu_ierat_ex4_par_err => iu_xu_ierat_ex4_par_err, + iu_xu_ierat_ex2_flush_req => iu_xu_ierat_ex2_flush_req, + xu_iu_ex5_ifar => xu_iu_ex5_ifar, + xu_iu_ex5_tid => xu_iu_ex5_tid, + xu_iu_ex5_val => xu_iu_ex5_val, + xu_iu_ex5_br_update => xu_iu_ex5_br_update, + xu_iu_ex5_br_hist => xu_iu_ex5_br_hist, + xu_iu_ex5_br_taken => xu_iu_ex5_br_taken, + xu_iu_ex5_bclr => xu_iu_ex5_bclr, + xu_iu_ex5_getNIA => xu_iu_ex5_getNIA, + xu_iu_ex5_lk => xu_iu_ex5_lk, + xu_iu_ex5_bh => xu_iu_ex5_bh, + xu_iu_ex5_gshare => xu_iu_ex5_gshare, + pc_iu_ram_instr => pc_iu_ram_instr, + pc_iu_ram_instr_ext => pc_iu_ram_instr_ext, + pc_iu_ram_force_cmplt => pc_iu_ram_force_cmplt, + xu_iu_ram_issue => xu_iu_ram_issue, + xu_iu_ex6_pri => xu_iu_ex6_pri, + xu_iu_ex6_pri_val => xu_iu_ex6_pri_val, + xu_iu_raise_iss_pri => xu_iu_raise_iss_pri, + xu_iu_msr_gs => xu_iu_msr_gs, + xu_iu_ucode_restart => xu_iu_ucode_restart, + xu_iu_spr_xer0 => xu_iu_spr_xer0, + xu_iu_spr_xer1 => xu_iu_spr_xer1, + xu_iu_spr_xer2 => xu_iu_spr_xer2, + xu_iu_spr_xer3 => xu_iu_spr_xer3, + xu_iu_uc_flush_ifar0 => xu_iu_uc_flush_ifar0, + xu_iu_uc_flush_ifar1 => xu_iu_uc_flush_ifar1, + xu_iu_uc_flush_ifar2 => xu_iu_uc_flush_ifar2, + xu_iu_uc_flush_ifar3 => xu_iu_uc_flush_ifar3, + rtim_sl_thold_7 => rtim_sl_thold_7, + func_sl_thold_7 => func_sl_thold_7, + func_nsl_thold_7 => func_nsl_thold_7, + ary_nsl_thold_7 => ary_nsl_thold_7, + sg_7 => sg_7, + fce_7 => fce_7, + rtim_sl_thold_6 => rtim_sl_thold_6, + func_sl_thold_6 => func_sl_thold_6, + func_nsl_thold_6 => func_nsl_thold_6, + ary_nsl_thold_6 => ary_nsl_thold_6, + sg_6 => sg_6, + fce_6 => fce_6, + an_ac_scom_dch => an_ac_scom_dch, + an_ac_scom_cch => an_ac_scom_cch, + an_ac_checkstop => an_ac_checkstop, + an_ac_debug_stop => an_ac_debug_stop, + an_ac_pm_thread_stop => an_ac_pm_thread_stop, + an_ac_reset_1_complete => an_ac_reset_1_complete, + an_ac_reset_2_complete => an_ac_reset_2_complete, + an_ac_reset_3_complete => an_ac_reset_3_complete, + an_ac_reset_wd_complete => an_ac_reset_wd_complete, + an_ac_abist_start_test => an_ac_abist_start_test, + ac_rp_trace_to_perfcntr => ac_rp_trace_to_perfcntr, + rp_pc_scom_dch_q => rp_pc_scom_dch_q, + rp_pc_scom_cch_q => rp_pc_scom_cch_q, + rp_pc_checkstop_q => rp_pc_checkstop_q, + rp_pc_debug_stop_q => rp_pc_debug_stop_q, + rp_pc_pm_thread_stop_q => rp_pc_pm_thread_stop_q, + rp_pc_reset_1_complete_q => rp_pc_reset_1_complete_q, + rp_pc_reset_2_complete_q => rp_pc_reset_2_complete_q, + rp_pc_reset_3_complete_q => rp_pc_reset_3_complete_q, + rp_pc_reset_wd_complete_q => rp_pc_reset_wd_complete_q, + rp_pc_abist_start_test_q => rp_pc_abist_start_test_q, + rp_pc_trace_to_perfcntr_q => rp_pc_trace_to_perfcntr_q, + pc_rp_scom_dch => pc_rp_scom_dch, + pc_rp_scom_cch => pc_rp_scom_cch, + pc_rp_special_attn => pc_rp_special_attn, + pc_rp_checkstop => pc_rp_checkstop, + pc_rp_local_checkstop => pc_rp_local_checkstop, + pc_rp_recov_err => pc_rp_recov_err, + pc_rp_trace_error => pc_rp_trace_error, + pc_rp_event_bus_enable => pc_rp_event_bus_enable, + pc_rp_event_bus => pc_rp_event_bus, + pc_rp_fu_bypass_events => pc_rp_fu_bypass_events, + pc_rp_iu_bypass_events => pc_rp_iu_bypass_events, + pc_rp_mm_bypass_events => pc_rp_mm_bypass_events, + pc_rp_lsu_bypass_events => pc_rp_lsu_bypass_events, + pc_rp_pm_thread_running => pc_rp_pm_thread_running, + pc_rp_power_managed => pc_rp_power_managed, + pc_rp_rvwinkle_mode => pc_rp_rvwinkle_mode, + ac_an_scom_dch_q => ac_an_scom_dch_q, + ac_an_scom_cch_q => ac_an_scom_cch_q, + ac_an_special_attn_q => ac_an_special_attn_q, + ac_an_checkstop_q => ac_an_checkstop_q, + ac_an_local_checkstop_q => ac_an_local_checkstop_q, + ac_an_recov_err_q => ac_an_recov_err_q, + ac_an_trace_error_q => ac_an_trace_error_q, + rp_mm_event_bus_enable_q => rp_mm_event_bus_enable_q, + ac_an_event_bus_q => ac_an_event_bus_q, + ac_an_fu_bypass_events_q => ac_an_fu_bypass_events_q, + ac_an_iu_bypass_events_q => ac_an_iu_bypass_events_q, + ac_an_mm_bypass_events_q => ac_an_mm_bypass_events_q, + ac_an_lsu_bypass_events_q => ac_an_lsu_bypass_events_q, + ac_an_pm_thread_running_q => ac_an_pm_thread_running_q, + ac_an_power_managed_q => ac_an_power_managed_q, + ac_an_rvwinkle_mode_q => ac_an_rvwinkle_mode_q, + pc_func_scan_in => pc_func_scan_in, + pc_func_scan_in_q => pc_func_scan_in_q, + pc_func_scan_out => pc_func_scan_out, + pc_func_scan_out_q => pc_func_scan_out_q, + pc_bcfg_scan_in => pc_bcfg_scan_in, + pc_bcfg_scan_in_q => pc_bcfg_scan_in_q, + pc_dcfg_scan_in => pc_dcfg_scan_in, + pc_dcfg_scan_in_q => pc_dcfg_scan_in_q, + pc_bcfg_scan_out => pc_bcfg_scan_out, + pc_bcfg_scan_out_q => pc_bcfg_scan_out_q, + pc_ccfg_scan_out => pc_ccfg_scan_out, + pc_ccfg_scan_out_q => pc_ccfg_scan_out_q, + pc_dcfg_scan_out => pc_dcfg_scan_out, + pc_dcfg_scan_out_q => pc_dcfg_scan_out_q, + fu_abst_scan_in => fu_abst_scan_in, + fu_abst_scan_in_q => fu_abst_scan_in_q, + fu_abst_scan_out => fu_abst_scan_out, + fu_abst_scan_out_q => fu_abst_scan_out_q, + fu_ccfg_scan_out => fu_ccfg_scan_out, + fu_ccfg_scan_out_q => fu_ccfg_scan_out_q, + fu_bcfg_scan_out => fu_bcfg_scan_out, + fu_bcfg_scan_out_q => fu_bcfg_scan_out_q, + fu_dcfg_scan_out => fu_dcfg_scan_out, + fu_dcfg_scan_out_q => fu_dcfg_scan_out_q, + fu_func_scan_in => fu_func_scan_in, + fu_func_scan_in_q => fu_func_scan_in_q, + fu_func_scan_out => fu_func_scan_out, + fu_func_scan_out_q => fu_func_scan_out_q, + bx_abst_scan_in => bx_abst_scan_in, + bx_abst_scan_in_q => bx_abst_scan_in_q, + bx_abst_scan_out => bx_abst_scan_out, + bx_abst_scan_out_q => bx_abst_scan_out_q, + bx_func_scan_in => bx_func_scan_in, + bx_func_scan_in_q => bx_func_scan_in_q, + bx_func_scan_out => bx_func_scan_out, + bx_func_scan_out_q => bx_func_scan_out_q, + iu_func_scan_in_q => iu_func_scan_in_q, + iu_func_scan_out => iu_func_scan_out, + spare_func_scan_in => spare_func_scan_in, + spare_func_scan_out_q => spare_func_scan_out_q, + rp_abst_scan_in => rp_abst_scan_in, + rp_func_scan_in => rp_func_scan_in, + rp_abst_scan_out => rp_abst_scan_out, + rp_func_scan_out => rp_func_scan_out, + bg_an_ac_func_scan_sn => bg_an_ac_func_scan_sn, + bg_an_ac_abst_scan_sn => bg_an_ac_abst_scan_sn, + bg_an_ac_func_scan_sn_q => bg_an_ac_func_scan_sn_q, + bg_an_ac_abst_scan_sn_q => bg_an_ac_abst_scan_sn_q, + bg_ac_an_func_scan_ns => bg_ac_an_func_scan_ns, + bg_ac_an_abst_scan_ns => bg_ac_an_abst_scan_ns, + bg_ac_an_func_scan_ns_q => bg_ac_an_func_scan_ns_q, + bg_ac_an_abst_scan_ns_q => bg_ac_an_abst_scan_ns_q, + bg_pc_l1p_abist_di_0 => bg_pc_l1p_abist_di_0, + bg_pc_l1p_abist_g8t1p_renb_0 => bg_pc_l1p_abist_g8t1p_renb_0, + bg_pc_l1p_abist_g8t_bw_0 => bg_pc_l1p_abist_g8t_bw_0, + bg_pc_l1p_abist_g8t_bw_1 => bg_pc_l1p_abist_g8t_bw_1, + bg_pc_l1p_abist_g8t_dcomp => bg_pc_l1p_abist_g8t_dcomp, + bg_pc_l1p_abist_g8t_wenb => bg_pc_l1p_abist_g8t_wenb, + bg_pc_l1p_abist_raddr_0 => bg_pc_l1p_abist_raddr_0, + bg_pc_l1p_abist_waddr_0 => bg_pc_l1p_abist_waddr_0, + bg_pc_l1p_abist_wl128_comp_ena => bg_pc_l1p_abist_wl128_comp_ena, + bg_pc_l1p_abist_wl32_comp_ena => bg_pc_l1p_abist_wl32_comp_ena, + bg_pc_l1p_abist_di_0_q => bg_pc_l1p_abist_di_0_q, + bg_pc_l1p_abist_g8t1p_renb_0_q => bg_pc_l1p_abist_g8t1p_renb_0_q, + bg_pc_l1p_abist_g8t_bw_0_q => bg_pc_l1p_abist_g8t_bw_0_q, + bg_pc_l1p_abist_g8t_bw_1_q => bg_pc_l1p_abist_g8t_bw_1_q, + bg_pc_l1p_abist_g8t_dcomp_q=> bg_pc_l1p_abist_g8t_dcomp_q, + bg_pc_l1p_abist_g8t_wenb_q => bg_pc_l1p_abist_g8t_wenb_q, + bg_pc_l1p_abist_raddr_0_q => bg_pc_l1p_abist_raddr_0_q, + bg_pc_l1p_abist_waddr_0_q => bg_pc_l1p_abist_waddr_0_q, + bg_pc_l1p_abist_wl128_comp_ena_q => bg_pc_l1p_abist_wl128_comp_ena_q, + bg_pc_l1p_abist_wl32_comp_ena_q => bg_pc_l1p_abist_wl32_comp_ena_q, + bg_pc_l1p_gptr_sl_thold_3 => bg_pc_l1p_gptr_sl_thold_3, + bg_pc_l1p_time_sl_thold_3 => bg_pc_l1p_time_sl_thold_3, + bg_pc_l1p_repr_sl_thold_3 => bg_pc_l1p_repr_sl_thold_3, + bg_pc_l1p_abst_sl_thold_3 => bg_pc_l1p_abst_sl_thold_3, + bg_pc_l1p_func_sl_thold_3 => bg_pc_l1p_func_sl_thold_3, + bg_pc_l1p_func_slp_sl_thold_3 => bg_pc_l1p_func_slp_sl_thold_3, + bg_pc_l1p_bolt_sl_thold_3 => bg_pc_l1p_bolt_sl_thold_3, + bg_pc_l1p_ary_nsl_thold_3 => bg_pc_l1p_ary_nsl_thold_3, + bg_pc_l1p_sg_3 => bg_pc_l1p_sg_3, + bg_pc_l1p_fce_3 => bg_pc_l1p_fce_3, + bg_pc_l1p_bo_enable_3 => bg_pc_l1p_bo_enable_3, + bg_pc_l1p_gptr_sl_thold_2 => bg_pc_l1p_gptr_sl_thold_2, + bg_pc_l1p_time_sl_thold_2 => bg_pc_l1p_time_sl_thold_2, + bg_pc_l1p_repr_sl_thold_2 => bg_pc_l1p_repr_sl_thold_2, + bg_pc_l1p_abst_sl_thold_2 => bg_pc_l1p_abst_sl_thold_2, + bg_pc_l1p_func_sl_thold_2 => bg_pc_l1p_func_sl_thold_2, + bg_pc_l1p_func_slp_sl_thold_2 => bg_pc_l1p_func_slp_sl_thold_2, + bg_pc_l1p_bolt_sl_thold_2 => bg_pc_l1p_bolt_sl_thold_2, + bg_pc_l1p_ary_nsl_thold_2 => bg_pc_l1p_ary_nsl_thold_2, + bg_pc_l1p_sg_2 => bg_pc_l1p_sg_2, + bg_pc_l1p_fce_2 => bg_pc_l1p_fce_2, + bg_pc_l1p_bo_enable_2 => bg_pc_l1p_bo_enable_2, + bg_pc_bo_unload_iiu => bg_pc_bo_unload_iiu, + bg_pc_bo_load_iiu => bg_pc_bo_load_iiu, + bg_pc_bo_repair_iiu => bg_pc_bo_repair_iiu, + bg_pc_bo_reset_iiu => bg_pc_bo_reset_iiu, + bg_pc_bo_shdata_iiu => bg_pc_bo_shdata_iiu, + bg_pc_bo_select_iiu => bg_pc_bo_select_iiu, + bg_pc_l1p_ccflush_dc_iiu => bg_pc_l1p_ccflush_dc_iiu, + bg_pc_l1p_abist_ena_dc_iiu => bg_pc_l1p_abist_ena_dc_iiu, + bg_pc_l1p_abist_raw_dc_b_iiu => bg_pc_l1p_abist_raw_dc_b_iiu, + bg_pc_bo_unload_oiu => bg_pc_bo_unload_oiu, + bg_pc_bo_load_oiu => bg_pc_bo_load_oiu, + bg_pc_bo_repair_oiu => bg_pc_bo_repair_oiu, + bg_pc_bo_reset_oiu => bg_pc_bo_reset_oiu, + bg_pc_bo_shdata_oiu => bg_pc_bo_shdata_oiu, + bg_pc_bo_select_oiu => bg_pc_bo_select_oiu, + bg_pc_l1p_ccflush_dc_oiu => bg_pc_l1p_ccflush_dc_oiu, + bg_pc_l1p_abist_ena_dc_oiu => bg_pc_l1p_abist_ena_dc_oiu, + bg_pc_l1p_abist_raw_dc_b_oiu => bg_pc_l1p_abist_raw_dc_b_oiu, + ac_an_abist_done_dc_iiu => ac_an_abist_done_dc_iiu, + ac_an_psro_ringsig_iiu => ac_an_psro_ringsig_iiu, + mm_pc_bo_fail_iiu => mm_pc_bo_fail_iiu, + mm_pc_bo_diagout_iiu => mm_pc_bo_diagout_iiu, + mm_pc_event_data_iiu => mm_pc_event_data_iiu, + ac_an_abist_done_dc_oiu => ac_an_abist_done_dc_oiu, + ac_an_psro_ringsig_oiu => ac_an_psro_ringsig_oiu, + mm_pc_bo_fail_oiu => mm_pc_bo_fail_oiu, + mm_pc_bo_diagout_oiu => mm_pc_bo_diagout_oiu, + mm_pc_event_data_oiu => mm_pc_event_data_oiu, + bg_pc_bo_fail_iiu => bg_pc_bo_fail_iiu, + bg_pc_bo_diagout_iiu => bg_pc_bo_diagout_iiu, + bg_pc_bo_fail_oiu => bg_pc_bo_fail_oiu, + bg_pc_bo_diagout_oiu => bg_pc_bo_diagout_oiu, + an_ac_abist_mode_dc_iiu => an_ac_abist_mode_dc_iiu, + an_ac_ccenable_dc_iiu => an_ac_ccenable_dc_iiu, + an_ac_ccflush_dc_iiu => an_ac_ccflush_dc_iiu, + an_ac_gsd_test_enable_dc_iiu => an_ac_gsd_test_enable_dc_iiu, + an_ac_gsd_test_acmode_dc_iiu => an_ac_gsd_test_acmode_dc_iiu, + an_ac_lbist_ip_dc_iiu => an_ac_lbist_ip_dc_iiu, + an_ac_lbist_ac_mode_dc_iiu => an_ac_lbist_ac_mode_dc_iiu, + an_ac_malf_alert_iiu => an_ac_malf_alert_iiu, + an_ac_psro_enable_dc_iiu => an_ac_psro_enable_dc_iiu, + an_ac_scan_type_dc_iiu => an_ac_scan_type_dc_iiu, + an_ac_scom_sat_id_iiu => an_ac_scom_sat_id_iiu, + pc_mm_abist_dcomp_g6t_2r_iiu => pc_mm_abist_dcomp_g6t_2r_iiu, + pc_mm_abist_di_g6t_2r_iiu => pc_mm_abist_di_g6t_2r_iiu, + pc_mm_abist_di_0_iiu => pc_mm_abist_di_0_iiu, + pc_mm_abist_ena_dc_iiu => pc_mm_abist_ena_dc_iiu, + pc_mm_abist_g6t_r_wb_iiu => pc_mm_abist_g6t_r_wb_iiu, + pc_mm_abist_g8t_bw_0_iiu => pc_mm_abist_g8t_bw_0_iiu, + pc_mm_abist_g8t_bw_1_iiu => pc_mm_abist_g8t_bw_1_iiu, + pc_mm_abist_g8t_dcomp_iiu => pc_mm_abist_g8t_dcomp_iiu, + pc_mm_abist_g8t_wenb_iiu => pc_mm_abist_g8t_wenb_iiu, + pc_mm_abist_g8t1p_renb_0_iiu => pc_mm_abist_g8t1p_renb_0_iiu, + pc_mm_abist_raddr_0_iiu => pc_mm_abist_raddr_0_iiu, + pc_mm_abist_raw_dc_b_iiu => pc_mm_abist_raw_dc_b_iiu, + pc_mm_abist_waddr_0_iiu => pc_mm_abist_waddr_0_iiu, + pc_mm_abist_wl128_comp_ena_iiu => pc_mm_abist_wl128_comp_ena_iiu, + pc_mm_bo_enable_4_iiu => pc_mm_bo_enable_4_iiu, + pc_mm_bo_repair_iiu => pc_mm_bo_repair_iiu, + pc_mm_bo_reset_iiu => pc_mm_bo_reset_iiu, + pc_mm_bo_select_iiu => pc_mm_bo_select_iiu, + pc_mm_bo_shdata_iiu => pc_mm_bo_shdata_iiu, + pc_mm_bo_unload_iiu => pc_mm_bo_unload_iiu, + pc_mm_ccflush_dc_iiu => pc_mm_ccflush_dc_iiu, + pc_mm_debug_mux1_ctrls_iiu => pc_mm_debug_mux1_ctrls_iiu, + pc_mm_event_count_mode_iiu => pc_mm_event_count_mode_iiu, + pc_mm_event_mux_ctrls_iiu => pc_mm_event_mux_ctrls_iiu, + pc_mm_trace_bus_enable_iiu => pc_mm_trace_bus_enable_iiu, + an_ac_abist_mode_dc_oiu => an_ac_abist_mode_dc_oiu, + an_ac_ccenable_dc_oiu => an_ac_ccenable_dc_oiu, + an_ac_ccflush_dc_oiu => an_ac_ccflush_dc_oiu, + an_ac_gsd_test_enable_dc_oiu => an_ac_gsd_test_enable_dc_oiu, + an_ac_gsd_test_acmode_dc_oiu => an_ac_gsd_test_acmode_dc_oiu, + an_ac_lbist_ip_dc_oiu => an_ac_lbist_ip_dc_oiu, + an_ac_lbist_ac_mode_dc_oiu => an_ac_lbist_ac_mode_dc_oiu, + an_ac_malf_alert_oiu => an_ac_malf_alert_oiu, + an_ac_psro_enable_dc_oiu => an_ac_psro_enable_dc_oiu, + an_ac_scan_type_dc_oiu => an_ac_scan_type_dc_oiu, + an_ac_scom_sat_id_oiu => an_ac_scom_sat_id_oiu, + pc_mm_abist_dcomp_g6t_2r_oiu => pc_mm_abist_dcomp_g6t_2r_oiu, + pc_mm_abist_di_g6t_2r_oiu => pc_mm_abist_di_g6t_2r_oiu, + pc_mm_abist_di_0_oiu => pc_mm_abist_di_0_oiu, + pc_mm_abist_ena_dc_oiu => pc_mm_abist_ena_dc_oiu, + pc_mm_abist_g6t_r_wb_oiu => pc_mm_abist_g6t_r_wb_oiu, + pc_mm_abist_g8t_bw_0_oiu => pc_mm_abist_g8t_bw_0_oiu, + pc_mm_abist_g8t_bw_1_oiu => pc_mm_abist_g8t_bw_1_oiu, + pc_mm_abist_g8t_dcomp_oiu => pc_mm_abist_g8t_dcomp_oiu, + pc_mm_abist_g8t_wenb_oiu => pc_mm_abist_g8t_wenb_oiu, + pc_mm_abist_g8t1p_renb_0_oiu => pc_mm_abist_g8t1p_renb_0_oiu, + pc_mm_abist_raddr_0_oiu => pc_mm_abist_raddr_0_oiu, + pc_mm_abist_raw_dc_b_oiu => pc_mm_abist_raw_dc_b_oiu, + pc_mm_abist_waddr_0_oiu => pc_mm_abist_waddr_0_oiu, + pc_mm_abist_wl128_comp_ena_oiu => pc_mm_abist_wl128_comp_ena_oiu, + pc_mm_abst_sl_thold_3_oiu => pc_mm_abst_sl_thold_3_oiu, + pc_mm_abst_slp_sl_thold_3_oiu => pc_mm_abst_slp_sl_thold_3_oiu, + pc_mm_ary_nsl_thold_3_oiu => pc_mm_ary_nsl_thold_3_oiu, + pc_mm_ary_slp_nsl_thold_3_oiu => pc_mm_ary_slp_nsl_thold_3_oiu, + pc_mm_bo_enable_3_oiu => pc_mm_bo_enable_3_oiu, + pc_mm_bo_repair_oiu => pc_mm_bo_repair_oiu, + pc_mm_bo_reset_oiu => pc_mm_bo_reset_oiu, + pc_mm_bo_select_oiu => pc_mm_bo_select_oiu, + pc_mm_bo_shdata_oiu => pc_mm_bo_shdata_oiu, + pc_mm_bo_unload_oiu => pc_mm_bo_unload_oiu, + pc_mm_bolt_sl_thold_3_oiu => pc_mm_bolt_sl_thold_3_oiu, + pc_mm_ccflush_dc_oiu => pc_mm_ccflush_dc_oiu, + pc_mm_cfg_sl_thold_3_oiu => pc_mm_cfg_sl_thold_3_oiu, + pc_mm_cfg_slp_sl_thold_3_oiu => pc_mm_cfg_slp_sl_thold_3_oiu, + pc_mm_debug_mux1_ctrls_oiu => pc_mm_debug_mux1_ctrls_oiu, + pc_mm_event_count_mode_oiu => pc_mm_event_count_mode_oiu, + pc_mm_event_mux_ctrls_oiu => pc_mm_event_mux_ctrls_oiu, + pc_mm_fce_3_oiu => pc_mm_fce_3_oiu, + pc_mm_func_nsl_thold_3_oiu => pc_mm_func_nsl_thold_3_oiu, + pc_mm_func_sl_thold_3_oiu => pc_mm_func_sl_thold_3_oiu, + pc_mm_func_slp_nsl_thold_3_oiu => pc_mm_func_slp_nsl_thold_3_oiu, + pc_mm_func_slp_sl_thold_3_oiu => pc_mm_func_slp_sl_thold_3_oiu, + pc_mm_gptr_sl_thold_3_oiu => pc_mm_gptr_sl_thold_3_oiu, + pc_mm_repr_sl_thold_3_oiu => pc_mm_repr_sl_thold_3_oiu, + pc_mm_sg_3_oiu => pc_mm_sg_3_oiu, + pc_mm_time_sl_thold_3_oiu => pc_mm_time_sl_thold_3_oiu, + pc_mm_trace_bus_enable_oiu => pc_mm_trace_bus_enable_oiu, + an_ac_back_inv_oiu => an_ac_back_inv_oiu, + an_ac_back_inv_addr_oiu => an_ac_back_inv_addr_oiu, + an_ac_back_inv_target_bit1_oiu => an_ac_back_inv_target_bit1_oiu, + an_ac_back_inv_target_bit3_oiu => an_ac_back_inv_target_bit3_oiu, + an_ac_back_inv_target_bit4_oiu => an_ac_back_inv_target_bit4_oiu, + an_ac_atpg_en_dc_oiu => an_ac_atpg_en_dc_oiu, + an_ac_lbist_ary_wrt_thru_dc_oiu => an_ac_lbist_ary_wrt_thru_dc_oiu, + an_ac_lbist_en_dc_oiu => an_ac_lbist_en_dc_oiu, + an_ac_scan_diag_dc_oiu => an_ac_scan_diag_dc_oiu, + an_ac_scan_dis_dc_b_oiu => an_ac_scan_dis_dc_b_oiu, + an_ac_grffence_en_dc_oiu => an_ac_grffence_en_dc_oiu, + an_ac_sync_ack => an_ac_sync_ack, + mm_iu_barrier_done => mm_iu_barrier_done, + an_ac_scan_dis_dc_b_oif => an_ac_scan_dis_dc_b_oif, + an_ac_back_inv_oif => an_ac_back_inv_oif, + an_ac_back_inv_target_oif => an_ac_back_inv_target_oif, + an_ac_sync_ack_oif => an_ac_sync_ack_oif, + mm_iu_barrier_done_oif => mm_iu_barrier_done_oif, + pc_iu_sg_2 => pc_iu_sg_2, + pc_iu_func_sl_thold_2 => pc_iu_func_sl_thold_2, + clkoff_b => clkoff_b, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + fiss_dbg_data => fiss_dbg_data, + fdep_dbg_data => fdep_dbg_data_pt_out, + ib_dbg_data => ib_dbg_data, + fu_iss_dbg_data => fu_iss_dbg_data, + axu_dbg_data_t0 => axu_dbg_data_t0, + axu_dbg_data_t1 => axu_dbg_data_t1, + axu_dbg_data_t2 => axu_dbg_data_t2, + axu_dbg_data_t3 => axu_dbg_data_t3, + ib_perf_event_t0 => ib_perf_event_t0, + ib_perf_event_t1 => ib_perf_event_t1, + ib_perf_event_t2 => ib_perf_event_t2, + ib_perf_event_t3 => ib_perf_event_t3, + fdep_perf_event_t0 => fdep_perf_event_pt_out_t0, + fdep_perf_event_t1 => fdep_perf_event_pt_out_t1, + fdep_perf_event_t2 => fdep_perf_event_pt_out_t2, + fdep_perf_event_t3 => fdep_perf_event_pt_out_t3, + fiss_perf_event_t0 => fiss_perf_event_t0, + fiss_perf_event_t1 => fiss_perf_event_t1, + fiss_perf_event_t2 => fiss_perf_event_t2, + fiss_perf_event_t3 => fiss_perf_event_t3, + ib_ic_empty => ib_ic_empty, + ib_ic_below_water => ib_ic_below_water, + ib_ic_iu5_redirect_tid => ib_ic_iu5_redirect_tid, + bp_ib_iu4_t0_val => bp_ib_iu4_t0_val, + bp_ib_iu4_t1_val => bp_ib_iu4_t1_val, + bp_ib_iu4_t2_val => bp_ib_iu4_t2_val, + bp_ib_iu4_t3_val => bp_ib_iu4_t3_val, + bp_ib_iu4_ifar_t0 => bp_ib_iu4_ifar_t0, + bp_ib_iu3_0_instr_t0 => bp_ib_iu3_0_instr_t0, + bp_ib_iu4_0_instr_t0 => bp_ib_iu4_0_instr_t0, + bp_ib_iu4_1_instr_t0 => bp_ib_iu4_1_instr_t0, + bp_ib_iu4_2_instr_t0 => bp_ib_iu4_2_instr_t0, + bp_ib_iu4_3_instr_t0 => bp_ib_iu4_3_instr_t0, + bp_ib_iu4_ifar_t1 => bp_ib_iu4_ifar_t1, + bp_ib_iu3_0_instr_t1 => bp_ib_iu3_0_instr_t1, + bp_ib_iu4_0_instr_t1 => bp_ib_iu4_0_instr_t1, + bp_ib_iu4_1_instr_t1 => bp_ib_iu4_1_instr_t1, + bp_ib_iu4_2_instr_t1 => bp_ib_iu4_2_instr_t1, + bp_ib_iu4_3_instr_t1 => bp_ib_iu4_3_instr_t1, + bp_ib_iu4_ifar_t2 => bp_ib_iu4_ifar_t2, + bp_ib_iu3_0_instr_t2 => bp_ib_iu3_0_instr_t2, + bp_ib_iu4_0_instr_t2 => bp_ib_iu4_0_instr_t2, + bp_ib_iu4_1_instr_t2 => bp_ib_iu4_1_instr_t2, + bp_ib_iu4_2_instr_t2 => bp_ib_iu4_2_instr_t2, + bp_ib_iu4_3_instr_t2 => bp_ib_iu4_3_instr_t2, + bp_ib_iu4_ifar_t3 => bp_ib_iu4_ifar_t3, + bp_ib_iu3_0_instr_t3 => bp_ib_iu3_0_instr_t3, + bp_ib_iu4_0_instr_t3 => bp_ib_iu4_0_instr_t3, + bp_ib_iu4_1_instr_t3 => bp_ib_iu4_1_instr_t3, + bp_ib_iu4_2_instr_t3 => bp_ib_iu4_2_instr_t3, + bp_ib_iu4_3_instr_t3 => bp_ib_iu4_3_instr_t3, + uc_ib_iu4_val => uc_ib_iu4_val, + uc_ib_iu4_ifar_t0 => uc_ib_iu4_ifar_t0, + uc_ib_iu4_instr_t0 => uc_ib_iu4_instr_t0, + uc_ib_iu4_ifar_t1 => uc_ib_iu4_ifar_t1, + uc_ib_iu4_instr_t1 => uc_ib_iu4_instr_t1, + uc_ib_iu4_ifar_t2 => uc_ib_iu4_ifar_t2, + uc_ib_iu4_instr_t2 => uc_ib_iu4_instr_t2, + uc_ib_iu4_ifar_t3 => uc_ib_iu4_ifar_t3, + uc_ib_iu4_instr_t3 => uc_ib_iu4_instr_t3, + rm_ib_iu4_val => rm_ib_iu4_val, + rm_ib_iu4_force_ram_t0 => rm_ib_iu4_force_ram_t0, + rm_ib_iu4_instr_t0 => rm_ib_iu4_instr_t0, + rm_ib_iu4_force_ram_t1 => rm_ib_iu4_force_ram_t1, + rm_ib_iu4_instr_t1 => rm_ib_iu4_instr_t1, + rm_ib_iu4_force_ram_t2 => rm_ib_iu4_force_ram_t2, + rm_ib_iu4_instr_t2 => rm_ib_iu4_instr_t2, + rm_ib_iu4_force_ram_t3 => rm_ib_iu4_force_ram_t3, + rm_ib_iu4_instr_t3 => rm_ib_iu4_instr_t3, + iu_au_config_iucr_t0 => iu_au_config_iucr_t0, + iu_au_config_iucr_t1 => iu_au_config_iucr_t1, + iu_au_config_iucr_t2 => iu_au_config_iucr_t2, + iu_au_config_iucr_t3 => iu_au_config_iucr_t3, + spr_issue_high_mask => spr_issue_high_mask, + spr_issue_med_mask => spr_issue_med_mask, + spr_fiss_count0_max => spr_fiss_count0_max, + spr_fiss_count1_max => spr_fiss_count1_max, + spr_fiss_count2_max => spr_fiss_count2_max, + spr_fiss_count3_max => spr_fiss_count3_max, + spr_fiss_pri_rand => spr_fiss_pri_rand, + spr_fiss_pri_rand_always => spr_fiss_pri_rand_always, + spr_fiss_pri_rand_flush => spr_fiss_pri_rand_flush, + spr_dec_mask_t0 => spr_dec_mask_pt_in_t0, + spr_dec_mask_t1 => spr_dec_mask_pt_in_t1, + spr_dec_mask_t2 => spr_dec_mask_pt_in_t2, + spr_dec_mask_t3 => spr_dec_mask_pt_in_t3, + spr_dec_match_t0 => spr_dec_match_t0, + spr_dec_match_t1 => spr_dec_match_t1, + spr_dec_match_t2 => spr_dec_match_t2, + spr_dec_match_t3 => spr_dec_match_t3, + spr_fdep_ll_hold_t0 => spr_fdep_ll_hold_t0, + spr_fdep_ll_hold_t1 => spr_fdep_ll_hold_t1, + spr_fdep_ll_hold_t2 => spr_fdep_ll_hold_t2, + spr_fdep_ll_hold_t3 => spr_fdep_ll_hold_t3, + ic_fdep_load_quiesce => ic_fdep_load_quiesce, + ic_fdep_icbi_ack => ic_fdep_icbi_ack, + fiss_uc_is2_ucode_vld => fiss_uc_is2_ucode_vld, + fiss_uc_is2_tid => fiss_uc_is2_tid, + fiss_uc_is2_instr => fiss_uc_is2_instr, + fiss_uc_is2_2ucode => fiss_uc_is2_2ucode, + fiss_uc_is2_2ucode_type => fiss_uc_is2_2ucode_type, + uc_flush_tid => uc_flush_tid +); +iuq_ib_buff_wrap0 : entity work.iuq_ib_buff_wrap +generic map(expand_type => expand_type, + uc_ifar => uc_ifar) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_iu_func_sl_thold_2 => pc_iu_func_sl_thold_2, + pc_iu_sg_2 => pc_iu_sg_2, + clkoff_b => clkoff_b, + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b_oif, + tc_ac_ccflush_dc => tc_ac_ccflush_dc, + delay_lclkr => delay_lclkr(5 to 8), + mpw1_b => mpw1_b(5 to 8), + iuq_b0_scan_in => iuq_b0_scan_in, + iuq_b0_scan_out => iuq_b0_scan_out, + iuq_b1_scan_in => iuq_b1_scan_in, + iuq_b1_scan_out => iuq_b1_scan_out, + iuq_b2_scan_in => iuq_b2_scan_in, + iuq_b2_scan_out => iuq_b2_scan_out, + iuq_b3_scan_in => iuq_b3_scan_in, + iuq_b3_scan_out => iuq_b3_scan_out, + + spr_dec_mask_pt_in_t0 => spr_dec_mask_pt_in_t0, + spr_dec_mask_pt_in_t1 => spr_dec_mask_pt_in_t1, + spr_dec_mask_pt_in_t2 => spr_dec_mask_pt_in_t2, + spr_dec_mask_pt_in_t3 => spr_dec_mask_pt_in_t3, + spr_dec_mask_pt_out_t0 => spr_dec_mask_pt_out_t0, + spr_dec_mask_pt_out_t1 => spr_dec_mask_pt_out_t1, + spr_dec_mask_pt_out_t2 => spr_dec_mask_pt_out_t2, + spr_dec_mask_pt_out_t3 => spr_dec_mask_pt_out_t3, + fdep_dbg_data_pt_in => fdep_dbg_data_pt_in, + fdep_dbg_data_pt_out => fdep_dbg_data_pt_out, + fdep_perf_event_pt_in_t0 => fdep_perf_event_pt_in_t0, + fdep_perf_event_pt_in_t1 => fdep_perf_event_pt_in_t1, + fdep_perf_event_pt_in_t2 => fdep_perf_event_pt_in_t2, + fdep_perf_event_pt_in_t3 => fdep_perf_event_pt_in_t3, + fdep_perf_event_pt_out_t0 => fdep_perf_event_pt_out_t0, + fdep_perf_event_pt_out_t1 => fdep_perf_event_pt_out_t1, + fdep_perf_event_pt_out_t2 => fdep_perf_event_pt_out_t2, + fdep_perf_event_pt_out_t3 => fdep_perf_event_pt_out_t3, + + pc_iu_trace_bus_enable => pc_iu_trace_bus_enable, + pc_iu_event_bus_enable => pc_iu_event_bus_enable, + ib_dbg_data => ib_dbg_data, + ib_perf_event_t0 => ib_perf_event_t0, + ib_perf_event_t1 => ib_perf_event_t1, + ib_perf_event_t2 => ib_perf_event_t2, + ib_perf_event_t3 => ib_perf_event_t3, + xu_iu_flush => xu_iu_u_flush, + uc_flush_tid => uc_flush_tid, + fdec_ibuf_stall_t0 => fdec_ibuf_stall_t0, + fdec_ibuf_stall_t1 => fdec_ibuf_stall_t1, + fdec_ibuf_stall_t2 => fdec_ibuf_stall_t2, + fdec_ibuf_stall_t3 => fdec_ibuf_stall_t3, + ib_ic_below_water => ib_ic_below_water, + ib_ic_empty => ib_ic_empty, + bp_ib_iu4_t0_val => bp_ib_iu4_t0_val, + bp_ib_iu4_t1_val => bp_ib_iu4_t1_val, + bp_ib_iu4_t2_val => bp_ib_iu4_t2_val, + bp_ib_iu4_t3_val => bp_ib_iu4_t3_val, + bp_ib_iu4_ifar_t0 => bp_ib_iu4_ifar_t0, + bp_ib_iu3_0_instr_t0 => bp_ib_iu3_0_instr_t0, + bp_ib_iu4_0_instr_t0 => bp_ib_iu4_0_instr_t0, + bp_ib_iu4_1_instr_t0 => bp_ib_iu4_1_instr_t0, + bp_ib_iu4_2_instr_t0 => bp_ib_iu4_2_instr_t0, + bp_ib_iu4_3_instr_t0 => bp_ib_iu4_3_instr_t0, + bp_ib_iu4_ifar_t1 => bp_ib_iu4_ifar_t1, + bp_ib_iu3_0_instr_t1 => bp_ib_iu3_0_instr_t1, + bp_ib_iu4_0_instr_t1 => bp_ib_iu4_0_instr_t1, + bp_ib_iu4_1_instr_t1 => bp_ib_iu4_1_instr_t1, + bp_ib_iu4_2_instr_t1 => bp_ib_iu4_2_instr_t1, + bp_ib_iu4_3_instr_t1 => bp_ib_iu4_3_instr_t1, + bp_ib_iu4_ifar_t2 => bp_ib_iu4_ifar_t2, + bp_ib_iu3_0_instr_t2 => bp_ib_iu3_0_instr_t2, + bp_ib_iu4_0_instr_t2 => bp_ib_iu4_0_instr_t2, + bp_ib_iu4_1_instr_t2 => bp_ib_iu4_1_instr_t2, + bp_ib_iu4_2_instr_t2 => bp_ib_iu4_2_instr_t2, + bp_ib_iu4_3_instr_t2 => bp_ib_iu4_3_instr_t2, + bp_ib_iu4_ifar_t3 => bp_ib_iu4_ifar_t3, + bp_ib_iu3_0_instr_t3 => bp_ib_iu3_0_instr_t3, + bp_ib_iu4_0_instr_t3 => bp_ib_iu4_0_instr_t3, + bp_ib_iu4_1_instr_t3 => bp_ib_iu4_1_instr_t3, + bp_ib_iu4_2_instr_t3 => bp_ib_iu4_2_instr_t3, + bp_ib_iu4_3_instr_t3 => bp_ib_iu4_3_instr_t3, + uc_ib_iu4_val => uc_ib_iu4_val, + uc_ib_iu4_ifar_t0 => uc_ib_iu4_ifar_t0, + uc_ib_iu4_instr_t0 => uc_ib_iu4_instr_t0, + uc_ib_iu4_ifar_t1 => uc_ib_iu4_ifar_t1, + uc_ib_iu4_instr_t1 => uc_ib_iu4_instr_t1, + uc_ib_iu4_ifar_t2 => uc_ib_iu4_ifar_t2, + uc_ib_iu4_instr_t2 => uc_ib_iu4_instr_t2, + uc_ib_iu4_ifar_t3 => uc_ib_iu4_ifar_t3, + uc_ib_iu4_instr_t3 => uc_ib_iu4_instr_t3, + rm_ib_iu4_val => rm_ib_iu4_val, + rm_ib_iu4_force_ram_t0 => rm_ib_iu4_force_ram_t0, + rm_ib_iu4_instr_t0 => rm_ib_iu4_instr_t0, + rm_ib_iu4_force_ram_t1 => rm_ib_iu4_force_ram_t1, + rm_ib_iu4_instr_t1 => rm_ib_iu4_instr_t1, + rm_ib_iu4_force_ram_t2 => rm_ib_iu4_force_ram_t2, + rm_ib_iu4_instr_t2 => rm_ib_iu4_instr_t2, + rm_ib_iu4_force_ram_t3 => rm_ib_iu4_force_ram_t3, + rm_ib_iu4_instr_t3 => rm_ib_iu4_instr_t3, + ib_ic_iu5_redirect_tid => ib_ic_iu5_redirect_tid, + iu_au_ib1_instr_vld_t0 => iu_au_ib1_instr_vld_t0, + iu_au_ib1_instr_vld_t1 => iu_au_ib1_instr_vld_t1, + iu_au_ib1_instr_vld_t2 => iu_au_ib1_instr_vld_t2, + iu_au_ib1_instr_vld_t3 => iu_au_ib1_instr_vld_t3, + iu_au_ib1_ifar_t0 => iu_au_ib1_ifar_t0, + iu_au_ib1_ifar_t1 => iu_au_ib1_ifar_t1, + iu_au_ib1_ifar_t2 => iu_au_ib1_ifar_t2, + iu_au_ib1_ifar_t3 => iu_au_ib1_ifar_t3, + iu_au_ib1_data_t0 => iu_au_ib1_data_t0, + iu_au_ib1_data_t1 => iu_au_ib1_data_t1, + iu_au_ib1_data_t2 => iu_au_ib1_data_t2, + iu_au_ib1_data_t3 => iu_au_ib1_data_t3 +); +iuq_slice_wrap0 : entity work.iuq_slice_wrap +generic map(expand_type => expand_type, + fpr_addr_width => fpr_addr_width, + regmode => regmode, + a2mode => a2mode, + lmq_entries => lmq_entries) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_iu_func_sl_thold_2 => pc_iu_func_sl_thold_2, + pc_iu_sg_2 => pc_iu_sg_2, + clkoff_b => clkoff_b, + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b_oif, + tc_ac_ccflush_dc => tc_ac_ccflush_dc, + delay_lclkr => delay_lclkr(9 to 14), + mpw1_b => mpw1_b(9 to 14), + iuq_s0_scan_in => iuq_s0_scan_in, + iuq_s0_scan_out => iuq_s0_scan_out, + iuq_s1_scan_in => iuq_s1_scan_in, + iuq_s1_scan_out => iuq_s1_scan_out, + iuq_s2_scan_in => iuq_s2_scan_in, + iuq_s2_scan_out => iuq_s2_scan_out, + iuq_s3_scan_in => iuq_s3_scan_in, + iuq_s3_scan_out => iuq_s3_scan_out, + pc_iu_ram_mode => pc_iu_ram_mode, + pc_iu_ram_thread => pc_iu_ram_thread, + pc_iu_trace_bus_enable => pc_iu_trace_bus_enable, + pc_iu_event_bus_enable => pc_iu_event_bus_enable, + fdep_dbg_data => fdep_dbg_data_pt_in, + fdep_perf_event_t0 => fdep_perf_event_pt_in_t0, + fdep_perf_event_t1 => fdep_perf_event_pt_in_t1, + fdep_perf_event_t2 => fdep_perf_event_pt_in_t2, + fdep_perf_event_t3 => fdep_perf_event_pt_in_t3, + iu_au_config_iucr_t0 => iu_au_config_iucr_t0, + iu_au_config_iucr_t1 => iu_au_config_iucr_t1, + iu_au_config_iucr_t2 => iu_au_config_iucr_t2, + iu_au_config_iucr_t3 => iu_au_config_iucr_t3, + spr_dec_mask_t0 => spr_dec_mask_pt_out_t0, + spr_dec_mask_t1 => spr_dec_mask_pt_out_t1, + spr_dec_mask_t2 => spr_dec_mask_pt_out_t2, + spr_dec_mask_t3 => spr_dec_mask_pt_out_t3, + spr_dec_match_t0 => spr_dec_match_t0, + spr_dec_match_t1 => spr_dec_match_t1, + spr_dec_match_t2 => spr_dec_match_t2, + spr_dec_match_t3 => spr_dec_match_t3, + uc_flush_tid => uc_flush_tid, + xu_iu_flush => xu_iu_u_flush, + xu_rf1_flush => xu_wu_rf1_flush, + xu_ex1_flush => xu_wu_ex1_flush, + xu_ex2_flush => xu_wu_ex2_flush, + xu_ex3_flush => xu_wu_ex3_flush, + xu_ex4_flush => xu_wu_ex4_flush, + xu_ex5_flush => xu_wu_ex5_flush, + fdec_ibuf_stall_t0 => fdec_ibuf_stall_t0, + fdec_ibuf_stall_t1 => fdec_ibuf_stall_t1, + fdec_ibuf_stall_t2 => fdec_ibuf_stall_t2, + fdec_ibuf_stall_t3 => fdec_ibuf_stall_t3, + iu_au_ib1_instr_vld_t0 => iu_au_ib1_instr_vld_t0, + iu_au_ib1_instr_vld_t1 => iu_au_ib1_instr_vld_t1, + iu_au_ib1_instr_vld_t2 => iu_au_ib1_instr_vld_t2, + iu_au_ib1_instr_vld_t3 => iu_au_ib1_instr_vld_t3, + iu_au_ib1_ifar_t0 => iu_au_ib1_ifar_t0, + iu_au_ib1_ifar_t1 => iu_au_ib1_ifar_t1, + iu_au_ib1_ifar_t2 => iu_au_ib1_ifar_t2, + iu_au_ib1_ifar_t3 => iu_au_ib1_ifar_t3, + iu_au_ib1_data_t0 => iu_au_ib1_data_t0, + iu_au_ib1_data_t1 => iu_au_ib1_data_t1, + iu_au_ib1_data_t2 => iu_au_ib1_data_t2, + iu_au_ib1_data_t3 => iu_au_ib1_data_t3, + xu_iu_ucode_restart => xu_iu_ucode_restart, + xu_iu_slowspr_done => xu_iu_slowspr_done, + xu_iu_multdiv_done => xu_iu_multdiv_done, + xu_iu_ex4_loadmiss_tid => xu_iu_ex4_loadmiss_tid, + xu_iu_ex4_loadmiss_qentry => xu_iu_ex4_loadmiss_qentry, + xu_iu_ex4_loadmiss_target => xu_iu_ex4_loadmiss_target, + xu_iu_ex4_loadmiss_target_type => xu_iu_ex4_loadmiss_target_type, + xu_iu_ex5_loadmiss_tid => xu_iu_ex5_loadmiss_tid, + xu_iu_ex5_loadmiss_qentry => xu_iu_ex5_loadmiss_qentry, + xu_iu_ex5_loadmiss_target => xu_iu_ex5_loadmiss_target(1 to 6), + xu_iu_ex5_loadmiss_target_type => xu_iu_ex5_loadmiss_target_type(0 to 0), + xu_iu_complete_tid => xu_iu_complete_tid, + xu_iu_complete_qentry => xu_iu_complete_qentry, + xu_iu_complete_target_type => xu_iu_complete_target_type, + ic_fdep_load_quiesce => ic_fdep_load_quiesce, + iu_xu_quiesce => iu_xu_quiesce, + xu_iu_membar_tid => xu_iu_membar_tid, + xu_iu_set_barr_tid => xu_iu_set_barr_tid, + xu_iu_larx_done_tid => xu_iu_larx_done_tid, + an_ac_sync_ack => an_ac_sync_ack_oif, + ic_fdep_icbi_ack => ic_fdep_icbi_ack, + an_ac_stcx_complete => an_ac_stcx_complete, + mm_iu_barrier_done => mm_iu_barrier_done_oif, + spr_fdep_ll_hold_t0 => spr_fdep_ll_hold_t0, + spr_fdep_ll_hold_t1 => spr_fdep_ll_hold_t1, + spr_fdep_ll_hold_t2 => spr_fdep_ll_hold_t2, + spr_fdep_ll_hold_t3 => spr_fdep_ll_hold_t3, + xu_iu_spr_ccr2_en_dcr => xu_iu_spr_ccr2_en_dcr, + xu_iu_single_instr_mode => xu_iu_single_instr_mode, + fu_iu_uc_special => fu_iu_uc_special, + iu_fu_ex2_n_flush => iu_fu_ex2_n_flush, + axu_dbg_data_t0 => axu_dbg_data_t0, + axu_dbg_data_t1 => axu_dbg_data_t1, + axu_dbg_data_t2 => axu_dbg_data_t2, + axu_dbg_data_t3 => axu_dbg_data_t3, + iuq_fi_scan_in => iuq_fi_scan_in, + iuq_fi_scan_out => iuq_fi_scan_out, + fiss_dbg_data => fiss_dbg_data, + fiss_perf_event_t0 => fiss_perf_event_t0, + fiss_perf_event_t1 => fiss_perf_event_t1, + fiss_perf_event_t2 => fiss_perf_event_t2, + fiss_perf_event_t3 => fiss_perf_event_t3, + xu_iu_need_hole => xu_iu_need_hole, + xu_iu_xucr0_rel => xu_iu_xucr0_rel, + an_ac_reld_data_vld_clone => an_ac_reld_data_vld_clone, + an_ac_reld_core_tag_clone => an_ac_reld_core_tag_clone(1 to 4), + an_ac_reld_ditc_clone => an_ac_reld_ditc_clone, + an_ac_reld_data_coming_clone => an_ac_reld_data_coming_clone, + an_ac_back_inv => an_ac_back_inv_oif, + an_ac_back_inv_target => an_ac_back_inv_target_oif, + fiss_uc_is2_ucode_vld => fiss_uc_is2_ucode_vld, + spr_issue_high_mask => spr_issue_high_mask, + spr_issue_med_mask => spr_issue_med_mask, + spr_fiss_count0_max => spr_fiss_count0_max, + spr_fiss_count1_max => spr_fiss_count1_max, + spr_fiss_count2_max => spr_fiss_count2_max, + spr_fiss_count3_max => spr_fiss_count3_max, + spr_fiss_pri_rand => spr_fiss_pri_rand, + spr_fiss_pri_rand_always => spr_fiss_pri_rand_always, + spr_fiss_pri_rand_flush => spr_fiss_pri_rand_flush, + xu_iu_ex5_ppc_cpl => xu_iu_ex5_ppc_cpl, + iu_xu_is2_vld_internal => iu_xu_is2_vld_internal, + iu_xu_is2_tid_internal => iu_xu_is2_tid_internal, + iu_xu_is2_instr_internal => iu_xu_is2_instr_internal, + iu_xu_is2_ta_vld => iu_xu_is2_ta_vld, + iu_xu_is2_ta => iu_xu_is2_ta, + iu_xu_is2_s1_vld => iu_xu_is2_s1_vld, + iu_xu_is2_s1 => iu_xu_is2_s1, + iu_xu_is2_s2_vld => iu_xu_is2_s2_vld, + iu_xu_is2_s2 => iu_xu_is2_s2, + iu_xu_is2_s3_vld => iu_xu_is2_s3_vld, + iu_xu_is2_s3 => iu_xu_is2_s3, + iu_xu_is2_pred_update_internal => iu_xu_is2_pred_update_internal, + iu_xu_is2_pred_taken_cnt_internal => iu_xu_is2_pred_taken_cnt_internal, + iu_xu_is2_gshare => iu_xu_is2_gshare, + iu_xu_is2_ifar_internal => iu_xu_is2_ifar_internal, + iu_xu_is2_error_internal => iu_xu_is2_error_internal, + iu_xu_is2_is_ucode => iu_xu_is2_is_ucode, + iu_xu_is2_axu_ld_or_st => iu_xu_is2_axu_ld_or_st, + iu_xu_is2_axu_store_internal => iu_xu_is2_axu_store_internal, + iu_xu_is2_axu_ldst_indexed => iu_xu_is2_axu_ldst_indexed, + iu_xu_is2_axu_ldst_tag => iu_xu_is2_axu_ldst_tag, + iu_xu_is2_axu_ldst_size => iu_xu_is2_axu_ldst_size, + iu_xu_is2_axu_ldst_update => iu_xu_is2_axu_ldst_update, + iu_xu_is2_axu_ldst_extpid => iu_xu_is2_axu_ldst_extpid, + iu_xu_is2_axu_ldst_forcealign => iu_xu_is2_axu_ldst_forcealign, + iu_xu_is2_axu_ldst_forceexcept => iu_xu_is2_axu_ldst_forceexcept, + iu_xu_is2_axu_mftgpr => iu_xu_is2_axu_mftgpr, + iu_xu_is2_axu_mffgpr => iu_xu_is2_axu_mffgpr, + iu_xu_is2_axu_movedp => iu_xu_is2_axu_movedp, + iu_xu_is2_axu_instr_type => iu_xu_is2_axu_instr_type, + iu_xu_is2_match => iu_xu_is2_match, + fiss_uc_is2_2ucode => fiss_uc_is2_2ucode, + fiss_uc_is2_2ucode_type => fiss_uc_is2_2ucode_type, + iu_fu_rf0_str_val => iu_fu_rf0_str_val, + iu_fu_rf0_ldst_val => iu_fu_rf0_ldst_val, + iu_fu_rf0_ldst_tid => iu_fu_rf0_ldst_tid, + iu_fu_rf0_ldst_tag => iu_fu_rf0_ldst_tag, + iuq_ai_scan_in => iuq_ai_scan_in, + iuq_ai_scan_out => iuq_ai_scan_out, + iu_fu_is2_tid_decode => iu_fu_is2_tid_decode, + iu_fu_rf0_instr_match => iu_fu_rf0_instr_match, + iu_fu_rf0_instr => iu_fu_rf0_instr, + iu_fu_rf0_instr_v => iu_fu_rf0_instr_v, + iu_fu_rf0_is_ucode => iu_fu_rf0_is_ucode, + iu_fu_rf0_fra => iu_fu_rf0_fra, + iu_fu_rf0_frb => iu_fu_rf0_frb, + iu_fu_rf0_frc => iu_fu_rf0_frc, + iu_fu_rf0_frt => iu_fu_rf0_frt, + iu_fu_rf0_fra_v => iu_fu_rf0_fra_v, + iu_fu_rf0_frb_v => iu_fu_rf0_frb_v, + iu_fu_rf0_frc_v => iu_fu_rf0_frc_v, + iu_fu_rf0_ucfmul => iu_fu_rf0_ucfmul, + fu_iss_dbg_data => fu_iss_dbg_data, + iu_fu_rf0_tid => iu_fu_rf0_tid, + iu_fu_rf0_bypsel => iu_fu_rf0_bypsel, + iu_fu_rf0_ifar => iu_fu_rf0_ifar +); +iu_xu_is2_vld <= iu_xu_is2_vld_internal; +iu_xu_is2_instr(0 to 31) <= iu_xu_is2_instr_internal(0 to 31); +iu_xu_is2_tid(0 to 3) <= iu_xu_is2_tid_internal(0 to 3); +iu_xu_is2_axu_store <= iu_xu_is2_axu_store_internal; +iu_xu_is2_error(0 to 2) <= iu_xu_is2_error_internal(0 to 2); +iu_xu_is2_ifar <= iu_xu_is2_ifar_internal; +iu_xu_is2_pred_update <= iu_xu_is2_pred_update_internal; +iu_xu_is2_pred_taken_cnt(0 to 1)<= iu_xu_is2_pred_taken_cnt_internal(0 to 1); +fiss_uc_is2_instr(0 to 31) <= iu_xu_is2_instr_internal(0 to 31); +fiss_uc_is2_tid(0 to 3) <= iu_xu_is2_tid_internal(0 to 3); +iu_xu_is2_ucode_vld <= fiss_uc_is2_ucode_vld; +iuq_b0_scan_in <= iuq_bp_scan_out; +iu_func_scan_out(0) <= iuq_b0_scan_out; +iuq_b1_scan_in <= iuq_mi_scan_out(0); +iu_func_scan_out(1) <= iuq_b1_scan_out; +iuq_fi_scan_in <= iu_func_scan_in_q(0); +iuq_ai_scan_in <= iuq_fi_scan_out; +iuq_b2_scan_in <= iuq_ai_scan_out; +iu_func_scan_out(2) <= iuq_b2_scan_out; +iuq_b3_scan_in <= iuq_mi_scan_out(1); +iu_func_scan_out(3) <= iuq_b3_scan_out; +iuq_s0_scan_in <= iu_func_scan_in_q(1); +iu_func_scan_out(4) <= iuq_s0_scan_out; +iuq_s1_scan_in <= iu_func_scan_in_q(2); +iu_func_scan_out(5) <= iuq_s1_scan_out; +iuq_s2_scan_in <= iu_func_scan_in_q(3); +iu_func_scan_out(6) <= iuq_s2_scan_out; +iuq_s3_scan_in <= iu_func_scan_in_q(4); +iu_func_scan_out(7) <= iuq_s3_scan_out; +end iuq; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_axu_fu_dec.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_axu_fu_dec.vhdl new file mode 100644 index 0000000..3066c13 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_axu_fu_dec.vhdl @@ -0,0 +1,1929 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + + + + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + use work.iuq_pkg.all; + + + + +entity iuq_axu_fu_dec is +generic( + expand_type : integer := 2; + fpr_addr_width : integer := 5; + needs_sreset : integer := 1); +port( + nclk : in clk_logic; + vdd : inout power_logic; + gnd : inout power_logic; + + i_dec_si : in std_ulogic; + i_dec_so : out std_ulogic; + + pc_iu_sg_0 : in std_ulogic; + pc_iu_func_sl_thold_0_b : in std_ulogic; + forcee : in std_ulogic; + d_mode : in std_ulogic; + delay_lclkr : in std_ulogic; + mpw1_b : in std_ulogic; + mpw2_b : in std_ulogic; + + pc_au_ram_mode : in std_ulogic; + pc_au_ram_thread_v : in std_ulogic; + + iu_au_is0_instr_v : in std_ulogic; + iu_au_is0_instr : in std_ulogic_vector(0 to 31); + iu_au_is0_ucode_ext : in std_ulogic_vector(0 to 3); + iu_au_is0_is_ucode : in std_ulogic; + iu_au_is0_2ucode : in std_ulogic; + iu_au_ucode_restart : in std_ulogic; + + iu_au_is0_cr_setter : in std_ulogic; + + iu_au_is1_stall : in std_ulogic; + iu_au_is0_flush : in std_ulogic; + iu_au_is1_flush : in std_ulogic; + + iu_au_config_iucr : in std_ulogic_vector(0 to 7); + ifdp_ex5_fmul_uc_complete : in std_ulogic; + + au_iu_is0_i_dec_b : out std_ulogic; + au_iu_is0_to_ucode : out std_ulogic; + au_iu_is0_ucode_only : out std_ulogic; + + au_iu_is0_ldst : out std_ulogic; + au_iu_is0_ldst_v : out std_ulogic; + au_iu_is0_st_v : out std_ulogic; + au_iu_is0_mftgpr : out std_ulogic; + au_iu_is0_mffgpr : out std_ulogic; + au_iu_is0_movedp : out std_ulogic; + au_iu_is0_ldst_extpid : out std_ulogic; + au_iu_is0_instr_type : out std_ulogic_vector(0 to 2); + au_iu_is0_ldst_size : out std_ulogic_vector(0 to 5); + au_iu_is0_ldst_tag : out std_ulogic_vector(0 to 8); + au_iu_is0_ldst_ra_v : out std_ulogic; + au_iu_is0_ldst_ra : out std_ulogic_vector(0 to 6); + au_iu_is0_ldst_rb_v : out std_ulogic; + au_iu_is0_ldst_rb : out std_ulogic_vector(0 to 6); + au_iu_is0_ldst_dimm : out std_ulogic_vector(0 to 15); + au_iu_is0_ldst_indexed : out std_ulogic; + au_iu_is0_ldst_update : out std_ulogic; + au_iu_is0_ldst_forcealign : out std_ulogic; + au_iu_is0_ldst_forceexcept : out std_ulogic; + i_afd_is1_is_ucode : out std_ulogic; + i_afd_is1_to_ucode : out std_ulogic; + + i_afd_in_ucode_mode_or1d : out std_ulogic; + + i_afd_config_iucr : out std_ulogic_vector(1 to 7); + i_afd_fmul_uc_is1 : out std_ulogic; + + i_afd_is1_fra_v : out std_ulogic; + i_afd_is1_frb_v : out std_ulogic; + i_afd_is1_frc_v : out std_ulogic; + i_afd_is1_frt_v : out std_ulogic; + i_afd_is1_prebubble1 : out std_ulogic; + i_afd_is1_est_bubble3 : out std_ulogic; + + i_afd_is1_cr_setter : out std_ulogic; + i_afd_is1_cr_writer : out std_ulogic; + + i_afd_is1_fra : out std_ulogic_vector(0 to 6); + i_afd_is1_frb : out std_ulogic_vector(0 to 6); + i_afd_is1_frc : out std_ulogic_vector(0 to 6); + i_afd_is1_frt : out std_ulogic_vector(0 to 6); + i_afd_is1_fra_buf : out std_ulogic_vector(1 to 6); + i_afd_is1_frb_buf : out std_ulogic_vector(1 to 6); + i_afd_is1_frc_buf : out std_ulogic_vector(1 to 6); + i_afd_is1_frt_buf : out std_ulogic_vector(1 to 6); + + i_afd_is1_instr_v : out std_ulogic; + + i_afd_is1_instr_ldst_v : out std_ulogic; + i_afd_is1_instr_ld_v : out std_ulogic; + i_afd_is1_instr_sto_v : out std_ulogic; + + i_afd_ignore_flush_is1 : out std_ulogic; + + i_afd_is1_divsqrt : out std_ulogic; + i_afd_is1_stall_rep : out std_ulogic; + + fu_dec_debug : out std_ulogic_vector(0 to 13) +); + + + + + +end iuq_axu_fu_dec; + + +architecture iuq_axu_fu_dec of iuq_axu_fu_dec is + + signal tidn : std_ulogic; + signal tiup : std_ulogic; + + + + signal iu_au_config_iucr_int : std_ulogic_vector(0 to 7); + signal iu_au_config_iucr_l2 : std_ulogic_vector(0 to 7); + signal iu_au_config_iucr_din : std_ulogic_vector(0 to 7); + signal is0_instr : std_ulogic_vector(00 to 31); + signal pri_is0 : std_ulogic_vector(0 to 5); + signal sec_is0 : std_ulogic_vector(20 to 31); + signal av,bv,cv,tv : std_ulogic; + signal isfu_dec_is0, ld_st_is0 : std_ulogic; + + signal st_is0, indexed, fdiv_is0, fsqrt_is0: std_ulogic; + signal update_form, forcealign : std_ulogic; + signal cr_writer : std_ulogic; + signal is1_st : std_ulogic; + signal is1_ldst : std_ulogic; + signal is1_fra_v : std_ulogic; + signal is1_frb_v : std_ulogic; + signal is1_frc_v : std_ulogic; + signal is1_frt_v : std_ulogic; + + + signal is0_instr_v : std_ulogic; + signal ucode_restart : std_ulogic; + signal is1_instr_v : std_ulogic; + signal is1_cr_setter : std_ulogic; + signal is1_cr_writer : std_ulogic; + signal is1_is_ucode : std_ulogic; + signal is1_to_ucode : std_ulogic; + + signal mffgpr, mftgpr : std_ulogic; + signal bubble3,prebubble1 :std_ulogic; + signal ldst_tag :std_ulogic_vector(0 to 8); + signal ldst_tag_addr :std_ulogic_vector(0 to 5); + signal is0_to_ucode : std_ulogic; + + + signal cmd_is0_ld, cmd_is1_l2, cmd_is1_scin, cmd_is1_scout : std_ulogic_vector(6 to 53); + + signal config_reg_scin : std_ulogic_vector(0 to 7); + signal config_reg_scout : std_ulogic_vector(0 to 7); + + + signal size : std_ulogic_vector(0 to 5); + signal spare_unused : std_ulogic_vector(2 to 49); + + signal is0_is_ucode, in_ucode_mode,in_fdivsqrt_mode_is0, only_from_ucode, only_graphics_mode ,graphics_mode : std_ulogic; + signal is0_invalid_kill, is0_invalid_kill_uc : std_ulogic; + signal is0_in_divsqrt_mode_or1d,is1_in_divsqrt_mode_or1d : std_ulogic; + + signal ldst_extpid : std_ulogic; + signal single_precision_ldst :std_ulogic; + signal int_word_ldst :std_ulogic; + signal sign_ext_ldst :std_ulogic; + signal is1_stall, is1_stall_b :std_ulogic; + signal io_port, io_port_ext :std_ulogic; + + signal ignore_flush_is0 : std_ulogic; + signal ucmodelat_din, ucmodelat_dout : std_ulogic; + signal final_fmul_uc : std_ulogic; + signal is1_fmul_uc : std_ulogic; + + signal is0_st_or_mtdp :std_ulogic; + signal is0_mftgpr :std_ulogic; + signal is0_usual_fra :std_ulogic; + signal is0_kill_or_divsqrt_b :std_ulogic; + signal au_iu_is0_i_dec : std_ulogic; + signal is0_i_dec_b : std_ulogic; + + signal is0_frt : std_ulogic_vector(0 to 5); + signal is0_fra_or_frs : std_ulogic_vector(0 to 5); + signal tag_in_16to20,mftgpr_not_DITC :std_ulogic; + signal cmd_is0_40_part :std_ulogic; + signal cmd_is0_41_part :std_ulogic; + signal cmd_is0_43_part :std_ulogic; + signal cmd_is0_50_part :std_ulogic; + + signal is1_frt_buf, is1_frt_buf_b : std_ulogic_vector(1 to 6); + signal is1_fra_buf, is1_fra_buf_b : std_ulogic_vector(1 to 6); + signal is1_frb_buf, is1_frb_buf_b : std_ulogic_vector(1 to 6); + signal is1_frc_buf, is1_frc_buf_b : std_ulogic_vector(1 to 6); + + signal is0_ins, is0_ins_b, is0_ins_dly, is0_ins_dly_b :std_ulogic_vector(0 to 31); + signal is0_ins_v, is0_ins_v_b :std_ulogic; + signal is1_v_nstall1_b, is1_v_nstall2_b :std_ulogic; + signal is1_v_nstall1, is1_v_nstall2,is1_v_nstall3,is1_v_nstall4,is1_v_nstall5,is1_v_nstall6,is1_v_nstall7,is1_v_nstall8 :std_ulogic; + + signal is1_v_nstall01_INVA_b, is1_v_nstall01_INVB :std_ulogic; + signal is1_v_nstall02_INVA_b, is1_v_nstall02_INVB :std_ulogic; + signal is1_v_nstall03_INVA_b, is1_v_nstall03_INVB :std_ulogic; + signal is1_v_nstall04_INVA_b, is1_v_nstall04_INVB :std_ulogic; + signal is1_v_nstall05_INVA_b, is1_v_nstall05_INVB :std_ulogic; + signal is1_v_nstall06_INVA_b, is1_v_nstall06_INVB :std_ulogic; + signal is1_v_nstall07_INVA_b, is1_v_nstall07_INVB :std_ulogic; + signal is1_v_nstall08_INVA_b, is1_v_nstall08_INVB :std_ulogic; + signal is1_v_nstall09_INVA_b, is1_v_nstall09_INVB :std_ulogic; + signal is1_v_nstall10_INVA_b, is1_v_nstall10_INVB :std_ulogic; + signal is1_v_nstall11_INVA_b, is1_v_nstall11_INVB :std_ulogic; + signal is1_v_nstall12_INVA_b, is1_v_nstall12_INVB :std_ulogic; + signal is1_v_nstall13_INVA_b, is1_v_nstall13_INVB :std_ulogic; + signal is1_v_nstall14_INVA_b, is1_v_nstall14_INVB :std_ulogic; + signal is1_v_nstall15_INVA_b, is1_v_nstall15_INVB :std_ulogic; + signal is1_v_nstall16_INVA_b, is1_v_nstall16_INVB :std_ulogic; + signal is1_v_nstall17_INVA_b, is1_v_nstall17_INVB :std_ulogic; + signal is1_v_nstall18_INVA_b, is1_v_nstall18_INVB :std_ulogic; + signal is1_v_nstall19_INVA_b, is1_v_nstall19_INVB :std_ulogic; + signal is1_v_nstall20_INVA_b, is1_v_nstall20_INVB :std_ulogic; + signal is1_v_nstall21_INVA_b, is1_v_nstall21_INVB :std_ulogic; + signal is1_v_nstall22_INVA_b, is1_v_nstall22_INVB :std_ulogic; + signal is1_v_nstall23_INVA_b, is1_v_nstall23_INVB :std_ulogic; + signal is1_v_nstall24_INVA_b, is1_v_nstall24_INVB :std_ulogic; + signal is1_v_nstall25_INVA_b, is1_v_nstall25_INVB :std_ulogic; + signal is1_v_nstall26_INVA_b, is1_v_nstall26_INVB :std_ulogic; + signal is1_v_nstall27_INVA_b, is1_v_nstall27_INVB :std_ulogic; + signal is1_v_nstall28_INVA_b, is1_v_nstall28_INVB :std_ulogic; + signal is1_v_nstall29_INVA_b, is1_v_nstall29_INVB :std_ulogic; + signal is1_v_nstall30_INVA_b, is1_v_nstall30_INVB :std_ulogic; + signal is1_v_nstall31_INVA_b, is1_v_nstall31_INVB :std_ulogic; + signal is1_v_nstall32_INVA_b, is1_v_nstall32_INVB :std_ulogic; + + signal ram_mode_v :std_ulogic; + + signal cmd_is0_go_b, cmd_is1_ho_b :std_ulogic_vector(6 to 53); +signal iu_au_is0_flush_b, iu_au_is1_flush_b :std_ulogic; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + begin + + + tidn <= '0'; + tiup <= '1'; + + is1_stall <= iu_au_is1_stall; + + + is0_instr <= iu_au_is0_instr; + is0_instr_v <= iu_au_is0_instr_v; + ucode_restart <= iu_au_ucode_restart; + spare_unused(48) <= tidn; + + pri_is0(0 to 5) <= is0_instr(0 to 5); + sec_is0(20 to 31) <= is0_instr(20 to 31); + + + spare_unused(49) <= d_mode; + +iu_au_is1_stall_INV: is1_stall_b <= not iu_au_is1_stall; + +is0_ins_inv: is0_ins_b(0 to 31) <= not( iu_au_is0_instr(0 to 31) ); +is0_ins_buf: is0_ins (0 to 31) <= not( is0_ins_b (0 to 31) ); +is0_ins_inv_dly: is0_ins_dly_b(0 to 31) <= not( is0_ins (0 to 31) ); +is0_ins_buf_dly: is0_ins_dly (0 to 31) <= not( is0_ins_dly_b (0 to 31) ); +is0_ins_v_inv: is0_ins_v_b <= not( iu_au_is0_instr_v ); +is0_ins_v_buf: is0_ins_v <= not( is0_ins_v_b ); + +spare_unused(12 to 27) <= is0_ins_dly(0 to 15); +spare_unused(28 to 33) <= is0_ins_dly(26 to 31); + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +isfu_dec_is0 <= ( pri_is0(0) and pri_is0(1) and pri_is0(3) and pri_is0(4) + and pri_is0(5) and not sec_is0(21) and not sec_is0(22) + and not sec_is0(23) and not sec_is0(24) and not sec_is0(25) + and sec_is0(27) and not sec_is0(29) and not sec_is0(30)) or + ( pri_is0(0) and pri_is0(1) and pri_is0(4) and pri_is0(5) + and sec_is0(26) and sec_is0(28) and not sec_is0(30)) or + ( pri_is0(0) and pri_is0(1) and pri_is0(3) and pri_is0(4) + and pri_is0(5) and sec_is0(26) and not sec_is0(30)) or + ( pri_is0(0) and pri_is0(1) and pri_is0(4) and pri_is0(5) + and sec_is0(26) and sec_is0(27) and not sec_is0(30)) or + (not pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(3) + and pri_is0(4) and pri_is0(5) and sec_is0(20) + and not sec_is0(21) and not sec_is0(22) and not sec_is0(23) + and not sec_is0(26) and not sec_is0(27) and not sec_is0(28) + and sec_is0(29) and sec_is0(30)) or + ( pri_is0(0) and pri_is0(1) and pri_is0(4) and pri_is0(5) + and sec_is0(21) and sec_is0(22) and sec_is0(24) + and not sec_is0(25) and sec_is0(27) and sec_is0(28) + and sec_is0(29) and not sec_is0(30)) or + ( pri_is0(0) and pri_is0(1) and not pri_is0(3) and pri_is0(4) + and pri_is0(5) and not sec_is0(21) and not sec_is0(22) + and sec_is0(23) and sec_is0(24) and not sec_is0(27) + and sec_is0(28) and not sec_is0(29) and sec_is0(30) + and not sec_is0(31)) or + ( pri_is0(0) and pri_is0(1) and pri_is0(3) and pri_is0(4) + and pri_is0(5) and not sec_is0(21) and sec_is0(22) + and sec_is0(23) and sec_is0(27) and not sec_is0(28) + and not sec_is0(29) and not sec_is0(30)) or + ( pri_is0(0) and pri_is0(1) and pri_is0(3) and pri_is0(4) + and pri_is0(5) and sec_is0(21) and sec_is0(22) + and not sec_is0(24) and sec_is0(25) and sec_is0(27) + and sec_is0(28) and sec_is0(29)) or + ( pri_is0(0) and pri_is0(1) and pri_is0(3) and pri_is0(4) + and pri_is0(5) and not sec_is0(21) and not sec_is0(24) + and not sec_is0(25) and sec_is0(27) and not sec_is0(28) + and not sec_is0(29) and not sec_is0(30)) or + ( pri_is0(1) and pri_is0(2) and pri_is0(3) and pri_is0(4) + and pri_is0(5) and sec_is0(21) and sec_is0(24) + and not sec_is0(25) and sec_is0(26) and not sec_is0(27) + and sec_is0(28) and sec_is0(29) and sec_is0(30)) or + ( pri_is0(1) and pri_is0(2) and pri_is0(3) and pri_is0(4) + and pri_is0(5) and sec_is0(21) and not sec_is0(23) + and sec_is0(24) and sec_is0(26) and not sec_is0(27) + and sec_is0(28) and sec_is0(29) and sec_is0(30)) or + ( pri_is0(1) and pri_is0(2) and pri_is0(3) and pri_is0(4) + and pri_is0(5) and sec_is0(21) and not sec_is0(22) + and sec_is0(23) and sec_is0(24) and not sec_is0(25) + and sec_is0(26) and sec_is0(27) and sec_is0(28) + and sec_is0(30)) or + ( pri_is0(0) and pri_is0(1) and pri_is0(3) and pri_is0(4) + and pri_is0(5) and not sec_is0(21) and not sec_is0(22) + and not sec_is0(23) and not sec_is0(24) and not sec_is0(28) + and not sec_is0(29) and not sec_is0(30)) or + ( pri_is0(1) and pri_is0(2) and pri_is0(3) and pri_is0(4) + and pri_is0(5) and sec_is0(21) and not sec_is0(22) + and not sec_is0(23) and sec_is0(24) and sec_is0(25) + and sec_is0(26) and sec_is0(27) and sec_is0(28)) or + ( pri_is0(1) and pri_is0(2) and pri_is0(3) and pri_is0(4) + and pri_is0(5) and sec_is0(21) and not sec_is0(22) + and sec_is0(26) and not sec_is0(27) and sec_is0(28) + and sec_is0(29) and sec_is0(30)) or + ( pri_is0(1) and pri_is0(2) and pri_is0(3) and pri_is0(4) + and pri_is0(5) and sec_is0(21) and not sec_is0(22) + and sec_is0(24) and sec_is0(25) and sec_is0(26) + and sec_is0(27) and sec_is0(28) and sec_is0(29)) or + ( pri_is0(0) and pri_is0(1) and pri_is0(3) and pri_is0(4) + and pri_is0(5) and sec_is0(21) and not sec_is0(22) + and sec_is0(24) and not sec_is0(25) and not sec_is0(27) + and sec_is0(28) and sec_is0(29) and sec_is0(30)) or + ( pri_is0(0) and pri_is0(1) and pri_is0(3) and pri_is0(4) + and pri_is0(5) and not sec_is0(21) and not sec_is0(22) + and not sec_is0(23) and not sec_is0(25) and not sec_is0(28) + and not sec_is0(29) and not sec_is0(30)) or + ( pri_is0(0) and pri_is0(1) and pri_is0(3) and pri_is0(4) + and pri_is0(5) and not sec_is0(21) and not sec_is0(22) + and sec_is0(23) and not sec_is0(24) and not sec_is0(25) + and sec_is0(28) and sec_is0(29) and not sec_is0(30)) or + ( pri_is0(0) and pri_is0(1) and pri_is0(3) and pri_is0(4) + and pri_is0(5) and not sec_is0(21) and not sec_is0(22) + and not sec_is0(24) and not sec_is0(25) and sec_is0(27) + and sec_is0(28) and sec_is0(29)) or + ( pri_is0(0) and pri_is0(1) and pri_is0(3) and pri_is0(4) + and pri_is0(5) and not sec_is0(21) and not sec_is0(22) + and not sec_is0(23) and not sec_is0(24) and sec_is0(25) + and not sec_is0(27) and sec_is0(28) and sec_is0(29) + and not sec_is0(30)) or + ( pri_is0(1) and pri_is0(2) and pri_is0(3) and pri_is0(4) + and pri_is0(5) and sec_is0(21) and not sec_is0(22) + and sec_is0(24) and sec_is0(26) and sec_is0(28) + and sec_is0(29) and sec_is0(30)) or + ( pri_is0(0) and pri_is0(1) and pri_is0(3) and pri_is0(4) + and pri_is0(5) and not sec_is0(21) and not sec_is0(22) + and not sec_is0(24) and not sec_is0(27) and not sec_is0(28) + and not sec_is0(29) and not sec_is0(30)) or + ( pri_is0(0) and pri_is0(1) and pri_is0(3) and pri_is0(4) + and pri_is0(5) and not sec_is0(21) and not sec_is0(22) + and not sec_is0(23) and sec_is0(24) and not sec_is0(25) + and not sec_is0(27) and sec_is0(28) and sec_is0(29) + and not sec_is0(30)) or + ( pri_is0(0) and pri_is0(1) and pri_is0(4) and pri_is0(5) + and sec_is0(26) and not sec_is0(29) and sec_is0(30)) or + ( pri_is0(0) and pri_is0(1) and pri_is0(4) and pri_is0(5) + and sec_is0(26) and sec_is0(29) and not sec_is0(30)) or + ( pri_is0(0) and pri_is0(1) and pri_is0(4) and pri_is0(5) + and sec_is0(26) and sec_is0(27) and sec_is0(28)) or + ( pri_is0(0) and pri_is0(1) and not pri_is0(2)) or + ( pri_is0(0) and pri_is0(1) and pri_is0(3) and pri_is0(4) + and pri_is0(5) and sec_is0(26) and sec_is0(28)); + +tv <= (not pri_is0(3) and sec_is0(30) and not sec_is0(31)) or + ( pri_is0(2) and pri_is0(4) and not sec_is0(21) and sec_is0(22)) or + ( pri_is0(2) and sec_is0(20) and not sec_is0(23) and not sec_is0(24) + and not sec_is0(26) and not sec_is0(27) and not sec_is0(28) and sec_is0(29) + and sec_is0(30)) or + ( pri_is0(2) and sec_is0(22) and not sec_is0(23) and sec_is0(24) + and sec_is0(26) and not sec_is0(27) and sec_is0(28) and sec_is0(29) + and sec_is0(30)) or + ( pri_is0(2) and pri_is0(4) and sec_is0(22) and not sec_is0(24) + and sec_is0(27)) or + ( pri_is0(2) and pri_is0(4) and sec_is0(21) and not sec_is0(22) + and not sec_is0(23) and sec_is0(28)) or + ( pri_is0(0) and pri_is0(2) and pri_is0(4) and not sec_is0(25) + and sec_is0(27)) or + ( pri_is0(0) and pri_is0(2) and pri_is0(4) and not sec_is0(23) + and sec_is0(27)) or + ( pri_is0(0) and pri_is0(2) and pri_is0(4) and sec_is0(26)) or + (not pri_is0(2) and not pri_is0(3)); + +av <= ( pri_is0(3) and sec_is0(20) and not sec_is0(22) and not sec_is0(23) + and sec_is0(24) and not sec_is0(26) and not sec_is0(27) and not sec_is0(28) + and sec_is0(29) and sec_is0(30)) or + ( pri_is0(0) and pri_is0(3) and pri_is0(4) and not sec_is0(22) + and not sec_is0(23) and not sec_is0(24) and not sec_is0(25) and not sec_is0(26) + and not sec_is0(28)) or + ( pri_is0(0) and pri_is0(3) and pri_is0(4) and not sec_is0(23) + and sec_is0(25) and not sec_is0(26) and not sec_is0(27) and not sec_is0(29)) or + (not pri_is0(0) and sec_is0(21) and sec_is0(23) and sec_is0(24) + and not sec_is0(25) and sec_is0(29)) or + ( pri_is0(0) and pri_is0(3) and pri_is0(4) and not sec_is0(24) + and not sec_is0(25) and not sec_is0(26) and not sec_is0(27) and not sec_is0(29) + and not sec_is0(30)) or + (not pri_is0(0) and sec_is0(21) and not sec_is0(22) and sec_is0(23) + and not sec_is0(27)) or + ( pri_is0(0) and pri_is0(2) and pri_is0(4) and sec_is0(26) + and sec_is0(27) and sec_is0(28)) or + ( pri_is0(0) and pri_is0(2) and pri_is0(4) and sec_is0(26) + and not sec_is0(27) and not sec_is0(28) and sec_is0(29)) or + ( pri_is0(0) and pri_is0(2) and pri_is0(4) and sec_is0(26) + and sec_is0(28) and not sec_is0(29)) or + ( pri_is0(0) and pri_is0(2) and sec_is0(26) and sec_is0(30)) or + ( pri_is0(1) and not pri_is0(2) and pri_is0(3)); + +bv <= (not pri_is0(0) and sec_is0(21) and not sec_is0(25) and not sec_is0(29)) or + ( pri_is0(2) and not pri_is0(3) and sec_is0(28) and sec_is0(30) + and not sec_is0(31)) or + (not pri_is0(0) and sec_is0(21) and sec_is0(23) and sec_is0(25) + and sec_is0(27) and sec_is0(28) and sec_is0(29)) or + ( pri_is0(0) and pri_is0(2) and pri_is0(4) and not sec_is0(24) + and not sec_is0(27) and not sec_is0(28) and not sec_is0(29) and not sec_is0(30)) or + ( pri_is0(2) and pri_is0(4) and sec_is0(22) and not sec_is0(24) + and not sec_is0(26)) or + ( pri_is0(0) and pri_is0(2) and pri_is0(4) and sec_is0(23) + and sec_is0(24) and not sec_is0(25) and sec_is0(29)) or + ( pri_is0(0) and pri_is0(2) and pri_is0(4) and not sec_is0(25) + and not sec_is0(26) and sec_is0(27)) or + ( pri_is0(0) and pri_is0(2) and pri_is0(4) and not sec_is0(21) + and sec_is0(24) and sec_is0(27) and not sec_is0(30)) or + ( pri_is0(0) and pri_is0(2) and sec_is0(26) and sec_is0(28) + and sec_is0(30)) or + ( pri_is0(0) and pri_is0(2) and pri_is0(4) and not sec_is0(23) + and not sec_is0(26) and sec_is0(27)) or + ( pri_is0(0) and pri_is0(2) and pri_is0(4) and sec_is0(26) + and not sec_is0(30)); + +cv <= ( pri_is0(0) and pri_is0(2) and sec_is0(26) and not sec_is0(28) + and sec_is0(30)) or + ( pri_is0(0) and pri_is0(2) and sec_is0(26) and sec_is0(29) + and sec_is0(30)) or + ( pri_is0(0) and pri_is0(2) and pri_is0(4) and sec_is0(26) + and sec_is0(27) and sec_is0(28)); + +bubble3 <= ( pri_is0(0) and pri_is0(2) and not sec_is0(23) and not sec_is0(26) + and sec_is0(29) and sec_is0(31)) or + ( pri_is0(0) and pri_is0(2) and pri_is0(4) and not sec_is0(23) + and sec_is0(24) and not sec_is0(26) and not sec_is0(27) and not sec_is0(28)) or + ( pri_is0(0) and pri_is0(2) and not sec_is0(25) and sec_is0(27) + and sec_is0(31)) or + ( pri_is0(2) and not sec_is0(21) and sec_is0(22) and sec_is0(27) + and sec_is0(31)) or + ( pri_is0(0) and pri_is0(2) and pri_is0(4) and sec_is0(23) + and not sec_is0(24) and not sec_is0(26) and not sec_is0(27) and not sec_is0(28) + and not sec_is0(29) and not sec_is0(30)) or + ( pri_is0(2) and sec_is0(22) and not sec_is0(24) and sec_is0(27) + and sec_is0(31)) or + ( pri_is0(0) and pri_is0(2) and not sec_is0(25) and not sec_is0(26) + and sec_is0(28) and sec_is0(29) and sec_is0(31)) or + ( pri_is0(0) and pri_is0(2) and not sec_is0(23) and sec_is0(27) + and sec_is0(31)) or + ( pri_is0(0) and pri_is0(2) and sec_is0(26) and sec_is0(30) + and sec_is0(31)) or + ( pri_is0(0) and pri_is0(2) and sec_is0(26) and sec_is0(28) + and not sec_is0(29) and sec_is0(31)) or + ( pri_is0(0) and pri_is0(2) and sec_is0(26) and sec_is0(27) + and sec_is0(31)); + +prebubble1 <= ( pri_is0(0) and pri_is0(2) and not sec_is0(23) and not sec_is0(26) + and not sec_is0(27) and sec_is0(30)); + +ld_st_is0 <= (not pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(3) + and pri_is0(4) and pri_is0(5) and sec_is0(20) and not sec_is0(21) + and not sec_is0(22) and not sec_is0(23) and not sec_is0(26) and not sec_is0(27) + and not sec_is0(28) and sec_is0(29) and sec_is0(30)) or + (not pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(3) + and pri_is0(4) and pri_is0(5) and sec_is0(21) + and not sec_is0(22) and not sec_is0(23) and sec_is0(24) + and sec_is0(25) and sec_is0(26) and sec_is0(27) + and sec_is0(28)) or + (not pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(3) + and pri_is0(4) and pri_is0(5) and sec_is0(21) + and not sec_is0(22) and sec_is0(23) and sec_is0(24) + and not sec_is0(25) and sec_is0(26) and sec_is0(27) + and sec_is0(28) and sec_is0(30)) or + (not pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(3) + and pri_is0(4) and pri_is0(5) and sec_is0(21) + and not sec_is0(22) and sec_is0(24) and sec_is0(25) + and sec_is0(26) and sec_is0(27) and sec_is0(28) + and sec_is0(29)) or + (not pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(3) + and pri_is0(4) and pri_is0(5) and sec_is0(21) + and sec_is0(24) and not sec_is0(25) and sec_is0(26) + and not sec_is0(27) and sec_is0(28) and sec_is0(29) + and sec_is0(30)) or + (not pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(3) + and pri_is0(4) and pri_is0(5) and sec_is0(21) + and not sec_is0(22) and sec_is0(26) and not sec_is0(27) + and sec_is0(28) and sec_is0(29) and sec_is0(30)) or + (not pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(3) + and pri_is0(4) and pri_is0(5) and sec_is0(21) + and not sec_is0(23) and sec_is0(24) and sec_is0(26) + and not sec_is0(27) and sec_is0(28) and sec_is0(29) + and sec_is0(30)) or + (not pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(3) + and pri_is0(4) and pri_is0(5) and sec_is0(21) + and not sec_is0(22) and sec_is0(24) and sec_is0(26) + and sec_is0(28) and sec_is0(29) and sec_is0(30)) or + ( pri_is0(0) and pri_is0(1) and not pri_is0(2)); + +st_is0 <= (not pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(3) + and pri_is0(4) and pri_is0(5) and sec_is0(20) + and not sec_is0(21) and not sec_is0(22) and not sec_is0(23) + and sec_is0(24) and not sec_is0(26) and not sec_is0(27) + and not sec_is0(28) and sec_is0(29) and sec_is0(30)) or + (not pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(3) + and pri_is0(4) and pri_is0(5) and sec_is0(21) and not sec_is0(22) + and sec_is0(23) and sec_is0(24) and sec_is0(25) and sec_is0(26) + and sec_is0(27) and sec_is0(28) and sec_is0(29)) or + (not pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(3) + and pri_is0(4) and pri_is0(5) and sec_is0(21) and not sec_is0(22) + and sec_is0(23) and sec_is0(24) and not sec_is0(25) and sec_is0(26) + and sec_is0(27) and sec_is0(28) and sec_is0(30)) or + (not pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(3) + and pri_is0(4) and pri_is0(5) and sec_is0(21) and sec_is0(23) + and sec_is0(24) and not sec_is0(25) and sec_is0(26) and not sec_is0(27) + and sec_is0(28) and sec_is0(29) and sec_is0(30)) or + (not pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(3) + and pri_is0(4) and pri_is0(5) and sec_is0(21) and not sec_is0(22) + and sec_is0(23) and sec_is0(26) and not sec_is0(27) and sec_is0(28) + and sec_is0(29) and sec_is0(30)) or + ( pri_is0(0) and pri_is0(1) and not pri_is0(2) and pri_is0(3)); + +indexed <= ( pri_is0(2) and sec_is0(20) and not sec_is0(23) and not sec_is0(25) + and not sec_is0(26) and not sec_is0(27) and not sec_is0(28) and sec_is0(29) + and sec_is0(30)) or + (not pri_is0(0) and sec_is0(21) and not sec_is0(25) and sec_is0(27) + and sec_is0(29)) or + (not pri_is0(0) and sec_is0(21) and not sec_is0(22) and not sec_is0(27)) or + (not pri_is0(0) and sec_is0(21) and sec_is0(24) and sec_is0(26) + and not sec_is0(27) and sec_is0(28) and sec_is0(29) and sec_is0(30)) or + (not pri_is0(0) and sec_is0(21) and not sec_is0(22) and not sec_is0(23) + and sec_is0(28) and not sec_is0(29)); + +update_form <= (not pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(3) + and pri_is0(4) and pri_is0(5) and sec_is0(21) and not sec_is0(22) + and sec_is0(25) and sec_is0(26) and not sec_is0(27) and sec_is0(28) + and sec_is0(29) and sec_is0(30)) or + ( pri_is0(0) and pri_is0(1) and not pri_is0(2) and pri_is0(5)); + +forcealign <= '0'; + +single_precision_ldst <= ( pri_is0(2) and not is0_instr(16) and not is0_instr(17) + and sec_is0(20) and not sec_is0(22) and not sec_is0(23) + and not sec_is0(26) and not sec_is0(27) and not sec_is0(28) + and sec_is0(29) and sec_is0(30)) or + ( pri_is0(1) and not pri_is0(2) and not pri_is0(4)) or + (not pri_is0(0) and sec_is0(21) and not sec_is0(22) + and sec_is0(28) and sec_is0(29) and not sec_is0(30)) or + (not pri_is0(0) and sec_is0(21) and not sec_is0(22) + and not sec_is0(24)); + +int_word_ldst <= (not pri_is0(0) and sec_is0(22) and sec_is0(24) + and sec_is0(26) and not sec_is0(27) and sec_is0(28) + and sec_is0(29) and sec_is0(30)) or + (not pri_is0(0) and sec_is0(21) and not sec_is0(22) + and not sec_is0(23) and sec_is0(28) and not sec_is0(29)) or + (not pri_is0(0) and sec_is0(21) and not sec_is0(25) + and not sec_is0(29)); + +sign_ext_ldst <= ( pri_is0(2) and not is0_instr(16) and not is0_instr(17) + and sec_is0(20) and not sec_is0(22) and not sec_is0(23) + and not sec_is0(26) and not sec_is0(27) and not sec_is0(28) + and sec_is0(29) and sec_is0(30)) or + (not pri_is0(0) and sec_is0(21) and not sec_is0(22) + and not sec_is0(23) and sec_is0(28) and not sec_is0(29) + and not sec_is0(30)) or + (not pri_is0(0) and sec_is0(22) and not sec_is0(23) + and sec_is0(24) and not sec_is0(25)); + +ldst_extpid <= (not pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(3) + and pri_is0(4) and pri_is0(5) and sec_is0(21) + and not sec_is0(22) and sec_is0(24) and not sec_is0(25) + and sec_is0(26) and sec_is0(27) and sec_is0(28) + and sec_is0(29) and sec_is0(30)); + +io_port <= (not pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(3) + and pri_is0(4) and pri_is0(5) and sec_is0(20) + and not sec_is0(21) and not sec_is0(22) and not sec_is0(23) + and not sec_is0(26) and not sec_is0(27) and not sec_is0(28) + and sec_is0(29) and sec_is0(30)); + +io_port_ext <= (not pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(3) + and pri_is0(4) and pri_is0(5) and sec_is0(20) + and not sec_is0(21) and not sec_is0(22) and not sec_is0(23) + and not sec_is0(25) and not sec_is0(26) and not sec_is0(27) + and not sec_is0(28) and sec_is0(29) and sec_is0(30)); + +size(0) <= '0'; + +size(1) <= '0'; + +size(2) <= (not pri_is0(0) and sec_is0(21) and not sec_is0(25) and sec_is0(27) + and sec_is0(29)) or + ( pri_is0(4) and sec_is0(21) and not sec_is0(22) and sec_is0(24) + and not sec_is0(27)) or + (not pri_is0(2) and pri_is0(4)); + +size(3) <= (not pri_is0(0) and sec_is0(21) and not sec_is0(22) and not sec_is0(24)) or + ( pri_is0(2) and sec_is0(22) and sec_is0(24) and sec_is0(26) + and not sec_is0(27) and sec_is0(28) and sec_is0(29) and sec_is0(30)) or + ( pri_is0(1) and not pri_is0(2) and not pri_is0(4)); + +size(4) <= '0'; + +size(5) <= '0'; + +cr_writer <= ( pri_is0(2) and sec_is0(20) and not sec_is0(22) and not sec_is0(23) + and not sec_is0(26) and not sec_is0(27) and not sec_is0(28) and sec_is0(29) + and sec_is0(30) and sec_is0(31)) or + ( pri_is0(0) and pri_is0(2) and not sec_is0(21) and sec_is0(24) + and sec_is0(27) and sec_is0(31)) or + ( pri_is0(0) and pri_is0(2) and not sec_is0(25) and not sec_is0(26) + and not sec_is0(29) and not sec_is0(30) and sec_is0(31)) or + ( pri_is0(2) and sec_is0(22) and not sec_is0(24) + and sec_is0(27) and sec_is0(31)) or + ( pri_is0(0) and pri_is0(2) and pri_is0(4) and not sec_is0(22) + and not sec_is0(26) and not sec_is0(27) and not sec_is0(28) + and not sec_is0(29) and not sec_is0(30)) or + ( pri_is0(0) and pri_is0(2) and not sec_is0(25) and not sec_is0(26) + and sec_is0(28) and sec_is0(29) and sec_is0(31)) or + ( pri_is0(0) and pri_is0(2) and not sec_is0(23) and not sec_is0(26) + and sec_is0(31)) or + ( pri_is0(0) and pri_is0(2) and sec_is0(26) and sec_is0(30) + and sec_is0(31)) or + ( pri_is0(0) and pri_is0(2) and sec_is0(26) and sec_is0(28) + and not sec_is0(29) and sec_is0(31)) or + ( pri_is0(0) and pri_is0(2) and sec_is0(26) and sec_is0(27) + and sec_is0(31)); + +mffgpr <= (not pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(3) + and pri_is0(4) and pri_is0(5) and sec_is0(21) + and not sec_is0(22) and not sec_is0(23) and sec_is0(24) + and sec_is0(25) and sec_is0(26) and sec_is0(27) + and sec_is0(28)) or + (not pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(3) + and pri_is0(4) and pri_is0(5) and not is0_instr(16) and sec_is0(20) + and not sec_is0(21) and not sec_is0(22) and not sec_is0(23) and not sec_is0(24) + and not sec_is0(26) and not sec_is0(27) and not sec_is0(28) and sec_is0(29) + and sec_is0(30)); + +mftgpr <= (not pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(3) + and pri_is0(4) and pri_is0(5) and sec_is0(21) and not sec_is0(22) + and sec_is0(23) and sec_is0(24) and not sec_is0(25) and sec_is0(26) + and sec_is0(27) and sec_is0(28) and not sec_is0(29) and sec_is0(30)) or + (not pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(3) + and pri_is0(4) and pri_is0(5) and sec_is0(21) and not sec_is0(22) + and sec_is0(23) and sec_is0(24) and sec_is0(25) and sec_is0(26) + and sec_is0(27) and sec_is0(28) and sec_is0(29)) or + (not pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(3) + and pri_is0(4) and pri_is0(5) and not is0_instr(16) and sec_is0(20) + and not sec_is0(21) and not sec_is0(22) and not sec_is0(23) and sec_is0(24) + and not sec_is0(26) and not sec_is0(27) and not sec_is0(28) and sec_is0(29) + and sec_is0(30)); + +fdiv_is0 <= ( pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(4) + and pri_is0(5) and sec_is0(26) and not sec_is0(27) and not sec_is0(28) + and sec_is0(29) and not sec_is0(30)); + +fsqrt_is0 <= ( pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(4) + and pri_is0(5) and sec_is0(26) and not sec_is0(27) and sec_is0(28) + and sec_is0(29) and not sec_is0(30)); + +only_from_ucode <= (not pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(3) + and pri_is0(4) and pri_is0(5) and sec_is0(21) and not sec_is0(22) + and sec_is0(24) and sec_is0(25) and sec_is0(26) and sec_is0(27) + and sec_is0(28) and sec_is0(29)) or + (not pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(3) + and pri_is0(4) and pri_is0(5) and sec_is0(21) + and not sec_is0(22) and sec_is0(23) and sec_is0(24) + and not sec_is0(25) and sec_is0(26) and sec_is0(27) + and sec_is0(28) and not sec_is0(29) and sec_is0(30)) or + (not pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(3) + and pri_is0(4) and pri_is0(5) and sec_is0(21) + and not sec_is0(22) and not sec_is0(23) and sec_is0(24) + and sec_is0(25) and sec_is0(26) and sec_is0(27) + and sec_is0(28)) or + ( pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(4) + and pri_is0(5) and sec_is0(26) and not sec_is0(27) + and not sec_is0(28) and not sec_is0(29) and sec_is0(30)) or + ( pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(3) + and pri_is0(4) and pri_is0(5) and sec_is0(26) + and not sec_is0(27) and not sec_is0(28) and not sec_is0(29)); + +final_fmul_uc <= ( pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(4) + and pri_is0(5) and sec_is0(26) and not sec_is0(27) + and not sec_is0(28) and not sec_is0(29) and sec_is0(30)); + +only_graphics_mode <= ( pri_is0(0) and pri_is0(1) and pri_is0(2) + and not pri_is0(3) and pri_is0(4) and pri_is0(5) + and not sec_is0(21) and not sec_is0(22) and sec_is0(23) + and sec_is0(24) and not sec_is0(26) and not sec_is0(27) + and sec_is0(28) and not sec_is0(29) and sec_is0(30) + and not sec_is0(31)) or + (not pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(3) + and pri_is0(4) and pri_is0(5) and sec_is0(21) + and not sec_is0(22) and not sec_is0(23) and sec_is0(24) + and sec_is0(25) and sec_is0(26) and sec_is0(27) + and sec_is0(28)) or + (not pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(3) + and pri_is0(4) and pri_is0(5) and sec_is0(21) + and not sec_is0(22) and sec_is0(23) and sec_is0(24) + and not sec_is0(25) and sec_is0(26) and sec_is0(27) + and sec_is0(28) and not sec_is0(29) and sec_is0(30)) or + (not pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(3) + and pri_is0(4) and pri_is0(5) and sec_is0(21) + and not sec_is0(22) and sec_is0(24) and sec_is0(25) + and sec_is0(26) and sec_is0(27) and sec_is0(28) + and sec_is0(29)); + + + + + + + + + + + + + +ldst_tag <= single_precision_ldst & + int_word_ldst & + sign_ext_ldst & + ldst_tag_addr(0 to 5); + +tag_in_16to20 <= mftgpr and not io_port; +mftgpr_not_DITC <= mftgpr and not io_port; + +ldst_tag_addr <= (iu_au_is0_ucode_ext(0) & is0_instr(06 to 10)) when tag_in_16to20='0' else + (iu_au_is0_ucode_ext(2) & is0_instr(16 to 20)) ; + +ram_mode_v <= pc_au_ram_mode and pc_au_ram_thread_v; + +iu_au_config_iucr_din <= iu_au_config_iucr; + + config_reg: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => iu_au_config_iucr_l2'length) + port map ( + vd => vdd, gd => gnd, + forcee => forcee, delay_lclkr => delay_lclkr, + nclk => nclk, mpw1_b => mpw1_b, + act => tiup, mpw2_b => mpw2_b, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + scin => config_reg_scin(0 to 7), + scout => config_reg_scout(0 to 7), + din => iu_au_config_iucr_din, + dout => iu_au_config_iucr_l2 + ); + + +iu_au_config_iucr_int(0 to 7) <= iu_au_config_iucr_l2(0 to 7); + + graphics_mode <= iu_au_config_iucr_int(0); +i_afd_config_iucr(1) <= iu_au_config_iucr_int(1); +i_afd_config_iucr(2) <= iu_au_config_iucr_int(2); +i_afd_config_iucr(3) <= iu_au_config_iucr_int(3); +i_afd_config_iucr(4) <= iu_au_config_iucr_int(4); +i_afd_config_iucr(5) <= iu_au_config_iucr_int(5); +i_afd_config_iucr(6) <= iu_au_config_iucr_int(6); +i_afd_config_iucr(7) <= iu_au_config_iucr_int(7); + + +spare_unused(4 to 7) <= tidn & tidn & tidn & tidn; +spare_unused(34) <= io_port_ext; + + +is0_is_ucode <= iu_au_is0_is_ucode; + +in_ucode_mode <= iu_au_is0_is_ucode and is0_instr_v; + +in_fdivsqrt_mode_is0 <= (fdiv_is0 or fsqrt_is0) and (is0_instr_v and not iu_au_is0_flush); +is0_in_divsqrt_mode_or1d <= in_fdivsqrt_mode_is0 or ucmodelat_dout; +ucmodelat_din <= (in_fdivsqrt_mode_is0 or ucmodelat_dout) and (not ifdp_ex5_fmul_uc_complete); + +au_iu_is0_ucode_only <= only_from_ucode; + + +is0_invalid_kill_uc <= (not (in_ucode_mode or ram_mode_v) and only_from_ucode) or + (not (graphics_mode or in_ucode_mode or ram_mode_v) and only_graphics_mode); + + + + +is0_invalid_kill <= (not (graphics_mode or in_ucode_mode or ram_mode_v) and only_graphics_mode); + +is0_kill_or_divsqrt_b <= not (is0_invalid_kill); + +is0_i_dec_b <= not (isfu_dec_is0 and is0_kill_or_divsqrt_b); +au_iu_is0_i_dec_b <= is0_i_dec_b; + +au_iu_is0_i_dec <= not is0_i_dec_b; +spare_unused(2) <= au_iu_is0_i_dec; + + + +ignore_flush_is0 <= (fdiv_is0 or fsqrt_is0) and isfu_dec_is0; + + is0_frt(0 to 5) <= "100001" when (fdiv_is0 ='1' or fsqrt_is0 ='1') else + iu_au_is0_ucode_ext(0) & is0_instr(06 to 10); + + +is0_st_or_mtdp <= st_is0 and not (mftgpr and not io_port); +is0_mftgpr <= st_is0 and mftgpr and not io_port; +is0_usual_fra <= not (st_is0 or mftgpr or io_port); + +is0_fra_or_frs(0 to 5) <= ((iu_au_is0_ucode_ext(0) & is0_instr(06 to 10)) and (0 to 5 => is0_st_or_mtdp)) or + ((iu_au_is0_ucode_ext(2) & is0_instr(16 to 20)) and (0 to 5 => is0_mftgpr)) or + ((iu_au_is0_ucode_ext(1) & is0_instr(11 to 15)) and (0 to 5 => is0_usual_fra)); + + +is0_to_ucode <= (iu_au_is0_2ucode or fdiv_is0 or fsqrt_is0) and isfu_dec_is0; +au_iu_is0_to_ucode <= (iu_au_is0_2ucode or fdiv_is0 or fsqrt_is0) and isfu_dec_is0; + +au_iu_is0_ldst <= ld_st_is0; +au_iu_is0_ldst_v <= ld_st_is0 and not is0_invalid_kill; +au_iu_is0_st_v <= st_is0 and not is0_invalid_kill; + +au_iu_is0_instr_type <= "001"; + +au_iu_is0_mffgpr <= mffgpr; +au_iu_is0_mftgpr <= mftgpr; + +au_iu_is0_movedp <= io_port and ld_st_is0; + +au_iu_is0_ldst_size <= size(0 to 5); +au_iu_is0_ldst_tag <= ldst_tag; +au_iu_is0_ldst_ra_v <= ld_st_is0 and (not mftgpr or (io_port and indexed)); +au_iu_is0_ldst_ra <= '0' & iu_au_is0_ucode_ext(1) & is0_instr(11 to 15) when mftgpr_not_DITC='0' else + '0' & iu_au_is0_ucode_ext(0) & is0_instr( 6 to 10); +au_iu_is0_ldst_rb_v <= (indexed or mffgpr) and ld_st_is0; +au_iu_is0_ldst_rb <= '0' & iu_au_is0_ucode_ext(2) & is0_instr(16 to 20); +au_iu_is0_ldst_dimm <= is0_instr(16 to 31); +au_iu_is0_ldst_indexed <= indexed; +au_iu_is0_ldst_update <= update_form; +au_iu_is0_ldst_forcealign <= forcealign; +au_iu_is0_ldst_forceexcept <= '0'; + +au_iu_is0_ldst_extpid <= ldst_extpid; + + + + + + + +is1_v_nstall1_b_NAND2: is1_v_nstall1_b <= not( is1_stall_b and is0_ins_v ); +is1_v_nstall2_b_NAND2: is1_v_nstall2_b <= not( is1_stall_b and is0_ins_v ); + +is1_v_nstall1_INV: is1_v_nstall1 <= not( is1_v_nstall1_b ); +is1_v_nstall2_INV: is1_v_nstall2 <= not( is1_v_nstall1_b ); +is1_v_nstall3_INV: is1_v_nstall3 <= not( is1_v_nstall1_b ); +is1_v_nstall4_INV: is1_v_nstall4 <= not( is1_v_nstall1_b ); + +is1_v_nstall5_INV: is1_v_nstall5 <= not( is1_v_nstall2_b ); +is1_v_nstall6_INV: is1_v_nstall6 <= not( is1_v_nstall2_b ); +is1_v_nstall7_INV: is1_v_nstall7 <= not( is1_v_nstall2_b ); +is1_v_nstall8_INV: is1_v_nstall8 <= not( is1_v_nstall2_b ); + + +is1_v_nstall01_INVaa: is1_v_nstall01_INVA_b <= not( is1_v_nstall1); +is1_v_nstall02_INVaa: is1_v_nstall02_INVA_b <= not( is1_v_nstall1); +is1_v_nstall03_INVaa: is1_v_nstall03_INVA_b <= not( is1_v_nstall1); +is1_v_nstall04_INVaa: is1_v_nstall04_INVA_b <= not( is1_v_nstall1); +is1_v_nstall05_INVaa: is1_v_nstall05_INVA_b <= not( is1_v_nstall2); +is1_v_nstall06_INVaa: is1_v_nstall06_INVA_b <= not( is1_v_nstall2); +is1_v_nstall07_INVaa: is1_v_nstall07_INVA_b <= not( is1_v_nstall2); +is1_v_nstall08_INVaa: is1_v_nstall08_INVA_b <= not( is1_v_nstall2); +is1_v_nstall09_INVaa: is1_v_nstall09_INVA_b <= not( is1_v_nstall3); +is1_v_nstall10_INVaa: is1_v_nstall10_INVA_b <= not( is1_v_nstall3); +is1_v_nstall11_INVaa: is1_v_nstall11_INVA_b <= not( is1_v_nstall3); +is1_v_nstall12_INVaa: is1_v_nstall12_INVA_b <= not( is1_v_nstall3); +is1_v_nstall13_INVaa: is1_v_nstall13_INVA_b <= not( is1_v_nstall4); +is1_v_nstall14_INVaa: is1_v_nstall14_INVA_b <= not( is1_v_nstall4); +is1_v_nstall15_INVaa: is1_v_nstall15_INVA_b <= not( is1_v_nstall4); +is1_v_nstall16_INVaa: is1_v_nstall16_INVA_b <= not( is1_v_nstall4); +is1_v_nstall17_INVaa: is1_v_nstall17_INVA_b <= not( is1_v_nstall5); +is1_v_nstall18_INVaa: is1_v_nstall18_INVA_b <= not( is1_v_nstall5); +is1_v_nstall19_INVaa: is1_v_nstall19_INVA_b <= not( is1_v_nstall5); +is1_v_nstall20_INVaa: is1_v_nstall20_INVA_b <= not( is1_v_nstall5); +is1_v_nstall21_INVaa: is1_v_nstall21_INVA_b <= not( is1_v_nstall6); +is1_v_nstall22_INVaa: is1_v_nstall22_INVA_b <= not( is1_v_nstall6); +is1_v_nstall23_INVaa: is1_v_nstall23_INVA_b <= not( is1_v_nstall6); +is1_v_nstall24_INVaa: is1_v_nstall24_INVA_b <= not( is1_v_nstall6); +is1_v_nstall25_INVaa: is1_v_nstall25_INVA_b <= not( is1_v_nstall7); +is1_v_nstall26_INVaa: is1_v_nstall26_INVA_b <= not( is1_v_nstall7); +is1_v_nstall27_INVaa: is1_v_nstall27_INVA_b <= not( is1_v_nstall7); +is1_v_nstall28_INVaa: is1_v_nstall28_INVA_b <= not( is1_v_nstall7); +is1_v_nstall29_INVaa: is1_v_nstall29_INVA_b <= not( is1_v_nstall8); +is1_v_nstall30_INVaa: is1_v_nstall30_INVA_b <= not( is1_v_nstall8); +is1_v_nstall31_INVaa: is1_v_nstall31_INVA_b <= not( is1_v_nstall8); +is1_v_nstall32_INVaa: is1_v_nstall32_INVA_b <= not( is1_v_nstall8); + + + +is1_v_nstall01_INVbb: is1_v_nstall01_INVB <= not( is1_v_nstall01_INVA_b ); +is1_v_nstall02_INVbb: is1_v_nstall02_INVB <= not( is1_v_nstall02_INVA_b ); +is1_v_nstall03_INVbb: is1_v_nstall03_INVB <= not( is1_v_nstall03_INVA_b ); +is1_v_nstall04_INVbb: is1_v_nstall04_INVB <= not( is1_v_nstall04_INVA_b ); +is1_v_nstall05_INVbb: is1_v_nstall05_INVB <= not( is1_v_nstall05_INVA_b ); +is1_v_nstall06_INVbb: is1_v_nstall06_INVB <= not( is1_v_nstall06_INVA_b ); +is1_v_nstall07_INVbb: is1_v_nstall07_INVB <= not( is1_v_nstall07_INVA_b ); +is1_v_nstall08_INVbb: is1_v_nstall08_INVB <= not( is1_v_nstall08_INVA_b ); +is1_v_nstall09_INVbb: is1_v_nstall09_INVB <= not( is1_v_nstall09_INVA_b ); +is1_v_nstall10_INVbb: is1_v_nstall10_INVB <= not( is1_v_nstall10_INVA_b ); +is1_v_nstall11_INVbb: is1_v_nstall11_INVB <= not( is1_v_nstall11_INVA_b ); +is1_v_nstall12_INVbb: is1_v_nstall12_INVB <= not( is1_v_nstall12_INVA_b ); +is1_v_nstall13_INVbb: is1_v_nstall13_INVB <= not( is1_v_nstall13_INVA_b ); +is1_v_nstall14_INVbb: is1_v_nstall14_INVB <= not( is1_v_nstall14_INVA_b ); +is1_v_nstall15_INVbb: is1_v_nstall15_INVB <= not( is1_v_nstall15_INVA_b ); +is1_v_nstall16_INVbb: is1_v_nstall16_INVB <= not( is1_v_nstall16_INVA_b ); +is1_v_nstall17_INVbb: is1_v_nstall17_INVB <= not( is1_v_nstall17_INVA_b ); +is1_v_nstall18_INVbb: is1_v_nstall18_INVB <= not( is1_v_nstall18_INVA_b ); +is1_v_nstall19_INVbb: is1_v_nstall19_INVB <= not( is1_v_nstall19_INVA_b ); +is1_v_nstall20_INVbb: is1_v_nstall20_INVB <= not( is1_v_nstall20_INVA_b ); +is1_v_nstall21_INVbb: is1_v_nstall21_INVB <= not( is1_v_nstall21_INVA_b ); +is1_v_nstall22_INVbb: is1_v_nstall22_INVB <= not( is1_v_nstall22_INVA_b ); +is1_v_nstall23_INVbb: is1_v_nstall23_INVB <= not( is1_v_nstall23_INVA_b ); +is1_v_nstall24_INVbb: is1_v_nstall24_INVB <= not( is1_v_nstall24_INVA_b ); +is1_v_nstall25_INVbb: is1_v_nstall25_INVB <= not( is1_v_nstall25_INVA_b ); +is1_v_nstall26_INVbb: is1_v_nstall26_INVB <= not( is1_v_nstall26_INVA_b ); +is1_v_nstall27_INVbb: is1_v_nstall27_INVB <= not( is1_v_nstall27_INVA_b ); +is1_v_nstall28_INVbb: is1_v_nstall28_INVB <= not( is1_v_nstall28_INVA_b ); +is1_v_nstall29_INVbb: is1_v_nstall29_INVB <= not( is1_v_nstall29_INVA_b ); +is1_v_nstall30_INVbb: is1_v_nstall30_INVB <= not( is1_v_nstall30_INVA_b ); +is1_v_nstall31_INVbb: is1_v_nstall31_INVB <= not( is1_v_nstall31_INVA_b ); +is1_v_nstall32_INVbb: is1_v_nstall32_INVB <= not( is1_v_nstall32_INVA_b ); + + + iu_au_is0_flush_b <= not iu_au_is0_flush ; + iu_au_is1_flush_b <= not iu_au_is1_flush ; + + cmd_is0_40_part <= ld_st_is0 and isfu_dec_is0 ; + cmd_is0_41_part <= st_is0 and isfu_dec_is0 ; + cmd_is0_43_part <= is0_ins_v and isfu_dec_is0 and not is0_invalid_kill_uc; + cmd_is0_50_part <= bubble3 and isfu_dec_is0 ; + + + cmd_is1_go_06: cmd_is0_go_b( 6) <= not( is1_v_nstall01_INVB and is0_frt(1) ); + cmd_is1_go_07: cmd_is0_go_b( 7) <= not( is1_v_nstall02_INVB and is0_frt(2) ); + cmd_is1_go_08: cmd_is0_go_b( 8) <= not( is1_v_nstall03_INVB and is0_frt(3) ); + cmd_is1_go_09: cmd_is0_go_b( 9) <= not( is1_v_nstall04_INVB and is0_frt(4) ); + cmd_is1_go_10: cmd_is0_go_b(10) <= not( is1_v_nstall05_INVB and is0_frt(5) ); + cmd_is1_go_11: cmd_is0_go_b(11) <= not( is1_v_nstall06_INVB and is0_fra_or_frs(1) ); + cmd_is1_go_12: cmd_is0_go_b(12) <= not( is1_v_nstall07_INVB and is0_fra_or_frs(2) ); + cmd_is1_go_13: cmd_is0_go_b(13) <= not( is1_v_nstall08_INVB and is0_fra_or_frs(3) ); + cmd_is1_go_14: cmd_is0_go_b(14) <= not( is1_v_nstall09_INVB and is0_fra_or_frs(4) ); + cmd_is1_go_15: cmd_is0_go_b(15) <= not( is1_v_nstall10_INVB and is0_fra_or_frs(5) ); + cmd_is1_go_16: cmd_is0_go_b(16) <= not( is1_v_nstall11_INVB and is0_ins_dly(16) ); + cmd_is1_go_17: cmd_is0_go_b(17) <= not( is1_v_nstall12_INVB and is0_ins_dly(17) ); + cmd_is1_go_18: cmd_is0_go_b(18) <= not( is1_v_nstall13_INVB and is0_ins_dly(18) ); + cmd_is1_go_19: cmd_is0_go_b(19) <= not( is1_v_nstall14_INVB and is0_ins_dly(19) ); + cmd_is1_go_20: cmd_is0_go_b(20) <= not( is1_v_nstall15_INVB and is0_ins_dly(20) ); + cmd_is1_go_21: cmd_is0_go_b(21) <= not( is1_v_nstall16_INVB and is0_ins_dly(21) ); + cmd_is1_go_22: cmd_is0_go_b(22) <= not( is1_v_nstall17_INVB and is0_ins_dly(22) ); + cmd_is1_go_23: cmd_is0_go_b(23) <= not( is1_v_nstall18_INVB and is0_ins_dly(23) ); + cmd_is1_go_24: cmd_is0_go_b(24) <= not( is1_v_nstall19_INVB and is0_ins_dly(24) ); + cmd_is1_go_25: cmd_is0_go_b(25) <= not( is1_v_nstall19_INVB and is0_ins_dly(25) ); +cmd_is0_go_b(26) <= tidn; +cmd_is0_go_b(27) <= tidn; +cmd_is0_go_b(28) <= tidn; +cmd_is0_go_b(29) <= tidn; +cmd_is0_go_b(30) <= tidn; +cmd_is0_go_b(31) <= tidn; + +spare_unused(35 to 40) <= cmd_is0_go_b(26 to 31); + + + cmd_is1_go_32: cmd_is0_go_b(32) <= not( is1_v_nstall20_INVB and is0_frt(0) ); + cmd_is1_go_33: cmd_is0_go_b(33) <= not( is1_v_nstall20_INVB and is0_fra_or_frs(0) ); + cmd_is1_go_34: cmd_is0_go_b(34) <= not( is1_v_nstall21_INVB and iu_au_is0_ucode_ext(2) ); + cmd_is1_go_35: cmd_is0_go_b(35) <= not( is1_v_nstall21_INVB and iu_au_is0_ucode_ext(3) ); + cmd_is1_go_36: cmd_is0_go_b(36) <= not( is1_v_nstall22_INVB and tv ); + cmd_is1_go_37: cmd_is0_go_b(37) <= not( is1_v_nstall22_INVB and av ); + cmd_is1_go_38: cmd_is0_go_b(38) <= not( is1_v_nstall23_INVB and bv ); + cmd_is1_go_39: cmd_is0_go_b(39) <= not( is1_v_nstall23_INVB and cv ); + cmd_is1_go_40: cmd_is0_go_b(40) <= not( is1_v_nstall29_INVB and iu_au_is0_flush_b and cmd_is0_40_part ); + cmd_is1_go_41: cmd_is0_go_b(41) <= not( is1_v_nstall30_INVB and iu_au_is0_flush_b and cmd_is0_41_part ); + cmd_is1_go_42: cmd_is0_go_b(42) <= not( is1_v_nstall24_INVB and cr_writer ); + cmd_is1_go_43: cmd_is0_go_b(43) <= not( is1_v_nstall31_INVB and iu_au_is0_flush_b and cmd_is0_43_part ); + cmd_is1_go_44: cmd_is0_go_b(44) <= not( is1_v_nstall24_INVB and is0_in_divsqrt_mode_or1d ); + cmd_is1_go_45: cmd_is0_go_b(45) <= not( is1_v_nstall25_INVB and tidn ); + cmd_is1_go_46: cmd_is0_go_b(46) <= ucode_restart; + cmd_is1_go_47: cmd_is0_go_b(47) <= not( is1_v_nstall26_INVB and is0_is_ucode ); + cmd_is1_go_48: cmd_is0_go_b(48) <= not( is1_v_nstall26_INVB and iu_au_is0_cr_setter ); + cmd_is1_go_49: cmd_is0_go_b(49) <= not( is1_v_nstall27_INVB and final_fmul_uc ); + cmd_is1_go_50: cmd_is0_go_b(50) <= not( is1_v_nstall27_INVB and cmd_is0_50_part ); + cmd_is1_go_51: cmd_is0_go_b(51) <= not( is1_v_nstall28_INVB and prebubble1 ); + cmd_is1_go_52: cmd_is0_go_b(52) <= not( is1_v_nstall32_INVB and iu_au_is0_flush_b and ignore_flush_is0 ); + cmd_is1_go_53: cmd_is0_go_b(53) <= not( is1_v_nstall28_INVB and is0_to_ucode ); + + + + + cmd_is1_ho_06: cmd_is1_ho_b( 6) <= not( is1_v_nstall01_INVA_b and is1_frt_buf(2) ); + cmd_is1_ho_07: cmd_is1_ho_b( 7) <= not( is1_v_nstall02_INVA_b and is1_frt_buf(3) ); + cmd_is1_ho_08: cmd_is1_ho_b( 8) <= not( is1_v_nstall03_INVA_b and is1_frt_buf(4) ); + cmd_is1_ho_09: cmd_is1_ho_b( 9) <= not( is1_v_nstall04_INVA_b and is1_frt_buf(5) ); + cmd_is1_ho_10: cmd_is1_ho_b(10) <= not( is1_v_nstall05_INVA_b and is1_frt_buf(6) ); + cmd_is1_ho_11: cmd_is1_ho_b(11) <= not( is1_v_nstall06_INVA_b and is1_fra_buf(2) ); + cmd_is1_ho_12: cmd_is1_ho_b(12) <= not( is1_v_nstall07_INVA_b and is1_fra_buf(3) ); + cmd_is1_ho_13: cmd_is1_ho_b(13) <= not( is1_v_nstall08_INVA_b and is1_fra_buf(4) ); + cmd_is1_ho_14: cmd_is1_ho_b(14) <= not( is1_v_nstall09_INVA_b and is1_fra_buf(5) ); + cmd_is1_ho_15: cmd_is1_ho_b(15) <= not( is1_v_nstall10_INVA_b and is1_fra_buf(6) ); + cmd_is1_ho_16: cmd_is1_ho_b(16) <= not( is1_v_nstall11_INVA_b and is1_frb_buf(2) ); + cmd_is1_ho_17: cmd_is1_ho_b(17) <= not( is1_v_nstall12_INVA_b and is1_frb_buf(3) ); + cmd_is1_ho_18: cmd_is1_ho_b(18) <= not( is1_v_nstall13_INVA_b and is1_frb_buf(4) ); + cmd_is1_ho_19: cmd_is1_ho_b(19) <= not( is1_v_nstall14_INVA_b and is1_frb_buf(5) ); + cmd_is1_ho_20: cmd_is1_ho_b(20) <= not( is1_v_nstall15_INVA_b and is1_frb_buf(6) ); + cmd_is1_ho_21: cmd_is1_ho_b(21) <= not( is1_v_nstall16_INVA_b and is1_frc_buf(2) ); + cmd_is1_ho_22: cmd_is1_ho_b(22) <= not( is1_v_nstall16_INVA_b and is1_frc_buf(3) ); + cmd_is1_ho_23: cmd_is1_ho_b(23) <= not( is1_v_nstall17_INVA_b and is1_frc_buf(4) ); + cmd_is1_ho_24: cmd_is1_ho_b(24) <= not( is1_v_nstall17_INVA_b and is1_frc_buf(5) ); + cmd_is1_ho_25: cmd_is1_ho_b(25) <= not( is1_v_nstall18_INVA_b and is1_frc_buf(6) ); +cmd_is1_ho_b(26) <= tidn; +cmd_is1_ho_b(27) <= tidn; +cmd_is1_ho_b(28) <= tidn; +cmd_is1_ho_b(29) <= tidn; +cmd_is1_ho_b(30) <= tidn; +cmd_is1_ho_b(31) <= tidn; +spare_unused(41 to 46) <= cmd_is1_ho_b(26 to 31); + + cmd_is1_ho_32: cmd_is1_ho_b(32) <= not( is1_v_nstall18_INVA_b and is1_frt_buf(1) ); + cmd_is1_ho_33: cmd_is1_ho_b(33) <= not( is1_v_nstall19_INVA_b and is1_fra_buf(1) ); + cmd_is1_ho_34: cmd_is1_ho_b(34) <= not( is1_v_nstall19_INVA_b and is1_frb_buf(1) ); + cmd_is1_ho_35: cmd_is1_ho_b(35) <= not( is1_v_nstall20_INVA_b and is1_frc_buf(1) ); + cmd_is1_ho_36: cmd_is1_ho_b(36) <= not( is1_v_nstall20_INVA_b and cmd_is1_l2(36) ); + cmd_is1_ho_37: cmd_is1_ho_b(37) <= not( is1_v_nstall21_INVA_b and cmd_is1_l2(37) ); + cmd_is1_ho_38: cmd_is1_ho_b(38) <= not( is1_v_nstall21_INVA_b and cmd_is1_l2(38) ); + cmd_is1_ho_39: cmd_is1_ho_b(39) <= not( is1_v_nstall22_INVA_b and cmd_is1_l2(39) ); + cmd_is1_ho_40: cmd_is1_ho_b(40) <= not( is1_v_nstall26_INVA_b and iu_au_is1_flush_b and is1_stall and cmd_is1_l2(40) ); + cmd_is1_ho_41: cmd_is1_ho_b(41) <= not( is1_v_nstall27_INVA_b and iu_au_is1_flush_b and is1_stall and cmd_is1_l2(41) ); + cmd_is1_ho_42: cmd_is1_ho_b(42) <= not( is1_v_nstall22_INVA_b and cmd_is1_l2(42) ); + cmd_is1_ho_43: cmd_is1_ho_b(43) <= not( is1_v_nstall28_INVA_b and iu_au_is1_flush_b and is1_stall and cmd_is1_l2(43) ); + cmd_is1_ho_44: cmd_is1_ho_b(44) <= not( is1_v_nstall29_INVA_b and iu_au_is1_flush_b and is1_stall and cmd_is1_l2(44) ); + cmd_is1_ho_45: cmd_is1_ho_b(45) <= not( is1_v_nstall23_INVA_b and cmd_is1_l2(45) ); + cmd_is1_ho_46: cmd_is1_ho_b(46) <= tidn; + cmd_is1_ho_47: cmd_is1_ho_b(47) <= not( is1_v_nstall24_INVA_b and cmd_is1_l2(47) ); + cmd_is1_ho_48: cmd_is1_ho_b(48) <= not( is1_v_nstall24_INVA_b and cmd_is1_l2(48) ); + cmd_is1_ho_49: cmd_is1_ho_b(49) <= not( is1_v_nstall30_INVA_b and iu_au_is1_flush_b and is1_stall and cmd_is1_l2(49) ); + cmd_is1_ho_50: cmd_is1_ho_b(50) <= not( is1_v_nstall31_INVA_b and iu_au_is1_flush_b and is1_stall and cmd_is1_l2(50) ); + cmd_is1_ho_51: cmd_is1_ho_b(51) <= not( is1_v_nstall25_INVA_b and cmd_is1_l2(51) ); + cmd_is1_ho_52: cmd_is1_ho_b(52) <= not( is1_v_nstall32_INVA_b and iu_au_is1_flush_b and is1_stall and cmd_is1_l2(52) ); + cmd_is1_ho_53: cmd_is1_ho_b(53) <= not( is1_v_nstall25_INVA_b and cmd_is1_l2(53) ); + + + + + + + is1_cmd_din_a: cmd_is0_ld(06 to 25) <= not( cmd_is0_go_b(6 to 25) and cmd_is1_ho_b(6 to 25) ); + is1_cmd_din_b: cmd_is0_ld(32 to 53) <= not( cmd_is0_go_b(32 to 53) and cmd_is1_ho_b(32 to 53) ); + + + cmd_is0_ld(26) <= ucmodelat_din; + + cmd_is0_ld(27 to 31) <= cmd_is1_l2(27 to 31); + + + cmd_reg_is1: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, ibuf => false, width => 48) + port map ( + vd => vdd, gd => gnd, + forcee => forcee, delay_lclkr => delay_lclkr, + nclk => nclk, mpw1_b => mpw1_b, + act => tiup, mpw2_b => mpw2_b, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + scin => cmd_is1_scin(6 to 53), + scout => cmd_is1_scout(6 to 53), + din => cmd_is0_ld, + dout => cmd_is1_l2 + ); + + + + ucmodelat_dout <= cmd_is1_l2(26); + + i_afd_fmul_uc_is1 <= cmd_is1_l2(49); + is1_fmul_uc <= cmd_is1_l2(49); + + i_afd_is1_is_ucode <= cmd_is1_l2(47); + i_afd_is1_to_ucode <= cmd_is1_l2(53); + is1_is_ucode <= cmd_is1_l2(47); + is1_to_ucode <= cmd_is1_l2(53); + + spare_unused(3) <= tidn; + spare_unused(8 to 11) <= tidn & tidn & tidn & tidn; + + + + + is1_instr_v <= cmd_is1_l2(43); + is1_ldst <= cmd_is1_l2(40); + is1_st <= cmd_is1_l2(41); + + + + + i_afd_is1_frt(0 to 6) <= tidn & cmd_is1_l2(32) & cmd_is1_l2(06 to 10); + + i_afd_is1_fra(0 to 6) <= tidn & cmd_is1_l2(33) & cmd_is1_l2(11 to 15); + + i_afd_is1_frb(0 to 6) <= tidn & cmd_is1_l2(34) & cmd_is1_l2(16 to 20); + + i_afd_is1_frc(0 to 6) <= tidn & cmd_is1_l2(35) & cmd_is1_l2(21 to 25); + + is1frtbufa: is1_frt_buf_b <= not (cmd_is1_l2(32) & cmd_is1_l2(06 to 10)); + is1frabufa: is1_fra_buf_b <= not (cmd_is1_l2(33) & cmd_is1_l2(11 to 15)); + is1frbbufa: is1_frb_buf_b <= not (cmd_is1_l2(34) & cmd_is1_l2(16 to 20)); + is1frcbufa: is1_frc_buf_b <= not (cmd_is1_l2(35) & cmd_is1_l2(21 to 25)); + + is1frtbufb: is1_frt_buf <= not is1_frt_buf_b; + is1frabufb: is1_fra_buf <= not is1_fra_buf_b; + is1frbbufb: is1_frb_buf <= not is1_frb_buf_b; + is1frcbufb: is1_frc_buf <= not is1_frc_buf_b; + + i_afd_is1_frt_buf <= is1_frt_buf; + i_afd_is1_fra_buf <= is1_fra_buf; + i_afd_is1_frb_buf <= is1_frb_buf; + i_afd_is1_frc_buf <= is1_frc_buf; + + + i_afd_is1_est_bubble3 <= cmd_is1_l2(50); + i_afd_is1_prebubble1 <= cmd_is1_l2(51) or cmd_is1_l2(52); + + i_afd_is1_instr_v <= is1_instr_v; + + + i_afd_is1_cr_writer <= cmd_is1_l2(42); + is1_cr_writer <= cmd_is1_l2(42); + spare_unused(47) <= cmd_is1_l2(46); + + i_afd_is1_cr_setter <= cmd_is1_l2(48); + is1_cr_setter <= cmd_is1_l2(48); + + is1_in_divsqrt_mode_or1d <= cmd_is1_l2(44); + i_afd_in_ucode_mode_or1d <= is1_in_divsqrt_mode_or1d; + + i_afd_is1_frt_v <= cmd_is1_l2(36); + i_afd_is1_fra_v <= cmd_is1_l2(37); + i_afd_is1_frb_v <= cmd_is1_l2(38); + i_afd_is1_frc_v <= cmd_is1_l2(39); + is1_frt_v <= cmd_is1_l2(36); + is1_fra_v <= cmd_is1_l2(37); + is1_frb_v <= cmd_is1_l2(38); + is1_frc_v <= cmd_is1_l2(39); + + i_afd_is1_instr_ldst_v <= is1_ldst; + i_afd_is1_instr_ld_v <= is1_ldst and not is1_st; + i_afd_is1_instr_sto_v <= is1_st; + + i_afd_is1_divsqrt <= cmd_is1_l2(52); + i_afd_is1_stall_rep <= is1_stall; + + + i_afd_ignore_flush_is1 <= cmd_is1_l2(52) ; + + + + + + + +fu_dec_debug(0 to 13) <= is1_instr_v & + is1_frt_v & + is1_fra_v & + is1_frb_v & + is1_frc_v & + is1_ldst & + is1_st & + is1_cr_setter & + is1_cr_writer & + is1_is_ucode & + is1_to_ucode & + is1_frt_buf(1) & + is1_fmul_uc & + is1_in_divsqrt_mode_or1d; + + + + + + + + + +config_reg_scin(0) <= i_dec_si; +config_reg_scin(1 to 7) <= config_reg_scout(0 to 6); + +cmd_is1_scin(6) <= config_reg_scout(7); +cmd_is1_scin(7 to 53) <= cmd_is1_scout(6 to 52); + +i_dec_so <= cmd_is1_scout(53); + + +end iuq_axu_fu_dec; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_axu_fu_dep.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_axu_fu_dep.vhdl new file mode 100644 index 0000000..80fe8d5 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_axu_fu_dep.vhdl @@ -0,0 +1,1931 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + use work.iuq_pkg.all; + + + +entity iuq_axu_fu_dep is +generic( + expand_type : integer := 2; + fpr_addr_width : integer := 5; + lmq_entries : integer := 8; + needs_sreset : integer := 1); +port( + nclk : in clk_logic; + vdd : inout power_logic; + gnd : inout power_logic; + i_dep_si : in std_ulogic; + i_dep_so : out std_ulogic; + + pc_iu_func_sl_thold_0_b : in std_ulogic; + pc_iu_sg_0 : in std_ulogic; + forcee : in std_ulogic; + d_mode : in std_ulogic; + delay_lclkr : in std_ulogic; + mpw1_b : in std_ulogic; + mpw2_b : in std_ulogic; + + + i_afd_is1_is_ucode : in std_ulogic; + i_afd_is1_to_ucode : in std_ulogic; + i_afd_is2_is_ucode : out std_ulogic; + + i_afd_config_iucr : in std_ulogic_vector(1 to 7); + + + i_afd_is1_instr_v : in std_ulogic; + i_afd_is1_instr : in std_ulogic_vector(26 to 31); + + i_afd_is1_fra_v : in std_ulogic; + i_afd_is1_frb_v : in std_ulogic; + i_afd_is1_frc_v : in std_ulogic; + i_afd_is1_frt_v : in std_ulogic; + + i_afd_is1_prebubble1 : in std_ulogic; + i_afd_is1_est_bubble3 : in std_ulogic; + + iu_au_is1_cr_user_v : in std_ulogic; + i_afd_is1_cr_setter : in std_ulogic; + i_afd_is1_cr_writer : in std_ulogic; + + i_afd_is1_fra : in std_ulogic_vector(0 to 6); + i_afd_is1_frb : in std_ulogic_vector(0 to 6); + i_afd_is1_frc : in std_ulogic_vector(0 to 6); + i_afd_is1_frt : in std_ulogic_vector(0 to 6); + i_afd_is1_fra_buf : in std_ulogic_vector(1 to 6); + i_afd_is1_frb_buf : in std_ulogic_vector(1 to 6); + i_afd_is1_frc_buf : in std_ulogic_vector(1 to 6); + i_afd_is1_frt_buf : in std_ulogic_vector(1 to 6); + + i_afd_is1_ifar : in std_ulogic_vector(56 to 61); + + i_afd_is1_instr_ldst_v : in std_ulogic; + i_afd_is1_instr_ld_v : in std_ulogic; + i_afd_is1_instr_sto_v : in std_ulogic; + + + i_afi_is2_take : in std_ulogic; + + xu_au_loadmiss_vld : in std_ulogic; + xu_au_loadmiss_qentry : in std_ulogic_vector(0 to lmq_entries-1); + xu_au_loadmiss_target : in std_ulogic_vector(0 to 8); + xu_au_loadmiss_target_type : in std_ulogic_vector(0 to 1); + + xu_au_loadmiss_complete_vld : in std_ulogic; + xu_au_loadmiss_complete_qentry : in std_ulogic_vector(0 to lmq_entries-1); + xu_au_loadmiss_complete_type : in std_ulogic_vector(0 to 1); + + iu_au_is1_hold : in std_ulogic; + + iu_au_is1_instr_match : in std_ulogic; + + iu_au_is2_stall : in std_ulogic; + + xu_iu_is2_flush : in std_ulogic; + + iu_au_is1_flush : in std_ulogic; + iu_au_is2_flush : in std_ulogic; + iu_au_rf0_flush : in std_ulogic; + iu_au_rf1_flush : in std_ulogic; + iu_au_ex1_flush : in std_ulogic; + iu_au_ex2_flush : in std_ulogic; + iu_au_ex3_flush : in std_ulogic; + iu_au_ex4_flush : in std_ulogic; + iu_au_ex5_flush : in std_ulogic; + + au_iu_is1_dep_hit : out std_ulogic; + au_iu_is1_dep_hit_b : out std_ulogic; + + au_iu_is2_issue_stall : out std_ulogic; + + i_axu_is1_early_v : out std_ulogic; + + i_axu_is2_instr_v : out std_ulogic; + + i_axu_is2_instr_match : out std_ulogic; + + i_axu_is2_fra : out std_ulogic_vector(0 to 6); + i_axu_is2_frb : out std_ulogic_vector(0 to 6); + i_axu_is2_frc : out std_ulogic_vector(0 to 6); + i_axu_is2_frt : out std_ulogic_vector(0 to 6); + + i_axu_is2_fra_v : out std_ulogic; + i_axu_is2_frb_v : out std_ulogic; + i_axu_is2_frc_v : out std_ulogic; + + + fu_iu_uc_special : in std_ulogic; + + iu_fu_ex2_n_flush : out std_ulogic; + + + ifdp_is2_est_bubble3 : out std_ulogic; + ifdp_ex5_fmul_uc_complete : out std_ulogic; + ifdp_is2_bypsel : out std_ulogic_vector(0 to 5); + + i_afd_ignore_flush_is1 : in std_ulogic; + i_afd_ignore_flush_is2 : out std_ulogic; + + i_afd_is1_divsqrt : in std_ulogic; + i_afd_is1_stall_rep : in std_ulogic; + + i_afd_fmul_uc_is1 : in std_ulogic; + i_afd_in_ucode_mode_or1d : in std_ulogic; + i_afd_in_ucode_mode_or1d_b : out std_ulogic; + + fu_dep_debug : out std_ulogic_vector(0 to 23); + au_iu_is2_axubusy : out std_ulogic + + + ); + + -- synopsys translate_off + + -- synopsys translate_on + + +end iuq_axu_fu_dep; + + +architecture iuq_axu_fu_dep of iuq_axu_fu_dep is + +signal tidn : std_ulogic; +signal tiup : std_ulogic; + +signal is1_ex6_a_bypass, is1_ex6_b_bypass, is1_ex6_c_bypass : std_ulogic; + +signal spare_unused : std_ulogic_vector(00 to 58); +signal iucr2_ss_ignore_flush,disable_cgat : std_ulogic; + +signal lm_tar : std_ulogic_vector(0 to 5); +signal lm0_valid : std_ulogic; +signal lm0_valid_din : std_ulogic; +signal lm0_ta : std_ulogic_vector(0 to 5); +signal lm0_ta_din : std_ulogic_vector(0 to 5); +signal lm1_valid : std_ulogic; +signal lm1_valid_din : std_ulogic; +signal lm1_ta : std_ulogic_vector(0 to 5); +signal lm1_ta_din : std_ulogic_vector(0 to 5); +signal lm2_valid : std_ulogic; +signal lm2_valid_din : std_ulogic; +signal lm2_ta : std_ulogic_vector(0 to 5); +signal lm2_ta_din : std_ulogic_vector(0 to 5); +signal lm3_valid : std_ulogic; +signal lm3_valid_din : std_ulogic; +signal lm3_ta : std_ulogic_vector(0 to 5); +signal lm3_ta_din : std_ulogic_vector(0 to 5); +signal lm4_valid : std_ulogic; +signal lm4_valid_din : std_ulogic; +signal lm4_ta : std_ulogic_vector(0 to 5); +signal lm4_ta_din : std_ulogic_vector(0 to 5); +signal lm5_valid : std_ulogic; +signal lm5_valid_din : std_ulogic; +signal lm5_ta : std_ulogic_vector(0 to 5); +signal lm5_ta_din : std_ulogic_vector(0 to 5); +signal lm6_valid : std_ulogic; +signal lm6_valid_din : std_ulogic; +signal lm6_ta : std_ulogic_vector(0 to 5); +signal lm6_ta_din : std_ulogic_vector(0 to 5); +signal lm7_valid : std_ulogic; +signal lm7_valid_din : std_ulogic; +signal lm7_ta : std_ulogic_vector(0 to 5); +signal lm7_ta_din : std_ulogic_vector(0 to 5); + +signal lmiss_qentry : std_ulogic_vector(0 to 7); +signal lmiss_complete : std_ulogic_vector(0 to 7); +signal lmiss_comp_v : std_ulogic; +signal lmiss_comp, lmiss_comp_ex0, lmiss_comp_ex1, lmiss_comp_ex2, lmiss_comp_ex3 : std_ulogic_vector(0 to 7); + +signal lmiss_comp_ex1_latch_scout, lmiss_comp_ex1_latch_scin : std_ulogic_vector(0 to 7); +signal lmiss_comp_ex2_latch_scout, lmiss_comp_ex2_latch_scin : std_ulogic_vector(0 to 7); +signal lmiss_comp_ex3_latch_scout, lmiss_comp_ex3_latch_scin : std_ulogic_vector(0 to 7); +signal lmc_ex4_latch_scin, lmc_ex4_latch_scout : std_ulogic_vector(0 to 6); +signal lmc_ex5_latch_scin, lmc_ex5_latch_scout : std_ulogic; +signal lmc_ex6_latch_scin, lmc_ex6_latch_scout : std_ulogic; + + +signal is1_cancel_bypass : std_ulogic; +signal is1_bypsel : std_ulogic_vector(0 to 5); +signal is2_bypsel : std_ulogic_vector(0 to 5); + +signal spare_l2 : std_ulogic_vector(0 to 4); + +signal is2_frt_v_din, rf1_frt_v_din, rf0_frt_v_din : std_ulogic; +signal ex1_frt_v_din, ex2_frt_v_din, ex3_frt_v_din: std_ulogic; +signal disable_bypass_chicken_switch, dis_byp_is1: std_ulogic; +signal is1_ld_v, is1_ld_v_din : std_ulogic; +signal is2_ld_v, is2_ld_v_din : std_ulogic; +signal rf0_ld_v_din : std_ulogic; +signal rf1_ld_v_din : std_ulogic; +signal ex1_ld_v_din : std_ulogic; +signal ex2_ld_v_din : std_ulogic; +signal ex3_ld_v_din : std_ulogic; + +signal rf0_ld_v : std_ulogic; +signal rf1_ld_v : std_ulogic; +signal ex1_ld_v, ex2_ld_v, ex3_ld_v, ex4_ld_v: std_ulogic; + + +signal bubble3_is1, bubble3_is2 : std_ulogic; +signal bubble3_rf0, bubble3_rf1, bubble3_ex1 : std_ulogic; + +signal bubble3_is1_db : std_ulogic; + +signal bubble3_is2_din : std_ulogic; +signal bubble3_rf0_din, bubble3_rf1_din : std_ulogic; + + +signal is1_fra : std_ulogic_vector(0 to 5); +signal is1_frb : std_ulogic_vector(0 to 5); +signal is1_frc : std_ulogic_vector(0 to 5); + +signal is2_fra : std_ulogic_vector(0 to 5); +signal is2_frb : std_ulogic_vector(0 to 5); +signal is2_frc : std_ulogic_vector(0 to 5); + +signal is1_ldst_v : std_ulogic ; +signal is2_act, rf0_act, rf1_act, ex1_act, ex2_act, ex3_act : std_ulogic; +signal is2_act_l2, rf0_act_l2, rf1_act_l2, ex1_act_l2, ex2_act_l2, ex3_act_l2 : std_ulogic; +signal is2_act_din, rf0_act_din, rf1_act_din, ex1_act_din, ex2_act_din, ex3_act_din : std_ulogic; + +signal is1_fra_v : std_ulogic; +signal is1_frb_v : std_ulogic; +signal is1_frc_v : std_ulogic; +signal is1_crs_v : std_ulogic; + +signal is2_fra_v : std_ulogic; +signal is2_frb_v : std_ulogic; +signal is2_frc_v : std_ulogic; + +signal is1_prebubble_skip : std_ulogic; + +signal is1_frt_v : std_ulogic; +signal is2_frt_v : std_ulogic; +signal rf0_frt_v : std_ulogic; +signal rf1_frt_v : std_ulogic; +signal ex1_frt_v, ex2_frt_v, ex3_frt_v, ex4_frt_v: std_ulogic; + +signal ex3_frt_v_forbyp : std_ulogic; + +signal is1_instr_v : std_ulogic; +signal is2_instr_v : std_ulogic; +signal rf0_instr_v : std_ulogic; +signal rf1_instr_v : std_ulogic; +signal ex1_instr_v, ex2_instr_v, ex3_instr_v, ex4_instr_v, ex5_instr_v, ex6_instr_v : std_ulogic; + +signal is1_instr_v_din : std_ulogic; +signal is2_instr_v_din : std_ulogic; +signal rf0_instr_v_din : std_ulogic; +signal rf1_instr_v_din : std_ulogic; +signal ex1_instr_v_din, ex2_instr_v_din, ex3_instr_v_din, ex4_instr_v_din, ex5_instr_v_din: std_ulogic; + +signal is1_fmul_uc_din : std_ulogic; +signal is2_fmul_uc_din : std_ulogic; +signal rf0_fmul_uc_din : std_ulogic; +signal rf1_fmul_uc_din : std_ulogic; +signal ex1_fmul_uc_din, ex2_fmul_uc_din, ex3_fmul_uc_din, ex4_fmul_uc_din, ex5_fmul_uc_din: std_ulogic; +signal is1_fmul_uc : std_ulogic; +signal is2_fmul_uc : std_ulogic; +signal rf0_fmul_uc : std_ulogic; +signal rf1_fmul_uc : std_ulogic; +signal ex1_fmul_uc, ex2_fmul_uc, ex3_fmul_uc, ex4_fmul_uc, ex5_fmul_uc: std_ulogic; + + +signal is1_lmq_waw_hit, is1_lmq_waw_hit_b, is1_waw_cr_hit : std_ulogic; + +signal is1_ta : std_ulogic_vector(0 to 5); +signal is2_ta : std_ulogic_vector(0 to 5); +signal rf0_ta : std_ulogic_vector(0 to 5); +signal rf1_ta : std_ulogic_vector(0 to 5); +signal ex1_ta : std_ulogic_vector(0 to 5); +signal ex2_ta : std_ulogic_vector(0 to 5); +signal ex3_ta : std_ulogic_vector(0 to 5); +signal ex4_ta : std_ulogic_vector(0 to 5); + + + +signal is1_crt_v, is1_crt_v_din: std_ulogic; +signal is2_crt_v, is2_crt_v_din: std_ulogic; +signal rf0_crt_v, rf0_crt_v_din: std_ulogic; +signal rf1_crt_v, rf1_crt_v_din: std_ulogic; +signal ex1_crt_v, ex1_crt_v_din: std_ulogic; +signal ex2_crt_v, ex2_crt_v_din: std_ulogic; +signal ex3_crt_v, ex3_crt_v_din: std_ulogic; +signal ex4_crt_v: std_ulogic; + +signal raw_cr_hit : std_ulogic; +signal is1_store_v : std_ulogic; +signal raw_fra_hit, raw_frb_hit, raw_frc_hit, is1_raw_hit, is1_dep_hit: std_ulogic; +signal raw_fra_hit_b, raw_frb_hit_b, raw_frc_hit_b, is1_dep_hit_b, is1_dep_hit_buf1,is1_dep_hit_buf2_b : std_ulogic; +signal is1_waw_load_hit : std_ulogic; +signal stall_is2_b : std_ulogic; +signal stall_is2 : std_ulogic; + +signal is1_stage_din, is1_stage_din_premux : std_ulogic_vector(0 to 42); +signal is2_stage_dout_premux : std_ulogic_vector(0 to 42); +signal is2_stage_dout : std_ulogic_vector(0 to 42); +signal is2_stage_latch_scin : std_ulogic_vector(0 to 42); +signal is2_stage_latch_scout : std_ulogic_vector(0 to 42); + +signal is2_instr_ldst_v : std_ulogic; +signal is2_bypass_latch_scin, is2_bypass_latch_scout : std_ulogic_vector(0 to 5); +signal rf0_sp_latch_scin, rf0_sp_latch_scout : std_ulogic_vector(0 to 14); +signal rf1_sp_latch_scin, rf1_sp_latch_scout : std_ulogic_vector(0 to 14); +signal ex1_sp_latch_scin, ex1_sp_latch_scout : std_ulogic_vector(0 to 14); +signal ex2_sp_latch_scin, ex2_sp_latch_scout : std_ulogic_vector(0 to 13); +signal ex3_sp_latch_scin, ex3_sp_latch_scout : std_ulogic_vector(0 to 13); +signal ex4_sp_latch_scin, ex4_sp_latch_scout : std_ulogic_vector(0 to 12); +signal ex5_sp_latch_scin, ex5_sp_latch_scout : std_ulogic_vector(0 to 10); +signal ex6_sp_latch_scin, ex6_sp_latch_scout : std_ulogic_vector(0 to 1); +signal busy_latch_scin, busy_latch_scout : std_ulogic_vector(0 to 2); +signal act_latch_scin, act_latch_scout : std_ulogic_vector(0 to 7); + +signal lmq0_latch_scin,lmq0_latch_scout : std_ulogic_vector(0 to 6); +signal lmq1_latch_scin,lmq1_latch_scout : std_ulogic_vector(0 to 6); +signal lmq2_latch_scin,lmq2_latch_scout : std_ulogic_vector(0 to 6); +signal lmq3_latch_scin,lmq3_latch_scout : std_ulogic_vector(0 to 6); +signal lmq4_latch_scin,lmq4_latch_scout : std_ulogic_vector(0 to 6); +signal lmq5_latch_scin,lmq5_latch_scout : std_ulogic_vector(0 to 6); +signal lmq6_latch_scin,lmq6_latch_scout : std_ulogic_vector(0 to 6); +signal lmq7_latch_scin,lmq7_latch_scout : std_ulogic_vector(0 to 6); + +signal is1_cmiss_flush : std_ulogic; +signal is2_cmiss_flush : std_ulogic; +signal is2_cmiss_flush_q : std_ulogic; +signal is2_cmiss_flush_din : std_ulogic; +signal rf0_cmiss_flush : std_ulogic; +signal rf1_cmiss_flush : std_ulogic; +signal ex1_cmiss_flush : std_ulogic; +signal ex2_cmiss_flush : std_ulogic; +signal rf0_cmiss_flush_din : std_ulogic; +signal rf1_cmiss_flush_din : std_ulogic; +signal ex1_cmiss_flush_din : std_ulogic; + +signal rf0_cmiss_waw_flush : std_ulogic; +signal rf1_cmiss_waw_flush : std_ulogic; +signal ex1_cmiss_waw_flush : std_ulogic; + +signal ignore_flush_is1, ignore_flush_is2 : std_ulogic; +signal ignore_flush_rf0, ignore_flush_rf1 : std_ulogic; +signal ignore_flush_ex1, ignore_flush_ex2 : std_ulogic; +signal ignore_flush_ex3, ignore_flush_ex4 : std_ulogic; +signal ignore_flush_ex5, ignore_flush_ex6 : std_ulogic; + +signal ignore_flush_rf0_din, ignore_flush_rf1_din : std_ulogic; +signal ignore_flush_ex1_din, ignore_flush_ex2_din : std_ulogic; +signal ignore_flush_ex3_din, ignore_flush_ex4_din : std_ulogic; +signal ignore_flush_ex5_din, ignore_flush_is2_din : std_ulogic; + + + + +signal is1_hold_v_b : std_ulogic; +signal is1_WAW_CRorLDhit_b : std_ulogic; +signal is1_allbut_RAW : std_ulogic; +signal is1_raw_hit_b : std_ulogic; + +signal debug_scin :std_ulogic_vector(0 to 15); +signal debug_scout :std_ulogic_vector(0 to 15); + +signal uc_rc_ld :std_ulogic; +signal uc_rc_l2 :std_ulogic; +signal uc_end_is1 :std_ulogic; +signal ppc_rc_latch_scin :std_ulogic; +signal ppc_rc_latch_scout :std_ulogic; +signal raw_frb_uc_hit_b, raw_frb_uc_hit :std_ulogic; +signal is1_dep_hit_db :std_ulogic; +signal is1_raw_hit_db :std_ulogic; +signal raw_fra_hit_db :std_ulogic; +signal raw_frb_hit_db :std_ulogic; +signal raw_frc_hit_db :std_ulogic; +signal is1_prebubble_skip_db :std_ulogic; +signal is1_instr_v_din_db :std_ulogic; +signal raw_cr_hit_db :std_ulogic; +signal is1_raw_hit_earlystuff_b :std_ulogic; +signal is1_lmq_waw_hit_db :std_ulogic; +signal is1_waw_load_hit_db :std_ulogic; +signal iu_au_is1_hold_db :std_ulogic; +signal iu_au_is2_stall_db :std_ulogic; +signal iu_au_is1_flush_db :std_ulogic; +signal iu_au_is2_flush_db :std_ulogic; +signal iu_au_rf0_flush_db :std_ulogic; + +signal lmiss_comp_type :std_ulogic_vector(0 to 1); + +signal lm_v :std_ulogic_vector(0 to 7); +signal set_lm0, set_lm0_1d, clear_lm0 :std_ulogic; +signal set_lm1, set_lm1_1d, clear_lm1 :std_ulogic; +signal set_lm2, set_lm2_1d, clear_lm2 :std_ulogic; +signal set_lm3, set_lm3_1d, clear_lm3 :std_ulogic; +signal set_lm4, set_lm4_1d, clear_lm4 :std_ulogic; +signal set_lm5, set_lm5_1d, clear_lm5 :std_ulogic; +signal set_lm6, set_lm6_1d, clear_lm6 :std_ulogic; +signal set_lm7, set_lm7_1d, clear_lm7 :std_ulogic; + + +signal lmc_ex3, lmc_ex4 :std_ulogic_vector(0 to 5); +signal lmc_ex3_v, lmc_ex4_v, lmc_ex5_v, lmc_ex6_v :std_ulogic; + +signal is1_ld6_a_bypass, is1_ld6_b_bypass, is1_ld6_c_bypass :std_ulogic; + +signal ppc_div_sqrt_is1 :std_ulogic; + +signal fu_busy,fu_busy_l2 :std_ulogic; + +signal is1_to_ucode, is1_is_ucode, is1_singlestep_ucode ,is1_singlestep_pn , is1_singlestep :std_ulogic; +signal config_iucr :std_ulogic_vector(1 to 7); +signal is2_axubusy, fmul_uc_busy, fmul_uc_busy_l2, ignore_flush_busy, ignore_flush_busy_l2, is2_ignore_flush_busy :std_ulogic; + +signal is1_stall_rep_b, is1_stall_rep, uc_rc_adv, uc_rc_go_b, uc_rc_ho_b :std_ulogic; + + + + + + + + + + + + + + + + +begin + + + + +tidn <= '0'; +tiup <= '1'; + + + +spare_unused(49) <= d_mode; +spare_unused(43 to 48) <= i_afd_is1_fra_buf(1 to 6); +spare_unused(37 to 42) <= i_afd_is1_frb_buf(1 to 6); +spare_unused(31 to 36) <= i_afd_is1_frc_buf(1 to 6); +spare_unused(25 to 30) <= i_afd_is1_frt_buf(1 to 6); +spare_unused(24) <= i_afd_is1_instr_sto_v; + +spare_unused(18 to 22) <= i_afd_is1_instr(26 to 30); +spare_unused(17) <= i_afd_is1_fra(0); +spare_unused(16) <= i_afd_is1_frb(0); +spare_unused(15) <= i_afd_is1_frc(0); + +spare_unused(23) <= tidn; +spare_unused(11) <= tidn; +spare_unused(12) <= tidn; +spare_unused(13) <= tidn; + + +uc_end_is1 <= is1_fmul_uc and is1_instr_v; +spare_unused(50 to 55) <= i_afd_is1_ifar(56 to 61); + + + + + is1_stall_rep_b <= not i_afd_is1_stall_rep ; + is1_stall_rep <= i_afd_is1_stall_rep ; + uc_rc_adv <= (i_afd_is1_divsqrt and i_afd_is1_instr(31)) or (not i_afd_is1_divsqrt and uc_rc_l2); + + +uc_rc_go: uc_rc_go_b <= not( is1_stall_rep_b and uc_rc_adv ); +uc_rc_ho: uc_rc_ho_b <= not( is1_stall_rep and uc_rc_l2 ); +uc_rc_do: uc_rc_ld <= not( uc_rc_go_b and uc_rc_ho_b ); + + + ppc_rc_latch: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 1) + port map ( + nclk => nclk, vd => vdd, gd => gnd, + forcee => forcee, mpw1_b => mpw1_b, mpw2_b => mpw2_b, + delay_lclkr => delay_lclkr, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + scin(0) => ppc_rc_latch_scin, + scout(0) => ppc_rc_latch_scout, + din(0) => uc_rc_ld, + dout(0) => uc_rc_l2 + ); + + + +is1_ta(0 to 5) <= i_afd_is1_frt(1 to 6); + + +is1_frt_v <= i_afd_is1_frt_v; + +is1_fra(0 to 5) <= i_afd_is1_fra(1 to 6); + +is1_frb(0 to 5) <= i_afd_is1_frb(1 to 6); + +is1_frc(0 to 5) <= i_afd_is1_frc(1 to 6); + + + + +is1_fra_v <= i_afd_is1_fra_v; +is1_frb_v <= i_afd_is1_frb_v; +is1_frc_v <= i_afd_is1_frc_v; + +is1_crs_v <= iu_au_is1_cr_user_v; +is1_crt_v <= i_afd_is1_cr_writer or (uc_end_is1 and uc_rc_l2); + + +is1_instr_v <= i_afd_is1_instr_v; + +bubble3_is1 <= i_afd_is1_est_bubble3; + + +config_iucr(1) <= i_afd_config_iucr(1); +config_iucr(2) <= i_afd_config_iucr(2); +config_iucr(3) <= i_afd_config_iucr(3); +config_iucr(4) <= i_afd_config_iucr(4); +config_iucr(5) <= i_afd_config_iucr(5); +config_iucr(6) <= i_afd_config_iucr(6); +config_iucr(7) <= i_afd_config_iucr(7); + +spare_unused(56) <= config_iucr(4); +iucr2_ss_ignore_flush <= config_iucr(6); +spare_unused(57) <= config_iucr(7); + disable_cgat <= config_iucr(5); +spare_unused(58) <= disable_cgat; + + + + + + + + + +axu_raw_cmp: entity work.iuq_axu_fu_dep_cmp(iuq_axu_fu_dep_cmp) +port map ( + vdd => vdd, + gnd => gnd, + lm_v => lm_v, + is1_instr_v => is1_instr_v, + lmc_ex4_v => lmc_ex4_v, + dis_byp_is1 => dis_byp_is1, + is1_store_v => is1_store_v, + ex3_ld_v => ex3_ld_v , + ex4_ld_v => ex4_ld_v , + uc_end_is1 => uc_end_is1 , + + is2_frt_v => is2_frt_v, + rf0_frt_v => rf0_frt_v, + rf1_frt_v => rf1_frt_v, + ex1_frt_v => ex1_frt_v, + ex2_frt_v => ex2_frt_v, + ex3_frt_v => ex3_frt_v, + ex4_frt_v => ex4_frt_v, + lm0_ta => lm0_ta, + lm1_ta => lm1_ta, + lm2_ta => lm2_ta, + lm3_ta => lm3_ta, + lm4_ta => lm4_ta, + lm5_ta => lm5_ta, + lm6_ta => lm6_ta, + lm7_ta => lm7_ta, + lmc_ex4 => lmc_ex4, + ex4_ta => ex4_ta , + ex3_ta => ex3_ta , + ex2_ta => ex2_ta , + ex1_ta => ex1_ta , + rf1_ta => rf1_ta , + rf0_ta => rf0_ta , + is2_ta => is2_ta , + + is1_fra_v => is1_fra_v, + is1_frb_v => is1_frb_v, + is1_frc_v => is1_frc_v, + is1_frt_v => is1_frt_v, + + is1_fra => is1_fra , + is1_frb => is1_frb , + is1_frc => is1_frc , + is1_ta => is1_ta , + + raw_fra_hit_b => raw_fra_hit_b , + raw_frb_hit_b => raw_frb_hit_b , + raw_frc_hit_b => raw_frc_hit_b , + raw_frb_uc_hit_b => raw_frb_uc_hit_b, + is1_lmq_waw_hit_b => is1_lmq_waw_hit_b + +); + + raw_fra_hit <= not raw_fra_hit_b; + raw_frb_hit <= not raw_frb_hit_b; + raw_frc_hit <= not raw_frc_hit_b; + + + +raw_cr_hit <= is1_crs_v and ((is2_crt_v and is2_instr_v) or + (rf0_crt_v and rf0_instr_v) or + (rf1_crt_v and rf1_instr_v) or + (ex1_crt_v and ex1_instr_v) or + (ex2_crt_v and ex2_instr_v) or + (ex3_crt_v and ex3_instr_v) or + (ex4_crt_v and ex4_instr_v) ); + + + + + +is1_raw_hit_earlystuff_b <= not ((is1_instr_v and (is1_prebubble_skip or is1_singlestep)) or raw_cr_hit); + +axudep_rawhit_nand4: is1_raw_hit <= not(raw_fra_hit_b and raw_frb_hit_b and raw_frc_hit_b and is1_raw_hit_earlystuff_b); + +is1_prebubble_skip <= i_afd_is1_prebubble1 and is2_instr_v; + + + + +is1_waw_cr_hit <= i_afd_is1_cr_setter and (bubble3_is2 or bubble3_rf0 or bubble3_rf1); + + +is1_waw_load_hit <= (is1_frt_v and is2_frt_v and is2_ld_v and (is2_ta = is1_ta)) or + (is1_frt_v and rf0_frt_v and rf0_ld_v and (rf0_ta = is1_ta)) ; + + + + + + + +is1_lmq_waw_hit <= not is1_lmq_waw_hit_b; + +axudep_hold_v_nand2: is1_hold_v_b <= not (iu_au_is1_hold and is1_instr_v); + +axudep_WAW_CRorLDhit_nor2: is1_WAW_CRorLDhit_b <= not (is1_waw_load_hit or is1_waw_cr_hit); + +axudep_allbut_RAW_nand3: is1_allbut_RAW <= not (is1_lmq_waw_hit_b and is1_WAW_CRorLDhit_b and is1_hold_v_b); + +is1_raw_hit_b <= not is1_raw_hit; +spare_unused(10) <= is1_raw_hit_b; + +raw_frb_uc_hit <= not raw_frb_uc_hit_b; + +axudep_dephit_nor3: is1_dep_hit_b <= not (is1_allbut_RAW or is1_raw_hit or raw_frb_uc_hit); + +axudep_dephit_buf1: is1_dep_hit_buf1 <= not is1_dep_hit_b; +axudep_dephit_buf2: is1_dep_hit_buf2_b <= not is1_dep_hit_buf1; +au_iu_is1_dep_hit_b <= is1_dep_hit_buf2_b; + + +is1_dep_hit <= not is1_dep_hit_b; + +au_iu_is1_dep_hit <= is1_dep_hit; + + + + +is2_instr_v_din <= is2_instr_v and (not iu_au_is2_flush or ignore_flush_is2); + + +rf0_instr_v_din <= rf0_instr_v and not iu_au_rf0_flush; +rf1_instr_v_din <= rf1_instr_v and not iu_au_rf1_flush; +ex1_instr_v_din <= ex1_instr_v and not iu_au_ex1_flush; +ex2_instr_v_din <= ex2_instr_v and not iu_au_ex2_flush; +ex3_instr_v_din <= ex3_instr_v and not iu_au_ex3_flush; +ex4_instr_v_din <= ex4_instr_v and not iu_au_ex4_flush; +ex5_instr_v_din <= ex5_instr_v and not iu_au_ex5_flush; + +is2_fmul_uc_din <= is2_fmul_uc and is2_instr_v_din and i_afi_is2_take; +rf0_fmul_uc_din <= rf0_fmul_uc and rf0_instr_v_din; +rf1_fmul_uc_din <= rf1_fmul_uc and rf1_instr_v_din; +ex1_fmul_uc_din <= ex1_fmul_uc and ex1_instr_v_din; +ex2_fmul_uc_din <= ex2_fmul_uc and ex2_instr_v_din; +ex3_fmul_uc_din <= ex3_fmul_uc and ex3_instr_v_din; +ex4_fmul_uc_din <= ex4_fmul_uc and ex4_instr_v_din; +ex5_fmul_uc_din <= ex5_fmul_uc and ex5_instr_v_din; + + +bubble3_is2_din <= bubble3_is2 and is2_instr_v_din; +bubble3_rf0_din <= bubble3_rf0 and rf0_instr_v_din; +bubble3_rf1_din <= bubble3_rf1 and rf1_instr_v_din; + + + +ignore_flush_is2_din <= ignore_flush_is2 and i_afi_is2_take and not iu_au_is2_flush; +ignore_flush_rf0_din <= ignore_flush_rf0 and not iu_au_rf0_flush; +ignore_flush_rf1_din <= ignore_flush_rf1 and not iu_au_rf1_flush; +ignore_flush_ex1_din <= ignore_flush_ex1 and not iu_au_ex1_flush; +ignore_flush_ex2_din <= ignore_flush_ex2 and not iu_au_ex2_flush; +ignore_flush_ex3_din <= ignore_flush_ex3 and not iu_au_ex3_flush; +ignore_flush_ex4_din <= ignore_flush_ex4 and not iu_au_ex4_flush; +ignore_flush_ex5_din <= ignore_flush_ex5 and not iu_au_ex5_flush; + + + + + + + +is2_frt_v_din <= is2_frt_v and (not iu_au_is2_flush or ignore_flush_is2) and stall_is2_b; +rf0_frt_v_din <= rf0_frt_v and not iu_au_rf0_flush; +rf1_frt_v_din <= rf1_frt_v and not iu_au_rf1_flush; +ex1_frt_v_din <= ex1_frt_v and not iu_au_ex1_flush; +ex2_frt_v_din <= ex2_frt_v and not iu_au_ex2_flush; +ex3_frt_v_din <= ex3_frt_v and not iu_au_ex3_flush; + + + +is1_crt_v_din <= is1_crt_v; +is2_crt_v_din <= is2_crt_v; +rf0_crt_v_din <= rf0_crt_v; +rf1_crt_v_din <= rf1_crt_v; +ex1_crt_v_din <= ex1_crt_v and bubble3_ex1; +ex2_crt_v_din <= ex2_crt_v; +ex3_crt_v_din <= ex3_crt_v; + + + + + + +four_loadmiss_entries : + if (lmq_entries = 4) generate + +lmiss_qentry(0 to 3) <= xu_au_loadmiss_qentry(0 to 3); +lmiss_complete(0 to 3) <= xu_au_loadmiss_complete_qentry(0 to 3); +lmiss_qentry(4 to 7) <= "0000"; +lmiss_complete(4 to 7) <= "0000"; + + + end generate four_loadmiss_entries; + +eight_loadmiss_entries : + if (lmq_entries = 8) generate + +lmiss_qentry <= xu_au_loadmiss_qentry; +lmiss_complete <= xu_au_loadmiss_complete_qentry; + + end generate eight_loadmiss_entries; + +lmiss_comp_type <= xu_au_loadmiss_complete_type; +lmiss_comp(0 to 7) <= lmiss_complete(0 to 7); +lmiss_comp_v <= xu_au_loadmiss_complete_vld and (lmiss_comp_type = "01"); + + + +lm_tar(0 to 5) <= xu_au_loadmiss_target(3) & xu_au_loadmiss_target(4 to 8); + +lm_v(0 to 7) <= lm0_valid & lm1_valid & lm2_valid & lm3_valid & lm4_valid & lm5_valid & lm6_valid & lm7_valid ; + +set_lm0 <= xu_au_loadmiss_vld and lmiss_qentry(0) and (xu_au_loadmiss_target_type = "01") and not iu_au_ex4_flush; +set_lm1 <= xu_au_loadmiss_vld and lmiss_qentry(1) and (xu_au_loadmiss_target_type = "01") and not iu_au_ex4_flush; +set_lm2 <= xu_au_loadmiss_vld and lmiss_qentry(2) and (xu_au_loadmiss_target_type = "01") and not iu_au_ex4_flush; +set_lm3 <= xu_au_loadmiss_vld and lmiss_qentry(3) and (xu_au_loadmiss_target_type = "01") and not iu_au_ex4_flush; +set_lm4 <= xu_au_loadmiss_vld and lmiss_qentry(4) and (xu_au_loadmiss_target_type = "01") and not iu_au_ex4_flush; +set_lm5 <= xu_au_loadmiss_vld and lmiss_qentry(5) and (xu_au_loadmiss_target_type = "01") and not iu_au_ex4_flush; +set_lm6 <= xu_au_loadmiss_vld and lmiss_qentry(6) and (xu_au_loadmiss_target_type = "01") and not iu_au_ex4_flush; +set_lm7 <= xu_au_loadmiss_vld and lmiss_qentry(7) and (xu_au_loadmiss_target_type = "01") and not iu_au_ex4_flush; + +clear_lm0 <= lmiss_comp_ex3(0) or (set_lm0_1d and iu_au_ex5_flush); +clear_lm1 <= lmiss_comp_ex3(1) or (set_lm1_1d and iu_au_ex5_flush); +clear_lm2 <= lmiss_comp_ex3(2) or (set_lm2_1d and iu_au_ex5_flush); +clear_lm3 <= lmiss_comp_ex3(3) or (set_lm3_1d and iu_au_ex5_flush); +clear_lm4 <= lmiss_comp_ex3(4) or (set_lm4_1d and iu_au_ex5_flush); +clear_lm5 <= lmiss_comp_ex3(5) or (set_lm5_1d and iu_au_ex5_flush); +clear_lm6 <= lmiss_comp_ex3(6) or (set_lm6_1d and iu_au_ex5_flush); +clear_lm7 <= lmiss_comp_ex3(7) or (set_lm7_1d and iu_au_ex5_flush); + +lmiss_comp_ex0(0) <= (lmiss_comp_v and lmiss_comp(0)); +lmiss_comp_ex0(1) <= (lmiss_comp_v and lmiss_comp(1)); +lmiss_comp_ex0(2) <= (lmiss_comp_v and lmiss_comp(2)); +lmiss_comp_ex0(3) <= (lmiss_comp_v and lmiss_comp(3)); +lmiss_comp_ex0(4) <= (lmiss_comp_v and lmiss_comp(4)); +lmiss_comp_ex0(5) <= (lmiss_comp_v and lmiss_comp(5)); +lmiss_comp_ex0(6) <= (lmiss_comp_v and lmiss_comp(6)); +lmiss_comp_ex0(7) <= (lmiss_comp_v and lmiss_comp(7)); + + + +lm0_valid_din <= '1' when set_lm0 ='1' else + '0' when clear_lm0 ='1' else + lm0_valid; +lm0_ta_din(0 to 5) <= lm_tar(0 to 5) when set_lm0 ='1' else + lm0_ta(0 to 5); + + +lm1_valid_din <= '1' when set_lm1 ='1' else + '0' when clear_lm1 ='1' else + lm1_valid; +lm1_ta_din(0 to 5) <= lm_tar(0 to 5) when set_lm1 ='1' else + lm1_ta(0 to 5); + + +lm2_valid_din <= '1' when set_lm2 ='1' else + '0' when clear_lm2 ='1' else + lm2_valid; +lm2_ta_din(0 to 5) <= lm_tar(0 to 5) when set_lm2 ='1' else + lm2_ta(0 to 5); + + +lm3_valid_din <= '1' when set_lm3 ='1' else + '0' when clear_lm3 ='1' else + lm3_valid; +lm3_ta_din(0 to 5) <= lm_tar(0 to 5) when set_lm3 ='1' else + lm3_ta(0 to 5); + + +lm4_valid_din <= '1' when set_lm4 ='1' else + '0' when clear_lm4 ='1' else + lm4_valid; +lm4_ta_din(0 to 5) <= lm_tar(0 to 5) when set_lm4 ='1' else + lm4_ta(0 to 5); + + +lm5_valid_din <= '1' when set_lm5 ='1' else + '0' when clear_lm5 ='1' else + lm5_valid; +lm5_ta_din(0 to 5) <= lm_tar(0 to 5) when set_lm5 ='1' else + lm5_ta(0 to 5); + + +lm6_valid_din <= '1' when set_lm6 ='1' else + '0' when clear_lm6 ='1' else + lm6_valid; +lm6_ta_din(0 to 5) <= lm_tar(0 to 5) when set_lm6 ='1' else + lm6_ta(0 to 5); + + +lm7_valid_din <= '1' when set_lm7 ='1' else + '0' when clear_lm7 ='1' else + lm7_valid; +lm7_ta_din(0 to 5) <= lm_tar(0 to 5) when set_lm7 ='1' else + lm7_ta(0 to 5); + + +lmc_ex3(0 to 5) <= (lm0_ta(0 to 5) and (0 to 5 => lmiss_comp_ex3(0))) or + (lm1_ta(0 to 5) and (0 to 5 => lmiss_comp_ex3(1))) or + (lm2_ta(0 to 5) and (0 to 5 => lmiss_comp_ex3(2))) or + (lm3_ta(0 to 5) and (0 to 5 => lmiss_comp_ex3(3))) or + (lm4_ta(0 to 5) and (0 to 5 => lmiss_comp_ex3(4))) or + (lm5_ta(0 to 5) and (0 to 5 => lmiss_comp_ex3(5))) or + (lm6_ta(0 to 5) and (0 to 5 => lmiss_comp_ex3(6))) or + (lm7_ta(0 to 5) and (0 to 5 => lmiss_comp_ex3(7))); + +lmc_ex3_v <= or_reduce(lmiss_comp_ex3(0 to 7)); + + + lmiss_comp_ex1_latch : tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 8) + port map ( + nclk => nclk, vd => vdd, gd => gnd, + forcee => forcee, mpw1_b => mpw1_b, mpw2_b => mpw2_b, + delay_lclkr => delay_lclkr, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + scin => lmiss_comp_ex1_latch_scin(0 to 7), + scout => lmiss_comp_ex1_latch_scout(0 to 7), + din => lmiss_comp_ex0, + dout => lmiss_comp_ex1 + ); + + lmiss_comp_ex2_latch : tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 8) + port map ( + nclk => nclk, vd => vdd, gd => gnd, + forcee => forcee, mpw1_b => mpw1_b, mpw2_b => mpw2_b, + delay_lclkr => delay_lclkr, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + scin => lmiss_comp_ex2_latch_scin(0 to 7), + scout => lmiss_comp_ex2_latch_scout(0 to 7), + din => lmiss_comp_ex1, + dout => lmiss_comp_ex2 + ); + + lmiss_comp_ex3_latch : tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 8) + port map ( + nclk => nclk, vd => vdd, gd => gnd, + forcee => forcee, mpw1_b => mpw1_b, mpw2_b => mpw2_b, + delay_lclkr => delay_lclkr, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + scin => lmiss_comp_ex3_latch_scin(0 to 7), + scout => lmiss_comp_ex3_latch_scout(0 to 7), + din => lmiss_comp_ex2, + dout => lmiss_comp_ex3 + ); + + lmc_ex4_latch : tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 7) + port map ( + nclk => nclk, vd => vdd, gd => gnd, + forcee => forcee, mpw1_b => mpw1_b, mpw2_b => mpw2_b, + delay_lclkr => delay_lclkr, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + scin => lmc_ex4_latch_scin(0 to 6), + scout => lmc_ex4_latch_scout(0 to 6), + din(0 to 5) => lmc_ex3(0 to 5), + din(6) => lmc_ex3_v, + dout(0 to 5) => lmc_ex4(0 to 5), + dout(6) => lmc_ex4_v + ); + + lmc_ex5_latch : tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 1) + port map ( + nclk => nclk, vd => vdd, gd => gnd, + forcee => forcee, mpw1_b => mpw1_b, mpw2_b => mpw2_b, + delay_lclkr => delay_lclkr, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + scin(0) => lmc_ex5_latch_scin, + scout(0) => lmc_ex5_latch_scout, + din(0) => lmc_ex4_v, + dout(0) => lmc_ex5_v + ); + + lmc_ex6_latch : tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 1) + port map ( + nclk => nclk, vd => vdd, gd => gnd, + forcee => forcee, mpw1_b => mpw1_b, mpw2_b => mpw2_b, + delay_lclkr => delay_lclkr, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + scin(0) => lmc_ex6_latch_scin, + scout(0) => lmc_ex6_latch_scout, + din(0) => lmc_ex5_v, + dout(0) => lmc_ex6_v + ); + + + + + +is1_fmul_uc <= i_afd_fmul_uc_is1 ; + +is1_fmul_uc_din <= is1_fmul_uc and is1_instr_v_din; + +ppc_div_sqrt_is1 <= i_afd_ignore_flush_is1; + +is1_to_ucode <= i_afd_is1_to_ucode; +is1_is_ucode <= i_afd_is1_is_ucode; + + + + + + + +is1_instr_v_din <= is1_instr_v + and + (not is1_dep_hit) + and + (not iu_au_is1_flush) + and + (not i_afd_is1_to_ucode or ppc_div_sqrt_is1); + + +i_axu_is1_early_v <= is1_instr_v + and + (not i_afd_is1_to_ucode or ppc_div_sqrt_is1) + and not i_afd_is1_instr_ldst_v; + +is1_ldst_v <= i_afd_is1_instr_ldst_v and not is1_dep_hit and not i_afd_is1_to_ucode and not iu_au_is1_flush; + +is1_ld_v <= i_afd_is1_instr_ld_v; +spare_unused(14) <= is1_ld_v; + +is1_ld_v_din <= i_afd_is1_instr_ld_v and is1_instr_v and not is1_dep_hit and not iu_au_is1_flush and not i_afd_is1_to_ucode; +is1_store_v <= i_afd_is1_instr_ldst_v and not i_afd_is1_instr_ld_v; + + +ignore_flush_is1 <= (i_afd_is1_divsqrt and not i_afd_is1_stall_rep) and not iu_au_is1_flush; + + +spare_unused(00) <= i_afd_is1_frt(0); + +is1_stage_din_premux <= + is1_ta(0 to 5) & + is1_ld_v_din & + i_afd_in_ucode_mode_or1d & + is1_instr_v_din & + is1_frt_v & + is1_is_ucode & + fu_iu_uc_special & + is1_fmul_uc_din & + is1_cmiss_flush & + is1_raw_hit & + is1_fra(0 to 5) & + tidn & + is1_frb(0 to 5) & + is1_frc(0 to 5) & + ignore_flush_is1 & + is1_fra_v & + is1_frb_v & + is1_frc_v & + is1_ldst_v & + is1_crt_v_din & + bubble3_is1 & + iu_au_is1_instr_match & + tidn ; + + + +stall_is2 <= iu_au_is2_stall and not (i_afi_is2_take and ignore_flush_is2); + +stall_is2_b <= not stall_is2; + +is1_stage_din <= (is1_stage_din_premux and (0 to (is1_stage_din'length-1) => stall_is2_b)) + or + (is2_stage_dout_premux and (0 to (is1_stage_din'length-1) => stall_is2)); + + + is2_stage_latch : tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => is2_stage_dout'length) + port map ( + nclk => nclk, vd => vdd, gd => gnd, + forcee => forcee, mpw1_b => mpw1_b, mpw2_b => mpw2_b, + delay_lclkr => delay_lclkr, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + scin => is2_stage_latch_scin(0 to ((is2_stage_dout'length)-1)), + scout => is2_stage_latch_scout(0 to ((is2_stage_dout'length)-1)), + din => is1_stage_din, + dout => is2_stage_dout + ); + + is2_stage_dout_premux <= is2_stage_dout(0 to 5) & + (is2_stage_dout(6) and (not iu_au_is2_flush or ignore_flush_is2)) & + is2_stage_dout(7) & + (is2_stage_dout(8) and (not iu_au_is2_flush or ignore_flush_is2)) & + is2_stage_dout(9 to 41) & + (is2_stage_dout(42) or is2_cmiss_flush) ; + +is2_ta(0 to 5) <= is2_stage_dout(0 to 5); +is2_ld_v <= is2_stage_dout(6); + +is2_ld_v_din <= is2_ld_v and is2_instr_v and not iu_au_is2_flush and stall_is2_b; +rf0_ld_v_din <= rf0_ld_v and rf0_instr_v_din; +rf1_ld_v_din <= rf1_ld_v and rf1_instr_v_din; +ex1_ld_v_din <= ex1_ld_v and ex1_instr_v_din; +ex2_ld_v_din <= ex2_ld_v and ex2_instr_v_din; +ex3_ld_v_din <= ex3_ld_v and ex3_instr_v_din; + +i_afd_in_ucode_mode_or1d_b <= not is2_stage_dout(7); + +is2_instr_v <= is2_stage_dout(8); + +is2_frt_v <= is2_stage_dout(9) and is2_instr_v; + + +is2_cmiss_flush_q <= is2_stage_dout(13); + + +i_afd_is2_is_ucode <= is2_stage_dout(10); + +is2_crt_v <= is2_stage_dout(39); + +spare_unused(01) <= is2_stage_dout(11); + + + + +ifdp_is2_est_bubble3 <= is2_stage_dout(40); +bubble3_is2 <= is2_stage_dout(40); + +spare_unused(02) <= is2_stage_dout(14); + +i_axu_is2_fra <= tidn & is2_stage_dout(15 to 20); +i_axu_is2_frb <= tidn & is2_stage_dout(22 to 27); +i_axu_is2_frc <= tidn & is2_stage_dout(28 to 33); +i_axu_is2_frt <= is2_stage_dout(7) & is2_stage_dout(0 to 5); + +is2_fra <= is2_stage_dout(15 to 20); +is2_frb <= is2_stage_dout(22 to 27); +is2_frc <= is2_stage_dout(28 to 33); + +ignore_flush_is2 <= is2_stage_dout(34) and not xu_iu_is2_flush; + +i_afd_ignore_flush_is2 <= is2_stage_dout(34); + +is2_fra_v <= is2_stage_dout(35); +is2_frb_v <= is2_stage_dout(36); +is2_frc_v <= is2_stage_dout(37); + + +i_axu_is2_fra_v <= is2_fra_v; +i_axu_is2_frb_v <= is2_frb_v; +i_axu_is2_frc_v <= is2_frc_v; + +is2_instr_ldst_v <= is2_stage_dout(38); +spare_unused(03) <= is2_stage_dout(21); + +i_axu_is2_instr_match <= is2_stage_dout(41); + +is2_fmul_uc <= is2_stage_dout(12); + + + +au_iu_is2_issue_stall <= (is2_instr_v and not is2_instr_ldst_v) and not i_afi_is2_take; + +i_axu_is2_instr_v <= is2_instr_v and not is2_instr_ldst_v; + + + + + + + + + + disable_bypass_chicken_switch <= config_iucr(1); + + dis_byp_is1 <= disable_bypass_chicken_switch; + +is1_cancel_bypass <= stall_is2 or dis_byp_is1 or is1_store_v; + + + is1_ex6_a_bypass <= (is1_fra_v and is1_instr_v_din and ex3_frt_v_forbyp and ex3_instr_v_din and not ex3_ld_v and (ex3_ta = is1_fra)) and not is1_cancel_bypass; + + is1_ex6_b_bypass <= (is1_frb_v and is1_instr_v_din and ex3_frt_v_forbyp and ex3_instr_v_din and not ex3_ld_v and (ex3_ta = is1_frb)) and not is1_cancel_bypass; + + is1_ex6_c_bypass <= (is1_frc_v and is1_instr_v_din and ex3_frt_v_forbyp and ex3_instr_v_din and not ex3_ld_v and (ex3_ta = is1_frc)) and not is1_cancel_bypass; + + + +is1_ld6_a_bypass <= ((is1_fra_v and is1_instr_v_din and ex4_ld_v and (ex4_ta = is1_fra)) and not is1_cancel_bypass); + +is1_ld6_b_bypass <= ((is1_frb_v and is1_instr_v_din and ex4_ld_v and (ex4_ta = is1_frb)) and not is1_cancel_bypass); + +is1_ld6_c_bypass <= ((is1_frc_v and is1_instr_v_din and ex4_ld_v and (ex4_ta = is1_frc)) and not is1_cancel_bypass); + + +is1_bypsel(0) <= is1_ld6_a_bypass; +is1_bypsel(1) <= is1_ld6_c_bypass; +is1_bypsel(2) <= is1_ld6_b_bypass; + +is1_bypsel(3) <= is1_ex6_a_bypass; +is1_bypsel(4) <= is1_ex6_c_bypass; +is1_bypsel(5) <= is1_ex6_b_bypass; + + + is2_bypass_latch: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 6) + port map ( + nclk => nclk, vd => vdd, gd => gnd, + forcee => forcee, mpw1_b => mpw1_b, mpw2_b => mpw2_b, + delay_lclkr => delay_lclkr, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + scin => is2_bypass_latch_scin, + scout => is2_bypass_latch_scout, + din(0 to 5) => is1_bypsel, + dout(0 to 5) => is2_bypsel + ); + + ifdp_is2_bypsel <= is2_bypsel; + + + + +is2_act_din <= is2_instr_v or disable_cgat; +rf0_act_din <= rf0_instr_v or disable_cgat; +rf1_act_din <= rf1_instr_v or disable_cgat; +ex1_act_din <= ex1_instr_v or disable_cgat; +ex2_act_din <= ex2_instr_v or disable_cgat; +ex3_act_din <= ex3_instr_v or disable_cgat; + + + act_latch: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 8) + port map ( + nclk => nclk, vd => vdd, gd => gnd, + forcee => forcee, mpw1_b => mpw1_b, mpw2_b => mpw2_b, + delay_lclkr => delay_lclkr, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + scin => act_latch_scin, + scout => act_latch_scout, + din(0) => is2_act_din, + din(1) => rf0_act_din, + din(2) => rf1_act_din, + din(3) => ex1_act_din, + din(4) => ex2_act_din, + din(5) => ex3_act_din, + din(6) => spare_l2(3), + din(7) => spare_l2(4), + + dout(0) => is2_act_l2, + dout(1) => rf0_act_l2, + dout(2) => rf1_act_l2, + dout(3) => ex1_act_l2, + dout(4) => ex2_act_l2, + dout(5) => ex3_act_l2, + dout(6) => spare_l2(3), + dout(7) => spare_l2(4) + + ); + + + + +is2_act <= is2_instr_v or is2_act_l2; + + rf0_sp_latch : tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 15) + port map ( + nclk => nclk, vd => vdd, gd => gnd, + forcee => forcee, mpw1_b => mpw1_b, mpw2_b => mpw2_b, + delay_lclkr => delay_lclkr, + act => is2_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + scin => rf0_sp_latch_scin(0 to 14), + scout => rf0_sp_latch_scout(0 to 14), + din(0 to 5) => is2_ta(0 to 5), + din(6) => is2_ld_v_din, + din(7) => spare_l2(0), + din(8) => is2_instr_v_din, + din(9) => is2_frt_v_din, + din(10) => is2_fmul_uc_din, + din(11) => is2_crt_v_din, + din(12) => bubble3_is2_din, + din(13) => is2_cmiss_flush_din, + din(14) => ignore_flush_is2_din, + dout(0 to 5) => rf0_ta(0 to 5), + dout(6) => rf0_ld_v, + dout(7) => spare_l2(0), + dout(8) => rf0_instr_v, + dout(9) => rf0_frt_v, + dout(10) => rf0_fmul_uc, + dout(11) => rf0_crt_v, + dout(12) => bubble3_rf0, + dout(13) => rf0_cmiss_flush, + dout(14) => ignore_flush_rf0 + ); + +spare_unused(04) <= tidn; + +rf0_act <= rf0_instr_v or rf0_act_l2; + + rf1_sp_latch : tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 15) + port map ( + nclk => nclk, vd => vdd, gd => gnd, + forcee => forcee, mpw1_b => mpw1_b, mpw2_b => mpw2_b, + delay_lclkr => delay_lclkr, + act => rf0_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + scin => rf1_sp_latch_scin(0 to 14), + scout => rf1_sp_latch_scout(0 to 14), + din(0 to 5) => rf0_ta(0 to 5), + din(6) => rf0_ld_v_din, + din(7) => spare_l2(1), + din(8) => rf0_instr_v_din, + din(9) => rf0_frt_v_din, + din(10) => rf0_fmul_uc_din, + din(11) => rf0_crt_v_din, + din(12) => bubble3_rf0_din, + din(13) => rf0_cmiss_flush_din, + din(14) => ignore_flush_rf0_din, + + dout(0 to 5) => rf1_ta(0 to 5), + dout(6) => rf1_ld_v, + dout(7) => spare_l2(1), + dout(8) => rf1_instr_v, + dout(9) => rf1_frt_v, + dout(10) => rf1_fmul_uc, + dout(11) => rf1_crt_v, + dout(12) => bubble3_rf1, + dout(13) => rf1_cmiss_flush, + dout(14) => ignore_flush_rf1 + ); + + spare_unused(05) <= tidn; + + rf1_act <= rf1_instr_v or rf1_act_l2; + + ex1_sp_latch: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 15) + port map ( + nclk => nclk, vd => vdd, gd => gnd, + forcee => forcee, mpw1_b => mpw1_b, mpw2_b => mpw2_b, + delay_lclkr => delay_lclkr, + act => rf1_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + scin => ex1_sp_latch_scin, + scout => ex1_sp_latch_scout, + din(0 to 5) => rf1_ta(0 to 5), + din(6) => rf1_ld_v_din, + din(7) => spare_l2(2), + din(8) => rf1_instr_v_din, + din(9) => rf1_frt_v_din, + din(10) => rf1_fmul_uc_din, + din(11) => rf1_crt_v_din, + din(12) => bubble3_rf1_din, + din(13) => rf1_cmiss_flush_din, + din(14) => ignore_flush_rf1_din, + dout(0 to 5) => ex1_ta(0 to 5), + dout(6) => ex1_ld_v, + dout(7) => spare_l2(2), + dout(8) => ex1_instr_v, + dout(9) => ex1_frt_v, + dout(10) => ex1_fmul_uc, + dout(11) => ex1_crt_v, + dout(12) => bubble3_ex1, + dout(13) => ex1_cmiss_flush, + dout(14) => ignore_flush_ex1 + ); + + spare_unused(06) <= tidn; + + + ex1_act <= ex1_instr_v or ex1_act_l2; + + ex2_sp_latch: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 14) + port map ( + nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act, + forcee => forcee, mpw1_b => mpw1_b, mpw2_b => mpw2_b, + delay_lclkr => delay_lclkr, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + scin => ex2_sp_latch_scin, + scout => ex2_sp_latch_scout, + din(0 to 5) => ex1_ta(0 to 5), + din(06) => ex1_ld_v_din, + din(07) => xu_au_loadmiss_target(0), + din(08) => ex1_instr_v_din, + din(09) => ex1_frt_v_din, + din(10) => ex1_fmul_uc_din, + din(11) => ex1_crt_v_din, + din(12) => ex1_cmiss_flush_din, + din(13) => ignore_flush_ex1_din, + dout(0 to 5) => ex2_ta(0 to 5), + dout(06) => ex2_ld_v, + dout(07) => spare_unused(07), + dout(08) => ex2_instr_v, + dout(09) => ex2_frt_v, + dout(10) => ex2_fmul_uc, + dout(11) => ex2_crt_v, + dout(12) => ex2_cmiss_flush, + dout(13) => ignore_flush_ex2 + ); + + ex2_act <= ex2_instr_v or ex2_act_l2; + + ex3_sp_latch: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 14) + port map ( + nclk => nclk, vd => vdd, gd => gnd, + act => ex2_act, + forcee => forcee, mpw1_b => mpw1_b, mpw2_b => mpw2_b, + delay_lclkr => delay_lclkr, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + scin => ex3_sp_latch_scin, + scout => ex3_sp_latch_scout, + din(0 to 5) => ex2_ta(0 to 5), + din(6) => ex2_ld_v_din, + din(7) => xu_au_loadmiss_target(1), + din(8) => ex2_instr_v_din, + din(9) => ex2_frt_v_din, + din(10) => ex2_fmul_uc_din, + din(11) => ex2_crt_v_din, + din(12) => ex2_frt_v, + din(13) => ignore_flush_ex2_din, + dout(0 to 5) => ex3_ta(0 to 5), + dout(6) => ex3_ld_v, + dout(7) => spare_unused(08), + dout(8) => ex3_instr_v, + dout(9) => ex3_frt_v, + dout(10) => ex3_fmul_uc, + dout(11) => ex3_crt_v, + dout(12) => ex3_frt_v_forbyp, + dout(13) => ignore_flush_ex3 + ); + + + ex3_act <= ex3_instr_v or ex3_act_l2; + + ex4_sp_latch: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 13) + port map ( + nclk => nclk, vd => vdd, gd => gnd, + forcee => forcee, mpw1_b => mpw1_b, mpw2_b => mpw2_b, + delay_lclkr => delay_lclkr, + act => ex3_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + scin => ex4_sp_latch_scin, + scout => ex4_sp_latch_scout, + din(0 to 5) => ex3_ta(0 to 5), + din(6) => ex3_ld_v_din, + din(7) => ex3_instr_v_din, + din(8) => ex3_frt_v_din, + din(9) => ex3_fmul_uc_din, + din(10) => ex3_crt_v_din, + din(11) => xu_au_loadmiss_target(2), + din(12) => ignore_flush_ex3_din, + dout(0 to 5) => ex4_ta(0 to 5), + dout(6) => ex4_ld_v, + dout(7) => ex4_instr_v, + dout(8) => ex4_frt_v, + dout(9) => ex4_fmul_uc, + dout(10) => ex4_crt_v, + dout(11) => spare_unused(09), + dout(12) => ignore_flush_ex4 + ); + + + + + ex5_sp_latch: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 11) + port map ( + nclk => nclk, vd => vdd, gd => gnd, + forcee => forcee, mpw1_b => mpw1_b, mpw2_b => mpw2_b, + delay_lclkr => delay_lclkr, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + scin => ex5_sp_latch_scin, + scout => ex5_sp_latch_scout, + din(0) => ex4_instr_v_din, + din(1) => ex4_fmul_uc_din, + din(2) => set_lm0, + din(3) => set_lm1, + din(4) => set_lm2, + din(5) => set_lm3, + din(6) => set_lm4, + din(7) => set_lm5, + din(8) => set_lm6, + din(9) => set_lm7, + din(10) => ignore_flush_ex4_din, + dout(0) => ex5_instr_v, + dout(1) => ex5_fmul_uc, + dout(2) => set_lm0_1d, + dout(3) => set_lm1_1d, + dout(4) => set_lm2_1d, + dout(5) => set_lm3_1d, + dout(6) => set_lm4_1d, + dout(7) => set_lm5_1d, + dout(8) => set_lm6_1d, + dout(9) => set_lm7_1d, + dout(10) => ignore_flush_ex5 + + ); + +ifdp_ex5_fmul_uc_complete <= ex5_fmul_uc; + + ex6_sp_latch: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 2) + port map ( + nclk => nclk, vd => vdd, gd => gnd, + forcee => forcee, mpw1_b => mpw1_b, mpw2_b => mpw2_b, + delay_lclkr => delay_lclkr, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + scin => ex6_sp_latch_scin, + scout => ex6_sp_latch_scout, + din(0) => ex5_instr_v_din, + din(1) => ignore_flush_ex5_din, + dout(0) => ex6_instr_v, + dout(1) => ignore_flush_ex6 + ); + + + + busy_latch: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 3) + port map ( + nclk => nclk, vd => vdd, gd => gnd, + forcee => forcee, mpw1_b => mpw1_b, mpw2_b => mpw2_b, + delay_lclkr => delay_lclkr, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + scin => busy_latch_scin, + scout => busy_latch_scout, + din(0) => fu_busy, + din(1) => fmul_uc_busy, + din(2) => ignore_flush_busy, + + dout(0) => fu_busy_l2, + dout(1) => fmul_uc_busy_l2, + dout(2) => ignore_flush_busy_l2 + + ); + + + + + +ignore_flush_busy <= is2_stage_dout(34) or + ignore_flush_rf0 or ignore_flush_rf1 or ignore_flush_ex1 or ignore_flush_ex2 or + ignore_flush_ex3 or ignore_flush_ex4 or ignore_flush_ex5 or ignore_flush_ex6; + +is2_ignore_flush_busy <= is2_stage_dout(34) or ignore_flush_busy_l2; + + +fu_busy <= is2_instr_v or rf0_instr_v or rf1_instr_v or + ex1_instr_v or ex2_instr_v or ex3_instr_v or ex4_instr_v or ex5_instr_v or ex6_instr_v or + lmc_ex4_v or lmc_ex5_v or lmc_ex6_v or + lm0_valid or lm1_valid or lm2_valid or lm3_valid or + lm4_valid or lm5_valid or lm6_valid or lm7_valid; + + is2_axubusy <= is2_instr_v or fu_busy_l2; +au_iu_is2_axubusy <= is2_axubusy ; + +fmul_uc_busy <= is2_fmul_uc_din or rf0_fmul_uc_din or rf1_fmul_uc_din or ex1_fmul_uc_din or + ex2_fmul_uc_din or ex3_fmul_uc_din or ex4_fmul_uc_din or ex5_fmul_uc_din; + + +is1_singlestep_ucode <= ( ((is1_to_ucode or is1_is_ucode) and is2_axubusy) + or ( is1_fmul_uc and is2_axubusy) + or ( fmul_uc_busy_l2 ) ) + and config_iucr(3); + +is1_singlestep_pn <= ((ppc_div_sqrt_is1 and is2_axubusy) or + (is1_instr_v and is2_ignore_flush_busy)) + and iucr2_ss_ignore_flush ; + + + is1_singlestep <= is1_singlestep_ucode or is1_singlestep_pn or (is2_axubusy and config_iucr(2)); + + + + + lmq0_latch: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 7) + port map ( + nclk => nclk, vd => vdd, gd => gnd, + forcee => forcee, mpw1_b => mpw1_b, mpw2_b => mpw2_b, + delay_lclkr => delay_lclkr, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + scin => lmq0_latch_scin, + scout => lmq0_latch_scout, + din(0) => lm0_valid_din, + din(1 to 6) => lm0_ta_din(0 to 5), + dout(0) => lm0_valid, + dout(1 to 6) => lm0_ta(0 to 5) + ); + lmq1_latch: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 7) + port map ( + nclk => nclk, vd => vdd, gd => gnd, + forcee => forcee, mpw1_b => mpw1_b, mpw2_b => mpw2_b, + delay_lclkr => delay_lclkr, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + scin => lmq1_latch_scin , + scout => lmq1_latch_scout, + din(0) => lm1_valid_din, + din(1 to 6) => lm1_ta_din(0 to 5), + dout(0) => lm1_valid, + dout(1 to 6) => lm1_ta(0 to 5) + ); + lmq2_latch: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 7) + port map ( + nclk => nclk, vd => vdd, gd => gnd, + forcee => forcee, mpw1_b => mpw1_b, mpw2_b => mpw2_b, + delay_lclkr => delay_lclkr, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + scin => lmq2_latch_scin, + scout => lmq2_latch_scout, + din(0) => lm2_valid_din, + din(1 to 6) => lm2_ta_din(0 to 5), + dout(0) => lm2_valid, + dout(1 to 6) => lm2_ta(0 to 5) + ); + lmq3_latch: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 7) + port map ( + nclk => nclk, vd => vdd, gd => gnd, + forcee => forcee, mpw1_b => mpw1_b, mpw2_b => mpw2_b, + delay_lclkr => delay_lclkr, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + scin => lmq3_latch_scin, + scout => lmq3_latch_scout, + din(0) => lm3_valid_din, + din(1 to 6) => lm3_ta_din(0 to 5), + dout(0) => lm3_valid, + dout(1 to 6) => lm3_ta(0 to 5) + ); + lmq4_latch: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 7) + port map ( + nclk => nclk, vd => vdd, gd => gnd, + forcee => forcee, mpw1_b => mpw1_b, mpw2_b => mpw2_b, + delay_lclkr => delay_lclkr, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + scin => lmq4_latch_scin, + scout => lmq4_latch_scout, + din(0) => lm4_valid_din, + din(1 to 6) => lm4_ta_din(0 to 5), + dout(0) => lm4_valid, + dout(1 to 6) => lm4_ta(0 to 5) + ); + lmq5_latch: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 7) + port map ( + nclk => nclk, vd => vdd, gd => gnd, + forcee => forcee, mpw1_b => mpw1_b, mpw2_b => mpw2_b, + delay_lclkr => delay_lclkr, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + scin => lmq5_latch_scin, + scout => lmq5_latch_scout, + din(0) => lm5_valid_din, + din(1 to 6) => lm5_ta_din(0 to 5), + dout(0) => lm5_valid, + dout(1 to 6) => lm5_ta(0 to 5) + ); + lmq6_latch: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 7) + port map ( + nclk => nclk, vd => vdd, gd => gnd, + forcee => forcee, mpw1_b => mpw1_b, mpw2_b => mpw2_b, + delay_lclkr => delay_lclkr, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + scin => lmq6_latch_scin, + scout => lmq6_latch_scout, + din(0) => lm6_valid_din, + din(1 to 6) => lm6_ta_din(0 to 5), + dout(0) => lm6_valid, + dout(1 to 6) => lm6_ta(0 to 5) + ); + lmq7_latch: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 7) + port map ( + nclk => nclk, vd => vdd, gd => gnd, + forcee => forcee, mpw1_b => mpw1_b, mpw2_b => mpw2_b, + delay_lclkr => delay_lclkr, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + scin => lmq7_latch_scin, + scout => lmq7_latch_scout, + din(0) => lm7_valid_din, + din(1 to 6) => lm7_ta_din(0 to 5), + dout(0) => lm7_valid, + dout(1 to 6) => lm7_ta(0 to 5) + ); + + + + + +is1_cmiss_flush <= ex4_ld_v and xu_au_loadmiss_vld and not is1_stall_rep and is1_instr_v and + ((is1_frt_v and (ex4_ta(0 to 5) = is1_ta(0 to 5))) + or + (is1_fra_v and (ex4_ta(0 to 5) = is1_fra(0 to 5))) + or + (is1_frb_v and (ex4_ta(0 to 5) = is1_frb(0 to 5))) + or + (is1_frc_v and (ex4_ta(0 to 5) = is1_frc(0 to 5)))); + + + + +is2_cmiss_flush <= ex4_ld_v and xu_au_loadmiss_vld and is2_instr_v and + ((is2_frt_v and (ex4_ta(0 to 5) = is2_ta(0 to 5))) + or + (is2_fra_v and (ex4_ta(0 to 5) = is2_fra(0 to 5))) + or + (is2_frb_v and (ex4_ta(0 to 5) = is2_frb(0 to 5))) + or + (is2_frc_v and (ex4_ta(0 to 5) = is2_frc(0 to 5)))); + +rf0_cmiss_waw_flush <= ex4_ld_v and xu_au_loadmiss_vld and rf0_instr_v and (rf0_frt_v and (ex4_ta(0 to 5) = rf0_ta(0 to 5))); +rf1_cmiss_waw_flush <= ex4_ld_v and xu_au_loadmiss_vld and rf1_instr_v and (rf1_frt_v and (ex4_ta(0 to 5) = rf1_ta(0 to 5))); +ex1_cmiss_waw_flush <= ex4_ld_v and xu_au_loadmiss_vld and ex1_instr_v and (ex1_frt_v and (ex4_ta(0 to 5) = ex1_ta(0 to 5))); + + +is2_cmiss_flush_din <= (is2_cmiss_flush or is2_cmiss_flush_q or is2_stage_dout(42)); + +rf0_cmiss_flush_din <= rf0_cmiss_flush or rf0_cmiss_waw_flush; +rf1_cmiss_flush_din <= rf1_cmiss_flush or rf1_cmiss_waw_flush; +ex1_cmiss_flush_din <= ex1_cmiss_flush or ex1_cmiss_waw_flush; + +iu_fu_ex2_n_flush <= ex2_cmiss_flush and ex2_instr_v; + + + + + + + debug_latch_for_timing: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 16) + port map ( + nclk => nclk, vd => vdd, gd => gnd, + forcee => forcee, mpw1_b => mpw1_b, mpw2_b => mpw2_b, + delay_lclkr => delay_lclkr, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + scin => debug_scin, + scout => debug_scout, + din(0) => is1_dep_hit, + din(1) => is1_raw_hit, + din(2) => raw_fra_hit, + din(3) => raw_frb_hit, + din(4) => raw_frc_hit, + din(5) => is1_prebubble_skip, + din(6) => raw_cr_hit, + din(7) => bubble3_is1, + din(8) => is1_lmq_waw_hit, + din(9) => is1_waw_load_hit, + din(10) => iu_au_is1_hold, + din(11) => iu_au_is2_stall, + din(12) => iu_au_is1_flush, + din(13) => iu_au_is2_flush, + din(14) => iu_au_rf0_flush, + din(15) => is1_instr_v_din, + dout(0) => is1_dep_hit_db, + dout(1) => is1_raw_hit_db, + dout(2) => raw_fra_hit_db, + dout(3) => raw_frb_hit_db, + dout(4) => raw_frc_hit_db, + dout(5) => is1_prebubble_skip_db, + dout(6) => raw_cr_hit_db, + dout(7) => bubble3_is1_db, + dout(8) => is1_lmq_waw_hit_db, + dout(9) => is1_waw_load_hit_db, + dout(10) => iu_au_is1_hold_db, + dout(11) => iu_au_is2_stall_db, + dout(12) => iu_au_is1_flush_db, + dout(13) => iu_au_is2_flush_db, + dout(14) => iu_au_rf0_flush_db, + dout(15) => is1_instr_v_din_db + ); + + +fu_dep_debug(0 to 23) <= is1_dep_hit_db & is1_raw_hit_db & raw_fra_hit_db & raw_frb_hit_db & + raw_frc_hit_db & is1_prebubble_skip_db & raw_cr_hit_db & bubble3_is1_db & + is1_lmq_waw_hit_db & is1_waw_load_hit_db & iu_au_is1_hold_db & iu_au_is2_stall_db & + iu_au_is1_flush_db & iu_au_is2_flush_db & iu_au_rf0_flush_db & is1_instr_v_din_db & + is2_instr_v & rf0_instr_v & rf1_instr_v & + is2_ta(1 to 5); + + + + + +ppc_rc_latch_scin <= i_dep_si; + +is2_stage_latch_scin(0) <= ppc_rc_latch_scout; + +is2_stage_latch_scin(1 to 42) <= is2_stage_latch_scout(0 to 41); + +is2_bypass_latch_scin(0) <= is2_stage_latch_scout(42); +is2_bypass_latch_scin(1 to 5) <= is2_bypass_latch_scout(0 to 4); + +rf0_sp_latch_scin(0) <= is2_bypass_latch_scout(5); +rf0_sp_latch_scin(1 to 14) <= rf0_sp_latch_scout(0 to 13); + +rf1_sp_latch_scin(0) <= rf0_sp_latch_scout(14); +rf1_sp_latch_scin(1 to 14) <= rf1_sp_latch_scout(0 to 13); + +ex1_sp_latch_scin(0) <= rf1_sp_latch_scout(14); +ex1_sp_latch_scin(1 to 14) <= ex1_sp_latch_scout(0 to 13); + +ex2_sp_latch_scin(0) <= ex1_sp_latch_scout(14); +ex2_sp_latch_scin(1 to 13) <= ex2_sp_latch_scout(0 to 12); + +ex3_sp_latch_scin(0) <= ex2_sp_latch_scout(13); +ex3_sp_latch_scin(1 to 13) <= ex3_sp_latch_scout(0 to 12); + +ex4_sp_latch_scin(0) <= ex3_sp_latch_scout(13); +ex4_sp_latch_scin(1 to 12) <= ex4_sp_latch_scout(0 to 11); + +ex5_sp_latch_scin(0) <= ex4_sp_latch_scout(12); +ex5_sp_latch_scin(1 to 10) <= ex5_sp_latch_scout(0 to 9); + +ex6_sp_latch_scin(0) <= ex5_sp_latch_scout(10); +ex6_sp_latch_scin(1) <= ex6_sp_latch_scout(0); + +busy_latch_scin(0) <= ex6_sp_latch_scout(1); +busy_latch_scin(1 to 2) <= busy_latch_scout(0 to 1); + +act_latch_scin(0) <= busy_latch_scout(2); +act_latch_scin(1 to 7) <= act_latch_scout(0 to 6); + + +lmq0_latch_scin(0) <= act_latch_scout(7); +lmq0_latch_scin(1 to 6) <= lmq0_latch_scout(0 to 5); + +lmq1_latch_scin(0) <= lmq0_latch_scout(6); +lmq1_latch_scin(1 to 6) <= lmq1_latch_scout(0 to 5); + +lmq2_latch_scin(0) <= lmq1_latch_scout(6); +lmq2_latch_scin(1 to 6) <= lmq2_latch_scout(0 to 5); + +lmq3_latch_scin(0) <= lmq2_latch_scout(6); +lmq3_latch_scin(1 to 6) <= lmq3_latch_scout(0 to 5); + +lmq4_latch_scin(0) <= lmq3_latch_scout(6); +lmq4_latch_scin(1 to 6) <= lmq4_latch_scout(0 to 5); + +lmq5_latch_scin(0) <= lmq4_latch_scout(6); +lmq5_latch_scin(1 to 6) <= lmq5_latch_scout(0 to 5); + +lmq6_latch_scin(0) <= lmq5_latch_scout(6); +lmq6_latch_scin(1 to 6) <= lmq6_latch_scout(0 to 5); + +lmq7_latch_scin(0) <= lmq6_latch_scout(6); +lmq7_latch_scin(1 to 6) <= lmq7_latch_scout(0 to 5); + +lmiss_comp_ex1_latch_scin(0) <= lmq7_latch_scout(6); +lmiss_comp_ex1_latch_scin(1 to 7) <= lmiss_comp_ex1_latch_scout(0 to 6); + +lmiss_comp_ex2_latch_scin(0) <= lmiss_comp_ex1_latch_scout(7); +lmiss_comp_ex2_latch_scin(1 to 7) <= lmiss_comp_ex2_latch_scout(0 to 6); + +lmiss_comp_ex3_latch_scin(0) <= lmiss_comp_ex2_latch_scout(7); +lmiss_comp_ex3_latch_scin(1 to 7) <= lmiss_comp_ex3_latch_scout(0 to 6); + +lmc_ex4_latch_scin(0) <= lmiss_comp_ex3_latch_scout(7); +lmc_ex4_latch_scin(1 to 6) <= lmc_ex4_latch_scout(0 to 5); + +lmc_ex5_latch_scin <= lmc_ex4_latch_scout(6); +lmc_ex6_latch_scin <= lmc_ex5_latch_scout; + +debug_scin(0) <= lmc_ex6_latch_scout; +debug_scin(1 to 15) <= debug_scout(0 to 14); + + +i_dep_so <= debug_scout(15); + + + +end iuq_axu_fu_dep; + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_axu_fu_dep_cmp.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_axu_fu_dep_cmp.vhdl new file mode 100644 index 0000000..ddebac7 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_axu_fu_dep_cmp.vhdl @@ -0,0 +1,1175 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; + use ieee.std_logic_1164.all ; +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; +library support; + use support.power_logic_pkg.all; + + + +entity iuq_axu_fu_dep_cmp is + +port( + lm_v : in std_ulogic_vector(0 to 7); + is1_instr_v : in std_ulogic; + vdd : inout power_logic; + gnd : inout power_logic; + lmc_ex4_v : in std_ulogic; + dis_byp_is1 : in std_ulogic; + is1_store_v : in std_ulogic; + ex3_ld_v : in std_ulogic; + ex4_ld_v : in std_ulogic; + uc_end_is1 : in std_ulogic; + + is2_frt_v : in std_ulogic; + rf0_frt_v : in std_ulogic; + rf1_frt_v : in std_ulogic; + ex1_frt_v : in std_ulogic; + ex2_frt_v : in std_ulogic; + ex3_frt_v : in std_ulogic; + ex4_frt_v : in std_ulogic; + + + lm0_ta : in std_ulogic_vector(0 to 5); + lm1_ta : in std_ulogic_vector(0 to 5); + lm2_ta : in std_ulogic_vector(0 to 5); + lm3_ta : in std_ulogic_vector(0 to 5); + lm4_ta : in std_ulogic_vector(0 to 5); + lm5_ta : in std_ulogic_vector(0 to 5); + lm6_ta : in std_ulogic_vector(0 to 5); + lm7_ta : in std_ulogic_vector(0 to 5); + lmc_ex4 : in std_ulogic_vector(0 to 5); + ex4_ta : in std_ulogic_vector(0 to 5); + ex3_ta : in std_ulogic_vector(0 to 5); + ex2_ta : in std_ulogic_vector(0 to 5); + ex1_ta : in std_ulogic_vector(0 to 5); + rf1_ta : in std_ulogic_vector(0 to 5); + rf0_ta : in std_ulogic_vector(0 to 5); + is2_ta : in std_ulogic_vector(0 to 5); + + is1_fra_v : in std_ulogic; + is1_frb_v : in std_ulogic; + is1_frc_v : in std_ulogic; + is1_frt_v : in std_ulogic; + + is1_fra : in std_ulogic_vector(0 to 5); + is1_frb : in std_ulogic_vector(0 to 5); + is1_frc : in std_ulogic_vector(0 to 5); + is1_ta : in std_ulogic_vector(0 to 5); + + raw_fra_hit_b : out std_ulogic; + raw_frb_hit_b : out std_ulogic; + raw_frc_hit_b : out std_ulogic; + + raw_frb_uc_hit_b : out std_ulogic; + is1_lmq_waw_hit_b : out std_ulogic + + ); + + +end iuq_axu_fu_dep_cmp; + +architecture iuq_axu_fu_dep_cmp of iuq_axu_fu_dep_cmp is + + signal lm0_ta_buf, lm0_ta_buf_b :std_ulogic_vector(0 to 5); + signal lm1_ta_buf, lm1_ta_buf_b :std_ulogic_vector(0 to 5); + signal lm2_ta_buf, lm2_ta_buf_b :std_ulogic_vector(0 to 5); + signal lm3_ta_buf, lm3_ta_buf_b :std_ulogic_vector(0 to 5); + signal lm4_ta_buf, lm4_ta_buf_b :std_ulogic_vector(0 to 5); + signal lm5_ta_buf, lm5_ta_buf_b :std_ulogic_vector(0 to 5); + signal lm6_ta_buf, lm6_ta_buf_b :std_ulogic_vector(0 to 5); + signal lm7_ta_buf, lm7_ta_buf_b :std_ulogic_vector(0 to 5); + signal lmc_ex4_buf, lmc_ex4_buf_b :std_ulogic_vector(0 to 5); + signal ex4_ta_buf, ex4_ta_buf_b :std_ulogic_vector(0 to 5); + signal ex3_ta_buf, ex3_ta_buf_b :std_ulogic_vector(0 to 5); + signal ex2_ta_buf, ex2_ta_buf_b :std_ulogic_vector(0 to 5); + signal ex1_ta_buf, ex1_ta_buf_b :std_ulogic_vector(0 to 5); + signal rf1_ta_buf, rf1_ta_buf_b :std_ulogic_vector(0 to 5); + signal rf0_ta_buf, rf0_ta_buf_b :std_ulogic_vector(0 to 5); + signal is2_ta_buf, is2_ta_buf_b :std_ulogic_vector(0 to 5); + + + signal is1_fra_buf1 :std_ulogic_vector(0 to 5); + signal is1_frb_buf1 :std_ulogic_vector(0 to 5); + signal is1_frc_buf1 :std_ulogic_vector(0 to 5); + signal is1_frt_buf1 :std_ulogic_vector(0 to 5); + signal is1_fra_buf2 :std_ulogic_vector(0 to 5); + signal is1_frb_buf2 :std_ulogic_vector(0 to 5); + signal is1_frc_buf2 :std_ulogic_vector(0 to 5); + signal is1_frt_buf2 :std_ulogic_vector(0 to 5); + signal is1_fra_buf3 :std_ulogic_vector(0 to 5); + signal is1_frb_buf3 :std_ulogic_vector(0 to 5); + signal is1_frc_buf3 :std_ulogic_vector(0 to 5); + signal is1_frt_buf3 :std_ulogic_vector(0 to 5); + signal is1_fra_buf4 :std_ulogic_vector(0 to 5); + signal is1_frb_buf4 :std_ulogic_vector(0 to 5); + signal is1_frc_buf4 :std_ulogic_vector(0 to 5); + signal is1_frt_buf4 :std_ulogic_vector(0 to 5); + signal is1_fra_buf5 :std_ulogic_vector(0 to 5); + signal is1_frb_buf5 :std_ulogic_vector(0 to 5); + signal is1_frc_buf5 :std_ulogic_vector(0 to 5); + signal is1_frt_buf5 :std_ulogic_vector(0 to 5); + signal is1_fra_buf6 :std_ulogic_vector(0 to 5); + signal is1_frb_buf6 :std_ulogic_vector(0 to 5); + signal is1_frc_buf6 :std_ulogic_vector(0 to 5); + signal is1_frt_buf6 :std_ulogic_vector(0 to 5); + + + + + signal is1_fra_buf2_b, is1_fra_buf1_b :std_ulogic_vector(0 to 5); + signal is1_frb_buf2_b, is1_frb_buf1_b :std_ulogic_vector(0 to 5); + signal is1_frc_buf2_b, is1_frc_buf1_b :std_ulogic_vector(0 to 5); + signal is1_frt_buf2_b, is1_frt_buf1_b :std_ulogic_vector(0 to 5); + + signal a_eq_lm0_x :std_ulogic_vector(0 to 5); + signal a_eq_lm0_01_b , a_eq_lm0_23_b , a_eq_lm0_45_b :std_ulogic; + signal a_eq_lm0_u ,a_eq_lm0_v , a_eq_lm0_b :std_ulogic; + signal b_eq_lm0_x :std_ulogic_vector(0 to 5); + signal b_eq_lm0_01_b , b_eq_lm0_23_b , b_eq_lm0_45_b :std_ulogic; + signal b_eq_lm0_u ,b_eq_lm0_v , b_eq_lm0_b :std_ulogic; + signal c_eq_lm0_x :std_ulogic_vector(0 to 5); + signal c_eq_lm0_01_b , c_eq_lm0_23_b , c_eq_lm0_45_b :std_ulogic; + signal c_eq_lm0_u ,c_eq_lm0_v , c_eq_lm0_b :std_ulogic; + signal t_eq_lm0_x :std_ulogic_vector(0 to 5); + signal t_eq_lm0_01_b , t_eq_lm0_23_b , t_eq_lm0_45_b :std_ulogic; + signal t_eq_lm0_u ,t_eq_lm0_v , t_eq_lm0_b :std_ulogic; + signal a_eq_lm1_x :std_ulogic_vector(0 to 5); + signal a_eq_lm1_01_b , a_eq_lm1_23_b , a_eq_lm1_45_b :std_ulogic; + signal a_eq_lm1_u ,a_eq_lm1_v , a_eq_lm1_b :std_ulogic; + signal b_eq_lm1_x :std_ulogic_vector(0 to 5); + signal b_eq_lm1_01_b , b_eq_lm1_23_b , b_eq_lm1_45_b :std_ulogic; + signal b_eq_lm1_u ,b_eq_lm1_v , b_eq_lm1_b :std_ulogic; + signal c_eq_lm1_x :std_ulogic_vector(0 to 5); + signal c_eq_lm1_01_b , c_eq_lm1_23_b , c_eq_lm1_45_b :std_ulogic; + signal c_eq_lm1_u ,c_eq_lm1_v , c_eq_lm1_b :std_ulogic; + signal t_eq_lm1_x :std_ulogic_vector(0 to 5); + signal t_eq_lm1_01_b , t_eq_lm1_23_b , t_eq_lm1_45_b :std_ulogic; + signal t_eq_lm1_u ,t_eq_lm1_v , t_eq_lm1_b :std_ulogic; + signal a_eq_lm2_x :std_ulogic_vector(0 to 5); + signal a_eq_lm2_01_b , a_eq_lm2_23_b , a_eq_lm2_45_b :std_ulogic; + signal a_eq_lm2_u ,a_eq_lm2_v , a_eq_lm2_b :std_ulogic; + signal b_eq_lm2_x :std_ulogic_vector(0 to 5); + signal b_eq_lm2_01_b , b_eq_lm2_23_b , b_eq_lm2_45_b :std_ulogic; + signal b_eq_lm2_u ,b_eq_lm2_v , b_eq_lm2_b :std_ulogic; + signal c_eq_lm2_x :std_ulogic_vector(0 to 5); + signal c_eq_lm2_01_b , c_eq_lm2_23_b , c_eq_lm2_45_b :std_ulogic; + signal c_eq_lm2_u ,c_eq_lm2_v , c_eq_lm2_b :std_ulogic; + signal t_eq_lm2_x :std_ulogic_vector(0 to 5); + signal t_eq_lm2_01_b , t_eq_lm2_23_b , t_eq_lm2_45_b :std_ulogic; + signal t_eq_lm2_u ,t_eq_lm2_v , t_eq_lm2_b :std_ulogic; + signal a_eq_lm3_x :std_ulogic_vector(0 to 5); + signal a_eq_lm3_01_b , a_eq_lm3_23_b , a_eq_lm3_45_b :std_ulogic; + signal a_eq_lm3_u ,a_eq_lm3_v , a_eq_lm3_b :std_ulogic; + signal b_eq_lm3_x :std_ulogic_vector(0 to 5); + signal b_eq_lm3_01_b , b_eq_lm3_23_b , b_eq_lm3_45_b :std_ulogic; + signal b_eq_lm3_u ,b_eq_lm3_v , b_eq_lm3_b :std_ulogic; + signal c_eq_lm3_x :std_ulogic_vector(0 to 5); + signal c_eq_lm3_01_b , c_eq_lm3_23_b , c_eq_lm3_45_b :std_ulogic; + signal c_eq_lm3_u ,c_eq_lm3_v , c_eq_lm3_b :std_ulogic; + signal t_eq_lm3_x :std_ulogic_vector(0 to 5); + signal t_eq_lm3_01_b , t_eq_lm3_23_b , t_eq_lm3_45_b :std_ulogic; + signal t_eq_lm3_u ,t_eq_lm3_v , t_eq_lm3_b :std_ulogic; + signal a_eq_lm4_x :std_ulogic_vector(0 to 5); + signal a_eq_lm4_01_b , a_eq_lm4_23_b , a_eq_lm4_45_b :std_ulogic; + signal a_eq_lm4_u ,a_eq_lm4_v , a_eq_lm4_b :std_ulogic; + signal b_eq_lm4_x :std_ulogic_vector(0 to 5); + signal b_eq_lm4_01_b , b_eq_lm4_23_b , b_eq_lm4_45_b :std_ulogic; + signal b_eq_lm4_u ,b_eq_lm4_v , b_eq_lm4_b :std_ulogic; + signal c_eq_lm4_x :std_ulogic_vector(0 to 5); + signal c_eq_lm4_01_b , c_eq_lm4_23_b , c_eq_lm4_45_b :std_ulogic; + signal c_eq_lm4_u ,c_eq_lm4_v , c_eq_lm4_b :std_ulogic; + signal t_eq_lm4_x :std_ulogic_vector(0 to 5); + signal t_eq_lm4_01_b , t_eq_lm4_23_b , t_eq_lm4_45_b :std_ulogic; + signal t_eq_lm4_u ,t_eq_lm4_v , t_eq_lm4_b :std_ulogic; + signal a_eq_lm5_x :std_ulogic_vector(0 to 5); + signal a_eq_lm5_01_b , a_eq_lm5_23_b , a_eq_lm5_45_b :std_ulogic; + signal a_eq_lm5_u ,a_eq_lm5_v , a_eq_lm5_b :std_ulogic; + signal b_eq_lm5_x :std_ulogic_vector(0 to 5); + signal b_eq_lm5_01_b , b_eq_lm5_23_b , b_eq_lm5_45_b :std_ulogic; + signal b_eq_lm5_u ,b_eq_lm5_v , b_eq_lm5_b :std_ulogic; + signal c_eq_lm5_x :std_ulogic_vector(0 to 5); + signal c_eq_lm5_01_b , c_eq_lm5_23_b , c_eq_lm5_45_b :std_ulogic; + signal c_eq_lm5_u ,c_eq_lm5_v , c_eq_lm5_b :std_ulogic; + signal t_eq_lm5_x :std_ulogic_vector(0 to 5); + signal t_eq_lm5_01_b , t_eq_lm5_23_b , t_eq_lm5_45_b :std_ulogic; + signal t_eq_lm5_u ,t_eq_lm5_v , t_eq_lm5_b :std_ulogic; + signal a_eq_lm6_x :std_ulogic_vector(0 to 5); + signal a_eq_lm6_01_b , a_eq_lm6_23_b , a_eq_lm6_45_b :std_ulogic; + signal a_eq_lm6_u ,a_eq_lm6_v , a_eq_lm6_b :std_ulogic; + signal b_eq_lm6_x :std_ulogic_vector(0 to 5); + signal b_eq_lm6_01_b , b_eq_lm6_23_b , b_eq_lm6_45_b :std_ulogic; + signal b_eq_lm6_u ,b_eq_lm6_v , b_eq_lm6_b :std_ulogic; + signal c_eq_lm6_x :std_ulogic_vector(0 to 5); + signal c_eq_lm6_01_b , c_eq_lm6_23_b , c_eq_lm6_45_b :std_ulogic; + signal c_eq_lm6_u ,c_eq_lm6_v , c_eq_lm6_b :std_ulogic; + signal t_eq_lm6_x :std_ulogic_vector(0 to 5); + signal t_eq_lm6_01_b , t_eq_lm6_23_b , t_eq_lm6_45_b :std_ulogic; + signal t_eq_lm6_u ,t_eq_lm6_v , t_eq_lm6_b :std_ulogic; + signal a_eq_lm7_x :std_ulogic_vector(0 to 5); + signal a_eq_lm7_01_b , a_eq_lm7_23_b , a_eq_lm7_45_b :std_ulogic; + signal a_eq_lm7_u ,a_eq_lm7_v , a_eq_lm7_b :std_ulogic; + signal b_eq_lm7_x :std_ulogic_vector(0 to 5); + signal b_eq_lm7_01_b , b_eq_lm7_23_b , b_eq_lm7_45_b :std_ulogic; + signal b_eq_lm7_u ,b_eq_lm7_v , b_eq_lm7_b :std_ulogic; + signal c_eq_lm7_x :std_ulogic_vector(0 to 5); + signal c_eq_lm7_01_b , c_eq_lm7_23_b , c_eq_lm7_45_b :std_ulogic; + signal c_eq_lm7_u ,c_eq_lm7_v , c_eq_lm7_b :std_ulogic; + signal t_eq_lm7_x :std_ulogic_vector(0 to 5); + signal t_eq_lm7_01_b , t_eq_lm7_23_b , t_eq_lm7_45_b :std_ulogic; + signal t_eq_lm7_u ,t_eq_lm7_v , t_eq_lm7_b :std_ulogic; + signal a_eq_lmc_ex4_x :std_ulogic_vector(0 to 5); + signal a_eq_lmc_ex4_01_b , a_eq_lmc_ex4_23_b , a_eq_lmc_ex4_45_b :std_ulogic; + signal a_eq_lmc_ex4_u ,a_eq_lmc_ex4_v , a_eq_lmc_ex4_b :std_ulogic; + signal b_eq_lmc_ex4_x :std_ulogic_vector(0 to 5); + signal b_eq_lmc_ex4_01_b , b_eq_lmc_ex4_23_b , b_eq_lmc_ex4_45_b :std_ulogic; + signal b_eq_lmc_ex4_u ,b_eq_lmc_ex4_v , b_eq_lmc_ex4_b :std_ulogic; + signal c_eq_lmc_ex4_x :std_ulogic_vector(0 to 5); + signal c_eq_lmc_ex4_01_b , c_eq_lmc_ex4_23_b , c_eq_lmc_ex4_45_b :std_ulogic; + signal c_eq_lmc_ex4_u ,c_eq_lmc_ex4_v , c_eq_lmc_ex4_b :std_ulogic; + signal a_eq_ex4_x :std_ulogic_vector(0 to 5); + signal a_eq_ex4_01_b , a_eq_ex4_23_b , a_eq_ex4_45_b :std_ulogic; + signal a_eq_ex4_u ,a_eq_ex4_v , a_eq_ex4_b :std_ulogic; + signal b_eq_ex4_x :std_ulogic_vector(0 to 5); + signal b_eq_ex4_01_b , b_eq_ex4_23_b , b_eq_ex4_45_b :std_ulogic; + signal b_eq_ex4_u ,b_eq_ex4_v , b_eq_ex4_b :std_ulogic; + signal u_eq_ex4_b :std_ulogic; + signal c_eq_ex4_x :std_ulogic_vector(0 to 5); + signal c_eq_ex4_01_b , c_eq_ex4_23_b , c_eq_ex4_45_b :std_ulogic; + signal c_eq_ex4_u ,c_eq_ex4_v , c_eq_ex4_b :std_ulogic; + signal a_eq_ex3_x :std_ulogic_vector(0 to 5); + signal a_eq_ex3_01_b , a_eq_ex3_23_b , a_eq_ex3_45_b :std_ulogic; + signal a_eq_ex3_u ,a_eq_ex3_v , a_eq_ex3_b :std_ulogic; + signal b_eq_ex3_x :std_ulogic_vector(0 to 5); + signal b_eq_ex3_01_b , b_eq_ex3_23_b , b_eq_ex3_45_b :std_ulogic; + signal b_eq_ex3_u ,b_eq_ex3_v , b_eq_ex3_b :std_ulogic; + signal u_eq_ex3_b :std_ulogic; + signal c_eq_ex3_x :std_ulogic_vector(0 to 5); + signal c_eq_ex3_01_b , c_eq_ex3_23_b , c_eq_ex3_45_b :std_ulogic; + signal c_eq_ex3_u ,c_eq_ex3_v , c_eq_ex3_b :std_ulogic; + signal a_eq_ex2_x :std_ulogic_vector(0 to 5); + signal a_eq_ex2_01_b , a_eq_ex2_23_b , a_eq_ex2_45_b :std_ulogic; + signal a_eq_ex2_u ,a_eq_ex2_v , a_eq_ex2_b :std_ulogic; + signal b_eq_ex2_x :std_ulogic_vector(0 to 5); + signal b_eq_ex2_01_b , b_eq_ex2_23_b , b_eq_ex2_45_b :std_ulogic; + signal b_eq_ex2_u ,b_eq_ex2_v , b_eq_ex2_b :std_ulogic; + signal u_eq_ex2_b :std_ulogic; + signal c_eq_ex2_x :std_ulogic_vector(0 to 5); + signal c_eq_ex2_01_b , c_eq_ex2_23_b , c_eq_ex2_45_b :std_ulogic; + signal c_eq_ex2_u ,c_eq_ex2_v , c_eq_ex2_b :std_ulogic; + signal a_eq_ex1_x :std_ulogic_vector(0 to 5); + signal a_eq_ex1_01_b , a_eq_ex1_23_b , a_eq_ex1_45_b :std_ulogic; + signal a_eq_ex1_u ,a_eq_ex1_v , a_eq_ex1_b :std_ulogic; + signal b_eq_ex1_x :std_ulogic_vector(0 to 5); + signal b_eq_ex1_01_b , b_eq_ex1_23_b , b_eq_ex1_45_b :std_ulogic; + signal b_eq_ex1_u ,b_eq_ex1_v , b_eq_ex1_b :std_ulogic; + signal u_eq_ex1_b :std_ulogic; + signal c_eq_ex1_x :std_ulogic_vector(0 to 5); + signal c_eq_ex1_01_b , c_eq_ex1_23_b , c_eq_ex1_45_b :std_ulogic; + signal c_eq_ex1_u ,c_eq_ex1_v , c_eq_ex1_b :std_ulogic; + signal a_eq_rf1_x :std_ulogic_vector(0 to 5); + signal a_eq_rf1_01_b , a_eq_rf1_23_b , a_eq_rf1_45_b :std_ulogic; + signal a_eq_rf1_u ,a_eq_rf1_v , a_eq_rf1_b :std_ulogic; + signal b_eq_rf1_x :std_ulogic_vector(0 to 5); + signal b_eq_rf1_01_b , b_eq_rf1_23_b , b_eq_rf1_45_b :std_ulogic; + signal b_eq_rf1_u ,b_eq_rf1_v , b_eq_rf1_b :std_ulogic; + signal u_eq_rf1_b :std_ulogic ; + signal c_eq_rf1_x :std_ulogic_vector(0 to 5); + signal c_eq_rf1_01_b , c_eq_rf1_23_b , c_eq_rf1_45_b :std_ulogic; + signal c_eq_rf1_u ,c_eq_rf1_v , c_eq_rf1_b :std_ulogic; + + signal a_eq_rf0_x :std_ulogic_vector(0 to 5); + signal a_eq_rf0_01_b , a_eq_rf0_23_b , a_eq_rf0_45_b :std_ulogic; + signal a_eq_rf0_u ,a_eq_rf0_v , a_eq_rf0_b :std_ulogic; + signal b_eq_rf0_x :std_ulogic_vector(0 to 5); + signal b_eq_rf0_01_b , b_eq_rf0_23_b , b_eq_rf0_45_b :std_ulogic; + signal b_eq_rf0_u ,b_eq_rf0_v , b_eq_rf0_b :std_ulogic; + signal u_eq_rf0_b :std_ulogic; + signal c_eq_rf0_x :std_ulogic_vector(0 to 5); + signal c_eq_rf0_01_b , c_eq_rf0_23_b , c_eq_rf0_45_b :std_ulogic; + signal c_eq_rf0_u ,c_eq_rf0_v , c_eq_rf0_b :std_ulogic; + signal a_eq_is2_x :std_ulogic_vector(0 to 5); + signal a_eq_is2_01_b , a_eq_is2_23_b , a_eq_is2_45_b :std_ulogic; + signal a_eq_is2_u ,a_eq_is2_v , a_eq_is2_b :std_ulogic; + signal b_eq_is2_x :std_ulogic_vector(0 to 5); + signal b_eq_is2_01_b , b_eq_is2_23_b , b_eq_is2_45_b :std_ulogic; + signal b_eq_is2_u ,b_eq_is2_v , b_eq_is2_b :std_ulogic; + signal u_eq_is2_b :std_ulogic; + signal c_eq_is2_x :std_ulogic_vector(0 to 5); + signal c_eq_is2_01_b , c_eq_is2_23_b , c_eq_is2_45_b :std_ulogic; + signal c_eq_is2_u ,c_eq_is2_v , c_eq_is2_b :std_ulogic; + + signal a_or_1_1 , a_or_1_2 , a_or_1_3 , a_or_1_4 :std_ulogic; + signal a_or_1_5 , a_or_1_6 , a_or_1_7 , a_or_1_8 :std_ulogic; + signal a_or_2_1_b , a_or_2_2_b , a_or_2_3_b , a_or_2_4_b :std_ulogic; + signal a_or_3_1 , a_or_3_2 , a_or_4_b :std_ulogic; + signal b_or_1_1 , b_or_1_2 , b_or_1_3 , b_or_1_4 :std_ulogic; + signal b_or_1_5 , b_or_1_6 , b_or_1_7 , b_or_1_8 :std_ulogic; + signal b_or_2_1_b , b_or_2_2_b , b_or_2_3_b , b_or_2_4_b :std_ulogic; + signal b_or_3_1 , b_or_3_2 , b_or_4_b :std_ulogic; + signal c_or_1_1 , c_or_1_2 , c_or_1_3 , c_or_1_4 :std_ulogic; + signal c_or_1_5 , c_or_1_6 , c_or_1_7 , c_or_1_8 :std_ulogic; + signal c_or_2_1_b , c_or_2_2_b , c_or_2_3_b , c_or_2_4_b :std_ulogic; + signal c_or_3_1 , c_or_3_2 , c_or_4_b :std_ulogic; + + signal t_or_1_1 , t_or_1_2 , t_or_1_3 , t_or_1_4 :std_ulogic; + signal t_or_2_1_b , t_or_2_2_b :std_ulogic; + signal t_or_3_1 , t_or_4_b :std_ulogic; + signal u_or_1_5 , u_or_1_6 , u_or_1_7 , u_or_1_8 :std_ulogic; + signal u_or_2_3_b , u_or_2_4_b , u_or_3_1 , u_or_4_b :std_ulogic; + + signal a_group_en :std_ulogic; + signal c_group_en :std_ulogic; + signal b_group_en :std_ulogic; + signal u_group_en :std_ulogic; + signal t_group_en :std_ulogic; + + signal lm0_a_cmp_en , lm0_b_cmp_en , lm0_c_cmp_en , lm0_t_cmp_en :std_ulogic; + signal lm1_a_cmp_en , lm1_b_cmp_en , lm1_c_cmp_en , lm1_t_cmp_en :std_ulogic; + signal lm2_a_cmp_en , lm2_b_cmp_en , lm2_c_cmp_en , lm2_t_cmp_en :std_ulogic; + signal lm3_a_cmp_en , lm3_b_cmp_en , lm3_c_cmp_en , lm3_t_cmp_en :std_ulogic; + signal lm4_a_cmp_en , lm4_b_cmp_en , lm4_c_cmp_en , lm4_t_cmp_en :std_ulogic; + signal lm5_a_cmp_en , lm5_b_cmp_en , lm5_c_cmp_en , lm5_t_cmp_en :std_ulogic; + signal lm6_a_cmp_en , lm6_b_cmp_en , lm6_c_cmp_en , lm6_t_cmp_en :std_ulogic; + signal lm7_a_cmp_en , lm7_b_cmp_en , lm7_c_cmp_en , lm7_t_cmp_en :std_ulogic; + signal lmc_ex4_a_cmp_en , lmc_ex4_b_cmp_en , lmc_ex4_c_cmp_en :std_ulogic; + signal is2_a_cmp_en , is2_b_cmp_en , is2_c_cmp_en , is2_u_cmp_en :std_ulogic; + signal rf0_a_cmp_en , rf0_b_cmp_en , rf0_c_cmp_en , rf0_u_cmp_en :std_ulogic; + signal rf1_a_cmp_en , rf1_b_cmp_en , rf1_c_cmp_en , rf1_u_cmp_en :std_ulogic; + signal ex1_a_cmp_en , ex1_b_cmp_en , ex1_c_cmp_en , ex1_u_cmp_en :std_ulogic; + signal ex2_a_cmp_en , ex2_b_cmp_en , ex2_c_cmp_en , ex2_u_cmp_en :std_ulogic; + signal ex3_a_cmp_en , ex3_b_cmp_en , ex3_c_cmp_en , ex3_u_cmp_en :std_ulogic; + signal ex4_a_cmp_en , ex4_b_cmp_en , ex4_c_cmp_en , ex4_u_cmp_en :std_ulogic; + +signal lm0_valid : std_ulogic; +signal lm1_valid : std_ulogic; +signal lm2_valid : std_ulogic; +signal lm3_valid : std_ulogic; +signal lm4_valid : std_ulogic; +signal lm5_valid : std_ulogic; +signal lm6_valid : std_ulogic; +signal lm7_valid : std_ulogic; + + + + + + + + + + + + + + + + + + + + + + + + +begin + + + + ucmp_lm0tabufb: lm0_ta_buf_b(0 to 5) <= not lm0_ta(0 to 5); + ucmp_lm1tabufb: lm1_ta_buf_b(0 to 5) <= not lm1_ta(0 to 5); + ucmp_lm2tabufb: lm2_ta_buf_b(0 to 5) <= not lm2_ta(0 to 5); + ucmp_lm3tabufb: lm3_ta_buf_b(0 to 5) <= not lm3_ta(0 to 5); + ucmp_lm4tabufb: lm4_ta_buf_b(0 to 5) <= not lm4_ta(0 to 5); + ucmp_lm5tabufb: lm5_ta_buf_b(0 to 5) <= not lm5_ta(0 to 5); + ucmp_lm6tabufb: lm6_ta_buf_b(0 to 5) <= not lm6_ta(0 to 5); + ucmp_lm7tabufb: lm7_ta_buf_b(0 to 5) <= not lm7_ta(0 to 5); + ucmp_lmxtabufb: lmc_ex4_buf_b(0 to 5) <= not lmc_ex4(0 to 5); + ucmp_ex4tabufb: ex4_ta_buf_b(0 to 5) <= not ex4_ta(0 to 5); + ucmp_ex3tabufb: ex3_ta_buf_b(0 to 5) <= not ex3_ta(0 to 5); + ucmp_ex2tabufb: ex2_ta_buf_b(0 to 5) <= not ex2_ta(0 to 5); + ucmp_ex1tabufb: ex1_ta_buf_b(0 to 5) <= not ex1_ta(0 to 5); + ucmp_rf1tabufb: rf1_ta_buf_b(0 to 5) <= not rf1_ta(0 to 5); + ucmp_rf0tabufb: rf0_ta_buf_b(0 to 5) <= not rf0_ta(0 to 5); + ucmp_is2tabufb: is2_ta_buf_b(0 to 5) <= not is2_ta(0 to 5); + + ucmp_lm0tabuf: lm0_ta_buf(0 to 5) <= not lm0_ta_buf_b (0 to 5); + ucmp_lm1tabuf: lm1_ta_buf(0 to 5) <= not lm1_ta_buf_b (0 to 5); + ucmp_lm2tabuf: lm2_ta_buf(0 to 5) <= not lm2_ta_buf_b (0 to 5); + ucmp_lm3tabuf: lm3_ta_buf(0 to 5) <= not lm3_ta_buf_b (0 to 5); + ucmp_lm4tabuf: lm4_ta_buf(0 to 5) <= not lm4_ta_buf_b (0 to 5); + ucmp_lm5tabuf: lm5_ta_buf(0 to 5) <= not lm5_ta_buf_b (0 to 5); + ucmp_lm6tabuf: lm6_ta_buf(0 to 5) <= not lm6_ta_buf_b (0 to 5); + ucmp_lm7tabuf: lm7_ta_buf(0 to 5) <= not lm7_ta_buf_b (0 to 5); + ucmp_lmxtabuf: lmc_ex4_buf(0 to 5) <= not lmc_ex4_buf_b (0 to 5); + ucmp_ex4tabuf: ex4_ta_buf(0 to 5) <= not ex4_ta_buf_b (0 to 5); + ucmp_ex3tabuf: ex3_ta_buf(0 to 5) <= not ex3_ta_buf_b (0 to 5); + ucmp_ex2tabuf: ex2_ta_buf(0 to 5) <= not ex2_ta_buf_b (0 to 5); + ucmp_ex1tabuf: ex1_ta_buf(0 to 5) <= not ex1_ta_buf_b (0 to 5); + ucmp_rf1tabuf: rf1_ta_buf(0 to 5) <= not rf1_ta_buf_b (0 to 5); + ucmp_rf0tabuf: rf0_ta_buf(0 to 5) <= not rf0_ta_buf_b (0 to 5); + ucmp_is2tabuf: is2_ta_buf(0 to 5) <= not is2_ta_buf_b (0 to 5); + + ucmp_is1frabufb1: is1_fra_buf1_b(0 to 5) <= not is1_fra(0 to 5); + ucmp_is1frbbufb1: is1_frb_buf1_b(0 to 5) <= not is1_frb(0 to 5); + ucmp_is1frcbufb1: is1_frc_buf1_b(0 to 5) <= not is1_frc(0 to 5); + ucmp_is1frtbufb1: is1_frt_buf1_b(0 to 5) <= not is1_ta(0 to 5); + + ucmp_is1frabufb2: is1_fra_buf2_b(0 to 5) <= not is1_fra(0 to 5); + ucmp_is1frbbufb2: is1_frb_buf2_b(0 to 5) <= not is1_frb(0 to 5); + ucmp_is1frcbufb2: is1_frc_buf2_b(0 to 5) <= not is1_frc(0 to 5); + ucmp_is1frtbufb2: is1_frt_buf2_b(0 to 5) <= not is1_ta(0 to 5); + + ucmp_is1frabuf1: is1_fra_buf1(0 to 5) <= not is1_fra_buf1_b(0 to 5); + ucmp_is1frbbuf1: is1_frb_buf1(0 to 5) <= not is1_frb_buf1_b(0 to 5); + ucmp_is1frcbuf1: is1_frc_buf1(0 to 5) <= not is1_frc_buf1_b(0 to 5); + ucmp_is1frtbuf1: is1_frt_buf1(0 to 5) <= not is1_frt_buf1_b(0 to 5); + + ucmp_is1frabuf2: is1_fra_buf2(0 to 5) <= not is1_fra_buf1_b(0 to 5); + ucmp_is1frbbuf2: is1_frb_buf2(0 to 5) <= not is1_frb_buf1_b(0 to 5); + ucmp_is1frcbuf2: is1_frc_buf2(0 to 5) <= not is1_frc_buf1_b(0 to 5); + ucmp_is1frtbuf2: is1_frt_buf2(0 to 5) <= not is1_frt_buf1_b(0 to 5); + + ucmp_is1frabuf3: is1_fra_buf3(0 to 5) <= not is1_fra_buf1_b(0 to 5); + ucmp_is1frbbuf3: is1_frb_buf3(0 to 5) <= not is1_frb_buf1_b(0 to 5); + ucmp_is1frcbuf3: is1_frc_buf3(0 to 5) <= not is1_frc_buf1_b(0 to 5); + ucmp_is1frtbuf3: is1_frt_buf3(0 to 5) <= not is1_frt_buf1_b(0 to 5); + + + ucmp_is1frabuf4: is1_fra_buf4(0 to 5) <= not is1_fra_buf2_b(0 to 5); + ucmp_is1frbbuf4: is1_frb_buf4(0 to 5) <= not is1_frb_buf2_b(0 to 5); + ucmp_is1frcbuf4: is1_frc_buf4(0 to 5) <= not is1_frc_buf2_b(0 to 5); + ucmp_is1frtbuf4: is1_frt_buf4(0 to 5) <= not is1_frt_buf2_b(0 to 5); + + ucmp_is1frabuf5: is1_fra_buf5(0 to 5) <= not is1_fra_buf2_b(0 to 5); + ucmp_is1frbbuf5: is1_frb_buf5(0 to 5) <= not is1_frb_buf2_b(0 to 5); + ucmp_is1frcbuf5: is1_frc_buf5(0 to 5) <= not is1_frc_buf2_b(0 to 5); + ucmp_is1frtbuf5: is1_frt_buf5(0 to 5) <= not is1_frt_buf2_b(0 to 5); + + ucmp_is1frabuf6: is1_fra_buf6(0 to 5) <= not is1_fra_buf2_b(0 to 5); + ucmp_is1frbbuf6: is1_frb_buf6(0 to 5) <= not is1_frb_buf2_b(0 to 5); + ucmp_is1frcbuf6: is1_frc_buf6(0 to 5) <= not is1_frc_buf2_b(0 to 5); + ucmp_is1frtbuf6: is1_frt_buf6(0 to 5) <= not is1_frt_buf2_b(0 to 5); + + + + + + + + ucmp_aeqis2_x: a_eq_is2_x(0 to 5) <= not( is2_ta_buf(0 to 5) xor is1_fra_buf1(0 to 5) ); + ucmp_aeqis2_01: a_eq_is2_01_b <= not( a_eq_is2_x(0) and a_eq_is2_x(1) ); + ucmp_aeqis2_23: a_eq_is2_23_b <= not( a_eq_is2_x(2) and a_eq_is2_x(3) ); + ucmp_aeqis2_45: a_eq_is2_45_b <= not( a_eq_is2_x(4) and a_eq_is2_x(5) ); + ucmp_aeqis2_u: a_eq_is2_u <= not( a_eq_is2_01_b or a_eq_is2_23_b ); + ucmp_aeqis2_w: a_eq_is2_v <= not( a_eq_is2_45_b ); + ucmp_aeqis2: a_eq_is2_b <= not( a_eq_is2_u and a_eq_is2_v and is2_a_cmp_en ); + + ucmp_aeqrf0_x: a_eq_rf0_x(0 to 5) <= not( rf0_ta_buf(0 to 5) xor is1_fra_buf1(0 to 5) ); + ucmp_aeqrf0_01: a_eq_rf0_01_b <= not( a_eq_rf0_x(0) and a_eq_rf0_x(1) ); + ucmp_aeqrf0_23: a_eq_rf0_23_b <= not( a_eq_rf0_x(2) and a_eq_rf0_x(3) ); + ucmp_aeqrf0_45: a_eq_rf0_45_b <= not( a_eq_rf0_x(4) and a_eq_rf0_x(5) ); + ucmp_aeqrf0_u: a_eq_rf0_u <= not( a_eq_rf0_01_b or a_eq_rf0_23_b ); + ucmp_aeqrf0_w: a_eq_rf0_v <= not( a_eq_rf0_45_b ); + ucmp_aeqrf0: a_eq_rf0_b <= not( a_eq_rf0_u and a_eq_rf0_v and rf0_a_cmp_en ); + + ucmp_aeqrf1_x: a_eq_rf1_x(0 to 5) <= not( rf1_ta_buf(0 to 5) xor is1_fra_buf1(0 to 5) ); + ucmp_aeqrf1_01: a_eq_rf1_01_b <= not( a_eq_rf1_x(0) and a_eq_rf1_x(1) ); + ucmp_aeqrf1_23: a_eq_rf1_23_b <= not( a_eq_rf1_x(2) and a_eq_rf1_x(3) ); + ucmp_aeqrf1_45: a_eq_rf1_45_b <= not( a_eq_rf1_x(4) and a_eq_rf1_x(5) ); + ucmp_aeqrf1_u: a_eq_rf1_u <= not( a_eq_rf1_01_b or a_eq_rf1_23_b ); + ucmp_aeqrf1_w: a_eq_rf1_v <= not( a_eq_rf1_45_b ); + ucmp_aeqrf1: a_eq_rf1_b <= not( a_eq_rf1_u and a_eq_rf1_v and rf1_a_cmp_en ); + + ucmp_aeqex1_x: a_eq_ex1_x(0 to 5) <= not( ex1_ta_buf(0 to 5) xor is1_fra_buf2(0 to 5) ); + ucmp_aeqex1_01: a_eq_ex1_01_b <= not( a_eq_ex1_x(0) and a_eq_ex1_x(1) ); + ucmp_aeqex1_23: a_eq_ex1_23_b <= not( a_eq_ex1_x(2) and a_eq_ex1_x(3) ); + ucmp_aeqex1_45: a_eq_ex1_45_b <= not( a_eq_ex1_x(4) and a_eq_ex1_x(5) ); + ucmp_aeqex1_u: a_eq_ex1_u <= not( a_eq_ex1_01_b or a_eq_ex1_23_b ); + ucmp_aeqex1_w: a_eq_ex1_v <= not( a_eq_ex1_45_b ); + ucmp_aeqex1: a_eq_ex1_b <= not( a_eq_ex1_u and a_eq_ex1_v and ex1_a_cmp_en ); + + ucmp_aeqex2_x: a_eq_ex2_x(0 to 5) <= not( ex2_ta_buf(0 to 5) xor is1_fra_buf2(0 to 5) ); + ucmp_aeqex2_01: a_eq_ex2_01_b <= not( a_eq_ex2_x(0) and a_eq_ex2_x(1) ); + ucmp_aeqex2_23: a_eq_ex2_23_b <= not( a_eq_ex2_x(2) and a_eq_ex2_x(3) ); + ucmp_aeqex2_45: a_eq_ex2_45_b <= not( a_eq_ex2_x(4) and a_eq_ex2_x(5) ); + ucmp_aeqex2_u: a_eq_ex2_u <= not( a_eq_ex2_01_b or a_eq_ex2_23_b ); + ucmp_aeqex2_w: a_eq_ex2_v <= not( a_eq_ex2_45_b ); + ucmp_aeqex2: a_eq_ex2_b <= not( a_eq_ex2_u and a_eq_ex2_v and ex2_a_cmp_en ); + + ucmp_aeqex3_x: a_eq_ex3_x(0 to 5) <= not( ex3_ta_buf(0 to 5) xor is1_fra_buf2(0 to 5) ); + ucmp_aeqex3_01: a_eq_ex3_01_b <= not( a_eq_ex3_x(0) and a_eq_ex3_x(1) ); + ucmp_aeqex3_23: a_eq_ex3_23_b <= not( a_eq_ex3_x(2) and a_eq_ex3_x(3) ); + ucmp_aeqex3_45: a_eq_ex3_45_b <= not( a_eq_ex3_x(4) and a_eq_ex3_x(5) ); + ucmp_aeqex3_u: a_eq_ex3_u <= not( a_eq_ex3_01_b or a_eq_ex3_23_b ); + ucmp_aeqex3_w: a_eq_ex3_v <= not( a_eq_ex3_45_b ); + ucmp_aeqex3: a_eq_ex3_b <= not( a_eq_ex3_u and a_eq_ex3_v and ex3_a_cmp_en ); + + ucmp_aeqex4_x: a_eq_ex4_x(0 to 5) <= not( ex4_ta_buf(0 to 5) xor is1_fra_buf3(0 to 5) ); + ucmp_aeqex4_01: a_eq_ex4_01_b <= not( a_eq_ex4_x(0) and a_eq_ex4_x(1) ); + ucmp_aeqex4_23: a_eq_ex4_23_b <= not( a_eq_ex4_x(2) and a_eq_ex4_x(3) ); + ucmp_aeqex4_45: a_eq_ex4_45_b <= not( a_eq_ex4_x(4) and a_eq_ex4_x(5) ); + ucmp_aeqex4_u: a_eq_ex4_u <= not( a_eq_ex4_01_b or a_eq_ex4_23_b ); + ucmp_aeqex4_w: a_eq_ex4_v <= not( a_eq_ex4_45_b ); + ucmp_aeqex4: a_eq_ex4_b <= not( a_eq_ex4_u and a_eq_ex4_v and ex4_a_cmp_en ); + + + ucmp_aeqlmx_x: a_eq_lmc_ex4_x(0 to 5) <= not( lmc_ex4_buf(0 to 5) xor is1_fra_buf3(0 to 5) ); + ucmp_aeqlmx_01: a_eq_lmc_ex4_01_b <= not( a_eq_lmc_ex4_x(0) and a_eq_lmc_ex4_x(1) ); + ucmp_aeqlmx_23: a_eq_lmc_ex4_23_b <= not( a_eq_lmc_ex4_x(2) and a_eq_lmc_ex4_x(3) ); + ucmp_aeqlmx_45: a_eq_lmc_ex4_45_b <= not( a_eq_lmc_ex4_x(4) and a_eq_lmc_ex4_x(5) ); + ucmp_aeqlmx_u: a_eq_lmc_ex4_u <= not( a_eq_lmc_ex4_01_b or a_eq_lmc_ex4_23_b ); + ucmp_aeqlmx_w: a_eq_lmc_ex4_v <= not( a_eq_lmc_ex4_45_b ); + ucmp_aeqlmx: a_eq_lmc_ex4_b <= not( a_eq_lmc_ex4_u and a_eq_lmc_ex4_v and lmc_ex4_a_cmp_en ); + + ucmp_aeqlm0_x: a_eq_lm0_x(0 to 5) <= not( lm0_ta_buf(0 to 5) xor is1_fra_buf3(0 to 5) ); + ucmp_aeqlm0_01: a_eq_lm0_01_b <= not( a_eq_lm0_x(0) and a_eq_lm0_x(1) ); + ucmp_aeqlm0_23: a_eq_lm0_23_b <= not( a_eq_lm0_x(2) and a_eq_lm0_x(3) ); + ucmp_aeqlm0_45: a_eq_lm0_45_b <= not( a_eq_lm0_x(4) and a_eq_lm0_x(5) ); + ucmp_aeqlm0_u: a_eq_lm0_u <= not( a_eq_lm0_01_b or a_eq_lm0_23_b ); + ucmp_aeqlm0_w: a_eq_lm0_v <= not( a_eq_lm0_45_b ); + ucmp_aeqlm0: a_eq_lm0_b <= not( a_eq_lm0_u and a_eq_lm0_v and lm0_a_cmp_en ); + + ucmp_aeqlm1_x: a_eq_lm1_x(0 to 5) <= not( lm1_ta_buf(0 to 5) xor is1_fra_buf4(0 to 5) ); + ucmp_aeqlm1_01: a_eq_lm1_01_b <= not( a_eq_lm1_x(0) and a_eq_lm1_x(1) ); + ucmp_aeqlm1_23: a_eq_lm1_23_b <= not( a_eq_lm1_x(2) and a_eq_lm1_x(3) ); + ucmp_aeqlm1_45: a_eq_lm1_45_b <= not( a_eq_lm1_x(4) and a_eq_lm1_x(5) ); + ucmp_aeqlm1_u: a_eq_lm1_u <= not( a_eq_lm1_01_b or a_eq_lm1_23_b ); + ucmp_aeqlm1_w: a_eq_lm1_v <= not( a_eq_lm1_45_b ); + ucmp_aeqlm1: a_eq_lm1_b <= not( a_eq_lm1_u and a_eq_lm1_v and lm1_a_cmp_en ); + + ucmp_aeqlm2_x: a_eq_lm2_x(0 to 5) <= not( lm2_ta_buf(0 to 5) xor is1_fra_buf4(0 to 5) ); + ucmp_aeqlm2_01: a_eq_lm2_01_b <= not( a_eq_lm2_x(0) and a_eq_lm2_x(1) ); + ucmp_aeqlm2_23: a_eq_lm2_23_b <= not( a_eq_lm2_x(2) and a_eq_lm2_x(3) ); + ucmp_aeqlm2_45: a_eq_lm2_45_b <= not( a_eq_lm2_x(4) and a_eq_lm2_x(5) ); + ucmp_aeqlm2_u: a_eq_lm2_u <= not( a_eq_lm2_01_b or a_eq_lm2_23_b ); + ucmp_aeqlm2_w: a_eq_lm2_v <= not( a_eq_lm2_45_b ); + ucmp_aeqlm2: a_eq_lm2_b <= not( a_eq_lm2_u and a_eq_lm2_v and lm2_a_cmp_en ); + + ucmp_aeqlm3_x: a_eq_lm3_x(0 to 5) <= not( lm3_ta_buf(0 to 5) xor is1_fra_buf4(0 to 5) ); + ucmp_aeqlm3_01: a_eq_lm3_01_b <= not( a_eq_lm3_x(0) and a_eq_lm3_x(1) ); + ucmp_aeqlm3_23: a_eq_lm3_23_b <= not( a_eq_lm3_x(2) and a_eq_lm3_x(3) ); + ucmp_aeqlm3_45: a_eq_lm3_45_b <= not( a_eq_lm3_x(4) and a_eq_lm3_x(5) ); + ucmp_aeqlm3_u: a_eq_lm3_u <= not( a_eq_lm3_01_b or a_eq_lm3_23_b ); + ucmp_aeqlm3_w: a_eq_lm3_v <= not( a_eq_lm3_45_b ); + ucmp_aeqlm3: a_eq_lm3_b <= not( a_eq_lm3_u and a_eq_lm3_v and lm3_a_cmp_en ); + + ucmp_aeqlm4_x: a_eq_lm4_x(0 to 5) <= not( lm4_ta_buf(0 to 5) xor is1_fra_buf5(0 to 5) ); + ucmp_aeqlm4_01: a_eq_lm4_01_b <= not( a_eq_lm4_x(0) and a_eq_lm4_x(1) ); + ucmp_aeqlm4_23: a_eq_lm4_23_b <= not( a_eq_lm4_x(2) and a_eq_lm4_x(3) ); + ucmp_aeqlm4_45: a_eq_lm4_45_b <= not( a_eq_lm4_x(4) and a_eq_lm4_x(5) ); + ucmp_aeqlm4_u: a_eq_lm4_u <= not( a_eq_lm4_01_b or a_eq_lm4_23_b ); + ucmp_aeqlm4_w: a_eq_lm4_v <= not( a_eq_lm4_45_b ); + ucmp_aeqlm4: a_eq_lm4_b <= not( a_eq_lm4_u and a_eq_lm4_v and lm4_a_cmp_en ); + + ucmp_aeqlm5_x: a_eq_lm5_x(0 to 5) <= not( lm5_ta_buf(0 to 5) xor is1_fra_buf5(0 to 5) ); + ucmp_aeqlm5_01: a_eq_lm5_01_b <= not( a_eq_lm5_x(0) and a_eq_lm5_x(1) ); + ucmp_aeqlm5_23: a_eq_lm5_23_b <= not( a_eq_lm5_x(2) and a_eq_lm5_x(3) ); + ucmp_aeqlm5_45: a_eq_lm5_45_b <= not( a_eq_lm5_x(4) and a_eq_lm5_x(5) ); + ucmp_aeqlm5_u: a_eq_lm5_u <= not( a_eq_lm5_01_b or a_eq_lm5_23_b ); + ucmp_aeqlm5_w: a_eq_lm5_v <= not( a_eq_lm5_45_b ); + ucmp_aeqlm5: a_eq_lm5_b <= not( a_eq_lm5_u and a_eq_lm5_v and lm5_a_cmp_en ); + + ucmp_aeqlm6_x: a_eq_lm6_x(0 to 5) <= not( lm6_ta_buf(0 to 5) xor is1_fra_buf6(0 to 5) ); + ucmp_aeqlm6_01: a_eq_lm6_01_b <= not( a_eq_lm6_x(0) and a_eq_lm6_x(1) ); + ucmp_aeqlm6_23: a_eq_lm6_23_b <= not( a_eq_lm6_x(2) and a_eq_lm6_x(3) ); + ucmp_aeqlm6_45: a_eq_lm6_45_b <= not( a_eq_lm6_x(4) and a_eq_lm6_x(5) ); + ucmp_aeqlm6_u: a_eq_lm6_u <= not( a_eq_lm6_01_b or a_eq_lm6_23_b ); + ucmp_aeqlm6_w: a_eq_lm6_v <= not( a_eq_lm6_45_b ); + ucmp_aeqlm6: a_eq_lm6_b <= not( a_eq_lm6_u and a_eq_lm6_v and lm6_a_cmp_en ); + + ucmp_aeqlm7_x: a_eq_lm7_x(0 to 5) <= not( lm7_ta_buf(0 to 5) xor is1_fra_buf6(0 to 5) ); + ucmp_aeqlm7_01: a_eq_lm7_01_b <= not( a_eq_lm7_x(0) and a_eq_lm7_x(1) ); + ucmp_aeqlm7_23: a_eq_lm7_23_b <= not( a_eq_lm7_x(2) and a_eq_lm7_x(3) ); + ucmp_aeqlm7_45: a_eq_lm7_45_b <= not( a_eq_lm7_x(4) and a_eq_lm7_x(5) ); + ucmp_aeqlm7_u: a_eq_lm7_u <= not( a_eq_lm7_01_b or a_eq_lm7_23_b ); + ucmp_aeqlm7_w: a_eq_lm7_v <= not( a_eq_lm7_45_b ); + ucmp_aeqlm7: a_eq_lm7_b <= not( a_eq_lm7_u and a_eq_lm7_v and lm7_a_cmp_en ); + + + + + + ucmp_beqis2_x: b_eq_is2_x(0 to 5) <= not( is2_ta_buf(0 to 5) xor is1_frb_buf1(0 to 5) ); + ucmp_beqis2_01: b_eq_is2_01_b <= not( b_eq_is2_x(0) and b_eq_is2_x(1) ); + ucmp_beqis2_23: b_eq_is2_23_b <= not( b_eq_is2_x(2) and b_eq_is2_x(3) ); + ucmp_beqis2_45: b_eq_is2_45_b <= not( b_eq_is2_x(4) and b_eq_is2_x(5) ); + ucmp_beqis2_u: b_eq_is2_u <= not( b_eq_is2_01_b or b_eq_is2_23_b ); + ucmp_beqis2_w: b_eq_is2_v <= not( b_eq_is2_45_b ); + ucmp_beqis2: b_eq_is2_b <= not( b_eq_is2_u and b_eq_is2_v and is2_b_cmp_en ); + ucmp_beqis2_uc: u_eq_is2_b <= not( b_eq_is2_u and b_eq_is2_v and is2_u_cmp_en ); + + ucmp_beqrf0_x: b_eq_rf0_x(0 to 5) <= not( rf0_ta_buf(0 to 5) xor is1_frb_buf1(0 to 5) ); + ucmp_beqrf0_01: b_eq_rf0_01_b <= not( b_eq_rf0_x(0) and b_eq_rf0_x(1) ); + ucmp_beqrf0_23: b_eq_rf0_23_b <= not( b_eq_rf0_x(2) and b_eq_rf0_x(3) ); + ucmp_beqrf0_45: b_eq_rf0_45_b <= not( b_eq_rf0_x(4) and b_eq_rf0_x(5) ); + ucmp_beqrf0_u: b_eq_rf0_u <= not( b_eq_rf0_01_b or b_eq_rf0_23_b ); + ucmp_beqrf0_w: b_eq_rf0_v <= not( b_eq_rf0_45_b ); + ucmp_beqrf0: b_eq_rf0_b <= not( b_eq_rf0_u and b_eq_rf0_v and rf0_b_cmp_en ); + ucmp_beqrf0_uc: u_eq_rf0_b <= not( b_eq_rf0_u and b_eq_rf0_v and rf0_u_cmp_en ); + + ucmp_beqrf1_x: b_eq_rf1_x(0 to 5) <= not( rf1_ta_buf(0 to 5) xor is1_frb_buf1(0 to 5) ); + ucmp_beqrf1_01: b_eq_rf1_01_b <= not( b_eq_rf1_x(0) and b_eq_rf1_x(1) ); + ucmp_beqrf1_23: b_eq_rf1_23_b <= not( b_eq_rf1_x(2) and b_eq_rf1_x(3) ); + ucmp_beqrf1_45: b_eq_rf1_45_b <= not( b_eq_rf1_x(4) and b_eq_rf1_x(5) ); + ucmp_beqrf1_u: b_eq_rf1_u <= not( b_eq_rf1_01_b or b_eq_rf1_23_b ); + ucmp_beqrf1_w: b_eq_rf1_v <= not( b_eq_rf1_45_b ); + ucmp_beqrf1: b_eq_rf1_b <= not( b_eq_rf1_u and b_eq_rf1_v and rf1_b_cmp_en ); + ucmp_beqrf1_uc: u_eq_rf1_b <= not( b_eq_rf1_u and b_eq_rf1_v and rf1_u_cmp_en ); + + ucmp_beqex1_x: b_eq_ex1_x(0 to 5) <= not( ex1_ta_buf(0 to 5) xor is1_frb_buf2(0 to 5) ); + ucmp_beqex1_01: b_eq_ex1_01_b <= not( b_eq_ex1_x(0) and b_eq_ex1_x(1) ); + ucmp_beqex1_23: b_eq_ex1_23_b <= not( b_eq_ex1_x(2) and b_eq_ex1_x(3) ); + ucmp_beqex1_45: b_eq_ex1_45_b <= not( b_eq_ex1_x(4) and b_eq_ex1_x(5) ); + ucmp_beqex1_u: b_eq_ex1_u <= not( b_eq_ex1_01_b or b_eq_ex1_23_b ); + ucmp_beqex1_w: b_eq_ex1_v <= not( b_eq_ex1_45_b ); + ucmp_beqex1: b_eq_ex1_b <= not( b_eq_ex1_u and b_eq_ex1_v and ex1_b_cmp_en ); + ucmp_beqex1_uc: u_eq_ex1_b <= not( b_eq_ex1_u and b_eq_ex1_v and ex1_u_cmp_en ); + + ucmp_beqex2_x: b_eq_ex2_x(0 to 5) <= not( ex2_ta_buf(0 to 5) xor is1_frb_buf2(0 to 5) ); + ucmp_beqex2_01: b_eq_ex2_01_b <= not( b_eq_ex2_x(0) and b_eq_ex2_x(1) ); + ucmp_beqex2_23: b_eq_ex2_23_b <= not( b_eq_ex2_x(2) and b_eq_ex2_x(3) ); + ucmp_beqex2_45: b_eq_ex2_45_b <= not( b_eq_ex2_x(4) and b_eq_ex2_x(5) ); + ucmp_beqex2_u: b_eq_ex2_u <= not( b_eq_ex2_01_b or b_eq_ex2_23_b ); + ucmp_beqex2_w: b_eq_ex2_v <= not( b_eq_ex2_45_b ); + ucmp_beqex2: b_eq_ex2_b <= not( b_eq_ex2_u and b_eq_ex2_v and ex2_b_cmp_en ); + ucmp_beqex2_uc: u_eq_ex2_b <= not( b_eq_ex2_u and b_eq_ex2_v and ex2_u_cmp_en ); + + ucmp_beqex3_x: b_eq_ex3_x(0 to 5) <= not( ex3_ta_buf(0 to 5) xor is1_frb_buf2(0 to 5) ); + ucmp_beqex3_01: b_eq_ex3_01_b <= not( b_eq_ex3_x(0) and b_eq_ex3_x(1) ); + ucmp_beqex3_23: b_eq_ex3_23_b <= not( b_eq_ex3_x(2) and b_eq_ex3_x(3) ); + ucmp_beqex3_45: b_eq_ex3_45_b <= not( b_eq_ex3_x(4) and b_eq_ex3_x(5) ); + ucmp_beqex3_u: b_eq_ex3_u <= not( b_eq_ex3_01_b or b_eq_ex3_23_b ); + ucmp_beqex3_w: b_eq_ex3_v <= not( b_eq_ex3_45_b ); + ucmp_beqex3: b_eq_ex3_b <= not( b_eq_ex3_u and b_eq_ex3_v and ex3_b_cmp_en ); + ucmp_beqex3_uc: u_eq_ex3_b <= not( b_eq_ex3_u and b_eq_ex3_v and ex3_u_cmp_en ); + + ucmp_beqex4_x: b_eq_ex4_x(0 to 5) <= not( ex4_ta_buf(0 to 5) xor is1_frb_buf3(0 to 5) ); + ucmp_beqex4_01: b_eq_ex4_01_b <= not( b_eq_ex4_x(0) and b_eq_ex4_x(1) ); + ucmp_beqex4_23: b_eq_ex4_23_b <= not( b_eq_ex4_x(2) and b_eq_ex4_x(3) ); + ucmp_beqex4_45: b_eq_ex4_45_b <= not( b_eq_ex4_x(4) and b_eq_ex4_x(5) ); + ucmp_beqex4_u: b_eq_ex4_u <= not( b_eq_ex4_01_b or b_eq_ex4_23_b ); + ucmp_beqex4_w: b_eq_ex4_v <= not( b_eq_ex4_45_b ); + ucmp_beqex4: b_eq_ex4_b <= not( b_eq_ex4_u and b_eq_ex4_v and ex4_b_cmp_en ); + ucmp_beqex4_uc: u_eq_ex4_b <= not( b_eq_ex4_u and b_eq_ex4_v and ex4_u_cmp_en ); + + ucmp_beqlmx_x: b_eq_lmc_ex4_x(0 to 5) <= not( lmc_ex4_buf(0 to 5) xor is1_frb_buf3(0 to 5) ); + ucmp_beqlmx_01: b_eq_lmc_ex4_01_b <= not( b_eq_lmc_ex4_x(0) and b_eq_lmc_ex4_x(1) ); + ucmp_beqlmx_23: b_eq_lmc_ex4_23_b <= not( b_eq_lmc_ex4_x(2) and b_eq_lmc_ex4_x(3) ); + ucmp_beqlmx_45: b_eq_lmc_ex4_45_b <= not( b_eq_lmc_ex4_x(4) and b_eq_lmc_ex4_x(5) ); + ucmp_beqlmx_u: b_eq_lmc_ex4_u <= not( b_eq_lmc_ex4_01_b or b_eq_lmc_ex4_23_b ); + ucmp_beqlmx_w: b_eq_lmc_ex4_v <= not( b_eq_lmc_ex4_45_b ); + ucmp_beqlmx: b_eq_lmc_ex4_b <= not( b_eq_lmc_ex4_u and b_eq_lmc_ex4_v and lmc_ex4_b_cmp_en ); + + ucmp_beqlm0_x: b_eq_lm0_x(0 to 5) <= not( lm0_ta_buf(0 to 5) xor is1_frb_buf3(0 to 5) ); + ucmp_beqlm0_01: b_eq_lm0_01_b <= not( b_eq_lm0_x(0) and b_eq_lm0_x(1) ); + ucmp_beqlm0_23: b_eq_lm0_23_b <= not( b_eq_lm0_x(2) and b_eq_lm0_x(3) ); + ucmp_beqlm0_45: b_eq_lm0_45_b <= not( b_eq_lm0_x(4) and b_eq_lm0_x(5) ); + ucmp_beqlm0_u: b_eq_lm0_u <= not( b_eq_lm0_01_b or b_eq_lm0_23_b ); + ucmp_beqlm0_w: b_eq_lm0_v <= not( b_eq_lm0_45_b ); + ucmp_beqlm0: b_eq_lm0_b <= not( b_eq_lm0_u and b_eq_lm0_v and lm0_b_cmp_en ); + + ucmp_beqlm1_x: b_eq_lm1_x(0 to 5) <= not( lm1_ta_buf(0 to 5) xor is1_frb_buf4(0 to 5) ); + ucmp_beqlm1_01: b_eq_lm1_01_b <= not( b_eq_lm1_x(0) and b_eq_lm1_x(1) ); + ucmp_beqlm1_23: b_eq_lm1_23_b <= not( b_eq_lm1_x(2) and b_eq_lm1_x(3) ); + ucmp_beqlm1_45: b_eq_lm1_45_b <= not( b_eq_lm1_x(4) and b_eq_lm1_x(5) ); + ucmp_beqlm1_u: b_eq_lm1_u <= not( b_eq_lm1_01_b or b_eq_lm1_23_b ); + ucmp_beqlm1_w: b_eq_lm1_v <= not( b_eq_lm1_45_b ); + ucmp_beqlm1: b_eq_lm1_b <= not( b_eq_lm1_u and b_eq_lm1_v and lm1_b_cmp_en ); + + ucmp_beqlm2_x: b_eq_lm2_x(0 to 5) <= not( lm2_ta_buf(0 to 5) xor is1_frb_buf4(0 to 5) ); + ucmp_beqlm2_01: b_eq_lm2_01_b <= not( b_eq_lm2_x(0) and b_eq_lm2_x(1) ); + ucmp_beqlm2_23: b_eq_lm2_23_b <= not( b_eq_lm2_x(2) and b_eq_lm2_x(3) ); + ucmp_beqlm2_45: b_eq_lm2_45_b <= not( b_eq_lm2_x(4) and b_eq_lm2_x(5) ); + ucmp_beqlm2_u: b_eq_lm2_u <= not( b_eq_lm2_01_b or b_eq_lm2_23_b ); + ucmp_beqlm2_w: b_eq_lm2_v <= not( b_eq_lm2_45_b ); + ucmp_beqlm2: b_eq_lm2_b <= not( b_eq_lm2_u and b_eq_lm2_v and lm2_b_cmp_en ); + + ucmp_beqlm3_x: b_eq_lm3_x(0 to 5) <= not( lm3_ta_buf(0 to 5) xor is1_frb_buf4(0 to 5) ); + ucmp_beqlm3_01: b_eq_lm3_01_b <= not( b_eq_lm3_x(0) and b_eq_lm3_x(1) ); + ucmp_beqlm3_23: b_eq_lm3_23_b <= not( b_eq_lm3_x(2) and b_eq_lm3_x(3) ); + ucmp_beqlm3_45: b_eq_lm3_45_b <= not( b_eq_lm3_x(4) and b_eq_lm3_x(5) ); + ucmp_beqlm3_u: b_eq_lm3_u <= not( b_eq_lm3_01_b or b_eq_lm3_23_b ); + ucmp_beqlm3_w: b_eq_lm3_v <= not( b_eq_lm3_45_b ); + ucmp_beqlm3: b_eq_lm3_b <= not( b_eq_lm3_u and b_eq_lm3_v and lm3_b_cmp_en ); + + ucmp_beqlm4_x: b_eq_lm4_x(0 to 5) <= not( lm4_ta_buf(0 to 5) xor is1_frb_buf5(0 to 5) ); + ucmp_beqlm4_01: b_eq_lm4_01_b <= not( b_eq_lm4_x(0) and b_eq_lm4_x(1) ); + ucmp_beqlm4_23: b_eq_lm4_23_b <= not( b_eq_lm4_x(2) and b_eq_lm4_x(3) ); + ucmp_beqlm4_45: b_eq_lm4_45_b <= not( b_eq_lm4_x(4) and b_eq_lm4_x(5) ); + ucmp_beqlm4_u: b_eq_lm4_u <= not( b_eq_lm4_01_b or b_eq_lm4_23_b ); + ucmp_beqlm4_w: b_eq_lm4_v <= not( b_eq_lm4_45_b ); + ucmp_beqlm4: b_eq_lm4_b <= not( b_eq_lm4_u and b_eq_lm4_v and lm4_b_cmp_en ); + + ucmp_beqlm5_x: b_eq_lm5_x(0 to 5) <= not( lm5_ta_buf(0 to 5) xor is1_frb_buf5(0 to 5) ); + ucmp_beqlm5_01: b_eq_lm5_01_b <= not( b_eq_lm5_x(0) and b_eq_lm5_x(1) ); + ucmp_beqlm5_23: b_eq_lm5_23_b <= not( b_eq_lm5_x(2) and b_eq_lm5_x(3) ); + ucmp_beqlm5_45: b_eq_lm5_45_b <= not( b_eq_lm5_x(4) and b_eq_lm5_x(5) ); + ucmp_beqlm5_u: b_eq_lm5_u <= not( b_eq_lm5_01_b or b_eq_lm5_23_b ); + ucmp_beqlm5_w: b_eq_lm5_v <= not( b_eq_lm5_45_b ); + ucmp_beqlm5: b_eq_lm5_b <= not( b_eq_lm5_u and b_eq_lm5_v and lm5_b_cmp_en ); + + ucmp_beqlm6_x: b_eq_lm6_x(0 to 5) <= not( lm6_ta_buf(0 to 5) xor is1_frb_buf6(0 to 5) ); + ucmp_beqlm6_01: b_eq_lm6_01_b <= not( b_eq_lm6_x(0) and b_eq_lm6_x(1) ); + ucmp_beqlm6_23: b_eq_lm6_23_b <= not( b_eq_lm6_x(2) and b_eq_lm6_x(3) ); + ucmp_beqlm6_45: b_eq_lm6_45_b <= not( b_eq_lm6_x(4) and b_eq_lm6_x(5) ); + ucmp_beqlm6_u: b_eq_lm6_u <= not( b_eq_lm6_01_b or b_eq_lm6_23_b ); + ucmp_beqlm6_w: b_eq_lm6_v <= not( b_eq_lm6_45_b ); + ucmp_beqlm6: b_eq_lm6_b <= not( b_eq_lm6_u and b_eq_lm6_v and lm6_b_cmp_en ); + + ucmp_beqlm7_x: b_eq_lm7_x(0 to 5) <= not( lm7_ta_buf(0 to 5) xor is1_frb_buf6(0 to 5) ); + ucmp_beqlm7_01: b_eq_lm7_01_b <= not( b_eq_lm7_x(0) and b_eq_lm7_x(1) ); + ucmp_beqlm7_23: b_eq_lm7_23_b <= not( b_eq_lm7_x(2) and b_eq_lm7_x(3) ); + ucmp_beqlm7_45: b_eq_lm7_45_b <= not( b_eq_lm7_x(4) and b_eq_lm7_x(5) ); + ucmp_beqlm7_u: b_eq_lm7_u <= not( b_eq_lm7_01_b or b_eq_lm7_23_b ); + ucmp_beqlm7_w: b_eq_lm7_v <= not( b_eq_lm7_45_b ); + ucmp_beqlm7: b_eq_lm7_b <= not( b_eq_lm7_u and b_eq_lm7_v and lm7_b_cmp_en ); + + + + + + + + + + + ucmp_ceqis2_x: c_eq_is2_x(0 to 5) <= not( is2_ta_buf(0 to 5) xor is1_frc_buf1(0 to 5) ); + ucmp_ceqis2_01: c_eq_is2_01_b <= not( c_eq_is2_x(0) and c_eq_is2_x(1) ); + ucmp_ceqis2_23: c_eq_is2_23_b <= not( c_eq_is2_x(2) and c_eq_is2_x(3) ); + ucmp_ceqis2_45: c_eq_is2_45_b <= not( c_eq_is2_x(4) and c_eq_is2_x(5) ); + ucmp_ceqis2_u: c_eq_is2_u <= not( c_eq_is2_01_b or c_eq_is2_23_b ); + ucmp_ceqis2_w: c_eq_is2_v <= not( c_eq_is2_45_b ); + ucmp_ceqis2: c_eq_is2_b <= not( c_eq_is2_u and c_eq_is2_v and is2_c_cmp_en ); + + ucmp_ceqrf0_x: c_eq_rf0_x(0 to 5) <= not( rf0_ta_buf(0 to 5) xor is1_frc_buf1(0 to 5) ); + ucmp_ceqrf0_01: c_eq_rf0_01_b <= not( c_eq_rf0_x(0) and c_eq_rf0_x(1) ); + ucmp_ceqrf0_23: c_eq_rf0_23_b <= not( c_eq_rf0_x(2) and c_eq_rf0_x(3) ); + ucmp_ceqrf0_45: c_eq_rf0_45_b <= not( c_eq_rf0_x(4) and c_eq_rf0_x(5) ); + ucmp_ceqrf0_u: c_eq_rf0_u <= not( c_eq_rf0_01_b or c_eq_rf0_23_b ); + ucmp_ceqrf0_w: c_eq_rf0_v <= not( c_eq_rf0_45_b ); + ucmp_ceqrf0: c_eq_rf0_b <= not( c_eq_rf0_u and c_eq_rf0_v and rf0_c_cmp_en ); + + ucmp_ceqrf1_x: c_eq_rf1_x(0 to 5) <= not( rf1_ta_buf(0 to 5) xor is1_frc_buf1(0 to 5) ); + ucmp_ceqrf1_01: c_eq_rf1_01_b <= not( c_eq_rf1_x(0) and c_eq_rf1_x(1) ); + ucmp_ceqrf1_23: c_eq_rf1_23_b <= not( c_eq_rf1_x(2) and c_eq_rf1_x(3) ); + ucmp_ceqrf1_45: c_eq_rf1_45_b <= not( c_eq_rf1_x(4) and c_eq_rf1_x(5) ); + ucmp_ceqrf1_u: c_eq_rf1_u <= not( c_eq_rf1_01_b or c_eq_rf1_23_b ); + ucmp_ceqrf1_w: c_eq_rf1_v <= not( c_eq_rf1_45_b ); + ucmp_ceqrf1: c_eq_rf1_b <= not( c_eq_rf1_u and c_eq_rf1_v and rf1_c_cmp_en ); + + ucmp_ceqex1_x: c_eq_ex1_x(0 to 5) <= not( ex1_ta_buf(0 to 5) xor is1_frc_buf2(0 to 5) ); + ucmp_ceqex1_01: c_eq_ex1_01_b <= not( c_eq_ex1_x(0) and c_eq_ex1_x(1) ); + ucmp_ceqex1_23: c_eq_ex1_23_b <= not( c_eq_ex1_x(2) and c_eq_ex1_x(3) ); + ucmp_ceqex1_45: c_eq_ex1_45_b <= not( c_eq_ex1_x(4) and c_eq_ex1_x(5) ); + ucmp_ceqex1_u: c_eq_ex1_u <= not( c_eq_ex1_01_b or c_eq_ex1_23_b ); + ucmp_ceqex1_w: c_eq_ex1_v <= not( c_eq_ex1_45_b ); + ucmp_ceqex1: c_eq_ex1_b <= not( c_eq_ex1_u and c_eq_ex1_v and ex1_c_cmp_en ); + + ucmp_ceqex2_x: c_eq_ex2_x(0 to 5) <= not( ex2_ta_buf(0 to 5) xor is1_frc_buf2(0 to 5) ); + ucmp_ceqex2_01: c_eq_ex2_01_b <= not( c_eq_ex2_x(0) and c_eq_ex2_x(1) ); + ucmp_ceqex2_23: c_eq_ex2_23_b <= not( c_eq_ex2_x(2) and c_eq_ex2_x(3) ); + ucmp_ceqex2_45: c_eq_ex2_45_b <= not( c_eq_ex2_x(4) and c_eq_ex2_x(5) ); + ucmp_ceqex2_u: c_eq_ex2_u <= not( c_eq_ex2_01_b or c_eq_ex2_23_b ); + ucmp_ceqex2_w: c_eq_ex2_v <= not( c_eq_ex2_45_b ); + ucmp_ceqex2: c_eq_ex2_b <= not( c_eq_ex2_u and c_eq_ex2_v and ex2_c_cmp_en ); + + ucmp_ceqex3_x: c_eq_ex3_x(0 to 5) <= not( ex3_ta_buf(0 to 5) xor is1_frc_buf2(0 to 5) ); + ucmp_ceqex3_01: c_eq_ex3_01_b <= not( c_eq_ex3_x(0) and c_eq_ex3_x(1) ); + ucmp_ceqex3_23: c_eq_ex3_23_b <= not( c_eq_ex3_x(2) and c_eq_ex3_x(3) ); + ucmp_ceqex3_45: c_eq_ex3_45_b <= not( c_eq_ex3_x(4) and c_eq_ex3_x(5) ); + ucmp_ceqex3_u: c_eq_ex3_u <= not( c_eq_ex3_01_b or c_eq_ex3_23_b ); + ucmp_ceqex3_w: c_eq_ex3_v <= not( c_eq_ex3_45_b ); + ucmp_ceqex3: c_eq_ex3_b <= not( c_eq_ex3_u and c_eq_ex3_v and ex3_c_cmp_en ); + + ucmp_ceqex4_x: c_eq_ex4_x(0 to 5) <= not( ex4_ta_buf(0 to 5) xor is1_frc_buf3(0 to 5) ); + ucmp_ceqex4_01: c_eq_ex4_01_b <= not( c_eq_ex4_x(0) and c_eq_ex4_x(1) ); + ucmp_ceqex4_23: c_eq_ex4_23_b <= not( c_eq_ex4_x(2) and c_eq_ex4_x(3) ); + ucmp_ceqex4_45: c_eq_ex4_45_b <= not( c_eq_ex4_x(4) and c_eq_ex4_x(5) ); + ucmp_ceqex4_u: c_eq_ex4_u <= not( c_eq_ex4_01_b or c_eq_ex4_23_b ); + ucmp_ceqex4_w: c_eq_ex4_v <= not( c_eq_ex4_45_b ); + ucmp_ceqex4: c_eq_ex4_b <= not( c_eq_ex4_u and c_eq_ex4_v and ex4_c_cmp_en ); + + ucmp_ceqlmx_x: c_eq_lmc_ex4_x(0 to 5) <= not( lmc_ex4_buf(0 to 5) xor is1_frc_buf3(0 to 5) ); + ucmp_ceqlmx_01: c_eq_lmc_ex4_01_b <= not( c_eq_lmc_ex4_x(0) and c_eq_lmc_ex4_x(1) ); + ucmp_ceqlmx_23: c_eq_lmc_ex4_23_b <= not( c_eq_lmc_ex4_x(2) and c_eq_lmc_ex4_x(3) ); + ucmp_ceqlmx_45: c_eq_lmc_ex4_45_b <= not( c_eq_lmc_ex4_x(4) and c_eq_lmc_ex4_x(5) ); + ucmp_ceqlmx_u: c_eq_lmc_ex4_u <= not( c_eq_lmc_ex4_01_b or c_eq_lmc_ex4_23_b ); + ucmp_ceqlmx_w: c_eq_lmc_ex4_v <= not( c_eq_lmc_ex4_45_b ); + ucmp_ceqlmx: c_eq_lmc_ex4_b <= not( c_eq_lmc_ex4_u and c_eq_lmc_ex4_v and lmc_ex4_c_cmp_en ); + + ucmp_ceqlm0_x: c_eq_lm0_x(0 to 5) <= not( lm0_ta_buf(0 to 5) xor is1_frc_buf3(0 to 5) ); + ucmp_ceqlm0_01: c_eq_lm0_01_b <= not( c_eq_lm0_x(0) and c_eq_lm0_x(1) ); + ucmp_ceqlm0_23: c_eq_lm0_23_b <= not( c_eq_lm0_x(2) and c_eq_lm0_x(3) ); + ucmp_ceqlm0_45: c_eq_lm0_45_b <= not( c_eq_lm0_x(4) and c_eq_lm0_x(5) ); + ucmp_ceqlm0_u: c_eq_lm0_u <= not( c_eq_lm0_01_b or c_eq_lm0_23_b ); + ucmp_ceqlm0_w: c_eq_lm0_v <= not( c_eq_lm0_45_b ); + ucmp_ceqlm0: c_eq_lm0_b <= not( c_eq_lm0_u and c_eq_lm0_v and lm0_c_cmp_en ); + + + ucmp_ceqlm1_x: c_eq_lm1_x(0 to 5) <= not( lm1_ta_buf(0 to 5) xor is1_frc_buf4(0 to 5) ); + ucmp_ceqlm1_01: c_eq_lm1_01_b <= not( c_eq_lm1_x(0) and c_eq_lm1_x(1) ); + ucmp_ceqlm1_23: c_eq_lm1_23_b <= not( c_eq_lm1_x(2) and c_eq_lm1_x(3) ); + ucmp_ceqlm1_45: c_eq_lm1_45_b <= not( c_eq_lm1_x(4) and c_eq_lm1_x(5) ); + ucmp_ceqlm1_u: c_eq_lm1_u <= not( c_eq_lm1_01_b or c_eq_lm1_23_b ); + ucmp_ceqlm1_w: c_eq_lm1_v <= not( c_eq_lm1_45_b ); + ucmp_ceqlm1: c_eq_lm1_b <= not( c_eq_lm1_u and c_eq_lm1_v and lm1_c_cmp_en ); + + ucmp_ceqlm2_x: c_eq_lm2_x(0 to 5) <= not( lm2_ta_buf(0 to 5) xor is1_frc_buf4(0 to 5) ); + ucmp_ceqlm2_01: c_eq_lm2_01_b <= not( c_eq_lm2_x(0) and c_eq_lm2_x(1) ); + ucmp_ceqlm2_23: c_eq_lm2_23_b <= not( c_eq_lm2_x(2) and c_eq_lm2_x(3) ); + ucmp_ceqlm2_45: c_eq_lm2_45_b <= not( c_eq_lm2_x(4) and c_eq_lm2_x(5) ); + ucmp_ceqlm2_u: c_eq_lm2_u <= not( c_eq_lm2_01_b or c_eq_lm2_23_b ); + ucmp_ceqlm2_w: c_eq_lm2_v <= not( c_eq_lm2_45_b ); + ucmp_ceqlm2: c_eq_lm2_b <= not( c_eq_lm2_u and c_eq_lm2_v and lm2_c_cmp_en ); + + ucmp_ceqlm3_x: c_eq_lm3_x(0 to 5) <= not( lm3_ta_buf(0 to 5) xor is1_frc_buf4(0 to 5) ); + ucmp_ceqlm3_01: c_eq_lm3_01_b <= not( c_eq_lm3_x(0) and c_eq_lm3_x(1) ); + ucmp_ceqlm3_23: c_eq_lm3_23_b <= not( c_eq_lm3_x(2) and c_eq_lm3_x(3) ); + ucmp_ceqlm3_45: c_eq_lm3_45_b <= not( c_eq_lm3_x(4) and c_eq_lm3_x(5) ); + ucmp_ceqlm3_u: c_eq_lm3_u <= not( c_eq_lm3_01_b or c_eq_lm3_23_b ); + ucmp_ceqlm3_w: c_eq_lm3_v <= not( c_eq_lm3_45_b ); + ucmp_ceqlm3: c_eq_lm3_b <= not( c_eq_lm3_u and c_eq_lm3_v and lm3_c_cmp_en ); + + ucmp_ceqlm4_x: c_eq_lm4_x(0 to 5) <= not( lm4_ta_buf(0 to 5) xor is1_frc_buf5(0 to 5) ); + ucmp_ceqlm4_01: c_eq_lm4_01_b <= not( c_eq_lm4_x(0) and c_eq_lm4_x(1) ); + ucmp_ceqlm4_23: c_eq_lm4_23_b <= not( c_eq_lm4_x(2) and c_eq_lm4_x(3) ); + ucmp_ceqlm4_45: c_eq_lm4_45_b <= not( c_eq_lm4_x(4) and c_eq_lm4_x(5) ); + ucmp_ceqlm4_u: c_eq_lm4_u <= not( c_eq_lm4_01_b or c_eq_lm4_23_b ); + ucmp_ceqlm4_w: c_eq_lm4_v <= not( c_eq_lm4_45_b ); + ucmp_ceqlm4: c_eq_lm4_b <= not( c_eq_lm4_u and c_eq_lm4_v and lm4_c_cmp_en ); + + ucmp_ceqlm5_x: c_eq_lm5_x(0 to 5) <= not( lm5_ta_buf(0 to 5) xor is1_frc_buf5(0 to 5) ); + ucmp_ceqlm5_01: c_eq_lm5_01_b <= not( c_eq_lm5_x(0) and c_eq_lm5_x(1) ); + ucmp_ceqlm5_23: c_eq_lm5_23_b <= not( c_eq_lm5_x(2) and c_eq_lm5_x(3) ); + ucmp_ceqlm5_45: c_eq_lm5_45_b <= not( c_eq_lm5_x(4) and c_eq_lm5_x(5) ); + ucmp_ceqlm5_u: c_eq_lm5_u <= not( c_eq_lm5_01_b or c_eq_lm5_23_b ); + ucmp_ceqlm5_w: c_eq_lm5_v <= not( c_eq_lm5_45_b ); + ucmp_ceqlm5: c_eq_lm5_b <= not( c_eq_lm5_u and c_eq_lm5_v and lm5_c_cmp_en ); + + ucmp_ceqlm6_x: c_eq_lm6_x(0 to 5) <= not( lm6_ta_buf(0 to 5) xor is1_frc_buf6(0 to 5) ); + ucmp_ceqlm6_01: c_eq_lm6_01_b <= not( c_eq_lm6_x(0) and c_eq_lm6_x(1) ); + ucmp_ceqlm6_23: c_eq_lm6_23_b <= not( c_eq_lm6_x(2) and c_eq_lm6_x(3) ); + ucmp_ceqlm6_45: c_eq_lm6_45_b <= not( c_eq_lm6_x(4) and c_eq_lm6_x(5) ); + ucmp_ceqlm6_u: c_eq_lm6_u <= not( c_eq_lm6_01_b or c_eq_lm6_23_b ); + ucmp_ceqlm6_w: c_eq_lm6_v <= not( c_eq_lm6_45_b ); + ucmp_ceqlm6: c_eq_lm6_b <= not( c_eq_lm6_u and c_eq_lm6_v and lm6_c_cmp_en ); + + ucmp_ceqlm7_x: c_eq_lm7_x(0 to 5) <= not( lm7_ta_buf(0 to 5) xor is1_frc_buf6(0 to 5) ); + ucmp_ceqlm7_01: c_eq_lm7_01_b <= not( c_eq_lm7_x(0) and c_eq_lm7_x(1) ); + ucmp_ceqlm7_23: c_eq_lm7_23_b <= not( c_eq_lm7_x(2) and c_eq_lm7_x(3) ); + ucmp_ceqlm7_45: c_eq_lm7_45_b <= not( c_eq_lm7_x(4) and c_eq_lm7_x(5) ); + ucmp_ceqlm7_u: c_eq_lm7_u <= not( c_eq_lm7_01_b or c_eq_lm7_23_b ); + ucmp_ceqlm7_w: c_eq_lm7_v <= not( c_eq_lm7_45_b ); + ucmp_ceqlm7: c_eq_lm7_b <= not( c_eq_lm7_u and c_eq_lm7_v and lm7_c_cmp_en ); + + + + + + ucmp_teqlm0_x: t_eq_lm0_x(0 to 5) <= not( lm0_ta_buf(0 to 5) xor is1_frt_buf1(0 to 5) ); + ucmp_teqlm0_01: t_eq_lm0_01_b <= not( t_eq_lm0_x(0) and t_eq_lm0_x(1) ); + ucmp_teqlm0_23: t_eq_lm0_23_b <= not( t_eq_lm0_x(2) and t_eq_lm0_x(3) ); + ucmp_teqlm0_45: t_eq_lm0_45_b <= not( t_eq_lm0_x(4) and t_eq_lm0_x(5) ); + ucmp_teqlm0_u: t_eq_lm0_u <= not( t_eq_lm0_01_b or t_eq_lm0_23_b ); + ucmp_teqlm0_w: t_eq_lm0_v <= not( t_eq_lm0_45_b ); + ucmp_teqlm0: t_eq_lm0_b <= not( t_eq_lm0_u and t_eq_lm0_v and lm0_t_cmp_en ); + + + ucmp_teqlm1_x: t_eq_lm1_x(0 to 5) <= not( lm1_ta_buf(0 to 5) xor is1_frt_buf1(0 to 5) ); + ucmp_teqlm1_01: t_eq_lm1_01_b <= not( t_eq_lm1_x(0) and t_eq_lm1_x(1) ); + ucmp_teqlm1_23: t_eq_lm1_23_b <= not( t_eq_lm1_x(2) and t_eq_lm1_x(3) ); + ucmp_teqlm1_45: t_eq_lm1_45_b <= not( t_eq_lm1_x(4) and t_eq_lm1_x(5) ); + ucmp_teqlm1_u: t_eq_lm1_u <= not( t_eq_lm1_01_b or t_eq_lm1_23_b ); + ucmp_teqlm1_w: t_eq_lm1_v <= not( t_eq_lm1_45_b ); + ucmp_teqlm1: t_eq_lm1_b <= not( t_eq_lm1_u and t_eq_lm1_v and lm1_t_cmp_en ); + + ucmp_teqlm2_x: t_eq_lm2_x(0 to 5) <= not( lm2_ta_buf(0 to 5) xor is1_frt_buf2(0 to 5) ); + ucmp_teqlm2_01: t_eq_lm2_01_b <= not( t_eq_lm2_x(0) and t_eq_lm2_x(1) ); + ucmp_teqlm2_23: t_eq_lm2_23_b <= not( t_eq_lm2_x(2) and t_eq_lm2_x(3) ); + ucmp_teqlm2_45: t_eq_lm2_45_b <= not( t_eq_lm2_x(4) and t_eq_lm2_x(5) ); + ucmp_teqlm2_u: t_eq_lm2_u <= not( t_eq_lm2_01_b or t_eq_lm2_23_b ); + ucmp_teqlm2_w: t_eq_lm2_v <= not( t_eq_lm2_45_b ); + ucmp_teqlm2: t_eq_lm2_b <= not( t_eq_lm2_u and t_eq_lm2_v and lm2_t_cmp_en ); + + ucmp_teqlm3_x: t_eq_lm3_x(0 to 5) <= not( lm3_ta_buf(0 to 5) xor is1_frt_buf3(0 to 5) ); + ucmp_teqlm3_01: t_eq_lm3_01_b <= not( t_eq_lm3_x(0) and t_eq_lm3_x(1) ); + ucmp_teqlm3_23: t_eq_lm3_23_b <= not( t_eq_lm3_x(2) and t_eq_lm3_x(3) ); + ucmp_teqlm3_45: t_eq_lm3_45_b <= not( t_eq_lm3_x(4) and t_eq_lm3_x(5) ); + ucmp_teqlm3_u: t_eq_lm3_u <= not( t_eq_lm3_01_b or t_eq_lm3_23_b ); + ucmp_teqlm3_w: t_eq_lm3_v <= not( t_eq_lm3_45_b ); + ucmp_teqlm3: t_eq_lm3_b <= not( t_eq_lm3_u and t_eq_lm3_v and lm3_t_cmp_en ); + + ucmp_teqlm4_x: t_eq_lm4_x(0 to 5) <= not( lm4_ta_buf(0 to 5) xor is1_frt_buf4(0 to 5) ); + ucmp_teqlm4_01: t_eq_lm4_01_b <= not( t_eq_lm4_x(0) and t_eq_lm4_x(1) ); + ucmp_teqlm4_23: t_eq_lm4_23_b <= not( t_eq_lm4_x(2) and t_eq_lm4_x(3) ); + ucmp_teqlm4_45: t_eq_lm4_45_b <= not( t_eq_lm4_x(4) and t_eq_lm4_x(5) ); + ucmp_teqlm4_u: t_eq_lm4_u <= not( t_eq_lm4_01_b or t_eq_lm4_23_b ); + ucmp_teqlm4_w: t_eq_lm4_v <= not( t_eq_lm4_45_b ); + ucmp_teqlm4: t_eq_lm4_b <= not( t_eq_lm4_u and t_eq_lm4_v and lm4_t_cmp_en ); + + ucmp_teqlm5_x: t_eq_lm5_x(0 to 5) <= not( lm5_ta_buf(0 to 5) xor is1_frt_buf5(0 to 5) ); + ucmp_teqlm5_01: t_eq_lm5_01_b <= not( t_eq_lm5_x(0) and t_eq_lm5_x(1) ); + ucmp_teqlm5_23: t_eq_lm5_23_b <= not( t_eq_lm5_x(2) and t_eq_lm5_x(3) ); + ucmp_teqlm5_45: t_eq_lm5_45_b <= not( t_eq_lm5_x(4) and t_eq_lm5_x(5) ); + ucmp_teqlm5_u: t_eq_lm5_u <= not( t_eq_lm5_01_b or t_eq_lm5_23_b ); + ucmp_teqlm5_w: t_eq_lm5_v <= not( t_eq_lm5_45_b ); + ucmp_teqlm5: t_eq_lm5_b <= not( t_eq_lm5_u and t_eq_lm5_v and lm5_t_cmp_en ); + + ucmp_teqlm6_x: t_eq_lm6_x(0 to 5) <= not( lm6_ta_buf(0 to 5) xor is1_frt_buf6(0 to 5) ); + ucmp_teqlm6_01: t_eq_lm6_01_b <= not( t_eq_lm6_x(0) and t_eq_lm6_x(1) ); + ucmp_teqlm6_23: t_eq_lm6_23_b <= not( t_eq_lm6_x(2) and t_eq_lm6_x(3) ); + ucmp_teqlm6_45: t_eq_lm6_45_b <= not( t_eq_lm6_x(4) and t_eq_lm6_x(5) ); + ucmp_teqlm6_u: t_eq_lm6_u <= not( t_eq_lm6_01_b or t_eq_lm6_23_b ); + ucmp_teqlm6_w: t_eq_lm6_v <= not( t_eq_lm6_45_b ); + ucmp_teqlm6: t_eq_lm6_b <= not( t_eq_lm6_u and t_eq_lm6_v and lm6_t_cmp_en ); + + ucmp_teqlm7_x: t_eq_lm7_x(0 to 5) <= not( lm7_ta_buf(0 to 5) xor is1_frt_buf6(0 to 5) ); + ucmp_teqlm7_01: t_eq_lm7_01_b <= not( t_eq_lm7_x(0) and t_eq_lm7_x(1) ); + ucmp_teqlm7_23: t_eq_lm7_23_b <= not( t_eq_lm7_x(2) and t_eq_lm7_x(3) ); + ucmp_teqlm7_45: t_eq_lm7_45_b <= not( t_eq_lm7_x(4) and t_eq_lm7_x(5) ); + ucmp_teqlm7_u: t_eq_lm7_u <= not( t_eq_lm7_01_b or t_eq_lm7_23_b ); + ucmp_teqlm7_w: t_eq_lm7_v <= not( t_eq_lm7_45_b ); + ucmp_teqlm7: t_eq_lm7_b <= not( t_eq_lm7_u and t_eq_lm7_v and lm7_t_cmp_en ); + + + + + + + + + ucmp_aor11: a_or_1_1 <= not( a_eq_lm0_b and a_eq_lm1_b ); + ucmp_aor12: a_or_1_2 <= not( a_eq_lm2_b and a_eq_lm3_b ); + ucmp_aor13: a_or_1_3 <= not( a_eq_lm4_b and a_eq_lm5_b ); + ucmp_aor14: a_or_1_4 <= not( a_eq_lm6_b and a_eq_lm7_b ); + ucmp_aor15: a_or_1_5 <= not( a_eq_lmc_ex4_b and a_eq_ex4_b ); + ucmp_aor16: a_or_1_6 <= not( a_eq_ex3_b and a_eq_ex2_b ); + ucmp_aor17: a_or_1_7 <= not( a_eq_ex1_b and a_eq_rf1_b ); + ucmp_aor18: a_or_1_8 <= not( a_eq_rf0_b and a_eq_is2_b ); + + ucmp_aor21: a_or_2_1_b <= not( a_or_1_1 or a_or_1_2 ); + ucmp_aor22: a_or_2_2_b <= not( a_or_1_3 or a_or_1_4 ); + ucmp_aor23: a_or_2_3_b <= not( a_or_1_5 or a_or_1_6 ); + ucmp_aor24: a_or_2_4_b <= not( a_or_1_7 or a_or_1_8 ); + + ucmp_aor31: a_or_3_1 <= not( a_or_2_1_b and a_or_2_2_b ); + ucmp_aor32: a_or_3_2 <= not( a_or_2_3_b and a_or_2_4_b ); + + ucmp_aor4: a_or_4_b <= not( a_group_en and (a_or_3_1 or a_or_3_2) ); + + + + ucmp_bor11: b_or_1_1 <= not( b_eq_lm0_b and b_eq_lm1_b ); + ucmp_bor12: b_or_1_2 <= not( b_eq_lm2_b and b_eq_lm3_b ); + ucmp_bor13: b_or_1_3 <= not( b_eq_lm4_b and b_eq_lm5_b ); + ucmp_bor14: b_or_1_4 <= not( b_eq_lm6_b and b_eq_lm7_b ); + ucmp_bor15: b_or_1_5 <= not( b_eq_lmc_ex4_b and b_eq_ex4_b ); + ucmp_bor16: b_or_1_6 <= not( b_eq_ex3_b and b_eq_ex2_b ); + ucmp_bor17: b_or_1_7 <= not( b_eq_ex1_b and b_eq_rf1_b ); + ucmp_bor18: b_or_1_8 <= not( b_eq_rf0_b and b_eq_is2_b ); + + ucmp_bor21: b_or_2_1_b <= not( b_or_1_1 or b_or_1_2 ); + ucmp_bor22: b_or_2_2_b <= not( b_or_1_3 or b_or_1_4 ); + ucmp_bor23: b_or_2_3_b <= not( b_or_1_5 or b_or_1_6 ); + ucmp_bor24: b_or_2_4_b <= not( b_or_1_7 or b_or_1_8 ); + + ucmp_bor31: b_or_3_1 <= not( b_or_2_1_b and b_or_2_2_b ); + ucmp_bor32: b_or_3_2 <= not( b_or_2_3_b and b_or_2_4_b ); + + ucmp_bor4: b_or_4_b <= not( b_group_en and (b_or_3_1 or b_or_3_2) ); + + + ucmp_uor15: u_or_1_5 <= not( u_eq_ex4_b ); + ucmp_uor16: u_or_1_6 <= not( u_eq_ex3_b and u_eq_ex2_b ); + ucmp_uor17: u_or_1_7 <= not( u_eq_ex1_b and u_eq_rf1_b ); + ucmp_uor18: u_or_1_8 <= not( u_eq_rf0_b and u_eq_is2_b ); + + ucmp_uor23: u_or_2_3_b <= not( u_or_1_5 or u_or_1_6 ); + ucmp_uor24: u_or_2_4_b <= not( u_or_1_7 or u_or_1_8 ); + + ucmp_uor31: u_or_3_1 <= not( u_or_2_3_b and u_or_2_4_b ); + + ucmp_uor4: u_or_4_b <= not( u_or_3_1 and u_group_en); + + + ucmp_cor11: c_or_1_1 <= not( c_eq_lm0_b and c_eq_lm1_b ); + ucmp_cor12: c_or_1_2 <= not( c_eq_lm2_b and c_eq_lm3_b ); + ucmp_cor13: c_or_1_3 <= not( c_eq_lm4_b and c_eq_lm5_b ); + ucmp_cor14: c_or_1_4 <= not( c_eq_lm6_b and c_eq_lm7_b ); + ucmp_cor15: c_or_1_5 <= not( c_eq_lmc_ex4_b and c_eq_ex4_b ); + ucmp_cor16: c_or_1_6 <= not( c_eq_ex3_b and c_eq_ex2_b ); + ucmp_cor17: c_or_1_7 <= not( c_eq_ex1_b and c_eq_rf1_b ); + ucmp_cor18: c_or_1_8 <= not( c_eq_rf0_b and c_eq_is2_b ); + + ucmp_cor21: c_or_2_1_b <= not( c_or_1_1 or c_or_1_2 ); + ucmp_cor22: c_or_2_2_b <= not( c_or_1_3 or c_or_1_4 ); + ucmp_cor23: c_or_2_3_b <= not( c_or_1_5 or c_or_1_6 ); + ucmp_cor24: c_or_2_4_b <= not( c_or_1_7 or c_or_1_8 ); + + ucmp_cor31: c_or_3_1 <= not( c_or_2_1_b and c_or_2_2_b ); + ucmp_cor32: c_or_3_2 <= not( c_or_2_3_b and c_or_2_4_b ); + + ucmp_cor4: c_or_4_b <= not( c_group_en and (c_or_3_1 or c_or_3_2) ); + + + ucmp_tor11: t_or_1_1 <= not( t_eq_lm0_b and t_eq_lm1_b ); + ucmp_tor12: t_or_1_2 <= not( t_eq_lm2_b and t_eq_lm3_b ); + ucmp_tor13: t_or_1_3 <= not( t_eq_lm4_b and t_eq_lm5_b ); + ucmp_tor14: t_or_1_4 <= not( t_eq_lm6_b and t_eq_lm7_b ); + + + ucmp_tor21: t_or_2_1_b <= not( t_or_1_1 or t_or_1_2 ); + ucmp_tor22: t_or_2_2_b <= not( t_or_1_3 or t_or_1_4 ); + + + ucmp_tor31: t_or_3_1 <= not( t_or_2_1_b and t_or_2_2_b ); + + + ucmp_tor4: t_or_4_b <= not( t_group_en and t_or_3_1 ); + + + +lm0_valid <= lm_v(0); +lm1_valid <= lm_v(1); +lm2_valid <= lm_v(2); +lm3_valid <= lm_v(3); +lm4_valid <= lm_v(4); +lm5_valid <= lm_v(5); +lm6_valid <= lm_v(6); +lm7_valid <= lm_v(7); + + + + lm0_a_cmp_en <= lm0_valid ; + lm0_b_cmp_en <= lm0_valid ; + lm0_c_cmp_en <= lm0_valid ; + lm0_t_cmp_en <= lm0_valid ; + + lm1_a_cmp_en <= lm1_valid ; + lm1_b_cmp_en <= lm1_valid ; + lm1_c_cmp_en <= lm1_valid ; + lm1_t_cmp_en <= lm1_valid ; + + lm2_a_cmp_en <= lm2_valid ; + lm2_b_cmp_en <= lm2_valid ; + lm2_c_cmp_en <= lm2_valid ; + lm2_t_cmp_en <= lm2_valid ; + + lm3_a_cmp_en <= lm3_valid ; + lm3_b_cmp_en <= lm3_valid ; + lm3_c_cmp_en <= lm3_valid ; + lm3_t_cmp_en <= lm3_valid ; + + lm4_a_cmp_en <= lm4_valid ; + lm4_b_cmp_en <= lm4_valid ; + lm4_c_cmp_en <= lm4_valid ; + lm4_t_cmp_en <= lm4_valid ; + + lm5_a_cmp_en <= lm5_valid ; + lm5_b_cmp_en <= lm5_valid ; + lm5_c_cmp_en <= lm5_valid ; + lm5_t_cmp_en <= lm5_valid ; + + lm6_a_cmp_en <= lm6_valid ; + lm6_b_cmp_en <= lm6_valid ; + lm6_c_cmp_en <= lm6_valid ; + lm6_t_cmp_en <= lm6_valid ; + + lm7_a_cmp_en <= lm7_valid ; + lm7_b_cmp_en <= lm7_valid ; + lm7_c_cmp_en <= lm7_valid ; + lm7_t_cmp_en <= lm7_valid ; + + lmc_ex4_a_cmp_en <= lmc_ex4_v; + lmc_ex4_b_cmp_en <= lmc_ex4_v; + lmc_ex4_c_cmp_en <= lmc_ex4_v; + + is2_a_cmp_en <= is2_frt_v ; + is2_b_cmp_en <= is2_frt_v ; + is2_c_cmp_en <= is2_frt_v ; + + rf0_a_cmp_en <= rf0_frt_v ; + rf0_b_cmp_en <= rf0_frt_v ; + rf0_c_cmp_en <= rf0_frt_v ; + + rf1_a_cmp_en <= rf1_frt_v ; + rf1_b_cmp_en <= rf1_frt_v ; + rf1_c_cmp_en <= rf1_frt_v ; + + ex1_a_cmp_en <= ex1_frt_v ; + ex1_b_cmp_en <= ex1_frt_v ; + ex1_c_cmp_en <= ex1_frt_v ; + + ex2_a_cmp_en <= ex2_frt_v ; + ex2_b_cmp_en <= ex2_frt_v ; + ex2_c_cmp_en <= ex2_frt_v ; + + ex3_a_cmp_en <= ex3_frt_v and (dis_byp_is1 or is1_store_v or ex3_ld_v) ; + ex3_b_cmp_en <= ex3_frt_v and (dis_byp_is1 or is1_store_v or ex3_ld_v) ; + ex3_c_cmp_en <= ex3_frt_v and (dis_byp_is1 or ex3_ld_v) ; + + ex4_a_cmp_en <= ex4_frt_v and (dis_byp_is1 or (is1_store_v and ex4_ld_v)); + ex4_b_cmp_en <= ex4_frt_v and (dis_byp_is1 or (is1_store_v and ex4_ld_v)); + ex4_c_cmp_en <= ex4_frt_v and dis_byp_is1 ; + + + is2_u_cmp_en <= is2_frt_v ; + rf0_u_cmp_en <= rf0_frt_v ; + rf1_u_cmp_en <= rf1_frt_v ; + ex1_u_cmp_en <= ex1_frt_v ; + ex2_u_cmp_en <= ex2_frt_v ; + ex3_u_cmp_en <= ex3_frt_v ; + ex4_u_cmp_en <= ex4_frt_v ; + + + a_group_en <= is1_fra_v and is1_instr_v ; + c_group_en <= is1_frc_v and is1_instr_v ; + b_group_en <= is1_frb_v and is1_instr_v ; + u_group_en <= uc_end_is1 and is1_instr_v ; + t_group_en <= is1_frt_v and is1_instr_v ; + + + raw_fra_hit_b <= a_or_4_b; + raw_frb_hit_b <= b_or_4_b; + raw_frc_hit_b <= c_or_4_b; + + raw_frb_uc_hit_b <= u_or_4_b; + is1_lmq_waw_hit_b <= t_or_4_b; + + +end iuq_axu_fu_dep_cmp; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_axu_fu_iss.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_axu_fu_iss.vhdl new file mode 100644 index 0000000..5a88d8e --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_axu_fu_iss.vhdl @@ -0,0 +1,1256 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + use work.iuq_pkg.all; + + + +entity iuq_axu_fu_iss is +generic( + expand_type : integer := 2; + fpr_addr_width : integer := 5; + needs_sreset : integer := 1); +port( + nclk : in clk_logic; + vdd : inout power_logic; + gnd : inout power_logic; + iu_au_is1_flush : in std_ulogic_vector(0 to 3); + xu_iu_is2_flush : in std_ulogic_vector(0 to 3); + uc_flush : in std_ulogic_vector(0 to 3); + i_iss_si : in std_ulogic; + i_iss_so : out std_ulogic; + an_ac_scan_dis_dc_b : in std_ulogic; + pc_iu_func_sl_thold_2 : in std_ulogic; + pc_iu_sg_2 : in std_ulogic; + mpw1_b : in std_ulogic; + + clkoff_b :in std_ulogic; + + tc_ac_ccflush_dc :in std_ulogic; + delay_lclkr : in std_ulogic; + + i_axu_is2_instr_match_t0 : in std_ulogic; + i_axu_is2_instr_match_t1 : in std_ulogic; + i_axu_is2_instr_match_t2 : in std_ulogic; + i_axu_is2_instr_match_t3 : in std_ulogic; + + i_afd_is2_is_ucode_t0 : in std_ulogic; + i_afd_is2_is_ucode_t1 : in std_ulogic; + i_afd_is2_is_ucode_t2 : in std_ulogic; + i_afd_is2_is_ucode_t3 : in std_ulogic; + + i_afd_is2_t0_instr_v : in std_ulogic; + i_afd_is2_t1_instr_v : in std_ulogic; + i_afd_is2_t2_instr_v : in std_ulogic; + i_afd_is2_t3_instr_v : in std_ulogic; + + i_afd_is2_t0_instr : in std_ulogic_vector(0 to 31); + i_afd_is2_t1_instr : in std_ulogic_vector(0 to 31); + i_afd_is2_t2_instr : in std_ulogic_vector(0 to 31); + i_afd_is2_t3_instr : in std_ulogic_vector(0 to 31); + + i_afd_is2_fra_t0 : in std_ulogic_vector(0 to 6); + i_afd_is2_fra_t1 : in std_ulogic_vector(0 to 6); + i_afd_is2_fra_t2 : in std_ulogic_vector(0 to 6); + i_afd_is2_fra_t3 : in std_ulogic_vector(0 to 6); + + i_afd_is2_frb_t0 : in std_ulogic_vector(0 to 6); + i_afd_is2_frb_t1 : in std_ulogic_vector(0 to 6); + i_afd_is2_frb_t2 : in std_ulogic_vector(0 to 6); + i_afd_is2_frb_t3 : in std_ulogic_vector(0 to 6); + + i_afd_is2_frc_t0 : in std_ulogic_vector(0 to 6); + i_afd_is2_frc_t1 : in std_ulogic_vector(0 to 6); + i_afd_is2_frc_t2 : in std_ulogic_vector(0 to 6); + i_afd_is2_frc_t3 : in std_ulogic_vector(0 to 6); + + i_afd_is2_frt_t0 : in std_ulogic_vector(0 to 6); + i_afd_is2_frt_t1 : in std_ulogic_vector(0 to 6); + i_afd_is2_frt_t2 : in std_ulogic_vector(0 to 6); + i_afd_is2_frt_t3 : in std_ulogic_vector(0 to 6); + + i_afd_is2_fra_v_t0 : in std_ulogic; + i_afd_is2_fra_v_t1 : in std_ulogic; + i_afd_is2_fra_v_t2 : in std_ulogic; + i_afd_is2_fra_v_t3 : in std_ulogic; + + i_afd_is2_frb_v_t0 : in std_ulogic; + i_afd_is2_frb_v_t1 : in std_ulogic; + i_afd_is2_frb_v_t2 : in std_ulogic; + i_afd_is2_frb_v_t3 : in std_ulogic; + + i_afd_is2_frc_v_t0 : in std_ulogic; + i_afd_is2_frc_v_t1 : in std_ulogic; + i_afd_is2_frc_v_t2 : in std_ulogic; + i_afd_is2_frc_v_t3 : in std_ulogic; + + i_afd_is2_bypsel_t0 : in std_ulogic_vector(0 to 5); + i_afd_is2_bypsel_t1 : in std_ulogic_vector(0 to 5); + i_afd_is2_bypsel_t2 : in std_ulogic_vector(0 to 5); + i_afd_is2_bypsel_t3 : in std_ulogic_vector(0 to 5); + + i_afd_is2_ifar_t0 : in EFF_IFAR; + i_afd_is2_ifar_t1 : in EFF_IFAR; + i_afd_is2_ifar_t2 : in EFF_IFAR; + i_afd_is2_ifar_t3 : in EFF_IFAR; + + + i_axu_is1_dep_hit_t0_b : in std_ulogic; + i_axu_is1_dep_hit_t1_b : in std_ulogic; + i_axu_is1_dep_hit_t2_b : in std_ulogic; + i_axu_is1_dep_hit_t3_b : in std_ulogic; + + i_axu_is1_early_v_t0 : in std_ulogic; + i_axu_is1_early_v_t1 : in std_ulogic; + i_axu_is1_early_v_t2 : in std_ulogic; + i_axu_is1_early_v_t3 : in std_ulogic; + + ifdp_is2_est_bubble3_t0 : in std_ulogic; + ifdp_is2_est_bubble3_t1 : in std_ulogic; + ifdp_is2_est_bubble3_t2 : in std_ulogic; + ifdp_is2_est_bubble3_t3 : in std_ulogic; + + iu_au_md_pri_mask : in std_ulogic_vector(0 to 3); + iu_au_hi_pri_mask : in std_ulogic_vector(0 to 3); + + spr_fiss_pri_rand : in std_ulogic_vector(0 to 4); + spr_fiss_pri_rand_always : in std_ulogic; + spr_fiss_pri_rand_flush : in std_ulogic; + + iu_is2_take_t : out std_ulogic_vector(0 to 3); + iu_fu_is2_tid_decode : out std_ulogic_vector(0 to 3); + iu_fu_rf0_instr_match : out std_ulogic; + iu_fu_rf0_instr : out std_ulogic_vector(0 to 31); + iu_fu_rf0_instr_v : out std_ulogic; + iu_fu_rf0_is_ucode : out std_ulogic; + + iu_fu_rf0_fra : out std_ulogic_vector(0 to 6); + iu_fu_rf0_frb : out std_ulogic_vector(0 to 6); + iu_fu_rf0_frc : out std_ulogic_vector(0 to 6); + iu_fu_rf0_frt : out std_ulogic_vector(0 to 6); + + iu_fu_rf0_fra_v : out std_ulogic; + iu_fu_rf0_frb_v : out std_ulogic; + iu_fu_rf0_frc_v : out std_ulogic; + + iu_fu_rf0_ucfmul : out std_ulogic; + + + + i_afd_ignore_flush_is2_t0 : in std_ulogic; + i_afd_ignore_flush_is2_t1 : in std_ulogic; + i_afd_ignore_flush_is2_t2 : in std_ulogic; + i_afd_ignore_flush_is2_t3 : in std_ulogic; + + i_afd_config_iucr_t0 : in std_ulogic_vector(2 to 4); + i_afd_config_iucr_t1 : in std_ulogic_vector(2 to 4); + i_afd_config_iucr_t2 : in std_ulogic_vector(2 to 4); + i_afd_config_iucr_t3 : in std_ulogic_vector(2 to 4); + + i_afd_in_ucode_mode_or1d_b_t0 : in std_ulogic; + i_afd_in_ucode_mode_or1d_b_t1 : in std_ulogic; + i_afd_in_ucode_mode_or1d_b_t2 : in std_ulogic; + i_afd_in_ucode_mode_or1d_b_t3 : in std_ulogic; + + fu_iss_debug : out std_ulogic_vector(0 to 23); + + iu_fu_rf0_tid : out std_ulogic_vector(0 to 1); + + iu_fu_rf0_bypsel : out std_ulogic_vector(0 to 5); + + iu_fu_rf0_ifar : out EFF_IFAR + +); + + -- synopsys translate_off + + + + + + -- synopsys translate_on + +end iuq_axu_fu_iss; + + +architecture iuq_axu_fu_iss of iuq_axu_fu_iss is +signal act_dis : std_ulogic; +signal d_mode : std_ulogic; +signal mpw2_b : std_ulogic; + +signal tidn : std_ulogic; +signal tiup : std_ulogic; + +signal is2_issue_sel : std_ulogic_vector(0 to 3); + +signal is2_issue_sel_buf1_b : std_ulogic_vector(0 to 3); +signal is2_issue_sel_buf2 : std_ulogic_vector(0 to 3); +signal is2_issue_sel_buf3_b : std_ulogic_vector(0 to 3); +signal is2_issue_sel_buf4 : std_ulogic_vector(0 to 3); + + +signal rf0_wpc_sp_latch_scout : std_ulogic_vector(0 to 4); +signal rf0_wpc_sp_latch_scin : std_ulogic_vector(0 to 4); + +signal debug_reg_scin : std_ulogic_vector(0 to 4); +signal debug_reg_scout : std_ulogic_vector(0 to 4); + +signal hi_n230, hi_n231, hi_n232 : std_ulogic; +signal hi_n220, hi_n221, hi_n210 : std_ulogic; +signal md_n230, md_n231, md_n232 : std_ulogic; +signal md_n220, md_n221, md_n210 : std_ulogic; + + +signal medpri_v, medpri_v_b, highpri_v, highpri_v_b : std_ulogic_vector(0 to 3); + +signal is2_bubble_latch_scin: std_ulogic_vector(0 to 2); +signal is2_bubble_latch_scout: std_ulogic_vector(0 to 2); +signal is2_skip_latch_scin: std_ulogic_vector(0 to 3); +signal is2_skip_latch_scout: std_ulogic_vector(0 to 3); + + + + +signal rf0_stage_latch_scin : std_ulogic_vector(0 to 76+EFF_IFAR'length); +signal rf0_stage_latch_scout : std_ulogic_vector(0 to 76+EFF_IFAR'length); + + +signal spare_unused : std_ulogic_vector(00 to 10); +signal spare_l2 : std_ulogic_vector(00 to 6); + + + +signal skip_b :std_ulogic_vector(0 to 3); + +signal is2_insert_one_bubble, is2_insert_two_bubbles, is2_insert_three_bubbles, is2_insert_seven_bubbles :std_ulogic; +signal single_step_mode, single_step_divsqrt_mode, divsqrt_mode :std_ulogic; + +signal bubble_din, bubble_dout : std_ulogic_vector(2 to 4); +signal skip_din, skip_dout : std_ulogic_vector(0 to 3); + +signal hi_mask_v_b, md_mask_v_b: std_ulogic_vector(0 to 3); +signal hi_mask_v, md_mask_v: std_ulogic_vector(0 to 3); + +signal is2_v_t : std_ulogic_vector(0 to 3); + +signal iu_fu_is2_instr_match : std_ulogic; +signal iu_fu_is2_instr : std_ulogic_vector(0 to 31); +signal iu_fu_is2_instr_v : std_ulogic; +signal is2_instr_v, disable_cgat : std_ulogic; +signal is2_act_din, is2_act_l2, is2_act : std_ulogic; + +signal iu_fu_is2_fra : std_ulogic_vector(0 to 6); +signal iu_fu_is2_frb : std_ulogic_vector(0 to 6); +signal iu_fu_is2_frc : std_ulogic_vector(0 to 6); +signal iu_fu_is2_frt : std_ulogic_vector(0 to 6); +signal iu_fu_is2_fra_v : std_ulogic; +signal iu_fu_is2_frb_v : std_ulogic; +signal iu_fu_is2_frc_v : std_ulogic; +signal iu_fu_is2_ucfmul : std_ulogic; +signal iu_fu_is2_tid : std_ulogic_vector(0 to 1); +signal rf0_tid : std_ulogic_vector(0 to 1); + +signal iu_fu_is2_bypsel : std_ulogic_vector(0 to 5); +signal iu_fu_is2_bypsel_din : std_ulogic_vector(0 to 5); +signal is2_ifar : EFF_IFAR; +signal is2_ifar_t0 : EFF_IFAR; +signal is2_ifar_t1 : EFF_IFAR; +signal is2_ifar_t2 : EFF_IFAR; +signal is2_ifar_t3 : EFF_IFAR; + +signal rf0_ifar : EFF_IFAR; + + +signal pc_iu_sg_0, pc_iu_sg_1 : std_ulogic; +signal pc_iu_func_sl_thold_0 , pc_iu_func_sl_thold_1 : std_ulogic; +signal pc_iu_func_sl_thold_0_b : std_ulogic; +signal forcee : std_ulogic; + +signal is2_flush : std_ulogic_vector(0 to 3); + +signal is2_is_ucode : std_ulogic; +signal is2_issue_sel_db : std_ulogic_vector(0 to 3); + +signal is2_stall : std_ulogic_vector(0 to 3); +signal dep_hit_b : std_ulogic_vector(0 to 3); + +signal is1_v_din_premux : std_ulogic_vector(0 to 3); +signal is2_v_dout_premux : std_ulogic_vector(0 to 3); +signal is1_v_din : std_ulogic_vector(0 to 3); +signal is2_v_dout : std_ulogic_vector(0 to 3); +signal ignore_flush_is2 : std_ulogic_vector(0 to 3); + +signal is2v_scin, is2v_scout : std_ulogic_vector(0 to 3); +signal mask_scin, mask_scout : std_ulogic_vector(0 to 7); +signal hi_pri_mask_q : std_ulogic_vector(0 to 3); +signal md_pri_mask_q : std_ulogic_vector(0 to 3); + +signal rf0_took_latch_scout : std_ulogic_vector(0 to 11); +signal rf0_took_latch_scin : std_ulogic_vector(0 to 11); + + +signal hi_did0no1, hi_did0no2, hi_did0no3 : std_ulogic; +signal hi_did1no0, hi_did1no2, hi_did1no3 : std_ulogic; +signal hi_did2no1, hi_did2no0, hi_did2no3 : std_ulogic; +signal hi_did3no1, hi_did3no2, hi_did3no0 : std_ulogic; + +signal md_did0no1, md_did0no2, md_did0no3 : std_ulogic; +signal md_did1no0, md_did1no2, md_did1no3 : std_ulogic; +signal md_did2no1, md_did2no0, md_did2no3 : std_ulogic; +signal md_did3no1, md_did3no2, md_did3no0 : std_ulogic; + +signal hi_sel, hi_sel_b, md_sel, md_sel_b, hi_later, md_later : std_ulogic_vector(0 to 3); + +signal hi_did3no0_din : std_ulogic; +signal hi_did3no1_din : std_ulogic; +signal hi_did3no2_din : std_ulogic; + +signal hi_did2no0_din : std_ulogic; +signal hi_did2no1_din : std_ulogic; + +signal hi_did1no0_din : std_ulogic; + +signal md_did3no0_din : std_ulogic; +signal md_did3no1_din : std_ulogic; +signal md_did3no2_din : std_ulogic; + +signal md_did2no0_din : std_ulogic; +signal md_did2no1_din : std_ulogic; + +signal md_did1no0_din : std_ulogic; +signal pri_rand : std_ulogic_vector(0 to 5); +signal hi_did3no0_d : std_ulogic; +signal hi_did3no1_d : std_ulogic; +signal hi_did3no2_d : std_ulogic; + +signal hi_did2no0_d : std_ulogic; +signal hi_did2no1_d : std_ulogic; + +signal hi_did1no0_d : std_ulogic; + +signal md_did3no0_d : std_ulogic; +signal md_did3no1_d : std_ulogic; +signal md_did3no2_d : std_ulogic; + +signal md_did2no0_d : std_ulogic; +signal md_did2no1_d : std_ulogic; + +signal md_did1no0_d : std_ulogic; + + +signal issselhi_b, issselmd_b : std_ulogic_vector(0 to 3); +signal issselhi2_b, issselmd2_b : std_ulogic_vector(0 to 3); +signal no_hi_v,no_hi_v_n01, no_hi_v_n23 : std_ulogic; + +signal hi_l30, hi_l31, hi_l32 : std_ulogic; +signal hi_l23, hi_l20, hi_l21 : std_ulogic; +signal hi_l12, hi_l13, hi_l10 : std_ulogic; +signal hi_l01, hi_l02, hi_l03 : std_ulogic; + +signal md_l30, md_l31, md_l32 : std_ulogic; +signal md_l23, md_l20, md_l21 : std_ulogic; +signal md_l12, md_l13, md_l10 : std_ulogic; +signal md_l01, md_l02, md_l03 : std_ulogic; + +signal iu_is2_take_t_int_b : std_ulogic_vector(0 to 3); +signal iu_is2_take_t_int : std_ulogic_vector(0 to 3); + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +begin + +tidn <= '0'; +tiup <= '1'; + +act_dis <= '0'; +d_mode <= '0'; +mpw2_b <= '1'; + + + + + + + + + + + + + auperv_2to1_reg: tri_plat + generic map (width => 2, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_iu_func_sl_thold_2, + din(1) => pc_iu_sg_2, + q(0) => pc_iu_func_sl_thold_1, + q(1) => pc_iu_sg_1); +auperv_1to0_reg: tri_plat + generic map (width => 2, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_iu_func_sl_thold_1, + din(1) => pc_iu_sg_1, + q(0) => pc_iu_func_sl_thold_0, + q(1) => pc_iu_sg_0); + + + + + lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map ( + clkoff_b => clkoff_b, + thold => pc_iu_func_sl_thold_0, + sg => pc_iu_sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => pc_iu_func_sl_thold_0_b ); + + + + + + + ignore_flush_is2(0 to 3) <= (i_afd_ignore_flush_is2_t0 and not xu_iu_is2_flush(0)) & + (i_afd_ignore_flush_is2_t1 and not xu_iu_is2_flush(1)) & + (i_afd_ignore_flush_is2_t2 and not xu_iu_is2_flush(2)) & + (i_afd_ignore_flush_is2_t3 and not xu_iu_is2_flush(3)); + + + + + is2_stall(0 to 3) <= is2_v_t(0 to 3) and not is2_issue_sel(0 to 3); + + dep_hit_b(0 to 3) <= i_axu_is1_dep_hit_t0_b & i_axu_is1_dep_hit_t1_b & i_axu_is1_dep_hit_t2_b & i_axu_is1_dep_hit_t3_b; + + is1_v_din_premux(0 to 3) <= ((i_axu_is1_early_v_t0 & i_axu_is1_early_v_t1 & i_axu_is1_early_v_t2 & i_axu_is1_early_v_t3) + and not is2_stall(0 to 3)) + and (not iu_au_is1_flush(0 to 3)); + + + is1_v_din(0 to 3) <= (is1_v_din_premux(0 to 3) and dep_hit_b(0 to 3)) or + (is2_v_dout_premux(0 to 3) and is2_stall(0 to 3)); + + is2v_reg: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 4) + port map ( + nclk => nclk, act => tiup, + vd => vdd, gd => gnd, + forcee => forcee, delay_lclkr => delay_lclkr, + thold_b => pc_iu_func_sl_thold_0_b, sg => pc_iu_sg_0, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + scin => is2v_scin, + scout => is2v_scout , + din(0 to 3) => is1_v_din(0 to 3), + + dout(0 to 3) => is2_v_dout(0 to 3) + + ); + + is2_v_dout_premux(0 to 3) <= is2_v_dout(0 to 3) and (not is2_flush(0 to 3) or ignore_flush_is2(0 to 3)); + + is2_v_t(0 to 3) <= is2_v_dout(0 to 3); + + + + mask_reg: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 8) + port map ( + nclk => nclk, act => tiup, + vd => vdd, gd => gnd, + forcee => forcee, delay_lclkr => delay_lclkr, + thold_b => pc_iu_func_sl_thold_0_b, sg => pc_iu_sg_0, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + scin => mask_scin, + scout => mask_scout , + din(0 to 3) => iu_au_hi_pri_mask(0 to 3), + din(4 to 7) => iu_au_md_pri_mask(0 to 3), + + dout(0 to 3) => hi_pri_mask_q(0 to 3), + dout(4 to 7) => md_pri_mask_q(0 to 3) + + ); + + + +is2_flush(0 to 3) <= xu_iu_is2_flush(0 to 3) or uc_flush(0 to 3); + + + + + + + + skip_b(0) <= not skip_dout(0); + skip_b(1) <= not skip_dout(1); + skip_b(2) <= not skip_dout(2); + skip_b(3) <= not skip_dout(3); + + + +hi_mask_v_nand2: hi_mask_v_b <= not(hi_pri_mask_q(0 to 3) and is2_v_dout(0 to 3)); +md_mask_v_nand2: md_mask_v_b <= not(md_pri_mask_q(0 to 3) and is2_v_dout(0 to 3)); + +hi_mask_v_inv: hi_mask_v <= not hi_mask_v_b; +md_mask_v_inv: md_mask_v <= not md_mask_v_b; + +highpri0v_nand2: highpri_v_b(0) <= not(hi_mask_v(0) and skip_b(0)); +highpri1v_nand2: highpri_v_b(1) <= not(hi_mask_v(1) and skip_b(1)); +highpri2v_nand2: highpri_v_b(2) <= not(hi_mask_v(2) and skip_b(2)); +highpri3v_nand2: highpri_v_b(3) <= not(hi_mask_v(3) and skip_b(3)); + + +medpri0v_nand2: medpri_v_b(0) <= not(md_mask_v(0) and skip_b(0)); +medpri1v_nand2: medpri_v_b(1) <= not(md_mask_v(1) and skip_b(1)); +medpri2v_nand2: medpri_v_b(2) <= not(md_mask_v(2) and skip_b(2)); +medpri3v_nand2: medpri_v_b(3) <= not(md_mask_v(3) and skip_b(3)); + + +highpri0v_inv: highpri_v(0) <= not highpri_v_b(0); +highpri1v_inv: highpri_v(1) <= not highpri_v_b(1); +highpri2v_inv: highpri_v(2) <= not highpri_v_b(2); +highpri3v_inv: highpri_v(3) <= not highpri_v_b(3); + +hi_sel_nor23: hi_sel(3) <= not (highpri_v_b(3) or hi_later(3)); +hi_sel_nand33: hi_later(3) <= not (hi_l30 and hi_l31 and hi_l32); +hi_sel_nand230: hi_l30 <= not (hi_did3no0 and highpri_v(0)); +hi_sel_nand231: hi_l31 <= not (hi_did3no1 and highpri_v(1)); +hi_sel_nand232: hi_l32 <= not (hi_did3no2 and highpri_v(2)); + +hi_sel_nor22: hi_sel(2) <= not (highpri_v_b(2) or hi_later(2)) ; +hi_sel_nand32: hi_later(2) <= not (hi_l23 and hi_l20 and hi_l21); +hi_sel_nand223: hi_l23 <= not (hi_did2no3 and highpri_v(3)); +hi_sel_nand220: hi_l20 <= not (hi_did2no0 and highpri_v(0)); +hi_sel_nand221: hi_l21 <= not (hi_did2no1 and highpri_v(1)); + +hi_sel_nor21: hi_sel(1) <= not (highpri_v_b(1) or hi_later(1)) ; +hi_sel_nand31: hi_later(1) <= not (hi_l12 and hi_l13 and hi_l10); +hi_sel_nand212: hi_l12 <= not (hi_did1no2 and highpri_v(2)); +hi_sel_nand213: hi_l13 <= not (hi_did1no3 and highpri_v(3)); +hi_sel_nand210: hi_l10 <= not (hi_did1no0 and highpri_v(0)); + +hi_sel_nor20: hi_sel(0) <= not (highpri_v_b(0) or hi_later(0)) ; +hi_sel_nand30: hi_later(0) <= not (hi_l01 and hi_l02 and hi_l03); +hi_sel_nand201: hi_l01 <= not (hi_did0no1 and highpri_v(1)); +hi_sel_nand202: hi_l02 <= not (hi_did0no2 and highpri_v(2)); +hi_sel_nand203: hi_l03 <= not (hi_did0no3 and highpri_v(3)); + + +medpri0v_inv: medpri_v(0) <= not medpri_v_b(0); +medpri1v_inv: medpri_v(1) <= not medpri_v_b(1); +medpri2v_inv: medpri_v(2) <= not medpri_v_b(2); +medpri3v_inv: medpri_v(3) <= not medpri_v_b(3); + +md_sel_nor23: md_sel(3) <= not (medpri_v_b(3) or md_later(3)); +md_sel_nand33: md_later(3) <= not (md_l30 and md_l31 and md_l32); +md_sel_nand230: md_l30 <= not (md_did3no0 and medpri_v(0)); +md_sel_nand231: md_l31 <= not (md_did3no1 and medpri_v(1)); +md_sel_nand232: md_l32 <= not (md_did3no2 and medpri_v(2)); + +md_sel_nor22: md_sel(2) <= not (medpri_v_b(2) or md_later(2)) ; +md_sel_nand32: md_later(2) <= not (md_l23 and md_l20 and md_l21); +md_sel_nand223: md_l23 <= not (md_did2no3 and medpri_v(3)); +md_sel_nand220: md_l20 <= not (md_did2no0 and medpri_v(0)); +md_sel_nand221: md_l21 <= not (md_did2no1 and medpri_v(1)); + +md_sel_nor21: md_sel(1) <= not (medpri_v_b(1) or md_later(1)) ; +md_sel_nand31: md_later(1) <= not (md_l12 and md_l13 and md_l10); +md_sel_nand212: md_l12 <= not (md_did1no2 and medpri_v(2)); +md_sel_nand213: md_l13 <= not (md_did1no3 and medpri_v(3)); +md_sel_nand210: md_l10 <= not (md_did1no0 and medpri_v(0)); + +md_sel_nor20: md_sel(0) <= not (medpri_v_b(0) or md_later(0)) ; +md_sel_nand30: md_later(0) <= not (md_l01 and md_l02 and md_l03); +md_sel_nand201: md_l01 <= not (md_did0no1 and medpri_v(1)); +md_sel_nand202: md_l02 <= not (md_did0no2 and medpri_v(2)); +md_sel_nand203: md_l03 <= not (md_did0no3 and medpri_v(3)); + + + + + +hi_sel_inv0: hi_sel_b(0) <= not hi_sel(0); +hi_sel_inv1: hi_sel_b(1) <= not hi_sel(1); +hi_sel_inv2: hi_sel_b(2) <= not hi_sel(2); +hi_sel_inv3: hi_sel_b(3) <= not hi_sel(3); + +hi_reordf_nand230: hi_did3no0_din <= not (hi_sel_b(3) and hi_n230); +hi_reordf_nand231: hi_did3no1_din <= not (hi_sel_b(3) and hi_n231); +hi_reordf_nand232: hi_did3no2_din <= not (hi_sel_b(3) and hi_n232); +hi_reord_nand230: hi_n230 <= not (hi_sel_b(0) and hi_did3no0); +hi_reord_nand231: hi_n231 <= not (hi_sel_b(1) and hi_did3no1); +hi_reord_nand232: hi_n232 <= not (hi_sel_b(2) and hi_did3no2); + + + +hi_reordf_nand220: hi_did2no0_din <= not(hi_sel_b(2) and hi_n220); +hi_reord_nand220: hi_n220 <= not(hi_sel_b(0) and hi_did2no0); + +hi_reordf_nand221: hi_did2no1_din <= not(hi_sel_b(2) and hi_n221); +hi_reord_nand221: hi_n221 <= not(hi_sel_b(1) and hi_did2no1); + +hi_reord_inv23: hi_did2no3 <= not hi_did3no2; + +hi_reordf_nand210: hi_did1no0_din <= not(hi_sel_b(1) and hi_n210); +hi_reord_nand210: hi_n210 <= not(hi_sel_b(0) and hi_did1no0); + +hi_reord_inv12: hi_did1no2 <= not hi_did2no1; +hi_reord_inv13: hi_did1no3 <= not hi_did3no1; + +hi_reord_inv01: hi_did0no1 <= not hi_did1no0; +hi_reord_inv02: hi_did0no2 <= not hi_did2no0; +hi_reord_inv03: hi_did0no3 <= not hi_did3no0; + + + +md_sel_inv0: md_sel_b(0) <= not md_sel(0); +md_sel_inv1: md_sel_b(1) <= not md_sel(1); +md_sel_inv2: md_sel_b(2) <= not md_sel(2); +md_sel_inv3: md_sel_b(3) <= not md_sel(3); + +md_reordf_nand230: md_did3no0_din <= not (md_sel_b(3) and md_n230); +md_reordf_nand231: md_did3no1_din <= not (md_sel_b(3) and md_n231); +md_reordf_nand232: md_did3no2_din <= not (md_sel_b(3) and md_n232); +md_reord_nand230: md_n230 <= not (md_sel_b(0) and md_did3no0); +md_reord_nand231: md_n231 <= not (md_sel_b(1) and md_did3no1); +md_reord_nand232: md_n232 <= not (md_sel_b(2) and md_did3no2); + + +md_reordf_nand220: md_did2no0_din <= not(md_sel_b(2) and md_n220); +md_reord_nand220: md_n220 <= not(md_sel_b(0) and md_did2no0); + +md_reordf_nand221: md_did2no1_din <= not(md_sel_b(2) and md_n221); +md_reord_nand221: md_n221 <= not(md_sel_b(1) and md_did2no1); + +md_reord_inv23: md_did2no3 <= not md_did3no2; + +md_reordf_nand210: md_did1no0_din <= not(md_sel_b(1) and md_n210); +md_reord_nand210: md_n210 <= not(md_sel_b(0) and md_did1no0); + +md_reord_inv12: md_did1no2 <= not md_did2no1; +md_reord_inv13: md_did1no3 <= not md_did3no1; + +md_reord_inv01: md_did0no1 <= not md_did1no0; +md_reord_inv02: md_did0no2 <= not md_did2no0; +md_reord_inv03: md_did0no3 <= not md_did3no0; + + + + + +nohi_nand21: no_hi_v_n01 <= not (hi_mask_v_b(0) and hi_mask_v_b(1)); +nohi_nand22: no_hi_v_n23 <= not (hi_mask_v_b(2) and hi_mask_v_b(3)); +nohi_nor2: no_hi_v <= not (no_hi_v_n01 or no_hi_v_n23); + + +isssel0_inv: issselhi_b(0) <= not (hi_sel(0)); +isssel1_inv: issselhi_b(1) <= not (hi_sel(1)); +isssel2_inv: issselhi_b(2) <= not (hi_sel(2)); +isssel3_inv: issselhi_b(3) <= not (hi_sel(3)); + +isssel0_bnand2: issselmd_b(0) <= not (md_sel(0) and no_hi_v); +isssel1_bnand2: issselmd_b(1) <= not (md_sel(1) and no_hi_v); +isssel2_bnand2: issselmd_b(2) <= not (md_sel(2) and no_hi_v); +isssel3_bnand2: issselmd_b(3) <= not (md_sel(3) and no_hi_v); + +isssel0_2inv: issselhi2_b(0) <= not (hi_sel(0)); +isssel1_2inv: issselhi2_b(1) <= not (hi_sel(1)); +isssel2_2inv: issselhi2_b(2) <= not (hi_sel(2)); +isssel3_2inv: issselhi2_b(3) <= not (hi_sel(3)); + +isssel0_2bnand2: issselmd2_b(0) <= not (md_sel(0) and no_hi_v); +isssel1_2bnand2: issselmd2_b(1) <= not (md_sel(1) and no_hi_v); +isssel2_2bnand2: issselmd2_b(2) <= not (md_sel(2) and no_hi_v); +isssel3_2bnand2: issselmd2_b(3) <= not (md_sel(3) and no_hi_v); + + + + +isssel0_fnand2: iu_is2_take_t(0) <= not (issselhi2_b(0) and issselmd2_b(0)); +isssel1_fnand2: iu_is2_take_t(1) <= not (issselhi2_b(1) and issselmd2_b(1)); +isssel2_fnand2: iu_is2_take_t(2) <= not (issselhi2_b(2) and issselmd2_b(2)); +isssel3_fnand2: iu_is2_take_t(3) <= not (issselhi2_b(3) and issselmd2_b(3)); + + + + + + iu_is2_take_t_int(0) <= not (issselhi_b(0) and issselmd_b(0)); + iu_is2_take_t_int(1) <= not (issselhi_b(1) and issselmd_b(1)); + iu_is2_take_t_int(2) <= not (issselhi_b(2) and issselmd_b(2)); + iu_is2_take_t_int(3) <= not (issselhi_b(3) and issselmd_b(3)); + + + +fu_tid_invB0: iu_is2_take_t_int_b(0) <= not iu_is2_take_t_int(0); +fu_tid_invB1: iu_is2_take_t_int_b(1) <= not iu_is2_take_t_int(1); +fu_tid_invB2: iu_is2_take_t_int_b(2) <= not iu_is2_take_t_int(2); +fu_tid_invB3: iu_is2_take_t_int_b(3) <= not iu_is2_take_t_int(3); + +fu_tid_invA0: iu_fu_is2_tid_decode(0) <= not iu_is2_take_t_int_b(0); +fu_tid_invA1: iu_fu_is2_tid_decode(1) <= not iu_is2_take_t_int_b(1); +fu_tid_invA2: iu_fu_is2_tid_decode(2) <= not iu_is2_take_t_int_b(2); +fu_tid_invA3: iu_fu_is2_tid_decode(3) <= not iu_is2_take_t_int_b(3); + + + +is2_issue_sel(0 to 3) <= not (issselhi_b(0 to 3) and issselmd_b(0 to 3)); + + + +is2_issue_sel_buf1_b(0 to 3) <= not is2_issue_sel(0 to 3); + +is2_issue_sel_buf2(0 to 3) <= not is2_issue_sel_buf1_b(0 to 3); + +is2_issue_sel_buf3_b(0 to 3) <= not is2_issue_sel_buf2(0 to 3); + +is2_issue_sel_buf4(0 to 3) <= not is2_issue_sel_buf3_b(0 to 3); + + + + +iu_fu_is2_instr(0 to 31) <= (i_afd_is2_t0_instr and (0 to 31 => is2_issue_sel_buf4(0))) or + (i_afd_is2_t1_instr and (0 to 31 => is2_issue_sel_buf4(1))) or + (i_afd_is2_t2_instr and (0 to 31 => is2_issue_sel_buf4(2))) or + (i_afd_is2_t3_instr and (0 to 31 => is2_issue_sel_buf4(3))); + +is2_instr_v <= i_afd_is2_t0_instr_v or i_afd_is2_t1_instr_v or i_afd_is2_t2_instr_v or i_afd_is2_t3_instr_v; + +iu_fu_is2_instr_v <= ((i_afd_is2_t0_instr_v and (not is2_flush(0) or ignore_flush_is2(0))) and is2_issue_sel_buf4(0)) or + ((i_afd_is2_t1_instr_v and (not is2_flush(1) or ignore_flush_is2(1))) and is2_issue_sel_buf4(1)) or + ((i_afd_is2_t2_instr_v and (not is2_flush(2) or ignore_flush_is2(2))) and is2_issue_sel_buf4(2)) or + ((i_afd_is2_t3_instr_v and (not is2_flush(3) or ignore_flush_is2(3))) and is2_issue_sel_buf4(3)) ; + + +iu_fu_is2_fra <= (i_afd_is2_fra_t0 and (0 to 6 => is2_issue_sel_buf4(0))) or + (i_afd_is2_fra_t1 and (0 to 6 => is2_issue_sel_buf4(1))) or + (i_afd_is2_fra_t2 and (0 to 6 => is2_issue_sel_buf4(2))) or + (i_afd_is2_fra_t3 and (0 to 6 => is2_issue_sel_buf4(3))) ; + +iu_fu_is2_frb <= (i_afd_is2_frb_t0 and (0 to 6 => is2_issue_sel_buf4(0))) or + (i_afd_is2_frb_t1 and (0 to 6 => is2_issue_sel_buf4(1))) or + (i_afd_is2_frb_t2 and (0 to 6 => is2_issue_sel_buf4(2))) or + (i_afd_is2_frb_t3 and (0 to 6 => is2_issue_sel_buf4(3))) ; + +iu_fu_is2_frc <= (i_afd_is2_frc_t0 and (0 to 6 => is2_issue_sel_buf4(0))) or + (i_afd_is2_frc_t1 and (0 to 6 => is2_issue_sel_buf4(1))) or + (i_afd_is2_frc_t2 and (0 to 6 => is2_issue_sel_buf4(2))) or + (i_afd_is2_frc_t3 and (0 to 6 => is2_issue_sel_buf4(3))) ; + +iu_fu_is2_frt <= (i_afd_is2_frt_t0 and (0 to 6 => is2_issue_sel_buf4(0))) or + (i_afd_is2_frt_t1 and (0 to 6 => is2_issue_sel_buf4(1))) or + (i_afd_is2_frt_t2 and (0 to 6 => is2_issue_sel_buf4(2))) or + (i_afd_is2_frt_t3 and (0 to 6 => is2_issue_sel_buf4(3))) ; + + +iu_fu_is2_fra_v <= (i_afd_is2_fra_v_t0 and is2_issue_sel_buf4(0)) or + (i_afd_is2_fra_v_t1 and is2_issue_sel_buf4(1)) or + (i_afd_is2_fra_v_t2 and is2_issue_sel_buf4(2)) or + (i_afd_is2_fra_v_t3 and is2_issue_sel_buf4(3)) ; + +iu_fu_is2_frb_v <= (i_afd_is2_frb_v_t0 and is2_issue_sel_buf4(0)) or + (i_afd_is2_frb_v_t1 and is2_issue_sel_buf4(1)) or + (i_afd_is2_frb_v_t2 and is2_issue_sel_buf4(2)) or + (i_afd_is2_frb_v_t3 and is2_issue_sel_buf4(3)) ; + +iu_fu_is2_frc_v <= (i_afd_is2_frc_v_t0 and is2_issue_sel_buf4(0)) or + (i_afd_is2_frc_v_t1 and is2_issue_sel_buf4(1)) or + (i_afd_is2_frc_v_t2 and is2_issue_sel_buf4(2)) or + (i_afd_is2_frc_v_t3 and is2_issue_sel_buf4(3)) ; + + + +iu_fu_is2_instr_match <= (i_axu_is2_instr_match_t0 and is2_issue_sel_buf4(0)) or + (i_axu_is2_instr_match_t1 and is2_issue_sel_buf4(1)) or + (i_axu_is2_instr_match_t2 and is2_issue_sel_buf4(2)) or + (i_axu_is2_instr_match_t3 and is2_issue_sel_buf4(3)) ; + + + + + +iu_fu_is2_ucfmul <= iu_fu_is2_instr(0 to 2) = "111" and iu_fu_is2_instr(4 to 5) = "11" and + iu_fu_is2_instr(26 to 30) = "10001"; + + + + is2_is_ucode <= (i_afd_is2_is_ucode_t0 and is2_issue_sel_buf4(0)) or + (i_afd_is2_is_ucode_t1 and is2_issue_sel_buf4(1)) or + (i_afd_is2_is_ucode_t2 and is2_issue_sel_buf4(2)) or + (i_afd_is2_is_ucode_t3 and is2_issue_sel_buf4(3)) ; + +is2_ifar_t0 <= i_afd_is2_ifar_t0; +is2_ifar_t1 <= i_afd_is2_ifar_t1; +is2_ifar_t2 <= i_afd_is2_ifar_t2; +is2_ifar_t3 <= i_afd_is2_ifar_t3; + + +is2_ifar <= (is2_ifar_t0 and (0 to EFF_IFAR'length-1 => is2_issue_sel_buf4(0))) or + (is2_ifar_t1 and (0 to EFF_IFAR'length-1 => is2_issue_sel_buf4(1))) or + (is2_ifar_t2 and (0 to EFF_IFAR'length-1 => is2_issue_sel_buf4(2))) or + (is2_ifar_t3 and (0 to EFF_IFAR'length-1 => is2_issue_sel_buf4(3))) ; + + +iu_fu_is2_tid(0) <= is2_issue_sel(2) or is2_issue_sel(3); +iu_fu_is2_tid(1) <= is2_issue_sel(1) or is2_issue_sel(3); + + + + +hi_did3no0_d <= pri_rand(0) when (spr_fiss_pri_rand_always or (spr_fiss_pri_rand_flush and or_reduce(xu_iu_is2_flush(0 to 3)))) = '1' else hi_did3no0_din; +hi_did3no1_d <= pri_rand(1) when (spr_fiss_pri_rand_always or (spr_fiss_pri_rand_flush and or_reduce(xu_iu_is2_flush(0 to 3)))) = '1' else hi_did3no1_din; +hi_did3no2_d <= pri_rand(2) when (spr_fiss_pri_rand_always or (spr_fiss_pri_rand_flush and or_reduce(xu_iu_is2_flush(0 to 3)))) = '1' else hi_did3no2_din; +hi_did2no0_d <= pri_rand(3) when (spr_fiss_pri_rand_always or (spr_fiss_pri_rand_flush and or_reduce(xu_iu_is2_flush(0 to 3)))) = '1' else hi_did2no0_din; +hi_did2no1_d <= pri_rand(4) when (spr_fiss_pri_rand_always or (spr_fiss_pri_rand_flush and or_reduce(xu_iu_is2_flush(0 to 3)))) = '1' else hi_did2no1_din; +hi_did1no0_d <= pri_rand(5) when (spr_fiss_pri_rand_always or (spr_fiss_pri_rand_flush and or_reduce(xu_iu_is2_flush(0 to 3)))) = '1' else hi_did1no0_din; +md_did3no0_d <= pri_rand(0) when (spr_fiss_pri_rand_always or (spr_fiss_pri_rand_flush and or_reduce(xu_iu_is2_flush(0 to 3)))) = '1' else md_did3no0_din; +md_did3no1_d <= pri_rand(1) when (spr_fiss_pri_rand_always or (spr_fiss_pri_rand_flush and or_reduce(xu_iu_is2_flush(0 to 3)))) = '1' else md_did3no1_din; +md_did3no2_d <= pri_rand(2) when (spr_fiss_pri_rand_always or (spr_fiss_pri_rand_flush and or_reduce(xu_iu_is2_flush(0 to 3)))) = '1' else md_did3no2_din; +md_did2no0_d <= pri_rand(3) when (spr_fiss_pri_rand_always or (spr_fiss_pri_rand_flush and or_reduce(xu_iu_is2_flush(0 to 3)))) = '1' else md_did2no0_din; +md_did2no1_d <= pri_rand(4) when (spr_fiss_pri_rand_always or (spr_fiss_pri_rand_flush and or_reduce(xu_iu_is2_flush(0 to 3)))) = '1' else md_did2no1_din; +md_did1no0_d <= pri_rand(5) when (spr_fiss_pri_rand_always or (spr_fiss_pri_rand_flush and or_reduce(xu_iu_is2_flush(0 to 3)))) = '1' else md_did1no0_din; + +pri_rand(0 TO 5) <= "001000" when spr_fiss_pri_rand(0 to 4) = "00000" else + "100111" when spr_fiss_pri_rand(0 to 4) = "00001" else + "110111" when spr_fiss_pri_rand(0 to 4) = "00010" else + "000001" when spr_fiss_pri_rand(0 to 4) = "00011" else + "000110" when spr_fiss_pri_rand(0 to 4) = "00100" else + "001001" when spr_fiss_pri_rand(0 to 4) = "00101" else + "011000" when spr_fiss_pri_rand(0 to 4) = "00110" else + "111101" when spr_fiss_pri_rand(0 to 4) = "00111" else + "100101" when spr_fiss_pri_rand(0 to 4) = "01000" else + "010110" when spr_fiss_pri_rand(0 to 4) = "01001" else + "101101" when spr_fiss_pri_rand(0 to 4) = "01010" else + "111110" when spr_fiss_pri_rand(0 to 4) = "01011" else + "110110" when spr_fiss_pri_rand(0 to 4) = "01100" else + "101001" when spr_fiss_pri_rand(0 to 4) = "01101" else + "000000" when spr_fiss_pri_rand(0 to 4) = "01110" else + "111010" when spr_fiss_pri_rand(0 to 4) = "01111" else + "000111" when spr_fiss_pri_rand(0 to 4) = "10000" else + "111001" when spr_fiss_pri_rand(0 to 4) = "10001" else + "111000" when spr_fiss_pri_rand(0 to 4) = "10010" else + "011010" when spr_fiss_pri_rand(0 to 4) = "10011" else + "111111" when spr_fiss_pri_rand(0 to 4) = "10100" else + "010010" when spr_fiss_pri_rand(0 to 4) = "10101" else + "000010" when spr_fiss_pri_rand(0 to 4) = "10110" else + "000101" when spr_fiss_pri_rand(0 to 4) = "10111" else + "111111" when spr_fiss_pri_rand(0 to 4) = "11000" else + "000000" when spr_fiss_pri_rand(0 to 4) = "11001" else + "011010" when spr_fiss_pri_rand(0 to 4) = "11010" else + "100101" when spr_fiss_pri_rand(0 to 4) = "11011" else + "001001" when spr_fiss_pri_rand(0 to 4) = "11100" else + "110110" when spr_fiss_pri_rand(0 to 4) = "11101" else + "000111" when spr_fiss_pri_rand(0 to 4) = "11110" else + "111000" ; + + + + + + rf0_took_latch: tri_rlmreg_p + generic map (init => 65, expand_type => expand_type, needs_sreset => needs_sreset, width => 12) + port map ( + nclk => nclk, act => tiup, + vd => vdd, gd => gnd, + forcee => forcee, delay_lclkr => delay_lclkr, + thold_b => pc_iu_func_sl_thold_0_b, sg => pc_iu_sg_0, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + scin => rf0_took_latch_scin, + scout => rf0_took_latch_scout, + din(00) => hi_did3no0_d, + din(01) => hi_did3no1_d, + din(02) => hi_did3no2_d, + din(03) => hi_did2no0_d, + din(04) => hi_did2no1_d, + din(05) => hi_did1no0_d, + din(06) => md_did3no0_d, + din(07) => md_did3no1_d, + din(08) => md_did3no2_d, + din(09) => md_did2no0_d, + din(10) => md_did2no1_d, + din(11) => md_did1no0_d, + + dout(00) => hi_did3no0, + dout(01) => hi_did3no1, + dout(02) => hi_did3no2, + dout(03) => hi_did2no0, + dout(04) => hi_did2no1, + dout(05) => hi_did1no0, + dout(06) => md_did3no0, + dout(07) => md_did3no1, + dout(08) => md_did3no2, + dout(09) => md_did2no0, + dout(10) => md_did2no1, + dout(11) => md_did1no0 + + ); + + + + + +is2_act <= is2_instr_v or is2_act_l2; + + rf0_stage_latch: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 77+EFF_IFAR'length) + port map ( + nclk => nclk, act => is2_act, + vd => vdd, gd => gnd, + forcee => forcee, delay_lclkr => delay_lclkr, + thold_b => pc_iu_func_sl_thold_0_b, sg => pc_iu_sg_0, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + scin => rf0_stage_latch_scin, + scout => rf0_stage_latch_scout, + + din(00 to 31) => iu_fu_is2_instr(0 to 31), + din(32 ) => iu_fu_is2_instr_v, + din(33 ) => is2_is_ucode, + din(34 ) => iu_fu_is2_fra_v, + din(35 to 41) => iu_fu_is2_fra(0 to 6), + din(42 ) => iu_fu_is2_frb_v, + din(43 to 49) => iu_fu_is2_frb(0 to 6), + din(50 ) => iu_fu_is2_frc_v, + din(51 to 57) => iu_fu_is2_frc(0 to 6), + din(58 ) => iu_fu_is2_ucfmul, + din(59 to 65) => iu_fu_is2_frt(0 to 6), + din(66 ) => spare_l2(0), + din(67 ) => spare_l2(1), + din(68 ) => iu_fu_is2_instr_match, + din(69 to 70) => iu_fu_is2_tid(0 to 1), + din(71 to 76) => iu_fu_is2_bypsel_din(0 to 5), + din(77 to 76+EFF_IFAR'length) => is2_ifar, + + dout(00 to 31) => iu_fu_rf0_instr(0 to 31), + dout(32 ) => iu_fu_rf0_instr_v, + dout(33 ) => iu_fu_rf0_is_ucode, + dout(34 ) => iu_fu_rf0_fra_v, + dout(35 to 41) => iu_fu_rf0_fra(0 to 6), + dout(42 ) => iu_fu_rf0_frb_v, + dout(43 to 49) => iu_fu_rf0_frb(0 to 6), + dout(50 ) => iu_fu_rf0_frc_v, + dout(51 to 57) => iu_fu_rf0_frc(0 to 6), + dout(58 ) => iu_fu_rf0_ucfmul, + dout(59 to 65) => iu_fu_rf0_frt(0 to 6), + dout(66 to 67) => spare_l2(0 to 1), + dout(68 ) => iu_fu_rf0_instr_match, + dout(69 to 70) => rf0_tid(0 to 1), + dout(71 to 76) => iu_fu_rf0_bypsel(0 to 5), + dout(77 to 76+EFF_IFAR'length) => rf0_ifar + + ); + +iu_fu_rf0_ifar <= rf0_ifar; +iu_fu_rf0_tid <= rf0_tid; + +spare_unused(0 to 1) <= tidn & tidn; + + + + + + + rf0_wpc_sp_latch: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 5) + port map ( + nclk => nclk, act => tiup, + vd => vdd, gd => gnd, + forcee => forcee, delay_lclkr => delay_lclkr, + thold_b => pc_iu_func_sl_thold_0_b, sg => pc_iu_sg_0, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + scin => rf0_wpc_sp_latch_scin, + scout => rf0_wpc_sp_latch_scout , + din(0) => is2_act_din, + din(1) => spare_l2(2), + din(2) => spare_l2(3), + din(3) => spare_l2(4), + din(4) => spare_l2(5), + + dout(0) => is2_act_l2, + dout(1) => spare_l2(2), + dout(2) => spare_l2(3), + dout(3) => spare_l2(4), + dout(4) => spare_l2(5) + + ); + + disable_cgat <= i_afd_config_iucr_t0(4) or i_afd_config_iucr_t1(4) or i_afd_config_iucr_t2(4) or i_afd_config_iucr_t3(4); + is2_act_din <= is2_instr_v or disable_cgat; + + spare_unused(2) <= d_mode; + spare_unused(3 to 6) <= tidn & tidn & tidn & tidn; + spare_unused(8) <= tidn; + + debug_reg: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 5) + port map ( + nclk => nclk, act => tiup, + vd => vdd, gd => gnd, + forcee => forcee, delay_lclkr => delay_lclkr, + thold_b => pc_iu_func_sl_thold_0_b, sg => pc_iu_sg_0, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + scin => debug_reg_scin, + scout => debug_reg_scout, + din(0 to 3) => is2_issue_sel(0 to 3), + din(4) => spare_l2(6), + + dout(0 to 3) => is2_issue_sel_db(0 to 3), + dout(4) => spare_l2(6) + + ); + +spare_unused(7) <= tidn; + + + + + + +single_step_mode <= i_afd_config_iucr_t0(2) and i_afd_config_iucr_t1(2) and i_afd_config_iucr_t2(2) and i_afd_config_iucr_t3(2); +single_step_divsqrt_mode <= i_afd_config_iucr_t0(3) and i_afd_config_iucr_t1(3) and i_afd_config_iucr_t2(3) and i_afd_config_iucr_t3(3); + +divsqrt_mode <= ((not i_afd_in_ucode_mode_or1d_b_t0) or + (not i_afd_in_ucode_mode_or1d_b_t1) or + (not i_afd_in_ucode_mode_or1d_b_t2) or + (not i_afd_in_ucode_mode_or1d_b_t3)); + + is2_insert_one_bubble <= '0'; + spare_unused(09) <= is2_insert_one_bubble; + + is2_insert_two_bubbles <= '0'; + spare_unused(10) <= is2_insert_two_bubbles; + + is2_insert_three_bubbles <= ((ifdp_is2_est_bubble3_t0 and is2_issue_sel(0)) or + (ifdp_is2_est_bubble3_t1 and is2_issue_sel(1)) or + (ifdp_is2_est_bubble3_t2 and is2_issue_sel(2)) or + (ifdp_is2_est_bubble3_t3 and is2_issue_sel(3))); + + is2_insert_seven_bubbles <= (single_step_mode and or_reduce(is2_issue_sel(0 to 3))) or + (single_step_divsqrt_mode and or_reduce(is2_issue_sel(0 to 3)) and divsqrt_mode); + + + +skip_din(0) <= or_reduce(bubble_din(2 to 4)); +skip_din(1) <= or_reduce(bubble_din(2 to 4)); +skip_din(2) <= or_reduce(bubble_din(2 to 4)); +skip_din(3) <= or_reduce(bubble_din(2 to 4)); + + + + + + +bubble_din(2) <= (not is2_insert_three_bubbles and bubble_dout(2) + and bubble_dout(3)) or + (not is2_insert_three_bubbles and bubble_dout(2) + and bubble_dout(4)) or + ( is2_insert_seven_bubbles); + +bubble_din(3) <= ( bubble_dout(2) and not bubble_dout(3) and not bubble_dout(4)) or + ( bubble_dout(3) and bubble_dout(4)) or + ( is2_insert_three_bubbles) or + ( is2_insert_seven_bubbles); + +bubble_din(4) <= ( bubble_dout(2) and not bubble_dout(4)) or + ( bubble_dout(3) and not bubble_dout(4)) or + ( is2_insert_three_bubbles) or + ( is2_insert_seven_bubbles); + + + + + +is2_bubble_latch: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 3) + port map ( + nclk => nclk, act => tiup, + vd => vdd, gd => gnd, + forcee => forcee, delay_lclkr => delay_lclkr, + thold_b => pc_iu_func_sl_thold_0_b, sg => pc_iu_sg_0, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + scin => is2_bubble_latch_scin, + scout => is2_bubble_latch_scout, + din(0 to 2) => bubble_din, + dout(0 to 2) => bubble_dout + ); + + + +is2_skip_latch: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 4) + port map ( + nclk => nclk, act => tiup, + vd => vdd, gd => gnd, + forcee => forcee, delay_lclkr => delay_lclkr, + thold_b => pc_iu_func_sl_thold_0_b, sg => pc_iu_sg_0, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + scin => is2_skip_latch_scin, + scout => is2_skip_latch_scout, + din(0 to 3) => skip_din, + dout(0 to 3) => skip_dout + ); + + iu_fu_is2_bypsel <= (i_afd_is2_bypsel_t0 and (0 to 5 => is2_issue_sel_buf4(0))) or + (i_afd_is2_bypsel_t1 and (0 to 5 => is2_issue_sel_buf4(1))) or + (i_afd_is2_bypsel_t2 and (0 to 5 => is2_issue_sel_buf4(2))) or + (i_afd_is2_bypsel_t3 and (0 to 5 => is2_issue_sel_buf4(3))) ; + + + iu_fu_is2_bypsel_din <= iu_fu_is2_bypsel; + + + + +fu_iss_debug(0 to 23) <= highpri_v(0 to 3) & medpri_v(0 to 3) & + hi_did3no0 & + hi_did3no1 & + hi_did3no2 & + hi_did2no1 & + hi_did2no0 & + hi_did1no0 & + md_did3no0 & + md_did3no1 & + md_did3no2 & + md_did2no1 & + md_did2no0 & + md_did1no0 & + is2_issue_sel_db(0 to 3); + + + + +is2v_scin(0 to 3) <= i_iss_si & is2v_scout(0 to 2); +mask_scin(0 to 7) <= is2v_scout(3) & mask_scout(0 to 6); + +rf0_took_latch_scin(0 to 11) <= mask_scout(7) & rf0_took_latch_scout(0 to 10); + +rf0_stage_latch_scin(0 to 76+EFF_IFAR'length) <= rf0_took_latch_scout(11) & rf0_stage_latch_scout(0 to 75+EFF_IFAR'length); + +rf0_wpc_sp_latch_scin <= rf0_stage_latch_scout(76+EFF_IFAR'length) & rf0_wpc_sp_latch_scout(0 to 3); + + +debug_reg_scin(0 to 4) <= rf0_wpc_sp_latch_scout(4) & debug_reg_scout(0 to 3); + + +is2_bubble_latch_scin <= debug_reg_scout(4) & is2_bubble_latch_scout(0 to 1); +is2_skip_latch_scin <= is2_bubble_latch_scout(2) & is2_skip_latch_scout(0 to 2); + + +i_iss_so <= is2_skip_latch_scout(3) and an_ac_scan_dis_dc_b; + + + + + + +end iuq_axu_fu_iss; + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_bd.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_bd.vhdl new file mode 100644 index 0000000..6d61b35 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_bd.vhdl @@ -0,0 +1,85 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee, ibm, support; + +use ieee.std_logic_1164.all; +use ibm.std_ulogic_support.all; + +entity iuq_bd is +port( + instruction : in std_ulogic_vector(0 to 31); + branch_decode : out std_ulogic_vector(0 to 3); + + bp_bc_en : in std_ulogic; + bp_bclr_en : in std_ulogic; + bp_bcctr_en : in std_ulogic; + bp_sw_en : in std_ulogic +); + +-- synopsys translate_off +-- synopsys translate_on +end iuq_bd; +architecture iuq_bd of iuq_bd is + +signal b : std_ulogic; +signal bc : std_ulogic; +signal bclr : std_ulogic; +signal bcctr : std_ulogic; +signal br_val : std_ulogic; + +signal bo : std_ulogic_vector(0 to 4); +signal hint : std_ulogic; +signal hint_val : std_ulogic; + +signal unused_instruction : std_ulogic_vector(0 to 10); + +begin + +unused_instruction <= instruction(11 to 20) & instruction(31); + +b <= instruction(0 to 5) = "010010"; +bc <= bp_bc_en and instruction(0 to 5) = "010000"; +bclr <= bp_bclr_en and instruction(0 to 5) = "010011" and instruction(21 to 30) = "0000010000"; +bcctr <= bp_bcctr_en and instruction(0 to 5) = "010011" and instruction(21 to 30) = "1000010000"; + +br_val <= b or bc or bclr or bcctr; + +bo(0 to 4) <= instruction(6 to 10); + + +hint_val <= (bo(0) and bo(2)) or (bp_sw_en and ((bo(0) = '0' and bo(2) = '1' and bo(3) = '1') or + (bo(0) = '1' and bo(2) = '0' and bo(1) = '1'))); + +hint <= (bo(0) and bo(2)) or bo(4); + +branch_decode(0 to 3) <= br_val & b & hint_val & hint; + +end iuq_bd; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_bp.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_bp.vhdl new file mode 100644 index 0000000..2727090 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_bp.vhdl @@ -0,0 +1,2643 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; +use ieee.std_logic_1164.all; + +library ibm; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; + +library support; +use support.power_logic_pkg.all; + +library tri; +use tri.tri_latches_pkg.all; + +library work; +use work.iuq_pkg.all; + +entity iuq_bp is +generic(expand_type : integer := 2 ); +port( + + bp_dbg_data0 : out std_ulogic_vector(0 to 87); + bp_dbg_data1 : out std_ulogic_vector(0 to 87); + + iu3_0_bh_rd_data : in std_ulogic_vector(0 to 1); + iu3_1_bh_rd_data : in std_ulogic_vector(0 to 1); + iu3_2_bh_rd_data : in std_ulogic_vector(0 to 1); + iu3_3_bh_rd_data : in std_ulogic_vector(0 to 1); + + iu1_bh_rd_addr : out std_ulogic_vector(0 to 7); + iu1_bh_rd_act : out std_ulogic; + ex6_bh_wr_data : out std_ulogic_vector(0 to 1); + ex6_bh_wr_addr : out std_ulogic_vector(0 to 7); + ex6_bh_wr_act : out std_ulogic_vector(0 to 3); + + ic_bp_iu1_val : in std_ulogic; + ic_bp_iu1_tid : in std_ulogic_vector(0 to 3); + ic_bp_iu1_ifar : in std_ulogic_vector(52 to 59); + + + ic_bp_iu3_val : in std_ulogic_vector(0 to 3); + ic_bp_iu3_tid : in std_ulogic_vector(0 to 3); + ic_bp_iu3_ifar : in EFF_IFAR; + ic_bp_iu3_error : in std_ulogic_vector(0 to 2); + ic_bp_iu3_2ucode : in std_ulogic; + ic_bp_iu3_2ucode_type : in std_ulogic; + ic_bp_iu3_flush : in std_ulogic; + + ic_bp_iu3_0_instr : in std_ulogic_vector(0 to 35); + ic_bp_iu3_1_instr : in std_ulogic_vector(0 to 35); + ic_bp_iu3_2_instr : in std_ulogic_vector(0 to 35); + ic_bp_iu3_3_instr : in std_ulogic_vector(0 to 35); + + bp_ib_iu4_t0_val : out std_ulogic_vector(0 to 3); + bp_ib_iu4_t1_val : out std_ulogic_vector(0 to 3); + bp_ib_iu4_t2_val : out std_ulogic_vector(0 to 3); + bp_ib_iu4_t3_val : out std_ulogic_vector(0 to 3); + bp_ib_iu4_ifar : out EFF_IFAR; + + bp_ib_iu3_0_instr : out std_ulogic_vector(0 to 31); + bp_ib_iu4_0_instr : out std_ulogic_vector(32 to 43); + bp_ib_iu4_1_instr : out std_ulogic_vector(0 to 43); + bp_ib_iu4_2_instr : out std_ulogic_vector(0 to 43); + bp_ib_iu4_3_instr : out std_ulogic_vector(0 to 43); + + bp_ic_iu5_hold_tid : out std_ulogic_vector(0 to 3); + bp_ic_iu5_redirect_tid : out std_ulogic_vector(0 to 3); + bp_ic_iu5_redirect_ifar : out EFF_IFAR; + + xu_iu_ex5_ifar : in EFF_IFAR; + xu_iu_ex5_tid : in std_ulogic_vector(0 to 3); + xu_iu_ex5_val : in std_ulogic; + xu_iu_ex5_br_update : in std_ulogic; + xu_iu_ex5_br_hist : in std_ulogic_vector(0 to 1); + xu_iu_ex5_br_taken : in std_ulogic; + xu_iu_ex5_bclr : in std_ulogic; + xu_iu_ex5_getNIA : in std_ulogic; + xu_iu_ex5_lk : in std_ulogic; + xu_iu_ex5_bh : in std_ulogic_vector(0 to 1); + xu_iu_ex5_gshare : in std_ulogic_vector(0 to 3); + + xu_iu_iu3_flush_tid : in std_ulogic_vector(0 to 3); + xu_iu_iu4_flush_tid : in std_ulogic_vector(0 to 3); + xu_iu_iu5_flush_tid : in std_ulogic_vector(0 to 3); + xu_iu_ex5_flush_tid : in std_ulogic_vector(0 to 3); + ib_ic_iu5_redirect_tid : in std_ulogic_vector(0 to 3); + uc_flush_tid : in std_ulogic_vector(0 to 3); + + spr_bp_config : in std_ulogic_vector(0 to 3); + spr_bp_gshare_mask : in std_ulogic_vector(0 to 3); + + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + an_ac_scan_dis_dc_b : in std_ulogic; + pc_iu_sg_2 : in std_ulogic; + pc_iu_func_sl_thold_2 : in std_ulogic; + clkoff_b : in std_ulogic; + tc_ac_ccflush_dc : in std_ulogic; + delay_lclkr : in std_ulogic; + mpw1_b : in std_ulogic; + scan_in : in std_ulogic_vector(0 to 1); + scan_out : out std_ulogic_vector(0 to 1) + +); + +-- synopsys translate_off + + +-- synopsys translate_on + +end iuq_bp; +architecture iuq_bp of iuq_bp is + + + +constant ic_bp_iu1_tid_offset : natural := 0; +constant gshare_t0_offset : natural := ic_bp_iu1_tid_offset + 4; +constant gshare_t1_offset : natural := gshare_t0_offset + 4; +constant gshare_t2_offset : natural := gshare_t1_offset + 4; +constant gshare_t3_offset : natural := gshare_t2_offset + 4; +constant cp_gshare_t0_offset : natural := gshare_t3_offset + 4; +constant cp_gshare_t1_offset : natural := cp_gshare_t0_offset + 4; +constant cp_gshare_t2_offset : natural := cp_gshare_t1_offset + 4; +constant cp_gshare_t3_offset : natural := cp_gshare_t2_offset + 4; +constant iu2_gshare_offset : natural := cp_gshare_t3_offset + 4; +constant iu3_gshare_offset : natural := iu2_gshare_offset + 4; +constant iu4_bh_offset : natural := iu3_gshare_offset + 4; +constant iu4_lk_offset : natural := iu4_bh_offset + 2; +constant iu4_aa_offset : natural := iu4_lk_offset + 1; +constant iu4_b_offset : natural := iu4_aa_offset + 1; +constant iu4_opcode_offset : natural := iu4_b_offset + 1; +constant iu4_excode_offset : natural := iu4_opcode_offset + 6; +constant iu4_bo_offset : natural := iu4_excode_offset + 10; +constant iu4_bi_offset : natural := iu4_bo_offset + 5; +constant iu4_tar_offset : natural := iu4_bi_offset + 5; +constant iu4_ifar_offset : natural := iu4_tar_offset + 24; +constant iu4_ifar_pri_offset : natural := iu4_ifar_offset + EFF_IFAR'length; +constant iu4_pr_taken_offset : natural := iu4_ifar_pri_offset + 2; +constant iu4_tid_offset : natural := iu4_pr_taken_offset + 4; +constant iu4_t0_val_offset : natural := iu4_tid_offset + 4; +constant iu4_t1_val_offset : natural := iu4_t0_val_offset + 4; +constant iu4_t2_val_offset : natural := iu4_t1_val_offset + 4; +constant iu4_t3_val_offset : natural := iu4_t2_val_offset + 4; +constant iu4_0_instr_offset : natural := iu4_t3_val_offset + 4; +constant iu4_1_instr_offset : natural := iu4_0_instr_offset + 12; +constant iu4_2_instr_offset : natural := iu4_1_instr_offset + 44; +constant iu4_3_instr_offset : natural := iu4_2_instr_offset + 44; +constant iu5_redirect_ifar_offset : natural := iu4_3_instr_offset + 44; +constant iu5_redirect_tid_offset : natural := iu5_redirect_ifar_offset + EFF_IFAR'length; +constant iu5_hold_tid_offset : natural := iu5_redirect_tid_offset + 4; +constant iu5_ls_push_offset : natural := iu5_hold_tid_offset + 4; +constant iu5_ls_pop_offset : natural := iu5_ls_push_offset + 4; +constant iu5_ifar_offset : natural := iu5_ls_pop_offset + 4; +constant scan_right0 : natural := iu5_ifar_offset + EFF_IFAR'length - 1; + +constant iu6_ls_t0_ptr_offset : natural := 0; +constant iu6_ls_t1_ptr_offset : natural := iu6_ls_t0_ptr_offset + 4; +constant iu6_ls_t2_ptr_offset : natural := iu6_ls_t1_ptr_offset + 4; +constant iu6_ls_t3_ptr_offset : natural := iu6_ls_t2_ptr_offset + 4; +constant iu6_ls_t00_offset : natural := iu6_ls_t3_ptr_offset + 4; +constant iu6_ls_t01_offset : natural := iu6_ls_t00_offset + EFF_IFAR'length; +constant iu6_ls_t02_offset : natural := iu6_ls_t01_offset + EFF_IFAR'length; +constant iu6_ls_t03_offset : natural := iu6_ls_t02_offset + EFF_IFAR'length; +constant iu6_ls_t10_offset : natural := iu6_ls_t03_offset + EFF_IFAR'length; +constant iu6_ls_t11_offset : natural := iu6_ls_t10_offset + EFF_IFAR'length; +constant iu6_ls_t12_offset : natural := iu6_ls_t11_offset + EFF_IFAR'length; +constant iu6_ls_t13_offset : natural := iu6_ls_t12_offset + EFF_IFAR'length; +constant iu6_ls_t20_offset : natural := iu6_ls_t13_offset + EFF_IFAR'length; +constant iu6_ls_t21_offset : natural := iu6_ls_t20_offset + EFF_IFAR'length; +constant iu6_ls_t22_offset : natural := iu6_ls_t21_offset + EFF_IFAR'length; +constant iu6_ls_t23_offset : natural := iu6_ls_t22_offset + EFF_IFAR'length; +constant iu6_ls_t30_offset : natural := iu6_ls_t23_offset + EFF_IFAR'length; +constant iu6_ls_t31_offset : natural := iu6_ls_t30_offset + EFF_IFAR'length; +constant iu6_ls_t32_offset : natural := iu6_ls_t31_offset + EFF_IFAR'length; +constant iu6_ls_t33_offset : natural := iu6_ls_t32_offset + EFF_IFAR'length; +constant ex6_val_offset : natural := iu6_ls_t33_offset + EFF_IFAR'length; +constant ex6_ifar_offset : natural := ex6_val_offset + 1; +constant ex6_tid_offset : natural := ex6_ifar_offset + EFF_IFAR'length; +constant ex6_br_update_offset : natural := ex6_tid_offset + 4; +constant ex6_br_hist_offset : natural := ex6_br_update_offset + 1; +constant ex6_br_taken_offset : natural := ex6_br_hist_offset + 2; +constant ex6_bclr_offset : natural := ex6_br_taken_offset + 1; +constant ex6_lk_offset : natural := ex6_bclr_offset + 1; +constant ex6_gshare_offset : natural := ex6_lk_offset + 1; +constant ex6_ls_push_offset : natural := ex6_gshare_offset + 4; +constant ex6_ls_pop_offset : natural := ex6_ls_push_offset + 4; +constant ex6_flush_tid_offset : natural := ex6_ls_pop_offset + 4; +constant ex7_ls_t0_ptr_offset : natural := ex6_flush_tid_offset + 4; +constant ex7_ls_t1_ptr_offset : natural := ex7_ls_t0_ptr_offset + 4; +constant ex7_ls_t2_ptr_offset : natural := ex7_ls_t1_ptr_offset + 4; +constant ex7_ls_t3_ptr_offset : natural := ex7_ls_t2_ptr_offset + 4; +constant bp_config_offset : natural := ex7_ls_t3_ptr_offset + 4; +constant gshare_mask_offset : natural := bp_config_offset + 4; +constant dft_offset : natural := gshare_mask_offset + 4; +constant spare_offset : natural := dft_offset + 1; +constant scan_right1 : natural := spare_offset + 12 - 1; + +signal spare_l2 : std_ulogic_vector(0 to 11); + + +signal bp_dy_en : std_ulogic; +signal bp_st_en : std_ulogic; +signal bp_ti_en : std_ulogic; +signal bp_gs_en : std_ulogic; + +signal bp_config_d : std_ulogic_vector(0 to 3); +signal bp_config_q : std_ulogic_vector(0 to 3); + +signal iu1_bh_ti0gs1_rd_addr : std_ulogic_vector(0 to 7); +signal iu1_bh_ti1gs1_rd_addr : std_ulogic_vector(0 to 7); +signal iu1_gshare : std_ulogic_vector(0 to 3); +signal iu1_tid_enc : std_ulogic_vector(0 to 1); + +signal ex6_bh_ti0gs1_wr_addr : std_ulogic_vector(0 to 7); +signal ex6_bh_ti1gs1_wr_addr : std_ulogic_vector(0 to 7); +signal ex6_gshare : std_ulogic_vector(0 to 3); +signal ex6_tid_enc : std_ulogic_vector(0 to 1); + +signal gshare_act : std_ulogic_vector(0 to 3); +signal gshare_taken : std_ulogic_vector(0 to 3); + +signal gshare_t0_shift1 : std_ulogic_vector(0 to 4); +signal gshare_t0_shift2 : std_ulogic_vector(0 to 4); +signal gshare_t0_shift3 : std_ulogic_vector(0 to 4); +signal gshare_t0_shift4 : std_ulogic_vector(1 to 4); +signal gshare_t0_shift : std_ulogic_vector(1 to 4); + +signal gshare_t1_shift1 : std_ulogic_vector(0 to 4); +signal gshare_t1_shift2 : std_ulogic_vector(0 to 4); +signal gshare_t1_shift3 : std_ulogic_vector(0 to 4); +signal gshare_t1_shift4 : std_ulogic_vector(1 to 4); +signal gshare_t1_shift : std_ulogic_vector(1 to 4); + +signal gshare_t2_shift1 : std_ulogic_vector(0 to 4); +signal gshare_t2_shift2 : std_ulogic_vector(0 to 4); +signal gshare_t2_shift3 : std_ulogic_vector(0 to 4); +signal gshare_t2_shift4 : std_ulogic_vector(1 to 4); +signal gshare_t2_shift : std_ulogic_vector(1 to 4); + +signal gshare_t3_shift1 : std_ulogic_vector(0 to 4); +signal gshare_t3_shift2 : std_ulogic_vector(0 to 4); +signal gshare_t3_shift3 : std_ulogic_vector(0 to 4); +signal gshare_t3_shift4 : std_ulogic_vector(1 to 4); +signal gshare_t3_shift : std_ulogic_vector(1 to 4); + +signal cp_gshare_act : std_ulogic_vector(0 to 3); +signal cp_gshare_shift : std_ulogic_vector(0 to 3); +signal cp_gshare_taken : std_ulogic; +signal cp_gshare_t0_d : std_ulogic_vector(0 to 3); +signal cp_gshare_t0_q : std_ulogic_vector(0 to 3); +signal cp_gshare_t1_d : std_ulogic_vector(0 to 3); +signal cp_gshare_t1_q : std_ulogic_vector(0 to 3); +signal cp_gshare_t2_d : std_ulogic_vector(0 to 3); +signal cp_gshare_t2_q : std_ulogic_vector(0 to 3); +signal cp_gshare_t3_d : std_ulogic_vector(0 to 3); +signal cp_gshare_t3_q : std_ulogic_vector(0 to 3); + +signal gshare_t0_d : std_ulogic_vector(0 to 3); +signal gshare_t0_q : std_ulogic_vector(0 to 3); +signal gshare_t1_d : std_ulogic_vector(0 to 3); +signal gshare_t1_q : std_ulogic_vector(0 to 3); +signal gshare_t2_d : std_ulogic_vector(0 to 3); +signal gshare_t2_q : std_ulogic_vector(0 to 3); +signal gshare_t3_d : std_ulogic_vector(0 to 3); +signal gshare_t3_q : std_ulogic_vector(0 to 3); + +signal gshare_mask_d : std_ulogic_vector(0 to 3); +signal gshare_mask_q : std_ulogic_vector(0 to 3); + +signal iu2_gshare_d : std_ulogic_vector(0 to 3); +signal iu2_gshare_q : std_ulogic_vector(0 to 3); +signal iu3_gshare_d : std_ulogic_vector(0 to 3); +signal iu3_gshare_q : std_ulogic_vector(0 to 3); + + + +signal ic_bp_iu1_tid_d : std_ulogic_vector(0 to 3); +signal ic_bp_iu1_tid_q : std_ulogic_vector(0 to 3); + +signal iu3_0_br_hist : std_ulogic_vector(0 to 1); +signal iu3_1_br_hist : std_ulogic_vector(0 to 1); +signal iu3_2_br_hist : std_ulogic_vector(0 to 1); +signal iu3_3_br_hist : std_ulogic_vector(0 to 1); + +signal iu3_br_val : std_ulogic_vector(0 to 3); +signal iu3_br_hard : std_ulogic_vector(0 to 3); +signal iu3_hint_val : std_ulogic_vector(0 to 3); +signal iu3_hint : std_ulogic_vector(0 to 3); +signal iu3_br_hist0 : std_ulogic_vector(0 to 3); +signal iu3_br_hist1 : std_ulogic_vector(0 to 3); + +signal iu3_br_update : std_ulogic_vector(0 to 3); +signal iu3_br_dynamic : std_ulogic_vector(0 to 3); +signal iu3_br_static : std_ulogic_vector(0 to 3); +signal iu3_br_pred : std_ulogic_vector(0 to 3); + +signal iu3_instr_pri : std_ulogic_vector(0 to 31); +signal iu3_instr_val : std_ulogic_vector(0 to 3); + + +signal iu4_b_d : std_ulogic; +signal iu4_b_q : std_ulogic; +signal iu4_bd : EFF_IFAR; +signal iu4_li : EFF_IFAR; + +signal iu3_flush_tid : std_ulogic_vector(0 to 3); + +signal iu4_act : std_ulogic; +signal iu4_instr_act : std_ulogic_vector(0 to 3); + +signal iu4_br_update : std_ulogic_vector(0 to 3); +signal iu4_br_pred : std_ulogic_vector(0 to 3); + +signal iu4_bh_d : std_ulogic_vector(0 to 1); +signal iu4_bh_q : std_ulogic_vector(0 to 1); +signal iu4_lk_d : std_ulogic; +signal iu4_lk_q : std_ulogic; +signal iu4_aa_d : std_ulogic; +signal iu4_aa_q : std_ulogic; + + +signal iu4_opcode_d : std_ulogic_vector(0 to 5); +signal iu4_opcode_q : std_ulogic_vector(0 to 5); +signal iu4_excode_d : std_ulogic_vector(21 to 30); +signal iu4_excode_q : std_ulogic_vector(21 to 30); +signal iu4_bclr : std_ulogic; +signal iu4_bcctr : std_ulogic; + +signal iu4_bo_d : std_ulogic_vector(6 to 10); +signal iu4_bo_q : std_ulogic_vector(6 to 10); +signal iu4_bi_d : std_ulogic_vector(11 to 15); +signal iu4_bi_q : std_ulogic_vector(11 to 15); +signal iu4_getNIA : std_ulogic; + +signal iu4_tar_d : std_ulogic_vector(6 to 29); +signal iu4_tar_q : std_ulogic_vector(6 to 29); +signal iu4_abs : EFF_IFAR; + +signal iu4_ifar_d : EFF_IFAR; +signal iu4_ifar_q : EFF_IFAR; +signal iu4_ifar_pri_d : std_ulogic_vector(60 to 61); +signal iu4_ifar_pri_q : std_ulogic_vector(60 to 61); + +signal iu4_off : EFF_IFAR; + +signal iu4_bta : EFF_IFAR; +signal iu4_lnk : EFF_IFAR; + +signal iu4_pr_taken_d : std_ulogic_vector(0 to 3); +signal iu4_pr_taken_q : std_ulogic_vector(0 to 3); + +signal iu4_tid_d : std_ulogic_vector(0 to 3); +signal iu4_tid_q : std_ulogic_vector(0 to 3); + + +signal iu4_t0_val_d : std_ulogic_vector(0 to 3); +signal iu4_t0_val_q : std_ulogic_vector(0 to 3); +signal iu4_t1_val_d : std_ulogic_vector(0 to 3); +signal iu4_t1_val_q : std_ulogic_vector(0 to 3); +signal iu4_t2_val_d : std_ulogic_vector(0 to 3); +signal iu4_t2_val_q : std_ulogic_vector(0 to 3); +signal iu4_t3_val_d : std_ulogic_vector(0 to 3); +signal iu4_t3_val_q : std_ulogic_vector(0 to 3); + + +signal iu4_0_instr_d : std_ulogic_vector(0 to 43); +signal iu4_0_instr_q : std_ulogic_vector(32 to 43); +signal iu4_1_instr_d : std_ulogic_vector(0 to 43); +signal iu4_1_instr_q : std_ulogic_vector(0 to 43); +signal iu4_2_instr_d : std_ulogic_vector(0 to 43); +signal iu4_2_instr_q : std_ulogic_vector(0 to 43); +signal iu4_3_instr_d : std_ulogic_vector(0 to 43); +signal iu4_3_instr_q : std_ulogic_vector(0 to 43); + +signal iu4_flush_tid : std_ulogic_vector(0 to 3); +signal iu4_redirect_tid : std_ulogic_vector(0 to 3); + + + + +signal iu5_flush_tid : std_ulogic_vector(0 to 3); + +signal iu5_redirect_ifar_d : EFF_IFAR; +signal iu5_redirect_ifar_q : EFF_IFAR; +signal iu5_redirect_tid_d : std_ulogic_vector(0 to 3); +signal iu5_redirect_tid_q : std_ulogic_vector(0 to 3); +signal iu5_redirect_act : std_ulogic; + +signal iu5_hold_tid_d : std_ulogic_vector(0 to 3); +signal iu5_hold_tid_q : std_ulogic_vector(0 to 3); + +signal iu5_act : std_ulogic; + +signal iu5_ls_push_d : std_ulogic_vector(0 to 3); +signal iu5_ls_push_q : std_ulogic_vector(0 to 3); +signal iu5_ls_pop_d : std_ulogic_vector(0 to 3); +signal iu5_ls_pop_q : std_ulogic_vector(0 to 3); + +signal iu5_ifar_d : EFF_IFAR; +signal iu5_ifar_q : EFF_IFAR; + +signal ex6_ifar_d : EFF_IFAR; +signal ex6_ifar_q : EFF_IFAR; +signal ex6_tid_d : std_ulogic_vector(0 to 3); +signal ex6_tid_q : std_ulogic_vector(0 to 3); +signal ex6_val_d : std_ulogic; +signal ex6_val_q : std_ulogic; +signal ex6_br_update_d : std_ulogic; +signal ex6_br_update_q : std_ulogic; +signal ex6_br_hist_d : std_ulogic_vector(0 to 1); +signal ex6_br_hist_q : std_ulogic_vector(0 to 1); +signal ex6_br_taken_d : std_ulogic; +signal ex6_br_taken_q : std_ulogic; +signal ex6_bclr_d : std_ulogic; +signal ex6_bclr_q : std_ulogic; +signal ex6_getNIA_d : std_ulogic; +signal ex6_lk_d : std_ulogic; +signal ex6_lk_q : std_ulogic; +signal ex6_bh_d : std_ulogic_vector(0 to 1); +signal ex6_gshare_d : std_ulogic_vector(0 to 3); +signal ex6_gshare_q : std_ulogic_vector(0 to 3); + +signal ex6_ls_push_d : std_ulogic_vector(0 to 3); +signal ex6_ls_push_q : std_ulogic_vector(0 to 3); +signal ex6_ls_pop_d : std_ulogic_vector(0 to 3); +signal ex6_ls_pop_q : std_ulogic_vector(0 to 3); + +signal ex7_ls_t0_ptr_d : std_ulogic_vector(0 to 3); +signal ex7_ls_t0_ptr_q : std_ulogic_vector(0 to 3); +signal ex7_ls_t1_ptr_d : std_ulogic_vector(0 to 3); +signal ex7_ls_t1_ptr_q : std_ulogic_vector(0 to 3); +signal ex7_ls_t2_ptr_d : std_ulogic_vector(0 to 3); +signal ex7_ls_t2_ptr_q : std_ulogic_vector(0 to 3); +signal ex7_ls_t3_ptr_d : std_ulogic_vector(0 to 3); +signal ex7_ls_t3_ptr_q : std_ulogic_vector(0 to 3); +signal ex7_ls_ptr_act : std_ulogic_vector(0 to 3); + +signal ex6_flush_tid_d : std_ulogic_vector(0 to 3); +signal ex6_flush_tid_q : std_ulogic_vector(0 to 3); + +signal ex6_br_hist_dec : std_ulogic; +signal ex6_br_hist_inc : std_ulogic; + +signal ex6_flush : std_ulogic; +signal ex6_val : std_ulogic; + +signal iu6_ls_t0_ptr_d : std_ulogic_vector(0 to 3); +signal iu6_ls_t0_ptr_q : std_ulogic_vector(0 to 3); +signal iu6_ls_t1_ptr_d : std_ulogic_vector(0 to 3); +signal iu6_ls_t1_ptr_q : std_ulogic_vector(0 to 3); +signal iu6_ls_t2_ptr_d : std_ulogic_vector(0 to 3); +signal iu6_ls_t2_ptr_q : std_ulogic_vector(0 to 3); +signal iu6_ls_t3_ptr_d : std_ulogic_vector(0 to 3); +signal iu6_ls_t3_ptr_q : std_ulogic_vector(0 to 3); +signal iu6_ls_ptr_act : std_ulogic_vector(0 to 3); + +signal iu5_ls_update : std_ulogic_vector(0 to 3); +signal ex6_ls_update : std_ulogic_vector(0 to 3); +signal ex6_repair : std_ulogic_vector(0 to 3); + +signal iu5_nia : EFF_IFAR; +signal ex6_nia : EFF_IFAR; + +signal iu6_ls_t00_d : EFF_IFAR; +signal iu6_ls_t00_q : EFF_IFAR; +signal iu6_ls_t01_d : EFF_IFAR; +signal iu6_ls_t01_q : EFF_IFAR; +signal iu6_ls_t02_d : EFF_IFAR; +signal iu6_ls_t02_q : EFF_IFAR; +signal iu6_ls_t03_d : EFF_IFAR; +signal iu6_ls_t03_q : EFF_IFAR; +signal iu6_ls_t0_act : std_ulogic_vector(0 to 3); + +signal iu6_ls_t10_d : EFF_IFAR; +signal iu6_ls_t10_q : EFF_IFAR; +signal iu6_ls_t11_d : EFF_IFAR; +signal iu6_ls_t11_q : EFF_IFAR; +signal iu6_ls_t12_d : EFF_IFAR; +signal iu6_ls_t12_q : EFF_IFAR; +signal iu6_ls_t13_d : EFF_IFAR; +signal iu6_ls_t13_q : EFF_IFAR; +signal iu6_ls_t1_act : std_ulogic_vector(0 to 3); + +signal iu6_ls_t20_d : EFF_IFAR; +signal iu6_ls_t20_q : EFF_IFAR; +signal iu6_ls_t21_d : EFF_IFAR; +signal iu6_ls_t21_q : EFF_IFAR; +signal iu6_ls_t22_d : EFF_IFAR; +signal iu6_ls_t22_q : EFF_IFAR; +signal iu6_ls_t23_d : EFF_IFAR; +signal iu6_ls_t23_q : EFF_IFAR; +signal iu6_ls_t2_act : std_ulogic_vector(0 to 3); + +signal iu6_ls_t30_d : EFF_IFAR; +signal iu6_ls_t30_q : EFF_IFAR; +signal iu6_ls_t31_d : EFF_IFAR; +signal iu6_ls_t31_q : EFF_IFAR; +signal iu6_ls_t32_d : EFF_IFAR; +signal iu6_ls_t32_q : EFF_IFAR; +signal iu6_ls_t33_d : EFF_IFAR; +signal iu6_ls_t33_q : EFF_IFAR; +signal iu6_ls_t3_act : std_ulogic_vector(0 to 3); + +signal tiup : std_ulogic; + + +signal pc_iu_func_sl_thold_1 : std_ulogic; +signal pc_iu_func_sl_thold_0 : std_ulogic; +signal pc_iu_func_sl_thold_0_b : std_ulogic; +signal pc_iu_sg_1 : std_ulogic; +signal pc_iu_sg_0 : std_ulogic; +signal forcee : std_ulogic; + +signal dclk : std_ulogic; +signal lclk : clk_logic; +signal dft_q : std_ulogic_vector(0 to 0); + +signal siv0 : std_ulogic_vector(0 to scan_right0); +signal sov0 : std_ulogic_vector(0 to scan_right0); + +signal siv1 : std_ulogic_vector(0 to scan_right1); +signal sov1 : std_ulogic_vector(0 to scan_right1); + +signal act_dis : std_ulogic; +signal d_mode : std_ulogic; +signal mpw2_b : std_ulogic; + + +begin + + +tiup <= '1'; + +act_dis <= '0'; +d_mode <= '0'; +mpw2_b <= '1'; + + +bp_config_d(0 to 3) <= spr_bp_config(0 to 3); + +bp_dy_en <= bp_config_q(0); +bp_st_en <= bp_config_q(1); +bp_ti_en <= bp_config_q(2); +bp_gs_en <= bp_config_q(3); + + +ex6_flush_tid_d <= xu_iu_ex5_flush_tid; + +ex6_ifar_d <= xu_iu_ex5_ifar; +ex6_tid_d <= xu_iu_ex5_tid; +ex6_val_d <= xu_iu_ex5_val; +ex6_br_update_d <= xu_iu_ex5_br_update; +ex6_br_hist_d <= xu_iu_ex5_br_hist; +ex6_br_taken_d <= xu_iu_ex5_br_taken; +ex6_bclr_d <= xu_iu_ex5_bclr; +ex6_getNIA_d <= xu_iu_ex5_getNIA; +ex6_lk_d <= xu_iu_ex5_lk; +ex6_bh_d <= xu_iu_ex5_bh; +ex6_gshare_d <= xu_iu_ex5_gshare; + + +iu1_bh_rd_act <= ic_bp_iu1_val; + + + +iu1_bh_ti0gs1_rd_addr(0 to 7) <= (ic_bp_iu1_ifar(52 to 55) xor iu1_gshare(0 to 3)) & ic_bp_iu1_ifar(56 to 59); +iu1_bh_ti1gs1_rd_addr(0 to 7) <= iu1_tid_enc(0 to 1) & (ic_bp_iu1_ifar(54 to 57) xor iu1_gshare(0 to 3)) & ic_bp_iu1_ifar(58 to 59); + +iu1_bh_rd_addr(0 to 7) <= gate(iu1_bh_ti0gs1_rd_addr(0 to 7), bp_ti_en = '0') or + gate(iu1_bh_ti1gs1_rd_addr(0 to 7), bp_ti_en = '1') ; + +ic_bp_iu1_tid_d <= ic_bp_iu1_tid; + +iu1_gshare(0 to 3) <= gate(gshare_t0_q(0 to 3), bp_gs_en and ic_bp_iu1_tid_q(0)) or + gate(gshare_t1_q(0 to 3), bp_gs_en and ic_bp_iu1_tid_q(1)) or + gate(gshare_t2_q(0 to 3), bp_gs_en and ic_bp_iu1_tid_q(2)) or + gate(gshare_t3_q(0 to 3), bp_gs_en and ic_bp_iu1_tid_q(3)); + +iu1_tid_enc(0 to 1) <= gate("00", ic_bp_iu1_tid_q(0)) or + gate("01", ic_bp_iu1_tid_q(1)) or + gate("10", ic_bp_iu1_tid_q(2)) or + gate("11", ic_bp_iu1_tid_q(3)); + +iu2_gshare_d(0 to 3) <= iu1_gshare(0 to 3); +iu3_gshare_d(0 to 3) <= iu2_gshare_q(0 to 3); + + + + +ex6_bh_ti0gs1_wr_addr(0 to 7) <= (ex6_ifar_q(52 to 55) xor ex6_gshare(0 to 3)) & ex6_ifar_q(56 to 59); +ex6_bh_ti1gs1_wr_addr(0 to 7) <= ex6_tid_enc(0 to 1) & (ex6_ifar_q(54 to 57) xor ex6_gshare(0 to 3)) & ex6_ifar_q(58 to 59); + +ex6_bh_wr_addr(0 to 7) <= gate(ex6_bh_ti0gs1_wr_addr(0 to 7), bp_ti_en = '0') or + gate(ex6_bh_ti1gs1_wr_addr(0 to 7), bp_ti_en = '1') ; + + +ex6_gshare(0 to 3) <= ex6_gshare_q(0 to 3); + +ex6_tid_enc(0 to 1) <= gate("00", ex6_tid_q(0)) or + gate("01", ex6_tid_q(1)) or + gate("10", ex6_tid_q(2)) or + gate("11", ex6_tid_q(3)); + + +ex6_flush <= or_reduce(ex6_tid_q(0 to 3) and ex6_flush_tid_q(0 to 3)); +ex6_val <= not ex6_flush; + +ex6_br_hist_dec <= ex6_val and ex6_val_q = '1' and ex6_br_update_q = '1' and ex6_br_taken_q = '0' and ex6_br_hist_q(0 to 1) /= "00"; +ex6_br_hist_inc <= ex6_val and ex6_val_q = '1' and ex6_br_update_q = '1' and ex6_br_taken_q = '1' and ex6_br_hist_q(0 to 1) /= "11"; + +ex6_bh_wr_data(0 to 1) <= ex6_br_hist_q(0 to 1) + 1 when ex6_br_taken_q = '1' else + ex6_br_hist_q(0 to 1) - 1; + +ex6_bh_wr_act(0) <= (ex6_br_hist_dec or ex6_br_hist_inc) and ex6_ifar_q(60 to 61) = "00"; +ex6_bh_wr_act(1) <= (ex6_br_hist_dec or ex6_br_hist_inc) and ex6_ifar_q(60 to 61) = "01"; +ex6_bh_wr_act(2) <= (ex6_br_hist_dec or ex6_br_hist_inc) and ex6_ifar_q(60 to 61) = "10"; +ex6_bh_wr_act(3) <= (ex6_br_hist_dec or ex6_br_hist_inc) and ex6_ifar_q(60 to 61) = "11"; + + + +gshare_mask_d(0 to 3) <= spr_bp_gshare_mask(0 to 3); + + + + + + + +gshare_t0_shift1(0 to 4) <= "01000" when (iu4_t0_val_q(0) and iu4_br_update(0)) = '1' else "10000"; +gshare_t0_shift2(0 to 4) <= '0' & gshare_t0_shift1(0 to 3) when (iu4_t0_val_q(1) and iu4_br_update(1)) = '1' else gshare_t0_shift1(0 to 4); +gshare_t0_shift3(0 to 4) <= '0' & gshare_t0_shift2(0 to 3) when (iu4_t0_val_q(2) and iu4_br_update(2)) = '1' else gshare_t0_shift2(0 to 4); +gshare_t0_shift4(1 to 4) <= gshare_t0_shift3(0 to 3) when (iu4_t0_val_q(3) and iu4_br_update(3)) = '1' else gshare_t0_shift3(1 to 4); +gshare_t0_shift(1 to 4) <= gate( gshare_t0_shift4(1 to 4), not iu4_flush_tid(0)); + +gshare_t1_shift1(0 to 4) <= "01000" when (iu4_t1_val_q(0) and iu4_br_update(0)) = '1' else "10000"; +gshare_t1_shift2(0 to 4) <= '0' & gshare_t1_shift1(0 to 3) when (iu4_t1_val_q(1) and iu4_br_update(1)) = '1' else gshare_t1_shift1(0 to 4); +gshare_t1_shift3(0 to 4) <= '0' & gshare_t1_shift2(0 to 3) when (iu4_t1_val_q(2) and iu4_br_update(2)) = '1' else gshare_t1_shift2(0 to 4); +gshare_t1_shift4(1 to 4) <= gshare_t1_shift3(0 to 3) when (iu4_t1_val_q(3) and iu4_br_update(3)) = '1' else gshare_t1_shift3(1 to 4); +gshare_t1_shift(1 to 4) <= gate( gshare_t1_shift4(1 to 4), not iu4_flush_tid(1)); + +gshare_t2_shift1(0 to 4) <= "01000" when (iu4_t2_val_q(0) and iu4_br_update(0)) = '1' else "10000"; +gshare_t2_shift2(0 to 4) <= '0' & gshare_t2_shift1(0 to 3) when (iu4_t2_val_q(1) and iu4_br_update(1)) = '1' else gshare_t2_shift1(0 to 4); +gshare_t2_shift3(0 to 4) <= '0' & gshare_t2_shift2(0 to 3) when (iu4_t2_val_q(2) and iu4_br_update(2)) = '1' else gshare_t2_shift2(0 to 4); +gshare_t2_shift4(1 to 4) <= gshare_t2_shift3(0 to 3) when (iu4_t2_val_q(3) and iu4_br_update(3)) = '1' else gshare_t2_shift3(1 to 4); +gshare_t2_shift(1 to 4) <= gate( gshare_t2_shift4(1 to 4), not iu4_flush_tid(2)); + +gshare_t3_shift1(0 to 4) <= "01000" when (iu4_t3_val_q(0) and iu4_br_update(0)) = '1' else "10000"; +gshare_t3_shift2(0 to 4) <= '0' & gshare_t3_shift1(0 to 3) when (iu4_t3_val_q(1) and iu4_br_update(1)) = '1' else gshare_t3_shift1(0 to 4); +gshare_t3_shift3(0 to 4) <= '0' & gshare_t3_shift2(0 to 3) when (iu4_t3_val_q(2) and iu4_br_update(2)) = '1' else gshare_t3_shift2(0 to 4); +gshare_t3_shift4(1 to 4) <= gshare_t3_shift3(0 to 3) when (iu4_t3_val_q(3) and iu4_br_update(3)) = '1' else gshare_t3_shift3(1 to 4); +gshare_t3_shift(1 to 4) <= gate( gshare_t3_shift4(1 to 4), not iu4_flush_tid(3)); + +gshare_taken(0) <= or_reduce(iu4_t0_val_q(0 to 3) and iu4_br_update(0 to 3) and iu4_br_pred(0 to 3)); +gshare_taken(1) <= or_reduce(iu4_t1_val_q(0 to 3) and iu4_br_update(0 to 3) and iu4_br_pred(0 to 3)); +gshare_taken(2) <= or_reduce(iu4_t2_val_q(0 to 3) and iu4_br_update(0 to 3) and iu4_br_pred(0 to 3)); +gshare_taken(3) <= or_reduce(iu4_t3_val_q(0 to 3) and iu4_br_update(0 to 3) and iu4_br_pred(0 to 3)); + + + + + +gshare_t0_d(0 to 3) <= cp_gshare_t0_d(0 to 3) when ex6_repair(0) = '1' else + (gshare_taken(0) & "000" ) and gshare_mask_q(0 to 3) when gshare_t0_shift(4) = '1' else + (gshare_taken(0) & "00" & gshare_t0_q(0) ) and gshare_mask_q(0 to 3) when gshare_t0_shift(3) = '1' else + (gshare_taken(0) & '0' & gshare_t0_q(0 to 1)) and gshare_mask_q(0 to 3) when gshare_t0_shift(2) = '1' else + (gshare_taken(0) & gshare_t0_q(0 to 2)) and gshare_mask_q(0 to 3) when gshare_t0_shift(1) = '1' else + gshare_t0_q(0 to 3); + +gshare_t1_d(0 to 3) <= cp_gshare_t1_d(0 to 3) when ex6_repair(1) = '1' else + (gshare_taken(1) & "000" ) and gshare_mask_q(0 to 3) when gshare_t1_shift(4) = '1' else + (gshare_taken(1) & "00" & gshare_t1_q(0) ) and gshare_mask_q(0 to 3) when gshare_t1_shift(3) = '1' else + (gshare_taken(1) & '0' & gshare_t1_q(0 to 1)) and gshare_mask_q(0 to 3) when gshare_t1_shift(2) = '1' else + (gshare_taken(1) & gshare_t1_q(0 to 2)) and gshare_mask_q(0 to 3) when gshare_t1_shift(1) = '1' else + gshare_t1_q(0 to 3); + +gshare_t2_d(0 to 3) <= cp_gshare_t2_d(0 to 3) when ex6_repair(2) = '1' else + (gshare_taken(2) & "000" ) and gshare_mask_q(0 to 3) when gshare_t2_shift(4) = '1' else + (gshare_taken(2) & "00" & gshare_t2_q(0) ) and gshare_mask_q(0 to 3) when gshare_t2_shift(3) = '1' else + (gshare_taken(2) & '0' & gshare_t2_q(0 to 1)) and gshare_mask_q(0 to 3) when gshare_t2_shift(2) = '1' else + (gshare_taken(2) & gshare_t2_q(0 to 2)) and gshare_mask_q(0 to 3) when gshare_t2_shift(1) = '1' else + gshare_t2_q(0 to 3); +gshare_t3_d(0 to 3) <= cp_gshare_t3_d(0 to 3) when ex6_repair(3) = '1' else + (gshare_taken(3) & "000" ) and gshare_mask_q(0 to 3) when gshare_t3_shift(4) = '1' else + (gshare_taken(3) & "00" & gshare_t3_q(0) ) and gshare_mask_q(0 to 3) when gshare_t3_shift(3) = '1' else + (gshare_taken(3) & '0' & gshare_t3_q(0 to 1)) and gshare_mask_q(0 to 3) when gshare_t3_shift(2) = '1' else + (gshare_taken(3) & gshare_t3_q(0 to 2)) and gshare_mask_q(0 to 3) when gshare_t3_shift(1) = '1' else + gshare_t3_q(0 to 3); + + +gshare_act(0) <= tiup; +gshare_act(1) <= tiup; +gshare_act(2) <= tiup; +gshare_act(3) <= tiup; + + + + +cp_gshare_shift(0 to 3) <= gate(ex6_tid_q(0 to 3) and not ex6_flush_tid_q(0 to 3), ex6_val_q and ex6_br_update_q); +cp_gshare_taken <= ex6_br_taken_q; + +cp_gshare_t0_d(0 to 3) <= (cp_gshare_taken & cp_gshare_t0_q(0 to 2)) and gshare_mask_q(0 to 3) when cp_gshare_shift(0) = '1' else + cp_gshare_t0_q(0 to 3); +cp_gshare_t1_d(0 to 3) <= (cp_gshare_taken & cp_gshare_t1_q(0 to 2)) and gshare_mask_q(0 to 3) when cp_gshare_shift(1) = '1' else + cp_gshare_t1_q(0 to 3); +cp_gshare_t2_d(0 to 3) <= (cp_gshare_taken & cp_gshare_t2_q(0 to 2)) and gshare_mask_q(0 to 3) when cp_gshare_shift(2) = '1' else + cp_gshare_t2_q(0 to 3); +cp_gshare_t3_d(0 to 3) <= (cp_gshare_taken & cp_gshare_t3_q(0 to 2)) and gshare_mask_q(0 to 3) when cp_gshare_shift(3) = '1' else + cp_gshare_t3_q(0 to 3); + + +cp_gshare_act(0 to 3) <= cp_gshare_shift(0 to 3); + + + + + + +with ic_bp_iu3_ifar(60 to 61) select +iu3_0_br_hist <= iu3_3_bh_rd_data(0 to 1) when "11", + iu3_2_bh_rd_data(0 to 1) when "10", + iu3_1_bh_rd_data(0 to 1) when "01", + iu3_0_bh_rd_data(0 to 1) when others; + +with ic_bp_iu3_ifar(60 to 61) select +iu3_1_br_hist <= iu3_3_bh_rd_data(0 to 1) when "10", + iu3_2_bh_rd_data(0 to 1) when "01", + iu3_1_bh_rd_data(0 to 1) when others; + +with ic_bp_iu3_ifar(60 to 61) select +iu3_2_br_hist <= iu3_3_bh_rd_data(0 to 1) when "01", + iu3_2_bh_rd_data(0 to 1) when others; + +iu3_3_br_hist <= iu3_3_bh_rd_data(0 to 1); + + + +iu3_br_val(0 to 3) <= ic_bp_iu3_0_instr(32) & ic_bp_iu3_1_instr(32) & ic_bp_iu3_2_instr(32) & ic_bp_iu3_3_instr(32); +iu3_br_hard(0 to 3) <= ic_bp_iu3_0_instr(33) & ic_bp_iu3_1_instr(33) & ic_bp_iu3_2_instr(33) & ic_bp_iu3_3_instr(33); +iu3_hint_val(0 to 3) <= ic_bp_iu3_0_instr(34) & ic_bp_iu3_1_instr(34) & ic_bp_iu3_2_instr(34) & ic_bp_iu3_3_instr(34); +iu3_hint(0 to 3) <= ic_bp_iu3_0_instr(35) & ic_bp_iu3_1_instr(35) & ic_bp_iu3_2_instr(35) & ic_bp_iu3_3_instr(35); + +iu3_br_hist0(0 to 3) <= iu3_0_br_hist(0) & iu3_1_br_hist(0) & iu3_2_br_hist(0) & iu3_3_br_hist(0); +iu3_br_hist1(0 to 3) <= iu3_0_br_hist(1) & iu3_1_br_hist(1) & iu3_2_br_hist(1) & iu3_3_br_hist(1); + + + + +iu3_br_dynamic(0 to 3) <= gate(not(iu3_br_hard(0 to 3) or iu3_hint_val(0 to 3)), bp_dy_en); +iu3_br_static(0 to 3) <= gate(not(iu3_br_hard(0 to 3) or iu3_hint_val(0 to 3)), bp_st_en and not bp_dy_en); + +iu3_br_pred(0 to 3) <= iu3_br_val(0 to 3) and + (iu3_br_hard(0 to 3) or + (iu3_hint_val(0 to 3) and iu3_hint(0 to 3)) or + (iu3_br_dynamic(0 to 3) and iu3_br_hist0(0 to 3)) or + (iu3_br_static(0 to 3))); + +iu3_br_update(0 to 3) <= iu3_br_val(0 to 3) and iu3_br_dynamic(0 to 3); + + + + + +iu3_instr_pri(0 to 31) <= ic_bp_iu3_0_instr(0 to 31) when iu3_br_pred(0) = '1' else + ic_bp_iu3_1_instr(0 to 31) when iu3_br_pred(1) = '1' else + ic_bp_iu3_2_instr(0 to 31) when iu3_br_pred(2) = '1' else + ic_bp_iu3_3_instr(0 to 31); + +iu4_b_d <= ic_bp_iu3_0_instr(33) when iu3_br_pred(0) = '1' else + ic_bp_iu3_1_instr(33) when iu3_br_pred(1) = '1' else + ic_bp_iu3_2_instr(33) when iu3_br_pred(2) = '1' else + ic_bp_iu3_3_instr(33); + +iu4_ifar_pri_d(60 to 61) <= ic_bp_iu3_ifar(60 to 61) when iu3_br_pred(0) = '1' else + ic_bp_iu3_ifar(60 to 61) + 1 when iu3_br_pred(1) = '1' else + ic_bp_iu3_ifar(60 to 61) + 2 when iu3_br_pred(2) = '1' else + ic_bp_iu3_ifar(60 to 61) + 3; + + + + + +iu4_tar_d(6 to 29) <= iu3_instr_pri(6 to 29); + + +sign_extend: for i in EFF_IFAR'left to 61 generate +begin + bd0:if(i < 48) generate begin iu4_bd(i) <= iu4_tar_q(16); end generate; + bd1:if(i > 47) generate begin iu4_bd(i) <= iu4_tar_q(i - 32); end generate; + li0:if(i < 38) generate begin iu4_li(i) <= iu4_tar_q(6); end generate; + li1:if(i > 37) generate begin iu4_li(i) <= iu4_tar_q(i - 32); end generate; +end generate; + +iu4_bh_d(0 to 1) <= iu3_instr_pri(19 to 20); +iu4_lk_d <= iu3_instr_pri(31); +iu4_aa_d <= iu3_instr_pri(30); + + +iu4_opcode_d(0 to 5) <= iu3_instr_pri(0 to 5); +iu4_excode_d(21 to 30) <= iu3_instr_pri(21 to 30); + +iu4_bclr <= (iu4_opcode_q(0 to 5) = "010011" and iu4_excode_q(21 to 30) = "0000010000") or dft_q(0); +iu4_bcctr <= iu4_opcode_q(0 to 5) = "010011" and iu4_excode_q(21 to 30) = "1000010000"; + +iu4_bo_d( 6 to 10) <= iu3_instr_pri( 6 to 10); +iu4_bi_d(11 to 15) <= iu3_instr_pri(11 to 15); + +iu4_getNIA <= iu4_opcode_q(0 to 5) = "010000" and + iu4_bo_q(6 to 10) = "10100" and + iu4_bi_q(11 to 15) = "11111" and + iu4_bd(EFF_IFAR'left to 61) = 1 and + iu4_aa_q = '0' and + iu4_lk_q = '1' ; + +iu4_pr_taken_d(0) <= ic_bp_iu3_tid(0) and not iu3_flush_tid(0) and or_reduce(iu3_br_pred(0 to 3) and ic_bp_iu3_val(0 to 3)); +iu4_pr_taken_d(1) <= ic_bp_iu3_tid(1) and not iu3_flush_tid(1) and or_reduce(iu3_br_pred(0 to 3) and ic_bp_iu3_val(0 to 3)); +iu4_pr_taken_d(2) <= ic_bp_iu3_tid(2) and not iu3_flush_tid(2) and or_reduce(iu3_br_pred(0 to 3) and ic_bp_iu3_val(0 to 3)); +iu4_pr_taken_d(3) <= ic_bp_iu3_tid(3) and not iu3_flush_tid(3) and or_reduce(iu3_br_pred(0 to 3) and ic_bp_iu3_val(0 to 3)); + + + + + + +iu4_abs(EFF_IFAR'left to 61) <= iu4_li(EFF_IFAR'left to 61) when iu4_b_q = '1' else + iu4_bd(EFF_IFAR'left to 61); + +iu4_off(EFF_IFAR'left to 61) <= iu4_abs(EFF_IFAR'left to 61) + (iu4_ifar_q(EFF_IFAR'left to 59) & iu4_ifar_pri_q(60 to 61)); + +iu4_bta(EFF_IFAR'left to 61) <= iu4_abs(EFF_IFAR'left to 61) when iu4_aa_q = '1' else + iu4_off(EFF_IFAR'left to 61); + + +iu4_act <= ic_bp_iu3_val(0); +iu4_instr_act(0 to 3) <= ic_bp_iu3_val(0 to 3); + +iu4_tid_d(0 to 3) <= ic_bp_iu3_tid(0 to 3); +iu4_ifar_d(EFF_IFAR'left to 61) <= ic_bp_iu3_ifar(EFF_IFAR'left to 61); + + + +iu3_instr_val(0) <= ic_bp_iu3_val(0); +iu3_instr_val(1) <= ic_bp_iu3_val(1) and not iu3_br_pred(0); +iu3_instr_val(2) <= ic_bp_iu3_val(2) and not iu3_br_pred(0) and not iu3_br_pred(1); +iu3_instr_val(3) <= ic_bp_iu3_val(3) and not iu3_br_pred(0) and not iu3_br_pred(1) and not iu3_br_pred(2); + + + +iu4_t0_val_d(0 to 3) <= gate(iu3_instr_val(0 to 3), ic_bp_iu3_tid(0) and not iu3_flush_tid(0)); +iu4_t1_val_d(0 to 3) <= gate(iu3_instr_val(0 to 3), ic_bp_iu3_tid(1) and not iu3_flush_tid(1)); +iu4_t2_val_d(0 to 3) <= gate(iu3_instr_val(0 to 3), ic_bp_iu3_tid(2) and not iu3_flush_tid(2)); +iu4_t3_val_d(0 to 3) <= gate(iu3_instr_val(0 to 3), ic_bp_iu3_tid(3) and not iu3_flush_tid(3)); + + +iu4_0_instr_d(0 to 31) <= ic_bp_iu3_0_instr(0 to 31); +iu4_1_instr_d(0 to 31) <= ic_bp_iu3_1_instr(0 to 31); +iu4_2_instr_d(0 to 31) <= ic_bp_iu3_2_instr(0 to 31); +iu4_3_instr_d(0 to 31) <= ic_bp_iu3_3_instr(0 to 31); + +iu4_0_instr_d(32) <= iu3_br_pred(0); +iu4_1_instr_d(32) <= iu3_br_pred(1); +iu4_2_instr_d(32) <= iu3_br_pred(2); +iu4_3_instr_d(32) <= iu3_br_pred(3); + +iu4_0_instr_d(33) <= iu3_br_hist1(0); +iu4_1_instr_d(33) <= iu3_br_hist1(1); +iu4_2_instr_d(33) <= iu3_br_hist1(2); +iu4_3_instr_d(33) <= iu3_br_hist1(3); + +iu4_0_instr_d(34) <= iu3_br_update(0); +iu4_1_instr_d(34) <= iu3_br_update(1); +iu4_2_instr_d(34) <= iu3_br_update(2); +iu4_3_instr_d(34) <= iu3_br_update(3); + +iu4_0_instr_d(35 to 37) <= ic_bp_iu3_error(0 to 2); +iu4_1_instr_d(35 to 37) <= ic_bp_iu3_error(0 to 2); +iu4_2_instr_d(35 to 37) <= ic_bp_iu3_error(0 to 2); +iu4_3_instr_d(35 to 37) <= ic_bp_iu3_error(0 to 2); + +iu4_0_instr_d(38) <= ic_bp_iu3_2ucode; +iu4_1_instr_d(38) <= ic_bp_iu3_2ucode; +iu4_2_instr_d(38) <= ic_bp_iu3_2ucode; +iu4_3_instr_d(38) <= ic_bp_iu3_2ucode; + +iu4_0_instr_d(39) <= ic_bp_iu3_2ucode_type; +iu4_1_instr_d(39) <= ic_bp_iu3_2ucode_type; +iu4_2_instr_d(39) <= ic_bp_iu3_2ucode_type; +iu4_3_instr_d(39) <= ic_bp_iu3_2ucode_type; + +iu4_0_instr_d(40 to 43) <= iu3_gshare_q(0 to 3); +iu4_1_instr_d(40 to 43) <= iu3_gshare_q(0 to 3); +iu4_2_instr_d(40 to 43) <= iu3_gshare_q(0 to 3); +iu4_3_instr_d(40 to 43) <= iu3_gshare_q(0 to 3); + + +iu4_br_pred(0 to 3) <= iu4_0_instr_q(32) & iu4_1_instr_q(32) & iu4_2_instr_q(32) & iu4_3_instr_q(32); +iu4_br_update(0 to 3) <= iu4_0_instr_q(34) & iu4_1_instr_q(34) & iu4_2_instr_q(34) & iu4_3_instr_q(34); + + + + +iu3_flush_tid(0 to 3) <= xu_iu_iu3_flush_tid(0 to 3) or (0 to 3 => ic_bp_iu3_flush) or iu4_redirect_tid(0 to 3) or + iu5_redirect_tid_q(0 to 3) or ib_ic_iu5_redirect_tid(0 to 3) or uc_flush_tid(0 to 3) ; + + +iu4_flush_tid(0 to 3) <= xu_iu_iu4_flush_tid(0 to 3) or iu5_redirect_tid_q(0 to 3) or ib_ic_iu5_redirect_tid(0 to 3) or uc_flush_tid(0 to 3); + + +iu5_flush_tid(0 to 3) <= xu_iu_iu5_flush_tid(0 to 3) or ib_ic_iu5_redirect_tid(0 to 3) or uc_flush_tid(0 to 3); + + + + +ex6_ls_push_d(0 to 3) <= gate(ex6_tid_d(0 to 3) and not ex6_flush_tid_d(0 to 3), ex6_val_d and ex6_br_taken_d and not ex6_bclr_d and ex6_lk_d and not ex6_getNIA_d); +ex6_ls_pop_d(0 to 3) <= gate(ex6_tid_d(0 to 3) and not ex6_flush_tid_d(0 to 3), ex6_val_d and ex6_br_taken_d and ex6_bclr_d and ex6_bh_d(0 to 1) = "00"); + +ex7_ls_t0_ptr_d(0 to 3) <= ex7_ls_t0_ptr_q(3) & ex7_ls_t0_ptr_q(0 to 2) when ex6_ls_push_q(0) = '1' and ex6_ls_pop_q(0) = '0' else + ex7_ls_t0_ptr_q(1 to 3) & ex7_ls_t0_ptr_q(0) when ex6_ls_push_q(0) = '0' and ex6_ls_pop_q(0) = '1' else + ex7_ls_t0_ptr_q(0 to 3); +ex7_ls_t1_ptr_d(0 to 3) <= ex7_ls_t1_ptr_q(3) & ex7_ls_t1_ptr_q(0 to 2) when ex6_ls_push_q(1) = '1' and ex6_ls_pop_q(1) = '0' else + ex7_ls_t1_ptr_q(1 to 3) & ex7_ls_t1_ptr_q(0) when ex6_ls_push_q(1) = '0' and ex6_ls_pop_q(1) = '1' else + ex7_ls_t1_ptr_q(0 to 3); +ex7_ls_t2_ptr_d(0 to 3) <= ex7_ls_t2_ptr_q(3) & ex7_ls_t2_ptr_q(0 to 2) when ex6_ls_push_q(2) = '1' and ex6_ls_pop_q(2) = '0' else + ex7_ls_t2_ptr_q(1 to 3) & ex7_ls_t2_ptr_q(0) when ex6_ls_push_q(2) = '0' and ex6_ls_pop_q(2) = '1' else + ex7_ls_t2_ptr_q(0 to 3); +ex7_ls_t3_ptr_d(0 to 3) <= ex7_ls_t3_ptr_q(3) & ex7_ls_t3_ptr_q(0 to 2) when ex6_ls_push_q(3) = '1' and ex6_ls_pop_q(3) = '0' else + ex7_ls_t3_ptr_q(1 to 3) & ex7_ls_t3_ptr_q(0) when ex6_ls_push_q(3) = '0' and ex6_ls_pop_q(3) = '1' else + ex7_ls_t3_ptr_q(0 to 3); + +ex7_ls_ptr_act(0 to 3) <= ex6_ls_push_q(0 to 3) xor ex6_ls_pop_q(0 to 3); + + +iu5_ls_push_d(0 to 3) <= gate(iu4_pr_taken_q(0 to 3) and not iu4_flush_tid(0 to 3), not iu4_bclr and iu4_lk_q and not iu4_getNIA); +iu5_ls_pop_d(0 to 3) <= gate(iu4_pr_taken_q(0 to 3) and not iu4_flush_tid(0 to 3), iu4_bclr and iu4_bh_q(0 to 1) = "00"); + +ex6_repair(0 to 3) <= gate(ex6_tid_q(0 to 3) and not ex6_flush_tid_q(0 to 3), ex6_val_q and (ex6_br_taken_q xor ex6_br_hist_q(0))) or + ex6_flush_tid_q(0 to 3); + + +iu6_ls_t0_ptr_d(0 to 3) <= ex7_ls_t0_ptr_d(0 to 3) when ex6_repair(0) = '1' else + iu6_ls_t0_ptr_q(3) & iu6_ls_t0_ptr_q(0 to 2) when iu5_ls_push_q(0) = '1' and iu5_ls_pop_q(0) = '0' else + iu6_ls_t0_ptr_q(1 to 3) & iu6_ls_t0_ptr_q(0) when iu5_ls_push_q(0) = '0' and iu5_ls_pop_q(0) = '1' else + iu6_ls_t0_ptr_q(0 to 3); +iu6_ls_t1_ptr_d(0 to 3) <= ex7_ls_t1_ptr_d(0 to 3) when ex6_repair(1) = '1' else + iu6_ls_t1_ptr_q(3) & iu6_ls_t1_ptr_q(0 to 2) when iu5_ls_push_q(1) = '1' and iu5_ls_pop_q(1) = '0' else + iu6_ls_t1_ptr_q(1 to 3) & iu6_ls_t1_ptr_q(0) when iu5_ls_push_q(1) = '0' and iu5_ls_pop_q(1) = '1' else + iu6_ls_t1_ptr_q(0 to 3); +iu6_ls_t2_ptr_d(0 to 3) <= ex7_ls_t2_ptr_d(0 to 3) when ex6_repair(2) = '1' else + iu6_ls_t2_ptr_q(3) & iu6_ls_t2_ptr_q(0 to 2) when iu5_ls_push_q(2) = '1' and iu5_ls_pop_q(2) = '0' else + iu6_ls_t2_ptr_q(1 to 3) & iu6_ls_t2_ptr_q(0) when iu5_ls_push_q(2) = '0' and iu5_ls_pop_q(2) = '1' else + iu6_ls_t2_ptr_q(0 to 3); +iu6_ls_t3_ptr_d(0 to 3) <= ex7_ls_t3_ptr_d(0 to 3) when ex6_repair(3) = '1' else + iu6_ls_t3_ptr_q(3) & iu6_ls_t3_ptr_q(0 to 2) when iu5_ls_push_q(3) = '1' and iu5_ls_pop_q(3) = '0' else + iu6_ls_t3_ptr_q(1 to 3) & iu6_ls_t3_ptr_q(0) when iu5_ls_push_q(3) = '0' and iu5_ls_pop_q(3) = '1' else + iu6_ls_t3_ptr_q(0 to 3); + +iu6_ls_ptr_act(0 to 3) <= ex6_repair(0 to 3) or not ib_ic_iu5_redirect_tid(0 to 3); + + +iu5_ls_update(0 to 3) <= iu5_ls_push_q(0 to 3) and not ib_ic_iu5_redirect_tid(0 to 3); +ex6_ls_update(0 to 3) <= gate(ex6_ls_push_q(0 to 3), not ex6_br_hist_q(0)); + +iu5_ifar_d(EFF_IFAR'left to 61) <= (iu4_ifar_q(EFF_IFAR'left to 59) & iu4_ifar_pri_q(60 to 61)); +iu5_act <= or_reduce(iu4_pr_taken_q(0 to 3)) and iu4_lk_q; + +iu5_nia(EFF_IFAR'left to 61) <= iu5_ifar_q(EFF_IFAR'left to 61) + 1; +ex6_nia(EFF_IFAR'left to 61) <= ex6_ifar_q(EFF_IFAR'left to 61) + 1; + + +iu6_ls_t00_d(EFF_IFAR'left to 61) <= ex6_nia(EFF_IFAR'left to 61) when ex6_ls_update(0) = '1' else + iu5_nia(EFF_IFAR'left to 61) when iu5_ls_update(0) = '1' else + iu6_ls_t00_q(EFF_IFAR'left to 61); +iu6_ls_t01_d(EFF_IFAR'left to 61) <= ex6_nia(EFF_IFAR'left to 61) when ex6_ls_update(0) = '1' else + iu5_nia(EFF_IFAR'left to 61) when iu5_ls_update(0) = '1' else + iu6_ls_t01_q(EFF_IFAR'left to 61); +iu6_ls_t02_d(EFF_IFAR'left to 61) <= ex6_nia(EFF_IFAR'left to 61) when ex6_ls_update(0) = '1' else + iu5_nia(EFF_IFAR'left to 61) when iu5_ls_update(0) = '1' else + iu6_ls_t02_q(EFF_IFAR'left to 61); +iu6_ls_t03_d(EFF_IFAR'left to 61) <= ex6_nia(EFF_IFAR'left to 61) when ex6_ls_update(0) = '1' else + iu5_nia(EFF_IFAR'left to 61) when iu5_ls_update(0) = '1' else + iu6_ls_t03_q(EFF_IFAR'left to 61); + +iu6_ls_t0_act(0 to 3) <= ex7_ls_t0_ptr_d(0 to 3) when ex6_ls_update(0) = '1' else + iu6_ls_t0_ptr_d(0 to 3) when iu5_ls_push_q(0) = '1' else + "0000"; + +iu6_ls_t10_d(EFF_IFAR'left to 61) <= ex6_nia(EFF_IFAR'left to 61) when ex6_ls_update(1) = '1' else + iu5_nia(EFF_IFAR'left to 61) when iu5_ls_update(1) = '1' else + iu6_ls_t10_q(EFF_IFAR'left to 61); +iu6_ls_t11_d(EFF_IFAR'left to 61) <= ex6_nia(EFF_IFAR'left to 61) when ex6_ls_update(1) = '1' else + iu5_nia(EFF_IFAR'left to 61) when iu5_ls_update(1) = '1' else + iu6_ls_t11_q(EFF_IFAR'left to 61); +iu6_ls_t12_d(EFF_IFAR'left to 61) <= ex6_nia(EFF_IFAR'left to 61) when ex6_ls_update(1) = '1' else + iu5_nia(EFF_IFAR'left to 61) when iu5_ls_update(1) = '1' else + iu6_ls_t12_q(EFF_IFAR'left to 61); +iu6_ls_t13_d(EFF_IFAR'left to 61) <= ex6_nia(EFF_IFAR'left to 61) when ex6_ls_update(1) = '1' else + iu5_nia(EFF_IFAR'left to 61) when iu5_ls_update(1) = '1' else + iu6_ls_t13_q(EFF_IFAR'left to 61); + +iu6_ls_t1_act(0 to 3) <= ex7_ls_t1_ptr_d(0 to 3) when ex6_ls_update(1) = '1' else + iu6_ls_t1_ptr_d(0 to 3) when iu5_ls_push_q(1) = '1' else + "0000"; + +iu6_ls_t20_d(EFF_IFAR'left to 61) <= ex6_nia(EFF_IFAR'left to 61) when ex6_ls_update(2) = '1' else + iu5_nia(EFF_IFAR'left to 61) when iu5_ls_update(2) = '1' else + iu6_ls_t20_q(EFF_IFAR'left to 61); +iu6_ls_t21_d(EFF_IFAR'left to 61) <= ex6_nia(EFF_IFAR'left to 61) when ex6_ls_update(2) = '1' else + iu5_nia(EFF_IFAR'left to 61) when iu5_ls_update(2) = '1' else + iu6_ls_t21_q(EFF_IFAR'left to 61); +iu6_ls_t22_d(EFF_IFAR'left to 61) <= ex6_nia(EFF_IFAR'left to 61) when ex6_ls_update(2) = '1' else + iu5_nia(EFF_IFAR'left to 61) when iu5_ls_update(2) = '1' else + iu6_ls_t22_q(EFF_IFAR'left to 61); +iu6_ls_t23_d(EFF_IFAR'left to 61) <= ex6_nia(EFF_IFAR'left to 61) when ex6_ls_update(2) = '1' else + iu5_nia(EFF_IFAR'left to 61) when iu5_ls_update(2) = '1' else + iu6_ls_t23_q(EFF_IFAR'left to 61); + +iu6_ls_t2_act(0 to 3) <= ex7_ls_t2_ptr_d(0 to 3) when ex6_ls_update(2) = '1' else + iu6_ls_t2_ptr_d(0 to 3) when iu5_ls_push_q(2) = '1' else + "0000"; + +iu6_ls_t30_d(EFF_IFAR'left to 61) <= ex6_nia(EFF_IFAR'left to 61) when ex6_ls_update(3) = '1' else + iu5_nia(EFF_IFAR'left to 61) when iu5_ls_update(3) = '1' else + iu6_ls_t30_q(EFF_IFAR'left to 61); +iu6_ls_t31_d(EFF_IFAR'left to 61) <= ex6_nia(EFF_IFAR'left to 61) when ex6_ls_update(3) = '1' else + iu5_nia(EFF_IFAR'left to 61) when iu5_ls_update(3) = '1' else + iu6_ls_t31_q(EFF_IFAR'left to 61); +iu6_ls_t32_d(EFF_IFAR'left to 61) <= ex6_nia(EFF_IFAR'left to 61) when ex6_ls_update(3) = '1' else + iu5_nia(EFF_IFAR'left to 61) when iu5_ls_update(3) = '1' else + iu6_ls_t32_q(EFF_IFAR'left to 61); +iu6_ls_t33_d(EFF_IFAR'left to 61) <= ex6_nia(EFF_IFAR'left to 61) when ex6_ls_update(3) = '1' else + iu5_nia(EFF_IFAR'left to 61) when iu5_ls_update(3) = '1' else + iu6_ls_t33_q(EFF_IFAR'left to 61); + +iu6_ls_t3_act(0 to 3) <= ex7_ls_t3_ptr_d(0 to 3) when ex6_ls_update(3) = '1' else + iu6_ls_t3_ptr_d(0 to 3) when iu5_ls_push_q(3) = '1' else + "0000"; + + +iu4_lnk(EFF_IFAR'left to 61) <= gate(iu6_ls_t00_q(EFF_IFAR'left to 61), iu4_tid_q(0) and iu6_ls_t0_ptr_q(0)) or + gate(iu6_ls_t01_q(EFF_IFAR'left to 61), iu4_tid_q(0) and iu6_ls_t0_ptr_q(1)) or + gate(iu6_ls_t02_q(EFF_IFAR'left to 61), iu4_tid_q(0) and iu6_ls_t0_ptr_q(2)) or + gate(iu6_ls_t03_q(EFF_IFAR'left to 61), iu4_tid_q(0) and iu6_ls_t0_ptr_q(3)) or + + gate(iu6_ls_t10_q(EFF_IFAR'left to 61), iu4_tid_q(1) and iu6_ls_t1_ptr_q(0)) or + gate(iu6_ls_t11_q(EFF_IFAR'left to 61), iu4_tid_q(1) and iu6_ls_t1_ptr_q(1)) or + gate(iu6_ls_t12_q(EFF_IFAR'left to 61), iu4_tid_q(1) and iu6_ls_t1_ptr_q(2)) or + gate(iu6_ls_t13_q(EFF_IFAR'left to 61), iu4_tid_q(1) and iu6_ls_t1_ptr_q(3)) or + + gate(iu6_ls_t20_q(EFF_IFAR'left to 61), iu4_tid_q(2) and iu6_ls_t2_ptr_q(0)) or + gate(iu6_ls_t21_q(EFF_IFAR'left to 61), iu4_tid_q(2) and iu6_ls_t2_ptr_q(1)) or + gate(iu6_ls_t22_q(EFF_IFAR'left to 61), iu4_tid_q(2) and iu6_ls_t2_ptr_q(2)) or + gate(iu6_ls_t23_q(EFF_IFAR'left to 61), iu4_tid_q(2) and iu6_ls_t2_ptr_q(3)) or + + gate(iu6_ls_t30_q(EFF_IFAR'left to 61), iu4_tid_q(3) and iu6_ls_t3_ptr_q(0)) or + gate(iu6_ls_t31_q(EFF_IFAR'left to 61), iu4_tid_q(3) and iu6_ls_t3_ptr_q(1)) or + gate(iu6_ls_t32_q(EFF_IFAR'left to 61), iu4_tid_q(3) and iu6_ls_t3_ptr_q(2)) or + gate(iu6_ls_t33_q(EFF_IFAR'left to 61), iu4_tid_q(3) and iu6_ls_t3_ptr_q(3)) ; + + + + + + + +iu5_hold_tid_d(0) <= '0' when iu5_flush_tid(0) = '1' else + '1' when iu4_pr_taken_q(0) = '1' and not iu4_flush_tid(0) = '1' and iu4_bcctr = '1' else + iu5_hold_tid_q(0); + +iu5_hold_tid_d(1) <= '0' when iu5_flush_tid(1) = '1' else + '1' when iu4_pr_taken_q(1) = '1' and not iu4_flush_tid(1) = '1' and iu4_bcctr = '1' else + iu5_hold_tid_q(1); + +iu5_hold_tid_d(2) <= '0' when iu5_flush_tid(2) = '1' else + '1' when iu4_pr_taken_q(2) = '1' and not iu4_flush_tid(2) = '1' and iu4_bcctr = '1' else + iu5_hold_tid_q(2); + +iu5_hold_tid_d(3) <= '0' when iu5_flush_tid(3) = '1' else + '1' when iu4_pr_taken_q(3) = '1' and not iu4_flush_tid(3) = '1' and iu4_bcctr = '1' else + iu5_hold_tid_q(3); + +bp_ic_iu5_hold_tid(0 to 3) <= iu5_hold_tid_q(0 to 3); + + +iu5_redirect_act <= or_reduce(iu4_redirect_tid(0 to 3)); + +iu5_redirect_ifar_d(EFF_IFAR'left to 61) <= iu4_lnk(EFF_IFAR'left to 61) when iu4_bclr = '1' else + iu4_bta(EFF_IFAR'left to 61); + +iu4_redirect_tid(0 to 3) <= iu4_pr_taken_q(0 to 3); +iu5_redirect_tid_d(0 to 3) <= iu4_redirect_tid(0 to 3) and not iu4_flush_tid(0 to 3); + +bp_ic_iu5_redirect_ifar(EFF_IFAR'left to 61) <= iu5_redirect_ifar_q(EFF_IFAR'left to 61); +bp_ic_iu5_redirect_tid(0 to 3) <= iu5_redirect_tid_q(0 to 3); + + + +bp_ib_iu4_ifar(EFF_IFAR'left to 61) <= iu4_ifar_q(EFF_IFAR'left to 61); + +bp_ib_iu4_t0_val(0 to 3) <= iu4_t0_val_q(0 to 3); +bp_ib_iu4_t1_val(0 to 3) <= iu4_t1_val_q(0 to 3); +bp_ib_iu4_t2_val(0 to 3) <= iu4_t2_val_q(0 to 3); +bp_ib_iu4_t3_val(0 to 3) <= iu4_t3_val_q(0 to 3); + +bp_ib_iu3_0_instr(0 to 31) <= iu4_0_instr_d(0 to 31); +bp_ib_iu4_0_instr(32 to 43) <= iu4_0_instr_q(32 to 43); +bp_ib_iu4_1_instr(0 to 43) <= iu4_1_instr_q(0 to 43); +bp_ib_iu4_2_instr(0 to 43) <= iu4_2_instr_q(0 to 43); +bp_ib_iu4_3_instr(0 to 43) <= iu4_3_instr_q(0 to 43); + + +bp_dbg_data0(0 to 7) <= iu6_ls_t00_q(54 to 61); +bp_dbg_data0(8 to 15) <= iu6_ls_t01_q(54 to 61); +bp_dbg_data0(16 to 23) <= iu6_ls_t02_q(54 to 61); +bp_dbg_data0(24 to 31) <= iu6_ls_t03_q(54 to 61); + +bp_dbg_data0(32 to 39) <= iu6_ls_t10_q(54 to 61); +bp_dbg_data0(40 to 47) <= iu6_ls_t11_q(54 to 61); +bp_dbg_data0(48 to 55) <= iu6_ls_t12_q(54 to 61); +bp_dbg_data0(56 to 63) <= iu6_ls_t13_q(54 to 61); + +bp_dbg_data0(64 to 67) <= iu6_ls_t0_ptr_q; +bp_dbg_data0(68 to 71) <= iu6_ls_t1_ptr_q; +bp_dbg_data0(72 to 75) <= ex7_ls_t0_ptr_q; +bp_dbg_data0(76 to 79) <= ex7_ls_t1_ptr_q; + +bp_dbg_data0(80 to 83) <= ex6_tid_q; +bp_dbg_data0(84) <= ex6_val_q; +bp_dbg_data0(85) <= ex6_br_update_q; +bp_dbg_data0(86 to 87) <= ex6_br_hist_q(0 to 1); + +bp_dbg_data1(0 to 7) <= iu6_ls_t20_q(54 to 61); +bp_dbg_data1(8 to 15) <= iu6_ls_t21_q(54 to 61); +bp_dbg_data1(16 to 23) <= iu6_ls_t22_q(54 to 61); +bp_dbg_data1(24 to 31) <= iu6_ls_t23_q(54 to 61); + +bp_dbg_data1(32 to 39) <= iu6_ls_t30_q(54 to 61); +bp_dbg_data1(40 to 47) <= iu6_ls_t31_q(54 to 61); +bp_dbg_data1(48 to 55) <= iu6_ls_t32_q(54 to 61); +bp_dbg_data1(56 to 63) <= iu6_ls_t33_q(54 to 61); + +bp_dbg_data1(64 to 67) <= iu6_ls_t2_ptr_q; +bp_dbg_data1(68 to 71) <= iu6_ls_t3_ptr_q; +bp_dbg_data1(72 to 75) <= ex7_ls_t2_ptr_q; +bp_dbg_data1(76 to 79) <= ex7_ls_t3_ptr_q; + +bp_dbg_data1(80 to 83) <= ex6_gshare_q(0 to 3); +bp_dbg_data1(84) <= ex6_br_taken_q; +bp_dbg_data1(85) <= ex6_bclr_q; +bp_dbg_data1(86) <= ex6_lk_q; +bp_dbg_data1(87) <= '0'; + + + +ic_bp_iu1_tid_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(ic_bp_iu1_tid_offset to ic_bp_iu1_tid_offset+3), + scout => sov0(ic_bp_iu1_tid_offset to ic_bp_iu1_tid_offset+3), + din => ic_bp_iu1_tid_d(0 to 3), + dout => ic_bp_iu1_tid_q(0 to 3)); + +gshare_t0_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => gshare_act(0), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(gshare_t0_offset to gshare_t0_offset+3), + scout => sov0(gshare_t0_offset to gshare_t0_offset+3), + din => gshare_t0_d(0 to 3), + dout => gshare_t0_q(0 to 3)); + +gshare_t1_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => gshare_act(1), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(gshare_t1_offset to gshare_t1_offset+3), + scout => sov0(gshare_t1_offset to gshare_t1_offset+3), + din => gshare_t1_d(0 to 3), + dout => gshare_t1_q(0 to 3)); + +gshare_t2_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => gshare_act(2), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(gshare_t2_offset to gshare_t2_offset+3), + scout => sov0(gshare_t2_offset to gshare_t2_offset+3), + din => gshare_t2_d(0 to 3), + dout => gshare_t2_q(0 to 3)); + +gshare_t3_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => gshare_act(3), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(gshare_t3_offset to gshare_t3_offset+3), + scout => sov0(gshare_t3_offset to gshare_t3_offset+3), + din => gshare_t3_d(0 to 3), + dout => gshare_t3_q(0 to 3)); + +cp_gshare_t0_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cp_gshare_act(0), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(cp_gshare_t0_offset to cp_gshare_t0_offset+3), + scout => sov0(cp_gshare_t0_offset to cp_gshare_t0_offset+3), + din => cp_gshare_t0_d(0 to 3), + dout => cp_gshare_t0_q(0 to 3)); + +cp_gshare_t1_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cp_gshare_act(1), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(cp_gshare_t1_offset to cp_gshare_t1_offset+3), + scout => sov0(cp_gshare_t1_offset to cp_gshare_t1_offset+3), + din => cp_gshare_t1_d(0 to 3), + dout => cp_gshare_t1_q(0 to 3)); + +cp_gshare_t2_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cp_gshare_act(2), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(cp_gshare_t2_offset to cp_gshare_t2_offset+3), + scout => sov0(cp_gshare_t2_offset to cp_gshare_t2_offset+3), + din => cp_gshare_t2_d(0 to 3), + dout => cp_gshare_t2_q(0 to 3)); + +cp_gshare_t3_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cp_gshare_act(3), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(cp_gshare_t3_offset to cp_gshare_t3_offset+3), + scout => sov0(cp_gshare_t3_offset to cp_gshare_t3_offset+3), + din => cp_gshare_t3_d(0 to 3), + dout => cp_gshare_t3_q(0 to 3)); + +iu2_gshare_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(iu2_gshare_offset to iu2_gshare_offset+3), + scout => sov0(iu2_gshare_offset to iu2_gshare_offset+3), + din => iu2_gshare_d(0 to 3), + dout => iu2_gshare_q(0 to 3)); + +iu3_gshare_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(iu3_gshare_offset to iu3_gshare_offset+3), + scout => sov0(iu3_gshare_offset to iu3_gshare_offset+3), + din => iu3_gshare_d(0 to 3), + dout => iu3_gshare_q(0 to 3)); + + +iu4_bh_reg: tri_rlmreg_p + generic map (width => 2, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu4_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(iu4_bh_offset to iu4_bh_offset+1), + scout => sov0(iu4_bh_offset to iu4_bh_offset+1), + din => iu4_bh_d(0 to 1), + dout => iu4_bh_q(0 to 1)); + +iu4_lk_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu4_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(iu4_lk_offset), + scout => sov0(iu4_lk_offset), + din => iu4_lk_d, + dout => iu4_lk_q); + +iu4_aa_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu4_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(iu4_aa_offset), + scout => sov0(iu4_aa_offset), + din => iu4_aa_d, + dout => iu4_aa_q); + +iu4_b_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu4_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(iu4_b_offset), + scout => sov0(iu4_b_offset), + din => iu4_b_d, + dout => iu4_b_q); + + +iu4_opcode_reg: tri_rlmreg_p + generic map (width => 6, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu4_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(iu4_opcode_offset to iu4_opcode_offset+5), + scout => sov0(iu4_opcode_offset to iu4_opcode_offset+5), + din => iu4_opcode_d(0 to 5), + dout => iu4_opcode_q(0 to 5)); + +iu4_excode_reg: tri_rlmreg_p + generic map (width => 10, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu4_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(iu4_excode_offset to iu4_excode_offset+9), + scout => sov0(iu4_excode_offset to iu4_excode_offset+9), + din => iu4_excode_d(21 to 30), + dout => iu4_excode_q(21 to 30)); + +iu4_bo_reg: tri_rlmreg_p + generic map (width => 5, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu4_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(iu4_bo_offset to iu4_bo_offset+4), + scout => sov0(iu4_bo_offset to iu4_bo_offset+4), + din => iu4_bo_d(6 to 10), + dout => iu4_bo_q(6 to 10)); + +iu4_bi_reg: tri_rlmreg_p + generic map (width => 5, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu4_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(iu4_bi_offset to iu4_bi_offset+4), + scout => sov0(iu4_bi_offset to iu4_bi_offset+4), + din => iu4_bi_d(11 to 15), + dout => iu4_bi_q(11 to 15)); + + +iu4_tar_reg: tri_rlmreg_p + generic map (width => 24, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu4_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(iu4_tar_offset to iu4_tar_offset+23), + scout => sov0(iu4_tar_offset to iu4_tar_offset+23), + din => iu4_tar_d(6 to 29), + dout => iu4_tar_q(6 to 29)); + +iu4_ifar_reg: tri_rlmreg_p + generic map (width => EFF_IFAR'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu4_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(iu4_ifar_offset to iu4_ifar_offset+EFF_IFAR'length-1), + scout => sov0(iu4_ifar_offset to iu4_ifar_offset+EFF_IFAR'length-1), + din => iu4_ifar_d(EFF_IFAR'left to 61), + dout => iu4_ifar_q(EFF_IFAR'left to 61)); + +iu4_ifar_pri_reg: tri_rlmreg_p + generic map (width => 2, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu4_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(iu4_ifar_pri_offset to iu4_ifar_pri_offset+1), + scout => sov0(iu4_ifar_pri_offset to iu4_ifar_pri_offset+1), + din => iu4_ifar_pri_d(60 to 61), + dout => iu4_ifar_pri_q(60 to 61)); + + +iu4_pr_taken_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(iu4_pr_taken_offset to iu4_pr_taken_offset+3), + scout => sov0(iu4_pr_taken_offset to iu4_pr_taken_offset+3), + din => iu4_pr_taken_d(0 to 3), + dout => iu4_pr_taken_q(0 to 3)); + +iu4_tid_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu4_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(iu4_tid_offset to iu4_tid_offset+3), + scout => sov0(iu4_tid_offset to iu4_tid_offset+3), + din => iu4_tid_d(0 to 3), + dout => iu4_tid_q(0 to 3)); + + +iu4_t0_val_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(iu4_t0_val_offset to iu4_t0_val_offset+3), + scout => sov0(iu4_t0_val_offset to iu4_t0_val_offset+3), + din => iu4_t0_val_d(0 to 3), + dout => iu4_t0_val_q(0 to 3)); + +iu4_t1_val_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(iu4_t1_val_offset to iu4_t1_val_offset+3), + scout => sov0(iu4_t1_val_offset to iu4_t1_val_offset+3), + din => iu4_t1_val_d(0 to 3), + dout => iu4_t1_val_q(0 to 3)); + +iu4_t2_val_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(iu4_t2_val_offset to iu4_t2_val_offset+3), + scout => sov0(iu4_t2_val_offset to iu4_t2_val_offset+3), + din => iu4_t2_val_d(0 to 3), + dout => iu4_t2_val_q(0 to 3)); + +iu4_t3_val_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(iu4_t3_val_offset to iu4_t3_val_offset+3), + scout => sov0(iu4_t3_val_offset to iu4_t3_val_offset+3), + din => iu4_t3_val_d(0 to 3), + dout => iu4_t3_val_q(0 to 3)); + + +iu4_0_instr_reg: tri_rlmreg_p + generic map (width => 12, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu4_instr_act(0), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(iu4_0_instr_offset to iu4_0_instr_offset+11), + scout => sov0(iu4_0_instr_offset to iu4_0_instr_offset+11), + din => iu4_0_instr_d(32 to 43), + dout => iu4_0_instr_q(32 to 43)); + +iu4_1_instr_reg: tri_rlmreg_p + generic map (width => 44, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu4_instr_act(1), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(iu4_1_instr_offset to iu4_1_instr_offset+43), + scout => sov0(iu4_1_instr_offset to iu4_1_instr_offset+43), + din => iu4_1_instr_d(0 to 43), + dout => iu4_1_instr_q(0 to 43)); + +iu4_2_instr_reg: tri_rlmreg_p + generic map (width => 44, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu4_instr_act(2), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(iu4_2_instr_offset to iu4_2_instr_offset+43), + scout => sov0(iu4_2_instr_offset to iu4_2_instr_offset+43), + din => iu4_2_instr_d(0 to 43), + dout => iu4_2_instr_q(0 to 43)); + +iu4_3_instr_reg: tri_rlmreg_p + generic map (width => 44, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu4_instr_act(3), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(iu4_3_instr_offset to iu4_3_instr_offset+43), + scout => sov0(iu4_3_instr_offset to iu4_3_instr_offset+43), + din => iu4_3_instr_d(0 to 43), + dout => iu4_3_instr_q(0 to 43)); + +iu5_redirect_ifar_reg: tri_rlmreg_p + generic map (width => EFF_IFAR'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu5_redirect_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(iu5_redirect_ifar_offset to iu5_redirect_ifar_offset+EFF_IFAR'length-1), + scout => sov0(iu5_redirect_ifar_offset to iu5_redirect_ifar_offset+EFF_IFAR'length-1), + din => iu5_redirect_ifar_d(EFF_IFAR'left to 61), + dout => iu5_redirect_ifar_q(EFF_IFAR'left to 61)); + +iu5_redirect_tid_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(iu5_redirect_tid_offset to iu5_redirect_tid_offset+3), + scout => sov0(iu5_redirect_tid_offset to iu5_redirect_tid_offset+3), + din => iu5_redirect_tid_d(0 to 3), + dout => iu5_redirect_tid_q(0 to 3)); + +iu5_hold_tid_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(iu5_hold_tid_offset to iu5_hold_tid_offset+3), + scout => sov0(iu5_hold_tid_offset to iu5_hold_tid_offset+3), + din => iu5_hold_tid_d(0 to 3), + dout => iu5_hold_tid_q(0 to 3)); + + +iu5_ls_push_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(iu5_ls_push_offset to iu5_ls_push_offset+3), + scout => sov0(iu5_ls_push_offset to iu5_ls_push_offset+3), + din => iu5_ls_push_d(0 to 3), + dout => iu5_ls_push_q(0 to 3)); + +iu5_ls_pop_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(iu5_ls_pop_offset to iu5_ls_pop_offset+3), + scout => sov0(iu5_ls_pop_offset to iu5_ls_pop_offset+3), + din => iu5_ls_pop_d(0 to 3), + dout => iu5_ls_pop_q(0 to 3)); + +iu5_ifar_reg: tri_rlmreg_p + generic map (width => EFF_IFAR'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu5_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(iu5_ifar_offset to iu5_ifar_offset+EFF_IFAR'length-1), + scout => sov0(iu5_ifar_offset to iu5_ifar_offset+EFF_IFAR'length-1), + din => iu5_ifar_d(EFF_IFAR'left to 61), + dout => iu5_ifar_q(EFF_IFAR'left to 61)); + +iu6_ls_t0_ptr_reg: tri_rlmreg_p + generic map (width => 4, init => 8, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu6_ls_ptr_act(0), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(iu6_ls_t0_ptr_offset to iu6_ls_t0_ptr_offset+3), + scout => sov1(iu6_ls_t0_ptr_offset to iu6_ls_t0_ptr_offset+3), + din => iu6_ls_t0_ptr_d(0 to 3), + dout => iu6_ls_t0_ptr_q(0 to 3)); + +iu6_ls_t1_ptr_reg: tri_rlmreg_p + generic map (width => 4, init => 8, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu6_ls_ptr_act(1), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(iu6_ls_t1_ptr_offset to iu6_ls_t1_ptr_offset+3), + scout => sov1(iu6_ls_t1_ptr_offset to iu6_ls_t1_ptr_offset+3), + din => iu6_ls_t1_ptr_d(0 to 3), + dout => iu6_ls_t1_ptr_q(0 to 3)); + +iu6_ls_t2_ptr_reg: tri_rlmreg_p + generic map (width => 4, init => 8, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu6_ls_ptr_act(2), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(iu6_ls_t2_ptr_offset to iu6_ls_t2_ptr_offset+3), + scout => sov1(iu6_ls_t2_ptr_offset to iu6_ls_t2_ptr_offset+3), + din => iu6_ls_t2_ptr_d(0 to 3), + dout => iu6_ls_t2_ptr_q(0 to 3)); + +iu6_ls_t3_ptr_reg: tri_rlmreg_p + generic map (width => 4, init => 8, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu6_ls_ptr_act(3), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(iu6_ls_t3_ptr_offset to iu6_ls_t3_ptr_offset+3), + scout => sov1(iu6_ls_t3_ptr_offset to iu6_ls_t3_ptr_offset+3), + din => iu6_ls_t3_ptr_d(0 to 3), + dout => iu6_ls_t3_ptr_q(0 to 3)); + +iu6_ls_t00_reg: tri_rlmreg_p + generic map (width => EFF_IFAR'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu6_ls_t0_act(0), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(iu6_ls_t00_offset to iu6_ls_t00_offset+EFF_IFAR'length-1), + scout => sov1(iu6_ls_t00_offset to iu6_ls_t00_offset+EFF_IFAR'length-1), + din => iu6_ls_t00_d(EFF_IFAR'left to 61), + dout => iu6_ls_t00_q(EFF_IFAR'left to 61)); + +iu6_ls_t01_reg: tri_rlmreg_p + generic map (width => EFF_IFAR'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu6_ls_t0_act(1), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(iu6_ls_t01_offset to iu6_ls_t01_offset+EFF_IFAR'length-1), + scout => sov1(iu6_ls_t01_offset to iu6_ls_t01_offset+EFF_IFAR'length-1), + din => iu6_ls_t01_d(EFF_IFAR'left to 61), + dout => iu6_ls_t01_q(EFF_IFAR'left to 61)); + +iu6_ls_t02_reg: tri_rlmreg_p + generic map (width => EFF_IFAR'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu6_ls_t0_act(2), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(iu6_ls_t02_offset to iu6_ls_t02_offset+EFF_IFAR'length-1), + scout => sov1(iu6_ls_t02_offset to iu6_ls_t02_offset+EFF_IFAR'length-1), + din => iu6_ls_t02_d(EFF_IFAR'left to 61), + dout => iu6_ls_t02_q(EFF_IFAR'left to 61)); + +iu6_ls_t03_reg: tri_rlmreg_p + generic map (width => EFF_IFAR'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu6_ls_t0_act(3), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(iu6_ls_t03_offset to iu6_ls_t03_offset+EFF_IFAR'length-1), + scout => sov1(iu6_ls_t03_offset to iu6_ls_t03_offset+EFF_IFAR'length-1), + din => iu6_ls_t03_d(EFF_IFAR'left to 61), + dout => iu6_ls_t03_q(EFF_IFAR'left to 61)); + +iu6_ls_t10_reg: tri_rlmreg_p + generic map (width => EFF_IFAR'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu6_ls_t1_act(0), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(iu6_ls_t10_offset to iu6_ls_t10_offset+EFF_IFAR'length-1), + scout => sov1(iu6_ls_t10_offset to iu6_ls_t10_offset+EFF_IFAR'length-1), + din => iu6_ls_t10_d(EFF_IFAR'left to 61), + dout => iu6_ls_t10_q(EFF_IFAR'left to 61)); + +iu6_ls_t11_reg: tri_rlmreg_p + generic map (width => EFF_IFAR'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu6_ls_t1_act(1), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(iu6_ls_t11_offset to iu6_ls_t11_offset+EFF_IFAR'length-1), + scout => sov1(iu6_ls_t11_offset to iu6_ls_t11_offset+EFF_IFAR'length-1), + din => iu6_ls_t11_d(EFF_IFAR'left to 61), + dout => iu6_ls_t11_q(EFF_IFAR'left to 61)); + +iu6_ls_t12_reg: tri_rlmreg_p + generic map (width => EFF_IFAR'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu6_ls_t1_act(2), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(iu6_ls_t12_offset to iu6_ls_t12_offset+EFF_IFAR'length-1), + scout => sov1(iu6_ls_t12_offset to iu6_ls_t12_offset+EFF_IFAR'length-1), + din => iu6_ls_t12_d(EFF_IFAR'left to 61), + dout => iu6_ls_t12_q(EFF_IFAR'left to 61)); + +iu6_ls_t13_reg: tri_rlmreg_p + generic map (width => EFF_IFAR'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu6_ls_t1_act(3), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(iu6_ls_t13_offset to iu6_ls_t13_offset+EFF_IFAR'length-1), + scout => sov1(iu6_ls_t13_offset to iu6_ls_t13_offset+EFF_IFAR'length-1), + din => iu6_ls_t13_d(EFF_IFAR'left to 61), + dout => iu6_ls_t13_q(EFF_IFAR'left to 61)); + +iu6_ls_t20_reg: tri_rlmreg_p + generic map (width => EFF_IFAR'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu6_ls_t2_act(0), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(iu6_ls_t20_offset to iu6_ls_t20_offset+EFF_IFAR'length-1), + scout => sov1(iu6_ls_t20_offset to iu6_ls_t20_offset+EFF_IFAR'length-1), + din => iu6_ls_t20_d(EFF_IFAR'left to 61), + dout => iu6_ls_t20_q(EFF_IFAR'left to 61)); + +iu6_ls_t21_reg: tri_rlmreg_p + generic map (width => EFF_IFAR'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu6_ls_t2_act(1), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(iu6_ls_t21_offset to iu6_ls_t21_offset+EFF_IFAR'length-1), + scout => sov1(iu6_ls_t21_offset to iu6_ls_t21_offset+EFF_IFAR'length-1), + din => iu6_ls_t21_d(EFF_IFAR'left to 61), + dout => iu6_ls_t21_q(EFF_IFAR'left to 61)); + +iu6_ls_t22_reg: tri_rlmreg_p + generic map (width => EFF_IFAR'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu6_ls_t2_act(2), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(iu6_ls_t22_offset to iu6_ls_t22_offset+EFF_IFAR'length-1), + scout => sov1(iu6_ls_t22_offset to iu6_ls_t22_offset+EFF_IFAR'length-1), + din => iu6_ls_t22_d(EFF_IFAR'left to 61), + dout => iu6_ls_t22_q(EFF_IFAR'left to 61)); + +iu6_ls_t23_reg: tri_rlmreg_p + generic map (width => EFF_IFAR'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu6_ls_t2_act(3), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(iu6_ls_t23_offset to iu6_ls_t23_offset+EFF_IFAR'length-1), + scout => sov1(iu6_ls_t23_offset to iu6_ls_t23_offset+EFF_IFAR'length-1), + din => iu6_ls_t23_d(EFF_IFAR'left to 61), + dout => iu6_ls_t23_q(EFF_IFAR'left to 61)); + +iu6_ls_t30_reg: tri_rlmreg_p + generic map (width => EFF_IFAR'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu6_ls_t3_act(0), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(iu6_ls_t30_offset to iu6_ls_t30_offset+EFF_IFAR'length-1), + scout => sov1(iu6_ls_t30_offset to iu6_ls_t30_offset+EFF_IFAR'length-1), + din => iu6_ls_t30_d(EFF_IFAR'left to 61), + dout => iu6_ls_t30_q(EFF_IFAR'left to 61)); + +iu6_ls_t31_reg: tri_rlmreg_p + generic map (width => EFF_IFAR'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu6_ls_t3_act(1), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(iu6_ls_t31_offset to iu6_ls_t31_offset+EFF_IFAR'length-1), + scout => sov1(iu6_ls_t31_offset to iu6_ls_t31_offset+EFF_IFAR'length-1), + din => iu6_ls_t31_d(EFF_IFAR'left to 61), + dout => iu6_ls_t31_q(EFF_IFAR'left to 61)); + +iu6_ls_t32_reg: tri_rlmreg_p + generic map (width => EFF_IFAR'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu6_ls_t3_act(2), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(iu6_ls_t32_offset to iu6_ls_t32_offset+EFF_IFAR'length-1), + scout => sov1(iu6_ls_t32_offset to iu6_ls_t32_offset+EFF_IFAR'length-1), + din => iu6_ls_t32_d(EFF_IFAR'left to 61), + dout => iu6_ls_t32_q(EFF_IFAR'left to 61)); + +iu6_ls_t33_reg: tri_rlmreg_p + generic map (width => EFF_IFAR'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu6_ls_t3_act(3), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(iu6_ls_t33_offset to iu6_ls_t33_offset+EFF_IFAR'length-1), + scout => sov1(iu6_ls_t33_offset to iu6_ls_t33_offset+EFF_IFAR'length-1), + din => iu6_ls_t33_d(EFF_IFAR'left to 61), + dout => iu6_ls_t33_q(EFF_IFAR'left to 61)); + +ex6_val_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(ex6_val_offset), + scout => sov1(ex6_val_offset), + din => ex6_val_d, + dout => ex6_val_q); + +ex6_ifar_reg: tri_rlmreg_p + generic map (width => EFF_IFAR'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex6_val_d, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(ex6_ifar_offset to ex6_ifar_offset+EFF_IFAR'length-1), + scout => sov1(ex6_ifar_offset to ex6_ifar_offset+EFF_IFAR'length-1), + din => ex6_ifar_d(EFF_IFAR'left to 61), + dout => ex6_ifar_q(EFF_IFAR'left to 61)); + +ex6_tid_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex6_val_d, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(ex6_tid_offset to ex6_tid_offset+3), + scout => sov1(ex6_tid_offset to ex6_tid_offset+3), + din => ex6_tid_d(0 to 3), + dout => ex6_tid_q(0 to 3)); + +ex6_br_update_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex6_val_d, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(ex6_br_update_offset), + scout => sov1(ex6_br_update_offset), + din => ex6_br_update_d, + dout => ex6_br_update_q); + +ex6_br_hist_reg: tri_rlmreg_p + generic map (width => 2, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex6_val_d, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(ex6_br_hist_offset to ex6_br_hist_offset+1), + scout => sov1(ex6_br_hist_offset to ex6_br_hist_offset+1), + din => ex6_br_hist_d(0 to 1), + dout => ex6_br_hist_q(0 to 1)); + +ex6_br_taken_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex6_val_d, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(ex6_br_taken_offset), + scout => sov1(ex6_br_taken_offset), + din => ex6_br_taken_d, + dout => ex6_br_taken_q); + +ex6_bclr_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex6_val_d, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(ex6_bclr_offset), + scout => sov1(ex6_bclr_offset), + din => ex6_bclr_d, + dout => ex6_bclr_q); + + +ex6_lk_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex6_val_d, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(ex6_lk_offset), + scout => sov1(ex6_lk_offset), + din => ex6_lk_d, + dout => ex6_lk_q); + + +ex6_gshare_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex6_val_d, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(ex6_gshare_offset to ex6_gshare_offset+3), + scout => sov1(ex6_gshare_offset to ex6_gshare_offset+3), + din => ex6_gshare_d(0 to 3), + dout => ex6_gshare_q(0 to 3)); + +ex6_ls_push_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(ex6_ls_push_offset to ex6_ls_push_offset+3), + scout => sov1(ex6_ls_push_offset to ex6_ls_push_offset+3), + din => ex6_ls_push_d(0 to 3), + dout => ex6_ls_push_q(0 to 3)); + +ex6_ls_pop_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(ex6_ls_pop_offset to ex6_ls_pop_offset+3), + scout => sov1(ex6_ls_pop_offset to ex6_ls_pop_offset+3), + din => ex6_ls_pop_d(0 to 3), + dout => ex6_ls_pop_q(0 to 3)); + +ex6_flush_tid_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(ex6_flush_tid_offset to ex6_flush_tid_offset+3), + scout => sov1(ex6_flush_tid_offset to ex6_flush_tid_offset+3), + din => ex6_flush_tid_d(0 to 3), + dout => ex6_flush_tid_q(0 to 3)); + +ex7_ls_t0_ptr_reg: tri_rlmreg_p + generic map (width => 4, init => 8, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex7_ls_ptr_act(0), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(ex7_ls_t0_ptr_offset to ex7_ls_t0_ptr_offset+3), + scout => sov1(ex7_ls_t0_ptr_offset to ex7_ls_t0_ptr_offset+3), + din => ex7_ls_t0_ptr_d(0 to 3), + dout => ex7_ls_t0_ptr_q(0 to 3)); + +ex7_ls_t1_ptr_reg: tri_rlmreg_p + generic map (width => 4, init => 8, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex7_ls_ptr_act(1), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(ex7_ls_t1_ptr_offset to ex7_ls_t1_ptr_offset+3), + scout => sov1(ex7_ls_t1_ptr_offset to ex7_ls_t1_ptr_offset+3), + din => ex7_ls_t1_ptr_d(0 to 3), + dout => ex7_ls_t1_ptr_q(0 to 3)); + +ex7_ls_t2_ptr_reg: tri_rlmreg_p + generic map (width => 4, init => 8, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex7_ls_ptr_act(2), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(ex7_ls_t2_ptr_offset to ex7_ls_t2_ptr_offset+3), + scout => sov1(ex7_ls_t2_ptr_offset to ex7_ls_t2_ptr_offset+3), + din => ex7_ls_t2_ptr_d(0 to 3), + dout => ex7_ls_t2_ptr_q(0 to 3)); + +ex7_ls_t3_ptr_reg: tri_rlmreg_p + generic map (width => 4, init => 8, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex7_ls_ptr_act(3), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(ex7_ls_t3_ptr_offset to ex7_ls_t3_ptr_offset+3), + scout => sov1(ex7_ls_t3_ptr_offset to ex7_ls_t3_ptr_offset+3), + din => ex7_ls_t3_ptr_d(0 to 3), + dout => ex7_ls_t3_ptr_q(0 to 3)); + +bp_config_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(bp_config_offset to bp_config_offset+3), + scout => sov1(bp_config_offset to bp_config_offset+3), + din => bp_config_d(0 to 3), + dout => bp_config_q(0 to 3)); + +gshare_mask_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + + scin => siv1(gshare_mask_offset to gshare_mask_offset+3), + scout => sov1(gshare_mask_offset to gshare_mask_offset+3), + din => gshare_mask_d(0 to 3), + dout => gshare_mask_q(0 to 3)); + +spare_latch: tri_rlmreg_p + generic map (width => spare_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(spare_offset to spare_offset + spare_l2'length-1), + scout => sov1(spare_offset to spare_offset + spare_l2'length-1), + din => spare_l2, + dout => spare_l2); + + + +perv_2to1_reg: tri_plat + generic map (width => 2, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_iu_func_sl_thold_2, + din(1) => pc_iu_sg_2, + q(0) => pc_iu_func_sl_thold_1, + q(1) => pc_iu_sg_1); + +perv_1to0_reg: tri_plat + generic map (width => 2, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_iu_func_sl_thold_1, + din(1) => pc_iu_sg_1, + q(0) => pc_iu_func_sl_thold_0, + q(1) => pc_iu_sg_0); + +perv_lcbor: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_b, + thold => pc_iu_func_sl_thold_0, + sg => pc_iu_sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => pc_iu_func_sl_thold_0_b); + +slat_lcb: tri_lcbs + generic map (expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + delay_lclkr => delay_lclkr, + nclk => nclk, + forcee => forcee, + thold_b => pc_iu_func_sl_thold_0_b, + dclk => dclk, + lclk => lclk ); + +dft_latch: tri_slat_scan + generic map (width => 1, init => "0", expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + dclk => dclk, + lclk => lclk, + scan_in => siv1(dft_offset to dft_offset), + scan_out => sov1(dft_offset to dft_offset), + q => dft_q, + q_b => open); + + + +siv0(0 to scan_right0) <= scan_in(0) & sov0(0 to scan_right0-1); +scan_out(0) <= sov0(scan_right0) and an_ac_scan_dis_dc_b; + +siv1(0 to scan_right1) <= scan_in(1) & sov1(0 to scan_right1-1); +scan_out(1) <= sov1(scan_right1) and an_ac_scan_dis_dc_b; + +end iuq_bp; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_dbg.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_dbg.vhdl new file mode 100644 index 0000000..9fd04f3 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_dbg.vhdl @@ -0,0 +1,338 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; +use ieee.std_logic_1164.all; + +library ibm,clib; +use ibm.std_ulogic_unsigned.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; + +library support; +use support.power_logic_pkg.all; + +library tri; +use tri.tri_latches_pkg.all; + +library work; +use work.iuq_pkg.all; + + +entity iuq_dbg is +generic(expand_type : integer := 2 ); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + pc_iu_func_slp_sl_thold_2 : in std_ulogic; + pc_iu_sg_2 : in std_ulogic; + clkoff_b : in std_ulogic; + act_dis : in std_ulogic; + tc_ac_ccflush_dc : in std_ulogic; + d_mode : in std_ulogic; + delay_lclkr : in std_ulogic; + mpw1_b : in std_ulogic; + mpw2_b : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + fiss_dbg_data : in std_ulogic_vector(0 to 87); + fdep_dbg_data : in std_ulogic_vector(0 to 87); + ib_dbg_data : in std_ulogic_vector(0 to 63); + bp_dbg_data0 : in std_ulogic_vector(0 to 87); + bp_dbg_data1 : in std_ulogic_vector(0 to 87); + fu_iss_dbg_data : in std_ulogic_vector(0 to 23); + axu_dbg_data_t0 : in std_ulogic_vector(0 to 37); + axu_dbg_data_t1 : in std_ulogic_vector(0 to 37); + axu_dbg_data_t2 : in std_ulogic_vector(0 to 37); + axu_dbg_data_t3 : in std_ulogic_vector(0 to 37); + bht_dbg_data : in std_ulogic_vector(0 to 31); + + pc_iu_trace_bus_enable : in std_ulogic; + pc_iu_debug_mux_ctrls : in std_ulogic_vector(0 to 15); + + debug_data_in : in std_ulogic_vector(0 to 87); + trace_triggers_in : in std_ulogic_vector(0 to 11); + + debug_data_out : out std_ulogic_vector(0 to 87); + trace_triggers_out : out std_ulogic_vector(0 to 11) +); + + -- synopsys translate_off + + + -- synopsys translate_on +end iuq_dbg; + + +architecture iuq_dbg of iuq_dbg is + +signal trigger_data_out_d : std_ulogic_vector(0 to 11); +signal trigger_data_out_q : std_ulogic_vector(0 to 11); +signal trace_data_out_d : std_ulogic_vector(0 to 87); +signal trace_data_out_q : std_ulogic_vector(0 to 87); + +constant trigger_data_out_offset: natural := 0; +constant trace_data_out_offset : natural := trigger_data_out_offset + trigger_data_out_q'length; +constant trace_bus_enable_offset: natural := trace_data_out_offset + trace_data_out_q'length; +constant debug_mux_ctrls_offset : natural := trace_bus_enable_offset + 1; +constant scan_right : natural := debug_mux_ctrls_offset + 16-1; + + + + + +signal dbg_group0 : std_ulogic_vector(0 to 87); +signal dbg_group1 : std_ulogic_vector(0 to 87); +signal dbg_group2 : std_ulogic_vector(0 to 87); +signal dbg_group3 : std_ulogic_vector(0 to 87); +signal dbg_group4 : std_ulogic_vector(0 to 87); +signal dbg_group5 : std_ulogic_vector(0 to 87); +signal dbg_group6 : std_ulogic_vector(0 to 87); +signal dbg_group7 : std_ulogic_vector(0 to 87); + +signal trg_group0 : std_ulogic_vector(0 to 11); +signal trg_group1 : std_ulogic_vector(0 to 11); +signal trg_group2 : std_ulogic_vector(0 to 11); +signal trg_group3 : std_ulogic_vector(0 to 11); + +signal siv : std_ulogic_vector(0 to scan_right); +signal sov : std_ulogic_vector(0 to scan_right); + +signal tiup : std_ulogic; + +signal pc_iu_func_slp_sl_thold_1 : std_ulogic; +signal pc_iu_func_slp_sl_thold_0 : std_ulogic; +signal pc_iu_func_slp_sl_thold_0_b : std_ulogic; +signal pc_iu_sg_1 : std_ulogic; +signal pc_iu_sg_0 : std_ulogic; +signal forcee : std_ulogic; + +signal trace_bus_enable_d : std_ulogic; +signal trace_bus_enable_q : std_ulogic; +signal debug_mux_ctrls_d : std_ulogic_vector(0 to 15); +signal debug_mux_ctrls_q : std_ulogic_vector(0 to 15); + +begin + + +tiup <= '1'; + + + + + + + + + +dbg_group0 <= bp_dbg_data0(0 to 87); +dbg_group1 <= bp_dbg_data1(0 to 87); +dbg_group2 <= ib_dbg_data(0 to 63) & fu_iss_dbg_data(0 to 23); +dbg_group3 <= fdep_dbg_data(0 to 87); +dbg_group4 <= fiss_dbg_data(0 to 87); +dbg_group5(0 to 75) <= axu_dbg_data_t0(0 to 37) & axu_dbg_data_t1(0 to 37); +dbg_group6(0 to 75) <= axu_dbg_data_t2(0 to 37) & axu_dbg_data_t3(0 to 37); +dbg_group7(0 to 31) <= bht_dbg_data(0 to 31); + +dbg_group5(76 to 87) <= (others => '0'); +dbg_group6(76 to 87) <= (others => '0'); +dbg_group7(32 to 87) <= (others => '0'); + +trg_group0 <= ib_dbg_data(0) & ib_dbg_data( 4 to 5) & + ib_dbg_data(16) & ib_dbg_data(20 to 21) & + ib_dbg_data(32) & ib_dbg_data(36 to 37) & + ib_dbg_data(48) & ib_dbg_data(52 to 53) ; + +trg_group1 <= fiss_dbg_data(0 to 7) & + fiss_dbg_data(44 to 45) & + bp_dbg_data0(84 to 85); + +trg_group2 <= fdep_dbg_data(14) & fdep_dbg_data(36) & fdep_dbg_data(58) & fdep_dbg_data(80) & + bht_dbg_data(27 to 31) & + bp_dbg_data1(84 to 86) ; + +trg_group3 <= axu_dbg_data_t0(10) & + axu_dbg_data_t1(10) & + axu_dbg_data_t2(10) & + axu_dbg_data_t3(10) & + axu_dbg_data_t0(21) & + axu_dbg_data_t1(21) & + axu_dbg_data_t2(21) & + axu_dbg_data_t3(21) & + fu_iss_dbg_data(20) & + fu_iss_dbg_data(21) & + fu_iss_dbg_data(22) & + fu_iss_dbg_data(23) ; + + +dbg_mux0: entity clib.c_debug_mux8 + port map( + vd => vdd, + gd => gnd, + + select_bits => debug_mux_ctrls_q, + trace_data_in => debug_data_in, + trigger_data_in => trace_triggers_in, + + dbg_group0 => dbg_group0, + dbg_group1 => dbg_group1, + dbg_group2 => dbg_group2, + dbg_group3 => dbg_group3, + dbg_group4 => dbg_group4, + dbg_group5 => dbg_group5, + dbg_group6 => dbg_group6, + dbg_group7 => dbg_group7, + + trg_group0 => trg_group0, + trg_group1 => trg_group1, + trg_group2 => trg_group2, + trg_group3 => trg_group3, + + trace_data_out => trace_data_out_d, + trigger_data_out=> trigger_data_out_d +); + +trace_triggers_out <= trigger_data_out_q; +debug_data_out <= trace_data_out_q; + +trace_bus_enable_d <= pc_iu_trace_bus_enable; +debug_mux_ctrls_d <= pc_iu_debug_mux_ctrls; + +trace_enable_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(trace_bus_enable_offset), + scout => sov(trace_bus_enable_offset), + din => trace_bus_enable_d, + dout => trace_bus_enable_q); + +debug_mux_ctrls_reg: tri_rlmreg_p + generic map (width => debug_mux_ctrls_q'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => trace_bus_enable_q, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(debug_mux_ctrls_offset to debug_mux_ctrls_offset + debug_mux_ctrls_q'length-1), + scout => sov(debug_mux_ctrls_offset to debug_mux_ctrls_offset + debug_mux_ctrls_q'length-1), + din => debug_mux_ctrls_d, + dout => debug_mux_ctrls_q); + +trigger_data_reg: tri_rlmreg_p + generic map (width => trigger_data_out_q'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => trace_bus_enable_q, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(trigger_data_out_offset to trigger_data_out_offset + trigger_data_out_q'length-1), + scout => sov(trigger_data_out_offset to trigger_data_out_offset + trigger_data_out_q'length-1), + din => trigger_data_out_d, + dout => trigger_data_out_q); + +trace_data_reg: tri_rlmreg_p + generic map (width => trace_data_out_q'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => trace_bus_enable_q, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(trace_data_out_offset to trace_data_out_offset + trace_data_out_q'length-1), + scout => sov(trace_data_out_offset to trace_data_out_offset + trace_data_out_q'length-1), + din => trace_data_out_d, + dout => trace_data_out_q); + + +perv_2to1_reg: tri_plat + generic map (width => 2, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_iu_func_slp_sl_thold_2, + din(1) => pc_iu_sg_2, + q(0) => pc_iu_func_slp_sl_thold_1, + q(1) => pc_iu_sg_1); + +perv_1to0_reg: tri_plat + generic map (width => 2, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_iu_func_slp_sl_thold_1, + din(1) => pc_iu_sg_1, + q(0) => pc_iu_func_slp_sl_thold_0, + q(1) => pc_iu_sg_0); + +perv_lcbor: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_b, + thold => pc_iu_func_slp_sl_thold_0, + sg => pc_iu_sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => pc_iu_func_slp_sl_thold_0_b); + +siv(0 to scan_right) <= sov(1 to scan_right) & scan_in; +scan_out <= sov(0); + + +end iuq_dbg; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_fxu_decode.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_fxu_decode.vhdl new file mode 100644 index 0000000..a313d51 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_fxu_decode.vhdl @@ -0,0 +1,4299 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; +use ieee.std_logic_1164.all; +library ibm; +use ibm.std_ulogic_unsigned.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +library support; +use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; +library work; +use work.iuq_pkg.all; + +entity iuq_fxu_decode is + generic(a2mode : integer := 1; + regmode : integer := 6; + expand_type : integer := 2 ); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + + pc_iu_sg_0 : in std_ulogic; + pc_iu_func_sl_thold_0_b : in std_ulogic; + forcee : in std_ulogic; + d_mode : in std_ulogic; + delay_lclkr : in std_ulogic; + mpw1_b : in std_ulogic; + mpw2_b : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + pc_au_ram_mode : in std_ulogic; + pc_au_ram_thread_v : in std_ulogic; + + spr_dec_mask : in std_ulogic_vector(0 to 31); + spr_dec_match : in std_ulogic_vector(0 to 31); + + + au_iu_i_dec_b : in std_ulogic; + iu_au_is1_cr_user_v : out std_ulogic; + iu_au_is0_cr_setter : out std_ulogic; + + au_iu_ib1_ldst : in std_ulogic; + au_iu_ib1_ldst_v : in std_ulogic; + au_iu_ib1_store : in std_ulogic; + au_iu_ib1_ldst_size : in std_ulogic_vector(0 to 5); + au_iu_ib1_ldst_tag : in std_ulogic_vector(0 to 8); + au_iu_ib1_ldst_ra_v : in std_ulogic; + au_iu_ib1_ldst_ra : in std_ulogic_vector(0 to 6); + au_iu_ib1_ldst_rb_v : in std_ulogic; + au_iu_ib1_ldst_rb : in std_ulogic_vector(0 to 6); + au_iu_ib1_ldst_dimm : in std_ulogic_vector(0 to 15); + au_iu_ib1_ldst_indexed : in std_ulogic; + au_iu_ib1_ldst_update : in std_ulogic; + au_iu_ib1_ldst_extpid : in std_ulogic; + au_iu_ib1_ldst_forcealign : in std_ulogic; + au_iu_ib1_ldst_forceexcept : in std_ulogic; + au_iu_ib1_mftgpr : in std_ulogic; + au_iu_ib1_mffgpr : in std_ulogic; + au_iu_ib1_movedp : in std_ulogic; + au_iu_ib1_instr_type : in std_ulogic_vector(0 to 2); + + iu_au_ib1_instr_vld : in std_ulogic; + iu_au_ib1_ifar : in EFF_IFAR; + iu_au_ib1_instr : in std_ulogic_vector(0 to 31); + iu_au_ib1_instr_ucode_ext : in std_ulogic_vector(0 to 3); + iu_au_ib1_instr_pred_vld : in std_ulogic; + iu_au_ib1_instr_pred_taken_cnt : in std_ulogic_vector(0 to 1); + iu_au_ib1_instr_gshare : in std_ulogic_vector(0 to 3); + iu_au_ib1_instr_error : in std_ulogic_vector(0 to 2); + iu_au_ib1_instr_is_ucode : in std_ulogic; + iu_au_ib1_instr_2ucode : in std_ulogic; + iu_au_ib1_instr_2ucode_type : in std_ulogic; + iu_au_ib1_instr_force_ram : in std_ulogic; + + au_iu_is0_to_ucode : in std_ulogic; + au_iu_is0_ucode_only : in std_ulogic; + iu_au_is1_stall : in std_ulogic; + + xu_iu_ib1_flush : in std_ulogic; + fdep_fdec_buff_stall : in std_ulogic; + fdep_fdec_weak_stall : in std_ulogic; + fdec_ibuf_stall : out std_ulogic; + + fdec_fdep_is1_vld : out std_ulogic; + fdec_fdep_is1_instr : out std_ulogic_vector(0 to 31); + fdec_fdep_is1_ta_vld : out std_ulogic; + fdec_fdep_is1_ta : out std_ulogic_vector(0 to 5); + fdec_fdep_is1_s1_vld : out std_ulogic; + fdec_fdep_is1_s1 : out std_ulogic_vector(0 to 5); + fdec_fdep_is1_s2_vld : out std_ulogic; + fdec_fdep_is1_s2 : out std_ulogic_vector(0 to 5); + fdec_fdep_is1_s3_vld : out std_ulogic; + fdec_fdep_is1_s3 : out std_ulogic_vector(0 to 5); + fdec_fdep_is1_pred_update : out std_ulogic; + fdec_fdep_is1_pred_taken_cnt : out std_ulogic_vector(0 to 1); + fdec_fdep_is1_gshare : out std_ulogic_vector(0 to 3); + fdec_fdep_is1_UpdatesLR : out std_ulogic; + fdec_fdep_is1_UpdatesCR : out std_ulogic; + fdec_fdep_is1_UpdatesCTR : out std_ulogic; + fdec_fdep_is1_UpdatesXER : out std_ulogic; + fdec_fdep_is1_UpdatesMSR : out std_ulogic; + fdec_fdep_is1_UpdatesSPR : out std_ulogic; + fdec_fdep_is1_UsesLR : out std_ulogic; + fdec_fdep_is1_UsesCR : out std_ulogic; + fdec_fdep_is1_UsesCTR : out std_ulogic; + fdec_fdep_is1_UsesXER : out std_ulogic; + fdec_fdep_is1_UsesMSR : out std_ulogic; + fdec_fdep_is1_UsesSPR : out std_ulogic; + fdec_fdep_is1_hole_delay : out std_ulogic_vector(0 to 2); + fdec_fdep_is1_ld_vld : out std_ulogic; + fdec_fdep_is1_to_ucode : out std_ulogic; + fdec_fdep_is1_is_ucode : out std_ulogic; + fdec_fdep_is1_ifar : out EFF_IFAR; + fdec_fdep_is1_error : out std_ulogic_vector(0 to 2); + fdec_fdep_is1_complete : out std_ulogic_vector(0 to 4); + fdec_fdep_is1_axu_ld_or_st : out std_ulogic; + fdec_fdep_is1_axu_store : out std_ulogic; + fdec_fdep_is1_axu_ldst_indexed : out std_ulogic; + fdec_fdep_is1_axu_ldst_tag : out std_ulogic_vector(0 to 8); + fdec_fdep_is1_axu_ldst_size : out std_ulogic_vector(0 to 5); + fdec_fdep_is1_axu_ldst_update : out std_ulogic; + fdec_fdep_is1_axu_ldst_extpid : out std_ulogic; + fdec_fdep_is1_axu_ldst_forcealign : out std_ulogic; + fdec_fdep_is1_axu_ldst_forceexcept : out std_ulogic; + fdec_fdep_is1_axu_mftgpr : out std_ulogic; + fdec_fdep_is1_axu_mffgpr : out std_ulogic; + fdec_fdep_is1_axu_movedp : out std_ulogic; + fdec_fdep_is1_axu_instr_type : out std_ulogic_vector(0 to 2); + fdec_fdep_is1_2ucode : out std_ulogic; + fdec_fdep_is1_2ucode_type : out std_ulogic; + fdec_fdep_is1_force_ram : out std_ulogic; + fdec_fdep_is1_match : out std_ulogic +); +end iuq_fxu_decode; +ARCHITECTURE IUQ_FXU_DECODE + OF IUQ_FXU_DECODE + IS +SIGNAL BR_DEP_PT : STD_ULOGIC_VECTOR(1 TO 105) := +(OTHERS=> 'U'); +SIGNAL INSTRUCTION_DECODER1_PT : STD_ULOGIC_VECTOR(1 TO 15) := +(OTHERS=> 'U'); +SIGNAL INSTRUCTION_DECODER2_PT : STD_ULOGIC_VECTOR(1 TO 121) := +(OTHERS=> 'U'); +SIGNAL INSTRUCTION_DECODER_PT : STD_ULOGIC_VECTOR(1 TO 58) := +(OTHERS=> 'U'); +SIGNAL MICROCODE_PT : STD_ULOGIC_VECTOR(1 TO 13) := +(OTHERS=> 'U'); +SIGNAL UpdatesCR : STD_ULOGIC := +'U'; +SIGNAL UpdatesCTR : STD_ULOGIC := +'U'; +SIGNAL UpdatesLR : STD_ULOGIC := +'U'; +SIGNAL UpdatesMSR : STD_ULOGIC := +'U'; +SIGNAL UpdatesSPR : STD_ULOGIC := +'U'; +SIGNAL UpdatesXER : STD_ULOGIC := +'U'; +SIGNAL UsesCR : STD_ULOGIC := +'U'; +SIGNAL UsesCTR : STD_ULOGIC := +'U'; +SIGNAL UsesLR : STD_ULOGIC := +'U'; +SIGNAL UsesMSR : STD_ULOGIC := +'U'; +SIGNAL UsesSPR : STD_ULOGIC := +'U'; +SIGNAL UsesXER : STD_ULOGIC := +'U'; +SIGNAL compl_ex : STD_ULOGIC_VECTOR(1 TO 5) := +"UUUUU"; +SIGNAL hole_delay : STD_ULOGIC_VECTOR(1 TO 3) := +"UUU"; +SIGNAL isFxuIssue : STD_ULOGIC := +'U'; +SIGNAL ld_vld : STD_ULOGIC := +'U'; +SIGNAL s1_sel : STD_ULOGIC := +'U'; +SIGNAL s1_vld : STD_ULOGIC := +'U'; +SIGNAL s2_sel : STD_ULOGIC := +'U'; +SIGNAL s2_vld : STD_ULOGIC := +'U'; +SIGNAL s3_sel : STD_ULOGIC := +'U'; +SIGNAL s3_vld : STD_ULOGIC := +'U'; +SIGNAL ta_sel : STD_ULOGIC := +'U'; +SIGNAL ta_vld : STD_ULOGIC := +'U'; +SIGNAL to_uc : STD_ULOGIC := +'U'; +constant is1_vld_offset : natural := 0; +constant is1_vld_type_offset : natural := is1_vld_offset + 1; +constant is1_instr_offset : natural := is1_vld_type_offset + 3; +constant is1_axu_instr_offset : natural := is1_instr_offset + 32; +constant is1_ta_vld_offset : natural := is1_axu_instr_offset + 26; +constant is1_ta_offset : natural := is1_ta_vld_offset + 1; +constant is1_s1_vld_offset : natural := is1_ta_offset + 6; +constant is1_s1_offset : natural := is1_s1_vld_offset + 1; +constant is1_s2_vld_offset : natural := is1_s1_offset + 6; +constant is1_s2_offset : natural := is1_s2_vld_offset + 1; +constant is1_s3_vld_offset : natural := is1_s2_offset + 6; +constant is1_s3_offset : natural := is1_s3_vld_offset + 1; +constant is1_ld_vld_offset : natural := is1_s3_offset + 6; +constant is1_pred_update_offset : natural := is1_ld_vld_offset + 1; +constant is1_pred_taken_cnt_offset : natural := is1_pred_update_offset + 1; +constant is1_gshare_offset : natural := is1_pred_taken_cnt_offset + 2; +constant is1_UpdatesLR_offset : natural := is1_gshare_offset + 4; +constant is1_UpdatesCR_offset : natural := is1_UpdatesLR_offset + 1; +constant is1_UpdatesCTR_offset : natural := is1_UpdatesCR_offset + 1; +constant is1_UpdatesXER_offset : natural := is1_UpdatesCTR_offset + 1; +constant is1_UpdatesMSR_offset : natural := is1_UpdatesXER_offset + 1; +constant is1_UpdatesSPR_offset : natural := is1_UpdatesMSR_offset + 1; +constant is1_UsesLR_offset : natural := is1_UpdatesSPR_offset + 1; +constant is1_UsesCR_offset : natural := is1_UsesLR_offset + 1; +constant is1_UsesCTR_offset : natural := is1_UsesCR_offset + 1; +constant is1_UsesXER_offset : natural := is1_UsesCTR_offset + 1; +constant is1_UsesMSR_offset : natural := is1_UsesXER_offset + 1; +constant is1_UsesSPR_offset : natural := is1_UsesMSR_offset + 1; +constant is1_to_ucode_offset : natural := is1_UsesSPR_offset + 1; +constant is1_is_ucode_offset : natural := is1_to_ucode_offset + 1; +constant is1_ifar_offset : natural := is1_is_ucode_offset + 1; +constant is1_error_offset : natural := is1_ifar_offset + EFF_IFAR'length; +constant is1_axu_ldst_ra_v_offset : natural := is1_error_offset + 3; +constant is1_axu_ldst_rb_v_offset : natural := is1_axu_ldst_ra_v_offset + 1; +constant is1_axu_ld_or_st_offset : natural := is1_axu_ldst_rb_v_offset + 1; +constant is1_axu_store_offset : natural := is1_axu_ld_or_st_offset + 1; +constant is1_axu_ldst_size_offset : natural := is1_axu_store_offset + 1; +constant is1_axu_ldst_update_offset : natural := is1_axu_ldst_size_offset + 6; +constant is1_axu_ldst_extpid_offset : natural := is1_axu_ldst_update_offset + 1; +constant is1_axu_ldst_forcealign_offset : natural := is1_axu_ldst_extpid_offset + 1; +constant is1_axu_ldst_forceexcept_offset: natural := is1_axu_ldst_forcealign_offset + 1; +constant is1_axu_mftgpr_offset : natural := is1_axu_ldst_forceexcept_offset + 1; +constant is1_axu_mffgpr_offset : natural := is1_axu_mftgpr_offset + 1; +constant is1_axu_movedp_offset : natural := is1_axu_mffgpr_offset + 1; +constant is1_axu_instr_type_offset : natural := is1_axu_movedp_offset + 1; +constant is1_force_ram_offset : natural := is1_axu_instr_type_offset + 3; +constant is1_2ucode_offset : natural := is1_force_ram_offset + 1; +constant is1_2ucode_type_offset : natural := is1_2ucode_offset + 1; +constant spare_offset : natural := is1_2ucode_type_offset + 1; +constant scan_right : natural := spare_offset + 6-1; +signal spare_l2 : std_ulogic_vector(0 to 5); +signal siv : std_ulogic_vector(0 to scan_right); +signal sov : std_ulogic_vector(0 to scan_right); +signal tiup : std_ulogic; +signal is1_vld_d : std_ulogic; +signal is1_vld_type_d : std_ulogic_vector(0 to 2); +signal is1_instr_d : std_ulogic_vector(0 to 31); +signal is1_axu_instr_d : std_ulogic_vector(6 to 31); +signal is1_ta_vld_d : std_ulogic; +signal is1_ta_d : std_ulogic_vector(0 to 5); +signal is1_s1_vld_d : std_ulogic; +signal is1_s1_d : std_ulogic_vector(0 to 5); +signal is1_s2_vld_d : std_ulogic; +signal is1_s2_d : std_ulogic_vector(0 to 5); +signal is1_s3_vld_d : std_ulogic; +signal is1_s3_d : std_ulogic_vector(0 to 5); +signal is1_pred_update_d : std_ulogic; +signal is1_pred_taken_cnt_d : std_ulogic_vector(0 to 1); +signal is1_gshare_d : std_ulogic_vector(0 to 3); +signal is1_UpdatesLR_d : std_ulogic; +signal is1_UpdatesCR_d : std_ulogic; +signal is1_UpdatesCTR_d : std_ulogic; +signal is1_UpdatesXER_d : std_ulogic; +signal is1_UpdatesMSR_d : std_ulogic; +signal is1_UpdatesSPR_d : std_ulogic; +signal is1_UsesLR_d : std_ulogic; +signal is1_UsesCR_d : std_ulogic; +signal is1_UsesCTR_d : std_ulogic; +signal is1_UsesXER_d : std_ulogic; +signal is1_UsesMSR_d : std_ulogic; +signal is1_UsesSPR_d : std_ulogic; +signal is1_ld_vld_d : std_ulogic; +signal is1_to_ucode_d : std_ulogic; +signal is1_is_ucode_d : std_ulogic; +signal is1_ifar_d : EFF_IFAR; +signal is1_error_d : std_ulogic_vector(0 to 2); +signal is1_axu_ld_or_st_d : std_ulogic; +signal is1_axu_store_d : std_ulogic; +signal is1_axu_ldst_size_d : std_ulogic_vector(0 to 5); +signal is1_axu_ldst_update_d : std_ulogic; +signal is1_axu_ldst_extpid_d : std_ulogic; +signal is1_axu_ldst_forcealign_d : std_ulogic; +signal is1_axu_ldst_forceexcept_d : std_ulogic; +signal is1_axu_mftgpr_d : std_ulogic; +signal is1_axu_mffgpr_d : std_ulogic; +signal is1_axu_movedp_d : std_ulogic; +signal is1_axu_instr_type_d : std_ulogic_vector(0 to 2); +signal is1_axu_ldst_ra_v_d : std_ulogic; +signal is1_axu_ldst_rb_v_d : std_ulogic; +signal is1_force_ram_d : std_ulogic; +signal is1_2ucode_d : std_ulogic; +signal is1_2ucode_type_d : std_ulogic; +signal is1_vld_L2 : std_ulogic; +signal is1_vld_type_L2 : std_ulogic_vector(0 to 2); +signal is1_instr_L2 : std_ulogic_vector(0 to 31); +signal is1_axu_instr_L2 : std_ulogic_vector(6 to 31); +signal is1_ta_vld_L2 : std_ulogic; +signal is1_ta_L2 : std_ulogic_vector(0 to 5); +signal is1_s1_vld_L2 : std_ulogic; +signal is1_s1_L2 : std_ulogic_vector(0 to 5); +signal is1_s2_vld_L2 : std_ulogic; +signal is1_s2_L2 : std_ulogic_vector(0 to 5); +signal is1_s3_vld_L2 : std_ulogic; +signal is1_s3_L2 : std_ulogic_vector(0 to 5); +signal is1_pred_update_L2 : std_ulogic; +signal is1_pred_taken_cnt_L2 : std_ulogic_vector(0 to 1); +signal is1_gshare_L2 : std_ulogic_vector(0 to 3); +signal is1_UpdatesLR_L2 : std_ulogic; +signal is1_UpdatesCR_L2 : std_ulogic; +signal is1_UpdatesCTR_L2 : std_ulogic; +signal is1_UpdatesXER_L2 : std_ulogic; +signal is1_UpdatesMSR_L2 : std_ulogic; +signal is1_UpdatesSPR_L2 : std_ulogic; +signal is1_UsesLR_L2 : std_ulogic; +signal is1_UsesCR_L2 : std_ulogic; +signal is1_UsesCTR_L2 : std_ulogic; +signal is1_UsesXER_L2 : std_ulogic; +signal is1_UsesMSR_L2 : std_ulogic; +signal is1_UsesSPR_L2 : std_ulogic; +signal is1_ld_vld_L2 : std_ulogic; +signal is1_to_ucode_L2 : std_ulogic; +signal is1_is_ucode_L2 : std_ulogic; +signal is1_ifar_L2 : EFF_IFAR; +signal is1_error_L2 : std_ulogic_vector(0 to 2); +signal is1_axu_ld_or_st_L2 : std_ulogic; +signal is1_axu_store_L2 : std_ulogic; +signal is1_axu_ldst_size_L2 : std_ulogic_vector(0 to 5); +signal is1_axu_ldst_update_L2 : std_ulogic; +signal is1_axu_ldst_extpid_L2 : std_ulogic; +signal is1_axu_ldst_forcealign_L2 : std_ulogic; +signal is1_axu_ldst_forceexcept_L2 : std_ulogic; +signal is1_axu_mftgpr_L2 : std_ulogic; +signal is1_axu_mffgpr_L2 : std_ulogic; +signal is1_axu_movedp_L2 : std_ulogic; +signal is1_axu_instr_type_L2 : std_ulogic_vector(0 to 2); +signal is1_axu_ldst_ra_v_L2 : std_ulogic; +signal is1_axu_ldst_rb_v_L2 : std_ulogic; +signal is1_force_ram_L2 : std_ulogic; +signal is1_2ucode_L2 : std_ulogic; +signal is1_2ucode_type_L2 : std_ulogic; +signal is1_vld_din : std_ulogic; +signal is1_vld_type_din : std_ulogic_vector(0 to 2); +signal is1_instr_din : std_ulogic_vector(0 to 31); +signal is1_axu_instr_din : std_ulogic_vector(6 to 31); +signal is1_ta_vld_din : std_ulogic; +signal is1_ta_din : std_ulogic_vector(0 to 5); +signal is1_s1_vld_din : std_ulogic; +signal is1_s1_din : std_ulogic_vector(0 to 5); +signal is1_s2_vld_din : std_ulogic; +signal is1_s2_din : std_ulogic_vector(0 to 5); +signal is1_s3_vld_din : std_ulogic; +signal is1_s3_din : std_ulogic_vector(0 to 5); +signal is1_pred_update_din : std_ulogic; +signal is1_pred_taken_cnt_din : std_ulogic_vector(0 to 1); +signal is1_gshare_din : std_ulogic_vector(0 to 3); +signal is1_UpdatesLR_din : std_ulogic; +signal is1_UpdatesCR_din : std_ulogic; +signal is1_UpdatesCTR_din : std_ulogic; +signal is1_UpdatesXER_din : std_ulogic; +signal is1_UpdatesMSR_din : std_ulogic; +signal is1_UpdatesSPR_din : std_ulogic; +signal is1_UsesLR_din : std_ulogic; +signal is1_UsesCR_din : std_ulogic; +signal is1_UsesCTR_din : std_ulogic; +signal is1_UsesXER_din : std_ulogic; +signal is1_UsesMSR_din : std_ulogic; +signal is1_UsesSPR_din : std_ulogic; +signal is1_ld_vld_din : std_ulogic; +signal is1_to_ucode_din : std_ulogic; +signal is1_is_ucode_din : std_ulogic; +signal is1_ifar_din : EFF_IFAR; +signal is1_error_din : std_ulogic_vector(0 to 2); +signal is1_axu_ld_or_st_din : std_ulogic; +signal is1_axu_store_din : std_ulogic; +signal is1_axu_ldst_size_din : std_ulogic_vector(0 to 5); +signal is1_axu_ldst_update_din : std_ulogic; +signal is1_axu_ldst_extpid_din : std_ulogic; +signal is1_axu_ldst_forcealign_din : std_ulogic; +signal is1_axu_ldst_forceexcept_din : std_ulogic; +signal is1_axu_mftgpr_din : std_ulogic; +signal is1_axu_mffgpr_din : std_ulogic; +signal is1_axu_movedp_din : std_ulogic; +signal is1_axu_instr_type_din : std_ulogic_vector(0 to 2); +signal is1_axu_ldst_ra_v_din : std_ulogic; +signal is1_axu_ldst_rb_v_din : std_ulogic; +signal is1_force_ram_din : std_ulogic; +signal is1_2ucode_din : std_ulogic; +signal is1_2ucode_type_din : std_ulogic; +signal act_valid : std_ulogic; +signal act_nonvalid : std_ulogic; +signal is1_ta_d0 : std_ulogic_vector(0 to 5); +signal is1_s1_d0 : std_ulogic_vector(0 to 5); +signal is1_s2_d0 : std_ulogic_vector(0 to 5); +signal is1_s3_d0 : std_ulogic_vector(0 to 5); +signal core64 : std_ulogic; +signal au_iu_i_dec : std_ulogic; +signal au_ib1_ld_or_st : std_ulogic; +signal au_ib1_store : std_ulogic; +signal unused : std_ulogic_vector(0 to 1); +-- synopsys translate_off +-- synopsys translate_on + BEGIN + +unused(0) <= au_iu_ib1_ldst_ra(0); +unused(1) <= au_iu_ib1_ldst_rb(0); +tiup <= '1'; +au_iu_i_dec <= not au_iu_i_dec_b and (not (au_iu_is0_ucode_only and not iu_au_ib1_instr_is_ucode) or (pc_au_ram_mode and pc_au_ram_thread_v)); +au_ib1_ld_or_st <= au_iu_ib1_ldst_v and (not (au_iu_is0_ucode_only and not iu_au_ib1_instr_is_ucode) or (pc_au_ram_mode and pc_au_ram_thread_v)); +au_ib1_store <= au_iu_ib1_store and (not (au_iu_is0_ucode_only and not iu_au_ib1_instr_is_ucode) or (pc_au_ram_mode and pc_au_ram_thread_v)); +fdec_ibuf_stall <= fdep_fdec_buff_stall and iu_au_ib1_instr_vld and not xu_iu_ib1_flush; +c64: if (regmode = 6) generate +begin +core64 <= '1'; +end generate; +c32: if (regmode = 5) generate +begin +core64 <= '0'; +end generate; +MQQ1:BR_DEP_PT(1) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(11) & IU_AU_IB1_INSTR(12) & + IU_AU_IB1_INSTR(13) & IU_AU_IB1_INSTR(14) & + IU_AU_IB1_INSTR(15) & IU_AU_IB1_INSTR(16) & + IU_AU_IB1_INSTR(17) & IU_AU_IB1_INSTR(18) & + IU_AU_IB1_INSTR(19) & IU_AU_IB1_INSTR(20) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("01111101000000000111010011")); +MQQ2:BR_DEP_PT(2) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(11) & IU_AU_IB1_INSTR(12) & + IU_AU_IB1_INSTR(13) & IU_AU_IB1_INSTR(14) & + IU_AU_IB1_INSTR(15) & IU_AU_IB1_INSTR(16) & + IU_AU_IB1_INSTR(17) & IU_AU_IB1_INSTR(18) & + IU_AU_IB1_INSTR(19) & IU_AU_IB1_INSTR(20) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("01111101001000000111010011")); +MQQ3:BR_DEP_PT(3) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(11) & IU_AU_IB1_INSTR(12) & + IU_AU_IB1_INSTR(13) & IU_AU_IB1_INSTR(14) & + IU_AU_IB1_INSTR(15) & IU_AU_IB1_INSTR(16) & + IU_AU_IB1_INSTR(17) & IU_AU_IB1_INSTR(18) & + IU_AU_IB1_INSTR(19) & IU_AU_IB1_INSTR(20) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("01111101000000000101010011")); +MQQ4:BR_DEP_PT(4) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(11) & IU_AU_IB1_INSTR(12) & + IU_AU_IB1_INSTR(13) & IU_AU_IB1_INSTR(14) & + IU_AU_IB1_INSTR(15) & IU_AU_IB1_INSTR(16) & + IU_AU_IB1_INSTR(17) & IU_AU_IB1_INSTR(18) & + IU_AU_IB1_INSTR(19) & IU_AU_IB1_INSTR(20) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("01111101001000000101010011")); +MQQ5:BR_DEP_PT(5) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(11) & IU_AU_IB1_INSTR(12) & + IU_AU_IB1_INSTR(13) & IU_AU_IB1_INSTR(14) & + IU_AU_IB1_INSTR(15) & IU_AU_IB1_INSTR(16) & + IU_AU_IB1_INSTR(17) & IU_AU_IB1_INSTR(18) & + IU_AU_IB1_INSTR(19) & IU_AU_IB1_INSTR(20) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("01111100001000000111010011")); +MQQ6:BR_DEP_PT(6) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(11) & + IU_AU_IB1_INSTR(12) & IU_AU_IB1_INSTR(13) & + IU_AU_IB1_INSTR(14) & IU_AU_IB1_INSTR(15) & + IU_AU_IB1_INSTR(16) & IU_AU_IB1_INSTR(17) & + IU_AU_IB1_INSTR(18) & IU_AU_IB1_INSTR(19) & + IU_AU_IB1_INSTR(20) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("0111100001000000101010011")); +MQQ7:BR_DEP_PT(7) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) & IU_AU_IB1_INSTR(31) + ) , STD_ULOGIC_VECTOR'("0100100000100001")); +MQQ8:BR_DEP_PT(8) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(8) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("01001111000010000")); +MQQ9:BR_DEP_PT(9) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(8) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) & IU_AU_IB1_INSTR(31) + ) , STD_ULOGIC_VECTOR'("0100110000100001")); +MQQ10:BR_DEP_PT(10) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(8) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("01001100000010000")); +MQQ11:BR_DEP_PT(11) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("010011000100110")); +MQQ12:BR_DEP_PT(12) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("0100110000010000")); +MQQ13:BR_DEP_PT(13) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("0111111110110110")); +MQQ14:BR_DEP_PT(14) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) & + IU_AU_IB1_INSTR(31) ) , STD_ULOGIC_VECTOR'("011111101101101")); +MQQ15:BR_DEP_PT(15) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(20) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("01111110111010011")); +MQQ16:BR_DEP_PT(16) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(19) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("01111110111010011")); +MQQ17:BR_DEP_PT(17) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(18) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("01111110111010011")); +MQQ18:BR_DEP_PT(18) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(17) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("01111110111010011")); +MQQ19:BR_DEP_PT(19) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(16) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("01111110111010011")); +MQQ20:BR_DEP_PT(20) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(14) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("01111110111010011")); +MQQ21:BR_DEP_PT(21) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(13) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("01111110111010011")); +MQQ22:BR_DEP_PT(22) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(11) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("01111110111010011")); +MQQ23:BR_DEP_PT(23) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("0100110000000000")); +MQQ24:BR_DEP_PT(24) <= + Eq(( CORE64 & IU_AU_IB1_INSTR(0) & + IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) + ) , STD_ULOGIC_VECTOR'("1011111110011101")); +MQQ25:BR_DEP_PT(25) <= + Eq(( CORE64 & IU_AU_IB1_INSTR(0) & + IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(31) ) , STD_ULOGIC_VECTOR'("101111100111011")); +MQQ26:BR_DEP_PT(26) <= + Eq(( CORE64 & IU_AU_IB1_INSTR(0) & + IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) ) , STD_ULOGIC_VECTOR'("101111110111010")); +MQQ27:BR_DEP_PT(27) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) & + IU_AU_IB1_INSTR(31) ) , STD_ULOGIC_VECTOR'("01111100110101001")); +MQQ28:BR_DEP_PT(28) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("010011000100001")); +MQQ29:BR_DEP_PT(29) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("010011010100001")); +MQQ30:BR_DEP_PT(30) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) ) , STD_ULOGIC_VECTOR'("010011000011001")); +MQQ31:BR_DEP_PT(31) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("011111100101000")); +MQQ32:BR_DEP_PT(32) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("010011001100001")); +MQQ33:BR_DEP_PT(33) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("0111110110010110")); +MQQ34:BR_DEP_PT(34) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("011111111000110")); +MQQ35:BR_DEP_PT(35) <= + Eq(( CORE64 & IU_AU_IB1_INSTR(0) & + IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(30) & + IU_AU_IB1_INSTR(31) ) , STD_ULOGIC_VECTOR'("101110011010101")); +MQQ36:BR_DEP_PT(36) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("010011011000001")); +MQQ37:BR_DEP_PT(37) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) ) , STD_ULOGIC_VECTOR'("011111101110101")); +MQQ38:BR_DEP_PT(38) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("010011001000001")); +MQQ39:BR_DEP_PT(39) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("010011010000001")); +MQQ40:BR_DEP_PT(40) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(20) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("0111111010110011")); +MQQ41:BR_DEP_PT(41) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(19) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("0111111010110011")); +MQQ42:BR_DEP_PT(42) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(18) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("0111111010110011")); +MQQ43:BR_DEP_PT(43) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(17) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("0111111010110011")); +MQQ44:BR_DEP_PT(44) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(16) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("0111111010110011")); +MQQ45:BR_DEP_PT(45) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(14) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("0111111010110011")); +MQQ46:BR_DEP_PT(46) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(13) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("0111111010110011")); +MQQ47:BR_DEP_PT(47) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(11) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("0111111010110011")); +MQQ48:BR_DEP_PT(48) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("011111110000110")); +MQQ49:BR_DEP_PT(49) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("0111110101110011")); +MQQ50:BR_DEP_PT(50) <= + Eq(( CORE64 & IU_AU_IB1_INSTR(0) & + IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("101111111001100")); +MQQ51:BR_DEP_PT(51) <= + Eq(( CORE64 & IU_AU_IB1_INSTR(0) & + IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(30) & IU_AU_IB1_INSTR(31) + ) , STD_ULOGIC_VECTOR'("10111110011001")); +MQQ52:BR_DEP_PT(52) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("0111110001010011")); +MQQ53:BR_DEP_PT(53) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("011111110011000")); +MQQ54:BR_DEP_PT(54) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("0111110010010010")); +MQQ55:BR_DEP_PT(55) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("011111100001010")); +MQQ56:BR_DEP_PT(56) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) & IU_AU_IB1_INSTR(31) + ) , STD_ULOGIC_VECTOR'("01111100110001")); +MQQ57:BR_DEP_PT(57) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("0111110000010011")); +MQQ58:BR_DEP_PT(58) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("01111100010101")); +MQQ59:BR_DEP_PT(59) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) & IU_AU_IB1_INSTR(31) + ) , STD_ULOGIC_VECTOR'("01110001111001")); +MQQ60:BR_DEP_PT(60) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("0111111000000000")); +MQQ61:BR_DEP_PT(61) <= + Eq(( CORE64 & IU_AU_IB1_INSTR(0) & + IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("10111111110101")); +MQQ62:BR_DEP_PT(62) <= + Eq(( CORE64 & IU_AU_IB1_INSTR(0) & + IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) & + IU_AU_IB1_INSTR(31) ) , STD_ULOGIC_VECTOR'("101111110110101")); +MQQ63:BR_DEP_PT(63) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) & + IU_AU_IB1_INSTR(31) ) , STD_ULOGIC_VECTOR'("011111010100101")); +MQQ64:BR_DEP_PT(64) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("011111001000011")); +MQQ65:BR_DEP_PT(65) <= + Eq(( CORE64 & IU_AU_IB1_INSTR(0) & + IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) & + IU_AU_IB1_INSTR(31) ) , STD_ULOGIC_VECTOR'("101110000110101")); +MQQ66:BR_DEP_PT(66) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("011110010010000")); +MQQ67:BR_DEP_PT(67) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) & IU_AU_IB1_INSTR(31) + ) , STD_ULOGIC_VECTOR'("01110110111001")); +MQQ68:BR_DEP_PT(68) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) & + IU_AU_IB1_INSTR(31) ) , STD_ULOGIC_VECTOR'("011100100100111")); +MQQ69:BR_DEP_PT(69) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("01111111101011")); +MQQ70:BR_DEP_PT(70) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) & IU_AU_IB1_INSTR(31) + ) , STD_ULOGIC_VECTOR'("01111110010101")); +MQQ71:BR_DEP_PT(71) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(30) & IU_AU_IB1_INSTR(31) + ) , STD_ULOGIC_VECTOR'("011101101001")); +MQQ72:BR_DEP_PT(72) <= + Eq(( CORE64 & IU_AU_IB1_INSTR(0) & + IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) & IU_AU_IB1_INSTR(31) + ) , STD_ULOGIC_VECTOR'("10111000010111")); +MQQ73:BR_DEP_PT(73) <= + Eq(( CORE64 & IU_AU_IB1_INSTR(0) & + IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(31) ) , STD_ULOGIC_VECTOR'("1011101110101")); +MQQ74:BR_DEP_PT(74) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) & IU_AU_IB1_INSTR(31) + ) , STD_ULOGIC_VECTOR'("01110100101101")); +MQQ75:BR_DEP_PT(75) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(30) & IU_AU_IB1_INSTR(31) + ) , STD_ULOGIC_VECTOR'("011101001001")); +MQQ76:BR_DEP_PT(76) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) & IU_AU_IB1_INSTR(31) + ) , STD_ULOGIC_VECTOR'("01111110110101")); +MQQ77:BR_DEP_PT(77) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) & + IU_AU_IB1_INSTR(31) ) , STD_ULOGIC_VECTOR'("0111000111001")); +MQQ78:BR_DEP_PT(78) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) & + IU_AU_IB1_INSTR(31) ) , STD_ULOGIC_VECTOR'("0111010111001")); +MQQ79:BR_DEP_PT(79) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) & + IU_AU_IB1_INSTR(31) ) , STD_ULOGIC_VECTOR'("0111001010001")); +MQQ80:BR_DEP_PT(80) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(31) ) , STD_ULOGIC_VECTOR'("0111011101011")); +MQQ81:BR_DEP_PT(81) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("0111110000100")); +MQQ82:BR_DEP_PT(82) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("01111000000000")); +MQQ83:BR_DEP_PT(83) <= + Eq(( CORE64 & IU_AU_IB1_INSTR(0) & + IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(30) & + IU_AU_IB1_INSTR(31) ) , STD_ULOGIC_VECTOR'("1011100001011")); +MQQ84:BR_DEP_PT(84) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) & + IU_AU_IB1_INSTR(31) ) , STD_ULOGIC_VECTOR'("0111000010001")); +MQQ85:BR_DEP_PT(85) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("011110100100")); +MQQ86:BR_DEP_PT(86) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("0111110110100")); +MQQ87:BR_DEP_PT(87) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) & + IU_AU_IB1_INSTR(31) ) , STD_ULOGIC_VECTOR'("0111000010101")); +MQQ88:BR_DEP_PT(88) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) & + IU_AU_IB1_INSTR(31) ) , STD_ULOGIC_VECTOR'("0111000010111")); +MQQ89:BR_DEP_PT(89) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(8) ) , STD_ULOGIC_VECTOR'("0100000")); +MQQ90:BR_DEP_PT(90) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(30) & + IU_AU_IB1_INSTR(31) ) , STD_ULOGIC_VECTOR'("0111000001001")); +MQQ91:BR_DEP_PT(91) <= + Eq(( CORE64 & IU_AU_IB1_INSTR(0) & + IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(30) & IU_AU_IB1_INSTR(31) + ) , STD_ULOGIC_VECTOR'("101111101011")); +MQQ92:BR_DEP_PT(92) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("01111101111")); +MQQ93:BR_DEP_PT(93) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) & + IU_AU_IB1_INSTR(31) ) , STD_ULOGIC_VECTOR'("0111000000111")); +MQQ94:BR_DEP_PT(94) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) & IU_AU_IB1_INSTR(31) + ) , STD_ULOGIC_VECTOR'("011111010111")); +MQQ95:BR_DEP_PT(95) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) + ) , STD_ULOGIC_VECTOR'("010000")); +MQQ96:BR_DEP_PT(96) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(31) + ) , STD_ULOGIC_VECTOR'("010001")); +MQQ97:BR_DEP_PT(97) <= + Eq(( CORE64 & IU_AU_IB1_INSTR(0) & + IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(31) ) , STD_ULOGIC_VECTOR'("101110001")); +MQQ98:BR_DEP_PT(98) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) ) , STD_ULOGIC_VECTOR'("00100")); +MQQ99:BR_DEP_PT(99) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("0100011")); +MQQ100:BR_DEP_PT(100) <= + Eq(( CORE64 & IU_AU_IB1_INSTR(0) & + IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(31) + ) , STD_ULOGIC_VECTOR'("10111001")); +MQQ101:BR_DEP_PT(101) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) ) , STD_ULOGIC_VECTOR'("00101")); +MQQ102:BR_DEP_PT(102) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) + ) , STD_ULOGIC_VECTOR'("001101")); +MQQ103:BR_DEP_PT(103) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(31) ) , STD_ULOGIC_VECTOR'("01101")); +MQQ104:BR_DEP_PT(104) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(31) + ) , STD_ULOGIC_VECTOR'("010111")); +MQQ105:BR_DEP_PT(105) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) ) , STD_ULOGIC_VECTOR'("01110")); +MQQ106:UPDATESLR <= + (BR_DEP_PT(1) OR BR_DEP_PT(7) + OR BR_DEP_PT(9) OR BR_DEP_PT(96) + ); +MQQ107:UPDATESCR <= + (BR_DEP_PT(14) OR BR_DEP_PT(23) + OR BR_DEP_PT(25) OR BR_DEP_PT(27) + OR BR_DEP_PT(28) OR BR_DEP_PT(29) + OR BR_DEP_PT(32) OR BR_DEP_PT(35) + OR BR_DEP_PT(36) OR BR_DEP_PT(38) + OR BR_DEP_PT(39) OR BR_DEP_PT(48) + OR BR_DEP_PT(51) OR BR_DEP_PT(56) + OR BR_DEP_PT(59) OR BR_DEP_PT(60) + OR BR_DEP_PT(62) OR BR_DEP_PT(63) + OR BR_DEP_PT(65) OR BR_DEP_PT(66) + OR BR_DEP_PT(67) OR BR_DEP_PT(68) + OR BR_DEP_PT(70) OR BR_DEP_PT(71) + OR BR_DEP_PT(72) OR BR_DEP_PT(73) + OR BR_DEP_PT(74) OR BR_DEP_PT(75) + OR BR_DEP_PT(76) OR BR_DEP_PT(77) + OR BR_DEP_PT(78) OR BR_DEP_PT(79) + OR BR_DEP_PT(80) OR BR_DEP_PT(82) + OR BR_DEP_PT(83) OR BR_DEP_PT(84) + OR BR_DEP_PT(87) OR BR_DEP_PT(88) + OR BR_DEP_PT(90) OR BR_DEP_PT(91) + OR BR_DEP_PT(93) OR BR_DEP_PT(94) + OR BR_DEP_PT(97) OR BR_DEP_PT(100) + OR BR_DEP_PT(101) OR BR_DEP_PT(102) + OR BR_DEP_PT(103) OR BR_DEP_PT(104) + OR BR_DEP_PT(105)); +MQQ108:UPDATESCTR <= + (BR_DEP_PT(2) OR BR_DEP_PT(10) + OR BR_DEP_PT(89)); +MQQ109:UPDATESXER <= + (BR_DEP_PT(5) OR BR_DEP_PT(24) + OR BR_DEP_PT(26) OR BR_DEP_PT(31) + OR BR_DEP_PT(37) OR BR_DEP_PT(50) + OR BR_DEP_PT(53) OR BR_DEP_PT(55) + OR BR_DEP_PT(60) OR BR_DEP_PT(61) + OR BR_DEP_PT(69) OR BR_DEP_PT(81) + OR BR_DEP_PT(86) OR BR_DEP_PT(98) + OR BR_DEP_PT(102)); +MQQ110:UPDATESMSR <= + (BR_DEP_PT(11) OR BR_DEP_PT(30) + OR BR_DEP_PT(54) OR BR_DEP_PT(64) + OR BR_DEP_PT(99)); +MQQ111:UPDATESSPR <= + (BR_DEP_PT(15) OR BR_DEP_PT(16) + OR BR_DEP_PT(17) OR BR_DEP_PT(18) + OR BR_DEP_PT(19) OR BR_DEP_PT(20) + OR BR_DEP_PT(21) OR BR_DEP_PT(22) + OR BR_DEP_PT(27) OR BR_DEP_PT(99) + ); +MQQ112:USESLR <= + (BR_DEP_PT(3) OR BR_DEP_PT(12) + ); +MQQ113:USESCR <= + (BR_DEP_PT(8) OR BR_DEP_PT(12) + OR BR_DEP_PT(23) OR BR_DEP_PT(28) + OR BR_DEP_PT(29) OR BR_DEP_PT(32) + OR BR_DEP_PT(36) OR BR_DEP_PT(38) + OR BR_DEP_PT(39) OR BR_DEP_PT(57) + OR BR_DEP_PT(92) OR BR_DEP_PT(95) + ); +MQQ114:USESCTR <= + (BR_DEP_PT(4) OR BR_DEP_PT(8) + OR BR_DEP_PT(10) OR BR_DEP_PT(89) + ); +MQQ115:USESXER <= + (BR_DEP_PT(6) OR BR_DEP_PT(14) + OR BR_DEP_PT(25) OR BR_DEP_PT(27) + OR BR_DEP_PT(35) OR BR_DEP_PT(48) + OR BR_DEP_PT(51) OR BR_DEP_PT(56) + OR BR_DEP_PT(58) OR BR_DEP_PT(59) + OR BR_DEP_PT(60) OR BR_DEP_PT(62) + OR BR_DEP_PT(65) OR BR_DEP_PT(67) + OR BR_DEP_PT(72) OR BR_DEP_PT(73) + OR BR_DEP_PT(74) OR BR_DEP_PT(76) + OR BR_DEP_PT(77) OR BR_DEP_PT(78) + OR BR_DEP_PT(79) OR BR_DEP_PT(80) + OR BR_DEP_PT(82) OR BR_DEP_PT(83) + OR BR_DEP_PT(84) OR BR_DEP_PT(85) + OR BR_DEP_PT(86) OR BR_DEP_PT(87) + OR BR_DEP_PT(88) OR BR_DEP_PT(90) + OR BR_DEP_PT(91) OR BR_DEP_PT(93) + OR BR_DEP_PT(94) OR BR_DEP_PT(97) + OR BR_DEP_PT(100) OR BR_DEP_PT(101) + OR BR_DEP_PT(102) OR BR_DEP_PT(103) + OR BR_DEP_PT(104) OR BR_DEP_PT(105) + ); +MQQ116:USESMSR <= + (BR_DEP_PT(13) OR BR_DEP_PT(33) + OR BR_DEP_PT(52) OR BR_DEP_PT(99) + ); +MQQ117:USESSPR <= + (BR_DEP_PT(11) OR BR_DEP_PT(13) + OR BR_DEP_PT(30) OR BR_DEP_PT(33) + OR BR_DEP_PT(34) OR BR_DEP_PT(40) + OR BR_DEP_PT(41) OR BR_DEP_PT(42) + OR BR_DEP_PT(43) OR BR_DEP_PT(44) + OR BR_DEP_PT(45) OR BR_DEP_PT(46) + OR BR_DEP_PT(47) OR BR_DEP_PT(49) + ); + +MQQ118:INSTRUCTION_DECODER_PT(1) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(6) & IU_AU_IB1_INSTR(7) & + IU_AU_IB1_INSTR(8) & IU_AU_IB1_INSTR(9) & + IU_AU_IB1_INSTR(10) & IU_AU_IB1_INSTR(11) & + IU_AU_IB1_INSTR(12) & IU_AU_IB1_INSTR(13) & + IU_AU_IB1_INSTR(14) & IU_AU_IB1_INSTR(15) & + IU_AU_IB1_INSTR(16) & IU_AU_IB1_INSTR(17) & + IU_AU_IB1_INSTR(18) & IU_AU_IB1_INSTR(19) & + IU_AU_IB1_INSTR(20) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) & IU_AU_IB1_INSTR(31) + ) , STD_ULOGIC_VECTOR'("100000000000000000000000000000")); +MQQ119:INSTRUCTION_DECODER_PT(2) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(29) + ) , STD_ULOGIC_VECTOR'("111110011011")); +MQQ120:INSTRUCTION_DECODER_PT(3) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) ) , STD_ULOGIC_VECTOR'("111110000")); +MQQ121:INSTRUCTION_DECODER_PT(4) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("11111001001")); +MQQ122:INSTRUCTION_DECODER_PT(5) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(28) ) , STD_ULOGIC_VECTOR'("11111100011")); +MQQ123:INSTRUCTION_DECODER_PT(6) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("11111100111")); +MQQ124:INSTRUCTION_DECODER_PT(7) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("11111010100")); +MQQ125:INSTRUCTION_DECODER_PT(8) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("1111111000")); +MQQ126:INSTRUCTION_DECODER_PT(9) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("11111001101")); +MQQ127:INSTRUCTION_DECODER_PT(10) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("1111100111")); +MQQ128:INSTRUCTION_DECODER_PT(11) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(29) + ) , STD_ULOGIC_VECTOR'("1111101001")); +MQQ129:INSTRUCTION_DECODER_PT(12) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("11111010110")); +MQQ130:INSTRUCTION_DECODER_PT(13) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(28) ) , STD_ULOGIC_VECTOR'("111111010")); +MQQ131:INSTRUCTION_DECODER_PT(14) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) + ) , STD_ULOGIC_VECTOR'("1111101100")); +MQQ132:INSTRUCTION_DECODER_PT(15) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) + ) , STD_ULOGIC_VECTOR'("1111101000")); +MQQ133:INSTRUCTION_DECODER_PT(16) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("1111111000")); +MQQ134:INSTRUCTION_DECODER_PT(17) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("1111111000")); +MQQ135:INSTRUCTION_DECODER_PT(18) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("11111101001")); +MQQ136:INSTRUCTION_DECODER_PT(19) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("11111101010")); +MQQ137:INSTRUCTION_DECODER_PT(20) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("1111111001")); +MQQ138:INSTRUCTION_DECODER_PT(21) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("1111110110")); +MQQ139:INSTRUCTION_DECODER_PT(22) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("11110000")); +MQQ140:INSTRUCTION_DECODER_PT(23) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) + ) , STD_ULOGIC_VECTOR'("1111101000")); +MQQ141:INSTRUCTION_DECODER_PT(24) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(28) + ) , STD_ULOGIC_VECTOR'("1111110111")); +MQQ142:INSTRUCTION_DECODER_PT(25) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("1111100011")); +MQQ143:INSTRUCTION_DECODER_PT(26) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("1111111101")); +MQQ144:INSTRUCTION_DECODER_PT(27) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) + ) , STD_ULOGIC_VECTOR'("1111111111")); +MQQ145:INSTRUCTION_DECODER_PT(28) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("011111110")); +MQQ146:INSTRUCTION_DECODER_PT(29) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(29) + ) , STD_ULOGIC_VECTOR'("01110110")); +MQQ147:INSTRUCTION_DECODER_PT(30) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(27) + ) , STD_ULOGIC_VECTOR'("01111001")); +MQQ148:INSTRUCTION_DECODER_PT(31) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) + ) , STD_ULOGIC_VECTOR'("01110010")); +MQQ149:INSTRUCTION_DECODER_PT(32) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) ) , STD_ULOGIC_VECTOR'("111111000")); +MQQ150:INSTRUCTION_DECODER_PT(33) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) ) , STD_ULOGIC_VECTOR'("111111000")); +MQQ151:INSTRUCTION_DECODER_PT(34) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("111111111")); +MQQ152:INSTRUCTION_DECODER_PT(35) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) ) , STD_ULOGIC_VECTOR'("111111100")); +MQQ153:INSTRUCTION_DECODER_PT(36) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(28) ) , STD_ULOGIC_VECTOR'("1111101")); +MQQ154:INSTRUCTION_DECODER_PT(37) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("11111011")); +MQQ155:INSTRUCTION_DECODER_PT(38) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(27) + ) , STD_ULOGIC_VECTOR'("11110100")); +MQQ156:INSTRUCTION_DECODER_PT(39) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("111110010")); +MQQ157:INSTRUCTION_DECODER_PT(40) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) ) , STD_ULOGIC_VECTOR'("0111011")); +MQQ158:INSTRUCTION_DECODER_PT(41) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) ) , STD_ULOGIC_VECTOR'("10110")); +MQQ159:INSTRUCTION_DECODER_PT(42) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(4) + ) , STD_ULOGIC_VECTOR'("0000")); +MQQ160:INSTRUCTION_DECODER_PT(43) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) + ) , STD_ULOGIC_VECTOR'("11111100")); +MQQ161:INSTRUCTION_DECODER_PT(44) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("11111000")); +MQQ162:INSTRUCTION_DECODER_PT(45) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(27) + ) , STD_ULOGIC_VECTOR'("011101")); +MQQ163:INSTRUCTION_DECODER_PT(46) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) + ) , STD_ULOGIC_VECTOR'("0001")); +MQQ164:INSTRUCTION_DECODER_PT(47) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("111011")); +MQQ165:INSTRUCTION_DECODER_PT(48) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("111011")); +MQQ166:INSTRUCTION_DECODER_PT(49) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(5) + ) , STD_ULOGIC_VECTOR'("0010")); +MQQ167:INSTRUCTION_DECODER_PT(50) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) + ) , STD_ULOGIC_VECTOR'("1100")); +MQQ168:INSTRUCTION_DECODER_PT(51) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(5) + ) , STD_ULOGIC_VECTOR'("1010")); +MQQ169:INSTRUCTION_DECODER_PT(52) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(3) + ) , STD_ULOGIC_VECTOR'("10")); +MQQ170:INSTRUCTION_DECODER_PT(53) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(31) + ) , STD_ULOGIC_VECTOR'("1110")); +MQQ171:INSTRUCTION_DECODER_PT(54) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) ) , STD_ULOGIC_VECTOR'("11111")); +MQQ172:INSTRUCTION_DECODER_PT(55) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) ) , STD_ULOGIC_VECTOR'("100")); +MQQ173:INSTRUCTION_DECODER_PT(56) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(5) ) , STD_ULOGIC_VECTOR'("111")); +MQQ174:INSTRUCTION_DECODER_PT(57) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) ) , STD_ULOGIC_VECTOR'("111")); +MQQ175:INSTRUCTION_DECODER_PT(58) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) + ) , STD_ULOGIC_VECTOR'("1011")); +MQQ176:TA_VLD <= NOT ( + (INSTRUCTION_DECODER_PT(1) OR INSTRUCTION_DECODER_PT(2) + OR INSTRUCTION_DECODER_PT(6) OR INSTRUCTION_DECODER_PT(9) + OR INSTRUCTION_DECODER_PT(12) OR INSTRUCTION_DECODER_PT(18) + OR INSTRUCTION_DECODER_PT(19) OR INSTRUCTION_DECODER_PT(20) + OR INSTRUCTION_DECODER_PT(21) OR INSTRUCTION_DECODER_PT(23) + OR INSTRUCTION_DECODER_PT(24) OR INSTRUCTION_DECODER_PT(27) + OR INSTRUCTION_DECODER_PT(28) OR INSTRUCTION_DECODER_PT(34) + OR INSTRUCTION_DECODER_PT(35) OR INSTRUCTION_DECODER_PT(39) + OR INSTRUCTION_DECODER_PT(42) OR INSTRUCTION_DECODER_PT(43) + OR INSTRUCTION_DECODER_PT(44) OR INSTRUCTION_DECODER_PT(46) + OR INSTRUCTION_DECODER_PT(50) OR INSTRUCTION_DECODER_PT(51) + OR INSTRUCTION_DECODER_PT(53) OR INSTRUCTION_DECODER_PT(54) + OR INSTRUCTION_DECODER_PT(55))); +MQQ177:S1_VLD <= NOT ( + (INSTRUCTION_DECODER_PT(1) OR INSTRUCTION_DECODER_PT(4) + OR INSTRUCTION_DECODER_PT(8) OR INSTRUCTION_DECODER_PT(11) + OR INSTRUCTION_DECODER_PT(14) OR INSTRUCTION_DECODER_PT(15) + OR INSTRUCTION_DECODER_PT(16) OR INSTRUCTION_DECODER_PT(17) + OR INSTRUCTION_DECODER_PT(21) OR INSTRUCTION_DECODER_PT(24) + OR INSTRUCTION_DECODER_PT(28) OR INSTRUCTION_DECODER_PT(32) + OR INSTRUCTION_DECODER_PT(33) OR INSTRUCTION_DECODER_PT(42) + OR INSTRUCTION_DECODER_PT(55))); +MQQ178:S2_VLD <= + (INSTRUCTION_DECODER_PT(2) OR INSTRUCTION_DECODER_PT(3) + OR INSTRUCTION_DECODER_PT(5) OR INSTRUCTION_DECODER_PT(7) + OR INSTRUCTION_DECODER_PT(9) OR INSTRUCTION_DECODER_PT(12) + OR INSTRUCTION_DECODER_PT(13) OR INSTRUCTION_DECODER_PT(18) + OR INSTRUCTION_DECODER_PT(19) OR INSTRUCTION_DECODER_PT(22) + OR INSTRUCTION_DECODER_PT(25) OR INSTRUCTION_DECODER_PT(26) + OR INSTRUCTION_DECODER_PT(27) OR INSTRUCTION_DECODER_PT(29) + OR INSTRUCTION_DECODER_PT(30) OR INSTRUCTION_DECODER_PT(31) + OR INSTRUCTION_DECODER_PT(34) OR INSTRUCTION_DECODER_PT(36) + OR INSTRUCTION_DECODER_PT(37) OR INSTRUCTION_DECODER_PT(38) + OR INSTRUCTION_DECODER_PT(39) OR INSTRUCTION_DECODER_PT(40) + OR INSTRUCTION_DECODER_PT(45) OR INSTRUCTION_DECODER_PT(47) + OR INSTRUCTION_DECODER_PT(48) OR INSTRUCTION_DECODER_PT(49) + OR INSTRUCTION_DECODER_PT(58)); +MQQ179:S3_VLD <= + (INSTRUCTION_DECODER_PT(2) OR INSTRUCTION_DECODER_PT(6) + OR INSTRUCTION_DECODER_PT(18) OR INSTRUCTION_DECODER_PT(19) + OR INSTRUCTION_DECODER_PT(20) OR INSTRUCTION_DECODER_PT(23) + OR INSTRUCTION_DECODER_PT(26) OR INSTRUCTION_DECODER_PT(50) + OR INSTRUCTION_DECODER_PT(51) OR INSTRUCTION_DECODER_PT(56) + OR INSTRUCTION_DECODER_PT(57)); +MQQ180:LD_VLD <= + (INSTRUCTION_DECODER_PT(5) OR INSTRUCTION_DECODER_PT(7) + OR INSTRUCTION_DECODER_PT(10) OR INSTRUCTION_DECODER_PT(25) + OR INSTRUCTION_DECODER_PT(41) OR INSTRUCTION_DECODER_PT(52) + ); + +MQQ181:INSTRUCTION_DECODER1_PT(1) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("1101100")); +MQQ182:INSTRUCTION_DECODER1_PT(2) <= + Eq(( IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) ) , STD_ULOGIC_VECTOR'("10100")); +MQQ183:INSTRUCTION_DECODER1_PT(3) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("011001")); +MQQ184:INSTRUCTION_DECODER1_PT(4) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(28) ) , STD_ULOGIC_VECTOR'("1111110")); +MQQ185:INSTRUCTION_DECODER1_PT(5) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(28) ) , STD_ULOGIC_VECTOR'("1111110")); +MQQ186:INSTRUCTION_DECODER1_PT(6) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(28) + ) , STD_ULOGIC_VECTOR'("011111")); +MQQ187:INSTRUCTION_DECODER1_PT(7) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(5) ) , STD_ULOGIC_VECTOR'("111")); +MQQ188:INSTRUCTION_DECODER1_PT(8) <= + Eq(( IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(27) + ) , STD_ULOGIC_VECTOR'("00")); +MQQ189:INSTRUCTION_DECODER1_PT(9) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("01110")); +MQQ190:INSTRUCTION_DECODER1_PT(10) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) ) , STD_ULOGIC_VECTOR'("01110")); +MQQ191:INSTRUCTION_DECODER1_PT(11) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(5) ) , STD_ULOGIC_VECTOR'("110")); +MQQ192:INSTRUCTION_DECODER1_PT(12) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(5) ) , STD_ULOGIC_VECTOR'("010")); +MQQ193:INSTRUCTION_DECODER1_PT(13) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) ) , STD_ULOGIC_VECTOR'("010")); +MQQ194:INSTRUCTION_DECODER1_PT(14) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) + ) , STD_ULOGIC_VECTOR'("10")); +MQQ195:INSTRUCTION_DECODER1_PT(15) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(4) + ) , STD_ULOGIC_VECTOR'("10")); +MQQ196:TA_SEL <= + (INSTRUCTION_DECODER1_PT(6) OR INSTRUCTION_DECODER1_PT(7) + OR INSTRUCTION_DECODER1_PT(9) OR INSTRUCTION_DECODER1_PT(10) + OR INSTRUCTION_DECODER1_PT(11) OR INSTRUCTION_DECODER1_PT(13) + OR INSTRUCTION_DECODER1_PT(14) OR INSTRUCTION_DECODER1_PT(15) + ); +MQQ197:S1_SEL <= + (INSTRUCTION_DECODER1_PT(1) OR INSTRUCTION_DECODER1_PT(3) + OR INSTRUCTION_DECODER1_PT(5) OR INSTRUCTION_DECODER1_PT(9) + OR INSTRUCTION_DECODER1_PT(10) OR INSTRUCTION_DECODER1_PT(12) + OR INSTRUCTION_DECODER1_PT(13) OR INSTRUCTION_DECODER1_PT(14) + OR INSTRUCTION_DECODER1_PT(15)); +MQQ198:S2_SEL <= + (INSTRUCTION_DECODER1_PT(2) OR INSTRUCTION_DECODER1_PT(4) + OR INSTRUCTION_DECODER1_PT(5) OR INSTRUCTION_DECODER1_PT(8) + OR INSTRUCTION_DECODER1_PT(15)); +MQQ199:S3_SEL <= + (INSTRUCTION_DECODER1_PT(4) OR INSTRUCTION_DECODER1_PT(5) + ); + +MQQ200:INSTRUCTION_DECODER2_PT(1) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(3) & + IS1_INSTR_L2(4) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("00000100000000")); +MQQ201:INSTRUCTION_DECODER2_PT(2) <= + Eq(( CORE64 & IS1_INSTR_L2(0) & + IS1_INSTR_L2(1) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(3) & IS1_INSTR_L2(4) & + IS1_INSTR_L2(5) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(25) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("10111111011101001")); +MQQ202:INSTRUCTION_DECODER2_PT(3) <= + Eq(( CORE64 & IS1_INSTR_L2(0) & + IS1_INSTR_L2(1) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(3) & IS1_INSTR_L2(4) & + IS1_INSTR_L2(5) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(25) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("10111110011101001")); +MQQ203:INSTRUCTION_DECODER2_PT(4) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(3) & + IS1_INSTR_L2(4) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(25) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) & IS1_INSTR_L2(31) + ) , STD_ULOGIC_VECTOR'("0111110110111000")); +MQQ204:INSTRUCTION_DECODER2_PT(5) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(3) & + IS1_INSTR_L2(4) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(25) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) & IS1_INSTR_L2(31) + ) , STD_ULOGIC_VECTOR'("0111110001111000")); +MQQ205:INSTRUCTION_DECODER2_PT(6) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(3) & IS1_INSTR_L2(4) & + IS1_INSTR_L2(5) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(25) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("000110000000000")); +MQQ206:INSTRUCTION_DECODER2_PT(7) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(3) & + IS1_INSTR_L2(4) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) & + IS1_INSTR_L2(31) ) , STD_ULOGIC_VECTOR'("011111010111000")); +MQQ207:INSTRUCTION_DECODER2_PT(8) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(3) & + IS1_INSTR_L2(4) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(11) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(25) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) + ) , STD_ULOGIC_VECTOR'("0111111000001001")); +MQQ208:INSTRUCTION_DECODER2_PT(9) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(3) & + IS1_INSTR_L2(4) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) & + IS1_INSTR_L2(31) ) , STD_ULOGIC_VECTOR'("011111000111000")); +MQQ209:INSTRUCTION_DECODER2_PT(10) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(4) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("00110010010110")); +MQQ210:INSTRUCTION_DECODER2_PT(11) <= + Eq(( CORE64 & IS1_INSTR_L2(0) & + IS1_INSTR_L2(1) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(3) & IS1_INSTR_L2(4) & + IS1_INSTR_L2(5) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(31) + ) , STD_ULOGIC_VECTOR'("1011111001010111")); +MQQ211:INSTRUCTION_DECODER2_PT(12) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(3) & IS1_INSTR_L2(4) & + IS1_INSTR_L2(5) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("00011011000001")); +MQQ212:INSTRUCTION_DECODER2_PT(13) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(3) & IS1_INSTR_L2(4) & + IS1_INSTR_L2(5) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("00011010100001")); +MQQ213:INSTRUCTION_DECODER2_PT(14) <= + Eq(( CORE64 & IS1_INSTR_L2(0) & + IS1_INSTR_L2(1) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(3) & IS1_INSTR_L2(4) & + IS1_INSTR_L2(5) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(25) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("101111100001001")); +MQQ214:INSTRUCTION_DECODER2_PT(15) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(3) & + IS1_INSTR_L2(4) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(31) + ) , STD_ULOGIC_VECTOR'("0111110010010111")); +MQQ215:INSTRUCTION_DECODER2_PT(16) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(3) & IS1_INSTR_L2(4) & + IS1_INSTR_L2(5) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("00011001100001")); +MQQ216:INSTRUCTION_DECODER2_PT(17) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(3) & IS1_INSTR_L2(4) & + IS1_INSTR_L2(5) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("00011000100001")); +MQQ217:INSTRUCTION_DECODER2_PT(18) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(3) & IS1_INSTR_L2(4) & + IS1_INSTR_L2(5) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("00011001000001")); +MQQ218:INSTRUCTION_DECODER2_PT(19) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(3) & IS1_INSTR_L2(4) & + IS1_INSTR_L2(8) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("01011000010000")); +MQQ219:INSTRUCTION_DECODER2_PT(20) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(3) & IS1_INSTR_L2(4) & + IS1_INSTR_L2(5) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("00011010000001")); +MQQ220:INSTRUCTION_DECODER2_PT(21) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(3) & IS1_INSTR_L2(4) & + IS1_INSTR_L2(5) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("00011000100110")); +MQQ221:INSTRUCTION_DECODER2_PT(22) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) & + IS1_INSTR_L2(31) ) , STD_ULOGIC_VECTOR'("011100110101001")); +MQQ222:INSTRUCTION_DECODER2_PT(23) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(3) & IS1_INSTR_L2(4) & + IS1_INSTR_L2(5) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(25) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) + ) , STD_ULOGIC_VECTOR'("00011000011001")); +MQQ223:INSTRUCTION_DECODER2_PT(24) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("011111100110")); +MQQ224:INSTRUCTION_DECODER2_PT(25) <= + Eq(( CORE64 & IS1_INSTR_L2(0) & + IS1_INSTR_L2(1) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(5) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("10111001111100")); +MQQ225:INSTRUCTION_DECODER2_PT(26) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(3) & IS1_INSTR_L2(4) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("0101000000000")); +MQQ226:INSTRUCTION_DECODER2_PT(27) <= + Eq(( CORE64 & IS1_INSTR_L2(0) & + IS1_INSTR_L2(1) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(5) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(25) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) + ) , STD_ULOGIC_VECTOR'("10111110011101")); +MQQ227:INSTRUCTION_DECODER2_PT(28) <= + Eq(( CORE64 & IS1_INSTR_L2(0) & + IS1_INSTR_L2(1) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(5) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("10111011111010")); +MQQ228:INSTRUCTION_DECODER2_PT(29) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("01111100110011")); +MQQ229:INSTRUCTION_DECODER2_PT(30) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(15) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("01111010110011")); +MQQ230:INSTRUCTION_DECODER2_PT(31) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(20) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("01111010110011")); +MQQ231:INSTRUCTION_DECODER2_PT(32) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(19) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("01111010110011")); +MQQ232:INSTRUCTION_DECODER2_PT(33) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(18) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("01111010110011")); +MQQ233:INSTRUCTION_DECODER2_PT(34) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(17) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("01111010110011")); +MQQ234:INSTRUCTION_DECODER2_PT(35) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(16) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("01111010110011")); +MQQ235:INSTRUCTION_DECODER2_PT(36) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(14) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("01111010110011")); +MQQ236:INSTRUCTION_DECODER2_PT(37) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(13) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("01111010110011")); +MQQ237:INSTRUCTION_DECODER2_PT(38) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(12) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("01111010110011")); +MQQ238:INSTRUCTION_DECODER2_PT(39) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(11) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("01111010110011")); +MQQ239:INSTRUCTION_DECODER2_PT(40) <= + Eq(( CORE64 & IS1_INSTR_L2(0) & + IS1_INSTR_L2(1) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(5) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("10111000011011")); +MQQ240:INSTRUCTION_DECODER2_PT(41) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) ) , STD_ULOGIC_VECTOR'("0111000001001")); +MQQ241:INSTRUCTION_DECODER2_PT(42) <= + Eq(( CORE64 & IS1_INSTR_L2(0) & + IS1_INSTR_L2(1) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(25) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) + ) , STD_ULOGIC_VECTOR'("101110001010")); +MQQ242:INSTRUCTION_DECODER2_PT(43) <= + Eq(( CORE64 & IS1_INSTR_L2(0) & + IS1_INSTR_L2(1) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(5) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("1011111001100")); +MQQ243:INSTRUCTION_DECODER2_PT(44) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(25) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("0111011100110")); +MQQ244:INSTRUCTION_DECODER2_PT(45) <= + Eq(( CORE64 & IS1_INSTR_L2(0) & + IS1_INSTR_L2(1) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(5) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("1011111101010")); +MQQ245:INSTRUCTION_DECODER2_PT(46) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) ) , STD_ULOGIC_VECTOR'("0111010000111")); +MQQ246:INSTRUCTION_DECODER2_PT(47) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("0111110011000")); +MQQ247:INSTRUCTION_DECODER2_PT(48) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(25) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("0111011110110")); +MQQ248:INSTRUCTION_DECODER2_PT(49) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("011110010110")); +MQQ249:INSTRUCTION_DECODER2_PT(50) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("011111111111")); +MQQ250:INSTRUCTION_DECODER2_PT(51) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(25) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("011100111111")); +MQQ251:INSTRUCTION_DECODER2_PT(52) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("0111011100011")); +MQQ252:INSTRUCTION_DECODER2_PT(53) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(25) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("0111001111010")); +MQQ253:INSTRUCTION_DECODER2_PT(54) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("0111000000100")); +MQQ254:INSTRUCTION_DECODER2_PT(55) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("0111001000110")); +MQQ255:INSTRUCTION_DECODER2_PT(56) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(25) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("0111000111100")); +MQQ256:INSTRUCTION_DECODER2_PT(57) <= + Eq(( CORE64 & IS1_INSTR_L2(0) & + IS1_INSTR_L2(1) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(25) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("101100000100")); +MQQ257:INSTRUCTION_DECODER2_PT(58) <= + Eq(( CORE64 & IS1_INSTR_L2(0) & + IS1_INSTR_L2(1) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(4) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(30) & IS1_INSTR_L2(31) + ) , STD_ULOGIC_VECTOR'("11111001")); +MQQ258:INSTRUCTION_DECODER2_PT(59) <= + Eq(( CORE64 & IS1_INSTR_L2(0) & + IS1_INSTR_L2(1) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(5) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("1011100011010")); +MQQ259:INSTRUCTION_DECODER2_PT(60) <= + Eq(( CORE64 & IS1_INSTR_L2(0) & + IS1_INSTR_L2(1) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("101101011011")); +MQQ260:INSTRUCTION_DECODER2_PT(61) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("0111010111011")); +MQQ261:INSTRUCTION_DECODER2_PT(62) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) & IS1_INSTR_L2(31) + ) , STD_ULOGIC_VECTOR'("011111010101")); +MQQ262:INSTRUCTION_DECODER2_PT(63) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("0111000100011")); +MQQ263:INSTRUCTION_DECODER2_PT(64) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("0111001001000")); +MQQ264:INSTRUCTION_DECODER2_PT(65) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) + ) , STD_ULOGIC_VECTOR'("011100110111")); +MQQ265:INSTRUCTION_DECODER2_PT(66) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("011100101000")); +MQQ266:INSTRUCTION_DECODER2_PT(67) <= + Eq(( CORE64 & IS1_INSTR_L2(0) & + IS1_INSTR_L2(1) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(25) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("101100011011")); +MQQ267:INSTRUCTION_DECODER2_PT(68) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("011110010101")); +MQQ268:INSTRUCTION_DECODER2_PT(69) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(25) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("011100000000")); +MQQ269:INSTRUCTION_DECODER2_PT(70) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(25) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) + ) , STD_ULOGIC_VECTOR'("011100001011")); +MQQ270:INSTRUCTION_DECODER2_PT(71) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(25) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("011111101010")); +MQQ271:INSTRUCTION_DECODER2_PT(72) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("011111110110")); +MQQ272:INSTRUCTION_DECODER2_PT(73) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(25) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) + ) , STD_ULOGIC_VECTOR'("011100001011")); +MQQ273:INSTRUCTION_DECODER2_PT(74) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(25) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("0111001010011")); +MQQ274:INSTRUCTION_DECODER2_PT(75) <= + Eq(( CORE64 & IS1_INSTR_L2(0) & + IS1_INSTR_L2(1) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(5) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("10111110101")); +MQQ275:INSTRUCTION_DECODER2_PT(76) <= + Eq(( CORE64 & IS1_INSTR_L2(0) & + IS1_INSTR_L2(1) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(5) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("101110000111")); +MQQ276:INSTRUCTION_DECODER2_PT(77) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(25) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("011100001000")); +MQQ277:INSTRUCTION_DECODER2_PT(78) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("011101111100")); +MQQ278:INSTRUCTION_DECODER2_PT(79) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("01111110111")); +MQQ279:INSTRUCTION_DECODER2_PT(80) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("011111101010")); +MQQ280:INSTRUCTION_DECODER2_PT(81) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("011100001010")); +MQQ281:INSTRUCTION_DECODER2_PT(82) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("011101000011")); +MQQ282:INSTRUCTION_DECODER2_PT(83) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("01110001111")); +MQQ283:INSTRUCTION_DECODER2_PT(84) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(3) & + IS1_INSTR_L2(4) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("01111101111")); +MQQ284:INSTRUCTION_DECODER2_PT(85) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) + ) , STD_ULOGIC_VECTOR'("011100001111")); +MQQ285:INSTRUCTION_DECODER2_PT(86) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("011100000000")); +MQQ286:INSTRUCTION_DECODER2_PT(87) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("011100011100")); +MQQ287:INSTRUCTION_DECODER2_PT(88) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("011100010110")); +MQQ288:INSTRUCTION_DECODER2_PT(89) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("01110110100")); +MQQ289:INSTRUCTION_DECODER2_PT(90) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(25) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("011100001010")); +MQQ290:INSTRUCTION_DECODER2_PT(91) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("01110100100")); +MQQ291:INSTRUCTION_DECODER2_PT(92) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("01110000111")); +MQQ292:INSTRUCTION_DECODER2_PT(93) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("01111100110")); +MQQ293:INSTRUCTION_DECODER2_PT(94) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("011101010111")); +MQQ294:INSTRUCTION_DECODER2_PT(95) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("01111001010")); +MQQ295:INSTRUCTION_DECODER2_PT(96) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("01111010010")); +MQQ296:INSTRUCTION_DECODER2_PT(97) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("0111110111")); +MQQ297:INSTRUCTION_DECODER2_PT(98) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("01110011111")); +MQQ298:INSTRUCTION_DECODER2_PT(99) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("01110000011")); +MQQ299:INSTRUCTION_DECODER2_PT(100) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("01110001111")); +MQQ300:INSTRUCTION_DECODER2_PT(101) <= + Eq(( CORE64 & IS1_INSTR_L2(2) & + IS1_INSTR_L2(3) & IS1_INSTR_L2(4) & + IS1_INSTR_L2(5) & IS1_INSTR_L2(31) + ) , STD_ULOGIC_VECTOR'("110100")); +MQQ301:INSTRUCTION_DECODER2_PT(102) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("01110010111")); +MQQ302:INSTRUCTION_DECODER2_PT(103) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("01110001011")); +MQQ303:INSTRUCTION_DECODER2_PT(104) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(3) & IS1_INSTR_L2(5) + ) , STD_ULOGIC_VECTOR'("1010")); +MQQ304:INSTRUCTION_DECODER2_PT(105) <= + Eq(( CORE64 & IS1_INSTR_L2(1) & + IS1_INSTR_L2(3) & IS1_INSTR_L2(4) + ) , STD_ULOGIC_VECTOR'("1001")); +MQQ305:INSTRUCTION_DECODER2_PT(106) <= + Eq(( CORE64 & IS1_INSTR_L2(0) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(4) & + IS1_INSTR_L2(5) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("111100")); +MQQ306:INSTRUCTION_DECODER2_PT(107) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(3) & + IS1_INSTR_L2(4) & IS1_INSTR_L2(5) + ) , STD_ULOGIC_VECTOR'("000111")); +MQQ307:INSTRUCTION_DECODER2_PT(108) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(3) ) , STD_ULOGIC_VECTOR'("101")); +MQQ308:INSTRUCTION_DECODER2_PT(109) <= + Eq(( CORE64 & IS1_INSTR_L2(0) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) + ) , STD_ULOGIC_VECTOR'("101000")); +MQQ309:INSTRUCTION_DECODER2_PT(110) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(3) & + IS1_INSTR_L2(4) ) , STD_ULOGIC_VECTOR'("01100")); +MQQ310:INSTRUCTION_DECODER2_PT(111) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(3) & + IS1_INSTR_L2(5) ) , STD_ULOGIC_VECTOR'("01100")); +MQQ311:INSTRUCTION_DECODER2_PT(112) <= + Eq(( IS1_INSTR_L2(1) & IS1_INSTR_L2(3) & + IS1_INSTR_L2(4) & IS1_INSTR_L2(5) + ) , STD_ULOGIC_VECTOR'("0011")); +MQQ312:INSTRUCTION_DECODER2_PT(113) <= + Eq(( CORE64 & IS1_INSTR_L2(0) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(27) ) , STD_ULOGIC_VECTOR'("10100")); +MQQ313:INSTRUCTION_DECODER2_PT(114) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(3) & IS1_INSTR_L2(5) + ) , STD_ULOGIC_VECTOR'("0100")); +MQQ314:INSTRUCTION_DECODER2_PT(115) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(3) & + IS1_INSTR_L2(5) ) , STD_ULOGIC_VECTOR'("01011")); +MQQ315:INSTRUCTION_DECODER2_PT(116) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) + ) , STD_ULOGIC_VECTOR'("10")); +MQQ316:INSTRUCTION_DECODER2_PT(117) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) + ) , STD_ULOGIC_VECTOR'("0010")); +MQQ317:INSTRUCTION_DECODER2_PT(118) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(4) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("0101")); +MQQ318:INSTRUCTION_DECODER2_PT(119) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(3) & IS1_INSTR_L2(4) + ) , STD_ULOGIC_VECTOR'("0110")); +MQQ319:INSTRUCTION_DECODER2_PT(120) <= + Eq(( IS1_INSTR_L2(1) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(3) ) , STD_ULOGIC_VECTOR'("011")); +MQQ320:INSTRUCTION_DECODER2_PT(121) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(3) + ) , STD_ULOGIC_VECTOR'("0110")); +MQQ321:ISFXUISSUE <= + (INSTRUCTION_DECODER2_PT(1) OR INSTRUCTION_DECODER2_PT(2) + OR INSTRUCTION_DECODER2_PT(3) OR INSTRUCTION_DECODER2_PT(10) + OR INSTRUCTION_DECODER2_PT(11) OR INSTRUCTION_DECODER2_PT(12) + OR INSTRUCTION_DECODER2_PT(13) OR INSTRUCTION_DECODER2_PT(14) + OR INSTRUCTION_DECODER2_PT(15) OR INSTRUCTION_DECODER2_PT(16) + OR INSTRUCTION_DECODER2_PT(17) OR INSTRUCTION_DECODER2_PT(18) + OR INSTRUCTION_DECODER2_PT(19) OR INSTRUCTION_DECODER2_PT(20) + OR INSTRUCTION_DECODER2_PT(21) OR INSTRUCTION_DECODER2_PT(22) + OR INSTRUCTION_DECODER2_PT(23) OR INSTRUCTION_DECODER2_PT(24) + OR INSTRUCTION_DECODER2_PT(25) OR INSTRUCTION_DECODER2_PT(26) + OR INSTRUCTION_DECODER2_PT(27) OR INSTRUCTION_DECODER2_PT(28) + OR INSTRUCTION_DECODER2_PT(29) OR INSTRUCTION_DECODER2_PT(30) + OR INSTRUCTION_DECODER2_PT(31) OR INSTRUCTION_DECODER2_PT(32) + OR INSTRUCTION_DECODER2_PT(33) OR INSTRUCTION_DECODER2_PT(34) + OR INSTRUCTION_DECODER2_PT(35) OR INSTRUCTION_DECODER2_PT(36) + OR INSTRUCTION_DECODER2_PT(37) OR INSTRUCTION_DECODER2_PT(38) + OR INSTRUCTION_DECODER2_PT(39) OR INSTRUCTION_DECODER2_PT(40) + OR INSTRUCTION_DECODER2_PT(42) OR INSTRUCTION_DECODER2_PT(43) + OR INSTRUCTION_DECODER2_PT(44) OR INSTRUCTION_DECODER2_PT(45) + OR INSTRUCTION_DECODER2_PT(46) OR INSTRUCTION_DECODER2_PT(47) + OR INSTRUCTION_DECODER2_PT(48) OR INSTRUCTION_DECODER2_PT(49) + OR INSTRUCTION_DECODER2_PT(50) OR INSTRUCTION_DECODER2_PT(52) + OR INSTRUCTION_DECODER2_PT(53) OR INSTRUCTION_DECODER2_PT(54) + OR INSTRUCTION_DECODER2_PT(55) OR INSTRUCTION_DECODER2_PT(56) + OR INSTRUCTION_DECODER2_PT(57) OR INSTRUCTION_DECODER2_PT(59) + OR INSTRUCTION_DECODER2_PT(60) OR INSTRUCTION_DECODER2_PT(61) + OR INSTRUCTION_DECODER2_PT(62) OR INSTRUCTION_DECODER2_PT(63) + OR INSTRUCTION_DECODER2_PT(64) OR INSTRUCTION_DECODER2_PT(65) + OR INSTRUCTION_DECODER2_PT(66) OR INSTRUCTION_DECODER2_PT(67) + OR INSTRUCTION_DECODER2_PT(68) OR INSTRUCTION_DECODER2_PT(69) + OR INSTRUCTION_DECODER2_PT(70) OR INSTRUCTION_DECODER2_PT(71) + OR INSTRUCTION_DECODER2_PT(72) OR INSTRUCTION_DECODER2_PT(73) + OR INSTRUCTION_DECODER2_PT(74) OR INSTRUCTION_DECODER2_PT(75) + OR INSTRUCTION_DECODER2_PT(76) OR INSTRUCTION_DECODER2_PT(77) + OR INSTRUCTION_DECODER2_PT(78) OR INSTRUCTION_DECODER2_PT(79) + OR INSTRUCTION_DECODER2_PT(80) OR INSTRUCTION_DECODER2_PT(81) + OR INSTRUCTION_DECODER2_PT(82) OR INSTRUCTION_DECODER2_PT(83) + OR INSTRUCTION_DECODER2_PT(84) OR INSTRUCTION_DECODER2_PT(85) + OR INSTRUCTION_DECODER2_PT(86) OR INSTRUCTION_DECODER2_PT(87) + OR INSTRUCTION_DECODER2_PT(88) OR INSTRUCTION_DECODER2_PT(89) + OR INSTRUCTION_DECODER2_PT(90) OR INSTRUCTION_DECODER2_PT(91) + OR INSTRUCTION_DECODER2_PT(92) OR INSTRUCTION_DECODER2_PT(93) + OR INSTRUCTION_DECODER2_PT(94) OR INSTRUCTION_DECODER2_PT(95) + OR INSTRUCTION_DECODER2_PT(96) OR INSTRUCTION_DECODER2_PT(97) + OR INSTRUCTION_DECODER2_PT(98) OR INSTRUCTION_DECODER2_PT(99) + OR INSTRUCTION_DECODER2_PT(100) OR INSTRUCTION_DECODER2_PT(101) + OR INSTRUCTION_DECODER2_PT(102) OR INSTRUCTION_DECODER2_PT(103) + OR INSTRUCTION_DECODER2_PT(105) OR INSTRUCTION_DECODER2_PT(106) + OR INSTRUCTION_DECODER2_PT(107) OR INSTRUCTION_DECODER2_PT(109) + OR INSTRUCTION_DECODER2_PT(112) OR INSTRUCTION_DECODER2_PT(113) + OR INSTRUCTION_DECODER2_PT(114) OR INSTRUCTION_DECODER2_PT(115) + OR INSTRUCTION_DECODER2_PT(116) OR INSTRUCTION_DECODER2_PT(117) + OR INSTRUCTION_DECODER2_PT(118) OR INSTRUCTION_DECODER2_PT(119) + OR INSTRUCTION_DECODER2_PT(120) OR INSTRUCTION_DECODER2_PT(121) + ); +MQQ322:HOLE_DELAY(1) <= + (INSTRUCTION_DECODER2_PT(107)); +MQQ323:HOLE_DELAY(2) <= + (INSTRUCTION_DECODER2_PT(3)); +MQQ324:HOLE_DELAY(3) <= + (INSTRUCTION_DECODER2_PT(2) OR INSTRUCTION_DECODER2_PT(14) + ); +MQQ325:COMPL_EX(1) <= + (INSTRUCTION_DECODER2_PT(4) OR INSTRUCTION_DECODER2_PT(5) + OR INSTRUCTION_DECODER2_PT(6) OR INSTRUCTION_DECODER2_PT(7) + OR INSTRUCTION_DECODER2_PT(8) OR INSTRUCTION_DECODER2_PT(9) + OR INSTRUCTION_DECODER2_PT(11) OR INSTRUCTION_DECODER2_PT(12) + OR INSTRUCTION_DECODER2_PT(13) OR INSTRUCTION_DECODER2_PT(15) + OR INSTRUCTION_DECODER2_PT(16) OR INSTRUCTION_DECODER2_PT(17) + OR INSTRUCTION_DECODER2_PT(18) OR INSTRUCTION_DECODER2_PT(20) + OR INSTRUCTION_DECODER2_PT(21) OR INSTRUCTION_DECODER2_PT(23) + OR INSTRUCTION_DECODER2_PT(84) OR INSTRUCTION_DECODER2_PT(104) + OR INSTRUCTION_DECODER2_PT(110) OR INSTRUCTION_DECODER2_PT(111) + ); +MQQ326:COMPL_EX(2) <= + (INSTRUCTION_DECODER2_PT(27) OR INSTRUCTION_DECODER2_PT(40) + OR INSTRUCTION_DECODER2_PT(43) OR INSTRUCTION_DECODER2_PT(45) + OR INSTRUCTION_DECODER2_PT(47) OR INSTRUCTION_DECODER2_PT(51) + OR INSTRUCTION_DECODER2_PT(56) OR INSTRUCTION_DECODER2_PT(58) + OR INSTRUCTION_DECODER2_PT(66) OR INSTRUCTION_DECODER2_PT(67) + OR INSTRUCTION_DECODER2_PT(77) OR INSTRUCTION_DECODER2_PT(78) + OR INSTRUCTION_DECODER2_PT(80) OR INSTRUCTION_DECODER2_PT(81) + OR INSTRUCTION_DECODER2_PT(86) OR INSTRUCTION_DECODER2_PT(87) + OR INSTRUCTION_DECODER2_PT(89) OR INSTRUCTION_DECODER2_PT(91) + OR INSTRUCTION_DECODER2_PT(94) OR INSTRUCTION_DECODER2_PT(108) + OR INSTRUCTION_DECODER2_PT(109) OR INSTRUCTION_DECODER2_PT(112) + OR INSTRUCTION_DECODER2_PT(113) OR INSTRUCTION_DECODER2_PT(115) + OR INSTRUCTION_DECODER2_PT(117) OR INSTRUCTION_DECODER2_PT(119) + OR INSTRUCTION_DECODER2_PT(120) OR INSTRUCTION_DECODER2_PT(121) + ); +MQQ327:COMPL_EX(3) <= + ('0'); +MQQ328:COMPL_EX(4) <= + (INSTRUCTION_DECODER2_PT(31) OR INSTRUCTION_DECODER2_PT(32) + OR INSTRUCTION_DECODER2_PT(33) OR INSTRUCTION_DECODER2_PT(34) + OR INSTRUCTION_DECODER2_PT(35) OR INSTRUCTION_DECODER2_PT(36) + OR INSTRUCTION_DECODER2_PT(37) OR INSTRUCTION_DECODER2_PT(38) + OR INSTRUCTION_DECODER2_PT(39) OR INSTRUCTION_DECODER2_PT(61) + OR INSTRUCTION_DECODER2_PT(74)); +MQQ329:COMPL_EX(5) <= + (INSTRUCTION_DECODER2_PT(30) OR INSTRUCTION_DECODER2_PT(41) + OR INSTRUCTION_DECODER2_PT(63) OR INSTRUCTION_DECODER2_PT(79) + OR INSTRUCTION_DECODER2_PT(92)); + +MQQ330:MICROCODE_PT(1) <= + Eq(( CORE64 & IS1_INSTR_L2(0) & + IS1_INSTR_L2(1) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(3) & IS1_INSTR_L2(4) & + IS1_INSTR_L2(5) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("101111100011010")); +MQQ331:MICROCODE_PT(2) <= + Eq(( CORE64 & IS1_INSTR_L2(0) & + IS1_INSTR_L2(1) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(3) & IS1_INSTR_L2(4) & + IS1_INSTR_L2(5) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("1011111011111010")); +MQQ332:MICROCODE_PT(3) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(3) & + IS1_INSTR_L2(4) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("0111111000000000")); +MQQ333:MICROCODE_PT(4) <= + Eq(( CORE64 & IS1_INSTR_L2(0) & + IS1_INSTR_L2(1) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(3) & IS1_INSTR_L2(4) & + IS1_INSTR_L2(5) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(25) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("1011111010111011")); +MQQ334:MICROCODE_PT(5) <= + Eq(( CORE64 & IS1_INSTR_L2(0) & + IS1_INSTR_L2(1) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(3) & IS1_INSTR_L2(4) & + IS1_INSTR_L2(5) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(25) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("10111110011111100")); +MQQ335:MICROCODE_PT(6) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(3) & + IS1_INSTR_L2(4) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("01111110010101")); +MQQ336:MICROCODE_PT(7) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(3) & + IS1_INSTR_L2(4) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(25) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("011111000011010")); +MQQ337:MICROCODE_PT(8) <= + Eq(( CORE64 & IS1_INSTR_L2(0) & + IS1_INSTR_L2(1) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(3) & IS1_INSTR_L2(4) & + IS1_INSTR_L2(5) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(25) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("1011111000011011")); +MQQ338:MICROCODE_PT(9) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(3) & + IS1_INSTR_L2(4) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(25) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("011111001111010")); +MQQ339:MICROCODE_PT(10) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(3) & + IS1_INSTR_L2(4) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("01111100110111")); +MQQ340:MICROCODE_PT(11) <= + Eq(( CORE64 & IS1_INSTR_L2(0) & + IS1_INSTR_L2(1) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(3) & IS1_INSTR_L2(4) & + IS1_INSTR_L2(5) & IS1_INSTR_L2(30) & + IS1_INSTR_L2(31) ) , STD_ULOGIC_VECTOR'("111101001")); +MQQ341:MICROCODE_PT(12) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(3) & IS1_INSTR_L2(5) + ) , STD_ULOGIC_VECTOR'("1001")); +MQQ342:MICROCODE_PT(13) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(3) & + IS1_INSTR_L2(4) ) , STD_ULOGIC_VECTOR'("10111")); +MQQ343:TO_UC <= + (MICROCODE_PT(1) OR MICROCODE_PT(2) + OR MICROCODE_PT(3) OR MICROCODE_PT(4) + OR MICROCODE_PT(5) OR MICROCODE_PT(6) + OR MICROCODE_PT(7) OR MICROCODE_PT(8) + OR MICROCODE_PT(9) OR MICROCODE_PT(10) + OR MICROCODE_PT(11) OR MICROCODE_PT(12) + OR MICROCODE_PT(13)); + +is1_UpdatesLR_din <= UpdatesLR; +is1_UpdatesCR_din <= UpdatesCR; +is1_UpdatesCTR_din <= UpdatesCTR; +is1_UpdatesXER_din <= UpdatesXER; +is1_UpdatesMSR_din <= UpdatesMSR; +is1_UpdatesSPR_din <= UpdatesSPR; +is1_UsesLR_din <= UsesLR; +is1_UsesCR_din <= UsesCR; +is1_UsesCTR_din <= UsesCTR; +is1_UsesXER_din <= UsesXER; +is1_UsesMSR_din <= UsesMSR; +is1_UsesSPR_din <= UsesSPR; +is1_vld_din <= iu_au_ib1_instr_vld; +is1_vld_type_din(0) <= au_iu_is0_to_ucode; +is1_vld_type_din(1) <= au_ib1_ld_or_st; +is1_vld_type_din(2) <= not au_iu_i_dec; +is1_ifar_din <= iu_au_ib1_ifar; +is1_instr_din(0 TO 31) <= iu_au_ib1_instr(0 to 31); +is1_axu_instr_din(6 TO 31) <= au_iu_ib1_ldst_indexed & + au_iu_ib1_ldst_tag(0 to 8) & + au_iu_ib1_ldst_dimm(0 to 15) ; +with ta_sel select is1_ta_d0 <= + iu_au_ib1_instr_ucode_ext(0) & iu_au_ib1_instr(6 to 10) when '0', + iu_au_ib1_instr_ucode_ext(0) & iu_au_ib1_instr(11 to 15) when others; +is1_ta_vld_din <= ta_vld; +is1_ta_din <= au_iu_ib1_ldst_ra(1 to 6) when (au_iu_ib1_ldst_update = '1' or au_iu_ib1_mftgpr = '1') else is1_ta_d0; +with s1_sel select is1_s1_d0 <= + iu_au_ib1_instr_ucode_ext(1) & iu_au_ib1_instr(11 to 15) when '0', + iu_au_ib1_instr_ucode_ext(1) & iu_au_ib1_instr(6 to 10) when others; +is1_s1_vld_din <= s1_vld; +is1_s1_din <= au_iu_ib1_ldst_ra(1 to 6) when au_iu_ib1_ldst = '1' else is1_s1_d0; +with s2_sel select is1_s2_d0 <= + iu_au_ib1_instr_ucode_ext(2) & iu_au_ib1_instr(16 to 20) when '0', + iu_au_ib1_instr_ucode_ext(2) & iu_au_ib1_instr(11 to 15) when others; +is1_s2_vld_din <= s2_vld; +is1_s2_din <= au_iu_ib1_ldst_rb(1 to 6) when au_iu_ib1_ldst_rb_v = '1' else is1_s2_d0; +with s3_sel select is1_s3_d0 <= + iu_au_ib1_instr_ucode_ext(3) & iu_au_ib1_instr(6 to 10) when '0', + iu_au_ib1_instr_ucode_ext(3) & iu_au_ib1_instr(16 to 20) when others; +is1_s3_vld_din <= s3_vld; +is1_s3_din <= au_iu_ib1_ldst_rb(1 to 6) when au_iu_ib1_mffgpr = '1' else is1_s3_d0; +is1_pred_update_din <= iu_au_ib1_instr_pred_vld; +is1_pred_taken_cnt_din <= iu_au_ib1_instr_pred_taken_cnt; +is1_gshare_din <= iu_au_ib1_instr_gshare; +is1_ld_vld_din <= ld_vld; +is1_to_ucode_din <= au_iu_is0_to_ucode; +is1_is_ucode_din <= iu_au_ib1_instr_is_ucode; +is1_axu_ld_or_st_din <= au_ib1_ld_or_st; +is1_axu_store_din <= au_ib1_store; +is1_axu_ldst_size_din <= au_iu_ib1_ldst_size; +is1_axu_ldst_update_din <= au_iu_ib1_ldst_update; +is1_axu_ldst_extpid_din <= au_iu_ib1_ldst_extpid; +is1_axu_ldst_forcealign_din <= au_iu_ib1_ldst_forcealign; +is1_axu_ldst_forceexcept_din <= au_iu_ib1_ldst_forceexcept; +is1_axu_mftgpr_din <= au_iu_ib1_mftgpr; +is1_axu_mffgpr_din <= au_iu_ib1_mffgpr; +is1_axu_movedp_din <= au_iu_ib1_movedp; +is1_axu_instr_type_din <= au_iu_ib1_instr_type; +is1_error_din(0 TO 2) <= iu_au_ib1_instr_error(0 to 2); +is1_force_ram_din <= iu_au_ib1_instr_force_ram; +is1_2ucode_din <= iu_au_ib1_instr_2ucode; +is1_2ucode_type_din <= iu_au_ib1_instr_2ucode_type; +is1_axu_ldst_ra_v_din <= au_iu_ib1_ldst_ra_v; +is1_axu_ldst_rb_v_din <= au_iu_ib1_ldst_rb_v; +is1_instr_proc : process ( + +xu_iu_ib1_flush, +iu_au_is1_stall, +is1_vld_din, +is1_vld_type_din, +is1_instr_din, +is1_axu_instr_din, +is1_ta_vld_din, +is1_ta_din, +is1_s1_vld_din, +is1_s1_din, +is1_s2_vld_din, +is1_s2_din, +is1_s3_vld_din, +is1_s3_din, +is1_pred_update_din, +is1_pred_taken_cnt_din, +is1_gshare_din, + +is1_UpdatesLR_din, +is1_UpdatesCR_din, +is1_UpdatesCTR_din, +is1_UpdatesXER_din, +is1_UpdatesMSR_din, +is1_UpdatesSPR_din, +is1_UsesLR_din, +is1_UsesCR_din, +is1_UsesCTR_din, +is1_UsesXER_din, +is1_UsesMSR_din, +is1_UsesSPR_din, + +is1_ld_vld_din, +is1_to_ucode_din, +is1_is_ucode_din, + +is1_ifar_din, +is1_error_din, +is1_axu_ldst_ra_v_din, +is1_axu_ldst_rb_v_din, +is1_axu_ld_or_st_din, +is1_axu_store_din, +is1_axu_ldst_size_din, +is1_axu_ldst_update_din, +is1_axu_ldst_extpid_din, +is1_axu_ldst_forcealign_din, +is1_axu_ldst_forceexcept_din, +is1_axu_mftgpr_din, +is1_axu_mffgpr_din, +is1_axu_movedp_din, +is1_axu_instr_type_din, + +is1_force_ram_din, +is1_2ucode_din, +is1_2ucode_type_din, +is1_vld_L2, +is1_vld_type_L2, +is1_instr_L2, +is1_axu_instr_L2, +is1_ta_vld_L2, +is1_ta_L2, +is1_s1_vld_L2, +is1_s1_L2, +is1_s2_vld_L2, +is1_s2_L2, +is1_s3_vld_L2, +is1_s3_L2, +is1_pred_update_L2, +is1_pred_taken_cnt_L2, +is1_gshare_L2, + +is1_UpdatesLR_L2, +is1_UpdatesCR_L2, +is1_UpdatesCTR_L2, +is1_UpdatesXER_L2, +is1_UpdatesMSR_L2, +is1_UpdatesSPR_L2, +is1_UsesLR_L2, +is1_UsesCR_L2, +is1_UsesCTR_L2, +is1_UsesXER_L2, +is1_UsesMSR_L2, +is1_UsesSPR_L2, + +is1_ld_vld_L2, +is1_to_ucode_L2, +is1_is_ucode_L2, + +is1_ifar_L2, +is1_error_L2, +is1_axu_ldst_ra_v_L2, +is1_axu_ldst_rb_v_L2, +is1_axu_ld_or_st_L2, +is1_axu_store_L2, +is1_axu_ldst_size_L2, +is1_axu_ldst_update_L2, +is1_axu_ldst_extpid_L2, +is1_axu_ldst_forcealign_L2, +is1_axu_ldst_forceexcept_L2, +is1_axu_mftgpr_L2, +is1_axu_mffgpr_L2, +is1_axu_movedp_L2, +is1_axu_instr_type_L2, + +is1_force_ram_L2, +is1_2ucode_L2, +is1_2ucode_type_L2 +) + +begin + +is1_vld_d <= is1_vld_din; +is1_vld_type_d <= is1_vld_type_din; +is1_instr_d <= is1_instr_din; +is1_axu_instr_d <= is1_axu_instr_din; +is1_ta_vld_d <= is1_ta_vld_din; +is1_ta_d <= is1_ta_din; +is1_s1_vld_d <= is1_s1_vld_din; +is1_s1_d <= is1_s1_din; +is1_s2_vld_d <= is1_s2_vld_din; +is1_s2_d <= is1_s2_din; +is1_s3_vld_d <= is1_s3_vld_din; +is1_s3_d <= is1_s3_din; +is1_pred_update_d <= is1_pred_update_din; +is1_pred_taken_cnt_d <= is1_pred_taken_cnt_din; +is1_gshare_d <= is1_gshare_din; +is1_UpdatesLR_d <= is1_UpdatesLR_din; +is1_UpdatesCR_d <= is1_UpdatesCR_din; +is1_UpdatesCTR_d <= is1_UpdatesCTR_din; +is1_UpdatesXER_d <= is1_UpdatesXER_din; +is1_UpdatesMSR_d <= is1_UpdatesMSR_din; +is1_UpdatesSPR_d <= is1_UpdatesSPR_din; +is1_UsesLR_d <= is1_UsesLR_din; +is1_UsesCR_d <= is1_UsesCR_din; +is1_UsesCTR_d <= is1_UsesCTR_din; +is1_UsesXER_d <= is1_UsesXER_din; +is1_UsesMSR_d <= is1_UsesMSR_din; +is1_UsesSPR_d <= is1_UsesSPR_din; +is1_ld_vld_d <= is1_ld_vld_din; +is1_to_ucode_d <= is1_to_ucode_din; +is1_is_ucode_d <= is1_is_ucode_din; +is1_ifar_d <= is1_ifar_din; +is1_error_d <= is1_error_din; +is1_axu_ldst_ra_v_d <= is1_axu_ldst_ra_v_din; +is1_axu_ldst_rb_v_d <= is1_axu_ldst_rb_v_din; +is1_axu_ld_or_st_d <= is1_axu_ld_or_st_din; +is1_axu_store_d <= is1_axu_store_din; +is1_axu_ldst_size_d <= is1_axu_ldst_size_din; +is1_axu_ldst_update_d <= is1_axu_ldst_update_din; +is1_axu_ldst_extpid_d <= is1_axu_ldst_extpid_din; +is1_axu_ldst_forcealign_d <= is1_axu_ldst_forcealign_din; +is1_axu_ldst_forceexcept_d <= is1_axu_ldst_forceexcept_din; +is1_axu_mftgpr_d <= is1_axu_mftgpr_din; +is1_axu_mffgpr_d <= is1_axu_mffgpr_din; +is1_axu_movedp_d <= is1_axu_movedp_din; +is1_axu_instr_type_d <= is1_axu_instr_type_din; +is1_force_ram_d <= is1_force_ram_din; +is1_2ucode_d <= is1_2ucode_din; +is1_2ucode_type_d <= is1_2ucode_type_din; +if (iu_au_is1_stall = '1') then +is1_vld_d <= is1_vld_l2; +is1_vld_type_d <= is1_vld_type_l2; +is1_instr_d <= is1_instr_l2; +is1_axu_instr_d <= is1_axu_instr_l2; +is1_ta_vld_d <= is1_ta_vld_l2; +is1_ta_d <= is1_ta_l2; +is1_s1_vld_d <= is1_s1_vld_l2; +is1_s1_d <= is1_s1_l2; +is1_s2_vld_d <= is1_s2_vld_l2; +is1_s2_d <= is1_s2_l2; +is1_s3_vld_d <= is1_s3_vld_l2; +is1_s3_d <= is1_s3_l2; +is1_pred_update_d <= is1_pred_update_l2; +is1_pred_taken_cnt_d <= is1_pred_taken_cnt_l2; +is1_gshare_d <= is1_gshare_l2; +is1_UpdatesLR_d <= is1_UpdatesLR_l2; +is1_UpdatesCR_d <= is1_UpdatesCR_l2; +is1_UpdatesCTR_d <= is1_UpdatesCTR_l2; +is1_UpdatesXER_d <= is1_UpdatesXER_l2; +is1_UpdatesMSR_d <= is1_UpdatesMSR_l2; +is1_UpdatesSPR_d <= is1_UpdatesSPR_l2; +is1_UsesLR_d <= is1_UsesLR_l2; +is1_UsesCR_d <= is1_UsesCR_l2; +is1_UsesCTR_d <= is1_UsesCTR_l2; +is1_UsesXER_d <= is1_UsesXER_l2; +is1_UsesMSR_d <= is1_UsesMSR_l2; +is1_UsesSPR_d <= is1_UsesSPR_l2; +is1_ld_vld_d <= is1_ld_vld_l2; +is1_to_ucode_d <= is1_to_ucode_l2; +is1_is_ucode_d <= is1_is_ucode_l2; +is1_ifar_d <= is1_ifar_l2; +is1_error_d <= is1_error_l2; +is1_axu_ldst_ra_v_d <= is1_axu_ldst_ra_v_l2; +is1_axu_ldst_rb_v_d <= is1_axu_ldst_rb_v_l2; +is1_axu_ld_or_st_d <= is1_axu_ld_or_st_l2; +is1_axu_store_d <= is1_axu_store_l2; +is1_axu_ldst_size_d <= is1_axu_ldst_size_l2; +is1_axu_ldst_update_d <= is1_axu_ldst_update_l2; +is1_axu_ldst_extpid_d <= is1_axu_ldst_extpid_l2; +is1_axu_ldst_forcealign_d <= is1_axu_ldst_forcealign_l2; +is1_axu_ldst_forceexcept_d <= is1_axu_ldst_forceexcept_l2; +is1_axu_mftgpr_d <= is1_axu_mftgpr_l2; +is1_axu_mffgpr_d <= is1_axu_mffgpr_l2; +is1_axu_movedp_d <= is1_axu_movedp_l2; +is1_axu_instr_type_d <= is1_axu_instr_type_l2; +is1_force_ram_d <= is1_force_ram_l2; +is1_2ucode_d <= is1_2ucode_l2; +is1_2ucode_type_d <= is1_2ucode_type_l2; +end if; +if (xu_iu_ib1_flush = '1') then +is1_vld_d <= '0'; +end if; +end process is1_instr_proc; +act_valid <= tiup; +act_nonvalid <= not fdep_fdec_weak_stall; +is1_vld: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_valid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_vld_offset), + scout => sov(is1_vld_offset), + din => is1_vld_d, + dout => is1_vld_l2); +is1_vld_type: tri_rlmreg_p + generic map (width => is1_vld_type_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_vld_type_offset to is1_vld_type_offset + is1_vld_type_l2'length-1), + scout => sov(is1_vld_type_offset to is1_vld_type_offset + is1_vld_type_l2'length-1), + din => is1_vld_type_d, + dout => is1_vld_type_l2); +is1_instr: tri_rlmreg_p + generic map (width => is1_instr_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_instr_offset to is1_instr_offset + is1_instr_l2'length-1), + scout => sov(is1_instr_offset to is1_instr_offset + is1_instr_l2'length-1), + din => is1_instr_d, + dout => is1_instr_l2); +is1_axu_instr: tri_rlmreg_p + generic map (width => is1_axu_instr_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_axu_instr_offset to is1_axu_instr_offset + is1_axu_instr_l2'length-1), + scout => sov(is1_axu_instr_offset to is1_axu_instr_offset + is1_axu_instr_l2'length-1), + din => is1_axu_instr_d, + dout => is1_axu_instr_l2); +is1_ta_vld: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_ta_vld_offset), + scout => sov(is1_ta_vld_offset), + din => is1_ta_vld_d, + dout => is1_ta_vld_l2); +is1_ta: tri_rlmreg_p + generic map (width => is1_ta_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_ta_offset to is1_ta_offset + is1_ta_l2'length-1), + scout => sov(is1_ta_offset to is1_ta_offset + is1_ta_l2'length-1), + din => is1_ta_d, + dout => is1_ta_l2); +is1_s1_vld: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_s1_vld_offset), + scout => sov(is1_s1_vld_offset), + din => is1_s1_vld_d, + dout => is1_s1_vld_l2); +is1_s1: tri_rlmreg_p + generic map (width => is1_s1_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_s1_offset to is1_s1_offset + is1_s1_l2'length-1), + scout => sov(is1_s1_offset to is1_s1_offset + is1_s1_l2'length-1), + din => is1_s1_d, + dout => is1_s1_l2); +is1_s2_vld: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_s2_vld_offset), + scout => sov(is1_s2_vld_offset), + din => is1_s2_vld_d, + dout => is1_s2_vld_l2); +is1_s2: tri_rlmreg_p + generic map (width => is1_s2_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_s2_offset to is1_s2_offset + is1_s2_l2'length-1), + scout => sov(is1_s2_offset to is1_s2_offset + is1_s2_l2'length-1), + din => is1_s2_d, + dout => is1_s2_l2); +is1_s3_vld: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_s3_vld_offset), + scout => sov(is1_s3_vld_offset), + din => is1_s3_vld_d, + dout => is1_s3_vld_l2); +is1_s3: tri_rlmreg_p + generic map (width => is1_s3_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_s3_offset to is1_s3_offset + is1_s3_l2'length-1), + scout => sov(is1_s3_offset to is1_s3_offset + is1_s3_l2'length-1), + din => is1_s3_d, + dout => is1_s3_l2); +is1_pred_update: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_pred_update_offset), + scout => sov(is1_pred_update_offset), + din => is1_pred_update_d, + dout => is1_pred_update_l2); +is1_pred_taken_cnt: tri_rlmreg_p + generic map (width => is1_pred_taken_cnt_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_pred_taken_cnt_offset to is1_pred_taken_cnt_offset + is1_pred_taken_cnt_l2'length-1), + scout => sov(is1_pred_taken_cnt_offset to is1_pred_taken_cnt_offset + is1_pred_taken_cnt_l2'length-1), + din => is1_pred_taken_cnt_d, + dout => is1_pred_taken_cnt_l2); +is1_gshare: tri_rlmreg_p + generic map (width => is1_gshare_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_gshare_offset to is1_gshare_offset + is1_gshare_l2'length-1), + scout => sov(is1_gshare_offset to is1_gshare_offset + is1_gshare_l2'length-1), + din => is1_gshare_d, + dout => is1_gshare_l2); +is1_UpdatesLR: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_UpdatesLR_offset), + scout => sov(is1_UpdatesLR_offset), + din => is1_UpdatesLR_d, + dout => is1_UpdatesLR_l2); +is1_UpdatesCR: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_UpdatesCR_offset), + scout => sov(is1_UpdatesCR_offset), + din => is1_UpdatesCR_d, + dout => is1_UpdatesCR_l2); +is1_UpdatesCTR: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_UpdatesCTR_offset), + scout => sov(is1_UpdatesCTR_offset), + din => is1_UpdatesCTR_d, + dout => is1_UpdatesCTR_l2); +is1_UpdatesXER: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_UpdatesXER_offset), + scout => sov(is1_UpdatesXER_offset), + din => is1_UpdatesXER_d, + dout => is1_UpdatesXER_l2); +is1_UpdatesMSR: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_UpdatesMSR_offset), + scout => sov(is1_UpdatesMSR_offset), + din => is1_UpdatesMSR_d, + dout => is1_UpdatesMSR_l2); +is1_UpdatesSPR: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_UpdatesSPR_offset), + scout => sov(is1_UpdatesSPR_offset), + din => is1_UpdatesSPR_d, + dout => is1_UpdatesSPR_l2); +is1_UsesLR: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_UsesLR_offset), + scout => sov(is1_UsesLR_offset), + din => is1_UsesLR_d, + dout => is1_UsesLR_l2); +is1_UsesCR: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_UsesCR_offset), + scout => sov(is1_UsesCR_offset), + din => is1_UsesCR_d, + dout => is1_UsesCR_l2); +is1_UsesCTR: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_UsesCTR_offset), + scout => sov(is1_UsesCTR_offset), + din => is1_UsesCTR_d, + dout => is1_UsesCTR_l2); +is1_UsesXER: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_UsesXER_offset), + scout => sov(is1_UsesXER_offset), + din => is1_UsesXER_d, + dout => is1_UsesXER_l2); +is1_UsesMSR: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_UsesMSR_offset), + scout => sov(is1_UsesMSR_offset), + din => is1_UsesMSR_d, + dout => is1_UsesMSR_l2); +is1_UsesSPR: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_UsesSPR_offset), + scout => sov(is1_UsesSPR_offset), + din => is1_UsesSPR_d, + dout => is1_UsesSPR_l2); +is1_ld_vld: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_ld_vld_offset), + scout => sov(is1_ld_vld_offset), + din => is1_ld_vld_d, + dout => is1_ld_vld_l2); +is1_is_ucode: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_is_ucode_offset), + scout => sov(is1_is_ucode_offset), + din => is1_is_ucode_d, + dout => is1_is_ucode_l2); +is1_to_ucode: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_to_ucode_offset), + scout => sov(is1_to_ucode_offset), + din => is1_to_ucode_d, + dout => is1_to_ucode_l2); +is1_ifar: tri_rlmreg_p + generic map (width => is1_ifar_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_ifar_offset to is1_ifar_offset + is1_ifar_l2'length-1), + scout => sov(is1_ifar_offset to is1_ifar_offset + is1_ifar_l2'length-1), + din => is1_ifar_d, + dout => is1_ifar_l2); +is1_error: tri_rlmreg_p + generic map (width => is1_error_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_error_offset to is1_error_offset + is1_error_l2'length-1), + scout => sov(is1_error_offset to is1_error_offset + is1_error_l2'length-1), + din => is1_error_d, + dout => is1_error_l2); +is1_axu_ldst_ra_v: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_axu_ldst_ra_v_offset), + scout => sov(is1_axu_ldst_ra_v_offset), + din => is1_axu_ldst_ra_v_d, + dout => is1_axu_ldst_ra_v_l2); +is1_axu_ldst_rb_v: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_axu_ldst_rb_v_offset), + scout => sov(is1_axu_ldst_rb_v_offset), + din => is1_axu_ldst_rb_v_d, + dout => is1_axu_ldst_rb_v_l2); +is1_axu_ld_or_st: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_axu_ld_or_st_offset), + scout => sov(is1_axu_ld_or_st_offset), + din => is1_axu_ld_or_st_d, + dout => is1_axu_ld_or_st_l2); +is1_axu_store: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_axu_store_offset), + scout => sov(is1_axu_store_offset), + din => is1_axu_store_d, + dout => is1_axu_store_l2); +is1_axu_ldst_size: tri_rlmreg_p + generic map (width => is1_axu_ldst_size_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_axu_ldst_size_offset to is1_axu_ldst_size_offset + is1_axu_ldst_size_l2'length-1), + scout => sov(is1_axu_ldst_size_offset to is1_axu_ldst_size_offset + is1_axu_ldst_size_l2'length-1), + din => is1_axu_ldst_size_d, + dout => is1_axu_ldst_size_l2); +is1_axu_ldst_update: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_axu_ldst_update_offset), + scout => sov(is1_axu_ldst_update_offset), + din => is1_axu_ldst_update_d, + dout => is1_axu_ldst_update_l2); +is1_axu_ldst_extpid: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_axu_ldst_extpid_offset), + scout => sov(is1_axu_ldst_extpid_offset), + din => is1_axu_ldst_extpid_d, + dout => is1_axu_ldst_extpid_l2); +is1_axu_ldst_forcealign: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_axu_ldst_forcealign_offset), + scout => sov(is1_axu_ldst_forcealign_offset), + din => is1_axu_ldst_forcealign_d, + dout => is1_axu_ldst_forcealign_l2); +is1_axu_ldst_forceexcept: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_axu_ldst_forceexcept_offset), + scout => sov(is1_axu_ldst_forceexcept_offset), + din => is1_axu_ldst_forceexcept_d, + dout => is1_axu_ldst_forceexcept_l2); +is1_axu_movedp: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_axu_movedp_offset), + scout => sov(is1_axu_movedp_offset), + din => is1_axu_movedp_d, + dout => is1_axu_movedp_l2); +is1_axu_mffgpr: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_axu_mffgpr_offset), + scout => sov(is1_axu_mffgpr_offset), + din => is1_axu_mffgpr_d, + dout => is1_axu_mffgpr_l2); +is1_axu_mftgpr: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_axu_mftgpr_offset), + scout => sov(is1_axu_mftgpr_offset), + din => is1_axu_mftgpr_d, + dout => is1_axu_mftgpr_l2); +is1_axu_instr_type: tri_rlmreg_p + generic map (width => is1_axu_instr_type_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_axu_instr_type_offset to is1_axu_instr_type_offset + is1_axu_instr_type_l2'length-1), + scout => sov(is1_axu_instr_type_offset to is1_axu_instr_type_offset + is1_axu_instr_type_l2'length-1), + din => is1_axu_instr_type_d, + dout => is1_axu_instr_type_l2); +is1_force_ram: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_force_ram_offset), + scout => sov(is1_force_ram_offset), + din => is1_force_ram_d, + dout => is1_force_ram_l2); +is1_2ucode: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_2ucode_offset), + scout => sov(is1_2ucode_offset), + din => is1_2ucode_d, + dout => is1_2ucode_l2); +is1_2ucode_type: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_2ucode_type_offset), + scout => sov(is1_2ucode_type_offset), + din => is1_2ucode_type_d, + dout => is1_2ucode_type_l2); +spare_latch: tri_rlmreg_p + generic map (width => spare_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(spare_offset to spare_offset + spare_l2'length-1), + scout => sov(spare_offset to spare_offset + spare_l2'length-1), + din => spare_l2, + dout => spare_l2); +iu_au_is1_cr_user_v <= is1_UsesCR_L2 and is1_vld_L2; +iu_au_is0_cr_setter <= UpdatesCR; +fdec_fdep_is1_vld <= is1_vld_L2 and or_reduce(is1_vld_type_L2(0 to 2)); +fdec_fdep_is1_instr(0 TO 15) <= is1_instr_L2(0 to 15); +fdec_fdep_is1_instr(16 TO 31) <= is1_axu_instr_L2(16 to 31) when is1_axu_ld_or_st_L2 = '1' and is1_to_ucode_L2 = '0' else + is1_instr_L2(16 to 31); +fdec_fdep_is1_axu_ldst_indexed <= is1_axu_instr_L2(6); +fdec_fdep_is1_axu_ldst_tag <= is1_axu_instr_L2(7 to 15); +fdec_fdep_is1_ta_vld <= (is1_ta_vld_L2 and is1_vld_type_L2(2)) or + (is1_axu_ldst_update_L2 or (is1_axu_mftgpr_L2 and not is1_axu_movedp_L2)); +fdec_fdep_is1_ta <= is1_ta_L2; +fdec_fdep_is1_s1_vld <= (is1_s1_vld_L2 and is1_vld_type_L2(2)) or + is1_axu_ldst_ra_v_L2; +fdec_fdep_is1_s1 <= is1_s1_L2; +fdec_fdep_is1_s2_vld <= (is1_s2_vld_L2 and is1_vld_type_L2(2)) or + is1_axu_ldst_rb_v_L2; +fdec_fdep_is1_s2 <= is1_s2_L2; +fdec_fdep_is1_s3_vld <= (is1_s3_vld_L2 and is1_vld_type_L2(2)) or + (is1_axu_ldst_rb_v_L2 and is1_axu_mffgpr_L2); +fdec_fdep_is1_s3 <= is1_s3_L2; +fdec_fdep_is1_pred_update <= is1_pred_update_L2; +fdec_fdep_is1_pred_taken_cnt <= is1_pred_taken_cnt_L2; +fdec_fdep_is1_gshare <= is1_gshare_L2; +fdec_fdep_is1_UpdatesLR <= is1_UpdatesLR_L2; +fdec_fdep_is1_UpdatesCR <= is1_UpdatesCR_L2; +fdec_fdep_is1_UpdatesCTR <= is1_UpdatesCTR_L2; +fdec_fdep_is1_UpdatesXER <= is1_UpdatesXER_L2; +fdec_fdep_is1_UpdatesMSR <= is1_UpdatesMSR_L2; +fdec_fdep_is1_UpdatesSPR <= is1_UpdatesSPR_L2; +fdec_fdep_is1_UsesLR <= is1_UsesLR_L2; +fdec_fdep_is1_UsesCR <= is1_UsesCR_L2; +fdec_fdep_is1_UsesCTR <= is1_UsesCTR_L2; +fdec_fdep_is1_UsesXER <= is1_UsesXER_L2; +fdec_fdep_is1_UsesMSR <= is1_UsesMSR_L2; +fdec_fdep_is1_UsesSPR <= is1_UsesSPR_L2; +fdec_fdep_is1_hole_delay <= hole_delay; +fdec_fdep_is1_ld_vld <= (is1_ld_vld_L2 and is1_vld_type_L2(2)) or + (is1_axu_ldst_update_L2 and not is1_axu_store_L2); +fdec_fdep_is1_to_ucode <= is1_to_ucode_L2 or is1_2ucode_L2 or to_uc; +fdec_fdep_is1_is_ucode <= is1_is_ucode_L2; +fdec_fdep_is1_complete <= compl_ex; +fdec_fdep_is1_ifar <= is1_ifar_L2; +fdec_fdep_is1_error(0 TO 1) <= is1_error_L2(0 to 1); +fdec_fdep_is1_error(2) <= not is1_axu_ld_or_st_L2 and not is1_to_ucode_L2 and not isFxuIssue when is1_error_L2(0 to 1) = "00" else + is1_error_L2(2); +fdec_fdep_is1_axu_ld_or_st <= is1_axu_ld_or_st_L2; +fdec_fdep_is1_axu_store <= is1_axu_store_L2; +fdec_fdep_is1_axu_ldst_size <= is1_axu_ldst_size_L2; +fdec_fdep_is1_axu_ldst_update <= is1_axu_ldst_update_L2; +fdec_fdep_is1_axu_ldst_extpid <= is1_axu_ldst_extpid_L2; +fdec_fdep_is1_axu_ldst_forcealign <= is1_axu_ldst_forcealign_L2; +fdec_fdep_is1_axu_ldst_forceexcept <= is1_axu_ldst_forceexcept_L2; +fdec_fdep_is1_axu_mftgpr <= is1_axu_mftgpr_L2; +fdec_fdep_is1_axu_mffgpr <= is1_axu_mffgpr_L2; +fdec_fdep_is1_axu_movedp <= is1_axu_movedp_L2; +fdec_fdep_is1_axu_instr_type <= gate(is1_axu_instr_type_L2, is1_axu_ld_or_st_L2 or is1_to_ucode_L2); +fdec_fdep_is1_match <= (spr_dec_mask(0 to 31) and is1_instr_L2(0 to 31)) = (spr_dec_mask(0 to 31) and spr_dec_match(0 to 31)); +fdec_fdep_is1_force_ram <= is1_force_ram_L2; +fdec_fdep_is1_2ucode <= is1_2ucode_L2; +fdec_fdep_is1_2ucode_type <= is1_2ucode_type_L2; +siv(0 TO scan_right) <= sov(1 to scan_right) & scan_in; +scan_out <= sov(0); +END IUQ_FXU_DECODE; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_fxu_dep.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_fxu_dep.vhdl new file mode 100644 index 0000000..0d9300d --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_fxu_dep.vhdl @@ -0,0 +1,2917 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee, ibm; +use ieee.std_logic_1164.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +library support; +use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; +library work; +use work.iuq_pkg.all; + +entity iuq_fxu_dep is + generic(expand_type : integer := 2; + regmode : integer := 6; + lmq_entries : integer := 8); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + + pc_iu_func_sl_thold_0_b : in std_ulogic; + pc_iu_sg_0 : in std_ulogic; + forcee : in std_ulogic; + d_mode : in std_ulogic; + delay_lclkr : in std_ulogic; + mpw1_b : in std_ulogic; + mpw2_b : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + pc_iu_trace_bus_enable : in std_ulogic; + pc_iu_event_bus_enable : in std_ulogic; + fdep_dbg_data : out std_ulogic_vector(0 to 21); + fdep_perf_event : out std_ulogic_vector(0 to 11); + + + + fdec_fdep_is1_vld : in std_ulogic; + fdec_fdep_is1_instr : in std_ulogic_vector(0 to 31); + fdec_fdep_is1_ta_vld : in std_ulogic; + fdec_fdep_is1_ta : in std_ulogic_vector(0 to 5); + fdec_fdep_is1_s1_vld : in std_ulogic; + fdec_fdep_is1_s1 : in std_ulogic_vector(0 to 5); + fdec_fdep_is1_s2_vld : in std_ulogic; + fdec_fdep_is1_s2 : in std_ulogic_vector(0 to 5); + fdec_fdep_is1_s3_vld : in std_ulogic; + fdec_fdep_is1_s3 : in std_ulogic_vector(0 to 5); + fdec_fdep_is1_pred_update : in std_ulogic; + fdec_fdep_is1_pred_taken_cnt : in std_ulogic_vector(0 to 1); + fdec_fdep_is1_gshare : in std_ulogic_vector(0 to 3); + fdec_fdep_is1_UpdatesLR : in std_ulogic; + fdec_fdep_is1_UpdatesCR : in std_ulogic; + fdec_fdep_is1_UpdatesCTR : in std_ulogic; + fdec_fdep_is1_UpdatesXER : in std_ulogic; + fdec_fdep_is1_UpdatesMSR : in std_ulogic; + fdec_fdep_is1_UpdatesSPR : in std_ulogic; + fdec_fdep_is1_UsesLR : in std_ulogic; + fdec_fdep_is1_UsesCR : in std_ulogic; + fdec_fdep_is1_UsesCTR : in std_ulogic; + fdec_fdep_is1_UsesXER : in std_ulogic; + fdec_fdep_is1_UsesMSR : in std_ulogic; + fdec_fdep_is1_UsesSPR : in std_ulogic; + fdec_fdep_is1_hole_delay : in std_ulogic_vector(0 to 2); + fdec_fdep_is1_ld_vld : in std_ulogic; + fdec_fdep_is1_to_ucode : in std_ulogic; + fdec_fdep_is1_is_ucode : in std_ulogic; + fdec_fdep_is1_ifar : in EFF_IFAR; + fdec_fdep_is1_error : in std_ulogic_vector(0 to 2); + fdec_fdep_is1_complete : in std_ulogic_vector(0 to 4); + + fdec_fdep_is1_axu_ld_or_st : in std_ulogic; + fdec_fdep_is1_axu_store : in std_ulogic; + fdec_fdep_is1_axu_ldst_indexed : in std_ulogic; + fdec_fdep_is1_axu_ldst_tag : in std_ulogic_vector(0 to 8); + fdec_fdep_is1_axu_ldst_size : in std_ulogic_vector(0 to 5); + fdec_fdep_is1_axu_ldst_update : in std_ulogic; + fdec_fdep_is1_axu_ldst_extpid : in std_ulogic; + fdec_fdep_is1_axu_ldst_forcealign : in std_ulogic; + fdec_fdep_is1_axu_ldst_forceexcept : in std_ulogic; + fdec_fdep_is1_axu_mftgpr : in std_ulogic; + fdec_fdep_is1_axu_mffgpr : in std_ulogic; + fdec_fdep_is1_axu_movedp : in std_ulogic; + fdec_fdep_is1_axu_instr_type : in std_ulogic_vector(0 to 2); + fdec_fdep_is1_match : in std_ulogic; + fdec_fdep_is1_force_ram : in std_ulogic; + fdec_fdep_is1_2ucode : in std_ulogic; + fdec_fdep_is1_2ucode_type : in std_ulogic; + + + fdep_fiss_is2_instr : out std_ulogic_vector(0 to 31); + fdep_fiss_is2_ta_vld : out std_ulogic; + fdep_fiss_is2_ta : out std_ulogic_vector(0 to 5); + fdep_fiss_is2_s1_vld : out std_ulogic; + fdep_fiss_is2_s1 : out std_ulogic_vector(0 to 5); + fdep_fiss_is2_s2_vld : out std_ulogic; + fdep_fiss_is2_s2 : out std_ulogic_vector(0 to 5); + fdep_fiss_is2_s3_vld : out std_ulogic; + fdep_fiss_is2_s3 : out std_ulogic_vector(0 to 5); + fdep_fiss_is2_pred_update : out std_ulogic; + fdep_fiss_is2_pred_taken_cnt : out std_ulogic_vector(0 to 1); + fdep_fiss_is2_gshare : out std_ulogic_vector(0 to 3); + fdep_fiss_is2_ifar : out EFF_IFAR; + fdep_fiss_is2_error : out std_ulogic_vector(0 to 2); + fdep_fiss_is2_axu_ld_or_st : out std_ulogic; + fdep_fiss_is2_axu_store : out std_ulogic; + fdep_fiss_is2_axu_ldst_indexed : out std_ulogic; + fdep_fiss_is2_axu_ldst_tag : out std_ulogic_vector(0 to 8); + fdep_fiss_is2_axu_ldst_size : out std_ulogic_vector(0 to 5); + fdep_fiss_is2_axu_ldst_update : out std_ulogic; + fdep_fiss_is2_axu_ldst_extpid : out std_ulogic; + fdep_fiss_is2_axu_ldst_forcealign : out std_ulogic; + fdep_fiss_is2_axu_ldst_forceexcept : out std_ulogic; + fdep_fiss_is2_axu_mftgpr : out std_ulogic; + fdep_fiss_is2_axu_mffgpr : out std_ulogic; + fdep_fiss_is2_axu_movedp : out std_ulogic; + fdep_fiss_is2_axu_instr_type : out std_ulogic_vector(0 to 2); + fdep_fiss_is2_match : out std_ulogic; + fdep_fiss_is2_2ucode : out std_ulogic; + fdep_fiss_is2_2ucode_type : out std_ulogic; + fdep_fiss_is2_hole_delay : out std_ulogic_vector(0 to 2); + fdep_fiss_is2_to_ucode : out std_ulogic; + fdep_fiss_is2_is_ucode : out std_ulogic; + fdep_fiss_is2early_vld : out std_ulogic; + fdep_fiss_is1_xu_dep_hit_b : out std_ulogic; + fiss_fdep_is2_take : in std_ulogic; + + i_afd_is1_instr_v : in std_ulogic; + au_iu_issue_stall : in std_ulogic; + iu_au_is2_stall : out std_ulogic; + au_iu_is1_dep_hit : in std_ulogic; + au_iu_is1_dep_hit_b : in std_ulogic; + au_iu_is2_axubusy : in std_ulogic; + iu_au_is1_hold : out std_ulogic; + iu_au_is1_stall : out std_ulogic; + fdep_fdec_buff_stall : out std_ulogic; + fdep_fdec_weak_stall : out std_ulogic; + + xu_iu_slowspr_done : in std_ulogic; + xu_iu_multdiv_done : in std_ulogic; + xu_iu_loadmiss_vld : in std_ulogic; + xu_iu_loadmiss_qentry : in std_ulogic_vector(0 to lmq_entries-1); + xu_iu_loadmiss_target : in std_ulogic_vector(0 to 5); + xu_iu_loadmiss_target_type : in std_ulogic; + xu_iu_complete_vld : in std_ulogic; + xu_iu_complete_qentry : in std_ulogic_vector(0 to lmq_entries-1); + xu_iu_complete_target_type : in std_ulogic; + xu_iu_single_instr_mode : in std_ulogic; + + ic_fdep_load_quiesce : in std_ulogic; + iu_xu_quiesce : out std_ulogic; + + xu_iu_membar_tid : in std_ulogic; + xu_iu_set_barr_tid : in std_ulogic; + xu_iu_larx_done_tid : in std_ulogic; + an_ac_sync_ack : in std_ulogic; + ic_fdep_icbi_ack : in std_ulogic; + an_ac_stcx_complete : in std_ulogic; + mm_iu_barrier_done : in std_ulogic; + + spr_fdep_ll_hold : in std_ulogic; + xu_iu_spr_ccr2_en_dcr : in std_ulogic; + + xu_iu_is1_flush : in std_ulogic; + xu_iu_is2_flush : in std_ulogic; + xu_iu_rf0_flush : in std_ulogic; + xu_iu_rf1_flush : in std_ulogic; + xu_iu_ex1_flush : in std_ulogic; + xu_iu_ex2_flush : in std_ulogic; + xu_iu_ex3_flush : in std_ulogic; + xu_iu_ex4_flush : in std_ulogic; + xu_iu_ex5_flush : in std_ulogic +); +end iuq_fxu_dep; +ARCHITECTURE IUQ_FXU_DEP + OF IUQ_FXU_DEP + IS +SIGNAL BARRIER_PT : STD_ULOGIC_VECTOR(1 TO 24) := +(OTHERS=> 'U'); +SIGNAL SLOWSPR_TABLE_PT : STD_ULOGIC_VECTOR(1 TO 20) := +(OTHERS=> 'U'); +SIGNAL is_bar : STD_ULOGIC := +'U'; +SIGNAL is_slowspr : STD_ULOGIC := +'U'; +constant is2_vld_offset : natural := 0; +constant is2_instr_offset : natural := is2_vld_offset + 1; +constant is2_ta_vld_offset : natural := is2_instr_offset + 32; +constant is2_ta_offset : natural := is2_ta_vld_offset + 1; +constant is2_s1_vld_offset : natural := is2_ta_offset + 6; +constant is2_s1_offset : natural := is2_s1_vld_offset + 1; +constant is2_s2_vld_offset : natural := is2_s1_offset + 6; +constant is2_s2_offset : natural := is2_s2_vld_offset + 1; +constant is2_s3_vld_offset : natural := is2_s2_offset + 6; +constant is2_s3_offset : natural := is2_s3_vld_offset + 1; +constant is2_is_barrier_offset : natural := is2_s3_offset + 6; +constant is2_is_slowspr_offset : natural := is2_is_barrier_offset + 1; +constant is2_pred_update_offset : natural := is2_is_slowspr_offset + 1; +constant is2_pred_taken_cnt_offset : natural := is2_pred_update_offset + 1; +constant is2_gshare_offset : natural := is2_pred_taken_cnt_offset + 2; +constant is2_hole_delay_offset : natural := is2_gshare_offset + 4; +constant is2_to_ucode_offset : natural := is2_hole_delay_offset +3; +constant is2_is_ucode_offset : natural := is2_to_ucode_offset + 1; +constant is2_ifar_offset : natural := is2_is_ucode_offset + 1; +constant is2_error_offset : natural := is2_ifar_offset + EFF_IFAR'length; +constant is2_axu_ld_or_st_offset : natural := is2_error_offset + 3; +constant is2_axu_store_offset : natural := is2_axu_ld_or_st_offset + 1; +constant is2_axu_ldst_indexed_offset : natural := is2_axu_store_offset + 1; +constant is2_axu_ldst_tag_offset : natural := is2_axu_ldst_indexed_offset + 1; +constant is2_axu_ldst_size_offset : natural := is2_axu_ldst_tag_offset + 9; +constant is2_axu_ldst_update_offset : natural := is2_axu_ldst_size_offset + 6; +constant is2_axu_ldst_extpid_offset : natural := is2_axu_ldst_update_offset + 1; +constant is2_axu_ldst_forcealign_offset : natural := is2_axu_ldst_extpid_offset + 1; +constant is2_axu_ldst_forceexcept_offset: natural := is2_axu_ldst_forcealign_offset + 1; +constant is2_axu_mftgpr_offset : natural := is2_axu_ldst_forceexcept_offset + 1; +constant is2_axu_mffgpr_offset : natural := is2_axu_mftgpr_offset + 1; +constant is2_axu_movedp_offset : natural := is2_axu_mffgpr_offset + 1; +constant is2_axu_instr_type_offset : natural := is2_axu_movedp_offset + 1; +constant is2_match_offset : natural := is2_axu_instr_type_offset + 3; +constant is2_2ucode_offset : natural := is2_match_offset + 1; +constant is2_2ucode_type_offset : natural := is2_2ucode_offset + 1; +constant sp_ex3_i_nobyp_vld_offset : natural := is2_2ucode_type_offset + 1; +constant sp_ex3_barrier_offset : natural := sp_ex3_i_nobyp_vld_offset + 1; +constant sp_ex4_i_nobyp_vld_offset : natural := sp_ex3_barrier_offset + 1; +constant sp_ex4_barrier_offset : natural := sp_ex4_i_nobyp_vld_offset + 1; +constant sp_ex5_i_nobyp_vld_offset : natural := sp_ex4_barrier_offset + 1; +constant sp_ex5_barrier_offset : natural := sp_ex5_i_nobyp_vld_offset + 1; +constant sp_is2_offset : natural := sp_ex5_barrier_offset + 1; +constant sp_rf0_offset : natural := sp_is2_offset +21; +constant sp_rf1_offset : natural := sp_rf0_offset +21; +constant sp_ex1_offset : natural := sp_rf1_offset +21; +constant sp_ex2_offset : natural := sp_ex1_offset +21; +constant sp_lm_offset : natural := sp_ex2_offset +21; +constant barrier_offset : natural := sp_lm_offset +7*lmq_entries; +constant xu_barrier_offset : natural := barrier_offset +1; +constant mult_hole_barrier_offset : natural := xu_barrier_offset +1; +constant single_instr_mode_offset : natural := mult_hole_barrier_offset +6; +constant quiesce_offset : natural := single_instr_mode_offset +1; +constant perf_event_offset : natural := quiesce_offset +1; +constant perf_early_offset : natural := perf_event_offset +12; +constant fdep_dbg_data_offset : natural := perf_early_offset +12; +constant an_ac_sync_ack_offset : natural := fdep_dbg_data_offset +22; +constant xu_iu_membar_tid_offset : natural := an_ac_sync_ack_offset +1; +constant xu_iu_multdiv_done_offset : natural := xu_iu_membar_tid_offset +1; +constant mm_iu_barrier_done_offset : natural := xu_iu_multdiv_done_offset +1; +constant spr_fdep_ll_hold_offset : natural := mm_iu_barrier_done_offset +1; +constant en_dcr_offset : natural := spr_fdep_ll_hold_offset +1; +constant spare_offset : natural := en_dcr_offset +1; +constant trace_bus_enable_offset : natural := spare_offset + 6; +constant event_bus_enable_offset : natural := trace_bus_enable_offset + 1; +constant scan_right : natural := event_bus_enable_offset + 1 - 1; +signal spare_l2 : std_ulogic_vector(0 to 5); +signal trace_bus_enable_d : std_ulogic; +signal trace_bus_enable_q : std_ulogic; +signal event_bus_enable_d : std_ulogic; +signal event_bus_enable_q : std_ulogic; +signal siv : std_ulogic_vector(0 to scan_right); +signal sov : std_ulogic_vector(0 to scan_right); +signal tiup : std_ulogic; +signal tidn : std_ulogic; +signal unused : std_ulogic_vector(0 to 4); +-- synopsys translate_off +-- synopsys translate_on +signal single_instr_mode_d : std_ulogic; +signal single_instr_mode_l2 : std_ulogic; +signal is2_vld_d : std_ulogic; +signal is2_instr_d : std_ulogic_vector(0 to 31); +signal is2_ta_vld_d : std_ulogic; +signal is2_ta_d : std_ulogic_vector(0 to 5); +signal is2_s1_vld_d : std_ulogic; +signal is2_s1_d : std_ulogic_vector(0 to 5); +signal is2_s2_vld_d : std_ulogic; +signal is2_s2_d : std_ulogic_vector(0 to 5); +signal is2_s3_vld_d : std_ulogic; +signal is2_s3_d : std_ulogic_vector(0 to 5); +signal is2_is_barrier_d : std_ulogic; +signal is2_is_slowspr_d : std_ulogic; +signal is2_pred_update_d : std_ulogic; +signal is2_pred_taken_cnt_d : std_ulogic_vector(0 to 1); +signal is2_gshare_d : std_ulogic_vector(0 to 3); +signal is2_hole_delay_d : std_ulogic_vector(0 to 2); +signal is2_to_ucode_d : std_ulogic; +signal is2_is_ucode_d : std_ulogic; +signal is2_ifar_d : EFF_IFAR; +signal is2_error_d : std_ulogic_vector(0 to 2); +signal is2_axu_ld_or_st_d : std_ulogic; +signal is2_axu_store_d : std_ulogic; +signal is2_axu_ldst_indexed_d : std_ulogic; +signal is2_axu_ldst_tag_d : std_ulogic_vector(0 to 8); +signal is2_axu_ldst_size_d : std_ulogic_vector(0 to 5); +signal is2_axu_ldst_update_d : std_ulogic; +signal is2_axu_ldst_extpid_d : std_ulogic; +signal is2_axu_ldst_forcealign_d : std_ulogic; +signal is2_axu_ldst_forceexcept_d : std_ulogic; +signal is2_axu_mftgpr_d : std_ulogic; +signal is2_axu_mffgpr_d : std_ulogic; +signal is2_axu_movedp_d : std_ulogic; +signal is2_axu_instr_type_d : std_ulogic_vector(0 to 2); +signal is2_match_d : std_ulogic; +signal is2_2ucode_d : std_ulogic; +signal is2_2ucode_type_d : std_ulogic; +signal is2_vld_L2 : std_ulogic; +signal is2_instr_L2 : std_ulogic_vector(0 to 31); +signal is2_ta_vld_L2 : std_ulogic; +signal is2_ta_L2 : std_ulogic_vector(0 to 5); +signal is2_s1_vld_L2 : std_ulogic; +signal is2_s1_L2 : std_ulogic_vector(0 to 5); +signal is2_s2_vld_L2 : std_ulogic; +signal is2_s2_L2 : std_ulogic_vector(0 to 5); +signal is2_s3_vld_L2 : std_ulogic; +signal is2_s3_L2 : std_ulogic_vector(0 to 5); +signal is2_is_barrier_L2 : std_ulogic; +signal is2_is_slowspr_L2 : std_ulogic; +signal is2_pred_update_L2 : std_ulogic; +signal is2_pred_taken_cnt_L2 : std_ulogic_vector(0 to 1); +signal is2_gshare_L2 : std_ulogic_vector(0 to 3); +signal is2_hole_delay_L2 : std_ulogic_vector(0 to 2); +signal is2_to_ucode_L2 : std_ulogic; +signal is2_is_ucode_L2 : std_ulogic; +signal is2_ifar_L2 : EFF_IFAR; +signal is2_error_L2 : std_ulogic_vector(0 to 2); +signal is2_axu_ld_or_st_L2 : std_ulogic; +signal is2_axu_store_L2 : std_ulogic; +signal is2_axu_ldst_indexed_L2 : std_ulogic; +signal is2_axu_ldst_tag_L2 : std_ulogic_vector(0 to 8); +signal is2_axu_ldst_size_L2 : std_ulogic_vector(0 to 5); +signal is2_axu_ldst_update_L2 : std_ulogic; +signal is2_axu_ldst_extpid_L2 : std_ulogic; +signal is2_axu_ldst_forcealign_L2 : std_ulogic; +signal is2_axu_ldst_forceexcept_L2 : std_ulogic; +signal is2_axu_mftgpr_L2 : std_ulogic; +signal is2_axu_mffgpr_L2 : std_ulogic; +signal is2_axu_movedp_L2 : std_ulogic; +signal is2_axu_instr_type_L2 : std_ulogic_vector(0 to 2); +signal is2_match_L2 : std_ulogic; +signal is2_2ucode_L2 : std_ulogic; +signal is2_2ucode_type_L2 : std_ulogic; +signal is1_instr_is_isync : std_ulogic; +signal is1_instr_is_sync : std_ulogic; +signal is1_instr_is_tlbsync : std_ulogic; +signal RAW_dep_hit : std_ulogic; +signal RAW_s1_hit_b : std_ulogic; +signal RAW_s2_hit_b : std_ulogic; +signal RAW_s3_hit_b : std_ulogic; +signal lr_dep_hit : std_ulogic; +signal cr_dep_hit : std_ulogic; +signal ctr_dep_hit : std_ulogic; +signal xer_dep_hit : std_ulogic; +signal msr_dep_hit : std_ulogic; +signal spr_dep_hit : std_ulogic; +signal br_sprs_dep_hit : std_ulogic; +signal WAW_LMQ_dep_hit : std_ulogic; +signal WAW_LMQ_dep_hit_b : std_ulogic; +signal single_instr_dep_hit : std_ulogic; +signal internal_is2_stall : std_ulogic; +signal dep_hit : std_ulogic; +signal dep_hit_no_stall : std_ulogic; +signal xu_dep_hit : std_ulogic; +signal is2_instr_is_barrier : std_ulogic; +signal act_nonvalid : std_ulogic; +signal sp_IS2_d : std_ulogic_vector(0 to 20); +signal sp_IS2_l2 : std_ulogic_vector(0 to 20); +signal sp_RF0_d : std_ulogic_vector(0 to 20); +signal sp_RF0_l2 : std_ulogic_vector(0 to 20); +signal sp_RF1_d : std_ulogic_vector(0 to 20); +signal sp_RF1_l2 : std_ulogic_vector(0 to 20); +signal sp_EX1_d : std_ulogic_vector(0 to 20); +signal sp_EX1_l2 : std_ulogic_vector(0 to 20); +signal sp_EX2_d : std_ulogic_vector(0 to 20); +signal sp_EX2_l2 : std_ulogic_vector(0 to 20); +signal sp_IS2_act : std_ulogic; +signal sp_RF0_act : std_ulogic; +signal sp_RF1_act : std_ulogic; +signal sp_EX1_act : std_ulogic; +signal sp_EX2_act : std_ulogic; +signal sp_EX3_act : std_ulogic; +signal sp_EX4_act : std_ulogic; +signal sp_EX5_act : std_ulogic; +signal sp_LM_d : std_ulogic_vector(0 to 7*lmq_entries-1); +signal sp_LM_l2 : std_ulogic_vector(0 to 7*lmq_entries-1); +signal lm_shadow_pipe_vld : std_ulogic_vector(0 to lmq_entries-1); +signal fdep_dbg_data_d : std_ulogic_vector(0 to 21); +signal fdep_dbg_data_l2 : std_ulogic_vector(0 to 21); +signal perf_event_d : std_ulogic_vector(0 to 11); +signal perf_event_l2 : std_ulogic_vector(0 to 11); +signal perf_early_d : std_ulogic_vector(0 to 11); +signal perf_early_l2 : std_ulogic_vector(0 to 11); +signal perf_dep_hit : std_ulogic; +signal perf_fdec_fdep_is1_vld : std_ulogic; +signal perf_internal_is2_stall : std_ulogic; +signal perf_i_afd_is1_instr_v : std_ulogic; +signal perf_au_iu_is1_dep_hit : std_ulogic; +signal perf_barrier_in_progress : std_ulogic; +signal perf_is2_is_slowspr_L2 : std_ulogic; +signal perf_RAW_dep_hit : std_ulogic; +signal perf_WAW_LMQ_dep_hit : std_ulogic; +signal perf_sync_dep_hit : std_ulogic; +signal perf_xu_dep_hit : std_ulogic; +signal perf_br_sprs_dep_hit : std_ulogic; +signal isMFSPR : std_ulogic; +signal isMTSPR : std_ulogic; +signal is1_is_slowspr : std_ulogic; +signal is1_is_barrier : std_ulogic; +signal an_ac_sync_ack_d : std_ulogic; +signal an_ac_sync_ack_l2 : std_ulogic; +signal xu_iu_membar_tid_d : std_ulogic; +signal xu_iu_membar_tid_l2 : std_ulogic; +signal xu_iu_multdiv_done_d : std_ulogic; +signal xu_iu_multdiv_done_l2 : std_ulogic; +signal mm_iu_barrier_done_d : std_ulogic; +signal mm_iu_barrier_done_l2 : std_ulogic; +signal spr_fdep_ll_hold_d : std_ulogic; +signal spr_fdep_ll_hold_l2 : std_ulogic; +signal is2_mult_hole_barrier : std_ulogic; +signal mult_hole_barrier_d : std_ulogic_vector(0 to 5); +signal mult_hole_barrier_l2 : std_ulogic_vector(0 to 5); +signal mult_hole_barrier_act : std_ulogic; +signal xu_barrier_d : std_ulogic; +signal xu_barrier_l2 : std_ulogic; +signal en_dcr_d : std_ulogic; +signal en_dcr_l2 : std_ulogic; +type PIPE_STAGE is record + i_nobyp_vld : std_ulogic; + i_vld : std_ulogic; + ta_vld : std_ulogic; + ta : std_ulogic_vector(0 to 5); + UpdatesLR : std_ulogic; + UpdatesCR : std_ulogic; + UPdatesCTR : std_ulogic; + UpdatesXER : std_ulogic; + UpdatesMSR : std_ulogic; + UPdatesSPR : std_ulogic; + complete : std_ulogic_vector(0 to 4); + barrier : std_ulogic; +end record; +type SHADOW_PIPE_STAGES is (IS2, RF0, RF1, EX1, EX2); +type MACHINE is array (SHADOW_PIPE_STAGES'left to SHADOW_PIPE_STAGES'right) of PIPE_STAGE; +signal sp_d : MACHINE; +signal sp_L2 : MACHINE; +signal sp_barrier_clr : std_ulogic; +signal sp_EX3_i_nobyp_vld_d : std_ulogic; +signal sp_EX3_i_nobyp_vld_l2 : std_ulogic; +signal sp_EX3_barrier_d : std_ulogic; +signal sp_EX3_barrier_l2 : std_ulogic; +signal sp_EX4_i_nobyp_vld_d : std_ulogic; +signal sp_EX4_i_nobyp_vld_l2 : std_ulogic; +signal sp_EX4_barrier_d : std_ulogic; +signal sp_EX4_barrier_l2 : std_ulogic; +signal sp_EX5_i_nobyp_vld_d : std_ulogic; +signal sp_EX5_i_nobyp_vld_l2 : std_ulogic; +signal sp_EX5_barrier_d : std_ulogic; +signal sp_EX5_barrier_l2 : std_ulogic; +type PIPE_STAGE_LM is record + ta_vld : std_ulogic; + ta : std_ulogic_vector(0 to 5); +end record; +type MACHINE_LM is array (0 to lmq_entries-1) of PIPE_STAGE_LM; +signal sp_d_LM : MACHINE_LM; +signal sp_L2_LM : MACHINE_LM; +signal loadmiss_qentry : std_ulogic_vector(0 to lmq_entries-1); +signal loadmiss_target : std_ulogic_vector(0 to 5); +signal loadmiss_complete : std_ulogic_vector(0 to lmq_entries-1); +signal shadow_pipe_vld : std_ulogic; +signal sync_dep_hit : std_ulogic; +signal set_barrier : std_ulogic; +signal clr_barrier : std_ulogic; +signal barrier_d : std_ulogic; +signal barrier_L2 : std_ulogic; +signal barrier_in_progress : std_ulogic; +signal quiesce_barrier : std_ulogic; +subtype s2 is std_ulogic_vector(0 to 1); +subtype s15 is std_ulogic_vector(0 to 14); +signal quiesce_d : std_ulogic; +signal quiesce_l2 : std_ulogic; +signal core64 : std_ulogic; +signal is1_force_ram_b : std_ulogic; +signal is1_valid : std_ulogic; +signal is1_dep : std_ulogic; +signal is1_dep0_b : std_ulogic; +signal is1_dep1_b : std_ulogic; +signal is1_stall_b : std_ulogic; +signal is2_stall_b : std_ulogic; +signal fxu_dep0_b : std_ulogic; +signal fxu_dep1_b : std_ulogic; +signal fxu_dep_hit : std_ulogic; +signal fxu_dep_hit_b : std_ulogic; +signal is2_vld_b : std_ulogic; +signal fxu_iss_stall : std_ulogic; +signal is2_iss_stall_b : std_ulogic; + BEGIN + +tiup <= '1'; +tidn <= '0'; +c64: if (regmode = 6) generate +begin +core64 <= '1'; +end generate; +c32: if (regmode = 5) generate +begin +core64 <= '0'; +end generate; +en_dcr_d <= xu_iu_spr_ccr2_en_dcr; +is1_instr_is_ISYNC <= (fdec_fdep_is1_instr(0 to 5) = "010011") and (fdec_fdep_is1_instr(21 to 30) = "0010010110"); +is1_instr_is_SYNC <= (fdec_fdep_is1_instr(0 to 5) = "011111") and (fdec_fdep_is1_instr(21 to 30) = "1001010110"); +is1_instr_is_TLBSYNC <= (fdec_fdep_is1_instr(0 to 5) = "011111") and (fdec_fdep_is1_instr(21 to 30) = "1000110110"); + +raw_s1_cmp: entity work.iuq_fxu_dep_cmp(iuq_fxu_dep_cmp) +port map ( + is1_v => fdec_fdep_is1_s1_vld, + + is2_v => sp_L2(IS2).ta_vld, + rf0_v => sp_L2(RF0).ta_vld, + rf1_v => sp_L2(RF1).ta_vld, + ex1_v => sp_L2(EX1).ta_vld, + ex2_v => sp_L2(EX2).ta_vld, + lm0_v => sp_L2_LM(0).ta_vld, + lm1_v => sp_L2_LM(1).ta_vld, + lm2_v => sp_L2_LM(2).ta_vld, + lm3_v => sp_L2_LM(3).ta_vld, + lm4_v => sp_L2_LM(4).ta_vld, + lm5_v => sp_L2_LM(5).ta_vld, + lm6_v => sp_L2_LM(6).ta_vld, + lm7_v => sp_L2_LM(7).ta_vld, + + is1_ad => fdec_fdep_is1_s1, + + is2_ad => sp_L2(IS2).ta, + rf0_ad => sp_L2(RF0).ta, + rf1_ad => sp_L2(RF1).ta, + ex1_ad => sp_L2(EX1).ta, + ex2_ad => sp_L2(EX2).ta, + lm0_ad => sp_L2_LM(0).ta, + lm1_ad => sp_L2_LM(1).ta, + lm2_ad => sp_L2_LM(2).ta, + lm3_ad => sp_L2_LM(3).ta, + lm4_ad => sp_L2_LM(4).ta, + lm5_ad => sp_L2_LM(5).ta, + lm6_ad => sp_L2_LM(6).ta, + lm7_ad => sp_L2_LM(7).ta, + + ad_hit_b => RAW_s1_hit_b +); + + +raw_s2_cmp: entity work.iuq_fxu_dep_cmp(iuq_fxu_dep_cmp) +port map ( + is1_v => fdec_fdep_is1_s2_vld, + + is2_v => sp_L2(IS2).ta_vld, + rf0_v => sp_L2(RF0).ta_vld, + rf1_v => sp_L2(RF1).ta_vld, + ex1_v => sp_L2(EX1).ta_vld, + ex2_v => sp_L2(EX2).ta_vld, + lm0_v => sp_L2_LM(0).ta_vld, + lm1_v => sp_L2_LM(1).ta_vld, + lm2_v => sp_L2_LM(2).ta_vld, + lm3_v => sp_L2_LM(3).ta_vld, + lm4_v => sp_L2_LM(4).ta_vld, + lm5_v => sp_L2_LM(5).ta_vld, + lm6_v => sp_L2_LM(6).ta_vld, + lm7_v => sp_L2_LM(7).ta_vld, + + is1_ad => fdec_fdep_is1_s2, + + is2_ad => sp_L2(IS2).ta, + rf0_ad => sp_L2(RF0).ta, + rf1_ad => sp_L2(RF1).ta, + ex1_ad => sp_L2(EX1).ta, + ex2_ad => sp_L2(EX2).ta, + lm0_ad => sp_L2_LM(0).ta, + lm1_ad => sp_L2_LM(1).ta, + lm2_ad => sp_L2_LM(2).ta, + lm3_ad => sp_L2_LM(3).ta, + lm4_ad => sp_L2_LM(4).ta, + lm5_ad => sp_L2_LM(5).ta, + lm6_ad => sp_L2_LM(6).ta, + lm7_ad => sp_L2_LM(7).ta, + + ad_hit_b => RAW_s2_hit_b +); + + +raw_s3_cmp: entity work.iuq_fxu_dep_cmp(iuq_fxu_dep_cmp) +port map ( + is1_v => fdec_fdep_is1_s3_vld, + + is2_v => sp_L2(IS2).ta_vld, + rf0_v => sp_L2(RF0).ta_vld, + rf1_v => sp_L2(RF1).ta_vld, + ex1_v => sp_L2(EX1).ta_vld, + ex2_v => sp_L2(EX2).ta_vld, + lm0_v => sp_L2_LM(0).ta_vld, + lm1_v => sp_L2_LM(1).ta_vld, + lm2_v => sp_L2_LM(2).ta_vld, + lm3_v => sp_L2_LM(3).ta_vld, + lm4_v => sp_L2_LM(4).ta_vld, + lm5_v => sp_L2_LM(5).ta_vld, + lm6_v => sp_L2_LM(6).ta_vld, + lm7_v => sp_L2_LM(7).ta_vld, + + is1_ad => fdec_fdep_is1_s3, + + is2_ad => sp_L2(IS2).ta, + rf0_ad => sp_L2(RF0).ta, + rf1_ad => sp_L2(RF1).ta, + ex1_ad => sp_L2(EX1).ta, + ex2_ad => sp_L2(EX2).ta, + lm0_ad => sp_L2_LM(0).ta, + lm1_ad => sp_L2_LM(1).ta, + lm2_ad => sp_L2_LM(2).ta, + lm3_ad => sp_L2_LM(3).ta, + lm4_ad => sp_L2_LM(4).ta, + lm5_ad => sp_L2_LM(5).ta, + lm6_ad => sp_L2_LM(6).ta, + lm7_ad => sp_L2_LM(7).ta, + + ad_hit_b => RAW_s3_hit_b +); +raw_dep_nand3: RAW_dep_hit <= not(RAW_s1_hit_b and RAW_s2_hit_b and RAW_s3_hit_b); +lr_dep_hit <= (sp_L2(IS2).i_vld and fdec_fdep_is1_UsesLR and sp_L2(IS2).UpdatesLR) or + (sp_L2(RF0).i_vld and fdec_fdep_is1_UsesLR and sp_L2(RF0).UpdatesLR) or + (sp_L2(RF1).i_vld and fdec_fdep_is1_UsesLR and sp_L2(RF1).UpdatesLR) or + (sp_L2(EX1).i_vld and fdec_fdep_is1_UsesLR and sp_L2(EX1).UpdatesLR) or + (sp_L2(EX2).i_vld and fdec_fdep_is1_UsesLR and sp_L2(EX2).UpdatesLR); +cr_dep_hit <= (sp_L2(IS2).i_vld and fdec_fdep_is1_UsesCR and sp_L2(IS2).UpdatesCR) or + (sp_L2(RF0).i_vld and fdec_fdep_is1_UsesCR and sp_L2(RF0).UpdatesCR) or + (sp_L2(RF1).i_vld and fdec_fdep_is1_UsesCR and sp_L2(RF1).UpdatesCR) or + (sp_L2(EX1).i_vld and fdec_fdep_is1_UsesCR and sp_L2(EX1).UpdatesCR) or + (sp_L2(EX2).i_vld and fdec_fdep_is1_UsesCR and sp_L2(EX2).UpdatesCR); +ctr_dep_hit <= (sp_L2(IS2).i_vld and fdec_fdep_is1_UsesCTR and sp_L2(IS2).UpdatesCTR) or + (sp_L2(RF0).i_vld and fdec_fdep_is1_UsesCTR and sp_L2(RF0).UpdatesCTR) or + (sp_L2(RF1).i_vld and fdec_fdep_is1_UsesCTR and sp_L2(RF1).UpdatesCTR) or + (sp_L2(EX1).i_vld and fdec_fdep_is1_UsesCTR and sp_L2(EX1).UpdatesCTR) or + (sp_L2(EX2).i_vld and fdec_fdep_is1_UsesCTR and sp_L2(EX2).UpdatesCTR); +xer_dep_hit <= (sp_L2(IS2).i_vld and fdec_fdep_is1_UsesXER and sp_L2(IS2).UpdatesXER) or + (sp_L2(RF0).i_vld and fdec_fdep_is1_UsesXER and sp_L2(RF0).UpdatesXER) or + (sp_L2(RF1).i_vld and fdec_fdep_is1_UsesXER and sp_L2(RF1).UpdatesXER) or + (sp_L2(EX1).i_vld and fdec_fdep_is1_UsesXER and sp_L2(EX1).UpdatesXER) or + (sp_L2(EX2).i_vld and fdec_fdep_is1_UsesXER and sp_L2(EX2).UpdatesXER); +msr_dep_hit <= (sp_L2(IS2).i_vld and fdec_fdep_is1_UsesMSR and sp_L2(IS2).UpdatesMSR) or + (sp_L2(RF0).i_vld and fdec_fdep_is1_UsesMSR and sp_L2(RF0).UpdatesMSR) or + (sp_L2(RF1).i_vld and fdec_fdep_is1_UsesMSR and sp_L2(RF1).UpdatesMSR) or + (sp_L2(EX1).i_vld and fdec_fdep_is1_UsesMSR and sp_L2(EX1).UpdatesMSR) or + (sp_L2(EX2).i_vld and fdec_fdep_is1_UsesMSR and sp_L2(EX2).UpdatesMSR); +spr_dep_hit <= (sp_L2(IS2).i_vld and fdec_fdep_is1_UsesSPR and sp_L2(IS2).UpdatesSPR) or + (sp_L2(RF0).i_vld and fdec_fdep_is1_UsesSPR and sp_L2(RF0).UpdatesSPR) or + (sp_L2(RF1).i_vld and fdec_fdep_is1_UsesSPR and sp_L2(RF1).UpdatesSPR) or + (sp_L2(EX1).i_vld and fdec_fdep_is1_UsesSPR and sp_L2(EX1).UpdatesSPR) or + (sp_L2(EX2).i_vld and fdec_fdep_is1_UsesSPR and sp_L2(EX2).UpdatesSPR); +br_sprs_dep_hit <= lr_dep_hit or cr_dep_hit or ctr_dep_hit or xer_dep_hit or msr_dep_hit or spr_dep_hit; + + +waw_cmp: entity work.iuq_fxu_dep_cmp(iuq_fxu_dep_cmp) +port map ( + is1_v => fdec_fdep_is1_ld_vld, + + is2_v => tidn, + rf0_v => tidn, + rf1_v => tidn, + ex1_v => tidn, + ex2_v => tidn, + lm0_v => sp_L2_LM(0).ta_vld, + lm1_v => sp_L2_LM(1).ta_vld, + lm2_v => sp_L2_LM(2).ta_vld, + lm3_v => sp_L2_LM(3).ta_vld, + lm4_v => sp_L2_LM(4).ta_vld, + lm5_v => sp_L2_LM(5).ta_vld, + lm6_v => sp_L2_LM(6).ta_vld, + lm7_v => sp_L2_LM(7).ta_vld, + + is1_ad => fdec_fdep_is1_ta, + + is2_ad => sp_L2(IS2).ta, + rf0_ad => sp_L2(RF0).ta, + rf1_ad => sp_L2(RF1).ta, + ex1_ad => sp_L2(EX1).ta, + ex2_ad => sp_L2(EX2).ta, + lm0_ad => sp_L2_LM(0).ta, + lm1_ad => sp_L2_LM(1).ta, + lm2_ad => sp_L2_LM(2).ta, + lm3_ad => sp_L2_LM(3).ta, + lm4_ad => sp_L2_LM(4).ta, + lm5_ad => sp_L2_LM(5).ta, + lm6_ad => sp_L2_LM(6).ta, + lm7_ad => sp_L2_LM(7).ta, + + ad_hit_b => WAW_LMQ_dep_hit_b +); +WAW_LMQ_dep_hit <= not WAW_LMQ_dep_hit_b; +single_instr_mode_d <= xu_iu_single_instr_mode; +single_instr_dep_hit <= ((shadow_pipe_vld or au_iu_is2_axubusy) and single_instr_mode_l2); +dep_hit <= (not fdec_fdep_is1_force_ram and (RAW_dep_hit or WAW_LMQ_dep_hit or sync_dep_hit or single_instr_dep_hit or br_sprs_dep_hit or barrier_in_progress)) or au_iu_is1_dep_hit or internal_is2_stall; +dep_hit_no_stall <= (not fdec_fdep_is1_force_ram and (RAW_dep_hit or WAW_LMQ_dep_hit or sync_dep_hit or single_instr_dep_hit or br_sprs_dep_hit or barrier_in_progress)) or au_iu_is1_dep_hit; +is1_force_ram_b <= not fdec_fdep_is1_force_ram; +is1_valid <= fdec_fdep_is1_vld or i_afd_is1_instr_v; +is1_dep0_nor2: is1_dep0_b <= not (RAW_dep_hit or br_sprs_dep_hit); +is1_dep1_nor3: is1_dep1_b <= not (sync_dep_hit or single_instr_dep_hit or barrier_in_progress); +is1_dep_nand3: is1_dep <= not (WAW_LMQ_dep_hit_b and is1_dep0_b and is1_dep1_b); +is1_stall_nand2: is1_stall_b <= not (is1_dep and fdec_fdep_is1_vld and is1_force_ram_b); +is2_stall_nand2: is2_stall_b <= not (internal_is2_stall and is1_valid); +fxu_stall_nand3: iu_au_is1_stall <= not (au_iu_is1_dep_hit_b and is1_stall_b and is2_stall_b); +buf_stall_nand3: fdep_fdec_buff_stall <= not (au_iu_is1_dep_hit_b and is1_stall_b and is2_stall_b); +fxu_dep0_nor2: fxu_dep0_b <= not (RAW_dep_hit or br_sprs_dep_hit); +fxu_dep1_nor3: fxu_dep1_b <= not (sync_dep_hit or single_instr_dep_hit or barrier_in_progress); +fxu_dep_nand3: fxu_dep_hit <= not (WAW_LMQ_dep_hit_b and fxu_dep0_b and fxu_dep1_b); +fxu_dep_nand2: fxu_dep_hit_b <= not (fxu_dep_hit and is1_force_ram_b); +xu_dep_hit <= not fxu_dep_hit_b; +fdep_fdec_weak_stall <= (sync_dep_hit or single_instr_dep_hit or barrier_in_progress) and fdec_fdep_is1_vld and is1_force_ram_b; +loadmiss_qentry <= gate_and(not xu_iu_ex5_flush and xu_iu_loadmiss_vld and xu_iu_loadmiss_target_type, xu_iu_loadmiss_qentry); +loadmiss_target <= gate_and(not xu_iu_ex5_flush and xu_iu_loadmiss_vld and xu_iu_loadmiss_target_type, xu_iu_loadmiss_target); +loadmiss_complete <= gate_and( xu_iu_complete_vld and xu_iu_complete_target_type, xu_iu_complete_qentry); +shadow_pipe_vld <= sp_L2(IS2).i_nobyp_vld or + sp_L2(RF0).i_nobyp_vld or + sp_L2(RF1).i_nobyp_vld or + sp_L2(EX1).i_nobyp_vld or + sp_L2(EX2).i_nobyp_vld or + sp_EX3_i_nobyp_vld_L2 or + sp_EX4_i_nobyp_vld_L2 or + sp_EX5_i_nobyp_vld_L2 or + or_reduce(lm_shadow_pipe_vld); +lm_shadow_pipe_vld_g: for i in 0 to lmq_entries-1 generate +lm_shadow_pipe_vld(i) <= sp_L2_LM(i).ta_vld; +end generate; + + + +sp_d_proc : process( +xu_iu_is2_flush, +xu_iu_rf0_flush, +xu_iu_rf1_flush, +xu_iu_ex1_flush, +xu_iu_ex2_flush, +xu_iu_ex3_flush, +xu_iu_ex4_flush, +internal_is2_stall, +sp_L2(IS2).i_nobyp_vld, sp_L2(IS2).i_vld, sp_L2(IS2).ta_vld, +sp_L2(IS2).ta, sp_L2(IS2).UpdatesLR, sp_L2(IS2).UpdatesCR, sp_L2(IS2).UPdatesCTR, +sp_L2(IS2).UpdatesXER, sp_L2(IS2).UpdatesMSR, sp_L2(IS2).UPdatesSPR, sp_L2(IS2).complete, sp_L2(IS2).barrier, +sp_L2(RF0).i_nobyp_vld, sp_L2(RF0).i_vld, sp_L2(RF0).ta_vld, +sp_L2(RF0).ta, sp_L2(RF0).UpdatesLR, sp_L2(RF0).UpdatesCR, sp_L2(RF0).UPdatesCTR, +sp_L2(RF0).UpdatesXER, sp_L2(RF0).UpdatesMSR, sp_L2(RF0).UPdatesSPR, sp_L2(RF0).complete, sp_L2(RF0).barrier, +sp_L2(RF1).i_nobyp_vld, sp_L2(RF1).i_vld, sp_L2(RF1).ta_vld, +sp_L2(RF1).ta, sp_L2(RF1).UpdatesLR, sp_L2(RF1).UpdatesCR, sp_L2(RF1).UPdatesCTR, +sp_L2(RF1).UpdatesXER, sp_L2(RF1).UpdatesMSR, sp_L2(RF1).UPdatesSPR, sp_L2(RF1).complete, sp_L2(RF1).barrier, +sp_L2(EX1).i_nobyp_vld, sp_L2(EX1).i_vld, sp_L2(EX1).ta_vld, +sp_L2(EX1).ta, sp_L2(EX1).UpdatesLR, sp_L2(EX1).UpdatesCR, sp_L2(EX1).UPdatesCTR, +sp_L2(EX1).UpdatesXER, sp_L2(EX1).UpdatesMSR, sp_L2(EX1).UPdatesSPR, sp_L2(EX1).complete, sp_L2(EX1).barrier, + +sp_L2(EX2).i_nobyp_vld, sp_L2(EX2).barrier, + +sp_EX3_i_nobyp_vld_l2, +sp_EX4_i_nobyp_vld_l2, +sp_EX3_barrier_l2, +sp_EX4_barrier_l2, +sp_LM_l2, + +fdec_fdep_is1_vld, +fdec_fdep_is1_ta_vld, + +fdec_fdep_is1_ta, +fdec_fdep_is1_UpdatesLR, +fdec_fdep_is1_UpdatesCR, +fdec_fdep_is1_UpdatesCTR, +fdec_fdep_is1_UpdatesXER, +fdec_fdep_is1_UpdatesMSR, +fdec_fdep_is1_UpdatesSPR, +fdec_fdep_is1_complete, +xu_iu_is1_flush, +loadmiss_qentry, +loadmiss_target, +loadmiss_complete, +is2_instr_is_barrier, +dep_hit_no_stall +) begin + + + +sp_d(IS2).i_nobyp_vld <= fdec_fdep_is1_vld and not dep_hit_no_stall; +sp_d(IS2).i_vld <= fdec_fdep_is1_vld and not dep_hit_no_stall and not fdec_fdep_is1_complete(0); +sp_d(IS2).ta_vld <= fdec_fdep_is1_vld and fdec_fdep_is1_ta_vld and not dep_hit_no_stall and not fdec_fdep_is1_complete(0); +sp_d(IS2).ta <= fdec_fdep_is1_ta; +sp_d(IS2).UpdatesLR <= fdec_fdep_is1_UpdatesLR; +sp_d(IS2).UpdatesCR <= fdec_fdep_is1_UpdatesCR; +sp_d(IS2).UpdatesCTR <= fdec_fdep_is1_UpdatesCTR; +sp_d(IS2).UpdatesXER <= fdec_fdep_is1_UpdatesXER; +sp_d(IS2).UpdatesMSR <= fdec_fdep_is1_UpdatesMSR; +sp_d(IS2).UpdatesSPR <= fdec_fdep_is1_UpdatesSPR; +sp_d(IS2).complete <= fdec_fdep_is1_complete; +sp_d(IS2).barrier <= '0'; +if ib(internal_is2_stall) then +sp_d(IS2) <= sp_L2(IS2); +end if; +if ib(xu_iu_is1_flush) then +sp_d(IS2).i_nobyp_vld <= '0'; +sp_d(IS2).i_vld <= '0'; +sp_d(IS2).ta_vld <= '0'; +end if; +sp_d(RF0) <= sp_L2(IS2); +sp_d(RF0).i_vld <=sp_L2(IS2).i_vld and not sp_L2(IS2).complete(1); +sp_d(RF0).ta_vld <=sp_L2(IS2).ta_vld and not sp_L2(IS2).complete(1); +sp_d(RF0).barrier <=is2_instr_is_barrier; +if ib(xu_iu_is2_flush) or ib(internal_is2_stall) then +sp_d(RF0).ta_vld <= '0'; +sp_d(RF0).i_nobyp_vld <= '0'; +sp_d(RF0).i_vld <= '0'; +sp_d(RF0).barrier <= '0'; +end if; +sp_d(RF1) <= sp_L2(RF0); +sp_d(RF1).i_vld <=sp_L2(RF0).i_vld and not sp_L2(RF0).complete(2); +sp_d(RF1).ta_vld <=sp_L2(RF0).ta_vld and not sp_L2(RF0).complete(2); +if ib(xu_iu_rf0_flush) then +sp_d(RF1).ta_vld <= '0'; +sp_d(RF1).i_nobyp_vld <= '0'; +sp_d(RF1).i_vld <= '0'; +sp_d(RF1).barrier <= '0'; +end if; +sp_d(EX1) <= sp_L2(RF1); +sp_d(EX1).i_vld <=sp_L2(RF1).i_vld and not sp_L2(RF1).complete(3); +sp_d(EX1).ta_vld <=sp_L2(RF1).ta_vld and not sp_L2(RF1).complete(3); +if ib(xu_iu_rf1_flush) then +sp_d(EX1).ta_vld <= '0'; +sp_d(EX1).i_nobyp_vld <= '0'; +sp_d(EX1).i_vld <= '0'; +sp_d(EX1).barrier <= '0'; +end if; +sp_d(EX2) <= sp_L2(EX1); +sp_d(EX2).i_vld <=sp_L2(EX1).i_vld and not sp_L2(EX1).complete(4); +sp_d(EX2).ta_vld <=sp_L2(EX1).ta_vld and not sp_L2(EX1).complete(4); +if ib(xu_iu_ex1_flush) then +sp_d(EX2).ta_vld <= '0'; +sp_d(EX2).i_nobyp_vld <= '0'; +sp_d(EX2).i_vld <= '0'; +sp_d(EX2).barrier <= '0'; +end if; +sp_EX3_i_nobyp_vld_d <= sp_L2(EX2).i_nobyp_vld; +sp_EX3_barrier_d <= sp_L2(EX2).barrier; +if ib(xu_iu_ex2_flush) then +sp_EX3_i_nobyp_vld_d <= '0'; +sp_EX3_barrier_d <= '0'; +end if; +sp_EX4_i_nobyp_vld_d <= sp_EX3_i_nobyp_vld_l2; +sp_EX4_barrier_d <= sp_EX3_barrier_l2; +if ib(xu_iu_ex3_flush) then +sp_EX4_i_nobyp_vld_d <= '0'; +sp_EX4_barrier_d <= '0'; +end if; +sp_EX5_i_nobyp_vld_d <= sp_EX4_i_nobyp_vld_l2; +sp_EX5_barrier_d <= sp_EX4_barrier_l2; +if ib(xu_iu_ex4_flush) then +sp_EX5_i_nobyp_vld_d <= '0'; +sp_EX5_barrier_d <= '0'; +end if; +lm_loop: for i in 0 to lmq_entries-1 loop +sp_d_LM(i).ta_vld <= sp_LM_l2(0+7*i); +sp_d_LM(i).ta <= sp_LM_l2(1+7*i to 6+7*i); +if ib(loadmiss_qentry(i)) then +sp_d_LM(i).ta_vld <='1'; +sp_d_LM(i).ta <= loadmiss_target; +elsif ib(loadmiss_complete(i)) then +sp_d_LM(i).ta_vld <= '0'; +end if; +end loop; + + +end process sp_d_proc; +unused(0 TO 4) <= sp_L2(EX2).complete(0 to 4); + +is2_instr_proc : process ( +fdec_fdep_is1_vld, + +fdec_fdep_is1_instr, +fdec_fdep_is1_ta_vld, +fdec_fdep_is1_ta, +fdec_fdep_is1_s1_vld, +fdec_fdep_is1_s1, +fdec_fdep_is1_s2_vld, +fdec_fdep_is1_s2, +fdec_fdep_is1_s3_vld, +fdec_fdep_is1_s3, +fdec_fdep_is1_pred_update, +fdec_fdep_is1_pred_taken_cnt, +fdec_fdep_is1_gshare, + +fdec_fdep_is1_hole_delay, + +fdec_fdep_is1_to_ucode, +fdec_fdep_is1_is_ucode, +fdec_fdep_is1_ifar, +fdec_fdep_is1_error, +is1_is_barrier, +is1_is_slowspr, +is2_vld_l2, +is2_instr_l2, +is2_ta_vld_l2, +is2_ta_l2, +is2_s1_vld_l2, +is2_s1_l2, +is2_s2_vld_l2, +is2_s2_l2, +is2_s3_vld_l2, +is2_s3_l2, +is2_is_barrier_l2, +is2_is_slowspr_l2, +is2_pred_update_l2, +is2_pred_taken_cnt_l2, +is2_gshare_l2, + +is2_hole_delay_l2, + +is2_to_ucode_l2, +is2_is_ucode_l2, +is2_error_l2, +is2_ifar_l2, +is2_axu_ld_or_st_l2, +is2_axu_store_l2, +is2_axu_ldst_indexed_l2, +is2_axu_ldst_tag_l2, +is2_axu_ldst_size_l2, +is2_axu_ldst_update_l2, +is2_axu_ldst_extpid_l2, +is2_axu_ldst_forcealign_l2, +is2_axu_ldst_forceexcept_l2, +is2_axu_mftgpr_l2, +is2_axu_mffgpr_l2, +is2_axu_movedp_l2, +is2_axu_instr_type_l2, +is2_match_l2, +is2_2ucode_l2, +is2_2ucode_type_l2, +dep_hit_no_stall, +xu_iu_is1_flush, +internal_is2_stall, +fdec_fdep_is1_axu_ld_or_st, +fdec_fdep_is1_axu_store, +fdec_fdep_is1_axu_ldst_indexed, +fdec_fdep_is1_axu_ldst_tag, +fdec_fdep_is1_axu_ldst_size, +fdec_fdep_is1_axu_ldst_update, +fdec_fdep_is1_axu_ldst_extpid, +fdec_fdep_is1_axu_ldst_forcealign, +fdec_fdep_is1_axu_ldst_forceexcept, +fdec_fdep_is1_axu_mftgpr, +fdec_fdep_is1_axu_mffgpr, +fdec_fdep_is1_axu_movedp, +fdec_fdep_is1_axu_instr_type, +fdec_fdep_is1_match, +fdec_fdep_is1_2ucode, +fdec_fdep_is1_2ucode_type +) begin + + is2_vld_d <= fdec_fdep_is1_vld and not dep_hit_no_stall; +is2_instr_d <= fdec_fdep_is1_instr; +is2_ta_vld_d <= fdec_fdep_is1_ta_vld; +is2_ta_d <= fdec_fdep_is1_ta; +is2_s1_vld_d <= fdec_fdep_is1_s1_vld; +is2_s1_d <= fdec_fdep_is1_s1; +is2_s2_vld_d <= fdec_fdep_is1_s2_vld; +is2_s2_d <= fdec_fdep_is1_s2; +is2_s3_vld_d <= fdec_fdep_is1_s3_vld; +is2_s3_d <= fdec_fdep_is1_s3; +is2_is_barrier_d <= is1_is_barrier; +is2_is_slowspr_d <= is1_is_slowspr; +is2_pred_update_d <= fdec_fdep_is1_pred_update; +is2_pred_taken_cnt_d <= fdec_fdep_is1_pred_taken_cnt; +is2_gshare_d <= fdec_fdep_is1_gshare; +is2_hole_delay_d <= fdec_fdep_is1_hole_delay; +is2_to_ucode_d <= fdec_fdep_is1_to_ucode; +is2_is_ucode_d <= fdec_fdep_is1_is_ucode; +is2_ifar_d <= fdec_fdep_is1_ifar; +is2_error_d <= fdec_fdep_is1_error; +is2_axu_ld_or_st_d <= fdec_fdep_is1_axu_ld_or_st; +is2_axu_store_d <= fdec_fdep_is1_axu_store; +is2_axu_ldst_indexed_d <= fdec_fdep_is1_axu_ldst_indexed; +is2_axu_ldst_tag_d <= fdec_fdep_is1_axu_ldst_tag; +is2_axu_ldst_size_d <= fdec_fdep_is1_axu_ldst_size; +is2_axu_ldst_update_d <= fdec_fdep_is1_axu_ldst_update; +is2_axu_ldst_extpid_d <= fdec_fdep_is1_axu_ldst_extpid; +is2_axu_ldst_forcealign_d <= fdec_fdep_is1_axu_ldst_forcealign; +is2_axu_ldst_forceexcept_d <= fdec_fdep_is1_axu_ldst_forceexcept; +is2_axu_mftgpr_d <= fdec_fdep_is1_axu_mftgpr; +is2_axu_mffgpr_d <= fdec_fdep_is1_axu_mffgpr; +is2_axu_movedp_d <= fdec_fdep_is1_axu_movedp; +is2_axu_instr_type_d <= fdec_fdep_is1_axu_instr_type; +is2_match_d <= fdec_fdep_is1_match; +is2_2ucode_d <= fdec_fdep_is1_2ucode; +is2_2ucode_type_d <= fdec_fdep_is1_2ucode_type; +if (internal_is2_stall = '1') then +is2_vld_d <= is2_vld_l2; +is2_instr_d <= is2_instr_l2; +is2_ta_vld_d <= is2_ta_vld_l2; +is2_ta_d <= is2_ta_l2; +is2_s1_vld_d <= is2_s1_vld_l2; +is2_s1_d <= is2_s1_l2; +is2_s2_vld_d <= is2_s2_vld_l2; +is2_s2_d <= is2_s2_l2; +is2_s3_vld_d <= is2_s3_vld_l2; +is2_s3_d <= is2_s3_l2; +is2_is_barrier_d <= is2_is_barrier_l2; +is2_is_slowspr_d <= is2_is_slowspr_l2; +is2_pred_update_d <= is2_pred_update_l2; +is2_pred_taken_cnt_d <= is2_pred_taken_cnt_l2; +is2_gshare_d <= is2_gshare_l2; +is2_hole_delay_d <= is2_hole_delay_l2; +is2_to_ucode_d <= is2_to_ucode_l2; +is2_is_ucode_d <= is2_is_ucode_l2; +is2_ifar_d <= is2_ifar_l2; +is2_error_d <= is2_error_l2; +is2_axu_ld_or_st_d <= is2_axu_ld_or_st_l2; +is2_axu_store_d <= is2_axu_store_l2; +is2_axu_ldst_indexed_d <= is2_axu_ldst_indexed_l2; +is2_axu_ldst_tag_d <= is2_axu_ldst_tag_l2; +is2_axu_ldst_size_d <= is2_axu_ldst_size_l2; +is2_axu_ldst_update_d <= is2_axu_ldst_update_l2; +is2_axu_ldst_extpid_d <= is2_axu_ldst_extpid_l2; +is2_axu_ldst_forcealign_d <= is2_axu_ldst_forcealign_l2; +is2_axu_ldst_forceexcept_d <= is2_axu_ldst_forceexcept_l2; +is2_axu_mftgpr_d <= is2_axu_mftgpr_l2; +is2_axu_mffgpr_d <= is2_axu_mffgpr_l2; +is2_axu_movedp_d <= is2_axu_movedp_l2; +is2_axu_instr_type_d <= is2_axu_instr_type_l2; +is2_match_d <= is2_match_l2; +is2_2ucode_d <= is2_2ucode_l2; +is2_2ucode_type_d <= is2_2ucode_type_l2; +end if; +if (xu_iu_is1_flush = '1') then +is2_vld_d <= '0'; +end if; + + +end process is2_instr_proc; +mult_hole_barrier_d(0) <= not xu_iu_is2_flush and ( mult_hole_barrier_L2(1)); +mult_hole_barrier_d(1) <= not xu_iu_is2_flush and ( mult_hole_barrier_L2(2)); +mult_hole_barrier_d(2) <= not xu_iu_is2_flush and ( mult_hole_barrier_L2(3)); +mult_hole_barrier_d(3) <= not xu_iu_is2_flush and ((is2_vld_l2 and is2_hole_delay_L2(0)) or mult_hole_barrier_L2(4)); +mult_hole_barrier_d(4) <= not xu_iu_is2_flush and ((is2_vld_l2 and is2_hole_delay_L2(1)) or mult_hole_barrier_L2(5)); +mult_hole_barrier_d(5) <= not xu_iu_is2_flush and ((is2_vld_l2 and is2_hole_delay_L2(2)) ); +is2_mult_hole_barrier <= (is2_vld_l2 and or_reduce(is2_hole_delay_L2(0 to 2))) or or_reduce(mult_hole_barrier_L2(0 to 5)); +mult_hole_barrier_act <= is2_mult_hole_barrier; +is1_is_slowspr <= is_slowspr and (isMTSPR or isMFSPR); +is1_is_barrier <= is_bar or is1_is_slowspr or fdec_fdep_is1_to_ucode; +is2_instr_is_barrier <= is2_vld_l2 and is2_is_barrier_L2; +MQQ1:BARRIER_PT(1) <= + Eq(( FDEC_FDEP_IS1_INSTR(0) & FDEC_FDEP_IS1_INSTR(1) & + FDEC_FDEP_IS1_INSTR(2) & FDEC_FDEP_IS1_INSTR(3) & + FDEC_FDEP_IS1_INSTR(4) & FDEC_FDEP_IS1_INSTR(5) & + FDEC_FDEP_IS1_INSTR(21) & FDEC_FDEP_IS1_INSTR(22) & + FDEC_FDEP_IS1_INSTR(24) & FDEC_FDEP_IS1_INSTR(25) & + FDEC_FDEP_IS1_INSTR(26) & FDEC_FDEP_IS1_INSTR(27) & + FDEC_FDEP_IS1_INSTR(29) & FDEC_FDEP_IS1_INSTR(30) & + FDEC_FDEP_IS1_INSTR(31) ) , STD_ULOGIC_VECTOR'("011111111010101")); +MQQ2:BARRIER_PT(2) <= + Eq(( FDEC_FDEP_IS1_INSTR(0) & FDEC_FDEP_IS1_INSTR(1) & + FDEC_FDEP_IS1_INSTR(2) & FDEC_FDEP_IS1_INSTR(3) & + FDEC_FDEP_IS1_INSTR(4) & FDEC_FDEP_IS1_INSTR(5) & + FDEC_FDEP_IS1_INSTR(21) & FDEC_FDEP_IS1_INSTR(22) & + FDEC_FDEP_IS1_INSTR(23) & FDEC_FDEP_IS1_INSTR(24) & + FDEC_FDEP_IS1_INSTR(25) & FDEC_FDEP_IS1_INSTR(26) & + FDEC_FDEP_IS1_INSTR(27) & FDEC_FDEP_IS1_INSTR(29) & + FDEC_FDEP_IS1_INSTR(30) ) , STD_ULOGIC_VECTOR'("011111111101010")); +MQQ3:BARRIER_PT(3) <= + Eq(( FDEC_FDEP_IS1_INSTR(0) & FDEC_FDEP_IS1_INSTR(1) & + FDEC_FDEP_IS1_INSTR(2) & FDEC_FDEP_IS1_INSTR(3) & + FDEC_FDEP_IS1_INSTR(4) & FDEC_FDEP_IS1_INSTR(5) & + FDEC_FDEP_IS1_INSTR(21) & FDEC_FDEP_IS1_INSTR(22) & + FDEC_FDEP_IS1_INSTR(23) & FDEC_FDEP_IS1_INSTR(25) & + FDEC_FDEP_IS1_INSTR(26) & FDEC_FDEP_IS1_INSTR(27) & + FDEC_FDEP_IS1_INSTR(28) & FDEC_FDEP_IS1_INSTR(29) & + FDEC_FDEP_IS1_INSTR(30) ) , STD_ULOGIC_VECTOR'("010011000100110")); +MQQ4:BARRIER_PT(4) <= + Eq(( CORE64 & FDEC_FDEP_IS1_INSTR(0) & + FDEC_FDEP_IS1_INSTR(1) & FDEC_FDEP_IS1_INSTR(2) & + FDEC_FDEP_IS1_INSTR(3) & FDEC_FDEP_IS1_INSTR(4) & + FDEC_FDEP_IS1_INSTR(5) & FDEC_FDEP_IS1_INSTR(21) & + FDEC_FDEP_IS1_INSTR(22) & FDEC_FDEP_IS1_INSTR(23) & + FDEC_FDEP_IS1_INSTR(25) & FDEC_FDEP_IS1_INSTR(26) & + FDEC_FDEP_IS1_INSTR(27) & FDEC_FDEP_IS1_INSTR(28) & + FDEC_FDEP_IS1_INSTR(29) & FDEC_FDEP_IS1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("1011111000010100")); +MQQ5:BARRIER_PT(5) <= + Eq(( FDEC_FDEP_IS1_INSTR(0) & FDEC_FDEP_IS1_INSTR(1) & + FDEC_FDEP_IS1_INSTR(2) & FDEC_FDEP_IS1_INSTR(3) & + FDEC_FDEP_IS1_INSTR(4) & FDEC_FDEP_IS1_INSTR(5) & + FDEC_FDEP_IS1_INSTR(21) & FDEC_FDEP_IS1_INSTR(22) & + FDEC_FDEP_IS1_INSTR(23) & FDEC_FDEP_IS1_INSTR(24) & + FDEC_FDEP_IS1_INSTR(25) & FDEC_FDEP_IS1_INSTR(26) & + FDEC_FDEP_IS1_INSTR(27) & FDEC_FDEP_IS1_INSTR(28) & + FDEC_FDEP_IS1_INSTR(29) ) , STD_ULOGIC_VECTOR'("010011000011001")); +MQQ6:BARRIER_PT(6) <= + Eq(( FDEC_FDEP_IS1_INSTR(0) & FDEC_FDEP_IS1_INSTR(1) & + FDEC_FDEP_IS1_INSTR(2) & FDEC_FDEP_IS1_INSTR(3) & + FDEC_FDEP_IS1_INSTR(4) & FDEC_FDEP_IS1_INSTR(5) & + FDEC_FDEP_IS1_INSTR(21) & FDEC_FDEP_IS1_INSTR(22) & + FDEC_FDEP_IS1_INSTR(23) & FDEC_FDEP_IS1_INSTR(24) & + FDEC_FDEP_IS1_INSTR(25) & FDEC_FDEP_IS1_INSTR(26) & + FDEC_FDEP_IS1_INSTR(27) & FDEC_FDEP_IS1_INSTR(28) & + FDEC_FDEP_IS1_INSTR(29) & FDEC_FDEP_IS1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("0100110010010110")); +MQQ7:BARRIER_PT(7) <= + Eq(( CORE64 & FDEC_FDEP_IS1_INSTR(0) & + FDEC_FDEP_IS1_INSTR(1) & FDEC_FDEP_IS1_INSTR(2) & + FDEC_FDEP_IS1_INSTR(3) & FDEC_FDEP_IS1_INSTR(4) & + FDEC_FDEP_IS1_INSTR(5) & FDEC_FDEP_IS1_INSTR(21) & + FDEC_FDEP_IS1_INSTR(22) & FDEC_FDEP_IS1_INSTR(23) & + FDEC_FDEP_IS1_INSTR(25) & FDEC_FDEP_IS1_INSTR(26) & + FDEC_FDEP_IS1_INSTR(27) & FDEC_FDEP_IS1_INSTR(28) & + FDEC_FDEP_IS1_INSTR(29) & FDEC_FDEP_IS1_INSTR(30) & + FDEC_FDEP_IS1_INSTR(31) ) , STD_ULOGIC_VECTOR'("10111110010101101")); +MQQ8:BARRIER_PT(8) <= + Eq(( FDEC_FDEP_IS1_INSTR(0) & FDEC_FDEP_IS1_INSTR(1) & + FDEC_FDEP_IS1_INSTR(2) & FDEC_FDEP_IS1_INSTR(3) & + FDEC_FDEP_IS1_INSTR(4) & FDEC_FDEP_IS1_INSTR(5) & + FDEC_FDEP_IS1_INSTR(21) & FDEC_FDEP_IS1_INSTR(22) & + FDEC_FDEP_IS1_INSTR(23) & FDEC_FDEP_IS1_INSTR(24) & + FDEC_FDEP_IS1_INSTR(25) & FDEC_FDEP_IS1_INSTR(26) & + FDEC_FDEP_IS1_INSTR(27) & FDEC_FDEP_IS1_INSTR(28) & + FDEC_FDEP_IS1_INSTR(29) & FDEC_FDEP_IS1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("0111110000010100")); +MQQ9:BARRIER_PT(9) <= + Eq(( FDEC_FDEP_IS1_INSTR(0) & FDEC_FDEP_IS1_INSTR(1) & + FDEC_FDEP_IS1_INSTR(2) & FDEC_FDEP_IS1_INSTR(3) & + FDEC_FDEP_IS1_INSTR(4) & FDEC_FDEP_IS1_INSTR(5) & + FDEC_FDEP_IS1_INSTR(21) & FDEC_FDEP_IS1_INSTR(23) & + FDEC_FDEP_IS1_INSTR(24) & FDEC_FDEP_IS1_INSTR(25) & + FDEC_FDEP_IS1_INSTR(26) & FDEC_FDEP_IS1_INSTR(27) & + FDEC_FDEP_IS1_INSTR(28) & FDEC_FDEP_IS1_INSTR(29) & + FDEC_FDEP_IS1_INSTR(30) ) , STD_ULOGIC_VECTOR'("011111101010110")); +MQQ10:BARRIER_PT(10) <= + Eq(( CORE64 & FDEC_FDEP_IS1_INSTR(0) & + FDEC_FDEP_IS1_INSTR(1) & FDEC_FDEP_IS1_INSTR(2) & + FDEC_FDEP_IS1_INSTR(3) & FDEC_FDEP_IS1_INSTR(4) & + FDEC_FDEP_IS1_INSTR(5) & FDEC_FDEP_IS1_INSTR(22) & + FDEC_FDEP_IS1_INSTR(23) & FDEC_FDEP_IS1_INSTR(26) & + FDEC_FDEP_IS1_INSTR(27) & FDEC_FDEP_IS1_INSTR(28) & + FDEC_FDEP_IS1_INSTR(30) ) , STD_ULOGIC_VECTOR'("1011111110101")); +MQQ11:BARRIER_PT(11) <= + Eq(( FDEC_FDEP_IS1_INSTR(0) & FDEC_FDEP_IS1_INSTR(1) & + FDEC_FDEP_IS1_INSTR(2) & FDEC_FDEP_IS1_INSTR(3) & + FDEC_FDEP_IS1_INSTR(4) & FDEC_FDEP_IS1_INSTR(5) & + FDEC_FDEP_IS1_INSTR(21) & FDEC_FDEP_IS1_INSTR(22) & + FDEC_FDEP_IS1_INSTR(23) & FDEC_FDEP_IS1_INSTR(24) & + FDEC_FDEP_IS1_INSTR(25) & FDEC_FDEP_IS1_INSTR(26) & + FDEC_FDEP_IS1_INSTR(27) & FDEC_FDEP_IS1_INSTR(28) & + FDEC_FDEP_IS1_INSTR(29) & FDEC_FDEP_IS1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("0111111000110110")); +MQQ12:BARRIER_PT(12) <= + Eq(( FDEC_FDEP_IS1_INSTR(0) & FDEC_FDEP_IS1_INSTR(1) & + FDEC_FDEP_IS1_INSTR(2) & FDEC_FDEP_IS1_INSTR(3) & + FDEC_FDEP_IS1_INSTR(4) & FDEC_FDEP_IS1_INSTR(5) & + FDEC_FDEP_IS1_INSTR(21) & FDEC_FDEP_IS1_INSTR(23) & + FDEC_FDEP_IS1_INSTR(24) & FDEC_FDEP_IS1_INSTR(25) & + FDEC_FDEP_IS1_INSTR(26) & FDEC_FDEP_IS1_INSTR(27) & + FDEC_FDEP_IS1_INSTR(28) & FDEC_FDEP_IS1_INSTR(29) & + FDEC_FDEP_IS1_INSTR(30) & FDEC_FDEP_IS1_INSTR(31) + ) , STD_ULOGIC_VECTOR'("0111110100101101")); +MQQ13:BARRIER_PT(13) <= + Eq(( FDEC_FDEP_IS1_INSTR(0) & FDEC_FDEP_IS1_INSTR(1) & + FDEC_FDEP_IS1_INSTR(2) & FDEC_FDEP_IS1_INSTR(3) & + FDEC_FDEP_IS1_INSTR(4) & FDEC_FDEP_IS1_INSTR(5) & + FDEC_FDEP_IS1_INSTR(21) & FDEC_FDEP_IS1_INSTR(22) & + FDEC_FDEP_IS1_INSTR(23) & FDEC_FDEP_IS1_INSTR(24) & + FDEC_FDEP_IS1_INSTR(25) & FDEC_FDEP_IS1_INSTR(26) & + FDEC_FDEP_IS1_INSTR(27) & FDEC_FDEP_IS1_INSTR(29) & + FDEC_FDEP_IS1_INSTR(30) & FDEC_FDEP_IS1_INSTR(31) + ) , STD_ULOGIC_VECTOR'("0111111110110101")); +MQQ14:BARRIER_PT(14) <= + Eq(( FDEC_FDEP_IS1_INSTR(0) & FDEC_FDEP_IS1_INSTR(1) & + FDEC_FDEP_IS1_INSTR(2) & FDEC_FDEP_IS1_INSTR(3) & + FDEC_FDEP_IS1_INSTR(4) & FDEC_FDEP_IS1_INSTR(5) & + FDEC_FDEP_IS1_INSTR(21) & FDEC_FDEP_IS1_INSTR(22) & + FDEC_FDEP_IS1_INSTR(24) & FDEC_FDEP_IS1_INSTR(25) & + FDEC_FDEP_IS1_INSTR(26) & FDEC_FDEP_IS1_INSTR(27) & + FDEC_FDEP_IS1_INSTR(28) & FDEC_FDEP_IS1_INSTR(29) & + FDEC_FDEP_IS1_INSTR(30) ) , STD_ULOGIC_VECTOR'("011111000010010")); +MQQ15:BARRIER_PT(15) <= + Eq(( EN_DCR_L2 & FDEC_FDEP_IS1_INSTR(0) & + FDEC_FDEP_IS1_INSTR(1) & FDEC_FDEP_IS1_INSTR(2) & + FDEC_FDEP_IS1_INSTR(3) & FDEC_FDEP_IS1_INSTR(4) & + FDEC_FDEP_IS1_INSTR(5) & FDEC_FDEP_IS1_INSTR(21) & + FDEC_FDEP_IS1_INSTR(22) & FDEC_FDEP_IS1_INSTR(25) & + FDEC_FDEP_IS1_INSTR(26) & FDEC_FDEP_IS1_INSTR(27) & + FDEC_FDEP_IS1_INSTR(28) & FDEC_FDEP_IS1_INSTR(29) & + FDEC_FDEP_IS1_INSTR(30) ) , STD_ULOGIC_VECTOR'("101111101000011")); +MQQ16:BARRIER_PT(16) <= + Eq(( EN_DCR_L2 & FDEC_FDEP_IS1_INSTR(0) & + FDEC_FDEP_IS1_INSTR(1) & FDEC_FDEP_IS1_INSTR(2) & + FDEC_FDEP_IS1_INSTR(3) & FDEC_FDEP_IS1_INSTR(4) & + FDEC_FDEP_IS1_INSTR(5) & FDEC_FDEP_IS1_INSTR(21) & + FDEC_FDEP_IS1_INSTR(22) & FDEC_FDEP_IS1_INSTR(24) & + FDEC_FDEP_IS1_INSTR(26) & FDEC_FDEP_IS1_INSTR(27) & + FDEC_FDEP_IS1_INSTR(28) & FDEC_FDEP_IS1_INSTR(29) & + FDEC_FDEP_IS1_INSTR(30) ) , STD_ULOGIC_VECTOR'("101111101000011")); +MQQ17:BARRIER_PT(17) <= + Eq(( FDEC_FDEP_IS1_INSTR(0) & FDEC_FDEP_IS1_INSTR(1) & + FDEC_FDEP_IS1_INSTR(2) & FDEC_FDEP_IS1_INSTR(3) & + FDEC_FDEP_IS1_INSTR(4) & FDEC_FDEP_IS1_INSTR(5) & + FDEC_FDEP_IS1_INSTR(21) & FDEC_FDEP_IS1_INSTR(22) & + FDEC_FDEP_IS1_INSTR(24) & FDEC_FDEP_IS1_INSTR(25) & + FDEC_FDEP_IS1_INSTR(26) & FDEC_FDEP_IS1_INSTR(27) & + FDEC_FDEP_IS1_INSTR(28) & FDEC_FDEP_IS1_INSTR(29) & + FDEC_FDEP_IS1_INSTR(30) ) , STD_ULOGIC_VECTOR'("011111000110011")); +MQQ18:BARRIER_PT(18) <= + Eq(( FDEC_FDEP_IS1_INSTR(0) & FDEC_FDEP_IS1_INSTR(1) & + FDEC_FDEP_IS1_INSTR(2) & FDEC_FDEP_IS1_INSTR(3) & + FDEC_FDEP_IS1_INSTR(4) & FDEC_FDEP_IS1_INSTR(5) & + FDEC_FDEP_IS1_INSTR(21) & FDEC_FDEP_IS1_INSTR(22) & + FDEC_FDEP_IS1_INSTR(23) & FDEC_FDEP_IS1_INSTR(24) & + FDEC_FDEP_IS1_INSTR(25) & FDEC_FDEP_IS1_INSTR(26) & + FDEC_FDEP_IS1_INSTR(27) & FDEC_FDEP_IS1_INSTR(28) & + FDEC_FDEP_IS1_INSTR(29) & FDEC_FDEP_IS1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("0111110100001110")); +MQQ19:BARRIER_PT(19) <= + Eq(( FDEC_FDEP_IS1_INSTR(0) & FDEC_FDEP_IS1_INSTR(1) & + FDEC_FDEP_IS1_INSTR(2) & FDEC_FDEP_IS1_INSTR(3) & + FDEC_FDEP_IS1_INSTR(4) & FDEC_FDEP_IS1_INSTR(5) & + FDEC_FDEP_IS1_INSTR(22) & FDEC_FDEP_IS1_INSTR(23) & + FDEC_FDEP_IS1_INSTR(26) & FDEC_FDEP_IS1_INSTR(27) & + FDEC_FDEP_IS1_INSTR(28) & FDEC_FDEP_IS1_INSTR(29) & + FDEC_FDEP_IS1_INSTR(30) ) , STD_ULOGIC_VECTOR'("0111111101011")); +MQQ20:BARRIER_PT(20) <= + Eq(( FDEC_FDEP_IS1_INSTR(0) & FDEC_FDEP_IS1_INSTR(1) & + FDEC_FDEP_IS1_INSTR(2) & FDEC_FDEP_IS1_INSTR(3) & + FDEC_FDEP_IS1_INSTR(4) & FDEC_FDEP_IS1_INSTR(5) & + FDEC_FDEP_IS1_INSTR(21) & FDEC_FDEP_IS1_INSTR(22) & + FDEC_FDEP_IS1_INSTR(24) & FDEC_FDEP_IS1_INSTR(25) & + FDEC_FDEP_IS1_INSTR(26) & FDEC_FDEP_IS1_INSTR(27) & + FDEC_FDEP_IS1_INSTR(28) & FDEC_FDEP_IS1_INSTR(29) & + FDEC_FDEP_IS1_INSTR(30) ) , STD_ULOGIC_VECTOR'("011111110010010")); +MQQ21:BARRIER_PT(21) <= + Eq(( FDEC_FDEP_IS1_INSTR(0) & FDEC_FDEP_IS1_INSTR(1) & + FDEC_FDEP_IS1_INSTR(2) & FDEC_FDEP_IS1_INSTR(3) & + FDEC_FDEP_IS1_INSTR(4) & FDEC_FDEP_IS1_INSTR(5) & + FDEC_FDEP_IS1_INSTR(21) & FDEC_FDEP_IS1_INSTR(22) & + FDEC_FDEP_IS1_INSTR(23) & FDEC_FDEP_IS1_INSTR(24) & + FDEC_FDEP_IS1_INSTR(25) & FDEC_FDEP_IS1_INSTR(26) & + FDEC_FDEP_IS1_INSTR(27) & FDEC_FDEP_IS1_INSTR(28) & + FDEC_FDEP_IS1_INSTR(29) & FDEC_FDEP_IS1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("0111111111011111")); +MQQ22:BARRIER_PT(22) <= + Eq(( FDEC_FDEP_IS1_INSTR(0) & FDEC_FDEP_IS1_INSTR(1) & + FDEC_FDEP_IS1_INSTR(2) & FDEC_FDEP_IS1_INSTR(3) & + FDEC_FDEP_IS1_INSTR(4) & FDEC_FDEP_IS1_INSTR(5) & + FDEC_FDEP_IS1_INSTR(21) & FDEC_FDEP_IS1_INSTR(22) & + FDEC_FDEP_IS1_INSTR(23) & FDEC_FDEP_IS1_INSTR(24) & + FDEC_FDEP_IS1_INSTR(25) & FDEC_FDEP_IS1_INSTR(26) & + FDEC_FDEP_IS1_INSTR(27) & FDEC_FDEP_IS1_INSTR(28) & + FDEC_FDEP_IS1_INSTR(29) & FDEC_FDEP_IS1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("0111111100110011")); +MQQ23:BARRIER_PT(23) <= + Eq(( FDEC_FDEP_IS1_INSTR(0) & FDEC_FDEP_IS1_INSTR(1) & + FDEC_FDEP_IS1_INSTR(2) & FDEC_FDEP_IS1_INSTR(3) & + FDEC_FDEP_IS1_INSTR(4) & FDEC_FDEP_IS1_INSTR(5) & + FDEC_FDEP_IS1_INSTR(21) & FDEC_FDEP_IS1_INSTR(22) & + FDEC_FDEP_IS1_INSTR(23) & FDEC_FDEP_IS1_INSTR(24) & + FDEC_FDEP_IS1_INSTR(26) & FDEC_FDEP_IS1_INSTR(27) & + FDEC_FDEP_IS1_INSTR(28) & FDEC_FDEP_IS1_INSTR(29) & + FDEC_FDEP_IS1_INSTR(30) ) , STD_ULOGIC_VECTOR'("011111111010010")); +MQQ24:BARRIER_PT(24) <= + Eq(( FDEC_FDEP_IS1_INSTR(0) & FDEC_FDEP_IS1_INSTR(1) & + FDEC_FDEP_IS1_INSTR(2) & FDEC_FDEP_IS1_INSTR(3) & + FDEC_FDEP_IS1_INSTR(4) & FDEC_FDEP_IS1_INSTR(5) & + FDEC_FDEP_IS1_INSTR(30) ) , STD_ULOGIC_VECTOR'("0100011")); +MQQ25:IS_BAR <= + (BARRIER_PT(1) OR BARRIER_PT(2) + OR BARRIER_PT(3) OR BARRIER_PT(4) + OR BARRIER_PT(5) OR BARRIER_PT(6) + OR BARRIER_PT(7) OR BARRIER_PT(8) + OR BARRIER_PT(9) OR BARRIER_PT(10) + OR BARRIER_PT(11) OR BARRIER_PT(12) + OR BARRIER_PT(13) OR BARRIER_PT(14) + OR BARRIER_PT(15) OR BARRIER_PT(16) + OR BARRIER_PT(17) OR BARRIER_PT(18) + OR BARRIER_PT(19) OR BARRIER_PT(20) + OR BARRIER_PT(21) OR BARRIER_PT(22) + OR BARRIER_PT(23) OR BARRIER_PT(24) + ); + +isMFSPR <= (fdec_fdep_is1_instr(0 to 5) = "011111") and (fdec_fdep_is1_instr(21 to 30) = "0101010011"); +isMTSPR <= (fdec_fdep_is1_instr(0 to 5) = "011111") and (fdec_fdep_is1_instr(21 to 30) = "0111010011"); +MQQ26:SLOWSPR_TABLE_PT(1) <= + Eq(( FDEC_FDEP_IS1_INSTR(16) & FDEC_FDEP_IS1_INSTR(17) & + FDEC_FDEP_IS1_INSTR(18) & FDEC_FDEP_IS1_INSTR(19) & + FDEC_FDEP_IS1_INSTR(20) & FDEC_FDEP_IS1_INSTR(11) & + FDEC_FDEP_IS1_INSTR(12) & FDEC_FDEP_IS1_INSTR(13) & + FDEC_FDEP_IS1_INSTR(15) ) , STD_ULOGIC_VECTOR'("010101110")); +MQQ27:SLOWSPR_TABLE_PT(2) <= + Eq(( FDEC_FDEP_IS1_INSTR(16) & FDEC_FDEP_IS1_INSTR(17) & + FDEC_FDEP_IS1_INSTR(18) & FDEC_FDEP_IS1_INSTR(19) & + FDEC_FDEP_IS1_INSTR(20) & FDEC_FDEP_IS1_INSTR(11) & + FDEC_FDEP_IS1_INSTR(13) & FDEC_FDEP_IS1_INSTR(14) & + FDEC_FDEP_IS1_INSTR(15) ) , STD_ULOGIC_VECTOR'("010101101")); +MQQ28:SLOWSPR_TABLE_PT(3) <= + Eq(( FDEC_FDEP_IS1_INSTR(16) & FDEC_FDEP_IS1_INSTR(17) & + FDEC_FDEP_IS1_INSTR(18) & FDEC_FDEP_IS1_INSTR(11) & + FDEC_FDEP_IS1_INSTR(12) & FDEC_FDEP_IS1_INSTR(13) & + FDEC_FDEP_IS1_INSTR(14) & FDEC_FDEP_IS1_INSTR(15) + ) , STD_ULOGIC_VECTOR'("11110100")); +MQQ29:SLOWSPR_TABLE_PT(4) <= + Eq(( FDEC_FDEP_IS1_INSTR(16) & FDEC_FDEP_IS1_INSTR(17) & + FDEC_FDEP_IS1_INSTR(18) & FDEC_FDEP_IS1_INSTR(19) & + FDEC_FDEP_IS1_INSTR(20) & FDEC_FDEP_IS1_INSTR(11) & + FDEC_FDEP_IS1_INSTR(12) & FDEC_FDEP_IS1_INSTR(14) + ) , STD_ULOGIC_VECTOR'("10011101")); +MQQ30:SLOWSPR_TABLE_PT(5) <= + Eq(( FDEC_FDEP_IS1_INSTR(16) & FDEC_FDEP_IS1_INSTR(17) & + FDEC_FDEP_IS1_INSTR(19) & FDEC_FDEP_IS1_INSTR(20) & + FDEC_FDEP_IS1_INSTR(11) & FDEC_FDEP_IS1_INSTR(12) & + FDEC_FDEP_IS1_INSTR(14) & FDEC_FDEP_IS1_INSTR(15) + ) , STD_ULOGIC_VECTOR'("11111100")); +MQQ31:SLOWSPR_TABLE_PT(6) <= + Eq(( FDEC_FDEP_IS1_INSTR(16) & FDEC_FDEP_IS1_INSTR(17) & + FDEC_FDEP_IS1_INSTR(19) & FDEC_FDEP_IS1_INSTR(20) & + FDEC_FDEP_IS1_INSTR(11) & FDEC_FDEP_IS1_INSTR(12) & + FDEC_FDEP_IS1_INSTR(14) & FDEC_FDEP_IS1_INSTR(15) + ) , STD_ULOGIC_VECTOR'("11111011")); +MQQ32:SLOWSPR_TABLE_PT(7) <= + Eq(( FDEC_FDEP_IS1_INSTR(16) & FDEC_FDEP_IS1_INSTR(18) & + FDEC_FDEP_IS1_INSTR(19) & FDEC_FDEP_IS1_INSTR(20) & + FDEC_FDEP_IS1_INSTR(11) & FDEC_FDEP_IS1_INSTR(12) & + FDEC_FDEP_IS1_INSTR(13) & FDEC_FDEP_IS1_INSTR(14) + ) , STD_ULOGIC_VECTOR'("10111000")); +MQQ33:SLOWSPR_TABLE_PT(8) <= + Eq(( FDEC_FDEP_IS1_INSTR(16) & FDEC_FDEP_IS1_INSTR(18) & + FDEC_FDEP_IS1_INSTR(19) & FDEC_FDEP_IS1_INSTR(20) & + FDEC_FDEP_IS1_INSTR(11) & FDEC_FDEP_IS1_INSTR(12) & + FDEC_FDEP_IS1_INSTR(13) & FDEC_FDEP_IS1_INSTR(15) + ) , STD_ULOGIC_VECTOR'("10111010")); +MQQ34:SLOWSPR_TABLE_PT(9) <= + Eq(( FDEC_FDEP_IS1_INSTR(16) & FDEC_FDEP_IS1_INSTR(17) & + FDEC_FDEP_IS1_INSTR(18) & FDEC_FDEP_IS1_INSTR(19) & + FDEC_FDEP_IS1_INSTR(20) & FDEC_FDEP_IS1_INSTR(12) & + FDEC_FDEP_IS1_INSTR(13) & FDEC_FDEP_IS1_INSTR(14) & + FDEC_FDEP_IS1_INSTR(15) ) , STD_ULOGIC_VECTOR'("111000010")); +MQQ35:SLOWSPR_TABLE_PT(10) <= + Eq(( FDEC_FDEP_IS1_INSTR(16) & FDEC_FDEP_IS1_INSTR(17) & + FDEC_FDEP_IS1_INSTR(18) & FDEC_FDEP_IS1_INSTR(19) & + FDEC_FDEP_IS1_INSTR(20) & FDEC_FDEP_IS1_INSTR(11) & + FDEC_FDEP_IS1_INSTR(12) & FDEC_FDEP_IS1_INSTR(13) & + FDEC_FDEP_IS1_INSTR(14) ) , STD_ULOGIC_VECTOR'("000011100")); +MQQ36:SLOWSPR_TABLE_PT(11) <= + Eq(( FDEC_FDEP_IS1_INSTR(16) & FDEC_FDEP_IS1_INSTR(18) & + FDEC_FDEP_IS1_INSTR(19) & FDEC_FDEP_IS1_INSTR(20) & + FDEC_FDEP_IS1_INSTR(11) & FDEC_FDEP_IS1_INSTR(12) & + FDEC_FDEP_IS1_INSTR(13) & FDEC_FDEP_IS1_INSTR(14) & + FDEC_FDEP_IS1_INSTR(15) ) , STD_ULOGIC_VECTOR'("110110000")); +MQQ37:SLOWSPR_TABLE_PT(12) <= + Eq(( FDEC_FDEP_IS1_INSTR(16) & FDEC_FDEP_IS1_INSTR(17) & + FDEC_FDEP_IS1_INSTR(18) & FDEC_FDEP_IS1_INSTR(19) & + FDEC_FDEP_IS1_INSTR(20) & FDEC_FDEP_IS1_INSTR(11) & + FDEC_FDEP_IS1_INSTR(13) & FDEC_FDEP_IS1_INSTR(14) & + FDEC_FDEP_IS1_INSTR(15) ) , STD_ULOGIC_VECTOR'("000011000")); +MQQ38:SLOWSPR_TABLE_PT(13) <= + Eq(( FDEC_FDEP_IS1_INSTR(16) & FDEC_FDEP_IS1_INSTR(17) & + FDEC_FDEP_IS1_INSTR(18) & FDEC_FDEP_IS1_INSTR(19) & + FDEC_FDEP_IS1_INSTR(20) & FDEC_FDEP_IS1_INSTR(11) & + FDEC_FDEP_IS1_INSTR(12) & FDEC_FDEP_IS1_INSTR(13) & + FDEC_FDEP_IS1_INSTR(14) ) , STD_ULOGIC_VECTOR'("010011111")); +MQQ39:SLOWSPR_TABLE_PT(14) <= + Eq(( FDEC_FDEP_IS1_INSTR(16) & FDEC_FDEP_IS1_INSTR(17) & + FDEC_FDEP_IS1_INSTR(18) & FDEC_FDEP_IS1_INSTR(11) & + FDEC_FDEP_IS1_INSTR(12) & FDEC_FDEP_IS1_INSTR(13) & + FDEC_FDEP_IS1_INSTR(14) & FDEC_FDEP_IS1_INSTR(15) + ) , STD_ULOGIC_VECTOR'("11110011")); +MQQ40:SLOWSPR_TABLE_PT(15) <= + Eq(( FDEC_FDEP_IS1_INSTR(16) & FDEC_FDEP_IS1_INSTR(17) & + FDEC_FDEP_IS1_INSTR(18) & FDEC_FDEP_IS1_INSTR(19) & + FDEC_FDEP_IS1_INSTR(20) & FDEC_FDEP_IS1_INSTR(11) & + FDEC_FDEP_IS1_INSTR(12) & FDEC_FDEP_IS1_INSTR(14) & + FDEC_FDEP_IS1_INSTR(15) ) , STD_ULOGIC_VECTOR'("010101100")); +MQQ41:SLOWSPR_TABLE_PT(16) <= + Eq(( FDEC_FDEP_IS1_INSTR(16) & FDEC_FDEP_IS1_INSTR(17) & + FDEC_FDEP_IS1_INSTR(18) & FDEC_FDEP_IS1_INSTR(19) & + FDEC_FDEP_IS1_INSTR(20) & FDEC_FDEP_IS1_INSTR(11) & + FDEC_FDEP_IS1_INSTR(12) & FDEC_FDEP_IS1_INSTR(14) + ) , STD_ULOGIC_VECTOR'("01010101")); +MQQ42:SLOWSPR_TABLE_PT(17) <= + Eq(( FDEC_FDEP_IS1_INSTR(16) & FDEC_FDEP_IS1_INSTR(17) & + FDEC_FDEP_IS1_INSTR(18) & FDEC_FDEP_IS1_INSTR(19) & + FDEC_FDEP_IS1_INSTR(11) & FDEC_FDEP_IS1_INSTR(12) & + FDEC_FDEP_IS1_INSTR(13) ) , STD_ULOGIC_VECTOR'("1111111")); +MQQ43:SLOWSPR_TABLE_PT(18) <= + Eq(( FDEC_FDEP_IS1_INSTR(16) & FDEC_FDEP_IS1_INSTR(17) & + FDEC_FDEP_IS1_INSTR(18) & FDEC_FDEP_IS1_INSTR(19) & + FDEC_FDEP_IS1_INSTR(20) & FDEC_FDEP_IS1_INSTR(11) & + FDEC_FDEP_IS1_INSTR(12) & FDEC_FDEP_IS1_INSTR(13) + ) , STD_ULOGIC_VECTOR'("11011110")); +MQQ44:SLOWSPR_TABLE_PT(19) <= + Eq(( FDEC_FDEP_IS1_INSTR(17) & FDEC_FDEP_IS1_INSTR(18) & + FDEC_FDEP_IS1_INSTR(19) & FDEC_FDEP_IS1_INSTR(20) & + FDEC_FDEP_IS1_INSTR(11) & FDEC_FDEP_IS1_INSTR(12) & + FDEC_FDEP_IS1_INSTR(13) & FDEC_FDEP_IS1_INSTR(14) + ) , STD_ULOGIC_VECTOR'("10111010")); +MQQ45:SLOWSPR_TABLE_PT(20) <= + Eq(( FDEC_FDEP_IS1_INSTR(16) & FDEC_FDEP_IS1_INSTR(17) & + FDEC_FDEP_IS1_INSTR(18) & FDEC_FDEP_IS1_INSTR(20) & + FDEC_FDEP_IS1_INSTR(11) ) , STD_ULOGIC_VECTOR'("11101")); +MQQ46:IS_SLOWSPR <= + (SLOWSPR_TABLE_PT(1) OR SLOWSPR_TABLE_PT(2) + OR SLOWSPR_TABLE_PT(3) OR SLOWSPR_TABLE_PT(4) + OR SLOWSPR_TABLE_PT(5) OR SLOWSPR_TABLE_PT(6) + OR SLOWSPR_TABLE_PT(7) OR SLOWSPR_TABLE_PT(8) + OR SLOWSPR_TABLE_PT(9) OR SLOWSPR_TABLE_PT(10) + OR SLOWSPR_TABLE_PT(11) OR SLOWSPR_TABLE_PT(12) + OR SLOWSPR_TABLE_PT(13) OR SLOWSPR_TABLE_PT(14) + OR SLOWSPR_TABLE_PT(15) OR SLOWSPR_TABLE_PT(16) + OR SLOWSPR_TABLE_PT(17) OR SLOWSPR_TABLE_PT(18) + OR SLOWSPR_TABLE_PT(19) OR SLOWSPR_TABLE_PT(20) + ); + +iu_au_is1_hold <= (barrier_in_progress or single_instr_dep_hit); +is2_vld_b <= not is2_vld_L2; +fxu_iss_stall_nor2: fxu_iss_stall <= not (fiss_fdep_is2_take or is2_vld_b); +is2_iss_stall_nor2: is2_iss_stall_b <= not (fxu_iss_stall or au_iu_issue_stall); +internal_is2_stall <= not is2_iss_stall_b; +iu_au_is2_stall <= internal_is2_stall; +sync_dep_hit <= (is1_instr_is_ISYNC or is1_instr_is_SYNC or is1_instr_is_TLBSYNC) and (shadow_pipe_vld or au_iu_is2_axubusy); +sp_barrier_clr <= (xu_iu_rf0_flush and sp_L2(RF0).barrier) or + (xu_iu_rf1_flush and sp_L2(RF1).barrier) or + (xu_iu_ex1_flush and sp_L2(EX1).barrier) or + (xu_iu_ex2_flush and sp_L2(EX2).barrier) or + (xu_iu_ex3_flush and sp_EX3_barrier_L2) or + (xu_iu_ex4_flush and sp_EX4_barrier_L2) or + (xu_iu_ex5_flush and sp_EX5_barrier_L2) ; +an_ac_sync_ack_d <= an_ac_sync_ack; +xu_iu_membar_tid_d <= xu_iu_membar_tid; +xu_iu_multdiv_done_d <= xu_iu_multdiv_done; +mm_iu_barrier_done_d <= mm_iu_barrier_done; +spr_fdep_ll_hold_d <= spr_fdep_ll_hold; +clr_barrier <= xu_iu_larx_done_tid or an_ac_sync_ack_l2 or ic_fdep_icbi_ack or an_ac_stcx_complete or sp_barrier_clr or xu_iu_slowspr_done or xu_iu_multdiv_done_l2 or mm_iu_barrier_done_l2; +set_barrier <= (not xu_iu_is2_flush and not barrier_L2 and is2_instr_is_barrier and not internal_is2_stall); +barrier_d_proc : process(barrier_L2, clr_barrier, set_barrier) +begin +barrier_d <= barrier_L2; +if ib(set_barrier) then +barrier_d <= '1'; +elsif ib(clr_barrier) then +barrier_d <= '0'; +end if; +end process barrier_d_proc; +xu_barrier_d_proc : process(xu_barrier_L2, xu_iu_membar_tid_l2, xu_iu_set_barr_tid) +begin +xu_barrier_d <= xu_barrier_L2; +if ib(xu_iu_set_barr_tid) then +xu_barrier_d <= '1'; +elsif ib(xu_iu_membar_tid_l2) then +xu_barrier_d <= '0'; +end if; +end process xu_barrier_d_proc; +barrier_in_progress <= barrier_L2 or is2_instr_is_barrier or is2_mult_hole_barrier or xu_barrier_L2 or spr_fdep_ll_hold_L2; +quiesce_barrier <= barrier_L2 or is2_instr_is_barrier or is2_mult_hole_barrier or xu_barrier_L2; +quiesce_d <= ic_fdep_load_quiesce and not quiesce_barrier and not au_iu_is2_axubusy; +iu_xu_quiesce <= quiesce_L2; +perf_early_d(0) <= dep_hit; +perf_early_d(1) <= fdec_fdep_is1_vld; +perf_early_d(2) <= internal_is2_stall; +perf_early_d(3) <= i_afd_is1_instr_v; +perf_early_d(4) <= au_iu_is1_dep_hit; +perf_early_d(5) <= barrier_in_progress; +perf_early_d(6) <= is2_is_slowspr_L2; +perf_early_d(7) <= RAW_dep_hit; +perf_early_d(8) <= WAW_LMQ_dep_hit; +perf_early_d(9) <= sync_dep_hit; +perf_early_d(10) <= xu_dep_hit; +perf_early_d(11) <= br_sprs_dep_hit; +perf_dep_hit <= perf_early_l2(0); +perf_fdec_fdep_is1_vld <= perf_early_l2(1); +perf_internal_is2_stall <= perf_early_l2(2); +perf_i_afd_is1_instr_v <= perf_early_l2(3); +perf_au_iu_is1_dep_hit <= perf_early_l2(4); +perf_barrier_in_progress <= perf_early_l2(5); +perf_is2_is_slowspr_L2 <= perf_early_l2(6); +perf_RAW_dep_hit <= perf_early_l2(7); +perf_WAW_LMQ_dep_hit <= perf_early_l2(8); +perf_sync_dep_hit <= perf_early_l2(9); +perf_xu_dep_hit <= perf_early_l2(10); +perf_br_sprs_dep_hit <= perf_early_l2(11); +perf_event_d(0) <= (perf_dep_hit and perf_fdec_fdep_is1_vld) or + (perf_internal_is2_stall and perf_i_afd_is1_instr_v) or + (perf_au_iu_is1_dep_hit); +perf_event_d(1) <= perf_internal_is2_stall and (perf_fdec_fdep_is1_vld or perf_i_afd_is1_instr_v); +perf_event_d(2) <= perf_barrier_in_progress and perf_fdec_fdep_is1_vld; +perf_event_d(3) <= perf_barrier_in_progress and perf_is2_is_slowspr_L2 and perf_fdec_fdep_is1_vld; +perf_event_d(4) <= perf_RAW_dep_hit and perf_fdec_fdep_is1_vld; +perf_event_d(5) <= perf_WAW_LMQ_dep_hit and perf_fdec_fdep_is1_vld; +perf_event_d(6) <= perf_sync_dep_hit and perf_fdec_fdep_is1_vld; +perf_event_d(7) <= perf_br_sprs_dep_hit and perf_fdec_fdep_is1_vld; +perf_event_d(8) <= perf_au_iu_is1_dep_hit; +perf_event_d(9) <= perf_xu_dep_hit and perf_fdec_fdep_is1_vld; +perf_event_d(10) <= (perf_xu_dep_hit and perf_fdec_fdep_is1_vld) or perf_au_iu_is1_dep_hit; +perf_event_d(11) <= '0'; +fdep_perf_event(0 TO 11) <= perf_event_l2(0 to 11); +fdep_dbg_data_d(0) <= barrier_l2; +fdep_dbg_data_d(1) <= is2_instr_is_barrier; +fdep_dbg_data_d(2) <= is2_mult_hole_barrier; +fdep_dbg_data_d(3) <= xu_barrier_L2; +fdep_dbg_data_d(4) <= xu_iu_larx_done_tid; +fdep_dbg_data_d(5) <= an_ac_sync_ack; +fdep_dbg_data_d(6) <= an_ac_stcx_complete; +fdep_dbg_data_d(7) <= ic_fdep_icbi_ack; +fdep_dbg_data_d(8) <= sp_barrier_clr; +fdep_dbg_data_d(9) <= xu_iu_slowspr_done; +fdep_dbg_data_d(10) <= xu_iu_multdiv_done; +fdep_dbg_data_d(11) <= mm_iu_barrier_done; +fdep_dbg_data_d(12) <= xu_iu_set_barr_tid; +fdep_dbg_data_d(13) <= xu_iu_membar_tid; +fdep_dbg_data_d(14) <= fdec_fdep_is1_vld; +fdep_dbg_data_d(15) <= internal_is2_stall; +fdep_dbg_data_d(16) <= RAW_dep_hit; +fdep_dbg_data_d(17) <= br_sprs_dep_hit; +fdep_dbg_data_d(18) <= sync_dep_hit; +fdep_dbg_data_d(19) <= single_instr_dep_hit; +fdep_dbg_data_d(20) <= WAW_LMQ_dep_hit; +fdep_dbg_data_d(21) <= fdec_fdep_is1_force_ram; +fdep_dbg_data(0 TO 21) <= fdep_dbg_data_l2(0 to 21); +act_nonvalid <= fdec_fdep_is1_vld or i_afd_is1_instr_v; +is2_vld: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_vld_offset), + scout => sov(is2_vld_offset), + din => is2_vld_d, + dout => is2_vld_l2); + + +is2_instr: tri_rlmreg_p + generic map (width => is2_instr_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_instr_offset to is2_instr_offset + is2_instr_l2'length-1), + scout => sov(is2_instr_offset to is2_instr_offset + is2_instr_l2'length-1), + din => is2_instr_d, + dout => is2_instr_l2); + + +is2_ta_vld: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_ta_vld_offset), + scout => sov(is2_ta_vld_offset), + din => is2_ta_vld_d, + dout => is2_ta_vld_l2); + + +is2_ta: tri_rlmreg_p + generic map (width => is2_ta_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_ta_offset to is2_ta_offset + is2_ta_l2'length-1), + scout => sov(is2_ta_offset to is2_ta_offset + is2_ta_l2'length-1), + din => is2_ta_d, + dout => is2_ta_l2); + + + + +is2_s1_vld: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_s1_vld_offset), + scout => sov(is2_s1_vld_offset), + din => is2_s1_vld_d, + dout => is2_s1_vld_l2); + + +is2_s1: tri_rlmreg_p + generic map (width => is2_s1_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_s1_offset to is2_s1_offset + is2_s1_l2'length-1), + scout => sov(is2_s1_offset to is2_s1_offset + is2_s1_l2'length-1), + din => is2_s1_d, + dout => is2_s1_l2); + + + +is2_s2_vld: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_s2_vld_offset), + scout => sov(is2_s2_vld_offset), + din => is2_s2_vld_d, + dout => is2_s2_vld_l2); + + +is2_s2: tri_rlmreg_p + generic map (width => is2_s2_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_s2_offset to is2_s2_offset + is2_s2_l2'length-1), + scout => sov(is2_s2_offset to is2_s2_offset + is2_s2_l2'length-1), + din => is2_s2_d, + dout => is2_s2_l2); + + + +is2_s3_vld: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_s3_vld_offset), + scout => sov(is2_s3_vld_offset), + din => is2_s3_vld_d, + dout => is2_s3_vld_l2); + + +is2_s3: tri_rlmreg_p + generic map (width => is2_s3_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_s3_offset to is2_s3_offset + is2_s3_l2'length-1), + scout => sov(is2_s3_offset to is2_s3_offset + is2_s3_l2'length-1), + din => is2_s3_d, + dout => is2_s3_l2); + + + + + +is2_is_slowspr: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_is_slowspr_offset), + scout => sov(is2_is_slowspr_offset), + din => is2_is_slowspr_d, + dout => is2_is_slowspr_l2); + + +is2_is_barrier: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_is_barrier_offset), + scout => sov(is2_is_barrier_offset), + din => is2_is_barrier_d, + dout => is2_is_barrier_l2); + + +is2_pred_update: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_pred_update_offset), + scout => sov(is2_pred_update_offset), + din => is2_pred_update_d, + dout => is2_pred_update_l2); + + +is2_pred_taken_cnt: tri_rlmreg_p + generic map (width => is2_pred_taken_cnt_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_pred_taken_cnt_offset to is2_pred_taken_cnt_offset + is2_pred_taken_cnt_l2'length-1), + scout => sov(is2_pred_taken_cnt_offset to is2_pred_taken_cnt_offset + is2_pred_taken_cnt_l2'length-1), + din => is2_pred_taken_cnt_d, + dout => is2_pred_taken_cnt_l2); + + +is2_gshare: tri_rlmreg_p + generic map (width => is2_gshare_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_gshare_offset to is2_gshare_offset + is2_gshare_l2'length-1), + scout => sov(is2_gshare_offset to is2_gshare_offset + is2_gshare_l2'length-1), + din => is2_gshare_d, + dout => is2_gshare_l2); + + +is2_hole_delay: tri_rlmreg_p + generic map (width => is2_hole_delay_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_hole_delay_offset to is2_hole_delay_offset + is2_hole_delay_l2'length-1), + scout => sov(is2_hole_delay_offset to is2_hole_delay_offset + is2_hole_delay_l2'length-1), + din => is2_hole_delay_d, + dout => is2_hole_delay_l2); + +is2_is_ucode: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_is_ucode_offset), + scout => sov(is2_is_ucode_offset), + din => is2_is_ucode_d, + dout => is2_is_ucode_l2); + + +is2_to_ucode: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_to_ucode_offset), + scout => sov(is2_to_ucode_offset), + din => is2_to_ucode_d, + dout => is2_to_ucode_l2); + + +is2_ifar: tri_rlmreg_p + generic map (width => is2_ifar_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_ifar_offset to is2_ifar_offset + is2_ifar_l2'length-1), + scout => sov(is2_ifar_offset to is2_ifar_offset + is2_ifar_l2'length-1), + din => is2_ifar_d, + dout => is2_ifar_l2); + + +is2_error: tri_rlmreg_p + generic map (width => is2_error_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_error_offset to is2_error_offset + is2_error_l2'length-1), + scout => sov(is2_error_offset to is2_error_offset + is2_error_l2'length-1), + din => is2_error_d, + dout => is2_error_l2); +sp_IS2_d <= sp_d(IS2).i_nobyp_vld & sp_d(IS2).i_vld & sp_d(IS2).ta_vld & sp_d(IS2).ta & + sp_d(IS2).UpdatesLR & sp_d(IS2).UpdatesCR & sp_d(IS2).UpdatesCTR & sp_d(IS2).UpdatesXER & sp_d(IS2).UpdatesMSR & sp_d(IS2).UpdatesSPR & + sp_d(IS2).complete & sp_d(IS2).barrier; +sp_l2(IS2).i_nobyp_vld <= sp_IS2_l2(0); +sp_l2(IS2).i_vld <= sp_IS2_l2(1); +sp_l2(IS2).ta_vld <= sp_IS2_l2(2); +sp_l2(IS2).ta <= sp_IS2_l2(3 to 8); +sp_l2(IS2).updateslr <= sp_IS2_l2(9); +sp_l2(IS2).updatescr <= sp_IS2_l2(10); +sp_l2(IS2).updatesctr <= sp_IS2_l2(11); +sp_l2(IS2).updatesxer <= sp_IS2_l2(12); +sp_l2(IS2).updatesmsr <= sp_IS2_l2(13); +sp_l2(IS2).updatesspr <= sp_IS2_l2(14); +sp_l2(IS2).complete <= sp_IS2_l2(15 to 19); +sp_l2(IS2).barrier <= sp_IS2_l2(20); + + + +sp_IS2: tri_rlmreg_p + generic map (width => 21, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => sp_IS2_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(sp_IS2_offset to sp_IS2_offset + 21-1), + scout => sov(sp_IS2_offset to sp_IS2_offset + 21-1), + din => sp_IS2_d, + dout => sp_IS2_l2); +sp_RF0_d <= sp_d(RF0).i_nobyp_vld & sp_d(RF0).i_vld & sp_d(RF0).ta_vld & sp_d(RF0).ta & + sp_d(RF0).UpdatesLR & sp_d(RF0).UpdatesCR & sp_d(RF0).UpdatesCTR & sp_d(RF0).UpdatesXER & sp_d(RF0).UpdatesMSR & sp_d(RF0).UpdatesSPR & + sp_d(RF0).complete & sp_d(RF0).barrier; +sp_l2(RF0).i_nobyp_vld <= sp_RF0_l2(0); +sp_l2(RF0).i_vld <= sp_RF0_l2(1); +sp_l2(RF0).ta_vld <= sp_RF0_l2(2); +sp_l2(RF0).ta <= sp_RF0_l2(3 to 8); +sp_l2(RF0).updateslr <= sp_RF0_l2(9); +sp_l2(RF0).updatescr <= sp_RF0_l2(10); +sp_l2(RF0).updatesctr <= sp_RF0_l2(11); +sp_l2(RF0).updatesxer <= sp_RF0_l2(12); +sp_l2(RF0).updatesmsr <= sp_RF0_l2(13); +sp_l2(RF0).updatesspr <= sp_RF0_l2(14); +sp_l2(RF0).complete <= sp_RF0_l2(15 to 19); +sp_l2(RF0).barrier <= sp_RF0_l2(20); + + + +sp_RF0: tri_rlmreg_p + generic map (width => 21, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => sp_RF0_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(sp_RF0_offset to sp_RF0_offset + 21-1), + scout => sov(sp_RF0_offset to sp_RF0_offset + 21-1), + din => sp_RF0_d, + dout => sp_RF0_l2); +sp_RF1_d <= sp_d(RF1).i_nobyp_vld & sp_d(RF1).i_vld & sp_d(RF1).ta_vld & sp_d(RF1).ta & + sp_d(RF1).UpdatesLR & sp_d(RF1).UpdatesCR & sp_d(RF1).UpdatesCTR & sp_d(RF1).UpdatesXER & sp_d(RF1).UpdatesMSR & sp_d(RF1).UpdatesSPR & + sp_d(RF1).complete & sp_d(RF1).barrier; +sp_l2(RF1).i_nobyp_vld <= sp_RF1_l2(0); +sp_l2(RF1).i_vld <= sp_RF1_l2(1); +sp_l2(RF1).ta_vld <= sp_RF1_l2(2); +sp_l2(RF1).ta <= sp_RF1_l2(3 to 8); +sp_l2(RF1).updateslr <= sp_RF1_l2(9); +sp_l2(RF1).updatescr <= sp_RF1_l2(10); +sp_l2(RF1).updatesctr <= sp_RF1_l2(11); +sp_l2(RF1).updatesxer <= sp_RF1_l2(12); +sp_l2(RF1).updatesmsr <= sp_RF1_l2(13); +sp_l2(RF1).updatesspr <= sp_RF1_l2(14); +sp_l2(RF1).complete <= sp_RF1_l2(15 to 19); +sp_l2(RF1).barrier <= sp_RF1_l2(20); + + + +sp_RF1: tri_rlmreg_p + generic map (width => 21, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => sp_RF1_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(sp_RF1_offset to sp_RF1_offset + 21-1), + scout => sov(sp_RF1_offset to sp_RF1_offset + 21-1), + din => sp_RF1_d, + dout => sp_RF1_l2); +sp_EX1_d <= sp_d(EX1).i_nobyp_vld & sp_d(EX1).i_vld & sp_d(EX1).ta_vld & sp_d(EX1).ta & + sp_d(EX1).UpdatesLR & sp_d(EX1).UpdatesCR & sp_d(EX1).UpdatesCTR & sp_d(EX1).UpdatesXER & sp_d(EX1).UpdatesMSR & sp_d(EX1).UpdatesSPR & + sp_d(EX1).complete & sp_d(EX1).barrier; +sp_l2(EX1).i_nobyp_vld <= sp_EX1_l2(0); +sp_l2(EX1).i_vld <= sp_EX1_l2(1); +sp_l2(EX1).ta_vld <= sp_EX1_l2(2); +sp_l2(EX1).ta <= sp_EX1_l2(3 to 8); +sp_l2(EX1).updateslr <= sp_EX1_l2(9); +sp_l2(EX1).updatescr <= sp_EX1_l2(10); +sp_l2(EX1).updatesctr <= sp_EX1_l2(11); +sp_l2(EX1).updatesxer <= sp_EX1_l2(12); +sp_l2(EX1).updatesmsr <= sp_EX1_l2(13); +sp_l2(EX1).updatesspr <= sp_EX1_l2(14); +sp_l2(EX1).complete <= sp_EX1_l2(15 to 19); +sp_l2(EX1).barrier <= sp_EX1_l2(20); + + + +sp_EX1: tri_rlmreg_p + generic map (width => 21, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => sp_EX1_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(sp_EX1_offset to sp_EX1_offset + 21-1), + scout => sov(sp_EX1_offset to sp_EX1_offset + 21-1), + din => sp_EX1_d, + dout => sp_EX1_l2); +sp_EX2_d <= sp_d(EX2).i_nobyp_vld & sp_d(EX2).i_vld & sp_d(EX2).ta_vld & sp_d(EX2).ta & + sp_d(EX2).UpdatesLR & sp_d(EX2).UpdatesCR & sp_d(EX2).UpdatesCTR & sp_d(EX2).UpdatesXER & sp_d(EX2).UpdatesMSR & sp_d(EX2).UpdatesSPR & + sp_d(EX2).complete & sp_d(EX2).barrier; +sp_l2(EX2).i_nobyp_vld <= sp_EX2_l2(0); +sp_l2(EX2).i_vld <= sp_EX2_l2(1); +sp_l2(EX2).ta_vld <= sp_EX2_l2(2); +sp_l2(EX2).ta <= sp_EX2_l2(3 to 8); +sp_l2(EX2).updateslr <= sp_EX2_l2(9); +sp_l2(EX2).updatescr <= sp_EX2_l2(10); +sp_l2(EX2).updatesctr <= sp_EX2_l2(11); +sp_l2(EX2).updatesxer <= sp_EX2_l2(12); +sp_l2(EX2).updatesmsr <= sp_EX2_l2(13); +sp_l2(EX2).updatesspr <= sp_EX2_l2(14); +sp_l2(EX2).complete <= sp_EX2_l2(15 to 19); +sp_l2(EX2).barrier <= sp_EX2_l2(20); + + + +sp_EX2: tri_rlmreg_p + generic map (width => 21, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => sp_EX2_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(sp_EX2_offset to sp_EX2_offset + 21-1), + scout => sov(sp_EX2_offset to sp_EX2_offset + 21-1), + din => sp_EX2_d, + dout => sp_EX2_l2); +sp_IS2_act <= sp_l2(IS2).i_nobyp_vld or fdec_fdep_is1_vld; +sp_RF0_act <= sp_l2(RF0).i_nobyp_vld or sp_l2(IS2).i_nobyp_vld; +sp_RF1_act <= sp_l2(RF1).i_nobyp_vld or sp_l2(RF0).i_nobyp_vld; +sp_EX1_act <= sp_l2(EX1).i_nobyp_vld or sp_l2(RF1).i_nobyp_vld; +sp_EX2_act <= sp_l2(EX2).i_nobyp_vld or sp_l2(EX1).i_nobyp_vld; +sp_EX3_act <= sp_ex3_i_nobyp_vld_l2 or sp_l2(EX2).i_nobyp_vld; +sp_EX4_act <= sp_ex4_i_nobyp_vld_l2 or sp_ex3_i_nobyp_vld_l2; +sp_EX5_act <= sp_ex5_i_nobyp_vld_l2 or sp_ex4_i_nobyp_vld_l2; + + +sp_ex3_i_nobyp_vld: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => sp_EX3_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(sp_ex3_i_nobyp_vld_offset), + scout => sov(sp_ex3_i_nobyp_vld_offset), + din => sp_ex3_i_nobyp_vld_d, + dout => sp_ex3_i_nobyp_vld_l2); + + +sp_ex3_barrier: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => sp_EX3_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(sp_ex3_barrier_offset), + scout => sov(sp_ex3_barrier_offset), + din => sp_ex3_barrier_d, + dout => sp_ex3_barrier_l2); + + +sp_ex4_i_nobyp_vld: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => sp_EX4_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(sp_ex4_i_nobyp_vld_offset), + scout => sov(sp_ex4_i_nobyp_vld_offset), + din => sp_ex4_i_nobyp_vld_d, + dout => sp_ex4_i_nobyp_vld_l2); + + +sp_ex4_barrier: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => sp_EX4_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(sp_ex4_barrier_offset), + scout => sov(sp_ex4_barrier_offset), + din => sp_ex4_barrier_d, + dout => sp_ex4_barrier_l2); + + +sp_ex5_i_nobyp_vld: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => sp_EX5_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(sp_ex5_i_nobyp_vld_offset), + scout => sov(sp_ex5_i_nobyp_vld_offset), + din => sp_ex5_i_nobyp_vld_d, + dout => sp_ex5_i_nobyp_vld_l2); + + +sp_ex5_barrier: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => sp_EX5_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(sp_ex5_barrier_offset), + scout => sov(sp_ex5_barrier_offset), + din => sp_ex5_barrier_d, + dout => sp_ex5_barrier_l2); +lm_assign: for i in 0 to lmq_entries-1 generate +sp_LM_d(7*i TO 6+7*i) <= sp_d_LM(i).ta_vld & sp_d_LM(i).ta; +sp_l2_LM(i).ta_vld <= sp_LM_l2(0+7*i); +sp_l2_LM(i).ta <= sp_LM_l2(1+7*i to 6+7*i); +end generate; + + +sp_LM: tri_rlmreg_p + generic map (width => 7*lmq_entries, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(sp_lm_offset to sp_lm_offset + 7*lmq_entries-1), + scout => sov(sp_lm_offset to sp_lm_offset + 7*lmq_entries-1), + din => sp_LM_d, + dout => sp_LM_l2); + + + +barrier: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(barrier_offset), + scout => sov(barrier_offset), + din => barrier_d, + dout => barrier_l2); + + +xu_barrier: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_barrier_offset), + scout => sov(xu_barrier_offset), + din => xu_barrier_d, + dout => xu_barrier_l2); + + +mult_hole_barrier: tri_rlmreg_p + generic map (width => mult_hole_barrier_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => mult_hole_barrier_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(mult_hole_barrier_offset to mult_hole_barrier_offset + mult_hole_barrier_l2'length-1), + scout => sov(mult_hole_barrier_offset to mult_hole_barrier_offset + mult_hole_barrier_l2'length-1), + din => mult_hole_barrier_d, + dout => mult_hole_barrier_l2); + +is2_axu_ld_or_st: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_axu_ld_or_st_offset), + scout => sov(is2_axu_ld_or_st_offset), + din => is2_axu_ld_or_st_d, + dout => is2_axu_ld_or_st_l2); + + +is2_axu_store: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_axu_store_offset), + scout => sov(is2_axu_store_offset), + din => is2_axu_store_d, + dout => is2_axu_store_l2); + + +is2_axu_ldst_indexed: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_axu_ldst_indexed_offset), + scout => sov(is2_axu_ldst_indexed_offset), + din => is2_axu_ldst_indexed_d, + dout => is2_axu_ldst_indexed_l2); + + +is2_axu_ldst_tag: tri_rlmreg_p + generic map (width => is2_axu_ldst_tag_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_axu_ldst_tag_offset to is2_axu_ldst_tag_offset + is2_axu_ldst_tag_l2'length-1), + scout => sov(is2_axu_ldst_tag_offset to is2_axu_ldst_tag_offset + is2_axu_ldst_tag_l2'length-1), + din => is2_axu_ldst_tag_d, + dout => is2_axu_ldst_tag_l2); + + +is2_axu_ldst_size: tri_rlmreg_p + generic map (width => is2_axu_ldst_size_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_axu_ldst_size_offset to is2_axu_ldst_size_offset + is2_axu_ldst_size_l2'length-1), + scout => sov(is2_axu_ldst_size_offset to is2_axu_ldst_size_offset + is2_axu_ldst_size_l2'length-1), + din => is2_axu_ldst_size_d, + dout => is2_axu_ldst_size_l2); + + + +is2_axu_ldst_update: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_axu_ldst_update_offset), + scout => sov(is2_axu_ldst_update_offset), + din => is2_axu_ldst_update_d, + dout => is2_axu_ldst_update_l2); + + +is2_axu_ldst_extpid: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_axu_ldst_extpid_offset), + scout => sov(is2_axu_ldst_extpid_offset), + din => is2_axu_ldst_extpid_d, + dout => is2_axu_ldst_extpid_l2); + + +is2_axu_ldst_forcealign: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_axu_ldst_forcealign_offset), + scout => sov(is2_axu_ldst_forcealign_offset), + din => is2_axu_ldst_forcealign_d, + dout => is2_axu_ldst_forcealign_l2); + + +is2_axu_ldst_forceexcept: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_axu_ldst_forceexcept_offset), + scout => sov(is2_axu_ldst_forceexcept_offset), + din => is2_axu_ldst_forceexcept_d, + dout => is2_axu_ldst_forceexcept_l2); + + +is2_axu_movedp: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_axu_movedp_offset), + scout => sov(is2_axu_movedp_offset), + din => is2_axu_movedp_d, + dout => is2_axu_movedp_l2); + + +is2_axu_mffgpr: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_axu_mffgpr_offset), + scout => sov(is2_axu_mffgpr_offset), + din => is2_axu_mffgpr_d, + dout => is2_axu_mffgpr_l2); + + +is2_axu_mftgpr: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_axu_mftgpr_offset), + scout => sov(is2_axu_mftgpr_offset), + din => is2_axu_mftgpr_d, + dout => is2_axu_mftgpr_l2); + + +is2_axu_instr_type: tri_rlmreg_p + generic map (width => is2_axu_instr_type_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_axu_instr_type_offset to is2_axu_instr_type_offset + is2_axu_instr_type_l2'length-1), + scout => sov(is2_axu_instr_type_offset to is2_axu_instr_type_offset + is2_axu_instr_type_l2'length-1), + din => is2_axu_instr_type_d, + dout => is2_axu_instr_type_l2); + + +is2_match: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_match_offset), + scout => sov(is2_match_offset), + din => is2_match_d, + dout => is2_match_l2); + + +is2_2ucode: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_2ucode_offset), + scout => sov(is2_2ucode_offset), + din => is2_2ucode_d, + dout => is2_2ucode_l2); + + +is2_2ucode_type: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_2ucode_type_offset), + scout => sov(is2_2ucode_type_offset), + din => is2_2ucode_type_d, + dout => is2_2ucode_type_l2); + + + +single_instr_mode: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(single_instr_mode_offset), + scout => sov(single_instr_mode_offset), + din => single_instr_mode_d, + dout => single_instr_mode_l2); +event_bus_enable_d <= pc_iu_event_bus_enable; + + +event_enable_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(event_bus_enable_offset), + scout => sov(event_bus_enable_offset), + din => event_bus_enable_d, + dout => event_bus_enable_q); +trace_bus_enable_d <= pc_iu_trace_bus_enable; + + +trace_enable_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(trace_bus_enable_offset), + scout => sov(trace_bus_enable_offset), + din => trace_bus_enable_d, + dout => trace_bus_enable_q); + + +perf_early: tri_rlmreg_p + generic map (width => perf_early_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => event_bus_enable_q, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(perf_early_offset to perf_early_offset + perf_early_l2'length-1), + scout => sov(perf_early_offset to perf_early_offset + perf_early_l2'length-1), + din => perf_early_d, + dout => perf_early_l2); + + +perf_event: tri_rlmreg_p + generic map (width => perf_event_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => event_bus_enable_q, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(perf_event_offset to perf_event_offset + perf_event_l2'length-1), + scout => sov(perf_event_offset to perf_event_offset + perf_event_l2'length-1), + din => perf_event_d, + dout => perf_event_l2); + + +fdep_dbg_data_reg: tri_rlmreg_p + generic map (width => fdep_dbg_data_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => trace_bus_enable_q, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(fdep_dbg_data_offset to fdep_dbg_data_offset + fdep_dbg_data_l2'length-1), + scout => sov(fdep_dbg_data_offset to fdep_dbg_data_offset + fdep_dbg_data_l2'length-1), + din => fdep_dbg_data_d, + dout => fdep_dbg_data_l2); + +quiesce: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + + scin => siv(quiesce_offset), + scout => sov(quiesce_offset), + din => quiesce_d, + dout => quiesce_l2); + +an_ac_sync_ack_latch: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(an_ac_sync_ack_offset), + scout => sov(an_ac_sync_ack_offset), + din => an_ac_sync_ack_d, + dout => an_ac_sync_ack_l2); + + +xu_iu_membar_tid_latch: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_iu_membar_tid_offset), + scout => sov(xu_iu_membar_tid_offset), + din => xu_iu_membar_tid_d, + dout => xu_iu_membar_tid_l2); + + +xu_iu_multdiv_done_latch: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_iu_multdiv_done_offset), + scout => sov(xu_iu_multdiv_done_offset), + din => xu_iu_multdiv_done_d, + dout => xu_iu_multdiv_done_l2); + + +mm_iu_barrier_done_latch: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(mm_iu_barrier_done_offset), + scout => sov(mm_iu_barrier_done_offset), + din => mm_iu_barrier_done_d, + dout => mm_iu_barrier_done_l2); + + +spr_fdep_ll_hold_latch: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(spr_fdep_ll_hold_offset), + scout => sov(spr_fdep_ll_hold_offset), + din => spr_fdep_ll_hold_d, + dout => spr_fdep_ll_hold_l2); + + +en_dcr_latch: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(en_dcr_offset), + scout => sov(en_dcr_offset), + din => en_dcr_d, + dout => en_dcr_l2); + + +spare_latch: tri_rlmreg_p + generic map (width => spare_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(spare_offset to spare_offset + spare_l2'length-1), + scout => sov(spare_offset to spare_offset + spare_l2'length-1), + din => spare_l2, + dout => spare_l2); +fdep_fiss_is2_instr <= is2_instr_l2; +fdep_fiss_is2_ta_vld <= is2_ta_vld_l2; +fdep_fiss_is2_ta <= is2_ta_l2; +fdep_fiss_is2_s1_vld <= is2_s1_vld_l2; +fdep_fiss_is2_s1 <= is2_s1_l2; +fdep_fiss_is2_s2_vld <= is2_s2_vld_l2; +fdep_fiss_is2_s2 <= is2_s2_l2; +fdep_fiss_is2_s3_vld <= is2_s3_vld_l2; +fdep_fiss_is2_s3 <= is2_s3_l2; +fdep_fiss_is2_pred_update <= is2_pred_update_l2; +fdep_fiss_is2_pred_taken_cnt <= is2_pred_taken_cnt_l2; +fdep_fiss_is2_gshare <= is2_gshare_l2; +fdep_fiss_is2_ifar <= is2_ifar_l2; +fdep_fiss_is2_error <= is2_error_l2; +fdep_fiss_is2_axu_ld_or_st <= is2_axu_ld_or_st_L2; +fdep_fiss_is2_axu_store <= is2_axu_store_L2; +fdep_fiss_is2_axu_ldst_indexed <= is2_axu_ldst_indexed_L2; +fdep_fiss_is2_axu_ldst_tag <= is2_axu_ldst_tag_L2; +fdep_fiss_is2_axu_ldst_size <= is2_axu_ldst_size_L2; +fdep_fiss_is2_axu_ldst_update <= is2_axu_ldst_update_L2; +fdep_fiss_is2_axu_ldst_extpid <= is2_axu_ldst_extpid_L2; +fdep_fiss_is2_axu_ldst_forcealign <= is2_axu_ldst_forcealign_L2; +fdep_fiss_is2_axu_ldst_forceexcept <= is2_axu_ldst_forceexcept_L2; +fdep_fiss_is2_axu_mftgpr <= is2_axu_mftgpr_L2; +fdep_fiss_is2_axu_mffgpr <= is2_axu_mffgpr_L2; +fdep_fiss_is2_axu_movedp <= is2_axu_movedp_L2; +fdep_fiss_is2_axu_instr_type <= is2_axu_instr_type_L2; +fdep_fiss_is2_match <= is2_match_L2; +fdep_fiss_is2_2ucode <= is2_2ucode_L2; +fdep_fiss_is2_2ucode_type <= is2_2ucode_type_L2; +fdep_fiss_is2_hole_delay <= is2_hole_delay_L2; +fdep_fiss_is2_to_ucode <= is2_to_ucode_L2; +fdep_fiss_is2_is_ucode <= is2_is_ucode_L2; +fdep_fiss_is2early_vld <= fdec_fdep_is1_vld; +fdep_fiss_is1_xu_dep_hit_b <= fxu_dep_hit_b; +siv(0 TO scan_right) <= sov(1 to scan_right) & scan_in; +scan_out <= sov(0); +END IUQ_FXU_DEP; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_fxu_dep_cmp.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_fxu_dep_cmp.vhdl new file mode 100644 index 0000000..3f0a7f2 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_fxu_dep_cmp.vhdl @@ -0,0 +1,377 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; + use ieee.std_logic_1164.all ; +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + +entity iuq_fxu_dep_cmp is + +port( + is1_v : in std_ulogic; + is2_v : in std_ulogic; + rf0_v : in std_ulogic; + rf1_v : in std_ulogic; + ex1_v : in std_ulogic; + ex2_v : in std_ulogic; + lm0_v : in std_ulogic; + lm1_v : in std_ulogic; + lm2_v : in std_ulogic; + lm3_v : in std_ulogic; + lm4_v : in std_ulogic; + lm5_v : in std_ulogic; + lm6_v : in std_ulogic; + lm7_v : in std_ulogic; + + is1_ad : in std_ulogic_vector(0 to 5); + is2_ad : in std_ulogic_vector(0 to 5); + rf0_ad : in std_ulogic_vector(0 to 5); + rf1_ad : in std_ulogic_vector(0 to 5); + ex1_ad : in std_ulogic_vector(0 to 5); + ex2_ad : in std_ulogic_vector(0 to 5); + lm0_ad : in std_ulogic_vector(0 to 5); + lm1_ad : in std_ulogic_vector(0 to 5); + lm2_ad : in std_ulogic_vector(0 to 5); + lm3_ad : in std_ulogic_vector(0 to 5); + lm4_ad : in std_ulogic_vector(0 to 5); + lm5_ad : in std_ulogic_vector(0 to 5); + lm6_ad : in std_ulogic_vector(0 to 5); + lm7_ad : in std_ulogic_vector(0 to 5); + + ad_hit_b : out std_ulogic + + ); + + + +end iuq_fxu_dep_cmp; + +architecture iuq_fxu_dep_cmp of iuq_fxu_dep_cmp is + +signal lm0_ad_buf, lm0_ad_buf_b :std_ulogic_vector(0 to 5); +signal lm1_ad_buf, lm1_ad_buf_b :std_ulogic_vector(0 to 5); +signal lm2_ad_buf, lm2_ad_buf_b :std_ulogic_vector(0 to 5); +signal lm3_ad_buf, lm3_ad_buf_b :std_ulogic_vector(0 to 5); +signal lm4_ad_buf, lm4_ad_buf_b :std_ulogic_vector(0 to 5); +signal lm5_ad_buf, lm5_ad_buf_b :std_ulogic_vector(0 to 5); +signal lm6_ad_buf, lm6_ad_buf_b :std_ulogic_vector(0 to 5); +signal lm7_ad_buf, lm7_ad_buf_b :std_ulogic_vector(0 to 5); +signal ex2_ad_buf, ex2_ad_buf_b :std_ulogic_vector(0 to 5); +signal ex1_ad_buf, ex1_ad_buf_b :std_ulogic_vector(0 to 5); +signal rf1_ad_buf, rf1_ad_buf_b :std_ulogic_vector(0 to 5); +signal rf0_ad_buf, rf0_ad_buf_b :std_ulogic_vector(0 to 5); +signal is2_ad_buf, is2_ad_buf_b :std_ulogic_vector(0 to 5); +signal is1_ad_buf0, is1_ad_buf0_b :std_ulogic_vector(0 to 5); +signal is1_ad_buf1, is1_ad_buf1_b :std_ulogic_vector(0 to 5); +signal is1_ad_buf2, is1_ad_buf2_b :std_ulogic_vector(0 to 5); + +signal a_eq_lm0_x :std_ulogic_vector(0 to 5); +signal a_eq_lm0_01_b , a_eq_lm0_23_b , a_eq_lm0_45_b :std_ulogic; +signal a_eq_lm0_u ,a_eq_lm0_v , a_eq_lm0_b :std_ulogic; + +signal a_eq_lm1_x :std_ulogic_vector(0 to 5); +signal a_eq_lm1_01_b , a_eq_lm1_23_b , a_eq_lm1_45_b :std_ulogic; +signal a_eq_lm1_u ,a_eq_lm1_v , a_eq_lm1_b :std_ulogic; + +signal a_eq_lm2_x :std_ulogic_vector(0 to 5); +signal a_eq_lm2_01_b , a_eq_lm2_23_b , a_eq_lm2_45_b :std_ulogic; +signal a_eq_lm2_u ,a_eq_lm2_v , a_eq_lm2_b :std_ulogic; + +signal a_eq_lm3_x :std_ulogic_vector(0 to 5); +signal a_eq_lm3_01_b , a_eq_lm3_23_b , a_eq_lm3_45_b :std_ulogic; +signal a_eq_lm3_u ,a_eq_lm3_v , a_eq_lm3_b :std_ulogic; + +signal a_eq_lm4_x :std_ulogic_vector(0 to 5); +signal a_eq_lm4_01_b , a_eq_lm4_23_b , a_eq_lm4_45_b :std_ulogic; +signal a_eq_lm4_u ,a_eq_lm4_v , a_eq_lm4_b :std_ulogic; + +signal a_eq_lm5_x :std_ulogic_vector(0 to 5); +signal a_eq_lm5_01_b , a_eq_lm5_23_b , a_eq_lm5_45_b :std_ulogic; +signal a_eq_lm5_u ,a_eq_lm5_v , a_eq_lm5_b :std_ulogic; + +signal a_eq_lm6_x :std_ulogic_vector(0 to 5); +signal a_eq_lm6_01_b , a_eq_lm6_23_b , a_eq_lm6_45_b :std_ulogic; +signal a_eq_lm6_u ,a_eq_lm6_v , a_eq_lm6_b :std_ulogic; + +signal a_eq_lm7_x :std_ulogic_vector(0 to 5); +signal a_eq_lm7_01_b , a_eq_lm7_23_b , a_eq_lm7_45_b :std_ulogic; +signal a_eq_lm7_u ,a_eq_lm7_v , a_eq_lm7_b :std_ulogic; + +signal a_eq_ex2_x :std_ulogic_vector(0 to 5); +signal a_eq_ex2_01_b , a_eq_ex2_23_b , a_eq_ex2_45_b :std_ulogic; +signal a_eq_ex2_u ,a_eq_ex2_v , a_eq_ex2_b :std_ulogic; + +signal a_eq_ex1_x :std_ulogic_vector(0 to 5); +signal a_eq_ex1_01_b , a_eq_ex1_23_b , a_eq_ex1_45_b :std_ulogic; +signal a_eq_ex1_u ,a_eq_ex1_v , a_eq_ex1_b :std_ulogic; + +signal a_eq_rf1_x :std_ulogic_vector(0 to 5); +signal a_eq_rf1_01_b , a_eq_rf1_23_b , a_eq_rf1_45_b :std_ulogic; +signal a_eq_rf1_u ,a_eq_rf1_v , a_eq_rf1_b :std_ulogic; + +signal a_eq_rf0_x :std_ulogic_vector(0 to 5); +signal a_eq_rf0_01_b , a_eq_rf0_23_b , a_eq_rf0_45_b :std_ulogic; +signal a_eq_rf0_u ,a_eq_rf0_v , a_eq_rf0_b :std_ulogic; + +signal a_eq_is2_x :std_ulogic_vector(0 to 5); +signal a_eq_is2_01_b , a_eq_is2_23_b , a_eq_is2_45_b :std_ulogic; +signal a_eq_is2_u ,a_eq_is2_v , a_eq_is2_b :std_ulogic; + +signal a_or_1_1 , a_or_1_2 , a_or_1_3 , a_or_1_4 :std_ulogic; +signal a_or_1_5 , a_or_1_6 :std_ulogic; +signal a_or_2_1_b , a_or_2_2_b , a_or_2_3_b :std_ulogic; +signal a_or_3_1 , a_or_4_b :std_ulogic; + + +signal a_group_en :std_ulogic; + +signal lm0_a_cmp_en :std_ulogic; +signal lm1_a_cmp_en :std_ulogic; +signal lm2_a_cmp_en :std_ulogic; +signal lm3_a_cmp_en :std_ulogic; +signal lm4_a_cmp_en :std_ulogic; +signal lm5_a_cmp_en :std_ulogic; +signal lm6_a_cmp_en :std_ulogic; +signal lm7_a_cmp_en :std_ulogic; + +signal is2_a_cmp_en :std_ulogic; +signal rf0_a_cmp_en :std_ulogic; +signal rf1_a_cmp_en :std_ulogic; +signal ex1_a_cmp_en :std_ulogic; +signal ex2_a_cmp_en :std_ulogic; + + + + + + + + + + + + + + + + + + + + +begin + + + + +ucmp_lm0adbufb: lm0_ad_buf_b(0 to 5) <= not lm0_ad(0 to 5); +ucmp_lm1adbufb: lm1_ad_buf_b(0 to 5) <= not lm1_ad(0 to 5); +ucmp_lm2adbufb: lm2_ad_buf_b(0 to 5) <= not lm2_ad(0 to 5); +ucmp_lm3adbufb: lm3_ad_buf_b(0 to 5) <= not lm3_ad(0 to 5); +ucmp_lm4adbufb: lm4_ad_buf_b(0 to 5) <= not lm4_ad(0 to 5); +ucmp_lm5adbufb: lm5_ad_buf_b(0 to 5) <= not lm5_ad(0 to 5); +ucmp_lm6adbufb: lm6_ad_buf_b(0 to 5) <= not lm6_ad(0 to 5); +ucmp_lm7adbufb: lm7_ad_buf_b(0 to 5) <= not lm7_ad(0 to 5); +ucmp_ex2adbufb: ex2_ad_buf_b(0 to 5) <= not ex2_ad(0 to 5); +ucmp_ex1adbufb: ex1_ad_buf_b(0 to 5) <= not ex1_ad(0 to 5); +ucmp_rf1adbufb: rf1_ad_buf_b(0 to 5) <= not rf1_ad(0 to 5); +ucmp_rf0adbufb: rf0_ad_buf_b(0 to 5) <= not rf0_ad(0 to 5); +ucmp_is2adbufb: is2_ad_buf_b(0 to 5) <= not is2_ad(0 to 5); +ucmp_is1adbuf0b: is1_ad_buf0_b(0 to 5) <= not is1_ad(0 to 5); +ucmp_is1adbuf1b: is1_ad_buf1_b(0 to 5) <= not is1_ad(0 to 5); +ucmp_is1adbuf2b: is1_ad_buf2_b(0 to 5) <= not is1_ad(0 to 5); + +ucmp_lm0adbuf: lm0_ad_buf(0 to 5) <= not lm0_ad_buf_b(0 to 5); +ucmp_lm1adbuf: lm1_ad_buf(0 to 5) <= not lm1_ad_buf_b(0 to 5); +ucmp_lm2adbuf: lm2_ad_buf(0 to 5) <= not lm2_ad_buf_b(0 to 5); +ucmp_lm3adbuf: lm3_ad_buf(0 to 5) <= not lm3_ad_buf_b(0 to 5); +ucmp_lm4adbuf: lm4_ad_buf(0 to 5) <= not lm4_ad_buf_b(0 to 5); +ucmp_lm5adbuf: lm5_ad_buf(0 to 5) <= not lm5_ad_buf_b(0 to 5); +ucmp_lm6adbuf: lm6_ad_buf(0 to 5) <= not lm6_ad_buf_b(0 to 5); +ucmp_lm7adbuf: lm7_ad_buf(0 to 5) <= not lm7_ad_buf_b(0 to 5); +ucmp_ex2adbuf: ex2_ad_buf(0 to 5) <= not ex2_ad_buf_b(0 to 5); +ucmp_ex1adbuf: ex1_ad_buf(0 to 5) <= not ex1_ad_buf_b(0 to 5); +ucmp_rf1adbuf: rf1_ad_buf(0 to 5) <= not rf1_ad_buf_b(0 to 5); +ucmp_rf0adbuf: rf0_ad_buf(0 to 5) <= not rf0_ad_buf_b(0 to 5); +ucmp_is2adbuf: is2_ad_buf(0 to 5) <= not is2_ad_buf_b(0 to 5); +ucmp_is1adbuf0: is1_ad_buf0(0 to 5) <= not is1_ad_buf0_b(0 to 5); +ucmp_is1adbuf1: is1_ad_buf1(0 to 5) <= not is1_ad_buf1_b(0 to 5); +ucmp_is1adbuf2: is1_ad_buf2(0 to 5) <= not is1_ad_buf2_b(0 to 5); + + + +ucmp_aeqis2_x: a_eq_is2_x(0 to 5) <= not( is2_ad_buf(0 to 5) xor is1_ad_buf0(0 to 5) ); +ucmp_aeqis2_01: a_eq_is2_01_b <= not( a_eq_is2_x(0) and a_eq_is2_x(1) ); +ucmp_aeqis2_23: a_eq_is2_23_b <= not( a_eq_is2_x(2) and a_eq_is2_x(3) ); +ucmp_aeqis2_45: a_eq_is2_45_b <= not( a_eq_is2_x(4) and a_eq_is2_x(5) ); +ucmp_aeqis2_u: a_eq_is2_u <= not( a_eq_is2_01_b or a_eq_is2_23_b ); +ucmp_aeqis2_w: a_eq_is2_v <= not( a_eq_is2_45_b ); +ucmp_aeqis2: a_eq_is2_b <= not( a_eq_is2_u and a_eq_is2_v and is2_a_cmp_en ); + +ucmp_aeqrf0_x: a_eq_rf0_x(0 to 5) <= not( rf0_ad_buf(0 to 5) xor is1_ad_buf0(0 to 5) ); +ucmp_aeqrf0_01: a_eq_rf0_01_b <= not( a_eq_rf0_x(0) and a_eq_rf0_x(1) ); +ucmp_aeqrf0_23: a_eq_rf0_23_b <= not( a_eq_rf0_x(2) and a_eq_rf0_x(3) ); +ucmp_aeqrf0_45: a_eq_rf0_45_b <= not( a_eq_rf0_x(4) and a_eq_rf0_x(5) ); +ucmp_aeqrf0_u: a_eq_rf0_u <= not( a_eq_rf0_01_b or a_eq_rf0_23_b ); +ucmp_aeqrf0_w: a_eq_rf0_v <= not( a_eq_rf0_45_b ); +ucmp_aeqrf0: a_eq_rf0_b <= not( a_eq_rf0_u and a_eq_rf0_v and rf0_a_cmp_en ); + +ucmp_aeqrf1_x: a_eq_rf1_x(0 to 5) <= not( rf1_ad_buf(0 to 5) xor is1_ad_buf0(0 to 5) ); +ucmp_aeqrf1_01: a_eq_rf1_01_b <= not( a_eq_rf1_x(0) and a_eq_rf1_x(1) ); +ucmp_aeqrf1_23: a_eq_rf1_23_b <= not( a_eq_rf1_x(2) and a_eq_rf1_x(3) ); +ucmp_aeqrf1_45: a_eq_rf1_45_b <= not( a_eq_rf1_x(4) and a_eq_rf1_x(5) ); +ucmp_aeqrf1_u: a_eq_rf1_u <= not( a_eq_rf1_01_b or a_eq_rf1_23_b ); +ucmp_aeqrf1_w: a_eq_rf1_v <= not( a_eq_rf1_45_b ); +ucmp_aeqrf1: a_eq_rf1_b <= not( a_eq_rf1_u and a_eq_rf1_v and rf1_a_cmp_en ); + +ucmp_aeqex1_x: a_eq_ex1_x(0 to 5) <= not( ex1_ad_buf(0 to 5) xor is1_ad_buf0(0 to 5) ); +ucmp_aeqex1_01: a_eq_ex1_01_b <= not( a_eq_ex1_x(0) and a_eq_ex1_x(1) ); +ucmp_aeqex1_23: a_eq_ex1_23_b <= not( a_eq_ex1_x(2) and a_eq_ex1_x(3) ); +ucmp_aeqex1_45: a_eq_ex1_45_b <= not( a_eq_ex1_x(4) and a_eq_ex1_x(5) ); +ucmp_aeqex1_u: a_eq_ex1_u <= not( a_eq_ex1_01_b or a_eq_ex1_23_b ); +ucmp_aeqex1_w: a_eq_ex1_v <= not( a_eq_ex1_45_b ); +ucmp_aeqex1: a_eq_ex1_b <= not( a_eq_ex1_u and a_eq_ex1_v and ex1_a_cmp_en ); + +ucmp_aeqex2_x: a_eq_ex2_x(0 to 5) <= not( ex2_ad_buf(0 to 5) xor is1_ad_buf0(0 to 5) ); +ucmp_aeqex2_01: a_eq_ex2_01_b <= not( a_eq_ex2_x(0) and a_eq_ex2_x(1) ); +ucmp_aeqex2_23: a_eq_ex2_23_b <= not( a_eq_ex2_x(2) and a_eq_ex2_x(3) ); +ucmp_aeqex2_45: a_eq_ex2_45_b <= not( a_eq_ex2_x(4) and a_eq_ex2_x(5) ); +ucmp_aeqex2_u: a_eq_ex2_u <= not( a_eq_ex2_01_b or a_eq_ex2_23_b ); +ucmp_aeqex2_w: a_eq_ex2_v <= not( a_eq_ex2_45_b ); +ucmp_aeqex2: a_eq_ex2_b <= not( a_eq_ex2_u and a_eq_ex2_v and ex2_a_cmp_en ); + +ucmp_aeqlm0_x: a_eq_lm0_x(0 to 5) <= not( lm0_ad_buf(0 to 5) xor is1_ad_buf1(0 to 5) ); +ucmp_aeqlm0_01: a_eq_lm0_01_b <= not( a_eq_lm0_x(0) and a_eq_lm0_x(1) ); +ucmp_aeqlm0_23: a_eq_lm0_23_b <= not( a_eq_lm0_x(2) and a_eq_lm0_x(3) ); +ucmp_aeqlm0_45: a_eq_lm0_45_b <= not( a_eq_lm0_x(4) and a_eq_lm0_x(5) ); +ucmp_aeqlm0_u: a_eq_lm0_u <= not( a_eq_lm0_01_b or a_eq_lm0_23_b ); +ucmp_aeqlm0_w: a_eq_lm0_v <= not( a_eq_lm0_45_b ); +ucmp_aeqlm0: a_eq_lm0_b <= not( a_eq_lm0_u and a_eq_lm0_v and lm0_a_cmp_en ); + +ucmp_aeqlm1_x: a_eq_lm1_x(0 to 5) <= not( lm1_ad_buf(0 to 5) xor is1_ad_buf1(0 to 5) ); +ucmp_aeqlm1_01: a_eq_lm1_01_b <= not( a_eq_lm1_x(0) and a_eq_lm1_x(1) ); +ucmp_aeqlm1_23: a_eq_lm1_23_b <= not( a_eq_lm1_x(2) and a_eq_lm1_x(3) ); +ucmp_aeqlm1_45: a_eq_lm1_45_b <= not( a_eq_lm1_x(4) and a_eq_lm1_x(5) ); +ucmp_aeqlm1_u: a_eq_lm1_u <= not( a_eq_lm1_01_b or a_eq_lm1_23_b ); +ucmp_aeqlm1_w: a_eq_lm1_v <= not( a_eq_lm1_45_b ); +ucmp_aeqlm1: a_eq_lm1_b <= not( a_eq_lm1_u and a_eq_lm1_v and lm1_a_cmp_en ); + +ucmp_aeqlm2_x: a_eq_lm2_x(0 to 5) <= not( lm2_ad_buf(0 to 5) xor is1_ad_buf1(0 to 5) ); +ucmp_aeqlm2_01: a_eq_lm2_01_b <= not( a_eq_lm2_x(0) and a_eq_lm2_x(1) ); +ucmp_aeqlm2_23: a_eq_lm2_23_b <= not( a_eq_lm2_x(2) and a_eq_lm2_x(3) ); +ucmp_aeqlm2_45: a_eq_lm2_45_b <= not( a_eq_lm2_x(4) and a_eq_lm2_x(5) ); +ucmp_aeqlm2_u: a_eq_lm2_u <= not( a_eq_lm2_01_b or a_eq_lm2_23_b ); +ucmp_aeqlm2_w: a_eq_lm2_v <= not( a_eq_lm2_45_b ); +ucmp_aeqlm2: a_eq_lm2_b <= not( a_eq_lm2_u and a_eq_lm2_v and lm2_a_cmp_en ); + +ucmp_aeqlm3_x: a_eq_lm3_x(0 to 5) <= not( lm3_ad_buf(0 to 5) xor is1_ad_buf1(0 to 5) ); +ucmp_aeqlm3_01: a_eq_lm3_01_b <= not( a_eq_lm3_x(0) and a_eq_lm3_x(1) ); +ucmp_aeqlm3_23: a_eq_lm3_23_b <= not( a_eq_lm3_x(2) and a_eq_lm3_x(3) ); +ucmp_aeqlm3_45: a_eq_lm3_45_b <= not( a_eq_lm3_x(4) and a_eq_lm3_x(5) ); +ucmp_aeqlm3_u: a_eq_lm3_u <= not( a_eq_lm3_01_b or a_eq_lm3_23_b ); +ucmp_aeqlm3_w: a_eq_lm3_v <= not( a_eq_lm3_45_b ); +ucmp_aeqlm3: a_eq_lm3_b <= not( a_eq_lm3_u and a_eq_lm3_v and lm3_a_cmp_en ); + +ucmp_aeqlm4_x: a_eq_lm4_x(0 to 5) <= not( lm4_ad_buf(0 to 5) xor is1_ad_buf2(0 to 5) ); +ucmp_aeqlm4_01: a_eq_lm4_01_b <= not( a_eq_lm4_x(0) and a_eq_lm4_x(1) ); +ucmp_aeqlm4_23: a_eq_lm4_23_b <= not( a_eq_lm4_x(2) and a_eq_lm4_x(3) ); +ucmp_aeqlm4_45: a_eq_lm4_45_b <= not( a_eq_lm4_x(4) and a_eq_lm4_x(5) ); +ucmp_aeqlm4_u: a_eq_lm4_u <= not( a_eq_lm4_01_b or a_eq_lm4_23_b ); +ucmp_aeqlm4_w: a_eq_lm4_v <= not( a_eq_lm4_45_b ); +ucmp_aeqlm4: a_eq_lm4_b <= not( a_eq_lm4_u and a_eq_lm4_v and lm4_a_cmp_en ); + +ucmp_aeqlm5_x: a_eq_lm5_x(0 to 5) <= not( lm5_ad_buf(0 to 5) xor is1_ad_buf2(0 to 5) ); +ucmp_aeqlm5_01: a_eq_lm5_01_b <= not( a_eq_lm5_x(0) and a_eq_lm5_x(1) ); +ucmp_aeqlm5_23: a_eq_lm5_23_b <= not( a_eq_lm5_x(2) and a_eq_lm5_x(3) ); +ucmp_aeqlm5_45: a_eq_lm5_45_b <= not( a_eq_lm5_x(4) and a_eq_lm5_x(5) ); +ucmp_aeqlm5_u: a_eq_lm5_u <= not( a_eq_lm5_01_b or a_eq_lm5_23_b ); +ucmp_aeqlm5_w: a_eq_lm5_v <= not( a_eq_lm5_45_b ); +ucmp_aeqlm5: a_eq_lm5_b <= not( a_eq_lm5_u and a_eq_lm5_v and lm5_a_cmp_en ); + +ucmp_aeqlm6_x: a_eq_lm6_x(0 to 5) <= not( lm6_ad_buf(0 to 5) xor is1_ad_buf2(0 to 5) ); +ucmp_aeqlm6_01: a_eq_lm6_01_b <= not( a_eq_lm6_x(0) and a_eq_lm6_x(1) ); +ucmp_aeqlm6_23: a_eq_lm6_23_b <= not( a_eq_lm6_x(2) and a_eq_lm6_x(3) ); +ucmp_aeqlm6_45: a_eq_lm6_45_b <= not( a_eq_lm6_x(4) and a_eq_lm6_x(5) ); +ucmp_aeqlm6_u: a_eq_lm6_u <= not( a_eq_lm6_01_b or a_eq_lm6_23_b ); +ucmp_aeqlm6_w: a_eq_lm6_v <= not( a_eq_lm6_45_b ); +ucmp_aeqlm6: a_eq_lm6_b <= not( a_eq_lm6_u and a_eq_lm6_v and lm6_a_cmp_en ); + +ucmp_aeqlm7_x: a_eq_lm7_x(0 to 5) <= not( lm7_ad_buf(0 to 5) xor is1_ad_buf2(0 to 5) ); +ucmp_aeqlm7_01: a_eq_lm7_01_b <= not( a_eq_lm7_x(0) and a_eq_lm7_x(1) ); +ucmp_aeqlm7_23: a_eq_lm7_23_b <= not( a_eq_lm7_x(2) and a_eq_lm7_x(3) ); +ucmp_aeqlm7_45: a_eq_lm7_45_b <= not( a_eq_lm7_x(4) and a_eq_lm7_x(5) ); +ucmp_aeqlm7_u: a_eq_lm7_u <= not( a_eq_lm7_01_b or a_eq_lm7_23_b ); +ucmp_aeqlm7_w: a_eq_lm7_v <= not( a_eq_lm7_45_b ); +ucmp_aeqlm7: a_eq_lm7_b <= not( a_eq_lm7_u and a_eq_lm7_v and lm7_a_cmp_en ); + + + +ucmp_aor11: a_or_1_1 <= not( a_eq_lm0_b and a_eq_lm1_b ); +ucmp_aor12: a_or_1_2 <= not( a_eq_lm2_b and a_eq_lm3_b ); +ucmp_aor13: a_or_1_3 <= not( a_eq_lm4_b and a_eq_lm5_b ); +ucmp_aor14: a_or_1_4 <= not( a_eq_lm6_b and a_eq_lm7_b ); +ucmp_aor15: a_or_1_5 <= not( a_eq_ex2_b and a_eq_ex1_b ); +ucmp_aor16: a_or_1_6 <= not( a_eq_rf1_b and a_eq_rf0_b and a_eq_is2_b ); + +ucmp_aor21: a_or_2_1_b <= not( a_or_1_1 or a_or_1_2 ); +ucmp_aor22: a_or_2_2_b <= not( a_or_1_3 or a_or_1_4 ); +ucmp_aor23: a_or_2_3_b <= not( a_or_1_5 or a_or_1_6 ); + +ucmp_aor31: a_or_3_1 <= not( a_or_2_1_b and a_or_2_2_b and a_or_2_3_b ); + +ucmp_aor4: a_or_4_b <= not( a_group_en and a_or_3_1); + + + + +a_group_en <= is1_v; + +lm0_a_cmp_en <= lm0_v; +lm1_a_cmp_en <= lm1_v; +lm2_a_cmp_en <= lm2_v; +lm3_a_cmp_en <= lm3_v; +lm4_a_cmp_en <= lm4_v; +lm5_a_cmp_en <= lm5_v; +lm6_a_cmp_en <= lm6_v; +lm7_a_cmp_en <= lm7_v; +is2_a_cmp_en <= is2_v; +rf0_a_cmp_en <= rf0_v; +rf1_a_cmp_en <= rf1_v; +ex1_a_cmp_en <= ex1_v; +ex2_a_cmp_en <= ex2_v; + +ad_hit_b <= a_or_4_b; + + +end iuq_fxu_dep_cmp; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_fxu_issue.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_fxu_issue.vhdl new file mode 100644 index 0000000..7a24b74 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_fxu_issue.vhdl @@ -0,0 +1,1904 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee, ibm; +use ieee.std_logic_1164.all; +use ibm.std_ulogic_unsigned.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +library support; +use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; +library work; +use work.iuq_pkg.all; + +entity iuq_fxu_issue is + generic(expand_type : integer := 2 ); +port(vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + pc_iu_sg_2 : in std_ulogic; + pc_iu_func_sl_thold_2 : in std_ulogic; + clkoff_b : in std_ulogic; + an_ac_scan_dis_dc_b : in std_ulogic; + tc_ac_ccflush_dc : in std_ulogic; + delay_lclkr : in std_ulogic; + mpw1_b : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + fiss_dbg_data : out std_ulogic_vector(0 to 87); + pc_iu_trace_bus_enable : in std_ulogic; + + pc_iu_event_bus_enable : in std_ulogic; + fiss_perf_event_t0 : out std_ulogic_vector(0 to 7); + fiss_perf_event_t1 : out std_ulogic_vector(0 to 7); + fiss_perf_event_t2 : out std_ulogic_vector(0 to 7); + fiss_perf_event_t3 : out std_ulogic_vector(0 to 7); + + xu_iu_need_hole : in std_ulogic; + xu_iu_xucr0_rel : in std_ulogic; + + an_ac_reld_data_vld : in std_ulogic; + an_ac_reld_core_tag : in std_ulogic_vector(1 to 4); + an_ac_reld_ditc : in std_ulogic; + an_ac_reld_data_coming : in std_ulogic; + an_ac_back_inv : in std_ulogic; + an_ac_back_inv_target : in std_ulogic; + + fiss_uc_is2_ucode_vld : out std_ulogic; + + + fdep_fiss_t0_is2_instr : in std_ulogic_vector(0 to 31); + fdep_fiss_t0_is2_ta_vld : in std_ulogic; + fdep_fiss_t0_is2_ta : in std_ulogic_vector(0 to 5); + fdep_fiss_t0_is2_s1_vld : in std_ulogic; + fdep_fiss_t0_is2_s1 : in std_ulogic_vector(0 to 5); + fdep_fiss_t0_is2_s2_vld : in std_ulogic; + fdep_fiss_t0_is2_s2 : in std_ulogic_vector(0 to 5); + fdep_fiss_t0_is2_s3_vld : in std_ulogic; + fdep_fiss_t0_is2_s3 : in std_ulogic_vector(0 to 5); + fdep_fiss_t0_is2_pred_update : in std_ulogic; + fdep_fiss_t0_is2_pred_taken_cnt : in std_ulogic_vector(0 to 1); + fdep_fiss_t0_is2_gshare : in std_ulogic_vector(0 to 3); + fdep_fiss_t0_is2_ifar : in eff_ifar; + fdep_fiss_t0_is2_error : in std_ulogic_vector(0 to 2); + fdep_fiss_t0_is2_axu_ld_or_st : in std_ulogic; + fdep_fiss_t0_is2_axu_store : in std_ulogic; + fdep_fiss_t0_is2_axu_ldst_indexed : in std_ulogic; + fdep_fiss_t0_is2_axu_ldst_tag : in std_ulogic_vector(0 to 8); + fdep_fiss_t0_is2_axu_ldst_size : in std_ulogic_vector(0 to 5); + fdep_fiss_t0_is2_axu_ldst_update : in std_ulogic; + fdep_fiss_t0_is2_axu_ldst_extpid : in std_ulogic; + fdep_fiss_t0_is2_axu_ldst_forcealign : in std_ulogic; + fdep_fiss_t0_is2_axu_ldst_forceexcept : in std_ulogic; + fdep_fiss_t0_is2_axu_mftgpr : in std_ulogic; + fdep_fiss_t0_is2_axu_mffgpr : in std_ulogic; + fdep_fiss_t0_is2_axu_movedp : in std_ulogic; + fdep_fiss_t0_is2_axu_instr_type : in std_ulogic_vector(0 to 2); + fdep_fiss_t0_is2_match : in std_ulogic; + fdep_fiss_t0_is2_2ucode : in std_ulogic; + fdep_fiss_t0_is2_2ucode_type : in std_ulogic; + fdep_fiss_t0_is2_hole_delay : in std_ulogic_vector(0 to 2); + fdep_fiss_t0_is2_to_ucode : in std_ulogic; + fdep_fiss_t0_is2_is_ucode : in std_ulogic; + fdep_fiss_t0_is2early_vld : in std_ulogic; + fdep_fiss_t0_is1_xu_dep_hit_b : in std_ulogic; + fdep_fiss_t1_is2_instr : in std_ulogic_vector(0 to 31); + fdep_fiss_t1_is2_ta_vld : in std_ulogic; + fdep_fiss_t1_is2_ta : in std_ulogic_vector(0 to 5); + fdep_fiss_t1_is2_s1_vld : in std_ulogic; + fdep_fiss_t1_is2_s1 : in std_ulogic_vector(0 to 5); + fdep_fiss_t1_is2_s2_vld : in std_ulogic; + fdep_fiss_t1_is2_s2 : in std_ulogic_vector(0 to 5); + fdep_fiss_t1_is2_s3_vld : in std_ulogic; + fdep_fiss_t1_is2_s3 : in std_ulogic_vector(0 to 5); + fdep_fiss_t1_is2_pred_update : in std_ulogic; + fdep_fiss_t1_is2_pred_taken_cnt : in std_ulogic_vector(0 to 1); + fdep_fiss_t1_is2_gshare : in std_ulogic_vector(0 to 3); + fdep_fiss_t1_is2_ifar : in eff_ifar; + fdep_fiss_t1_is2_error : in std_ulogic_vector(0 to 2); + fdep_fiss_t1_is2_axu_ld_or_st : in std_ulogic; + fdep_fiss_t1_is2_axu_store : in std_ulogic; + fdep_fiss_t1_is2_axu_ldst_indexed : in std_ulogic; + fdep_fiss_t1_is2_axu_ldst_tag : in std_ulogic_vector(0 to 8); + fdep_fiss_t1_is2_axu_ldst_size : in std_ulogic_vector(0 to 5); + fdep_fiss_t1_is2_axu_ldst_update : in std_ulogic; + fdep_fiss_t1_is2_axu_ldst_extpid : in std_ulogic; + fdep_fiss_t1_is2_axu_ldst_forcealign : in std_ulogic; + fdep_fiss_t1_is2_axu_ldst_forceexcept : in std_ulogic; + fdep_fiss_t1_is2_axu_mftgpr : in std_ulogic; + fdep_fiss_t1_is2_axu_mffgpr : in std_ulogic; + fdep_fiss_t1_is2_axu_movedp : in std_ulogic; + fdep_fiss_t1_is2_axu_instr_type : in std_ulogic_vector(0 to 2); + fdep_fiss_t1_is2_match : in std_ulogic; + fdep_fiss_t1_is2_2ucode : in std_ulogic; + fdep_fiss_t1_is2_2ucode_type : in std_ulogic; + fdep_fiss_t1_is2_hole_delay : in std_ulogic_vector(0 to 2); + fdep_fiss_t1_is2_to_ucode : in std_ulogic; + fdep_fiss_t1_is2_is_ucode : in std_ulogic; + fdep_fiss_t1_is2early_vld : in std_ulogic; + fdep_fiss_t1_is1_xu_dep_hit_b : in std_ulogic; + fdep_fiss_t2_is2_instr : in std_ulogic_vector(0 to 31); + fdep_fiss_t2_is2_ta_vld : in std_ulogic; + fdep_fiss_t2_is2_ta : in std_ulogic_vector(0 to 5); + fdep_fiss_t2_is2_s1_vld : in std_ulogic; + fdep_fiss_t2_is2_s1 : in std_ulogic_vector(0 to 5); + fdep_fiss_t2_is2_s2_vld : in std_ulogic; + fdep_fiss_t2_is2_s2 : in std_ulogic_vector(0 to 5); + fdep_fiss_t2_is2_s3_vld : in std_ulogic; + fdep_fiss_t2_is2_s3 : in std_ulogic_vector(0 to 5); + fdep_fiss_t2_is2_pred_update : in std_ulogic; + fdep_fiss_t2_is2_pred_taken_cnt : in std_ulogic_vector(0 to 1); + fdep_fiss_t2_is2_gshare : in std_ulogic_vector(0 to 3); + fdep_fiss_t2_is2_ifar : in eff_ifar; + fdep_fiss_t2_is2_error : in std_ulogic_vector(0 to 2); + fdep_fiss_t2_is2_axu_ld_or_st : in std_ulogic; + fdep_fiss_t2_is2_axu_store : in std_ulogic; + fdep_fiss_t2_is2_axu_ldst_indexed : in std_ulogic; + fdep_fiss_t2_is2_axu_ldst_tag : in std_ulogic_vector(0 to 8); + fdep_fiss_t2_is2_axu_ldst_size : in std_ulogic_vector(0 to 5); + fdep_fiss_t2_is2_axu_ldst_update : in std_ulogic; + fdep_fiss_t2_is2_axu_ldst_extpid : in std_ulogic; + fdep_fiss_t2_is2_axu_ldst_forcealign : in std_ulogic; + fdep_fiss_t2_is2_axu_ldst_forceexcept : in std_ulogic; + fdep_fiss_t2_is2_axu_mftgpr : in std_ulogic; + fdep_fiss_t2_is2_axu_mffgpr : in std_ulogic; + fdep_fiss_t2_is2_axu_movedp : in std_ulogic; + fdep_fiss_t2_is2_axu_instr_type : in std_ulogic_vector(0 to 2); + fdep_fiss_t2_is2_match : in std_ulogic; + fdep_fiss_t2_is2_2ucode : in std_ulogic; + fdep_fiss_t2_is2_2ucode_type : in std_ulogic; + fdep_fiss_t2_is2_hole_delay : in std_ulogic_vector(0 to 2); + fdep_fiss_t2_is2_to_ucode : in std_ulogic; + fdep_fiss_t2_is2_is_ucode : in std_ulogic; + fdep_fiss_t2_is2early_vld : in std_ulogic; + fdep_fiss_t2_is1_xu_dep_hit_b : in std_ulogic; + fdep_fiss_t3_is2_instr : in std_ulogic_vector(0 to 31); + fdep_fiss_t3_is2_ta_vld : in std_ulogic; + fdep_fiss_t3_is2_ta : in std_ulogic_vector(0 to 5); + fdep_fiss_t3_is2_s1_vld : in std_ulogic; + fdep_fiss_t3_is2_s1 : in std_ulogic_vector(0 to 5); + fdep_fiss_t3_is2_s2_vld : in std_ulogic; + fdep_fiss_t3_is2_s2 : in std_ulogic_vector(0 to 5); + fdep_fiss_t3_is2_s3_vld : in std_ulogic; + fdep_fiss_t3_is2_s3 : in std_ulogic_vector(0 to 5); + fdep_fiss_t3_is2_pred_update : in std_ulogic; + fdep_fiss_t3_is2_pred_taken_cnt : in std_ulogic_vector(0 to 1); + fdep_fiss_t3_is2_gshare : in std_ulogic_vector(0 to 3); + fdep_fiss_t3_is2_ifar : in eff_ifar; + fdep_fiss_t3_is2_error : in std_ulogic_vector(0 to 2); + fdep_fiss_t3_is2_axu_ld_or_st : in std_ulogic; + fdep_fiss_t3_is2_axu_store : in std_ulogic; + fdep_fiss_t3_is2_axu_ldst_indexed : in std_ulogic; + fdep_fiss_t3_is2_axu_ldst_tag : in std_ulogic_vector(0 to 8); + fdep_fiss_t3_is2_axu_ldst_size : in std_ulogic_vector(0 to 5); + fdep_fiss_t3_is2_axu_ldst_update : in std_ulogic; + fdep_fiss_t3_is2_axu_ldst_extpid : in std_ulogic; + fdep_fiss_t3_is2_axu_ldst_forcealign : in std_ulogic; + fdep_fiss_t3_is2_axu_ldst_forceexcept : in std_ulogic; + fdep_fiss_t3_is2_axu_mftgpr : in std_ulogic; + fdep_fiss_t3_is2_axu_mffgpr : in std_ulogic; + fdep_fiss_t3_is2_axu_movedp : in std_ulogic; + fdep_fiss_t3_is2_axu_instr_type : in std_ulogic_vector(0 to 2); + fdep_fiss_t3_is2_match : in std_ulogic; + fdep_fiss_t3_is2_2ucode : in std_ulogic; + fdep_fiss_t3_is2_2ucode_type : in std_ulogic; + fdep_fiss_t3_is2_hole_delay : in std_ulogic_vector(0 to 2); + fdep_fiss_t3_is2_to_ucode : in std_ulogic; + fdep_fiss_t3_is2_is_ucode : in std_ulogic; + fdep_fiss_t3_is2early_vld : in std_ulogic; + fdep_fiss_t3_is1_xu_dep_hit_b : in std_ulogic; + + fiss_fdep_is2_take0 : out std_ulogic; + fiss_fdep_is2_take1 : out std_ulogic; + fiss_fdep_is2_take2 : out std_ulogic; + fiss_fdep_is2_take3 : out std_ulogic; + + spr_issue_high_mask : in std_ulogic_vector(0 to 3); + spr_issue_med_mask : in std_ulogic_vector(0 to 3); + spr_fiss_count0_max : in std_ulogic_vector(0 to 5); + spr_fiss_count1_max : in std_ulogic_vector(0 to 5); + spr_fiss_count2_max : in std_ulogic_vector(0 to 5); + spr_fiss_count3_max : in std_ulogic_vector(0 to 5); + + spr_fiss_pri_rand : in std_ulogic_vector(0 to 4); + spr_fiss_pri_rand_always : in std_ulogic; + spr_fiss_pri_rand_flush : in std_ulogic; + + iu_au_hi_pri_mask : out std_ulogic_vector(0 to 3); + iu_au_md_pri_mask : out std_ulogic_vector(0 to 3); + i_afi_is2_take_t : in std_ulogic_vector(0 to 3); + i_afd_is2_t0_instr_v : in std_ulogic; + i_afd_is2_t1_instr_v : in std_ulogic; + i_afd_is2_t2_instr_v : in std_ulogic; + i_afd_is2_t3_instr_v : in std_ulogic; + i_axu_is1_dep_hit_t0_b : in std_ulogic; + i_axu_is1_dep_hit_t1_b : in std_ulogic; + i_axu_is1_dep_hit_t2_b : in std_ulogic; + i_axu_is1_dep_hit_t3_b : in std_ulogic; + + xu_iu_is2_flush_tid : in std_ulogic_vector(0 to 3); + xu_iu_rf0_flush_tid : in std_ulogic_vector(0 to 3); + xu_iu_rf1_flush_tid : in std_ulogic_vector(0 to 3); + xu_iu_ex1_flush_tid : in std_ulogic_vector(0 to 3); + xu_iu_ex2_flush_tid : in std_ulogic_vector(0 to 3); + xu_iu_ex3_flush_tid : in std_ulogic_vector(0 to 3); + xu_iu_ex4_flush_tid : in std_ulogic_vector(0 to 3); + xu_iu_ex5_flush_tid : in std_ulogic_vector(0 to 3); + xu_iu_ex5_ppc_cpl : in std_ulogic_vector(0 to 3); + + iu_xu_is2_vld : out std_ulogic; + iu_xu_is2_tid : out std_ulogic_vector(0 to 3); + iu_xu_is2_instr : out std_ulogic_vector(0 to 31); + iu_xu_is2_ta_vld : out std_ulogic; + iu_xu_is2_ta : out std_ulogic_vector(0 to 5); + iu_xu_is2_s1_vld : out std_ulogic; + iu_xu_is2_s1 : out std_ulogic_vector(0 to 5); + iu_xu_is2_s2_vld : out std_ulogic; + iu_xu_is2_s2 : out std_ulogic_vector(0 to 5); + iu_xu_is2_s3_vld : out std_ulogic; + iu_xu_is2_s3 : out std_ulogic_vector(0 to 5); + iu_xu_is2_pred_update : out std_ulogic; + iu_xu_is2_pred_taken_cnt : out std_ulogic_vector(0 to 1); + iu_xu_is2_gshare : out std_ulogic_vector(0 to 3); + iu_xu_is2_ifar : out eff_ifar; + iu_xu_is2_error : out std_ulogic_vector(0 to 2); + iu_xu_is2_is_ucode : out std_ulogic; + iu_xu_is2_axu_ld_or_st : out std_ulogic; + iu_xu_is2_axu_store : out std_ulogic; + iu_xu_is2_axu_ldst_indexed : out std_ulogic; + iu_xu_is2_axu_ldst_tag : out std_ulogic_vector(0 to 8); + iu_xu_is2_axu_ldst_size : out std_ulogic_vector(0 to 5); + iu_xu_is2_axu_ldst_update : out std_ulogic; + iu_xu_is2_axu_ldst_extpid : out std_ulogic; + iu_xu_is2_axu_ldst_forcealign : out std_ulogic; + iu_xu_is2_axu_ldst_forceexcept : out std_ulogic; + iu_xu_is2_axu_mftgpr : out std_ulogic; + iu_xu_is2_axu_mffgpr : out std_ulogic; + iu_xu_is2_axu_movedp : out std_ulogic; + iu_xu_is2_axu_instr_type : out std_ulogic_vector(0 to 2); + iu_xu_is2_match : out std_ulogic; + fiss_uc_is2_2ucode : out std_ulogic; + fiss_uc_is2_2ucode_type : out std_ulogic; + iu_fu_rf0_str_val : out std_ulogic; + iu_fu_rf0_ldst_val : out std_ulogic; + iu_fu_rf0_ldst_tid : out std_ulogic_vector(0 to 1); + iu_fu_rf0_ldst_tag : out std_ulogic_vector(0 to 8)); +-- synopsys translate_off +-- synopsys translate_on +end iuq_fxu_issue; +ARCHITECTURE IUQ_FXU_ISSUE + OF IUQ_FXU_ISSUE + IS +constant uc_flush_tid_offset : natural := 0; +constant xu_iu_need_hole_offset : natural := uc_flush_tid_offset + 4; +constant xu_iu_xucr0_rel_offset : natural := xu_iu_need_hole_offset + 1; +constant an_ac_back_inv_offset : natural := xu_iu_xucr0_rel_offset + 1; +constant an_ac_back_inv_target_offset : natural := an_ac_back_inv_offset + 1; +constant gap_l2_rel_hole_dly1_offset : natural := an_ac_back_inv_target_offset + 1; +constant gap_l2_rel_hole_dly2_offset : natural := gap_l2_rel_hole_dly1_offset + 1; +constant gap_l2_tag_dly1_offset : natural := gap_l2_rel_hole_dly2_offset + 1; +constant gap_l2_tag_dly2_offset : natural := gap_l2_tag_dly1_offset + 3; +constant low_pri_rf0_offset : natural := gap_l2_tag_dly2_offset + 3; +constant low_pri_rf1_offset : natural := low_pri_rf0_offset + 4; +constant low_pri_ex1_offset : natural := low_pri_rf1_offset + 4; +constant low_pri_ex2_offset : natural := low_pri_ex1_offset + 4; +constant low_pri_ex3_offset : natural := low_pri_ex2_offset + 4; +constant low_pri_ex4_offset : natural := low_pri_ex3_offset + 4; +constant low_pri_ex5_offset : natural := low_pri_ex4_offset + 4; +constant low_pri_ex6_offset : natural := low_pri_ex5_offset + 4; +constant xu_iu_ex6_ppc_cpl_offset: natural := low_pri_ex6_offset + 4; +constant low_pri_counter0_offset: natural := xu_iu_ex6_ppc_cpl_offset + 4; +constant low_pri_counter1_offset: natural := low_pri_counter0_offset + 8; +constant low_pri_counter2_offset: natural := low_pri_counter1_offset + 8; +constant low_pri_counter3_offset: natural := low_pri_counter2_offset + 8; +constant low_pri_max0_offset : natural := low_pri_counter3_offset + 8; +constant low_pri_max1_offset : natural := low_pri_max0_offset + 6; +constant low_pri_max2_offset : natural := low_pri_max1_offset + 6; +constant low_pri_max3_offset : natural := low_pri_max2_offset + 6; +constant high_pri_mask_offset : natural := low_pri_max3_offset + 6; +constant med_pri_mask_offset : natural := high_pri_mask_offset + 4; +constant spr_high_mask_offset : natural := med_pri_mask_offset + 4; +constant spr_med_mask_offset : natural := spr_high_mask_offset + 4; +constant hole_delay0_offset : natural := spr_med_mask_offset + 4; +constant hole_delay1_offset : natural := hole_delay0_offset + 2; +constant hole_delay2_offset : natural := hole_delay1_offset + 2; +constant hole_delay3_offset : natural := hole_delay2_offset + 2; +constant is2_vld_offset : natural := hole_delay3_offset + 2; +constant perf_event_offset : natural := is2_vld_offset + 4; +constant fiss_dbg_data_offset : natural := perf_event_offset + 32; +constant rf0_str_val_offset : natural := fiss_dbg_data_offset + 44; +constant rf0_ldst_val_offset : natural := rf0_str_val_offset + 1; +constant rf0_ldst_tid_offset : natural := rf0_ldst_val_offset + 1; +constant rf0_ldst_tag_offset : natural := rf0_ldst_tid_offset + 2; +constant rf0_took_offset : natural := rf0_ldst_tag_offset + 9; +constant spare_offset : natural := rf0_took_offset + 12; +constant trace_bus_enable_offset : natural := spare_offset + 4; +constant event_bus_enable_offset : natural := trace_bus_enable_offset + 1; +constant scan_right : natural := event_bus_enable_offset + 1 - 1; +signal act_dis : std_ulogic; +signal d_mode : std_ulogic; +signal mpw2_b : std_ulogic; +signal spare_l2 : std_ulogic_vector(0 to 3); +signal trace_bus_enable_d : std_ulogic; +signal trace_bus_enable_q : std_ulogic; +signal event_bus_enable_d : std_ulogic; +signal event_bus_enable_q : std_ulogic; +signal siv : std_ulogic_vector(0 to scan_right); +signal sov : std_ulogic_vector(0 to scan_right); +signal tiup : std_ulogic; +signal pc_iu_func_sl_thold_1 : std_ulogic; +signal pc_iu_func_sl_thold_0 : std_ulogic; +signal pc_iu_func_sl_thold_0_b : std_ulogic; +signal pc_iu_sg_1 : std_ulogic; +signal pc_iu_sg_0 : std_ulogic; +signal forcee : std_ulogic; +signal xu_iu_need_hole_d : std_ulogic; +signal xu_iu_need_hole_l2 : std_ulogic; +signal xu_iu_xucr0_rel_d : std_ulogic; +signal xu_iu_xucr0_rel_l2 : std_ulogic; +signal an_ac_back_inv_d : std_ulogic; +signal an_ac_back_inv_l2 : std_ulogic; +signal an_ac_back_inv_target_d : std_ulogic; +signal an_ac_back_inv_target_l2 : std_ulogic; +signal gap_l2_rel_hole_dly1_d : std_ulogic; +signal gap_l2_rel_hole_dly1_l2 : std_ulogic; +signal gap_l2_rel_hole_dly2_d : std_ulogic; +signal gap_l2_rel_hole_dly2_l2 : std_ulogic; +signal gap_l2_tag_dly1_d : std_ulogic_vector(2 to 4); +signal gap_l2_tag_dly1_l2 : std_ulogic_vector(2 to 4); +signal gap_l2_tag_dly2_d : std_ulogic_vector(2 to 4); +signal gap_l2_tag_dly2_l2 : std_ulogic_vector(2 to 4); +signal need_hole : std_ulogic; +signal gap_l2_rel_hole : std_ulogic; +signal dcache_rel_hole : std_ulogic; +signal dcache_rel_tag_2nd_beat : std_ulogic; +signal dcache_binv_hole : std_ulogic; +signal is2_vld_d : std_ulogic_vector(0 to 3); +signal hole_delay0_d : std_ulogic_vector(0 to 1); +signal hole_delay1_d : std_ulogic_vector(0 to 1); +signal hole_delay2_d : std_ulogic_vector(0 to 1); +signal hole_delay3_d : std_ulogic_vector(0 to 1); +signal is2_vld_l2 : std_ulogic_vector(0 to 3); +signal hole_delay0_l2 : std_ulogic_vector(0 to 1); +signal hole_delay1_l2 : std_ulogic_vector(0 to 1); +signal hole_delay2_l2 : std_ulogic_vector(0 to 1); +signal hole_delay3_l2 : std_ulogic_vector(0 to 1); +signal hole0 : std_ulogic; +signal hole1 : std_ulogic; +signal hole2 : std_ulogic; +signal hole3 : std_ulogic; +signal hole0_b : std_ulogic; +signal hole1_b : std_ulogic; +signal hole2_b : std_ulogic; +signal hole3_b : std_ulogic; +signal low_pri_rf0_d : std_ulogic_vector(0 to 3); +signal low_pri_rf1_d : std_ulogic_vector(0 to 3); +signal low_pri_ex1_d : std_ulogic_vector(0 to 3); +signal low_pri_ex2_d : std_ulogic_vector(0 to 3); +signal low_pri_ex3_d : std_ulogic_vector(0 to 3); +signal low_pri_ex4_d : std_ulogic_vector(0 to 3); +signal low_pri_ex5_d : std_ulogic_vector(0 to 3); +signal low_pri_ex6_d : std_ulogic_vector(0 to 3); +signal xu_iu_ex6_ppc_cpl_d : std_ulogic_vector(0 to 3); +signal low_pri_counter0_d : std_ulogic_vector(0 to 7); +signal low_pri_counter1_d : std_ulogic_vector(0 to 7); +signal low_pri_counter2_d : std_ulogic_vector(0 to 7); +signal low_pri_counter3_d : std_ulogic_vector(0 to 7); +signal low_pri_max0_d : std_ulogic_vector(0 to 5); +signal low_pri_max1_d : std_ulogic_vector(0 to 5); +signal low_pri_max2_d : std_ulogic_vector(0 to 5); +signal low_pri_max3_d : std_ulogic_vector(0 to 5); +signal high_pri_mask_d : std_ulogic_vector(0 to 3); +signal med_pri_mask_d : std_ulogic_vector(0 to 3); +signal spr_high_mask_d : std_ulogic_vector(0 to 3); +signal spr_med_mask_d : std_ulogic_vector(0 to 3); +signal fiss_dbg_data_d : std_ulogic_vector(44 to 87); +signal low_pri_rf0_l2 : std_ulogic_vector(0 to 3); +signal low_pri_rf1_l2 : std_ulogic_vector(0 to 3); +signal low_pri_ex1_l2 : std_ulogic_vector(0 to 3); +signal low_pri_ex2_l2 : std_ulogic_vector(0 to 3); +signal low_pri_ex3_l2 : std_ulogic_vector(0 to 3); +signal low_pri_ex4_l2 : std_ulogic_vector(0 to 3); +signal low_pri_ex5_l2 : std_ulogic_vector(0 to 3); +signal low_pri_ex6_l2 : std_ulogic_vector(0 to 3); +signal xu_iu_ex6_ppc_cpl_l2 : std_ulogic_vector(0 to 3); +signal low_pri_counter0_l2 : std_ulogic_vector(0 to 7); +signal low_pri_counter1_l2 : std_ulogic_vector(0 to 7); +signal low_pri_counter2_l2 : std_ulogic_vector(0 to 7); +signal low_pri_counter3_l2 : std_ulogic_vector(0 to 7); +signal low_pri_max0_l2 : std_ulogic_vector(0 to 5); +signal low_pri_max1_l2 : std_ulogic_vector(0 to 5); +signal low_pri_max2_l2 : std_ulogic_vector(0 to 5); +signal low_pri_max3_l2 : std_ulogic_vector(0 to 5); +signal high_pri_mask_l2 : std_ulogic_vector(0 to 3); +signal med_pri_mask_l2 : std_ulogic_vector(0 to 3); +signal spr_high_mask_l2 : std_ulogic_vector(0 to 3); +signal spr_med_mask_l2 : std_ulogic_vector(0 to 3); +signal fiss_dbg_data_l2 : std_ulogic_vector(44 to 87); +signal low_pri_counter0_act : std_ulogic; +signal low_pri_counter1_act : std_ulogic; +signal low_pri_counter2_act : std_ulogic; +signal low_pri_counter3_act : std_ulogic; +signal low_pri_rf1_act : std_ulogic; +signal low_pri_ex1_act : std_ulogic; +signal low_pri_ex2_act : std_ulogic; +signal low_pri_ex3_act : std_ulogic; +signal low_pri_ex4_act : std_ulogic; +signal low_pri_ex5_act : std_ulogic; +signal low_pri_ex6_act : std_ulogic; +signal high_pri_mask_din : std_ulogic_vector(0 to 3); +signal med_pri_mask_din : std_ulogic_vector(0 to 3); +signal low_pri_en : std_ulogic_vector(0 to 3); +signal low_pri_val : std_ulogic_vector(0 to 3); +signal pri_rand : std_ulogic_vector(0 to 5); +signal high_priority_valids : std_ulogic_vector(0 to 3); +signal med_priority_valids : std_ulogic_vector(0 to 3); +signal n_thread : std_ulogic_vector(0 to 3); +signal uc_flush_tid_d : std_ulogic_vector(0 to 3); +signal uc_flush_tid_l2 : std_ulogic_vector(0 to 3); +signal int_is2_vld : std_ulogic; +signal iss_is2_vld : std_ulogic; +signal int_is2_to_ucode : std_ulogic; +signal is1_dep_hit : std_ulogic_vector(0 to 3); +signal is2_stall : std_ulogic_vector(0 to 3); +signal perf_event_d : std_ulogic_vector(0 to 31); +signal perf_event_l2 : std_ulogic_vector(0 to 31); +signal iu_xu_is2_axu_ldst_tag_int : std_ulogic_vector(0 to 8); +signal iu_xu_is2_axu_store_int : std_ulogic; +signal iu_xu_is2_axu_ld_or_st_int : std_ulogic; +signal iu_xu_is2_instr_int : std_ulogic_vector(0 to 31); +signal iu_xu_is2_vld_int : std_ulogic; +signal iu_xu_is2_tid_int : std_ulogic_vector(0 to 3); +signal iu_xu_is2_error_int : std_ulogic_vector(0 to 2); +signal iu_xu_is2_pred_update_int : std_ulogic; +signal iu_xu_is2_pred_taken_cnt_int : std_ulogic_vector(0 to 1); +signal fiss_uc_is2_ucode_vld_int : std_ulogic; +signal rf0_str_val_d : std_ulogic; +signal rf0_str_val_l2 : std_ulogic; +signal rf0_ldst_val_d : std_ulogic; +signal rf0_ldst_val_l2 : std_ulogic; +signal rf0_ldst_tid_d : std_ulogic_vector(0 to 1); +signal rf0_ldst_tid_l2 : std_ulogic_vector(0 to 1); +signal rf0_ldst_tag_d : std_ulogic_vector(0 to 8); +signal rf0_ldst_tag_l2 : std_ulogic_vector(0 to 8); +signal rf0_ldst_act : std_ulogic; +signal next_tid : std_ulogic_vector(0 to 3); +signal hi_did3no0_d : std_ulogic; +signal hi_did3no1_d : std_ulogic; +signal hi_did3no2_d : std_ulogic; +signal hi_did2no0_d : std_ulogic; +signal hi_did2no1_d : std_ulogic; +signal hi_did1no0_d : std_ulogic; +signal md_did3no0_d : std_ulogic; +signal md_did3no1_d : std_ulogic; +signal md_did3no2_d : std_ulogic; +signal md_did2no0_d : std_ulogic; +signal md_did2no1_d : std_ulogic; +signal md_did1no0_d : std_ulogic; +signal hi_n230, hi_n231, hi_n232 : std_ulogic; +signal hi_n220, hi_n221, hi_n210 : std_ulogic; +signal md_n230, md_n231, md_n232 : std_ulogic; +signal md_n220, md_n221, md_n210 : std_ulogic; +signal medpri_v, medpri_v_b, highpri_v, highpri_v_b : std_ulogic_vector(0 to 3); +signal medpri_v_b0, highpri_v_b0 : std_ulogic_vector(0 to 3); +signal hi_did0no1, hi_did0no2, hi_did0no3 : std_ulogic; +signal hi_did1no0, hi_did1no2, hi_did1no3 : std_ulogic; +signal hi_did2no1, hi_did2no0, hi_did2no3 : std_ulogic; +signal hi_did3no1, hi_did3no2, hi_did3no0 : std_ulogic; +signal md_did0no1, md_did0no2, md_did0no3 : std_ulogic; +signal md_did1no0, md_did1no2, md_did1no3 : std_ulogic; +signal md_did2no1, md_did2no0, md_did2no3 : std_ulogic; +signal md_did3no1, md_did3no2, md_did3no0 : std_ulogic; +signal hi_sel, hi_sel_b, md_sel, md_sel_b, hi_later, md_later : std_ulogic_vector(0 to 3); +signal hi_did3no0_din : std_ulogic; +signal hi_did3no1_din : std_ulogic; +signal hi_did3no2_din : std_ulogic; +signal hi_did2no0_din : std_ulogic; +signal hi_did2no1_din : std_ulogic; +signal hi_did1no0_din : std_ulogic; +signal md_did3no0_din : std_ulogic; +signal md_did3no1_din : std_ulogic; +signal md_did3no2_din : std_ulogic; +signal md_did2no0_din : std_ulogic; +signal md_did2no1_din : std_ulogic; +signal md_did1no0_din : std_ulogic; +signal issselhi_b, issselmd_b : std_ulogic_vector(0 to 3); +signal no_hi_v,no_hi_v_n01, no_hi_v_n23 : std_ulogic; +signal hi_l30, hi_l31, hi_l32 : std_ulogic; +signal hi_l23, hi_l20, hi_l21 : std_ulogic; +signal hi_l12, hi_l13, hi_l10 : std_ulogic; +signal hi_l01, hi_l02, hi_l03 : std_ulogic; +signal md_l30, md_l31, md_l32 : std_ulogic; +signal md_l23, md_l20, md_l21 : std_ulogic; +signal md_l12, md_l13, md_l10 : std_ulogic; +signal md_l01, md_l02, md_l03 : std_ulogic; +signal take, take_b : std_ulogic_vector(0 to 3); +signal no_hi_v_b : std_ulogic; + BEGIN + +tiup <= '1'; +act_dis <= '0'; +d_mode <= '0'; +mpw2_b <= '1'; +perv_2to1_reg: tri_plat + generic map (width => 2, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_iu_func_sl_thold_2, + din(1) => pc_iu_sg_2, + q(0) => pc_iu_func_sl_thold_1, + q(1) => pc_iu_sg_1); +perv_1to0_reg: tri_plat + generic map (width => 2, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_iu_func_sl_thold_1, + din(1) => pc_iu_sg_1, + q(0) => pc_iu_func_sl_thold_0, + q(1) => pc_iu_sg_0); +perv_lcbor: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_b, + thold => pc_iu_func_sl_thold_0, + sg => pc_iu_sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => pc_iu_func_sl_thold_0_b); +uc_flush_tid_latch: tri_rlmreg_p + generic map (width => uc_flush_tid_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(uc_flush_tid_offset to uc_flush_tid_offset + uc_flush_tid_l2'length-1), + scout => sov(uc_flush_tid_offset to uc_flush_tid_offset + uc_flush_tid_l2'length-1), + din => uc_flush_tid_d, + dout => uc_flush_tid_l2); +xu_iu_need_hole_latch: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_iu_need_hole_offset), + scout => sov(xu_iu_need_hole_offset), + din => xu_iu_need_hole_d, + dout => xu_iu_need_hole_l2); +xu_iu_xucr0_rel_latch: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_iu_xucr0_rel_offset), + scout => sov(xu_iu_xucr0_rel_offset), + din => xu_iu_xucr0_rel_d, + dout => xu_iu_xucr0_rel_l2); +an_ac_back_inv_latch: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(an_ac_back_inv_offset), + scout => sov(an_ac_back_inv_offset), + din => an_ac_back_inv_d, + dout => an_ac_back_inv_l2); +an_ac_back_inv_target_latch: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(an_ac_back_inv_target_offset), + scout => sov(an_ac_back_inv_target_offset), + din => an_ac_back_inv_target_d, + dout => an_ac_back_inv_target_l2); +gap_l2_rel_hole_dly1_latch: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(gap_l2_rel_hole_dly1_offset), + scout => sov(gap_l2_rel_hole_dly1_offset), + din => gap_l2_rel_hole_dly1_d, + dout => gap_l2_rel_hole_dly1_l2); +gap_l2_rel_hole_dly2_latch: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(gap_l2_rel_hole_dly2_offset), + scout => sov(gap_l2_rel_hole_dly2_offset), + din => gap_l2_rel_hole_dly2_d, + dout => gap_l2_rel_hole_dly2_l2); +gap_l2_tag_dly1_latch: tri_rlmreg_p + generic map (width => gap_l2_tag_dly1_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(gap_l2_tag_dly1_offset to gap_l2_tag_dly1_offset + gap_l2_tag_dly1_l2'length-1), + scout => sov(gap_l2_tag_dly1_offset to gap_l2_tag_dly1_offset + gap_l2_tag_dly1_l2'length-1), + din => gap_l2_tag_dly1_d, + dout => gap_l2_tag_dly1_l2); +gap_l2_tag_dly2_latch: tri_rlmreg_p + generic map (width => gap_l2_tag_dly2_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(gap_l2_tag_dly2_offset to gap_l2_tag_dly2_offset + gap_l2_tag_dly2_l2'length-1), + scout => sov(gap_l2_tag_dly2_offset to gap_l2_tag_dly2_offset + gap_l2_tag_dly2_l2'length-1), + din => gap_l2_tag_dly2_d, + dout => gap_l2_tag_dly2_l2); +is2_vld: tri_rlmreg_p + generic map (width => is2_vld_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_vld_offset to is2_vld_offset + is2_vld_l2'length-1), + scout => sov(is2_vld_offset to is2_vld_offset + is2_vld_l2'length-1), + din => is2_vld_d, + dout => is2_vld_l2); +hole_delay0: tri_rlmreg_p + generic map (width => hole_delay0_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(hole_delay0_offset to hole_delay0_offset + hole_delay0_l2'length-1), + scout => sov(hole_delay0_offset to hole_delay0_offset + hole_delay0_l2'length-1), + din => hole_delay0_d, + dout => hole_delay0_l2); +hole_delay1: tri_rlmreg_p + generic map (width => hole_delay1_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(hole_delay1_offset to hole_delay1_offset + hole_delay1_l2'length-1), + scout => sov(hole_delay1_offset to hole_delay1_offset + hole_delay1_l2'length-1), + din => hole_delay1_d, + dout => hole_delay1_l2); +hole_delay2: tri_rlmreg_p + generic map (width => hole_delay2_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(hole_delay2_offset to hole_delay2_offset + hole_delay2_l2'length-1), + scout => sov(hole_delay2_offset to hole_delay2_offset + hole_delay2_l2'length-1), + din => hole_delay2_d, + dout => hole_delay2_l2); +hole_delay3: tri_rlmreg_p + generic map (width => hole_delay3_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(hole_delay3_offset to hole_delay3_offset + hole_delay3_l2'length-1), + scout => sov(hole_delay3_offset to hole_delay3_offset + hole_delay3_l2'length-1), + din => hole_delay3_d, + dout => hole_delay3_l2); +med_pri_mask: tri_rlmreg_p + generic map (width => med_pri_mask_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(med_pri_mask_offset to med_pri_mask_offset + med_pri_mask_l2'length-1), + scout => sov(med_pri_mask_offset to med_pri_mask_offset + med_pri_mask_l2'length-1), + din => med_pri_mask_d, + dout => med_pri_mask_l2); +high_pri_mask: tri_rlmreg_p + generic map (width => high_pri_mask_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(high_pri_mask_offset to high_pri_mask_offset + high_pri_mask_l2'length-1), + scout => sov(high_pri_mask_offset to high_pri_mask_offset + high_pri_mask_l2'length-1), + din => high_pri_mask_d, + dout => high_pri_mask_l2); +spr_high_mask: tri_rlmreg_p + generic map (width => spr_high_mask_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(spr_high_mask_offset to spr_high_mask_offset + spr_high_mask_l2'length-1), + scout => sov(spr_high_mask_offset to spr_high_mask_offset + spr_high_mask_l2'length-1), + din => spr_high_mask_d, + dout => spr_high_mask_l2); +spr_med_mask: tri_rlmreg_p + generic map (width => spr_med_mask_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(spr_med_mask_offset to spr_med_mask_offset + spr_med_mask_l2'length-1), + scout => sov(spr_med_mask_offset to spr_med_mask_offset + spr_med_mask_l2'length-1), + din => spr_med_mask_d, + dout => spr_med_mask_l2); +low_pri_max0: tri_rlmreg_p + generic map (width => low_pri_max0_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(low_pri_max0_offset to low_pri_max0_offset + low_pri_max0_l2'length-1), + scout => sov(low_pri_max0_offset to low_pri_max0_offset + low_pri_max0_l2'length-1), + din => low_pri_max0_d, + dout => low_pri_max0_l2); +low_pri_max1: tri_rlmreg_p + generic map (width => low_pri_max1_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(low_pri_max1_offset to low_pri_max1_offset + low_pri_max1_l2'length-1), + scout => sov(low_pri_max1_offset to low_pri_max1_offset + low_pri_max1_l2'length-1), + din => low_pri_max1_d, + dout => low_pri_max1_l2); +low_pri_max2: tri_rlmreg_p + generic map (width => low_pri_max2_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(low_pri_max2_offset to low_pri_max2_offset + low_pri_max2_l2'length-1), + scout => sov(low_pri_max2_offset to low_pri_max2_offset + low_pri_max2_l2'length-1), + din => low_pri_max2_d, + dout => low_pri_max2_l2); +low_pri_max3: tri_rlmreg_p + generic map (width => low_pri_max3_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(low_pri_max3_offset to low_pri_max3_offset + low_pri_max3_l2'length-1), + scout => sov(low_pri_max3_offset to low_pri_max3_offset + low_pri_max3_l2'length-1), + din => low_pri_max3_d, + dout => low_pri_max3_l2); +low_pri_counter0: tri_rlmreg_p + generic map (width => low_pri_counter0_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => low_pri_counter0_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(low_pri_counter0_offset to low_pri_counter0_offset + low_pri_counter0_l2'length-1), + scout => sov(low_pri_counter0_offset to low_pri_counter0_offset + low_pri_counter0_l2'length-1), + din => low_pri_counter0_d, + dout => low_pri_counter0_l2); +low_pri_counter1: tri_rlmreg_p + generic map (width => low_pri_counter1_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => low_pri_counter1_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(low_pri_counter1_offset to low_pri_counter1_offset + low_pri_counter1_l2'length-1), + scout => sov(low_pri_counter1_offset to low_pri_counter1_offset + low_pri_counter1_l2'length-1), + din => low_pri_counter1_d, + dout => low_pri_counter1_l2); +low_pri_counter2: tri_rlmreg_p + generic map (width => low_pri_counter2_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => low_pri_counter2_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(low_pri_counter2_offset to low_pri_counter2_offset + low_pri_counter2_l2'length-1), + scout => sov(low_pri_counter2_offset to low_pri_counter2_offset + low_pri_counter2_l2'length-1), + din => low_pri_counter2_d, + dout => low_pri_counter2_l2); +low_pri_counter3: tri_rlmreg_p + generic map (width => low_pri_counter3_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => low_pri_counter3_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(low_pri_counter3_offset to low_pri_counter3_offset + low_pri_counter3_l2'length-1), + scout => sov(low_pri_counter3_offset to low_pri_counter3_offset + low_pri_counter3_l2'length-1), + din => low_pri_counter3_d, + dout => low_pri_counter3_l2); +low_pri_rf0: tri_rlmreg_p + generic map (width => low_pri_rf0_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(low_pri_rf0_offset to low_pri_rf0_offset + low_pri_rf0_l2'length-1), + scout => sov(low_pri_rf0_offset to low_pri_rf0_offset + low_pri_rf0_l2'length-1), + din => low_pri_rf0_d, + dout => low_pri_rf0_l2); +low_pri_rf1: tri_rlmreg_p + generic map (width => low_pri_rf1_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => low_pri_rf1_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(low_pri_rf1_offset to low_pri_rf1_offset + low_pri_rf1_l2'length-1), + scout => sov(low_pri_rf1_offset to low_pri_rf1_offset + low_pri_rf1_l2'length-1), + din => low_pri_rf1_d, + dout => low_pri_rf1_l2); +low_pri_ex1: tri_rlmreg_p + generic map (width => low_pri_ex1_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => low_pri_ex1_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(low_pri_ex1_offset to low_pri_ex1_offset + low_pri_ex1_l2'length-1), + scout => sov(low_pri_ex1_offset to low_pri_ex1_offset + low_pri_ex1_l2'length-1), + din => low_pri_ex1_d, + dout => low_pri_ex1_l2); +low_pri_ex2: tri_rlmreg_p + generic map (width => low_pri_ex2_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => low_pri_ex2_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(low_pri_ex2_offset to low_pri_ex2_offset + low_pri_ex2_l2'length-1), + scout => sov(low_pri_ex2_offset to low_pri_ex2_offset + low_pri_ex2_l2'length-1), + din => low_pri_ex2_d, + dout => low_pri_ex2_l2); +low_pri_ex3: tri_rlmreg_p + generic map (width => low_pri_ex3_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => low_pri_ex3_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(low_pri_ex3_offset to low_pri_ex3_offset + low_pri_ex3_l2'length-1), + scout => sov(low_pri_ex3_offset to low_pri_ex3_offset + low_pri_ex3_l2'length-1), + din => low_pri_ex3_d, + dout => low_pri_ex3_l2); +low_pri_ex4: tri_rlmreg_p + generic map (width => low_pri_ex4_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => low_pri_ex4_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(low_pri_ex4_offset to low_pri_ex4_offset + low_pri_ex4_l2'length-1), + scout => sov(low_pri_ex4_offset to low_pri_ex4_offset + low_pri_ex4_l2'length-1), + din => low_pri_ex4_d, + dout => low_pri_ex4_l2); +low_pri_ex5: tri_rlmreg_p + generic map (width => low_pri_ex5_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => low_pri_ex5_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(low_pri_ex5_offset to low_pri_ex5_offset + low_pri_ex5_l2'length-1), + scout => sov(low_pri_ex5_offset to low_pri_ex5_offset + low_pri_ex5_l2'length-1), + din => low_pri_ex5_d, + dout => low_pri_ex5_l2); +low_pri_ex6: tri_rlmreg_p + generic map (width => low_pri_ex6_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => low_pri_ex6_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(low_pri_ex6_offset to low_pri_ex6_offset + low_pri_ex6_l2'length-1), + scout => sov(low_pri_ex6_offset to low_pri_ex6_offset + low_pri_ex6_l2'length-1), + din => low_pri_ex6_d, + dout => low_pri_ex6_l2); +xu_iu_ex6_ppc_cpl_reg: tri_rlmreg_p + generic map (width => xu_iu_ex6_ppc_cpl_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_iu_ex6_ppc_cpl_offset to xu_iu_ex6_ppc_cpl_offset + xu_iu_ex6_ppc_cpl_l2'length-1), + scout => sov(xu_iu_ex6_ppc_cpl_offset to xu_iu_ex6_ppc_cpl_offset + xu_iu_ex6_ppc_cpl_l2'length-1), + din => xu_iu_ex6_ppc_cpl_d, + dout => xu_iu_ex6_ppc_cpl_l2); +event_bus_enable_d <= pc_iu_event_bus_enable; +event_enable_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(event_bus_enable_offset), + scout => sov(event_bus_enable_offset), + din => event_bus_enable_d, + dout => event_bus_enable_q); +trace_bus_enable_d <= pc_iu_trace_bus_enable; +trace_enable_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(trace_bus_enable_offset), + scout => sov(trace_bus_enable_offset), + din => trace_bus_enable_d, + dout => trace_bus_enable_q); +perf_event: tri_rlmreg_p + generic map (width => perf_event_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => event_bus_enable_q, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(perf_event_offset to perf_event_offset + perf_event_l2'length-1), + scout => sov(perf_event_offset to perf_event_offset + perf_event_l2'length-1), + din => perf_event_d, + dout => perf_event_l2); +fiss_dbg_data_latch: tri_rlmreg_p + generic map (width => fiss_dbg_data_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => trace_bus_enable_q, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(fiss_dbg_data_offset to fiss_dbg_data_offset + fiss_dbg_data_l2'length-1), + scout => sov(fiss_dbg_data_offset to fiss_dbg_data_offset + fiss_dbg_data_l2'length-1), + din => fiss_dbg_data_d, + dout => fiss_dbg_data_l2); +spare_latch: tri_rlmreg_p + generic map (width => spare_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(spare_offset to spare_offset + spare_l2'length-1), + scout => sov(spare_offset to spare_offset + spare_l2'length-1), + din => spare_l2, + dout => spare_l2); +rf0_str_val: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(rf0_str_val_offset), + scout => sov(rf0_str_val_offset), + din => rf0_str_val_d, + dout => rf0_str_val_l2); +rf0_ldst_val: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(rf0_ldst_val_offset), + scout => sov(rf0_ldst_val_offset), + din => rf0_ldst_val_d, + dout => rf0_ldst_val_l2); +rf0_ldst_tid: tri_rlmreg_p + generic map (width => rf0_ldst_tid_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf0_ldst_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(rf0_ldst_tid_offset to rf0_ldst_tid_offset + rf0_ldst_tid_l2'length-1), + scout => sov(rf0_ldst_tid_offset to rf0_ldst_tid_offset + rf0_ldst_tid_l2'length-1), + din => rf0_ldst_tid_d, + dout => rf0_ldst_tid_l2); +rf0_ldst_tag: tri_rlmreg_p + generic map (width => rf0_ldst_tag_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf0_ldst_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(rf0_ldst_tag_offset to rf0_ldst_tag_offset + rf0_ldst_tag_l2'length-1), + scout => sov(rf0_ldst_tag_offset to rf0_ldst_tag_offset + rf0_ldst_tag_l2'length-1), + din => rf0_ldst_tag_d, + dout => rf0_ldst_tag_l2); +rf0_took_latch: tri_rlmreg_p + generic map (init => 65, expand_type => expand_type, width => 12) + port map ( + nclk => nclk, + act => tiup, + vd => vdd, + gd => gnd, + forcee => forcee, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(rf0_took_offset to rf0_took_offset + 12-1), + scout => sov(rf0_took_offset to rf0_took_offset + 12-1), + din(00) => hi_did3no0_d, + din(01) => hi_did3no1_d, + din(02) => hi_did3no2_d, + din(03) => hi_did2no0_d, + din(04) => hi_did2no1_d, + din(05) => hi_did1no0_d, + din(06) => md_did3no0_d, + din(07) => md_did3no1_d, + din(08) => md_did3no2_d, + din(09) => md_did2no0_d, + din(10) => md_did2no1_d, + din(11) => md_did1no0_d, + dout(00) => hi_did3no0, + dout(01) => hi_did3no1, + dout(02) => hi_did3no2, + dout(03) => hi_did2no0, + dout(04) => hi_did2no1, + dout(05) => hi_did1no0, + dout(06) => md_did3no0, + dout(07) => md_did3no1, + dout(08) => md_did3no2, + dout(09) => md_did2no0, + dout(10) => md_did2no1, + dout(11) => md_did1no0 + ); +hi_did3no0_d <= pri_rand(0) when (spr_fiss_pri_rand_always or (spr_fiss_pri_rand_flush and or_reduce(xu_iu_is2_flush_tid(0 to 3)))) = '1' else hi_did3no0_din; +hi_did3no1_d <= pri_rand(1) when (spr_fiss_pri_rand_always or (spr_fiss_pri_rand_flush and or_reduce(xu_iu_is2_flush_tid(0 to 3)))) = '1' else hi_did3no1_din; +hi_did3no2_d <= pri_rand(2) when (spr_fiss_pri_rand_always or (spr_fiss_pri_rand_flush and or_reduce(xu_iu_is2_flush_tid(0 to 3)))) = '1' else hi_did3no2_din; +hi_did2no0_d <= pri_rand(3) when (spr_fiss_pri_rand_always or (spr_fiss_pri_rand_flush and or_reduce(xu_iu_is2_flush_tid(0 to 3)))) = '1' else hi_did2no0_din; +hi_did2no1_d <= pri_rand(4) when (spr_fiss_pri_rand_always or (spr_fiss_pri_rand_flush and or_reduce(xu_iu_is2_flush_tid(0 to 3)))) = '1' else hi_did2no1_din; +hi_did1no0_d <= pri_rand(5) when (spr_fiss_pri_rand_always or (spr_fiss_pri_rand_flush and or_reduce(xu_iu_is2_flush_tid(0 to 3)))) = '1' else hi_did1no0_din; +md_did3no0_d <= pri_rand(0) when (spr_fiss_pri_rand_always or (spr_fiss_pri_rand_flush and or_reduce(xu_iu_is2_flush_tid(0 to 3)))) = '1' else md_did3no0_din; +md_did3no1_d <= pri_rand(1) when (spr_fiss_pri_rand_always or (spr_fiss_pri_rand_flush and or_reduce(xu_iu_is2_flush_tid(0 to 3)))) = '1' else md_did3no1_din; +md_did3no2_d <= pri_rand(2) when (spr_fiss_pri_rand_always or (spr_fiss_pri_rand_flush and or_reduce(xu_iu_is2_flush_tid(0 to 3)))) = '1' else md_did3no2_din; +md_did2no0_d <= pri_rand(3) when (spr_fiss_pri_rand_always or (spr_fiss_pri_rand_flush and or_reduce(xu_iu_is2_flush_tid(0 to 3)))) = '1' else md_did2no0_din; +md_did2no1_d <= pri_rand(4) when (spr_fiss_pri_rand_always or (spr_fiss_pri_rand_flush and or_reduce(xu_iu_is2_flush_tid(0 to 3)))) = '1' else md_did2no1_din; +md_did1no0_d <= pri_rand(5) when (spr_fiss_pri_rand_always or (spr_fiss_pri_rand_flush and or_reduce(xu_iu_is2_flush_tid(0 to 3)))) = '1' else md_did1no0_din; +pri_rand(0 TO 5) <= "001000" when spr_fiss_pri_rand(0 to 4) = "00000" else + "100111" when spr_fiss_pri_rand(0 to 4) = "00001" else + "110111" when spr_fiss_pri_rand(0 to 4) = "00010" else + "000001" when spr_fiss_pri_rand(0 to 4) = "00011" else + "000110" when spr_fiss_pri_rand(0 to 4) = "00100" else + "001001" when spr_fiss_pri_rand(0 to 4) = "00101" else + "011000" when spr_fiss_pri_rand(0 to 4) = "00110" else + "111101" when spr_fiss_pri_rand(0 to 4) = "00111" else + "100101" when spr_fiss_pri_rand(0 to 4) = "01000" else + "010110" when spr_fiss_pri_rand(0 to 4) = "01001" else + "101101" when spr_fiss_pri_rand(0 to 4) = "01010" else + "111110" when spr_fiss_pri_rand(0 to 4) = "01011" else + "110110" when spr_fiss_pri_rand(0 to 4) = "01100" else + "101001" when spr_fiss_pri_rand(0 to 4) = "01101" else + "000000" when spr_fiss_pri_rand(0 to 4) = "01110" else + "111010" when spr_fiss_pri_rand(0 to 4) = "01111" else + "000111" when spr_fiss_pri_rand(0 to 4) = "10000" else + "111001" when spr_fiss_pri_rand(0 to 4) = "10001" else + "111000" when spr_fiss_pri_rand(0 to 4) = "10010" else + "011010" when spr_fiss_pri_rand(0 to 4) = "10011" else + "111111" when spr_fiss_pri_rand(0 to 4) = "10100" else + "010010" when spr_fiss_pri_rand(0 to 4) = "10101" else + "000010" when spr_fiss_pri_rand(0 to 4) = "10110" else + "000101" when spr_fiss_pri_rand(0 to 4) = "10111" else + "111111" when spr_fiss_pri_rand(0 to 4) = "11000" else + "000000" when spr_fiss_pri_rand(0 to 4) = "11001" else + "011010" when spr_fiss_pri_rand(0 to 4) = "11010" else + "100101" when spr_fiss_pri_rand(0 to 4) = "11011" else + "001001" when spr_fiss_pri_rand(0 to 4) = "11100" else + "110110" when spr_fiss_pri_rand(0 to 4) = "11101" else + "000111" when spr_fiss_pri_rand(0 to 4) = "11110" else + "111000" ; +hole0_nor2: hole0 <= not (hole0_b or xu_iu_is2_flush_tid(0)); +hole0_b <= not (((n_thread(0) and fdep_fiss_t0_is2_hole_delay(0)) or hole_delay0_l2(0)) and not uc_flush_tid_l2(0)); +hole_delay0_d(0) <= ((n_thread(0) and fdep_fiss_t0_is2_hole_delay(1)) or hole_delay0_l2(1)) and not uc_flush_tid_l2(0) and not xu_iu_is2_flush_tid(0); +hole_delay0_d(1) <= (n_thread(0) and fdep_fiss_t0_is2_hole_delay(2)) and not uc_flush_tid_l2(0) and not xu_iu_is2_flush_tid(0); +hole1_nor2: hole1 <= not (hole1_b or xu_iu_is2_flush_tid(1)); +hole1_b <= not (((n_thread(1) and fdep_fiss_t1_is2_hole_delay(0)) or hole_delay1_l2(0)) and not uc_flush_tid_l2(1)); +hole_delay1_d(0) <= ((n_thread(1) and fdep_fiss_t1_is2_hole_delay(1)) or hole_delay1_l2(1)) and not uc_flush_tid_l2(1) and not xu_iu_is2_flush_tid(1); +hole_delay1_d(1) <= (n_thread(1) and fdep_fiss_t1_is2_hole_delay(2)) and not uc_flush_tid_l2(1) and not xu_iu_is2_flush_tid(1); +hole2_nor2: hole2 <= not (hole2_b or xu_iu_is2_flush_tid(2)); +hole2_b <= not (((n_thread(2) and fdep_fiss_t2_is2_hole_delay(0)) or hole_delay2_l2(0)) and not uc_flush_tid_l2(2)); +hole_delay2_d(0) <= ((n_thread(2) and fdep_fiss_t2_is2_hole_delay(1)) or hole_delay2_l2(1)) and not uc_flush_tid_l2(2) and not xu_iu_is2_flush_tid(2); +hole_delay2_d(1) <= (n_thread(2) and fdep_fiss_t2_is2_hole_delay(2)) and not uc_flush_tid_l2(2) and not xu_iu_is2_flush_tid(2); +hole3_nor2: hole3 <= not (hole3_b or xu_iu_is2_flush_tid(3)); +hole3_b <= not (((n_thread(3) and fdep_fiss_t3_is2_hole_delay(0)) or hole_delay3_l2(0)) and not uc_flush_tid_l2(3)); +hole_delay3_d(0) <= ((n_thread(3) and fdep_fiss_t3_is2_hole_delay(1)) or hole_delay3_l2(1)) and not uc_flush_tid_l2(3) and not xu_iu_is2_flush_tid(3); +hole_delay3_d(1) <= (n_thread(3) and fdep_fiss_t3_is2_hole_delay(2)) and not uc_flush_tid_l2(3) and not xu_iu_is2_flush_tid(3); +is1_dep_hit(0) <= not(fdep_fiss_t0_is1_xu_dep_hit_b) or not(i_axu_is1_dep_hit_t0_b); +is1_dep_hit(1) <= not(fdep_fiss_t1_is1_xu_dep_hit_b) or not(i_axu_is1_dep_hit_t1_b); +is1_dep_hit(2) <= not(fdep_fiss_t2_is1_xu_dep_hit_b) or not(i_axu_is1_dep_hit_t2_b); +is1_dep_hit(3) <= not(fdep_fiss_t3_is1_xu_dep_hit_b) or not(i_axu_is1_dep_hit_t3_b); +is2_vld_d(0) <= fdep_fiss_t0_is2early_vld and not is1_dep_hit(0) and not xu_iu_is2_flush_tid(0) and not uc_flush_tid_l2(0) when is2_stall(0) = '0' else + is2_vld_l2(0) and not xu_iu_is2_flush_tid(0) and not uc_flush_tid_l2(0); +is2_vld_d(1) <= fdep_fiss_t1_is2early_vld and not is1_dep_hit(1) and not xu_iu_is2_flush_tid(1) and not uc_flush_tid_l2(1) when is2_stall(1) = '0' else + is2_vld_l2(1) and not xu_iu_is2_flush_tid(1) and not uc_flush_tid_l2(1); +is2_vld_d(2) <= fdep_fiss_t2_is2early_vld and not is1_dep_hit(2) and not xu_iu_is2_flush_tid(2) and not uc_flush_tid_l2(2) when is2_stall(2) = '0' else + is2_vld_l2(2) and not xu_iu_is2_flush_tid(2) and not uc_flush_tid_l2(2); +is2_vld_d(3) <= fdep_fiss_t3_is2early_vld and not is1_dep_hit(3) and not xu_iu_is2_flush_tid(3) and not uc_flush_tid_l2(3) when is2_stall(3) = '0' else + is2_vld_l2(3) and not xu_iu_is2_flush_tid(3) and not uc_flush_tid_l2(3); +is2_stall(0) <= (not next_tid(0) and is2_vld_l2(0)) or (not i_afi_is2_take_t(0) and i_afd_is2_t0_instr_v); +is2_stall(1) <= (not next_tid(1) and is2_vld_l2(1)) or (not i_afi_is2_take_t(1) and i_afd_is2_t1_instr_v); +is2_stall(2) <= (not next_tid(2) and is2_vld_l2(2)) or (not i_afi_is2_take_t(2) and i_afd_is2_t2_instr_v); +is2_stall(3) <= (not next_tid(3) and is2_vld_l2(3)) or (not i_afi_is2_take_t(3) and i_afd_is2_t3_instr_v); +high_priority_valids <= high_pri_mask_l2; +med_priority_valids <= med_pri_mask_l2; +highpri_v_b0 <= not high_priority_valids; +medpri_v_b0 <= not med_priority_valids; +highpri0v_inv: highpri_v(0) <= not highpri_v_b0(0); +highpri1v_inv: highpri_v(1) <= not highpri_v_b0(1); +highpri2v_inv: highpri_v(2) <= not highpri_v_b0(2); +highpri3v_inv: highpri_v(3) <= not highpri_v_b0(3); +highpri0vb_inv: highpri_v_b(0) <= not highpri_v(0); +highpri1vb_inv: highpri_v_b(1) <= not highpri_v(1); +highpri2vb_inv: highpri_v_b(2) <= not highpri_v(2); +highpri3vb_inv: highpri_v_b(3) <= not highpri_v(3); +hi_sel_nor23: hi_sel(3) <= not (highpri_v_b(3) or hi_later(3)); +hi_sel_nand33: hi_later(3) <= not (hi_l30 and hi_l31 and hi_l32); +hi_sel_nand230: hi_l30 <= not (hi_did3no0 and highpri_v(0)); +hi_sel_nand231: hi_l31 <= not (hi_did3no1 and highpri_v(1)); +hi_sel_nand232: hi_l32 <= not (hi_did3no2 and highpri_v(2)); +hi_sel_nor22: hi_sel(2) <= not (highpri_v_b(2) or hi_later(2)); +hi_sel_nand32: hi_later(2) <= not (hi_l23 and hi_l20 and hi_l21); +hi_sel_nand223: hi_l23 <= not (hi_did2no3 and highpri_v(3)); +hi_sel_nand220: hi_l20 <= not (hi_did2no0 and highpri_v(0)); +hi_sel_nand221: hi_l21 <= not (hi_did2no1 and highpri_v(1)); +hi_sel_nor21: hi_sel(1) <= not (highpri_v_b(1) or hi_later(1)); +hi_sel_nand31: hi_later(1) <= not (hi_l12 and hi_l13 and hi_l10); +hi_sel_nand212: hi_l12 <= not (hi_did1no2 and highpri_v(2)); +hi_sel_nand213: hi_l13 <= not (hi_did1no3 and highpri_v(3)); +hi_sel_nand210: hi_l10 <= not (hi_did1no0 and highpri_v(0)); +hi_sel_nor20: hi_sel(0) <= not (highpri_v_b(0) or hi_later(0)); +hi_sel_nand30: hi_later(0) <= not (hi_l01 and hi_l02 and hi_l03); +hi_sel_nand201: hi_l01 <= not (hi_did0no1 and highpri_v(1)); +hi_sel_nand202: hi_l02 <= not (hi_did0no2 and highpri_v(2)); +hi_sel_nand203: hi_l03 <= not (hi_did0no3 and highpri_v(3)); +medpri0v_inv: medpri_v(0) <= not medpri_v_b0(0); +medpri1v_inv: medpri_v(1) <= not medpri_v_b0(1); +medpri2v_inv: medpri_v(2) <= not medpri_v_b0(2); +medpri3v_inv: medpri_v(3) <= not medpri_v_b0(3); +medpri0vb_inv: medpri_v_b(0) <= not medpri_v(0); +medpri1vb_inv: medpri_v_b(1) <= not medpri_v(1); +medpri2vb_inv: medpri_v_b(2) <= not medpri_v(2); +medpri3vb_inv: medpri_v_b(3) <= not medpri_v(3); +md_sel_nor23: md_sel(3) <= not (medpri_v_b(3) or md_later(3)); +md_sel_nand33: md_later(3) <= not (md_l30 and md_l31 and md_l32); +md_sel_nand230: md_l30 <= not (md_did3no0 and medpri_v(0)); +md_sel_nand231: md_l31 <= not (md_did3no1 and medpri_v(1)); +md_sel_nand232: md_l32 <= not (md_did3no2 and medpri_v(2)); +md_sel_nor22: md_sel(2) <= not (medpri_v_b(2) or md_later(2)); +md_sel_nand32: md_later(2) <= not (md_l23 and md_l20 and md_l21); +md_sel_nand223: md_l23 <= not (md_did2no3 and medpri_v(3)); +md_sel_nand220: md_l20 <= not (md_did2no0 and medpri_v(0)); +md_sel_nand221: md_l21 <= not (md_did2no1 and medpri_v(1)); +md_sel_nor21: md_sel(1) <= not (medpri_v_b(1) or md_later(1)); +md_sel_nand31: md_later(1) <= not (md_l12 and md_l13 and md_l10); +md_sel_nand212: md_l12 <= not (md_did1no2 and medpri_v(2)); +md_sel_nand213: md_l13 <= not (md_did1no3 and medpri_v(3)); +md_sel_nand210: md_l10 <= not (md_did1no0 and medpri_v(0)); +md_sel_nor20: md_sel(0) <= not (medpri_v_b(0) or md_later(0)); +md_sel_nand30: md_later(0) <= not (md_l01 and md_l02 and md_l03); +md_sel_nand201: md_l01 <= not (md_did0no1 and medpri_v(1)); +md_sel_nand202: md_l02 <= not (md_did0no2 and medpri_v(2)); +md_sel_nand203: md_l03 <= not (md_did0no3 and medpri_v(3)); +hi_sel_inv0: hi_sel_b(0) <= not hi_sel(0); +hi_sel_inv1: hi_sel_b(1) <= not hi_sel(1); +hi_sel_inv2: hi_sel_b(2) <= not hi_sel(2); +hi_sel_inv3: hi_sel_b(3) <= not hi_sel(3); +hi_reordf_nand230: hi_did3no0_din <= not (hi_sel_b(3) and hi_n230); +hi_reordf_nand231: hi_did3no1_din <= not (hi_sel_b(3) and hi_n231); +hi_reordf_nand232: hi_did3no2_din <= not (hi_sel_b(3) and hi_n232); +hi_reord_nand230: hi_n230 <= not (hi_sel_b(0) and hi_did3no0); +hi_reord_nand231: hi_n231 <= not (hi_sel_b(1) and hi_did3no1); +hi_reord_nand232: hi_n232 <= not (hi_sel_b(2) and hi_did3no2); +hi_reordf_nand220: hi_did2no0_din <= not(hi_sel_b(2) and hi_n220); +hi_reord_nand220: hi_n220 <= not(hi_sel_b(0) and hi_did2no0); +hi_reordf_nand221: hi_did2no1_din <= not(hi_sel_b(2) and hi_n221); +hi_reord_nand221: hi_n221 <= not(hi_sel_b(1) and hi_did2no1); +hi_reord_inv23: hi_did2no3 <= not hi_did3no2; +hi_reordf_nand210: hi_did1no0_din <= not(hi_sel_b(1) and hi_n210); +hi_reord_nand210: hi_n210 <= not(hi_sel_b(0) and hi_did1no0); +hi_reord_inv12: hi_did1no2 <= not hi_did2no1; +hi_reord_inv13: hi_did1no3 <= not hi_did3no1; +hi_reord_inv01: hi_did0no1 <= not hi_did1no0; +hi_reord_inv02: hi_did0no2 <= not hi_did2no0; +hi_reord_inv03: hi_did0no3 <= not hi_did3no0; +md_sel_inv0: md_sel_b(0) <= not md_sel(0); +md_sel_inv1: md_sel_b(1) <= not md_sel(1); +md_sel_inv2: md_sel_b(2) <= not md_sel(2); +md_sel_inv3: md_sel_b(3) <= not md_sel(3); +md_reordf_nand230: md_did3no0_din <= not (md_sel_b(3) and md_n230); +md_reordf_nand231: md_did3no1_din <= not (md_sel_b(3) and md_n231); +md_reordf_nand232: md_did3no2_din <= not (md_sel_b(3) and md_n232); +md_reord_nand230: md_n230 <= not (md_sel_b(0) and md_did3no0); +md_reord_nand231: md_n231 <= not (md_sel_b(1) and md_did3no1); +md_reord_nand232: md_n232 <= not (md_sel_b(2) and md_did3no2); +md_reordf_nand220: md_did2no0_din <= not(md_sel_b(2) and md_n220); +md_reord_nand220: md_n220 <= not(md_sel_b(0) and md_did2no0); +md_reordf_nand221: md_did2no1_din <= not(md_sel_b(2) and md_n221); +md_reord_nand221: md_n221 <= not(md_sel_b(1) and md_did2no1); +md_reord_inv23: md_did2no3 <= not md_did3no2; +md_reordf_nand210: md_did1no0_din <= not(md_sel_b(1) and md_n210); +md_reord_nand210: md_n210 <= not(md_sel_b(0) and md_did1no0); +md_reord_inv12: md_did1no2 <= not md_did2no1; +md_reord_inv13: md_did1no3 <= not md_did3no1; +md_reord_inv01: md_did0no1 <= not md_did1no0; +md_reord_inv02: md_did0no2 <= not md_did2no0; +md_reord_inv03: md_did0no3 <= not md_did3no0; +nohi_nor21: no_hi_v_n01 <= not (highpri_v(0) or highpri_v(1)); +nohi_nor22: no_hi_v_n23 <= not (highpri_v(2) or highpri_v(3)); +nohi_nand2: no_hi_v_b <= not (no_hi_v_n01 and no_hi_v_n23); +nohi_inv: no_hi_v <= not (no_hi_v_b); +isssel0_inv: issselhi_b(0) <= not (hi_sel(0)); +isssel1_inv: issselhi_b(1) <= not (hi_sel(1)); +isssel2_inv: issselhi_b(2) <= not (hi_sel(2)); +isssel3_inv: issselhi_b(3) <= not (hi_sel(3)); +isssel0_bnand2: issselmd_b(0) <= not (md_sel(0) and no_hi_v); +isssel1_bnand2: issselmd_b(1) <= not (md_sel(1) and no_hi_v); +isssel2_bnand2: issselmd_b(2) <= not (md_sel(2) and no_hi_v); +isssel3_bnand2: issselmd_b(3) <= not (md_sel(3) and no_hi_v); +isssel0_fnand2: take(0) <= not (issselhi_b(0) and issselmd_b(0)); +isssel1_fnand2: take(1) <= not (issselhi_b(1) and issselmd_b(1)); +isssel2_fnand2: take(2) <= not (issselhi_b(2) and issselmd_b(2)); +isssel3_fnand2: take(3) <= not (issselhi_b(3) and issselmd_b(3)); +nexttid0_fnand2: next_tid(0) <= not (issselhi_b(0) and issselmd_b(0)); +nexttid1_fnand2: next_tid(1) <= not (issselhi_b(1) and issselmd_b(1)); +nexttid2_fnand2: next_tid(2) <= not (issselhi_b(2) and issselmd_b(2)); +nexttid3_fnand2: next_tid(3) <= not (issselhi_b(3) and issselmd_b(3)); +take0_rp1_inv: take_b(0) <= not(take(0)); +take1_rp1_inv: take_b(1) <= not(take(1)); +take2_rp1_inv: take_b(2) <= not(take(2)); +take3_rp1_inv: take_b(3) <= not(take(3)); +take0_rp2_inv: fiss_fdep_is2_take0 <= not(take_b(0)); +take1_rp2_inv: fiss_fdep_is2_take1 <= not(take_b(1)); +take2_rp2_inv: fiss_fdep_is2_take2 <= not(take_b(2)); +take3_rp2_inv: fiss_fdep_is2_take3 <= not(take_b(3)); +xu_iu_ex6_ppc_cpl_d <= xu_iu_ex5_ppc_cpl; +low_pri_en(0) <= low_pri_counter0_l2(0 to 5) = low_pri_max0_l2(0 to 5) and not (next_tid(0) = '1' or i_afi_is2_take_t(0) = '1') and not low_pri_val(0); +low_pri_en(1) <= low_pri_counter1_l2(0 to 5) = low_pri_max1_l2(0 to 5) and not (next_tid(1) = '1' or i_afi_is2_take_t(1) = '1') and not low_pri_val(1); +low_pri_en(2) <= low_pri_counter2_l2(0 to 5) = low_pri_max2_l2(0 to 5) and not (next_tid(2) = '1' or i_afi_is2_take_t(2) = '1') and not low_pri_val(2); +low_pri_en(3) <= low_pri_counter3_l2(0 to 5) = low_pri_max3_l2(0 to 5) and not (next_tid(3) = '1' or i_afi_is2_take_t(3) = '1') and not low_pri_val(3); +low_pri_counter0_d(0 TO 7) <= "00000000" when xu_iu_ex6_ppc_cpl_l2(0) = '1' else + low_pri_counter0_l2 + 1; +low_pri_counter1_d(0 TO 7) <= "00000000" when xu_iu_ex6_ppc_cpl_l2(1) = '1' else + low_pri_counter1_l2 + 1; +low_pri_counter2_d(0 TO 7) <= "00000000" when xu_iu_ex6_ppc_cpl_l2(2) = '1' else + low_pri_counter2_l2 + 1; +low_pri_counter3_d(0 TO 7) <= "00000000" when xu_iu_ex6_ppc_cpl_l2(3) = '1' else + low_pri_counter3_l2 + 1; +low_pri_counter0_act <= (xu_iu_ex6_ppc_cpl_l2(0) = '1') or (low_pri_counter0_l2(0 to 5) /= low_pri_max0_l2(0 to 5)); +low_pri_counter1_act <= (xu_iu_ex6_ppc_cpl_l2(1) = '1') or (low_pri_counter1_l2(0 to 5) /= low_pri_max1_l2(0 to 5)); +low_pri_counter2_act <= (xu_iu_ex6_ppc_cpl_l2(2) = '1') or (low_pri_counter2_l2(0 to 5) /= low_pri_max2_l2(0 to 5)); +low_pri_counter3_act <= (xu_iu_ex6_ppc_cpl_l2(3) = '1') or (low_pri_counter3_l2(0 to 5) /= low_pri_max3_l2(0 to 5)); +low_pri_rf0_d(0 TO 3) <= (next_tid(0 to 3) or i_afi_is2_take_t(0 to 3)) and not xu_iu_is2_flush_tid(0 to 3); +low_pri_rf1_d(0 TO 3) <= low_pri_rf0_l2(0 to 3) and not xu_iu_rf0_flush_tid(0 to 3); +low_pri_ex1_d(0 TO 3) <= low_pri_rf1_l2(0 to 3) and not xu_iu_rf1_flush_tid(0 to 3); +low_pri_ex2_d(0 TO 3) <= low_pri_ex1_l2(0 to 3) and not xu_iu_ex1_flush_tid(0 to 3); +low_pri_ex3_d(0 TO 3) <= low_pri_ex2_l2(0 to 3) and not xu_iu_ex2_flush_tid(0 to 3); +low_pri_ex4_d(0 TO 3) <= low_pri_ex3_l2(0 to 3) and not xu_iu_ex3_flush_tid(0 to 3); +low_pri_ex5_d(0 TO 3) <= low_pri_ex4_l2(0 to 3) and not xu_iu_ex4_flush_tid(0 to 3); +low_pri_ex6_d(0 TO 3) <= low_pri_ex5_l2(0 to 3) and not xu_iu_ex5_flush_tid(0 to 3); +low_pri_rf1_act <= or_reduce(low_pri_rf0_l2(0 to 3)) or or_reduce(low_pri_rf1_l2(0 to 3)); +low_pri_ex1_act <= or_reduce(low_pri_rf1_l2(0 to 3)) or or_reduce(low_pri_ex1_l2(0 to 3)); +low_pri_ex2_act <= or_reduce(low_pri_ex1_l2(0 to 3)) or or_reduce(low_pri_ex2_l2(0 to 3)); +low_pri_ex3_act <= or_reduce(low_pri_ex2_l2(0 to 3)) or or_reduce(low_pri_ex3_l2(0 to 3)); +low_pri_ex4_act <= or_reduce(low_pri_ex3_l2(0 to 3)) or or_reduce(low_pri_ex4_l2(0 to 3)); +low_pri_ex5_act <= or_reduce(low_pri_ex4_l2(0 to 3)) or or_reduce(low_pri_ex5_l2(0 to 3)); +low_pri_ex6_act <= or_reduce(low_pri_ex5_l2(0 to 3)) or or_reduce(low_pri_ex6_l2(0 to 3)); +low_pri_val(0 TO 3) <= low_pri_rf0_l2(0 to 3) or + low_pri_rf1_l2(0 to 3) or + low_pri_ex1_l2(0 to 3) or + low_pri_ex2_l2(0 to 3) or + low_pri_ex3_l2(0 to 3) or + low_pri_ex4_l2(0 to 3) or + low_pri_ex5_l2(0 to 3) or + low_pri_ex6_l2(0 to 3) ; +xu_iu_need_hole_d <= xu_iu_need_hole; +xu_iu_xucr0_rel_d <= xu_iu_xucr0_rel; +an_ac_back_inv_d <= an_ac_back_inv; +an_ac_back_inv_target_d <= an_ac_back_inv_target; +gap_l2_rel_hole <= an_ac_reld_data_vld and not an_ac_reld_core_tag(1) and not an_ac_reld_ditc and not dcache_rel_tag_2nd_beat; +gap_l2_rel_hole_dly1_d <= gap_l2_rel_hole; +gap_l2_rel_hole_dly2_d <= gap_l2_rel_hole_dly1_l2; +gap_l2_tag_dly1_d <= an_ac_reld_core_tag(2 to 4); +gap_l2_tag_dly2_d <= gap_l2_tag_dly1_l2; +dcache_rel_tag_2nd_beat <= (gap_l2_tag_dly2_l2(2 to 4) = an_ac_reld_core_tag(2 to 4)) and gap_l2_rel_hole_dly2_l2; +dcache_rel_hole <= (gap_l2_rel_hole and not xu_iu_xucr0_rel_l2) or + (an_ac_reld_data_coming and xu_iu_xucr0_rel_l2); +dcache_binv_hole <= an_ac_back_inv_l2 and an_ac_back_inv_target_l2; +need_hole <= dcache_binv_hole or dcache_rel_hole or xu_iu_need_hole_l2; +high_pri_mask_din <= spr_high_mask_l2 or low_pri_en; +med_pri_mask_din <= spr_med_mask_l2 and not low_pri_en; +high_pri_mask_d <= gate(is2_vld_d and high_pri_mask_din, not (hole0 or hole1 or hole2 or hole3 or need_hole)); +med_pri_mask_d <= gate(is2_vld_d and med_pri_mask_din, not (hole0 or hole1 or hole2 or hole3 or need_hole)); +iu_au_hi_pri_mask <= high_pri_mask_din; +iu_au_md_pri_mask <= med_pri_mask_din; +low_pri_max0_d <= spr_fiss_count0_max; +low_pri_max1_d <= spr_fiss_count1_max; +low_pri_max2_d <= spr_fiss_count2_max; +low_pri_max3_d <= spr_fiss_count3_max; +spr_high_mask_d <= spr_issue_high_mask; +spr_med_mask_d <= spr_issue_med_mask; +n_thread <= next_tid; +int_is2_vld <= (not xu_iu_is2_flush_tid(0) and not uc_flush_tid_l2(0) and n_thread(0)) or + (not xu_iu_is2_flush_tid(1) and not uc_flush_tid_l2(1) and n_thread(1)) or + (not xu_iu_is2_flush_tid(2) and not uc_flush_tid_l2(2) and n_thread(2)) or + (not xu_iu_is2_flush_tid(3) and not uc_flush_tid_l2(3) and n_thread(3)) ; +iss_is2_vld <= (not uc_flush_tid_l2(0) and n_thread(0)) or + (not uc_flush_tid_l2(1) and n_thread(1)) or + (not uc_flush_tid_l2(2) and n_thread(2)) or + (not uc_flush_tid_l2(3) and n_thread(3)) ; +iu_xu_is2_instr_int <= gate(fdep_fiss_t0_is2_instr, n_thread(0)) or + gate(fdep_fiss_t1_is2_instr, n_thread(1)) or + gate(fdep_fiss_t2_is2_instr, n_thread(2)) or + gate(fdep_fiss_t3_is2_instr, n_thread(3)) ; +iu_xu_is2_ta_vld <= (fdep_fiss_t0_is2_ta_vld and not fdep_fiss_t0_is2_to_ucode and not uc_flush_tid_l2(0) and n_thread(0)) or + (fdep_fiss_t1_is2_ta_vld and not fdep_fiss_t1_is2_to_ucode and not uc_flush_tid_l2(1) and n_thread(1)) or + (fdep_fiss_t2_is2_ta_vld and not fdep_fiss_t2_is2_to_ucode and not uc_flush_tid_l2(2) and n_thread(2)) or + (fdep_fiss_t3_is2_ta_vld and not fdep_fiss_t3_is2_to_ucode and not uc_flush_tid_l2(3) and n_thread(3)) ; +iu_xu_is2_ta <= gate(fdep_fiss_t0_is2_ta, n_thread(0)) or + gate(fdep_fiss_t1_is2_ta, n_thread(1)) or + gate(fdep_fiss_t2_is2_ta, n_thread(2)) or + gate(fdep_fiss_t3_is2_ta, n_thread(3)) ; +iu_xu_is2_s1_vld <= (fdep_fiss_t0_is2_s1_vld and not uc_flush_tid_l2(0) and n_thread(0)) or + (fdep_fiss_t1_is2_s1_vld and not uc_flush_tid_l2(1) and n_thread(1)) or + (fdep_fiss_t2_is2_s1_vld and not uc_flush_tid_l2(2) and n_thread(2)) or + (fdep_fiss_t3_is2_s1_vld and not uc_flush_tid_l2(3) and n_thread(3)) ; +iu_xu_is2_s1 <= gate(fdep_fiss_t0_is2_s1, n_thread(0)) or + gate(fdep_fiss_t1_is2_s1, n_thread(1)) or + gate(fdep_fiss_t2_is2_s1, n_thread(2)) or + gate(fdep_fiss_t3_is2_s1, n_thread(3)) ; +iu_xu_is2_s2_vld <= (fdep_fiss_t0_is2_s2_vld and not uc_flush_tid_l2(0) and n_thread(0)) or + (fdep_fiss_t1_is2_s2_vld and not uc_flush_tid_l2(1) and n_thread(1)) or + (fdep_fiss_t2_is2_s2_vld and not uc_flush_tid_l2(2) and n_thread(2)) or + (fdep_fiss_t3_is2_s2_vld and not uc_flush_tid_l2(3) and n_thread(3)) ; +iu_xu_is2_s2 <= gate(fdep_fiss_t0_is2_s2, n_thread(0)) or + gate(fdep_fiss_t1_is2_s2, n_thread(1)) or + gate(fdep_fiss_t2_is2_s2, n_thread(2)) or + gate(fdep_fiss_t3_is2_s2, n_thread(3)) ; +iu_xu_is2_s3_vld <= (fdep_fiss_t0_is2_s3_vld and not uc_flush_tid_l2(0) and n_thread(0)) or + (fdep_fiss_t1_is2_s3_vld and not uc_flush_tid_l2(1) and n_thread(1)) or + (fdep_fiss_t2_is2_s3_vld and not uc_flush_tid_l2(2) and n_thread(2)) or + (fdep_fiss_t3_is2_s3_vld and not uc_flush_tid_l2(3) and n_thread(3)) ; +iu_xu_is2_s3 <= gate(fdep_fiss_t0_is2_s3, n_thread(0)) or + gate(fdep_fiss_t1_is2_s3, n_thread(1)) or + gate(fdep_fiss_t2_is2_s3, n_thread(2)) or + gate(fdep_fiss_t3_is2_s3, n_thread(3)) ; +iu_xu_is2_pred_update_int <= (fdep_fiss_t0_is2_pred_update and n_thread(0)) or + (fdep_fiss_t1_is2_pred_update and n_thread(1)) or + (fdep_fiss_t2_is2_pred_update and n_thread(2)) or + (fdep_fiss_t3_is2_pred_update and n_thread(3)) ; +iu_xu_is2_pred_update <= iu_xu_is2_pred_update_int; +iu_xu_is2_pred_taken_cnt_int <= gate(fdep_fiss_t0_is2_pred_taken_cnt, n_thread(0)) or + gate(fdep_fiss_t1_is2_pred_taken_cnt, n_thread(1)) or + gate(fdep_fiss_t2_is2_pred_taken_cnt, n_thread(2)) or + gate(fdep_fiss_t3_is2_pred_taken_cnt, n_thread(3)) ; +iu_xu_is2_pred_taken_cnt <= iu_xu_is2_pred_taken_cnt_int; +iu_xu_is2_gshare <= gate(fdep_fiss_t0_is2_gshare, n_thread(0)) or + gate(fdep_fiss_t1_is2_gshare, n_thread(1)) or + gate(fdep_fiss_t2_is2_gshare, n_thread(2)) or + gate(fdep_fiss_t3_is2_gshare, n_thread(3)) ; +iu_xu_is2_ifar <= gate(fdep_fiss_t0_is2_ifar, n_thread(0)) or + gate(fdep_fiss_t1_is2_ifar, n_thread(1)) or + gate(fdep_fiss_t2_is2_ifar, n_thread(2)) or + gate(fdep_fiss_t3_is2_ifar, n_thread(3)) ; +iu_xu_is2_error_int <= gate(fdep_fiss_t0_is2_error, n_thread(0)) or + gate(fdep_fiss_t1_is2_error, n_thread(1)) or + gate(fdep_fiss_t2_is2_error, n_thread(2)) or + gate(fdep_fiss_t3_is2_error, n_thread(3)) ; +iu_xu_is2_error <= iu_xu_is2_error_int; +int_is2_to_ucode <= (fdep_fiss_t0_is2_to_ucode and n_thread(0)) or + (fdep_fiss_t1_is2_to_ucode and n_thread(1)) or + (fdep_fiss_t2_is2_to_ucode and n_thread(2)) or + (fdep_fiss_t3_is2_to_ucode and n_thread(3)) ; +iu_xu_is2_is_ucode <= (fdep_fiss_t0_is2_is_ucode and n_thread(0)) or + (fdep_fiss_t1_is2_is_ucode and n_thread(1)) or + (fdep_fiss_t2_is2_is_ucode and n_thread(2)) or + (fdep_fiss_t3_is2_is_ucode and n_thread(3)) ; +iu_xu_is2_axu_ld_or_st_int <= (fdep_fiss_t0_is2_axu_ld_or_st and n_thread(0)) or + (fdep_fiss_t1_is2_axu_ld_or_st and n_thread(1)) or + (fdep_fiss_t2_is2_axu_ld_or_st and n_thread(2)) or + (fdep_fiss_t3_is2_axu_ld_or_st and n_thread(3)) ; +iu_xu_is2_axu_store_int <= (fdep_fiss_t0_is2_axu_store and n_thread(0)) or + (fdep_fiss_t1_is2_axu_store and n_thread(1)) or + (fdep_fiss_t2_is2_axu_store and n_thread(2)) or + (fdep_fiss_t3_is2_axu_store and n_thread(3)) ; +iu_xu_is2_axu_ldst_indexed <= (fdep_fiss_t0_is2_axu_ldst_indexed and n_thread(0)) or + (fdep_fiss_t1_is2_axu_ldst_indexed and n_thread(1)) or + (fdep_fiss_t2_is2_axu_ldst_indexed and n_thread(2)) or + (fdep_fiss_t3_is2_axu_ldst_indexed and n_thread(3)) ; +iu_xu_is2_axu_ldst_tag_int <= gate(fdep_fiss_t0_is2_axu_ldst_tag, n_thread(0)) or + gate(fdep_fiss_t1_is2_axu_ldst_tag, n_thread(1)) or + gate(fdep_fiss_t2_is2_axu_ldst_tag, n_thread(2)) or + gate(fdep_fiss_t3_is2_axu_ldst_tag, n_thread(3)) ; +iu_xu_is2_axu_ldst_size <= gate(fdep_fiss_t0_is2_axu_ldst_size, n_thread(0)) or + gate(fdep_fiss_t1_is2_axu_ldst_size, n_thread(1)) or + gate(fdep_fiss_t2_is2_axu_ldst_size, n_thread(2)) or + gate(fdep_fiss_t3_is2_axu_ldst_size, n_thread(3)) ; +iu_xu_is2_axu_ldst_update <= (fdep_fiss_t0_is2_axu_ldst_update and n_thread(0)) or + (fdep_fiss_t1_is2_axu_ldst_update and n_thread(1)) or + (fdep_fiss_t2_is2_axu_ldst_update and n_thread(2)) or + (fdep_fiss_t3_is2_axu_ldst_update and n_thread(3)) ; +iu_xu_is2_axu_ldst_extpid <= (fdep_fiss_t0_is2_axu_ldst_extpid and n_thread(0)) or + (fdep_fiss_t1_is2_axu_ldst_extpid and n_thread(1)) or + (fdep_fiss_t2_is2_axu_ldst_extpid and n_thread(2)) or + (fdep_fiss_t3_is2_axu_ldst_extpid and n_thread(3)) ; +iu_xu_is2_axu_ldst_forcealign <= (fdep_fiss_t0_is2_axu_ldst_forcealign and n_thread(0)) or + (fdep_fiss_t1_is2_axu_ldst_forcealign and n_thread(1)) or + (fdep_fiss_t2_is2_axu_ldst_forcealign and n_thread(2)) or + (fdep_fiss_t3_is2_axu_ldst_forcealign and n_thread(3)) ; +iu_xu_is2_axu_ldst_forceexcept <= (fdep_fiss_t0_is2_axu_ldst_forceexcept and n_thread(0)) or + (fdep_fiss_t1_is2_axu_ldst_forceexcept and n_thread(1)) or + (fdep_fiss_t2_is2_axu_ldst_forceexcept and n_thread(2)) or + (fdep_fiss_t3_is2_axu_ldst_forceexcept and n_thread(3)) ; +iu_xu_is2_axu_mftgpr <= (fdep_fiss_t0_is2_axu_mftgpr and n_thread(0)) or + (fdep_fiss_t1_is2_axu_mftgpr and n_thread(1)) or + (fdep_fiss_t2_is2_axu_mftgpr and n_thread(2)) or + (fdep_fiss_t3_is2_axu_mftgpr and n_thread(3)) ; +iu_xu_is2_axu_mffgpr <= (fdep_fiss_t0_is2_axu_mffgpr and n_thread(0)) or + (fdep_fiss_t1_is2_axu_mffgpr and n_thread(1)) or + (fdep_fiss_t2_is2_axu_mffgpr and n_thread(2)) or + (fdep_fiss_t3_is2_axu_mffgpr and n_thread(3)) ; +iu_xu_is2_axu_movedp <= (fdep_fiss_t0_is2_axu_movedp and n_thread(0)) or + (fdep_fiss_t1_is2_axu_movedp and n_thread(1)) or + (fdep_fiss_t2_is2_axu_movedp and n_thread(2)) or + (fdep_fiss_t3_is2_axu_movedp and n_thread(3)) ; +iu_xu_is2_axu_instr_type <= gate(fdep_fiss_t0_is2_axu_instr_type, n_thread(0)) or + gate(fdep_fiss_t1_is2_axu_instr_type, n_thread(1)) or + gate(fdep_fiss_t2_is2_axu_instr_type, n_thread(2)) or + gate(fdep_fiss_t3_is2_axu_instr_type, n_thread(3)) ; +iu_xu_is2_match <= (fdep_fiss_t0_is2_match and n_thread(0)) or + (fdep_fiss_t1_is2_match and n_thread(1)) or + (fdep_fiss_t2_is2_match and n_thread(2)) or + (fdep_fiss_t3_is2_match and n_thread(3)) ; +fiss_uc_is2_2ucode <= (fdep_fiss_t0_is2_2ucode and n_thread(0)) or + (fdep_fiss_t1_is2_2ucode and n_thread(1)) or + (fdep_fiss_t2_is2_2ucode and n_thread(2)) or + (fdep_fiss_t3_is2_2ucode and n_thread(3)) ; +fiss_uc_is2_2ucode_type <= (fdep_fiss_t0_is2_2ucode_type and n_thread(0)) or + (fdep_fiss_t1_is2_2ucode_type and n_thread(1)) or + (fdep_fiss_t2_is2_2ucode_type and n_thread(2)) or + (fdep_fiss_t3_is2_2ucode_type and n_thread(3)) ; +uc_flush_tid_d(0) <= n_thread(0) and fdep_fiss_t0_is2_to_ucode and not xu_iu_is2_flush_tid(0) and not uc_flush_tid_l2(0); +uc_flush_tid_d(1) <= n_thread(1) and fdep_fiss_t1_is2_to_ucode and not xu_iu_is2_flush_tid(1) and not uc_flush_tid_l2(1); +uc_flush_tid_d(2) <= n_thread(2) and fdep_fiss_t2_is2_to_ucode and not xu_iu_is2_flush_tid(2) and not uc_flush_tid_l2(2); +uc_flush_tid_d(3) <= n_thread(3) and fdep_fiss_t3_is2_to_ucode and not xu_iu_is2_flush_tid(3) and not uc_flush_tid_l2(3); +iu_xu_is2_vld_int <= iss_is2_vld and not int_is2_to_ucode; +iu_xu_is2_tid_int <= n_thread; +iu_xu_is2_vld <= iu_xu_is2_vld_int; +iu_xu_is2_tid <= iu_xu_is2_tid_int; +fiss_uc_is2_ucode_vld_int <= iss_is2_vld and int_is2_to_ucode; +fiss_uc_is2_ucode_vld <= fiss_uc_is2_ucode_vld_int; +iu_xu_is2_axu_store <= iu_xu_is2_axu_store_int; +iu_xu_is2_axu_ld_or_st <= iu_xu_is2_axu_ld_or_st_int; +iu_xu_is2_instr <= iu_xu_is2_instr_int; +iu_xu_is2_axu_ldst_tag <= iu_xu_is2_axu_ldst_tag_int; +rf0_str_val_d <= iu_xu_is2_axu_store_int; +rf0_ldst_val_d <= iu_xu_is2_axu_ld_or_st_int and int_is2_vld and not int_is2_to_ucode; +rf0_ldst_tid_d <= gate("11", n_thread(3)) or + gate("10", n_thread(2)) or + gate("01", n_thread(1)) ; +rf0_ldst_tag_d <= iu_xu_is2_axu_ldst_tag_int; +rf0_ldst_act <= iss_is2_vld; +iu_fu_rf0_str_val <= rf0_str_val_l2; +iu_fu_rf0_ldst_val <= rf0_ldst_val_l2; +iu_fu_rf0_ldst_tid <= rf0_ldst_tid_l2; +iu_fu_rf0_ldst_tag <= rf0_ldst_tag_l2; +perf_event_d(0) <= i_afi_is2_take_t(0) and n_thread(0); +perf_event_d(1) <= i_afi_is2_take_t(1) and n_thread(1); +perf_event_d(2) <= i_afi_is2_take_t(2) and n_thread(2); +perf_event_d(3) <= i_afi_is2_take_t(3) and n_thread(3); +perf_event_d(4) <= not i_afi_is2_take_t(0) and i_afd_is2_t0_instr_v; +perf_event_d(5) <= not i_afi_is2_take_t(1) and i_afd_is2_t1_instr_v; +perf_event_d(6) <= not i_afi_is2_take_t(2) and i_afd_is2_t2_instr_v; +perf_event_d(7) <= not i_afi_is2_take_t(3) and i_afd_is2_t3_instr_v; +perf_event_d(8) <= not next_tid(0) and is2_vld_l2(0); +perf_event_d(9) <= not next_tid(1) and is2_vld_l2(1); +perf_event_d(10) <= not next_tid(2) and is2_vld_l2(2); +perf_event_d(11) <= not next_tid(3) and is2_vld_l2(3); +perf_event_d(12) <= i_afi_is2_take_t(0); +perf_event_d(13) <= i_afi_is2_take_t(1); +perf_event_d(14) <= i_afi_is2_take_t(2); +perf_event_d(15) <= i_afi_is2_take_t(3); +perf_event_d(16) <= n_thread(0); +perf_event_d(17) <= n_thread(1); +perf_event_d(18) <= n_thread(2); +perf_event_d(19) <= n_thread(3); +perf_event_d(20) <= i_afi_is2_take_t(0) or n_thread(0); +perf_event_d(21) <= i_afi_is2_take_t(1) or n_thread(1); +perf_event_d(22) <= i_afi_is2_take_t(2) or n_thread(2); +perf_event_d(23) <= i_afi_is2_take_t(3) or n_thread(3); +perf_event_d(24) <= n_thread(0) and fdep_fiss_t0_is2_match; +perf_event_d(25) <= n_thread(1) and fdep_fiss_t1_is2_match; +perf_event_d(26) <= n_thread(2) and fdep_fiss_t2_is2_match; +perf_event_d(27) <= n_thread(3) and fdep_fiss_t3_is2_match; +perf_event_d(28) <= i_afi_is2_take_t(0) or (n_thread(0) and not fdep_fiss_t0_is2_to_ucode and not fdep_fiss_t0_is2_is_ucode); +perf_event_d(29) <= i_afi_is2_take_t(1) or (n_thread(1) and not fdep_fiss_t1_is2_to_ucode and not fdep_fiss_t1_is2_is_ucode); +perf_event_d(30) <= i_afi_is2_take_t(2) or (n_thread(2) and not fdep_fiss_t2_is2_to_ucode and not fdep_fiss_t2_is2_is_ucode); +perf_event_d(31) <= i_afi_is2_take_t(3) or (n_thread(3) and not fdep_fiss_t3_is2_to_ucode and not fdep_fiss_t3_is2_is_ucode); +fiss_perf_event_t0(0 TO 7) <= perf_event_l2(0) & + perf_event_l2(4) & + perf_event_l2(8) & + perf_event_l2(12) & + perf_event_l2(16) & + perf_event_l2(20) & + perf_event_l2(24) & + perf_event_l2(28); +fiss_perf_event_t1(0 TO 7) <= perf_event_l2(1) & + perf_event_l2(5) & + perf_event_l2(9) & + perf_event_l2(13) & + perf_event_l2(17) & + perf_event_l2(21) & + perf_event_l2(25) & + perf_event_l2(29); +fiss_perf_event_t2(0 TO 7) <= perf_event_l2(2) & + perf_event_l2(6) & + perf_event_l2(10) & + perf_event_l2(14) & + perf_event_l2(18) & + perf_event_l2(22) & + perf_event_l2(26) & + perf_event_l2(30); +fiss_perf_event_t3(0 TO 7) <= perf_event_l2(3) & + perf_event_l2(7) & + perf_event_l2(11) & + perf_event_l2(15) & + perf_event_l2(19) & + perf_event_l2(23) & + perf_event_l2(27) & + perf_event_l2(31); +fiss_dbg_data(0 TO 3) <= high_pri_mask_l2(0 to 3); +fiss_dbg_data(4 TO 7) <= med_pri_mask_l2(0 to 3); +fiss_dbg_data(8) <= hi_did3no0; +fiss_dbg_data(9) <= hi_did3no1; +fiss_dbg_data(10) <= hi_did3no2; +fiss_dbg_data(11) <= hi_did2no0; +fiss_dbg_data(12) <= hi_did2no1; +fiss_dbg_data(13) <= hi_did1no0; +fiss_dbg_data(14) <= md_did3no0; +fiss_dbg_data(15) <= md_did3no1; +fiss_dbg_data(16) <= md_did3no2; +fiss_dbg_data(17) <= md_did2no0; +fiss_dbg_data(18) <= md_did2no1; +fiss_dbg_data(19) <= md_did1no0; +fiss_dbg_data(20 TO 25) <= low_pri_counter0_l2(0 to 5); +fiss_dbg_data(26 TO 31) <= low_pri_counter1_l2(0 to 5); +fiss_dbg_data(32 TO 37) <= low_pri_counter2_l2(0 to 5); +fiss_dbg_data(38 TO 43) <= low_pri_counter3_l2(0 to 5); +fiss_dbg_data_d(44) <= iu_xu_is2_vld_int; +fiss_dbg_data_d(45) <= fiss_uc_is2_ucode_vld_int; +fiss_dbg_data_d(46 TO 49) <= iu_xu_is2_tid_int(0 to 3); +fiss_dbg_data_d(50 TO 81) <= iu_xu_is2_instr_int(0 to 31); +fiss_dbg_data_d(82) <= iu_xu_is2_pred_update_int; +fiss_dbg_data_d(83 TO 84) <= iu_xu_is2_pred_taken_cnt_int(0 to 1); +fiss_dbg_data_d(85 TO 87) <= iu_xu_is2_error_int(0 to 2); +fiss_dbg_data(44 TO 87) <= fiss_dbg_data_l2(44 to 87); +siv(0 TO scan_right) <= sov(1 to scan_right) & scan_in; +scan_out <= sov(0) and an_ac_scan_dis_dc_b; +END IUQ_FXU_ISSUE; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_ib_buff.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_ib_buff.vhdl new file mode 100644 index 0000000..535ae4a --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_ib_buff.vhdl @@ -0,0 +1,1116 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; use ieee.std_logic_1164.all; +library ibm; use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; +library support; +use support.power_logic_pkg.all; +library tri; use tri.tri_latches_pkg.all; +library work; use work.iuq_pkg.all; + +entity iuq_ib_buff is + generic(ibuff_data_width : integer := 50; + ibuff_ifar_width : integer := 22; + uc_ifar : integer := 21; + expand_type : integer := 2 ); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + pc_iu_sg_2 : in std_ulogic; + pc_iu_func_sl_thold_2 : in std_ulogic; + clkoff_b : in std_ulogic; + an_ac_scan_dis_dc_b : in std_ulogic; + tc_ac_ccflush_dc : in std_ulogic; + delay_lclkr : in std_ulogic; + mpw1_b : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + spr_dec_mask_pt_in : in std_ulogic_vector(0 to 31); + spr_dec_mask_pt_out : out std_ulogic_vector(0 to 31); + fdep_dbg_data_pt_in : in std_ulogic_vector(0 to 21); + fdep_dbg_data_pt_out : out std_ulogic_vector(0 to 21); + fdep_perf_event_pt_in : in std_ulogic_vector(0 to 11); + fdep_perf_event_pt_out : out std_ulogic_vector(0 to 11); + + pc_iu_trace_bus_enable : in std_ulogic; + pc_iu_event_bus_enable : in std_ulogic; + ib_dbg_data : out std_ulogic_vector(0 to 15); + ib_perf_event : out std_ulogic_vector(0 to 1); + + xu_iu_ib1_flush : in std_ulogic; + uc_flush : in std_ulogic; + + fdec_ibuf_stall : in std_ulogic; + + ib_ic_empty : out std_ulogic; + ib_ic_below_water : out std_ulogic; + + bp_ib_iu4_ifar : in EFF_IFAR; + bp_ib_iu4_val : in std_ulogic_vector(0 to 3); + bp_ib_iu3_0_instr : in std_ulogic_vector(0 to 31); + bp_ib_iu4_0_instr : in std_ulogic_vector(32 to 43); + bp_ib_iu4_1_instr : in std_ulogic_vector(0 to 43); + bp_ib_iu4_2_instr : in std_ulogic_vector(0 to 43); + bp_ib_iu4_3_instr : in std_ulogic_vector(0 to 43); + + uc_ib_iu4_ifar : in std_ulogic_vector(62-uc_ifar to 61); + uc_ib_iu4_val : in std_ulogic; + uc_ib_iu4_instr : in std_ulogic_vector(0 to 36); + + rm_ib_iu4_val : in std_ulogic; + rm_ib_iu4_force_ram : in std_ulogic; + rm_ib_iu4_instr : in std_ulogic_vector(0 to 35); + + ib_ic_iu5_redirect_tid : out std_ulogic; + + iu_au_ib1_valid : out std_ulogic; + iu_au_ib1_ifar : out EFF_IFAR; + iu_au_ib1_data : out std_ulogic_vector(0 to ibuff_data_width-1) +); + -- synopsys translate_off + + + -- synopsys translate_on +end iuq_ib_buff; + + +architecture iuq_ib_buff of iuq_ib_buff is + +constant command_width_full : integer := (ibuff_data_width+EFF_IFAR'length); +constant command_width_lite : integer := (ibuff_data_width+ibuff_ifar_width); + +constant bp_ib_iu4_0_instr_offset : natural := 0; +constant buffer1_valid_offset : natural := bp_ib_iu4_0_instr_offset + 32; +constant buffer2_valid_offset : natural := buffer1_valid_offset + 1; +constant buffer3_valid_offset : natural := buffer2_valid_offset + 1; +constant buffer4_valid_offset : natural := buffer3_valid_offset + 1; +constant buffer5_valid_offset : natural := buffer4_valid_offset + 1; +constant buffer6_valid_offset : natural := buffer5_valid_offset + 1; +constant buffer7_valid_offset : natural := buffer6_valid_offset + 1; +constant buffer1_data_offset : natural := buffer7_valid_offset + 1; +constant buffer2_data_offset : natural := buffer1_data_offset + command_width_lite; +constant buffer3_data_offset : natural := buffer2_data_offset + command_width_lite; +constant buffer4_data_offset : natural := buffer3_data_offset + command_width_lite; +constant buffer5_data_offset : natural := buffer4_data_offset + command_width_lite; +constant buffer6_data_offset : natural := buffer5_data_offset + command_width_lite; +constant buffer7_data_offset : natural := buffer6_data_offset + command_width_lite; +constant stall_buffer_data_offset : natural := buffer7_data_offset + command_width_lite; +constant buffer_ifar_offset : natural := stall_buffer_data_offset + command_width_full; +constant redirect_offset : natural := buffer_ifar_offset + (EFF_IFAR'length-ibuff_ifar_width); +constant stall_offset : natural := redirect_offset + 1; +constant buff1_sel_offset : natural := stall_offset + 3; +constant perf_event_offset : natural := buff1_sel_offset + 5; +constant ib_dbg_data_offset : natural := perf_event_offset + 2; +constant spare_offset : natural := ib_dbg_data_offset + 6; +constant trace_bus_enable_offset : natural := spare_offset + 8; +constant event_bus_enable_offset : natural := trace_bus_enable_offset + 1; +constant scan_right : natural := event_bus_enable_offset + 1 - 1; + +signal spare_l2 : std_ulogic_vector(0 to 7); + +signal ib_iu4_val : std_ulogic_vector(0 to 3); +signal ib_iu4_ifar : EFF_IFAR; +signal rm_iu4_0_instr : std_ulogic_vector(0 to ibuff_data_width-1); +signal uc_iu4_0_instr : std_ulogic_vector(0 to ibuff_data_width-1); +signal bp_iu4_0_instr : std_ulogic_vector(0 to ibuff_data_width-1); +signal ib_iu4_0_instr : std_ulogic_vector(0 to ibuff_data_width-1); +signal ib_iu4_1_instr : std_ulogic_vector(0 to ibuff_data_width-1); +signal ib_iu4_2_instr : std_ulogic_vector(0 to ibuff_data_width-1); +signal ib_iu4_3_instr : std_ulogic_vector(0 to ibuff_data_width-1); + +signal bp_ib_iu4_0_instr_d : std_ulogic_vector(0 to 31); +signal bp_ib_iu4_0_instr_l2 : std_ulogic_vector(0 to 31); +signal iu4_act : std_ulogic; + +signal uc_ib_iu4_ifar_int : EFF_IFAR; + +signal buffer1_valid_d : std_ulogic; +signal buffer1_valid_l2 : std_ulogic; +signal buffer2_valid_d : std_ulogic; +signal buffer2_valid_l2 : std_ulogic; +signal buffer3_valid_d : std_ulogic; +signal buffer3_valid_l2 : std_ulogic; +signal buffer4_valid_d : std_ulogic; +signal buffer4_valid_l2 : std_ulogic; +signal buffer5_valid_d : std_ulogic; +signal buffer5_valid_l2 : std_ulogic; +signal buffer6_valid_d : std_ulogic; +signal buffer6_valid_l2 : std_ulogic; +signal buffer7_valid_d : std_ulogic; +signal buffer7_valid_l2 : std_ulogic; + +signal buffer1_data_d : std_ulogic_vector(0 to command_width_lite-1); +signal buffer1_data_l2 : std_ulogic_vector(0 to command_width_lite-1); +signal buffer2_data_d : std_ulogic_vector(0 to command_width_lite-1); +signal buffer2_data_l2 : std_ulogic_vector(0 to command_width_lite-1); +signal buffer3_data_d : std_ulogic_vector(0 to command_width_lite-1); +signal buffer3_data_l2 : std_ulogic_vector(0 to command_width_lite-1); +signal buffer4_data_d : std_ulogic_vector(0 to command_width_lite-1); +signal buffer4_data_l2 : std_ulogic_vector(0 to command_width_lite-1); +signal buffer5_data_d : std_ulogic_vector(0 to command_width_lite-1); +signal buffer5_data_l2 : std_ulogic_vector(0 to command_width_lite-1); +signal buffer6_data_d : std_ulogic_vector(0 to command_width_lite-1); +signal buffer6_data_l2 : std_ulogic_vector(0 to command_width_lite-1); +signal buffer7_data_d : std_ulogic_vector(0 to command_width_lite-1); +signal buffer7_data_l2 : std_ulogic_vector(0 to command_width_lite-1); + +signal buffer_data : std_ulogic_vector(0 to command_width_full-1); +signal stall_buffer_data_d : std_ulogic_vector(0 to command_width_full-1); +signal stall_buffer_data_l2 : std_ulogic_vector(0 to command_width_full-1); +signal stall_d : std_ulogic_vector(0 to 2); +signal stall_l2 : std_ulogic_vector(0 to 2); +signal buff1_sel_d : std_ulogic_vector(0 to 4); +signal buff1_sel_l2 : std_ulogic_vector(0 to 4); + +signal buffer1_data : std_ulogic_vector(0 to command_width_full-1); +signal buffer_ifar_d : std_ulogic_vector(EFF_IFAR'left to EFF_IFAR'right-ibuff_ifar_width); +signal buffer_ifar_l2 : std_ulogic_vector(EFF_IFAR'left to EFF_IFAR'right-ibuff_ifar_width); +signal buffer_ifar_update : std_ulogic; +signal buffer_ifar_match : std_ulogic; +signal buffer_ifar_match_uc : std_ulogic; +signal redirect_d : std_ulogic; +signal redirect_l2 : std_ulogic; + +signal pc_ext_1 : std_ulogic_vector(60 to 61); +signal pc_ext_2 : std_ulogic_vector(60 to 61); +signal pc_ext_3 : std_ulogic_vector(60 to 61); + +signal stall_buffer_act : std_ulogic; +signal buffer1_data_act : std_ulogic; +signal buffer2_data_act : std_ulogic; +signal buffer3_data_act : std_ulogic; +signal buffer4_data_act : std_ulogic; +signal buffer5_data_act : std_ulogic; +signal buffer6_data_act : std_ulogic; +signal buffer7_data_act : std_ulogic; + +signal valid_out : std_ulogic; +signal data_out : std_ulogic_vector(0 to command_width_full-1); + +signal pc_iu_func_sl_thold_1 : std_ulogic; +signal pc_iu_func_sl_thold_0 : std_ulogic; +signal pc_iu_func_sl_thold_0_b : std_ulogic; +signal pc_iu_sg_1 : std_ulogic; +signal pc_iu_sg_0 : std_ulogic; +signal forcee : std_ulogic; + +signal siv : std_ulogic_vector(0 to scan_right); +signal sov : std_ulogic_vector(0 to scan_right); + +signal tiup : std_ulogic; + +signal valid_in : std_ulogic_vector(0 to 3); +signal valid_in_uc : std_ulogic; +signal valid_fast : std_ulogic; +signal valid_slow : std_ulogic; + +signal perf_event_d : std_ulogic_vector(0 to 1); +signal perf_event_l2 : std_ulogic_vector(0 to 1); + +signal ib_dbg_data_d : std_ulogic_vector(0 to 5); +signal ib_dbg_data_l2 : std_ulogic_vector(0 to 5); + +signal trace_bus_enable_d : std_ulogic; +signal trace_bus_enable_q : std_ulogic; +signal event_bus_enable_d : std_ulogic; +signal event_bus_enable_q : std_ulogic; + +signal act_dis : std_ulogic; +signal d_mode : std_ulogic; +signal mpw2_b : std_ulogic; + +begin + + +tiup <= '1'; + + +act_dis <= '0'; +d_mode <= '0'; +mpw2_b <= '1'; + + +spr_dec_mask_pt_out <= spr_dec_mask_pt_in; +fdep_dbg_data_pt_out <= fdep_dbg_data_pt_in; +fdep_perf_event_pt_out <= fdep_perf_event_pt_in; + + + + + +ib_iu4_val(0) <= rm_ib_iu4_val or uc_ib_iu4_val or bp_ib_iu4_val(0); + +ib_iu4_val(1 to 3) <= bp_ib_iu4_val(1 to 3); + +uc_ib_iu4_ifar_int(62-uc_ifar to 61) <= uc_ib_iu4_ifar; +uc_ib_iu4_ifar_int(EFF_IFAR'left to 61-uc_ifar) <= (others => '0'); + + +ib_iu4_ifar <= gate(uc_ib_iu4_ifar_int, uc_ib_iu4_val) or + gate(bp_ib_iu4_ifar , bp_ib_iu4_val(0)); + + +bp_ib_iu4_0_instr_d <= bp_ib_iu3_0_instr; + +rm_iu4_0_instr(0 to 49) <= rm_ib_iu4_instr(0 to 35) & "000000000" & rm_ib_iu4_force_ram & "0000"; +uc_iu4_0_instr(0 to 49) <= uc_ib_iu4_instr(0 to 35) & "000000" & uc_ib_iu4_instr(36) & "0000000"; +bp_iu4_0_instr(0 to 49) <= bp_ib_iu4_0_instr_l2(0 to 31) & "0000" & bp_ib_iu4_0_instr(32 to 37) & '0' & bp_ib_iu4_0_instr(38 to 39) & '0' & bp_ib_iu4_0_instr(40 to 43); + +ib_iu4_0_instr(0 to 49) <= gate(rm_iu4_0_instr(0 to 49), rm_ib_iu4_val) or + gate(uc_iu4_0_instr(0 to 49), uc_ib_iu4_val) or + gate(bp_iu4_0_instr(0 to 49), bp_ib_iu4_val(0)); + +ib_iu4_1_instr(0 to 49) <= bp_ib_iu4_1_instr(0 to 31) & "0000" & bp_ib_iu4_1_instr(32 to 37) & '0' & bp_ib_iu4_1_instr(38 to 39) & '0' & bp_ib_iu4_1_instr(40 to 43); +ib_iu4_2_instr(0 to 49) <= bp_ib_iu4_2_instr(0 to 31) & "0000" & bp_ib_iu4_2_instr(32 to 37) & '0' & bp_ib_iu4_2_instr(38 to 39) & '0' & bp_ib_iu4_2_instr(40 to 43); +ib_iu4_3_instr(0 to 49) <= bp_ib_iu4_3_instr(0 to 31) & "0000" & bp_ib_iu4_3_instr(32 to 37) & '0' & bp_ib_iu4_3_instr(38 to 39) & '0' & bp_ib_iu4_3_instr(40 to 43); + + +valid_slow <= (rm_ib_iu4_val or uc_ib_iu4_val) and not redirect_l2; +valid_fast <= bp_ib_iu4_val(0) and not redirect_l2; + +valid_in(0 to 3) <= gate(ib_iu4_val(0 to 3), not redirect_l2); +valid_in_uc <= uc_ib_iu4_val and not redirect_l2; + +with ib_iu4_ifar(60 to 61) select +pc_ext_1 <= "11" when "10", + "10" when "01", + "01" when others; +pc_ext_2 <= '1' & ib_iu4_ifar(61); +pc_ext_3 <= "11"; + + +buffer_ifar_d <= ib_iu4_ifar(EFF_IFAR'left to EFF_IFAR'right-ibuff_ifar_width) when buffer_ifar_update='1' else buffer_ifar_l2; + +check_vals:process(xu_iu_ib1_flush, uc_flush, valid_in, ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to EFF_IFAR'right), ib_iu4_0_instr, + pc_ext_1, pc_ext_2, pc_ext_3, stall_l2(0), + buffer1_valid_l2, buffer2_valid_l2, buffer3_valid_l2, + buffer4_valid_l2, buffer5_valid_l2, buffer6_valid_l2, buffer7_valid_l2, + buffer1_data_l2, buffer2_data_l2, buffer3_data_l2, + buffer4_data_l2, buffer5_data_l2, buffer6_data_l2, buffer7_data_l2, + ib_iu4_1_instr, ib_iu4_2_instr, ib_iu4_3_instr, buffer_ifar_match, buffer_ifar_match_uc, valid_fast, valid_slow, valid_in_uc, uc_iu4_0_instr) begin + + buffer1_valid_d <= buffer1_valid_l2; + buffer2_valid_d <= buffer2_valid_l2; + buffer3_valid_d <= buffer3_valid_l2; + buffer4_valid_d <= buffer4_valid_l2; + buffer5_valid_d <= buffer5_valid_l2; + buffer6_valid_d <= buffer6_valid_l2; + buffer7_valid_d <= buffer7_valid_l2; + + buffer1_data_d <= buffer1_data_l2; + buffer2_data_d <= buffer2_data_l2; + buffer3_data_d <= buffer3_data_l2; + buffer4_data_d <= buffer4_data_l2; + buffer5_data_d <= buffer5_data_l2; + buffer6_data_d <= buffer6_data_l2; + buffer7_data_d <= buffer7_data_l2; + + buffer_ifar_update <= '0'; + + if (stall_l2(0) = '1') then + if(buffer1_valid_l2 = '0') then + buffer1_valid_d <= valid_in(0); + buffer_ifar_update <= valid_in(0); + buffer2_valid_d <= valid_in(1); + buffer3_valid_d <= valid_in(2); + buffer4_valid_d <= valid_in(3); + buffer1_data_d <= ib_iu4_0_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to EFF_IFAR'right); + buffer2_data_d <= ib_iu4_1_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to 59) & pc_ext_1; + buffer3_data_d <= ib_iu4_2_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to 59) & pc_ext_2; + buffer4_data_d <= ib_iu4_3_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to 59) & pc_ext_3; + end if; + + if(buffer1_valid_l2 = '1' and buffer2_valid_l2 = '0' and buffer_ifar_match = '1') then + buffer2_valid_d <= valid_in(0); + buffer3_valid_d <= valid_in(1); + buffer4_valid_d <= valid_in(2); + buffer5_valid_d <= valid_in(3); + end if; + if(buffer1_valid_l2 = '1' and buffer2_valid_l2 = '0') then + buffer2_data_d <= ib_iu4_0_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to EFF_IFAR'right); + buffer3_data_d <= ib_iu4_1_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to 59) & pc_ext_1; + buffer4_data_d <= ib_iu4_2_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to 59) & pc_ext_2; + buffer5_data_d <= ib_iu4_3_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to 59) & pc_ext_3; + end if; + + if(buffer2_valid_l2 = '1' and buffer3_valid_l2 = '0' and buffer_ifar_match = '1') then + buffer3_valid_d <= valid_in(0); + buffer4_valid_d <= valid_in(1); + buffer5_valid_d <= valid_in(2); + buffer6_valid_d <= valid_in(3); + end if; + if(buffer2_valid_l2 = '1' and buffer3_valid_l2 = '0' ) then + buffer3_data_d <= ib_iu4_0_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to EFF_IFAR'right); + buffer4_data_d <= ib_iu4_1_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to 59) & pc_ext_1; + buffer5_data_d <= ib_iu4_2_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to 59) & pc_ext_2; + buffer6_data_d <= ib_iu4_3_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to 59) & pc_ext_3; + end if; + + if(buffer3_valid_l2 = '1' and buffer4_valid_l2 = '0' and buffer_ifar_match = '1') then + buffer4_valid_d <= valid_in(0); + buffer5_valid_d <= valid_in(1); + buffer6_valid_d <= valid_in(2); + buffer7_valid_d <= valid_in(3); + end if; + if(buffer3_valid_l2 = '1' and buffer4_valid_l2 = '0') then + buffer4_data_d <= ib_iu4_0_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to EFF_IFAR'right); + buffer5_data_d <= ib_iu4_1_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to 59) & pc_ext_1; + buffer6_data_d <= ib_iu4_2_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to 59) & pc_ext_2; + buffer7_data_d <= ib_iu4_3_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to 59) & pc_ext_3; + end if; + + if(buffer4_valid_l2 = '1' and buffer5_valid_l2 = '0' and buffer_ifar_match_uc = '1') then + buffer5_valid_d <= valid_in_uc; + end if; + if(buffer4_valid_l2 = '1' and buffer5_valid_l2 = '0') then + buffer5_data_d <= uc_iu4_0_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to EFF_IFAR'right); + end if; + + if(buffer5_valid_l2 = '1' and buffer6_valid_l2 = '0' and buffer_ifar_match_uc = '1') then + buffer6_valid_d <= valid_in_uc; + end if; + if(buffer5_valid_l2 = '1' and buffer6_valid_l2 = '0') then + buffer6_data_d <= uc_iu4_0_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to EFF_IFAR'right); + end if; + + + else + buffer1_data_d <= buffer2_data_l2; + buffer2_data_d <= buffer3_data_l2; + buffer3_data_d <= buffer4_data_l2; + buffer4_data_d <= buffer5_data_l2; + buffer5_data_d <= buffer6_data_l2; + buffer6_data_d <= buffer7_data_l2; + + buffer1_valid_d <= buffer2_valid_l2; + buffer2_valid_d <= buffer3_valid_l2; + buffer3_valid_d <= buffer4_valid_l2; + buffer4_valid_d <= buffer5_valid_l2; + buffer5_valid_d <= buffer6_valid_l2; + buffer6_valid_d <= buffer7_valid_l2; + buffer7_valid_d <= '0'; + + if(buffer1_valid_l2 = '0' and valid_fast = '1') then + buffer_ifar_update <= valid_in(0); + buffer1_valid_d <= valid_in(1); + buffer2_valid_d <= valid_in(2); + buffer3_valid_d <= valid_in(3); + buffer1_data_d <= ib_iu4_1_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to 59) & pc_ext_1; + buffer2_data_d <= ib_iu4_2_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to 59) & pc_ext_2; + buffer3_data_d <= ib_iu4_3_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to 59) & pc_ext_3; + end if; + + if((buffer1_valid_l2 = '1' and buffer2_valid_l2 = '0') or (buffer1_valid_l2 = '0' and valid_slow = '1')) then + buffer1_valid_d <= valid_in(0); + buffer_ifar_update <= valid_in(0); + buffer2_valid_d <= valid_in(1); + buffer3_valid_d <= valid_in(2); + buffer4_valid_d <= valid_in(3); + buffer1_data_d <= ib_iu4_0_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to EFF_IFAR'right); + buffer2_data_d <= ib_iu4_1_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to 59) & pc_ext_1; + buffer3_data_d <= ib_iu4_2_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to 59) & pc_ext_2; + buffer4_data_d <= ib_iu4_3_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to 59) & pc_ext_3; + end if; + + if(buffer2_valid_l2 = '1' and buffer3_valid_l2 = '0' and buffer_ifar_match = '1') then + buffer2_valid_d <= valid_in(0); + buffer3_valid_d <= valid_in(1); + buffer4_valid_d <= valid_in(2); + buffer5_valid_d <= valid_in(3); + end if; + if(buffer2_valid_l2 = '1' and buffer3_valid_l2 = '0') then + buffer2_data_d <= ib_iu4_0_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to EFF_IFAR'right); + buffer3_data_d <= ib_iu4_1_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to 59) & pc_ext_1; + buffer4_data_d <= ib_iu4_2_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to 59) & pc_ext_2; + buffer5_data_d <= ib_iu4_3_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to 59) & pc_ext_3; + end if; + + if(buffer3_valid_l2 = '1' and buffer4_valid_l2 = '0' and buffer_ifar_match = '1') then + buffer3_valid_d <= valid_in(0); + buffer4_valid_d <= valid_in(1); + buffer5_valid_d <= valid_in(2); + buffer6_valid_d <= valid_in(3); + end if; + if(buffer3_valid_l2 = '1' and buffer4_valid_l2 = '0' ) then + buffer3_data_d <= ib_iu4_0_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to EFF_IFAR'right); + buffer4_data_d <= ib_iu4_1_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to 59) & pc_ext_1; + buffer5_data_d <= ib_iu4_2_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to 59) & pc_ext_2; + buffer6_data_d <= ib_iu4_3_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to 59) & pc_ext_3; + end if; + + if(buffer4_valid_l2 = '1' and buffer5_valid_l2 = '0' and buffer_ifar_match_uc = '1') then + buffer4_valid_d <= valid_in_uc; + end if; + if(buffer4_valid_l2 = '1' and buffer5_valid_l2 = '0' ) then + buffer4_data_d <= uc_iu4_0_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to EFF_IFAR'right); + end if; + + if(buffer5_valid_l2 = '1' and buffer6_valid_l2 = '0' and buffer_ifar_match_uc = '1') then + buffer5_valid_d <= valid_in_uc; + end if; + if(buffer5_valid_l2 = '1' and buffer6_valid_l2 = '0' ) then + buffer5_data_d <= uc_iu4_0_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to EFF_IFAR'right); + end if; + + end if; + + if(xu_iu_ib1_flush = '1' or uc_flush = '1') then + buffer1_valid_d <= '0'; + buffer2_valid_d <= '0'; + buffer3_valid_d <= '0'; + buffer4_valid_d <= '0'; + buffer5_valid_d <= '0'; + buffer6_valid_d <= '0'; + buffer7_valid_d <= '0'; + end if; + +end process; + +buffer1_data_act <= not (stall_l2(0) and buffer1_valid_l2); +buffer2_data_act <= not (stall_l2(0) and buffer2_valid_l2); +buffer3_data_act <= not (stall_l2(0) and buffer3_valid_l2); +buffer4_data_act <= not (stall_l2(0) and buffer4_valid_l2); +buffer5_data_act <= not (stall_l2(0) and buffer5_valid_l2); +buffer6_data_act <= not (stall_l2(0) and buffer6_valid_l2); +buffer7_data_act <= not (stall_l2(0) and buffer7_valid_l2); + + + +ib_ic_empty <= not (buffer1_valid_l2 or stall_l2(0)); +ib_ic_below_water <= (not buffer4_valid_l2) or (not buffer5_valid_l2 and not stall_l2(0)); +iu4_act <= (not buffer4_valid_l2) or (not buffer5_valid_l2 and not stall_l2(0)); + +buffer1_data <= buffer1_data_l2(0 to ibuff_data_width-1) & + buffer_ifar_l2(EFF_IFAR'left to EFF_IFAR'right-ibuff_ifar_width) & + buffer1_data_l2(ibuff_data_width to command_width_lite-1); + +gen_uc_match1: if (ibuff_ifar_width < uc_ifar) generate +begin +buffer_ifar_match <= '1' when buffer_ifar_l2(EFF_IFAR'left to EFF_IFAR'right-ibuff_ifar_width) = ib_iu4_ifar(EFF_IFAR'left to EFF_IFAR'right-ibuff_ifar_width) else + '0'; +buffer_ifar_match_uc <= buffer_ifar_match; +end generate; + +gen_uc_match0: if (ibuff_ifar_width >= uc_ifar) generate +begin +buffer_ifar_match <= (not bp_ib_iu4_val(0)) or + (buffer_ifar_l2(EFF_IFAR'left to EFF_IFAR'right-ibuff_ifar_width) = bp_ib_iu4_ifar(EFF_IFAR'left to EFF_IFAR'right-ibuff_ifar_width)); +buffer_ifar_match_uc <= '1'; +end generate; + +redirect_d <= valid_in(0) and not xu_iu_ib1_flush and not uc_flush and not buffer_ifar_match and not buffer_ifar_update; + +ib_ic_iu5_redirect_tid <= redirect_l2; + + +stall_d(0) <= fdec_ibuf_stall; +stall_d(1) <= fdec_ibuf_stall; +stall_d(2) <= fdec_ibuf_stall; + +stall_buffer_data_d <= + buffer1_data when buffer1_valid_l2 = '1' else + ib_iu4_0_instr & ib_iu4_ifar; + + + +buff1_sel_d(0) <= buffer1_valid_d; +buff1_sel_d(1) <= buffer1_valid_d; +buff1_sel_d(2) <= buffer1_valid_d; +buff1_sel_d(3) <= buffer1_valid_d; +buff1_sel_d(4) <= buffer1_valid_d; + + +valid_out <= (buffer1_valid_l2 or valid_fast or stall_l2(0)); + + + + +buffer_data(0 to 7) <= buffer1_data(0 to 7) when buff1_sel_l2(1) = '1' else + bp_iu4_0_instr(0 to 7); + +buffer_data(8 to 15) <= buffer1_data(8 to 15) when buff1_sel_l2(2) = '1' else + bp_iu4_0_instr(8 to 15); + +buffer_data(16 to 23) <= buffer1_data(16 to 23) when buff1_sel_l2(3) = '1' else + bp_iu4_0_instr(16 to 23); + +buffer_data(24 to 31) <= buffer1_data(24 to 31) when buff1_sel_l2(4) = '1' else + bp_iu4_0_instr(24 to 31); + +buffer_data(32 to command_width_full-1) <= buffer1_data(32 to command_width_full-1) when buff1_sel_l2(0) = '1' else + (bp_iu4_0_instr(32 to 49) & bp_ib_iu4_ifar); + + +data_out(0 to 15) <= stall_buffer_data_l2(0 to 15) when stall_L2(1) = '1' else + buffer_data(0 to 15); + +data_out(16 to 31) <= stall_buffer_data_l2(16 to 31) when stall_L2(2) = '1' else + buffer_data(16 to 31); + +data_out(32 to command_width_full-1) <= stall_buffer_data_l2(32 to command_width_full-1) when stall_L2(0) = '1' else + buffer_data(32 to command_width_full-1); + +iu_au_ib1_valid <= valid_out; + +iu_au_ib1_data <= data_out(0 to ibuff_data_width-1); + +iu_au_ib1_ifar <= data_out(ibuff_data_width to command_width_full-1); + + + +perf_event_d(0) <= not (buffer1_valid_l2 or stall_l2(0)); +perf_event_d(1) <= redirect_l2; + +ib_perf_event(0) <= perf_event_l2(0); +ib_perf_event(1) <= perf_event_l2(1); + + + +ib_dbg_data_d(0 to 3) <= bp_ib_iu4_val(0 to 3); +ib_dbg_data_d(4) <= rm_ib_iu4_val; +ib_dbg_data_d(5) <= uc_ib_iu4_val; + +ib_dbg_data(0 to 5) <= ib_dbg_data_l2(0 to 5); +ib_dbg_data(6) <= redirect_l2; +ib_dbg_data(7) <= (not buffer4_valid_l2) or (not buffer5_valid_l2 and not stall_l2(0)); +ib_dbg_data(8) <= stall_l2(0); +ib_dbg_data(9) <= buffer1_valid_l2; +ib_dbg_data(10) <= buffer2_valid_l2; +ib_dbg_data(11) <= buffer3_valid_l2; +ib_dbg_data(12) <= buffer4_valid_l2; +ib_dbg_data(13) <= buffer5_valid_l2; +ib_dbg_data(14) <= buffer6_valid_l2; +ib_dbg_data(15) <= buffer7_valid_l2; + +bp_ib_iu4_0_instr_latch: tri_rlmreg_p + generic map (width => bp_ib_iu4_0_instr_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu4_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(bp_ib_iu4_0_instr_offset to bp_ib_iu4_0_instr_offset+bp_ib_iu4_0_instr_l2'length-1), + scout => sov(bp_ib_iu4_0_instr_offset to bp_ib_iu4_0_instr_offset+bp_ib_iu4_0_instr_l2'length-1), + din => bp_ib_iu4_0_instr_d(0 to bp_ib_iu4_0_instr_l2'length-1), + dout => bp_ib_iu4_0_instr_l2(0 to bp_ib_iu4_0_instr_l2'length-1) ); + +buffer1_data_latch: tri_rlmreg_p + generic map (width => buffer1_data_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => buffer1_data_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(buffer1_data_offset to buffer1_data_offset+buffer1_data_l2'length-1), + scout => sov(buffer1_data_offset to buffer1_data_offset+buffer1_data_l2'length-1), + din => buffer1_data_d(0 to command_width_lite-1), + dout => buffer1_data_l2(0 to command_width_lite-1) ); + +buffer2_data_latch: tri_rlmreg_p + generic map (width => buffer2_data_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => buffer2_data_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(buffer2_data_offset to buffer2_data_offset+buffer2_data_l2'length-1), + scout => sov(buffer2_data_offset to buffer2_data_offset+buffer2_data_l2'length-1), + din => buffer2_data_d(0 to command_width_lite-1), + dout => buffer2_data_l2(0 to command_width_lite-1) ); + +buffer3_data_latch: tri_rlmreg_p + generic map (width => buffer3_data_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => buffer3_data_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(buffer3_data_offset to buffer3_data_offset+buffer3_data_l2'length-1), + scout => sov(buffer3_data_offset to buffer3_data_offset+buffer3_data_l2'length-1), + din => buffer3_data_d(0 to command_width_lite-1), + dout => buffer3_data_l2(0 to command_width_lite-1) ); + +buffer4_data_latch: tri_rlmreg_p + generic map (width => buffer4_data_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => buffer4_data_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(buffer4_data_offset to buffer4_data_offset+buffer4_data_l2'length-1), + scout => sov(buffer4_data_offset to buffer4_data_offset+buffer4_data_l2'length-1), + din => buffer4_data_d(0 to command_width_lite-1), + dout => buffer4_data_l2(0 to command_width_lite-1) ); + +buffer5_data_latch: tri_rlmreg_p + generic map (width => buffer5_data_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => buffer5_data_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(buffer5_data_offset to buffer5_data_offset+buffer5_data_l2'length-1), + scout => sov(buffer5_data_offset to buffer5_data_offset+buffer5_data_l2'length-1), + din => buffer5_data_d(0 to command_width_lite-1), + dout => buffer5_data_l2(0 to command_width_lite-1) ); + +buffer6_data_latch: tri_rlmreg_p + generic map (width => buffer6_data_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => buffer6_data_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(buffer6_data_offset to buffer6_data_offset+buffer6_data_l2'length-1), + scout => sov(buffer6_data_offset to buffer6_data_offset+buffer6_data_l2'length-1), + din => buffer6_data_d(0 to command_width_lite-1), + dout => buffer6_data_l2(0 to command_width_lite-1) ); + +buffer7_data_latch: tri_rlmreg_p + generic map (width => buffer7_data_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => buffer7_data_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(buffer7_data_offset to buffer7_data_offset+buffer7_data_l2'length-1), + scout => sov(buffer7_data_offset to buffer7_data_offset+buffer7_data_l2'length-1), + din => buffer7_data_d(0 to command_width_lite-1), + dout => buffer7_data_l2(0 to command_width_lite-1) ); + +buffer1_valid_latch: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(buffer1_valid_offset), + scout => sov(buffer1_valid_offset), + din => buffer1_valid_d, + dout => buffer1_valid_l2 ); + +buffer2_valid_latch: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(buffer2_valid_offset), + scout => sov(buffer2_valid_offset), + din => buffer2_valid_d, + dout => buffer2_valid_l2 ); + +buffer3_valid_latch: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(buffer3_valid_offset), + scout => sov(buffer3_valid_offset), + din => buffer3_valid_d, + dout => buffer3_valid_l2 ); + +buffer4_valid_latch: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(buffer4_valid_offset), + scout => sov(buffer4_valid_offset), + din => buffer4_valid_d, + dout => buffer4_valid_l2 ); + +buffer5_valid_latch: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(buffer5_valid_offset), + scout => sov(buffer5_valid_offset), + din => buffer5_valid_d, + dout => buffer5_valid_l2 ); + +buffer6_valid_latch: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(buffer6_valid_offset), + scout => sov(buffer6_valid_offset), + din => buffer6_valid_d, + dout => buffer6_valid_l2 ); + +buffer7_valid_latch: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(buffer7_valid_offset), + scout => sov(buffer7_valid_offset), + din => buffer7_valid_d, + dout => buffer7_valid_l2 ); + +stall_buffer_act <= not stall_l2(0); +stall_buffer_data_latch: tri_rlmreg_p + generic map (width => stall_buffer_data_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => stall_buffer_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(stall_buffer_data_offset to stall_buffer_data_offset+stall_buffer_data_l2'length-1), + scout => sov(stall_buffer_data_offset to stall_buffer_data_offset+stall_buffer_data_l2'length-1), + din => stall_buffer_data_d(0 to command_width_full-1), + dout => stall_buffer_data_l2(0 to command_width_full-1) ); + +stall_latch: tri_rlmreg_p + generic map (width => stall_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(stall_offset to stall_offset+stall_l2'length-1), + scout => sov(stall_offset to stall_offset+stall_l2'length-1), + din => stall_d(0 to 2), + dout => stall_l2(0 to 2) ); + +buffer_ifar_latch: tri_rlmreg_p + generic map (width => buffer_ifar_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => valid_in(0), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(buffer_ifar_offset to buffer_ifar_offset+buffer_ifar_l2'length-1), + scout => sov(buffer_ifar_offset to buffer_ifar_offset+buffer_ifar_l2'length-1), + din => buffer_ifar_d, + dout => buffer_ifar_l2 ); + +redirect_latch: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(redirect_offset), + scout => sov(redirect_offset), + din => redirect_d, + dout => redirect_l2 ); + + + + +buff1_sel_latch: tri_rlmreg_p + generic map (width => buff1_sel_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(buff1_sel_offset to buff1_sel_offset+buff1_sel_l2'length-1), + scout => sov(buff1_sel_offset to buff1_sel_offset+buff1_sel_l2'length-1), + din => buff1_sel_d(0 to 4), + dout => buff1_sel_l2(0 to 4) ); + + +event_bus_enable_d <= pc_iu_event_bus_enable; + +event_enable_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(event_bus_enable_offset), + scout => sov(event_bus_enable_offset), + din => event_bus_enable_d, + dout => event_bus_enable_q); + +trace_bus_enable_d <= pc_iu_trace_bus_enable; + +trace_enable_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(trace_bus_enable_offset), + scout => sov(trace_bus_enable_offset), + din => trace_bus_enable_d, + dout => trace_bus_enable_q); + +perf_event_latch: tri_rlmreg_p + generic map (width => perf_event_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => event_bus_enable_q, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + + scin => siv(perf_event_offset to perf_event_offset+perf_event_l2'length-1), + scout => sov(perf_event_offset to perf_event_offset+perf_event_l2'length-1), + din => perf_event_d(0 to 1), + dout => perf_event_l2(0 to 1) ); + +ib_dbg_data_latch: tri_rlmreg_p + generic map (width => ib_dbg_data_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => trace_bus_enable_q, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + + scin => siv(ib_dbg_data_offset to ib_dbg_data_offset+ib_dbg_data_l2'length-1), + scout => sov(ib_dbg_data_offset to ib_dbg_data_offset+ib_dbg_data_l2'length-1), + din => ib_dbg_data_d, + dout => ib_dbg_data_l2 ); + +spare_latch: tri_rlmreg_p + generic map (width => spare_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(spare_offset to spare_offset + spare_l2'length-1), + scout => sov(spare_offset to spare_offset + spare_l2'length-1), + din => spare_l2, + dout => spare_l2); + + +perv_2to1_reg: tri_plat + generic map (width => 2, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_iu_func_sl_thold_2, + din(1) => pc_iu_sg_2, + q(0) => pc_iu_func_sl_thold_1, + q(1) => pc_iu_sg_1); + +perv_1to0_reg: tri_plat + generic map (width => 2, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_iu_func_sl_thold_1, + din(1) => pc_iu_sg_1, + q(0) => pc_iu_func_sl_thold_0, + q(1) => pc_iu_sg_0); + +perv_lcbor: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_b, + thold => pc_iu_func_sl_thold_0, + sg => pc_iu_sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => pc_iu_func_sl_thold_0_b); + + + + +siv(0 to scan_right) <= sov(1 to scan_right) & scan_in; +scan_out <= sov(0) and an_ac_scan_dis_dc_b; + + +end iuq_ib_buff; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_ib_buff_wrap.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_ib_buff_wrap.vhdl new file mode 100644 index 0000000..d985fed --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_ib_buff_wrap.vhdl @@ -0,0 +1,361 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; +use ieee.std_logic_1164.all; +library support; +use support.power_logic_pkg.all; +library work; +use work.iuq_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity iuq_ib_buff_wrap is + generic(expand_type : integer := 2; + uc_ifar : integer := 21); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + pc_iu_func_sl_thold_2 : in std_ulogic_vector(0 to 3); + pc_iu_sg_2 : in std_ulogic_vector(0 to 3); + clkoff_b : in std_ulogic_vector(0 to 3); + an_ac_scan_dis_dc_b : in std_ulogic_vector(0 to 3); + tc_ac_ccflush_dc : in std_ulogic; + delay_lclkr : in std_ulogic_vector(5 to 8); + mpw1_b : in std_ulogic_vector(5 to 8); + iuq_b0_scan_in : in std_ulogic; + iuq_b0_scan_out : out std_ulogic; + iuq_b1_scan_in : in std_ulogic; + iuq_b1_scan_out : out std_ulogic; + iuq_b2_scan_in : in std_ulogic; + iuq_b2_scan_out : out std_ulogic; + iuq_b3_scan_in : in std_ulogic; + iuq_b3_scan_out : out std_ulogic; + + spr_dec_mask_pt_in_t0 : in std_ulogic_vector(0 to 31); + spr_dec_mask_pt_in_t1 : in std_ulogic_vector(0 to 31); + spr_dec_mask_pt_in_t2 : in std_ulogic_vector(0 to 31); + spr_dec_mask_pt_in_t3 : in std_ulogic_vector(0 to 31); + spr_dec_mask_pt_out_t0 : out std_ulogic_vector(0 to 31); + spr_dec_mask_pt_out_t1 : out std_ulogic_vector(0 to 31); + spr_dec_mask_pt_out_t2 : out std_ulogic_vector(0 to 31); + spr_dec_mask_pt_out_t3 : out std_ulogic_vector(0 to 31); + fdep_dbg_data_pt_in : in std_ulogic_vector(0 to 87); + fdep_dbg_data_pt_out : out std_ulogic_vector(0 to 87); + fdep_perf_event_pt_in_t0 : in std_ulogic_vector(0 to 11); + fdep_perf_event_pt_in_t1 : in std_ulogic_vector(0 to 11); + fdep_perf_event_pt_in_t2 : in std_ulogic_vector(0 to 11); + fdep_perf_event_pt_in_t3 : in std_ulogic_vector(0 to 11); + fdep_perf_event_pt_out_t0 : out std_ulogic_vector(0 to 11); + fdep_perf_event_pt_out_t1 : out std_ulogic_vector(0 to 11); + fdep_perf_event_pt_out_t2 : out std_ulogic_vector(0 to 11); + fdep_perf_event_pt_out_t3 : out std_ulogic_vector(0 to 11); + + pc_iu_trace_bus_enable : in std_ulogic; + pc_iu_event_bus_enable : in std_ulogic; + ib_dbg_data : out std_ulogic_vector(0 to 63); + ib_perf_event_t0 : out std_ulogic_vector(0 to 1); + ib_perf_event_t1 : out std_ulogic_vector(0 to 1); + ib_perf_event_t2 : out std_ulogic_vector(0 to 1); + ib_perf_event_t3 : out std_ulogic_vector(0 to 1); + xu_iu_flush : in std_ulogic_vector(0 to 3); + uc_flush_tid : in std_ulogic_vector(0 to 3); + fdec_ibuf_stall_t0 : in std_ulogic; + fdec_ibuf_stall_t1 : in std_ulogic; + fdec_ibuf_stall_t2 : in std_ulogic; + fdec_ibuf_stall_t3 : in std_ulogic; + ib_ic_below_water : out std_ulogic_vector(0 to 3); + ib_ic_empty : out std_ulogic_vector(0 to 3); + bp_ib_iu4_t0_val : in std_ulogic_vector(0 to 3); + bp_ib_iu4_t1_val : in std_ulogic_vector(0 to 3); + bp_ib_iu4_t2_val : in std_ulogic_vector(0 to 3); + bp_ib_iu4_t3_val : in std_ulogic_vector(0 to 3); + bp_ib_iu4_ifar_t0 : in EFF_IFAR; + bp_ib_iu3_0_instr_t0 : in std_ulogic_vector(0 to 31); + bp_ib_iu4_0_instr_t0 : in std_ulogic_vector(32 to 43); + bp_ib_iu4_1_instr_t0 : in std_ulogic_vector(0 to 43); + bp_ib_iu4_2_instr_t0 : in std_ulogic_vector(0 to 43); + bp_ib_iu4_3_instr_t0 : in std_ulogic_vector(0 to 43); + bp_ib_iu4_ifar_t1 : in EFF_IFAR; + bp_ib_iu3_0_instr_t1 : in std_ulogic_vector(0 to 31); + bp_ib_iu4_0_instr_t1 : in std_ulogic_vector(32 to 43); + bp_ib_iu4_1_instr_t1 : in std_ulogic_vector(0 to 43); + bp_ib_iu4_2_instr_t1 : in std_ulogic_vector(0 to 43); + bp_ib_iu4_3_instr_t1 : in std_ulogic_vector(0 to 43); + bp_ib_iu4_ifar_t2 : in EFF_IFAR; + bp_ib_iu3_0_instr_t2 : in std_ulogic_vector(0 to 31); + bp_ib_iu4_0_instr_t2 : in std_ulogic_vector(32 to 43); + bp_ib_iu4_1_instr_t2 : in std_ulogic_vector(0 to 43); + bp_ib_iu4_2_instr_t2 : in std_ulogic_vector(0 to 43); + bp_ib_iu4_3_instr_t2 : in std_ulogic_vector(0 to 43); + bp_ib_iu4_ifar_t3 : in EFF_IFAR; + bp_ib_iu3_0_instr_t3 : in std_ulogic_vector(0 to 31); + bp_ib_iu4_0_instr_t3 : in std_ulogic_vector(32 to 43); + bp_ib_iu4_1_instr_t3 : in std_ulogic_vector(0 to 43); + bp_ib_iu4_2_instr_t3 : in std_ulogic_vector(0 to 43); + bp_ib_iu4_3_instr_t3 : in std_ulogic_vector(0 to 43); + uc_ib_iu4_val : in std_ulogic_vector(0 to 3); + uc_ib_iu4_ifar_t0 : in std_ulogic_vector(62-uc_ifar to 61); + uc_ib_iu4_instr_t0 : in std_ulogic_vector(0 to 36); + uc_ib_iu4_ifar_t1 : in std_ulogic_vector(62-uc_ifar to 61); + uc_ib_iu4_instr_t1 : in std_ulogic_vector(0 to 36); + uc_ib_iu4_ifar_t2 : in std_ulogic_vector(62-uc_ifar to 61); + uc_ib_iu4_instr_t2 : in std_ulogic_vector(0 to 36); + uc_ib_iu4_ifar_t3 : in std_ulogic_vector(62-uc_ifar to 61); + uc_ib_iu4_instr_t3 : in std_ulogic_vector(0 to 36); + rm_ib_iu4_val : in std_ulogic_vector(0 to 3); + rm_ib_iu4_force_ram_t0 : in std_ulogic; + rm_ib_iu4_instr_t0 : in std_ulogic_vector(0 to 35); + rm_ib_iu4_force_ram_t1 : in std_ulogic; + rm_ib_iu4_instr_t1 : in std_ulogic_vector(0 to 35); + rm_ib_iu4_force_ram_t2 : in std_ulogic; + rm_ib_iu4_instr_t2 : in std_ulogic_vector(0 to 35); + rm_ib_iu4_force_ram_t3 : in std_ulogic; + rm_ib_iu4_instr_t3 : in std_ulogic_vector(0 to 35); + ib_ic_iu5_redirect_tid : out std_ulogic_vector(0 to 3); + iu_au_ib1_instr_vld_t0 : out std_ulogic; + iu_au_ib1_instr_vld_t1 : out std_ulogic; + iu_au_ib1_instr_vld_t2 : out std_ulogic; + iu_au_ib1_instr_vld_t3 : out std_ulogic; + iu_au_ib1_ifar_t0 : out EFF_IFAR; + iu_au_ib1_ifar_t1 : out EFF_IFAR; + iu_au_ib1_ifar_t2 : out EFF_IFAR; + iu_au_ib1_ifar_t3 : out EFF_IFAR; + iu_au_ib1_data_t0 : out std_ulogic_vector(0 to 49); + iu_au_ib1_data_t1 : out std_ulogic_vector(0 to 49); + iu_au_ib1_data_t2 : out std_ulogic_vector(0 to 49); + iu_au_ib1_data_t3 : out std_ulogic_vector(0 to 49) +); +end iuq_ib_buff_wrap; +architecture iuq_ib_buff_wrap of iuq_ib_buff_wrap is +begin +ibuff0 : entity work.iuq_ib_buff +generic map( + uc_ifar => uc_ifar, + expand_type => expand_type ) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_iu_func_sl_thold_2 => pc_iu_func_sl_thold_2(0), + pc_iu_sg_2 => pc_iu_sg_2(0), + clkoff_b => clkoff_b(0), + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b(0), + tc_ac_ccflush_dc => tc_ac_ccflush_dc, + delay_lclkr => delay_lclkr(5+0), + mpw1_b => mpw1_b(5+0), + scan_in => iuq_b0_scan_in, + scan_out => iuq_b0_scan_out, + spr_dec_mask_pt_in => spr_dec_mask_pt_in_t0, + spr_dec_mask_pt_out => spr_dec_mask_pt_out_t0, + fdep_dbg_data_pt_in => fdep_dbg_data_pt_in(22*0 to 22*0+21), + fdep_dbg_data_pt_out => fdep_dbg_data_pt_out(22*0 to 22*0+21), + fdep_perf_event_pt_in => fdep_perf_event_pt_in_t0, + fdep_perf_event_pt_out => fdep_perf_event_pt_out_t0, + pc_iu_trace_bus_enable => pc_iu_trace_bus_enable, + pc_iu_event_bus_enable => pc_iu_event_bus_enable, + ib_dbg_data => ib_dbg_data(16*0 to 16*0+15), + ib_perf_event => ib_perf_event_t0, + xu_iu_ib1_flush => xu_iu_flush(0), + uc_flush => uc_flush_tid(0), + fdec_ibuf_stall => fdec_ibuf_stall_t0, + ib_ic_below_water => ib_ic_below_water(0), + ib_ic_empty => ib_ic_empty(0), + bp_ib_iu4_ifar => bp_ib_iu4_ifar_t0, + bp_ib_iu4_val => bp_ib_iu4_t0_val, + bp_ib_iu3_0_instr => bp_ib_iu3_0_instr_t0, + bp_ib_iu4_0_instr => bp_ib_iu4_0_instr_t0, + bp_ib_iu4_1_instr => bp_ib_iu4_1_instr_t0, + bp_ib_iu4_2_instr => bp_ib_iu4_2_instr_t0, + bp_ib_iu4_3_instr => bp_ib_iu4_3_instr_t0, + uc_ib_iu4_ifar => uc_ib_iu4_ifar_t0, + uc_ib_iu4_val => uc_ib_iu4_val(0), + uc_ib_iu4_instr => uc_ib_iu4_instr_t0, + rm_ib_iu4_val => rm_ib_iu4_val(0), + rm_ib_iu4_force_ram => rm_ib_iu4_force_ram_t0, + rm_ib_iu4_instr => rm_ib_iu4_instr_t0, + ib_ic_iu5_redirect_tid => ib_ic_iu5_redirect_tid(0), + iu_au_ib1_valid => iu_au_ib1_instr_vld_t0, + iu_au_ib1_ifar => iu_au_ib1_ifar_t0, + iu_au_ib1_data => iu_au_ib1_data_t0 +); +ibuff1 : entity work.iuq_ib_buff +generic map( + uc_ifar => uc_ifar, + expand_type => expand_type ) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_iu_func_sl_thold_2 => pc_iu_func_sl_thold_2(1), + pc_iu_sg_2 => pc_iu_sg_2(1), + clkoff_b => clkoff_b(1), + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b(1), + tc_ac_ccflush_dc => tc_ac_ccflush_dc, + delay_lclkr => delay_lclkr(5+1), + mpw1_b => mpw1_b(5+1), + scan_in => iuq_b1_scan_in, + scan_out => iuq_b1_scan_out, + spr_dec_mask_pt_in => spr_dec_mask_pt_in_t1, + spr_dec_mask_pt_out => spr_dec_mask_pt_out_t1, + fdep_dbg_data_pt_in => fdep_dbg_data_pt_in(22*1 to 22*1+21), + fdep_dbg_data_pt_out => fdep_dbg_data_pt_out(22*1 to 22*1+21), + fdep_perf_event_pt_in => fdep_perf_event_pt_in_t1, + fdep_perf_event_pt_out => fdep_perf_event_pt_out_t1, + pc_iu_trace_bus_enable => pc_iu_trace_bus_enable, + pc_iu_event_bus_enable => pc_iu_event_bus_enable, + ib_dbg_data => ib_dbg_data(16*1 to 16*1+15), + ib_perf_event => ib_perf_event_t1, + xu_iu_ib1_flush => xu_iu_flush(1), + uc_flush => uc_flush_tid(1), + fdec_ibuf_stall => fdec_ibuf_stall_t1, + ib_ic_below_water => ib_ic_below_water(1), + ib_ic_empty => ib_ic_empty(1), + bp_ib_iu4_ifar => bp_ib_iu4_ifar_t1, + bp_ib_iu4_val => bp_ib_iu4_t1_val, + bp_ib_iu3_0_instr => bp_ib_iu3_0_instr_t1, + bp_ib_iu4_0_instr => bp_ib_iu4_0_instr_t1, + bp_ib_iu4_1_instr => bp_ib_iu4_1_instr_t1, + bp_ib_iu4_2_instr => bp_ib_iu4_2_instr_t1, + bp_ib_iu4_3_instr => bp_ib_iu4_3_instr_t1, + uc_ib_iu4_ifar => uc_ib_iu4_ifar_t1, + uc_ib_iu4_val => uc_ib_iu4_val(1), + uc_ib_iu4_instr => uc_ib_iu4_instr_t1, + rm_ib_iu4_val => rm_ib_iu4_val(1), + rm_ib_iu4_force_ram => rm_ib_iu4_force_ram_t1, + rm_ib_iu4_instr => rm_ib_iu4_instr_t1, + ib_ic_iu5_redirect_tid => ib_ic_iu5_redirect_tid(1), + iu_au_ib1_valid => iu_au_ib1_instr_vld_t1, + iu_au_ib1_ifar => iu_au_ib1_ifar_t1, + iu_au_ib1_data => iu_au_ib1_data_t1 +); +ibuff2 : entity work.iuq_ib_buff +generic map( + uc_ifar => uc_ifar, + expand_type => expand_type ) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_iu_func_sl_thold_2 => pc_iu_func_sl_thold_2(2), + pc_iu_sg_2 => pc_iu_sg_2(2), + clkoff_b => clkoff_b(2), + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b(2), + tc_ac_ccflush_dc => tc_ac_ccflush_dc, + delay_lclkr => delay_lclkr(5+2), + mpw1_b => mpw1_b(5+2), + scan_in => iuq_b2_scan_in, + scan_out => iuq_b2_scan_out, + spr_dec_mask_pt_in => spr_dec_mask_pt_in_t2, + spr_dec_mask_pt_out => spr_dec_mask_pt_out_t2, + fdep_dbg_data_pt_in => fdep_dbg_data_pt_in(22*2 to 22*2+21), + fdep_dbg_data_pt_out => fdep_dbg_data_pt_out(22*2 to 22*2+21), + fdep_perf_event_pt_in => fdep_perf_event_pt_in_t2, + fdep_perf_event_pt_out => fdep_perf_event_pt_out_t2, + pc_iu_trace_bus_enable => pc_iu_trace_bus_enable, + pc_iu_event_bus_enable => pc_iu_event_bus_enable, + ib_dbg_data => ib_dbg_data(16*2 to 16*2+15), + ib_perf_event => ib_perf_event_t2, + xu_iu_ib1_flush => xu_iu_flush(2), + uc_flush => uc_flush_tid(2), + fdec_ibuf_stall => fdec_ibuf_stall_t2, + ib_ic_below_water => ib_ic_below_water(2), + ib_ic_empty => ib_ic_empty(2), + bp_ib_iu4_ifar => bp_ib_iu4_ifar_t2, + bp_ib_iu4_val => bp_ib_iu4_t2_val, + bp_ib_iu3_0_instr => bp_ib_iu3_0_instr_t2, + bp_ib_iu4_0_instr => bp_ib_iu4_0_instr_t2, + bp_ib_iu4_1_instr => bp_ib_iu4_1_instr_t2, + bp_ib_iu4_2_instr => bp_ib_iu4_2_instr_t2, + bp_ib_iu4_3_instr => bp_ib_iu4_3_instr_t2, + uc_ib_iu4_ifar => uc_ib_iu4_ifar_t2, + uc_ib_iu4_val => uc_ib_iu4_val(2), + uc_ib_iu4_instr => uc_ib_iu4_instr_t2, + rm_ib_iu4_val => rm_ib_iu4_val(2), + rm_ib_iu4_force_ram => rm_ib_iu4_force_ram_t2, + rm_ib_iu4_instr => rm_ib_iu4_instr_t2, + ib_ic_iu5_redirect_tid => ib_ic_iu5_redirect_tid(2), + iu_au_ib1_valid => iu_au_ib1_instr_vld_t2, + iu_au_ib1_ifar => iu_au_ib1_ifar_t2, + iu_au_ib1_data => iu_au_ib1_data_t2 +); +ibuff3 : entity work.iuq_ib_buff +generic map( + uc_ifar => uc_ifar, + expand_type => expand_type ) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_iu_func_sl_thold_2 => pc_iu_func_sl_thold_2(3), + pc_iu_sg_2 => pc_iu_sg_2(3), + clkoff_b => clkoff_b(3), + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b(3), + tc_ac_ccflush_dc => tc_ac_ccflush_dc, + delay_lclkr => delay_lclkr(5+3), + mpw1_b => mpw1_b(5+3), + scan_in => iuq_b3_scan_in, + scan_out => iuq_b3_scan_out, + spr_dec_mask_pt_in => spr_dec_mask_pt_in_t3, + spr_dec_mask_pt_out => spr_dec_mask_pt_out_t3, + fdep_dbg_data_pt_in => fdep_dbg_data_pt_in(22*3 to 22*3+21), + fdep_dbg_data_pt_out => fdep_dbg_data_pt_out(22*3 to 22*3+21), + fdep_perf_event_pt_in => fdep_perf_event_pt_in_t3, + fdep_perf_event_pt_out => fdep_perf_event_pt_out_t3, + pc_iu_trace_bus_enable => pc_iu_trace_bus_enable, + pc_iu_event_bus_enable => pc_iu_event_bus_enable, + ib_dbg_data => ib_dbg_data(16*3 to 16*3+15), + ib_perf_event => ib_perf_event_t3, + xu_iu_ib1_flush => xu_iu_flush(3), + uc_flush => uc_flush_tid(3), + fdec_ibuf_stall => fdec_ibuf_stall_t3, + ib_ic_below_water => ib_ic_below_water(3), + ib_ic_empty => ib_ic_empty(3), + bp_ib_iu4_ifar => bp_ib_iu4_ifar_t3, + bp_ib_iu4_val => bp_ib_iu4_t3_val, + bp_ib_iu3_0_instr => bp_ib_iu3_0_instr_t3, + bp_ib_iu4_0_instr => bp_ib_iu4_0_instr_t3, + bp_ib_iu4_1_instr => bp_ib_iu4_1_instr_t3, + bp_ib_iu4_2_instr => bp_ib_iu4_2_instr_t3, + bp_ib_iu4_3_instr => bp_ib_iu4_3_instr_t3, + uc_ib_iu4_ifar => uc_ib_iu4_ifar_t3, + uc_ib_iu4_val => uc_ib_iu4_val(3), + uc_ib_iu4_instr => uc_ib_iu4_instr_t3, + rm_ib_iu4_val => rm_ib_iu4_val(3), + rm_ib_iu4_force_ram => rm_ib_iu4_force_ram_t3, + rm_ib_iu4_instr => rm_ib_iu4_instr_t3, + ib_ic_iu5_redirect_tid => ib_ic_iu5_redirect_tid(3), + iu_au_ib1_valid => iu_au_ib1_instr_vld_t3, + iu_au_ib1_ifar => iu_au_ib1_ifar_t3, + iu_au_ib1_data => iu_au_ib1_data_t3 +); +end iuq_ib_buff_wrap; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_ic.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_ic.vhdl new file mode 100644 index 0000000..0e0712d --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_ic.vhdl @@ -0,0 +1,1355 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; +use ieee.std_logic_1164.all; +library support; +use support.power_logic_pkg.all; +library clib; +library tri; +use tri.tri_latches_pkg.all; +library work; +use work.iuq_pkg.all; + +entity iuq_ic is + generic(regmode : integer := 6; + bcfg_epn_0to15 : integer := 0; + bcfg_epn_16to31 : integer := 0; + bcfg_epn_32to47 : integer := (2**16)-1; + bcfg_epn_48to51 : integer := (2**4)-1; + bcfg_rpn_22to31 : integer := (2**10)-1; + bcfg_rpn_32to47 : integer := (2**16)-1; + bcfg_rpn_48to51 : integer := (2**4)-1; + expand_type : integer := 2 ); +port( + vcs : inout power_logic; + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + + tc_ac_ccflush_dc : in std_ulogic; + an_ac_scan_dis_dc_b : in std_ulogic; + an_ac_scan_diag_dc : in std_ulogic; + + pc_iu_func_sl_thold_2 : in std_ulogic; + pc_iu_func_slp_sl_thold_2 : in std_ulogic; + pc_iu_time_sl_thold_2 : in std_ulogic; + pc_iu_abst_sl_thold_2 : in std_ulogic; + pc_iu_abst_slp_sl_thold_2 : in std_ulogic; + pc_iu_repr_sl_thold_2 : in std_ulogic; + pc_iu_cfg_slp_sl_thold_2 : in std_ulogic; + pc_iu_regf_slp_sl_thold_2 : in std_ulogic; + pc_iu_ary_nsl_thold_2 : in std_ulogic; + pc_iu_ary_slp_nsl_thold_2 : in std_ulogic; + pc_iu_func_slp_nsl_thold_2 : in std_ulogic; + pc_iu_bolt_sl_thold_2 : in std_ulogic; + pc_iu_sg_2 : in std_ulogic; + pc_iu_fce_2 : in std_ulogic; + clkoff_b : in std_ulogic; + delay_lclkr : in std_ulogic_vector(0 to 1); + mpw1_b : in std_ulogic_vector(0 to 1); + g8t_clkoff_b : in std_ulogic; + g8t_d_mode : in std_ulogic; + g8t_delay_lclkr : in std_ulogic_vector(0 to 4); + g8t_mpw1_b : in std_ulogic_vector(0 to 4); + g8t_mpw2_b : in std_ulogic; + g6t_clkoff_b : in std_ulogic; + g6t_d_mode : in std_ulogic; + g6t_delay_lclkr : in std_ulogic_vector(0 to 3); + g6t_mpw1_b : in std_ulogic_vector(0 to 4); + g6t_mpw2_b : in std_ulogic; + cam_clkoff_b : in std_ulogic; + cam_d_mode : in std_ulogic; + cam_delay_lclkr : in std_ulogic_vector(0 to 4); + cam_mpw1_b : in std_ulogic_vector(0 to 4); + cam_mpw2_b : in std_ulogic; + + func_scan_in : in std_ulogic_vector(0 to 4); + func_scan_out : out std_ulogic_vector(0 to 4); + ac_ccfg_scan_in : in std_ulogic; + ac_ccfg_scan_out : out std_ulogic; + time_scan_in : in std_ulogic; + time_scan_out : out std_ulogic; + repr_scan_in : in std_ulogic; + repr_scan_out : out std_ulogic; + abst_scan_in : in std_ulogic_vector(0 to 2); + abst_scan_out : out std_ulogic_vector(0 to 2); + regf_scan_in : in std_ulogic_vector(0 to 4); + regf_scan_out : out std_ulogic_vector(0 to 4); + + uc_dbg_data : in std_ulogic_vector(0 to 87); + + pc_iu_trace_bus_enable : in std_ulogic; + pc_iu_debug_mux_ctrls : in std_ulogic_vector(0 to 15); + + debug_data_in : in std_ulogic_vector(0 to 87); + trace_triggers_in : in std_ulogic_vector(0 to 11); + + debug_data_out : out std_ulogic_vector(0 to 87); + trace_triggers_out : out std_ulogic_vector(0 to 11); + + pc_iu_event_bus_enable : in std_ulogic; + + ic_perf_event_t0 : out std_ulogic_vector(0 to 6); + ic_perf_event_t1 : out std_ulogic_vector(0 to 6); + ic_perf_event_t2 : out std_ulogic_vector(0 to 6); + ic_perf_event_t3 : out std_ulogic_vector(0 to 6); + ic_perf_event : out std_ulogic_vector(0 to 1); + + iu_pc_err_icache_parity : out std_ulogic; + iu_pc_err_icachedir_parity : out std_ulogic; + iu_pc_err_icachedir_multihit : out std_ulogic; + + pc_iu_inj_icache_parity : in std_ulogic; + pc_iu_inj_icachedir_parity : in std_ulogic; + pc_iu_inj_icachedir_multihit : in std_ulogic; + + pc_iu_abist_g8t_wenb : in std_ulogic; + pc_iu_abist_g8t1p_renb_0 : in std_ulogic; + pc_iu_abist_di_0 : in std_ulogic_vector(0 to 3); + pc_iu_abist_g8t_bw_1 : in std_ulogic; + pc_iu_abist_g8t_bw_0 : in std_ulogic; + pc_iu_abist_waddr_0 : in std_ulogic_vector(4 to 9); + pc_iu_abist_raddr_0 : in std_ulogic_vector(2 to 9); + pc_iu_abist_ena_dc : in std_ulogic; + pc_iu_abist_wl64_comp_ena : in std_ulogic; + pc_iu_abist_raw_dc_b : in std_ulogic; + pc_iu_abist_g8t_dcomp : in std_ulogic_vector(0 to 3); + pc_iu_abist_g6t_bw : in std_ulogic_vector(0 to 1); + pc_iu_abist_di_g6t_2r : in std_ulogic_vector(0 to 3); + pc_iu_abist_wl256_comp_ena : in std_ulogic; + pc_iu_abist_dcomp_g6t_2r : in std_ulogic_vector(0 to 3); + pc_iu_abist_g6t_r_wb : in std_ulogic; + an_ac_lbist_ary_wrt_thru_dc: in std_ulogic; + an_ac_lbist_en_dc : in std_ulogic; + an_ac_atpg_en_dc : in std_ulogic; + an_ac_grffence_en_dc : in std_ulogic; + + pc_iu_bo_enable_3 : in std_ulogic; + pc_iu_bo_reset : in std_ulogic; + pc_iu_bo_unload : in std_ulogic; + pc_iu_bo_repair : in std_ulogic; + pc_iu_bo_shdata : in std_ulogic; + pc_iu_bo_select : in std_ulogic_vector(0 to 3); + iu_pc_bo_fail : out std_ulogic_vector(0 to 3); + iu_pc_bo_diagout : out std_ulogic_vector(0 to 3); + + pc_iu_init_reset : in std_ulogic; + + xu_iu_rf1_val : in std_ulogic_vector(0 to 3); + xu_iu_rf1_is_eratre : in std_ulogic; + xu_iu_rf1_is_eratwe : in std_ulogic; + xu_iu_rf1_is_eratsx : in std_ulogic; + xu_iu_rf1_is_eratilx : in std_ulogic; + xu_iu_ex1_is_isync : in std_ulogic; + xu_iu_ex1_is_csync : in std_ulogic; + xu_iu_rf1_ws : in std_ulogic_vector(0 to 1); + xu_iu_rf1_t : in std_ulogic_vector(0 to 2); + xu_iu_ex1_rs_is : in std_ulogic_vector(0 to 8); + xu_iu_ex1_ra_entry : in std_ulogic_vector(0 to 3); + + xu_iu_ex1_rb : in std_ulogic_vector(64-(2**regmode) to 51); + xu_rf1_flush : in std_ulogic_vector(0 to 3); + xu_ex1_flush : in std_ulogic_vector(0 to 3); + xu_ex2_flush : in std_ulogic_vector(0 to 3); + xu_ex3_flush : in std_ulogic_vector(0 to 3); + xu_ex4_flush : in std_ulogic_vector(0 to 3); + xu_ex5_flush : in std_ulogic_vector(0 to 3); + xu_iu_ex4_rs_data : in std_ulogic_vector(64-(2**regmode) to 63); + xu_iu_msr_hv : in std_ulogic_vector(0 to 3); + xu_iu_msr_pr : in std_ulogic_vector(0 to 3); + xu_iu_msr_is : in std_ulogic_vector(0 to 3); + xu_iu_hid_mmu_mode : in std_ulogic; + xu_iu_spr_ccr2_ifratsc : in std_ulogic_vector(0 to 8); + xu_iu_spr_ccr2_ifrat : in std_ulogic; + xu_iu_xucr4_mmu_mchk : in std_ulogic; + iu_xu_ex4_data : out std_ulogic_vector(64-(2**regmode) to 63); + iu_xu_ierat_ex3_par_err : out std_ulogic_vector(0 to 3); + iu_xu_ierat_ex4_par_err : out std_ulogic_vector(0 to 3); + iu_xu_ierat_ex2_flush_req : out std_ulogic_vector(0 to 3); + + iu_mm_ierat_req : out std_ulogic; + iu_mm_ierat_epn : out std_ulogic_vector(0 to 51); + iu_mm_ierat_thdid : out std_ulogic_vector(0 to 3); + iu_mm_ierat_state : out std_ulogic_vector(0 to 3); + iu_mm_ierat_tid : out std_ulogic_vector(0 to 13); + iu_mm_ierat_flush : out std_ulogic_vector(0 to 3); + + mm_iu_ierat_rel_val : in std_ulogic_vector(0 to 4); + mm_iu_ierat_rel_data : in std_ulogic_vector(0 to 131); + + mm_iu_ierat_pid0 : in std_ulogic_vector(0 to 13); + mm_iu_ierat_pid1 : in std_ulogic_vector(0 to 13); + mm_iu_ierat_pid2 : in std_ulogic_vector(0 to 13); + mm_iu_ierat_pid3 : in std_ulogic_vector(0 to 13); + mm_iu_ierat_mmucr0_0 : in std_ulogic_vector(0 to 19); + mm_iu_ierat_mmucr0_1 : in std_ulogic_vector(0 to 19); + mm_iu_ierat_mmucr0_2 : in std_ulogic_vector(0 to 19); + mm_iu_ierat_mmucr0_3 : in std_ulogic_vector(0 to 19); + iu_mm_ierat_mmucr0 : out std_ulogic_vector(0 to 17); + iu_mm_ierat_mmucr0_we : out std_ulogic_vector(0 to 3); + mm_iu_ierat_mmucr1 : in std_ulogic_vector(0 to 8); + iu_mm_ierat_mmucr1 : out std_ulogic_vector(0 to 3); + iu_mm_ierat_mmucr1_we : out std_ulogic; + + mm_iu_ierat_snoop_coming : in std_ulogic; + mm_iu_ierat_snoop_val : in std_ulogic; + mm_iu_ierat_snoop_attr : in std_ulogic_vector(0 to 25); + mm_iu_ierat_snoop_vpn : in std_ulogic_vector(EFF_IFAR'left to 51); + iu_mm_ierat_snoop_ack : out std_ulogic; + + iu_mm_lmq_empty : out std_ulogic; + + ac_an_power_managed : in std_ulogic; + + xu_iu_run_thread : in std_ulogic_vector(0 to 3); + + xu_iu_flush : in std_ulogic_vector(0 to 3); + xu_iu_iu0_flush_ifar0 : in EFF_IFAR; + xu_iu_iu0_flush_ifar1 : in EFF_IFAR; + xu_iu_iu0_flush_ifar2 : in EFF_IFAR; + xu_iu_iu0_flush_ifar3 : in EFF_IFAR; + xu_iu_flush_2ucode : in std_ulogic_vector(0 to 3); + xu_iu_flush_2ucode_type : in std_ulogic_vector(0 to 3); + + xu_iu_msr_cm : in std_ulogic_vector(0 to 3); + + xu_iu_ex6_icbi_val : in std_ulogic_vector(0 to 3); + xu_iu_ex6_icbi_addr : in std_ulogic_vector(REAL_IFAR'left to 57); + + xu_iu_ici : in std_ulogic; + + spr_ic_cls : in std_ulogic; + spr_ic_clockgate_dis : in std_ulogic_vector(0 to 1); + spr_ic_icbi_ack_en : in std_ulogic; + spr_ic_bp_config : in std_ulogic_vector(0 to 3); + + spr_ic_idir_read : in std_ulogic; + spr_ic_idir_way : in std_ulogic_vector(0 to 1); + spr_ic_idir_row : in std_ulogic_vector(52 to 57); + spr_ic_pri_rand : in std_ulogic_vector(0 to 4); + spr_ic_pri_rand_always : in std_ulogic; + spr_ic_pri_rand_flush : in std_ulogic; + + ic_spr_idir_done : out std_ulogic; + ic_spr_idir_lru : out std_ulogic_vector(0 to 2); + ic_spr_idir_parity : out std_ulogic_vector(0 to 3); + ic_spr_idir_endian : out std_ulogic; + ic_spr_idir_valid : out std_ulogic; + ic_spr_idir_tag : out std_ulogic_vector(0 to 29); + + iu_xu_request : out std_ulogic; + iu_xu_thread : out std_ulogic_vector(0 to 3); + iu_xu_ra : out std_ulogic_vector(REAL_IFAR'left to 59); + iu_xu_wimge : out std_ulogic_vector(0 to 4); + iu_xu_userdef : out std_ulogic_vector(0 to 3); + + an_ac_reld_data_vld : in std_ulogic; + an_ac_reld_core_tag : in std_ulogic_vector(0 to 4); + an_ac_reld_qw : in std_ulogic_vector(57 to 59); + an_ac_reld_data : in std_ulogic_vector(0 to 127); + an_ac_reld_ecc_err : in std_ulogic; + an_ac_reld_ecc_err_ue : in std_ulogic; + + an_ac_back_inv : in std_ulogic; + an_ac_back_inv_addr : in std_ulogic_vector(REAL_IFAR'left to 57); + an_ac_back_inv_target : in std_ulogic; + + an_ac_icbi_ack : in std_ulogic; + an_ac_icbi_ack_thread : in std_ulogic_vector(0 to 1); + + bp_ib_iu4_ifar : in EFF_IFAR; + + bp_ic_iu5_hold_tid : in std_ulogic_vector(0 to 3); + bp_ic_iu5_redirect_tid : in std_ulogic_vector(0 to 3); + bp_ic_iu5_redirect_ifar : in EFF_IFAR; + + ic_bp_iu1_val : out std_ulogic; + ic_bp_iu1_tid : out std_ulogic_vector(0 to 3); + ic_bp_iu1_ifar : out std_ulogic_vector(52 to 59); + + ic_bp_iu3_val : out std_ulogic_vector(0 to 3); + ic_bp_iu3_tid : out std_ulogic_vector(0 to 3); + ic_bp_iu3_ifar : out EFF_IFAR; + ic_bp_iu3_2ucode : out std_ulogic; + ic_bp_iu3_2ucode_type : out std_ulogic; + ic_bp_iu3_error : out std_ulogic_vector(0 to 2); + ic_bp_iu3_flush : out std_ulogic; + + ic_bp_iu3_0_instr : out std_ulogic_vector(0 to 35); + ic_bp_iu3_1_instr : out std_ulogic_vector(0 to 35); + ic_bp_iu3_2_instr : out std_ulogic_vector(0 to 35); + ic_bp_iu3_3_instr : out std_ulogic_vector(0 to 35); + + ib_ic_empty : in std_ulogic_vector(0 to 3); + ib_ic_below_water : in std_ulogic_vector(0 to 3); + ib_ic_iu5_redirect_tid : in std_ulogic_vector(0 to 3); + + ic_fdep_load_quiesce : out std_ulogic_vector(0 to 3); + ic_fdep_icbi_ack : out std_ulogic_vector(0 to 3); + + uc_flush_tid : in std_ulogic_vector(0 to 3); + uc_ic_hold_thread : in std_ulogic_vector(0 to 3) + +); +-- synopsys translate_off +-- synopsys translate_on +end iuq_ic; +architecture iuq_ic of iuq_ic is +constant epn_width : integer := 52-EFF_IFAR'left; +constant rpn_width : integer := 52-REAL_IFAR'left; +constant rs_data_width : integer := 2**regmode; +constant data_out_width : integer := 2**regmode; +constant trigger_data_out_offset: natural := 0; +constant trace_data_out_offset : natural := trigger_data_out_offset + 12; +constant event_bus_enable_offset: natural := trace_data_out_offset + 88; +constant trace_bus_enable_offset: natural := event_bus_enable_offset + 1; +constant debug_mux_ctrls_offset : natural := trace_bus_enable_offset + 1; +constant scan_right : natural := debug_mux_ctrls_offset + 16-1; +signal iu_ierat_iu0_val : std_ulogic; +signal iu_ierat_iu0_thdid : std_ulogic_vector(0 to 3); +signal iu_ierat_iu0_ifar : std_ulogic_vector(0 to 51); +signal iu_ierat_iu0_flush : std_ulogic_vector(0 to 3); +signal iu_ierat_iu1_flush : std_ulogic_vector(0 to 3); +signal iu_ierat_iu1_back_inv : std_ulogic; +signal iu_ierat_ium1_back_inv : std_ulogic; +signal ierat_iu_iu2_rpn : std_ulogic_vector(22 to 51); +signal ierat_iu_iu2_wimge : std_ulogic_vector(0 to 4); +signal ierat_iu_iu2_u : std_ulogic_vector(0 to 3); +signal ierat_iu_iu2_error : std_ulogic_vector(0 to 2); +signal ierat_iu_iu2_miss : std_ulogic; +signal ierat_iu_iu2_multihit : std_ulogic; +signal ierat_iu_iu2_isi : std_ulogic; +signal ierat_iu_hold_req : std_ulogic_vector(0 to 3); +signal ierat_iu_iu2_flush_req : std_ulogic_vector(0 to 3); +signal ics_icd_dir_rd_act : std_ulogic; +signal ics_icd_data_rd_act : std_ulogic; +signal ics_icd_iu0_valid : std_ulogic; +signal ics_icd_iu0_tid : std_ulogic_vector(0 to 3); +signal ics_icd_iu0_ifar : EFF_IFAR; +signal ics_icd_iu0_inval : std_ulogic; +signal ics_icd_iu0_2ucode : std_ulogic; +signal ics_icd_iu0_2ucode_type : std_ulogic; +signal ics_icd_iu0_spr_idir_read: std_ulogic; +signal icd_ics_iu1_valid : std_ulogic; +signal icd_ics_iu1_tid : std_ulogic_vector(0 to 3); +signal icd_ics_iu1_ifar : EFF_IFAR; +signal icd_ics_iu1_2ucode : std_ulogic; +signal icd_ics_iu1_2ucode_type : std_ulogic; +signal ics_icd_all_flush_prev : std_ulogic_vector(0 to 3); +signal ics_icd_iu1_flush_tid : std_ulogic_vector(0 to 3); +signal ics_icd_iu2_flush_tid : std_ulogic_vector(0 to 3); +signal icd_ics_iu2_miss_flush_prev : std_ulogic_vector(0 to 3); +signal icd_ics_iu2_ifar_eff : EFF_IFAR; +signal icd_ics_iu2_2ucode : std_ulogic; +signal icd_ics_iu2_2ucode_type : std_ulogic; +signal icd_ics_iu3_parity_flush : std_ulogic_vector(0 to 3); +signal icd_ics_iu3_ifar : EFF_IFAR; +signal icd_ics_iu3_2ucode : std_ulogic; +signal icd_ics_iu3_2ucode_type : std_ulogic; +signal icm_ics_iu0_preload_val : std_ulogic; +signal icm_ics_iu0_preload_tid : std_ulogic_vector(0 to 3); +signal icm_ics_iu0_preload_ifar : std_ulogic_vector(52 to 59); +signal icm_ics_hold_thread : std_ulogic_vector(0 to 3); +signal icm_ics_hold_thread_dbg : std_ulogic_vector(0 to 3); +signal icm_ics_hold_iu0 : std_ulogic; +signal icm_ics_ecc_block_iu0 : std_ulogic_vector(0 to 3); +signal icm_ics_load_tid : std_ulogic_vector(0 to 3); +signal icm_ics_iu1_ecc_flush : std_ulogic; +signal icm_ics_iu2_miss_match_prev : std_ulogic; +signal ics_icm_iu2_flush_tid : std_ulogic_vector(0 to 3); +signal ics_icm_iu3_flush_tid : std_ulogic_vector(0 to 3); +signal ics_icm_iu0_ifar0 : std_ulogic_vector(46 to 52); +signal ics_icm_iu0_ifar1 : std_ulogic_vector(46 to 52); +signal ics_icm_iu0_ifar2 : std_ulogic_vector(46 to 52); +signal ics_icm_iu0_ifar3 : std_ulogic_vector(46 to 52); +signal ics_icm_iu0_inval : std_ulogic; +signal ics_icm_iu0_inval_addr : std_ulogic_vector(52 to 57); +signal icm_icd_lru_addr : std_ulogic_vector(52 to 57); +signal icm_icd_dir_inval : std_ulogic; +signal icm_icd_dir_val : std_ulogic; +signal icm_icd_data_write : std_ulogic; +signal icm_icd_reload_addr : std_ulogic_vector(52 to 59); +signal icm_icd_reload_data : std_ulogic_vector(0 to 161); +signal icm_icd_reload_way : std_ulogic_vector(0 to 3); +signal icm_icd_load_tid : std_ulogic_vector(0 to 3); +signal icm_icd_load_addr : EFF_IFAR; +signal icm_icd_load_2ucode : std_ulogic; +signal icm_icd_load_2ucode_type : std_ulogic; +signal icm_icd_dir_write : std_ulogic; +signal icm_icd_dir_write_addr : std_ulogic_vector(REAL_IFAR'left to 57); +signal icm_icd_dir_write_endian : std_ulogic; +signal icm_icd_dir_write_way : std_ulogic_vector(0 to 3); +signal icm_icd_lru_write : std_ulogic; +signal icm_icd_lru_write_addr : std_ulogic_vector(52 to 57); +signal icm_icd_lru_write_way : std_ulogic_vector(0 to 3); +signal icm_icd_ecc_inval : std_ulogic; +signal icm_icd_ecc_addr : std_ulogic_vector(52 to 57); +signal icm_icd_ecc_way : std_ulogic_vector(0 to 3); +signal icm_icd_iu3_ecc_fp_cancel: std_ulogic; +signal icm_icd_iu3_ecc_err : std_ulogic; +signal icm_icd_any_reld_r2 : std_ulogic; +signal icm_icd_any_checkecc : std_ulogic; +signal icd_icm_miss : std_ulogic; +signal icd_icm_tid : std_ulogic_vector(0 to 3); +signal icd_icm_addr_real : REAL_IFAR; +signal icd_icm_addr_eff : std_ulogic_vector(EFF_IFAR'left to 51); +signal icd_icm_wimge : std_ulogic_vector(0 to 4); +signal icd_icm_userdef : std_ulogic_vector(0 to 3); +signal icd_icm_2ucode : std_ulogic; +signal icd_icm_2ucode_type : std_ulogic; +signal icd_icm_iu3_erat_err : std_ulogic; +signal icd_icm_iu2_inval : std_ulogic; +signal icd_icm_ici : std_ulogic; +signal icd_icm_any_iu2_valid : std_ulogic; +signal icd_icm_row_lru : std_ulogic_vector(0 to 2); +signal icd_icm_row_val : std_ulogic_vector(0 to 3); +signal int_ic_bp_iu3_val : std_ulogic_vector(0 to 3); +signal int_ic_bp_iu3_0_instr : std_ulogic_vector(0 to 35); +signal int_ic_bp_iu3_1_instr : std_ulogic_vector(0 to 35); +signal int_ic_bp_iu3_2_instr : std_ulogic_vector(0 to 35); +signal int_ic_bp_iu3_3_instr : std_ulogic_vector(0 to 35); +signal trigger_data_out_d : std_ulogic_vector(0 to 11); +signal trigger_data_out_q : std_ulogic_vector(0 to 11); +signal trace_data_out_d : std_ulogic_vector(0 to 87); +signal trace_data_out_q : std_ulogic_vector(0 to 87); +signal sel_dbg_data : std_ulogic_vector(0 to 87); +signal dir_dbg_data0 : std_ulogic_vector(0 to 87); +signal dir_dbg_data1 : std_ulogic_vector(0 to 87); +signal dir_dbg_data2 : std_ulogic_vector(0 to 43); +signal dir_dbg_trigger0 : std_ulogic_vector(0 to 7); +signal dir_dbg_trigger1 : std_ulogic_vector(0 to 11); +signal miss_dbg_data0 : std_ulogic_vector(0 to 87); +signal miss_dbg_data1 : std_ulogic_vector(0 to 87); +signal miss_dbg_data2 : std_ulogic_vector(0 to 43); +signal miss_dbg_trigger : std_ulogic_vector(0 to 11); +signal iu3_dbg_data : std_ulogic_vector(0 to 87); +signal ierat_iu_debug_group0 : std_ulogic_vector(0 to 87); +signal ierat_iu_debug_group1 : std_ulogic_vector(0 to 87); +signal ierat_iu_debug_group2 : std_ulogic_vector(0 to 87); +signal ierat_iu_debug_group3 : std_ulogic_vector(0 to 87); +signal dbg_group0 : std_ulogic_vector(0 to 87); +signal dbg_group1 : std_ulogic_vector(0 to 87); +signal dbg_group2 : std_ulogic_vector(0 to 87); +signal dbg_group3 : std_ulogic_vector(0 to 87); +signal dbg_group4 : std_ulogic_vector(0 to 87); +signal dbg_group5 : std_ulogic_vector(0 to 87); +signal dbg_group6 : std_ulogic_vector(0 to 87); +signal dbg_group7 : std_ulogic_vector(0 to 87); +signal dbg_group8 : std_ulogic_vector(0 to 87); +signal dbg_group9 : std_ulogic_vector(0 to 87); +signal dbg_group10 : std_ulogic_vector(0 to 87); +signal dbg_group11 : std_ulogic_vector(0 to 87); +signal dbg_group12 : std_ulogic_vector(0 to 87); +signal dbg_group13 : std_ulogic_vector(0 to 87); +signal dbg_group14 : std_ulogic_vector(0 to 87); +signal dbg_group15 : std_ulogic_vector(0 to 87); +signal trg_group0 : std_ulogic_vector(0 to 11); +signal trg_group1 : std_ulogic_vector(0 to 11); +signal trg_group2 : std_ulogic_vector(0 to 11); +signal trg_group3 : std_ulogic_vector(0 to 11); +signal pc_iu_func_sl_thold_1 : std_ulogic; +signal pc_iu_func_sl_thold_0 : std_ulogic; +signal pc_iu_func_sl_thold_0_b : std_ulogic; +signal pc_iu_func_slp_sl_thold_1: std_ulogic; +signal pc_iu_func_slp_sl_thold_0: std_ulogic; +signal pc_iu_func_slp_sl_thold_0_b : std_ulogic; +signal pc_iu_time_sl_thold_1 : std_ulogic; +signal pc_iu_time_sl_thold_0 : std_ulogic; +signal pc_iu_abst_sl_thold_1 : std_ulogic; +signal pc_iu_abst_sl_thold_0 : std_ulogic; +signal pc_iu_abst_sl_thold_0_b : std_ulogic; +signal pc_iu_abst_slp_sl_thold_1: std_ulogic; +signal pc_iu_abst_slp_sl_thold_0: std_ulogic; +signal pc_iu_repr_sl_thold_1 : std_ulogic; +signal pc_iu_repr_sl_thold_0 : std_ulogic; +signal pc_iu_ary_nsl_thold_1 : std_ulogic; +signal pc_iu_ary_nsl_thold_0 : std_ulogic; +signal pc_iu_ary_slp_nsl_thold_1: std_ulogic; +signal pc_iu_ary_slp_nsl_thold_0: std_ulogic; +signal pc_iu_regf_slp_sl_thold_1: std_ulogic; +signal pc_iu_regf_slp_sl_thold_0: std_ulogic; +signal regf_slat_slp_sl_thold_0_b: std_ulogic; +signal pc_iu_bolt_sl_thold_1 : std_ulogic; +signal pc_iu_bolt_sl_thold_0 : std_ulogic; +signal pc_iu_sg_1 : std_ulogic; +signal pc_iu_sg_0 : std_ulogic; +signal forcee : std_ulogic; +signal funcslp_force : std_ulogic; +signal abst_force : std_ulogic; +signal pc_iu_bo_enable_2 : std_ulogic; +signal ierat_func_scan_in : std_ulogic_vector(0 to 1); +signal sel_func_scan_in : std_ulogic; +signal dir_func_scan_in : std_ulogic_vector(0 to 1); +signal miss_func_scan_in : std_ulogic; +signal ierat_func_scan_out : std_ulogic_vector(0 to 1); +signal sel_func_scan_out : std_ulogic; +signal dir_func_scan_out : std_ulogic_vector(0 to 1); +signal miss_func_scan_out : std_ulogic; +signal siv : std_ulogic_vector(0 to scan_right); +signal sov : std_ulogic_vector(0 to scan_right); +signal tsiv : std_ulogic_vector(0 to 1); +signal tsov : std_ulogic_vector(0 to 1); +signal func_scan_in_cam : std_ulogic; +signal func_scan_out_cam : std_ulogic; +signal regf_scan_out_cam : std_ulogic_vector(0 to 4); +signal ac_ccfg_scan_out_int : std_ulogic; +signal event_bus_enable_d : std_ulogic; +signal event_bus_enable_q : std_ulogic; +signal trace_bus_enable_d : std_ulogic; +signal trace_bus_enable_q : std_ulogic; +signal debug_mux_ctrls_d : std_ulogic_vector(0 to 15); +signal debug_mux_ctrls_q : std_ulogic_vector(0 to 15); +signal tiup : std_ulogic; +signal act_dis : std_ulogic; +signal d_mode : std_ulogic; +signal mpw2_b : std_ulogic; +signal g6t_act_dis : std_ulogic; +signal cam_act_dis : std_ulogic; +begin +tiup <= '1'; +act_dis <= '0'; +d_mode <= '0'; +mpw2_b <= '1'; +g6t_act_dis <= '0'; +cam_act_dis <= '0'; +iuq_ic_ierat0 : entity work.iuq_ic_ierat +generic map(thdid_width => 4, + epn_width => epn_width, + rpn_width => rpn_width, + bcfg_epn_0to15 => bcfg_epn_0to15, + bcfg_epn_16to31 => bcfg_epn_16to31, + bcfg_epn_32to47 => bcfg_epn_32to47, + bcfg_epn_48to51 => bcfg_epn_48to51, + bcfg_rpn_22to31 => bcfg_rpn_22to31, + bcfg_rpn_32to47 => bcfg_rpn_32to47, + bcfg_rpn_48to51 => bcfg_rpn_48to51, + rs_data_width => rs_data_width, + data_out_width => data_out_width, + expand_type => expand_type) +port map( + gnd => gnd, + vdd => vdd, + vcs => vcs, + nclk => nclk, + pc_iu_init_reset => pc_iu_init_reset, + tc_ccflush_dc => tc_ac_ccflush_dc, + tc_scan_dis_dc_b => an_ac_scan_dis_dc_b, + tc_scan_diag_dc => an_ac_scan_diag_dc, + tc_lbist_en_dc => an_ac_lbist_en_dc, + an_ac_atpg_en_dc => an_ac_atpg_en_dc, + an_ac_grffence_en_dc => an_ac_grffence_en_dc, + + lcb_d_mode_dc => d_mode, + lcb_clkoff_dc_b => clkoff_b, + lcb_act_dis_dc => act_dis, + lcb_mpw1_dc_b => mpw1_b, + lcb_mpw2_dc_b => mpw2_b, + lcb_delay_lclkr_dc => delay_lclkr, + pc_iu_func_sl_thold_2 => pc_iu_func_sl_thold_2, + pc_iu_func_slp_sl_thold_2 => pc_iu_func_slp_sl_thold_2, + pc_iu_func_slp_nsl_thold_2 => pc_iu_func_slp_nsl_thold_2, + pc_iu_cfg_slp_sl_thold_2 => pc_iu_cfg_slp_sl_thold_2, + pc_iu_regf_slp_sl_thold_2 => pc_iu_regf_slp_sl_thold_2, + pc_iu_time_sl_thold_2 => pc_iu_time_sl_thold_2, + pc_iu_sg_2 => pc_iu_sg_2, + pc_iu_fce_2 => pc_iu_fce_2, + + cam_clkoff_b => cam_clkoff_b, + cam_act_dis => cam_act_dis, + cam_d_mode => cam_d_mode, + cam_delay_lclkr => cam_delay_lclkr, + cam_mpw1_b => cam_mpw1_b, + cam_mpw2_b => cam_mpw2_b, + ac_func_scan_in => ierat_func_scan_in, + ac_func_scan_out => ierat_func_scan_out, + ac_ccfg_scan_in => ac_ccfg_scan_in, + ac_ccfg_scan_out => ac_ccfg_scan_out_int, + func_scan_in_cam => func_scan_in_cam, + func_scan_out_cam => func_scan_out_cam, + time_scan_in => tsiv(0), + time_scan_out => tsov(0), + regf_scan_in => regf_scan_in, + regf_scan_out => regf_scan_out_cam, + iu_ierat_iu0_val => iu_ierat_iu0_val, + iu_ierat_iu0_thdid => iu_ierat_iu0_thdid, + iu_ierat_iu0_ifar => iu_ierat_iu0_ifar, + iu_ierat_iu0_flush => iu_ierat_iu0_flush, + iu_ierat_iu1_flush => iu_ierat_iu1_flush, + iu_ierat_iu1_back_inv => iu_ierat_iu1_back_inv, + iu_ierat_ium1_back_inv => iu_ierat_ium1_back_inv, + spr_ic_clockgate_dis => spr_ic_clockgate_dis(1), + ierat_iu_iu2_rpn => ierat_iu_iu2_rpn, + ierat_iu_iu2_wimge => ierat_iu_iu2_wimge, + ierat_iu_iu2_u => ierat_iu_iu2_u, + ierat_iu_iu2_error => ierat_iu_iu2_error, + ierat_iu_iu2_miss => ierat_iu_iu2_miss, + ierat_iu_iu2_multihit => ierat_iu_iu2_multihit, + ierat_iu_iu2_isi => ierat_iu_iu2_isi, + xu_iu_rf1_val => xu_iu_rf1_val, + xu_iu_rf1_is_eratre => xu_iu_rf1_is_eratre, + xu_iu_rf1_is_eratwe => xu_iu_rf1_is_eratwe, + xu_iu_rf1_is_eratsx => xu_iu_rf1_is_eratsx, + xu_iu_rf1_is_eratilx => xu_iu_rf1_is_eratilx, + xu_iu_ex1_is_isync => xu_iu_ex1_is_isync, + xu_iu_ex1_is_csync => xu_iu_ex1_is_csync, + xu_iu_rf1_ws => xu_iu_rf1_ws, + xu_iu_rf1_t => xu_iu_rf1_t, + xu_iu_ex1_rs_is => xu_iu_ex1_rs_is, + xu_iu_ex1_ra_entry => xu_iu_ex1_ra_entry, + xu_iu_ex1_rb => xu_iu_ex1_rb, + xu_iu_flush => xu_iu_flush, + xu_rf1_flush => xu_rf1_flush, + xu_ex1_flush => xu_ex1_flush, + xu_ex2_flush => xu_ex2_flush, + xu_ex3_flush => xu_ex3_flush, + xu_ex4_flush => xu_ex4_flush, + xu_ex5_flush => xu_ex5_flush, + xu_iu_ex4_rs_data => xu_iu_ex4_rs_data, + xu_iu_msr_hv => xu_iu_msr_hv, + xu_iu_msr_pr => xu_iu_msr_pr, + xu_iu_msr_is => xu_iu_msr_is, + xu_iu_msr_cm => xu_iu_msr_cm, + xu_iu_hid_mmu_mode => xu_iu_hid_mmu_mode, + xu_iu_spr_ccr2_ifrat => xu_iu_spr_ccr2_ifrat, + xu_iu_spr_ccr2_ifratsc => xu_iu_spr_ccr2_ifratsc, + xu_iu_xucr4_mmu_mchk => xu_iu_xucr4_mmu_mchk, + ierat_iu_hold_req => ierat_iu_hold_req, + ierat_iu_iu2_flush_req => ierat_iu_iu2_flush_req, + iu_xu_ex4_data => iu_xu_ex4_data, + iu_xu_ierat_ex3_par_err => iu_xu_ierat_ex3_par_err, + iu_xu_ierat_ex4_par_err => iu_xu_ierat_ex4_par_err, + iu_xu_ierat_ex2_flush_req => iu_xu_ierat_ex2_flush_req, + iu_mm_ierat_req => iu_mm_ierat_req, + iu_mm_ierat_thdid => iu_mm_ierat_thdid, + iu_mm_ierat_state => iu_mm_ierat_state, + iu_mm_ierat_tid => iu_mm_ierat_tid, + iu_mm_ierat_flush => iu_mm_ierat_flush, + mm_iu_ierat_rel_val => mm_iu_ierat_rel_val, + mm_iu_ierat_rel_data => mm_iu_ierat_rel_data, + mm_iu_ierat_pid0 => mm_iu_ierat_pid0, + mm_iu_ierat_pid1 => mm_iu_ierat_pid1, + mm_iu_ierat_pid2 => mm_iu_ierat_pid2, + mm_iu_ierat_pid3 => mm_iu_ierat_pid3, + mm_iu_ierat_mmucr0_0 => mm_iu_ierat_mmucr0_0, + mm_iu_ierat_mmucr0_1 => mm_iu_ierat_mmucr0_1, + mm_iu_ierat_mmucr0_2 => mm_iu_ierat_mmucr0_2, + mm_iu_ierat_mmucr0_3 => mm_iu_ierat_mmucr0_3, + iu_mm_ierat_mmucr0 => iu_mm_ierat_mmucr0, + iu_mm_ierat_mmucr0_we => iu_mm_ierat_mmucr0_we, + mm_iu_ierat_mmucr1 => mm_iu_ierat_mmucr1, + iu_mm_ierat_mmucr1 => iu_mm_ierat_mmucr1, + iu_mm_ierat_mmucr1_we => iu_mm_ierat_mmucr1_we, + mm_iu_ierat_snoop_coming => mm_iu_ierat_snoop_coming, + mm_iu_ierat_snoop_val => mm_iu_ierat_snoop_val, + mm_iu_ierat_snoop_attr => mm_iu_ierat_snoop_attr, + mm_iu_ierat_snoop_vpn => mm_iu_ierat_snoop_vpn, + iu_mm_ierat_snoop_ack => iu_mm_ierat_snoop_ack, + pc_iu_trace_bus_enable => pc_iu_trace_bus_enable, + ierat_iu_debug_group0 => ierat_iu_debug_group0, + ierat_iu_debug_group1 => ierat_iu_debug_group1, + ierat_iu_debug_group2 => ierat_iu_debug_group2, + ierat_iu_debug_group3 => ierat_iu_debug_group3 +); +iuq_ic_select0 : entity work.iuq_ic_select +generic map(expand_type => expand_type) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_iu_func_sl_thold_0_b => pc_iu_func_sl_thold_0_b, + pc_iu_func_slp_sl_thold_0_b => pc_iu_func_slp_sl_thold_0_b, + pc_iu_sg_0 => pc_iu_sg_0, + forcee => forcee, + funcslp_force => funcslp_force, + d_mode => d_mode, + delay_lclkr => delay_lclkr(0), + mpw1_b => mpw1_b(0), + mpw2_b => mpw2_b, + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b, + func_scan_in => sel_func_scan_in, + func_scan_out => sel_func_scan_out, + ac_an_power_managed => ac_an_power_managed, + xu_iu_run_thread => xu_iu_run_thread, + xu_iu_flush => xu_iu_flush, + xu_iu_iu0_flush_ifar0 => xu_iu_iu0_flush_ifar0, + xu_iu_iu0_flush_ifar1 => xu_iu_iu0_flush_ifar1, + xu_iu_iu0_flush_ifar2 => xu_iu_iu0_flush_ifar2, + xu_iu_iu0_flush_ifar3 => xu_iu_iu0_flush_ifar3, + xu_iu_flush_2ucode => xu_iu_flush_2ucode, + xu_iu_flush_2ucode_type => xu_iu_flush_2ucode_type, + xu_iu_msr_cm => xu_iu_msr_cm, + xu_iu_ex6_icbi_val => xu_iu_ex6_icbi_val, + xu_iu_ex6_icbi_addr => xu_iu_ex6_icbi_addr, + an_ac_back_inv => an_ac_back_inv, + an_ac_back_inv_addr => an_ac_back_inv_addr, + an_ac_back_inv_target => an_ac_back_inv_target, + an_ac_icbi_ack => an_ac_icbi_ack, + an_ac_icbi_ack_thread => an_ac_icbi_ack_thread, + spr_ic_clockgate_dis => spr_ic_clockgate_dis(0), + spr_ic_icbi_ack_en => spr_ic_icbi_ack_en, + spr_ic_idir_read => spr_ic_idir_read, + spr_ic_idir_row => spr_ic_idir_row, + spr_ic_pri_rand => spr_ic_pri_rand, + spr_ic_pri_rand_always => spr_ic_pri_rand_always, + spr_ic_pri_rand_flush => spr_ic_pri_rand_flush, + ic_perf_event_t0 => ic_perf_event_t0(2 to 3), + ic_perf_event_t1 => ic_perf_event_t1(2 to 3), + ic_perf_event_t2 => ic_perf_event_t2(2 to 3), + ic_perf_event_t3 => ic_perf_event_t3(2 to 3), + iu_ierat_iu0_val => iu_ierat_iu0_val, + iu_ierat_iu0_thdid => iu_ierat_iu0_thdid, + iu_ierat_iu0_ifar => iu_ierat_iu0_ifar, + iu_ierat_iu0_flush => iu_ierat_iu0_flush, + iu_ierat_iu1_flush => iu_ierat_iu1_flush, + iu_ierat_ium1_back_inv => iu_ierat_ium1_back_inv, + ierat_iu_hold_req => ierat_iu_hold_req, + ierat_iu_iu2_flush_req => ierat_iu_iu2_flush_req, + ierat_iu_iu2_miss => ierat_iu_iu2_miss, + icm_ics_iu0_preload_val => icm_ics_iu0_preload_val, + icm_ics_iu0_preload_tid => icm_ics_iu0_preload_tid, + icm_ics_iu0_preload_ifar => icm_ics_iu0_preload_ifar, + icm_ics_hold_thread => icm_ics_hold_thread, + icm_ics_hold_thread_dbg => icm_ics_hold_thread_dbg, + icm_ics_hold_iu0 => icm_ics_hold_iu0, + icm_ics_ecc_block_iu0 => icm_ics_ecc_block_iu0, + icm_ics_load_tid => icm_ics_load_tid, + icm_ics_iu1_ecc_flush => icm_ics_iu1_ecc_flush, + icm_ics_iu2_miss_match_prev=> icm_ics_iu2_miss_match_prev, + ics_icm_iu2_flush_tid => ics_icm_iu2_flush_tid, + ics_icm_iu3_flush_tid => ics_icm_iu3_flush_tid, + ics_icm_iu0_ifar0 => ics_icm_iu0_ifar0, + ics_icm_iu0_ifar1 => ics_icm_iu0_ifar1, + ics_icm_iu0_ifar2 => ics_icm_iu0_ifar2, + ics_icm_iu0_ifar3 => ics_icm_iu0_ifar3, + ics_icm_iu0_inval => ics_icm_iu0_inval, + ics_icm_iu0_inval_addr => ics_icm_iu0_inval_addr, + ics_icd_dir_rd_act => ics_icd_dir_rd_act, + ics_icd_data_rd_act => ics_icd_data_rd_act, + ics_icd_iu0_valid => ics_icd_iu0_valid, + ics_icd_iu0_tid => ics_icd_iu0_tid, + ics_icd_iu0_ifar => ics_icd_iu0_ifar, + ics_icd_iu0_inval => ics_icd_iu0_inval, + ics_icd_iu0_2ucode => ics_icd_iu0_2ucode, + ics_icd_iu0_2ucode_type => ics_icd_iu0_2ucode_type, + ics_icd_iu0_spr_idir_read => ics_icd_iu0_spr_idir_read, + icd_ics_iu1_valid => icd_ics_iu1_valid, + icd_ics_iu1_tid => icd_ics_iu1_tid, + icd_ics_iu1_ifar => icd_ics_iu1_ifar, + icd_ics_iu1_2ucode => icd_ics_iu1_2ucode, + icd_ics_iu1_2ucode_type => icd_ics_iu1_2ucode_type, + ics_icd_all_flush_prev => ics_icd_all_flush_prev, + ics_icd_iu1_flush_tid => ics_icd_iu1_flush_tid, + ics_icd_iu2_flush_tid => ics_icd_iu2_flush_tid, + icd_ics_iu2_miss_flush_prev=> icd_ics_iu2_miss_flush_prev, + icd_ics_iu2_ifar_eff => icd_ics_iu2_ifar_eff, + icd_ics_iu2_2ucode => icd_ics_iu2_2ucode, + icd_ics_iu2_2ucode_type => icd_ics_iu2_2ucode_type, + icd_ics_iu3_parity_flush => icd_ics_iu3_parity_flush, + icd_ics_iu3_ifar => icd_ics_iu3_ifar, + icd_ics_iu3_2ucode => icd_ics_iu3_2ucode, + icd_ics_iu3_2ucode_type => icd_ics_iu3_2ucode_type, + ic_bp_iu1_val => ic_bp_iu1_val, + ic_bp_iu1_tid => ic_bp_iu1_tid, + ic_bp_iu1_ifar => ic_bp_iu1_ifar, + bp_ib_iu4_ifar => bp_ib_iu4_ifar, + bp_ic_iu5_hold_tid => bp_ic_iu5_hold_tid, + bp_ic_iu5_redirect_tid => bp_ic_iu5_redirect_tid, + bp_ic_iu5_redirect_ifar => bp_ic_iu5_redirect_ifar, + ib_ic_empty => ib_ic_empty, + ib_ic_below_water => ib_ic_below_water, + ib_ic_iu5_redirect_tid => ib_ic_iu5_redirect_tid, + ic_fdep_icbi_ack => ic_fdep_icbi_ack, + uc_flush_tid => uc_flush_tid, + uc_ic_hold_thread => uc_ic_hold_thread, + event_bus_enable => event_bus_enable_q, + sel_dbg_data => sel_dbg_data +); +iuq_ic_dir0 : entity work.iuq_ic_dir +generic map(expand_type => expand_type) +port map( + vcs => vcs, + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_iu_func_sl_thold_0_b => pc_iu_func_sl_thold_0_b, + pc_iu_func_slp_sl_thold_0_b => pc_iu_func_slp_sl_thold_0_b, + pc_iu_time_sl_thold_0 => pc_iu_time_sl_thold_0, + pc_iu_repr_sl_thold_0 => pc_iu_repr_sl_thold_0, + pc_iu_abst_sl_thold_0 => pc_iu_abst_sl_thold_0, + pc_iu_abst_sl_thold_0_b => pc_iu_abst_sl_thold_0_b, + pc_iu_abst_slp_sl_thold_0 => pc_iu_abst_slp_sl_thold_0, + pc_iu_ary_nsl_thold_0 => pc_iu_ary_nsl_thold_0, + pc_iu_ary_slp_nsl_thold_0 => pc_iu_ary_slp_nsl_thold_0, + pc_iu_bolt_sl_thold_0 => pc_iu_bolt_sl_thold_0, + pc_iu_sg_0 => pc_iu_sg_0, + pc_iu_sg_1 => pc_iu_sg_1, + forcee => forcee, + funcslp_force => funcslp_force, + abst_force => abst_force, + d_mode => d_mode, + delay_lclkr => delay_lclkr(0), + mpw1_b => mpw1_b(0), + mpw2_b => mpw2_b, + clkoff_b => clkoff_b, + act_dis => act_dis, + g8t_clkoff_b => g8t_clkoff_b, + g8t_d_mode => g8t_d_mode, + g8t_delay_lclkr => g8t_delay_lclkr, + g8t_mpw1_b => g8t_mpw1_b, + g8t_mpw2_b => g8t_mpw2_b, + g6t_clkoff_b => g6t_clkoff_b, + g6t_act_dis => g6t_act_dis, + g6t_d_mode => g6t_d_mode, + g6t_delay_lclkr => g6t_delay_lclkr, + g6t_mpw1_b => g6t_mpw1_b, + g6t_mpw2_b => g6t_mpw2_b, + tc_ac_ccflush_dc => tc_ac_ccflush_dc, + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b, + an_ac_scan_diag_dc => an_ac_scan_diag_dc, + func_scan_in => dir_func_scan_in, + time_scan_in => tsiv(1), + repr_scan_in => repr_scan_in, + abst_scan_in => abst_scan_in, + func_scan_out => dir_func_scan_out, + time_scan_out => tsov(1), + repr_scan_out => repr_scan_out, + abst_scan_out => abst_scan_out, + spr_ic_cls => spr_ic_cls, + spr_ic_clockgate_dis => spr_ic_clockgate_dis(0), + spr_ic_idir_way => spr_ic_idir_way, + ic_spr_idir_done => ic_spr_idir_done, + ic_spr_idir_lru => ic_spr_idir_lru, + ic_spr_idir_parity => ic_spr_idir_parity, + ic_spr_idir_endian => ic_spr_idir_endian, + ic_spr_idir_valid => ic_spr_idir_valid, + ic_spr_idir_tag => ic_spr_idir_tag, + ic_perf_event_t0 => ic_perf_event_t0(4 to 6), + ic_perf_event_t1 => ic_perf_event_t1(4 to 6), + ic_perf_event_t2 => ic_perf_event_t2(4 to 6), + ic_perf_event_t3 => ic_perf_event_t3(4 to 6), + ic_perf_event => ic_perf_event, + iu_pc_err_icache_parity => iu_pc_err_icache_parity, + iu_pc_err_icachedir_parity => iu_pc_err_icachedir_parity, + iu_pc_err_icachedir_multihit => iu_pc_err_icachedir_multihit, + pc_iu_inj_icache_parity => pc_iu_inj_icache_parity, + pc_iu_inj_icachedir_parity => pc_iu_inj_icachedir_parity, + pc_iu_inj_icachedir_multihit => pc_iu_inj_icachedir_multihit, + pc_iu_abist_g8t_wenb => pc_iu_abist_g8t_wenb, + pc_iu_abist_g8t1p_renb_0 => pc_iu_abist_g8t1p_renb_0, + pc_iu_abist_di_0 => pc_iu_abist_di_0, + pc_iu_abist_g8t_bw_1 => pc_iu_abist_g8t_bw_1, + pc_iu_abist_g8t_bw_0 => pc_iu_abist_g8t_bw_0, + pc_iu_abist_waddr_0 => pc_iu_abist_waddr_0, + pc_iu_abist_raddr_0 => pc_iu_abist_raddr_0, + pc_iu_abist_ena_dc => pc_iu_abist_ena_dc, + pc_iu_abist_wl64_comp_ena => pc_iu_abist_wl64_comp_ena, + pc_iu_abist_raw_dc_b => pc_iu_abist_raw_dc_b, + pc_iu_abist_g8t_dcomp => pc_iu_abist_g8t_dcomp, + pc_iu_abist_g6t_bw => pc_iu_abist_g6t_bw, + pc_iu_abist_di_g6t_2r => pc_iu_abist_di_g6t_2r, + pc_iu_abist_wl256_comp_ena => pc_iu_abist_wl256_comp_ena, + pc_iu_abist_dcomp_g6t_2r => pc_iu_abist_dcomp_g6t_2r, + pc_iu_abist_g6t_r_wb => pc_iu_abist_g6t_r_wb, + an_ac_lbist_ary_wrt_thru_dc=> an_ac_lbist_ary_wrt_thru_dc, + pc_iu_bo_enable_2 => pc_iu_bo_enable_2, + pc_iu_bo_reset => pc_iu_bo_reset, + pc_iu_bo_unload => pc_iu_bo_unload, + pc_iu_bo_repair => pc_iu_bo_repair, + pc_iu_bo_shdata => pc_iu_bo_shdata, + pc_iu_bo_select => pc_iu_bo_select, + iu_pc_bo_fail => iu_pc_bo_fail, + iu_pc_bo_diagout => iu_pc_bo_diagout, + xu_iu_ici => xu_iu_ici, + iu_mm_ierat_epn => iu_mm_ierat_epn, + iu_ierat_iu1_back_inv => iu_ierat_iu1_back_inv, + ierat_iu_iu2_rpn => ierat_iu_iu2_rpn, + ierat_iu_iu2_wimge => ierat_iu_iu2_wimge, + ierat_iu_iu2_u => ierat_iu_iu2_u, + ierat_iu_iu2_error => ierat_iu_iu2_error, + ierat_iu_iu2_miss => ierat_iu_iu2_miss, + ierat_iu_iu2_multihit => ierat_iu_iu2_multihit, + ierat_iu_iu2_isi => ierat_iu_iu2_isi, + ics_icd_dir_rd_act => ics_icd_dir_rd_act, + ics_icd_data_rd_act => ics_icd_data_rd_act, + ics_icd_iu0_valid => ics_icd_iu0_valid, + ics_icd_iu0_tid => ics_icd_iu0_tid, + ics_icd_iu0_ifar => ics_icd_iu0_ifar, + ics_icd_iu0_inval => ics_icd_iu0_inval, + ics_icd_iu0_2ucode => ics_icd_iu0_2ucode, + ics_icd_iu0_2ucode_type => ics_icd_iu0_2ucode_type, + ics_icd_iu0_spr_idir_read => ics_icd_iu0_spr_idir_read, + icd_ics_iu1_valid => icd_ics_iu1_valid, + icd_ics_iu1_tid => icd_ics_iu1_tid, + icd_ics_iu1_ifar => icd_ics_iu1_ifar, + icd_ics_iu1_2ucode => icd_ics_iu1_2ucode, + icd_ics_iu1_2ucode_type => icd_ics_iu1_2ucode_type, + ics_icd_all_flush_prev => ics_icd_all_flush_prev, + ics_icd_iu1_flush_tid => ics_icd_iu1_flush_tid, + ics_icd_iu2_flush_tid => ics_icd_iu2_flush_tid, + icd_ics_iu2_miss_flush_prev=> icd_ics_iu2_miss_flush_prev, + icd_ics_iu2_ifar_eff => icd_ics_iu2_ifar_eff, + icd_ics_iu2_2ucode => icd_ics_iu2_2ucode, + icd_ics_iu2_2ucode_type => icd_ics_iu2_2ucode_type, + icd_ics_iu3_parity_flush => icd_ics_iu3_parity_flush, + icd_ics_iu3_ifar => icd_ics_iu3_ifar, + icd_ics_iu3_2ucode => icd_ics_iu3_2ucode, + icd_ics_iu3_2ucode_type => icd_ics_iu3_2ucode_type, + icm_icd_lru_addr => icm_icd_lru_addr, + icm_icd_dir_inval => icm_icd_dir_inval, + icm_icd_dir_val => icm_icd_dir_val, + icm_icd_data_write => icm_icd_data_write, + icm_icd_reload_addr => icm_icd_reload_addr, + icm_icd_reload_data => icm_icd_reload_data, + icm_icd_reload_way => icm_icd_reload_way, + icm_icd_load_tid => icm_icd_load_tid, + icm_icd_load_addr => icm_icd_load_addr, + icm_icd_load_2ucode => icm_icd_load_2ucode, + icm_icd_load_2ucode_type => icm_icd_load_2ucode_type, + icm_icd_dir_write => icm_icd_dir_write, + icm_icd_dir_write_addr => icm_icd_dir_write_addr, + icm_icd_dir_write_endian => icm_icd_dir_write_endian, + icm_icd_dir_write_way => icm_icd_dir_write_way, + icm_icd_lru_write => icm_icd_lru_write, + icm_icd_lru_write_addr => icm_icd_lru_write_addr, + icm_icd_lru_write_way => icm_icd_lru_write_way, + icm_icd_ecc_inval => icm_icd_ecc_inval, + icm_icd_ecc_addr => icm_icd_ecc_addr, + icm_icd_ecc_way => icm_icd_ecc_way, + icm_icd_iu3_ecc_fp_cancel => icm_icd_iu3_ecc_fp_cancel, + icm_icd_iu3_ecc_err => icm_icd_iu3_ecc_err, + icm_icd_any_reld_r2 => icm_icd_any_reld_r2, + icm_icd_any_checkecc => icm_icd_any_checkecc, + icd_icm_miss => icd_icm_miss, + icd_icm_tid => icd_icm_tid, + icd_icm_addr_real => icd_icm_addr_real, + icd_icm_addr_eff => icd_icm_addr_eff, + icd_icm_wimge => icd_icm_wimge, + icd_icm_userdef => icd_icm_userdef, + icd_icm_2ucode => icd_icm_2ucode, + icd_icm_2ucode_type => icd_icm_2ucode_type, + icd_icm_iu3_erat_err => icd_icm_iu3_erat_err, + icd_icm_iu2_inval => icd_icm_iu2_inval, + icd_icm_ici => icd_icm_ici, + icd_icm_any_iu2_valid => icd_icm_any_iu2_valid, + icd_icm_row_lru => icd_icm_row_lru, + icd_icm_row_val => icd_icm_row_val, + ic_bp_iu3_val => int_ic_bp_iu3_val, + ic_bp_iu3_tid => ic_bp_iu3_tid, + ic_bp_iu3_ifar => ic_bp_iu3_ifar, + ic_bp_iu3_2ucode => ic_bp_iu3_2ucode, + ic_bp_iu3_2ucode_type => ic_bp_iu3_2ucode_type, + ic_bp_iu3_error => ic_bp_iu3_error, + ic_bp_iu3_flush => ic_bp_iu3_flush, + ic_bp_iu3_0_instr => int_ic_bp_iu3_0_instr, + ic_bp_iu3_1_instr => int_ic_bp_iu3_1_instr, + ic_bp_iu3_2_instr => int_ic_bp_iu3_2_instr, + ic_bp_iu3_3_instr => int_ic_bp_iu3_3_instr, + event_bus_enable => event_bus_enable_q, + trace_bus_enable => trace_bus_enable_q, + dir_dbg_data0 => dir_dbg_data0, + dir_dbg_data1 => dir_dbg_data1, + dir_dbg_data2 => dir_dbg_data2, + dir_dbg_trigger0 => dir_dbg_trigger0, + dir_dbg_trigger1 => dir_dbg_trigger1 +); +ic_bp_iu3_val <= int_ic_bp_iu3_val; +ic_bp_iu3_0_instr <= int_ic_bp_iu3_0_instr; +ic_bp_iu3_1_instr <= int_ic_bp_iu3_1_instr; +ic_bp_iu3_2_instr <= int_ic_bp_iu3_2_instr; +ic_bp_iu3_3_instr <= int_ic_bp_iu3_3_instr; +iuq_ic_miss0 : entity work.iuq_ic_miss +generic map(expand_type => expand_type) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_iu_func_sl_thold_0_b => pc_iu_func_sl_thold_0_b, + pc_iu_sg_0 => pc_iu_sg_0, + forcee => forcee, + d_mode => d_mode, + delay_lclkr => delay_lclkr(0), + mpw1_b => mpw1_b(0), + mpw2_b => mpw2_b, + scan_in => miss_func_scan_in, + scan_out => miss_func_scan_out, + xu_iu_flush => xu_iu_flush, + bp_ic_iu5_redirect_tid => bp_ic_iu5_redirect_tid, + ics_icm_iu0_ifar0 => ics_icm_iu0_ifar0, + ics_icm_iu0_ifar1 => ics_icm_iu0_ifar1, + ics_icm_iu0_ifar2 => ics_icm_iu0_ifar2, + ics_icm_iu0_ifar3 => ics_icm_iu0_ifar3, + ics_icm_iu0_inval => ics_icm_iu0_inval, + ics_icm_iu0_inval_addr => ics_icm_iu0_inval_addr, + ics_icm_iu2_flush_tid => ics_icm_iu2_flush_tid, + ics_icm_iu3_flush_tid => ics_icm_iu3_flush_tid, + icm_ics_hold_thread => icm_ics_hold_thread, + icm_ics_hold_thread_dbg => icm_ics_hold_thread_dbg, + icm_ics_hold_iu0 => icm_ics_hold_iu0, + icm_ics_ecc_block_iu0 => icm_ics_ecc_block_iu0, + icm_ics_load_tid => icm_ics_load_tid, + icm_ics_iu1_ecc_flush => icm_ics_iu1_ecc_flush, + icm_ics_iu2_miss_match_prev => icm_ics_iu2_miss_match_prev, + icm_ics_iu0_preload_val => icm_ics_iu0_preload_val, + icm_ics_iu0_preload_tid => icm_ics_iu0_preload_tid, + icm_ics_iu0_preload_ifar => icm_ics_iu0_preload_ifar, + icm_icd_lru_addr => icm_icd_lru_addr, + icm_icd_dir_inval => icm_icd_dir_inval, + icm_icd_dir_val => icm_icd_dir_val, + icm_icd_data_write => icm_icd_data_write, + icm_icd_reload_addr => icm_icd_reload_addr, + icm_icd_reload_data => icm_icd_reload_data, + icm_icd_reload_way => icm_icd_reload_way, + icm_icd_load_tid => icm_icd_load_tid, + icm_icd_load_addr => icm_icd_load_addr, + icm_icd_load_2ucode => icm_icd_load_2ucode, + icm_icd_load_2ucode_type => icm_icd_load_2ucode_type, + icm_icd_dir_write => icm_icd_dir_write, + icm_icd_dir_write_addr => icm_icd_dir_write_addr, + icm_icd_dir_write_endian => icm_icd_dir_write_endian, + icm_icd_dir_write_way => icm_icd_dir_write_way, + icm_icd_lru_write => icm_icd_lru_write, + icm_icd_lru_write_addr => icm_icd_lru_write_addr, + icm_icd_lru_write_way => icm_icd_lru_write_way, + icm_icd_ecc_inval => icm_icd_ecc_inval, + icm_icd_ecc_addr => icm_icd_ecc_addr, + icm_icd_ecc_way => icm_icd_ecc_way, + icm_icd_iu3_ecc_fp_cancel => icm_icd_iu3_ecc_fp_cancel, + icm_icd_iu3_ecc_err => icm_icd_iu3_ecc_err, + icm_icd_any_reld_r2 => icm_icd_any_reld_r2, + icm_icd_any_checkecc => icm_icd_any_checkecc, + icd_icm_miss => icd_icm_miss, + icd_icm_tid => icd_icm_tid, + icd_icm_addr_real => icd_icm_addr_real, + icd_icm_addr_eff => icd_icm_addr_eff, + icd_icm_wimge => icd_icm_wimge, + icd_icm_userdef => icd_icm_userdef, + icd_icm_2ucode => icd_icm_2ucode, + icd_icm_2ucode_type => icd_icm_2ucode_type, + icd_icm_iu3_erat_err => icd_icm_iu3_erat_err, + icd_icm_iu2_inval => icd_icm_iu2_inval, + icd_icm_ici => icd_icm_ici, + icd_icm_any_iu2_valid => icd_icm_any_iu2_valid, + icd_icm_row_lru => icd_icm_row_lru, + icd_icm_row_val => icd_icm_row_val, + ic_fdep_load_quiesce => ic_fdep_load_quiesce, + iu_mm_lmq_empty => iu_mm_lmq_empty, + ic_perf_event_t0 => ic_perf_event_t0(0 to 1), + ic_perf_event_t1 => ic_perf_event_t1(0 to 1), + ic_perf_event_t2 => ic_perf_event_t2(0 to 1), + ic_perf_event_t3 => ic_perf_event_t3(0 to 1), + an_ac_reld_data_vld => an_ac_reld_data_vld, + an_ac_reld_core_tag => an_ac_reld_core_tag, + an_ac_reld_qw => an_ac_reld_qw, + an_ac_reld_data => an_ac_reld_data, + an_ac_reld_ecc_err => an_ac_reld_ecc_err, + an_ac_reld_ecc_err_ue => an_ac_reld_ecc_err_ue, + spr_ic_bp_config => spr_ic_bp_config, + spr_ic_cls => spr_ic_cls, + spr_ic_clockgate_dis => spr_ic_clockgate_dis(0), + iu_xu_request => iu_xu_request, + iu_xu_thread => iu_xu_thread, + iu_xu_ra => iu_xu_ra, + iu_xu_wimge => iu_xu_wimge, + iu_xu_userdef => iu_xu_userdef, + event_bus_enable => event_bus_enable_q, + trace_bus_enable => trace_bus_enable_q, + miss_dbg_data0 => miss_dbg_data0, + miss_dbg_data1 => miss_dbg_data1, + miss_dbg_data2 => miss_dbg_data2, + miss_dbg_trigger => miss_dbg_trigger +); +iu3_dbg_data(0 to 21) <= int_ic_bp_iu3_val(0) & int_ic_bp_iu3_0_instr(0 to 5) & int_ic_bp_iu3_0_instr(21 to 31) & int_ic_bp_iu3_0_instr(32 to 35); +iu3_dbg_data(22 to 43) <= int_ic_bp_iu3_val(1) & int_ic_bp_iu3_1_instr(0 to 5) & int_ic_bp_iu3_1_instr(21 to 31) & int_ic_bp_iu3_1_instr(32 to 35); +iu3_dbg_data(44 to 65) <= int_ic_bp_iu3_val(2) & int_ic_bp_iu3_2_instr(0 to 5) & int_ic_bp_iu3_2_instr(21 to 31) & int_ic_bp_iu3_2_instr(32 to 35); +iu3_dbg_data(66 to 87) <= int_ic_bp_iu3_val(3) & int_ic_bp_iu3_3_instr(0 to 5) & int_ic_bp_iu3_3_instr(21 to 31) & int_ic_bp_iu3_3_instr(32 to 35); +dbg_group0 <= sel_dbg_data; +dbg_group1 <= dir_dbg_data0; +dbg_group2 <= dir_dbg_data1; +dbg_group3 <= dir_dbg_data2 & miss_dbg_data2; +dbg_group4 <= miss_dbg_data0; +dbg_group5 <= miss_dbg_data1; +dbg_group6 <= iu3_dbg_data; +dbg_group7 <= uc_dbg_data; +dbg_group8 <= ierat_iu_debug_group0; +dbg_group9 <= ierat_iu_debug_group1; +dbg_group10 <= ierat_iu_debug_group2; +dbg_group11 <= ierat_iu_debug_group3; +dbg_group12 <= (others => '0'); +dbg_group13 <= (others => '0'); +dbg_group14 <= (others => '0'); +dbg_group15 <= (others => '0'); +trg_group0 <= sel_dbg_data(65 to 66) & + dir_dbg_trigger0 & + miss_dbg_trigger(10) & miss_dbg_trigger(7); +trg_group1 <= dir_dbg_trigger1; +trg_group2 <= miss_dbg_trigger; +trg_group3 <= (others => '0'); +dbg_mux0: entity clib.c_debug_mux16 + port map( + vd => vdd, + gd => gnd, + + select_bits => debug_mux_ctrls_q, + trace_data_in => debug_data_in, + trigger_data_in => trace_triggers_in, + + dbg_group0 => dbg_group0, + dbg_group1 => dbg_group1, + dbg_group2 => dbg_group2, + dbg_group3 => dbg_group3, + dbg_group4 => dbg_group4, + dbg_group5 => dbg_group5, + dbg_group6 => dbg_group6, + dbg_group7 => dbg_group7, + dbg_group8 => dbg_group8, + dbg_group9 => dbg_group9, + dbg_group10 => dbg_group10, + dbg_group11 => dbg_group11, + dbg_group12 => dbg_group12, + dbg_group13 => dbg_group13, + dbg_group14 => dbg_group14, + dbg_group15 => dbg_group15, + + trg_group0 => trg_group0, + trg_group1 => trg_group1, + trg_group2 => trg_group2, + trg_group3 => trg_group3, + + trace_data_out => trace_data_out_d, + trigger_data_out=> trigger_data_out_d +); +trace_triggers_out <= trigger_data_out_q; +debug_data_out <= trace_data_out_q; +event_bus_enable_d <= pc_iu_event_bus_enable; +trace_bus_enable_d <= pc_iu_trace_bus_enable; +debug_mux_ctrls_d <= pc_iu_debug_mux_ctrls; +event_bus_enable_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr(0), + mpw1_b => mpw1_b(0), + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(event_bus_enable_offset), + scout => sov(event_bus_enable_offset), + din => event_bus_enable_d, + dout => event_bus_enable_q); +trace_enable_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr(0), + mpw1_b => mpw1_b(0), + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(trace_bus_enable_offset), + scout => sov(trace_bus_enable_offset), + din => trace_bus_enable_d, + dout => trace_bus_enable_q); +debug_mux_ctrls_reg: tri_rlmreg_p + generic map (width => debug_mux_ctrls_q'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => trace_bus_enable_q, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr(0), + mpw1_b => mpw1_b(0), + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(debug_mux_ctrls_offset to debug_mux_ctrls_offset + debug_mux_ctrls_q'length-1), + scout => sov(debug_mux_ctrls_offset to debug_mux_ctrls_offset + debug_mux_ctrls_q'length-1), + din => debug_mux_ctrls_d, + dout => debug_mux_ctrls_q); +dbg_trigger_data_reg: tri_rlmreg_p + generic map (width => trigger_data_out_q'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => trace_bus_enable_q, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr(0), + mpw1_b => mpw1_b(0), + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(trigger_data_out_offset to trigger_data_out_offset + trigger_data_out_q'length-1), + scout => sov(trigger_data_out_offset to trigger_data_out_offset + trigger_data_out_q'length-1), + din => trigger_data_out_d, + dout => trigger_data_out_q); +dbg_trace_data_reg: tri_rlmreg_p + generic map (width => trace_data_out_q'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => trace_bus_enable_q, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr(0), + mpw1_b => mpw1_b(0), + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(trace_data_out_offset to trace_data_out_offset + trace_data_out_q'length-1), + scout => sov(trace_data_out_offset to trace_data_out_offset + trace_data_out_q'length-1), + din => trace_data_out_d, + dout => trace_data_out_q); +perv_3to2_reg: tri_plat + generic map (width => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_iu_bo_enable_3, + q(0) => pc_iu_bo_enable_2); +perv_2to1_reg: tri_plat + generic map (width => 11, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_iu_func_sl_thold_2, + din(1) => pc_iu_func_slp_sl_thold_2, + din(2) => pc_iu_time_sl_thold_2, + din(3) => pc_iu_repr_sl_thold_2, + din(4) => pc_iu_abst_sl_thold_2, + din(5) => pc_iu_abst_slp_sl_thold_2, + din(6) => pc_iu_ary_nsl_thold_2, + din(7) => pc_iu_ary_slp_nsl_thold_2, + din(8) => pc_iu_regf_slp_sl_thold_2, + din(9) => pc_iu_bolt_sl_thold_2, + din(10) => pc_iu_sg_2, + q(0) => pc_iu_func_sl_thold_1, + q(1) => pc_iu_func_slp_sl_thold_1, + q(2) => pc_iu_time_sl_thold_1, + q(3) => pc_iu_repr_sl_thold_1, + q(4) => pc_iu_abst_sl_thold_1, + q(5) => pc_iu_abst_slp_sl_thold_1, + q(6) => pc_iu_ary_nsl_thold_1, + q(7) => pc_iu_ary_slp_nsl_thold_1, + q(8) => pc_iu_regf_slp_sl_thold_1, + q(9) => pc_iu_bolt_sl_thold_1, + q(10) => pc_iu_sg_1); +perv_1to0_reg: tri_plat + generic map (width => 11, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_iu_func_sl_thold_1, + din(1) => pc_iu_func_slp_sl_thold_1, + din(2) => pc_iu_time_sl_thold_1, + din(3) => pc_iu_repr_sl_thold_1, + din(4) => pc_iu_abst_sl_thold_1, + din(5) => pc_iu_abst_slp_sl_thold_1, + din(6) => pc_iu_ary_nsl_thold_1, + din(7) => pc_iu_ary_slp_nsl_thold_1, + din(8) => pc_iu_regf_slp_sl_thold_1, + din(9) => pc_iu_bolt_sl_thold_1, + din(10) => pc_iu_sg_1, + q(0) => pc_iu_func_sl_thold_0, + q(1) => pc_iu_func_slp_sl_thold_0, + q(2) => pc_iu_time_sl_thold_0, + q(3) => pc_iu_repr_sl_thold_0, + q(4) => pc_iu_abst_sl_thold_0, + q(5) => pc_iu_abst_slp_sl_thold_0, + q(6) => pc_iu_ary_nsl_thold_0, + q(7) => pc_iu_ary_slp_nsl_thold_0, + q(8) => pc_iu_regf_slp_sl_thold_0, + q(9) => pc_iu_bolt_sl_thold_0, + q(10) => pc_iu_sg_0); +perv_lcbor: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_b, + thold => pc_iu_func_sl_thold_0, + sg => pc_iu_sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => pc_iu_func_sl_thold_0_b); +func_slp_lcbor: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_b, + thold => pc_iu_func_slp_sl_thold_0, + sg => pc_iu_sg_0, + act_dis => act_dis, + forcee => funcslp_force, + thold_b => pc_iu_func_slp_sl_thold_0_b); +abst_lcbor: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_b, + thold => pc_iu_abst_sl_thold_0, + sg => pc_iu_sg_0, + act_dis => act_dis, + forcee => abst_force, + thold_b => pc_iu_abst_sl_thold_0_b); +ierat_func_scan_in(0) <= func_scan_in(0); +func_scan_out(0) <= ierat_func_scan_out(0) and an_ac_scan_dis_dc_b; +siv(0 to scan_right) <= sov(1 to scan_right) & func_scan_in(1); +func_scan_in_cam <= sov(0); +sel_func_scan_in <= func_scan_out_cam; +func_scan_out(1) <= sel_func_scan_out and an_ac_scan_dis_dc_b; +dir_func_scan_in(1) <= func_scan_in(2); +func_scan_out(2) <= dir_func_scan_out(1) and an_ac_scan_dis_dc_b; +miss_func_scan_in <= func_scan_in(3); +ierat_func_scan_in(1) <= miss_func_scan_out; +func_scan_out(3) <= ierat_func_scan_out(1) and an_ac_scan_dis_dc_b; +dir_func_scan_in(0) <= func_scan_in(4); +func_scan_out(4) <= dir_func_scan_out(0) and an_ac_scan_dis_dc_b; +ac_ccfg_scan_out <= ac_ccfg_scan_out_int and an_ac_scan_dis_dc_b; +tsiv <= time_scan_in & tsov(0); +time_scan_out <= tsov(1) and an_ac_scan_dis_dc_b; +regf_slat_slp_sl_thold_0_b <= not pc_iu_regf_slp_sl_thold_0; +regf_scan_latch: entity tri.tri_regs + generic map (width => 5, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + forcee => pc_iu_sg_0, + thold_b => regf_slat_slp_sl_thold_0_b, + delay_lclkr => delay_lclkr(0), + scin => regf_scan_out_cam, + scout => regf_scan_out, + dout => open ); +end iuq_ic; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_ic_dir.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_ic_dir.vhdl new file mode 100644 index 0000000..f3645b1 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_ic_dir.vhdl @@ -0,0 +1,6852 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee,ibm,support,tri,work; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ibm.std_ulogic_unsigned.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use support.power_logic_pkg.all; +use tri.tri_latches_pkg.all; +use work.iuq_pkg.all; + +entity iuq_ic_dir is +generic(expand_type : integer := 2); +port( + vcs : inout power_logic; + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + pc_iu_func_sl_thold_0_b : in std_ulogic; + pc_iu_func_slp_sl_thold_0_b: in std_ulogic; + pc_iu_time_sl_thold_0 : in std_ulogic; + pc_iu_repr_sl_thold_0 : in std_ulogic; + pc_iu_abst_sl_thold_0 : in std_ulogic; + pc_iu_abst_sl_thold_0_b : in std_ulogic; + pc_iu_abst_slp_sl_thold_0 : in std_ulogic; + pc_iu_ary_nsl_thold_0 : in std_ulogic; + pc_iu_ary_slp_nsl_thold_0 : in std_ulogic; + pc_iu_bolt_sl_thold_0 : in std_ulogic; + pc_iu_sg_0 : in std_ulogic; + pc_iu_sg_1 : in std_ulogic; + forcee : in std_ulogic; + funcslp_force : in std_ulogic; + abst_force : in std_ulogic; + + d_mode : in std_ulogic; + delay_lclkr : in std_ulogic; + mpw1_b : in std_ulogic; + mpw2_b : in std_ulogic; + clkoff_b : in std_ulogic; + act_dis : in std_ulogic; + + g8t_clkoff_b : in std_ulogic; + g8t_d_mode : in std_ulogic; + g8t_delay_lclkr : in std_ulogic_vector(0 to 4); + g8t_mpw1_b : in std_ulogic_vector(0 to 4); + g8t_mpw2_b : in std_ulogic; + + g6t_clkoff_b : in std_ulogic; + g6t_act_dis : in std_ulogic; + g6t_d_mode : in std_ulogic; + g6t_delay_lclkr : in std_ulogic_vector(0 to 3); + g6t_mpw1_b : in std_ulogic_vector(0 to 4); + g6t_mpw2_b : in std_ulogic; + + tc_ac_ccflush_dc : in std_ulogic; + an_ac_scan_dis_dc_b : in std_ulogic; + an_ac_scan_diag_dc : in std_ulogic; + func_scan_in : in std_ulogic_vector(0 to 1); + time_scan_in : in std_ulogic; + repr_scan_in : in std_ulogic; + abst_scan_in : in std_ulogic_vector(0 to 2); + func_scan_out : out std_ulogic_vector(0 to 1); + time_scan_out : out std_ulogic; + repr_scan_out : out std_ulogic; + abst_scan_out : out std_ulogic_vector(0 to 2); + + spr_ic_cls : in std_ulogic; + spr_ic_clockgate_dis : in std_ulogic; + + spr_ic_idir_way : in std_ulogic_vector(0 to 1); + ic_spr_idir_done : out std_ulogic; + ic_spr_idir_lru : out std_ulogic_vector(0 to 2); + ic_spr_idir_parity : out std_ulogic_vector(0 to 3); + ic_spr_idir_endian : out std_ulogic; + ic_spr_idir_valid : out std_ulogic; + ic_spr_idir_tag : out std_ulogic_vector(0 to 29); + + ic_perf_event_t0 : out std_ulogic_vector(4 to 6); + ic_perf_event_t1 : out std_ulogic_vector(4 to 6); + ic_perf_event_t2 : out std_ulogic_vector(4 to 6); + ic_perf_event_t3 : out std_ulogic_vector(4 to 6); + ic_perf_event : out std_ulogic_vector(0 to 1); + + iu_pc_err_icache_parity : out std_ulogic; + iu_pc_err_icachedir_parity : out std_ulogic; + iu_pc_err_icachedir_multihit : out std_ulogic; + + pc_iu_inj_icache_parity : in std_ulogic; + pc_iu_inj_icachedir_parity : in std_ulogic; + pc_iu_inj_icachedir_multihit : in std_ulogic; + + pc_iu_abist_g8t_wenb : in std_ulogic; + pc_iu_abist_g8t1p_renb_0 : in std_ulogic; + pc_iu_abist_di_0 : in std_ulogic_vector(0 to 3); + pc_iu_abist_g8t_bw_1 : in std_ulogic; + pc_iu_abist_g8t_bw_0 : in std_ulogic; + pc_iu_abist_waddr_0 : in std_ulogic_vector(4 to 9); + pc_iu_abist_raddr_0 : in std_ulogic_vector(2 to 9); + pc_iu_abist_ena_dc : in std_ulogic; + pc_iu_abist_wl64_comp_ena : in std_ulogic; + pc_iu_abist_raw_dc_b : in std_ulogic; + pc_iu_abist_g8t_dcomp : in std_ulogic_vector(0 to 3); + pc_iu_abist_g6t_bw : in std_ulogic_vector(0 to 1); + pc_iu_abist_di_g6t_2r : in std_ulogic_vector(0 to 3); + pc_iu_abist_wl256_comp_ena : in std_ulogic; + pc_iu_abist_dcomp_g6t_2r : in std_ulogic_vector(0 to 3); + pc_iu_abist_g6t_r_wb : in std_ulogic; + an_ac_lbist_ary_wrt_thru_dc: in std_ulogic; + + pc_iu_bo_enable_2 : in std_ulogic; + pc_iu_bo_reset : in std_ulogic; + pc_iu_bo_unload : in std_ulogic; + pc_iu_bo_repair : in std_ulogic; + pc_iu_bo_shdata : in std_ulogic; + pc_iu_bo_select : in std_ulogic_vector(0 to 3); + iu_pc_bo_fail : out std_ulogic_vector(0 to 3); + iu_pc_bo_diagout : out std_ulogic_vector(0 to 3); + + xu_iu_ici : in std_ulogic; + + iu_mm_ierat_epn : out std_ulogic_vector(0 to 51); + + iu_ierat_iu1_back_inv : out std_ulogic; + + ierat_iu_iu2_rpn : in std_ulogic_vector(REAL_IFAR'left to 51); + ierat_iu_iu2_wimge : in std_ulogic_vector(0 to 4); + ierat_iu_iu2_u : in std_ulogic_vector(0 to 3); + ierat_iu_iu2_error : in std_ulogic_vector(0 to 2); + ierat_iu_iu2_miss : in std_ulogic; + ierat_iu_iu2_multihit : in std_ulogic; + ierat_iu_iu2_isi : in std_ulogic; + + ics_icd_dir_rd_act : in std_ulogic; + ics_icd_data_rd_act : in std_ulogic; + ics_icd_iu0_valid : in std_ulogic; + ics_icd_iu0_tid : in std_ulogic_vector(0 to 3); + ics_icd_iu0_ifar : in EFF_IFAR; + ics_icd_iu0_inval : in std_ulogic; + ics_icd_iu0_2ucode : in std_ulogic; + ics_icd_iu0_2ucode_type : in std_ulogic; + ics_icd_iu0_spr_idir_read : in std_ulogic; + + icd_ics_iu1_valid : out std_ulogic; + icd_ics_iu1_tid : out std_ulogic_vector(0 to 3); + icd_ics_iu1_ifar : out EFF_IFAR; + icd_ics_iu1_2ucode : out std_ulogic; + icd_ics_iu1_2ucode_type : out std_ulogic; + + ics_icd_all_flush_prev : in std_ulogic_vector(0 to 3); + ics_icd_iu1_flush_tid : in std_ulogic_vector(0 to 3); + ics_icd_iu2_flush_tid : in std_ulogic_vector(0 to 3); + icd_ics_iu2_miss_flush_prev: out std_ulogic_vector(0 to 3); + icd_ics_iu2_ifar_eff : out EFF_IFAR; + icd_ics_iu2_2ucode : out std_ulogic; + icd_ics_iu2_2ucode_type : out std_ulogic; + icd_ics_iu3_parity_flush : out std_ulogic_vector(0 to 3); + icd_ics_iu3_ifar : out EFF_IFAR; + icd_ics_iu3_2ucode : out std_ulogic; + icd_ics_iu3_2ucode_type : out std_ulogic; + + icm_icd_lru_addr : in std_ulogic_vector(52 to 57); + icm_icd_dir_inval : in std_ulogic; + icm_icd_dir_val : in std_ulogic; + icm_icd_data_write : in std_ulogic; + icm_icd_reload_addr : in std_ulogic_vector(52 to 59); + icm_icd_reload_data : in std_ulogic_vector(0 to 161); + icm_icd_reload_way : in std_ulogic_vector(0 to 3); + icm_icd_load_tid : in std_ulogic_vector(0 to 3); + icm_icd_load_addr : in EFF_IFAR; + icm_icd_load_2ucode : in std_ulogic; + icm_icd_load_2ucode_type : in std_ulogic; + icm_icd_dir_write : in std_ulogic; + icm_icd_dir_write_addr : in std_ulogic_vector(REAL_IFAR'left to 57); + icm_icd_dir_write_endian : in std_ulogic; + icm_icd_dir_write_way : in std_ulogic_vector(0 to 3); + icm_icd_lru_write : in std_ulogic; + icm_icd_lru_write_addr : in std_ulogic_vector(52 to 57); + icm_icd_lru_write_way : in std_ulogic_vector(0 to 3); + icm_icd_ecc_inval : in std_ulogic; + icm_icd_ecc_addr : in std_ulogic_vector(52 to 57); + icm_icd_ecc_way : in std_ulogic_vector(0 to 3); + icm_icd_iu3_ecc_fp_cancel : in std_ulogic; + icm_icd_iu3_ecc_err : in std_ulogic; + icm_icd_any_reld_r2 : in std_ulogic; + icm_icd_any_checkecc : in std_ulogic; + + icd_icm_miss : out std_ulogic; + icd_icm_tid : out std_ulogic_vector(0 to 3); + icd_icm_addr_real : out REAL_IFAR; + icd_icm_addr_eff : out std_ulogic_vector(EFF_IFAR'left to 51); + icd_icm_wimge : out std_ulogic_vector(0 to 4); + icd_icm_userdef : out std_ulogic_vector(0 to 3); + icd_icm_2ucode : out std_ulogic; + icd_icm_2ucode_type : out std_ulogic; + icd_icm_iu3_erat_err : out std_ulogic; + icd_icm_iu2_inval : out std_ulogic; + icd_icm_ici : out std_ulogic; + icd_icm_any_iu2_valid : out std_ulogic; + + icd_icm_row_lru : out std_ulogic_vector(0 to 2); + icd_icm_row_val : out std_ulogic_vector(0 to 3); + + ic_bp_iu3_val : out std_ulogic_vector(0 to 3); + ic_bp_iu3_tid : out std_ulogic_vector(0 to 3); + ic_bp_iu3_ifar : out EFF_IFAR; + ic_bp_iu3_2ucode : out std_ulogic; + ic_bp_iu3_2ucode_type : out std_ulogic; + ic_bp_iu3_error : out std_ulogic_vector(0 to 2); + ic_bp_iu3_flush : out std_ulogic; + + ic_bp_iu3_0_instr : out std_ulogic_vector(0 to 35); + ic_bp_iu3_1_instr : out std_ulogic_vector(0 to 35); + ic_bp_iu3_2_instr : out std_ulogic_vector(0 to 35); + ic_bp_iu3_3_instr : out std_ulogic_vector(0 to 35); + + event_bus_enable : in std_ulogic; + + trace_bus_enable : in std_ulogic; + dir_dbg_data0 : out std_ulogic_vector(0 to 87); + dir_dbg_data1 : out std_ulogic_vector(0 to 87); + dir_dbg_data2 : out std_ulogic_vector(0 to 43); + dir_dbg_trigger0 : out std_ulogic_vector(0 to 7); + dir_dbg_trigger1 : out std_ulogic_vector(0 to 11) +); +-- synopsys translate_off +-- synopsys translate_on +end iuq_ic_dir; +ARCHITECTURE IUQ_IC_DIR + OF IUQ_IC_DIR + IS +constant ways : natural := 4; +constant dir_ext_bits : natural := 8 - ((52-REAL_IFAR'left+1) mod 8); +constant dir_parity_width : natural := (52-REAL_IFAR'left+1+dir_ext_bits)/8; +constant dir_array_way_width : natural := 36; +constant dir_way_width : natural := 52-REAL_IFAR'left+1+dir_parity_width; +constant dbg_dir_write_offset : natural := 0; +constant dbg_dir_rd_act_offset : natural := dbg_dir_write_offset + 1; +constant dbg_iu2_lru_rd_update_offset : natural := dbg_dir_rd_act_offset + 1; +constant dbg_iu2_rd_way_tag_hit_offset : natural := dbg_iu2_lru_rd_update_offset + 1; +constant dbg_iu2_rd_way_hit_offset : natural := dbg_iu2_rd_way_tag_hit_offset + 4; +constant dbg_load_iu2_offset : natural := dbg_iu2_rd_way_hit_offset + 4; +constant iu1_valid_offset : natural := dbg_load_iu2_offset + 1; +constant spare_a_offset : natural := iu1_valid_offset + 1; +constant iu1_tid_offset : natural := spare_a_offset + 8; +constant iu1_ifar_offset : natural := iu1_tid_offset + 4; +constant iu1_inval_offset : natural := iu1_ifar_offset + EFF_IFAR'length; +constant iu1_2ucode_offset : natural := iu1_inval_offset + 1; +constant iu1_2ucode_type_offset : natural := iu1_2ucode_offset + 1; +constant iu2_valid_offset : natural := iu1_2ucode_type_offset + 1; +constant iu2_tid_offset : natural := iu2_valid_offset + 1; +constant iu2_ifar_eff_offset : natural := iu2_tid_offset + 4; +constant iu2_2ucode_offset : natural := iu2_ifar_eff_offset + EFF_IFAR'length; +constant iu2_2ucode_type_offset : natural := iu2_2ucode_offset + 1; +constant iu2_inval_offset : natural := iu2_2ucode_type_offset + 1; +constant iu2_dir_rd_val_offset : natural := iu2_inval_offset + 1; +constant iu3_instr_valid_offset : natural := iu2_dir_rd_val_offset + 4; +constant iu3_tid_offset : natural := iu3_instr_valid_offset + 4; +constant iu3_ifar_offset : natural := iu3_tid_offset + 4; +constant iu3_ifar_dec_offset : natural := iu3_ifar_offset + EFF_IFAR'length; +constant iu3_2ucode_offset : natural := iu3_ifar_dec_offset + 4; +constant iu3_2ucode_type_offset : natural := iu3_2ucode_offset + 1; +constant iu3_erat_err_offset : natural := iu3_2ucode_type_offset + 1; +constant iu3_instr_offset : natural := iu3_erat_err_offset + 3; +constant iu3_dir_parity_err_way_offset : natural := iu3_instr_offset + 1; +constant iu3_data_parity_err_way_offset : natural := iu3_dir_parity_err_way_offset + 4; +constant iu3_parity_needs_flush_offset : natural := iu3_data_parity_err_way_offset + 4; +constant iu3_rd_parity_err_offset : natural := iu3_parity_needs_flush_offset + 4; +constant iu3_rd_miss_offset : natural := iu3_rd_parity_err_offset + 1; +constant err_icache_parity_offset : natural := iu3_rd_miss_offset + 1; +constant err_icachedir_parity_offset : natural := err_icache_parity_offset + 1; +constant iu3_multihit_err_way_offset : natural := err_icachedir_parity_offset + 1; +constant iu3_multihit_flush_offset : natural := iu3_multihit_err_way_offset + 4; +constant iu3_parity_tag_offset : natural := iu3_multihit_flush_offset + 1; +constant spare_slp_offset : natural := iu3_parity_tag_offset + 6; +constant perf_instr_count_t0_offset : natural := spare_slp_offset + 16; +constant perf_instr_count_t1_offset : natural := perf_instr_count_t0_offset + 2; +constant perf_instr_count_t2_offset : natural := perf_instr_count_t1_offset + 2; +constant perf_instr_count_t3_offset : natural := perf_instr_count_t2_offset + 2; +constant perf_event_t0_offset : natural := perf_instr_count_t3_offset + 2; +constant perf_event_t1_offset : natural := perf_event_t0_offset + 3; +constant perf_event_t2_offset : natural := perf_event_t1_offset + 3; +constant perf_event_t3_offset : natural := perf_event_t2_offset + 3; +constant perf_event_offset : natural := perf_event_t3_offset + 3; +constant spr_ic_cls_offset : natural := perf_event_offset + 2; +constant spr_ic_idir_way_offset : natural := spr_ic_cls_offset + 1; +constant spare_b_offset : natural := spr_ic_idir_way_offset + 2; +constant iu1_spr_idir_read_offset : natural := spare_b_offset + 8; +constant iu2_spr_idir_read_offset : natural := iu1_spr_idir_read_offset + 1; +constant iu2_spr_idir_lru_offset : natural := iu2_spr_idir_read_offset + 1; +constant scan0_right : natural := iu2_spr_idir_lru_offset + 3 - 1; +constant scan1_left : natural := scan0_right + 1; +constant iu2_dir_dataout_offset : natural := scan1_left; +constant iu2_dir_dataout_0_par_offset : natural := iu2_dir_dataout_offset + 1; +constant iu2_dir_dataout_1_par_offset : natural := iu2_dir_dataout_0_par_offset + dir_parity_width; +constant iu2_dir_dataout_2_par_offset : natural := iu2_dir_dataout_1_par_offset + dir_parity_width; +constant iu2_dir_dataout_3_par_offset : natural := iu2_dir_dataout_2_par_offset + dir_parity_width; +constant iu2_data_dataout_offset : natural := iu2_dir_dataout_3_par_offset + dir_parity_width; +constant xu_iu_ici_offset : natural := iu2_data_dataout_offset + 162*ways; +constant dir_row0_val_offset : natural := xu_iu_ici_offset + 1; +constant dir_row1_val_offset : natural := dir_row0_val_offset + 4; +constant dir_row2_val_offset : natural := dir_row1_val_offset + 4; +constant dir_row3_val_offset : natural := dir_row2_val_offset + 4; +constant dir_row4_val_offset : natural := dir_row3_val_offset + 4; +constant dir_row5_val_offset : natural := dir_row4_val_offset + 4; +constant dir_row6_val_offset : natural := dir_row5_val_offset + 4; +constant dir_row7_val_offset : natural := dir_row6_val_offset + 4; +constant dir_row8_val_offset : natural := dir_row7_val_offset + 4; +constant dir_row9_val_offset : natural := dir_row8_val_offset + 4; +constant dir_row10_val_offset : natural := dir_row9_val_offset + 4; +constant dir_row11_val_offset : natural := dir_row10_val_offset + 4; +constant dir_row12_val_offset : natural := dir_row11_val_offset + 4; +constant dir_row13_val_offset : natural := dir_row12_val_offset + 4; +constant dir_row14_val_offset : natural := dir_row13_val_offset + 4; +constant dir_row15_val_offset : natural := dir_row14_val_offset + 4; +constant dir_row16_val_offset : natural := dir_row15_val_offset + 4; +constant dir_row17_val_offset : natural := dir_row16_val_offset + 4; +constant dir_row18_val_offset : natural := dir_row17_val_offset + 4; +constant dir_row19_val_offset : natural := dir_row18_val_offset + 4; +constant dir_row20_val_offset : natural := dir_row19_val_offset + 4; +constant dir_row21_val_offset : natural := dir_row20_val_offset + 4; +constant dir_row22_val_offset : natural := dir_row21_val_offset + 4; +constant dir_row23_val_offset : natural := dir_row22_val_offset + 4; +constant dir_row24_val_offset : natural := dir_row23_val_offset + 4; +constant dir_row25_val_offset : natural := dir_row24_val_offset + 4; +constant dir_row26_val_offset : natural := dir_row25_val_offset + 4; +constant dir_row27_val_offset : natural := dir_row26_val_offset + 4; +constant dir_row28_val_offset : natural := dir_row27_val_offset + 4; +constant dir_row29_val_offset : natural := dir_row28_val_offset + 4; +constant dir_row30_val_offset : natural := dir_row29_val_offset + 4; +constant dir_row31_val_offset : natural := dir_row30_val_offset + 4; +constant dir_row32_val_offset : natural := dir_row31_val_offset + 4; +constant dir_row33_val_offset : natural := dir_row32_val_offset + 4; +constant dir_row34_val_offset : natural := dir_row33_val_offset + 4; +constant dir_row35_val_offset : natural := dir_row34_val_offset + 4; +constant dir_row36_val_offset : natural := dir_row35_val_offset + 4; +constant dir_row37_val_offset : natural := dir_row36_val_offset + 4; +constant dir_row38_val_offset : natural := dir_row37_val_offset + 4; +constant dir_row39_val_offset : natural := dir_row38_val_offset + 4; +constant dir_row40_val_offset : natural := dir_row39_val_offset + 4; +constant dir_row41_val_offset : natural := dir_row40_val_offset + 4; +constant dir_row42_val_offset : natural := dir_row41_val_offset + 4; +constant dir_row43_val_offset : natural := dir_row42_val_offset + 4; +constant dir_row44_val_offset : natural := dir_row43_val_offset + 4; +constant dir_row45_val_offset : natural := dir_row44_val_offset + 4; +constant dir_row46_val_offset : natural := dir_row45_val_offset + 4; +constant dir_row47_val_offset : natural := dir_row46_val_offset + 4; +constant dir_row48_val_offset : natural := dir_row47_val_offset + 4; +constant dir_row49_val_offset : natural := dir_row48_val_offset + 4; +constant dir_row50_val_offset : natural := dir_row49_val_offset + 4; +constant dir_row51_val_offset : natural := dir_row50_val_offset + 4; +constant dir_row52_val_offset : natural := dir_row51_val_offset + 4; +constant dir_row53_val_offset : natural := dir_row52_val_offset + 4; +constant dir_row54_val_offset : natural := dir_row53_val_offset + 4; +constant dir_row55_val_offset : natural := dir_row54_val_offset + 4; +constant dir_row56_val_offset : natural := dir_row55_val_offset + 4; +constant dir_row57_val_offset : natural := dir_row56_val_offset + 4; +constant dir_row58_val_offset : natural := dir_row57_val_offset + 4; +constant dir_row59_val_offset : natural := dir_row58_val_offset + 4; +constant dir_row60_val_offset : natural := dir_row59_val_offset + 4; +constant dir_row61_val_offset : natural := dir_row60_val_offset + 4; +constant dir_row62_val_offset : natural := dir_row61_val_offset + 4; +constant dir_row63_val_offset : natural := dir_row62_val_offset + 4; +constant dir_row0_lru_offset : natural := dir_row63_val_offset + 4; +constant dir_row1_lru_offset : natural := dir_row0_lru_offset + 3; +constant dir_row2_lru_offset : natural := dir_row1_lru_offset + 3; +constant dir_row3_lru_offset : natural := dir_row2_lru_offset + 3; +constant dir_row4_lru_offset : natural := dir_row3_lru_offset + 3; +constant dir_row5_lru_offset : natural := dir_row4_lru_offset + 3; +constant dir_row6_lru_offset : natural := dir_row5_lru_offset + 3; +constant dir_row7_lru_offset : natural := dir_row6_lru_offset + 3; +constant dir_row8_lru_offset : natural := dir_row7_lru_offset + 3; +constant dir_row9_lru_offset : natural := dir_row8_lru_offset + 3; +constant dir_row10_lru_offset : natural := dir_row9_lru_offset + 3; +constant dir_row11_lru_offset : natural := dir_row10_lru_offset + 3; +constant dir_row12_lru_offset : natural := dir_row11_lru_offset + 3; +constant dir_row13_lru_offset : natural := dir_row12_lru_offset + 3; +constant dir_row14_lru_offset : natural := dir_row13_lru_offset + 3; +constant dir_row15_lru_offset : natural := dir_row14_lru_offset + 3; +constant dir_row16_lru_offset : natural := dir_row15_lru_offset + 3; +constant dir_row17_lru_offset : natural := dir_row16_lru_offset + 3; +constant dir_row18_lru_offset : natural := dir_row17_lru_offset + 3; +constant dir_row19_lru_offset : natural := dir_row18_lru_offset + 3; +constant dir_row20_lru_offset : natural := dir_row19_lru_offset + 3; +constant dir_row21_lru_offset : natural := dir_row20_lru_offset + 3; +constant dir_row22_lru_offset : natural := dir_row21_lru_offset + 3; +constant dir_row23_lru_offset : natural := dir_row22_lru_offset + 3; +constant dir_row24_lru_offset : natural := dir_row23_lru_offset + 3; +constant dir_row25_lru_offset : natural := dir_row24_lru_offset + 3; +constant dir_row26_lru_offset : natural := dir_row25_lru_offset + 3; +constant dir_row27_lru_offset : natural := dir_row26_lru_offset + 3; +constant dir_row28_lru_offset : natural := dir_row27_lru_offset + 3; +constant dir_row29_lru_offset : natural := dir_row28_lru_offset + 3; +constant dir_row30_lru_offset : natural := dir_row29_lru_offset + 3; +constant dir_row31_lru_offset : natural := dir_row30_lru_offset + 3; +constant dir_row32_lru_offset : natural := dir_row31_lru_offset + 3; +constant dir_row33_lru_offset : natural := dir_row32_lru_offset + 3; +constant dir_row34_lru_offset : natural := dir_row33_lru_offset + 3; +constant dir_row35_lru_offset : natural := dir_row34_lru_offset + 3; +constant dir_row36_lru_offset : natural := dir_row35_lru_offset + 3; +constant dir_row37_lru_offset : natural := dir_row36_lru_offset + 3; +constant dir_row38_lru_offset : natural := dir_row37_lru_offset + 3; +constant dir_row39_lru_offset : natural := dir_row38_lru_offset + 3; +constant dir_row40_lru_offset : natural := dir_row39_lru_offset + 3; +constant dir_row41_lru_offset : natural := dir_row40_lru_offset + 3; +constant dir_row42_lru_offset : natural := dir_row41_lru_offset + 3; +constant dir_row43_lru_offset : natural := dir_row42_lru_offset + 3; +constant dir_row44_lru_offset : natural := dir_row43_lru_offset + 3; +constant dir_row45_lru_offset : natural := dir_row44_lru_offset + 3; +constant dir_row46_lru_offset : natural := dir_row45_lru_offset + 3; +constant dir_row47_lru_offset : natural := dir_row46_lru_offset + 3; +constant dir_row48_lru_offset : natural := dir_row47_lru_offset + 3; +constant dir_row49_lru_offset : natural := dir_row48_lru_offset + 3; +constant dir_row50_lru_offset : natural := dir_row49_lru_offset + 3; +constant dir_row51_lru_offset : natural := dir_row50_lru_offset + 3; +constant dir_row52_lru_offset : natural := dir_row51_lru_offset + 3; +constant dir_row53_lru_offset : natural := dir_row52_lru_offset + 3; +constant dir_row54_lru_offset : natural := dir_row53_lru_offset + 3; +constant dir_row55_lru_offset : natural := dir_row54_lru_offset + 3; +constant dir_row56_lru_offset : natural := dir_row55_lru_offset + 3; +constant dir_row57_lru_offset : natural := dir_row56_lru_offset + 3; +constant dir_row58_lru_offset : natural := dir_row57_lru_offset + 3; +constant dir_row59_lru_offset : natural := dir_row58_lru_offset + 3; +constant dir_row60_lru_offset : natural := dir_row59_lru_offset + 3; +constant dir_row61_lru_offset : natural := dir_row60_lru_offset + 3; +constant dir_row62_lru_offset : natural := dir_row61_lru_offset + 3; +constant dir_row63_lru_offset : natural := dir_row62_lru_offset + 3; +constant scan_right : natural := dir_row63_lru_offset + 3 - 1; +subtype s2 is std_ulogic_vector(0 to 1); +subtype s3 is std_ulogic_vector(0 to 2); +subtype s6 is std_ulogic_vector(0 to 5); +subtype s11 is std_ulogic_vector(0 to 10); +signal ZEROS : std_ulogic_vector(6 to 35); +signal tidn : std_ulogic; +signal tiup : std_ulogic; +signal iu1_valid_d : std_ulogic; +signal iu1_valid_l2 : std_ulogic; +signal iu1_tid_d : std_ulogic_vector(0 to 3); +signal iu1_tid_l2 : std_ulogic_vector(0 to 3); +signal iu1_ifar_d : EFF_IFAR; +signal iu1_ifar_l2 : EFF_IFAR; +signal iu1_inval_d : std_ulogic; +signal iu1_inval_l2 : std_ulogic; +signal iu1_2ucode_d : std_ulogic; +signal iu1_2ucode_l2 : std_ulogic; +signal iu1_2ucode_type_d : std_ulogic; +signal iu1_2ucode_type_l2 : std_ulogic; +signal iu2_valid_d : std_ulogic; +signal iu2_valid_l2 : std_ulogic; +signal iu2_tid_d : std_ulogic_vector(0 to 3); +signal iu2_tid_l2 : std_ulogic_vector(0 to 3); +signal iu2_ifar_eff_d : EFF_IFAR; +signal iu2_ifar_eff_l2 : EFF_IFAR; +signal iu2_2ucode_d : std_ulogic; +signal iu2_2ucode_l2 : std_ulogic; +signal iu2_2ucode_type_d : std_ulogic; +signal iu2_2ucode_type_l2 : std_ulogic; +signal iu2_inval_d : std_ulogic; +signal iu2_inval_l2 : std_ulogic; +signal iu2_dir_rd_val_d : std_ulogic_vector(0 to 3); +signal iu2_dir_rd_val_l2 : std_ulogic_vector(0 to 3); +signal iu2_dir_dataout_0_d : std_ulogic_vector(22 to 52); +signal iu2_dir_dataout_0_noncmp : std_ulogic_vector(22 to 52); +signal iu2_dir_dataout_1_d : std_ulogic_vector(22 to 52); +signal iu2_dir_dataout_1_noncmp : std_ulogic_vector(22 to 52); +signal iu2_dir_dataout_2_d : std_ulogic_vector(22 to 52); +signal iu2_dir_dataout_2_noncmp : std_ulogic_vector(22 to 52); +signal iu2_dir_dataout_3_d : std_ulogic_vector(22 to 52); +signal iu2_dir_dataout_3_noncmp : std_ulogic_vector(22 to 52); +signal iu2_dir_dataout_0_par_d : std_ulogic_vector(0 to dir_parity_width-1); +signal iu2_dir_dataout_0_par_l2 : std_ulogic_vector(0 to dir_parity_width-1); +signal iu2_dir_dataout_1_par_d : std_ulogic_vector(0 to dir_parity_width-1); +signal iu2_dir_dataout_1_par_l2 : std_ulogic_vector(0 to dir_parity_width-1); +signal iu2_dir_dataout_2_par_d : std_ulogic_vector(0 to dir_parity_width-1); +signal iu2_dir_dataout_2_par_l2 : std_ulogic_vector(0 to dir_parity_width-1); +signal iu2_dir_dataout_3_par_d : std_ulogic_vector(0 to dir_parity_width-1); +signal iu2_dir_dataout_3_par_l2 : std_ulogic_vector(0 to dir_parity_width-1); +signal iu2_data_dataout_d : std_ulogic_vector(0 to 162*ways-1); +signal iu2_data_dataout_l2 : std_ulogic_vector(0 to 162*ways-1); +signal xu_iu_ici_d : std_ulogic; +signal xu_iu_ici_l2 : std_ulogic; +signal dir_row0_val_d : std_ulogic_vector(0 to 3); +signal dir_row0_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row0_lru_d : std_ulogic_vector(0 to 2); +signal dir_row0_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row1_val_d : std_ulogic_vector(0 to 3); +signal dir_row1_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row1_lru_d : std_ulogic_vector(0 to 2); +signal dir_row1_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row2_val_d : std_ulogic_vector(0 to 3); +signal dir_row2_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row2_lru_d : std_ulogic_vector(0 to 2); +signal dir_row2_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row3_val_d : std_ulogic_vector(0 to 3); +signal dir_row3_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row3_lru_d : std_ulogic_vector(0 to 2); +signal dir_row3_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row4_val_d : std_ulogic_vector(0 to 3); +signal dir_row4_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row4_lru_d : std_ulogic_vector(0 to 2); +signal dir_row4_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row5_val_d : std_ulogic_vector(0 to 3); +signal dir_row5_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row5_lru_d : std_ulogic_vector(0 to 2); +signal dir_row5_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row6_val_d : std_ulogic_vector(0 to 3); +signal dir_row6_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row6_lru_d : std_ulogic_vector(0 to 2); +signal dir_row6_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row7_val_d : std_ulogic_vector(0 to 3); +signal dir_row7_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row7_lru_d : std_ulogic_vector(0 to 2); +signal dir_row7_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row8_val_d : std_ulogic_vector(0 to 3); +signal dir_row8_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row8_lru_d : std_ulogic_vector(0 to 2); +signal dir_row8_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row9_val_d : std_ulogic_vector(0 to 3); +signal dir_row9_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row9_lru_d : std_ulogic_vector(0 to 2); +signal dir_row9_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row10_val_d : std_ulogic_vector(0 to 3); +signal dir_row10_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row10_lru_d : std_ulogic_vector(0 to 2); +signal dir_row10_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row11_val_d : std_ulogic_vector(0 to 3); +signal dir_row11_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row11_lru_d : std_ulogic_vector(0 to 2); +signal dir_row11_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row12_val_d : std_ulogic_vector(0 to 3); +signal dir_row12_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row12_lru_d : std_ulogic_vector(0 to 2); +signal dir_row12_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row13_val_d : std_ulogic_vector(0 to 3); +signal dir_row13_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row13_lru_d : std_ulogic_vector(0 to 2); +signal dir_row13_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row14_val_d : std_ulogic_vector(0 to 3); +signal dir_row14_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row14_lru_d : std_ulogic_vector(0 to 2); +signal dir_row14_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row15_val_d : std_ulogic_vector(0 to 3); +signal dir_row15_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row15_lru_d : std_ulogic_vector(0 to 2); +signal dir_row15_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row16_val_d : std_ulogic_vector(0 to 3); +signal dir_row16_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row16_lru_d : std_ulogic_vector(0 to 2); +signal dir_row16_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row17_val_d : std_ulogic_vector(0 to 3); +signal dir_row17_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row17_lru_d : std_ulogic_vector(0 to 2); +signal dir_row17_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row18_val_d : std_ulogic_vector(0 to 3); +signal dir_row18_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row18_lru_d : std_ulogic_vector(0 to 2); +signal dir_row18_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row19_val_d : std_ulogic_vector(0 to 3); +signal dir_row19_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row19_lru_d : std_ulogic_vector(0 to 2); +signal dir_row19_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row20_val_d : std_ulogic_vector(0 to 3); +signal dir_row20_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row20_lru_d : std_ulogic_vector(0 to 2); +signal dir_row20_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row21_val_d : std_ulogic_vector(0 to 3); +signal dir_row21_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row21_lru_d : std_ulogic_vector(0 to 2); +signal dir_row21_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row22_val_d : std_ulogic_vector(0 to 3); +signal dir_row22_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row22_lru_d : std_ulogic_vector(0 to 2); +signal dir_row22_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row23_val_d : std_ulogic_vector(0 to 3); +signal dir_row23_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row23_lru_d : std_ulogic_vector(0 to 2); +signal dir_row23_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row24_val_d : std_ulogic_vector(0 to 3); +signal dir_row24_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row24_lru_d : std_ulogic_vector(0 to 2); +signal dir_row24_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row25_val_d : std_ulogic_vector(0 to 3); +signal dir_row25_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row25_lru_d : std_ulogic_vector(0 to 2); +signal dir_row25_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row26_val_d : std_ulogic_vector(0 to 3); +signal dir_row26_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row26_lru_d : std_ulogic_vector(0 to 2); +signal dir_row26_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row27_val_d : std_ulogic_vector(0 to 3); +signal dir_row27_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row27_lru_d : std_ulogic_vector(0 to 2); +signal dir_row27_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row28_val_d : std_ulogic_vector(0 to 3); +signal dir_row28_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row28_lru_d : std_ulogic_vector(0 to 2); +signal dir_row28_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row29_val_d : std_ulogic_vector(0 to 3); +signal dir_row29_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row29_lru_d : std_ulogic_vector(0 to 2); +signal dir_row29_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row30_val_d : std_ulogic_vector(0 to 3); +signal dir_row30_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row30_lru_d : std_ulogic_vector(0 to 2); +signal dir_row30_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row31_val_d : std_ulogic_vector(0 to 3); +signal dir_row31_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row31_lru_d : std_ulogic_vector(0 to 2); +signal dir_row31_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row32_val_d : std_ulogic_vector(0 to 3); +signal dir_row32_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row32_lru_d : std_ulogic_vector(0 to 2); +signal dir_row32_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row33_val_d : std_ulogic_vector(0 to 3); +signal dir_row33_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row33_lru_d : std_ulogic_vector(0 to 2); +signal dir_row33_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row34_val_d : std_ulogic_vector(0 to 3); +signal dir_row34_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row34_lru_d : std_ulogic_vector(0 to 2); +signal dir_row34_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row35_val_d : std_ulogic_vector(0 to 3); +signal dir_row35_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row35_lru_d : std_ulogic_vector(0 to 2); +signal dir_row35_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row36_val_d : std_ulogic_vector(0 to 3); +signal dir_row36_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row36_lru_d : std_ulogic_vector(0 to 2); +signal dir_row36_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row37_val_d : std_ulogic_vector(0 to 3); +signal dir_row37_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row37_lru_d : std_ulogic_vector(0 to 2); +signal dir_row37_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row38_val_d : std_ulogic_vector(0 to 3); +signal dir_row38_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row38_lru_d : std_ulogic_vector(0 to 2); +signal dir_row38_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row39_val_d : std_ulogic_vector(0 to 3); +signal dir_row39_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row39_lru_d : std_ulogic_vector(0 to 2); +signal dir_row39_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row40_val_d : std_ulogic_vector(0 to 3); +signal dir_row40_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row40_lru_d : std_ulogic_vector(0 to 2); +signal dir_row40_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row41_val_d : std_ulogic_vector(0 to 3); +signal dir_row41_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row41_lru_d : std_ulogic_vector(0 to 2); +signal dir_row41_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row42_val_d : std_ulogic_vector(0 to 3); +signal dir_row42_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row42_lru_d : std_ulogic_vector(0 to 2); +signal dir_row42_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row43_val_d : std_ulogic_vector(0 to 3); +signal dir_row43_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row43_lru_d : std_ulogic_vector(0 to 2); +signal dir_row43_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row44_val_d : std_ulogic_vector(0 to 3); +signal dir_row44_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row44_lru_d : std_ulogic_vector(0 to 2); +signal dir_row44_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row45_val_d : std_ulogic_vector(0 to 3); +signal dir_row45_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row45_lru_d : std_ulogic_vector(0 to 2); +signal dir_row45_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row46_val_d : std_ulogic_vector(0 to 3); +signal dir_row46_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row46_lru_d : std_ulogic_vector(0 to 2); +signal dir_row46_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row47_val_d : std_ulogic_vector(0 to 3); +signal dir_row47_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row47_lru_d : std_ulogic_vector(0 to 2); +signal dir_row47_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row48_val_d : std_ulogic_vector(0 to 3); +signal dir_row48_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row48_lru_d : std_ulogic_vector(0 to 2); +signal dir_row48_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row49_val_d : std_ulogic_vector(0 to 3); +signal dir_row49_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row49_lru_d : std_ulogic_vector(0 to 2); +signal dir_row49_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row50_val_d : std_ulogic_vector(0 to 3); +signal dir_row50_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row50_lru_d : std_ulogic_vector(0 to 2); +signal dir_row50_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row51_val_d : std_ulogic_vector(0 to 3); +signal dir_row51_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row51_lru_d : std_ulogic_vector(0 to 2); +signal dir_row51_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row52_val_d : std_ulogic_vector(0 to 3); +signal dir_row52_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row52_lru_d : std_ulogic_vector(0 to 2); +signal dir_row52_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row53_val_d : std_ulogic_vector(0 to 3); +signal dir_row53_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row53_lru_d : std_ulogic_vector(0 to 2); +signal dir_row53_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row54_val_d : std_ulogic_vector(0 to 3); +signal dir_row54_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row54_lru_d : std_ulogic_vector(0 to 2); +signal dir_row54_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row55_val_d : std_ulogic_vector(0 to 3); +signal dir_row55_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row55_lru_d : std_ulogic_vector(0 to 2); +signal dir_row55_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row56_val_d : std_ulogic_vector(0 to 3); +signal dir_row56_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row56_lru_d : std_ulogic_vector(0 to 2); +signal dir_row56_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row57_val_d : std_ulogic_vector(0 to 3); +signal dir_row57_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row57_lru_d : std_ulogic_vector(0 to 2); +signal dir_row57_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row58_val_d : std_ulogic_vector(0 to 3); +signal dir_row58_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row58_lru_d : std_ulogic_vector(0 to 2); +signal dir_row58_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row59_val_d : std_ulogic_vector(0 to 3); +signal dir_row59_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row59_lru_d : std_ulogic_vector(0 to 2); +signal dir_row59_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row60_val_d : std_ulogic_vector(0 to 3); +signal dir_row60_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row60_lru_d : std_ulogic_vector(0 to 2); +signal dir_row60_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row61_val_d : std_ulogic_vector(0 to 3); +signal dir_row61_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row61_lru_d : std_ulogic_vector(0 to 2); +signal dir_row61_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row62_val_d : std_ulogic_vector(0 to 3); +signal dir_row62_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row62_lru_d : std_ulogic_vector(0 to 2); +signal dir_row62_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row63_val_d : std_ulogic_vector(0 to 3); +signal dir_row63_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row63_lru_d : std_ulogic_vector(0 to 2); +signal dir_row63_lru_l2 : std_ulogic_vector(0 to 2); +signal iu3_instr_valid_d : std_ulogic_vector(0 to 3); +signal iu3_instr_valid_l2 : std_ulogic_vector(0 to 3); +signal iu3_tid_d : std_ulogic_vector(0 to 3); +signal iu3_tid_l2 : std_ulogic_vector(0 to 3); +signal iu3_ifar_d : EFF_IFAR; +signal iu3_ifar_l2 : EFF_IFAR; +signal iu3_ifar_dec_d : std_ulogic_vector(0 to 3); +signal iu3_ifar_dec_l2 : std_ulogic_vector(0 to 3); +signal iu3_2ucode_d : std_ulogic; +signal iu3_2ucode_l2 : std_ulogic; +signal iu3_2ucode_type_d : std_ulogic; +signal iu3_2ucode_type_l2 : std_ulogic; +signal iu3_erat_err_d : std_ulogic_vector(0 to 2); +signal iu3_erat_err_l2 : std_ulogic_vector(0 to 2); +signal iu3_dir_parity_err_way_d : std_ulogic_vector(0 to 3); +signal iu3_dir_parity_err_way_l2 : std_ulogic_vector(0 to 3); +signal iu3_data_parity_err_way_d : std_ulogic_vector(0 to 3); +signal iu3_data_parity_err_way_l2: std_ulogic_vector(0 to 3); +signal iu3_parity_tag_d : std_ulogic_vector(52 to 57); +signal iu3_parity_tag_l2 : std_ulogic_vector(52 to 57); +signal iu3_parity_needs_flush_d : std_ulogic_vector(0 to 3); +signal iu3_parity_needs_flush_l2 : std_ulogic_vector(0 to 3); +signal iu3_parity_needs_flush : std_ulogic; +signal iu3_parity_flush_tid : std_ulogic_vector(0 to 3); +signal iu3_parity_flush : std_ulogic; +signal iu3_rd_parity_err_d : std_ulogic; +signal iu3_rd_parity_err_l2 : std_ulogic; +signal iu3_rd_miss_d : std_ulogic; +signal iu3_rd_miss_l2 : std_ulogic; +signal err_icache_parity_d : std_ulogic; +signal err_icache_parity_l2 : std_ulogic; +signal err_icachedir_parity_d : std_ulogic; +signal err_icachedir_parity_l2 : std_ulogic; +signal iu3_multihit_err_way_d : std_ulogic_vector(0 to 3); +signal iu3_multihit_err_way_l2 : std_ulogic_vector(0 to 3); +signal iu3_multihit_flush_d : std_ulogic; +signal iu3_multihit_flush_l2 : std_ulogic; +signal perf_instr_count_t0_d : std_ulogic_vector(0 to 1); +signal perf_instr_count_t0_l2 : std_ulogic_vector(0 to 1); +signal perf_instr_count_t1_d : std_ulogic_vector(0 to 1); +signal perf_instr_count_t1_l2 : std_ulogic_vector(0 to 1); +signal perf_instr_count_t2_d : std_ulogic_vector(0 to 1); +signal perf_instr_count_t2_l2 : std_ulogic_vector(0 to 1); +signal perf_instr_count_t3_d : std_ulogic_vector(0 to 1); +signal perf_instr_count_t3_l2 : std_ulogic_vector(0 to 1); +signal perf_event_t0_d : std_ulogic_vector(4 to 6); +signal perf_event_t0_l2 : std_ulogic_vector(4 to 6); +signal perf_event_t1_d : std_ulogic_vector(4 to 6); +signal perf_event_t1_l2 : std_ulogic_vector(4 to 6); +signal perf_event_t2_d : std_ulogic_vector(4 to 6); +signal perf_event_t2_l2 : std_ulogic_vector(4 to 6); +signal perf_event_t3_d : std_ulogic_vector(4 to 6); +signal perf_event_t3_l2 : std_ulogic_vector(4 to 6); +signal perf_event_d : std_ulogic_vector(0 to 1); +signal perf_event_l2 : std_ulogic_vector(0 to 1); +signal spr_ic_cls_d : std_ulogic; +signal spr_ic_cls_l2 : std_ulogic; +signal spr_ic_idir_way_d : std_ulogic_vector(0 to 1); +signal spr_ic_idir_way_l2 : std_ulogic_vector(0 to 1); +signal iu1_spr_idir_read_d : std_ulogic; +signal iu1_spr_idir_read_l2 : std_ulogic; +signal iu2_spr_idir_read_d : std_ulogic; +signal iu2_spr_idir_read_l2 : std_ulogic; +signal iu2_spr_idir_lru_d : std_ulogic_vector(0 to 2); +signal iu2_spr_idir_lru_l2 : std_ulogic_vector(0 to 2); +signal dbg_dir_write_d : std_ulogic; +signal dbg_dir_write_l2 : std_ulogic; +signal dbg_dir_rd_act_d : std_ulogic; +signal dbg_dir_rd_act_l2 : std_ulogic; +signal dbg_iu2_lru_rd_update_d : std_ulogic; +signal dbg_iu2_lru_rd_update_l2 : std_ulogic; +signal dbg_iu2_rd_way_tag_hit_d : std_ulogic_vector(0 to 3); +signal dbg_iu2_rd_way_tag_hit_l2 : std_ulogic_vector(0 to 3); +signal dbg_iu2_rd_way_hit_d : std_ulogic_vector(0 to 3); +signal dbg_iu2_rd_way_hit_l2 : std_ulogic_vector(0 to 3); +signal dbg_load_iu2_d : std_ulogic; +signal dbg_load_iu2_l2 : std_ulogic; +signal spare_slp_l2 : std_ulogic_vector(0 to 15); +signal spare_l2 : std_ulogic_vector(0 to 15); +signal iu2_ci : std_ulogic; +signal iu2_endian : std_ulogic; +signal dir_rd_act : std_ulogic; +signal dir_write : std_ulogic; +signal dir_way : std_ulogic_vector(0 to ways-1); +signal dir_wr_addr : std_ulogic_vector(0 to 5); +signal dir_rd_addr : std_ulogic_vector(0 to 5); +signal ext_dir_datain : std_ulogic_vector(0 to dir_parity_width*8-1); +signal dir_parity_in : std_ulogic_vector(0 to dir_parity_width-1); +signal way_datain : std_ulogic_vector(0 to dir_array_way_width-1); +signal way_datain_rev : std_ulogic_vector(0 to dir_array_way_width-1); +signal dir_datain_rev : std_ulogic_vector(0 to dir_array_way_width*ways-1); +signal dir_dataout_rev : std_ulogic_vector(0 to dir_array_way_width*ways-1); +signal dir_dataout : std_ulogic_vector(0 to dir_array_way_width*ways-1); +signal dir_dataout_act : std_ulogic; +signal iu1_ifar_cacheline : std_ulogic_vector(0 to 5); +signal dir_rd_val : std_ulogic_vector(0 to 3); +signal data_write : std_ulogic; +signal data_way : std_ulogic_vector(0 to ways-1); +signal data_addr : std_ulogic_vector(0 to 7); +signal data_parity_in : std_ulogic_vector(0 to 17); +signal data_datain : std_ulogic_vector(0 to 161); +signal data_dataout : std_ulogic_vector(0 to 162*ways-1); +signal data_dataout_inj : std_ulogic_vector(0 to 162*ways-1); +signal ierat_iu_iu2_rpn_noncmp : std_ulogic_vector(22 to 51); +signal iu2_rd_way_tag_hit : std_ulogic_vector(0 to 3); +signal iu2_rd_way_hit : std_ulogic_vector(0 to 3); +signal iu2_rd_way_hit_insmux_b : std_ulogic_vector(0 to 3); +signal iu2_dir_miss : std_ulogic; +signal iu2_valid : std_ulogic; +signal dir_row_lru_even_act : std_ulogic; +signal dir_row_lru_odd_act : std_ulogic; +signal iu2_erat_err_lite : std_ulogic; +signal iu2_lru_rd_update : std_ulogic; +signal dir_row0_lru_read : std_ulogic_vector(0 to 2); +signal dir_row0_lru_write : std_ulogic_vector(0 to 2); +signal dir_row1_lru_read : std_ulogic_vector(0 to 2); +signal dir_row1_lru_write : std_ulogic_vector(0 to 2); +signal dir_row2_lru_read : std_ulogic_vector(0 to 2); +signal dir_row2_lru_write : std_ulogic_vector(0 to 2); +signal dir_row3_lru_read : std_ulogic_vector(0 to 2); +signal dir_row3_lru_write : std_ulogic_vector(0 to 2); +signal dir_row4_lru_read : std_ulogic_vector(0 to 2); +signal dir_row4_lru_write : std_ulogic_vector(0 to 2); +signal dir_row5_lru_read : std_ulogic_vector(0 to 2); +signal dir_row5_lru_write : std_ulogic_vector(0 to 2); +signal dir_row6_lru_read : std_ulogic_vector(0 to 2); +signal dir_row6_lru_write : std_ulogic_vector(0 to 2); +signal dir_row7_lru_read : std_ulogic_vector(0 to 2); +signal dir_row7_lru_write : std_ulogic_vector(0 to 2); +signal dir_row8_lru_read : std_ulogic_vector(0 to 2); +signal dir_row8_lru_write : std_ulogic_vector(0 to 2); +signal dir_row9_lru_read : std_ulogic_vector(0 to 2); +signal dir_row9_lru_write : std_ulogic_vector(0 to 2); +signal dir_row10_lru_read : std_ulogic_vector(0 to 2); +signal dir_row10_lru_write : std_ulogic_vector(0 to 2); +signal dir_row11_lru_read : std_ulogic_vector(0 to 2); +signal dir_row11_lru_write : std_ulogic_vector(0 to 2); +signal dir_row12_lru_read : std_ulogic_vector(0 to 2); +signal dir_row12_lru_write : std_ulogic_vector(0 to 2); +signal dir_row13_lru_read : std_ulogic_vector(0 to 2); +signal dir_row13_lru_write : std_ulogic_vector(0 to 2); +signal dir_row14_lru_read : std_ulogic_vector(0 to 2); +signal dir_row14_lru_write : std_ulogic_vector(0 to 2); +signal dir_row15_lru_read : std_ulogic_vector(0 to 2); +signal dir_row15_lru_write : std_ulogic_vector(0 to 2); +signal dir_row16_lru_read : std_ulogic_vector(0 to 2); +signal dir_row16_lru_write : std_ulogic_vector(0 to 2); +signal dir_row17_lru_read : std_ulogic_vector(0 to 2); +signal dir_row17_lru_write : std_ulogic_vector(0 to 2); +signal dir_row18_lru_read : std_ulogic_vector(0 to 2); +signal dir_row18_lru_write : std_ulogic_vector(0 to 2); +signal dir_row19_lru_read : std_ulogic_vector(0 to 2); +signal dir_row19_lru_write : std_ulogic_vector(0 to 2); +signal dir_row20_lru_read : std_ulogic_vector(0 to 2); +signal dir_row20_lru_write : std_ulogic_vector(0 to 2); +signal dir_row21_lru_read : std_ulogic_vector(0 to 2); +signal dir_row21_lru_write : std_ulogic_vector(0 to 2); +signal dir_row22_lru_read : std_ulogic_vector(0 to 2); +signal dir_row22_lru_write : std_ulogic_vector(0 to 2); +signal dir_row23_lru_read : std_ulogic_vector(0 to 2); +signal dir_row23_lru_write : std_ulogic_vector(0 to 2); +signal dir_row24_lru_read : std_ulogic_vector(0 to 2); +signal dir_row24_lru_write : std_ulogic_vector(0 to 2); +signal dir_row25_lru_read : std_ulogic_vector(0 to 2); +signal dir_row25_lru_write : std_ulogic_vector(0 to 2); +signal dir_row26_lru_read : std_ulogic_vector(0 to 2); +signal dir_row26_lru_write : std_ulogic_vector(0 to 2); +signal dir_row27_lru_read : std_ulogic_vector(0 to 2); +signal dir_row27_lru_write : std_ulogic_vector(0 to 2); +signal dir_row28_lru_read : std_ulogic_vector(0 to 2); +signal dir_row28_lru_write : std_ulogic_vector(0 to 2); +signal dir_row29_lru_read : std_ulogic_vector(0 to 2); +signal dir_row29_lru_write : std_ulogic_vector(0 to 2); +signal dir_row30_lru_read : std_ulogic_vector(0 to 2); +signal dir_row30_lru_write : std_ulogic_vector(0 to 2); +signal dir_row31_lru_read : std_ulogic_vector(0 to 2); +signal dir_row31_lru_write : std_ulogic_vector(0 to 2); +signal dir_row32_lru_read : std_ulogic_vector(0 to 2); +signal dir_row32_lru_write : std_ulogic_vector(0 to 2); +signal dir_row33_lru_read : std_ulogic_vector(0 to 2); +signal dir_row33_lru_write : std_ulogic_vector(0 to 2); +signal dir_row34_lru_read : std_ulogic_vector(0 to 2); +signal dir_row34_lru_write : std_ulogic_vector(0 to 2); +signal dir_row35_lru_read : std_ulogic_vector(0 to 2); +signal dir_row35_lru_write : std_ulogic_vector(0 to 2); +signal dir_row36_lru_read : std_ulogic_vector(0 to 2); +signal dir_row36_lru_write : std_ulogic_vector(0 to 2); +signal dir_row37_lru_read : std_ulogic_vector(0 to 2); +signal dir_row37_lru_write : std_ulogic_vector(0 to 2); +signal dir_row38_lru_read : std_ulogic_vector(0 to 2); +signal dir_row38_lru_write : std_ulogic_vector(0 to 2); +signal dir_row39_lru_read : std_ulogic_vector(0 to 2); +signal dir_row39_lru_write : std_ulogic_vector(0 to 2); +signal dir_row40_lru_read : std_ulogic_vector(0 to 2); +signal dir_row40_lru_write : std_ulogic_vector(0 to 2); +signal dir_row41_lru_read : std_ulogic_vector(0 to 2); +signal dir_row41_lru_write : std_ulogic_vector(0 to 2); +signal dir_row42_lru_read : std_ulogic_vector(0 to 2); +signal dir_row42_lru_write : std_ulogic_vector(0 to 2); +signal dir_row43_lru_read : std_ulogic_vector(0 to 2); +signal dir_row43_lru_write : std_ulogic_vector(0 to 2); +signal dir_row44_lru_read : std_ulogic_vector(0 to 2); +signal dir_row44_lru_write : std_ulogic_vector(0 to 2); +signal dir_row45_lru_read : std_ulogic_vector(0 to 2); +signal dir_row45_lru_write : std_ulogic_vector(0 to 2); +signal dir_row46_lru_read : std_ulogic_vector(0 to 2); +signal dir_row46_lru_write : std_ulogic_vector(0 to 2); +signal dir_row47_lru_read : std_ulogic_vector(0 to 2); +signal dir_row47_lru_write : std_ulogic_vector(0 to 2); +signal dir_row48_lru_read : std_ulogic_vector(0 to 2); +signal dir_row48_lru_write : std_ulogic_vector(0 to 2); +signal dir_row49_lru_read : std_ulogic_vector(0 to 2); +signal dir_row49_lru_write : std_ulogic_vector(0 to 2); +signal dir_row50_lru_read : std_ulogic_vector(0 to 2); +signal dir_row50_lru_write : std_ulogic_vector(0 to 2); +signal dir_row51_lru_read : std_ulogic_vector(0 to 2); +signal dir_row51_lru_write : std_ulogic_vector(0 to 2); +signal dir_row52_lru_read : std_ulogic_vector(0 to 2); +signal dir_row52_lru_write : std_ulogic_vector(0 to 2); +signal dir_row53_lru_read : std_ulogic_vector(0 to 2); +signal dir_row53_lru_write : std_ulogic_vector(0 to 2); +signal dir_row54_lru_read : std_ulogic_vector(0 to 2); +signal dir_row54_lru_write : std_ulogic_vector(0 to 2); +signal dir_row55_lru_read : std_ulogic_vector(0 to 2); +signal dir_row55_lru_write : std_ulogic_vector(0 to 2); +signal dir_row56_lru_read : std_ulogic_vector(0 to 2); +signal dir_row56_lru_write : std_ulogic_vector(0 to 2); +signal dir_row57_lru_read : std_ulogic_vector(0 to 2); +signal dir_row57_lru_write : std_ulogic_vector(0 to 2); +signal dir_row58_lru_read : std_ulogic_vector(0 to 2); +signal dir_row58_lru_write : std_ulogic_vector(0 to 2); +signal dir_row59_lru_read : std_ulogic_vector(0 to 2); +signal dir_row59_lru_write : std_ulogic_vector(0 to 2); +signal dir_row60_lru_read : std_ulogic_vector(0 to 2); +signal dir_row60_lru_write : std_ulogic_vector(0 to 2); +signal dir_row61_lru_read : std_ulogic_vector(0 to 2); +signal dir_row61_lru_write : std_ulogic_vector(0 to 2); +signal dir_row62_lru_read : std_ulogic_vector(0 to 2); +signal dir_row62_lru_write : std_ulogic_vector(0 to 2); +signal dir_row63_lru_read : std_ulogic_vector(0 to 2); +signal dir_row63_lru_write : std_ulogic_vector(0 to 2); +signal iu2_ifar_eff_cacheline : std_ulogic_vector(0 to 5); +signal iu3_parity_tag_cacheline : std_ulogic_vector(0 to 5); +signal reload_cacheline : std_ulogic_vector(0 to 5); +signal ecc_inval_cacheline : std_ulogic_vector(0 to 5); +signal lru_write_cacheline : std_ulogic_vector(0 to 5); +signal iu3_any_parity_err_way : std_ulogic_vector(0 to 3); +signal dir_row0_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row0_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row0_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row1_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row1_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row1_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row2_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row2_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row2_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row3_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row3_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row3_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row4_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row4_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row4_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row5_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row5_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row5_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row6_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row6_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row6_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row7_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row7_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row7_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row8_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row8_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row8_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row9_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row9_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row9_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row10_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row10_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row10_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row11_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row11_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row11_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row12_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row12_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row12_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row13_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row13_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row13_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row14_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row14_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row14_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row15_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row15_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row15_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row16_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row16_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row16_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row17_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row17_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row17_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row18_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row18_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row18_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row19_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row19_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row19_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row20_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row20_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row20_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row21_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row21_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row21_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row22_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row22_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row22_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row23_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row23_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row23_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row24_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row24_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row24_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row25_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row25_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row25_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row26_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row26_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row26_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row27_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row27_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row27_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row28_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row28_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row28_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row29_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row29_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row29_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row30_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row30_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row30_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row31_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row31_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row31_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row32_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row32_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row32_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row33_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row33_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row33_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row34_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row34_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row34_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row35_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row35_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row35_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row36_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row36_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row36_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row37_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row37_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row37_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row38_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row38_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row38_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row39_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row39_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row39_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row40_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row40_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row40_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row41_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row41_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row41_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row42_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row42_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row42_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row43_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row43_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row43_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row44_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row44_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row44_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row45_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row45_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row45_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row46_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row46_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row46_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row47_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row47_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row47_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row48_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row48_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row48_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row49_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row49_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row49_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row50_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row50_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row50_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row51_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row51_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row51_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row52_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row52_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row52_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row53_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row53_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row53_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row54_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row54_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row54_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row55_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row55_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row55_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row56_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row56_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row56_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row57_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row57_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row57_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row58_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row58_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row58_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row59_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row59_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row59_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row60_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row60_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row60_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row61_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row61_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row61_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row62_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row62_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row62_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row63_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row63_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row63_val_d_part2_b : std_ulogic_vector(0 to 3); +-- synopsys translate_off +-- synopsys translate_on +signal dir_row_val_even_act : std_ulogic; +signal dir_row_val_odd_act : std_ulogic; +signal iu2_multihit_err : std_ulogic; +signal iu3_multihit_err : std_ulogic; +signal iu2_pc_inj_icachedir_multihit : std_ulogic; +signal ext_dir_dataout0 : std_ulogic_vector(0 to dir_parity_width*8-1); +signal gen_dir_parity_out0 : std_ulogic_vector(0 to dir_parity_width-1); +signal dir_parity_err_byte0 : std_ulogic_vector(0 to dir_parity_width-1); +signal ext_dir_dataout1 : std_ulogic_vector(0 to dir_parity_width*8-1); +signal gen_dir_parity_out1 : std_ulogic_vector(0 to dir_parity_width-1); +signal dir_parity_err_byte1 : std_ulogic_vector(0 to dir_parity_width-1); +signal ext_dir_dataout2 : std_ulogic_vector(0 to dir_parity_width*8-1); +signal gen_dir_parity_out2 : std_ulogic_vector(0 to dir_parity_width-1); +signal dir_parity_err_byte2 : std_ulogic_vector(0 to dir_parity_width-1); +signal ext_dir_dataout3 : std_ulogic_vector(0 to dir_parity_width*8-1); +signal gen_dir_parity_out3 : std_ulogic_vector(0 to dir_parity_width-1); +signal dir_parity_err_byte3 : std_ulogic_vector(0 to dir_parity_width-1); +signal dir_parity_err_way : std_ulogic_vector(0 to 3); +signal dir_parity_err : std_ulogic; +signal iu2_rd_parity_err : std_ulogic; +signal data_parity_out0 : std_ulogic_vector(0 to 17); +signal gen_data_parity_out0 : std_ulogic_vector(0 to 17); +signal data_parity_err_byte0 : std_ulogic_vector(0 to 17); +signal data_parity_out1 : std_ulogic_vector(0 to 17); +signal gen_data_parity_out1 : std_ulogic_vector(0 to 17); +signal data_parity_err_byte1 : std_ulogic_vector(0 to 17); +signal data_parity_out2 : std_ulogic_vector(0 to 17); +signal gen_data_parity_out2 : std_ulogic_vector(0 to 17); +signal data_parity_err_byte2 : std_ulogic_vector(0 to 17); +signal data_parity_out3 : std_ulogic_vector(0 to 17); +signal gen_data_parity_out3 : std_ulogic_vector(0 to 17); +signal data_parity_err_byte3 : std_ulogic_vector(0 to 17); +signal data_parity_err : std_ulogic; +signal iu3_parity_act : std_ulogic; +signal lru_select : std_ulogic_vector(0 to 5); +signal return_lru : std_ulogic_vector(0 to 2); +signal return_val : std_ulogic_vector(0 to 3); +signal iu2_rd_miss : std_ulogic; +signal iu3_rd_miss : std_ulogic; +signal iu2_miss_flush_prev : std_ulogic_vector(0 to 3); +signal load_iu2 : std_ulogic; +signal iu3_act : std_ulogic; +signal iu3_valid_next : std_ulogic; +signal iu2_erat_err : std_ulogic_vector(0 to 2); +signal iu2_data_dataout_0 : std_ulogic_vector(0 to 143); +signal iu2_data_dataout_1 : std_ulogic_vector(0 to 143); +signal iu2_data_dataout_2 : std_ulogic_vector(0 to 143); +signal iu2_data_dataout_3 : std_ulogic_vector(0 to 143); +signal iu3_instr0_buf : std_ulogic_vector(0 to 35); +signal iu3_instr1_buf : std_ulogic_vector(0 to 35); +signal iu3_instr2_buf : std_ulogic_vector(0 to 35); +signal iu3_instr3_buf : std_ulogic_vector(0 to 35); +signal iu2_ifar_dec : std_ulogic_vector(0 to 3); +signal uc_illegal : std_ulogic; +signal xnop : std_ulogic_vector(0 to 35); +signal int_ic_bp_iu3_error : std_ulogic_vector(0 to 2); +signal iu3_0_instr_rot : std_ulogic_vector(0 to 35); +signal iu3_1_instr_rot : std_ulogic_vector(0 to 35); +signal iu3_2_instr_rot : std_ulogic_vector(0 to 35); +signal iu3_3_instr_rot : std_ulogic_vector(0 to 35); +signal int_ic_bp_iu3_flush : std_ulogic; +signal iu2_instr_count : std_ulogic_vector(0 to 2); +signal perf_instr_count_t0_new: std_ulogic_vector(0 to 2); +signal perf_instr_count_t1_new: std_ulogic_vector(0 to 2); +signal perf_instr_count_t2_new: std_ulogic_vector(0 to 2); +signal perf_instr_count_t3_new: std_ulogic_vector(0 to 2); +signal stage_abist_g8t_wenb : std_ulogic; +signal stage_abist_g8t1p_renb_0 : std_ulogic; +signal stage_abist_di_0 : std_ulogic_vector(0 to 3); +signal stage_abist_g8t_bw_1 : std_ulogic; +signal stage_abist_g8t_bw_0 : std_ulogic; +signal stage_abist_waddr_0 : std_ulogic_vector(4 to 9); +signal stage_abist_raddr_0 : std_ulogic_vector(2 to 9); +signal stage_abist_wl64_comp_ena : std_ulogic; +signal stage_abist_g8t_dcomp : std_ulogic_vector(0 to 3); +signal stage_abist_g6t_bw : std_ulogic_vector(0 to 1); +signal stage_abist_di_g6t_2r : std_ulogic_vector(0 to 3); +signal stage_abist_wl256_comp_ena : std_ulogic; +signal stage_abist_dcomp_g6t_2r : std_ulogic_vector(0 to 3); +signal stage_abist_g6t_r_wb : std_ulogic; +signal siv : std_ulogic_vector(0 to scan_right); +signal sov : std_ulogic_vector(0 to scan_right); +signal abst_siv : std_ulogic_vector(0 to 42); +signal abst_sov : std_ulogic_vector(0 to 42); +signal time_siv : std_ulogic_vector(0 to 2); +signal time_sov : std_ulogic_vector(0 to 2); +signal repr_siv : std_ulogic_vector(0 to 2); +signal repr_sov : std_ulogic_vector(0 to 2); +signal repr_slat_sl_thold_0_b : std_ulogic; +signal time_slat_sl_thold_0_b : std_ulogic; +-- synopsys translate_off +-- synopsys translate_on + BEGIN + +tidn <= '0'; +tiup <= '1'; +ZEROS <= (others => '0'); +spr_ic_cls_d <= spr_ic_cls; +spr_ic_idir_way_d <= spr_ic_idir_way; +xu_iu_ici_d <= xu_iu_ici; +iu1_valid_d <= ics_icd_iu0_valid; +iu1_tid_d <= ics_icd_iu0_tid; +iu1_ifar_d <= ics_icd_iu0_ifar; +iu1_inval_d <= ics_icd_iu0_inval; +iu1_2ucode_d <= ics_icd_iu0_2ucode; +iu1_2ucode_type_d <= ics_icd_iu0_2ucode_type; +iu1_spr_idir_read_d <= ics_icd_iu0_spr_idir_read; +icd_ics_iu1_valid <= iu1_valid_l2; +icd_ics_iu1_tid <= iu1_tid_l2; +icd_ics_iu1_ifar <= iu1_ifar_l2; +icd_ics_iu1_2ucode <= iu1_2ucode_l2; +icd_ics_iu1_2ucode_type <= iu1_2ucode_type_l2; +iu_ierat_iu1_back_inv <= iu1_inval_l2; +iu2_ci <= ierat_iu_iu2_wimge(1); +iu2_endian <= ierat_iu_iu2_wimge(4); +iu2_ifar_eff_d <= iu1_ifar_l2; +dir_rd_act <= ics_icd_dir_rd_act; +dir_write <= icm_icd_dir_write; +dir_way <= icm_icd_dir_write_way; +dir_wr_addr <= icm_icd_dir_write_addr(52 to 56) & (icm_icd_dir_write_addr(57) and not spr_ic_cls_l2); +dir_rd_addr <= ics_icd_iu0_ifar(52 to 56) & + (ics_icd_iu0_ifar(57) and not (spr_ic_cls_l2 and not ics_icd_iu0_spr_idir_read)); +calc_ext_dir_data: for i in ext_dir_datain'range generate +begin + R0:if(i < 52-REAL_IFAR'left) generate begin ext_dir_datain(i) <= icm_icd_dir_write_addr(REAL_IFAR'left+i); +end generate; +R1:if(i = 52-REAL_IFAR'left) generate +begin ext_dir_datain(i) <= icm_icd_dir_write_endian; +end generate; +R2:if(i > 52-REAL_IFAR'left) generate +begin ext_dir_datain(i) <= '0'; +end generate; +end generate; +gen_dir_parity: for i in dir_parity_in'range generate +begin + dir_parity_in(i) <= xor_reduce( ext_dir_datain(i*8 to i*8+7) ); +end generate; +way_datain(0 TO 52-REAL_IFAR'left-1) <= icm_icd_dir_write_addr(REAL_IFAR'left to 51); +way_datain(52-REAL_IFAR'left) <= icm_icd_dir_write_endian; +way_datain(52-REAL_IFAR'left+1 TO 52-REAL_IFAR'left+1+dir_parity_width-1) <= dir_parity_in; +ext: if (dir_way_width < way_datain'length) generate +way_datain(52-REAL_IFAR'left+1+dir_parity_width TO way_datain'right) <= (others => '0'); +end generate; +way_datain_rev <= reverse(way_datain); +dir_datain_rev <= way_datain_rev & way_datain_rev & way_datain_rev & way_datain_rev; +idir: entity tri.tri_64x36_4w_1r1w(tri_64x36_4w_1r1w) + generic map ( expand_type => expand_type ) + port map( + gnd => gnd, + vdd => vdd, + vcs => vcs, + nclk => nclk, + rd_act => dir_rd_act, + wr_act => dir_write, + sg_0 => pc_iu_sg_0, + abst_sl_thold_0 => pc_iu_abst_slp_sl_thold_0, + ary_nsl_thold_0 => pc_iu_ary_slp_nsl_thold_0, + time_sl_thold_0 => pc_iu_time_sl_thold_0, + repr_sl_thold_0 => pc_iu_repr_sl_thold_0, + clkoff_dc_b => g8t_clkoff_b, + ccflush_dc => tc_ac_ccflush_dc, + scan_dis_dc_b => an_ac_scan_dis_dc_b, + scan_diag_dc => an_ac_scan_diag_dc, + d_mode_dc => g8t_d_mode, + mpw1_dc_b => g8t_mpw1_b, + mpw2_dc_b => g8t_mpw2_b, + delay_lclkr_dc => g8t_delay_lclkr, + wr_abst_act => stage_abist_g8t_wenb, + rd0_abst_act => stage_abist_g8t1p_renb_0, + abist_di => stage_abist_di_0, + abist_bw_odd => stage_abist_g8t_bw_1, + abist_bw_even => stage_abist_g8t_bw_0, + abist_wr_adr => stage_abist_waddr_0(4 to 9), + abist_rd0_adr => stage_abist_raddr_0(4 to 9), + tc_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc, + abist_ena_1 => pc_iu_abist_ena_dc, + abist_g8t_rd0_comp_ena => stage_abist_wl64_comp_ena, + abist_raw_dc_b => pc_iu_abist_raw_dc_b, + obs0_abist_cmp => stage_abist_g8t_dcomp, + abst_scan_in(0) => abst_siv(0), + abst_scan_in(1) => abst_siv(2), + time_scan_in => time_siv(0), + repr_scan_in => repr_siv(0), + abst_scan_out(0) => abst_sov(0), + abst_scan_out(1) => abst_sov(2), + time_scan_out => time_sov(0), + repr_scan_out => repr_sov(0), + lcb_bolt_sl_thold_0 => pc_iu_bolt_sl_thold_0, + pc_bo_enable_2 => pc_iu_bo_enable_2, + pc_bo_reset => pc_iu_bo_reset, + pc_bo_unload => pc_iu_bo_unload, + pc_bo_repair => pc_iu_bo_repair, + pc_bo_shdata => pc_iu_bo_shdata, + pc_bo_select => pc_iu_bo_select(0 to 1), + bo_pc_failout => iu_pc_bo_fail(0 to 1), + bo_pc_diagloop => iu_pc_bo_diagout(0 to 1), + tri_lcb_mpw1_dc_b => mpw1_b, + tri_lcb_mpw2_dc_b => mpw2_b, + tri_lcb_delay_lclkr_dc => delay_lclkr, + tri_lcb_clkoff_dc_b => clkoff_b, + tri_lcb_act_dis_dc => act_dis, + wr_way => dir_way, + wr_addr => dir_wr_addr, + data_in => dir_datain_rev, + rd_addr => dir_rd_addr, + data_out => dir_dataout_rev +); +dir_dataout(0 TO dir_array_way_width-1) <= reverse(dir_dataout_rev( 0 to dir_array_way_width-1)); +dir_dataout(dir_array_way_width TO 2*dir_array_way_width-1) <= reverse(dir_dataout_rev( dir_array_way_width to 2*dir_array_way_width-1)); +dir_dataout(2*dir_array_way_width TO 3*dir_array_way_width-1) <= reverse(dir_dataout_rev(2*dir_array_way_width to 3*dir_array_way_width-1)); +dir_dataout(3*dir_array_way_width TO 4*dir_array_way_width-1) <= reverse(dir_dataout_rev(3*dir_array_way_width to 4*dir_array_way_width-1)); +dir_dataout_act <= iu1_valid_l2 or iu1_inval_l2 or iu1_spr_idir_read_l2; +iu2_dir_dataout_0_d(REAL_IFAR'left) <= dir_dataout(0) xor pc_iu_inj_icachedir_parity; +iu2_dir_dataout_0_d(REAL_IFAR'left+1 TO iu2_dir_dataout_0_d'right) <= dir_dataout( 1 to dir_way_width-dir_parity_width-1); +iu2_dir_dataout_1_d(REAL_IFAR'left TO iu2_dir_dataout_1_d'right) <= dir_dataout( dir_array_way_width to dir_array_way_width+dir_way_width-dir_parity_width-1); +iu2_dir_dataout_2_d(REAL_IFAR'left TO iu2_dir_dataout_1_d'right) <= dir_dataout(2*dir_array_way_width to 2*dir_array_way_width+dir_way_width-dir_parity_width-1); +iu2_dir_dataout_3_d(REAL_IFAR'left TO iu2_dir_dataout_1_d'right) <= dir_dataout(3*dir_array_way_width to 3*dir_array_way_width+dir_way_width-dir_parity_width-1); +ext_iu2_dir_dataout: if (REAL_IFAR'left > 22) generate +begin + iu2_dir_dataout_0_d(22 TO REAL_IFAR'left-1) <= (others => '0'); +iu2_dir_dataout_1_d(22 TO REAL_IFAR'left-1) <= (others => '0'); +iu2_dir_dataout_2_d(22 TO REAL_IFAR'left-1) <= (others => '0'); +iu2_dir_dataout_3_d(22 TO REAL_IFAR'left-1) <= (others => '0'); +end generate; +iu2_dir_dataout_0_par_d <= dir_dataout( dir_way_width-dir_parity_width to dir_way_width-1); +iu2_dir_dataout_1_par_d <= dir_dataout( dir_array_way_width+dir_way_width-dir_parity_width to dir_array_way_width+dir_way_width-1); +iu2_dir_dataout_2_par_d <= dir_dataout(2*dir_array_way_width+dir_way_width-dir_parity_width to 2*dir_array_way_width+dir_way_width-1); +iu2_dir_dataout_3_par_d <= dir_dataout(3*dir_array_way_width+dir_way_width-dir_parity_width to 3*dir_array_way_width+dir_way_width-1); +iu1_ifar_cacheline <= iu1_ifar_l2(52 to 56) & + (iu1_ifar_l2(57) and not (spr_ic_cls_l2 and not iu1_spr_idir_read_l2)); +with iu1_ifar_cacheline select +dir_rd_val <= dir_row0_val_l2 when "000000", + dir_row1_val_l2 when "000001", + dir_row2_val_l2 when "000010", + dir_row3_val_l2 when "000011", + dir_row4_val_l2 when "000100", + dir_row5_val_l2 when "000101", + dir_row6_val_l2 when "000110", + dir_row7_val_l2 when "000111", + dir_row8_val_l2 when "001000", + dir_row9_val_l2 when "001001", + dir_row10_val_l2 when "001010", + dir_row11_val_l2 when "001011", + dir_row12_val_l2 when "001100", + dir_row13_val_l2 when "001101", + dir_row14_val_l2 when "001110", + dir_row15_val_l2 when "001111", + dir_row16_val_l2 when "010000", + dir_row17_val_l2 when "010001", + dir_row18_val_l2 when "010010", + dir_row19_val_l2 when "010011", + dir_row20_val_l2 when "010100", + dir_row21_val_l2 when "010101", + dir_row22_val_l2 when "010110", + dir_row23_val_l2 when "010111", + dir_row24_val_l2 when "011000", + dir_row25_val_l2 when "011001", + dir_row26_val_l2 when "011010", + dir_row27_val_l2 when "011011", + dir_row28_val_l2 when "011100", + dir_row29_val_l2 when "011101", + dir_row30_val_l2 when "011110", + dir_row31_val_l2 when "011111", + dir_row32_val_l2 when "100000", + dir_row33_val_l2 when "100001", + dir_row34_val_l2 when "100010", + dir_row35_val_l2 when "100011", + dir_row36_val_l2 when "100100", + dir_row37_val_l2 when "100101", + dir_row38_val_l2 when "100110", + dir_row39_val_l2 when "100111", + dir_row40_val_l2 when "101000", + dir_row41_val_l2 when "101001", + dir_row42_val_l2 when "101010", + dir_row43_val_l2 when "101011", + dir_row44_val_l2 when "101100", + dir_row45_val_l2 when "101101", + dir_row46_val_l2 when "101110", + dir_row47_val_l2 when "101111", + dir_row48_val_l2 when "110000", + dir_row49_val_l2 when "110001", + dir_row50_val_l2 when "110010", + dir_row51_val_l2 when "110011", + dir_row52_val_l2 when "110100", + dir_row53_val_l2 when "110101", + dir_row54_val_l2 when "110110", + dir_row55_val_l2 when "110111", + dir_row56_val_l2 when "111000", + dir_row57_val_l2 when "111001", + dir_row58_val_l2 when "111010", + dir_row59_val_l2 when "111011", + dir_row60_val_l2 when "111100", + dir_row61_val_l2 when "111101", + dir_row62_val_l2 when "111110", + dir_row63_val_l2 when "111111", + "0000" when others; +iu2_dir_rd_val_d <= dir_rd_val; +with spr_ic_idir_way_l2 select +ic_spr_idir_valid <= iu2_dir_rd_val_l2(0) when "00", + iu2_dir_rd_val_l2(1) when "01", + iu2_dir_rd_val_l2(2) when "10", + iu2_dir_rd_val_l2(3) when others; + WITH s6'(iu1_ifar_l2(52 to 57)) SELECT iu2_spr_idir_lru_d <= dir_row0_lru_l2 when "000000", + dir_row1_lru_l2 when "000001", + dir_row2_lru_l2 when "000010", + dir_row3_lru_l2 when "000011", + dir_row4_lru_l2 when "000100", + dir_row5_lru_l2 when "000101", + dir_row6_lru_l2 when "000110", + dir_row7_lru_l2 when "000111", + dir_row8_lru_l2 when "001000", + dir_row9_lru_l2 when "001001", + dir_row10_lru_l2 when "001010", + dir_row11_lru_l2 when "001011", + dir_row12_lru_l2 when "001100", + dir_row13_lru_l2 when "001101", + dir_row14_lru_l2 when "001110", + dir_row15_lru_l2 when "001111", + dir_row16_lru_l2 when "010000", + dir_row17_lru_l2 when "010001", + dir_row18_lru_l2 when "010010", + dir_row19_lru_l2 when "010011", + dir_row20_lru_l2 when "010100", + dir_row21_lru_l2 when "010101", + dir_row22_lru_l2 when "010110", + dir_row23_lru_l2 when "010111", + dir_row24_lru_l2 when "011000", + dir_row25_lru_l2 when "011001", + dir_row26_lru_l2 when "011010", + dir_row27_lru_l2 when "011011", + dir_row28_lru_l2 when "011100", + dir_row29_lru_l2 when "011101", + dir_row30_lru_l2 when "011110", + dir_row31_lru_l2 when "011111", + dir_row32_lru_l2 when "100000", + dir_row33_lru_l2 when "100001", + dir_row34_lru_l2 when "100010", + dir_row35_lru_l2 when "100011", + dir_row36_lru_l2 when "100100", + dir_row37_lru_l2 when "100101", + dir_row38_lru_l2 when "100110", + dir_row39_lru_l2 when "100111", + dir_row40_lru_l2 when "101000", + dir_row41_lru_l2 when "101001", + dir_row42_lru_l2 when "101010", + dir_row43_lru_l2 when "101011", + dir_row44_lru_l2 when "101100", + dir_row45_lru_l2 when "101101", + dir_row46_lru_l2 when "101110", + dir_row47_lru_l2 when "101111", + dir_row48_lru_l2 when "110000", + dir_row49_lru_l2 when "110001", + dir_row50_lru_l2 when "110010", + dir_row51_lru_l2 when "110011", + dir_row52_lru_l2 when "110100", + dir_row53_lru_l2 when "110101", + dir_row54_lru_l2 when "110110", + dir_row55_lru_l2 when "110111", + dir_row56_lru_l2 when "111000", + dir_row57_lru_l2 when "111001", + dir_row58_lru_l2 when "111010", + dir_row59_lru_l2 when "111011", + dir_row60_lru_l2 when "111100", + dir_row61_lru_l2 when "111101", + dir_row62_lru_l2 when "111110", + dir_row63_lru_l2 when others; +ic_spr_idir_lru <= iu2_spr_idir_lru_l2; +with spr_ic_idir_way_l2 select +ic_spr_idir_tag <= iu2_dir_dataout_0_noncmp(22 to 51) when "00", + iu2_dir_dataout_1_noncmp(22 to 51) when "01", + iu2_dir_dataout_2_noncmp(22 to 51) when "10", + iu2_dir_dataout_3_noncmp(22 to 51) when others; +with spr_ic_idir_way_l2 select +ic_spr_idir_endian <= iu2_dir_dataout_0_noncmp(52) when "00", + iu2_dir_dataout_1_noncmp(52) when "01", + iu2_dir_dataout_2_noncmp(52) when "10", + iu2_dir_dataout_3_noncmp(52) when others; +with spr_ic_idir_way_l2 select +ic_spr_idir_parity(0 to dir_parity_width-1) <= iu2_dir_dataout_0_par_l2 when "00", + iu2_dir_dataout_1_par_l2 when "01", + iu2_dir_dataout_2_par_l2 when "10", + iu2_dir_dataout_3_par_l2 when others; +ext_spr_parity: if (dir_parity_width < 4) generate +begin ic_spr_idir_parity(dir_parity_width TO 3) <= (others => '0'); +end generate; +ic_spr_idir_done <= iu2_spr_idir_read_l2; +data_write <= icm_icd_data_write; +data_way <= icm_icd_reload_way; +data_addr <= icm_icd_reload_addr(52 to 59) when data_write = '1' + else ics_icd_iu0_ifar(52 to 59); +data_parity_in <= icm_icd_reload_data(144 to 161); +data_datain <= icm_icd_reload_data(0 to 143) & data_parity_in; +idata: entity tri.tri_256x162_4w_0(tri_256x162_4w_0) + generic map ( expand_type => expand_type ) + port map( + gnd => gnd, + vdd => vdd, + vcs => vcs, + nclk => nclk, + ccflush_dc => tc_ac_ccflush_dc, + lcb_clkoff_dc_b => g6t_clkoff_b, + lcb_d_mode_dc => g6t_d_mode, + lcb_act_dis_dc => g6t_act_dis, + lcb_ary_nsl_thold_0 => pc_iu_ary_nsl_thold_0, + lcb_sg_1 => pc_iu_sg_1, + lcb_abst_sl_thold_0 => pc_iu_abst_sl_thold_0, + scan_diag_dc => an_ac_scan_diag_dc, + scan_dis_dc_b => an_ac_scan_dis_dc_b, + abst_scan_in(0) => abst_siv(1), + abst_scan_in(1) => abst_siv(3), + abst_scan_out(0) => abst_sov(1), + abst_scan_out(1) => abst_sov(3), + lcb_delay_lclkr_np_dc => g6t_delay_lclkr(0), + ctrl_lcb_delay_lclkr_np_dc => g6t_delay_lclkr(1), + dibw_lcb_delay_lclkr_np_dc => g6t_delay_lclkr(2), + ctrl_lcb_mpw1_np_dc_b => g6t_mpw1_b(0), + dibw_lcb_mpw1_np_dc_b => g6t_mpw1_b(1), + lcb_mpw1_pp_dc_b => g6t_mpw1_b(2), + lcb_mpw1_2_pp_dc_b => g6t_mpw1_b(3), + aodo_lcb_delay_lclkr_dc => g6t_delay_lclkr(3), + aodo_lcb_mpw1_dc_b => g6t_mpw1_b(4), + aodo_lcb_mpw2_dc_b => g6t_mpw2_b, + lcb_time_sg_0 => pc_iu_sg_0, + lcb_time_sl_thold_0 => pc_iu_time_sl_thold_0, + time_scan_in => time_siv(1), + time_scan_out => time_sov(1), + bitw_abist => stage_abist_g6t_bw, + lcb_repr_sl_thold_0 => pc_iu_repr_sl_thold_0, + lcb_repr_sg_0 => pc_iu_sg_0, + repr_scan_in => repr_siv(1), + repr_scan_out => repr_sov(1), + tc_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc, + abist_en_1 => pc_iu_abist_ena_dc, + din_abist => stage_abist_di_g6t_2r, + abist_cmp_en => stage_abist_wl256_comp_ena, + abist_raw_b_dc => pc_iu_abist_raw_dc_b, + data_cmp_abist => stage_abist_dcomp_g6t_2r, + addr_abist => stage_abist_raddr_0(2 to 9), + r_wb_abist => stage_abist_g6t_r_wb, + write_thru_en_dc => tidn, + lcb_bolt_sl_thold_0 => pc_iu_bolt_sl_thold_0, + pc_bo_enable_2 => pc_iu_bo_enable_2, + pc_bo_reset => pc_iu_bo_reset, + pc_bo_unload => pc_iu_bo_unload, + pc_bo_repair => pc_iu_bo_repair, + pc_bo_shdata => pc_iu_bo_shdata, + pc_bo_select => pc_iu_bo_select(2 to 3), + bo_pc_failout => iu_pc_bo_fail(2 to 3), + bo_pc_diagloop => iu_pc_bo_diagout(2 to 3), + tri_lcb_mpw1_dc_b => mpw1_b, + tri_lcb_mpw2_dc_b => mpw2_b, + tri_lcb_delay_lclkr_dc => delay_lclkr, + tri_lcb_clkoff_dc_b => clkoff_b, + tri_lcb_act_dis_dc => act_dis, + read_act => ics_icd_data_rd_act, + write_enable => data_write, + write_way => data_way, + addr => data_addr, + data_in => data_datain, + data_out => data_dataout +); +iu2_data_dataout_d <= data_dataout; +data_dataout_inj(0) <= iu2_data_dataout_l2(0) xor pc_iu_inj_icache_parity; +data_dataout_inj(1 TO data_dataout'right) <= iu2_data_dataout_l2(1 to data_dataout'right); +dircmp: entity work.iuq_ic_dir_cmp(iuq_ic_dir_cmp) + generic map ( expand_type => expand_type ) + port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + forcee => funcslp_force, + sg_0 => pc_iu_sg_0, + thold_0_b => pc_iu_func_slp_sl_thold_0_b, + scan_in => siv(iu2_dir_dataout_offset), + scan_out => sov(iu2_dir_dataout_offset), + dir_dataout_act => dir_dataout_act , + iu2_endian => iu2_endian , + ierat_iu_iu2_rpn(22 to 51) => ierat_iu_iu2_rpn(22 to 51) , + iu2_dir_dataout_0_d(22 to 52) => iu2_dir_dataout_0_d(22 to 52) , + iu2_dir_dataout_1_d(22 to 52) => iu2_dir_dataout_1_d(22 to 52) , + iu2_dir_dataout_2_d(22 to 52) => iu2_dir_dataout_2_d(22 to 52) , + iu2_dir_dataout_3_d(22 to 52) => iu2_dir_dataout_3_d(22 to 52) , + ierat_iu_iu2_rpn_noncmp(22 to 51) => ierat_iu_iu2_rpn_noncmp(22 to 51) , + iu2_dir_dataout_0_noncmp(22 to 52) => iu2_dir_dataout_0_noncmp(22 to 52) , + iu2_dir_dataout_1_noncmp(22 to 52) => iu2_dir_dataout_1_noncmp(22 to 52) , + iu2_dir_dataout_2_noncmp(22 to 52) => iu2_dir_dataout_2_noncmp(22 to 52) , + iu2_dir_dataout_3_noncmp(22 to 52) => iu2_dir_dataout_3_noncmp(22 to 52) , + iu2_dir_rd_val(0 to 3) => iu2_dir_rd_val_l2(0 to 3) , + iu2_rd_way_tag_hit(0 to 3) => iu2_rd_way_tag_hit(0 to 3) , + iu2_rd_way_hit(0 to 3) => iu2_rd_way_hit(0 to 3) , + iu2_rd_way_hit_insmux_b(0 to 3) => iu2_rd_way_hit_insmux_b(0 to 3) ); +iu2_dir_miss <= not or_reduce(iu2_rd_way_hit); +iu2_valid_d <= iu1_valid_l2 and or_reduce(iu1_tid_l2 and not ics_icd_iu1_flush_tid and not ics_icd_all_flush_prev); +iu2_valid <= iu2_valid_l2 and or_reduce(iu2_tid_l2 and not ics_icd_all_flush_prev and not iu2_miss_flush_prev); +iu2_tid_d <= iu1_tid_l2; +iu2_2ucode_d <= iu1_2ucode_l2; +iu2_2ucode_type_d <= iu1_2ucode_type_l2; +iu2_inval_d <= iu1_inval_l2; +iu2_spr_idir_read_d <= iu1_spr_idir_read_l2; +iu2_multihit_err <= (iu2_valid or iu2_inval_l2 or iu2_spr_idir_read_l2) and + not (( iu2_rd_way_hit(0 to 2) = "000") or + ((iu2_rd_way_hit(0 to 1) & iu2_rd_way_hit(3)) = "000") or + ((iu2_rd_way_hit(0) & iu2_rd_way_hit(2 to 3)) = "000") or + ( iu2_rd_way_hit(1 to 3) = "000")); +iu2_pc_inj_icachedir_multihit <= (iu2_valid or iu2_inval_l2 or iu2_spr_idir_read_l2) and pc_iu_inj_icachedir_multihit and not iu2_dir_miss; +iu3_multihit_err_way_d <= gate_and(iu2_multihit_err, iu2_rd_way_hit) or + (iu2_pc_inj_icachedir_multihit & iu2_pc_inj_icachedir_multihit & iu2_pc_inj_icachedir_multihit & iu2_pc_inj_icachedir_multihit); +iu3_multihit_err <= or_reduce(iu3_multihit_err_way_l2); +iu3_multihit_flush_d <= (iu2_multihit_err or (pc_iu_inj_icachedir_multihit and not iu2_dir_miss)) and (iu2_valid and or_reduce(iu2_tid_l2 and not ics_icd_iu2_flush_tid) and not iu2_ci); +err_icachedir_multihit: tri_direct_err_rpt + generic map (width => 1, expand_type => expand_type) + port map ( + vd => vdd, + gd => gnd, + err_in(0) => iu3_multihit_err, + err_out(0) => iu_pc_err_icachedir_multihit + ); +calc_ext_dir_dataout0: for i in ext_dir_datain'range generate +begin + R0:if(i < 52-REAL_IFAR'left+1) generate begin ext_dir_dataout0(i) <= iu2_dir_dataout_0_noncmp(REAL_IFAR'left+i); +end generate; +R1:if(i >= 52-REAL_IFAR'left+1) generate +begin ext_dir_dataout0(i) <= '0'; +end generate; +end generate; +chk_dir_parity0: for i in dir_parity_in'range generate +begin + gen_dir_parity_out0(i) <= xor_reduce( ext_dir_dataout0(i*8 to i*8+7) ); +end generate; +dir_parity_err_byte0 <= iu2_dir_dataout_0_par_l2 xor gen_dir_parity_out0; +dir_parity_err_way(0) <= or_reduce(dir_parity_err_byte0) and iu2_dir_rd_val_l2(0) and (iu2_valid or iu2_inval_l2 or iu2_spr_idir_read_l2); +calc_ext_dir_dataout1: for i in ext_dir_datain'range generate +begin + R0:if(i < 52-REAL_IFAR'left+1) generate begin ext_dir_dataout1(i) <= iu2_dir_dataout_1_noncmp(REAL_IFAR'left+i); +end generate; +R1:if(i >= 52-REAL_IFAR'left+1) generate +begin ext_dir_dataout1(i) <= '0'; +end generate; +end generate; +chk_dir_parity1: for i in dir_parity_in'range generate +begin + gen_dir_parity_out1(i) <= xor_reduce( ext_dir_dataout1(i*8 to i*8+7) ); +end generate; +dir_parity_err_byte1 <= iu2_dir_dataout_1_par_l2 xor gen_dir_parity_out1; +dir_parity_err_way(1) <= or_reduce(dir_parity_err_byte1) and iu2_dir_rd_val_l2(1) and (iu2_valid or iu2_inval_l2 or iu2_spr_idir_read_l2); +calc_ext_dir_dataout2: for i in ext_dir_datain'range generate +begin + R0:if(i < 52-REAL_IFAR'left+1) generate begin ext_dir_dataout2(i) <= iu2_dir_dataout_2_noncmp(REAL_IFAR'left+i); +end generate; +R1:if(i >= 52-REAL_IFAR'left+1) generate +begin ext_dir_dataout2(i) <= '0'; +end generate; +end generate; +chk_dir_parity2: for i in dir_parity_in'range generate +begin + gen_dir_parity_out2(i) <= xor_reduce( ext_dir_dataout2(i*8 to i*8+7) ); +end generate; +dir_parity_err_byte2 <= iu2_dir_dataout_2_par_l2 xor gen_dir_parity_out2; +dir_parity_err_way(2) <= or_reduce(dir_parity_err_byte2) and iu2_dir_rd_val_l2(2) and (iu2_valid or iu2_inval_l2 or iu2_spr_idir_read_l2); +calc_ext_dir_dataout3: for i in ext_dir_datain'range generate +begin + R0:if(i < 52-REAL_IFAR'left+1) generate begin ext_dir_dataout3(i) <= iu2_dir_dataout_3_noncmp(REAL_IFAR'left+i); +end generate; +R1:if(i >= 52-REAL_IFAR'left+1) generate +begin ext_dir_dataout3(i) <= '0'; +end generate; +end generate; +chk_dir_parity3: for i in dir_parity_in'range generate +begin + gen_dir_parity_out3(i) <= xor_reduce( ext_dir_dataout3(i*8 to i*8+7) ); +end generate; +dir_parity_err_byte3 <= iu2_dir_dataout_3_par_l2 xor gen_dir_parity_out3; +dir_parity_err_way(3) <= or_reduce(dir_parity_err_byte3) and iu2_dir_rd_val_l2(3) and (iu2_valid or iu2_inval_l2 or iu2_spr_idir_read_l2); +iu3_dir_parity_err_way_d <= dir_parity_err_way; +dir_parity_err <= or_reduce(dir_parity_err_way); +iu2_rd_parity_err <= or_reduce(dir_parity_err_way and iu2_rd_way_hit); +err_icachedir_parity_d <= dir_parity_err; +err_icachedir_parity: tri_direct_err_rpt + generic map (width => 1, expand_type => expand_type) + port map ( + vd => vdd, + gd => gnd, + err_in(0) => err_icachedir_parity_l2, + err_out(0) => iu_pc_err_icachedir_parity + ); +data_parity_out0 <= data_dataout_inj(144 to 144+data_parity_in'length-1); +chk_data_parity0: for i in data_parity_in'range generate +begin + gen_data_parity_out0(i) <= xor_reduce( data_dataout_inj(0+i*8 to 0+i*8+7) ); +end generate; +data_parity_err_byte0 <= data_parity_out0 xor gen_data_parity_out0; +iu3_data_parity_err_way_d(0) <= or_reduce(data_parity_err_byte0) and iu2_dir_rd_val_l2(0) and iu2_valid_l2; +data_parity_out1 <= data_dataout_inj(306 to 306+data_parity_in'length-1); +chk_data_parity1: for i in data_parity_in'range generate +begin + gen_data_parity_out1(i) <= xor_reduce( data_dataout_inj(162+i*8 to 162+i*8+7) ); +end generate; +data_parity_err_byte1 <= data_parity_out1 xor gen_data_parity_out1; +iu3_data_parity_err_way_d(1) <= or_reduce(data_parity_err_byte1) and iu2_dir_rd_val_l2(1) and iu2_valid_l2; +data_parity_out2 <= data_dataout_inj(468 to 468+data_parity_in'length-1); +chk_data_parity2: for i in data_parity_in'range generate +begin + gen_data_parity_out2(i) <= xor_reduce( data_dataout_inj(324+i*8 to 324+i*8+7) ); +end generate; +data_parity_err_byte2 <= data_parity_out2 xor gen_data_parity_out2; +iu3_data_parity_err_way_d(2) <= or_reduce(data_parity_err_byte2) and iu2_dir_rd_val_l2(2) and iu2_valid_l2; +data_parity_out3 <= data_dataout_inj(630 to 630+data_parity_in'length-1); +chk_data_parity3: for i in data_parity_in'range generate +begin + gen_data_parity_out3(i) <= xor_reduce( data_dataout_inj(486+i*8 to 486+i*8+7) ); +end generate; +data_parity_err_byte3 <= data_parity_out3 xor gen_data_parity_out3; +iu3_data_parity_err_way_d(3) <= or_reduce(data_parity_err_byte3) and iu2_dir_rd_val_l2(3) and iu2_valid_l2; +data_parity_err <= or_reduce(iu3_data_parity_err_way_l2); +err_icache_parity_d <= data_parity_err; +err_icache_parity: tri_direct_err_rpt + generic map (width => 1, expand_type => expand_type) + port map ( + vd => vdd, + gd => gnd, + err_in(0) => err_icache_parity_l2, + err_out(0) => iu_pc_err_icache_parity + ); +iu3_parity_needs_flush_d <= gate_and(iu2_valid and or_reduce(iu2_tid_l2 and not ics_icd_iu2_flush_tid) and not iu2_ci, iu2_rd_way_hit); +iu3_parity_needs_flush <= or_reduce(iu3_data_parity_err_way_l2 and iu3_parity_needs_flush_l2); +iu3_parity_flush_tid(0) <= iu3_tid_l2(0) and not ics_icd_all_flush_prev(0) and not iu3_erat_err_l2(0); +iu3_parity_flush_tid(1) <= iu3_tid_l2(1) and not ics_icd_all_flush_prev(1) and not iu3_erat_err_l2(0); +iu3_parity_flush_tid(2) <= iu3_tid_l2(2) and not ics_icd_all_flush_prev(2) and not iu3_erat_err_l2(0); +iu3_parity_flush_tid(3) <= iu3_tid_l2(3) and not ics_icd_all_flush_prev(3) and not iu3_erat_err_l2(0); +iu3_parity_flush <= (iu3_parity_needs_flush or iu3_rd_parity_err_l2 or iu3_multihit_flush_l2); +icd_ics_iu3_parity_flush <= gate_and(iu3_parity_flush, iu3_parity_flush_tid); +iu3_parity_tag_d <= iu2_ifar_eff_l2(52 to 57); +iu3_parity_act <= spr_ic_clockgate_dis or + (iu2_valid or iu2_inval_l2 or iu2_spr_idir_read_l2) or or_reduce(iu3_any_parity_err_way); +dir_row0_lru_d <= dir_row0_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "000000")) = '1' + else dir_row0_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "000000") = '1' + else dir_row0_lru_l2; +dir_row1_lru_d <= dir_row1_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "000001")) = '1' + else dir_row1_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "000001") = '1' + else dir_row1_lru_l2; +dir_row2_lru_d <= dir_row2_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "000010")) = '1' + else dir_row2_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "000010") = '1' + else dir_row2_lru_l2; +dir_row3_lru_d <= dir_row3_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "000011")) = '1' + else dir_row3_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "000011") = '1' + else dir_row3_lru_l2; +dir_row4_lru_d <= dir_row4_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "000100")) = '1' + else dir_row4_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "000100") = '1' + else dir_row4_lru_l2; +dir_row5_lru_d <= dir_row5_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "000101")) = '1' + else dir_row5_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "000101") = '1' + else dir_row5_lru_l2; +dir_row6_lru_d <= dir_row6_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "000110")) = '1' + else dir_row6_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "000110") = '1' + else dir_row6_lru_l2; +dir_row7_lru_d <= dir_row7_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "000111")) = '1' + else dir_row7_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "000111") = '1' + else dir_row7_lru_l2; +dir_row8_lru_d <= dir_row8_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "001000")) = '1' + else dir_row8_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "001000") = '1' + else dir_row8_lru_l2; +dir_row9_lru_d <= dir_row9_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "001001")) = '1' + else dir_row9_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "001001") = '1' + else dir_row9_lru_l2; +dir_row10_lru_d <= dir_row10_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "001010")) = '1' + else dir_row10_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "001010") = '1' + else dir_row10_lru_l2; +dir_row11_lru_d <= dir_row11_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "001011")) = '1' + else dir_row11_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "001011") = '1' + else dir_row11_lru_l2; +dir_row12_lru_d <= dir_row12_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "001100")) = '1' + else dir_row12_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "001100") = '1' + else dir_row12_lru_l2; +dir_row13_lru_d <= dir_row13_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "001101")) = '1' + else dir_row13_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "001101") = '1' + else dir_row13_lru_l2; +dir_row14_lru_d <= dir_row14_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "001110")) = '1' + else dir_row14_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "001110") = '1' + else dir_row14_lru_l2; +dir_row15_lru_d <= dir_row15_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "001111")) = '1' + else dir_row15_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "001111") = '1' + else dir_row15_lru_l2; +dir_row16_lru_d <= dir_row16_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "010000")) = '1' + else dir_row16_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "010000") = '1' + else dir_row16_lru_l2; +dir_row17_lru_d <= dir_row17_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "010001")) = '1' + else dir_row17_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "010001") = '1' + else dir_row17_lru_l2; +dir_row18_lru_d <= dir_row18_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "010010")) = '1' + else dir_row18_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "010010") = '1' + else dir_row18_lru_l2; +dir_row19_lru_d <= dir_row19_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "010011")) = '1' + else dir_row19_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "010011") = '1' + else dir_row19_lru_l2; +dir_row20_lru_d <= dir_row20_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "010100")) = '1' + else dir_row20_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "010100") = '1' + else dir_row20_lru_l2; +dir_row21_lru_d <= dir_row21_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "010101")) = '1' + else dir_row21_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "010101") = '1' + else dir_row21_lru_l2; +dir_row22_lru_d <= dir_row22_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "010110")) = '1' + else dir_row22_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "010110") = '1' + else dir_row22_lru_l2; +dir_row23_lru_d <= dir_row23_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "010111")) = '1' + else dir_row23_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "010111") = '1' + else dir_row23_lru_l2; +dir_row24_lru_d <= dir_row24_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "011000")) = '1' + else dir_row24_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "011000") = '1' + else dir_row24_lru_l2; +dir_row25_lru_d <= dir_row25_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "011001")) = '1' + else dir_row25_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "011001") = '1' + else dir_row25_lru_l2; +dir_row26_lru_d <= dir_row26_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "011010")) = '1' + else dir_row26_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "011010") = '1' + else dir_row26_lru_l2; +dir_row27_lru_d <= dir_row27_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "011011")) = '1' + else dir_row27_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "011011") = '1' + else dir_row27_lru_l2; +dir_row28_lru_d <= dir_row28_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "011100")) = '1' + else dir_row28_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "011100") = '1' + else dir_row28_lru_l2; +dir_row29_lru_d <= dir_row29_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "011101")) = '1' + else dir_row29_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "011101") = '1' + else dir_row29_lru_l2; +dir_row30_lru_d <= dir_row30_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "011110")) = '1' + else dir_row30_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "011110") = '1' + else dir_row30_lru_l2; +dir_row31_lru_d <= dir_row31_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "011111")) = '1' + else dir_row31_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "011111") = '1' + else dir_row31_lru_l2; +dir_row32_lru_d <= dir_row32_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "100000")) = '1' + else dir_row32_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "100000") = '1' + else dir_row32_lru_l2; +dir_row33_lru_d <= dir_row33_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "100001")) = '1' + else dir_row33_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "100001") = '1' + else dir_row33_lru_l2; +dir_row34_lru_d <= dir_row34_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "100010")) = '1' + else dir_row34_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "100010") = '1' + else dir_row34_lru_l2; +dir_row35_lru_d <= dir_row35_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "100011")) = '1' + else dir_row35_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "100011") = '1' + else dir_row35_lru_l2; +dir_row36_lru_d <= dir_row36_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "100100")) = '1' + else dir_row36_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "100100") = '1' + else dir_row36_lru_l2; +dir_row37_lru_d <= dir_row37_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "100101")) = '1' + else dir_row37_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "100101") = '1' + else dir_row37_lru_l2; +dir_row38_lru_d <= dir_row38_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "100110")) = '1' + else dir_row38_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "100110") = '1' + else dir_row38_lru_l2; +dir_row39_lru_d <= dir_row39_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "100111")) = '1' + else dir_row39_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "100111") = '1' + else dir_row39_lru_l2; +dir_row40_lru_d <= dir_row40_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "101000")) = '1' + else dir_row40_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "101000") = '1' + else dir_row40_lru_l2; +dir_row41_lru_d <= dir_row41_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "101001")) = '1' + else dir_row41_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "101001") = '1' + else dir_row41_lru_l2; +dir_row42_lru_d <= dir_row42_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "101010")) = '1' + else dir_row42_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "101010") = '1' + else dir_row42_lru_l2; +dir_row43_lru_d <= dir_row43_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "101011")) = '1' + else dir_row43_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "101011") = '1' + else dir_row43_lru_l2; +dir_row44_lru_d <= dir_row44_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "101100")) = '1' + else dir_row44_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "101100") = '1' + else dir_row44_lru_l2; +dir_row45_lru_d <= dir_row45_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "101101")) = '1' + else dir_row45_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "101101") = '1' + else dir_row45_lru_l2; +dir_row46_lru_d <= dir_row46_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "101110")) = '1' + else dir_row46_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "101110") = '1' + else dir_row46_lru_l2; +dir_row47_lru_d <= dir_row47_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "101111")) = '1' + else dir_row47_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "101111") = '1' + else dir_row47_lru_l2; +dir_row48_lru_d <= dir_row48_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "110000")) = '1' + else dir_row48_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "110000") = '1' + else dir_row48_lru_l2; +dir_row49_lru_d <= dir_row49_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "110001")) = '1' + else dir_row49_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "110001") = '1' + else dir_row49_lru_l2; +dir_row50_lru_d <= dir_row50_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "110010")) = '1' + else dir_row50_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "110010") = '1' + else dir_row50_lru_l2; +dir_row51_lru_d <= dir_row51_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "110011")) = '1' + else dir_row51_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "110011") = '1' + else dir_row51_lru_l2; +dir_row52_lru_d <= dir_row52_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "110100")) = '1' + else dir_row52_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "110100") = '1' + else dir_row52_lru_l2; +dir_row53_lru_d <= dir_row53_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "110101")) = '1' + else dir_row53_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "110101") = '1' + else dir_row53_lru_l2; +dir_row54_lru_d <= dir_row54_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "110110")) = '1' + else dir_row54_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "110110") = '1' + else dir_row54_lru_l2; +dir_row55_lru_d <= dir_row55_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "110111")) = '1' + else dir_row55_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "110111") = '1' + else dir_row55_lru_l2; +dir_row56_lru_d <= dir_row56_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "111000")) = '1' + else dir_row56_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "111000") = '1' + else dir_row56_lru_l2; +dir_row57_lru_d <= dir_row57_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "111001")) = '1' + else dir_row57_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "111001") = '1' + else dir_row57_lru_l2; +dir_row58_lru_d <= dir_row58_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "111010")) = '1' + else dir_row58_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "111010") = '1' + else dir_row58_lru_l2; +dir_row59_lru_d <= dir_row59_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "111011")) = '1' + else dir_row59_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "111011") = '1' + else dir_row59_lru_l2; +dir_row60_lru_d <= dir_row60_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "111100")) = '1' + else dir_row60_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "111100") = '1' + else dir_row60_lru_l2; +dir_row61_lru_d <= dir_row61_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "111101")) = '1' + else dir_row61_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "111101") = '1' + else dir_row61_lru_l2; +dir_row62_lru_d <= dir_row62_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "111110")) = '1' + else dir_row62_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "111110") = '1' + else dir_row62_lru_l2; +dir_row63_lru_d <= dir_row63_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "111111")) = '1' + else dir_row63_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "111111") = '1' + else dir_row63_lru_l2; +dir_row_lru_even_act <= (icm_icd_lru_write and lru_write_cacheline(5) = '0') or + (iu2_valid_l2 and iu2_ifar_eff_cacheline(5) = '0'); +dir_row_lru_odd_act <= (icm_icd_lru_write and lru_write_cacheline(5) = '1') or + (iu2_valid_l2 and iu2_ifar_eff_cacheline(5) = '1'); +iu2_erat_err_lite <= ierat_iu_iu2_miss or ierat_iu_iu2_multihit or ierat_iu_iu2_isi; +iu2_lru_rd_update <= iu2_valid and not iu2_erat_err_lite and or_reduce(iu2_rd_way_hit(0 to 3)); +dir_row0_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row0_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row0_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row0_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row0_lru_l2(1) & '0')); +dir_row1_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row1_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row1_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row1_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row1_lru_l2(1) & '0')); +dir_row2_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row2_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row2_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row2_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row2_lru_l2(1) & '0')); +dir_row3_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row3_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row3_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row3_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row3_lru_l2(1) & '0')); +dir_row4_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row4_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row4_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row4_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row4_lru_l2(1) & '0')); +dir_row5_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row5_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row5_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row5_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row5_lru_l2(1) & '0')); +dir_row6_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row6_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row6_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row6_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row6_lru_l2(1) & '0')); +dir_row7_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row7_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row7_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row7_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row7_lru_l2(1) & '0')); +dir_row8_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row8_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row8_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row8_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row8_lru_l2(1) & '0')); +dir_row9_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row9_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row9_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row9_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row9_lru_l2(1) & '0')); +dir_row10_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row10_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row10_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row10_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row10_lru_l2(1) & '0')); +dir_row11_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row11_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row11_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row11_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row11_lru_l2(1) & '0')); +dir_row12_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row12_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row12_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row12_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row12_lru_l2(1) & '0')); +dir_row13_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row13_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row13_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row13_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row13_lru_l2(1) & '0')); +dir_row14_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row14_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row14_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row14_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row14_lru_l2(1) & '0')); +dir_row15_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row15_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row15_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row15_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row15_lru_l2(1) & '0')); +dir_row16_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row16_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row16_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row16_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row16_lru_l2(1) & '0')); +dir_row17_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row17_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row17_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row17_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row17_lru_l2(1) & '0')); +dir_row18_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row18_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row18_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row18_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row18_lru_l2(1) & '0')); +dir_row19_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row19_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row19_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row19_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row19_lru_l2(1) & '0')); +dir_row20_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row20_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row20_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row20_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row20_lru_l2(1) & '0')); +dir_row21_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row21_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row21_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row21_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row21_lru_l2(1) & '0')); +dir_row22_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row22_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row22_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row22_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row22_lru_l2(1) & '0')); +dir_row23_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row23_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row23_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row23_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row23_lru_l2(1) & '0')); +dir_row24_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row24_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row24_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row24_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row24_lru_l2(1) & '0')); +dir_row25_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row25_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row25_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row25_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row25_lru_l2(1) & '0')); +dir_row26_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row26_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row26_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row26_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row26_lru_l2(1) & '0')); +dir_row27_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row27_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row27_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row27_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row27_lru_l2(1) & '0')); +dir_row28_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row28_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row28_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row28_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row28_lru_l2(1) & '0')); +dir_row29_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row29_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row29_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row29_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row29_lru_l2(1) & '0')); +dir_row30_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row30_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row30_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row30_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row30_lru_l2(1) & '0')); +dir_row31_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row31_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row31_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row31_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row31_lru_l2(1) & '0')); +dir_row32_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row32_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row32_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row32_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row32_lru_l2(1) & '0')); +dir_row33_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row33_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row33_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row33_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row33_lru_l2(1) & '0')); +dir_row34_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row34_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row34_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row34_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row34_lru_l2(1) & '0')); +dir_row35_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row35_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row35_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row35_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row35_lru_l2(1) & '0')); +dir_row36_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row36_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row36_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row36_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row36_lru_l2(1) & '0')); +dir_row37_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row37_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row37_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row37_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row37_lru_l2(1) & '0')); +dir_row38_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row38_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row38_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row38_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row38_lru_l2(1) & '0')); +dir_row39_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row39_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row39_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row39_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row39_lru_l2(1) & '0')); +dir_row40_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row40_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row40_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row40_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row40_lru_l2(1) & '0')); +dir_row41_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row41_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row41_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row41_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row41_lru_l2(1) & '0')); +dir_row42_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row42_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row42_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row42_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row42_lru_l2(1) & '0')); +dir_row43_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row43_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row43_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row43_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row43_lru_l2(1) & '0')); +dir_row44_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row44_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row44_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row44_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row44_lru_l2(1) & '0')); +dir_row45_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row45_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row45_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row45_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row45_lru_l2(1) & '0')); +dir_row46_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row46_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row46_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row46_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row46_lru_l2(1) & '0')); +dir_row47_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row47_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row47_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row47_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row47_lru_l2(1) & '0')); +dir_row48_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row48_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row48_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row48_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row48_lru_l2(1) & '0')); +dir_row49_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row49_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row49_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row49_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row49_lru_l2(1) & '0')); +dir_row50_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row50_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row50_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row50_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row50_lru_l2(1) & '0')); +dir_row51_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row51_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row51_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row51_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row51_lru_l2(1) & '0')); +dir_row52_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row52_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row52_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row52_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row52_lru_l2(1) & '0')); +dir_row53_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row53_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row53_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row53_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row53_lru_l2(1) & '0')); +dir_row54_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row54_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row54_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row54_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row54_lru_l2(1) & '0')); +dir_row55_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row55_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row55_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row55_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row55_lru_l2(1) & '0')); +dir_row56_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row56_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row56_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row56_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row56_lru_l2(1) & '0')); +dir_row57_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row57_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row57_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row57_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row57_lru_l2(1) & '0')); +dir_row58_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row58_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row58_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row58_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row58_lru_l2(1) & '0')); +dir_row59_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row59_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row59_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row59_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row59_lru_l2(1) & '0')); +dir_row60_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row60_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row60_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row60_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row60_lru_l2(1) & '0')); +dir_row61_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row61_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row61_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row61_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row61_lru_l2(1) & '0')); +dir_row62_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row62_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row62_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row62_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row62_lru_l2(1) & '0')); +dir_row63_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row63_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row63_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row63_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row63_lru_l2(1) & '0')); +dir_row0_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row0_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row0_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row0_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row0_lru_l2(1) & '0')); +dir_row1_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row1_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row1_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row1_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row1_lru_l2(1) & '0')); +dir_row2_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row2_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row2_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row2_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row2_lru_l2(1) & '0')); +dir_row3_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row3_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row3_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row3_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row3_lru_l2(1) & '0')); +dir_row4_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row4_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row4_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row4_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row4_lru_l2(1) & '0')); +dir_row5_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row5_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row5_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row5_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row5_lru_l2(1) & '0')); +dir_row6_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row6_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row6_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row6_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row6_lru_l2(1) & '0')); +dir_row7_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row7_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row7_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row7_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row7_lru_l2(1) & '0')); +dir_row8_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row8_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row8_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row8_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row8_lru_l2(1) & '0')); +dir_row9_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row9_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row9_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row9_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row9_lru_l2(1) & '0')); +dir_row10_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row10_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row10_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row10_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row10_lru_l2(1) & '0')); +dir_row11_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row11_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row11_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row11_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row11_lru_l2(1) & '0')); +dir_row12_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row12_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row12_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row12_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row12_lru_l2(1) & '0')); +dir_row13_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row13_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row13_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row13_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row13_lru_l2(1) & '0')); +dir_row14_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row14_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row14_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row14_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row14_lru_l2(1) & '0')); +dir_row15_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row15_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row15_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row15_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row15_lru_l2(1) & '0')); +dir_row16_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row16_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row16_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row16_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row16_lru_l2(1) & '0')); +dir_row17_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row17_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row17_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row17_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row17_lru_l2(1) & '0')); +dir_row18_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row18_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row18_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row18_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row18_lru_l2(1) & '0')); +dir_row19_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row19_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row19_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row19_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row19_lru_l2(1) & '0')); +dir_row20_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row20_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row20_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row20_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row20_lru_l2(1) & '0')); +dir_row21_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row21_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row21_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row21_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row21_lru_l2(1) & '0')); +dir_row22_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row22_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row22_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row22_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row22_lru_l2(1) & '0')); +dir_row23_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row23_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row23_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row23_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row23_lru_l2(1) & '0')); +dir_row24_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row24_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row24_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row24_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row24_lru_l2(1) & '0')); +dir_row25_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row25_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row25_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row25_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row25_lru_l2(1) & '0')); +dir_row26_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row26_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row26_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row26_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row26_lru_l2(1) & '0')); +dir_row27_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row27_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row27_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row27_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row27_lru_l2(1) & '0')); +dir_row28_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row28_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row28_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row28_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row28_lru_l2(1) & '0')); +dir_row29_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row29_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row29_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row29_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row29_lru_l2(1) & '0')); +dir_row30_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row30_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row30_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row30_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row30_lru_l2(1) & '0')); +dir_row31_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row31_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row31_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row31_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row31_lru_l2(1) & '0')); +dir_row32_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row32_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row32_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row32_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row32_lru_l2(1) & '0')); +dir_row33_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row33_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row33_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row33_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row33_lru_l2(1) & '0')); +dir_row34_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row34_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row34_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row34_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row34_lru_l2(1) & '0')); +dir_row35_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row35_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row35_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row35_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row35_lru_l2(1) & '0')); +dir_row36_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row36_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row36_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row36_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row36_lru_l2(1) & '0')); +dir_row37_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row37_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row37_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row37_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row37_lru_l2(1) & '0')); +dir_row38_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row38_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row38_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row38_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row38_lru_l2(1) & '0')); +dir_row39_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row39_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row39_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row39_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row39_lru_l2(1) & '0')); +dir_row40_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row40_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row40_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row40_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row40_lru_l2(1) & '0')); +dir_row41_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row41_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row41_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row41_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row41_lru_l2(1) & '0')); +dir_row42_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row42_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row42_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row42_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row42_lru_l2(1) & '0')); +dir_row43_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row43_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row43_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row43_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row43_lru_l2(1) & '0')); +dir_row44_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row44_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row44_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row44_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row44_lru_l2(1) & '0')); +dir_row45_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row45_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row45_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row45_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row45_lru_l2(1) & '0')); +dir_row46_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row46_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row46_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row46_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row46_lru_l2(1) & '0')); +dir_row47_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row47_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row47_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row47_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row47_lru_l2(1) & '0')); +dir_row48_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row48_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row48_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row48_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row48_lru_l2(1) & '0')); +dir_row49_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row49_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row49_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row49_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row49_lru_l2(1) & '0')); +dir_row50_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row50_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row50_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row50_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row50_lru_l2(1) & '0')); +dir_row51_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row51_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row51_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row51_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row51_lru_l2(1) & '0')); +dir_row52_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row52_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row52_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row52_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row52_lru_l2(1) & '0')); +dir_row53_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row53_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row53_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row53_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row53_lru_l2(1) & '0')); +dir_row54_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row54_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row54_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row54_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row54_lru_l2(1) & '0')); +dir_row55_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row55_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row55_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row55_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row55_lru_l2(1) & '0')); +dir_row56_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row56_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row56_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row56_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row56_lru_l2(1) & '0')); +dir_row57_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row57_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row57_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row57_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row57_lru_l2(1) & '0')); +dir_row58_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row58_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row58_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row58_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row58_lru_l2(1) & '0')); +dir_row59_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row59_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row59_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row59_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row59_lru_l2(1) & '0')); +dir_row60_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row60_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row60_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row60_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row60_lru_l2(1) & '0')); +dir_row61_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row61_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row61_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row61_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row61_lru_l2(1) & '0')); +dir_row62_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row62_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row62_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row62_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row62_lru_l2(1) & '0')); +dir_row63_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row63_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row63_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row63_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row63_lru_l2(1) & '0')); +iu2_ifar_eff_cacheline <= iu2_ifar_eff_l2(52 to 56) & + (iu2_ifar_eff_l2(57) and not (spr_ic_cls_l2 and not iu2_spr_idir_read_l2)); +iu3_parity_tag_cacheline <= iu3_parity_tag_l2(52 to 56) & (iu3_parity_tag_l2(57) and not spr_ic_cls_l2); +reload_cacheline <= icm_icd_reload_addr(52 to 56) & (icm_icd_reload_addr(57) and not spr_ic_cls_l2); +ecc_inval_cacheline <= icm_icd_ecc_addr(52 to 56) & (icm_icd_ecc_addr(57) and not spr_ic_cls_l2); +lru_write_cacheline <= icm_icd_lru_write_addr(52 to 56) & (icm_icd_lru_write_addr(57) and not spr_ic_cls_l2); +iu3_any_parity_err_way <= iu3_dir_parity_err_way_l2 or iu3_multihit_err_way_l2 or iu3_data_parity_err_way_l2; +dir_row0_val_d_part1 <= + ((dir_row0_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "000000"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "000000"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "000000"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "000000"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row0_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "000000"), dir_row0_val_l2); +dir_row0_val_d_part2_b <= not(dir_row0_val_d_part2a and iu2_rd_way_tag_hit); +dir_row0_val_d <= dir_row0_val_d_part1 and dir_row0_val_d_part2_b; +dir_row1_val_d_part1 <= + ((dir_row1_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "000001"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "000001"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "000001"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "000001"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row1_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "000001"), dir_row1_val_l2); +dir_row1_val_d_part2_b <= not(dir_row1_val_d_part2a and iu2_rd_way_tag_hit); +dir_row1_val_d <= dir_row1_val_d_part1 and dir_row1_val_d_part2_b; +dir_row2_val_d_part1 <= + ((dir_row2_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "000010"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "000010"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "000010"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "000010"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row2_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "000010"), dir_row2_val_l2); +dir_row2_val_d_part2_b <= not(dir_row2_val_d_part2a and iu2_rd_way_tag_hit); +dir_row2_val_d <= dir_row2_val_d_part1 and dir_row2_val_d_part2_b; +dir_row3_val_d_part1 <= + ((dir_row3_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "000011"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "000011"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "000011"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "000011"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row3_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "000011"), dir_row3_val_l2); +dir_row3_val_d_part2_b <= not(dir_row3_val_d_part2a and iu2_rd_way_tag_hit); +dir_row3_val_d <= dir_row3_val_d_part1 and dir_row3_val_d_part2_b; +dir_row4_val_d_part1 <= + ((dir_row4_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "000100"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "000100"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "000100"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "000100"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row4_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "000100"), dir_row4_val_l2); +dir_row4_val_d_part2_b <= not(dir_row4_val_d_part2a and iu2_rd_way_tag_hit); +dir_row4_val_d <= dir_row4_val_d_part1 and dir_row4_val_d_part2_b; +dir_row5_val_d_part1 <= + ((dir_row5_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "000101"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "000101"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "000101"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "000101"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row5_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "000101"), dir_row5_val_l2); +dir_row5_val_d_part2_b <= not(dir_row5_val_d_part2a and iu2_rd_way_tag_hit); +dir_row5_val_d <= dir_row5_val_d_part1 and dir_row5_val_d_part2_b; +dir_row6_val_d_part1 <= + ((dir_row6_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "000110"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "000110"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "000110"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "000110"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row6_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "000110"), dir_row6_val_l2); +dir_row6_val_d_part2_b <= not(dir_row6_val_d_part2a and iu2_rd_way_tag_hit); +dir_row6_val_d <= dir_row6_val_d_part1 and dir_row6_val_d_part2_b; +dir_row7_val_d_part1 <= + ((dir_row7_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "000111"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "000111"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "000111"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "000111"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row7_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "000111"), dir_row7_val_l2); +dir_row7_val_d_part2_b <= not(dir_row7_val_d_part2a and iu2_rd_way_tag_hit); +dir_row7_val_d <= dir_row7_val_d_part1 and dir_row7_val_d_part2_b; +dir_row8_val_d_part1 <= + ((dir_row8_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "001000"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "001000"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "001000"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "001000"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row8_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "001000"), dir_row8_val_l2); +dir_row8_val_d_part2_b <= not(dir_row8_val_d_part2a and iu2_rd_way_tag_hit); +dir_row8_val_d <= dir_row8_val_d_part1 and dir_row8_val_d_part2_b; +dir_row9_val_d_part1 <= + ((dir_row9_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "001001"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "001001"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "001001"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "001001"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row9_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "001001"), dir_row9_val_l2); +dir_row9_val_d_part2_b <= not(dir_row9_val_d_part2a and iu2_rd_way_tag_hit); +dir_row9_val_d <= dir_row9_val_d_part1 and dir_row9_val_d_part2_b; +dir_row10_val_d_part1 <= + ((dir_row10_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "001010"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "001010"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "001010"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "001010"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row10_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "001010"), dir_row10_val_l2); +dir_row10_val_d_part2_b <= not(dir_row10_val_d_part2a and iu2_rd_way_tag_hit); +dir_row10_val_d <= dir_row10_val_d_part1 and dir_row10_val_d_part2_b; +dir_row11_val_d_part1 <= + ((dir_row11_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "001011"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "001011"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "001011"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "001011"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row11_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "001011"), dir_row11_val_l2); +dir_row11_val_d_part2_b <= not(dir_row11_val_d_part2a and iu2_rd_way_tag_hit); +dir_row11_val_d <= dir_row11_val_d_part1 and dir_row11_val_d_part2_b; +dir_row12_val_d_part1 <= + ((dir_row12_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "001100"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "001100"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "001100"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "001100"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row12_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "001100"), dir_row12_val_l2); +dir_row12_val_d_part2_b <= not(dir_row12_val_d_part2a and iu2_rd_way_tag_hit); +dir_row12_val_d <= dir_row12_val_d_part1 and dir_row12_val_d_part2_b; +dir_row13_val_d_part1 <= + ((dir_row13_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "001101"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "001101"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "001101"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "001101"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row13_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "001101"), dir_row13_val_l2); +dir_row13_val_d_part2_b <= not(dir_row13_val_d_part2a and iu2_rd_way_tag_hit); +dir_row13_val_d <= dir_row13_val_d_part1 and dir_row13_val_d_part2_b; +dir_row14_val_d_part1 <= + ((dir_row14_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "001110"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "001110"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "001110"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "001110"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row14_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "001110"), dir_row14_val_l2); +dir_row14_val_d_part2_b <= not(dir_row14_val_d_part2a and iu2_rd_way_tag_hit); +dir_row14_val_d <= dir_row14_val_d_part1 and dir_row14_val_d_part2_b; +dir_row15_val_d_part1 <= + ((dir_row15_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "001111"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "001111"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "001111"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "001111"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row15_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "001111"), dir_row15_val_l2); +dir_row15_val_d_part2_b <= not(dir_row15_val_d_part2a and iu2_rd_way_tag_hit); +dir_row15_val_d <= dir_row15_val_d_part1 and dir_row15_val_d_part2_b; +dir_row16_val_d_part1 <= + ((dir_row16_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "010000"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "010000"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "010000"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "010000"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row16_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "010000"), dir_row16_val_l2); +dir_row16_val_d_part2_b <= not(dir_row16_val_d_part2a and iu2_rd_way_tag_hit); +dir_row16_val_d <= dir_row16_val_d_part1 and dir_row16_val_d_part2_b; +dir_row17_val_d_part1 <= + ((dir_row17_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "010001"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "010001"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "010001"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "010001"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row17_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "010001"), dir_row17_val_l2); +dir_row17_val_d_part2_b <= not(dir_row17_val_d_part2a and iu2_rd_way_tag_hit); +dir_row17_val_d <= dir_row17_val_d_part1 and dir_row17_val_d_part2_b; +dir_row18_val_d_part1 <= + ((dir_row18_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "010010"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "010010"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "010010"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "010010"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row18_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "010010"), dir_row18_val_l2); +dir_row18_val_d_part2_b <= not(dir_row18_val_d_part2a and iu2_rd_way_tag_hit); +dir_row18_val_d <= dir_row18_val_d_part1 and dir_row18_val_d_part2_b; +dir_row19_val_d_part1 <= + ((dir_row19_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "010011"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "010011"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "010011"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "010011"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row19_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "010011"), dir_row19_val_l2); +dir_row19_val_d_part2_b <= not(dir_row19_val_d_part2a and iu2_rd_way_tag_hit); +dir_row19_val_d <= dir_row19_val_d_part1 and dir_row19_val_d_part2_b; +dir_row20_val_d_part1 <= + ((dir_row20_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "010100"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "010100"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "010100"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "010100"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row20_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "010100"), dir_row20_val_l2); +dir_row20_val_d_part2_b <= not(dir_row20_val_d_part2a and iu2_rd_way_tag_hit); +dir_row20_val_d <= dir_row20_val_d_part1 and dir_row20_val_d_part2_b; +dir_row21_val_d_part1 <= + ((dir_row21_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "010101"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "010101"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "010101"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "010101"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row21_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "010101"), dir_row21_val_l2); +dir_row21_val_d_part2_b <= not(dir_row21_val_d_part2a and iu2_rd_way_tag_hit); +dir_row21_val_d <= dir_row21_val_d_part1 and dir_row21_val_d_part2_b; +dir_row22_val_d_part1 <= + ((dir_row22_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "010110"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "010110"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "010110"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "010110"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row22_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "010110"), dir_row22_val_l2); +dir_row22_val_d_part2_b <= not(dir_row22_val_d_part2a and iu2_rd_way_tag_hit); +dir_row22_val_d <= dir_row22_val_d_part1 and dir_row22_val_d_part2_b; +dir_row23_val_d_part1 <= + ((dir_row23_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "010111"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "010111"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "010111"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "010111"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row23_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "010111"), dir_row23_val_l2); +dir_row23_val_d_part2_b <= not(dir_row23_val_d_part2a and iu2_rd_way_tag_hit); +dir_row23_val_d <= dir_row23_val_d_part1 and dir_row23_val_d_part2_b; +dir_row24_val_d_part1 <= + ((dir_row24_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "011000"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "011000"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "011000"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "011000"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row24_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "011000"), dir_row24_val_l2); +dir_row24_val_d_part2_b <= not(dir_row24_val_d_part2a and iu2_rd_way_tag_hit); +dir_row24_val_d <= dir_row24_val_d_part1 and dir_row24_val_d_part2_b; +dir_row25_val_d_part1 <= + ((dir_row25_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "011001"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "011001"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "011001"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "011001"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row25_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "011001"), dir_row25_val_l2); +dir_row25_val_d_part2_b <= not(dir_row25_val_d_part2a and iu2_rd_way_tag_hit); +dir_row25_val_d <= dir_row25_val_d_part1 and dir_row25_val_d_part2_b; +dir_row26_val_d_part1 <= + ((dir_row26_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "011010"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "011010"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "011010"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "011010"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row26_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "011010"), dir_row26_val_l2); +dir_row26_val_d_part2_b <= not(dir_row26_val_d_part2a and iu2_rd_way_tag_hit); +dir_row26_val_d <= dir_row26_val_d_part1 and dir_row26_val_d_part2_b; +dir_row27_val_d_part1 <= + ((dir_row27_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "011011"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "011011"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "011011"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "011011"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row27_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "011011"), dir_row27_val_l2); +dir_row27_val_d_part2_b <= not(dir_row27_val_d_part2a and iu2_rd_way_tag_hit); +dir_row27_val_d <= dir_row27_val_d_part1 and dir_row27_val_d_part2_b; +dir_row28_val_d_part1 <= + ((dir_row28_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "011100"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "011100"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "011100"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "011100"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row28_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "011100"), dir_row28_val_l2); +dir_row28_val_d_part2_b <= not(dir_row28_val_d_part2a and iu2_rd_way_tag_hit); +dir_row28_val_d <= dir_row28_val_d_part1 and dir_row28_val_d_part2_b; +dir_row29_val_d_part1 <= + ((dir_row29_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "011101"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "011101"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "011101"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "011101"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row29_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "011101"), dir_row29_val_l2); +dir_row29_val_d_part2_b <= not(dir_row29_val_d_part2a and iu2_rd_way_tag_hit); +dir_row29_val_d <= dir_row29_val_d_part1 and dir_row29_val_d_part2_b; +dir_row30_val_d_part1 <= + ((dir_row30_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "011110"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "011110"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "011110"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "011110"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row30_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "011110"), dir_row30_val_l2); +dir_row30_val_d_part2_b <= not(dir_row30_val_d_part2a and iu2_rd_way_tag_hit); +dir_row30_val_d <= dir_row30_val_d_part1 and dir_row30_val_d_part2_b; +dir_row31_val_d_part1 <= + ((dir_row31_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "011111"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "011111"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "011111"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "011111"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row31_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "011111"), dir_row31_val_l2); +dir_row31_val_d_part2_b <= not(dir_row31_val_d_part2a and iu2_rd_way_tag_hit); +dir_row31_val_d <= dir_row31_val_d_part1 and dir_row31_val_d_part2_b; +dir_row32_val_d_part1 <= + ((dir_row32_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "100000"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "100000"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "100000"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "100000"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row32_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "100000"), dir_row32_val_l2); +dir_row32_val_d_part2_b <= not(dir_row32_val_d_part2a and iu2_rd_way_tag_hit); +dir_row32_val_d <= dir_row32_val_d_part1 and dir_row32_val_d_part2_b; +dir_row33_val_d_part1 <= + ((dir_row33_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "100001"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "100001"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "100001"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "100001"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row33_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "100001"), dir_row33_val_l2); +dir_row33_val_d_part2_b <= not(dir_row33_val_d_part2a and iu2_rd_way_tag_hit); +dir_row33_val_d <= dir_row33_val_d_part1 and dir_row33_val_d_part2_b; +dir_row34_val_d_part1 <= + ((dir_row34_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "100010"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "100010"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "100010"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "100010"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row34_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "100010"), dir_row34_val_l2); +dir_row34_val_d_part2_b <= not(dir_row34_val_d_part2a and iu2_rd_way_tag_hit); +dir_row34_val_d <= dir_row34_val_d_part1 and dir_row34_val_d_part2_b; +dir_row35_val_d_part1 <= + ((dir_row35_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "100011"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "100011"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "100011"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "100011"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row35_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "100011"), dir_row35_val_l2); +dir_row35_val_d_part2_b <= not(dir_row35_val_d_part2a and iu2_rd_way_tag_hit); +dir_row35_val_d <= dir_row35_val_d_part1 and dir_row35_val_d_part2_b; +dir_row36_val_d_part1 <= + ((dir_row36_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "100100"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "100100"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "100100"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "100100"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row36_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "100100"), dir_row36_val_l2); +dir_row36_val_d_part2_b <= not(dir_row36_val_d_part2a and iu2_rd_way_tag_hit); +dir_row36_val_d <= dir_row36_val_d_part1 and dir_row36_val_d_part2_b; +dir_row37_val_d_part1 <= + ((dir_row37_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "100101"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "100101"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "100101"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "100101"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row37_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "100101"), dir_row37_val_l2); +dir_row37_val_d_part2_b <= not(dir_row37_val_d_part2a and iu2_rd_way_tag_hit); +dir_row37_val_d <= dir_row37_val_d_part1 and dir_row37_val_d_part2_b; +dir_row38_val_d_part1 <= + ((dir_row38_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "100110"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "100110"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "100110"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "100110"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row38_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "100110"), dir_row38_val_l2); +dir_row38_val_d_part2_b <= not(dir_row38_val_d_part2a and iu2_rd_way_tag_hit); +dir_row38_val_d <= dir_row38_val_d_part1 and dir_row38_val_d_part2_b; +dir_row39_val_d_part1 <= + ((dir_row39_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "100111"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "100111"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "100111"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "100111"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row39_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "100111"), dir_row39_val_l2); +dir_row39_val_d_part2_b <= not(dir_row39_val_d_part2a and iu2_rd_way_tag_hit); +dir_row39_val_d <= dir_row39_val_d_part1 and dir_row39_val_d_part2_b; +dir_row40_val_d_part1 <= + ((dir_row40_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "101000"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "101000"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "101000"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "101000"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row40_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "101000"), dir_row40_val_l2); +dir_row40_val_d_part2_b <= not(dir_row40_val_d_part2a and iu2_rd_way_tag_hit); +dir_row40_val_d <= dir_row40_val_d_part1 and dir_row40_val_d_part2_b; +dir_row41_val_d_part1 <= + ((dir_row41_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "101001"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "101001"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "101001"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "101001"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row41_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "101001"), dir_row41_val_l2); +dir_row41_val_d_part2_b <= not(dir_row41_val_d_part2a and iu2_rd_way_tag_hit); +dir_row41_val_d <= dir_row41_val_d_part1 and dir_row41_val_d_part2_b; +dir_row42_val_d_part1 <= + ((dir_row42_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "101010"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "101010"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "101010"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "101010"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row42_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "101010"), dir_row42_val_l2); +dir_row42_val_d_part2_b <= not(dir_row42_val_d_part2a and iu2_rd_way_tag_hit); +dir_row42_val_d <= dir_row42_val_d_part1 and dir_row42_val_d_part2_b; +dir_row43_val_d_part1 <= + ((dir_row43_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "101011"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "101011"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "101011"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "101011"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row43_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "101011"), dir_row43_val_l2); +dir_row43_val_d_part2_b <= not(dir_row43_val_d_part2a and iu2_rd_way_tag_hit); +dir_row43_val_d <= dir_row43_val_d_part1 and dir_row43_val_d_part2_b; +dir_row44_val_d_part1 <= + ((dir_row44_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "101100"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "101100"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "101100"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "101100"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row44_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "101100"), dir_row44_val_l2); +dir_row44_val_d_part2_b <= not(dir_row44_val_d_part2a and iu2_rd_way_tag_hit); +dir_row44_val_d <= dir_row44_val_d_part1 and dir_row44_val_d_part2_b; +dir_row45_val_d_part1 <= + ((dir_row45_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "101101"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "101101"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "101101"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "101101"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row45_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "101101"), dir_row45_val_l2); +dir_row45_val_d_part2_b <= not(dir_row45_val_d_part2a and iu2_rd_way_tag_hit); +dir_row45_val_d <= dir_row45_val_d_part1 and dir_row45_val_d_part2_b; +dir_row46_val_d_part1 <= + ((dir_row46_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "101110"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "101110"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "101110"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "101110"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row46_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "101110"), dir_row46_val_l2); +dir_row46_val_d_part2_b <= not(dir_row46_val_d_part2a and iu2_rd_way_tag_hit); +dir_row46_val_d <= dir_row46_val_d_part1 and dir_row46_val_d_part2_b; +dir_row47_val_d_part1 <= + ((dir_row47_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "101111"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "101111"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "101111"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "101111"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row47_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "101111"), dir_row47_val_l2); +dir_row47_val_d_part2_b <= not(dir_row47_val_d_part2a and iu2_rd_way_tag_hit); +dir_row47_val_d <= dir_row47_val_d_part1 and dir_row47_val_d_part2_b; +dir_row48_val_d_part1 <= + ((dir_row48_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "110000"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "110000"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "110000"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "110000"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row48_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "110000"), dir_row48_val_l2); +dir_row48_val_d_part2_b <= not(dir_row48_val_d_part2a and iu2_rd_way_tag_hit); +dir_row48_val_d <= dir_row48_val_d_part1 and dir_row48_val_d_part2_b; +dir_row49_val_d_part1 <= + ((dir_row49_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "110001"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "110001"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "110001"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "110001"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row49_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "110001"), dir_row49_val_l2); +dir_row49_val_d_part2_b <= not(dir_row49_val_d_part2a and iu2_rd_way_tag_hit); +dir_row49_val_d <= dir_row49_val_d_part1 and dir_row49_val_d_part2_b; +dir_row50_val_d_part1 <= + ((dir_row50_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "110010"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "110010"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "110010"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "110010"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row50_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "110010"), dir_row50_val_l2); +dir_row50_val_d_part2_b <= not(dir_row50_val_d_part2a and iu2_rd_way_tag_hit); +dir_row50_val_d <= dir_row50_val_d_part1 and dir_row50_val_d_part2_b; +dir_row51_val_d_part1 <= + ((dir_row51_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "110011"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "110011"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "110011"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "110011"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row51_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "110011"), dir_row51_val_l2); +dir_row51_val_d_part2_b <= not(dir_row51_val_d_part2a and iu2_rd_way_tag_hit); +dir_row51_val_d <= dir_row51_val_d_part1 and dir_row51_val_d_part2_b; +dir_row52_val_d_part1 <= + ((dir_row52_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "110100"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "110100"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "110100"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "110100"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row52_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "110100"), dir_row52_val_l2); +dir_row52_val_d_part2_b <= not(dir_row52_val_d_part2a and iu2_rd_way_tag_hit); +dir_row52_val_d <= dir_row52_val_d_part1 and dir_row52_val_d_part2_b; +dir_row53_val_d_part1 <= + ((dir_row53_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "110101"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "110101"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "110101"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "110101"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row53_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "110101"), dir_row53_val_l2); +dir_row53_val_d_part2_b <= not(dir_row53_val_d_part2a and iu2_rd_way_tag_hit); +dir_row53_val_d <= dir_row53_val_d_part1 and dir_row53_val_d_part2_b; +dir_row54_val_d_part1 <= + ((dir_row54_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "110110"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "110110"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "110110"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "110110"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row54_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "110110"), dir_row54_val_l2); +dir_row54_val_d_part2_b <= not(dir_row54_val_d_part2a and iu2_rd_way_tag_hit); +dir_row54_val_d <= dir_row54_val_d_part1 and dir_row54_val_d_part2_b; +dir_row55_val_d_part1 <= + ((dir_row55_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "110111"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "110111"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "110111"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "110111"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row55_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "110111"), dir_row55_val_l2); +dir_row55_val_d_part2_b <= not(dir_row55_val_d_part2a and iu2_rd_way_tag_hit); +dir_row55_val_d <= dir_row55_val_d_part1 and dir_row55_val_d_part2_b; +dir_row56_val_d_part1 <= + ((dir_row56_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "111000"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "111000"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "111000"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "111000"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row56_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "111000"), dir_row56_val_l2); +dir_row56_val_d_part2_b <= not(dir_row56_val_d_part2a and iu2_rd_way_tag_hit); +dir_row56_val_d <= dir_row56_val_d_part1 and dir_row56_val_d_part2_b; +dir_row57_val_d_part1 <= + ((dir_row57_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "111001"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "111001"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "111001"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "111001"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row57_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "111001"), dir_row57_val_l2); +dir_row57_val_d_part2_b <= not(dir_row57_val_d_part2a and iu2_rd_way_tag_hit); +dir_row57_val_d <= dir_row57_val_d_part1 and dir_row57_val_d_part2_b; +dir_row58_val_d_part1 <= + ((dir_row58_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "111010"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "111010"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "111010"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "111010"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row58_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "111010"), dir_row58_val_l2); +dir_row58_val_d_part2_b <= not(dir_row58_val_d_part2a and iu2_rd_way_tag_hit); +dir_row58_val_d <= dir_row58_val_d_part1 and dir_row58_val_d_part2_b; +dir_row59_val_d_part1 <= + ((dir_row59_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "111011"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "111011"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "111011"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "111011"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row59_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "111011"), dir_row59_val_l2); +dir_row59_val_d_part2_b <= not(dir_row59_val_d_part2a and iu2_rd_way_tag_hit); +dir_row59_val_d <= dir_row59_val_d_part1 and dir_row59_val_d_part2_b; +dir_row60_val_d_part1 <= + ((dir_row60_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "111100"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "111100"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "111100"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "111100"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row60_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "111100"), dir_row60_val_l2); +dir_row60_val_d_part2_b <= not(dir_row60_val_d_part2a and iu2_rd_way_tag_hit); +dir_row60_val_d <= dir_row60_val_d_part1 and dir_row60_val_d_part2_b; +dir_row61_val_d_part1 <= + ((dir_row61_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "111101"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "111101"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "111101"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "111101"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row61_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "111101"), dir_row61_val_l2); +dir_row61_val_d_part2_b <= not(dir_row61_val_d_part2a and iu2_rd_way_tag_hit); +dir_row61_val_d <= dir_row61_val_d_part1 and dir_row61_val_d_part2_b; +dir_row62_val_d_part1 <= + ((dir_row62_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "111110"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "111110"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "111110"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "111110"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row62_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "111110"), dir_row62_val_l2); +dir_row62_val_d_part2_b <= not(dir_row62_val_d_part2a and iu2_rd_way_tag_hit); +dir_row62_val_d <= dir_row62_val_d_part1 and dir_row62_val_d_part2_b; +dir_row63_val_d_part1 <= + ((dir_row63_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "111111"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "111111"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "111111"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "111111"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row63_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "111111"), dir_row63_val_l2); +dir_row63_val_d_part2_b <= not(dir_row63_val_d_part2a and iu2_rd_way_tag_hit); +dir_row63_val_d <= dir_row63_val_d_part1 and dir_row63_val_d_part2_b; +dir_row_val_even_act <= xu_iu_ici_l2 or + (or_reduce(iu3_any_parity_err_way) and (iu3_parity_tag_cacheline(5) = '0')) or + (icm_icd_any_reld_r2 and (reload_cacheline(5) = '0')) or + (icm_icd_any_checkecc and (ecc_inval_cacheline(5) = '0')) or + (iu2_inval_l2 and (iu2_ifar_eff_cacheline(5) = '0')); +dir_row_val_odd_act <= xu_iu_ici_l2 or + (or_reduce(iu3_any_parity_err_way) and (iu3_parity_tag_cacheline(5) = '1')) or + (icm_icd_any_reld_r2 and (reload_cacheline(5) = '1')) or + (icm_icd_any_checkecc and (ecc_inval_cacheline(5) = '1')) or + (iu2_inval_l2 and (iu2_ifar_eff_cacheline(5) = '1')); +lru_select <= icm_icd_lru_addr(52 to 56) & (icm_icd_lru_addr(57) and not spr_ic_cls_l2); +with lru_select select +return_lru <= dir_row0_lru_l2 when "000000", + dir_row1_lru_l2 when "000001", + dir_row2_lru_l2 when "000010", + dir_row3_lru_l2 when "000011", + dir_row4_lru_l2 when "000100", + dir_row5_lru_l2 when "000101", + dir_row6_lru_l2 when "000110", + dir_row7_lru_l2 when "000111", + dir_row8_lru_l2 when "001000", + dir_row9_lru_l2 when "001001", + dir_row10_lru_l2 when "001010", + dir_row11_lru_l2 when "001011", + dir_row12_lru_l2 when "001100", + dir_row13_lru_l2 when "001101", + dir_row14_lru_l2 when "001110", + dir_row15_lru_l2 when "001111", + dir_row16_lru_l2 when "010000", + dir_row17_lru_l2 when "010001", + dir_row18_lru_l2 when "010010", + dir_row19_lru_l2 when "010011", + dir_row20_lru_l2 when "010100", + dir_row21_lru_l2 when "010101", + dir_row22_lru_l2 when "010110", + dir_row23_lru_l2 when "010111", + dir_row24_lru_l2 when "011000", + dir_row25_lru_l2 when "011001", + dir_row26_lru_l2 when "011010", + dir_row27_lru_l2 when "011011", + dir_row28_lru_l2 when "011100", + dir_row29_lru_l2 when "011101", + dir_row30_lru_l2 when "011110", + dir_row31_lru_l2 when "011111", + dir_row32_lru_l2 when "100000", + dir_row33_lru_l2 when "100001", + dir_row34_lru_l2 when "100010", + dir_row35_lru_l2 when "100011", + dir_row36_lru_l2 when "100100", + dir_row37_lru_l2 when "100101", + dir_row38_lru_l2 when "100110", + dir_row39_lru_l2 when "100111", + dir_row40_lru_l2 when "101000", + dir_row41_lru_l2 when "101001", + dir_row42_lru_l2 when "101010", + dir_row43_lru_l2 when "101011", + dir_row44_lru_l2 when "101100", + dir_row45_lru_l2 when "101101", + dir_row46_lru_l2 when "101110", + dir_row47_lru_l2 when "101111", + dir_row48_lru_l2 when "110000", + dir_row49_lru_l2 when "110001", + dir_row50_lru_l2 when "110010", + dir_row51_lru_l2 when "110011", + dir_row52_lru_l2 when "110100", + dir_row53_lru_l2 when "110101", + dir_row54_lru_l2 when "110110", + dir_row55_lru_l2 when "110111", + dir_row56_lru_l2 when "111000", + dir_row57_lru_l2 when "111001", + dir_row58_lru_l2 when "111010", + dir_row59_lru_l2 when "111011", + dir_row60_lru_l2 when "111100", + dir_row61_lru_l2 when "111101", + dir_row62_lru_l2 when "111110", + dir_row63_lru_l2 when others; +icd_icm_row_lru <= return_lru; +with lru_select select +return_val <= dir_row0_val_l2 when "000000", + dir_row1_val_l2 when "000001", + dir_row2_val_l2 when "000010", + dir_row3_val_l2 when "000011", + dir_row4_val_l2 when "000100", + dir_row5_val_l2 when "000101", + dir_row6_val_l2 when "000110", + dir_row7_val_l2 when "000111", + dir_row8_val_l2 when "001000", + dir_row9_val_l2 when "001001", + dir_row10_val_l2 when "001010", + dir_row11_val_l2 when "001011", + dir_row12_val_l2 when "001100", + dir_row13_val_l2 when "001101", + dir_row14_val_l2 when "001110", + dir_row15_val_l2 when "001111", + dir_row16_val_l2 when "010000", + dir_row17_val_l2 when "010001", + dir_row18_val_l2 when "010010", + dir_row19_val_l2 when "010011", + dir_row20_val_l2 when "010100", + dir_row21_val_l2 when "010101", + dir_row22_val_l2 when "010110", + dir_row23_val_l2 when "010111", + dir_row24_val_l2 when "011000", + dir_row25_val_l2 when "011001", + dir_row26_val_l2 when "011010", + dir_row27_val_l2 when "011011", + dir_row28_val_l2 when "011100", + dir_row29_val_l2 when "011101", + dir_row30_val_l2 when "011110", + dir_row31_val_l2 when "011111", + dir_row32_val_l2 when "100000", + dir_row33_val_l2 when "100001", + dir_row34_val_l2 when "100010", + dir_row35_val_l2 when "100011", + dir_row36_val_l2 when "100100", + dir_row37_val_l2 when "100101", + dir_row38_val_l2 when "100110", + dir_row39_val_l2 when "100111", + dir_row40_val_l2 when "101000", + dir_row41_val_l2 when "101001", + dir_row42_val_l2 when "101010", + dir_row43_val_l2 when "101011", + dir_row44_val_l2 when "101100", + dir_row45_val_l2 when "101101", + dir_row46_val_l2 when "101110", + dir_row47_val_l2 when "101111", + dir_row48_val_l2 when "110000", + dir_row49_val_l2 when "110001", + dir_row50_val_l2 when "110010", + dir_row51_val_l2 when "110011", + dir_row52_val_l2 when "110100", + dir_row53_val_l2 when "110101", + dir_row54_val_l2 when "110110", + dir_row55_val_l2 when "110111", + dir_row56_val_l2 when "111000", + dir_row57_val_l2 when "111001", + dir_row58_val_l2 when "111010", + dir_row59_val_l2 when "111011", + dir_row60_val_l2 when "111100", + dir_row61_val_l2 when "111101", + dir_row62_val_l2 when "111110", + dir_row63_val_l2 when others; +icd_icm_row_val <= return_val; +mm_epn: for i in 0 to 51 generate +begin + R0:if(i < EFF_IFAR'left) generate begin iu_mm_ierat_epn(i) <= '0'; +end generate; +R1:if(i >= EFF_IFAR'left) generate +begin iu_mm_ierat_epn(i) <= iu2_ifar_eff_l2(i); +end generate; +end generate; +iu2_rd_miss <= iu2_valid and (iu2_dir_miss or iu2_ci); +iu3_rd_parity_err_d <= iu2_valid and iu2_rd_parity_err and or_reduce(iu2_tid_l2 and not ics_icd_iu2_flush_tid) and not iu2_ci; +iu3_rd_miss_d <= iu2_rd_miss and not or_reduce(iu2_tid_l2 and ics_icd_iu2_flush_tid); +iu3_rd_miss <= iu3_rd_miss_l2 and not iu3_erat_err_l2(0); +iu2_miss_flush_prev <= gate_and(iu3_rd_miss, iu3_tid_l2) and not ics_icd_all_flush_prev; +icd_icm_miss <= iu2_rd_miss; +icd_icm_tid <= iu2_tid_l2; +icd_icm_addr_real <= ierat_iu_iu2_rpn_noncmp(REAL_IFAR'left to 51) & iu2_ifar_eff_l2(52 to 61); +icd_icm_addr_eff <= iu2_ifar_eff_l2(EFF_IFAR'left to 51); +icd_icm_wimge <= ierat_iu_iu2_wimge; +icd_icm_userdef <= ierat_iu_iu2_u; +icd_icm_2ucode <= iu2_2ucode_l2; +icd_icm_2ucode_type <= iu2_2ucode_type_l2; +icd_icm_iu2_inval <= iu2_inval_l2; +icd_icm_ici <= xu_iu_ici_l2; +icd_icm_any_iu2_valid <= iu2_valid; +icd_ics_iu2_miss_flush_prev <= iu2_miss_flush_prev; +icd_ics_iu2_ifar_eff <= iu2_ifar_eff_l2; +icd_ics_iu2_2ucode <= iu2_2ucode_l2; +icd_ics_iu2_2ucode_type <= iu2_2ucode_type_l2; +load_iu2 <= or_reduce(icm_icd_load_tid); +iu3_act <= iu2_valid or load_iu2; +iu3_valid_next <= (iu2_valid and or_reduce(iu2_tid_l2 and not ics_icd_iu2_flush_tid)) or + or_reduce(icm_icd_load_tid); + WITH s3'(iu3_valid_next & iu3_ifar_d(60 to 61)) SELECT iu3_instr_valid_d(0 TO 3) <= "1111" when "100", + "1110" when "101", + "1100" when "110", + "1000" when "111", + "0000" when others; +with load_iu2 select +iu3_tid_d <= iu2_tid_l2 when '0', + icm_icd_load_tid when others; +with load_iu2 select +iu3_ifar_d <= iu2_ifar_eff_l2 when '0', + icm_icd_load_addr when others; +iu3_2ucode_d <= icm_icd_load_2ucode when load_iu2 = '1' + else iu2_2ucode_l2; +with load_iu2 select +iu3_2ucode_type_d <= iu2_2ucode_type_l2 when '0', + icm_icd_load_2ucode_type when others; +iu2_erat_err <= (ierat_iu_iu2_error(0) and not load_iu2) & + (ierat_iu_iu2_error(1) and not load_iu2) & + (ierat_iu_iu2_error(2) and not load_iu2); +iu3_erat_err_d <= iu2_erat_err; +iu2_data_dataout_0 <= iu2_data_dataout_l2( 0 to 143); +iu2_data_dataout_1 <= iu2_data_dataout_l2(162 to 305); +iu2_data_dataout_2 <= iu2_data_dataout_l2(324 to 467); +iu2_data_dataout_3 <= iu2_data_dataout_l2(486 to 629); +insmux : entity work.iuq_ic_insmux + generic map( expand_type=> expand_type) + port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + forcee => forcee, + sg_0 => pc_iu_sg_0, + thold_0_b => pc_iu_func_sl_thold_0_b, + scan_in => siv(iu3_instr_offset), + scan_out => sov(iu3_instr_offset), + inslat_act => iu3_act, + iu2_rd_way_hit_b => iu2_rd_way_hit_insmux_b, + load_iu2 => load_iu2, + icm_icd_reload_data => icm_icd_reload_data(0 to 143), + iu2_data_dataout_0 => iu2_data_dataout_0, + iu2_data_dataout_1 => iu2_data_dataout_1, + iu2_data_dataout_2 => iu2_data_dataout_2, + iu2_data_dataout_3 => iu2_data_dataout_3, + iu3_instr0_buf => iu3_instr0_buf, + iu3_instr1_buf => iu3_instr1_buf, + iu3_instr2_buf => iu3_instr2_buf, + iu3_instr3_buf => iu3_instr3_buf +); + WITH s3'(iu2_erat_err(0) & iu3_ifar_d(60 to 61)) SELECT iu2_ifar_dec(0 TO 3) <= "1000" when "000", + "0100" when "001", + "0010" when "010", + "0001" when "011", + "0000" when others; +iu3_ifar_dec_d <= iu2_ifar_dec; +uc_illegal <= iu3_0_instr_rot(32) or + (iu3_0_instr_rot(0 to 5) = "011000"); +ic_bp_iu3_val <= iu3_instr_valid_l2; +ic_bp_iu3_tid <= iu3_tid_l2; +ic_bp_iu3_ifar <= iu3_ifar_l2; +ic_bp_iu3_2ucode <= iu3_2ucode_l2 and not uc_illegal and not iu3_erat_err_l2(0); +ic_bp_iu3_2ucode_type <= iu3_2ucode_type_l2; +int_ic_bp_iu3_error(0) <= iu3_erat_err_l2(0); +int_ic_bp_iu3_error(1) <= iu3_erat_err_l2(1) or (icm_icd_iu3_ecc_err and not iu3_erat_err_l2(0)); +int_ic_bp_iu3_error(2) <= iu3_erat_err_l2(2); +ic_bp_iu3_error <= int_ic_bp_iu3_error; +icd_icm_iu3_erat_err <= iu3_erat_err_l2(0); +xnop <= "011010" & ZEROS(6 to 35); +iu3_0_instr_rot <= gate(xnop, iu3_erat_err_l2(0)) or + gate(iu3_instr0_buf, iu3_ifar_dec_l2(0)) or + gate(iu3_instr1_buf, iu3_ifar_dec_l2(1)) or + gate(iu3_instr2_buf, iu3_ifar_dec_l2(2)) or + gate(iu3_instr3_buf, iu3_ifar_dec_l2(3)) ; +iu3_1_instr_rot <= gate(xnop, iu3_erat_err_l2(0)) or + gate(iu3_instr1_buf, iu3_ifar_dec_l2(0)) or + gate(iu3_instr2_buf, iu3_ifar_dec_l2(1)) or + gate(iu3_instr3_buf, iu3_ifar_dec_l2(2)) ; +iu3_2_instr_rot <= gate(xnop, iu3_erat_err_l2(0)) or + gate(iu3_instr2_buf, iu3_ifar_dec_l2(0)) or + gate(iu3_instr3_buf, iu3_ifar_dec_l2(1)) ; +iu3_3_instr_rot <= xnop when iu3_erat_err_l2(0) = '1' + else iu3_instr3_buf; +ic_bp_iu3_0_instr <= iu3_0_instr_rot; +ic_bp_iu3_1_instr <= iu3_1_instr_rot; +ic_bp_iu3_2_instr <= iu3_2_instr_rot; +ic_bp_iu3_3_instr <= iu3_3_instr_rot; +int_ic_bp_iu3_flush <= icm_icd_iu3_ecc_fp_cancel or (iu3_parity_flush and not iu3_erat_err_l2(0)) or + iu3_rd_miss or or_reduce(iu3_tid_l2 and ics_icd_all_flush_prev); +ic_bp_iu3_flush <= int_ic_bp_iu3_flush; +icd_ics_iu3_ifar <= iu3_ifar_l2; +icd_ics_iu3_2ucode <= iu3_2ucode_l2; +icd_ics_iu3_2ucode_type <= iu3_2ucode_type_l2; +perf_event_t0_d(4) <= iu2_valid and iu2_tid_l2(0) and ierat_iu_iu2_miss; +perf_event_t1_d(4) <= iu2_valid and iu2_tid_l2(1) and ierat_iu_iu2_miss; +perf_event_t2_d(4) <= iu2_valid and iu2_tid_l2(2) and ierat_iu_iu2_miss; +perf_event_t3_d(4) <= iu2_valid and iu2_tid_l2(3) and ierat_iu_iu2_miss; +perf_event_t0_d(5) <= iu2_valid and iu2_tid_l2(0); +perf_event_t1_d(5) <= iu2_valid and iu2_tid_l2(1); +perf_event_t2_d(5) <= iu2_valid and iu2_tid_l2(2); +perf_event_t3_d(5) <= iu2_valid and iu2_tid_l2(3); + WITH s2'(iu2_ifar_eff_l2(60 to 61)) SELECT iu2_instr_count <= "100" when "00", + "011" when "01", + "010" when "10", + "001" when others; +perf_instr_count_t0_new(0 TO 2) <= std_ulogic_vector( + unsigned('0' & perf_instr_count_t0_l2) + unsigned(iu2_instr_count) ); +perf_instr_count_t0_d(0 TO 1) <= perf_instr_count_t0_new(1 to 2) when (iu2_valid and iu2_tid_l2(0)) = '1' + else perf_instr_count_t0_l2; +perf_event_t0_d(6) <= iu2_valid and iu2_tid_l2(0) and perf_instr_count_t0_new(0); +perf_instr_count_t1_new(0 TO 2) <= std_ulogic_vector( + unsigned('0' & perf_instr_count_t1_l2) + unsigned(iu2_instr_count) ); +perf_instr_count_t1_d(0 TO 1) <= perf_instr_count_t1_new(1 to 2) when (iu2_valid and iu2_tid_l2(1)) = '1' + else perf_instr_count_t1_l2; +perf_event_t1_d(6) <= iu2_valid and iu2_tid_l2(1) and perf_instr_count_t1_new(0); +perf_instr_count_t2_new(0 TO 2) <= std_ulogic_vector( + unsigned('0' & perf_instr_count_t2_l2) + unsigned(iu2_instr_count) ); +perf_instr_count_t2_d(0 TO 1) <= perf_instr_count_t2_new(1 to 2) when (iu2_valid and iu2_tid_l2(2)) = '1' + else perf_instr_count_t2_l2; +perf_event_t2_d(6) <= iu2_valid and iu2_tid_l2(2) and perf_instr_count_t2_new(0); +perf_instr_count_t3_new(0 TO 2) <= std_ulogic_vector( + unsigned('0' & perf_instr_count_t3_l2) + unsigned(iu2_instr_count) ); +perf_instr_count_t3_d(0 TO 1) <= perf_instr_count_t3_new(1 to 2) when (iu2_valid and iu2_tid_l2(3)) = '1' + else perf_instr_count_t3_l2; +perf_event_t3_d(6) <= iu2_valid and iu2_tid_l2(3) and perf_instr_count_t3_new(0); +perf_event_d(0) <= iu2_inval_l2; +perf_event_d(1) <= iu2_inval_l2 and or_reduce(iu2_rd_way_tag_hit and iu2_dir_rd_val_l2); +ic_perf_event_t0 <= perf_event_t0_l2; +ic_perf_event_t1 <= perf_event_t1_l2; +ic_perf_event_t2 <= perf_event_t2_l2; +ic_perf_event_t3 <= perf_event_t3_l2; +ic_perf_event <= perf_event_l2; +dbg_dir_write_d <= dir_write; +dbg_dir_rd_act_d <= dir_rd_act; +dbg_iu2_lru_rd_update_d <= iu2_lru_rd_update; +dbg_iu2_rd_way_tag_hit_d <= iu2_rd_way_tag_hit; +dbg_iu2_rd_way_hit_d <= iu2_rd_way_hit; +dbg_load_iu2_d <= load_iu2; +dir_dbg_data0(0 TO 10) <= data_datain(21 to 31); +dir_dbg_data0(11 TO 21) <= iu2_data_dataout_l2(21 to 31); +dir_dbg_data0(22) <= dbg_dir_write_l2; +dir_dbg_data0(23) <= data_write; +dir_dbg_data0(24 TO 31) <= icm_icd_reload_addr(52 to 59); +dir_dbg_data0(32 TO 35) <= icm_icd_reload_way(0 to 3); +dir_dbg_data0(36) <= dbg_dir_rd_act_l2; +dir_dbg_data0(37) <= icm_icd_dir_write_endian; +dir_dbg_data0(38 TO 43) <= iu2_ifar_eff_l2(52 to 57); +dir_dbg_data0(44 TO 47) <= iu2_dir_rd_val_l2; +dir_dbg_data0(48 TO 51) <= dbg_iu2_rd_way_tag_hit_l2; +dir_dbg_data0(52 TO 55) <= iu3_dir_parity_err_way_l2; +dir_dbg_data0(56 TO 59) <= iu3_multihit_err_way_l2; +dir_dbg_data0(60 TO 63) <= iu3_data_parity_err_way_l2; +dir_dbg_data0(64) <= xu_iu_ici_l2; +dir_dbg_data0(65) <= iu2_inval_l2; +dir_dbg_data0(66) <= icm_icd_dir_val; +dir_dbg_data0(67) <= icm_icd_dir_inval; +dir_dbg_data0(68) <= icm_icd_ecc_inval; +dir_dbg_data0(69) <= icm_icd_lru_write; +dir_dbg_data0(70) <= dbg_iu2_lru_rd_update_l2; +dir_dbg_data0(71 TO 73) <= iu2_spr_idir_lru_l2; +dir_dbg_data0(74 TO 79) <= icm_icd_lru_write_addr(52 to 57); +dir_dbg_data0(80 TO 83) <= icm_icd_lru_write_way; +dir_dbg_data0(84) <= perf_event_t0_d(5); +dir_dbg_data0(85) <= perf_event_t1_d(5); +dir_dbg_data0(86) <= perf_event_t2_d(5); +dir_dbg_data0(87) <= perf_event_t3_d(5); +dbg1: if (EFF_IFAR'left > 0 )generate +begin dir_dbg_data1(0 TO EFF_IFAR'left-1) <= (others => '0'); +end generate; +dir_dbg_data1(EFF_IFAR'left TO 61) <= iu3_ifar_l2; +dir_dbg_data1(62 TO 67) <= iu3_0_instr_rot(0 to 5); +dir_dbg_data1(68 TO 71) <= iu3_instr_valid_l2; +dir_dbg_data1(72 TO 75) <= iu3_tid_l2; +dir_dbg_data1(76) <= int_ic_bp_iu3_flush; +dir_dbg_data1(77 TO 79) <= int_ic_bp_iu3_error; +dir_dbg_data1(80 TO 83) <= ics_icd_all_flush_prev; +dir_dbg_data1(84) <= dbg_load_iu2_l2; +dir_dbg_data1(85) <= uc_illegal; +dir_dbg_data1(86) <= iu3_2ucode_l2; +dir_dbg_data1(87) <= iu3_2ucode_type_l2; +dir_dbg_data2(0) <= iu2_valid; +dir_dbg_data2(1 TO 3) <= iu3_erat_err_l2; +dir_dbg_data2(4 TO 7) <= iu2_tid_l2; +dir_dbg_data2(8 TO 11) <= dbg_iu2_rd_way_hit_l2; +dir_dbg_data2(12) <= iu2_ci; +dir_dbg_data2(13) <= iu2_endian; +dir_dbg_data2(14 TO 43) <= ierat_iu_iu2_rpn_noncmp; +dir_dbg_trigger0(0) <= iu1_valid_l2; +dir_dbg_trigger0(1) <= iu1_inval_l2; +dir_dbg_trigger0(2 TO 5) <= iu1_tid_l2; +dir_dbg_trigger0(6) <= iu3_rd_miss_l2; +dir_dbg_trigger0(7) <= iu3_instr_valid_l2(0); +dir_dbg_trigger1(0 TO 9) <= iu2_ifar_eff_l2(52 to 61); +dir_dbg_trigger1(10) <= iu2_valid_l2; +dir_dbg_trigger1(11) <= iu2_inval_l2; +iu1_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu1_valid_offset), + scout => sov(iu1_valid_offset), + din => iu1_valid_d, + dout => iu1_valid_l2); +iu1_tid_latch: tri_rlmreg_p + generic map (width => iu1_tid_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_rd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu1_tid_offset to iu1_tid_offset + iu1_tid_l2'length-1), + scout => sov(iu1_tid_offset to iu1_tid_offset + iu1_tid_l2'length-1), + din => iu1_tid_d, + dout => iu1_tid_l2); +iu1_ifar_latch: tri_rlmreg_p + generic map (width => iu1_ifar_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_rd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu1_ifar_offset to iu1_ifar_offset + iu1_ifar_l2'length-1), + scout => sov(iu1_ifar_offset to iu1_ifar_offset + iu1_ifar_l2'length-1), + din => iu1_ifar_d, + dout => iu1_ifar_l2); +iu1_inval_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu1_inval_offset), + scout => sov(iu1_inval_offset), + din => iu1_inval_d, + dout => iu1_inval_l2); +iu1_2ucode_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_rd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu1_2ucode_offset), + scout => sov(iu1_2ucode_offset), + din => iu1_2ucode_d, + dout => iu1_2ucode_l2); +iu1_2ucode_type_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_rd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu1_2ucode_type_offset), + scout => sov(iu1_2ucode_type_offset), + din => iu1_2ucode_type_d, + dout => iu1_2ucode_type_l2); +iu2_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu2_valid_offset), + scout => sov(iu2_valid_offset), + din => iu2_valid_d, + dout => iu2_valid_l2); +iu2_tid_latch: tri_rlmreg_p + generic map (width => iu2_tid_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu1_valid_l2, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu2_tid_offset to iu2_tid_offset + iu2_tid_l2'length-1), + scout => sov(iu2_tid_offset to iu2_tid_offset + iu2_tid_l2'length-1), + din => iu2_tid_d, + dout => iu2_tid_l2); +iu2_ifar_eff_latch: tri_rlmreg_p + generic map (width => 52-EFF_IFAR'left, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_dataout_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu2_ifar_eff_offset to iu2_ifar_eff_offset + 52-EFF_IFAR'left-1), + scout => sov(iu2_ifar_eff_offset to iu2_ifar_eff_offset + 52-EFF_IFAR'left-1), + din => iu2_ifar_eff_d(EFF_IFAR'left to 51), + dout => iu2_ifar_eff_l2(EFF_IFAR'left to 51)); +iu2_ifar_eff_slp_latch: tri_rlmreg_p + generic map (width => 10, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_dataout_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu2_ifar_eff_offset+52 to iu2_ifar_eff_offset + iu2_ifar_eff_l2'length-1), + scout => sov(iu2_ifar_eff_offset+52 to iu2_ifar_eff_offset + iu2_ifar_eff_l2'length-1), + din => iu2_ifar_eff_d(52 to 61), + dout => iu2_ifar_eff_l2(52 to 61)); +iu2_2ucode_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu1_valid_l2, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu2_2ucode_offset), + scout => sov(iu2_2ucode_offset), + din => iu2_2ucode_d, + dout => iu2_2ucode_l2); +iu2_2ucode_type_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu1_valid_l2, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu2_2ucode_type_offset), + scout => sov(iu2_2ucode_type_offset), + din => iu2_2ucode_type_d, + dout => iu2_2ucode_type_l2); +iu2_inval_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu2_inval_offset), + scout => sov(iu2_inval_offset), + din => iu2_inval_d, + dout => iu2_inval_l2); +iu2_dir_rd_val_latch: tri_rlmreg_p + generic map (width => iu2_dir_rd_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_dataout_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu2_dir_rd_val_offset to iu2_dir_rd_val_offset + iu2_dir_rd_val_l2'length-1), + scout => sov(iu2_dir_rd_val_offset to iu2_dir_rd_val_offset + iu2_dir_rd_val_l2'length-1), + din => iu2_dir_rd_val_d, + dout => iu2_dir_rd_val_l2); +iu2_dir_dataout_0_par_latch: tri_rlmreg_p + generic map (width => iu2_dir_dataout_0_par_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_dataout_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu2_dir_dataout_0_par_offset to iu2_dir_dataout_0_par_offset + iu2_dir_dataout_0_par_l2'length-1), + scout => sov(iu2_dir_dataout_0_par_offset to iu2_dir_dataout_0_par_offset + iu2_dir_dataout_0_par_l2'length-1), + din => iu2_dir_dataout_0_par_d, + dout => iu2_dir_dataout_0_par_l2); +iu2_dir_dataout_1_par_latch: tri_rlmreg_p + generic map (width => iu2_dir_dataout_1_par_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_dataout_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu2_dir_dataout_1_par_offset to iu2_dir_dataout_1_par_offset + iu2_dir_dataout_1_par_l2'length-1), + scout => sov(iu2_dir_dataout_1_par_offset to iu2_dir_dataout_1_par_offset + iu2_dir_dataout_1_par_l2'length-1), + din => iu2_dir_dataout_1_par_d, + dout => iu2_dir_dataout_1_par_l2); +iu2_dir_dataout_2_par_latch: tri_rlmreg_p + generic map (width => iu2_dir_dataout_2_par_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_dataout_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu2_dir_dataout_2_par_offset to iu2_dir_dataout_2_par_offset + iu2_dir_dataout_2_par_l2'length-1), + scout => sov(iu2_dir_dataout_2_par_offset to iu2_dir_dataout_2_par_offset + iu2_dir_dataout_2_par_l2'length-1), + din => iu2_dir_dataout_2_par_d, + dout => iu2_dir_dataout_2_par_l2); +iu2_dir_dataout_3_par_latch: tri_rlmreg_p + generic map (width => iu2_dir_dataout_3_par_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_dataout_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu2_dir_dataout_3_par_offset to iu2_dir_dataout_3_par_offset + iu2_dir_dataout_3_par_l2'length-1), + scout => sov(iu2_dir_dataout_3_par_offset to iu2_dir_dataout_3_par_offset + iu2_dir_dataout_3_par_l2'length-1), + din => iu2_dir_dataout_3_par_d, + dout => iu2_dir_dataout_3_par_l2); +iu2_data_dataout_latch: tri_rlmreg_p + generic map (width => iu2_data_dataout_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu1_valid_l2, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu2_data_dataout_offset to iu2_data_dataout_offset + iu2_data_dataout_l2'length-1), + scout => sov(iu2_data_dataout_offset to iu2_data_dataout_offset + iu2_data_dataout_l2'length-1), + din => iu2_data_dataout_d, + dout => iu2_data_dataout_l2); +xu_iu_ici_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_iu_ici_offset), + scout => sov(xu_iu_ici_offset), + din => xu_iu_ici_d, + dout => xu_iu_ici_l2); +dir_row0_val_latch: tri_rlmreg_p + generic map (width => dir_row0_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row0_val_offset to dir_row0_val_offset + dir_row0_val_l2'length-1), + scout => sov(dir_row0_val_offset to dir_row0_val_offset + dir_row0_val_l2'length-1), + din => dir_row0_val_d, + dout => dir_row0_val_l2); +dir_row2_val_latch: tri_rlmreg_p + generic map (width => dir_row2_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row2_val_offset to dir_row2_val_offset + dir_row2_val_l2'length-1), + scout => sov(dir_row2_val_offset to dir_row2_val_offset + dir_row2_val_l2'length-1), + din => dir_row2_val_d, + dout => dir_row2_val_l2); +dir_row4_val_latch: tri_rlmreg_p + generic map (width => dir_row4_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row4_val_offset to dir_row4_val_offset + dir_row4_val_l2'length-1), + scout => sov(dir_row4_val_offset to dir_row4_val_offset + dir_row4_val_l2'length-1), + din => dir_row4_val_d, + dout => dir_row4_val_l2); +dir_row6_val_latch: tri_rlmreg_p + generic map (width => dir_row6_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row6_val_offset to dir_row6_val_offset + dir_row6_val_l2'length-1), + scout => sov(dir_row6_val_offset to dir_row6_val_offset + dir_row6_val_l2'length-1), + din => dir_row6_val_d, + dout => dir_row6_val_l2); +dir_row8_val_latch: tri_rlmreg_p + generic map (width => dir_row8_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row8_val_offset to dir_row8_val_offset + dir_row8_val_l2'length-1), + scout => sov(dir_row8_val_offset to dir_row8_val_offset + dir_row8_val_l2'length-1), + din => dir_row8_val_d, + dout => dir_row8_val_l2); +dir_row10_val_latch: tri_rlmreg_p + generic map (width => dir_row10_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row10_val_offset to dir_row10_val_offset + dir_row10_val_l2'length-1), + scout => sov(dir_row10_val_offset to dir_row10_val_offset + dir_row10_val_l2'length-1), + din => dir_row10_val_d, + dout => dir_row10_val_l2); +dir_row12_val_latch: tri_rlmreg_p + generic map (width => dir_row12_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row12_val_offset to dir_row12_val_offset + dir_row12_val_l2'length-1), + scout => sov(dir_row12_val_offset to dir_row12_val_offset + dir_row12_val_l2'length-1), + din => dir_row12_val_d, + dout => dir_row12_val_l2); +dir_row14_val_latch: tri_rlmreg_p + generic map (width => dir_row14_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row14_val_offset to dir_row14_val_offset + dir_row14_val_l2'length-1), + scout => sov(dir_row14_val_offset to dir_row14_val_offset + dir_row14_val_l2'length-1), + din => dir_row14_val_d, + dout => dir_row14_val_l2); +dir_row16_val_latch: tri_rlmreg_p + generic map (width => dir_row16_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row16_val_offset to dir_row16_val_offset + dir_row16_val_l2'length-1), + scout => sov(dir_row16_val_offset to dir_row16_val_offset + dir_row16_val_l2'length-1), + din => dir_row16_val_d, + dout => dir_row16_val_l2); +dir_row18_val_latch: tri_rlmreg_p + generic map (width => dir_row18_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row18_val_offset to dir_row18_val_offset + dir_row18_val_l2'length-1), + scout => sov(dir_row18_val_offset to dir_row18_val_offset + dir_row18_val_l2'length-1), + din => dir_row18_val_d, + dout => dir_row18_val_l2); +dir_row20_val_latch: tri_rlmreg_p + generic map (width => dir_row20_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row20_val_offset to dir_row20_val_offset + dir_row20_val_l2'length-1), + scout => sov(dir_row20_val_offset to dir_row20_val_offset + dir_row20_val_l2'length-1), + din => dir_row20_val_d, + dout => dir_row20_val_l2); +dir_row22_val_latch: tri_rlmreg_p + generic map (width => dir_row22_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row22_val_offset to dir_row22_val_offset + dir_row22_val_l2'length-1), + scout => sov(dir_row22_val_offset to dir_row22_val_offset + dir_row22_val_l2'length-1), + din => dir_row22_val_d, + dout => dir_row22_val_l2); +dir_row24_val_latch: tri_rlmreg_p + generic map (width => dir_row24_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row24_val_offset to dir_row24_val_offset + dir_row24_val_l2'length-1), + scout => sov(dir_row24_val_offset to dir_row24_val_offset + dir_row24_val_l2'length-1), + din => dir_row24_val_d, + dout => dir_row24_val_l2); +dir_row26_val_latch: tri_rlmreg_p + generic map (width => dir_row26_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row26_val_offset to dir_row26_val_offset + dir_row26_val_l2'length-1), + scout => sov(dir_row26_val_offset to dir_row26_val_offset + dir_row26_val_l2'length-1), + din => dir_row26_val_d, + dout => dir_row26_val_l2); +dir_row28_val_latch: tri_rlmreg_p + generic map (width => dir_row28_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row28_val_offset to dir_row28_val_offset + dir_row28_val_l2'length-1), + scout => sov(dir_row28_val_offset to dir_row28_val_offset + dir_row28_val_l2'length-1), + din => dir_row28_val_d, + dout => dir_row28_val_l2); +dir_row30_val_latch: tri_rlmreg_p + generic map (width => dir_row30_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row30_val_offset to dir_row30_val_offset + dir_row30_val_l2'length-1), + scout => sov(dir_row30_val_offset to dir_row30_val_offset + dir_row30_val_l2'length-1), + din => dir_row30_val_d, + dout => dir_row30_val_l2); +dir_row32_val_latch: tri_rlmreg_p + generic map (width => dir_row32_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row32_val_offset to dir_row32_val_offset + dir_row32_val_l2'length-1), + scout => sov(dir_row32_val_offset to dir_row32_val_offset + dir_row32_val_l2'length-1), + din => dir_row32_val_d, + dout => dir_row32_val_l2); +dir_row34_val_latch: tri_rlmreg_p + generic map (width => dir_row34_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row34_val_offset to dir_row34_val_offset + dir_row34_val_l2'length-1), + scout => sov(dir_row34_val_offset to dir_row34_val_offset + dir_row34_val_l2'length-1), + din => dir_row34_val_d, + dout => dir_row34_val_l2); +dir_row36_val_latch: tri_rlmreg_p + generic map (width => dir_row36_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row36_val_offset to dir_row36_val_offset + dir_row36_val_l2'length-1), + scout => sov(dir_row36_val_offset to dir_row36_val_offset + dir_row36_val_l2'length-1), + din => dir_row36_val_d, + dout => dir_row36_val_l2); +dir_row38_val_latch: tri_rlmreg_p + generic map (width => dir_row38_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row38_val_offset to dir_row38_val_offset + dir_row38_val_l2'length-1), + scout => sov(dir_row38_val_offset to dir_row38_val_offset + dir_row38_val_l2'length-1), + din => dir_row38_val_d, + dout => dir_row38_val_l2); +dir_row40_val_latch: tri_rlmreg_p + generic map (width => dir_row40_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row40_val_offset to dir_row40_val_offset + dir_row40_val_l2'length-1), + scout => sov(dir_row40_val_offset to dir_row40_val_offset + dir_row40_val_l2'length-1), + din => dir_row40_val_d, + dout => dir_row40_val_l2); +dir_row42_val_latch: tri_rlmreg_p + generic map (width => dir_row42_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row42_val_offset to dir_row42_val_offset + dir_row42_val_l2'length-1), + scout => sov(dir_row42_val_offset to dir_row42_val_offset + dir_row42_val_l2'length-1), + din => dir_row42_val_d, + dout => dir_row42_val_l2); +dir_row44_val_latch: tri_rlmreg_p + generic map (width => dir_row44_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row44_val_offset to dir_row44_val_offset + dir_row44_val_l2'length-1), + scout => sov(dir_row44_val_offset to dir_row44_val_offset + dir_row44_val_l2'length-1), + din => dir_row44_val_d, + dout => dir_row44_val_l2); +dir_row46_val_latch: tri_rlmreg_p + generic map (width => dir_row46_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row46_val_offset to dir_row46_val_offset + dir_row46_val_l2'length-1), + scout => sov(dir_row46_val_offset to dir_row46_val_offset + dir_row46_val_l2'length-1), + din => dir_row46_val_d, + dout => dir_row46_val_l2); +dir_row48_val_latch: tri_rlmreg_p + generic map (width => dir_row48_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row48_val_offset to dir_row48_val_offset + dir_row48_val_l2'length-1), + scout => sov(dir_row48_val_offset to dir_row48_val_offset + dir_row48_val_l2'length-1), + din => dir_row48_val_d, + dout => dir_row48_val_l2); +dir_row50_val_latch: tri_rlmreg_p + generic map (width => dir_row50_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row50_val_offset to dir_row50_val_offset + dir_row50_val_l2'length-1), + scout => sov(dir_row50_val_offset to dir_row50_val_offset + dir_row50_val_l2'length-1), + din => dir_row50_val_d, + dout => dir_row50_val_l2); +dir_row52_val_latch: tri_rlmreg_p + generic map (width => dir_row52_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row52_val_offset to dir_row52_val_offset + dir_row52_val_l2'length-1), + scout => sov(dir_row52_val_offset to dir_row52_val_offset + dir_row52_val_l2'length-1), + din => dir_row52_val_d, + dout => dir_row52_val_l2); +dir_row54_val_latch: tri_rlmreg_p + generic map (width => dir_row54_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row54_val_offset to dir_row54_val_offset + dir_row54_val_l2'length-1), + scout => sov(dir_row54_val_offset to dir_row54_val_offset + dir_row54_val_l2'length-1), + din => dir_row54_val_d, + dout => dir_row54_val_l2); +dir_row56_val_latch: tri_rlmreg_p + generic map (width => dir_row56_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row56_val_offset to dir_row56_val_offset + dir_row56_val_l2'length-1), + scout => sov(dir_row56_val_offset to dir_row56_val_offset + dir_row56_val_l2'length-1), + din => dir_row56_val_d, + dout => dir_row56_val_l2); +dir_row58_val_latch: tri_rlmreg_p + generic map (width => dir_row58_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row58_val_offset to dir_row58_val_offset + dir_row58_val_l2'length-1), + scout => sov(dir_row58_val_offset to dir_row58_val_offset + dir_row58_val_l2'length-1), + din => dir_row58_val_d, + dout => dir_row58_val_l2); +dir_row60_val_latch: tri_rlmreg_p + generic map (width => dir_row60_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row60_val_offset to dir_row60_val_offset + dir_row60_val_l2'length-1), + scout => sov(dir_row60_val_offset to dir_row60_val_offset + dir_row60_val_l2'length-1), + din => dir_row60_val_d, + dout => dir_row60_val_l2); +dir_row62_val_latch: tri_rlmreg_p + generic map (width => dir_row62_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row62_val_offset to dir_row62_val_offset + dir_row62_val_l2'length-1), + scout => sov(dir_row62_val_offset to dir_row62_val_offset + dir_row62_val_l2'length-1), + din => dir_row62_val_d, + dout => dir_row62_val_l2); +dir_row0_lru_latch: tri_rlmreg_p + generic map (width => dir_row0_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row0_lru_offset to dir_row0_lru_offset + dir_row0_lru_l2'length-1), + scout => sov(dir_row0_lru_offset to dir_row0_lru_offset + dir_row0_lru_l2'length-1), + din => dir_row0_lru_d, + dout => dir_row0_lru_l2); +dir_row2_lru_latch: tri_rlmreg_p + generic map (width => dir_row2_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row2_lru_offset to dir_row2_lru_offset + dir_row2_lru_l2'length-1), + scout => sov(dir_row2_lru_offset to dir_row2_lru_offset + dir_row2_lru_l2'length-1), + din => dir_row2_lru_d, + dout => dir_row2_lru_l2); +dir_row4_lru_latch: tri_rlmreg_p + generic map (width => dir_row4_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row4_lru_offset to dir_row4_lru_offset + dir_row4_lru_l2'length-1), + scout => sov(dir_row4_lru_offset to dir_row4_lru_offset + dir_row4_lru_l2'length-1), + din => dir_row4_lru_d, + dout => dir_row4_lru_l2); +dir_row6_lru_latch: tri_rlmreg_p + generic map (width => dir_row6_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row6_lru_offset to dir_row6_lru_offset + dir_row6_lru_l2'length-1), + scout => sov(dir_row6_lru_offset to dir_row6_lru_offset + dir_row6_lru_l2'length-1), + din => dir_row6_lru_d, + dout => dir_row6_lru_l2); +dir_row8_lru_latch: tri_rlmreg_p + generic map (width => dir_row8_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row8_lru_offset to dir_row8_lru_offset + dir_row8_lru_l2'length-1), + scout => sov(dir_row8_lru_offset to dir_row8_lru_offset + dir_row8_lru_l2'length-1), + din => dir_row8_lru_d, + dout => dir_row8_lru_l2); +dir_row10_lru_latch: tri_rlmreg_p + generic map (width => dir_row10_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row10_lru_offset to dir_row10_lru_offset + dir_row10_lru_l2'length-1), + scout => sov(dir_row10_lru_offset to dir_row10_lru_offset + dir_row10_lru_l2'length-1), + din => dir_row10_lru_d, + dout => dir_row10_lru_l2); +dir_row12_lru_latch: tri_rlmreg_p + generic map (width => dir_row12_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row12_lru_offset to dir_row12_lru_offset + dir_row12_lru_l2'length-1), + scout => sov(dir_row12_lru_offset to dir_row12_lru_offset + dir_row12_lru_l2'length-1), + din => dir_row12_lru_d, + dout => dir_row12_lru_l2); +dir_row14_lru_latch: tri_rlmreg_p + generic map (width => dir_row14_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row14_lru_offset to dir_row14_lru_offset + dir_row14_lru_l2'length-1), + scout => sov(dir_row14_lru_offset to dir_row14_lru_offset + dir_row14_lru_l2'length-1), + din => dir_row14_lru_d, + dout => dir_row14_lru_l2); +dir_row16_lru_latch: tri_rlmreg_p + generic map (width => dir_row16_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row16_lru_offset to dir_row16_lru_offset + dir_row16_lru_l2'length-1), + scout => sov(dir_row16_lru_offset to dir_row16_lru_offset + dir_row16_lru_l2'length-1), + din => dir_row16_lru_d, + dout => dir_row16_lru_l2); +dir_row18_lru_latch: tri_rlmreg_p + generic map (width => dir_row18_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row18_lru_offset to dir_row18_lru_offset + dir_row18_lru_l2'length-1), + scout => sov(dir_row18_lru_offset to dir_row18_lru_offset + dir_row18_lru_l2'length-1), + din => dir_row18_lru_d, + dout => dir_row18_lru_l2); +dir_row20_lru_latch: tri_rlmreg_p + generic map (width => dir_row20_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row20_lru_offset to dir_row20_lru_offset + dir_row20_lru_l2'length-1), + scout => sov(dir_row20_lru_offset to dir_row20_lru_offset + dir_row20_lru_l2'length-1), + din => dir_row20_lru_d, + dout => dir_row20_lru_l2); +dir_row22_lru_latch: tri_rlmreg_p + generic map (width => dir_row22_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row22_lru_offset to dir_row22_lru_offset + dir_row22_lru_l2'length-1), + scout => sov(dir_row22_lru_offset to dir_row22_lru_offset + dir_row22_lru_l2'length-1), + din => dir_row22_lru_d, + dout => dir_row22_lru_l2); +dir_row24_lru_latch: tri_rlmreg_p + generic map (width => dir_row24_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row24_lru_offset to dir_row24_lru_offset + dir_row24_lru_l2'length-1), + scout => sov(dir_row24_lru_offset to dir_row24_lru_offset + dir_row24_lru_l2'length-1), + din => dir_row24_lru_d, + dout => dir_row24_lru_l2); +dir_row26_lru_latch: tri_rlmreg_p + generic map (width => dir_row26_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row26_lru_offset to dir_row26_lru_offset + dir_row26_lru_l2'length-1), + scout => sov(dir_row26_lru_offset to dir_row26_lru_offset + dir_row26_lru_l2'length-1), + din => dir_row26_lru_d, + dout => dir_row26_lru_l2); +dir_row28_lru_latch: tri_rlmreg_p + generic map (width => dir_row28_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row28_lru_offset to dir_row28_lru_offset + dir_row28_lru_l2'length-1), + scout => sov(dir_row28_lru_offset to dir_row28_lru_offset + dir_row28_lru_l2'length-1), + din => dir_row28_lru_d, + dout => dir_row28_lru_l2); +dir_row30_lru_latch: tri_rlmreg_p + generic map (width => dir_row30_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row30_lru_offset to dir_row30_lru_offset + dir_row30_lru_l2'length-1), + scout => sov(dir_row30_lru_offset to dir_row30_lru_offset + dir_row30_lru_l2'length-1), + din => dir_row30_lru_d, + dout => dir_row30_lru_l2); +dir_row32_lru_latch: tri_rlmreg_p + generic map (width => dir_row32_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row32_lru_offset to dir_row32_lru_offset + dir_row32_lru_l2'length-1), + scout => sov(dir_row32_lru_offset to dir_row32_lru_offset + dir_row32_lru_l2'length-1), + din => dir_row32_lru_d, + dout => dir_row32_lru_l2); +dir_row34_lru_latch: tri_rlmreg_p + generic map (width => dir_row34_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row34_lru_offset to dir_row34_lru_offset + dir_row34_lru_l2'length-1), + scout => sov(dir_row34_lru_offset to dir_row34_lru_offset + dir_row34_lru_l2'length-1), + din => dir_row34_lru_d, + dout => dir_row34_lru_l2); +dir_row36_lru_latch: tri_rlmreg_p + generic map (width => dir_row36_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row36_lru_offset to dir_row36_lru_offset + dir_row36_lru_l2'length-1), + scout => sov(dir_row36_lru_offset to dir_row36_lru_offset + dir_row36_lru_l2'length-1), + din => dir_row36_lru_d, + dout => dir_row36_lru_l2); +dir_row38_lru_latch: tri_rlmreg_p + generic map (width => dir_row38_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row38_lru_offset to dir_row38_lru_offset + dir_row38_lru_l2'length-1), + scout => sov(dir_row38_lru_offset to dir_row38_lru_offset + dir_row38_lru_l2'length-1), + din => dir_row38_lru_d, + dout => dir_row38_lru_l2); +dir_row40_lru_latch: tri_rlmreg_p + generic map (width => dir_row40_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row40_lru_offset to dir_row40_lru_offset + dir_row40_lru_l2'length-1), + scout => sov(dir_row40_lru_offset to dir_row40_lru_offset + dir_row40_lru_l2'length-1), + din => dir_row40_lru_d, + dout => dir_row40_lru_l2); +dir_row42_lru_latch: tri_rlmreg_p + generic map (width => dir_row42_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row42_lru_offset to dir_row42_lru_offset + dir_row42_lru_l2'length-1), + scout => sov(dir_row42_lru_offset to dir_row42_lru_offset + dir_row42_lru_l2'length-1), + din => dir_row42_lru_d, + dout => dir_row42_lru_l2); +dir_row44_lru_latch: tri_rlmreg_p + generic map (width => dir_row44_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row44_lru_offset to dir_row44_lru_offset + dir_row44_lru_l2'length-1), + scout => sov(dir_row44_lru_offset to dir_row44_lru_offset + dir_row44_lru_l2'length-1), + din => dir_row44_lru_d, + dout => dir_row44_lru_l2); +dir_row46_lru_latch: tri_rlmreg_p + generic map (width => dir_row46_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row46_lru_offset to dir_row46_lru_offset + dir_row46_lru_l2'length-1), + scout => sov(dir_row46_lru_offset to dir_row46_lru_offset + dir_row46_lru_l2'length-1), + din => dir_row46_lru_d, + dout => dir_row46_lru_l2); +dir_row48_lru_latch: tri_rlmreg_p + generic map (width => dir_row48_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row48_lru_offset to dir_row48_lru_offset + dir_row48_lru_l2'length-1), + scout => sov(dir_row48_lru_offset to dir_row48_lru_offset + dir_row48_lru_l2'length-1), + din => dir_row48_lru_d, + dout => dir_row48_lru_l2); +dir_row50_lru_latch: tri_rlmreg_p + generic map (width => dir_row50_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row50_lru_offset to dir_row50_lru_offset + dir_row50_lru_l2'length-1), + scout => sov(dir_row50_lru_offset to dir_row50_lru_offset + dir_row50_lru_l2'length-1), + din => dir_row50_lru_d, + dout => dir_row50_lru_l2); +dir_row52_lru_latch: tri_rlmreg_p + generic map (width => dir_row52_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row52_lru_offset to dir_row52_lru_offset + dir_row52_lru_l2'length-1), + scout => sov(dir_row52_lru_offset to dir_row52_lru_offset + dir_row52_lru_l2'length-1), + din => dir_row52_lru_d, + dout => dir_row52_lru_l2); +dir_row54_lru_latch: tri_rlmreg_p + generic map (width => dir_row54_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row54_lru_offset to dir_row54_lru_offset + dir_row54_lru_l2'length-1), + scout => sov(dir_row54_lru_offset to dir_row54_lru_offset + dir_row54_lru_l2'length-1), + din => dir_row54_lru_d, + dout => dir_row54_lru_l2); +dir_row56_lru_latch: tri_rlmreg_p + generic map (width => dir_row56_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row56_lru_offset to dir_row56_lru_offset + dir_row56_lru_l2'length-1), + scout => sov(dir_row56_lru_offset to dir_row56_lru_offset + dir_row56_lru_l2'length-1), + din => dir_row56_lru_d, + dout => dir_row56_lru_l2); +dir_row58_lru_latch: tri_rlmreg_p + generic map (width => dir_row58_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row58_lru_offset to dir_row58_lru_offset + dir_row58_lru_l2'length-1), + scout => sov(dir_row58_lru_offset to dir_row58_lru_offset + dir_row58_lru_l2'length-1), + din => dir_row58_lru_d, + dout => dir_row58_lru_l2); +dir_row60_lru_latch: tri_rlmreg_p + generic map (width => dir_row60_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row60_lru_offset to dir_row60_lru_offset + dir_row60_lru_l2'length-1), + scout => sov(dir_row60_lru_offset to dir_row60_lru_offset + dir_row60_lru_l2'length-1), + din => dir_row60_lru_d, + dout => dir_row60_lru_l2); +dir_row62_lru_latch: tri_rlmreg_p + generic map (width => dir_row62_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row62_lru_offset to dir_row62_lru_offset + dir_row62_lru_l2'length-1), + scout => sov(dir_row62_lru_offset to dir_row62_lru_offset + dir_row62_lru_l2'length-1), + din => dir_row62_lru_d, + dout => dir_row62_lru_l2); +dir_row1_val_latch: tri_rlmreg_p + generic map (width => dir_row1_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row1_val_offset to dir_row1_val_offset + dir_row1_val_l2'length-1), + scout => sov(dir_row1_val_offset to dir_row1_val_offset + dir_row1_val_l2'length-1), + din => dir_row1_val_d, + dout => dir_row1_val_l2); +dir_row3_val_latch: tri_rlmreg_p + generic map (width => dir_row3_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row3_val_offset to dir_row3_val_offset + dir_row3_val_l2'length-1), + scout => sov(dir_row3_val_offset to dir_row3_val_offset + dir_row3_val_l2'length-1), + din => dir_row3_val_d, + dout => dir_row3_val_l2); +dir_row5_val_latch: tri_rlmreg_p + generic map (width => dir_row5_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row5_val_offset to dir_row5_val_offset + dir_row5_val_l2'length-1), + scout => sov(dir_row5_val_offset to dir_row5_val_offset + dir_row5_val_l2'length-1), + din => dir_row5_val_d, + dout => dir_row5_val_l2); +dir_row7_val_latch: tri_rlmreg_p + generic map (width => dir_row7_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row7_val_offset to dir_row7_val_offset + dir_row7_val_l2'length-1), + scout => sov(dir_row7_val_offset to dir_row7_val_offset + dir_row7_val_l2'length-1), + din => dir_row7_val_d, + dout => dir_row7_val_l2); +dir_row9_val_latch: tri_rlmreg_p + generic map (width => dir_row9_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row9_val_offset to dir_row9_val_offset + dir_row9_val_l2'length-1), + scout => sov(dir_row9_val_offset to dir_row9_val_offset + dir_row9_val_l2'length-1), + din => dir_row9_val_d, + dout => dir_row9_val_l2); +dir_row11_val_latch: tri_rlmreg_p + generic map (width => dir_row11_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row11_val_offset to dir_row11_val_offset + dir_row11_val_l2'length-1), + scout => sov(dir_row11_val_offset to dir_row11_val_offset + dir_row11_val_l2'length-1), + din => dir_row11_val_d, + dout => dir_row11_val_l2); +dir_row13_val_latch: tri_rlmreg_p + generic map (width => dir_row13_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row13_val_offset to dir_row13_val_offset + dir_row13_val_l2'length-1), + scout => sov(dir_row13_val_offset to dir_row13_val_offset + dir_row13_val_l2'length-1), + din => dir_row13_val_d, + dout => dir_row13_val_l2); +dir_row15_val_latch: tri_rlmreg_p + generic map (width => dir_row15_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row15_val_offset to dir_row15_val_offset + dir_row15_val_l2'length-1), + scout => sov(dir_row15_val_offset to dir_row15_val_offset + dir_row15_val_l2'length-1), + din => dir_row15_val_d, + dout => dir_row15_val_l2); +dir_row17_val_latch: tri_rlmreg_p + generic map (width => dir_row17_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row17_val_offset to dir_row17_val_offset + dir_row17_val_l2'length-1), + scout => sov(dir_row17_val_offset to dir_row17_val_offset + dir_row17_val_l2'length-1), + din => dir_row17_val_d, + dout => dir_row17_val_l2); +dir_row19_val_latch: tri_rlmreg_p + generic map (width => dir_row19_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row19_val_offset to dir_row19_val_offset + dir_row19_val_l2'length-1), + scout => sov(dir_row19_val_offset to dir_row19_val_offset + dir_row19_val_l2'length-1), + din => dir_row19_val_d, + dout => dir_row19_val_l2); +dir_row21_val_latch: tri_rlmreg_p + generic map (width => dir_row21_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row21_val_offset to dir_row21_val_offset + dir_row21_val_l2'length-1), + scout => sov(dir_row21_val_offset to dir_row21_val_offset + dir_row21_val_l2'length-1), + din => dir_row21_val_d, + dout => dir_row21_val_l2); +dir_row23_val_latch: tri_rlmreg_p + generic map (width => dir_row23_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row23_val_offset to dir_row23_val_offset + dir_row23_val_l2'length-1), + scout => sov(dir_row23_val_offset to dir_row23_val_offset + dir_row23_val_l2'length-1), + din => dir_row23_val_d, + dout => dir_row23_val_l2); +dir_row25_val_latch: tri_rlmreg_p + generic map (width => dir_row25_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row25_val_offset to dir_row25_val_offset + dir_row25_val_l2'length-1), + scout => sov(dir_row25_val_offset to dir_row25_val_offset + dir_row25_val_l2'length-1), + din => dir_row25_val_d, + dout => dir_row25_val_l2); +dir_row27_val_latch: tri_rlmreg_p + generic map (width => dir_row27_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row27_val_offset to dir_row27_val_offset + dir_row27_val_l2'length-1), + scout => sov(dir_row27_val_offset to dir_row27_val_offset + dir_row27_val_l2'length-1), + din => dir_row27_val_d, + dout => dir_row27_val_l2); +dir_row29_val_latch: tri_rlmreg_p + generic map (width => dir_row29_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row29_val_offset to dir_row29_val_offset + dir_row29_val_l2'length-1), + scout => sov(dir_row29_val_offset to dir_row29_val_offset + dir_row29_val_l2'length-1), + din => dir_row29_val_d, + dout => dir_row29_val_l2); +dir_row31_val_latch: tri_rlmreg_p + generic map (width => dir_row31_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row31_val_offset to dir_row31_val_offset + dir_row31_val_l2'length-1), + scout => sov(dir_row31_val_offset to dir_row31_val_offset + dir_row31_val_l2'length-1), + din => dir_row31_val_d, + dout => dir_row31_val_l2); +dir_row33_val_latch: tri_rlmreg_p + generic map (width => dir_row33_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row33_val_offset to dir_row33_val_offset + dir_row33_val_l2'length-1), + scout => sov(dir_row33_val_offset to dir_row33_val_offset + dir_row33_val_l2'length-1), + din => dir_row33_val_d, + dout => dir_row33_val_l2); +dir_row35_val_latch: tri_rlmreg_p + generic map (width => dir_row35_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row35_val_offset to dir_row35_val_offset + dir_row35_val_l2'length-1), + scout => sov(dir_row35_val_offset to dir_row35_val_offset + dir_row35_val_l2'length-1), + din => dir_row35_val_d, + dout => dir_row35_val_l2); +dir_row37_val_latch: tri_rlmreg_p + generic map (width => dir_row37_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row37_val_offset to dir_row37_val_offset + dir_row37_val_l2'length-1), + scout => sov(dir_row37_val_offset to dir_row37_val_offset + dir_row37_val_l2'length-1), + din => dir_row37_val_d, + dout => dir_row37_val_l2); +dir_row39_val_latch: tri_rlmreg_p + generic map (width => dir_row39_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row39_val_offset to dir_row39_val_offset + dir_row39_val_l2'length-1), + scout => sov(dir_row39_val_offset to dir_row39_val_offset + dir_row39_val_l2'length-1), + din => dir_row39_val_d, + dout => dir_row39_val_l2); +dir_row41_val_latch: tri_rlmreg_p + generic map (width => dir_row41_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row41_val_offset to dir_row41_val_offset + dir_row41_val_l2'length-1), + scout => sov(dir_row41_val_offset to dir_row41_val_offset + dir_row41_val_l2'length-1), + din => dir_row41_val_d, + dout => dir_row41_val_l2); +dir_row43_val_latch: tri_rlmreg_p + generic map (width => dir_row43_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row43_val_offset to dir_row43_val_offset + dir_row43_val_l2'length-1), + scout => sov(dir_row43_val_offset to dir_row43_val_offset + dir_row43_val_l2'length-1), + din => dir_row43_val_d, + dout => dir_row43_val_l2); +dir_row45_val_latch: tri_rlmreg_p + generic map (width => dir_row45_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row45_val_offset to dir_row45_val_offset + dir_row45_val_l2'length-1), + scout => sov(dir_row45_val_offset to dir_row45_val_offset + dir_row45_val_l2'length-1), + din => dir_row45_val_d, + dout => dir_row45_val_l2); +dir_row47_val_latch: tri_rlmreg_p + generic map (width => dir_row47_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row47_val_offset to dir_row47_val_offset + dir_row47_val_l2'length-1), + scout => sov(dir_row47_val_offset to dir_row47_val_offset + dir_row47_val_l2'length-1), + din => dir_row47_val_d, + dout => dir_row47_val_l2); +dir_row49_val_latch: tri_rlmreg_p + generic map (width => dir_row49_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row49_val_offset to dir_row49_val_offset + dir_row49_val_l2'length-1), + scout => sov(dir_row49_val_offset to dir_row49_val_offset + dir_row49_val_l2'length-1), + din => dir_row49_val_d, + dout => dir_row49_val_l2); +dir_row51_val_latch: tri_rlmreg_p + generic map (width => dir_row51_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row51_val_offset to dir_row51_val_offset + dir_row51_val_l2'length-1), + scout => sov(dir_row51_val_offset to dir_row51_val_offset + dir_row51_val_l2'length-1), + din => dir_row51_val_d, + dout => dir_row51_val_l2); +dir_row53_val_latch: tri_rlmreg_p + generic map (width => dir_row53_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row53_val_offset to dir_row53_val_offset + dir_row53_val_l2'length-1), + scout => sov(dir_row53_val_offset to dir_row53_val_offset + dir_row53_val_l2'length-1), + din => dir_row53_val_d, + dout => dir_row53_val_l2); +dir_row55_val_latch: tri_rlmreg_p + generic map (width => dir_row55_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row55_val_offset to dir_row55_val_offset + dir_row55_val_l2'length-1), + scout => sov(dir_row55_val_offset to dir_row55_val_offset + dir_row55_val_l2'length-1), + din => dir_row55_val_d, + dout => dir_row55_val_l2); +dir_row57_val_latch: tri_rlmreg_p + generic map (width => dir_row57_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row57_val_offset to dir_row57_val_offset + dir_row57_val_l2'length-1), + scout => sov(dir_row57_val_offset to dir_row57_val_offset + dir_row57_val_l2'length-1), + din => dir_row57_val_d, + dout => dir_row57_val_l2); +dir_row59_val_latch: tri_rlmreg_p + generic map (width => dir_row59_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row59_val_offset to dir_row59_val_offset + dir_row59_val_l2'length-1), + scout => sov(dir_row59_val_offset to dir_row59_val_offset + dir_row59_val_l2'length-1), + din => dir_row59_val_d, + dout => dir_row59_val_l2); +dir_row61_val_latch: tri_rlmreg_p + generic map (width => dir_row61_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row61_val_offset to dir_row61_val_offset + dir_row61_val_l2'length-1), + scout => sov(dir_row61_val_offset to dir_row61_val_offset + dir_row61_val_l2'length-1), + din => dir_row61_val_d, + dout => dir_row61_val_l2); +dir_row63_val_latch: tri_rlmreg_p + generic map (width => dir_row63_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row63_val_offset to dir_row63_val_offset + dir_row63_val_l2'length-1), + scout => sov(dir_row63_val_offset to dir_row63_val_offset + dir_row63_val_l2'length-1), + din => dir_row63_val_d, + dout => dir_row63_val_l2); +dir_row1_lru_latch: tri_rlmreg_p + generic map (width => dir_row1_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row1_lru_offset to dir_row1_lru_offset + dir_row1_lru_l2'length-1), + scout => sov(dir_row1_lru_offset to dir_row1_lru_offset + dir_row1_lru_l2'length-1), + din => dir_row1_lru_d, + dout => dir_row1_lru_l2); +dir_row3_lru_latch: tri_rlmreg_p + generic map (width => dir_row3_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row3_lru_offset to dir_row3_lru_offset + dir_row3_lru_l2'length-1), + scout => sov(dir_row3_lru_offset to dir_row3_lru_offset + dir_row3_lru_l2'length-1), + din => dir_row3_lru_d, + dout => dir_row3_lru_l2); +dir_row5_lru_latch: tri_rlmreg_p + generic map (width => dir_row5_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row5_lru_offset to dir_row5_lru_offset + dir_row5_lru_l2'length-1), + scout => sov(dir_row5_lru_offset to dir_row5_lru_offset + dir_row5_lru_l2'length-1), + din => dir_row5_lru_d, + dout => dir_row5_lru_l2); +dir_row7_lru_latch: tri_rlmreg_p + generic map (width => dir_row7_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row7_lru_offset to dir_row7_lru_offset + dir_row7_lru_l2'length-1), + scout => sov(dir_row7_lru_offset to dir_row7_lru_offset + dir_row7_lru_l2'length-1), + din => dir_row7_lru_d, + dout => dir_row7_lru_l2); +dir_row9_lru_latch: tri_rlmreg_p + generic map (width => dir_row9_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row9_lru_offset to dir_row9_lru_offset + dir_row9_lru_l2'length-1), + scout => sov(dir_row9_lru_offset to dir_row9_lru_offset + dir_row9_lru_l2'length-1), + din => dir_row9_lru_d, + dout => dir_row9_lru_l2); +dir_row11_lru_latch: tri_rlmreg_p + generic map (width => dir_row11_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row11_lru_offset to dir_row11_lru_offset + dir_row11_lru_l2'length-1), + scout => sov(dir_row11_lru_offset to dir_row11_lru_offset + dir_row11_lru_l2'length-1), + din => dir_row11_lru_d, + dout => dir_row11_lru_l2); +dir_row13_lru_latch: tri_rlmreg_p + generic map (width => dir_row13_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row13_lru_offset to dir_row13_lru_offset + dir_row13_lru_l2'length-1), + scout => sov(dir_row13_lru_offset to dir_row13_lru_offset + dir_row13_lru_l2'length-1), + din => dir_row13_lru_d, + dout => dir_row13_lru_l2); +dir_row15_lru_latch: tri_rlmreg_p + generic map (width => dir_row15_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row15_lru_offset to dir_row15_lru_offset + dir_row15_lru_l2'length-1), + scout => sov(dir_row15_lru_offset to dir_row15_lru_offset + dir_row15_lru_l2'length-1), + din => dir_row15_lru_d, + dout => dir_row15_lru_l2); +dir_row17_lru_latch: tri_rlmreg_p + generic map (width => dir_row17_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row17_lru_offset to dir_row17_lru_offset + dir_row17_lru_l2'length-1), + scout => sov(dir_row17_lru_offset to dir_row17_lru_offset + dir_row17_lru_l2'length-1), + din => dir_row17_lru_d, + dout => dir_row17_lru_l2); +dir_row19_lru_latch: tri_rlmreg_p + generic map (width => dir_row19_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row19_lru_offset to dir_row19_lru_offset + dir_row19_lru_l2'length-1), + scout => sov(dir_row19_lru_offset to dir_row19_lru_offset + dir_row19_lru_l2'length-1), + din => dir_row19_lru_d, + dout => dir_row19_lru_l2); +dir_row21_lru_latch: tri_rlmreg_p + generic map (width => dir_row21_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row21_lru_offset to dir_row21_lru_offset + dir_row21_lru_l2'length-1), + scout => sov(dir_row21_lru_offset to dir_row21_lru_offset + dir_row21_lru_l2'length-1), + din => dir_row21_lru_d, + dout => dir_row21_lru_l2); +dir_row23_lru_latch: tri_rlmreg_p + generic map (width => dir_row23_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row23_lru_offset to dir_row23_lru_offset + dir_row23_lru_l2'length-1), + scout => sov(dir_row23_lru_offset to dir_row23_lru_offset + dir_row23_lru_l2'length-1), + din => dir_row23_lru_d, + dout => dir_row23_lru_l2); +dir_row25_lru_latch: tri_rlmreg_p + generic map (width => dir_row25_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row25_lru_offset to dir_row25_lru_offset + dir_row25_lru_l2'length-1), + scout => sov(dir_row25_lru_offset to dir_row25_lru_offset + dir_row25_lru_l2'length-1), + din => dir_row25_lru_d, + dout => dir_row25_lru_l2); +dir_row27_lru_latch: tri_rlmreg_p + generic map (width => dir_row27_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row27_lru_offset to dir_row27_lru_offset + dir_row27_lru_l2'length-1), + scout => sov(dir_row27_lru_offset to dir_row27_lru_offset + dir_row27_lru_l2'length-1), + din => dir_row27_lru_d, + dout => dir_row27_lru_l2); +dir_row29_lru_latch: tri_rlmreg_p + generic map (width => dir_row29_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row29_lru_offset to dir_row29_lru_offset + dir_row29_lru_l2'length-1), + scout => sov(dir_row29_lru_offset to dir_row29_lru_offset + dir_row29_lru_l2'length-1), + din => dir_row29_lru_d, + dout => dir_row29_lru_l2); +dir_row31_lru_latch: tri_rlmreg_p + generic map (width => dir_row31_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row31_lru_offset to dir_row31_lru_offset + dir_row31_lru_l2'length-1), + scout => sov(dir_row31_lru_offset to dir_row31_lru_offset + dir_row31_lru_l2'length-1), + din => dir_row31_lru_d, + dout => dir_row31_lru_l2); +dir_row33_lru_latch: tri_rlmreg_p + generic map (width => dir_row33_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row33_lru_offset to dir_row33_lru_offset + dir_row33_lru_l2'length-1), + scout => sov(dir_row33_lru_offset to dir_row33_lru_offset + dir_row33_lru_l2'length-1), + din => dir_row33_lru_d, + dout => dir_row33_lru_l2); +dir_row35_lru_latch: tri_rlmreg_p + generic map (width => dir_row35_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row35_lru_offset to dir_row35_lru_offset + dir_row35_lru_l2'length-1), + scout => sov(dir_row35_lru_offset to dir_row35_lru_offset + dir_row35_lru_l2'length-1), + din => dir_row35_lru_d, + dout => dir_row35_lru_l2); +dir_row37_lru_latch: tri_rlmreg_p + generic map (width => dir_row37_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row37_lru_offset to dir_row37_lru_offset + dir_row37_lru_l2'length-1), + scout => sov(dir_row37_lru_offset to dir_row37_lru_offset + dir_row37_lru_l2'length-1), + din => dir_row37_lru_d, + dout => dir_row37_lru_l2); +dir_row39_lru_latch: tri_rlmreg_p + generic map (width => dir_row39_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row39_lru_offset to dir_row39_lru_offset + dir_row39_lru_l2'length-1), + scout => sov(dir_row39_lru_offset to dir_row39_lru_offset + dir_row39_lru_l2'length-1), + din => dir_row39_lru_d, + dout => dir_row39_lru_l2); +dir_row41_lru_latch: tri_rlmreg_p + generic map (width => dir_row41_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row41_lru_offset to dir_row41_lru_offset + dir_row41_lru_l2'length-1), + scout => sov(dir_row41_lru_offset to dir_row41_lru_offset + dir_row41_lru_l2'length-1), + din => dir_row41_lru_d, + dout => dir_row41_lru_l2); +dir_row43_lru_latch: tri_rlmreg_p + generic map (width => dir_row43_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row43_lru_offset to dir_row43_lru_offset + dir_row43_lru_l2'length-1), + scout => sov(dir_row43_lru_offset to dir_row43_lru_offset + dir_row43_lru_l2'length-1), + din => dir_row43_lru_d, + dout => dir_row43_lru_l2); +dir_row45_lru_latch: tri_rlmreg_p + generic map (width => dir_row45_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row45_lru_offset to dir_row45_lru_offset + dir_row45_lru_l2'length-1), + scout => sov(dir_row45_lru_offset to dir_row45_lru_offset + dir_row45_lru_l2'length-1), + din => dir_row45_lru_d, + dout => dir_row45_lru_l2); +dir_row47_lru_latch: tri_rlmreg_p + generic map (width => dir_row47_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row47_lru_offset to dir_row47_lru_offset + dir_row47_lru_l2'length-1), + scout => sov(dir_row47_lru_offset to dir_row47_lru_offset + dir_row47_lru_l2'length-1), + din => dir_row47_lru_d, + dout => dir_row47_lru_l2); +dir_row49_lru_latch: tri_rlmreg_p + generic map (width => dir_row49_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row49_lru_offset to dir_row49_lru_offset + dir_row49_lru_l2'length-1), + scout => sov(dir_row49_lru_offset to dir_row49_lru_offset + dir_row49_lru_l2'length-1), + din => dir_row49_lru_d, + dout => dir_row49_lru_l2); +dir_row51_lru_latch: tri_rlmreg_p + generic map (width => dir_row51_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row51_lru_offset to dir_row51_lru_offset + dir_row51_lru_l2'length-1), + scout => sov(dir_row51_lru_offset to dir_row51_lru_offset + dir_row51_lru_l2'length-1), + din => dir_row51_lru_d, + dout => dir_row51_lru_l2); +dir_row53_lru_latch: tri_rlmreg_p + generic map (width => dir_row53_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row53_lru_offset to dir_row53_lru_offset + dir_row53_lru_l2'length-1), + scout => sov(dir_row53_lru_offset to dir_row53_lru_offset + dir_row53_lru_l2'length-1), + din => dir_row53_lru_d, + dout => dir_row53_lru_l2); +dir_row55_lru_latch: tri_rlmreg_p + generic map (width => dir_row55_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row55_lru_offset to dir_row55_lru_offset + dir_row55_lru_l2'length-1), + scout => sov(dir_row55_lru_offset to dir_row55_lru_offset + dir_row55_lru_l2'length-1), + din => dir_row55_lru_d, + dout => dir_row55_lru_l2); +dir_row57_lru_latch: tri_rlmreg_p + generic map (width => dir_row57_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row57_lru_offset to dir_row57_lru_offset + dir_row57_lru_l2'length-1), + scout => sov(dir_row57_lru_offset to dir_row57_lru_offset + dir_row57_lru_l2'length-1), + din => dir_row57_lru_d, + dout => dir_row57_lru_l2); +dir_row59_lru_latch: tri_rlmreg_p + generic map (width => dir_row59_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row59_lru_offset to dir_row59_lru_offset + dir_row59_lru_l2'length-1), + scout => sov(dir_row59_lru_offset to dir_row59_lru_offset + dir_row59_lru_l2'length-1), + din => dir_row59_lru_d, + dout => dir_row59_lru_l2); +dir_row61_lru_latch: tri_rlmreg_p + generic map (width => dir_row61_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row61_lru_offset to dir_row61_lru_offset + dir_row61_lru_l2'length-1), + scout => sov(dir_row61_lru_offset to dir_row61_lru_offset + dir_row61_lru_l2'length-1), + din => dir_row61_lru_d, + dout => dir_row61_lru_l2); +dir_row63_lru_latch: tri_rlmreg_p + generic map (width => dir_row63_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row63_lru_offset to dir_row63_lru_offset + dir_row63_lru_l2'length-1), + scout => sov(dir_row63_lru_offset to dir_row63_lru_offset + dir_row63_lru_l2'length-1), + din => dir_row63_lru_d, + dout => dir_row63_lru_l2); +iu3_instr_valid_latch: tri_rlmreg_p + generic map (width => iu3_instr_valid_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu3_instr_valid_offset to iu3_instr_valid_offset + iu3_instr_valid_l2'length-1), + scout => sov(iu3_instr_valid_offset to iu3_instr_valid_offset + iu3_instr_valid_l2'length-1), + din => iu3_instr_valid_d, + dout => iu3_instr_valid_l2); +iu3_tid_latch: tri_rlmreg_p + generic map (width => iu3_tid_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu3_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu3_tid_offset to iu3_tid_offset + iu3_tid_l2'length-1), + scout => sov(iu3_tid_offset to iu3_tid_offset + iu3_tid_l2'length-1), + din => iu3_tid_d, + dout => iu3_tid_l2); +iu3_ifar_latch: tri_rlmreg_p + generic map (width => iu3_ifar_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu3_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu3_ifar_offset to iu3_ifar_offset + iu3_ifar_l2'length-1), + scout => sov(iu3_ifar_offset to iu3_ifar_offset + iu3_ifar_l2'length-1), + din => iu3_ifar_d, + dout => iu3_ifar_l2); +iu3_ifar_dec_latch: tri_rlmreg_p + generic map (width => iu3_ifar_dec_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu3_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu3_ifar_dec_offset to iu3_ifar_dec_offset + iu3_ifar_dec_l2'length-1), + scout => sov(iu3_ifar_dec_offset to iu3_ifar_dec_offset + iu3_ifar_dec_l2'length-1), + din => iu3_ifar_dec_d, + dout => iu3_ifar_dec_l2); +iu3_2ucode_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu3_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu3_2ucode_offset), + scout => sov(iu3_2ucode_offset), + din => iu3_2ucode_d, + dout => iu3_2ucode_l2); +iu3_2ucode_type_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu3_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu3_2ucode_type_offset), + scout => sov(iu3_2ucode_type_offset), + din => iu3_2ucode_type_d, + dout => iu3_2ucode_type_l2); +iu3_erat_err_latch: tri_rlmreg_p + generic map (width => iu3_erat_err_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu3_erat_err_offset to iu3_erat_err_offset + iu3_erat_err_l2'length-1), + scout => sov(iu3_erat_err_offset to iu3_erat_err_offset + iu3_erat_err_l2'length-1), + din => iu3_erat_err_d, + dout => iu3_erat_err_l2); +iu3_dir_parity_err_way_latch: tri_rlmreg_p + generic map (width => iu3_dir_parity_err_way_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu3_parity_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu3_dir_parity_err_way_offset to iu3_dir_parity_err_way_offset + iu3_dir_parity_err_way_l2'length-1), + scout => sov(iu3_dir_parity_err_way_offset to iu3_dir_parity_err_way_offset + iu3_dir_parity_err_way_l2'length-1), + din => iu3_dir_parity_err_way_d, + dout => iu3_dir_parity_err_way_l2); +iu3_data_parity_err_way_latch: tri_rlmreg_p + generic map (width => iu3_data_parity_err_way_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu3_parity_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu3_data_parity_err_way_offset to iu3_data_parity_err_way_offset + iu3_data_parity_err_way_l2'length-1), + scout => sov(iu3_data_parity_err_way_offset to iu3_data_parity_err_way_offset + iu3_data_parity_err_way_l2'length-1), + din => iu3_data_parity_err_way_d, + dout => iu3_data_parity_err_way_l2); +iu3_parity_needs_flush_latch: tri_rlmreg_p + generic map (width => iu3_parity_needs_flush_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu3_parity_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu3_parity_needs_flush_offset to iu3_parity_needs_flush_offset + iu3_parity_needs_flush_l2'length-1), + scout => sov(iu3_parity_needs_flush_offset to iu3_parity_needs_flush_offset + iu3_parity_needs_flush_l2'length-1), + din => iu3_parity_needs_flush_d, + dout => iu3_parity_needs_flush_l2); +iu3_parity_tag_latch: tri_rlmreg_p + generic map (width => iu3_parity_tag_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu3_parity_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu3_parity_tag_offset to iu3_parity_tag_offset + iu3_parity_tag_l2'length-1), + scout => sov(iu3_parity_tag_offset to iu3_parity_tag_offset + iu3_parity_tag_l2'length-1), + din => iu3_parity_tag_d, + dout => iu3_parity_tag_l2); +iu3_rd_parity_err_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu3_parity_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu3_rd_parity_err_offset), + scout => sov(iu3_rd_parity_err_offset), + din => iu3_rd_parity_err_d, + dout => iu3_rd_parity_err_l2); +iu3_rd_miss_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu3_rd_miss_offset), + scout => sov(iu3_rd_miss_offset), + din => iu3_rd_miss_d, + dout => iu3_rd_miss_l2); +err_icache_parity_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(err_icache_parity_offset), + scout => sov(err_icache_parity_offset), + din => err_icache_parity_d, + dout => err_icache_parity_l2); +err_icachedir_parity_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu3_parity_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(err_icachedir_parity_offset), + scout => sov(err_icachedir_parity_offset), + din => err_icachedir_parity_d, + dout => err_icachedir_parity_l2); +iu3_multihit_err_way_latch: tri_rlmreg_p + generic map (width => iu3_multihit_err_way_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu3_parity_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu3_multihit_err_way_offset to iu3_multihit_err_way_offset + iu3_multihit_err_way_l2'length-1), + scout => sov(iu3_multihit_err_way_offset to iu3_multihit_err_way_offset + iu3_multihit_err_way_l2'length-1), + din => iu3_multihit_err_way_d, + dout => iu3_multihit_err_way_l2); +iu3_multihit_flush_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu3_parity_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu3_multihit_flush_offset), + scout => sov(iu3_multihit_flush_offset), + din => iu3_multihit_flush_d, + dout => iu3_multihit_flush_l2); +perf_instr_count_t0_latch: tri_rlmreg_p + generic map (width => perf_instr_count_t0_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu3_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(perf_instr_count_t0_offset to perf_instr_count_t0_offset + perf_instr_count_t0_l2'length-1), + scout => sov(perf_instr_count_t0_offset to perf_instr_count_t0_offset + perf_instr_count_t0_l2'length-1), + din => perf_instr_count_t0_d, + dout => perf_instr_count_t0_l2); +perf_instr_count_t1_latch: tri_rlmreg_p + generic map (width => perf_instr_count_t1_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu3_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(perf_instr_count_t1_offset to perf_instr_count_t1_offset + perf_instr_count_t1_l2'length-1), + scout => sov(perf_instr_count_t1_offset to perf_instr_count_t1_offset + perf_instr_count_t1_l2'length-1), + din => perf_instr_count_t1_d, + dout => perf_instr_count_t1_l2); +perf_instr_count_t2_latch: tri_rlmreg_p + generic map (width => perf_instr_count_t2_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu3_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(perf_instr_count_t2_offset to perf_instr_count_t2_offset + perf_instr_count_t2_l2'length-1), + scout => sov(perf_instr_count_t2_offset to perf_instr_count_t2_offset + perf_instr_count_t2_l2'length-1), + din => perf_instr_count_t2_d, + dout => perf_instr_count_t2_l2); +perf_instr_count_t3_latch: tri_rlmreg_p + generic map (width => perf_instr_count_t3_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu3_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(perf_instr_count_t3_offset to perf_instr_count_t3_offset + perf_instr_count_t3_l2'length-1), + scout => sov(perf_instr_count_t3_offset to perf_instr_count_t3_offset + perf_instr_count_t3_l2'length-1), + din => perf_instr_count_t3_d, + dout => perf_instr_count_t3_l2); +perf_event_t0_latch: tri_rlmreg_p + generic map (width => perf_event_t0_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => event_bus_enable, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(perf_event_t0_offset to perf_event_t0_offset + perf_event_t0_l2'length-1), + scout => sov(perf_event_t0_offset to perf_event_t0_offset + perf_event_t0_l2'length-1), + din => perf_event_t0_d, + dout => perf_event_t0_l2); +perf_event_t1_latch: tri_rlmreg_p + generic map (width => perf_event_t1_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => event_bus_enable, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(perf_event_t1_offset to perf_event_t1_offset + perf_event_t1_l2'length-1), + scout => sov(perf_event_t1_offset to perf_event_t1_offset + perf_event_t1_l2'length-1), + din => perf_event_t1_d, + dout => perf_event_t1_l2); +perf_event_t2_latch: tri_rlmreg_p + generic map (width => perf_event_t2_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => event_bus_enable, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(perf_event_t2_offset to perf_event_t2_offset + perf_event_t2_l2'length-1), + scout => sov(perf_event_t2_offset to perf_event_t2_offset + perf_event_t2_l2'length-1), + din => perf_event_t2_d, + dout => perf_event_t2_l2); +perf_event_t3_latch: tri_rlmreg_p + generic map (width => perf_event_t3_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => event_bus_enable, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(perf_event_t3_offset to perf_event_t3_offset + perf_event_t3_l2'length-1), + scout => sov(perf_event_t3_offset to perf_event_t3_offset + perf_event_t3_l2'length-1), + din => perf_event_t3_d, + dout => perf_event_t3_l2); +perf_event_latch: tri_rlmreg_p + generic map (width => perf_event_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => event_bus_enable, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(perf_event_offset to perf_event_offset + perf_event_l2'length-1), + scout => sov(perf_event_offset to perf_event_offset + perf_event_l2'length-1), + din => perf_event_d, + dout => perf_event_l2); +spr_ic_cls_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(spr_ic_cls_offset), + scout => sov(spr_ic_cls_offset), + din => spr_ic_cls_d, + dout => spr_ic_cls_l2); +spr_ic_idir_way_latch: tri_rlmreg_p + generic map (width => spr_ic_idir_way_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_dataout_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(spr_ic_idir_way_offset to spr_ic_idir_way_offset + spr_ic_idir_way_l2'length-1), + scout => sov(spr_ic_idir_way_offset to spr_ic_idir_way_offset + spr_ic_idir_way_l2'length-1), + din => spr_ic_idir_way_d, + dout => spr_ic_idir_way_l2); +iu1_spr_idir_read_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu1_spr_idir_read_offset), + scout => sov(iu1_spr_idir_read_offset), + din => iu1_spr_idir_read_d, + dout => iu1_spr_idir_read_l2); +iu2_spr_idir_read_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu2_spr_idir_read_offset), + scout => sov(iu2_spr_idir_read_offset), + din => iu2_spr_idir_read_d, + dout => iu2_spr_idir_read_l2); +iu2_spr_idir_lru_latch: tri_rlmreg_p + generic map (width => iu2_spr_idir_lru_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_dataout_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu2_spr_idir_lru_offset to iu2_spr_idir_lru_offset + iu2_spr_idir_lru_l2'length-1), + scout => sov(iu2_spr_idir_lru_offset to iu2_spr_idir_lru_offset + iu2_spr_idir_lru_l2'length-1), + din => iu2_spr_idir_lru_d, + dout => iu2_spr_idir_lru_l2); +dbg_dir_write_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => trace_bus_enable, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dbg_dir_write_offset), + scout => sov(dbg_dir_write_offset), + din => dbg_dir_write_d, + dout => dbg_dir_write_l2); +dbg_dir_rd_act_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => trace_bus_enable, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dbg_dir_rd_act_offset), + scout => sov(dbg_dir_rd_act_offset), + din => dbg_dir_rd_act_d, + dout => dbg_dir_rd_act_l2); +dbg_iu2_lru_rd_update_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => trace_bus_enable, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dbg_iu2_lru_rd_update_offset), + scout => sov(dbg_iu2_lru_rd_update_offset), + din => dbg_iu2_lru_rd_update_d, + dout => dbg_iu2_lru_rd_update_l2); +dbg_iu2_rd_way_tag_hit_latch: tri_rlmreg_p + generic map (width => dbg_iu2_rd_way_tag_hit_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => trace_bus_enable, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dbg_iu2_rd_way_tag_hit_offset to dbg_iu2_rd_way_tag_hit_offset + dbg_iu2_rd_way_tag_hit_l2'length-1), + scout => sov(dbg_iu2_rd_way_tag_hit_offset to dbg_iu2_rd_way_tag_hit_offset + dbg_iu2_rd_way_tag_hit_l2'length-1), + din => dbg_iu2_rd_way_tag_hit_d, + dout => dbg_iu2_rd_way_tag_hit_l2); +dbg_iu2_rd_way_hit_latch: tri_rlmreg_p + generic map (width => dbg_iu2_rd_way_hit_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => trace_bus_enable, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dbg_iu2_rd_way_hit_offset to dbg_iu2_rd_way_hit_offset + dbg_iu2_rd_way_hit_l2'length-1), + scout => sov(dbg_iu2_rd_way_hit_offset to dbg_iu2_rd_way_hit_offset + dbg_iu2_rd_way_hit_l2'length-1), + din => dbg_iu2_rd_way_hit_d, + dout => dbg_iu2_rd_way_hit_l2); +dbg_load_iu2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => trace_bus_enable, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dbg_load_iu2_offset), + scout => sov(dbg_load_iu2_offset), + din => dbg_load_iu2_d, + dout => dbg_load_iu2_l2); +spare_slp_latch: tri_rlmreg_p + generic map (width => spare_slp_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(spare_slp_offset to spare_slp_offset + spare_slp_l2'length-1), + scout => sov(spare_slp_offset to spare_slp_offset + spare_slp_l2'length-1), + din => spare_slp_l2, + dout => spare_slp_l2); +spare_a_latch: tri_rlmreg_p + generic map (width => 8, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(spare_a_offset to spare_a_offset + 7), + scout => sov(spare_a_offset to spare_a_offset + 7), + din => spare_l2(0 to 7), + dout => spare_l2(0 to 7)); +spare_b_latch: tri_rlmreg_p + generic map (width => 8, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(spare_b_offset to spare_b_offset + 7), + scout => sov(spare_b_offset to spare_b_offset + 7), + din => spare_l2(8 to 15), + dout => spare_l2(8 to 15)); +ab_reg: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 39, needs_sreset => 0) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => pc_iu_abist_ena_dc, + thold_b => pc_iu_abst_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => abst_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => abst_siv(4 to 42), + scout => abst_sov(4 to 42), + din ( 0 ) => pc_iu_abist_g8t_wenb, + din ( 1 ) => pc_iu_abist_g8t1p_renb_0, + din ( 2 to 5) => pc_iu_abist_di_0, + din ( 6 ) => pc_iu_abist_g8t_bw_1, + din ( 7 ) => pc_iu_abist_g8t_bw_0, + din ( 8 to 13) => pc_iu_abist_waddr_0, + din (14 ) => pc_iu_abist_wl64_comp_ena, + din (15 to 18) => pc_iu_abist_g8t_dcomp, + din (19 to 26) => pc_iu_abist_raddr_0, + din (27 to 28) => pc_iu_abist_g6t_bw, + din (29 to 32) => pc_iu_abist_di_g6t_2r, + din (33 ) => pc_iu_abist_wl256_comp_ena, + din (34 to 37) => pc_iu_abist_dcomp_g6t_2r, + din (38 ) => pc_iu_abist_g6t_r_wb, + dout( 0 ) => stage_abist_g8t_wenb, + dout( 1 ) => stage_abist_g8t1p_renb_0, + dout( 2 to 5 ) => stage_abist_di_0, + dout( 6 ) => stage_abist_g8t_bw_1, + dout( 7 ) => stage_abist_g8t_bw_0, + dout( 8 to 13) => stage_abist_waddr_0, + dout(14 ) => stage_abist_wl64_comp_ena, + dout(15 to 18) => stage_abist_g8t_dcomp, + dout(19 to 26) => stage_abist_raddr_0, + dout(27 to 28) => stage_abist_g6t_bw, + dout(29 to 32) => stage_abist_di_g6t_2r, + dout(33 ) => stage_abist_wl256_comp_ena, + dout(34 to 37) => stage_abist_dcomp_g6t_2r, + dout(38 ) => stage_abist_g6t_r_wb); +repr_slat_sl_thold_0_b <= not pc_iu_repr_sl_thold_0; +time_slat_sl_thold_0_b <= not pc_iu_time_sl_thold_0; +repr_scan_latch: entity tri.tri_regs + generic map (width => 2, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + forcee => pc_iu_sg_0, + thold_b => repr_slat_sl_thold_0_b, + delay_lclkr => delay_lclkr, + scin(0) => repr_scan_in, + scin(1) => repr_siv(2), + scout(0) => repr_siv(0), + scout(1) => repr_sov(2), + dout => open ); +time_scan_latch: entity tri.tri_regs + generic map (width => 1, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + forcee => pc_iu_sg_0, + thold_b => time_slat_sl_thold_0_b, + delay_lclkr => delay_lclkr, + scin(0) => time_siv(2), + scout(0) => time_sov(2), + dout => open ); +siv(0 TO scan0_right) <= sov(1 to scan0_right) & func_scan_in(0); +func_scan_out(0) <= sov(0) and an_ac_scan_dis_dc_b; +siv(scan1_left TO scan_right) <= sov(scan1_left+1 to scan_right) & func_scan_in(1); +func_scan_out(1) <= sov(scan1_left) and an_ac_scan_dis_dc_b; +abst_siv(0 TO 1) <= abst_sov(1) & abst_scan_in(0); +abst_scan_out(0) <= abst_sov(0) and an_ac_scan_dis_dc_b; +abst_siv(2 TO 3) <= abst_sov(3) & abst_scan_in(1); +abst_scan_out(1) <= abst_sov(2) and an_ac_scan_dis_dc_b; +abst_siv(4 TO abst_siv'right) <= abst_sov(5 to abst_sov'right) & abst_scan_in(2); +abst_scan_out(2) <= abst_sov(4) and an_ac_scan_dis_dc_b; +time_siv <= time_scan_in & time_sov(0 to 1); +time_scan_out <= time_sov(2) and an_ac_scan_dis_dc_b; +repr_siv(1 TO 2) <= repr_sov(0 to 1); +repr_scan_out <= repr_sov(2) and an_ac_scan_dis_dc_b; +END IUQ_IC_DIR; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_ic_dir_cmp.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_ic_dir_cmp.vhdl new file mode 100644 index 0000000..84c1ccf --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_ic_dir_cmp.vhdl @@ -0,0 +1,265 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + +entity iuq_ic_dir_cmp is +generic( expand_type: integer := 2 ); +port( + vdd :inout power_logic; + gnd :inout power_logic; + nclk :in clk_logic; + delay_lclkr :in std_ulogic; + mpw1_b :in std_ulogic; + mpw2_b :in std_ulogic; + forcee :in std_ulogic; + sg_0 :in std_ulogic; + thold_0_b :in std_ulogic; + scan_in :in std_ulogic; + scan_out :out std_ulogic; + + dir_dataout_act :in std_ulogic; + + iu2_endian :in std_ulogic ; + ierat_iu_iu2_rpn :in std_ulogic_vector(22 to 51) ; + iu2_dir_dataout_0_d :in std_ulogic_vector(22 to 52) ; + iu2_dir_dataout_1_d :in std_ulogic_vector(22 to 52) ; + iu2_dir_dataout_2_d :in std_ulogic_vector(22 to 52) ; + iu2_dir_dataout_3_d :in std_ulogic_vector(22 to 52) ; + + ierat_iu_iu2_rpn_noncmp :out std_ulogic_vector(22 to 51) ; + iu2_dir_dataout_0_noncmp :out std_ulogic_vector(22 to 52) ; + iu2_dir_dataout_1_noncmp :out std_ulogic_vector(22 to 52) ; + iu2_dir_dataout_2_noncmp :out std_ulogic_vector(22 to 52) ; + iu2_dir_dataout_3_noncmp :out std_ulogic_vector(22 to 52) ; + + iu2_dir_rd_val :in std_ulogic_vector(0 to 3) ; + iu2_rd_way_tag_hit :out std_ulogic_vector(0 to 3) ; + + iu2_rd_way_hit :out std_ulogic_vector(0 to 3) ; + iu2_rd_way_hit_insmux_b :out std_ulogic_vector(0 to 3) +); + +-- synopsys translate_off + + +-- synopsys translate_on + +end iuq_ic_dir_cmp; + +architecture iuq_ic_dir_cmp of iuq_ic_dir_cmp is + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal dir_lclk :clk_logic; + signal dir_d1clk :std_ulogic; + signal dir_d2clk :std_ulogic; + + signal iu2_dir_dataout_0_l2_b , dir0_q , dir0_si, dir0_so , dir0_slow_b :std_ulogic_vector(0 to 30) ; + signal iu2_dir_dataout_1_l2_b , dir1_q , dir1_si, dir1_so , dir1_slow_b :std_ulogic_vector(0 to 30) ; + signal iu2_dir_dataout_2_l2_b , dir2_q , dir2_si, dir2_so , dir2_slow_b :std_ulogic_vector(0 to 30) ; + signal iu2_dir_dataout_3_l2_b , dir3_q , dir3_si, dir3_so , dir3_slow_b :std_ulogic_vector(0 to 30) ; + signal dir_eq_b :std_ulogic_vector(0 to 3); + + signal dir_val_le_b, le_cmp :std_ulogic_vector(0 to 3) ; +-- synopsys translate_off + +-- synopsys translate_on + + + signal erat_i1_b :std_ulogic_vector(0 to 29) ; +-- synopsys translate_off +-- synopsys translate_on + + + +-- synopsys translate_off +-- synopsys translate_on + + + signal iu2_rd_way_hit_0 :std_ulogic_vector(0 to 3) ; + signal iu2_rd_way_hit_1x_b :std_ulogic_vector(0 to 3) ; + signal iu2_rd_way_hit_1y_b :std_ulogic_vector(0 to 3) ; + signal iu2_rd_way_hit_2x :std_ulogic_vector(0 to 3) ; +-- synopsys translate_off +-- synopsys translate_on + +begin + + + u_dir0_q: dir0_q(0 to 30) <= not( iu2_dir_dataout_0_l2_b(0 to 30) ); + u_dir1_q: dir1_q(0 to 30) <= not( iu2_dir_dataout_1_l2_b(0 to 30) ); + u_dir2_q: dir2_q(0 to 30) <= not( iu2_dir_dataout_2_l2_b(0 to 30) ); + u_dir3_q: dir3_q(0 to 30) <= not( iu2_dir_dataout_3_l2_b(0 to 30) ); + + u_dir0_slowi: dir0_slow_b(0 to 30) <= not( dir0_q(0 to 30) ); + u_dir1_slowi: dir1_slow_b(0 to 30) <= not( dir1_q(0 to 30) ); + u_dir2_slowi: dir2_slow_b(0 to 30) <= not( dir2_q(0 to 30) ); + u_dir3_slowi: dir3_slow_b(0 to 30) <= not( dir3_q(0 to 30) ); + + iu2_dir_dataout_0_noncmp(22 to 52) <= not dir0_slow_b(0 to 30) ; + iu2_dir_dataout_1_noncmp(22 to 52) <= not dir1_slow_b(0 to 30) ; + iu2_dir_dataout_2_noncmp(22 to 52) <= not dir2_slow_b(0 to 30) ; + iu2_dir_dataout_3_noncmp(22 to 52) <= not dir3_slow_b(0 to 30) ; + + u_erat_i1: erat_i1_b(0 to 29) <= not( ierat_iu_iu2_rpn(22 to 51) ); + + + ierat_iu_iu2_rpn_noncmp(22 to 51) <= ierat_iu_iu2_rpn(22 to 51); + + + cmp0: entity work.iuq_ic_dir_cmp30(iuq_ic_dir_cmp30) port map( + d0_b(0 to 29) => erat_i1_b (0 to 29) , + d1 (0 to 29) => dir0_q (0 to 29) , + eq_b => dir_eq_b(0) ); + + cmp1: entity work.iuq_ic_dir_cmp30(iuq_ic_dir_cmp30) port map( + d0_b(0 to 29) => erat_i1_b (0 to 29) , + d1 (0 to 29) => dir1_q (0 to 29) , + eq_b => dir_eq_b(1) ); + + cmp2: entity work.iuq_ic_dir_cmp30(iuq_ic_dir_cmp30) port map( + d0_b(0 to 29) => erat_i1_b (0 to 29) , + d1 (0 to 29) => dir2_q (0 to 29) , + eq_b => dir_eq_b(2) ); + + cmp3: entity work.iuq_ic_dir_cmp30(iuq_ic_dir_cmp30) port map( + d0_b(0 to 29) => erat_i1_b (0 to 29) , + d1 (0 to 29) => dir3_q (0 to 29) , + eq_b => dir_eq_b(3) ); + + + + u_match30: iu2_rd_way_tag_hit(0 to 3) <= not( dir_eq_b(0 to 3) ); + u_match31: iu2_rd_way_hit_0(0 to 3) <= not( dir_eq_b(0 to 3) or dir_val_le_b(0 to 3) ); + + u_match31_1x: iu2_rd_way_hit_1x_b (0 to 3) <= not( iu2_rd_way_hit_0(0 to 3) ) ; + u_match31_1y: iu2_rd_way_hit_1y_b (0 to 3) <= not( iu2_rd_way_hit_0(0 to 3) ) ; + + u_match31_2x: iu2_rd_way_hit_2x (0 to 3) <= not( iu2_rd_way_hit_1x_b(0 to 3) ) ; + iu2_rd_way_hit (0 to 3) <= not( iu2_rd_way_hit_1y_b(0 to 3) ); + + u_match31_3x: iu2_rd_way_hit_insmux_b(0 to 3) <= not( iu2_rd_way_hit_2x (0 to 3) ) ; + + + + + dir_val_le_b(0 to 3) <= not( iu2_dir_rd_val(0 to 3) and le_cmp(0 to 3) ); + + le_cmp(0) <= ( dir0_q(30) xnor iu2_endian ); + le_cmp(1) <= ( dir1_q(30) xnor iu2_endian ); + le_cmp(2) <= ( dir2_q(30) xnor iu2_endian ); + le_cmp(3) <= ( dir3_q(30) xnor iu2_endian ); + + + + iu2_dir_dataout_0_lat: entity tri.tri_inv_nlats generic map (width => 31, btr=> "NLI0001_X2_A12TH", needs_sreset => 0, expand_type => expand_type) port map ( + VD => vdd , + GD => gnd , + LCLK => dir_lclk , + D1CLK => dir_d1clk , + D2CLK => dir_d2clk , + SCANIN => dir0_si , + SCANOUT => dir0_so , + D => iu2_dir_dataout_0_d(22 to 52) , + QB => iu2_dir_dataout_0_l2_b(0 to 30) ); + + iu2_dir_dataout_1_lat: entity tri.tri_inv_nlats generic map (width => 31, btr=> "NLI0001_X2_A12TH", needs_sreset => 0, expand_type => expand_type) port map ( + VD => vdd , + GD => gnd , + LCLK => dir_lclk , + D1CLK => dir_d1clk , + D2CLK => dir_d2clk , + SCANIN => dir1_si , + SCANOUT => dir1_so , + D => iu2_dir_dataout_1_d(22 to 52) , + QB => iu2_dir_dataout_1_l2_b(0 to 30) ); + + iu2_dir_dataout_2_lat: entity tri.tri_inv_nlats generic map (width => 31, btr=> "NLI0001_X2_A12TH", needs_sreset => 0, expand_type => expand_type) port map ( + VD => vdd , + GD => gnd , + LCLK => dir_lclk , + D1CLK => dir_d1clk , + D2CLK => dir_d2clk , + SCANIN => dir2_si , + SCANOUT => dir2_so , + D => iu2_dir_dataout_2_d(22 to 52) , + QB => iu2_dir_dataout_2_l2_b(0 to 30) ); + + iu2_dir_dataout_3_lat: entity tri.tri_inv_nlats generic map (width => 31, btr=> "NLI0001_X2_A12TH", needs_sreset => 0, expand_type => expand_type) port map ( + VD => vdd , + GD => gnd , + LCLK => dir_lclk , + D1CLK => dir_d1clk , + D2CLK => dir_d2clk , + SCANIN => dir3_si , + SCANOUT => dir3_so , + D => iu2_dir_dataout_3_d(22 to 52) , + QB => iu2_dir_dataout_3_l2_b(0 to 30) ); + + + dir0_si(0 to 30) <= scan_in & dir0_so(0 to 29); + dir1_si(0 to 30) <= dir1_so(1 to 30) & dir0_so(30); + dir2_si(0 to 30) <= dir1_so(0) & dir2_so(0 to 29) ; + dir3_si(0 to 30) <= dir3_so(1 to 30) & dir2_so(30) ; + scan_out <= dir3_so(0) ; + + + dir_lcb : tri_lcbnd generic map (expand_type => expand_type) port map( + nclk => nclk , + vd => vdd , + gd => gnd , + act => dir_dataout_act , + delay_lclkr => delay_lclkr , + mpw1_b => mpw1_b , + mpw2_b => mpw2_b , + forcee => forcee, + sg => sg_0 , + thold_b => thold_0_b , + d1clk => dir_d1clk , + d2clk => dir_d2clk , + lclk => dir_lclk ); + + + + + + +end; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_ic_dir_cmp30.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_ic_dir_cmp30.vhdl new file mode 100644 index 0000000..183bc0d --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_ic_dir_cmp30.vhdl @@ -0,0 +1,129 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + + + +LIBRARY ieee; USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY ibm; + USE ibm.std_ulogic_support.all; + USE ibm.std_ulogic_unsigned.all; + USE ibm.std_ulogic_function_support.all; +LIBRARY support; + USE support.power_logic_pkg.all; +LIBRARY tri; USE tri.tri_latches_pkg.all; + + +entity iuq_ic_dir_cmp30 is +generic( expand_type: integer := 2 ); +port( + d0_b :in std_ulogic_vector(0 to 29); + d1 :in std_ulogic_vector(0 to 29); + eq_b :out std_ulogic +); + +-- synopsys translate_off + +-- synopsys translate_on + + + +end iuq_ic_dir_cmp30; + +architecture iuq_ic_dir_cmp30 of iuq_ic_dir_cmp30 is + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal eq01 :std_ulogic_vector(0 to 29) ; +-- synopsys translate_off +-- synopsys translate_on + + signal eq02_b : std_ulogic_vector(0 to 14); + signal eq04 : std_ulogic_vector(0 to 7); + signal eq08_b : std_ulogic_vector(0 to 3); + signal eq16 : std_ulogic_vector(0 to 1); + +-- synopsys translate_off + + + + + + +-- synopsys translate_on + + +begin + + + u_eq01: eq01(0 to 29) <= ( d0_b(0 to 29) xor d1(0 to 29) ); + + + u_00_eq02: eq02_b( 0) <= not( eq01 ( 0) and eq01 ( 1) ); + u_02_eq02: eq02_b( 1) <= not( eq01 ( 2) and eq01 ( 3) ); + u_04_eq02: eq02_b( 2) <= not( eq01 ( 4) and eq01 ( 5) ); + u_06_eq02: eq02_b( 3) <= not( eq01 ( 6) and eq01 ( 7) ); + u_08_eq02: eq02_b( 4) <= not( eq01 ( 8) and eq01 ( 9) ); + u_10_eq02: eq02_b( 5) <= not( eq01 (10) and eq01 (11) ); + u_12_eq02: eq02_b( 6) <= not( eq01 (12) and eq01 (13) ); + u_14_eq02: eq02_b( 7) <= not( eq01 (14) and eq01 (15) ); + u_16_eq02: eq02_b( 8) <= not( eq01 (16) and eq01 (17) ); + u_18_eq02: eq02_b( 9) <= not( eq01 (18) and eq01 (19) ); + u_20_eq02: eq02_b(10) <= not( eq01 (20) and eq01 (21) ); + u_22_eq02: eq02_b(11) <= not( eq01 (22) and eq01 (23) ); + u_24_eq02: eq02_b(12) <= not( eq01 (24) and eq01 (25) ); + u_26_eq02: eq02_b(13) <= not( eq01 (26) and eq01 (27) ); + u_28_eq02: eq02_b(14) <= not( eq01 (28) and eq01 (29) ); + + u_01_eq04: eq04 ( 0) <= not( eq02_b( 0) or eq02_b( 1) ); + u_05_eq04: eq04 ( 1) <= not( eq02_b( 2) or eq02_b( 3) ); + u_09_eq04: eq04 ( 2) <= not( eq02_b( 4) or eq02_b( 5) ); + u_13_eq04: eq04 ( 3) <= not( eq02_b( 6) or eq02_b( 7) ); + u_17_eq04: eq04 ( 4) <= not( eq02_b( 8) or eq02_b( 9) ); + u_21_eq04: eq04 ( 5) <= not( eq02_b(10) or eq02_b(11) ); + u_25_eq04: eq04 ( 6) <= not( eq02_b(12) or eq02_b(13) ); + u_29_eq04: eq04 ( 7) <= not( eq02_b(14) ); + + u_03_eq08: eq08_b( 0) <= not( eq04 ( 0) and eq04 ( 1) ); + u_11_eq08: eq08_b( 1) <= not( eq04 ( 2) and eq04 ( 3) ); + u_19_eq08: eq08_b( 2) <= not( eq04 ( 4) and eq04 ( 5) ); + u_27_eq08: eq08_b( 3) <= not( eq04 ( 6) and eq04 ( 7) ); + + u_07_eq16: eq16 ( 0) <= not( eq08_b( 0) or eq08_b( 1) ); + u_23_eq16: eq16 ( 1) <= not( eq08_b( 2) or eq08_b( 3) ); + + u_15_eq32: eq_b <= not( eq16 ( 0) and eq16 ( 1) ); + +end; + + + + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_ic_ierat.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_ic_ierat.vhdl new file mode 100644 index 0000000..e3aa2e3 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_ic_ierat.vhdl @@ -0,0 +1,6225 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library ibm; +use ibm.std_ulogic_unsigned.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_support.all; +library support; +use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity iuq_ic_ierat is + generic(thdid_width : integer := 4; + ttype_width : integer := 6; + state_width : integer := 4; + pid_width : integer := 14; + pid_width_erat : integer := 8; + extclass_width : integer := 2; + tlbsel_width : integer := 2; + epn_width : integer := 52; + vpn_width : integer := 61; + rpn_width : integer := 30; + ws_width : integer := 2; + rs_is_width : integer := 9; + ra_entry_width : integer := 4; + rs_data_width : integer := 64; + data_out_width : integer := 64; + error_width : integer := 3; + cam_data_width : natural := 84; + array_data_width : natural := 68; + num_entry : natural := 16; + num_entry_log2 : natural := 4; + por_seq_width : integer := 3; + watermark_width : integer := 4; + eptr_width : integer := 4; + lru_width : integer := 15; + bcfg_width : integer := 123; + bcfg_epn_0to15 : integer := 0; + bcfg_epn_16to31 : integer := 0; + bcfg_epn_32to47 : integer := (2**16)-1; + bcfg_epn_48to51 : integer := (2**4)-1; + bcfg_rpn_22to31 : integer := (2**10)-1; + bcfg_rpn_32to47 : integer := (2**16)-1; + bcfg_rpn_48to51 : integer := (2**4)-1; + bcfg_rpn2_32to47 : integer := 0; + bcfg_rpn2_48to51 : integer := 0; + bcfg_attr : integer := 0; + check_parity : integer := 1; + expand_type : integer := 2 ); +port( + gnd : inout power_logic; + vdd : inout power_logic; + vcs : inout power_logic; + nclk : in clk_logic; + pc_iu_init_reset : in std_ulogic; + +tc_ccflush_dc : in std_ulogic; +tc_scan_dis_dc_b : in std_ulogic; +tc_scan_diag_dc : in std_ulogic; +tc_lbist_en_dc : in std_ulogic; +an_ac_atpg_en_dc : in std_ulogic; +an_ac_grffence_en_dc : in std_ulogic; +lcb_d_mode_dc : in std_ulogic; +lcb_clkoff_dc_b : in std_ulogic; +lcb_act_dis_dc : in std_ulogic; +lcb_mpw1_dc_b : in std_ulogic_vector(0 to 1); +lcb_mpw2_dc_b : in std_ulogic; +lcb_delay_lclkr_dc : in std_ulogic_vector(0 to 1); +pc_iu_func_sl_thold_2 : in std_ulogic; +pc_iu_func_slp_sl_thold_2 : in std_ulogic; +pc_iu_func_slp_nsl_thold_2 : in std_ulogic; +pc_iu_cfg_slp_sl_thold_2 : in std_ulogic; +pc_iu_regf_slp_sl_thold_2 : in std_ulogic; +pc_iu_time_sl_thold_2 : in std_ulogic; +pc_iu_sg_2 : in std_ulogic; +pc_iu_fce_2 : in std_ulogic; +cam_clkoff_b : in std_ulogic; +cam_act_dis : in std_ulogic; +cam_d_mode : in std_ulogic; +cam_delay_lclkr : in std_ulogic_vector(0 to 4); +cam_mpw1_b : in std_ulogic_vector(0 to 4); +cam_mpw2_b : in std_ulogic; +ac_func_scan_in : in std_ulogic_vector(0 to 1); +ac_func_scan_out : out std_ulogic_vector(0 to 1); +ac_ccfg_scan_in : in std_ulogic; +ac_ccfg_scan_out : out std_ulogic; +func_scan_in_cam : in std_ulogic; +func_scan_out_cam : out std_ulogic; +time_scan_in : in std_ulogic; +time_scan_out : out std_ulogic; +regf_scan_in : in std_ulogic_vector(0 to 4); +regf_scan_out : out std_ulogic_vector(0 to 4); +iu_ierat_iu0_val : in std_ulogic; +iu_ierat_iu0_thdid : in std_ulogic_vector(0 to thdid_width-1); +iu_ierat_iu0_ifar : in std_ulogic_vector(0 to 51); +iu_ierat_iu0_flush : in std_ulogic_vector(0 to thdid_width-1); +iu_ierat_iu1_flush : in std_ulogic_vector(0 to thdid_width-1); +iu_ierat_iu1_back_inv : in std_ulogic; +iu_ierat_ium1_back_inv : in std_ulogic; +spr_ic_clockgate_dis : in std_ulogic; +ierat_iu_iu2_rpn : out std_ulogic_vector(22 to 51); +ierat_iu_iu2_wimge : out std_ulogic_vector(0 to 4); +ierat_iu_iu2_u : out std_ulogic_vector(0 to 3); +ierat_iu_iu2_error : out std_ulogic_vector(0 to 2); +ierat_iu_iu2_miss : out std_ulogic; +ierat_iu_iu2_multihit : out std_ulogic; +ierat_iu_iu2_isi : out std_ulogic; +xu_iu_rf1_val : in std_ulogic_vector(0 to thdid_width-1); +xu_iu_rf1_is_eratre : in std_ulogic; +xu_iu_rf1_is_eratwe : in std_ulogic; +xu_iu_rf1_is_eratsx : in std_ulogic; +xu_iu_rf1_is_eratilx : in std_ulogic; +xu_iu_ex1_is_isync : in std_ulogic; +xu_iu_ex1_is_csync : in std_ulogic; +xu_iu_rf1_ws : in std_ulogic_vector(0 to ws_width-1); +xu_iu_rf1_t : in std_ulogic_vector(0 to 2); +xu_iu_ex1_rs_is : in std_ulogic_vector(0 to rs_is_width-1); +xu_iu_ex1_ra_entry : in std_ulogic_vector(0 to ra_entry_width-1); +xu_iu_ex1_rb : in std_ulogic_vector(64-rs_data_width to 51); +xu_iu_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_rf1_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_ex1_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_ex2_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_ex3_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_ex4_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_ex5_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_iu_ex4_rs_data : in std_ulogic_vector(64-rs_data_width to 63); +xu_iu_msr_hv : in std_ulogic_vector(0 to thdid_width-1); +xu_iu_msr_pr : in std_ulogic_vector(0 to thdid_width-1); +xu_iu_msr_is : in std_ulogic_vector(0 to thdid_width-1); +xu_iu_msr_cm : in std_ulogic_vector(0 to thdid_width-1); +xu_iu_hid_mmu_mode : in std_ulogic; +xu_iu_spr_ccr2_ifrat : in std_ulogic; +xu_iu_spr_ccr2_ifratsc : in std_ulogic_vector(0 to 8); +xu_iu_xucr4_mmu_mchk : in std_ulogic; +ierat_iu_hold_req : out std_ulogic_vector(0 to thdid_width-1); +ierat_iu_iu2_flush_req : out std_ulogic_vector(0 to thdid_width-1); +iu_xu_ex4_data : out std_ulogic_vector(64-data_out_width to 63); +iu_xu_ierat_ex3_par_err : out std_ulogic_vector(0 to thdid_width-1); +iu_xu_ierat_ex4_par_err : out std_ulogic_vector(0 to thdid_width-1); +iu_xu_ierat_ex2_flush_req : out std_ulogic_vector(0 to thdid_width-1); +iu_mm_ierat_req : out std_ulogic; +iu_mm_ierat_thdid : out std_ulogic_vector(0 to thdid_width-1); +iu_mm_ierat_state : out std_ulogic_vector(0 to state_width-1); +iu_mm_ierat_tid : out std_ulogic_vector(0 to pid_width-1); +iu_mm_ierat_flush : out std_ulogic_vector(0 to thdid_width-1); +mm_iu_ierat_rel_val : in std_ulogic_vector(0 to 4); +mm_iu_ierat_rel_data : in std_ulogic_vector(0 to 131); +mm_iu_ierat_pid0 : in std_ulogic_vector(0 to pid_width-1); +mm_iu_ierat_pid1 : in std_ulogic_vector(0 to pid_width-1); +mm_iu_ierat_pid2 : in std_ulogic_vector(0 to pid_width-1); +mm_iu_ierat_pid3 : in std_ulogic_vector(0 to pid_width-1); +mm_iu_ierat_mmucr0_0 : in std_ulogic_vector(0 to 19); +mm_iu_ierat_mmucr0_1 : in std_ulogic_vector(0 to 19); +mm_iu_ierat_mmucr0_2 : in std_ulogic_vector(0 to 19); +mm_iu_ierat_mmucr0_3 : in std_ulogic_vector(0 to 19); +iu_mm_ierat_mmucr0 : out std_ulogic_vector(0 to 17); +iu_mm_ierat_mmucr0_we : out std_ulogic_vector(0 to 3); +mm_iu_ierat_mmucr1 : in std_ulogic_vector(0 to 8); +iu_mm_ierat_mmucr1 : out std_ulogic_vector(0 to 3); +iu_mm_ierat_mmucr1_we : out std_ulogic; +mm_iu_ierat_snoop_coming : in std_ulogic; +mm_iu_ierat_snoop_val : in std_ulogic; +mm_iu_ierat_snoop_attr : in std_ulogic_vector(0 to 25); +mm_iu_ierat_snoop_vpn : in std_ulogic_vector(52-epn_width to 51); +iu_mm_ierat_snoop_ack : out std_ulogic; +pc_iu_trace_bus_enable : in std_ulogic; +ierat_iu_debug_group0 : out std_ulogic_vector(0 to 87); +ierat_iu_debug_group1 : out std_ulogic_vector(0 to 87); +ierat_iu_debug_group2 : out std_ulogic_vector(0 to 87); +ierat_iu_debug_group3 : out std_ulogic_vector(0 to 87) + +); +end iuq_ic_ierat; +ARCHITECTURE IUQ_IC_IERAT + OF IUQ_IC_IERAT + IS +SIGNAL CAM_MASK_BITS_PT : STD_ULOGIC_VECTOR(1 TO 19) := +(OTHERS=> 'U'); +SIGNAL IU1_FIRST_HIT_ENTRY_PT : STD_ULOGIC_VECTOR(1 TO 15) := +(OTHERS=> 'U'); +SIGNAL IU1_MULTIHIT_B_PT : STD_ULOGIC_VECTOR(1 TO 16) := +(OTHERS=> 'U'); +SIGNAL LRU_RMT_VEC_PT : STD_ULOGIC_VECTOR(1 TO 17) := +(OTHERS=> 'U'); +SIGNAL LRU_SET_RESET_VEC_PT : STD_ULOGIC_VECTOR(1 TO 80) := +(OTHERS=> 'U'); +SIGNAL LRU_WATERMARK_MASK_PT : STD_ULOGIC_VECTOR(1 TO 15) := +(OTHERS=> 'U'); +SIGNAL LRU_WAY_ENCODE_PT : STD_ULOGIC_VECTOR(1 TO 15) := +(OTHERS=> 'U'); +component tri_cam_16x143_1r1w1c + generic (expand_type : integer := 2); + port ( + gnd : inout power_logic; + vdd : inout power_logic; + vcs : inout power_logic; + nclk : in clk_logic; + tc_ccflush_dc : in std_ulogic; + tc_scan_dis_dc_b : in std_ulogic; + tc_scan_diag_dc : in std_ulogic; + tc_lbist_en_dc : in std_ulogic; + an_ac_atpg_en_dc : in std_ulogic; + + lcb_d_mode_dc : in std_ulogic; + lcb_clkoff_dc_b : in std_ulogic; + lcb_act_dis_dc : in std_ulogic; + lcb_mpw1_dc_b : in std_ulogic_vector(0 to 3); + lcb_mpw2_dc_b : in std_ulogic; + lcb_delay_lclkr_dc : in std_ulogic_vector(0 to 3); + + pc_sg_2 : in std_ulogic; + pc_func_slp_sl_thold_2 : in std_ulogic; + pc_func_slp_nsl_thold_2 : in std_ulogic; + pc_regf_slp_sl_thold_2 : in std_ulogic; + pc_time_sl_thold_2 : in std_ulogic; + pc_fce_2 : in std_ulogic; + + func_scan_in : in std_ulogic; + func_scan_out : out std_ulogic; + regfile_scan_in : in std_ulogic_vector(0 to 4); + regfile_scan_out : out std_ulogic_vector(0 to 4); + time_scan_in : in std_ulogic; + time_scan_out : out std_ulogic; + + + rd_val : in std_ulogic; + rd_val_late : in std_ulogic; + rw_entry : in std_ulogic_vector(0 to 3); + + wr_array_data : in std_ulogic_vector(0 to array_data_width-1); + wr_cam_data : in std_ulogic_vector(0 to cam_data_width-1); + wr_array_val : in std_ulogic_vector(0 to 1); + wr_cam_val : in std_ulogic_vector(0 to 1); + wr_val_early : in std_ulogic; + + comp_request : in std_ulogic; + comp_addr : in std_ulogic_vector(0 to 51); + addr_enable : in std_ulogic_vector(0 to 1); + comp_pgsize : in std_ulogic_vector(0 to 2); + pgsize_enable : in std_ulogic; + comp_class : in std_ulogic_vector(0 to 1); + class_enable : in std_ulogic_vector(0 to 2); + comp_extclass : in std_ulogic_vector(0 to 1); + extclass_enable : in std_ulogic_vector(0 to 1); + comp_state : in std_ulogic_vector(0 to 1); + state_enable : in std_ulogic_vector(0 to 1); + comp_thdid : in std_ulogic_vector(0 to 3); + thdid_enable : in std_ulogic_vector(0 to 1); + comp_pid : in std_ulogic_vector(0 to 7); + pid_enable : in std_ulogic; + comp_invalidate : in std_ulogic; + flash_invalidate : in std_ulogic; + + array_cmp_data : out std_ulogic_vector(0 to array_data_width-1); + rd_array_data : out std_ulogic_vector(0 to array_data_width-1); + + cam_cmp_data : out std_ulogic_vector(0 to cam_data_width-1); + cam_hit : out std_ulogic; + cam_hit_entry : out std_ulogic_vector(0 to 3); + entry_match : out std_ulogic_vector(0 to 15); + entry_valid : out std_ulogic_vector(0 to 15); + rd_cam_data : out std_ulogic_vector(0 to cam_data_width-1); + + bypass_mux_enab_np1 : in std_ulogic; + bypass_attr_np1 : in std_ulogic_vector(0 to 20); + attr_np2 : out std_ulogic_vector(0 to 20); + rpn_np2 : out std_ulogic_vector(22 to 51) + + ); +END component; +constant MMU_Mode_Value : std_ulogic := '0'; +constant TlbSel_Tlb : std_ulogic_vector(0 to 1) := "00"; +constant TlbSel_IErat : std_ulogic_vector(0 to 1) := "10"; +constant TlbSel_DErat : std_ulogic_vector(0 to 1) := "11"; +constant CAM_PgSize_1GB : std_ulogic_vector(0 to 2) := "110"; +constant CAM_PgSize_16MB : std_ulogic_vector(0 to 2) := "111"; +constant CAM_PgSize_1MB : std_ulogic_vector(0 to 2) := "101"; +constant CAM_PgSize_64KB : std_ulogic_vector(0 to 2) := "011"; +constant CAM_PgSize_4KB : std_ulogic_vector(0 to 2) := "001"; +constant WS0_PgSize_1GB : std_ulogic_vector(0 to 3) := "1010"; +constant WS0_PgSize_16MB : std_ulogic_vector(0 to 3) := "0111"; +constant WS0_PgSize_1MB : std_ulogic_vector(0 to 3) := "0101"; +constant WS0_PgSize_64KB : std_ulogic_vector(0 to 3) := "0011"; +constant WS0_PgSize_4KB : std_ulogic_vector(0 to 3) := "0001"; +constant eratpos_epn : natural := 0; +constant eratpos_x : natural := 52; +constant eratpos_size : natural := 53; +constant eratpos_v : natural := 56; +constant eratpos_thdid : natural := 57; +constant eratpos_class : natural := 61; +constant eratpos_extclass : natural := 63; +constant eratpos_wren : natural := 65; +constant eratpos_rpnrsvd : natural := 66; +constant eratpos_rpn : natural := 70; +constant eratpos_r : natural := 100; +constant eratpos_c : natural := 101; +constant eratpos_relsoon : natural := 102; +constant eratpos_wlc : natural := 103; +constant eratpos_resvattr : natural := 105; +constant eratpos_vf : natural := 106; +constant eratpos_ubits : natural := 107; +constant eratpos_wimge : natural := 111; +constant eratpos_usxwr : natural := 116; +constant eratpos_gs : natural := 122; +constant eratpos_ts : natural := 123; +constant eratpos_tid : natural := 124; +constant PorSeq_Idle : std_ulogic_vector(0 to 2) := "000"; +constant PorSeq_Stg1 : std_ulogic_vector(0 to 2) := "001"; +constant PorSeq_Stg2 : std_ulogic_vector(0 to 2) := "011"; +constant PorSeq_Stg3 : std_ulogic_vector(0 to 2) := "010"; +constant PorSeq_Stg4 : std_ulogic_vector(0 to 2) := "110"; +constant PorSeq_Stg5 : std_ulogic_vector(0 to 2) := "100"; +constant PorSeq_Stg6 : std_ulogic_vector(0 to 2) := "101"; +constant PorSeq_Stg7 : std_ulogic_vector(0 to 2) := "111"; +constant Por_Wr_Entry_Num1 : std_ulogic_vector(0 to num_entry_log2-1) := "1110"; +constant Por_Wr_Entry_Num2 : std_ulogic_vector(0 to num_entry_log2-1) := "1111"; +constant Por_Wr_Cam_Data1 : std_ulogic_vector(0 to 83) := "0000000000000000000000000000000011111111111111111111" & + '0' & "001" & '1' & "1111" & "00" & "00" & "00" & "00000000" & "11110000" & '0'; +constant Por_Wr_Cam_Data2 : std_ulogic_vector(0 to 83) := "0000000000000000000000000000000000000000000000000000" & + '0' & "001" & '1' & "1111" & "00" & "10" & "00" & "00000000" & "11110000" & '0'; +constant Por_Wr_Array_Data1 : std_ulogic_vector(0 to 67) := "111111111111111111111111111111" & + "00" & "0000" & "0000" & "01010" & "01" & "00" & "01" & "0000001000" & "0000000"; +constant Por_Wr_Array_Data2 : std_ulogic_vector(0 to 67) := "000000000000000000000000000000" & + "00" & "0000" & "0000" & "01010" & "01" & "00" & "01" & "0000001010" & "0000000"; +constant ex1_valid_offset : natural := 0; +constant ex1_ttype_offset : natural := ex1_valid_offset + thdid_width; +constant ex1_ws_offset : natural := ex1_ttype_offset + ttype_width+1; +constant ex1_rs_is_offset : natural := ex1_ws_offset + ws_width; +constant ex1_ra_entry_offset : natural := ex1_rs_is_offset + rs_is_width; +constant ex1_state_offset : natural := ex1_ra_entry_offset + ra_entry_width; +constant ex1_pid_offset : natural := ex1_state_offset + state_width; +constant ex1_extclass_offset : natural := ex1_pid_offset + pid_width; +constant ex1_tlbsel_offset : natural := ex1_extclass_offset + extclass_width; +constant ex2_valid_offset : natural := ex1_tlbsel_offset + tlbsel_width; +constant ex2_ttype_offset : natural := ex2_valid_offset + thdid_width; +constant ex2_ws_offset : natural := ex2_ttype_offset + ttype_width; +constant ex2_rs_is_offset : natural := ex2_ws_offset + ws_width; +constant ex2_ra_entry_offset : natural := ex2_rs_is_offset + rs_is_width; +constant ex2_state_offset : natural := ex2_ra_entry_offset + ra_entry_width; +constant ex2_pid_offset : natural := ex2_state_offset + state_width; +constant ex2_extclass_offset : natural := ex2_pid_offset + pid_width; +constant ex2_tlbsel_offset : natural := ex2_extclass_offset + extclass_width; +constant ex3_valid_offset : natural := ex2_tlbsel_offset + tlbsel_width; +constant ex3_ttype_offset : natural := ex3_valid_offset + thdid_width; +constant ex3_ws_offset : natural := ex3_ttype_offset + ttype_width; +constant ex3_rs_is_offset : natural := ex3_ws_offset + ws_width; +constant ex3_ra_entry_offset : natural := ex3_rs_is_offset + rs_is_width; +constant ex3_state_offset : natural := ex3_ra_entry_offset + ra_entry_width; +constant ex3_pid_offset : natural := ex3_state_offset + state_width; +constant ex3_extclass_offset : natural := ex3_pid_offset + pid_width; +constant ex3_tlbsel_offset : natural := ex3_extclass_offset + extclass_width; +constant ex3_eratsx_data_offset : natural := ex3_tlbsel_offset + tlbsel_width; +constant ex4_valid_offset : natural := ex3_eratsx_data_offset + 2 + num_entry_log2; +constant ex4_ttype_offset : natural := ex4_valid_offset + thdid_width; +constant ex4_ws_offset : natural := ex4_ttype_offset + ttype_width; +constant ex4_rs_is_offset : natural := ex4_ws_offset + ws_width; +constant ex4_ra_entry_offset : natural := ex4_rs_is_offset + rs_is_width; +constant ex4_state_offset : natural := ex4_ra_entry_offset + ra_entry_width; +constant ex4_pid_offset : natural := ex4_state_offset + state_width; +constant ex4_extclass_offset : natural := ex4_pid_offset + pid_width; +constant ex4_tlbsel_offset : natural := ex4_extclass_offset + extclass_width; +constant ex4_data_out_offset : natural := ex4_tlbsel_offset + tlbsel_width; +constant ex5_valid_offset : natural := ex4_data_out_offset + data_out_width; +constant ex5_ttype_offset : natural := ex5_valid_offset + thdid_width; +constant ex5_ws_offset : natural := ex5_ttype_offset + ttype_width; +constant ex5_rs_is_offset : natural := ex5_ws_offset + ws_width; +constant ex5_ra_entry_offset : natural := ex5_rs_is_offset + rs_is_width; +constant ex5_state_offset : natural := ex5_ra_entry_offset + ra_entry_width; +constant ex5_pid_offset : natural := ex5_state_offset + state_width; +constant ex5_extclass_offset : natural := ex5_pid_offset + pid_width; +constant ex5_tlbsel_offset : natural := ex5_extclass_offset + extclass_width; +constant ex5_data_in_offset : natural := ex5_tlbsel_offset + tlbsel_width; +constant ex6_valid_offset : natural := ex5_data_in_offset + rs_data_width; +constant ex6_ttype_offset : natural := ex6_valid_offset + thdid_width; +constant ex6_ws_offset : natural := ex6_ttype_offset + ttype_width; +constant ex6_rs_is_offset : natural := ex6_ws_offset + ws_width; +constant ex6_ra_entry_offset : natural := ex6_rs_is_offset + rs_is_width; +constant ex6_state_offset : natural := ex6_ra_entry_offset + ra_entry_width; +constant ex6_pid_offset : natural := ex6_state_offset + state_width; +constant ex6_extclass_offset : natural := ex6_pid_offset + pid_width; +constant ex6_tlbsel_offset : natural := ex6_extclass_offset + extclass_width; +constant ex6_data_in_offset : natural := ex6_tlbsel_offset + tlbsel_width; +constant iu1_flush_enab_offset : natural := ex6_data_in_offset + rs_data_width; +constant iu2_n_flush_req_offset : natural := iu1_flush_enab_offset + 1; +constant hold_req_offset : natural := iu2_n_flush_req_offset + thdid_width; +constant tlb_miss_offset : natural := hold_req_offset + thdid_width; +constant tlb_req_inprogress_offset : natural := tlb_miss_offset + thdid_width; +constant iu1_valid_offset : natural := tlb_req_inprogress_offset + thdid_width; +constant iu1_state_offset : natural := iu1_valid_offset + thdid_width; +constant iu1_pid_offset : natural := iu1_state_offset + state_width; +constant iu2_valid_offset : natural := iu1_pid_offset + pid_width; +constant iu2_state_offset : natural := iu2_valid_offset + thdid_width; +constant iu2_pid_offset : natural := iu2_state_offset + state_width; +constant iu2_miss_offset : natural := iu2_pid_offset + pid_width; +constant iu2_multihit_offset : natural := iu2_miss_offset + 2; +constant iu2_parerr_offset : natural := iu2_multihit_offset + 2; +constant iu2_isi_offset : natural := iu2_parerr_offset + 2; +constant iu2_tlbreq_offset : natural := iu2_isi_offset + 6; +constant iu2_multihit_b_pt_offset : natural := iu2_tlbreq_offset + 1; +constant iu2_first_hit_entry_pt_offset : natural := iu2_multihit_b_pt_offset + num_entry; +constant iu2_cam_cmp_data_offset : natural := iu2_first_hit_entry_pt_offset + num_entry-1; +constant iu2_array_cmp_data_offset : natural := iu2_cam_cmp_data_offset + cam_data_width; +constant ex4_rd_cam_data_offset : natural := iu2_array_cmp_data_offset + array_data_width; +constant ex4_rd_array_data_offset : natural := ex4_rd_cam_data_offset + cam_data_width; +constant ex3_parerr_offset : natural := ex4_rd_array_data_offset + array_data_width; +constant ex4_parerr_offset : natural := ex3_parerr_offset + thdid_width + 1; +constant ex4_ieen_offset : natural := ex4_parerr_offset + thdid_width + 2; +constant ex5_ieen_offset : natural := ex4_ieen_offset + thdid_width + num_entry_log2; +constant ex6_ieen_offset : natural := ex5_ieen_offset + thdid_width + num_entry_log2; +constant mmucr1_offset : natural := ex6_ieen_offset + 1 + num_entry_log2; +constant rpn_holdreg0_offset : natural := mmucr1_offset + 9; +constant rpn_holdreg1_offset : natural := rpn_holdreg0_offset + 64; +constant rpn_holdreg2_offset : natural := rpn_holdreg1_offset + 64; +constant rpn_holdreg3_offset : natural := rpn_holdreg2_offset + 64; +constant entry_valid_offset : natural := rpn_holdreg3_offset + 64; +constant entry_match_offset : natural := entry_valid_offset + 16; +constant watermark_offset : natural := entry_match_offset + 16; +constant eptr_offset : natural := watermark_offset + watermark_width; +constant lru_offset : natural := eptr_offset + eptr_width; +constant lru_update_event_offset : natural := lru_offset + lru_width; +constant lru_debug_offset : natural := lru_update_event_offset + 9; +constant scan_right_0 : natural := lru_debug_offset + 24 -1; +constant snoop_val_offset : natural := 0; +constant spare_a_offset : natural := snoop_val_offset + 3; +constant snoop_attr_offset : natural := spare_a_offset + 16; +constant snoop_addr_offset : natural := snoop_attr_offset + 26; +constant spare_b_offset : natural := snoop_addr_offset + epn_width; +constant por_seq_offset : natural := spare_b_offset + 16; +constant tlb_rel_val_offset : natural := por_seq_offset + 3; +constant tlb_rel_data_offset : natural := tlb_rel_val_offset + thdid_width + 1; +constant iu_mm_ierat_flush_offset : natural := tlb_rel_data_offset + 132; +constant iu_xu_ierat_ex2_flush_offset : natural := iu_mm_ierat_flush_offset + thdid_width; +constant ccr2_frat_paranoia_offset : natural := iu_xu_ierat_ex2_flush_offset + thdid_width; +constant ccr2_notlb_offset : natural := ccr2_frat_paranoia_offset + 10; +constant xucr4_mmu_mchk_offset : natural := ccr2_notlb_offset + 1; +constant mchk_flash_inv_offset : natural := xucr4_mmu_mchk_offset + 1; +constant ex7_valid_offset : natural := mchk_flash_inv_offset + 4; +constant ex7_ttype_offset : natural := ex7_valid_offset + thdid_width; +constant ex7_tlbsel_offset : natural := ex7_ttype_offset + ttype_width; +constant iu1_debug_offset : natural := ex7_tlbsel_offset + 2; +constant iu2_debug_offset : natural := iu1_debug_offset + 11; +constant iu1_stg_act_offset : natural := iu2_debug_offset + 17; +constant iu2_stg_act_offset : natural := iu1_stg_act_offset + 1; +constant iu3_stg_act_offset : natural := iu2_stg_act_offset + 1; +constant iu4_stg_act_offset : natural := iu3_stg_act_offset + 1; +constant ex1_stg_act_offset : natural := iu4_stg_act_offset + 1; +constant ex2_stg_act_offset : natural := ex1_stg_act_offset + 1; +constant ex3_stg_act_offset : natural := ex2_stg_act_offset + 1; +constant ex4_stg_act_offset : natural := ex3_stg_act_offset + 1; +constant ex5_stg_act_offset : natural := ex4_stg_act_offset + 1; +constant ex6_stg_act_offset : natural := ex5_stg_act_offset + 1; +constant ex7_stg_act_offset : natural := ex6_stg_act_offset + 1; +constant tlb_rel_act_offset : natural := ex7_stg_act_offset + 1; +constant snoop_act_offset : natural := tlb_rel_act_offset + 1; +constant trace_bus_enable_offset : natural := snoop_act_offset + 1; +constant an_ac_grffence_en_dc_offset : natural := trace_bus_enable_offset + 1; +constant scan_right_1 : natural := an_ac_grffence_en_dc_offset + 1 -1; +constant bcfg_offset : natural := 0; +constant boot_scan_right : natural := bcfg_offset + bcfg_width - 1; +signal ex1_valid_d, ex1_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal ex1_ttype_d, ex1_ttype_q : std_ulogic_vector(0 to ttype_width); +signal ex1_ws_d, ex1_ws_q : std_ulogic_vector(0 to ws_width-1); +signal ex1_rs_is_d, ex1_rs_is_q : std_ulogic_vector(0 to rs_is_width-1); +signal ex1_ra_entry_d, ex1_ra_entry_q : std_ulogic_vector(0 to ra_entry_width-1); +signal ex1_state_d, ex1_state_q : std_ulogic_vector(0 to state_width-1); +signal ex1_pid_d, ex1_pid_q : std_ulogic_vector(0 to pid_width-1); +signal ex1_extclass_d, ex1_extclass_q : std_ulogic_vector(0 to extclass_width-1); +signal ex1_tlbsel_d, ex1_tlbsel_q : std_ulogic_vector(0 to tlbsel_width-1); +signal ex2_valid_d, ex2_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal ex2_ttype_d, ex2_ttype_q : std_ulogic_vector(0 to ttype_width-1); +signal ex2_ws_d, ex2_ws_q : std_ulogic_vector(0 to ws_width-1); +signal ex2_rs_is_d, ex2_rs_is_q : std_ulogic_vector(0 to rs_is_width-1); +signal ex2_ra_entry_d, ex2_ra_entry_q : std_ulogic_vector(0 to ra_entry_width-1); +signal ex2_state_d, ex2_state_q : std_ulogic_vector(0 to state_width-1); +signal ex2_pid_d, ex2_pid_q : std_ulogic_vector(0 to pid_width-1); +signal ex2_extclass_d, ex2_extclass_q : std_ulogic_vector(0 to extclass_width-1); +signal ex2_tlbsel_d, ex2_tlbsel_q : std_ulogic_vector(0 to tlbsel_width-1); +signal ex3_valid_d, ex3_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal ex3_ttype_d, ex3_ttype_q : std_ulogic_vector(0 to ttype_width-1); +signal ex3_ws_d, ex3_ws_q : std_ulogic_vector(0 to ws_width-1); +signal ex3_rs_is_d, ex3_rs_is_q : std_ulogic_vector(0 to rs_is_width-1); +signal ex3_ra_entry_d, ex3_ra_entry_q : std_ulogic_vector(0 to ra_entry_width-1); +signal ex3_state_d, ex3_state_q : std_ulogic_vector(0 to state_width-1); +signal ex3_pid_d, ex3_pid_q : std_ulogic_vector(0 to pid_width-1); +signal ex3_extclass_d, ex3_extclass_q : std_ulogic_vector(0 to extclass_width-1); +signal ex3_tlbsel_d, ex3_tlbsel_q : std_ulogic_vector(0 to tlbsel_width-1); +signal ex3_eratsx_data_d, ex3_eratsx_data_q : std_ulogic_vector(0 to 2+num_entry_log2-1); +signal ex4_valid_d, ex4_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal ex4_ttype_d, ex4_ttype_q : std_ulogic_vector(0 to ttype_width-1); +signal ex4_ws_d, ex4_ws_q : std_ulogic_vector(0 to ws_width-1); +signal ex4_rs_is_d, ex4_rs_is_q : std_ulogic_vector(0 to rs_is_width-1); +signal ex4_ra_entry_d, ex4_ra_entry_q : std_ulogic_vector(0 to ra_entry_width-1); +signal ex4_state_d, ex4_state_q : std_ulogic_vector(0 to state_width-1); +signal ex4_pid_d, ex4_pid_q : std_ulogic_vector(0 to pid_width-1); +signal ex4_extclass_d, ex4_extclass_q : std_ulogic_vector(0 to extclass_width-1); +signal ex4_tlbsel_d, ex4_tlbsel_q : std_ulogic_vector(0 to tlbsel_width-1); +signal ex4_data_out_d, ex4_data_out_q : std_ulogic_vector(64-data_out_width to 63); +signal ex5_valid_d, ex5_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal ex5_ttype_d, ex5_ttype_q : std_ulogic_vector(0 to ttype_width-1); +signal ex5_ws_d, ex5_ws_q : std_ulogic_vector(0 to ws_width-1); +signal ex5_rs_is_d, ex5_rs_is_q : std_ulogic_vector(0 to rs_is_width-1); +signal ex5_ra_entry_d, ex5_ra_entry_q : std_ulogic_vector(0 to ra_entry_width-1); +signal ex5_state_d, ex5_state_q : std_ulogic_vector(0 to state_width-1); +signal ex5_pid_d, ex5_pid_q : std_ulogic_vector(0 to pid_width-1); +signal ex5_extclass_d, ex5_extclass_q : std_ulogic_vector(0 to extclass_width-1); +signal ex5_tlbsel_d, ex5_tlbsel_q : std_ulogic_vector(0 to tlbsel_width-1); +signal ex5_data_in_d, ex5_data_in_q : std_ulogic_vector(64-rs_data_width to 63); +signal ex6_valid_d, ex6_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal ex6_ttype_d, ex6_ttype_q : std_ulogic_vector(0 to ttype_width-1); +signal ex6_ws_d, ex6_ws_q : std_ulogic_vector(0 to ws_width-1); +signal ex6_rs_is_d, ex6_rs_is_q : std_ulogic_vector(0 to rs_is_width-1); +signal ex6_ra_entry_d, ex6_ra_entry_q : std_ulogic_vector(0 to ra_entry_width-1); +signal ex6_state_d, ex6_state_q : std_ulogic_vector(0 to state_width-1); +signal ex6_pid_d, ex6_pid_q : std_ulogic_vector(0 to pid_width-1); +signal ex6_extclass_d, ex6_extclass_q : std_ulogic_vector(0 to extclass_width-1); +signal ex6_tlbsel_d, ex6_tlbsel_q : std_ulogic_vector(0 to tlbsel_width-1); +signal ex6_data_in_d, ex6_data_in_q : std_ulogic_vector(64-rs_data_width to 63); +signal ex7_valid_d, ex7_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal ex7_ttype_d, ex7_ttype_q : std_ulogic_vector(0 to ttype_width-1); +signal ex7_tlbsel_d, ex7_tlbsel_q : std_ulogic_vector(0 to tlbsel_width-1); +signal iu1_valid_d, iu1_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal iu1_state_d, iu1_state_q : std_ulogic_vector(0 to state_width-1); +signal iu1_pid_d, iu1_pid_q : std_ulogic_vector(0 to pid_width-1); +signal iu2_valid_d, iu2_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal iu2_state_d, iu2_state_q : std_ulogic_vector(0 to state_width-1); +signal iu2_pid_d, iu2_pid_q : std_ulogic_vector(0 to pid_width-1); +signal iu1_flush_enab_d, iu1_flush_enab_q : std_ulogic; +signal iu2_n_flush_req_d, iu2_n_flush_req_q : std_ulogic_vector(0 to thdid_width-1); +signal hold_req_d, hold_req_q : std_ulogic_vector(0 to thdid_width-1); +signal tlb_miss_d, tlb_miss_q : std_ulogic_vector(0 to thdid_width-1); +signal tlb_req_inprogress_d, tlb_req_inprogress_q : std_ulogic_vector(0 to thdid_width-1); +signal iu2_tlbreq_d, iu2_tlbreq_q : std_ulogic; +signal iu2_miss_d, iu2_miss_q : std_ulogic_vector(0 to 1); +signal iu2_multihit_d, iu2_multihit_q : std_ulogic_vector(0 to 1); +signal iu2_parerr_d, iu2_parerr_q : std_ulogic_vector(0 to 1); +signal iu2_isi_d, iu2_isi_q : std_ulogic_vector(0 to 5); +signal iu1_debug_d, iu1_debug_q : std_ulogic_vector(0 to 10); +signal iu2_debug_d, iu2_debug_q : std_ulogic_vector(0 to 16); +signal iu2_multihit_b_pt_d, iu2_multihit_b_pt_q : std_ulogic_vector(1 to num_entry); +signal iu2_first_hit_entry_pt_d, iu2_first_hit_entry_pt_q : std_ulogic_vector(1 to num_entry-1); +signal iu2_cam_cmp_data_d, iu2_cam_cmp_data_q : std_ulogic_vector(0 to cam_data_width-1); +signal iu2_array_cmp_data_d, iu2_array_cmp_data_q : std_ulogic_vector(0 to array_data_width-1); +signal ex4_rd_cam_data_d, ex4_rd_cam_data_q : std_ulogic_vector(0 to cam_data_width-1); +signal ex4_rd_array_data_d, ex4_rd_array_data_q : std_ulogic_vector(0 to array_data_width-1); +signal por_seq_d, por_seq_q : std_ulogic_vector(0 to 2); +signal ex3_parerr_d, ex3_parerr_q : std_ulogic_vector(0 to thdid_width); +signal ex4_parerr_d, ex4_parerr_q : std_ulogic_vector(0 to thdid_width+1); +signal ex4_ieen_d, ex4_ieen_q : std_ulogic_vector(0 to thdid_width+num_entry_log2-1); +signal ex5_ieen_d, ex5_ieen_q : std_ulogic_vector(0 to thdid_width+num_entry_log2-1); +signal ex6_ieen_d, ex6_ieen_q : std_ulogic_vector(0 to num_entry_log2); +signal mmucr1_d, mmucr1_q : std_ulogic_vector(0 to 8); +signal rpn_holdreg0_d, rpn_holdreg0_q : std_ulogic_vector(0 to 63); +signal rpn_holdreg1_d, rpn_holdreg1_q : std_ulogic_vector(0 to 63); +signal rpn_holdreg2_d, rpn_holdreg2_q : std_ulogic_vector(0 to 63); +signal rpn_holdreg3_d, rpn_holdreg3_q : std_ulogic_vector(0 to 63); +signal watermark_d, watermark_q : std_ulogic_vector(0 to watermark_width-1); +signal eptr_d, eptr_q : std_ulogic_vector(0 to eptr_width-1); +signal lru_d, lru_q : std_ulogic_vector(1 to lru_width); +signal lru_update_event_d, lru_update_event_q : std_ulogic_vector(0 to 8); +signal lru_debug_d, lru_debug_q : std_ulogic_vector(0 to 23); +signal snoop_val_d, snoop_val_q : std_ulogic_vector(0 to 2); +signal snoop_attr_d, snoop_attr_q : std_ulogic_vector(0 to 25); +signal snoop_addr_d, snoop_addr_q : std_ulogic_vector(52-epn_width to 51); +signal tlb_rel_val_d, tlb_rel_val_q : std_ulogic_vector(0 to 4); +signal tlb_rel_data_d, tlb_rel_data_q : std_ulogic_vector(0 to 131); +signal iu_mm_ierat_flush_d, iu_mm_ierat_flush_q : std_ulogic_vector(0 to thdid_width-1); +signal iu_xu_ierat_ex2_flush_d, iu_xu_ierat_ex2_flush_q : std_ulogic_vector(0 to thdid_width-1); +signal ccr2_frat_paranoia_d, ccr2_frat_paranoia_q : std_ulogic_vector(0 to 9); +signal ccr2_notlb_q, xucr4_mmu_mchk_q : std_ulogic; +signal mchk_flash_inv_d, mchk_flash_inv_q : std_ulogic_vector(0 to 3); +signal mchk_flash_inv_enab : std_ulogic; +signal spare_q : std_ulogic_vector(0 to 31); +signal bcfg_q, bcfg_q_b : std_ulogic_vector(0 to bcfg_width-1); +signal iu2_isi_sig : std_ulogic; +signal iu2_miss_sig : std_ulogic; +signal iu2_parerr_sig : std_ulogic; +signal iu2_multihit_sig : std_ulogic; +signal iu1_multihit : std_ulogic; +signal iu1_multihit_b : std_ulogic; +signal iu1_first_hit_entry : std_ulogic_vector(0 to num_entry_log2-1); +signal iu2_first_hit_entry : std_ulogic_vector(0 to num_entry_log2-1); +signal iu2_multihit_enab : std_ulogic; +signal por_wr_cam_val : std_ulogic_vector(0 to 1); +signal por_wr_array_val : std_ulogic_vector(0 to 1); +signal por_wr_cam_data : std_ulogic_vector(0 to cam_data_width-1); +signal por_wr_array_data : std_ulogic_vector(0 to array_data_width-1); +signal por_wr_entry : std_ulogic_vector(0 to num_entry_log2-1); +signal por_hold_req : std_ulogic_vector(0 to thdid_width-1); +signal lru_way_encode : std_ulogic_vector(0 to num_entry_log2-1); +signal lru_rmt_vec : std_ulogic_vector(0 to lru_width); +signal lru_reset_vec, lru_set_vec : std_ulogic_vector(1 to lru_width); +signal lru_op_vec, lru_vp_vec : std_ulogic_vector(1 to lru_width); +signal lru_eff : std_ulogic_vector(1 to lru_width); +signal lru_watermark_mask : std_ulogic_vector(0 to lru_width); +signal entry_valid_watermarked : std_ulogic_vector(0 to lru_width); +signal eptr_p1 : std_ulogic_vector(0 to eptr_width-1); +signal ex1_ieratre, ex1_ieratwe, ex1_ieratsx : std_ulogic; +signal ex3_parerr_enab : std_ulogic; +signal ex4_parerr_enab : std_ulogic; +signal ex3_ieratwe, ex4_ieratwe, ex5_ieratwe, ex6_ieratwe, ex7_ieratwe : std_ulogic; +signal ex6_ieratwe_ws3 : std_ulogic; +signal iu2_cmp_data_calc_par : std_ulogic_vector(50 to 67); +-- synopsys translate_off +-- synopsys translate_on +signal iu2_cmp_data_parerr_epn : std_ulogic; +signal iu2_cmp_data_parerr_rpn : std_ulogic; +signal ex4_rd_data_calc_par : std_ulogic_vector(50 to 67); +signal ex4_rd_data_parerr_epn : std_ulogic; +signal ex4_rd_data_parerr_rpn : std_ulogic; +-- synopsys translate_off +-- synopsys translate_on +signal unused_dc : std_ulogic_vector(0 to 29); +-- synopsys translate_off +-- synopsys translate_on +signal mmucr0_gs_vec : std_ulogic_vector(0 to thdid_width-1); +signal mmucr0_ts_vec : std_ulogic_vector(0 to thdid_width-1); +signal tlb_rel_cmpmask : std_ulogic_vector(0 to 3); +signal tlb_rel_xbitmask : std_ulogic_vector(0 to 3); +signal tlb_rel_maskpar : std_ulogic; +signal ex6_data_cmpmask : std_ulogic_vector(0 to 3); +signal ex6_data_xbitmask : std_ulogic_vector(0 to 3); +signal ex6_data_maskpar : std_ulogic; +signal comp_addr_mux1 : std_ulogic_vector(0 to 51); +signal comp_addr_mux1_sel : std_ulogic; +signal lru_way_is_written : std_ulogic; +signal lru_way_is_hit_entry : std_ulogic; +signal ex1_pid_0, ex1_pid_1 : std_ulogic_vector(0 to pid_width-1); +signal rd_val : std_ulogic; +signal rw_entry : std_ulogic_vector(0 to 3); +signal wr_array_par : std_ulogic_vector(51 to 67); +signal wr_array_data_nopar : std_ulogic_vector(0 to array_data_width-1-10-7); +signal wr_array_data : std_ulogic_vector(0 to array_data_width-1); +signal wr_cam_data : std_ulogic_vector(0 to cam_data_width-1); +signal wr_array_val : std_ulogic_vector(0 to 1); +signal wr_cam_val : std_ulogic_vector(0 to 1); +signal wr_val_early : std_ulogic; +signal comp_request : std_ulogic; +signal comp_addr : std_ulogic_vector(0 to 51); +signal addr_enable : std_ulogic_vector(0 to 1); +signal comp_pgsize : std_ulogic_vector(0 to 2); +signal pgsize_enable : std_ulogic; +signal comp_class : std_ulogic_vector(0 to 1); +signal class_enable : std_ulogic_vector(0 to 2); +signal comp_extclass : std_ulogic_vector(0 to 1); +signal extclass_enable : std_ulogic_vector(0 to 1); +signal comp_state : std_ulogic_vector(0 to 1); +signal state_enable : std_ulogic_vector(0 to 1); +signal comp_thdid : std_ulogic_vector(0 to 3); +signal thdid_enable : std_ulogic_vector(0 to 1); +signal comp_pid : std_ulogic_vector(0 to 7); +signal pid_enable : std_ulogic; +signal comp_invalidate : std_ulogic; +signal flash_invalidate : std_ulogic; +signal array_cmp_data : std_ulogic_vector(0 to array_data_width-1); +signal rd_array_data : std_ulogic_vector(0 to array_data_width-1); +signal cam_cmp_data : std_ulogic_vector(0 to cam_data_width-1); +signal cam_hit : std_ulogic; +signal cam_hit_entry : std_ulogic_vector(0 to 3); +signal entry_match, entry_match_q : std_ulogic_vector(0 to 15); +signal entry_valid, entry_valid_q : std_ulogic_vector(0 to 15); +signal rd_cam_data : std_ulogic_vector(0 to cam_data_width-1); +-- synopsys translate_off +-- synopsys translate_on +signal cam_pgsize : std_ulogic_vector(0 to 2); +signal ws0_pgsize : std_ulogic_vector(0 to 3); +signal bypass_mux_enab_np1 : std_ulogic; +signal bypass_attr_np1 : std_ulogic_vector(0 to 20); +signal attr_np2 : std_ulogic_vector(0 to 20); +signal rpn_np2 : std_ulogic_vector(22 to 51); +signal pc_sg_1 : std_ulogic; +signal pc_sg_0 : std_ulogic; +signal pc_func_sl_thold_1 : std_ulogic; +signal pc_func_sl_thold_0 : std_ulogic; +signal pc_func_sl_thold_0_b : std_ulogic; +signal pc_func_slp_sl_thold_1 : std_ulogic; +signal pc_func_slp_sl_thold_0 : std_ulogic; +signal pc_func_slp_sl_thold_0_b : std_ulogic; +signal pc_func_sl_force : std_ulogic; +signal pc_func_slp_sl_force : std_ulogic; +signal pc_cfg_slp_sl_thold_1 : std_ulogic; +signal pc_cfg_slp_sl_thold_0 : std_ulogic; +signal pc_cfg_slp_sl_thold_0_b : std_ulogic; +signal pc_cfg_slp_sl_force : std_ulogic; +signal lcb_dclk : std_ulogic; +signal lcb_lclk : clk_logic; +signal init_alias : std_ulogic; +signal iu1_stg_act_d, iu1_stg_act_q :std_ulogic; +signal iu2_stg_act_d, iu2_stg_act_q :std_ulogic; +signal iu3_stg_act_d, iu3_stg_act_q :std_ulogic; +signal iu4_stg_act_d, iu4_stg_act_q :std_ulogic; +signal ex1_stg_act_d, ex1_stg_act_q :std_ulogic; +signal ex2_stg_act_d, ex2_stg_act_q :std_ulogic; +signal ex3_stg_act_d, ex3_stg_act_q :std_ulogic; +signal ex4_stg_act_d, ex4_stg_act_q :std_ulogic; +signal ex5_stg_act_d, ex5_stg_act_q :std_ulogic; +signal ex6_stg_act_d, ex6_stg_act_q :std_ulogic; +signal ex7_stg_act_d, ex7_stg_act_q :std_ulogic; +signal iu1_cmp_data_act, iu1_grffence_act, iu1_or_iu2_grffence_act, iu2_to_iu4_grffence_act :std_ulogic; +signal ex3_rd_data_act, ex3_data_out_act :std_ulogic; +signal ex2_grffence_act, ex3_grffence_act :std_ulogic; +signal an_ac_grffence_en_dc_q, trace_bus_enable_q :std_ulogic; +signal entry_valid_act, entry_match_act :std_ulogic; +signal not_grffence_act, notlb_grffence_act :std_ulogic; +signal tlb_rel_act_d, tlb_rel_act_q, tlb_rel_act :std_ulogic; +signal snoop_act_q :std_ulogic; +signal lru_update_act, debug_grffence_act, eratsx_data_act :std_ulogic; +signal siv_0 : std_ulogic_vector(0 to scan_right_0); +signal sov_0 : std_ulogic_vector(0 to scan_right_0); +signal siv_1 : std_ulogic_vector(0 to scan_right_1); +signal sov_1 : std_ulogic_vector(0 to scan_right_1); +signal bsiv : std_ulogic_vector(0 to boot_scan_right); +signal bsov : std_ulogic_vector(0 to boot_scan_right); +signal tiup : std_ulogic; + BEGIN + +iu1_stg_act_d <= comp_request or spr_ic_clockgate_dis; +iu2_stg_act_d <= iu1_stg_act_q; +iu3_stg_act_d <= iu2_stg_act_q; +iu4_stg_act_d <= iu3_stg_act_q; +ex1_stg_act_d <= or_reduce(xu_iu_rf1_val) or spr_ic_clockgate_dis; +ex2_stg_act_d <= ex1_stg_act_q; +ex3_stg_act_d <= ex2_stg_act_q; +ex4_stg_act_d <= ex3_stg_act_q; +ex5_stg_act_d <= ex4_stg_act_q; +ex6_stg_act_d <= ex5_stg_act_q; +ex7_stg_act_d <= ex6_stg_act_q; +iu1_cmp_data_act <= iu1_stg_act_q and not(an_ac_grffence_en_dc); +iu1_grffence_act <= iu1_stg_act_q and not(an_ac_grffence_en_dc); +iu1_or_iu2_grffence_act <= (iu1_stg_act_q or iu2_stg_act_q) and not(an_ac_grffence_en_dc); +iu2_to_iu4_grffence_act <= (iu2_stg_act_q or iu3_stg_act_q or iu4_stg_act_q) and not(an_ac_grffence_en_dc); +ex2_grffence_act <= ex2_stg_act_q and not(an_ac_grffence_en_dc); +ex3_rd_data_act <= ex3_stg_act_q and not(an_ac_grffence_en_dc); +ex3_data_out_act <= ex3_stg_act_q and not(an_ac_grffence_en_dc); +ex3_grffence_act <= ex3_stg_act_q and not(an_ac_grffence_en_dc); +entry_valid_act <= not an_ac_grffence_en_dc; +entry_match_act <= not an_ac_grffence_en_dc; +not_grffence_act <= not an_ac_grffence_en_dc; +lru_update_act <= ex6_stg_act_q or ex7_stg_act_q or lru_update_event_q(4) or lru_update_event_q(8) or flash_invalidate or ex6_ieratwe_ws3; +notlb_grffence_act <= (not(ccr2_notlb_q) or spr_ic_clockgate_dis) and not(an_ac_grffence_en_dc); +debug_grffence_act <= trace_bus_enable_q and not(an_ac_grffence_en_dc); +eratsx_data_act <= (iu1_stg_act_q or ex2_stg_act_q) and not(an_ac_grffence_en_dc); +tiup <= '1'; +init_alias <= pc_iu_init_reset; +tlb_rel_val_d <= mm_iu_ierat_rel_val; +tlb_rel_data_d <= mm_iu_ierat_rel_data; +tlb_rel_act_d <= mm_iu_ierat_rel_data(eratpos_relsoon); +tlb_rel_act <= (tlb_rel_act_q and not(ccr2_notlb_q)); +ccr2_frat_paranoia_d(0 TO 8) <= xu_iu_spr_ccr2_ifratsc; +ccr2_frat_paranoia_d(9) <= xu_iu_spr_ccr2_ifrat; +ex1_valid_d <= xu_iu_rf1_val and not(xu_rf1_flush); +ex1_ttype_d(0 TO ttype_width-3) <= xu_iu_rf1_is_eratre & xu_iu_rf1_is_eratwe & xu_iu_rf1_is_eratsx & xu_iu_rf1_is_eratilx; +ex1_ttype_d(ttype_width-2 TO ttype_width) <= xu_iu_rf1_t; +ex1_ws_d <= xu_iu_rf1_ws; +ex1_rs_is_d <= (others => '0'); +ex1_ra_entry_d <= (others => '0'); +ex1_state_d(0) <= or_reduce(xu_iu_msr_pr and xu_iu_rf1_val); +ex1_state_d(1) <= (or_reduce(xu_iu_msr_hv and xu_iu_rf1_val) and not xu_iu_rf1_is_eratsx) or + (or_reduce(mmucr0_gs_vec and xu_iu_rf1_val) and xu_iu_rf1_is_eratsx); +ex1_state_d(2) <= (or_reduce(xu_iu_msr_is and xu_iu_rf1_val) and not xu_iu_rf1_is_eratsx) or + (or_reduce(mmucr0_ts_vec and xu_iu_rf1_val) and xu_iu_rf1_is_eratsx); +ex1_state_d(3) <= or_reduce(xu_iu_msr_cm and xu_iu_rf1_val); +mmucr0_gs_vec <= mm_iu_ierat_mmucr0_0(2) & mm_iu_ierat_mmucr0_1(2) & mm_iu_ierat_mmucr0_2(2) & mm_iu_ierat_mmucr0_3(2); +mmucr0_ts_vec <= mm_iu_ierat_mmucr0_0(3) & mm_iu_ierat_mmucr0_1(3) & mm_iu_ierat_mmucr0_2(3) & mm_iu_ierat_mmucr0_3(3); +ex1_extclass_d <= mm_iu_ierat_mmucr0_1(0 to 1) when xu_iu_rf1_val(1)='1' + else mm_iu_ierat_mmucr0_2(0 to 1) when xu_iu_rf1_val(2)='1' + else mm_iu_ierat_mmucr0_3(0 to 1) when xu_iu_rf1_val(3)='1' + else mm_iu_ierat_mmucr0_0(0 to 1); +ex1_tlbsel_d <= mm_iu_ierat_mmucr0_1(4 to 5) when xu_iu_rf1_val(1)='1' + else mm_iu_ierat_mmucr0_2(4 to 5) when xu_iu_rf1_val(2)='1' + else mm_iu_ierat_mmucr0_3(4 to 5) when xu_iu_rf1_val(3)='1' + else mm_iu_ierat_mmucr0_0(4 to 5); +ex1_pid_d <= gate_and((xu_iu_rf1_is_eratsx='1'), ex1_pid_0) or gate_and((xu_iu_rf1_is_eratsx='0'), ex1_pid_1); +ex1_pid_0 <= gate_and((xu_iu_rf1_val(0)='1'),mm_iu_ierat_mmucr0_0(6 to 19)) or + gate_and((xu_iu_rf1_val(1)='1'),mm_iu_ierat_mmucr0_1(6 to 19)) or + gate_and((xu_iu_rf1_val(2)='1'),mm_iu_ierat_mmucr0_2(6 to 19)) or + gate_and((xu_iu_rf1_val(3)='1'),mm_iu_ierat_mmucr0_3(6 to 19)); +ex1_pid_1 <= gate_and((xu_iu_rf1_val(0)='1'),mm_iu_ierat_pid0) or + gate_and((xu_iu_rf1_val(1)='1'),mm_iu_ierat_pid1) or + gate_and((xu_iu_rf1_val(2)='1'),mm_iu_ierat_pid2) or + gate_and((xu_iu_rf1_val(3)='1'),mm_iu_ierat_pid3); +ex1_ieratre <= or_reduce(ex1_valid_q) and ex1_ttype_q(0) and ex1_tlbsel_q(0) and not ex1_tlbsel_q(1); +ex1_ieratwe <= or_reduce(ex1_valid_q) and ex1_ttype_q(1) and ex1_tlbsel_q(0) and not ex1_tlbsel_q(1); +ex1_ieratsx <= or_reduce(ex1_valid_q) and ex1_ttype_q(2) and ex1_tlbsel_q(0) and not ex1_tlbsel_q(1); +ex2_valid_d <= ex1_valid_q and not(xu_ex1_flush); +ex2_ttype_d(0 TO ttype_width-3) <= ex1_ttype_q(0 to ttype_width-3); +ex2_ttype_d(ttype_width-2 TO ttype_width-1) <= xu_iu_ex1_is_csync & xu_iu_ex1_is_isync; +ex2_ws_d <= ex1_ws_q; +ex2_rs_is_d <= xu_iu_ex1_rs_is; +ex2_ra_entry_d <= xu_iu_ex1_ra_entry; +ex2_state_d <= ex1_state_q; +ex2_pid_d <= ex1_pid_q; +ex2_extclass_d <= ex1_extclass_q; +ex2_tlbsel_d <= ex1_tlbsel_q; +ex3_valid_d <= ex2_valid_q and not(xu_ex2_flush); +ex3_ttype_d <= ex2_ttype_q; +ex3_ws_d <= ex2_ws_q; +ex3_rs_is_d <= ex2_rs_is_q; +ex3_ra_entry_d <= iu1_first_hit_entry when ex2_ttype_q(2 to 3)/="00" else ex2_ra_entry_q; +ex3_tlbsel_d <= ex2_tlbsel_q; +ex3_extclass_d <= ex2_extclass_q; +ex3_state_d <= ex2_state_q; +ex3_pid_d <= ex2_pid_q; +ex3_ieratwe <= or_reduce(ex3_valid_q) and ex3_ttype_q(1) and ex3_tlbsel_q(0) and not ex3_tlbsel_q(1); +ex4_valid_d <= ex3_valid_q and not(xu_ex3_flush); +ex4_ttype_d <= ex3_ttype_q; +ex4_ws_d <= ex3_ws_q; +ex4_rs_is_d <= ex3_rs_is_q; +ex4_ra_entry_d <= ex3_ra_entry_q; +ex4_tlbsel_d <= ex3_tlbsel_q; +ex4_extclass_d <= rd_cam_data(63 to 64) when (ex3_valid_q/="0000" and ex3_ttype_q(0)='1' and ex3_ws_q="00") + else ex3_extclass_q; +ex4_state_d <= ex3_state_q(0) & rd_cam_data(65 to 66) & ex3_state_q(3) when (ex3_valid_q/="0000" and ex3_ttype_q(0)='1' and ex3_ws_q="00") + else ex3_state_q; +ex4_pid_d <= rd_cam_data(61 to 62) & rd_cam_data(57 to 60) & rd_cam_data(67 to 74) + when (ex3_valid_q/="0000" and ex3_ttype_q(0)='1' and ex3_ws_q="00") + else ex3_pid_q; +ex4_ieratwe <= or_reduce(ex4_valid_q) and ex4_ttype_q(1) and ex4_tlbsel_q(0) and not ex4_tlbsel_q(1); +ex5_valid_d <= ex4_valid_q and not(xu_ex4_flush); +ex5_ws_d <= ex4_ws_q; +ex5_rs_is_d <= ex4_rs_is_q; +ex5_ra_entry_d <= ex4_ra_entry_q; +ex5_ttype_d(0 TO 5) <= ex4_ttype_q(0 to 5); +ex5_extclass_d <= ex4_extclass_q; +ex5_state_d <= ex4_state_q; +ex5_pid_d <= ex4_pid_q; +ex5_tlbsel_d <= ex4_tlbsel_q; +ex5_data_in_d <= xu_iu_ex4_rs_data; +ex5_ieratwe <= or_reduce(ex5_valid_q) and ex5_ttype_q(1) and ex5_tlbsel_q(0) and not ex5_tlbsel_q(1); +ex6_valid_d <= ex5_valid_q and not(xu_ex5_flush); +ex6_ws_d <= ex5_ws_q; +ex6_rs_is_d <= ex5_rs_is_q; +ex6_ra_entry_d <= ex5_ra_entry_q; +ex6_ttype_d(0 TO 3) <= ex5_ttype_q(0 to 3); +ex6_ttype_d(4) <= '1' when (ex5_ttype_q(4)='1' and mmucr1_q(3)='0' and ccr2_notlb_q=MMU_Mode_Value) + else '0'; +ex6_ttype_d(5) <= '1' when (ex5_ttype_q(5)='1' and mmucr1_q(4)='0' and ccr2_notlb_q=MMU_Mode_Value) + else '0'; +ex6_extclass_d <= mm_iu_ierat_mmucr0_0(0 to 1) + when (ex5_valid_q="1000" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else mm_iu_ierat_mmucr0_1(0 to 1) + when (ex5_valid_q="0100" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else mm_iu_ierat_mmucr0_2(0 to 1) + when (ex5_valid_q="0010" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else mm_iu_ierat_mmucr0_3(0 to 1) + when (ex5_valid_q="0001" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else ex5_extclass_q; +ex6_state_d <= xu_iu_msr_pr(0) & mm_iu_ierat_mmucr0_0(2 to 3) & xu_iu_msr_cm(0) + when (ex5_valid_q="1000" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else xu_iu_msr_pr(1) & mm_iu_ierat_mmucr0_1(2 to 3) & xu_iu_msr_cm(1) + when (ex5_valid_q="0100" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else xu_iu_msr_pr(2) & mm_iu_ierat_mmucr0_2(2 to 3) & xu_iu_msr_cm(2) + when (ex5_valid_q="0010" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else xu_iu_msr_pr(3) & mm_iu_ierat_mmucr0_3(2 to 3) & xu_iu_msr_cm(3) + when (ex5_valid_q="0001" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else ex5_state_q; +ex6_pid_d <= mm_iu_ierat_mmucr0_0(6 to 19) + when (ex5_valid_q="1000" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else mm_iu_ierat_mmucr0_1(6 to 19) + when (ex5_valid_q="0100" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else mm_iu_ierat_mmucr0_2(6 to 19) + when (ex5_valid_q="0010" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else mm_iu_ierat_mmucr0_3(6 to 19) + when (ex5_valid_q="0001" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else ex5_pid_q; +ex6_tlbsel_d <= mm_iu_ierat_mmucr0_0(4 to 5) + when (ex5_valid_q="1000" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else mm_iu_ierat_mmucr0_1(4 to 5) + when (ex5_valid_q="0100" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else mm_iu_ierat_mmucr0_2(4 to 5) + when (ex5_valid_q="0010" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else mm_iu_ierat_mmucr0_3(4 to 5) + when (ex5_valid_q="0001" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else ex5_tlbsel_q; +ex6_data_in_d <= ex5_data_in_q; +ex6_ieratwe <= or_reduce(ex6_valid_q) and ex6_ttype_q(1) and ex6_tlbsel_q(0) and not ex6_tlbsel_q(1); +ex7_valid_d <= ex6_valid_q; +ex7_ttype_d <= ex6_ttype_q; +ex7_tlbsel_d <= ex6_tlbsel_q; +ex7_ieratwe <= or_reduce(ex7_valid_q) and ex7_ttype_q(1) and ex7_tlbsel_q(0) and not ex7_tlbsel_q(1); +iu1_valid_d <= iu_ierat_iu0_thdid and (0 to thdid_width-1 => iu_ierat_iu0_val) and not(iu_ierat_iu0_flush) and not(xu_iu_flush) and not(iu2_n_flush_req_q); +iu1_state_d(0) <= or_reduce(xu_iu_msr_pr and iu_ierat_iu0_thdid); +iu1_state_d(1) <= or_reduce(xu_iu_msr_hv and iu_ierat_iu0_thdid); +iu1_state_d(2) <= or_reduce(xu_iu_msr_is and iu_ierat_iu0_thdid); +iu1_state_d(3) <= or_reduce(xu_iu_msr_cm and iu_ierat_iu0_thdid); +iu1_pid_d <= ( mm_iu_ierat_pid0 and (0 to pid_width-1 => iu_ierat_iu0_thdid(0)) ) or + ( mm_iu_ierat_pid1 and (0 to pid_width-1 => iu_ierat_iu0_thdid(1)) ) or + ( mm_iu_ierat_pid2 and (0 to pid_width-1 => iu_ierat_iu0_thdid(2)) ) or + ( mm_iu_ierat_pid3 and (0 to pid_width-1 => iu_ierat_iu0_thdid(3)) ); +iu2_valid_d <= iu1_valid_q and not(iu_ierat_iu1_flush) and not(xu_iu_flush) and not(iu2_n_flush_req_q); +iu2_state_d <= iu1_state_q; +iu2_pid_d <= iu1_pid_q; +iu_mm_ierat_flush_d <= iu_ierat_iu1_flush; +mmucr1_d <= mm_iu_ierat_mmucr1; +MQQ1:IU1_MULTIHIT_B_PT(1) <= + Eq(( ENTRY_MATCH(1) & ENTRY_MATCH(2) & + ENTRY_MATCH(3) & ENTRY_MATCH(4) & + ENTRY_MATCH(5) & ENTRY_MATCH(6) & + ENTRY_MATCH(7) & ENTRY_MATCH(8) & + ENTRY_MATCH(9) & ENTRY_MATCH(10) & + ENTRY_MATCH(11) & ENTRY_MATCH(12) & + ENTRY_MATCH(13) & ENTRY_MATCH(14) & + ENTRY_MATCH(15) ) , STD_ULOGIC_VECTOR'("000000000000000")); +MQQ2:IU1_MULTIHIT_B_PT(2) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(2) & + ENTRY_MATCH(3) & ENTRY_MATCH(4) & + ENTRY_MATCH(5) & ENTRY_MATCH(6) & + ENTRY_MATCH(7) & ENTRY_MATCH(8) & + ENTRY_MATCH(9) & ENTRY_MATCH(10) & + ENTRY_MATCH(11) & ENTRY_MATCH(12) & + ENTRY_MATCH(13) & ENTRY_MATCH(14) & + ENTRY_MATCH(15) ) , STD_ULOGIC_VECTOR'("000000000000000")); +MQQ3:IU1_MULTIHIT_B_PT(3) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(3) & ENTRY_MATCH(4) & + ENTRY_MATCH(5) & ENTRY_MATCH(6) & + ENTRY_MATCH(7) & ENTRY_MATCH(8) & + ENTRY_MATCH(9) & ENTRY_MATCH(10) & + ENTRY_MATCH(11) & ENTRY_MATCH(12) & + ENTRY_MATCH(13) & ENTRY_MATCH(14) & + ENTRY_MATCH(15) ) , STD_ULOGIC_VECTOR'("000000000000000")); +MQQ4:IU1_MULTIHIT_B_PT(4) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(4) & + ENTRY_MATCH(5) & ENTRY_MATCH(6) & + ENTRY_MATCH(7) & ENTRY_MATCH(8) & + ENTRY_MATCH(9) & ENTRY_MATCH(10) & + ENTRY_MATCH(11) & ENTRY_MATCH(12) & + ENTRY_MATCH(13) & ENTRY_MATCH(14) & + ENTRY_MATCH(15) ) , STD_ULOGIC_VECTOR'("000000000000000")); +MQQ5:IU1_MULTIHIT_B_PT(5) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(5) & ENTRY_MATCH(6) & + ENTRY_MATCH(7) & ENTRY_MATCH(8) & + ENTRY_MATCH(9) & ENTRY_MATCH(10) & + ENTRY_MATCH(11) & ENTRY_MATCH(12) & + ENTRY_MATCH(13) & ENTRY_MATCH(14) & + ENTRY_MATCH(15) ) , STD_ULOGIC_VECTOR'("000000000000000")); +MQQ6:IU1_MULTIHIT_B_PT(6) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(6) & + ENTRY_MATCH(7) & ENTRY_MATCH(8) & + ENTRY_MATCH(9) & ENTRY_MATCH(10) & + ENTRY_MATCH(11) & ENTRY_MATCH(12) & + ENTRY_MATCH(13) & ENTRY_MATCH(14) & + ENTRY_MATCH(15) ) , STD_ULOGIC_VECTOR'("000000000000000")); +MQQ7:IU1_MULTIHIT_B_PT(7) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(7) & ENTRY_MATCH(8) & + ENTRY_MATCH(9) & ENTRY_MATCH(10) & + ENTRY_MATCH(11) & ENTRY_MATCH(12) & + ENTRY_MATCH(13) & ENTRY_MATCH(14) & + ENTRY_MATCH(15) ) , STD_ULOGIC_VECTOR'("000000000000000")); +MQQ8:IU1_MULTIHIT_B_PT(8) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(8) & + ENTRY_MATCH(9) & ENTRY_MATCH(10) & + ENTRY_MATCH(11) & ENTRY_MATCH(12) & + ENTRY_MATCH(13) & ENTRY_MATCH(14) & + ENTRY_MATCH(15) ) , STD_ULOGIC_VECTOR'("000000000000000")); +MQQ9:IU1_MULTIHIT_B_PT(9) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(9) & ENTRY_MATCH(10) & + ENTRY_MATCH(11) & ENTRY_MATCH(12) & + ENTRY_MATCH(13) & ENTRY_MATCH(14) & + ENTRY_MATCH(15) ) , STD_ULOGIC_VECTOR'("000000000000000")); +MQQ10:IU1_MULTIHIT_B_PT(10) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(10) & + ENTRY_MATCH(11) & ENTRY_MATCH(12) & + ENTRY_MATCH(13) & ENTRY_MATCH(14) & + ENTRY_MATCH(15) ) , STD_ULOGIC_VECTOR'("000000000000000")); +MQQ11:IU1_MULTIHIT_B_PT(11) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(11) & ENTRY_MATCH(12) & + ENTRY_MATCH(13) & ENTRY_MATCH(14) & + ENTRY_MATCH(15) ) , STD_ULOGIC_VECTOR'("000000000000000")); +MQQ12:IU1_MULTIHIT_B_PT(12) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(12) & + ENTRY_MATCH(13) & ENTRY_MATCH(14) & + ENTRY_MATCH(15) ) , STD_ULOGIC_VECTOR'("000000000000000")); +MQQ13:IU1_MULTIHIT_B_PT(13) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(13) & ENTRY_MATCH(14) & + ENTRY_MATCH(15) ) , STD_ULOGIC_VECTOR'("000000000000000")); +MQQ14:IU1_MULTIHIT_B_PT(14) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(14) & + ENTRY_MATCH(15) ) , STD_ULOGIC_VECTOR'("000000000000000")); +MQQ15:IU1_MULTIHIT_B_PT(15) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(15) ) , STD_ULOGIC_VECTOR'("000000000000000")); +MQQ16:IU1_MULTIHIT_B_PT(16) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) ) , STD_ULOGIC_VECTOR'("000000000000000")); +MQQ17:IU1_MULTIHIT_B <= + (IU1_MULTIHIT_B_PT(1) OR IU1_MULTIHIT_B_PT(2) + OR IU1_MULTIHIT_B_PT(3) OR IU1_MULTIHIT_B_PT(4) + OR IU1_MULTIHIT_B_PT(5) OR IU1_MULTIHIT_B_PT(6) + OR IU1_MULTIHIT_B_PT(7) OR IU1_MULTIHIT_B_PT(8) + OR IU1_MULTIHIT_B_PT(9) OR IU1_MULTIHIT_B_PT(10) + OR IU1_MULTIHIT_B_PT(11) OR IU1_MULTIHIT_B_PT(12) + OR IU1_MULTIHIT_B_PT(13) OR IU1_MULTIHIT_B_PT(14) + OR IU1_MULTIHIT_B_PT(15) OR IU1_MULTIHIT_B_PT(16) + ); + +iu1_multihit <= not iu1_multihit_b; +iu2_multihit_b_pt_d <= iu1_multihit_b_pt; +iu2_multihit_enab <= not or_reduce(iu2_multihit_b_pt_q); +MQQ18:IU1_FIRST_HIT_ENTRY_PT(1) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) + ) , STD_ULOGIC_VECTOR'("0000000000000001")); +MQQ19:IU1_FIRST_HIT_ENTRY_PT(2) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) ) , STD_ULOGIC_VECTOR'("000000000000001")); +MQQ20:IU1_FIRST_HIT_ENTRY_PT(3) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) + ) , STD_ULOGIC_VECTOR'("00000000000001")); +MQQ21:IU1_FIRST_HIT_ENTRY_PT(4) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) ) , STD_ULOGIC_VECTOR'("0000000000001")); +MQQ22:IU1_FIRST_HIT_ENTRY_PT(5) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) + ) , STD_ULOGIC_VECTOR'("000000000001")); +MQQ23:IU1_FIRST_HIT_ENTRY_PT(6) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) ) , STD_ULOGIC_VECTOR'("00000000001")); +MQQ24:IU1_FIRST_HIT_ENTRY_PT(7) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) + ) , STD_ULOGIC_VECTOR'("0000000001")); +MQQ25:IU1_FIRST_HIT_ENTRY_PT(8) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) ) , STD_ULOGIC_VECTOR'("000000001")); +MQQ26:IU1_FIRST_HIT_ENTRY_PT(9) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) + ) , STD_ULOGIC_VECTOR'("00000001")); +MQQ27:IU1_FIRST_HIT_ENTRY_PT(10) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) ) , STD_ULOGIC_VECTOR'("0000001")); +MQQ28:IU1_FIRST_HIT_ENTRY_PT(11) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) + ) , STD_ULOGIC_VECTOR'("000001")); +MQQ29:IU1_FIRST_HIT_ENTRY_PT(12) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) ) , STD_ULOGIC_VECTOR'("00001")); +MQQ30:IU1_FIRST_HIT_ENTRY_PT(13) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) + ) , STD_ULOGIC_VECTOR'("0001")); +MQQ31:IU1_FIRST_HIT_ENTRY_PT(14) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) ) , STD_ULOGIC_VECTOR'("001")); +MQQ32:IU1_FIRST_HIT_ENTRY_PT(15) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) + ) , STD_ULOGIC_VECTOR'("01")); +MQQ33:IU1_FIRST_HIT_ENTRY(0) <= + (IU1_FIRST_HIT_ENTRY_PT(1) OR IU1_FIRST_HIT_ENTRY_PT(2) + OR IU1_FIRST_HIT_ENTRY_PT(3) OR IU1_FIRST_HIT_ENTRY_PT(4) + OR IU1_FIRST_HIT_ENTRY_PT(5) OR IU1_FIRST_HIT_ENTRY_PT(6) + OR IU1_FIRST_HIT_ENTRY_PT(7) OR IU1_FIRST_HIT_ENTRY_PT(8) + ); +MQQ34:IU1_FIRST_HIT_ENTRY(1) <= + (IU1_FIRST_HIT_ENTRY_PT(1) OR IU1_FIRST_HIT_ENTRY_PT(2) + OR IU1_FIRST_HIT_ENTRY_PT(3) OR IU1_FIRST_HIT_ENTRY_PT(4) + OR IU1_FIRST_HIT_ENTRY_PT(9) OR IU1_FIRST_HIT_ENTRY_PT(10) + OR IU1_FIRST_HIT_ENTRY_PT(11) OR IU1_FIRST_HIT_ENTRY_PT(12) + ); +MQQ35:IU1_FIRST_HIT_ENTRY(2) <= + (IU1_FIRST_HIT_ENTRY_PT(1) OR IU1_FIRST_HIT_ENTRY_PT(2) + OR IU1_FIRST_HIT_ENTRY_PT(5) OR IU1_FIRST_HIT_ENTRY_PT(6) + OR IU1_FIRST_HIT_ENTRY_PT(9) OR IU1_FIRST_HIT_ENTRY_PT(10) + OR IU1_FIRST_HIT_ENTRY_PT(13) OR IU1_FIRST_HIT_ENTRY_PT(14) + ); +MQQ36:IU1_FIRST_HIT_ENTRY(3) <= + (IU1_FIRST_HIT_ENTRY_PT(1) OR IU1_FIRST_HIT_ENTRY_PT(3) + OR IU1_FIRST_HIT_ENTRY_PT(5) OR IU1_FIRST_HIT_ENTRY_PT(7) + OR IU1_FIRST_HIT_ENTRY_PT(9) OR IU1_FIRST_HIT_ENTRY_PT(11) + OR IU1_FIRST_HIT_ENTRY_PT(13) OR IU1_FIRST_HIT_ENTRY_PT(15) + ); + +iu2_first_hit_entry_pt_d <= iu1_first_hit_entry_pt; +iu2_first_hit_entry(0) <= + (iu2_first_hit_entry_pt_q(1) or iu2_first_hit_entry_pt_q(2) + or iu2_first_hit_entry_pt_q(3) or iu2_first_hit_entry_pt_q(4) + or iu2_first_hit_entry_pt_q(5) or iu2_first_hit_entry_pt_q(6) + or iu2_first_hit_entry_pt_q(7) or iu2_first_hit_entry_pt_q(8)); +iu2_first_hit_entry(1) <= + (iu2_first_hit_entry_pt_q(1) or iu2_first_hit_entry_pt_q(2) + or iu2_first_hit_entry_pt_q(3) or iu2_first_hit_entry_pt_q(4) + or iu2_first_hit_entry_pt_q(9) or iu2_first_hit_entry_pt_q(10) + or iu2_first_hit_entry_pt_q(11) or iu2_first_hit_entry_pt_q(12)); +iu2_first_hit_entry(2) <= + (iu2_first_hit_entry_pt_q(1) or iu2_first_hit_entry_pt_q(2) + or iu2_first_hit_entry_pt_q(5) or iu2_first_hit_entry_pt_q(6) + or iu2_first_hit_entry_pt_q(9) or iu2_first_hit_entry_pt_q(10) + or iu2_first_hit_entry_pt_q(13) or iu2_first_hit_entry_pt_q(14)); +iu2_first_hit_entry(3) <= + (iu2_first_hit_entry_pt_q(1) or iu2_first_hit_entry_pt_q(3) + or iu2_first_hit_entry_pt_q(5) or iu2_first_hit_entry_pt_q(7) + or iu2_first_hit_entry_pt_q(9) or iu2_first_hit_entry_pt_q(11) + or iu2_first_hit_entry_pt_q(13) or iu2_first_hit_entry_pt_q(15)); +iu2_cam_cmp_data_d <= cam_cmp_data; +iu2_array_cmp_data_d <= array_cmp_data; +iu2_miss_d(0) <= ( or_reduce(iu1_valid_q and not(iu_ierat_iu1_flush) and not(xu_iu_flush) and not(iu2_n_flush_req_q)) and + not iu1_flush_enab_q and not ccr2_frat_paranoia_q(9) ); +iu2_miss_d(1) <= not cam_hit; +iu2_miss_sig <= iu2_miss_q(0) and iu2_miss_q(1); +iu2_multihit_d(0) <= ( cam_hit and iu1_multihit and + or_reduce(iu1_valid_q and not(iu_ierat_iu1_flush) and not(xu_iu_flush) and not(iu2_n_flush_req_q)) and + not iu1_flush_enab_q and not ccr2_frat_paranoia_q(9) ); +iu2_multihit_d(1) <= iu1_multihit; +iu2_multihit_sig <= iu2_multihit_q(0) and iu2_multihit_q(1); +iu2_parerr_d(0) <= ( cam_hit and iu1_multihit_b and + or_reduce(iu1_valid_q and not(iu_ierat_iu1_flush) and not(xu_iu_flush) and not(iu2_n_flush_req_q)) and + not iu1_flush_enab_q and not ccr2_frat_paranoia_q(9) ); +iu2_parerr_d(1) <= ( cam_hit and iu1_multihit_b and + or_reduce(iu1_valid_q and not(iu_ierat_iu1_flush) and not(xu_iu_flush) and not(iu2_n_flush_req_q)) and + not iu1_flush_enab_q and not ccr2_frat_paranoia_q(9) ); +iu2_parerr_sig <= (iu2_parerr_q(0) and iu2_cmp_data_parerr_epn) or + (iu2_parerr_q(1) and iu2_cmp_data_parerr_rpn); +iu2_isi_d(0) <= ( or_reduce(iu1_valid_q and not(iu_ierat_iu1_flush) and not(xu_iu_flush) and not(iu2_n_flush_req_q)) + and not iu1_flush_enab_q and iu1_state_q(0) and not ccr2_frat_paranoia_q(9) ); +iu2_isi_d(2) <= ( or_reduce(iu1_valid_q and not(iu_ierat_iu1_flush) and not(xu_iu_flush) and not(iu2_n_flush_req_q)) + and not iu1_flush_enab_q and not iu1_state_q(0) and not ccr2_frat_paranoia_q(9) ); +iu2_isi_d(4) <= ( or_reduce(iu1_valid_q and not(iu_ierat_iu1_flush) and not(xu_iu_flush) and not(iu2_n_flush_req_q)) + and not iu1_flush_enab_q and mmucr1_q(1) and not ccr2_frat_paranoia_q(9) ); +iu2_isi_d(1) <= not array_cmp_data(45); +iu2_isi_d(3) <= not array_cmp_data(46); +iu2_isi_d(5) <= not array_cmp_data(30); +iu2_isi_sig <= (iu2_isi_q(0) and iu2_isi_q(1)) or + (iu2_isi_q(2) and iu2_isi_q(3)) or + (iu2_isi_q(4) and iu2_isi_q(5)); +ex3_eratsx_data_d <= iu1_multihit & cam_hit & iu1_first_hit_entry; +ex3_parerr_d(0 TO thdid_width-1) <= ex2_valid_q and not(xu_ex2_flush); +ex3_parerr_d(thdid_width) <= ( cam_hit and iu1_multihit_b and ex2_ttype_q(2) and ex2_tlbsel_q(0) and not(ex2_tlbsel_q(1)) + and not(ex3_ieratwe or ex4_ieratwe or ex5_ieratwe or ex6_ieratwe or ex7_ieratwe) + and or_reduce(ex2_valid_q and not(xu_ex2_flush)) ); +ex3_parerr_enab <= ex3_parerr_q(thdid_width) and iu2_cmp_data_parerr_epn; +ex4_rd_array_data_d <= rd_array_data; +ex4_rd_cam_data_d <= rd_cam_data; +ex4_parerr_d(0 TO thdid_width-1) <= ex3_valid_q and not(xu_ex3_flush); +ex4_parerr_d(thdid_width) <= (ex3_ttype_q(0) and not ex3_ws_q(0) and not ex3_ws_q(1) and ex3_tlbsel_q(0) and not ex3_tlbsel_q(1) + and not(ex4_ieratwe or ex5_ieratwe or ex6_ieratwe)); +ex4_parerr_d(thdid_width+1) <= (ex3_ttype_q(0) and xor_reduce(ex3_ws_q) and ex3_tlbsel_q(0) and not ex3_tlbsel_q(1) + and not(ex4_ieratwe or ex5_ieratwe or ex6_ieratwe)); +ex4_parerr_enab <= (ex4_parerr_q(thdid_width) and ex4_rd_data_parerr_epn) or + (ex4_parerr_q(thdid_width+1) and ex4_rd_data_parerr_rpn); +ex4_ieen_d(0 TO thdid_width-1) <= (ex3_parerr_q(0 to thdid_width-1) and (0 to thdid_width-1 => ex3_parerr_enab) and not(xu_ex3_flush)) + when (ex3_ttype_q(2)='1' ) + else (iu2_valid_q and not iu2_n_flush_req_q) + when (iu2_multihit_sig='1' or iu2_parerr_sig='1') + else (others => '0'); +ex4_ieen_d(thdid_width TO thdid_width+num_entry_log2-1) <= ex3_eratsx_data_q(2 to 2+num_entry_log2-1) + when (ex3_ttype_q(2)='1') + else ex3_ra_entry_q + when (ex3_ttype_q(0)='1' and ex3_ws_q="00" and ex3_tlbsel_q=TlbSel_IErat) + else ex3_ra_entry_q + when (ex3_ttype_q(0)='1' and (ex3_ws_q="01" or ex3_ws_q="10") and ex3_tlbsel_q=TlbSel_IErat) + else ex3_eratsx_data_q(2 to 2+num_entry_log2-1) + when (iu2_multihit_sig='1' or iu2_parerr_sig='1') + else (others => '0'); +ex5_ieen_d(0 TO thdid_width-1) <= (ex4_ieen_q(0 to thdid_width-1) and not(xu_ex4_flush)) or + (ex4_parerr_q(0 to thdid_width-1) and (0 to thdid_width-1 => ex4_parerr_enab) and not(xu_ex4_flush)); +ex5_ieen_d(thdid_width TO thdid_width+num_entry_log2-1) <= ex4_ieen_q(thdid_width to thdid_width+num_entry_log2-1); +ex6_ieen_d <= or_reduce(ex5_ieen_q(0 to thdid_width-1)) & + ex5_ieen_q(thdid_width to thdid_width+num_entry_log2-1); +mchk_flash_inv_d(0) <= or_reduce(iu2_valid_q and not(xu_iu_flush) and not(iu2_n_flush_req_q)); +mchk_flash_inv_d(1) <= iu2_parerr_sig; +mchk_flash_inv_d(2) <= iu2_multihit_sig; +mchk_flash_inv_d(3) <= mchk_flash_inv_enab; +mchk_flash_inv_enab <= mchk_flash_inv_q(0) and (mchk_flash_inv_q(1) or mchk_flash_inv_q(2)) and not(ccr2_notlb_q) and not(xucr4_mmu_mchk_q); +iu1_flush_enab_d <= '1' when (tlb_rel_val_q(0 to 3)/="0000" and tlb_rel_val_q(4)='1') + else '1' when snoop_val_q(0 to 1)="11" + else '1' when (ex1_valid_q/="0000" and ex1_ttype_q(2)='1' and ex1_tlbsel_q=TlbSel_IErat) + else '1' when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_ws_q="00" and ex6_tlbsel_q=TlbSel_IErat) + else '1' when ((ex6_valid_q/="0000" and ex6_ttype_q(4 to 5)/="00") or mchk_flash_inv_enab='1' or mchk_flash_inv_q(3)='1') + else '0'; +iu2_n_flush_req_d <= (iu1_valid_q and not(iu_ierat_iu1_flush) and not(xu_iu_flush) and not(iu2_n_flush_req_q)) + when iu1_flush_enab_q='1' + else (iu1_valid_q and not(iu_ierat_iu1_flush) and not(xu_iu_flush) and not(iu2_n_flush_req_q) and not(tlb_miss_q)) + when (cam_hit='0' and ccr2_notlb_q=MMU_Mode_Value and ccr2_frat_paranoia_q(9)='0') + else (others => '0'); +hold_req_d(0) <= '1' when por_hold_req(0)='1' + else '0' when ccr2_frat_paranoia_q(9)='1' + else '0' when (xu_iu_flush(0)='1' or iu_ierat_iu1_flush(0)='1') + else '0' when (tlb_rel_val_q(0)='1' and ccr2_notlb_q=MMU_Mode_Value) + else '1' when (cam_hit='0' and iu1_valid_q(0)='1' + and iu_ierat_iu1_flush(0)='0' and xu_iu_flush(0)='0' and iu1_flush_enab_q='0' + and iu2_n_flush_req_q(0)='0' and tlb_miss_q(0)='0' and ccr2_notlb_q=MMU_Mode_Value) + else '1' when (iu1_valid_q(0)='1' and iu_ierat_iu1_flush(0)='0' and xu_iu_flush(0)='0' and iu1_flush_enab_q='0' + and iu2_n_flush_req_q(0)='0' and tlb_miss_q(0)='1' and ccr2_notlb_q=MMU_Mode_Value) + else hold_req_q(0); +hold_req_d(1) <= '1' when por_hold_req(1)='1' + else '0' when ccr2_frat_paranoia_q(9)='1' + else '0' when (xu_iu_flush(1)='1' or iu_ierat_iu1_flush(1)='1') + else '0' when (tlb_rel_val_q(1)='1' and ccr2_notlb_q=MMU_Mode_Value) + else '1' when (cam_hit='0' and iu1_valid_q(1)='1' + and iu_ierat_iu1_flush(1)='0' and xu_iu_flush(1)='0' and iu1_flush_enab_q='0' + and iu2_n_flush_req_q(1)='0' and tlb_miss_q(1)='0' and ccr2_notlb_q=MMU_Mode_Value) + else '1' when (iu1_valid_q(1)='1' and iu_ierat_iu1_flush(1)='0' and xu_iu_flush(1)='0' and iu1_flush_enab_q='0' + and iu2_n_flush_req_q(1)='0' and tlb_miss_q(1)='1' and ccr2_notlb_q=MMU_Mode_Value) + else hold_req_q(1); +hold_req_d(2) <= '1' when por_hold_req(2)='1' + else '0' when ccr2_frat_paranoia_q(9)='1' + else '0' when (xu_iu_flush(2)='1' or iu_ierat_iu1_flush(2)='1') + else '0' when (tlb_rel_val_q(2)='1' and ccr2_notlb_q=MMU_Mode_Value) + else '1' when (cam_hit='0' and iu1_valid_q(2)='1' + and iu_ierat_iu1_flush(2)='0' and xu_iu_flush(2)='0' and iu1_flush_enab_q='0' + and iu2_n_flush_req_q(2)='0' and tlb_miss_q(2)='0' and ccr2_notlb_q=MMU_Mode_Value) + else '1' when (iu1_valid_q(2)='1' and iu_ierat_iu1_flush(2)='0' and xu_iu_flush(2)='0' and iu1_flush_enab_q='0' + and iu2_n_flush_req_q(2)='0' and tlb_miss_q(2)='1' and ccr2_notlb_q=MMU_Mode_Value) + else hold_req_q(2); +hold_req_d(3) <= '1' when por_hold_req(3)='1' + else '0' when ccr2_frat_paranoia_q(9)='1' + else '0' when (xu_iu_flush(3)='1' or iu_ierat_iu1_flush(3)='1') + else '0' when (tlb_rel_val_q(3)='1' and ccr2_notlb_q=MMU_Mode_Value) + else '1' when (cam_hit='0' and iu1_valid_q(3)='1' + and iu_ierat_iu1_flush(3)='0' and xu_iu_flush(3)='0' and iu1_flush_enab_q='0' + and iu2_n_flush_req_q(3)='0' and tlb_miss_q(3)='0' and ccr2_notlb_q=MMU_Mode_Value) + else '1' when (iu1_valid_q(3)='1' and iu_ierat_iu1_flush(3)='0' and xu_iu_flush(3)='0' and iu1_flush_enab_q='0' + and iu2_n_flush_req_q(3)='0' and tlb_miss_q(3)='1' and ccr2_notlb_q=MMU_Mode_Value) + else hold_req_q(3); +tlb_miss_d(0) <= '0' when (ccr2_notlb_q/=MMU_Mode_Value or por_seq_q/=PorSeq_Idle or ccr2_frat_paranoia_q(9)='1') + else '0' when xu_iu_flush(0)='1' + else hold_req_q(0) when (tlb_miss_q(0)='0' and tlb_rel_val_q(0)='1' and tlb_rel_val_q(4)='0') + else tlb_miss_q(0); +tlb_miss_d(1) <= '0' when (ccr2_notlb_q/=MMU_Mode_Value or por_seq_q/=PorSeq_Idle or ccr2_frat_paranoia_q(9)='1') + else '0' when xu_iu_flush(1)='1' + else hold_req_q(1) when (tlb_miss_q(1)='0' and tlb_rel_val_q(1)='1' and tlb_rel_val_q(4)='0') + else tlb_miss_q(1); +tlb_miss_d(2) <= '0' when (ccr2_notlb_q/=MMU_Mode_Value or por_seq_q/=PorSeq_Idle or ccr2_frat_paranoia_q(9)='1') + else '0' when xu_iu_flush(2)='1' + else hold_req_q(2) when (tlb_miss_q(2)='0' and tlb_rel_val_q(2)='1' and tlb_rel_val_q(4)='0') + else tlb_miss_q(2); +tlb_miss_d(3) <= '0' when (ccr2_notlb_q/=MMU_Mode_Value or por_seq_q/=PorSeq_Idle or ccr2_frat_paranoia_q(9)='1') + else '0' when xu_iu_flush(3)='1' + else hold_req_q(3) when (tlb_miss_q(3)='0' and tlb_rel_val_q(3)='1' and tlb_rel_val_q(4)='0') + else tlb_miss_q(3); +tlb_req_inprogress_d(0) <= '0' when (ccr2_frat_paranoia_q(9)='1' or por_hold_req(0)='1' or ccr2_notlb_q/=MMU_Mode_Value or tlb_rel_val_q(0)='1') + else '0' when (xu_iu_flush(0)='0' and iu2_valid_q(0)='1' and hold_req_q(0)='0') + else '1' when (iu2_tlbreq_q='1' and iu2_valid_q(0)='1' and ccr2_notlb_q=MMU_Mode_Value) + else tlb_req_inprogress_q(0); +tlb_req_inprogress_d(1) <= '0' when (ccr2_frat_paranoia_q(9)='1' or por_hold_req(1)='1' or ccr2_notlb_q/=MMU_Mode_Value or tlb_rel_val_q(1)='1') + else '0' when (xu_iu_flush(1)='0' and iu2_valid_q(1)='1' and hold_req_q(1)='0') + else '1' when (iu2_tlbreq_q='1' and iu2_valid_q(1)='1' and ccr2_notlb_q=MMU_Mode_Value) + else tlb_req_inprogress_q(1); +tlb_req_inprogress_d(2) <= '0' when (ccr2_frat_paranoia_q(9)='1' or por_hold_req(2)='1' or ccr2_notlb_q/=MMU_Mode_Value or tlb_rel_val_q(2)='1') + else '0' when (xu_iu_flush(2)='0' and iu2_valid_q(2)='1' and hold_req_q(2)='0') + else '1' when (iu2_tlbreq_q='1' and iu2_valid_q(2)='1' and ccr2_notlb_q=MMU_Mode_Value) + else tlb_req_inprogress_q(2); +tlb_req_inprogress_d(3) <= '0' when (ccr2_frat_paranoia_q(9)='1' or por_hold_req(3)='1' or ccr2_notlb_q/=MMU_Mode_Value or tlb_rel_val_q(3)='1') + else '0' when (xu_iu_flush(3)='0' and iu2_valid_q(3)='1' and hold_req_q(3)='0') + else '1' when (iu2_tlbreq_q='1' and iu2_valid_q(3)='1' and ccr2_notlb_q=MMU_Mode_Value) + else tlb_req_inprogress_q(3); +iu2_tlbreq_d <= '1' when (cam_hit='0' and iu1_flush_enab_q='0' and ccr2_notlb_q=MMU_Mode_Value and ccr2_frat_paranoia_q(9)='0' and + (iu1_valid_q and not(iu_ierat_iu1_flush) and not(xu_iu_flush) and not(iu2_n_flush_req_q) and not(tlb_miss_q) and not(hold_req_q))/="0000") + else '0'; +snoop_val_d(0) <= mm_iu_ierat_snoop_val when snoop_val_q(0)='0' + else '0' when (tlb_rel_val_q(4)='0' and snoop_val_q(1)='1') + else snoop_val_q(0); +snoop_val_d(1) <= not iu_ierat_ium1_back_inv; +snoop_val_d(2) <= '0' when (tlb_rel_val_q(4)='1' or snoop_val_q(1)='0') + else snoop_val_q(0); +snoop_attr_d <= mm_iu_ierat_snoop_attr when snoop_val_q(0)='0' + else snoop_attr_q; +snoop_addr_d <= mm_iu_ierat_snoop_vpn when snoop_val_q(0)='0' + else snoop_addr_q; +iu_mm_ierat_snoop_ack <= snoop_val_q(2); +gen64_holdreg: if rs_data_width = 64 generate +rpn_holdreg0_d(0 TO 19) <= ex6_data_in_q(0 to 19) when (ex6_valid_q(0)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='1') + else ex6_data_in_q(32 to 51) when (ex6_valid_q(0)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='0') + else rpn_holdreg0_q(0 to 19); +rpn_holdreg0_d(20 TO 31) <= ex6_data_in_q(20 to 31) when (ex6_valid_q(0)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='1') + else ex6_data_in_q(52 to 63) when (ex6_valid_q(0)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='0') + else rpn_holdreg0_q(20 to 31); +rpn_holdreg0_d(32 TO 51) <= ex6_data_in_q(32 to 51) when (ex6_valid_q(0)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='1') + else ex6_data_in_q(32 to 51) when (ex6_valid_q(0)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='0') + else rpn_holdreg0_q(32 to 51); +rpn_holdreg0_d(52 TO 63) <= ex6_data_in_q(52 to 63) when (ex6_valid_q(0)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='1') + else ex6_data_in_q(52 to 63) when (ex6_valid_q(0)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='0') + else rpn_holdreg0_q(52 to 63); +rpn_holdreg1_d(0 TO 19) <= ex6_data_in_q(0 to 19) when (ex6_valid_q(1)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='1') + else ex6_data_in_q(32 to 51) when (ex6_valid_q(1)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='0') + else rpn_holdreg1_q(0 to 19); +rpn_holdreg1_d(20 TO 31) <= ex6_data_in_q(20 to 31) when (ex6_valid_q(1)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='1') + else ex6_data_in_q(52 to 63) when (ex6_valid_q(1)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='0') + else rpn_holdreg1_q(20 to 31); +rpn_holdreg1_d(32 TO 51) <= ex6_data_in_q(32 to 51) when (ex6_valid_q(1)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='1') + else ex6_data_in_q(32 to 51) when (ex6_valid_q(1)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='0') + else rpn_holdreg1_q(32 to 51); +rpn_holdreg1_d(52 TO 63) <= ex6_data_in_q(52 to 63) when (ex6_valid_q(1)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='1') + else ex6_data_in_q(52 to 63) when (ex6_valid_q(1)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='0') + else rpn_holdreg1_q(52 to 63); +rpn_holdreg2_d(0 TO 19) <= ex6_data_in_q(0 to 19) when (ex6_valid_q(2)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='1') + else ex6_data_in_q(32 to 51) when (ex6_valid_q(2)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='0') + else rpn_holdreg2_q(0 to 19); +rpn_holdreg2_d(20 TO 31) <= ex6_data_in_q(20 to 31) when (ex6_valid_q(2)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='1') + else ex6_data_in_q(52 to 63) when (ex6_valid_q(2)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='0') + else rpn_holdreg2_q(20 to 31); +rpn_holdreg2_d(32 TO 51) <= ex6_data_in_q(32 to 51) when (ex6_valid_q(2)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='1') + else ex6_data_in_q(32 to 51) when (ex6_valid_q(2)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='0') + else rpn_holdreg2_q(32 to 51); +rpn_holdreg2_d(52 TO 63) <= ex6_data_in_q(52 to 63) when (ex6_valid_q(2)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='1') + else ex6_data_in_q(52 to 63) when (ex6_valid_q(2)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='0') + else rpn_holdreg2_q(52 to 63); +rpn_holdreg3_d(0 TO 19) <= ex6_data_in_q(0 to 19) when (ex6_valid_q(3)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='1') + else ex6_data_in_q(32 to 51) when (ex6_valid_q(3)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='0') + else rpn_holdreg3_q(0 to 19); +rpn_holdreg3_d(20 TO 31) <= ex6_data_in_q(20 to 31) when (ex6_valid_q(3)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='1') + else ex6_data_in_q(52 to 63) when (ex6_valid_q(3)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='0') + else rpn_holdreg3_q(20 to 31); +rpn_holdreg3_d(32 TO 51) <= ex6_data_in_q(32 to 51) when (ex6_valid_q(3)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='1') + else ex6_data_in_q(32 to 51) when (ex6_valid_q(3)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='0') + else rpn_holdreg3_q(32 to 51); +rpn_holdreg3_d(52 TO 63) <= ex6_data_in_q(52 to 63) when (ex6_valid_q(3)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='1') + else ex6_data_in_q(52 to 63) when (ex6_valid_q(3)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='0') + else rpn_holdreg3_q(52 to 63); +end generate gen64_holdreg; +gen32_holdreg: if rs_data_width = 32 generate +rpn_holdreg0_d(32 TO 51) <= ex6_data_in_q(32 to 51) when (ex6_valid_q(0)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat) + else rpn_holdreg0_q(32 to 51); +rpn_holdreg0_d(20 TO 31) <= ex6_data_in_q(52 to 63) when (ex6_valid_q(0)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat) + else rpn_holdreg0_q(20 to 31); +rpn_holdreg0_d(52 TO 63) <= ex6_data_in_q(52 to 63) when (ex6_valid_q(0)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_IErat) + else rpn_holdreg0_q(52 to 63); +rpn_holdreg0_d(0 TO 19) <= ex6_data_in_q(32 to 51) when (ex6_valid_q(0)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_IErat) + else rpn_holdreg0_q(0 to 19); +rpn_holdreg1_d(32 TO 51) <= ex6_data_in_q(32 to 51) when (ex6_valid_q(1)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat) + else rpn_holdreg1_q(32 to 51); +rpn_holdreg1_d(20 TO 31) <= ex6_data_in_q(52 to 63) when (ex6_valid_q(1)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat) + else rpn_holdreg1_q(20 to 31); +rpn_holdreg1_d(52 TO 63) <= ex6_data_in_q(52 to 63) when (ex6_valid_q(1)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_IErat) + else rpn_holdreg1_q(52 to 63); +rpn_holdreg1_d(0 TO 19) <= ex6_data_in_q(32 to 51) when (ex6_valid_q(1)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_IErat) + else rpn_holdreg1_q(0 to 19); +rpn_holdreg2_d(32 TO 51) <= ex6_data_in_q(32 to 51) when (ex6_valid_q(2)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat) + else rpn_holdreg2_q(32 to 51); +rpn_holdreg2_d(20 TO 31) <= ex6_data_in_q(52 to 63) when (ex6_valid_q(2)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat) + else rpn_holdreg2_q(20 to 31); +rpn_holdreg2_d(52 TO 63) <= ex6_data_in_q(52 to 63) when (ex6_valid_q(2)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_IErat) + else rpn_holdreg2_q(52 to 63); +rpn_holdreg2_d(0 TO 19) <= ex6_data_in_q(32 to 51) when (ex6_valid_q(2)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_IErat) + else rpn_holdreg2_q(0 to 19); +rpn_holdreg3_d(32 TO 51) <= ex6_data_in_q(32 to 51) when (ex6_valid_q(3)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat) + else rpn_holdreg3_q(32 to 51); +rpn_holdreg3_d(20 TO 31) <= ex6_data_in_q(52 to 63) when (ex6_valid_q(3)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat) + else rpn_holdreg3_q(20 to 31); +rpn_holdreg3_d(52 TO 63) <= ex6_data_in_q(52 to 63) when (ex6_valid_q(3)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_IErat) + else rpn_holdreg3_q(52 to 63); +rpn_holdreg3_d(0 TO 19) <= ex6_data_in_q(32 to 51) when (ex6_valid_q(3)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_IErat) + else rpn_holdreg3_q(0 to 19); +end generate gen32_holdreg; +ex6_ieratwe_ws3 <= or_reduce(ex6_valid_q) and ex6_ttype_q(1) and Eq(ex6_ws_q,"11") and Eq(ex6_tlbsel_q,TlbSel_IErat); +watermark_d <= ex6_data_in_q(64-watermark_width to 63) when ex6_ieratwe_ws3='1' + else watermark_q; +eptr_d <= (others => '0') when (ex6_ieratwe_ws3='1' and mmucr1_q(0)='1') + else (others => '0') when (eptr_q="1111" or eptr_q=watermark_q) and + ( (ex6_valid_q /= "0000" and ex6_ttype_q(1)='1' and ex6_ws_q="00" and + ex6_tlbsel_q=TlbSel_IErat and mmucr1_q(0)='1') or + (tlb_rel_val_q(0 to 3)/="0000" and tlb_rel_val_q(4)='1' and + tlb_rel_data_q(eratpos_wren)='1' and mmucr1_q(0)='1') ) + else eptr_p1 when ( (ex6_valid_q /= "0000" and ex6_ttype_q(1)='1' and ex6_ws_q="00" and + ex6_tlbsel_q=TlbSel_IErat and mmucr1_q(0)='1') or + (tlb_rel_val_q(0 to 3)/="0000" and tlb_rel_val_q(4)='1' and + tlb_rel_data_q(eratpos_wren)='1' and mmucr1_q(0)='1') ) + else eptr_q; +eptr_p1 <= "0001" when eptr_q="0000" + else "0010" when eptr_q="0001" + else "0011" when eptr_q="0010" + else "0100" when eptr_q="0011" + else "0101" when eptr_q="0100" + else "0110" when eptr_q="0101" + else "0111" when eptr_q="0110" + else "1000" when eptr_q="0111" + else "1001" when eptr_q="1000" + else "1010" when eptr_q="1001" + else "1011" when eptr_q="1010" + else "1100" when eptr_q="1011" + else "1101" when eptr_q="1100" + else "1110" when eptr_q="1101" + else "1111" when eptr_q="1110" + else "0000"; +lru_way_is_written <= Eq(lru_way_encode, ex6_ra_entry_q); +lru_way_is_hit_entry <= Eq(lru_way_encode, iu1_first_hit_entry); +lru_update_event_d(0) <= ( tlb_rel_data_q(eratpos_wren) and or_reduce(tlb_rel_val_q(0 to 3)) and tlb_rel_val_q(4) ); +lru_update_event_d(1) <= ( snoop_val_q(0) and snoop_val_q(1) ); +lru_update_event_d(2) <= ( or_reduce(ex6_valid_q) and (ex6_ttype_q(4) or ex6_ttype_q(5)) ); +lru_update_event_d(3) <= ( or_reduce(ex6_valid_q) and ex6_ttype_q(1) and not ex6_ws_q(0) and not ex6_ws_q(1) + and ex6_tlbsel_q(0) and not ex6_tlbsel_q(1) and lru_way_is_written ); +lru_update_event_d(4) <= ( or_reduce(iu1_valid_q and not(iu_ierat_iu1_flush) and not(xu_iu_flush) and not(iu2_n_flush_req_q)) + and not iu1_flush_enab_q and cam_hit and lru_way_is_hit_entry ); +lru_update_event_d(5) <= lru_update_event_q(0) or lru_update_event_q(3); +lru_update_event_d(6) <= lru_update_event_q(1) or lru_update_event_q(2); +lru_update_event_d(7) <= ( or_reduce(iu1_valid_q and not(iu_ierat_iu1_flush) and not(xu_iu_flush) and not(iu2_n_flush_req_q)) + and not iu1_flush_enab_q and cam_hit and lru_way_is_hit_entry ); +lru_update_event_d(8) <= lru_update_event_q(0) or lru_update_event_q(1) or lru_update_event_q(2) or lru_update_event_q(3); +lru_d(1) <= '0' when ((ex6_ieratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(1)='1' and mmucr1_q(0)='0' and lru_op_vec(1)='0' and ccr2_frat_paranoia_q(9)='0' and + (lru_update_event_q(8)='1' or (lru_update_event_q(4) and not(iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig))='1') + else '1' when lru_set_vec(1)='1' and mmucr1_q(0)='0' and lru_op_vec(1)='0' and ccr2_frat_paranoia_q(9)='0' and + (lru_update_event_q(8)='1' or (lru_update_event_q(4) and not(iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig))='1') + else lru_q(1); +lru_eff(1) <= (lru_vp_vec(1) and lru_op_vec(1)) or (lru_q(1) and not lru_op_vec(1)); +lru_d(2) <= '0' when ((ex6_ieratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(2)='1' and mmucr1_q(0)='0' and lru_op_vec(2)='0' and ccr2_frat_paranoia_q(9)='0' and + (lru_update_event_q(8)='1' or (lru_update_event_q(4) and not(iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig))='1') + else '1' when lru_set_vec(2)='1' and mmucr1_q(0)='0' and lru_op_vec(2)='0' and ccr2_frat_paranoia_q(9)='0' and + (lru_update_event_q(8)='1' or (lru_update_event_q(4) and not(iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig))='1') + else lru_q(2); +lru_eff(2) <= (lru_vp_vec(2) and lru_op_vec(2)) or (lru_q(2) and not lru_op_vec(2)); +lru_d(3) <= '0' when ((ex6_ieratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(3)='1' and mmucr1_q(0)='0' and lru_op_vec(3)='0' and ccr2_frat_paranoia_q(9)='0' and + (lru_update_event_q(8)='1' or (lru_update_event_q(4) and not(iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig))='1') + else '1' when lru_set_vec(3)='1' and mmucr1_q(0)='0' and lru_op_vec(3)='0' and ccr2_frat_paranoia_q(9)='0' and + (lru_update_event_q(8)='1' or (lru_update_event_q(4) and not(iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig))='1') + else lru_q(3); +lru_eff(3) <= (lru_vp_vec(3) and lru_op_vec(3)) or (lru_q(3) and not lru_op_vec(3)); +lru_d(4) <= '0' when ((ex6_ieratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(4)='1' and mmucr1_q(0)='0' and lru_op_vec(4)='0' and ccr2_frat_paranoia_q(9)='0' and + (lru_update_event_q(8)='1' or (lru_update_event_q(4) and not(iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig))='1') + else '1' when lru_set_vec(4)='1' and mmucr1_q(0)='0' and lru_op_vec(4)='0' and ccr2_frat_paranoia_q(9)='0' and + (lru_update_event_q(8)='1' or (lru_update_event_q(4) and not(iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig))='1') + else lru_q(4); +lru_eff(4) <= (lru_vp_vec(4) and lru_op_vec(4)) or (lru_q(4) and not lru_op_vec(4)); +lru_d(5) <= '0' when ((ex6_ieratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(5)='1' and mmucr1_q(0)='0' and lru_op_vec(5)='0' and ccr2_frat_paranoia_q(9)='0' and + (lru_update_event_q(8)='1' or (lru_update_event_q(4) and not(iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig))='1') + else '1' when lru_set_vec(5)='1' and mmucr1_q(0)='0' and lru_op_vec(5)='0' and ccr2_frat_paranoia_q(9)='0' and + (lru_update_event_q(8)='1' or (lru_update_event_q(4) and not(iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig))='1') + else lru_q(5); +lru_eff(5) <= (lru_vp_vec(5) and lru_op_vec(5)) or (lru_q(5) and not lru_op_vec(5)); +lru_d(6) <= '0' when ((ex6_ieratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(6)='1' and mmucr1_q(0)='0' and lru_op_vec(6)='0' and ccr2_frat_paranoia_q(9)='0' and + (lru_update_event_q(8)='1' or (lru_update_event_q(4) and not(iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig))='1') + else '1' when lru_set_vec(6)='1' and mmucr1_q(0)='0' and lru_op_vec(6)='0' and ccr2_frat_paranoia_q(9)='0' and + (lru_update_event_q(8)='1' or (lru_update_event_q(4) and not(iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig))='1') + else lru_q(6); +lru_eff(6) <= (lru_vp_vec(6) and lru_op_vec(6)) or (lru_q(6) and not lru_op_vec(6)); +lru_d(7) <= '0' when ((ex6_ieratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(7)='1' and mmucr1_q(0)='0' and lru_op_vec(7)='0' and ccr2_frat_paranoia_q(9)='0' and + (lru_update_event_q(8)='1' or (lru_update_event_q(4) and not(iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig))='1') + else '1' when lru_set_vec(7)='1' and mmucr1_q(0)='0' and lru_op_vec(7)='0' and ccr2_frat_paranoia_q(9)='0' and + (lru_update_event_q(8)='1' or (lru_update_event_q(4) and not(iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig))='1') + else lru_q(7); +lru_eff(7) <= (lru_vp_vec(7) and lru_op_vec(7)) or (lru_q(7) and not lru_op_vec(7)); +lru_d(8) <= '0' when ((ex6_ieratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(8)='1' and mmucr1_q(0)='0' and lru_op_vec(8)='0' and ccr2_frat_paranoia_q(9)='0' and + (lru_update_event_q(8)='1' or (lru_update_event_q(4) and not(iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig))='1') + else '1' when lru_set_vec(8)='1' and mmucr1_q(0)='0' and lru_op_vec(8)='0' and ccr2_frat_paranoia_q(9)='0' and + (lru_update_event_q(8)='1' or (lru_update_event_q(4) and not(iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig))='1') + else lru_q(8); +lru_eff(8) <= (lru_vp_vec(8) and lru_op_vec(8)) or (lru_q(8) and not lru_op_vec(8)); +lru_d(9) <= '0' when ((ex6_ieratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(9)='1' and mmucr1_q(0)='0' and lru_op_vec(9)='0' and ccr2_frat_paranoia_q(9)='0' and + (lru_update_event_q(8)='1' or (lru_update_event_q(4) and not(iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig))='1') + else '1' when lru_set_vec(9)='1' and mmucr1_q(0)='0' and lru_op_vec(9)='0' and ccr2_frat_paranoia_q(9)='0' and + (lru_update_event_q(8)='1' or (lru_update_event_q(4) and not(iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig))='1') + else lru_q(9); +lru_eff(9) <= (lru_vp_vec(9) and lru_op_vec(9)) or (lru_q(9) and not lru_op_vec(9)); +lru_d(10) <= '0' when ((ex6_ieratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(10)='1' and mmucr1_q(0)='0' and lru_op_vec(10)='0' and ccr2_frat_paranoia_q(9)='0' and + (lru_update_event_q(8)='1' or (lru_update_event_q(4) and not(iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig))='1') + else '1' when lru_set_vec(10)='1' and mmucr1_q(0)='0' and lru_op_vec(10)='0' and ccr2_frat_paranoia_q(9)='0' and + (lru_update_event_q(8)='1' or (lru_update_event_q(4) and not(iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig))='1') + else lru_q(10); +lru_eff(10) <= (lru_vp_vec(10) and lru_op_vec(10)) or (lru_q(10) and not lru_op_vec(10)); +lru_d(11) <= '0' when ((ex6_ieratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(11)='1' and mmucr1_q(0)='0' and lru_op_vec(11)='0' and ccr2_frat_paranoia_q(9)='0' and + (lru_update_event_q(8)='1' or (lru_update_event_q(4) and not(iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig))='1') + else '1' when lru_set_vec(11)='1' and mmucr1_q(0)='0' and lru_op_vec(11)='0' and ccr2_frat_paranoia_q(9)='0' and + (lru_update_event_q(8)='1' or (lru_update_event_q(4) and not(iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig))='1') + else lru_q(11); +lru_eff(11) <= (lru_vp_vec(11) and lru_op_vec(11)) or (lru_q(11) and not lru_op_vec(11)); +lru_d(12) <= '0' when ((ex6_ieratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(12)='1' and mmucr1_q(0)='0' and lru_op_vec(12)='0' and ccr2_frat_paranoia_q(9)='0' and + (lru_update_event_q(8)='1' or (lru_update_event_q(4) and not(iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig))='1') + else '1' when lru_set_vec(12)='1' and mmucr1_q(0)='0' and lru_op_vec(12)='0' and ccr2_frat_paranoia_q(9)='0' and + (lru_update_event_q(8)='1' or (lru_update_event_q(4) and not(iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig))='1') + else lru_q(12); +lru_eff(12) <= (lru_vp_vec(12) and lru_op_vec(12)) or (lru_q(12) and not lru_op_vec(12)); +lru_d(13) <= '0' when ((ex6_ieratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(13)='1' and mmucr1_q(0)='0' and lru_op_vec(13)='0' and ccr2_frat_paranoia_q(9)='0' and + (lru_update_event_q(8)='1' or (lru_update_event_q(4) and not(iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig))='1') + else '1' when lru_set_vec(13)='1' and mmucr1_q(0)='0' and lru_op_vec(13)='0' and ccr2_frat_paranoia_q(9)='0' and + (lru_update_event_q(8)='1' or (lru_update_event_q(4) and not(iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig))='1') + else lru_q(13); +lru_eff(13) <= (lru_vp_vec(13) and lru_op_vec(13)) or (lru_q(13) and not lru_op_vec(13)); +lru_d(14) <= '0' when ((ex6_ieratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(14)='1' and mmucr1_q(0)='0' and lru_op_vec(14)='0' and ccr2_frat_paranoia_q(9)='0' and + (lru_update_event_q(8)='1' or (lru_update_event_q(4) and not(iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig))='1') + else '1' when lru_set_vec(14)='1' and mmucr1_q(0)='0' and lru_op_vec(14)='0' and ccr2_frat_paranoia_q(9)='0' and + (lru_update_event_q(8)='1' or (lru_update_event_q(4) and not(iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig))='1') + else lru_q(14); +lru_eff(14) <= (lru_vp_vec(14) and lru_op_vec(14)) or (lru_q(14) and not lru_op_vec(14)); +lru_d(15) <= '0' when ((ex6_ieratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(15)='1' and mmucr1_q(0)='0' and lru_op_vec(15)='0' and ccr2_frat_paranoia_q(9)='0' and + (lru_update_event_q(8)='1' or (lru_update_event_q(4) and not(iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig))='1') + else '1' when lru_set_vec(15)='1' and mmucr1_q(0)='0' and lru_op_vec(15)='0' and ccr2_frat_paranoia_q(9)='0' and + (lru_update_event_q(8)='1' or (lru_update_event_q(4) and not(iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig))='1') + else lru_q(15); +lru_eff(15) <= (lru_vp_vec(15) and lru_op_vec(15)) or (lru_q(15) and not lru_op_vec(15)); +lru_op_vec(1) <= (lru_rmt_vec(0) or lru_rmt_vec(1) or lru_rmt_vec(2) or lru_rmt_vec(3) or + lru_rmt_vec(4) or lru_rmt_vec(5) or lru_rmt_vec(6) or lru_rmt_vec(7)) xor + (lru_rmt_vec(8) or lru_rmt_vec(9) or lru_rmt_vec(10) or lru_rmt_vec(11) or + lru_rmt_vec(12) or lru_rmt_vec(13) or lru_rmt_vec(14) or lru_rmt_vec(15)); +lru_op_vec(2) <= (lru_rmt_vec(0) or lru_rmt_vec(1) or lru_rmt_vec(2) or lru_rmt_vec(3)) xor + (lru_rmt_vec(4) or lru_rmt_vec(5) or lru_rmt_vec(6) or lru_rmt_vec(7)); +lru_op_vec(3) <= (lru_rmt_vec(8) or lru_rmt_vec(9) or lru_rmt_vec(10) or lru_rmt_vec(11)) xor + (lru_rmt_vec(12) or lru_rmt_vec(13) or lru_rmt_vec(14) or lru_rmt_vec(15)); +lru_op_vec(4) <= (lru_rmt_vec(0) or lru_rmt_vec(1)) xor (lru_rmt_vec(2) or lru_rmt_vec(3)); +lru_op_vec(5) <= (lru_rmt_vec(4) or lru_rmt_vec(5)) xor (lru_rmt_vec(6) or lru_rmt_vec(7)); +lru_op_vec(6) <= (lru_rmt_vec(8) or lru_rmt_vec(9)) xor (lru_rmt_vec(10) or lru_rmt_vec(11)); +lru_op_vec(7) <= (lru_rmt_vec(12) or lru_rmt_vec(13)) xor (lru_rmt_vec(14) or lru_rmt_vec(15)); +lru_op_vec(8) <= lru_rmt_vec(0) xor lru_rmt_vec(1); +lru_op_vec(9) <= lru_rmt_vec(2) xor lru_rmt_vec(3); +lru_op_vec(10) <= lru_rmt_vec(4) xor lru_rmt_vec(5); +lru_op_vec(11) <= lru_rmt_vec(6) xor lru_rmt_vec(7); +lru_op_vec(12) <= lru_rmt_vec(8) xor lru_rmt_vec(9); +lru_op_vec(13) <= lru_rmt_vec(10) xor lru_rmt_vec(11); +lru_op_vec(14) <= lru_rmt_vec(12) xor lru_rmt_vec(13); +lru_op_vec(15) <= lru_rmt_vec(14) xor lru_rmt_vec(15); +lru_vp_vec(1) <= (lru_rmt_vec(8) or lru_rmt_vec(9) or lru_rmt_vec(10) or lru_rmt_vec(11) or + lru_rmt_vec(12) or lru_rmt_vec(13) or lru_rmt_vec(14) or lru_rmt_vec(15)); +lru_vp_vec(2) <= (lru_rmt_vec(4) or lru_rmt_vec(5) or lru_rmt_vec(6) or lru_rmt_vec(7)); +lru_vp_vec(3) <= (lru_rmt_vec(12) or lru_rmt_vec(13) or lru_rmt_vec(14) or lru_rmt_vec(15)); +lru_vp_vec(4) <= (lru_rmt_vec(2) or lru_rmt_vec(3)); +lru_vp_vec(5) <= (lru_rmt_vec(6) or lru_rmt_vec(7)); +lru_vp_vec(6) <= (lru_rmt_vec(10) or lru_rmt_vec(11)); +lru_vp_vec(7) <= (lru_rmt_vec(14) or lru_rmt_vec(15)); +lru_vp_vec(8) <= lru_rmt_vec(1); +lru_vp_vec(9) <= lru_rmt_vec(3); +lru_vp_vec(10) <= lru_rmt_vec(5); +lru_vp_vec(11) <= lru_rmt_vec(7); +lru_vp_vec(12) <= lru_rmt_vec(9); +lru_vp_vec(13) <= lru_rmt_vec(11); +lru_vp_vec(14) <= lru_rmt_vec(13); +lru_vp_vec(15) <= lru_rmt_vec(15); +MQQ37:LRU_RMT_VEC_PT(1) <= + Eq(( WATERMARK_Q(0) & WATERMARK_Q(1) & + WATERMARK_Q(2) & WATERMARK_Q(3) + ) , STD_ULOGIC_VECTOR'("1111")); +MQQ38:LRU_RMT_VEC_PT(2) <= + Eq(( WATERMARK_Q(1) & WATERMARK_Q(2) & + WATERMARK_Q(3) ) , STD_ULOGIC_VECTOR'("111")); +MQQ39:LRU_RMT_VEC_PT(3) <= + Eq(( WATERMARK_Q(0) & WATERMARK_Q(2) & + WATERMARK_Q(3) ) , STD_ULOGIC_VECTOR'("111")); +MQQ40:LRU_RMT_VEC_PT(4) <= + Eq(( WATERMARK_Q(2) & WATERMARK_Q(3) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ41:LRU_RMT_VEC_PT(5) <= + Eq(( WATERMARK_Q(0) & WATERMARK_Q(1) & + WATERMARK_Q(3) ) , STD_ULOGIC_VECTOR'("111")); +MQQ42:LRU_RMT_VEC_PT(6) <= + Eq(( WATERMARK_Q(1) & WATERMARK_Q(3) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ43:LRU_RMT_VEC_PT(7) <= + Eq(( WATERMARK_Q(0) & WATERMARK_Q(3) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ44:LRU_RMT_VEC_PT(8) <= + Eq(( WATERMARK_Q(3) ) , STD_ULOGIC'('1')); +MQQ45:LRU_RMT_VEC_PT(9) <= + Eq(( WATERMARK_Q(0) & WATERMARK_Q(1) & + WATERMARK_Q(2) ) , STD_ULOGIC_VECTOR'("111")); +MQQ46:LRU_RMT_VEC_PT(10) <= + Eq(( WATERMARK_Q(1) & WATERMARK_Q(2) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ47:LRU_RMT_VEC_PT(11) <= + Eq(( WATERMARK_Q(0) & WATERMARK_Q(2) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ48:LRU_RMT_VEC_PT(12) <= + Eq(( WATERMARK_Q(2) ) , STD_ULOGIC'('1')); +MQQ49:LRU_RMT_VEC_PT(13) <= + Eq(( WATERMARK_Q(0) & WATERMARK_Q(1) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ50:LRU_RMT_VEC_PT(14) <= + Eq(( WATERMARK_Q(1) ) , STD_ULOGIC'('1')); +MQQ51:LRU_RMT_VEC_PT(15) <= + Eq(( WATERMARK_Q(0) ) , STD_ULOGIC'('1')); +MQQ52:LRU_RMT_VEC_PT(16) <= + Eq(( MMUCR1_Q(0) ) , STD_ULOGIC'('1')); +MQQ53:LRU_RMT_VEC_PT(17) <= + '1'; +MQQ54:LRU_RMT_VEC(0) <= + (LRU_RMT_VEC_PT(17)); +MQQ55:LRU_RMT_VEC(1) <= + (LRU_RMT_VEC_PT(8) OR LRU_RMT_VEC_PT(12) + OR LRU_RMT_VEC_PT(14) OR LRU_RMT_VEC_PT(15) + OR LRU_RMT_VEC_PT(16)); +MQQ56:LRU_RMT_VEC(2) <= + (LRU_RMT_VEC_PT(12) OR LRU_RMT_VEC_PT(14) + OR LRU_RMT_VEC_PT(15) OR LRU_RMT_VEC_PT(16) + ); +MQQ57:LRU_RMT_VEC(3) <= + (LRU_RMT_VEC_PT(4) OR LRU_RMT_VEC_PT(14) + OR LRU_RMT_VEC_PT(15) OR LRU_RMT_VEC_PT(16) + ); +MQQ58:LRU_RMT_VEC(4) <= + (LRU_RMT_VEC_PT(14) OR LRU_RMT_VEC_PT(15) + OR LRU_RMT_VEC_PT(16)); +MQQ59:LRU_RMT_VEC(5) <= + (LRU_RMT_VEC_PT(6) OR LRU_RMT_VEC_PT(10) + OR LRU_RMT_VEC_PT(15) OR LRU_RMT_VEC_PT(16) + ); +MQQ60:LRU_RMT_VEC(6) <= + (LRU_RMT_VEC_PT(10) OR LRU_RMT_VEC_PT(15) + OR LRU_RMT_VEC_PT(16)); +MQQ61:LRU_RMT_VEC(7) <= + (LRU_RMT_VEC_PT(2) OR LRU_RMT_VEC_PT(15) + OR LRU_RMT_VEC_PT(16)); +MQQ62:LRU_RMT_VEC(8) <= + (LRU_RMT_VEC_PT(15) OR LRU_RMT_VEC_PT(16) + ); +MQQ63:LRU_RMT_VEC(9) <= + (LRU_RMT_VEC_PT(7) OR LRU_RMT_VEC_PT(11) + OR LRU_RMT_VEC_PT(13) OR LRU_RMT_VEC_PT(16) + ); +MQQ64:LRU_RMT_VEC(10) <= + (LRU_RMT_VEC_PT(11) OR LRU_RMT_VEC_PT(13) + OR LRU_RMT_VEC_PT(16)); +MQQ65:LRU_RMT_VEC(11) <= + (LRU_RMT_VEC_PT(3) OR LRU_RMT_VEC_PT(13) + OR LRU_RMT_VEC_PT(16)); +MQQ66:LRU_RMT_VEC(12) <= + (LRU_RMT_VEC_PT(13) OR LRU_RMT_VEC_PT(16) + ); +MQQ67:LRU_RMT_VEC(13) <= + (LRU_RMT_VEC_PT(5) OR LRU_RMT_VEC_PT(9) + OR LRU_RMT_VEC_PT(16)); +MQQ68:LRU_RMT_VEC(14) <= + (LRU_RMT_VEC_PT(9) OR LRU_RMT_VEC_PT(16) + ); +MQQ69:LRU_RMT_VEC(15) <= + (LRU_RMT_VEC_PT(1) OR LRU_RMT_VEC_PT(16) + ); + +MQQ70:LRU_WATERMARK_MASK_PT(1) <= + Eq(( WATERMARK_Q(0) & WATERMARK_Q(1) & + WATERMARK_Q(2) & WATERMARK_Q(3) + ) , STD_ULOGIC_VECTOR'("0000")); +MQQ71:LRU_WATERMARK_MASK_PT(2) <= + Eq(( WATERMARK_Q(1) & WATERMARK_Q(2) & + WATERMARK_Q(3) ) , STD_ULOGIC_VECTOR'("000")); +MQQ72:LRU_WATERMARK_MASK_PT(3) <= + Eq(( WATERMARK_Q(0) & WATERMARK_Q(2) & + WATERMARK_Q(3) ) , STD_ULOGIC_VECTOR'("000")); +MQQ73:LRU_WATERMARK_MASK_PT(4) <= + Eq(( WATERMARK_Q(2) & WATERMARK_Q(3) + ) , STD_ULOGIC_VECTOR'("00")); +MQQ74:LRU_WATERMARK_MASK_PT(5) <= + Eq(( WATERMARK_Q(0) & WATERMARK_Q(1) & + WATERMARK_Q(3) ) , STD_ULOGIC_VECTOR'("000")); +MQQ75:LRU_WATERMARK_MASK_PT(6) <= + Eq(( WATERMARK_Q(1) & WATERMARK_Q(3) + ) , STD_ULOGIC_VECTOR'("00")); +MQQ76:LRU_WATERMARK_MASK_PT(7) <= + Eq(( WATERMARK_Q(0) & WATERMARK_Q(3) + ) , STD_ULOGIC_VECTOR'("00")); +MQQ77:LRU_WATERMARK_MASK_PT(8) <= + Eq(( WATERMARK_Q(3) ) , STD_ULOGIC'('0')); +MQQ78:LRU_WATERMARK_MASK_PT(9) <= + Eq(( WATERMARK_Q(0) & WATERMARK_Q(1) & + WATERMARK_Q(2) ) , STD_ULOGIC_VECTOR'("000")); +MQQ79:LRU_WATERMARK_MASK_PT(10) <= + Eq(( WATERMARK_Q(1) & WATERMARK_Q(2) + ) , STD_ULOGIC_VECTOR'("00")); +MQQ80:LRU_WATERMARK_MASK_PT(11) <= + Eq(( WATERMARK_Q(0) & WATERMARK_Q(2) + ) , STD_ULOGIC_VECTOR'("00")); +MQQ81:LRU_WATERMARK_MASK_PT(12) <= + Eq(( WATERMARK_Q(2) ) , STD_ULOGIC'('0')); +MQQ82:LRU_WATERMARK_MASK_PT(13) <= + Eq(( WATERMARK_Q(0) & WATERMARK_Q(1) + ) , STD_ULOGIC_VECTOR'("00")); +MQQ83:LRU_WATERMARK_MASK_PT(14) <= + Eq(( WATERMARK_Q(1) ) , STD_ULOGIC'('0')); +MQQ84:LRU_WATERMARK_MASK_PT(15) <= + Eq(( WATERMARK_Q(0) ) , STD_ULOGIC'('0')); +MQQ85:LRU_WATERMARK_MASK(0) <= + ('0'); +MQQ86:LRU_WATERMARK_MASK(1) <= + (LRU_WATERMARK_MASK_PT(1)); +MQQ87:LRU_WATERMARK_MASK(2) <= + (LRU_WATERMARK_MASK_PT(9)); +MQQ88:LRU_WATERMARK_MASK(3) <= + (LRU_WATERMARK_MASK_PT(5) OR LRU_WATERMARK_MASK_PT(9) + ); +MQQ89:LRU_WATERMARK_MASK(4) <= + (LRU_WATERMARK_MASK_PT(13)); +MQQ90:LRU_WATERMARK_MASK(5) <= + (LRU_WATERMARK_MASK_PT(3) OR LRU_WATERMARK_MASK_PT(13) + ); +MQQ91:LRU_WATERMARK_MASK(6) <= + (LRU_WATERMARK_MASK_PT(11) OR LRU_WATERMARK_MASK_PT(13) + ); +MQQ92:LRU_WATERMARK_MASK(7) <= + (LRU_WATERMARK_MASK_PT(7) OR LRU_WATERMARK_MASK_PT(11) + OR LRU_WATERMARK_MASK_PT(13)); +MQQ93:LRU_WATERMARK_MASK(8) <= + (LRU_WATERMARK_MASK_PT(15)); +MQQ94:LRU_WATERMARK_MASK(9) <= + (LRU_WATERMARK_MASK_PT(2) OR LRU_WATERMARK_MASK_PT(15) + ); +MQQ95:LRU_WATERMARK_MASK(10) <= + (LRU_WATERMARK_MASK_PT(10) OR LRU_WATERMARK_MASK_PT(15) + ); +MQQ96:LRU_WATERMARK_MASK(11) <= + (LRU_WATERMARK_MASK_PT(6) OR LRU_WATERMARK_MASK_PT(10) + OR LRU_WATERMARK_MASK_PT(15)); +MQQ97:LRU_WATERMARK_MASK(12) <= + (LRU_WATERMARK_MASK_PT(14) OR LRU_WATERMARK_MASK_PT(15) + ); +MQQ98:LRU_WATERMARK_MASK(13) <= + (LRU_WATERMARK_MASK_PT(4) OR LRU_WATERMARK_MASK_PT(14) + OR LRU_WATERMARK_MASK_PT(15)); +MQQ99:LRU_WATERMARK_MASK(14) <= + (LRU_WATERMARK_MASK_PT(12) OR LRU_WATERMARK_MASK_PT(14) + OR LRU_WATERMARK_MASK_PT(15)); +MQQ100:LRU_WATERMARK_MASK(15) <= + (LRU_WATERMARK_MASK_PT(8) OR LRU_WATERMARK_MASK_PT(12) + OR LRU_WATERMARK_MASK_PT(14) OR LRU_WATERMARK_MASK_PT(15) + ); + +entry_valid_watermarked <= entry_valid_q or lru_watermark_mask; +MQQ101:LRU_SET_RESET_VEC_PT(1) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) & + ENTRY_MATCH_Q(13) & ENTRY_MATCH_Q(14) & + ENTRY_MATCH_Q(15) ) , STD_ULOGIC_VECTOR'("00111111111111111110000000000000001")); +MQQ102:LRU_SET_RESET_VEC_PT(2) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) & + ENTRY_MATCH_Q(13) & ENTRY_MATCH_Q(14) + ) , STD_ULOGIC_VECTOR'("0011111111111111111000000000000001")); +MQQ103:LRU_SET_RESET_VEC_PT(3) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_MATCH_Q(0) & ENTRY_MATCH_Q(1) & + ENTRY_MATCH_Q(2) & ENTRY_MATCH_Q(3) & + ENTRY_MATCH_Q(4) & ENTRY_MATCH_Q(5) & + ENTRY_MATCH_Q(6) & ENTRY_MATCH_Q(7) & + ENTRY_MATCH_Q(8) & ENTRY_MATCH_Q(9) & + ENTRY_MATCH_Q(10) & ENTRY_MATCH_Q(11) & + ENTRY_MATCH_Q(12) & ENTRY_MATCH_Q(13) & + ENTRY_MATCH_Q(14) ) , STD_ULOGIC_VECTOR'("001111111111111111000000000000001")); +MQQ104:LRU_SET_RESET_VEC_PT(4) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) & + ENTRY_MATCH_Q(13) ) , STD_ULOGIC_VECTOR'("001111111111111111100000000000001")); +MQQ105:LRU_SET_RESET_VEC_PT(5) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(13) + ) , STD_ULOGIC_VECTOR'("001111111111111110000000000001")); +MQQ106:LRU_SET_RESET_VEC_PT(6) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) + ) , STD_ULOGIC_VECTOR'("00111111111111111110000000000001")); +MQQ107:LRU_SET_RESET_VEC_PT(7) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) ) , STD_ULOGIC_VECTOR'("0011111111111111111000000000001")); +MQQ108:LRU_SET_RESET_VEC_PT(8) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(11) + ) , STD_ULOGIC_VECTOR'("001111111111111000000001")); +MQQ109:LRU_SET_RESET_VEC_PT(9) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) + ) , STD_ULOGIC_VECTOR'("001111111111111111100000000001")); +MQQ110:LRU_SET_RESET_VEC_PT(10) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) ) , STD_ULOGIC_VECTOR'("00111111111111111110000000001")); +MQQ111:LRU_SET_RESET_VEC_PT(11) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(9) + ) , STD_ULOGIC_VECTOR'("0011111111111111111000000001")); +MQQ112:LRU_SET_RESET_VEC_PT(12) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) + ) , STD_ULOGIC_VECTOR'("0011111111111111111000000001")); +MQQ113:LRU_SET_RESET_VEC_PT(13) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) + ) , STD_ULOGIC_VECTOR'("00111111111000000001")); +MQQ114:LRU_SET_RESET_VEC_PT(14) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) ) , STD_ULOGIC_VECTOR'("001111111111111111100000001")); +MQQ115:LRU_SET_RESET_VEC_PT(15) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_MATCH_Q(7) + ) , STD_ULOGIC_VECTOR'("001111111111")); +MQQ116:LRU_SET_RESET_VEC_PT(16) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) + ) , STD_ULOGIC_VECTOR'("00111111111111111110000001")); +MQQ117:LRU_SET_RESET_VEC_PT(17) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) ) , STD_ULOGIC_VECTOR'("0011111111111111111000001")); +MQQ118:LRU_SET_RESET_VEC_PT(18) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(5) + ) , STD_ULOGIC_VECTOR'("001111111111111111100001")); +MQQ119:LRU_SET_RESET_VEC_PT(19) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) + ) , STD_ULOGIC_VECTOR'("001111111111111111100001")); +MQQ120:LRU_SET_RESET_VEC_PT(20) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) + ) , STD_ULOGIC_VECTOR'("00111111111111100001")); +MQQ121:LRU_SET_RESET_VEC_PT(21) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) ) , STD_ULOGIC_VECTOR'("00111111111111111110001")); +MQQ122:LRU_SET_RESET_VEC_PT(22) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_MATCH_Q(3) + ) , STD_ULOGIC_VECTOR'("00111111111111111111")); +MQQ123:LRU_SET_RESET_VEC_PT(23) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) + ) , STD_ULOGIC_VECTOR'("0011111111111111111001")); +MQQ124:LRU_SET_RESET_VEC_PT(24) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) + ) , STD_ULOGIC_VECTOR'("00111111111111111001")); +MQQ125:LRU_SET_RESET_VEC_PT(25) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_MATCH_Q(0) & ENTRY_MATCH_Q(1) + ) , STD_ULOGIC_VECTOR'("00111111111111111101")); +MQQ126:LRU_SET_RESET_VEC_PT(26) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_MATCH_Q(1) + ) , STD_ULOGIC_VECTOR'("00111111111111111111")); +MQQ127:LRU_SET_RESET_VEC_PT(27) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_MATCH_Q(0) + ) , STD_ULOGIC_VECTOR'("00111111111111111111")); +MQQ128:LRU_SET_RESET_VEC_PT(28) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + LRU_Q(1) & LRU_Q(3) & + LRU_Q(7) & LRU_Q(15) + ) , STD_ULOGIC_VECTOR'("11111111111111111110")); +MQQ129:LRU_SET_RESET_VEC_PT(29) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(15) & + LRU_Q(1) & LRU_Q(3) & + LRU_Q(7) & LRU_Q(15) + ) , STD_ULOGIC_VECTOR'("11111111111111111111")); +MQQ130:LRU_SET_RESET_VEC_PT(30) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + LRU_Q(1) & LRU_Q(3) & + LRU_Q(7) & LRU_Q(14) + ) , STD_ULOGIC_VECTOR'("11111111111111111100")); +MQQ131:LRU_SET_RESET_VEC_PT(31) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + LRU_Q(1) & LRU_Q(3) & + LRU_Q(7) & LRU_Q(14) + ) , STD_ULOGIC_VECTOR'("11111111111111111101")); +MQQ132:LRU_SET_RESET_VEC_PT(32) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + LRU_Q(1) & LRU_Q(3) & + LRU_Q(6) & LRU_Q(13) + ) , STD_ULOGIC_VECTOR'("11111111111111111010")); +MQQ133:LRU_SET_RESET_VEC_PT(33) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + LRU_Q(1) & LRU_Q(3) & + LRU_Q(6) & LRU_Q(13) + ) , STD_ULOGIC_VECTOR'("11111111111111111011")); +MQQ134:LRU_SET_RESET_VEC_PT(34) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + LRU_Q(1) & LRU_Q(3) & + LRU_Q(6) & LRU_Q(12) + ) , STD_ULOGIC_VECTOR'("11111111111111111000")); +MQQ135:LRU_SET_RESET_VEC_PT(35) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + LRU_Q(1) & LRU_Q(3) & + LRU_Q(6) & LRU_Q(12) + ) , STD_ULOGIC_VECTOR'("11111111111111111001")); +MQQ136:LRU_SET_RESET_VEC_PT(36) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + LRU_Q(1) & LRU_Q(2) & + LRU_Q(5) & LRU_Q(11) + ) , STD_ULOGIC_VECTOR'("11111111111111110110")); +MQQ137:LRU_SET_RESET_VEC_PT(37) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + LRU_Q(1) & LRU_Q(2) & + LRU_Q(5) & LRU_Q(11) + ) , STD_ULOGIC_VECTOR'("11111111111111110111")); +MQQ138:LRU_SET_RESET_VEC_PT(38) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + LRU_Q(1) & LRU_Q(2) & + LRU_Q(5) & LRU_Q(10) + ) , STD_ULOGIC_VECTOR'("11111111111111110100")); +MQQ139:LRU_SET_RESET_VEC_PT(39) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + LRU_Q(1) & LRU_Q(2) & + LRU_Q(5) & LRU_Q(10) + ) , STD_ULOGIC_VECTOR'("11111111111111110101")); +MQQ140:LRU_SET_RESET_VEC_PT(40) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + LRU_Q(1) & LRU_Q(2) & + LRU_Q(4) & LRU_Q(9) + ) , STD_ULOGIC_VECTOR'("11111111111111110010")); +MQQ141:LRU_SET_RESET_VEC_PT(41) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + LRU_Q(1) & LRU_Q(2) & + LRU_Q(4) & LRU_Q(9) + ) , STD_ULOGIC_VECTOR'("11111111111111110011")); +MQQ142:LRU_SET_RESET_VEC_PT(42) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + LRU_Q(1) & LRU_Q(2) & + LRU_Q(4) & LRU_Q(8) + ) , STD_ULOGIC_VECTOR'("11111111111111110000")); +MQQ143:LRU_SET_RESET_VEC_PT(43) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + LRU_Q(1) & LRU_Q(2) & + LRU_Q(4) & LRU_Q(8) + ) , STD_ULOGIC_VECTOR'("11111111111111110001")); +MQQ144:LRU_SET_RESET_VEC_PT(44) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & LRU_Q(1) & + LRU_Q(3) & LRU_Q(7) + ) , STD_ULOGIC_VECTOR'("111111111111111110")); +MQQ145:LRU_SET_RESET_VEC_PT(45) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & LRU_Q(1) & + LRU_Q(3) & LRU_Q(7) + ) , STD_ULOGIC_VECTOR'("111111111111111111")); +MQQ146:LRU_SET_RESET_VEC_PT(46) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & LRU_Q(1) & + LRU_Q(3) & LRU_Q(6) + ) , STD_ULOGIC_VECTOR'("111111111111111100")); +MQQ147:LRU_SET_RESET_VEC_PT(47) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & LRU_Q(1) & + LRU_Q(3) & LRU_Q(6) + ) , STD_ULOGIC_VECTOR'("111111111111111101")); +MQQ148:LRU_SET_RESET_VEC_PT(48) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & LRU_Q(1) & + LRU_Q(2) & LRU_Q(5) + ) , STD_ULOGIC_VECTOR'("111111111111111010")); +MQQ149:LRU_SET_RESET_VEC_PT(49) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & LRU_Q(1) & + LRU_Q(2) & LRU_Q(5) + ) , STD_ULOGIC_VECTOR'("111111111111111011")); +MQQ150:LRU_SET_RESET_VEC_PT(50) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & LRU_Q(1) & + LRU_Q(2) & LRU_Q(4) + ) , STD_ULOGIC_VECTOR'("111111111111111000")); +MQQ151:LRU_SET_RESET_VEC_PT(51) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & LRU_Q(1) & + LRU_Q(2) & LRU_Q(4) + ) , STD_ULOGIC_VECTOR'("111111111111111001")); +MQQ152:LRU_SET_RESET_VEC_PT(52) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & LRU_Q(1) & + LRU_Q(3) ) , STD_ULOGIC_VECTOR'("111111111111110")); +MQQ153:LRU_SET_RESET_VEC_PT(53) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & LRU_Q(1) & + LRU_Q(3) ) , STD_ULOGIC_VECTOR'("111111111111111")); +MQQ154:LRU_SET_RESET_VEC_PT(54) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & LRU_Q(1) & + LRU_Q(2) ) , STD_ULOGIC_VECTOR'("111111111111100")); +MQQ155:LRU_SET_RESET_VEC_PT(55) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & LRU_Q(1) & + LRU_Q(2) ) , STD_ULOGIC_VECTOR'("111111111111101")); +MQQ156:LRU_SET_RESET_VEC_PT(56) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & LRU_Q(1) + ) , STD_ULOGIC_VECTOR'("1111111110")); +MQQ157:LRU_SET_RESET_VEC_PT(57) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & LRU_Q(1) + ) , STD_ULOGIC_VECTOR'("1111111111")); +MQQ158:LRU_SET_RESET_VEC_PT(58) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) + ) , STD_ULOGIC_VECTOR'("1111111111111110")); +MQQ159:LRU_SET_RESET_VEC_PT(59) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) ) , STD_ULOGIC_VECTOR'("111111111111110")); +MQQ160:LRU_SET_RESET_VEC_PT(60) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) + ) , STD_ULOGIC_VECTOR'("11111111111110")); +MQQ161:LRU_SET_RESET_VEC_PT(61) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(13) ) , STD_ULOGIC_VECTOR'("1111111111110")); +MQQ162:LRU_SET_RESET_VEC_PT(62) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) ) , STD_ULOGIC_VECTOR'("1111111111110")); +MQQ163:LRU_SET_RESET_VEC_PT(63) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) + ) , STD_ULOGIC_VECTOR'("111111111110")); +MQQ164:LRU_SET_RESET_VEC_PT(64) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(11) ) , STD_ULOGIC_VECTOR'("111111110")); +MQQ165:LRU_SET_RESET_VEC_PT(65) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) ) , STD_ULOGIC_VECTOR'("11111111110")); +MQQ166:LRU_SET_RESET_VEC_PT(66) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) + ) , STD_ULOGIC_VECTOR'("1111111110")); +MQQ167:LRU_SET_RESET_VEC_PT(67) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(9) ) , STD_ULOGIC_VECTOR'("111111110")); +MQQ168:LRU_SET_RESET_VEC_PT(68) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) ) , STD_ULOGIC_VECTOR'("111111110")); +MQQ169:LRU_SET_RESET_VEC_PT(69) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) + ) , STD_ULOGIC_VECTOR'("11111110")); +MQQ170:LRU_SET_RESET_VEC_PT(70) <= + Eq(( ENTRY_VALID_WATERMARKED(7) ) , STD_ULOGIC'('0')); +MQQ171:LRU_SET_RESET_VEC_PT(71) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) ) , STD_ULOGIC_VECTOR'("1111110")); +MQQ172:LRU_SET_RESET_VEC_PT(72) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) + ) , STD_ULOGIC_VECTOR'("111110")); +MQQ173:LRU_SET_RESET_VEC_PT(73) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(5) ) , STD_ULOGIC_VECTOR'("11110")); +MQQ174:LRU_SET_RESET_VEC_PT(74) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) ) , STD_ULOGIC_VECTOR'("11110")); +MQQ175:LRU_SET_RESET_VEC_PT(75) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) + ) , STD_ULOGIC_VECTOR'("1110")); +MQQ176:LRU_SET_RESET_VEC_PT(76) <= + Eq(( ENTRY_VALID_WATERMARKED(3) ) , STD_ULOGIC'('0')); +MQQ177:LRU_SET_RESET_VEC_PT(77) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) ) , STD_ULOGIC_VECTOR'("110")); +MQQ178:LRU_SET_RESET_VEC_PT(78) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) + ) , STD_ULOGIC_VECTOR'("10")); +MQQ179:LRU_SET_RESET_VEC_PT(79) <= + Eq(( ENTRY_VALID_WATERMARKED(1) ) , STD_ULOGIC'('0')); +MQQ180:LRU_SET_RESET_VEC_PT(80) <= + Eq(( ENTRY_VALID_WATERMARKED(0) ) , STD_ULOGIC'('0')); +MQQ181:LRU_RESET_VEC(1) <= + (LRU_SET_RESET_VEC_PT(1) OR LRU_SET_RESET_VEC_PT(2) + OR LRU_SET_RESET_VEC_PT(4) OR LRU_SET_RESET_VEC_PT(6) + OR LRU_SET_RESET_VEC_PT(7) OR LRU_SET_RESET_VEC_PT(9) + OR LRU_SET_RESET_VEC_PT(10) OR LRU_SET_RESET_VEC_PT(13) + OR LRU_SET_RESET_VEC_PT(57) OR LRU_SET_RESET_VEC_PT(70) + OR LRU_SET_RESET_VEC_PT(71) OR LRU_SET_RESET_VEC_PT(73) + OR LRU_SET_RESET_VEC_PT(74) OR LRU_SET_RESET_VEC_PT(76) + OR LRU_SET_RESET_VEC_PT(77) OR LRU_SET_RESET_VEC_PT(79) + OR LRU_SET_RESET_VEC_PT(80)); +MQQ182:LRU_RESET_VEC(2) <= + (LRU_SET_RESET_VEC_PT(14) OR LRU_SET_RESET_VEC_PT(16) + OR LRU_SET_RESET_VEC_PT(17) OR LRU_SET_RESET_VEC_PT(20) + OR LRU_SET_RESET_VEC_PT(55) OR LRU_SET_RESET_VEC_PT(76) + OR LRU_SET_RESET_VEC_PT(77) OR LRU_SET_RESET_VEC_PT(79) + OR LRU_SET_RESET_VEC_PT(80)); +MQQ183:LRU_RESET_VEC(3) <= + (LRU_SET_RESET_VEC_PT(1) OR LRU_SET_RESET_VEC_PT(2) + OR LRU_SET_RESET_VEC_PT(4) OR LRU_SET_RESET_VEC_PT(6) + OR LRU_SET_RESET_VEC_PT(53) OR LRU_SET_RESET_VEC_PT(64) + OR LRU_SET_RESET_VEC_PT(65) OR LRU_SET_RESET_VEC_PT(67) + OR LRU_SET_RESET_VEC_PT(68)); +MQQ184:LRU_RESET_VEC(4) <= + (LRU_SET_RESET_VEC_PT(21) OR LRU_SET_RESET_VEC_PT(24) + OR LRU_SET_RESET_VEC_PT(51) OR LRU_SET_RESET_VEC_PT(79) + OR LRU_SET_RESET_VEC_PT(80)); +MQQ185:LRU_RESET_VEC(5) <= + (LRU_SET_RESET_VEC_PT(14) OR LRU_SET_RESET_VEC_PT(16) + OR LRU_SET_RESET_VEC_PT(49) OR LRU_SET_RESET_VEC_PT(73) + OR LRU_SET_RESET_VEC_PT(74)); +MQQ186:LRU_RESET_VEC(6) <= + (LRU_SET_RESET_VEC_PT(7) OR LRU_SET_RESET_VEC_PT(9) + OR LRU_SET_RESET_VEC_PT(47) OR LRU_SET_RESET_VEC_PT(67) + OR LRU_SET_RESET_VEC_PT(68)); +MQQ187:LRU_RESET_VEC(7) <= + (LRU_SET_RESET_VEC_PT(1) OR LRU_SET_RESET_VEC_PT(2) + OR LRU_SET_RESET_VEC_PT(45) OR LRU_SET_RESET_VEC_PT(61) + OR LRU_SET_RESET_VEC_PT(62)); +MQQ188:LRU_RESET_VEC(8) <= + (LRU_SET_RESET_VEC_PT(25) OR LRU_SET_RESET_VEC_PT(43) + OR LRU_SET_RESET_VEC_PT(80)); +MQQ189:LRU_RESET_VEC(9) <= + (LRU_SET_RESET_VEC_PT(21) OR LRU_SET_RESET_VEC_PT(41) + OR LRU_SET_RESET_VEC_PT(77)); +MQQ190:LRU_RESET_VEC(10) <= + (LRU_SET_RESET_VEC_PT(17) OR LRU_SET_RESET_VEC_PT(39) + OR LRU_SET_RESET_VEC_PT(74)); +MQQ191:LRU_RESET_VEC(11) <= + (LRU_SET_RESET_VEC_PT(14) OR LRU_SET_RESET_VEC_PT(37) + OR LRU_SET_RESET_VEC_PT(71)); +MQQ192:LRU_RESET_VEC(12) <= + (LRU_SET_RESET_VEC_PT(10) OR LRU_SET_RESET_VEC_PT(35) + OR LRU_SET_RESET_VEC_PT(68)); +MQQ193:LRU_RESET_VEC(13) <= + (LRU_SET_RESET_VEC_PT(7) OR LRU_SET_RESET_VEC_PT(33) + OR LRU_SET_RESET_VEC_PT(65)); +MQQ194:LRU_RESET_VEC(14) <= + (LRU_SET_RESET_VEC_PT(4) OR LRU_SET_RESET_VEC_PT(31) + OR LRU_SET_RESET_VEC_PT(62)); +MQQ195:LRU_RESET_VEC(15) <= + (LRU_SET_RESET_VEC_PT(1) OR LRU_SET_RESET_VEC_PT(29) + OR LRU_SET_RESET_VEC_PT(59)); +MQQ196:LRU_SET_VEC(1) <= + (LRU_SET_RESET_VEC_PT(15) OR LRU_SET_RESET_VEC_PT(16) + OR LRU_SET_RESET_VEC_PT(18) OR LRU_SET_RESET_VEC_PT(19) + OR LRU_SET_RESET_VEC_PT(22) OR LRU_SET_RESET_VEC_PT(23) + OR LRU_SET_RESET_VEC_PT(26) OR LRU_SET_RESET_VEC_PT(27) + OR LRU_SET_RESET_VEC_PT(56) OR LRU_SET_RESET_VEC_PT(58) + OR LRU_SET_RESET_VEC_PT(59) OR LRU_SET_RESET_VEC_PT(60) + OR LRU_SET_RESET_VEC_PT(62) OR LRU_SET_RESET_VEC_PT(63) + OR LRU_SET_RESET_VEC_PT(65) OR LRU_SET_RESET_VEC_PT(66) + OR LRU_SET_RESET_VEC_PT(68)); +MQQ197:LRU_SET_VEC(2) <= + (LRU_SET_RESET_VEC_PT(22) OR LRU_SET_RESET_VEC_PT(23) + OR LRU_SET_RESET_VEC_PT(26) OR LRU_SET_RESET_VEC_PT(27) + OR LRU_SET_RESET_VEC_PT(54) OR LRU_SET_RESET_VEC_PT(69) + OR LRU_SET_RESET_VEC_PT(71) OR LRU_SET_RESET_VEC_PT(72) + OR LRU_SET_RESET_VEC_PT(74)); +MQQ198:LRU_SET_VEC(3) <= + (LRU_SET_RESET_VEC_PT(8) OR LRU_SET_RESET_VEC_PT(9) + OR LRU_SET_RESET_VEC_PT(11) OR LRU_SET_RESET_VEC_PT(12) + OR LRU_SET_RESET_VEC_PT(52) OR LRU_SET_RESET_VEC_PT(58) + OR LRU_SET_RESET_VEC_PT(59) OR LRU_SET_RESET_VEC_PT(60) + OR LRU_SET_RESET_VEC_PT(62)); +MQQ199:LRU_SET_VEC(4) <= + (LRU_SET_RESET_VEC_PT(26) OR LRU_SET_RESET_VEC_PT(27) + OR LRU_SET_RESET_VEC_PT(50) OR LRU_SET_RESET_VEC_PT(75) + OR LRU_SET_RESET_VEC_PT(77)); +MQQ200:LRU_SET_VEC(5) <= + (LRU_SET_RESET_VEC_PT(18) OR LRU_SET_RESET_VEC_PT(19) + OR LRU_SET_RESET_VEC_PT(48) OR LRU_SET_RESET_VEC_PT(69) + OR LRU_SET_RESET_VEC_PT(71)); +MQQ201:LRU_SET_VEC(6) <= + (LRU_SET_RESET_VEC_PT(11) OR LRU_SET_RESET_VEC_PT(12) + OR LRU_SET_RESET_VEC_PT(46) OR LRU_SET_RESET_VEC_PT(63) + OR LRU_SET_RESET_VEC_PT(65)); +MQQ202:LRU_SET_VEC(7) <= + (LRU_SET_RESET_VEC_PT(5) OR LRU_SET_RESET_VEC_PT(6) + OR LRU_SET_RESET_VEC_PT(44) OR LRU_SET_RESET_VEC_PT(58) + OR LRU_SET_RESET_VEC_PT(59)); +MQQ203:LRU_SET_VEC(8) <= + (LRU_SET_RESET_VEC_PT(27) OR LRU_SET_RESET_VEC_PT(42) + OR LRU_SET_RESET_VEC_PT(78)); +MQQ204:LRU_SET_VEC(9) <= + (LRU_SET_RESET_VEC_PT(23) OR LRU_SET_RESET_VEC_PT(40) + OR LRU_SET_RESET_VEC_PT(75)); +MQQ205:LRU_SET_VEC(10) <= + (LRU_SET_RESET_VEC_PT(19) OR LRU_SET_RESET_VEC_PT(38) + OR LRU_SET_RESET_VEC_PT(72)); +MQQ206:LRU_SET_VEC(11) <= + (LRU_SET_RESET_VEC_PT(16) OR LRU_SET_RESET_VEC_PT(36) + OR LRU_SET_RESET_VEC_PT(69)); +MQQ207:LRU_SET_VEC(12) <= + (LRU_SET_RESET_VEC_PT(12) OR LRU_SET_RESET_VEC_PT(34) + OR LRU_SET_RESET_VEC_PT(66)); +MQQ208:LRU_SET_VEC(13) <= + (LRU_SET_RESET_VEC_PT(9) OR LRU_SET_RESET_VEC_PT(32) + OR LRU_SET_RESET_VEC_PT(63)); +MQQ209:LRU_SET_VEC(14) <= + (LRU_SET_RESET_VEC_PT(6) OR LRU_SET_RESET_VEC_PT(30) + OR LRU_SET_RESET_VEC_PT(60)); +MQQ210:LRU_SET_VEC(15) <= + (LRU_SET_RESET_VEC_PT(3) OR LRU_SET_RESET_VEC_PT(28) + OR LRU_SET_RESET_VEC_PT(58)); + +MQQ211:LRU_WAY_ENCODE_PT(1) <= + Eq(( LRU_EFF(1) & LRU_EFF(3) & + LRU_EFF(7) & LRU_EFF(15) + ) , STD_ULOGIC_VECTOR'("1111")); +MQQ212:LRU_WAY_ENCODE_PT(2) <= + Eq(( LRU_EFF(1) & LRU_EFF(3) & + LRU_EFF(7) & LRU_EFF(14) + ) , STD_ULOGIC_VECTOR'("1101")); +MQQ213:LRU_WAY_ENCODE_PT(3) <= + Eq(( LRU_EFF(1) & LRU_EFF(3) & + LRU_EFF(6) & LRU_EFF(13) + ) , STD_ULOGIC_VECTOR'("1011")); +MQQ214:LRU_WAY_ENCODE_PT(4) <= + Eq(( LRU_EFF(1) & LRU_EFF(3) & + LRU_EFF(6) & LRU_EFF(12) + ) , STD_ULOGIC_VECTOR'("1001")); +MQQ215:LRU_WAY_ENCODE_PT(5) <= + Eq(( LRU_EFF(1) & LRU_EFF(2) & + LRU_EFF(5) & LRU_EFF(11) + ) , STD_ULOGIC_VECTOR'("0111")); +MQQ216:LRU_WAY_ENCODE_PT(6) <= + Eq(( LRU_EFF(1) & LRU_EFF(2) & + LRU_EFF(5) & LRU_EFF(10) + ) , STD_ULOGIC_VECTOR'("0101")); +MQQ217:LRU_WAY_ENCODE_PT(7) <= + Eq(( LRU_EFF(1) & LRU_EFF(2) & + LRU_EFF(4) & LRU_EFF(9) + ) , STD_ULOGIC_VECTOR'("0011")); +MQQ218:LRU_WAY_ENCODE_PT(8) <= + Eq(( LRU_EFF(1) & LRU_EFF(2) & + LRU_EFF(4) & LRU_EFF(8) + ) , STD_ULOGIC_VECTOR'("0001")); +MQQ219:LRU_WAY_ENCODE_PT(9) <= + Eq(( LRU_EFF(1) & LRU_EFF(3) & + LRU_EFF(7) ) , STD_ULOGIC_VECTOR'("111")); +MQQ220:LRU_WAY_ENCODE_PT(10) <= + Eq(( LRU_EFF(1) & LRU_EFF(3) & + LRU_EFF(6) ) , STD_ULOGIC_VECTOR'("101")); +MQQ221:LRU_WAY_ENCODE_PT(11) <= + Eq(( LRU_EFF(1) & LRU_EFF(2) & + LRU_EFF(5) ) , STD_ULOGIC_VECTOR'("011")); +MQQ222:LRU_WAY_ENCODE_PT(12) <= + Eq(( LRU_EFF(1) & LRU_EFF(2) & + LRU_EFF(4) ) , STD_ULOGIC_VECTOR'("001")); +MQQ223:LRU_WAY_ENCODE_PT(13) <= + Eq(( LRU_EFF(1) & LRU_EFF(3) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ224:LRU_WAY_ENCODE_PT(14) <= + Eq(( LRU_EFF(1) & LRU_EFF(2) + ) , STD_ULOGIC_VECTOR'("01")); +MQQ225:LRU_WAY_ENCODE_PT(15) <= + Eq(( LRU_EFF(1) ) , STD_ULOGIC'('1')); +MQQ226:LRU_WAY_ENCODE(0) <= + (LRU_WAY_ENCODE_PT(15)); +MQQ227:LRU_WAY_ENCODE(1) <= + (LRU_WAY_ENCODE_PT(13) OR LRU_WAY_ENCODE_PT(14) + ); +MQQ228:LRU_WAY_ENCODE(2) <= + (LRU_WAY_ENCODE_PT(9) OR LRU_WAY_ENCODE_PT(10) + OR LRU_WAY_ENCODE_PT(11) OR LRU_WAY_ENCODE_PT(12) + ); +MQQ229:LRU_WAY_ENCODE(3) <= + (LRU_WAY_ENCODE_PT(1) OR LRU_WAY_ENCODE_PT(2) + OR LRU_WAY_ENCODE_PT(3) OR LRU_WAY_ENCODE_PT(4) + OR LRU_WAY_ENCODE_PT(5) OR LRU_WAY_ENCODE_PT(6) + OR LRU_WAY_ENCODE_PT(7) OR LRU_WAY_ENCODE_PT(8) + ); + +Por_Sequencer: PROCESS (por_seq_q, init_alias, bcfg_q(0 to 106)) +BEGIN +por_wr_cam_val <= (others => '0'); +por_wr_array_val <= (others => '0'); +por_wr_cam_data <= (others => '0'); +por_wr_array_data <= (others => '0'); +por_wr_entry <= (others => '0'); +CASE por_seq_q IS + WHEN PorSeq_Idle => + por_wr_cam_val <= (others => '0'); por_wr_array_val <= (others => '0'); + por_hold_req <= (others => init_alias); + + if init_alias ='1' then + por_seq_d <= PorSeq_Stg1; + else + por_seq_d <= PorSeq_Idle; + end if; + WHEN PorSeq_Stg1 => + por_wr_cam_val <= (others => '0'); por_wr_array_val <= (others => '0'); + por_seq_d <= PorSeq_Stg2; por_hold_req <= (others => '1'); + + WHEN PorSeq_Stg2 => + por_wr_cam_val <= (others => '1'); por_wr_array_val <= (others => '1'); + por_wr_entry <= Por_Wr_Entry_Num1; + por_wr_cam_data <= bcfg_q(0 to 51) & Por_Wr_Cam_Data1(52 to 83); + por_wr_array_data <= bcfg_q(52 to 81) & Por_Wr_Array_Data1(30 to 35) & bcfg_q(82 to 85) & + Por_Wr_Array_Data1(40 to 43) & bcfg_q(86) & Por_Wr_Array_Data1(45 to 67); + por_hold_req <= (others => '1'); + por_seq_d <= PorSeq_Stg3; + + WHEN PorSeq_Stg3 => + por_wr_cam_val <= (others => '0'); por_wr_array_val <= (others => '0'); + por_hold_req <= (others => '1'); + por_seq_d <= PorSeq_Stg4; + + WHEN PorSeq_Stg4 => + por_wr_cam_val <= (others => '1'); por_wr_array_val <= (others => '1'); + por_wr_entry <= Por_Wr_Entry_Num2; + por_wr_cam_data <= Por_Wr_Cam_Data2; + por_wr_array_data <= bcfg_q(52 to 61) & bcfg_q(87 to 106) & Por_Wr_Array_Data2(30 to 35) & bcfg_q(82 to 85) & + Por_Wr_Array_Data2(40 to 43) & bcfg_q(86) & Por_Wr_Array_Data2(45 to 67); + por_hold_req <= (others => '1'); + por_seq_d <= PorSeq_Stg5; + + WHEN PorSeq_Stg5 => + por_wr_cam_val <= (others => '0'); por_wr_array_val <= (others => '0'); + por_hold_req <= (others => '1'); + por_seq_d <= PorSeq_Stg6; + + WHEN PorSeq_Stg6 => + por_wr_cam_val <= (others => '0'); por_wr_array_val <= (others => '0'); + por_hold_req <= (others => '0'); + por_seq_d <= PorSeq_Stg7; + + WHEN PorSeq_Stg7 => + por_wr_cam_val <= (others => '0'); por_wr_array_val <= (others => '0'); + por_hold_req <= (others => '0'); + + if init_alias ='0' then + por_seq_d <= PorSeq_Idle; + else + por_seq_d <= PorSeq_Stg7; + end if; + + WHEN OTHERS => + por_seq_d <= PorSeq_Idle; + END CASE; +END PROCESS Por_Sequencer; +cam_pgsize(0 TO 2) <= (CAM_PgSize_1GB and (0 to 2 => Eq(ex6_data_in_q(56 to 59),WS0_PgSize_1GB))) + or (CAM_PgSize_16MB and (0 to 2 => Eq(ex6_data_in_q(56 to 59),WS0_PgSize_16MB))) + or (CAM_PgSize_1MB and (0 to 2 => Eq(ex6_data_in_q(56 to 59),WS0_PgSize_1MB))) + or (CAM_PgSize_64KB and (0 to 2 => Eq(ex6_data_in_q(56 to 59),WS0_PgSize_64KB))) + or (CAM_PgSize_4KB and (0 to 2 => not(Eq(ex6_data_in_q(56 to 59),WS0_PgSize_1GB) or + Eq(ex6_data_in_q(56 to 59),WS0_PgSize_16MB) or + Eq(ex6_data_in_q(56 to 59),WS0_PgSize_1MB) or + Eq(ex6_data_in_q(56 to 59),WS0_PgSize_64KB)))); +ws0_pgsize(0 TO 3) <= (WS0_PgSize_1GB and (0 to 3 => Eq(rd_cam_data(53 to 55),CAM_PgSize_1GB))) + or (WS0_PgSize_16MB and (0 to 3 => Eq(rd_cam_data(53 to 55),CAM_PgSize_16MB))) + or (WS0_PgSize_1MB and (0 to 3 => Eq(rd_cam_data(53 to 55),CAM_PgSize_1MB))) + or (WS0_PgSize_64KB and (0 to 3 => Eq(rd_cam_data(53 to 55),CAM_PgSize_64KB))) + or (WS0_PgSize_4KB and (0 to 3 => Eq(rd_cam_data(53 to 55),CAM_PgSize_4KB))); +rd_val <= or_reduce(ex2_valid_q) and ex2_ttype_q(0) and Eq(ex2_tlbsel_q, TlbSel_IErat); +rw_entry <= ( por_wr_entry and (0 to 3 => or_reduce(por_seq_q)) ) + or ( eptr_q and (0 to 3 => (or_reduce(tlb_rel_val_q(0 to 3)) and tlb_rel_val_q(4) and mmucr1_q(0))) ) + or ( lru_way_encode and (0 to 3 => (or_reduce(tlb_rel_val_q(0 to 3)) and tlb_rel_val_q(4) and not mmucr1_q(0))) ) + or ( eptr_q and (0 to 3 => (or_reduce(ex6_valid_q) and ex6_ttype_q(1) and Eq(ex6_tlbsel_q, TlbSel_IErat) and not tlb_rel_val_q(4) and mmucr1_q(0))) ) + or ( ex6_ra_entry_q and (0 to 3 => (or_reduce(ex6_valid_q) and ex6_ttype_q(1) and Eq(ex6_tlbsel_q, TlbSel_IErat) and not tlb_rel_val_q(4) and not mmucr1_q(0))) ) + or ( ex2_ra_entry_q and (0 to 3 => (or_reduce(ex2_valid_q) and ex2_ttype_q(0) and not(or_reduce(ex6_valid_q) and ex6_ttype_q(1) and Eq(ex6_tlbsel_q, TlbSel_IErat)) and not tlb_rel_val_q(4))) ); +wr_cam_val <= por_wr_cam_val when por_seq_q/=PorSeq_Idle + else (others => '0') when (ex6_valid_q/="0000" and ex6_ttype_q(4 to 5)/="00") + else (others => tlb_rel_data_q(eratpos_wren)) when (tlb_rel_val_q(0 to 3)/="0000" and tlb_rel_val_q(4)='1') + else (others => '1') when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' and ex6_ws_q="00" and ex6_tlbsel_q=TlbSel_IErat) + else (others => '0'); +wr_val_early <= or_reduce(por_seq_q) or + or_reduce(tlb_req_inprogress_q) or + (or_reduce(ex5_valid_q) and ex5_ttype_q(1) and Eq(ex5_ws_q,"00") and Eq(ex5_tlbsel_q,TlbSel_IErat)) or + (or_reduce(ex6_valid_q) and ex6_ttype_q(1) and Eq(ex6_ws_q,"00") and Eq(ex6_tlbsel_q,TlbSel_IErat)); +gen64_wr_cam_data: if rs_data_width = 64 generate +wr_cam_data <= por_wr_cam_data when por_seq_q/=PorSeq_Idle + else (tlb_rel_data_q(0 to 64) & tlb_rel_data_q(122 to 131) & + tlb_rel_cmpmask(0 to 3) & tlb_rel_xbitmask(0 to 3) & tlb_rel_maskpar ) + when (tlb_rel_val_q(0 to 3)/="0000" and tlb_rel_val_q(4)='1') + else ( (ex6_data_in_q(0 to 31) and (0 to 31 => ex6_state_q(3))) & ex6_data_in_q(32 to 51) & ex6_data_in_q(55) & + cam_pgsize(0 to 2) & ex6_data_in_q(54) & ex6_data_in_q(60 to 63) & ex6_data_in_q(52 to 53) & + ex6_extclass_q & ex6_state_q(1 to 2) & ex6_pid_q(pid_width-8 to pid_width-1) & + ex6_data_cmpmask(0 to 3) & ex6_data_xbitmask(0 to 3) & ex6_data_maskpar ) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' and ex6_ws_q="00") + else (others => '0'); +end generate gen64_wr_cam_data; +gen32_wr_cam_data: if rs_data_width = 32 generate +wr_cam_data <= por_wr_cam_data when por_seq_q/=PorSeq_Idle + else (tlb_rel_data_q(0 to 64) & tlb_rel_data_q(122 to 131) & + tlb_rel_cmpmask(0 to 3) & tlb_rel_xbitmask(0 to 3) & tlb_rel_maskpar ) + when (tlb_rel_val_q(0 to 3)/="0000" and tlb_rel_val_q(4)='1') + else ((0 to 31 => '0') & ex6_data_in_q(32 to 51) & ex6_data_in_q(55) & cam_pgsize(0 to 2) & ex6_data_in_q(54) & + ex6_data_in_q(60 to 63) & ex6_data_in_q(52 to 53) & + ex6_extclass_q & ex6_state_q(1 to 2) & ex6_pid_q(pid_width-8 to pid_width-1) & + ex6_data_cmpmask(0 to 3) & ex6_data_xbitmask(0 to 3) & ex6_data_maskpar ) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' and ex6_ws_q="00") + else (others => '0'); +end generate gen32_wr_cam_data; +MQQ230:CAM_MASK_BITS_PT(1) <= + Eq(( EX6_DATA_IN_Q(55) & EX6_DATA_IN_Q(56) & + EX6_DATA_IN_Q(57) & EX6_DATA_IN_Q(58) & + EX6_DATA_IN_Q(59) ) , STD_ULOGIC_VECTOR'("11010")); +MQQ231:CAM_MASK_BITS_PT(2) <= + Eq(( EX6_DATA_IN_Q(56) & EX6_DATA_IN_Q(59) + ) , STD_ULOGIC_VECTOR'("00")); +MQQ232:CAM_MASK_BITS_PT(3) <= + Eq(( EX6_DATA_IN_Q(55) & EX6_DATA_IN_Q(56) & + EX6_DATA_IN_Q(57) & EX6_DATA_IN_Q(58) & + EX6_DATA_IN_Q(59) ) , STD_ULOGIC_VECTOR'("10101")); +MQQ233:CAM_MASK_BITS_PT(4) <= + Eq(( EX6_DATA_IN_Q(55) & EX6_DATA_IN_Q(56) & + EX6_DATA_IN_Q(57) & EX6_DATA_IN_Q(58) & + EX6_DATA_IN_Q(59) ) , STD_ULOGIC_VECTOR'("10011")); +MQQ234:CAM_MASK_BITS_PT(5) <= + Eq(( EX6_DATA_IN_Q(55) & EX6_DATA_IN_Q(56) & + EX6_DATA_IN_Q(57) & EX6_DATA_IN_Q(58) & + EX6_DATA_IN_Q(59) ) , STD_ULOGIC_VECTOR'("10111")); +MQQ235:CAM_MASK_BITS_PT(6) <= + Eq(( EX6_DATA_IN_Q(55) & EX6_DATA_IN_Q(56) & + EX6_DATA_IN_Q(58) & EX6_DATA_IN_Q(59) + ) , STD_ULOGIC_VECTOR'("0011")); +MQQ236:CAM_MASK_BITS_PT(7) <= + Eq(( EX6_DATA_IN_Q(56) & EX6_DATA_IN_Q(59) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ237:CAM_MASK_BITS_PT(8) <= + Eq(( EX6_DATA_IN_Q(57) & EX6_DATA_IN_Q(58) + ) , STD_ULOGIC_VECTOR'("00")); +MQQ238:CAM_MASK_BITS_PT(9) <= + Eq(( EX6_DATA_IN_Q(58) ) , STD_ULOGIC'('0')); +MQQ239:CAM_MASK_BITS_PT(10) <= + Eq(( EX6_DATA_IN_Q(56) & EX6_DATA_IN_Q(57) + ) , STD_ULOGIC_VECTOR'("00")); +MQQ240:CAM_MASK_BITS_PT(11) <= + Eq(( EX6_DATA_IN_Q(56) & EX6_DATA_IN_Q(57) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ241:CAM_MASK_BITS_PT(12) <= + Eq(( TLB_REL_DATA_Q(52) & TLB_REL_DATA_Q(55) + ) , STD_ULOGIC_VECTOR'("10")); +MQQ242:CAM_MASK_BITS_PT(13) <= + Eq(( TLB_REL_DATA_Q(52) & TLB_REL_DATA_Q(53) & + TLB_REL_DATA_Q(54) & TLB_REL_DATA_Q(55) + ) , STD_ULOGIC_VECTOR'("1111")); +MQQ243:CAM_MASK_BITS_PT(14) <= + Eq(( TLB_REL_DATA_Q(52) & TLB_REL_DATA_Q(54) & + TLB_REL_DATA_Q(55) ) , STD_ULOGIC_VECTOR'("011")); +MQQ244:CAM_MASK_BITS_PT(15) <= + Eq(( TLB_REL_DATA_Q(53) & TLB_REL_DATA_Q(54) + ) , STD_ULOGIC_VECTOR'("00")); +MQQ245:CAM_MASK_BITS_PT(16) <= + Eq(( TLB_REL_DATA_Q(52) & TLB_REL_DATA_Q(53) & + TLB_REL_DATA_Q(54) ) , STD_ULOGIC_VECTOR'("110")); +MQQ246:CAM_MASK_BITS_PT(17) <= + Eq(( TLB_REL_DATA_Q(54) ) , STD_ULOGIC'('0')); +MQQ247:CAM_MASK_BITS_PT(18) <= + Eq(( TLB_REL_DATA_Q(52) & TLB_REL_DATA_Q(53) & + TLB_REL_DATA_Q(54) ) , STD_ULOGIC_VECTOR'("101")); +MQQ248:CAM_MASK_BITS_PT(19) <= + Eq(( TLB_REL_DATA_Q(53) ) , STD_ULOGIC'('0')); +MQQ249:TLB_REL_CMPMASK(0) <= + (CAM_MASK_BITS_PT(13) OR CAM_MASK_BITS_PT(14) + OR CAM_MASK_BITS_PT(17) OR CAM_MASK_BITS_PT(18) + ); +MQQ250:TLB_REL_CMPMASK(1) <= + (CAM_MASK_BITS_PT(17) OR CAM_MASK_BITS_PT(19) + ); +MQQ251:TLB_REL_CMPMASK(2) <= + (CAM_MASK_BITS_PT(19)); +MQQ252:TLB_REL_CMPMASK(3) <= + (CAM_MASK_BITS_PT(15)); +MQQ253:TLB_REL_XBITMASK(0) <= + (CAM_MASK_BITS_PT(12)); +MQQ254:TLB_REL_XBITMASK(1) <= + (CAM_MASK_BITS_PT(13)); +MQQ255:TLB_REL_XBITMASK(2) <= + (CAM_MASK_BITS_PT(16)); +MQQ256:TLB_REL_XBITMASK(3) <= + (CAM_MASK_BITS_PT(18)); +MQQ257:TLB_REL_MASKPAR <= + (CAM_MASK_BITS_PT(12) OR CAM_MASK_BITS_PT(14) + OR CAM_MASK_BITS_PT(16)); +MQQ258:EX6_DATA_CMPMASK(0) <= + (CAM_MASK_BITS_PT(2) OR CAM_MASK_BITS_PT(4) + OR CAM_MASK_BITS_PT(5) OR CAM_MASK_BITS_PT(6) + OR CAM_MASK_BITS_PT(7) OR CAM_MASK_BITS_PT(9) + OR CAM_MASK_BITS_PT(11)); +MQQ259:EX6_DATA_CMPMASK(1) <= + (CAM_MASK_BITS_PT(2) OR CAM_MASK_BITS_PT(7) + OR CAM_MASK_BITS_PT(9) OR CAM_MASK_BITS_PT(10) + OR CAM_MASK_BITS_PT(11)); +MQQ260:EX6_DATA_CMPMASK(2) <= + (CAM_MASK_BITS_PT(2) OR CAM_MASK_BITS_PT(7) + OR CAM_MASK_BITS_PT(8) OR CAM_MASK_BITS_PT(10) + OR CAM_MASK_BITS_PT(11)); +MQQ261:EX6_DATA_CMPMASK(3) <= + (CAM_MASK_BITS_PT(2) OR CAM_MASK_BITS_PT(7) + OR CAM_MASK_BITS_PT(8) OR CAM_MASK_BITS_PT(11) + ); +MQQ262:EX6_DATA_XBITMASK(0) <= + (CAM_MASK_BITS_PT(1)); +MQQ263:EX6_DATA_XBITMASK(1) <= + (CAM_MASK_BITS_PT(5)); +MQQ264:EX6_DATA_XBITMASK(2) <= + (CAM_MASK_BITS_PT(3)); +MQQ265:EX6_DATA_XBITMASK(3) <= + (CAM_MASK_BITS_PT(4)); +MQQ266:EX6_DATA_MASKPAR <= + (CAM_MASK_BITS_PT(1) OR CAM_MASK_BITS_PT(3) + OR CAM_MASK_BITS_PT(6)); + +wr_array_val <= por_wr_array_val when por_seq_q/=PorSeq_Idle + else (others => '0') when (ex6_valid_q/="0000" and ex6_ttype_q(4 to 5)/="00") + else (others => tlb_rel_data_q(eratpos_wren)) + when (tlb_rel_val_q(0 to 3)/="0000" and tlb_rel_val_q(4)='1') + else (others => '1') when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_ws_q="00" and ex6_tlbsel_q=TlbSel_IErat) + else (others => '0'); +wr_array_data_nopar <= por_wr_array_data(0 to 50) when por_seq_q/=PorSeq_Idle + else (tlb_rel_data_q(70 to 101) & tlb_rel_data_q(103 to 121)) + when (tlb_rel_val_q(0 to 3)/="0000" and tlb_rel_val_q(4)='1') + else (rpn_holdreg0_q(22 to 51) & rpn_holdreg0_q(16 to 17) & rpn_holdreg0_q(8 to 10) & '0' & + rpn_holdreg0_q(12 to 15) & rpn_holdreg0_q(52 to 56) & rpn_holdreg0_q(58 to 63)) + when (ex6_valid_q(0)='1' and ex6_ttype_q(1)='1' and ex6_ws_q="00") + else (rpn_holdreg1_q(22 to 51) & rpn_holdreg1_q(16 to 17) & rpn_holdreg1_q(8 to 10) & '0' & + rpn_holdreg1_q(12 to 15) & rpn_holdreg1_q(52 to 56) & rpn_holdreg1_q(58 to 63)) + when (ex6_valid_q(1)='1' and ex6_ttype_q(1)='1' and ex6_ws_q="00") + else (rpn_holdreg2_q(22 to 51) & rpn_holdreg2_q(16 to 17) & rpn_holdreg2_q(8 to 10) & '0' & + rpn_holdreg2_q(12 to 15) & rpn_holdreg2_q(52 to 56) & rpn_holdreg2_q(58 to 63)) + when (ex6_valid_q(2)='1' and ex6_ttype_q(1)='1' and ex6_ws_q="00") + else (rpn_holdreg3_q(22 to 51) & rpn_holdreg3_q(16 to 17) & rpn_holdreg3_q(8 to 10) & '0' & + rpn_holdreg3_q(12 to 15) & rpn_holdreg3_q(52 to 56) & rpn_holdreg3_q(58 to 63)) + when (ex6_valid_q(3)='1' and ex6_ttype_q(1)='1' and ex6_ws_q="00") + else (others => '0'); +wr_array_par(51) <= xor_reduce(wr_cam_data(0 to 7)); +wr_array_par(52) <= xor_reduce(wr_cam_data(8 to 15)); +wr_array_par(53) <= xor_reduce(wr_cam_data(16 to 23)); +wr_array_par(54) <= xor_reduce(wr_cam_data(24 to 31)); +wr_array_par(55) <= xor_reduce(wr_cam_data(32 to 39)); +wr_array_par(56) <= xor_reduce(wr_cam_data(40 to 47)); +wr_array_par(57) <= xor_reduce(wr_cam_data(48 to 55)); +wr_array_par(58) <= xor_reduce(wr_cam_data(57 to 62)); +wr_array_par(59) <= xor_reduce(wr_cam_data(63 to 66)); +wr_array_par(60) <= xor_reduce(wr_cam_data(67 to 74)); +wr_array_par(61) <= xor_reduce(wr_array_data_nopar(0 to 5)); +wr_array_par(62) <= xor_reduce(wr_array_data_nopar(6 to 13)); +wr_array_par(63) <= xor_reduce(wr_array_data_nopar(14 to 21)); +wr_array_par(64) <= xor_reduce(wr_array_data_nopar(22 to 29)); +wr_array_par(65) <= xor_reduce(wr_array_data_nopar(30 to 37)); +wr_array_par(66) <= xor_reduce(wr_array_data_nopar(38 to 44)); +wr_array_par(67) <= xor_reduce(wr_array_data_nopar(45 to 50)); +wr_array_data(0 TO 50) <= wr_array_data_nopar; +wr_array_data(51 TO 67) <= (wr_array_par(51 to 60) & wr_array_par(61 to 67)) + when ((tlb_rel_val_q(0 to 3)/="0000" and tlb_rel_val_q(4)='1') or + por_seq_q/=PorSeq_Idle) + else ((wr_array_par(51) xor mmucr1_q(5)) & wr_array_par(52 to 60) & + (wr_array_par(61) xor mmucr1_q(6)) & wr_array_par(62 to 67)) + when (ex6_valid_q(0 to 3)/="0000" and ex6_ttype_q(1)='1' and ex6_ws_q="00") + else (others => '0'); +unused_dc(22) <= lcb_delay_lclkr_dc(1) or lcb_mpw1_dc_b(1); +iu2_cmp_data_calc_par(50) <= xor_reduce(iu2_cam_cmp_data_q(75 to 82)); +iu2_cmp_data_calc_par(51) <= xor_reduce(iu2_cam_cmp_data_q(0 to 7)); +iu2_cmp_data_calc_par(52) <= xor_reduce(iu2_cam_cmp_data_q(8 to 15)); +iu2_cmp_data_calc_par(53) <= xor_reduce(iu2_cam_cmp_data_q(16 to 23)); +iu2_cmp_data_calc_par(54) <= xor_reduce(iu2_cam_cmp_data_q(24 to 31)); +iu2_cmp_data_calc_par(55) <= xor_reduce(iu2_cam_cmp_data_q(32 to 39)); +iu2_cmp_data_calc_par(56) <= xor_reduce(iu2_cam_cmp_data_q(40 to 47)); +iu2_cmp_data_calc_par(57) <= xor_reduce(iu2_cam_cmp_data_q(48 to 55)); +iu2_cmp_data_calc_par(58) <= xor_reduce(iu2_cam_cmp_data_q(57 to 62)); +iu2_cmp_data_calc_par(59) <= xor_reduce(iu2_cam_cmp_data_q(63 to 66)); +iu2_cmp_data_calc_par(60) <= xor_reduce(iu2_cam_cmp_data_q(67 to 74)); +iu2_cmp_data_calc_par(61) <= xor_reduce(iu2_array_cmp_data_q(0 to 5)); +iu2_cmp_data_calc_par(62) <= xor_reduce(iu2_array_cmp_data_q(6 to 13)); +iu2_cmp_data_calc_par(63) <= xor_reduce(iu2_array_cmp_data_q(14 to 21)); +iu2_cmp_data_calc_par(64) <= xor_reduce(iu2_array_cmp_data_q(22 to 29)); +iu2_cmp_data_calc_par(65) <= xor_reduce(iu2_array_cmp_data_q(30 to 37)); +iu2_cmp_data_calc_par(66) <= xor_reduce(iu2_array_cmp_data_q(38 to 44)); +iu2_cmp_data_calc_par(67) <= xor_reduce(iu2_array_cmp_data_q(45 to 50)); +ex4_rd_data_calc_par(50) <= xor_reduce(ex4_rd_cam_data_q(75 to 82)); +ex4_rd_data_calc_par(51) <= xor_reduce(ex4_rd_cam_data_q(0 to 7)); +ex4_rd_data_calc_par(52) <= xor_reduce(ex4_rd_cam_data_q(8 to 15)); +ex4_rd_data_calc_par(53) <= xor_reduce(ex4_rd_cam_data_q(16 to 23)); +ex4_rd_data_calc_par(54) <= xor_reduce(ex4_rd_cam_data_q(24 to 31)); +ex4_rd_data_calc_par(55) <= xor_reduce(ex4_rd_cam_data_q(32 to 39)); +ex4_rd_data_calc_par(56) <= xor_reduce(ex4_rd_cam_data_q(40 to 47)); +ex4_rd_data_calc_par(57) <= xor_reduce(ex4_rd_cam_data_q(48 to 55)); +ex4_rd_data_calc_par(58) <= xor_reduce(ex4_rd_cam_data_q(57 to 62)); +ex4_rd_data_calc_par(59) <= xor_reduce(ex4_rd_cam_data_q(63 to 66)); +ex4_rd_data_calc_par(60) <= xor_reduce(ex4_rd_cam_data_q(67 to 74)); +ex4_rd_data_calc_par(61) <= xor_reduce(ex4_rd_array_data_q(0 to 5)); +ex4_rd_data_calc_par(62) <= xor_reduce(ex4_rd_array_data_q(6 to 13)); +ex4_rd_data_calc_par(63) <= xor_reduce(ex4_rd_array_data_q(14 to 21)); +ex4_rd_data_calc_par(64) <= xor_reduce(ex4_rd_array_data_q(22 to 29)); +ex4_rd_data_calc_par(65) <= xor_reduce(ex4_rd_array_data_q(30 to 37)); +ex4_rd_data_calc_par(66) <= xor_reduce(ex4_rd_array_data_q(38 to 44)); +ex4_rd_data_calc_par(67) <= xor_reduce(ex4_rd_array_data_q(45 to 50)); +parerr_gen0: if check_parity = 0 generate +iu2_cmp_data_parerr_epn <= '0'; +iu2_cmp_data_parerr_rpn <= '0'; +end generate parerr_gen0; +parerr_gen1: if check_parity = 1 generate +iu2_cmp_data_parerr_epn <= or_reduce(iu2_cmp_data_calc_par(50 to 60) xor (iu2_cam_cmp_data_q(83) & iu2_array_cmp_data_q(51 to 60))); +iu2_cmp_data_parerr_rpn <= or_reduce(iu2_cmp_data_calc_par(61 to 67) xor iu2_array_cmp_data_q(61 to 67)); +end generate parerr_gen1; +parerr_gen2: if check_parity = 0 generate +ex4_rd_data_parerr_epn <= '0'; +ex4_rd_data_parerr_rpn <= '0'; +end generate parerr_gen2; +parerr_gen3: if check_parity = 1 generate +ex4_rd_data_parerr_epn <= or_reduce(ex4_rd_data_calc_par(50 to 60) xor (ex4_rd_cam_data_q(83) & ex4_rd_array_data_q(51 to 60))); +ex4_rd_data_parerr_rpn <= or_reduce(ex4_rd_data_calc_par(61 to 67) xor ex4_rd_array_data_q(61 to 67)); +end generate parerr_gen3; +flash_invalidate <= Eq(por_seq_q,PorSeq_Stg1) or mchk_flash_inv_enab; +comp_invalidate <= '1' when (ex6_valid_q/="0000" and ex6_ttype_q(4 to 5)/="00") + else '0' when (tlb_rel_val_q(0 to 3)/="0000" and tlb_rel_val_q(4)='1') + else '1' when snoop_val_q(0 to 1)="11" + else '0'; +comp_request <= ( or_reduce(ex6_valid_q) and or_reduce(ex6_ttype_q(4 to 5)) ) + or ( snoop_val_q(0) and snoop_val_q(1) and not(or_reduce(tlb_rel_val_q(0 to 3)) and tlb_rel_val_q(4)) ) + or ( ex1_ieratsx ) + or ( iu_ierat_iu0_val ); +gen64_comp_addr: if rs_data_width = 64 generate +comp_addr_mux1 <= ( snoop_addr_q and (52-epn_width to 51 => (snoop_val_q(0) and snoop_val_q(1))) ) + or ( xu_iu_ex1_rb and (64-rs_data_width to 51 => (not(snoop_val_q(0) and snoop_val_q(1)) and ex1_ieratsx)) ); +comp_addr_mux1_sel <= (snoop_val_q(0) and snoop_val_q(1)) or (ex1_ieratsx and snoop_val_q(1)); +comp_addr <= ( comp_addr_mux1 and (52-epn_width to 51 => comp_addr_mux1_sel) ) or + ( iu_ierat_iu0_ifar and (52-epn_width to 51 => not comp_addr_mux1_sel) ); +end generate gen64_comp_addr; +iu_xu_ierat_ex2_flush_d <= ( ex1_valid_q and not(xu_ex1_flush) and (0 to 3 => (ex1_ieratsx and not snoop_val_q(1))) ) + or ( ex1_valid_q and not(xu_ex1_flush) and (0 to 3 => ((ex1_ieratre or ex1_ieratwe or ex1_ieratsx) and tlb_rel_data_q(eratpos_relsoon))) ); +iu_xu_ierat_ex2_flush_req <= iu_xu_ierat_ex2_flush_q; +gen32_comp_addr: if rs_data_width = 32 generate +comp_addr_mux1 <= ( ((0 to 31 => '0') & snoop_addr_q) and (52-epn_width to 51 => (snoop_val_q(0) and snoop_val_q(1))) ) + or ( ((0 to 31 => '0') & xu_iu_ex1_rb) and (64-rs_data_width to 51 => (not(snoop_val_q(0) and snoop_val_q(1)) and ex1_ieratsx)) ); +comp_addr_mux1_sel <= (snoop_val_q(0) and snoop_val_q(1)) or ex1_ieratsx; +comp_addr <= ( comp_addr_mux1 and (0 to 51 => comp_addr_mux1_sel) ) + or ( ((0 to 31 => '0') & iu_ierat_iu0_ifar(32 to 51)) and (0 to 51 => not comp_addr_mux1_sel) ); +end generate gen32_comp_addr; +addr_enable(0) <= not(or_reduce(ex6_valid_q) and or_reduce(ex6_ttype_q(4 to 5))) and + ( (snoop_val_q(0) and snoop_val_q(1) and not snoop_attr_q(1) and snoop_attr_q(2) and snoop_attr_q(3)) + or (or_reduce(ex1_valid_q) and ex1_ttype_q(2) and ex1_tlbsel_q(0) and not ex1_tlbsel_q(1) and not(snoop_val_q(0) and snoop_val_q(1))) + or (iu_ierat_iu0_val and not(snoop_val_q(0) and snoop_val_q(1))) ); +addr_enable(1) <= not(or_reduce(ex6_valid_q) and or_reduce(ex6_ttype_q(4 to 5))) and + ( (snoop_val_q(0) and snoop_val_q(1) and snoop_attr_q(0) and not snoop_attr_q(1) and snoop_attr_q(2) and snoop_attr_q(3)) + or (or_reduce(ex1_valid_q) and ex1_ttype_q(2) and ex1_tlbsel_q(0) and not ex1_tlbsel_q(1) and not(snoop_val_q(0) and snoop_val_q(1))) + or (iu_ierat_iu0_val and not(snoop_val_q(0) and snoop_val_q(1))) ); +comp_pgsize <= CAM_PgSize_1GB when snoop_attr_q(14 to 17)=WS0_PgSize_1GB + else CAM_PgSize_16MB when snoop_attr_q(14 to 17)=WS0_PgSize_16MB + else CAM_PgSize_1MB when snoop_attr_q(14 to 17)=WS0_PgSize_1MB + else CAM_PgSize_64KB when snoop_attr_q(14 to 17)=WS0_PgSize_64KB + else CAM_PgSize_4KB; +pgsize_enable <= '0' when (ex6_valid_q/="0000" and ex6_ttype_q(4 to 5)/="00") + else '1' when (snoop_val_q(0 to 1)="11" and snoop_attr_q(0 to 3)="0011") + else '0'; +comp_class <= ( snoop_attr_q(20 to 21) and (0 to 1 => (snoop_val_q(0) and snoop_val_q(1) and mmucr1_q(7))) ) + or ( snoop_attr_q(2 to 3) and (0 to 1 => (snoop_val_q(0) and snoop_val_q(1) and not mmucr1_q(7))) ) + or ( ex1_pid_q(pid_width-14 to pid_width-13) and (0 to 1 => (not(snoop_val_q(0) and snoop_val_q(1)) and mmucr1_q(7) and ex1_ieratsx)) ) + or ( iu1_pid_d(pid_width-14 to pid_width-13) and (0 to 1 => (not(snoop_val_q(0) and snoop_val_q(1)) and mmucr1_q(7) and not(ex1_ieratsx))) ); +class_enable(0) <= '0' when (mmucr1_q(7)='1') + else '0' when (ex6_valid_q/="0000" and ex6_ttype_q(4 to 5)/="00") + else '1' when (snoop_val_q(0 to 1)="11" and snoop_attr_q(1)='1') + else '0'; +class_enable(1) <= '0' when (mmucr1_q(7)='1') + else '0' when (ex6_valid_q/="0000" and ex6_ttype_q(4 to 5)/="00") + else '1' when (snoop_val_q(0 to 1)="11" and snoop_attr_q(1)='1') + else '0'; +class_enable(2) <= '0' when (mmucr1_q(7)='0') + else pid_enable; +comp_extclass(0) <= '0'; +comp_extclass(1) <= snoop_attr_q(19); +extclass_enable(0) <= ( or_reduce(ex6_valid_q) and or_reduce(ex6_ttype_q(4 to 5)) ) + or ( snoop_val_q(0) and snoop_val_q(1) and snoop_attr_q(18) ); +extclass_enable(1) <= ( snoop_val_q(0) and snoop_val_q(1) and not snoop_attr_q(1) and snoop_attr_q(3) ); +comp_state <= ( snoop_attr_q(4 to 5) and (0 to 1 => (snoop_val_q(0) and snoop_val_q(1) and not snoop_attr_q(1) and snoop_attr_q(2))) ) + or ( ex1_state_q(1 to 2) and (0 to 1 => (not(snoop_val_q(0) and snoop_val_q(1)) and ex1_ieratsx)) ) + or ( iu1_state_d(1 to 2) and (0 to 1 => (not(snoop_val_q(0) and snoop_val_q(1)) and not ex1_ieratsx)) ) ; +state_enable(0) <= not(or_reduce(ex6_valid_q) and or_reduce(ex6_ttype_q(4 to 5))) and + ( (snoop_val_q(0) and snoop_val_q(1) and not snoop_attr_q(1) and snoop_attr_q(2) ) + or (or_reduce(ex1_valid_q) and ex1_ttype_q(2) and ex1_tlbsel_q(0) and not ex1_tlbsel_q(1) and not(snoop_val_q(0) and snoop_val_q(1))) + or (iu_ierat_iu0_val and not(snoop_val_q(0) and snoop_val_q(1))) ); +state_enable(1) <= not(or_reduce(ex6_valid_q) and or_reduce(ex6_ttype_q(4 to 5))) and + ( (snoop_val_q(0) and snoop_val_q(1) and not snoop_attr_q(1) and snoop_attr_q(2) and snoop_attr_q(3)) + or (or_reduce(ex1_valid_q) and ex1_ttype_q(2) and ex1_tlbsel_q(0) and not ex1_tlbsel_q(1) and not(snoop_val_q(0) and snoop_val_q(1))) + or (iu_ierat_iu0_val and not(snoop_val_q(0) and snoop_val_q(1))) ); +comp_thdid <= ( snoop_attr_q(22 to 25) and (0 to 3 => (mmucr1_q(8) and snoop_val_q(0) and snoop_val_q(1))) ) + or ( ex1_pid_q(pid_width-12 to pid_width-9) and (0 to 3 => (mmucr1_q(8) and not(snoop_val_q(0) and snoop_val_q(1)) and ex1_ieratsx)) ) + or ( iu1_pid_d(pid_width-12 to pid_width-9) and (0 to 3 => (mmucr1_q(8) and not(snoop_val_q(0) and snoop_val_q(1)) and not ex1_ieratsx)) ) + or ( 0 to 3 => (snoop_val_q(0) and snoop_val_q(1) and not mmucr1_q(8)) ) + or ( ex1_valid_q and (0 to 3 => (ex1_ttype_q(2) and ex1_tlbsel_q(0) and not ex1_tlbsel_q(1) and not(snoop_val_q(0) and snoop_val_q(1)) and not mmucr1_q(8))) ) + or ( iu_ierat_iu0_thdid and (0 to 3 => ((not or_reduce(ex1_valid_q) or not ex1_ttype_q(2) or not Eq(ex1_tlbsel_q,TlbSel_IErat)) + and not(snoop_val_q(0) and snoop_val_q(1)) and not mmucr1_q(8))) ); +thdid_enable(0) <= ( (iu_ierat_iu0_val or (or_reduce(ex1_valid_q) and ex1_ttype_q(2) and ex1_tlbsel_q(0) and not ex1_tlbsel_q(1))) and + (not mmucr1_q(8) and not(snoop_val_q(0) and snoop_val_q(1)) and not(or_reduce(ex6_valid_q) and or_reduce(ex6_ttype_q(4 to 5)))) ); +thdid_enable(1) <= pid_enable and mmucr1_q(8); +comp_pid <= ( snoop_attr_q(6 to 13) and (0 to 7 => (snoop_val_q(0) and snoop_val_q(1))) ) + or ( ex1_pid_q(pid_width-8 to pid_width-1) and + (0 to 7 => (or_reduce(ex1_valid_q) and ex1_ttype_q(2) and ex1_tlbsel_q(0) and not ex1_tlbsel_q(1) and not(snoop_val_q(0) and snoop_val_q(1)))) ) + or ( iu1_pid_d(pid_width-8 to pid_width-1) and + (0 to 7 => (not(or_reduce(ex1_valid_q) and ex1_ttype_q(2) and ex1_tlbsel_q(0) and not ex1_tlbsel_q(1)) and not(snoop_val_q(0) and snoop_val_q(1)))) ); +pid_enable <= not(or_reduce(ex6_valid_q) and or_reduce(ex6_ttype_q(4 to 5))) and + ( (snoop_val_q(0) and snoop_val_q(1) and not snoop_attr_q(1) and snoop_attr_q(3)) + or (or_reduce(ex1_valid_q) and ex1_ttype_q(2) and ex1_tlbsel_q(0) and not ex1_tlbsel_q(1) and not(snoop_val_q(0) and snoop_val_q(1))) + or (iu_ierat_iu0_val and not(snoop_val_q(0) and snoop_val_q(1))) ); +gen64_data_out: if data_out_width = 64 generate +ex4_data_out_d <= ( ((0 to 31 => '0') & rd_cam_data(32 to 51) & rd_cam_data(61 to 62) & rd_cam_data(56) & + rd_cam_data(52) & ws0_pgsize(0 to 3) & rd_cam_data(57 to 60)) + and (64-data_out_width to 63 => (or_reduce(ex3_valid_q) and ex3_ttype_q(0) and not ex3_ws_q(0) and not ex3_ws_q(1) and not ex3_state_q(3))) ) + or ( ((0 to 31 => '0') & rd_array_data(10 to 29) & "00" & rd_array_data(0 to 9)) + and (64-data_out_width to 63 => (or_reduce(ex3_valid_q) and ex3_ttype_q(0) and not ex3_ws_q(0) and ex3_ws_q(1) and not ex3_state_q(3))) ) + or ( ((0 to 31 => '0') & "00000000" & rd_array_data(32 to 34) & '0' & rd_array_data(36 to 39) & rd_array_data(30 to 31) & + "00" & rd_array_data(40 to 44) & '0' & rd_array_data(45 to 50)) + and (64-data_out_width to 63 => (or_reduce(ex3_valid_q) and ex3_ttype_q(0) and ex3_ws_q(0) and not ex3_ws_q(1) and not ex3_state_q(3))) ) + or ( (rd_cam_data(0 to 51) & rd_cam_data(61 to 62) & rd_cam_data(56) & + rd_cam_data(52) & ws0_pgsize(0 to 3) & rd_cam_data(57 to 60)) + and (64-data_out_width to 63 => (or_reduce(ex3_valid_q) and ex3_ttype_q(0) and not ex3_ws_q(0) and not ex3_ws_q(1) and ex3_state_q(3))) ) + or ( ("00000000" & rd_array_data(32 to 34) & '0' & rd_array_data(36 to 39) & rd_array_data(30 to 31) & + "0000" & rd_array_data(0 to 29) & rd_array_data(40 to 44) & '0' & rd_array_data(45 to 50)) + and (64-data_out_width to 63 => (or_reduce(ex3_valid_q) and ex3_ttype_q(0) and not ex3_ws_q(0) and ex3_ws_q(1) and ex3_state_q(3))) ) + or ( ((0 to 47-watermark_width => '0') & (watermark_q and (48-watermark_width to 47 => bcfg_q(107))) & (48 to 63-eptr_width => '0') & eptr_q) + and (64-data_out_width to 63 => (or_reduce(ex3_valid_q) and ex3_ttype_q(0) and ex3_ws_q(0) and ex3_ws_q(1) and mmucr1_q(0))) ) + or ( ((0 to 47-watermark_width => '0') & (watermark_q and (48-watermark_width to 47 => bcfg_q(107))) & (48 to 63-num_entry_log2 => '0') & lru_way_encode) + and (64-data_out_width to 63 => (or_reduce(ex3_valid_q) and ex3_ttype_q(0) and ex3_ws_q(0) and ex3_ws_q(1) and not mmucr1_q(0))) ) + or ( ((0 to 49 => '0') & ex3_eratsx_data_q(0 to 1) & (52 to 59 => '0') & ex3_eratsx_data_q(2 to 2+num_entry_log2-1)) + and (64-data_out_width to 63 => (or_reduce(ex3_valid_q) and ex3_ttype_q(2))) ); +end generate gen64_data_out; +gen32_data_out: if data_out_width = 32 generate +ex4_data_out_d <= ( (rd_cam_data(32 to 51) & rd_cam_data(61 to 62) & rd_cam_data(56) & + rd_cam_data(52) & ws0_pgsize(0 to 3) & rd_cam_data(57 to 60)) + and (64-data_out_width to 63 => (or_reduce(ex3_valid_q) and ex3_ttype_q(0) and not ex3_ws_q(0) and not ex3_ws_q(1))) ) + or ( (rd_array_data(10 to 29) & "00" & rd_array_data(0 to 9)) + and (64-data_out_width to 63 => (or_reduce(ex3_valid_q) and ex3_ttype_q(0) and not ex3_ws_q(0) and ex3_ws_q(1))) ) + or ( ("00000000" & rd_array_data(32 to 34) & '0' & rd_array_data(36 to 39) & rd_array_data(30 to 31) & + "00" & rd_array_data(40 to 44) & rd_array_data(35) & rd_array_data(45 to 50)) + and (64-data_out_width to 63 => (or_reduce(ex3_valid_q) and ex3_ttype_q(0) and ex3_ws_q(0) and not ex3_ws_q(1))) ) + or ( ((32 to 47-watermark_width => '0') & (watermark_q and (48-watermark_width to 47 => bcfg_q(107))) & (48 to 63-eptr_width => '0') & eptr_q) + and (64-data_out_width to 63 => (or_reduce(ex3_valid_q) and ex3_ttype_q(0) and ex3_ws_q(0) and ex3_ws_q(1) and mmucr1_q(0))) ) + or ( ((32 to 47-watermark_width => '0') & (watermark_q and (48-watermark_width to 47 => bcfg_q(107))) & (48 to 63-num_entry_log2 => '0') & lru_way_encode) + and (64-data_out_width to 63 => (or_reduce(ex3_valid_q) and ex3_ttype_q(0) and ex3_ws_q(0) and ex3_ws_q(1) and not mmucr1_q(0))) ) + or ( ((32 to 49 => '0') & ex3_eratsx_data_q(0 to 1) & (52 to 59 => '0') & ex3_eratsx_data_q(2 to 2+num_entry_log2-1)) + and (64-data_out_width to 63 => (or_reduce(ex3_valid_q) and ex3_ttype_q(2))) ); +end generate gen32_data_out; +bypass_mux_enab_np1 <= (ccr2_frat_paranoia_q(9) or iu_ierat_iu1_back_inv or an_ac_grffence_en_dc); +bypass_attr_np1(0 TO 5) <= (others => '0'); +bypass_attr_np1(6 TO 9) <= ccr2_frat_paranoia_q(5 to 8); +bypass_attr_np1(10 TO 14) <= ccr2_frat_paranoia_q(0 to 4); +bypass_attr_np1(15 TO 20) <= "111111"; +ierat_iu_iu2_error(0) <= iu2_miss_sig or iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig; +ierat_iu_iu2_error(1) <= iu2_miss_sig or iu2_multihit_sig; +ierat_iu_iu2_error(2) <= iu2_miss_sig or iu2_parerr_sig; +ierat_iu_iu2_miss <= iu2_miss_sig; +ierat_iu_iu2_multihit <= iu2_multihit_sig; +ierat_iu_iu2_isi <= iu2_isi_sig; +ierat_iu_hold_req <= hold_req_q; +ierat_iu_iu2_flush_req <= iu2_n_flush_req_q; +iu_xu_ex4_data <= ex4_data_out_q; +iu_mm_ierat_req <= iu2_tlbreq_q; +iu_mm_ierat_thdid <= iu2_valid_q; +iu_mm_ierat_state <= iu2_state_q; +iu_mm_ierat_tid <= iu2_pid_q; +iu_mm_ierat_flush <= iu_mm_ierat_flush_q; +iu_mm_ierat_mmucr0 <= ex6_extclass_q & ex6_state_q(1 to 2) & ex6_pid_q; +iu_mm_ierat_mmucr0_we <= ex6_valid_q when (ex6_ttype_q(0)='1' and ex6_ws_q="00" and ex6_tlbsel_q=TlbSel_IErat) + else (others => '0'); +iu_mm_ierat_mmucr1 <= ex6_ieen_q(1 to num_entry_log2); +iu_mm_ierat_mmucr1_we <= ex6_ieen_q(0); +iu_xu_ierat_ex3_par_err <= ex3_parerr_q(0 to thdid_width-1) and (0 to thdid_width-1 => ex3_parerr_enab); +iu_xu_ierat_ex4_par_err <= ex4_parerr_q(0 to thdid_width-1) and (0 to thdid_width-1 => ex4_parerr_enab); +ierat_cam: entity tri.tri_cam_16x143_1r1w1c + generic map (expand_type => expand_type) + port map ( + gnd => gnd, + vdd => vdd, + vcs => vcs, + nclk => nclk, + + + tc_ccflush_dc => tc_ccflush_dc, + tc_scan_dis_dc_b => tc_scan_dis_dc_b, + tc_scan_diag_dc => tc_scan_diag_dc, + tc_lbist_en_dc => tc_lbist_en_dc, + an_ac_atpg_en_dc => an_ac_atpg_en_dc, + + + lcb_d_mode_dc => cam_d_mode, + lcb_clkoff_dc_b => cam_clkoff_b, + lcb_act_dis_dc => cam_act_dis, + lcb_mpw1_dc_b => cam_mpw1_b(0 to 3), + lcb_mpw2_dc_b => cam_mpw2_b, + lcb_delay_lclkr_dc => cam_delay_lclkr(0 to 3), + + pc_sg_2 => pc_iu_sg_2, + pc_func_slp_sl_thold_2 => pc_iu_func_slp_sl_thold_2, + pc_func_slp_nsl_thold_2 => pc_iu_func_slp_nsl_thold_2, + pc_regf_slp_sl_thold_2 => pc_iu_regf_slp_sl_thold_2, + pc_time_sl_thold_2 => pc_iu_time_sl_thold_2, + pc_fce_2 => pc_iu_fce_2, + + func_scan_in => func_scan_in_cam, + func_scan_out => func_scan_out_cam, + regfile_scan_in => regf_scan_in, + regfile_scan_out => regf_scan_out, + time_scan_in => time_scan_in, + time_scan_out => time_scan_out, + + rd_val => rd_val, + rd_val_late => tiup, + rw_entry => rw_entry, + + wr_array_data => wr_array_data, + wr_cam_data => wr_cam_data, + wr_array_val => wr_array_val, + wr_cam_val => wr_cam_val, + wr_val_early => wr_val_early, + + comp_request => comp_request, + comp_addr => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + comp_class => comp_class, + class_enable => class_enable, + comp_extclass => comp_extclass, + extclass_enable => extclass_enable, + comp_state => comp_state, + state_enable => state_enable, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + comp_pid => comp_pid, + pid_enable => pid_enable, + comp_invalidate => comp_invalidate, + flash_invalidate => flash_invalidate, + + array_cmp_data => array_cmp_data, + rd_array_data => rd_array_data, + + cam_cmp_data => cam_cmp_data, + cam_hit => cam_hit, + cam_hit_entry => cam_hit_entry, + entry_match => entry_match, + entry_valid => entry_valid, + rd_cam_data => rd_cam_data, + + +bypass_mux_enab_np1 => bypass_mux_enab_np1, + bypass_attr_np1 => bypass_attr_np1, + attr_np2 => attr_np2, + rpn_np2 => rpn_np2 + + ); +ierat_iu_iu2_rpn <= rpn_np2; +ierat_iu_iu2_wimge <= attr_np2(10 to 14); +ierat_iu_iu2_u <= attr_np2(6 to 9); +iu1_debug_d(0) <= comp_request; +iu1_debug_d(1) <= comp_invalidate; +iu1_debug_d(2) <= ( or_reduce(ex6_valid_q) and or_reduce(ex6_ttype_q(4 to 5)) ); +iu1_debug_d(3) <= '0'; +iu1_debug_d(4) <= ( snoop_val_q(0) and snoop_val_q(1) and not(or_reduce(tlb_rel_val_q(0 to 3)) and tlb_rel_val_q(4)) ); +iu1_debug_d(5) <= ( ex1_ieratsx ); +iu1_debug_d(6) <= ( iu_ierat_iu0_val ); +iu1_debug_d(7) <= ( or_reduce(tlb_rel_val_q(0 to 3)) and tlb_rel_val_q(4) ); +iu1_debug_d(8) <= ( or_reduce(tlb_rel_val_q(0 to 3)) ); +iu1_debug_d(9) <= ( snoop_val_q(0) and snoop_val_q(1) ); +iu1_debug_d(10) <= '0'; +iu2_debug_d(0 TO 10) <= iu1_debug_q(0 to 10); +iu2_debug_d(11 TO 15) <= '0' & iu1_first_hit_entry; +iu2_debug_d(16) <= iu1_multihit; +lru_debug_d(0) <= ( tlb_rel_data_q(eratpos_wren) and or_reduce(tlb_rel_val_q(0 to 3)) and tlb_rel_val_q(4) ); +lru_debug_d(1) <= ( snoop_val_q(0) and snoop_val_q(1) ); +lru_debug_d(2) <= ( or_reduce(ex6_valid_q) and (ex6_ttype_q(4) or ex6_ttype_q(5)) ); +lru_debug_d(3) <= ( or_reduce(ex6_valid_q) and ex6_ttype_q(1) and not ex6_ws_q(0) and not ex6_ws_q(1) + and ex6_tlbsel_q(0) and not ex6_tlbsel_q(1) and lru_way_is_written ); +lru_debug_d(4) <= ( or_reduce(iu1_valid_q and not(iu_ierat_iu1_flush) and not(xu_iu_flush) and not(iu2_n_flush_req_q)) + and not iu1_flush_enab_q and cam_hit and lru_way_is_hit_entry ); +lru_debug_d(5 TO 19) <= lru_eff; +lru_debug_d(20 TO 23) <= lru_way_encode; +ierat_iu_debug_group0(0 TO 83) <= iu2_cam_cmp_data_q(0 to 83); +ierat_iu_debug_group0(84) <= ex3_eratsx_data_q(1); +ierat_iu_debug_group0(85) <= iu2_debug_q(0); +ierat_iu_debug_group0(86) <= iu2_debug_q(1); +ierat_iu_debug_group0(87) <= iu2_debug_q(9); +ierat_iu_debug_group1(0 TO 67) <= iu2_array_cmp_data_q(0 to 67); +ierat_iu_debug_group1(68) <= ex3_eratsx_data_q(1); +ierat_iu_debug_group1(69) <= iu2_debug_q(16); +ierat_iu_debug_group1(70 TO 74) <= iu2_debug_q(11 to 15); +ierat_iu_debug_group1(75) <= iu2_debug_q(0); +ierat_iu_debug_group1(76) <= iu2_debug_q(1); +ierat_iu_debug_group1(77) <= iu2_debug_q(2); +ierat_iu_debug_group1(78) <= iu2_debug_q(3); +ierat_iu_debug_group1(79) <= iu2_debug_q(4); +ierat_iu_debug_group1(80) <= iu2_debug_q(5); +ierat_iu_debug_group1(81) <= iu2_debug_q(6); +ierat_iu_debug_group1(82) <= iu2_debug_q(7); +ierat_iu_debug_group1(83) <= iu2_debug_q(8); +ierat_iu_debug_group1(84) <= iu2_debug_q(9); +ierat_iu_debug_group1(85) <= iu2_debug_q(10); +ierat_iu_debug_group1(86) <= '0'; +ierat_iu_debug_group1(87) <= lru_update_event_q(7) or lru_update_event_q(8); +ierat_iu_debug_group2(0 TO 15) <= entry_valid_q(0 to 15); +ierat_iu_debug_group2(16 TO 31) <= entry_match_q(0 to 15); +ierat_iu_debug_group2(32 TO 47) <= '0' & lru_q(1 to 15); +ierat_iu_debug_group2(48 TO 63) <= '0' & lru_debug_q(5 to 19); +ierat_iu_debug_group2(64 TO 73) <= lru_update_event_q(0 to 8) & iu2_debug_q(16); +ierat_iu_debug_group2(74 TO 78) <= '0' & lru_debug_q(20 to 23); +ierat_iu_debug_group2(79 TO 83) <= '0' & watermark_q(0 to 3); +ierat_iu_debug_group2(84) <= ex3_eratsx_data_q(1); +ierat_iu_debug_group2(85) <= iu2_debug_q(0); +ierat_iu_debug_group2(86) <= iu2_debug_q(1); +ierat_iu_debug_group2(87) <= iu2_debug_q(9); +ierat_iu_debug_group3(0) <= ex3_eratsx_data_q(1); +ierat_iu_debug_group3(1) <= iu2_debug_q(0); +ierat_iu_debug_group3(2) <= iu2_debug_q(1); +ierat_iu_debug_group3(3) <= iu2_debug_q(9); +ierat_iu_debug_group3(4 TO 8) <= iu2_debug_q(11 to 15); +ierat_iu_debug_group3(9) <= lru_update_event_q(7) or lru_update_event_q(8); +ierat_iu_debug_group3(10 TO 14) <= lru_debug_q(0 to 4); +ierat_iu_debug_group3(15 TO 19) <= '0' & watermark_q(0 to 3); +ierat_iu_debug_group3(20 TO 35) <= entry_valid_q(0 to 15); +ierat_iu_debug_group3(36 TO 51) <= entry_match_q(0 to 15); +ierat_iu_debug_group3(52 TO 67) <= '0' & lru_q(1 to 15); +ierat_iu_debug_group3(68 TO 83) <= '0' & lru_debug_q(5 to 19); +ierat_iu_debug_group3(84 TO 87) <= lru_debug_q(20 to 23); +unused_dc(0) <= mmucr1_q(2); +unused_dc(1) <= iu2_multihit_enab and or_reduce(iu2_first_hit_entry); +unused_dc(2) <= or_reduce(ex6_ttype_q(2 to 3)) and ex6_state_q(0); +unused_dc(3) <= or_reduce(tlb_rel_data_q(eratpos_rpnrsvd to eratpos_rpnrsvd+3)); +unused_dc(4) <= iu2_cam_cmp_data_q(56) or ex4_rd_cam_data_q(56); +unused_dc(5) <= or_reduce(attr_np2(0 to 5)); +unused_dc(6) <= or_reduce(attr_np2(15 to 20)); +unused_dc(7) <= or_reduce(cam_hit_entry); +unused_dc(8) <= or_reduce(bcfg_q_b(0 to 15)); +unused_dc(9) <= or_reduce(bcfg_q_b(16 to 31)); +unused_dc(10) <= or_reduce(bcfg_q_b(32 to 47)); +unused_dc(11) <= or_reduce(bcfg_q_b(48 to 51)); +unused_dc(12) <= or_reduce(bcfg_q_b(52 to 61)); +unused_dc(13) <= or_reduce(bcfg_q_b(62 to 77)); +unused_dc(14) <= or_reduce(bcfg_q_b(78 to 81)); +unused_dc(15) <= or_reduce(bcfg_q_b(82 to 86)); +unused_dc(16) <= or_reduce(ex1_ra_entry_q); +unused_dc(17) <= or_reduce(ex1_rs_is_q); +unused_dc(18) <= or_reduce(ex6_rs_is_q); +unused_dc(19) <= pc_func_sl_thold_0_b or pc_func_sl_force; +unused_dc(20) <= cam_mpw1_b(4) or cam_delay_lclkr(4); +unused_dc(21) <= or_reduce(ex1_ttype_q(ttype_width-2 to ttype_width)); +unused_dc(23) <= ex7_ttype_q(0); +unused_dc(24) <= or_reduce(ex7_ttype_q(2 TO 5)); +unused_dc(25) <= or_reduce(por_wr_array_data(51 to 67)); +unused_dc(26) <= or_reduce(bcfg_q_b(87 to 102)); +unused_dc(27) <= or_reduce(bcfg_q_b(103 to 106)); +unused_dc(28) <= or_reduce(bcfg_q(108 to 122)); +unused_dc(29) <= or_reduce(bcfg_q_b(107 to 122)); +ex1_valid_latch: tri_rlmreg_p + generic map (width => ex1_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex1_valid_offset to ex1_valid_offset+ex1_valid_q'length-1), + scout => sov_0(ex1_valid_offset to ex1_valid_offset+ex1_valid_q'length-1), + din => ex1_valid_d(0 to thdid_width-1), + dout => ex1_valid_q(0 to thdid_width-1) ); +ex1_ttype_latch: tri_rlmreg_p + generic map (width => ex1_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex1_ttype_offset to ex1_ttype_offset+ex1_ttype_q'length-1), + scout => sov_0(ex1_ttype_offset to ex1_ttype_offset+ex1_ttype_q'length-1), + din => ex1_ttype_d, + dout => ex1_ttype_q ); +ex1_ws_latch: tri_rlmreg_p + generic map (width => ex1_ws_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex1_ws_offset to ex1_ws_offset+ex1_ws_q'length-1), + scout => sov_0(ex1_ws_offset to ex1_ws_offset+ex1_ws_q'length-1), + din => ex1_ws_d(0 to ws_width-1), + dout => ex1_ws_q(0 to ws_width-1) ); +ex1_rs_is_latch: tri_rlmreg_p + generic map (width => ex1_rs_is_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex1_rs_is_offset to ex1_rs_is_offset+ex1_rs_is_q'length-1), + scout => sov_0(ex1_rs_is_offset to ex1_rs_is_offset+ex1_rs_is_q'length-1), + din => ex1_rs_is_d(0 to rs_is_width-1), + dout => ex1_rs_is_q(0 to rs_is_width-1) ); +ex1_ra_entry_latch: tri_rlmreg_p + generic map (width => ex1_ra_entry_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex1_ra_entry_offset to ex1_ra_entry_offset+ex1_ra_entry_q'length-1), + scout => sov_0(ex1_ra_entry_offset to ex1_ra_entry_offset+ex1_ra_entry_q'length-1), + din => ex1_ra_entry_d(0 to ra_entry_width-1), + dout => ex1_ra_entry_q(0 to ra_entry_width-1) ); +ex1_state_latch: tri_rlmreg_p + generic map (width => ex1_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex1_state_offset to ex1_state_offset+ex1_state_q'length-1), + scout => sov_0(ex1_state_offset to ex1_state_offset+ex1_state_q'length-1), + din => ex1_state_d(0 to state_width-1), + dout => ex1_state_q(0 to state_width-1) ); +ex1_pid_latch: tri_rlmreg_p + generic map (width => ex1_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex1_pid_offset to ex1_pid_offset+ex1_pid_q'length-1), + scout => sov_0(ex1_pid_offset to ex1_pid_offset+ex1_pid_q'length-1), + din => ex1_pid_d, + dout => ex1_pid_q ); +ex1_extclass_latch: tri_rlmreg_p + generic map (width => ex1_extclass_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex1_extclass_offset to ex1_extclass_offset+ex1_extclass_q'length-1), + scout => sov_0(ex1_extclass_offset to ex1_extclass_offset+ex1_extclass_q'length-1), + din => ex1_extclass_d(0 to extclass_width-1), + dout => ex1_extclass_q(0 to extclass_width-1) ); +ex1_tlbsel_latch: tri_rlmreg_p + generic map (width => ex1_tlbsel_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex1_tlbsel_offset to ex1_tlbsel_offset+ex1_tlbsel_q'length-1), + scout => sov_0(ex1_tlbsel_offset to ex1_tlbsel_offset+ex1_tlbsel_q'length-1), + din => ex1_tlbsel_d(0 to tlbsel_width-1), + dout => ex1_tlbsel_q(0 to tlbsel_width-1) ); +ex2_valid_latch: tri_rlmreg_p + generic map (width => ex2_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex2_valid_offset to ex2_valid_offset+ex2_valid_q'length-1), + scout => sov_0(ex2_valid_offset to ex2_valid_offset+ex2_valid_q'length-1), + din => ex2_valid_d(0 to thdid_width-1), + dout => ex2_valid_q(0 to thdid_width-1) ); +ex2_ttype_latch: tri_rlmreg_p + generic map (width => ex2_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex2_ttype_offset to ex2_ttype_offset+ex2_ttype_q'length-1), + scout => sov_0(ex2_ttype_offset to ex2_ttype_offset+ex2_ttype_q'length-1), + din => ex2_ttype_d(0 to ttype_width-1), + dout => ex2_ttype_q(0 to ttype_width-1) ); +ex2_ws_latch: tri_rlmreg_p + generic map (width => ex2_ws_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex2_ws_offset to ex2_ws_offset+ex2_ws_q'length-1), + scout => sov_0(ex2_ws_offset to ex2_ws_offset+ex2_ws_q'length-1), + din => ex2_ws_d(0 to ws_width-1), + dout => ex2_ws_q(0 to ws_width-1) ); +ex2_rs_is_latch: tri_rlmreg_p + generic map (width => ex2_rs_is_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex2_rs_is_offset to ex2_rs_is_offset+ex2_rs_is_q'length-1), + scout => sov_0(ex2_rs_is_offset to ex2_rs_is_offset+ex2_rs_is_q'length-1), + din => ex2_rs_is_d(0 to rs_is_width-1), + dout => ex2_rs_is_q(0 to rs_is_width-1) ); +ex2_ra_entry_latch: tri_rlmreg_p + generic map (width => ex2_ra_entry_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex2_ra_entry_offset to ex2_ra_entry_offset+ex2_ra_entry_q'length-1), + scout => sov_0(ex2_ra_entry_offset to ex2_ra_entry_offset+ex2_ra_entry_q'length-1), + din => ex2_ra_entry_d(0 to ra_entry_width-1), + dout => ex2_ra_entry_q(0 to ra_entry_width-1) ); +ex2_state_latch: tri_rlmreg_p + generic map (width => ex2_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex2_state_offset to ex2_state_offset+ex2_state_q'length-1), + scout => sov_0(ex2_state_offset to ex2_state_offset+ex2_state_q'length-1), + din => ex2_state_d(0 to state_width-1), + dout => ex2_state_q(0 to state_width-1) ); +ex2_pid_latch: tri_rlmreg_p + generic map (width => ex2_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex2_pid_offset to ex2_pid_offset+ex2_pid_q'length-1), + scout => sov_0(ex2_pid_offset to ex2_pid_offset+ex2_pid_q'length-1), + din => ex2_pid_d, + dout => ex2_pid_q ); +ex2_extclass_latch: tri_rlmreg_p + generic map (width => ex2_extclass_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex2_extclass_offset to ex2_extclass_offset+ex2_extclass_q'length-1), + scout => sov_0(ex2_extclass_offset to ex2_extclass_offset+ex2_extclass_q'length-1), + din => ex2_extclass_d(0 to extclass_width-1), + dout => ex2_extclass_q(0 to extclass_width-1) ); +ex2_tlbsel_latch: tri_rlmreg_p + generic map (width => ex2_tlbsel_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex2_tlbsel_offset to ex2_tlbsel_offset+ex2_tlbsel_q'length-1), + scout => sov_0(ex2_tlbsel_offset to ex2_tlbsel_offset+ex2_tlbsel_q'length-1), + din => ex2_tlbsel_d(0 to tlbsel_width-1), + dout => ex2_tlbsel_q(0 to tlbsel_width-1) ); +ex3_valid_latch: tri_rlmreg_p + generic map (width => ex3_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_valid_offset to ex3_valid_offset+ex3_valid_q'length-1), + scout => sov_0(ex3_valid_offset to ex3_valid_offset+ex3_valid_q'length-1), + din => ex3_valid_d(0 to thdid_width-1), + dout => ex3_valid_q(0 to thdid_width-1) ); +ex3_ttype_latch: tri_rlmreg_p + generic map (width => ex3_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_ttype_offset to ex3_ttype_offset+ex3_ttype_q'length-1), + scout => sov_0(ex3_ttype_offset to ex3_ttype_offset+ex3_ttype_q'length-1), + din => ex3_ttype_d(0 to ttype_width-1), + dout => ex3_ttype_q(0 to ttype_width-1) ); +ex3_ws_latch: tri_rlmreg_p + generic map (width => ex3_ws_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_ws_offset to ex3_ws_offset+ex3_ws_q'length-1), + scout => sov_0(ex3_ws_offset to ex3_ws_offset+ex3_ws_q'length-1), + din => ex3_ws_d(0 to ws_width-1), + dout => ex3_ws_q(0 to ws_width-1) ); +ex3_rs_is_latch: tri_rlmreg_p + generic map (width => ex3_rs_is_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_rs_is_offset to ex3_rs_is_offset+ex3_rs_is_q'length-1), + scout => sov_0(ex3_rs_is_offset to ex3_rs_is_offset+ex3_rs_is_q'length-1), + din => ex3_rs_is_d(0 to rs_is_width-1), + dout => ex3_rs_is_q(0 to rs_is_width-1) ); +ex3_ra_entry_latch: tri_rlmreg_p + generic map (width => ex3_ra_entry_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_ra_entry_offset to ex3_ra_entry_offset+ex3_ra_entry_q'length-1), + scout => sov_0(ex3_ra_entry_offset to ex3_ra_entry_offset+ex3_ra_entry_q'length-1), + din => ex3_ra_entry_d(0 to ra_entry_width-1), + dout => ex3_ra_entry_q(0 to ra_entry_width-1) ); +ex3_state_latch: tri_rlmreg_p + generic map (width => ex3_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_state_offset to ex3_state_offset+ex3_state_q'length-1), + scout => sov_0(ex3_state_offset to ex3_state_offset+ex3_state_q'length-1), + din => ex3_state_d(0 to state_width-1), + dout => ex3_state_q(0 to state_width-1) ); +ex3_pid_latch: tri_rlmreg_p + generic map (width => ex3_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_pid_offset to ex3_pid_offset+ex3_pid_q'length-1), + scout => sov_0(ex3_pid_offset to ex3_pid_offset+ex3_pid_q'length-1), + din => ex3_pid_d, + dout => ex3_pid_q ); +ex3_extclass_latch: tri_rlmreg_p + generic map (width => ex3_extclass_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_extclass_offset to ex3_extclass_offset+ex3_extclass_q'length-1), + scout => sov_0(ex3_extclass_offset to ex3_extclass_offset+ex3_extclass_q'length-1), + din => ex3_extclass_d(0 to extclass_width-1), + dout => ex3_extclass_q(0 to extclass_width-1) ); +ex3_tlbsel_latch: tri_rlmreg_p + generic map (width => ex3_tlbsel_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_tlbsel_offset to ex3_tlbsel_offset+ex3_tlbsel_q'length-1), + scout => sov_0(ex3_tlbsel_offset to ex3_tlbsel_offset+ex3_tlbsel_q'length-1), + din => ex3_tlbsel_d(0 to tlbsel_width-1), + dout => ex3_tlbsel_q(0 to tlbsel_width-1) ); +ex3_eratsx_data_latch: tri_rlmreg_p + generic map (width => ex3_eratsx_data_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => eratsx_data_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_eratsx_data_offset to ex3_eratsx_data_offset+ex3_eratsx_data_q'length-1), + scout => sov_0(ex3_eratsx_data_offset to ex3_eratsx_data_offset+ex3_eratsx_data_q'length-1), + din => ex3_eratsx_data_d(0 to 2+num_entry_log2-1), + dout => ex3_eratsx_data_q(0 to 2+num_entry_log2-1) ); +ex4_valid_latch: tri_rlmreg_p + generic map (width => ex4_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex4_valid_offset to ex4_valid_offset+ex4_valid_q'length-1), + scout => sov_0(ex4_valid_offset to ex4_valid_offset+ex4_valid_q'length-1), + din => ex4_valid_d(0 to thdid_width-1), + dout => ex4_valid_q(0 to thdid_width-1) ); +ex4_ttype_latch: tri_rlmreg_p + generic map (width => ex4_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex4_ttype_offset to ex4_ttype_offset+ex4_ttype_q'length-1), + scout => sov_0(ex4_ttype_offset to ex4_ttype_offset+ex4_ttype_q'length-1), + din => ex4_ttype_d(0 to ttype_width-1), + dout => ex4_ttype_q(0 to ttype_width-1) ); +ex4_ws_latch: tri_rlmreg_p + generic map (width => ex4_ws_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex4_ws_offset to ex4_ws_offset+ex4_ws_q'length-1), + scout => sov_0(ex4_ws_offset to ex4_ws_offset+ex4_ws_q'length-1), + din => ex4_ws_d(0 to ws_width-1), + dout => ex4_ws_q(0 to ws_width-1) ); +ex4_rs_is_latch: tri_rlmreg_p + generic map (width => ex4_rs_is_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex4_rs_is_offset to ex4_rs_is_offset+ex4_rs_is_q'length-1), + scout => sov_0(ex4_rs_is_offset to ex4_rs_is_offset+ex4_rs_is_q'length-1), + din => ex4_rs_is_d(0 to rs_is_width-1), + dout => ex4_rs_is_q(0 to rs_is_width-1) ); +ex4_ra_entry_latch: tri_rlmreg_p + generic map (width => ex4_ra_entry_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex4_ra_entry_offset to ex4_ra_entry_offset+ex4_ra_entry_q'length-1), + scout => sov_0(ex4_ra_entry_offset to ex4_ra_entry_offset+ex4_ra_entry_q'length-1), + din => ex4_ra_entry_d(0 to ra_entry_width-1), + dout => ex4_ra_entry_q(0 to ra_entry_width-1) ); +ex4_state_latch: tri_rlmreg_p + generic map (width => ex4_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex4_state_offset to ex4_state_offset+ex4_state_q'length-1), + scout => sov_0(ex4_state_offset to ex4_state_offset+ex4_state_q'length-1), + din => ex4_state_d(0 to state_width-1), + dout => ex4_state_q(0 to state_width-1) ); +ex4_pid_latch: tri_rlmreg_p + generic map (width => ex4_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex4_pid_offset to ex4_pid_offset+ex4_pid_q'length-1), + scout => sov_0(ex4_pid_offset to ex4_pid_offset+ex4_pid_q'length-1), + din => ex4_pid_d, + dout => ex4_pid_q ); +ex4_extclass_latch: tri_rlmreg_p + generic map (width => ex4_extclass_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex4_extclass_offset to ex4_extclass_offset+ex4_extclass_q'length-1), + scout => sov_0(ex4_extclass_offset to ex4_extclass_offset+ex4_extclass_q'length-1), + din => ex4_extclass_d(0 to extclass_width-1), + dout => ex4_extclass_q(0 to extclass_width-1) ); +ex4_tlbsel_latch: tri_rlmreg_p + generic map (width => ex4_tlbsel_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex4_tlbsel_offset to ex4_tlbsel_offset+ex4_tlbsel_q'length-1), + scout => sov_0(ex4_tlbsel_offset to ex4_tlbsel_offset+ex4_tlbsel_q'length-1), + din => ex4_tlbsel_d(0 to tlbsel_width-1), + dout => ex4_tlbsel_q(0 to tlbsel_width-1) ); +ex4_data_out_latch: tri_rlmreg_p + generic map (width => ex4_data_out_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_data_out_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex4_data_out_offset to ex4_data_out_offset+ex4_data_out_q'length-1), + scout => sov_0(ex4_data_out_offset to ex4_data_out_offset+ex4_data_out_q'length-1), + din => ex4_data_out_d(64-data_out_width to 63), + dout => ex4_data_out_q(64-data_out_width to 63) ); +ex5_valid_latch: tri_rlmreg_p + generic map (width => ex5_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex5_valid_offset to ex5_valid_offset+ex5_valid_q'length-1), + scout => sov_0(ex5_valid_offset to ex5_valid_offset+ex5_valid_q'length-1), + din => ex5_valid_d(0 to thdid_width-1), + dout => ex5_valid_q(0 to thdid_width-1) ); +ex5_ttype_latch: tri_rlmreg_p + generic map (width => ex5_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex5_ttype_offset to ex5_ttype_offset+ex5_ttype_q'length-1), + scout => sov_0(ex5_ttype_offset to ex5_ttype_offset+ex5_ttype_q'length-1), + din => ex5_ttype_d(0 to ttype_width-1), + dout => ex5_ttype_q(0 to ttype_width-1) ); +ex5_ws_latch: tri_rlmreg_p + generic map (width => ex5_ws_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex5_ws_offset to ex5_ws_offset+ex5_ws_q'length-1), + scout => sov_0(ex5_ws_offset to ex5_ws_offset+ex5_ws_q'length-1), + din => ex5_ws_d(0 to ws_width-1), + dout => ex5_ws_q(0 to ws_width-1) ); +ex5_rs_is_latch: tri_rlmreg_p + generic map (width => ex5_rs_is_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex5_rs_is_offset to ex5_rs_is_offset+ex5_rs_is_q'length-1), + scout => sov_0(ex5_rs_is_offset to ex5_rs_is_offset+ex5_rs_is_q'length-1), + din => ex5_rs_is_d(0 to rs_is_width-1), + dout => ex5_rs_is_q(0 to rs_is_width-1) ); +ex5_ra_entry_latch: tri_rlmreg_p + generic map (width => ex5_ra_entry_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex5_ra_entry_offset to ex5_ra_entry_offset+ex5_ra_entry_q'length-1), + scout => sov_0(ex5_ra_entry_offset to ex5_ra_entry_offset+ex5_ra_entry_q'length-1), + din => ex5_ra_entry_d(0 to ra_entry_width-1), + dout => ex5_ra_entry_q(0 to ra_entry_width-1) ); +ex5_state_latch: tri_rlmreg_p + generic map (width => ex5_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex5_state_offset to ex5_state_offset+ex5_state_q'length-1), + scout => sov_0(ex5_state_offset to ex5_state_offset+ex5_state_q'length-1), + din => ex5_state_d(0 to state_width-1), + dout => ex5_state_q(0 to state_width-1) ); +ex5_pid_latch: tri_rlmreg_p + generic map (width => ex5_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex5_pid_offset to ex5_pid_offset+ex5_pid_q'length-1), + scout => sov_0(ex5_pid_offset to ex5_pid_offset+ex5_pid_q'length-1), + din => ex5_pid_d, + dout => ex5_pid_q ); +ex5_extclass_latch: tri_rlmreg_p + generic map (width => ex5_extclass_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex5_extclass_offset to ex5_extclass_offset+ex5_extclass_q'length-1), + scout => sov_0(ex5_extclass_offset to ex5_extclass_offset+ex5_extclass_q'length-1), + din => ex5_extclass_d(0 to extclass_width-1), + dout => ex5_extclass_q(0 to extclass_width-1) ); +ex5_tlbsel_latch: tri_rlmreg_p + generic map (width => ex5_tlbsel_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex5_tlbsel_offset to ex5_tlbsel_offset+ex5_tlbsel_q'length-1), + scout => sov_0(ex5_tlbsel_offset to ex5_tlbsel_offset+ex5_tlbsel_q'length-1), + din => ex5_tlbsel_d(0 to tlbsel_width-1), + dout => ex5_tlbsel_q(0 to tlbsel_width-1) ); +ex5_data_in_latch: tri_rlmreg_p + generic map (width => ex5_data_in_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex5_data_in_offset to ex5_data_in_offset+ex5_data_in_q'length-1), + scout => sov_0(ex5_data_in_offset to ex5_data_in_offset+ex5_data_in_q'length-1), + din => ex5_data_in_d(64-rs_data_width to 63), + dout => ex5_data_in_q(64-rs_data_width to 63) ); +ex6_valid_latch: tri_rlmreg_p + generic map (width => ex6_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex6_valid_offset to ex6_valid_offset+ex6_valid_q'length-1), + scout => sov_0(ex6_valid_offset to ex6_valid_offset+ex6_valid_q'length-1), + din => ex6_valid_d(0 to thdid_width-1), + dout => ex6_valid_q(0 to thdid_width-1) ); +ex6_ttype_latch: tri_rlmreg_p + generic map (width => ex6_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex6_ttype_offset to ex6_ttype_offset+ex6_ttype_q'length-1), + scout => sov_0(ex6_ttype_offset to ex6_ttype_offset+ex6_ttype_q'length-1), + din => ex6_ttype_d(0 to ttype_width-1), + dout => ex6_ttype_q(0 to ttype_width-1) ); +ex6_ws_latch: tri_rlmreg_p + generic map (width => ex6_ws_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex5_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex6_ws_offset to ex6_ws_offset+ex6_ws_q'length-1), + scout => sov_0(ex6_ws_offset to ex6_ws_offset+ex6_ws_q'length-1), + din => ex6_ws_d(0 to ws_width-1), + dout => ex6_ws_q(0 to ws_width-1) ); +ex6_rs_is_latch: tri_rlmreg_p + generic map (width => ex6_rs_is_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex5_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex6_rs_is_offset to ex6_rs_is_offset+ex6_rs_is_q'length-1), + scout => sov_0(ex6_rs_is_offset to ex6_rs_is_offset+ex6_rs_is_q'length-1), + din => ex6_rs_is_d(0 to rs_is_width-1), + dout => ex6_rs_is_q(0 to rs_is_width-1) ); +ex6_ra_entry_latch: tri_rlmreg_p + generic map (width => ex6_ra_entry_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex5_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex6_ra_entry_offset to ex6_ra_entry_offset+ex6_ra_entry_q'length-1), + scout => sov_0(ex6_ra_entry_offset to ex6_ra_entry_offset+ex6_ra_entry_q'length-1), + din => ex6_ra_entry_d(0 to ra_entry_width-1), + dout => ex6_ra_entry_q(0 to ra_entry_width-1) ); +ex6_state_latch: tri_rlmreg_p + generic map (width => ex6_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex5_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex6_state_offset to ex6_state_offset+ex6_state_q'length-1), + scout => sov_0(ex6_state_offset to ex6_state_offset+ex6_state_q'length-1), + din => ex6_state_d(0 to state_width-1), + dout => ex6_state_q(0 to state_width-1) ); +ex6_pid_latch: tri_rlmreg_p + generic map (width => ex6_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex5_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex6_pid_offset to ex6_pid_offset+ex6_pid_q'length-1), + scout => sov_0(ex6_pid_offset to ex6_pid_offset+ex6_pid_q'length-1), + din => ex6_pid_d, + dout => ex6_pid_q ); +ex6_extclass_latch: tri_rlmreg_p + generic map (width => ex6_extclass_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex5_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex6_extclass_offset to ex6_extclass_offset+ex6_extclass_q'length-1), + scout => sov_0(ex6_extclass_offset to ex6_extclass_offset+ex6_extclass_q'length-1), + din => ex6_extclass_d(0 to extclass_width-1), + dout => ex6_extclass_q(0 to extclass_width-1) ); +ex6_tlbsel_latch: tri_rlmreg_p + generic map (width => ex6_tlbsel_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex5_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex6_tlbsel_offset to ex6_tlbsel_offset+ex6_tlbsel_q'length-1), + scout => sov_0(ex6_tlbsel_offset to ex6_tlbsel_offset+ex6_tlbsel_q'length-1), + din => ex6_tlbsel_d(0 to tlbsel_width-1), + dout => ex6_tlbsel_q(0 to tlbsel_width-1) ); +ex6_data_in_latch: tri_rlmreg_p + generic map (width => ex6_data_in_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex5_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex6_data_in_offset to ex6_data_in_offset+ex6_data_in_q'length-1), + scout => sov_0(ex6_data_in_offset to ex6_data_in_offset+ex6_data_in_q'length-1), + din => ex6_data_in_d(64-rs_data_width to 63), + dout => ex6_data_in_q(64-rs_data_width to 63) ); +ex7_valid_latch: tri_rlmreg_p + generic map (width => ex7_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ex7_valid_offset to ex7_valid_offset+ex7_valid_q'length-1), + scout => sov_1(ex7_valid_offset to ex7_valid_offset+ex7_valid_q'length-1), + din => ex7_valid_d(0 to thdid_width-1), + dout => ex7_valid_q(0 to thdid_width-1) ); +ex7_ttype_latch: tri_rlmreg_p + generic map (width => ex7_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ex7_ttype_offset to ex7_ttype_offset+ex7_ttype_q'length-1), + scout => sov_1(ex7_ttype_offset to ex7_ttype_offset+ex7_ttype_q'length-1), + din => ex7_ttype_d(0 to ttype_width-1), + dout => ex7_ttype_q(0 to ttype_width-1) ); +ex7_tlbsel_latch: tri_rlmreg_p + generic map (width => ex7_tlbsel_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex6_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ex7_tlbsel_offset to ex7_tlbsel_offset+ex7_tlbsel_q'length-1), + scout => sov_1(ex7_tlbsel_offset to ex7_tlbsel_offset+ex7_tlbsel_q'length-1), + din => ex7_tlbsel_d(0 to tlbsel_width-1), + dout => ex7_tlbsel_q(0 to tlbsel_width-1) ); +iu1_flush_enab_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(iu1_flush_enab_offset), + scout => sov_0(iu1_flush_enab_offset), + din => iu1_flush_enab_d, + dout => iu1_flush_enab_q); +iu2_n_flush_req_latch: tri_rlmreg_p + generic map (width => iu2_n_flush_req_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu1_or_iu2_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(iu2_n_flush_req_offset to iu2_n_flush_req_offset+iu2_n_flush_req_q'length-1), + scout => sov_0(iu2_n_flush_req_offset to iu2_n_flush_req_offset+iu2_n_flush_req_q'length-1), + din => iu2_n_flush_req_d(0 to thdid_width-1), + dout => iu2_n_flush_req_q(0 to thdid_width-1) ); +hold_req_latch: tri_rlmreg_p + generic map (width => hold_req_q'length, init => 15, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => not_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(hold_req_offset to hold_req_offset+hold_req_q'length-1), + scout => sov_0(hold_req_offset to hold_req_offset+hold_req_q'length-1), + din => hold_req_d(0 to thdid_width-1), + dout => hold_req_q(0 to thdid_width-1) ); +tlb_miss_latch: tri_rlmreg_p + generic map (width => tlb_miss_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_miss_offset to tlb_miss_offset+tlb_miss_q'length-1), + scout => sov_0(tlb_miss_offset to tlb_miss_offset+tlb_miss_q'length-1), + din => tlb_miss_d(0 to thdid_width-1), + dout => tlb_miss_q(0 to thdid_width-1) ); +tlb_req_inprogress_latch: tri_rlmreg_p + generic map (width => tlb_req_inprogress_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_req_inprogress_offset to tlb_req_inprogress_offset+tlb_req_inprogress_q'length-1), + scout => sov_0(tlb_req_inprogress_offset to tlb_req_inprogress_offset+tlb_req_inprogress_q'length-1), + din => tlb_req_inprogress_d(0 to thdid_width-1), + dout => tlb_req_inprogress_q(0 to thdid_width-1) ); +iu1_valid_latch: tri_rlmreg_p + generic map (width => iu1_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(iu1_valid_offset to iu1_valid_offset+iu1_valid_q'length-1), + scout => sov_0(iu1_valid_offset to iu1_valid_offset+iu1_valid_q'length-1), + din => iu1_valid_d(0 to thdid_width-1), + dout => iu1_valid_q(0 to thdid_width-1) ); +iu1_state_latch: tri_rlmreg_p + generic map (width => iu1_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(iu1_state_offset to iu1_state_offset+iu1_state_q'length-1), + scout => sov_0(iu1_state_offset to iu1_state_offset+iu1_state_q'length-1), + din => iu1_state_d(0 to state_width-1), + dout => iu1_state_q(0 to state_width-1) ); +iu1_pid_latch: tri_rlmreg_p + generic map (width => iu1_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(iu1_pid_offset to iu1_pid_offset+iu1_pid_q'length-1), + scout => sov_0(iu1_pid_offset to iu1_pid_offset+iu1_pid_q'length-1), + din => iu1_pid_d, + dout => iu1_pid_q ); +iu2_valid_latch: tri_rlmreg_p + generic map (width => iu2_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(iu2_valid_offset to iu2_valid_offset+iu2_valid_q'length-1), + scout => sov_0(iu2_valid_offset to iu2_valid_offset+iu2_valid_q'length-1), + din => iu2_valid_d(0 to thdid_width-1), + dout => iu2_valid_q(0 to thdid_width-1) ); +iu2_state_latch: tri_rlmreg_p + generic map (width => iu2_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu1_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(iu2_state_offset to iu2_state_offset+iu2_state_q'length-1), + scout => sov_0(iu2_state_offset to iu2_state_offset+iu2_state_q'length-1), + din => iu2_state_d(0 to state_width-1), + dout => iu2_state_q(0 to state_width-1) ); +iu2_pid_latch: tri_rlmreg_p + generic map (width => iu2_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu1_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(iu2_pid_offset to iu2_pid_offset+iu2_pid_q'length-1), + scout => sov_0(iu2_pid_offset to iu2_pid_offset+iu2_pid_q'length-1), + din => iu2_pid_d, + dout => iu2_pid_q ); +iu2_miss_latch: tri_rlmreg_p + generic map (width => iu2_miss_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu1_or_iu2_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(iu2_miss_offset to iu2_miss_offset+iu2_miss_q'length-1), + scout => sov_0(iu2_miss_offset to iu2_miss_offset+iu2_miss_q'length-1), + din => iu2_miss_d, + dout => iu2_miss_q ); +iu2_multihit_latch: tri_rlmreg_p + generic map (width => iu2_multihit_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu1_or_iu2_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(iu2_multihit_offset to iu2_multihit_offset+iu2_multihit_q'length-1), + scout => sov_0(iu2_multihit_offset to iu2_multihit_offset+iu2_multihit_q'length-1), + din => iu2_multihit_d, + dout => iu2_multihit_q ); +iu2_parerr_latch: tri_rlmreg_p + generic map (width => iu2_parerr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu1_or_iu2_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(iu2_parerr_offset to iu2_parerr_offset+iu2_parerr_q'length-1), + scout => sov_0(iu2_parerr_offset to iu2_parerr_offset+iu2_parerr_q'length-1), + din => iu2_parerr_d, + dout => iu2_parerr_q ); +iu2_isi_latch: tri_rlmreg_p + generic map (width => iu2_isi_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => not_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(iu2_isi_offset to iu2_isi_offset+iu2_isi_q'length-1), + scout => sov_0(iu2_isi_offset to iu2_isi_offset+iu2_isi_q'length-1), + din => iu2_isi_d, + dout => iu2_isi_q ); +iu2_tlbreq_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => notlb_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(iu2_tlbreq_offset), + scout => sov_0(iu2_tlbreq_offset), + din => iu2_tlbreq_d, + dout => iu2_tlbreq_q); +iu2_multihit_b_pt_latch: tri_rlmreg_p + generic map (width => iu2_multihit_b_pt_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu1_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(iu2_multihit_b_pt_offset to iu2_multihit_b_pt_offset+iu2_multihit_b_pt_q'length-1), + scout => sov_0(iu2_multihit_b_pt_offset to iu2_multihit_b_pt_offset+iu2_multihit_b_pt_q'length-1), + din => iu2_multihit_b_pt_d, + dout => iu2_multihit_b_pt_q ); +iu2_first_hit_entry_pt_latch: tri_rlmreg_p + generic map (width => iu2_first_hit_entry_pt_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu1_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(iu2_first_hit_entry_pt_offset to iu2_first_hit_entry_pt_offset+iu2_first_hit_entry_pt_q'length-1), + scout => sov_0(iu2_first_hit_entry_pt_offset to iu2_first_hit_entry_pt_offset+iu2_first_hit_entry_pt_q'length-1), + din => iu2_first_hit_entry_pt_d, + dout => iu2_first_hit_entry_pt_q ); +iu2_cam_cmp_data_latch: tri_rlmreg_p + generic map (width => iu2_cam_cmp_data_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu1_cmp_data_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(iu2_cam_cmp_data_offset to iu2_cam_cmp_data_offset+iu2_cam_cmp_data_q'length-1), + scout => sov_0(iu2_cam_cmp_data_offset to iu2_cam_cmp_data_offset+iu2_cam_cmp_data_q'length-1), + din => iu2_cam_cmp_data_d(0 to cam_data_width-1), + dout => iu2_cam_cmp_data_q(0 to cam_data_width-1)); +iu2_array_cmp_data_latch: tri_rlmreg_p + generic map (width => iu2_array_cmp_data_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu1_cmp_data_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(iu2_array_cmp_data_offset to iu2_array_cmp_data_offset+iu2_array_cmp_data_q'length-1), + scout => sov_0(iu2_array_cmp_data_offset to iu2_array_cmp_data_offset+iu2_array_cmp_data_q'length-1), + din => iu2_array_cmp_data_d(0 to array_data_width-1), + dout => iu2_array_cmp_data_q(0 to array_data_width-1)); +ex4_rd_cam_data_latch: tri_rlmreg_p + generic map (width => ex4_rd_cam_data_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_rd_data_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex4_rd_cam_data_offset to ex4_rd_cam_data_offset+ex4_rd_cam_data_q'length-1), + scout => sov_0(ex4_rd_cam_data_offset to ex4_rd_cam_data_offset+ex4_rd_cam_data_q'length-1), + din => ex4_rd_cam_data_d(0 to cam_data_width-1), + dout => ex4_rd_cam_data_q(0 to cam_data_width-1)); +ex4_rd_array_data_latch: tri_rlmreg_p + generic map (width => ex4_rd_array_data_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_rd_data_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex4_rd_array_data_offset to ex4_rd_array_data_offset+ex4_rd_array_data_q'length-1), + scout => sov_0(ex4_rd_array_data_offset to ex4_rd_array_data_offset+ex4_rd_array_data_q'length-1), + din => ex4_rd_array_data_d(0 to array_data_width-1), + dout => ex4_rd_array_data_q(0 to array_data_width-1)); +ex3_parerr_latch: tri_rlmreg_p + generic map (width => ex3_parerr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => not_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_parerr_offset to ex3_parerr_offset+ex3_parerr_q'length-1), + scout => sov_0(ex3_parerr_offset to ex3_parerr_offset+ex3_parerr_q'length-1), + din => ex3_parerr_d, + dout => ex3_parerr_q ); +ex4_parerr_latch: tri_rlmreg_p + generic map (width => ex4_parerr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex4_parerr_offset to ex4_parerr_offset+ex4_parerr_q'length-1), + scout => sov_0(ex4_parerr_offset to ex4_parerr_offset+ex4_parerr_q'length-1), + din => ex4_parerr_d, + dout => ex4_parerr_q ); +ex4_ieen_latch: tri_rlmreg_p + generic map (width => ex4_ieen_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex4_ieen_offset to ex4_ieen_offset+ex4_ieen_q'length-1), + scout => sov_0(ex4_ieen_offset to ex4_ieen_offset+ex4_ieen_q'length-1), + din => ex4_ieen_d(0 to ex4_ieen_d'length-1), + dout => ex4_ieen_q(0 to ex4_ieen_q'length-1)); +ex5_ieen_latch: tri_rlmreg_p + generic map (width => ex5_ieen_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex5_ieen_offset to ex5_ieen_offset+ex5_ieen_q'length-1), + scout => sov_0(ex5_ieen_offset to ex5_ieen_offset+ex5_ieen_q'length-1), + din => ex5_ieen_d(0 to ex5_ieen_d'length-1), + dout => ex5_ieen_q(0 to ex5_ieen_q'length-1)); +ex6_ieen_latch: tri_rlmreg_p + generic map (width => ex6_ieen_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex6_ieen_offset to ex6_ieen_offset+ex6_ieen_q'length-1), + scout => sov_0(ex6_ieen_offset to ex6_ieen_offset+ex6_ieen_q'length-1), + din => ex6_ieen_d(0 to ex6_ieen_d'length-1), + dout => ex6_ieen_q(0 to ex6_ieen_q'length-1)); +mmucr1_latch: tri_rlmreg_p + generic map (width => mmucr1_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(mmucr1_offset to mmucr1_offset+mmucr1_q'length-1), + scout => sov_0(mmucr1_offset to mmucr1_offset+mmucr1_q'length-1), + din => mmucr1_d, + dout => mmucr1_q ); +rpn_holdreg0_latch: tri_rlmreg_p + generic map (width => rpn_holdreg0_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex6_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(rpn_holdreg0_offset to rpn_holdreg0_offset+rpn_holdreg0_q'length-1), + scout => sov_0(rpn_holdreg0_offset to rpn_holdreg0_offset+rpn_holdreg0_q'length-1), + din => rpn_holdreg0_d(0 to 63), + dout => rpn_holdreg0_q(0 to 63) ); +rpn_holdreg1_latch: tri_rlmreg_p + generic map (width => rpn_holdreg1_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex6_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(rpn_holdreg1_offset to rpn_holdreg1_offset+rpn_holdreg1_q'length-1), + scout => sov_0(rpn_holdreg1_offset to rpn_holdreg1_offset+rpn_holdreg1_q'length-1), + din => rpn_holdreg1_d(0 to 63), + dout => rpn_holdreg1_q(0 to 63) ); +rpn_holdreg2_latch: tri_rlmreg_p + generic map (width => rpn_holdreg2_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex6_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(rpn_holdreg2_offset to rpn_holdreg2_offset+rpn_holdreg2_q'length-1), + scout => sov_0(rpn_holdreg2_offset to rpn_holdreg2_offset+rpn_holdreg2_q'length-1), + din => rpn_holdreg2_d(0 to 63), + dout => rpn_holdreg2_q(0 to 63) ); +rpn_holdreg3_latch: tri_rlmreg_p + generic map (width => rpn_holdreg3_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex6_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(rpn_holdreg3_offset to rpn_holdreg3_offset+rpn_holdreg3_q'length-1), + scout => sov_0(rpn_holdreg3_offset to rpn_holdreg3_offset+rpn_holdreg3_q'length-1), + din => rpn_holdreg3_d(0 to 63), + dout => rpn_holdreg3_q(0 to 63) ); +entry_valid_latch: tri_rlmreg_p + generic map (width => entry_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => entry_valid_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(entry_valid_offset to entry_valid_offset+entry_valid_q'length-1), + scout => sov_0(entry_valid_offset to entry_valid_offset+entry_valid_q'length-1), + din => entry_valid, + dout => entry_valid_q ); +entry_match_latch: tri_rlmreg_p + generic map (width => entry_match_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => entry_match_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(entry_match_offset to entry_match_offset+entry_match_q'length-1), + scout => sov_0(entry_match_offset to entry_match_offset+entry_match_q'length-1), + din => entry_match, + dout => entry_match_q ); +watermark_latch: tri_rlmreg_p + generic map (width => watermark_q'length, init => 13, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex6_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(watermark_offset to watermark_offset+watermark_q'length-1), + scout => sov_0(watermark_offset to watermark_offset+watermark_q'length-1), + din => watermark_d(0 to watermark_width-1), + dout => watermark_q(0 to watermark_width-1) ); +eptr_latch: tri_rlmreg_p + generic map (width => eptr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => mmucr1_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(eptr_offset to eptr_offset+eptr_q'length-1), + scout => sov_0(eptr_offset to eptr_offset+eptr_q'length-1), + din => eptr_d(0 to eptr_width-1), + dout => eptr_q(0 to eptr_width-1) ); +lru_latch: tri_rlmreg_p + generic map (width => lru_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lru_update_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(lru_offset to lru_offset+lru_q'length-1), + scout => sov_0(lru_offset to lru_offset+lru_q'length-1), + din => lru_d(1 to lru_width), + dout => lru_q(1 to lru_width) ); +lru_update_event_latch: tri_rlmreg_p + generic map (width => lru_update_event_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => not_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(lru_update_event_offset to lru_update_event_offset+lru_update_event_q'length-1), + scout => sov_0(lru_update_event_offset to lru_update_event_offset+lru_update_event_q'length-1), + din => lru_update_event_d, + dout => lru_update_event_q ); +lru_debug_latch: tri_rlmreg_p + generic map (width => lru_debug_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => debug_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(lru_debug_offset to lru_debug_offset+lru_debug_q'length-1), + scout => sov_0(lru_debug_offset to lru_debug_offset+lru_debug_q'length-1), + din => lru_debug_d, + dout => lru_debug_q ); +snoop_val_latch: tri_rlmreg_p + generic map (width => snoop_val_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(snoop_val_offset to snoop_val_offset+snoop_val_q'length-1), + scout => sov_1(snoop_val_offset to snoop_val_offset+snoop_val_q'length-1), + din => snoop_val_d, + dout => snoop_val_q ); +snoop_attr_latch: tri_rlmreg_p + generic map (width => snoop_attr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => snoop_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(snoop_attr_offset to snoop_attr_offset+snoop_attr_q'length-1), + scout => sov_1(snoop_attr_offset to snoop_attr_offset+snoop_attr_q'length-1), + din => snoop_attr_d, + dout => snoop_attr_q ); +snoop_addr_latch: tri_rlmreg_p + generic map (width => snoop_addr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => snoop_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(snoop_addr_offset to snoop_addr_offset+snoop_addr_q'length-1), + scout => sov_1(snoop_addr_offset to snoop_addr_offset+snoop_addr_q'length-1), + din => snoop_addr_d(52-epn_width to 51), + dout => snoop_addr_q(52-epn_width to 51) ); +por_seq_latch: tri_rlmreg_p + generic map (width => por_seq_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(por_seq_offset to por_seq_offset+por_seq_q'length-1), + scout => sov_1(por_seq_offset to por_seq_offset+por_seq_q'length-1), + din => por_seq_d(0 to por_seq_width-1), + dout => por_seq_q(0 to por_seq_width-1) ); +tlb_rel_val_latch: tri_rlmreg_p + generic map (width => tlb_rel_val_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(tlb_rel_val_offset to tlb_rel_val_offset+tlb_rel_val_q'length-1), + scout => sov_1(tlb_rel_val_offset to tlb_rel_val_offset+tlb_rel_val_q'length-1), + din => tlb_rel_val_d, + dout => tlb_rel_val_q ); +tlb_rel_data_latch: tri_rlmreg_p + generic map (width => tlb_rel_data_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_rel_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(tlb_rel_data_offset to tlb_rel_data_offset+tlb_rel_data_q'length-1), + scout => sov_1(tlb_rel_data_offset to tlb_rel_data_offset+tlb_rel_data_q'length-1), + din => tlb_rel_data_d, + dout => tlb_rel_data_q ); +iu_mm_ierat_flush_latch: tri_rlmreg_p + generic map (width => iu_mm_ierat_flush_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(iu_mm_ierat_flush_offset to iu_mm_ierat_flush_offset+iu_mm_ierat_flush_q'length-1), + scout => sov_1(iu_mm_ierat_flush_offset to iu_mm_ierat_flush_offset+iu_mm_ierat_flush_q'length-1), + din => iu_mm_ierat_flush_d(0 to thdid_width-1), + dout => iu_mm_ierat_flush_q(0 to thdid_width-1) ); +iu_xu_ierat_ex2_flush_latch: tri_rlmreg_p + generic map (width => iu_xu_ierat_ex2_flush_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(iu_xu_ierat_ex2_flush_offset to iu_xu_ierat_ex2_flush_offset+iu_xu_ierat_ex2_flush_q'length-1), + scout => sov_1(iu_xu_ierat_ex2_flush_offset to iu_xu_ierat_ex2_flush_offset+iu_xu_ierat_ex2_flush_q'length-1), + din => iu_xu_ierat_ex2_flush_d(0 to thdid_width-1), + dout => iu_xu_ierat_ex2_flush_q(0 to thdid_width-1) ); +ccr2_frat_paranoia_latch: tri_rlmreg_p + generic map (width => ccr2_frat_paranoia_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ccr2_frat_paranoia_offset to ccr2_frat_paranoia_offset+ccr2_frat_paranoia_q'length-1), + scout => sov_1(ccr2_frat_paranoia_offset to ccr2_frat_paranoia_offset+ccr2_frat_paranoia_q'length-1), + din => ccr2_frat_paranoia_d, + dout => ccr2_frat_paranoia_q ); +ccr2_notlb_latch: tri_rlmlatch_p + generic map (init => 1, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ccr2_notlb_offset), + scout => sov_1(ccr2_notlb_offset), + din => xu_iu_hid_mmu_mode, + dout => ccr2_notlb_q); +mchk_flash_inv_latch: tri_rlmreg_p + generic map (width => mchk_flash_inv_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu2_to_iu4_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mchk_flash_inv_offset to mchk_flash_inv_offset+mchk_flash_inv_q'length-1), + scout => sov_1(mchk_flash_inv_offset to mchk_flash_inv_offset+mchk_flash_inv_q'length-1), + din => mchk_flash_inv_d, + dout => mchk_flash_inv_q ); +xucr4_mmu_mchk_latch: tri_rlmlatch_p + generic map (init => 1, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(xucr4_mmu_mchk_offset), + scout => sov_1(xucr4_mmu_mchk_offset), + din => xu_iu_xucr4_mmu_mchk, + dout => xucr4_mmu_mchk_q); +iu1_debug_latch: tri_rlmreg_p + generic map (width => iu1_debug_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => trace_bus_enable_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(iu1_debug_offset to iu1_debug_offset+iu1_debug_q'length-1), + scout => sov_1(iu1_debug_offset to iu1_debug_offset+iu1_debug_q'length-1), + din => iu1_debug_d, + dout => iu1_debug_q); +iu2_debug_latch: tri_rlmreg_p + generic map (width => iu2_debug_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => debug_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(iu2_debug_offset to iu2_debug_offset+iu2_debug_q'length-1), + scout => sov_1(iu2_debug_offset to iu2_debug_offset+iu2_debug_q'length-1), + din => iu2_debug_d, + dout => iu2_debug_q); +iu1_stg_act_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(iu1_stg_act_offset), + scout => sov_1(iu1_stg_act_offset), + din => iu1_stg_act_d, + dout => iu1_stg_act_q); +iu2_stg_act_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(iu2_stg_act_offset), + scout => sov_1(iu2_stg_act_offset), + din => iu2_stg_act_d, + dout => iu2_stg_act_q); +iu3_stg_act_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(iu3_stg_act_offset), + scout => sov_1(iu3_stg_act_offset), + din => iu3_stg_act_d, + dout => iu3_stg_act_q); +iu4_stg_act_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(iu4_stg_act_offset), + scout => sov_1(iu4_stg_act_offset), + din => iu4_stg_act_d, + dout => iu4_stg_act_q); +ex1_stg_act_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ex1_stg_act_offset), + scout => sov_1(ex1_stg_act_offset), + din => ex1_stg_act_d, + dout => ex1_stg_act_q); +ex2_stg_act_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ex2_stg_act_offset), + scout => sov_1(ex2_stg_act_offset), + din => ex2_stg_act_d, + dout => ex2_stg_act_q); +ex3_stg_act_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ex3_stg_act_offset), + scout => sov_1(ex3_stg_act_offset), + din => ex3_stg_act_d, + dout => ex3_stg_act_q); +ex4_stg_act_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ex4_stg_act_offset), + scout => sov_1(ex4_stg_act_offset), + din => ex4_stg_act_d, + dout => ex4_stg_act_q); +ex5_stg_act_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ex5_stg_act_offset), + scout => sov_1(ex5_stg_act_offset), + din => ex5_stg_act_d, + dout => ex5_stg_act_q); +ex6_stg_act_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ex6_stg_act_offset), + scout => sov_1(ex6_stg_act_offset), + din => ex6_stg_act_d, + dout => ex6_stg_act_q); +ex7_stg_act_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ex7_stg_act_offset), + scout => sov_1(ex7_stg_act_offset), + din => ex7_stg_act_d, + dout => ex7_stg_act_q); +tlb_rel_act_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(tlb_rel_act_offset), + scout => sov_1(tlb_rel_act_offset), + din => tlb_rel_act_d, + dout => tlb_rel_act_q); +snoop_act_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(snoop_act_offset), + scout => sov_1(snoop_act_offset), + din => mm_iu_ierat_snoop_coming, + dout => snoop_act_q); +trace_bus_enable_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(trace_bus_enable_offset), + scout => sov_1(trace_bus_enable_offset), + din => pc_iu_trace_bus_enable, + dout => trace_bus_enable_q); +an_ac_grffence_en_dc_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(an_ac_grffence_en_dc_offset), + scout => sov_1(an_ac_grffence_en_dc_offset), + din => an_ac_grffence_en_dc_q, + dout => an_ac_grffence_en_dc_q); +spare_a_latch: tri_rlmreg_p + generic map (width => 16, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spare_a_offset to spare_a_offset+15), + scout => sov_1(spare_a_offset to spare_a_offset+15), + din => spare_q(0 to 15), + dout => spare_q(0 to 15) ); +spare_b_latch: tri_rlmreg_p + generic map (width => 16, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spare_b_offset to spare_b_offset+15), + scout => sov_1(spare_b_offset to spare_b_offset+15), + din => spare_q(16 to 31), + dout => spare_q(16 to 31) ); +mpg_bcfg_gen: if expand_type /= 1 generate +bcfg_epn_0to15_latch: tri_slat_scan + generic map (width => 16, init => std_ulogic_vector( to_unsigned( bcfg_epn_0to15, 16 ) ), + reset_inverts_scan => true, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + dclk => lcb_dclk, + lclk => lcb_lclk, + scan_in => bsiv(bcfg_offset to bcfg_offset+15), + scan_out => bsov(bcfg_offset to bcfg_offset+15), + q => bcfg_q(0 to 15), + q_b => bcfg_q_b(0 to 15) ); +bcfg_epn_16to31_latch: tri_slat_scan + generic map (width => 16, init => std_ulogic_vector( to_unsigned( bcfg_epn_16to31, 16 ) ), + reset_inverts_scan => true, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + dclk => lcb_dclk, + lclk => lcb_lclk, + scan_in => bsiv(bcfg_offset+16 to bcfg_offset+31), + scan_out => bsov(bcfg_offset+16 to bcfg_offset+31), + q => bcfg_q(16 to 31), + q_b => bcfg_q_b(16 to 31) ); +bcfg_epn_32to47_latch: tri_slat_scan + generic map (width => 16, init => std_ulogic_vector( to_unsigned( bcfg_epn_32to47, 16 ) ), + reset_inverts_scan => true, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + dclk => lcb_dclk, + lclk => lcb_lclk, + scan_in => bsiv(bcfg_offset+32 to bcfg_offset+47), + scan_out => bsov(bcfg_offset+32 to bcfg_offset+47), + q => bcfg_q(32 to 47), + q_b => bcfg_q_b(32 to 47) ); +bcfg_epn_48to51_latch: tri_slat_scan + generic map (width => 4, init => std_ulogic_vector( to_unsigned( bcfg_epn_48to51, 4 ) ), + reset_inverts_scan => true, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + dclk => lcb_dclk, + lclk => lcb_lclk, + scan_in => bsiv(bcfg_offset+48 to bcfg_offset+51), + scan_out => bsov(bcfg_offset+48 to bcfg_offset+51), + q => bcfg_q(48 to 51), + q_b => bcfg_q_b(48 to 51) ); +bcfg_rpn_22to31_latch: tri_slat_scan + generic map (width => 10, init => std_ulogic_vector( to_unsigned( bcfg_rpn_22to31, 10 ) ), + reset_inverts_scan => true, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + dclk => lcb_dclk, + lclk => lcb_lclk, + scan_in => bsiv(bcfg_offset+52 to bcfg_offset+61), + scan_out => bsov(bcfg_offset+52 to bcfg_offset+61), + q => bcfg_q(52 to 61), + q_b => bcfg_q_b(52 to 61) ); +bcfg_rpn_32to47_latch: tri_slat_scan + generic map (width => 16, init => std_ulogic_vector( to_unsigned( bcfg_rpn_32to47, 16 ) ), + reset_inverts_scan => true, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + dclk => lcb_dclk, + lclk => lcb_lclk, + scan_in => bsiv(bcfg_offset+62 to bcfg_offset+77), + scan_out => bsov(bcfg_offset+62 to bcfg_offset+77), + q => bcfg_q(62 to 77), + q_b => bcfg_q_b(62 to 77) ); +bcfg_rpn_48to51_latch: tri_slat_scan + generic map (width => 4, init => std_ulogic_vector( to_unsigned( bcfg_rpn_48to51, 4 ) ), + reset_inverts_scan => true, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + dclk => lcb_dclk, + lclk => lcb_lclk, + scan_in => bsiv(bcfg_offset+78 to bcfg_offset+81), + scan_out => bsov(bcfg_offset+78 to bcfg_offset+81), + q => bcfg_q(78 to 81), + q_b => bcfg_q_b(78 to 81) ); +bcfg_attr_latch: tri_slat_scan + generic map (width => 5, init => std_ulogic_vector( to_unsigned( bcfg_attr, 5 ) ), + reset_inverts_scan => true, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + dclk => lcb_dclk, + lclk => lcb_lclk, + scan_in => bsiv(bcfg_offset+82 to bcfg_offset+86), + scan_out => bsov(bcfg_offset+82 to bcfg_offset+86), + q => bcfg_q(82 to 86), + q_b => bcfg_q_b(82 to 86) ); +bcfg_rpn2_32to47_latch: tri_slat_scan + generic map (width => 16, init => std_ulogic_vector( to_unsigned( bcfg_rpn2_32to47, 16 ) ), + reset_inverts_scan => true, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + dclk => lcb_dclk, + lclk => lcb_lclk, + scan_in => bsiv(bcfg_offset+87 to bcfg_offset+102), + scan_out => bsov(bcfg_offset+87 to bcfg_offset+102), + q => bcfg_q(87 to 102), + q_b => bcfg_q_b(87 to 102) ); +bcfg_rpn2_48to51_latch: tri_slat_scan + generic map (width => 4, init => std_ulogic_vector( to_unsigned( bcfg_rpn2_48to51, 4 ) ), + reset_inverts_scan => true, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + dclk => lcb_dclk, + lclk => lcb_lclk, + scan_in => bsiv(bcfg_offset+103 to bcfg_offset+106), + scan_out => bsov(bcfg_offset+103 to bcfg_offset+106), + q => bcfg_q(103 to 106), + q_b => bcfg_q_b(103 to 106) ); +bcfg_spare_latch: tri_slat_scan + generic map (width => 16, init => std_ulogic_vector( to_unsigned( 0, 16 ) ), + reset_inverts_scan => true, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + dclk => lcb_dclk, + lclk => lcb_lclk, + scan_in => bsiv(bcfg_offset+107 to bcfg_offset+122), + scan_out => bsov(bcfg_offset+107 to bcfg_offset+122), + q => bcfg_q(107 to 122), + q_b => bcfg_q_b(107 to 122) ); +end generate mpg_bcfg_gen; +fpga_bcfg_gen: if expand_type = 1 generate +bcfg_epn_0to15_latch: tri_rlmreg_p + generic map (width => 16, init => bcfg_epn_0to15, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(0 to 15), + scout => bsov(0 to 15), + din => bcfg_q(0 to 15), + dout => bcfg_q(0 to 15) ); +bcfg_epn_16to31_latch: tri_rlmreg_p + generic map (width => 16, init => bcfg_epn_16to31, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(16 to 31), + scout => bsov(16 to 31), + din => bcfg_q(16 to 31), + dout => bcfg_q(16 to 31) ); +bcfg_epn_32to47_latch: tri_rlmreg_p + generic map (width => 16, init => bcfg_epn_32to47, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(32 to 47), + scout => bsov(32 to 47), + din => bcfg_q(32 to 47), + dout => bcfg_q(32 to 47) ); +bcfg_epn_48to51_latch: tri_rlmreg_p + generic map (width => 4, init => bcfg_epn_48to51, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(48 to 51), + scout => bsov(48 to 51), + din => bcfg_q(48 to 51), + dout => bcfg_q(48 to 51) ); +bcfg_rpn_22to31_latch: tri_rlmreg_p + generic map (width => 10, init => bcfg_rpn_22to31, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(52 to 61), + scout => bsov(52 to 61), + din => bcfg_q(52 to 61), + dout => bcfg_q(52 to 61) ); +bcfg_rpn_32to47_latch: tri_rlmreg_p + generic map (width => 16, init => bcfg_rpn_32to47, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(62 to 77), + scout => bsov(62 to 77), + din => bcfg_q(62 to 77), + dout => bcfg_q(62 to 77) ); +bcfg_rpn_48to51_latch: tri_rlmreg_p + generic map (width => 4, init => bcfg_rpn_48to51, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(78 to 81), + scout => bsov(78 to 81), + din => bcfg_q(78 to 81), + dout => bcfg_q(78 to 81) ); +bcfg_attr_latch: tri_rlmreg_p + generic map (width => 5, init => bcfg_attr, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(82 to 86), + scout => bsov(82 to 86), + din => bcfg_q(82 to 86), + dout => bcfg_q(82 to 86) ); +bcfg_rpn2_32to47_latch: tri_rlmreg_p + generic map (width => 16, init => bcfg_rpn2_32to47, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(87 to 102), + scout => bsov(87 to 102), + din => bcfg_q(87 to 102), + dout => bcfg_q(87 to 102) ); +bcfg_rpn2_48to51_latch: tri_rlmreg_p + generic map (width => 4, init => bcfg_rpn2_48to51, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(103 to 106), + scout => bsov(103 to 106), + din => bcfg_q(103 to 106), + dout => bcfg_q(103 to 106) ); +bcfg_spare_latch: tri_rlmreg_p + generic map (width => 16, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(107 to 122), + scout => bsov(107 to 122), + din => bcfg_q(107 to 122), + dout => bcfg_q(107 to 122) ); +end generate fpga_bcfg_gen; +perv_2to1_reg: tri_plat + generic map (width => 4, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ccflush_dc, + din(0) => pc_iu_func_sl_thold_2, + din(1) => pc_iu_func_slp_sl_thold_2, + din(2) => pc_iu_cfg_slp_sl_thold_2, + din(3) => pc_iu_sg_2, + q(0) => pc_func_sl_thold_1, + q(1) => pc_func_slp_sl_thold_1, + q(2) => pc_cfg_slp_sl_thold_1, + q(3) => pc_sg_1); +perv_1to0_reg: tri_plat + generic map (width => 4, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ccflush_dc, + din(0) => pc_func_sl_thold_1, + din(1) => pc_func_slp_sl_thold_1, + din(2) => pc_cfg_slp_sl_thold_1, + din(3) => pc_sg_1, + q(0) => pc_func_sl_thold_0, + q(1) => pc_func_slp_sl_thold_0, + q(2) => pc_cfg_slp_sl_thold_0, + q(3) => pc_sg_0); +perv_lcbor_func_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b, + thold => pc_func_sl_thold_0, + sg => pc_sg_0, + act_dis => lcb_act_dis_dc, + forcee => pc_func_sl_force, + thold_b => pc_func_sl_thold_0_b); +perv_lcbor_func_slp_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b, + thold => pc_func_slp_sl_thold_0, + sg => pc_sg_0, + act_dis => lcb_act_dis_dc, + forcee => pc_func_slp_sl_force, + thold_b => pc_func_slp_sl_thold_0_b); +mpg_bcfg_lcb_gen: if expand_type /= 1 generate +bcfg_lcb: tri_lcbs + generic map (expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + delay_lclkr => lcb_delay_lclkr_dc(0), + nclk => nclk, + forcee => pc_cfg_slp_sl_force, + thold_b => pc_cfg_slp_sl_thold_0_b, + dclk => lcb_dclk, + lclk => lcb_lclk ); +pc_cfg_slp_sl_thold_0_b <= NOT pc_cfg_slp_sl_thold_0; +pc_cfg_slp_sl_force <= pc_sg_0; +end generate mpg_bcfg_lcb_gen; +fpga_bcfg_lcb_gen: if expand_type = 1 generate +perv_lcbor_cfg_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b, + thold => pc_cfg_slp_sl_thold_0, + sg => pc_sg_0, + act_dis => lcb_act_dis_dc, + forcee => pc_cfg_slp_sl_force, + thold_b => pc_cfg_slp_sl_thold_0_b); +end generate fpga_bcfg_lcb_gen; +siv_0(0 TO scan_right_0) <= sov_0(1 to scan_right_0) & ac_func_scan_in(0); +ac_func_scan_out(0) <= sov_0(0); +siv_1(0 TO scan_right_1) <= sov_1(1 to scan_right_1) & ac_func_scan_in(1); +ac_func_scan_out(1) <= sov_1(0); +bsiv(0 TO boot_scan_right) <= bsov(1 to boot_scan_right) & ac_ccfg_scan_in; +ac_ccfg_scan_out <= bsov(0); +END IUQ_IC_IERAT; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_ic_insmux.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_ic_insmux.vhdl new file mode 100644 index 0000000..c15183d --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_ic_insmux.vhdl @@ -0,0 +1,389 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + +entity iuq_ic_insmux is +generic( expand_type: integer := 2 ); +port( + vdd :inout power_logic; + gnd :inout power_logic; + nclk :in clk_logic; + delay_lclkr :in std_ulogic; + mpw1_b :in std_ulogic; + mpw2_b :in std_ulogic; + forcee :in std_ulogic; + sg_0 :in std_ulogic; + thold_0_b :in std_ulogic; + scan_in :in std_ulogic; + scan_out :out std_ulogic; + inslat_act :in std_ulogic; + + iu2_rd_way_hit_b :in std_ulogic_vector(0 to 3); + load_iu2 :in std_ulogic ; + + icm_icd_reload_data :in std_ulogic_vector(0 to 143); + iu2_data_dataout_0 :in std_ulogic_vector(0 to 143); + iu2_data_dataout_1 :in std_ulogic_vector(0 to 143); + iu2_data_dataout_2 :in std_ulogic_vector(0 to 143); + iu2_data_dataout_3 :in std_ulogic_vector(0 to 143); + + iu3_instr0_buf :out std_ulogic_vector(0 to 35) ; + iu3_instr1_buf :out std_ulogic_vector(0 to 35) ; + iu3_instr2_buf :out std_ulogic_vector(0 to 35) ; + iu3_instr3_buf :out std_ulogic_vector(0 to 35) +); + +-- synopsys translate_off + + + +-- synopsys translate_on + + +end iuq_ic_insmux; + +architecture iuq_ic_insmux of iuq_ic_insmux is + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal inslat_lclk :clk_logic; + signal inslat_d1clk :std_ulogic; + signal inslat_d2clk :std_ulogic; + + signal iu3_instr0_si, iu3_instr0_so, iu3_instr0_l2_b, iu3_instr0_d1, iu3_instr0_d2 :std_ulogic_vector(0 to 35); + signal iu3_instr1_si, iu3_instr1_so, iu3_instr1_l2_b, iu3_instr1_d1, iu3_instr1_d2 :std_ulogic_vector(0 to 35); + signal iu3_instr2_si, iu3_instr2_so, iu3_instr2_l2_b, iu3_instr2_d1, iu3_instr2_d2 :std_ulogic_vector(0 to 35); + signal iu3_instr3_si, iu3_instr3_so, iu3_instr3_l2_b, iu3_instr3_d1, iu3_instr3_d2 :std_ulogic_vector(0 to 35); + signal iu3_instr0_oth_b, iu3_instr1_oth_b, iu3_instr2_oth_b, iu3_instr3_oth_b :std_ulogic_vector(0 to 35); + signal iu3_instr0_dx0_b, iu3_instr0_dx1_b, iu3_instr0_dx2_b, iu3_instr0_dx3_b :std_ulogic_vector(0 to 35); + signal iu3_instr1_dx0_b, iu3_instr1_dx1_b, iu3_instr1_dx2_b, iu3_instr1_dx3_b :std_ulogic_vector(0 to 35); + signal iu3_instr2_dx0_b, iu3_instr2_dx1_b, iu3_instr2_dx2_b, iu3_instr2_dx3_b :std_ulogic_vector(0 to 35); + signal iu3_instr3_dx0_b, iu3_instr3_dx1_b, iu3_instr3_dx2_b, iu3_instr3_dx3_b :std_ulogic_vector(0 to 35); + + +-- synopsys translate_off + + + + + + + + +-- synopsys translate_on + + + + + signal hit0_en0, hit0_en1, hit0_en2, hit0_en3 :std_ulogic_vector(0 to 35); + signal hit1_en0, hit1_en1, hit1_en2, hit1_en3 :std_ulogic_vector(0 to 35); + signal hit2_en0, hit2_en1, hit2_en2, hit2_en3 :std_ulogic_vector(0 to 35); + signal hit3_en0, hit3_en1, hit3_en2, hit3_en3 :std_ulogic_vector(0 to 35); + signal cached_enable :std_ulogic; + + signal hit0, hit1, hit2, hit3 :std_ulogic; +-- synopsys translate_off +-- synopsys translate_on + signal hit0_en_b, hit1_en_b, hit2_en_b, hit3_en_b :std_ulogic_vector(0 to 3); +-- synopsys translate_off +-- synopsys translate_on + signal hit0_en , hit1_en , hit2_en , hit3_en :std_ulogic_vector(0 to 7); +-- synopsys translate_off + + + + + + + +-- synopsys translate_on + + + +begin + + + + + + + + cached_enable <= not load_iu2 ; + + u_hit0_i1: hit0 <= not( iu2_rd_way_hit_b(0) ); + u_hit1_i1: hit1 <= not( iu2_rd_way_hit_b(1) ); + u_hit2_i1: hit2 <= not( iu2_rd_way_hit_b(2) ); + u_hit3_i1: hit3 <= not( iu2_rd_way_hit_b(3) ); + + u_hit0_a2_cp0: hit0_en_b(0) <= not( hit0 and cached_enable) ; + u_hit0_a2_cp1: hit0_en_b(1) <= not( hit0 and cached_enable) ; + u_hit0_a2_cp2: hit0_en_b(2) <= not( hit0 and cached_enable) ; + u_hit0_a2_cp3: hit0_en_b(3) <= not( hit0 and cached_enable) ; + + u_hit1_a2_cp0: hit1_en_b(0) <= not( hit1 and cached_enable) ; + u_hit1_a2_cp1: hit1_en_b(1) <= not( hit1 and cached_enable) ; + u_hit1_a2_cp2: hit1_en_b(2) <= not( hit1 and cached_enable) ; + u_hit1_a2_cp3: hit1_en_b(3) <= not( hit1 and cached_enable) ; + + u_hit2_a2_cp0: hit2_en_b(0) <= not( hit2 and cached_enable) ; + u_hit2_a2_cp1: hit2_en_b(1) <= not( hit2 and cached_enable) ; + u_hit2_a2_cp2: hit2_en_b(2) <= not( hit2 and cached_enable) ; + u_hit2_a2_cp3: hit2_en_b(3) <= not( hit2 and cached_enable) ; + + u_hit3_a2_cp0: hit3_en_b(0) <= not( hit3 and cached_enable) ; + u_hit3_a2_cp1: hit3_en_b(1) <= not( hit3 and cached_enable) ; + u_hit3_a2_cp2: hit3_en_b(2) <= not( hit3 and cached_enable) ; + u_hit3_a2_cp3: hit3_en_b(3) <= not( hit3 and cached_enable) ; + + + u_hit0_i2_cp0: hit0_en(0) <= not( hit0_en_b(0) ) ; + u_hit0_i2_cp1: hit0_en(1) <= not( hit0_en_b(0) ) ; + u_hit0_i2_cp2: hit0_en(2) <= not( hit0_en_b(1) ) ; + u_hit0_i2_cp3: hit0_en(3) <= not( hit0_en_b(1) ) ; + u_hit0_i2_cp4: hit0_en(4) <= not( hit0_en_b(2) ) ; + u_hit0_i2_cp5: hit0_en(5) <= not( hit0_en_b(2) ) ; + u_hit0_i2_cp6: hit0_en(6) <= not( hit0_en_b(3) ) ; + u_hit0_i2_cp7: hit0_en(7) <= not( hit0_en_b(3) ) ; + + u_hit1_i2_cp0: hit1_en(0) <= not( hit1_en_b(0) ) ; + u_hit1_i2_cp1: hit1_en(1) <= not( hit1_en_b(0) ) ; + u_hit1_i2_cp2: hit1_en(2) <= not( hit1_en_b(1) ) ; + u_hit1_i2_cp3: hit1_en(3) <= not( hit1_en_b(1) ) ; + u_hit1_i2_cp4: hit1_en(4) <= not( hit1_en_b(2) ) ; + u_hit1_i2_cp5: hit1_en(5) <= not( hit1_en_b(2) ) ; + u_hit1_i2_cp6: hit1_en(6) <= not( hit1_en_b(3) ) ; + u_hit1_i2_cp7: hit1_en(7) <= not( hit1_en_b(3) ) ; + + u_hit2_i2_cp0: hit2_en(0) <= not( hit2_en_b(0) ) ; + u_hit2_i2_cp1: hit2_en(1) <= not( hit2_en_b(0) ) ; + u_hit2_i2_cp2: hit2_en(2) <= not( hit2_en_b(1) ) ; + u_hit2_i2_cp3: hit2_en(3) <= not( hit2_en_b(1) ) ; + u_hit2_i2_cp4: hit2_en(4) <= not( hit2_en_b(2) ) ; + u_hit2_i2_cp5: hit2_en(5) <= not( hit2_en_b(2) ) ; + u_hit2_i2_cp6: hit2_en(6) <= not( hit2_en_b(3) ) ; + u_hit2_i2_cp7: hit2_en(7) <= not( hit2_en_b(3) ) ; + + u_hit3_i2_cp0: hit3_en(0) <= not( hit3_en_b(0) ) ; + u_hit3_i2_cp1: hit3_en(1) <= not( hit3_en_b(0) ) ; + u_hit3_i2_cp2: hit3_en(2) <= not( hit3_en_b(1) ) ; + u_hit3_i2_cp3: hit3_en(3) <= not( hit3_en_b(1) ) ; + u_hit3_i2_cp4: hit3_en(4) <= not( hit3_en_b(2) ) ; + u_hit3_i2_cp5: hit3_en(5) <= not( hit3_en_b(2) ) ; + u_hit3_i2_cp6: hit3_en(6) <= not( hit3_en_b(3) ) ; + u_hit3_i2_cp7: hit3_en(7) <= not( hit3_en_b(3) ) ; + + + + + hit0_en0( 0 to 17) <= ( 0 to 17 => hit0_en(0) ); + hit0_en0(18 to 35) <= (18 to 35 => hit0_en(1) ); + hit0_en1( 0 to 17) <= ( 0 to 17 => hit0_en(2) ); + hit0_en1(18 to 35) <= (18 to 35 => hit0_en(3) ); + hit0_en2( 0 to 17) <= ( 0 to 17 => hit0_en(4) ); + hit0_en2(18 to 35) <= (18 to 35 => hit0_en(5) ); + hit0_en3( 0 to 17) <= ( 0 to 17 => hit0_en(6) ); + hit0_en3(18 to 35) <= (18 to 35 => hit0_en(7) ); + + hit1_en0( 0 to 17) <= ( 0 to 17 => hit1_en(0) ); + hit1_en0(18 to 35) <= (18 to 35 => hit1_en(1) ); + hit1_en1( 0 to 17) <= ( 0 to 17 => hit1_en(2) ); + hit1_en1(18 to 35) <= (18 to 35 => hit1_en(3) ); + hit1_en2( 0 to 17) <= ( 0 to 17 => hit1_en(4) ); + hit1_en2(18 to 35) <= (18 to 35 => hit1_en(5) ); + hit1_en3( 0 to 17) <= ( 0 to 17 => hit1_en(6) ); + hit1_en3(18 to 35) <= (18 to 35 => hit1_en(7) ); + + hit2_en0( 0 to 17) <= ( 0 to 17 => hit2_en(0) ); + hit2_en0(18 to 35) <= (18 to 35 => hit2_en(1) ); + hit2_en1( 0 to 17) <= ( 0 to 17 => hit2_en(2) ); + hit2_en1(18 to 35) <= (18 to 35 => hit2_en(3) ); + hit2_en2( 0 to 17) <= ( 0 to 17 => hit2_en(4) ); + hit2_en2(18 to 35) <= (18 to 35 => hit2_en(5) ); + hit2_en3( 0 to 17) <= ( 0 to 17 => hit2_en(6) ); + hit2_en3(18 to 35) <= (18 to 35 => hit2_en(7) ); + + hit3_en0( 0 to 17) <= ( 0 to 17 => hit3_en(0) ); + hit3_en0(18 to 35) <= (18 to 35 => hit3_en(1) ); + hit3_en1( 0 to 17) <= ( 0 to 17 => hit3_en(2) ); + hit3_en1(18 to 35) <= (18 to 35 => hit3_en(3) ); + hit3_en2( 0 to 17) <= ( 0 to 17 => hit3_en(4) ); + hit3_en2(18 to 35) <= (18 to 35 => hit3_en(5) ); + hit3_en3( 0 to 17) <= ( 0 to 17 => hit3_en(6) ); + hit3_en3(18 to 35) <= (18 to 35 => hit3_en(7) ); + + + + + u_iu3_instr0_dx0: iu3_instr0_dx0_b( 0 to 35) <= not( hit0_en0(0 to 35) and iu2_data_dataout_0( 0 to 35) ) ; + u_iu3_instr0_dx1: iu3_instr0_dx1_b( 0 to 35) <= not( hit1_en0(0 to 35) and iu2_data_dataout_1( 0 to 35) ) ; + u_iu3_instr0_dx2: iu3_instr0_dx2_b( 0 to 35) <= not( hit2_en0(0 to 35) and iu2_data_dataout_2( 0 to 35) ) ; + u_iu3_instr0_dx3: iu3_instr0_dx3_b( 0 to 35) <= not( hit3_en0(0 to 35) and iu2_data_dataout_3( 0 to 35) ) ; + + u_iu3_instr1_dx0: iu3_instr1_dx0_b( 0 to 35) <= not( hit0_en1(0 to 35) and iu2_data_dataout_0( 36 to 71) ) ; + u_iu3_instr1_dx1: iu3_instr1_dx1_b( 0 to 35) <= not( hit1_en1(0 to 35) and iu2_data_dataout_1( 36 to 71) ) ; + u_iu3_instr1_dx2: iu3_instr1_dx2_b( 0 to 35) <= not( hit2_en1(0 to 35) and iu2_data_dataout_2( 36 to 71) ) ; + u_iu3_instr1_dx3: iu3_instr1_dx3_b( 0 to 35) <= not( hit3_en1(0 to 35) and iu2_data_dataout_3( 36 to 71) ) ; + + u_iu3_instr2_dx0: iu3_instr2_dx0_b( 0 to 35) <= not( hit0_en2(0 to 35) and iu2_data_dataout_0( 72 to 107) ) ; + u_iu3_instr2_dx1: iu3_instr2_dx1_b( 0 to 35) <= not( hit1_en2(0 to 35) and iu2_data_dataout_1( 72 to 107) ) ; + u_iu3_instr2_dx2: iu3_instr2_dx2_b( 0 to 35) <= not( hit2_en2(0 to 35) and iu2_data_dataout_2( 72 to 107) ) ; + u_iu3_instr2_dx3: iu3_instr2_dx3_b( 0 to 35) <= not( hit3_en2(0 to 35) and iu2_data_dataout_3( 72 to 107) ) ; + + u_iu3_instr3_dx0: iu3_instr3_dx0_b( 0 to 35) <= not( hit0_en3(0 to 35) and iu2_data_dataout_0(108 to 143) ) ; + u_iu3_instr3_dx1: iu3_instr3_dx1_b( 0 to 35) <= not( hit1_en3(0 to 35) and iu2_data_dataout_1(108 to 143) ) ; + u_iu3_instr3_dx2: iu3_instr3_dx2_b( 0 to 35) <= not( hit2_en3(0 to 35) and iu2_data_dataout_2(108 to 143) ) ; + u_iu3_instr3_dx3: iu3_instr3_dx3_b( 0 to 35) <= not( hit3_en3(0 to 35) and iu2_data_dataout_3(108 to 143) ) ; + + + + u_iu3_instr0_d1: iu3_instr0_d1(0 to 35) <= not( iu3_instr0_dx0_b(0 to 35) and iu3_instr0_dx1_b(0 to 35) and iu3_instr0_oth_b(0 to 35) ); + u_iu3_instr0_d2: iu3_instr0_d2(0 to 35) <= not( iu3_instr0_dx2_b(0 to 35) and iu3_instr0_dx3_b(0 to 35) ); + + u_iu3_instr1_d1: iu3_instr1_d1(0 to 35) <= not( iu3_instr1_dx0_b(0 to 35) and iu3_instr1_dx1_b(0 to 35) and iu3_instr1_oth_b(0 to 35) ); + u_iu3_instr1_d2: iu3_instr1_d2(0 to 35) <= not( iu3_instr1_dx2_b(0 to 35) and iu3_instr1_dx3_b(0 to 35) ); + + u_iu3_instr2_d1: iu3_instr2_d1(0 to 35) <= not( iu3_instr2_dx0_b(0 to 35) and iu3_instr2_dx1_b(0 to 35) and iu3_instr2_oth_b(0 to 35) ); + u_iu3_instr2_d2: iu3_instr2_d2(0 to 35) <= not( iu3_instr2_dx2_b(0 to 35) and iu3_instr2_dx3_b(0 to 35) ); + + u_iu3_instr3_d1: iu3_instr3_d1(0 to 35) <= not( iu3_instr3_dx0_b(0 to 35) and iu3_instr3_dx1_b(0 to 35) and iu3_instr3_oth_b(0 to 35) ); + u_iu3_instr3_d2: iu3_instr3_d2(0 to 35) <= not( iu3_instr3_dx2_b(0 to 35) and iu3_instr3_dx3_b(0 to 35) ); + + + + + iu3_instr0_oth_b(0 to 35) <= not( + icm_icd_reload_data( 0 to 35) and (0 to 35=> load_iu2 ) ); + + iu3_instr1_oth_b(0 to 35) <= not( + icm_icd_reload_data( 36 to 71) and (0 to 35=> load_iu2 ) ); + + iu3_instr2_oth_b(0 to 35) <= not( + icm_icd_reload_data( 72 to 107) and (0 to 35=> load_iu2 ) ); + + iu3_instr3_oth_b(0 to 35) <= not( + icm_icd_reload_data(108 to 143) and (0 to 35=> load_iu2 ) ); + + + + + iu3_instr0_lat: entity tri.tri_nor2_nlats generic map (width => 36, btr=> "NLO0001_X2_A12TH", needs_sreset => 0, expand_type => expand_type) port map ( + VD => vdd , + GD => gnd , + LCLK => inslat_lclk , + D1CLK => inslat_d1clk , + D2CLK => inslat_d2clk , + SCANIN => iu3_instr0_si , + SCANOUT => iu3_instr0_so , + A1 => iu3_instr0_d1 (0 to 35) , + A2 => iu3_instr0_d2 (0 to 35) , + QB => iu3_instr0_l2_b(0 to 35) ); + + iu3_instr1_lat: entity tri.tri_nor2_nlats generic map (width => 36, btr=> "NLO0001_X2_A12TH", needs_sreset => 0, expand_type => expand_type) port map ( + VD => vdd , + GD => gnd , + LCLK => inslat_lclk , + D1CLK => inslat_d1clk , + D2CLK => inslat_d2clk , + SCANIN => iu3_instr1_si , + SCANOUT => iu3_instr1_so , + A1 => iu3_instr1_d1 (0 to 35) , + A2 => iu3_instr1_d2 (0 to 35) , + QB => iu3_instr1_l2_b(0 to 35) ); + + iu3_instr2_lat: entity tri.tri_nor2_nlats generic map (width => 36, btr=> "NLO0001_X2_A12TH", needs_sreset => 0, expand_type => expand_type) port map ( + VD => vdd , + GD => gnd , + LCLK => inslat_lclk , + D1CLK => inslat_d1clk , + D2CLK => inslat_d2clk , + SCANIN => iu3_instr2_si , + SCANOUT => iu3_instr2_so , + A1 => iu3_instr2_d1 (0 to 35) , + A2 => iu3_instr2_d2 (0 to 35) , + QB => iu3_instr2_l2_b(0 to 35) ); + + iu3_instr3_lat: entity tri.tri_nor2_nlats generic map (width => 36, btr=> "NLO0001_X2_A12TH", needs_sreset => 0, expand_type => expand_type) port map ( + VD => vdd , + GD => gnd , + LCLK => inslat_lclk , + D1CLK => inslat_d1clk , + D2CLK => inslat_d2clk , + SCANIN => iu3_instr3_si , + SCANOUT => iu3_instr3_so , + A1 => iu3_instr3_d1 (0 to 35) , + A2 => iu3_instr3_d2 (0 to 35) , + QB => iu3_instr3_l2_b(0 to 35) ); + + + u_iu3_instr0_inv: iu3_instr0_buf <= not( iu3_instr0_l2_b ); + u_iu3_instr1_inv: iu3_instr1_buf <= not( iu3_instr1_l2_b ); + u_iu3_instr2_inv: iu3_instr2_buf <= not( iu3_instr2_l2_b ); + u_iu3_instr3_inv: iu3_instr3_buf <= not( iu3_instr3_l2_b ); + + + + + iu3_instr0_si(0 to 35) <= scan_in & iu3_instr0_so(0 to 34); + iu3_instr1_si(0 to 35) <= iu3_instr1_so(1 to 35) & iu3_instr0_so(35); + iu3_instr2_si(0 to 35) <= iu3_instr1_so(0) & iu3_instr2_so(0 to 34) ; + iu3_instr3_si(0 to 35) <= iu3_instr3_so(1 to 35) & iu3_instr2_so(35) ; + scan_out <= iu3_instr3_so(0) ; + + + inslat_lcb : tri_lcbnd generic map (expand_type => expand_type) port map( + nclk => nclk , + vd => vdd , + gd => gnd , + act => inslat_act , + delay_lclkr => delay_lclkr , + mpw1_b => mpw1_b , + mpw2_b => mpw2_b , + forcee => forcee, + sg => sg_0 , + thold_b => thold_0_b , + d1clk => inslat_d1clk , + d2clk => inslat_d2clk , + lclk => inslat_lclk ); + + + + +end; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_ic_miss.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_ic_miss.vhdl new file mode 100644 index 0000000..51ec633 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_ic_miss.vhdl @@ -0,0 +1,4219 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee,ibm,support,tri,work; +use ieee.std_logic_1164.all; +use ibm.std_ulogic_unsigned.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use support.power_logic_pkg.all; +use tri.tri_latches_pkg.all; +use work.iuq_pkg.all; +entity iuq_ic_miss is + generic(expand_type : integer := 2); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + pc_iu_func_sl_thold_0_b : in std_ulogic; + pc_iu_sg_0 : in std_ulogic; + forcee : in std_ulogic; + d_mode : in std_ulogic; + delay_lclkr : in std_ulogic; + mpw1_b : in std_ulogic; + mpw2_b : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + xu_iu_flush : in std_ulogic_vector(0 to 3); + bp_ic_iu5_redirect_tid : in std_ulogic_vector(0 to 3); + + ics_icm_iu0_ifar0 : in std_ulogic_vector(46 to 52); + ics_icm_iu0_ifar1 : in std_ulogic_vector(46 to 52); + ics_icm_iu0_ifar2 : in std_ulogic_vector(46 to 52); + ics_icm_iu0_ifar3 : in std_ulogic_vector(46 to 52); + + ics_icm_iu0_inval : in std_ulogic; + ics_icm_iu0_inval_addr : in std_ulogic_vector(52 to 57); + + ics_icm_iu2_flush_tid : in std_ulogic_vector(0 to 3); + ics_icm_iu3_flush_tid : in std_ulogic_vector(0 to 3); + icm_ics_hold_thread : out std_ulogic_vector(0 to 3); + icm_ics_hold_thread_dbg : out std_ulogic_vector(0 to 3); + icm_ics_hold_iu0 : out std_ulogic; + icm_ics_ecc_block_iu0 : out std_ulogic_vector(0 to 3); + icm_ics_load_tid : out std_ulogic_vector(0 to 3); + icm_ics_iu1_ecc_flush : out std_ulogic; + icm_ics_iu2_miss_match_prev : out std_ulogic; + + icm_ics_iu0_preload_val : out std_ulogic; + icm_ics_iu0_preload_tid : out std_ulogic_vector(0 to 3); + icm_ics_iu0_preload_ifar : out std_ulogic_vector(52 to 59); + + icm_icd_lru_addr : out std_ulogic_vector(52 to 57); + icm_icd_dir_inval : out std_ulogic; + icm_icd_dir_val : out std_ulogic; + icm_icd_data_write : out std_ulogic; + icm_icd_reload_addr : out std_ulogic_vector(52 to 59); + icm_icd_reload_data : out std_ulogic_vector(0 to 161); + icm_icd_reload_way : out std_ulogic_vector(0 to 3); + icm_icd_load_tid : out std_ulogic_vector(0 to 3); + icm_icd_load_addr : out EFF_IFAR; + icm_icd_load_2ucode : out std_ulogic; + icm_icd_load_2ucode_type : out std_ulogic; + icm_icd_dir_write : out std_ulogic; + icm_icd_dir_write_addr : out std_ulogic_vector(REAL_IFAR'left to 57); + icm_icd_dir_write_endian : out std_ulogic; + icm_icd_dir_write_way : out std_ulogic_vector(0 to 3); + icm_icd_lru_write : out std_ulogic; + icm_icd_lru_write_addr : out std_ulogic_vector(52 to 57); + icm_icd_lru_write_way : out std_ulogic_vector(0 to 3); + icm_icd_ecc_inval : out std_ulogic; + icm_icd_ecc_addr : out std_ulogic_vector(52 to 57); + icm_icd_ecc_way : out std_ulogic_vector(0 to 3); + icm_icd_iu3_ecc_fp_cancel : out std_ulogic; + icm_icd_iu3_ecc_err : out std_ulogic; + icm_icd_any_reld_r2 : out std_ulogic; + icm_icd_any_checkecc : out std_ulogic; + + icd_icm_miss : in std_ulogic; + icd_icm_tid : in std_ulogic_vector(0 to 3); + icd_icm_addr_real : in REAL_IFAR; + icd_icm_addr_eff : in std_ulogic_vector(EFF_IFAR'left to 51); + icd_icm_wimge : in std_ulogic_vector(0 to 4); + icd_icm_userdef : in std_ulogic_vector(0 to 3); + icd_icm_2ucode : in std_ulogic; + icd_icm_2ucode_type : in std_ulogic; + icd_icm_iu3_erat_err : in std_ulogic; + icd_icm_iu2_inval : in std_ulogic; + icd_icm_ici : in std_ulogic; + icd_icm_any_iu2_valid : in std_ulogic; + + icd_icm_row_lru : in std_ulogic_vector(0 to 2); + icd_icm_row_val : in std_ulogic_vector(0 to 3); + + ic_fdep_load_quiesce : out std_ulogic_vector(0 to 3); + + iu_mm_lmq_empty : out std_ulogic; + + ic_perf_event_t0 : out std_ulogic_vector(0 to 1); + ic_perf_event_t1 : out std_ulogic_vector(0 to 1); + ic_perf_event_t2 : out std_ulogic_vector(0 to 1); + ic_perf_event_t3 : out std_ulogic_vector(0 to 1); + + an_ac_reld_data_vld : in std_ulogic; + an_ac_reld_core_tag : in std_ulogic_vector(0 to 4); + an_ac_reld_qw : in std_ulogic_vector(57 to 59); + an_ac_reld_data : in std_ulogic_vector(0 to 127); + an_ac_reld_ecc_err : in std_ulogic; + an_ac_reld_ecc_err_ue : in std_ulogic; + + spr_ic_cls : in std_ulogic; + spr_ic_clockgate_dis : in std_ulogic; + spr_ic_bp_config : in std_ulogic_vector(0 to 3); + + iu_xu_request : out std_ulogic; + iu_xu_thread : out std_ulogic_vector(0 to 3); + iu_xu_ra : out std_ulogic_vector(REAL_IFAR'left to 59); + iu_xu_wimge : out std_ulogic_vector(0 to 4); + iu_xu_userdef : out std_ulogic_vector(0 to 3); + + event_bus_enable : in std_ulogic; + trace_bus_enable : in std_ulogic; + miss_dbg_data0 : out std_ulogic_vector(0 to 87); + miss_dbg_data1 : out std_ulogic_vector(0 to 87); + miss_dbg_data2 : out std_ulogic_vector(0 to 43); + miss_dbg_trigger : out std_ulogic_vector(0 to 11) +); +-- synopsys translate_off +-- synopsys translate_on +end iuq_ic_miss; +ARCHITECTURE IUQ_IC_MISS + OF IUQ_IC_MISS + IS +SIGNAL IU2_SM_0_PT : STD_ULOGIC_VECTOR(1 TO 49) := +(OTHERS=> 'U'); +SIGNAL IU2_SM_1_PT : STD_ULOGIC_VECTOR(1 TO 49) := +(OTHERS=> 'U'); +SIGNAL IU2_SM_2_PT : STD_ULOGIC_VECTOR(1 TO 49) := +(OTHERS=> 'U'); +SIGNAL IU2_SM_3_PT : STD_ULOGIC_VECTOR(1 TO 49) := +(OTHERS=> 'U'); +SIGNAL SELECT_LRU_WAY_PT : STD_ULOGIC_VECTOR(1 TO 24) := +(OTHERS=> 'U'); +component iuq_bd is +port( + instruction : in std_ulogic_vector(0 to 31); + branch_decode : out std_ulogic_vector(0 to 3); + + bp_bc_en : in std_ulogic; + bp_bclr_en : in std_ulogic; + bp_bcctr_en : in std_ulogic; + bp_sw_en : in std_ulogic +); +end component; +constant spr_ic_cls_offset : natural := 0; +constant bp_config_offset : natural := spr_ic_cls_offset + 1; +constant spare_offset : natural := bp_config_offset + 4; +constant an_ac_reld_data_vld_offset : natural := spare_offset + 16; +constant an_ac_reld_core_tag_offset : natural := an_ac_reld_data_vld_offset + 1; +constant an_ac_reld_qw_offset : natural := an_ac_reld_core_tag_offset + 5; +constant an_ac_reld_data_offset : natural := an_ac_reld_qw_offset + 3; +constant an_ac_reld_ecc_err_offset : natural := an_ac_reld_data_offset + 128; +constant an_ac_reld_ecc_err_ue_offset : natural := an_ac_reld_ecc_err_offset + 1; +constant reld_r1_tid_offset : natural := an_ac_reld_ecc_err_ue_offset + 1; +constant reld_r1_qw_offset : natural := reld_r1_tid_offset + 4; +constant reld_r2_tid_offset : natural := reld_r1_qw_offset + 3; +constant reld_r2_qw_offset : natural := reld_r2_tid_offset + 4; +constant r2_crit_qw_offset : natural := reld_r2_qw_offset + 3; +constant reld_r3_tid_offset : natural := r2_crit_qw_offset + 1; +constant r3_loaded_offset : natural := reld_r3_tid_offset + 4; +constant r3_need_back_inval_offset : natural := r3_loaded_offset + 1; +constant row_lru_offset : natural := r3_need_back_inval_offset + 1; +constant row_val_offset : natural := row_lru_offset + 3; +constant request_offset : natural := row_val_offset + 4; +constant req_thread_offset : natural := request_offset + 1; +constant req_ra_offset : natural := req_thread_offset + 4; +constant req_wimge_offset : natural := req_ra_offset + 60-REAL_IFAR'left; +constant req_userdef_offset : natural := req_wimge_offset + 5; +constant iu3_miss_match_offset : natural := req_userdef_offset + 4; +constant miss_tid0_sm_offset : natural := iu3_miss_match_offset + 1; +constant miss_flush_occurred0_offset : natural := miss_tid0_sm_offset + 20; +constant miss_flushed0_offset : natural := miss_flush_occurred0_offset + 1; +constant miss_inval0_offset : natural := miss_flushed0_offset + 1; +constant miss_block_fp0_offset : natural := miss_inval0_offset + 1; +constant miss_ecc_err0_offset : natural := miss_block_fp0_offset + 1; +constant miss_ecc_err_ue0_offset : natural := miss_ecc_err0_offset + 1; +constant miss_wrote_dir0_offset : natural := miss_ecc_err_ue0_offset + 1; +constant miss_need_hold0_offset : natural := miss_wrote_dir0_offset + 1; +constant miss_addr0_real_offset : natural := miss_need_hold0_offset + 1; +constant miss_addr0_eff_offset : natural := miss_addr0_real_offset + REAL_IFAR'length; +constant miss_ci0_offset : natural := miss_addr0_eff_offset + EFF_IFAR'length - 10; +constant miss_endian0_offset : natural := miss_ci0_offset + 1; +constant miss_2ucode0_offset : natural := miss_endian0_offset + 1; +constant miss_2ucode0_type_offset : natural := miss_2ucode0_offset + 1; +constant miss_way0_offset : natural := miss_2ucode0_type_offset + 1; +constant perf_event_t0_offset : natural := miss_way0_offset + 4; +constant miss_tid1_sm_offset : natural := perf_event_t0_offset + 2; +constant miss_flush_occurred1_offset : natural := miss_tid1_sm_offset + 20; +constant miss_flushed1_offset : natural := miss_flush_occurred1_offset + 1; +constant miss_inval1_offset : natural := miss_flushed1_offset + 1; +constant miss_block_fp1_offset : natural := miss_inval1_offset + 1; +constant miss_ecc_err1_offset : natural := miss_block_fp1_offset + 1; +constant miss_ecc_err_ue1_offset : natural := miss_ecc_err1_offset + 1; +constant miss_wrote_dir1_offset : natural := miss_ecc_err_ue1_offset + 1; +constant miss_need_hold1_offset : natural := miss_wrote_dir1_offset + 1; +constant miss_addr1_real_offset : natural := miss_need_hold1_offset + 1; +constant miss_addr1_eff_offset : natural := miss_addr1_real_offset + REAL_IFAR'length; +constant miss_ci1_offset : natural := miss_addr1_eff_offset + EFF_IFAR'length - 10; +constant miss_endian1_offset : natural := miss_ci1_offset + 1; +constant miss_2ucode1_offset : natural := miss_endian1_offset + 1; +constant miss_2ucode1_type_offset : natural := miss_2ucode1_offset + 1; +constant miss_way1_offset : natural := miss_2ucode1_type_offset + 1; +constant perf_event_t1_offset : natural := miss_way1_offset + 4; +constant miss_tid2_sm_offset : natural := perf_event_t1_offset + 2; +constant miss_flush_occurred2_offset : natural := miss_tid2_sm_offset + 20; +constant miss_flushed2_offset : natural := miss_flush_occurred2_offset + 1; +constant miss_inval2_offset : natural := miss_flushed2_offset + 1; +constant miss_block_fp2_offset : natural := miss_inval2_offset + 1; +constant miss_ecc_err2_offset : natural := miss_block_fp2_offset + 1; +constant miss_ecc_err_ue2_offset : natural := miss_ecc_err2_offset + 1; +constant miss_wrote_dir2_offset : natural := miss_ecc_err_ue2_offset + 1; +constant miss_need_hold2_offset : natural := miss_wrote_dir2_offset + 1; +constant miss_addr2_real_offset : natural := miss_need_hold2_offset + 1; +constant miss_addr2_eff_offset : natural := miss_addr2_real_offset + REAL_IFAR'length; +constant miss_ci2_offset : natural := miss_addr2_eff_offset + EFF_IFAR'length - 10; +constant miss_endian2_offset : natural := miss_ci2_offset + 1; +constant miss_2ucode2_offset : natural := miss_endian2_offset + 1; +constant miss_2ucode2_type_offset : natural := miss_2ucode2_offset + 1; +constant miss_way2_offset : natural := miss_2ucode2_type_offset + 1; +constant perf_event_t2_offset : natural := miss_way2_offset + 4; +constant miss_tid3_sm_offset : natural := perf_event_t2_offset + 2; +constant miss_flush_occurred3_offset : natural := miss_tid3_sm_offset + 20; +constant miss_flushed3_offset : natural := miss_flush_occurred3_offset + 1; +constant miss_inval3_offset : natural := miss_flushed3_offset + 1; +constant miss_block_fp3_offset : natural := miss_inval3_offset + 1; +constant miss_ecc_err3_offset : natural := miss_block_fp3_offset + 1; +constant miss_ecc_err_ue3_offset : natural := miss_ecc_err3_offset + 1; +constant miss_wrote_dir3_offset : natural := miss_ecc_err_ue3_offset + 1; +constant miss_need_hold3_offset : natural := miss_wrote_dir3_offset + 1; +constant miss_addr3_real_offset : natural := miss_need_hold3_offset + 1; +constant miss_addr3_eff_offset : natural := miss_addr3_real_offset + REAL_IFAR'length; +constant miss_ci3_offset : natural := miss_addr3_eff_offset + EFF_IFAR'length - 10; +constant miss_endian3_offset : natural := miss_ci3_offset + 1; +constant miss_2ucode3_offset : natural := miss_endian3_offset + 1; +constant miss_2ucode3_type_offset : natural := miss_2ucode3_offset + 1; +constant miss_way3_offset : natural := miss_2ucode3_type_offset + 1; +constant perf_event_t3_offset : natural := miss_way3_offset + 4; +constant lru_write_next_cycle_offset : natural := perf_event_t3_offset + 2; +constant lru_write_offset : natural := lru_write_next_cycle_offset + 4; +constant miss_dbg_data1_offset : natural := lru_write_offset + 4; +constant scan_right : natural := miss_dbg_data1_offset + 9 - 1; +subtype s2 is std_ulogic_vector(0 to 1); +subtype s5 is std_ulogic_vector(0 to 4); +signal spr_ic_cls_d : std_ulogic; +signal bp_config_d : std_ulogic_vector(0 to 3); +signal an_ac_reld_data_vld_d : std_ulogic; +signal an_ac_reld_core_tag_d : std_ulogic_vector(0 to 4); +signal an_ac_reld_qw_d : std_ulogic_vector(57 to 59); +signal an_ac_reld_data_d : std_ulogic_vector(0 to 127); +signal an_ac_reld_ecc_err_d : std_ulogic; +signal an_ac_reld_ecc_err_ue_d : std_ulogic; +signal reld_r1_tid_d : std_ulogic_vector(0 to 3); +signal reld_r1_qw_d : std_ulogic_vector(0 to 2); +signal reld_r2_tid_d : std_ulogic_vector(0 to 3); +signal reld_r2_qw_d : std_ulogic_vector(0 to 2); +signal r2_crit_qw_d : std_ulogic; +signal reld_r3_tid_d : std_ulogic_vector(0 to 3); +signal r3_loaded_d : std_ulogic; +signal r3_need_back_inval_d : std_ulogic; +signal row_lru_d : std_ulogic_vector(0 to 2); +signal row_val_d : std_ulogic_vector(0 to 3); +signal request_d : std_ulogic; +signal req_thread_d : std_ulogic_vector(0 to 3); +signal req_ra_d : std_ulogic_vector(REAL_IFAR'left to 59); +signal req_wimge_d : std_ulogic_vector(0 to 4); +signal req_userdef_d : std_ulogic_vector(0 to 3); +signal iu3_miss_match_d : std_ulogic; +signal miss_tid0_sm_d : std_ulogic_vector(0 to 19); +signal miss_flush_occurred0_d : std_ulogic; +signal miss_flushed0_d : std_ulogic; +signal miss_inval0_d : std_ulogic; +signal miss_block_fp0_d : std_ulogic; +signal miss_ecc_err0_d : std_ulogic; +signal miss_ecc_err_ue0_d : std_ulogic; +signal miss_wrote_dir0_d : std_ulogic; +signal miss_need_hold0_d : std_ulogic; +signal miss_addr0_real_d : REAL_IFAR; +signal miss_addr0_eff_d : std_ulogic_vector(EFF_IFAR'left to 51); +signal miss_ci0_d : std_ulogic; +signal miss_endian0_d : std_ulogic; +signal miss_2ucode0_d : std_ulogic; +signal miss_2ucode0_type_d : std_ulogic; +signal miss_way0_d : std_ulogic_vector(0 to 3); +signal perf_event_t0_d : std_ulogic_vector(0 to 1); +signal miss_tid1_sm_d : std_ulogic_vector(0 to 19); +signal miss_flush_occurred1_d : std_ulogic; +signal miss_flushed1_d : std_ulogic; +signal miss_inval1_d : std_ulogic; +signal miss_block_fp1_d : std_ulogic; +signal miss_ecc_err1_d : std_ulogic; +signal miss_ecc_err_ue1_d : std_ulogic; +signal miss_wrote_dir1_d : std_ulogic; +signal miss_need_hold1_d : std_ulogic; +signal miss_addr1_real_d : REAL_IFAR; +signal miss_addr1_eff_d : std_ulogic_vector(EFF_IFAR'left to 51); +signal miss_ci1_d : std_ulogic; +signal miss_endian1_d : std_ulogic; +signal miss_2ucode1_d : std_ulogic; +signal miss_2ucode1_type_d : std_ulogic; +signal miss_way1_d : std_ulogic_vector(0 to 3); +signal perf_event_t1_d : std_ulogic_vector(0 to 1); +signal miss_tid2_sm_d : std_ulogic_vector(0 to 19); +signal miss_flush_occurred2_d : std_ulogic; +signal miss_flushed2_d : std_ulogic; +signal miss_inval2_d : std_ulogic; +signal miss_block_fp2_d : std_ulogic; +signal miss_ecc_err2_d : std_ulogic; +signal miss_ecc_err_ue2_d : std_ulogic; +signal miss_wrote_dir2_d : std_ulogic; +signal miss_need_hold2_d : std_ulogic; +signal miss_addr2_real_d : REAL_IFAR; +signal miss_addr2_eff_d : std_ulogic_vector(EFF_IFAR'left to 51); +signal miss_ci2_d : std_ulogic; +signal miss_endian2_d : std_ulogic; +signal miss_2ucode2_d : std_ulogic; +signal miss_2ucode2_type_d : std_ulogic; +signal miss_way2_d : std_ulogic_vector(0 to 3); +signal perf_event_t2_d : std_ulogic_vector(0 to 1); +signal miss_tid3_sm_d : std_ulogic_vector(0 to 19); +signal miss_flush_occurred3_d : std_ulogic; +signal miss_flushed3_d : std_ulogic; +signal miss_inval3_d : std_ulogic; +signal miss_block_fp3_d : std_ulogic; +signal miss_ecc_err3_d : std_ulogic; +signal miss_ecc_err_ue3_d : std_ulogic; +signal miss_wrote_dir3_d : std_ulogic; +signal miss_need_hold3_d : std_ulogic; +signal miss_addr3_real_d : REAL_IFAR; +signal miss_addr3_eff_d : std_ulogic_vector(EFF_IFAR'left to 51); +signal miss_ci3_d : std_ulogic; +signal miss_endian3_d : std_ulogic; +signal miss_2ucode3_d : std_ulogic; +signal miss_2ucode3_type_d : std_ulogic; +signal miss_way3_d : std_ulogic_vector(0 to 3); +signal perf_event_t3_d : std_ulogic_vector(0 to 1); +signal lru_write_next_cycle_d : std_ulogic_vector(0 to 3); +signal lru_write_d : std_ulogic_vector(0 to 3); +signal spr_ic_cls_l2 : std_ulogic; +signal bp_config_l2 : std_ulogic_vector(0 to 3); +signal an_ac_reld_data_vld_l2 : std_ulogic; +signal an_ac_reld_core_tag_l2 : std_ulogic_vector(0 to 4); +signal an_ac_reld_qw_l2 : std_ulogic_vector(57 to 59); +signal an_ac_reld_data_l2 : std_ulogic_vector(0 to 127); +signal an_ac_reld_ecc_err_l2 : std_ulogic; +signal an_ac_reld_ecc_err_ue_l2 : std_ulogic; +signal reld_r1_tid_l2 : std_ulogic_vector(0 to 3); +signal reld_r1_qw_l2 : std_ulogic_vector(0 to 2); +signal reld_r2_tid_l2 : std_ulogic_vector(0 to 3); +signal reld_r2_qw_l2 : std_ulogic_vector(0 to 2); +signal r2_crit_qw_l2 : std_ulogic; +signal reld_r3_tid_l2 : std_ulogic_vector(0 to 3); +signal r3_loaded_l2 : std_ulogic; +signal r3_need_back_inval_l2 : std_ulogic; +signal row_lru_l2 : std_ulogic_vector(0 to 2); +signal row_val_l2 : std_ulogic_vector(0 to 3); +signal request_l2 : std_ulogic; +signal req_thread_l2 : std_ulogic_vector(0 to 3); +signal req_ra_l2 : std_ulogic_vector(REAL_IFAR'left to 59); +signal req_wimge_l2 : std_ulogic_vector(0 to 4); +signal req_userdef_l2 : std_ulogic_vector(0 to 3); +signal iu3_miss_match_l2 : std_ulogic; +signal miss_tid0_sm_l2 : std_ulogic_vector(0 to 19); +signal miss_flush_occurred0_l2 : std_ulogic; +signal miss_flushed0_l2 : std_ulogic; +signal miss_inval0_l2 : std_ulogic; +signal miss_block_fp0_l2 : std_ulogic; +signal miss_ecc_err0_l2 : std_ulogic; +signal miss_ecc_err_ue0_l2 : std_ulogic; +signal miss_wrote_dir0_l2 : std_ulogic; +signal miss_need_hold0_l2 : std_ulogic; +signal miss_addr0_real_l2 : REAL_IFAR; +signal miss_addr0_eff_l2 : std_ulogic_vector(EFF_IFAR'left to 51); +signal miss_ci0_l2 : std_ulogic; +signal miss_endian0_l2 : std_ulogic; +signal miss_2ucode0_l2 : std_ulogic; +signal miss_2ucode0_type_l2 : std_ulogic; +signal miss_way0_l2 : std_ulogic_vector(0 to 3); +signal perf_event_t0_l2 : std_ulogic_vector(0 to 1); +signal miss_tid1_sm_l2 : std_ulogic_vector(0 to 19); +signal miss_flush_occurred1_l2 : std_ulogic; +signal miss_flushed1_l2 : std_ulogic; +signal miss_inval1_l2 : std_ulogic; +signal miss_block_fp1_l2 : std_ulogic; +signal miss_ecc_err1_l2 : std_ulogic; +signal miss_ecc_err_ue1_l2 : std_ulogic; +signal miss_wrote_dir1_l2 : std_ulogic; +signal miss_need_hold1_l2 : std_ulogic; +signal miss_addr1_real_l2 : REAL_IFAR; +signal miss_addr1_eff_l2 : std_ulogic_vector(EFF_IFAR'left to 51); +signal miss_ci1_l2 : std_ulogic; +signal miss_endian1_l2 : std_ulogic; +signal miss_2ucode1_l2 : std_ulogic; +signal miss_2ucode1_type_l2 : std_ulogic; +signal miss_way1_l2 : std_ulogic_vector(0 to 3); +signal perf_event_t1_l2 : std_ulogic_vector(0 to 1); +signal miss_tid2_sm_l2 : std_ulogic_vector(0 to 19); +signal miss_flush_occurred2_l2 : std_ulogic; +signal miss_flushed2_l2 : std_ulogic; +signal miss_inval2_l2 : std_ulogic; +signal miss_block_fp2_l2 : std_ulogic; +signal miss_ecc_err2_l2 : std_ulogic; +signal miss_ecc_err_ue2_l2 : std_ulogic; +signal miss_wrote_dir2_l2 : std_ulogic; +signal miss_need_hold2_l2 : std_ulogic; +signal miss_addr2_real_l2 : REAL_IFAR; +signal miss_addr2_eff_l2 : std_ulogic_vector(EFF_IFAR'left to 51); +signal miss_ci2_l2 : std_ulogic; +signal miss_endian2_l2 : std_ulogic; +signal miss_2ucode2_l2 : std_ulogic; +signal miss_2ucode2_type_l2 : std_ulogic; +signal miss_way2_l2 : std_ulogic_vector(0 to 3); +signal perf_event_t2_l2 : std_ulogic_vector(0 to 1); +signal miss_tid3_sm_l2 : std_ulogic_vector(0 to 19); +signal miss_flush_occurred3_l2 : std_ulogic; +signal miss_flushed3_l2 : std_ulogic; +signal miss_inval3_l2 : std_ulogic; +signal miss_block_fp3_l2 : std_ulogic; +signal miss_ecc_err3_l2 : std_ulogic; +signal miss_ecc_err_ue3_l2 : std_ulogic; +signal miss_wrote_dir3_l2 : std_ulogic; +signal miss_need_hold3_l2 : std_ulogic; +signal miss_addr3_real_l2 : REAL_IFAR; +signal miss_addr3_eff_l2 : std_ulogic_vector(EFF_IFAR'left to 51); +signal miss_ci3_l2 : std_ulogic; +signal miss_endian3_l2 : std_ulogic; +signal miss_2ucode3_l2 : std_ulogic; +signal miss_2ucode3_type_l2 : std_ulogic; +signal miss_way3_l2 : std_ulogic_vector(0 to 3); +signal perf_event_t3_l2 : std_ulogic_vector(0 to 1); +signal lru_write_next_cycle_l2 : std_ulogic_vector(0 to 3); +signal lru_write_l2 : std_ulogic_vector(0 to 3); +signal spare_l2 : std_ulogic_vector(0 to 15); +signal miss_dbg_data1_d : std_ulogic_vector(51 to 59); +signal miss_dbg_data1_l2 : std_ulogic_vector(51 to 59); +signal default_reld_act : std_ulogic; +signal reld_r2_act : std_ulogic; +signal miss_act : std_ulogic_vector(0 to 3); +signal reld_r0_vld : std_ulogic; +signal reld_r0_tid_plain: std_ulogic_vector(0 to 3); +signal reld_r1_vld : std_ulogic; +signal load_quiesce : std_ulogic_vector(0 to 3); +signal set_flush_occurred : std_ulogic_vector(0 to 3); +signal flush_addr_outside_range : std_ulogic_vector(0 to 3); +signal set_flushed : std_ulogic_vector(0 to 3); +signal inval_equal : std_ulogic_vector(0 to 3); +signal set_invalidated : std_ulogic_vector(0 to 3); +signal reset_state : std_ulogic_vector(0 to 3); +signal sent_fp : std_ulogic_vector(0 to 3); +signal set_block_fp : std_ulogic_vector(0 to 3); +signal addr_equal : std_ulogic_vector(0 to 3); +signal addr_match : std_ulogic; +signal miss_thread_is_idle : std_ulogic; +signal release_sm : std_ulogic; +signal release_sm_hold : std_ulogic_vector(0 to 3); +signal iu0_inval_match : std_ulogic_vector(0 to 3); +signal miss_wrote_dir_v : std_ulogic_vector(0 to 3); +signal request_tid : std_ulogic_vector(0 to 3); +signal erat_err : std_ulogic_vector(0 to 3); +signal preload_r0_tid : std_ulogic_vector(0 to 3); +signal preload_hold_iu0 : std_ulogic; +signal load_tid : std_ulogic_vector(0 to 3); +signal r2_load_addr : EFF_IFAR; +signal r2_load_2ucode : std_ulogic; +signal r2_load_2ucode_type : std_ulogic; +signal load_tid_no_block: std_ulogic_vector(0 to 3); +signal r0_crit_qw : std_ulogic_vector(0 to 3); +signal r1_crit_qw : std_ulogic_vector(0 to 3); +signal lru_write_hit : std_ulogic; +signal hit_lru : std_ulogic_vector(0 to 2); +signal select_lru : std_ulogic_vector(0 to 3); +signal r0_addr : std_ulogic_vector(52 to 59); +signal lru_valid : std_ulogic_vector(0 to 3); +signal r1_addr : std_ulogic_vector(52 to 57); +signal row_match : std_ulogic_vector(0 to 3); +signal row_match_way : std_ulogic_vector(0 to 3); +signal val_or_match : std_ulogic_vector(0 to 3); +signal next_lru_way : std_ulogic_vector(0 to 3); +signal next_way : std_ulogic_vector(0 to 3); +signal hold_tid : std_ulogic_vector(0 to 3); +signal hold_iu0 : std_ulogic; +signal dir_inval : std_ulogic; +signal write_dir_inval : std_ulogic_vector(0 to 3); +signal write_dir_val : std_ulogic_vector(0 to 3); +signal data_write : std_ulogic_vector(0 to 3); +signal dir_write : std_ulogic_vector(0 to 3); +signal dir_write_no_block : std_ulogic_vector(0 to 3); +signal reload_way : std_ulogic_vector(0 to 3); +signal reload_endian : std_ulogic; +signal swap_endian_data : std_ulogic_vector(0 to 127); +signal branch_decode0 : std_ulogic_vector(0 to 3); +signal swap_branch_decode0 : std_ulogic_vector(0 to 3); +signal branch_decode1 : std_ulogic_vector(0 to 3); +signal swap_branch_decode1 : std_ulogic_vector(0 to 3); +signal branch_decode2 : std_ulogic_vector(0 to 3); +signal swap_branch_decode2 : std_ulogic_vector(0 to 3); +signal branch_decode3 : std_ulogic_vector(0 to 3); +signal swap_branch_decode3 : std_ulogic_vector(0 to 3); +signal instr_data : std_ulogic_vector(0 to 143); +signal swap_data : std_ulogic_vector(0 to 143); +signal data_parity_in : std_ulogic_vector(0 to 17); +signal swap_parity_in : std_ulogic_vector(0 to 17); +signal r2_real_addr : std_ulogic_vector(REAL_IFAR'left to 57); +signal lru_write : std_ulogic_vector(0 to 3); +signal lru_write_addr : std_ulogic_vector(52 to 57); +signal lru_write_way : std_ulogic_vector(0 to 3); +signal r3_addr : std_ulogic_vector(52 to 57); +signal r3_way : std_ulogic_vector(0 to 3); +signal new_ecc_err : std_ulogic_vector(0 to 3); +signal new_ecc_err_ue : std_ulogic_vector(0 to 3); +signal ecc_err : std_ulogic_vector(0 to 3); +signal ecc_err_ue : std_ulogic_vector(0 to 3); +signal ecc_inval : std_ulogic_vector(0 to 3); +signal ecc_block_iu0 : std_ulogic_vector(0 to 3); +signal ecc_fp : std_ulogic; +signal siv : std_ulogic_vector(0 to scan_right); +signal sov : std_ulogic_vector(0 to scan_right); +signal tiup : std_ulogic; + BEGIN + +tiup <= '1'; +default_reld_act <= spr_ic_clockgate_dis or + not miss_tid0_sm_l2(0) or not miss_tid1_sm_l2(0) or not miss_tid2_sm_l2(0) or not miss_tid3_sm_l2(0); +reld_r2_act <= spr_ic_clockgate_dis or reld_r1_vld; +bp_config_d <= spr_ic_bp_config; +spr_ic_cls_d <= spr_ic_cls; +an_ac_reld_data_vld_d <= an_ac_reld_data_vld; +an_ac_reld_core_tag_d <= an_ac_reld_core_tag; +an_ac_reld_qw_d <= an_ac_reld_qw; +reld_r0_vld <= an_ac_reld_data_vld_l2 and (an_ac_reld_core_tag_l2(0 to 2) = "010"); + WITH s2'(an_ac_reld_core_tag_l2(3 to 4)) SELECT reld_r0_tid_plain <= "1000" when "00", + "0100" when "01", + "0010" when "10", + "0001" when others; +reld_r1_tid_d <= gate_and(reld_r0_vld, reld_r0_tid_plain); +reld_r1_qw_d <= an_ac_reld_qw_l2; +reld_r1_vld <= or_reduce(reld_r1_tid_l2); +an_ac_reld_data_d <= an_ac_reld_data; +reld_r2_tid_d <= reld_r1_tid_l2; +reld_r2_qw_d <= reld_r1_qw_l2; +reld_r3_tid_d <= reld_r2_tid_l2; +an_ac_reld_ecc_err_d <= an_ac_reld_ecc_err; +an_ac_reld_ecc_err_ue_d <= an_ac_reld_ecc_err_ue; +MQQ1:IU2_SM_0_PT(1) <= + Eq(( ICS_ICM_IU2_FLUSH_TID(0) & MISS_TID0_SM_L2(1) & + MISS_TID0_SM_L2(3) & MISS_TID0_SM_L2(4) & + MISS_TID0_SM_L2(5) & MISS_TID0_SM_L2(6) & + MISS_TID0_SM_L2(7) & MISS_TID0_SM_L2(8) & + MISS_TID0_SM_L2(9) & MISS_TID0_SM_L2(10) & + MISS_TID0_SM_L2(11) & MISS_TID0_SM_L2(12) & + MISS_TID0_SM_L2(13) & MISS_TID0_SM_L2(14) & + MISS_TID0_SM_L2(15) & MISS_TID0_SM_L2(16) & + MISS_TID0_SM_L2(17) & MISS_TID0_SM_L2(18) & + MISS_TID0_SM_L2(19) ) , STD_ULOGIC_VECTOR'("1000000000000000000")); +MQQ2:IU2_SM_0_PT(2) <= + Eq(( MISS_TID0_SM_L2(0) & MISS_TID0_SM_L2(1) & + MISS_TID0_SM_L2(2) & MISS_TID0_SM_L2(3) & + MISS_TID0_SM_L2(4) & MISS_TID0_SM_L2(5) & + MISS_TID0_SM_L2(8) & MISS_TID0_SM_L2(9) & + MISS_TID0_SM_L2(10) & MISS_TID0_SM_L2(11) & + MISS_TID0_SM_L2(12) & MISS_TID0_SM_L2(13) & + MISS_TID0_SM_L2(14) & MISS_TID0_SM_L2(15) & + MISS_TID0_SM_L2(16) & MISS_TID0_SM_L2(17) & + MISS_TID0_SM_L2(18) & MISS_TID0_SM_L2(19) + ) , STD_ULOGIC_VECTOR'("000000000000000000")); +MQQ3:IU2_SM_0_PT(3) <= + Eq(( RELD_R1_TID_L2(0) & MISS_TID0_SM_L2(0) & + MISS_TID0_SM_L2(1) & MISS_TID0_SM_L2(2) & + MISS_TID0_SM_L2(3) & MISS_TID0_SM_L2(5) & + MISS_TID0_SM_L2(6) & MISS_TID0_SM_L2(7) & + MISS_TID0_SM_L2(8) & MISS_TID0_SM_L2(10) & + MISS_TID0_SM_L2(11) & MISS_TID0_SM_L2(12) & + MISS_TID0_SM_L2(13) & MISS_TID0_SM_L2(14) & + MISS_TID0_SM_L2(15) & MISS_TID0_SM_L2(16) & + MISS_TID0_SM_L2(17) & MISS_TID0_SM_L2(18) & + MISS_TID0_SM_L2(19) ) , STD_ULOGIC_VECTOR'("0000000000000000000")); +MQQ4:IU2_SM_0_PT(4) <= + Eq(( RELD_R1_TID_L2(0) & MISS_TID0_SM_L2(0) & + MISS_TID0_SM_L2(1) & MISS_TID0_SM_L2(2) & + MISS_TID0_SM_L2(3) & MISS_TID0_SM_L2(5) & + MISS_TID0_SM_L2(7) & MISS_TID0_SM_L2(8) & + MISS_TID0_SM_L2(10) & MISS_TID0_SM_L2(11) & + MISS_TID0_SM_L2(12) & MISS_TID0_SM_L2(13) & + MISS_TID0_SM_L2(14) & MISS_TID0_SM_L2(15) & + MISS_TID0_SM_L2(16) & MISS_TID0_SM_L2(17) & + MISS_TID0_SM_L2(18) & MISS_TID0_SM_L2(19) + ) , STD_ULOGIC_VECTOR'("100000000000000000")); +MQQ5:IU2_SM_0_PT(5) <= + Eq(( MISS_FLUSHED0_L2 & MISS_INVAL0_L2 & + MISS_TID0_SM_L2(0) & MISS_TID0_SM_L2(1) & + MISS_TID0_SM_L2(2) & MISS_TID0_SM_L2(6) & + MISS_TID0_SM_L2(7) & MISS_TID0_SM_L2(8) & + MISS_TID0_SM_L2(9) & MISS_TID0_SM_L2(10) & + MISS_TID0_SM_L2(11) & MISS_TID0_SM_L2(16) & + MISS_TID0_SM_L2(17) & MISS_TID0_SM_L2(18) & + MISS_TID0_SM_L2(19) ) , STD_ULOGIC_VECTOR'("000000000000000")); +MQQ6:IU2_SM_0_PT(6) <= + Eq(( R2_CRIT_QW_L2 & MISS_FLUSHED0_L2 & + MISS_TID0_SM_L2(0) & MISS_TID0_SM_L2(1) & + MISS_TID0_SM_L2(2) & MISS_TID0_SM_L2(8) & + MISS_TID0_SM_L2(9) & MISS_TID0_SM_L2(10) & + MISS_TID0_SM_L2(11) & MISS_TID0_SM_L2(16) & + MISS_TID0_SM_L2(17) & MISS_TID0_SM_L2(18) & + MISS_TID0_SM_L2(19) ) , STD_ULOGIC_VECTOR'("1000000000000")); +MQQ7:IU2_SM_0_PT(7) <= + Eq(( RELD_R1_TID_L2(0) & MISS_TID0_SM_L2(0) & + MISS_TID0_SM_L2(1) & MISS_TID0_SM_L2(2) & + MISS_TID0_SM_L2(3) & MISS_TID0_SM_L2(4) & + MISS_TID0_SM_L2(5) & MISS_TID0_SM_L2(6) & + MISS_TID0_SM_L2(7) & MISS_TID0_SM_L2(8) & + MISS_TID0_SM_L2(9) & MISS_TID0_SM_L2(10) & + MISS_TID0_SM_L2(11) & MISS_TID0_SM_L2(13) & + MISS_TID0_SM_L2(14) & MISS_TID0_SM_L2(15) & + MISS_TID0_SM_L2(16) & MISS_TID0_SM_L2(18) & + MISS_TID0_SM_L2(19) ) , STD_ULOGIC_VECTOR'("0000000000000000000")); +MQQ8:IU2_SM_0_PT(8) <= + Eq(( RELD_R1_TID_L2(0) & MISS_TID0_SM_L2(0) & + MISS_TID0_SM_L2(1) & MISS_TID0_SM_L2(2) & + MISS_TID0_SM_L2(3) & MISS_TID0_SM_L2(4) & + MISS_TID0_SM_L2(5) & MISS_TID0_SM_L2(7) & + MISS_TID0_SM_L2(8) & MISS_TID0_SM_L2(9) & + MISS_TID0_SM_L2(10) & MISS_TID0_SM_L2(11) & + MISS_TID0_SM_L2(13) & MISS_TID0_SM_L2(14) & + MISS_TID0_SM_L2(15) & MISS_TID0_SM_L2(16) & + MISS_TID0_SM_L2(18) & MISS_TID0_SM_L2(19) + ) , STD_ULOGIC_VECTOR'("100000000000000000")); +MQQ9:IU2_SM_0_PT(9) <= + Eq(( RELD_R1_TID_L2(0) & MISS_TID0_SM_L2(0) & + MISS_TID0_SM_L2(1) & MISS_TID0_SM_L2(2) & + MISS_TID0_SM_L2(3) & MISS_TID0_SM_L2(4) & + MISS_TID0_SM_L2(5) & MISS_TID0_SM_L2(6) & + MISS_TID0_SM_L2(7) & MISS_TID0_SM_L2(8) & + MISS_TID0_SM_L2(9) & MISS_TID0_SM_L2(10) & + MISS_TID0_SM_L2(11) & MISS_TID0_SM_L2(12) & + MISS_TID0_SM_L2(13) & MISS_TID0_SM_L2(15) & + MISS_TID0_SM_L2(16) & MISS_TID0_SM_L2(17) & + MISS_TID0_SM_L2(18) ) , STD_ULOGIC_VECTOR'("0000000000000000000")); +MQQ10:IU2_SM_0_PT(10) <= + Eq(( RELD_R1_TID_L2(0) & MISS_TID0_SM_L2(0) & + MISS_TID0_SM_L2(1) & MISS_TID0_SM_L2(2) & + MISS_TID0_SM_L2(3) & MISS_TID0_SM_L2(4) & + MISS_TID0_SM_L2(5) & MISS_TID0_SM_L2(7) & + MISS_TID0_SM_L2(8) & MISS_TID0_SM_L2(9) & + MISS_TID0_SM_L2(10) & MISS_TID0_SM_L2(11) & + MISS_TID0_SM_L2(12) & MISS_TID0_SM_L2(13) & + MISS_TID0_SM_L2(15) & MISS_TID0_SM_L2(16) & + MISS_TID0_SM_L2(17) & MISS_TID0_SM_L2(18) + ) , STD_ULOGIC_VECTOR'("100000000000000000")); +MQQ11:IU2_SM_0_PT(11) <= + Eq(( MISS_TID0_SM_L2(18) ) , STD_ULOGIC'('1')); +MQQ12:IU2_SM_0_PT(12) <= + Eq(( MISS_TID0_SM_L2(16) ) , STD_ULOGIC'('1')); +MQQ13:IU2_SM_0_PT(13) <= + Eq(( RELD_R1_TID_L2(0) & MISS_TID0_SM_L2(15) + ) , STD_ULOGIC_VECTOR'("01")); +MQQ14:IU2_SM_0_PT(14) <= + Eq(( RELD_R1_TID_L2(0) & MISS_TID0_SM_L2(15) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ15:IU2_SM_0_PT(15) <= + Eq(( RELD_R1_TID_L2(0) & MISS_TID0_SM_L2(13) + ) , STD_ULOGIC_VECTOR'("01")); +MQQ16:IU2_SM_0_PT(16) <= + Eq(( RELD_R1_TID_L2(0) & MISS_TID0_SM_L2(13) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ17:IU2_SM_0_PT(17) <= + Eq(( MISS_TID0_SM_L2(0) & MISS_TID0_SM_L2(1) & + MISS_TID0_SM_L2(2) & MISS_TID0_SM_L2(6) & + MISS_TID0_SM_L2(7) & MISS_TID0_SM_L2(11) + ) , STD_ULOGIC_VECTOR'("000000")); +MQQ18:IU2_SM_0_PT(18) <= + Eq(( ERAT_ERR(0) & MISS_TID0_SM_L2(0) & + MISS_TID0_SM_L2(6) & MISS_TID0_SM_L2(7) & + MISS_TID0_SM_L2(11) ) , STD_ULOGIC_VECTOR'("00000")); +MQQ19:IU2_SM_0_PT(19) <= + Eq(( ECC_ERR(0) & MISS_TID0_SM_L2(11) + ) , STD_ULOGIC_VECTOR'("01")); +MQQ20:IU2_SM_0_PT(20) <= + Eq(( ECC_ERR(0) & MISS_TID0_SM_L2(11) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ21:IU2_SM_0_PT(21) <= + Eq(( MISS_TID0_SM_L2(10) ) , STD_ULOGIC'('1')); +MQQ22:IU2_SM_0_PT(22) <= + Eq(( MISS_TID0_SM_L2(8) ) , STD_ULOGIC'('1')); +MQQ23:IU2_SM_0_PT(23) <= + Eq(( ECC_ERR(0) & MISS_TID0_SM_L2(0) & + MISS_TID0_SM_L2(1) & MISS_TID0_SM_L2(2) & + MISS_TID0_SM_L2(7) ) , STD_ULOGIC_VECTOR'("10000")); +MQQ24:IU2_SM_0_PT(24) <= + Eq(( MISS_FLUSHED0_L2 & MISS_TID0_SM_L2(7) + ) , STD_ULOGIC_VECTOR'("01")); +MQQ25:IU2_SM_0_PT(25) <= + Eq(( ECC_ERR(0) & ECC_ERR_UE(0) & + MISS_FLUSHED0_L2 & MISS_INVAL0_L2 & + MISS_TID0_SM_L2(6) ) , STD_ULOGIC_VECTOR'("00001")); +MQQ26:IU2_SM_0_PT(26) <= + Eq(( MISS_FLUSHED0_L2 & MISS_INVAL0_L2 & + MISS_TID0_SM_L2(6) ) , STD_ULOGIC_VECTOR'("001")); +MQQ27:IU2_SM_0_PT(27) <= + Eq(( MISS_INVAL0_L2 & MISS_TID0_SM_L2(6) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ28:IU2_SM_0_PT(28) <= + Eq(( MISS_FLUSHED0_L2 & MISS_TID0_SM_L2(6) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ29:IU2_SM_0_PT(29) <= + Eq(( ECC_ERR_UE(0) & MISS_TID0_SM_L2(6) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ30:IU2_SM_0_PT(30) <= + Eq(( RELD_R1_TID_L2(0) & SPR_IC_CLS_L2 & + MISS_TID0_SM_L2(5) ) , STD_ULOGIC_VECTOR'("001")); +MQQ31:IU2_SM_0_PT(31) <= + Eq(( RELD_R1_TID_L2(0) & SPR_IC_CLS_L2 & + MISS_TID0_SM_L2(5) ) , STD_ULOGIC_VECTOR'("101")); +MQQ32:IU2_SM_0_PT(32) <= + Eq(( RELD_R1_TID_L2(0) & SPR_IC_CLS_L2 & + MISS_TID0_SM_L2(5) ) , STD_ULOGIC_VECTOR'("011")); +MQQ33:IU2_SM_0_PT(33) <= + Eq(( RELD_R1_TID_L2(0) & SPR_IC_CLS_L2 & + MISS_TID0_SM_L2(5) ) , STD_ULOGIC_VECTOR'("111")); +MQQ34:IU2_SM_0_PT(34) <= + Eq(( MISS_FLUSHED0_L2 & MISS_INVAL0_L2 & + MISS_TID0_SM_L2(3) ) , STD_ULOGIC_VECTOR'("001")); +MQQ35:IU2_SM_0_PT(35) <= + Eq(( RELD_R1_TID_L2(0) & MISS_TID0_SM_L2(3) + ) , STD_ULOGIC_VECTOR'("01")); +MQQ36:IU2_SM_0_PT(36) <= + Eq(( RELD_R1_TID_L2(0) & MISS_TID0_SM_L2(3) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ37:IU2_SM_0_PT(37) <= + Eq(( ERAT_ERR(0) & ICS_ICM_IU2_FLUSH_TID(0) & + RELEASE_SM & MISS_TID0_SM_L2(2) + ) , STD_ULOGIC_VECTOR'("0001")); +MQQ38:IU2_SM_0_PT(38) <= + Eq(( RELEASE_SM & MISS_TID0_SM_L2(2) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ39:IU2_SM_0_PT(39) <= + Eq(( ERAT_ERR(0) & MISS_TID0_SM_L2(2) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ40:IU2_SM_0_PT(40) <= + Eq(( ERAT_ERR(0) & RELD_R1_TID_L2(0) & + MISS_TID0_SM_L2(1) ) , STD_ULOGIC_VECTOR'("001")); +MQQ41:IU2_SM_0_PT(41) <= + Eq(( ERAT_ERR(0) & MISS_CI0_L2 & + RELD_R1_TID_L2(0) & MISS_TID0_SM_L2(1) + ) , STD_ULOGIC_VECTOR'("0011")); +MQQ42:IU2_SM_0_PT(42) <= + Eq(( ERAT_ERR(0) & MISS_CI0_L2 & + RELD_R1_TID_L2(0) & MISS_TID0_SM_L2(1) + ) , STD_ULOGIC_VECTOR'("0111")); +MQQ43:IU2_SM_0_PT(43) <= + Eq(( ERAT_ERR(0) & MISS_TID0_SM_L2(1) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ44:IU2_SM_0_PT(44) <= + Eq(( ICD_ICM_MISS & ICD_ICM_TID(0) & + ICD_ICM_WIMGE(1) & ADDR_MATCH & + ICS_ICM_IU2_FLUSH_TID(0) & RELEASE_SM & + MISS_TID0_SM_L2(0) ) , STD_ULOGIC_VECTOR'("1101001")); +MQQ45:IU2_SM_0_PT(45) <= + Eq(( ICD_ICM_WIMGE(1) & ADDR_MATCH & + RELEASE_SM & MISS_TID0_SM_L2(0) + ) , STD_ULOGIC_VECTOR'("0111")); +MQQ46:IU2_SM_0_PT(46) <= + Eq(( ICD_ICM_MISS & ICD_ICM_TID(0) & + ADDR_MATCH & ICS_ICM_IU2_FLUSH_TID(0) & + MISS_TID0_SM_L2(0) ) , STD_ULOGIC_VECTOR'("11001")); +MQQ47:IU2_SM_0_PT(47) <= + Eq(( ICD_ICM_MISS & ICD_ICM_TID(0) & + ICD_ICM_WIMGE(1) & ICS_ICM_IU2_FLUSH_TID(0) & + MISS_TID0_SM_L2(0) ) , STD_ULOGIC_VECTOR'("11101")); +MQQ48:IU2_SM_0_PT(48) <= + Eq(( ICD_ICM_TID(0) & MISS_TID0_SM_L2(0) + ) , STD_ULOGIC_VECTOR'("01")); +MQQ49:IU2_SM_0_PT(49) <= + Eq(( ICD_ICM_MISS & MISS_TID0_SM_L2(0) + ) , STD_ULOGIC_VECTOR'("01")); +MQQ50:MISS_TID0_SM_D(0) <= + (IU2_SM_0_PT(1) OR IU2_SM_0_PT(19) + OR IU2_SM_0_PT(38) OR IU2_SM_0_PT(39) + OR IU2_SM_0_PT(43) OR IU2_SM_0_PT(45) + OR IU2_SM_0_PT(48) OR IU2_SM_0_PT(49) + ); +MQQ51:MISS_TID0_SM_D(1) <= + (IU2_SM_0_PT(20) OR IU2_SM_0_PT(40) + OR IU2_SM_0_PT(46) OR IU2_SM_0_PT(47) + ); +MQQ52:MISS_TID0_SM_D(2) <= + (IU2_SM_0_PT(37) OR IU2_SM_0_PT(44) + ); +MQQ53:MISS_TID0_SM_D(3) <= + (IU2_SM_0_PT(41)); +MQQ54:MISS_TID0_SM_D(4) <= + (IU2_SM_0_PT(22) OR IU2_SM_0_PT(36) + ); +MQQ55:MISS_TID0_SM_D(5) <= + (IU2_SM_0_PT(4)); +MQQ56:MISS_TID0_SM_D(6) <= + (IU2_SM_0_PT(14) OR IU2_SM_0_PT(21) + OR IU2_SM_0_PT(31)); +MQQ57:MISS_TID0_SM_D(7) <= + (IU2_SM_0_PT(42)); +MQQ58:MISS_TID0_SM_D(8) <= + (IU2_SM_0_PT(35)); +MQQ59:MISS_TID0_SM_D(9) <= + (IU2_SM_0_PT(3)); +MQQ60:MISS_TID0_SM_D(10) <= + (IU2_SM_0_PT(13) OR IU2_SM_0_PT(30) + ); +MQQ61:MISS_TID0_SM_D(11) <= + (IU2_SM_0_PT(2)); +MQQ62:MISS_TID0_SM_D(12) <= + (IU2_SM_0_PT(12) OR IU2_SM_0_PT(33) + ); +MQQ63:MISS_TID0_SM_D(13) <= + (IU2_SM_0_PT(8)); +MQQ64:MISS_TID0_SM_D(14) <= + (IU2_SM_0_PT(11) OR IU2_SM_0_PT(16) + ); +MQQ65:MISS_TID0_SM_D(15) <= + (IU2_SM_0_PT(10)); +MQQ66:MISS_TID0_SM_D(16) <= + (IU2_SM_0_PT(32)); +MQQ67:MISS_TID0_SM_D(17) <= + (IU2_SM_0_PT(7)); +MQQ68:MISS_TID0_SM_D(18) <= + (IU2_SM_0_PT(15)); +MQQ69:MISS_TID0_SM_D(19) <= + (IU2_SM_0_PT(9)); +MQQ70:RESET_STATE(0) <= + (IU2_SM_0_PT(19) OR IU2_SM_0_PT(43) + ); +MQQ71:REQUEST_TID(0) <= + (IU2_SM_0_PT(46) OR IU2_SM_0_PT(47) + ); + +MQQ72:WRITE_DIR_INVAL(0) <= + (IU2_SM_0_PT(34)); +MQQ73:WRITE_DIR_VAL(0) <= + (IU2_SM_0_PT(25)); +MQQ74:HOLD_TID(0) <= + (IU2_SM_0_PT(17) OR IU2_SM_0_PT(18) + OR IU2_SM_0_PT(23) OR IU2_SM_0_PT(27) + OR IU2_SM_0_PT(28) OR IU2_SM_0_PT(29) + ); +MQQ75:DATA_WRITE(0) <= + (IU2_SM_0_PT(5) OR IU2_SM_0_PT(26) + ); +MQQ76:DIR_WRITE(0) <= + (IU2_SM_0_PT(5)); +MQQ77:LOAD_TID(0) <= + (IU2_SM_0_PT(6) OR IU2_SM_0_PT(24) + ); +MQQ78:RELEASE_SM_HOLD(0) <= + (IU2_SM_0_PT(2) OR IU2_SM_0_PT(19) + OR IU2_SM_0_PT(43)); + +MQQ79:IU2_SM_1_PT(1) <= + Eq(( ICS_ICM_IU2_FLUSH_TID(1) & MISS_TID1_SM_L2(1) & + MISS_TID1_SM_L2(3) & MISS_TID1_SM_L2(4) & + MISS_TID1_SM_L2(5) & MISS_TID1_SM_L2(6) & + MISS_TID1_SM_L2(7) & MISS_TID1_SM_L2(8) & + MISS_TID1_SM_L2(9) & MISS_TID1_SM_L2(10) & + MISS_TID1_SM_L2(11) & MISS_TID1_SM_L2(12) & + MISS_TID1_SM_L2(13) & MISS_TID1_SM_L2(14) & + MISS_TID1_SM_L2(15) & MISS_TID1_SM_L2(16) & + MISS_TID1_SM_L2(17) & MISS_TID1_SM_L2(18) & + MISS_TID1_SM_L2(19) ) , STD_ULOGIC_VECTOR'("1000000000000000000")); +MQQ80:IU2_SM_1_PT(2) <= + Eq(( MISS_TID1_SM_L2(0) & MISS_TID1_SM_L2(1) & + MISS_TID1_SM_L2(2) & MISS_TID1_SM_L2(3) & + MISS_TID1_SM_L2(4) & MISS_TID1_SM_L2(5) & + MISS_TID1_SM_L2(8) & MISS_TID1_SM_L2(9) & + MISS_TID1_SM_L2(10) & MISS_TID1_SM_L2(11) & + MISS_TID1_SM_L2(12) & MISS_TID1_SM_L2(13) & + MISS_TID1_SM_L2(14) & MISS_TID1_SM_L2(15) & + MISS_TID1_SM_L2(16) & MISS_TID1_SM_L2(17) & + MISS_TID1_SM_L2(18) & MISS_TID1_SM_L2(19) + ) , STD_ULOGIC_VECTOR'("000000000000000000")); +MQQ81:IU2_SM_1_PT(3) <= + Eq(( RELD_R1_TID_L2(1) & MISS_TID1_SM_L2(0) & + MISS_TID1_SM_L2(1) & MISS_TID1_SM_L2(2) & + MISS_TID1_SM_L2(3) & MISS_TID1_SM_L2(5) & + MISS_TID1_SM_L2(6) & MISS_TID1_SM_L2(7) & + MISS_TID1_SM_L2(8) & MISS_TID1_SM_L2(10) & + MISS_TID1_SM_L2(11) & MISS_TID1_SM_L2(12) & + MISS_TID1_SM_L2(13) & MISS_TID1_SM_L2(14) & + MISS_TID1_SM_L2(15) & MISS_TID1_SM_L2(16) & + MISS_TID1_SM_L2(17) & MISS_TID1_SM_L2(18) & + MISS_TID1_SM_L2(19) ) , STD_ULOGIC_VECTOR'("0000000000000000000")); +MQQ82:IU2_SM_1_PT(4) <= + Eq(( RELD_R1_TID_L2(1) & MISS_TID1_SM_L2(0) & + MISS_TID1_SM_L2(1) & MISS_TID1_SM_L2(2) & + MISS_TID1_SM_L2(3) & MISS_TID1_SM_L2(5) & + MISS_TID1_SM_L2(7) & MISS_TID1_SM_L2(8) & + MISS_TID1_SM_L2(10) & MISS_TID1_SM_L2(11) & + MISS_TID1_SM_L2(12) & MISS_TID1_SM_L2(13) & + MISS_TID1_SM_L2(14) & MISS_TID1_SM_L2(15) & + MISS_TID1_SM_L2(16) & MISS_TID1_SM_L2(17) & + MISS_TID1_SM_L2(18) & MISS_TID1_SM_L2(19) + ) , STD_ULOGIC_VECTOR'("100000000000000000")); +MQQ83:IU2_SM_1_PT(5) <= + Eq(( MISS_FLUSHED1_L2 & MISS_INVAL1_L2 & + MISS_TID1_SM_L2(0) & MISS_TID1_SM_L2(1) & + MISS_TID1_SM_L2(2) & MISS_TID1_SM_L2(6) & + MISS_TID1_SM_L2(7) & MISS_TID1_SM_L2(8) & + MISS_TID1_SM_L2(9) & MISS_TID1_SM_L2(10) & + MISS_TID1_SM_L2(11) & MISS_TID1_SM_L2(16) & + MISS_TID1_SM_L2(17) & MISS_TID1_SM_L2(18) & + MISS_TID1_SM_L2(19) ) , STD_ULOGIC_VECTOR'("000000000000000")); +MQQ84:IU2_SM_1_PT(6) <= + Eq(( R2_CRIT_QW_L2 & MISS_FLUSHED1_L2 & + MISS_TID1_SM_L2(0) & MISS_TID1_SM_L2(1) & + MISS_TID1_SM_L2(2) & MISS_TID1_SM_L2(8) & + MISS_TID1_SM_L2(9) & MISS_TID1_SM_L2(10) & + MISS_TID1_SM_L2(11) & MISS_TID1_SM_L2(16) & + MISS_TID1_SM_L2(17) & MISS_TID1_SM_L2(18) & + MISS_TID1_SM_L2(19) ) , STD_ULOGIC_VECTOR'("1000000000000")); +MQQ85:IU2_SM_1_PT(7) <= + Eq(( RELD_R1_TID_L2(1) & MISS_TID1_SM_L2(0) & + MISS_TID1_SM_L2(1) & MISS_TID1_SM_L2(2) & + MISS_TID1_SM_L2(3) & MISS_TID1_SM_L2(4) & + MISS_TID1_SM_L2(5) & MISS_TID1_SM_L2(6) & + MISS_TID1_SM_L2(7) & MISS_TID1_SM_L2(8) & + MISS_TID1_SM_L2(9) & MISS_TID1_SM_L2(10) & + MISS_TID1_SM_L2(11) & MISS_TID1_SM_L2(13) & + MISS_TID1_SM_L2(14) & MISS_TID1_SM_L2(15) & + MISS_TID1_SM_L2(16) & MISS_TID1_SM_L2(18) & + MISS_TID1_SM_L2(19) ) , STD_ULOGIC_VECTOR'("0000000000000000000")); +MQQ86:IU2_SM_1_PT(8) <= + Eq(( RELD_R1_TID_L2(1) & MISS_TID1_SM_L2(0) & + MISS_TID1_SM_L2(1) & MISS_TID1_SM_L2(2) & + MISS_TID1_SM_L2(3) & MISS_TID1_SM_L2(4) & + MISS_TID1_SM_L2(5) & MISS_TID1_SM_L2(7) & + MISS_TID1_SM_L2(8) & MISS_TID1_SM_L2(9) & + MISS_TID1_SM_L2(10) & MISS_TID1_SM_L2(11) & + MISS_TID1_SM_L2(13) & MISS_TID1_SM_L2(14) & + MISS_TID1_SM_L2(15) & MISS_TID1_SM_L2(16) & + MISS_TID1_SM_L2(18) & MISS_TID1_SM_L2(19) + ) , STD_ULOGIC_VECTOR'("100000000000000000")); +MQQ87:IU2_SM_1_PT(9) <= + Eq(( RELD_R1_TID_L2(1) & MISS_TID1_SM_L2(0) & + MISS_TID1_SM_L2(1) & MISS_TID1_SM_L2(2) & + MISS_TID1_SM_L2(3) & MISS_TID1_SM_L2(4) & + MISS_TID1_SM_L2(5) & MISS_TID1_SM_L2(6) & + MISS_TID1_SM_L2(7) & MISS_TID1_SM_L2(8) & + MISS_TID1_SM_L2(9) & MISS_TID1_SM_L2(10) & + MISS_TID1_SM_L2(11) & MISS_TID1_SM_L2(12) & + MISS_TID1_SM_L2(13) & MISS_TID1_SM_L2(15) & + MISS_TID1_SM_L2(16) & MISS_TID1_SM_L2(17) & + MISS_TID1_SM_L2(18) ) , STD_ULOGIC_VECTOR'("0000000000000000000")); +MQQ88:IU2_SM_1_PT(10) <= + Eq(( RELD_R1_TID_L2(1) & MISS_TID1_SM_L2(0) & + MISS_TID1_SM_L2(1) & MISS_TID1_SM_L2(2) & + MISS_TID1_SM_L2(3) & MISS_TID1_SM_L2(4) & + MISS_TID1_SM_L2(5) & MISS_TID1_SM_L2(7) & + MISS_TID1_SM_L2(8) & MISS_TID1_SM_L2(9) & + MISS_TID1_SM_L2(10) & MISS_TID1_SM_L2(11) & + MISS_TID1_SM_L2(12) & MISS_TID1_SM_L2(13) & + MISS_TID1_SM_L2(15) & MISS_TID1_SM_L2(16) & + MISS_TID1_SM_L2(17) & MISS_TID1_SM_L2(18) + ) , STD_ULOGIC_VECTOR'("100000000000000000")); +MQQ89:IU2_SM_1_PT(11) <= + Eq(( MISS_TID1_SM_L2(18) ) , STD_ULOGIC'('1')); +MQQ90:IU2_SM_1_PT(12) <= + Eq(( MISS_TID1_SM_L2(16) ) , STD_ULOGIC'('1')); +MQQ91:IU2_SM_1_PT(13) <= + Eq(( RELD_R1_TID_L2(1) & MISS_TID1_SM_L2(15) + ) , STD_ULOGIC_VECTOR'("01")); +MQQ92:IU2_SM_1_PT(14) <= + Eq(( RELD_R1_TID_L2(1) & MISS_TID1_SM_L2(15) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ93:IU2_SM_1_PT(15) <= + Eq(( RELD_R1_TID_L2(1) & MISS_TID1_SM_L2(13) + ) , STD_ULOGIC_VECTOR'("01")); +MQQ94:IU2_SM_1_PT(16) <= + Eq(( RELD_R1_TID_L2(1) & MISS_TID1_SM_L2(13) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ95:IU2_SM_1_PT(17) <= + Eq(( MISS_TID1_SM_L2(0) & MISS_TID1_SM_L2(1) & + MISS_TID1_SM_L2(2) & MISS_TID1_SM_L2(6) & + MISS_TID1_SM_L2(7) & MISS_TID1_SM_L2(11) + ) , STD_ULOGIC_VECTOR'("000000")); +MQQ96:IU2_SM_1_PT(18) <= + Eq(( ERAT_ERR(1) & MISS_TID1_SM_L2(0) & + MISS_TID1_SM_L2(6) & MISS_TID1_SM_L2(7) & + MISS_TID1_SM_L2(11) ) , STD_ULOGIC_VECTOR'("00000")); +MQQ97:IU2_SM_1_PT(19) <= + Eq(( ECC_ERR(1) & MISS_TID1_SM_L2(11) + ) , STD_ULOGIC_VECTOR'("01")); +MQQ98:IU2_SM_1_PT(20) <= + Eq(( ECC_ERR(1) & MISS_TID1_SM_L2(11) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ99:IU2_SM_1_PT(21) <= + Eq(( MISS_TID1_SM_L2(10) ) , STD_ULOGIC'('1')); +MQQ100:IU2_SM_1_PT(22) <= + Eq(( MISS_TID1_SM_L2(8) ) , STD_ULOGIC'('1')); +MQQ101:IU2_SM_1_PT(23) <= + Eq(( ECC_ERR(1) & MISS_TID1_SM_L2(0) & + MISS_TID1_SM_L2(1) & MISS_TID1_SM_L2(2) & + MISS_TID1_SM_L2(7) ) , STD_ULOGIC_VECTOR'("10000")); +MQQ102:IU2_SM_1_PT(24) <= + Eq(( MISS_FLUSHED1_L2 & MISS_TID1_SM_L2(7) + ) , STD_ULOGIC_VECTOR'("01")); +MQQ103:IU2_SM_1_PT(25) <= + Eq(( ECC_ERR(1) & ECC_ERR_UE(1) & + MISS_FLUSHED1_L2 & MISS_INVAL1_L2 & + MISS_TID1_SM_L2(6) ) , STD_ULOGIC_VECTOR'("00001")); +MQQ104:IU2_SM_1_PT(26) <= + Eq(( MISS_FLUSHED1_L2 & MISS_INVAL1_L2 & + MISS_TID1_SM_L2(6) ) , STD_ULOGIC_VECTOR'("001")); +MQQ105:IU2_SM_1_PT(27) <= + Eq(( MISS_INVAL1_L2 & MISS_TID1_SM_L2(6) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ106:IU2_SM_1_PT(28) <= + Eq(( MISS_FLUSHED1_L2 & MISS_TID1_SM_L2(6) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ107:IU2_SM_1_PT(29) <= + Eq(( ECC_ERR_UE(1) & MISS_TID1_SM_L2(6) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ108:IU2_SM_1_PT(30) <= + Eq(( RELD_R1_TID_L2(1) & SPR_IC_CLS_L2 & + MISS_TID1_SM_L2(5) ) , STD_ULOGIC_VECTOR'("001")); +MQQ109:IU2_SM_1_PT(31) <= + Eq(( RELD_R1_TID_L2(1) & SPR_IC_CLS_L2 & + MISS_TID1_SM_L2(5) ) , STD_ULOGIC_VECTOR'("101")); +MQQ110:IU2_SM_1_PT(32) <= + Eq(( RELD_R1_TID_L2(1) & SPR_IC_CLS_L2 & + MISS_TID1_SM_L2(5) ) , STD_ULOGIC_VECTOR'("011")); +MQQ111:IU2_SM_1_PT(33) <= + Eq(( RELD_R1_TID_L2(1) & SPR_IC_CLS_L2 & + MISS_TID1_SM_L2(5) ) , STD_ULOGIC_VECTOR'("111")); +MQQ112:IU2_SM_1_PT(34) <= + Eq(( MISS_FLUSHED1_L2 & MISS_INVAL1_L2 & + MISS_TID1_SM_L2(3) ) , STD_ULOGIC_VECTOR'("001")); +MQQ113:IU2_SM_1_PT(35) <= + Eq(( RELD_R1_TID_L2(1) & MISS_TID1_SM_L2(3) + ) , STD_ULOGIC_VECTOR'("01")); +MQQ114:IU2_SM_1_PT(36) <= + Eq(( RELD_R1_TID_L2(1) & MISS_TID1_SM_L2(3) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ115:IU2_SM_1_PT(37) <= + Eq(( ERAT_ERR(1) & ICS_ICM_IU2_FLUSH_TID(1) & + RELEASE_SM & MISS_TID1_SM_L2(2) + ) , STD_ULOGIC_VECTOR'("0001")); +MQQ116:IU2_SM_1_PT(38) <= + Eq(( RELEASE_SM & MISS_TID1_SM_L2(2) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ117:IU2_SM_1_PT(39) <= + Eq(( ERAT_ERR(1) & MISS_TID1_SM_L2(2) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ118:IU2_SM_1_PT(40) <= + Eq(( ERAT_ERR(1) & RELD_R1_TID_L2(1) & + MISS_TID1_SM_L2(1) ) , STD_ULOGIC_VECTOR'("001")); +MQQ119:IU2_SM_1_PT(41) <= + Eq(( ERAT_ERR(1) & MISS_CI1_L2 & + RELD_R1_TID_L2(1) & MISS_TID1_SM_L2(1) + ) , STD_ULOGIC_VECTOR'("0011")); +MQQ120:IU2_SM_1_PT(42) <= + Eq(( ERAT_ERR(1) & MISS_CI1_L2 & + RELD_R1_TID_L2(1) & MISS_TID1_SM_L2(1) + ) , STD_ULOGIC_VECTOR'("0111")); +MQQ121:IU2_SM_1_PT(43) <= + Eq(( ERAT_ERR(1) & MISS_TID1_SM_L2(1) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ122:IU2_SM_1_PT(44) <= + Eq(( ICD_ICM_MISS & ICD_ICM_TID(1) & + ICD_ICM_WIMGE(1) & ADDR_MATCH & + ICS_ICM_IU2_FLUSH_TID(1) & RELEASE_SM & + MISS_TID1_SM_L2(0) ) , STD_ULOGIC_VECTOR'("1101001")); +MQQ123:IU2_SM_1_PT(45) <= + Eq(( ICD_ICM_WIMGE(1) & ADDR_MATCH & + RELEASE_SM & MISS_TID1_SM_L2(0) + ) , STD_ULOGIC_VECTOR'("0111")); +MQQ124:IU2_SM_1_PT(46) <= + Eq(( ICD_ICM_MISS & ICD_ICM_TID(1) & + ADDR_MATCH & ICS_ICM_IU2_FLUSH_TID(1) & + MISS_TID1_SM_L2(0) ) , STD_ULOGIC_VECTOR'("11001")); +MQQ125:IU2_SM_1_PT(47) <= + Eq(( ICD_ICM_MISS & ICD_ICM_TID(1) & + ICD_ICM_WIMGE(1) & ICS_ICM_IU2_FLUSH_TID(1) & + MISS_TID1_SM_L2(0) ) , STD_ULOGIC_VECTOR'("11101")); +MQQ126:IU2_SM_1_PT(48) <= + Eq(( ICD_ICM_TID(1) & MISS_TID1_SM_L2(0) + ) , STD_ULOGIC_VECTOR'("01")); +MQQ127:IU2_SM_1_PT(49) <= + Eq(( ICD_ICM_MISS & MISS_TID1_SM_L2(0) + ) , STD_ULOGIC_VECTOR'("01")); +MQQ128:MISS_TID1_SM_D(0) <= + (IU2_SM_1_PT(1) OR IU2_SM_1_PT(19) + OR IU2_SM_1_PT(38) OR IU2_SM_1_PT(39) + OR IU2_SM_1_PT(43) OR IU2_SM_1_PT(45) + OR IU2_SM_1_PT(48) OR IU2_SM_1_PT(49) + ); +MQQ129:MISS_TID1_SM_D(1) <= + (IU2_SM_1_PT(20) OR IU2_SM_1_PT(40) + OR IU2_SM_1_PT(46) OR IU2_SM_1_PT(47) + ); +MQQ130:MISS_TID1_SM_D(2) <= + (IU2_SM_1_PT(37) OR IU2_SM_1_PT(44) + ); +MQQ131:MISS_TID1_SM_D(3) <= + (IU2_SM_1_PT(41)); +MQQ132:MISS_TID1_SM_D(4) <= + (IU2_SM_1_PT(22) OR IU2_SM_1_PT(36) + ); +MQQ133:MISS_TID1_SM_D(5) <= + (IU2_SM_1_PT(4)); +MQQ134:MISS_TID1_SM_D(6) <= + (IU2_SM_1_PT(14) OR IU2_SM_1_PT(21) + OR IU2_SM_1_PT(31)); +MQQ135:MISS_TID1_SM_D(7) <= + (IU2_SM_1_PT(42)); +MQQ136:MISS_TID1_SM_D(8) <= + (IU2_SM_1_PT(35)); +MQQ137:MISS_TID1_SM_D(9) <= + (IU2_SM_1_PT(3)); +MQQ138:MISS_TID1_SM_D(10) <= + (IU2_SM_1_PT(13) OR IU2_SM_1_PT(30) + ); +MQQ139:MISS_TID1_SM_D(11) <= + (IU2_SM_1_PT(2)); +MQQ140:MISS_TID1_SM_D(12) <= + (IU2_SM_1_PT(12) OR IU2_SM_1_PT(33) + ); +MQQ141:MISS_TID1_SM_D(13) <= + (IU2_SM_1_PT(8)); +MQQ142:MISS_TID1_SM_D(14) <= + (IU2_SM_1_PT(11) OR IU2_SM_1_PT(16) + ); +MQQ143:MISS_TID1_SM_D(15) <= + (IU2_SM_1_PT(10)); +MQQ144:MISS_TID1_SM_D(16) <= + (IU2_SM_1_PT(32)); +MQQ145:MISS_TID1_SM_D(17) <= + (IU2_SM_1_PT(7)); +MQQ146:MISS_TID1_SM_D(18) <= + (IU2_SM_1_PT(15)); +MQQ147:MISS_TID1_SM_D(19) <= + (IU2_SM_1_PT(9)); +MQQ148:RESET_STATE(1) <= + (IU2_SM_1_PT(19) OR IU2_SM_1_PT(43) + ); +MQQ149:REQUEST_TID(1) <= + (IU2_SM_1_PT(46) OR IU2_SM_1_PT(47) + ); +MQQ150:WRITE_DIR_INVAL(1) <= + (IU2_SM_1_PT(34)); +MQQ151:WRITE_DIR_VAL(1) <= + (IU2_SM_1_PT(25)); +MQQ152:HOLD_TID(1) <= + (IU2_SM_1_PT(17) OR IU2_SM_1_PT(18) + OR IU2_SM_1_PT(23) OR IU2_SM_1_PT(27) + OR IU2_SM_1_PT(28) OR IU2_SM_1_PT(29) + ); +MQQ153:DATA_WRITE(1) <= + (IU2_SM_1_PT(5) OR IU2_SM_1_PT(26) + ); +MQQ154:DIR_WRITE(1) <= + (IU2_SM_1_PT(5)); +MQQ155:LOAD_TID(1) <= + (IU2_SM_1_PT(6) OR IU2_SM_1_PT(24) + ); +MQQ156:RELEASE_SM_HOLD(1) <= + (IU2_SM_1_PT(2) OR IU2_SM_1_PT(19) + OR IU2_SM_1_PT(43)); + +MQQ157:IU2_SM_2_PT(1) <= + Eq(( ICS_ICM_IU2_FLUSH_TID(2) & MISS_TID2_SM_L2(1) & + MISS_TID2_SM_L2(3) & MISS_TID2_SM_L2(4) & + MISS_TID2_SM_L2(5) & MISS_TID2_SM_L2(6) & + MISS_TID2_SM_L2(7) & MISS_TID2_SM_L2(8) & + MISS_TID2_SM_L2(9) & MISS_TID2_SM_L2(10) & + MISS_TID2_SM_L2(11) & MISS_TID2_SM_L2(12) & + MISS_TID2_SM_L2(13) & MISS_TID2_SM_L2(14) & + MISS_TID2_SM_L2(15) & MISS_TID2_SM_L2(16) & + MISS_TID2_SM_L2(17) & MISS_TID2_SM_L2(18) & + MISS_TID2_SM_L2(19) ) , STD_ULOGIC_VECTOR'("1000000000000000000")); +MQQ158:IU2_SM_2_PT(2) <= + Eq(( MISS_TID2_SM_L2(0) & MISS_TID2_SM_L2(1) & + MISS_TID2_SM_L2(2) & MISS_TID2_SM_L2(3) & + MISS_TID2_SM_L2(4) & MISS_TID2_SM_L2(5) & + MISS_TID2_SM_L2(8) & MISS_TID2_SM_L2(9) & + MISS_TID2_SM_L2(10) & MISS_TID2_SM_L2(11) & + MISS_TID2_SM_L2(12) & MISS_TID2_SM_L2(13) & + MISS_TID2_SM_L2(14) & MISS_TID2_SM_L2(15) & + MISS_TID2_SM_L2(16) & MISS_TID2_SM_L2(17) & + MISS_TID2_SM_L2(18) & MISS_TID2_SM_L2(19) + ) , STD_ULOGIC_VECTOR'("000000000000000000")); +MQQ159:IU2_SM_2_PT(3) <= + Eq(( RELD_R1_TID_L2(2) & MISS_TID2_SM_L2(0) & + MISS_TID2_SM_L2(1) & MISS_TID2_SM_L2(2) & + MISS_TID2_SM_L2(3) & MISS_TID2_SM_L2(5) & + MISS_TID2_SM_L2(6) & MISS_TID2_SM_L2(7) & + MISS_TID2_SM_L2(8) & MISS_TID2_SM_L2(10) & + MISS_TID2_SM_L2(11) & MISS_TID2_SM_L2(12) & + MISS_TID2_SM_L2(13) & MISS_TID2_SM_L2(14) & + MISS_TID2_SM_L2(15) & MISS_TID2_SM_L2(16) & + MISS_TID2_SM_L2(17) & MISS_TID2_SM_L2(18) & + MISS_TID2_SM_L2(19) ) , STD_ULOGIC_VECTOR'("0000000000000000000")); +MQQ160:IU2_SM_2_PT(4) <= + Eq(( RELD_R1_TID_L2(2) & MISS_TID2_SM_L2(0) & + MISS_TID2_SM_L2(1) & MISS_TID2_SM_L2(2) & + MISS_TID2_SM_L2(3) & MISS_TID2_SM_L2(5) & + MISS_TID2_SM_L2(7) & MISS_TID2_SM_L2(8) & + MISS_TID2_SM_L2(10) & MISS_TID2_SM_L2(11) & + MISS_TID2_SM_L2(12) & MISS_TID2_SM_L2(13) & + MISS_TID2_SM_L2(14) & MISS_TID2_SM_L2(15) & + MISS_TID2_SM_L2(16) & MISS_TID2_SM_L2(17) & + MISS_TID2_SM_L2(18) & MISS_TID2_SM_L2(19) + ) , STD_ULOGIC_VECTOR'("100000000000000000")); +MQQ161:IU2_SM_2_PT(5) <= + Eq(( MISS_FLUSHED2_L2 & MISS_INVAL2_L2 & + MISS_TID2_SM_L2(0) & MISS_TID2_SM_L2(1) & + MISS_TID2_SM_L2(2) & MISS_TID2_SM_L2(6) & + MISS_TID2_SM_L2(7) & MISS_TID2_SM_L2(8) & + MISS_TID2_SM_L2(9) & MISS_TID2_SM_L2(10) & + MISS_TID2_SM_L2(11) & MISS_TID2_SM_L2(16) & + MISS_TID2_SM_L2(17) & MISS_TID2_SM_L2(18) & + MISS_TID2_SM_L2(19) ) , STD_ULOGIC_VECTOR'("000000000000000")); +MQQ162:IU2_SM_2_PT(6) <= + Eq(( R2_CRIT_QW_L2 & MISS_FLUSHED2_L2 & + MISS_TID2_SM_L2(0) & MISS_TID2_SM_L2(1) & + MISS_TID2_SM_L2(2) & MISS_TID2_SM_L2(8) & + MISS_TID2_SM_L2(9) & MISS_TID2_SM_L2(10) & + MISS_TID2_SM_L2(11) & MISS_TID2_SM_L2(16) & + MISS_TID2_SM_L2(17) & MISS_TID2_SM_L2(18) & + MISS_TID2_SM_L2(19) ) , STD_ULOGIC_VECTOR'("1000000000000")); +MQQ163:IU2_SM_2_PT(7) <= + Eq(( RELD_R1_TID_L2(2) & MISS_TID2_SM_L2(0) & + MISS_TID2_SM_L2(1) & MISS_TID2_SM_L2(2) & + MISS_TID2_SM_L2(3) & MISS_TID2_SM_L2(4) & + MISS_TID2_SM_L2(5) & MISS_TID2_SM_L2(6) & + MISS_TID2_SM_L2(7) & MISS_TID2_SM_L2(8) & + MISS_TID2_SM_L2(9) & MISS_TID2_SM_L2(10) & + MISS_TID2_SM_L2(11) & MISS_TID2_SM_L2(13) & + MISS_TID2_SM_L2(14) & MISS_TID2_SM_L2(15) & + MISS_TID2_SM_L2(16) & MISS_TID2_SM_L2(18) & + MISS_TID2_SM_L2(19) ) , STD_ULOGIC_VECTOR'("0000000000000000000")); +MQQ164:IU2_SM_2_PT(8) <= + Eq(( RELD_R1_TID_L2(2) & MISS_TID2_SM_L2(0) & + MISS_TID2_SM_L2(1) & MISS_TID2_SM_L2(2) & + MISS_TID2_SM_L2(3) & MISS_TID2_SM_L2(4) & + MISS_TID2_SM_L2(5) & MISS_TID2_SM_L2(7) & + MISS_TID2_SM_L2(8) & MISS_TID2_SM_L2(9) & + MISS_TID2_SM_L2(10) & MISS_TID2_SM_L2(11) & + MISS_TID2_SM_L2(13) & MISS_TID2_SM_L2(14) & + MISS_TID2_SM_L2(15) & MISS_TID2_SM_L2(16) & + MISS_TID2_SM_L2(18) & MISS_TID2_SM_L2(19) + ) , STD_ULOGIC_VECTOR'("100000000000000000")); +MQQ165:IU2_SM_2_PT(9) <= + Eq(( RELD_R1_TID_L2(2) & MISS_TID2_SM_L2(0) & + MISS_TID2_SM_L2(1) & MISS_TID2_SM_L2(2) & + MISS_TID2_SM_L2(3) & MISS_TID2_SM_L2(4) & + MISS_TID2_SM_L2(5) & MISS_TID2_SM_L2(6) & + MISS_TID2_SM_L2(7) & MISS_TID2_SM_L2(8) & + MISS_TID2_SM_L2(9) & MISS_TID2_SM_L2(10) & + MISS_TID2_SM_L2(11) & MISS_TID2_SM_L2(12) & + MISS_TID2_SM_L2(13) & MISS_TID2_SM_L2(15) & + MISS_TID2_SM_L2(16) & MISS_TID2_SM_L2(17) & + MISS_TID2_SM_L2(18) ) , STD_ULOGIC_VECTOR'("0000000000000000000")); +MQQ166:IU2_SM_2_PT(10) <= + Eq(( RELD_R1_TID_L2(2) & MISS_TID2_SM_L2(0) & + MISS_TID2_SM_L2(1) & MISS_TID2_SM_L2(2) & + MISS_TID2_SM_L2(3) & MISS_TID2_SM_L2(4) & + MISS_TID2_SM_L2(5) & MISS_TID2_SM_L2(7) & + MISS_TID2_SM_L2(8) & MISS_TID2_SM_L2(9) & + MISS_TID2_SM_L2(10) & MISS_TID2_SM_L2(11) & + MISS_TID2_SM_L2(12) & MISS_TID2_SM_L2(13) & + MISS_TID2_SM_L2(15) & MISS_TID2_SM_L2(16) & + MISS_TID2_SM_L2(17) & MISS_TID2_SM_L2(18) + ) , STD_ULOGIC_VECTOR'("100000000000000000")); +MQQ167:IU2_SM_2_PT(11) <= + Eq(( MISS_TID2_SM_L2(18) ) , STD_ULOGIC'('1')); +MQQ168:IU2_SM_2_PT(12) <= + Eq(( MISS_TID2_SM_L2(16) ) , STD_ULOGIC'('1')); +MQQ169:IU2_SM_2_PT(13) <= + Eq(( RELD_R1_TID_L2(2) & MISS_TID2_SM_L2(15) + ) , STD_ULOGIC_VECTOR'("01")); +MQQ170:IU2_SM_2_PT(14) <= + Eq(( RELD_R1_TID_L2(2) & MISS_TID2_SM_L2(15) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ171:IU2_SM_2_PT(15) <= + Eq(( RELD_R1_TID_L2(2) & MISS_TID2_SM_L2(13) + ) , STD_ULOGIC_VECTOR'("01")); +MQQ172:IU2_SM_2_PT(16) <= + Eq(( RELD_R1_TID_L2(2) & MISS_TID2_SM_L2(13) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ173:IU2_SM_2_PT(17) <= + Eq(( MISS_TID2_SM_L2(0) & MISS_TID2_SM_L2(1) & + MISS_TID2_SM_L2(2) & MISS_TID2_SM_L2(6) & + MISS_TID2_SM_L2(7) & MISS_TID2_SM_L2(11) + ) , STD_ULOGIC_VECTOR'("000000")); +MQQ174:IU2_SM_2_PT(18) <= + Eq(( ERAT_ERR(2) & MISS_TID2_SM_L2(0) & + MISS_TID2_SM_L2(6) & MISS_TID2_SM_L2(7) & + MISS_TID2_SM_L2(11) ) , STD_ULOGIC_VECTOR'("00000")); +MQQ175:IU2_SM_2_PT(19) <= + Eq(( ECC_ERR(2) & MISS_TID2_SM_L2(11) + ) , STD_ULOGIC_VECTOR'("01")); +MQQ176:IU2_SM_2_PT(20) <= + Eq(( ECC_ERR(2) & MISS_TID2_SM_L2(11) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ177:IU2_SM_2_PT(21) <= + Eq(( MISS_TID2_SM_L2(10) ) , STD_ULOGIC'('1')); +MQQ178:IU2_SM_2_PT(22) <= + Eq(( MISS_TID2_SM_L2(8) ) , STD_ULOGIC'('1')); +MQQ179:IU2_SM_2_PT(23) <= + Eq(( ECC_ERR(2) & MISS_TID2_SM_L2(0) & + MISS_TID2_SM_L2(1) & MISS_TID2_SM_L2(2) & + MISS_TID2_SM_L2(7) ) , STD_ULOGIC_VECTOR'("10000")); +MQQ180:IU2_SM_2_PT(24) <= + Eq(( MISS_FLUSHED2_L2 & MISS_TID2_SM_L2(7) + ) , STD_ULOGIC_VECTOR'("01")); +MQQ181:IU2_SM_2_PT(25) <= + Eq(( ECC_ERR(2) & ECC_ERR_UE(2) & + MISS_FLUSHED2_L2 & MISS_INVAL2_L2 & + MISS_TID2_SM_L2(6) ) , STD_ULOGIC_VECTOR'("00001")); +MQQ182:IU2_SM_2_PT(26) <= + Eq(( MISS_FLUSHED2_L2 & MISS_INVAL2_L2 & + MISS_TID2_SM_L2(6) ) , STD_ULOGIC_VECTOR'("001")); +MQQ183:IU2_SM_2_PT(27) <= + Eq(( MISS_INVAL2_L2 & MISS_TID2_SM_L2(6) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ184:IU2_SM_2_PT(28) <= + Eq(( MISS_FLUSHED2_L2 & MISS_TID2_SM_L2(6) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ185:IU2_SM_2_PT(29) <= + Eq(( ECC_ERR_UE(2) & MISS_TID2_SM_L2(6) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ186:IU2_SM_2_PT(30) <= + Eq(( RELD_R1_TID_L2(2) & SPR_IC_CLS_L2 & + MISS_TID2_SM_L2(5) ) , STD_ULOGIC_VECTOR'("001")); +MQQ187:IU2_SM_2_PT(31) <= + Eq(( RELD_R1_TID_L2(2) & SPR_IC_CLS_L2 & + MISS_TID2_SM_L2(5) ) , STD_ULOGIC_VECTOR'("101")); +MQQ188:IU2_SM_2_PT(32) <= + Eq(( RELD_R1_TID_L2(2) & SPR_IC_CLS_L2 & + MISS_TID2_SM_L2(5) ) , STD_ULOGIC_VECTOR'("011")); +MQQ189:IU2_SM_2_PT(33) <= + Eq(( RELD_R1_TID_L2(2) & SPR_IC_CLS_L2 & + MISS_TID2_SM_L2(5) ) , STD_ULOGIC_VECTOR'("111")); +MQQ190:IU2_SM_2_PT(34) <= + Eq(( MISS_FLUSHED2_L2 & MISS_INVAL2_L2 & + MISS_TID2_SM_L2(3) ) , STD_ULOGIC_VECTOR'("001")); +MQQ191:IU2_SM_2_PT(35) <= + Eq(( RELD_R1_TID_L2(2) & MISS_TID2_SM_L2(3) + ) , STD_ULOGIC_VECTOR'("01")); +MQQ192:IU2_SM_2_PT(36) <= + Eq(( RELD_R1_TID_L2(2) & MISS_TID2_SM_L2(3) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ193:IU2_SM_2_PT(37) <= + Eq(( ERAT_ERR(2) & ICS_ICM_IU2_FLUSH_TID(2) & + RELEASE_SM & MISS_TID2_SM_L2(2) + ) , STD_ULOGIC_VECTOR'("0001")); +MQQ194:IU2_SM_2_PT(38) <= + Eq(( RELEASE_SM & MISS_TID2_SM_L2(2) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ195:IU2_SM_2_PT(39) <= + Eq(( ERAT_ERR(2) & MISS_TID2_SM_L2(2) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ196:IU2_SM_2_PT(40) <= + Eq(( ERAT_ERR(2) & RELD_R1_TID_L2(2) & + MISS_TID2_SM_L2(1) ) , STD_ULOGIC_VECTOR'("001")); +MQQ197:IU2_SM_2_PT(41) <= + Eq(( ERAT_ERR(2) & MISS_CI2_L2 & + RELD_R1_TID_L2(2) & MISS_TID2_SM_L2(1) + ) , STD_ULOGIC_VECTOR'("0011")); +MQQ198:IU2_SM_2_PT(42) <= + Eq(( ERAT_ERR(2) & MISS_CI2_L2 & + RELD_R1_TID_L2(2) & MISS_TID2_SM_L2(1) + ) , STD_ULOGIC_VECTOR'("0111")); +MQQ199:IU2_SM_2_PT(43) <= + Eq(( ERAT_ERR(2) & MISS_TID2_SM_L2(1) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ200:IU2_SM_2_PT(44) <= + Eq(( ICD_ICM_MISS & ICD_ICM_TID(2) & + ICD_ICM_WIMGE(1) & ADDR_MATCH & + ICS_ICM_IU2_FLUSH_TID(2) & RELEASE_SM & + MISS_TID2_SM_L2(0) ) , STD_ULOGIC_VECTOR'("1101001")); +MQQ201:IU2_SM_2_PT(45) <= + Eq(( ICD_ICM_WIMGE(1) & ADDR_MATCH & + RELEASE_SM & MISS_TID2_SM_L2(0) + ) , STD_ULOGIC_VECTOR'("0111")); +MQQ202:IU2_SM_2_PT(46) <= + Eq(( ICD_ICM_MISS & ICD_ICM_TID(2) & + ADDR_MATCH & ICS_ICM_IU2_FLUSH_TID(2) & + MISS_TID2_SM_L2(0) ) , STD_ULOGIC_VECTOR'("11001")); +MQQ203:IU2_SM_2_PT(47) <= + Eq(( ICD_ICM_MISS & ICD_ICM_TID(2) & + ICD_ICM_WIMGE(1) & ICS_ICM_IU2_FLUSH_TID(2) & + MISS_TID2_SM_L2(0) ) , STD_ULOGIC_VECTOR'("11101")); +MQQ204:IU2_SM_2_PT(48) <= + Eq(( ICD_ICM_TID(2) & MISS_TID2_SM_L2(0) + ) , STD_ULOGIC_VECTOR'("01")); +MQQ205:IU2_SM_2_PT(49) <= + Eq(( ICD_ICM_MISS & MISS_TID2_SM_L2(0) + ) , STD_ULOGIC_VECTOR'("01")); +MQQ206:MISS_TID2_SM_D(0) <= + (IU2_SM_2_PT(1) OR IU2_SM_2_PT(19) + OR IU2_SM_2_PT(38) OR IU2_SM_2_PT(39) + OR IU2_SM_2_PT(43) OR IU2_SM_2_PT(45) + OR IU2_SM_2_PT(48) OR IU2_SM_2_PT(49) + ); +MQQ207:MISS_TID2_SM_D(1) <= + (IU2_SM_2_PT(20) OR IU2_SM_2_PT(40) + OR IU2_SM_2_PT(46) OR IU2_SM_2_PT(47) + ); +MQQ208:MISS_TID2_SM_D(2) <= + (IU2_SM_2_PT(37) OR IU2_SM_2_PT(44) + ); +MQQ209:MISS_TID2_SM_D(3) <= + (IU2_SM_2_PT(41)); +MQQ210:MISS_TID2_SM_D(4) <= + (IU2_SM_2_PT(22) OR IU2_SM_2_PT(36) + ); +MQQ211:MISS_TID2_SM_D(5) <= + (IU2_SM_2_PT(4)); +MQQ212:MISS_TID2_SM_D(6) <= + (IU2_SM_2_PT(14) OR IU2_SM_2_PT(21) + OR IU2_SM_2_PT(31)); +MQQ213:MISS_TID2_SM_D(7) <= + (IU2_SM_2_PT(42)); +MQQ214:MISS_TID2_SM_D(8) <= + (IU2_SM_2_PT(35)); +MQQ215:MISS_TID2_SM_D(9) <= + (IU2_SM_2_PT(3)); +MQQ216:MISS_TID2_SM_D(10) <= + (IU2_SM_2_PT(13) OR IU2_SM_2_PT(30) + ); +MQQ217:MISS_TID2_SM_D(11) <= + (IU2_SM_2_PT(2)); +MQQ218:MISS_TID2_SM_D(12) <= + (IU2_SM_2_PT(12) OR IU2_SM_2_PT(33) + ); +MQQ219:MISS_TID2_SM_D(13) <= + (IU2_SM_2_PT(8)); +MQQ220:MISS_TID2_SM_D(14) <= + (IU2_SM_2_PT(11) OR IU2_SM_2_PT(16) + ); +MQQ221:MISS_TID2_SM_D(15) <= + (IU2_SM_2_PT(10)); +MQQ222:MISS_TID2_SM_D(16) <= + (IU2_SM_2_PT(32)); +MQQ223:MISS_TID2_SM_D(17) <= + (IU2_SM_2_PT(7)); +MQQ224:MISS_TID2_SM_D(18) <= + (IU2_SM_2_PT(15)); +MQQ225:MISS_TID2_SM_D(19) <= + (IU2_SM_2_PT(9)); +MQQ226:RESET_STATE(2) <= + (IU2_SM_2_PT(19) OR IU2_SM_2_PT(43) + ); +MQQ227:REQUEST_TID(2) <= + (IU2_SM_2_PT(46) OR IU2_SM_2_PT(47) + ); +MQQ228:WRITE_DIR_INVAL(2) <= + (IU2_SM_2_PT(34)); +MQQ229:WRITE_DIR_VAL(2) <= + (IU2_SM_2_PT(25)); +MQQ230:HOLD_TID(2) <= + (IU2_SM_2_PT(17) OR IU2_SM_2_PT(18) + OR IU2_SM_2_PT(23) OR IU2_SM_2_PT(27) + OR IU2_SM_2_PT(28) OR IU2_SM_2_PT(29) + ); +MQQ231:DATA_WRITE(2) <= + (IU2_SM_2_PT(5) OR IU2_SM_2_PT(26) + ); +MQQ232:DIR_WRITE(2) <= + (IU2_SM_2_PT(5)); +MQQ233:LOAD_TID(2) <= + (IU2_SM_2_PT(6) OR IU2_SM_2_PT(24) + ); +MQQ234:RELEASE_SM_HOLD(2) <= + (IU2_SM_2_PT(2) OR IU2_SM_2_PT(19) + OR IU2_SM_2_PT(43)); + +MQQ235:IU2_SM_3_PT(1) <= + Eq(( ICS_ICM_IU2_FLUSH_TID(3) & MISS_TID3_SM_L2(1) & + MISS_TID3_SM_L2(3) & MISS_TID3_SM_L2(4) & + MISS_TID3_SM_L2(5) & MISS_TID3_SM_L2(6) & + MISS_TID3_SM_L2(7) & MISS_TID3_SM_L2(8) & + MISS_TID3_SM_L2(9) & MISS_TID3_SM_L2(10) & + MISS_TID3_SM_L2(11) & MISS_TID3_SM_L2(12) & + MISS_TID3_SM_L2(13) & MISS_TID3_SM_L2(14) & + MISS_TID3_SM_L2(15) & MISS_TID3_SM_L2(16) & + MISS_TID3_SM_L2(17) & MISS_TID3_SM_L2(18) & + MISS_TID3_SM_L2(19) ) , STD_ULOGIC_VECTOR'("1000000000000000000")); +MQQ236:IU2_SM_3_PT(2) <= + Eq(( MISS_TID3_SM_L2(0) & MISS_TID3_SM_L2(1) & + MISS_TID3_SM_L2(2) & MISS_TID3_SM_L2(3) & + MISS_TID3_SM_L2(4) & MISS_TID3_SM_L2(5) & + MISS_TID3_SM_L2(8) & MISS_TID3_SM_L2(9) & + MISS_TID3_SM_L2(10) & MISS_TID3_SM_L2(11) & + MISS_TID3_SM_L2(12) & MISS_TID3_SM_L2(13) & + MISS_TID3_SM_L2(14) & MISS_TID3_SM_L2(15) & + MISS_TID3_SM_L2(16) & MISS_TID3_SM_L2(17) & + MISS_TID3_SM_L2(18) & MISS_TID3_SM_L2(19) + ) , STD_ULOGIC_VECTOR'("000000000000000000")); +MQQ237:IU2_SM_3_PT(3) <= + Eq(( RELD_R1_TID_L2(3) & MISS_TID3_SM_L2(0) & + MISS_TID3_SM_L2(1) & MISS_TID3_SM_L2(2) & + MISS_TID3_SM_L2(3) & MISS_TID3_SM_L2(5) & + MISS_TID3_SM_L2(6) & MISS_TID3_SM_L2(7) & + MISS_TID3_SM_L2(8) & MISS_TID3_SM_L2(10) & + MISS_TID3_SM_L2(11) & MISS_TID3_SM_L2(12) & + MISS_TID3_SM_L2(13) & MISS_TID3_SM_L2(14) & + MISS_TID3_SM_L2(15) & MISS_TID3_SM_L2(16) & + MISS_TID3_SM_L2(17) & MISS_TID3_SM_L2(18) & + MISS_TID3_SM_L2(19) ) , STD_ULOGIC_VECTOR'("0000000000000000000")); +MQQ238:IU2_SM_3_PT(4) <= + Eq(( RELD_R1_TID_L2(3) & MISS_TID3_SM_L2(0) & + MISS_TID3_SM_L2(1) & MISS_TID3_SM_L2(2) & + MISS_TID3_SM_L2(3) & MISS_TID3_SM_L2(5) & + MISS_TID3_SM_L2(7) & MISS_TID3_SM_L2(8) & + MISS_TID3_SM_L2(10) & MISS_TID3_SM_L2(11) & + MISS_TID3_SM_L2(12) & MISS_TID3_SM_L2(13) & + MISS_TID3_SM_L2(14) & MISS_TID3_SM_L2(15) & + MISS_TID3_SM_L2(16) & MISS_TID3_SM_L2(17) & + MISS_TID3_SM_L2(18) & MISS_TID3_SM_L2(19) + ) , STD_ULOGIC_VECTOR'("100000000000000000")); +MQQ239:IU2_SM_3_PT(5) <= + Eq(( MISS_FLUSHED3_L2 & MISS_INVAL3_L2 & + MISS_TID3_SM_L2(0) & MISS_TID3_SM_L2(1) & + MISS_TID3_SM_L2(2) & MISS_TID3_SM_L2(6) & + MISS_TID3_SM_L2(7) & MISS_TID3_SM_L2(8) & + MISS_TID3_SM_L2(9) & MISS_TID3_SM_L2(10) & + MISS_TID3_SM_L2(11) & MISS_TID3_SM_L2(16) & + MISS_TID3_SM_L2(17) & MISS_TID3_SM_L2(18) & + MISS_TID3_SM_L2(19) ) , STD_ULOGIC_VECTOR'("000000000000000")); +MQQ240:IU2_SM_3_PT(6) <= + Eq(( R2_CRIT_QW_L2 & MISS_FLUSHED3_L2 & + MISS_TID3_SM_L2(0) & MISS_TID3_SM_L2(1) & + MISS_TID3_SM_L2(2) & MISS_TID3_SM_L2(8) & + MISS_TID3_SM_L2(9) & MISS_TID3_SM_L2(10) & + MISS_TID3_SM_L2(11) & MISS_TID3_SM_L2(16) & + MISS_TID3_SM_L2(17) & MISS_TID3_SM_L2(18) & + MISS_TID3_SM_L2(19) ) , STD_ULOGIC_VECTOR'("1000000000000")); +MQQ241:IU2_SM_3_PT(7) <= + Eq(( RELD_R1_TID_L2(3) & MISS_TID3_SM_L2(0) & + MISS_TID3_SM_L2(1) & MISS_TID3_SM_L2(2) & + MISS_TID3_SM_L2(3) & MISS_TID3_SM_L2(4) & + MISS_TID3_SM_L2(5) & MISS_TID3_SM_L2(6) & + MISS_TID3_SM_L2(7) & MISS_TID3_SM_L2(8) & + MISS_TID3_SM_L2(9) & MISS_TID3_SM_L2(10) & + MISS_TID3_SM_L2(11) & MISS_TID3_SM_L2(13) & + MISS_TID3_SM_L2(14) & MISS_TID3_SM_L2(15) & + MISS_TID3_SM_L2(16) & MISS_TID3_SM_L2(18) & + MISS_TID3_SM_L2(19) ) , STD_ULOGIC_VECTOR'("0000000000000000000")); +MQQ242:IU2_SM_3_PT(8) <= + Eq(( RELD_R1_TID_L2(3) & MISS_TID3_SM_L2(0) & + MISS_TID3_SM_L2(1) & MISS_TID3_SM_L2(2) & + MISS_TID3_SM_L2(3) & MISS_TID3_SM_L2(4) & + MISS_TID3_SM_L2(5) & MISS_TID3_SM_L2(7) & + MISS_TID3_SM_L2(8) & MISS_TID3_SM_L2(9) & + MISS_TID3_SM_L2(10) & MISS_TID3_SM_L2(11) & + MISS_TID3_SM_L2(13) & MISS_TID3_SM_L2(14) & + MISS_TID3_SM_L2(15) & MISS_TID3_SM_L2(16) & + MISS_TID3_SM_L2(18) & MISS_TID3_SM_L2(19) + ) , STD_ULOGIC_VECTOR'("100000000000000000")); +MQQ243:IU2_SM_3_PT(9) <= + Eq(( RELD_R1_TID_L2(3) & MISS_TID3_SM_L2(0) & + MISS_TID3_SM_L2(1) & MISS_TID3_SM_L2(2) & + MISS_TID3_SM_L2(3) & MISS_TID3_SM_L2(4) & + MISS_TID3_SM_L2(5) & MISS_TID3_SM_L2(6) & + MISS_TID3_SM_L2(7) & MISS_TID3_SM_L2(8) & + MISS_TID3_SM_L2(9) & MISS_TID3_SM_L2(10) & + MISS_TID3_SM_L2(11) & MISS_TID3_SM_L2(12) & + MISS_TID3_SM_L2(13) & MISS_TID3_SM_L2(15) & + MISS_TID3_SM_L2(16) & MISS_TID3_SM_L2(17) & + MISS_TID3_SM_L2(18) ) , STD_ULOGIC_VECTOR'("0000000000000000000")); +MQQ244:IU2_SM_3_PT(10) <= + Eq(( RELD_R1_TID_L2(3) & MISS_TID3_SM_L2(0) & + MISS_TID3_SM_L2(1) & MISS_TID3_SM_L2(2) & + MISS_TID3_SM_L2(3) & MISS_TID3_SM_L2(4) & + MISS_TID3_SM_L2(5) & MISS_TID3_SM_L2(7) & + MISS_TID3_SM_L2(8) & MISS_TID3_SM_L2(9) & + MISS_TID3_SM_L2(10) & MISS_TID3_SM_L2(11) & + MISS_TID3_SM_L2(12) & MISS_TID3_SM_L2(13) & + MISS_TID3_SM_L2(15) & MISS_TID3_SM_L2(16) & + MISS_TID3_SM_L2(17) & MISS_TID3_SM_L2(18) + ) , STD_ULOGIC_VECTOR'("100000000000000000")); +MQQ245:IU2_SM_3_PT(11) <= + Eq(( MISS_TID3_SM_L2(18) ) , STD_ULOGIC'('1')); +MQQ246:IU2_SM_3_PT(12) <= + Eq(( MISS_TID3_SM_L2(16) ) , STD_ULOGIC'('1')); +MQQ247:IU2_SM_3_PT(13) <= + Eq(( RELD_R1_TID_L2(3) & MISS_TID3_SM_L2(15) + ) , STD_ULOGIC_VECTOR'("01")); +MQQ248:IU2_SM_3_PT(14) <= + Eq(( RELD_R1_TID_L2(3) & MISS_TID3_SM_L2(15) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ249:IU2_SM_3_PT(15) <= + Eq(( RELD_R1_TID_L2(3) & MISS_TID3_SM_L2(13) + ) , STD_ULOGIC_VECTOR'("01")); +MQQ250:IU2_SM_3_PT(16) <= + Eq(( RELD_R1_TID_L2(3) & MISS_TID3_SM_L2(13) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ251:IU2_SM_3_PT(17) <= + Eq(( MISS_TID3_SM_L2(0) & MISS_TID3_SM_L2(1) & + MISS_TID3_SM_L2(2) & MISS_TID3_SM_L2(6) & + MISS_TID3_SM_L2(7) & MISS_TID3_SM_L2(11) + ) , STD_ULOGIC_VECTOR'("000000")); +MQQ252:IU2_SM_3_PT(18) <= + Eq(( ERAT_ERR(3) & MISS_TID3_SM_L2(0) & + MISS_TID3_SM_L2(6) & MISS_TID3_SM_L2(7) & + MISS_TID3_SM_L2(11) ) , STD_ULOGIC_VECTOR'("00000")); +MQQ253:IU2_SM_3_PT(19) <= + Eq(( ECC_ERR(3) & MISS_TID3_SM_L2(11) + ) , STD_ULOGIC_VECTOR'("01")); +MQQ254:IU2_SM_3_PT(20) <= + Eq(( ECC_ERR(3) & MISS_TID3_SM_L2(11) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ255:IU2_SM_3_PT(21) <= + Eq(( MISS_TID3_SM_L2(10) ) , STD_ULOGIC'('1')); +MQQ256:IU2_SM_3_PT(22) <= + Eq(( MISS_TID3_SM_L2(8) ) , STD_ULOGIC'('1')); +MQQ257:IU2_SM_3_PT(23) <= + Eq(( ECC_ERR(3) & MISS_TID3_SM_L2(0) & + MISS_TID3_SM_L2(1) & MISS_TID3_SM_L2(2) & + MISS_TID3_SM_L2(7) ) , STD_ULOGIC_VECTOR'("10000")); +MQQ258:IU2_SM_3_PT(24) <= + Eq(( MISS_FLUSHED3_L2 & MISS_TID3_SM_L2(7) + ) , STD_ULOGIC_VECTOR'("01")); +MQQ259:IU2_SM_3_PT(25) <= + Eq(( ECC_ERR(3) & ECC_ERR_UE(3) & + MISS_FLUSHED3_L2 & MISS_INVAL3_L2 & + MISS_TID3_SM_L2(6) ) , STD_ULOGIC_VECTOR'("00001")); +MQQ260:IU2_SM_3_PT(26) <= + Eq(( MISS_FLUSHED3_L2 & MISS_INVAL3_L2 & + MISS_TID3_SM_L2(6) ) , STD_ULOGIC_VECTOR'("001")); +MQQ261:IU2_SM_3_PT(27) <= + Eq(( MISS_INVAL3_L2 & MISS_TID3_SM_L2(6) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ262:IU2_SM_3_PT(28) <= + Eq(( MISS_FLUSHED3_L2 & MISS_TID3_SM_L2(6) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ263:IU2_SM_3_PT(29) <= + Eq(( ECC_ERR_UE(3) & MISS_TID3_SM_L2(6) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ264:IU2_SM_3_PT(30) <= + Eq(( RELD_R1_TID_L2(3) & SPR_IC_CLS_L2 & + MISS_TID3_SM_L2(5) ) , STD_ULOGIC_VECTOR'("001")); +MQQ265:IU2_SM_3_PT(31) <= + Eq(( RELD_R1_TID_L2(3) & SPR_IC_CLS_L2 & + MISS_TID3_SM_L2(5) ) , STD_ULOGIC_VECTOR'("101")); +MQQ266:IU2_SM_3_PT(32) <= + Eq(( RELD_R1_TID_L2(3) & SPR_IC_CLS_L2 & + MISS_TID3_SM_L2(5) ) , STD_ULOGIC_VECTOR'("011")); +MQQ267:IU2_SM_3_PT(33) <= + Eq(( RELD_R1_TID_L2(3) & SPR_IC_CLS_L2 & + MISS_TID3_SM_L2(5) ) , STD_ULOGIC_VECTOR'("111")); +MQQ268:IU2_SM_3_PT(34) <= + Eq(( MISS_FLUSHED3_L2 & MISS_INVAL3_L2 & + MISS_TID3_SM_L2(3) ) , STD_ULOGIC_VECTOR'("001")); +MQQ269:IU2_SM_3_PT(35) <= + Eq(( RELD_R1_TID_L2(3) & MISS_TID3_SM_L2(3) + ) , STD_ULOGIC_VECTOR'("01")); +MQQ270:IU2_SM_3_PT(36) <= + Eq(( RELD_R1_TID_L2(3) & MISS_TID3_SM_L2(3) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ271:IU2_SM_3_PT(37) <= + Eq(( ERAT_ERR(3) & ICS_ICM_IU2_FLUSH_TID(3) & + RELEASE_SM & MISS_TID3_SM_L2(2) + ) , STD_ULOGIC_VECTOR'("0001")); +MQQ272:IU2_SM_3_PT(38) <= + Eq(( RELEASE_SM & MISS_TID3_SM_L2(2) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ273:IU2_SM_3_PT(39) <= + Eq(( ERAT_ERR(3) & MISS_TID3_SM_L2(2) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ274:IU2_SM_3_PT(40) <= + Eq(( ERAT_ERR(3) & RELD_R1_TID_L2(3) & + MISS_TID3_SM_L2(1) ) , STD_ULOGIC_VECTOR'("001")); +MQQ275:IU2_SM_3_PT(41) <= + Eq(( ERAT_ERR(3) & MISS_CI3_L2 & + RELD_R1_TID_L2(3) & MISS_TID3_SM_L2(1) + ) , STD_ULOGIC_VECTOR'("0011")); +MQQ276:IU2_SM_3_PT(42) <= + Eq(( ERAT_ERR(3) & MISS_CI3_L2 & + RELD_R1_TID_L2(3) & MISS_TID3_SM_L2(1) + ) , STD_ULOGIC_VECTOR'("0111")); +MQQ277:IU2_SM_3_PT(43) <= + Eq(( ERAT_ERR(3) & MISS_TID3_SM_L2(1) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ278:IU2_SM_3_PT(44) <= + Eq(( ICD_ICM_MISS & ICD_ICM_TID(3) & + ICD_ICM_WIMGE(1) & ADDR_MATCH & + ICS_ICM_IU2_FLUSH_TID(3) & RELEASE_SM & + MISS_TID3_SM_L2(0) ) , STD_ULOGIC_VECTOR'("1101001")); +MQQ279:IU2_SM_3_PT(45) <= + Eq(( ICD_ICM_WIMGE(1) & ADDR_MATCH & + RELEASE_SM & MISS_TID3_SM_L2(0) + ) , STD_ULOGIC_VECTOR'("0111")); +MQQ280:IU2_SM_3_PT(46) <= + Eq(( ICD_ICM_MISS & ICD_ICM_TID(3) & + ADDR_MATCH & ICS_ICM_IU2_FLUSH_TID(3) & + MISS_TID3_SM_L2(0) ) , STD_ULOGIC_VECTOR'("11001")); +MQQ281:IU2_SM_3_PT(47) <= + Eq(( ICD_ICM_MISS & ICD_ICM_TID(3) & + ICD_ICM_WIMGE(1) & ICS_ICM_IU2_FLUSH_TID(3) & + MISS_TID3_SM_L2(0) ) , STD_ULOGIC_VECTOR'("11101")); +MQQ282:IU2_SM_3_PT(48) <= + Eq(( ICD_ICM_TID(3) & MISS_TID3_SM_L2(0) + ) , STD_ULOGIC_VECTOR'("01")); +MQQ283:IU2_SM_3_PT(49) <= + Eq(( ICD_ICM_MISS & MISS_TID3_SM_L2(0) + ) , STD_ULOGIC_VECTOR'("01")); +MQQ284:MISS_TID3_SM_D(0) <= + (IU2_SM_3_PT(1) OR IU2_SM_3_PT(19) + OR IU2_SM_3_PT(38) OR IU2_SM_3_PT(39) + OR IU2_SM_3_PT(43) OR IU2_SM_3_PT(45) + OR IU2_SM_3_PT(48) OR IU2_SM_3_PT(49) + ); +MQQ285:MISS_TID3_SM_D(1) <= + (IU2_SM_3_PT(20) OR IU2_SM_3_PT(40) + OR IU2_SM_3_PT(46) OR IU2_SM_3_PT(47) + ); +MQQ286:MISS_TID3_SM_D(2) <= + (IU2_SM_3_PT(37) OR IU2_SM_3_PT(44) + ); +MQQ287:MISS_TID3_SM_D(3) <= + (IU2_SM_3_PT(41)); +MQQ288:MISS_TID3_SM_D(4) <= + (IU2_SM_3_PT(22) OR IU2_SM_3_PT(36) + ); +MQQ289:MISS_TID3_SM_D(5) <= + (IU2_SM_3_PT(4)); +MQQ290:MISS_TID3_SM_D(6) <= + (IU2_SM_3_PT(14) OR IU2_SM_3_PT(21) + OR IU2_SM_3_PT(31)); +MQQ291:MISS_TID3_SM_D(7) <= + (IU2_SM_3_PT(42)); +MQQ292:MISS_TID3_SM_D(8) <= + (IU2_SM_3_PT(35)); +MQQ293:MISS_TID3_SM_D(9) <= + (IU2_SM_3_PT(3)); +MQQ294:MISS_TID3_SM_D(10) <= + (IU2_SM_3_PT(13) OR IU2_SM_3_PT(30) + ); +MQQ295:MISS_TID3_SM_D(11) <= + (IU2_SM_3_PT(2)); +MQQ296:MISS_TID3_SM_D(12) <= + (IU2_SM_3_PT(12) OR IU2_SM_3_PT(33) + ); +MQQ297:MISS_TID3_SM_D(13) <= + (IU2_SM_3_PT(8)); +MQQ298:MISS_TID3_SM_D(14) <= + (IU2_SM_3_PT(11) OR IU2_SM_3_PT(16) + ); +MQQ299:MISS_TID3_SM_D(15) <= + (IU2_SM_3_PT(10)); +MQQ300:MISS_TID3_SM_D(16) <= + (IU2_SM_3_PT(32)); +MQQ301:MISS_TID3_SM_D(17) <= + (IU2_SM_3_PT(7)); +MQQ302:MISS_TID3_SM_D(18) <= + (IU2_SM_3_PT(15)); +MQQ303:MISS_TID3_SM_D(19) <= + (IU2_SM_3_PT(9)); +MQQ304:RESET_STATE(3) <= + (IU2_SM_3_PT(19) OR IU2_SM_3_PT(43) + ); +MQQ305:REQUEST_TID(3) <= + (IU2_SM_3_PT(46) OR IU2_SM_3_PT(47) + ); +MQQ306:WRITE_DIR_INVAL(3) <= + (IU2_SM_3_PT(34)); +MQQ307:WRITE_DIR_VAL(3) <= + (IU2_SM_3_PT(25)); +MQQ308:HOLD_TID(3) <= + (IU2_SM_3_PT(17) OR IU2_SM_3_PT(18) + OR IU2_SM_3_PT(23) OR IU2_SM_3_PT(27) + OR IU2_SM_3_PT(28) OR IU2_SM_3_PT(29) + ); +MQQ309:DATA_WRITE(3) <= + (IU2_SM_3_PT(5) OR IU2_SM_3_PT(26) + ); +MQQ310:DIR_WRITE(3) <= + (IU2_SM_3_PT(5)); +MQQ311:LOAD_TID(3) <= + (IU2_SM_3_PT(6) OR IU2_SM_3_PT(24) + ); +MQQ312:RELEASE_SM_HOLD(3) <= + (IU2_SM_3_PT(2) OR IU2_SM_3_PT(19) + OR IU2_SM_3_PT(43)); + +load_quiesce(0) <= miss_tid0_sm_l2(0); +load_quiesce(1) <= miss_tid1_sm_l2(0); +load_quiesce(2) <= miss_tid2_sm_l2(0); +load_quiesce(3) <= miss_tid3_sm_l2(0); +ic_fdep_load_quiesce <= load_quiesce; +iu_mm_lmq_empty <= and_reduce(load_quiesce); +miss_act(0) <= miss_tid0_sm_l2(0) and icd_icm_any_iu2_valid and icd_icm_tid(0); +miss_addr0_real_d <= icd_icm_addr_real; +miss_addr0_eff_d <= icd_icm_addr_eff; +miss_ci0_d <= icd_icm_wimge(1); +miss_endian0_d <= icd_icm_wimge(4); +miss_2ucode0_d <= icd_icm_2ucode; +miss_2ucode0_type_d <= icd_icm_2ucode_type; +set_flush_occurred(0) <= (xu_iu_flush(0) or bp_ic_iu5_redirect_tid(0)) and not miss_tid0_sm_l2(0) and not miss_tid0_sm_l2(2); +miss_flush_occurred0_d <= '0' when reset_state(0) = '1' + else '1' when set_flush_occurred(0) = '1' + else miss_flush_occurred0_l2; +flush_addr_outside_range(0) <= ics_icm_iu0_ifar0 /= (miss_addr0_eff_l2(46 to 51) & miss_addr0_real_l2(52)); +set_flushed(0) <= miss_flush_occurred0_l2 and flush_addr_outside_range(0) and reld_r1_tid_l2(0) and (miss_tid0_sm_l2(1) or miss_tid0_sm_l2(11)); +miss_flushed0_d <= '0' when reset_state(0) = '1' + else '1' when set_flushed(0) = '1' + else miss_flushed0_l2; +inval_equal(0) <= icd_icm_iu2_inval and addr_equal(0); +set_invalidated(0) <= (inval_equal(0) or icd_icm_ici) and not miss_tid0_sm_l2(0) and not miss_tid0_sm_l2(2) and not miss_ci0_l2; +miss_inval0_d <= '0' when reset_state(0) = '1' + else '1' when set_invalidated(0) = '1' + else miss_inval0_l2; +sent_fp(0) <= reld_r3_tid_l2(0) and r3_loaded_l2 and not (an_ac_reld_ecc_err_l2 and not an_ac_reld_ecc_err_ue_l2); +set_block_fp(0) <= sent_fp(0) or + (ics_icm_iu3_flush_tid(0) and not (miss_tid0_sm_l2(0) or miss_tid0_sm_l2(2))); +miss_block_fp0_d <= '0' when reset_state(0) = '1' + else '1' when set_block_fp(0) = '1' + else miss_block_fp0_l2; +miss_ecc_err0_d <= '0' when (reset_state(0) or miss_tid0_sm_d(3) or miss_tid0_sm_d(7)) = '1' + else '1' when (new_ecc_err(0) and not miss_tid0_sm_l2(3) and not miss_tid0_sm_l2(7))= '1' + else miss_ecc_err0_l2; +miss_ecc_err_ue0_d <= '0' when (reset_state(0) or miss_tid0_sm_d(3) or miss_tid0_sm_d(7)) = '1' + else an_ac_reld_ecc_err_ue_l2 when new_ecc_err_ue(0) = '1' + else miss_ecc_err_ue0_l2; +miss_act(1) <= miss_tid1_sm_l2(0) and icd_icm_any_iu2_valid and icd_icm_tid(1); +miss_addr1_real_d <= icd_icm_addr_real; +miss_addr1_eff_d <= icd_icm_addr_eff; +miss_ci1_d <= icd_icm_wimge(1); +miss_endian1_d <= icd_icm_wimge(4); +miss_2ucode1_d <= icd_icm_2ucode; +miss_2ucode1_type_d <= icd_icm_2ucode_type; +set_flush_occurred(1) <= (xu_iu_flush(1) or bp_ic_iu5_redirect_tid(1)) and not miss_tid1_sm_l2(0) and not miss_tid1_sm_l2(2); +miss_flush_occurred1_d <= '0' when reset_state(1) = '1' + else '1' when set_flush_occurred(1) = '1' + else miss_flush_occurred1_l2; +flush_addr_outside_range(1) <= ics_icm_iu0_ifar1 /= (miss_addr1_eff_l2(46 to 51) & miss_addr1_real_l2(52)); +set_flushed(1) <= miss_flush_occurred1_l2 and flush_addr_outside_range(1) and reld_r1_tid_l2(1) and (miss_tid1_sm_l2(1) or miss_tid1_sm_l2(11)); +miss_flushed1_d <= '0' when reset_state(1) = '1' + else '1' when set_flushed(1) = '1' + else miss_flushed1_l2; +inval_equal(1) <= icd_icm_iu2_inval and addr_equal(1); +set_invalidated(1) <= (inval_equal(1) or icd_icm_ici) and not miss_tid1_sm_l2(0) and not miss_tid1_sm_l2(2) and not miss_ci1_l2; +miss_inval1_d <= '0' when reset_state(1) = '1' + else '1' when set_invalidated(1) = '1' + else miss_inval1_l2; +sent_fp(1) <= reld_r3_tid_l2(1) and r3_loaded_l2 and not (an_ac_reld_ecc_err_l2 and not an_ac_reld_ecc_err_ue_l2); +set_block_fp(1) <= sent_fp(1) or + (ics_icm_iu3_flush_tid(1) and not (miss_tid1_sm_l2(0) or miss_tid1_sm_l2(2))); +miss_block_fp1_d <= '0' when reset_state(1) = '1' + else '1' when set_block_fp(1) = '1' + else miss_block_fp1_l2; +miss_ecc_err1_d <= '0' when (reset_state(1) or miss_tid1_sm_d(3) or miss_tid1_sm_d(7)) = '1' + else '1' when (new_ecc_err(1) and not miss_tid1_sm_l2(3) and not miss_tid1_sm_l2(7))= '1' + else miss_ecc_err1_l2; +miss_ecc_err_ue1_d <= '0' when (reset_state(1) or miss_tid1_sm_d(3) or miss_tid1_sm_d(7)) = '1' + else an_ac_reld_ecc_err_ue_l2 when new_ecc_err_ue(1) = '1' + else miss_ecc_err_ue1_l2; +miss_act(2) <= miss_tid2_sm_l2(0) and icd_icm_any_iu2_valid and icd_icm_tid(2); +miss_addr2_real_d <= icd_icm_addr_real; +miss_addr2_eff_d <= icd_icm_addr_eff; +miss_ci2_d <= icd_icm_wimge(1); +miss_endian2_d <= icd_icm_wimge(4); +miss_2ucode2_d <= icd_icm_2ucode; +miss_2ucode2_type_d <= icd_icm_2ucode_type; +set_flush_occurred(2) <= (xu_iu_flush(2) or bp_ic_iu5_redirect_tid(2)) and not miss_tid2_sm_l2(0) and not miss_tid2_sm_l2(2); +miss_flush_occurred2_d <= '0' when reset_state(2) = '1' + else '1' when set_flush_occurred(2) = '1' + else miss_flush_occurred2_l2; +flush_addr_outside_range(2) <= ics_icm_iu0_ifar2 /= (miss_addr2_eff_l2(46 to 51) & miss_addr2_real_l2(52)); +set_flushed(2) <= miss_flush_occurred2_l2 and flush_addr_outside_range(2) and reld_r1_tid_l2(2) and (miss_tid2_sm_l2(1) or miss_tid2_sm_l2(11)); +miss_flushed2_d <= '0' when reset_state(2) = '1' + else '1' when set_flushed(2) = '1' + else miss_flushed2_l2; +inval_equal(2) <= icd_icm_iu2_inval and addr_equal(2); +set_invalidated(2) <= (inval_equal(2) or icd_icm_ici) and not miss_tid2_sm_l2(0) and not miss_tid2_sm_l2(2) and not miss_ci2_l2; +miss_inval2_d <= '0' when reset_state(2) = '1' + else '1' when set_invalidated(2) = '1' + else miss_inval2_l2; +sent_fp(2) <= reld_r3_tid_l2(2) and r3_loaded_l2 and not (an_ac_reld_ecc_err_l2 and not an_ac_reld_ecc_err_ue_l2); +set_block_fp(2) <= sent_fp(2) or + (ics_icm_iu3_flush_tid(2) and not (miss_tid2_sm_l2(0) or miss_tid2_sm_l2(2))); +miss_block_fp2_d <= '0' when reset_state(2) = '1' + else '1' when set_block_fp(2) = '1' + else miss_block_fp2_l2; +miss_ecc_err2_d <= '0' when (reset_state(2) or miss_tid2_sm_d(3) or miss_tid2_sm_d(7)) = '1' + else '1' when (new_ecc_err(2) and not miss_tid2_sm_l2(3) and not miss_tid2_sm_l2(7))= '1' + else miss_ecc_err2_l2; +miss_ecc_err_ue2_d <= '0' when (reset_state(2) or miss_tid2_sm_d(3) or miss_tid2_sm_d(7)) = '1' + else an_ac_reld_ecc_err_ue_l2 when new_ecc_err_ue(2) = '1' + else miss_ecc_err_ue2_l2; +miss_act(3) <= miss_tid3_sm_l2(0) and icd_icm_any_iu2_valid and icd_icm_tid(3); +miss_addr3_real_d <= icd_icm_addr_real; +miss_addr3_eff_d <= icd_icm_addr_eff; +miss_ci3_d <= icd_icm_wimge(1); +miss_endian3_d <= icd_icm_wimge(4); +miss_2ucode3_d <= icd_icm_2ucode; +miss_2ucode3_type_d <= icd_icm_2ucode_type; +set_flush_occurred(3) <= (xu_iu_flush(3) or bp_ic_iu5_redirect_tid(3)) and not miss_tid3_sm_l2(0) and not miss_tid3_sm_l2(2); +miss_flush_occurred3_d <= '0' when reset_state(3) = '1' + else '1' when set_flush_occurred(3) = '1' + else miss_flush_occurred3_l2; +flush_addr_outside_range(3) <= ics_icm_iu0_ifar3 /= (miss_addr3_eff_l2(46 to 51) & miss_addr3_real_l2(52)); +set_flushed(3) <= miss_flush_occurred3_l2 and flush_addr_outside_range(3) and reld_r1_tid_l2(3) and (miss_tid3_sm_l2(1) or miss_tid3_sm_l2(11)); +miss_flushed3_d <= '0' when reset_state(3) = '1' + else '1' when set_flushed(3) = '1' + else miss_flushed3_l2; +inval_equal(3) <= icd_icm_iu2_inval and addr_equal(3); +set_invalidated(3) <= (inval_equal(3) or icd_icm_ici) and not miss_tid3_sm_l2(0) and not miss_tid3_sm_l2(2) and not miss_ci3_l2; +miss_inval3_d <= '0' when reset_state(3) = '1' + else '1' when set_invalidated(3) = '1' + else miss_inval3_l2; +sent_fp(3) <= reld_r3_tid_l2(3) and r3_loaded_l2 and not (an_ac_reld_ecc_err_l2 and not an_ac_reld_ecc_err_ue_l2); +set_block_fp(3) <= sent_fp(3) or + (ics_icm_iu3_flush_tid(3) and not (miss_tid3_sm_l2(0) or miss_tid3_sm_l2(2))); +miss_block_fp3_d <= '0' when reset_state(3) = '1' + else '1' when set_block_fp(3) = '1' + else miss_block_fp3_l2; +miss_ecc_err3_d <= '0' when (reset_state(3) or miss_tid3_sm_d(3) or miss_tid3_sm_d(7)) = '1' + else '1' when (new_ecc_err(3) and not miss_tid3_sm_l2(3) and not miss_tid3_sm_l2(7))= '1' + else miss_ecc_err3_l2; +miss_ecc_err_ue3_d <= '0' when (reset_state(3) or miss_tid3_sm_d(3) or miss_tid3_sm_d(7)) = '1' + else an_ac_reld_ecc_err_ue_l2 when new_ecc_err_ue(3) = '1' + else miss_ecc_err_ue3_l2; +addr_equal(0) <= (icd_icm_addr_real(REAL_IFAR'left to 56) = miss_addr0_real_l2(REAL_IFAR'left to 56)) and + (spr_ic_cls_l2 or (icd_icm_addr_real(57) = miss_addr0_real_l2(57))); +addr_equal(1) <= (icd_icm_addr_real(REAL_IFAR'left to 56) = miss_addr1_real_l2(REAL_IFAR'left to 56)) and + (spr_ic_cls_l2 or (icd_icm_addr_real(57) = miss_addr1_real_l2(57))); +addr_equal(2) <= (icd_icm_addr_real(REAL_IFAR'left to 56) = miss_addr2_real_l2(REAL_IFAR'left to 56)) and + (spr_ic_cls_l2 or (icd_icm_addr_real(57) = miss_addr2_real_l2(57))); +addr_equal(3) <= (icd_icm_addr_real(REAL_IFAR'left to 56) = miss_addr3_real_l2(REAL_IFAR'left to 56)) and + (spr_ic_cls_l2 or (icd_icm_addr_real(57) = miss_addr3_real_l2(57))); +addr_match <= + (addr_equal(0) and not miss_tid0_sm_l2(0) and not miss_ci0_l2) or + (addr_equal(1) and not miss_tid1_sm_l2(0) and not miss_ci1_l2) or + (addr_equal(2) and not miss_tid2_sm_l2(0) and not miss_ci2_l2) or + (addr_equal(3) and not miss_tid3_sm_l2(0) and not miss_ci3_l2); +miss_thread_is_idle <= (miss_tid0_sm_l2(0) and icd_icm_tid(0)) or + (miss_tid1_sm_l2(0) and icd_icm_tid(1)) or + (miss_tid2_sm_l2(0) and icd_icm_tid(2)) or + (miss_tid3_sm_l2(0) and icd_icm_tid(3)) ; +iu3_miss_match_d <= (addr_match and not icd_icm_wimge(1)) when miss_thread_is_idle = '1' + else (not miss_thread_is_idle); +icm_ics_iu2_miss_match_prev <= iu3_miss_match_l2; +release_sm <= or_reduce( release_sm_hold(0 to 3) ); +iu0_inval_match(0) <= ics_icm_iu0_inval and (ics_icm_iu0_inval_addr(52 to 56) = miss_addr0_real_l2(52 to 56)) and + (spr_ic_cls_l2 or (ics_icm_iu0_inval_addr(57) = miss_addr0_real_l2(57))); +miss_wrote_dir0_d <= '0' when reset_state(0) = '1' + else (dir_write_no_block(0) or miss_wrote_dir0_l2); +miss_wrote_dir_v(0) <= miss_wrote_dir0_l2; +iu0_inval_match(1) <= ics_icm_iu0_inval and (ics_icm_iu0_inval_addr(52 to 56) = miss_addr1_real_l2(52 to 56)) and + (spr_ic_cls_l2 or (ics_icm_iu0_inval_addr(57) = miss_addr1_real_l2(57))); +miss_wrote_dir1_d <= '0' when reset_state(1) = '1' + else (dir_write_no_block(1) or miss_wrote_dir1_l2); +miss_wrote_dir_v(1) <= miss_wrote_dir1_l2; +iu0_inval_match(2) <= ics_icm_iu0_inval and (ics_icm_iu0_inval_addr(52 to 56) = miss_addr2_real_l2(52 to 56)) and + (spr_ic_cls_l2 or (ics_icm_iu0_inval_addr(57) = miss_addr2_real_l2(57))); +miss_wrote_dir2_d <= '0' when reset_state(2) = '1' + else (dir_write_no_block(2) or miss_wrote_dir2_l2); +miss_wrote_dir_v(2) <= miss_wrote_dir2_l2; +iu0_inval_match(3) <= ics_icm_iu0_inval and (ics_icm_iu0_inval_addr(52 to 56) = miss_addr3_real_l2(52 to 56)) and + (spr_ic_cls_l2 or (ics_icm_iu0_inval_addr(57) = miss_addr3_real_l2(57))); +miss_wrote_dir3_d <= '0' when reset_state(3) = '1' + else (dir_write_no_block(3) or miss_wrote_dir3_l2); +miss_wrote_dir_v(3) <= miss_wrote_dir3_l2; +miss_need_hold0_d <= '0' when ics_icm_iu3_flush_tid(0) = '1' + else '1' when (icd_icm_miss and icd_icm_tid(0)) = '1' + else miss_need_hold0_l2; +miss_need_hold1_d <= '0' when ics_icm_iu3_flush_tid(1) = '1' + else '1' when (icd_icm_miss and icd_icm_tid(1)) = '1' + else miss_need_hold1_l2; +miss_need_hold2_d <= '0' when ics_icm_iu3_flush_tid(2) = '1' + else '1' when (icd_icm_miss and icd_icm_tid(2)) = '1' + else miss_need_hold2_l2; +miss_need_hold3_d <= '0' when ics_icm_iu3_flush_tid(3) = '1' + else '1' when (icd_icm_miss and icd_icm_tid(3)) = '1' + else miss_need_hold3_l2; +request_d <= or_reduce( request_tid(0 to 3) ); +req_thread_d <= icd_icm_tid; +req_ra_d <= icd_icm_addr_real(REAL_IFAR'left to 59); +req_wimge_d <= icd_icm_wimge; +req_userdef_d <= icd_icm_userdef; +iu_xu_request <= request_l2 and not icd_icm_iu3_erat_err; +iu_xu_thread <= req_thread_l2; +iu_xu_ra <= req_ra_l2; +iu_xu_wimge <= req_wimge_l2; +iu_xu_userdef <= req_userdef_l2; +erat_err <= gate_and( (request_l2 and icd_icm_iu3_erat_err), req_thread_l2 ); +preload_r0_tid(0) <= r0_crit_qw(0) and reld_r0_tid_plain(0) and not miss_block_fp0_l2; +preload_r0_tid(1) <= r0_crit_qw(1) and reld_r0_tid_plain(1) and not miss_block_fp1_l2; +preload_r0_tid(2) <= r0_crit_qw(2) and reld_r0_tid_plain(2) and not miss_block_fp2_l2; +preload_r0_tid(3) <= r0_crit_qw(3) and reld_r0_tid_plain(3) and not miss_block_fp3_l2; +preload_hold_iu0 <= reld_r0_vld and or_reduce(preload_r0_tid); +r0_addr <= + gate_and(reld_r0_tid_plain(0), miss_addr0_real_l2(52 to 59)) or + gate_and(reld_r0_tid_plain(1), miss_addr1_real_l2(52 to 59)) or + gate_and(reld_r0_tid_plain(2), miss_addr2_real_l2(52 to 59)) or + gate_and(reld_r0_tid_plain(3), miss_addr3_real_l2(52 to 59)); +icm_ics_iu0_preload_val <= preload_hold_iu0; +icm_ics_iu0_preload_tid <= reld_r0_tid_plain; +icm_ics_iu0_preload_ifar <= r0_addr(52 to 59); +r2_load_addr <= +gate_and(reld_r2_tid_l2(0),(miss_addr0_eff_l2 & miss_addr0_real_l2(52 to 61))) or +gate_and(reld_r2_tid_l2(1),(miss_addr1_eff_l2 & miss_addr1_real_l2(52 to 61))) or +gate_and(reld_r2_tid_l2(2),(miss_addr2_eff_l2 & miss_addr2_real_l2(52 to 61))) or +gate_and(reld_r2_tid_l2(3),(miss_addr3_eff_l2 & miss_addr3_real_l2(52 to 61))); +r2_load_2ucode <= +(reld_r2_tid_l2(0) and miss_2ucode0_l2) or +(reld_r2_tid_l2(1) and miss_2ucode1_l2) or +(reld_r2_tid_l2(2) and miss_2ucode2_l2) or +(reld_r2_tid_l2(3) and miss_2ucode3_l2); +r2_load_2ucode_type <= +(reld_r2_tid_l2(0) and miss_2ucode0_type_l2) or +(reld_r2_tid_l2(1) and miss_2ucode1_type_l2) or +(reld_r2_tid_l2(2) and miss_2ucode2_type_l2) or +(reld_r2_tid_l2(3) and miss_2ucode3_type_l2); +load_tid_no_block(0) <= load_tid(0) and not miss_block_fp0_l2; +load_tid_no_block(1) <= load_tid(1) and not miss_block_fp1_l2; +load_tid_no_block(2) <= load_tid(2) and not miss_block_fp2_l2; +load_tid_no_block(3) <= load_tid(3) and not miss_block_fp3_l2; +icm_ics_load_tid <= load_tid_no_block; +icm_icd_load_tid <= load_tid_no_block; +icm_icd_load_addr <= r2_load_addr; +icm_icd_load_2ucode <= r2_load_2ucode; +icm_icd_load_2ucode_type <= r2_load_2ucode_type; +r3_loaded_d <= or_reduce( load_tid_no_block ); +r0_crit_qw(0) <= an_ac_reld_qw_l2(58 to 59) = miss_addr0_real_l2(58 to 59) when spr_ic_cls_l2 = '0' + else an_ac_reld_qw_l2(57 to 59) = miss_addr0_real_l2(57 to 59); +r1_crit_qw(0) <= reld_r1_qw_l2(1 to 2) = miss_addr0_real_l2(58 to 59) when spr_ic_cls_l2 = '0' + else reld_r1_qw_l2(0 to 2) = miss_addr0_real_l2(57 to 59); +r0_crit_qw(1) <= an_ac_reld_qw_l2(58 to 59) = miss_addr1_real_l2(58 to 59) when spr_ic_cls_l2 = '0' + else an_ac_reld_qw_l2(57 to 59) = miss_addr1_real_l2(57 to 59); +r1_crit_qw(1) <= reld_r1_qw_l2(1 to 2) = miss_addr1_real_l2(58 to 59) when spr_ic_cls_l2 = '0' + else reld_r1_qw_l2(0 to 2) = miss_addr1_real_l2(57 to 59); +r0_crit_qw(2) <= an_ac_reld_qw_l2(58 to 59) = miss_addr2_real_l2(58 to 59) when spr_ic_cls_l2 = '0' + else an_ac_reld_qw_l2(57 to 59) = miss_addr2_real_l2(57 to 59); +r1_crit_qw(2) <= reld_r1_qw_l2(1 to 2) = miss_addr2_real_l2(58 to 59) when spr_ic_cls_l2 = '0' + else reld_r1_qw_l2(0 to 2) = miss_addr2_real_l2(57 to 59); +r0_crit_qw(3) <= an_ac_reld_qw_l2(58 to 59) = miss_addr3_real_l2(58 to 59) when spr_ic_cls_l2 = '0' + else an_ac_reld_qw_l2(57 to 59) = miss_addr3_real_l2(57 to 59); +r1_crit_qw(3) <= reld_r1_qw_l2(1 to 2) = miss_addr3_real_l2(58 to 59) when spr_ic_cls_l2 = '0' + else reld_r1_qw_l2(0 to 2) = miss_addr3_real_l2(57 to 59); +r2_crit_qw_d <= or_reduce(r1_crit_qw and reld_r1_tid_l2); +icm_icd_lru_addr <= r0_addr(52 to 57); +lru_write_hit <= or_reduce(lru_write) and (r0_addr(52 to 56) = lru_write_addr(52 to 56)) and + (spr_ic_cls_l2 or (r0_addr(57) = lru_write_addr(57))); +row_val_d <= icd_icm_row_val; +hit_lru <= gate_and(lru_write_way(0), ("11" & icd_icm_row_lru(2))) or + gate_and(lru_write_way(1), ("10" & icd_icm_row_lru(2))) or + gate_and(lru_write_way(2), ('0' & icd_icm_row_lru(1) & '1')) or + gate_and(lru_write_way(3), ('0' & icd_icm_row_lru(1) & '0')); +row_lru_d <= icd_icm_row_lru when lru_write_hit = '0' + else hit_lru; +select_lru(0) <= not miss_ci0_l2 and reld_r1_tid_l2(0) and miss_tid0_sm_l2(1); +select_lru(1) <= not miss_ci1_l2 and reld_r1_tid_l2(1) and miss_tid1_sm_l2(1); +select_lru(2) <= not miss_ci2_l2 and reld_r1_tid_l2(2) and miss_tid2_sm_l2(1); +select_lru(3) <= not miss_ci3_l2 and reld_r1_tid_l2(3) and miss_tid3_sm_l2(1); +lru_valid(0) <= not (miss_tid0_sm_l2(0) or miss_tid0_sm_l2(1) or miss_tid0_sm_l2(2) or miss_flushed0_l2 or miss_inval0_l2 or miss_ci0_l2); +lru_valid(1) <= not (miss_tid1_sm_l2(0) or miss_tid1_sm_l2(1) or miss_tid1_sm_l2(2) or miss_flushed1_l2 or miss_inval1_l2 or miss_ci1_l2); +lru_valid(2) <= not (miss_tid2_sm_l2(0) or miss_tid2_sm_l2(1) or miss_tid2_sm_l2(2) or miss_flushed2_l2 or miss_inval2_l2 or miss_ci2_l2); +lru_valid(3) <= not (miss_tid3_sm_l2(0) or miss_tid3_sm_l2(1) or miss_tid3_sm_l2(2) or miss_flushed3_l2 or miss_inval3_l2 or miss_ci3_l2); +r1_addr <= + gate_and(reld_r1_tid_l2(0), miss_addr0_real_l2(52 to 57)) or + gate_and(reld_r1_tid_l2(1), miss_addr1_real_l2(52 to 57)) or + gate_and(reld_r1_tid_l2(2), miss_addr2_real_l2(52 to 57)) or + gate_and(reld_r1_tid_l2(3), miss_addr3_real_l2(52 to 57)); +row_match(0) <= lru_valid(0) and (r1_addr(52 to 56) = miss_addr0_real_l2(52 to 56)) and + (spr_ic_cls_l2 or (r1_addr(57) = miss_addr0_real_l2(57))); +row_match(1) <= lru_valid(1) and (r1_addr(52 to 56) = miss_addr1_real_l2(52 to 56)) and + (spr_ic_cls_l2 or (r1_addr(57) = miss_addr1_real_l2(57))); +row_match(2) <= lru_valid(2) and (r1_addr(52 to 56) = miss_addr2_real_l2(52 to 56)) and + (spr_ic_cls_l2 or (r1_addr(57) = miss_addr2_real_l2(57))); +row_match(3) <= lru_valid(3) and (r1_addr(52 to 56) = miss_addr3_real_l2(52 to 56)) and + (spr_ic_cls_l2 or (r1_addr(57) = miss_addr3_real_l2(57))); +row_match_way <= + gate_and(row_match(0), miss_way0_l2) or + gate_and(row_match(1), miss_way1_l2) or + gate_and(row_match(2), miss_way2_l2) or + gate_and(row_match(3), miss_way3_l2); +val_or_match <= row_val_l2 or row_match_way; +MQQ313:SELECT_LRU_WAY_PT(1) <= + Eq(( ROW_LRU_L2(0) & ROW_LRU_L2(2) & + ROW_MATCH_WAY(0) & ROW_MATCH_WAY(1) & + ROW_MATCH_WAY(3) ) , STD_ULOGIC_VECTOR'("01011")); +MQQ314:SELECT_LRU_WAY_PT(2) <= + Eq(( ROW_LRU_L2(0) & ROW_LRU_L2(2) & + ROW_MATCH_WAY(0) & ROW_MATCH_WAY(1) & + ROW_MATCH_WAY(2) ) , STD_ULOGIC_VECTOR'("00011")); +MQQ315:SELECT_LRU_WAY_PT(3) <= + Eq(( ROW_LRU_L2(0) & ROW_LRU_L2(2) & + ROW_MATCH_WAY(0) & ROW_MATCH_WAY(1) & + ROW_MATCH_WAY(3) ) , STD_ULOGIC_VECTOR'("01101")); +MQQ316:SELECT_LRU_WAY_PT(4) <= + Eq(( ROW_LRU_L2(0) & ROW_LRU_L2(2) & + ROW_MATCH_WAY(0) & ROW_MATCH_WAY(1) & + ROW_MATCH_WAY(2) ) , STD_ULOGIC_VECTOR'("00101")); +MQQ317:SELECT_LRU_WAY_PT(5) <= + Eq(( ROW_LRU_L2(0) & ROW_LRU_L2(1) & + ROW_MATCH_WAY(1) & ROW_MATCH_WAY(2) & + ROW_MATCH_WAY(3) ) , STD_ULOGIC_VECTOR'("11101")); +MQQ318:SELECT_LRU_WAY_PT(6) <= + Eq(( ROW_LRU_L2(0) & ROW_LRU_L2(1) & + ROW_MATCH_WAY(0) & ROW_MATCH_WAY(2) & + ROW_MATCH_WAY(3) ) , STD_ULOGIC_VECTOR'("10101")); +MQQ319:SELECT_LRU_WAY_PT(7) <= + Eq(( ROW_LRU_L2(0) & ROW_LRU_L2(1) & + ROW_MATCH_WAY(1) & ROW_MATCH_WAY(2) & + ROW_MATCH_WAY(3) ) , STD_ULOGIC_VECTOR'("11110")); +MQQ320:SELECT_LRU_WAY_PT(8) <= + Eq(( ROW_LRU_L2(0) & ROW_LRU_L2(1) & + ROW_MATCH_WAY(0) & ROW_MATCH_WAY(2) & + ROW_MATCH_WAY(3) ) , STD_ULOGIC_VECTOR'("10110")); +MQQ321:SELECT_LRU_WAY_PT(9) <= + Eq(( ROW_LRU_L2(0) & ROW_LRU_L2(1) & + ROW_MATCH_WAY(1) & ROW_MATCH_WAY(2) & + ROW_MATCH_WAY(3) ) , STD_ULOGIC_VECTOR'("11111")); +MQQ322:SELECT_LRU_WAY_PT(10) <= + Eq(( ROW_LRU_L2(0) & ROW_LRU_L2(1) & + ROW_MATCH_WAY(0) & ROW_MATCH_WAY(2) & + ROW_MATCH_WAY(3) ) , STD_ULOGIC_VECTOR'("10111")); +MQQ323:SELECT_LRU_WAY_PT(11) <= + Eq(( ROW_LRU_L2(0) & ROW_LRU_L2(2) & + ROW_MATCH_WAY(0) & ROW_MATCH_WAY(1) & + ROW_MATCH_WAY(3) ) , STD_ULOGIC_VECTOR'("01111")); +MQQ324:SELECT_LRU_WAY_PT(12) <= + Eq(( ROW_LRU_L2(0) & ROW_LRU_L2(2) & + ROW_MATCH_WAY(0) & ROW_MATCH_WAY(1) & + ROW_MATCH_WAY(2) ) , STD_ULOGIC_VECTOR'("00111")); +MQQ325:SELECT_LRU_WAY_PT(13) <= + Eq(( ROW_LRU_L2(1) & ROW_LRU_L2(2) & + ROW_MATCH_WAY(0) & ROW_MATCH_WAY(3) + ) , STD_ULOGIC_VECTOR'("0101")); +MQQ326:SELECT_LRU_WAY_PT(14) <= + Eq(( ROW_LRU_L2(1) & ROW_LRU_L2(2) & + ROW_MATCH_WAY(0) & ROW_MATCH_WAY(2) + ) , STD_ULOGIC_VECTOR'("0001")); +MQQ327:SELECT_LRU_WAY_PT(15) <= + Eq(( ROW_LRU_L2(1) & ROW_LRU_L2(2) & + ROW_MATCH_WAY(1) & ROW_MATCH_WAY(3) + ) , STD_ULOGIC_VECTOR'("1101")); +MQQ328:SELECT_LRU_WAY_PT(16) <= + Eq(( ROW_LRU_L2(1) & ROW_LRU_L2(2) & + ROW_MATCH_WAY(1) & ROW_MATCH_WAY(2) + ) , STD_ULOGIC_VECTOR'("1001")); +MQQ329:SELECT_LRU_WAY_PT(17) <= + Eq(( ROW_LRU_L2(1) & ROW_LRU_L2(2) & + ROW_MATCH_WAY(1) & ROW_MATCH_WAY(2) + ) , STD_ULOGIC_VECTOR'("1010")); +MQQ330:SELECT_LRU_WAY_PT(18) <= + Eq(( ROW_LRU_L2(1) & ROW_LRU_L2(2) & + ROW_MATCH_WAY(0) & ROW_MATCH_WAY(2) + ) , STD_ULOGIC_VECTOR'("0010")); +MQQ331:SELECT_LRU_WAY_PT(19) <= + Eq(( ROW_LRU_L2(1) & ROW_LRU_L2(2) & + ROW_MATCH_WAY(1) & ROW_MATCH_WAY(3) + ) , STD_ULOGIC_VECTOR'("1110")); +MQQ332:SELECT_LRU_WAY_PT(20) <= + Eq(( ROW_LRU_L2(1) & ROW_LRU_L2(2) & + ROW_MATCH_WAY(0) & ROW_MATCH_WAY(3) + ) , STD_ULOGIC_VECTOR'("0110")); +MQQ333:SELECT_LRU_WAY_PT(21) <= + Eq(( ROW_LRU_L2(0) & ROW_LRU_L2(1) & + ROW_MATCH_WAY(0) ) , STD_ULOGIC_VECTOR'("000")); +MQQ334:SELECT_LRU_WAY_PT(22) <= + Eq(( ROW_LRU_L2(0) & ROW_LRU_L2(1) & + ROW_MATCH_WAY(1) ) , STD_ULOGIC_VECTOR'("010")); +MQQ335:SELECT_LRU_WAY_PT(23) <= + Eq(( ROW_LRU_L2(0) & ROW_LRU_L2(2) & + ROW_MATCH_WAY(2) ) , STD_ULOGIC_VECTOR'("100")); +MQQ336:SELECT_LRU_WAY_PT(24) <= + Eq(( ROW_LRU_L2(0) & ROW_LRU_L2(2) & + ROW_MATCH_WAY(3) ) , STD_ULOGIC_VECTOR'("110")); +MQQ337:NEXT_LRU_WAY(0) <= + (SELECT_LRU_WAY_PT(1) OR SELECT_LRU_WAY_PT(2) + OR SELECT_LRU_WAY_PT(9) OR SELECT_LRU_WAY_PT(13) + OR SELECT_LRU_WAY_PT(14) OR SELECT_LRU_WAY_PT(21) + ); +MQQ338:NEXT_LRU_WAY(1) <= + (SELECT_LRU_WAY_PT(3) OR SELECT_LRU_WAY_PT(4) + OR SELECT_LRU_WAY_PT(10) OR SELECT_LRU_WAY_PT(15) + OR SELECT_LRU_WAY_PT(16) OR SELECT_LRU_WAY_PT(22) + ); +MQQ339:NEXT_LRU_WAY(2) <= + (SELECT_LRU_WAY_PT(5) OR SELECT_LRU_WAY_PT(6) + OR SELECT_LRU_WAY_PT(11) OR SELECT_LRU_WAY_PT(17) + OR SELECT_LRU_WAY_PT(18) OR SELECT_LRU_WAY_PT(23) + ); +MQQ340:NEXT_LRU_WAY(3) <= + (SELECT_LRU_WAY_PT(7) OR SELECT_LRU_WAY_PT(8) + OR SELECT_LRU_WAY_PT(12) OR SELECT_LRU_WAY_PT(19) + OR SELECT_LRU_WAY_PT(20) OR SELECT_LRU_WAY_PT(24) + ); + +next_way(0) <= (val_or_match(0) = '0') or (next_lru_way(0) and (val_or_match(0 to 3) = "1111")); +next_way(1) <= (val_or_match(0 to 1) = "10") or (next_lru_way(1) and (val_or_match(0 to 3) = "1111")); +next_way(2) <= (val_or_match(0 to 2) = "110") or (next_lru_way(2) and (val_or_match(0 to 3) = "1111")); +next_way(3) <= (val_or_match(0 to 3) = "1110") or (next_lru_way(3) and (val_or_match(0 to 3) = "1111")); +miss_way0_d <= next_way when select_lru(0) = '1' + else miss_way0_l2; +miss_way1_d <= next_way when select_lru(1) = '1' + else miss_way1_l2; +miss_way2_d <= next_way when select_lru(2) = '1' + else miss_way2_l2; +miss_way3_d <= next_way when select_lru(3) = '1' + else miss_way3_l2; +icm_ics_hold_thread(0) <= hold_tid(0) and miss_need_hold0_l2 and not ics_icm_iu3_flush_tid(0); +icm_ics_hold_thread_dbg(0) <= hold_tid(0) and miss_need_hold0_l2; +icm_ics_hold_thread(1) <= hold_tid(1) and miss_need_hold1_l2 and not ics_icm_iu3_flush_tid(1); +icm_ics_hold_thread_dbg(1) <= hold_tid(1) and miss_need_hold1_l2; +icm_ics_hold_thread(2) <= hold_tid(2) and miss_need_hold2_l2 and not ics_icm_iu3_flush_tid(2); +icm_ics_hold_thread_dbg(2) <= hold_tid(2) and miss_need_hold2_l2; +icm_ics_hold_thread(3) <= hold_tid(3) and miss_need_hold3_l2 and not ics_icm_iu3_flush_tid(3); +icm_ics_hold_thread_dbg(3) <= hold_tid(3) and miss_need_hold3_l2; +hold_iu0 <= or_reduce( data_write(0 to 3) ) or + preload_hold_iu0; +icm_ics_hold_iu0 <= hold_iu0; +icm_icd_data_write <= or_reduce( data_write(0 to 3) ); +dir_inval <= or_reduce( write_dir_inval(0 to 3) ); +icm_icd_dir_inval <= dir_inval; +icm_icd_dir_val <= or_reduce( (write_dir_val(0 to 3) and miss_wrote_dir_v) ); +r3_need_back_inval_d <= or_reduce(inval_equal and write_dir_val and miss_wrote_dir_v); +icm_icd_reload_addr <= (r2_load_addr(52 to 57) & reld_r2_qw_l2(1 to 2)) when spr_ic_cls_l2 = '0' + else (r2_load_addr(52 to 56) & reld_r2_qw_l2(0 to 2)); +reload_way <= gate_and(reld_r2_tid_l2(0), miss_way0_l2) or + gate_and(reld_r2_tid_l2(1), miss_way1_l2) or + gate_and(reld_r2_tid_l2(2), miss_way2_l2) or + gate_and(reld_r2_tid_l2(3), miss_way3_l2); +icm_icd_reload_way <= reload_way; +reload_endian <= (reld_r2_tid_l2(0) and miss_endian0_l2) or + (reld_r2_tid_l2(1) and miss_endian1_l2) or + (reld_r2_tid_l2(2) and miss_endian2_l2) or + (reld_r2_tid_l2(3) and miss_endian3_l2); +swap_endian_data <= + an_ac_reld_data_l2(24 to 31) & an_ac_reld_data_l2(16 to 23) & an_ac_reld_data_l2(8 to 15) & an_ac_reld_data_l2(0 to 7) & + an_ac_reld_data_l2(56 to 63) & an_ac_reld_data_l2(48 to 55) & an_ac_reld_data_l2(40 to 47) & an_ac_reld_data_l2(32 to 39) & + an_ac_reld_data_l2(88 to 95) & an_ac_reld_data_l2(80 to 87) & an_ac_reld_data_l2(72 to 79) & an_ac_reld_data_l2(64 to 71) & + an_ac_reld_data_l2(120 to 127) & an_ac_reld_data_l2(112 to 119) & an_ac_reld_data_l2(104 to 111) & an_ac_reld_data_l2(96 to 103); +br_decode0 : iuq_bd + port map( + instruction => an_ac_reld_data_l2(0 to 31), + branch_decode => branch_decode0(0 to 3), + bp_bc_en => bp_config_l2(0), + bp_bclr_en => bp_config_l2(1), + bp_bcctr_en => bp_config_l2(2), + bp_sw_en => bp_config_l2(3) + ); +br_decode1 : iuq_bd + port map( + instruction => an_ac_reld_data_l2(32 to 63), + branch_decode => branch_decode1(0 to 3), + bp_bc_en => bp_config_l2(0), + bp_bclr_en => bp_config_l2(1), + bp_bcctr_en => bp_config_l2(2), + bp_sw_en => bp_config_l2(3) + ); +br_decode2 : iuq_bd + port map( + instruction => an_ac_reld_data_l2(64 to 95), + branch_decode => branch_decode2(0 to 3), + bp_bc_en => bp_config_l2(0), + bp_bclr_en => bp_config_l2(1), + bp_bcctr_en => bp_config_l2(2), + bp_sw_en => bp_config_l2(3) + ); +br_decode3 : iuq_bd + port map( + instruction => an_ac_reld_data_l2(96 to 127), + branch_decode => branch_decode3(0 to 3), + bp_bc_en => bp_config_l2(0), + bp_bclr_en => bp_config_l2(1), + bp_bcctr_en => bp_config_l2(2), + bp_sw_en => bp_config_l2(3) + ); +swap_br_decode0 : iuq_bd + port map( + instruction => swap_endian_data(0 to 31), + branch_decode => swap_branch_decode0(0 to 3), + bp_bc_en => bp_config_l2(0), + bp_bclr_en => bp_config_l2(1), + bp_bcctr_en => bp_config_l2(2), + bp_sw_en => bp_config_l2(3) + ); +swap_br_decode1 : iuq_bd + port map( + instruction => swap_endian_data(32 to 63), + branch_decode => swap_branch_decode1(0 to 3), + bp_bc_en => bp_config_l2(0), + bp_bclr_en => bp_config_l2(1), + bp_bcctr_en => bp_config_l2(2), + bp_sw_en => bp_config_l2(3) + ); +swap_br_decode2 : iuq_bd + port map( + instruction => swap_endian_data(64 to 95), + branch_decode => swap_branch_decode2(0 to 3), + bp_bc_en => bp_config_l2(0), + bp_bclr_en => bp_config_l2(1), + bp_bcctr_en => bp_config_l2(2), + bp_sw_en => bp_config_l2(3) + ); +swap_br_decode3 : iuq_bd + port map( + instruction => swap_endian_data(96 to 127), + branch_decode => swap_branch_decode3(0 to 3), + bp_bc_en => bp_config_l2(0), + bp_bclr_en => bp_config_l2(1), + bp_bcctr_en => bp_config_l2(2), + bp_sw_en => bp_config_l2(3) + ); +instr_data <= an_ac_reld_data_l2( 0 to 31) & branch_decode0(0 to 3) & + an_ac_reld_data_l2( 32 to 63) & branch_decode1(0 to 3) & + an_ac_reld_data_l2( 64 to 95) & branch_decode2(0 to 3) & + an_ac_reld_data_l2( 96 to 127) & branch_decode3(0 to 3); +swap_data <= swap_endian_data( 0 to 31) & swap_branch_decode0(0 to 3) & + swap_endian_data( 32 to 63) & swap_branch_decode1(0 to 3) & + swap_endian_data( 64 to 95) & swap_branch_decode2(0 to 3) & + swap_endian_data( 96 to 127) & swap_branch_decode3(0 to 3); +gen_data_parity: for i in 0 to 17 generate +begin + data_parity_in(i) <= xor_reduce( instr_data(i*8 to i*8+7) ); +swap_parity_in(i) <= xor_reduce( swap_data(i*8 to i*8+7) ); +end generate; +with reload_endian select +icm_icd_reload_data <= instr_data & data_parity_in when '0', + swap_data & swap_parity_in when others; +dir_write_no_block <= dir_write and not iu0_inval_match; +icm_icd_dir_write <= or_reduce(dir_write_no_block); +icm_icd_dir_write_addr <= r2_real_addr; +icm_icd_dir_write_endian <= reload_endian; +icm_icd_dir_write_way <= reload_way; +r2_real_addr <= + gate_and(reld_r2_tid_l2(0), miss_addr0_real_l2(REAL_IFAR'left to 57)) or + gate_and(reld_r2_tid_l2(1), miss_addr1_real_l2(REAL_IFAR'left to 57)) or + gate_and(reld_r2_tid_l2(2), miss_addr2_real_l2(REAL_IFAR'left to 57)) or + gate_and(reld_r2_tid_l2(3), miss_addr3_real_l2(REAL_IFAR'left to 57)); +lru_write_next_cycle_d(0) <= data_write(0) and ((miss_tid0_sm_l2(5) and spr_ic_cls_l2 = '0') or + (miss_tid0_sm_l2(15) and spr_ic_cls_l2 = '1')); +lru_write_d(0) <= lru_write_next_cycle_l2(0); +lru_write(0) <= lru_write_l2(0) and not miss_inval0_l2 and (miss_tid0_sm_l2(6) or miss_tid0_sm_l2(11)); +lru_write_next_cycle_d(1) <= data_write(1) and ((miss_tid1_sm_l2(5) and spr_ic_cls_l2 = '0') or + (miss_tid1_sm_l2(15) and spr_ic_cls_l2 = '1')); +lru_write_d(1) <= lru_write_next_cycle_l2(1); +lru_write(1) <= lru_write_l2(1) and not miss_inval1_l2 and (miss_tid1_sm_l2(6) or miss_tid1_sm_l2(11)); +lru_write_next_cycle_d(2) <= data_write(2) and ((miss_tid2_sm_l2(5) and spr_ic_cls_l2 = '0') or + (miss_tid2_sm_l2(15) and spr_ic_cls_l2 = '1')); +lru_write_d(2) <= lru_write_next_cycle_l2(2); +lru_write(2) <= lru_write_l2(2) and not miss_inval2_l2 and (miss_tid2_sm_l2(6) or miss_tid2_sm_l2(11)); +lru_write_next_cycle_d(3) <= data_write(3) and ((miss_tid3_sm_l2(5) and spr_ic_cls_l2 = '0') or + (miss_tid3_sm_l2(15) and spr_ic_cls_l2 = '1')); +lru_write_d(3) <= lru_write_next_cycle_l2(3); +lru_write(3) <= lru_write_l2(3) and not miss_inval3_l2 and (miss_tid3_sm_l2(6) or miss_tid3_sm_l2(11)); +icm_icd_lru_write <= or_reduce( lru_write ); +lru_write_addr <= gate_and(lru_write_l2(0), miss_addr0_real_l2(52 to 57)) or + gate_and(lru_write_l2(1), miss_addr1_real_l2(52 to 57)) or + gate_and(lru_write_l2(2), miss_addr2_real_l2(52 to 57)) or + gate_and(lru_write_l2(3), miss_addr3_real_l2(52 to 57)); +lru_write_way <= gate_and(lru_write_l2(0), miss_way0_l2) or + gate_and(lru_write_l2(1), miss_way1_l2) or + gate_and(lru_write_l2(2), miss_way2_l2) or + gate_and(lru_write_l2(3), miss_way3_l2); +icm_icd_lru_write_addr <= lru_write_addr; +icm_icd_lru_write_way <= lru_write_way; +icm_icd_any_reld_r2 <= or_reduce(reld_r2_tid_l2); +icm_icd_any_checkecc <= miss_tid0_sm_l2(11) or miss_tid1_sm_l2(11) or miss_tid2_sm_l2(11) or miss_tid3_sm_l2(11); +new_ecc_err <= gate_and(an_ac_reld_ecc_err_l2, reld_r3_tid_l2); +new_ecc_err_ue <= gate_and(an_ac_reld_ecc_err_ue_l2, reld_r3_tid_l2); +ecc_err(0) <= new_ecc_err(0) or miss_ecc_err0_l2; +ecc_err_ue(0) <= new_ecc_err_ue(0) or miss_ecc_err_ue0_l2; +ecc_inval(0) <= (an_ac_reld_ecc_err_l2 or an_ac_reld_ecc_err_ue_l2) and + miss_tid0_sm_l2(11) and not miss_ci0_l2 and not miss_flushed0_l2 and not miss_inval0_l2; +ecc_block_iu0(0) <= an_ac_reld_ecc_err_l2 and miss_tid0_sm_l2(11) and miss_need_hold0_l2; +ecc_err(1) <= new_ecc_err(1) or miss_ecc_err1_l2; +ecc_err_ue(1) <= new_ecc_err_ue(1) or miss_ecc_err_ue1_l2; +ecc_inval(1) <= (an_ac_reld_ecc_err_l2 or an_ac_reld_ecc_err_ue_l2) and + miss_tid1_sm_l2(11) and not miss_ci1_l2 and not miss_flushed1_l2 and not miss_inval1_l2; +ecc_block_iu0(1) <= an_ac_reld_ecc_err_l2 and miss_tid1_sm_l2(11) and miss_need_hold1_l2; +ecc_err(2) <= new_ecc_err(2) or miss_ecc_err2_l2; +ecc_err_ue(2) <= new_ecc_err_ue(2) or miss_ecc_err_ue2_l2; +ecc_inval(2) <= (an_ac_reld_ecc_err_l2 or an_ac_reld_ecc_err_ue_l2) and + miss_tid2_sm_l2(11) and not miss_ci2_l2 and not miss_flushed2_l2 and not miss_inval2_l2; +ecc_block_iu0(2) <= an_ac_reld_ecc_err_l2 and miss_tid2_sm_l2(11) and miss_need_hold2_l2; +ecc_err(3) <= new_ecc_err(3) or miss_ecc_err3_l2; +ecc_err_ue(3) <= new_ecc_err_ue(3) or miss_ecc_err_ue3_l2; +ecc_inval(3) <= (an_ac_reld_ecc_err_l2 or an_ac_reld_ecc_err_ue_l2) and + miss_tid3_sm_l2(11) and not miss_ci3_l2 and not miss_flushed3_l2 and not miss_inval3_l2; +ecc_block_iu0(3) <= an_ac_reld_ecc_err_l2 and miss_tid3_sm_l2(11) and miss_need_hold3_l2; +icm_ics_ecc_block_iu0 <= ecc_block_iu0; +icm_icd_ecc_inval <= or_reduce(ecc_inval) or r3_need_back_inval_l2; +r3_addr <= + gate_and(reld_r3_tid_l2(0), miss_addr0_real_l2(52 to 57)) or + gate_and(reld_r3_tid_l2(1), miss_addr1_real_l2(52 to 57)) or + gate_and(reld_r3_tid_l2(2), miss_addr2_real_l2(52 to 57)) or + gate_and(reld_r3_tid_l2(3), miss_addr3_real_l2(52 to 57)); +icm_icd_ecc_addr <= r3_addr(52 to 57); +r3_way <= gate_and(reld_r3_tid_l2(0), miss_way0_l2) or + gate_and(reld_r3_tid_l2(1), miss_way1_l2) or + gate_and(reld_r3_tid_l2(2), miss_way2_l2) or + gate_and(reld_r3_tid_l2(3), miss_way3_l2); +icm_icd_ecc_way <= r3_way; +icm_ics_iu1_ecc_flush <= or_reduce(ecc_inval); +ecc_fp <= r3_loaded_l2 and an_ac_reld_ecc_err_l2; +icm_icd_iu3_ecc_fp_cancel <= ecc_fp and not an_ac_reld_ecc_err_ue_l2; +icm_icd_iu3_ecc_err <= r3_loaded_l2 and an_ac_reld_ecc_err_ue_l2; +perf_event_t0_d(0) <= not miss_ci0_l2 and not miss_tid0_sm_l2(0) and not miss_tid0_sm_l2(2) and + not (miss_tid0_sm_l2(11) and (ecc_err_ue(0) or not ecc_err(0))) and + not erat_err(0); +perf_event_t1_d(0) <= not miss_ci1_l2 and not miss_tid1_sm_l2(0) and not miss_tid1_sm_l2(2) and + not (miss_tid1_sm_l2(11) and (ecc_err_ue(1) or not ecc_err(1))) and + not erat_err(1); +perf_event_t2_d(0) <= not miss_ci2_l2 and not miss_tid2_sm_l2(0) and not miss_tid2_sm_l2(2) and + not (miss_tid2_sm_l2(11) and (ecc_err_ue(2) or not ecc_err(2))) and + not erat_err(2); +perf_event_t3_d(0) <= not miss_ci3_l2 and not miss_tid3_sm_l2(0) and not miss_tid3_sm_l2(2) and + not (miss_tid3_sm_l2(11) and (ecc_err_ue(3) or not ecc_err(3))) and + not erat_err(3); +perf_event_t0_d(1) <= not miss_ci0_l2 and miss_flushed0_l2 and (release_sm_hold(0) and not miss_tid0_sm_d(11)); +perf_event_t1_d(1) <= not miss_ci1_l2 and miss_flushed1_l2 and (release_sm_hold(1) and not miss_tid1_sm_d(11)); +perf_event_t2_d(1) <= not miss_ci2_l2 and miss_flushed2_l2 and (release_sm_hold(2) and not miss_tid2_sm_d(11)); +perf_event_t3_d(1) <= not miss_ci3_l2 and miss_flushed3_l2 and (release_sm_hold(3) and not miss_tid3_sm_d(11)); +ic_perf_event_t0 <= perf_event_t0_l2; +ic_perf_event_t1 <= perf_event_t1_l2; +ic_perf_event_t2 <= perf_event_t2_l2; +ic_perf_event_t3 <= perf_event_t3_l2; +miss_dbg_data0(0 TO 21) <= miss_tid0_sm_l2(0 to 11) & + miss_flush_occurred0_l2 & miss_flushed0_l2 & miss_inval0_l2 & miss_block_fp0_l2 & + miss_ecc_err0_l2 & miss_ecc_err_ue0_l2 & miss_wrote_dir0_l2 & miss_need_hold0_l2 & + reld_r2_tid_l2(0) & load_tid_no_block(0); +miss_dbg_data0(22 TO 43) <= miss_tid1_sm_l2(0 to 11) & + miss_flush_occurred1_l2 & miss_flushed1_l2 & miss_inval1_l2 & miss_block_fp1_l2 & + miss_ecc_err1_l2 & miss_ecc_err_ue1_l2 & miss_wrote_dir1_l2 & miss_need_hold1_l2 & + reld_r2_tid_l2(1) & load_tid_no_block(1); +miss_dbg_data0(44 TO 65) <= miss_tid2_sm_l2(0 to 11) & + miss_flush_occurred2_l2 & miss_flushed2_l2 & miss_inval2_l2 & miss_block_fp2_l2 & + miss_ecc_err2_l2 & miss_ecc_err_ue2_l2 & miss_wrote_dir2_l2 & miss_need_hold2_l2 & + reld_r2_tid_l2(2) & load_tid_no_block(2); +miss_dbg_data0(66 TO 87) <= miss_tid3_sm_l2(0 to 11) & + miss_flush_occurred3_l2 & miss_flushed3_l2 & miss_inval3_l2 & miss_block_fp3_l2 & + miss_ecc_err3_l2 & miss_ecc_err_ue3_l2 & miss_wrote_dir3_l2 & miss_need_hold3_l2 & + reld_r2_tid_l2(3) & load_tid_no_block(3); +miss_dbg_data1(0 TO 11) <= miss_tid0_sm_l2(0 to 11); +miss_dbg_data1(12 TO 23) <= miss_tid1_sm_l2(0 to 11); +miss_dbg_data1(24) <= miss_tid2_sm_l2(0); +miss_dbg_data1(25) <= miss_tid3_sm_l2(0); +miss_dbg_data1(26 TO 35) <= r2_load_addr(52 to 61); +miss_dbg_data1(36 TO 39) <= row_val_l2; +miss_dbg_data1_d(51) <= lru_write_hit; +miss_dbg_data1(40) <= miss_dbg_data1_l2(51); +miss_dbg_data1(41 TO 43) <= row_lru_l2; +miss_dbg_data1(44 TO 47) <= select_lru; +miss_dbg_data1(48 TO 51) <= lru_valid; +miss_dbg_data1_d(52 TO 55) <= row_match_way; +miss_dbg_data1_d(56 TO 59) <= next_way; +miss_dbg_data1(52 TO 59) <= miss_dbg_data1_l2(52 to 59); +miss_dbg_data1(60 TO 63) <= perf_event_t0_l2(1) & perf_event_t1_l2(1) & perf_event_t2_l2(1) & perf_event_t3_l2(1); +miss_dbg_data1(64 TO 67) <= data_write; +miss_dbg_data1(68 TO 71) <= miss_inval0_l2 & miss_inval1_l2 & miss_inval2_l2 & miss_inval3_l2; +miss_dbg_data1(72) <= icd_icm_iu2_inval; +miss_dbg_data1(73) <= r2_load_2ucode; +miss_dbg_data1(74) <= dir_inval; +miss_dbg_data1(75) <= r3_need_back_inval_l2; +miss_dbg_data1(76 TO 79) <= write_dir_val; +miss_dbg_data1(80 TO 83) <= load_tid_no_block; +miss_dbg_data1(84 TO 87) <= reld_r2_tid_l2; +miss_dbg_data2(0 TO 9) <= icd_icm_addr_real(52 to 61); +miss_dbg_data2(10 TO 13) <= miss_tid0_sm_l2(0) & miss_tid1_sm_l2(0) & miss_tid2_sm_l2(0) & miss_tid3_sm_l2(0); +miss_dbg_data2(14 TO 17) <= req_thread_l2; +miss_dbg_data2(18) <= request_l2; +miss_dbg_data2(19 TO 27) <= req_wimge_l2 & req_userdef_l2; +miss_dbg_data2(28) <= iu3_miss_match_l2; +miss_dbg_data2(29) <= preload_hold_iu0; +miss_dbg_data2(30) <= dir_inval; +miss_dbg_data2(31) <= r3_need_back_inval_l2; +miss_dbg_data2(32 TO 35) <= write_dir_val; +miss_dbg_data2(36 TO 39) <= load_tid_no_block; +miss_dbg_data2(40 TO 43) <= reld_r2_tid_l2; +miss_dbg_trigger(0 TO 5) <= req_ra_l2(52 to 57); +miss_dbg_trigger(6) <= request_l2; +miss_dbg_trigger(7) <= reld_r0_vld; +miss_dbg_trigger(8 TO 9) <= an_ac_reld_core_tag_l2(3 to 4); +miss_dbg_trigger(10) <= an_ac_reld_ecc_err_l2; +miss_dbg_trigger(11) <= an_ac_reld_ecc_err_ue_l2; +spr_ic_cls_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(spr_ic_cls_offset), + scout => sov(spr_ic_cls_offset), + din => spr_ic_cls_d, + dout => spr_ic_cls_l2); +bp_config_latch: tri_rlmreg_p + generic map (width => bp_config_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(bp_config_offset to bp_config_offset + bp_config_l2'length-1), + scout => sov(bp_config_offset to bp_config_offset + bp_config_l2'length-1), + din => bp_config_d, + dout => bp_config_l2 ); +an_ac_reld_data_vld_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(an_ac_reld_data_vld_offset), + scout => sov(an_ac_reld_data_vld_offset), + din => an_ac_reld_data_vld_d, + dout => an_ac_reld_data_vld_l2 ); +an_ac_reld_core_tag_latch: tri_rlmreg_p + generic map (width => an_ac_reld_core_tag_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(an_ac_reld_core_tag_offset to an_ac_reld_core_tag_offset + an_ac_reld_core_tag_l2'length-1), + scout => sov(an_ac_reld_core_tag_offset to an_ac_reld_core_tag_offset + an_ac_reld_core_tag_l2'length-1), + din => an_ac_reld_core_tag_d, + dout => an_ac_reld_core_tag_l2); +an_ac_reld_qw_latch: tri_rlmreg_p + generic map (width => an_ac_reld_qw_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(an_ac_reld_qw_offset to an_ac_reld_qw_offset + an_ac_reld_qw_l2'length-1), + scout => sov(an_ac_reld_qw_offset to an_ac_reld_qw_offset + an_ac_reld_qw_l2'length-1), + din => an_ac_reld_qw_d, + dout => an_ac_reld_qw_l2); +reld_r1_tid_latch: tri_rlmreg_p + generic map (width => reld_r1_tid_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(reld_r1_tid_offset to reld_r1_tid_offset + reld_r1_tid_l2'length-1), + scout => sov(reld_r1_tid_offset to reld_r1_tid_offset + reld_r1_tid_l2'length-1), + din => reld_r1_tid_d, + dout => reld_r1_tid_l2); +reld_r1_qw_latch: tri_rlmreg_p + generic map (width => reld_r1_qw_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(reld_r1_qw_offset to reld_r1_qw_offset + reld_r1_qw_l2'length-1), + scout => sov(reld_r1_qw_offset to reld_r1_qw_offset + reld_r1_qw_l2'length-1), + din => reld_r1_qw_d, + dout => reld_r1_qw_l2); +an_ac_reld_data_latch: tri_rlmreg_p + generic map (width => an_ac_reld_data_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => reld_r2_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(an_ac_reld_data_offset to an_ac_reld_data_offset + an_ac_reld_data_l2'length-1), + scout => sov(an_ac_reld_data_offset to an_ac_reld_data_offset + an_ac_reld_data_l2'length-1), + din => an_ac_reld_data_d, + dout => an_ac_reld_data_l2); +reld_r2_tid_latch: tri_rlmreg_p + generic map (width => reld_r2_tid_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(reld_r2_tid_offset to reld_r2_tid_offset + reld_r2_tid_l2'length-1), + scout => sov(reld_r2_tid_offset to reld_r2_tid_offset + reld_r2_tid_l2'length-1), + din => reld_r2_tid_d, + dout => reld_r2_tid_l2); +reld_r2_qw_latch: tri_rlmreg_p + generic map (width => reld_r2_qw_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => reld_r2_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(reld_r2_qw_offset to reld_r2_qw_offset + reld_r2_qw_l2'length-1), + scout => sov(reld_r2_qw_offset to reld_r2_qw_offset + reld_r2_qw_l2'length-1), + din => reld_r2_qw_d, + dout => reld_r2_qw_l2); +r2_crit_qw_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(r2_crit_qw_offset), + scout => sov(r2_crit_qw_offset), + din => r2_crit_qw_d, + dout => r2_crit_qw_l2 ); +reld_r3_tid_latch: tri_rlmreg_p + generic map (width => reld_r3_tid_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(reld_r3_tid_offset to reld_r3_tid_offset + reld_r3_tid_l2'length-1), + scout => sov(reld_r3_tid_offset to reld_r3_tid_offset + reld_r3_tid_l2'length-1), + din => reld_r3_tid_d, + dout => reld_r3_tid_l2); +r3_loaded_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(r3_loaded_offset), + scout => sov(r3_loaded_offset), + din => r3_loaded_d, + dout => r3_loaded_l2 ); +r3_need_back_inval_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(r3_need_back_inval_offset), + scout => sov(r3_need_back_inval_offset), + din => r3_need_back_inval_d, + dout => r3_need_back_inval_l2 ); +row_lru_latch: tri_rlmreg_p + generic map (width => row_lru_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(row_lru_offset to row_lru_offset + row_lru_l2'length-1), + scout => sov(row_lru_offset to row_lru_offset + row_lru_l2'length-1), + din => row_lru_d, + dout => row_lru_l2); +row_val_latch: tri_rlmreg_p + generic map (width => row_val_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(row_val_offset to row_val_offset + row_val_l2'length-1), + scout => sov(row_val_offset to row_val_offset + row_val_l2'length-1), + din => row_val_d, + dout => row_val_l2); +an_ac_reld_ecc_err_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(an_ac_reld_ecc_err_offset), + scout => sov(an_ac_reld_ecc_err_offset), + din => an_ac_reld_ecc_err_d, + dout => an_ac_reld_ecc_err_l2 ); +an_ac_reld_ecc_err_ue_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(an_ac_reld_ecc_err_ue_offset), + scout => sov(an_ac_reld_ecc_err_ue_offset), + din => an_ac_reld_ecc_err_ue_d, + dout => an_ac_reld_ecc_err_ue_l2 ); +request_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(request_offset), + scout => sov(request_offset), + din => request_d, + dout => request_l2 ); +req_thread_latch: tri_rlmreg_p + generic map (width => req_thread_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => icd_icm_any_iu2_valid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(req_thread_offset to req_thread_offset + req_thread_l2'length-1), + scout => sov(req_thread_offset to req_thread_offset + req_thread_l2'length-1), + din => req_thread_d, + dout => req_thread_l2); +req_ra_latch: tri_rlmreg_p + generic map (width => req_ra_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => icd_icm_any_iu2_valid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(req_ra_offset to req_ra_offset + req_ra_l2'length-1), + scout => sov(req_ra_offset to req_ra_offset + req_ra_l2'length-1), + din => req_ra_d, + dout => req_ra_l2); +req_wimge_latch: tri_rlmreg_p + generic map (width => req_wimge_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => icd_icm_any_iu2_valid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(req_wimge_offset to req_wimge_offset + req_wimge_l2'length-1), + scout => sov(req_wimge_offset to req_wimge_offset + req_wimge_l2'length-1), + din => req_wimge_d, + dout => req_wimge_l2); +req_userdef_latch: tri_rlmreg_p + generic map (width => req_userdef_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => icd_icm_any_iu2_valid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(req_userdef_offset to req_userdef_offset + req_userdef_l2'length-1), + scout => sov(req_userdef_offset to req_userdef_offset + req_userdef_l2'length-1), + din => req_userdef_d, + dout => req_userdef_l2); +iu3_miss_match_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu3_miss_match_offset), + scout => sov(iu3_miss_match_offset), + din => iu3_miss_match_d, + dout => iu3_miss_match_l2 ); +miss_tid0_sm_a_latch: tri_rlmreg_p + generic map (width => 3, init => 2**(3-1), needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_tid0_sm_offset to miss_tid0_sm_offset + 2), + scout => sov(miss_tid0_sm_offset to miss_tid0_sm_offset + 2), + din => miss_tid0_sm_d(0 to 2), + dout => miss_tid0_sm_l2(0 to 2)); +miss_tid1_sm_a_latch: tri_rlmreg_p + generic map (width => 3, init => 2**(3-1), needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_tid1_sm_offset to miss_tid1_sm_offset + 2), + scout => sov(miss_tid1_sm_offset to miss_tid1_sm_offset + 2), + din => miss_tid1_sm_d(0 to 2), + dout => miss_tid1_sm_l2(0 to 2)); +miss_tid2_sm_a_latch: tri_rlmreg_p + generic map (width => 3, init => 2**(3-1), needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_tid2_sm_offset to miss_tid2_sm_offset + 2), + scout => sov(miss_tid2_sm_offset to miss_tid2_sm_offset + 2), + din => miss_tid2_sm_d(0 to 2), + dout => miss_tid2_sm_l2(0 to 2)); +miss_tid3_sm_a_latch: tri_rlmreg_p + generic map (width => 3, init => 2**(3-1), needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_tid3_sm_offset to miss_tid3_sm_offset + 2), + scout => sov(miss_tid3_sm_offset to miss_tid3_sm_offset + 2), + din => miss_tid3_sm_d(0 to 2), + dout => miss_tid3_sm_l2(0 to 2)); +miss_tid0_sm_b_latch: tri_rlmreg_p + generic map (width => miss_tid0_sm_l2'length-3, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_tid0_sm_offset+3 to miss_tid0_sm_offset + miss_tid0_sm_l2'length-1), + scout => sov(miss_tid0_sm_offset+3 to miss_tid0_sm_offset + miss_tid0_sm_l2'length-1), + din => miss_tid0_sm_d(3 to miss_tid0_sm_l2'length-1), + dout => miss_tid0_sm_l2(3 to miss_tid0_sm_l2'length-1)); +miss_tid1_sm_b_latch: tri_rlmreg_p + generic map (width => miss_tid1_sm_l2'length-3, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_tid1_sm_offset+3 to miss_tid1_sm_offset + miss_tid1_sm_l2'length-1), + scout => sov(miss_tid1_sm_offset+3 to miss_tid1_sm_offset + miss_tid1_sm_l2'length-1), + din => miss_tid1_sm_d(3 to miss_tid1_sm_l2'length-1), + dout => miss_tid1_sm_l2(3 to miss_tid1_sm_l2'length-1)); +miss_tid2_sm_b_latch: tri_rlmreg_p + generic map (width => miss_tid2_sm_l2'length-3, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_tid2_sm_offset+3 to miss_tid2_sm_offset + miss_tid2_sm_l2'length-1), + scout => sov(miss_tid2_sm_offset+3 to miss_tid2_sm_offset + miss_tid2_sm_l2'length-1), + din => miss_tid2_sm_d(3 to miss_tid2_sm_l2'length-1), + dout => miss_tid2_sm_l2(3 to miss_tid2_sm_l2'length-1)); +miss_tid3_sm_b_latch: tri_rlmreg_p + generic map (width => miss_tid3_sm_l2'length-3, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_tid3_sm_offset+3 to miss_tid3_sm_offset + miss_tid3_sm_l2'length-1), + scout => sov(miss_tid3_sm_offset+3 to miss_tid3_sm_offset + miss_tid3_sm_l2'length-1), + din => miss_tid3_sm_d(3 to miss_tid3_sm_l2'length-1), + dout => miss_tid3_sm_l2(3 to miss_tid3_sm_l2'length-1)); +miss_flush_occurred0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_flush_occurred0_offset), + scout => sov(miss_flush_occurred0_offset), + din => miss_flush_occurred0_d, + dout => miss_flush_occurred0_l2 ); +miss_flush_occurred1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_flush_occurred1_offset), + scout => sov(miss_flush_occurred1_offset), + din => miss_flush_occurred1_d, + dout => miss_flush_occurred1_l2 ); +miss_flush_occurred2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_flush_occurred2_offset), + scout => sov(miss_flush_occurred2_offset), + din => miss_flush_occurred2_d, + dout => miss_flush_occurred2_l2 ); +miss_flush_occurred3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_flush_occurred3_offset), + scout => sov(miss_flush_occurred3_offset), + din => miss_flush_occurred3_d, + dout => miss_flush_occurred3_l2 ); +miss_flushed0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_flushed0_offset), + scout => sov(miss_flushed0_offset), + din => miss_flushed0_d, + dout => miss_flushed0_l2 ); +miss_flushed1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_flushed1_offset), + scout => sov(miss_flushed1_offset), + din => miss_flushed1_d, + dout => miss_flushed1_l2 ); +miss_flushed2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_flushed2_offset), + scout => sov(miss_flushed2_offset), + din => miss_flushed2_d, + dout => miss_flushed2_l2 ); +miss_flushed3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_flushed3_offset), + scout => sov(miss_flushed3_offset), + din => miss_flushed3_d, + dout => miss_flushed3_l2 ); +miss_inval0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_inval0_offset), + scout => sov(miss_inval0_offset), + din => miss_inval0_d, + dout => miss_inval0_l2 ); +miss_inval1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_inval1_offset), + scout => sov(miss_inval1_offset), + din => miss_inval1_d, + dout => miss_inval1_l2 ); +miss_inval2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_inval2_offset), + scout => sov(miss_inval2_offset), + din => miss_inval2_d, + dout => miss_inval2_l2 ); +miss_inval3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_inval3_offset), + scout => sov(miss_inval3_offset), + din => miss_inval3_d, + dout => miss_inval3_l2 ); +miss_block_fp0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_block_fp0_offset), + scout => sov(miss_block_fp0_offset), + din => miss_block_fp0_d, + dout => miss_block_fp0_l2 ); +miss_block_fp1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_block_fp1_offset), + scout => sov(miss_block_fp1_offset), + din => miss_block_fp1_d, + dout => miss_block_fp1_l2 ); +miss_block_fp2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_block_fp2_offset), + scout => sov(miss_block_fp2_offset), + din => miss_block_fp2_d, + dout => miss_block_fp2_l2 ); +miss_block_fp3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_block_fp3_offset), + scout => sov(miss_block_fp3_offset), + din => miss_block_fp3_d, + dout => miss_block_fp3_l2 ); +miss_ecc_err0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_ecc_err0_offset), + scout => sov(miss_ecc_err0_offset), + din => miss_ecc_err0_d, + dout => miss_ecc_err0_l2 ); +miss_ecc_err1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_ecc_err1_offset), + scout => sov(miss_ecc_err1_offset), + din => miss_ecc_err1_d, + dout => miss_ecc_err1_l2 ); +miss_ecc_err2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_ecc_err2_offset), + scout => sov(miss_ecc_err2_offset), + din => miss_ecc_err2_d, + dout => miss_ecc_err2_l2 ); +miss_ecc_err3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_ecc_err3_offset), + scout => sov(miss_ecc_err3_offset), + din => miss_ecc_err3_d, + dout => miss_ecc_err3_l2 ); +miss_ecc_err_ue0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_ecc_err_ue0_offset), + scout => sov(miss_ecc_err_ue0_offset), + din => miss_ecc_err_ue0_d, + dout => miss_ecc_err_ue0_l2 ); +miss_ecc_err_ue1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_ecc_err_ue1_offset), + scout => sov(miss_ecc_err_ue1_offset), + din => miss_ecc_err_ue1_d, + dout => miss_ecc_err_ue1_l2 ); +miss_ecc_err_ue2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_ecc_err_ue2_offset), + scout => sov(miss_ecc_err_ue2_offset), + din => miss_ecc_err_ue2_d, + dout => miss_ecc_err_ue2_l2 ); +miss_ecc_err_ue3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_ecc_err_ue3_offset), + scout => sov(miss_ecc_err_ue3_offset), + din => miss_ecc_err_ue3_d, + dout => miss_ecc_err_ue3_l2 ); +miss_wrote_dir0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_wrote_dir0_offset), + scout => sov(miss_wrote_dir0_offset), + din => miss_wrote_dir0_d, + dout => miss_wrote_dir0_l2 ); +miss_wrote_dir1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_wrote_dir1_offset), + scout => sov(miss_wrote_dir1_offset), + din => miss_wrote_dir1_d, + dout => miss_wrote_dir1_l2 ); +miss_wrote_dir2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_wrote_dir2_offset), + scout => sov(miss_wrote_dir2_offset), + din => miss_wrote_dir2_d, + dout => miss_wrote_dir2_l2 ); +miss_wrote_dir3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_wrote_dir3_offset), + scout => sov(miss_wrote_dir3_offset), + din => miss_wrote_dir3_d, + dout => miss_wrote_dir3_l2 ); +miss_need_hold0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_need_hold0_offset), + scout => sov(miss_need_hold0_offset), + din => miss_need_hold0_d, + dout => miss_need_hold0_l2 ); +miss_need_hold1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_need_hold1_offset), + scout => sov(miss_need_hold1_offset), + din => miss_need_hold1_d, + dout => miss_need_hold1_l2 ); +miss_need_hold2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_need_hold2_offset), + scout => sov(miss_need_hold2_offset), + din => miss_need_hold2_d, + dout => miss_need_hold2_l2 ); +miss_need_hold3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_need_hold3_offset), + scout => sov(miss_need_hold3_offset), + din => miss_need_hold3_d, + dout => miss_need_hold3_l2 ); +miss_addr0_real_latch: tri_rlmreg_p + generic map (width => miss_addr0_real_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => miss_act(0), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_addr0_real_offset to miss_addr0_real_offset + miss_addr0_real_l2'length-1), + scout => sov(miss_addr0_real_offset to miss_addr0_real_offset + miss_addr0_real_l2'length-1), + din => miss_addr0_real_d, + dout => miss_addr0_real_l2); +miss_addr1_real_latch: tri_rlmreg_p + generic map (width => miss_addr1_real_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => miss_act(1), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_addr1_real_offset to miss_addr1_real_offset + miss_addr1_real_l2'length-1), + scout => sov(miss_addr1_real_offset to miss_addr1_real_offset + miss_addr1_real_l2'length-1), + din => miss_addr1_real_d, + dout => miss_addr1_real_l2); +miss_addr2_real_latch: tri_rlmreg_p + generic map (width => miss_addr2_real_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => miss_act(2), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_addr2_real_offset to miss_addr2_real_offset + miss_addr2_real_l2'length-1), + scout => sov(miss_addr2_real_offset to miss_addr2_real_offset + miss_addr2_real_l2'length-1), + din => miss_addr2_real_d, + dout => miss_addr2_real_l2); +miss_addr3_real_latch: tri_rlmreg_p + generic map (width => miss_addr3_real_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => miss_act(3), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_addr3_real_offset to miss_addr3_real_offset + miss_addr3_real_l2'length-1), + scout => sov(miss_addr3_real_offset to miss_addr3_real_offset + miss_addr3_real_l2'length-1), + din => miss_addr3_real_d, + dout => miss_addr3_real_l2); +miss_addr0_eff_latch: tri_rlmreg_p + generic map (width => miss_addr0_eff_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => miss_act(0), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_addr0_eff_offset to miss_addr0_eff_offset + miss_addr0_eff_l2'length-1), + scout => sov(miss_addr0_eff_offset to miss_addr0_eff_offset + miss_addr0_eff_l2'length-1), + din => miss_addr0_eff_d, + dout => miss_addr0_eff_l2); +miss_addr1_eff_latch: tri_rlmreg_p + generic map (width => miss_addr1_eff_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => miss_act(1), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_addr1_eff_offset to miss_addr1_eff_offset + miss_addr1_eff_l2'length-1), + scout => sov(miss_addr1_eff_offset to miss_addr1_eff_offset + miss_addr1_eff_l2'length-1), + din => miss_addr1_eff_d, + dout => miss_addr1_eff_l2); +miss_addr2_eff_latch: tri_rlmreg_p + generic map (width => miss_addr2_eff_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => miss_act(2), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_addr2_eff_offset to miss_addr2_eff_offset + miss_addr2_eff_l2'length-1), + scout => sov(miss_addr2_eff_offset to miss_addr2_eff_offset + miss_addr2_eff_l2'length-1), + din => miss_addr2_eff_d, + dout => miss_addr2_eff_l2); +miss_addr3_eff_latch: tri_rlmreg_p + generic map (width => miss_addr3_eff_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => miss_act(3), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_addr3_eff_offset to miss_addr3_eff_offset + miss_addr3_eff_l2'length-1), + scout => sov(miss_addr3_eff_offset to miss_addr3_eff_offset + miss_addr3_eff_l2'length-1), + din => miss_addr3_eff_d, + dout => miss_addr3_eff_l2); +miss_ci0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => miss_act(0), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_ci0_offset), + scout => sov(miss_ci0_offset), + din => miss_ci0_d, + dout => miss_ci0_l2 ); +miss_ci1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => miss_act(1), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_ci1_offset), + scout => sov(miss_ci1_offset), + din => miss_ci1_d, + dout => miss_ci1_l2 ); +miss_ci2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => miss_act(2), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_ci2_offset), + scout => sov(miss_ci2_offset), + din => miss_ci2_d, + dout => miss_ci2_l2 ); +miss_ci3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => miss_act(3), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_ci3_offset), + scout => sov(miss_ci3_offset), + din => miss_ci3_d, + dout => miss_ci3_l2 ); +miss_endian0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => miss_act(0), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_endian0_offset), + scout => sov(miss_endian0_offset), + din => miss_endian0_d, + dout => miss_endian0_l2 ); +miss_endian1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => miss_act(1), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_endian1_offset), + scout => sov(miss_endian1_offset), + din => miss_endian1_d, + dout => miss_endian1_l2 ); +miss_endian2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => miss_act(2), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_endian2_offset), + scout => sov(miss_endian2_offset), + din => miss_endian2_d, + dout => miss_endian2_l2 ); +miss_endian3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => miss_act(3), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_endian3_offset), + scout => sov(miss_endian3_offset), + din => miss_endian3_d, + dout => miss_endian3_l2 ); +miss_2ucode0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => miss_act(0), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_2ucode0_offset), + scout => sov(miss_2ucode0_offset), + din => miss_2ucode0_d, + dout => miss_2ucode0_l2 ); +miss_2ucode1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => miss_act(1), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_2ucode1_offset), + scout => sov(miss_2ucode1_offset), + din => miss_2ucode1_d, + dout => miss_2ucode1_l2 ); +miss_2ucode2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => miss_act(2), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_2ucode2_offset), + scout => sov(miss_2ucode2_offset), + din => miss_2ucode2_d, + dout => miss_2ucode2_l2 ); +miss_2ucode3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => miss_act(3), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_2ucode3_offset), + scout => sov(miss_2ucode3_offset), + din => miss_2ucode3_d, + dout => miss_2ucode3_l2 ); +miss_2ucode0_type_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => miss_act(0), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_2ucode0_type_offset), + scout => sov(miss_2ucode0_type_offset), + din => miss_2ucode0_type_d, + dout => miss_2ucode0_type_l2 ); +miss_2ucode1_type_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => miss_act(1), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_2ucode1_type_offset), + scout => sov(miss_2ucode1_type_offset), + din => miss_2ucode1_type_d, + dout => miss_2ucode1_type_l2 ); +miss_2ucode2_type_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => miss_act(2), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_2ucode2_type_offset), + scout => sov(miss_2ucode2_type_offset), + din => miss_2ucode2_type_d, + dout => miss_2ucode2_type_l2 ); +miss_2ucode3_type_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => miss_act(3), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_2ucode3_type_offset), + scout => sov(miss_2ucode3_type_offset), + din => miss_2ucode3_type_d, + dout => miss_2ucode3_type_l2 ); +miss_way0_latch: tri_rlmreg_p + generic map (width => miss_way0_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => reld_r2_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_way0_offset to miss_way0_offset + miss_way0_l2'length-1), + scout => sov(miss_way0_offset to miss_way0_offset + miss_way0_l2'length-1), + din => miss_way0_d, + dout => miss_way0_l2); +miss_way1_latch: tri_rlmreg_p + generic map (width => miss_way1_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => reld_r2_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_way1_offset to miss_way1_offset + miss_way1_l2'length-1), + scout => sov(miss_way1_offset to miss_way1_offset + miss_way1_l2'length-1), + din => miss_way1_d, + dout => miss_way1_l2); +miss_way2_latch: tri_rlmreg_p + generic map (width => miss_way2_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => reld_r2_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_way2_offset to miss_way2_offset + miss_way2_l2'length-1), + scout => sov(miss_way2_offset to miss_way2_offset + miss_way2_l2'length-1), + din => miss_way2_d, + dout => miss_way2_l2); +miss_way3_latch: tri_rlmreg_p + generic map (width => miss_way3_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => reld_r2_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_way3_offset to miss_way3_offset + miss_way3_l2'length-1), + scout => sov(miss_way3_offset to miss_way3_offset + miss_way3_l2'length-1), + din => miss_way3_d, + dout => miss_way3_l2); +perf_event_t0_latch: tri_rlmreg_p + generic map (width => perf_event_t0_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => event_bus_enable, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(perf_event_t0_offset to perf_event_t0_offset + perf_event_t0_l2'length-1), + scout => sov(perf_event_t0_offset to perf_event_t0_offset + perf_event_t0_l2'length-1), + din => perf_event_t0_d, + dout => perf_event_t0_l2); +perf_event_t1_latch: tri_rlmreg_p + generic map (width => perf_event_t1_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => event_bus_enable, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(perf_event_t1_offset to perf_event_t1_offset + perf_event_t1_l2'length-1), + scout => sov(perf_event_t1_offset to perf_event_t1_offset + perf_event_t1_l2'length-1), + din => perf_event_t1_d, + dout => perf_event_t1_l2); +perf_event_t2_latch: tri_rlmreg_p + generic map (width => perf_event_t2_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => event_bus_enable, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(perf_event_t2_offset to perf_event_t2_offset + perf_event_t2_l2'length-1), + scout => sov(perf_event_t2_offset to perf_event_t2_offset + perf_event_t2_l2'length-1), + din => perf_event_t2_d, + dout => perf_event_t2_l2); +perf_event_t3_latch: tri_rlmreg_p + generic map (width => perf_event_t3_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => event_bus_enable, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(perf_event_t3_offset to perf_event_t3_offset + perf_event_t3_l2'length-1), + scout => sov(perf_event_t3_offset to perf_event_t3_offset + perf_event_t3_l2'length-1), + din => perf_event_t3_d, + dout => perf_event_t3_l2); +lru_write_next_cycle_latch: tri_rlmreg_p + generic map (width => lru_write_next_cycle_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(lru_write_next_cycle_offset to lru_write_next_cycle_offset + lru_write_next_cycle_l2'length-1), + scout => sov(lru_write_next_cycle_offset to lru_write_next_cycle_offset + lru_write_next_cycle_l2'length-1), + din => lru_write_next_cycle_d, + dout => lru_write_next_cycle_l2); +lru_write_latch: tri_rlmreg_p + generic map (width => lru_write_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(lru_write_offset to lru_write_offset + lru_write_l2'length-1), + scout => sov(lru_write_offset to lru_write_offset + lru_write_l2'length-1), + din => lru_write_d, + dout => lru_write_l2); +miss_dbg_data1_latch: tri_rlmreg_p + generic map (width => miss_dbg_data1_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => trace_bus_enable, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_dbg_data1_offset to miss_dbg_data1_offset + miss_dbg_data1_l2'length-1), + scout => sov(miss_dbg_data1_offset to miss_dbg_data1_offset + miss_dbg_data1_l2'length-1), + din => miss_dbg_data1_d, + dout => miss_dbg_data1_l2); +spare_latch: tri_rlmreg_p + generic map (width => spare_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(spare_offset to spare_offset + spare_l2'length-1), + scout => sov(spare_offset to spare_offset + spare_l2'length-1), + din => spare_l2, + dout => spare_l2); +siv(0 TO scan_right) <= sov(1 to scan_right) & scan_in; +scan_out <= sov(0); +END IUQ_IC_MISS; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_ic_select.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_ic_select.vhdl new file mode 100644 index 0000000..253fc21 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_ic_select.vhdl @@ -0,0 +1,1950 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee,ibm,support,tri,work; +use ieee.std_logic_1164.all; +use ibm.std_ulogic_unsigned.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use support.power_logic_pkg.all; +use tri.tri_latches_pkg.all; +use work.iuq_pkg.all; + +entity iuq_ic_select is +generic(expand_type : integer := 2); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + pc_iu_func_sl_thold_0_b : in std_ulogic; + pc_iu_func_slp_sl_thold_0_b: in std_ulogic; + pc_iu_sg_0 : in std_ulogic; + forcee : in std_ulogic; + funcslp_force : in std_ulogic; + d_mode : in std_ulogic; + delay_lclkr : in std_ulogic; + mpw1_b : in std_ulogic; + mpw2_b : in std_ulogic; + an_ac_scan_dis_dc_b : in std_ulogic; + func_scan_in : in std_ulogic; + func_scan_out : out std_ulogic; + + ac_an_power_managed : in std_ulogic; + + xu_iu_run_thread : in std_ulogic_vector(0 to 3); + + xu_iu_flush : in std_ulogic_vector(0 to 3); + xu_iu_iu0_flush_ifar0 : in EFF_IFAR; + xu_iu_iu0_flush_ifar1 : in EFF_IFAR; + xu_iu_iu0_flush_ifar2 : in EFF_IFAR; + xu_iu_iu0_flush_ifar3 : in EFF_IFAR; + xu_iu_flush_2ucode : in std_ulogic_vector(0 to 3); + xu_iu_flush_2ucode_type : in std_ulogic_vector(0 to 3); + + xu_iu_msr_cm : in std_ulogic_vector(0 to 3); + + xu_iu_ex6_icbi_val : in std_ulogic_vector(0 to 3); + xu_iu_ex6_icbi_addr : in std_ulogic_vector(REAL_IFAR'left to 57); + + an_ac_back_inv : in std_ulogic; + an_ac_back_inv_addr : in std_ulogic_vector(REAL_IFAR'left to 57); + an_ac_back_inv_target : in std_ulogic; + + an_ac_icbi_ack : in std_ulogic; + an_ac_icbi_ack_thread : in std_ulogic_vector(0 to 1); + + spr_ic_clockgate_dis : in std_ulogic; + spr_ic_icbi_ack_en : in std_ulogic; + + spr_ic_idir_read : in std_ulogic; + spr_ic_idir_row : in std_ulogic_vector(52 to 57); + + spr_ic_pri_rand : in std_ulogic_vector(0 to 4); + spr_ic_pri_rand_always : in std_ulogic; + spr_ic_pri_rand_flush : in std_ulogic; + + ic_perf_event_t0 : out std_ulogic_vector(2 to 3); + ic_perf_event_t1 : out std_ulogic_vector(2 to 3); + ic_perf_event_t2 : out std_ulogic_vector(2 to 3); + ic_perf_event_t3 : out std_ulogic_vector(2 to 3); + + iu_ierat_iu0_val : out std_ulogic; + iu_ierat_iu0_thdid : out std_ulogic_vector(0 to 3); + iu_ierat_iu0_ifar : out std_ulogic_vector(0 to 51); + iu_ierat_iu0_flush : out std_ulogic_vector(0 to 3); + iu_ierat_iu1_flush : out std_ulogic_vector(0 to 3); + iu_ierat_ium1_back_inv : out std_ulogic; + ierat_iu_hold_req : in std_ulogic_vector(0 to 3); + ierat_iu_iu2_flush_req : in std_ulogic_vector(0 to 3); + ierat_iu_iu2_miss : in std_ulogic; + + icm_ics_iu0_preload_val : in std_ulogic; + icm_ics_iu0_preload_tid : in std_ulogic_vector(0 to 3); + icm_ics_iu0_preload_ifar : in std_ulogic_vector(52 to 59); + + icm_ics_hold_thread : in std_ulogic_vector(0 to 3); + icm_ics_hold_thread_dbg : in std_ulogic_vector(0 to 3); + icm_ics_hold_iu0 : in std_ulogic; + icm_ics_ecc_block_iu0 : in std_ulogic_vector(0 to 3); + icm_ics_load_tid : in std_ulogic_vector(0 to 3); + icm_ics_iu1_ecc_flush : in std_ulogic; + icm_ics_iu2_miss_match_prev: in std_ulogic; + + ics_icm_iu2_flush_tid : out std_ulogic_vector(0 to 3); + ics_icm_iu3_flush_tid : out std_ulogic_vector(0 to 3); + + ics_icm_iu0_ifar0 : out std_ulogic_vector(46 to 52); + ics_icm_iu0_ifar1 : out std_ulogic_vector(46 to 52); + ics_icm_iu0_ifar2 : out std_ulogic_vector(46 to 52); + ics_icm_iu0_ifar3 : out std_ulogic_vector(46 to 52); + + ics_icm_iu0_inval : out std_ulogic; + ics_icm_iu0_inval_addr : out std_ulogic_vector(52 to 57); + + ics_icd_dir_rd_act : out std_ulogic; + ics_icd_data_rd_act : out std_ulogic; + ics_icd_iu0_valid : out std_ulogic; + ics_icd_iu0_tid : out std_ulogic_vector(0 to 3); + ics_icd_iu0_ifar : out EFF_IFAR; + ics_icd_iu0_inval : out std_ulogic; + ics_icd_iu0_2ucode : out std_ulogic; + ics_icd_iu0_2ucode_type : out std_ulogic; + ics_icd_iu0_spr_idir_read : out std_ulogic; + + icd_ics_iu1_valid : in std_ulogic; + icd_ics_iu1_tid : in std_ulogic_vector(0 to 3); + icd_ics_iu1_ifar : in EFF_IFAR; + icd_ics_iu1_2ucode : in std_ulogic; + icd_ics_iu1_2ucode_type : in std_ulogic; + + ics_icd_all_flush_prev : out std_ulogic_vector(0 to 3); + ics_icd_iu1_flush_tid : out std_ulogic_vector(0 to 3); + ics_icd_iu2_flush_tid : out std_ulogic_vector(0 to 3); + icd_ics_iu2_miss_flush_prev: in std_ulogic_vector(0 to 3); + icd_ics_iu2_ifar_eff : in EFF_IFAR; + icd_ics_iu2_2ucode : in std_ulogic; + icd_ics_iu2_2ucode_type : in std_ulogic; + icd_ics_iu3_parity_flush : in std_ulogic_vector(0 to 3); + icd_ics_iu3_ifar : in EFF_IFAR; + icd_ics_iu3_2ucode : in std_ulogic; + icd_ics_iu3_2ucode_type : in std_ulogic; + + ic_bp_iu1_val : out std_ulogic; + ic_bp_iu1_tid : out std_ulogic_vector(0 to 3); + ic_bp_iu1_ifar : out std_ulogic_vector(52 to 59); + + bp_ib_iu4_ifar : in EFF_IFAR; + + bp_ic_iu5_hold_tid : in std_ulogic_vector(0 to 3); + bp_ic_iu5_redirect_tid : in std_ulogic_vector(0 to 3); + bp_ic_iu5_redirect_ifar : in EFF_IFAR; + + ib_ic_empty : in std_ulogic_vector(0 to 3); + ib_ic_below_water : in std_ulogic_vector(0 to 3); + ib_ic_iu5_redirect_tid : in std_ulogic_vector(0 to 3); + + ic_fdep_icbi_ack : out std_ulogic_vector(0 to 3); + + uc_flush_tid : in std_ulogic_vector(0 to 3); + uc_ic_hold_thread : in std_ulogic_vector(0 to 3); + + event_bus_enable : in std_ulogic; + sel_dbg_data : out std_ulogic_vector(0 to 87) +); +-- synopsys translate_off +-- synopsys translate_on +end iuq_ic_select; +ARCHITECTURE IUQ_IC_SELECT + OF IUQ_IC_SELECT + IS +constant an_ac_back_inv_offset : natural := 0; +constant an_ac_back_inv_target_offset : natural := an_ac_back_inv_offset + 1; +constant an_ac_back_inv_addr_offset : natural := an_ac_back_inv_target_offset + 1; +constant back_inv_offset : natural := an_ac_back_inv_addr_offset + REAL_IFAR'length - 4; +constant back_inv_clone_offset : natural := back_inv_offset + 1; +constant an_ac_icbi_ack_offset : natural := back_inv_clone_offset + 1; +constant an_ac_icbi_ack_thread_offset : natural := an_ac_icbi_ack_offset + 1; +constant xu_icbi_buffer0_val_tid_offset : natural := an_ac_icbi_ack_thread_offset + 2; +constant xu_icbi_buffer0_addr_offset : natural := xu_icbi_buffer0_val_tid_offset + 4; +constant xu_icbi_buffer1_val_tid_offset : natural := xu_icbi_buffer0_addr_offset + REAL_IFAR'length - 4; +constant xu_icbi_buffer1_addr_offset : natural := xu_icbi_buffer1_val_tid_offset + 4; +constant xu_icbi_buffer2_val_tid_offset : natural := xu_icbi_buffer1_addr_offset + REAL_IFAR'length - 4; +constant xu_icbi_buffer2_addr_offset : natural := xu_icbi_buffer2_val_tid_offset + 4; +constant xu_icbi_buffer3_val_tid_offset : natural := xu_icbi_buffer2_addr_offset + REAL_IFAR'length - 4; +constant xu_icbi_buffer3_addr_offset : natural := xu_icbi_buffer3_val_tid_offset + 4; +constant xu_iu_run_thread_offset : natural := xu_icbi_buffer3_addr_offset + REAL_IFAR'length - 4; +constant all_stages_flush_prev_offset : natural := xu_iu_run_thread_offset + 4; +constant spare_offset : natural := all_stages_flush_prev_offset + 4; +constant iu0_ifar0_offset : natural := spare_offset + 12; +constant iu0_ifar1_offset : natural := iu0_ifar0_offset + EFF_IFAR'length; +constant iu0_ifar2_offset : natural := iu0_ifar1_offset + EFF_IFAR'length; +constant iu0_ifar3_offset : natural := iu0_ifar2_offset + EFF_IFAR'length; +constant iu0_2ucode_offset : natural := iu0_ifar3_offset + EFF_IFAR'length; +constant iu0_2ucode_type_offset : natural := iu0_2ucode_offset + 4; +constant iu0_high_sent1_offset : natural := iu0_2ucode_type_offset + 4; +constant iu0_high_sent2_offset : natural := iu0_high_sent1_offset + 4; +constant iu0_high_sent3_offset : natural := iu0_high_sent2_offset + 4; +constant iu0_high_sent4_offset : natural := iu0_high_sent3_offset + 4; +constant high_mask_offset : natural := iu0_high_sent4_offset + 4; +constant iu0_low_sent1_offset : natural := high_mask_offset + 4; +constant iu0_low_sent2_offset : natural := iu0_low_sent1_offset + 4; +constant iu0_low_sent3_offset : natural := iu0_low_sent2_offset + 4; +constant iu0_low_sent4_offset : natural := iu0_low_sent3_offset + 4; +constant low_mask_offset : natural := iu0_low_sent4_offset + 4; +constant iu1_bp_val_offset : natural := low_mask_offset + 4; +constant iu1_bp_ifar_offset : natural := iu1_bp_val_offset + 1; +constant iu5_ifar_offset : natural := iu1_bp_ifar_offset + 8; +constant perf_event_t0_offset : natural := iu5_ifar_offset + EFF_IFAR'length; +constant perf_event_t1_offset : natural := perf_event_t0_offset + 2; +constant perf_event_t2_offset : natural := perf_event_t1_offset + 2; +constant perf_event_t3_offset : natural := perf_event_t2_offset + 2; +constant pri_took_offset : natural := perf_event_t3_offset + 2; +constant spr_ic_icbi_ack_en_offset : natural := pri_took_offset + 12; +constant spr_idir_read_offset : natural := spr_ic_icbi_ack_en_offset + 1; +constant spr_idir_row_offset : natural := spr_idir_read_offset + 1; +constant xu_iu_flush_offset : natural := spr_idir_row_offset + 6; +constant scan_right : natural := xu_iu_flush_offset + 4 - 1; +subtype s3 is std_ulogic_vector(0 to 2); +signal tiup : std_ulogic; +signal an_ac_back_inv_d : std_ulogic; +signal an_ac_back_inv_l2 : std_ulogic; +signal an_ac_back_inv_target_d : std_ulogic; +signal an_ac_back_inv_target_l2 : std_ulogic; +signal an_ac_back_inv_addr_d : std_ulogic_vector(REAL_IFAR'left to 57); +signal an_ac_back_inv_addr_l2 : std_ulogic_vector(REAL_IFAR'left to 57); +signal back_inv_d : std_ulogic; +signal back_inv_l2 : std_ulogic; +signal back_inv_l2_clone : std_ulogic; +signal an_ac_icbi_ack_d : std_ulogic; +signal an_ac_icbi_ack_l2 : std_ulogic; +signal an_ac_icbi_ack_thread_d : std_ulogic_vector(0 to 1); +signal an_ac_icbi_ack_thread_l2 : std_ulogic_vector(0 to 1); +signal xu_icbi_buffer0_val_tid_d : std_ulogic_vector(0 to 3); +signal xu_icbi_buffer0_val_tid_l2 : std_ulogic_vector(0 to 3); +signal xu_icbi_buffer1_val_tid_d : std_ulogic_vector(0 to 3); +signal xu_icbi_buffer1_val_tid_l2 : std_ulogic_vector(0 to 3); +signal xu_icbi_buffer2_val_tid_d : std_ulogic_vector(0 to 3); +signal xu_icbi_buffer2_val_tid_l2 : std_ulogic_vector(0 to 3); +signal xu_icbi_buffer3_val_tid_d : std_ulogic_vector(0 to 3); +signal xu_icbi_buffer3_val_tid_l2 : std_ulogic_vector(0 to 3); +signal xu_icbi_buffer0_addr_d : std_ulogic_vector(REAL_IFAR'left to 57); +signal xu_icbi_buffer0_addr_l2 : std_ulogic_vector(REAL_IFAR'left to 57); +signal xu_icbi_buffer1_addr_d : std_ulogic_vector(REAL_IFAR'left to 57); +signal xu_icbi_buffer1_addr_l2 : std_ulogic_vector(REAL_IFAR'left to 57); +signal xu_icbi_buffer2_addr_d : std_ulogic_vector(REAL_IFAR'left to 57); +signal xu_icbi_buffer2_addr_l2 : std_ulogic_vector(REAL_IFAR'left to 57); +signal xu_icbi_buffer3_addr_d : std_ulogic_vector(REAL_IFAR'left to 57); +signal xu_icbi_buffer3_addr_l2 : std_ulogic_vector(REAL_IFAR'left to 57); +signal xu_iu_run_thread_d : std_ulogic_vector(0 to 3); +signal xu_iu_run_thread_l2 : std_ulogic_vector(0 to 3); +signal iu5_ifar_d : EFF_IFAR; +signal iu5_ifar_l2 : EFF_IFAR; +signal all_stages_flush_prev_d : std_ulogic_vector(0 to 3); +signal all_stages_flush_prev_l2 : std_ulogic_vector(0 to 3); +signal iu0_ifar0_d : EFF_IFAR; +signal iu0_ifar0_l2 : EFF_IFAR; +signal iu0_ifar1_d : EFF_IFAR; +signal iu0_ifar1_l2 : EFF_IFAR; +signal iu0_ifar2_d : EFF_IFAR; +signal iu0_ifar2_l2 : EFF_IFAR; +signal iu0_ifar3_d : EFF_IFAR; +signal iu0_ifar3_l2 : EFF_IFAR; +signal iu0_2ucode_d : std_ulogic_vector(0 to 3); +signal iu0_2ucode_l2 : std_ulogic_vector(0 to 3); +signal iu0_2ucode_type_d : std_ulogic_vector(0 to 3); +signal iu0_2ucode_type_l2 : std_ulogic_vector(0 to 3); +signal iu0_high_sent1_d : std_ulogic_vector(0 to 3); +signal iu0_high_sent1_l2 : std_ulogic_vector(0 to 3); +signal iu0_low_sent1_d : std_ulogic_vector(0 to 3); +signal iu0_low_sent1_l2 : std_ulogic_vector(0 to 3); +signal iu0_high_sent2_d : std_ulogic_vector(0 to 3); +signal iu0_high_sent2_l2 : std_ulogic_vector(0 to 3); +signal iu0_low_sent2_d : std_ulogic_vector(0 to 3); +signal iu0_low_sent2_l2 : std_ulogic_vector(0 to 3); +signal iu0_high_sent3_d : std_ulogic_vector(0 to 3); +signal iu0_high_sent3_l2 : std_ulogic_vector(0 to 3); +signal iu0_low_sent3_d : std_ulogic_vector(0 to 3); +signal iu0_low_sent3_l2 : std_ulogic_vector(0 to 3); +signal iu0_high_sent4_d : std_ulogic_vector(0 to 3); +signal iu0_high_sent4_l2 : std_ulogic_vector(0 to 3); +signal iu0_low_sent4_d : std_ulogic_vector(0 to 3); +signal iu0_low_sent4_l2 : std_ulogic_vector(0 to 3); +signal high_mask_d : std_ulogic_vector(0 to 3); +signal high_mask_l2 : std_ulogic_vector(0 to 3); +signal low_mask_d : std_ulogic_vector(0 to 3); +signal low_mask_l2 : std_ulogic_vector(0 to 3); +signal iu1_bp_val_d : std_ulogic; +signal iu1_bp_val_l2 : std_ulogic; +signal iu1_bp_tid_d : std_ulogic_vector(0 to 3); +signal iu1_bp_ifar_d : std_ulogic_vector(52 to 59); +signal iu1_bp_ifar_l2 : std_ulogic_vector(52 to 59); +signal perf_event_t0_d : std_ulogic_vector(2 to 3); +signal perf_event_t0_l2 : std_ulogic_vector(2 to 3); +signal perf_event_t1_d : std_ulogic_vector(2 to 3); +signal perf_event_t1_l2 : std_ulogic_vector(2 to 3); +signal perf_event_t2_d : std_ulogic_vector(2 to 3); +signal perf_event_t2_l2 : std_ulogic_vector(2 to 3); +signal perf_event_t3_d : std_ulogic_vector(2 to 3); +signal perf_event_t3_l2 : std_ulogic_vector(2 to 3); +signal spr_ic_icbi_ack_en_l2 : std_ulogic; +signal spr_idir_read_d : std_ulogic; +signal spr_idir_read_l2 : std_ulogic; +signal spr_idir_row_d : std_ulogic_vector(52 to 57); +signal spr_idir_row_l2 : std_ulogic_vector(52 to 57); +signal xu_iu_flush_l2 : std_ulogic_vector(0 to 3); +signal spare_l2 : std_ulogic_vector(0 to 11); +signal back_inv : std_ulogic; +signal iu5_act : std_ulogic; +signal iu0_high_act : std_ulogic; +signal iu0_low_act : std_ulogic; +signal xu_icbi_buffer0_act : std_ulogic; +signal xu_icbi_buffer123_act : std_ulogic; +signal xu_icbi_buffer_val : std_ulogic_vector(0 to 3); +signal l2_icbi_ack : std_ulogic_vector(0 to 3); +signal block_spr_idir_read : std_ulogic; +signal iu0_spr_idir_read : std_ulogic; +signal iu1_icm_flush_tid : std_ulogic_vector(0 to 3); +signal hold_iu0_v : std_ulogic_vector(0 to 3); +signal iu0_hold_ecc : std_ulogic; +signal iu0_hold_ecc_v : std_ulogic_vector(0 to 3); +signal all_stages_flush_tid : std_ulogic_vector(0 to 3); +signal iu0_flush_tid : std_ulogic_vector(0 to 3); +signal iu1_flush_tid : std_ulogic_vector(0 to 3); +signal iu2_flush_tid : std_ulogic_vector(0 to 3); +signal iu3_flush_tid : std_ulogic_vector(0 to 3); +signal hold_thread_pre_iu0 : std_ulogic_vector(0 to 3); +signal hold_thread_iu0 : std_ulogic_vector(0 to 3); +signal next_high_valid : std_ulogic; +signal next_low_valid : std_ulogic; +signal next_tid : std_ulogic_vector(0 to 3); +signal iu0_ifar0_early : EFF_IFAR; +signal iu0_ifar1_early : EFF_IFAR; +signal iu0_ifar2_early : EFF_IFAR; +signal iu0_ifar3_early : EFF_IFAR; +signal iu0_ifar0_pre_cm : EFF_IFAR; +signal iu0_ifar1_pre_cm : EFF_IFAR; +signal iu0_ifar2_pre_cm : EFF_IFAR; +signal iu0_ifar3_pre_cm : EFF_IFAR; +signal iu0_2ucode_early : std_ulogic_vector(0 to 3); +signal iu0_2ucode_type_early : std_ulogic_vector(0 to 3); +signal iu0_early_valid : std_ulogic; +signal iu0_valid : std_ulogic; +signal iu0_high_sentall4 : std_ulogic_vector(0 to 3); +signal iu0_low_sentall4 : std_ulogic_vector(0 to 3); +signal back_inv_addr_ext : std_ulogic_vector(EFF_IFAR'left to 57); +signal xu_icbi_addr_ext : std_ulogic_vector(EFF_IFAR'left to 57); +signal iu0_inval : std_ulogic; +signal iu0_ifar0_or_back_inv_addr: EFF_IFAR; +signal select_iu0_ifar0 : std_ulogic; +signal iu0_ifar : EFF_IFAR; +signal iu0_2ucode : std_ulogic; +signal iu0_2ucode_type : std_ulogic; +signal iu1_bp_act : std_ulogic; +signal siv : std_ulogic_vector(0 to scan_right); +signal sov : std_ulogic_vector(0 to scan_right); +-- synopsys translate_off +-- synopsys translate_on +signal hi_did3no0_d : std_ulogic; +signal hi_did3no1_d : std_ulogic; +signal hi_did3no2_d : std_ulogic; +signal hi_did2no0_d : std_ulogic; +signal hi_did2no1_d : std_ulogic; +signal hi_did1no0_d : std_ulogic; +signal md_did3no0_d : std_ulogic; +signal md_did3no1_d : std_ulogic; +signal md_did3no2_d : std_ulogic; +signal md_did2no0_d : std_ulogic; +signal md_did2no1_d : std_ulogic; +signal md_did1no0_d : std_ulogic; +signal hi_n230, hi_n231, hi_n232 : std_ulogic; +signal hi_n220, hi_n221, hi_n210 : std_ulogic; +signal md_n230, md_n231, md_n232 : std_ulogic; +signal md_n220, md_n221, md_n210 : std_ulogic; +signal medpri_v, medpri_v_b, highpri_v, highpri_v_b : std_ulogic_vector(0 to 3); +signal medpri_v_b0, highpri_v_b0 : std_ulogic_vector(0 to 3); +signal hi_did0no1, hi_did0no2, hi_did0no3 : std_ulogic; +signal hi_did1no0, hi_did1no2, hi_did1no3 : std_ulogic; +signal hi_did2no1, hi_did2no0, hi_did2no3 : std_ulogic; +signal hi_did3no1, hi_did3no2, hi_did3no0 : std_ulogic; +signal md_did0no1, md_did0no2, md_did0no3 : std_ulogic; +signal md_did1no0, md_did1no2, md_did1no3 : std_ulogic; +signal md_did2no1, md_did2no0, md_did2no3 : std_ulogic; +signal md_did3no1, md_did3no2, md_did3no0 : std_ulogic; +signal hi_sel, hi_sel_b, md_sel, md_sel_b, hi_later, md_later : std_ulogic_vector(0 to 3); +signal hi_did3no0_din : std_ulogic; +signal hi_did3no1_din : std_ulogic; +signal hi_did3no2_din : std_ulogic; +signal hi_did2no0_din : std_ulogic; +signal hi_did2no1_din : std_ulogic; +signal hi_did1no0_din : std_ulogic; +signal md_did3no0_din : std_ulogic; +signal md_did3no1_din : std_ulogic; +signal md_did3no2_din : std_ulogic; +signal md_did2no0_din : std_ulogic; +signal md_did2no1_din : std_ulogic; +signal md_did1no0_din : std_ulogic; +signal issselhi_b, issselmd_b : std_ulogic_vector(0 to 3); +signal no_hi_v,no_hi_v_n01, no_hi_v_n23 : std_ulogic; +signal hi_l30, hi_l31, hi_l32 : std_ulogic; +signal hi_l23, hi_l20, hi_l21 : std_ulogic; +signal hi_l12, hi_l13, hi_l10 : std_ulogic; +signal hi_l01, hi_l02, hi_l03 : std_ulogic; +signal md_l30, md_l31, md_l32 : std_ulogic; +signal md_l23, md_l20, md_l21 : std_ulogic; +signal md_l12, md_l13, md_l10 : std_ulogic; +signal md_l01, md_l02, md_l03 : std_ulogic; +signal no_hi_v_b : std_ulogic; +signal pri_rand : std_ulogic_vector(0 to 5); +-- synopsys translate_off +-- synopsys translate_on + BEGIN + +tiup <= '1'; +xu_iu_run_thread_d <= xu_iu_run_thread; +iu5_ifar_d <= bp_ib_iu4_ifar; +iu5_act <= spr_ic_clockgate_dis or or_reduce(iu0_high_sent4_l2) or or_reduce(iu0_low_sent4_l2); +an_ac_back_inv_d <= an_ac_back_inv; +an_ac_back_inv_target_d <= an_ac_back_inv_target; +an_ac_back_inv_addr_d <= an_ac_back_inv_addr; +back_inv <= an_ac_back_inv_l2 and an_ac_back_inv_target_l2; +back_inv_d <= back_inv; +iu_ierat_ium1_back_inv <= back_inv or (or_reduce(xu_icbi_buffer0_val_tid_d)); +an_ac_icbi_ack_d <= an_ac_icbi_ack; +an_ac_icbi_ack_thread_d <= an_ac_icbi_ack_thread; +iu0_high_act <= spr_ic_clockgate_dis or + or_reduce(high_mask_l2 or iu0_high_sent1_l2 or iu0_high_sent2_l2 or + iu0_high_sent3_l2 or iu0_high_sent4_l2); +iu0_low_act <= spr_ic_clockgate_dis or + or_reduce((low_mask_l2 and not high_mask_l2) or iu0_low_sent1_l2 or iu0_low_sent2_l2 or + iu0_low_sent3_l2 or iu0_low_sent4_l2 or icm_ics_load_tid); +xu_icbi_buffer123_act <= (xu_icbi_buffer_val(0) and back_inv_l2) or xu_icbi_buffer_val(1); +xu_icbi_buffer0_act <= not (xu_icbi_buffer_val(0) and back_inv_l2); +xu_icbi_buffer_val(0) <= or_reduce(xu_icbi_buffer0_val_tid_l2); +xu_icbi_buffer_val(1) <= or_reduce(xu_icbi_buffer1_val_tid_l2); +xu_icbi_buffer_val(2) <= or_reduce(xu_icbi_buffer2_val_tid_l2); +xu_icbi_buffer_val(3) <= or_reduce(xu_icbi_buffer3_val_tid_l2); +xu_icbi_buffer0_val_tid_d <= xu_icbi_buffer0_val_tid_l2 when (xu_icbi_buffer_val(0) and back_inv_l2) = '1' + else xu_icbi_buffer1_val_tid_l2 when (xu_icbi_buffer_val(1) and not back_inv_l2) = '1' + else xu_iu_ex6_icbi_val; +xu_icbi_buffer1_val_tid_d <= xu_iu_ex6_icbi_val when ((xu_icbi_buffer_val(0) and not xu_icbi_buffer_val(1) and back_inv_l2) or + (xu_icbi_buffer_val(1) and not xu_icbi_buffer_val(2) and not back_inv_l2)) = '1' + else xu_icbi_buffer2_val_tid_l2 when (xu_icbi_buffer_val(2) and not back_inv_l2) = '1' + else xu_icbi_buffer1_val_tid_l2; +xu_icbi_buffer2_val_tid_d <= xu_iu_ex6_icbi_val when ((xu_icbi_buffer_val(1) and not xu_icbi_buffer_val(2) and back_inv_l2) or + (xu_icbi_buffer_val(2) and not xu_icbi_buffer_val(3) and not back_inv_l2)) = '1' + else xu_icbi_buffer3_val_tid_l2 when (xu_icbi_buffer_val(3) and not back_inv_l2) = '1' + else xu_icbi_buffer2_val_tid_l2; +xu_icbi_buffer3_val_tid_d <= xu_iu_ex6_icbi_val when (xu_icbi_buffer_val(2) and not xu_icbi_buffer_val(3) and back_inv_l2) = '1' + else xu_icbi_buffer3_val_tid_l2 when back_inv_l2 = '1' + else "0000"; +xu_icbi_buffer0_addr_d <= + xu_icbi_buffer1_addr_l2 when (xu_icbi_buffer_val(1) and not back_inv_l2) = '1' + else xu_iu_ex6_icbi_addr; +xu_icbi_buffer1_addr_d <= xu_iu_ex6_icbi_addr when ((xu_icbi_buffer_val(0) and not xu_icbi_buffer_val(1) and back_inv_l2) or + (xu_icbi_buffer_val(1) and not xu_icbi_buffer_val(2) and not back_inv_l2)) = '1' + else xu_icbi_buffer2_addr_l2 when (xu_icbi_buffer_val(2) and not back_inv_l2) = '1' + else xu_icbi_buffer1_addr_l2; +xu_icbi_buffer2_addr_d <= xu_iu_ex6_icbi_addr when ((xu_icbi_buffer_val(1) and not xu_icbi_buffer_val(2) and back_inv_l2) or + (xu_icbi_buffer_val(2) and not xu_icbi_buffer_val(3) and not back_inv_l2)) = '1' + else xu_icbi_buffer3_addr_l2 when (xu_icbi_buffer_val(3) and not back_inv_l2) = '1' + else xu_icbi_buffer2_addr_l2; +xu_icbi_buffer3_addr_d <= xu_iu_ex6_icbi_addr when (xu_icbi_buffer_val(2) and not xu_icbi_buffer_val(3) and back_inv_l2) = '1' + else xu_icbi_buffer3_addr_l2; + WITH s3'(an_ac_icbi_ack_l2 & an_ac_icbi_ack_thread_l2(0 to 1)) SELECT l2_icbi_ack <= "1000" when "100", + "0100" when "101", + "0010" when "110", + "0001" when "111", + "0000" when others; +ic_fdep_icbi_ack <= l2_icbi_ack when spr_ic_icbi_ack_en_l2 = '1' + else "0000" when back_inv_l2 = '1' + else xu_icbi_buffer0_val_tid_l2; +block_spr_idir_read <= iu0_inval or icm_ics_hold_iu0; +spr_idir_read_d <= spr_ic_idir_read or + (spr_idir_read_l2 and block_spr_idir_read); +spr_idir_row_d <= spr_ic_idir_row; +iu0_spr_idir_read <= spr_idir_read_l2 and not block_spr_idir_read; +ics_icd_iu0_spr_idir_read <= iu0_spr_idir_read; +iu1_icm_flush_tid <= (gate_and( (icd_ics_iu1_valid and icm_ics_iu1_ecc_flush) , icd_ics_iu1_tid)) and not all_stages_flush_prev_l2; +hold_iu0_v <= ( 0 to 3 => icm_ics_hold_iu0); +iu0_hold_ecc <= icm_ics_iu1_ecc_flush; +iu0_hold_ecc_v <= ( 0 to 3 => icm_ics_iu1_ecc_flush); +iu_ierat_iu0_flush <= uc_flush_tid or ib_ic_iu5_redirect_tid or bp_ic_iu5_redirect_tid or + icd_ics_iu3_parity_flush or icd_ics_iu2_miss_flush_prev or iu1_icm_flush_tid or + hold_thread_iu0 or hold_iu0_v or iu0_hold_ecc_v; +iu_ierat_iu1_flush <= uc_flush_tid or ib_ic_iu5_redirect_tid or bp_ic_iu5_redirect_tid or + icd_ics_iu3_parity_flush or icd_ics_iu2_miss_flush_prev or iu1_icm_flush_tid; +all_stages_flush_tid <= xu_iu_flush or uc_flush_tid or ib_ic_iu5_redirect_tid or bp_ic_iu5_redirect_tid; +all_stages_flush_prev_d <= all_stages_flush_tid; +iu0_flush_tid <= icd_ics_iu3_parity_flush or ierat_iu_iu2_flush_req or icd_ics_iu2_miss_flush_prev or iu1_icm_flush_tid; +iu1_flush_tid <= icd_ics_iu3_parity_flush or ierat_iu_iu2_flush_req or icd_ics_iu2_miss_flush_prev or iu1_icm_flush_tid; +iu2_flush_tid(0) <= icd_ics_iu3_parity_flush(0) or (ierat_iu_iu2_flush_req(0) and not ierat_iu_iu2_miss); +iu2_flush_tid(1) <= icd_ics_iu3_parity_flush(1) or (ierat_iu_iu2_flush_req(1) and not ierat_iu_iu2_miss); +iu2_flush_tid(2) <= icd_ics_iu3_parity_flush(2) or (ierat_iu_iu2_flush_req(2) and not ierat_iu_iu2_miss); +iu2_flush_tid(3) <= icd_ics_iu3_parity_flush(3) or (ierat_iu_iu2_flush_req(3) and not ierat_iu_iu2_miss); +iu3_flush_tid <= icd_ics_iu3_parity_flush; +ics_icd_all_flush_prev <= all_stages_flush_prev_l2; +ics_icd_iu1_flush_tid <= iu1_flush_tid; +ics_icd_iu2_flush_tid <= iu2_flush_tid; +ics_icm_iu2_flush_tid <= iu2_flush_tid or all_stages_flush_tid; +ics_icm_iu3_flush_tid <= all_stages_flush_tid; +hold_thread_pre_iu0(0) <= uc_ic_hold_thread(0) or uc_flush_tid(0) or + (bp_ic_iu5_hold_tid(0) and not xu_iu_flush(0)) or + icm_ics_hold_thread(0); +hold_thread_pre_iu0(1) <= uc_ic_hold_thread(1) or uc_flush_tid(1) or + (bp_ic_iu5_hold_tid(1) and not xu_iu_flush(1)) or + icm_ics_hold_thread(1); +hold_thread_pre_iu0(2) <= uc_ic_hold_thread(2) or uc_flush_tid(2) or + (bp_ic_iu5_hold_tid(2) and not xu_iu_flush(2)) or + icm_ics_hold_thread(2); +hold_thread_pre_iu0(3) <= uc_ic_hold_thread(3) or uc_flush_tid(3) or + (bp_ic_iu5_hold_tid(3) and not xu_iu_flush(3)) or + icm_ics_hold_thread(3); +hold_thread_iu0(0) <= not(xu_iu_run_thread_l2(0)) or ac_an_power_managed or ierat_iu_hold_req(0) or icm_ics_ecc_block_iu0(0); +hold_thread_iu0(1) <= not(xu_iu_run_thread_l2(1)) or ac_an_power_managed or ierat_iu_hold_req(1) or icm_ics_ecc_block_iu0(1); +hold_thread_iu0(2) <= not(xu_iu_run_thread_l2(2)) or ac_an_power_managed or ierat_iu_hold_req(2) or icm_ics_ecc_block_iu0(2); +hold_thread_iu0(3) <= not(xu_iu_run_thread_l2(3)) or ac_an_power_managed or ierat_iu_hold_req(3) or icm_ics_ecc_block_iu0(3); +high_mask_d(0) <= ((ib_ic_empty(0) and not iu0_high_sentall4(0)) or xu_iu_flush(0)) + and not hold_thread_pre_iu0(0) and not hold_thread_iu0(0) and not back_inv and not (or_reduce(xu_icbi_buffer0_val_tid_d)) and not spr_idir_read_d; +high_mask_d(1) <= ((ib_ic_empty(1) and not iu0_high_sentall4(1)) or xu_iu_flush(1)) + and not hold_thread_pre_iu0(1) and not hold_thread_iu0(1) and not back_inv and not (or_reduce(xu_icbi_buffer0_val_tid_d)) and not spr_idir_read_d; +high_mask_d(2) <= ((ib_ic_empty(2) and not iu0_high_sentall4(2)) or xu_iu_flush(2)) + and not hold_thread_pre_iu0(2) and not hold_thread_iu0(2) and not back_inv and not (or_reduce(xu_icbi_buffer0_val_tid_d)) and not spr_idir_read_d; +high_mask_d(3) <= ((ib_ic_empty(3) and not iu0_high_sentall4(3)) or xu_iu_flush(3)) + and not hold_thread_pre_iu0(3) and not hold_thread_iu0(3) and not back_inv and not (or_reduce(xu_icbi_buffer0_val_tid_d)) and not spr_idir_read_d; +low_mask_d(0) <= ib_ic_below_water(0) and not iu0_low_sentall4(0) and + (ib_ic_empty(0) or not iu0_high_sentall4(0)) and + not hold_thread_pre_iu0(0) and not hold_thread_iu0(0) and not back_inv and not (or_reduce(xu_icbi_buffer0_val_tid_d)) and not spr_idir_read_d; +low_mask_d(1) <= ib_ic_below_water(1) and not iu0_low_sentall4(1) and + (ib_ic_empty(1) or not iu0_high_sentall4(1)) and + not hold_thread_pre_iu0(1) and not hold_thread_iu0(1) and not back_inv and not (or_reduce(xu_icbi_buffer0_val_tid_d)) and not spr_idir_read_d; +low_mask_d(2) <= ib_ic_below_water(2) and not iu0_low_sentall4(2) and + (ib_ic_empty(2) or not iu0_high_sentall4(2)) and + not hold_thread_pre_iu0(2) and not hold_thread_iu0(2) and not back_inv and not (or_reduce(xu_icbi_buffer0_val_tid_d)) and not spr_idir_read_d; +low_mask_d(3) <= ib_ic_below_water(3) and not iu0_low_sentall4(3) and + (ib_ic_empty(3) or not iu0_high_sentall4(3)) and + not hold_thread_pre_iu0(3) and not hold_thread_iu0(3) and not back_inv and not (or_reduce(xu_icbi_buffer0_val_tid_d)) and not spr_idir_read_d; +next_low_valid <= or_reduce(low_mask_l2) and not or_reduce(high_mask_l2); +next_high_valid <= or_reduce(high_mask_l2); +highpri_v_b0 <= not high_mask_l2; +medpri_v_b0 <= not low_mask_l2; +highpri0v_inv: highpri_v(0) <= not highpri_v_b0(0); +highpri1v_inv: highpri_v(1) <= not highpri_v_b0(1); +highpri2v_inv: highpri_v(2) <= not highpri_v_b0(2); +highpri3v_inv: highpri_v(3) <= not highpri_v_b0(3); +highpri0vb_inv: highpri_v_b(0) <= not highpri_v(0); +highpri1vb_inv: highpri_v_b(1) <= not highpri_v(1); +highpri2vb_inv: highpri_v_b(2) <= not highpri_v(2); +highpri3vb_inv: highpri_v_b(3) <= not highpri_v(3); +hi_sel_nor23: hi_sel(3) <= not (highpri_v_b(3) or hi_later(3)); +hi_sel_nand33: hi_later(3) <= not (hi_l30 and hi_l31 and hi_l32); +hi_sel_nand230: hi_l30 <= not (hi_did3no0 and highpri_v(0)); +hi_sel_nand231: hi_l31 <= not (hi_did3no1 and highpri_v(1)); +hi_sel_nand232: hi_l32 <= not (hi_did3no2 and highpri_v(2)); +hi_sel_nor22: hi_sel(2) <= not (highpri_v_b(2) or hi_later(2)); +hi_sel_nand32: hi_later(2) <= not (hi_l23 and hi_l20 and hi_l21); +hi_sel_nand223: hi_l23 <= not (hi_did2no3 and highpri_v(3)); +hi_sel_nand220: hi_l20 <= not (hi_did2no0 and highpri_v(0)); +hi_sel_nand221: hi_l21 <= not (hi_did2no1 and highpri_v(1)); +hi_sel_nor21: hi_sel(1) <= not (highpri_v_b(1) or hi_later(1)); +hi_sel_nand31: hi_later(1) <= not (hi_l12 and hi_l13 and hi_l10); +hi_sel_nand212: hi_l12 <= not (hi_did1no2 and highpri_v(2)); +hi_sel_nand213: hi_l13 <= not (hi_did1no3 and highpri_v(3)); +hi_sel_nand210: hi_l10 <= not (hi_did1no0 and highpri_v(0)); +hi_sel_nor20: hi_sel(0) <= not (highpri_v_b(0) or hi_later(0)); +hi_sel_nand30: hi_later(0) <= not (hi_l01 and hi_l02 and hi_l03); +hi_sel_nand201: hi_l01 <= not (hi_did0no1 and highpri_v(1)); +hi_sel_nand202: hi_l02 <= not (hi_did0no2 and highpri_v(2)); +hi_sel_nand203: hi_l03 <= not (hi_did0no3 and highpri_v(3)); +medpri0v_inv: medpri_v(0) <= not medpri_v_b0(0); +medpri1v_inv: medpri_v(1) <= not medpri_v_b0(1); +medpri2v_inv: medpri_v(2) <= not medpri_v_b0(2); +medpri3v_inv: medpri_v(3) <= not medpri_v_b0(3); +medpri0vb_inv: medpri_v_b(0) <= not medpri_v(0); +medpri1vb_inv: medpri_v_b(1) <= not medpri_v(1); +medpri2vb_inv: medpri_v_b(2) <= not medpri_v(2); +medpri3vb_inv: medpri_v_b(3) <= not medpri_v(3); +md_sel_nor23: md_sel(3) <= not (medpri_v_b(3) or md_later(3)); +md_sel_nand33: md_later(3) <= not (md_l30 and md_l31 and md_l32); +md_sel_nand230: md_l30 <= not (md_did3no0 and medpri_v(0)); +md_sel_nand231: md_l31 <= not (md_did3no1 and medpri_v(1)); +md_sel_nand232: md_l32 <= not (md_did3no2 and medpri_v(2)); +md_sel_nor22: md_sel(2) <= not (medpri_v_b(2) or md_later(2)); +md_sel_nand32: md_later(2) <= not (md_l23 and md_l20 and md_l21); +md_sel_nand223: md_l23 <= not (md_did2no3 and medpri_v(3)); +md_sel_nand220: md_l20 <= not (md_did2no0 and medpri_v(0)); +md_sel_nand221: md_l21 <= not (md_did2no1 and medpri_v(1)); +md_sel_nor21: md_sel(1) <= not (medpri_v_b(1) or md_later(1)); +md_sel_nand31: md_later(1) <= not (md_l12 and md_l13 and md_l10); +md_sel_nand212: md_l12 <= not (md_did1no2 and medpri_v(2)); +md_sel_nand213: md_l13 <= not (md_did1no3 and medpri_v(3)); +md_sel_nand210: md_l10 <= not (md_did1no0 and medpri_v(0)); +md_sel_nor20: md_sel(0) <= not (medpri_v_b(0) or md_later(0)); +md_sel_nand30: md_later(0) <= not (md_l01 and md_l02 and md_l03); +md_sel_nand201: md_l01 <= not (md_did0no1 and medpri_v(1)); +md_sel_nand202: md_l02 <= not (md_did0no2 and medpri_v(2)); +md_sel_nand203: md_l03 <= not (md_did0no3 and medpri_v(3)); +hi_sel_inv0: hi_sel_b(0) <= not hi_sel(0); +hi_sel_inv1: hi_sel_b(1) <= not hi_sel(1); +hi_sel_inv2: hi_sel_b(2) <= not hi_sel(2); +hi_sel_inv3: hi_sel_b(3) <= not hi_sel(3); +hi_reordf_nand230: hi_did3no0_din <= not (hi_sel_b(3) and hi_n230); +hi_reordf_nand231: hi_did3no1_din <= not (hi_sel_b(3) and hi_n231); +hi_reordf_nand232: hi_did3no2_din <= not (hi_sel_b(3) and hi_n232); +hi_reord_nand230: hi_n230 <= not (hi_sel_b(0) and hi_did3no0); +hi_reord_nand231: hi_n231 <= not (hi_sel_b(1) and hi_did3no1); +hi_reord_nand232: hi_n232 <= not (hi_sel_b(2) and hi_did3no2); +hi_reordf_nand220: hi_did2no0_din <= not(hi_sel_b(2) and hi_n220); +hi_reord_nand220: hi_n220 <= not(hi_sel_b(0) and hi_did2no0); +hi_reordf_nand221: hi_did2no1_din <= not(hi_sel_b(2) and hi_n221); +hi_reord_nand221: hi_n221 <= not(hi_sel_b(1) and hi_did2no1); +hi_reord_inv23: hi_did2no3 <= not hi_did3no2; +hi_reordf_nand210: hi_did1no0_din <= not(hi_sel_b(1) and hi_n210); +hi_reord_nand210: hi_n210 <= not(hi_sel_b(0) and hi_did1no0); +hi_reord_inv12: hi_did1no2 <= not hi_did2no1; +hi_reord_inv13: hi_did1no3 <= not hi_did3no1; +hi_reord_inv01: hi_did0no1 <= not hi_did1no0; +hi_reord_inv02: hi_did0no2 <= not hi_did2no0; +hi_reord_inv03: hi_did0no3 <= not hi_did3no0; +md_sel_inv0: md_sel_b(0) <= not md_sel(0); +md_sel_inv1: md_sel_b(1) <= not md_sel(1); +md_sel_inv2: md_sel_b(2) <= not md_sel(2); +md_sel_inv3: md_sel_b(3) <= not md_sel(3); +md_reordf_nand230: md_did3no0_din <= not (md_sel_b(3) and md_n230); +md_reordf_nand231: md_did3no1_din <= not (md_sel_b(3) and md_n231); +md_reordf_nand232: md_did3no2_din <= not (md_sel_b(3) and md_n232); +md_reord_nand230: md_n230 <= not (md_sel_b(0) and md_did3no0); +md_reord_nand231: md_n231 <= not (md_sel_b(1) and md_did3no1); +md_reord_nand232: md_n232 <= not (md_sel_b(2) and md_did3no2); +md_reordf_nand220: md_did2no0_din <= not(md_sel_b(2) and md_n220); +md_reord_nand220: md_n220 <= not(md_sel_b(0) and md_did2no0); +md_reordf_nand221: md_did2no1_din <= not(md_sel_b(2) and md_n221); +md_reord_nand221: md_n221 <= not(md_sel_b(1) and md_did2no1); +md_reord_inv23: md_did2no3 <= not md_did3no2; +md_reordf_nand210: md_did1no0_din <= not(md_sel_b(1) and md_n210); +md_reord_nand210: md_n210 <= not(md_sel_b(0) and md_did1no0); +md_reord_inv12: md_did1no2 <= not md_did2no1; +md_reord_inv13: md_did1no3 <= not md_did3no1; +md_reord_inv01: md_did0no1 <= not md_did1no0; +md_reord_inv02: md_did0no2 <= not md_did2no0; +md_reord_inv03: md_did0no3 <= not md_did3no0; +nohi_nor21: no_hi_v_n01 <= not (highpri_v(0) or highpri_v(1)); +nohi_nor22: no_hi_v_n23 <= not (highpri_v(2) or highpri_v(3)); +nohi_nand2: no_hi_v_b <= not (no_hi_v_n01 and no_hi_v_n23); +nohi_inv: no_hi_v <= not (no_hi_v_b); +isssel0_inv: issselhi_b(0) <= not (hi_sel(0)); +isssel1_inv: issselhi_b(1) <= not (hi_sel(1)); +isssel2_inv: issselhi_b(2) <= not (hi_sel(2)); +isssel3_inv: issselhi_b(3) <= not (hi_sel(3)); +isssel0_bnand2: issselmd_b(0) <= not (md_sel(0) and no_hi_v); +isssel1_bnand2: issselmd_b(1) <= not (md_sel(1) and no_hi_v); +isssel2_bnand2: issselmd_b(2) <= not (md_sel(2) and no_hi_v); +isssel3_bnand2: issselmd_b(3) <= not (md_sel(3) and no_hi_v); +nexttid0_fnand2: next_tid(0) <= not (issselhi_b(0) and issselmd_b(0)); +nexttid1_fnand2: next_tid(1) <= not (issselhi_b(1) and issselmd_b(1)); +nexttid2_fnand2: next_tid(2) <= not (issselhi_b(2) and issselmd_b(2)); +nexttid3_fnand2: next_tid(3) <= not (issselhi_b(3) and issselmd_b(3)); +iu0_ifar_early_proc: process( + ib_ic_iu5_redirect_tid, iu5_ifar_l2, + bp_ic_iu5_redirect_tid, bp_ic_iu5_redirect_ifar, + icd_ics_iu3_parity_flush, icd_ics_iu3_ifar, icd_ics_iu3_2ucode, icd_ics_iu3_2ucode_type, + ierat_iu_iu2_flush_req, icd_ics_iu2_2ucode, icd_ics_iu2_2ucode_type, + icd_ics_iu2_miss_flush_prev, icd_ics_iu2_ifar_eff, icm_ics_iu2_miss_match_prev, + iu1_icm_flush_tid, icd_ics_iu1_ifar, icd_ics_iu1_2ucode, icd_ics_iu1_2ucode_type, + icm_ics_hold_iu0, hold_thread_iu0, iu0_hold_ecc, + next_tid, iu0_2ucode_l2, iu0_2ucode_type_l2, + iu0_ifar0_l2, iu0_ifar1_l2, iu0_ifar2_l2, iu0_ifar3_l2 ) +begin +if (ib_ic_iu5_redirect_tid(0) = '1') then +iu0_ifar0_early <= iu5_ifar_l2; +iu0_2ucode_early(0) <= '0'; +iu0_2ucode_type_early(0) <= '0'; +elsif (bp_ic_iu5_redirect_tid(0) = '1') then +iu0_ifar0_early <= bp_ic_iu5_redirect_ifar; +iu0_2ucode_early(0) <= '0'; +iu0_2ucode_type_early(0) <= '0'; +elsif ((icd_ics_iu3_parity_flush(0) or + (icd_ics_iu2_miss_flush_prev(0) and icm_ics_iu2_miss_match_prev)) = '1') then +iu0_ifar0_early <= icd_ics_iu3_ifar; +iu0_2ucode_early(0) <= icd_ics_iu3_2ucode; +iu0_2ucode_type_early(0) <= icd_ics_iu3_2ucode_type; +elsif (icd_ics_iu2_miss_flush_prev(0) = '1') then +iu0_ifar0_early <= (icd_ics_iu3_ifar(EFF_IFAR'left to 59) + 1) & "00"; +iu0_2ucode_early(0) <= '0'; +iu0_2ucode_type_early(0) <= '0'; +elsif (ierat_iu_iu2_flush_req(0) = '1') then +iu0_ifar0_early <= icd_ics_iu2_ifar_eff; +iu0_2ucode_early(0) <= icd_ics_iu2_2ucode; +iu0_2ucode_type_early(0) <= icd_ics_iu2_2ucode_type; +elsif (iu1_icm_flush_tid(0) = '1') then +iu0_ifar0_early <= icd_ics_iu1_ifar; +iu0_2ucode_early(0) <= icd_ics_iu1_2ucode; +iu0_2ucode_type_early(0) <= icd_ics_iu1_2ucode_type; +elsif ((next_tid(0) and not icm_ics_hold_iu0 and not hold_thread_iu0(0) and not iu0_hold_ecc) = '1') then +iu0_ifar0_early <= (iu0_ifar0_l2(EFF_IFAR'left to 59) + 1) & "00"; +iu0_2ucode_early(0) <= '0'; +iu0_2ucode_type_early(0) <= '0'; +else +iu0_ifar0_early <= iu0_ifar0_l2; +iu0_2ucode_early(0) <= iu0_2ucode_l2(0); +iu0_2ucode_type_early(0) <= iu0_2ucode_type_l2(0); +end if; +if (ib_ic_iu5_redirect_tid(1) = '1') then +iu0_ifar1_early <= iu5_ifar_l2; +iu0_2ucode_early(1) <= '0'; +iu0_2ucode_type_early(1) <= '0'; +elsif (bp_ic_iu5_redirect_tid(1) = '1') then +iu0_ifar1_early <= bp_ic_iu5_redirect_ifar; +iu0_2ucode_early(1) <= '0'; +iu0_2ucode_type_early(1) <= '0'; +elsif ((icd_ics_iu3_parity_flush(1) or + (icd_ics_iu2_miss_flush_prev(1) and icm_ics_iu2_miss_match_prev)) = '1') then +iu0_ifar1_early <= icd_ics_iu3_ifar; +iu0_2ucode_early(1) <= icd_ics_iu3_2ucode; +iu0_2ucode_type_early(1) <= icd_ics_iu3_2ucode_type; +elsif (icd_ics_iu2_miss_flush_prev(1) = '1') then +iu0_ifar1_early <= (icd_ics_iu3_ifar(EFF_IFAR'left to 59) + 1) & "00"; +iu0_2ucode_early(1) <= '0'; +iu0_2ucode_type_early(1) <= '0'; +elsif (ierat_iu_iu2_flush_req(1) = '1') then +iu0_ifar1_early <= icd_ics_iu2_ifar_eff; +iu0_2ucode_early(1) <= icd_ics_iu2_2ucode; +iu0_2ucode_type_early(1) <= icd_ics_iu2_2ucode_type; +elsif (iu1_icm_flush_tid(1) = '1') then +iu0_ifar1_early <= icd_ics_iu1_ifar; +iu0_2ucode_early(1) <= icd_ics_iu1_2ucode; +iu0_2ucode_type_early(1) <= icd_ics_iu1_2ucode_type; +elsif ((next_tid(1) and not icm_ics_hold_iu0 and not hold_thread_iu0(1) and not iu0_hold_ecc) = '1') then +iu0_ifar1_early <= (iu0_ifar1_l2(EFF_IFAR'left to 59) + 1) & "00"; +iu0_2ucode_early(1) <= '0'; +iu0_2ucode_type_early(1) <= '0'; +else +iu0_ifar1_early <= iu0_ifar1_l2; +iu0_2ucode_early(1) <= iu0_2ucode_l2(1); +iu0_2ucode_type_early(1) <= iu0_2ucode_type_l2(1); +end if; +if (ib_ic_iu5_redirect_tid(2) = '1') then +iu0_ifar2_early <= iu5_ifar_l2; +iu0_2ucode_early(2) <= '0'; +iu0_2ucode_type_early(2) <= '0'; +elsif (bp_ic_iu5_redirect_tid(2) = '1') then +iu0_ifar2_early <= bp_ic_iu5_redirect_ifar; +iu0_2ucode_early(2) <= '0'; +iu0_2ucode_type_early(2) <= '0'; +elsif ((icd_ics_iu3_parity_flush(2) or + (icd_ics_iu2_miss_flush_prev(2) and icm_ics_iu2_miss_match_prev)) = '1') then +iu0_ifar2_early <= icd_ics_iu3_ifar; +iu0_2ucode_early(2) <= icd_ics_iu3_2ucode; +iu0_2ucode_type_early(2) <= icd_ics_iu3_2ucode_type; +elsif (icd_ics_iu2_miss_flush_prev(2) = '1') then +iu0_ifar2_early <= (icd_ics_iu3_ifar(EFF_IFAR'left to 59) + 1) & "00"; +iu0_2ucode_early(2) <= '0'; +iu0_2ucode_type_early(2) <= '0'; +elsif (ierat_iu_iu2_flush_req(2) = '1') then +iu0_ifar2_early <= icd_ics_iu2_ifar_eff; +iu0_2ucode_early(2) <= icd_ics_iu2_2ucode; +iu0_2ucode_type_early(2) <= icd_ics_iu2_2ucode_type; +elsif (iu1_icm_flush_tid(2) = '1') then +iu0_ifar2_early <= icd_ics_iu1_ifar; +iu0_2ucode_early(2) <= icd_ics_iu1_2ucode; +iu0_2ucode_type_early(2) <= icd_ics_iu1_2ucode_type; +elsif ((next_tid(2) and not icm_ics_hold_iu0 and not hold_thread_iu0(2) and not iu0_hold_ecc) = '1') then +iu0_ifar2_early <= (iu0_ifar2_l2(EFF_IFAR'left to 59) + 1) & "00"; +iu0_2ucode_early(2) <= '0'; +iu0_2ucode_type_early(2) <= '0'; +else +iu0_ifar2_early <= iu0_ifar2_l2; +iu0_2ucode_early(2) <= iu0_2ucode_l2(2); +iu0_2ucode_type_early(2) <= iu0_2ucode_type_l2(2); +end if; +if (ib_ic_iu5_redirect_tid(3) = '1') then +iu0_ifar3_early <= iu5_ifar_l2; +iu0_2ucode_early(3) <= '0'; +iu0_2ucode_type_early(3) <= '0'; +elsif (bp_ic_iu5_redirect_tid(3) = '1') then +iu0_ifar3_early <= bp_ic_iu5_redirect_ifar; +iu0_2ucode_early(3) <= '0'; +iu0_2ucode_type_early(3) <= '0'; +elsif ((icd_ics_iu3_parity_flush(3) or + (icd_ics_iu2_miss_flush_prev(3) and icm_ics_iu2_miss_match_prev)) = '1') then +iu0_ifar3_early <= icd_ics_iu3_ifar; +iu0_2ucode_early(3) <= icd_ics_iu3_2ucode; +iu0_2ucode_type_early(3) <= icd_ics_iu3_2ucode_type; +elsif (icd_ics_iu2_miss_flush_prev(3) = '1') then +iu0_ifar3_early <= (icd_ics_iu3_ifar(EFF_IFAR'left to 59) + 1) & "00"; +iu0_2ucode_early(3) <= '0'; +iu0_2ucode_type_early(3) <= '0'; +elsif (ierat_iu_iu2_flush_req(3) = '1') then +iu0_ifar3_early <= icd_ics_iu2_ifar_eff; +iu0_2ucode_early(3) <= icd_ics_iu2_2ucode; +iu0_2ucode_type_early(3) <= icd_ics_iu2_2ucode_type; +elsif (iu1_icm_flush_tid(3) = '1') then +iu0_ifar3_early <= icd_ics_iu1_ifar; +iu0_2ucode_early(3) <= icd_ics_iu1_2ucode; +iu0_2ucode_type_early(3) <= icd_ics_iu1_2ucode_type; +elsif ((next_tid(3) and not icm_ics_hold_iu0 and not hold_thread_iu0(3) and not iu0_hold_ecc) = '1') then +iu0_ifar3_early <= (iu0_ifar3_l2(EFF_IFAR'left to 59) + 1) & "00"; +iu0_2ucode_early(3) <= '0'; +iu0_2ucode_type_early(3) <= '0'; +else +iu0_ifar3_early <= iu0_ifar3_l2; +iu0_2ucode_early(3) <= iu0_2ucode_l2(3); +iu0_2ucode_type_early(3) <= iu0_2ucode_type_l2(3); +end if; +end process; +iu0_ifar0_mux: +iu0_ifar0_pre_cm <= xu_iu_iu0_flush_ifar0 when xu_iu_flush(0) = '1' + else iu0_ifar0_early; +iu0_ifar0: for i in EFF_IFAR'left to EFF_IFAR'right generate +begin + R0:if(i < 32) generate begin iu0_ifar0_d(i) <= iu0_ifar0_pre_cm(i) and xu_iu_msr_cm(0); +end generate; +R1:if(i >= 32) generate +begin iu0_ifar0_d(i) <= iu0_ifar0_pre_cm(i); +end generate; +end generate; +iu0_2ucode0_mux: +iu0_2ucode_d(0) <= xu_iu_flush_2ucode(0) when xu_iu_flush(0) = '1' + else iu0_2ucode_early(0); +iu0_2ucode_type0_mux: +iu0_2ucode_type_d(0) <= xu_iu_flush_2ucode_type(0) when xu_iu_flush(0) = '1' + else iu0_2ucode_type_early(0); +iu0_ifar1_mux: +iu0_ifar1_pre_cm <= xu_iu_iu0_flush_ifar1 when xu_iu_flush(1) = '1' + else iu0_ifar1_early; +iu0_ifar1: for i in EFF_IFAR'left to EFF_IFAR'right generate +begin + R0:if(i < 32) generate begin iu0_ifar1_d(i) <= iu0_ifar1_pre_cm(i) and xu_iu_msr_cm(1); +end generate; +R1:if(i >= 32) generate +begin iu0_ifar1_d(i) <= iu0_ifar1_pre_cm(i); +end generate; +end generate; +iu0_2ucode1_mux: +iu0_2ucode_d(1) <= xu_iu_flush_2ucode(1) when xu_iu_flush(1) = '1' + else iu0_2ucode_early(1); +iu0_2ucode_type1_mux: +iu0_2ucode_type_d(1) <= xu_iu_flush_2ucode_type(1) when xu_iu_flush(1) = '1' + else iu0_2ucode_type_early(1); +iu0_ifar2_mux: +iu0_ifar2_pre_cm <= xu_iu_iu0_flush_ifar2 when xu_iu_flush(2) = '1' + else iu0_ifar2_early; +iu0_ifar2: for i in EFF_IFAR'left to EFF_IFAR'right generate +begin + R0:if(i < 32) generate begin iu0_ifar2_d(i) <= iu0_ifar2_pre_cm(i) and xu_iu_msr_cm(2); +end generate; +R1:if(i >= 32) generate +begin iu0_ifar2_d(i) <= iu0_ifar2_pre_cm(i); +end generate; +end generate; +iu0_2ucode2_mux: +iu0_2ucode_d(2) <= xu_iu_flush_2ucode(2) when xu_iu_flush(2) = '1' + else iu0_2ucode_early(2); +iu0_2ucode_type2_mux: +iu0_2ucode_type_d(2) <= xu_iu_flush_2ucode_type(2) when xu_iu_flush(2) = '1' + else iu0_2ucode_type_early(2); +iu0_ifar3_mux: +iu0_ifar3_pre_cm <= xu_iu_iu0_flush_ifar3 when xu_iu_flush(3) = '1' + else iu0_ifar3_early; +iu0_ifar3: for i in EFF_IFAR'left to EFF_IFAR'right generate +begin + R0:if(i < 32) generate begin iu0_ifar3_d(i) <= iu0_ifar3_pre_cm(i) and xu_iu_msr_cm(3); +end generate; +R1:if(i >= 32) generate +begin iu0_ifar3_d(i) <= iu0_ifar3_pre_cm(i); +end generate; +end generate; +iu0_2ucode3_mux: +iu0_2ucode_d(3) <= xu_iu_flush_2ucode(3) when xu_iu_flush(3) = '1' + else iu0_2ucode_early(3); +iu0_2ucode_type3_mux: +iu0_2ucode_type_d(3) <= xu_iu_flush_2ucode_type(3) when xu_iu_flush(3) = '1' + else iu0_2ucode_type_early(3); +ics_icm_iu0_ifar0 <= iu0_ifar0_l2(46 to 52); +ics_icm_iu0_ifar1 <= iu0_ifar1_l2(46 to 52); +ics_icm_iu0_ifar2 <= iu0_ifar2_l2(46 to 52); +ics_icm_iu0_ifar3 <= iu0_ifar3_l2(46 to 52); +iu0_early_valid <= next_high_valid or next_low_valid; +iu0_valid <= iu0_early_valid and not icm_ics_hold_iu0 and not iu0_hold_ecc and not or_reduce((iu0_flush_tid or hold_thread_iu0) and next_tid); +ics_icd_iu0_valid <= iu0_valid; +ics_icd_iu0_tid <= next_tid; +last_sent_proc: process(next_high_valid, next_low_valid, next_tid, icm_ics_hold_iu0, hold_thread_iu0, + iu0_flush_tid, iu0_hold_ecc ) +begin +iu0_high_sent1_d <= "0000"; +iu0_low_sent1_d <= "0000"; +if(next_high_valid = '1' and (icm_ics_hold_iu0 = '0' and iu0_hold_ecc = '0' and (or_reduce(hold_thread_iu0 and next_tid)) = '0')) then +iu0_high_sent1_d <= next_tid and not iu0_flush_tid; +elsif (next_low_valid = '1' and (icm_ics_hold_iu0 = '0' and iu0_hold_ecc = '0' and (or_reduce(hold_thread_iu0 and next_tid)) = '0')) then +iu0_low_sent1_d <= next_tid and not iu0_flush_tid; +end if; +end process; +iu0_high_sent2_d <= iu0_high_sent1_l2 and not iu1_flush_tid and not all_stages_flush_prev_l2; +iu0_low_sent2_d <= iu0_low_sent1_l2 and not iu1_flush_tid and not all_stages_flush_prev_l2; +iu0_high_sent3_d <= iu0_high_sent2_l2 and not iu2_flush_tid and not icd_ics_iu2_miss_flush_prev and not all_stages_flush_prev_l2; +iu0_low_sent3_d <= ((iu0_low_sent2_l2 and not iu2_flush_tid and not icd_ics_iu2_miss_flush_prev) or icm_ics_load_tid) and not all_stages_flush_prev_l2; +iu0_high_sent4_d <= iu0_high_sent3_l2 and not iu3_flush_tid and not icd_ics_iu2_miss_flush_prev and not all_stages_flush_prev_l2; +iu0_low_sent4_d <= iu0_low_sent3_l2 and not iu3_flush_tid and not icd_ics_iu2_miss_flush_prev and not all_stages_flush_prev_l2; +iu0_high_sentall4 <= not bp_ic_iu5_redirect_tid and not ib_ic_iu5_redirect_tid and + (iu0_high_sent1_d or + (((iu0_high_sent1_l2 and not iu1_flush_tid) or + (iu0_high_sent2_l2 and not (iu2_flush_tid or icd_ics_iu2_miss_flush_prev)) or + (iu0_high_sent3_l2 and not (iu3_flush_tid or icd_ics_iu2_miss_flush_prev)) or + (iu0_high_sent4_l2)) and not all_stages_flush_prev_l2)); +iu0_low_sentall4 <= not bp_ic_iu5_redirect_tid and not ib_ic_iu5_redirect_tid and + (iu0_low_sent1_d or + (((iu0_low_sent1_l2 and not iu1_flush_tid) or + (iu0_low_sent2_l2 and not (iu2_flush_tid or icd_ics_iu2_miss_flush_prev)) or + (icm_ics_load_tid and not iu3_flush_tid) or + (iu0_low_sent3_l2 and not (iu3_flush_tid or icd_ics_iu2_miss_flush_prev)) or + (iu0_low_sent4_l2)) and not all_stages_flush_prev_l2)); +R0: if (EFF_IFAR'left < REAL_IFAR'left) generate +begin + back_inv_addr_ext(EFF_IFAR'left TO REAL_IFAR'left-1) <= (others => '0'); +end generate; +back_inv_addr_ext(REAL_IFAR'left TO 57) <= an_ac_back_inv_addr_l2; +R1: if (EFF_IFAR'left < REAL_IFAR'left) generate +begin + xu_icbi_addr_ext(EFF_IFAR'left TO REAL_IFAR'left-1) <= (others => '0'); +end generate; +xu_icbi_addr_ext(REAL_IFAR'left TO 57) <= xu_icbi_buffer0_addr_l2; +iu0_inval <= back_inv_l2 or xu_icbi_buffer_val(0); +ics_icd_iu0_inval <= iu0_inval; +ics_icm_iu0_inval <= iu0_inval; +ics_icm_iu0_inval_addr <= an_ac_back_inv_addr_l2(52 to 57) when back_inv_l2_clone = '1' + else xu_icbi_buffer0_addr_l2(52 to 57); +iu0_ifar0_or_back_inv_addr(EFF_IFAR'left TO 51) <= + back_inv_addr_ext(EFF_IFAR'left to 51) when back_inv_l2 = '1' + else xu_icbi_addr_ext(EFF_IFAR'left to 51) when xu_icbi_buffer_val(0) = '1' + else iu0_ifar0_l2(EFF_IFAR'left to 51); +iu0_ifar0_or_back_inv_addr(52 TO 57) <= + back_inv_addr_ext(52 to 57) when back_inv_l2 = '1' + else xu_icbi_addr_ext(52 to 57) when xu_icbi_buffer_val(0) = '1' + else spr_idir_row_l2(52 to 57) when spr_idir_read_l2 = '1' + else iu0_ifar0_l2(52 to 57); +iu0_ifar0_or_back_inv_addr(58 TO 61) <= iu0_ifar0_l2(58 to 61); +select_iu0_ifar0 <= next_tid(0) or iu0_inval or spr_idir_read_l2; +iu0_ifar <= + gate_and( select_iu0_ifar0, iu0_ifar0_or_back_inv_addr) or + gate_and( next_tid(1), iu0_ifar1_l2) or + gate_and( next_tid(2), iu0_ifar2_l2) or + gate_and( next_tid(3), iu0_ifar3_l2); +ics_icd_iu0_ifar <= iu0_ifar; +iu0_2ucode <= or_reduce(next_tid and iu0_2ucode_l2); +iu0_2ucode_type <= or_reduce(next_tid and iu0_2ucode_type_l2); +ics_icd_iu0_2ucode <= iu0_2ucode; +ics_icd_iu0_2ucode_type <= iu0_2ucode_type; +iu1_bp_val_d <= icm_ics_iu0_preload_val or iu0_valid; +iu1_bp_tid_d <= icm_ics_iu0_preload_tid when icm_ics_iu0_preload_val = '1' + else next_tid; +iu1_bp_ifar_d <= icm_ics_iu0_preload_ifar when icm_ics_iu0_preload_val = '1' + else iu0_ifar(52 to 59); +iu1_bp_act <= spr_ic_clockgate_dis or + icm_ics_iu0_preload_val or (iu0_early_valid and not icm_ics_hold_iu0 and not iu0_hold_ecc); +ic_bp_iu1_val <= iu1_bp_val_l2; +ic_bp_iu1_tid <= iu1_bp_tid_d; +ic_bp_iu1_ifar <= iu1_bp_ifar_l2(52 to 59); +iu_ierat_iu0_val <= iu0_early_valid; +iu_ierat_iu0_thdid <= next_tid; +ierat_ifar: for i in 0 to 51 generate +begin + R0:if(i < EFF_IFAR'left) generate begin iu_ierat_iu0_ifar(i) <= '0'; +end generate; +R1:if(i >= EFF_IFAR'left) generate +begin iu_ierat_iu0_ifar(i) <= iu0_ifar(i); +end generate; +end generate; +ics_icd_dir_rd_act <= (iu0_early_valid and not icm_ics_hold_iu0 and not iu0_hold_ecc) or back_inv_l2 or xu_icbi_buffer_val(0) or + spr_idir_read_l2; +ics_icd_data_rd_act <= iu0_early_valid; +perf_event_t0_d(2) <= (high_mask_l2(0) or low_mask_l2(0)) and icm_ics_hold_iu0; +perf_event_t1_d(2) <= (high_mask_l2(1) or low_mask_l2(1)) and icm_ics_hold_iu0; +perf_event_t2_d(2) <= (high_mask_l2(2) or low_mask_l2(2)) and icm_ics_hold_iu0; +perf_event_t3_d(2) <= (high_mask_l2(3) or low_mask_l2(3)) and icm_ics_hold_iu0; +perf_event_t0_d(3) <= all_stages_flush_tid(0) or iu0_flush_tid(0); +perf_event_t1_d(3) <= all_stages_flush_tid(1) or iu0_flush_tid(1); +perf_event_t2_d(3) <= all_stages_flush_tid(2) or iu0_flush_tid(2); +perf_event_t3_d(3) <= all_stages_flush_tid(3) or iu0_flush_tid(3); +ic_perf_event_t0 <= perf_event_t0_l2; +ic_perf_event_t1 <= perf_event_t1_l2; +ic_perf_event_t2 <= perf_event_t2_l2; +ic_perf_event_t3 <= perf_event_t3_l2; +sel_dbg_data(0 TO 6) <= xu_iu_flush_l2(0) & uc_flush_tid(0) & ib_ic_iu5_redirect_tid(0) & + bp_ic_iu5_redirect_tid(0) & icd_ics_iu3_parity_flush(0) & icd_ics_iu2_miss_flush_prev(0) & ierat_iu_iu2_flush_req(0); +sel_dbg_data(8 TO 14) <= xu_iu_flush_l2(1) & uc_flush_tid(1) & ib_ic_iu5_redirect_tid(1) & + bp_ic_iu5_redirect_tid(1) & icd_ics_iu3_parity_flush(1) & icd_ics_iu2_miss_flush_prev(1) & ierat_iu_iu2_flush_req(1); +sel_dbg_data(16 TO 22) <= xu_iu_flush_l2(2) & uc_flush_tid(2) & ib_ic_iu5_redirect_tid(2) & + bp_ic_iu5_redirect_tid(2) & icd_ics_iu3_parity_flush(2) & icd_ics_iu2_miss_flush_prev(2) & ierat_iu_iu2_flush_req(2); +sel_dbg_data(24 TO 30) <= xu_iu_flush_l2(3) & uc_flush_tid(3) & ib_ic_iu5_redirect_tid(3) & + bp_ic_iu5_redirect_tid(3) & icd_ics_iu3_parity_flush(3) & icd_ics_iu2_miss_flush_prev(3) & ierat_iu_iu2_flush_req(3); +sel_dbg_data(7) <= icm_ics_iu1_ecc_flush; +sel_dbg_data(15) <= icm_ics_iu2_miss_match_prev; +sel_dbg_data(23) <= ierat_iu_iu2_miss; +sel_dbg_data(31) <= icd_ics_iu1_valid; +sel_dbg_data(32 TO 35) <= icd_ics_iu1_tid; +sel_dbg_data(36 TO 39) <= ib_ic_empty; +sel_dbg_data(40 TO 43) <= ib_ic_below_water; +sel_dbg_data(44 TO 49) <= hi_did3no0 & hi_did3no1 & hi_did3no2 & hi_did2no0 & hi_did2no1 & hi_did1no0; +sel_dbg_data(50 TO 55) <= md_did3no0 & md_did3no1 & md_did3no2 & md_did2no0 & md_did2no1 & md_did1no0; +sel_dbg_data(56 TO 59) <= high_mask_l2; +sel_dbg_data(60 TO 63) <= low_mask_l2; +sel_dbg_data(64) <= spr_idir_read_l2; +sel_dbg_data(65) <= xu_icbi_buffer_val(0); +sel_dbg_data(66) <= back_inv_l2; +sel_dbg_data(67) <= icm_ics_hold_iu0; +sel_dbg_data(68 TO 72) <= xu_iu_run_thread_l2(0) & uc_ic_hold_thread(0) & + bp_ic_iu5_hold_tid(0) & icm_ics_hold_thread_dbg(0) & ierat_iu_hold_req(0); +sel_dbg_data(73 TO 77) <= xu_iu_run_thread_l2(1) & uc_ic_hold_thread(1) & + bp_ic_iu5_hold_tid(1) & icm_ics_hold_thread_dbg(1) & ierat_iu_hold_req(1); +sel_dbg_data(78 TO 82) <= xu_iu_run_thread_l2(2) & uc_ic_hold_thread(2) & + bp_ic_iu5_hold_tid(2) & icm_ics_hold_thread_dbg(2) & ierat_iu_hold_req(2); +sel_dbg_data(83 TO 87) <= xu_iu_run_thread_l2(3) & uc_ic_hold_thread(3) & + bp_ic_iu5_hold_tid(3) & icm_ics_hold_thread_dbg(3) & ierat_iu_hold_req(3); +an_ac_back_inv_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(an_ac_back_inv_offset), + scout => sov(an_ac_back_inv_offset), + din => an_ac_back_inv_d, + dout => an_ac_back_inv_l2); +an_ac_back_inv_target_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(an_ac_back_inv_target_offset), + scout => sov(an_ac_back_inv_target_offset), + din => an_ac_back_inv_target_d, + dout => an_ac_back_inv_target_l2); +an_ac_back_inv_addr_latch: tri_rlmreg_p + generic map (width => an_ac_back_inv_addr_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => back_inv, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(an_ac_back_inv_addr_offset to an_ac_back_inv_addr_offset + an_ac_back_inv_addr_l2'length-1), + scout => sov(an_ac_back_inv_addr_offset to an_ac_back_inv_addr_offset + an_ac_back_inv_addr_l2'length-1), + din => an_ac_back_inv_addr_d, + dout => an_ac_back_inv_addr_l2); +back_inv_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(back_inv_offset), + scout => sov(back_inv_offset), + din => back_inv_d, + dout => back_inv_l2); +back_inv_clone_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(back_inv_clone_offset), + scout => sov(back_inv_clone_offset), + din => back_inv_d, + dout => back_inv_l2_clone); +an_ac_icbi_ack_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(an_ac_icbi_ack_offset), + scout => sov(an_ac_icbi_ack_offset), + din => an_ac_icbi_ack_d, + dout => an_ac_icbi_ack_l2); +an_ac_icbi_ack_thread_latch: tri_rlmreg_p + generic map (width => an_ac_icbi_ack_thread_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(an_ac_icbi_ack_thread_offset to an_ac_icbi_ack_thread_offset + an_ac_icbi_ack_thread_l2'length-1), + scout => sov(an_ac_icbi_ack_thread_offset to an_ac_icbi_ack_thread_offset + an_ac_icbi_ack_thread_l2'length-1), + din => an_ac_icbi_ack_thread_d, + dout => an_ac_icbi_ack_thread_l2); +xu_icbi_buffer0_val_tid_latch: tri_rlmreg_p + generic map (width => xu_icbi_buffer0_val_tid_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_icbi_buffer0_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_icbi_buffer0_val_tid_offset to xu_icbi_buffer0_val_tid_offset + xu_icbi_buffer0_val_tid_l2'length-1), + scout => sov(xu_icbi_buffer0_val_tid_offset to xu_icbi_buffer0_val_tid_offset + xu_icbi_buffer0_val_tid_l2'length-1), + din => xu_icbi_buffer0_val_tid_d, + dout => xu_icbi_buffer0_val_tid_l2); +xu_icbi_buffer1_val_tid_latch: tri_rlmreg_p + generic map (width => xu_icbi_buffer1_val_tid_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_icbi_buffer123_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_icbi_buffer1_val_tid_offset to xu_icbi_buffer1_val_tid_offset + xu_icbi_buffer1_val_tid_l2'length-1), + scout => sov(xu_icbi_buffer1_val_tid_offset to xu_icbi_buffer1_val_tid_offset + xu_icbi_buffer1_val_tid_l2'length-1), + din => xu_icbi_buffer1_val_tid_d, + dout => xu_icbi_buffer1_val_tid_l2); +xu_icbi_buffer2_val_tid_latch: tri_rlmreg_p + generic map (width => xu_icbi_buffer2_val_tid_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_icbi_buffer123_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_icbi_buffer2_val_tid_offset to xu_icbi_buffer2_val_tid_offset + xu_icbi_buffer2_val_tid_l2'length-1), + scout => sov(xu_icbi_buffer2_val_tid_offset to xu_icbi_buffer2_val_tid_offset + xu_icbi_buffer2_val_tid_l2'length-1), + din => xu_icbi_buffer2_val_tid_d, + dout => xu_icbi_buffer2_val_tid_l2); +xu_icbi_buffer3_val_tid_latch: tri_rlmreg_p + generic map (width => xu_icbi_buffer3_val_tid_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_icbi_buffer123_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_icbi_buffer3_val_tid_offset to xu_icbi_buffer3_val_tid_offset + xu_icbi_buffer3_val_tid_l2'length-1), + scout => sov(xu_icbi_buffer3_val_tid_offset to xu_icbi_buffer3_val_tid_offset + xu_icbi_buffer3_val_tid_l2'length-1), + din => xu_icbi_buffer3_val_tid_d, + dout => xu_icbi_buffer3_val_tid_l2); +xu_icbi_buffer0_addr_latch: tri_rlmreg_p + generic map (width => xu_icbi_buffer0_addr_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_icbi_buffer0_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_icbi_buffer0_addr_offset to xu_icbi_buffer0_addr_offset + xu_icbi_buffer0_addr_l2'length-1), + scout => sov(xu_icbi_buffer0_addr_offset to xu_icbi_buffer0_addr_offset + xu_icbi_buffer0_addr_l2'length-1), + din => xu_icbi_buffer0_addr_d, + dout => xu_icbi_buffer0_addr_l2); +xu_icbi_buffer1_addr_latch: tri_rlmreg_p + generic map (width => xu_icbi_buffer1_addr_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_icbi_buffer123_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_icbi_buffer1_addr_offset to xu_icbi_buffer1_addr_offset + xu_icbi_buffer1_addr_l2'length-1), + scout => sov(xu_icbi_buffer1_addr_offset to xu_icbi_buffer1_addr_offset + xu_icbi_buffer1_addr_l2'length-1), + din => xu_icbi_buffer1_addr_d, + dout => xu_icbi_buffer1_addr_l2); +xu_icbi_buffer2_addr_latch: tri_rlmreg_p + generic map (width => xu_icbi_buffer2_addr_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_icbi_buffer123_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_icbi_buffer2_addr_offset to xu_icbi_buffer2_addr_offset + xu_icbi_buffer2_addr_l2'length-1), + scout => sov(xu_icbi_buffer2_addr_offset to xu_icbi_buffer2_addr_offset + xu_icbi_buffer2_addr_l2'length-1), + din => xu_icbi_buffer2_addr_d, + dout => xu_icbi_buffer2_addr_l2); +xu_icbi_buffer3_addr_latch: tri_rlmreg_p + generic map (width => xu_icbi_buffer3_addr_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_icbi_buffer123_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_icbi_buffer3_addr_offset to xu_icbi_buffer3_addr_offset + xu_icbi_buffer3_addr_l2'length-1), + scout => sov(xu_icbi_buffer3_addr_offset to xu_icbi_buffer3_addr_offset + xu_icbi_buffer3_addr_l2'length-1), + din => xu_icbi_buffer3_addr_d, + dout => xu_icbi_buffer3_addr_l2); +xu_iu_run_thread_latch: tri_rlmreg_p + generic map (width => xu_iu_run_thread_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_iu_run_thread_offset to xu_iu_run_thread_offset + xu_iu_run_thread_l2'length-1), + scout => sov(xu_iu_run_thread_offset to xu_iu_run_thread_offset + xu_iu_run_thread_l2'length-1), + din => xu_iu_run_thread_d, + dout => xu_iu_run_thread_l2); +all_stages_flush_prev_latch: tri_rlmreg_p + generic map (width => all_stages_flush_prev_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(all_stages_flush_prev_offset to all_stages_flush_prev_offset + all_stages_flush_prev_l2'length-1), + scout => sov(all_stages_flush_prev_offset to all_stages_flush_prev_offset + all_stages_flush_prev_l2'length-1), + din => all_stages_flush_prev_d, + dout => all_stages_flush_prev_l2); +iu0_ifar0a_latch: tri_rlmreg_p + generic map (width => EFF_IFAR'length/2, init => ((2**(EFF_IFAR'length/2 - 1)-1)*2+1), needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu0_ifar0_offset to iu0_ifar0_offset + (EFF_IFAR'length/2)-1), + scout => sov(iu0_ifar0_offset to iu0_ifar0_offset + (EFF_IFAR'length/2)-1), + din => iu0_ifar0_d(EFF_IFAR'left to EFF_IFAR'left+(EFF_IFAR'length/2)-1), + dout => iu0_ifar0_l2(EFF_IFAR'left to EFF_IFAR'left+(EFF_IFAR'length/2)-1)); +iu0_ifar0b_latch: tri_rlmreg_p + generic map (width => (EFF_IFAR'length - (EFF_IFAR'length/2)), init => ((2**(EFF_IFAR'length-(EFF_IFAR'length/2) - 1)-1)*2+1), needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu0_ifar0_offset + (EFF_IFAR'length/2) to iu0_ifar0_offset + iu0_ifar0_l2'length-1), + scout => sov(iu0_ifar0_offset + (EFF_IFAR'length/2) to iu0_ifar0_offset + iu0_ifar0_l2'length-1), + din => iu0_ifar0_d(EFF_IFAR'left+(EFF_IFAR'length/2) to EFF_IFAR'right), + dout => iu0_ifar0_l2(EFF_IFAR'left+(EFF_IFAR'length/2) to EFF_IFAR'right)); +iu0_ifar1a_latch: tri_rlmreg_p + generic map (width => EFF_IFAR'length/2, init => ((2**(EFF_IFAR'length/2 - 1)-1)*2+1), needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu0_ifar1_offset to iu0_ifar1_offset + (EFF_IFAR'length/2)-1), + scout => sov(iu0_ifar1_offset to iu0_ifar1_offset + (EFF_IFAR'length/2)-1), + din => iu0_ifar1_d(EFF_IFAR'left to EFF_IFAR'left+(EFF_IFAR'length/2)-1), + dout => iu0_ifar1_l2(EFF_IFAR'left to EFF_IFAR'left+(EFF_IFAR'length/2)-1)); +iu0_ifar1b_latch: tri_rlmreg_p + generic map (width => (EFF_IFAR'length - (EFF_IFAR'length/2)), init => ((2**(EFF_IFAR'length-(EFF_IFAR'length/2) - 1)-1)*2+1), needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu0_ifar1_offset + (EFF_IFAR'length/2) to iu0_ifar1_offset + iu0_ifar1_l2'length-1), + scout => sov(iu0_ifar1_offset + (EFF_IFAR'length/2) to iu0_ifar1_offset + iu0_ifar1_l2'length-1), + din => iu0_ifar1_d(EFF_IFAR'left+(EFF_IFAR'length/2) to EFF_IFAR'right), + dout => iu0_ifar1_l2(EFF_IFAR'left+(EFF_IFAR'length/2) to EFF_IFAR'right)); +iu0_ifar2a_latch: tri_rlmreg_p + generic map (width => EFF_IFAR'length/2, init => ((2**(EFF_IFAR'length/2 - 1)-1)*2+1), needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu0_ifar2_offset to iu0_ifar2_offset + (EFF_IFAR'length/2)-1), + scout => sov(iu0_ifar2_offset to iu0_ifar2_offset + (EFF_IFAR'length/2)-1), + din => iu0_ifar2_d(EFF_IFAR'left to EFF_IFAR'left+(EFF_IFAR'length/2)-1), + dout => iu0_ifar2_l2(EFF_IFAR'left to EFF_IFAR'left+(EFF_IFAR'length/2)-1)); +iu0_ifar2b_latch: tri_rlmreg_p + generic map (width => (EFF_IFAR'length - (EFF_IFAR'length/2)), init => ((2**(EFF_IFAR'length-(EFF_IFAR'length/2) - 1)-1)*2+1), needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu0_ifar2_offset + (EFF_IFAR'length/2) to iu0_ifar2_offset + iu0_ifar2_l2'length-1), + scout => sov(iu0_ifar2_offset + (EFF_IFAR'length/2) to iu0_ifar2_offset + iu0_ifar2_l2'length-1), + din => iu0_ifar2_d(EFF_IFAR'left+(EFF_IFAR'length/2) to EFF_IFAR'right), + dout => iu0_ifar2_l2(EFF_IFAR'left+(EFF_IFAR'length/2) to EFF_IFAR'right)); +iu0_ifar3a_latch: tri_rlmreg_p + generic map (width => EFF_IFAR'length/2, init => ((2**(EFF_IFAR'length/2 - 1)-1)*2+1), needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu0_ifar3_offset to iu0_ifar3_offset + (EFF_IFAR'length/2)-1), + scout => sov(iu0_ifar3_offset to iu0_ifar3_offset + (EFF_IFAR'length/2)-1), + din => iu0_ifar3_d(EFF_IFAR'left to EFF_IFAR'left+(EFF_IFAR'length/2)-1), + dout => iu0_ifar3_l2(EFF_IFAR'left to EFF_IFAR'left+(EFF_IFAR'length/2)-1)); +iu0_ifar3b_latch: tri_rlmreg_p + generic map (width => (EFF_IFAR'length - (EFF_IFAR'length/2)), init => ((2**(EFF_IFAR'length-(EFF_IFAR'length/2) - 1)-1)*2+1), needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu0_ifar3_offset + (EFF_IFAR'length/2) to iu0_ifar3_offset + iu0_ifar3_l2'length-1), + scout => sov(iu0_ifar3_offset + (EFF_IFAR'length/2) to iu0_ifar3_offset + iu0_ifar3_l2'length-1), + din => iu0_ifar3_d(EFF_IFAR'left+(EFF_IFAR'length/2) to EFF_IFAR'right), + dout => iu0_ifar3_l2(EFF_IFAR'left+(EFF_IFAR'length/2) to EFF_IFAR'right)); +iu0_2ucode_latch: tri_rlmreg_p + generic map (width => iu0_2ucode_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu0_2ucode_offset to iu0_2ucode_offset + iu0_2ucode_l2'length-1), + scout => sov(iu0_2ucode_offset to iu0_2ucode_offset + iu0_2ucode_l2'length-1), + din => iu0_2ucode_d, + dout => iu0_2ucode_l2); +iu0_2ucode_type_latch: tri_rlmreg_p + generic map (width => iu0_2ucode_type_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu0_2ucode_type_offset to iu0_2ucode_type_offset + iu0_2ucode_type_l2'length-1), + scout => sov(iu0_2ucode_type_offset to iu0_2ucode_type_offset + iu0_2ucode_type_l2'length-1), + din => iu0_2ucode_type_d, + dout => iu0_2ucode_type_l2); +iu0_high_sent1_latch: tri_rlmreg_p + generic map (width => iu0_high_sent1_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu0_high_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu0_high_sent1_offset to iu0_high_sent1_offset + iu0_high_sent1_l2'length-1), + scout => sov(iu0_high_sent1_offset to iu0_high_sent1_offset + iu0_high_sent1_l2'length-1), + din => iu0_high_sent1_d, + dout => iu0_high_sent1_l2); +iu0_high_sent2_latch: tri_rlmreg_p + generic map (width => iu0_high_sent2_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu0_high_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu0_high_sent2_offset to iu0_high_sent2_offset + iu0_high_sent2_l2'length-1), + scout => sov(iu0_high_sent2_offset to iu0_high_sent2_offset + iu0_high_sent2_l2'length-1), + din => iu0_high_sent2_d, + dout => iu0_high_sent2_l2); +iu0_high_sent3_latch: tri_rlmreg_p + generic map (width => iu0_high_sent3_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu0_high_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu0_high_sent3_offset to iu0_high_sent3_offset + iu0_high_sent3_l2'length-1), + scout => sov(iu0_high_sent3_offset to iu0_high_sent3_offset + iu0_high_sent3_l2'length-1), + din => iu0_high_sent3_d, + dout => iu0_high_sent3_l2); +iu0_high_sent4_latch: tri_rlmreg_p + generic map (width => iu0_high_sent4_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu0_high_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu0_high_sent4_offset to iu0_high_sent4_offset + iu0_high_sent4_l2'length-1), + scout => sov(iu0_high_sent4_offset to iu0_high_sent4_offset + iu0_high_sent4_l2'length-1), + din => iu0_high_sent4_d, + dout => iu0_high_sent4_l2); +iu0_low_sent1_latch: tri_rlmreg_p + generic map (width => iu0_low_sent1_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu0_low_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu0_low_sent1_offset to iu0_low_sent1_offset + iu0_low_sent1_l2'length-1), + scout => sov(iu0_low_sent1_offset to iu0_low_sent1_offset + iu0_low_sent1_l2'length-1), + din => iu0_low_sent1_d, + dout => iu0_low_sent1_l2); +iu0_low_sent2_latch: tri_rlmreg_p + generic map (width => iu0_low_sent2_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu0_low_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu0_low_sent2_offset to iu0_low_sent2_offset + iu0_low_sent2_l2'length-1), + scout => sov(iu0_low_sent2_offset to iu0_low_sent2_offset + iu0_low_sent2_l2'length-1), + din => iu0_low_sent2_d, + dout => iu0_low_sent2_l2); +iu0_low_sent3_latch: tri_rlmreg_p + generic map (width => iu0_low_sent3_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu0_low_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu0_low_sent3_offset to iu0_low_sent3_offset + iu0_low_sent3_l2'length-1), + scout => sov(iu0_low_sent3_offset to iu0_low_sent3_offset + iu0_low_sent3_l2'length-1), + din => iu0_low_sent3_d, + dout => iu0_low_sent3_l2); +iu0_low_sent4_latch: tri_rlmreg_p + generic map (width => iu0_low_sent4_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu0_low_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu0_low_sent4_offset to iu0_low_sent4_offset + iu0_low_sent4_l2'length-1), + scout => sov(iu0_low_sent4_offset to iu0_low_sent4_offset + iu0_low_sent4_l2'length-1), + din => iu0_low_sent4_d, + dout => iu0_low_sent4_l2); +high_mask_latch: tri_rlmreg_p + generic map (width => high_mask_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(high_mask_offset to high_mask_offset + high_mask_l2'length-1), + scout => sov(high_mask_offset to high_mask_offset + high_mask_l2'length-1), + din => high_mask_d, + dout => high_mask_l2); +low_mask_latch: tri_rlmreg_p + generic map (width => low_mask_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(low_mask_offset to low_mask_offset + low_mask_l2'length-1), + scout => sov(low_mask_offset to low_mask_offset + low_mask_l2'length-1), + din => low_mask_d, + dout => low_mask_l2); +iu1_bp_val_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu1_bp_val_offset), + scout => sov(iu1_bp_val_offset), + din => iu1_bp_val_d, + dout => iu1_bp_val_l2); +iu1_bp_ifar_latch: tri_rlmreg_p + generic map (width => iu1_bp_ifar_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu1_bp_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu1_bp_ifar_offset to iu1_bp_ifar_offset + iu1_bp_ifar_l2'length-1), + scout => sov(iu1_bp_ifar_offset to iu1_bp_ifar_offset + iu1_bp_ifar_l2'length-1), + din => iu1_bp_ifar_d, + dout => iu1_bp_ifar_l2); +iu5_ifar_latch: tri_rlmreg_p + generic map (width => iu5_ifar_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu5_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu5_ifar_offset to iu5_ifar_offset + iu5_ifar_l2'length-1), + scout => sov(iu5_ifar_offset to iu5_ifar_offset + iu5_ifar_l2'length-1), + din => iu5_ifar_d, + dout => iu5_ifar_l2); +perf_event_t0_latch: tri_rlmreg_p + generic map (width => perf_event_t0_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => event_bus_enable, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(perf_event_t0_offset to perf_event_t0_offset + perf_event_t0_l2'length-1), + scout => sov(perf_event_t0_offset to perf_event_t0_offset + perf_event_t0_l2'length-1), + din => perf_event_t0_d, + dout => perf_event_t0_l2); +perf_event_t1_latch: tri_rlmreg_p + generic map (width => perf_event_t1_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => event_bus_enable, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(perf_event_t1_offset to perf_event_t1_offset + perf_event_t1_l2'length-1), + scout => sov(perf_event_t1_offset to perf_event_t1_offset + perf_event_t1_l2'length-1), + din => perf_event_t1_d, + dout => perf_event_t1_l2); +perf_event_t2_latch: tri_rlmreg_p + generic map (width => perf_event_t2_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => event_bus_enable, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(perf_event_t2_offset to perf_event_t2_offset + perf_event_t2_l2'length-1), + scout => sov(perf_event_t2_offset to perf_event_t2_offset + perf_event_t2_l2'length-1), + din => perf_event_t2_d, + dout => perf_event_t2_l2); +perf_event_t3_latch: tri_rlmreg_p + generic map (width => perf_event_t3_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => event_bus_enable, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(perf_event_t3_offset to perf_event_t3_offset + perf_event_t3_l2'length-1), + scout => sov(perf_event_t3_offset to perf_event_t3_offset + perf_event_t3_l2'length-1), + din => perf_event_t3_d, + dout => perf_event_t3_l2); +pri_took_latch: tri_rlmreg_p + generic map (init => 65, expand_type => expand_type, width => 12) + port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(pri_took_offset to pri_took_offset + 12-1), + scout => sov(pri_took_offset to pri_took_offset + 12-1), + din(00) => hi_did3no0_d, + din(01) => hi_did3no1_d, + din(02) => hi_did3no2_d, + din(03) => hi_did2no0_d, + din(04) => hi_did2no1_d, + din(05) => hi_did1no0_d, + din(06) => md_did3no0_d, + din(07) => md_did3no1_d, + din(08) => md_did3no2_d, + din(09) => md_did2no0_d, + din(10) => md_did2no1_d, + din(11) => md_did1no0_d, + dout(00) => hi_did3no0, + dout(01) => hi_did3no1, + dout(02) => hi_did3no2, + dout(03) => hi_did2no0, + dout(04) => hi_did2no1, + dout(05) => hi_did1no0, + dout(06) => md_did3no0, + dout(07) => md_did3no1, + dout(08) => md_did3no2, + dout(09) => md_did2no0, + dout(10) => md_did2no1, + dout(11) => md_did1no0 + ); +hi_did3no0_d <= pri_rand(0) when (spr_ic_pri_rand_always or (spr_ic_pri_rand_flush and or_reduce(xu_iu_flush_l2(0 to 3)))) = '1' else hi_did3no0_din; +hi_did3no1_d <= pri_rand(1) when (spr_ic_pri_rand_always or (spr_ic_pri_rand_flush and or_reduce(xu_iu_flush_l2(0 to 3)))) = '1' else hi_did3no1_din; +hi_did3no2_d <= pri_rand(2) when (spr_ic_pri_rand_always or (spr_ic_pri_rand_flush and or_reduce(xu_iu_flush_l2(0 to 3)))) = '1' else hi_did3no2_din; +hi_did2no0_d <= pri_rand(3) when (spr_ic_pri_rand_always or (spr_ic_pri_rand_flush and or_reduce(xu_iu_flush_l2(0 to 3)))) = '1' else hi_did2no0_din; +hi_did2no1_d <= pri_rand(4) when (spr_ic_pri_rand_always or (spr_ic_pri_rand_flush and or_reduce(xu_iu_flush_l2(0 to 3)))) = '1' else hi_did2no1_din; +hi_did1no0_d <= pri_rand(5) when (spr_ic_pri_rand_always or (spr_ic_pri_rand_flush and or_reduce(xu_iu_flush_l2(0 to 3)))) = '1' else hi_did1no0_din; +md_did3no0_d <= pri_rand(0) when (spr_ic_pri_rand_always or (spr_ic_pri_rand_flush and or_reduce(xu_iu_flush_l2(0 to 3)))) = '1' else md_did3no0_din; +md_did3no1_d <= pri_rand(1) when (spr_ic_pri_rand_always or (spr_ic_pri_rand_flush and or_reduce(xu_iu_flush_l2(0 to 3)))) = '1' else md_did3no1_din; +md_did3no2_d <= pri_rand(2) when (spr_ic_pri_rand_always or (spr_ic_pri_rand_flush and or_reduce(xu_iu_flush_l2(0 to 3)))) = '1' else md_did3no2_din; +md_did2no0_d <= pri_rand(3) when (spr_ic_pri_rand_always or (spr_ic_pri_rand_flush and or_reduce(xu_iu_flush_l2(0 to 3)))) = '1' else md_did2no0_din; +md_did2no1_d <= pri_rand(4) when (spr_ic_pri_rand_always or (spr_ic_pri_rand_flush and or_reduce(xu_iu_flush_l2(0 to 3)))) = '1' else md_did2no1_din; +md_did1no0_d <= pri_rand(5) when (spr_ic_pri_rand_always or (spr_ic_pri_rand_flush and or_reduce(xu_iu_flush_l2(0 to 3)))) = '1' else md_did1no0_din; +pri_rand(0 TO 5) <= "001000" when spr_ic_pri_rand(0 to 4) = "00000" else + "100111" when spr_ic_pri_rand(0 to 4) = "00001" else + "110111" when spr_ic_pri_rand(0 to 4) = "00010" else + "000001" when spr_ic_pri_rand(0 to 4) = "00011" else + "000110" when spr_ic_pri_rand(0 to 4) = "00100" else + "001001" when spr_ic_pri_rand(0 to 4) = "00101" else + "011000" when spr_ic_pri_rand(0 to 4) = "00110" else + "111101" when spr_ic_pri_rand(0 to 4) = "00111" else + "100101" when spr_ic_pri_rand(0 to 4) = "01000" else + "010110" when spr_ic_pri_rand(0 to 4) = "01001" else + "101101" when spr_ic_pri_rand(0 to 4) = "01010" else + "111110" when spr_ic_pri_rand(0 to 4) = "01011" else + "110110" when spr_ic_pri_rand(0 to 4) = "01100" else + "101001" when spr_ic_pri_rand(0 to 4) = "01101" else + "000000" when spr_ic_pri_rand(0 to 4) = "01110" else + "111010" when spr_ic_pri_rand(0 to 4) = "01111" else + "000111" when spr_ic_pri_rand(0 to 4) = "10000" else + "111001" when spr_ic_pri_rand(0 to 4) = "10001" else + "111000" when spr_ic_pri_rand(0 to 4) = "10010" else + "011010" when spr_ic_pri_rand(0 to 4) = "10011" else + "111111" when spr_ic_pri_rand(0 to 4) = "10100" else + "010010" when spr_ic_pri_rand(0 to 4) = "10101" else + "000010" when spr_ic_pri_rand(0 to 4) = "10110" else + "000101" when spr_ic_pri_rand(0 to 4) = "10111" else + "111111" when spr_ic_pri_rand(0 to 4) = "11000" else + "000000" when spr_ic_pri_rand(0 to 4) = "11001" else + "011010" when spr_ic_pri_rand(0 to 4) = "11010" else + "100101" when spr_ic_pri_rand(0 to 4) = "11011" else + "001001" when spr_ic_pri_rand(0 to 4) = "11100" else + "110110" when spr_ic_pri_rand(0 to 4) = "11101" else + "000111" when spr_ic_pri_rand(0 to 4) = "11110" else + "111000" ; +spr_ic_icbi_ack_en_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(spr_ic_icbi_ack_en_offset), + scout => sov(spr_ic_icbi_ack_en_offset), + din => spr_ic_icbi_ack_en, + dout => spr_ic_icbi_ack_en_l2); +spr_idir_read_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(spr_idir_read_offset), + scout => sov(spr_idir_read_offset), + din => spr_idir_read_d, + dout => spr_idir_read_l2); +spr_idir_row_latch: tri_rlmreg_p + generic map (width => spr_idir_row_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(spr_idir_row_offset to spr_idir_row_offset + spr_idir_row_l2'length-1), + scout => sov(spr_idir_row_offset to spr_idir_row_offset + spr_idir_row_l2'length-1), + din => spr_idir_row_d, + dout => spr_idir_row_l2); +xu_iu_flush_latch: tri_rlmreg_p + generic map (width => xu_iu_flush_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_iu_flush_offset to xu_iu_flush_offset + xu_iu_flush_l2'length-1), + scout => sov(xu_iu_flush_offset to xu_iu_flush_offset + xu_iu_flush_l2'length-1), + din => xu_iu_flush, + dout => xu_iu_flush_l2); +spare_latch: tri_rlmreg_p + generic map (width => spare_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(spare_offset to spare_offset + spare_l2'length-1), + scout => sov(spare_offset to spare_offset + spare_l2'length-1), + din => spare_l2, + dout => spare_l2); +siv(0 TO scan_right) <= sov(1 to scan_right) & func_scan_in; +func_scan_out <= sov(0) and an_ac_scan_dis_dc_b; +END IUQ_IC_SELECT; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_ifetch.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_ifetch.vhdl new file mode 100644 index 0000000..5bd8632 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_ifetch.vhdl @@ -0,0 +1,1939 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; +use ieee.std_logic_1164.all; +library support; +use support.power_logic_pkg.all; +library work; +use work.iuq_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity iuq_ifetch is + generic(expand_type : integer := 2; + a2mode : integer := 1; + regmode : integer := 6; + threads : integer := 4; + ucode_mode : integer := 1; + bcfg_epn_0to15 : integer := 0; + bcfg_epn_16to31 : integer := 0; + bcfg_epn_32to47 : integer := (2**16)-1; + bcfg_epn_48to51 : integer := (2**4)-1; + bcfg_rpn_22to31 : integer := (2**10)-1; + bcfg_rpn_32to47 : integer := (2**16)-1; + bcfg_rpn_48to51 : integer := (2**4)-1; + uc_ifar : integer := 21); +port( + vcs : inout power_logic; + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + + tc_ac_ccflush_dc : in std_ulogic; + an_ac_scan_dis_dc_b : in std_ulogic; + an_ac_scan_diag_dc : in std_ulogic; + + pc_iu_gptr_sl_thold_4 : in std_ulogic; + pc_iu_time_sl_thold_4 : in std_ulogic; + pc_iu_repr_sl_thold_4 : in std_ulogic; + pc_iu_abst_sl_thold_4 : in std_ulogic; + pc_iu_abst_slp_sl_thold_4 : in std_ulogic; + pc_iu_bolt_sl_thold_4 : in std_ulogic; + pc_iu_regf_slp_sl_thold_4 : in std_ulogic; + pc_iu_func_sl_thold_4 : in std_ulogic; + pc_iu_func_slp_sl_thold_4 : in std_ulogic; + pc_iu_cfg_sl_thold_4 : in std_ulogic; + pc_iu_cfg_slp_sl_thold_4 : in std_ulogic; + pc_iu_func_nsl_thold_4 : in std_ulogic; + pc_iu_func_slp_nsl_thold_4 : in std_ulogic; + pc_iu_ary_nsl_thold_4 : in std_ulogic; + pc_iu_ary_slp_nsl_thold_4 : in std_ulogic; + pc_iu_sg_4 : in std_ulogic; + pc_iu_fce_4 : in std_ulogic; + + pc_iu_abist_dcomp_g6t_2r : in std_ulogic_vector(0 to 3); + pc_iu_abist_di_0 : in std_ulogic_vector(0 to 3); + pc_iu_abist_di_g6t_2r : in std_ulogic_vector(0 to 3); + pc_iu_abist_ena_dc : in std_ulogic; + pc_iu_abist_g6t_bw : in std_ulogic_vector(0 to 1); + pc_iu_abist_g6t_r_wb : in std_ulogic; + pc_iu_abist_g8t1p_renb_0 : in std_ulogic; + pc_iu_abist_g8t_bw_0 : in std_ulogic; + pc_iu_abist_g8t_bw_1 : in std_ulogic; + pc_iu_abist_g8t_dcomp : in std_ulogic_vector(0 to 3); + pc_iu_abist_g8t_wenb : in std_ulogic; + pc_iu_abist_raddr_0 : in std_ulogic_vector(2 to 9); + pc_iu_abist_raw_dc_b : in std_ulogic; + pc_iu_abist_waddr_0 : in std_ulogic_vector(3 to 9); + pc_iu_abist_wl256_comp_ena : in std_ulogic; + pc_iu_abist_wl64_comp_ena : in std_ulogic; + pc_iu_abist_wl128_comp_ena : in std_ulogic; + an_ac_lbist_ary_wrt_thru_dc: in std_ulogic; + an_ac_lbist_en_dc : in std_ulogic; + an_ac_atpg_en_dc : in std_ulogic; + an_ac_grffence_en_dc : in std_ulogic; + + pc_iu_bo_enable_4 : in std_ulogic; + pc_iu_bo_reset : in std_ulogic; + pc_iu_bo_unload : in std_ulogic; + pc_iu_bo_repair : in std_ulogic; + pc_iu_bo_shdata : in std_ulogic; + pc_iu_bo_select : in std_ulogic_vector(0 to 4); + iu_pc_bo_fail : out std_ulogic_vector(0 to 4); + iu_pc_bo_diagout : out std_ulogic_vector(0 to 4); + + iu_pc_err_icache_parity : out std_ulogic; + iu_pc_err_icachedir_parity : out std_ulogic; + iu_pc_err_icachedir_multihit : out std_ulogic; + + iu_pc_err_ucode_illegal : out std_ulogic_vector(0 to 3); + + pc_iu_inj_icache_parity : in std_ulogic; + pc_iu_inj_icachedir_parity : in std_ulogic; + pc_iu_inj_icachedir_multihit : in std_ulogic; + + pc_iu_trace_bus_enable : in std_ulogic; + pc_iu_debug_mux1_ctrls : in std_ulogic_vector(0 to 15); + pc_iu_debug_mux2_ctrls : in std_ulogic_vector(0 to 15); + debug_data_in : in std_ulogic_vector(0 to 87); + trace_triggers_in : in std_ulogic_vector(0 to 11); + debug_data_out : out std_ulogic_vector(0 to 87); + trace_triggers_out : out std_ulogic_vector(0 to 11); + pc_iu_event_mux_ctrls : in std_ulogic_vector(0 to 47); + pc_iu_event_count_mode : in std_ulogic_vector(0 to 2); + pc_iu_event_bus_enable : in std_ulogic; + iu_pc_event_data : out std_ulogic_vector(0 to 7); + + pc_iu_init_reset : in std_ulogic; + + gptr_scan_in : in std_ulogic; + time_scan_in : in std_ulogic; + repr_scan_in : in std_ulogic; + abst_scan_in : in std_ulogic_vector(0 to 2); + func_scan_in : in std_ulogic_vector(0 to 13); + ccfg_scan_in : in std_ulogic; + bcfg_scan_in : in std_ulogic; + dcfg_scan_in : in std_ulogic; + regf_scan_in : in std_ulogic_vector(0 to 4); + + gptr_scan_out : out std_ulogic; + time_scan_out : out std_ulogic; + repr_scan_out : out std_ulogic; + abst_scan_out : out std_ulogic_vector(0 to 2); + func_scan_out : out std_ulogic_vector(0 to 13); + ccfg_scan_out : out std_ulogic; + bcfg_scan_out : out std_ulogic; + dcfg_scan_out : out std_ulogic; + regf_scan_out : out std_ulogic_vector(0 to 4); + + + iuq_mi_scan_out : out std_ulogic_vector(0 to 1); + iuq_bp_scan_out : out std_ulogic; + + slowspr_val_in : in std_ulogic; + slowspr_rw_in : in std_ulogic; + slowspr_etid_in : in std_ulogic_vector(0 to 1); + slowspr_addr_in : in std_ulogic_vector(0 to 9); + slowspr_data_in : in std_ulogic_vector(64-(2**regmode) to 63); + slowspr_done_in : in std_ulogic; + + slowspr_val_out : out std_ulogic; + slowspr_rw_out : out std_ulogic; + slowspr_etid_out : out std_ulogic_vector(0 to 1); + slowspr_addr_out : out std_ulogic_vector(0 to 9); + slowspr_data_out : out std_ulogic_vector(64-(2**regmode) to 63); + slowspr_done_out : out std_ulogic; + + xu_iu_run_thread : in std_ulogic_vector(0 to 3); + xu_iu_flush : in std_ulogic_vector(0 to 3); + xu_iu_iu0_flush_ifar0 : in EFF_IFAR; + xu_iu_iu0_flush_ifar1 : in EFF_IFAR; + xu_iu_iu0_flush_ifar2 : in EFF_IFAR; + xu_iu_iu0_flush_ifar3 : in EFF_IFAR; + xu_iu_flush_2ucode : in std_ulogic_vector(0 to 3); + xu_iu_flush_2ucode_type : in std_ulogic_vector(0 to 3); + xu_iu_msr_cm : in std_ulogic_vector(0 to threads-1); + xu_iu_ex6_icbi_val : in std_ulogic_vector(0 to threads-1); + xu_iu_ex6_icbi_addr : in std_ulogic_vector(REAL_IFAR'left to 57); + xu_iu_ici : in std_ulogic; + iu_xu_request : out std_ulogic; + iu_xu_thread : out std_ulogic_vector(0 to 3); + iu_xu_ra : out std_ulogic_vector(REAL_IFAR'left to 59); + iu_xu_wimge : out std_ulogic_vector(0 to 4); + iu_xu_userdef : out std_ulogic_vector(0 to 3); + + an_ac_reld_data_vld : in std_ulogic; + an_ac_reld_core_tag : in std_ulogic_vector(0 to 4); + an_ac_reld_qw : in std_ulogic_vector(57 to 59); + an_ac_reld_data : in std_ulogic_vector(0 to 127); + an_ac_reld_ecc_err : in std_ulogic; + an_ac_reld_ecc_err_ue : in std_ulogic; + an_ac_back_inv : in std_ulogic; + an_ac_back_inv_addr : in std_ulogic_vector(REAL_IFAR'left to 63); + an_ac_back_inv_target_iiu_a: in std_ulogic_vector(0 to 1); + an_ac_back_inv_target_iiu_b: in std_ulogic_vector(3 to 4); + an_ac_icbi_ack : in std_ulogic; + an_ac_icbi_ack_thread : in std_ulogic_vector(0 to 1); + + iu_mm_ierat_req : out std_ulogic; + iu_mm_ierat_epn : out std_ulogic_vector(0 to 51); + iu_mm_ierat_thdid : out std_ulogic_vector(0 to 3); + iu_mm_ierat_state : out std_ulogic_vector(0 to 3); + iu_mm_ierat_tid : out std_ulogic_vector(0 to 13); + iu_mm_ierat_flush : out std_ulogic_vector(0 to 3); + mm_iu_ierat_rel_val : in std_ulogic_vector(0 to 4); + mm_iu_ierat_rel_data : in std_ulogic_vector(0 to 131); + mm_iu_ierat_snoop_coming : in std_ulogic; + mm_iu_ierat_snoop_val : in std_ulogic; + mm_iu_ierat_snoop_attr : in std_ulogic_vector(0 to 25); + mm_iu_ierat_snoop_vpn : in std_ulogic_vector(EFF_IFAR'left to 51); + iu_mm_ierat_snoop_ack : out std_ulogic; + mm_iu_ierat_pid0 : in std_ulogic_vector(0 to 13); + mm_iu_ierat_pid1 : in std_ulogic_vector(0 to 13); + mm_iu_ierat_pid2 : in std_ulogic_vector(0 to 13); + mm_iu_ierat_pid3 : in std_ulogic_vector(0 to 13); + mm_iu_ierat_mmucr0_0 : in std_ulogic_vector(0 to 19); + mm_iu_ierat_mmucr0_1 : in std_ulogic_vector(0 to 19); + mm_iu_ierat_mmucr0_2 : in std_ulogic_vector(0 to 19); + mm_iu_ierat_mmucr0_3 : in std_ulogic_vector(0 to 19); + iu_mm_ierat_mmucr0 : out std_ulogic_vector(0 to 17); + iu_mm_ierat_mmucr0_we : out std_ulogic_vector(0 to 3); + mm_iu_ierat_mmucr1 : in std_ulogic_vector(0 to 8); + iu_mm_ierat_mmucr1 : out std_ulogic_vector(0 to 3); + iu_mm_ierat_mmucr1_we : out std_ulogic; + iu_mm_lmq_empty : out std_ulogic; + + xu_iu_ex1_rb : in std_ulogic_vector(64-(2**regmode) to 51); + xu_rf1_flush : in std_ulogic_vector(0 to 3); + xu_ex1_flush : in std_ulogic_vector(0 to 3); + xu_ex2_flush : in std_ulogic_vector(0 to 3); + xu_ex3_flush : in std_ulogic_vector(0 to 3); + xu_ex4_flush : in std_ulogic_vector(0 to 3); + xu_ex5_flush : in std_ulogic_vector(0 to 3); + xu_iu_ex4_rs_data : in std_ulogic_vector(64-(2**regmode) to 63); + xu_iu_hid_mmu_mode : in std_ulogic; + xu_iu_msr_hv : in std_ulogic_vector(0 to threads-1); + xu_iu_msr_is : in std_ulogic_vector(0 to threads-1); + xu_iu_msr_pr : in std_ulogic_vector(0 to threads-1); + xu_iu_spr_ccr2_ifratsc : in std_ulogic_vector(0 to 8); + xu_iu_spr_ccr2_ifrat : in std_ulogic; + xu_iu_xucr4_mmu_mchk : in std_ulogic; + xu_iu_rf1_val : in std_ulogic_vector(0 to 3); + xu_iu_rf1_is_eratre : in std_ulogic; + xu_iu_rf1_is_eratsx : in std_ulogic; + xu_iu_rf1_is_eratwe : in std_ulogic; + xu_iu_rf1_is_eratilx : in std_ulogic; + xu_iu_ex1_is_isync : in std_ulogic; + xu_iu_ex1_is_csync : in std_ulogic; + xu_iu_rf1_ws : in std_ulogic_vector(0 to 1); + xu_iu_rf1_t : in std_ulogic_vector(0 to 2); + xu_iu_ex1_ra_entry : in std_ulogic_vector(8 to 11); + xu_iu_ex1_rs_is : in std_ulogic_vector(0 to 8); + iu_xu_ex4_tlb_data : out std_ulogic_vector(64-(2**regmode) to 63); + iu_xu_ierat_ex3_par_err : out std_ulogic_vector(0 to threads-1); + iu_xu_ierat_ex4_par_err : out std_ulogic_vector(0 to threads-1); + iu_xu_ierat_ex2_flush_req : out std_ulogic_vector(0 to threads-1); + + xu_iu_ex5_ifar : in EFF_IFAR; + xu_iu_ex5_tid : in std_ulogic_vector(0 to 3); + xu_iu_ex5_val : in std_ulogic; + xu_iu_ex5_br_update : in std_ulogic; + xu_iu_ex5_br_hist : in std_ulogic_vector(0 to 1); + xu_iu_ex5_br_taken : in std_ulogic; + xu_iu_ex5_bclr : in std_ulogic; + xu_iu_ex5_getNIA : in std_ulogic; + xu_iu_ex5_lk : in std_ulogic; + xu_iu_ex5_bh : in std_ulogic_vector(0 to 1); + xu_iu_ex5_gshare : in std_ulogic_vector(0 to 3); + + pc_iu_ram_instr : in std_ulogic_vector(0 to 31); + pc_iu_ram_instr_ext : in std_ulogic_vector(0 to 3); + pc_iu_ram_force_cmplt : in std_ulogic; + xu_iu_ram_issue : in std_ulogic_vector(0 to 3); + + xu_iu_ex6_pri : in std_ulogic_vector(0 to 2); + xu_iu_ex6_pri_val : in std_ulogic_vector(0 to 3); + xu_iu_raise_iss_pri : in std_ulogic_vector(0 to 3); + xu_iu_msr_gs : in std_ulogic_vector(0 to 3); + + xu_iu_ucode_restart : in std_ulogic_vector(0 to 3); + xu_iu_spr_xer0 : in std_ulogic_vector(57 to 63); + xu_iu_spr_xer1 : in std_ulogic_vector(57 to 63); + xu_iu_spr_xer2 : in std_ulogic_vector(57 to 63); + xu_iu_spr_xer3 : in std_ulogic_vector(57 to 63); + xu_iu_uc_flush_ifar0 : in std_ulogic_vector(62-uc_ifar to 61); + xu_iu_uc_flush_ifar1 : in std_ulogic_vector(62-uc_ifar to 61); + xu_iu_uc_flush_ifar2 : in std_ulogic_vector(62-uc_ifar to 61); + xu_iu_uc_flush_ifar3 : in std_ulogic_vector(62-uc_ifar to 61); + + rtim_sl_thold_7 : in std_ulogic; + func_sl_thold_7 : in std_ulogic; + func_nsl_thold_7 : in std_ulogic; + ary_nsl_thold_7 : in std_ulogic; + sg_7 : in std_ulogic; + fce_7 : in std_ulogic; + rtim_sl_thold_6 : out std_ulogic; + func_sl_thold_6 : out std_ulogic; + func_nsl_thold_6 : out std_ulogic; + ary_nsl_thold_6 : out std_ulogic; + sg_6 : out std_ulogic; + fce_6 : out std_ulogic; + an_ac_scom_dch : in std_ulogic; + an_ac_scom_cch : in std_ulogic; + an_ac_checkstop : in std_ulogic; + an_ac_debug_stop : in std_ulogic; + an_ac_pm_thread_stop : in std_ulogic_vector(0 to 3); + an_ac_reset_1_complete : in std_ulogic; + an_ac_reset_2_complete : in std_ulogic; + an_ac_reset_3_complete : in std_ulogic; + an_ac_reset_wd_complete : in std_ulogic; + an_ac_abist_start_test : in std_ulogic; + ac_rp_trace_to_perfcntr : in std_ulogic_vector(0 to 7); + rp_pc_scom_dch_q : out std_ulogic; + rp_pc_scom_cch_q : out std_ulogic; + rp_pc_checkstop_q : out std_ulogic; + rp_pc_debug_stop_q : out std_ulogic; + rp_pc_pm_thread_stop_q : out std_ulogic_vector(0 to 3); + rp_pc_reset_1_complete_q : out std_ulogic; + rp_pc_reset_2_complete_q : out std_ulogic; + rp_pc_reset_3_complete_q : out std_ulogic; + rp_pc_reset_wd_complete_q : out std_ulogic; + rp_pc_abist_start_test_q : out std_ulogic; + rp_pc_trace_to_perfcntr_q : out std_ulogic_vector(0 to 7); + pc_rp_scom_dch : in std_ulogic; + pc_rp_scom_cch : in std_ulogic; + pc_rp_special_attn : in std_ulogic_vector(0 to 3); + pc_rp_checkstop : in std_ulogic_vector(0 to 2); + pc_rp_local_checkstop : in std_ulogic_vector(0 to 2); + pc_rp_recov_err : in std_ulogic_vector(0 to 2); + pc_rp_trace_error : in std_ulogic; + pc_rp_event_bus_enable : in std_ulogic; + pc_rp_event_bus : in std_ulogic_vector(0 to 7); + pc_rp_fu_bypass_events : in std_ulogic_vector(0 to 7); + pc_rp_iu_bypass_events : in std_ulogic_vector(0 to 7); + pc_rp_mm_bypass_events : in std_ulogic_vector(0 to 7); + pc_rp_lsu_bypass_events : in std_ulogic_vector(0 to 7); + pc_rp_pm_thread_running : in std_ulogic_vector(0 to 3); + pc_rp_power_managed : in std_ulogic; + pc_rp_rvwinkle_mode : in std_ulogic; + ac_an_scom_dch_q : out std_ulogic; + ac_an_scom_cch_q : out std_ulogic; + ac_an_special_attn_q : out std_ulogic_vector(0 to 3); + ac_an_checkstop_q : out std_ulogic_vector(0 to 2); + ac_an_local_checkstop_q : out std_ulogic_vector(0 to 2); + ac_an_recov_err_q : out std_ulogic_vector(0 to 2); + ac_an_trace_error_q : out std_ulogic; + rp_mm_event_bus_enable_q : out std_ulogic; + ac_an_event_bus_q : out std_ulogic_vector(0 to 7); + ac_an_fu_bypass_events_q : out std_ulogic_vector(0 to 7); + ac_an_iu_bypass_events_q : out std_ulogic_vector(0 to 7); + ac_an_mm_bypass_events_q : out std_ulogic_vector(0 to 7); + ac_an_lsu_bypass_events_q : out std_ulogic_vector(0 to 7); + ac_an_pm_thread_running_q : out std_ulogic_vector(0 to 3); + ac_an_power_managed_q : out std_ulogic; + ac_an_rvwinkle_mode_q : out std_ulogic; + + pc_func_scan_in : in std_ulogic_vector(0 to 1); + pc_func_scan_in_q : out std_ulogic_vector(0 to 1); + pc_func_scan_out : in std_ulogic; + pc_func_scan_out_q : out std_ulogic; + pc_bcfg_scan_in : in std_ulogic; + pc_bcfg_scan_in_q : out std_ulogic; + pc_dcfg_scan_in : in std_ulogic; + pc_dcfg_scan_in_q : out std_ulogic; + pc_bcfg_scan_out : in std_ulogic; + pc_bcfg_scan_out_q : out std_ulogic; + pc_ccfg_scan_out : in std_ulogic; + pc_ccfg_scan_out_q : out std_ulogic; + pc_dcfg_scan_out : in std_ulogic; + pc_dcfg_scan_out_q : out std_ulogic; + fu_abst_scan_in : in std_ulogic; + fu_abst_scan_in_q : out std_ulogic; + fu_abst_scan_out : in std_ulogic; + fu_abst_scan_out_q : out std_ulogic; + fu_ccfg_scan_out : in std_ulogic; + fu_ccfg_scan_out_q : out std_ulogic; + fu_bcfg_scan_out : in std_ulogic; + fu_bcfg_scan_out_q : out std_ulogic; + fu_dcfg_scan_out : in std_ulogic; + fu_dcfg_scan_out_q : out std_ulogic; + fu_func_scan_in : in std_ulogic_vector(0 to 3); + fu_func_scan_in_q : out std_ulogic_vector(0 to 3); + fu_func_scan_out : in std_ulogic_vector(0 to 3); + fu_func_scan_out_q : out std_ulogic_vector(0 to 3); + bx_abst_scan_in : in std_ulogic; + bx_abst_scan_in_q : out std_ulogic; + bx_abst_scan_out : in std_ulogic; + bx_abst_scan_out_q : out std_ulogic; + bx_func_scan_in : in std_ulogic_vector(0 to 1); + bx_func_scan_in_q : out std_ulogic_vector(0 to 1); + bx_func_scan_out : in std_ulogic_vector(0 to 1); + bx_func_scan_out_q : out std_ulogic_vector(0 to 1); + iu_func_scan_in_q : out std_ulogic_vector(0 to 4); + iu_func_scan_out : in std_ulogic_vector(0 to 7); + spare_func_scan_in : in std_ulogic_vector(0 to 3); + spare_func_scan_out_q : out std_ulogic_vector(0 to 3); + rp_abst_scan_in : in std_ulogic; + rp_func_scan_in : in std_ulogic; + rp_abst_scan_out : out std_ulogic; + rp_func_scan_out : out std_ulogic; + + bg_an_ac_func_scan_sn : in std_ulogic_vector(60 to 69); + bg_an_ac_abst_scan_sn : in std_ulogic_vector(10 to 11); + bg_an_ac_func_scan_sn_q : out std_ulogic_vector(60 to 69); + bg_an_ac_abst_scan_sn_q : out std_ulogic_vector(10 to 11); + + bg_ac_an_func_scan_ns : in std_ulogic_vector(60 to 69); + bg_ac_an_abst_scan_ns : in std_ulogic_vector(10 to 11); + bg_ac_an_func_scan_ns_q : out std_ulogic_vector(60 to 69); + bg_ac_an_abst_scan_ns_q : out std_ulogic_vector(10 to 11); + + bg_pc_l1p_abist_di_0 : in std_ulogic_vector(0 to 3); + bg_pc_l1p_abist_g8t1p_renb_0 : in std_ulogic; + bg_pc_l1p_abist_g8t_bw_0 : in std_ulogic; + bg_pc_l1p_abist_g8t_bw_1 : in std_ulogic; + bg_pc_l1p_abist_g8t_dcomp : in std_ulogic_vector(0 to 3); + bg_pc_l1p_abist_g8t_wenb : in std_ulogic; + bg_pc_l1p_abist_raddr_0 : in std_ulogic_vector(0 to 9); + bg_pc_l1p_abist_waddr_0 : in std_ulogic_vector(0 to 9); + bg_pc_l1p_abist_wl128_comp_ena : in std_ulogic; + bg_pc_l1p_abist_wl32_comp_ena : in std_ulogic; + bg_pc_l1p_abist_di_0_q : out std_ulogic_vector(0 to 3); + bg_pc_l1p_abist_g8t1p_renb_0_q : out std_ulogic; + bg_pc_l1p_abist_g8t_bw_0_q : out std_ulogic; + bg_pc_l1p_abist_g8t_bw_1_q : out std_ulogic; + bg_pc_l1p_abist_g8t_dcomp_q: out std_ulogic_vector(0 to 3); + bg_pc_l1p_abist_g8t_wenb_q : out std_ulogic; + bg_pc_l1p_abist_raddr_0_q : out std_ulogic_vector(0 to 9); + bg_pc_l1p_abist_waddr_0_q : out std_ulogic_vector(0 to 9); + bg_pc_l1p_abist_wl128_comp_ena_q : out std_ulogic; + bg_pc_l1p_abist_wl32_comp_ena_q : out std_ulogic; + + bg_pc_l1p_gptr_sl_thold_3 : in std_ulogic; + bg_pc_l1p_time_sl_thold_3 : in std_ulogic; + bg_pc_l1p_repr_sl_thold_3 : in std_ulogic; + bg_pc_l1p_abst_sl_thold_3 : in std_ulogic; + bg_pc_l1p_func_sl_thold_3 : in std_ulogic_vector(0 to 1); + bg_pc_l1p_func_slp_sl_thold_3 : in std_ulogic; + bg_pc_l1p_bolt_sl_thold_3 : in std_ulogic; + bg_pc_l1p_ary_nsl_thold_3 : in std_ulogic; + bg_pc_l1p_sg_3 : in std_ulogic_vector(0 to 1); + bg_pc_l1p_fce_3 : in std_ulogic; + bg_pc_l1p_bo_enable_3 : in std_ulogic; + bg_pc_l1p_gptr_sl_thold_2 : out std_ulogic; + bg_pc_l1p_time_sl_thold_2 : out std_ulogic; + bg_pc_l1p_repr_sl_thold_2 : out std_ulogic; + bg_pc_l1p_abst_sl_thold_2 : out std_ulogic; + bg_pc_l1p_func_sl_thold_2 : out std_ulogic_vector(0 to 1); + bg_pc_l1p_func_slp_sl_thold_2 : out std_ulogic; + bg_pc_l1p_bolt_sl_thold_2 : out std_ulogic; + bg_pc_l1p_ary_nsl_thold_2 : out std_ulogic; + bg_pc_l1p_sg_2 : out std_ulogic_vector(0 to 1); + bg_pc_l1p_fce_2 : out std_ulogic; + bg_pc_l1p_bo_enable_2 : out std_ulogic; + + + bg_pc_bo_unload_iiu : in std_ulogic; + bg_pc_bo_load_iiu : in std_ulogic; + bg_pc_bo_repair_iiu : in std_ulogic; + bg_pc_bo_reset_iiu : in std_ulogic; + bg_pc_bo_shdata_iiu : in std_ulogic; + bg_pc_bo_select_iiu : in std_ulogic_vector(0 to 10); + bg_pc_l1p_ccflush_dc_iiu : in std_ulogic; + bg_pc_l1p_abist_ena_dc_iiu : in std_ulogic; + bg_pc_l1p_abist_raw_dc_b_iiu : in std_ulogic; + + bg_pc_bo_unload_oiu : out std_ulogic; + bg_pc_bo_load_oiu : out std_ulogic; + bg_pc_bo_repair_oiu : out std_ulogic; + bg_pc_bo_reset_oiu : out std_ulogic; + bg_pc_bo_shdata_oiu : out std_ulogic; + bg_pc_bo_select_oiu : out std_ulogic_vector(0 to 10); + bg_pc_l1p_ccflush_dc_oiu : out std_ulogic; + bg_pc_l1p_abist_ena_dc_oiu : out std_ulogic; + bg_pc_l1p_abist_raw_dc_b_oiu : out std_ulogic; + + ac_an_abist_done_dc_iiu : in std_ulogic; + ac_an_psro_ringsig_iiu : in std_ulogic; + mm_pc_bo_fail_iiu : in std_ulogic_vector(0 to 4); + mm_pc_bo_diagout_iiu : in std_ulogic_vector(0 to 4); + mm_pc_event_data_iiu : in std_ulogic_vector(0 to 7); + + ac_an_abist_done_dc_oiu : out std_ulogic; + ac_an_psro_ringsig_oiu : out std_ulogic; + mm_pc_bo_fail_oiu : out std_ulogic_vector(0 to 4); + mm_pc_bo_diagout_oiu : out std_ulogic_vector(0 to 4); + mm_pc_event_data_oiu : out std_ulogic_vector(0 to 7); + + bg_pc_bo_fail_iiu : in std_ulogic_vector(0 to 10); + bg_pc_bo_diagout_iiu : in std_ulogic_vector(0 to 10); + + bg_pc_bo_fail_oiu : out std_ulogic_vector(0 to 10); + bg_pc_bo_diagout_oiu : out std_ulogic_vector(0 to 10); + + an_ac_abist_mode_dc_iiu : in std_ulogic; + an_ac_ccenable_dc_iiu : in std_ulogic; + an_ac_ccflush_dc_iiu : in std_ulogic; + an_ac_gsd_test_enable_dc_iiu : in std_ulogic; + an_ac_gsd_test_acmode_dc_iiu : in std_ulogic; + an_ac_lbist_ip_dc_iiu : in std_ulogic; + an_ac_lbist_ac_mode_dc_iiu : in std_ulogic; + an_ac_malf_alert_iiu : in std_ulogic; + an_ac_psro_enable_dc_iiu : in std_ulogic_vector(0 to 2); + an_ac_scan_type_dc_iiu : in std_ulogic_vector(0 to 8); + an_ac_scom_sat_id_iiu : in std_ulogic_vector(0 to 3); + + pc_mm_abist_dcomp_g6t_2r_iiu : in std_ulogic_vector(0 to 3); + pc_mm_abist_di_g6t_2r_iiu : in std_ulogic_vector(0 to 3); + pc_mm_abist_di_0_iiu : in std_ulogic_vector(0 to 3); + pc_mm_abist_ena_dc_iiu : in std_ulogic; + pc_mm_abist_g6t_r_wb_iiu : in std_ulogic; + pc_mm_abist_g8t_bw_0_iiu : in std_ulogic; + pc_mm_abist_g8t_bw_1_iiu : in std_ulogic; + pc_mm_abist_g8t_dcomp_iiu : in std_ulogic_vector(0 to 3); + pc_mm_abist_g8t_wenb_iiu : in std_ulogic; + pc_mm_abist_g8t1p_renb_0_iiu : in std_ulogic; + pc_mm_abist_raddr_0_iiu : in std_ulogic_vector(0 to 9); + pc_mm_abist_raw_dc_b_iiu : in std_ulogic; + pc_mm_abist_waddr_0_iiu : in std_ulogic_vector(0 to 9); + pc_mm_abist_wl128_comp_ena_iiu : in std_ulogic; + pc_mm_bo_enable_4_iiu : in std_ulogic; + pc_mm_bo_repair_iiu : in std_ulogic; + pc_mm_bo_reset_iiu : in std_ulogic; + pc_mm_bo_select_iiu : in std_ulogic_vector(0 to 4); + pc_mm_bo_shdata_iiu : in std_ulogic; + pc_mm_bo_unload_iiu : in std_ulogic; + pc_mm_ccflush_dc_iiu : in std_ulogic; + pc_mm_debug_mux1_ctrls_iiu : in std_ulogic_vector(0 to 15); + pc_mm_event_count_mode_iiu : in std_ulogic_vector(0 to 2); + pc_mm_event_mux_ctrls_iiu : in std_ulogic_vector(0 to 39); + pc_mm_trace_bus_enable_iiu : in std_ulogic; + + an_ac_abist_mode_dc_oiu : out std_ulogic; + an_ac_ccenable_dc_oiu : out std_ulogic; + an_ac_ccflush_dc_oiu : out std_ulogic; + an_ac_gsd_test_enable_dc_oiu : out std_ulogic; + an_ac_gsd_test_acmode_dc_oiu : out std_ulogic; + an_ac_lbist_ip_dc_oiu : out std_ulogic; + an_ac_lbist_ac_mode_dc_oiu : out std_ulogic; + an_ac_malf_alert_oiu : out std_ulogic; + an_ac_psro_enable_dc_oiu : out std_ulogic_vector(0 to 2); + an_ac_scan_type_dc_oiu : out std_ulogic_vector(0 to 8); + an_ac_scom_sat_id_oiu : out std_ulogic_vector(0 to 3); + + pc_mm_abist_dcomp_g6t_2r_oiu : out std_ulogic_vector(0 to 3); + pc_mm_abist_di_g6t_2r_oiu : out std_ulogic_vector(0 to 3); + pc_mm_abist_di_0_oiu : out std_ulogic_vector(0 to 3); + pc_mm_abist_ena_dc_oiu : out std_ulogic; + pc_mm_abist_g6t_r_wb_oiu : out std_ulogic; + pc_mm_abist_g8t_bw_0_oiu : out std_ulogic; + pc_mm_abist_g8t_bw_1_oiu : out std_ulogic; + pc_mm_abist_g8t_dcomp_oiu : out std_ulogic_vector(0 to 3); + pc_mm_abist_g8t_wenb_oiu : out std_ulogic; + pc_mm_abist_g8t1p_renb_0_oiu : out std_ulogic; + pc_mm_abist_raddr_0_oiu : out std_ulogic_vector(0 to 9); + pc_mm_abist_raw_dc_b_oiu : out std_ulogic; + pc_mm_abist_waddr_0_oiu : out std_ulogic_vector(0 to 9); + pc_mm_abist_wl128_comp_ena_oiu : out std_ulogic; + pc_mm_abst_sl_thold_3_oiu : out std_ulogic; + pc_mm_abst_slp_sl_thold_3_oiu : out std_ulogic; + pc_mm_ary_nsl_thold_3_oiu : out std_ulogic; + pc_mm_ary_slp_nsl_thold_3_oiu : out std_ulogic; + pc_mm_bo_enable_3_oiu : out std_ulogic; + pc_mm_bo_repair_oiu : out std_ulogic; + pc_mm_bo_reset_oiu : out std_ulogic; + pc_mm_bo_select_oiu : out std_ulogic_vector(0 to 4); + pc_mm_bo_shdata_oiu : out std_ulogic; + pc_mm_bo_unload_oiu : out std_ulogic; + pc_mm_bolt_sl_thold_3_oiu : out std_ulogic; + pc_mm_ccflush_dc_oiu : out std_ulogic; + pc_mm_cfg_sl_thold_3_oiu : out std_ulogic; + pc_mm_cfg_slp_sl_thold_3_oiu : out std_ulogic; + pc_mm_debug_mux1_ctrls_oiu : out std_ulogic_vector(0 to 15); + pc_mm_event_count_mode_oiu : out std_ulogic_vector(0 to 2); + pc_mm_event_mux_ctrls_oiu : out std_ulogic_vector(0 to 39); + pc_mm_fce_3_oiu : out std_ulogic; + pc_mm_func_nsl_thold_3_oiu : out std_ulogic; + pc_mm_func_sl_thold_3_oiu : out std_ulogic_vector(0 to 1); + pc_mm_func_slp_nsl_thold_3_oiu : out std_ulogic; + pc_mm_func_slp_sl_thold_3_oiu : out std_ulogic_vector(0 to 1); + pc_mm_gptr_sl_thold_3_oiu : out std_ulogic; + pc_mm_repr_sl_thold_3_oiu : out std_ulogic; + pc_mm_sg_3_oiu : out std_ulogic_vector(0 to 1); + pc_mm_time_sl_thold_3_oiu : out std_ulogic; + pc_mm_trace_bus_enable_oiu : out std_ulogic; + + an_ac_back_inv_oiu : out std_ulogic; + an_ac_back_inv_addr_oiu : out std_ulogic_vector(REAL_IFAR'left to 63); + an_ac_back_inv_target_bit1_oiu : out std_ulogic; + an_ac_back_inv_target_bit3_oiu : out std_ulogic; + an_ac_back_inv_target_bit4_oiu : out std_ulogic; + an_ac_atpg_en_dc_oiu : out std_ulogic; + an_ac_lbist_ary_wrt_thru_dc_oiu : out std_ulogic; + an_ac_lbist_en_dc_oiu : out std_ulogic; + an_ac_scan_diag_dc_oiu : out std_ulogic; + an_ac_scan_dis_dc_b_oiu : out std_ulogic; + an_ac_grffence_en_dc_oiu : out std_ulogic; + + an_ac_sync_ack : in std_ulogic_vector(0 to 3); + mm_iu_barrier_done : in std_ulogic_vector(0 to 3); + + an_ac_scan_dis_dc_b_oif : out std_ulogic_vector(0 to 3); + an_ac_back_inv_oif : out std_ulogic; + an_ac_back_inv_target_oif : out std_ulogic_vector(1 to 1); + an_ac_sync_ack_oif : out std_ulogic_vector(0 to 3); + mm_iu_barrier_done_oif : out std_ulogic_vector(0 to 3); + + pc_iu_sg_2 : out std_ulogic_vector(0 to 3); + pc_iu_func_sl_thold_2 : out std_ulogic_vector(0 to 3); + + clkoff_b : out std_ulogic_vector(0 to 3); + delay_lclkr : out std_ulogic_vector(5 to 14); + mpw1_b : out std_ulogic_vector(5 to 14); + + fiss_dbg_data : in std_ulogic_vector(0 to 87); + fdep_dbg_data : in std_ulogic_vector(0 to 87); + ib_dbg_data : in std_ulogic_vector(0 to 63); + fu_iss_dbg_data : in std_ulogic_vector(0 to 23); + axu_dbg_data_t0 : in std_ulogic_vector(0 to 37); + axu_dbg_data_t1 : in std_ulogic_vector(0 to 37); + axu_dbg_data_t2 : in std_ulogic_vector(0 to 37); + axu_dbg_data_t3 : in std_ulogic_vector(0 to 37); + + ib_perf_event_t0 : in std_ulogic_vector(0 to 1); + ib_perf_event_t1 : in std_ulogic_vector(0 to 1); + ib_perf_event_t2 : in std_ulogic_vector(0 to 1); + ib_perf_event_t3 : in std_ulogic_vector(0 to 1); + fdep_perf_event_t0 : in std_ulogic_vector(0 to 11); + fdep_perf_event_t1 : in std_ulogic_vector(0 to 11); + fdep_perf_event_t2 : in std_ulogic_vector(0 to 11); + fdep_perf_event_t3 : in std_ulogic_vector(0 to 11); + fiss_perf_event_t0 : in std_ulogic_vector(0 to 7); + fiss_perf_event_t1 : in std_ulogic_vector(0 to 7); + fiss_perf_event_t2 : in std_ulogic_vector(0 to 7); + fiss_perf_event_t3 : in std_ulogic_vector(0 to 7); + + ib_ic_empty : in std_ulogic_vector(0 to 3); + ib_ic_below_water : in std_ulogic_vector(0 to 3); + ib_ic_iu5_redirect_tid : in std_ulogic_vector(0 to 3); + + bp_ib_iu4_t0_val : out std_ulogic_vector(0 to 3); + bp_ib_iu4_t1_val : out std_ulogic_vector(0 to 3); + bp_ib_iu4_t2_val : out std_ulogic_vector(0 to 3); + bp_ib_iu4_t3_val : out std_ulogic_vector(0 to 3); + bp_ib_iu4_ifar_t0 : out EFF_IFAR; + bp_ib_iu3_0_instr_t0 : out std_ulogic_vector(0 to 31); + bp_ib_iu4_0_instr_t0 : out std_ulogic_vector(32 to 43); + bp_ib_iu4_1_instr_t0 : out std_ulogic_vector(0 to 43); + bp_ib_iu4_2_instr_t0 : out std_ulogic_vector(0 to 43); + bp_ib_iu4_3_instr_t0 : out std_ulogic_vector(0 to 43); + bp_ib_iu4_ifar_t1 : out EFF_IFAR; + bp_ib_iu3_0_instr_t1 : out std_ulogic_vector(0 to 31); + bp_ib_iu4_0_instr_t1 : out std_ulogic_vector(32 to 43); + bp_ib_iu4_1_instr_t1 : out std_ulogic_vector(0 to 43); + bp_ib_iu4_2_instr_t1 : out std_ulogic_vector(0 to 43); + bp_ib_iu4_3_instr_t1 : out std_ulogic_vector(0 to 43); + bp_ib_iu4_ifar_t2 : out EFF_IFAR; + bp_ib_iu3_0_instr_t2 : out std_ulogic_vector(0 to 31); + bp_ib_iu4_0_instr_t2 : out std_ulogic_vector(32 to 43); + bp_ib_iu4_1_instr_t2 : out std_ulogic_vector(0 to 43); + bp_ib_iu4_2_instr_t2 : out std_ulogic_vector(0 to 43); + bp_ib_iu4_3_instr_t2 : out std_ulogic_vector(0 to 43); + bp_ib_iu4_ifar_t3 : out EFF_IFAR; + bp_ib_iu3_0_instr_t3 : out std_ulogic_vector(0 to 31); + bp_ib_iu4_0_instr_t3 : out std_ulogic_vector(32 to 43); + bp_ib_iu4_1_instr_t3 : out std_ulogic_vector(0 to 43); + bp_ib_iu4_2_instr_t3 : out std_ulogic_vector(0 to 43); + bp_ib_iu4_3_instr_t3 : out std_ulogic_vector(0 to 43); + + uc_ib_iu4_val : out std_ulogic_vector(0 to 3); + uc_ib_iu4_ifar_t0 : out std_ulogic_vector(62-uc_ifar to 61); + uc_ib_iu4_instr_t0 : out std_ulogic_vector(0 to 36); + uc_ib_iu4_ifar_t1 : out std_ulogic_vector(62-uc_ifar to 61); + uc_ib_iu4_instr_t1 : out std_ulogic_vector(0 to 36); + uc_ib_iu4_ifar_t2 : out std_ulogic_vector(62-uc_ifar to 61); + uc_ib_iu4_instr_t2 : out std_ulogic_vector(0 to 36); + uc_ib_iu4_ifar_t3 : out std_ulogic_vector(62-uc_ifar to 61); + uc_ib_iu4_instr_t3 : out std_ulogic_vector(0 to 36); + + rm_ib_iu4_val : out std_ulogic_vector(0 to 3); + rm_ib_iu4_force_ram_t0 : out std_ulogic; + rm_ib_iu4_instr_t0 : out std_ulogic_vector(0 to 35); + rm_ib_iu4_force_ram_t1 : out std_ulogic; + rm_ib_iu4_instr_t1 : out std_ulogic_vector(0 to 35); + rm_ib_iu4_force_ram_t2 : out std_ulogic; + rm_ib_iu4_instr_t2 : out std_ulogic_vector(0 to 35); + rm_ib_iu4_force_ram_t3 : out std_ulogic; + rm_ib_iu4_instr_t3 : out std_ulogic_vector(0 to 35); + + iu_au_config_iucr_t0 : out std_ulogic_vector(0 to 7); + iu_au_config_iucr_t1 : out std_ulogic_vector(0 to 7); + iu_au_config_iucr_t2 : out std_ulogic_vector(0 to 7); + iu_au_config_iucr_t3 : out std_ulogic_vector(0 to 7); + + spr_issue_high_mask : out std_ulogic_vector(0 to 3); + spr_issue_med_mask : out std_ulogic_vector(0 to 3); + spr_fiss_count0_max : out std_ulogic_vector(0 to 5); + spr_fiss_count1_max : out std_ulogic_vector(0 to 5); + spr_fiss_count2_max : out std_ulogic_vector(0 to 5); + spr_fiss_count3_max : out std_ulogic_vector(0 to 5); + spr_fiss_pri_rand : out std_ulogic_vector(0 to 4); + spr_fiss_pri_rand_always : out std_ulogic; + spr_fiss_pri_rand_flush : out std_ulogic; + spr_dec_mask_t0 : out std_ulogic_vector(0 to 31); + spr_dec_mask_t1 : out std_ulogic_vector(0 to 31); + spr_dec_mask_t2 : out std_ulogic_vector(0 to 31); + spr_dec_mask_t3 : out std_ulogic_vector(0 to 31); + spr_dec_match_t0 : out std_ulogic_vector(0 to 31); + spr_dec_match_t1 : out std_ulogic_vector(0 to 31); + spr_dec_match_t2 : out std_ulogic_vector(0 to 31); + spr_dec_match_t3 : out std_ulogic_vector(0 to 31); + spr_fdep_ll_hold_t0 : out std_ulogic; + spr_fdep_ll_hold_t1 : out std_ulogic; + spr_fdep_ll_hold_t2 : out std_ulogic; + spr_fdep_ll_hold_t3 : out std_ulogic; + + ic_fdep_load_quiesce : out std_ulogic_vector(0 to 3); + ic_fdep_icbi_ack : out std_ulogic_vector(0 to 3); + + fiss_uc_is2_ucode_vld : in std_ulogic; + fiss_uc_is2_tid : in std_ulogic_vector(0 to 3); + fiss_uc_is2_instr : in std_ulogic_vector(0 to 31); + fiss_uc_is2_2ucode : in std_ulogic; + fiss_uc_is2_2ucode_type : in std_ulogic; + + uc_flush_tid : out std_ulogic_vector(0 to 3) + +); +-- synopsys translate_off +-- synopsys translate_on +end iuq_ifetch; +architecture iuq_ifetch of iuq_ifetch is +signal int_clkoff_b : std_ulogic_vector(0 to 2); +signal int_delay_lclkr : std_ulogic_vector(1 to 14); +signal int_mpw1_b : std_ulogic_vector(1 to 14); +signal g8t_clkoff_b : std_ulogic; +signal g8t_d_mode : std_ulogic; +signal g8t_delay_lclkr : std_ulogic_vector(0 to 4); +signal g8t_mpw1_b : std_ulogic_vector(0 to 4); +signal g8t_mpw2_b : std_ulogic; +signal g6t_clkoff_b : std_ulogic; +signal g6t_d_mode : std_ulogic; +signal g6t_delay_lclkr : std_ulogic_vector(0 to 3); +signal g6t_mpw1_b : std_ulogic_vector(0 to 4); +signal g6t_mpw2_b : std_ulogic; +signal cam_clkoff_b : std_ulogic; +signal cam_d_mode : std_ulogic; +signal cam_delay_lclkr : std_ulogic_vector(0 to 4); +signal cam_mpw1_b : std_ulogic_vector(0 to 4); +signal cam_mpw2_b : std_ulogic; +signal int_pc_iu_sg_2 : std_ulogic_vector(0 to 3); +signal pc_iu_fce_2 : std_ulogic; +signal int_pc_iu_func_sl_thold_2 : std_ulogic_vector(0 to 3); +signal pc_iu_func_slp_sl_thold_2: std_ulogic; +signal pc_iu_regf_slp_sl_thold_2: std_ulogic; +signal pc_iu_time_sl_thold_2 : std_ulogic; +signal pc_iu_repr_sl_thold_2 : std_ulogic; +signal pc_iu_abst_sl_thold_2 : std_ulogic; +signal pc_iu_abst_slp_sl_thold_2: std_ulogic; +signal pc_iu_cfg_slp_sl_thold_2 : std_ulogic; +signal pc_iu_ary_nsl_thold_2 : std_ulogic; +signal pc_iu_ary_slp_nsl_thold_2: std_ulogic; +signal pc_iu_func_slp_nsl_thold_2 : std_ulogic; +signal pc_iu_bolt_sl_thold_2 : std_ulogic; +signal ac_an_power_managed_q_int : std_ulogic; +signal pc_iu_bo_enable_3 : std_ulogic; +signal pc_iu_gptr_sl_thold_3 : std_ulogic; +signal pc_iu_time_sl_thold_3 : std_ulogic; +signal pc_iu_repr_sl_thold_3 : std_ulogic; +signal pc_iu_abst_sl_thold_3 : std_ulogic; +signal pc_iu_abst_slp_sl_thold_3 : std_ulogic; +signal pc_iu_bolt_sl_thold_3 : std_ulogic; +signal pc_iu_regf_slp_sl_thold_3 : std_ulogic; +signal pc_iu_func_sl_thold_3 : std_ulogic_vector(0 to 3); +signal pc_iu_func_slp_sl_thold_3 : std_ulogic; +signal pc_iu_cfg_sl_thold_3 : std_ulogic; +signal pc_iu_cfg_slp_sl_thold_3 : std_ulogic; +signal pc_iu_func_slp_nsl_thold_3 : std_ulogic; +signal pc_iu_ary_nsl_thold_3 : std_ulogic; +signal pc_iu_ary_slp_nsl_thold_3 : std_ulogic; +signal pc_iu_sg_3 : std_ulogic_vector(0 to 3); +signal pc_iu_fce_3 : std_ulogic; +signal pc_mm_gptr_sl_thold_3 : std_ulogic; +signal pc_mm_time_sl_thold_3 : std_ulogic; +signal pc_mm_repr_sl_thold_3 : std_ulogic; +signal pc_mm_abst_sl_thold_3 : std_ulogic; +signal pc_mm_abst_slp_sl_thold_3 : std_ulogic; +signal pc_mm_bolt_sl_thold_3 : std_ulogic; +signal pc_mm_func_sl_thold_3 : std_ulogic_vector(0 to 1); +signal pc_mm_func_slp_sl_thold_3 : std_ulogic_vector(0 to 1); +signal pc_mm_cfg_sl_thold_3 : std_ulogic; +signal pc_mm_cfg_slp_sl_thold_3 : std_ulogic; +signal pc_mm_func_nsl_thold_3 : std_ulogic; +signal pc_mm_func_slp_nsl_thold_3 : std_ulogic; +signal pc_mm_ary_nsl_thold_3 : std_ulogic; +signal pc_mm_ary_slp_nsl_thold_3 : std_ulogic; +signal pc_mm_sg_3 : std_ulogic_vector(0 to 1); +signal pc_mm_fce_3 : std_ulogic; +signal ic_bp_iu1_val : std_ulogic; +signal ic_bp_iu1_tid : std_ulogic_vector(0 to 3); +signal ic_bp_iu1_ifar : std_ulogic_vector(52 to 59); +signal ic_bp_iu3_val : std_ulogic_vector(0 to 3); +signal ic_bp_iu3_tid : std_ulogic_vector(0 to 3); +signal ic_bp_iu3_ifar : EFF_IFAR; +signal ic_bp_iu3_2ucode : std_ulogic; +signal ic_bp_iu3_2ucode_type : std_ulogic; +signal ic_bp_iu3_error : std_ulogic_vector(0 to 2); +signal ic_bp_iu3_0_instr : std_ulogic_vector(0 to 35); +signal ic_bp_iu3_1_instr : std_ulogic_vector(0 to 35); +signal ic_bp_iu3_2_instr : std_ulogic_vector(0 to 35); +signal ic_bp_iu3_3_instr : std_ulogic_vector(0 to 35); +signal ic_bp_iu3_flush : std_ulogic; +signal iu3_0_bh_rd_data : std_ulogic_vector(0 to 1); +signal iu3_1_bh_rd_data : std_ulogic_vector(0 to 1); +signal iu3_2_bh_rd_data : std_ulogic_vector(0 to 1); +signal iu3_3_bh_rd_data : std_ulogic_vector(0 to 1); +signal iu1_bh_rd_addr : std_ulogic_vector(0 to 7); +signal iu1_bh_rd_act : std_ulogic; +signal ex6_bh_wr_data : std_ulogic_vector(0 to 1); +signal ex6_bh_wr_addr : std_ulogic_vector(0 to 7); +signal ex6_bh_wr_act : std_ulogic_vector(0 to 3); +signal int_bp_ib_iu4_ifar : EFF_IFAR; +signal bp_ic_iu5_hold_tid : std_ulogic_vector(0 to 3); +signal bp_ic_iu5_redirect_tid : std_ulogic_vector(0 to 3); +signal bp_ic_iu5_redirect_ifar : EFF_IFAR; +signal int_uc_flush_tid : std_ulogic_vector(0 to 3); +signal uc_ic_hold_thread : std_ulogic_vector(0 to 3); +signal spr_ic_icbi_ack_en : std_ulogic; +signal spr_ic_cls : std_ulogic; +signal spr_ic_clockgate_dis : std_ulogic_vector(0 to 1); +signal spr_ic_bp_config : std_ulogic_vector(0 to 3); +signal spr_ic_idir_read : std_ulogic; +signal spr_ic_idir_way : std_ulogic_vector(0 to 1); +signal spr_ic_idir_row : std_ulogic_vector(52 to 57); +signal ic_spr_idir_done : std_ulogic; +signal ic_spr_idir_lru : std_ulogic_vector(0 to 2); +signal ic_spr_idir_parity : std_ulogic_vector(0 to 3); +signal ic_spr_idir_endian : std_ulogic; +signal ic_spr_idir_valid : std_ulogic; +signal ic_spr_idir_tag : std_ulogic_vector(0 to 29); +signal spr_bp_config : std_ulogic_vector(0 to 3); +signal spr_bp_gshare_mask : std_ulogic_vector(0 to 3); +signal spr_ic_pri_rand : std_ulogic_vector(0 to 4); +signal spr_ic_pri_rand_always : std_ulogic; +signal spr_ic_pri_rand_flush : std_ulogic; +signal iuq_mi_scan_in : std_ulogic_vector(0 to 1); +signal iuq_mi_gptr_scan_in : std_ulogic; +signal iuq_mi_gptr_scan_out : std_ulogic; +signal iuq_mi_repr_scan_in : std_ulogic; +signal iuq_mi_repr_scan_out : std_ulogic; +signal iuq_mi_time_scan_in : std_ulogic; +signal iuq_mi_time_scan_out : std_ulogic; +signal iuq_mi_ccfg_scan_in : std_ulogic; +signal iuq_mi_ccfg_scan_out : std_ulogic; +signal iuq_mi_bcfg_scan_in : std_ulogic; +signal iuq_mi_bcfg_scan_out : std_ulogic; +signal iuq_mi_dcfg_scan_in : std_ulogic; +signal iuq_mi_dcfg_scan_out : std_ulogic; +signal iuq_mi_abst_scan_in : std_ulogic; +signal iuq_ic_ccfg_scan_in : std_ulogic; +signal iuq_ic_ccfg_scan_out : std_ulogic; +signal rp_gptr_scan_in : std_ulogic; +signal rp_gptr_scan_out : std_ulogic; +signal iuq_ic_scan_in : std_ulogic_vector(0 to 4); +signal iuq_ic_scan_out : std_ulogic_vector(0 to 4); +signal iuq_ic_repr_scan_in : std_ulogic; +signal iuq_ic_repr_scan_out : std_ulogic; +signal iuq_ic_time_scan_in : std_ulogic; +signal iuq_ic_time_scan_out : std_ulogic; +signal iuq_ic_abst_scan_out : std_ulogic_vector(2 to 2); +signal iuq_bp_scan_in : std_ulogic_vector(0 to 1); +signal int_iuq_bp_scan_out : std_ulogic_vector(0 to 1); +signal iuq_uc_scan_in : std_ulogic; +signal iuq_uc_scan_out : std_ulogic; +signal iu_func_scan_in : std_ulogic_vector(0 to 8); +signal int_iu_func_scan_in_q : std_ulogic_vector(0 to 8); +signal int_iu_func_scan_out : std_ulogic_vector(0 to 9); +signal iu_func_scan_out_q : std_ulogic_vector(0 to 9); +signal bcfg_scan_in_q : std_ulogic; +signal spare_func_scan_in_q : std_ulogic_vector(0 to 3); +signal ic_perf_event_t0 : std_ulogic_vector(0 to 6); +signal ic_perf_event_t1 : std_ulogic_vector(0 to 6); +signal ic_perf_event_t2 : std_ulogic_vector(0 to 6); +signal ic_perf_event_t3 : std_ulogic_vector(0 to 6); +signal ic_perf_event : std_ulogic_vector(0 to 1); +signal bp_dbg_data0 : std_ulogic_vector(0 to 87); +signal bp_dbg_data1 : std_ulogic_vector(0 to 87); +signal uc_dbg_data : std_ulogic_vector(0 to 87); +signal dbg_debug_data_out : std_ulogic_vector(0 to 87); +signal dbg_trace_triggers_out : std_ulogic_vector(0 to 11); +signal bp_ib_iu3_0_instr : std_ulogic_vector(0 to 31); +signal bp_ib_iu4_0_instr : std_ulogic_vector(32 to 43); +signal bp_ib_iu4_1_instr : std_ulogic_vector(0 to 43); +signal bp_ib_iu4_2_instr : std_ulogic_vector(0 to 43); +signal bp_ib_iu4_3_instr : std_ulogic_vector(0 to 43); +signal uc_ib_iu4_ifar : std_ulogic_vector(62-uc_ifar to 61); +signal uc_ib_iu4_instr : std_ulogic_vector(0 to 36); +signal rm_ib_iu4_force_ram : std_ulogic; +signal rm_ib_iu4_instr : std_ulogic_vector(0 to 35); +signal spr_dec_mask : std_ulogic_vector(0 to 31); +signal spr_dec_match : std_ulogic_vector(0 to 31); +signal spr_fdep_ll_hold : std_ulogic; +signal ac_an_psro_ringsig_i1_b : std_ulogic; +signal ac_an_psro_ringsig_i2 : std_ulogic; +signal ac_an_psro_ringsig_i3_b : std_ulogic; +signal ac_an_psro_ringsig_i4 : std_ulogic; +signal ac_an_psro_ringsig_i5_b : std_ulogic; +-- synopsys translate_off +-- synopsys translate_on +begin +pc_iu_sg_2(0 to 2) <= int_pc_iu_sg_2(1 to 3); +pc_iu_sg_2(3) <= int_pc_iu_sg_2(3); +pc_iu_func_sl_thold_2(0 to 2) <= int_pc_iu_func_sl_thold_2(1 to 3); +pc_iu_func_sl_thold_2(3) <= int_pc_iu_func_sl_thold_2(3); +clkoff_b(0) <= int_clkoff_b(1); +clkoff_b(1) <= int_clkoff_b(1); +clkoff_b(2) <= int_clkoff_b(2); +clkoff_b(3) <= int_clkoff_b(2); +delay_lclkr(5 to 14) <= int_delay_lclkr(5 to 14); +mpw1_b(5 to 14) <= int_mpw1_b(5 to 14); +uc_flush_tid <= int_uc_flush_tid; +iuq_bp_scan_out <= int_iuq_bp_scan_out(0); +ac_an_power_managed_q <= ac_an_power_managed_q_int; +bp_ib_iu4_ifar_t0 <= int_bp_ib_iu4_ifar; +bp_ib_iu3_0_instr_t0 <= bp_ib_iu3_0_instr; +bp_ib_iu4_0_instr_t0 <= bp_ib_iu4_0_instr; +bp_ib_iu4_1_instr_t0 <= bp_ib_iu4_1_instr; +bp_ib_iu4_2_instr_t0 <= bp_ib_iu4_2_instr; +bp_ib_iu4_3_instr_t0 <= bp_ib_iu4_3_instr; +uc_ib_iu4_ifar_t0 <= uc_ib_iu4_ifar; +uc_ib_iu4_instr_t0 <= uc_ib_iu4_instr; +rm_ib_iu4_force_ram_t0 <= rm_ib_iu4_force_ram; +rm_ib_iu4_instr_t0 <= rm_ib_iu4_instr; +spr_dec_mask_t0 <= spr_dec_mask; +spr_dec_match_t0 <= spr_dec_match; +spr_fdep_ll_hold_t0 <= spr_fdep_ll_hold; +bp_ib_iu4_ifar_t1 <= int_bp_ib_iu4_ifar; +bp_ib_iu3_0_instr_t1 <= bp_ib_iu3_0_instr; +bp_ib_iu4_0_instr_t1 <= bp_ib_iu4_0_instr; +bp_ib_iu4_1_instr_t1 <= bp_ib_iu4_1_instr; +bp_ib_iu4_2_instr_t1 <= bp_ib_iu4_2_instr; +bp_ib_iu4_3_instr_t1 <= bp_ib_iu4_3_instr; +uc_ib_iu4_ifar_t1 <= uc_ib_iu4_ifar; +uc_ib_iu4_instr_t1 <= uc_ib_iu4_instr; +rm_ib_iu4_force_ram_t1 <= rm_ib_iu4_force_ram; +rm_ib_iu4_instr_t1 <= rm_ib_iu4_instr; +spr_dec_mask_t1 <= spr_dec_mask; +spr_dec_match_t1 <= spr_dec_match; +spr_fdep_ll_hold_t1 <= spr_fdep_ll_hold; +bp_ib_iu4_ifar_t2 <= int_bp_ib_iu4_ifar; +bp_ib_iu3_0_instr_t2 <= bp_ib_iu3_0_instr; +bp_ib_iu4_0_instr_t2 <= bp_ib_iu4_0_instr; +bp_ib_iu4_1_instr_t2 <= bp_ib_iu4_1_instr; +bp_ib_iu4_2_instr_t2 <= bp_ib_iu4_2_instr; +bp_ib_iu4_3_instr_t2 <= bp_ib_iu4_3_instr; +uc_ib_iu4_ifar_t2 <= uc_ib_iu4_ifar; +uc_ib_iu4_instr_t2 <= uc_ib_iu4_instr; +rm_ib_iu4_force_ram_t2 <= rm_ib_iu4_force_ram; +rm_ib_iu4_instr_t2 <= rm_ib_iu4_instr; +spr_dec_mask_t2 <= spr_dec_mask; +spr_dec_match_t2 <= spr_dec_match; +spr_fdep_ll_hold_t2 <= spr_fdep_ll_hold; +bp_ib_iu4_ifar_t3 <= int_bp_ib_iu4_ifar; +bp_ib_iu3_0_instr_t3 <= bp_ib_iu3_0_instr; +bp_ib_iu4_0_instr_t3 <= bp_ib_iu4_0_instr; +bp_ib_iu4_1_instr_t3 <= bp_ib_iu4_1_instr; +bp_ib_iu4_2_instr_t3 <= bp_ib_iu4_2_instr; +bp_ib_iu4_3_instr_t3 <= bp_ib_iu4_3_instr; +uc_ib_iu4_ifar_t3 <= uc_ib_iu4_ifar; +uc_ib_iu4_instr_t3 <= uc_ib_iu4_instr; +rm_ib_iu4_force_ram_t3 <= rm_ib_iu4_force_ram; +rm_ib_iu4_instr_t3 <= rm_ib_iu4_instr; +spr_dec_mask_t3 <= spr_dec_mask; +spr_dec_match_t3 <= spr_dec_match; +spr_fdep_ll_hold_t3 <= spr_fdep_ll_hold; +iuq_misc0 : entity work.iuq_misc +generic map(regmode => regmode, + a2mode => a2mode, + expand_type => expand_type) +port map ( + vdd => vdd, + gnd => gnd, + vcs => vcs, + nclk => nclk, + pc_iu_sg_3 => pc_iu_sg_3, + pc_iu_func_sl_thold_3 => pc_iu_func_sl_thold_3, + pc_iu_func_slp_sl_thold_3 => pc_iu_func_slp_sl_thold_3, + pc_iu_gptr_sl_thold_3 => pc_iu_gptr_sl_thold_3, + pc_iu_time_sl_thold_3 => pc_iu_time_sl_thold_3, + pc_iu_repr_sl_thold_3 => pc_iu_repr_sl_thold_3, + pc_iu_abst_sl_thold_3 => pc_iu_abst_sl_thold_3, + pc_iu_abst_slp_sl_thold_3 => pc_iu_abst_slp_sl_thold_3, + pc_iu_cfg_sl_thold_3 => pc_iu_cfg_sl_thold_3, + pc_iu_cfg_slp_sl_thold_3 => pc_iu_cfg_slp_sl_thold_3, + pc_iu_regf_slp_sl_thold_3 => pc_iu_regf_slp_sl_thold_3, + pc_iu_ary_nsl_thold_3 => pc_iu_ary_nsl_thold_3, + pc_iu_ary_slp_nsl_thold_3 => pc_iu_ary_slp_nsl_thold_3, + pc_iu_func_slp_nsl_thold_3 => pc_iu_func_slp_nsl_thold_3, + pc_iu_bolt_sl_thold_3 => pc_iu_bolt_sl_thold_3, + pc_iu_fce_3 => pc_iu_fce_3, + tc_ac_ccflush_dc => tc_ac_ccflush_dc, + scan_diag_dc => an_ac_scan_diag_dc, + pc_iu_sg_2 => int_pc_iu_sg_2, + pc_iu_func_sl_thold_2 => int_pc_iu_func_sl_thold_2, + pc_iu_func_slp_sl_thold_2 => pc_iu_func_slp_sl_thold_2, + pc_iu_time_sl_thold_2 => pc_iu_time_sl_thold_2, + pc_iu_repr_sl_thold_2 => pc_iu_repr_sl_thold_2, + pc_iu_abst_sl_thold_2 => pc_iu_abst_sl_thold_2, + pc_iu_abst_slp_sl_thold_2 => pc_iu_abst_slp_sl_thold_2, + pc_iu_cfg_slp_sl_thold_2 => pc_iu_cfg_slp_sl_thold_2, + pc_iu_regf_slp_sl_thold_2 => pc_iu_regf_slp_sl_thold_2, + pc_iu_ary_nsl_thold_2 => pc_iu_ary_nsl_thold_2, + pc_iu_ary_slp_nsl_thold_2 => pc_iu_ary_slp_nsl_thold_2, + pc_iu_func_slp_nsl_thold_2 => pc_iu_func_slp_nsl_thold_2, + pc_iu_bolt_sl_thold_2 => pc_iu_bolt_sl_thold_2, + pc_iu_fce_2 => pc_iu_fce_2, + clkoff_b => int_clkoff_b, + +delay_lclkr => int_delay_lclkr, + mpw1_b => int_mpw1_b, + +g8t_clkoff_b => g8t_clkoff_b, + g8t_d_mode => g8t_d_mode, + g8t_delay_lclkr => g8t_delay_lclkr, + g8t_mpw1_b => g8t_mpw1_b, + g8t_mpw2_b => g8t_mpw2_b, + g6t_clkoff_b => g6t_clkoff_b, + +g6t_d_mode => g6t_d_mode, + g6t_delay_lclkr => g6t_delay_lclkr, + g6t_mpw1_b => g6t_mpw1_b, + g6t_mpw2_b => g6t_mpw2_b, + cam_clkoff_b => cam_clkoff_b, + +cam_d_mode => cam_d_mode, + cam_delay_lclkr => cam_delay_lclkr, + cam_mpw1_b => cam_mpw1_b, + cam_mpw2_b => cam_mpw2_b, + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b, + func_scan_in => iuq_mi_scan_in, + gptr_scan_in => iuq_mi_gptr_scan_in, + time_scan_in => iuq_mi_time_scan_in, + abst_scan_in => iuq_mi_abst_scan_in, + repr_scan_in => iuq_mi_repr_scan_in, + ccfg_scan_in => iuq_mi_ccfg_scan_in, + bcfg_scan_in => iuq_mi_bcfg_scan_in, + dcfg_scan_in => iuq_mi_dcfg_scan_in, + func_scan_out => iuq_mi_scan_out, + gptr_scan_out => iuq_mi_gptr_scan_out, + time_scan_out => iuq_mi_time_scan_out, + abst_scan_out => abst_scan_out(2), + repr_scan_out => iuq_mi_repr_scan_out, + ccfg_scan_out => iuq_mi_ccfg_scan_out, + bcfg_scan_out => iuq_mi_bcfg_scan_out, + dcfg_scan_out => iuq_mi_dcfg_scan_out, + pc_iu_abist_di_0 => pc_iu_abist_di_0, + pc_iu_abist_g8t_bw_1 => pc_iu_abist_g8t_bw_1, + pc_iu_abist_g8t_bw_0 => pc_iu_abist_g8t_bw_0, + pc_iu_abist_waddr_0 => pc_iu_abist_waddr_0(3 to 9), + pc_iu_abist_g8t_wenb => pc_iu_abist_g8t_wenb, + pc_iu_abist_raddr_0 => pc_iu_abist_raddr_0(3 to 9), + pc_iu_abist_g8t1p_renb_0 => pc_iu_abist_g8t1p_renb_0, + an_ac_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc, + pc_iu_abist_ena_dc => pc_iu_abist_ena_dc, + pc_iu_abist_wl128_comp_ena => pc_iu_abist_wl128_comp_ena, + pc_iu_abist_raw_dc_b => pc_iu_abist_raw_dc_b, + pc_iu_abist_g8t_dcomp => pc_iu_abist_g8t_dcomp, + pc_iu_bo_enable_3 => pc_iu_bo_enable_3, + pc_iu_bo_reset => pc_iu_bo_reset, + pc_iu_bo_unload => pc_iu_bo_unload, + pc_iu_bo_repair => pc_iu_bo_repair, + pc_iu_bo_shdata => pc_iu_bo_shdata, + pc_iu_bo_select => pc_iu_bo_select(4), + iu_pc_bo_fail => iu_pc_bo_fail(4), + iu_pc_bo_diagout => iu_pc_bo_diagout(4), + r_act => iu1_bh_rd_act, + w_act => ex6_bh_wr_act, + r_addr => iu1_bh_rd_addr, + w_addr => ex6_bh_wr_addr, + data_in => ex6_bh_wr_data, + data_out0 => iu3_0_bh_rd_data, + data_out1 => iu3_1_bh_rd_data, + data_out2 => iu3_2_bh_rd_data, + data_out3 => iu3_3_bh_rd_data, + pc_iu_ram_instr => pc_iu_ram_instr, + pc_iu_ram_instr_ext => pc_iu_ram_instr_ext, + pc_iu_ram_force_cmplt => pc_iu_ram_force_cmplt, + xu_iu_ram_issue => xu_iu_ram_issue, + rm_ib_iu4_val => rm_ib_iu4_val, + rm_ib_iu4_force_ram => rm_ib_iu4_force_ram, + rm_ib_iu4_instr => rm_ib_iu4_instr, + slowspr_val_in => slowspr_val_in, + slowspr_rw_in => slowspr_rw_in, + slowspr_etid_in => slowspr_etid_in, + slowspr_addr_in => slowspr_addr_in, + slowspr_data_in => slowspr_data_in, + slowspr_done_in => slowspr_done_in, + slowspr_val_out => slowspr_val_out, + slowspr_rw_out => slowspr_rw_out, + slowspr_etid_out => slowspr_etid_out, + slowspr_addr_out => slowspr_addr_out, + slowspr_data_out => slowspr_data_out, + slowspr_done_out => slowspr_done_out, + spr_ic_idir_read => spr_ic_idir_read, + spr_ic_idir_way => spr_ic_idir_way, + spr_ic_idir_row => spr_ic_idir_row, + ic_spr_idir_done => ic_spr_idir_done, + ic_spr_idir_lru => ic_spr_idir_lru, + ic_spr_idir_parity => ic_spr_idir_parity, + ic_spr_idir_endian => ic_spr_idir_endian, + ic_spr_idir_valid => ic_spr_idir_valid, + ic_spr_idir_tag => ic_spr_idir_tag, + spr_ic_cls => spr_ic_cls, + spr_ic_clockgate_dis => spr_ic_clockgate_dis, + spr_ic_icbi_ack_en => spr_ic_icbi_ack_en, + spr_ic_bp_config => spr_ic_bp_config, + spr_bp_config => spr_bp_config, + spr_bp_gshare_mask => spr_bp_gshare_mask, + spr_issue_high_mask => spr_issue_high_mask, + spr_issue_med_mask => spr_issue_med_mask, + spr_fiss_count0_max => spr_fiss_count0_max, + spr_fiss_count1_max => spr_fiss_count1_max, + spr_fiss_count2_max => spr_fiss_count2_max, + spr_fiss_count3_max => spr_fiss_count3_max, + spr_ic_pri_rand => spr_ic_pri_rand, + spr_ic_pri_rand_always => spr_ic_pri_rand_always, + spr_ic_pri_rand_flush => spr_ic_pri_rand_flush, + spr_fiss_pri_rand => spr_fiss_pri_rand, + spr_fiss_pri_rand_always => spr_fiss_pri_rand_always, + spr_fiss_pri_rand_flush => spr_fiss_pri_rand_flush, + spr_dec_mask => spr_dec_mask, + spr_dec_match => spr_dec_match, + spr_fdep_ll_hold => spr_fdep_ll_hold, + xu_iu_run_thread => xu_iu_run_thread, + iu_au_config_iucr_t0 => iu_au_config_iucr_t0, + iu_au_config_iucr_t1 => iu_au_config_iucr_t1, + iu_au_config_iucr_t2 => iu_au_config_iucr_t2, + iu_au_config_iucr_t3 => iu_au_config_iucr_t3, + xu_iu_ex6_pri => xu_iu_ex6_pri, + xu_iu_ex6_pri_val => xu_iu_ex6_pri_val, + xu_iu_raise_iss_pri => xu_iu_raise_iss_pri, + xu_iu_msr_gs => xu_iu_msr_gs, + xu_iu_msr_pr => xu_iu_msr_pr, + pc_iu_trace_bus_enable => pc_iu_trace_bus_enable, + pc_iu_debug_mux_ctrls => pc_iu_debug_mux1_ctrls, + debug_data_in => debug_data_in, + trace_triggers_in => trace_triggers_in, + debug_data_out => dbg_debug_data_out, + trace_triggers_out => dbg_trace_triggers_out, + fiss_dbg_data => fiss_dbg_data, + fdep_dbg_data => fdep_dbg_data, + ib_dbg_data => ib_dbg_data, + bp_dbg_data0 => bp_dbg_data0, + bp_dbg_data1 => bp_dbg_data1, + fu_iss_dbg_data => fu_iss_dbg_data, + axu_dbg_data_t0 => axu_dbg_data_t0, + axu_dbg_data_t1 => axu_dbg_data_t1, + axu_dbg_data_t2 => axu_dbg_data_t2, + axu_dbg_data_t3 => axu_dbg_data_t3, + ic_perf_event_t0 => ic_perf_event_t0, + ic_perf_event_t1 => ic_perf_event_t1, + ic_perf_event_t2 => ic_perf_event_t2, + ic_perf_event_t3 => ic_perf_event_t3, + ic_perf_event => ic_perf_event, + ib_perf_event_t0 => ib_perf_event_t0, + ib_perf_event_t1 => ib_perf_event_t1, + ib_perf_event_t2 => ib_perf_event_t2, + ib_perf_event_t3 => ib_perf_event_t3, + fdep_perf_event_t0 => fdep_perf_event_t0, + fdep_perf_event_t1 => fdep_perf_event_t1, + fdep_perf_event_t2 => fdep_perf_event_t2, + fdep_perf_event_t3 => fdep_perf_event_t3, + fiss_perf_event_t0 => fiss_perf_event_t0, + fiss_perf_event_t1 => fiss_perf_event_t1, + fiss_perf_event_t2 => fiss_perf_event_t2, + fiss_perf_event_t3 => fiss_perf_event_t3, + pc_iu_event_mux_ctrls => pc_iu_event_mux_ctrls, + pc_iu_event_count_mode => pc_iu_event_count_mode, + pc_iu_event_bus_enable => pc_iu_event_bus_enable, + iu_pc_event_data => iu_pc_event_data + +); +iuq_ic0 : entity work.iuq_ic +generic map(regmode => regmode, + bcfg_epn_0to15 => bcfg_epn_0to15, + bcfg_epn_16to31 => bcfg_epn_16to31, + bcfg_epn_32to47 => bcfg_epn_32to47, + bcfg_epn_48to51 => bcfg_epn_48to51, + bcfg_rpn_22to31 => bcfg_rpn_22to31, + bcfg_rpn_32to47 => bcfg_rpn_32to47, + bcfg_rpn_48to51 => bcfg_rpn_48to51, + expand_type => expand_type) +port map( + vcs => vcs, + vdd => vdd, + gnd => gnd, + nclk => nclk, + tc_ac_ccflush_dc => tc_ac_ccflush_dc, + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b, + an_ac_scan_diag_dc => an_ac_scan_diag_dc, + pc_iu_func_sl_thold_2 => int_pc_iu_func_sl_thold_2(0), + pc_iu_func_slp_sl_thold_2 => pc_iu_func_slp_sl_thold_2, + pc_iu_time_sl_thold_2 => pc_iu_time_sl_thold_2, + pc_iu_repr_sl_thold_2 => pc_iu_repr_sl_thold_2, + pc_iu_abst_sl_thold_2 => pc_iu_abst_sl_thold_2, + pc_iu_abst_slp_sl_thold_2 => pc_iu_abst_slp_sl_thold_2, + pc_iu_cfg_slp_sl_thold_2 => pc_iu_cfg_slp_sl_thold_2, + pc_iu_regf_slp_sl_thold_2 => pc_iu_regf_slp_sl_thold_2, + pc_iu_ary_nsl_thold_2 => pc_iu_ary_nsl_thold_2, + pc_iu_ary_slp_nsl_thold_2 => pc_iu_ary_slp_nsl_thold_2, + pc_iu_func_slp_nsl_thold_2 => pc_iu_func_slp_nsl_thold_2, + pc_iu_bolt_sl_thold_2 => pc_iu_bolt_sl_thold_2, + pc_iu_sg_2 => int_pc_iu_sg_2(0), + pc_iu_fce_2 => pc_iu_fce_2, + clkoff_b => int_clkoff_b(0), + delay_lclkr(0) => int_delay_lclkr(1), + delay_lclkr(1) => int_delay_lclkr(4), + mpw1_b(0) => int_mpw1_b(1), + mpw1_b(1) => int_mpw1_b(4), + g8t_clkoff_b => g8t_clkoff_b, + g8t_d_mode => g8t_d_mode, + g8t_delay_lclkr => g8t_delay_lclkr, + g8t_mpw1_b => g8t_mpw1_b, + g8t_mpw2_b => g8t_mpw2_b, + g6t_clkoff_b => g6t_clkoff_b, + g6t_d_mode => g6t_d_mode, + g6t_delay_lclkr => g6t_delay_lclkr, + g6t_mpw1_b => g6t_mpw1_b, + g6t_mpw2_b => g6t_mpw2_b, + cam_clkoff_b => cam_clkoff_b, + cam_d_mode => cam_d_mode, + cam_delay_lclkr => cam_delay_lclkr, + cam_mpw1_b => cam_mpw1_b, + cam_mpw2_b => cam_mpw2_b, + func_scan_in => iuq_ic_scan_in, + func_scan_out => iuq_ic_scan_out, + ac_ccfg_scan_in => iuq_ic_ccfg_scan_in, + ac_ccfg_scan_out => iuq_ic_ccfg_scan_out, + time_scan_in => iuq_ic_time_scan_in, + time_scan_out => iuq_ic_time_scan_out, + repr_scan_in => iuq_ic_repr_scan_in, + repr_scan_out => iuq_ic_repr_scan_out, + abst_scan_in => abst_scan_in(0 to 2), + abst_scan_out(0 to 1) => abst_scan_out(0 to 1), + abst_scan_out(2) => iuq_ic_abst_scan_out(2), + regf_scan_in => regf_scan_in, + regf_scan_out => regf_scan_out, + uc_dbg_data => uc_dbg_data, + pc_iu_trace_bus_enable => pc_iu_trace_bus_enable, + pc_iu_debug_mux_ctrls => pc_iu_debug_mux2_ctrls, + debug_data_in => dbg_debug_data_out, + trace_triggers_in => dbg_trace_triggers_out, + debug_data_out => debug_data_out, + trace_triggers_out => trace_triggers_out, + pc_iu_event_bus_enable => pc_iu_event_bus_enable, + ic_perf_event_t0 => ic_perf_event_t0, + ic_perf_event_t1 => ic_perf_event_t1, + ic_perf_event_t2 => ic_perf_event_t2, + ic_perf_event_t3 => ic_perf_event_t3, + ic_perf_event => ic_perf_event, + iu_pc_err_icache_parity => iu_pc_err_icache_parity, + iu_pc_err_icachedir_parity => iu_pc_err_icachedir_parity, + iu_pc_err_icachedir_multihit => iu_pc_err_icachedir_multihit, + pc_iu_inj_icache_parity => pc_iu_inj_icache_parity, + pc_iu_inj_icachedir_parity => pc_iu_inj_icachedir_parity, + pc_iu_inj_icachedir_multihit => pc_iu_inj_icachedir_multihit, + pc_iu_abist_g8t_wenb => pc_iu_abist_g8t_wenb, + pc_iu_abist_g8t1p_renb_0 => pc_iu_abist_g8t1p_renb_0, + pc_iu_abist_di_0 => pc_iu_abist_di_0, + pc_iu_abist_g8t_bw_1 => pc_iu_abist_g8t_bw_1, + pc_iu_abist_g8t_bw_0 => pc_iu_abist_g8t_bw_0, + pc_iu_abist_waddr_0 => pc_iu_abist_waddr_0(4 to 9), + pc_iu_abist_raddr_0 => pc_iu_abist_raddr_0(2 to 9), + pc_iu_abist_ena_dc => pc_iu_abist_ena_dc, + pc_iu_abist_wl64_comp_ena => pc_iu_abist_wl64_comp_ena, + pc_iu_abist_raw_dc_b => pc_iu_abist_raw_dc_b, + pc_iu_abist_g8t_dcomp => pc_iu_abist_g8t_dcomp, + pc_iu_abist_g6t_bw => pc_iu_abist_g6t_bw, + pc_iu_abist_di_g6t_2r => pc_iu_abist_di_g6t_2r, + pc_iu_abist_wl256_comp_ena => pc_iu_abist_wl256_comp_ena, + pc_iu_abist_dcomp_g6t_2r => pc_iu_abist_dcomp_g6t_2r, + pc_iu_abist_g6t_r_wb => pc_iu_abist_g6t_r_wb, + an_ac_lbist_ary_wrt_thru_dc=> an_ac_lbist_ary_wrt_thru_dc, + an_ac_lbist_en_dc => an_ac_lbist_en_dc, + an_ac_atpg_en_dc => an_ac_atpg_en_dc, + an_ac_grffence_en_dc => an_ac_grffence_en_dc, + pc_iu_bo_enable_3 => pc_iu_bo_enable_3, + pc_iu_bo_reset => pc_iu_bo_reset, + pc_iu_bo_unload => pc_iu_bo_unload, + pc_iu_bo_repair => pc_iu_bo_repair, + pc_iu_bo_shdata => pc_iu_bo_shdata, + pc_iu_bo_select => pc_iu_bo_select(0 to 3), + iu_pc_bo_fail => iu_pc_bo_fail(0 to 3), + iu_pc_bo_diagout => iu_pc_bo_diagout(0 to 3), + pc_iu_init_reset => pc_iu_init_reset, + xu_iu_rf1_val => xu_iu_rf1_val, + xu_iu_rf1_is_eratre => xu_iu_rf1_is_eratre, + xu_iu_rf1_is_eratwe => xu_iu_rf1_is_eratwe, + xu_iu_rf1_is_eratsx => xu_iu_rf1_is_eratsx, + xu_iu_rf1_is_eratilx => xu_iu_rf1_is_eratilx, + xu_iu_ex1_is_isync => xu_iu_ex1_is_isync, + xu_iu_ex1_is_csync => xu_iu_ex1_is_csync, + xu_iu_rf1_ws => xu_iu_rf1_ws, + xu_iu_rf1_t => xu_iu_rf1_t, + xu_iu_ex1_rs_is => xu_iu_ex1_rs_is, + xu_iu_ex1_ra_entry => xu_iu_ex1_ra_entry(8 to 11), + xu_iu_ex1_rb => xu_iu_ex1_rb, + xu_rf1_flush => xu_rf1_flush, + xu_ex1_flush => xu_ex1_flush, + xu_ex2_flush => xu_ex2_flush, + xu_ex3_flush => xu_ex3_flush, + xu_ex4_flush => xu_ex4_flush, + xu_ex5_flush => xu_ex5_flush, + xu_iu_ex4_rs_data => xu_iu_ex4_rs_data, + xu_iu_msr_hv => xu_iu_msr_hv, + xu_iu_msr_is => xu_iu_msr_is, + xu_iu_msr_pr => xu_iu_msr_pr, + xu_iu_hid_mmu_mode => xu_iu_hid_mmu_mode, + xu_iu_spr_ccr2_ifratsc => xu_iu_spr_ccr2_ifratsc, + xu_iu_spr_ccr2_ifrat => xu_iu_spr_ccr2_ifrat, + xu_iu_xucr4_mmu_mchk => xu_iu_xucr4_mmu_mchk, + iu_xu_ex4_data => iu_xu_ex4_tlb_data, + iu_xu_ierat_ex3_par_err => iu_xu_ierat_ex3_par_err, + iu_xu_ierat_ex4_par_err => iu_xu_ierat_ex4_par_err, + iu_xu_ierat_ex2_flush_req => iu_xu_ierat_ex2_flush_req, + iu_mm_ierat_req => iu_mm_ierat_req, + iu_mm_ierat_epn => iu_mm_ierat_epn, + iu_mm_ierat_thdid => iu_mm_ierat_thdid, + iu_mm_ierat_state => iu_mm_ierat_state, + iu_mm_ierat_tid => iu_mm_ierat_tid, + iu_mm_ierat_flush => iu_mm_ierat_flush, + mm_iu_ierat_rel_val => mm_iu_ierat_rel_val, + mm_iu_ierat_rel_data => mm_iu_ierat_rel_data, + mm_iu_ierat_pid0 => mm_iu_ierat_pid0, + mm_iu_ierat_pid1 => mm_iu_ierat_pid1, + mm_iu_ierat_pid2 => mm_iu_ierat_pid2, + mm_iu_ierat_pid3 => mm_iu_ierat_pid3, + mm_iu_ierat_mmucr0_0 => mm_iu_ierat_mmucr0_0, + mm_iu_ierat_mmucr0_1 => mm_iu_ierat_mmucr0_1, + mm_iu_ierat_mmucr0_2 => mm_iu_ierat_mmucr0_2, + mm_iu_ierat_mmucr0_3 => mm_iu_ierat_mmucr0_3, + iu_mm_ierat_mmucr0 => iu_mm_ierat_mmucr0, + iu_mm_ierat_mmucr0_we => iu_mm_ierat_mmucr0_we, + mm_iu_ierat_mmucr1 => mm_iu_ierat_mmucr1, + iu_mm_ierat_mmucr1 => iu_mm_ierat_mmucr1, + iu_mm_ierat_mmucr1_we => iu_mm_ierat_mmucr1_we, + mm_iu_ierat_snoop_coming => mm_iu_ierat_snoop_coming, + mm_iu_ierat_snoop_val => mm_iu_ierat_snoop_val, + mm_iu_ierat_snoop_attr => mm_iu_ierat_snoop_attr, + mm_iu_ierat_snoop_vpn => mm_iu_ierat_snoop_vpn, + iu_mm_ierat_snoop_ack => iu_mm_ierat_snoop_ack, + iu_mm_lmq_empty => iu_mm_lmq_empty, + ac_an_power_managed => ac_an_power_managed_q_int, + xu_iu_run_thread => xu_iu_run_thread, + xu_iu_flush => xu_iu_flush, + xu_iu_iu0_flush_ifar0 => xu_iu_iu0_flush_ifar0, + xu_iu_iu0_flush_ifar1 => xu_iu_iu0_flush_ifar1, + xu_iu_iu0_flush_ifar2 => xu_iu_iu0_flush_ifar2, + xu_iu_iu0_flush_ifar3 => xu_iu_iu0_flush_ifar3, + xu_iu_flush_2ucode => xu_iu_flush_2ucode, + xu_iu_flush_2ucode_type => xu_iu_flush_2ucode_type, + xu_iu_msr_cm => xu_iu_msr_cm, + xu_iu_ex6_icbi_val => xu_iu_ex6_icbi_val, + xu_iu_ex6_icbi_addr => xu_iu_ex6_icbi_addr, + xu_iu_ici => xu_iu_ici, + spr_ic_cls => spr_ic_cls, + spr_ic_clockgate_dis => spr_ic_clockgate_dis, + spr_ic_icbi_ack_en => spr_ic_icbi_ack_en, + spr_ic_bp_config => spr_ic_bp_config, + spr_ic_idir_read => spr_ic_idir_read, + spr_ic_idir_way => spr_ic_idir_way, + spr_ic_idir_row => spr_ic_idir_row, + spr_ic_pri_rand => spr_ic_pri_rand, + spr_ic_pri_rand_always => spr_ic_pri_rand_always, + spr_ic_pri_rand_flush => spr_ic_pri_rand_flush, + ic_spr_idir_done => ic_spr_idir_done, + ic_spr_idir_lru => ic_spr_idir_lru, + ic_spr_idir_parity => ic_spr_idir_parity, + ic_spr_idir_endian => ic_spr_idir_endian, + ic_spr_idir_valid => ic_spr_idir_valid, + ic_spr_idir_tag => ic_spr_idir_tag, + iu_xu_request => iu_xu_request, + iu_xu_thread => iu_xu_thread, + iu_xu_ra => iu_xu_ra, + iu_xu_wimge => iu_xu_wimge, + iu_xu_userdef => iu_xu_userdef, + an_ac_reld_data_vld => an_ac_reld_data_vld, + an_ac_reld_core_tag => an_ac_reld_core_tag, + an_ac_reld_qw => an_ac_reld_qw, + an_ac_reld_data => an_ac_reld_data, + an_ac_reld_ecc_err => an_ac_reld_ecc_err, + an_ac_reld_ecc_err_ue => an_ac_reld_ecc_err_ue, + an_ac_back_inv => an_ac_back_inv, + an_ac_back_inv_addr => an_ac_back_inv_addr(REAL_IFAR'left to 57), + an_ac_back_inv_target => an_ac_back_inv_target_iiu_a(0), + an_ac_icbi_ack => an_ac_icbi_ack, + an_ac_icbi_ack_thread => an_ac_icbi_ack_thread, + bp_ib_iu4_ifar => int_bp_ib_iu4_ifar, + bp_ic_iu5_hold_tid => bp_ic_iu5_hold_tid, + bp_ic_iu5_redirect_tid => bp_ic_iu5_redirect_tid, + bp_ic_iu5_redirect_ifar => bp_ic_iu5_redirect_ifar, + ic_bp_iu1_val => ic_bp_iu1_val, + ic_bp_iu1_tid => ic_bp_iu1_tid, + ic_bp_iu1_ifar => ic_bp_iu1_ifar, + ic_bp_iu3_val => ic_bp_iu3_val, + ic_bp_iu3_tid => ic_bp_iu3_tid, + ic_bp_iu3_ifar => ic_bp_iu3_ifar, + ic_bp_iu3_2ucode => ic_bp_iu3_2ucode, + ic_bp_iu3_2ucode_type => ic_bp_iu3_2ucode_type, + ic_bp_iu3_error => ic_bp_iu3_error, + ic_bp_iu3_flush => ic_bp_iu3_flush, + ic_bp_iu3_0_instr => ic_bp_iu3_0_instr, + ic_bp_iu3_1_instr => ic_bp_iu3_1_instr, + ic_bp_iu3_2_instr => ic_bp_iu3_2_instr, + ic_bp_iu3_3_instr => ic_bp_iu3_3_instr, + ib_ic_empty => ib_ic_empty, + ib_ic_below_water => ib_ic_below_water, + ib_ic_iu5_redirect_tid => ib_ic_iu5_redirect_tid, + ic_fdep_load_quiesce => ic_fdep_load_quiesce, + ic_fdep_icbi_ack => ic_fdep_icbi_ack, + uc_flush_tid => int_uc_flush_tid, + uc_ic_hold_thread => uc_ic_hold_thread +); +iuq_bp0 : entity work.iuq_bp +generic map(expand_type => expand_type) +port map( + bp_dbg_data0 => bp_dbg_data0, + bp_dbg_data1 => bp_dbg_data1, + iu3_0_bh_rd_data => iu3_0_bh_rd_data, + iu3_1_bh_rd_data => iu3_1_bh_rd_data, + iu3_2_bh_rd_data => iu3_2_bh_rd_data, + iu3_3_bh_rd_data => iu3_3_bh_rd_data, + iu1_bh_rd_addr => iu1_bh_rd_addr, + iu1_bh_rd_act => iu1_bh_rd_act, + ex6_bh_wr_data => ex6_bh_wr_data, + ex6_bh_wr_addr => ex6_bh_wr_addr, + ex6_bh_wr_act => ex6_bh_wr_act, + ic_bp_iu1_val => ic_bp_iu1_val, + ic_bp_iu1_tid => ic_bp_iu1_tid, + ic_bp_iu1_ifar => ic_bp_iu1_ifar, + ic_bp_iu3_val => ic_bp_iu3_val, + ic_bp_iu3_tid => ic_bp_iu3_tid, + ic_bp_iu3_ifar => ic_bp_iu3_ifar, + ic_bp_iu3_error => ic_bp_iu3_error, + ic_bp_iu3_2ucode => ic_bp_iu3_2ucode, + ic_bp_iu3_2ucode_type => ic_bp_iu3_2ucode_type, + ic_bp_iu3_flush => ic_bp_iu3_flush, + ic_bp_iu3_0_instr => ic_bp_iu3_0_instr, + ic_bp_iu3_1_instr => ic_bp_iu3_1_instr, + ic_bp_iu3_2_instr => ic_bp_iu3_2_instr, + ic_bp_iu3_3_instr => ic_bp_iu3_3_instr, + bp_ib_iu4_t0_val => bp_ib_iu4_t0_val, + bp_ib_iu4_t1_val => bp_ib_iu4_t1_val, + bp_ib_iu4_t2_val => bp_ib_iu4_t2_val, + bp_ib_iu4_t3_val => bp_ib_iu4_t3_val, + bp_ib_iu4_ifar => int_bp_ib_iu4_ifar, + bp_ib_iu3_0_instr => bp_ib_iu3_0_instr, + bp_ib_iu4_0_instr => bp_ib_iu4_0_instr, + bp_ib_iu4_1_instr => bp_ib_iu4_1_instr, + bp_ib_iu4_2_instr => bp_ib_iu4_2_instr, + bp_ib_iu4_3_instr => bp_ib_iu4_3_instr, + bp_ic_iu5_hold_tid => bp_ic_iu5_hold_tid, + bp_ic_iu5_redirect_tid => bp_ic_iu5_redirect_tid, + bp_ic_iu5_redirect_ifar => bp_ic_iu5_redirect_ifar, + xu_iu_ex5_ifar => xu_iu_ex5_ifar, + xu_iu_ex5_tid => xu_iu_ex5_tid, + xu_iu_ex5_val => xu_iu_ex5_val, + xu_iu_ex5_br_update => xu_iu_ex5_br_update, + xu_iu_ex5_br_hist => xu_iu_ex5_br_hist, + xu_iu_ex5_br_taken => xu_iu_ex5_br_taken, + xu_iu_ex5_bclr => xu_iu_ex5_bclr, + xu_iu_ex5_getNIA => xu_iu_ex5_getNIA, + xu_iu_ex5_lk => xu_iu_ex5_lk, + xu_iu_ex5_bh => xu_iu_ex5_bh, + xu_iu_ex5_gshare => xu_iu_ex5_gshare, + xu_iu_iu3_flush_tid => xu_iu_flush, + xu_iu_iu4_flush_tid => xu_iu_flush, + xu_iu_iu5_flush_tid => xu_iu_flush, + xu_iu_ex5_flush_tid => xu_ex5_flush, + ib_ic_iu5_redirect_tid => ib_ic_iu5_redirect_tid, + uc_flush_tid => int_uc_flush_tid, + spr_bp_config => spr_bp_config, + spr_bp_gshare_mask => spr_bp_gshare_mask, + vdd => vdd, + gnd => gnd, + nclk => nclk, + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b, + pc_iu_sg_2 => int_pc_iu_sg_2(0), + pc_iu_func_sl_thold_2 => int_pc_iu_func_sl_thold_2(0), + clkoff_b => int_clkoff_b(0), + +tc_ac_ccflush_dc => tc_ac_ccflush_dc, + +delay_lclkr => int_delay_lclkr(2), + mpw1_b => int_mpw1_b(2), + +scan_in => iuq_bp_scan_in(0 to 1), + scan_out => int_iuq_bp_scan_out(0 to 1) +); +u0: if ucode_mode = 0 generate +begin + iuq_uc_scan_out <= iuq_uc_scan_in; +int_uc_flush_tid <= (others => '0'); +uc_ib_iu4_val <= (others => '0'); +uc_ib_iu4_ifar <= (others => '0'); +uc_ib_iu4_instr <= (others => '0'); +uc_ic_hold_thread <= (others => '0'); +iu_pc_err_ucode_illegal <= (others => '0'); +end generate u0; +u1: if ucode_mode = 1 generate +begin +iuq_uc0 : entity work.iuq_uc +generic map(uc_ifar => uc_ifar, + regmode => regmode, + expand_type => expand_type) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_iu_func_sl_thold_2 => int_pc_iu_func_sl_thold_2(0), + pc_iu_sg_2 => int_pc_iu_sg_2(0), + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b, + tc_ac_ccflush_dc => tc_ac_ccflush_dc, + clkoff_b => int_clkoff_b(0), + delay_lclkr => int_delay_lclkr(3), + mpw1_b => int_mpw1_b(3), + scan_in => iuq_uc_scan_in, + scan_out => iuq_uc_scan_out, + spr_ic_clockgate_dis => spr_ic_clockgate_dis(0), + iu_pc_err_ucode_illegal => iu_pc_err_ucode_illegal, + xu_iu_spr_xer0 => xu_iu_spr_xer0, + xu_iu_spr_xer1 => xu_iu_spr_xer1, + xu_iu_spr_xer2 => xu_iu_spr_xer2, + xu_iu_spr_xer3 => xu_iu_spr_xer3, + xu_iu_flush => xu_iu_flush, + xu_iu_ucode_restart => xu_iu_ucode_restart, + xu_iu_uc_flush_ifar0 => xu_iu_uc_flush_ifar0, + xu_iu_uc_flush_ifar1 => xu_iu_uc_flush_ifar1, + xu_iu_uc_flush_ifar2 => xu_iu_uc_flush_ifar2, + xu_iu_uc_flush_ifar3 => xu_iu_uc_flush_ifar3, + uc_flush_tid => int_uc_flush_tid, + fiss_uc_is2_ucode_vld => fiss_uc_is2_ucode_vld, + fiss_uc_is2_tid => fiss_uc_is2_tid, + fiss_uc_is2_instr => fiss_uc_is2_instr, + fiss_uc_is2_2ucode => fiss_uc_is2_2ucode, + fiss_uc_is2_2ucode_type => fiss_uc_is2_2ucode_type, + ib_uc_buff0_avail => ib_ic_below_water(0), + ib_uc_buff1_avail => ib_ic_below_water(1), + ib_uc_buff2_avail => ib_ic_below_water(2), + ib_uc_buff3_avail => ib_ic_below_water(3), + uc_ib_iu4_valid_tid => uc_ib_iu4_val, + uc_ib_iu4_ifar => uc_ib_iu4_ifar(62-uc_ifar to 61), + uc_ib_iu4_instr => uc_ib_iu4_instr(0 to 31), + uc_ib_iu4_is_ucode => uc_ib_iu4_instr(36), + uc_ib_iu4_ext => uc_ib_iu4_instr(32 to 35), + uc_ic_hold_thread => uc_ic_hold_thread, + pc_iu_trace_bus_enable => pc_iu_trace_bus_enable, + uc_dbg_data => uc_dbg_data +); +end generate u1; +iuq_rp0 : entity work.iuq_rp +generic map(expand_type => expand_type) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + scan_diag_dc => an_ac_scan_diag_dc, + scan_dis_dc_b => an_ac_scan_dis_dc_b, + an_ac_ccflush_dc => tc_ac_ccflush_dc, + rtim_sl_thold_7 => rtim_sl_thold_7, + func_sl_thold_7 => func_sl_thold_7, + func_nsl_thold_7 => func_nsl_thold_7, + ary_nsl_thold_7 => ary_nsl_thold_7, + sg_7 => sg_7, + fce_7 => fce_7, + rtim_sl_thold_6 => rtim_sl_thold_6, + func_sl_thold_6 => func_sl_thold_6, + func_nsl_thold_6 => func_nsl_thold_6, + ary_nsl_thold_6 => ary_nsl_thold_6, + sg_6 => sg_6, + fce_6 => fce_6, + an_ac_scom_dch => an_ac_scom_dch, + an_ac_scom_cch => an_ac_scom_cch, + an_ac_checkstop => an_ac_checkstop, + an_ac_debug_stop => an_ac_debug_stop, + an_ac_pm_thread_stop => an_ac_pm_thread_stop, + an_ac_reset_1_complete => an_ac_reset_1_complete, + an_ac_reset_2_complete => an_ac_reset_2_complete, + an_ac_reset_3_complete => an_ac_reset_3_complete, + an_ac_reset_wd_complete => an_ac_reset_wd_complete, + an_ac_abist_start_test => an_ac_abist_start_test, + ac_rp_trace_to_perfcntr => ac_rp_trace_to_perfcntr, + rp_pc_scom_dch_q => rp_pc_scom_dch_q, + rp_pc_scom_cch_q => rp_pc_scom_cch_q, + rp_pc_checkstop_q => rp_pc_checkstop_q, + rp_pc_debug_stop_q => rp_pc_debug_stop_q, + rp_pc_pm_thread_stop_q => rp_pc_pm_thread_stop_q, + rp_pc_reset_1_complete_q => rp_pc_reset_1_complete_q, + rp_pc_reset_2_complete_q => rp_pc_reset_2_complete_q, + rp_pc_reset_3_complete_q => rp_pc_reset_3_complete_q, + rp_pc_reset_wd_complete_q => rp_pc_reset_wd_complete_q, + rp_pc_abist_start_test_q => rp_pc_abist_start_test_q, + rp_pc_trace_to_perfcntr_q => rp_pc_trace_to_perfcntr_q, + pc_rp_scom_dch => pc_rp_scom_dch, + pc_rp_scom_cch => pc_rp_scom_cch, + pc_rp_special_attn => pc_rp_special_attn, + pc_rp_checkstop => pc_rp_checkstop, + pc_rp_local_checkstop => pc_rp_local_checkstop, + pc_rp_recov_err => pc_rp_recov_err, + pc_rp_trace_error => pc_rp_trace_error, + pc_rp_event_bus_enable => pc_rp_event_bus_enable, + pc_rp_event_bus => pc_rp_event_bus, + pc_rp_fu_bypass_events => pc_rp_fu_bypass_events, + pc_rp_iu_bypass_events => pc_rp_iu_bypass_events, + pc_rp_mm_bypass_events => pc_rp_mm_bypass_events, + pc_rp_lsu_bypass_events => pc_rp_lsu_bypass_events, + pc_rp_pm_thread_running => pc_rp_pm_thread_running, + pc_rp_power_managed => pc_rp_power_managed, + pc_rp_rvwinkle_mode => pc_rp_rvwinkle_mode, + ac_an_scom_dch_q => ac_an_scom_dch_q, + ac_an_scom_cch_q => ac_an_scom_cch_q, + ac_an_special_attn_q => ac_an_special_attn_q, + ac_an_checkstop_q => ac_an_checkstop_q, + ac_an_local_checkstop_q => ac_an_local_checkstop_q, + ac_an_recov_err_q => ac_an_recov_err_q, + ac_an_trace_error_q => ac_an_trace_error_q, + rp_mm_event_bus_enable_q => rp_mm_event_bus_enable_q, + ac_an_event_bus_q => ac_an_event_bus_q, + ac_an_fu_bypass_events_q => ac_an_fu_bypass_events_q, + ac_an_iu_bypass_events_q => ac_an_iu_bypass_events_q, + ac_an_mm_bypass_events_q => ac_an_mm_bypass_events_q, + ac_an_lsu_bypass_events_q => ac_an_lsu_bypass_events_q, + ac_an_pm_thread_running_q => ac_an_pm_thread_running_q, + ac_an_power_managed_q => ac_an_power_managed_q_int, + ac_an_rvwinkle_mode_q => ac_an_rvwinkle_mode_q, + pc_func_scan_in => pc_func_scan_in, + pc_func_scan_in_q => pc_func_scan_in_q, + pc_func_scan_out => pc_func_scan_out, + pc_func_scan_out_q => pc_func_scan_out_q, + pc_bcfg_scan_in => pc_bcfg_scan_in, + pc_bcfg_scan_in_q => pc_bcfg_scan_in_q, + pc_dcfg_scan_in => pc_dcfg_scan_in, + pc_dcfg_scan_in_q => pc_dcfg_scan_in_q, + pc_bcfg_scan_out => pc_bcfg_scan_out, + pc_bcfg_scan_out_q => pc_bcfg_scan_out_q, + pc_ccfg_scan_out => pc_ccfg_scan_out, + pc_ccfg_scan_out_q => pc_ccfg_scan_out_q, + pc_dcfg_scan_out => pc_dcfg_scan_out, + pc_dcfg_scan_out_q => pc_dcfg_scan_out_q, + fu_abst_scan_in => fu_abst_scan_in, + fu_abst_scan_in_q => fu_abst_scan_in_q, + fu_abst_scan_out => fu_abst_scan_out, + fu_abst_scan_out_q => fu_abst_scan_out_q, + fu_ccfg_scan_out => fu_ccfg_scan_out, + fu_ccfg_scan_out_q => fu_ccfg_scan_out_q, + fu_bcfg_scan_out => fu_bcfg_scan_out, + fu_bcfg_scan_out_q => fu_bcfg_scan_out_q, + fu_dcfg_scan_out => fu_dcfg_scan_out, + fu_dcfg_scan_out_q => fu_dcfg_scan_out_q, + fu_func_scan_in => fu_func_scan_in, + fu_func_scan_in_q => fu_func_scan_in_q, + fu_func_scan_out => fu_func_scan_out, + fu_func_scan_out_q => fu_func_scan_out_q, + bx_abst_scan_in => bx_abst_scan_in, + bx_abst_scan_in_q => bx_abst_scan_in_q, + bx_abst_scan_out => bx_abst_scan_out, + bx_abst_scan_out_q => bx_abst_scan_out_q, + bx_func_scan_in => bx_func_scan_in, + bx_func_scan_in_q => bx_func_scan_in_q, + bx_func_scan_out => bx_func_scan_out, + bx_func_scan_out_q => bx_func_scan_out_q, + iu_func_scan_in => iu_func_scan_in, + iu_func_scan_in_q => int_iu_func_scan_in_q, + iu_func_scan_out => int_iu_func_scan_out, + iu_func_scan_out_q => iu_func_scan_out_q, + iu_bcfg_scan_in => bcfg_scan_in, + iu_bcfg_scan_in_q => bcfg_scan_in_q, + spare_func_scan_in => spare_func_scan_in, + spare_func_scan_in_q => spare_func_scan_in_q, + spare_func_scan_out => spare_func_scan_in_q, + spare_func_scan_out_q => spare_func_scan_out_q, + bg_an_ac_func_scan_sn => bg_an_ac_func_scan_sn, + bg_an_ac_abst_scan_sn => bg_an_ac_abst_scan_sn, + bg_an_ac_func_scan_sn_q => bg_an_ac_func_scan_sn_q, + bg_an_ac_abst_scan_sn_q => bg_an_ac_abst_scan_sn_q, + bg_ac_an_func_scan_ns => bg_ac_an_func_scan_ns, + bg_ac_an_abst_scan_ns => bg_ac_an_abst_scan_ns, + bg_ac_an_func_scan_ns_q => bg_ac_an_func_scan_ns_q, + bg_ac_an_abst_scan_ns_q => bg_ac_an_abst_scan_ns_q, + bg_pc_l1p_abist_di_0 => bg_pc_l1p_abist_di_0, + bg_pc_l1p_abist_g8t1p_renb_0 => bg_pc_l1p_abist_g8t1p_renb_0, + bg_pc_l1p_abist_g8t_bw_0 => bg_pc_l1p_abist_g8t_bw_0, + bg_pc_l1p_abist_g8t_bw_1 => bg_pc_l1p_abist_g8t_bw_1, + bg_pc_l1p_abist_g8t_dcomp => bg_pc_l1p_abist_g8t_dcomp, + bg_pc_l1p_abist_g8t_wenb => bg_pc_l1p_abist_g8t_wenb, + bg_pc_l1p_abist_raddr_0 => bg_pc_l1p_abist_raddr_0, + bg_pc_l1p_abist_waddr_0 => bg_pc_l1p_abist_waddr_0, + bg_pc_l1p_abist_wl128_comp_ena => bg_pc_l1p_abist_wl128_comp_ena, + bg_pc_l1p_abist_wl32_comp_ena => bg_pc_l1p_abist_wl32_comp_ena, + bg_pc_l1p_abist_di_0_q => bg_pc_l1p_abist_di_0_q, + bg_pc_l1p_abist_g8t1p_renb_0_q => bg_pc_l1p_abist_g8t1p_renb_0_q, + bg_pc_l1p_abist_g8t_bw_0_q => bg_pc_l1p_abist_g8t_bw_0_q, + bg_pc_l1p_abist_g8t_bw_1_q => bg_pc_l1p_abist_g8t_bw_1_q, + bg_pc_l1p_abist_g8t_dcomp_q=> bg_pc_l1p_abist_g8t_dcomp_q, + bg_pc_l1p_abist_g8t_wenb_q => bg_pc_l1p_abist_g8t_wenb_q, + bg_pc_l1p_abist_raddr_0_q => bg_pc_l1p_abist_raddr_0_q, + bg_pc_l1p_abist_waddr_0_q => bg_pc_l1p_abist_waddr_0_q, + bg_pc_l1p_abist_wl128_comp_ena_q => bg_pc_l1p_abist_wl128_comp_ena_q, + bg_pc_l1p_abist_wl32_comp_ena_q => bg_pc_l1p_abist_wl32_comp_ena_q, + bg_pc_l1p_gptr_sl_thold_3 => bg_pc_l1p_gptr_sl_thold_3, + bg_pc_l1p_time_sl_thold_3 => bg_pc_l1p_time_sl_thold_3, + bg_pc_l1p_repr_sl_thold_3 => bg_pc_l1p_repr_sl_thold_3, + bg_pc_l1p_abst_sl_thold_3 => bg_pc_l1p_abst_sl_thold_3, + bg_pc_l1p_func_sl_thold_3 => bg_pc_l1p_func_sl_thold_3, + bg_pc_l1p_func_slp_sl_thold_3 => bg_pc_l1p_func_slp_sl_thold_3, + bg_pc_l1p_bolt_sl_thold_3 => bg_pc_l1p_bolt_sl_thold_3, + bg_pc_l1p_ary_nsl_thold_3 => bg_pc_l1p_ary_nsl_thold_3, + bg_pc_l1p_sg_3 => bg_pc_l1p_sg_3, + bg_pc_l1p_fce_3 => bg_pc_l1p_fce_3, + bg_pc_l1p_bo_enable_3 => bg_pc_l1p_bo_enable_3, + bg_pc_l1p_gptr_sl_thold_2 => bg_pc_l1p_gptr_sl_thold_2, + bg_pc_l1p_time_sl_thold_2 => bg_pc_l1p_time_sl_thold_2, + bg_pc_l1p_repr_sl_thold_2 => bg_pc_l1p_repr_sl_thold_2, + bg_pc_l1p_abst_sl_thold_2 => bg_pc_l1p_abst_sl_thold_2, + bg_pc_l1p_func_sl_thold_2 => bg_pc_l1p_func_sl_thold_2, + bg_pc_l1p_func_slp_sl_thold_2 => bg_pc_l1p_func_slp_sl_thold_2, + bg_pc_l1p_bolt_sl_thold_2 => bg_pc_l1p_bolt_sl_thold_2, + bg_pc_l1p_ary_nsl_thold_2 => bg_pc_l1p_ary_nsl_thold_2, + bg_pc_l1p_sg_2 => bg_pc_l1p_sg_2, + bg_pc_l1p_fce_2 => bg_pc_l1p_fce_2, + bg_pc_l1p_bo_enable_2 => bg_pc_l1p_bo_enable_2, + pc_mm_bo_enable_4 => pc_mm_bo_enable_4_iiu, + pc_iu_bo_enable_4 => pc_iu_bo_enable_4, + pc_mm_bo_enable_3 => pc_mm_bo_enable_3_oiu, + pc_iu_bo_enable_3 => pc_iu_bo_enable_3, + pc_iu_gptr_sl_thold_4 => pc_iu_gptr_sl_thold_4, + pc_iu_time_sl_thold_4 => pc_iu_time_sl_thold_4, + pc_iu_repr_sl_thold_4 => pc_iu_repr_sl_thold_4, + pc_iu_abst_sl_thold_4 => pc_iu_abst_sl_thold_4, + pc_iu_abst_slp_sl_thold_4 => pc_iu_abst_slp_sl_thold_4, + pc_iu_bolt_sl_thold_4 => pc_iu_bolt_sl_thold_4, + pc_iu_regf_slp_sl_thold_4 => pc_iu_regf_slp_sl_thold_4, + pc_iu_func_sl_thold_4 => pc_iu_func_sl_thold_4, + pc_iu_func_slp_sl_thold_4 => pc_iu_func_slp_sl_thold_4, + pc_iu_cfg_sl_thold_4 => pc_iu_cfg_sl_thold_4, + pc_iu_cfg_slp_sl_thold_4 => pc_iu_cfg_slp_sl_thold_4, + pc_iu_func_nsl_thold_4 => pc_iu_func_nsl_thold_4, + pc_iu_func_slp_nsl_thold_4 => pc_iu_func_slp_nsl_thold_4, + pc_iu_ary_nsl_thold_4 => pc_iu_ary_nsl_thold_4, + pc_iu_ary_slp_nsl_thold_4 => pc_iu_ary_slp_nsl_thold_4, + pc_iu_sg_4 => pc_iu_sg_4, + pc_iu_fce_4 => pc_iu_fce_4, + pc_iu_gptr_sl_thold_3 => pc_iu_gptr_sl_thold_3, + pc_iu_time_sl_thold_3 => pc_iu_time_sl_thold_3, + pc_iu_repr_sl_thold_3 => pc_iu_repr_sl_thold_3, + pc_iu_abst_sl_thold_3 => pc_iu_abst_sl_thold_3, + pc_iu_abst_slp_sl_thold_3 => pc_iu_abst_slp_sl_thold_3, + pc_iu_bolt_sl_thold_3 => pc_iu_bolt_sl_thold_3, + pc_iu_regf_slp_sl_thold_3 => pc_iu_regf_slp_sl_thold_3, + pc_iu_func_sl_thold_3 => pc_iu_func_sl_thold_3, + pc_iu_func_slp_sl_thold_3 => pc_iu_func_slp_sl_thold_3, + pc_iu_cfg_sl_thold_3 => pc_iu_cfg_sl_thold_3, + pc_iu_cfg_slp_sl_thold_3 => pc_iu_cfg_slp_sl_thold_3, + pc_iu_func_slp_nsl_thold_3 => pc_iu_func_slp_nsl_thold_3, + pc_iu_ary_nsl_thold_3 => pc_iu_ary_nsl_thold_3, + pc_iu_ary_slp_nsl_thold_3 => pc_iu_ary_slp_nsl_thold_3, + pc_iu_sg_3 => pc_iu_sg_3, + pc_iu_fce_3 => pc_iu_fce_3, + pc_mm_gptr_sl_thold_3 => pc_mm_gptr_sl_thold_3, + pc_mm_time_sl_thold_3 => pc_mm_time_sl_thold_3, + pc_mm_repr_sl_thold_3 => pc_mm_repr_sl_thold_3, + pc_mm_abst_sl_thold_3 => pc_mm_abst_sl_thold_3, + pc_mm_abst_slp_sl_thold_3 => pc_mm_abst_slp_sl_thold_3, + pc_mm_bolt_sl_thold_3 => pc_mm_bolt_sl_thold_3, + pc_mm_func_sl_thold_3 => pc_mm_func_sl_thold_3, + pc_mm_func_slp_sl_thold_3 => pc_mm_func_slp_sl_thold_3, + pc_mm_cfg_sl_thold_3 => pc_mm_cfg_sl_thold_3, + pc_mm_cfg_slp_sl_thold_3 => pc_mm_cfg_slp_sl_thold_3, + pc_mm_func_nsl_thold_3 => pc_mm_func_nsl_thold_3, + pc_mm_func_slp_nsl_thold_3 => pc_mm_func_slp_nsl_thold_3, + pc_mm_ary_nsl_thold_3 => pc_mm_ary_nsl_thold_3, + pc_mm_ary_slp_nsl_thold_3 => pc_mm_ary_slp_nsl_thold_3, + pc_mm_sg_3 => pc_mm_sg_3, + pc_mm_fce_3 => pc_mm_fce_3, + sg_2 => int_pc_iu_sg_2(0), + func_sl_thold_2 => int_pc_iu_func_sl_thold_2(0), + func_slp_sl_thold_2 => pc_iu_func_slp_sl_thold_2, + abst_sl_thold_2 => pc_iu_abst_sl_thold_2, + abst_scan_in => rp_abst_scan_in, + func_scan_in => rp_func_scan_in, + gptr_scan_in => rp_gptr_scan_in, + abst_scan_out => rp_abst_scan_out, + func_scan_out => rp_func_scan_out, + gptr_scan_out => rp_gptr_scan_out +); +bg_pc_bo_unload_oiu <= bg_pc_bo_unload_iiu; +bg_pc_bo_load_oiu <= bg_pc_bo_load_iiu; +bg_pc_bo_repair_oiu <= bg_pc_bo_repair_iiu; +bg_pc_bo_reset_oiu <= bg_pc_bo_reset_iiu; +bg_pc_bo_shdata_oiu <= bg_pc_bo_shdata_iiu; +bg_pc_bo_select_oiu <= bg_pc_bo_select_iiu; +bg_pc_l1p_ccflush_dc_oiu <= bg_pc_l1p_ccflush_dc_iiu; +bg_pc_l1p_abist_ena_dc_oiu <= bg_pc_l1p_abist_ena_dc_iiu; +bg_pc_l1p_abist_raw_dc_b_oiu <= bg_pc_l1p_abist_raw_dc_b_iiu; +ac_an_abist_done_dc_oiu <= ac_an_abist_done_dc_iiu; +u_psro_rsig_i1: ac_an_psro_ringsig_i1_b <= not ac_an_psro_ringsig_iiu; +u_psro_rsig_i2: ac_an_psro_ringsig_i2 <= not ac_an_psro_ringsig_i1_b; +u_psro_rsig_i3: ac_an_psro_ringsig_i3_b <= not ac_an_psro_ringsig_i2; +u_psro_rsig_i4: ac_an_psro_ringsig_i4 <= not ac_an_psro_ringsig_i3_b; +u_psro_rsig_i5: ac_an_psro_ringsig_i5_b <= not ac_an_psro_ringsig_i4; +u_psro_rsig_i6: ac_an_psro_ringsig_oiu <= not ac_an_psro_ringsig_i5_b; +mm_pc_bo_fail_oiu <= mm_pc_bo_fail_iiu; +mm_pc_bo_diagout_oiu <= mm_pc_bo_diagout_iiu; +mm_pc_event_data_oiu <= mm_pc_event_data_iiu; +bg_pc_bo_fail_oiu <= bg_pc_bo_fail_iiu; +bg_pc_bo_diagout_oiu <= bg_pc_bo_diagout_iiu; +an_ac_abist_mode_dc_oiu <= an_ac_abist_mode_dc_iiu; +an_ac_ccenable_dc_oiu <= an_ac_ccenable_dc_iiu; +an_ac_ccflush_dc_oiu <= an_ac_ccflush_dc_iiu; +an_ac_gsd_test_enable_dc_oiu <= an_ac_gsd_test_enable_dc_iiu; +an_ac_gsd_test_acmode_dc_oiu <= an_ac_gsd_test_acmode_dc_iiu; +an_ac_lbist_ip_dc_oiu <= an_ac_lbist_ip_dc_iiu; +an_ac_lbist_ac_mode_dc_oiu <= an_ac_lbist_ac_mode_dc_iiu; +an_ac_malf_alert_oiu <= an_ac_malf_alert_iiu; +an_ac_psro_enable_dc_oiu <= an_ac_psro_enable_dc_iiu; +an_ac_scan_type_dc_oiu <= an_ac_scan_type_dc_iiu; +an_ac_scom_sat_id_oiu <= an_ac_scom_sat_id_iiu; +pc_mm_abist_dcomp_g6t_2r_oiu <= pc_mm_abist_dcomp_g6t_2r_iiu; +pc_mm_abist_di_g6t_2r_oiu <= pc_mm_abist_di_g6t_2r_iiu; +pc_mm_abist_di_0_oiu <= pc_mm_abist_di_0_iiu; +pc_mm_abist_ena_dc_oiu <= pc_mm_abist_ena_dc_iiu; +pc_mm_abist_g6t_r_wb_oiu <= pc_mm_abist_g6t_r_wb_iiu; +pc_mm_abist_g8t_bw_0_oiu <= pc_mm_abist_g8t_bw_0_iiu; +pc_mm_abist_g8t_bw_1_oiu <= pc_mm_abist_g8t_bw_1_iiu; +pc_mm_abist_g8t_dcomp_oiu <= pc_mm_abist_g8t_dcomp_iiu; +pc_mm_abist_g8t_wenb_oiu <= pc_mm_abist_g8t_wenb_iiu; +pc_mm_abist_g8t1p_renb_0_oiu <= pc_mm_abist_g8t1p_renb_0_iiu; +pc_mm_abist_raddr_0_oiu <= pc_mm_abist_raddr_0_iiu; +pc_mm_abist_raw_dc_b_oiu <= pc_mm_abist_raw_dc_b_iiu; +pc_mm_abist_waddr_0_oiu <= pc_mm_abist_waddr_0_iiu; +pc_mm_abist_wl128_comp_ena_oiu <= pc_mm_abist_wl128_comp_ena_iiu; +pc_mm_bo_repair_oiu <= pc_mm_bo_repair_iiu; +pc_mm_bo_reset_oiu <= pc_mm_bo_reset_iiu; +pc_mm_bo_select_oiu <= pc_mm_bo_select_iiu; +pc_mm_bo_shdata_oiu <= pc_mm_bo_shdata_iiu; +pc_mm_bo_unload_oiu <= pc_mm_bo_unload_iiu; +pc_mm_ccflush_dc_oiu <= pc_mm_ccflush_dc_iiu; +pc_mm_debug_mux1_ctrls_oiu <= pc_mm_debug_mux1_ctrls_iiu; +pc_mm_event_count_mode_oiu <= pc_mm_event_count_mode_iiu; +pc_mm_event_mux_ctrls_oiu <= pc_mm_event_mux_ctrls_iiu; +pc_mm_trace_bus_enable_oiu <= pc_mm_trace_bus_enable_iiu; +pc_mm_gptr_sl_thold_3_oiu <= pc_mm_gptr_sl_thold_3; +pc_mm_time_sl_thold_3_oiu <= pc_mm_time_sl_thold_3; +pc_mm_repr_sl_thold_3_oiu <= pc_mm_repr_sl_thold_3; +pc_mm_abst_sl_thold_3_oiu <= pc_mm_abst_sl_thold_3; +pc_mm_abst_slp_sl_thold_3_oiu <= pc_mm_abst_slp_sl_thold_3; +pc_mm_bolt_sl_thold_3_oiu <= pc_mm_bolt_sl_thold_3; +pc_mm_func_sl_thold_3_oiu <= pc_mm_func_sl_thold_3; +pc_mm_func_slp_sl_thold_3_oiu <= pc_mm_func_slp_sl_thold_3; +pc_mm_cfg_sl_thold_3_oiu <= pc_mm_cfg_sl_thold_3; +pc_mm_cfg_slp_sl_thold_3_oiu <= pc_mm_cfg_slp_sl_thold_3; +pc_mm_func_nsl_thold_3_oiu <= pc_mm_func_nsl_thold_3; +pc_mm_func_slp_nsl_thold_3_oiu <= pc_mm_func_slp_nsl_thold_3; +pc_mm_ary_nsl_thold_3_oiu <= pc_mm_ary_nsl_thold_3; +pc_mm_ary_slp_nsl_thold_3_oiu <= pc_mm_ary_slp_nsl_thold_3; +pc_mm_sg_3_oiu <= pc_mm_sg_3; +pc_mm_fce_3_oiu <= pc_mm_fce_3; +an_ac_back_inv_oiu <= an_ac_back_inv; +an_ac_back_inv_addr_oiu <= an_ac_back_inv_addr; +an_ac_back_inv_target_bit1_oiu <= an_ac_back_inv_target_iiu_a(1); +an_ac_back_inv_target_bit3_oiu <= an_ac_back_inv_target_iiu_b(3); +an_ac_back_inv_target_bit4_oiu <= an_ac_back_inv_target_iiu_b(4); +an_ac_atpg_en_dc_oiu <= an_ac_atpg_en_dc; +an_ac_lbist_ary_wrt_thru_dc_oiu <= an_ac_lbist_ary_wrt_thru_dc; +an_ac_lbist_en_dc_oiu <= an_ac_lbist_en_dc; +an_ac_scan_diag_dc_oiu <= an_ac_scan_diag_dc; +an_ac_scan_dis_dc_b_oiu <= an_ac_scan_dis_dc_b; +an_ac_grffence_en_dc_oiu <= an_ac_grffence_en_dc; +an_ac_scan_dis_dc_b_oif(0) <= an_ac_scan_dis_dc_b; +an_ac_scan_dis_dc_b_oif(1) <= an_ac_scan_dis_dc_b; +an_ac_scan_dis_dc_b_oif(2) <= an_ac_scan_dis_dc_b; +an_ac_scan_dis_dc_b_oif(3) <= an_ac_scan_dis_dc_b; +an_ac_back_inv_oif <= an_ac_back_inv; +an_ac_back_inv_target_oif(1) <= an_ac_back_inv_target_iiu_a(1); +an_ac_sync_ack_oif <= an_ac_sync_ack; +mm_iu_barrier_done_oif <= mm_iu_barrier_done; +iuq_ic_scan_in(0) <= func_scan_in(0); +func_scan_out(0) <= iuq_ic_scan_out(0); +iuq_ic_scan_in(1) <= func_scan_in(1); +func_scan_out(1) <= iuq_ic_scan_out(1); +iuq_ic_scan_in(2) <= func_scan_in(2); +func_scan_out(2) <= iuq_ic_scan_out(2); +iu_func_scan_in(0) <= func_scan_in(3); +iuq_bp_scan_in(1) <= int_iu_func_scan_in_q(0); +int_iu_func_scan_out(0) <= int_iuq_bp_scan_out(1); +int_iu_func_scan_out(1 to 8) <= iu_func_scan_out; +func_scan_out(3 to 11) <= iu_func_scan_out_q(0 to 8); +iu_func_scan_in(1) <= func_scan_in(4); +iuq_bp_scan_in(0) <= int_iu_func_scan_in_q(1); +iu_func_scan_in(2) <= func_scan_in(5); +iuq_mi_scan_in(0) <= int_iu_func_scan_in_q(2); +iu_func_scan_in(3) <= func_scan_in(6); +iu_func_scan_in_q(0) <= int_iu_func_scan_in_q(3); +iu_func_scan_in(4) <= func_scan_in(7); +iuq_mi_scan_in(1) <= int_iu_func_scan_in_q(4); +iu_func_scan_in(5 to 8) <= func_scan_in(8 to 11); +iu_func_scan_in_q(1 to 4) <= int_iu_func_scan_in_q(5 to 8); +iuq_ic_scan_in(3) <= func_scan_in(12); +func_scan_out(12) <= iuq_ic_scan_out(3); +iuq_ic_scan_in(4) <= func_scan_in(13); +iuq_uc_scan_in <= iuq_ic_scan_out(4); +int_iu_func_scan_out(9) <= iuq_uc_scan_out; +func_scan_out(13) <= iu_func_scan_out_q(9); +iuq_ic_time_scan_in <= time_scan_in; +iuq_mi_time_scan_in <= iuq_ic_time_scan_out; +time_scan_out <= iuq_mi_time_scan_out; +iuq_ic_repr_scan_in <= repr_scan_in; +iuq_mi_repr_scan_in <= iuq_ic_repr_scan_out; +repr_scan_out <= iuq_mi_repr_scan_out; +iuq_mi_abst_scan_in <= iuq_ic_abst_scan_out(2); +rp_gptr_scan_in <= gptr_scan_in; +iuq_mi_gptr_scan_in <= rp_gptr_scan_out; +gptr_scan_out <= iuq_mi_gptr_scan_out; +iuq_mi_ccfg_scan_in <= ccfg_scan_in; +iuq_ic_ccfg_scan_in <= iuq_mi_ccfg_scan_out; +ccfg_scan_out <= iuq_ic_ccfg_scan_out; +iuq_mi_bcfg_scan_in <= bcfg_scan_in_q; +bcfg_scan_out <= iuq_mi_bcfg_scan_out; +iuq_mi_dcfg_scan_in <= dcfg_scan_in; +dcfg_scan_out <= iuq_mi_dcfg_scan_out; +end iuq_ifetch; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_misc.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_misc.vhdl new file mode 100644 index 0000000..7e818a0 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_misc.vhdl @@ -0,0 +1,731 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; +use ieee.std_logic_1164.all; + +library ibm; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; + +library support; +use support.power_logic_pkg.all; + +library tri; +use tri.tri_latches_pkg.all; + +library work; +use work.iuq_pkg.all; + +entity iuq_misc is +generic(regmode : integer := 6; + a2mode : integer := 1; + expand_type : integer := 2 ); +port( + vdd : inout power_logic; + gnd : inout power_logic; + vcs : inout power_logic; + nclk : in clk_logic; + pc_iu_sg_3 : in std_ulogic_vector(0 to 3); + pc_iu_func_sl_thold_3 : in std_ulogic_vector(0 to 3); + pc_iu_func_slp_sl_thold_3 : in std_ulogic; + pc_iu_gptr_sl_thold_3 : in std_ulogic; + pc_iu_time_sl_thold_3 : in std_ulogic; + pc_iu_repr_sl_thold_3 : in std_ulogic; + pc_iu_abst_sl_thold_3 : in std_ulogic; + pc_iu_abst_slp_sl_thold_3 : in std_ulogic; + pc_iu_cfg_sl_thold_3 : in std_ulogic; + pc_iu_cfg_slp_sl_thold_3 : in std_ulogic; + pc_iu_regf_slp_sl_thold_3 : in std_ulogic; + pc_iu_ary_nsl_thold_3 : in std_ulogic; + pc_iu_ary_slp_nsl_thold_3 : in std_ulogic; + pc_iu_func_slp_nsl_thold_3 : in std_ulogic; + pc_iu_bolt_sl_thold_3 : in std_ulogic; + pc_iu_fce_3 : in std_ulogic; + tc_ac_ccflush_dc : in std_ulogic; + scan_diag_dc : in std_ulogic; + pc_iu_sg_2 : out std_ulogic_vector(0 to 3); + pc_iu_func_sl_thold_2 : out std_ulogic_vector(0 to 3); + pc_iu_func_slp_sl_thold_2 : out std_ulogic; + pc_iu_time_sl_thold_2 : out std_ulogic; + pc_iu_repr_sl_thold_2 : out std_ulogic; + pc_iu_abst_sl_thold_2 : out std_ulogic; + pc_iu_abst_slp_sl_thold_2 : out std_ulogic; + pc_iu_cfg_slp_sl_thold_2 : out std_ulogic; + pc_iu_regf_slp_sl_thold_2 : out std_ulogic; + pc_iu_ary_nsl_thold_2 : out std_ulogic; + pc_iu_ary_slp_nsl_thold_2 : out std_ulogic; + pc_iu_func_slp_nsl_thold_2 : out std_ulogic; + pc_iu_bolt_sl_thold_2 : out std_ulogic; + pc_iu_fce_2 : out std_ulogic; + + clkoff_b : out std_ulogic_vector(0 to 2); + delay_lclkr : out std_ulogic_vector(1 to 14); + mpw1_b : out std_ulogic_vector(1 to 14); + + g8t_clkoff_b : out std_ulogic; + g8t_d_mode : out std_ulogic; + g8t_delay_lclkr : out std_ulogic_vector(0 to 4); + g8t_mpw1_b : out std_ulogic_vector(0 to 4); + g8t_mpw2_b : out std_ulogic; + + g6t_clkoff_b : out std_ulogic; + g6t_d_mode : out std_ulogic; + g6t_delay_lclkr : out std_ulogic_vector(0 to 3); + g6t_mpw1_b : out std_ulogic_vector(0 to 4); + g6t_mpw2_b : out std_ulogic; + + cam_clkoff_b : out std_ulogic; + cam_d_mode : out std_ulogic; + cam_delay_lclkr : out std_ulogic_vector(0 to 4); + cam_mpw1_b : out std_ulogic_vector(0 to 4); + cam_mpw2_b : out std_ulogic; + + an_ac_scan_dis_dc_b : in std_ulogic; + func_scan_in : in std_ulogic_vector(0 to 1); + gptr_scan_in : in std_ulogic; + time_scan_in : in std_ulogic; + abst_scan_in : in std_ulogic; + repr_scan_in : in std_ulogic; + ccfg_scan_in : in std_ulogic; + bcfg_scan_in : in std_ulogic; + dcfg_scan_in : in std_ulogic; + func_scan_out : out std_ulogic_vector(0 to 1); + gptr_scan_out : out std_ulogic; + time_scan_out : out std_ulogic; + abst_scan_out : out std_ulogic; + repr_scan_out : out std_ulogic; + ccfg_scan_out : out std_ulogic; + bcfg_scan_out : out std_ulogic; + dcfg_scan_out : out std_ulogic; + + pc_iu_abist_di_0 : in std_ulogic_vector(0 to 3); + pc_iu_abist_g8t_bw_1 : in std_ulogic; + pc_iu_abist_g8t_bw_0 : in std_ulogic; + pc_iu_abist_waddr_0 : in std_ulogic_vector(3 to 9); + pc_iu_abist_g8t_wenb : in std_ulogic; + pc_iu_abist_raddr_0 : in std_ulogic_vector(3 to 9); + pc_iu_abist_g8t1p_renb_0 : in std_ulogic; + an_ac_lbist_ary_wrt_thru_dc: in std_ulogic; + pc_iu_abist_ena_dc : in std_ulogic; + pc_iu_abist_wl128_comp_ena : in std_ulogic; + pc_iu_abist_raw_dc_b : in std_ulogic; + pc_iu_abist_g8t_dcomp : in std_ulogic_vector(0 to 3); + + pc_iu_bo_enable_3 : in std_ulogic; + pc_iu_bo_reset : in std_ulogic; + pc_iu_bo_unload : in std_ulogic; + pc_iu_bo_repair : in std_ulogic; + pc_iu_bo_shdata : in std_ulogic; + pc_iu_bo_select : in std_ulogic; + iu_pc_bo_fail : out std_ulogic; + iu_pc_bo_diagout : out std_ulogic; + + r_act : in std_ulogic; + w_act : in std_ulogic_vector(0 to 3); + r_addr : in std_ulogic_vector(0 to 7); + w_addr : in std_ulogic_vector(0 to 7); + data_in : in std_ulogic_vector(0 to 1); + data_out0 : out std_ulogic_vector(0 to 1); + data_out1 : out std_ulogic_vector(0 to 1); + data_out2 : out std_ulogic_vector(0 to 1); + data_out3 : out std_ulogic_vector(0 to 1); + + pc_iu_ram_instr : in std_ulogic_vector(0 to 31); + pc_iu_ram_instr_ext : in std_ulogic_vector(0 to 3); + pc_iu_ram_force_cmplt : in std_ulogic; + xu_iu_ram_issue : in std_ulogic_vector(0 to 3); + rm_ib_iu4_val : out std_ulogic_vector(0 to 3); + rm_ib_iu4_force_ram : out std_ulogic; + rm_ib_iu4_instr : out std_ulogic_vector(0 to 35); + + slowspr_val_in : in std_ulogic; + slowspr_rw_in : in std_ulogic; + slowspr_etid_in : in std_ulogic_vector(0 to 1); + slowspr_addr_in : in std_ulogic_vector(0 to 9); + slowspr_data_in : in std_ulogic_vector(64-(2**regmode) to 63); + slowspr_done_in : in std_ulogic; + slowspr_val_out : out std_ulogic; + slowspr_rw_out : out std_ulogic; + slowspr_etid_out : out std_ulogic_vector(0 to 1); + slowspr_addr_out : out std_ulogic_vector(0 to 9); + slowspr_data_out : out std_ulogic_vector(64-(2**regmode) to 63); + slowspr_done_out : out std_ulogic; + spr_ic_idir_read : out std_ulogic; + spr_ic_idir_way : out std_ulogic_vector(0 to 1); + spr_ic_idir_row : out std_ulogic_vector(52 to 57); + ic_spr_idir_done : in std_ulogic; + ic_spr_idir_lru : in std_ulogic_vector(0 to 2); + ic_spr_idir_parity : in std_ulogic_vector(0 to 3); + ic_spr_idir_endian : in std_ulogic; + ic_spr_idir_valid : in std_ulogic; + ic_spr_idir_tag : in std_ulogic_vector(0 to 29); + spr_ic_icbi_ack_en : out std_ulogic; + spr_ic_cls : out std_ulogic; + spr_ic_clockgate_dis : out std_ulogic_vector(0 to 1); + spr_ic_bp_config : out std_ulogic_vector(0 to 3); + spr_bp_config : out std_ulogic_vector(0 to 3); + spr_bp_gshare_mask : out std_ulogic_vector(0 to 3); + spr_dec_mask : out std_ulogic_vector(0 to 31); + spr_dec_match : out std_ulogic_vector(0 to 31); + iu_au_config_iucr_t0 : out std_ulogic_vector(0 to 7); + iu_au_config_iucr_t1 : out std_ulogic_vector(0 to 7); + iu_au_config_iucr_t2 : out std_ulogic_vector(0 to 7); + iu_au_config_iucr_t3 : out std_ulogic_vector(0 to 7); + spr_issue_high_mask : out std_ulogic_vector(0 to 3); + spr_issue_med_mask : out std_ulogic_vector(0 to 3); + spr_fiss_count0_max : out std_ulogic_vector(0 to 5); + spr_fiss_count1_max : out std_ulogic_vector(0 to 5); + spr_fiss_count2_max : out std_ulogic_vector(0 to 5); + spr_fiss_count3_max : out std_ulogic_vector(0 to 5); + spr_ic_pri_rand : out std_ulogic_vector(0 to 4); + spr_ic_pri_rand_always : out std_ulogic; + spr_ic_pri_rand_flush : out std_ulogic; + spr_fiss_pri_rand : out std_ulogic_vector(0 to 4); + spr_fiss_pri_rand_always : out std_ulogic; + spr_fiss_pri_rand_flush : out std_ulogic; + spr_fdep_ll_hold : out std_ulogic; + xu_iu_run_thread : in std_ulogic_vector(0 to 3); + xu_iu_ex6_pri : in std_ulogic_vector(0 to 2); + xu_iu_ex6_pri_val : in std_ulogic_vector(0 to 3); + xu_iu_raise_iss_pri : in std_ulogic_vector(0 to 3); + xu_iu_msr_gs : in std_ulogic_vector(0 to 3); + xu_iu_msr_pr : in std_ulogic_vector(0 to 3); + + pc_iu_trace_bus_enable : in std_ulogic; + pc_iu_debug_mux_ctrls : in std_ulogic_vector(0 to 15); + debug_data_in : in std_ulogic_vector(0 to 87); + trace_triggers_in : in std_ulogic_vector(0 to 11); + debug_data_out : out std_ulogic_vector(0 to 87); + trace_triggers_out : out std_ulogic_vector(0 to 11); + + fiss_dbg_data : in std_ulogic_vector(0 to 87); + fdep_dbg_data : in std_ulogic_vector(0 to 87); + ib_dbg_data : in std_ulogic_vector(0 to 63); + bp_dbg_data0 : in std_ulogic_vector(0 to 87); + bp_dbg_data1 : in std_ulogic_vector(0 to 87); + fu_iss_dbg_data : in std_ulogic_vector(0 to 23); + axu_dbg_data_t0 : in std_ulogic_vector(0 to 37); + axu_dbg_data_t1 : in std_ulogic_vector(0 to 37); + axu_dbg_data_t2 : in std_ulogic_vector(0 to 37); + axu_dbg_data_t3 : in std_ulogic_vector(0 to 37); + + + ic_perf_event_t0 : in std_ulogic_vector(0 to 6); + ic_perf_event_t1 : in std_ulogic_vector(0 to 6); + ic_perf_event_t2 : in std_ulogic_vector(0 to 6); + ic_perf_event_t3 : in std_ulogic_vector(0 to 6); + ic_perf_event : in std_ulogic_vector(0 to 1); + ib_perf_event_t0 : in std_ulogic_vector(0 to 1); + ib_perf_event_t1 : in std_ulogic_vector(0 to 1); + ib_perf_event_t2 : in std_ulogic_vector(0 to 1); + ib_perf_event_t3 : in std_ulogic_vector(0 to 1); + fdep_perf_event_t0 : in std_ulogic_vector(0 to 11); + fdep_perf_event_t1 : in std_ulogic_vector(0 to 11); + fdep_perf_event_t2 : in std_ulogic_vector(0 to 11); + fdep_perf_event_t3 : in std_ulogic_vector(0 to 11); + fiss_perf_event_t0 : in std_ulogic_vector(0 to 7); + fiss_perf_event_t1 : in std_ulogic_vector(0 to 7); + fiss_perf_event_t2 : in std_ulogic_vector(0 to 7); + fiss_perf_event_t3 : in std_ulogic_vector(0 to 7); + pc_iu_event_mux_ctrls : in std_ulogic_vector(0 to 47); + pc_iu_event_count_mode : in std_ulogic_vector(0 to 2); + pc_iu_event_bus_enable : in std_ulogic; + iu_pc_event_data : out std_ulogic_vector(0 to 7) +); + +-- synopsys translate_off + + +-- synopsys translate_on + +end iuq_misc; +architecture iuq_misc of iuq_misc is + +signal iuq_pv_gptr_scan_in : std_ulogic; +signal iuq_pv_gptr_scan_out : std_ulogic; + +signal iuq_bh_scan_in : std_ulogic; +signal iuq_bh_scan_out : std_ulogic; +signal iuq_rm_scan_in : std_ulogic; +signal iuq_rm_scan_out : std_ulogic; +signal iuq_sp_scan_in : std_ulogic; +signal iuq_sp_scan_out : std_ulogic; +signal iuq_pf_scan_in : std_ulogic; +signal iuq_pf_scan_out : std_ulogic; +signal iuq_db_scan_in : std_ulogic; +signal iuq_db_scan_out : std_ulogic; + +signal iuq_bh_repr_scan_in : std_ulogic; +signal iuq_bh_repr_scan_out : std_ulogic; +signal iuq_bh_time_scan_in : std_ulogic; +signal iuq_bh_time_scan_out : std_ulogic; +signal iuq_bh_abst_scan_in : std_ulogic; +signal iuq_bh_abst_scan_out : std_ulogic; + +signal iuq_sp_ccfg_scan_in : std_ulogic; +signal iuq_sp_ccfg_scan_out : std_ulogic; +signal iuq_sp_bcfg_scan_in : std_ulogic; +signal iuq_sp_bcfg_scan_out : std_ulogic; +signal iuq_sp_dcfg_scan_in : std_ulogic; +signal iuq_sp_dcfg_scan_out : std_ulogic; + + +signal int_pc_iu_sg_2 : std_ulogic_vector(0 to 3); +signal int_pc_iu_func_sl_thold_2 : std_ulogic_vector(0 to 3); +signal int_pc_iu_func_slp_sl_thold_2 : std_ulogic; +signal int_pc_iu_time_sl_thold_2 : std_ulogic; +signal int_pc_iu_repr_sl_thold_2 : std_ulogic; +signal int_pc_iu_abst_sl_thold_2 : std_ulogic; +signal int_pc_iu_cfg_sl_thold_2 : std_ulogic; +signal int_pc_iu_cfg_slp_sl_thold_2 : std_ulogic; +signal int_pc_iu_regf_slp_sl_thold_2 : std_ulogic; +signal int_pc_iu_ary_nsl_thold_2 : std_ulogic; +signal int_pc_iu_bolt_sl_thold_2 : std_ulogic; +signal pc_iu_bo_enable_2 : std_ulogic; +signal int_clkoff_b : std_ulogic_vector(0 to 2); +signal int_act_dis : std_ulogic_vector(0 to 2); +signal int_d_mode : std_ulogic_vector(0 to 2); +signal int_delay_lclkr : std_ulogic_vector(0 to 14); +signal int_mpw1_b : std_ulogic_vector(0 to 14); +signal int_mpw2_b : std_ulogic_vector(0 to 2); +signal bht_g8t_clkoff_b : std_ulogic; +signal bht_g8t_d_mode : std_ulogic; +signal bht_g8t_delay_lclkr : std_ulogic_vector(0 to 4); +signal bht_g8t_mpw1_b : std_ulogic_vector(0 to 4); +signal bht_g8t_mpw2_b : std_ulogic; + +signal bht_dbg_data : std_ulogic_vector(0 to 31); +signal data_out0_int : std_ulogic_vector(0 to 1); +signal data_out1_int : std_ulogic_vector(0 to 1); +signal data_out2_int : std_ulogic_vector(0 to 1); +signal data_out3_int : std_ulogic_vector(0 to 1); + + +-- synopsys translate_off +-- synopsys translate_on + + +begin + + + +pc_iu_sg_2 <= int_pc_iu_sg_2; +pc_iu_func_sl_thold_2 <= int_pc_iu_func_sl_thold_2; +pc_iu_func_slp_sl_thold_2<= int_pc_iu_func_slp_sl_thold_2; +pc_iu_time_sl_thold_2 <= int_pc_iu_time_sl_thold_2; +pc_iu_repr_sl_thold_2 <= int_pc_iu_repr_sl_thold_2; +pc_iu_abst_sl_thold_2 <= int_pc_iu_abst_sl_thold_2; +pc_iu_cfg_slp_sl_thold_2 <= int_pc_iu_cfg_slp_sl_thold_2; +pc_iu_regf_slp_sl_thold_2 <= int_pc_iu_regf_slp_sl_thold_2; +pc_iu_ary_nsl_thold_2 <= int_pc_iu_ary_nsl_thold_2; +pc_iu_bolt_sl_thold_2 <= int_pc_iu_bolt_sl_thold_2; +clkoff_b <= int_clkoff_b; +delay_lclkr(1 to 14) <= int_delay_lclkr(1 to 14); +mpw1_b(1 to 14) <= int_mpw1_b(1 to 14); + + + +iuq_perv0 : entity work.iuq_perv +generic map (expand_type => expand_type) +port map ( + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_iu_sg_3 => pc_iu_sg_3, + pc_iu_func_sl_thold_3 => pc_iu_func_sl_thold_3, + pc_iu_func_slp_sl_thold_3 => pc_iu_func_slp_sl_thold_3, + pc_iu_gptr_sl_thold_3 => pc_iu_gptr_sl_thold_3, + pc_iu_time_sl_thold_3 => pc_iu_time_sl_thold_3, + pc_iu_repr_sl_thold_3 => pc_iu_repr_sl_thold_3, + pc_iu_abst_sl_thold_3 => pc_iu_abst_sl_thold_3, + pc_iu_abst_slp_sl_thold_3 => pc_iu_abst_slp_sl_thold_3, + pc_iu_cfg_sl_thold_3 => pc_iu_cfg_sl_thold_3, + pc_iu_cfg_slp_sl_thold_3 => pc_iu_cfg_slp_sl_thold_3, + pc_iu_regf_slp_sl_thold_3 => pc_iu_regf_slp_sl_thold_3, + pc_iu_ary_nsl_thold_3 => pc_iu_ary_nsl_thold_3, + pc_iu_ary_slp_nsl_thold_3 => pc_iu_ary_slp_nsl_thold_3, + pc_iu_func_slp_nsl_thold_3 => pc_iu_func_slp_nsl_thold_3, + pc_iu_bolt_sl_thold_3 => pc_iu_bolt_sl_thold_3, + pc_iu_bo_enable_3 => pc_iu_bo_enable_3, + pc_iu_fce_3 => pc_iu_fce_3, + tc_ac_ccflush_dc => tc_ac_ccflush_dc, + scan_diag_dc => scan_diag_dc, + pc_iu_sg_2 => int_pc_iu_sg_2, + pc_iu_func_sl_thold_2 => int_pc_iu_func_sl_thold_2, + pc_iu_func_slp_sl_thold_2=> int_pc_iu_func_slp_sl_thold_2, + pc_iu_time_sl_thold_2 => int_pc_iu_time_sl_thold_2, + pc_iu_repr_sl_thold_2 => int_pc_iu_repr_sl_thold_2, + pc_iu_abst_sl_thold_2 => int_pc_iu_abst_sl_thold_2, + pc_iu_abst_slp_sl_thold_2 => pc_iu_abst_slp_sl_thold_2, + pc_iu_cfg_sl_thold_2 => int_pc_iu_cfg_sl_thold_2, + pc_iu_cfg_slp_sl_thold_2 => int_pc_iu_cfg_slp_sl_thold_2, + pc_iu_regf_slp_sl_thold_2 => int_pc_iu_regf_slp_sl_thold_2, + pc_iu_ary_nsl_thold_2 => int_pc_iu_ary_nsl_thold_2, + pc_iu_ary_slp_nsl_thold_2 => pc_iu_ary_slp_nsl_thold_2, + pc_iu_func_slp_nsl_thold_2 => pc_iu_func_slp_nsl_thold_2, + pc_iu_bolt_sl_thold_2 => int_pc_iu_bolt_sl_thold_2, + pc_iu_bo_enable_2 => pc_iu_bo_enable_2, + pc_iu_fce_2 => pc_iu_fce_2, + clkoff_b => int_clkoff_b, + act_dis => int_act_dis, + d_mode => int_d_mode, + delay_lclkr => int_delay_lclkr, + mpw1_b => int_mpw1_b, + mpw2_b => int_mpw2_b, + bht_g8t_clkoff_b => bht_g8t_clkoff_b, + bht_g8t_d_mode => bht_g8t_d_mode, + bht_g8t_delay_lclkr => bht_g8t_delay_lclkr, + bht_g8t_mpw1_b => bht_g8t_mpw1_b, + bht_g8t_mpw2_b => bht_g8t_mpw2_b, + g8t_clkoff_b => g8t_clkoff_b, + g8t_d_mode => g8t_d_mode, + g8t_delay_lclkr => g8t_delay_lclkr, + g8t_mpw1_b => g8t_mpw1_b, + g8t_mpw2_b => g8t_mpw2_b, + g6t_clkoff_b => g6t_clkoff_b, + g6t_d_mode => g6t_d_mode, + g6t_delay_lclkr => g6t_delay_lclkr, + g6t_mpw1_b => g6t_mpw1_b, + g6t_mpw2_b => g6t_mpw2_b, + cam_clkoff_b => cam_clkoff_b, + cam_d_mode => cam_d_mode, + cam_delay_lclkr => cam_delay_lclkr, + cam_mpw1_b => cam_mpw1_b, + cam_mpw2_b => cam_mpw2_b, + gptr_scan_in => iuq_pv_gptr_scan_in, + gptr_scan_out => iuq_pv_gptr_scan_out); + + +bht: entity tri.tri_bht + generic map ( expand_type => expand_type ) + port map( + gnd => gnd, + vdd => vdd, + vcs => vcs, + nclk => nclk, + pc_iu_func_sl_thold_2 => int_pc_iu_func_sl_thold_2(0), + pc_iu_sg_2 => int_pc_iu_sg_2(3), + pc_iu_time_sl_thold_2 => int_pc_iu_time_sl_thold_2, + pc_iu_abst_sl_thold_2 => int_pc_iu_abst_sl_thold_2, + pc_iu_ary_nsl_thold_2 => int_pc_iu_ary_nsl_thold_2, + pc_iu_repr_sl_thold_2 => int_pc_iu_repr_sl_thold_2, + pc_iu_bolt_sl_thold_2 => int_pc_iu_bolt_sl_thold_2, + tc_ac_ccflush_dc => tc_ac_ccflush_dc, + tc_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b, + clkoff_b => int_clkoff_b(0), + scan_diag_dc => scan_diag_dc, + act_dis => int_act_dis(0), + d_mode => int_d_mode(0), + delay_lclkr => int_delay_lclkr(0), + mpw1_b => int_mpw1_b(0), + mpw2_b => int_mpw2_b(0), + g8t_clkoff_b => bht_g8t_clkoff_b, + g8t_d_mode => bht_g8t_d_mode, + g8t_delay_lclkr => bht_g8t_delay_lclkr, + g8t_mpw1_b => bht_g8t_mpw1_b, + g8t_mpw2_b => bht_g8t_mpw2_b, + func_scan_in => iuq_bh_scan_in, + time_scan_in => iuq_bh_time_scan_in, + abst_scan_in => iuq_bh_abst_scan_in, + repr_scan_in => iuq_bh_repr_scan_in, + func_scan_out => iuq_bh_scan_out, + time_scan_out => iuq_bh_time_scan_out, + abst_scan_out => iuq_bh_abst_scan_out, + repr_scan_out => iuq_bh_repr_scan_out, + pc_iu_abist_di_0 => pc_iu_abist_di_0, + pc_iu_abist_g8t_bw_1 => pc_iu_abist_g8t_bw_1, + pc_iu_abist_g8t_bw_0 => pc_iu_abist_g8t_bw_0, + pc_iu_abist_waddr_0 => pc_iu_abist_waddr_0(3 to 9), + pc_iu_abist_g8t_wenb => pc_iu_abist_g8t_wenb, + pc_iu_abist_raddr_0 => pc_iu_abist_raddr_0(3 to 9), + pc_iu_abist_g8t1p_renb_0 => pc_iu_abist_g8t1p_renb_0, + an_ac_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc, + pc_iu_abist_ena_dc => pc_iu_abist_ena_dc, + pc_iu_abist_wl128_comp_ena => pc_iu_abist_wl128_comp_ena, + pc_iu_abist_raw_dc_b => pc_iu_abist_raw_dc_b, + pc_iu_abist_g8t_dcomp => pc_iu_abist_g8t_dcomp, + pc_iu_bo_enable_2 => pc_iu_bo_enable_2, + pc_iu_bo_reset => pc_iu_bo_reset, + pc_iu_bo_unload => pc_iu_bo_unload, + pc_iu_bo_repair => pc_iu_bo_repair, + pc_iu_bo_shdata => pc_iu_bo_shdata, + pc_iu_bo_select => pc_iu_bo_select, + iu_pc_bo_fail => iu_pc_bo_fail, + iu_pc_bo_diagout => iu_pc_bo_diagout, + r_act => r_act, + w_act => w_act, + r_addr => r_addr, + w_addr => w_addr, + data_in => data_in, + data_out0 => data_out0_int, + data_out1 => data_out1_int, + data_out2 => data_out2_int, + data_out3 => data_out3_int +); + +data_out0 <= data_out0_int; +data_out1 <= data_out1_int; +data_out2 <= data_out2_int; +data_out3 <= data_out3_int; + +iuq_ram0 : entity work.iuq_ram +generic map ( expand_type => expand_type ) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_iu_func_sl_thold_2 => int_pc_iu_func_sl_thold_2(0), + pc_iu_sg_2 => int_pc_iu_sg_2(3), + clkoff_b => int_clkoff_b(0), + act_dis => int_act_dis(0), + tc_ac_ccflush_dc => tc_ac_ccflush_dc, + d_mode => int_d_mode(0), + delay_lclkr => int_delay_lclkr(0), + mpw1_b => int_mpw1_b(0), + mpw2_b => int_mpw2_b(0), + scan_in => iuq_rm_scan_in, + scan_out => iuq_rm_scan_out, + pc_iu_ram_instr => pc_iu_ram_instr, + pc_iu_ram_instr_ext => pc_iu_ram_instr_ext, + pc_iu_ram_force_cmplt => pc_iu_ram_force_cmplt, + xu_iu_ram_issue => xu_iu_ram_issue, + rm_ib_iu4_val => rm_ib_iu4_val, + rm_ib_iu4_force_ram => rm_ib_iu4_force_ram, + rm_ib_iu4_instr => rm_ib_iu4_instr +); + +iuq_spr : entity work.iuq_spr +generic map(regmode => regmode, + a2mode => a2mode, + expand_type => expand_type) +port map( + slowspr_val_in => slowspr_val_in, + slowspr_rw_in => slowspr_rw_in, + slowspr_etid_in => slowspr_etid_in, + slowspr_addr_in => slowspr_addr_in, + slowspr_data_in => slowspr_data_in, + slowspr_done_in => slowspr_done_in, + slowspr_val_out => slowspr_val_out, + slowspr_rw_out => slowspr_rw_out, + slowspr_etid_out => slowspr_etid_out, + slowspr_addr_out => slowspr_addr_out, + slowspr_data_out => slowspr_data_out, + slowspr_done_out => slowspr_done_out, + spr_ic_idir_read => spr_ic_idir_read, + spr_ic_idir_way => spr_ic_idir_way, + spr_ic_idir_row => spr_ic_idir_row, + ic_spr_idir_done => ic_spr_idir_done, + ic_spr_idir_lru => ic_spr_idir_lru, + ic_spr_idir_parity => ic_spr_idir_parity, + ic_spr_idir_endian => ic_spr_idir_endian, + ic_spr_idir_valid => ic_spr_idir_valid, + ic_spr_idir_tag => ic_spr_idir_tag, + spr_ic_icbi_ack_en => spr_ic_icbi_ack_en, + spr_ic_cls => spr_ic_cls, + spr_ic_clockgate_dis => spr_ic_clockgate_dis, + spr_ic_bp_config => spr_ic_bp_config, + spr_bp_config => spr_bp_config, + spr_bp_gshare_mask => spr_bp_gshare_mask, + spr_issue_high_mask => spr_issue_high_mask, + spr_issue_med_mask => spr_issue_med_mask, + spr_fiss_count0_max => spr_fiss_count0_max, + spr_fiss_count1_max => spr_fiss_count1_max, + spr_fiss_count2_max => spr_fiss_count2_max, + spr_fiss_count3_max => spr_fiss_count3_max, + spr_ic_pri_rand => spr_ic_pri_rand, + spr_ic_pri_rand_always => spr_ic_pri_rand_always, + spr_ic_pri_rand_flush => spr_ic_pri_rand_flush, + spr_fiss_pri_rand => spr_fiss_pri_rand, + spr_fiss_pri_rand_always => spr_fiss_pri_rand_always, + spr_fiss_pri_rand_flush => spr_fiss_pri_rand_flush, + spr_dec_mask => spr_dec_mask, + spr_dec_match => spr_dec_match, + spr_fdep_ll_hold => spr_fdep_ll_hold, + xu_iu_run_thread => xu_iu_run_thread, + iu_au_config_iucr_t0 => iu_au_config_iucr_t0, + iu_au_config_iucr_t1 => iu_au_config_iucr_t1, + iu_au_config_iucr_t2 => iu_au_config_iucr_t2, + iu_au_config_iucr_t3 => iu_au_config_iucr_t3, + xu_iu_ex6_pri => xu_iu_ex6_pri, + xu_iu_ex6_pri_val => xu_iu_ex6_pri_val, + xu_iu_raise_iss_pri => xu_iu_raise_iss_pri, + xu_iu_msr_gs => xu_iu_msr_gs, + xu_iu_msr_pr => xu_iu_msr_pr, + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_iu_sg_2 => int_pc_iu_sg_2(3), + pc_iu_func_sl_thold_2 => int_pc_iu_func_sl_thold_2(0), + pc_iu_cfg_sl_thold_2 => int_pc_iu_cfg_sl_thold_2, + clkoff_b => int_clkoff_b(0), + act_dis => int_act_dis(0), + tc_ac_ccflush_dc => tc_ac_ccflush_dc, + d_mode => int_d_mode(0), + delay_lclkr => int_delay_lclkr(0), + mpw1_b => int_mpw1_b(0), + mpw2_b => int_mpw2_b(0), + ccfg_scan_in => iuq_sp_ccfg_scan_in, + ccfg_scan_out => iuq_sp_ccfg_scan_out, + bcfg_scan_in => iuq_sp_bcfg_scan_in, + bcfg_scan_out => iuq_sp_bcfg_scan_out, + dcfg_scan_in => iuq_sp_dcfg_scan_in, + dcfg_scan_out => iuq_sp_dcfg_scan_out, + scan_in => iuq_sp_scan_in, + scan_out => iuq_sp_scan_out +); + +iuq_perf0 : entity work.iuq_perf +generic map(expand_type => expand_type) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_iu_func_sl_thold_2 => int_pc_iu_func_sl_thold_2(0), + pc_iu_sg_2 => int_pc_iu_sg_2(3), + clkoff_b => int_clkoff_b(0), + act_dis => int_act_dis(0), + tc_ac_ccflush_dc => tc_ac_ccflush_dc, + d_mode => int_d_mode(0), + delay_lclkr => int_delay_lclkr(0), + mpw1_b => int_mpw1_b(0), + mpw2_b => int_mpw2_b(0), + scan_in => iuq_pf_scan_in, + scan_out => iuq_pf_scan_out, + + xu_iu_msr_gs => xu_iu_msr_gs, + xu_iu_msr_pr => xu_iu_msr_pr, + + ic_perf_event_t0 => ic_perf_event_t0, + ic_perf_event_t1 => ic_perf_event_t1, + ic_perf_event_t2 => ic_perf_event_t2, + ic_perf_event_t3 => ic_perf_event_t3, + ic_perf_event => ic_perf_event, + + ib_perf_event_t0 => ib_perf_event_t0, + ib_perf_event_t1 => ib_perf_event_t1, + ib_perf_event_t2 => ib_perf_event_t2, + ib_perf_event_t3 => ib_perf_event_t3, + + fdep_perf_event_t0 => fdep_perf_event_t0, + fdep_perf_event_t1 => fdep_perf_event_t1, + fdep_perf_event_t2 => fdep_perf_event_t2, + fdep_perf_event_t3 => fdep_perf_event_t3, + + fiss_perf_event_t0 => fiss_perf_event_t0, + fiss_perf_event_t1 => fiss_perf_event_t1, + fiss_perf_event_t2 => fiss_perf_event_t2, + fiss_perf_event_t3 => fiss_perf_event_t3, + + pc_iu_event_mux_ctrls => pc_iu_event_mux_ctrls, + pc_iu_event_count_mode => pc_iu_event_count_mode, + pc_iu_event_bus_enable => pc_iu_event_bus_enable, + + iu_pc_event_data => iu_pc_event_data +); + +bht_dbg_data(0 to 7) <= r_addr(0 to 7); +bht_dbg_data(8 to 15) <= data_out0_int(0 to 1) & data_out1_int(0 to 1) & data_out2_int(0 to 1) & data_out3_int(0 to 1); +bht_dbg_data(16 to 23) <= w_addr(0 to 7); +bht_dbg_data(24 to 25) <= data_in(0 to 1); +bht_dbg_data(26 to 27) <= '0' & r_act; +bht_dbg_data(28 to 31) <= w_act(0 to 3); + + +iuq_dbg0 : entity work.iuq_dbg +generic map(expand_type => expand_type) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_iu_func_slp_sl_thold_2 => int_pc_iu_func_slp_sl_thold_2, + pc_iu_sg_2 => int_pc_iu_sg_2(3), + clkoff_b => int_clkoff_b(0), + act_dis => int_act_dis(0), + tc_ac_ccflush_dc => tc_ac_ccflush_dc, + d_mode => int_d_mode(0), + delay_lclkr => int_delay_lclkr(0), + mpw1_b => int_mpw1_b(0), + mpw2_b => int_mpw2_b(0), + scan_in => iuq_db_scan_in, + scan_out => iuq_db_scan_out, + fiss_dbg_data => fiss_dbg_data, + fdep_dbg_data => fdep_dbg_data, + ib_dbg_data => ib_dbg_data, + bp_dbg_data0 => bp_dbg_data0, + bp_dbg_data1 => bp_dbg_data1, + fu_iss_dbg_data => fu_iss_dbg_data, + axu_dbg_data_t0 => axu_dbg_data_t0, + axu_dbg_data_t1 => axu_dbg_data_t1, + axu_dbg_data_t2 => axu_dbg_data_t2, + axu_dbg_data_t3 => axu_dbg_data_t3, + bht_dbg_data => bht_dbg_data, + pc_iu_trace_bus_enable => pc_iu_trace_bus_enable, + pc_iu_debug_mux_ctrls => pc_iu_debug_mux_ctrls, + debug_data_in => debug_data_in, + trace_triggers_in => trace_triggers_in, + debug_data_out => debug_data_out, + trace_triggers_out => trace_triggers_out +); + + + + + +iuq_pf_scan_in <= func_scan_in(0); +iuq_sp_scan_in <= iuq_pf_scan_out; +iuq_bh_scan_in <= iuq_sp_scan_out; +func_scan_out(0) <= iuq_bh_scan_out and an_ac_scan_dis_dc_b; + +iuq_db_scan_in <= func_scan_in(1); +iuq_rm_scan_in <= iuq_db_scan_out; +func_scan_out(1) <= iuq_rm_scan_out and an_ac_scan_dis_dc_b; + +iuq_bh_time_scan_in <= time_scan_in; +time_scan_out <= iuq_bh_time_scan_out and an_ac_scan_dis_dc_b; + +iuq_sp_ccfg_scan_in <= ccfg_scan_in; +iuq_sp_bcfg_scan_in <= bcfg_scan_in; +iuq_sp_dcfg_scan_in <= dcfg_scan_in; +iuq_pv_gptr_scan_in <= gptr_scan_in; +iuq_bh_abst_scan_in <= abst_scan_in; +iuq_bh_repr_scan_in <= repr_scan_in; + +ccfg_scan_out <= iuq_sp_ccfg_scan_out and an_ac_scan_dis_dc_b; +bcfg_scan_out <= iuq_sp_bcfg_scan_out and an_ac_scan_dis_dc_b; +dcfg_scan_out <= iuq_sp_dcfg_scan_out and an_ac_scan_dis_dc_b; +gptr_scan_out <= iuq_pv_gptr_scan_out and an_ac_scan_dis_dc_b; +abst_scan_out <= iuq_bh_abst_scan_out and an_ac_scan_dis_dc_b; +repr_scan_out <= iuq_bh_repr_scan_out and an_ac_scan_dis_dc_b; + + + +end iuq_misc; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_perf.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_perf.vhdl new file mode 100644 index 0000000..d9c7f23 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_perf.vhdl @@ -0,0 +1,364 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + + +library ieee; +use ieee.std_logic_1164.all; + +library ibm,clib; +use ibm.std_ulogic_unsigned.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; + +library support; +use support.power_logic_pkg.all; + +library tri; +use tri.tri_latches_pkg.all; + +library work; +use work.iuq_pkg.all; + +entity iuq_perf is +generic(expand_type : integer := 2 ); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + pc_iu_func_sl_thold_2 : in std_ulogic; + pc_iu_sg_2 : in std_ulogic; + clkoff_b : in std_ulogic; + act_dis : in std_ulogic; + tc_ac_ccflush_dc : in std_ulogic; + d_mode : in std_ulogic; + delay_lclkr : in std_ulogic; + mpw1_b : in std_ulogic; + mpw2_b : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + xu_iu_msr_gs : in std_ulogic_vector(0 to 3); + xu_iu_msr_pr : in std_ulogic_vector(0 to 3); + + ic_perf_event_t0 : in std_ulogic_vector(0 to 6); + ic_perf_event_t1 : in std_ulogic_vector(0 to 6); + ic_perf_event_t2 : in std_ulogic_vector(0 to 6); + ic_perf_event_t3 : in std_ulogic_vector(0 to 6); + ic_perf_event : in std_ulogic_vector(0 to 1); + + ib_perf_event_t0 : in std_ulogic_vector(0 to 1); + ib_perf_event_t1 : in std_ulogic_vector(0 to 1); + ib_perf_event_t2 : in std_ulogic_vector(0 to 1); + ib_perf_event_t3 : in std_ulogic_vector(0 to 1); + + fdep_perf_event_t0 : in std_ulogic_vector(0 to 11); + fdep_perf_event_t1 : in std_ulogic_vector(0 to 11); + fdep_perf_event_t2 : in std_ulogic_vector(0 to 11); + fdep_perf_event_t3 : in std_ulogic_vector(0 to 11); + + fiss_perf_event_t0 : in std_ulogic_vector(0 to 7); + fiss_perf_event_t1 : in std_ulogic_vector(0 to 7); + fiss_perf_event_t2 : in std_ulogic_vector(0 to 7); + fiss_perf_event_t3 : in std_ulogic_vector(0 to 7); + + pc_iu_event_mux_ctrls : in std_ulogic_vector(0 to 47); + pc_iu_event_count_mode : in std_ulogic_vector(0 to 2); + pc_iu_event_bus_enable : in std_ulogic; + + iu_pc_event_data : out std_ulogic_vector(0 to 7) + +); + -- synopsys translate_off + + + -- synopsys translate_on +end iuq_perf; + + +architecture iuq_perf of iuq_perf is + +constant event_data_offset : natural := 0; +constant event_count_mode_offset: natural := event_data_offset + 8; +constant xu_iu_msr_gs_offset : natural := event_count_mode_offset + 3; +constant xu_iu_msr_pr_offset : natural := xu_iu_msr_gs_offset + 4; +constant event_bus_enable_offset: natural := xu_iu_msr_pr_offset + 4; +constant event_mux_ctrls_offset : natural := event_bus_enable_offset + 1; +constant scan_right : natural := event_mux_ctrls_offset + 48-1; + +signal event_data_d : std_ulogic_vector(0 to 7); +signal event_data_q : std_ulogic_vector(0 to 7); + +signal t0_events : std_ulogic_vector(0 to 31); +signal t1_events : std_ulogic_vector(0 to 31); +signal t2_events : std_ulogic_vector(0 to 31); +signal t3_events : std_ulogic_vector(0 to 31); + +signal xu_iu_msr_gs_d : std_ulogic_vector(0 to 3); +signal xu_iu_msr_gs_q : std_ulogic_vector(0 to 3); +signal xu_iu_msr_pr_d : std_ulogic_vector(0 to 3); +signal xu_iu_msr_pr_q : std_ulogic_vector(0 to 3); +signal event_count_mode_d : std_ulogic_vector(0 to 2); +signal event_count_mode_q : std_ulogic_vector(0 to 2); + +signal event_en : std_ulogic_vector(0 to 3); + +signal siv : std_ulogic_vector(0 to scan_right); +signal sov : std_ulogic_vector(0 to scan_right); + +signal tiup : std_ulogic; + +signal pc_iu_func_sl_thold_1 : std_ulogic; +signal pc_iu_func_sl_thold_0 : std_ulogic; +signal pc_iu_func_sl_thold_0_b : std_ulogic; +signal pc_iu_sg_1 : std_ulogic; +signal pc_iu_sg_0 : std_ulogic; +signal forcee : std_ulogic; + +signal event_bus_enable_d : std_ulogic; +signal event_bus_enable_q : std_ulogic; +signal event_mux_ctrls_d : std_ulogic_vector(0 to 47); +signal event_mux_ctrls_q : std_ulogic_vector(0 to 47); + +begin + + +tiup <= '1'; + + +xu_iu_msr_gs_d <= xu_iu_msr_gs; +xu_iu_msr_pr_d <= xu_iu_msr_pr; +event_count_mode_d <= pc_iu_event_count_mode; + + +event_en(0 to 3) <= gate( xu_iu_msr_pr_q(0 to 3) , event_count_mode_q(0)) or + gate(not xu_iu_msr_pr_q(0 to 3) and xu_iu_msr_gs_q(0 to 3), event_count_mode_q(1)) or + gate(not xu_iu_msr_pr_q(0 to 3) and not xu_iu_msr_gs_q(0 to 3), event_count_mode_q(2)); + + +t0_events(0 to 31) <= gate( + ic_perf_event_t0(0 to 6) & '0' & + ic_perf_event(0 to 1) & + ib_perf_event_t0(0 to 1) & + fdep_perf_event_t0(0 to 11) & + fiss_perf_event_t0(0 to 7), + event_en(0)); + +t1_events(0 to 31) <= gate( + ic_perf_event_t1(0 to 6) & '0' & + ic_perf_event(0 to 1) & + ib_perf_event_t1(0 to 1) & + fdep_perf_event_t1(0 to 11) & + fiss_perf_event_t1(0 to 7), + event_en(1)); + +t2_events(0 to 31) <= gate( + ic_perf_event_t2(0 to 6) & '0' & + ic_perf_event(0 to 1) & + ib_perf_event_t2(0 to 1) & + fdep_perf_event_t2(0 to 11) & + fiss_perf_event_t2(0 to 7), + event_en(2)); + +t3_events(0 to 31) <= gate( + ic_perf_event_t3(0 to 6) & '0' & + ic_perf_event(0 to 1) & + ib_perf_event_t3(0 to 1) & + fdep_perf_event_t3(0 to 11) & + fiss_perf_event_t3(0 to 7), + event_en(3)); + + +event_mux1: entity clib.c_event_mux + generic map ( events_in => 128 ) + port map(vd => vdd, + gd => gnd, + + t0_events => t0_events(0 to 31), + t1_events => t1_events(0 to 31), + t2_events => t2_events(0 to 31), + t3_events => t3_events(0 to 31), + + select_bits => event_mux_ctrls_q(0 to 47), + event_bits => event_data_d(0 to 7) +); + + +iu_pc_event_data <= event_data_q(0 to 7); + + +event_bus_enable_d <= pc_iu_event_bus_enable; +event_mux_ctrls_d <= pc_iu_event_mux_ctrls; + +event_enable_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(event_bus_enable_offset), + scout => sov(event_bus_enable_offset), + din => event_bus_enable_d, + dout => event_bus_enable_q); + +event_mux_ctrls_reg: tri_rlmreg_p + generic map (width => event_mux_ctrls_q'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => event_bus_enable_q, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(event_mux_ctrls_offset to event_mux_ctrls_offset + event_mux_ctrls_q'length-1), + scout => sov(event_mux_ctrls_offset to event_mux_ctrls_offset + event_mux_ctrls_q'length-1), + din => event_mux_ctrls_d, + dout => event_mux_ctrls_q); + +event_data_reg: tri_rlmreg_p + generic map (width => event_data_q'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => event_bus_enable_q, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(event_data_offset to event_data_offset + event_data_q'length-1), + scout => sov(event_data_offset to event_data_offset + event_data_q'length-1), + din => event_data_d, + dout => event_data_q); + +event_count_mode_reg: tri_rlmreg_p + generic map (width => event_count_mode_q'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => event_bus_enable_q, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(event_count_mode_offset to event_count_mode_offset + event_count_mode_q'length-1), + scout => sov(event_count_mode_offset to event_count_mode_offset + event_count_mode_q'length-1), + din => event_count_mode_d, + dout => event_count_mode_q); + +xu_iu_msr_gs_reg: tri_rlmreg_p + generic map (width => xu_iu_msr_gs_q'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => event_bus_enable_q, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_iu_msr_gs_offset to xu_iu_msr_gs_offset + xu_iu_msr_gs_q'length-1), + scout => sov(xu_iu_msr_gs_offset to xu_iu_msr_gs_offset + xu_iu_msr_gs_q'length-1), + din => xu_iu_msr_gs_d, + dout => xu_iu_msr_gs_q); + +xu_iu_msr_pr_reg: tri_rlmreg_p + generic map (width => xu_iu_msr_pr_q'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => event_bus_enable_q, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_iu_msr_pr_offset to xu_iu_msr_pr_offset + xu_iu_msr_pr_q'length-1), + scout => sov(xu_iu_msr_pr_offset to xu_iu_msr_pr_offset + xu_iu_msr_pr_q'length-1), + din => xu_iu_msr_pr_d, + dout => xu_iu_msr_pr_q); + + + +perv_2to1_reg: tri_plat + generic map (width => 2, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_iu_func_sl_thold_2, + din(1) => pc_iu_sg_2, + q(0) => pc_iu_func_sl_thold_1, + q(1) => pc_iu_sg_1); + +perv_1to0_reg: tri_plat + generic map (width => 2, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_iu_func_sl_thold_1, + din(1) => pc_iu_sg_1, + q(0) => pc_iu_func_sl_thold_0, + q(1) => pc_iu_sg_0); + +perv_lcbor: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_b, + thold => pc_iu_func_sl_thold_0, + sg => pc_iu_sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => pc_iu_func_sl_thold_0_b); + +siv(0 to scan_right) <= sov(1 to scan_right) & scan_in; +scan_out <= sov(0); + + +end iuq_perf; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_perv.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_perv.vhdl new file mode 100644 index 0000000..96e4c3d --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_perv.vhdl @@ -0,0 +1,350 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + + +library ieee; +use ieee.std_logic_1164.all; + +library ibm; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; + +library support; +use support.power_logic_pkg.all; + +library tri; +use tri.tri_latches_pkg.all; + +entity iuq_perv is +generic(expand_type : integer := 2 ); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + pc_iu_sg_3 : in std_ulogic_vector(0 to 3); + pc_iu_func_sl_thold_3 : in std_ulogic_vector(0 to 3); + pc_iu_func_slp_sl_thold_3 : in std_ulogic; + pc_iu_gptr_sl_thold_3 : in std_ulogic; + pc_iu_time_sl_thold_3 : in std_ulogic; + pc_iu_repr_sl_thold_3 : in std_ulogic; + pc_iu_abst_sl_thold_3 : in std_ulogic; + pc_iu_abst_slp_sl_thold_3 : in std_ulogic; + pc_iu_cfg_sl_thold_3 : in std_ulogic; + pc_iu_cfg_slp_sl_thold_3 : in std_ulogic; + pc_iu_regf_slp_sl_thold_3 : in std_ulogic; + pc_iu_ary_nsl_thold_3 : in std_ulogic; + pc_iu_ary_slp_nsl_thold_3 : in std_ulogic; + pc_iu_func_slp_nsl_thold_3 : in std_ulogic; + pc_iu_bolt_sl_thold_3 : in std_ulogic; + pc_iu_bo_enable_3 : in std_ulogic; + pc_iu_fce_3 : in std_ulogic; + tc_ac_ccflush_dc : in std_ulogic; + scan_diag_dc : in std_ulogic; + pc_iu_sg_2 : out std_ulogic_vector(0 to 3); + pc_iu_func_sl_thold_2 : out std_ulogic_vector(0 to 3); + pc_iu_func_slp_sl_thold_2 : out std_ulogic; + pc_iu_time_sl_thold_2 : out std_ulogic; + pc_iu_repr_sl_thold_2 : out std_ulogic; + pc_iu_abst_sl_thold_2 : out std_ulogic; + pc_iu_abst_slp_sl_thold_2 : out std_ulogic; + pc_iu_cfg_sl_thold_2 : out std_ulogic; + pc_iu_cfg_slp_sl_thold_2 : out std_ulogic; + pc_iu_regf_slp_sl_thold_2 : out std_ulogic; + pc_iu_ary_nsl_thold_2 : out std_ulogic; + pc_iu_ary_slp_nsl_thold_2 : out std_ulogic; + pc_iu_func_slp_nsl_thold_2 : out std_ulogic; + pc_iu_bolt_sl_thold_2 : out std_ulogic; + pc_iu_bo_enable_2 : out std_ulogic; + pc_iu_fce_2 : out std_ulogic; + clkoff_b : out std_ulogic_vector(0 to 2); + act_dis : out std_ulogic_vector(0 to 2); + d_mode : out std_ulogic_vector(0 to 2); + delay_lclkr : out std_ulogic_vector(0 to 14); + mpw1_b : out std_ulogic_vector(0 to 14); + mpw2_b : out std_ulogic_vector(0 to 2); + bht_g8t_clkoff_b : out std_ulogic; + bht_g8t_d_mode : out std_ulogic; + bht_g8t_delay_lclkr : out std_ulogic_vector(0 to 4); + bht_g8t_mpw1_b : out std_ulogic_vector(0 to 4); + bht_g8t_mpw2_b : out std_ulogic; + g8t_clkoff_b : out std_ulogic; + g8t_d_mode : out std_ulogic; + g8t_delay_lclkr : out std_ulogic_vector(0 to 4); + g8t_mpw1_b : out std_ulogic_vector(0 to 4); + g8t_mpw2_b : out std_ulogic; + g6t_clkoff_b : out std_ulogic; + g6t_d_mode : out std_ulogic; + g6t_delay_lclkr : out std_ulogic_vector(0 to 3); + g6t_mpw1_b : out std_ulogic_vector(0 to 4); + g6t_mpw2_b : out std_ulogic; + cam_clkoff_b : out std_ulogic; + cam_d_mode : out std_ulogic; + cam_delay_lclkr : out std_ulogic_vector(0 to 4); + cam_mpw1_b : out std_ulogic_vector(0 to 4); + cam_mpw2_b : out std_ulogic; + gptr_scan_in : in std_ulogic; + gptr_scan_out : out std_ulogic +); + +-- synopsys translate_off + + +-- synopsys translate_on + +end iuq_perv; +architecture iuq_perv of iuq_perv is + +signal pc_iu_gptr_sl_thold_2_int : std_ulogic; +signal pc_iu_time_sl_thold_2_int : std_ulogic; +signal pc_iu_sg_2_int : std_ulogic_vector(0 to 3); + +signal pc_iu_gptr_sl_thold_1 : std_ulogic; +signal pc_iu_sg_1 : std_ulogic; +signal pc_iu_gptr_sl_thold_0 : std_ulogic; +signal pc_iu_sg_0 : std_ulogic; + +signal int_g6t_delay_lclkr : std_ulogic_vector(0 to 4); +signal unused : std_ulogic; +-- synopsys translate_off +-- synopsys translate_on + + +signal gptr_siv : std_ulogic_vector(0 to 6); +signal gptr_sov : std_ulogic_vector(0 to 6); + +begin + +perv_3to2_reg: tri_plat + generic map (width => 23, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0 to 3) => pc_iu_func_sl_thold_3(0 to 3), + din(4) => pc_iu_gptr_sl_thold_3, + din(5) => pc_iu_time_sl_thold_3, + din(6) => pc_iu_repr_sl_thold_3, + din(7) => pc_iu_abst_sl_thold_3, + din(8) => pc_iu_ary_nsl_thold_3, + din(9 to 12) => pc_iu_sg_3(0 to 3), + din(13) => pc_iu_fce_3, + din(14) => pc_iu_cfg_slp_sl_thold_3, + din(15) => pc_iu_cfg_sl_thold_3, + din(16) => pc_iu_regf_slp_sl_thold_3, + din(17) => pc_iu_func_slp_sl_thold_3, + din(18) => pc_iu_ary_slp_nsl_thold_3, + din(19) => pc_iu_abst_slp_sl_thold_3, + din(20) => pc_iu_func_slp_nsl_thold_3, + din(21) => pc_iu_bolt_sl_thold_3, + din(22) => pc_iu_bo_enable_3, + q(0 to 3) => pc_iu_func_sl_thold_2(0 to 3), + q(4) => pc_iu_gptr_sl_thold_2_int, + q(5) => pc_iu_time_sl_thold_2_int, + q(6) => pc_iu_repr_sl_thold_2, + q(7) => pc_iu_abst_sl_thold_2, + q(8) => pc_iu_ary_nsl_thold_2, + q(9 to 12) => pc_iu_sg_2_int(0 to 3), + q(13) => pc_iu_fce_2, + q(14) => pc_iu_cfg_slp_sl_thold_2, + q(15) => pc_iu_cfg_sl_thold_2, + q(16) => pc_iu_regf_slp_sl_thold_2, + q(17) => pc_iu_func_slp_sl_thold_2, + q(18) => pc_iu_ary_slp_nsl_thold_2, + q(19) => pc_iu_abst_slp_sl_thold_2, + q(20) => pc_iu_func_slp_nsl_thold_2, + q(21) => pc_iu_bolt_sl_thold_2, + q(22) => pc_iu_bo_enable_2); + +pc_iu_time_sl_thold_2 <= pc_iu_time_sl_thold_2_int; +pc_iu_sg_2 <= pc_iu_sg_2_int; + +perv_2to1_reg: tri_plat + generic map (width => 2, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_iu_gptr_sl_thold_2_int, + din(1) => pc_iu_sg_2_int(0), + q(0) => pc_iu_gptr_sl_thold_1, + q(1) => pc_iu_sg_1); + +perv_1to0_reg: tri_plat + generic map (width => 2, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_iu_gptr_sl_thold_1, + din(1) => pc_iu_sg_1, + q(0) => pc_iu_gptr_sl_thold_0, + q(1) => pc_iu_sg_0); + + +perv_lcbcntl0: tri_lcbcntl_mac + generic map (expand_type => expand_type) + port map ( + vdd => vdd, + gnd => gnd, + sg => pc_iu_sg_0, + nclk => nclk, + scan_in => gptr_siv(0), + scan_diag_dc => scan_diag_dc, + thold => pc_iu_gptr_sl_thold_0, + clkoff_dc_b => clkoff_b(0), + delay_lclkr_dc => delay_lclkr(0 to 4), + act_dis_dc => open, + d_mode_dc => d_mode(0), + mpw1_dc_b => mpw1_b(0 to 4), + mpw2_dc_b => mpw2_b(0), + scan_out => gptr_sov(0)); + +perv_lcbcntl1: tri_lcbcntl_mac + generic map (expand_type => expand_type) + port map ( + vdd => vdd, + gnd => gnd, + sg => pc_iu_sg_0, + nclk => nclk, + scan_in => gptr_siv(1), + scan_diag_dc => scan_diag_dc, + thold => pc_iu_gptr_sl_thold_0, + clkoff_dc_b => clkoff_b(1), + delay_lclkr_dc => delay_lclkr(5 to 9), + act_dis_dc => open, + d_mode_dc => d_mode(1), + mpw1_dc_b => mpw1_b(5 to 9), + mpw2_dc_b => mpw2_b(1), + scan_out => gptr_sov(1)); + + +perv_lcbcntl2: tri_lcbcntl_mac + generic map (expand_type => expand_type) + port map ( + vdd => vdd, + gnd => gnd, + sg => pc_iu_sg_0, + nclk => nclk, + scan_in => gptr_siv(2), + scan_diag_dc => scan_diag_dc, + thold => pc_iu_gptr_sl_thold_0, + clkoff_dc_b => clkoff_b(2), + delay_lclkr_dc => delay_lclkr(10 to 14), + act_dis_dc => open, + d_mode_dc => d_mode(2), + mpw1_dc_b => mpw1_b(10 to 14), + mpw2_dc_b => mpw2_b(2), + scan_out => gptr_sov(2)); + + +perv_lcbcntl_g8t_bht: tri_lcbcntl_array_mac + generic map (expand_type => expand_type) + port map ( + vdd => vdd, + gnd => gnd, + sg => pc_iu_sg_0, + nclk => nclk, + scan_in => gptr_siv(3), + scan_diag_dc => scan_diag_dc, + thold => pc_iu_gptr_sl_thold_0, + clkoff_dc_b => bht_g8t_clkoff_b, + delay_lclkr_dc => bht_g8t_delay_lclkr(0 to 4), + act_dis_dc => open, + d_mode_dc => bht_g8t_d_mode, + mpw1_dc_b => bht_g8t_mpw1_b(0 to 4), + mpw2_dc_b => bht_g8t_mpw2_b, + scan_out => gptr_sov(3)); + +perv_lcbcntl_g8t: tri_lcbcntl_array_mac + generic map (expand_type => expand_type) + port map ( + vdd => vdd, + gnd => gnd, + sg => pc_iu_sg_0, + nclk => nclk, + scan_in => gptr_siv(4), + scan_diag_dc => scan_diag_dc, + thold => pc_iu_gptr_sl_thold_0, + clkoff_dc_b => g8t_clkoff_b, + delay_lclkr_dc => g8t_delay_lclkr(0 to 4), + act_dis_dc => open, + d_mode_dc => g8t_d_mode, + mpw1_dc_b => g8t_mpw1_b(0 to 4), + mpw2_dc_b => g8t_mpw2_b, + scan_out => gptr_sov(4)); + +perv_lcbcntl_g6t: tri_lcbcntl_array_mac + generic map (expand_type => expand_type) + port map ( + vdd => vdd, + gnd => gnd, + sg => pc_iu_sg_0, + nclk => nclk, + scan_in => gptr_siv(5), + scan_diag_dc => scan_diag_dc, + thold => pc_iu_gptr_sl_thold_0, + clkoff_dc_b => g6t_clkoff_b, + delay_lclkr_dc => int_g6t_delay_lclkr, + act_dis_dc => open, + d_mode_dc => g6t_d_mode, + mpw1_dc_b => g6t_mpw1_b(0 to 4), + mpw2_dc_b => g6t_mpw2_b, + scan_out => gptr_sov(5)); + +perv_lcbcntl_cam: tri_lcbcntl_array_mac + generic map (expand_type => expand_type) + port map ( + vdd => vdd, + gnd => gnd, + sg => pc_iu_sg_0, + nclk => nclk, + scan_in => gptr_siv(6), + scan_diag_dc => scan_diag_dc, + thold => pc_iu_gptr_sl_thold_0, + clkoff_dc_b => cam_clkoff_b, + delay_lclkr_dc => cam_delay_lclkr(0 to 4), + act_dis_dc => open, + d_mode_dc => cam_d_mode, + mpw1_dc_b => cam_mpw1_b(0 to 4), + mpw2_dc_b => cam_mpw2_b, + scan_out => gptr_sov(6)); + +g6t_delay_lclkr <= int_g6t_delay_lclkr(0 to 3); +unused <= int_g6t_delay_lclkr(4); + +act_dis(0 to 2) <= "000"; + + +gptr_siv(0 to 6) <= gptr_sov(1 to 6) & gptr_scan_in; +gptr_scan_out <= gptr_sov(0); + + +end iuq_perv; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_pkg.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_pkg.vhdl new file mode 100644 index 0000000..d35d6a3 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_pkg.vhdl @@ -0,0 +1,423 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee; +use ieee.std_logic_1164.all; + +package iuq_pkg is + subtype EFF_IFAR is std_ulogic_vector( 0 to 61); + subtype REAL_IFAR is std_ulogic_vector(22 to 61); + subtype EFF_DATA_ADD is std_ulogic_vector( 0 to 61); + subtype REAL_DATA_ADD is std_ulogic_vector(18 to 61); + + function ib(x : std_ulogic) return boolean; + + function barrel_left(a : std_ulogic_vector; s : std_ulogic_vector) return std_ulogic_vector; + function barrel_right(a : std_ulogic_vector; s : std_ulogic_vector) return std_ulogic_vector; + function pri_enc(a : std_ulogic_vector) return std_ulogic_vector; + function shift_left(a : std_ulogic_vector; s : std_ulogic_vector) return std_ulogic_vector; + function shift_right(a : std_ulogic_vector; s : std_ulogic_vector) return std_ulogic_vector; + function mask_left(a : std_ulogic_vector ) return std_ulogic_vector; + function mask_right(a : std_ulogic_vector ) return std_ulogic_vector; + + function shift_leftx1B(a : std_ulogic_vector; s: std_ulogic_vector) return std_ulogic_vector; + function shift_rightx1B(a : std_ulogic_vector; s: std_ulogic_vector) return std_ulogic_vector; + + procedure zeros(signal x : out std_ulogic); + procedure zeros(signal x : out std_ulogic_vector); + + function encode_4to2( a : std_ulogic_vector(0 to 3) ) return std_ulogic_vector; + function encode_8to3( a : std_ulogic_vector(0 to 7) ) return std_ulogic_vector; + function encode_16to4(a : std_ulogic_vector(0 to 15)) return std_ulogic_vector; + + type PPC_INSTR is record + vld : std_ulogic; + instr : std_ulogic_vector(0 to 31); + + ta : std_ulogic_vector(0 to 6); + ta_vld : std_ulogic; + ta_typ : std_ulogic_vector(0 to 1); + + s1 : std_ulogic_vector(0 to 6); + s1_vld : std_ulogic; + s1_typ : std_ulogic_vector(0 to 1); + + s2 : std_ulogic_vector(0 to 6); + s2_vld : std_ulogic; + s2_typ : std_ulogic_vector(0 to 1); + + s3 : std_ulogic_vector(0 to 6); + s3_vld : std_ulogic; + s3_typ : std_ulogic_vector(0 to 1); + + isFxuIssue : std_ulogic; + isVsuIssue : std_ulogic; + + EX4_exit : std_ulogic; + EX7_exit : std_ulogic; + + isLWARX : std_ulogic; + isSTWCX : std_ulogic; + is_vcrs : std_ulogic; + + pred_update : std_ulogic; + pred_taken_cnt : std_ulogic_vector(0 to 1); + + isINVALID_OP : std_ulogic; + isATTN : std_ulogic; + + UpdatesLR : std_ulogic; + UpdatesCR : std_ulogic; + UpdatesCTR : std_ulogic; + UsesLR : std_ulogic; + UsesCR : std_ulogic; + UsesCTR : std_ulogic; + + is_st : std_ulogic; + is_ld : std_ulogic; + ibat_err : std_ulogic; + + tid : std_ulogic_vector(0 to 3); + + ifar : EFF_IFAR; + bta : EFF_IFAR; + + end record; + + function TO_STLV ( x : PPC_INSTR ) return std_ulogic_vector; + function TO_PPCI ( x : std_ulogic_vector(0 to 97+2*EFF_IFAR'length) ) return PPC_INSTR; + + +end iuq_pkg; + +package body iuq_pkg is + + function ib(x : std_ulogic) return boolean + is + begin + return(x = '1'); + end ib; + + + function barrel_left(a : std_ulogic_vector; s : std_ulogic_vector) return std_ulogic_vector + is + variable result : std_ulogic_vector(a'left to a'right); + variable i : integer := 0; + begin + + result := a; + for i in s'left to s'right loop + if s(i) = '1' then + exit; + end if; + result := result(result'left+1 to result'right)&result(result'left); + end loop; + + return( result ); + end barrel_left; + + function barrel_right(a : std_ulogic_vector; s : std_ulogic_vector) return std_ulogic_vector + is + variable result : std_ulogic_vector(a'left to a'right); + begin + + result := a; + for i in a'left to a'right loop + if s(i) = '1' then + exit; + end if; + result := result(result'right) & result(result'left to result'right-1); + end loop; + + return( result ); + end barrel_right; + + + function pri_enc(a : std_ulogic_vector) return std_ulogic_vector + is + variable result : std_ulogic_vector(a'left to a'right); + begin + result := (others => '0'); + + for i in a'left to a'right loop + if a(i) = '1' then + result(i) := '1'; + exit; + end if; + end loop; + + return( result ); + end pri_enc; + + function shift_left(a : std_ulogic_vector; s : std_ulogic_vector) return std_ulogic_vector is + variable result : std_ulogic_vector(a'left to a'right); + begin + result := a; + for i in s'left to s'right loop + if s(i) = '1' then + exit; + end if; + result := result( result'left+1 to result'right)&'0'; + end loop; + return(result); + end shift_left; + + function shift_right(a : std_ulogic_vector; s : std_ulogic_vector) return std_ulogic_vector is + variable result : std_ulogic_vector(a'left to a'right); + begin + result := a; + for i in s'left to s'right loop + if s(i) = '1' then + exit; + end if; + result := '0'&result(result'left to result'right-1); + end loop; + return(result); + end shift_right; + + function mask_left(a : std_ulogic_vector ) return std_ulogic_vector is + variable result : std_ulogic_vector(a'left to a'right); + variable flag : integer := 0; + begin + for i in a'right downto a'left loop + if ((a(i) = '1') or (flag = 1)) then + result(i) := '1'; + flag := 1; + else + result(i) := a(i); + end if; + end loop; + return( result ); + end mask_left; + + function mask_right(a : std_ulogic_vector ) return std_ulogic_vector is + variable result : std_ulogic_vector(a'left to a'right); + variable flag : integer := 0; + begin + for i in a'left to a'right loop + if ((a(i) = '1') or (flag = 1)) then + result(i) := '1'; + flag := 1; + else + result(i) := a(i); + end if; + end loop; + return( result ); + end mask_right; + + function encode_4to2( a : std_ulogic_vector(0 to 3) ) return std_ulogic_vector is + variable result : std_ulogic_vector(0 to 1); + begin + case a is + when "1000" => result := "00"; + when "0100" => result := "01"; + when "0010" => result := "10"; + when "0001" => result := "11"; + when others => result := "00"; + end case; + return(result); + end encode_4to2; + + function encode_8to3( a : std_ulogic_vector(0 to 7) ) return std_ulogic_vector is + variable result : std_ulogic_vector(0 to 2); + begin + case a is + when "10000000" => result := "000"; + when "01000000" => result := "001"; + when "00100000" => result := "010"; + when "00010000" => result := "011"; + when "00001000" => result := "100"; + when "00000100" => result := "101"; + when "00000010" => result := "110"; + when "00000001" => result := "111"; + when others => result := "000"; + end case; + return(result); + end encode_8to3; + + function encode_16to4(a : std_ulogic_vector(0 to 15)) return std_ulogic_vector is + variable result : std_ulogic_vector(0 to 3); + begin + case a is + when "1000000000000000" => result := "0000"; + when "0100000000000000" => result := "0001"; + when "0010000000000000" => result := "0010"; + when "0001000000000000" => result := "0011"; + when "0000100000000000" => result := "0100"; + when "0000010000000000" => result := "0101"; + when "0000001000000000" => result := "0110"; + when "0000000100000000" => result := "0111"; + when "0000000010000000" => result := "1000"; + when "0000000001000000" => result := "1001"; + when "0000000000100000" => result := "1010"; + when "0000000000010000" => result := "1011"; + when "0000000000001000" => result := "1100"; + when "0000000000000100" => result := "1101"; + when "0000000000000010" => result := "1110"; + when "0000000000000001" => result := "1111"; + when others => result := "0000"; + end case; + return(result); + end encode_16to4; + + function shift_leftx1B(a : std_ulogic_vector; s: std_ulogic_vector) return std_ulogic_vector is + variable result : std_ulogic_vector(a'left to a'right); + begin + result := a; + for i in s'left to s'right loop + if s(i) = '1' then + exit; + end if; + result := result( result'left+8 to result'right)&"00000000"; + end loop; + return(result); + end shift_leftx1B; + + function shift_rightx1B(a : std_ulogic_vector; s: std_ulogic_vector) return std_ulogic_vector is + variable result : std_ulogic_vector(a'left to a'right); + begin + result := a; + for i in s'left to s'right loop + if s(i) = '1' then + exit; + end if; + result := "00000000"&result(result'left to result'right-8); + end loop; + return(result); + end shift_rightx1B; + + + + + function TO_STLV ( x : PPC_INSTR ) return std_ulogic_vector + is + variable result : std_ulogic_vector(0 to 97+2*EFF_IFAR'length); + begin + result := x.vld & + x.instr & + x.ta & + x.ta_vld & + x.ta_typ & + x.s1 & + x.s1_vld & + x.s1_typ & + x.s2 & + x.s2_vld & + x.s2_typ & + x.s3 & + x.s3_vld & + x.s3_typ & + x.isFxuIssue & + x.isVsuIssue & + x.EX4_exit & + x.EX7_exit & + x.isLWARX & + x.isSTWCX & + x.is_vcrs & + x.pred_update & + x.pred_taken_cnt & + x.isINVALID_OP & + x.isATTN & + x.UpdatesLR & + x.UpdatesCR & + x.UpdatesCTR & + x.UsesLR & + x.UsesCR & + x.UsesCTR & + x.is_st & + x.is_ld & + x.ibat_err & + x.tid & + x.ifar & + x.bta + ; + + return result; + end TO_STLV; + + function TO_PPCI ( x : std_ulogic_vector(0 to 97+2*EFF_IFAR'length) ) return PPC_INSTR is + variable result : PPC_INSTR; + begin + + result.vld := x(0); + result.instr := x(1 to 32); + result.ta := x(33 to 39); + result.ta_vld := x(40); + result.ta_typ := x(41 to 42); + result.s1 := x(43 to 49); + result.s1_vld := x(50); + result.s1_typ := x(51 to 52); + result.s2 := x(53 to 59); + result.s2_vld := x(60); + result.s2_typ := x(61 to 62); + result.s3 := x(63 to 69); + result.s3_vld := x(70); + result.s3_typ := x(71 to 72); + result.isFxuIssue := x(73); + result.isVsuIssue := x(74); + result.EX4_exit := x(75); + result.EX7_exit := x(76); + result.isLWARX := x(77); + result.isSTWCX := x(78); + result.is_vcrs := x(79); + result.pred_update := x(80); + result.pred_taken_cnt := x(81 to 82); + result.isINVALID_OP := x(83); + result.isATTN := x(84); + result.UpdatesLR := x(85); + result.UpdatesCR := x(86); + result.UpdatesCTR := x(87); + result.UsesLR := x(88); + result.UsesCR := x(89); + result.UsesCTR := x(90); + result.is_st := x(91); + result.is_ld := x(92); + result.ibat_err := x(93); + result.tid := x(94 to 97); + result.ifar := x(98 to 97+EFF_IFAR'length); + result.bta := x(98+EFF_IFAR'length to 97+2*EFF_IFAR'length); + + return result; + end TO_PPCI; + +procedure zeros(signal x : out std_ulogic) + is + begin + x <= '0'; + end zeros; + +procedure zeros(signal x : out std_ulogic_vector) + is + begin + for i in x'range loop + x(i) <= '0'; + end loop; + end zeros; + + +end iuq_pkg; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_ram.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_ram.vhdl new file mode 100644 index 0000000..70bfd11 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_ram.vhdl @@ -0,0 +1,254 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + + +library ieee; +use ieee.std_logic_1164.all; + +library ibm; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; + +library support; +use support.power_logic_pkg.all; + +library tri; +use tri.tri_latches_pkg.all; + +library work; +use work.iuq_pkg.all; + +entity iuq_ram is +generic(expand_type : integer := 2 ); +port( + pc_iu_ram_instr : in std_ulogic_vector(0 to 31); + pc_iu_ram_instr_ext : in std_ulogic_vector(0 to 3); + pc_iu_ram_force_cmplt : in std_ulogic; + + xu_iu_ram_issue : in std_ulogic_vector(0 to 3); + + rm_ib_iu4_val : out std_ulogic_vector(0 to 3); + rm_ib_iu4_force_ram : out std_ulogic; + rm_ib_iu4_instr : out std_ulogic_vector(0 to 35); + + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + pc_iu_sg_2 : in std_ulogic; + pc_iu_func_sl_thold_2 : in std_ulogic; + clkoff_b : in std_ulogic; + act_dis : in std_ulogic; + tc_ac_ccflush_dc : in std_ulogic; + d_mode : in std_ulogic; + delay_lclkr : in std_ulogic; + mpw1_b : in std_ulogic; + mpw2_b : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic + +); + +-- synopsys translate_off + + +-- synopsys translate_on + +end iuq_ram; +architecture iuq_ram of iuq_ram is + + + +constant ram_val_offset : natural := 0; +constant ram_iss_offset : natural := ram_val_offset + 4; +constant ram_instr_offset : natural := ram_iss_offset + 4; +constant ram_force_offset : natural := ram_instr_offset + 36; +constant scan_right : natural := ram_force_offset + 1-1; + + +signal tiup : std_ulogic; + +signal ram_valid : std_ulogic; + +signal ram_iss_d : std_ulogic_vector(0 to 3); +signal ram_iss_q : std_ulogic_vector(0 to 3); +signal ram_val_d : std_ulogic_vector(0 to 3); +signal ram_val_q : std_ulogic_vector(0 to 3); +signal ram_instr_d : std_ulogic_vector(0 to 35); +signal ram_instr_q : std_ulogic_vector(0 to 35); +signal ram_force_d : std_ulogic; +signal ram_force_q : std_ulogic; + +signal pc_iu_func_sl_thold_1 : std_ulogic; +signal pc_iu_func_sl_thold_0 : std_ulogic; +signal pc_iu_func_sl_thold_0_b : std_ulogic; +signal pc_iu_sg_1 : std_ulogic; +signal pc_iu_sg_0 : std_ulogic; +signal forcee : std_ulogic; + +signal siv : std_ulogic_vector(0 to scan_right); +signal sov : std_ulogic_vector(0 to scan_right); + +begin + +tiup <= '1'; + + + + + +ram_iss_d <= xu_iu_ram_issue; +ram_val_d <= ram_iss_q and not ram_iss_d; +ram_valid <= or_reduce(ram_iss_q); + + +ram_instr_d <= pc_iu_ram_instr & pc_iu_ram_instr_ext; +ram_force_d <= pc_iu_ram_force_cmplt; + + +rm_ib_iu4_val <= ram_val_q; +rm_ib_iu4_instr <= ram_instr_q; +rm_ib_iu4_force_ram <= ram_force_q; + + + +ram_iss_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(ram_iss_offset to ram_iss_offset+3), + scout => sov(ram_iss_offset to ram_iss_offset+3), + din => ram_iss_d(0 to 3), + dout => ram_iss_q(0 to 3)); + +ram_val_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(ram_val_offset to ram_val_offset+3), + scout => sov(ram_val_offset to ram_val_offset+3), + din => ram_val_d(0 to 3), + dout => ram_val_q(0 to 3)); + + +ram_instr_reg: tri_rlmreg_p + generic map (width => 36, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ram_valid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(ram_instr_offset to ram_instr_offset+35), + scout => sov(ram_instr_offset to ram_instr_offset+35), + din => ram_instr_d(0 to 35), + dout => ram_instr_q(0 to 35)); + +ram_force_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ram_valid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(ram_force_offset), + scout => sov(ram_force_offset), + din => ram_force_d, + dout => ram_force_q); + + + +perv_2to1_reg: tri_plat + generic map (width => 2, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_iu_func_sl_thold_2, + din(1) => pc_iu_sg_2, + q(0) => pc_iu_func_sl_thold_1, + q(1) => pc_iu_sg_1); + +perv_1to0_reg: tri_plat + generic map (width => 2, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_iu_func_sl_thold_1, + din(1) => pc_iu_sg_1, + q(0) => pc_iu_func_sl_thold_0, + q(1) => pc_iu_sg_0); + +perv_lcbor: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_b, + thold => pc_iu_func_sl_thold_0, + sg => pc_iu_sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => pc_iu_func_sl_thold_0_b); + + + +siv(0 to scan_right) <= scan_in & sov(0 to scan_right-1); +scan_out <= sov(scan_right); + + +end iuq_ram; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_rp.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_rp.vhdl new file mode 100644 index 0000000..07aec1c --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_rp.vhdl @@ -0,0 +1,980 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; +use ieee.std_logic_1164.all; + +library ibm; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; + +library support; +use support.power_logic_pkg.all; + +library tri; +use tri.tri_latches_pkg.all; + +entity iuq_rp is +generic(expand_type : integer := 2 ); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + scan_diag_dc : in std_ulogic; + scan_dis_dc_b : in std_ulogic; + an_ac_ccflush_dc : in std_ulogic; + rtim_sl_thold_7 : in std_ulogic; + func_sl_thold_7 : in std_ulogic; + func_nsl_thold_7 : in std_ulogic; + ary_nsl_thold_7 : in std_ulogic; + sg_7 : in std_ulogic; + fce_7 : in std_ulogic; + rtim_sl_thold_6 : out std_ulogic; + func_sl_thold_6 : out std_ulogic; + func_nsl_thold_6 : out std_ulogic; + ary_nsl_thold_6 : out std_ulogic; + sg_6 : out std_ulogic; + fce_6 : out std_ulogic; + an_ac_scom_dch : in std_ulogic; + an_ac_scom_cch : in std_ulogic; + an_ac_checkstop : in std_ulogic; + an_ac_debug_stop : in std_ulogic; + an_ac_pm_thread_stop : in std_ulogic_vector(0 to 3); + an_ac_reset_1_complete : in std_ulogic; + an_ac_reset_2_complete : in std_ulogic; + an_ac_reset_3_complete : in std_ulogic; + an_ac_reset_wd_complete : in std_ulogic; + an_ac_abist_start_test : in std_ulogic; + ac_rp_trace_to_perfcntr : in std_ulogic_vector(0 to 7); + rp_pc_scom_dch_q : out std_ulogic; + rp_pc_scom_cch_q : out std_ulogic; + rp_pc_checkstop_q : out std_ulogic; + rp_pc_debug_stop_q : out std_ulogic; + rp_pc_pm_thread_stop_q : out std_ulogic_vector(0 to 3); + rp_pc_reset_1_complete_q : out std_ulogic; + rp_pc_reset_2_complete_q : out std_ulogic; + rp_pc_reset_3_complete_q : out std_ulogic; + rp_pc_reset_wd_complete_q : out std_ulogic; + rp_pc_abist_start_test_q : out std_ulogic; + rp_pc_trace_to_perfcntr_q : out std_ulogic_vector(0 to 7); + pc_rp_scom_dch : in std_ulogic; + pc_rp_scom_cch : in std_ulogic; + pc_rp_special_attn : in std_ulogic_vector(0 to 3); + pc_rp_checkstop : in std_ulogic_vector(0 to 2); + pc_rp_local_checkstop : in std_ulogic_vector(0 to 2); + pc_rp_recov_err : in std_ulogic_vector(0 to 2); + pc_rp_trace_error : in std_ulogic; + pc_rp_event_bus_enable : in std_ulogic; + pc_rp_event_bus : in std_ulogic_vector(0 to 7); + pc_rp_fu_bypass_events : in std_ulogic_vector(0 to 7); + pc_rp_iu_bypass_events : in std_ulogic_vector(0 to 7); + pc_rp_mm_bypass_events : in std_ulogic_vector(0 to 7); + pc_rp_lsu_bypass_events : in std_ulogic_vector(0 to 7); + pc_rp_pm_thread_running : in std_ulogic_vector(0 to 3); + pc_rp_power_managed : in std_ulogic; + pc_rp_rvwinkle_mode : in std_ulogic; + ac_an_scom_dch_q : out std_ulogic; + ac_an_scom_cch_q : out std_ulogic; + ac_an_special_attn_q : out std_ulogic_vector(0 to 3); + ac_an_checkstop_q : out std_ulogic_vector(0 to 2); + ac_an_local_checkstop_q : out std_ulogic_vector(0 to 2); + ac_an_recov_err_q : out std_ulogic_vector(0 to 2); + ac_an_trace_error_q : out std_ulogic; + rp_mm_event_bus_enable_q : out std_ulogic; + ac_an_event_bus_q : out std_ulogic_vector(0 to 7); + ac_an_fu_bypass_events_q : out std_ulogic_vector(0 to 7); + ac_an_iu_bypass_events_q : out std_ulogic_vector(0 to 7); + ac_an_mm_bypass_events_q : out std_ulogic_vector(0 to 7); + ac_an_lsu_bypass_events_q : out std_ulogic_vector(0 to 7); + ac_an_pm_thread_running_q : out std_ulogic_vector(0 to 3); + ac_an_power_managed_q : out std_ulogic; + ac_an_rvwinkle_mode_q : out std_ulogic; + + + + pc_func_scan_in : in std_ulogic_vector(0 to 1); + pc_func_scan_in_q : out std_ulogic_vector(0 to 1); + pc_func_scan_out : in std_ulogic; + pc_func_scan_out_q : out std_ulogic; + pc_bcfg_scan_in : in std_ulogic; + pc_bcfg_scan_in_q : out std_ulogic; + pc_dcfg_scan_in : in std_ulogic; + pc_dcfg_scan_in_q : out std_ulogic; + pc_bcfg_scan_out : in std_ulogic; + pc_bcfg_scan_out_q : out std_ulogic; + pc_ccfg_scan_out : in std_ulogic; + pc_ccfg_scan_out_q : out std_ulogic; + pc_dcfg_scan_out : in std_ulogic; + pc_dcfg_scan_out_q : out std_ulogic; + fu_abst_scan_in : in std_ulogic; + fu_abst_scan_in_q : out std_ulogic; + fu_abst_scan_out : in std_ulogic; + fu_abst_scan_out_q : out std_ulogic; + fu_ccfg_scan_out : in std_ulogic; + fu_ccfg_scan_out_q : out std_ulogic; + fu_bcfg_scan_out : in std_ulogic; + fu_bcfg_scan_out_q : out std_ulogic; + fu_dcfg_scan_out : in std_ulogic; + fu_dcfg_scan_out_q : out std_ulogic; + fu_func_scan_in : in std_ulogic_vector(0 to 3); + fu_func_scan_in_q : out std_ulogic_vector(0 to 3); + fu_func_scan_out : in std_ulogic_vector(0 to 3); + fu_func_scan_out_q : out std_ulogic_vector(0 to 3); + bx_abst_scan_in : in std_ulogic; + bx_abst_scan_in_q : out std_ulogic; + bx_abst_scan_out : in std_ulogic; + bx_abst_scan_out_q : out std_ulogic; + bx_func_scan_in : in std_ulogic_vector(0 to 1); + bx_func_scan_in_q : out std_ulogic_vector(0 to 1); + bx_func_scan_out : in std_ulogic_vector(0 to 1); + bx_func_scan_out_q : out std_ulogic_vector(0 to 1); + iu_func_scan_in : in std_ulogic_vector(0 to 8); + iu_func_scan_in_q : out std_ulogic_vector(0 to 8); + iu_func_scan_out : in std_ulogic_vector(0 to 9); + iu_func_scan_out_q : out std_ulogic_vector(0 to 9); + iu_bcfg_scan_in : in std_ulogic; + iu_bcfg_scan_in_q : out std_ulogic; + spare_func_scan_in : in std_ulogic_vector(0 to 3); + spare_func_scan_in_q : out std_ulogic_vector(0 to 3); + spare_func_scan_out : in std_ulogic_vector(0 to 3); + spare_func_scan_out_q : out std_ulogic_vector(0 to 3); + + bg_an_ac_func_scan_sn : in std_ulogic_vector(60 to 69); + bg_an_ac_abst_scan_sn : in std_ulogic_vector(10 to 11); + bg_an_ac_func_scan_sn_q : out std_ulogic_vector(60 to 69); + bg_an_ac_abst_scan_sn_q : out std_ulogic_vector(10 to 11); + + bg_ac_an_func_scan_ns : in std_ulogic_vector(60 to 69); + bg_ac_an_abst_scan_ns : in std_ulogic_vector(10 to 11); + bg_ac_an_func_scan_ns_q : out std_ulogic_vector(60 to 69); + bg_ac_an_abst_scan_ns_q : out std_ulogic_vector(10 to 11); + + bg_pc_l1p_abist_di_0 : in std_ulogic_vector(0 to 3); + bg_pc_l1p_abist_g8t1p_renb_0 : in std_ulogic; + bg_pc_l1p_abist_g8t_bw_0 : in std_ulogic; + bg_pc_l1p_abist_g8t_bw_1 : in std_ulogic; + bg_pc_l1p_abist_g8t_dcomp : in std_ulogic_vector(0 to 3); + bg_pc_l1p_abist_g8t_wenb : in std_ulogic; + bg_pc_l1p_abist_raddr_0 : in std_ulogic_vector(0 to 9); + bg_pc_l1p_abist_waddr_0 : in std_ulogic_vector(0 to 9); + bg_pc_l1p_abist_wl128_comp_ena : in std_ulogic; + bg_pc_l1p_abist_wl32_comp_ena : in std_ulogic; + bg_pc_l1p_abist_di_0_q : out std_ulogic_vector(0 to 3); + bg_pc_l1p_abist_g8t1p_renb_0_q : out std_ulogic; + bg_pc_l1p_abist_g8t_bw_0_q : out std_ulogic; + bg_pc_l1p_abist_g8t_bw_1_q : out std_ulogic; + bg_pc_l1p_abist_g8t_dcomp_q: out std_ulogic_vector(0 to 3); + bg_pc_l1p_abist_g8t_wenb_q : out std_ulogic; + bg_pc_l1p_abist_raddr_0_q : out std_ulogic_vector(0 to 9); + bg_pc_l1p_abist_waddr_0_q : out std_ulogic_vector(0 to 9); + bg_pc_l1p_abist_wl128_comp_ena_q : out std_ulogic; + bg_pc_l1p_abist_wl32_comp_ena_q : out std_ulogic; + + bg_pc_l1p_gptr_sl_thold_3 : in std_ulogic; + bg_pc_l1p_time_sl_thold_3 : in std_ulogic; + bg_pc_l1p_repr_sl_thold_3 : in std_ulogic; + bg_pc_l1p_abst_sl_thold_3 : in std_ulogic; + bg_pc_l1p_func_sl_thold_3 : in std_ulogic_vector(0 to 1); + bg_pc_l1p_func_slp_sl_thold_3 : in std_ulogic; + bg_pc_l1p_bolt_sl_thold_3 : in std_ulogic; + bg_pc_l1p_ary_nsl_thold_3 : in std_ulogic; + bg_pc_l1p_sg_3 : in std_ulogic_vector(0 to 1); + bg_pc_l1p_fce_3 : in std_ulogic; + bg_pc_l1p_bo_enable_3 : in std_ulogic; + bg_pc_l1p_gptr_sl_thold_2 : out std_ulogic; + bg_pc_l1p_time_sl_thold_2 : out std_ulogic; + bg_pc_l1p_repr_sl_thold_2 : out std_ulogic; + bg_pc_l1p_abst_sl_thold_2 : out std_ulogic; + bg_pc_l1p_func_sl_thold_2 : out std_ulogic_vector(0 to 1); + bg_pc_l1p_func_slp_sl_thold_2 : out std_ulogic; + bg_pc_l1p_bolt_sl_thold_2 : out std_ulogic; + bg_pc_l1p_ary_nsl_thold_2 : out std_ulogic; + bg_pc_l1p_sg_2 : out std_ulogic_vector(0 to 1); + bg_pc_l1p_fce_2 : out std_ulogic; + bg_pc_l1p_bo_enable_2 : out std_ulogic; + + pc_mm_bo_enable_4 : in std_ulogic; + pc_iu_bo_enable_4 : in std_ulogic; + pc_mm_bo_enable_3 : out std_ulogic; + pc_iu_bo_enable_3 : out std_ulogic; + pc_iu_gptr_sl_thold_4 : in std_ulogic; + pc_iu_time_sl_thold_4 : in std_ulogic; + pc_iu_repr_sl_thold_4 : in std_ulogic; + pc_iu_abst_sl_thold_4 : in std_ulogic; + pc_iu_abst_slp_sl_thold_4 : in std_ulogic; + pc_iu_bolt_sl_thold_4 : in std_ulogic; + pc_iu_regf_slp_sl_thold_4 : in std_ulogic; + pc_iu_func_sl_thold_4 : in std_ulogic; + pc_iu_func_slp_sl_thold_4 : in std_ulogic; + pc_iu_cfg_sl_thold_4 : in std_ulogic; + pc_iu_cfg_slp_sl_thold_4 : in std_ulogic; + pc_iu_func_nsl_thold_4 : in std_ulogic; + pc_iu_func_slp_nsl_thold_4 : in std_ulogic; + pc_iu_ary_nsl_thold_4 : in std_ulogic; + pc_iu_ary_slp_nsl_thold_4 : in std_ulogic; + pc_iu_sg_4 : in std_ulogic; + pc_iu_fce_4 : in std_ulogic; + pc_iu_gptr_sl_thold_3 : out std_ulogic; + pc_iu_time_sl_thold_3 : out std_ulogic; + pc_iu_repr_sl_thold_3 : out std_ulogic; + pc_iu_abst_sl_thold_3 : out std_ulogic; + pc_iu_abst_slp_sl_thold_3 : out std_ulogic; + pc_iu_bolt_sl_thold_3 : out std_ulogic; + pc_iu_regf_slp_sl_thold_3 : out std_ulogic; + pc_iu_func_sl_thold_3 : out std_ulogic_vector(0 to 3); + pc_iu_func_slp_sl_thold_3 : out std_ulogic; + pc_iu_cfg_sl_thold_3 : out std_ulogic; + pc_iu_cfg_slp_sl_thold_3 : out std_ulogic; + pc_iu_func_slp_nsl_thold_3 : out std_ulogic; + pc_iu_ary_nsl_thold_3 : out std_ulogic; + pc_iu_ary_slp_nsl_thold_3 : out std_ulogic; + pc_iu_sg_3 : out std_ulogic_vector(0 to 3); + pc_iu_fce_3 : out std_ulogic; + pc_mm_gptr_sl_thold_3 : out std_ulogic; + pc_mm_time_sl_thold_3 : out std_ulogic; + pc_mm_repr_sl_thold_3 : out std_ulogic; + pc_mm_abst_sl_thold_3 : out std_ulogic; + pc_mm_abst_slp_sl_thold_3 : out std_ulogic; + pc_mm_bolt_sl_thold_3 : out std_ulogic; + pc_mm_func_sl_thold_3 : out std_ulogic_vector(0 to 1); + pc_mm_func_slp_sl_thold_3 : out std_ulogic_vector(0 to 1); + pc_mm_cfg_sl_thold_3 : out std_ulogic; + pc_mm_cfg_slp_sl_thold_3 : out std_ulogic; + pc_mm_func_nsl_thold_3 : out std_ulogic; + pc_mm_func_slp_nsl_thold_3 : out std_ulogic; + pc_mm_ary_nsl_thold_3 : out std_ulogic; + pc_mm_ary_slp_nsl_thold_3 : out std_ulogic; + pc_mm_sg_3 : out std_ulogic_vector(0 to 1); + pc_mm_fce_3 : out std_ulogic; + + sg_2 : in std_ulogic; + func_sl_thold_2 : in std_ulogic; + func_slp_sl_thold_2 : in std_ulogic; + abst_sl_thold_2 : in std_ulogic; + abst_scan_in : in std_ulogic; + func_scan_in : in std_ulogic; + gptr_scan_in : in std_ulogic; + abst_scan_out : out std_ulogic; + func_scan_out : out std_ulogic; + gptr_scan_out : out std_ulogic +); + +-- synopsys translate_off + + +-- synopsys translate_on + +end iuq_rp; +architecture iuq_rp of iuq_rp is + +constant abst_size : positive := 1; +constant abst_bg_size : positive := 34; +constant abst_offset : natural := 0; +constant abst_bg_offset : natural := abst_offset + abst_size; +constant abst_right : natural := abst_bg_offset + abst_bg_size - 1; + +constant perf_size : positive := 40; +constant func1_size : positive := 12; +constant func2_size : positive := 31; +constant perf_offset : natural := 0; +constant func1_offset : natural := perf_offset + perf_size; +constant func2_offset : natural := func1_offset + func1_size; +constant func_right : natural := func2_offset + func2_size - 1; + +signal abst_siv, abst_sov : std_ulogic_vector(0 to abst_right); +signal func_siv, func_sov : std_ulogic_vector(0 to func_right); + +signal slat_force : std_ulogic; +signal func_slat_thold_b : std_ulogic; +signal func_slat_d2clk : std_ulogic; +signal func_slat_lclk : clk_logic; +signal abst_slat_thold_b : std_ulogic; +signal abst_slat_d2clk : std_ulogic; +signal abst_slat_lclk : clk_logic; +signal cfg_slat_thold_b : std_ulogic; +signal cfg_slat_d2clk : std_ulogic; +signal cfg_slat_lclk : clk_logic; + +signal gptr_sl_thold_3_int : std_ulogic; +signal cfg_sl_thold_3_int : std_ulogic; +signal gptr_sl_thold_2 : std_ulogic; +signal cfg_sl_thold_2 : std_ulogic; +signal sg_1 : std_ulogic; +signal func_sl_thold_1 : std_ulogic; +signal func_slp_sl_thold_1 : std_ulogic; +signal gptr_sl_thold_1 : std_ulogic; +signal abst_sl_thold_1 : std_ulogic; +signal cfg_sl_thold_1 : std_ulogic; +signal sg_0 : std_ulogic; +signal func_sl_thold_0 : std_ulogic; +signal func_sl_thold_0_b : std_ulogic; +signal force_func : std_ulogic; +signal func_slp_sl_thold_0 : std_ulogic; +signal func_slp_sl_thold_0_b : std_ulogic; +signal force_func_slp : std_ulogic; +signal gptr_sl_thold_0 : std_ulogic; +signal abst_sl_thold_0 : std_ulogic; +signal abst_sl_thold_0_b : std_ulogic; +signal force_abst : std_ulogic; +signal cfg_sl_thold_0 : std_ulogic; + +signal clkoff_b : std_ulogic; +signal act_dis : std_ulogic; +signal d_mode : std_ulogic; +signal delay_lclkr : std_ulogic_vector(0 to 4); +signal mpw1_b : std_ulogic_vector(0 to 4); +signal mpw2_b : std_ulogic; + +signal event_bus_enable_int : std_ulogic; +signal unused : std_ulogic; + +-- synopsys translate_off +-- synopsys translate_on + +begin + +rp_mm_event_bus_enable_q <= event_bus_enable_int; +pc_iu_gptr_sl_thold_3 <= gptr_sl_thold_3_int; +pc_iu_cfg_sl_thold_3 <= cfg_sl_thold_3_int; + + + +perv_3to2_reg: tri_plat + generic map (width => 2, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => an_ac_ccflush_dc, + din(0) => gptr_sl_thold_3_int, + din(1) => cfg_sl_thold_3_int, + q(0) => gptr_sl_thold_2, + q(1) => cfg_sl_thold_2); + +perv_2to1_reg: tri_plat + generic map (width => 6, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => an_ac_ccflush_dc, + din(0) => func_sl_thold_2, + din(1) => func_slp_sl_thold_2, + din(2) => gptr_sl_thold_2, + din(3) => abst_sl_thold_2, + din(4) => cfg_sl_thold_2, + din(5) => sg_2, + q(0) => func_sl_thold_1, + q(1) => func_slp_sl_thold_1, + q(2) => gptr_sl_thold_1, + q(3) => abst_sl_thold_1, + q(4) => cfg_sl_thold_1, + q(5) => sg_1); + +perv_1to0_reg: tri_plat + generic map (width => 6, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => an_ac_ccflush_dc, + din(0) => func_sl_thold_1, + din(1) => func_slp_sl_thold_1, + din(2) => gptr_sl_thold_1, + din(3) => abst_sl_thold_1, + din(4) => cfg_sl_thold_1, + din(5) => sg_1, + q(0) => func_sl_thold_0, + q(1) => func_slp_sl_thold_0, + q(2) => gptr_sl_thold_0, + q(3) => abst_sl_thold_0, + q(4) => cfg_sl_thold_0, + q(5) => sg_0); + + +perv_lcbcntl: tri_lcbcntl_mac + generic map (expand_type => expand_type) + port map ( + vdd => vdd, + gnd => gnd, + sg => sg_0, + nclk => nclk, + scan_in => gptr_scan_in, + scan_diag_dc => scan_diag_dc, + thold => gptr_sl_thold_0, + clkoff_dc_b => clkoff_b, + delay_lclkr_dc => delay_lclkr(0 to 4), + act_dis_dc => act_dis, + d_mode_dc => d_mode, + mpw1_dc_b => mpw1_b(0 to 4), + mpw2_dc_b => mpw2_b, + scan_out => gptr_scan_out); + +unused <= or_reduce(delay_lclkr(1 to 4) & + d_mode & + mpw1_b(1 to 4) ); + +abst_lcbor: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_b, + thold => abst_sl_thold_0, + sg => sg_0, + act_dis => act_dis, + forcee => force_abst, + thold_b => abst_sl_thold_0_b); + +func_lcbor: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_b, + thold => func_sl_thold_0, + sg => sg_0, + act_dis => act_dis, + forcee => force_func, + thold_b => func_sl_thold_0_b); + +func_slp_lcbor: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_b, + thold => func_slp_sl_thold_0, + sg => sg_0, + act_dis => act_dis, + forcee => force_func_slp, + thold_b => func_slp_sl_thold_0_b); + + +slat_force <= sg_0; +func_slat_thold_b <= NOT func_sl_thold_0; +abst_slat_thold_b <= NOT abst_sl_thold_0; +cfg_slat_thold_b <= NOT cfg_sl_thold_0; + +lcbs_func: tri_lcbs + generic map (expand_type => expand_type ) + port map ( + vd => vdd, + gd => gnd, + delay_lclkr => delay_lclkr(0), + nclk => nclk, + forcee => slat_force, + thold_b => func_slat_thold_b, + dclk => func_slat_d2clk, + lclk => func_slat_lclk ); + +lcbs_abst: tri_lcbs + generic map (expand_type => expand_type ) + port map ( + vd => vdd, + gd => gnd, + delay_lclkr => delay_lclkr(0), + nclk => nclk, + forcee => slat_force, + thold_b => abst_slat_thold_b, + dclk => abst_slat_d2clk, + lclk => abst_slat_lclk ); + +lcbs_cfg: tri_lcbs + generic map (expand_type => expand_type ) + port map ( + vd => vdd, + gd => gnd, + delay_lclkr => delay_lclkr(0), + nclk => nclk, + forcee => slat_force, + thold_b => cfg_slat_thold_b, + dclk => cfg_slat_d2clk, + lclk => cfg_slat_lclk ); + +pcq_lvl7to6: tri_plat + generic map( width => 6, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => an_ac_ccflush_dc, + din( 0) => rtim_sl_thold_7, + din( 1) => func_sl_thold_7, + din( 2) => func_nsl_thold_7, + din( 3) => ary_nsl_thold_7, + din( 4) => sg_7, + din( 5) => fce_7, + q( 0) => rtim_sl_thold_6, + q( 1) => func_sl_thold_6, + q( 2) => func_nsl_thold_6, + q( 3) => ary_nsl_thold_6, + q( 4) => sg_6, + q( 5) => fce_6 + ); + + +bg_lvl3to2: tri_plat + generic map( width => 13, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => an_ac_ccflush_dc, + din( 0) => bg_pc_l1p_gptr_sl_thold_3, + din( 1) => bg_pc_l1p_time_sl_thold_3, + din( 2) => bg_pc_l1p_repr_sl_thold_3, + din( 3) => bg_pc_l1p_abst_sl_thold_3, + din( 4) => bg_pc_l1p_func_sl_thold_3(0), + din( 5) => bg_pc_l1p_func_sl_thold_3(1), + din( 6) => bg_pc_l1p_func_slp_sl_thold_3, + din( 7) => bg_pc_l1p_bolt_sl_thold_3, + din( 8) => bg_pc_l1p_ary_nsl_thold_3, + din( 9) => bg_pc_l1p_sg_3(0), + din(10) => bg_pc_l1p_sg_3(1), + din(11) => bg_pc_l1p_fce_3, + din(12) => bg_pc_l1p_bo_enable_3, + q( 0) => bg_pc_l1p_gptr_sl_thold_2, + q( 1) => bg_pc_l1p_time_sl_thold_2, + q( 2) => bg_pc_l1p_repr_sl_thold_2, + q( 3) => bg_pc_l1p_abst_sl_thold_2, + q( 4) => bg_pc_l1p_func_sl_thold_2(0), + q( 5) => bg_pc_l1p_func_sl_thold_2(1), + q( 6) => bg_pc_l1p_func_slp_sl_thold_2, + q( 7) => bg_pc_l1p_bolt_sl_thold_2, + q( 8) => bg_pc_l1p_ary_nsl_thold_2, + q( 9) => bg_pc_l1p_sg_2(0), + q(10) => bg_pc_l1p_sg_2(1), + q(11) => bg_pc_l1p_fce_2, + q(12) => bg_pc_l1p_bo_enable_2 + ); +fu_abst_stg: tri_slat_scan + generic map (width => 2, init => "00", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => abst_slat_d2clk, + lclk => abst_slat_lclk, + scan_in(0) => fu_abst_scan_in, + scan_in(1) => fu_abst_scan_out, + scan_out(0) => fu_abst_scan_in_q, + scan_out(1) => fu_abst_scan_out_q ); + +bx_abst_stg: tri_slat_scan + generic map (width => 2, init => "00", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => abst_slat_d2clk, + lclk => abst_slat_lclk, + scan_in(0) => bx_abst_scan_in, + scan_in(1) => bx_abst_scan_out, + scan_out(0) => bx_abst_scan_in_q, + scan_out(1) => bx_abst_scan_out_q ); + +bg_abst_stg: tri_slat_scan + generic map (width => 4, init => "0000", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => abst_slat_d2clk, + lclk => abst_slat_lclk, + scan_in(0 to 1) => bg_an_ac_abst_scan_sn(10 to 11), + scan_in(2 to 3) => bg_ac_an_abst_scan_ns(10 to 11), + scan_out(0 to 1) => bg_an_ac_abst_scan_sn_q(10 to 11), + scan_out(2 to 3) => bg_ac_an_abst_scan_ns_q(10 to 11) ); + +pc_func_stg: tri_slat_scan + generic map (width => 3, init => "000", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => func_slat_d2clk, + lclk => func_slat_lclk, + scan_in(0 to 1) => pc_func_scan_in(0 to 1), + scan_in(2) => pc_func_scan_out, + scan_out(0 to 1)=> pc_func_scan_in_q(0 to 1), + scan_out(2) => pc_func_scan_out_q ); + +fu_func_stg: tri_slat_scan + generic map (width => 8, init => "00000000", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => func_slat_d2clk, + lclk => func_slat_lclk, + scan_in(0 to 3) => fu_func_scan_in(0 to 3), + scan_in(4 to 7) => fu_func_scan_out(0 to 3), + scan_out(0 to 3) => fu_func_scan_in_q(0 to 3), + scan_out(4 to 7) => fu_func_scan_out_q(0 to 3) ); + +bx_func_stg: tri_slat_scan + generic map (width => 4, init => "0000", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => func_slat_d2clk, + lclk => func_slat_lclk, + scan_in(0 to 1) => bx_func_scan_in(0 to 1), + scan_in(2 to 3) => bx_func_scan_out(0 to 1), + scan_out(0 to 1) => bx_func_scan_in_q(0 to 1), + scan_out(2 to 3) => bx_func_scan_out_q(0 to 1) ); + +iu_func_stg: tri_slat_scan + generic map (width => 19, init => "0000000000000000000", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => func_slat_d2clk, + lclk => func_slat_lclk, + scan_in(0 to 8) => iu_func_scan_in(0 to 8), + scan_in(9 to 18) => iu_func_scan_out(0 to 9), + scan_out(0 to 8) => iu_func_scan_in_q(0 to 8), + scan_out(9 to 18) => iu_func_scan_out_q(0 to 9) ); + +spare_func_stg: tri_slat_scan + generic map (width => 8, init => "00000000", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => func_slat_d2clk, + lclk => func_slat_lclk, + scan_in(0 to 3) => spare_func_scan_in(0 to 3), + scan_in(4 to 7) => spare_func_scan_out(0 to 3), + scan_out(0 to 3) => spare_func_scan_in_q(0 to 3), + scan_out(4 to 7) => spare_func_scan_out_q(0 to 3) ); + +bg_func_stg: tri_slat_scan + generic map (width => 20, init => "00000000000000000000", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => func_slat_d2clk, + lclk => func_slat_lclk, + scan_in(0 to 9) => bg_an_ac_func_scan_sn(60 to 69), + scan_in(10 to 19) => bg_ac_an_func_scan_ns(60 to 69), + scan_out(0 to 9) => bg_an_ac_func_scan_sn_q(60 to 69), + scan_out(10 to 19)=> bg_ac_an_func_scan_ns_q(60 to 69) ); + +pc_cfg_stg: tri_slat_scan + generic map (width => 5, init => "00000", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => cfg_slat_d2clk, + lclk => cfg_slat_lclk, + scan_in(0) => pc_bcfg_scan_in, + scan_in(1) => pc_dcfg_scan_in, + scan_in(2) => pc_bcfg_scan_out, + scan_in(3) => pc_ccfg_scan_out, + scan_in(4) => pc_dcfg_scan_out, + scan_out(0) => pc_bcfg_scan_in_q, + scan_out(1) => pc_dcfg_scan_in_q, + scan_out(2) => pc_bcfg_scan_out_q, + scan_out(3) => pc_ccfg_scan_out_q, + scan_out(4) => pc_dcfg_scan_out_q ); + +fu_cfg_stg: tri_slat_scan + generic map (width => 3, init => "000", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => cfg_slat_d2clk, + lclk => cfg_slat_lclk, + scan_in(0) => fu_bcfg_scan_out, + scan_in(1) => fu_ccfg_scan_out, + scan_in(2) => fu_dcfg_scan_out, + scan_out(0) => fu_bcfg_scan_out_q, + scan_out(1) => fu_ccfg_scan_out_q, + scan_out(2) => fu_dcfg_scan_out_q ); + +iu_cfg_stg: tri_slat_scan + generic map (width => 1, init => "0", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => cfg_slat_d2clk, + lclk => cfg_slat_lclk, + scan_in(0) => iu_bcfg_scan_in, + scan_out(0) => iu_bcfg_scan_in_q ); + +abist_staging: tri_rlmreg_p + generic map (width => abst_size, init => 0, expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + nclk => nclk, + act => '1', + thold_b => abst_sl_thold_0_b, + sg => sg_0, + forcee => force_abst, + delay_lclkr => delay_lclkr(0), + mpw1_b => mpw1_b(0), + mpw2_b => mpw2_b, + scin => abst_siv(abst_offset to abst_offset + abst_size-1), + scout => abst_sov(abst_offset to abst_offset + abst_size-1), + din(0) => an_ac_abist_start_test, + dout(0) => rp_pc_abist_start_test_q ); + +abist_bg_staging: tri_rlmreg_p + generic map (width => abst_bg_size, init => 0, expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + nclk => nclk, + act => '1', + thold_b => abst_sl_thold_0_b, + sg => sg_0, + forcee => force_abst, + delay_lclkr => delay_lclkr(0), + mpw1_b => mpw1_b(0), + mpw2_b => mpw2_b, + scin => abst_siv(abst_bg_offset to abst_bg_offset + abst_bg_size-1), + scout => abst_sov(abst_bg_offset to abst_bg_offset + abst_bg_size-1), + din( 0 to 3) => bg_pc_l1p_abist_di_0, + din( 4) => bg_pc_l1p_abist_g8t1p_renb_0, + din( 5) => bg_pc_l1p_abist_g8t_bw_0, + din( 6) => bg_pc_l1p_abist_g8t_bw_1, + din( 7 to 10) => bg_pc_l1p_abist_g8t_dcomp, + din(11) => bg_pc_l1p_abist_g8t_wenb, + din(12 to 21) => bg_pc_l1p_abist_raddr_0, + din(22 to 31) => bg_pc_l1p_abist_waddr_0, + din(32) => bg_pc_l1p_abist_wl128_comp_ena, + din(33) => bg_pc_l1p_abist_wl32_comp_ena, + dout( 0 to 3) => bg_pc_l1p_abist_di_0_q, + dout( 4) => bg_pc_l1p_abist_g8t1p_renb_0_q, + dout( 5) => bg_pc_l1p_abist_g8t_bw_0_q, + dout( 6) => bg_pc_l1p_abist_g8t_bw_1_q, + dout( 7 to 10) => bg_pc_l1p_abist_g8t_dcomp_q, + dout(11) => bg_pc_l1p_abist_g8t_wenb_q, + dout(12 to 21) => bg_pc_l1p_abist_raddr_0_q, + dout(22 to 31) => bg_pc_l1p_abist_waddr_0_q, + dout(32) => bg_pc_l1p_abist_wl128_comp_ena_q, + dout(33) => bg_pc_l1p_abist_wl32_comp_ena_q ); + +perf_staging: tri_rlmreg_p + generic map (width => perf_size, init => 0, expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + nclk => nclk, + act => event_bus_enable_int, + thold_b => func_sl_thold_0_b, + sg => sg_0, + forcee => force_func, + delay_lclkr => delay_lclkr(0), + mpw1_b => mpw1_b(0), + mpw2_b => mpw2_b, + scin => func_siv(perf_offset to perf_offset + perf_size-1), + scout => func_sov(perf_offset to perf_offset + perf_size-1), + din(0 to 7) => pc_rp_event_bus, + din(8 to 15) => pc_rp_fu_bypass_events, + din(16 to 23) => pc_rp_iu_bypass_events, + din(24 to 31) => pc_rp_mm_bypass_events, + din(32 to 39) => pc_rp_lsu_bypass_events, + + dout(0 to 7) => ac_an_event_bus_q, + dout(8 to 15) => ac_an_fu_bypass_events_q, + dout(16 to 23) => ac_an_iu_bypass_events_q, + dout(24 to 31) => ac_an_mm_bypass_events_q, + dout(32 to 39) => ac_an_lsu_bypass_events_q ); + + +func_staging: tri_rlmreg_p + generic map (width => func1_size, init => 0, expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + nclk => nclk, + act => '1', + thold_b => func_sl_thold_0_b, + sg => sg_0, + forcee => force_func, + delay_lclkr => delay_lclkr(0), + mpw1_b => mpw1_b(0), + mpw2_b => mpw2_b, + scin => func_siv(func1_offset to func1_offset + func1_size-1), + scout => func_sov(func1_offset to func1_offset + func1_size-1), + din(0) => an_ac_reset_1_complete, + din(1) => an_ac_reset_2_complete, + din(2) => an_ac_reset_3_complete, + din(3) => an_ac_reset_wd_complete, + din(4 to 11)=> ac_rp_trace_to_perfcntr, + + dout(0) => rp_pc_reset_1_complete_q, + dout(1) => rp_pc_reset_2_complete_q, + dout(2) => rp_pc_reset_3_complete_q, + dout(3) => rp_pc_reset_wd_complete_q, + dout(4 to 11)=> rp_pc_trace_to_perfcntr_q ); + +func_slp_staging: tri_rlmreg_p + generic map (width => func2_size, init => 0, expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + nclk => nclk, + act => '1', + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + forcee => force_func_slp, + delay_lclkr => delay_lclkr(0), + mpw1_b => mpw1_b(0), + mpw2_b => mpw2_b, + scin => func_siv(func2_offset to func2_offset + func2_size-1), + scout => func_sov(func2_offset to func2_offset + func2_size-1), + din(0) => an_ac_scom_dch, + din(1) => an_ac_scom_cch, + din(2) => an_ac_checkstop, + din(3) => an_ac_debug_stop, + din(4 to 7) => an_ac_pm_thread_stop, + din(8) => pc_rp_scom_dch, + din(9) => pc_rp_scom_cch, + din(10 to 13) => pc_rp_special_attn, + din(14 to 16) => pc_rp_checkstop, + din(17 to 19) => pc_rp_local_checkstop, + din(20 to 22) => pc_rp_recov_err, + din(23 to 26) => pc_rp_pm_thread_running, + din(27) => pc_rp_power_managed, + din(28) => pc_rp_rvwinkle_mode, + din(29) => pc_rp_event_bus_enable, + din(30) => pc_rp_trace_error, + + dout(0) => rp_pc_scom_dch_q, + dout(1) => rp_pc_scom_cch_q, + dout(2) => rp_pc_checkstop_q, + dout(3) => rp_pc_debug_stop_q, + dout(4 to 7) => rp_pc_pm_thread_stop_q, + dout(8) => ac_an_scom_dch_q, + dout(9) => ac_an_scom_cch_q, + dout(10 to 13) => ac_an_special_attn_q, + dout(14 to 16) => ac_an_checkstop_q, + dout(17 to 19) => ac_an_local_checkstop_q, + dout(20 to 22) => ac_an_recov_err_q, + dout(23 to 26) => ac_an_pm_thread_running_q, + dout(27) => ac_an_power_managed_q, + dout(28) => ac_an_rvwinkle_mode_q, + dout(29) => event_bus_enable_int, + dout(30) => ac_an_trace_error_q ); + + +iu_bo_enab_4_3: tri_plat + generic map (width => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => an_ac_ccflush_dc, + din(0) => pc_iu_bo_enable_4, + q(0) => pc_iu_bo_enable_3); + +mm_bo_enab_4_3: tri_plat + generic map (width => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => an_ac_ccflush_dc, + din(0) => pc_mm_bo_enable_4, + q(0) => pc_mm_bo_enable_3 ); + +iu_thold_stg4to3: tri_plat + generic map( width => 22, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => an_ac_ccflush_dc, + din( 0) => pc_iu_gptr_sl_thold_4, + din( 1) => pc_iu_time_sl_thold_4, + din( 2) => pc_iu_repr_sl_thold_4, + din( 3) => pc_iu_abst_sl_thold_4, + din( 4) => pc_iu_abst_slp_sl_thold_4, + din( 5) => pc_iu_bolt_sl_thold_4, + din( 6) => pc_iu_regf_slp_sl_thold_4, + din( 7) => pc_iu_func_sl_thold_4, + din( 8) => pc_iu_func_sl_thold_4, + din( 9) => pc_iu_func_sl_thold_4, + din(10) => pc_iu_func_sl_thold_4, + din(11) => pc_iu_func_slp_sl_thold_4, + din(12) => pc_iu_cfg_sl_thold_4, + din(13) => pc_iu_cfg_slp_sl_thold_4, + din(14) => pc_iu_func_slp_nsl_thold_4, + din(15) => pc_iu_ary_nsl_thold_4, + din(16) => pc_iu_ary_slp_nsl_thold_4, + din(17) => pc_iu_sg_4, + din(18) => pc_iu_sg_4, + din(19) => pc_iu_sg_4, + din(20) => pc_iu_sg_4, + din(21) => pc_iu_fce_4, + q( 0) => gptr_sl_thold_3_int, + q( 1) => pc_iu_time_sl_thold_3, + q( 2) => pc_iu_repr_sl_thold_3, + q( 3) => pc_iu_abst_sl_thold_3, + q( 4) => pc_iu_abst_slp_sl_thold_3, + q( 5) => pc_iu_bolt_sl_thold_3, + q( 6) => pc_iu_regf_slp_sl_thold_3, + q( 7) => pc_iu_func_sl_thold_3(0), + q( 8) => pc_iu_func_sl_thold_3(1), + q( 9) => pc_iu_func_sl_thold_3(2), + q(10) => pc_iu_func_sl_thold_3(3), + q(11) => pc_iu_func_slp_sl_thold_3, + q(12) => cfg_sl_thold_3_int, + q(13) => pc_iu_cfg_slp_sl_thold_3, + q(14) => pc_iu_func_slp_nsl_thold_3, + q(15) => pc_iu_ary_nsl_thold_3, + q(16) => pc_iu_ary_slp_nsl_thold_3, + q(17) => pc_iu_sg_3(0), + q(18) => pc_iu_sg_3(1), + q(19) => pc_iu_sg_3(2), + q(20) => pc_iu_sg_3(3), + q(21) => pc_iu_fce_3 + ); + + +mm_thold_stg4to3: tri_plat + generic map( width => 19, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => an_ac_ccflush_dc, + din( 0) => pc_iu_gptr_sl_thold_4, + din( 1) => pc_iu_time_sl_thold_4, + din( 2) => pc_iu_repr_sl_thold_4, + din( 3) => pc_iu_abst_sl_thold_4, + din( 4) => pc_iu_abst_slp_sl_thold_4, + din( 5) => pc_iu_bolt_sl_thold_4, + din( 6) => pc_iu_func_sl_thold_4, + din( 7) => pc_iu_func_sl_thold_4, + din( 8) => pc_iu_func_slp_sl_thold_4, + din( 9) => pc_iu_func_slp_sl_thold_4, + din(10) => pc_iu_cfg_sl_thold_4, + din(11) => pc_iu_cfg_slp_sl_thold_4, + din(12) => pc_iu_func_nsl_thold_4, + din(13) => pc_iu_func_slp_nsl_thold_4, + din(14) => pc_iu_ary_nsl_thold_4, + din(15) => pc_iu_ary_slp_nsl_thold_4, + din(16) => pc_iu_sg_4, + din(17) => pc_iu_sg_4, + din(18) => pc_iu_fce_4, + q( 0) => pc_mm_gptr_sl_thold_3, + q( 1) => pc_mm_time_sl_thold_3, + q( 2) => pc_mm_repr_sl_thold_3, + q( 3) => pc_mm_abst_sl_thold_3, + q( 4) => pc_mm_abst_slp_sl_thold_3, + q( 5) => pc_mm_bolt_sl_thold_3, + q( 6) => pc_mm_func_sl_thold_3(0), + q( 7) => pc_mm_func_sl_thold_3(1), + q( 8) => pc_mm_func_slp_sl_thold_3(0), + q( 9) => pc_mm_func_slp_sl_thold_3(1), + q(10) => pc_mm_cfg_sl_thold_3, + q(11) => pc_mm_cfg_slp_sl_thold_3, + q(12) => pc_mm_func_nsl_thold_3, + q(13) => pc_mm_func_slp_nsl_thold_3, + q(14) => pc_mm_ary_nsl_thold_3, + q(15) => pc_mm_ary_slp_nsl_thold_3, + q(16) => pc_mm_sg_3(0), + q(17) => pc_mm_sg_3(1), + q(18) => pc_mm_fce_3 + ); + +abst_siv(0 TO abst_right) <= abst_scan_in & abst_sov(0 to abst_right-1); +abst_scan_out <= abst_sov(abst_right) and scan_dis_dc_b; + +func_siv(0 TO func_right) <= func_scan_in & func_sov(0 to func_right-1); +func_scan_out <= func_sov(func_right) and scan_dis_dc_b; + +end iuq_rp; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_slice.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_slice.vhdl new file mode 100644 index 0000000..6fe52db --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_slice.vhdl @@ -0,0 +1,817 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; +use ieee.std_logic_1164.all; +library ibm; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; +library support; +use support.power_logic_pkg.all; +library work; +use work.iuq_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity iuq_slice is + generic(expand_type : integer := 2; + regmode : integer := 6; + a2mode : integer := 1; + lmq_entries : integer := 8); +port( + slice_id : in std_ulogic_vector(0 to 1); + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + pc_iu_sg_2 : in std_ulogic; + pc_iu_func_sl_thold_2 : in std_ulogic; + clkoff_b : in std_ulogic; + an_ac_scan_dis_dc_b : in std_ulogic; + tc_ac_ccflush_dc : in std_ulogic; + delay_lclkr : in std_ulogic; + mpw1_b : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + + pc_iu_trace_bus_enable : in std_ulogic; + pc_iu_event_bus_enable : in std_ulogic; + fdep_dbg_data : out std_ulogic_vector(0 to 21); + fdep_perf_event : out std_ulogic_vector(0 to 11); + + pc_iu_ram_mode : in std_ulogic; + pc_iu_ram_thread : in std_ulogic_vector(0 to 1); + + spr_dec_mask : in std_ulogic_vector(0 to 31); + spr_dec_match : in std_ulogic_vector(0 to 31); + iu_au_config_iucr : in std_ulogic_vector(0 to 7); + iu_au_config_iucr_pt : out std_ulogic_vector(2 to 4); + spr_fdep_ll_hold : in std_ulogic; + + + uc_flush : in std_ulogic; + xu_iu_flush : in std_ulogic; + xu_iu_rf1_flush : in std_ulogic; + xu_iu_ex1_flush : in std_ulogic; + xu_iu_ex2_flush : in std_ulogic; + xu_iu_ex3_flush : in std_ulogic; + xu_iu_ex4_flush : in std_ulogic; + xu_iu_ex5_flush : in std_ulogic; + + iu_au_ib1_instr_vld : in std_ulogic; + iu_au_ib1_ifar : in EFF_IFAR; + iu_au_ib1_data : in std_ulogic_vector(0 to 49); + + + fdec_ibuf_stall : out std_ulogic; + + +xu_iu_ucode_restart : in std_ulogic; +xu_iu_slowspr_done : in std_ulogic; +xu_iu_multdiv_done : in std_ulogic; +xu_iu_ex4_loadmiss_vld : in std_ulogic; +xu_iu_ex4_loadmiss_qentry : in std_ulogic_vector(0 to lmq_entries-1); +xu_iu_ex4_loadmiss_target : in std_ulogic_vector(0 to 8); +xu_iu_ex4_loadmiss_target_type : in std_ulogic_vector(0 to 1); +xu_iu_ex5_loadmiss_vld : in std_ulogic; +xu_iu_ex5_loadmiss_qentry : in std_ulogic_vector(0 to lmq_entries-1); +xu_iu_ex5_loadmiss_target : in std_ulogic_vector(1 to 6); +xu_iu_ex5_loadmiss_target_type : in std_ulogic_vector(0 to 0); +xu_iu_complete_vld : in std_ulogic; +xu_iu_complete_qentry : in std_ulogic_vector(0 to lmq_entries-1); +xu_iu_complete_target_type : in std_ulogic_vector(0 to 1); +xu_iu_single_instr_mode : in std_ulogic; +ic_fdep_load_quiesce : in std_ulogic; +iu_xu_quiesce : out std_ulogic; +xu_iu_membar_tid : in std_ulogic; +xu_iu_set_barr_tid : in std_ulogic; +xu_iu_larx_done_tid : in std_ulogic; +an_ac_sync_ack : in std_ulogic; +an_ac_stcx_complete : in std_ulogic; +ic_fdep_icbi_ack : in std_ulogic; +mm_iu_barrier_done : in std_ulogic; +xu_iu_spr_ccr2_en_dcr : in std_ulogic; +fiss_fdep_is2_take : in std_ulogic; +fdep_fiss_is2_instr : out std_ulogic_vector(0 to 31); +fdep_fiss_is2_ta_vld : out std_ulogic; +fdep_fiss_is2_ta : out std_ulogic_vector(0 to 5); +fdep_fiss_is2_s1_vld : out std_ulogic; +fdep_fiss_is2_s1 : out std_ulogic_vector(0 to 5); +fdep_fiss_is2_s2_vld : out std_ulogic; +fdep_fiss_is2_s2 : out std_ulogic_vector(0 to 5); +fdep_fiss_is2_s3_vld : out std_ulogic; +fdep_fiss_is2_s3 : out std_ulogic_vector(0 to 5); +fdep_fiss_is2_pred_update : out std_ulogic; +fdep_fiss_is2_pred_taken_cnt : out std_ulogic_vector(0 to 1); +fdep_fiss_is2_gshare : out std_ulogic_vector(0 to 3); +fdep_fiss_is2_ifar : out eff_ifar; +fdep_fiss_is2_error : out std_ulogic_vector(0 to 2); +fdep_fiss_is2_axu_ld_or_st : out std_ulogic; +fdep_fiss_is2_axu_store : out std_ulogic; +fdep_fiss_is2_axu_ldst_indexed : out std_ulogic; +fdep_fiss_is2_axu_ldst_tag : out std_ulogic_vector(0 to 8); +fdep_fiss_is2_axu_ldst_size : out std_ulogic_vector(0 to 5); +fdep_fiss_is2_axu_ldst_update : out std_ulogic; +fdep_fiss_is2_axu_ldst_extpid : out std_ulogic; +fdep_fiss_is2_axu_ldst_forcealign : out std_ulogic; +fdep_fiss_is2_axu_ldst_forceexcept : out std_ulogic; +fdep_fiss_is2_axu_mftgpr : out std_ulogic; +fdep_fiss_is2_axu_mffgpr : out std_ulogic; +fdep_fiss_is2_axu_movedp : out std_ulogic; +fdep_fiss_is2_axu_instr_type : out std_ulogic_vector(0 to 2); +fdep_fiss_is2_match : out std_ulogic; +fdep_fiss_is2_2ucode : out std_ulogic; +fdep_fiss_is2_2ucode_type : out std_ulogic; +fdep_fiss_is2early_vld : out std_ulogic; +fdep_fiss_is1_xu_dep_hit_b : out std_ulogic; +fdep_fiss_is2_hole_delay : out std_ulogic_vector(0 to 2); +fdep_fiss_is2_to_ucode : out std_ulogic; +fdep_fiss_is2_is_ucode : out std_ulogic; +fu_iu_uc_special : in std_ulogic; +iu_fu_ex2_n_flush : out std_ulogic; +i_afi_is2_take : in std_ulogic; +i_axu_is1_early_v : out std_ulogic; +i_axu_is1_dep_hit_b : out std_ulogic; +i_axu_is2_instr_match : out std_ulogic; +i_axu_is2_instr_v : out std_ulogic; +i_axu_is2_fra : out std_ulogic_vector(0 to 6); +i_axu_is2_frb : out std_ulogic_vector(0 to 6); +i_axu_is2_frc : out std_ulogic_vector(0 to 6); +i_axu_is2_frt : out std_ulogic_vector(0 to 6); +i_axu_is2_fra_v : out std_ulogic; +i_axu_is2_frb_v : out std_ulogic; +i_axu_is2_frc_v : out std_ulogic; +i_afd_is2_is_ucode : out std_ulogic; +i_afd_ignore_flush_is2 : out std_ulogic; +i_afd_in_ucode_mode_or1d_b : out std_ulogic; +ifdp_is2_est_bubble3 : out std_ulogic; +ifdp_is2_bypsel : out std_ulogic_vector(0 to 5); +axu_dbg_data : out std_ulogic_vector(00 to 37) + ); +-- synopsys translate_off +-- synopsys translate_on +end iuq_slice; +architecture iuq_slice of iuq_slice is +constant ibuff_data_width : integer := 42; +constant scan_dec : natural := 0; +constant scan_dep : natural := 1; +constant scan_axu_dec : natural := 2; +constant scan_axu_dep : natural := 3; +constant scan_right : natural := 3; +signal au_iu_is0_to_ucode : std_ulogic; +signal au_iu_is0_ucode_only : std_ulogic; +signal ib1_flush : std_ulogic; +signal is1_flush : std_ulogic; +signal is2_flush : std_ulogic; +signal rf0_flush : std_ulogic; +signal iu_au_ib1_instr0 : std_ulogic_vector(0 to 31); +signal iu_au_ib1_instr0_pred_vld : std_ulogic; +signal iu_au_ib1_instr0_ucode_ext : std_ulogic_vector(0 to 3); +signal iu_au_ib1_instr0_pred_taken_cnt : std_ulogic_vector(0 to 1); +signal iu_au_ib1_instr0_error : std_ulogic_vector(0 to 2); +signal iu_au_ib1_instr0_is_ucode : std_ulogic; +signal iu_au_ib1_instr0_2ucode : std_ulogic; +signal iu_au_ib1_instr0_2ucode_type : std_ulogic; +signal iu_au_ib1_instr0_force_ram : std_ulogic; +signal iu_au_ib1_instr0_gshare : std_ulogic_vector(0 to 3); +signal iu_au_is1_cr_user_v : std_ulogic; +signal iu_au_is0_cr_setter : std_ulogic; +signal i_afd_is1_cr_setter : std_ulogic; +signal fdec_fdep_is1_vld : std_ulogic; +signal fdec_fdep_is1_instr : std_ulogic_vector(0 to 31); +signal fdec_fdep_is1_ta_vld : std_ulogic; +signal fdec_fdep_is1_ta : std_ulogic_vector(0 to 5); +signal fdec_fdep_is1_s1_vld : std_ulogic; +signal fdec_fdep_is1_s1 : std_ulogic_vector(0 to 5); +signal fdec_fdep_is1_s2_vld : std_ulogic; +signal fdec_fdep_is1_s2 : std_ulogic_vector(0 to 5); +signal fdec_fdep_is1_s3_vld : std_ulogic; +signal fdec_fdep_is1_s3 : std_ulogic_vector(0 to 5); +signal fdec_fdep_is1_pred_update : std_ulogic; +signal fdec_fdep_is1_pred_taken_cnt : std_ulogic_vector(0 to 1); +signal fdec_fdep_is1_gshare : std_ulogic_vector(0 to 3); +signal fdec_fdep_is1_UpdatesLR : std_ulogic; +signal fdec_fdep_is1_UpdatesCR : std_ulogic; +signal fdec_fdep_is1_UpdatesCTR : std_ulogic; +signal fdec_fdep_is1_UpdatesXER : std_ulogic; +signal fdec_fdep_is1_UpdatesMSR : std_ulogic; +signal fdec_fdep_is1_UpdatesSPR : std_ulogic; +signal fdec_fdep_is1_UsesLR : std_ulogic; +signal fdec_fdep_is1_UsesCR : std_ulogic; +signal fdec_fdep_is1_UsesCTR : std_ulogic; +signal fdec_fdep_is1_UsesXER : std_ulogic; +signal fdec_fdep_is1_UsesMSR : std_ulogic; +signal fdec_fdep_is1_UsesSPR : std_ulogic; +signal fdec_fdep_is1_hole_delay : std_ulogic_vector(0 to 2); +signal fdec_fdep_is1_ld_vld : std_ulogic; +signal fdec_fdep_is1_to_ucode : std_ulogic; +signal fdec_fdep_is1_is_ucode : std_ulogic; +signal fdec_fdep_is1_ifar : EFF_IFAR; +signal fdec_fdep_is1_error : std_ulogic_vector(0 to 2); +signal fdec_fdep_is1_complete : std_ulogic_vector(0 to 4); +signal fdec_fdep_is1_axu_ld_or_st : std_ulogic; +signal fdec_fdep_is1_axu_store : std_ulogic; +signal fdec_fdep_is1_axu_ldst_indexed : std_ulogic; +signal fdec_fdep_is1_axu_ldst_tag : std_ulogic_vector(0 to 8); +signal fdec_fdep_is1_axu_ldst_size : std_ulogic_vector(0 to 5); +signal fdec_fdep_is1_axu_ldst_update : std_ulogic; +signal fdec_fdep_is1_axu_ldst_extpid : std_ulogic; +signal fdec_fdep_is1_axu_ldst_forcealign: std_ulogic; +signal fdec_fdep_is1_axu_ldst_forceexcept: std_ulogic; +signal fdec_fdep_is1_axu_mftgpr : std_ulogic; +signal fdec_fdep_is1_axu_mffgpr : std_ulogic; +signal fdec_fdep_is1_axu_movedp : std_ulogic; +signal fdec_fdep_is1_axu_instr_type : std_ulogic_vector(0 to 2); +signal fdec_fdep_is1_match : std_ulogic; +signal fdec_fdep_is1_2ucode : std_ulogic; +signal fdec_fdep_is1_2ucode_type : std_ulogic; +signal fdec_fdep_is1_force_ram : std_ulogic; +signal iu_au_is2_stall : std_ulogic; +signal iu_au_is1_stall_int : std_ulogic; +signal iu_au_is1_hold : std_ulogic; +signal fdep_fdec_buff_stall : std_ulogic; +signal fdep_fdec_weak_stall : std_ulogic; +signal au_iu_ib1_store : std_ulogic; +signal au_iu_ib1_ldst_size : std_ulogic_vector(0 to 5); +signal au_iu_ib1_ldst_tag : std_ulogic_vector(0 to 8); +signal au_iu_ib1_ldst_ra_v : std_ulogic; +signal au_iu_ib1_ldst_ra : std_ulogic_vector(0 to 6); +signal au_iu_ib1_ldst_rb_v : std_ulogic; +signal au_iu_ib1_ldst_rb : std_ulogic_vector(0 to 6); +signal au_iu_ib1_ldst_dimm : std_ulogic_vector(0 to 15); +signal au_iu_ib1_ldst_indexed : std_ulogic; +signal au_iu_ib1_ldst_update : std_ulogic; +signal au_iu_ib1_ldst_extpid : std_ulogic; +signal au_iu_ib1_ldst_forcealign : std_ulogic; +signal au_iu_ib1_ldst_forceexcept : std_ulogic; +signal au_iu_ib1_mftgpr : std_ulogic; +signal au_iu_ib1_mffgpr : std_ulogic; +signal au_iu_ib1_movedp : std_ulogic; +signal au_iu_ib1_instr_type : std_ulogic_vector(0 to 2); +signal au_iu_ib1_ldst : std_ulogic; +signal au_iu_ib1_ldst_v : std_ulogic; +signal au_iu_i_dec_b : std_ulogic; +signal i_afd_is1_fra_v : std_ulogic; +signal i_afd_is1_frb_v : std_ulogic; +signal i_afd_is1_frc_v : std_ulogic; +signal i_afd_is1_frt_v : std_ulogic; +signal i_afd_is1_prebubble1 : std_ulogic; +signal i_afd_is1_est_bubble3 : std_ulogic; +signal i_afd_is1_cr_writer : std_ulogic; +signal i_afd_is1_fra : std_ulogic_vector(0 to 6); +signal i_afd_is1_frb : std_ulogic_vector(0 to 6); +signal i_afd_is1_frc : std_ulogic_vector(0 to 6); +signal i_afd_is1_frt : std_ulogic_vector(0 to 6); +signal i_afd_is1_instr_v : std_ulogic; +signal i_afd_is1_instr_ldst_v : std_ulogic; +signal i_afd_is1_instr_ld_v : std_ulogic; +signal i_afd_is1_is_ucode : std_ulogic; +signal i_afd_is1_to_ucode : std_ulogic; +signal i_afd_ignore_flush_is1_int : std_ulogic; +signal i_afd_config_iucr : std_ulogic_vector(1 to 7); +signal i_afd_in_ucode_mode_or1d : std_ulogic; +signal i_afd_is1_fra_buf : std_ulogic_vector(1 to 6); +signal i_afd_is1_frb_buf : std_ulogic_vector(1 to 6); +signal i_afd_is1_frc_buf : std_ulogic_vector(1 to 6); +signal i_afd_is1_frt_buf : std_ulogic_vector(1 to 6); +signal i_afd_is1_divsqrt : std_ulogic; +signal i_afd_is1_stall_rep : std_ulogic; +signal i_afd_is1_instr_sto_v : std_ulogic; +signal au_iu_is1_dep_hit : std_ulogic; +signal au_iu_is1_dep_hit_b : std_ulogic; +signal au_iu_is2_axubusy : std_ulogic; +signal au_iu_issue_stall : std_ulogic; +signal ifdp_ex5_fmul_uc_complete : std_ulogic; +signal i_afd_fmul_uc_is1 : std_ulogic; +signal pc_au_ram_mode : std_ulogic; +signal pc_au_ram_thread_v : std_ulogic; +signal fu_dec_debug : std_ulogic_vector(0 to 13); +signal fu_dep_debug : std_ulogic_vector(0 to 23); +signal siv : std_ulogic_vector(0 to scan_right); +signal sov : std_ulogic_vector(0 to scan_right); +signal pc_iu_func_sl_thold_1 : std_ulogic; +signal pc_iu_func_sl_thold_0 : std_ulogic; +signal pc_iu_func_sl_thold_0_b : std_ulogic; +signal pc_iu_sg_1 : std_ulogic; +signal pc_iu_sg_0 : std_ulogic; +signal forcee : std_ulogic; +signal act_dis : std_ulogic; +signal d_mode : std_ulogic; +signal mpw2_b : std_ulogic; +begin +act_dis <= '0'; +d_mode <= '0'; +mpw2_b <= '1'; +iu_au_config_iucr_pt(2 to 4) <= iu_au_config_iucr(2 to 3) & iu_au_config_iucr(5); +iu_au_ib1_instr0(0 to 31) <= iu_au_ib1_data(0 to 31); +iu_au_ib1_instr0_ucode_ext(0 to 3) <= iu_au_ib1_data(32 to 35); +iu_au_ib1_instr0_pred_taken_cnt(0 to 1) <= iu_au_ib1_data(36 to 37); +iu_au_ib1_instr0_pred_vld <= iu_au_ib1_data(38); +iu_au_ib1_instr0_error <= iu_au_ib1_data(39 to 41); +iu_au_ib1_instr0_is_ucode <= iu_au_ib1_data(42); +iu_au_ib1_instr0_2ucode <= iu_au_ib1_data(43); +iu_au_ib1_instr0_2ucode_type <= iu_au_ib1_data(44); +iu_au_ib1_instr0_force_ram <= iu_au_ib1_data(45); +iu_au_ib1_instr0_gshare <= iu_au_ib1_data(46 to 49); +ib1_flush <= xu_iu_flush or uc_flush; +is1_flush <= xu_iu_flush or uc_flush; +is2_flush <= xu_iu_flush or uc_flush; +rf0_flush <= xu_iu_flush or uc_flush; +i_axu_is1_dep_hit_b <= au_iu_is1_dep_hit_b; +pc_au_ram_mode <= pc_iu_ram_mode; +pc_au_ram_thread_v <= pc_iu_ram_thread(0 to 1) = slice_id(0 to 1); +iu_fxu_decode0 : entity work.iuq_fxu_decode +generic map(a2mode => a2mode, + regmode => regmode, + expand_type => expand_type) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_iu_func_sl_thold_0_b => pc_iu_func_sl_thold_0_b, + pc_iu_sg_0 => pc_iu_sg_0, + forcee => forcee, + d_mode => d_mode, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + scan_in => siv(scan_dec), + scan_out => sov(scan_dec), + pc_au_ram_mode => pc_au_ram_mode, + pc_au_ram_thread_v => pc_au_ram_thread_v, + spr_dec_mask => spr_dec_mask, + spr_dec_match => spr_dec_match, + fdep_fdec_buff_stall => fdep_fdec_buff_stall, + fdep_fdec_weak_stall => fdep_fdec_weak_stall, + au_iu_i_dec_b => au_iu_i_dec_b, + iu_au_is1_cr_user_v => iu_au_is1_cr_user_v, + iu_au_is0_cr_setter => iu_au_is0_cr_setter, + au_iu_ib1_ldst => au_iu_ib1_ldst, + au_iu_ib1_ldst_v => au_iu_ib1_ldst_v, + au_iu_ib1_store => au_iu_ib1_store, + au_iu_ib1_ldst_size => au_iu_ib1_ldst_size, + au_iu_ib1_ldst_tag => au_iu_ib1_ldst_tag, + au_iu_ib1_ldst_ra => au_iu_ib1_ldst_ra, + au_iu_ib1_ldst_ra_v => au_iu_ib1_ldst_ra_v, + au_iu_ib1_ldst_rb => au_iu_ib1_ldst_rb, + au_iu_ib1_ldst_rb_v => au_iu_ib1_ldst_rb_v, + au_iu_ib1_ldst_dimm => au_iu_ib1_ldst_dimm, + au_iu_ib1_ldst_indexed => au_iu_ib1_ldst_indexed, + au_iu_ib1_ldst_update => au_iu_ib1_ldst_update, + au_iu_ib1_ldst_extpid => au_iu_ib1_ldst_extpid, + au_iu_ib1_ldst_forcealign => au_iu_ib1_ldst_forcealign, + au_iu_ib1_ldst_forceexcept => au_iu_ib1_ldst_forceexcept, + au_iu_ib1_mftgpr => au_iu_ib1_mftgpr, + au_iu_ib1_mffgpr => au_iu_ib1_mffgpr, + au_iu_ib1_movedp => au_iu_ib1_movedp, + au_iu_ib1_instr_type => au_iu_ib1_instr_type, + iu_au_ib1_instr_vld => iu_au_ib1_instr_vld, + iu_au_ib1_ifar => iu_au_ib1_ifar, + iu_au_ib1_instr => iu_au_ib1_instr0, + iu_au_ib1_instr_ucode_ext => iu_au_ib1_instr0_ucode_ext, + iu_au_ib1_instr_pred_vld => iu_au_ib1_instr0_pred_vld, + iu_au_ib1_instr_pred_taken_cnt => iu_au_ib1_instr0_pred_taken_cnt, + iu_au_ib1_instr_gshare => iu_au_ib1_instr0_gshare, + iu_au_ib1_instr_error => iu_au_ib1_instr0_error, + iu_au_ib1_instr_is_ucode => iu_au_ib1_instr0_is_ucode, + iu_au_ib1_instr_2ucode => iu_au_ib1_instr0_2ucode, + iu_au_ib1_instr_2ucode_type => iu_au_ib1_instr0_2ucode_type, + iu_au_ib1_instr_force_ram => iu_au_ib1_instr0_force_ram, + au_iu_is0_to_ucode => au_iu_is0_to_ucode, + au_iu_is0_ucode_only => au_iu_is0_ucode_only, + iu_au_is1_stall => iu_au_is1_stall_int, + xu_iu_ib1_flush => ib1_flush, + fdec_ibuf_stall => fdec_ibuf_stall, + fdec_fdep_is1_vld => fdec_fdep_is1_vld, + fdec_fdep_is1_instr => fdec_fdep_is1_instr, + fdec_fdep_is1_ta_vld => fdec_fdep_is1_ta_vld, + fdec_fdep_is1_ta => fdec_fdep_is1_ta, + fdec_fdep_is1_s1_vld => fdec_fdep_is1_s1_vld, + fdec_fdep_is1_s1 => fdec_fdep_is1_s1, + fdec_fdep_is1_s2_vld => fdec_fdep_is1_s2_vld, + fdec_fdep_is1_s2 => fdec_fdep_is1_s2, + fdec_fdep_is1_s3_vld => fdec_fdep_is1_s3_vld, + fdec_fdep_is1_s3 => fdec_fdep_is1_s3, + fdec_fdep_is1_pred_update => fdec_fdep_is1_pred_update, + fdec_fdep_is1_pred_taken_cnt => fdec_fdep_is1_pred_taken_cnt, + fdec_fdep_is1_gshare => fdec_fdep_is1_gshare, + fdec_fdep_is1_UpdatesLR => fdec_fdep_is1_UpdatesLR, + fdec_fdep_is1_UpdatesCR => fdec_fdep_is1_UpdatesCR, + fdec_fdep_is1_UpdatesCTR => fdec_fdep_is1_UpdatesCTR, + fdec_fdep_is1_UpdatesXER => fdec_fdep_is1_UpdatesXER, + fdec_fdep_is1_UpdatesMSR => fdec_fdep_is1_UpdatesMSR, + fdec_fdep_is1_UpdatesSPR => fdec_fdep_is1_UpdatesSPR, + fdec_fdep_is1_UsesLR => fdec_fdep_is1_UsesLR, + fdec_fdep_is1_UsesCR => fdec_fdep_is1_UsesCR, + fdec_fdep_is1_UsesCTR => fdec_fdep_is1_UsesCTR, + fdec_fdep_is1_UsesXER => fdec_fdep_is1_UsesXER, + fdec_fdep_is1_UsesMSR => fdec_fdep_is1_UsesMSR, + fdec_fdep_is1_UsesSPR => fdec_fdep_is1_UsesSPR, + fdec_fdep_is1_hole_delay => fdec_fdep_is1_hole_delay, + fdec_fdep_is1_ld_vld => fdec_fdep_is1_ld_vld, + fdec_fdep_is1_to_ucode => fdec_fdep_is1_to_ucode, + fdec_fdep_is1_is_ucode => fdec_fdep_is1_is_ucode, + fdec_fdep_is1_ifar => fdec_fdep_is1_ifar, + fdec_fdep_is1_error => fdec_fdep_is1_error, + fdec_fdep_is1_complete => fdec_fdep_is1_complete, + fdec_fdep_is1_axu_ld_or_st => fdec_fdep_is1_axu_ld_or_st, + fdec_fdep_is1_axu_store => fdec_fdep_is1_axu_store, + fdec_fdep_is1_axu_ldst_size => fdec_fdep_is1_axu_ldst_size, + fdec_fdep_is1_axu_ldst_tag => fdec_fdep_is1_axu_ldst_tag, + +fdec_fdep_is1_axu_ldst_indexed => fdec_fdep_is1_axu_ldst_indexed, + fdec_fdep_is1_axu_ldst_update => fdec_fdep_is1_axu_ldst_update, + fdec_fdep_is1_axu_ldst_extpid => fdec_fdep_is1_axu_ldst_extpid, + fdec_fdep_is1_axu_ldst_forcealign => fdec_fdep_is1_axu_ldst_forcealign, + fdec_fdep_is1_axu_ldst_forceexcept => fdec_fdep_is1_axu_ldst_forceexcept, + fdec_fdep_is1_axu_mftgpr => fdec_fdep_is1_axu_mftgpr, + fdec_fdep_is1_axu_mffgpr => fdec_fdep_is1_axu_mffgpr, + fdec_fdep_is1_axu_movedp => fdec_fdep_is1_axu_movedp, + fdec_fdep_is1_axu_instr_type => fdec_fdep_is1_axu_instr_type, + fdec_fdep_is1_2ucode => fdec_fdep_is1_2ucode, + fdec_fdep_is1_2ucode_type => fdec_fdep_is1_2ucode_type, + fdec_fdep_is1_force_ram => fdec_fdep_is1_force_ram, + fdec_fdep_is1_match => fdec_fdep_is1_match +); +iu_fxu_dep0 : entity work.iuq_fxu_dep +generic map(expand_type => expand_type, + regmode => regmode, + lmq_entries => lmq_entries) +port map(vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_iu_func_sl_thold_0_b => pc_iu_func_sl_thold_0_b, + pc_iu_sg_0 => pc_iu_sg_0, + forcee => forcee, + d_mode => d_mode, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + scan_in => siv(scan_dep), + scan_out => sov(scan_dep), + pc_iu_trace_bus_enable => pc_iu_trace_bus_enable, + pc_iu_event_bus_enable => pc_iu_event_bus_enable, + fdep_dbg_data => fdep_dbg_data, + fdep_perf_event => fdep_perf_event, + fdep_fdec_buff_stall => fdep_fdec_buff_stall, + fdep_fdec_weak_stall => fdep_fdec_weak_stall, + fdec_fdep_is1_vld => fdec_fdep_is1_vld, + fdec_fdep_is1_instr => fdec_fdep_is1_instr, + fdec_fdep_is1_ta_vld => fdec_fdep_is1_ta_vld, + fdec_fdep_is1_ta => fdec_fdep_is1_ta, + fdec_fdep_is1_s1_vld => fdec_fdep_is1_s1_vld, + fdec_fdep_is1_s1 => fdec_fdep_is1_s1, + fdec_fdep_is1_s2_vld => fdec_fdep_is1_s2_vld, + fdec_fdep_is1_s2 => fdec_fdep_is1_s2, + fdec_fdep_is1_s3_vld => fdec_fdep_is1_s3_vld, + fdec_fdep_is1_s3 => fdec_fdep_is1_s3, + fdec_fdep_is1_pred_update => fdec_fdep_is1_pred_update, + fdec_fdep_is1_pred_taken_cnt => fdec_fdep_is1_pred_taken_cnt, + fdec_fdep_is1_gshare => fdec_fdep_is1_gshare, + fdec_fdep_is1_UpdatesLR => fdec_fdep_is1_UpdatesLR, + fdec_fdep_is1_UpdatesCR => fdec_fdep_is1_UpdatesCR, + fdec_fdep_is1_UpdatesCTR => fdec_fdep_is1_UpdatesCTR, + fdec_fdep_is1_UpdatesXER => fdec_fdep_is1_UpdatesXER, + fdec_fdep_is1_UpdatesMSR => fdec_fdep_is1_UpdatesMSR, + fdec_fdep_is1_UpdatesSPR => fdec_fdep_is1_UpdatesSPR, + fdec_fdep_is1_UsesLR => fdec_fdep_is1_UsesLR, + fdec_fdep_is1_UsesCR => fdec_fdep_is1_UsesCR, + fdec_fdep_is1_UsesCTR => fdec_fdep_is1_UsesCTR, + fdec_fdep_is1_UsesXER => fdec_fdep_is1_UsesXER, + fdec_fdep_is1_UsesMSR => fdec_fdep_is1_UsesMSR, + fdec_fdep_is1_UsesSPR => fdec_fdep_is1_UsesSPR, + fdec_fdep_is1_hole_delay => fdec_fdep_is1_hole_delay, + fdec_fdep_is1_ld_vld => fdec_fdep_is1_ld_vld, + fdec_fdep_is1_to_ucode => fdec_fdep_is1_to_ucode, + fdec_fdep_is1_is_ucode => fdec_fdep_is1_is_ucode, + fdec_fdep_is1_ifar => fdec_fdep_is1_ifar, + fdec_fdep_is1_error => fdec_fdep_is1_error, + fdec_fdep_is1_complete => fdec_fdep_is1_complete, + fdec_fdep_is1_axu_ld_or_st => fdec_fdep_is1_axu_ld_or_st, + fdec_fdep_is1_axu_store => fdec_fdep_is1_axu_store, + fdec_fdep_is1_axu_ldst_size => fdec_fdep_is1_axu_ldst_size, + fdec_fdep_is1_axu_ldst_tag => fdec_fdep_is1_axu_ldst_tag, + +fdec_fdep_is1_axu_ldst_indexed => fdec_fdep_is1_axu_ldst_indexed, + fdec_fdep_is1_axu_ldst_update => fdec_fdep_is1_axu_ldst_update, + fdec_fdep_is1_axu_ldst_extpid => fdec_fdep_is1_axu_ldst_extpid, + fdec_fdep_is1_axu_ldst_forcealign => fdec_fdep_is1_axu_ldst_forcealign, + fdec_fdep_is1_axu_ldst_forceexcept => fdec_fdep_is1_axu_ldst_forceexcept, + fdec_fdep_is1_axu_mftgpr => fdec_fdep_is1_axu_mftgpr, + fdec_fdep_is1_axu_mffgpr => fdec_fdep_is1_axu_mffgpr, + fdec_fdep_is1_axu_movedp => fdec_fdep_is1_axu_movedp, + fdec_fdep_is1_axu_instr_type => fdec_fdep_is1_axu_instr_type, + fdec_fdep_is1_match => fdec_fdep_is1_match, + fdec_fdep_is1_2ucode => fdec_fdep_is1_2ucode, + fdec_fdep_is1_2ucode_type => fdec_fdep_is1_2ucode_type, + fdec_fdep_is1_force_ram => fdec_fdep_is1_force_ram, + fdep_fiss_is2_instr => fdep_fiss_is2_instr, + fdep_fiss_is2_ta_vld => fdep_fiss_is2_ta_vld, + fdep_fiss_is2_ta => fdep_fiss_is2_ta, + fdep_fiss_is2_s1_vld => fdep_fiss_is2_s1_vld, + fdep_fiss_is2_s1 => fdep_fiss_is2_s1, + fdep_fiss_is2_s2_vld => fdep_fiss_is2_s2_vld, + fdep_fiss_is2_s2 => fdep_fiss_is2_s2, + fdep_fiss_is2_s3_vld => fdep_fiss_is2_s3_vld, + fdep_fiss_is2_s3 => fdep_fiss_is2_s3, + fdep_fiss_is2_pred_update => fdep_fiss_is2_pred_update, + fdep_fiss_is2_pred_taken_cnt => fdep_fiss_is2_pred_taken_cnt, + fdep_fiss_is2_gshare => fdep_fiss_is2_gshare, + fdep_fiss_is2_ifar => fdep_fiss_is2_ifar, + fdep_fiss_is2_error => fdep_fiss_is2_error, + fdep_fiss_is2_axu_ld_or_st => fdep_fiss_is2_axu_ld_or_st, + fdep_fiss_is2_axu_store => fdep_fiss_is2_axu_store, + fdep_fiss_is2_axu_ldst_size => fdep_fiss_is2_axu_ldst_size, + fdep_fiss_is2_axu_ldst_tag => fdep_fiss_is2_axu_ldst_tag, + +fdep_fiss_is2_axu_ldst_indexed => fdep_fiss_is2_axu_ldst_indexed, + fdep_fiss_is2_axu_ldst_update => fdep_fiss_is2_axu_ldst_update, + fdep_fiss_is2_axu_ldst_extpid => fdep_fiss_is2_axu_ldst_extpid, + fdep_fiss_is2_axu_ldst_forcealign => fdep_fiss_is2_axu_ldst_forcealign, + fdep_fiss_is2_axu_ldst_forceexcept => fdep_fiss_is2_axu_ldst_forceexcept, + fdep_fiss_is2_axu_mftgpr => fdep_fiss_is2_axu_mftgpr, + fdep_fiss_is2_axu_mffgpr => fdep_fiss_is2_axu_mffgpr, + fdep_fiss_is2_axu_movedp => fdep_fiss_is2_axu_movedp, + fdep_fiss_is2_axu_instr_type => fdep_fiss_is2_axu_instr_type, + fdep_fiss_is2_match => fdep_fiss_is2_match, + fdep_fiss_is2_2ucode => fdep_fiss_is2_2ucode, + fdep_fiss_is2_2ucode_type => fdep_fiss_is2_2ucode_type, + fdep_fiss_is2early_vld => fdep_fiss_is2early_vld, + fdep_fiss_is1_xu_dep_hit_b => fdep_fiss_is1_xu_dep_hit_b, + fdep_fiss_is2_hole_delay => fdep_fiss_is2_hole_delay, + fdep_fiss_is2_to_ucode => fdep_fiss_is2_to_ucode, + fdep_fiss_is2_is_ucode => fdep_fiss_is2_is_ucode, + fiss_fdep_is2_take => fiss_fdep_is2_take, + i_afd_is1_instr_v => i_afd_is1_instr_v, + au_iu_issue_stall => au_iu_issue_stall, + iu_au_is2_stall => iu_au_is2_stall, + au_iu_is1_dep_hit => au_iu_is1_dep_hit, + au_iu_is1_dep_hit_b => au_iu_is1_dep_hit_b, + au_iu_is2_axubusy => au_iu_is2_axubusy, + iu_au_is1_hold => iu_au_is1_hold, + iu_au_is1_stall => iu_au_is1_stall_int, + xu_iu_slowspr_done => xu_iu_slowspr_done, + xu_iu_multdiv_done => xu_iu_multdiv_done, + xu_iu_loadmiss_vld => xu_iu_ex5_loadmiss_vld, + xu_iu_loadmiss_qentry => xu_iu_ex5_loadmiss_qentry, + xu_iu_loadmiss_target => xu_iu_ex5_loadmiss_target(1 to 6), + xu_iu_loadmiss_target_type => xu_iu_ex5_loadmiss_target_type(0), + xu_iu_complete_vld => xu_iu_complete_vld, + xu_iu_complete_qentry => xu_iu_complete_qentry, + xu_iu_complete_target_type => xu_iu_complete_target_type(0), + ic_fdep_load_quiesce => ic_fdep_load_quiesce, + iu_xu_quiesce => iu_xu_quiesce, + xu_iu_membar_tid => xu_iu_membar_tid, + xu_iu_set_barr_tid => xu_iu_set_barr_tid, + xu_iu_larx_done_tid => xu_iu_larx_done_tid, + an_ac_sync_ack => an_ac_sync_ack, + ic_fdep_icbi_ack => ic_fdep_icbi_ack, + an_ac_stcx_complete => an_ac_stcx_complete, + mm_iu_barrier_done => mm_iu_barrier_done, + spr_fdep_ll_hold => spr_fdep_ll_hold, + xu_iu_spr_ccr2_en_dcr => xu_iu_spr_ccr2_en_dcr, + xu_iu_is1_flush => is1_flush, + xu_iu_is2_flush => is2_flush, + xu_iu_rf0_flush => rf0_flush, + xu_iu_rf1_flush => xu_iu_rf1_flush, + xu_iu_ex1_flush => xu_iu_ex1_flush, + xu_iu_ex2_flush => xu_iu_ex2_flush, + xu_iu_ex3_flush => xu_iu_ex3_flush, + xu_iu_ex4_flush => xu_iu_ex4_flush, + xu_iu_ex5_flush => xu_iu_ex5_flush, + xu_iu_single_instr_mode => xu_iu_single_instr_mode); +dec0: entity work.iuq_axu_fu_dec +generic map(expand_type => expand_type) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + i_dec_si => siv(scan_axu_dec), + i_dec_so => sov(scan_axu_dec), + pc_iu_func_sl_thold_0_b => pc_iu_func_sl_thold_0_b, + pc_iu_sg_0 => pc_iu_sg_0, + forcee => forcee, + d_mode => d_mode, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + pc_au_ram_mode => pc_au_ram_mode, + pc_au_ram_thread_v => pc_au_ram_thread_v, + iu_au_ucode_restart => xu_iu_ucode_restart, + ifdp_ex5_fmul_uc_complete => ifdp_ex5_fmul_uc_complete, + i_afd_fmul_uc_is1 => i_afd_fmul_uc_is1, + iu_au_config_iucr => iu_au_config_iucr, + iu_au_is0_instr_v => iu_au_ib1_instr_vld, + iu_au_is0_instr => iu_au_ib1_instr0, + iu_au_is0_ucode_ext => iu_au_ib1_instr0_ucode_ext, + iu_au_is0_cr_setter => iu_au_is0_cr_setter, + iu_au_is1_stall => iu_au_is1_stall_int, + iu_au_is0_flush => ib1_flush, + iu_au_is1_flush => is1_flush, + au_iu_is0_i_dec_b => au_iu_i_dec_b, + au_iu_is0_to_ucode => au_iu_is0_to_ucode, + au_iu_is0_ucode_only => au_iu_is0_ucode_only, + iu_au_is0_is_ucode => iu_au_ib1_instr0_is_ucode, + iu_au_is0_2ucode => iu_au_ib1_instr0_2ucode, + au_iu_is0_ldst => au_iu_ib1_ldst, + au_iu_is0_ldst_v => au_iu_ib1_ldst_v, + au_iu_is0_st_v => au_iu_ib1_store, + au_iu_is0_ldst_size => au_iu_ib1_ldst_size, + au_iu_is0_ldst_tag => au_iu_ib1_ldst_tag, + au_iu_is0_ldst_ra => au_iu_ib1_ldst_ra, + au_iu_is0_ldst_ra_v => au_iu_ib1_ldst_ra_v, + au_iu_is0_ldst_rb => au_iu_ib1_ldst_rb, + au_iu_is0_ldst_rb_v => au_iu_ib1_ldst_rb_v, + au_iu_is0_ldst_dimm => au_iu_ib1_ldst_dimm, + au_iu_is0_ldst_indexed => au_iu_ib1_ldst_indexed, + au_iu_is0_ldst_update => au_iu_ib1_ldst_update, + au_iu_is0_ldst_extpid => au_iu_ib1_ldst_extpid, + au_iu_is0_ldst_forcealign => au_iu_ib1_ldst_forcealign, + au_iu_is0_ldst_forceexcept => au_iu_ib1_ldst_forceexcept, + au_iu_is0_mftgpr => au_iu_ib1_mftgpr, + au_iu_is0_mffgpr => au_iu_ib1_mffgpr, + au_iu_is0_movedp => au_iu_ib1_movedp, + au_iu_is0_instr_type => au_iu_ib1_instr_type, + i_afd_is1_cr_setter => i_afd_is1_cr_setter, + i_afd_is1_is_ucode => i_afd_is1_is_ucode, + i_afd_is1_to_ucode => i_afd_is1_to_ucode, + i_afd_is1_fra_v => i_afd_is1_fra_v, + i_afd_is1_frb_v => i_afd_is1_frb_v, + i_afd_is1_frc_v => i_afd_is1_frc_v, + i_afd_is1_frt_v => i_afd_is1_frt_v, + i_afd_is1_prebubble1 => i_afd_is1_prebubble1, + i_afd_is1_est_bubble3 => i_afd_is1_est_bubble3, + i_afd_is1_cr_writer => i_afd_is1_cr_writer, + i_afd_is1_fra => i_afd_is1_fra, + i_afd_is1_frb => i_afd_is1_frb, + i_afd_is1_frc => i_afd_is1_frc, + i_afd_is1_frt => i_afd_is1_frt, + i_afd_is1_instr_v => i_afd_is1_instr_v, + i_afd_is1_instr_ldst_v => i_afd_is1_instr_ldst_v, + i_afd_is1_instr_ld_v => i_afd_is1_instr_ld_v, + i_afd_ignore_flush_is1 => i_afd_ignore_flush_is1_int, + i_afd_in_ucode_mode_or1d => i_afd_in_ucode_mode_or1d, + i_afd_is1_fra_buf => i_afd_is1_fra_buf, + i_afd_is1_frb_buf => i_afd_is1_frb_buf, + i_afd_is1_frc_buf => i_afd_is1_frc_buf, + i_afd_is1_frt_buf => i_afd_is1_frt_buf, + i_afd_is1_divsqrt => i_afd_is1_divsqrt, + i_afd_is1_stall_rep => i_afd_is1_stall_rep, + i_afd_is1_instr_sto_v => i_afd_is1_instr_sto_v, + i_afd_config_iucr => i_afd_config_iucr, + fu_dec_debug => fu_dec_debug + ); +dep0: entity work.iuq_axu_fu_dep +generic map(expand_type => expand_type, + lmq_entries => lmq_entries) +port map ( + vdd => vdd, + gnd => gnd, + nclk => nclk, + i_dep_si => siv(scan_axu_dep), + i_dep_so => sov(scan_axu_dep), + pc_iu_func_sl_thold_0_b => pc_iu_func_sl_thold_0_b, + pc_iu_sg_0 => pc_iu_sg_0, + forcee => forcee, + d_mode => d_mode, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + ifdp_ex5_fmul_uc_complete => ifdp_ex5_fmul_uc_complete, + i_afd_fmul_uc_is1 => i_afd_fmul_uc_is1, + iu_fu_ex2_n_flush => iu_fu_ex2_n_flush, + fu_iu_uc_special => fu_iu_uc_special, + i_afd_is1_cr_setter => i_afd_is1_cr_setter, + i_afd_is1_is_ucode => i_afd_is1_is_ucode, + i_afd_is1_to_ucode => i_afd_is1_to_ucode, + i_afd_is2_is_ucode => i_afd_is2_is_ucode, + i_afd_is1_instr_v => i_afd_is1_instr_v, + i_afd_is1_instr => fdec_fdep_is1_instr(26 to 31), + i_afd_is1_fra_v => i_afd_is1_fra_v, + i_afd_is1_frb_v => i_afd_is1_frb_v, + i_afd_is1_frc_v => i_afd_is1_frc_v, + i_afd_is1_frt_v => i_afd_is1_frt_v, + i_afd_is1_prebubble1 => i_afd_is1_prebubble1, + i_afd_is1_est_bubble3 => i_afd_is1_est_bubble3, + iu_au_is1_cr_user_v => iu_au_is1_cr_user_v, + i_afd_is1_cr_writer => i_afd_is1_cr_writer, + i_afd_is1_fra => i_afd_is1_fra, + i_afd_is1_frb => i_afd_is1_frb, + i_afd_is1_frc => i_afd_is1_frc, + i_afd_is1_frt => i_afd_is1_frt, + i_afd_is1_ifar => fdec_fdep_is1_ifar(56 to 61), + i_afd_is1_instr_ldst_v => i_afd_is1_instr_ldst_v, + i_afd_is1_instr_ld_v => i_afd_is1_instr_ld_v, + i_afi_is2_take => i_afi_is2_take, + xu_au_loadmiss_vld => xu_iu_ex4_loadmiss_vld, + xu_au_loadmiss_qentry => xu_iu_ex4_loadmiss_qentry, + xu_au_loadmiss_target => xu_iu_ex4_loadmiss_target, + xu_au_loadmiss_target_type => xu_iu_ex4_loadmiss_target_type, + xu_au_loadmiss_complete_vld => xu_iu_complete_vld, + xu_au_loadmiss_complete_qentry => xu_iu_complete_qentry, + xu_au_loadmiss_complete_type => xu_iu_complete_target_type, + iu_au_is1_hold => iu_au_is1_hold, + iu_au_is1_instr_match => fdec_fdep_is1_match, + iu_au_is2_stall => iu_au_is2_stall, + xu_iu_is2_flush => xu_iu_flush, + iu_au_is1_flush => is1_flush, + iu_au_is2_flush => is2_flush, + iu_au_rf0_flush => xu_iu_flush, + iu_au_rf1_flush => xu_iu_rf1_flush, + iu_au_ex1_flush => xu_iu_ex1_flush, + iu_au_ex2_flush => xu_iu_ex2_flush, + iu_au_ex3_flush => xu_iu_ex3_flush, + iu_au_ex4_flush => xu_iu_ex4_flush, + iu_au_ex5_flush => xu_iu_ex5_flush, + au_iu_is1_dep_hit => au_iu_is1_dep_hit, + au_iu_is2_issue_stall => au_iu_issue_stall, + i_axu_is2_instr_v => i_axu_is2_instr_v, + i_axu_is1_early_v => i_axu_is1_early_v, + au_iu_is1_dep_hit_b => au_iu_is1_dep_hit_b, + i_axu_is2_instr_match => i_axu_is2_instr_match, + + i_axu_is2_fra => i_axu_is2_fra, + i_axu_is2_frb => i_axu_is2_frb, + i_axu_is2_frc => i_axu_is2_frc, + i_axu_is2_frt => i_axu_is2_frt, + i_axu_is2_fra_v => i_axu_is2_fra_v, + i_axu_is2_frb_v => i_axu_is2_frb_v, + i_axu_is2_frc_v => i_axu_is2_frc_v, + ifdp_is2_est_bubble3 => ifdp_is2_est_bubble3, + ifdp_is2_bypsel => ifdp_is2_bypsel, + i_afd_ignore_flush_is1 => i_afd_ignore_flush_is1_int, + i_afd_ignore_flush_is2 => i_afd_ignore_flush_is2, + au_iu_is2_axubusy => au_iu_is2_axubusy, + i_afd_in_ucode_mode_or1d => i_afd_in_ucode_mode_or1d, + i_afd_in_ucode_mode_or1d_b => i_afd_in_ucode_mode_or1d_b, + i_afd_is1_fra_buf => i_afd_is1_fra_buf, + i_afd_is1_frb_buf => i_afd_is1_frb_buf, + i_afd_is1_frc_buf => i_afd_is1_frc_buf, + i_afd_is1_frt_buf => i_afd_is1_frt_buf, + i_afd_is1_divsqrt => i_afd_is1_divsqrt, + i_afd_is1_stall_rep => i_afd_is1_stall_rep, + i_afd_is1_instr_sto_v => i_afd_is1_instr_sto_v, + i_afd_config_iucr => i_afd_config_iucr, + fu_dep_debug => fu_dep_debug + ); +axu_dbg_data(0 to 37) <= fu_dec_debug(0 to 13) & fu_dep_debug(0 to 23); +perv_2to1_reg: tri_plat + generic map (width => 2, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_iu_func_sl_thold_2, + din(1) => pc_iu_sg_2, + q(0) => pc_iu_func_sl_thold_1, + q(1) => pc_iu_sg_1); +perv_1to0_reg: tri_plat + generic map (width => 2, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_iu_func_sl_thold_1, + din(1) => pc_iu_sg_1, + q(0) => pc_iu_func_sl_thold_0, + q(1) => pc_iu_sg_0); +perv_lcbor: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_b, + thold => pc_iu_func_sl_thold_0, + sg => pc_iu_sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => pc_iu_func_sl_thold_0_b); +siv <= scan_in & sov(0 to scan_right-1); +scan_out <= sov(scan_right) and an_ac_scan_dis_dc_b; +end iuq_slice; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_slice_wrap.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_slice_wrap.vhdl new file mode 100644 index 0000000..b0421eb --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_slice_wrap.vhdl @@ -0,0 +1,1316 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; +use ieee.std_logic_1164.all; +library support; +use support.power_logic_pkg.all; +library work; +use work.iuq_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity iuq_slice_wrap is + generic(expand_type : integer := 2; + fpr_addr_width : integer := 5; + regmode : integer := 6; + a2mode : integer := 1; + lmq_entries : integer := 8); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + pc_iu_func_sl_thold_2 : in std_ulogic_vector(0 to 3); + pc_iu_sg_2 : in std_ulogic_vector(0 to 3); + clkoff_b : in std_ulogic_vector(0 to 3); + an_ac_scan_dis_dc_b : in std_ulogic_vector(0 to 3); + tc_ac_ccflush_dc : in std_ulogic; + delay_lclkr : in std_ulogic_vector(9 to 14); + mpw1_b : in std_ulogic_vector(9 to 14); + + iuq_s0_scan_in : in std_ulogic; + iuq_s0_scan_out : out std_ulogic; + iuq_s1_scan_in : in std_ulogic; + iuq_s1_scan_out : out std_ulogic; + iuq_s2_scan_in : in std_ulogic; + iuq_s2_scan_out : out std_ulogic; + iuq_s3_scan_in : in std_ulogic; + iuq_s3_scan_out : out std_ulogic; + pc_iu_ram_mode : in std_ulogic; + pc_iu_ram_thread : in std_ulogic_vector(0 to 1); + pc_iu_trace_bus_enable : in std_ulogic; + pc_iu_event_bus_enable : in std_ulogic; + fdep_dbg_data : out std_ulogic_vector(0 to 87); + fdep_perf_event_t0 : out std_ulogic_vector(0 to 11); + fdep_perf_event_t1 : out std_ulogic_vector(0 to 11); + fdep_perf_event_t2 : out std_ulogic_vector(0 to 11); + fdep_perf_event_t3 : out std_ulogic_vector(0 to 11); + iu_au_config_iucr_t0 : in std_ulogic_vector(0 to 7); + iu_au_config_iucr_t1 : in std_ulogic_vector(0 to 7); + iu_au_config_iucr_t2 : in std_ulogic_vector(0 to 7); + iu_au_config_iucr_t3 : in std_ulogic_vector(0 to 7); + spr_dec_mask_t0 : in std_ulogic_vector(0 to 31); + spr_dec_mask_t1 : in std_ulogic_vector(0 to 31); + spr_dec_mask_t2 : in std_ulogic_vector(0 to 31); + spr_dec_mask_t3 : in std_ulogic_vector(0 to 31); + spr_dec_match_t0 : in std_ulogic_vector(0 to 31); + spr_dec_match_t1 : in std_ulogic_vector(0 to 31); + spr_dec_match_t2 : in std_ulogic_vector(0 to 31); + spr_dec_match_t3 : in std_ulogic_vector(0 to 31); + uc_flush_tid : in std_ulogic_vector(0 to 3); + xu_iu_flush : in std_ulogic_vector(0 to 3); + xu_rf1_flush : in std_ulogic_vector(0 to 3); + xu_ex1_flush : in std_ulogic_vector(0 to 3); + xu_ex2_flush : in std_ulogic_vector(0 to 3); + xu_ex3_flush : in std_ulogic_vector(0 to 3); + xu_ex4_flush : in std_ulogic_vector(0 to 3); + xu_ex5_flush : in std_ulogic_vector(0 to 3); + fdec_ibuf_stall_t0 : out std_ulogic; + fdec_ibuf_stall_t1 : out std_ulogic; + fdec_ibuf_stall_t2 : out std_ulogic; + fdec_ibuf_stall_t3 : out std_ulogic; + iu_au_ib1_instr_vld_t0 : in std_ulogic; + iu_au_ib1_instr_vld_t1 : in std_ulogic; + iu_au_ib1_instr_vld_t2 : in std_ulogic; + iu_au_ib1_instr_vld_t3 : in std_ulogic; + iu_au_ib1_ifar_t0 : in EFF_IFAR; + iu_au_ib1_ifar_t1 : in EFF_IFAR; + iu_au_ib1_ifar_t2 : in EFF_IFAR; + iu_au_ib1_ifar_t3 : in EFF_IFAR; + iu_au_ib1_data_t0 : in std_ulogic_vector(0 to 49); + iu_au_ib1_data_t1 : in std_ulogic_vector(0 to 49); + iu_au_ib1_data_t2 : in std_ulogic_vector(0 to 49); + iu_au_ib1_data_t3 : in std_ulogic_vector(0 to 49); + xu_iu_ucode_restart : in std_ulogic_vector(0 to 3); + xu_iu_slowspr_done : in std_ulogic_vector(0 to 3); + xu_iu_multdiv_done : in std_ulogic_vector(0 to 3); + xu_iu_ex4_loadmiss_tid : in std_ulogic_vector(0 to 3); + xu_iu_ex4_loadmiss_qentry : in std_ulogic_vector(0 to lmq_entries-1); + xu_iu_ex4_loadmiss_target : in std_ulogic_vector(0 to 8); + xu_iu_ex4_loadmiss_target_type : in std_ulogic_vector(0 to 1); + xu_iu_ex5_loadmiss_tid : in std_ulogic_vector(0 to 3); + xu_iu_ex5_loadmiss_qentry : in std_ulogic_vector(0 to lmq_entries-1); + xu_iu_ex5_loadmiss_target : in std_ulogic_vector(1 to 6); + xu_iu_ex5_loadmiss_target_type : in std_ulogic_vector(0 to 0); + xu_iu_complete_tid : in std_ulogic_vector(0 to 3); + xu_iu_complete_qentry : in std_ulogic_vector(0 to lmq_entries-1); + xu_iu_complete_target_type : in std_ulogic_vector(0 to 1); + ic_fdep_load_quiesce : in std_ulogic_vector(0 to 3); + iu_xu_quiesce : out std_ulogic_vector(0 to 3); + xu_iu_membar_tid : in std_ulogic_vector(0 to 3); + xu_iu_set_barr_tid : in std_ulogic_vector(0 to 3); + xu_iu_larx_done_tid : in std_ulogic_vector(0 to 3); + an_ac_sync_ack : in std_ulogic_vector(0 to 3); + ic_fdep_icbi_ack : in std_ulogic_vector(0 to 3); + an_ac_stcx_complete : in std_ulogic_vector(0 to 3); + mm_iu_barrier_done : in std_ulogic_vector(0 to 3); + spr_fdep_ll_hold_t0 : in std_ulogic; + spr_fdep_ll_hold_t1 : in std_ulogic; + spr_fdep_ll_hold_t2 : in std_ulogic; + spr_fdep_ll_hold_t3 : in std_ulogic; + xu_iu_spr_ccr2_en_dcr : in std_ulogic; + xu_iu_single_instr_mode : in std_ulogic_vector(0 to 3); + fu_iu_uc_special : in std_ulogic_vector(0 to 3); + iu_fu_ex2_n_flush : out std_ulogic_vector(0 to 3); + axu_dbg_data_t0 : out std_ulogic_vector(0 to 37); + axu_dbg_data_t1 : out std_ulogic_vector(0 to 37); + axu_dbg_data_t2 : out std_ulogic_vector(0 to 37); + axu_dbg_data_t3 : out std_ulogic_vector(0 to 37); + + iuq_fi_scan_in : in std_ulogic; + iuq_fi_scan_out : out std_ulogic; + fiss_dbg_data : out std_ulogic_vector(0 to 87); + fiss_perf_event_t0 : out std_ulogic_vector(0 to 7); + fiss_perf_event_t1 : out std_ulogic_vector(0 to 7); + fiss_perf_event_t2 : out std_ulogic_vector(0 to 7); + fiss_perf_event_t3 : out std_ulogic_vector(0 to 7); + xu_iu_need_hole : in std_ulogic; + xu_iu_xucr0_rel : in std_ulogic; + an_ac_reld_data_vld_clone : in std_ulogic; + an_ac_reld_core_tag_clone : in std_ulogic_vector(1 to 4); + an_ac_reld_ditc_clone : in std_ulogic; + an_ac_reld_data_coming_clone : in std_ulogic; + an_ac_back_inv : in std_ulogic; + an_ac_back_inv_target : in std_ulogic_vector(1 to 1); + fiss_uc_is2_ucode_vld : out std_ulogic; + spr_issue_high_mask : in std_ulogic_vector(0 to 3); + spr_issue_med_mask : in std_ulogic_vector(0 to 3); + spr_fiss_count0_max : in std_ulogic_vector(0 to 5); + spr_fiss_count1_max : in std_ulogic_vector(0 to 5); + spr_fiss_count2_max : in std_ulogic_vector(0 to 5); + spr_fiss_count3_max : in std_ulogic_vector(0 to 5); + spr_fiss_pri_rand : in std_ulogic_vector(0 to 4); + spr_fiss_pri_rand_always : in std_ulogic; + spr_fiss_pri_rand_flush : in std_ulogic; + xu_iu_ex5_ppc_cpl : in std_ulogic_vector(0 to 3); + iu_xu_is2_vld_internal : out std_ulogic; + iu_xu_is2_tid_internal : out std_ulogic_vector(0 to 3); + iu_xu_is2_instr_internal : out std_ulogic_vector(0 to 31); + iu_xu_is2_ta_vld : out std_ulogic; + iu_xu_is2_ta : out std_ulogic_vector(0 to 5); + iu_xu_is2_s1_vld : out std_ulogic; + iu_xu_is2_s1 : out std_ulogic_vector(0 to 5); + iu_xu_is2_s2_vld : out std_ulogic; + iu_xu_is2_s2 : out std_ulogic_vector(0 to 5); + iu_xu_is2_s3_vld : out std_ulogic; + iu_xu_is2_s3 : out std_ulogic_vector(0 to 5); + iu_xu_is2_pred_update_internal : out std_ulogic; + iu_xu_is2_pred_taken_cnt_internal : out std_ulogic_vector(0 to 1); + iu_xu_is2_gshare : out std_ulogic_vector(0 to 3); + iu_xu_is2_ifar_internal : out eff_ifar; + iu_xu_is2_error_internal : out std_ulogic_vector(0 to 2); + iu_xu_is2_is_ucode : out std_ulogic; + iu_xu_is2_axu_ld_or_st : out std_ulogic; + iu_xu_is2_axu_store_internal : out std_ulogic; + iu_xu_is2_axu_ldst_indexed : out std_ulogic; + iu_xu_is2_axu_ldst_tag : out std_ulogic_vector(0 to 8); + iu_xu_is2_axu_ldst_size : out std_ulogic_vector(0 to 5); + iu_xu_is2_axu_ldst_update : out std_ulogic; + iu_xu_is2_axu_ldst_extpid : out std_ulogic; + iu_xu_is2_axu_ldst_forcealign : out std_ulogic; + iu_xu_is2_axu_ldst_forceexcept : out std_ulogic; + iu_xu_is2_axu_mftgpr : out std_ulogic; + iu_xu_is2_axu_mffgpr : out std_ulogic; + iu_xu_is2_axu_movedp : out std_ulogic; + iu_xu_is2_axu_instr_type : out std_ulogic_vector(0 to 2); + iu_xu_is2_match : out std_ulogic; + fiss_uc_is2_2ucode : out std_ulogic; + fiss_uc_is2_2ucode_type : out std_ulogic; + iu_fu_rf0_str_val : out std_ulogic; + iu_fu_rf0_ldst_val : out std_ulogic; + iu_fu_rf0_ldst_tid : out std_ulogic_vector(0 to 1); + iu_fu_rf0_ldst_tag : out std_ulogic_vector(0 to 8); + + iuq_ai_scan_in : in std_ulogic; + iuq_ai_scan_out : out std_ulogic; + iu_fu_is2_tid_decode : out std_ulogic_vector(0 to 3); + iu_fu_rf0_instr_match : out std_ulogic; + iu_fu_rf0_instr : out std_ulogic_vector(0 to 31); + iu_fu_rf0_instr_v : out std_ulogic; + iu_fu_rf0_is_ucode : out std_ulogic; + iu_fu_rf0_fra : out std_ulogic_vector(0 to 6); + iu_fu_rf0_frb : out std_ulogic_vector(0 to 6); + iu_fu_rf0_frc : out std_ulogic_vector(0 to 6); + iu_fu_rf0_frt : out std_ulogic_vector(0 to 6); + iu_fu_rf0_fra_v : out std_ulogic; + iu_fu_rf0_frb_v : out std_ulogic; + iu_fu_rf0_frc_v : out std_ulogic; + iu_fu_rf0_ucfmul : out std_ulogic; + fu_iss_dbg_data : out std_ulogic_vector(0 to 23); + iu_fu_rf0_tid : out std_ulogic_vector(0 to 1); + iu_fu_rf0_bypsel : out std_ulogic_vector(0 to 5); + iu_fu_rf0_ifar : out EFF_IFAR + +); +end iuq_slice_wrap; +architecture iuq_slice_wrap of iuq_slice_wrap is +signal fiss_fdep_is2_take0 : std_ulogic; +signal fdep_fiss_t0_is2_instr : std_ulogic_vector(0 to 31); +signal fdep_fiss_t0_is2_ta_vld : std_ulogic; +signal fdep_fiss_t0_is2_ta : std_ulogic_vector(0 to 5); +signal fdep_fiss_t0_is2_s1_vld : std_ulogic; +signal fdep_fiss_t0_is2_s1 : std_ulogic_vector(0 to 5); +signal fdep_fiss_t0_is2_s2_vld : std_ulogic; +signal fdep_fiss_t0_is2_s2 : std_ulogic_vector(0 to 5); +signal fdep_fiss_t0_is2_s3_vld : std_ulogic; +signal fdep_fiss_t0_is2_s3 : std_ulogic_vector(0 to 5); +signal fdep_fiss_t0_is2_pred_update : std_ulogic; +signal fdep_fiss_t0_is2_pred_taken_cnt : std_ulogic_vector(0 to 1); +signal fdep_fiss_t0_is2_gshare : std_ulogic_vector(0 to 3); +signal fdep_fiss_t0_is2_ifar : eff_ifar; +signal fdep_fiss_t0_is2_error : std_ulogic_vector(0 to 2); +signal fdep_fiss_t0_is2_axu_ld_or_st : std_ulogic; +signal fdep_fiss_t0_is2_axu_store : std_ulogic; +signal fdep_fiss_t0_is2_axu_ldst_size : std_ulogic_vector(0 to 5); +signal fdep_fiss_t0_is2_axu_ldst_tag : std_ulogic_vector(0 to 8); +signal fdep_fiss_t0_is2_axu_ldst_indexed : std_ulogic; +signal fdep_fiss_t0_is2_axu_ldst_update : std_ulogic; +signal fdep_fiss_t0_is2_axu_ldst_extpid : std_ulogic; +signal fdep_fiss_t0_is2_axu_ldst_forcealign : std_ulogic; +signal fdep_fiss_t0_is2_axu_ldst_forceexcept : std_ulogic; +signal fdep_fiss_t0_is2_axu_mftgpr : std_ulogic; +signal fdep_fiss_t0_is2_axu_mffgpr : std_ulogic; +signal fdep_fiss_t0_is2_axu_movedp : std_ulogic; +signal fdep_fiss_t0_is2_axu_instr_type : std_ulogic_vector(0 to 2); +signal fdep_fiss_t0_is2_match : std_ulogic; +signal fdep_fiss_t0_is2_2ucode : std_ulogic; +signal fdep_fiss_t0_is2_2ucode_type : std_ulogic; +signal fdep_fiss_t0_is2early_vld : std_ulogic; +signal fdep_fiss_t0_is1_xu_dep_hit_b : std_ulogic; +signal fdep_fiss_t0_is2_hole_delay : std_ulogic_vector(0 to 2); +signal fdep_fiss_t0_is2_to_ucode : std_ulogic; +signal fdep_fiss_t0_is2_is_ucode : std_ulogic; +signal fiss_fdep_is2_take1 : std_ulogic; +signal fdep_fiss_t1_is2_instr : std_ulogic_vector(0 to 31); +signal fdep_fiss_t1_is2_ta_vld : std_ulogic; +signal fdep_fiss_t1_is2_ta : std_ulogic_vector(0 to 5); +signal fdep_fiss_t1_is2_s1_vld : std_ulogic; +signal fdep_fiss_t1_is2_s1 : std_ulogic_vector(0 to 5); +signal fdep_fiss_t1_is2_s2_vld : std_ulogic; +signal fdep_fiss_t1_is2_s2 : std_ulogic_vector(0 to 5); +signal fdep_fiss_t1_is2_s3_vld : std_ulogic; +signal fdep_fiss_t1_is2_s3 : std_ulogic_vector(0 to 5); +signal fdep_fiss_t1_is2_pred_update : std_ulogic; +signal fdep_fiss_t1_is2_pred_taken_cnt : std_ulogic_vector(0 to 1); +signal fdep_fiss_t1_is2_gshare : std_ulogic_vector(0 to 3); +signal fdep_fiss_t1_is2_ifar : eff_ifar; +signal fdep_fiss_t1_is2_error : std_ulogic_vector(0 to 2); +signal fdep_fiss_t1_is2_axu_ld_or_st : std_ulogic; +signal fdep_fiss_t1_is2_axu_store : std_ulogic; +signal fdep_fiss_t1_is2_axu_ldst_size : std_ulogic_vector(0 to 5); +signal fdep_fiss_t1_is2_axu_ldst_tag : std_ulogic_vector(0 to 8); +signal fdep_fiss_t1_is2_axu_ldst_indexed : std_ulogic; +signal fdep_fiss_t1_is2_axu_ldst_update : std_ulogic; +signal fdep_fiss_t1_is2_axu_ldst_extpid : std_ulogic; +signal fdep_fiss_t1_is2_axu_ldst_forcealign : std_ulogic; +signal fdep_fiss_t1_is2_axu_ldst_forceexcept : std_ulogic; +signal fdep_fiss_t1_is2_axu_mftgpr : std_ulogic; +signal fdep_fiss_t1_is2_axu_mffgpr : std_ulogic; +signal fdep_fiss_t1_is2_axu_movedp : std_ulogic; +signal fdep_fiss_t1_is2_axu_instr_type : std_ulogic_vector(0 to 2); +signal fdep_fiss_t1_is2_match : std_ulogic; +signal fdep_fiss_t1_is2_2ucode : std_ulogic; +signal fdep_fiss_t1_is2_2ucode_type : std_ulogic; +signal fdep_fiss_t1_is2early_vld : std_ulogic; +signal fdep_fiss_t1_is1_xu_dep_hit_b : std_ulogic; +signal fdep_fiss_t1_is2_hole_delay : std_ulogic_vector(0 to 2); +signal fdep_fiss_t1_is2_to_ucode : std_ulogic; +signal fdep_fiss_t1_is2_is_ucode : std_ulogic; +signal fiss_fdep_is2_take2 : std_ulogic; +signal fdep_fiss_t2_is2_instr : std_ulogic_vector(0 to 31); +signal fdep_fiss_t2_is2_ta_vld : std_ulogic; +signal fdep_fiss_t2_is2_ta : std_ulogic_vector(0 to 5); +signal fdep_fiss_t2_is2_s1_vld : std_ulogic; +signal fdep_fiss_t2_is2_s1 : std_ulogic_vector(0 to 5); +signal fdep_fiss_t2_is2_s2_vld : std_ulogic; +signal fdep_fiss_t2_is2_s2 : std_ulogic_vector(0 to 5); +signal fdep_fiss_t2_is2_s3_vld : std_ulogic; +signal fdep_fiss_t2_is2_s3 : std_ulogic_vector(0 to 5); +signal fdep_fiss_t2_is2_pred_update : std_ulogic; +signal fdep_fiss_t2_is2_pred_taken_cnt : std_ulogic_vector(0 to 1); +signal fdep_fiss_t2_is2_gshare : std_ulogic_vector(0 to 3); +signal fdep_fiss_t2_is2_ifar : eff_ifar; +signal fdep_fiss_t2_is2_error : std_ulogic_vector(0 to 2); +signal fdep_fiss_t2_is2_axu_ld_or_st : std_ulogic; +signal fdep_fiss_t2_is2_axu_store : std_ulogic; +signal fdep_fiss_t2_is2_axu_ldst_size : std_ulogic_vector(0 to 5); +signal fdep_fiss_t2_is2_axu_ldst_tag : std_ulogic_vector(0 to 8); +signal fdep_fiss_t2_is2_axu_ldst_indexed : std_ulogic; +signal fdep_fiss_t2_is2_axu_ldst_update : std_ulogic; +signal fdep_fiss_t2_is2_axu_ldst_extpid : std_ulogic; +signal fdep_fiss_t2_is2_axu_ldst_forcealign : std_ulogic; +signal fdep_fiss_t2_is2_axu_ldst_forceexcept : std_ulogic; +signal fdep_fiss_t2_is2_axu_mftgpr : std_ulogic; +signal fdep_fiss_t2_is2_axu_mffgpr : std_ulogic; +signal fdep_fiss_t2_is2_axu_movedp : std_ulogic; +signal fdep_fiss_t2_is2_axu_instr_type : std_ulogic_vector(0 to 2); +signal fdep_fiss_t2_is2_match : std_ulogic; +signal fdep_fiss_t2_is2_2ucode : std_ulogic; +signal fdep_fiss_t2_is2_2ucode_type : std_ulogic; +signal fdep_fiss_t2_is2early_vld : std_ulogic; +signal fdep_fiss_t2_is1_xu_dep_hit_b : std_ulogic; +signal fdep_fiss_t2_is2_hole_delay : std_ulogic_vector(0 to 2); +signal fdep_fiss_t2_is2_to_ucode : std_ulogic; +signal fdep_fiss_t2_is2_is_ucode : std_ulogic; +signal fiss_fdep_is2_take3 : std_ulogic; +signal fdep_fiss_t3_is2_instr : std_ulogic_vector(0 to 31); +signal fdep_fiss_t3_is2_ta_vld : std_ulogic; +signal fdep_fiss_t3_is2_ta : std_ulogic_vector(0 to 5); +signal fdep_fiss_t3_is2_s1_vld : std_ulogic; +signal fdep_fiss_t3_is2_s1 : std_ulogic_vector(0 to 5); +signal fdep_fiss_t3_is2_s2_vld : std_ulogic; +signal fdep_fiss_t3_is2_s2 : std_ulogic_vector(0 to 5); +signal fdep_fiss_t3_is2_s3_vld : std_ulogic; +signal fdep_fiss_t3_is2_s3 : std_ulogic_vector(0 to 5); +signal fdep_fiss_t3_is2_pred_update : std_ulogic; +signal fdep_fiss_t3_is2_pred_taken_cnt : std_ulogic_vector(0 to 1); +signal fdep_fiss_t3_is2_gshare : std_ulogic_vector(0 to 3); +signal fdep_fiss_t3_is2_ifar : eff_ifar; +signal fdep_fiss_t3_is2_error : std_ulogic_vector(0 to 2); +signal fdep_fiss_t3_is2_axu_ld_or_st : std_ulogic; +signal fdep_fiss_t3_is2_axu_store : std_ulogic; +signal fdep_fiss_t3_is2_axu_ldst_size : std_ulogic_vector(0 to 5); +signal fdep_fiss_t3_is2_axu_ldst_tag : std_ulogic_vector(0 to 8); +signal fdep_fiss_t3_is2_axu_ldst_indexed : std_ulogic; +signal fdep_fiss_t3_is2_axu_ldst_update : std_ulogic; +signal fdep_fiss_t3_is2_axu_ldst_extpid : std_ulogic; +signal fdep_fiss_t3_is2_axu_ldst_forcealign : std_ulogic; +signal fdep_fiss_t3_is2_axu_ldst_forceexcept : std_ulogic; +signal fdep_fiss_t3_is2_axu_mftgpr : std_ulogic; +signal fdep_fiss_t3_is2_axu_mffgpr : std_ulogic; +signal fdep_fiss_t3_is2_axu_movedp : std_ulogic; +signal fdep_fiss_t3_is2_axu_instr_type : std_ulogic_vector(0 to 2); +signal fdep_fiss_t3_is2_match : std_ulogic; +signal fdep_fiss_t3_is2_2ucode : std_ulogic; +signal fdep_fiss_t3_is2_2ucode_type : std_ulogic; +signal fdep_fiss_t3_is2early_vld : std_ulogic; +signal fdep_fiss_t3_is1_xu_dep_hit_b : std_ulogic; +signal fdep_fiss_t3_is2_hole_delay : std_ulogic_vector(0 to 2); +signal fdep_fiss_t3_is2_to_ucode : std_ulogic; +signal fdep_fiss_t3_is2_is_ucode : std_ulogic; +signal i_afi_is2_take_t : std_ulogic_vector(0 to 3); +signal i_axu_is1_dep_hit_t0_b : std_ulogic; +signal i_axu_is2_instr_match_t0 : std_ulogic; +signal i_afd_is2_t0_instr_v : std_ulogic; +signal i_axu_is1_early_v_t0 : std_ulogic; +signal i_afd_is2_fra_t0 : std_ulogic_vector(0 to 6); +signal i_afd_is2_frb_t0 : std_ulogic_vector(0 to 6); +signal i_afd_is2_frc_t0 : std_ulogic_vector(0 to 6); +signal i_afd_is2_frt_t0 : std_ulogic_vector(0 to 6); +signal i_afd_is2_fra_v_t0 : std_ulogic; +signal i_afd_is2_frb_v_t0 : std_ulogic; +signal i_afd_is2_frc_v_t0 : std_ulogic; +signal ifdp_is2_est_bubble3_t0 : std_ulogic; +signal i_afd_is2_is_ucode_t0 : std_ulogic; +signal i_afd_ignore_flush_is2_t0 : std_ulogic; +signal i_afd_in_ucode_mode_or1d_b_t0 : std_ulogic; +signal i_axu_is1_dep_hit_t1_b : std_ulogic; +signal i_axu_is2_instr_match_t1 : std_ulogic; +signal i_afd_is2_t1_instr_v : std_ulogic; +signal i_axu_is1_early_v_t1 : std_ulogic; +signal i_afd_is2_fra_t1 : std_ulogic_vector(0 to 6); +signal i_afd_is2_frb_t1 : std_ulogic_vector(0 to 6); +signal i_afd_is2_frc_t1 : std_ulogic_vector(0 to 6); +signal i_afd_is2_frt_t1 : std_ulogic_vector(0 to 6); +signal i_afd_is2_fra_v_t1 : std_ulogic; +signal i_afd_is2_frb_v_t1 : std_ulogic; +signal i_afd_is2_frc_v_t1 : std_ulogic; +signal ifdp_is2_est_bubble3_t1 : std_ulogic; +signal i_afd_is2_is_ucode_t1 : std_ulogic; +signal i_afd_ignore_flush_is2_t1 : std_ulogic; +signal i_afd_in_ucode_mode_or1d_b_t1 : std_ulogic; +signal i_axu_is1_dep_hit_t2_b : std_ulogic; +signal i_axu_is2_instr_match_t2 : std_ulogic; +signal i_afd_is2_t2_instr_v : std_ulogic; +signal i_axu_is1_early_v_t2 : std_ulogic; +signal i_afd_is2_fra_t2 : std_ulogic_vector(0 to 6); +signal i_afd_is2_frb_t2 : std_ulogic_vector(0 to 6); +signal i_afd_is2_frc_t2 : std_ulogic_vector(0 to 6); +signal i_afd_is2_frt_t2 : std_ulogic_vector(0 to 6); +signal i_afd_is2_fra_v_t2 : std_ulogic; +signal i_afd_is2_frb_v_t2 : std_ulogic; +signal i_afd_is2_frc_v_t2 : std_ulogic; +signal ifdp_is2_est_bubble3_t2 : std_ulogic; +signal i_afd_is2_is_ucode_t2 : std_ulogic; +signal i_afd_ignore_flush_is2_t2 : std_ulogic; +signal i_afd_in_ucode_mode_or1d_b_t2 : std_ulogic; +signal i_axu_is1_dep_hit_t3_b : std_ulogic; +signal i_axu_is2_instr_match_t3 : std_ulogic; +signal i_afd_is2_t3_instr_v : std_ulogic; +signal i_axu_is1_early_v_t3 : std_ulogic; +signal i_afd_is2_fra_t3 : std_ulogic_vector(0 to 6); +signal i_afd_is2_frb_t3 : std_ulogic_vector(0 to 6); +signal i_afd_is2_frc_t3 : std_ulogic_vector(0 to 6); +signal i_afd_is2_frt_t3 : std_ulogic_vector(0 to 6); +signal i_afd_is2_fra_v_t3 : std_ulogic; +signal i_afd_is2_frb_v_t3 : std_ulogic; +signal i_afd_is2_frc_v_t3 : std_ulogic; +signal ifdp_is2_est_bubble3_t3 : std_ulogic; +signal i_afd_is2_is_ucode_t3 : std_ulogic; +signal i_afd_ignore_flush_is2_t3 : std_ulogic; +signal i_afd_in_ucode_mode_or1d_b_t3 : std_ulogic; +signal i_afd_is2_bypsel_t0 : std_ulogic_vector(0 to 5); +signal i_afd_is2_bypsel_t1 : std_ulogic_vector(0 to 5); +signal i_afd_is2_bypsel_t2 : std_ulogic_vector(0 to 5); +signal i_afd_is2_bypsel_t3 : std_ulogic_vector(0 to 5); +signal iu_au_hi_pri_mask : std_ulogic_vector(0 to 3); +signal iu_au_md_pri_mask : std_ulogic_vector(0 to 3); +signal slice_id0 : std_ulogic_vector(0 to 1); +signal slice_id1 : std_ulogic_vector(0 to 1); +signal slice_id2 : std_ulogic_vector(0 to 1); +signal slice_id3 : std_ulogic_vector(0 to 1); +signal iu_au_config_iucr_pt_t0 : std_ulogic_vector(2 to 4); +signal iu_au_config_iucr_pt_t1 : std_ulogic_vector(2 to 4); +signal iu_au_config_iucr_pt_t2 : std_ulogic_vector(2 to 4); +signal iu_au_config_iucr_pt_t3 : std_ulogic_vector(2 to 4); +begin +iuq_slice0 : entity work.iuq_slice +generic map(expand_type => expand_type, + regmode => regmode, + a2mode => a2mode, + lmq_entries => lmq_entries) +port map( + slice_id => slice_id0, + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_iu_func_sl_thold_2 => pc_iu_func_sl_thold_2(0), + pc_iu_sg_2 => pc_iu_sg_2(0), + clkoff_b => clkoff_b(0), + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b(0), + tc_ac_ccflush_dc => tc_ac_ccflush_dc, + delay_lclkr => delay_lclkr(10+0), + mpw1_b => mpw1_b(10+0), + scan_in => iuq_s0_scan_in, + scan_out => iuq_s0_scan_out, + pc_iu_ram_mode => pc_iu_ram_mode, + pc_iu_ram_thread => pc_iu_ram_thread, + pc_iu_trace_bus_enable => pc_iu_trace_bus_enable, + pc_iu_event_bus_enable => pc_iu_event_bus_enable, + fdep_dbg_data => fdep_dbg_data(22*0 to 22*0+21), + fdep_perf_event => fdep_perf_event_t0, + iu_au_config_iucr => iu_au_config_iucr_t0, + iu_au_config_iucr_pt => iu_au_config_iucr_pt_t0, + spr_dec_mask => spr_dec_mask_t0, + spr_dec_match => spr_dec_match_t0, + uc_flush => uc_flush_tid(0), + xu_iu_flush => xu_iu_flush(0), + xu_iu_rf1_flush => xu_rf1_flush(0), + xu_iu_ex1_flush => xu_ex1_flush(0), + xu_iu_ex2_flush => xu_ex2_flush(0), + xu_iu_ex3_flush => xu_ex3_flush(0), + xu_iu_ex4_flush => xu_ex4_flush(0), + xu_iu_ex5_flush => xu_ex5_flush(0), + fdec_ibuf_stall => fdec_ibuf_stall_t0, + iu_au_ib1_instr_vld => iu_au_ib1_instr_vld_t0, + iu_au_ib1_ifar => iu_au_ib1_ifar_t0, + iu_au_ib1_data => iu_au_ib1_data_t0, + xu_iu_ucode_restart => xu_iu_ucode_restart(0), + xu_iu_slowspr_done => xu_iu_slowspr_done(0), + xu_iu_multdiv_done => xu_iu_multdiv_done(0), + xu_iu_ex4_loadmiss_vld => xu_iu_ex4_loadmiss_tid(0), + xu_iu_ex4_loadmiss_qentry => xu_iu_ex4_loadmiss_qentry, + xu_iu_ex4_loadmiss_target => xu_iu_ex4_loadmiss_target, + xu_iu_ex4_loadmiss_target_type => xu_iu_ex4_loadmiss_target_type, + xu_iu_ex5_loadmiss_vld => xu_iu_ex5_loadmiss_tid(0), + xu_iu_ex5_loadmiss_qentry => xu_iu_ex5_loadmiss_qentry, + xu_iu_ex5_loadmiss_target => xu_iu_ex5_loadmiss_target(1 to 6), + xu_iu_ex5_loadmiss_target_type => xu_iu_ex5_loadmiss_target_type(0 to 0), + xu_iu_complete_vld => xu_iu_complete_tid(0), + xu_iu_complete_qentry => xu_iu_complete_qentry, + xu_iu_complete_target_type => xu_iu_complete_target_type, + ic_fdep_load_quiesce => ic_fdep_load_quiesce(0), + iu_xu_quiesce => iu_xu_quiesce(0), + xu_iu_membar_tid => xu_iu_membar_tid(0), + xu_iu_set_barr_tid => xu_iu_set_barr_tid(0), + xu_iu_larx_done_tid => xu_iu_larx_done_tid(0), + an_ac_sync_ack => an_ac_sync_ack(0), + ic_fdep_icbi_ack => ic_fdep_icbi_ack(0), + an_ac_stcx_complete => an_ac_stcx_complete(0), + mm_iu_barrier_done => mm_iu_barrier_done(0), + spr_fdep_ll_hold => spr_fdep_ll_hold_t0, + xu_iu_spr_ccr2_en_dcr => xu_iu_spr_ccr2_en_dcr, + xu_iu_single_instr_mode => xu_iu_single_instr_mode(0), + fiss_fdep_is2_take => fiss_fdep_is2_take0, + fdep_fiss_is2_instr => fdep_fiss_t0_is2_instr, + fdep_fiss_is2_ta_vld => fdep_fiss_t0_is2_ta_vld, + fdep_fiss_is2_ta => fdep_fiss_t0_is2_ta, + fdep_fiss_is2_s1_vld => fdep_fiss_t0_is2_s1_vld, + fdep_fiss_is2_s1 => fdep_fiss_t0_is2_s1, + fdep_fiss_is2_s2_vld => fdep_fiss_t0_is2_s2_vld, + fdep_fiss_is2_s2 => fdep_fiss_t0_is2_s2, + fdep_fiss_is2_s3_vld => fdep_fiss_t0_is2_s3_vld, + fdep_fiss_is2_s3 => fdep_fiss_t0_is2_s3, + fdep_fiss_is2_pred_update => fdep_fiss_t0_is2_pred_update, + fdep_fiss_is2_pred_taken_cnt => fdep_fiss_t0_is2_pred_taken_cnt, + fdep_fiss_is2_gshare => fdep_fiss_t0_is2_gshare, + fdep_fiss_is2_ifar => fdep_fiss_t0_is2_ifar, + fdep_fiss_is2_error => fdep_fiss_t0_is2_error, + fdep_fiss_is2_axu_ld_or_st => fdep_fiss_t0_is2_axu_ld_or_st, + fdep_fiss_is2_axu_store => fdep_fiss_t0_is2_axu_store, + fdep_fiss_is2_axu_ldst_size => fdep_fiss_t0_is2_axu_ldst_size, + fdep_fiss_is2_axu_ldst_tag => fdep_fiss_t0_is2_axu_ldst_tag, + fdep_fiss_is2_axu_ldst_indexed => fdep_fiss_t0_is2_axu_ldst_indexed, + fdep_fiss_is2_axu_ldst_update => fdep_fiss_t0_is2_axu_ldst_update, + fdep_fiss_is2_axu_ldst_extpid => fdep_fiss_t0_is2_axu_ldst_extpid, + fdep_fiss_is2_axu_ldst_forcealign => fdep_fiss_t0_is2_axu_ldst_forcealign, + fdep_fiss_is2_axu_ldst_forceexcept => fdep_fiss_t0_is2_axu_ldst_forceexcept, + fdep_fiss_is2_axu_mftgpr => fdep_fiss_t0_is2_axu_mftgpr, + fdep_fiss_is2_axu_mffgpr => fdep_fiss_t0_is2_axu_mffgpr, + fdep_fiss_is2_axu_movedp => fdep_fiss_t0_is2_axu_movedp, + fdep_fiss_is2_axu_instr_type => fdep_fiss_t0_is2_axu_instr_type, + fdep_fiss_is2_match => fdep_fiss_t0_is2_match, + fdep_fiss_is2_2ucode => fdep_fiss_t0_is2_2ucode, + fdep_fiss_is2_2ucode_type => fdep_fiss_t0_is2_2ucode_type, + fdep_fiss_is2early_vld => fdep_fiss_t0_is2early_vld, + fdep_fiss_is1_xu_dep_hit_b => fdep_fiss_t0_is1_xu_dep_hit_b, + fdep_fiss_is2_hole_delay => fdep_fiss_t0_is2_hole_delay, + fdep_fiss_is2_to_ucode => fdep_fiss_t0_is2_to_ucode, + fdep_fiss_is2_is_ucode => fdep_fiss_t0_is2_is_ucode, + fu_iu_uc_special => fu_iu_uc_special(0), + iu_fu_ex2_n_flush => iu_fu_ex2_n_flush(0), + i_afi_is2_take => i_afi_is2_take_t(0), + i_axu_is1_dep_hit_b => i_axu_is1_dep_hit_t0_b, + i_axu_is2_instr_v => i_afd_is2_t0_instr_v, + i_axu_is1_early_v => i_axu_is1_early_v_t0, + i_axu_is2_instr_match => i_axu_is2_instr_match_t0, + i_axu_is2_fra => i_afd_is2_fra_t0, + i_axu_is2_frb => i_afd_is2_frb_t0, + i_axu_is2_frc => i_afd_is2_frc_t0, + i_axu_is2_frt => i_afd_is2_frt_t0, + i_axu_is2_fra_v => i_afd_is2_fra_v_t0, + i_axu_is2_frb_v => i_afd_is2_frb_v_t0, + i_axu_is2_frc_v => i_afd_is2_frc_v_t0, + i_afd_is2_is_ucode => i_afd_is2_is_ucode_t0, + i_afd_ignore_flush_is2 => i_afd_ignore_flush_is2_t0, + i_afd_in_ucode_mode_or1d_b => i_afd_in_ucode_mode_or1d_b_t0, + ifdp_is2_est_bubble3 => ifdp_is2_est_bubble3_t0, + ifdp_is2_bypsel => i_afd_is2_bypsel_t0, + axu_dbg_data => axu_dbg_data_t0 +); +iuq_slice1 : entity work.iuq_slice +generic map(expand_type => expand_type, + regmode => regmode, + a2mode => a2mode, + lmq_entries => lmq_entries) +port map( + slice_id => slice_id1, + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_iu_func_sl_thold_2 => pc_iu_func_sl_thold_2(1), + pc_iu_sg_2 => pc_iu_sg_2(1), + clkoff_b => clkoff_b(1), + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b(1), + tc_ac_ccflush_dc => tc_ac_ccflush_dc, + delay_lclkr => delay_lclkr(10+1), + mpw1_b => mpw1_b(10+1), + scan_in => iuq_s1_scan_in, + scan_out => iuq_s1_scan_out, + pc_iu_ram_mode => pc_iu_ram_mode, + pc_iu_ram_thread => pc_iu_ram_thread, + pc_iu_trace_bus_enable => pc_iu_trace_bus_enable, + pc_iu_event_bus_enable => pc_iu_event_bus_enable, + fdep_dbg_data => fdep_dbg_data(22*1 to 22*1+21), + fdep_perf_event => fdep_perf_event_t1, + iu_au_config_iucr => iu_au_config_iucr_t1, + iu_au_config_iucr_pt => iu_au_config_iucr_pt_t1, + spr_dec_mask => spr_dec_mask_t1, + spr_dec_match => spr_dec_match_t1, + uc_flush => uc_flush_tid(1), + xu_iu_flush => xu_iu_flush(1), + xu_iu_rf1_flush => xu_rf1_flush(1), + xu_iu_ex1_flush => xu_ex1_flush(1), + xu_iu_ex2_flush => xu_ex2_flush(1), + xu_iu_ex3_flush => xu_ex3_flush(1), + xu_iu_ex4_flush => xu_ex4_flush(1), + xu_iu_ex5_flush => xu_ex5_flush(1), + fdec_ibuf_stall => fdec_ibuf_stall_t1, + iu_au_ib1_instr_vld => iu_au_ib1_instr_vld_t1, + iu_au_ib1_ifar => iu_au_ib1_ifar_t1, + iu_au_ib1_data => iu_au_ib1_data_t1, + xu_iu_ucode_restart => xu_iu_ucode_restart(1), + xu_iu_slowspr_done => xu_iu_slowspr_done(1), + xu_iu_multdiv_done => xu_iu_multdiv_done(1), + xu_iu_ex4_loadmiss_vld => xu_iu_ex4_loadmiss_tid(1), + xu_iu_ex4_loadmiss_qentry => xu_iu_ex4_loadmiss_qentry, + xu_iu_ex4_loadmiss_target => xu_iu_ex4_loadmiss_target, + xu_iu_ex4_loadmiss_target_type => xu_iu_ex4_loadmiss_target_type, + xu_iu_ex5_loadmiss_vld => xu_iu_ex5_loadmiss_tid(1), + xu_iu_ex5_loadmiss_qentry => xu_iu_ex5_loadmiss_qentry, + xu_iu_ex5_loadmiss_target => xu_iu_ex5_loadmiss_target(1 to 6), + xu_iu_ex5_loadmiss_target_type => xu_iu_ex5_loadmiss_target_type(0 to 0), + xu_iu_complete_vld => xu_iu_complete_tid(1), + xu_iu_complete_qentry => xu_iu_complete_qentry, + xu_iu_complete_target_type => xu_iu_complete_target_type, + ic_fdep_load_quiesce => ic_fdep_load_quiesce(1), + iu_xu_quiesce => iu_xu_quiesce(1), + xu_iu_membar_tid => xu_iu_membar_tid(1), + xu_iu_set_barr_tid => xu_iu_set_barr_tid(1), + xu_iu_larx_done_tid => xu_iu_larx_done_tid(1), + an_ac_sync_ack => an_ac_sync_ack(1), + ic_fdep_icbi_ack => ic_fdep_icbi_ack(1), + an_ac_stcx_complete => an_ac_stcx_complete(1), + mm_iu_barrier_done => mm_iu_barrier_done(1), + spr_fdep_ll_hold => spr_fdep_ll_hold_t1, + xu_iu_spr_ccr2_en_dcr => xu_iu_spr_ccr2_en_dcr, + xu_iu_single_instr_mode => xu_iu_single_instr_mode(1), + fiss_fdep_is2_take => fiss_fdep_is2_take1, + fdep_fiss_is2_instr => fdep_fiss_t1_is2_instr, + fdep_fiss_is2_ta_vld => fdep_fiss_t1_is2_ta_vld, + fdep_fiss_is2_ta => fdep_fiss_t1_is2_ta, + fdep_fiss_is2_s1_vld => fdep_fiss_t1_is2_s1_vld, + fdep_fiss_is2_s1 => fdep_fiss_t1_is2_s1, + fdep_fiss_is2_s2_vld => fdep_fiss_t1_is2_s2_vld, + fdep_fiss_is2_s2 => fdep_fiss_t1_is2_s2, + fdep_fiss_is2_s3_vld => fdep_fiss_t1_is2_s3_vld, + fdep_fiss_is2_s3 => fdep_fiss_t1_is2_s3, + fdep_fiss_is2_pred_update => fdep_fiss_t1_is2_pred_update, + fdep_fiss_is2_pred_taken_cnt => fdep_fiss_t1_is2_pred_taken_cnt, + fdep_fiss_is2_gshare => fdep_fiss_t1_is2_gshare, + fdep_fiss_is2_ifar => fdep_fiss_t1_is2_ifar, + fdep_fiss_is2_error => fdep_fiss_t1_is2_error, + fdep_fiss_is2_axu_ld_or_st => fdep_fiss_t1_is2_axu_ld_or_st, + fdep_fiss_is2_axu_store => fdep_fiss_t1_is2_axu_store, + fdep_fiss_is2_axu_ldst_size => fdep_fiss_t1_is2_axu_ldst_size, + fdep_fiss_is2_axu_ldst_tag => fdep_fiss_t1_is2_axu_ldst_tag, + fdep_fiss_is2_axu_ldst_indexed => fdep_fiss_t1_is2_axu_ldst_indexed, + fdep_fiss_is2_axu_ldst_update => fdep_fiss_t1_is2_axu_ldst_update, + fdep_fiss_is2_axu_ldst_extpid => fdep_fiss_t1_is2_axu_ldst_extpid, + fdep_fiss_is2_axu_ldst_forcealign => fdep_fiss_t1_is2_axu_ldst_forcealign, + fdep_fiss_is2_axu_ldst_forceexcept => fdep_fiss_t1_is2_axu_ldst_forceexcept, + fdep_fiss_is2_axu_mftgpr => fdep_fiss_t1_is2_axu_mftgpr, + fdep_fiss_is2_axu_mffgpr => fdep_fiss_t1_is2_axu_mffgpr, + fdep_fiss_is2_axu_movedp => fdep_fiss_t1_is2_axu_movedp, + fdep_fiss_is2_axu_instr_type => fdep_fiss_t1_is2_axu_instr_type, + fdep_fiss_is2_match => fdep_fiss_t1_is2_match, + fdep_fiss_is2_2ucode => fdep_fiss_t1_is2_2ucode, + fdep_fiss_is2_2ucode_type => fdep_fiss_t1_is2_2ucode_type, + fdep_fiss_is2early_vld => fdep_fiss_t1_is2early_vld, + fdep_fiss_is1_xu_dep_hit_b => fdep_fiss_t1_is1_xu_dep_hit_b, + fdep_fiss_is2_hole_delay => fdep_fiss_t1_is2_hole_delay, + fdep_fiss_is2_to_ucode => fdep_fiss_t1_is2_to_ucode, + fdep_fiss_is2_is_ucode => fdep_fiss_t1_is2_is_ucode, + fu_iu_uc_special => fu_iu_uc_special(1), + iu_fu_ex2_n_flush => iu_fu_ex2_n_flush(1), + i_afi_is2_take => i_afi_is2_take_t(1), + i_axu_is1_dep_hit_b => i_axu_is1_dep_hit_t1_b, + i_axu_is2_instr_v => i_afd_is2_t1_instr_v, + i_axu_is1_early_v => i_axu_is1_early_v_t1, + i_axu_is2_instr_match => i_axu_is2_instr_match_t1, + i_axu_is2_fra => i_afd_is2_fra_t1, + i_axu_is2_frb => i_afd_is2_frb_t1, + i_axu_is2_frc => i_afd_is2_frc_t1, + i_axu_is2_frt => i_afd_is2_frt_t1, + i_axu_is2_fra_v => i_afd_is2_fra_v_t1, + i_axu_is2_frb_v => i_afd_is2_frb_v_t1, + i_axu_is2_frc_v => i_afd_is2_frc_v_t1, + i_afd_is2_is_ucode => i_afd_is2_is_ucode_t1, + i_afd_ignore_flush_is2 => i_afd_ignore_flush_is2_t1, + i_afd_in_ucode_mode_or1d_b => i_afd_in_ucode_mode_or1d_b_t1, + ifdp_is2_est_bubble3 => ifdp_is2_est_bubble3_t1, + ifdp_is2_bypsel => i_afd_is2_bypsel_t1, + axu_dbg_data => axu_dbg_data_t1 +); +iuq_slice2 : entity work.iuq_slice +generic map(expand_type => expand_type, + regmode => regmode, + a2mode => a2mode, + lmq_entries => lmq_entries) +port map( + slice_id => slice_id2, + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_iu_func_sl_thold_2 => pc_iu_func_sl_thold_2(2), + pc_iu_sg_2 => pc_iu_sg_2(2), + clkoff_b => clkoff_b(2), + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b(2), + tc_ac_ccflush_dc => tc_ac_ccflush_dc, + delay_lclkr => delay_lclkr(10+2), + mpw1_b => mpw1_b(10+2), + scan_in => iuq_s2_scan_in, + scan_out => iuq_s2_scan_out, + pc_iu_ram_mode => pc_iu_ram_mode, + pc_iu_ram_thread => pc_iu_ram_thread, + pc_iu_trace_bus_enable => pc_iu_trace_bus_enable, + pc_iu_event_bus_enable => pc_iu_event_bus_enable, + fdep_dbg_data => fdep_dbg_data(22*2 to 22*2+21), + fdep_perf_event => fdep_perf_event_t2, + iu_au_config_iucr => iu_au_config_iucr_t2, + iu_au_config_iucr_pt => iu_au_config_iucr_pt_t2, + spr_dec_mask => spr_dec_mask_t2, + spr_dec_match => spr_dec_match_t2, + uc_flush => uc_flush_tid(2), + xu_iu_flush => xu_iu_flush(2), + xu_iu_rf1_flush => xu_rf1_flush(2), + xu_iu_ex1_flush => xu_ex1_flush(2), + xu_iu_ex2_flush => xu_ex2_flush(2), + xu_iu_ex3_flush => xu_ex3_flush(2), + xu_iu_ex4_flush => xu_ex4_flush(2), + xu_iu_ex5_flush => xu_ex5_flush(2), + fdec_ibuf_stall => fdec_ibuf_stall_t2, + iu_au_ib1_instr_vld => iu_au_ib1_instr_vld_t2, + iu_au_ib1_ifar => iu_au_ib1_ifar_t2, + iu_au_ib1_data => iu_au_ib1_data_t2, + xu_iu_ucode_restart => xu_iu_ucode_restart(2), + xu_iu_slowspr_done => xu_iu_slowspr_done(2), + xu_iu_multdiv_done => xu_iu_multdiv_done(2), + xu_iu_ex4_loadmiss_vld => xu_iu_ex4_loadmiss_tid(2), + xu_iu_ex4_loadmiss_qentry => xu_iu_ex4_loadmiss_qentry, + xu_iu_ex4_loadmiss_target => xu_iu_ex4_loadmiss_target, + xu_iu_ex4_loadmiss_target_type => xu_iu_ex4_loadmiss_target_type, + xu_iu_ex5_loadmiss_vld => xu_iu_ex5_loadmiss_tid(2), + xu_iu_ex5_loadmiss_qentry => xu_iu_ex5_loadmiss_qentry, + xu_iu_ex5_loadmiss_target => xu_iu_ex5_loadmiss_target(1 to 6), + xu_iu_ex5_loadmiss_target_type => xu_iu_ex5_loadmiss_target_type(0 to 0), + xu_iu_complete_vld => xu_iu_complete_tid(2), + xu_iu_complete_qentry => xu_iu_complete_qentry, + xu_iu_complete_target_type => xu_iu_complete_target_type, + ic_fdep_load_quiesce => ic_fdep_load_quiesce(2), + iu_xu_quiesce => iu_xu_quiesce(2), + xu_iu_membar_tid => xu_iu_membar_tid(2), + xu_iu_set_barr_tid => xu_iu_set_barr_tid(2), + xu_iu_larx_done_tid => xu_iu_larx_done_tid(2), + an_ac_sync_ack => an_ac_sync_ack(2), + ic_fdep_icbi_ack => ic_fdep_icbi_ack(2), + an_ac_stcx_complete => an_ac_stcx_complete(2), + mm_iu_barrier_done => mm_iu_barrier_done(2), + spr_fdep_ll_hold => spr_fdep_ll_hold_t2, + xu_iu_spr_ccr2_en_dcr => xu_iu_spr_ccr2_en_dcr, + xu_iu_single_instr_mode => xu_iu_single_instr_mode(2), + fiss_fdep_is2_take => fiss_fdep_is2_take2, + fdep_fiss_is2_instr => fdep_fiss_t2_is2_instr, + fdep_fiss_is2_ta_vld => fdep_fiss_t2_is2_ta_vld, + fdep_fiss_is2_ta => fdep_fiss_t2_is2_ta, + fdep_fiss_is2_s1_vld => fdep_fiss_t2_is2_s1_vld, + fdep_fiss_is2_s1 => fdep_fiss_t2_is2_s1, + fdep_fiss_is2_s2_vld => fdep_fiss_t2_is2_s2_vld, + fdep_fiss_is2_s2 => fdep_fiss_t2_is2_s2, + fdep_fiss_is2_s3_vld => fdep_fiss_t2_is2_s3_vld, + fdep_fiss_is2_s3 => fdep_fiss_t2_is2_s3, + fdep_fiss_is2_pred_update => fdep_fiss_t2_is2_pred_update, + fdep_fiss_is2_pred_taken_cnt => fdep_fiss_t2_is2_pred_taken_cnt, + fdep_fiss_is2_gshare => fdep_fiss_t2_is2_gshare, + fdep_fiss_is2_ifar => fdep_fiss_t2_is2_ifar, + fdep_fiss_is2_error => fdep_fiss_t2_is2_error, + fdep_fiss_is2_axu_ld_or_st => fdep_fiss_t2_is2_axu_ld_or_st, + fdep_fiss_is2_axu_store => fdep_fiss_t2_is2_axu_store, + fdep_fiss_is2_axu_ldst_size => fdep_fiss_t2_is2_axu_ldst_size, + fdep_fiss_is2_axu_ldst_tag => fdep_fiss_t2_is2_axu_ldst_tag, + fdep_fiss_is2_axu_ldst_indexed => fdep_fiss_t2_is2_axu_ldst_indexed, + fdep_fiss_is2_axu_ldst_update => fdep_fiss_t2_is2_axu_ldst_update, + fdep_fiss_is2_axu_ldst_extpid => fdep_fiss_t2_is2_axu_ldst_extpid, + fdep_fiss_is2_axu_ldst_forcealign => fdep_fiss_t2_is2_axu_ldst_forcealign, + fdep_fiss_is2_axu_ldst_forceexcept => fdep_fiss_t2_is2_axu_ldst_forceexcept, + fdep_fiss_is2_axu_mftgpr => fdep_fiss_t2_is2_axu_mftgpr, + fdep_fiss_is2_axu_mffgpr => fdep_fiss_t2_is2_axu_mffgpr, + fdep_fiss_is2_axu_movedp => fdep_fiss_t2_is2_axu_movedp, + fdep_fiss_is2_axu_instr_type => fdep_fiss_t2_is2_axu_instr_type, + fdep_fiss_is2_match => fdep_fiss_t2_is2_match, + fdep_fiss_is2_2ucode => fdep_fiss_t2_is2_2ucode, + fdep_fiss_is2_2ucode_type => fdep_fiss_t2_is2_2ucode_type, + fdep_fiss_is2early_vld => fdep_fiss_t2_is2early_vld, + fdep_fiss_is1_xu_dep_hit_b => fdep_fiss_t2_is1_xu_dep_hit_b, + fdep_fiss_is2_hole_delay => fdep_fiss_t2_is2_hole_delay, + fdep_fiss_is2_to_ucode => fdep_fiss_t2_is2_to_ucode, + fdep_fiss_is2_is_ucode => fdep_fiss_t2_is2_is_ucode, + fu_iu_uc_special => fu_iu_uc_special(2), + iu_fu_ex2_n_flush => iu_fu_ex2_n_flush(2), + i_afi_is2_take => i_afi_is2_take_t(2), + i_axu_is1_dep_hit_b => i_axu_is1_dep_hit_t2_b, + i_axu_is2_instr_v => i_afd_is2_t2_instr_v, + i_axu_is1_early_v => i_axu_is1_early_v_t2, + i_axu_is2_instr_match => i_axu_is2_instr_match_t2, + i_axu_is2_fra => i_afd_is2_fra_t2, + i_axu_is2_frb => i_afd_is2_frb_t2, + i_axu_is2_frc => i_afd_is2_frc_t2, + i_axu_is2_frt => i_afd_is2_frt_t2, + i_axu_is2_fra_v => i_afd_is2_fra_v_t2, + i_axu_is2_frb_v => i_afd_is2_frb_v_t2, + i_axu_is2_frc_v => i_afd_is2_frc_v_t2, + i_afd_is2_is_ucode => i_afd_is2_is_ucode_t2, + i_afd_ignore_flush_is2 => i_afd_ignore_flush_is2_t2, + i_afd_in_ucode_mode_or1d_b => i_afd_in_ucode_mode_or1d_b_t2, + ifdp_is2_est_bubble3 => ifdp_is2_est_bubble3_t2, + ifdp_is2_bypsel => i_afd_is2_bypsel_t2, + axu_dbg_data => axu_dbg_data_t2 +); +iuq_slice3 : entity work.iuq_slice +generic map(expand_type => expand_type, + regmode => regmode, + a2mode => a2mode, + lmq_entries => lmq_entries) +port map( + slice_id => slice_id3, + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_iu_func_sl_thold_2 => pc_iu_func_sl_thold_2(3), + pc_iu_sg_2 => pc_iu_sg_2(3), + clkoff_b => clkoff_b(3), + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b(3), + tc_ac_ccflush_dc => tc_ac_ccflush_dc, + delay_lclkr => delay_lclkr(10+3), + mpw1_b => mpw1_b(10+3), + scan_in => iuq_s3_scan_in, + scan_out => iuq_s3_scan_out, + pc_iu_ram_mode => pc_iu_ram_mode, + pc_iu_ram_thread => pc_iu_ram_thread, + pc_iu_trace_bus_enable => pc_iu_trace_bus_enable, + pc_iu_event_bus_enable => pc_iu_event_bus_enable, + fdep_dbg_data => fdep_dbg_data(22*3 to 22*3+21), + fdep_perf_event => fdep_perf_event_t3, + iu_au_config_iucr => iu_au_config_iucr_t3, + iu_au_config_iucr_pt => iu_au_config_iucr_pt_t3, + spr_dec_mask => spr_dec_mask_t3, + spr_dec_match => spr_dec_match_t3, + uc_flush => uc_flush_tid(3), + xu_iu_flush => xu_iu_flush(3), + xu_iu_rf1_flush => xu_rf1_flush(3), + xu_iu_ex1_flush => xu_ex1_flush(3), + xu_iu_ex2_flush => xu_ex2_flush(3), + xu_iu_ex3_flush => xu_ex3_flush(3), + xu_iu_ex4_flush => xu_ex4_flush(3), + xu_iu_ex5_flush => xu_ex5_flush(3), + fdec_ibuf_stall => fdec_ibuf_stall_t3, + iu_au_ib1_instr_vld => iu_au_ib1_instr_vld_t3, + iu_au_ib1_ifar => iu_au_ib1_ifar_t3, + iu_au_ib1_data => iu_au_ib1_data_t3, + xu_iu_ucode_restart => xu_iu_ucode_restart(3), + xu_iu_slowspr_done => xu_iu_slowspr_done(3), + xu_iu_multdiv_done => xu_iu_multdiv_done(3), + xu_iu_ex4_loadmiss_vld => xu_iu_ex4_loadmiss_tid(3), + xu_iu_ex4_loadmiss_qentry => xu_iu_ex4_loadmiss_qentry, + xu_iu_ex4_loadmiss_target => xu_iu_ex4_loadmiss_target, + xu_iu_ex4_loadmiss_target_type => xu_iu_ex4_loadmiss_target_type, + xu_iu_ex5_loadmiss_vld => xu_iu_ex5_loadmiss_tid(3), + xu_iu_ex5_loadmiss_qentry => xu_iu_ex5_loadmiss_qentry, + xu_iu_ex5_loadmiss_target => xu_iu_ex5_loadmiss_target(1 to 6), + xu_iu_ex5_loadmiss_target_type => xu_iu_ex5_loadmiss_target_type(0 to 0), + xu_iu_complete_vld => xu_iu_complete_tid(3), + xu_iu_complete_qentry => xu_iu_complete_qentry, + xu_iu_complete_target_type => xu_iu_complete_target_type, + ic_fdep_load_quiesce => ic_fdep_load_quiesce(3), + iu_xu_quiesce => iu_xu_quiesce(3), + xu_iu_membar_tid => xu_iu_membar_tid(3), + xu_iu_set_barr_tid => xu_iu_set_barr_tid(3), + xu_iu_larx_done_tid => xu_iu_larx_done_tid(3), + an_ac_sync_ack => an_ac_sync_ack(3), + ic_fdep_icbi_ack => ic_fdep_icbi_ack(3), + an_ac_stcx_complete => an_ac_stcx_complete(3), + mm_iu_barrier_done => mm_iu_barrier_done(3), + spr_fdep_ll_hold => spr_fdep_ll_hold_t3, + xu_iu_spr_ccr2_en_dcr => xu_iu_spr_ccr2_en_dcr, + xu_iu_single_instr_mode => xu_iu_single_instr_mode(3), + fiss_fdep_is2_take => fiss_fdep_is2_take3, + fdep_fiss_is2_instr => fdep_fiss_t3_is2_instr, + fdep_fiss_is2_ta_vld => fdep_fiss_t3_is2_ta_vld, + fdep_fiss_is2_ta => fdep_fiss_t3_is2_ta, + fdep_fiss_is2_s1_vld => fdep_fiss_t3_is2_s1_vld, + fdep_fiss_is2_s1 => fdep_fiss_t3_is2_s1, + fdep_fiss_is2_s2_vld => fdep_fiss_t3_is2_s2_vld, + fdep_fiss_is2_s2 => fdep_fiss_t3_is2_s2, + fdep_fiss_is2_s3_vld => fdep_fiss_t3_is2_s3_vld, + fdep_fiss_is2_s3 => fdep_fiss_t3_is2_s3, + fdep_fiss_is2_pred_update => fdep_fiss_t3_is2_pred_update, + fdep_fiss_is2_pred_taken_cnt => fdep_fiss_t3_is2_pred_taken_cnt, + fdep_fiss_is2_gshare => fdep_fiss_t3_is2_gshare, + fdep_fiss_is2_ifar => fdep_fiss_t3_is2_ifar, + fdep_fiss_is2_error => fdep_fiss_t3_is2_error, + fdep_fiss_is2_axu_ld_or_st => fdep_fiss_t3_is2_axu_ld_or_st, + fdep_fiss_is2_axu_store => fdep_fiss_t3_is2_axu_store, + fdep_fiss_is2_axu_ldst_size => fdep_fiss_t3_is2_axu_ldst_size, + fdep_fiss_is2_axu_ldst_tag => fdep_fiss_t3_is2_axu_ldst_tag, + fdep_fiss_is2_axu_ldst_indexed => fdep_fiss_t3_is2_axu_ldst_indexed, + fdep_fiss_is2_axu_ldst_update => fdep_fiss_t3_is2_axu_ldst_update, + fdep_fiss_is2_axu_ldst_extpid => fdep_fiss_t3_is2_axu_ldst_extpid, + fdep_fiss_is2_axu_ldst_forcealign => fdep_fiss_t3_is2_axu_ldst_forcealign, + fdep_fiss_is2_axu_ldst_forceexcept => fdep_fiss_t3_is2_axu_ldst_forceexcept, + fdep_fiss_is2_axu_mftgpr => fdep_fiss_t3_is2_axu_mftgpr, + fdep_fiss_is2_axu_mffgpr => fdep_fiss_t3_is2_axu_mffgpr, + fdep_fiss_is2_axu_movedp => fdep_fiss_t3_is2_axu_movedp, + fdep_fiss_is2_axu_instr_type => fdep_fiss_t3_is2_axu_instr_type, + fdep_fiss_is2_match => fdep_fiss_t3_is2_match, + fdep_fiss_is2_2ucode => fdep_fiss_t3_is2_2ucode, + fdep_fiss_is2_2ucode_type => fdep_fiss_t3_is2_2ucode_type, + fdep_fiss_is2early_vld => fdep_fiss_t3_is2early_vld, + fdep_fiss_is1_xu_dep_hit_b => fdep_fiss_t3_is1_xu_dep_hit_b, + fdep_fiss_is2_hole_delay => fdep_fiss_t3_is2_hole_delay, + fdep_fiss_is2_to_ucode => fdep_fiss_t3_is2_to_ucode, + fdep_fiss_is2_is_ucode => fdep_fiss_t3_is2_is_ucode, + fu_iu_uc_special => fu_iu_uc_special(3), + iu_fu_ex2_n_flush => iu_fu_ex2_n_flush(3), + i_afi_is2_take => i_afi_is2_take_t(3), + i_axu_is1_dep_hit_b => i_axu_is1_dep_hit_t3_b, + i_axu_is2_instr_v => i_afd_is2_t3_instr_v, + i_axu_is1_early_v => i_axu_is1_early_v_t3, + i_axu_is2_instr_match => i_axu_is2_instr_match_t3, + i_axu_is2_fra => i_afd_is2_fra_t3, + i_axu_is2_frb => i_afd_is2_frb_t3, + i_axu_is2_frc => i_afd_is2_frc_t3, + i_axu_is2_frt => i_afd_is2_frt_t3, + i_axu_is2_fra_v => i_afd_is2_fra_v_t3, + i_axu_is2_frb_v => i_afd_is2_frb_v_t3, + i_axu_is2_frc_v => i_afd_is2_frc_v_t3, + i_afd_is2_is_ucode => i_afd_is2_is_ucode_t3, + i_afd_ignore_flush_is2 => i_afd_ignore_flush_is2_t3, + i_afd_in_ucode_mode_or1d_b => i_afd_in_ucode_mode_or1d_b_t3, + ifdp_is2_est_bubble3 => ifdp_is2_est_bubble3_t3, + ifdp_is2_bypsel => i_afd_is2_bypsel_t3, + axu_dbg_data => axu_dbg_data_t3 +); +slice_id0(0 to 1) <= "00"; +slice_id1(0 to 1) <= "01"; +slice_id2(0 to 1) <= "10"; +slice_id3(0 to 1) <= "11"; +iuq_fxu_issue0 : entity work.iuq_fxu_issue +generic map(expand_type => expand_type) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_iu_func_sl_thold_2 => pc_iu_func_sl_thold_2(1), + pc_iu_sg_2 => pc_iu_sg_2(1), + clkoff_b => clkoff_b(1), + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b(1), + tc_ac_ccflush_dc => tc_ac_ccflush_dc, + delay_lclkr => delay_lclkr(9), + mpw1_b => mpw1_b(9), + scan_in => iuq_fi_scan_in, + scan_out => iuq_fi_scan_out, + fiss_dbg_data => fiss_dbg_data, + pc_iu_trace_bus_enable => pc_iu_trace_bus_enable, + pc_iu_event_bus_enable => pc_iu_event_bus_enable, + fiss_perf_event_t0 => fiss_perf_event_t0, + fiss_perf_event_t1 => fiss_perf_event_t1, + fiss_perf_event_t2 => fiss_perf_event_t2, + fiss_perf_event_t3 => fiss_perf_event_t3, + xu_iu_need_hole => xu_iu_need_hole, + xu_iu_xucr0_rel => xu_iu_xucr0_rel, + an_ac_reld_data_vld => an_ac_reld_data_vld_clone, + an_ac_reld_core_tag => an_ac_reld_core_tag_clone(1 to 4), + an_ac_reld_ditc => an_ac_reld_ditc_clone, + an_ac_reld_data_coming => an_ac_reld_data_coming_clone, + an_ac_back_inv => an_ac_back_inv, + an_ac_back_inv_target => an_ac_back_inv_target(1), + fiss_uc_is2_ucode_vld => fiss_uc_is2_ucode_vld, + fdep_fiss_t0_is2_instr => fdep_fiss_t0_is2_instr, + fdep_fiss_t0_is2_ta_vld => fdep_fiss_t0_is2_ta_vld, + fdep_fiss_t0_is2_ta => fdep_fiss_t0_is2_ta, + fdep_fiss_t0_is2_s1_vld => fdep_fiss_t0_is2_s1_vld, + fdep_fiss_t0_is2_s1 => fdep_fiss_t0_is2_s1, + fdep_fiss_t0_is2_s2_vld => fdep_fiss_t0_is2_s2_vld, + fdep_fiss_t0_is2_s2 => fdep_fiss_t0_is2_s2, + fdep_fiss_t0_is2_s3_vld => fdep_fiss_t0_is2_s3_vld, + fdep_fiss_t0_is2_s3 => fdep_fiss_t0_is2_s3, + fdep_fiss_t0_is2_pred_update => fdep_fiss_t0_is2_pred_update, + fdep_fiss_t0_is2_pred_taken_cnt => fdep_fiss_t0_is2_pred_taken_cnt, + fdep_fiss_t0_is2_gshare => fdep_fiss_t0_is2_gshare, + fdep_fiss_t0_is2_ifar => fdep_fiss_t0_is2_ifar, + fdep_fiss_t0_is2_error => fdep_fiss_t0_is2_error, + fdep_fiss_t0_is2_axu_ld_or_st => fdep_fiss_t0_is2_axu_ld_or_st, + fdep_fiss_t0_is2_axu_store => fdep_fiss_t0_is2_axu_store, + fdep_fiss_t0_is2_axu_ldst_size => fdep_fiss_t0_is2_axu_ldst_size, + fdep_fiss_t0_is2_axu_ldst_tag => fdep_fiss_t0_is2_axu_ldst_tag, + fdep_fiss_t0_is2_axu_ldst_indexed=> fdep_fiss_t0_is2_axu_ldst_indexed, + fdep_fiss_t0_is2_axu_ldst_update => fdep_fiss_t0_is2_axu_ldst_update, + fdep_fiss_t0_is2_axu_ldst_extpid => fdep_fiss_t0_is2_axu_ldst_extpid, + fdep_fiss_t0_is2_axu_ldst_forcealign => fdep_fiss_t0_is2_axu_ldst_forcealign, + fdep_fiss_t0_is2_axu_ldst_forceexcept => fdep_fiss_t0_is2_axu_ldst_forceexcept, + fdep_fiss_t0_is2_axu_mftgpr => fdep_fiss_t0_is2_axu_mftgpr, + fdep_fiss_t0_is2_axu_mffgpr => fdep_fiss_t0_is2_axu_mffgpr, + fdep_fiss_t0_is2_axu_movedp => fdep_fiss_t0_is2_axu_movedp, + fdep_fiss_t0_is2_axu_instr_type => fdep_fiss_t0_is2_axu_instr_type, + fdep_fiss_t0_is2_match => fdep_fiss_t0_is2_match, + fdep_fiss_t0_is2_2ucode => fdep_fiss_t0_is2_2ucode, + fdep_fiss_t0_is2_2ucode_type => fdep_fiss_t0_is2_2ucode_type, + fdep_fiss_t0_is2_hole_delay => fdep_fiss_t0_is2_hole_delay, + fdep_fiss_t0_is2_to_ucode => fdep_fiss_t0_is2_to_ucode, + fdep_fiss_t0_is2_is_ucode => fdep_fiss_t0_is2_is_ucode, + fdep_fiss_t0_is2early_vld => fdep_fiss_t0_is2early_vld, + fdep_fiss_t0_is1_xu_dep_hit_b => fdep_fiss_t0_is1_xu_dep_hit_b, + fdep_fiss_t1_is2_instr => fdep_fiss_t1_is2_instr, + fdep_fiss_t1_is2_ta_vld => fdep_fiss_t1_is2_ta_vld, + fdep_fiss_t1_is2_ta => fdep_fiss_t1_is2_ta, + fdep_fiss_t1_is2_s1_vld => fdep_fiss_t1_is2_s1_vld, + fdep_fiss_t1_is2_s1 => fdep_fiss_t1_is2_s1, + fdep_fiss_t1_is2_s2_vld => fdep_fiss_t1_is2_s2_vld, + fdep_fiss_t1_is2_s2 => fdep_fiss_t1_is2_s2, + fdep_fiss_t1_is2_s3_vld => fdep_fiss_t1_is2_s3_vld, + fdep_fiss_t1_is2_s3 => fdep_fiss_t1_is2_s3, + fdep_fiss_t1_is2_pred_update => fdep_fiss_t1_is2_pred_update, + fdep_fiss_t1_is2_pred_taken_cnt => fdep_fiss_t1_is2_pred_taken_cnt, + fdep_fiss_t1_is2_gshare => fdep_fiss_t1_is2_gshare, + fdep_fiss_t1_is2_ifar => fdep_fiss_t1_is2_ifar, + fdep_fiss_t1_is2_error => fdep_fiss_t1_is2_error, + fdep_fiss_t1_is2_axu_ld_or_st => fdep_fiss_t1_is2_axu_ld_or_st, + fdep_fiss_t1_is2_axu_store => fdep_fiss_t1_is2_axu_store, + fdep_fiss_t1_is2_axu_ldst_size => fdep_fiss_t1_is2_axu_ldst_size, + fdep_fiss_t1_is2_axu_ldst_tag => fdep_fiss_t1_is2_axu_ldst_tag, + fdep_fiss_t1_is2_axu_ldst_indexed=> fdep_fiss_t1_is2_axu_ldst_indexed, + fdep_fiss_t1_is2_axu_ldst_update => fdep_fiss_t1_is2_axu_ldst_update, + fdep_fiss_t1_is2_axu_ldst_extpid => fdep_fiss_t1_is2_axu_ldst_extpid, + fdep_fiss_t1_is2_axu_ldst_forcealign => fdep_fiss_t1_is2_axu_ldst_forcealign, + fdep_fiss_t1_is2_axu_ldst_forceexcept => fdep_fiss_t1_is2_axu_ldst_forceexcept, + fdep_fiss_t1_is2_axu_mftgpr => fdep_fiss_t1_is2_axu_mftgpr, + fdep_fiss_t1_is2_axu_mffgpr => fdep_fiss_t1_is2_axu_mffgpr, + fdep_fiss_t1_is2_axu_movedp => fdep_fiss_t1_is2_axu_movedp, + fdep_fiss_t1_is2_axu_instr_type => fdep_fiss_t1_is2_axu_instr_type, + fdep_fiss_t1_is2_match => fdep_fiss_t1_is2_match, + fdep_fiss_t1_is2_2ucode => fdep_fiss_t1_is2_2ucode, + fdep_fiss_t1_is2_2ucode_type => fdep_fiss_t1_is2_2ucode_type, + fdep_fiss_t1_is2_hole_delay => fdep_fiss_t1_is2_hole_delay, + fdep_fiss_t1_is2_to_ucode => fdep_fiss_t1_is2_to_ucode, + fdep_fiss_t1_is2_is_ucode => fdep_fiss_t1_is2_is_ucode, + fdep_fiss_t1_is2early_vld => fdep_fiss_t1_is2early_vld, + fdep_fiss_t1_is1_xu_dep_hit_b => fdep_fiss_t1_is1_xu_dep_hit_b, + fdep_fiss_t2_is2_instr => fdep_fiss_t2_is2_instr, + fdep_fiss_t2_is2_ta_vld => fdep_fiss_t2_is2_ta_vld, + fdep_fiss_t2_is2_ta => fdep_fiss_t2_is2_ta, + fdep_fiss_t2_is2_s1_vld => fdep_fiss_t2_is2_s1_vld, + fdep_fiss_t2_is2_s1 => fdep_fiss_t2_is2_s1, + fdep_fiss_t2_is2_s2_vld => fdep_fiss_t2_is2_s2_vld, + fdep_fiss_t2_is2_s2 => fdep_fiss_t2_is2_s2, + fdep_fiss_t2_is2_s3_vld => fdep_fiss_t2_is2_s3_vld, + fdep_fiss_t2_is2_s3 => fdep_fiss_t2_is2_s3, + fdep_fiss_t2_is2_pred_update => fdep_fiss_t2_is2_pred_update, + fdep_fiss_t2_is2_pred_taken_cnt => fdep_fiss_t2_is2_pred_taken_cnt, + fdep_fiss_t2_is2_gshare => fdep_fiss_t2_is2_gshare, + fdep_fiss_t2_is2_ifar => fdep_fiss_t2_is2_ifar, + fdep_fiss_t2_is2_error => fdep_fiss_t2_is2_error, + fdep_fiss_t2_is2_axu_ld_or_st => fdep_fiss_t2_is2_axu_ld_or_st, + fdep_fiss_t2_is2_axu_store => fdep_fiss_t2_is2_axu_store, + fdep_fiss_t2_is2_axu_ldst_size => fdep_fiss_t2_is2_axu_ldst_size, + fdep_fiss_t2_is2_axu_ldst_tag => fdep_fiss_t2_is2_axu_ldst_tag, + fdep_fiss_t2_is2_axu_ldst_indexed=> fdep_fiss_t2_is2_axu_ldst_indexed, + fdep_fiss_t2_is2_axu_ldst_update => fdep_fiss_t2_is2_axu_ldst_update, + fdep_fiss_t2_is2_axu_ldst_extpid => fdep_fiss_t2_is2_axu_ldst_extpid, + fdep_fiss_t2_is2_axu_ldst_forcealign => fdep_fiss_t2_is2_axu_ldst_forcealign, + fdep_fiss_t2_is2_axu_ldst_forceexcept => fdep_fiss_t2_is2_axu_ldst_forceexcept, + fdep_fiss_t2_is2_axu_mftgpr => fdep_fiss_t2_is2_axu_mftgpr, + fdep_fiss_t2_is2_axu_mffgpr => fdep_fiss_t2_is2_axu_mffgpr, + fdep_fiss_t2_is2_axu_movedp => fdep_fiss_t2_is2_axu_movedp, + fdep_fiss_t2_is2_axu_instr_type => fdep_fiss_t2_is2_axu_instr_type, + fdep_fiss_t2_is2_match => fdep_fiss_t2_is2_match, + fdep_fiss_t2_is2_2ucode => fdep_fiss_t2_is2_2ucode, + fdep_fiss_t2_is2_2ucode_type => fdep_fiss_t2_is2_2ucode_type, + fdep_fiss_t2_is2_hole_delay => fdep_fiss_t2_is2_hole_delay, + fdep_fiss_t2_is2_to_ucode => fdep_fiss_t2_is2_to_ucode, + fdep_fiss_t2_is2_is_ucode => fdep_fiss_t2_is2_is_ucode, + fdep_fiss_t2_is2early_vld => fdep_fiss_t2_is2early_vld, + fdep_fiss_t2_is1_xu_dep_hit_b => fdep_fiss_t2_is1_xu_dep_hit_b, + fdep_fiss_t3_is2_instr => fdep_fiss_t3_is2_instr, + fdep_fiss_t3_is2_ta_vld => fdep_fiss_t3_is2_ta_vld, + fdep_fiss_t3_is2_ta => fdep_fiss_t3_is2_ta, + fdep_fiss_t3_is2_s1_vld => fdep_fiss_t3_is2_s1_vld, + fdep_fiss_t3_is2_s1 => fdep_fiss_t3_is2_s1, + fdep_fiss_t3_is2_s2_vld => fdep_fiss_t3_is2_s2_vld, + fdep_fiss_t3_is2_s2 => fdep_fiss_t3_is2_s2, + fdep_fiss_t3_is2_s3_vld => fdep_fiss_t3_is2_s3_vld, + fdep_fiss_t3_is2_s3 => fdep_fiss_t3_is2_s3, + fdep_fiss_t3_is2_pred_update => fdep_fiss_t3_is2_pred_update, + fdep_fiss_t3_is2_pred_taken_cnt => fdep_fiss_t3_is2_pred_taken_cnt, + fdep_fiss_t3_is2_gshare => fdep_fiss_t3_is2_gshare, + fdep_fiss_t3_is2_ifar => fdep_fiss_t3_is2_ifar, + fdep_fiss_t3_is2_error => fdep_fiss_t3_is2_error, + fdep_fiss_t3_is2_axu_ld_or_st => fdep_fiss_t3_is2_axu_ld_or_st, + fdep_fiss_t3_is2_axu_store => fdep_fiss_t3_is2_axu_store, + fdep_fiss_t3_is2_axu_ldst_size => fdep_fiss_t3_is2_axu_ldst_size, + fdep_fiss_t3_is2_axu_ldst_tag => fdep_fiss_t3_is2_axu_ldst_tag, + fdep_fiss_t3_is2_axu_ldst_indexed=> fdep_fiss_t3_is2_axu_ldst_indexed, + fdep_fiss_t3_is2_axu_ldst_update => fdep_fiss_t3_is2_axu_ldst_update, + fdep_fiss_t3_is2_axu_ldst_extpid => fdep_fiss_t3_is2_axu_ldst_extpid, + fdep_fiss_t3_is2_axu_ldst_forcealign => fdep_fiss_t3_is2_axu_ldst_forcealign, + fdep_fiss_t3_is2_axu_ldst_forceexcept => fdep_fiss_t3_is2_axu_ldst_forceexcept, + fdep_fiss_t3_is2_axu_mftgpr => fdep_fiss_t3_is2_axu_mftgpr, + fdep_fiss_t3_is2_axu_mffgpr => fdep_fiss_t3_is2_axu_mffgpr, + fdep_fiss_t3_is2_axu_movedp => fdep_fiss_t3_is2_axu_movedp, + fdep_fiss_t3_is2_axu_instr_type => fdep_fiss_t3_is2_axu_instr_type, + fdep_fiss_t3_is2_match => fdep_fiss_t3_is2_match, + fdep_fiss_t3_is2_2ucode => fdep_fiss_t3_is2_2ucode, + fdep_fiss_t3_is2_2ucode_type => fdep_fiss_t3_is2_2ucode_type, + fdep_fiss_t3_is2_hole_delay => fdep_fiss_t3_is2_hole_delay, + fdep_fiss_t3_is2_to_ucode => fdep_fiss_t3_is2_to_ucode, + fdep_fiss_t3_is2_is_ucode => fdep_fiss_t3_is2_is_ucode, + fdep_fiss_t3_is2early_vld => fdep_fiss_t3_is2early_vld, + fdep_fiss_t3_is1_xu_dep_hit_b => fdep_fiss_t3_is1_xu_dep_hit_b, + fiss_fdep_is2_take0 => fiss_fdep_is2_take0, + fiss_fdep_is2_take1 => fiss_fdep_is2_take1, + fiss_fdep_is2_take2 => fiss_fdep_is2_take2, + fiss_fdep_is2_take3 => fiss_fdep_is2_take3, + spr_issue_high_mask => spr_issue_high_mask, + spr_issue_med_mask => spr_issue_med_mask, + spr_fiss_count0_max => spr_fiss_count0_max, + spr_fiss_count1_max => spr_fiss_count1_max, + spr_fiss_count2_max => spr_fiss_count2_max, + spr_fiss_count3_max => spr_fiss_count3_max, + spr_fiss_pri_rand => spr_fiss_pri_rand, + spr_fiss_pri_rand_always => spr_fiss_pri_rand_always, + spr_fiss_pri_rand_flush => spr_fiss_pri_rand_flush, + iu_au_hi_pri_mask => iu_au_hi_pri_mask, + iu_au_md_pri_mask => iu_au_md_pri_mask, + i_afi_is2_take_t => i_afi_is2_take_t, + i_afd_is2_t0_instr_v => i_afd_is2_t0_instr_v, + i_afd_is2_t1_instr_v => i_afd_is2_t1_instr_v, + i_afd_is2_t2_instr_v => i_afd_is2_t2_instr_v, + i_afd_is2_t3_instr_v => i_afd_is2_t3_instr_v, + i_axu_is1_dep_hit_t0_b => i_axu_is1_dep_hit_t0_b, + i_axu_is1_dep_hit_t1_b => i_axu_is1_dep_hit_t1_b, + i_axu_is1_dep_hit_t2_b => i_axu_is1_dep_hit_t2_b, + i_axu_is1_dep_hit_t3_b => i_axu_is1_dep_hit_t3_b, + xu_iu_is2_flush_tid => xu_iu_flush, + xu_iu_rf0_flush_tid => xu_iu_flush, + xu_iu_rf1_flush_tid => xu_rf1_flush, + xu_iu_ex1_flush_tid => xu_ex1_flush, + xu_iu_ex2_flush_tid => xu_ex2_flush, + xu_iu_ex3_flush_tid => xu_ex3_flush, + xu_iu_ex4_flush_tid => xu_ex4_flush, + xu_iu_ex5_flush_tid => xu_ex5_flush, + xu_iu_ex5_ppc_cpl => xu_iu_ex5_ppc_cpl, + iu_xu_is2_vld => iu_xu_is2_vld_internal, + iu_xu_is2_tid => iu_xu_is2_tid_internal, + iu_xu_is2_instr => iu_xu_is2_instr_internal, + iu_xu_is2_ta_vld => iu_xu_is2_ta_vld, + iu_xu_is2_ta => iu_xu_is2_ta, + iu_xu_is2_s1_vld => iu_xu_is2_s1_vld, + iu_xu_is2_s1 => iu_xu_is2_s1, + iu_xu_is2_s2_vld => iu_xu_is2_s2_vld, + iu_xu_is2_s2 => iu_xu_is2_s2, + iu_xu_is2_s3_vld => iu_xu_is2_s3_vld, + iu_xu_is2_s3 => iu_xu_is2_s3, + iu_xu_is2_pred_update => iu_xu_is2_pred_update_internal, + iu_xu_is2_pred_taken_cnt => iu_xu_is2_pred_taken_cnt_internal, + iu_xu_is2_gshare => iu_xu_is2_gshare, + iu_xu_is2_ifar => iu_xu_is2_ifar_internal, + iu_xu_is2_error => iu_xu_is2_error_internal, + iu_xu_is2_is_ucode => iu_xu_is2_is_ucode, + iu_xu_is2_match => iu_xu_is2_match, + fiss_uc_is2_2ucode => fiss_uc_is2_2ucode, + fiss_uc_is2_2ucode_type => fiss_uc_is2_2ucode_type, + iu_xu_is2_axu_ldst_update => iu_xu_is2_axu_ldst_update, + iu_xu_is2_axu_ldst_extpid => iu_xu_is2_axu_ldst_extpid, + iu_xu_is2_axu_ldst_forcealign => iu_xu_is2_axu_ldst_forcealign, + iu_xu_is2_axu_ldst_forceexcept => iu_xu_is2_axu_ldst_forceexcept, + iu_xu_is2_axu_mftgpr => iu_xu_is2_axu_mftgpr, + iu_xu_is2_axu_mffgpr => iu_xu_is2_axu_mffgpr, + iu_xu_is2_axu_movedp => iu_xu_is2_axu_movedp, + iu_xu_is2_axu_instr_type => iu_xu_is2_axu_instr_type, + iu_xu_is2_axu_ld_or_st => iu_xu_is2_axu_ld_or_st, + iu_xu_is2_axu_store => iu_xu_is2_axu_store_internal, + iu_xu_is2_axu_ldst_size => iu_xu_is2_axu_ldst_size, + iu_xu_is2_axu_ldst_tag => iu_xu_is2_axu_ldst_tag, + iu_xu_is2_axu_ldst_indexed => iu_xu_is2_axu_ldst_indexed, + iu_fu_rf0_str_val => iu_fu_rf0_str_val, + iu_fu_rf0_ldst_val => iu_fu_rf0_ldst_val, + iu_fu_rf0_ldst_tid => iu_fu_rf0_ldst_tid, + iu_fu_rf0_ldst_tag => iu_fu_rf0_ldst_tag +); +iuq_axu_fu_iss0 : entity work.iuq_axu_fu_iss +generic map(expand_type => expand_type, + fpr_addr_width => fpr_addr_width) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + i_iss_si => iuq_ai_scan_in, + i_iss_so => iuq_ai_scan_out, + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b(2), + pc_iu_func_sl_thold_2 => pc_iu_func_sl_thold_2(2), + pc_iu_sg_2 => pc_iu_sg_2(2), + clkoff_b => clkoff_b(2), + tc_ac_ccflush_dc => tc_ac_ccflush_dc, + delay_lclkr => delay_lclkr(14), + mpw1_b => mpw1_b(14), + iu_au_is1_flush => xu_iu_flush, + xu_iu_is2_flush => xu_iu_flush, + uc_flush => uc_flush_tid, + i_afd_config_iucr_t0 => iu_au_config_iucr_pt_t0(2 to 4), + i_afd_config_iucr_t1 => iu_au_config_iucr_pt_t1(2 to 4), + i_afd_config_iucr_t2 => iu_au_config_iucr_pt_t2(2 to 4), + i_afd_config_iucr_t3 => iu_au_config_iucr_pt_t3(2 to 4), + i_afd_in_ucode_mode_or1d_b_t0 => i_afd_in_ucode_mode_or1d_b_t0, + i_afd_in_ucode_mode_or1d_b_t1 => i_afd_in_ucode_mode_or1d_b_t1, + i_afd_in_ucode_mode_or1d_b_t2 => i_afd_in_ucode_mode_or1d_b_t2, + i_afd_in_ucode_mode_or1d_b_t3 => i_afd_in_ucode_mode_or1d_b_t3, + i_axu_is2_instr_match_t0 => i_axu_is2_instr_match_t0, + i_axu_is2_instr_match_t1 => i_axu_is2_instr_match_t1, + i_axu_is2_instr_match_t2 => i_axu_is2_instr_match_t2, + i_axu_is2_instr_match_t3 => i_axu_is2_instr_match_t3, + i_afd_is2_is_ucode_t0 => i_afd_is2_is_ucode_t0, + i_afd_is2_is_ucode_t1 => i_afd_is2_is_ucode_t1, + i_afd_is2_is_ucode_t2 => i_afd_is2_is_ucode_t2, + i_afd_is2_is_ucode_t3 => i_afd_is2_is_ucode_t3, + i_afd_ignore_flush_is2_t0 => i_afd_ignore_flush_is2_t0, + i_afd_ignore_flush_is2_t1 => i_afd_ignore_flush_is2_t1, + i_afd_ignore_flush_is2_t2 => i_afd_ignore_flush_is2_t2, + i_afd_ignore_flush_is2_t3 => i_afd_ignore_flush_is2_t3, + i_afd_is2_t0_instr_v => i_afd_is2_t0_instr_v, + i_afd_is2_t1_instr_v => i_afd_is2_t1_instr_v, + i_afd_is2_t2_instr_v => i_afd_is2_t2_instr_v, + i_afd_is2_t3_instr_v => i_afd_is2_t3_instr_v, + i_axu_is1_early_v_t0 => i_axu_is1_early_v_t0, + i_axu_is1_early_v_t1 => i_axu_is1_early_v_t1, + i_axu_is1_early_v_t2 => i_axu_is1_early_v_t2, + i_axu_is1_early_v_t3 => i_axu_is1_early_v_t3, + i_afd_is2_t0_instr => fdep_fiss_t0_is2_instr, + i_afd_is2_t1_instr => fdep_fiss_t1_is2_instr, + i_afd_is2_t2_instr => fdep_fiss_t2_is2_instr, + i_afd_is2_t3_instr => fdep_fiss_t3_is2_instr, + i_afd_is2_fra_t0 => i_afd_is2_fra_t0, + i_afd_is2_fra_t1 => i_afd_is2_fra_t1, + i_afd_is2_fra_t2 => i_afd_is2_fra_t2, + i_afd_is2_fra_t3 => i_afd_is2_fra_t3, + i_afd_is2_frb_t0 => i_afd_is2_frb_t0, + i_afd_is2_frb_t1 => i_afd_is2_frb_t1, + i_afd_is2_frb_t2 => i_afd_is2_frb_t2, + i_afd_is2_frb_t3 => i_afd_is2_frb_t3, + i_afd_is2_frc_t0 => i_afd_is2_frc_t0, + i_afd_is2_frc_t1 => i_afd_is2_frc_t1, + i_afd_is2_frc_t2 => i_afd_is2_frc_t2, + i_afd_is2_frc_t3 => i_afd_is2_frc_t3, + i_afd_is2_frt_t0 => i_afd_is2_frt_t0, + i_afd_is2_frt_t1 => i_afd_is2_frt_t1, + i_afd_is2_frt_t2 => i_afd_is2_frt_t2, + i_afd_is2_frt_t3 => i_afd_is2_frt_t3, + i_afd_is2_fra_v_t0 => i_afd_is2_fra_v_t0, + i_afd_is2_fra_v_t1 => i_afd_is2_fra_v_t1, + i_afd_is2_fra_v_t2 => i_afd_is2_fra_v_t2, + i_afd_is2_fra_v_t3 => i_afd_is2_fra_v_t3, + i_afd_is2_frb_v_t0 => i_afd_is2_frb_v_t0, + i_afd_is2_frb_v_t1 => i_afd_is2_frb_v_t1, + i_afd_is2_frb_v_t2 => i_afd_is2_frb_v_t2, + i_afd_is2_frb_v_t3 => i_afd_is2_frb_v_t3, + i_afd_is2_frc_v_t0 => i_afd_is2_frc_v_t0, + i_afd_is2_frc_v_t1 => i_afd_is2_frc_v_t1, + i_afd_is2_frc_v_t2 => i_afd_is2_frc_v_t2, + i_afd_is2_frc_v_t3 => i_afd_is2_frc_v_t3, + i_afd_is2_bypsel_t0 => i_afd_is2_bypsel_t0, + i_afd_is2_bypsel_t1 => i_afd_is2_bypsel_t1, + i_afd_is2_bypsel_t2 => i_afd_is2_bypsel_t2, + i_afd_is2_bypsel_t3 => i_afd_is2_bypsel_t3, + i_afd_is2_ifar_t0 => fdep_fiss_t0_is2_ifar, + i_afd_is2_ifar_t1 => fdep_fiss_t1_is2_ifar, + i_afd_is2_ifar_t2 => fdep_fiss_t2_is2_ifar, + i_afd_is2_ifar_t3 => fdep_fiss_t3_is2_ifar, + ifdp_is2_est_bubble3_t0 => ifdp_is2_est_bubble3_t0, + ifdp_is2_est_bubble3_t1 => ifdp_is2_est_bubble3_t1, + ifdp_is2_est_bubble3_t2 => ifdp_is2_est_bubble3_t2, + ifdp_is2_est_bubble3_t3 => ifdp_is2_est_bubble3_t3, + iu_au_hi_pri_mask => iu_au_hi_pri_mask, + iu_au_md_pri_mask => iu_au_md_pri_mask, + spr_fiss_pri_rand => spr_fiss_pri_rand, + spr_fiss_pri_rand_always => spr_fiss_pri_rand_always, + spr_fiss_pri_rand_flush => spr_fiss_pri_rand_flush, + iu_is2_take_t => i_afi_is2_take_t, + i_axu_is1_dep_hit_t0_b => i_axu_is1_dep_hit_t0_b, + i_axu_is1_dep_hit_t1_b => i_axu_is1_dep_hit_t1_b, + i_axu_is1_dep_hit_t2_b => i_axu_is1_dep_hit_t2_b, + i_axu_is1_dep_hit_t3_b => i_axu_is1_dep_hit_t3_b, + iu_fu_is2_tid_decode => iu_fu_is2_tid_decode, + iu_fu_rf0_ucfmul => iu_fu_rf0_ucfmul, + iu_fu_rf0_instr_match => iu_fu_rf0_instr_match, + iu_fu_rf0_is_ucode => iu_fu_rf0_is_ucode, + iu_fu_rf0_instr => iu_fu_rf0_instr, + iu_fu_rf0_instr_v => iu_fu_rf0_instr_v, + iu_fu_rf0_fra => iu_fu_rf0_fra, + iu_fu_rf0_frb => iu_fu_rf0_frb, + iu_fu_rf0_frc => iu_fu_rf0_frc, + iu_fu_rf0_frt => iu_fu_rf0_frt, + iu_fu_rf0_fra_v => iu_fu_rf0_fra_v, + iu_fu_rf0_frb_v => iu_fu_rf0_frb_v, + iu_fu_rf0_frc_v => iu_fu_rf0_frc_v, + iu_fu_rf0_tid => iu_fu_rf0_tid, + iu_fu_rf0_bypsel => iu_fu_rf0_bypsel, + iu_fu_rf0_ifar => iu_fu_rf0_ifar, + fu_iss_debug => fu_iss_dbg_data +); +end iuq_slice_wrap; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_spr.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_spr.vhdl new file mode 100644 index 0000000..c1854bf --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_spr.vhdl @@ -0,0 +1,1748 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; +use ieee.std_logic_1164.all; + +library ibm; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; + +library support; +use support.power_logic_pkg.all; + +library tri; +use tri.tri_latches_pkg.all; + +library work; +use work.iuq_pkg.all; + +entity iuq_spr is +generic(regmode : integer := 6; + a2mode : integer := 1; + expand_type : integer := 2 ); +port( + vdd : inout power_logic; + gnd : inout power_logic; + + slowspr_val_in : in std_ulogic; + slowspr_rw_in : in std_ulogic; + slowspr_etid_in : in std_ulogic_vector(0 to 1); + slowspr_addr_in : in std_ulogic_vector(0 to 9); + slowspr_data_in : in std_ulogic_vector(64-(2**regmode) to 63); + slowspr_done_in : in std_ulogic; + + slowspr_val_out : out std_ulogic; + slowspr_rw_out : out std_ulogic; + slowspr_etid_out : out std_ulogic_vector(0 to 1); + slowspr_addr_out : out std_ulogic_vector(0 to 9); + slowspr_data_out : out std_ulogic_vector(64-(2**regmode) to 63); + slowspr_done_out : out std_ulogic; + + spr_ic_idir_read : out std_ulogic; + spr_ic_idir_way : out std_ulogic_vector(0 to 1); + spr_ic_idir_row : out std_ulogic_vector(52 to 57); + ic_spr_idir_done : in std_ulogic; + ic_spr_idir_lru : in std_ulogic_vector(0 to 2); + ic_spr_idir_parity : in std_ulogic_vector(0 to 3); + ic_spr_idir_endian : in std_ulogic; + ic_spr_idir_valid : in std_ulogic; + ic_spr_idir_tag : in std_ulogic_vector(0 to 29); + + spr_ic_icbi_ack_en : out std_ulogic; + spr_ic_cls : out std_ulogic; + spr_ic_clockgate_dis : out std_ulogic_vector(0 to 1); + + spr_ic_bp_config : out std_ulogic_vector(0 to 3); + spr_bp_config : out std_ulogic_vector(0 to 3); + spr_bp_gshare_mask : out std_ulogic_vector(0 to 3); + + spr_dec_mask : out std_ulogic_vector(0 to 31); + spr_dec_match : out std_ulogic_vector(0 to 31); + + iu_au_config_iucr_t0 : out std_ulogic_vector(0 to 7); + iu_au_config_iucr_t1 : out std_ulogic_vector(0 to 7); + iu_au_config_iucr_t2 : out std_ulogic_vector(0 to 7); + iu_au_config_iucr_t3 : out std_ulogic_vector(0 to 7); + + + + spr_issue_high_mask : out std_ulogic_vector(0 to 3); + spr_issue_med_mask : out std_ulogic_vector(0 to 3); + spr_fiss_count0_max : out std_ulogic_vector(0 to 5); + spr_fiss_count1_max : out std_ulogic_vector(0 to 5); + spr_fiss_count2_max : out std_ulogic_vector(0 to 5); + spr_fiss_count3_max : out std_ulogic_vector(0 to 5); + + spr_ic_pri_rand : out std_ulogic_vector(0 to 4); + spr_ic_pri_rand_always : out std_ulogic; + spr_ic_pri_rand_flush : out std_ulogic; + + spr_fiss_pri_rand : out std_ulogic_vector(0 to 4); + spr_fiss_pri_rand_always : out std_ulogic; + spr_fiss_pri_rand_flush : out std_ulogic; + + spr_fdep_ll_hold : out std_ulogic; + + + xu_iu_run_thread : in std_ulogic_vector(0 to 3); + + xu_iu_ex6_pri : in std_ulogic_vector(0 to 2); + xu_iu_ex6_pri_val : in std_ulogic_vector(0 to 3); + + xu_iu_raise_iss_pri : in std_ulogic_vector(0 to 3); + xu_iu_msr_gs : in std_ulogic_vector(0 to 3); + xu_iu_msr_pr : in std_ulogic_vector(0 to 3); + + nclk : in clk_logic; + pc_iu_sg_2 : in std_ulogic; + pc_iu_func_sl_thold_2 : in std_ulogic; + pc_iu_cfg_sl_thold_2 : in std_ulogic; + clkoff_b : in std_ulogic; + act_dis : in std_ulogic; + tc_ac_ccflush_dc : in std_ulogic; + d_mode : in std_ulogic; + delay_lclkr : in std_ulogic; + mpw1_b : in std_ulogic; + mpw2_b : in std_ulogic; + ccfg_scan_in : in std_ulogic; + ccfg_scan_out : out std_ulogic; + bcfg_scan_in : in std_ulogic; + bcfg_scan_out : out std_ulogic; + dcfg_scan_in : in std_ulogic; + dcfg_scan_out : out std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic +); + +-- synopsys translate_off + + +-- synopsys translate_on + +end iuq_spr; +architecture iuq_spr of iuq_spr is + + + +constant ll_trig_rnd_offset : natural := 0; +constant ll_trig_cnt_offset : natural := ll_trig_rnd_offset + 14; +constant ll_hold_cnt_offset : natural := ll_trig_cnt_offset + 18; +constant xu_iu_run_thread_offset : natural := ll_hold_cnt_offset + 10; +constant xu_iu_ex6_pri_offset : natural := xu_iu_run_thread_offset + 4; +constant xu_iu_ex6_pri_val_offset : natural := xu_iu_ex6_pri_offset + 3; +constant xu_iu_raise_iss_pri_offset : natural := xu_iu_ex6_pri_val_offset + 4; +constant xu_iu_msr_gs_offset : natural := xu_iu_raise_iss_pri_offset + 4; +constant xu_iu_msr_pr_offset : natural := xu_iu_msr_gs_offset + 4; +constant slowspr_val_offset : natural := xu_iu_msr_pr_offset + 4; +constant slowspr_rw_offset : natural := slowspr_val_offset + 1; +constant slowspr_etid_offset : natural := slowspr_rw_offset + 1; +constant slowspr_addr_offset : natural := slowspr_etid_offset + 2; +constant slowspr_data_offset : natural := slowspr_addr_offset + 10; +constant slowspr_done_offset : natural := slowspr_data_offset + 2**regmode; +constant iu_slowspr_val_offset : natural := slowspr_done_offset + 1; +constant iu_slowspr_rw_offset : natural := iu_slowspr_val_offset + 1; +constant iu_slowspr_etid_offset : natural := iu_slowspr_rw_offset + 1; +constant iu_slowspr_addr_offset : natural := iu_slowspr_etid_offset + 2; +constant iu_slowspr_data_offset : natural := iu_slowspr_addr_offset + 10; +constant iu_slowspr_done_offset : natural := iu_slowspr_data_offset + 2**regmode; +constant immr0_offset : natural := iu_slowspr_done_offset + 1; +constant imr0_offset : natural := immr0_offset + 32; +constant iulfsr_offset : natural := imr0_offset + 32; +constant iudbg0_offset : natural := iulfsr_offset + 32; +constant iudbg1_offset : natural := iudbg0_offset + 8; +constant iudbg2_offset : natural := iudbg1_offset + 11; +constant iudbg0_exec_offset : natural := iudbg2_offset + 30; +constant iudbg0_done_offset : natural := iudbg0_exec_offset + 1; +constant spare_offset : natural := iudbg0_done_offset + 1; +constant scan_right : natural := spare_offset + 4 - 1; + +constant iullcr_offset : natural := 0; +constant iucr0_offset : natural := iullcr_offset + 18; +constant iucr1_t0_offset : natural := iucr0_offset + 16; +constant iucr1_t1_offset : natural := iucr1_t0_offset + 14; +constant iucr1_t2_offset : natural := iucr1_t1_offset + 14; +constant iucr1_t3_offset : natural := iucr1_t2_offset + 14; +constant iucr2_t0_offset : natural := iucr1_t3_offset + 14; +constant iucr2_t1_offset : natural := iucr2_t0_offset + 8; +constant iucr2_t2_offset : natural := iucr2_t1_offset + 8; +constant iucr2_t3_offset : natural := iucr2_t2_offset + 8; +constant ppr32_t0_offset : natural := iucr2_t3_offset + 8; +constant ppr32_t1_offset : natural := ppr32_t0_offset + 3; +constant ppr32_t2_offset : natural := ppr32_t1_offset + 3; +constant ppr32_t3_offset : natural := ppr32_t2_offset + 3; +constant ccfg_spare_offset : natural := ppr32_t3_offset + 3; +constant ccfg_scan_right : natural := ccfg_spare_offset + 8 - 1; + + + +constant IMMR0_MASK : std_ulogic_vector(32 to 63) := "11111111111111111111111111111111"; +constant IMR0_MASK : std_ulogic_vector(32 to 63) := "11111111111111111111111111111111"; +constant IULFSR_MASK : std_ulogic_vector(32 to 63) := "11111111111111111111111111111111"; +constant IUDBG0_MASK : std_ulogic_vector(32 to 63) := "00000000000000000011111111000011"; +constant IUDBG1_MASK : std_ulogic_vector(32 to 63) := "00000000000000000000011111111001"; +constant IUDBG2_MASK : std_ulogic_vector(32 to 63) := "00111111111111111111111111111111"; +constant IULLCR_MASK : std_ulogic_vector(32 to 63) := "00000000000000111100001111110001"; +constant IUCR0_MASK : std_ulogic_vector(32 to 63) := "00000000000000001111111111111111"; +constant IUCR1_MASK : std_ulogic_vector(32 to 63) := "00000000000000000011000000111111"; +constant IUCR2_MASK : std_ulogic_vector(32 to 63) := "11111111000000000000000000000000"; +constant PPR32_MASK : std_ulogic_vector(32 to 63) := "00000000000111000000000000000000"; + + +signal spare_l2 : std_ulogic_vector(0 to 3); +signal ccfg_spare_l2 : std_ulogic_vector(0 to 7); + +signal xu_iu_run_thread_d : std_ulogic_vector(0 to 3); +signal xu_iu_run_thread_l2 : std_ulogic_vector(0 to 3); +signal xu_iu_ex6_pri_d : std_ulogic_vector(0 to 2); +signal xu_iu_ex6_pri_l2 : std_ulogic_vector(0 to 2); +signal xu_iu_ex6_pri_val_d : std_ulogic_vector(0 to 3); +signal xu_iu_ex6_pri_val_l2 : std_ulogic_vector(0 to 3); +signal xu_iu_raise_iss_pri_d : std_ulogic_vector(0 to 3); +signal xu_iu_raise_iss_pri_l2 : std_ulogic_vector(0 to 3); +signal xu_iu_msr_gs_d : std_ulogic_vector(0 to 3); +signal xu_iu_msr_gs_l2 : std_ulogic_vector(0 to 3); +signal xu_iu_msr_pr_d : std_ulogic_vector(0 to 3); +signal xu_iu_msr_pr_l2 : std_ulogic_vector(0 to 3); + +signal slowspr_val_d : std_ulogic; +signal slowspr_val_l2 : std_ulogic; +signal slowspr_rw_d : std_ulogic; +signal slowspr_rw_l2 : std_ulogic; +signal slowspr_etid_d : std_ulogic_vector(0 to 1); +signal slowspr_etid_l2 : std_ulogic_vector(0 to 1); +signal slowspr_addr_d : std_ulogic_vector(0 to 9); +signal slowspr_addr_l2 : std_ulogic_vector(0 to 9); +signal slowspr_data_d : std_ulogic_vector(64-(2**regmode) to 63); +signal slowspr_data_l2 : std_ulogic_vector(64-(2**regmode) to 63); +signal slowspr_done_d : std_ulogic; +signal slowspr_done_l2 : std_ulogic; + +signal iu_slowspr_val_d : std_ulogic; +signal iu_slowspr_val_l2 : std_ulogic; +signal iu_slowspr_rw_d : std_ulogic; +signal iu_slowspr_rw_l2 : std_ulogic; +signal iu_slowspr_etid_d : std_ulogic_vector(0 to 1); +signal iu_slowspr_etid_l2 : std_ulogic_vector(0 to 1); +signal iu_slowspr_addr_d : std_ulogic_vector(0 to 9); +signal iu_slowspr_addr_l2 : std_ulogic_vector(0 to 9); +signal iu_slowspr_data_d : std_ulogic_vector(64-(2**regmode) to 63); +signal iu_slowspr_data_l2 : std_ulogic_vector(64-(2**regmode) to 63); +signal iu_slowspr_done_d : std_ulogic; +signal iu_slowspr_done_l2 : std_ulogic; + +signal iu_slowspr_done : std_ulogic; +signal iu_slowspr_data : std_ulogic_vector(64-(2**regmode) to 63); + +signal immr0_sel : std_ulogic; +signal immr0_wren : std_ulogic; +signal immr0_rden : std_ulogic; +signal immr0_d : std_ulogic_vector(32 to 63); +signal immr0_l2 : std_ulogic_vector(32 to 63); + +signal imr0_sel : std_ulogic; +signal imr0_wren : std_ulogic; +signal imr0_rden : std_ulogic; +signal imr0_d : std_ulogic_vector(32 to 63); +signal imr0_l2 : std_ulogic_vector(32 to 63); + +signal iulfsr_sel : std_ulogic; +signal iulfsr_wren : std_ulogic; +signal iulfsr_rden : std_ulogic; +signal iulfsr_d : std_ulogic_vector(32 to 63); +signal iulfsr_l2 : std_ulogic_vector(32 to 63); +signal iulfsr : std_ulogic_vector(1 to 28); +signal iulfsr_act : std_ulogic; + +signal iudbg0_sel : std_ulogic; +signal iudbg0_wren : std_ulogic; +signal iudbg0_rden : std_ulogic; +signal iudbg0_d : std_ulogic_vector(50 to 57); +signal iudbg0_l2 : std_ulogic_vector(50 to 57); +signal iudbg0 : std_ulogic_vector(32 to 63); + +signal iudbg0_exec_wren : std_ulogic; +signal iudbg0_exec_d : std_ulogic; +signal iudbg0_exec_l2 : std_ulogic; +signal iudbg0_done_wren : std_ulogic; +signal iudbg0_done_d : std_ulogic; +signal iudbg0_done_l2 : std_ulogic; + +signal iudbg1_sel : std_ulogic; +signal iudbg1_wren : std_ulogic; +signal iudbg1_rden : std_ulogic; +signal iudbg1_d : std_ulogic_vector(53 to 63); +signal iudbg1_l2 : std_ulogic_vector(53 to 63); +signal iudbg1 : std_ulogic_vector(32 to 63); + +signal iudbg2_sel : std_ulogic; +signal iudbg2_wren : std_ulogic; +signal iudbg2_rden : std_ulogic; +signal iudbg2_d : std_ulogic_vector(34 to 63); +signal iudbg2_l2 : std_ulogic_vector(34 to 63); +signal iudbg2 : std_ulogic_vector(32 to 63); + +signal iullcr_sel : std_ulogic; +signal iullcr_wren : std_ulogic; +signal iullcr_rden : std_ulogic; +signal iullcr_d : std_ulogic_vector(46 to 63); +signal iullcr_l2 : std_ulogic_vector(46 to 63); +signal iullcr : std_ulogic_vector(32 to 63); + +signal iucr0_sel : std_ulogic; +signal iucr0_wren : std_ulogic; +signal iucr0_rden : std_ulogic; +signal iucr0_d : std_ulogic_vector(48 to 63); +signal iucr0_l2 : std_ulogic_vector(48 to 63); +signal iucr0 : std_ulogic_vector(32 to 63); + +signal iucr1_t0_sel : std_ulogic; +signal iucr1_t0_wren : std_ulogic; +signal iucr1_t0_rden : std_ulogic; +signal iucr1_t0_d : std_ulogic_vector(50 to 63); +signal iucr1_t0_l2 : std_ulogic_vector(50 to 63); +signal iucr1_t0 : std_ulogic_vector(32 to 63); + +signal iucr1_t1_sel : std_ulogic; +signal iucr1_t1_wren : std_ulogic; +signal iucr1_t1_rden : std_ulogic; +signal iucr1_t1_d : std_ulogic_vector(50 to 63); +signal iucr1_t1_l2 : std_ulogic_vector(50 to 63); +signal iucr1_t1 : std_ulogic_vector(32 to 63); + +signal iucr1_t2_sel : std_ulogic; +signal iucr1_t2_wren : std_ulogic; +signal iucr1_t2_rden : std_ulogic; +signal iucr1_t2_d : std_ulogic_vector(50 to 63); +signal iucr1_t2_l2 : std_ulogic_vector(50 to 63); +signal iucr1_t2 : std_ulogic_vector(32 to 63); + +signal iucr1_t3_sel : std_ulogic; +signal iucr1_t3_wren : std_ulogic; +signal iucr1_t3_rden : std_ulogic; +signal iucr1_t3_d : std_ulogic_vector(50 to 63); +signal iucr1_t3_l2 : std_ulogic_vector(50 to 63); +signal iucr1_t3 : std_ulogic_vector(32 to 63); + +signal iucr2_t0_sel : std_ulogic; +signal iucr2_t0_wren : std_ulogic; +signal iucr2_t0_rden : std_ulogic; +signal iucr2_t0_d : std_ulogic_vector(32 to 39); +signal iucr2_t0_l2 : std_ulogic_vector(32 to 39); +signal iucr2_t0 : std_ulogic_vector(32 to 63); + +signal iucr2_t1_sel : std_ulogic; +signal iucr2_t1_wren : std_ulogic; +signal iucr2_t1_rden : std_ulogic; +signal iucr2_t1_d : std_ulogic_vector(32 to 39); +signal iucr2_t1_l2 : std_ulogic_vector(32 to 39); +signal iucr2_t1 : std_ulogic_vector(32 to 63); + +signal iucr2_t2_sel : std_ulogic; +signal iucr2_t2_wren : std_ulogic; +signal iucr2_t2_rden : std_ulogic; +signal iucr2_t2_d : std_ulogic_vector(32 to 39); +signal iucr2_t2_l2 : std_ulogic_vector(32 to 39); +signal iucr2_t2 : std_ulogic_vector(32 to 63); + +signal iucr2_t3_sel : std_ulogic; +signal iucr2_t3_wren : std_ulogic; +signal iucr2_t3_rden : std_ulogic; +signal iucr2_t3_d : std_ulogic_vector(32 to 39); +signal iucr2_t3_l2 : std_ulogic_vector(32 to 39); +signal iucr2_t3 : std_ulogic_vector(32 to 63); + +signal ppr32_t0_sel : std_ulogic; +signal ppr32_t0_wren : std_ulogic; +signal ppr32_t0_rden : std_ulogic; +signal ppr32_t0_d : std_ulogic_vector(43 to 45); +signal ppr32_t0_l2 : std_ulogic_vector(43 to 45); +signal ppr32_t0 : std_ulogic_vector(32 to 63); + +signal ppr32_t1_sel : std_ulogic; +signal ppr32_t1_wren : std_ulogic; +signal ppr32_t1_rden : std_ulogic; +signal ppr32_t1_d : std_ulogic_vector(43 to 45); +signal ppr32_t1_l2 : std_ulogic_vector(43 to 45); +signal ppr32_t1 : std_ulogic_vector(32 to 63); + +signal ppr32_t2_sel : std_ulogic; +signal ppr32_t2_wren : std_ulogic; +signal ppr32_t2_rden : std_ulogic; +signal ppr32_t2_d : std_ulogic_vector(43 to 45); +signal ppr32_t2_l2 : std_ulogic_vector(43 to 45); +signal ppr32_t2 : std_ulogic_vector(32 to 63); + +signal ppr32_t3_sel : std_ulogic; +signal ppr32_t3_wren : std_ulogic; +signal ppr32_t3_rden : std_ulogic; +signal ppr32_t3_d : std_ulogic_vector(43 to 45); +signal ppr32_t3_l2 : std_ulogic_vector(43 to 45); +signal ppr32_t3 : std_ulogic_vector(32 to 63); + + + + + +signal lo_pri : std_ulogic_vector(0 to 3); +signal hi_pri : std_ulogic_vector(0 to 3); + + +signal priv_mode : std_ulogic_vector(0 to 3); +signal hypv_mode : std_ulogic_vector(0 to 3); + + +signal hi_pri_level_t0 : std_ulogic_vector(0 to 1); +signal hi_pri_level_t1 : std_ulogic_vector(0 to 1); +signal hi_pri_level_t2 : std_ulogic_vector(0 to 1); +signal hi_pri_level_t3 : std_ulogic_vector(0 to 1); + + +signal iull_en : std_ulogic; +signal ll_trig_dly : std_ulogic_vector(0 to 17); +signal ll_hold_dly : std_ulogic_vector(0 to 9); + +signal ll_trig_rnd_act : std_ulogic; +signal ll_trig_rnd_d : std_ulogic_vector(4 to 17); +signal ll_trig_rnd_l2 : std_ulogic_vector(4 to 17); + +signal ll_trig_cnt_act : std_ulogic; +signal ll_trig_cnt_d : std_ulogic_vector(0 to 17); +signal ll_trig_cnt_l2 : std_ulogic_vector(0 to 17); + +signal ll_hold_cnt_act : std_ulogic; +signal ll_hold_cnt_d : std_ulogic_vector(0 to 9); +signal ll_hold_cnt_l2 : std_ulogic_vector(0 to 9); + +signal ll_rand : std_ulogic; +signal ll_trig : std_ulogic; +signal ll_hold : std_ulogic; + + +signal tiup : std_ulogic; + +signal pc_iu_cfg_sl_thold_1 : std_ulogic; +signal pc_iu_cfg_sl_thold_0 : std_ulogic; +signal pc_iu_cfg_sl_thold_0_b : std_ulogic; +signal pc_iu_func_sl_thold_1 : std_ulogic; +signal pc_iu_func_sl_thold_0 : std_ulogic; +signal pc_iu_func_sl_thold_0_b : std_ulogic; +signal pc_iu_sg_1 : std_ulogic; +signal pc_iu_sg_0 : std_ulogic; +signal forcee : std_ulogic; +signal cfg_force : std_ulogic; +signal dclk : std_ulogic; +signal lclk : clk_logic; + +signal siv : std_ulogic_vector(0 to scan_right); +signal sov : std_ulogic_vector(0 to scan_right); + +signal ccfg_siv : std_ulogic_vector(0 to ccfg_scan_right); +signal ccfg_sov : std_ulogic_vector(0 to ccfg_scan_right); + +begin + + +tiup <= '1'; + + + +ll_trig_rnd_reg: tri_rlmreg_p + generic map (width => ll_trig_rnd_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ll_trig_rnd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(ll_trig_rnd_offset to ll_trig_rnd_offset + ll_trig_rnd_l2'length-1), + scout => sov(ll_trig_rnd_offset to ll_trig_rnd_offset + ll_trig_rnd_l2'length-1), + din => ll_trig_rnd_d, + dout => ll_trig_rnd_l2); + +ll_trig_cnt_reg: tri_rlmreg_p + generic map (width => ll_trig_cnt_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ll_trig_cnt_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(ll_trig_cnt_offset to ll_trig_cnt_offset + ll_trig_cnt_l2'length-1), + scout => sov(ll_trig_cnt_offset to ll_trig_cnt_offset + ll_trig_cnt_l2'length-1), + din => ll_trig_cnt_d, + dout => ll_trig_cnt_l2); + +ll_hold_cnt_reg: tri_rlmreg_p + generic map (width => ll_hold_cnt_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ll_hold_cnt_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(ll_hold_cnt_offset to ll_hold_cnt_offset + ll_hold_cnt_l2'length-1), + scout => sov(ll_hold_cnt_offset to ll_hold_cnt_offset + ll_hold_cnt_l2'length-1), + din => ll_hold_cnt_d, + dout => ll_hold_cnt_l2); + +xu_iu_run_thread_reg: tri_rlmreg_p + generic map (width => xu_iu_run_thread_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_iu_run_thread_offset to xu_iu_run_thread_offset + xu_iu_run_thread_l2'length-1), + scout => sov(xu_iu_run_thread_offset to xu_iu_run_thread_offset + xu_iu_run_thread_l2'length-1), + din => xu_iu_run_thread_d, + dout => xu_iu_run_thread_l2); + +xu_iu_ex6_pri_reg: tri_rlmreg_p + generic map (width => xu_iu_ex6_pri_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_iu_ex6_pri_offset to xu_iu_ex6_pri_offset + xu_iu_ex6_pri_l2'length-1), + scout => sov(xu_iu_ex6_pri_offset to xu_iu_ex6_pri_offset + xu_iu_ex6_pri_l2'length-1), + din => xu_iu_ex6_pri_d, + dout => xu_iu_ex6_pri_l2); + +xu_iu_ex6_pri_val_reg: tri_rlmreg_p + generic map (width => xu_iu_ex6_pri_val_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_iu_ex6_pri_val_offset to xu_iu_ex6_pri_val_offset + xu_iu_ex6_pri_val_l2'length-1), + scout => sov(xu_iu_ex6_pri_val_offset to xu_iu_ex6_pri_val_offset + xu_iu_ex6_pri_val_l2'length-1), + din => xu_iu_ex6_pri_val_d, + dout => xu_iu_ex6_pri_val_l2); + +xu_iu_raise_iss_pri_reg: tri_rlmreg_p + generic map (width => xu_iu_raise_iss_pri_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_iu_raise_iss_pri_offset to xu_iu_raise_iss_pri_offset + xu_iu_raise_iss_pri_l2'length-1), + scout => sov(xu_iu_raise_iss_pri_offset to xu_iu_raise_iss_pri_offset + xu_iu_raise_iss_pri_l2'length-1), + din => xu_iu_raise_iss_pri_d, + dout => xu_iu_raise_iss_pri_l2); + +xu_iu_msr_gs_reg: tri_rlmreg_p + generic map (width => xu_iu_msr_gs_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_iu_msr_gs_offset to xu_iu_msr_gs_offset + xu_iu_msr_gs_l2'length-1), + scout => sov(xu_iu_msr_gs_offset to xu_iu_msr_gs_offset + xu_iu_msr_gs_l2'length-1), + din => xu_iu_msr_gs_d, + dout => xu_iu_msr_gs_l2); + +xu_iu_msr_pr_reg: tri_rlmreg_p + generic map (width => xu_iu_msr_pr_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_iu_msr_pr_offset to xu_iu_msr_pr_offset + xu_iu_msr_pr_l2'length-1), + scout => sov(xu_iu_msr_pr_offset to xu_iu_msr_pr_offset + xu_iu_msr_pr_l2'length-1), + din => xu_iu_msr_pr_d, + dout => xu_iu_msr_pr_l2); + +slowspr_val_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(slowspr_val_offset), + scout => sov(slowspr_val_offset), + din => slowspr_val_d, + dout => slowspr_val_l2); + +slowspr_rw_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(slowspr_rw_offset), + scout => sov(slowspr_rw_offset), + din => slowspr_rw_d, + dout => slowspr_rw_l2); + +slowspr_etid_reg: tri_rlmreg_p + generic map (width => slowspr_etid_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(slowspr_etid_offset to slowspr_etid_offset + slowspr_etid_l2'length-1), + scout => sov(slowspr_etid_offset to slowspr_etid_offset + slowspr_etid_l2'length-1), + din => slowspr_etid_d, + dout => slowspr_etid_l2); + +slowspr_addr_reg: tri_rlmreg_p + generic map (width => slowspr_addr_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(slowspr_addr_offset to slowspr_addr_offset + slowspr_addr_l2'length-1), + scout => sov(slowspr_addr_offset to slowspr_addr_offset + slowspr_addr_l2'length-1), + din => slowspr_addr_d, + dout => slowspr_addr_l2); + +slowspr_data_reg: tri_rlmreg_p + generic map (width => slowspr_data_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(slowspr_data_offset to slowspr_data_offset + slowspr_data_l2'length-1), + scout => sov(slowspr_data_offset to slowspr_data_offset + slowspr_data_l2'length-1), + din => slowspr_data_d, + dout => slowspr_data_l2); + +slowspr_done_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(slowspr_done_offset), + scout => sov(slowspr_done_offset), + din => slowspr_done_d, + dout => slowspr_done_l2); + +iu_slowspr_val_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu_slowspr_val_offset), + scout => sov(iu_slowspr_val_offset), + din => iu_slowspr_val_d, + dout => iu_slowspr_val_l2); + +iu_slowspr_rw_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu_slowspr_val_d, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu_slowspr_rw_offset), + scout => sov(iu_slowspr_rw_offset), + din => iu_slowspr_rw_d, + dout => iu_slowspr_rw_l2); + +iu_slowspr_etid_reg: tri_rlmreg_p + generic map (width => iu_slowspr_etid_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu_slowspr_val_d, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu_slowspr_etid_offset to iu_slowspr_etid_offset + iu_slowspr_etid_l2'length-1), + scout => sov(iu_slowspr_etid_offset to iu_slowspr_etid_offset + iu_slowspr_etid_l2'length-1), + din => iu_slowspr_etid_d, + dout => iu_slowspr_etid_l2); + +iu_slowspr_addr_reg: tri_rlmreg_p + generic map (width => iu_slowspr_addr_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu_slowspr_val_d, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu_slowspr_addr_offset to iu_slowspr_addr_offset + iu_slowspr_addr_l2'length-1), + scout => sov(iu_slowspr_addr_offset to iu_slowspr_addr_offset + iu_slowspr_addr_l2'length-1), + din => iu_slowspr_addr_d, + dout => iu_slowspr_addr_l2); + +iu_slowspr_data_reg: tri_rlmreg_p + generic map (width => iu_slowspr_data_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu_slowspr_val_d, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu_slowspr_data_offset to iu_slowspr_data_offset + iu_slowspr_data_l2'length-1), + scout => sov(iu_slowspr_data_offset to iu_slowspr_data_offset + iu_slowspr_data_l2'length-1), + din => iu_slowspr_data_d, + dout => iu_slowspr_data_l2); + +iu_slowspr_done_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu_slowspr_val_d, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu_slowspr_done_offset), + scout => sov(iu_slowspr_done_offset), + din => iu_slowspr_done_d, + dout => iu_slowspr_done_l2); + +immr0a_reg: tri_ser_rlmreg_p + generic map (width => 16, init => 65535, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => immr0_wren, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(immr0_offset to immr0_offset + 16-1), + scout => sov(immr0_offset to immr0_offset + 16-1), + din => immr0_d(32 to 47), + dout => immr0_l2(32 to 47)); + +immr0b_reg: tri_ser_rlmreg_p + generic map (width => 16, init => 65535, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => immr0_wren, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(immr0_offset + 16 to immr0_offset + immr0_l2'length-1), + scout => sov(immr0_offset + 16 to immr0_offset + immr0_l2'length-1), + din => immr0_d(48 to 63), + dout => immr0_l2(48 to 63)); + +imr0_reg: tri_ser_rlmreg_p + generic map (width => imr0_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => imr0_wren, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(imr0_offset to imr0_offset + imr0_l2'length-1), + scout => sov(imr0_offset to imr0_offset + imr0_l2'length-1), + din => imr0_d, + dout => imr0_l2); + +iulfsr_reg: tri_ser_rlmreg_p + generic map (width => iulfsr_l2'length, init => 26, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iulfsr_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iulfsr_offset to iulfsr_offset + iulfsr_l2'length-1), + scout => sov(iulfsr_offset to iulfsr_offset + iulfsr_l2'length-1), + din => iulfsr_d, + dout => iulfsr_l2); + +iudbg0_reg: tri_ser_rlmreg_p + generic map (width => iudbg0_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iudbg0_wren, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iudbg0_offset to iudbg0_offset + iudbg0_l2'length-1), + scout => sov(iudbg0_offset to iudbg0_offset + iudbg0_l2'length-1), + din => iudbg0_d, + dout => iudbg0_l2); + +iudbg0_done_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iudbg0_done_wren, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iudbg0_done_offset), + scout => sov(iudbg0_done_offset), + din => iudbg0_done_d, + dout => iudbg0_done_l2); + +iudbg0_exec_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iudbg0_exec_wren, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iudbg0_exec_offset), + scout => sov(iudbg0_exec_offset), + din => iudbg0_exec_d, + dout => iudbg0_exec_l2); + +iudbg1_reg: tri_ser_rlmreg_p + generic map (width => iudbg1_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iudbg1_wren, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iudbg1_offset to iudbg1_offset + iudbg1_l2'length-1), + scout => sov(iudbg1_offset to iudbg1_offset + iudbg1_l2'length-1), + din => iudbg1_d, + dout => iudbg1_l2); + +iudbg2_reg: tri_ser_rlmreg_p + generic map (width => iudbg2_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iudbg2_wren, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iudbg2_offset to iudbg2_offset + iudbg2_l2'length-1), + scout => sov(iudbg2_offset to iudbg2_offset + iudbg2_l2'length-1), + din => iudbg2_d, + dout => iudbg2_l2); + +spare_latch: tri_rlmreg_p + generic map (width => spare_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(spare_offset to spare_offset + spare_l2'length-1), + scout => sov(spare_offset to spare_offset + spare_l2'length-1), + din => spare_l2, + dout => spare_l2); + + +iullcr_reg: tri_ser_rlmreg_p + generic map (width => iullcr_l2'length, init => 131136, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iullcr_wren, + thold_b => pc_iu_cfg_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => cfg_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => ccfg_siv(iullcr_offset to iullcr_offset + iullcr_l2'length-1), + scout => ccfg_sov(iullcr_offset to iullcr_offset + iullcr_l2'length-1), + din => iullcr_d, + dout => iullcr_l2); + +iucr0_reg: tri_ser_rlmreg_p + generic map (width => iucr0_l2'length, init => 4346, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iucr0_wren, + thold_b => pc_iu_cfg_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => cfg_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => ccfg_siv(iucr0_offset to iucr0_offset + iucr0_l2'length-1), + scout => ccfg_sov(iucr0_offset to iucr0_offset + iucr0_l2'length-1), + din => iucr0_d, + dout => iucr0_l2); + +iucr1_t0_reg: tri_ser_rlmreg_p + generic map (width => iucr1_t0_l2'length, init => 4096, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iucr1_t0_wren, + thold_b => pc_iu_cfg_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => cfg_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => ccfg_siv(iucr1_t0_offset to iucr1_t0_offset + iucr1_t0_l2'length-1), + scout => ccfg_sov(iucr1_t0_offset to iucr1_t0_offset + iucr1_t0_l2'length-1), + din => iucr1_t0_d, + dout => iucr1_t0_l2); + +iucr1_t1_reg: tri_ser_rlmreg_p + generic map (width => iucr1_t1_l2'length, init => 4096, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iucr1_t1_wren, + thold_b => pc_iu_cfg_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => cfg_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => ccfg_siv(iucr1_t1_offset to iucr1_t1_offset + iucr1_t1_l2'length-1), + scout => ccfg_sov(iucr1_t1_offset to iucr1_t1_offset + iucr1_t1_l2'length-1), + din => iucr1_t1_d, + dout => iucr1_t1_l2); + +iucr1_t2_reg: tri_ser_rlmreg_p + generic map (width => iucr1_t2_l2'length, init => 4096, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iucr1_t2_wren, + thold_b => pc_iu_cfg_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => cfg_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => ccfg_siv(iucr1_t2_offset to iucr1_t2_offset + iucr1_t2_l2'length-1), + scout => ccfg_sov(iucr1_t2_offset to iucr1_t2_offset + iucr1_t2_l2'length-1), + din => iucr1_t2_d, + dout => iucr1_t2_l2); + +iucr1_t3_reg: tri_ser_rlmreg_p + generic map (width => iucr1_t3_l2'length, init => 4096, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iucr1_t3_wren, + thold_b => pc_iu_cfg_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => cfg_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => ccfg_siv(iucr1_t3_offset to iucr1_t3_offset + iucr1_t3_l2'length-1), + scout => ccfg_sov(iucr1_t3_offset to iucr1_t3_offset + iucr1_t3_l2'length-1), + din => iucr1_t3_d, + dout => iucr1_t3_l2); + +iucr2_t0_reg: tri_ser_rlmreg_p + generic map (width => iucr2_t0_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iucr2_t0_wren, + thold_b => pc_iu_cfg_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => cfg_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => ccfg_siv(iucr2_t0_offset to iucr2_t0_offset + iucr2_t0_l2'length-1), + scout => ccfg_sov(iucr2_t0_offset to iucr2_t0_offset + iucr2_t0_l2'length-1), + din => iucr2_t0_d, + dout => iucr2_t0_l2); + +iucr2_t1_reg: tri_ser_rlmreg_p + generic map (width => iucr2_t1_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iucr2_t1_wren, + thold_b => pc_iu_cfg_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => cfg_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => ccfg_siv(iucr2_t1_offset to iucr2_t1_offset + iucr2_t1_l2'length-1), + scout => ccfg_sov(iucr2_t1_offset to iucr2_t1_offset + iucr2_t1_l2'length-1), + din => iucr2_t1_d, + dout => iucr2_t1_l2); + +iucr2_t2_reg: tri_ser_rlmreg_p + generic map (width => iucr2_t2_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iucr2_t2_wren, + thold_b => pc_iu_cfg_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => cfg_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => ccfg_siv(iucr2_t2_offset to iucr2_t2_offset + iucr2_t2_l2'length-1), + scout => ccfg_sov(iucr2_t2_offset to iucr2_t2_offset + iucr2_t2_l2'length-1), + din => iucr2_t2_d, + dout => iucr2_t2_l2); + +iucr2_t3_reg: tri_ser_rlmreg_p + generic map (width => iucr2_t3_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iucr2_t3_wren, + thold_b => pc_iu_cfg_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => cfg_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => ccfg_siv(iucr2_t3_offset to iucr2_t3_offset + iucr2_t3_l2'length-1), + scout => ccfg_sov(iucr2_t3_offset to iucr2_t3_offset + iucr2_t3_l2'length-1), + din => iucr2_t3_d, + dout => iucr2_t3_l2); + +ppr32_t0_reg: tri_ser_rlmreg_p + generic map (width => ppr32_t0_l2'length, init => 3, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ppr32_t0_wren, + thold_b => pc_iu_cfg_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => cfg_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => ccfg_siv(ppr32_t0_offset to ppr32_t0_offset + ppr32_t0_l2'length-1), + scout => ccfg_sov(ppr32_t0_offset to ppr32_t0_offset + ppr32_t0_l2'length-1), + din => ppr32_t0_d, + dout => ppr32_t0_l2); + +ppr32_t1_reg: tri_ser_rlmreg_p + generic map (width => ppr32_t1_l2'length, init => 3, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ppr32_t1_wren, + thold_b => pc_iu_cfg_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => cfg_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => ccfg_siv(ppr32_t1_offset to ppr32_t1_offset + ppr32_t1_l2'length-1), + scout => ccfg_sov(ppr32_t1_offset to ppr32_t1_offset + ppr32_t1_l2'length-1), + din => ppr32_t1_d, + dout => ppr32_t1_l2); + +ppr32_t2_reg: tri_ser_rlmreg_p + generic map (width => ppr32_t2_l2'length, init => 3, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ppr32_t2_wren, + thold_b => pc_iu_cfg_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => cfg_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => ccfg_siv(ppr32_t2_offset to ppr32_t2_offset + ppr32_t2_l2'length-1), + scout => ccfg_sov(ppr32_t2_offset to ppr32_t2_offset + ppr32_t2_l2'length-1), + din => ppr32_t2_d, + dout => ppr32_t2_l2); + +ppr32_t3_reg: tri_ser_rlmreg_p + generic map (width => ppr32_t3_l2'length, init => 3, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ppr32_t3_wren, + thold_b => pc_iu_cfg_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => cfg_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => ccfg_siv(ppr32_t3_offset to ppr32_t3_offset + ppr32_t3_l2'length-1), + scout => ccfg_sov(ppr32_t3_offset to ppr32_t3_offset + ppr32_t3_l2'length-1), + din => ppr32_t3_d, + dout => ppr32_t3_l2); + +ccfg_spare_latch: tri_rlmreg_p + generic map (width => ccfg_spare_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_cfg_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => cfg_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => ccfg_siv(ccfg_spare_offset to ccfg_spare_offset + ccfg_spare_l2'length-1), + scout => ccfg_sov(ccfg_spare_offset to ccfg_spare_offset + ccfg_spare_l2'length-1), + din => ccfg_spare_l2, + dout => ccfg_spare_l2); + + +xu_iu_run_thread_d <= xu_iu_run_thread; +xu_iu_ex6_pri_d <= xu_iu_ex6_pri; +xu_iu_ex6_pri_val_d <= xu_iu_ex6_pri_val; +xu_iu_raise_iss_pri_d <= xu_iu_raise_iss_pri; +xu_iu_msr_gs_d <= xu_iu_msr_gs; +xu_iu_msr_pr_d <= xu_iu_msr_pr; + +slowspr_val_d <= slowspr_val_in; +slowspr_rw_d <= slowspr_rw_in; +slowspr_etid_d <= slowspr_etid_in; +slowspr_addr_d <= slowspr_addr_in; +slowspr_data_d <= slowspr_data_in; +slowspr_done_d <= slowspr_done_in; + +iu_slowspr_val_d <= slowspr_val_l2; +iu_slowspr_rw_d <= slowspr_rw_l2; +iu_slowspr_etid_d <= slowspr_etid_l2; +iu_slowspr_addr_d <= slowspr_addr_l2; +iu_slowspr_data_d <= slowspr_data_l2 or iu_slowspr_data; +iu_slowspr_done_d <= slowspr_done_l2 or iu_slowspr_done; + +slowspr_val_out <= iu_slowspr_val_l2; +slowspr_rw_out <= iu_slowspr_rw_l2; +slowspr_etid_out <= iu_slowspr_etid_l2; +slowspr_addr_out <= iu_slowspr_addr_l2; +slowspr_data_out <= iu_slowspr_data_l2; +slowspr_done_out <= iu_slowspr_done_l2; + + +spr_dec_mask(0 to 31) <= immr0_l2(32 to 63); +spr_dec_match(0 to 31) <= imr0_l2(32 to 63); + +spr_ic_pri_rand <= iulfsr_l2(58) & iulfsr_l2(51) & iulfsr_l2(45) & iulfsr_l2(40) & iulfsr_l2(36); +spr_ic_pri_rand_flush <= iulfsr_l2(60); +spr_ic_pri_rand_always <= iulfsr_l2(61); + +spr_fiss_pri_rand <= iulfsr_l2(32) & iulfsr_l2(35) & iulfsr_l2(39) & iulfsr_l2(44) & iulfsr_l2(50); +spr_fiss_pri_rand_flush <= iulfsr_l2(62); +spr_fiss_pri_rand_always<= iulfsr_l2(63) or ll_hold; + + +spr_ic_clockgate_dis <= iucr0_l2(48 to 49); +spr_ic_cls <= iucr0_l2(50); +spr_ic_icbi_ack_en <= iucr0_l2(51); + +spr_bp_gshare_mask <= "0000" when iucr0_l2(52 to 55) = "0000" else + "1000" when iucr0_l2(52 to 55) = "0001" else + "1100" when iucr0_l2(52 to 55) = "0010" else + "1110" when iucr0_l2(52 to 55) = "0011" else + "1111" ; + +spr_ic_bp_config <= iucr0_l2(56 to 59); +spr_bp_config <= iucr0_l2(60 to 63); + +iu_au_config_iucr_t0 <= iucr2_t0_l2(32 to 39); +iu_au_config_iucr_t1 <= iucr2_t1_l2(32 to 39); +iu_au_config_iucr_t2 <= iucr2_t2_l2(32 to 39); +iu_au_config_iucr_t3 <= iucr2_t3_l2(32 to 39); + +spr_issue_high_mask(0 to 3) <= hi_pri(0 to 3); +spr_issue_med_mask(0 to 3) <= not hi_pri(0 to 3) and not lo_pri(0 to 3); + +spr_fiss_count0_max <= iucr1_t0_l2(58 to 63); +spr_fiss_count1_max <= iucr1_t1_l2(58 to 63); +spr_fiss_count2_max <= iucr1_t2_l2(58 to 63); +spr_fiss_count3_max <= iucr1_t3_l2(58 to 63); + +hi_pri_level_t0 <= iucr1_t0_l2(50 to 51); +hi_pri_level_t1 <= iucr1_t1_l2(50 to 51); +hi_pri_level_t2 <= iucr1_t2_l2(50 to 51); +hi_pri_level_t3 <= iucr1_t3_l2(50 to 51); + +spr_ic_idir_read <= iudbg0_exec_l2; +spr_ic_idir_way <= iudbg0_l2(50 to 51); +spr_ic_idir_row <= iudbg0_l2(52 to 57); + +iull_en <= iullcr_l2(63); + +ll_trig_dly(0 to 3) <= "0001" when iullcr_l2(46 to 49) = "0000" else iullcr_l2(46 to 49); +ll_trig_dly(4 to 17) <= ll_trig_rnd_l2(4 to 17); + +ll_hold_dly(0 to 5) <= iullcr_l2(54 to 59); +ll_hold_dly(6 to 9) <= "0000"; + +ll_trig_rnd_act <= iull_en and ll_rand; +ll_trig_rnd_d(4 to 17) <= iulfsr_l2(32) & iulfsr_l2(33) & iulfsr_l2(35) & iulfsr_l2(36) & + iulfsr_l2(38) & iulfsr_l2(39) & iulfsr_l2(41) & iulfsr_l2(42) & + iulfsr_l2(44) & iulfsr_l2(45) & iulfsr_l2(47) & iulfsr_l2(48) & + iulfsr_l2(50) & iulfsr_l2(51); + +ll_trig_cnt_act <= iull_en and not ll_hold; +ll_trig_cnt_d(0 to 17) <= "000000000000000000" when ll_trig_cnt_l2(0 to 17) = ll_trig_dly(0 to 17) else ll_trig_cnt_l2(0 to 17) + 1; +ll_trig <= ll_trig_cnt_l2(0 to 17) = ll_trig_dly(0 to 17); +ll_rand <= ll_trig_cnt_l2(0 to 3) /= ll_trig_dly(0 to 3); + +ll_hold_cnt_act <= iull_en and (ll_hold or ll_trig); +ll_hold_cnt_d(0 to 9) <= "0000000000" when ll_hold_cnt_l2(0 to 9) = ll_hold_dly(0 to 9) else ll_hold_cnt_l2(0 to 9) + 1; +ll_hold <= iull_en and or_reduce(ll_hold_cnt_l2(0 to 9)); + +spr_fdep_ll_hold <= ll_hold; + + +immr0_sel <= slowspr_val_l2 and slowspr_addr_l2 = "1101110001"; +imr0_sel <= slowspr_val_l2 and slowspr_addr_l2 = "1101110000"; +iulfsr_sel <= slowspr_val_l2 and slowspr_addr_l2 = "1101111011"; +iudbg0_sel <= slowspr_val_l2 and slowspr_addr_l2 = "1101111000"; +iudbg1_sel <= slowspr_val_l2 and slowspr_addr_l2 = "1101111001"; +iudbg2_sel <= slowspr_val_l2 and slowspr_addr_l2 = "1101111010"; +iullcr_sel <= slowspr_val_l2 and slowspr_addr_l2 = "1101111100"; +iucr0_sel <= slowspr_val_l2 and slowspr_addr_l2 = "1111110011"; +iucr1_t0_sel <= slowspr_val_l2 and slowspr_addr_l2 = "1101110011" and slowspr_etid_l2 = "00"; +iucr1_t1_sel <= slowspr_val_l2 and slowspr_addr_l2 = "1101110011" and slowspr_etid_l2 = "01"; +iucr1_t2_sel <= slowspr_val_l2 and slowspr_addr_l2 = "1101110011" and slowspr_etid_l2 = "10"; +iucr1_t3_sel <= slowspr_val_l2 and slowspr_addr_l2 = "1101110011" and slowspr_etid_l2 = "11"; +iucr2_t0_sel <= slowspr_val_l2 and slowspr_addr_l2 = "1101110100" and slowspr_etid_l2 = "00"; +iucr2_t1_sel <= slowspr_val_l2 and slowspr_addr_l2 = "1101110100" and slowspr_etid_l2 = "01"; +iucr2_t2_sel <= slowspr_val_l2 and slowspr_addr_l2 = "1101110100" and slowspr_etid_l2 = "10"; +iucr2_t3_sel <= slowspr_val_l2 and slowspr_addr_l2 = "1101110100" and slowspr_etid_l2 = "11"; +ppr32_t0_sel <= slowspr_val_l2 and slowspr_addr_l2 = "1110000010" and slowspr_etid_l2 = "00"; +ppr32_t1_sel <= slowspr_val_l2 and slowspr_addr_l2 = "1110000010" and slowspr_etid_l2 = "01"; +ppr32_t2_sel <= slowspr_val_l2 and slowspr_addr_l2 = "1110000010" and slowspr_etid_l2 = "10"; +ppr32_t3_sel <= slowspr_val_l2 and slowspr_addr_l2 = "1110000010" and slowspr_etid_l2 = "11"; + +iu_slowspr_done <= immr0_sel or imr0_sel or iulfsr_sel or iullcr_sel or iucr0_sel or + iudbg0_sel or iudbg1_sel or iudbg2_sel or + iucr1_t0_sel or iucr1_t1_sel or iucr1_t2_sel or iucr1_t3_sel or + iucr2_t0_sel or iucr2_t1_sel or iucr2_t2_sel or iucr2_t3_sel or + ppr32_t0_sel or ppr32_t1_sel or ppr32_t2_sel or ppr32_t3_sel; + + + +priv_mode(0 to 3) <= not xu_iu_msr_pr_l2(0 to 3); +hypv_mode(0 to 3) <= not xu_iu_msr_pr_l2(0 to 3) and not xu_iu_msr_gs_l2(0 to 3); + + + +lo_pri(0) <= not xu_iu_raise_iss_pri_l2(0) and + (ppr32_t0_l2(43 to 45) = "000" or + ppr32_t0_l2(43 to 45) = "001" or + ppr32_t0_l2(43 to 45) = "010" ); + +lo_pri(1) <= not xu_iu_raise_iss_pri_l2(1) and + (ppr32_t1_l2(43 to 45) = "000" or + ppr32_t1_l2(43 to 45) = "001" or + ppr32_t1_l2(43 to 45) = "010" ); + +lo_pri(2) <= not xu_iu_raise_iss_pri_l2(2) and + (ppr32_t2_l2(43 to 45) = "000" or + ppr32_t2_l2(43 to 45) = "001" or + ppr32_t2_l2(43 to 45) = "010" ); + +lo_pri(3) <= not xu_iu_raise_iss_pri_l2(3) and + (ppr32_t3_l2(43 to 45) = "000" or + ppr32_t3_l2(43 to 45) = "001" or + ppr32_t3_l2(43 to 45) = "010" ); + + +hi_pri(0) <=(ppr32_t0_l2(43 to 45) = "100" and hi_pri_level_t0(0 to 1) = "00") or + (ppr32_t0_l2(43 to 45) = "101" and (hi_pri_level_t0(0 to 1) = "00" or hi_pri_level_t0(0 to 1) = "01")) or + (ppr32_t0_l2(43 to 45) = "110" and (hi_pri_level_t0(0 to 1) = "00" or hi_pri_level_t0(0 to 1) = "01" or hi_pri_level_t0(0 to 1) = "10")) or + ppr32_t0_l2(43 to 45) = "111" ; + +hi_pri(1) <=(ppr32_t1_l2(43 to 45) = "100" and hi_pri_level_t1(0 to 1) = "00") or + (ppr32_t1_l2(43 to 45) = "101" and (hi_pri_level_t1(0 to 1) = "00" or hi_pri_level_t1(0 to 1) = "01")) or + (ppr32_t1_l2(43 to 45) = "110" and (hi_pri_level_t1(0 to 1) = "00" or hi_pri_level_t1(0 to 1) = "01" or hi_pri_level_t1(0 to 1) = "10")) or + ppr32_t1_l2(43 to 45) = "111" ; + +hi_pri(2) <=(ppr32_t2_l2(43 to 45) = "100" and hi_pri_level_t2(0 to 1) = "00") or + (ppr32_t2_l2(43 to 45) = "101" and (hi_pri_level_t2(0 to 1) = "00" or hi_pri_level_t2(0 to 1) = "01")) or + (ppr32_t2_l2(43 to 45) = "110" and (hi_pri_level_t2(0 to 1) = "00" or hi_pri_level_t2(0 to 1) = "01" or hi_pri_level_t2(0 to 1) = "10")) or + ppr32_t2_l2(43 to 45) = "111" ; + +hi_pri(3) <=(ppr32_t3_l2(43 to 45) = "100" and hi_pri_level_t3(0 to 1) = "00") or + (ppr32_t3_l2(43 to 45) = "101" and (hi_pri_level_t3(0 to 1) = "00" or hi_pri_level_t3(0 to 1) = "01")) or + (ppr32_t3_l2(43 to 45) = "110" and (hi_pri_level_t3(0 to 1) = "00" or hi_pri_level_t3(0 to 1) = "01" or hi_pri_level_t3(0 to 1) = "10")) or + ppr32_t3_l2(43 to 45) = "111" ; + + + + + +iudbg0_exec_wren <= iudbg0_wren or iudbg0_exec_L2; +iudbg0_done_wren <= iudbg0_wren or ic_spr_idir_done; + +iudbg1_wren <= ic_spr_idir_done; +iudbg2_wren <= ic_spr_idir_done; + +immr0_wren <= immr0_sel and slowspr_rw_l2 = '0'; +imr0_wren <= imr0_sel and slowspr_rw_l2 = '0'; +iulfsr_wren <= iulfsr_sel and slowspr_rw_l2 = '0'; +iudbg0_wren <= iudbg0_sel and slowspr_rw_l2 = '0'; +iullcr_wren <= iullcr_sel and slowspr_rw_l2 = '0'; +iucr0_wren <= iucr0_sel and slowspr_rw_l2 = '0'; +iucr1_t0_wren <= iucr1_t0_sel and slowspr_rw_l2 = '0'; +iucr1_t1_wren <= iucr1_t1_sel and slowspr_rw_l2 = '0'; +iucr1_t2_wren <= iucr1_t2_sel and slowspr_rw_l2 = '0'; +iucr1_t3_wren <= iucr1_t3_sel and slowspr_rw_l2 = '0'; +iucr2_t0_wren <= iucr2_t0_sel and slowspr_rw_l2 = '0'; +iucr2_t1_wren <= iucr2_t1_sel and slowspr_rw_l2 = '0'; +iucr2_t2_wren <= iucr2_t2_sel and slowspr_rw_l2 = '0'; +iucr2_t3_wren <= iucr2_t3_sel and slowspr_rw_l2 = '0'; + + + +ppr32_t0_wren <= ((ppr32_t0_sel and slowspr_rw_l2 = '0') or xu_iu_ex6_pri_val_l2(0)) and + ((ppr32_t0_d(43 to 45) = "001" and priv_mode(0)) or + (ppr32_t0_d(43 to 45) = "010" ) or + (ppr32_t0_d(43 to 45) = "011" ) or + (ppr32_t0_d(43 to 45) = "100" ) or + (ppr32_t0_d(43 to 45) = "101" and priv_mode(0)) or + (ppr32_t0_d(43 to 45) = "110" and priv_mode(0)) or + (ppr32_t0_d(43 to 45) = "111" and hypv_mode(0)) ); + +ppr32_t1_wren <= ((ppr32_t1_sel and slowspr_rw_l2 = '0') or xu_iu_ex6_pri_val_l2(1)) and + ((ppr32_t1_d(43 to 45) = "001" and priv_mode(1)) or + (ppr32_t1_d(43 to 45) = "010" ) or + (ppr32_t1_d(43 to 45) = "011" ) or + (ppr32_t1_d(43 to 45) = "100" ) or + (ppr32_t1_d(43 to 45) = "101" and priv_mode(1)) or + (ppr32_t1_d(43 to 45) = "110" and priv_mode(1)) or + (ppr32_t1_d(43 to 45) = "111" and hypv_mode(1)) ); + +ppr32_t2_wren <= ((ppr32_t2_sel and slowspr_rw_l2 = '0') or xu_iu_ex6_pri_val_l2(2)) and + ((ppr32_t2_d(43 to 45) = "001" and priv_mode(2)) or + (ppr32_t2_d(43 to 45) = "010" ) or + (ppr32_t2_d(43 to 45) = "011" ) or + (ppr32_t2_d(43 to 45) = "100" ) or + (ppr32_t2_d(43 to 45) = "101" and priv_mode(2)) or + (ppr32_t2_d(43 to 45) = "110" and priv_mode(2)) or + (ppr32_t2_d(43 to 45) = "111" and hypv_mode(2)) ); + +ppr32_t3_wren <= ((ppr32_t3_sel and slowspr_rw_l2 = '0') or xu_iu_ex6_pri_val_l2(3)) and + ((ppr32_t3_d(43 to 45) = "001" and priv_mode(3)) or + (ppr32_t3_d(43 to 45) = "010" ) or + (ppr32_t3_d(43 to 45) = "011" ) or + (ppr32_t3_d(43 to 45) = "100" ) or + (ppr32_t3_d(43 to 45) = "101" and priv_mode(3)) or + (ppr32_t3_d(43 to 45) = "110" and priv_mode(3)) or + (ppr32_t3_d(43 to 45) = "111" and hypv_mode(3)) ); + + + + +iudbg0_exec_d <= IUDBG0_MASK(62) and slowspr_data_l2(62) when iudbg0_wren = '1' else '0'; +iudbg0_done_d <= IUDBG0_MASK(63) and slowspr_data_l2(63) when iudbg0_wren = '1' else ic_spr_idir_done; + +iudbg1_d <= IUDBG1_MASK(53 to 63) and (ic_spr_idir_lru(0 to 2) & ic_spr_idir_parity(0 to 3) & ic_spr_idir_endian & "00" & ic_spr_idir_valid); +iudbg2_d <= IUDBG2_MASK(34 to 63) and ic_spr_idir_tag(0 to 29); + +immr0_d <= IMMR0_MASK and slowspr_data_l2(32 to 63); +imr0_d <= IMR0_MASK and slowspr_data_l2(32 to 63); + + +iulfsr(1 to 28) <= iulfsr_l2(32 to 59); +iulfsr_d <= IULFSR_MASK and slowspr_data_l2(32 to 63) when iulfsr_wren = '1' else + (iulfsr(28) xor iulfsr(27) xor iulfsr(26) xor iulfsr(25) xor iulfsr(24) xor iulfsr(8)) & iulfsr(1 to 27) & iulfsr_l2(60 to 63); +iulfsr_act <= iulfsr_wren or or_reduce(xu_iu_run_thread_l2(0 to 3)); + +iudbg0_d <= IUDBG0_MASK(50 to 57) and slowspr_data_l2(50 to 57); +iullcr_d <= IULLCR_MASK(46 to 63) and slowspr_data_l2(46 to 63); +iucr0_d <= IUCR0_MASK(48 to 63) and (slowspr_data_l2(48 to 49) & iucr0_L2(50) & slowspr_data_l2(51 to 63)); + +iucr1_t0_d <= IUCR1_MASK(50 to 63) and slowspr_data_l2(50 to 63); +iucr1_t1_d <= IUCR1_MASK(50 to 63) and slowspr_data_l2(50 to 63); +iucr1_t2_d <= IUCR1_MASK(50 to 63) and slowspr_data_l2(50 to 63); +iucr1_t3_d <= IUCR1_MASK(50 to 63) and slowspr_data_l2(50 to 63); + +iucr2_t0_d <= IUCR2_MASK(32 to 39) and slowspr_data_l2(32 to 39); +iucr2_t1_d <= IUCR2_MASK(32 to 39) and slowspr_data_l2(32 to 39); +iucr2_t2_d <= IUCR2_MASK(32 to 39) and slowspr_data_l2(32 to 39); +iucr2_t3_d <= IUCR2_MASK(32 to 39) and slowspr_data_l2(32 to 39); + + + +ppr32_t0_d <= PPR32_MASK(43 to 45) and xu_iu_ex6_pri_l2(0 to 2) when xu_iu_ex6_pri_val_l2(0) = '1' else + PPR32_MASK(43 to 45) and slowspr_data_l2(43 to 45); +ppr32_t1_d <= PPR32_MASK(43 to 45) and xu_iu_ex6_pri_l2(0 to 2) when xu_iu_ex6_pri_val_l2(1) = '1' else + PPR32_MASK(43 to 45) and slowspr_data_l2(43 to 45); +ppr32_t2_d <= PPR32_MASK(43 to 45) and xu_iu_ex6_pri_l2(0 to 2) when xu_iu_ex6_pri_val_l2(2) = '1' else + PPR32_MASK(43 to 45) and slowspr_data_l2(43 to 45); +ppr32_t3_d <= PPR32_MASK(43 to 45) and xu_iu_ex6_pri_l2(0 to 2) when xu_iu_ex6_pri_val_l2(3) = '1' else + PPR32_MASK(43 to 45) and slowspr_data_l2(43 to 45); + + + + +immr0_rden <= immr0_sel and slowspr_rw_l2 = '1'; +imr0_rden <= imr0_sel and slowspr_rw_l2 = '1'; +iulfsr_rden <= iulfsr_sel and slowspr_rw_l2 = '1'; +iudbg0_rden <= iudbg0_sel and slowspr_rw_l2 = '1'; +iudbg1_rden <= iudbg1_sel and slowspr_rw_l2 = '1'; +iudbg2_rden <= iudbg2_sel and slowspr_rw_l2 = '1'; +iullcr_rden <= iullcr_sel and slowspr_rw_l2 = '1'; +iucr0_rden <= iucr0_sel and slowspr_rw_l2 = '1'; +iucr1_t0_rden <= iucr1_t0_sel and slowspr_rw_l2 = '1'; +iucr1_t1_rden <= iucr1_t1_sel and slowspr_rw_l2 = '1'; +iucr1_t2_rden <= iucr1_t2_sel and slowspr_rw_l2 = '1'; +iucr1_t3_rden <= iucr1_t3_sel and slowspr_rw_l2 = '1'; +iucr2_t0_rden <= iucr2_t0_sel and slowspr_rw_l2 = '1'; +iucr2_t1_rden <= iucr2_t1_sel and slowspr_rw_l2 = '1'; +iucr2_t2_rden <= iucr2_t2_sel and slowspr_rw_l2 = '1'; +iucr2_t3_rden <= iucr2_t3_sel and slowspr_rw_l2 = '1'; +ppr32_t0_rden <= ppr32_t0_sel and slowspr_rw_l2 = '1'; +ppr32_t1_rden <= ppr32_t1_sel and slowspr_rw_l2 = '1'; +ppr32_t2_rden <= ppr32_t2_sel and slowspr_rw_l2 = '1'; +ppr32_t3_rden <= ppr32_t3_sel and slowspr_rw_l2 = '1'; + +r64: if (regmode > 5) generate begin +iu_slowspr_data(0 to 31) <= (others => '0'); +end generate; +iu_slowspr_data(32 to 63) <= immr0_L2 when immr0_rden = '1' else + imr0_L2 when imr0_rden = '1' else + iulfsr_L2 when iulfsr_rden = '1' else + iudbg0 when iudbg0_rden = '1' else + iudbg1 when iudbg1_rden = '1' else + iudbg2 when iudbg2_rden = '1' else + iullcr when iullcr_rden = '1' else + iucr0 when iucr0_rden = '1' else + iucr1_t0 when iucr1_t0_rden = '1' else + iucr1_t1 when iucr1_t1_rden = '1' else + iucr1_t2 when iucr1_t2_rden = '1' else + iucr1_t3 when iucr1_t3_rden = '1' else + iucr2_t0 when iucr2_t0_rden = '1' else + iucr2_t1 when iucr2_t1_rden = '1' else + iucr2_t2 when iucr2_t2_rden = '1' else + iucr2_t3 when iucr2_t3_rden = '1' else + ppr32_t0 when ppr32_t0_rden = '1' else + ppr32_t1 when ppr32_t1_rden = '1' else + ppr32_t2 when ppr32_t2_rden = '1' else + ppr32_t3 when ppr32_t3_rden = '1' else + (others => '0'); + + +iudbg0(32 to 63) <= IUDBG0_MASK(32 to 49) & iudbg0_L2(50 to 57) & IUDBG0_MASK(58 to 61) & iudbg0_exec_L2 & iudbg0_done_L2; +iudbg1(32 to 63) <= IUDBG1_MASK(32 to 52) & iudbg1_L2(53 to 63); +iudbg2(32 to 63) <= IUDBG2_MASK(32 to 33) & iudbg2_L2(34 to 63); + +iullcr(32 to 63) <= IULLCR_MASK(32 to 45) & iullcr_L2(46 to 63); +iucr0(32 to 63) <= IUCR0_MASK(32 to 47) & iucr0_L2(48 to 63); + +iucr1_t0(32 to 63) <= IUCR1_MASK(32 to 49) & iucr1_t0_L2(50 to 63); +iucr1_t1(32 to 63) <= IUCR1_MASK(32 to 49) & iucr1_t1_L2(50 to 63); +iucr1_t2(32 to 63) <= IUCR1_MASK(32 to 49) & iucr1_t2_L2(50 to 63); +iucr1_t3(32 to 63) <= IUCR1_MASK(32 to 49) & iucr1_t3_L2(50 to 63); + +iucr2_t0(32 to 63) <= iucr2_t0_L2(32 to 39) & IUCR2_MASK(40 to 63); +iucr2_t1(32 to 63) <= iucr2_t1_L2(32 to 39) & IUCR2_MASK(40 to 63); +iucr2_t2(32 to 63) <= iucr2_t2_L2(32 to 39) & IUCR2_MASK(40 to 63); +iucr2_t3(32 to 63) <= iucr2_t3_L2(32 to 39) & IUCR2_MASK(40 to 63); + +ppr32_t0(32 to 63) <= PPR32_MASK(32 to 42) & ppr32_t0_L2(43 to 45) & PPR32_MASK(46 to 63); +ppr32_t1(32 to 63) <= PPR32_MASK(32 to 42) & ppr32_t1_L2(43 to 45) & PPR32_MASK(46 to 63); +ppr32_t2(32 to 63) <= PPR32_MASK(32 to 42) & ppr32_t2_L2(43 to 45) & PPR32_MASK(46 to 63); +ppr32_t3(32 to 63) <= PPR32_MASK(32 to 42) & ppr32_t3_L2(43 to 45) & PPR32_MASK(46 to 63); + + + + + +perv_2to1_reg: tri_plat + generic map (width => 3, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_iu_func_sl_thold_2, + din(1) => pc_iu_sg_2, + din(2) => pc_iu_cfg_sl_thold_2, + q(0) => pc_iu_func_sl_thold_1, + q(1) => pc_iu_sg_1, + q(2) => pc_iu_cfg_sl_thold_1); + +perv_1to0_reg: tri_plat + generic map (width => 3, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_iu_func_sl_thold_1, + din(1) => pc_iu_sg_1, + din(2) => pc_iu_cfg_sl_thold_1, + q(0) => pc_iu_func_sl_thold_0, + q(1) => pc_iu_sg_0, + q(2) => pc_iu_cfg_sl_thold_0); + +perv_lcbor: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_b, + thold => pc_iu_func_sl_thold_0, + sg => pc_iu_sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => pc_iu_func_sl_thold_0_b); + +cfg_perv_lcbor: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_b, + thold => pc_iu_cfg_sl_thold_0, + sg => pc_iu_sg_0, + act_dis => act_dis, + forcee => cfg_force, + thold_b => pc_iu_cfg_sl_thold_0_b); + + + +slat_lcb: tri_lcbs + generic map (expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + delay_lclkr => delay_lclkr, + nclk => nclk, + forcee => cfg_force, + thold_b => pc_iu_cfg_sl_thold_0_b, + dclk => dclk, + lclk => lclk ); + +repower_latch: tri_slat_scan + generic map (width => 2, init => "00", expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + dclk => dclk, + lclk => lclk, + scan_in(0) => bcfg_scan_in, + scan_in(1) => dcfg_scan_in, + scan_out(0) => bcfg_scan_out, + scan_out(1) => dcfg_scan_out, + q => open, + q_b => open); + + + + + + +siv(0 to scan_right) <= scan_in & sov(0 to scan_right-1); +scan_out <= sov(scan_right); + +ccfg_siv(0 to ccfg_scan_right) <= ccfg_scan_in & ccfg_sov(0 to ccfg_scan_right-1); +ccfg_scan_out <= ccfg_sov(ccfg_scan_right); + +end iuq_spr; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_uc.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_uc.vhdl new file mode 100644 index 0000000..00f2057 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_uc.vhdl @@ -0,0 +1,2166 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee,ibm,support,tri,work; +use ieee.std_logic_1164.all; +use ibm.std_ulogic_unsigned.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use support.power_logic_pkg.all; +use tri.tri_latches_pkg.all; +use work.iuq_pkg.all; + +entity iuq_uc is + generic(ucode_width : integer := 71; + uc_ifar : integer := 21; + regmode : integer := 6; + expand_type : integer := 2); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + pc_iu_func_sl_thold_2 : in std_ulogic; + pc_iu_sg_2 : in std_ulogic; + an_ac_scan_dis_dc_b : in std_ulogic; + tc_ac_ccflush_dc : in std_ulogic; + clkoff_b : in std_ulogic; + delay_lclkr : in std_ulogic; + mpw1_b : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + spr_ic_clockgate_dis : in std_ulogic; + + iu_pc_err_ucode_illegal : out std_ulogic_vector(0 to 3); + + xu_iu_spr_xer0 : in std_ulogic_vector(57 to 63); + xu_iu_spr_xer1 : in std_ulogic_vector(57 to 63); + xu_iu_spr_xer2 : in std_ulogic_vector(57 to 63); + xu_iu_spr_xer3 : in std_ulogic_vector(57 to 63); + + + xu_iu_flush : in std_ulogic_vector(0 to 3); + xu_iu_ucode_restart : in std_ulogic_vector(0 to 3); + xu_iu_uc_flush_ifar0 : in std_ulogic_vector(62-uc_ifar to 61); + xu_iu_uc_flush_ifar1 : in std_ulogic_vector(62-uc_ifar to 61); + xu_iu_uc_flush_ifar2 : in std_ulogic_vector(62-uc_ifar to 61); + xu_iu_uc_flush_ifar3 : in std_ulogic_vector(62-uc_ifar to 61); + + uc_flush_tid : out std_ulogic_vector(0 to 3); + + fiss_uc_is2_ucode_vld : in std_ulogic; + fiss_uc_is2_tid : in std_ulogic_vector(0 to 3); + fiss_uc_is2_instr : in std_ulogic_vector(0 to 31); + fiss_uc_is2_2ucode : in std_ulogic; + fiss_uc_is2_2ucode_type : in std_ulogic; + + ib_uc_buff0_avail : in std_ulogic; + ib_uc_buff1_avail : in std_ulogic; + ib_uc_buff2_avail : in std_ulogic; + ib_uc_buff3_avail : in std_ulogic; + + uc_ib_iu4_valid_tid : out std_ulogic_vector(0 to 3); + uc_ib_iu4_ifar : out std_ulogic_vector(62-uc_ifar to 61); + uc_ib_iu4_instr : out std_ulogic_vector(0 to 31); + uc_ib_iu4_is_ucode : out std_ulogic; + uc_ib_iu4_ext : out std_ulogic_vector(0 to 3); + + uc_ic_hold_thread : out std_ulogic_vector(0 to 3); + + pc_iu_trace_bus_enable : in std_ulogic; + uc_dbg_data : out std_ulogic_vector(0 to 87) + +); +-- synopsys translate_off +-- synopsys translate_on +end iuq_uc; +ARCHITECTURE IUQ_UC + OF IUQ_UC + IS +SIGNAL GET_ADDRESS_PT : STD_ULOGIC_VECTOR(1 TO 96) := +(OTHERS=> 'U'); +SIGNAL ROM_ISSUE_TABLE_PT : STD_ULOGIC_VECTOR(1 TO 16) := +(OTHERS=> 'U'); +SIGNAL force_ep : STD_ULOGIC := +'U'; +SIGNAL late_end : STD_ULOGIC := +'U'; +SIGNAL romtoken_L2 : STD_ULOGIC_VECTOR(0 TO 3) := +"UUUU"; +SIGNAL romtoken_d : STD_ULOGIC_VECTOR(0 TO 3) := +"UUUU"; +SIGNAL start_addr : STD_ULOGIC_VECTOR(0 TO 9) := +"UUUUUUUUUU"; +SIGNAL uc_legal : STD_ULOGIC := +'U'; +SIGNAL vld_fast : STD_ULOGIC_VECTOR(0 TO 3) := +"UUUU"; +SIGNAL xer_type : STD_ULOGIC := +'U'; +constant xu_iu_flush_offset : natural := 0; +constant xu_iu_ucode_restart_offset : natural := xu_iu_flush_offset + 4; +constant xu_iu_uc_flush_ifar0_offset : natural := xu_iu_ucode_restart_offset + 4; +constant xu_iu_uc_flush_ifar1_offset : natural := xu_iu_uc_flush_ifar0_offset + uc_ifar; +constant xu_iu_uc_flush_ifar2_offset : natural := xu_iu_uc_flush_ifar1_offset + uc_ifar; +constant xu_iu_uc_flush_ifar3_offset : natural := xu_iu_uc_flush_ifar2_offset + uc_ifar; +constant iu_pc_err_ucode_illegal_offset : natural := xu_iu_uc_flush_ifar3_offset + uc_ifar; +constant ib_uc_buff_avail_offset : natural := iu_pc_err_ucode_illegal_offset + 4; +constant fiss_uc_is2_ucode_vld_offset : natural := ib_uc_buff_avail_offset + 4; +constant fiss_uc_is2_tid_offset : natural := fiss_uc_is2_ucode_vld_offset + 1; +constant fiss_uc_is2_instr_offset : natural := fiss_uc_is2_tid_offset + 4; +constant fiss_uc_is2_2ucode_offset : natural := fiss_uc_is2_instr_offset + 32; +constant fiss_uc_is2_2ucode_type_offset : natural := fiss_uc_is2_2ucode_offset + 1; +constant romtoken_offset : natural := fiss_uc_is2_2ucode_type_offset + 1; +constant romvalid_offset : natural := romtoken_offset + 4; +constant rom_data_late_offset : natural := romvalid_offset + 4; +constant iu4_valid_tid_offset : natural := rom_data_late_offset + 32; +constant iu4_data_tid_offset : natural := iu4_valid_tid_offset + 4; +constant iu4_ifar_offset : natural := iu4_data_tid_offset + 4; +constant iu4_is_ucode_offset : natural := iu4_ifar_offset + uc_ifar; +constant iu4_ext_offset : natural := iu4_is_ucode_offset + 1; +constant iu5_valid_tid_offset : natural := iu4_ext_offset + 4; +constant iu5_ifar_offset : natural := iu5_valid_tid_offset + 4; +constant uc_dbg_data_offset : natural := iu5_ifar_offset + uc_ifar; +constant spare_offset : natural := uc_dbg_data_offset + 16; +constant trace_bus_enable_offset: natural := spare_offset + 12; +constant scan_right : natural := trace_bus_enable_offset + 1 - 1; +signal trace_bus_enable_d : std_ulogic; +signal trace_bus_enable_q : std_ulogic; +signal iu_pc_err_ucode_illegal_d : std_ulogic_vector(0 to 3); +signal iu_pc_err_ucode_illegal_l2 : std_ulogic_vector(0 to 3); +signal fiss_uc_is2_ucode_vld_d : std_ulogic; +signal fiss_uc_is2_tid_d : std_ulogic_vector(0 to 3); +signal fiss_uc_is2_instr_d : std_ulogic_vector(0 to 31); +signal fiss_uc_is2_2ucode_d : std_ulogic; +signal fiss_uc_is2_2ucode_type_d: std_ulogic; +signal fiss_uc_is2_ucode_vld_l2 : std_ulogic; +signal fiss_uc_is2_tid_l2 : std_ulogic_vector(0 to 3); +signal fiss_uc_is2_instr_l2 : std_ulogic_vector(0 to 31); +signal fiss_uc_is2_2ucode_l2 : std_ulogic; +signal fiss_uc_is2_2ucode_type_l2 : std_ulogic; +signal romvalid_d : std_ulogic_vector(0 to 3); +signal romvalid_l2 : std_ulogic_vector(0 to 3); +signal xu_iu_flush_d : std_ulogic_vector(0 to 3); +signal xu_iu_flush_l2 : std_ulogic_vector(0 to 3); +signal xu_iu_ucode_restart_d : std_ulogic_vector(0 to 3); +signal xu_iu_ucode_restart_l2 : std_ulogic_vector(0 to 3); +signal xu_iu_uc_flush_ifar0_d : std_ulogic_vector(62-uc_ifar to 61); +signal xu_iu_uc_flush_ifar0_l2 : std_ulogic_vector(62-uc_ifar to 61); +signal xu_iu_uc_flush_ifar1_d : std_ulogic_vector(62-uc_ifar to 61); +signal xu_iu_uc_flush_ifar1_l2 : std_ulogic_vector(62-uc_ifar to 61); +signal xu_iu_uc_flush_ifar2_d : std_ulogic_vector(62-uc_ifar to 61); +signal xu_iu_uc_flush_ifar2_l2 : std_ulogic_vector(62-uc_ifar to 61); +signal xu_iu_uc_flush_ifar3_d : std_ulogic_vector(62-uc_ifar to 61); +signal xu_iu_uc_flush_ifar3_l2 : std_ulogic_vector(62-uc_ifar to 61); +signal iu4_valid_tid_d : std_ulogic_vector(0 to 3); +signal iu4_data_tid_d : std_ulogic_vector(0 to 3); +signal iu4_ifar_d : std_ulogic_vector(62-uc_ifar to 61); +signal iu4_is_ucode_d : std_ulogic; +signal iu4_ext_d : std_ulogic_vector(0 to 3); +signal iu4_valid_tid_l2 : std_ulogic_vector(0 to 3); +signal iu4_data_tid_l2 : std_ulogic_vector(0 to 3); +signal iu4_ifar_l2 : std_ulogic_vector(62-uc_ifar to 61); +signal iu4_instr_l2 : std_ulogic_vector(0 to 31); +signal iu4_is_ucode_l2 : std_ulogic; +signal iu4_ext_l2 : std_ulogic_vector(0 to 3); +signal iu5_ifar_l2 : std_ulogic_vector(62-uc_ifar to 61); +signal ib_uc_buff_avail_d : std_ulogic_vector(0 to 3); +signal ib_uc_buff_avail_l2 : std_ulogic_vector(0 to 3); +signal spare_l2 : std_ulogic_vector(0 to 11); +signal load_command : std_ulogic_vector(0 to 3); +signal early_end : std_ulogic; +signal new_cond : std_ulogic; +signal rom_ra0 : std_ulogic_vector(0 to 9); +signal ucode_ifar0 : std_ulogic_vector(62-uc_ifar to 61); +signal ucode_instr0 : std_ulogic_vector(0 to 31); +signal ucode_is_ucode0: std_ulogic; +signal ucode_ext0 : std_ulogic_vector(0 to 3); +signal rom_ra1 : std_ulogic_vector(0 to 9); +signal ucode_ifar1 : std_ulogic_vector(62-uc_ifar to 61); +signal ucode_instr1 : std_ulogic_vector(0 to 31); +signal ucode_is_ucode1: std_ulogic; +signal ucode_ext1 : std_ulogic_vector(0 to 3); +signal rom_ra2 : std_ulogic_vector(0 to 9); +signal ucode_ifar2 : std_ulogic_vector(62-uc_ifar to 61); +signal ucode_instr2 : std_ulogic_vector(0 to 31); +signal ucode_is_ucode2: std_ulogic; +signal ucode_ext2 : std_ulogic_vector(0 to 3); +signal rom_ra3 : std_ulogic_vector(0 to 9); +signal ucode_ifar3 : std_ulogic_vector(62-uc_ifar to 61); +signal ucode_instr3 : std_ulogic_vector(0 to 31); +signal ucode_is_ucode3: std_ulogic; +signal ucode_ext3 : std_ulogic_vector(0 to 3); +signal ucode_valid : std_ulogic_vector(0 to 3); +signal uc_control_dbg_data0 : std_ulogic_vector(0 to 3); +signal uc_control_dbg_data1 : std_ulogic_vector(0 to 3); +signal uc_control_dbg_data2 : std_ulogic_vector(0 to 3); +signal uc_control_dbg_data3 : std_ulogic_vector(0 to 3); +signal uc_act : std_ulogic_vector(0 to 3); +signal uc_any_act : std_ulogic; +signal rom_act : std_ulogic; +signal rom_addr : std_ulogic_vector(0 to 9); +signal rom_data_tid : std_ulogic_vector(0 to 3); +signal data_valid : std_ulogic_vector(0 to 3); +signal rom_data : std_ulogic_vector(0 to ucode_width-1); +signal rom_data_late_d : std_ulogic_vector(0 to 31); +signal rom_data_late_l2 : std_ulogic_vector(0 to 31); +signal iu4_stage_act : std_ulogic; +signal ib_flush : std_ulogic_vector(0 to 3); +signal vld_mask : std_ulogic_vector(0 to 3); +signal pc_iu_func_sl_thold_1 : std_ulogic; +signal pc_iu_func_sl_thold_0 : std_ulogic; +signal pc_iu_func_sl_thold_0_b : std_ulogic; +signal pc_iu_sg_1 : std_ulogic; +signal pc_iu_sg_0 : std_ulogic; +signal forcee : std_ulogic; +signal siv : std_ulogic_vector(0 to scan_right+5); +signal sov : std_ulogic_vector(0 to scan_right+5); +signal tiup : std_ulogic; +signal act_dis : std_ulogic; +signal d_mode : std_ulogic; +signal mpw2_b : std_ulogic; +signal uc_dbg_data_d : std_ulogic_vector(44 to 59); +signal uc_dbg_data_l2 : std_ulogic_vector(44 to 59); +-- synopsys translate_off +-- synopsys translate_on + BEGIN + +tiup <= '1'; +act_dis <= '0'; +d_mode <= '0'; +mpw2_b <= '1'; +fiss_uc_is2_ucode_vld_d <= fiss_uc_is2_ucode_vld; +fiss_uc_is2_tid_d <= fiss_uc_is2_tid and not xu_iu_flush; +fiss_uc_is2_instr_d <= fiss_uc_is2_instr; +fiss_uc_is2_2ucode_d <= fiss_uc_is2_2ucode; +fiss_uc_is2_2ucode_type_d <= fiss_uc_is2_2ucode_type; +load_command <= gate_and(fiss_uc_is2_ucode_vld_l2, fiss_uc_is2_tid_l2); +uc_flush_tid <= gate_and(fiss_uc_is2_ucode_vld_l2, fiss_uc_is2_tid_l2); +early_end <= not late_end; +new_cond <= not fiss_uc_is2_2ucode_type_l2; +MQQ1:GET_ADDRESS_PT(1) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(24) & FISS_UC_IS2_INSTR_L2(25) & + FISS_UC_IS2_INSTR_L2(26) & FISS_UC_IS2_INSTR_L2(27) & + FISS_UC_IS2_INSTR_L2(28) & FISS_UC_IS2_INSTR_L2(29) & + FISS_UC_IS2_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("011111101011111")); +MQQ2:GET_ADDRESS_PT(2) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("0111110000111010")); +MQQ3:GET_ADDRESS_PT(3) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("0111111000010101")); +MQQ4:GET_ADDRESS_PT(4) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) & + FISS_UC_IS2_2UCODE_L2 ) , STD_ULOGIC_VECTOR'("01111101011101011")); +MQQ5:GET_ADDRESS_PT(5) <= + Eq(( FISS_UC_IS2_INSTR_L2(1) & FISS_UC_IS2_INSTR_L2(2) & + FISS_UC_IS2_INSTR_L2(3) & FISS_UC_IS2_INSTR_L2(4) & + FISS_UC_IS2_INSTR_L2(5) & FISS_UC_IS2_INSTR_L2(21) & + FISS_UC_IS2_INSTR_L2(22) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("11111011111010")); +MQQ6:GET_ADDRESS_PT(6) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("0111111000000000")); +MQQ7:GET_ADDRESS_PT(7) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(4) & + FISS_UC_IS2_INSTR_L2(5) & FISS_UC_IS2_INSTR_L2(21) & + FISS_UC_IS2_INSTR_L2(22) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("00000111001110")); +MQQ8:GET_ADDRESS_PT(8) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) & + FISS_UC_IS2_2UCODE_L2 ) , STD_ULOGIC_VECTOR'("01111100001101011")); +MQQ9:GET_ADDRESS_PT(9) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("0111111110010110")); +MQQ10:GET_ADDRESS_PT(10) <= + Eq(( FISS_UC_IS2_INSTR_L2(1) & FISS_UC_IS2_INSTR_L2(2) & + FISS_UC_IS2_INSTR_L2(3) & FISS_UC_IS2_INSTR_L2(4) & + FISS_UC_IS2_INSTR_L2(5) & FISS_UC_IS2_INSTR_L2(21) & + FISS_UC_IS2_INSTR_L2(22) & FISS_UC_IS2_INSTR_L2(23) & + FISS_UC_IS2_INSTR_L2(24) & FISS_UC_IS2_INSTR_L2(25) & + FISS_UC_IS2_INSTR_L2(26) & FISS_UC_IS2_INSTR_L2(27) & + FISS_UC_IS2_INSTR_L2(28) & FISS_UC_IS2_INSTR_L2(29) & + FISS_UC_IS2_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("111110111111010")); +MQQ11:GET_ADDRESS_PT(11) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(24) & FISS_UC_IS2_INSTR_L2(25) & + FISS_UC_IS2_INSTR_L2(26) & FISS_UC_IS2_INSTR_L2(27) & + FISS_UC_IS2_INSTR_L2(28) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("01111100001111")); +MQQ12:GET_ADDRESS_PT(12) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(26) & FISS_UC_IS2_INSTR_L2(27) & + FISS_UC_IS2_INSTR_L2(28) & FISS_UC_IS2_INSTR_L2(29) & + FISS_UC_IS2_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("011111101010111")); +MQQ13:GET_ADDRESS_PT(13) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("01111100011111")); +MQQ14:GET_ADDRESS_PT(14) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(26) & FISS_UC_IS2_INSTR_L2(27) & + FISS_UC_IS2_INSTR_L2(28) & FISS_UC_IS2_INSTR_L2(29) & + FISS_UC_IS2_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("011111010110111")); +MQQ15:GET_ADDRESS_PT(15) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(26) & FISS_UC_IS2_INSTR_L2(27) & + FISS_UC_IS2_INSTR_L2(28) & FISS_UC_IS2_INSTR_L2(29) & + FISS_UC_IS2_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("011111100010111")); +MQQ16:GET_ADDRESS_PT(16) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("0111110101010101")); +MQQ17:GET_ADDRESS_PT(17) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) & + FISS_UC_IS2_2UCODE_L2 ) , STD_ULOGIC_VECTOR'("01111101011101010")); +MQQ18:GET_ADDRESS_PT(18) <= + Eq(( FISS_UC_IS2_INSTR_L2(1) & FISS_UC_IS2_INSTR_L2(2) & + FISS_UC_IS2_INSTR_L2(3) & FISS_UC_IS2_INSTR_L2(4) & + FISS_UC_IS2_INSTR_L2(5) & FISS_UC_IS2_INSTR_L2(21) & + FISS_UC_IS2_INSTR_L2(22) & FISS_UC_IS2_INSTR_L2(23) & + FISS_UC_IS2_INSTR_L2(24) & FISS_UC_IS2_INSTR_L2(25) & + FISS_UC_IS2_INSTR_L2(26) & FISS_UC_IS2_INSTR_L2(27) & + FISS_UC_IS2_INSTR_L2(28) & FISS_UC_IS2_INSTR_L2(29) & + FISS_UC_IS2_INSTR_L2(30) & FISS_UC_IS2_2UCODE_L2 + ) , STD_ULOGIC_VECTOR'("1111100001101010")); +MQQ19:GET_ADDRESS_PT(19) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("0111110010011010")); +MQQ20:GET_ADDRESS_PT(20) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("0111111000010100")); +MQQ21:GET_ADDRESS_PT(21) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(25) & + FISS_UC_IS2_INSTR_L2(26) & FISS_UC_IS2_INSTR_L2(27) & + FISS_UC_IS2_INSTR_L2(28) & FISS_UC_IS2_INSTR_L2(29) & + FISS_UC_IS2_INSTR_L2(30) & FISS_UC_IS2_2UCODE_L2 + ) , STD_ULOGIC_VECTOR'("0111110101101111")); +MQQ22:GET_ADDRESS_PT(22) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) & + FISS_UC_IS2_2UCODE_L2 ) , STD_ULOGIC_VECTOR'("01111100001101111")); +MQQ23:GET_ADDRESS_PT(23) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) & + FISS_UC_IS2_2UCODE_L2 ) , STD_ULOGIC_VECTOR'("01111100001101110")); +MQQ24:GET_ADDRESS_PT(24) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(25) & + FISS_UC_IS2_INSTR_L2(26) & FISS_UC_IS2_INSTR_L2(27) & + FISS_UC_IS2_INSTR_L2(28) & FISS_UC_IS2_INSTR_L2(29) & + FISS_UC_IS2_INSTR_L2(30) & FISS_UC_IS2_2UCODE_L2 + ) , STD_ULOGIC_VECTOR'("0111110101101110")); +MQQ25:GET_ADDRESS_PT(25) <= + Eq(( FISS_UC_IS2_INSTR_L2(1) & FISS_UC_IS2_INSTR_L2(2) & + FISS_UC_IS2_INSTR_L2(3) & FISS_UC_IS2_INSTR_L2(4) & + FISS_UC_IS2_INSTR_L2(5) & FISS_UC_IS2_INSTR_L2(21) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("11111001111010")); +MQQ26:GET_ADDRESS_PT(26) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(26) & FISS_UC_IS2_INSTR_L2(27) & + FISS_UC_IS2_INSTR_L2(28) & FISS_UC_IS2_INSTR_L2(29) & + FISS_UC_IS2_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("011111000011010")); +MQQ27:GET_ADDRESS_PT(27) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("0111110010111010")); +MQQ28:GET_ADDRESS_PT(28) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(24) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("01111110110111")); +MQQ29:GET_ADDRESS_PT(29) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("01111110110111")); +MQQ30:GET_ADDRESS_PT(30) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("0111111010010110")); +MQQ31:GET_ADDRESS_PT(31) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("0111110011111100")); +MQQ32:GET_ADDRESS_PT(32) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("0111111000010110")); +MQQ33:GET_ADDRESS_PT(33) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(24) & FISS_UC_IS2_INSTR_L2(25) & + FISS_UC_IS2_INSTR_L2(26) & FISS_UC_IS2_INSTR_L2(27) & + FISS_UC_IS2_INSTR_L2(28) & FISS_UC_IS2_INSTR_L2(29) & + FISS_UC_IS2_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("011111110010110")); +MQQ34:GET_ADDRESS_PT(34) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(28) & FISS_UC_IS2_INSTR_L2(29) & + FISS_UC_IS2_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("011111011001111")); +MQQ35:GET_ADDRESS_PT(35) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("0111111010010100")); +MQQ36:GET_ADDRESS_PT(36) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(25) & + FISS_UC_IS2_INSTR_L2(26) & FISS_UC_IS2_INSTR_L2(27) & + FISS_UC_IS2_INSTR_L2(28) & FISS_UC_IS2_INSTR_L2(29) & + FISS_UC_IS2_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("011111010010111")); +MQQ37:GET_ADDRESS_PT(37) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("1111110010000000")); +MQQ38:GET_ADDRESS_PT(38) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("0111111011010101")); +MQQ39:GET_ADDRESS_PT(39) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("0111110001110111")); +MQQ40:GET_ADDRESS_PT(40) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(28) & FISS_UC_IS2_INSTR_L2(29) & + FISS_UC_IS2_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("011111000001101")); +MQQ41:GET_ADDRESS_PT(41) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("0111110010110111")); +MQQ42:GET_ADDRESS_PT(42) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("0111111010010101")); +MQQ43:GET_ADDRESS_PT(43) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("1111111011000111")); +MQQ44:GET_ADDRESS_PT(44) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("0111110010110101")); +MQQ45:GET_ADDRESS_PT(45) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(28) & FISS_UC_IS2_INSTR_L2(29) & + FISS_UC_IS2_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("011111001001111")); +MQQ46:GET_ADDRESS_PT(46) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(24) & FISS_UC_IS2_INSTR_L2(25) & + FISS_UC_IS2_INSTR_L2(26) & FISS_UC_IS2_INSTR_L2(27) & + FISS_UC_IS2_INSTR_L2(28) & FISS_UC_IS2_INSTR_L2(29) & + FISS_UC_IS2_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("111111000100000")); +MQQ47:GET_ADDRESS_PT(47) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(28) & FISS_UC_IS2_INSTR_L2(29) & + FISS_UC_IS2_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("011111000001111")); +MQQ48:GET_ADDRESS_PT(48) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(24) & FISS_UC_IS2_INSTR_L2(25) & + FISS_UC_IS2_INSTR_L2(26) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("01111101001111")); +MQQ49:GET_ADDRESS_PT(49) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(28) & FISS_UC_IS2_INSTR_L2(29) & + FISS_UC_IS2_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("011111101101111")); +MQQ50:GET_ADDRESS_PT(50) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("0111111101010111")); +MQQ51:GET_ADDRESS_PT(51) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_2UCODE_L2 ) , STD_ULOGIC_VECTOR'("1000010")); +MQQ52:GET_ADDRESS_PT(52) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(26) & FISS_UC_IS2_INSTR_L2(27) & + FISS_UC_IS2_INSTR_L2(28) & FISS_UC_IS2_INSTR_L2(29) & + FISS_UC_IS2_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("111111000000000")); +MQQ53:GET_ADDRESS_PT(53) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(28) & FISS_UC_IS2_INSTR_L2(29) & + FISS_UC_IS2_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("011111100101111")); +MQQ54:GET_ADDRESS_PT(54) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(28) & FISS_UC_IS2_INSTR_L2(29) & + FISS_UC_IS2_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("011111001001101")); +MQQ55:GET_ADDRESS_PT(55) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("0111111111010111")); +MQQ56:GET_ADDRESS_PT(56) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("0111111101110111")); +MQQ57:GET_ADDRESS_PT(57) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("01111110110111")); +MQQ58:GET_ADDRESS_PT(58) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("01111110010111")); +MQQ59:GET_ADDRESS_PT(59) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("0111110110110111")); +MQQ60:GET_ADDRESS_PT(60) <= + Eq(( FISS_UC_IS2_INSTR_L2(1) & FISS_UC_IS2_INSTR_L2(2) & + FISS_UC_IS2_INSTR_L2(3) & FISS_UC_IS2_INSTR_L2(4) & + FISS_UC_IS2_INSTR_L2(5) & FISS_UC_IS2_INSTR_L2(21) & + FISS_UC_IS2_INSTR_L2(22) & FISS_UC_IS2_INSTR_L2(23) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("11111100010101")); +MQQ61:GET_ADDRESS_PT(61) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_2UCODE_L2 + ) , STD_ULOGIC_VECTOR'("100001")); +MQQ62:GET_ADDRESS_PT(62) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(3) & FISS_UC_IS2_INSTR_L2(4) & + FISS_UC_IS2_INSTR_L2(5) & FISS_UC_IS2_INSTR_L2(30) & + FISS_UC_IS2_INSTR_L2(31) & FISS_UC_IS2_2UCODE_L2 + ) , STD_ULOGIC_VECTOR'("11010010")); +MQQ63:GET_ADDRESS_PT(63) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(3) & FISS_UC_IS2_INSTR_L2(4) & + FISS_UC_IS2_INSTR_L2(5) & FISS_UC_IS2_2UCODE_L2 + ) , STD_ULOGIC_VECTOR'("100010")); +MQQ64:GET_ADDRESS_PT(64) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(4) & + FISS_UC_IS2_INSTR_L2(5) & FISS_UC_IS2_INSTR_L2(21) & + FISS_UC_IS2_INSTR_L2(22) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(27) & + FISS_UC_IS2_INSTR_L2(28) & FISS_UC_IS2_INSTR_L2(29) & + FISS_UC_IS2_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("1111111101110")); +MQQ65:GET_ADDRESS_PT(65) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(3) & FISS_UC_IS2_INSTR_L2(4) & + FISS_UC_IS2_INSTR_L2(5) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("11011110")); +MQQ66:GET_ADDRESS_PT(66) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) + ) , STD_ULOGIC_VECTOR'("100000")); +MQQ67:GET_ADDRESS_PT(67) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(4) & + FISS_UC_IS2_INSTR_L2(5) & FISS_UC_IS2_INSTR_L2(30) & + FISS_UC_IS2_INSTR_L2(31) ) , STD_ULOGIC_VECTOR'("1111001")); +MQQ68:GET_ADDRESS_PT(68) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_2UCODE_L2 ) , STD_ULOGIC_VECTOR'("1010110")); +MQQ69:GET_ADDRESS_PT(69) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(30) & FISS_UC_IS2_INSTR_L2(31) + ) , STD_ULOGIC_VECTOR'("11101010")); +MQQ70:GET_ADDRESS_PT(70) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_2UCODE_L2 + ) , STD_ULOGIC_VECTOR'("101011")); +MQQ71:GET_ADDRESS_PT(71) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(30) & FISS_UC_IS2_INSTR_L2(31) + ) , STD_ULOGIC_VECTOR'("11101000")); +MQQ72:GET_ADDRESS_PT(72) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(4) & + FISS_UC_IS2_INSTR_L2(5) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(28) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("00000001")); +MQQ73:GET_ADDRESS_PT(73) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) + ) , STD_ULOGIC_VECTOR'("101010")); +MQQ74:GET_ADDRESS_PT(74) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(30) & FISS_UC_IS2_2UCODE_L2 + ) , STD_ULOGIC_VECTOR'("11101001")); +MQQ75:GET_ADDRESS_PT(75) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(4) & + FISS_UC_IS2_INSTR_L2(5) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(28) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("11111110")); +MQQ76:GET_ADDRESS_PT(76) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(4) & + FISS_UC_IS2_INSTR_L2(5) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("00000110")); +MQQ77:GET_ADDRESS_PT(77) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(4) & + FISS_UC_IS2_INSTR_L2(5) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) + ) , STD_ULOGIC_VECTOR'("00000111")); +MQQ78:GET_ADDRESS_PT(78) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(4) & + FISS_UC_IS2_INSTR_L2(5) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(28) & FISS_UC_IS2_INSTR_L2(29) + ) , STD_ULOGIC_VECTOR'("00000110")); +MQQ79:GET_ADDRESS_PT(79) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) ) , STD_ULOGIC_VECTOR'("10010")); +MQQ80:GET_ADDRESS_PT(80) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) ) , STD_ULOGIC_VECTOR'("11001")); +MQQ81:GET_ADDRESS_PT(81) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("1111100")); +MQQ82:GET_ADDRESS_PT(82) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(5) + ) , STD_ULOGIC_VECTOR'("1101")); +MQQ83:GET_ADDRESS_PT(83) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(5) + ) , STD_ULOGIC_VECTOR'("1011")); +MQQ84:GET_ADDRESS_PT(84) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(2) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) + ) , STD_ULOGIC_VECTOR'("1001")); +MQQ85:GET_ADDRESS_PT(85) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) ) , STD_ULOGIC_VECTOR'("10110")); +MQQ86:GET_ADDRESS_PT(86) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) + ) , STD_ULOGIC_VECTOR'("101110")); +MQQ87:GET_ADDRESS_PT(87) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) + ) , STD_ULOGIC_VECTOR'("101111")); +MQQ88:GET_ADDRESS_PT(88) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(4) & + FISS_UC_IS2_INSTR_L2(5) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(29) & + FISS_UC_IS2_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("111111010")); +MQQ89:GET_ADDRESS_PT(89) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) ) , STD_ULOGIC_VECTOR'("11011")); +MQQ90:GET_ADDRESS_PT(90) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(2) & + FISS_UC_IS2_INSTR_L2(3) & FISS_UC_IS2_INSTR_L2(4) & + FISS_UC_IS2_INSTR_L2(5) ) , STD_ULOGIC_VECTOR'("10011")); +MQQ91:GET_ADDRESS_PT(91) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) + ) , STD_ULOGIC_VECTOR'("1100")); +MQQ92:GET_ADDRESS_PT(92) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) ) , STD_ULOGIC_VECTOR'("101")); +MQQ93:GET_ADDRESS_PT(93) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) + ) , STD_ULOGIC_VECTOR'("1101")); +MQQ94:GET_ADDRESS_PT(94) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(4) & + FISS_UC_IS2_INSTR_L2(5) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("11111110")); +MQQ95:GET_ADDRESS_PT(95) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(4) & + FISS_UC_IS2_INSTR_L2(5) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) + ) , STD_ULOGIC_VECTOR'("11111111")); +MQQ96:GET_ADDRESS_PT(96) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(4) & + FISS_UC_IS2_INSTR_L2(5) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(28) & FISS_UC_IS2_INSTR_L2(29) + ) , STD_ULOGIC_VECTOR'("11111110")); +MQQ97:START_ADDR(0) <= + (GET_ADDRESS_PT(7) OR GET_ADDRESS_PT(17) + OR GET_ADDRESS_PT(18) OR GET_ADDRESS_PT(23) + OR GET_ADDRESS_PT(24) OR GET_ADDRESS_PT(37) + OR GET_ADDRESS_PT(38) OR GET_ADDRESS_PT(39) + OR GET_ADDRESS_PT(42) OR GET_ADDRESS_PT(43) + OR GET_ADDRESS_PT(46) OR GET_ADDRESS_PT(49) + OR GET_ADDRESS_PT(50) OR GET_ADDRESS_PT(52) + OR GET_ADDRESS_PT(53) OR GET_ADDRESS_PT(55) + OR GET_ADDRESS_PT(56) OR GET_ADDRESS_PT(57) + OR GET_ADDRESS_PT(58) OR GET_ADDRESS_PT(60) + OR GET_ADDRESS_PT(62) OR GET_ADDRESS_PT(63) + OR GET_ADDRESS_PT(64) OR GET_ADDRESS_PT(68) + OR GET_ADDRESS_PT(72) OR GET_ADDRESS_PT(76) + OR GET_ADDRESS_PT(77) OR GET_ADDRESS_PT(78) + OR GET_ADDRESS_PT(86) OR GET_ADDRESS_PT(87) + OR GET_ADDRESS_PT(88) OR GET_ADDRESS_PT(90) + OR GET_ADDRESS_PT(91) OR GET_ADDRESS_PT(93) + OR GET_ADDRESS_PT(94) OR GET_ADDRESS_PT(95) + OR GET_ADDRESS_PT(96)); +MQQ98:START_ADDR(1) <= + (GET_ADDRESS_PT(6) OR GET_ADDRESS_PT(7) + OR GET_ADDRESS_PT(10) OR GET_ADDRESS_PT(19) + OR GET_ADDRESS_PT(25) OR GET_ADDRESS_PT(27) + OR GET_ADDRESS_PT(31) OR GET_ADDRESS_PT(37) + OR GET_ADDRESS_PT(43) OR GET_ADDRESS_PT(46) + OR GET_ADDRESS_PT(49) OR GET_ADDRESS_PT(52) + OR GET_ADDRESS_PT(53) OR GET_ADDRESS_PT(55) + OR GET_ADDRESS_PT(57) OR GET_ADDRESS_PT(58) + OR GET_ADDRESS_PT(64) OR GET_ADDRESS_PT(72) + OR GET_ADDRESS_PT(76) OR GET_ADDRESS_PT(77) + OR GET_ADDRESS_PT(78) OR GET_ADDRESS_PT(88) + OR GET_ADDRESS_PT(91) OR GET_ADDRESS_PT(93) + OR GET_ADDRESS_PT(94) OR GET_ADDRESS_PT(95) + OR GET_ADDRESS_PT(96)); +MQQ99:START_ADDR(2) <= + (GET_ADDRESS_PT(6) OR GET_ADDRESS_PT(7) + OR GET_ADDRESS_PT(26) OR GET_ADDRESS_PT(30) + OR GET_ADDRESS_PT(35) OR GET_ADDRESS_PT(37) + OR GET_ADDRESS_PT(41) OR GET_ADDRESS_PT(43) + OR GET_ADDRESS_PT(44) OR GET_ADDRESS_PT(45) + OR GET_ADDRESS_PT(46) OR GET_ADDRESS_PT(50) + OR GET_ADDRESS_PT(52) OR GET_ADDRESS_PT(54) + OR GET_ADDRESS_PT(56) OR GET_ADDRESS_PT(64) + OR GET_ADDRESS_PT(72) OR GET_ADDRESS_PT(76) + OR GET_ADDRESS_PT(77) OR GET_ADDRESS_PT(78) + OR GET_ADDRESS_PT(79) OR GET_ADDRESS_PT(81) + OR GET_ADDRESS_PT(88) OR GET_ADDRESS_PT(94) + OR GET_ADDRESS_PT(95) OR GET_ADDRESS_PT(96) + ); +MQQ100:START_ADDR(3) <= + (GET_ADDRESS_PT(4) OR GET_ADDRESS_PT(8) + OR GET_ADDRESS_PT(9) OR GET_ADDRESS_PT(16) + OR GET_ADDRESS_PT(19) OR GET_ADDRESS_PT(20) + OR GET_ADDRESS_PT(26) OR GET_ADDRESS_PT(27) + OR GET_ADDRESS_PT(31) OR GET_ADDRESS_PT(34) + OR GET_ADDRESS_PT(38) OR GET_ADDRESS_PT(40) + OR GET_ADDRESS_PT(42) OR GET_ADDRESS_PT(49) + OR GET_ADDRESS_PT(50) OR GET_ADDRESS_PT(56) + OR GET_ADDRESS_PT(57) OR GET_ADDRESS_PT(59) + OR GET_ADDRESS_PT(69) OR GET_ADDRESS_PT(71) + OR GET_ADDRESS_PT(74) OR GET_ADDRESS_PT(85) + OR GET_ADDRESS_PT(87) OR GET_ADDRESS_PT(88) + OR GET_ADDRESS_PT(93)); +MQQ101:START_ADDR(4) <= + (GET_ADDRESS_PT(6) OR GET_ADDRESS_PT(7) + OR GET_ADDRESS_PT(8) OR GET_ADDRESS_PT(9) + OR GET_ADDRESS_PT(10) OR GET_ADDRESS_PT(18) + OR GET_ADDRESS_PT(19) OR GET_ADDRESS_PT(20) + OR GET_ADDRESS_PT(22) OR GET_ADDRESS_PT(28) + OR GET_ADDRESS_PT(31) OR GET_ADDRESS_PT(32) + OR GET_ADDRESS_PT(34) OR GET_ADDRESS_PT(35) + OR GET_ADDRESS_PT(37) OR GET_ADDRESS_PT(40) + OR GET_ADDRESS_PT(42) OR GET_ADDRESS_PT(43) + OR GET_ADDRESS_PT(44) OR GET_ADDRESS_PT(46) + OR GET_ADDRESS_PT(47) OR GET_ADDRESS_PT(49) + OR GET_ADDRESS_PT(50) OR GET_ADDRESS_PT(52) + OR GET_ADDRESS_PT(53) OR GET_ADDRESS_PT(54) + OR GET_ADDRESS_PT(55) OR GET_ADDRESS_PT(56) + OR GET_ADDRESS_PT(59) OR GET_ADDRESS_PT(60) + OR GET_ADDRESS_PT(61) OR GET_ADDRESS_PT(64) + OR GET_ADDRESS_PT(66) OR GET_ADDRESS_PT(72) + OR GET_ADDRESS_PT(75) OR GET_ADDRESS_PT(76) + OR GET_ADDRESS_PT(77) OR GET_ADDRESS_PT(78) + OR GET_ADDRESS_PT(81) OR GET_ADDRESS_PT(85) + OR GET_ADDRESS_PT(86) OR GET_ADDRESS_PT(94) + OR GET_ADDRESS_PT(95) OR GET_ADDRESS_PT(96) + ); +MQQ102:START_ADDR(5) <= + (GET_ADDRESS_PT(2) OR GET_ADDRESS_PT(3) + OR GET_ADDRESS_PT(5) OR GET_ADDRESS_PT(7) + OR GET_ADDRESS_PT(9) OR GET_ADDRESS_PT(14) + OR GET_ADDRESS_PT(17) OR GET_ADDRESS_PT(22) + OR GET_ADDRESS_PT(23) OR GET_ADDRESS_PT(24) + OR GET_ADDRESS_PT(27) OR GET_ADDRESS_PT(30) + OR GET_ADDRESS_PT(32) OR GET_ADDRESS_PT(34) + OR GET_ADDRESS_PT(37) OR GET_ADDRESS_PT(38) + OR GET_ADDRESS_PT(41) OR GET_ADDRESS_PT(43) + OR GET_ADDRESS_PT(45) OR GET_ADDRESS_PT(46) + OR GET_ADDRESS_PT(47) OR GET_ADDRESS_PT(52) + OR GET_ADDRESS_PT(55) OR GET_ADDRESS_PT(56) + OR GET_ADDRESS_PT(59) OR GET_ADDRESS_PT(64) + OR GET_ADDRESS_PT(65) OR GET_ADDRESS_PT(70) + OR GET_ADDRESS_PT(71) OR GET_ADDRESS_PT(72) + OR GET_ADDRESS_PT(73) OR GET_ADDRESS_PT(74) + OR GET_ADDRESS_PT(76) OR GET_ADDRESS_PT(77) + OR GET_ADDRESS_PT(78) OR GET_ADDRESS_PT(80) + OR GET_ADDRESS_PT(85) OR GET_ADDRESS_PT(87) + OR GET_ADDRESS_PT(89) OR GET_ADDRESS_PT(94) + OR GET_ADDRESS_PT(95) OR GET_ADDRESS_PT(96) + ); +MQQ103:START_ADDR(6) <= + (GET_ADDRESS_PT(2) OR GET_ADDRESS_PT(4) + OR GET_ADDRESS_PT(5) OR GET_ADDRESS_PT(7) + OR GET_ADDRESS_PT(12) OR GET_ADDRESS_PT(16) + OR GET_ADDRESS_PT(17) OR GET_ADDRESS_PT(21) + OR GET_ADDRESS_PT(23) OR GET_ADDRESS_PT(27) + OR GET_ADDRESS_PT(31) OR GET_ADDRESS_PT(33) + OR GET_ADDRESS_PT(35) OR GET_ADDRESS_PT(36) + OR GET_ADDRESS_PT(39) OR GET_ADDRESS_PT(43) + OR GET_ADDRESS_PT(44) OR GET_ADDRESS_PT(46) + OR GET_ADDRESS_PT(48) OR GET_ADDRESS_PT(50) + OR GET_ADDRESS_PT(52) OR GET_ADDRESS_PT(53) + OR GET_ADDRESS_PT(54) OR GET_ADDRESS_PT(58) + OR GET_ADDRESS_PT(59) OR GET_ADDRESS_PT(60) + OR GET_ADDRESS_PT(61) OR GET_ADDRESS_PT(62) + OR GET_ADDRESS_PT(64) OR GET_ADDRESS_PT(66) + OR GET_ADDRESS_PT(71) OR GET_ADDRESS_PT(72) + OR GET_ADDRESS_PT(74) OR GET_ADDRESS_PT(76) + OR GET_ADDRESS_PT(77) OR GET_ADDRESS_PT(78) + OR GET_ADDRESS_PT(79) OR GET_ADDRESS_PT(80) + OR GET_ADDRESS_PT(94) OR GET_ADDRESS_PT(95) + OR GET_ADDRESS_PT(96)); +MQQ104:START_ADDR(7) <= + (GET_ADDRESS_PT(2) OR GET_ADDRESS_PT(4) + OR GET_ADDRESS_PT(7) OR GET_ADDRESS_PT(8) + OR GET_ADDRESS_PT(9) OR GET_ADDRESS_PT(14) + OR GET_ADDRESS_PT(15) OR GET_ADDRESS_PT(16) + OR GET_ADDRESS_PT(17) OR GET_ADDRESS_PT(20) + OR GET_ADDRESS_PT(22) OR GET_ADDRESS_PT(30) + OR GET_ADDRESS_PT(32) OR GET_ADDRESS_PT(34) + OR GET_ADDRESS_PT(35) OR GET_ADDRESS_PT(37) + OR GET_ADDRESS_PT(38) OR GET_ADDRESS_PT(39) + OR GET_ADDRESS_PT(40) OR GET_ADDRESS_PT(41) + OR GET_ADDRESS_PT(42) OR GET_ADDRESS_PT(44) + OR GET_ADDRESS_PT(45) OR GET_ADDRESS_PT(47) + OR GET_ADDRESS_PT(51) OR GET_ADDRESS_PT(54) + OR GET_ADDRESS_PT(55) OR GET_ADDRESS_PT(59) + OR GET_ADDRESS_PT(68) OR GET_ADDRESS_PT(70) + OR GET_ADDRESS_PT(73) OR GET_ADDRESS_PT(85) + OR GET_ADDRESS_PT(86) OR GET_ADDRESS_PT(89) + ); +MQQ105:START_ADDR(8) <= + (GET_ADDRESS_PT(3) OR GET_ADDRESS_PT(15) + OR GET_ADDRESS_PT(21) OR GET_ADDRESS_PT(30) + OR GET_ADDRESS_PT(33) OR GET_ADDRESS_PT(36) + OR GET_ADDRESS_PT(41) OR GET_ADDRESS_PT(45) + OR GET_ADDRESS_PT(48) OR GET_ADDRESS_PT(49) + OR GET_ADDRESS_PT(55) OR GET_ADDRESS_PT(56) + OR GET_ADDRESS_PT(57) OR GET_ADDRESS_PT(59) + OR GET_ADDRESS_PT(63) OR GET_ADDRESS_PT(79) + OR GET_ADDRESS_PT(89) OR GET_ADDRESS_PT(91) + ); +MQQ106:START_ADDR(9) <= + (GET_ADDRESS_PT(3) OR GET_ADDRESS_PT(12) + OR GET_ADDRESS_PT(21) OR GET_ADDRESS_PT(33) + OR GET_ADDRESS_PT(35) OR GET_ADDRESS_PT(36) + OR GET_ADDRESS_PT(37) OR GET_ADDRESS_PT(44) + OR GET_ADDRESS_PT(48) OR GET_ADDRESS_PT(54) + OR GET_ADDRESS_PT(56) OR GET_ADDRESS_PT(59) + OR GET_ADDRESS_PT(80) OR GET_ADDRESS_PT(81) + ); +MQQ107:XER_TYPE <= + (GET_ADDRESS_PT(3) OR GET_ADDRESS_PT(42) + ); +MQQ108:LATE_END <= + (GET_ADDRESS_PT(4) OR GET_ADDRESS_PT(6) + OR GET_ADDRESS_PT(7) OR GET_ADDRESS_PT(8) + OR GET_ADDRESS_PT(10) OR GET_ADDRESS_PT(17) + OR GET_ADDRESS_PT(18) OR GET_ADDRESS_PT(19) + OR GET_ADDRESS_PT(21) OR GET_ADDRESS_PT(22) + OR GET_ADDRESS_PT(23) OR GET_ADDRESS_PT(24) + OR GET_ADDRESS_PT(25) OR GET_ADDRESS_PT(26) + OR GET_ADDRESS_PT(27) OR GET_ADDRESS_PT(29) + OR GET_ADDRESS_PT(31) OR GET_ADDRESS_PT(37) + OR GET_ADDRESS_PT(38) OR GET_ADDRESS_PT(39) + OR GET_ADDRESS_PT(41) OR GET_ADDRESS_PT(42) + OR GET_ADDRESS_PT(43) OR GET_ADDRESS_PT(44) + OR GET_ADDRESS_PT(46) OR GET_ADDRESS_PT(50) + OR GET_ADDRESS_PT(52) OR GET_ADDRESS_PT(55) + OR GET_ADDRESS_PT(56) OR GET_ADDRESS_PT(59) + OR GET_ADDRESS_PT(60) OR GET_ADDRESS_PT(64) + OR GET_ADDRESS_PT(67) OR GET_ADDRESS_PT(69) + OR GET_ADDRESS_PT(72) OR GET_ADDRESS_PT(76) + OR GET_ADDRESS_PT(77) OR GET_ADDRESS_PT(78) + OR GET_ADDRESS_PT(82) OR GET_ADDRESS_PT(83) + OR GET_ADDRESS_PT(84) OR GET_ADDRESS_PT(86) + OR GET_ADDRESS_PT(88) OR GET_ADDRESS_PT(90) + OR GET_ADDRESS_PT(94) OR GET_ADDRESS_PT(95) + OR GET_ADDRESS_PT(96)); +MQQ109:FORCE_EP <= + (GET_ADDRESS_PT(1) OR GET_ADDRESS_PT(11) + OR GET_ADDRESS_PT(13)); +MQQ110:UC_LEGAL <= + (GET_ADDRESS_PT(4) OR GET_ADDRESS_PT(6) + OR GET_ADDRESS_PT(7) OR GET_ADDRESS_PT(8) + OR GET_ADDRESS_PT(10) OR GET_ADDRESS_PT(16) + OR GET_ADDRESS_PT(17) OR GET_ADDRESS_PT(18) + OR GET_ADDRESS_PT(19) OR GET_ADDRESS_PT(20) + OR GET_ADDRESS_PT(21) OR GET_ADDRESS_PT(22) + OR GET_ADDRESS_PT(23) OR GET_ADDRESS_PT(24) + OR GET_ADDRESS_PT(25) OR GET_ADDRESS_PT(26) + OR GET_ADDRESS_PT(27) OR GET_ADDRESS_PT(30) + OR GET_ADDRESS_PT(31) OR GET_ADDRESS_PT(32) + OR GET_ADDRESS_PT(33) OR GET_ADDRESS_PT(35) + OR GET_ADDRESS_PT(36) OR GET_ADDRESS_PT(37) + OR GET_ADDRESS_PT(38) OR GET_ADDRESS_PT(39) + OR GET_ADDRESS_PT(40) OR GET_ADDRESS_PT(41) + OR GET_ADDRESS_PT(42) OR GET_ADDRESS_PT(43) + OR GET_ADDRESS_PT(44) OR GET_ADDRESS_PT(45) + OR GET_ADDRESS_PT(46) OR GET_ADDRESS_PT(47) + OR GET_ADDRESS_PT(48) OR GET_ADDRESS_PT(49) + OR GET_ADDRESS_PT(50) OR GET_ADDRESS_PT(52) + OR GET_ADDRESS_PT(53) OR GET_ADDRESS_PT(54) + OR GET_ADDRESS_PT(55) OR GET_ADDRESS_PT(56) + OR GET_ADDRESS_PT(57) OR GET_ADDRESS_PT(58) + OR GET_ADDRESS_PT(59) OR GET_ADDRESS_PT(60) + OR GET_ADDRESS_PT(62) OR GET_ADDRESS_PT(64) + OR GET_ADDRESS_PT(66) OR GET_ADDRESS_PT(69) + OR GET_ADDRESS_PT(71) OR GET_ADDRESS_PT(72) + OR GET_ADDRESS_PT(74) OR GET_ADDRESS_PT(76) + OR GET_ADDRESS_PT(77) OR GET_ADDRESS_PT(78) + OR GET_ADDRESS_PT(79) OR GET_ADDRESS_PT(81) + OR GET_ADDRESS_PT(84) OR GET_ADDRESS_PT(88) + OR GET_ADDRESS_PT(90) OR GET_ADDRESS_PT(91) + OR GET_ADDRESS_PT(92) OR GET_ADDRESS_PT(93) + OR GET_ADDRESS_PT(94) OR GET_ADDRESS_PT(95) + OR GET_ADDRESS_PT(96)); + +iu_pc_err_ucode_illegal_d <= gate_and(fiss_uc_is2_ucode_vld_l2 and not uc_legal, fiss_uc_is2_tid_l2); +err_ucode_illegal: tri_direct_err_rpt + generic map (width => 4, expand_type => expand_type) + port map ( + vd => vdd, + gd => gnd, + err_in => iu_pc_err_ucode_illegal_L2, + err_out => iu_pc_err_ucode_illegal); +xu_iu_flush_d <= xu_iu_flush; +xu_iu_ucode_restart_d <= xu_iu_ucode_restart; +xu_iu_uc_flush_ifar0_d <= xu_iu_uc_flush_ifar0; +xu_iu_uc_flush_ifar1_d <= xu_iu_uc_flush_ifar1; +xu_iu_uc_flush_ifar2_d <= xu_iu_uc_flush_ifar2; +xu_iu_uc_flush_ifar3_d <= xu_iu_uc_flush_ifar3; +uc_control0 : entity work.iuq_uc_control + generic map( ucode_width => ucode_width, + expand_type => expand_type) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_iu_func_sl_thold_0_b => pc_iu_func_sl_thold_0_b, + pc_iu_sg_0 => pc_iu_sg_0, + forcee => forcee, + d_mode => d_mode, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + scan_in => siv(scan_right + 1), + scan_out => sov(scan_right + 1), + spr_ic_clockgate_dis => spr_ic_clockgate_dis, + xu_iu_spr_xer => xu_iu_spr_xer0, + flush => xu_iu_flush_l2(0), + restart => xu_iu_ucode_restart_l2(0), + flush_ifar => xu_iu_uc_flush_ifar0_l2, + ib_flush => ib_flush(0), + ib_flush_ifar => iu5_ifar_l2, + buff_avail => ib_uc_buff0_avail, + load_command => load_command(0), + new_instr => fiss_uc_is2_instr_l2, + start_addr => start_addr, + xer_type => xer_type, + early_end => early_end, + force_ep => force_ep, + new_cond => new_cond, + uc_act_thread => uc_act(0), + vld_fast => vld_fast(0), + ra_valid => vld_mask(0), + rom_ra => rom_ra0, + data_valid => data_valid(0), + rom_data => rom_data(32 to ucode_width-1), + rom_data_late => rom_data_late_l2(0 to 31), + ucode_valid => ucode_valid(0), + ucode_ifar => ucode_ifar0, + ucode_instruction => ucode_instr0, + is_ucode => ucode_is_ucode0, + extRT => ucode_ext0(0), + extS1 => ucode_ext0(1), + extS2 => ucode_ext0(2), + extS3 => ucode_ext0(3), + hold_thread => uc_ic_hold_thread(0), + uc_control_dbg_data => uc_control_dbg_data0 +); +uc_control1 : entity work.iuq_uc_control + generic map( ucode_width => ucode_width, + expand_type => expand_type) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_iu_func_sl_thold_0_b => pc_iu_func_sl_thold_0_b, + pc_iu_sg_0 => pc_iu_sg_0, + forcee => forcee, + d_mode => d_mode, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + scan_in => siv(scan_right + 2), + scan_out => sov(scan_right + 2), + spr_ic_clockgate_dis => spr_ic_clockgate_dis, + xu_iu_spr_xer => xu_iu_spr_xer1, + flush => xu_iu_flush_l2(1), + restart => xu_iu_ucode_restart_l2(1), + flush_ifar => xu_iu_uc_flush_ifar1_l2, + ib_flush => ib_flush(1), + ib_flush_ifar => iu5_ifar_l2, + buff_avail => ib_uc_buff1_avail, + load_command => load_command(1), + new_instr => fiss_uc_is2_instr_l2, + start_addr => start_addr, + xer_type => xer_type, + early_end => early_end, + force_ep => force_ep, + new_cond => new_cond, + uc_act_thread => uc_act(1), + vld_fast => vld_fast(1), + ra_valid => vld_mask(1), + rom_ra => rom_ra1, + data_valid => data_valid(1), + rom_data => rom_data(32 to ucode_width-1), + rom_data_late => rom_data_late_l2(0 to 31), + ucode_valid => ucode_valid(1), + ucode_ifar => ucode_ifar1, + ucode_instruction => ucode_instr1, + is_ucode => ucode_is_ucode1, + extRT => ucode_ext1(0), + extS1 => ucode_ext1(1), + extS2 => ucode_ext1(2), + extS3 => ucode_ext1(3), + hold_thread => uc_ic_hold_thread(1), + uc_control_dbg_data => uc_control_dbg_data1 +); +uc_control2 : entity work.iuq_uc_control + generic map( ucode_width => ucode_width, + expand_type => expand_type) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_iu_func_sl_thold_0_b => pc_iu_func_sl_thold_0_b, + pc_iu_sg_0 => pc_iu_sg_0, + forcee => forcee, + d_mode => d_mode, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + scan_in => siv(scan_right + 3), + scan_out => sov(scan_right + 3), + spr_ic_clockgate_dis => spr_ic_clockgate_dis, + xu_iu_spr_xer => xu_iu_spr_xer2, + flush => xu_iu_flush_l2(2), + restart => xu_iu_ucode_restart_l2(2), + flush_ifar => xu_iu_uc_flush_ifar2_l2, + ib_flush => ib_flush(2), + ib_flush_ifar => iu5_ifar_l2, + buff_avail => ib_uc_buff2_avail, + load_command => load_command(2), + new_instr => fiss_uc_is2_instr_l2, + start_addr => start_addr, + xer_type => xer_type, + early_end => early_end, + force_ep => force_ep, + new_cond => new_cond, + uc_act_thread => uc_act(2), + vld_fast => vld_fast(2), + ra_valid => vld_mask(2), + rom_ra => rom_ra2, + data_valid => data_valid(2), + rom_data => rom_data(32 to ucode_width-1), + rom_data_late => rom_data_late_l2(0 to 31), + ucode_valid => ucode_valid(2), + ucode_ifar => ucode_ifar2, + ucode_instruction => ucode_instr2, + is_ucode => ucode_is_ucode2, + extRT => ucode_ext2(0), + extS1 => ucode_ext2(1), + extS2 => ucode_ext2(2), + extS3 => ucode_ext2(3), + hold_thread => uc_ic_hold_thread(2), + uc_control_dbg_data => uc_control_dbg_data2 +); +uc_control3 : entity work.iuq_uc_control + generic map( ucode_width => ucode_width, + expand_type => expand_type) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_iu_func_sl_thold_0_b => pc_iu_func_sl_thold_0_b, + pc_iu_sg_0 => pc_iu_sg_0, + forcee => forcee, + d_mode => d_mode, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + scan_in => siv(scan_right + 4), + scan_out => sov(scan_right + 4), + spr_ic_clockgate_dis => spr_ic_clockgate_dis, + xu_iu_spr_xer => xu_iu_spr_xer3, + flush => xu_iu_flush_l2(3), + restart => xu_iu_ucode_restart_l2(3), + flush_ifar => xu_iu_uc_flush_ifar3_l2, + ib_flush => ib_flush(3), + ib_flush_ifar => iu5_ifar_l2, + buff_avail => ib_uc_buff3_avail, + load_command => load_command(3), + new_instr => fiss_uc_is2_instr_l2, + start_addr => start_addr, + xer_type => xer_type, + early_end => early_end, + force_ep => force_ep, + new_cond => new_cond, + uc_act_thread => uc_act(3), + vld_fast => vld_fast(3), + ra_valid => vld_mask(3), + rom_ra => rom_ra3, + data_valid => data_valid(3), + rom_data => rom_data(32 to ucode_width-1), + rom_data_late => rom_data_late_l2(0 to 31), + ucode_valid => ucode_valid(3), + ucode_ifar => ucode_ifar3, + ucode_instruction => ucode_instr3, + is_ucode => ucode_is_ucode3, + extRT => ucode_ext3(0), + extS1 => ucode_ext3(1), + extS2 => ucode_ext3(2), + extS3 => ucode_ext3(3), + hold_thread => uc_ic_hold_thread(3), + uc_control_dbg_data => uc_control_dbg_data3 +); +MQQ111:ROM_ISSUE_TABLE_PT(1) <= + Eq(( ROMTOKEN_L2(3) & VLD_FAST(0) & + VLD_FAST(1) ) , STD_ULOGIC_VECTOR'("101")); +MQQ112:ROM_ISSUE_TABLE_PT(2) <= + Eq(( ROMTOKEN_L2(2) & VLD_FAST(0) & + VLD_FAST(3) ) , STD_ULOGIC_VECTOR'("110")); +MQQ113:ROM_ISSUE_TABLE_PT(3) <= + Eq(( ROMTOKEN_L2(2) & ROMTOKEN_L2(3) & + VLD_FAST(1) & VLD_FAST(2) + ) , STD_ULOGIC_VECTOR'("0001")); +MQQ114:ROM_ISSUE_TABLE_PT(4) <= + Eq(( ROMTOKEN_L2(1) & VLD_FAST(0) & + VLD_FAST(2) & VLD_FAST(3) + ) , STD_ULOGIC_VECTOR'("1000")); +MQQ115:ROM_ISSUE_TABLE_PT(5) <= + Eq(( ROMTOKEN_L2(0) & VLD_FAST(1) & + VLD_FAST(2) & VLD_FAST(3) + ) , STD_ULOGIC_VECTOR'("1001")); +MQQ116:ROM_ISSUE_TABLE_PT(6) <= + Eq(( ROMTOKEN_L2(2) & VLD_FAST(0) & + VLD_FAST(1) & VLD_FAST(3) + ) , STD_ULOGIC_VECTOR'("1000")); +MQQ117:ROM_ISSUE_TABLE_PT(7) <= + Eq(( ROMTOKEN_L2(3) & VLD_FAST(0) & + VLD_FAST(1) & VLD_FAST(2) + ) , STD_ULOGIC_VECTOR'("1000")); +MQQ118:ROM_ISSUE_TABLE_PT(8) <= + Eq(( ROMTOKEN_L2(0) & VLD_FAST(1) & + VLD_FAST(2) & VLD_FAST(3) + ) , STD_ULOGIC_VECTOR'("1000")); +MQQ119:ROM_ISSUE_TABLE_PT(9) <= + Eq(( ROMTOKEN_L2(1) & VLD_FAST(2) & + VLD_FAST(3) ) , STD_ULOGIC_VECTOR'("101")); +MQQ120:ROM_ISSUE_TABLE_PT(10) <= + Eq(( ROMTOKEN_L2(0) & VLD_FAST(0) & + VLD_FAST(2) & VLD_FAST(3) + ) , STD_ULOGIC_VECTOR'("0100")); +MQQ121:ROM_ISSUE_TABLE_PT(11) <= + Eq(( ROMTOKEN_L2(1) & VLD_FAST(0) & + VLD_FAST(1) & VLD_FAST(3) + ) , STD_ULOGIC_VECTOR'("0010")); +MQQ122:ROM_ISSUE_TABLE_PT(12) <= + Eq(( ROMTOKEN_L2(2) & VLD_FAST(0) & + VLD_FAST(1) & VLD_FAST(2) + ) , STD_ULOGIC_VECTOR'("0001")); +MQQ123:ROM_ISSUE_TABLE_PT(13) <= + Eq(( ROMTOKEN_L2(1) & VLD_FAST(2) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ124:ROM_ISSUE_TABLE_PT(14) <= + Eq(( ROMTOKEN_L2(3) & VLD_FAST(0) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ125:ROM_ISSUE_TABLE_PT(15) <= + Eq(( ROMTOKEN_L2(0) & VLD_FAST(1) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ126:ROM_ISSUE_TABLE_PT(16) <= + Eq(( ROMTOKEN_L2(2) & VLD_FAST(3) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ127:ROMTOKEN_D(0) <= + (ROM_ISSUE_TABLE_PT(2) OR ROM_ISSUE_TABLE_PT(8) + OR ROM_ISSUE_TABLE_PT(10) OR ROM_ISSUE_TABLE_PT(14) + ); +MQQ128:ROMTOKEN_D(1) <= + (ROM_ISSUE_TABLE_PT(1) OR ROM_ISSUE_TABLE_PT(4) + OR ROM_ISSUE_TABLE_PT(11) OR ROM_ISSUE_TABLE_PT(15) + ); +MQQ129:ROMTOKEN_D(2) <= + (ROM_ISSUE_TABLE_PT(3) OR ROM_ISSUE_TABLE_PT(6) + OR ROM_ISSUE_TABLE_PT(12) OR ROM_ISSUE_TABLE_PT(13) + ); +MQQ130:ROMTOKEN_D(3) <= + (ROM_ISSUE_TABLE_PT(5) OR ROM_ISSUE_TABLE_PT(7) + OR ROM_ISSUE_TABLE_PT(9) OR ROM_ISSUE_TABLE_PT(16) + ); + +romvalid_d <= vld_mask; +rom_addr <= gate_and(romtoken_d(0), rom_ra0) or + gate_and(romtoken_d(1), rom_ra1) or + gate_and(romtoken_d(2), rom_ra2) or + gate_and(romtoken_d(3), rom_ra3) ; +uc_any_act <= or_reduce(uc_act); +rom_act <= uc_any_act; +rom_data_tid <= romtoken_L2; +data_valid <= romvalid_l2 and rom_data_tid; +uc_rom: entity work.iuq_uc_rom + generic map( ucode_width => ucode_width, + regmode => regmode, + expand_type => expand_type) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_iu_func_sl_thold_0_b => pc_iu_func_sl_thold_0_b, + pc_iu_sg_0 => pc_iu_sg_0, + forcee => forcee, + d_mode => d_mode, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + scan_in => siv(scan_right + 5), + scan_out => sov(scan_right + 5), + rom_act => rom_act, + rom_addr => rom_addr, + rom_data => rom_data +); +rom_data_late_d <= rom_data(0 to 31); +iu4_stage_act <= or_reduce(data_valid); +iu4_valid_tid_d <= ucode_valid and not xu_iu_flush_d; +iu4_is_ucode_d <= gate_and(rom_data_tid(0), ucode_is_ucode0) or + gate_and(rom_data_tid(1), ucode_is_ucode1) or + gate_and(rom_data_tid(2), ucode_is_ucode2) or + gate_and(rom_data_tid(3), ucode_is_ucode3) ; +iu4_ifar_d <= gate_and(rom_data_tid(0), ucode_ifar0) or + gate_and(rom_data_tid(1), ucode_ifar1) or + gate_and(rom_data_tid(2), ucode_ifar2) or + gate_and(rom_data_tid(3), ucode_ifar3) ; +iu4_ext_d <= gate_and(rom_data_tid(0), ucode_ext0) or + gate_and(rom_data_tid(1), ucode_ext1) or + gate_and(rom_data_tid(2), ucode_ext2) or + gate_and(rom_data_tid(3), ucode_ext3) ; +iu4_data_tid_d <= rom_data_tid; +iu4_instr_l2 <= gate_and(iu4_data_tid_l2(0), ucode_instr0) or + gate_and(iu4_data_tid_l2(1), ucode_instr1) or + gate_and(iu4_data_tid_l2(2), ucode_instr2) or + gate_and(iu4_data_tid_l2(3), ucode_instr3) ; +uc_ib_iu4_valid_tid <= iu4_valid_tid_l2; +uc_ib_iu4_ifar <= iu4_ifar_l2; +uc_ib_iu4_instr <= iu4_instr_l2; +uc_ib_iu4_is_ucode <= iu4_is_ucode_l2; +uc_ib_iu4_ext <= iu4_ext_l2; +ib_flush <= "0000"; +iu5_ifar_l2 <= (others => '0'); +sov(iu5_valid_tid_offset TO iu5_valid_tid_offset+4-1) <= + siv(iu5_valid_tid_offset to iu5_valid_tid_offset + 4 - 1); +sov(iu5_ifar_offset TO iu5_ifar_offset+iu5_ifar_l2'length-1) <= + siv(iu5_ifar_offset to iu5_ifar_offset + iu5_ifar_l2'length-1); +ib_uc_buff_avail_d <= ib_uc_buff0_avail & ib_uc_buff1_avail & ib_uc_buff2_avail & ib_uc_buff3_avail; +uc_dbg_data(0 TO 3) <= uc_control_dbg_data0; +uc_dbg_data(4 TO 7) <= uc_control_dbg_data1; +uc_dbg_data(8 TO 11) <= uc_control_dbg_data2; +uc_dbg_data(12 TO 15) <= uc_control_dbg_data3; +uc_dbg_data(16 TO 19) <= xu_iu_flush_l2; +uc_dbg_data(20 TO 23) <= ib_uc_buff_avail_l2; +uc_dbg_data(24) <= fiss_uc_is2_ucode_vld_l2; +uc_dbg_data(25) <= fiss_uc_is2_2ucode_l2; +uc_dbg_data(26) <= fiss_uc_is2_2ucode_type_l2; +uc_dbg_data(27 TO 43) <= fiss_uc_is2_instr_l2(0 to 5) & fiss_uc_is2_instr_l2(21 to 31); +uc_dbg_data_d(44 TO 59) <= iu4_instr_l2(0 to 15); +uc_dbg_data(44 TO 59) <= uc_dbg_data_l2(44 to 59); +uc_dbg_data(60 TO 63) <= iu4_ext_l2; +uc_dbg_data(64 TO 65) <= iu4_ifar_l2(41 to 42); +uc_dbg_data(66 TO 73) <= iu4_ifar_l2(54 to 61); +uc_dbg_data(74) <= iu4_ifar_l2(48); +uc_dbg_data(75 TO 79) <= iu4_ifar_l2(43 to 47); +uc_dbg_data(80 TO 83) <= iu4_valid_tid_l2; +uc_dbg_data(84 TO 87) <= romtoken_l2; +iu_pc_err_ucode_illegal_0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => uc_act(0), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu_pc_err_ucode_illegal_offset + 0), + scout => sov(iu_pc_err_ucode_illegal_offset + 0), + din => iu_pc_err_ucode_illegal_d(0), + dout => iu_pc_err_ucode_illegal_l2(0)); +iu_pc_err_ucode_illegal_1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => uc_act(1), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu_pc_err_ucode_illegal_offset + 1), + scout => sov(iu_pc_err_ucode_illegal_offset + 1), + din => iu_pc_err_ucode_illegal_d(1), + dout => iu_pc_err_ucode_illegal_l2(1)); +iu_pc_err_ucode_illegal_2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => uc_act(2), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu_pc_err_ucode_illegal_offset + 2), + scout => sov(iu_pc_err_ucode_illegal_offset + 2), + din => iu_pc_err_ucode_illegal_d(2), + dout => iu_pc_err_ucode_illegal_l2(2)); +iu_pc_err_ucode_illegal_3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => uc_act(3), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu_pc_err_ucode_illegal_offset + 3), + scout => sov(iu_pc_err_ucode_illegal_offset + 3), + din => iu_pc_err_ucode_illegal_d(3), + dout => iu_pc_err_ucode_illegal_l2(3)); +ib_uc_buff_avail_latch: tri_rlmreg_p + generic map (width => ib_uc_buff_avail_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => trace_bus_enable_q, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(ib_uc_buff_avail_offset to ib_uc_buff_avail_offset + ib_uc_buff_avail_l2'length-1), + scout => sov(ib_uc_buff_avail_offset to ib_uc_buff_avail_offset + ib_uc_buff_avail_l2'length-1), + din => ib_uc_buff_avail_d, + dout => ib_uc_buff_avail_l2); +xu_iu_flush_latch: tri_rlmreg_p + generic map (width => xu_iu_flush_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_iu_flush_offset to xu_iu_flush_offset + xu_iu_flush_l2'length-1), + scout => sov(xu_iu_flush_offset to xu_iu_flush_offset + xu_iu_flush_l2'length-1), + din => xu_iu_flush_d, + dout => xu_iu_flush_l2); +xu_iu_ucode_restart_latch: tri_rlmreg_p + generic map (width => xu_iu_ucode_restart_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_iu_ucode_restart_offset to xu_iu_ucode_restart_offset + xu_iu_ucode_restart_l2'length-1), + scout => sov(xu_iu_ucode_restart_offset to xu_iu_ucode_restart_offset + xu_iu_ucode_restart_l2'length-1), + din => xu_iu_ucode_restart_d, + dout => xu_iu_ucode_restart_l2); +xu_iu_uc_flush_ifar0_latch: tri_rlmreg_p + generic map (width => xu_iu_uc_flush_ifar0_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => uc_act(0), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_iu_uc_flush_ifar0_offset to xu_iu_uc_flush_ifar0_offset + xu_iu_uc_flush_ifar0_l2'length-1), + scout => sov(xu_iu_uc_flush_ifar0_offset to xu_iu_uc_flush_ifar0_offset + xu_iu_uc_flush_ifar0_l2'length-1), + din => xu_iu_uc_flush_ifar0_d, + dout => xu_iu_uc_flush_ifar0_l2); +xu_iu_uc_flush_ifar1_latch: tri_rlmreg_p + generic map (width => xu_iu_uc_flush_ifar1_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => uc_act(1), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_iu_uc_flush_ifar1_offset to xu_iu_uc_flush_ifar1_offset + xu_iu_uc_flush_ifar1_l2'length-1), + scout => sov(xu_iu_uc_flush_ifar1_offset to xu_iu_uc_flush_ifar1_offset + xu_iu_uc_flush_ifar1_l2'length-1), + din => xu_iu_uc_flush_ifar1_d, + dout => xu_iu_uc_flush_ifar1_l2); +xu_iu_uc_flush_ifar2_latch: tri_rlmreg_p + generic map (width => xu_iu_uc_flush_ifar2_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => uc_act(2), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_iu_uc_flush_ifar2_offset to xu_iu_uc_flush_ifar2_offset + xu_iu_uc_flush_ifar2_l2'length-1), + scout => sov(xu_iu_uc_flush_ifar2_offset to xu_iu_uc_flush_ifar2_offset + xu_iu_uc_flush_ifar2_l2'length-1), + din => xu_iu_uc_flush_ifar2_d, + dout => xu_iu_uc_flush_ifar2_l2); +xu_iu_uc_flush_ifar3_latch: tri_rlmreg_p + generic map (width => xu_iu_uc_flush_ifar3_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => uc_act(3), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_iu_uc_flush_ifar3_offset to xu_iu_uc_flush_ifar3_offset + xu_iu_uc_flush_ifar3_l2'length-1), + scout => sov(xu_iu_uc_flush_ifar3_offset to xu_iu_uc_flush_ifar3_offset + xu_iu_uc_flush_ifar3_l2'length-1), + din => xu_iu_uc_flush_ifar3_d, + dout => xu_iu_uc_flush_ifar3_l2); +fiss_uc_is2_ucode_vld_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(fiss_uc_is2_ucode_vld_offset), + scout => sov(fiss_uc_is2_ucode_vld_offset), + din => fiss_uc_is2_ucode_vld_d, + dout => fiss_uc_is2_ucode_vld_l2); +fiss_uc_is2_tid_latch: tri_rlmreg_p + generic map (width => fiss_uc_is2_tid_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(fiss_uc_is2_tid_offset to fiss_uc_is2_tid_offset + fiss_uc_is2_tid_l2'length-1), + scout => sov(fiss_uc_is2_tid_offset to fiss_uc_is2_tid_offset + fiss_uc_is2_tid_l2'length-1), + din => fiss_uc_is2_tid_d, + dout => fiss_uc_is2_tid_l2); +fiss_uc_is2_instr_latch: tri_rlmreg_p + generic map (width => fiss_uc_is2_instr_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(fiss_uc_is2_instr_offset to fiss_uc_is2_instr_offset + fiss_uc_is2_instr_l2'length-1), + scout => sov(fiss_uc_is2_instr_offset to fiss_uc_is2_instr_offset + fiss_uc_is2_instr_l2'length-1), + din => fiss_uc_is2_instr_d, + dout => fiss_uc_is2_instr_l2); +fiss_uc_is2_2ucode_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(fiss_uc_is2_2ucode_offset), + scout => sov(fiss_uc_is2_2ucode_offset), + din => fiss_uc_is2_2ucode_d, + dout => fiss_uc_is2_2ucode_l2); +fiss_uc_is2_2ucode_type_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(fiss_uc_is2_2ucode_type_offset), + scout => sov(fiss_uc_is2_2ucode_type_offset), + din => fiss_uc_is2_2ucode_type_d, + dout => fiss_uc_is2_2ucode_type_l2); +romtoken_latch: tri_rlmreg_p + generic map (width => romtoken_l2'length, init => 8, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => uc_any_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(romtoken_offset to romtoken_offset + romtoken_l2'length-1), + scout => sov(romtoken_offset to romtoken_offset + romtoken_l2'length-1), + din => romtoken_d, + dout => romtoken_l2); +romvalid_latch: tri_rlmreg_p + generic map (width => romvalid_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => uc_any_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(romvalid_offset to romvalid_offset + romvalid_l2'length-1), + scout => sov(romvalid_offset to romvalid_offset + romvalid_l2'length-1), + din => romvalid_d, + dout => romvalid_l2); +rom_data_late_latch: tri_rlmreg_p + generic map (width => rom_data_late_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu4_stage_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(rom_data_late_offset to rom_data_late_offset + rom_data_late_l2'length-1), + scout => sov(rom_data_late_offset to rom_data_late_offset + rom_data_late_l2'length-1), + din => rom_data_late_d, + dout => rom_data_late_l2); +iu4_valid_tid_0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => uc_act(0), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu4_valid_tid_offset+0), + scout => sov(iu4_valid_tid_offset+0), + din => iu4_valid_tid_d(0), + dout => iu4_valid_tid_l2(0)); +iu4_valid_tid_1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => uc_act(1), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu4_valid_tid_offset+1), + scout => sov(iu4_valid_tid_offset+1), + din => iu4_valid_tid_d(1), + dout => iu4_valid_tid_l2(1)); +iu4_valid_tid_2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => uc_act(2), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu4_valid_tid_offset+2), + scout => sov(iu4_valid_tid_offset+2), + din => iu4_valid_tid_d(2), + dout => iu4_valid_tid_l2(2)); +iu4_valid_tid_3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => uc_act(3), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu4_valid_tid_offset+3), + scout => sov(iu4_valid_tid_offset+3), + din => iu4_valid_tid_d(3), + dout => iu4_valid_tid_l2(3)); +iu4_data_tid_latch: tri_rlmreg_p + generic map (width => iu4_data_tid_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu4_stage_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu4_data_tid_offset to iu4_data_tid_offset + iu4_data_tid_l2'length-1), + scout => sov(iu4_data_tid_offset to iu4_data_tid_offset + iu4_data_tid_l2'length-1), + din => iu4_data_tid_d, + dout => iu4_data_tid_l2); +iu4_ifar_latch: tri_rlmreg_p + generic map (width => iu4_ifar_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu4_stage_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu4_ifar_offset to iu4_ifar_offset + iu4_ifar_l2'length-1), + scout => sov(iu4_ifar_offset to iu4_ifar_offset + iu4_ifar_l2'length-1), + din => iu4_ifar_d, + dout => iu4_ifar_l2); +iu4_is_ucode_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu4_stage_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu4_is_ucode_offset), + scout => sov(iu4_is_ucode_offset), + din => iu4_is_ucode_d, + dout => iu4_is_ucode_l2); +iu4_ext_latch: tri_rlmreg_p + generic map (width => iu4_ext_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu4_stage_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu4_ext_offset to iu4_ext_offset + iu4_ext_l2'length-1), + scout => sov(iu4_ext_offset to iu4_ext_offset + iu4_ext_l2'length-1), + din => iu4_ext_d, + dout => iu4_ext_l2); +trace_bus_enable_d <= pc_iu_trace_bus_enable; +trace_enable_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(trace_bus_enable_offset), + scout => sov(trace_bus_enable_offset), + din => trace_bus_enable_d, + dout => trace_bus_enable_q); +uc_dbg_data_latch: tri_rlmreg_p + generic map (width => uc_dbg_data_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => trace_bus_enable_q, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(uc_dbg_data_offset to uc_dbg_data_offset + uc_dbg_data_l2'length-1), + scout => sov(uc_dbg_data_offset to uc_dbg_data_offset + uc_dbg_data_l2'length-1), + din => uc_dbg_data_d, + dout => uc_dbg_data_l2); +spare_latch: tri_rlmreg_p + generic map (width => spare_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(spare_offset to spare_offset + spare_l2'length-1), + scout => sov(spare_offset to spare_offset + spare_l2'length-1), + din => spare_l2, + dout => spare_l2); +perv_2to1_reg: tri_plat + generic map (width => 2, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_iu_func_sl_thold_2, + din(1) => pc_iu_sg_2, + q(0) => pc_iu_func_sl_thold_1, + q(1) => pc_iu_sg_1); +perv_1to0_reg: tri_plat + generic map (width => 2, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_iu_func_sl_thold_1, + din(1) => pc_iu_sg_1, + q(0) => pc_iu_func_sl_thold_0, + q(1) => pc_iu_sg_0); +perv_lcbor: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_b, + thold => pc_iu_func_sl_thold_0, + sg => pc_iu_sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => pc_iu_func_sl_thold_0_b); +siv(0 TO scan_right+5) <= sov(1 to scan_right+5) & scan_in; +scan_out <= sov(0) and an_ac_scan_dis_dc_b; +END IUQ_UC; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_uc_control.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_uc_control.vhdl new file mode 100644 index 0000000..b541101 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_uc_control.vhdl @@ -0,0 +1,797 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee,ibm,support,tri,work; +use ieee.std_logic_1164.all; +use ibm.std_ulogic_unsigned.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use support.power_logic_pkg.all; +use tri.tri_latches_pkg.all; +use work.iuq_pkg.all; + + +entity iuq_uc_control is + generic(ucode_width : integer := 71; + expand_type : integer := 2); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + pc_iu_func_sl_thold_0_b : in std_ulogic; + pc_iu_sg_0 : in std_ulogic; + forcee : in std_ulogic; + d_mode : in std_ulogic; + delay_lclkr : in std_ulogic; + mpw1_b : in std_ulogic; + mpw2_b : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + spr_ic_clockgate_dis : in std_ulogic; + xu_iu_spr_xer : in std_ulogic_vector(57 to 63); + flush : in std_ulogic; + restart : in std_ulogic; + flush_ifar : in std_ulogic_vector(41 to 61); + ib_flush : in std_ulogic; + ib_flush_ifar : in std_ulogic_vector(41 to 61); + buff_avail : in std_ulogic; + load_command : in std_ulogic; + new_instr : in std_ulogic_vector(0 to 31); + start_addr : in std_ulogic_vector(0 to 9); + xer_type : in std_ulogic; + early_end : in std_ulogic; + force_ep : in std_ulogic; + new_cond : in std_ulogic; + + uc_act_thread : out std_ulogic; + vld_fast : out std_ulogic; + + ra_valid : out std_ulogic; + rom_ra : out std_ulogic_vector(0 to 9); + + data_valid : in std_ulogic; + rom_data : in std_ulogic_vector(32 to ucode_width-1); + rom_data_late : in std_ulogic_vector(0 to 31); + + ucode_valid : out std_ulogic; + ucode_ifar : out std_ulogic_vector(41 to 61); + ucode_instruction : out std_ulogic_vector(0 to 31); + is_uCode : out std_ulogic; + extRT : out std_ulogic; + extS1 : out std_ulogic; + extS2 : out std_ulogic; + extS3 : out std_ulogic; + + hold_thread : out std_ulogic; + + uc_control_dbg_data : out std_ulogic_vector(0 to 3) +); +-- synopsys translate_off + + + +-- synopsys translate_on + +end iuq_uc_control; + + +architecture iuq_uc_control of iuq_uc_control is + +constant xu_iu_spr_xer_offset : natural := 0; +constant bubble_offset : natural := xu_iu_spr_xer_offset + 7; +constant valid_offset : natural := bubble_offset + 1; +constant instr_offset : natural := valid_offset + 1; +constant instr_late_offset : natural := instr_offset + 32; +constant sel_late_offset : natural := instr_late_offset + 15; +constant early_end_offset : natural := sel_late_offset + 11; +constant cond_offset : natural := early_end_offset + 1; +constant rom_addr_offset : natural := cond_offset + 1; +constant inloop_offset : natural := rom_addr_offset + 10; +constant count_offset : natural := inloop_offset + 1; +constant skip_zero_offset : natural := count_offset + 5; +constant skip_to_np1_offset : natural := skip_zero_offset + 1; +constant skip_cond_offset : natural := skip_to_np1_offset + 1; +constant skip_offset : natural := skip_cond_offset + 1; +constant wait_offset : natural := skip_offset + 1; +constant force_ep_offset : natural := wait_offset + 1; +constant ep_force_late_offset : natural := force_ep_offset + 1; +constant scan_right : natural := ep_force_late_offset + 1 - 1; + +subtype s3 is std_ulogic_vector(0 to 2); + +signal bubble_fast : std_ulogic; +signal valid_fast : std_ulogic; + +signal xu_iu_spr_xer_d : std_ulogic_vector(57 to 63); +signal bubble_d : std_ulogic; +signal valid_d : std_ulogic; +signal instr_d : std_ulogic_vector(0 to 31); +signal early_end_d : std_ulogic; +signal cond_d : std_ulogic; +signal rom_addr_d : std_ulogic_vector(0 to 9); +signal inLoop_d : std_ulogic; +signal count_d : std_ulogic_vector(0 to 4); +signal skip_zero_d : std_ulogic; +signal skip_to_np1_d : std_ulogic; +signal skip_cond_d : std_ulogic; +signal skip_d : std_ulogic; +signal wait_d : std_ulogic; + +signal xu_iu_spr_xer_l2 : std_ulogic_vector(57 to 63); +signal bubble_l2 : std_ulogic; +signal valid_l2 : std_ulogic; +signal instr_l2 : std_ulogic_vector(0 to 31); +signal early_end_l2 : std_ulogic; +signal cond_l2 : std_ulogic; +signal rom_addr_l2 : std_ulogic_vector(0 to 9); +signal inLoop_l2 : std_ulogic; +signal count_l2 : std_ulogic_vector(0 to 4); +signal skip_zero_l2 : std_ulogic; +signal skip_to_np1_l2 : std_ulogic; +signal skip_cond_l2 : std_ulogic; +signal skip_l2 : std_ulogic; +signal wait_l2 : std_ulogic; + +signal force_ep_d : std_ulogic; +signal force_ep_l2 : std_ulogic; + + +signal new_command : std_ulogic; +signal uC_flush : std_ulogic; +signal uc_act : std_ulogic; + +signal template_code : std_ulogic_vector(0 to 31); +signal uc_end : std_ulogic; +signal uc_end_early : std_ulogic; +signal loop_begin : std_ulogic; +signal loop_end : std_ulogic; +signal loop_end_rom : std_ulogic; +signal count_src : std_ulogic_vector(0 to 2); +signal sel0_5 : std_ulogic; +signal sel6_10 : std_ulogic_vector(0 to 1); +signal sel11_15 : std_ulogic_vector(0 to 1); +signal sel16_20 : std_ulogic_vector(0 to 1); +signal sel21_25 : std_ulogic_vector(0 to 1); +signal sel26_30 : std_ulogic; +signal sel31 : std_ulogic; +signal cr_bf2fxm : std_ulogic; +signal skip_cond : std_ulogic; +signal skip_zero : std_ulogic; +signal loop_addr : std_ulogic_vector(0 to 9); +signal loop_init : std_ulogic_vector(0 to 2); +signal ep_instr : std_ulogic; + +signal ucode_end : std_ulogic; +signal fxm : std_ulogic_vector(0 to 7); + +signal sel0_5_late : std_ulogic; +signal sel6_10_late : std_ulogic_vector(0 to 1); +signal sel11_15_late : std_ulogic_vector(0 to 1); +signal sel16_20_late : std_ulogic_vector(0 to 1); +signal sel21_25_late : std_ulogic_vector(0 to 1); +signal sel26_30_late : std_ulogic; +signal sel31_late : std_ulogic; + +signal sel_late_d : std_ulogic_vector(0 to 10); +signal sel_late_l2 : std_ulogic_vector(0 to 10); +signal ep_force_late_d : std_ulogic; +signal ep_force_late_l2 : std_ulogic; +signal instr_late_d : std_ulogic_vector(6 to 20); +signal instr_late_l2 : std_ulogic_vector(6 to 20); + + +signal last_loop : std_ulogic; +signal loopback_part1 : std_ulogic; +signal loopback : std_ulogic; +signal inc_RT : std_ulogic; + +signal NB_dec : std_ulogic_vector(0 to 4); +signal NB_comp : std_ulogic_vector(0 to 1); +signal XER_dec_z : std_ulogic_vector(0 to 6); +signal XER_low : std_ulogic_vector(0 to 2); +signal XER_comp : std_ulogic_vector(0 to 1); +signal count_init : std_ulogic_vector(0 to 4); +signal skip : std_ulogic; + + +signal siv : std_ulogic_vector(0 to scan_right); +signal sov : std_ulogic_vector(0 to scan_right); + +begin + + + +new_command <= load_command and not bubble_l2; +uC_flush <= flush and not restart and (valid_l2 or wait_l2); + +uc_act <= load_command or valid_l2 or wait_l2 or spr_ic_clockgate_dis; +uc_act_thread <= uc_act; + +bubble_d <= not flush and new_command; + +valid_d <= (new_command and not flush) or + (valid_l2 and not (ucode_end and data_valid) and not flush) or + uC_flush or + (ib_flush and not flush); + + +bubble_fast <= bubble_d; + +valid_fast <= (new_command and not flush) or + (valid_l2 and not flush) or + uC_flush or + (ib_flush and not flush); + + +instr_d(0 to 5) <= new_instr(0 to 5) when new_command = '1' + else instr_l2(0 to 5); + +instr_d(6 to 10) <= flush_ifar(49 to 53) when flush = '1' + else ib_flush_ifar(49 to 53) when ib_flush = '1' + else new_instr(6 to 10) when new_command = '1' + else instr_l2(6 to 10) + 1 when inc_RT = '1' + else instr_l2(6 to 10); + +instr_d(11 to 31) <= new_instr(11 to 31) when new_command = '1' + else instr_l2(11 to 31); + +early_end_d <= early_end when new_command = '1' + else early_end_l2; + +cond_d <= new_cond when new_command = '1' + else cond_l2; + +force_ep_d <= force_ep when new_command = '1' + else force_ep_l2; + +rom_addr_d <= flush_ifar(41 to 42) & flush_ifar(54 to 61) when flush = '1' + else ib_flush_ifar(41 to 42) & ib_flush_ifar(54 to 61) when ib_flush = '1' + else start_addr when new_command = '1' + else loop_addr when loopback = '1' + else rom_addr_l2(0 to 1) & (rom_addr_l2(2 to 9) + 1) when data_valid = '1' + else rom_addr_l2; + +rom_ra <= rom_addr_d; + +ra_valid <= valid_d and not bubble_d and buff_avail; +vld_fast <= valid_fast and not bubble_fast and buff_avail; + +uc_end <= rom_data(32); +uc_end_early <= rom_data(33); +loop_begin <= rom_data(34); +loop_end <= rom_data(35) and inLoop_l2; +loop_end_rom <= rom_data(35); +count_src <= rom_data(36 to 38); +extRT <= rom_data(39); +extS1 <= rom_data(40); +extS2 <= rom_data(41); +extS3 <= rom_data(42); +sel0_5 <= rom_data(43); +sel6_10 <= rom_data(44 to 45); +sel11_15 <= rom_data(46 to 47); +sel16_20 <= rom_data(48 to 49); +sel21_25 <= rom_data(50 to 51); +sel26_30 <= rom_data(52); +sel31 <= rom_data(53); +cr_bf2fxm <= rom_data(54); +skip_cond <= rom_data(55); +skip_zero <= rom_data(56); +loop_addr <= rom_data(57 to 66); +loop_init <= rom_data(67 to 69); +ep_instr <= rom_data(70); + + +template_code(0 to 26) <= rom_data_late(0 to 26); +template_code(27) <= rom_data_late(27) or ep_force_late_l2; +template_code(28 to 31) <= rom_data_late(28 to 31); + +sel_late_d(0) <= sel0_5; +sel_late_d(1 to 2) <= sel6_10; +sel_late_d(3 to 4) <= sel11_15; +sel_late_d(5 to 6) <= sel16_20; +sel_late_d(7 to 8) <= sel21_25; +sel_late_d(9) <= sel26_30; +sel_late_d(10) <= sel31; + +sel0_5_late <= sel_late_l2(0); +sel6_10_late <= sel_late_l2(1 to 2); +sel11_15_late <= sel_late_l2(3 to 4); +sel16_20_late <= sel_late_l2(5 to 6); +sel21_25_late <= sel_late_l2(7 to 8); +sel26_30_late <= sel_late_l2(9); +sel31_late <= sel_late_l2(10); + +ep_force_late_d <= ep_instr and force_ep_l2; + +ucode_end <= uc_end or (uc_end_early and early_end_l2); + +with s3'(instr_l2(6 to 8)) select +fxm <= "10000000" when "000", + "01000000" when "001", + "00100000" when "010", + "00010000" when "011", + "00001000" when "100", + "00000100" when "101", + "00000010" when "110", + "00000001" when others; + +instr_late_d( 6 to 10) <= instr_l2( 6 to 10); +instr_late_d(11 to 20) <= instr_l2(11 to 20) when cr_bf2fxm = '0' else ('1' & fxm(0 to 7) & '0'); + + + +with sel0_5_late select +ucode_instruction(0 to 5) <= template_code(0 to 5) when '0', + instr_l2(0 to 5) when others; + +with sel6_10_late select +ucode_instruction(6 to 10) <= template_code(6 to 10) when "00", + instr_late_l2(6 to 10) when "01", + instr_late_l2(11 to 15) when "10", + instr_late_l2(16 to 20) when others; + + +with sel11_15_late select +ucode_instruction(11 to 15) <= template_code(11 to 15) when "00", + instr_late_l2(11 to 15) when "01", + instr_late_l2(16 to 20) when "10", + instr_late_l2(6 to 10) when others; + +with sel16_20_late select +ucode_instruction(16 to 20) <= template_code(16 to 20) when "00", + instr_late_l2(16 to 20) when "01", + instr_late_l2(6 to 10) when "10", + instr_late_l2(11 to 15) when others; + +with sel21_25_late select +ucode_instruction(21 to 25) <= template_code(21 to 25) when "00", + instr_l2(21 to 25) when "01", + instr_late_l2(16 to 20) when others; + +with sel26_30_late select +ucode_instruction(26 to 30) <= template_code(26 to 30) when '0', + instr_l2(26 to 30) when others; + +with sel31_late select +ucode_instruction(31) <= template_code(31) when '0', + instr_l2(31) when others; + +ucode_valid <= data_valid and not flush and not ib_flush and not skip; +is_ucode <= not ucode_end; + + +ucode_ifar(41 to 61) <= rom_addr_l2(0 to 1) & count_l2 & inLoop_l2 & instr_l2(6 to 10) & rom_addr_l2(2 to 9); + + +inLoop_d <= flush_ifar(48) when uC_flush = '1' + else '0' when flush = '1' + else ib_flush_ifar(48) when ib_flush = '1' + else (((data_valid and loop_begin) or inLoop_l2) and not ((data_valid and loop_end) and last_loop) and valid_l2 and not bubble_l2); + +last_loop <= (count_l2 = "00000") or (skip_zero_l2 and count_l2 = "00001") or skip_cond_l2; + +loopback_part1 <= data_valid and inLoop_l2 and not last_loop; +loopback <= loopback_part1 and loop_end_rom; + +inc_RT <= data_valid and loop_end and not (skip_zero_l2 and count_l2 = "00000") and + count_src(0) and not (count_src = "111"); + + + +NB_dec <= instr_l2(16 to 20) - 1; +NB_comp(0) <= instr_l2(19) xor instr_l2(20); +NB_comp(1) <= instr_l2(20); + + +xu_iu_spr_xer_d <= xu_iu_spr_xer; + +XER_dec_z <= "0000000" when xu_iu_spr_xer_l2(57 to 63) = "0000000" + else xu_iu_spr_xer_l2(57 to 63) - 1; +XER_low <= "100" when XER_dec_z(5 to 6) = "11" + else '0' & xu_iu_spr_xer_l2(62 to 63); +XER_comp(0) <= xu_iu_spr_xer_l2(62) xor xu_iu_spr_xer_l2(63); +XER_comp(1) <= xu_iu_spr_xer_l2(63); + +with count_src select +count_init <= "000" & NB_dec(3 to 4) when "000", + "000" & NB_comp(0 to 1) when "001", + "00" & XER_low when "010", + "000" & XER_comp(0 to 1) when "011", + not (instr_l2(6 to 10)) when "100", + "00" & NB_dec(0 to 2) when "101", + XER_dec_z(0 to 4) when "110", + "00" & loop_init when others; + + +count_d <= flush_ifar(43 to 47) when flush = '1' + else ib_flush_ifar(43 to 47) when ib_flush = '1' + else "00000" when new_command = '1' + else count_init when (data_valid and loop_begin and not inLoop_l2) = '1' + else count_l2 - 1 when ((data_valid and loop_end) = '1') + else count_l2; + + +skip_zero_d <= '0' when (flush or ib_flush or (data_valid and loop_end) or new_command) = '1' + else skip_zero when (data_valid and loop_begin) = '1' + else skip_zero_l2; + +skip_to_np1_d <= not restart when flush = '1' + else '0' when data_valid = '1' + else skip_to_np1_l2; + +skip_cond_d <= '0' when (flush or ib_flush or new_command) = '1' + else (skip_cond and cond_l2) when data_valid = '1' + else skip_cond_l2; + +skip <= (((skip_zero and loop_begin) or skip_zero_l2) and (count_l2 = "00000") and inLoop_l2) or + ( (skip_zero and loop_begin) and count_init = "00000" and not inLoop_l2) or + (skip_cond and cond_l2) or + skip_to_np1_l2; + +skip_d <= skip; + +wait_d <= ((valid_l2 and ucode_end and data_valid) or + wait_l2) + and not flush and not ib_flush; + + +hold_thread <= valid_l2 or wait_l2; + +uc_control_dbg_data <= bubble_l2 & valid_l2 & wait_l2 & skip_l2; + + +xu_iu_spr_xer_latch: tri_rlmreg_p + generic map (width => xu_iu_spr_xer_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => uc_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_iu_spr_xer_offset to xu_iu_spr_xer_offset + xu_iu_spr_xer_l2'length-1), + scout => sov(xu_iu_spr_xer_offset to xu_iu_spr_xer_offset + xu_iu_spr_xer_l2'length-1), + din => xu_iu_spr_xer_d, + dout => xu_iu_spr_xer_l2); + +bubble_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => uc_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(bubble_offset), + scout => sov(bubble_offset), + din => bubble_d, + dout => bubble_l2); + +valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => uc_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(valid_offset), + scout => sov(valid_offset), + din => valid_d, + dout => valid_l2); + +instr_latch: tri_rlmreg_p + generic map (width => instr_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => uc_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(instr_offset to instr_offset + instr_l2'length-1), + scout => sov(instr_offset to instr_offset + instr_l2'length-1), + din => instr_d, + dout => instr_l2); + +instr_late_latch: tri_rlmreg_p + generic map (width => instr_late_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => data_valid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(instr_late_offset to instr_late_offset + instr_late_l2'length-1), + scout => sov(instr_late_offset to instr_late_offset + instr_late_l2'length-1), + din => instr_late_d, + dout => instr_late_l2); + +sel_late_latch: tri_rlmreg_p + generic map (width => sel_late_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => data_valid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(sel_late_offset to sel_late_offset + sel_late_l2'length-1), + scout => sov(sel_late_offset to sel_late_offset + sel_late_l2'length-1), + din => sel_late_d, + dout => sel_late_l2); + +early_end_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => uc_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(early_end_offset), + scout => sov(early_end_offset), + din => early_end_d, + dout => early_end_l2); + +cond_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => uc_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(cond_offset), + scout => sov(cond_offset), + din => cond_d, + dout => cond_l2); + +rom_addr_latch: tri_rlmreg_p + generic map (width => rom_addr_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => uc_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(rom_addr_offset to rom_addr_offset + rom_addr_l2'length-1), + scout => sov(rom_addr_offset to rom_addr_offset + rom_addr_l2'length-1), + din => rom_addr_d, + dout => rom_addr_l2); + +count_latch: tri_rlmreg_p + generic map (width => count_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => uc_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(count_offset to count_offset + count_l2'length-1), + scout => sov(count_offset to count_offset + count_l2'length-1), + din => count_d, + dout => count_l2); + +inloop_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => uc_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(inloop_offset), + scout => sov(inloop_offset), + din => inloop_d, + dout => inloop_l2); + +skip_zero_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => uc_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(skip_zero_offset), + scout => sov(skip_zero_offset), + din => skip_zero_d, + dout => skip_zero_l2); + +skip_to_np1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => uc_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(skip_to_np1_offset), + scout => sov(skip_to_np1_offset), + din => skip_to_np1_d, + dout => skip_to_np1_l2); + +skip_cond_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => uc_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(skip_cond_offset), + scout => sov(skip_cond_offset), + din => skip_cond_d, + dout => skip_cond_l2); + +skip_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => uc_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(skip_offset), + scout => sov(skip_offset), + din => skip_d, + dout => skip_l2); + +wait_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => uc_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(wait_offset), + scout => sov(wait_offset), + din => wait_d, + dout => wait_l2); + +force_ep_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => uc_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(force_ep_offset), + scout => sov(force_ep_offset), + din => force_ep_d, + dout => force_ep_l2); + +ep_force_late_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => data_valid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(ep_force_late_offset), + scout => sov(ep_force_late_offset), + din => ep_force_late_d, + dout => ep_force_late_l2); + +siv(0 to scan_right) <= sov(1 to scan_right) & scan_in; +scan_out <= sov(0); + +end iuq_uc_control; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_uc_rom.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_uc_rom.vhdl new file mode 100644 index 0000000..d304ddf --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/iuq_uc_rom.vhdl @@ -0,0 +1,16287 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee,ibm,support,tri; +use ieee.std_logic_1164.all; +use ibm.std_ulogic_unsigned.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use support.power_logic_pkg.all; +use tri.tri_latches_pkg.all; + +entity iuq_uc_rom is + generic(ucode_width : integer := 71; + regmode : integer := 6; + expand_type : integer := 2); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + pc_iu_func_sl_thold_0_b : in std_ulogic; + pc_iu_sg_0 : in std_ulogic; + forcee : in std_ulogic; + d_mode : in std_ulogic; + delay_lclkr : in std_ulogic; + mpw1_b : in std_ulogic; + mpw2_b : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + rom_act : in std_ulogic; + rom_addr : in std_ulogic_vector(0 to 9); + rom_data : out std_ulogic_vector(0 to ucode_width-1) +); +-- synopsys translate_off +-- synopsys translate_on +end iuq_uc_rom; +ARCHITECTURE IUQ_UC_ROM + OF IUQ_UC_ROM + IS +SIGNAL ROM32_INSTR_PT : STD_ULOGIC_VECTOR(1 TO 893) := +(OTHERS=> 'U'); +SIGNAL ROM64_INSTR_PT : STD_ULOGIC_VECTOR(1 TO 890) := +(OTHERS=> 'U'); +SIGNAL count_src : STD_ULOGIC_VECTOR(0 TO 2) := +"UUU"; +SIGNAL cr_bf2fxm : STD_ULOGIC := +'U'; +SIGNAL ep : STD_ULOGIC := +'U'; +SIGNAL extRT : STD_ULOGIC := +'U'; +SIGNAL extS1 : STD_ULOGIC := +'U'; +SIGNAL extS2 : STD_ULOGIC := +'U'; +SIGNAL extS3 : STD_ULOGIC := +'U'; +SIGNAL loop_addr : STD_ULOGIC_VECTOR(0 TO 9) := +"UUUUUUUUUU"; +SIGNAL loop_begin : STD_ULOGIC := +'U'; +SIGNAL loop_end : STD_ULOGIC := +'U'; +SIGNAL loop_init : STD_ULOGIC_VECTOR(0 TO 2) := +"UUU"; +SIGNAL sel0_5 : STD_ULOGIC := +'U'; +SIGNAL sel11_15 : STD_ULOGIC_VECTOR(0 TO 1) := +"UU"; +SIGNAL sel16_20 : STD_ULOGIC_VECTOR(0 TO 1) := +"UU"; +SIGNAL sel21_25 : STD_ULOGIC_VECTOR(0 TO 1) := +"UU"; +SIGNAL sel26_30 : STD_ULOGIC := +'U'; +SIGNAL sel31 : STD_ULOGIC := +'U'; +SIGNAL sel6_10 : STD_ULOGIC_VECTOR(0 TO 1) := +"UU"; +SIGNAL skip_cond : STD_ULOGIC := +'U'; +SIGNAL skip_zero : STD_ULOGIC := +'U'; +SIGNAL template : STD_ULOGIC_VECTOR(0 TO 31) := +"UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU"; +SIGNAL ucode_end : STD_ULOGIC := +'U'; +SIGNAL ucode_end_early : STD_ULOGIC := +'U'; +constant rom_addr_offset : natural := 0; +constant scan_right : natural := rom_addr_offset + 10 - 1; +signal rom_addr_d : std_ulogic_vector(0 to 9); +signal rom_addr_l2 : std_ulogic_vector(0 to 9); +signal siv : std_ulogic_vector(0 to scan_right); +signal sov : std_ulogic_vector(0 to scan_right); +signal rom_unused : std_ulogic; +-- synopsys translate_off +-- synopsys translate_on + BEGIN + +c64: if (regmode = 6) generate +begin + + +ROM32_INSTR_PT <= (others => '0'); +rom_unused <= or_reduce(ROM32_INSTR_PT); +MQQ1:ROM64_INSTR_PT(1) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("100000000")); +MQQ2:ROM64_INSTR_PT(2) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10000000")); +MQQ3:ROM64_INSTR_PT(3) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011000000")); +MQQ4:ROM64_INSTR_PT(4) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("101000000")); +MQQ5:ROM64_INSTR_PT(5) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000000000")); +MQQ6:ROM64_INSTR_PT(6) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110000000")); +MQQ7:ROM64_INSTR_PT(7) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011000000")); +MQQ8:ROM64_INSTR_PT(8) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00100000")); +MQQ9:ROM64_INSTR_PT(9) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001100000")); +MQQ10:ROM64_INSTR_PT(10) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011100000")); +MQQ11:ROM64_INSTR_PT(11) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01100000")); +MQQ12:ROM64_INSTR_PT(12) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00000000")); +MQQ13:ROM64_INSTR_PT(13) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11000000")); +MQQ14:ROM64_INSTR_PT(14) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001010000")); +MQQ15:ROM64_INSTR_PT(15) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011010000")); +MQQ16:ROM64_INSTR_PT(16) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("101010000")); +MQQ17:ROM64_INSTR_PT(17) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0000110000")); +MQQ18:ROM64_INSTR_PT(18) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010110000")); +MQQ19:ROM64_INSTR_PT(19) <= + Eq(( ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0110000")); +MQQ20:ROM64_INSTR_PT(20) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011110000")); +MQQ21:ROM64_INSTR_PT(21) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011110000")); +MQQ22:ROM64_INSTR_PT(22) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110000")); +MQQ23:ROM64_INSTR_PT(23) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000010000")); +MQQ24:ROM64_INSTR_PT(24) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110000")); +MQQ25:ROM64_INSTR_PT(25) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110000")); +MQQ26:ROM64_INSTR_PT(26) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11000000")); +MQQ27:ROM64_INSTR_PT(27) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000100000")); +MQQ28:ROM64_INSTR_PT(28) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10010000")); +MQQ29:ROM64_INSTR_PT(29) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110000")); +MQQ30:ROM64_INSTR_PT(30) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110000")); +MQQ31:ROM64_INSTR_PT(31) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1110000")); +MQQ32:ROM64_INSTR_PT(32) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0010000")); +MQQ33:ROM64_INSTR_PT(33) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10010000")); +MQQ34:ROM64_INSTR_PT(34) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1010000")); +MQQ35:ROM64_INSTR_PT(35) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1110000")); +MQQ36:ROM64_INSTR_PT(36) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10001000")); +MQQ37:ROM64_INSTR_PT(37) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("101001000")); +MQQ38:ROM64_INSTR_PT(38) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110001000")); +MQQ39:ROM64_INSTR_PT(39) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01001000")); +MQQ40:ROM64_INSTR_PT(40) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110101000")); +MQQ41:ROM64_INSTR_PT(41) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001101000")); +MQQ42:ROM64_INSTR_PT(42) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011101000")); +MQQ43:ROM64_INSTR_PT(43) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011101000")); +MQQ44:ROM64_INSTR_PT(44) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000101000")); +MQQ45:ROM64_INSTR_PT(45) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("111101000")); +MQQ46:ROM64_INSTR_PT(46) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000001000")); +MQQ47:ROM64_INSTR_PT(47) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1101000")); +MQQ48:ROM64_INSTR_PT(48) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001011000")); +MQQ49:ROM64_INSTR_PT(49) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011011000")); +MQQ50:ROM64_INSTR_PT(50) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01011000")); +MQQ51:ROM64_INSTR_PT(51) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000111000")); +MQQ52:ROM64_INSTR_PT(52) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110111000")); +MQQ53:ROM64_INSTR_PT(53) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01111000")); +MQQ54:ROM64_INSTR_PT(54) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010011000")); +MQQ55:ROM64_INSTR_PT(55) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110111000")); +MQQ56:ROM64_INSTR_PT(56) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10111000")); +MQQ57:ROM64_INSTR_PT(57) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01111000")); +MQQ58:ROM64_INSTR_PT(58) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01001000")); +MQQ59:ROM64_INSTR_PT(59) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00011000")); +MQQ60:ROM64_INSTR_PT(60) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00011000")); +MQQ61:ROM64_INSTR_PT(61) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("100111000")); +MQQ62:ROM64_INSTR_PT(62) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110111000")); +MQQ63:ROM64_INSTR_PT(63) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000000000")); +MQQ64:ROM64_INSTR_PT(64) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01000000")); +MQQ65:ROM64_INSTR_PT(65) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10000000")); +MQQ66:ROM64_INSTR_PT(66) <= + Eq(( ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("010000")); +MQQ67:ROM64_INSTR_PT(67) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110000")); +MQQ68:ROM64_INSTR_PT(68) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1100000")); +MQQ69:ROM64_INSTR_PT(69) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1010000")); +MQQ70:ROM64_INSTR_PT(70) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000001000")); +MQQ71:ROM64_INSTR_PT(71) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01011000")); +MQQ72:ROM64_INSTR_PT(72) <= + Eq(( ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000")); +MQQ73:ROM64_INSTR_PT(73) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0100000100")); +MQQ74:ROM64_INSTR_PT(74) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001000100")); +MQQ75:ROM64_INSTR_PT(75) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("1101000100")); +MQQ76:ROM64_INSTR_PT(76) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011000100")); +MQQ77:ROM64_INSTR_PT(77) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011000100")); +MQQ78:ROM64_INSTR_PT(78) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011000100")); +MQQ79:ROM64_INSTR_PT(79) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10000100")); +MQQ80:ROM64_INSTR_PT(80) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0100100100")); +MQQ81:ROM64_INSTR_PT(81) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110100100")); +MQQ82:ROM64_INSTR_PT(82) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001100100")); +MQQ83:ROM64_INSTR_PT(83) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011100100")); +MQQ84:ROM64_INSTR_PT(84) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11100100")); +MQQ85:ROM64_INSTR_PT(85) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10100100")); +MQQ86:ROM64_INSTR_PT(86) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000000100")); +MQQ87:ROM64_INSTR_PT(87) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10000100")); +MQQ88:ROM64_INSTR_PT(88) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110100100")); +MQQ89:ROM64_INSTR_PT(89) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0100010100")); +MQQ90:ROM64_INSTR_PT(90) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110010100")); +MQQ91:ROM64_INSTR_PT(91) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001010100")); +MQQ92:ROM64_INSTR_PT(92) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011010100")); +MQQ93:ROM64_INSTR_PT(93) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01010100")); +MQQ94:ROM64_INSTR_PT(94) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1010100")); +MQQ95:ROM64_INSTR_PT(95) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0000110100")); +MQQ96:ROM64_INSTR_PT(96) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010110100")); +MQQ97:ROM64_INSTR_PT(97) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011110100")); +MQQ98:ROM64_INSTR_PT(98) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110100")); +MQQ99:ROM64_INSTR_PT(99) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000110100")); +MQQ100:ROM64_INSTR_PT(100) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110100")); +MQQ101:ROM64_INSTR_PT(101) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110100")); +MQQ102:ROM64_INSTR_PT(102) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01000100")); +MQQ103:ROM64_INSTR_PT(103) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10010100")); +MQQ104:ROM64_INSTR_PT(104) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110100")); +MQQ105:ROM64_INSTR_PT(105) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1010100")); +MQQ106:ROM64_INSTR_PT(106) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0100001100")); +MQQ107:ROM64_INSTR_PT(107) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001001100")); +MQQ108:ROM64_INSTR_PT(108) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("001001100")); +MQQ109:ROM64_INSTR_PT(109) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11001100")); +MQQ110:ROM64_INSTR_PT(110) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011001100")); +MQQ111:ROM64_INSTR_PT(111) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11001100")); +MQQ112:ROM64_INSTR_PT(112) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000101100")); +MQQ113:ROM64_INSTR_PT(113) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("100101100")); +MQQ114:ROM64_INSTR_PT(114) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010101100")); +MQQ115:ROM64_INSTR_PT(115) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110101100")); +MQQ116:ROM64_INSTR_PT(116) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011101100")); +MQQ117:ROM64_INSTR_PT(117) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01101100")); +MQQ118:ROM64_INSTR_PT(118) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01101100")); +MQQ119:ROM64_INSTR_PT(119) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110011100")); +MQQ120:ROM64_INSTR_PT(120) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11011100")); +MQQ121:ROM64_INSTR_PT(121) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011011100")); +MQQ122:ROM64_INSTR_PT(122) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11111100")); +MQQ123:ROM64_INSTR_PT(123) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("100111100")); +MQQ124:ROM64_INSTR_PT(124) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110111100")); +MQQ125:ROM64_INSTR_PT(125) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01111100")); +MQQ126:ROM64_INSTR_PT(126) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11111100")); +MQQ127:ROM64_INSTR_PT(127) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000011100")); +MQQ128:ROM64_INSTR_PT(128) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010011100")); +MQQ129:ROM64_INSTR_PT(129) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000111100")); +MQQ130:ROM64_INSTR_PT(130) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11111100")); +MQQ131:ROM64_INSTR_PT(131) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0011100")); +MQQ132:ROM64_INSTR_PT(132) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01111100")); +MQQ133:ROM64_INSTR_PT(133) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10001100")); +MQQ134:ROM64_INSTR_PT(134) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11101100")); +MQQ135:ROM64_INSTR_PT(135) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1101100")); +MQQ136:ROM64_INSTR_PT(136) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000111100")); +MQQ137:ROM64_INSTR_PT(137) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10111100")); +MQQ138:ROM64_INSTR_PT(138) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0100100")); +MQQ139:ROM64_INSTR_PT(139) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11010100")); +MQQ140:ROM64_INSTR_PT(140) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1010100")); +MQQ141:ROM64_INSTR_PT(141) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000001100")); +MQQ142:ROM64_INSTR_PT(142) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00001100")); +MQQ143:ROM64_INSTR_PT(143) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1101100")); +MQQ144:ROM64_INSTR_PT(144) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00111100")); +MQQ145:ROM64_INSTR_PT(145) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01111100")); +MQQ146:ROM64_INSTR_PT(146) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1001100")); +MQQ147:ROM64_INSTR_PT(147) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11000000")); +MQQ148:ROM64_INSTR_PT(148) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01010000")); +MQQ149:ROM64_INSTR_PT(149) <= + Eq(( ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("010000")); +MQQ150:ROM64_INSTR_PT(150) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01001000")); +MQQ151:ROM64_INSTR_PT(151) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1001000")); +MQQ152:ROM64_INSTR_PT(152) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("1000")); +MQQ153:ROM64_INSTR_PT(153) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000000100")); +MQQ154:ROM64_INSTR_PT(154) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01000100")); +MQQ155:ROM64_INSTR_PT(155) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10100100")); +MQQ156:ROM64_INSTR_PT(156) <= + Eq(( ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("00100")); +MQQ157:ROM64_INSTR_PT(157) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01111100")); +MQQ158:ROM64_INSTR_PT(158) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11111100")); +MQQ159:ROM64_INSTR_PT(159) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1111100")); +MQQ160:ROM64_INSTR_PT(160) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10011100")); +MQQ161:ROM64_INSTR_PT(161) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("011100")); +MQQ162:ROM64_INSTR_PT(162) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0111100")); +MQQ163:ROM64_INSTR_PT(163) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("01000")); +MQQ164:ROM64_INSTR_PT(164) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1000100")); +MQQ165:ROM64_INSTR_PT(165) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("10100")); +MQQ166:ROM64_INSTR_PT(166) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1101100")); +MQQ167:ROM64_INSTR_PT(167) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("01100")); +MQQ168:ROM64_INSTR_PT(168) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0100000010")); +MQQ169:ROM64_INSTR_PT(169) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("1101000010")); +MQQ170:ROM64_INSTR_PT(170) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011000010")); +MQQ171:ROM64_INSTR_PT(171) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("101000010")); +MQQ172:ROM64_INSTR_PT(172) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011000010")); +MQQ173:ROM64_INSTR_PT(173) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110100010")); +MQQ174:ROM64_INSTR_PT(174) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011100010")); +MQQ175:ROM64_INSTR_PT(175) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011100010")); +MQQ176:ROM64_INSTR_PT(176) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000000010")); +MQQ177:ROM64_INSTR_PT(177) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1100010")); +MQQ178:ROM64_INSTR_PT(178) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("000010")); +MQQ179:ROM64_INSTR_PT(179) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010010010")); +MQQ180:ROM64_INSTR_PT(180) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("001110010")); +MQQ181:ROM64_INSTR_PT(181) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011110010")); +MQQ182:ROM64_INSTR_PT(182) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110010")); +MQQ183:ROM64_INSTR_PT(183) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11110010")); +MQQ184:ROM64_INSTR_PT(184) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010010010")); +MQQ185:ROM64_INSTR_PT(185) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11010010")); +MQQ186:ROM64_INSTR_PT(186) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000110010")); +MQQ187:ROM64_INSTR_PT(187) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110010")); +MQQ188:ROM64_INSTR_PT(188) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110010")); +MQQ189:ROM64_INSTR_PT(189) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11000010")); +MQQ190:ROM64_INSTR_PT(190) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1000010")); +MQQ191:ROM64_INSTR_PT(191) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01100010")); +MQQ192:ROM64_INSTR_PT(192) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1100010")); +MQQ193:ROM64_INSTR_PT(193) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000110010")); +MQQ194:ROM64_INSTR_PT(194) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110010")); +MQQ195:ROM64_INSTR_PT(195) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1110010")); +MQQ196:ROM64_INSTR_PT(196) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110010")); +MQQ197:ROM64_INSTR_PT(197) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11110010")); +MQQ198:ROM64_INSTR_PT(198) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1010010")); +MQQ199:ROM64_INSTR_PT(199) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10001010")); +MQQ200:ROM64_INSTR_PT(200) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("1101001010")); +MQQ201:ROM64_INSTR_PT(201) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("001001010")); +MQQ202:ROM64_INSTR_PT(202) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00001010")); +MQQ203:ROM64_INSTR_PT(203) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011001010")); +MQQ204:ROM64_INSTR_PT(204) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10001010")); +MQQ205:ROM64_INSTR_PT(205) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011101010")); +MQQ206:ROM64_INSTR_PT(206) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011101010")); +MQQ207:ROM64_INSTR_PT(207) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110101010")); +MQQ208:ROM64_INSTR_PT(208) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000101010")); +MQQ209:ROM64_INSTR_PT(209) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10101010")); +MQQ210:ROM64_INSTR_PT(210) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00001010")); +MQQ211:ROM64_INSTR_PT(211) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110011010")); +MQQ212:ROM64_INSTR_PT(212) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10011010")); +MQQ213:ROM64_INSTR_PT(213) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11011010")); +MQQ214:ROM64_INSTR_PT(214) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011011010")); +MQQ215:ROM64_INSTR_PT(215) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00111010")); +MQQ216:ROM64_INSTR_PT(216) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011111010")); +MQQ217:ROM64_INSTR_PT(217) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10111010")); +MQQ218:ROM64_INSTR_PT(218) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01111010")); +MQQ219:ROM64_INSTR_PT(219) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010011010")); +MQQ220:ROM64_INSTR_PT(220) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01011010")); +MQQ221:ROM64_INSTR_PT(221) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("100111010")); +MQQ222:ROM64_INSTR_PT(222) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110111010")); +MQQ223:ROM64_INSTR_PT(223) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01111010")); +MQQ224:ROM64_INSTR_PT(224) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000101010")); +MQQ225:ROM64_INSTR_PT(225) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01011010")); +MQQ226:ROM64_INSTR_PT(226) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10011010")); +MQQ227:ROM64_INSTR_PT(227) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("011010")); +MQQ228:ROM64_INSTR_PT(228) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000100010")); +MQQ229:ROM64_INSTR_PT(229) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01100010")); +MQQ230:ROM64_INSTR_PT(230) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010010010")); +MQQ231:ROM64_INSTR_PT(231) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1010010")); +MQQ232:ROM64_INSTR_PT(232) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000001010")); +MQQ233:ROM64_INSTR_PT(233) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1101010")); +MQQ234:ROM64_INSTR_PT(234) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011010")); +MQQ235:ROM64_INSTR_PT(235) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("011010")); +MQQ236:ROM64_INSTR_PT(236) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0100000110")); +MQQ237:ROM64_INSTR_PT(237) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110000110")); +MQQ238:ROM64_INSTR_PT(238) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001000110")); +MQQ239:ROM64_INSTR_PT(239) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("1101000110")); +MQQ240:ROM64_INSTR_PT(240) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11000110")); +MQQ241:ROM64_INSTR_PT(241) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("101000110")); +MQQ242:ROM64_INSTR_PT(242) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("111000110")); +MQQ243:ROM64_INSTR_PT(243) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010000110")); +MQQ244:ROM64_INSTR_PT(244) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011000110")); +MQQ245:ROM64_INSTR_PT(245) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0000100110")); +MQQ246:ROM64_INSTR_PT(246) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001100110")); +MQQ247:ROM64_INSTR_PT(247) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("001100110")); +MQQ248:ROM64_INSTR_PT(248) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000000110")); +MQQ249:ROM64_INSTR_PT(249) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010000110")); +MQQ250:ROM64_INSTR_PT(250) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01000110")); +MQQ251:ROM64_INSTR_PT(251) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10100110")); +MQQ252:ROM64_INSTR_PT(252) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110010110")); +MQQ253:ROM64_INSTR_PT(253) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001010110")); +MQQ254:ROM64_INSTR_PT(254) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011010110")); +MQQ255:ROM64_INSTR_PT(255) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000110110")); +MQQ256:ROM64_INSTR_PT(256) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110110")); +MQQ257:ROM64_INSTR_PT(257) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011110110")); +MQQ258:ROM64_INSTR_PT(258) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110110")); +MQQ259:ROM64_INSTR_PT(259) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("100110110")); +MQQ260:ROM64_INSTR_PT(260) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110110")); +MQQ261:ROM64_INSTR_PT(261) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110110")); +MQQ262:ROM64_INSTR_PT(262) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1100110")); +MQQ263:ROM64_INSTR_PT(263) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("100110110")); +MQQ264:ROM64_INSTR_PT(264) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110110")); +MQQ265:ROM64_INSTR_PT(265) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("100001110")); +MQQ266:ROM64_INSTR_PT(266) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010001110")); +MQQ267:ROM64_INSTR_PT(267) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110001110")); +MQQ268:ROM64_INSTR_PT(268) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011001110")); +MQQ269:ROM64_INSTR_PT(269) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011001110")); +MQQ270:ROM64_INSTR_PT(270) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0000101110")); +MQQ271:ROM64_INSTR_PT(271) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("100101110")); +MQQ272:ROM64_INSTR_PT(272) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011101110")); +MQQ273:ROM64_INSTR_PT(273) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11101110")); +MQQ274:ROM64_INSTR_PT(274) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11101110")); +MQQ275:ROM64_INSTR_PT(275) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110101110")); +MQQ276:ROM64_INSTR_PT(276) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01101110")); +MQQ277:ROM64_INSTR_PT(277) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110011110")); +MQQ278:ROM64_INSTR_PT(278) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11011110")); +MQQ279:ROM64_INSTR_PT(279) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01011110")); +MQQ280:ROM64_INSTR_PT(280) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11111110")); +MQQ281:ROM64_INSTR_PT(281) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0111110")); +MQQ282:ROM64_INSTR_PT(282) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11111110")); +MQQ283:ROM64_INSTR_PT(283) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000011110")); +MQQ284:ROM64_INSTR_PT(284) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010011110")); +MQQ285:ROM64_INSTR_PT(285) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01011110")); +MQQ286:ROM64_INSTR_PT(286) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000111110")); +MQQ287:ROM64_INSTR_PT(287) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10111110")); +MQQ288:ROM64_INSTR_PT(288) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11111110")); +MQQ289:ROM64_INSTR_PT(289) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("111110")); +MQQ290:ROM64_INSTR_PT(290) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01011110")); +MQQ291:ROM64_INSTR_PT(291) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000111110")); +MQQ292:ROM64_INSTR_PT(292) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00111110")); +MQQ293:ROM64_INSTR_PT(293) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1111110")); +MQQ294:ROM64_INSTR_PT(294) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11110110")); +MQQ295:ROM64_INSTR_PT(295) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("100110")); +MQQ296:ROM64_INSTR_PT(296) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000001110")); +MQQ297:ROM64_INSTR_PT(297) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01011110")); +MQQ298:ROM64_INSTR_PT(298) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00111110")); +MQQ299:ROM64_INSTR_PT(299) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11011110")); +MQQ300:ROM64_INSTR_PT(300) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1111110")); +MQQ301:ROM64_INSTR_PT(301) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("101110")); +MQQ302:ROM64_INSTR_PT(302) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("101110")); +MQQ303:ROM64_INSTR_PT(303) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01000010")); +MQQ304:ROM64_INSTR_PT(304) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000011010")); +MQQ305:ROM64_INSTR_PT(305) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10011010")); +MQQ306:ROM64_INSTR_PT(306) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10011010")); +MQQ307:ROM64_INSTR_PT(307) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("101010")); +MQQ308:ROM64_INSTR_PT(308) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000000110")); +MQQ309:ROM64_INSTR_PT(309) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00000110")); +MQQ310:ROM64_INSTR_PT(310) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11010110")); +MQQ311:ROM64_INSTR_PT(311) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11110110")); +MQQ312:ROM64_INSTR_PT(312) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000001110")); +MQQ313:ROM64_INSTR_PT(313) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0001110")); +MQQ314:ROM64_INSTR_PT(314) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00111110")); +MQQ315:ROM64_INSTR_PT(315) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011110")); +MQQ316:ROM64_INSTR_PT(316) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00010110")); +MQQ317:ROM64_INSTR_PT(317) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("010010")); +MQQ318:ROM64_INSTR_PT(318) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("01010")); +MQQ319:ROM64_INSTR_PT(319) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011110")); +MQQ320:ROM64_INSTR_PT(320) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0000010")); +MQQ321:ROM64_INSTR_PT(321) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1000000")); +MQQ322:ROM64_INSTR_PT(322) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01010000")); +MQQ323:ROM64_INSTR_PT(323) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1000000")); +MQQ324:ROM64_INSTR_PT(324) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10101000")); +MQQ325:ROM64_INSTR_PT(325) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01101000")); +MQQ326:ROM64_INSTR_PT(326) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0101000")); +MQQ327:ROM64_INSTR_PT(327) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1100000")); +MQQ328:ROM64_INSTR_PT(328) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011000")); +MQQ329:ROM64_INSTR_PT(329) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0000100")); +MQQ330:ROM64_INSTR_PT(330) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11000100")); +MQQ331:ROM64_INSTR_PT(331) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00000100")); +MQQ332:ROM64_INSTR_PT(332) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00000100")); +MQQ333:ROM64_INSTR_PT(333) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1001100")); +MQQ334:ROM64_INSTR_PT(334) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00101100")); +MQQ335:ROM64_INSTR_PT(335) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11011100")); +MQQ336:ROM64_INSTR_PT(336) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1000000")); +MQQ337:ROM64_INSTR_PT(337) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1100010")); +MQQ338:ROM64_INSTR_PT(338) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1000010")); +MQQ339:ROM64_INSTR_PT(339) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1100010")); +MQQ340:ROM64_INSTR_PT(340) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10010010")); +MQQ341:ROM64_INSTR_PT(341) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110010")); +MQQ342:ROM64_INSTR_PT(342) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1010010")); +MQQ343:ROM64_INSTR_PT(343) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01001010")); +MQQ344:ROM64_INSTR_PT(344) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11001010")); +MQQ345:ROM64_INSTR_PT(345) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1100110")); +MQQ346:ROM64_INSTR_PT(346) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1111110")); +MQQ347:ROM64_INSTR_PT(347) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011110")); +MQQ348:ROM64_INSTR_PT(348) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011110")); +MQQ349:ROM64_INSTR_PT(349) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0101110")); +MQQ350:ROM64_INSTR_PT(350) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1111110")); +MQQ351:ROM64_INSTR_PT(351) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("101010")); +MQQ352:ROM64_INSTR_PT(352) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0101110")); +MQQ353:ROM64_INSTR_PT(353) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("011110")); +MQQ354:ROM64_INSTR_PT(354) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1000000")); +MQQ355:ROM64_INSTR_PT(355) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1101100")); +MQQ356:ROM64_INSTR_PT(356) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00000010")); +MQQ357:ROM64_INSTR_PT(357) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("100010")); +MQQ358:ROM64_INSTR_PT(358) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("110110")); +MQQ359:ROM64_INSTR_PT(359) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0011110")); +MQQ360:ROM64_INSTR_PT(360) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("100010")); +MQQ361:ROM64_INSTR_PT(361) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("100000001")); +MQQ362:ROM64_INSTR_PT(362) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001000001")); +MQQ363:ROM64_INSTR_PT(363) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011000001")); +MQQ364:ROM64_INSTR_PT(364) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110000001")); +MQQ365:ROM64_INSTR_PT(365) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011000001")); +MQQ366:ROM64_INSTR_PT(366) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011100001")); +MQQ367:ROM64_INSTR_PT(367) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11100001")); +MQQ368:ROM64_INSTR_PT(368) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000000001")); +MQQ369:ROM64_INSTR_PT(369) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11000001")); +MQQ370:ROM64_INSTR_PT(370) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010010001")); +MQQ371:ROM64_INSTR_PT(371) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011010001")); +MQQ372:ROM64_INSTR_PT(372) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000010001")); +MQQ373:ROM64_INSTR_PT(373) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000110001")); +MQQ374:ROM64_INSTR_PT(374) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010110001")); +MQQ375:ROM64_INSTR_PT(375) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("001110001")); +MQQ376:ROM64_INSTR_PT(376) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00110001")); +MQQ377:ROM64_INSTR_PT(377) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110001")); +MQQ378:ROM64_INSTR_PT(378) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11110001")); +MQQ379:ROM64_INSTR_PT(379) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110001")); +MQQ380:ROM64_INSTR_PT(380) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10110001")); +MQQ381:ROM64_INSTR_PT(381) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110001")); +MQQ382:ROM64_INSTR_PT(382) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1110001")); +MQQ383:ROM64_INSTR_PT(383) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11000001")); +MQQ384:ROM64_INSTR_PT(384) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1100001")); +MQQ385:ROM64_INSTR_PT(385) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("100110001")); +MQQ386:ROM64_INSTR_PT(386) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110001")); +MQQ387:ROM64_INSTR_PT(387) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1010001")); +MQQ388:ROM64_INSTR_PT(388) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10001001")); +MQQ389:ROM64_INSTR_PT(389) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("111001001")); +MQQ390:ROM64_INSTR_PT(390) <= + Eq(( ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1001001")); +MQQ391:ROM64_INSTR_PT(391) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01001001")); +MQQ392:ROM64_INSTR_PT(392) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000101001")); +MQQ393:ROM64_INSTR_PT(393) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00101001")); +MQQ394:ROM64_INSTR_PT(394) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110101001")); +MQQ395:ROM64_INSTR_PT(395) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001101001")); +MQQ396:ROM64_INSTR_PT(396) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011101001")); +MQQ397:ROM64_INSTR_PT(397) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011101001")); +MQQ398:ROM64_INSTR_PT(398) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("111101001")); +MQQ399:ROM64_INSTR_PT(399) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010001001")); +MQQ400:ROM64_INSTR_PT(400) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("001001")); +MQQ401:ROM64_INSTR_PT(401) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110011001")); +MQQ402:ROM64_INSTR_PT(402) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001011001")); +MQQ403:ROM64_INSTR_PT(403) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011111001")); +MQQ404:ROM64_INSTR_PT(404) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10111001")); +MQQ405:ROM64_INSTR_PT(405) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000011001")); +MQQ406:ROM64_INSTR_PT(406) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010011001")); +MQQ407:ROM64_INSTR_PT(407) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011001")); +MQQ408:ROM64_INSTR_PT(408) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110111001")); +MQQ409:ROM64_INSTR_PT(409) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01111001")); +MQQ410:ROM64_INSTR_PT(410) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10111001")); +MQQ411:ROM64_INSTR_PT(411) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10011001")); +MQQ412:ROM64_INSTR_PT(412) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110111001")); +MQQ413:ROM64_INSTR_PT(413) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10111001")); +MQQ414:ROM64_INSTR_PT(414) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01000001")); +MQQ415:ROM64_INSTR_PT(415) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11000001")); +MQQ416:ROM64_INSTR_PT(416) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01100001")); +MQQ417:ROM64_INSTR_PT(417) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01010001")); +MQQ418:ROM64_INSTR_PT(418) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1010001")); +MQQ419:ROM64_INSTR_PT(419) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01101001")); +MQQ420:ROM64_INSTR_PT(420) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01011001")); +MQQ421:ROM64_INSTR_PT(421) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0011001")); +MQQ422:ROM64_INSTR_PT(422) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0100000101")); +MQQ423:ROM64_INSTR_PT(423) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("1101000101")); +MQQ424:ROM64_INSTR_PT(424) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("101000101")); +MQQ425:ROM64_INSTR_PT(425) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011000101")); +MQQ426:ROM64_INSTR_PT(426) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000000101")); +MQQ427:ROM64_INSTR_PT(427) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011000101")); +MQQ428:ROM64_INSTR_PT(428) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11000101")); +MQQ429:ROM64_INSTR_PT(429) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0100100101")); +MQQ430:ROM64_INSTR_PT(430) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110100101")); +MQQ431:ROM64_INSTR_PT(431) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10100101")); +MQQ432:ROM64_INSTR_PT(432) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001100101")); +MQQ433:ROM64_INSTR_PT(433) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011100101")); +MQQ434:ROM64_INSTR_PT(434) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011100101")); +MQQ435:ROM64_INSTR_PT(435) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11100101")); +MQQ436:ROM64_INSTR_PT(436) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10100101")); +MQQ437:ROM64_INSTR_PT(437) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110010101")); +MQQ438:ROM64_INSTR_PT(438) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001010101")); +MQQ439:ROM64_INSTR_PT(439) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("101010101")); +MQQ440:ROM64_INSTR_PT(440) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01010101")); +MQQ441:ROM64_INSTR_PT(441) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0000110101")); +MQQ442:ROM64_INSTR_PT(442) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011110101")); +MQQ443:ROM64_INSTR_PT(443) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110101")); +MQQ444:ROM64_INSTR_PT(444) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110101")); +MQQ445:ROM64_INSTR_PT(445) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110101")); +MQQ446:ROM64_INSTR_PT(446) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01000101")); +MQQ447:ROM64_INSTR_PT(447) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1100101")); +MQQ448:ROM64_INSTR_PT(448) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110101")); +MQQ449:ROM64_INSTR_PT(449) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("110101")); +MQQ450:ROM64_INSTR_PT(450) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1010101")); +MQQ451:ROM64_INSTR_PT(451) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0100001101")); +MQQ452:ROM64_INSTR_PT(452) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110001101")); +MQQ453:ROM64_INSTR_PT(453) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001001101")); +MQQ454:ROM64_INSTR_PT(454) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011001101")); +MQQ455:ROM64_INSTR_PT(455) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010101101")); +MQQ456:ROM64_INSTR_PT(456) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110101101")); +MQQ457:ROM64_INSTR_PT(457) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011101101")); +MQQ458:ROM64_INSTR_PT(458) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011101101")); +MQQ459:ROM64_INSTR_PT(459) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01001101")); +MQQ460:ROM64_INSTR_PT(460) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01101101")); +MQQ461:ROM64_INSTR_PT(461) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11011101")); +MQQ462:ROM64_INSTR_PT(462) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11011101")); +MQQ463:ROM64_INSTR_PT(463) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11111101")); +MQQ464:ROM64_INSTR_PT(464) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10111101")); +MQQ465:ROM64_INSTR_PT(465) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000011101")); +MQQ466:ROM64_INSTR_PT(466) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010011101")); +MQQ467:ROM64_INSTR_PT(467) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000111101")); +MQQ468:ROM64_INSTR_PT(468) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("100111101")); +MQQ469:ROM64_INSTR_PT(469) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0111101")); +MQQ470:ROM64_INSTR_PT(470) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11111101")); +MQQ471:ROM64_INSTR_PT(471) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11001101")); +MQQ472:ROM64_INSTR_PT(472) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01100101")); +MQQ473:ROM64_INSTR_PT(473) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000010101")); +MQQ474:ROM64_INSTR_PT(474) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000110101")); +MQQ475:ROM64_INSTR_PT(475) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1010101")); +MQQ476:ROM64_INSTR_PT(476) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("010101")); +MQQ477:ROM64_INSTR_PT(477) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00001101")); +MQQ478:ROM64_INSTR_PT(478) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01001101")); +MQQ479:ROM64_INSTR_PT(479) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1001101")); +MQQ480:ROM64_INSTR_PT(480) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11011101")); +MQQ481:ROM64_INSTR_PT(481) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0111101")); +MQQ482:ROM64_INSTR_PT(482) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11000001")); +MQQ483:ROM64_INSTR_PT(483) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01010001")); +MQQ484:ROM64_INSTR_PT(484) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10110001")); +MQQ485:ROM64_INSTR_PT(485) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01001001")); +MQQ486:ROM64_INSTR_PT(486) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0001001")); +MQQ487:ROM64_INSTR_PT(487) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10101001")); +MQQ488:ROM64_INSTR_PT(488) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10011001")); +MQQ489:ROM64_INSTR_PT(489) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000111001")); +MQQ490:ROM64_INSTR_PT(490) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01111001")); +MQQ491:ROM64_INSTR_PT(491) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000000101")); +MQQ492:ROM64_INSTR_PT(492) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000100101")); +MQQ493:ROM64_INSTR_PT(493) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10100101")); +MQQ494:ROM64_INSTR_PT(494) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("100101")); +MQQ495:ROM64_INSTR_PT(495) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00111101")); +MQQ496:ROM64_INSTR_PT(496) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10011101")); +MQQ497:ROM64_INSTR_PT(497) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0111101")); +MQQ498:ROM64_INSTR_PT(498) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0101101")); +MQQ499:ROM64_INSTR_PT(499) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0001101")); +MQQ500:ROM64_INSTR_PT(500) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0000001")); +MQQ501:ROM64_INSTR_PT(501) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("001101")); +MQQ502:ROM64_INSTR_PT(502) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("001")); +MQQ503:ROM64_INSTR_PT(503) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0100000011")); +MQQ504:ROM64_INSTR_PT(504) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010000011")); +MQQ505:ROM64_INSTR_PT(505) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("1101000011")); +MQQ506:ROM64_INSTR_PT(506) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011000011")); +MQQ507:ROM64_INSTR_PT(507) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11000011")); +MQQ508:ROM64_INSTR_PT(508) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010100011")); +MQQ509:ROM64_INSTR_PT(509) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10100011")); +MQQ510:ROM64_INSTR_PT(510) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011100011")); +MQQ511:ROM64_INSTR_PT(511) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000000011")); +MQQ512:ROM64_INSTR_PT(512) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10100011")); +MQQ513:ROM64_INSTR_PT(513) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1000011")); +MQQ514:ROM64_INSTR_PT(514) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00010011")); +MQQ515:ROM64_INSTR_PT(515) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010010011")); +MQQ516:ROM64_INSTR_PT(516) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00010011")); +MQQ517:ROM64_INSTR_PT(517) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10010011")); +MQQ518:ROM64_INSTR_PT(518) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10010011")); +MQQ519:ROM64_INSTR_PT(519) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("001110011")); +MQQ520:ROM64_INSTR_PT(520) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011110011")); +MQQ521:ROM64_INSTR_PT(521) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000110011")); +MQQ522:ROM64_INSTR_PT(522) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110011")); +MQQ523:ROM64_INSTR_PT(523) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110011")); +MQQ524:ROM64_INSTR_PT(524) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01000011")); +MQQ525:ROM64_INSTR_PT(525) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01100011")); +MQQ526:ROM64_INSTR_PT(526) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1100011")); +MQQ527:ROM64_INSTR_PT(527) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10010011")); +MQQ528:ROM64_INSTR_PT(528) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000110011")); +MQQ529:ROM64_INSTR_PT(529) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1010011")); +MQQ530:ROM64_INSTR_PT(530) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10001011")); +MQQ531:ROM64_INSTR_PT(531) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("1101001011")); +MQQ532:ROM64_INSTR_PT(532) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("001001011")); +MQQ533:ROM64_INSTR_PT(533) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("111001011")); +MQQ534:ROM64_INSTR_PT(534) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0000101011")); +MQQ535:ROM64_INSTR_PT(535) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110101011")); +MQQ536:ROM64_INSTR_PT(536) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("001101011")); +MQQ537:ROM64_INSTR_PT(537) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011101011")); +MQQ538:ROM64_INSTR_PT(538) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01101011")); +MQQ539:ROM64_INSTR_PT(539) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010001011")); +MQQ540:ROM64_INSTR_PT(540) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01101011")); +MQQ541:ROM64_INSTR_PT(541) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10011011")); +MQQ542:ROM64_INSTR_PT(542) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11011011")); +MQQ543:ROM64_INSTR_PT(543) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0011011")); +MQQ544:ROM64_INSTR_PT(544) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11111011")); +MQQ545:ROM64_INSTR_PT(545) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010011011")); +MQQ546:ROM64_INSTR_PT(546) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01011011")); +MQQ547:ROM64_INSTR_PT(547) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11011011")); +MQQ548:ROM64_INSTR_PT(548) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11111011")); +MQQ549:ROM64_INSTR_PT(549) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000101011")); +MQQ550:ROM64_INSTR_PT(550) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011011")); +MQQ551:ROM64_INSTR_PT(551) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("11011")); +MQQ552:ROM64_INSTR_PT(552) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000100011")); +MQQ553:ROM64_INSTR_PT(553) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01100011")); +MQQ554:ROM64_INSTR_PT(554) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010010011")); +MQQ555:ROM64_INSTR_PT(555) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10110011")); +MQQ556:ROM64_INSTR_PT(556) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00001011")); +MQQ557:ROM64_INSTR_PT(557) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1101011")); +MQQ558:ROM64_INSTR_PT(558) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000011011")); +MQQ559:ROM64_INSTR_PT(559) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011011")); +MQQ560:ROM64_INSTR_PT(560) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000111011")); +MQQ561:ROM64_INSTR_PT(561) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0101011")); +MQQ562:ROM64_INSTR_PT(562) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00011011")); +MQQ563:ROM64_INSTR_PT(563) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0111011")); +MQQ564:ROM64_INSTR_PT(564) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1111011")); +MQQ565:ROM64_INSTR_PT(565) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("11011")); +MQQ566:ROM64_INSTR_PT(566) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010000111")); +MQQ567:ROM64_INSTR_PT(567) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00000111")); +MQQ568:ROM64_INSTR_PT(568) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110000111")); +MQQ569:ROM64_INSTR_PT(569) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001000111")); +MQQ570:ROM64_INSTR_PT(570) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011000111")); +MQQ571:ROM64_INSTR_PT(571) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011000111")); +MQQ572:ROM64_INSTR_PT(572) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010100111")); +MQQ573:ROM64_INSTR_PT(573) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110100111")); +MQQ574:ROM64_INSTR_PT(574) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10100111")); +MQQ575:ROM64_INSTR_PT(575) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001100111")); +MQQ576:ROM64_INSTR_PT(576) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011100111")); +MQQ577:ROM64_INSTR_PT(577) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011100111")); +MQQ578:ROM64_INSTR_PT(578) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00000111")); +MQQ579:ROM64_INSTR_PT(579) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000010111")); +MQQ580:ROM64_INSTR_PT(580) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10010111")); +MQQ581:ROM64_INSTR_PT(581) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("001010111")); +MQQ582:ROM64_INSTR_PT(582) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011010111")); +MQQ583:ROM64_INSTR_PT(583) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110111")); +MQQ584:ROM64_INSTR_PT(584) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01010111")); +MQQ585:ROM64_INSTR_PT(585) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010000111")); +MQQ586:ROM64_INSTR_PT(586) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01100111")); +MQQ587:ROM64_INSTR_PT(587) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010010111")); +MQQ588:ROM64_INSTR_PT(588) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000001111")); +MQQ589:ROM64_INSTR_PT(589) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0100001111")); +MQQ590:ROM64_INSTR_PT(590) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010001111")); +MQQ591:ROM64_INSTR_PT(591) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10001111")); +MQQ592:ROM64_INSTR_PT(592) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11001111")); +MQQ593:ROM64_INSTR_PT(593) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10001111")); +MQQ594:ROM64_INSTR_PT(594) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0001111")); +MQQ595:ROM64_INSTR_PT(595) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0000101111")); +MQQ596:ROM64_INSTR_PT(596) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010101111")); +MQQ597:ROM64_INSTR_PT(597) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001101111")); +MQQ598:ROM64_INSTR_PT(598) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11101111")); +MQQ599:ROM64_INSTR_PT(599) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11101111")); +MQQ600:ROM64_INSTR_PT(600) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11101111")); +MQQ601:ROM64_INSTR_PT(601) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00011111")); +MQQ602:ROM64_INSTR_PT(602) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10011111")); +MQQ603:ROM64_INSTR_PT(603) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("001011111")); +MQQ604:ROM64_INSTR_PT(604) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000111111")); +MQQ605:ROM64_INSTR_PT(605) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01111111")); +MQQ606:ROM64_INSTR_PT(606) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11111111")); +MQQ607:ROM64_INSTR_PT(607) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011111")); +MQQ608:ROM64_INSTR_PT(608) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10011111")); +MQQ609:ROM64_INSTR_PT(609) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1111111")); +MQQ610:ROM64_INSTR_PT(610) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10111111")); +MQQ611:ROM64_INSTR_PT(611) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01111111")); +MQQ612:ROM64_INSTR_PT(612) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11111111")); +MQQ613:ROM64_INSTR_PT(613) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01101111")); +MQQ614:ROM64_INSTR_PT(614) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011111")); +MQQ615:ROM64_INSTR_PT(615) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10111111")); +MQQ616:ROM64_INSTR_PT(616) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01111111")); +MQQ617:ROM64_INSTR_PT(617) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("111111")); +MQQ618:ROM64_INSTR_PT(618) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("111111")); +MQQ619:ROM64_INSTR_PT(619) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11110111")); +MQQ620:ROM64_INSTR_PT(620) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1100111")); +MQQ621:ROM64_INSTR_PT(621) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01011111")); +MQQ622:ROM64_INSTR_PT(622) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011111")); +MQQ623:ROM64_INSTR_PT(623) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01111111")); +MQQ624:ROM64_INSTR_PT(624) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011111")); +MQQ625:ROM64_INSTR_PT(625) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0111111")); +MQQ626:ROM64_INSTR_PT(626) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01001111")); +MQQ627:ROM64_INSTR_PT(627) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011111")); +MQQ628:ROM64_INSTR_PT(628) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0111111")); +MQQ629:ROM64_INSTR_PT(629) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0111111")); +MQQ630:ROM64_INSTR_PT(630) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("100011")); +MQQ631:ROM64_INSTR_PT(631) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("110011")); +MQQ632:ROM64_INSTR_PT(632) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01101011")); +MQQ633:ROM64_INSTR_PT(633) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000011011")); +MQQ634:ROM64_INSTR_PT(634) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000111011")); +MQQ635:ROM64_INSTR_PT(635) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00111011")); +MQQ636:ROM64_INSTR_PT(636) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01001011")); +MQQ637:ROM64_INSTR_PT(637) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11011011")); +MQQ638:ROM64_INSTR_PT(638) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("10011")); +MQQ639:ROM64_INSTR_PT(639) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000100111")); +MQQ640:ROM64_INSTR_PT(640) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110111")); +MQQ641:ROM64_INSTR_PT(641) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1000111")); +MQQ642:ROM64_INSTR_PT(642) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0111111")); +MQQ643:ROM64_INSTR_PT(643) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("111111")); +MQQ644:ROM64_INSTR_PT(644) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("111111")); +MQQ645:ROM64_INSTR_PT(645) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1110111")); +MQQ646:ROM64_INSTR_PT(646) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11011111")); +MQQ647:ROM64_INSTR_PT(647) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("11111")); +MQQ648:ROM64_INSTR_PT(648) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1111111")); +MQQ649:ROM64_INSTR_PT(649) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("111111")); +MQQ650:ROM64_INSTR_PT(650) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("11111")); +MQQ651:ROM64_INSTR_PT(651) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("10111")); +MQQ652:ROM64_INSTR_PT(652) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("11011")); +MQQ653:ROM64_INSTR_PT(653) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11000001")); +MQQ654:ROM64_INSTR_PT(654) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1000001")); +MQQ655:ROM64_INSTR_PT(655) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110001")); +MQQ656:ROM64_INSTR_PT(656) <= + Eq(( ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("110001")); +MQQ657:ROM64_INSTR_PT(657) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10101001")); +MQQ658:ROM64_INSTR_PT(658) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1001001")); +MQQ659:ROM64_INSTR_PT(659) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00011001")); +MQQ660:ROM64_INSTR_PT(660) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("101001")); +MQQ661:ROM64_INSTR_PT(661) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00000101")); +MQQ662:ROM64_INSTR_PT(662) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01000101")); +MQQ663:ROM64_INSTR_PT(663) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000100101")); +MQQ664:ROM64_INSTR_PT(664) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11110101")); +MQQ665:ROM64_INSTR_PT(665) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11001101")); +MQQ666:ROM64_INSTR_PT(666) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10011101")); +MQQ667:ROM64_INSTR_PT(667) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011101")); +MQQ668:ROM64_INSTR_PT(668) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1000001")); +MQQ669:ROM64_INSTR_PT(669) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("010001")); +MQQ670:ROM64_INSTR_PT(670) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("110001")); +MQQ671:ROM64_INSTR_PT(671) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0001001")); +MQQ672:ROM64_INSTR_PT(672) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0010101")); +MQQ673:ROM64_INSTR_PT(673) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("011101")); +MQQ674:ROM64_INSTR_PT(674) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1000011")); +MQQ675:ROM64_INSTR_PT(675) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110100011")); +MQQ676:ROM64_INSTR_PT(676) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("100011")); +MQQ677:ROM64_INSTR_PT(677) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01001011")); +MQQ678:ROM64_INSTR_PT(678) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10101011")); +MQQ679:ROM64_INSTR_PT(679) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10011011")); +MQQ680:ROM64_INSTR_PT(680) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011011")); +MQQ681:ROM64_INSTR_PT(681) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01001011")); +MQQ682:ROM64_INSTR_PT(682) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11011011")); +MQQ683:ROM64_INSTR_PT(683) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("010011")); +MQQ684:ROM64_INSTR_PT(684) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110100111")); +MQQ685:ROM64_INSTR_PT(685) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10010111")); +MQQ686:ROM64_INSTR_PT(686) <= + Eq(( ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0111")); +MQQ687:ROM64_INSTR_PT(687) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10001111")); +MQQ688:ROM64_INSTR_PT(688) <= + Eq(( ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("101111")); +MQQ689:ROM64_INSTR_PT(689) <= + Eq(( ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("011111")); +MQQ690:ROM64_INSTR_PT(690) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1111111")); +MQQ691:ROM64_INSTR_PT(691) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0111111")); +MQQ692:ROM64_INSTR_PT(692) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("101111")); +MQQ693:ROM64_INSTR_PT(693) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("111111")); +MQQ694:ROM64_INSTR_PT(694) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1000111")); +MQQ695:ROM64_INSTR_PT(695) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1110111")); +MQQ696:ROM64_INSTR_PT(696) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("000111")); +MQQ697:ROM64_INSTR_PT(697) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("110111")); +MQQ698:ROM64_INSTR_PT(698) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11011111")); +MQQ699:ROM64_INSTR_PT(699) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1111111")); +MQQ700:ROM64_INSTR_PT(700) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("011011")); +MQQ701:ROM64_INSTR_PT(701) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("11011")); +MQQ702:ROM64_INSTR_PT(702) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("110111")); +MQQ703:ROM64_INSTR_PT(703) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0101111")); +MQQ704:ROM64_INSTR_PT(704) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011111")); +MQQ705:ROM64_INSTR_PT(705) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1111111")); +MQQ706:ROM64_INSTR_PT(706) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1000001")); +MQQ707:ROM64_INSTR_PT(707) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("010001")); +MQQ708:ROM64_INSTR_PT(708) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1001001")); +MQQ709:ROM64_INSTR_PT(709) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("111001")); +MQQ710:ROM64_INSTR_PT(710) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("100101")); +MQQ711:ROM64_INSTR_PT(711) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("100001")); +MQQ712:ROM64_INSTR_PT(712) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("111101")); +MQQ713:ROM64_INSTR_PT(713) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0110111")); +MQQ714:ROM64_INSTR_PT(714) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("110111")); +MQQ715:ROM64_INSTR_PT(715) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1111111")); +MQQ716:ROM64_INSTR_PT(716) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("111111")); +MQQ717:ROM64_INSTR_PT(717) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("011111")); +MQQ718:ROM64_INSTR_PT(718) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("11011")); +MQQ719:ROM64_INSTR_PT(719) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("100101")); +MQQ720:ROM64_INSTR_PT(720) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("100011")); +MQQ721:ROM64_INSTR_PT(721) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("1101")); +MQQ722:ROM64_INSTR_PT(722) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("01100000")); +MQQ723:ROM64_INSTR_PT(723) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("01100000")); +MQQ724:ROM64_INSTR_PT(724) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("010010000")); +MQQ725:ROM64_INSTR_PT(725) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("000110000")); +MQQ726:ROM64_INSTR_PT(726) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("01110000")); +MQQ727:ROM64_INSTR_PT(727) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0100000")); +MQQ728:ROM64_INSTR_PT(728) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("010001000")); +MQQ729:ROM64_INSTR_PT(729) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("11011000")); +MQQ730:ROM64_INSTR_PT(730) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("111000")); +MQQ731:ROM64_INSTR_PT(731) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0111000")); +MQQ732:ROM64_INSTR_PT(732) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("110000")); +MQQ733:ROM64_INSTR_PT(733) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("00000100")); +MQQ734:ROM64_INSTR_PT(734) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0000100")); +MQQ735:ROM64_INSTR_PT(735) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("01100100")); +MQQ736:ROM64_INSTR_PT(736) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1100100")); +MQQ737:ROM64_INSTR_PT(737) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("100100")); +MQQ738:ROM64_INSTR_PT(738) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("010010100")); +MQQ739:ROM64_INSTR_PT(739) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("01101100")); +MQQ740:ROM64_INSTR_PT(740) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("01101100")); +MQQ741:ROM64_INSTR_PT(741) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("10011100")); +MQQ742:ROM64_INSTR_PT(742) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("101100")); +MQQ743:ROM64_INSTR_PT(743) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0111100")); +MQQ744:ROM64_INSTR_PT(744) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0100100")); +MQQ745:ROM64_INSTR_PT(745) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0100000")); +MQQ746:ROM64_INSTR_PT(746) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1100000")); +MQQ747:ROM64_INSTR_PT(747) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("00000100")); +MQQ748:ROM64_INSTR_PT(748) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0101100")); +MQQ749:ROM64_INSTR_PT(749) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("011100")); +MQQ750:ROM64_INSTR_PT(750) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1101100")); +MQQ751:ROM64_INSTR_PT(751) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("11100")); +MQQ752:ROM64_INSTR_PT(752) <= + Eq(( ROM_ADDR_L2(3) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("000")); +MQQ753:ROM64_INSTR_PT(753) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("01100010")); +MQQ754:ROM64_INSTR_PT(754) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("00010010")); +MQQ755:ROM64_INSTR_PT(755) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("00000010")); +MQQ756:ROM64_INSTR_PT(756) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("11001010")); +MQQ757:ROM64_INSTR_PT(757) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("111010")); +MQQ758:ROM64_INSTR_PT(758) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1111010")); +MQQ759:ROM64_INSTR_PT(759) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("101010")); +MQQ760:ROM64_INSTR_PT(760) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1000110")); +MQQ761:ROM64_INSTR_PT(761) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("110100110")); +MQQ762:ROM64_INSTR_PT(762) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0010110")); +MQQ763:ROM64_INSTR_PT(763) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("010110")); +MQQ764:ROM64_INSTR_PT(764) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0001110")); +MQQ765:ROM64_INSTR_PT(765) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("00011110")); +MQQ766:ROM64_INSTR_PT(766) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("10011110")); +MQQ767:ROM64_INSTR_PT(767) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1010010")); +MQQ768:ROM64_INSTR_PT(768) <= + Eq(( ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("0110")); +MQQ769:ROM64_INSTR_PT(769) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("00011110")); +MQQ770:ROM64_INSTR_PT(770) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1111110")); +MQQ771:ROM64_INSTR_PT(771) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("010110")); +MQQ772:ROM64_INSTR_PT(772) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("10000")); +MQQ773:ROM64_INSTR_PT(773) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1101100")); +MQQ774:ROM64_INSTR_PT(774) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("011100")); +MQQ775:ROM64_INSTR_PT(775) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("00100")); +MQQ776:ROM64_INSTR_PT(776) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0100010")); +MQQ777:ROM64_INSTR_PT(777) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("11010010")); +MQQ778:ROM64_INSTR_PT(778) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("101010")); +MQQ779:ROM64_INSTR_PT(779) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("01110")); +MQQ780:ROM64_INSTR_PT(780) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("01110")); +MQQ781:ROM64_INSTR_PT(781) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("01000001")); +MQQ782:ROM64_INSTR_PT(782) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("110100001")); +MQQ783:ROM64_INSTR_PT(783) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("01010001")); +MQQ784:ROM64_INSTR_PT(784) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("11010001")); +MQQ785:ROM64_INSTR_PT(785) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1010001")); +MQQ786:ROM64_INSTR_PT(786) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0000001")); +MQQ787:ROM64_INSTR_PT(787) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("010001")); +MQQ788:ROM64_INSTR_PT(788) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0001001")); +MQQ789:ROM64_INSTR_PT(789) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("001001")); +MQQ790:ROM64_INSTR_PT(790) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("00011001")); +MQQ791:ROM64_INSTR_PT(791) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("111001")); +MQQ792:ROM64_INSTR_PT(792) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("00011001")); +MQQ793:ROM64_INSTR_PT(793) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("111001")); +MQQ794:ROM64_INSTR_PT(794) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("00100101")); +MQQ795:ROM64_INSTR_PT(795) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("00010101")); +MQQ796:ROM64_INSTR_PT(796) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("00011101")); +MQQ797:ROM64_INSTR_PT(797) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("10011101")); +MQQ798:ROM64_INSTR_PT(798) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("110101")); +MQQ799:ROM64_INSTR_PT(799) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("10101")); +MQQ800:ROM64_INSTR_PT(800) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("11101")); +MQQ801:ROM64_INSTR_PT(801) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0000101")); +MQQ802:ROM64_INSTR_PT(802) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0000101")); +MQQ803:ROM64_INSTR_PT(803) <= + Eq(( ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("11101")); +MQQ804:ROM64_INSTR_PT(804) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("000100011")); +MQQ805:ROM64_INSTR_PT(805) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("01110011")); +MQQ806:ROM64_INSTR_PT(806) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("00000011")); +MQQ807:ROM64_INSTR_PT(807) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0000011")); +MQQ808:ROM64_INSTR_PT(808) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0000011")); +MQQ809:ROM64_INSTR_PT(809) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1010011")); +MQQ810:ROM64_INSTR_PT(810) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("010011")); +MQQ811:ROM64_INSTR_PT(811) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("01101011")); +MQQ812:ROM64_INSTR_PT(812) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("00001011")); +MQQ813:ROM64_INSTR_PT(813) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("01001011")); +MQQ814:ROM64_INSTR_PT(814) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("101011")); +MQQ815:ROM64_INSTR_PT(815) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("11011")); +MQQ816:ROM64_INSTR_PT(816) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("100111")); +MQQ817:ROM64_INSTR_PT(817) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("00010111")); +MQQ818:ROM64_INSTR_PT(818) <= + Eq(( ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("110111")); +MQQ819:ROM64_INSTR_PT(819) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1110111")); +MQQ820:ROM64_INSTR_PT(820) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("11010111")); +MQQ821:ROM64_INSTR_PT(821) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("000101111")); +MQQ822:ROM64_INSTR_PT(822) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("01101111")); +MQQ823:ROM64_INSTR_PT(823) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("111111")); +MQQ824:ROM64_INSTR_PT(824) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("111111")); +MQQ825:ROM64_INSTR_PT(825) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("11111")); +MQQ826:ROM64_INSTR_PT(826) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("111111")); +MQQ827:ROM64_INSTR_PT(827) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("101011")); +MQQ828:ROM64_INSTR_PT(828) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0110111")); +MQQ829:ROM64_INSTR_PT(829) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("110111")); +MQQ830:ROM64_INSTR_PT(830) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("11111")); +MQQ831:ROM64_INSTR_PT(831) <= + Eq(( ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("0111")); +MQQ832:ROM64_INSTR_PT(832) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("111111")); +MQQ833:ROM64_INSTR_PT(833) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("11111")); +MQQ834:ROM64_INSTR_PT(834) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("110001")); +MQQ835:ROM64_INSTR_PT(835) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1001101")); +MQQ836:ROM64_INSTR_PT(836) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("101101")); +MQQ837:ROM64_INSTR_PT(837) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("101011")); +MQQ838:ROM64_INSTR_PT(838) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1111011")); +MQQ839:ROM64_INSTR_PT(839) <= + Eq(( ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("011")); +MQQ840:ROM64_INSTR_PT(840) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0000111")); +MQQ841:ROM64_INSTR_PT(841) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1111111")); +MQQ842:ROM64_INSTR_PT(842) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("101111")); +MQQ843:ROM64_INSTR_PT(843) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("01111")); +MQQ844:ROM64_INSTR_PT(844) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("100011")); +MQQ845:ROM64_INSTR_PT(845) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("110111")); +MQQ846:ROM64_INSTR_PT(846) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("011111")); +MQQ847:ROM64_INSTR_PT(847) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("000101")); +MQQ848:ROM64_INSTR_PT(848) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("01101")); +MQQ849:ROM64_INSTR_PT(849) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("100011")); +MQQ850:ROM64_INSTR_PT(850) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("1111")); +MQQ851:ROM64_INSTR_PT(851) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("01001")); +MQQ852:ROM64_INSTR_PT(852) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("1001000")); +MQQ853:ROM64_INSTR_PT(853) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) + ) , STD_ULOGIC_VECTOR'("110000")); +MQQ854:ROM64_INSTR_PT(854) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) + ) , STD_ULOGIC_VECTOR'("00011100")); +MQQ855:ROM64_INSTR_PT(855) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) + ) , STD_ULOGIC_VECTOR'("00000010")); +MQQ856:ROM64_INSTR_PT(856) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("0100010")); +MQQ857:ROM64_INSTR_PT(857) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("0000010")); +MQQ858:ROM64_INSTR_PT(858) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) + ) , STD_ULOGIC_VECTOR'("101110")); +MQQ859:ROM64_INSTR_PT(859) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("1101110")); +MQQ860:ROM64_INSTR_PT(860) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) + ) , STD_ULOGIC_VECTOR'("000110")); +MQQ861:ROM64_INSTR_PT(861) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("1001100")); +MQQ862:ROM64_INSTR_PT(862) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) + ) , STD_ULOGIC_VECTOR'("1110")); +MQQ863:ROM64_INSTR_PT(863) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("010")); +MQQ864:ROM64_INSTR_PT(864) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("0100101")); +MQQ865:ROM64_INSTR_PT(865) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("1100101")); +MQQ866:ROM64_INSTR_PT(866) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("1001101")); +MQQ867:ROM64_INSTR_PT(867) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("1101101")); +MQQ868:ROM64_INSTR_PT(868) <= + Eq(( ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("01011")); +MQQ869:ROM64_INSTR_PT(869) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) + ) , STD_ULOGIC_VECTOR'("110111")); +MQQ870:ROM64_INSTR_PT(870) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("0011111")); +MQQ871:ROM64_INSTR_PT(871) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) + ) , STD_ULOGIC_VECTOR'("100111")); +MQQ872:ROM64_INSTR_PT(872) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("11111")); +MQQ873:ROM64_INSTR_PT(873) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) + ) , STD_ULOGIC_VECTOR'("110111")); +MQQ874:ROM64_INSTR_PT(874) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("11111")); +MQQ875:ROM64_INSTR_PT(875) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("01111")); +MQQ876:ROM64_INSTR_PT(876) <= + Eq(( ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("101")); +MQQ877:ROM64_INSTR_PT(877) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) + ) , STD_ULOGIC_VECTOR'("010001")); +MQQ878:ROM64_INSTR_PT(878) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("01111")); +MQQ879:ROM64_INSTR_PT(879) <= + Eq(( ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("111")); +MQQ880:ROM64_INSTR_PT(880) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) ) , STD_ULOGIC_VECTOR'("01110")); +MQQ881:ROM64_INSTR_PT(881) <= + Eq(( ROM_ADDR_L2(4) & ROM_ADDR_L2(6) + ) , STD_ULOGIC_VECTOR'("00")); +MQQ882:ROM64_INSTR_PT(882) <= + Eq(( ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) ) , STD_ULOGIC_VECTOR'("111")); +MQQ883:ROM64_INSTR_PT(883) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) + ) , STD_ULOGIC_VECTOR'("110111")); +MQQ884:ROM64_INSTR_PT(884) <= + Eq(( ROM_ADDR_L2(4) & ROM_ADDR_L2(5) + ) , STD_ULOGIC_VECTOR'("00")); +MQQ885:ROM64_INSTR_PT(885) <= + Eq(( ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) ) , STD_ULOGIC_VECTOR'("111")); +MQQ886:ROM64_INSTR_PT(886) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) ) , STD_ULOGIC_VECTOR'("111")); +MQQ887:ROM64_INSTR_PT(887) <= + Eq(( ROM_ADDR_L2(2) ) , STD_ULOGIC'('1')); +MQQ888:ROM64_INSTR_PT(888) <= + Eq(( ROM_ADDR_L2(1) ) , STD_ULOGIC'('1')); +MQQ889:ROM64_INSTR_PT(889) <= + Eq(( ROM_ADDR_L2(0) ) , STD_ULOGIC'('0')); +MQQ890:ROM64_INSTR_PT(890) <= + '1'; +MQQ891:TEMPLATE(0) <= + (ROM64_INSTR_PT(29) OR ROM64_INSTR_PT(35) + OR ROM64_INSTR_PT(45) OR ROM64_INSTR_PT(65) + OR ROM64_INSTR_PT(74) OR ROM64_INSTR_PT(84) + OR ROM64_INSTR_PT(112) OR ROM64_INSTR_PT(119) + OR ROM64_INSTR_PT(129) OR ROM64_INSTR_PT(134) + OR ROM64_INSTR_PT(143) OR ROM64_INSTR_PT(158) + OR ROM64_INSTR_PT(160) OR ROM64_INSTR_PT(176) + OR ROM64_INSTR_PT(177) OR ROM64_INSTR_PT(179) + OR ROM64_INSTR_PT(183) OR ROM64_INSTR_PT(221) + OR ROM64_INSTR_PT(225) OR ROM64_INSTR_PT(233) + OR ROM64_INSTR_PT(237) OR ROM64_INSTR_PT(242) + OR ROM64_INSTR_PT(259) OR ROM64_INSTR_PT(294) + OR ROM64_INSTR_PT(296) OR ROM64_INSTR_PT(311) + OR ROM64_INSTR_PT(339) OR ROM64_INSTR_PT(350) + OR ROM64_INSTR_PT(354) OR ROM64_INSTR_PT(355) + OR ROM64_INSTR_PT(358) OR ROM64_INSTR_PT(359) + OR ROM64_INSTR_PT(362) OR ROM64_INSTR_PT(367) + OR ROM64_INSTR_PT(368) OR ROM64_INSTR_PT(378) + OR ROM64_INSTR_PT(384) OR ROM64_INSTR_PT(389) + OR ROM64_INSTR_PT(392) OR ROM64_INSTR_PT(402) + OR ROM64_INSTR_PT(428) OR ROM64_INSTR_PT(435) + OR ROM64_INSTR_PT(470) OR ROM64_INSTR_PT(477) + OR ROM64_INSTR_PT(527) OR ROM64_INSTR_PT(557) + OR ROM64_INSTR_PT(564) OR ROM64_INSTR_PT(572) + OR ROM64_INSTR_PT(590) OR ROM64_INSTR_PT(602) + OR ROM64_INSTR_PT(610) OR ROM64_INSTR_PT(619) + OR ROM64_INSTR_PT(653) OR ROM64_INSTR_PT(657) + OR ROM64_INSTR_PT(664) OR ROM64_INSTR_PT(694) + OR ROM64_INSTR_PT(695) OR ROM64_INSTR_PT(702) + OR ROM64_INSTR_PT(716) OR ROM64_INSTR_PT(719) + OR ROM64_INSTR_PT(720) OR ROM64_INSTR_PT(721) + OR ROM64_INSTR_PT(736) OR ROM64_INSTR_PT(770) + OR ROM64_INSTR_PT(798) OR ROM64_INSTR_PT(832) + OR ROM64_INSTR_PT(834) OR ROM64_INSTR_PT(858) + OR ROM64_INSTR_PT(873)); +MQQ892:TEMPLATE(1) <= + (ROM64_INSTR_PT(2) OR ROM64_INSTR_PT(4) + OR ROM64_INSTR_PT(6) OR ROM64_INSTR_PT(8) + OR ROM64_INSTR_PT(9) OR ROM64_INSTR_PT(10) + OR ROM64_INSTR_PT(11) OR ROM64_INSTR_PT(14) + OR ROM64_INSTR_PT(15) OR ROM64_INSTR_PT(17) + OR ROM64_INSTR_PT(18) OR ROM64_INSTR_PT(21) + OR ROM64_INSTR_PT(22) OR ROM64_INSTR_PT(25) + OR ROM64_INSTR_PT(34) OR ROM64_INSTR_PT(36) + OR ROM64_INSTR_PT(38) OR ROM64_INSTR_PT(41) + OR ROM64_INSTR_PT(42) OR ROM64_INSTR_PT(43) + OR ROM64_INSTR_PT(49) OR ROM64_INSTR_PT(51) + OR ROM64_INSTR_PT(52) OR ROM64_INSTR_PT(53) + OR ROM64_INSTR_PT(55) OR ROM64_INSTR_PT(56) + OR ROM64_INSTR_PT(61) OR ROM64_INSTR_PT(64) + OR ROM64_INSTR_PT(68) OR ROM64_INSTR_PT(69) + OR ROM64_INSTR_PT(70) OR ROM64_INSTR_PT(71) + OR ROM64_INSTR_PT(73) OR ROM64_INSTR_PT(75) + OR ROM64_INSTR_PT(77) OR ROM64_INSTR_PT(78) + OR ROM64_INSTR_PT(82) OR ROM64_INSTR_PT(83) + OR ROM64_INSTR_PT(86) OR ROM64_INSTR_PT(89) + OR ROM64_INSTR_PT(90) OR ROM64_INSTR_PT(92) + OR ROM64_INSTR_PT(93) OR ROM64_INSTR_PT(95) + OR ROM64_INSTR_PT(96) OR ROM64_INSTR_PT(97) + OR ROM64_INSTR_PT(99) OR ROM64_INSTR_PT(100) + OR ROM64_INSTR_PT(101) OR ROM64_INSTR_PT(102) + OR ROM64_INSTR_PT(104) OR ROM64_INSTR_PT(105) + OR ROM64_INSTR_PT(106) OR ROM64_INSTR_PT(108) + OR ROM64_INSTR_PT(109) OR ROM64_INSTR_PT(110) + OR ROM64_INSTR_PT(113) OR ROM64_INSTR_PT(116) + OR ROM64_INSTR_PT(117) OR ROM64_INSTR_PT(118) + OR ROM64_INSTR_PT(124) OR ROM64_INSTR_PT(127) + OR ROM64_INSTR_PT(136) OR ROM64_INSTR_PT(137) + OR ROM64_INSTR_PT(140) OR ROM64_INSTR_PT(144) + OR ROM64_INSTR_PT(145) OR ROM64_INSTR_PT(148) + OR ROM64_INSTR_PT(153) OR ROM64_INSTR_PT(161) + OR ROM64_INSTR_PT(162) OR ROM64_INSTR_PT(164) + OR ROM64_INSTR_PT(169) OR ROM64_INSTR_PT(170) + OR ROM64_INSTR_PT(171) OR ROM64_INSTR_PT(172) + OR ROM64_INSTR_PT(173) OR ROM64_INSTR_PT(175) + OR ROM64_INSTR_PT(180) OR ROM64_INSTR_PT(184) + OR ROM64_INSTR_PT(185) OR ROM64_INSTR_PT(186) + OR ROM64_INSTR_PT(188) OR ROM64_INSTR_PT(193) + OR ROM64_INSTR_PT(195) OR ROM64_INSTR_PT(196) + OR ROM64_INSTR_PT(199) OR ROM64_INSTR_PT(201) + OR ROM64_INSTR_PT(202) OR ROM64_INSTR_PT(203) + OR ROM64_INSTR_PT(205) OR ROM64_INSTR_PT(206) + OR ROM64_INSTR_PT(208) OR ROM64_INSTR_PT(214) + OR ROM64_INSTR_PT(215) OR ROM64_INSTR_PT(216) + OR ROM64_INSTR_PT(217) OR ROM64_INSTR_PT(218) + OR ROM64_INSTR_PT(222) OR ROM64_INSTR_PT(223) + OR ROM64_INSTR_PT(226) OR ROM64_INSTR_PT(229) + OR ROM64_INSTR_PT(230) OR ROM64_INSTR_PT(238) + OR ROM64_INSTR_PT(241) OR ROM64_INSTR_PT(243) + OR ROM64_INSTR_PT(244) OR ROM64_INSTR_PT(252) + OR ROM64_INSTR_PT(254) OR ROM64_INSTR_PT(257) + OR ROM64_INSTR_PT(258) OR ROM64_INSTR_PT(260) + OR ROM64_INSTR_PT(261) OR ROM64_INSTR_PT(263) + OR ROM64_INSTR_PT(264) OR ROM64_INSTR_PT(265) + OR ROM64_INSTR_PT(268) OR ROM64_INSTR_PT(269) + OR ROM64_INSTR_PT(270) OR ROM64_INSTR_PT(271) + OR ROM64_INSTR_PT(273) OR ROM64_INSTR_PT(275) + OR ROM64_INSTR_PT(276) OR ROM64_INSTR_PT(277) + OR ROM64_INSTR_PT(280) OR ROM64_INSTR_PT(282) + OR ROM64_INSTR_PT(284) OR ROM64_INSTR_PT(285) + OR ROM64_INSTR_PT(286) OR ROM64_INSTR_PT(287) + OR ROM64_INSTR_PT(292) OR ROM64_INSTR_PT(293) + OR ROM64_INSTR_PT(297) OR ROM64_INSTR_PT(298) + OR ROM64_INSTR_PT(299) OR ROM64_INSTR_PT(302) + OR ROM64_INSTR_PT(305) OR ROM64_INSTR_PT(308) + OR ROM64_INSTR_PT(315) OR ROM64_INSTR_PT(322) + OR ROM64_INSTR_PT(325) OR ROM64_INSTR_PT(331) + OR ROM64_INSTR_PT(333) OR ROM64_INSTR_PT(345) + OR ROM64_INSTR_PT(349) OR ROM64_INSTR_PT(351) + OR ROM64_INSTR_PT(357) OR ROM64_INSTR_PT(364) + OR ROM64_INSTR_PT(365) OR ROM64_INSTR_PT(366) + OR ROM64_INSTR_PT(369) OR ROM64_INSTR_PT(371) + OR ROM64_INSTR_PT(372) OR ROM64_INSTR_PT(375) + OR ROM64_INSTR_PT(377) OR ROM64_INSTR_PT(379) + OR ROM64_INSTR_PT(381) OR ROM64_INSTR_PT(383) + OR ROM64_INSTR_PT(385) OR ROM64_INSTR_PT(388) + OR ROM64_INSTR_PT(391) OR ROM64_INSTR_PT(394) + OR ROM64_INSTR_PT(395) OR ROM64_INSTR_PT(397) + OR ROM64_INSTR_PT(403) OR ROM64_INSTR_PT(404) + OR ROM64_INSTR_PT(405) OR ROM64_INSTR_PT(408) + OR ROM64_INSTR_PT(409) OR ROM64_INSTR_PT(410) + OR ROM64_INSTR_PT(413) OR ROM64_INSTR_PT(414) + OR ROM64_INSTR_PT(415) OR ROM64_INSTR_PT(418) + OR ROM64_INSTR_PT(419) OR ROM64_INSTR_PT(420) + OR ROM64_INSTR_PT(422) OR ROM64_INSTR_PT(424) + OR ROM64_INSTR_PT(425) OR ROM64_INSTR_PT(426) + OR ROM64_INSTR_PT(427) OR ROM64_INSTR_PT(429) + OR ROM64_INSTR_PT(430) OR ROM64_INSTR_PT(432) + OR ROM64_INSTR_PT(433) OR ROM64_INSTR_PT(434) + OR ROM64_INSTR_PT(437) OR ROM64_INSTR_PT(438) + OR ROM64_INSTR_PT(439) OR ROM64_INSTR_PT(440) + OR ROM64_INSTR_PT(443) OR ROM64_INSTR_PT(445) + OR ROM64_INSTR_PT(446) OR ROM64_INSTR_PT(451) + OR ROM64_INSTR_PT(453) OR ROM64_INSTR_PT(454) + OR ROM64_INSTR_PT(455) OR ROM64_INSTR_PT(456) + OR ROM64_INSTR_PT(457) OR ROM64_INSTR_PT(458) + OR ROM64_INSTR_PT(460) OR ROM64_INSTR_PT(463) + OR ROM64_INSTR_PT(466) OR ROM64_INSTR_PT(467) + OR ROM64_INSTR_PT(473) OR ROM64_INSTR_PT(475) + OR ROM64_INSTR_PT(478) OR ROM64_INSTR_PT(480) + OR ROM64_INSTR_PT(481) OR ROM64_INSTR_PT(482) + OR ROM64_INSTR_PT(483) OR ROM64_INSTR_PT(484) + OR ROM64_INSTR_PT(485) OR ROM64_INSTR_PT(490) + OR ROM64_INSTR_PT(493) OR ROM64_INSTR_PT(495) + OR ROM64_INSTR_PT(497) OR ROM64_INSTR_PT(498) + OR ROM64_INSTR_PT(499) OR ROM64_INSTR_PT(503) + OR ROM64_INSTR_PT(504) OR ROM64_INSTR_PT(505) + OR ROM64_INSTR_PT(506) OR ROM64_INSTR_PT(508) + OR ROM64_INSTR_PT(509) OR ROM64_INSTR_PT(510) + OR ROM64_INSTR_PT(511) OR ROM64_INSTR_PT(512) + OR ROM64_INSTR_PT(514) OR ROM64_INSTR_PT(519) + OR ROM64_INSTR_PT(521) OR ROM64_INSTR_PT(522) + OR ROM64_INSTR_PT(523) OR ROM64_INSTR_PT(525) + OR ROM64_INSTR_PT(530) OR ROM64_INSTR_PT(531) + OR ROM64_INSTR_PT(532) OR ROM64_INSTR_PT(534) + OR ROM64_INSTR_PT(535) OR ROM64_INSTR_PT(536) + OR ROM64_INSTR_PT(537) OR ROM64_INSTR_PT(539) + OR ROM64_INSTR_PT(540) OR ROM64_INSTR_PT(542) + OR ROM64_INSTR_PT(544) OR ROM64_INSTR_PT(545) + OR ROM64_INSTR_PT(546) OR ROM64_INSTR_PT(548) + OR ROM64_INSTR_PT(549) OR ROM64_INSTR_PT(552) + OR ROM64_INSTR_PT(553) OR ROM64_INSTR_PT(554) + OR ROM64_INSTR_PT(555) OR ROM64_INSTR_PT(558) + OR ROM64_INSTR_PT(559) OR ROM64_INSTR_PT(563) + OR ROM64_INSTR_PT(566) OR ROM64_INSTR_PT(568) + OR ROM64_INSTR_PT(569) OR ROM64_INSTR_PT(570) + OR ROM64_INSTR_PT(571) OR ROM64_INSTR_PT(575) + OR ROM64_INSTR_PT(576) OR ROM64_INSTR_PT(577) + OR ROM64_INSTR_PT(579) OR ROM64_INSTR_PT(580) + OR ROM64_INSTR_PT(581) OR ROM64_INSTR_PT(582) + OR ROM64_INSTR_PT(583) OR ROM64_INSTR_PT(584) + OR ROM64_INSTR_PT(586) OR ROM64_INSTR_PT(588) + OR ROM64_INSTR_PT(589) OR ROM64_INSTR_PT(591) + OR ROM64_INSTR_PT(592) OR ROM64_INSTR_PT(593) + OR ROM64_INSTR_PT(595) OR ROM64_INSTR_PT(596) + OR ROM64_INSTR_PT(598) OR ROM64_INSTR_PT(599) + OR ROM64_INSTR_PT(600) OR ROM64_INSTR_PT(603) + OR ROM64_INSTR_PT(604) OR ROM64_INSTR_PT(606) + OR ROM64_INSTR_PT(607) OR ROM64_INSTR_PT(608) + OR ROM64_INSTR_PT(611) OR ROM64_INSTR_PT(612) + OR ROM64_INSTR_PT(613) OR ROM64_INSTR_PT(614) + OR ROM64_INSTR_PT(615) OR ROM64_INSTR_PT(616) + OR ROM64_INSTR_PT(617) OR ROM64_INSTR_PT(618) + OR ROM64_INSTR_PT(623) OR ROM64_INSTR_PT(626) + OR ROM64_INSTR_PT(627) OR ROM64_INSTR_PT(628) + OR ROM64_INSTR_PT(629) OR ROM64_INSTR_PT(633) + OR ROM64_INSTR_PT(637) OR ROM64_INSTR_PT(639) + OR ROM64_INSTR_PT(642) OR ROM64_INSTR_PT(643) + OR ROM64_INSTR_PT(644) OR ROM64_INSTR_PT(646) + OR ROM64_INSTR_PT(655) OR ROM64_INSTR_PT(660) + OR ROM64_INSTR_PT(663) OR ROM64_INSTR_PT(666) + OR ROM64_INSTR_PT(678) OR ROM64_INSTR_PT(679) + OR ROM64_INSTR_PT(681) OR ROM64_INSTR_PT(682) + OR ROM64_INSTR_PT(687) OR ROM64_INSTR_PT(703) + OR ROM64_INSTR_PT(713) OR ROM64_INSTR_PT(717) + OR ROM64_INSTR_PT(722) OR ROM64_INSTR_PT(731) + OR ROM64_INSTR_PT(741) OR ROM64_INSTR_PT(744) + OR ROM64_INSTR_PT(753) OR ROM64_INSTR_PT(761) + OR ROM64_INSTR_PT(769) OR ROM64_INSTR_PT(776) + OR ROM64_INSTR_PT(791) OR ROM64_INSTR_PT(801) + OR ROM64_INSTR_PT(808) OR ROM64_INSTR_PT(811) + OR ROM64_INSTR_PT(813) OR ROM64_INSTR_PT(822) + OR ROM64_INSTR_PT(824) OR ROM64_INSTR_PT(846) + OR ROM64_INSTR_PT(849) OR ROM64_INSTR_PT(852) + OR ROM64_INSTR_PT(854) OR ROM64_INSTR_PT(855) + OR ROM64_INSTR_PT(856) OR ROM64_INSTR_PT(864) + OR ROM64_INSTR_PT(869) OR ROM64_INSTR_PT(870) + OR ROM64_INSTR_PT(872) OR ROM64_INSTR_PT(886) + ); +MQQ893:TEMPLATE(2) <= + (ROM64_INSTR_PT(2) OR ROM64_INSTR_PT(5) + OR ROM64_INSTR_PT(6) OR ROM64_INSTR_PT(10) + OR ROM64_INSTR_PT(14) OR ROM64_INSTR_PT(15) + OR ROM64_INSTR_PT(18) OR ROM64_INSTR_PT(20) + OR ROM64_INSTR_PT(25) OR ROM64_INSTR_PT(28) + OR ROM64_INSTR_PT(33) OR ROM64_INSTR_PT(36) + OR ROM64_INSTR_PT(39) OR ROM64_INSTR_PT(41) + OR ROM64_INSTR_PT(42) OR ROM64_INSTR_PT(43) + OR ROM64_INSTR_PT(53) OR ROM64_INSTR_PT(56) + OR ROM64_INSTR_PT(60) OR ROM64_INSTR_PT(66) + OR ROM64_INSTR_PT(69) OR ROM64_INSTR_PT(73) + OR ROM64_INSTR_PT(77) OR ROM64_INSTR_PT(78) + OR ROM64_INSTR_PT(79) OR ROM64_INSTR_PT(82) + OR ROM64_INSTR_PT(89) OR ROM64_INSTR_PT(92) + OR ROM64_INSTR_PT(95) OR ROM64_INSTR_PT(96) + OR ROM64_INSTR_PT(97) OR ROM64_INSTR_PT(98) + OR ROM64_INSTR_PT(101) OR ROM64_INSTR_PT(104) + OR ROM64_INSTR_PT(106) OR ROM64_INSTR_PT(108) + OR ROM64_INSTR_PT(109) OR ROM64_INSTR_PT(110) + OR ROM64_INSTR_PT(116) OR ROM64_INSTR_PT(124) + OR ROM64_INSTR_PT(140) OR ROM64_INSTR_PT(142) + OR ROM64_INSTR_PT(145) OR ROM64_INSTR_PT(146) + OR ROM64_INSTR_PT(147) OR ROM64_INSTR_PT(150) + OR ROM64_INSTR_PT(151) OR ROM64_INSTR_PT(153) + OR ROM64_INSTR_PT(161) OR ROM64_INSTR_PT(166) + OR ROM64_INSTR_PT(168) OR ROM64_INSTR_PT(172) + OR ROM64_INSTR_PT(173) OR ROM64_INSTR_PT(174) + OR ROM64_INSTR_PT(175) OR ROM64_INSTR_PT(184) + OR ROM64_INSTR_PT(187) OR ROM64_INSTR_PT(188) + OR ROM64_INSTR_PT(190) OR ROM64_INSTR_PT(191) + OR ROM64_INSTR_PT(193) OR ROM64_INSTR_PT(195) + OR ROM64_INSTR_PT(202) OR ROM64_INSTR_PT(203) + OR ROM64_INSTR_PT(205) OR ROM64_INSTR_PT(206) + OR ROM64_INSTR_PT(207) OR ROM64_INSTR_PT(208) + OR ROM64_INSTR_PT(209) OR ROM64_INSTR_PT(216) + OR ROM64_INSTR_PT(219) OR ROM64_INSTR_PT(228) + OR ROM64_INSTR_PT(229) OR ROM64_INSTR_PT(230) + OR ROM64_INSTR_PT(231) OR ROM64_INSTR_PT(240) + OR ROM64_INSTR_PT(243) OR ROM64_INSTR_PT(247) + OR ROM64_INSTR_PT(253) OR ROM64_INSTR_PT(254) + OR ROM64_INSTR_PT(257) OR ROM64_INSTR_PT(258) + OR ROM64_INSTR_PT(260) OR ROM64_INSTR_PT(261) + OR ROM64_INSTR_PT(265) OR ROM64_INSTR_PT(269) + OR ROM64_INSTR_PT(273) OR ROM64_INSTR_PT(277) + OR ROM64_INSTR_PT(281) OR ROM64_INSTR_PT(284) + OR ROM64_INSTR_PT(288) OR ROM64_INSTR_PT(292) + OR ROM64_INSTR_PT(295) OR ROM64_INSTR_PT(304) + OR ROM64_INSTR_PT(307) OR ROM64_INSTR_PT(309) + OR ROM64_INSTR_PT(313) OR ROM64_INSTR_PT(324) + OR ROM64_INSTR_PT(325) OR ROM64_INSTR_PT(327) + OR ROM64_INSTR_PT(332) OR ROM64_INSTR_PT(333) + OR ROM64_INSTR_PT(334) OR ROM64_INSTR_PT(340) + OR ROM64_INSTR_PT(341) OR ROM64_INSTR_PT(342) + OR ROM64_INSTR_PT(345) OR ROM64_INSTR_PT(351) + OR ROM64_INSTR_PT(352) OR ROM64_INSTR_PT(357) + OR ROM64_INSTR_PT(361) OR ROM64_INSTR_PT(365) + OR ROM64_INSTR_PT(366) OR ROM64_INSTR_PT(369) + OR ROM64_INSTR_PT(371) OR ROM64_INSTR_PT(372) + OR ROM64_INSTR_PT(374) OR ROM64_INSTR_PT(377) + OR ROM64_INSTR_PT(379) OR ROM64_INSTR_PT(381) + OR ROM64_INSTR_PT(388) OR ROM64_INSTR_PT(394) + OR ROM64_INSTR_PT(395) OR ROM64_INSTR_PT(396) + OR ROM64_INSTR_PT(401) OR ROM64_INSTR_PT(403) + OR ROM64_INSTR_PT(405) OR ROM64_INSTR_PT(406) + OR ROM64_INSTR_PT(408) OR ROM64_INSTR_PT(409) + OR ROM64_INSTR_PT(413) OR ROM64_INSTR_PT(418) + OR ROM64_INSTR_PT(419) OR ROM64_INSTR_PT(420) + OR ROM64_INSTR_PT(422) OR ROM64_INSTR_PT(425) + OR ROM64_INSTR_PT(426) OR ROM64_INSTR_PT(429) + OR ROM64_INSTR_PT(430) OR ROM64_INSTR_PT(438) + OR ROM64_INSTR_PT(439) OR ROM64_INSTR_PT(440) + OR ROM64_INSTR_PT(443) OR ROM64_INSTR_PT(445) + OR ROM64_INSTR_PT(446) OR ROM64_INSTR_PT(448) + OR ROM64_INSTR_PT(451) OR ROM64_INSTR_PT(453) + OR ROM64_INSTR_PT(454) OR ROM64_INSTR_PT(455) + OR ROM64_INSTR_PT(456) OR ROM64_INSTR_PT(458) + OR ROM64_INSTR_PT(460) OR ROM64_INSTR_PT(463) + OR ROM64_INSTR_PT(464) OR ROM64_INSTR_PT(466) + OR ROM64_INSTR_PT(467) OR ROM64_INSTR_PT(468) + OR ROM64_INSTR_PT(471) OR ROM64_INSTR_PT(472) + OR ROM64_INSTR_PT(473) OR ROM64_INSTR_PT(474) + OR ROM64_INSTR_PT(475) OR ROM64_INSTR_PT(483) + OR ROM64_INSTR_PT(490) OR ROM64_INSTR_PT(491) + OR ROM64_INSTR_PT(497) OR ROM64_INSTR_PT(498) + OR ROM64_INSTR_PT(499) OR ROM64_INSTR_PT(503) + OR ROM64_INSTR_PT(506) OR ROM64_INSTR_PT(508) + OR ROM64_INSTR_PT(510) OR ROM64_INSTR_PT(514) + OR ROM64_INSTR_PT(516) OR ROM64_INSTR_PT(519) + OR ROM64_INSTR_PT(532) OR ROM64_INSTR_PT(538) + OR ROM64_INSTR_PT(542) OR ROM64_INSTR_PT(546) + OR ROM64_INSTR_PT(549) OR ROM64_INSTR_PT(551) + OR ROM64_INSTR_PT(553) OR ROM64_INSTR_PT(554) + OR ROM64_INSTR_PT(559) OR ROM64_INSTR_PT(562) + OR ROM64_INSTR_PT(566) OR ROM64_INSTR_PT(570) + OR ROM64_INSTR_PT(571) OR ROM64_INSTR_PT(575) + OR ROM64_INSTR_PT(580) OR ROM64_INSTR_PT(581) + OR ROM64_INSTR_PT(586) OR ROM64_INSTR_PT(589) + OR ROM64_INSTR_PT(593) OR ROM64_INSTR_PT(596) + OR ROM64_INSTR_PT(597) OR ROM64_INSTR_PT(598) + OR ROM64_INSTR_PT(601) OR ROM64_INSTR_PT(603) + OR ROM64_INSTR_PT(604) OR ROM64_INSTR_PT(606) + OR ROM64_INSTR_PT(611) OR ROM64_INSTR_PT(612) + OR ROM64_INSTR_PT(613) OR ROM64_INSTR_PT(614) + OR ROM64_INSTR_PT(615) OR ROM64_INSTR_PT(616) + OR ROM64_INSTR_PT(617) OR ROM64_INSTR_PT(620) + OR ROM64_INSTR_PT(626) OR ROM64_INSTR_PT(627) + OR ROM64_INSTR_PT(628) OR ROM64_INSTR_PT(632) + OR ROM64_INSTR_PT(635) OR ROM64_INSTR_PT(654) + OR ROM64_INSTR_PT(659) OR ROM64_INSTR_PT(660) + OR ROM64_INSTR_PT(663) OR ROM64_INSTR_PT(668) + OR ROM64_INSTR_PT(675) OR ROM64_INSTR_PT(679) + OR ROM64_INSTR_PT(681) OR ROM64_INSTR_PT(682) + OR ROM64_INSTR_PT(687) OR ROM64_INSTR_PT(691) + OR ROM64_INSTR_PT(703) OR ROM64_INSTR_PT(709) + OR ROM64_INSTR_PT(711) OR ROM64_INSTR_PT(713) + OR ROM64_INSTR_PT(717) OR ROM64_INSTR_PT(723) + OR ROM64_INSTR_PT(724) OR ROM64_INSTR_PT(728) + OR ROM64_INSTR_PT(733) OR ROM64_INSTR_PT(735) + OR ROM64_INSTR_PT(738) OR ROM64_INSTR_PT(741) + OR ROM64_INSTR_PT(759) OR ROM64_INSTR_PT(766) + OR ROM64_INSTR_PT(781) OR ROM64_INSTR_PT(791) + OR ROM64_INSTR_PT(794) OR ROM64_INSTR_PT(797) + OR ROM64_INSTR_PT(801) OR ROM64_INSTR_PT(808) + OR ROM64_INSTR_PT(809) OR ROM64_INSTR_PT(811) + OR ROM64_INSTR_PT(813) OR ROM64_INSTR_PT(822) + OR ROM64_INSTR_PT(824) OR ROM64_INSTR_PT(846) + OR ROM64_INSTR_PT(849) OR ROM64_INSTR_PT(852) + OR ROM64_INSTR_PT(854) OR ROM64_INSTR_PT(855) + OR ROM64_INSTR_PT(869) OR ROM64_INSTR_PT(872) + OR ROM64_INSTR_PT(883) OR ROM64_INSTR_PT(886) + ); +MQQ894:TEMPLATE(3) <= + (ROM64_INSTR_PT(2) OR ROM64_INSTR_PT(5) + OR ROM64_INSTR_PT(6) OR ROM64_INSTR_PT(9) + OR ROM64_INSTR_PT(10) OR ROM64_INSTR_PT(11) + OR ROM64_INSTR_PT(14) OR ROM64_INSTR_PT(15) + OR ROM64_INSTR_PT(17) OR ROM64_INSTR_PT(18) + OR ROM64_INSTR_PT(20) OR ROM64_INSTR_PT(21) + OR ROM64_INSTR_PT(22) OR ROM64_INSTR_PT(25) + OR ROM64_INSTR_PT(28) OR ROM64_INSTR_PT(29) + OR ROM64_INSTR_PT(33) OR ROM64_INSTR_PT(34) + OR ROM64_INSTR_PT(35) OR ROM64_INSTR_PT(36) + OR ROM64_INSTR_PT(38) OR ROM64_INSTR_PT(39) + OR ROM64_INSTR_PT(41) OR ROM64_INSTR_PT(42) + OR ROM64_INSTR_PT(43) OR ROM64_INSTR_PT(45) + OR ROM64_INSTR_PT(49) OR ROM64_INSTR_PT(52) + OR ROM64_INSTR_PT(53) OR ROM64_INSTR_PT(56) + OR ROM64_INSTR_PT(60) OR ROM64_INSTR_PT(61) + OR ROM64_INSTR_PT(64) OR ROM64_INSTR_PT(66) + OR ROM64_INSTR_PT(69) OR ROM64_INSTR_PT(70) + OR ROM64_INSTR_PT(71) OR ROM64_INSTR_PT(73) + OR ROM64_INSTR_PT(75) OR ROM64_INSTR_PT(76) + OR ROM64_INSTR_PT(77) OR ROM64_INSTR_PT(78) + OR ROM64_INSTR_PT(80) OR ROM64_INSTR_PT(82) + OR ROM64_INSTR_PT(83) OR ROM64_INSTR_PT(84) + OR ROM64_INSTR_PT(86) OR ROM64_INSTR_PT(89) + OR ROM64_INSTR_PT(90) OR ROM64_INSTR_PT(92) + OR ROM64_INSTR_PT(93) OR ROM64_INSTR_PT(95) + OR ROM64_INSTR_PT(96) OR ROM64_INSTR_PT(97) + OR ROM64_INSTR_PT(98) OR ROM64_INSTR_PT(99) + OR ROM64_INSTR_PT(101) OR ROM64_INSTR_PT(102) + OR ROM64_INSTR_PT(104) OR ROM64_INSTR_PT(106) + OR ROM64_INSTR_PT(108) OR ROM64_INSTR_PT(109) + OR ROM64_INSTR_PT(110) OR ROM64_INSTR_PT(113) + OR ROM64_INSTR_PT(114) OR ROM64_INSTR_PT(115) + OR ROM64_INSTR_PT(116) OR ROM64_INSTR_PT(117) + OR ROM64_INSTR_PT(118) OR ROM64_INSTR_PT(124) + OR ROM64_INSTR_PT(127) OR ROM64_INSTR_PT(133) + OR ROM64_INSTR_PT(136) OR ROM64_INSTR_PT(140) + OR ROM64_INSTR_PT(142) OR ROM64_INSTR_PT(144) + OR ROM64_INSTR_PT(145) OR ROM64_INSTR_PT(146) + OR ROM64_INSTR_PT(147) OR ROM64_INSTR_PT(148) + OR ROM64_INSTR_PT(150) OR ROM64_INSTR_PT(151) + OR ROM64_INSTR_PT(153) OR ROM64_INSTR_PT(155) + OR ROM64_INSTR_PT(160) OR ROM64_INSTR_PT(161) + OR ROM64_INSTR_PT(164) OR ROM64_INSTR_PT(166) + OR ROM64_INSTR_PT(168) OR ROM64_INSTR_PT(169) + OR ROM64_INSTR_PT(171) OR ROM64_INSTR_PT(172) + OR ROM64_INSTR_PT(173) OR ROM64_INSTR_PT(174) + OR ROM64_INSTR_PT(175) OR ROM64_INSTR_PT(177) + OR ROM64_INSTR_PT(179) OR ROM64_INSTR_PT(180) + OR ROM64_INSTR_PT(181) OR ROM64_INSTR_PT(182) + OR ROM64_INSTR_PT(183) OR ROM64_INSTR_PT(184) + OR ROM64_INSTR_PT(186) OR ROM64_INSTR_PT(187) + OR ROM64_INSTR_PT(188) OR ROM64_INSTR_PT(191) + OR ROM64_INSTR_PT(194) OR ROM64_INSTR_PT(199) + OR ROM64_INSTR_PT(201) OR ROM64_INSTR_PT(202) + OR ROM64_INSTR_PT(203) OR ROM64_INSTR_PT(205) + OR ROM64_INSTR_PT(206) OR ROM64_INSTR_PT(207) + OR ROM64_INSTR_PT(208) OR ROM64_INSTR_PT(209) + OR ROM64_INSTR_PT(211) OR ROM64_INSTR_PT(215) + OR ROM64_INSTR_PT(216) OR ROM64_INSTR_PT(217) + OR ROM64_INSTR_PT(218) OR ROM64_INSTR_PT(219) + OR ROM64_INSTR_PT(221) OR ROM64_INSTR_PT(222) + OR ROM64_INSTR_PT(223) OR ROM64_INSTR_PT(225) + OR ROM64_INSTR_PT(226) OR ROM64_INSTR_PT(228) + OR ROM64_INSTR_PT(229) OR ROM64_INSTR_PT(230) + OR ROM64_INSTR_PT(231) OR ROM64_INSTR_PT(233) + OR ROM64_INSTR_PT(238) OR ROM64_INSTR_PT(240) + OR ROM64_INSTR_PT(242) OR ROM64_INSTR_PT(243) + OR ROM64_INSTR_PT(245) OR ROM64_INSTR_PT(247) + OR ROM64_INSTR_PT(249) OR ROM64_INSTR_PT(252) + OR ROM64_INSTR_PT(253) OR ROM64_INSTR_PT(254) + OR ROM64_INSTR_PT(257) OR ROM64_INSTR_PT(258) + OR ROM64_INSTR_PT(259) OR ROM64_INSTR_PT(260) + OR ROM64_INSTR_PT(261) OR ROM64_INSTR_PT(264) + OR ROM64_INSTR_PT(265) OR ROM64_INSTR_PT(268) + OR ROM64_INSTR_PT(269) OR ROM64_INSTR_PT(270) + OR ROM64_INSTR_PT(271) OR ROM64_INSTR_PT(272) + OR ROM64_INSTR_PT(273) OR ROM64_INSTR_PT(274) + OR ROM64_INSTR_PT(275) OR ROM64_INSTR_PT(277) + OR ROM64_INSTR_PT(280) OR ROM64_INSTR_PT(281) + OR ROM64_INSTR_PT(282) OR ROM64_INSTR_PT(284) + OR ROM64_INSTR_PT(287) OR ROM64_INSTR_PT(288) + OR ROM64_INSTR_PT(290) OR ROM64_INSTR_PT(293) + OR ROM64_INSTR_PT(294) OR ROM64_INSTR_PT(295) + OR ROM64_INSTR_PT(298) OR ROM64_INSTR_PT(299) + OR ROM64_INSTR_PT(302) OR ROM64_INSTR_PT(304) + OR ROM64_INSTR_PT(305) OR ROM64_INSTR_PT(307) + OR ROM64_INSTR_PT(309) OR ROM64_INSTR_PT(311) + OR ROM64_INSTR_PT(313) OR ROM64_INSTR_PT(315) + OR ROM64_INSTR_PT(319) OR ROM64_INSTR_PT(324) + OR ROM64_INSTR_PT(325) OR ROM64_INSTR_PT(327) + OR ROM64_INSTR_PT(331) OR ROM64_INSTR_PT(332) + OR ROM64_INSTR_PT(334) OR ROM64_INSTR_PT(339) + OR ROM64_INSTR_PT(340) OR ROM64_INSTR_PT(341) + OR ROM64_INSTR_PT(342) OR ROM64_INSTR_PT(348) + OR ROM64_INSTR_PT(350) OR ROM64_INSTR_PT(352) + OR ROM64_INSTR_PT(353) OR ROM64_INSTR_PT(359) + OR ROM64_INSTR_PT(361) OR ROM64_INSTR_PT(364) + OR ROM64_INSTR_PT(365) OR ROM64_INSTR_PT(366) + OR ROM64_INSTR_PT(369) OR ROM64_INSTR_PT(371) + OR ROM64_INSTR_PT(372) OR ROM64_INSTR_PT(374) + OR ROM64_INSTR_PT(375) OR ROM64_INSTR_PT(378) + OR ROM64_INSTR_PT(379) OR ROM64_INSTR_PT(381) + OR ROM64_INSTR_PT(383) OR ROM64_INSTR_PT(384) + OR ROM64_INSTR_PT(385) OR ROM64_INSTR_PT(388) + OR ROM64_INSTR_PT(389) OR ROM64_INSTR_PT(391) + OR ROM64_INSTR_PT(394) OR ROM64_INSTR_PT(395) + OR ROM64_INSTR_PT(396) OR ROM64_INSTR_PT(397) + OR ROM64_INSTR_PT(401) OR ROM64_INSTR_PT(403) + OR ROM64_INSTR_PT(404) OR ROM64_INSTR_PT(405) + OR ROM64_INSTR_PT(406) OR ROM64_INSTR_PT(408) + OR ROM64_INSTR_PT(409) OR ROM64_INSTR_PT(410) + OR ROM64_INSTR_PT(413) OR ROM64_INSTR_PT(414) + OR ROM64_INSTR_PT(415) OR ROM64_INSTR_PT(418) + OR ROM64_INSTR_PT(419) OR ROM64_INSTR_PT(420) + OR ROM64_INSTR_PT(422) OR ROM64_INSTR_PT(424) + OR ROM64_INSTR_PT(425) OR ROM64_INSTR_PT(426) + OR ROM64_INSTR_PT(427) OR ROM64_INSTR_PT(428) + OR ROM64_INSTR_PT(429) OR ROM64_INSTR_PT(430) + OR ROM64_INSTR_PT(437) OR ROM64_INSTR_PT(438) + OR ROM64_INSTR_PT(439) OR ROM64_INSTR_PT(440) + OR ROM64_INSTR_PT(441) OR ROM64_INSTR_PT(443) + OR ROM64_INSTR_PT(445) OR ROM64_INSTR_PT(446) + OR ROM64_INSTR_PT(448) OR ROM64_INSTR_PT(451) + OR ROM64_INSTR_PT(453) OR ROM64_INSTR_PT(454) + OR ROM64_INSTR_PT(455) OR ROM64_INSTR_PT(456) + OR ROM64_INSTR_PT(457) OR ROM64_INSTR_PT(458) + OR ROM64_INSTR_PT(460) OR ROM64_INSTR_PT(463) + OR ROM64_INSTR_PT(464) OR ROM64_INSTR_PT(466) + OR ROM64_INSTR_PT(467) OR ROM64_INSTR_PT(468) + OR ROM64_INSTR_PT(470) OR ROM64_INSTR_PT(471) + OR ROM64_INSTR_PT(472) OR ROM64_INSTR_PT(473) + OR ROM64_INSTR_PT(474) OR ROM64_INSTR_PT(475) + OR ROM64_INSTR_PT(478) OR ROM64_INSTR_PT(481) + OR ROM64_INSTR_PT(482) OR ROM64_INSTR_PT(483) + OR ROM64_INSTR_PT(484) OR ROM64_INSTR_PT(485) + OR ROM64_INSTR_PT(488) OR ROM64_INSTR_PT(490) + OR ROM64_INSTR_PT(491) OR ROM64_INSTR_PT(493) + OR ROM64_INSTR_PT(495) OR ROM64_INSTR_PT(497) + OR ROM64_INSTR_PT(498) OR ROM64_INSTR_PT(503) + OR ROM64_INSTR_PT(505) OR ROM64_INSTR_PT(506) + OR ROM64_INSTR_PT(508) OR ROM64_INSTR_PT(509) + OR ROM64_INSTR_PT(510) OR ROM64_INSTR_PT(511) + OR ROM64_INSTR_PT(516) OR ROM64_INSTR_PT(517) + OR ROM64_INSTR_PT(519) OR ROM64_INSTR_PT(520) + OR ROM64_INSTR_PT(521) OR ROM64_INSTR_PT(522) + OR ROM64_INSTR_PT(523) OR ROM64_INSTR_PT(525) + OR ROM64_INSTR_PT(532) OR ROM64_INSTR_PT(534) + OR ROM64_INSTR_PT(538) OR ROM64_INSTR_PT(542) + OR ROM64_INSTR_PT(546) OR ROM64_INSTR_PT(549) + OR ROM64_INSTR_PT(551) OR ROM64_INSTR_PT(552) + OR ROM64_INSTR_PT(553) OR ROM64_INSTR_PT(554) + OR ROM64_INSTR_PT(555) OR ROM64_INSTR_PT(558) + OR ROM64_INSTR_PT(559) OR ROM64_INSTR_PT(562) + OR ROM64_INSTR_PT(563) OR ROM64_INSTR_PT(564) + OR ROM64_INSTR_PT(566) OR ROM64_INSTR_PT(569) + OR ROM64_INSTR_PT(570) OR ROM64_INSTR_PT(571) + OR ROM64_INSTR_PT(572) OR ROM64_INSTR_PT(575) + OR ROM64_INSTR_PT(576) OR ROM64_INSTR_PT(579) + OR ROM64_INSTR_PT(580) OR ROM64_INSTR_PT(581) + OR ROM64_INSTR_PT(582) OR ROM64_INSTR_PT(583) + OR ROM64_INSTR_PT(584) OR ROM64_INSTR_PT(585) + OR ROM64_INSTR_PT(586) OR ROM64_INSTR_PT(587) + OR ROM64_INSTR_PT(588) OR ROM64_INSTR_PT(589) + OR ROM64_INSTR_PT(590) OR ROM64_INSTR_PT(592) + OR ROM64_INSTR_PT(595) OR ROM64_INSTR_PT(596) + OR ROM64_INSTR_PT(597) OR ROM64_INSTR_PT(598) + OR ROM64_INSTR_PT(600) OR ROM64_INSTR_PT(601) + OR ROM64_INSTR_PT(603) OR ROM64_INSTR_PT(604) + OR ROM64_INSTR_PT(606) OR ROM64_INSTR_PT(608) + OR ROM64_INSTR_PT(610) OR ROM64_INSTR_PT(611) + OR ROM64_INSTR_PT(612) OR ROM64_INSTR_PT(613) + OR ROM64_INSTR_PT(614) OR ROM64_INSTR_PT(615) + OR ROM64_INSTR_PT(616) OR ROM64_INSTR_PT(617) + OR ROM64_INSTR_PT(618) OR ROM64_INSTR_PT(620) + OR ROM64_INSTR_PT(623) OR ROM64_INSTR_PT(626) + OR ROM64_INSTR_PT(627) OR ROM64_INSTR_PT(628) + OR ROM64_INSTR_PT(629) OR ROM64_INSTR_PT(632) + OR ROM64_INSTR_PT(633) OR ROM64_INSTR_PT(635) + OR ROM64_INSTR_PT(636) OR ROM64_INSTR_PT(639) + OR ROM64_INSTR_PT(642) OR ROM64_INSTR_PT(644) + OR ROM64_INSTR_PT(654) OR ROM64_INSTR_PT(657) + OR ROM64_INSTR_PT(659) OR ROM64_INSTR_PT(660) + OR ROM64_INSTR_PT(663) OR ROM64_INSTR_PT(664) + OR ROM64_INSTR_PT(666) OR ROM64_INSTR_PT(668) + OR ROM64_INSTR_PT(675) OR ROM64_INSTR_PT(678) + OR ROM64_INSTR_PT(681) OR ROM64_INSTR_PT(682) + OR ROM64_INSTR_PT(691) OR ROM64_INSTR_PT(695) + OR ROM64_INSTR_PT(703) OR ROM64_INSTR_PT(706) + OR ROM64_INSTR_PT(709) OR ROM64_INSTR_PT(713) + OR ROM64_INSTR_PT(717) OR ROM64_INSTR_PT(721) + OR ROM64_INSTR_PT(722) OR ROM64_INSTR_PT(723) + OR ROM64_INSTR_PT(724) OR ROM64_INSTR_PT(728) + OR ROM64_INSTR_PT(731) OR ROM64_INSTR_PT(733) + OR ROM64_INSTR_PT(735) OR ROM64_INSTR_PT(736) + OR ROM64_INSTR_PT(738) OR ROM64_INSTR_PT(744) + OR ROM64_INSTR_PT(759) OR ROM64_INSTR_PT(761) + OR ROM64_INSTR_PT(766) OR ROM64_INSTR_PT(769) + OR ROM64_INSTR_PT(776) OR ROM64_INSTR_PT(781) + OR ROM64_INSTR_PT(794) OR ROM64_INSTR_PT(797) + OR ROM64_INSTR_PT(798) OR ROM64_INSTR_PT(809) + OR ROM64_INSTR_PT(811) OR ROM64_INSTR_PT(813) + OR ROM64_INSTR_PT(822) OR ROM64_INSTR_PT(824) + OR ROM64_INSTR_PT(834) OR ROM64_INSTR_PT(846) + OR ROM64_INSTR_PT(854) OR ROM64_INSTR_PT(855) + OR ROM64_INSTR_PT(856) OR ROM64_INSTR_PT(858) + OR ROM64_INSTR_PT(864) OR ROM64_INSTR_PT(869) + OR ROM64_INSTR_PT(870) OR ROM64_INSTR_PT(883) + ); +MQQ895:TEMPLATE(4) <= + (ROM64_INSTR_PT(2) OR ROM64_INSTR_PT(5) + OR ROM64_INSTR_PT(6) OR ROM64_INSTR_PT(10) + OR ROM64_INSTR_PT(14) OR ROM64_INSTR_PT(15) + OR ROM64_INSTR_PT(18) OR ROM64_INSTR_PT(20) + OR ROM64_INSTR_PT(25) OR ROM64_INSTR_PT(28) + OR ROM64_INSTR_PT(29) OR ROM64_INSTR_PT(33) + OR ROM64_INSTR_PT(35) OR ROM64_INSTR_PT(36) + OR ROM64_INSTR_PT(39) OR ROM64_INSTR_PT(41) + OR ROM64_INSTR_PT(42) OR ROM64_INSTR_PT(43) + OR ROM64_INSTR_PT(45) OR ROM64_INSTR_PT(53) + OR ROM64_INSTR_PT(56) OR ROM64_INSTR_PT(60) + OR ROM64_INSTR_PT(65) OR ROM64_INSTR_PT(66) + OR ROM64_INSTR_PT(69) OR ROM64_INSTR_PT(73) + OR ROM64_INSTR_PT(74) OR ROM64_INSTR_PT(77) + OR ROM64_INSTR_PT(78) OR ROM64_INSTR_PT(79) + OR ROM64_INSTR_PT(80) OR ROM64_INSTR_PT(82) + OR ROM64_INSTR_PT(84) OR ROM64_INSTR_PT(89) + OR ROM64_INSTR_PT(92) OR ROM64_INSTR_PT(95) + OR ROM64_INSTR_PT(96) OR ROM64_INSTR_PT(97) + OR ROM64_INSTR_PT(98) OR ROM64_INSTR_PT(101) + OR ROM64_INSTR_PT(104) OR ROM64_INSTR_PT(106) + OR ROM64_INSTR_PT(108) OR ROM64_INSTR_PT(109) + OR ROM64_INSTR_PT(110) OR ROM64_INSTR_PT(112) + OR ROM64_INSTR_PT(114) OR ROM64_INSTR_PT(116) + OR ROM64_INSTR_PT(119) OR ROM64_INSTR_PT(124) + OR ROM64_INSTR_PT(129) OR ROM64_INSTR_PT(139) + OR ROM64_INSTR_PT(140) OR ROM64_INSTR_PT(142) + OR ROM64_INSTR_PT(143) OR ROM64_INSTR_PT(145) + OR ROM64_INSTR_PT(146) OR ROM64_INSTR_PT(147) + OR ROM64_INSTR_PT(150) OR ROM64_INSTR_PT(151) + OR ROM64_INSTR_PT(153) OR ROM64_INSTR_PT(155) + OR ROM64_INSTR_PT(158) OR ROM64_INSTR_PT(160) + OR ROM64_INSTR_PT(161) OR ROM64_INSTR_PT(166) + OR ROM64_INSTR_PT(168) OR ROM64_INSTR_PT(172) + OR ROM64_INSTR_PT(173) OR ROM64_INSTR_PT(174) + OR ROM64_INSTR_PT(175) OR ROM64_INSTR_PT(176) + OR ROM64_INSTR_PT(177) OR ROM64_INSTR_PT(179) + OR ROM64_INSTR_PT(181) OR ROM64_INSTR_PT(182) + OR ROM64_INSTR_PT(183) OR ROM64_INSTR_PT(184) + OR ROM64_INSTR_PT(187) OR ROM64_INSTR_PT(188) + OR ROM64_INSTR_PT(191) OR ROM64_INSTR_PT(193) + OR ROM64_INSTR_PT(194) OR ROM64_INSTR_PT(202) + OR ROM64_INSTR_PT(203) OR ROM64_INSTR_PT(205) + OR ROM64_INSTR_PT(206) OR ROM64_INSTR_PT(207) + OR ROM64_INSTR_PT(208) OR ROM64_INSTR_PT(209) + OR ROM64_INSTR_PT(211) OR ROM64_INSTR_PT(216) + OR ROM64_INSTR_PT(219) OR ROM64_INSTR_PT(221) + OR ROM64_INSTR_PT(225) OR ROM64_INSTR_PT(228) + OR ROM64_INSTR_PT(229) OR ROM64_INSTR_PT(230) + OR ROM64_INSTR_PT(231) OR ROM64_INSTR_PT(233) + OR ROM64_INSTR_PT(237) OR ROM64_INSTR_PT(240) + OR ROM64_INSTR_PT(242) OR ROM64_INSTR_PT(243) + OR ROM64_INSTR_PT(247) OR ROM64_INSTR_PT(253) + OR ROM64_INSTR_PT(254) OR ROM64_INSTR_PT(257) + OR ROM64_INSTR_PT(258) OR ROM64_INSTR_PT(259) + OR ROM64_INSTR_PT(260) OR ROM64_INSTR_PT(261) + OR ROM64_INSTR_PT(265) OR ROM64_INSTR_PT(269) + OR ROM64_INSTR_PT(273) OR ROM64_INSTR_PT(274) + OR ROM64_INSTR_PT(277) OR ROM64_INSTR_PT(281) + OR ROM64_INSTR_PT(284) OR ROM64_INSTR_PT(288) + OR ROM64_INSTR_PT(290) OR ROM64_INSTR_PT(292) + OR ROM64_INSTR_PT(294) OR ROM64_INSTR_PT(295) + OR ROM64_INSTR_PT(304) OR ROM64_INSTR_PT(307) + OR ROM64_INSTR_PT(309) OR ROM64_INSTR_PT(311) + OR ROM64_INSTR_PT(313) OR ROM64_INSTR_PT(319) + OR ROM64_INSTR_PT(320) OR ROM64_INSTR_PT(324) + OR ROM64_INSTR_PT(325) OR ROM64_INSTR_PT(327) + OR ROM64_INSTR_PT(332) OR ROM64_INSTR_PT(334) + OR ROM64_INSTR_PT(339) OR ROM64_INSTR_PT(340) + OR ROM64_INSTR_PT(341) OR ROM64_INSTR_PT(342) + OR ROM64_INSTR_PT(348) OR ROM64_INSTR_PT(350) + OR ROM64_INSTR_PT(352) OR ROM64_INSTR_PT(353) + OR ROM64_INSTR_PT(358) OR ROM64_INSTR_PT(359) + OR ROM64_INSTR_PT(360) OR ROM64_INSTR_PT(361) + OR ROM64_INSTR_PT(362) OR ROM64_INSTR_PT(365) + OR ROM64_INSTR_PT(366) OR ROM64_INSTR_PT(368) + OR ROM64_INSTR_PT(369) OR ROM64_INSTR_PT(371) + OR ROM64_INSTR_PT(372) OR ROM64_INSTR_PT(374) + OR ROM64_INSTR_PT(377) OR ROM64_INSTR_PT(378) + OR ROM64_INSTR_PT(379) OR ROM64_INSTR_PT(381) + OR ROM64_INSTR_PT(384) OR ROM64_INSTR_PT(388) + OR ROM64_INSTR_PT(389) OR ROM64_INSTR_PT(392) + OR ROM64_INSTR_PT(394) OR ROM64_INSTR_PT(395) + OR ROM64_INSTR_PT(396) OR ROM64_INSTR_PT(401) + OR ROM64_INSTR_PT(402) OR ROM64_INSTR_PT(403) + OR ROM64_INSTR_PT(405) OR ROM64_INSTR_PT(406) + OR ROM64_INSTR_PT(408) OR ROM64_INSTR_PT(409) + OR ROM64_INSTR_PT(413) OR ROM64_INSTR_PT(418) + OR ROM64_INSTR_PT(419) OR ROM64_INSTR_PT(420) + OR ROM64_INSTR_PT(422) OR ROM64_INSTR_PT(425) + OR ROM64_INSTR_PT(426) OR ROM64_INSTR_PT(428) + OR ROM64_INSTR_PT(429) OR ROM64_INSTR_PT(430) + OR ROM64_INSTR_PT(438) OR ROM64_INSTR_PT(439) + OR ROM64_INSTR_PT(440) OR ROM64_INSTR_PT(443) + OR ROM64_INSTR_PT(445) OR ROM64_INSTR_PT(446) + OR ROM64_INSTR_PT(448) OR ROM64_INSTR_PT(451) + OR ROM64_INSTR_PT(453) OR ROM64_INSTR_PT(454) + OR ROM64_INSTR_PT(455) OR ROM64_INSTR_PT(456) + OR ROM64_INSTR_PT(458) OR ROM64_INSTR_PT(460) + OR ROM64_INSTR_PT(463) OR ROM64_INSTR_PT(464) + OR ROM64_INSTR_PT(466) OR ROM64_INSTR_PT(467) + OR ROM64_INSTR_PT(468) OR ROM64_INSTR_PT(470) + OR ROM64_INSTR_PT(471) OR ROM64_INSTR_PT(472) + OR ROM64_INSTR_PT(473) OR ROM64_INSTR_PT(474) + OR ROM64_INSTR_PT(475) OR ROM64_INSTR_PT(477) + OR ROM64_INSTR_PT(483) OR ROM64_INSTR_PT(490) + OR ROM64_INSTR_PT(491) OR ROM64_INSTR_PT(497) + OR ROM64_INSTR_PT(498) OR ROM64_INSTR_PT(499) + OR ROM64_INSTR_PT(503) OR ROM64_INSTR_PT(506) + OR ROM64_INSTR_PT(508) OR ROM64_INSTR_PT(510) + OR ROM64_INSTR_PT(516) OR ROM64_INSTR_PT(517) + OR ROM64_INSTR_PT(519) OR ROM64_INSTR_PT(520) + OR ROM64_INSTR_PT(527) OR ROM64_INSTR_PT(532) + OR ROM64_INSTR_PT(538) OR ROM64_INSTR_PT(542) + OR ROM64_INSTR_PT(546) OR ROM64_INSTR_PT(549) + OR ROM64_INSTR_PT(551) OR ROM64_INSTR_PT(553) + OR ROM64_INSTR_PT(554) OR ROM64_INSTR_PT(557) + OR ROM64_INSTR_PT(559) OR ROM64_INSTR_PT(562) + OR ROM64_INSTR_PT(564) OR ROM64_INSTR_PT(566) + OR ROM64_INSTR_PT(570) OR ROM64_INSTR_PT(571) + OR ROM64_INSTR_PT(572) OR ROM64_INSTR_PT(575) + OR ROM64_INSTR_PT(580) OR ROM64_INSTR_PT(581) + OR ROM64_INSTR_PT(586) OR ROM64_INSTR_PT(589) + OR ROM64_INSTR_PT(590) OR ROM64_INSTR_PT(593) + OR ROM64_INSTR_PT(596) OR ROM64_INSTR_PT(597) + OR ROM64_INSTR_PT(598) OR ROM64_INSTR_PT(601) + OR ROM64_INSTR_PT(602) OR ROM64_INSTR_PT(603) + OR ROM64_INSTR_PT(604) OR ROM64_INSTR_PT(606) + OR ROM64_INSTR_PT(610) OR ROM64_INSTR_PT(611) + OR ROM64_INSTR_PT(612) OR ROM64_INSTR_PT(613) + OR ROM64_INSTR_PT(614) OR ROM64_INSTR_PT(615) + OR ROM64_INSTR_PT(616) OR ROM64_INSTR_PT(617) + OR ROM64_INSTR_PT(620) OR ROM64_INSTR_PT(626) + OR ROM64_INSTR_PT(627) OR ROM64_INSTR_PT(628) + OR ROM64_INSTR_PT(632) OR ROM64_INSTR_PT(635) + OR ROM64_INSTR_PT(636) OR ROM64_INSTR_PT(641) + OR ROM64_INSTR_PT(653) OR ROM64_INSTR_PT(654) + OR ROM64_INSTR_PT(659) OR ROM64_INSTR_PT(660) + OR ROM64_INSTR_PT(663) OR ROM64_INSTR_PT(664) + OR ROM64_INSTR_PT(668) OR ROM64_INSTR_PT(675) + OR ROM64_INSTR_PT(681) OR ROM64_INSTR_PT(682) + OR ROM64_INSTR_PT(685) OR ROM64_INSTR_PT(691) + OR ROM64_INSTR_PT(694) OR ROM64_INSTR_PT(695) + OR ROM64_INSTR_PT(702) OR ROM64_INSTR_PT(703) + OR ROM64_INSTR_PT(706) OR ROM64_INSTR_PT(709) + OR ROM64_INSTR_PT(713) OR ROM64_INSTR_PT(716) + OR ROM64_INSTR_PT(717) OR ROM64_INSTR_PT(721) + OR ROM64_INSTR_PT(723) OR ROM64_INSTR_PT(724) + OR ROM64_INSTR_PT(728) OR ROM64_INSTR_PT(733) + OR ROM64_INSTR_PT(735) OR ROM64_INSTR_PT(736) + OR ROM64_INSTR_PT(738) OR ROM64_INSTR_PT(741) + OR ROM64_INSTR_PT(759) OR ROM64_INSTR_PT(766) + OR ROM64_INSTR_PT(770) OR ROM64_INSTR_PT(781) + OR ROM64_INSTR_PT(794) OR ROM64_INSTR_PT(797) + OR ROM64_INSTR_PT(798) OR ROM64_INSTR_PT(801) + OR ROM64_INSTR_PT(808) OR ROM64_INSTR_PT(809) + OR ROM64_INSTR_PT(811) OR ROM64_INSTR_PT(813) + OR ROM64_INSTR_PT(822) OR ROM64_INSTR_PT(824) + OR ROM64_INSTR_PT(832) OR ROM64_INSTR_PT(834) + OR ROM64_INSTR_PT(846) OR ROM64_INSTR_PT(849) + OR ROM64_INSTR_PT(852) OR ROM64_INSTR_PT(854) + OR ROM64_INSTR_PT(855) OR ROM64_INSTR_PT(858) + OR ROM64_INSTR_PT(869) OR ROM64_INSTR_PT(873) + OR ROM64_INSTR_PT(883)); +MQQ896:TEMPLATE(5) <= + (ROM64_INSTR_PT(4) OR ROM64_INSTR_PT(6) + OR ROM64_INSTR_PT(7) OR ROM64_INSTR_PT(8) + OR ROM64_INSTR_PT(11) OR ROM64_INSTR_PT(14) + OR ROM64_INSTR_PT(15) OR ROM64_INSTR_PT(18) + OR ROM64_INSTR_PT(21) OR ROM64_INSTR_PT(35) + OR ROM64_INSTR_PT(38) OR ROM64_INSTR_PT(41) + OR ROM64_INSTR_PT(42) OR ROM64_INSTR_PT(45) + OR ROM64_INSTR_PT(49) OR ROM64_INSTR_PT(51) + OR ROM64_INSTR_PT(52) OR ROM64_INSTR_PT(53) + OR ROM64_INSTR_PT(56) OR ROM64_INSTR_PT(57) + OR ROM64_INSTR_PT(61) OR ROM64_INSTR_PT(64) + OR ROM64_INSTR_PT(68) OR ROM64_INSTR_PT(69) + OR ROM64_INSTR_PT(70) OR ROM64_INSTR_PT(73) + OR ROM64_INSTR_PT(82) OR ROM64_INSTR_PT(83) + OR ROM64_INSTR_PT(84) OR ROM64_INSTR_PT(86) + OR ROM64_INSTR_PT(90) OR ROM64_INSTR_PT(93) + OR ROM64_INSTR_PT(95) OR ROM64_INSTR_PT(100) + OR ROM64_INSTR_PT(101) OR ROM64_INSTR_PT(102) + OR ROM64_INSTR_PT(105) OR ROM64_INSTR_PT(108) + OR ROM64_INSTR_PT(109) OR ROM64_INSTR_PT(115) + OR ROM64_INSTR_PT(116) OR ROM64_INSTR_PT(117) + OR ROM64_INSTR_PT(118) OR ROM64_INSTR_PT(124) + OR ROM64_INSTR_PT(128) OR ROM64_INSTR_PT(132) + OR ROM64_INSTR_PT(133) OR ROM64_INSTR_PT(137) + OR ROM64_INSTR_PT(140) OR ROM64_INSTR_PT(143) + OR ROM64_INSTR_PT(144) OR ROM64_INSTR_PT(145) + OR ROM64_INSTR_PT(153) OR ROM64_INSTR_PT(155) + OR ROM64_INSTR_PT(157) OR ROM64_INSTR_PT(158) + OR ROM64_INSTR_PT(162) OR ROM64_INSTR_PT(164) + OR ROM64_INSTR_PT(168) OR ROM64_INSTR_PT(169) + OR ROM64_INSTR_PT(170) OR ROM64_INSTR_PT(177) + OR ROM64_INSTR_PT(180) OR ROM64_INSTR_PT(181) + OR ROM64_INSTR_PT(183) OR ROM64_INSTR_PT(185) + OR ROM64_INSTR_PT(186) OR ROM64_INSTR_PT(194) + OR ROM64_INSTR_PT(196) OR ROM64_INSTR_PT(201) + OR ROM64_INSTR_PT(203) OR ROM64_INSTR_PT(204) + OR ROM64_INSTR_PT(205) OR ROM64_INSTR_PT(206) + OR ROM64_INSTR_PT(211) OR ROM64_INSTR_PT(215) + OR ROM64_INSTR_PT(218) OR ROM64_INSTR_PT(219) + OR ROM64_INSTR_PT(223) OR ROM64_INSTR_PT(226) + OR ROM64_INSTR_PT(233) OR ROM64_INSTR_PT(238) + OR ROM64_INSTR_PT(241) OR ROM64_INSTR_PT(243) + OR ROM64_INSTR_PT(244) OR ROM64_INSTR_PT(245) + OR ROM64_INSTR_PT(249) OR ROM64_INSTR_PT(254) + OR ROM64_INSTR_PT(258) OR ROM64_INSTR_PT(260) + OR ROM64_INSTR_PT(263) OR ROM64_INSTR_PT(264) + OR ROM64_INSTR_PT(265) OR ROM64_INSTR_PT(268) + OR ROM64_INSTR_PT(269) OR ROM64_INSTR_PT(270) + OR ROM64_INSTR_PT(272) OR ROM64_INSTR_PT(276) + OR ROM64_INSTR_PT(278) OR ROM64_INSTR_PT(280) + OR ROM64_INSTR_PT(282) OR ROM64_INSTR_PT(284) + OR ROM64_INSTR_PT(285) OR ROM64_INSTR_PT(287) + OR ROM64_INSTR_PT(290) OR ROM64_INSTR_PT(293) + OR ROM64_INSTR_PT(294) OR ROM64_INSTR_PT(297) + OR ROM64_INSTR_PT(302) OR ROM64_INSTR_PT(305) + OR ROM64_INSTR_PT(308) OR ROM64_INSTR_PT(311) + OR ROM64_INSTR_PT(312) OR ROM64_INSTR_PT(319) + OR ROM64_INSTR_PT(325) OR ROM64_INSTR_PT(339) + OR ROM64_INSTR_PT(348) OR ROM64_INSTR_PT(350) + OR ROM64_INSTR_PT(353) OR ROM64_INSTR_PT(355) + OR ROM64_INSTR_PT(358) OR ROM64_INSTR_PT(364) + OR ROM64_INSTR_PT(366) OR ROM64_INSTR_PT(367) + OR ROM64_INSTR_PT(370) OR ROM64_INSTR_PT(372) + OR ROM64_INSTR_PT(375) OR ROM64_INSTR_PT(378) + OR ROM64_INSTR_PT(379) OR ROM64_INSTR_PT(383) + OR ROM64_INSTR_PT(384) OR ROM64_INSTR_PT(385) + OR ROM64_INSTR_PT(391) OR ROM64_INSTR_PT(394) + OR ROM64_INSTR_PT(395) OR ROM64_INSTR_PT(397) + OR ROM64_INSTR_PT(399) OR ROM64_INSTR_PT(403) + OR ROM64_INSTR_PT(405) OR ROM64_INSTR_PT(409) + OR ROM64_INSTR_PT(410) OR ROM64_INSTR_PT(413) + OR ROM64_INSTR_PT(416) OR ROM64_INSTR_PT(417) + OR ROM64_INSTR_PT(418) OR ROM64_INSTR_PT(419) + OR ROM64_INSTR_PT(425) OR ROM64_INSTR_PT(426) + OR ROM64_INSTR_PT(427) OR ROM64_INSTR_PT(428) + OR ROM64_INSTR_PT(429) OR ROM64_INSTR_PT(430) + OR ROM64_INSTR_PT(432) OR ROM64_INSTR_PT(433) + OR ROM64_INSTR_PT(435) OR ROM64_INSTR_PT(438) + OR ROM64_INSTR_PT(439) OR ROM64_INSTR_PT(440) + OR ROM64_INSTR_PT(441) OR ROM64_INSTR_PT(443) + OR ROM64_INSTR_PT(445) OR ROM64_INSTR_PT(446) + OR ROM64_INSTR_PT(451) OR ROM64_INSTR_PT(453) + OR ROM64_INSTR_PT(454) OR ROM64_INSTR_PT(455) + OR ROM64_INSTR_PT(456) OR ROM64_INSTR_PT(457) + OR ROM64_INSTR_PT(460) OR ROM64_INSTR_PT(467) + OR ROM64_INSTR_PT(473) OR ROM64_INSTR_PT(475) + OR ROM64_INSTR_PT(478) OR ROM64_INSTR_PT(481) + OR ROM64_INSTR_PT(482) OR ROM64_INSTR_PT(484) + OR ROM64_INSTR_PT(485) OR ROM64_INSTR_PT(488) + OR ROM64_INSTR_PT(490) OR ROM64_INSTR_PT(493) + OR ROM64_INSTR_PT(495) OR ROM64_INSTR_PT(496) + OR ROM64_INSTR_PT(504) OR ROM64_INSTR_PT(506) + OR ROM64_INSTR_PT(510) OR ROM64_INSTR_PT(512) + OR ROM64_INSTR_PT(514) OR ROM64_INSTR_PT(519) + OR ROM64_INSTR_PT(522) OR ROM64_INSTR_PT(523) + OR ROM64_INSTR_PT(525) OR ROM64_INSTR_PT(530) + OR ROM64_INSTR_PT(531) OR ROM64_INSTR_PT(532) + OR ROM64_INSTR_PT(534) OR ROM64_INSTR_PT(539) + OR ROM64_INSTR_PT(542) OR ROM64_INSTR_PT(546) + OR ROM64_INSTR_PT(552) OR ROM64_INSTR_PT(553) + OR ROM64_INSTR_PT(554) OR ROM64_INSTR_PT(555) + OR ROM64_INSTR_PT(557) OR ROM64_INSTR_PT(559) + OR ROM64_INSTR_PT(563) OR ROM64_INSTR_PT(564) + OR ROM64_INSTR_PT(566) OR ROM64_INSTR_PT(568) + OR ROM64_INSTR_PT(570) OR ROM64_INSTR_PT(571) + OR ROM64_INSTR_PT(576) OR ROM64_INSTR_PT(577) + OR ROM64_INSTR_PT(580) OR ROM64_INSTR_PT(581) + OR ROM64_INSTR_PT(582) OR ROM64_INSTR_PT(583) + OR ROM64_INSTR_PT(584) OR ROM64_INSTR_PT(585) + OR ROM64_INSTR_PT(586) OR ROM64_INSTR_PT(587) + OR ROM64_INSTR_PT(589) OR ROM64_INSTR_PT(591) + OR ROM64_INSTR_PT(592) OR ROM64_INSTR_PT(604) + OR ROM64_INSTR_PT(606) OR ROM64_INSTR_PT(607) + OR ROM64_INSTR_PT(608) OR ROM64_INSTR_PT(611) + OR ROM64_INSTR_PT(615) OR ROM64_INSTR_PT(616) + OR ROM64_INSTR_PT(619) OR ROM64_INSTR_PT(625) + OR ROM64_INSTR_PT(626) OR ROM64_INSTR_PT(627) + OR ROM64_INSTR_PT(629) OR ROM64_INSTR_PT(633) + OR ROM64_INSTR_PT(636) OR ROM64_INSTR_PT(639) + OR ROM64_INSTR_PT(642) OR ROM64_INSTR_PT(643) + OR ROM64_INSTR_PT(655) OR ROM64_INSTR_PT(660) + OR ROM64_INSTR_PT(663) OR ROM64_INSTR_PT(664) + OR ROM64_INSTR_PT(666) OR ROM64_INSTR_PT(678) + OR ROM64_INSTR_PT(681) OR ROM64_INSTR_PT(695) + OR ROM64_INSTR_PT(698) OR ROM64_INSTR_PT(702) + OR ROM64_INSTR_PT(713) OR ROM64_INSTR_PT(716) + OR ROM64_INSTR_PT(721) OR ROM64_INSTR_PT(722) + OR ROM64_INSTR_PT(731) OR ROM64_INSTR_PT(736) + OR ROM64_INSTR_PT(753) OR ROM64_INSTR_PT(761) + OR ROM64_INSTR_PT(769) OR ROM64_INSTR_PT(770) + OR ROM64_INSTR_PT(798) OR ROM64_INSTR_PT(811) + OR ROM64_INSTR_PT(813) OR ROM64_INSTR_PT(823) + OR ROM64_INSTR_PT(824) OR ROM64_INSTR_PT(832) + OR ROM64_INSTR_PT(834) OR ROM64_INSTR_PT(846) + OR ROM64_INSTR_PT(854) OR ROM64_INSTR_PT(855) + OR ROM64_INSTR_PT(856) OR ROM64_INSTR_PT(858) + OR ROM64_INSTR_PT(864) OR ROM64_INSTR_PT(870) + OR ROM64_INSTR_PT(873)); +MQQ897:TEMPLATE(6) <= + ('0'); +MQQ898:TEMPLATE(7) <= + ('0'); +MQQ899:TEMPLATE(8) <= + ('0'); +MQQ900:TEMPLATE(9) <= + (ROM64_INSTR_PT(7) OR ROM64_INSTR_PT(9) + OR ROM64_INSTR_PT(11) OR ROM64_INSTR_PT(13) + OR ROM64_INSTR_PT(15) OR ROM64_INSTR_PT(22) + OR ROM64_INSTR_PT(25) OR ROM64_INSTR_PT(29) + OR ROM64_INSTR_PT(36) OR ROM64_INSTR_PT(38) + OR ROM64_INSTR_PT(42) OR ROM64_INSTR_PT(45) + OR ROM64_INSTR_PT(53) OR ROM64_INSTR_PT(55) + OR ROM64_INSTR_PT(56) OR ROM64_INSTR_PT(58) + OR ROM64_INSTR_PT(61) OR ROM64_INSTR_PT(70) + OR ROM64_INSTR_PT(71) OR ROM64_INSTR_PT(84) + OR ROM64_INSTR_PT(86) OR ROM64_INSTR_PT(90) + OR ROM64_INSTR_PT(93) OR ROM64_INSTR_PT(97) + OR ROM64_INSTR_PT(100) OR ROM64_INSTR_PT(102) + OR ROM64_INSTR_PT(104) OR ROM64_INSTR_PT(105) + OR ROM64_INSTR_PT(116) OR ROM64_INSTR_PT(119) + OR ROM64_INSTR_PT(124) OR ROM64_INSTR_PT(132) + OR ROM64_INSTR_PT(136) OR ROM64_INSTR_PT(137) + OR ROM64_INSTR_PT(143) OR ROM64_INSTR_PT(144) + OR ROM64_INSTR_PT(148) OR ROM64_INSTR_PT(154) + OR ROM64_INSTR_PT(155) OR ROM64_INSTR_PT(160) + OR ROM64_INSTR_PT(172) OR ROM64_INSTR_PT(174) + OR ROM64_INSTR_PT(176) OR ROM64_INSTR_PT(177) + OR ROM64_INSTR_PT(179) OR ROM64_INSTR_PT(180) + OR ROM64_INSTR_PT(181) OR ROM64_INSTR_PT(183) + OR ROM64_INSTR_PT(186) OR ROM64_INSTR_PT(193) + OR ROM64_INSTR_PT(201) OR ROM64_INSTR_PT(208) + OR ROM64_INSTR_PT(213) OR ROM64_INSTR_PT(215) + OR ROM64_INSTR_PT(216) OR ROM64_INSTR_PT(221) + OR ROM64_INSTR_PT(222) OR ROM64_INSTR_PT(225) + OR ROM64_INSTR_PT(226) OR ROM64_INSTR_PT(238) + OR ROM64_INSTR_PT(240) OR ROM64_INSTR_PT(242) + OR ROM64_INSTR_PT(243) OR ROM64_INSTR_PT(245) + OR ROM64_INSTR_PT(249) OR ROM64_INSTR_PT(259) + OR ROM64_INSTR_PT(261) OR ROM64_INSTR_PT(262) + OR ROM64_INSTR_PT(263) OR ROM64_INSTR_PT(265) + OR ROM64_INSTR_PT(270) OR ROM64_INSTR_PT(274) + OR ROM64_INSTR_PT(275) OR ROM64_INSTR_PT(276) + OR ROM64_INSTR_PT(277) OR ROM64_INSTR_PT(282) + OR ROM64_INSTR_PT(284) OR ROM64_INSTR_PT(285) + OR ROM64_INSTR_PT(286) OR ROM64_INSTR_PT(292) + OR ROM64_INSTR_PT(293) OR ROM64_INSTR_PT(297) + OR ROM64_INSTR_PT(299) OR ROM64_INSTR_PT(302) + OR ROM64_INSTR_PT(305) OR ROM64_INSTR_PT(311) + OR ROM64_INSTR_PT(315) OR ROM64_INSTR_PT(319) + OR ROM64_INSTR_PT(320) OR ROM64_INSTR_PT(322) + OR ROM64_INSTR_PT(341) OR ROM64_INSTR_PT(349) + OR ROM64_INSTR_PT(355) OR ROM64_INSTR_PT(359) + OR ROM64_INSTR_PT(362) OR ROM64_INSTR_PT(365) + OR ROM64_INSTR_PT(366) OR ROM64_INSTR_PT(369) + OR ROM64_INSTR_PT(372) OR ROM64_INSTR_PT(379) + OR ROM64_INSTR_PT(382) OR ROM64_INSTR_PT(383) + OR ROM64_INSTR_PT(385) OR ROM64_INSTR_PT(388) + OR ROM64_INSTR_PT(389) OR ROM64_INSTR_PT(392) + OR ROM64_INSTR_PT(394) OR ROM64_INSTR_PT(395) + OR ROM64_INSTR_PT(396) OR ROM64_INSTR_PT(402) + OR ROM64_INSTR_PT(403) OR ROM64_INSTR_PT(404) + OR ROM64_INSTR_PT(405) OR ROM64_INSTR_PT(410) + OR ROM64_INSTR_PT(413) OR ROM64_INSTR_PT(415) + OR ROM64_INSTR_PT(418) OR ROM64_INSTR_PT(425) + OR ROM64_INSTR_PT(426) OR ROM64_INSTR_PT(429) + OR ROM64_INSTR_PT(434) OR ROM64_INSTR_PT(435) + OR ROM64_INSTR_PT(437) OR ROM64_INSTR_PT(438) + OR ROM64_INSTR_PT(440) OR ROM64_INSTR_PT(445) + OR ROM64_INSTR_PT(446) OR ROM64_INSTR_PT(451) + OR ROM64_INSTR_PT(453) OR ROM64_INSTR_PT(456) + OR ROM64_INSTR_PT(457) OR ROM64_INSTR_PT(467) + OR ROM64_INSTR_PT(470) OR ROM64_INSTR_PT(473) + OR ROM64_INSTR_PT(474) OR ROM64_INSTR_PT(475) + OR ROM64_INSTR_PT(478) OR ROM64_INSTR_PT(482) + OR ROM64_INSTR_PT(485) OR ROM64_INSTR_PT(491) + OR ROM64_INSTR_PT(493) OR ROM64_INSTR_PT(495) + OR ROM64_INSTR_PT(498) OR ROM64_INSTR_PT(499) + OR ROM64_INSTR_PT(504) OR ROM64_INSTR_PT(505) + OR ROM64_INSTR_PT(507) OR ROM64_INSTR_PT(509) + OR ROM64_INSTR_PT(517) OR ROM64_INSTR_PT(519) + OR ROM64_INSTR_PT(520) OR ROM64_INSTR_PT(521) + OR ROM64_INSTR_PT(522) OR ROM64_INSTR_PT(532) + OR ROM64_INSTR_PT(534) OR ROM64_INSTR_PT(535) + OR ROM64_INSTR_PT(544) OR ROM64_INSTR_PT(546) + OR ROM64_INSTR_PT(549) OR ROM64_INSTR_PT(552) + OR ROM64_INSTR_PT(555) OR ROM64_INSTR_PT(558) + OR ROM64_INSTR_PT(559) OR ROM64_INSTR_PT(568) + OR ROM64_INSTR_PT(569) OR ROM64_INSTR_PT(571) + OR ROM64_INSTR_PT(572) OR ROM64_INSTR_PT(575) + OR ROM64_INSTR_PT(576) OR ROM64_INSTR_PT(590) + OR ROM64_INSTR_PT(591) OR ROM64_INSTR_PT(592) + OR ROM64_INSTR_PT(593) OR ROM64_INSTR_PT(595) + OR ROM64_INSTR_PT(606) OR ROM64_INSTR_PT(608) + OR ROM64_INSTR_PT(610) OR ROM64_INSTR_PT(612) + OR ROM64_INSTR_PT(615) OR ROM64_INSTR_PT(617) + OR ROM64_INSTR_PT(618) OR ROM64_INSTR_PT(623) + OR ROM64_INSTR_PT(628) OR ROM64_INSTR_PT(633) + OR ROM64_INSTR_PT(639) OR ROM64_INSTR_PT(645) + OR ROM64_INSTR_PT(646) OR ROM64_INSTR_PT(653) + OR ROM64_INSTR_PT(659) OR ROM64_INSTR_PT(663) + OR ROM64_INSTR_PT(666) OR ROM64_INSTR_PT(678) + OR ROM64_INSTR_PT(691) OR ROM64_INSTR_PT(693) + OR ROM64_INSTR_PT(703) OR ROM64_INSTR_PT(705) + OR ROM64_INSTR_PT(741) OR ROM64_INSTR_PT(753) + OR ROM64_INSTR_PT(797) OR ROM64_INSTR_PT(846) + ); +MQQ901:TEMPLATE(10) <= + (ROM64_INSTR_PT(4) OR ROM64_INSTR_PT(6) + OR ROM64_INSTR_PT(7) OR ROM64_INSTR_PT(14) + OR ROM64_INSTR_PT(15) OR ROM64_INSTR_PT(17) + OR ROM64_INSTR_PT(20) OR ROM64_INSTR_PT(34) + OR ROM64_INSTR_PT(39) OR ROM64_INSTR_PT(41) + OR ROM64_INSTR_PT(42) OR ROM64_INSTR_PT(45) + OR ROM64_INSTR_PT(51) OR ROM64_INSTR_PT(52) + OR ROM64_INSTR_PT(53) OR ROM64_INSTR_PT(57) + OR ROM64_INSTR_PT(73) OR ROM64_INSTR_PT(74) + OR ROM64_INSTR_PT(75) OR ROM64_INSTR_PT(84) + OR ROM64_INSTR_PT(98) OR ROM64_INSTR_PT(99) + OR ROM64_INSTR_PT(112) OR ROM64_INSTR_PT(113) + OR ROM64_INSTR_PT(116) OR ROM64_INSTR_PT(117) + OR ROM64_INSTR_PT(122) OR ROM64_INSTR_PT(125) + OR ROM64_INSTR_PT(127) OR ROM64_INSTR_PT(128) + OR ROM64_INSTR_PT(129) OR ROM64_INSTR_PT(132) + OR ROM64_INSTR_PT(139) OR ROM64_INSTR_PT(140) + OR ROM64_INSTR_PT(143) OR ROM64_INSTR_PT(153) + OR ROM64_INSTR_PT(168) OR ROM64_INSTR_PT(169) + OR ROM64_INSTR_PT(171) OR ROM64_INSTR_PT(173) + OR ROM64_INSTR_PT(174) OR ROM64_INSTR_PT(181) + OR ROM64_INSTR_PT(183) OR ROM64_INSTR_PT(184) + OR ROM64_INSTR_PT(185) OR ROM64_INSTR_PT(191) + OR ROM64_INSTR_PT(194) OR ROM64_INSTR_PT(199) + OR ROM64_INSTR_PT(202) OR ROM64_INSTR_PT(203) + OR ROM64_INSTR_PT(204) OR ROM64_INSTR_PT(213) + OR ROM64_INSTR_PT(217) OR ROM64_INSTR_PT(219) + OR ROM64_INSTR_PT(229) OR ROM64_INSTR_PT(230) + OR ROM64_INSTR_PT(237) OR ROM64_INSTR_PT(240) + OR ROM64_INSTR_PT(241) OR ROM64_INSTR_PT(252) + OR ROM64_INSTR_PT(253) OR ROM64_INSTR_PT(258) + OR ROM64_INSTR_PT(260) OR ROM64_INSTR_PT(264) + OR ROM64_INSTR_PT(268) OR ROM64_INSTR_PT(271) + OR ROM64_INSTR_PT(272) OR ROM64_INSTR_PT(273) + OR ROM64_INSTR_PT(276) OR ROM64_INSTR_PT(278) + OR ROM64_INSTR_PT(283) OR ROM64_INSTR_PT(331) + OR ROM64_INSTR_PT(339) OR ROM64_INSTR_PT(361) + OR ROM64_INSTR_PT(364) OR ROM64_INSTR_PT(366) + OR ROM64_INSTR_PT(367) OR ROM64_INSTR_PT(368) + OR ROM64_INSTR_PT(374) OR ROM64_INSTR_PT(375) + OR ROM64_INSTR_PT(377) OR ROM64_INSTR_PT(381) + OR ROM64_INSTR_PT(384) OR ROM64_INSTR_PT(391) + OR ROM64_INSTR_PT(396) OR ROM64_INSTR_PT(401) + OR ROM64_INSTR_PT(403) OR ROM64_INSTR_PT(406) + OR ROM64_INSTR_PT(408) OR ROM64_INSTR_PT(420) + OR ROM64_INSTR_PT(424) OR ROM64_INSTR_PT(440) + OR ROM64_INSTR_PT(442) OR ROM64_INSTR_PT(445) + OR ROM64_INSTR_PT(448) OR ROM64_INSTR_PT(458) + OR ROM64_INSTR_PT(472) OR ROM64_INSTR_PT(477) + OR ROM64_INSTR_PT(480) OR ROM64_INSTR_PT(481) + OR ROM64_INSTR_PT(483) OR ROM64_INSTR_PT(491) + OR ROM64_INSTR_PT(503) OR ROM64_INSTR_PT(506) + OR ROM64_INSTR_PT(507) OR ROM64_INSTR_PT(508) + OR ROM64_INSTR_PT(511) OR ROM64_INSTR_PT(512) + OR ROM64_INSTR_PT(519) OR ROM64_INSTR_PT(525) + OR ROM64_INSTR_PT(527) OR ROM64_INSTR_PT(531) + OR ROM64_INSTR_PT(532) OR ROM64_INSTR_PT(538) + OR ROM64_INSTR_PT(539) OR ROM64_INSTR_PT(545) + OR ROM64_INSTR_PT(548) OR ROM64_INSTR_PT(553) + OR ROM64_INSTR_PT(554) OR ROM64_INSTR_PT(557) + OR ROM64_INSTR_PT(562) OR ROM64_INSTR_PT(563) + OR ROM64_INSTR_PT(571) OR ROM64_INSTR_PT(579) + OR ROM64_INSTR_PT(583) OR ROM64_INSTR_PT(588) + OR ROM64_INSTR_PT(597) OR ROM64_INSTR_PT(599) + OR ROM64_INSTR_PT(600) OR ROM64_INSTR_PT(602) + OR ROM64_INSTR_PT(603) OR ROM64_INSTR_PT(609) + OR ROM64_INSTR_PT(614) OR ROM64_INSTR_PT(619) + OR ROM64_INSTR_PT(627) OR ROM64_INSTR_PT(629) + OR ROM64_INSTR_PT(632) OR ROM64_INSTR_PT(636) + OR ROM64_INSTR_PT(637) OR ROM64_INSTR_PT(641) + OR ROM64_INSTR_PT(642) OR ROM64_INSTR_PT(644) + OR ROM64_INSTR_PT(655) OR ROM64_INSTR_PT(682) + OR ROM64_INSTR_PT(685) OR ROM64_INSTR_PT(691) + OR ROM64_INSTR_PT(713) OR ROM64_INSTR_PT(717) + OR ROM64_INSTR_PT(721) OR ROM64_INSTR_PT(723) + OR ROM64_INSTR_PT(724) OR ROM64_INSTR_PT(728) + OR ROM64_INSTR_PT(733) OR ROM64_INSTR_PT(735) + OR ROM64_INSTR_PT(736) OR ROM64_INSTR_PT(738) + OR ROM64_INSTR_PT(739) OR ROM64_INSTR_PT(761) + OR ROM64_INSTR_PT(770) OR ROM64_INSTR_PT(824) + OR ROM64_INSTR_PT(858) OR ROM64_INSTR_PT(873) + ); +MQQ902:TEMPLATE(11) <= + ('0'); +MQQ903:TEMPLATE(12) <= + ('0'); +MQQ904:TEMPLATE(13) <= + ('0'); +MQQ905:TEMPLATE(14) <= + (ROM64_INSTR_PT(7) OR ROM64_INSTR_PT(11) + OR ROM64_INSTR_PT(13) OR ROM64_INSTR_PT(15) + OR ROM64_INSTR_PT(17) OR ROM64_INSTR_PT(21) + OR ROM64_INSTR_PT(25) OR ROM64_INSTR_PT(34) + OR ROM64_INSTR_PT(36) OR ROM64_INSTR_PT(38) + OR ROM64_INSTR_PT(42) OR ROM64_INSTR_PT(52) + OR ROM64_INSTR_PT(53) OR ROM64_INSTR_PT(55) + OR ROM64_INSTR_PT(56) OR ROM64_INSTR_PT(61) + OR ROM64_INSTR_PT(64) OR ROM64_INSTR_PT(70) + OR ROM64_INSTR_PT(73) OR ROM64_INSTR_PT(75) + OR ROM64_INSTR_PT(77) OR ROM64_INSTR_PT(80) + OR ROM64_INSTR_PT(84) OR ROM64_INSTR_PT(86) + OR ROM64_INSTR_PT(89) OR ROM64_INSTR_PT(90) + OR ROM64_INSTR_PT(92) OR ROM64_INSTR_PT(93) + OR ROM64_INSTR_PT(96) OR ROM64_INSTR_PT(97) + OR ROM64_INSTR_PT(99) OR ROM64_INSTR_PT(102) + OR ROM64_INSTR_PT(104) OR ROM64_INSTR_PT(106) + OR ROM64_INSTR_PT(110) OR ROM64_INSTR_PT(113) + OR ROM64_INSTR_PT(114) OR ROM64_INSTR_PT(117) + OR ROM64_INSTR_PT(118) OR ROM64_INSTR_PT(125) + OR ROM64_INSTR_PT(127) OR ROM64_INSTR_PT(128) + OR ROM64_INSTR_PT(132) OR ROM64_INSTR_PT(139) + OR ROM64_INSTR_PT(144) OR ROM64_INSTR_PT(155) + OR ROM64_INSTR_PT(169) OR ROM64_INSTR_PT(171) + OR ROM64_INSTR_PT(172) OR ROM64_INSTR_PT(174) + OR ROM64_INSTR_PT(180) OR ROM64_INSTR_PT(181) + OR ROM64_INSTR_PT(184) OR ROM64_INSTR_PT(186) + OR ROM64_INSTR_PT(196) OR ROM64_INSTR_PT(199) + OR ROM64_INSTR_PT(201) OR ROM64_INSTR_PT(202) + OR ROM64_INSTR_PT(208) OR ROM64_INSTR_PT(213) + OR ROM64_INSTR_PT(215) OR ROM64_INSTR_PT(216) + OR ROM64_INSTR_PT(217) OR ROM64_INSTR_PT(223) + OR ROM64_INSTR_PT(226) OR ROM64_INSTR_PT(229) + OR ROM64_INSTR_PT(230) OR ROM64_INSTR_PT(238) + OR ROM64_INSTR_PT(240) OR ROM64_INSTR_PT(252) + OR ROM64_INSTR_PT(261) OR ROM64_INSTR_PT(264) + OR ROM64_INSTR_PT(268) OR ROM64_INSTR_PT(270) + OR ROM64_INSTR_PT(271) OR ROM64_INSTR_PT(272) + OR ROM64_INSTR_PT(274) OR ROM64_INSTR_PT(275) + OR ROM64_INSTR_PT(276) OR ROM64_INSTR_PT(277) + OR ROM64_INSTR_PT(280) OR ROM64_INSTR_PT(282) + OR ROM64_INSTR_PT(286) OR ROM64_INSTR_PT(287) + OR ROM64_INSTR_PT(293) OR ROM64_INSTR_PT(294) + OR ROM64_INSTR_PT(298) OR ROM64_INSTR_PT(302) + OR ROM64_INSTR_PT(305) OR ROM64_INSTR_PT(311) + OR ROM64_INSTR_PT(315) OR ROM64_INSTR_PT(322) + OR ROM64_INSTR_PT(331) OR ROM64_INSTR_PT(349) + OR ROM64_INSTR_PT(364) OR ROM64_INSTR_PT(365) + OR ROM64_INSTR_PT(366) OR ROM64_INSTR_PT(369) + OR ROM64_INSTR_PT(371) OR ROM64_INSTR_PT(372) + OR ROM64_INSTR_PT(375) OR ROM64_INSTR_PT(377) + OR ROM64_INSTR_PT(383) OR ROM64_INSTR_PT(385) + OR ROM64_INSTR_PT(388) OR ROM64_INSTR_PT(391) + OR ROM64_INSTR_PT(395) OR ROM64_INSTR_PT(396) + OR ROM64_INSTR_PT(397) OR ROM64_INSTR_PT(403) + OR ROM64_INSTR_PT(404) OR ROM64_INSTR_PT(405) + OR ROM64_INSTR_PT(410) OR ROM64_INSTR_PT(414) + OR ROM64_INSTR_PT(415) OR ROM64_INSTR_PT(420) + OR ROM64_INSTR_PT(422) OR ROM64_INSTR_PT(424) + OR ROM64_INSTR_PT(426) OR ROM64_INSTR_PT(427) + OR ROM64_INSTR_PT(434) OR ROM64_INSTR_PT(437) + OR ROM64_INSTR_PT(440) OR ROM64_INSTR_PT(445) + OR ROM64_INSTR_PT(456) OR ROM64_INSTR_PT(457) + OR ROM64_INSTR_PT(466) OR ROM64_INSTR_PT(467) + OR ROM64_INSTR_PT(473) OR ROM64_INSTR_PT(475) + OR ROM64_INSTR_PT(478) OR ROM64_INSTR_PT(482) + OR ROM64_INSTR_PT(483) OR ROM64_INSTR_PT(484) + OR ROM64_INSTR_PT(485) OR ROM64_INSTR_PT(488) + OR ROM64_INSTR_PT(493) OR ROM64_INSTR_PT(495) + OR ROM64_INSTR_PT(498) OR ROM64_INSTR_PT(503) + OR ROM64_INSTR_PT(505) OR ROM64_INSTR_PT(511) + OR ROM64_INSTR_PT(517) OR ROM64_INSTR_PT(519) + OR ROM64_INSTR_PT(520) OR ROM64_INSTR_PT(521) + OR ROM64_INSTR_PT(522) OR ROM64_INSTR_PT(523) + OR ROM64_INSTR_PT(525) OR ROM64_INSTR_PT(532) + OR ROM64_INSTR_PT(534) OR ROM64_INSTR_PT(535) + OR ROM64_INSTR_PT(537) OR ROM64_INSTR_PT(539) + OR ROM64_INSTR_PT(542) OR ROM64_INSTR_PT(544) + OR ROM64_INSTR_PT(545) OR ROM64_INSTR_PT(548) + OR ROM64_INSTR_PT(549) OR ROM64_INSTR_PT(552) + OR ROM64_INSTR_PT(553) OR ROM64_INSTR_PT(554) + OR ROM64_INSTR_PT(555) OR ROM64_INSTR_PT(558) + OR ROM64_INSTR_PT(568) OR ROM64_INSTR_PT(569) + OR ROM64_INSTR_PT(571) OR ROM64_INSTR_PT(575) + OR ROM64_INSTR_PT(576) OR ROM64_INSTR_PT(579) + OR ROM64_INSTR_PT(583) OR ROM64_INSTR_PT(584) + OR ROM64_INSTR_PT(588) OR ROM64_INSTR_PT(592) + OR ROM64_INSTR_PT(595) OR ROM64_INSTR_PT(596) + OR ROM64_INSTR_PT(600) OR ROM64_INSTR_PT(608) + OR ROM64_INSTR_PT(609) OR ROM64_INSTR_PT(612) + OR ROM64_INSTR_PT(613) OR ROM64_INSTR_PT(617) + OR ROM64_INSTR_PT(618) OR ROM64_INSTR_PT(623) + OR ROM64_INSTR_PT(628) OR ROM64_INSTR_PT(633) + OR ROM64_INSTR_PT(636) OR ROM64_INSTR_PT(637) + OR ROM64_INSTR_PT(639) OR ROM64_INSTR_PT(642) + OR ROM64_INSTR_PT(644) OR ROM64_INSTR_PT(646) + OR ROM64_INSTR_PT(649) OR ROM64_INSTR_PT(666) + OR ROM64_INSTR_PT(678) OR ROM64_INSTR_PT(682) + OR ROM64_INSTR_PT(691) OR ROM64_INSTR_PT(693) + OR ROM64_INSTR_PT(703) OR ROM64_INSTR_PT(739) + OR ROM64_INSTR_PT(744) OR ROM64_INSTR_PT(753) + OR ROM64_INSTR_PT(761) OR ROM64_INSTR_PT(769) + OR ROM64_INSTR_PT(776) OR ROM64_INSTR_PT(805) + OR ROM64_INSTR_PT(823) OR ROM64_INSTR_PT(856) + OR ROM64_INSTR_PT(864) OR ROM64_INSTR_PT(870) + ); +MQQ906:TEMPLATE(15) <= + (ROM64_INSTR_PT(9) OR ROM64_INSTR_PT(15) + OR ROM64_INSTR_PT(22) OR ROM64_INSTR_PT(53) + OR ROM64_INSTR_PT(57) OR ROM64_INSTR_PT(71) + OR ROM64_INSTR_PT(77) OR ROM64_INSTR_PT(80) + OR ROM64_INSTR_PT(83) OR ROM64_INSTR_PT(89) + OR ROM64_INSTR_PT(92) OR ROM64_INSTR_PT(96) + OR ROM64_INSTR_PT(106) OR ROM64_INSTR_PT(110) + OR ROM64_INSTR_PT(114) OR ROM64_INSTR_PT(116) + OR ROM64_INSTR_PT(121) OR ROM64_INSTR_PT(122) + OR ROM64_INSTR_PT(136) OR ROM64_INSTR_PT(148) + OR ROM64_INSTR_PT(158) OR ROM64_INSTR_PT(162) + OR ROM64_INSTR_PT(168) OR ROM64_INSTR_PT(170) + OR ROM64_INSTR_PT(173) OR ROM64_INSTR_PT(174) + OR ROM64_INSTR_PT(175) OR ROM64_INSTR_PT(203) + OR ROM64_INSTR_PT(211) OR ROM64_INSTR_PT(213) + OR ROM64_INSTR_PT(214) OR ROM64_INSTR_PT(218) + OR ROM64_INSTR_PT(219) OR ROM64_INSTR_PT(222) + OR ROM64_INSTR_PT(236) OR ROM64_INSTR_PT(240) + OR ROM64_INSTR_PT(272) OR ROM64_INSTR_PT(273) + OR ROM64_INSTR_PT(278) OR ROM64_INSTR_PT(284) + OR ROM64_INSTR_PT(294) OR ROM64_INSTR_PT(299) + OR ROM64_INSTR_PT(311) OR ROM64_INSTR_PT(350) + OR ROM64_INSTR_PT(353) OR ROM64_INSTR_PT(358) + OR ROM64_INSTR_PT(363) OR ROM64_INSTR_PT(370) + OR ROM64_INSTR_PT(371) OR ROM64_INSTR_PT(396) + OR ROM64_INSTR_PT(399) OR ROM64_INSTR_PT(408) + OR ROM64_INSTR_PT(416) OR ROM64_INSTR_PT(417) + OR ROM64_INSTR_PT(422) OR ROM64_INSTR_PT(425) + OR ROM64_INSTR_PT(429) OR ROM64_INSTR_PT(433) + OR ROM64_INSTR_PT(435) OR ROM64_INSTR_PT(440) + OR ROM64_INSTR_PT(442) OR ROM64_INSTR_PT(443) + OR ROM64_INSTR_PT(451) OR ROM64_INSTR_PT(458) + OR ROM64_INSTR_PT(461) OR ROM64_INSTR_PT(466) + OR ROM64_INSTR_PT(474) OR ROM64_INSTR_PT(480) + OR ROM64_INSTR_PT(506) OR ROM64_INSTR_PT(508) + OR ROM64_INSTR_PT(509) OR ROM64_INSTR_PT(519) + OR ROM64_INSTR_PT(532) OR ROM64_INSTR_PT(537) + OR ROM64_INSTR_PT(562) OR ROM64_INSTR_PT(564) + OR ROM64_INSTR_PT(581) OR ROM64_INSTR_PT(582) + OR ROM64_INSTR_PT(585) OR ROM64_INSTR_PT(596) + OR ROM64_INSTR_PT(599) OR ROM64_INSTR_PT(603) + OR ROM64_INSTR_PT(604) OR ROM64_INSTR_PT(613) + OR ROM64_INSTR_PT(614) OR ROM64_INSTR_PT(626) + OR ROM64_INSTR_PT(659) OR ROM64_INSTR_PT(664) + OR ROM64_INSTR_PT(691) OR ROM64_INSTR_PT(695) + OR ROM64_INSTR_PT(716) OR ROM64_INSTR_PT(731) + OR ROM64_INSTR_PT(832) OR ROM64_INSTR_PT(834) + OR ROM64_INSTR_PT(846) OR ROM64_INSTR_PT(854) + ); +MQQ907:TEMPLATE(16) <= + (ROM64_INSTR_PT(5) OR ROM64_INSTR_PT(10) + OR ROM64_INSTR_PT(17) OR ROM64_INSTR_PT(20) + OR ROM64_INSTR_PT(21) OR ROM64_INSTR_PT(34) + OR ROM64_INSTR_PT(39) OR ROM64_INSTR_PT(49) + OR ROM64_INSTR_PT(55) OR ROM64_INSTR_PT(64) + OR ROM64_INSTR_PT(75) OR ROM64_INSTR_PT(77) + OR ROM64_INSTR_PT(80) OR ROM64_INSTR_PT(83) + OR ROM64_INSTR_PT(89) OR ROM64_INSTR_PT(96) + OR ROM64_INSTR_PT(98) OR ROM64_INSTR_PT(99) + OR ROM64_INSTR_PT(104) OR ROM64_INSTR_PT(106) + OR ROM64_INSTR_PT(110) OR ROM64_INSTR_PT(113) + OR ROM64_INSTR_PT(114) OR ROM64_INSTR_PT(117) + OR ROM64_INSTR_PT(118) OR ROM64_INSTR_PT(121) + OR ROM64_INSTR_PT(127) OR ROM64_INSTR_PT(171) + OR ROM64_INSTR_PT(175) OR ROM64_INSTR_PT(188) + OR ROM64_INSTR_PT(191) OR ROM64_INSTR_PT(199) + OR ROM64_INSTR_PT(208) OR ROM64_INSTR_PT(214) + OR ROM64_INSTR_PT(217) OR ROM64_INSTR_PT(218) + OR ROM64_INSTR_PT(223) OR ROM64_INSTR_PT(226) + OR ROM64_INSTR_PT(252) OR ROM64_INSTR_PT(253) + OR ROM64_INSTR_PT(257) OR ROM64_INSTR_PT(264) + OR ROM64_INSTR_PT(268) OR ROM64_INSTR_PT(274) + OR ROM64_INSTR_PT(275) OR ROM64_INSTR_PT(280) + OR ROM64_INSTR_PT(283) OR ROM64_INSTR_PT(286) + OR ROM64_INSTR_PT(315) OR ROM64_INSTR_PT(322) + OR ROM64_INSTR_PT(331) OR ROM64_INSTR_PT(349) + OR ROM64_INSTR_PT(363) OR ROM64_INSTR_PT(369) + OR ROM64_INSTR_PT(371) OR ROM64_INSTR_PT(375) + OR ROM64_INSTR_PT(391) OR ROM64_INSTR_PT(397) + OR ROM64_INSTR_PT(401) OR ROM64_INSTR_PT(404) + OR ROM64_INSTR_PT(415) OR ROM64_INSTR_PT(422) + OR ROM64_INSTR_PT(427) OR ROM64_INSTR_PT(437) + OR ROM64_INSTR_PT(448) OR ROM64_INSTR_PT(466) + OR ROM64_INSTR_PT(472) OR ROM64_INSTR_PT(481) + OR ROM64_INSTR_PT(505) OR ROM64_INSTR_PT(521) + OR ROM64_INSTR_PT(523) OR ROM64_INSTR_PT(525) + OR ROM64_INSTR_PT(538) OR ROM64_INSTR_PT(540) + OR ROM64_INSTR_PT(558) OR ROM64_INSTR_PT(563) + OR ROM64_INSTR_PT(569) OR ROM64_INSTR_PT(582) + OR ROM64_INSTR_PT(584) OR ROM64_INSTR_PT(595) + OR ROM64_INSTR_PT(596) OR ROM64_INSTR_PT(597) + OR ROM64_INSTR_PT(598) OR ROM64_INSTR_PT(600) + OR ROM64_INSTR_PT(608) OR ROM64_INSTR_PT(613) + OR ROM64_INSTR_PT(618) OR ROM64_INSTR_PT(629) + OR ROM64_INSTR_PT(642) OR ROM64_INSTR_PT(644) + OR ROM64_INSTR_PT(744) OR ROM64_INSTR_PT(769) + OR ROM64_INSTR_PT(776) OR ROM64_INSTR_PT(870) + ); +MQQ908:TEMPLATE(17) <= + (ROM64_INSTR_PT(5) OR ROM64_INSTR_PT(17) + OR ROM64_INSTR_PT(20) OR ROM64_INSTR_PT(21) + OR ROM64_INSTR_PT(34) OR ROM64_INSTR_PT(38) + OR ROM64_INSTR_PT(39) OR ROM64_INSTR_PT(43) + OR ROM64_INSTR_PT(49) OR ROM64_INSTR_PT(55) + OR ROM64_INSTR_PT(61) OR ROM64_INSTR_PT(70) + OR ROM64_INSTR_PT(77) OR ROM64_INSTR_PT(78) + OR ROM64_INSTR_PT(80) OR ROM64_INSTR_PT(86) + OR ROM64_INSTR_PT(89) OR ROM64_INSTR_PT(90) + OR ROM64_INSTR_PT(98) OR ROM64_INSTR_PT(99) + OR ROM64_INSTR_PT(102) OR ROM64_INSTR_PT(104) + OR ROM64_INSTR_PT(106) OR ROM64_INSTR_PT(111) + OR ROM64_INSTR_PT(114) OR ROM64_INSTR_PT(118) + OR ROM64_INSTR_PT(121) OR ROM64_INSTR_PT(127) + OR ROM64_INSTR_PT(144) OR ROM64_INSTR_PT(168) + OR ROM64_INSTR_PT(173) OR ROM64_INSTR_PT(175) + OR ROM64_INSTR_PT(186) OR ROM64_INSTR_PT(188) + OR ROM64_INSTR_PT(191) OR ROM64_INSTR_PT(199) + OR ROM64_INSTR_PT(208) OR ROM64_INSTR_PT(215) + OR ROM64_INSTR_PT(219) OR ROM64_INSTR_PT(223) + OR ROM64_INSTR_PT(226) OR ROM64_INSTR_PT(238) + OR ROM64_INSTR_PT(252) OR ROM64_INSTR_PT(253) + OR ROM64_INSTR_PT(257) OR ROM64_INSTR_PT(270) + OR ROM64_INSTR_PT(271) OR ROM64_INSTR_PT(274) + OR ROM64_INSTR_PT(277) OR ROM64_INSTR_PT(280) + OR ROM64_INSTR_PT(282) OR ROM64_INSTR_PT(283) + OR ROM64_INSTR_PT(286) OR ROM64_INSTR_PT(287) + OR ROM64_INSTR_PT(293) OR ROM64_INSTR_PT(302) + OR ROM64_INSTR_PT(305) OR ROM64_INSTR_PT(322) + OR ROM64_INSTR_PT(329) OR ROM64_INSTR_PT(331) + OR ROM64_INSTR_PT(343) OR ROM64_INSTR_PT(349) + OR ROM64_INSTR_PT(361) OR ROM64_INSTR_PT(364) + OR ROM64_INSTR_PT(369) OR ROM64_INSTR_PT(383) + OR ROM64_INSTR_PT(385) OR ROM64_INSTR_PT(397) + OR ROM64_INSTR_PT(401) OR ROM64_INSTR_PT(406) + OR ROM64_INSTR_PT(408) OR ROM64_INSTR_PT(410) + OR ROM64_INSTR_PT(420) OR ROM64_INSTR_PT(422) + OR ROM64_INSTR_PT(424) OR ROM64_INSTR_PT(427) + OR ROM64_INSTR_PT(448) OR ROM64_INSTR_PT(466) + OR ROM64_INSTR_PT(472) OR ROM64_INSTR_PT(478) + OR ROM64_INSTR_PT(480) OR ROM64_INSTR_PT(481) + OR ROM64_INSTR_PT(482) OR ROM64_INSTR_PT(483) + OR ROM64_INSTR_PT(484) OR ROM64_INSTR_PT(485) + OR ROM64_INSTR_PT(493) OR ROM64_INSTR_PT(495) + OR ROM64_INSTR_PT(498) OR ROM64_INSTR_PT(508) + OR ROM64_INSTR_PT(511) OR ROM64_INSTR_PT(522) + OR ROM64_INSTR_PT(523) OR ROM64_INSTR_PT(534) + OR ROM64_INSTR_PT(535) OR ROM64_INSTR_PT(536) + OR ROM64_INSTR_PT(538) OR ROM64_INSTR_PT(548) + OR ROM64_INSTR_PT(549) OR ROM64_INSTR_PT(552) + OR ROM64_INSTR_PT(555) OR ROM64_INSTR_PT(563) + OR ROM64_INSTR_PT(575) OR ROM64_INSTR_PT(579) + OR ROM64_INSTR_PT(583) OR ROM64_INSTR_PT(584) + OR ROM64_INSTR_PT(588) OR ROM64_INSTR_PT(596) + OR ROM64_INSTR_PT(597) OR ROM64_INSTR_PT(599) + OR ROM64_INSTR_PT(603) OR ROM64_INSTR_PT(608) + OR ROM64_INSTR_PT(612) OR ROM64_INSTR_PT(613) + OR ROM64_INSTR_PT(614) OR ROM64_INSTR_PT(633) + OR ROM64_INSTR_PT(637) OR ROM64_INSTR_PT(639) + OR ROM64_INSTR_PT(642) OR ROM64_INSTR_PT(644) + OR ROM64_INSTR_PT(646) OR ROM64_INSTR_PT(666) + OR ROM64_INSTR_PT(678) OR ROM64_INSTR_PT(682) + OR ROM64_INSTR_PT(703) OR ROM64_INSTR_PT(870) + ); +MQQ909:TEMPLATE(18) <= + (ROM64_INSTR_PT(5) OR ROM64_INSTR_PT(20) + OR ROM64_INSTR_PT(21) OR ROM64_INSTR_PT(39) + OR ROM64_INSTR_PT(49) OR ROM64_INSTR_PT(77) + OR ROM64_INSTR_PT(80) OR ROM64_INSTR_PT(89) + OR ROM64_INSTR_PT(97) OR ROM64_INSTR_PT(98) + OR ROM64_INSTR_PT(106) OR ROM64_INSTR_PT(110) + OR ROM64_INSTR_PT(114) OR ROM64_INSTR_PT(118) + OR ROM64_INSTR_PT(172) OR ROM64_INSTR_PT(223) + OR ROM64_INSTR_PT(253) OR ROM64_INSTR_PT(273) + OR ROM64_INSTR_PT(280) OR ROM64_INSTR_PT(283) + OR ROM64_INSTR_PT(397) OR ROM64_INSTR_PT(401) + OR ROM64_INSTR_PT(422) OR ROM64_INSTR_PT(427) + OR ROM64_INSTR_PT(466) OR ROM64_INSTR_PT(472) + OR ROM64_INSTR_PT(523) OR ROM64_INSTR_PT(538) + OR ROM64_INSTR_PT(544) OR ROM64_INSTR_PT(563) + OR ROM64_INSTR_PT(584) OR ROM64_INSTR_PT(597) + OR ROM64_INSTR_PT(642) OR ROM64_INSTR_PT(723) + OR ROM64_INSTR_PT(724) OR ROM64_INSTR_PT(733) + ); +MQQ910:TEMPLATE(19) <= + (ROM64_INSTR_PT(5) OR ROM64_INSTR_PT(15) + OR ROM64_INSTR_PT(18) OR ROM64_INSTR_PT(20) + OR ROM64_INSTR_PT(21) OR ROM64_INSTR_PT(25) + OR ROM64_INSTR_PT(39) OR ROM64_INSTR_PT(42) + OR ROM64_INSTR_PT(45) OR ROM64_INSTR_PT(49) + OR ROM64_INSTR_PT(53) OR ROM64_INSTR_PT(57) + OR ROM64_INSTR_PT(73) OR ROM64_INSTR_PT(77) + OR ROM64_INSTR_PT(80) OR ROM64_INSTR_PT(84) + OR ROM64_INSTR_PT(97) OR ROM64_INSTR_PT(98) + OR ROM64_INSTR_PT(101) OR ROM64_INSTR_PT(106) + OR ROM64_INSTR_PT(109) OR ROM64_INSTR_PT(118) + OR ROM64_INSTR_PT(128) OR ROM64_INSTR_PT(145) + OR ROM64_INSTR_PT(157) OR ROM64_INSTR_PT(168) + OR ROM64_INSTR_PT(182) OR ROM64_INSTR_PT(203) + OR ROM64_INSTR_PT(205) OR ROM64_INSTR_PT(206) + OR ROM64_INSTR_PT(218) OR ROM64_INSTR_PT(219) + OR ROM64_INSTR_PT(223) OR ROM64_INSTR_PT(236) + OR ROM64_INSTR_PT(244) OR ROM64_INSTR_PT(253) + OR ROM64_INSTR_PT(254) OR ROM64_INSTR_PT(262) + OR ROM64_INSTR_PT(269) OR ROM64_INSTR_PT(272) + OR ROM64_INSTR_PT(273) OR ROM64_INSTR_PT(280) + OR ROM64_INSTR_PT(283) OR ROM64_INSTR_PT(284) + OR ROM64_INSTR_PT(290) OR ROM64_INSTR_PT(308) + OR ROM64_INSTR_PT(325) OR ROM64_INSTR_PT(348) + OR ROM64_INSTR_PT(361) OR ROM64_INSTR_PT(381) + OR ROM64_INSTR_PT(387) OR ROM64_INSTR_PT(388) + OR ROM64_INSTR_PT(397) OR ROM64_INSTR_PT(401) + OR ROM64_INSTR_PT(406) OR ROM64_INSTR_PT(409) + OR ROM64_INSTR_PT(419) OR ROM64_INSTR_PT(422) + OR ROM64_INSTR_PT(425) OR ROM64_INSTR_PT(427) + OR ROM64_INSTR_PT(429) OR ROM64_INSTR_PT(430) + OR ROM64_INSTR_PT(439) OR ROM64_INSTR_PT(440) + OR ROM64_INSTR_PT(451) OR ROM64_INSTR_PT(454) + OR ROM64_INSTR_PT(455) OR ROM64_INSTR_PT(460) + OR ROM64_INSTR_PT(466) OR ROM64_INSTR_PT(472) + OR ROM64_INSTR_PT(490) OR ROM64_INSTR_PT(506) + OR ROM64_INSTR_PT(510) OR ROM64_INSTR_PT(519) + OR ROM64_INSTR_PT(523) OR ROM64_INSTR_PT(530) + OR ROM64_INSTR_PT(532) OR ROM64_INSTR_PT(538) + OR ROM64_INSTR_PT(539) OR ROM64_INSTR_PT(542) + OR ROM64_INSTR_PT(553) OR ROM64_INSTR_PT(554) + OR ROM64_INSTR_PT(570) OR ROM64_INSTR_PT(577) + OR ROM64_INSTR_PT(580) OR ROM64_INSTR_PT(582) + OR ROM64_INSTR_PT(584) OR ROM64_INSTR_PT(597) + OR ROM64_INSTR_PT(611) OR ROM64_INSTR_PT(616) + OR ROM64_INSTR_PT(619) OR ROM64_INSTR_PT(636) + OR ROM64_INSTR_PT(642) OR ROM64_INSTR_PT(643) + OR ROM64_INSTR_PT(681) OR ROM64_INSTR_PT(723) + OR ROM64_INSTR_PT(724) OR ROM64_INSTR_PT(733) + OR ROM64_INSTR_PT(736) OR ROM64_INSTR_PT(770) + OR ROM64_INSTR_PT(813) OR ROM64_INSTR_PT(823) + OR ROM64_INSTR_PT(824)); +MQQ911:TEMPLATE(20) <= + (ROM64_INSTR_PT(5) OR ROM64_INSTR_PT(13) + OR ROM64_INSTR_PT(18) OR ROM64_INSTR_PT(21) + OR ROM64_INSTR_PT(35) OR ROM64_INSTR_PT(36) + OR ROM64_INSTR_PT(39) OR ROM64_INSTR_PT(42) + OR ROM64_INSTR_PT(45) OR ROM64_INSTR_PT(49) + OR ROM64_INSTR_PT(56) OR ROM64_INSTR_PT(98) + OR ROM64_INSTR_PT(118) OR ROM64_INSTR_PT(155) + OR ROM64_INSTR_PT(162) OR ROM64_INSTR_PT(196) + OR ROM64_INSTR_PT(216) OR ROM64_INSTR_PT(223) + OR ROM64_INSTR_PT(236) OR ROM64_INSTR_PT(253) + OR ROM64_INSTR_PT(261) OR ROM64_INSTR_PT(262) + OR ROM64_INSTR_PT(273) OR ROM64_INSTR_PT(280) + OR ROM64_INSTR_PT(283) OR ROM64_INSTR_PT(284) + OR ROM64_INSTR_PT(308) OR ROM64_INSTR_PT(325) + OR ROM64_INSTR_PT(353) OR ROM64_INSTR_PT(365) + OR ROM64_INSTR_PT(372) OR ROM64_INSTR_PT(388) + OR ROM64_INSTR_PT(395) OR ROM64_INSTR_PT(397) + OR ROM64_INSTR_PT(401) OR ROM64_INSTR_PT(405) + OR ROM64_INSTR_PT(422) OR ROM64_INSTR_PT(425) + OR ROM64_INSTR_PT(426) OR ROM64_INSTR_PT(427) + OR ROM64_INSTR_PT(429) OR ROM64_INSTR_PT(435) + OR ROM64_INSTR_PT(439) OR ROM64_INSTR_PT(451) + OR ROM64_INSTR_PT(454) OR ROM64_INSTR_PT(455) + OR ROM64_INSTR_PT(456) OR ROM64_INSTR_PT(458) + OR ROM64_INSTR_PT(466) OR ROM64_INSTR_PT(467) + OR ROM64_INSTR_PT(473) OR ROM64_INSTR_PT(475) + OR ROM64_INSTR_PT(488) OR ROM64_INSTR_PT(507) + OR ROM64_INSTR_PT(517) OR ROM64_INSTR_PT(520) + OR ROM64_INSTR_PT(523) OR ROM64_INSTR_PT(538) + OR ROM64_INSTR_PT(542) OR ROM64_INSTR_PT(544) + OR ROM64_INSTR_PT(564) OR ROM64_INSTR_PT(568) + OR ROM64_INSTR_PT(584) OR ROM64_INSTR_PT(586) + OR ROM64_INSTR_PT(587) OR ROM64_INSTR_PT(589) + OR ROM64_INSTR_PT(597) OR ROM64_INSTR_PT(617) + OR ROM64_INSTR_PT(619) OR ROM64_INSTR_PT(628) + OR ROM64_INSTR_PT(642) OR ROM64_INSTR_PT(681) + OR ROM64_INSTR_PT(693) OR ROM64_INSTR_PT(721) + OR ROM64_INSTR_PT(728) OR ROM64_INSTR_PT(735) + OR ROM64_INSTR_PT(738) OR ROM64_INSTR_PT(770) + OR ROM64_INSTR_PT(811) OR ROM64_INSTR_PT(823) + ); +MQQ912:TEMPLATE(21) <= + (ROM64_INSTR_PT(5) OR ROM64_INSTR_PT(6) + OR ROM64_INSTR_PT(9) OR ROM64_INSTR_PT(10) + OR ROM64_INSTR_PT(11) OR ROM64_INSTR_PT(21) + OR ROM64_INSTR_PT(22) OR ROM64_INSTR_PT(25) + OR ROM64_INSTR_PT(36) OR ROM64_INSTR_PT(39) + OR ROM64_INSTR_PT(43) OR ROM64_INSTR_PT(58) + OR ROM64_INSTR_PT(70) OR ROM64_INSTR_PT(71) + OR ROM64_INSTR_PT(76) OR ROM64_INSTR_PT(78) + OR ROM64_INSTR_PT(83) OR ROM64_INSTR_PT(86) + OR ROM64_INSTR_PT(93) OR ROM64_INSTR_PT(96) + OR ROM64_INSTR_PT(97) OR ROM64_INSTR_PT(98) + OR ROM64_INSTR_PT(117) OR ROM64_INSTR_PT(118) + OR ROM64_INSTR_PT(136) OR ROM64_INSTR_PT(148) + OR ROM64_INSTR_PT(154) OR ROM64_INSTR_PT(168) + OR ROM64_INSTR_PT(172) OR ROM64_INSTR_PT(180) + OR ROM64_INSTR_PT(182) OR ROM64_INSTR_PT(184) + OR ROM64_INSTR_PT(188) OR ROM64_INSTR_PT(194) + OR ROM64_INSTR_PT(201) OR ROM64_INSTR_PT(202) + OR ROM64_INSTR_PT(205) OR ROM64_INSTR_PT(214) + OR ROM64_INSTR_PT(216) OR ROM64_INSTR_PT(219) + OR ROM64_INSTR_PT(222) OR ROM64_INSTR_PT(223) + OR ROM64_INSTR_PT(229) OR ROM64_INSTR_PT(230) + OR ROM64_INSTR_PT(245) OR ROM64_INSTR_PT(253) + OR ROM64_INSTR_PT(257) OR ROM64_INSTR_PT(258) + OR ROM64_INSTR_PT(260) OR ROM64_INSTR_PT(261) + OR ROM64_INSTR_PT(264) OR ROM64_INSTR_PT(268) + OR ROM64_INSTR_PT(271) OR ROM64_INSTR_PT(273) + OR ROM64_INSTR_PT(275) OR ROM64_INSTR_PT(277) + OR ROM64_INSTR_PT(280) OR ROM64_INSTR_PT(283) + OR ROM64_INSTR_PT(298) OR ROM64_INSTR_PT(299) + OR ROM64_INSTR_PT(312) OR ROM64_INSTR_PT(315) + OR ROM64_INSTR_PT(348) OR ROM64_INSTR_PT(361) + OR ROM64_INSTR_PT(363) OR ROM64_INSTR_PT(365) + OR ROM64_INSTR_PT(371) OR ROM64_INSTR_PT(375) + OR ROM64_INSTR_PT(387) OR ROM64_INSTR_PT(388) + OR ROM64_INSTR_PT(391) OR ROM64_INSTR_PT(397) + OR ROM64_INSTR_PT(401) OR ROM64_INSTR_PT(404) + OR ROM64_INSTR_PT(406) OR ROM64_INSTR_PT(414) + OR ROM64_INSTR_PT(415) OR ROM64_INSTR_PT(424) + OR ROM64_INSTR_PT(427) OR ROM64_INSTR_PT(430) + OR ROM64_INSTR_PT(434) OR ROM64_INSTR_PT(437) + OR ROM64_INSTR_PT(438) OR ROM64_INSTR_PT(457) + OR ROM64_INSTR_PT(458) OR ROM64_INSTR_PT(463) + OR ROM64_INSTR_PT(497) OR ROM64_INSTR_PT(503) + OR ROM64_INSTR_PT(505) OR ROM64_INSTR_PT(509) + OR ROM64_INSTR_PT(510) OR ROM64_INSTR_PT(511) + OR ROM64_INSTR_PT(520) OR ROM64_INSTR_PT(521) + OR ROM64_INSTR_PT(523) OR ROM64_INSTR_PT(525) + OR ROM64_INSTR_PT(530) OR ROM64_INSTR_PT(531) + OR ROM64_INSTR_PT(535) OR ROM64_INSTR_PT(538) + OR ROM64_INSTR_PT(540) OR ROM64_INSTR_PT(544) + OR ROM64_INSTR_PT(545) OR ROM64_INSTR_PT(549) + OR ROM64_INSTR_PT(558) OR ROM64_INSTR_PT(569) + OR ROM64_INSTR_PT(570) OR ROM64_INSTR_PT(575) + OR ROM64_INSTR_PT(576) OR ROM64_INSTR_PT(579) + OR ROM64_INSTR_PT(580) OR ROM64_INSTR_PT(584) + OR ROM64_INSTR_PT(588) OR ROM64_INSTR_PT(592) + OR ROM64_INSTR_PT(595) OR ROM64_INSTR_PT(597) + OR ROM64_INSTR_PT(598) OR ROM64_INSTR_PT(617) + OR ROM64_INSTR_PT(618) OR ROM64_INSTR_PT(623) + OR ROM64_INSTR_PT(628) OR ROM64_INSTR_PT(629) + OR ROM64_INSTR_PT(663) OR ROM64_INSTR_PT(728) + OR ROM64_INSTR_PT(735) OR ROM64_INSTR_PT(738) + OR ROM64_INSTR_PT(822)); +MQQ913:TEMPLATE(22) <= + (ROM64_INSTR_PT(5) OR ROM64_INSTR_PT(8) + OR ROM64_INSTR_PT(9) OR ROM64_INSTR_PT(11) + OR ROM64_INSTR_PT(13) OR ROM64_INSTR_PT(15) + OR ROM64_INSTR_PT(18) OR ROM64_INSTR_PT(21) + OR ROM64_INSTR_PT(22) OR ROM64_INSTR_PT(25) + OR ROM64_INSTR_PT(30) OR ROM64_INSTR_PT(36) + OR ROM64_INSTR_PT(39) OR ROM64_INSTR_PT(43) + OR ROM64_INSTR_PT(53) OR ROM64_INSTR_PT(56) + OR ROM64_INSTR_PT(57) OR ROM64_INSTR_PT(71) + OR ROM64_INSTR_PT(73) OR ROM64_INSTR_PT(76) + OR ROM64_INSTR_PT(78) OR ROM64_INSTR_PT(93) + OR ROM64_INSTR_PT(97) OR ROM64_INSTR_PT(98) + OR ROM64_INSTR_PT(101) OR ROM64_INSTR_PT(113) + OR ROM64_INSTR_PT(118) OR ROM64_INSTR_PT(121) + OR ROM64_INSTR_PT(128) OR ROM64_INSTR_PT(133) + OR ROM64_INSTR_PT(136) OR ROM64_INSTR_PT(148) + OR ROM64_INSTR_PT(155) OR ROM64_INSTR_PT(157) + OR ROM64_INSTR_PT(162) OR ROM64_INSTR_PT(164) + OR ROM64_INSTR_PT(171) OR ROM64_INSTR_PT(172) + OR ROM64_INSTR_PT(175) OR ROM64_INSTR_PT(180) + OR ROM64_INSTR_PT(184) OR ROM64_INSTR_PT(188) + OR ROM64_INSTR_PT(196) OR ROM64_INSTR_PT(201) + OR ROM64_INSTR_PT(202) OR ROM64_INSTR_PT(203) + OR ROM64_INSTR_PT(206) OR ROM64_INSTR_PT(211) + OR ROM64_INSTR_PT(216) OR ROM64_INSTR_PT(218) + OR ROM64_INSTR_PT(222) OR ROM64_INSTR_PT(223) + OR ROM64_INSTR_PT(229) OR ROM64_INSTR_PT(230) + OR ROM64_INSTR_PT(244) OR ROM64_INSTR_PT(245) + OR ROM64_INSTR_PT(253) OR ROM64_INSTR_PT(257) + OR ROM64_INSTR_PT(261) OR ROM64_INSTR_PT(272) + OR ROM64_INSTR_PT(273) OR ROM64_INSTR_PT(280) + OR ROM64_INSTR_PT(283) OR ROM64_INSTR_PT(298) + OR ROM64_INSTR_PT(299) OR ROM64_INSTR_PT(312) + OR ROM64_INSTR_PT(325) OR ROM64_INSTR_PT(353) + OR ROM64_INSTR_PT(365) OR ROM64_INSTR_PT(372) + OR ROM64_INSTR_PT(381) OR ROM64_INSTR_PT(388) + OR ROM64_INSTR_PT(395) OR ROM64_INSTR_PT(397) + OR ROM64_INSTR_PT(401) OR ROM64_INSTR_PT(405) + OR ROM64_INSTR_PT(414) OR ROM64_INSTR_PT(426) + OR ROM64_INSTR_PT(427) OR ROM64_INSTR_PT(434) + OR ROM64_INSTR_PT(438) OR ROM64_INSTR_PT(439) + OR ROM64_INSTR_PT(440) OR ROM64_INSTR_PT(443) + OR ROM64_INSTR_PT(454) OR ROM64_INSTR_PT(455) + OR ROM64_INSTR_PT(456) OR ROM64_INSTR_PT(457) + OR ROM64_INSTR_PT(458) OR ROM64_INSTR_PT(460) + OR ROM64_INSTR_PT(463) OR ROM64_INSTR_PT(467) + OR ROM64_INSTR_PT(473) OR ROM64_INSTR_PT(475) + OR ROM64_INSTR_PT(481) OR ROM64_INSTR_PT(488) + OR ROM64_INSTR_PT(490) OR ROM64_INSTR_PT(497) + OR ROM64_INSTR_PT(503) OR ROM64_INSTR_PT(506) + OR ROM64_INSTR_PT(509) OR ROM64_INSTR_PT(514) + OR ROM64_INSTR_PT(519) OR ROM64_INSTR_PT(520) + OR ROM64_INSTR_PT(523) OR ROM64_INSTR_PT(532) + OR ROM64_INSTR_PT(538) OR ROM64_INSTR_PT(539) + OR ROM64_INSTR_PT(540) OR ROM64_INSTR_PT(544) + OR ROM64_INSTR_PT(545) OR ROM64_INSTR_PT(553) + OR ROM64_INSTR_PT(554) OR ROM64_INSTR_PT(566) + OR ROM64_INSTR_PT(568) OR ROM64_INSTR_PT(576) + OR ROM64_INSTR_PT(581) OR ROM64_INSTR_PT(582) + OR ROM64_INSTR_PT(584) OR ROM64_INSTR_PT(586) + OR ROM64_INSTR_PT(587) OR ROM64_INSTR_PT(589) + OR ROM64_INSTR_PT(592) OR ROM64_INSTR_PT(596) + OR ROM64_INSTR_PT(597) OR ROM64_INSTR_PT(598) + OR ROM64_INSTR_PT(604) OR ROM64_INSTR_PT(607) + OR ROM64_INSTR_PT(611) OR ROM64_INSTR_PT(613) + OR ROM64_INSTR_PT(617) OR ROM64_INSTR_PT(625) + OR ROM64_INSTR_PT(628) OR ROM64_INSTR_PT(636) + OR ROM64_INSTR_PT(643) OR ROM64_INSTR_PT(655) + OR ROM64_INSTR_PT(663) OR ROM64_INSTR_PT(681) + OR ROM64_INSTR_PT(698) OR ROM64_INSTR_PT(713) + OR ROM64_INSTR_PT(723) OR ROM64_INSTR_PT(724) + OR ROM64_INSTR_PT(728) OR ROM64_INSTR_PT(733) + OR ROM64_INSTR_PT(735) OR ROM64_INSTR_PT(738) + OR ROM64_INSTR_PT(822) OR ROM64_INSTR_PT(824) + OR ROM64_INSTR_PT(846) OR ROM64_INSTR_PT(854) + ); +MQQ914:TEMPLATE(23) <= + (ROM64_INSTR_PT(5) OR ROM64_INSTR_PT(6) + OR ROM64_INSTR_PT(13) OR ROM64_INSTR_PT(25) + OR ROM64_INSTR_PT(36) OR ROM64_INSTR_PT(39) + OR ROM64_INSTR_PT(56) OR ROM64_INSTR_PT(57) + OR ROM64_INSTR_PT(73) OR ROM64_INSTR_PT(89) + OR ROM64_INSTR_PT(93) OR ROM64_INSTR_PT(98) + OR ROM64_INSTR_PT(100) OR ROM64_INSTR_PT(101) + OR ROM64_INSTR_PT(110) OR ROM64_INSTR_PT(114) + OR ROM64_INSTR_PT(124) OR ROM64_INSTR_PT(128) + OR ROM64_INSTR_PT(137) OR ROM64_INSTR_PT(155) + OR ROM64_INSTR_PT(157) OR ROM64_INSTR_PT(162) + OR ROM64_INSTR_PT(168) OR ROM64_INSTR_PT(180) + OR ROM64_INSTR_PT(184) OR ROM64_INSTR_PT(194) + OR ROM64_INSTR_PT(201) OR ROM64_INSTR_PT(202) + OR ROM64_INSTR_PT(203) OR ROM64_INSTR_PT(206) + OR ROM64_INSTR_PT(216) OR ROM64_INSTR_PT(218) + OR ROM64_INSTR_PT(219) OR ROM64_INSTR_PT(229) + OR ROM64_INSTR_PT(230) OR ROM64_INSTR_PT(244) + OR ROM64_INSTR_PT(245) OR ROM64_INSTR_PT(253) + OR ROM64_INSTR_PT(258) OR ROM64_INSTR_PT(260) + OR ROM64_INSTR_PT(261) OR ROM64_INSTR_PT(263) + OR ROM64_INSTR_PT(277) OR ROM64_INSTR_PT(283) + OR ROM64_INSTR_PT(285) OR ROM64_INSTR_PT(297) + OR ROM64_INSTR_PT(312) OR ROM64_INSTR_PT(319) + OR ROM64_INSTR_PT(353) OR ROM64_INSTR_PT(361) + OR ROM64_INSTR_PT(365) OR ROM64_INSTR_PT(372) + OR ROM64_INSTR_PT(379) OR ROM64_INSTR_PT(381) + OR ROM64_INSTR_PT(388) OR ROM64_INSTR_PT(395) + OR ROM64_INSTR_PT(401) OR ROM64_INSTR_PT(405) + OR ROM64_INSTR_PT(406) OR ROM64_INSTR_PT(413) + OR ROM64_INSTR_PT(426) OR ROM64_INSTR_PT(434) + OR ROM64_INSTR_PT(438) OR ROM64_INSTR_PT(446) + OR ROM64_INSTR_PT(456) OR ROM64_INSTR_PT(457) + OR ROM64_INSTR_PT(458) OR ROM64_INSTR_PT(460) + OR ROM64_INSTR_PT(467) OR ROM64_INSTR_PT(473) + OR ROM64_INSTR_PT(475) OR ROM64_INSTR_PT(488) + OR ROM64_INSTR_PT(490) OR ROM64_INSTR_PT(503) + OR ROM64_INSTR_PT(504) OR ROM64_INSTR_PT(506) + OR ROM64_INSTR_PT(517) OR ROM64_INSTR_PT(520) + OR ROM64_INSTR_PT(531) OR ROM64_INSTR_PT(535) + OR ROM64_INSTR_PT(538) OR ROM64_INSTR_PT(539) + OR ROM64_INSTR_PT(545) OR ROM64_INSTR_PT(546) + OR ROM64_INSTR_PT(549) OR ROM64_INSTR_PT(553) + OR ROM64_INSTR_PT(554) OR ROM64_INSTR_PT(559) + OR ROM64_INSTR_PT(563) OR ROM64_INSTR_PT(568) + OR ROM64_INSTR_PT(575) OR ROM64_INSTR_PT(582) + OR ROM64_INSTR_PT(592) OR ROM64_INSTR_PT(597) + OR ROM64_INSTR_PT(606) OR ROM64_INSTR_PT(611) + OR ROM64_INSTR_PT(615) OR ROM64_INSTR_PT(617) + OR ROM64_INSTR_PT(623) OR ROM64_INSTR_PT(628) + OR ROM64_INSTR_PT(636) OR ROM64_INSTR_PT(643) + OR ROM64_INSTR_PT(663) OR ROM64_INSTR_PT(693) + OR ROM64_INSTR_PT(717) OR ROM64_INSTR_PT(723) + OR ROM64_INSTR_PT(724) OR ROM64_INSTR_PT(728) + OR ROM64_INSTR_PT(733) OR ROM64_INSTR_PT(735) + OR ROM64_INSTR_PT(738) OR ROM64_INSTR_PT(822) + OR ROM64_INSTR_PT(824) OR ROM64_INSTR_PT(846) + ); +MQQ915:TEMPLATE(24) <= + (ROM64_INSTR_PT(4) OR ROM64_INSTR_PT(5) + OR ROM64_INSTR_PT(6) OR ROM64_INSTR_PT(11) + OR ROM64_INSTR_PT(14) OR ROM64_INSTR_PT(30) + OR ROM64_INSTR_PT(36) OR ROM64_INSTR_PT(41) + OR ROM64_INSTR_PT(45) OR ROM64_INSTR_PT(51) + OR ROM64_INSTR_PT(77) OR ROM64_INSTR_PT(80) + OR ROM64_INSTR_PT(93) OR ROM64_INSTR_PT(98) + OR ROM64_INSTR_PT(100) OR ROM64_INSTR_PT(105) + OR ROM64_INSTR_PT(106) OR ROM64_INSTR_PT(115) + OR ROM64_INSTR_PT(124) OR ROM64_INSTR_PT(137) + OR ROM64_INSTR_PT(140) OR ROM64_INSTR_PT(143) + OR ROM64_INSTR_PT(153) OR ROM64_INSTR_PT(158) + OR ROM64_INSTR_PT(170) OR ROM64_INSTR_PT(172) + OR ROM64_INSTR_PT(184) OR ROM64_INSTR_PT(185) + OR ROM64_INSTR_PT(194) OR ROM64_INSTR_PT(202) + OR ROM64_INSTR_PT(204) OR ROM64_INSTR_PT(216) + OR ROM64_INSTR_PT(218) OR ROM64_INSTR_PT(229) + OR ROM64_INSTR_PT(230) OR ROM64_INSTR_PT(241) + OR ROM64_INSTR_PT(253) OR ROM64_INSTR_PT(258) + OR ROM64_INSTR_PT(260) OR ROM64_INSTR_PT(261) + OR ROM64_INSTR_PT(262) OR ROM64_INSTR_PT(263) + OR ROM64_INSTR_PT(277) OR ROM64_INSTR_PT(278) + OR ROM64_INSTR_PT(283) OR ROM64_INSTR_PT(285) + OR ROM64_INSTR_PT(294) OR ROM64_INSTR_PT(297) + OR ROM64_INSTR_PT(308) OR ROM64_INSTR_PT(311) + OR ROM64_INSTR_PT(319) OR ROM64_INSTR_PT(348) + OR ROM64_INSTR_PT(365) OR ROM64_INSTR_PT(366) + OR ROM64_INSTR_PT(379) OR ROM64_INSTR_PT(387) + OR ROM64_INSTR_PT(394) OR ROM64_INSTR_PT(401) + OR ROM64_INSTR_PT(413) OR ROM64_INSTR_PT(418) + OR ROM64_INSTR_PT(428) OR ROM64_INSTR_PT(430) + OR ROM64_INSTR_PT(432) OR ROM64_INSTR_PT(433) + OR ROM64_INSTR_PT(434) OR ROM64_INSTR_PT(438) + OR ROM64_INSTR_PT(441) OR ROM64_INSTR_PT(446) + OR ROM64_INSTR_PT(453) OR ROM64_INSTR_PT(458) + OR ROM64_INSTR_PT(496) OR ROM64_INSTR_PT(503) + OR ROM64_INSTR_PT(504) OR ROM64_INSTR_PT(512) + OR ROM64_INSTR_PT(520) OR ROM64_INSTR_PT(530) + OR ROM64_INSTR_PT(531) OR ROM64_INSTR_PT(535) + OR ROM64_INSTR_PT(544) OR ROM64_INSTR_PT(545) + OR ROM64_INSTR_PT(546) OR ROM64_INSTR_PT(549) + OR ROM64_INSTR_PT(557) OR ROM64_INSTR_PT(559) + OR ROM64_INSTR_PT(564) OR ROM64_INSTR_PT(575) + OR ROM64_INSTR_PT(576) OR ROM64_INSTR_PT(580) + OR ROM64_INSTR_PT(582) OR ROM64_INSTR_PT(591) + OR ROM64_INSTR_PT(597) OR ROM64_INSTR_PT(606) + OR ROM64_INSTR_PT(615) OR ROM64_INSTR_PT(617) + OR ROM64_INSTR_PT(619) OR ROM64_INSTR_PT(623) + OR ROM64_INSTR_PT(627) OR ROM64_INSTR_PT(628) + OR ROM64_INSTR_PT(645) OR ROM64_INSTR_PT(663) + OR ROM64_INSTR_PT(693) OR ROM64_INSTR_PT(705) + OR ROM64_INSTR_PT(736) OR ROM64_INSTR_PT(753) + OR ROM64_INSTR_PT(770) OR ROM64_INSTR_PT(822) + OR ROM64_INSTR_PT(846)); +MQQ916:TEMPLATE(25) <= + (ROM64_INSTR_PT(5) OR ROM64_INSTR_PT(6) + OR ROM64_INSTR_PT(13) OR ROM64_INSTR_PT(21) + OR ROM64_INSTR_PT(25) OR ROM64_INSTR_PT(36) + OR ROM64_INSTR_PT(42) OR ROM64_INSTR_PT(56) + OR ROM64_INSTR_PT(57) OR ROM64_INSTR_PT(73) + OR ROM64_INSTR_PT(97) OR ROM64_INSTR_PT(98) + OR ROM64_INSTR_PT(101) OR ROM64_INSTR_PT(118) + OR ROM64_INSTR_PT(125) OR ROM64_INSTR_PT(128) + OR ROM64_INSTR_PT(134) OR ROM64_INSTR_PT(143) + OR ROM64_INSTR_PT(155) OR ROM64_INSTR_PT(157) + OR ROM64_INSTR_PT(158) OR ROM64_INSTR_PT(162) + OR ROM64_INSTR_PT(168) OR ROM64_INSTR_PT(170) + OR ROM64_INSTR_PT(172) OR ROM64_INSTR_PT(180) + OR ROM64_INSTR_PT(182) OR ROM64_INSTR_PT(184) + OR ROM64_INSTR_PT(194) OR ROM64_INSTR_PT(196) + OR ROM64_INSTR_PT(202) OR ROM64_INSTR_PT(203) + OR ROM64_INSTR_PT(206) OR ROM64_INSTR_PT(216) + OR ROM64_INSTR_PT(219) OR ROM64_INSTR_PT(223) + OR ROM64_INSTR_PT(229) OR ROM64_INSTR_PT(230) + OR ROM64_INSTR_PT(244) OR ROM64_INSTR_PT(253) + OR ROM64_INSTR_PT(260) OR ROM64_INSTR_PT(261) + OR ROM64_INSTR_PT(277) OR ROM64_INSTR_PT(278) + OR ROM64_INSTR_PT(280) OR ROM64_INSTR_PT(283) + OR ROM64_INSTR_PT(294) OR ROM64_INSTR_PT(311) + OR ROM64_INSTR_PT(339) OR ROM64_INSTR_PT(348) + OR ROM64_INSTR_PT(353) OR ROM64_INSTR_PT(361) + OR ROM64_INSTR_PT(365) OR ROM64_INSTR_PT(366) + OR ROM64_INSTR_PT(372) OR ROM64_INSTR_PT(381) + OR ROM64_INSTR_PT(387) OR ROM64_INSTR_PT(395) + OR ROM64_INSTR_PT(397) OR ROM64_INSTR_PT(401) + OR ROM64_INSTR_PT(405) OR ROM64_INSTR_PT(406) + OR ROM64_INSTR_PT(422) OR ROM64_INSTR_PT(426) + OR ROM64_INSTR_PT(427) OR ROM64_INSTR_PT(430) + OR ROM64_INSTR_PT(433) OR ROM64_INSTR_PT(434) + OR ROM64_INSTR_PT(456) OR ROM64_INSTR_PT(458) + OR ROM64_INSTR_PT(460) OR ROM64_INSTR_PT(466) + OR ROM64_INSTR_PT(467) OR ROM64_INSTR_PT(473) + OR ROM64_INSTR_PT(475) OR ROM64_INSTR_PT(488) + OR ROM64_INSTR_PT(490) OR ROM64_INSTR_PT(503) + OR ROM64_INSTR_PT(506) OR ROM64_INSTR_PT(507) + OR ROM64_INSTR_PT(517) OR ROM64_INSTR_PT(520) + OR ROM64_INSTR_PT(523) OR ROM64_INSTR_PT(530) + OR ROM64_INSTR_PT(531) OR ROM64_INSTR_PT(535) + OR ROM64_INSTR_PT(539) OR ROM64_INSTR_PT(542) + OR ROM64_INSTR_PT(545) OR ROM64_INSTR_PT(549) + OR ROM64_INSTR_PT(553) OR ROM64_INSTR_PT(554) + OR ROM64_INSTR_PT(557) OR ROM64_INSTR_PT(568) + OR ROM64_INSTR_PT(575) OR ROM64_INSTR_PT(576) + OR ROM64_INSTR_PT(580) OR ROM64_INSTR_PT(584) + OR ROM64_INSTR_PT(585) OR ROM64_INSTR_PT(592) + OR ROM64_INSTR_PT(597) OR ROM64_INSTR_PT(611) + OR ROM64_INSTR_PT(617) OR ROM64_INSTR_PT(626) + OR ROM64_INSTR_PT(632) OR ROM64_INSTR_PT(636) + OR ROM64_INSTR_PT(642) OR ROM64_INSTR_PT(643) + OR ROM64_INSTR_PT(649) OR ROM64_INSTR_PT(655) + OR ROM64_INSTR_PT(664) OR ROM64_INSTR_PT(693) + OR ROM64_INSTR_PT(702) OR ROM64_INSTR_PT(713) + OR ROM64_INSTR_PT(736) OR ROM64_INSTR_PT(739) + OR ROM64_INSTR_PT(753) OR ROM64_INSTR_PT(798) + OR ROM64_INSTR_PT(822) OR ROM64_INSTR_PT(823) + OR ROM64_INSTR_PT(824) OR ROM64_INSTR_PT(832) + ); +MQQ917:TEMPLATE(26) <= + (ROM64_INSTR_PT(4) OR ROM64_INSTR_PT(5) + OR ROM64_INSTR_PT(6) OR ROM64_INSTR_PT(7) + OR ROM64_INSTR_PT(9) OR ROM64_INSTR_PT(11) + OR ROM64_INSTR_PT(14) OR ROM64_INSTR_PT(21) + OR ROM64_INSTR_PT(22) OR ROM64_INSTR_PT(25) + OR ROM64_INSTR_PT(30) OR ROM64_INSTR_PT(35) + OR ROM64_INSTR_PT(36) OR ROM64_INSTR_PT(38) + OR ROM64_INSTR_PT(41) OR ROM64_INSTR_PT(43) + OR ROM64_INSTR_PT(45) OR ROM64_INSTR_PT(50) + OR ROM64_INSTR_PT(51) OR ROM64_INSTR_PT(52) + OR ROM64_INSTR_PT(56) OR ROM64_INSTR_PT(57) + OR ROM64_INSTR_PT(58) OR ROM64_INSTR_PT(61) + OR ROM64_INSTR_PT(68) OR ROM64_INSTR_PT(69) + OR ROM64_INSTR_PT(70) OR ROM64_INSTR_PT(71) + OR ROM64_INSTR_PT(73) OR ROM64_INSTR_PT(76) + OR ROM64_INSTR_PT(78) OR ROM64_INSTR_PT(82) + OR ROM64_INSTR_PT(83) OR ROM64_INSTR_PT(84) + OR ROM64_INSTR_PT(86) OR ROM64_INSTR_PT(90) + OR ROM64_INSTR_PT(92) OR ROM64_INSTR_PT(93) + OR ROM64_INSTR_PT(95) OR ROM64_INSTR_PT(97) + OR ROM64_INSTR_PT(98) OR ROM64_INSTR_PT(100) + OR ROM64_INSTR_PT(101) OR ROM64_INSTR_PT(102) + OR ROM64_INSTR_PT(105) OR ROM64_INSTR_PT(108) + OR ROM64_INSTR_PT(109) OR ROM64_INSTR_PT(115) + OR ROM64_INSTR_PT(116) OR ROM64_INSTR_PT(117) + OR ROM64_INSTR_PT(118) OR ROM64_INSTR_PT(124) + OR ROM64_INSTR_PT(128) OR ROM64_INSTR_PT(132) + OR ROM64_INSTR_PT(136) OR ROM64_INSTR_PT(137) + OR ROM64_INSTR_PT(140) OR ROM64_INSTR_PT(143) + OR ROM64_INSTR_PT(144) OR ROM64_INSTR_PT(145) + OR ROM64_INSTR_PT(148) OR ROM64_INSTR_PT(153) + OR ROM64_INSTR_PT(154) OR ROM64_INSTR_PT(155) + OR ROM64_INSTR_PT(157) OR ROM64_INSTR_PT(158) + OR ROM64_INSTR_PT(162) OR ROM64_INSTR_PT(169) + OR ROM64_INSTR_PT(172) OR ROM64_INSTR_PT(174) + OR ROM64_INSTR_PT(177) OR ROM64_INSTR_PT(180) + OR ROM64_INSTR_PT(181) OR ROM64_INSTR_PT(183) + OR ROM64_INSTR_PT(185) OR ROM64_INSTR_PT(186) + OR ROM64_INSTR_PT(188) OR ROM64_INSTR_PT(194) + OR ROM64_INSTR_PT(196) OR ROM64_INSTR_PT(201) + OR ROM64_INSTR_PT(203) OR ROM64_INSTR_PT(204) + OR ROM64_INSTR_PT(205) OR ROM64_INSTR_PT(206) + OR ROM64_INSTR_PT(215) OR ROM64_INSTR_PT(216) + OR ROM64_INSTR_PT(218) OR ROM64_INSTR_PT(222) + OR ROM64_INSTR_PT(223) OR ROM64_INSTR_PT(226) + OR ROM64_INSTR_PT(233) OR ROM64_INSTR_PT(238) + OR ROM64_INSTR_PT(241) OR ROM64_INSTR_PT(243) + OR ROM64_INSTR_PT(244) OR ROM64_INSTR_PT(245) + OR ROM64_INSTR_PT(249) OR ROM64_INSTR_PT(253) + OR ROM64_INSTR_PT(254) OR ROM64_INSTR_PT(257) + OR ROM64_INSTR_PT(258) OR ROM64_INSTR_PT(260) + OR ROM64_INSTR_PT(261) OR ROM64_INSTR_PT(263) + OR ROM64_INSTR_PT(264) OR ROM64_INSTR_PT(265) + OR ROM64_INSTR_PT(268) OR ROM64_INSTR_PT(269) + OR ROM64_INSTR_PT(270) OR ROM64_INSTR_PT(271) + OR ROM64_INSTR_PT(273) OR ROM64_INSTR_PT(275) + OR ROM64_INSTR_PT(276) OR ROM64_INSTR_PT(277) + OR ROM64_INSTR_PT(280) OR ROM64_INSTR_PT(282) + OR ROM64_INSTR_PT(283) OR ROM64_INSTR_PT(284) + OR ROM64_INSTR_PT(285) OR ROM64_INSTR_PT(287) + OR ROM64_INSTR_PT(290) OR ROM64_INSTR_PT(293) + OR ROM64_INSTR_PT(294) OR ROM64_INSTR_PT(297) + OR ROM64_INSTR_PT(298) OR ROM64_INSTR_PT(299) + OR ROM64_INSTR_PT(302) OR ROM64_INSTR_PT(305) + OR ROM64_INSTR_PT(308) OR ROM64_INSTR_PT(311) + OR ROM64_INSTR_PT(312) OR ROM64_INSTR_PT(315) + OR ROM64_INSTR_PT(319) OR ROM64_INSTR_PT(339) + OR ROM64_INSTR_PT(348) OR ROM64_INSTR_PT(350) + OR ROM64_INSTR_PT(353) OR ROM64_INSTR_PT(355) + OR ROM64_INSTR_PT(358) OR ROM64_INSTR_PT(364) + OR ROM64_INSTR_PT(365) OR ROM64_INSTR_PT(367) + OR ROM64_INSTR_PT(372) OR ROM64_INSTR_PT(374) + OR ROM64_INSTR_PT(375) OR ROM64_INSTR_PT(378) + OR ROM64_INSTR_PT(379) OR ROM64_INSTR_PT(381) + OR ROM64_INSTR_PT(383) OR ROM64_INSTR_PT(384) + OR ROM64_INSTR_PT(385) OR ROM64_INSTR_PT(388) + OR ROM64_INSTR_PT(391) OR ROM64_INSTR_PT(394) + OR ROM64_INSTR_PT(395) OR ROM64_INSTR_PT(397) + OR ROM64_INSTR_PT(401) OR ROM64_INSTR_PT(403) + OR ROM64_INSTR_PT(404) OR ROM64_INSTR_PT(405) + OR ROM64_INSTR_PT(409) OR ROM64_INSTR_PT(410) + OR ROM64_INSTR_PT(413) OR ROM64_INSTR_PT(414) + OR ROM64_INSTR_PT(415) OR ROM64_INSTR_PT(418) + OR ROM64_INSTR_PT(419) OR ROM64_INSTR_PT(424) + OR ROM64_INSTR_PT(425) OR ROM64_INSTR_PT(426) + OR ROM64_INSTR_PT(427) OR ROM64_INSTR_PT(428) + OR ROM64_INSTR_PT(429) OR ROM64_INSTR_PT(430) + OR ROM64_INSTR_PT(432) OR ROM64_INSTR_PT(435) + OR ROM64_INSTR_PT(437) OR ROM64_INSTR_PT(438) + OR ROM64_INSTR_PT(441) OR ROM64_INSTR_PT(445) + OR ROM64_INSTR_PT(446) OR ROM64_INSTR_PT(451) + OR ROM64_INSTR_PT(453) OR ROM64_INSTR_PT(456) + OR ROM64_INSTR_PT(457) OR ROM64_INSTR_PT(458) + OR ROM64_INSTR_PT(460) OR ROM64_INSTR_PT(461) + OR ROM64_INSTR_PT(463) OR ROM64_INSTR_PT(467) + OR ROM64_INSTR_PT(473) OR ROM64_INSTR_PT(475) + OR ROM64_INSTR_PT(478) OR ROM64_INSTR_PT(481) + OR ROM64_INSTR_PT(482) OR ROM64_INSTR_PT(484) + OR ROM64_INSTR_PT(485) OR ROM64_INSTR_PT(488) + OR ROM64_INSTR_PT(490) OR ROM64_INSTR_PT(493) + OR ROM64_INSTR_PT(495) OR ROM64_INSTR_PT(496) + OR ROM64_INSTR_PT(497) OR ROM64_INSTR_PT(504) + OR ROM64_INSTR_PT(505) OR ROM64_INSTR_PT(506) + OR ROM64_INSTR_PT(509) OR ROM64_INSTR_PT(510) + OR ROM64_INSTR_PT(511) OR ROM64_INSTR_PT(512) + OR ROM64_INSTR_PT(517) OR ROM64_INSTR_PT(520) + OR ROM64_INSTR_PT(521) OR ROM64_INSTR_PT(522) + OR ROM64_INSTR_PT(523) OR ROM64_INSTR_PT(525) + OR ROM64_INSTR_PT(530) OR ROM64_INSTR_PT(531) + OR ROM64_INSTR_PT(534) OR ROM64_INSTR_PT(535) + OR ROM64_INSTR_PT(539) OR ROM64_INSTR_PT(540) + OR ROM64_INSTR_PT(544) OR ROM64_INSTR_PT(546) + OR ROM64_INSTR_PT(549) OR ROM64_INSTR_PT(552) + OR ROM64_INSTR_PT(553) OR ROM64_INSTR_PT(554) + OR ROM64_INSTR_PT(555) OR ROM64_INSTR_PT(557) + OR ROM64_INSTR_PT(558) OR ROM64_INSTR_PT(559) + OR ROM64_INSTR_PT(563) OR ROM64_INSTR_PT(564) + OR ROM64_INSTR_PT(568) OR ROM64_INSTR_PT(569) + OR ROM64_INSTR_PT(570) OR ROM64_INSTR_PT(571) + OR ROM64_INSTR_PT(575) OR ROM64_INSTR_PT(576) + OR ROM64_INSTR_PT(577) OR ROM64_INSTR_PT(579) + OR ROM64_INSTR_PT(580) OR ROM64_INSTR_PT(582) + OR ROM64_INSTR_PT(583) OR ROM64_INSTR_PT(584) + OR ROM64_INSTR_PT(588) OR ROM64_INSTR_PT(591) + OR ROM64_INSTR_PT(592) OR ROM64_INSTR_PT(595) + OR ROM64_INSTR_PT(597) OR ROM64_INSTR_PT(598) + OR ROM64_INSTR_PT(606) OR ROM64_INSTR_PT(608) + OR ROM64_INSTR_PT(609) OR ROM64_INSTR_PT(611) + OR ROM64_INSTR_PT(615) OR ROM64_INSTR_PT(616) + OR ROM64_INSTR_PT(617) OR ROM64_INSTR_PT(618) + OR ROM64_INSTR_PT(619) OR ROM64_INSTR_PT(623) + OR ROM64_INSTR_PT(627) OR ROM64_INSTR_PT(628) + OR ROM64_INSTR_PT(629) OR ROM64_INSTR_PT(632) + OR ROM64_INSTR_PT(633) OR ROM64_INSTR_PT(636) + OR ROM64_INSTR_PT(639) OR ROM64_INSTR_PT(642) + OR ROM64_INSTR_PT(643) OR ROM64_INSTR_PT(655) + OR ROM64_INSTR_PT(660) OR ROM64_INSTR_PT(663) + OR ROM64_INSTR_PT(664) OR ROM64_INSTR_PT(666) + OR ROM64_INSTR_PT(678) OR ROM64_INSTR_PT(695) + OR ROM64_INSTR_PT(702) OR ROM64_INSTR_PT(713) + OR ROM64_INSTR_PT(716) OR ROM64_INSTR_PT(717) + OR ROM64_INSTR_PT(721) OR ROM64_INSTR_PT(722) + OR ROM64_INSTR_PT(723) OR ROM64_INSTR_PT(724) + OR ROM64_INSTR_PT(733) OR ROM64_INSTR_PT(736) + OR ROM64_INSTR_PT(761) OR ROM64_INSTR_PT(770) + OR ROM64_INSTR_PT(798) OR ROM64_INSTR_PT(811) + OR ROM64_INSTR_PT(813) OR ROM64_INSTR_PT(822) + OR ROM64_INSTR_PT(824) OR ROM64_INSTR_PT(832) + OR ROM64_INSTR_PT(834) OR ROM64_INSTR_PT(846) + OR ROM64_INSTR_PT(855) OR ROM64_INSTR_PT(856) + OR ROM64_INSTR_PT(858) OR ROM64_INSTR_PT(864) + OR ROM64_INSTR_PT(870) OR ROM64_INSTR_PT(873) + ); +MQQ918:TEMPLATE(27) <= + (ROM64_INSTR_PT(5) OR ROM64_INSTR_PT(6) + OR ROM64_INSTR_PT(7) OR ROM64_INSTR_PT(8) + OR ROM64_INSTR_PT(9) OR ROM64_INSTR_PT(11) + OR ROM64_INSTR_PT(15) OR ROM64_INSTR_PT(18) + OR ROM64_INSTR_PT(21) OR ROM64_INSTR_PT(22) + OR ROM64_INSTR_PT(35) OR ROM64_INSTR_PT(38) + OR ROM64_INSTR_PT(42) OR ROM64_INSTR_PT(45) + OR ROM64_INSTR_PT(49) OR ROM64_INSTR_PT(52) + OR ROM64_INSTR_PT(53) OR ROM64_INSTR_PT(56) + OR ROM64_INSTR_PT(57) OR ROM64_INSTR_PT(61) + OR ROM64_INSTR_PT(68) OR ROM64_INSTR_PT(69) + OR ROM64_INSTR_PT(71) OR ROM64_INSTR_PT(73) + OR ROM64_INSTR_PT(82) OR ROM64_INSTR_PT(83) + OR ROM64_INSTR_PT(84) OR ROM64_INSTR_PT(90) + OR ROM64_INSTR_PT(93) OR ROM64_INSTR_PT(95) + OR ROM64_INSTR_PT(98) OR ROM64_INSTR_PT(101) + OR ROM64_INSTR_PT(102) OR ROM64_INSTR_PT(108) + OR ROM64_INSTR_PT(109) OR ROM64_INSTR_PT(113) + OR ROM64_INSTR_PT(116) OR ROM64_INSTR_PT(117) + OR ROM64_INSTR_PT(118) OR ROM64_INSTR_PT(128) + OR ROM64_INSTR_PT(132) OR ROM64_INSTR_PT(133) + OR ROM64_INSTR_PT(136) OR ROM64_INSTR_PT(143) + OR ROM64_INSTR_PT(144) OR ROM64_INSTR_PT(145) + OR ROM64_INSTR_PT(148) OR ROM64_INSTR_PT(155) + OR ROM64_INSTR_PT(157) OR ROM64_INSTR_PT(158) + OR ROM64_INSTR_PT(162) OR ROM64_INSTR_PT(164) + OR ROM64_INSTR_PT(168) OR ROM64_INSTR_PT(169) + OR ROM64_INSTR_PT(170) OR ROM64_INSTR_PT(171) + OR ROM64_INSTR_PT(177) OR ROM64_INSTR_PT(180) + OR ROM64_INSTR_PT(181) OR ROM64_INSTR_PT(182) + OR ROM64_INSTR_PT(183) OR ROM64_INSTR_PT(186) + OR ROM64_INSTR_PT(194) OR ROM64_INSTR_PT(196) + OR ROM64_INSTR_PT(201) OR ROM64_INSTR_PT(203) + OR ROM64_INSTR_PT(205) OR ROM64_INSTR_PT(206) + OR ROM64_INSTR_PT(211) OR ROM64_INSTR_PT(215) + OR ROM64_INSTR_PT(218) OR ROM64_INSTR_PT(219) + OR ROM64_INSTR_PT(222) OR ROM64_INSTR_PT(223) + OR ROM64_INSTR_PT(226) OR ROM64_INSTR_PT(233) + OR ROM64_INSTR_PT(238) OR ROM64_INSTR_PT(240) + OR ROM64_INSTR_PT(243) OR ROM64_INSTR_PT(244) + OR ROM64_INSTR_PT(245) OR ROM64_INSTR_PT(249) + OR ROM64_INSTR_PT(253) OR ROM64_INSTR_PT(254) + OR ROM64_INSTR_PT(258) OR ROM64_INSTR_PT(260) + OR ROM64_INSTR_PT(264) OR ROM64_INSTR_PT(265) + OR ROM64_INSTR_PT(268) OR ROM64_INSTR_PT(269) + OR ROM64_INSTR_PT(270) OR ROM64_INSTR_PT(272) + OR ROM64_INSTR_PT(276) OR ROM64_INSTR_PT(278) + OR ROM64_INSTR_PT(280) OR ROM64_INSTR_PT(282) + OR ROM64_INSTR_PT(283) OR ROM64_INSTR_PT(284) + OR ROM64_INSTR_PT(287) OR ROM64_INSTR_PT(290) + OR ROM64_INSTR_PT(293) OR ROM64_INSTR_PT(294) + OR ROM64_INSTR_PT(298) OR ROM64_INSTR_PT(299) + OR ROM64_INSTR_PT(302) OR ROM64_INSTR_PT(311) + OR ROM64_INSTR_PT(312) OR ROM64_INSTR_PT(325) + OR ROM64_INSTR_PT(339) OR ROM64_INSTR_PT(348) + OR ROM64_INSTR_PT(353) OR ROM64_INSTR_PT(361) + OR ROM64_INSTR_PT(364) OR ROM64_INSTR_PT(366) + OR ROM64_INSTR_PT(367) OR ROM64_INSTR_PT(372) + OR ROM64_INSTR_PT(374) OR ROM64_INSTR_PT(375) + OR ROM64_INSTR_PT(378) OR ROM64_INSTR_PT(381) + OR ROM64_INSTR_PT(383) OR ROM64_INSTR_PT(384) + OR ROM64_INSTR_PT(385) OR ROM64_INSTR_PT(391) + OR ROM64_INSTR_PT(395) OR ROM64_INSTR_PT(396) + OR ROM64_INSTR_PT(397) OR ROM64_INSTR_PT(401) + OR ROM64_INSTR_PT(403) OR ROM64_INSTR_PT(405) + OR ROM64_INSTR_PT(406) OR ROM64_INSTR_PT(409) + OR ROM64_INSTR_PT(410) OR ROM64_INSTR_PT(414) + OR ROM64_INSTR_PT(419) OR ROM64_INSTR_PT(425) + OR ROM64_INSTR_PT(426) OR ROM64_INSTR_PT(427) + OR ROM64_INSTR_PT(428) OR ROM64_INSTR_PT(429) + OR ROM64_INSTR_PT(430) OR ROM64_INSTR_PT(433) + OR ROM64_INSTR_PT(435) OR ROM64_INSTR_PT(438) + OR ROM64_INSTR_PT(439) OR ROM64_INSTR_PT(440) + OR ROM64_INSTR_PT(443) OR ROM64_INSTR_PT(445) + OR ROM64_INSTR_PT(451) OR ROM64_INSTR_PT(454) + OR ROM64_INSTR_PT(455) OR ROM64_INSTR_PT(456) + OR ROM64_INSTR_PT(457) OR ROM64_INSTR_PT(460) + OR ROM64_INSTR_PT(467) OR ROM64_INSTR_PT(473) + OR ROM64_INSTR_PT(475) OR ROM64_INSTR_PT(478) + OR ROM64_INSTR_PT(481) OR ROM64_INSTR_PT(482) + OR ROM64_INSTR_PT(484) OR ROM64_INSTR_PT(485) + OR ROM64_INSTR_PT(488) OR ROM64_INSTR_PT(490) + OR ROM64_INSTR_PT(495) OR ROM64_INSTR_PT(506) + OR ROM64_INSTR_PT(509) OR ROM64_INSTR_PT(510) + OR ROM64_INSTR_PT(514) OR ROM64_INSTR_PT(519) + OR ROM64_INSTR_PT(522) OR ROM64_INSTR_PT(523) + OR ROM64_INSTR_PT(525) OR ROM64_INSTR_PT(530) + OR ROM64_INSTR_PT(531) OR ROM64_INSTR_PT(532) + OR ROM64_INSTR_PT(534) OR ROM64_INSTR_PT(539) + OR ROM64_INSTR_PT(542) OR ROM64_INSTR_PT(552) + OR ROM64_INSTR_PT(553) OR ROM64_INSTR_PT(554) + OR ROM64_INSTR_PT(555) OR ROM64_INSTR_PT(557) + OR ROM64_INSTR_PT(563) OR ROM64_INSTR_PT(564) + OR ROM64_INSTR_PT(566) OR ROM64_INSTR_PT(568) + OR ROM64_INSTR_PT(570) OR ROM64_INSTR_PT(571) + OR ROM64_INSTR_PT(576) OR ROM64_INSTR_PT(577) + OR ROM64_INSTR_PT(580) OR ROM64_INSTR_PT(581) + OR ROM64_INSTR_PT(582) OR ROM64_INSTR_PT(583) + OR ROM64_INSTR_PT(584) OR ROM64_INSTR_PT(585) + OR ROM64_INSTR_PT(586) OR ROM64_INSTR_PT(587) + OR ROM64_INSTR_PT(589) OR ROM64_INSTR_PT(592) + OR ROM64_INSTR_PT(597) OR ROM64_INSTR_PT(604) + OR ROM64_INSTR_PT(607) OR ROM64_INSTR_PT(608) + OR ROM64_INSTR_PT(611) OR ROM64_INSTR_PT(616) + OR ROM64_INSTR_PT(619) OR ROM64_INSTR_PT(625) + OR ROM64_INSTR_PT(626) OR ROM64_INSTR_PT(629) + OR ROM64_INSTR_PT(632) OR ROM64_INSTR_PT(633) + OR ROM64_INSTR_PT(636) OR ROM64_INSTR_PT(639) + OR ROM64_INSTR_PT(642) OR ROM64_INSTR_PT(643) + OR ROM64_INSTR_PT(655) OR ROM64_INSTR_PT(660) + OR ROM64_INSTR_PT(663) OR ROM64_INSTR_PT(664) + OR ROM64_INSTR_PT(666) OR ROM64_INSTR_PT(678) + OR ROM64_INSTR_PT(681) OR ROM64_INSTR_PT(698) + OR ROM64_INSTR_PT(702) OR ROM64_INSTR_PT(713) + OR ROM64_INSTR_PT(722) OR ROM64_INSTR_PT(723) + OR ROM64_INSTR_PT(724) OR ROM64_INSTR_PT(733) + OR ROM64_INSTR_PT(736) OR ROM64_INSTR_PT(753) + OR ROM64_INSTR_PT(761) OR ROM64_INSTR_PT(770) + OR ROM64_INSTR_PT(798) OR ROM64_INSTR_PT(811) + OR ROM64_INSTR_PT(813) OR ROM64_INSTR_PT(823) + OR ROM64_INSTR_PT(824) OR ROM64_INSTR_PT(832) + OR ROM64_INSTR_PT(834) OR ROM64_INSTR_PT(854) + OR ROM64_INSTR_PT(855) OR ROM64_INSTR_PT(856) + OR ROM64_INSTR_PT(864) OR ROM64_INSTR_PT(870) + ); +MQQ919:TEMPLATE(28) <= + (ROM64_INSTR_PT(4) OR ROM64_INSTR_PT(5) + OR ROM64_INSTR_PT(6) OR ROM64_INSTR_PT(9) + OR ROM64_INSTR_PT(14) OR ROM64_INSTR_PT(17) + OR ROM64_INSTR_PT(22) OR ROM64_INSTR_PT(34) + OR ROM64_INSTR_PT(38) OR ROM64_INSTR_PT(41) + OR ROM64_INSTR_PT(45) OR ROM64_INSTR_PT(51) + OR ROM64_INSTR_PT(52) OR ROM64_INSTR_PT(56) + OR ROM64_INSTR_PT(57) OR ROM64_INSTR_PT(61) + OR ROM64_INSTR_PT(64) OR ROM64_INSTR_PT(68) + OR ROM64_INSTR_PT(69) OR ROM64_INSTR_PT(70) + OR ROM64_INSTR_PT(71) OR ROM64_INSTR_PT(73) + OR ROM64_INSTR_PT(75) OR ROM64_INSTR_PT(82) + OR ROM64_INSTR_PT(83) OR ROM64_INSTR_PT(84) + OR ROM64_INSTR_PT(86) OR ROM64_INSTR_PT(90) + OR ROM64_INSTR_PT(93) OR ROM64_INSTR_PT(95) + OR ROM64_INSTR_PT(98) OR ROM64_INSTR_PT(99) + OR ROM64_INSTR_PT(100) OR ROM64_INSTR_PT(101) + OR ROM64_INSTR_PT(102) OR ROM64_INSTR_PT(105) + OR ROM64_INSTR_PT(108) OR ROM64_INSTR_PT(113) + OR ROM64_INSTR_PT(115) OR ROM64_INSTR_PT(117) + OR ROM64_INSTR_PT(124) OR ROM64_INSTR_PT(125) + OR ROM64_INSTR_PT(127) OR ROM64_INSTR_PT(128) + OR ROM64_INSTR_PT(134) OR ROM64_INSTR_PT(136) + OR ROM64_INSTR_PT(137) OR ROM64_INSTR_PT(140) + OR ROM64_INSTR_PT(143) OR ROM64_INSTR_PT(144) + OR ROM64_INSTR_PT(148) OR ROM64_INSTR_PT(153) + OR ROM64_INSTR_PT(155) OR ROM64_INSTR_PT(157) + OR ROM64_INSTR_PT(158) OR ROM64_INSTR_PT(162) + OR ROM64_INSTR_PT(169) OR ROM64_INSTR_PT(171) + OR ROM64_INSTR_PT(180) OR ROM64_INSTR_PT(185) + OR ROM64_INSTR_PT(186) OR ROM64_INSTR_PT(194) + OR ROM64_INSTR_PT(196) OR ROM64_INSTR_PT(199) + OR ROM64_INSTR_PT(201) OR ROM64_INSTR_PT(203) + OR ROM64_INSTR_PT(204) OR ROM64_INSTR_PT(206) + OR ROM64_INSTR_PT(215) OR ROM64_INSTR_PT(217) + OR ROM64_INSTR_PT(218) OR ROM64_INSTR_PT(222) + OR ROM64_INSTR_PT(226) OR ROM64_INSTR_PT(238) + OR ROM64_INSTR_PT(241) OR ROM64_INSTR_PT(243) + OR ROM64_INSTR_PT(244) OR ROM64_INSTR_PT(249) + OR ROM64_INSTR_PT(252) OR ROM64_INSTR_PT(253) + OR ROM64_INSTR_PT(258) OR ROM64_INSTR_PT(260) + OR ROM64_INSTR_PT(263) OR ROM64_INSTR_PT(264) + OR ROM64_INSTR_PT(265) OR ROM64_INSTR_PT(268) + OR ROM64_INSTR_PT(269) OR ROM64_INSTR_PT(270) + OR ROM64_INSTR_PT(271) OR ROM64_INSTR_PT(275) + OR ROM64_INSTR_PT(282) OR ROM64_INSTR_PT(283) + OR ROM64_INSTR_PT(284) OR ROM64_INSTR_PT(285) + OR ROM64_INSTR_PT(287) OR ROM64_INSTR_PT(290) + OR ROM64_INSTR_PT(293) OR ROM64_INSTR_PT(294) + OR ROM64_INSTR_PT(297) OR ROM64_INSTR_PT(298) + OR ROM64_INSTR_PT(299) OR ROM64_INSTR_PT(302) + OR ROM64_INSTR_PT(305) OR ROM64_INSTR_PT(308) + OR ROM64_INSTR_PT(311) OR ROM64_INSTR_PT(315) + OR ROM64_INSTR_PT(319) OR ROM64_INSTR_PT(331) + OR ROM64_INSTR_PT(339) OR ROM64_INSTR_PT(348) + OR ROM64_INSTR_PT(353) OR ROM64_INSTR_PT(364) + OR ROM64_INSTR_PT(372) OR ROM64_INSTR_PT(374) + OR ROM64_INSTR_PT(375) OR ROM64_INSTR_PT(379) + OR ROM64_INSTR_PT(381) OR ROM64_INSTR_PT(383) + OR ROM64_INSTR_PT(384) OR ROM64_INSTR_PT(385) + OR ROM64_INSTR_PT(391) OR ROM64_INSTR_PT(394) + OR ROM64_INSTR_PT(395) OR ROM64_INSTR_PT(401) + OR ROM64_INSTR_PT(404) OR ROM64_INSTR_PT(405) + OR ROM64_INSTR_PT(410) OR ROM64_INSTR_PT(413) + OR ROM64_INSTR_PT(414) OR ROM64_INSTR_PT(415) + OR ROM64_INSTR_PT(418) OR ROM64_INSTR_PT(424) + OR ROM64_INSTR_PT(425) OR ROM64_INSTR_PT(426) + OR ROM64_INSTR_PT(428) OR ROM64_INSTR_PT(429) + OR ROM64_INSTR_PT(430) OR ROM64_INSTR_PT(432) + OR ROM64_INSTR_PT(435) OR ROM64_INSTR_PT(437) + OR ROM64_INSTR_PT(441) OR ROM64_INSTR_PT(446) + OR ROM64_INSTR_PT(451) OR ROM64_INSTR_PT(453) + OR ROM64_INSTR_PT(456) OR ROM64_INSTR_PT(457) + OR ROM64_INSTR_PT(460) OR ROM64_INSTR_PT(467) + OR ROM64_INSTR_PT(473) OR ROM64_INSTR_PT(475) + OR ROM64_INSTR_PT(478) OR ROM64_INSTR_PT(481) + OR ROM64_INSTR_PT(482) OR ROM64_INSTR_PT(484) + OR ROM64_INSTR_PT(485) OR ROM64_INSTR_PT(488) + OR ROM64_INSTR_PT(490) OR ROM64_INSTR_PT(493) + OR ROM64_INSTR_PT(495) OR ROM64_INSTR_PT(496) + OR ROM64_INSTR_PT(504) OR ROM64_INSTR_PT(505) + OR ROM64_INSTR_PT(506) OR ROM64_INSTR_PT(507) + OR ROM64_INSTR_PT(509) OR ROM64_INSTR_PT(511) + OR ROM64_INSTR_PT(512) OR ROM64_INSTR_PT(517) + OR ROM64_INSTR_PT(521) OR ROM64_INSTR_PT(522) + OR ROM64_INSTR_PT(525) OR ROM64_INSTR_PT(530) + OR ROM64_INSTR_PT(531) OR ROM64_INSTR_PT(534) + OR ROM64_INSTR_PT(539) OR ROM64_INSTR_PT(546) + OR ROM64_INSTR_PT(552) OR ROM64_INSTR_PT(553) + OR ROM64_INSTR_PT(554) OR ROM64_INSTR_PT(555) + OR ROM64_INSTR_PT(557) OR ROM64_INSTR_PT(558) + OR ROM64_INSTR_PT(559) OR ROM64_INSTR_PT(563) + OR ROM64_INSTR_PT(564) OR ROM64_INSTR_PT(568) + OR ROM64_INSTR_PT(569) OR ROM64_INSTR_PT(577) + OR ROM64_INSTR_PT(579) OR ROM64_INSTR_PT(580) + OR ROM64_INSTR_PT(582) OR ROM64_INSTR_PT(583) + OR ROM64_INSTR_PT(588) OR ROM64_INSTR_PT(591) + OR ROM64_INSTR_PT(592) OR ROM64_INSTR_PT(595) + OR ROM64_INSTR_PT(597) OR ROM64_INSTR_PT(600) + OR ROM64_INSTR_PT(606) OR ROM64_INSTR_PT(608) + OR ROM64_INSTR_PT(611) OR ROM64_INSTR_PT(615) + OR ROM64_INSTR_PT(618) OR ROM64_INSTR_PT(619) + OR ROM64_INSTR_PT(623) OR ROM64_INSTR_PT(627) + OR ROM64_INSTR_PT(629) OR ROM64_INSTR_PT(632) + OR ROM64_INSTR_PT(633) OR ROM64_INSTR_PT(636) + OR ROM64_INSTR_PT(639) OR ROM64_INSTR_PT(642) + OR ROM64_INSTR_PT(643) OR ROM64_INSTR_PT(644) + OR ROM64_INSTR_PT(655) OR ROM64_INSTR_PT(660) + OR ROM64_INSTR_PT(664) OR ROM64_INSTR_PT(666) + OR ROM64_INSTR_PT(678) OR ROM64_INSTR_PT(702) + OR ROM64_INSTR_PT(713) OR ROM64_INSTR_PT(722) + OR ROM64_INSTR_PT(728) OR ROM64_INSTR_PT(735) + OR ROM64_INSTR_PT(736) OR ROM64_INSTR_PT(738) + OR ROM64_INSTR_PT(739) OR ROM64_INSTR_PT(744) + OR ROM64_INSTR_PT(761) OR ROM64_INSTR_PT(769) + OR ROM64_INSTR_PT(770) OR ROM64_INSTR_PT(776) + OR ROM64_INSTR_PT(798) OR ROM64_INSTR_PT(811) + OR ROM64_INSTR_PT(813) OR ROM64_INSTR_PT(824) + OR ROM64_INSTR_PT(832) OR ROM64_INSTR_PT(855) + OR ROM64_INSTR_PT(856) OR ROM64_INSTR_PT(864) + OR ROM64_INSTR_PT(870)); +MQQ920:TEMPLATE(29) <= + (ROM64_INSTR_PT(4) OR ROM64_INSTR_PT(5) + OR ROM64_INSTR_PT(6) OR ROM64_INSTR_PT(7) + OR ROM64_INSTR_PT(8) OR ROM64_INSTR_PT(9) + OR ROM64_INSTR_PT(11) OR ROM64_INSTR_PT(14) + OR ROM64_INSTR_PT(15) OR ROM64_INSTR_PT(17) + OR ROM64_INSTR_PT(18) OR ROM64_INSTR_PT(22) + OR ROM64_INSTR_PT(25) OR ROM64_INSTR_PT(28) + OR ROM64_INSTR_PT(31) OR ROM64_INSTR_PT(38) + OR ROM64_INSTR_PT(41) OR ROM64_INSTR_PT(49) + OR ROM64_INSTR_PT(51) OR ROM64_INSTR_PT(52) + OR ROM64_INSTR_PT(53) OR ROM64_INSTR_PT(61) + OR ROM64_INSTR_PT(64) OR ROM64_INSTR_PT(70) + OR ROM64_INSTR_PT(71) OR ROM64_INSTR_PT(75) + OR ROM64_INSTR_PT(76) OR ROM64_INSTR_PT(83) + OR ROM64_INSTR_PT(86) OR ROM64_INSTR_PT(90) + OR ROM64_INSTR_PT(93) OR ROM64_INSTR_PT(97) + OR ROM64_INSTR_PT(99) OR ROM64_INSTR_PT(100) + OR ROM64_INSTR_PT(102) OR ROM64_INSTR_PT(105) + OR ROM64_INSTR_PT(113) OR ROM64_INSTR_PT(115) + OR ROM64_INSTR_PT(116) OR ROM64_INSTR_PT(117) + OR ROM64_INSTR_PT(124) OR ROM64_INSTR_PT(127) + OR ROM64_INSTR_PT(132) OR ROM64_INSTR_PT(133) + OR ROM64_INSTR_PT(134) OR ROM64_INSTR_PT(136) + OR ROM64_INSTR_PT(137) OR ROM64_INSTR_PT(140) + OR ROM64_INSTR_PT(144) OR ROM64_INSTR_PT(148) + OR ROM64_INSTR_PT(153) OR ROM64_INSTR_PT(158) + OR ROM64_INSTR_PT(164) OR ROM64_INSTR_PT(168) + OR ROM64_INSTR_PT(169) OR ROM64_INSTR_PT(171) + OR ROM64_INSTR_PT(172) OR ROM64_INSTR_PT(181) + OR ROM64_INSTR_PT(184) OR ROM64_INSTR_PT(185) + OR ROM64_INSTR_PT(186) OR ROM64_INSTR_PT(194) + OR ROM64_INSTR_PT(199) OR ROM64_INSTR_PT(202) + OR ROM64_INSTR_PT(204) OR ROM64_INSTR_PT(211) + OR ROM64_INSTR_PT(215) OR ROM64_INSTR_PT(217) + OR ROM64_INSTR_PT(218) OR ROM64_INSTR_PT(219) + OR ROM64_INSTR_PT(222) OR ROM64_INSTR_PT(226) + OR ROM64_INSTR_PT(229) OR ROM64_INSTR_PT(230) + OR ROM64_INSTR_PT(238) OR ROM64_INSTR_PT(241) + OR ROM64_INSTR_PT(245) OR ROM64_INSTR_PT(252) + OR ROM64_INSTR_PT(253) OR ROM64_INSTR_PT(260) + OR ROM64_INSTR_PT(263) OR ROM64_INSTR_PT(264) + OR ROM64_INSTR_PT(268) OR ROM64_INSTR_PT(270) + OR ROM64_INSTR_PT(271) OR ROM64_INSTR_PT(272) + OR ROM64_INSTR_PT(273) OR ROM64_INSTR_PT(275) + OR ROM64_INSTR_PT(276) OR ROM64_INSTR_PT(277) + OR ROM64_INSTR_PT(282) OR ROM64_INSTR_PT(283) + OR ROM64_INSTR_PT(285) OR ROM64_INSTR_PT(287) + OR ROM64_INSTR_PT(293) OR ROM64_INSTR_PT(294) + OR ROM64_INSTR_PT(297) OR ROM64_INSTR_PT(298) + OR ROM64_INSTR_PT(299) OR ROM64_INSTR_PT(302) + OR ROM64_INSTR_PT(305) OR ROM64_INSTR_PT(308) + OR ROM64_INSTR_PT(311) OR ROM64_INSTR_PT(312) + OR ROM64_INSTR_PT(315) OR ROM64_INSTR_PT(319) + OR ROM64_INSTR_PT(324) OR ROM64_INSTR_PT(325) + OR ROM64_INSTR_PT(331) OR ROM64_INSTR_PT(340) + OR ROM64_INSTR_PT(361) OR ROM64_INSTR_PT(364) + OR ROM64_INSTR_PT(374) OR ROM64_INSTR_PT(375) + OR ROM64_INSTR_PT(379) OR ROM64_INSTR_PT(383) + OR ROM64_INSTR_PT(384) OR ROM64_INSTR_PT(385) + OR ROM64_INSTR_PT(388) OR ROM64_INSTR_PT(391) + OR ROM64_INSTR_PT(394) OR ROM64_INSTR_PT(401) + OR ROM64_INSTR_PT(403) OR ROM64_INSTR_PT(404) + OR ROM64_INSTR_PT(406) OR ROM64_INSTR_PT(410) + OR ROM64_INSTR_PT(413) OR ROM64_INSTR_PT(414) + OR ROM64_INSTR_PT(415) OR ROM64_INSTR_PT(418) + OR ROM64_INSTR_PT(424) OR ROM64_INSTR_PT(428) + OR ROM64_INSTR_PT(430) OR ROM64_INSTR_PT(432) + OR ROM64_INSTR_PT(434) OR ROM64_INSTR_PT(437) + OR ROM64_INSTR_PT(438) OR ROM64_INSTR_PT(439) + OR ROM64_INSTR_PT(440) OR ROM64_INSTR_PT(441) + OR ROM64_INSTR_PT(443) OR ROM64_INSTR_PT(445) + OR ROM64_INSTR_PT(446) OR ROM64_INSTR_PT(453) + OR ROM64_INSTR_PT(454) OR ROM64_INSTR_PT(455) + OR ROM64_INSTR_PT(468) OR ROM64_INSTR_PT(478) + OR ROM64_INSTR_PT(481) OR ROM64_INSTR_PT(482) + OR ROM64_INSTR_PT(484) OR ROM64_INSTR_PT(485) + OR ROM64_INSTR_PT(493) OR ROM64_INSTR_PT(495) + OR ROM64_INSTR_PT(496) OR ROM64_INSTR_PT(503) + OR ROM64_INSTR_PT(504) OR ROM64_INSTR_PT(505) + OR ROM64_INSTR_PT(509) OR ROM64_INSTR_PT(510) + OR ROM64_INSTR_PT(511) OR ROM64_INSTR_PT(512) + OR ROM64_INSTR_PT(516) OR ROM64_INSTR_PT(519) + OR ROM64_INSTR_PT(521) OR ROM64_INSTR_PT(522) + OR ROM64_INSTR_PT(525) OR ROM64_INSTR_PT(530) + OR ROM64_INSTR_PT(531) OR ROM64_INSTR_PT(532) + OR ROM64_INSTR_PT(534) OR ROM64_INSTR_PT(535) + OR ROM64_INSTR_PT(544) OR ROM64_INSTR_PT(545) + OR ROM64_INSTR_PT(546) OR ROM64_INSTR_PT(549) + OR ROM64_INSTR_PT(552) OR ROM64_INSTR_PT(555) + OR ROM64_INSTR_PT(558) OR ROM64_INSTR_PT(559) + OR ROM64_INSTR_PT(563) OR ROM64_INSTR_PT(564) + OR ROM64_INSTR_PT(566) OR ROM64_INSTR_PT(569) + OR ROM64_INSTR_PT(571) OR ROM64_INSTR_PT(575) + OR ROM64_INSTR_PT(576) OR ROM64_INSTR_PT(579) + OR ROM64_INSTR_PT(580) OR ROM64_INSTR_PT(581) + OR ROM64_INSTR_PT(582) OR ROM64_INSTR_PT(583) + OR ROM64_INSTR_PT(586) OR ROM64_INSTR_PT(587) + OR ROM64_INSTR_PT(588) OR ROM64_INSTR_PT(589) + OR ROM64_INSTR_PT(591) OR ROM64_INSTR_PT(595) + OR ROM64_INSTR_PT(600) OR ROM64_INSTR_PT(604) + OR ROM64_INSTR_PT(606) OR ROM64_INSTR_PT(607) + OR ROM64_INSTR_PT(608) OR ROM64_INSTR_PT(615) + OR ROM64_INSTR_PT(618) OR ROM64_INSTR_PT(625) + OR ROM64_INSTR_PT(627) OR ROM64_INSTR_PT(628) + OR ROM64_INSTR_PT(629) OR ROM64_INSTR_PT(632) + OR ROM64_INSTR_PT(633) OR ROM64_INSTR_PT(639) + OR ROM64_INSTR_PT(642) OR ROM64_INSTR_PT(644) + OR ROM64_INSTR_PT(663) OR ROM64_INSTR_PT(664) + OR ROM64_INSTR_PT(666) OR ROM64_INSTR_PT(678) + OR ROM64_INSTR_PT(681) OR ROM64_INSTR_PT(698) + OR ROM64_INSTR_PT(702) OR ROM64_INSTR_PT(722) + OR ROM64_INSTR_PT(728) OR ROM64_INSTR_PT(731) + OR ROM64_INSTR_PT(735) OR ROM64_INSTR_PT(738) + OR ROM64_INSTR_PT(744) OR ROM64_INSTR_PT(761) + OR ROM64_INSTR_PT(769) OR ROM64_INSTR_PT(776) + OR ROM64_INSTR_PT(798) OR ROM64_INSTR_PT(832) + OR ROM64_INSTR_PT(846) OR ROM64_INSTR_PT(854) + OR ROM64_INSTR_PT(856) OR ROM64_INSTR_PT(864) + OR ROM64_INSTR_PT(870)); +MQQ921:TEMPLATE(30) <= + (ROM64_INSTR_PT(4) OR ROM64_INSTR_PT(5) + OR ROM64_INSTR_PT(7) OR ROM64_INSTR_PT(9) + OR ROM64_INSTR_PT(10) OR ROM64_INSTR_PT(14) + OR ROM64_INSTR_PT(17) OR ROM64_INSTR_PT(21) + OR ROM64_INSTR_PT(22) OR ROM64_INSTR_PT(34) + OR ROM64_INSTR_PT(38) OR ROM64_INSTR_PT(41) + OR ROM64_INSTR_PT(45) OR ROM64_INSTR_PT(50) + OR ROM64_INSTR_PT(51) OR ROM64_INSTR_PT(52) + OR ROM64_INSTR_PT(55) OR ROM64_INSTR_PT(61) + OR ROM64_INSTR_PT(64) OR ROM64_INSTR_PT(70) + OR ROM64_INSTR_PT(71) OR ROM64_INSTR_PT(75) + OR ROM64_INSTR_PT(76) OR ROM64_INSTR_PT(77) + OR ROM64_INSTR_PT(78) OR ROM64_INSTR_PT(80) + OR ROM64_INSTR_PT(83) OR ROM64_INSTR_PT(84) + OR ROM64_INSTR_PT(86) OR ROM64_INSTR_PT(89) + OR ROM64_INSTR_PT(90) OR ROM64_INSTR_PT(92) + OR ROM64_INSTR_PT(96) OR ROM64_INSTR_PT(99) + OR ROM64_INSTR_PT(100) OR ROM64_INSTR_PT(102) + OR ROM64_INSTR_PT(104) OR ROM64_INSTR_PT(105) + OR ROM64_INSTR_PT(106) OR ROM64_INSTR_PT(110) + OR ROM64_INSTR_PT(113) OR ROM64_INSTR_PT(114) + OR ROM64_INSTR_PT(115) OR ROM64_INSTR_PT(116) + OR ROM64_INSTR_PT(117) OR ROM64_INSTR_PT(118) + OR ROM64_INSTR_PT(121) OR ROM64_INSTR_PT(124) + OR ROM64_INSTR_PT(127) OR ROM64_INSTR_PT(132) + OR ROM64_INSTR_PT(136) OR ROM64_INSTR_PT(137) + OR ROM64_INSTR_PT(140) OR ROM64_INSTR_PT(143) + OR ROM64_INSTR_PT(144) OR ROM64_INSTR_PT(148) + OR ROM64_INSTR_PT(153) OR ROM64_INSTR_PT(169) + OR ROM64_INSTR_PT(171) OR ROM64_INSTR_PT(175) + OR ROM64_INSTR_PT(177) OR ROM64_INSTR_PT(180) + OR ROM64_INSTR_PT(181) OR ROM64_INSTR_PT(183) + OR ROM64_INSTR_PT(184) OR ROM64_INSTR_PT(185) + OR ROM64_INSTR_PT(186) OR ROM64_INSTR_PT(188) + OR ROM64_INSTR_PT(194) OR ROM64_INSTR_PT(199) + OR ROM64_INSTR_PT(202) OR ROM64_INSTR_PT(204) + OR ROM64_INSTR_PT(208) OR ROM64_INSTR_PT(213) + OR ROM64_INSTR_PT(214) OR ROM64_INSTR_PT(215) + OR ROM64_INSTR_PT(217) OR ROM64_INSTR_PT(218) + OR ROM64_INSTR_PT(221) OR ROM64_INSTR_PT(222) + OR ROM64_INSTR_PT(223) OR ROM64_INSTR_PT(226) + OR ROM64_INSTR_PT(229) OR ROM64_INSTR_PT(230) + OR ROM64_INSTR_PT(233) OR ROM64_INSTR_PT(238) + OR ROM64_INSTR_PT(241) OR ROM64_INSTR_PT(252) + OR ROM64_INSTR_PT(258) OR ROM64_INSTR_PT(260) + OR ROM64_INSTR_PT(263) OR ROM64_INSTR_PT(264) + OR ROM64_INSTR_PT(268) OR ROM64_INSTR_PT(270) + OR ROM64_INSTR_PT(271) OR ROM64_INSTR_PT(274) + OR ROM64_INSTR_PT(275) OR ROM64_INSTR_PT(276) + OR ROM64_INSTR_PT(280) OR ROM64_INSTR_PT(282) + OR ROM64_INSTR_PT(285) OR ROM64_INSTR_PT(286) + OR ROM64_INSTR_PT(293) OR ROM64_INSTR_PT(297) + OR ROM64_INSTR_PT(298) OR ROM64_INSTR_PT(299) + OR ROM64_INSTR_PT(302) OR ROM64_INSTR_PT(305) + OR ROM64_INSTR_PT(308) OR ROM64_INSTR_PT(315) + OR ROM64_INSTR_PT(319) OR ROM64_INSTR_PT(322) + OR ROM64_INSTR_PT(331) OR ROM64_INSTR_PT(339) + OR ROM64_INSTR_PT(347) OR ROM64_INSTR_PT(349) + OR ROM64_INSTR_PT(350) OR ROM64_INSTR_PT(358) + OR ROM64_INSTR_PT(364) OR ROM64_INSTR_PT(367) + OR ROM64_INSTR_PT(369) OR ROM64_INSTR_PT(371) + OR ROM64_INSTR_PT(374) OR ROM64_INSTR_PT(375) + OR ROM64_INSTR_PT(378) OR ROM64_INSTR_PT(379) + OR ROM64_INSTR_PT(383) OR ROM64_INSTR_PT(385) + OR ROM64_INSTR_PT(391) OR ROM64_INSTR_PT(394) + OR ROM64_INSTR_PT(397) OR ROM64_INSTR_PT(403) + OR ROM64_INSTR_PT(404) OR ROM64_INSTR_PT(410) + OR ROM64_INSTR_PT(413) OR ROM64_INSTR_PT(414) + OR ROM64_INSTR_PT(415) OR ROM64_INSTR_PT(418) + OR ROM64_INSTR_PT(422) OR ROM64_INSTR_PT(424) + OR ROM64_INSTR_PT(427) OR ROM64_INSTR_PT(430) + OR ROM64_INSTR_PT(432) OR ROM64_INSTR_PT(434) + OR ROM64_INSTR_PT(435) OR ROM64_INSTR_PT(437) + OR ROM64_INSTR_PT(441) OR ROM64_INSTR_PT(445) + OR ROM64_INSTR_PT(446) OR ROM64_INSTR_PT(453) + OR ROM64_INSTR_PT(461) OR ROM64_INSTR_PT(463) + OR ROM64_INSTR_PT(466) OR ROM64_INSTR_PT(478) + OR ROM64_INSTR_PT(481) OR ROM64_INSTR_PT(482) + OR ROM64_INSTR_PT(484) OR ROM64_INSTR_PT(485) + OR ROM64_INSTR_PT(493) OR ROM64_INSTR_PT(495) + OR ROM64_INSTR_PT(496) OR ROM64_INSTR_PT(503) + OR ROM64_INSTR_PT(504) OR ROM64_INSTR_PT(505) + OR ROM64_INSTR_PT(509) OR ROM64_INSTR_PT(510) + OR ROM64_INSTR_PT(511) OR ROM64_INSTR_PT(512) + OR ROM64_INSTR_PT(521) OR ROM64_INSTR_PT(522) + OR ROM64_INSTR_PT(523) OR ROM64_INSTR_PT(525) + OR ROM64_INSTR_PT(534) OR ROM64_INSTR_PT(540) + OR ROM64_INSTR_PT(545) OR ROM64_INSTR_PT(546) + OR ROM64_INSTR_PT(552) OR ROM64_INSTR_PT(555) + OR ROM64_INSTR_PT(557) OR ROM64_INSTR_PT(558) + OR ROM64_INSTR_PT(559) OR ROM64_INSTR_PT(563) + OR ROM64_INSTR_PT(569) OR ROM64_INSTR_PT(571) + OR ROM64_INSTR_PT(576) OR ROM64_INSTR_PT(579) + OR ROM64_INSTR_PT(582) OR ROM64_INSTR_PT(583) + OR ROM64_INSTR_PT(584) OR ROM64_INSTR_PT(588) + OR ROM64_INSTR_PT(591) OR ROM64_INSTR_PT(592) + OR ROM64_INSTR_PT(595) OR ROM64_INSTR_PT(596) + OR ROM64_INSTR_PT(600) OR ROM64_INSTR_PT(606) + OR ROM64_INSTR_PT(608) OR ROM64_INSTR_PT(609) + OR ROM64_INSTR_PT(613) OR ROM64_INSTR_PT(615) + OR ROM64_INSTR_PT(618) OR ROM64_INSTR_PT(619) + OR ROM64_INSTR_PT(627) OR ROM64_INSTR_PT(629) + OR ROM64_INSTR_PT(632) OR ROM64_INSTR_PT(633) + OR ROM64_INSTR_PT(639) OR ROM64_INSTR_PT(642) + OR ROM64_INSTR_PT(644) OR ROM64_INSTR_PT(666) + OR ROM64_INSTR_PT(678) OR ROM64_INSTR_PT(685) + OR ROM64_INSTR_PT(687) OR ROM64_INSTR_PT(691) + OR ROM64_INSTR_PT(695) OR ROM64_INSTR_PT(716) + OR ROM64_INSTR_PT(722) OR ROM64_INSTR_PT(723) + OR ROM64_INSTR_PT(724) OR ROM64_INSTR_PT(728) + OR ROM64_INSTR_PT(731) OR ROM64_INSTR_PT(733) + OR ROM64_INSTR_PT(735) OR ROM64_INSTR_PT(736) + OR ROM64_INSTR_PT(738) OR ROM64_INSTR_PT(744) + OR ROM64_INSTR_PT(761) OR ROM64_INSTR_PT(769) + OR ROM64_INSTR_PT(770) OR ROM64_INSTR_PT(776) + OR ROM64_INSTR_PT(834) OR ROM64_INSTR_PT(846) + OR ROM64_INSTR_PT(856) OR ROM64_INSTR_PT(864) + OR ROM64_INSTR_PT(870)); +MQQ922:TEMPLATE(31) <= + (ROM64_INSTR_PT(33) OR ROM64_INSTR_PT(60) + OR ROM64_INSTR_PT(79) OR ROM64_INSTR_PT(98) + OR ROM64_INSTR_PT(103) OR ROM64_INSTR_PT(142) + OR ROM64_INSTR_PT(147) OR ROM64_INSTR_PT(150) + OR ROM64_INSTR_PT(160) OR ROM64_INSTR_PT(168) + OR ROM64_INSTR_PT(176) OR ROM64_INSTR_PT(187) + OR ROM64_INSTR_PT(207) OR ROM64_INSTR_PT(209) + OR ROM64_INSTR_PT(219) OR ROM64_INSTR_PT(224) + OR ROM64_INSTR_PT(228) OR ROM64_INSTR_PT(231) + OR ROM64_INSTR_PT(247) OR ROM64_INSTR_PT(253) + OR ROM64_INSTR_PT(281) OR ROM64_INSTR_PT(288) + OR ROM64_INSTR_PT(296) OR ROM64_INSTR_PT(304) + OR ROM64_INSTR_PT(309) OR ROM64_INSTR_PT(314) + OR ROM64_INSTR_PT(327) OR ROM64_INSTR_PT(332) + OR ROM64_INSTR_PT(341) OR ROM64_INSTR_PT(352) + OR ROM64_INSTR_PT(361) OR ROM64_INSTR_PT(374) + OR ROM64_INSTR_PT(401) OR ROM64_INSTR_PT(406) + OR ROM64_INSTR_PT(464) OR ROM64_INSTR_PT(471) + OR ROM64_INSTR_PT(491) OR ROM64_INSTR_PT(597) + OR ROM64_INSTR_PT(632) OR ROM64_INSTR_PT(635) + OR ROM64_INSTR_PT(641) OR ROM64_INSTR_PT(654) + OR ROM64_INSTR_PT(675) OR ROM64_INSTR_PT(723) + OR ROM64_INSTR_PT(724) OR ROM64_INSTR_PT(728) + OR ROM64_INSTR_PT(733) OR ROM64_INSTR_PT(735) + OR ROM64_INSTR_PT(738) OR ROM64_INSTR_PT(759) + OR ROM64_INSTR_PT(766) OR ROM64_INSTR_PT(781) + OR ROM64_INSTR_PT(794) OR ROM64_INSTR_PT(809) + ); +MQQ923:UCODE_END <= + (ROM64_INSTR_PT(198) OR ROM64_INSTR_PT(200) + OR ROM64_INSTR_PT(212) OR ROM64_INSTR_PT(386) + OR ROM64_INSTR_PT(443) OR ROM64_INSTR_PT(444) + OR ROM64_INSTR_PT(452) OR ROM64_INSTR_PT(516) + OR ROM64_INSTR_PT(518) OR ROM64_INSTR_PT(528) + OR ROM64_INSTR_PT(542) OR ROM64_INSTR_PT(550) + OR ROM64_INSTR_PT(556) OR ROM64_INSTR_PT(560) + OR ROM64_INSTR_PT(567) OR ROM64_INSTR_PT(574) + OR ROM64_INSTR_PT(577) OR ROM64_INSTR_PT(578) + OR ROM64_INSTR_PT(581) OR ROM64_INSTR_PT(593) + OR ROM64_INSTR_PT(604) OR ROM64_INSTR_PT(606) + OR ROM64_INSTR_PT(607) OR ROM64_INSTR_PT(622) + OR ROM64_INSTR_PT(663) OR ROM64_INSTR_PT(668) + OR ROM64_INSTR_PT(690) OR ROM64_INSTR_PT(699) + OR ROM64_INSTR_PT(704) OR ROM64_INSTR_PT(706) + OR ROM64_INSTR_PT(714) OR ROM64_INSTR_PT(718) + OR ROM64_INSTR_PT(741) OR ROM64_INSTR_PT(785) + OR ROM64_INSTR_PT(790) OR ROM64_INSTR_PT(813) + OR ROM64_INSTR_PT(823) OR ROM64_INSTR_PT(824) + OR ROM64_INSTR_PT(826) OR ROM64_INSTR_PT(828) + OR ROM64_INSTR_PT(841) OR ROM64_INSTR_PT(844) + OR ROM64_INSTR_PT(845) OR ROM64_INSTR_PT(849) + OR ROM64_INSTR_PT(854)); +MQQ924:UCODE_END_EARLY <= + (ROM64_INSTR_PT(376) OR ROM64_INSTR_PT(390) + OR ROM64_INSTR_PT(650) OR ROM64_INSTR_PT(676) + OR ROM64_INSTR_PT(683) OR ROM64_INSTR_PT(689) + OR ROM64_INSTR_PT(730) OR ROM64_INSTR_PT(742) + OR ROM64_INSTR_PT(757) OR ROM64_INSTR_PT(760) + OR ROM64_INSTR_PT(787) OR ROM64_INSTR_PT(788) + OR ROM64_INSTR_PT(800) OR ROM64_INSTR_PT(802) + OR ROM64_INSTR_PT(803) OR ROM64_INSTR_PT(807) + OR ROM64_INSTR_PT(814) OR ROM64_INSTR_PT(818) + OR ROM64_INSTR_PT(825) OR ROM64_INSTR_PT(830) + OR ROM64_INSTR_PT(874)); +MQQ925:LOOP_BEGIN <= + (ROM64_INSTR_PT(26) OR ROM64_INSTR_PT(55) + OR ROM64_INSTR_PT(104) OR ROM64_INSTR_PT(124) + OR ROM64_INSTR_PT(147) OR ROM64_INSTR_PT(210) + OR ROM64_INSTR_PT(228) OR ROM64_INSTR_PT(231) + OR ROM64_INSTR_PT(239) OR ROM64_INSTR_PT(246) + OR ROM64_INSTR_PT(255) OR ROM64_INSTR_PT(306) + OR ROM64_INSTR_PT(310) OR ROM64_INSTR_PT(316) + OR ROM64_INSTR_PT(322) OR ROM64_INSTR_PT(349) + OR ROM64_INSTR_PT(369) OR ROM64_INSTR_PT(379) + OR ROM64_INSTR_PT(411) OR ROM64_INSTR_PT(412) + OR ROM64_INSTR_PT(436) OR ROM64_INSTR_PT(450) + OR ROM64_INSTR_PT(462) OR ROM64_INSTR_PT(487) + OR ROM64_INSTR_PT(493) OR ROM64_INSTR_PT(496) + OR ROM64_INSTR_PT(546) OR ROM64_INSTR_PT(559) + OR ROM64_INSTR_PT(572) OR ROM64_INSTR_PT(590) + OR ROM64_INSTR_PT(610)); +MQQ926:LOOP_END <= + (ROM64_INSTR_PT(149) OR ROM64_INSTR_PT(156) + OR ROM64_INSTR_PT(376) OR ROM64_INSTR_PT(469) + OR ROM64_INSTR_PT(494) OR ROM64_INSTR_PT(502) + OR ROM64_INSTR_PT(565) OR ROM64_INSTR_PT(638) + OR ROM64_INSTR_PT(647) OR ROM64_INSTR_PT(656) + OR ROM64_INSTR_PT(680) OR ROM64_INSTR_PT(701) + OR ROM64_INSTR_PT(751) OR ROM64_INSTR_PT(775) + OR ROM64_INSTR_PT(779) OR ROM64_INSTR_PT(789) + OR ROM64_INSTR_PT(799) OR ROM64_INSTR_PT(807) + OR ROM64_INSTR_PT(815) OR ROM64_INSTR_PT(816) + OR ROM64_INSTR_PT(850) OR ROM64_INSTR_PT(862) + OR ROM64_INSTR_PT(875)); +MQQ927:COUNT_SRC(0) <= + (ROM64_INSTR_PT(72) OR ROM64_INSTR_PT(752) + OR ROM64_INSTR_PT(768) OR ROM64_INSTR_PT(876) + OR ROM64_INSTR_PT(881) OR ROM64_INSTR_PT(882) + OR ROM64_INSTR_PT(887) OR ROM64_INSTR_PT(888) + OR ROM64_INSTR_PT(889)); +MQQ928:COUNT_SRC(1) <= + (ROM64_INSTR_PT(839) OR ROM64_INSTR_PT(879) + OR ROM64_INSTR_PT(882) OR ROM64_INSTR_PT(884) + OR ROM64_INSTR_PT(885) OR ROM64_INSTR_PT(888) + OR ROM64_INSTR_PT(889)); +MQQ929:COUNT_SRC(2) <= + (ROM64_INSTR_PT(686) OR ROM64_INSTR_PT(752) + OR ROM64_INSTR_PT(768) OR ROM64_INSTR_PT(831) + OR ROM64_INSTR_PT(839) OR ROM64_INSTR_PT(887) + OR ROM64_INSTR_PT(888) OR ROM64_INSTR_PT(889) + ); +MQQ930:EXTRT <= + (ROM64_INSTR_PT(4) OR ROM64_INSTR_PT(6) + OR ROM64_INSTR_PT(19) OR ROM64_INSTR_PT(24) + OR ROM64_INSTR_PT(27) OR ROM64_INSTR_PT(47) + OR ROM64_INSTR_PT(48) OR ROM64_INSTR_PT(63) + OR ROM64_INSTR_PT(69) OR ROM64_INSTR_PT(74) + OR ROM64_INSTR_PT(91) OR ROM64_INSTR_PT(95) + OR ROM64_INSTR_PT(98) OR ROM64_INSTR_PT(107) + OR ROM64_INSTR_PT(120) OR ROM64_INSTR_PT(123) + OR ROM64_INSTR_PT(130) OR ROM64_INSTR_PT(131) + OR ROM64_INSTR_PT(133) OR ROM64_INSTR_PT(135) + OR ROM64_INSTR_PT(138) OR ROM64_INSTR_PT(140) + OR ROM64_INSTR_PT(141) OR ROM64_INSTR_PT(151) + OR ROM64_INSTR_PT(152) OR ROM64_INSTR_PT(159) + OR ROM64_INSTR_PT(163) OR ROM64_INSTR_PT(164) + OR ROM64_INSTR_PT(167) OR ROM64_INSTR_PT(189) + OR ROM64_INSTR_PT(192) OR ROM64_INSTR_PT(220) + OR ROM64_INSTR_PT(227) OR ROM64_INSTR_PT(234) + OR ROM64_INSTR_PT(235) OR ROM64_INSTR_PT(250) + OR ROM64_INSTR_PT(253) OR ROM64_INSTR_PT(258) + OR ROM64_INSTR_PT(266) OR ROM64_INSTR_PT(267) + OR ROM64_INSTR_PT(279) OR ROM64_INSTR_PT(283) + OR ROM64_INSTR_PT(300) OR ROM64_INSTR_PT(301) + OR ROM64_INSTR_PT(303) OR ROM64_INSTR_PT(317) + OR ROM64_INSTR_PT(318) OR ROM64_INSTR_PT(328) + OR ROM64_INSTR_PT(330) OR ROM64_INSTR_PT(331) + OR ROM64_INSTR_PT(335) OR ROM64_INSTR_PT(337) + OR ROM64_INSTR_PT(338) OR ROM64_INSTR_PT(344) + OR ROM64_INSTR_PT(355) OR ROM64_INSTR_PT(356) + OR ROM64_INSTR_PT(384) OR ROM64_INSTR_PT(393) + OR ROM64_INSTR_PT(394) OR ROM64_INSTR_PT(398) + OR ROM64_INSTR_PT(418) OR ROM64_INSTR_PT(423) + OR ROM64_INSTR_PT(441) OR ROM64_INSTR_PT(447) + OR ROM64_INSTR_PT(449) OR ROM64_INSTR_PT(476) + OR ROM64_INSTR_PT(486) OR ROM64_INSTR_PT(487) + OR ROM64_INSTR_PT(496) OR ROM64_INSTR_PT(500) + OR ROM64_INSTR_PT(501) OR ROM64_INSTR_PT(526) + OR ROM64_INSTR_PT(547) OR ROM64_INSTR_PT(591) + OR ROM64_INSTR_PT(594) OR ROM64_INSTR_PT(597) + OR ROM64_INSTR_PT(624) OR ROM64_INSTR_PT(630) + OR ROM64_INSTR_PT(631) OR ROM64_INSTR_PT(640) + OR ROM64_INSTR_PT(651) OR ROM64_INSTR_PT(665) + OR ROM64_INSTR_PT(670) OR ROM64_INSTR_PT(671) + OR ROM64_INSTR_PT(672) OR ROM64_INSTR_PT(673) + OR ROM64_INSTR_PT(674) OR ROM64_INSTR_PT(688) + OR ROM64_INSTR_PT(696) OR ROM64_INSTR_PT(700) + OR ROM64_INSTR_PT(707) OR ROM64_INSTR_PT(712) + OR ROM64_INSTR_PT(727) OR ROM64_INSTR_PT(732) + OR ROM64_INSTR_PT(737) OR ROM64_INSTR_PT(743) + OR ROM64_INSTR_PT(744) OR ROM64_INSTR_PT(746) + OR ROM64_INSTR_PT(747) OR ROM64_INSTR_PT(750) + OR ROM64_INSTR_PT(755) OR ROM64_INSTR_PT(756) + OR ROM64_INSTR_PT(763) OR ROM64_INSTR_PT(764) + OR ROM64_INSTR_PT(767) OR ROM64_INSTR_PT(771) + OR ROM64_INSTR_PT(774) OR ROM64_INSTR_PT(776) + OR ROM64_INSTR_PT(777) OR ROM64_INSTR_PT(780) + OR ROM64_INSTR_PT(782) OR ROM64_INSTR_PT(783) + OR ROM64_INSTR_PT(784) OR ROM64_INSTR_PT(786) + OR ROM64_INSTR_PT(793) OR ROM64_INSTR_PT(795) + OR ROM64_INSTR_PT(798) OR ROM64_INSTR_PT(810) + OR ROM64_INSTR_PT(812) OR ROM64_INSTR_PT(820) + OR ROM64_INSTR_PT(821) OR ROM64_INSTR_PT(833) + OR ROM64_INSTR_PT(835) OR ROM64_INSTR_PT(837) + OR ROM64_INSTR_PT(838) OR ROM64_INSTR_PT(848) + OR ROM64_INSTR_PT(857) OR ROM64_INSTR_PT(859) + OR ROM64_INSTR_PT(860) OR ROM64_INSTR_PT(863) + OR ROM64_INSTR_PT(864) OR ROM64_INSTR_PT(865) + OR ROM64_INSTR_PT(866) OR ROM64_INSTR_PT(867) + OR ROM64_INSTR_PT(868) OR ROM64_INSTR_PT(871) + OR ROM64_INSTR_PT(877) OR ROM64_INSTR_PT(878) + OR ROM64_INSTR_PT(880)); +MQQ931:EXTS1 <= + (ROM64_INSTR_PT(4) OR ROM64_INSTR_PT(19) + OR ROM64_INSTR_PT(32) OR ROM64_INSTR_PT(34) + OR ROM64_INSTR_PT(47) OR ROM64_INSTR_PT(74) + OR ROM64_INSTR_PT(81) OR ROM64_INSTR_PT(91) + OR ROM64_INSTR_PT(94) OR ROM64_INSTR_PT(100) + OR ROM64_INSTR_PT(131) OR ROM64_INSTR_PT(137) + OR ROM64_INSTR_PT(138) OR ROM64_INSTR_PT(159) + OR ROM64_INSTR_PT(165) OR ROM64_INSTR_PT(167) + OR ROM64_INSTR_PT(193) OR ROM64_INSTR_PT(211) + OR ROM64_INSTR_PT(225) OR ROM64_INSTR_PT(227) + OR ROM64_INSTR_PT(232) OR ROM64_INSTR_PT(235) + OR ROM64_INSTR_PT(279) OR ROM64_INSTR_PT(289) + OR ROM64_INSTR_PT(291) OR ROM64_INSTR_PT(297) + OR ROM64_INSTR_PT(300) OR ROM64_INSTR_PT(301) + OR ROM64_INSTR_PT(317) OR ROM64_INSTR_PT(318) + OR ROM64_INSTR_PT(326) OR ROM64_INSTR_PT(328) + OR ROM64_INSTR_PT(330) OR ROM64_INSTR_PT(331) + OR ROM64_INSTR_PT(335) OR ROM64_INSTR_PT(337) + OR ROM64_INSTR_PT(338) OR ROM64_INSTR_PT(344) + OR ROM64_INSTR_PT(350) OR ROM64_INSTR_PT(358) + OR ROM64_INSTR_PT(373) OR ROM64_INSTR_PT(379) + OR ROM64_INSTR_PT(393) OR ROM64_INSTR_PT(398) + OR ROM64_INSTR_PT(400) OR ROM64_INSTR_PT(421) + OR ROM64_INSTR_PT(438) OR ROM64_INSTR_PT(446) + OR ROM64_INSTR_PT(449) OR ROM64_INSTR_PT(465) + OR ROM64_INSTR_PT(476) OR ROM64_INSTR_PT(479) + OR ROM64_INSTR_PT(486) OR ROM64_INSTR_PT(500) + OR ROM64_INSTR_PT(526) OR ROM64_INSTR_PT(543) + OR ROM64_INSTR_PT(566) OR ROM64_INSTR_PT(577) + OR ROM64_INSTR_PT(581) OR ROM64_INSTR_PT(593) + OR ROM64_INSTR_PT(594) OR ROM64_INSTR_PT(604) + OR ROM64_INSTR_PT(624) OR ROM64_INSTR_PT(630) + OR ROM64_INSTR_PT(631) OR ROM64_INSTR_PT(652) + OR ROM64_INSTR_PT(669) OR ROM64_INSTR_PT(671) + OR ROM64_INSTR_PT(672) OR ROM64_INSTR_PT(673) + OR ROM64_INSTR_PT(674) OR ROM64_INSTR_PT(688) + OR ROM64_INSTR_PT(692) OR ROM64_INSTR_PT(694) + OR ROM64_INSTR_PT(697) OR ROM64_INSTR_PT(700) + OR ROM64_INSTR_PT(707) OR ROM64_INSTR_PT(708) + OR ROM64_INSTR_PT(710) OR ROM64_INSTR_PT(712) + OR ROM64_INSTR_PT(715) OR ROM64_INSTR_PT(720) + OR ROM64_INSTR_PT(725) OR ROM64_INSTR_PT(732) + OR ROM64_INSTR_PT(737) OR ROM64_INSTR_PT(741) + OR ROM64_INSTR_PT(743) OR ROM64_INSTR_PT(746) + OR ROM64_INSTR_PT(747) OR ROM64_INSTR_PT(749) + OR ROM64_INSTR_PT(750) OR ROM64_INSTR_PT(755) + OR ROM64_INSTR_PT(758) OR ROM64_INSTR_PT(762) + OR ROM64_INSTR_PT(763) OR ROM64_INSTR_PT(764) + OR ROM64_INSTR_PT(767) OR ROM64_INSTR_PT(771) + OR ROM64_INSTR_PT(774) OR ROM64_INSTR_PT(777) + OR ROM64_INSTR_PT(778) OR ROM64_INSTR_PT(780) + OR ROM64_INSTR_PT(782) OR ROM64_INSTR_PT(783) + OR ROM64_INSTR_PT(784) OR ROM64_INSTR_PT(786) + OR ROM64_INSTR_PT(793) OR ROM64_INSTR_PT(795) + OR ROM64_INSTR_PT(796) OR ROM64_INSTR_PT(806) + OR ROM64_INSTR_PT(810) OR ROM64_INSTR_PT(812) + OR ROM64_INSTR_PT(817) OR ROM64_INSTR_PT(820) + OR ROM64_INSTR_PT(821) OR ROM64_INSTR_PT(823) + OR ROM64_INSTR_PT(828) OR ROM64_INSTR_PT(835) + OR ROM64_INSTR_PT(836) OR ROM64_INSTR_PT(837) + OR ROM64_INSTR_PT(838) OR ROM64_INSTR_PT(842) + OR ROM64_INSTR_PT(843) OR ROM64_INSTR_PT(844) + OR ROM64_INSTR_PT(847) OR ROM64_INSTR_PT(848) + OR ROM64_INSTR_PT(849) OR ROM64_INSTR_PT(851) + OR ROM64_INSTR_PT(853) OR ROM64_INSTR_PT(859) + OR ROM64_INSTR_PT(861) OR ROM64_INSTR_PT(865) + OR ROM64_INSTR_PT(866) OR ROM64_INSTR_PT(867) + OR ROM64_INSTR_PT(871) OR ROM64_INSTR_PT(877) + OR ROM64_INSTR_PT(880)); +MQQ932:EXTS2 <= + (ROM64_INSTR_PT(23) OR ROM64_INSTR_PT(27) + OR ROM64_INSTR_PT(44) OR ROM64_INSTR_PT(47) + OR ROM64_INSTR_PT(88) OR ROM64_INSTR_PT(91) + OR ROM64_INSTR_PT(131) OR ROM64_INSTR_PT(138) + OR ROM64_INSTR_PT(140) OR ROM64_INSTR_PT(152) + OR ROM64_INSTR_PT(167) OR ROM64_INSTR_PT(178) + OR ROM64_INSTR_PT(182) OR ROM64_INSTR_PT(189) + OR ROM64_INSTR_PT(211) OR ROM64_INSTR_PT(298) + OR ROM64_INSTR_PT(318) OR ROM64_INSTR_PT(330) + OR ROM64_INSTR_PT(331) OR ROM64_INSTR_PT(335) + OR ROM64_INSTR_PT(337) OR ROM64_INSTR_PT(344) + OR ROM64_INSTR_PT(346) OR ROM64_INSTR_PT(350) + OR ROM64_INSTR_PT(356) OR ROM64_INSTR_PT(358) + OR ROM64_INSTR_PT(373) OR ROM64_INSTR_PT(380) + OR ROM64_INSTR_PT(384) OR ROM64_INSTR_PT(394) + OR ROM64_INSTR_PT(400) OR ROM64_INSTR_PT(418) + OR ROM64_INSTR_PT(432) OR ROM64_INSTR_PT(441) + OR ROM64_INSTR_PT(479) OR ROM64_INSTR_PT(500) + OR ROM64_INSTR_PT(516) OR ROM64_INSTR_PT(526) + OR ROM64_INSTR_PT(530) OR ROM64_INSTR_PT(542) + OR ROM64_INSTR_PT(577) OR ROM64_INSTR_PT(580) + OR ROM64_INSTR_PT(581) OR ROM64_INSTR_PT(591) + OR ROM64_INSTR_PT(604) OR ROM64_INSTR_PT(627) + OR ROM64_INSTR_PT(631) OR ROM64_INSTR_PT(652) + OR ROM64_INSTR_PT(672) OR ROM64_INSTR_PT(674) + OR ROM64_INSTR_PT(696) OR ROM64_INSTR_PT(697) + OR ROM64_INSTR_PT(700) OR ROM64_INSTR_PT(707) + OR ROM64_INSTR_PT(715) OR ROM64_INSTR_PT(718) + OR ROM64_INSTR_PT(725) OR ROM64_INSTR_PT(737) + OR ROM64_INSTR_PT(743) OR ROM64_INSTR_PT(744) + OR ROM64_INSTR_PT(745) OR ROM64_INSTR_PT(746) + OR ROM64_INSTR_PT(750) OR ROM64_INSTR_PT(754) + OR ROM64_INSTR_PT(756) OR ROM64_INSTR_PT(758) + OR ROM64_INSTR_PT(763) OR ROM64_INSTR_PT(765) + OR ROM64_INSTR_PT(767) OR ROM64_INSTR_PT(771) + OR ROM64_INSTR_PT(772) OR ROM64_INSTR_PT(774) + OR ROM64_INSTR_PT(776) OR ROM64_INSTR_PT(778) + OR ROM64_INSTR_PT(784) OR ROM64_INSTR_PT(786) + OR ROM64_INSTR_PT(812) OR ROM64_INSTR_PT(813) + OR ROM64_INSTR_PT(820) OR ROM64_INSTR_PT(823) + OR ROM64_INSTR_PT(828) OR ROM64_INSTR_PT(842) + OR ROM64_INSTR_PT(843) OR ROM64_INSTR_PT(848) + OR ROM64_INSTR_PT(854) OR ROM64_INSTR_PT(859) + OR ROM64_INSTR_PT(860) OR ROM64_INSTR_PT(863) + OR ROM64_INSTR_PT(866) OR ROM64_INSTR_PT(867) + OR ROM64_INSTR_PT(868) OR ROM64_INSTR_PT(877) + OR ROM64_INSTR_PT(880)); +MQQ933:EXTS3 <= + (ROM64_INSTR_PT(47) OR ROM64_INSTR_PT(94) + OR ROM64_INSTR_PT(100) OR ROM64_INSTR_PT(135) + OR ROM64_INSTR_PT(159) OR ROM64_INSTR_PT(163) + OR ROM64_INSTR_PT(192) OR ROM64_INSTR_PT(225) + OR ROM64_INSTR_PT(235) OR ROM64_INSTR_PT(251) + OR ROM64_INSTR_PT(279) OR ROM64_INSTR_PT(297) + OR ROM64_INSTR_PT(300) OR ROM64_INSTR_PT(326) + OR ROM64_INSTR_PT(337) OR ROM64_INSTR_PT(338) + OR ROM64_INSTR_PT(350) OR ROM64_INSTR_PT(358) + OR ROM64_INSTR_PT(379) OR ROM64_INSTR_PT(384) + OR ROM64_INSTR_PT(398) OR ROM64_INSTR_PT(413) + OR ROM64_INSTR_PT(446) OR ROM64_INSTR_PT(447) + OR ROM64_INSTR_PT(524) OR ROM64_INSTR_PT(526) + OR ROM64_INSTR_PT(561) OR ROM64_INSTR_PT(572) + OR ROM64_INSTR_PT(594) OR ROM64_INSTR_PT(630) + OR ROM64_INSTR_PT(670) OR ROM64_INSTR_PT(692) + OR ROM64_INSTR_PT(697) OR ROM64_INSTR_PT(712) + OR ROM64_INSTR_PT(715) OR ROM64_INSTR_PT(749) + OR ROM64_INSTR_PT(758) OR ROM64_INSTR_PT(778) + OR ROM64_INSTR_PT(798) OR ROM64_INSTR_PT(833) + OR ROM64_INSTR_PT(837) OR ROM64_INSTR_PT(838) + OR ROM64_INSTR_PT(871)); +MQQ934:SEL0_5 <= + (ROM64_INSTR_PT(652) OR ROM64_INSTR_PT(718) + ); +MQQ935:SEL6_10(0) <= + (ROM64_INSTR_PT(40) OR ROM64_INSTR_PT(69) + OR ROM64_INSTR_PT(82) OR ROM64_INSTR_PT(95) + OR ROM64_INSTR_PT(107) OR ROM64_INSTR_PT(200) + OR ROM64_INSTR_PT(211) OR ROM64_INSTR_PT(267) + OR ROM64_INSTR_PT(386) OR ROM64_INSTR_PT(443) + OR ROM64_INSTR_PT(444) OR ROM64_INSTR_PT(452) + OR ROM64_INSTR_PT(516) OR ROM64_INSTR_PT(528) + OR ROM64_INSTR_PT(529) OR ROM64_INSTR_PT(537) + OR ROM64_INSTR_PT(542) OR ROM64_INSTR_PT(550) + OR ROM64_INSTR_PT(560) OR ROM64_INSTR_PT(566) + OR ROM64_INSTR_PT(573) OR ROM64_INSTR_PT(581) + OR ROM64_INSTR_PT(604) OR ROM64_INSTR_PT(607) + OR ROM64_INSTR_PT(621) OR ROM64_INSTR_PT(661) + OR ROM64_INSTR_PT(698) OR ROM64_INSTR_PT(706) + OR ROM64_INSTR_PT(790) OR ROM64_INSTR_PT(823) + OR ROM64_INSTR_PT(854)); +MQQ936:SEL6_10(1) <= + (ROM64_INSTR_PT(1) OR ROM64_INSTR_PT(3) + OR ROM64_INSTR_PT(40) OR ROM64_INSTR_PT(54) + OR ROM64_INSTR_PT(67) OR ROM64_INSTR_PT(69) + OR ROM64_INSTR_PT(78) OR ROM64_INSTR_PT(82) + OR ROM64_INSTR_PT(95) OR ROM64_INSTR_PT(107) + OR ROM64_INSTR_PT(120) OR ROM64_INSTR_PT(182) + OR ROM64_INSTR_PT(188) OR ROM64_INSTR_PT(256) + OR ROM64_INSTR_PT(267) OR ROM64_INSTR_PT(287) + OR ROM64_INSTR_PT(336) OR ROM64_INSTR_PT(346) + OR ROM64_INSTR_PT(350) OR ROM64_INSTR_PT(354) + OR ROM64_INSTR_PT(358) OR ROM64_INSTR_PT(380) + OR ROM64_INSTR_PT(407) OR ROM64_INSTR_PT(431) + OR ROM64_INSTR_PT(436) OR ROM64_INSTR_PT(459) + OR ROM64_INSTR_PT(463) OR ROM64_INSTR_PT(487) + OR ROM64_INSTR_PT(529) OR ROM64_INSTR_PT(530) + OR ROM64_INSTR_PT(540) OR ROM64_INSTR_PT(580) + OR ROM64_INSTR_PT(605) OR ROM64_INSTR_PT(640) + OR ROM64_INSTR_PT(652) OR ROM64_INSTR_PT(658) + OR ROM64_INSTR_PT(694) OR ROM64_INSTR_PT(697) + OR ROM64_INSTR_PT(708) OR ROM64_INSTR_PT(715) + OR ROM64_INSTR_PT(718) OR ROM64_INSTR_PT(720) + OR ROM64_INSTR_PT(726) OR ROM64_INSTR_PT(727) + OR ROM64_INSTR_PT(740) OR ROM64_INSTR_PT(769) + OR ROM64_INSTR_PT(857) OR ROM64_INSTR_PT(864) + ); +MQQ937:SEL11_15(0) <= + (ROM64_INSTR_PT(37) OR ROM64_INSTR_PT(135) + OR ROM64_INSTR_PT(193) OR ROM64_INSTR_PT(232) + OR ROM64_INSTR_PT(248) OR ROM64_INSTR_PT(291) + OR ROM64_INSTR_PT(373) OR ROM64_INSTR_PT(384) + OR ROM64_INSTR_PT(438) OR ROM64_INSTR_PT(447) + OR ROM64_INSTR_PT(465) OR ROM64_INSTR_PT(593) + OR ROM64_INSTR_PT(663) OR ROM64_INSTR_PT(741) + OR ROM64_INSTR_PT(798) OR ROM64_INSTR_PT(829) + ); +MQQ938:SEL11_15(1) <= + (ROM64_INSTR_PT(24) OR ROM64_INSTR_PT(27) + OR ROM64_INSTR_PT(37) OR ROM64_INSTR_PT(44) + OR ROM64_INSTR_PT(48) OR ROM64_INSTR_PT(59) + OR ROM64_INSTR_PT(62) OR ROM64_INSTR_PT(63) + OR ROM64_INSTR_PT(85) OR ROM64_INSTR_PT(98) + OR ROM64_INSTR_PT(105) OR ROM64_INSTR_PT(115) + OR ROM64_INSTR_PT(123) OR ROM64_INSTR_PT(130) + OR ROM64_INSTR_PT(133) OR ROM64_INSTR_PT(140) + OR ROM64_INSTR_PT(141) OR ROM64_INSTR_PT(151) + OR ROM64_INSTR_PT(164) OR ROM64_INSTR_PT(189) + OR ROM64_INSTR_PT(192) OR ROM64_INSTR_PT(193) + OR ROM64_INSTR_PT(200) OR ROM64_INSTR_PT(220) + OR ROM64_INSTR_PT(232) OR ROM64_INSTR_PT(234) + OR ROM64_INSTR_PT(250) OR ROM64_INSTR_PT(253) + OR ROM64_INSTR_PT(266) OR ROM64_INSTR_PT(283) + OR ROM64_INSTR_PT(291) OR ROM64_INSTR_PT(303) + OR ROM64_INSTR_PT(323) OR ROM64_INSTR_PT(354) + OR ROM64_INSTR_PT(356) OR ROM64_INSTR_PT(373) + OR ROM64_INSTR_PT(386) OR ROM64_INSTR_PT(394) + OR ROM64_INSTR_PT(418) OR ROM64_INSTR_PT(423) + OR ROM64_INSTR_PT(432) OR ROM64_INSTR_PT(438) + OR ROM64_INSTR_PT(441) OR ROM64_INSTR_PT(444) + OR ROM64_INSTR_PT(452) OR ROM64_INSTR_PT(465) + OR ROM64_INSTR_PT(492) OR ROM64_INSTR_PT(516) + OR ROM64_INSTR_PT(524) OR ROM64_INSTR_PT(528) + OR ROM64_INSTR_PT(547) OR ROM64_INSTR_PT(550) + OR ROM64_INSTR_PT(560) OR ROM64_INSTR_PT(573) + OR ROM64_INSTR_PT(577) OR ROM64_INSTR_PT(591) + OR ROM64_INSTR_PT(593) OR ROM64_INSTR_PT(597) + OR ROM64_INSTR_PT(607) OR ROM64_INSTR_PT(621) + OR ROM64_INSTR_PT(627) OR ROM64_INSTR_PT(634) + OR ROM64_INSTR_PT(665) OR ROM64_INSTR_PT(698) + OR ROM64_INSTR_PT(706) OR ROM64_INSTR_PT(717) + OR ROM64_INSTR_PT(718) OR ROM64_INSTR_PT(734) + OR ROM64_INSTR_PT(790) OR ROM64_INSTR_PT(806) + OR ROM64_INSTR_PT(813) OR ROM64_INSTR_PT(824) + OR ROM64_INSTR_PT(828) OR ROM64_INSTR_PT(840) + OR ROM64_INSTR_PT(844) OR ROM64_INSTR_PT(849) + ); +MQQ939:SEL16_20(0) <= + (ROM64_INSTR_PT(6) OR ROM64_INSTR_PT(135) + OR ROM64_INSTR_PT(194) OR ROM64_INSTR_PT(258) + OR ROM64_INSTR_PT(260) OR ROM64_INSTR_PT(355) + OR ROM64_INSTR_PT(447) OR ROM64_INSTR_PT(533) + OR ROM64_INSTR_PT(798) OR ROM64_INSTR_PT(829) + ); +MQQ940:SEL16_20(1) <= + (ROM64_INSTR_PT(4) OR ROM64_INSTR_PT(12) + OR ROM64_INSTR_PT(16) OR ROM64_INSTR_PT(40) + OR ROM64_INSTR_PT(46) OR ROM64_INSTR_PT(48) + OR ROM64_INSTR_PT(69) OR ROM64_INSTR_PT(74) + OR ROM64_INSTR_PT(82) OR ROM64_INSTR_PT(87) + OR ROM64_INSTR_PT(95) OR ROM64_INSTR_PT(100) + OR ROM64_INSTR_PT(107) OR ROM64_INSTR_PT(126) + OR ROM64_INSTR_PT(133) OR ROM64_INSTR_PT(135) + OR ROM64_INSTR_PT(137) OR ROM64_INSTR_PT(141) + OR ROM64_INSTR_PT(159) OR ROM64_INSTR_PT(164) + OR ROM64_INSTR_PT(200) OR ROM64_INSTR_PT(204) + OR ROM64_INSTR_PT(225) OR ROM64_INSTR_PT(251) + OR ROM64_INSTR_PT(266) OR ROM64_INSTR_PT(267) + OR ROM64_INSTR_PT(279) OR ROM64_INSTR_PT(297) + OR ROM64_INSTR_PT(300) OR ROM64_INSTR_PT(319) + OR ROM64_INSTR_PT(321) OR ROM64_INSTR_PT(336) + OR ROM64_INSTR_PT(354) OR ROM64_INSTR_PT(355) + OR ROM64_INSTR_PT(362) OR ROM64_INSTR_PT(379) + OR ROM64_INSTR_PT(398) OR ROM64_INSTR_PT(413) + OR ROM64_INSTR_PT(423) OR ROM64_INSTR_PT(444) + OR ROM64_INSTR_PT(446) OR ROM64_INSTR_PT(447) + OR ROM64_INSTR_PT(452) OR ROM64_INSTR_PT(470) + OR ROM64_INSTR_PT(496) OR ROM64_INSTR_PT(513) + OR ROM64_INSTR_PT(524) OR ROM64_INSTR_PT(528) + OR ROM64_INSTR_PT(529) OR ROM64_INSTR_PT(541) + OR ROM64_INSTR_PT(550) OR ROM64_INSTR_PT(560) + OR ROM64_INSTR_PT(561) OR ROM64_INSTR_PT(566) + OR ROM64_INSTR_PT(572) OR ROM64_INSTR_PT(573) + OR ROM64_INSTR_PT(606) OR ROM64_INSTR_PT(607) + OR ROM64_INSTR_PT(615) OR ROM64_INSTR_PT(621) + OR ROM64_INSTR_PT(634) OR ROM64_INSTR_PT(648) + OR ROM64_INSTR_PT(661) OR ROM64_INSTR_PT(698) + OR ROM64_INSTR_PT(706) OR ROM64_INSTR_PT(717) + OR ROM64_INSTR_PT(729) OR ROM64_INSTR_PT(773) + OR ROM64_INSTR_PT(790) OR ROM64_INSTR_PT(798) + OR ROM64_INSTR_PT(829) OR ROM64_INSTR_PT(838) + ); +MQQ941:SEL21_25(0) <= + (ROM64_INSTR_PT(197)); +MQQ942:SEL21_25(1) <= + (ROM64_INSTR_PT(16) OR ROM64_INSTR_PT(46) + OR ROM64_INSTR_PT(48) OR ROM64_INSTR_PT(63) + OR ROM64_INSTR_PT(74) OR ROM64_INSTR_PT(87) + OR ROM64_INSTR_PT(141) OR ROM64_INSTR_PT(200) + OR ROM64_INSTR_PT(225) OR ROM64_INSTR_PT(266) + OR ROM64_INSTR_PT(321) OR ROM64_INSTR_PT(354) + OR ROM64_INSTR_PT(362) OR ROM64_INSTR_PT(423) + OR ROM64_INSTR_PT(452) OR ROM64_INSTR_PT(470) + OR ROM64_INSTR_PT(515) OR ROM64_INSTR_PT(528) + OR ROM64_INSTR_PT(541) OR ROM64_INSTR_PT(550) + OR ROM64_INSTR_PT(560) OR ROM64_INSTR_PT(572) + OR ROM64_INSTR_PT(573) OR ROM64_INSTR_PT(634) + OR ROM64_INSTR_PT(652) OR ROM64_INSTR_PT(706) + OR ROM64_INSTR_PT(718) OR ROM64_INSTR_PT(729) + OR ROM64_INSTR_PT(734) OR ROM64_INSTR_PT(790) + ); +MQQ943:SEL26_30 <= + (ROM64_INSTR_PT(16) OR ROM64_INSTR_PT(46) + OR ROM64_INSTR_PT(48) OR ROM64_INSTR_PT(63) + OR ROM64_INSTR_PT(74) OR ROM64_INSTR_PT(87) + OR ROM64_INSTR_PT(141) OR ROM64_INSTR_PT(200) + OR ROM64_INSTR_PT(225) OR ROM64_INSTR_PT(266) + OR ROM64_INSTR_PT(321) OR ROM64_INSTR_PT(354) + OR ROM64_INSTR_PT(362) OR ROM64_INSTR_PT(423) + OR ROM64_INSTR_PT(452) OR ROM64_INSTR_PT(470) + OR ROM64_INSTR_PT(515) OR ROM64_INSTR_PT(528) + OR ROM64_INSTR_PT(541) OR ROM64_INSTR_PT(550) + OR ROM64_INSTR_PT(560) OR ROM64_INSTR_PT(572) + OR ROM64_INSTR_PT(573) OR ROM64_INSTR_PT(634) + OR ROM64_INSTR_PT(652) OR ROM64_INSTR_PT(706) + OR ROM64_INSTR_PT(718) OR ROM64_INSTR_PT(729) + OR ROM64_INSTR_PT(734) OR ROM64_INSTR_PT(790) + ); +MQQ944:SEL31 <= + (ROM64_INSTR_PT(16) OR ROM64_INSTR_PT(46) + OR ROM64_INSTR_PT(63) OR ROM64_INSTR_PT(74) + OR ROM64_INSTR_PT(87) OR ROM64_INSTR_PT(141) + OR ROM64_INSTR_PT(200) OR ROM64_INSTR_PT(266) + OR ROM64_INSTR_PT(321) OR ROM64_INSTR_PT(350) + OR ROM64_INSTR_PT(354) OR ROM64_INSTR_PT(358) + OR ROM64_INSTR_PT(362) OR ROM64_INSTR_PT(423) + OR ROM64_INSTR_PT(452) OR ROM64_INSTR_PT(470) + OR ROM64_INSTR_PT(541) OR ROM64_INSTR_PT(542) + OR ROM64_INSTR_PT(560) OR ROM64_INSTR_PT(561) + OR ROM64_INSTR_PT(573) OR ROM64_INSTR_PT(634) + OR ROM64_INSTR_PT(652) OR ROM64_INSTR_PT(697) + OR ROM64_INSTR_PT(706) OR ROM64_INSTR_PT(715) + OR ROM64_INSTR_PT(718) OR ROM64_INSTR_PT(729) + OR ROM64_INSTR_PT(790) OR ROM64_INSTR_PT(823) + ); +MQQ945:CR_BF2FXM <= + (ROM64_INSTR_PT(717)); +MQQ946:SKIP_COND <= + (ROM64_INSTR_PT(23) OR ROM64_INSTR_PT(34) + OR ROM64_INSTR_PT(81) OR ROM64_INSTR_PT(88) + OR ROM64_INSTR_PT(91) OR ROM64_INSTR_PT(127) + OR ROM64_INSTR_PT(298) OR ROM64_INSTR_PT(330) + OR ROM64_INSTR_PT(331) OR ROM64_INSTR_PT(335) + OR ROM64_INSTR_PT(344) OR ROM64_INSTR_PT(369) + OR ROM64_INSTR_PT(489) OR ROM64_INSTR_PT(662) + OR ROM64_INSTR_PT(667) OR ROM64_INSTR_PT(677) + OR ROM64_INSTR_PT(684) OR ROM64_INSTR_PT(725) + OR ROM64_INSTR_PT(744) OR ROM64_INSTR_PT(745) + OR ROM64_INSTR_PT(746) OR ROM64_INSTR_PT(747) + OR ROM64_INSTR_PT(748) OR ROM64_INSTR_PT(750) + OR ROM64_INSTR_PT(754) OR ROM64_INSTR_PT(755) + OR ROM64_INSTR_PT(756) OR ROM64_INSTR_PT(765) + OR ROM64_INSTR_PT(776) OR ROM64_INSTR_PT(782) + OR ROM64_INSTR_PT(783) OR ROM64_INSTR_PT(784) + OR ROM64_INSTR_PT(792) OR ROM64_INSTR_PT(795) + OR ROM64_INSTR_PT(796) OR ROM64_INSTR_PT(804) + OR ROM64_INSTR_PT(817) OR ROM64_INSTR_PT(819) + OR ROM64_INSTR_PT(820) OR ROM64_INSTR_PT(821) + OR ROM64_INSTR_PT(827) OR ROM64_INSTR_PT(842) + OR ROM64_INSTR_PT(859) OR ROM64_INSTR_PT(867) + ); +MQQ947:SKIP_ZERO <= + (ROM64_INSTR_PT(301) OR ROM64_INSTR_PT(319) + OR ROM64_INSTR_PT(393) OR ROM64_INSTR_PT(436) + OR ROM64_INSTR_PT(487) OR ROM64_INSTR_PT(496) + OR ROM64_INSTR_PT(778)); +MQQ948:LOOP_ADDR(0) <= + (ROM64_INSTR_PT(235) OR ROM64_INSTR_PT(289) + OR ROM64_INSTR_PT(301) OR ROM64_INSTR_PT(317) + OR ROM64_INSTR_PT(328) OR ROM64_INSTR_PT(373) + OR ROM64_INSTR_PT(479) OR ROM64_INSTR_PT(526) + OR ROM64_INSTR_PT(674) OR ROM64_INSTR_PT(692) + OR ROM64_INSTR_PT(700) OR ROM64_INSTR_PT(732) + OR ROM64_INSTR_PT(743) OR ROM64_INSTR_PT(777) + OR ROM64_INSTR_PT(778) OR ROM64_INSTR_PT(784) + OR ROM64_INSTR_PT(837) OR ROM64_INSTR_PT(861) + OR ROM64_INSTR_PT(866) OR ROM64_INSTR_PT(867) + ); +MQQ949:LOOP_ADDR(1) <= + (ROM64_INSTR_PT(289) OR ROM64_INSTR_PT(479) + OR ROM64_INSTR_PT(526) OR ROM64_INSTR_PT(674) + OR ROM64_INSTR_PT(732) OR ROM64_INSTR_PT(777) + OR ROM64_INSTR_PT(784) OR ROM64_INSTR_PT(833) + OR ROM64_INSTR_PT(837) OR ROM64_INSTR_PT(859) + OR ROM64_INSTR_PT(867)); +MQQ950:LOOP_ADDR(2) <= + (ROM64_INSTR_PT(393) OR ROM64_INSTR_PT(449) + OR ROM64_INSTR_PT(486) OR ROM64_INSTR_PT(700) + OR ROM64_INSTR_PT(743) OR ROM64_INSTR_PT(748) + OR ROM64_INSTR_PT(754) OR ROM64_INSTR_PT(764) + ); +MQQ951:LOOP_ADDR(3) <= + (ROM64_INSTR_PT(317) OR ROM64_INSTR_PT(328) + OR ROM64_INSTR_PT(501) OR ROM64_INSTR_PT(672) + OR ROM64_INSTR_PT(688) OR ROM64_INSTR_PT(700) + OR ROM64_INSTR_PT(707) OR ROM64_INSTR_PT(725) + OR ROM64_INSTR_PT(743) OR ROM64_INSTR_PT(765) + OR ROM64_INSTR_PT(767) OR ROM64_INSTR_PT(777) + OR ROM64_INSTR_PT(836) OR ROM64_INSTR_PT(837) + OR ROM64_INSTR_PT(859) OR ROM64_INSTR_PT(867) + OR ROM64_INSTR_PT(878)); +MQQ952:LOOP_ADDR(4) <= + (ROM64_INSTR_PT(37) OR ROM64_INSTR_PT(289) + OR ROM64_INSTR_PT(301) OR ROM64_INSTR_PT(328) + OR ROM64_INSTR_PT(373) OR ROM64_INSTR_PT(400) + OR ROM64_INSTR_PT(421) OR ROM64_INSTR_PT(449) + OR ROM64_INSTR_PT(479) OR ROM64_INSTR_PT(700) + OR ROM64_INSTR_PT(743) OR ROM64_INSTR_PT(748) + OR ROM64_INSTR_PT(750) OR ROM64_INSTR_PT(754) + OR ROM64_INSTR_PT(762) OR ROM64_INSTR_PT(784) + OR ROM64_INSTR_PT(837) OR ROM64_INSTR_PT(866) + OR ROM64_INSTR_PT(867)); +MQQ953:LOOP_ADDR(5) <= + (ROM64_INSTR_PT(37) OR ROM64_INSTR_PT(235) + OR ROM64_INSTR_PT(289) OR ROM64_INSTR_PT(421) + OR ROM64_INSTR_PT(449) OR ROM64_INSTR_PT(526) + OR ROM64_INSTR_PT(688) OR ROM64_INSTR_PT(725) + OR ROM64_INSTR_PT(743) OR ROM64_INSTR_PT(764) + OR ROM64_INSTR_PT(772) OR ROM64_INSTR_PT(861) + OR ROM64_INSTR_PT(866)); +MQQ954:LOOP_ADDR(6) <= + (ROM64_INSTR_PT(37) OR ROM64_INSTR_PT(163) + OR ROM64_INSTR_PT(289) OR ROM64_INSTR_PT(317) + OR ROM64_INSTR_PT(373) OR ROM64_INSTR_PT(486) + OR ROM64_INSTR_PT(672) OR ROM64_INSTR_PT(696) + OR ROM64_INSTR_PT(700) OR ROM64_INSTR_PT(748) + OR ROM64_INSTR_PT(750) OR ROM64_INSTR_PT(764) + OR ROM64_INSTR_PT(767) OR ROM64_INSTR_PT(833) + OR ROM64_INSTR_PT(837) OR ROM64_INSTR_PT(859) + OR ROM64_INSTR_PT(861) OR ROM64_INSTR_PT(868) + ); +MQQ955:LOOP_ADDR(7) <= + (ROM64_INSTR_PT(37) OR ROM64_INSTR_PT(289) + OR ROM64_INSTR_PT(301) OR ROM64_INSTR_PT(317) + OR ROM64_INSTR_PT(328) OR ROM64_INSTR_PT(400) + OR ROM64_INSTR_PT(421) OR ROM64_INSTR_PT(486) + OR ROM64_INSTR_PT(651) OR ROM64_INSTR_PT(672) + OR ROM64_INSTR_PT(674) OR ROM64_INSTR_PT(692) + OR ROM64_INSTR_PT(725) OR ROM64_INSTR_PT(732) + OR ROM64_INSTR_PT(743) OR ROM64_INSTR_PT(748) + OR ROM64_INSTR_PT(777) OR ROM64_INSTR_PT(861) + OR ROM64_INSTR_PT(867)); +MQQ956:LOOP_ADDR(8) <= + (ROM64_INSTR_PT(400) OR ROM64_INSTR_PT(421) + OR ROM64_INSTR_PT(449) OR ROM64_INSTR_PT(479) + OR ROM64_INSTR_PT(486) OR ROM64_INSTR_PT(672) + OR ROM64_INSTR_PT(696) OR ROM64_INSTR_PT(700) + OR ROM64_INSTR_PT(707) OR ROM64_INSTR_PT(725) + OR ROM64_INSTR_PT(748) OR ROM64_INSTR_PT(750) + OR ROM64_INSTR_PT(754) OR ROM64_INSTR_PT(762) + OR ROM64_INSTR_PT(764) OR ROM64_INSTR_PT(777) + OR ROM64_INSTR_PT(861) OR ROM64_INSTR_PT(866) + ); +MQQ957:LOOP_ADDR(9) <= + (ROM64_INSTR_PT(301) OR ROM64_INSTR_PT(317) + OR ROM64_INSTR_PT(328) OR ROM64_INSTR_PT(373) + OR ROM64_INSTR_PT(393) OR ROM64_INSTR_PT(449) + OR ROM64_INSTR_PT(486) OR ROM64_INSTR_PT(692) + OR ROM64_INSTR_PT(743) OR ROM64_INSTR_PT(764) + OR ROM64_INSTR_PT(772) OR ROM64_INSTR_PT(778) + OR ROM64_INSTR_PT(784) OR ROM64_INSTR_PT(836) + OR ROM64_INSTR_PT(837) OR ROM64_INSTR_PT(861) + ); +MQQ958:LOOP_INIT(0) <= + (ROM64_INSTR_PT(235) OR ROM64_INSTR_PT(369) + OR ROM64_INSTR_PT(398) OR ROM64_INSTR_PT(572) + OR ROM64_INSTR_PT(673) OR ROM64_INSTR_PT(692) + OR ROM64_INSTR_PT(783) OR ROM64_INSTR_PT(795) + OR ROM64_INSTR_PT(810) OR ROM64_INSTR_PT(817) + OR ROM64_INSTR_PT(821) OR ROM64_INSTR_PT(837) + OR ROM64_INSTR_PT(859) OR ROM64_INSTR_PT(867) + ); +MQQ959:LOOP_INIT(1) <= + (ROM64_INSTR_PT(890)); +MQQ960:LOOP_INIT(2) <= + (ROM64_INSTR_PT(783) OR ROM64_INSTR_PT(817) + OR ROM64_INSTR_PT(859) OR ROM64_INSTR_PT(867) + ); +MQQ961:EP <= + (ROM64_INSTR_PT(44) OR ROM64_INSTR_PT(59) + OR ROM64_INSTR_PT(115) OR ROM64_INSTR_PT(137) + OR ROM64_INSTR_PT(279) OR ROM64_INSTR_PT(297) + OR ROM64_INSTR_PT(356) OR ROM64_INSTR_PT(394) + OR ROM64_INSTR_PT(398) OR ROM64_INSTR_PT(432) + OR ROM64_INSTR_PT(441) OR ROM64_INSTR_PT(446) + OR ROM64_INSTR_PT(524) OR ROM64_INSTR_PT(561) + ); + +end generate; +c32: if (regmode = 5) generate +begin + +ROM64_INSTR_PT <= (others => '0'); +rom_unused <= or_reduce(ROM64_INSTR_PT); +MQQ962:ROM32_INSTR_PT(1) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("100000000")); +MQQ963:ROM32_INSTR_PT(2) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011000000")); +MQQ964:ROM32_INSTR_PT(3) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("101000000")); +MQQ965:ROM32_INSTR_PT(4) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000000000")); +MQQ966:ROM32_INSTR_PT(5) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110000000")); +MQQ967:ROM32_INSTR_PT(6) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011000000")); +MQQ968:ROM32_INSTR_PT(7) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00100000")); +MQQ969:ROM32_INSTR_PT(8) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001100000")); +MQQ970:ROM32_INSTR_PT(9) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011100000")); +MQQ971:ROM32_INSTR_PT(10) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01100000")); +MQQ972:ROM32_INSTR_PT(11) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00000000")); +MQQ973:ROM32_INSTR_PT(12) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11000000")); +MQQ974:ROM32_INSTR_PT(13) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001010000")); +MQQ975:ROM32_INSTR_PT(14) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011010000")); +MQQ976:ROM32_INSTR_PT(15) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("101010000")); +MQQ977:ROM32_INSTR_PT(16) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000110000")); +MQQ978:ROM32_INSTR_PT(17) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10110000")); +MQQ979:ROM32_INSTR_PT(18) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011110000")); +MQQ980:ROM32_INSTR_PT(19) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10110000")); +MQQ981:ROM32_INSTR_PT(20) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110000")); +MQQ982:ROM32_INSTR_PT(21) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000010000")); +MQQ983:ROM32_INSTR_PT(22) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110000")); +MQQ984:ROM32_INSTR_PT(23) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110000")); +MQQ985:ROM32_INSTR_PT(24) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11000000")); +MQQ986:ROM32_INSTR_PT(25) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000100000")); +MQQ987:ROM32_INSTR_PT(26) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010010000")); +MQQ988:ROM32_INSTR_PT(27) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10010000")); +MQQ989:ROM32_INSTR_PT(28) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110000")); +MQQ990:ROM32_INSTR_PT(29) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110000")); +MQQ991:ROM32_INSTR_PT(30) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1110000")); +MQQ992:ROM32_INSTR_PT(31) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10010000")); +MQQ993:ROM32_INSTR_PT(32) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1010000")); +MQQ994:ROM32_INSTR_PT(33) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1110000")); +MQQ995:ROM32_INSTR_PT(34) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000001000")); +MQQ996:ROM32_INSTR_PT(35) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10001000")); +MQQ997:ROM32_INSTR_PT(36) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("101001000")); +MQQ998:ROM32_INSTR_PT(37) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110001000")); +MQQ999:ROM32_INSTR_PT(38) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01001000")); +MQQ1000:ROM32_INSTR_PT(39) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("100101000")); +MQQ1001:ROM32_INSTR_PT(40) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110101000")); +MQQ1002:ROM32_INSTR_PT(41) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001101000")); +MQQ1003:ROM32_INSTR_PT(42) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011101000")); +MQQ1004:ROM32_INSTR_PT(43) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011101000")); +MQQ1005:ROM32_INSTR_PT(44) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000101000")); +MQQ1006:ROM32_INSTR_PT(45) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("111101000")); +MQQ1007:ROM32_INSTR_PT(46) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000001000")); +MQQ1008:ROM32_INSTR_PT(47) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1101000")); +MQQ1009:ROM32_INSTR_PT(48) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001011000")); +MQQ1010:ROM32_INSTR_PT(49) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011011000")); +MQQ1011:ROM32_INSTR_PT(50) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011011000")); +MQQ1012:ROM32_INSTR_PT(51) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000111000")); +MQQ1013:ROM32_INSTR_PT(52) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110111000")); +MQQ1014:ROM32_INSTR_PT(53) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01111000")); +MQQ1015:ROM32_INSTR_PT(54) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010011000")); +MQQ1016:ROM32_INSTR_PT(55) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110111000")); +MQQ1017:ROM32_INSTR_PT(56) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10111000")); +MQQ1018:ROM32_INSTR_PT(57) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01111000")); +MQQ1019:ROM32_INSTR_PT(58) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("111000")); +MQQ1020:ROM32_INSTR_PT(59) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010001000")); +MQQ1021:ROM32_INSTR_PT(60) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01001000")); +MQQ1022:ROM32_INSTR_PT(61) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000011000")); +MQQ1023:ROM32_INSTR_PT(62) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00011000")); +MQQ1024:ROM32_INSTR_PT(63) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("100111000")); +MQQ1025:ROM32_INSTR_PT(64) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110111000")); +MQQ1026:ROM32_INSTR_PT(65) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000000000")); +MQQ1027:ROM32_INSTR_PT(66) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10000000")); +MQQ1028:ROM32_INSTR_PT(67) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01000000")); +MQQ1029:ROM32_INSTR_PT(68) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10000000")); +MQQ1030:ROM32_INSTR_PT(69) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10010000")); +MQQ1031:ROM32_INSTR_PT(70) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1010000")); +MQQ1032:ROM32_INSTR_PT(71) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110000")); +MQQ1033:ROM32_INSTR_PT(72) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1010000")); +MQQ1034:ROM32_INSTR_PT(73) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000001000")); +MQQ1035:ROM32_INSTR_PT(74) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01011000")); +MQQ1036:ROM32_INSTR_PT(75) <= + Eq(( ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000")); +MQQ1037:ROM32_INSTR_PT(76) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001000100")); +MQQ1038:ROM32_INSTR_PT(77) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("1101000100")); +MQQ1039:ROM32_INSTR_PT(78) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011000100")); +MQQ1040:ROM32_INSTR_PT(79) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011000100")); +MQQ1041:ROM32_INSTR_PT(80) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011000100")); +MQQ1042:ROM32_INSTR_PT(81) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10000100")); +MQQ1043:ROM32_INSTR_PT(82) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110100100")); +MQQ1044:ROM32_INSTR_PT(83) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001100100")); +MQQ1045:ROM32_INSTR_PT(84) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011100100")); +MQQ1046:ROM32_INSTR_PT(85) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11100100")); +MQQ1047:ROM32_INSTR_PT(86) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10100100")); +MQQ1048:ROM32_INSTR_PT(87) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000000100")); +MQQ1049:ROM32_INSTR_PT(88) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10000100")); +MQQ1050:ROM32_INSTR_PT(89) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110100100")); +MQQ1051:ROM32_INSTR_PT(90) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110010100")); +MQQ1052:ROM32_INSTR_PT(91) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001010100")); +MQQ1053:ROM32_INSTR_PT(92) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010010100")); +MQQ1054:ROM32_INSTR_PT(93) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01010100")); +MQQ1055:ROM32_INSTR_PT(94) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000110100")); +MQQ1056:ROM32_INSTR_PT(95) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10110100")); +MQQ1057:ROM32_INSTR_PT(96) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000110100")); +MQQ1058:ROM32_INSTR_PT(97) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110100")); +MQQ1059:ROM32_INSTR_PT(98) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00010100")); +MQQ1060:ROM32_INSTR_PT(99) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000110100")); +MQQ1061:ROM32_INSTR_PT(100) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110100")); +MQQ1062:ROM32_INSTR_PT(101) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110100")); +MQQ1063:ROM32_INSTR_PT(102) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010000100")); +MQQ1064:ROM32_INSTR_PT(103) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01000100")); +MQQ1065:ROM32_INSTR_PT(104) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10010100")); +MQQ1066:ROM32_INSTR_PT(105) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110100")); +MQQ1067:ROM32_INSTR_PT(106) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1010100")); +MQQ1068:ROM32_INSTR_PT(107) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1110100")); +MQQ1069:ROM32_INSTR_PT(108) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001001100")); +MQQ1070:ROM32_INSTR_PT(109) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("001001100")); +MQQ1071:ROM32_INSTR_PT(110) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11001100")); +MQQ1072:ROM32_INSTR_PT(111) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011001100")); +MQQ1073:ROM32_INSTR_PT(112) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11001100")); +MQQ1074:ROM32_INSTR_PT(113) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000101100")); +MQQ1075:ROM32_INSTR_PT(114) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("100101100")); +MQQ1076:ROM32_INSTR_PT(115) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010101100")); +MQQ1077:ROM32_INSTR_PT(116) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110101100")); +MQQ1078:ROM32_INSTR_PT(117) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011101100")); +MQQ1079:ROM32_INSTR_PT(118) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01101100")); +MQQ1080:ROM32_INSTR_PT(119) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01101100")); +MQQ1081:ROM32_INSTR_PT(120) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110011100")); +MQQ1082:ROM32_INSTR_PT(121) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11011100")); +MQQ1083:ROM32_INSTR_PT(122) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011011100")); +MQQ1084:ROM32_INSTR_PT(123) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11111100")); +MQQ1085:ROM32_INSTR_PT(124) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110111100")); +MQQ1086:ROM32_INSTR_PT(125) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01111100")); +MQQ1087:ROM32_INSTR_PT(126) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11111100")); +MQQ1088:ROM32_INSTR_PT(127) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000011100")); +MQQ1089:ROM32_INSTR_PT(128) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000111100")); +MQQ1090:ROM32_INSTR_PT(129) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11111100")); +MQQ1091:ROM32_INSTR_PT(130) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01111100")); +MQQ1092:ROM32_INSTR_PT(131) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10001100")); +MQQ1093:ROM32_INSTR_PT(132) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11101100")); +MQQ1094:ROM32_INSTR_PT(133) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1101100")); +MQQ1095:ROM32_INSTR_PT(134) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000111100")); +MQQ1096:ROM32_INSTR_PT(135) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10111100")); +MQQ1097:ROM32_INSTR_PT(136) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("011100")); +MQQ1098:ROM32_INSTR_PT(137) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0100100")); +MQQ1099:ROM32_INSTR_PT(138) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11010100")); +MQQ1100:ROM32_INSTR_PT(139) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1010100")); +MQQ1101:ROM32_INSTR_PT(140) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000001100")); +MQQ1102:ROM32_INSTR_PT(141) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010001100")); +MQQ1103:ROM32_INSTR_PT(142) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1101100")); +MQQ1104:ROM32_INSTR_PT(143) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01011100")); +MQQ1105:ROM32_INSTR_PT(144) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01111100")); +MQQ1106:ROM32_INSTR_PT(145) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0101100")); +MQQ1107:ROM32_INSTR_PT(146) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1001100")); +MQQ1108:ROM32_INSTR_PT(147) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11000000")); +MQQ1109:ROM32_INSTR_PT(148) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01010000")); +MQQ1110:ROM32_INSTR_PT(149) <= + Eq(( ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("010000")); +MQQ1111:ROM32_INSTR_PT(150) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01001000")); +MQQ1112:ROM32_INSTR_PT(151) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1001000")); +MQQ1113:ROM32_INSTR_PT(152) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("1000")); +MQQ1114:ROM32_INSTR_PT(153) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000000100")); +MQQ1115:ROM32_INSTR_PT(154) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01000100")); +MQQ1116:ROM32_INSTR_PT(155) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10100100")); +MQQ1117:ROM32_INSTR_PT(156) <= + Eq(( ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("00100")); +MQQ1118:ROM32_INSTR_PT(157) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("010100")); +MQQ1119:ROM32_INSTR_PT(158) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01111100")); +MQQ1120:ROM32_INSTR_PT(159) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11111100")); +MQQ1121:ROM32_INSTR_PT(160) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10011100")); +MQQ1122:ROM32_INSTR_PT(161) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1111100")); +MQQ1123:ROM32_INSTR_PT(162) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10011100")); +MQQ1124:ROM32_INSTR_PT(163) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0111100")); +MQQ1125:ROM32_INSTR_PT(164) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1000100")); +MQQ1126:ROM32_INSTR_PT(165) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0101100")); +MQQ1127:ROM32_INSTR_PT(166) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1101100")); +MQQ1128:ROM32_INSTR_PT(167) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("01100")); +MQQ1129:ROM32_INSTR_PT(168) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("10100")); +MQQ1130:ROM32_INSTR_PT(169) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("1101000010")); +MQQ1131:ROM32_INSTR_PT(170) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011000010")); +MQQ1132:ROM32_INSTR_PT(171) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("101000010")); +MQQ1133:ROM32_INSTR_PT(172) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011000010")); +MQQ1134:ROM32_INSTR_PT(173) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110100010")); +MQQ1135:ROM32_INSTR_PT(174) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011100010")); +MQQ1136:ROM32_INSTR_PT(175) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000000010")); +MQQ1137:ROM32_INSTR_PT(176) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1100010")); +MQQ1138:ROM32_INSTR_PT(177) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010010010")); +MQQ1139:ROM32_INSTR_PT(178) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10110010")); +MQQ1140:ROM32_INSTR_PT(179) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("001110010")); +MQQ1141:ROM32_INSTR_PT(180) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11110010")); +MQQ1142:ROM32_INSTR_PT(181) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110010")); +MQQ1143:ROM32_INSTR_PT(182) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11010010")); +MQQ1144:ROM32_INSTR_PT(183) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11010010")); +MQQ1145:ROM32_INSTR_PT(184) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000110010")); +MQQ1146:ROM32_INSTR_PT(185) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110010")); +MQQ1147:ROM32_INSTR_PT(186) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110010")); +MQQ1148:ROM32_INSTR_PT(187) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010000010")); +MQQ1149:ROM32_INSTR_PT(188) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11000010")); +MQQ1150:ROM32_INSTR_PT(189) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01100010")); +MQQ1151:ROM32_INSTR_PT(190) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1100010")); +MQQ1152:ROM32_INSTR_PT(191) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("000010")); +MQQ1153:ROM32_INSTR_PT(192) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010010010")); +MQQ1154:ROM32_INSTR_PT(193) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000110010")); +MQQ1155:ROM32_INSTR_PT(194) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110010")); +MQQ1156:ROM32_INSTR_PT(195) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1110010")); +MQQ1157:ROM32_INSTR_PT(196) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110010")); +MQQ1158:ROM32_INSTR_PT(197) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11110010")); +MQQ1159:ROM32_INSTR_PT(198) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1010010")); +MQQ1160:ROM32_INSTR_PT(199) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000001010")); +MQQ1161:ROM32_INSTR_PT(200) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10001010")); +MQQ1162:ROM32_INSTR_PT(201) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("1101001010")); +MQQ1163:ROM32_INSTR_PT(202) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("001001010")); +MQQ1164:ROM32_INSTR_PT(203) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011001010")); +MQQ1165:ROM32_INSTR_PT(204) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10001010")); +MQQ1166:ROM32_INSTR_PT(205) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0100101010")); +MQQ1167:ROM32_INSTR_PT(206) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011101010")); +MQQ1168:ROM32_INSTR_PT(207) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011101010")); +MQQ1169:ROM32_INSTR_PT(208) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110101010")); +MQQ1170:ROM32_INSTR_PT(209) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000101010")); +MQQ1171:ROM32_INSTR_PT(210) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10101010")); +MQQ1172:ROM32_INSTR_PT(211) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00001010")); +MQQ1173:ROM32_INSTR_PT(212) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110011010")); +MQQ1174:ROM32_INSTR_PT(213) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10011010")); +MQQ1175:ROM32_INSTR_PT(214) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11011010")); +MQQ1176:ROM32_INSTR_PT(215) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011011010")); +MQQ1177:ROM32_INSTR_PT(216) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00111010")); +MQQ1178:ROM32_INSTR_PT(217) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10111010")); +MQQ1179:ROM32_INSTR_PT(218) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011111010")); +MQQ1180:ROM32_INSTR_PT(219) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10111010")); +MQQ1181:ROM32_INSTR_PT(220) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01111010")); +MQQ1182:ROM32_INSTR_PT(221) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01011010")); +MQQ1183:ROM32_INSTR_PT(222) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("100111010")); +MQQ1184:ROM32_INSTR_PT(223) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110111010")); +MQQ1185:ROM32_INSTR_PT(224) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01111010")); +MQQ1186:ROM32_INSTR_PT(225) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000101010")); +MQQ1187:ROM32_INSTR_PT(226) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01011010")); +MQQ1188:ROM32_INSTR_PT(227) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10011010")); +MQQ1189:ROM32_INSTR_PT(228) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000100010")); +MQQ1190:ROM32_INSTR_PT(229) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01100010")); +MQQ1191:ROM32_INSTR_PT(230) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1010010")); +MQQ1192:ROM32_INSTR_PT(231) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000001010")); +MQQ1193:ROM32_INSTR_PT(232) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010001010")); +MQQ1194:ROM32_INSTR_PT(233) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1101010")); +MQQ1195:ROM32_INSTR_PT(234) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011010")); +MQQ1196:ROM32_INSTR_PT(235) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01011010")); +MQQ1197:ROM32_INSTR_PT(236) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("011010")); +MQQ1198:ROM32_INSTR_PT(237) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110000110")); +MQQ1199:ROM32_INSTR_PT(238) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001000110")); +MQQ1200:ROM32_INSTR_PT(239) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("1101000110")); +MQQ1201:ROM32_INSTR_PT(240) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11000110")); +MQQ1202:ROM32_INSTR_PT(241) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("101000110")); +MQQ1203:ROM32_INSTR_PT(242) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("111000110")); +MQQ1204:ROM32_INSTR_PT(243) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011000110")); +MQQ1205:ROM32_INSTR_PT(244) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0000100110")); +MQQ1206:ROM32_INSTR_PT(245) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("001100110")); +MQQ1207:ROM32_INSTR_PT(246) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000000110")); +MQQ1208:ROM32_INSTR_PT(247) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01000110")); +MQQ1209:ROM32_INSTR_PT(248) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10100110")); +MQQ1210:ROM32_INSTR_PT(249) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01100110")); +MQQ1211:ROM32_INSTR_PT(250) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110010110")); +MQQ1212:ROM32_INSTR_PT(251) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001010110")); +MQQ1213:ROM32_INSTR_PT(252) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011010110")); +MQQ1214:ROM32_INSTR_PT(253) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000110110")); +MQQ1215:ROM32_INSTR_PT(254) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110110")); +MQQ1216:ROM32_INSTR_PT(255) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("100110110")); +MQQ1217:ROM32_INSTR_PT(256) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110110")); +MQQ1218:ROM32_INSTR_PT(257) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110110")); +MQQ1219:ROM32_INSTR_PT(258) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1100110")); +MQQ1220:ROM32_INSTR_PT(259) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010010110")); +MQQ1221:ROM32_INSTR_PT(260) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("100110110")); +MQQ1222:ROM32_INSTR_PT(261) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110110")); +MQQ1223:ROM32_INSTR_PT(262) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110110")); +MQQ1224:ROM32_INSTR_PT(263) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1010110")); +MQQ1225:ROM32_INSTR_PT(264) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0100001110")); +MQQ1226:ROM32_INSTR_PT(265) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010001110")); +MQQ1227:ROM32_INSTR_PT(266) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110001110")); +MQQ1228:ROM32_INSTR_PT(267) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011001110")); +MQQ1229:ROM32_INSTR_PT(268) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011001110")); +MQQ1230:ROM32_INSTR_PT(269) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0000101110")); +MQQ1231:ROM32_INSTR_PT(270) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("100101110")); +MQQ1232:ROM32_INSTR_PT(271) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011101110")); +MQQ1233:ROM32_INSTR_PT(272) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11101110")); +MQQ1234:ROM32_INSTR_PT(273) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110101110")); +MQQ1235:ROM32_INSTR_PT(274) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01101110")); +MQQ1236:ROM32_INSTR_PT(275) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110011110")); +MQQ1237:ROM32_INSTR_PT(276) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11011110")); +MQQ1238:ROM32_INSTR_PT(277) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01011110")); +MQQ1239:ROM32_INSTR_PT(278) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11111110")); +MQQ1240:ROM32_INSTR_PT(279) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0111110")); +MQQ1241:ROM32_INSTR_PT(280) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11111110")); +MQQ1242:ROM32_INSTR_PT(281) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000011110")); +MQQ1243:ROM32_INSTR_PT(282) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01011110")); +MQQ1244:ROM32_INSTR_PT(283) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000111110")); +MQQ1245:ROM32_INSTR_PT(284) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10111110")); +MQQ1246:ROM32_INSTR_PT(285) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11111110")); +MQQ1247:ROM32_INSTR_PT(286) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000111110")); +MQQ1248:ROM32_INSTR_PT(287) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00111110")); +MQQ1249:ROM32_INSTR_PT(288) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1111110")); +MQQ1250:ROM32_INSTR_PT(289) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110110")); +MQQ1251:ROM32_INSTR_PT(290) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11110110")); +MQQ1252:ROM32_INSTR_PT(291) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("100110")); +MQQ1253:ROM32_INSTR_PT(292) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000001110")); +MQQ1254:ROM32_INSTR_PT(293) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01011110")); +MQQ1255:ROM32_INSTR_PT(294) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01011110")); +MQQ1256:ROM32_INSTR_PT(295) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00111110")); +MQQ1257:ROM32_INSTR_PT(296) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1101110")); +MQQ1258:ROM32_INSTR_PT(297) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11011110")); +MQQ1259:ROM32_INSTR_PT(298) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1111110")); +MQQ1260:ROM32_INSTR_PT(299) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("101110")); +MQQ1261:ROM32_INSTR_PT(300) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01000010")); +MQQ1262:ROM32_INSTR_PT(301) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110010")); +MQQ1263:ROM32_INSTR_PT(302) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00011010")); +MQQ1264:ROM32_INSTR_PT(303) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10011010")); +MQQ1265:ROM32_INSTR_PT(304) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10011010")); +MQQ1266:ROM32_INSTR_PT(305) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("101010")); +MQQ1267:ROM32_INSTR_PT(306) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000000110")); +MQQ1268:ROM32_INSTR_PT(307) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00000110")); +MQQ1269:ROM32_INSTR_PT(308) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11010110")); +MQQ1270:ROM32_INSTR_PT(309) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11110110")); +MQQ1271:ROM32_INSTR_PT(310) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000001110")); +MQQ1272:ROM32_INSTR_PT(311) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0001110")); +MQQ1273:ROM32_INSTR_PT(312) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00111110")); +MQQ1274:ROM32_INSTR_PT(313) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011110")); +MQQ1275:ROM32_INSTR_PT(314) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00010110")); +MQQ1276:ROM32_INSTR_PT(315) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("101110")); +MQQ1277:ROM32_INSTR_PT(316) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("010010")); +MQQ1278:ROM32_INSTR_PT(317) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("011010")); +MQQ1279:ROM32_INSTR_PT(318) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011110")); +MQQ1280:ROM32_INSTR_PT(319) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0000010")); +MQQ1281:ROM32_INSTR_PT(320) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1000000")); +MQQ1282:ROM32_INSTR_PT(321) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01010000")); +MQQ1283:ROM32_INSTR_PT(322) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10101000")); +MQQ1284:ROM32_INSTR_PT(323) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01101000")); +MQQ1285:ROM32_INSTR_PT(324) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0101000")); +MQQ1286:ROM32_INSTR_PT(325) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1100000")); +MQQ1287:ROM32_INSTR_PT(326) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0000100")); +MQQ1288:ROM32_INSTR_PT(327) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11000100")); +MQQ1289:ROM32_INSTR_PT(328) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00000100")); +MQQ1290:ROM32_INSTR_PT(329) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00000100")); +MQQ1291:ROM32_INSTR_PT(330) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0100100")); +MQQ1292:ROM32_INSTR_PT(331) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1001100")); +MQQ1293:ROM32_INSTR_PT(332) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00101100")); +MQQ1294:ROM32_INSTR_PT(333) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("011100")); +MQQ1295:ROM32_INSTR_PT(334) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1000000")); +MQQ1296:ROM32_INSTR_PT(335) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1100010")); +MQQ1297:ROM32_INSTR_PT(336) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1100010")); +MQQ1298:ROM32_INSTR_PT(337) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10010010")); +MQQ1299:ROM32_INSTR_PT(338) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110010")); +MQQ1300:ROM32_INSTR_PT(339) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1010010")); +MQQ1301:ROM32_INSTR_PT(340) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01001010")); +MQQ1302:ROM32_INSTR_PT(341) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11001010")); +MQQ1303:ROM32_INSTR_PT(342) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1100110")); +MQQ1304:ROM32_INSTR_PT(343) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011110")); +MQQ1305:ROM32_INSTR_PT(344) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011110")); +MQQ1306:ROM32_INSTR_PT(345) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0101110")); +MQQ1307:ROM32_INSTR_PT(346) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1111110")); +MQQ1308:ROM32_INSTR_PT(347) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00011110")); +MQQ1309:ROM32_INSTR_PT(348) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011110")); +MQQ1310:ROM32_INSTR_PT(349) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("100110")); +MQQ1311:ROM32_INSTR_PT(350) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("011110")); +MQQ1312:ROM32_INSTR_PT(351) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1000000")); +MQQ1313:ROM32_INSTR_PT(352) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1101000")); +MQQ1314:ROM32_INSTR_PT(353) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1101100")); +MQQ1315:ROM32_INSTR_PT(354) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00000010")); +MQQ1316:ROM32_INSTR_PT(355) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("100010")); +MQQ1317:ROM32_INSTR_PT(356) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("110110")); +MQQ1318:ROM32_INSTR_PT(357) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0011110")); +MQQ1319:ROM32_INSTR_PT(358) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("100010")); +MQQ1320:ROM32_INSTR_PT(359) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001000001")); +MQQ1321:ROM32_INSTR_PT(360) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011000001")); +MQQ1322:ROM32_INSTR_PT(361) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110000001")); +MQQ1323:ROM32_INSTR_PT(362) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011000001")); +MQQ1324:ROM32_INSTR_PT(363) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011100001")); +MQQ1325:ROM32_INSTR_PT(364) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11100001")); +MQQ1326:ROM32_INSTR_PT(365) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000000001")); +MQQ1327:ROM32_INSTR_PT(366) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11000001")); +MQQ1328:ROM32_INSTR_PT(367) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000010001")); +MQQ1329:ROM32_INSTR_PT(368) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010010001")); +MQQ1330:ROM32_INSTR_PT(369) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000110001")); +MQQ1331:ROM32_INSTR_PT(370) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10110001")); +MQQ1332:ROM32_INSTR_PT(371) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("001110001")); +MQQ1333:ROM32_INSTR_PT(372) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00110001")); +MQQ1334:ROM32_INSTR_PT(373) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11110001")); +MQQ1335:ROM32_INSTR_PT(374) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110001")); +MQQ1336:ROM32_INSTR_PT(375) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10110001")); +MQQ1337:ROM32_INSTR_PT(376) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110001")); +MQQ1338:ROM32_INSTR_PT(377) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1110001")); +MQQ1339:ROM32_INSTR_PT(378) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010000001")); +MQQ1340:ROM32_INSTR_PT(379) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11000001")); +MQQ1341:ROM32_INSTR_PT(380) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0100001")); +MQQ1342:ROM32_INSTR_PT(381) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1100001")); +MQQ1343:ROM32_INSTR_PT(382) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010010001")); +MQQ1344:ROM32_INSTR_PT(383) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("100110001")); +MQQ1345:ROM32_INSTR_PT(384) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110001")); +MQQ1346:ROM32_INSTR_PT(385) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1010001")); +MQQ1347:ROM32_INSTR_PT(386) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000001001")); +MQQ1348:ROM32_INSTR_PT(387) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10001001")); +MQQ1349:ROM32_INSTR_PT(388) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("111001001")); +MQQ1350:ROM32_INSTR_PT(389) <= + Eq(( ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1001001")); +MQQ1351:ROM32_INSTR_PT(390) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01001001")); +MQQ1352:ROM32_INSTR_PT(391) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000101001")); +MQQ1353:ROM32_INSTR_PT(392) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0100101001")); +MQQ1354:ROM32_INSTR_PT(393) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110101001")); +MQQ1355:ROM32_INSTR_PT(394) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001101001")); +MQQ1356:ROM32_INSTR_PT(395) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011101001")); +MQQ1357:ROM32_INSTR_PT(396) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011101001")); +MQQ1358:ROM32_INSTR_PT(397) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("111101001")); +MQQ1359:ROM32_INSTR_PT(398) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110011001")); +MQQ1360:ROM32_INSTR_PT(399) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001011001")); +MQQ1361:ROM32_INSTR_PT(400) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011111001")); +MQQ1362:ROM32_INSTR_PT(401) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10111001")); +MQQ1363:ROM32_INSTR_PT(402) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000011001")); +MQQ1364:ROM32_INSTR_PT(403) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011001")); +MQQ1365:ROM32_INSTR_PT(404) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110111001")); +MQQ1366:ROM32_INSTR_PT(405) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01111001")); +MQQ1367:ROM32_INSTR_PT(406) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10111001")); +MQQ1368:ROM32_INSTR_PT(407) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10011001")); +MQQ1369:ROM32_INSTR_PT(408) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110111001")); +MQQ1370:ROM32_INSTR_PT(409) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10111001")); +MQQ1371:ROM32_INSTR_PT(410) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0011001")); +MQQ1372:ROM32_INSTR_PT(411) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01000001")); +MQQ1373:ROM32_INSTR_PT(412) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11000001")); +MQQ1374:ROM32_INSTR_PT(413) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01100001")); +MQQ1375:ROM32_INSTR_PT(414) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0010001")); +MQQ1376:ROM32_INSTR_PT(415) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1010001")); +MQQ1377:ROM32_INSTR_PT(416) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010001001")); +MQQ1378:ROM32_INSTR_PT(417) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01101001")); +MQQ1379:ROM32_INSTR_PT(418) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01011001")); +MQQ1380:ROM32_INSTR_PT(419) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01011001")); +MQQ1381:ROM32_INSTR_PT(420) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("1101000101")); +MQQ1382:ROM32_INSTR_PT(421) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("101000101")); +MQQ1383:ROM32_INSTR_PT(422) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011000101")); +MQQ1384:ROM32_INSTR_PT(423) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000000101")); +MQQ1385:ROM32_INSTR_PT(424) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011000101")); +MQQ1386:ROM32_INSTR_PT(425) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11000101")); +MQQ1387:ROM32_INSTR_PT(426) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110100101")); +MQQ1388:ROM32_INSTR_PT(427) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10100101")); +MQQ1389:ROM32_INSTR_PT(428) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001100101")); +MQQ1390:ROM32_INSTR_PT(429) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("001100101")); +MQQ1391:ROM32_INSTR_PT(430) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011100101")); +MQQ1392:ROM32_INSTR_PT(431) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11100101")); +MQQ1393:ROM32_INSTR_PT(432) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10100101")); +MQQ1394:ROM32_INSTR_PT(433) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110010101")); +MQQ1395:ROM32_INSTR_PT(434) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001010101")); +MQQ1396:ROM32_INSTR_PT(435) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("101010101")); +MQQ1397:ROM32_INSTR_PT(436) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01010101")); +MQQ1398:ROM32_INSTR_PT(437) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000110101")); +MQQ1399:ROM32_INSTR_PT(438) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110101")); +MQQ1400:ROM32_INSTR_PT(439) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110101")); +MQQ1401:ROM32_INSTR_PT(440) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110101")); +MQQ1402:ROM32_INSTR_PT(441) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110101")); +MQQ1403:ROM32_INSTR_PT(442) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010000101")); +MQQ1404:ROM32_INSTR_PT(443) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01000101")); +MQQ1405:ROM32_INSTR_PT(444) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1100101")); +MQQ1406:ROM32_INSTR_PT(445) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00010101")); +MQQ1407:ROM32_INSTR_PT(446) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110101")); +MQQ1408:ROM32_INSTR_PT(447) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1110101")); +MQQ1409:ROM32_INSTR_PT(448) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1010101")); +MQQ1410:ROM32_INSTR_PT(449) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0100001101")); +MQQ1411:ROM32_INSTR_PT(450) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110001101")); +MQQ1412:ROM32_INSTR_PT(451) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001001101")); +MQQ1413:ROM32_INSTR_PT(452) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011001101")); +MQQ1414:ROM32_INSTR_PT(453) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011101101")); +MQQ1415:ROM32_INSTR_PT(454) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011101101")); +MQQ1416:ROM32_INSTR_PT(455) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01001101")); +MQQ1417:ROM32_INSTR_PT(456) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11001101")); +MQQ1418:ROM32_INSTR_PT(457) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10101101")); +MQQ1419:ROM32_INSTR_PT(458) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01101101")); +MQQ1420:ROM32_INSTR_PT(459) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11011101")); +MQQ1421:ROM32_INSTR_PT(460) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11011101")); +MQQ1422:ROM32_INSTR_PT(461) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11111101")); +MQQ1423:ROM32_INSTR_PT(462) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000011101")); +MQQ1424:ROM32_INSTR_PT(463) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11011101")); +MQQ1425:ROM32_INSTR_PT(464) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000111101")); +MQQ1426:ROM32_INSTR_PT(465) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("100111101")); +MQQ1427:ROM32_INSTR_PT(466) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0111101")); +MQQ1428:ROM32_INSTR_PT(467) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11111101")); +MQQ1429:ROM32_INSTR_PT(468) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01100101")); +MQQ1430:ROM32_INSTR_PT(469) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000010101")); +MQQ1431:ROM32_INSTR_PT(470) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0010101")); +MQQ1432:ROM32_INSTR_PT(471) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000110101")); +MQQ1433:ROM32_INSTR_PT(472) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1010101")); +MQQ1434:ROM32_INSTR_PT(473) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00001101")); +MQQ1435:ROM32_INSTR_PT(474) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010001101")); +MQQ1436:ROM32_INSTR_PT(475) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01001101")); +MQQ1437:ROM32_INSTR_PT(476) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01011101")); +MQQ1438:ROM32_INSTR_PT(477) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11011101")); +MQQ1439:ROM32_INSTR_PT(478) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0111101")); +MQQ1440:ROM32_INSTR_PT(479) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11000001")); +MQQ1441:ROM32_INSTR_PT(480) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01010001")); +MQQ1442:ROM32_INSTR_PT(481) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10110001")); +MQQ1443:ROM32_INSTR_PT(482) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01001001")); +MQQ1444:ROM32_INSTR_PT(483) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10101001")); +MQQ1445:ROM32_INSTR_PT(484) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10011001")); +MQQ1446:ROM32_INSTR_PT(485) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000111001")); +MQQ1447:ROM32_INSTR_PT(486) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0111001")); +MQQ1448:ROM32_INSTR_PT(487) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11011001")); +MQQ1449:ROM32_INSTR_PT(488) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("011001")); +MQQ1450:ROM32_INSTR_PT(489) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000000101")); +MQQ1451:ROM32_INSTR_PT(490) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10100101")); +MQQ1452:ROM32_INSTR_PT(491) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11010101")); +MQQ1453:ROM32_INSTR_PT(492) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("100101")); +MQQ1454:ROM32_INSTR_PT(493) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("010101")); +MQQ1455:ROM32_INSTR_PT(494) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00111101")); +MQQ1456:ROM32_INSTR_PT(495) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10011101")); +MQQ1457:ROM32_INSTR_PT(496) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0111101")); +MQQ1458:ROM32_INSTR_PT(497) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0101101")); +MQQ1459:ROM32_INSTR_PT(498) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0001101")); +MQQ1460:ROM32_INSTR_PT(499) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0000001")); +MQQ1461:ROM32_INSTR_PT(500) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("001")); +MQQ1462:ROM32_INSTR_PT(501) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010000011")); +MQQ1463:ROM32_INSTR_PT(502) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("1101000011")); +MQQ1464:ROM32_INSTR_PT(503) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011000011")); +MQQ1465:ROM32_INSTR_PT(504) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11000011")); +MQQ1466:ROM32_INSTR_PT(505) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010100011")); +MQQ1467:ROM32_INSTR_PT(506) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10100011")); +MQQ1468:ROM32_INSTR_PT(507) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011100011")); +MQQ1469:ROM32_INSTR_PT(508) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000000011")); +MQQ1470:ROM32_INSTR_PT(509) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10100011")); +MQQ1471:ROM32_INSTR_PT(510) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1000011")); +MQQ1472:ROM32_INSTR_PT(511) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000010011")); +MQQ1473:ROM32_INSTR_PT(512) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010010011")); +MQQ1474:ROM32_INSTR_PT(513) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00010011")); +MQQ1475:ROM32_INSTR_PT(514) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10010011")); +MQQ1476:ROM32_INSTR_PT(515) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10010011")); +MQQ1477:ROM32_INSTR_PT(516) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("101110011")); +MQQ1478:ROM32_INSTR_PT(517) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("001110011")); +MQQ1479:ROM32_INSTR_PT(518) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00010011")); +MQQ1480:ROM32_INSTR_PT(519) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000110011")); +MQQ1481:ROM32_INSTR_PT(520) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110011")); +MQQ1482:ROM32_INSTR_PT(521) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110011")); +MQQ1483:ROM32_INSTR_PT(522) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010000011")); +MQQ1484:ROM32_INSTR_PT(523) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01000011")); +MQQ1485:ROM32_INSTR_PT(524) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01100011")); +MQQ1486:ROM32_INSTR_PT(525) <= + Eq(( ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("100011")); +MQQ1487:ROM32_INSTR_PT(526) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1100011")); +MQQ1488:ROM32_INSTR_PT(527) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10010011")); +MQQ1489:ROM32_INSTR_PT(528) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000110011")); +MQQ1490:ROM32_INSTR_PT(529) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1010011")); +MQQ1491:ROM32_INSTR_PT(530) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10001011")); +MQQ1492:ROM32_INSTR_PT(531) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("1101001011")); +MQQ1493:ROM32_INSTR_PT(532) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("001001011")); +MQQ1494:ROM32_INSTR_PT(533) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("111001011")); +MQQ1495:ROM32_INSTR_PT(534) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0000101011")); +MQQ1496:ROM32_INSTR_PT(535) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110101011")); +MQQ1497:ROM32_INSTR_PT(536) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011101011")); +MQQ1498:ROM32_INSTR_PT(537) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01101011")); +MQQ1499:ROM32_INSTR_PT(538) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000101011")); +MQQ1500:ROM32_INSTR_PT(539) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01101011")); +MQQ1501:ROM32_INSTR_PT(540) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10011011")); +MQQ1502:ROM32_INSTR_PT(541) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11011011")); +MQQ1503:ROM32_INSTR_PT(542) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0011011")); +MQQ1504:ROM32_INSTR_PT(543) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11111011")); +MQQ1505:ROM32_INSTR_PT(544) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01011011")); +MQQ1506:ROM32_INSTR_PT(545) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11011011")); +MQQ1507:ROM32_INSTR_PT(546) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11111011")); +MQQ1508:ROM32_INSTR_PT(547) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000101011")); +MQQ1509:ROM32_INSTR_PT(548) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011011")); +MQQ1510:ROM32_INSTR_PT(549) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("111011")); +MQQ1511:ROM32_INSTR_PT(550) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000100011")); +MQQ1512:ROM32_INSTR_PT(551) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01100011")); +MQQ1513:ROM32_INSTR_PT(552) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10110011")); +MQQ1514:ROM32_INSTR_PT(553) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00001011")); +MQQ1515:ROM32_INSTR_PT(554) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010001011")); +MQQ1516:ROM32_INSTR_PT(555) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1101011")); +MQQ1517:ROM32_INSTR_PT(556) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000011011")); +MQQ1518:ROM32_INSTR_PT(557) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011011")); +MQQ1519:ROM32_INSTR_PT(558) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01011011")); +MQQ1520:ROM32_INSTR_PT(559) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000111011")); +MQQ1521:ROM32_INSTR_PT(560) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0101011")); +MQQ1522:ROM32_INSTR_PT(561) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0011011")); +MQQ1523:ROM32_INSTR_PT(562) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0111011")); +MQQ1524:ROM32_INSTR_PT(563) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1111011")); +MQQ1525:ROM32_INSTR_PT(564) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("11011")); +MQQ1526:ROM32_INSTR_PT(565) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00000111")); +MQQ1527:ROM32_INSTR_PT(566) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010000111")); +MQQ1528:ROM32_INSTR_PT(567) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00000111")); +MQQ1529:ROM32_INSTR_PT(568) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001000111")); +MQQ1530:ROM32_INSTR_PT(569) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011000111")); +MQQ1531:ROM32_INSTR_PT(570) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011000111")); +MQQ1532:ROM32_INSTR_PT(571) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010100111")); +MQQ1533:ROM32_INSTR_PT(572) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110100111")); +MQQ1534:ROM32_INSTR_PT(573) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10100111")); +MQQ1535:ROM32_INSTR_PT(574) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("001100111")); +MQQ1536:ROM32_INSTR_PT(575) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011100111")); +MQQ1537:ROM32_INSTR_PT(576) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00000111")); +MQQ1538:ROM32_INSTR_PT(577) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11000111")); +MQQ1539:ROM32_INSTR_PT(578) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000010111")); +MQQ1540:ROM32_INSTR_PT(579) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10010111")); +MQQ1541:ROM32_INSTR_PT(580) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("001010111")); +MQQ1542:ROM32_INSTR_PT(581) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011010111")); +MQQ1543:ROM32_INSTR_PT(582) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110111")); +MQQ1544:ROM32_INSTR_PT(583) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01010111")); +MQQ1545:ROM32_INSTR_PT(584) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01100111")); +MQQ1546:ROM32_INSTR_PT(585) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000001111")); +MQQ1547:ROM32_INSTR_PT(586) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010001111")); +MQQ1548:ROM32_INSTR_PT(587) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10001111")); +MQQ1549:ROM32_INSTR_PT(588) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11001111")); +MQQ1550:ROM32_INSTR_PT(589) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10001111")); +MQQ1551:ROM32_INSTR_PT(590) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000101111")); +MQQ1552:ROM32_INSTR_PT(591) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001101111")); +MQQ1553:ROM32_INSTR_PT(592) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11101111")); +MQQ1554:ROM32_INSTR_PT(593) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11101111")); +MQQ1555:ROM32_INSTR_PT(594) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0001111")); +MQQ1556:ROM32_INSTR_PT(595) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11101111")); +MQQ1557:ROM32_INSTR_PT(596) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00011111")); +MQQ1558:ROM32_INSTR_PT(597) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10011111")); +MQQ1559:ROM32_INSTR_PT(598) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("001011111")); +MQQ1560:ROM32_INSTR_PT(599) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000111111")); +MQQ1561:ROM32_INSTR_PT(600) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11111111")); +MQQ1562:ROM32_INSTR_PT(601) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011111")); +MQQ1563:ROM32_INSTR_PT(602) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10011111")); +MQQ1564:ROM32_INSTR_PT(603) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1111111")); +MQQ1565:ROM32_INSTR_PT(604) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10111111")); +MQQ1566:ROM32_INSTR_PT(605) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01111111")); +MQQ1567:ROM32_INSTR_PT(606) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11111111")); +MQQ1568:ROM32_INSTR_PT(607) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01101111")); +MQQ1569:ROM32_INSTR_PT(608) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011111")); +MQQ1570:ROM32_INSTR_PT(609) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10111111")); +MQQ1571:ROM32_INSTR_PT(610) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01111111")); +MQQ1572:ROM32_INSTR_PT(611) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("111111")); +MQQ1573:ROM32_INSTR_PT(612) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("111111")); +MQQ1574:ROM32_INSTR_PT(613) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11000111")); +MQQ1575:ROM32_INSTR_PT(614) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110111")); +MQQ1576:ROM32_INSTR_PT(615) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11110111")); +MQQ1577:ROM32_INSTR_PT(616) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01000111")); +MQQ1578:ROM32_INSTR_PT(617) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01001111")); +MQQ1579:ROM32_INSTR_PT(618) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01011111")); +MQQ1580:ROM32_INSTR_PT(619) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011111")); +MQQ1581:ROM32_INSTR_PT(620) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01011111")); +MQQ1582:ROM32_INSTR_PT(621) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01111111")); +MQQ1583:ROM32_INSTR_PT(622) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0111111")); +MQQ1584:ROM32_INSTR_PT(623) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011111")); +MQQ1585:ROM32_INSTR_PT(624) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011111")); +MQQ1586:ROM32_INSTR_PT(625) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0111111")); +MQQ1587:ROM32_INSTR_PT(626) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0111111")); +MQQ1588:ROM32_INSTR_PT(627) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1000011")); +MQQ1589:ROM32_INSTR_PT(628) <= + Eq(( ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("10011")); +MQQ1590:ROM32_INSTR_PT(629) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01001011")); +MQQ1591:ROM32_INSTR_PT(630) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00011011")); +MQQ1592:ROM32_INSTR_PT(631) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000111011")); +MQQ1593:ROM32_INSTR_PT(632) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00111011")); +MQQ1594:ROM32_INSTR_PT(633) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1111011")); +MQQ1595:ROM32_INSTR_PT(634) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01001011")); +MQQ1596:ROM32_INSTR_PT(635) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11011011")); +MQQ1597:ROM32_INSTR_PT(636) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("011011")); +MQQ1598:ROM32_INSTR_PT(637) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("10011")); +MQQ1599:ROM32_INSTR_PT(638) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010000111")); +MQQ1600:ROM32_INSTR_PT(639) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000100111")); +MQQ1601:ROM32_INSTR_PT(640) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01010111")); +MQQ1602:ROM32_INSTR_PT(641) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1000111")); +MQQ1603:ROM32_INSTR_PT(642) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0111111")); +MQQ1604:ROM32_INSTR_PT(643) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("111111")); +MQQ1605:ROM32_INSTR_PT(644) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("111111")); +MQQ1606:ROM32_INSTR_PT(645) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0010111")); +MQQ1607:ROM32_INSTR_PT(646) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1110111")); +MQQ1608:ROM32_INSTR_PT(647) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11011111")); +MQQ1609:ROM32_INSTR_PT(648) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("11111")); +MQQ1610:ROM32_INSTR_PT(649) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1111111")); +MQQ1611:ROM32_INSTR_PT(650) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("11111")); +MQQ1612:ROM32_INSTR_PT(651) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("11011")); +MQQ1613:ROM32_INSTR_PT(652) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11000001")); +MQQ1614:ROM32_INSTR_PT(653) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1000001")); +MQQ1615:ROM32_INSTR_PT(654) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110001")); +MQQ1616:ROM32_INSTR_PT(655) <= + Eq(( ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("110001")); +MQQ1617:ROM32_INSTR_PT(656) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1001001")); +MQQ1618:ROM32_INSTR_PT(657) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10101001")); +MQQ1619:ROM32_INSTR_PT(658) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1001001")); +MQQ1620:ROM32_INSTR_PT(659) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00011001")); +MQQ1621:ROM32_INSTR_PT(660) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("101001")); +MQQ1622:ROM32_INSTR_PT(661) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00000101")); +MQQ1623:ROM32_INSTR_PT(662) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01000101")); +MQQ1624:ROM32_INSTR_PT(663) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000100101")); +MQQ1625:ROM32_INSTR_PT(664) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11110101")); +MQQ1626:ROM32_INSTR_PT(665) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11001101")); +MQQ1627:ROM32_INSTR_PT(666) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10011101")); +MQQ1628:ROM32_INSTR_PT(667) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011101")); +MQQ1629:ROM32_INSTR_PT(668) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1000001")); +MQQ1630:ROM32_INSTR_PT(669) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("011101")); +MQQ1631:ROM32_INSTR_PT(670) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("01001")); +MQQ1632:ROM32_INSTR_PT(671) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("100101")); +MQQ1633:ROM32_INSTR_PT(672) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110100011")); +MQQ1634:ROM32_INSTR_PT(673) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("100011")); +MQQ1635:ROM32_INSTR_PT(674) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110011")); +MQQ1636:ROM32_INSTR_PT(675) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("000011")); +MQQ1637:ROM32_INSTR_PT(676) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01001011")); +MQQ1638:ROM32_INSTR_PT(677) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10101011")); +MQQ1639:ROM32_INSTR_PT(678) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10011011")); +MQQ1640:ROM32_INSTR_PT(679) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011011")); +MQQ1641:ROM32_INSTR_PT(680) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11011011")); +MQQ1642:ROM32_INSTR_PT(681) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("010011")); +MQQ1643:ROM32_INSTR_PT(682) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110100111")); +MQQ1644:ROM32_INSTR_PT(683) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10010111")); +MQQ1645:ROM32_INSTR_PT(684) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01010111")); +MQQ1646:ROM32_INSTR_PT(685) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10001111")); +MQQ1647:ROM32_INSTR_PT(686) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("101111")); +MQQ1648:ROM32_INSTR_PT(687) <= + Eq(( ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("011111")); +MQQ1649:ROM32_INSTR_PT(688) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1111111")); +MQQ1650:ROM32_INSTR_PT(689) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0111111")); +MQQ1651:ROM32_INSTR_PT(690) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("111111")); +MQQ1652:ROM32_INSTR_PT(691) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1000111")); +MQQ1653:ROM32_INSTR_PT(692) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1110111")); +MQQ1654:ROM32_INSTR_PT(693) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11011111")); +MQQ1655:ROM32_INSTR_PT(694) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1111111")); +MQQ1656:ROM32_INSTR_PT(695) <= + Eq(( ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0011")); +MQQ1657:ROM32_INSTR_PT(696) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("11011")); +MQQ1658:ROM32_INSTR_PT(697) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("110111")); +MQQ1659:ROM32_INSTR_PT(698) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0101111")); +MQQ1660:ROM32_INSTR_PT(699) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011111")); +MQQ1661:ROM32_INSTR_PT(700) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1111111")); +MQQ1662:ROM32_INSTR_PT(701) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("01111")); +MQQ1663:ROM32_INSTR_PT(702) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1000001")); +MQQ1664:ROM32_INSTR_PT(703) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1001001")); +MQQ1665:ROM32_INSTR_PT(704) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("111001")); +MQQ1666:ROM32_INSTR_PT(705) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("100001")); +MQQ1667:ROM32_INSTR_PT(706) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("001001")); +MQQ1668:ROM32_INSTR_PT(707) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("111101")); +MQQ1669:ROM32_INSTR_PT(708) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0110111")); +MQQ1670:ROM32_INSTR_PT(709) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("110111")); +MQQ1671:ROM32_INSTR_PT(710) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1111111")); +MQQ1672:ROM32_INSTR_PT(711) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("111111")); +MQQ1673:ROM32_INSTR_PT(712) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("100111")); +MQQ1674:ROM32_INSTR_PT(713) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("011111")); +MQQ1675:ROM32_INSTR_PT(714) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("11011")); +MQQ1676:ROM32_INSTR_PT(715) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("100101")); +MQQ1677:ROM32_INSTR_PT(716) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("100011")); +MQQ1678:ROM32_INSTR_PT(717) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0111")); +MQQ1679:ROM32_INSTR_PT(718) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("1101")); +MQQ1680:ROM32_INSTR_PT(719) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("01100000")); +MQQ1681:ROM32_INSTR_PT(720) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("01100000")); +MQQ1682:ROM32_INSTR_PT(721) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1010000")); +MQQ1683:ROM32_INSTR_PT(722) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("000110000")); +MQQ1684:ROM32_INSTR_PT(723) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("01110000")); +MQQ1685:ROM32_INSTR_PT(724) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0100000")); +MQQ1686:ROM32_INSTR_PT(725) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("111000")); +MQQ1687:ROM32_INSTR_PT(726) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0111000")); +MQQ1688:ROM32_INSTR_PT(727) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0000100")); +MQQ1689:ROM32_INSTR_PT(728) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("01100100")); +MQQ1690:ROM32_INSTR_PT(729) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1100100")); +MQQ1691:ROM32_INSTR_PT(730) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1100100")); +MQQ1692:ROM32_INSTR_PT(731) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("01101100")); +MQQ1693:ROM32_INSTR_PT(732) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("01101100")); +MQQ1694:ROM32_INSTR_PT(733) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("10011100")); +MQQ1695:ROM32_INSTR_PT(734) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("101100")); +MQQ1696:ROM32_INSTR_PT(735) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("01100")); +MQQ1697:ROM32_INSTR_PT(736) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0100100")); +MQQ1698:ROM32_INSTR_PT(737) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0100000")); +MQQ1699:ROM32_INSTR_PT(738) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1100000")); +MQQ1700:ROM32_INSTR_PT(739) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("00000100")); +MQQ1701:ROM32_INSTR_PT(740) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0101100")); +MQQ1702:ROM32_INSTR_PT(741) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("011100")); +MQQ1703:ROM32_INSTR_PT(742) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1101100")); +MQQ1704:ROM32_INSTR_PT(743) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("11100")); +MQQ1705:ROM32_INSTR_PT(744) <= + Eq(( ROM_ADDR_L2(3) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("000")); +MQQ1706:ROM32_INSTR_PT(745) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("01100010")); +MQQ1707:ROM32_INSTR_PT(746) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0000010")); +MQQ1708:ROM32_INSTR_PT(747) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("00010010")); +MQQ1709:ROM32_INSTR_PT(748) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("00000010")); +MQQ1710:ROM32_INSTR_PT(749) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("11001010")); +MQQ1711:ROM32_INSTR_PT(750) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("111010")); +MQQ1712:ROM32_INSTR_PT(751) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("01001010")); +MQQ1713:ROM32_INSTR_PT(752) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("101010")); +MQQ1714:ROM32_INSTR_PT(753) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("010000110")); +MQQ1715:ROM32_INSTR_PT(754) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1000110")); +MQQ1716:ROM32_INSTR_PT(755) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("110100110")); +MQQ1717:ROM32_INSTR_PT(756) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0001110")); +MQQ1718:ROM32_INSTR_PT(757) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1001110")); +MQQ1719:ROM32_INSTR_PT(758) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("00011110")); +MQQ1720:ROM32_INSTR_PT(759) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("10011110")); +MQQ1721:ROM32_INSTR_PT(760) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1010010")); +MQQ1722:ROM32_INSTR_PT(761) <= + Eq(( ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("0110")); +MQQ1723:ROM32_INSTR_PT(762) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("00011110")); +MQQ1724:ROM32_INSTR_PT(763) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1111110")); +MQQ1725:ROM32_INSTR_PT(764) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("010110")); +MQQ1726:ROM32_INSTR_PT(765) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("010100")); +MQQ1727:ROM32_INSTR_PT(766) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1101100")); +MQQ1728:ROM32_INSTR_PT(767) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("011100")); +MQQ1729:ROM32_INSTR_PT(768) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("110000")); +MQQ1730:ROM32_INSTR_PT(769) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("00100")); +MQQ1731:ROM32_INSTR_PT(770) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0100010")); +MQQ1732:ROM32_INSTR_PT(771) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1001110")); +MQQ1733:ROM32_INSTR_PT(772) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("0000")); +MQQ1734:ROM32_INSTR_PT(773) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("01110")); +MQQ1735:ROM32_INSTR_PT(774) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("01000001")); +MQQ1736:ROM32_INSTR_PT(775) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("110100001")); +MQQ1737:ROM32_INSTR_PT(776) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("01010001")); +MQQ1738:ROM32_INSTR_PT(777) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("11010001")); +MQQ1739:ROM32_INSTR_PT(778) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1010001")); +MQQ1740:ROM32_INSTR_PT(779) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0000001")); +MQQ1741:ROM32_INSTR_PT(780) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1000001")); +MQQ1742:ROM32_INSTR_PT(781) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("010001")); +MQQ1743:ROM32_INSTR_PT(782) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0001001")); +MQQ1744:ROM32_INSTR_PT(783) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("001001")); +MQQ1745:ROM32_INSTR_PT(784) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("00011001")); +MQQ1746:ROM32_INSTR_PT(785) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("111001")); +MQQ1747:ROM32_INSTR_PT(786) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("00011001")); +MQQ1748:ROM32_INSTR_PT(787) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("00100101")); +MQQ1749:ROM32_INSTR_PT(788) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("00010101")); +MQQ1750:ROM32_INSTR_PT(789) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("00011101")); +MQQ1751:ROM32_INSTR_PT(790) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("10011101")); +MQQ1752:ROM32_INSTR_PT(791) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("011101")); +MQQ1753:ROM32_INSTR_PT(792) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("110101")); +MQQ1754:ROM32_INSTR_PT(793) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("10101")); +MQQ1755:ROM32_INSTR_PT(794) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("11101")); +MQQ1756:ROM32_INSTR_PT(795) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0000101")); +MQQ1757:ROM32_INSTR_PT(796) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0000101")); +MQQ1758:ROM32_INSTR_PT(797) <= + Eq(( ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("11101")); +MQQ1759:ROM32_INSTR_PT(798) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("101101")); +MQQ1760:ROM32_INSTR_PT(799) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("100001")); +MQQ1761:ROM32_INSTR_PT(800) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("000100011")); +MQQ1762:ROM32_INSTR_PT(801) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("00000011")); +MQQ1763:ROM32_INSTR_PT(802) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0000011")); +MQQ1764:ROM32_INSTR_PT(803) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1010011")); +MQQ1765:ROM32_INSTR_PT(804) <= + Eq(( ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("10011")); +MQQ1766:ROM32_INSTR_PT(805) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("01001011")); +MQQ1767:ROM32_INSTR_PT(806) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0001011")); +MQQ1768:ROM32_INSTR_PT(807) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("01000011")); +MQQ1769:ROM32_INSTR_PT(808) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("101011")); +MQQ1770:ROM32_INSTR_PT(809) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("11011")); +MQQ1771:ROM32_INSTR_PT(810) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("100111")); +MQQ1772:ROM32_INSTR_PT(811) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("00010111")); +MQQ1773:ROM32_INSTR_PT(812) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("01010111")); +MQQ1774:ROM32_INSTR_PT(813) <= + Eq(( ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("110111")); +MQQ1775:ROM32_INSTR_PT(814) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1110111")); +MQQ1776:ROM32_INSTR_PT(815) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("11010111")); +MQQ1777:ROM32_INSTR_PT(816) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("000101111")); +MQQ1778:ROM32_INSTR_PT(817) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("01101111")); +MQQ1779:ROM32_INSTR_PT(818) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("111111")); +MQQ1780:ROM32_INSTR_PT(819) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("111111")); +MQQ1781:ROM32_INSTR_PT(820) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("11111")); +MQQ1782:ROM32_INSTR_PT(821) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("111111")); +MQQ1783:ROM32_INSTR_PT(822) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("101011")); +MQQ1784:ROM32_INSTR_PT(823) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("01000111")); +MQQ1785:ROM32_INSTR_PT(824) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0110111")); +MQQ1786:ROM32_INSTR_PT(825) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("110111")); +MQQ1787:ROM32_INSTR_PT(826) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("101111")); +MQQ1788:ROM32_INSTR_PT(827) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("11111")); +MQQ1789:ROM32_INSTR_PT(828) <= + Eq(( ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("0111")); +MQQ1790:ROM32_INSTR_PT(829) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("111111")); +MQQ1791:ROM32_INSTR_PT(830) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("01111")); +MQQ1792:ROM32_INSTR_PT(831) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("110001")); +MQQ1793:ROM32_INSTR_PT(832) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("011001")); +MQQ1794:ROM32_INSTR_PT(833) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1001101")); +MQQ1795:ROM32_INSTR_PT(834) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("01001")); +MQQ1796:ROM32_INSTR_PT(835) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0100011")); +MQQ1797:ROM32_INSTR_PT(836) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1111011")); +MQQ1798:ROM32_INSTR_PT(837) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("11011")); +MQQ1799:ROM32_INSTR_PT(838) <= + Eq(( ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("011")); +MQQ1800:ROM32_INSTR_PT(839) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0000111")); +MQQ1801:ROM32_INSTR_PT(840) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1111111")); +MQQ1802:ROM32_INSTR_PT(841) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("011111")); +MQQ1803:ROM32_INSTR_PT(842) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("101111")); +MQQ1804:ROM32_INSTR_PT(843) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("100011")); +MQQ1805:ROM32_INSTR_PT(844) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("110111")); +MQQ1806:ROM32_INSTR_PT(845) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("011111")); +MQQ1807:ROM32_INSTR_PT(846) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("000101")); +MQQ1808:ROM32_INSTR_PT(847) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("100011")); +MQQ1809:ROM32_INSTR_PT(848) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("1111")); +MQQ1810:ROM32_INSTR_PT(849) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("10111")); +MQQ1811:ROM32_INSTR_PT(850) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("0111")); +MQQ1812:ROM32_INSTR_PT(851) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("1001000")); +MQQ1813:ROM32_INSTR_PT(852) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) + ) , STD_ULOGIC_VECTOR'("110000")); +MQQ1814:ROM32_INSTR_PT(853) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) + ) , STD_ULOGIC_VECTOR'("00011100")); +MQQ1815:ROM32_INSTR_PT(854) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) + ) , STD_ULOGIC_VECTOR'("00000010")); +MQQ1816:ROM32_INSTR_PT(855) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("0100010")); +MQQ1817:ROM32_INSTR_PT(856) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("0000010")); +MQQ1818:ROM32_INSTR_PT(857) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) + ) , STD_ULOGIC_VECTOR'("101110")); +MQQ1819:ROM32_INSTR_PT(858) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("1101110")); +MQQ1820:ROM32_INSTR_PT(859) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("1001100")); +MQQ1821:ROM32_INSTR_PT(860) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("00000")); +MQQ1822:ROM32_INSTR_PT(861) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) + ) , STD_ULOGIC_VECTOR'("1110")); +MQQ1823:ROM32_INSTR_PT(862) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("0100101")); +MQQ1824:ROM32_INSTR_PT(863) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("1001101")); +MQQ1825:ROM32_INSTR_PT(864) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) + ) , STD_ULOGIC_VECTOR'("001101")); +MQQ1826:ROM32_INSTR_PT(865) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("1101101")); +MQQ1827:ROM32_INSTR_PT(866) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) + ) , STD_ULOGIC_VECTOR'("1101")); +MQQ1828:ROM32_INSTR_PT(867) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("1010011")); +MQQ1829:ROM32_INSTR_PT(868) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("1001011")); +MQQ1830:ROM32_INSTR_PT(869) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) + ) , STD_ULOGIC_VECTOR'("110111")); +MQQ1831:ROM32_INSTR_PT(870) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("0011111")); +MQQ1832:ROM32_INSTR_PT(871) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) + ) , STD_ULOGIC_VECTOR'("111111")); +MQQ1833:ROM32_INSTR_PT(872) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) + ) , STD_ULOGIC_VECTOR'("110111")); +MQQ1834:ROM32_INSTR_PT(873) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("11111")); +MQQ1835:ROM32_INSTR_PT(874) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("01111")); +MQQ1836:ROM32_INSTR_PT(875) <= + Eq(( ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) + ) , STD_ULOGIC_VECTOR'("1101")); +MQQ1837:ROM32_INSTR_PT(876) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) + ) , STD_ULOGIC_VECTOR'("000011")); +MQQ1838:ROM32_INSTR_PT(877) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) ) , STD_ULOGIC_VECTOR'("0000100")); +MQQ1839:ROM32_INSTR_PT(878) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) + ) , STD_ULOGIC_VECTOR'("010010")); +MQQ1840:ROM32_INSTR_PT(879) <= + Eq(( ROM_ADDR_L2(4) & ROM_ADDR_L2(6) + ) , STD_ULOGIC_VECTOR'("00")); +MQQ1841:ROM32_INSTR_PT(880) <= + Eq(( ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) ) , STD_ULOGIC_VECTOR'("111")); +MQQ1842:ROM32_INSTR_PT(881) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) + ) , STD_ULOGIC_VECTOR'("110111")); +MQQ1843:ROM32_INSTR_PT(882) <= + Eq(( ROM_ADDR_L2(4) & ROM_ADDR_L2(5) + ) , STD_ULOGIC_VECTOR'("00")); +MQQ1844:ROM32_INSTR_PT(883) <= + Eq(( ROM_ADDR_L2(3) & ROM_ADDR_L2(5) + ) , STD_ULOGIC_VECTOR'("00")); +MQQ1845:ROM32_INSTR_PT(884) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) + ) , STD_ULOGIC_VECTOR'("0110")); +MQQ1846:ROM32_INSTR_PT(885) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) + ) , STD_ULOGIC_VECTOR'("0110")); +MQQ1847:ROM32_INSTR_PT(886) <= + Eq(( ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) ) , STD_ULOGIC_VECTOR'("111")); +MQQ1848:ROM32_INSTR_PT(887) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) ) , STD_ULOGIC_VECTOR'("000")); +MQQ1849:ROM32_INSTR_PT(888) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) + ) , STD_ULOGIC_VECTOR'("0111")); +MQQ1850:ROM32_INSTR_PT(889) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) ) , STD_ULOGIC_VECTOR'("111")); +MQQ1851:ROM32_INSTR_PT(890) <= + Eq(( ROM_ADDR_L2(2) ) , STD_ULOGIC'('1')); +MQQ1852:ROM32_INSTR_PT(891) <= + Eq(( ROM_ADDR_L2(1) ) , STD_ULOGIC'('1')); +MQQ1853:ROM32_INSTR_PT(892) <= + Eq(( ROM_ADDR_L2(0) ) , STD_ULOGIC'('0')); +MQQ1854:ROM32_INSTR_PT(893) <= + '1'; +MQQ1855:TEMPLATE(0) <= + (ROM32_INSTR_PT(28) OR ROM32_INSTR_PT(33) + OR ROM32_INSTR_PT(45) OR ROM32_INSTR_PT(68) + OR ROM32_INSTR_PT(76) OR ROM32_INSTR_PT(85) + OR ROM32_INSTR_PT(113) OR ROM32_INSTR_PT(120) + OR ROM32_INSTR_PT(128) OR ROM32_INSTR_PT(132) + OR ROM32_INSTR_PT(142) OR ROM32_INSTR_PT(159) + OR ROM32_INSTR_PT(162) OR ROM32_INSTR_PT(175) + OR ROM32_INSTR_PT(176) OR ROM32_INSTR_PT(177) + OR ROM32_INSTR_PT(180) OR ROM32_INSTR_PT(222) + OR ROM32_INSTR_PT(226) OR ROM32_INSTR_PT(233) + OR ROM32_INSTR_PT(237) OR ROM32_INSTR_PT(242) + OR ROM32_INSTR_PT(255) OR ROM32_INSTR_PT(290) + OR ROM32_INSTR_PT(292) OR ROM32_INSTR_PT(309) + OR ROM32_INSTR_PT(335) OR ROM32_INSTR_PT(346) + OR ROM32_INSTR_PT(351) OR ROM32_INSTR_PT(353) + OR ROM32_INSTR_PT(356) OR ROM32_INSTR_PT(357) + OR ROM32_INSTR_PT(359) OR ROM32_INSTR_PT(364) + OR ROM32_INSTR_PT(365) OR ROM32_INSTR_PT(373) + OR ROM32_INSTR_PT(381) OR ROM32_INSTR_PT(388) + OR ROM32_INSTR_PT(391) OR ROM32_INSTR_PT(399) + OR ROM32_INSTR_PT(425) OR ROM32_INSTR_PT(431) + OR ROM32_INSTR_PT(467) OR ROM32_INSTR_PT(473) + OR ROM32_INSTR_PT(527) OR ROM32_INSTR_PT(555) + OR ROM32_INSTR_PT(563) OR ROM32_INSTR_PT(571) + OR ROM32_INSTR_PT(586) OR ROM32_INSTR_PT(597) + OR ROM32_INSTR_PT(604) OR ROM32_INSTR_PT(615) + OR ROM32_INSTR_PT(652) OR ROM32_INSTR_PT(657) + OR ROM32_INSTR_PT(664) OR ROM32_INSTR_PT(691) + OR ROM32_INSTR_PT(692) OR ROM32_INSTR_PT(697) + OR ROM32_INSTR_PT(711) OR ROM32_INSTR_PT(715) + OR ROM32_INSTR_PT(716) OR ROM32_INSTR_PT(718) + OR ROM32_INSTR_PT(729) OR ROM32_INSTR_PT(763) + OR ROM32_INSTR_PT(792) OR ROM32_INSTR_PT(829) + OR ROM32_INSTR_PT(831) OR ROM32_INSTR_PT(857) + OR ROM32_INSTR_PT(872)); +MQQ1856:TEMPLATE(1) <= + (ROM32_INSTR_PT(3) OR ROM32_INSTR_PT(5) + OR ROM32_INSTR_PT(6) OR ROM32_INSTR_PT(7) + OR ROM32_INSTR_PT(8) OR ROM32_INSTR_PT(9) + OR ROM32_INSTR_PT(10) OR ROM32_INSTR_PT(13) + OR ROM32_INSTR_PT(14) OR ROM32_INSTR_PT(16) + OR ROM32_INSTR_PT(17) OR ROM32_INSTR_PT(20) + OR ROM32_INSTR_PT(23) OR ROM32_INSTR_PT(26) + OR ROM32_INSTR_PT(32) OR ROM32_INSTR_PT(35) + OR ROM32_INSTR_PT(37) OR ROM32_INSTR_PT(39) + OR ROM32_INSTR_PT(41) OR ROM32_INSTR_PT(42) + OR ROM32_INSTR_PT(43) OR ROM32_INSTR_PT(49) + OR ROM32_INSTR_PT(50) OR ROM32_INSTR_PT(51) + OR ROM32_INSTR_PT(52) OR ROM32_INSTR_PT(53) + OR ROM32_INSTR_PT(55) OR ROM32_INSTR_PT(56) + OR ROM32_INSTR_PT(57) OR ROM32_INSTR_PT(59) + OR ROM32_INSTR_PT(63) OR ROM32_INSTR_PT(66) + OR ROM32_INSTR_PT(67) OR ROM32_INSTR_PT(72) + OR ROM32_INSTR_PT(73) OR ROM32_INSTR_PT(74) + OR ROM32_INSTR_PT(77) OR ROM32_INSTR_PT(79) + OR ROM32_INSTR_PT(80) OR ROM32_INSTR_PT(83) + OR ROM32_INSTR_PT(84) OR ROM32_INSTR_PT(87) + OR ROM32_INSTR_PT(90) OR ROM32_INSTR_PT(92) + OR ROM32_INSTR_PT(93) OR ROM32_INSTR_PT(96) + OR ROM32_INSTR_PT(97) OR ROM32_INSTR_PT(99) + OR ROM32_INSTR_PT(100) OR ROM32_INSTR_PT(101) + OR ROM32_INSTR_PT(102) OR ROM32_INSTR_PT(103) + OR ROM32_INSTR_PT(105) OR ROM32_INSTR_PT(106) + OR ROM32_INSTR_PT(109) OR ROM32_INSTR_PT(110) + OR ROM32_INSTR_PT(111) OR ROM32_INSTR_PT(114) + OR ROM32_INSTR_PT(115) OR ROM32_INSTR_PT(117) + OR ROM32_INSTR_PT(118) OR ROM32_INSTR_PT(119) + OR ROM32_INSTR_PT(122) OR ROM32_INSTR_PT(124) + OR ROM32_INSTR_PT(127) OR ROM32_INSTR_PT(130) + OR ROM32_INSTR_PT(134) OR ROM32_INSTR_PT(135) + OR ROM32_INSTR_PT(139) OR ROM32_INSTR_PT(141) + OR ROM32_INSTR_PT(144) OR ROM32_INSTR_PT(148) + OR ROM32_INSTR_PT(153) OR ROM32_INSTR_PT(158) + OR ROM32_INSTR_PT(163) OR ROM32_INSTR_PT(164) + OR ROM32_INSTR_PT(165) OR ROM32_INSTR_PT(169) + OR ROM32_INSTR_PT(170) OR ROM32_INSTR_PT(171) + OR ROM32_INSTR_PT(172) OR ROM32_INSTR_PT(179) + OR ROM32_INSTR_PT(183) OR ROM32_INSTR_PT(184) + OR ROM32_INSTR_PT(186) OR ROM32_INSTR_PT(192) + OR ROM32_INSTR_PT(193) OR ROM32_INSTR_PT(195) + OR ROM32_INSTR_PT(196) OR ROM32_INSTR_PT(199) + OR ROM32_INSTR_PT(200) OR ROM32_INSTR_PT(202) + OR ROM32_INSTR_PT(203) OR ROM32_INSTR_PT(205) + OR ROM32_INSTR_PT(206) OR ROM32_INSTR_PT(207) + OR ROM32_INSTR_PT(209) OR ROM32_INSTR_PT(215) + OR ROM32_INSTR_PT(216) OR ROM32_INSTR_PT(218) + OR ROM32_INSTR_PT(219) OR ROM32_INSTR_PT(220) + OR ROM32_INSTR_PT(223) OR ROM32_INSTR_PT(224) + OR ROM32_INSTR_PT(227) OR ROM32_INSTR_PT(229) + OR ROM32_INSTR_PT(238) OR ROM32_INSTR_PT(241) + OR ROM32_INSTR_PT(243) OR ROM32_INSTR_PT(249) + OR ROM32_INSTR_PT(250) OR ROM32_INSTR_PT(252) + OR ROM32_INSTR_PT(254) OR ROM32_INSTR_PT(256) + OR ROM32_INSTR_PT(257) OR ROM32_INSTR_PT(259) + OR ROM32_INSTR_PT(260) OR ROM32_INSTR_PT(261) + OR ROM32_INSTR_PT(262) OR ROM32_INSTR_PT(264) + OR ROM32_INSTR_PT(267) OR ROM32_INSTR_PT(268) + OR ROM32_INSTR_PT(269) OR ROM32_INSTR_PT(270) + OR ROM32_INSTR_PT(273) OR ROM32_INSTR_PT(274) + OR ROM32_INSTR_PT(275) OR ROM32_INSTR_PT(278) + OR ROM32_INSTR_PT(280) OR ROM32_INSTR_PT(282) + OR ROM32_INSTR_PT(283) OR ROM32_INSTR_PT(284) + OR ROM32_INSTR_PT(287) OR ROM32_INSTR_PT(288) + OR ROM32_INSTR_PT(289) OR ROM32_INSTR_PT(293) + OR ROM32_INSTR_PT(294) OR ROM32_INSTR_PT(295) + OR ROM32_INSTR_PT(297) OR ROM32_INSTR_PT(299) + OR ROM32_INSTR_PT(301) OR ROM32_INSTR_PT(303) + OR ROM32_INSTR_PT(306) OR ROM32_INSTR_PT(313) + OR ROM32_INSTR_PT(321) OR ROM32_INSTR_PT(323) + OR ROM32_INSTR_PT(328) OR ROM32_INSTR_PT(331) + OR ROM32_INSTR_PT(342) OR ROM32_INSTR_PT(345) + OR ROM32_INSTR_PT(348) OR ROM32_INSTR_PT(350) + OR ROM32_INSTR_PT(352) OR ROM32_INSTR_PT(355) + OR ROM32_INSTR_PT(361) OR ROM32_INSTR_PT(362) + OR ROM32_INSTR_PT(363) OR ROM32_INSTR_PT(366) + OR ROM32_INSTR_PT(367) OR ROM32_INSTR_PT(368) + OR ROM32_INSTR_PT(370) OR ROM32_INSTR_PT(371) + OR ROM32_INSTR_PT(374) OR ROM32_INSTR_PT(376) + OR ROM32_INSTR_PT(379) OR ROM32_INSTR_PT(382) + OR ROM32_INSTR_PT(383) OR ROM32_INSTR_PT(386) + OR ROM32_INSTR_PT(387) OR ROM32_INSTR_PT(390) + OR ROM32_INSTR_PT(392) OR ROM32_INSTR_PT(394) + OR ROM32_INSTR_PT(396) OR ROM32_INSTR_PT(400) + OR ROM32_INSTR_PT(401) OR ROM32_INSTR_PT(402) + OR ROM32_INSTR_PT(404) OR ROM32_INSTR_PT(405) + OR ROM32_INSTR_PT(406) OR ROM32_INSTR_PT(409) + OR ROM32_INSTR_PT(411) OR ROM32_INSTR_PT(412) + OR ROM32_INSTR_PT(415) OR ROM32_INSTR_PT(417) + OR ROM32_INSTR_PT(418) OR ROM32_INSTR_PT(421) + OR ROM32_INSTR_PT(422) OR ROM32_INSTR_PT(423) + OR ROM32_INSTR_PT(424) OR ROM32_INSTR_PT(426) + OR ROM32_INSTR_PT(428) OR ROM32_INSTR_PT(430) + OR ROM32_INSTR_PT(433) OR ROM32_INSTR_PT(434) + OR ROM32_INSTR_PT(435) OR ROM32_INSTR_PT(436) + OR ROM32_INSTR_PT(438) OR ROM32_INSTR_PT(441) + OR ROM32_INSTR_PT(442) OR ROM32_INSTR_PT(443) + OR ROM32_INSTR_PT(451) OR ROM32_INSTR_PT(452) + OR ROM32_INSTR_PT(453) OR ROM32_INSTR_PT(454) + OR ROM32_INSTR_PT(458) OR ROM32_INSTR_PT(461) + OR ROM32_INSTR_PT(464) OR ROM32_INSTR_PT(469) + OR ROM32_INSTR_PT(472) OR ROM32_INSTR_PT(474) + OR ROM32_INSTR_PT(475) OR ROM32_INSTR_PT(476) + OR ROM32_INSTR_PT(477) OR ROM32_INSTR_PT(478) + OR ROM32_INSTR_PT(479) OR ROM32_INSTR_PT(480) + OR ROM32_INSTR_PT(481) OR ROM32_INSTR_PT(482) + OR ROM32_INSTR_PT(486) OR ROM32_INSTR_PT(490) + OR ROM32_INSTR_PT(491) OR ROM32_INSTR_PT(494) + OR ROM32_INSTR_PT(496) OR ROM32_INSTR_PT(497) + OR ROM32_INSTR_PT(498) OR ROM32_INSTR_PT(501) + OR ROM32_INSTR_PT(502) OR ROM32_INSTR_PT(503) + OR ROM32_INSTR_PT(505) OR ROM32_INSTR_PT(506) + OR ROM32_INSTR_PT(507) OR ROM32_INSTR_PT(508) + OR ROM32_INSTR_PT(509) OR ROM32_INSTR_PT(514) + OR ROM32_INSTR_PT(517) OR ROM32_INSTR_PT(519) + OR ROM32_INSTR_PT(520) OR ROM32_INSTR_PT(521) + OR ROM32_INSTR_PT(522) OR ROM32_INSTR_PT(524) + OR ROM32_INSTR_PT(530) OR ROM32_INSTR_PT(531) + OR ROM32_INSTR_PT(532) OR ROM32_INSTR_PT(534) + OR ROM32_INSTR_PT(535) OR ROM32_INSTR_PT(536) + OR ROM32_INSTR_PT(538) OR ROM32_INSTR_PT(539) + OR ROM32_INSTR_PT(541) OR ROM32_INSTR_PT(543) + OR ROM32_INSTR_PT(544) OR ROM32_INSTR_PT(546) + OR ROM32_INSTR_PT(547) OR ROM32_INSTR_PT(550) + OR ROM32_INSTR_PT(551) OR ROM32_INSTR_PT(552) + OR ROM32_INSTR_PT(554) OR ROM32_INSTR_PT(556) + OR ROM32_INSTR_PT(557) OR ROM32_INSTR_PT(558) + OR ROM32_INSTR_PT(562) OR ROM32_INSTR_PT(566) + OR ROM32_INSTR_PT(568) OR ROM32_INSTR_PT(569) + OR ROM32_INSTR_PT(570) OR ROM32_INSTR_PT(574) + OR ROM32_INSTR_PT(575) OR ROM32_INSTR_PT(578) + OR ROM32_INSTR_PT(579) OR ROM32_INSTR_PT(580) + OR ROM32_INSTR_PT(581) OR ROM32_INSTR_PT(582) + OR ROM32_INSTR_PT(583) OR ROM32_INSTR_PT(584) + OR ROM32_INSTR_PT(585) OR ROM32_INSTR_PT(588) + OR ROM32_INSTR_PT(589) OR ROM32_INSTR_PT(590) + OR ROM32_INSTR_PT(593) OR ROM32_INSTR_PT(595) + OR ROM32_INSTR_PT(598) OR ROM32_INSTR_PT(599) + OR ROM32_INSTR_PT(600) OR ROM32_INSTR_PT(601) + OR ROM32_INSTR_PT(602) OR ROM32_INSTR_PT(605) + OR ROM32_INSTR_PT(606) OR ROM32_INSTR_PT(607) + OR ROM32_INSTR_PT(608) OR ROM32_INSTR_PT(609) + OR ROM32_INSTR_PT(610) OR ROM32_INSTR_PT(611) + OR ROM32_INSTR_PT(612) OR ROM32_INSTR_PT(613) + OR ROM32_INSTR_PT(614) OR ROM32_INSTR_PT(620) + OR ROM32_INSTR_PT(621) OR ROM32_INSTR_PT(624) + OR ROM32_INSTR_PT(625) OR ROM32_INSTR_PT(626) + OR ROM32_INSTR_PT(630) OR ROM32_INSTR_PT(634) + OR ROM32_INSTR_PT(635) OR ROM32_INSTR_PT(638) + OR ROM32_INSTR_PT(639) OR ROM32_INSTR_PT(642) + OR ROM32_INSTR_PT(643) OR ROM32_INSTR_PT(644) + OR ROM32_INSTR_PT(647) OR ROM32_INSTR_PT(654) + OR ROM32_INSTR_PT(660) OR ROM32_INSTR_PT(663) + OR ROM32_INSTR_PT(666) OR ROM32_INSTR_PT(674) + OR ROM32_INSTR_PT(677) OR ROM32_INSTR_PT(678) + OR ROM32_INSTR_PT(680) OR ROM32_INSTR_PT(684) + OR ROM32_INSTR_PT(685) OR ROM32_INSTR_PT(698) + OR ROM32_INSTR_PT(708) OR ROM32_INSTR_PT(713) + OR ROM32_INSTR_PT(719) OR ROM32_INSTR_PT(726) + OR ROM32_INSTR_PT(733) OR ROM32_INSTR_PT(736) + OR ROM32_INSTR_PT(745) OR ROM32_INSTR_PT(755) + OR ROM32_INSTR_PT(762) OR ROM32_INSTR_PT(770) + OR ROM32_INSTR_PT(785) OR ROM32_INSTR_PT(795) + OR ROM32_INSTR_PT(801) OR ROM32_INSTR_PT(805) + OR ROM32_INSTR_PT(812) OR ROM32_INSTR_PT(817) + OR ROM32_INSTR_PT(819) OR ROM32_INSTR_PT(845) + OR ROM32_INSTR_PT(847) OR ROM32_INSTR_PT(851) + OR ROM32_INSTR_PT(853) OR ROM32_INSTR_PT(854) + OR ROM32_INSTR_PT(855) OR ROM32_INSTR_PT(862) + OR ROM32_INSTR_PT(869) OR ROM32_INSTR_PT(870) + OR ROM32_INSTR_PT(871) OR ROM32_INSTR_PT(878) + OR ROM32_INSTR_PT(889)); +MQQ1857:TEMPLATE(2) <= + (ROM32_INSTR_PT(4) OR ROM32_INSTR_PT(5) + OR ROM32_INSTR_PT(6) OR ROM32_INSTR_PT(7) + OR ROM32_INSTR_PT(13) OR ROM32_INSTR_PT(14) + OR ROM32_INSTR_PT(18) OR ROM32_INSTR_PT(23) + OR ROM32_INSTR_PT(27) OR ROM32_INSTR_PT(29) + OR ROM32_INSTR_PT(31) OR ROM32_INSTR_PT(35) + OR ROM32_INSTR_PT(38) OR ROM32_INSTR_PT(39) + OR ROM32_INSTR_PT(41) OR ROM32_INSTR_PT(42) + OR ROM32_INSTR_PT(43) OR ROM32_INSTR_PT(53) + OR ROM32_INSTR_PT(56) OR ROM32_INSTR_PT(57) + OR ROM32_INSTR_PT(62) OR ROM32_INSTR_PT(70) + OR ROM32_INSTR_PT(72) OR ROM32_INSTR_PT(79) + OR ROM32_INSTR_PT(80) OR ROM32_INSTR_PT(81) + OR ROM32_INSTR_PT(83) OR ROM32_INSTR_PT(92) + OR ROM32_INSTR_PT(95) OR ROM32_INSTR_PT(97) + OR ROM32_INSTR_PT(98) OR ROM32_INSTR_PT(101) + OR ROM32_INSTR_PT(102) OR ROM32_INSTR_PT(105) + OR ROM32_INSTR_PT(109) OR ROM32_INSTR_PT(110) + OR ROM32_INSTR_PT(111) OR ROM32_INSTR_PT(117) + OR ROM32_INSTR_PT(122) OR ROM32_INSTR_PT(124) + OR ROM32_INSTR_PT(130) OR ROM32_INSTR_PT(139) + OR ROM32_INSTR_PT(141) OR ROM32_INSTR_PT(144) + OR ROM32_INSTR_PT(145) OR ROM32_INSTR_PT(146) + OR ROM32_INSTR_PT(147) OR ROM32_INSTR_PT(150) + OR ROM32_INSTR_PT(151) OR ROM32_INSTR_PT(153) + OR ROM32_INSTR_PT(158) OR ROM32_INSTR_PT(163) + OR ROM32_INSTR_PT(165) OR ROM32_INSTR_PT(166) + OR ROM32_INSTR_PT(172) OR ROM32_INSTR_PT(174) + OR ROM32_INSTR_PT(185) OR ROM32_INSTR_PT(186) + OR ROM32_INSTR_PT(187) OR ROM32_INSTR_PT(189) + OR ROM32_INSTR_PT(192) OR ROM32_INSTR_PT(193) + OR ROM32_INSTR_PT(195) OR ROM32_INSTR_PT(199) + OR ROM32_INSTR_PT(203) OR ROM32_INSTR_PT(205) + OR ROM32_INSTR_PT(206) OR ROM32_INSTR_PT(207) + OR ROM32_INSTR_PT(208) OR ROM32_INSTR_PT(209) + OR ROM32_INSTR_PT(210) OR ROM32_INSTR_PT(218) + OR ROM32_INSTR_PT(228) OR ROM32_INSTR_PT(229) + OR ROM32_INSTR_PT(230) OR ROM32_INSTR_PT(232) + OR ROM32_INSTR_PT(235) OR ROM32_INSTR_PT(240) + OR ROM32_INSTR_PT(245) OR ROM32_INSTR_PT(249) + OR ROM32_INSTR_PT(251) OR ROM32_INSTR_PT(252) + OR ROM32_INSTR_PT(254) OR ROM32_INSTR_PT(256) + OR ROM32_INSTR_PT(257) OR ROM32_INSTR_PT(262) + OR ROM32_INSTR_PT(268) OR ROM32_INSTR_PT(275) + OR ROM32_INSTR_PT(279) OR ROM32_INSTR_PT(285) + OR ROM32_INSTR_PT(287) OR ROM32_INSTR_PT(289) + OR ROM32_INSTR_PT(291) OR ROM32_INSTR_PT(294) + OR ROM32_INSTR_PT(302) OR ROM32_INSTR_PT(305) + OR ROM32_INSTR_PT(307) OR ROM32_INSTR_PT(311) + OR ROM32_INSTR_PT(322) OR ROM32_INSTR_PT(323) + OR ROM32_INSTR_PT(325) OR ROM32_INSTR_PT(329) + OR ROM32_INSTR_PT(331) OR ROM32_INSTR_PT(332) + OR ROM32_INSTR_PT(337) OR ROM32_INSTR_PT(338) + OR ROM32_INSTR_PT(339) OR ROM32_INSTR_PT(342) + OR ROM32_INSTR_PT(350) OR ROM32_INSTR_PT(352) + OR ROM32_INSTR_PT(355) OR ROM32_INSTR_PT(362) + OR ROM32_INSTR_PT(363) OR ROM32_INSTR_PT(366) + OR ROM32_INSTR_PT(367) OR ROM32_INSTR_PT(368) + OR ROM32_INSTR_PT(370) OR ROM32_INSTR_PT(374) + OR ROM32_INSTR_PT(376) OR ROM32_INSTR_PT(378) + OR ROM32_INSTR_PT(382) OR ROM32_INSTR_PT(386) + OR ROM32_INSTR_PT(387) OR ROM32_INSTR_PT(393) + OR ROM32_INSTR_PT(394) OR ROM32_INSTR_PT(395) + OR ROM32_INSTR_PT(398) OR ROM32_INSTR_PT(400) + OR ROM32_INSTR_PT(402) OR ROM32_INSTR_PT(404) + OR ROM32_INSTR_PT(405) OR ROM32_INSTR_PT(409) + OR ROM32_INSTR_PT(415) OR ROM32_INSTR_PT(416) + OR ROM32_INSTR_PT(417) OR ROM32_INSTR_PT(418) + OR ROM32_INSTR_PT(419) OR ROM32_INSTR_PT(422) + OR ROM32_INSTR_PT(423) OR ROM32_INSTR_PT(426) + OR ROM32_INSTR_PT(434) OR ROM32_INSTR_PT(435) + OR ROM32_INSTR_PT(436) OR ROM32_INSTR_PT(438) + OR ROM32_INSTR_PT(441) OR ROM32_INSTR_PT(442) + OR ROM32_INSTR_PT(443) OR ROM32_INSTR_PT(446) + OR ROM32_INSTR_PT(451) OR ROM32_INSTR_PT(452) + OR ROM32_INSTR_PT(454) OR ROM32_INSTR_PT(456) + OR ROM32_INSTR_PT(458) OR ROM32_INSTR_PT(461) + OR ROM32_INSTR_PT(463) OR ROM32_INSTR_PT(464) + OR ROM32_INSTR_PT(465) OR ROM32_INSTR_PT(468) + OR ROM32_INSTR_PT(469) OR ROM32_INSTR_PT(471) + OR ROM32_INSTR_PT(472) OR ROM32_INSTR_PT(474) + OR ROM32_INSTR_PT(476) OR ROM32_INSTR_PT(480) + OR ROM32_INSTR_PT(486) OR ROM32_INSTR_PT(489) + OR ROM32_INSTR_PT(496) OR ROM32_INSTR_PT(497) + OR ROM32_INSTR_PT(498) OR ROM32_INSTR_PT(503) + OR ROM32_INSTR_PT(505) OR ROM32_INSTR_PT(507) + OR ROM32_INSTR_PT(513) OR ROM32_INSTR_PT(514) + OR ROM32_INSTR_PT(517) OR ROM32_INSTR_PT(532) + OR ROM32_INSTR_PT(537) OR ROM32_INSTR_PT(539) + OR ROM32_INSTR_PT(541) OR ROM32_INSTR_PT(544) + OR ROM32_INSTR_PT(547) OR ROM32_INSTR_PT(549) + OR ROM32_INSTR_PT(551) OR ROM32_INSTR_PT(557) + OR ROM32_INSTR_PT(558) OR ROM32_INSTR_PT(561) + OR ROM32_INSTR_PT(566) OR ROM32_INSTR_PT(569) + OR ROM32_INSTR_PT(570) OR ROM32_INSTR_PT(574) + OR ROM32_INSTR_PT(577) OR ROM32_INSTR_PT(579) + OR ROM32_INSTR_PT(580) OR ROM32_INSTR_PT(584) + OR ROM32_INSTR_PT(587) OR ROM32_INSTR_PT(589) + OR ROM32_INSTR_PT(591) OR ROM32_INSTR_PT(593) + OR ROM32_INSTR_PT(596) OR ROM32_INSTR_PT(598) + OR ROM32_INSTR_PT(599) OR ROM32_INSTR_PT(600) + OR ROM32_INSTR_PT(605) OR ROM32_INSTR_PT(606) + OR ROM32_INSTR_PT(607) OR ROM32_INSTR_PT(608) + OR ROM32_INSTR_PT(609) OR ROM32_INSTR_PT(610) + OR ROM32_INSTR_PT(611) OR ROM32_INSTR_PT(614) + OR ROM32_INSTR_PT(620) OR ROM32_INSTR_PT(624) + OR ROM32_INSTR_PT(625) OR ROM32_INSTR_PT(629) + OR ROM32_INSTR_PT(632) OR ROM32_INSTR_PT(634) + OR ROM32_INSTR_PT(638) OR ROM32_INSTR_PT(640) + OR ROM32_INSTR_PT(643) OR ROM32_INSTR_PT(653) + OR ROM32_INSTR_PT(659) OR ROM32_INSTR_PT(660) + OR ROM32_INSTR_PT(663) OR ROM32_INSTR_PT(668) + OR ROM32_INSTR_PT(672) OR ROM32_INSTR_PT(678) + OR ROM32_INSTR_PT(680) OR ROM32_INSTR_PT(684) + OR ROM32_INSTR_PT(685) OR ROM32_INSTR_PT(689) + OR ROM32_INSTR_PT(698) OR ROM32_INSTR_PT(704) + OR ROM32_INSTR_PT(705) OR ROM32_INSTR_PT(708) + OR ROM32_INSTR_PT(713) OR ROM32_INSTR_PT(720) + OR ROM32_INSTR_PT(728) OR ROM32_INSTR_PT(733) + OR ROM32_INSTR_PT(751) OR ROM32_INSTR_PT(752) + OR ROM32_INSTR_PT(753) OR ROM32_INSTR_PT(759) + OR ROM32_INSTR_PT(774) OR ROM32_INSTR_PT(785) + OR ROM32_INSTR_PT(787) OR ROM32_INSTR_PT(790) + OR ROM32_INSTR_PT(795) OR ROM32_INSTR_PT(799) + OR ROM32_INSTR_PT(801) OR ROM32_INSTR_PT(803) + OR ROM32_INSTR_PT(805) OR ROM32_INSTR_PT(807) + OR ROM32_INSTR_PT(812) OR ROM32_INSTR_PT(817) + OR ROM32_INSTR_PT(819) OR ROM32_INSTR_PT(823) + OR ROM32_INSTR_PT(845) OR ROM32_INSTR_PT(847) + OR ROM32_INSTR_PT(851) OR ROM32_INSTR_PT(853) + OR ROM32_INSTR_PT(854) OR ROM32_INSTR_PT(869) + OR ROM32_INSTR_PT(871) OR ROM32_INSTR_PT(878) + OR ROM32_INSTR_PT(881) OR ROM32_INSTR_PT(889) + ); +MQQ1858:TEMPLATE(3) <= + (ROM32_INSTR_PT(4) OR ROM32_INSTR_PT(5) + OR ROM32_INSTR_PT(6) OR ROM32_INSTR_PT(7) + OR ROM32_INSTR_PT(8) OR ROM32_INSTR_PT(9) + OR ROM32_INSTR_PT(10) OR ROM32_INSTR_PT(13) + OR ROM32_INSTR_PT(14) OR ROM32_INSTR_PT(16) + OR ROM32_INSTR_PT(17) OR ROM32_INSTR_PT(18) + OR ROM32_INSTR_PT(20) OR ROM32_INSTR_PT(23) + OR ROM32_INSTR_PT(26) OR ROM32_INSTR_PT(27) + OR ROM32_INSTR_PT(28) OR ROM32_INSTR_PT(31) + OR ROM32_INSTR_PT(32) OR ROM32_INSTR_PT(33) + OR ROM32_INSTR_PT(35) OR ROM32_INSTR_PT(37) + OR ROM32_INSTR_PT(38) OR ROM32_INSTR_PT(39) + OR ROM32_INSTR_PT(41) OR ROM32_INSTR_PT(42) + OR ROM32_INSTR_PT(43) OR ROM32_INSTR_PT(45) + OR ROM32_INSTR_PT(49) OR ROM32_INSTR_PT(52) + OR ROM32_INSTR_PT(53) OR ROM32_INSTR_PT(56) + OR ROM32_INSTR_PT(57) OR ROM32_INSTR_PT(59) + OR ROM32_INSTR_PT(62) OR ROM32_INSTR_PT(63) + OR ROM32_INSTR_PT(66) OR ROM32_INSTR_PT(67) + OR ROM32_INSTR_PT(70) OR ROM32_INSTR_PT(72) + OR ROM32_INSTR_PT(73) OR ROM32_INSTR_PT(74) + OR ROM32_INSTR_PT(77) OR ROM32_INSTR_PT(78) + OR ROM32_INSTR_PT(79) OR ROM32_INSTR_PT(80) + OR ROM32_INSTR_PT(83) OR ROM32_INSTR_PT(84) + OR ROM32_INSTR_PT(85) OR ROM32_INSTR_PT(87) + OR ROM32_INSTR_PT(90) OR ROM32_INSTR_PT(92) + OR ROM32_INSTR_PT(93) OR ROM32_INSTR_PT(95) + OR ROM32_INSTR_PT(97) OR ROM32_INSTR_PT(98) + OR ROM32_INSTR_PT(99) OR ROM32_INSTR_PT(101) + OR ROM32_INSTR_PT(102) OR ROM32_INSTR_PT(103) + OR ROM32_INSTR_PT(105) OR ROM32_INSTR_PT(109) + OR ROM32_INSTR_PT(110) OR ROM32_INSTR_PT(111) + OR ROM32_INSTR_PT(114) OR ROM32_INSTR_PT(115) + OR ROM32_INSTR_PT(116) OR ROM32_INSTR_PT(117) + OR ROM32_INSTR_PT(118) OR ROM32_INSTR_PT(119) + OR ROM32_INSTR_PT(122) OR ROM32_INSTR_PT(124) + OR ROM32_INSTR_PT(127) OR ROM32_INSTR_PT(130) + OR ROM32_INSTR_PT(131) OR ROM32_INSTR_PT(134) + OR ROM32_INSTR_PT(139) OR ROM32_INSTR_PT(141) + OR ROM32_INSTR_PT(144) OR ROM32_INSTR_PT(145) + OR ROM32_INSTR_PT(146) OR ROM32_INSTR_PT(147) + OR ROM32_INSTR_PT(148) OR ROM32_INSTR_PT(150) + OR ROM32_INSTR_PT(151) OR ROM32_INSTR_PT(153) + OR ROM32_INSTR_PT(155) OR ROM32_INSTR_PT(158) + OR ROM32_INSTR_PT(162) OR ROM32_INSTR_PT(163) + OR ROM32_INSTR_PT(164) OR ROM32_INSTR_PT(165) + OR ROM32_INSTR_PT(166) OR ROM32_INSTR_PT(169) + OR ROM32_INSTR_PT(171) OR ROM32_INSTR_PT(172) + OR ROM32_INSTR_PT(173) OR ROM32_INSTR_PT(174) + OR ROM32_INSTR_PT(176) OR ROM32_INSTR_PT(177) + OR ROM32_INSTR_PT(178) OR ROM32_INSTR_PT(179) + OR ROM32_INSTR_PT(180) OR ROM32_INSTR_PT(181) + OR ROM32_INSTR_PT(184) OR ROM32_INSTR_PT(185) + OR ROM32_INSTR_PT(186) OR ROM32_INSTR_PT(187) + OR ROM32_INSTR_PT(189) OR ROM32_INSTR_PT(192) + OR ROM32_INSTR_PT(194) OR ROM32_INSTR_PT(199) + OR ROM32_INSTR_PT(200) OR ROM32_INSTR_PT(202) + OR ROM32_INSTR_PT(203) OR ROM32_INSTR_PT(205) + OR ROM32_INSTR_PT(206) OR ROM32_INSTR_PT(207) + OR ROM32_INSTR_PT(208) OR ROM32_INSTR_PT(209) + OR ROM32_INSTR_PT(210) OR ROM32_INSTR_PT(212) + OR ROM32_INSTR_PT(216) OR ROM32_INSTR_PT(218) + OR ROM32_INSTR_PT(219) OR ROM32_INSTR_PT(220) + OR ROM32_INSTR_PT(222) OR ROM32_INSTR_PT(223) + OR ROM32_INSTR_PT(224) OR ROM32_INSTR_PT(226) + OR ROM32_INSTR_PT(227) OR ROM32_INSTR_PT(228) + OR ROM32_INSTR_PT(229) OR ROM32_INSTR_PT(230) + OR ROM32_INSTR_PT(232) OR ROM32_INSTR_PT(233) + OR ROM32_INSTR_PT(235) OR ROM32_INSTR_PT(238) + OR ROM32_INSTR_PT(240) OR ROM32_INSTR_PT(242) + OR ROM32_INSTR_PT(244) OR ROM32_INSTR_PT(245) + OR ROM32_INSTR_PT(249) OR ROM32_INSTR_PT(250) + OR ROM32_INSTR_PT(251) OR ROM32_INSTR_PT(252) + OR ROM32_INSTR_PT(254) OR ROM32_INSTR_PT(255) + OR ROM32_INSTR_PT(256) OR ROM32_INSTR_PT(257) + OR ROM32_INSTR_PT(259) OR ROM32_INSTR_PT(261) + OR ROM32_INSTR_PT(262) OR ROM32_INSTR_PT(264) + OR ROM32_INSTR_PT(266) OR ROM32_INSTR_PT(267) + OR ROM32_INSTR_PT(268) OR ROM32_INSTR_PT(269) + OR ROM32_INSTR_PT(270) OR ROM32_INSTR_PT(271) + OR ROM32_INSTR_PT(272) OR ROM32_INSTR_PT(273) + OR ROM32_INSTR_PT(275) OR ROM32_INSTR_PT(278) + OR ROM32_INSTR_PT(279) OR ROM32_INSTR_PT(280) + OR ROM32_INSTR_PT(284) OR ROM32_INSTR_PT(285) + OR ROM32_INSTR_PT(288) OR ROM32_INSTR_PT(289) + OR ROM32_INSTR_PT(290) OR ROM32_INSTR_PT(291) + OR ROM32_INSTR_PT(294) OR ROM32_INSTR_PT(295) + OR ROM32_INSTR_PT(297) OR ROM32_INSTR_PT(299) + OR ROM32_INSTR_PT(301) OR ROM32_INSTR_PT(302) + OR ROM32_INSTR_PT(303) OR ROM32_INSTR_PT(305) + OR ROM32_INSTR_PT(307) OR ROM32_INSTR_PT(309) + OR ROM32_INSTR_PT(311) OR ROM32_INSTR_PT(313) + OR ROM32_INSTR_PT(318) OR ROM32_INSTR_PT(322) + OR ROM32_INSTR_PT(323) OR ROM32_INSTR_PT(325) + OR ROM32_INSTR_PT(328) OR ROM32_INSTR_PT(329) + OR ROM32_INSTR_PT(332) OR ROM32_INSTR_PT(335) + OR ROM32_INSTR_PT(337) OR ROM32_INSTR_PT(338) + OR ROM32_INSTR_PT(339) OR ROM32_INSTR_PT(344) + OR ROM32_INSTR_PT(346) OR ROM32_INSTR_PT(348) + OR ROM32_INSTR_PT(350) OR ROM32_INSTR_PT(357) + OR ROM32_INSTR_PT(361) OR ROM32_INSTR_PT(362) + OR ROM32_INSTR_PT(363) OR ROM32_INSTR_PT(366) + OR ROM32_INSTR_PT(367) OR ROM32_INSTR_PT(368) + OR ROM32_INSTR_PT(371) OR ROM32_INSTR_PT(373) + OR ROM32_INSTR_PT(374) OR ROM32_INSTR_PT(376) + OR ROM32_INSTR_PT(378) OR ROM32_INSTR_PT(379) + OR ROM32_INSTR_PT(381) OR ROM32_INSTR_PT(382) + OR ROM32_INSTR_PT(383) OR ROM32_INSTR_PT(386) + OR ROM32_INSTR_PT(387) OR ROM32_INSTR_PT(388) + OR ROM32_INSTR_PT(390) OR ROM32_INSTR_PT(392) + OR ROM32_INSTR_PT(393) OR ROM32_INSTR_PT(394) + OR ROM32_INSTR_PT(395) OR ROM32_INSTR_PT(396) + OR ROM32_INSTR_PT(398) OR ROM32_INSTR_PT(400) + OR ROM32_INSTR_PT(401) OR ROM32_INSTR_PT(402) + OR ROM32_INSTR_PT(404) OR ROM32_INSTR_PT(405) + OR ROM32_INSTR_PT(406) OR ROM32_INSTR_PT(409) + OR ROM32_INSTR_PT(411) OR ROM32_INSTR_PT(412) + OR ROM32_INSTR_PT(415) OR ROM32_INSTR_PT(416) + OR ROM32_INSTR_PT(417) OR ROM32_INSTR_PT(418) + OR ROM32_INSTR_PT(419) OR ROM32_INSTR_PT(421) + OR ROM32_INSTR_PT(422) OR ROM32_INSTR_PT(423) + OR ROM32_INSTR_PT(424) OR ROM32_INSTR_PT(425) + OR ROM32_INSTR_PT(426) OR ROM32_INSTR_PT(433) + OR ROM32_INSTR_PT(434) OR ROM32_INSTR_PT(435) + OR ROM32_INSTR_PT(436) OR ROM32_INSTR_PT(437) + OR ROM32_INSTR_PT(438) OR ROM32_INSTR_PT(441) + OR ROM32_INSTR_PT(442) OR ROM32_INSTR_PT(443) + OR ROM32_INSTR_PT(446) OR ROM32_INSTR_PT(451) + OR ROM32_INSTR_PT(452) OR ROM32_INSTR_PT(453) + OR ROM32_INSTR_PT(454) OR ROM32_INSTR_PT(456) + OR ROM32_INSTR_PT(458) OR ROM32_INSTR_PT(461) + OR ROM32_INSTR_PT(463) OR ROM32_INSTR_PT(464) + OR ROM32_INSTR_PT(465) OR ROM32_INSTR_PT(467) + OR ROM32_INSTR_PT(468) OR ROM32_INSTR_PT(469) + OR ROM32_INSTR_PT(471) OR ROM32_INSTR_PT(472) + OR ROM32_INSTR_PT(474) OR ROM32_INSTR_PT(475) + OR ROM32_INSTR_PT(476) OR ROM32_INSTR_PT(478) + OR ROM32_INSTR_PT(479) OR ROM32_INSTR_PT(480) + OR ROM32_INSTR_PT(481) OR ROM32_INSTR_PT(482) + OR ROM32_INSTR_PT(484) OR ROM32_INSTR_PT(486) + OR ROM32_INSTR_PT(489) OR ROM32_INSTR_PT(490) + OR ROM32_INSTR_PT(494) OR ROM32_INSTR_PT(495) + OR ROM32_INSTR_PT(496) OR ROM32_INSTR_PT(497) + OR ROM32_INSTR_PT(502) OR ROM32_INSTR_PT(503) + OR ROM32_INSTR_PT(505) OR ROM32_INSTR_PT(506) + OR ROM32_INSTR_PT(507) OR ROM32_INSTR_PT(508) + OR ROM32_INSTR_PT(513) OR ROM32_INSTR_PT(514) + OR ROM32_INSTR_PT(517) OR ROM32_INSTR_PT(519) + OR ROM32_INSTR_PT(520) OR ROM32_INSTR_PT(521) + OR ROM32_INSTR_PT(522) OR ROM32_INSTR_PT(524) + OR ROM32_INSTR_PT(532) OR ROM32_INSTR_PT(534) + OR ROM32_INSTR_PT(537) OR ROM32_INSTR_PT(539) + OR ROM32_INSTR_PT(541) OR ROM32_INSTR_PT(544) + OR ROM32_INSTR_PT(547) OR ROM32_INSTR_PT(549) + OR ROM32_INSTR_PT(550) OR ROM32_INSTR_PT(551) + OR ROM32_INSTR_PT(552) OR ROM32_INSTR_PT(554) + OR ROM32_INSTR_PT(556) OR ROM32_INSTR_PT(557) + OR ROM32_INSTR_PT(558) OR ROM32_INSTR_PT(561) + OR ROM32_INSTR_PT(562) OR ROM32_INSTR_PT(563) + OR ROM32_INSTR_PT(566) OR ROM32_INSTR_PT(568) + OR ROM32_INSTR_PT(569) OR ROM32_INSTR_PT(570) + OR ROM32_INSTR_PT(571) OR ROM32_INSTR_PT(574) + OR ROM32_INSTR_PT(575) OR ROM32_INSTR_PT(577) + OR ROM32_INSTR_PT(578) OR ROM32_INSTR_PT(579) + OR ROM32_INSTR_PT(580) OR ROM32_INSTR_PT(581) + OR ROM32_INSTR_PT(582) OR ROM32_INSTR_PT(583) + OR ROM32_INSTR_PT(584) OR ROM32_INSTR_PT(585) + OR ROM32_INSTR_PT(586) OR ROM32_INSTR_PT(587) + OR ROM32_INSTR_PT(588) OR ROM32_INSTR_PT(590) + OR ROM32_INSTR_PT(591) OR ROM32_INSTR_PT(593) + OR ROM32_INSTR_PT(595) OR ROM32_INSTR_PT(596) + OR ROM32_INSTR_PT(598) OR ROM32_INSTR_PT(599) + OR ROM32_INSTR_PT(600) OR ROM32_INSTR_PT(602) + OR ROM32_INSTR_PT(604) OR ROM32_INSTR_PT(605) + OR ROM32_INSTR_PT(606) OR ROM32_INSTR_PT(607) + OR ROM32_INSTR_PT(608) OR ROM32_INSTR_PT(609) + OR ROM32_INSTR_PT(610) OR ROM32_INSTR_PT(611) + OR ROM32_INSTR_PT(612) OR ROM32_INSTR_PT(614) + OR ROM32_INSTR_PT(620) OR ROM32_INSTR_PT(621) + OR ROM32_INSTR_PT(624) OR ROM32_INSTR_PT(625) + OR ROM32_INSTR_PT(626) OR ROM32_INSTR_PT(629) + OR ROM32_INSTR_PT(630) OR ROM32_INSTR_PT(632) + OR ROM32_INSTR_PT(634) OR ROM32_INSTR_PT(638) + OR ROM32_INSTR_PT(639) OR ROM32_INSTR_PT(640) + OR ROM32_INSTR_PT(642) OR ROM32_INSTR_PT(643) + OR ROM32_INSTR_PT(644) OR ROM32_INSTR_PT(653) + OR ROM32_INSTR_PT(657) OR ROM32_INSTR_PT(659) + OR ROM32_INSTR_PT(660) OR ROM32_INSTR_PT(663) + OR ROM32_INSTR_PT(664) OR ROM32_INSTR_PT(666) + OR ROM32_INSTR_PT(668) OR ROM32_INSTR_PT(672) + OR ROM32_INSTR_PT(677) OR ROM32_INSTR_PT(680) + OR ROM32_INSTR_PT(684) OR ROM32_INSTR_PT(689) + OR ROM32_INSTR_PT(692) OR ROM32_INSTR_PT(698) + OR ROM32_INSTR_PT(702) OR ROM32_INSTR_PT(704) + OR ROM32_INSTR_PT(708) OR ROM32_INSTR_PT(713) + OR ROM32_INSTR_PT(718) OR ROM32_INSTR_PT(719) + OR ROM32_INSTR_PT(720) OR ROM32_INSTR_PT(726) + OR ROM32_INSTR_PT(728) OR ROM32_INSTR_PT(729) + OR ROM32_INSTR_PT(736) OR ROM32_INSTR_PT(751) + OR ROM32_INSTR_PT(752) OR ROM32_INSTR_PT(753) + OR ROM32_INSTR_PT(755) OR ROM32_INSTR_PT(759) + OR ROM32_INSTR_PT(762) OR ROM32_INSTR_PT(770) + OR ROM32_INSTR_PT(774) OR ROM32_INSTR_PT(787) + OR ROM32_INSTR_PT(790) OR ROM32_INSTR_PT(792) + OR ROM32_INSTR_PT(803) OR ROM32_INSTR_PT(805) + OR ROM32_INSTR_PT(807) OR ROM32_INSTR_PT(812) + OR ROM32_INSTR_PT(817) OR ROM32_INSTR_PT(819) + OR ROM32_INSTR_PT(823) OR ROM32_INSTR_PT(831) + OR ROM32_INSTR_PT(845) OR ROM32_INSTR_PT(853) + OR ROM32_INSTR_PT(854) OR ROM32_INSTR_PT(855) + OR ROM32_INSTR_PT(857) OR ROM32_INSTR_PT(862) + OR ROM32_INSTR_PT(869) OR ROM32_INSTR_PT(870) + OR ROM32_INSTR_PT(878) OR ROM32_INSTR_PT(881) + ); +MQQ1859:TEMPLATE(4) <= + (ROM32_INSTR_PT(4) OR ROM32_INSTR_PT(5) + OR ROM32_INSTR_PT(6) OR ROM32_INSTR_PT(7) + OR ROM32_INSTR_PT(13) OR ROM32_INSTR_PT(14) + OR ROM32_INSTR_PT(18) OR ROM32_INSTR_PT(23) + OR ROM32_INSTR_PT(27) OR ROM32_INSTR_PT(28) + OR ROM32_INSTR_PT(29) OR ROM32_INSTR_PT(31) + OR ROM32_INSTR_PT(33) OR ROM32_INSTR_PT(35) + OR ROM32_INSTR_PT(38) OR ROM32_INSTR_PT(39) + OR ROM32_INSTR_PT(41) OR ROM32_INSTR_PT(42) + OR ROM32_INSTR_PT(43) OR ROM32_INSTR_PT(45) + OR ROM32_INSTR_PT(53) OR ROM32_INSTR_PT(56) + OR ROM32_INSTR_PT(57) OR ROM32_INSTR_PT(62) + OR ROM32_INSTR_PT(68) OR ROM32_INSTR_PT(70) + OR ROM32_INSTR_PT(72) OR ROM32_INSTR_PT(76) + OR ROM32_INSTR_PT(79) OR ROM32_INSTR_PT(80) + OR ROM32_INSTR_PT(81) OR ROM32_INSTR_PT(83) + OR ROM32_INSTR_PT(85) OR ROM32_INSTR_PT(92) + OR ROM32_INSTR_PT(95) OR ROM32_INSTR_PT(97) + OR ROM32_INSTR_PT(98) OR ROM32_INSTR_PT(101) + OR ROM32_INSTR_PT(102) OR ROM32_INSTR_PT(105) + OR ROM32_INSTR_PT(109) OR ROM32_INSTR_PT(110) + OR ROM32_INSTR_PT(111) OR ROM32_INSTR_PT(113) + OR ROM32_INSTR_PT(117) OR ROM32_INSTR_PT(120) + OR ROM32_INSTR_PT(122) OR ROM32_INSTR_PT(124) + OR ROM32_INSTR_PT(128) OR ROM32_INSTR_PT(130) + OR ROM32_INSTR_PT(138) OR ROM32_INSTR_PT(139) + OR ROM32_INSTR_PT(141) OR ROM32_INSTR_PT(142) + OR ROM32_INSTR_PT(144) OR ROM32_INSTR_PT(145) + OR ROM32_INSTR_PT(146) OR ROM32_INSTR_PT(147) + OR ROM32_INSTR_PT(150) OR ROM32_INSTR_PT(151) + OR ROM32_INSTR_PT(153) OR ROM32_INSTR_PT(155) + OR ROM32_INSTR_PT(158) OR ROM32_INSTR_PT(159) + OR ROM32_INSTR_PT(162) OR ROM32_INSTR_PT(163) + OR ROM32_INSTR_PT(165) OR ROM32_INSTR_PT(166) + OR ROM32_INSTR_PT(172) OR ROM32_INSTR_PT(173) + OR ROM32_INSTR_PT(174) OR ROM32_INSTR_PT(175) + OR ROM32_INSTR_PT(176) OR ROM32_INSTR_PT(177) + OR ROM32_INSTR_PT(178) OR ROM32_INSTR_PT(180) + OR ROM32_INSTR_PT(181) OR ROM32_INSTR_PT(185) + OR ROM32_INSTR_PT(186) OR ROM32_INSTR_PT(187) + OR ROM32_INSTR_PT(189) OR ROM32_INSTR_PT(192) + OR ROM32_INSTR_PT(193) OR ROM32_INSTR_PT(194) + OR ROM32_INSTR_PT(199) OR ROM32_INSTR_PT(203) + OR ROM32_INSTR_PT(205) OR ROM32_INSTR_PT(206) + OR ROM32_INSTR_PT(207) OR ROM32_INSTR_PT(208) + OR ROM32_INSTR_PT(209) OR ROM32_INSTR_PT(210) + OR ROM32_INSTR_PT(212) OR ROM32_INSTR_PT(218) + OR ROM32_INSTR_PT(222) OR ROM32_INSTR_PT(226) + OR ROM32_INSTR_PT(228) OR ROM32_INSTR_PT(229) + OR ROM32_INSTR_PT(230) OR ROM32_INSTR_PT(232) + OR ROM32_INSTR_PT(233) OR ROM32_INSTR_PT(235) + OR ROM32_INSTR_PT(237) OR ROM32_INSTR_PT(240) + OR ROM32_INSTR_PT(242) OR ROM32_INSTR_PT(245) + OR ROM32_INSTR_PT(249) OR ROM32_INSTR_PT(251) + OR ROM32_INSTR_PT(252) OR ROM32_INSTR_PT(254) + OR ROM32_INSTR_PT(255) OR ROM32_INSTR_PT(256) + OR ROM32_INSTR_PT(257) OR ROM32_INSTR_PT(262) + OR ROM32_INSTR_PT(266) OR ROM32_INSTR_PT(268) + OR ROM32_INSTR_PT(272) OR ROM32_INSTR_PT(275) + OR ROM32_INSTR_PT(279) OR ROM32_INSTR_PT(285) + OR ROM32_INSTR_PT(287) OR ROM32_INSTR_PT(289) + OR ROM32_INSTR_PT(290) OR ROM32_INSTR_PT(291) + OR ROM32_INSTR_PT(292) OR ROM32_INSTR_PT(294) + OR ROM32_INSTR_PT(302) OR ROM32_INSTR_PT(305) + OR ROM32_INSTR_PT(307) OR ROM32_INSTR_PT(309) + OR ROM32_INSTR_PT(311) OR ROM32_INSTR_PT(318) + OR ROM32_INSTR_PT(322) OR ROM32_INSTR_PT(323) + OR ROM32_INSTR_PT(325) OR ROM32_INSTR_PT(329) + OR ROM32_INSTR_PT(332) OR ROM32_INSTR_PT(335) + OR ROM32_INSTR_PT(337) OR ROM32_INSTR_PT(338) + OR ROM32_INSTR_PT(339) OR ROM32_INSTR_PT(344) + OR ROM32_INSTR_PT(346) OR ROM32_INSTR_PT(350) + OR ROM32_INSTR_PT(356) OR ROM32_INSTR_PT(357) + OR ROM32_INSTR_PT(358) OR ROM32_INSTR_PT(359) + OR ROM32_INSTR_PT(362) OR ROM32_INSTR_PT(363) + OR ROM32_INSTR_PT(365) OR ROM32_INSTR_PT(366) + OR ROM32_INSTR_PT(367) OR ROM32_INSTR_PT(368) + OR ROM32_INSTR_PT(370) OR ROM32_INSTR_PT(373) + OR ROM32_INSTR_PT(374) OR ROM32_INSTR_PT(376) + OR ROM32_INSTR_PT(378) OR ROM32_INSTR_PT(381) + OR ROM32_INSTR_PT(382) OR ROM32_INSTR_PT(386) + OR ROM32_INSTR_PT(387) OR ROM32_INSTR_PT(388) + OR ROM32_INSTR_PT(391) OR ROM32_INSTR_PT(393) + OR ROM32_INSTR_PT(394) OR ROM32_INSTR_PT(395) + OR ROM32_INSTR_PT(398) OR ROM32_INSTR_PT(399) + OR ROM32_INSTR_PT(400) OR ROM32_INSTR_PT(402) + OR ROM32_INSTR_PT(404) OR ROM32_INSTR_PT(405) + OR ROM32_INSTR_PT(409) OR ROM32_INSTR_PT(415) + OR ROM32_INSTR_PT(416) OR ROM32_INSTR_PT(417) + OR ROM32_INSTR_PT(418) OR ROM32_INSTR_PT(419) + OR ROM32_INSTR_PT(422) OR ROM32_INSTR_PT(423) + OR ROM32_INSTR_PT(425) OR ROM32_INSTR_PT(426) + OR ROM32_INSTR_PT(434) OR ROM32_INSTR_PT(435) + OR ROM32_INSTR_PT(436) OR ROM32_INSTR_PT(438) + OR ROM32_INSTR_PT(441) OR ROM32_INSTR_PT(442) + OR ROM32_INSTR_PT(443) OR ROM32_INSTR_PT(446) + OR ROM32_INSTR_PT(451) OR ROM32_INSTR_PT(452) + OR ROM32_INSTR_PT(454) OR ROM32_INSTR_PT(456) + OR ROM32_INSTR_PT(458) OR ROM32_INSTR_PT(461) + OR ROM32_INSTR_PT(463) OR ROM32_INSTR_PT(464) + OR ROM32_INSTR_PT(465) OR ROM32_INSTR_PT(467) + OR ROM32_INSTR_PT(468) OR ROM32_INSTR_PT(469) + OR ROM32_INSTR_PT(471) OR ROM32_INSTR_PT(472) + OR ROM32_INSTR_PT(473) OR ROM32_INSTR_PT(474) + OR ROM32_INSTR_PT(476) OR ROM32_INSTR_PT(480) + OR ROM32_INSTR_PT(486) OR ROM32_INSTR_PT(489) + OR ROM32_INSTR_PT(496) OR ROM32_INSTR_PT(497) + OR ROM32_INSTR_PT(498) OR ROM32_INSTR_PT(503) + OR ROM32_INSTR_PT(505) OR ROM32_INSTR_PT(507) + OR ROM32_INSTR_PT(513) OR ROM32_INSTR_PT(514) + OR ROM32_INSTR_PT(517) OR ROM32_INSTR_PT(527) + OR ROM32_INSTR_PT(532) OR ROM32_INSTR_PT(537) + OR ROM32_INSTR_PT(539) OR ROM32_INSTR_PT(541) + OR ROM32_INSTR_PT(544) OR ROM32_INSTR_PT(547) + OR ROM32_INSTR_PT(549) OR ROM32_INSTR_PT(551) + OR ROM32_INSTR_PT(555) OR ROM32_INSTR_PT(557) + OR ROM32_INSTR_PT(558) OR ROM32_INSTR_PT(561) + OR ROM32_INSTR_PT(563) OR ROM32_INSTR_PT(566) + OR ROM32_INSTR_PT(569) OR ROM32_INSTR_PT(570) + OR ROM32_INSTR_PT(571) OR ROM32_INSTR_PT(574) + OR ROM32_INSTR_PT(577) OR ROM32_INSTR_PT(579) + OR ROM32_INSTR_PT(580) OR ROM32_INSTR_PT(584) + OR ROM32_INSTR_PT(586) OR ROM32_INSTR_PT(587) + OR ROM32_INSTR_PT(589) OR ROM32_INSTR_PT(591) + OR ROM32_INSTR_PT(593) OR ROM32_INSTR_PT(596) + OR ROM32_INSTR_PT(597) OR ROM32_INSTR_PT(598) + OR ROM32_INSTR_PT(599) OR ROM32_INSTR_PT(600) + OR ROM32_INSTR_PT(604) OR ROM32_INSTR_PT(605) + OR ROM32_INSTR_PT(606) OR ROM32_INSTR_PT(607) + OR ROM32_INSTR_PT(608) OR ROM32_INSTR_PT(609) + OR ROM32_INSTR_PT(610) OR ROM32_INSTR_PT(611) + OR ROM32_INSTR_PT(614) OR ROM32_INSTR_PT(620) + OR ROM32_INSTR_PT(624) OR ROM32_INSTR_PT(625) + OR ROM32_INSTR_PT(629) OR ROM32_INSTR_PT(632) + OR ROM32_INSTR_PT(634) OR ROM32_INSTR_PT(638) + OR ROM32_INSTR_PT(640) OR ROM32_INSTR_PT(641) + OR ROM32_INSTR_PT(643) OR ROM32_INSTR_PT(652) + OR ROM32_INSTR_PT(653) OR ROM32_INSTR_PT(659) + OR ROM32_INSTR_PT(660) OR ROM32_INSTR_PT(663) + OR ROM32_INSTR_PT(664) OR ROM32_INSTR_PT(668) + OR ROM32_INSTR_PT(672) OR ROM32_INSTR_PT(680) + OR ROM32_INSTR_PT(683) OR ROM32_INSTR_PT(684) + OR ROM32_INSTR_PT(689) OR ROM32_INSTR_PT(691) + OR ROM32_INSTR_PT(692) OR ROM32_INSTR_PT(697) + OR ROM32_INSTR_PT(698) OR ROM32_INSTR_PT(702) + OR ROM32_INSTR_PT(704) OR ROM32_INSTR_PT(708) + OR ROM32_INSTR_PT(711) OR ROM32_INSTR_PT(713) + OR ROM32_INSTR_PT(718) OR ROM32_INSTR_PT(720) + OR ROM32_INSTR_PT(728) OR ROM32_INSTR_PT(729) + OR ROM32_INSTR_PT(733) OR ROM32_INSTR_PT(751) + OR ROM32_INSTR_PT(752) OR ROM32_INSTR_PT(753) + OR ROM32_INSTR_PT(759) OR ROM32_INSTR_PT(763) + OR ROM32_INSTR_PT(774) OR ROM32_INSTR_PT(787) + OR ROM32_INSTR_PT(790) OR ROM32_INSTR_PT(792) + OR ROM32_INSTR_PT(795) OR ROM32_INSTR_PT(801) + OR ROM32_INSTR_PT(803) OR ROM32_INSTR_PT(805) + OR ROM32_INSTR_PT(807) OR ROM32_INSTR_PT(812) + OR ROM32_INSTR_PT(817) OR ROM32_INSTR_PT(819) + OR ROM32_INSTR_PT(823) OR ROM32_INSTR_PT(829) + OR ROM32_INSTR_PT(831) OR ROM32_INSTR_PT(845) + OR ROM32_INSTR_PT(847) OR ROM32_INSTR_PT(851) + OR ROM32_INSTR_PT(853) OR ROM32_INSTR_PT(854) + OR ROM32_INSTR_PT(857) OR ROM32_INSTR_PT(869) + OR ROM32_INSTR_PT(872) OR ROM32_INSTR_PT(878) + OR ROM32_INSTR_PT(881)); +MQQ1860:TEMPLATE(5) <= + (ROM32_INSTR_PT(3) OR ROM32_INSTR_PT(5) + OR ROM32_INSTR_PT(6) OR ROM32_INSTR_PT(7) + OR ROM32_INSTR_PT(9) OR ROM32_INSTR_PT(10) + OR ROM32_INSTR_PT(12) OR ROM32_INSTR_PT(13) + OR ROM32_INSTR_PT(14) OR ROM32_INSTR_PT(20) + OR ROM32_INSTR_PT(26) OR ROM32_INSTR_PT(33) + OR ROM32_INSTR_PT(37) OR ROM32_INSTR_PT(39) + OR ROM32_INSTR_PT(41) OR ROM32_INSTR_PT(42) + OR ROM32_INSTR_PT(45) OR ROM32_INSTR_PT(49) + OR ROM32_INSTR_PT(51) OR ROM32_INSTR_PT(52) + OR ROM32_INSTR_PT(53) OR ROM32_INSTR_PT(56) + OR ROM32_INSTR_PT(57) OR ROM32_INSTR_PT(59) + OR ROM32_INSTR_PT(63) OR ROM32_INSTR_PT(66) + OR ROM32_INSTR_PT(67) OR ROM32_INSTR_PT(72) + OR ROM32_INSTR_PT(73) OR ROM32_INSTR_PT(83) + OR ROM32_INSTR_PT(84) OR ROM32_INSTR_PT(85) + OR ROM32_INSTR_PT(87) OR ROM32_INSTR_PT(90) + OR ROM32_INSTR_PT(93) OR ROM32_INSTR_PT(96) + OR ROM32_INSTR_PT(100) OR ROM32_INSTR_PT(101) + OR ROM32_INSTR_PT(102) OR ROM32_INSTR_PT(103) + OR ROM32_INSTR_PT(106) OR ROM32_INSTR_PT(109) + OR ROM32_INSTR_PT(110) OR ROM32_INSTR_PT(115) + OR ROM32_INSTR_PT(116) OR ROM32_INSTR_PT(117) + OR ROM32_INSTR_PT(118) OR ROM32_INSTR_PT(119) + OR ROM32_INSTR_PT(124) OR ROM32_INSTR_PT(130) + OR ROM32_INSTR_PT(131) OR ROM32_INSTR_PT(135) + OR ROM32_INSTR_PT(139) OR ROM32_INSTR_PT(141) + OR ROM32_INSTR_PT(142) OR ROM32_INSTR_PT(143) + OR ROM32_INSTR_PT(144) OR ROM32_INSTR_PT(153) + OR ROM32_INSTR_PT(155) OR ROM32_INSTR_PT(158) + OR ROM32_INSTR_PT(159) OR ROM32_INSTR_PT(163) + OR ROM32_INSTR_PT(164) OR ROM32_INSTR_PT(169) + OR ROM32_INSTR_PT(170) OR ROM32_INSTR_PT(176) + OR ROM32_INSTR_PT(179) OR ROM32_INSTR_PT(180) + OR ROM32_INSTR_PT(181) OR ROM32_INSTR_PT(183) + OR ROM32_INSTR_PT(184) OR ROM32_INSTR_PT(187) + OR ROM32_INSTR_PT(192) OR ROM32_INSTR_PT(194) + OR ROM32_INSTR_PT(196) OR ROM32_INSTR_PT(199) + OR ROM32_INSTR_PT(202) OR ROM32_INSTR_PT(203) + OR ROM32_INSTR_PT(204) OR ROM32_INSTR_PT(205) + OR ROM32_INSTR_PT(206) OR ROM32_INSTR_PT(207) + OR ROM32_INSTR_PT(212) OR ROM32_INSTR_PT(216) + OR ROM32_INSTR_PT(220) OR ROM32_INSTR_PT(224) + OR ROM32_INSTR_PT(227) OR ROM32_INSTR_PT(232) + OR ROM32_INSTR_PT(233) OR ROM32_INSTR_PT(235) + OR ROM32_INSTR_PT(238) OR ROM32_INSTR_PT(241) + OR ROM32_INSTR_PT(243) OR ROM32_INSTR_PT(244) + OR ROM32_INSTR_PT(249) OR ROM32_INSTR_PT(252) + OR ROM32_INSTR_PT(254) OR ROM32_INSTR_PT(256) + OR ROM32_INSTR_PT(259) OR ROM32_INSTR_PT(260) + OR ROM32_INSTR_PT(261) OR ROM32_INSTR_PT(264) + OR ROM32_INSTR_PT(266) OR ROM32_INSTR_PT(267) + OR ROM32_INSTR_PT(268) OR ROM32_INSTR_PT(269) + OR ROM32_INSTR_PT(271) OR ROM32_INSTR_PT(274) + OR ROM32_INSTR_PT(276) OR ROM32_INSTR_PT(278) + OR ROM32_INSTR_PT(280) OR ROM32_INSTR_PT(282) + OR ROM32_INSTR_PT(284) OR ROM32_INSTR_PT(288) + OR ROM32_INSTR_PT(290) OR ROM32_INSTR_PT(293) + OR ROM32_INSTR_PT(294) OR ROM32_INSTR_PT(299) + OR ROM32_INSTR_PT(301) OR ROM32_INSTR_PT(303) + OR ROM32_INSTR_PT(306) OR ROM32_INSTR_PT(309) + OR ROM32_INSTR_PT(310) OR ROM32_INSTR_PT(318) + OR ROM32_INSTR_PT(323) OR ROM32_INSTR_PT(335) + OR ROM32_INSTR_PT(344) OR ROM32_INSTR_PT(346) + OR ROM32_INSTR_PT(348) OR ROM32_INSTR_PT(350) + OR ROM32_INSTR_PT(353) OR ROM32_INSTR_PT(356) + OR ROM32_INSTR_PT(361) OR ROM32_INSTR_PT(363) + OR ROM32_INSTR_PT(364) OR ROM32_INSTR_PT(367) + OR ROM32_INSTR_PT(371) OR ROM32_INSTR_PT(373) + OR ROM32_INSTR_PT(374) OR ROM32_INSTR_PT(376) + OR ROM32_INSTR_PT(379) OR ROM32_INSTR_PT(381) + OR ROM32_INSTR_PT(382) OR ROM32_INSTR_PT(383) + OR ROM32_INSTR_PT(386) OR ROM32_INSTR_PT(390) + OR ROM32_INSTR_PT(392) OR ROM32_INSTR_PT(394) + OR ROM32_INSTR_PT(396) OR ROM32_INSTR_PT(400) + OR ROM32_INSTR_PT(402) OR ROM32_INSTR_PT(405) + OR ROM32_INSTR_PT(406) OR ROM32_INSTR_PT(409) + OR ROM32_INSTR_PT(413) OR ROM32_INSTR_PT(415) + OR ROM32_INSTR_PT(417) OR ROM32_INSTR_PT(422) + OR ROM32_INSTR_PT(423) OR ROM32_INSTR_PT(424) + OR ROM32_INSTR_PT(425) OR ROM32_INSTR_PT(426) + OR ROM32_INSTR_PT(428) OR ROM32_INSTR_PT(430) + OR ROM32_INSTR_PT(431) OR ROM32_INSTR_PT(434) + OR ROM32_INSTR_PT(435) OR ROM32_INSTR_PT(436) + OR ROM32_INSTR_PT(438) OR ROM32_INSTR_PT(441) + OR ROM32_INSTR_PT(442) OR ROM32_INSTR_PT(443) + OR ROM32_INSTR_PT(445) OR ROM32_INSTR_PT(449) + OR ROM32_INSTR_PT(451) OR ROM32_INSTR_PT(452) + OR ROM32_INSTR_PT(453) OR ROM32_INSTR_PT(458) + OR ROM32_INSTR_PT(464) OR ROM32_INSTR_PT(469) + OR ROM32_INSTR_PT(472) OR ROM32_INSTR_PT(474) + OR ROM32_INSTR_PT(475) OR ROM32_INSTR_PT(478) + OR ROM32_INSTR_PT(479) OR ROM32_INSTR_PT(481) + OR ROM32_INSTR_PT(482) OR ROM32_INSTR_PT(484) + OR ROM32_INSTR_PT(486) OR ROM32_INSTR_PT(490) + OR ROM32_INSTR_PT(491) OR ROM32_INSTR_PT(494) + OR ROM32_INSTR_PT(495) OR ROM32_INSTR_PT(501) + OR ROM32_INSTR_PT(503) OR ROM32_INSTR_PT(507) + OR ROM32_INSTR_PT(509) OR ROM32_INSTR_PT(511) + OR ROM32_INSTR_PT(514) OR ROM32_INSTR_PT(517) + OR ROM32_INSTR_PT(520) OR ROM32_INSTR_PT(521) + OR ROM32_INSTR_PT(522) OR ROM32_INSTR_PT(524) + OR ROM32_INSTR_PT(530) OR ROM32_INSTR_PT(531) + OR ROM32_INSTR_PT(532) OR ROM32_INSTR_PT(534) + OR ROM32_INSTR_PT(541) OR ROM32_INSTR_PT(544) + OR ROM32_INSTR_PT(550) OR ROM32_INSTR_PT(551) + OR ROM32_INSTR_PT(552) OR ROM32_INSTR_PT(554) + OR ROM32_INSTR_PT(555) OR ROM32_INSTR_PT(557) + OR ROM32_INSTR_PT(562) OR ROM32_INSTR_PT(563) + OR ROM32_INSTR_PT(566) OR ROM32_INSTR_PT(569) + OR ROM32_INSTR_PT(570) OR ROM32_INSTR_PT(575) + OR ROM32_INSTR_PT(579) OR ROM32_INSTR_PT(580) + OR ROM32_INSTR_PT(581) OR ROM32_INSTR_PT(582) + OR ROM32_INSTR_PT(583) OR ROM32_INSTR_PT(584) + OR ROM32_INSTR_PT(588) OR ROM32_INSTR_PT(599) + OR ROM32_INSTR_PT(600) OR ROM32_INSTR_PT(601) + OR ROM32_INSTR_PT(602) OR ROM32_INSTR_PT(605) + OR ROM32_INSTR_PT(609) OR ROM32_INSTR_PT(610) + OR ROM32_INSTR_PT(613) OR ROM32_INSTR_PT(615) + OR ROM32_INSTR_PT(616) OR ROM32_INSTR_PT(617) + OR ROM32_INSTR_PT(620) OR ROM32_INSTR_PT(622) + OR ROM32_INSTR_PT(624) OR ROM32_INSTR_PT(626) + OR ROM32_INSTR_PT(630) OR ROM32_INSTR_PT(634) + OR ROM32_INSTR_PT(638) OR ROM32_INSTR_PT(639) + OR ROM32_INSTR_PT(642) OR ROM32_INSTR_PT(643) + OR ROM32_INSTR_PT(654) OR ROM32_INSTR_PT(660) + OR ROM32_INSTR_PT(663) OR ROM32_INSTR_PT(664) + OR ROM32_INSTR_PT(666) OR ROM32_INSTR_PT(674) + OR ROM32_INSTR_PT(677) OR ROM32_INSTR_PT(684) + OR ROM32_INSTR_PT(692) OR ROM32_INSTR_PT(693) + OR ROM32_INSTR_PT(697) OR ROM32_INSTR_PT(708) + OR ROM32_INSTR_PT(711) OR ROM32_INSTR_PT(713) + OR ROM32_INSTR_PT(718) OR ROM32_INSTR_PT(719) + OR ROM32_INSTR_PT(726) OR ROM32_INSTR_PT(729) + OR ROM32_INSTR_PT(745) OR ROM32_INSTR_PT(755) + OR ROM32_INSTR_PT(762) OR ROM32_INSTR_PT(763) + OR ROM32_INSTR_PT(792) OR ROM32_INSTR_PT(805) + OR ROM32_INSTR_PT(812) OR ROM32_INSTR_PT(818) + OR ROM32_INSTR_PT(819) OR ROM32_INSTR_PT(829) + OR ROM32_INSTR_PT(831) OR ROM32_INSTR_PT(845) + OR ROM32_INSTR_PT(853) OR ROM32_INSTR_PT(854) + OR ROM32_INSTR_PT(855) OR ROM32_INSTR_PT(857) + OR ROM32_INSTR_PT(862) OR ROM32_INSTR_PT(870) + OR ROM32_INSTR_PT(872) OR ROM32_INSTR_PT(878) + ); +MQQ1861:TEMPLATE(6) <= + ('0'); +MQQ1862:TEMPLATE(7) <= + ('0'); +MQQ1863:TEMPLATE(8) <= + ('0'); +MQQ1864:TEMPLATE(9) <= + (ROM32_INSTR_PT(6) OR ROM32_INSTR_PT(8) + OR ROM32_INSTR_PT(10) OR ROM32_INSTR_PT(12) + OR ROM32_INSTR_PT(14) OR ROM32_INSTR_PT(17) + OR ROM32_INSTR_PT(23) OR ROM32_INSTR_PT(28) + OR ROM32_INSTR_PT(35) OR ROM32_INSTR_PT(37) + OR ROM32_INSTR_PT(42) OR ROM32_INSTR_PT(45) + OR ROM32_INSTR_PT(53) OR ROM32_INSTR_PT(55) + OR ROM32_INSTR_PT(56) OR ROM32_INSTR_PT(60) + OR ROM32_INSTR_PT(63) OR ROM32_INSTR_PT(73) + OR ROM32_INSTR_PT(74) OR ROM32_INSTR_PT(85) + OR ROM32_INSTR_PT(87) OR ROM32_INSTR_PT(90) + OR ROM32_INSTR_PT(93) OR ROM32_INSTR_PT(97) + OR ROM32_INSTR_PT(100) OR ROM32_INSTR_PT(102) + OR ROM32_INSTR_PT(103) OR ROM32_INSTR_PT(105) + OR ROM32_INSTR_PT(106) OR ROM32_INSTR_PT(117) + OR ROM32_INSTR_PT(120) OR ROM32_INSTR_PT(124) + OR ROM32_INSTR_PT(130) OR ROM32_INSTR_PT(134) + OR ROM32_INSTR_PT(135) OR ROM32_INSTR_PT(141) + OR ROM32_INSTR_PT(142) OR ROM32_INSTR_PT(148) + OR ROM32_INSTR_PT(154) OR ROM32_INSTR_PT(155) + OR ROM32_INSTR_PT(162) OR ROM32_INSTR_PT(172) + OR ROM32_INSTR_PT(174) OR ROM32_INSTR_PT(175) + OR ROM32_INSTR_PT(176) OR ROM32_INSTR_PT(177) + OR ROM32_INSTR_PT(179) OR ROM32_INSTR_PT(180) + OR ROM32_INSTR_PT(181) OR ROM32_INSTR_PT(184) + OR ROM32_INSTR_PT(187) OR ROM32_INSTR_PT(192) + OR ROM32_INSTR_PT(193) OR ROM32_INSTR_PT(199) + OR ROM32_INSTR_PT(202) OR ROM32_INSTR_PT(209) + OR ROM32_INSTR_PT(214) OR ROM32_INSTR_PT(216) + OR ROM32_INSTR_PT(218) OR ROM32_INSTR_PT(222) + OR ROM32_INSTR_PT(223) OR ROM32_INSTR_PT(226) + OR ROM32_INSTR_PT(227) OR ROM32_INSTR_PT(232) + OR ROM32_INSTR_PT(238) OR ROM32_INSTR_PT(240) + OR ROM32_INSTR_PT(242) OR ROM32_INSTR_PT(244) + OR ROM32_INSTR_PT(249) OR ROM32_INSTR_PT(255) + OR ROM32_INSTR_PT(257) OR ROM32_INSTR_PT(258) + OR ROM32_INSTR_PT(260) OR ROM32_INSTR_PT(269) + OR ROM32_INSTR_PT(272) OR ROM32_INSTR_PT(273) + OR ROM32_INSTR_PT(274) OR ROM32_INSTR_PT(275) + OR ROM32_INSTR_PT(280) OR ROM32_INSTR_PT(282) + OR ROM32_INSTR_PT(283) OR ROM32_INSTR_PT(287) + OR ROM32_INSTR_PT(288) OR ROM32_INSTR_PT(293) + OR ROM32_INSTR_PT(294) OR ROM32_INSTR_PT(297) + OR ROM32_INSTR_PT(299) OR ROM32_INSTR_PT(303) + OR ROM32_INSTR_PT(309) OR ROM32_INSTR_PT(313) + OR ROM32_INSTR_PT(318) OR ROM32_INSTR_PT(319) + OR ROM32_INSTR_PT(321) OR ROM32_INSTR_PT(338) + OR ROM32_INSTR_PT(345) OR ROM32_INSTR_PT(348) + OR ROM32_INSTR_PT(353) OR ROM32_INSTR_PT(357) + OR ROM32_INSTR_PT(359) OR ROM32_INSTR_PT(362) + OR ROM32_INSTR_PT(363) OR ROM32_INSTR_PT(366) + OR ROM32_INSTR_PT(367) OR ROM32_INSTR_PT(374) + OR ROM32_INSTR_PT(377) OR ROM32_INSTR_PT(378) + OR ROM32_INSTR_PT(379) OR ROM32_INSTR_PT(382) + OR ROM32_INSTR_PT(383) OR ROM32_INSTR_PT(386) + OR ROM32_INSTR_PT(387) OR ROM32_INSTR_PT(388) + OR ROM32_INSTR_PT(391) OR ROM32_INSTR_PT(394) + OR ROM32_INSTR_PT(395) OR ROM32_INSTR_PT(399) + OR ROM32_INSTR_PT(400) OR ROM32_INSTR_PT(401) + OR ROM32_INSTR_PT(402) OR ROM32_INSTR_PT(406) + OR ROM32_INSTR_PT(409) OR ROM32_INSTR_PT(412) + OR ROM32_INSTR_PT(415) OR ROM32_INSTR_PT(416) + OR ROM32_INSTR_PT(422) OR ROM32_INSTR_PT(423) + OR ROM32_INSTR_PT(431) OR ROM32_INSTR_PT(433) + OR ROM32_INSTR_PT(434) OR ROM32_INSTR_PT(436) + OR ROM32_INSTR_PT(441) OR ROM32_INSTR_PT(443) + OR ROM32_INSTR_PT(451) OR ROM32_INSTR_PT(453) + OR ROM32_INSTR_PT(464) OR ROM32_INSTR_PT(467) + OR ROM32_INSTR_PT(469) OR ROM32_INSTR_PT(471) + OR ROM32_INSTR_PT(472) OR ROM32_INSTR_PT(475) + OR ROM32_INSTR_PT(479) OR ROM32_INSTR_PT(482) + OR ROM32_INSTR_PT(489) OR ROM32_INSTR_PT(490) + OR ROM32_INSTR_PT(491) OR ROM32_INSTR_PT(494) + OR ROM32_INSTR_PT(497) OR ROM32_INSTR_PT(498) + OR ROM32_INSTR_PT(501) OR ROM32_INSTR_PT(502) + OR ROM32_INSTR_PT(504) OR ROM32_INSTR_PT(506) + OR ROM32_INSTR_PT(514) OR ROM32_INSTR_PT(516) + OR ROM32_INSTR_PT(517) OR ROM32_INSTR_PT(519) + OR ROM32_INSTR_PT(520) OR ROM32_INSTR_PT(532) + OR ROM32_INSTR_PT(534) OR ROM32_INSTR_PT(535) + OR ROM32_INSTR_PT(543) OR ROM32_INSTR_PT(544) + OR ROM32_INSTR_PT(547) OR ROM32_INSTR_PT(550) + OR ROM32_INSTR_PT(552) OR ROM32_INSTR_PT(556) + OR ROM32_INSTR_PT(557) OR ROM32_INSTR_PT(568) + OR ROM32_INSTR_PT(570) OR ROM32_INSTR_PT(571) + OR ROM32_INSTR_PT(574) OR ROM32_INSTR_PT(575) + OR ROM32_INSTR_PT(586) OR ROM32_INSTR_PT(588) + OR ROM32_INSTR_PT(589) OR ROM32_INSTR_PT(590) + OR ROM32_INSTR_PT(600) OR ROM32_INSTR_PT(602) + OR ROM32_INSTR_PT(604) OR ROM32_INSTR_PT(606) + OR ROM32_INSTR_PT(609) OR ROM32_INSTR_PT(611) + OR ROM32_INSTR_PT(612) OR ROM32_INSTR_PT(613) + OR ROM32_INSTR_PT(621) OR ROM32_INSTR_PT(625) + OR ROM32_INSTR_PT(630) OR ROM32_INSTR_PT(639) + OR ROM32_INSTR_PT(640) OR ROM32_INSTR_PT(646) + OR ROM32_INSTR_PT(647) OR ROM32_INSTR_PT(652) + OR ROM32_INSTR_PT(659) OR ROM32_INSTR_PT(663) + OR ROM32_INSTR_PT(666) OR ROM32_INSTR_PT(677) + OR ROM32_INSTR_PT(689) OR ROM32_INSTR_PT(690) + OR ROM32_INSTR_PT(698) OR ROM32_INSTR_PT(700) + OR ROM32_INSTR_PT(733) OR ROM32_INSTR_PT(745) + OR ROM32_INSTR_PT(751) OR ROM32_INSTR_PT(753) + OR ROM32_INSTR_PT(790) OR ROM32_INSTR_PT(807) + OR ROM32_INSTR_PT(823) OR ROM32_INSTR_PT(845) + ); +MQQ1865:TEMPLATE(10) <= + (ROM32_INSTR_PT(3) OR ROM32_INSTR_PT(5) + OR ROM32_INSTR_PT(6) OR ROM32_INSTR_PT(13) + OR ROM32_INSTR_PT(14) OR ROM32_INSTR_PT(16) + OR ROM32_INSTR_PT(18) OR ROM32_INSTR_PT(32) + OR ROM32_INSTR_PT(38) OR ROM32_INSTR_PT(41) + OR ROM32_INSTR_PT(42) OR ROM32_INSTR_PT(45) + OR ROM32_INSTR_PT(51) OR ROM32_INSTR_PT(52) + OR ROM32_INSTR_PT(53) OR ROM32_INSTR_PT(57) + OR ROM32_INSTR_PT(76) OR ROM32_INSTR_PT(77) + OR ROM32_INSTR_PT(85) OR ROM32_INSTR_PT(95) + OR ROM32_INSTR_PT(99) OR ROM32_INSTR_PT(113) + OR ROM32_INSTR_PT(114) OR ROM32_INSTR_PT(117) + OR ROM32_INSTR_PT(118) OR ROM32_INSTR_PT(123) + OR ROM32_INSTR_PT(125) OR ROM32_INSTR_PT(127) + OR ROM32_INSTR_PT(128) OR ROM32_INSTR_PT(130) + OR ROM32_INSTR_PT(138) OR ROM32_INSTR_PT(139) + OR ROM32_INSTR_PT(142) OR ROM32_INSTR_PT(143) + OR ROM32_INSTR_PT(153) OR ROM32_INSTR_PT(169) + OR ROM32_INSTR_PT(171) OR ROM32_INSTR_PT(173) + OR ROM32_INSTR_PT(174) OR ROM32_INSTR_PT(180) + OR ROM32_INSTR_PT(181) OR ROM32_INSTR_PT(183) + OR ROM32_INSTR_PT(189) OR ROM32_INSTR_PT(194) + OR ROM32_INSTR_PT(200) OR ROM32_INSTR_PT(203) + OR ROM32_INSTR_PT(204) OR ROM32_INSTR_PT(214) + OR ROM32_INSTR_PT(219) OR ROM32_INSTR_PT(229) + OR ROM32_INSTR_PT(235) OR ROM32_INSTR_PT(237) + OR ROM32_INSTR_PT(240) OR ROM32_INSTR_PT(241) + OR ROM32_INSTR_PT(250) OR ROM32_INSTR_PT(251) + OR ROM32_INSTR_PT(254) OR ROM32_INSTR_PT(256) + OR ROM32_INSTR_PT(261) OR ROM32_INSTR_PT(267) + OR ROM32_INSTR_PT(270) OR ROM32_INSTR_PT(271) + OR ROM32_INSTR_PT(274) OR ROM32_INSTR_PT(276) + OR ROM32_INSTR_PT(281) OR ROM32_INSTR_PT(289) + OR ROM32_INSTR_PT(328) OR ROM32_INSTR_PT(335) + OR ROM32_INSTR_PT(361) OR ROM32_INSTR_PT(363) + OR ROM32_INSTR_PT(364) OR ROM32_INSTR_PT(365) + OR ROM32_INSTR_PT(370) OR ROM32_INSTR_PT(371) + OR ROM32_INSTR_PT(376) OR ROM32_INSTR_PT(381) + OR ROM32_INSTR_PT(390) OR ROM32_INSTR_PT(395) + OR ROM32_INSTR_PT(398) OR ROM32_INSTR_PT(400) + OR ROM32_INSTR_PT(404) OR ROM32_INSTR_PT(418) + OR ROM32_INSTR_PT(419) OR ROM32_INSTR_PT(421) + OR ROM32_INSTR_PT(436) OR ROM32_INSTR_PT(439) + OR ROM32_INSTR_PT(441) OR ROM32_INSTR_PT(446) + OR ROM32_INSTR_PT(454) OR ROM32_INSTR_PT(468) + OR ROM32_INSTR_PT(473) OR ROM32_INSTR_PT(477) + OR ROM32_INSTR_PT(478) OR ROM32_INSTR_PT(480) + OR ROM32_INSTR_PT(489) OR ROM32_INSTR_PT(503) + OR ROM32_INSTR_PT(504) OR ROM32_INSTR_PT(505) + OR ROM32_INSTR_PT(508) OR ROM32_INSTR_PT(509) + OR ROM32_INSTR_PT(517) OR ROM32_INSTR_PT(524) + OR ROM32_INSTR_PT(527) OR ROM32_INSTR_PT(531) + OR ROM32_INSTR_PT(532) OR ROM32_INSTR_PT(537) + OR ROM32_INSTR_PT(538) OR ROM32_INSTR_PT(546) + OR ROM32_INSTR_PT(551) OR ROM32_INSTR_PT(555) + OR ROM32_INSTR_PT(558) OR ROM32_INSTR_PT(562) + OR ROM32_INSTR_PT(570) OR ROM32_INSTR_PT(578) + OR ROM32_INSTR_PT(582) OR ROM32_INSTR_PT(585) + OR ROM32_INSTR_PT(591) OR ROM32_INSTR_PT(593) + OR ROM32_INSTR_PT(595) OR ROM32_INSTR_PT(597) + OR ROM32_INSTR_PT(598) OR ROM32_INSTR_PT(603) + OR ROM32_INSTR_PT(608) OR ROM32_INSTR_PT(615) + OR ROM32_INSTR_PT(624) OR ROM32_INSTR_PT(626) + OR ROM32_INSTR_PT(629) OR ROM32_INSTR_PT(635) + OR ROM32_INSTR_PT(641) OR ROM32_INSTR_PT(642) + OR ROM32_INSTR_PT(644) OR ROM32_INSTR_PT(654) + OR ROM32_INSTR_PT(680) OR ROM32_INSTR_PT(683) + OR ROM32_INSTR_PT(689) OR ROM32_INSTR_PT(708) + OR ROM32_INSTR_PT(713) OR ROM32_INSTR_PT(718) + OR ROM32_INSTR_PT(720) OR ROM32_INSTR_PT(728) + OR ROM32_INSTR_PT(729) OR ROM32_INSTR_PT(731) + OR ROM32_INSTR_PT(755) OR ROM32_INSTR_PT(763) + OR ROM32_INSTR_PT(819) OR ROM32_INSTR_PT(857) + OR ROM32_INSTR_PT(872)); +MQQ1866:TEMPLATE(11) <= + ('0'); +MQQ1867:TEMPLATE(12) <= + ('0'); +MQQ1868:TEMPLATE(13) <= + ('0'); +MQQ1869:TEMPLATE(14) <= + (ROM32_INSTR_PT(6) OR ROM32_INSTR_PT(10) + OR ROM32_INSTR_PT(12) OR ROM32_INSTR_PT(14) + OR ROM32_INSTR_PT(16) OR ROM32_INSTR_PT(20) + OR ROM32_INSTR_PT(23) OR ROM32_INSTR_PT(26) + OR ROM32_INSTR_PT(32) OR ROM32_INSTR_PT(34) + OR ROM32_INSTR_PT(35) OR ROM32_INSTR_PT(37) + OR ROM32_INSTR_PT(42) OR ROM32_INSTR_PT(52) + OR ROM32_INSTR_PT(53) OR ROM32_INSTR_PT(55) + OR ROM32_INSTR_PT(56) OR ROM32_INSTR_PT(63) + OR ROM32_INSTR_PT(67) OR ROM32_INSTR_PT(73) + OR ROM32_INSTR_PT(77) OR ROM32_INSTR_PT(79) + OR ROM32_INSTR_PT(85) OR ROM32_INSTR_PT(87) + OR ROM32_INSTR_PT(90) OR ROM32_INSTR_PT(92) + OR ROM32_INSTR_PT(93) OR ROM32_INSTR_PT(97) + OR ROM32_INSTR_PT(99) OR ROM32_INSTR_PT(103) + OR ROM32_INSTR_PT(105) OR ROM32_INSTR_PT(111) + OR ROM32_INSTR_PT(114) OR ROM32_INSTR_PT(115) + OR ROM32_INSTR_PT(118) OR ROM32_INSTR_PT(119) + OR ROM32_INSTR_PT(125) OR ROM32_INSTR_PT(127) + OR ROM32_INSTR_PT(130) OR ROM32_INSTR_PT(138) + OR ROM32_INSTR_PT(143) OR ROM32_INSTR_PT(155) + OR ROM32_INSTR_PT(169) OR ROM32_INSTR_PT(171) + OR ROM32_INSTR_PT(172) OR ROM32_INSTR_PT(174) + OR ROM32_INSTR_PT(179) OR ROM32_INSTR_PT(181) + OR ROM32_INSTR_PT(184) OR ROM32_INSTR_PT(187) + OR ROM32_INSTR_PT(196) OR ROM32_INSTR_PT(200) + OR ROM32_INSTR_PT(202) OR ROM32_INSTR_PT(209) + OR ROM32_INSTR_PT(214) OR ROM32_INSTR_PT(216) + OR ROM32_INSTR_PT(218) OR ROM32_INSTR_PT(219) + OR ROM32_INSTR_PT(224) OR ROM32_INSTR_PT(227) + OR ROM32_INSTR_PT(229) OR ROM32_INSTR_PT(232) + OR ROM32_INSTR_PT(238) OR ROM32_INSTR_PT(240) + OR ROM32_INSTR_PT(250) OR ROM32_INSTR_PT(257) + OR ROM32_INSTR_PT(259) OR ROM32_INSTR_PT(261) + OR ROM32_INSTR_PT(264) OR ROM32_INSTR_PT(267) + OR ROM32_INSTR_PT(269) OR ROM32_INSTR_PT(270) + OR ROM32_INSTR_PT(271) OR ROM32_INSTR_PT(272) + OR ROM32_INSTR_PT(273) OR ROM32_INSTR_PT(274) + OR ROM32_INSTR_PT(275) OR ROM32_INSTR_PT(278) + OR ROM32_INSTR_PT(280) OR ROM32_INSTR_PT(283) + OR ROM32_INSTR_PT(284) OR ROM32_INSTR_PT(288) + OR ROM32_INSTR_PT(290) OR ROM32_INSTR_PT(295) + OR ROM32_INSTR_PT(299) OR ROM32_INSTR_PT(303) + OR ROM32_INSTR_PT(309) OR ROM32_INSTR_PT(313) + OR ROM32_INSTR_PT(321) OR ROM32_INSTR_PT(328) + OR ROM32_INSTR_PT(345) OR ROM32_INSTR_PT(348) + OR ROM32_INSTR_PT(361) OR ROM32_INSTR_PT(362) + OR ROM32_INSTR_PT(363) OR ROM32_INSTR_PT(366) + OR ROM32_INSTR_PT(367) OR ROM32_INSTR_PT(368) + OR ROM32_INSTR_PT(370) OR ROM32_INSTR_PT(371) + OR ROM32_INSTR_PT(379) OR ROM32_INSTR_PT(383) + OR ROM32_INSTR_PT(387) OR ROM32_INSTR_PT(390) + OR ROM32_INSTR_PT(392) OR ROM32_INSTR_PT(394) + OR ROM32_INSTR_PT(395) OR ROM32_INSTR_PT(396) + OR ROM32_INSTR_PT(400) OR ROM32_INSTR_PT(401) + OR ROM32_INSTR_PT(402) OR ROM32_INSTR_PT(406) + OR ROM32_INSTR_PT(411) OR ROM32_INSTR_PT(412) + OR ROM32_INSTR_PT(418) OR ROM32_INSTR_PT(421) + OR ROM32_INSTR_PT(423) OR ROM32_INSTR_PT(424) + OR ROM32_INSTR_PT(433) OR ROM32_INSTR_PT(436) + OR ROM32_INSTR_PT(441) OR ROM32_INSTR_PT(445) + OR ROM32_INSTR_PT(449) OR ROM32_INSTR_PT(453) + OR ROM32_INSTR_PT(456) OR ROM32_INSTR_PT(464) + OR ROM32_INSTR_PT(469) OR ROM32_INSTR_PT(472) + OR ROM32_INSTR_PT(475) OR ROM32_INSTR_PT(476) + OR ROM32_INSTR_PT(479) OR ROM32_INSTR_PT(480) + OR ROM32_INSTR_PT(481) OR ROM32_INSTR_PT(482) + OR ROM32_INSTR_PT(484) OR ROM32_INSTR_PT(490) + OR ROM32_INSTR_PT(494) OR ROM32_INSTR_PT(497) + OR ROM32_INSTR_PT(502) OR ROM32_INSTR_PT(508) + OR ROM32_INSTR_PT(514) OR ROM32_INSTR_PT(517) + OR ROM32_INSTR_PT(519) OR ROM32_INSTR_PT(520) + OR ROM32_INSTR_PT(521) OR ROM32_INSTR_PT(522) + OR ROM32_INSTR_PT(524) OR ROM32_INSTR_PT(532) + OR ROM32_INSTR_PT(534) OR ROM32_INSTR_PT(535) + OR ROM32_INSTR_PT(536) OR ROM32_INSTR_PT(541) + OR ROM32_INSTR_PT(543) OR ROM32_INSTR_PT(546) + OR ROM32_INSTR_PT(547) OR ROM32_INSTR_PT(550) + OR ROM32_INSTR_PT(551) OR ROM32_INSTR_PT(552) + OR ROM32_INSTR_PT(554) OR ROM32_INSTR_PT(556) + OR ROM32_INSTR_PT(558) OR ROM32_INSTR_PT(565) + OR ROM32_INSTR_PT(568) OR ROM32_INSTR_PT(570) + OR ROM32_INSTR_PT(574) OR ROM32_INSTR_PT(575) + OR ROM32_INSTR_PT(578) OR ROM32_INSTR_PT(582) + OR ROM32_INSTR_PT(585) OR ROM32_INSTR_PT(588) + OR ROM32_INSTR_PT(590) OR ROM32_INSTR_PT(595) + OR ROM32_INSTR_PT(602) OR ROM32_INSTR_PT(603) + OR ROM32_INSTR_PT(606) OR ROM32_INSTR_PT(607) + OR ROM32_INSTR_PT(611) OR ROM32_INSTR_PT(612) + OR ROM32_INSTR_PT(617) OR ROM32_INSTR_PT(621) + OR ROM32_INSTR_PT(625) OR ROM32_INSTR_PT(630) + OR ROM32_INSTR_PT(633) OR ROM32_INSTR_PT(635) + OR ROM32_INSTR_PT(639) OR ROM32_INSTR_PT(642) + OR ROM32_INSTR_PT(644) OR ROM32_INSTR_PT(647) + OR ROM32_INSTR_PT(666) OR ROM32_INSTR_PT(677) + OR ROM32_INSTR_PT(680) OR ROM32_INSTR_PT(689) + OR ROM32_INSTR_PT(690) OR ROM32_INSTR_PT(698) + OR ROM32_INSTR_PT(718) OR ROM32_INSTR_PT(731) + OR ROM32_INSTR_PT(736) OR ROM32_INSTR_PT(745) + OR ROM32_INSTR_PT(755) OR ROM32_INSTR_PT(762) + OR ROM32_INSTR_PT(770) OR ROM32_INSTR_PT(818) + OR ROM32_INSTR_PT(855) OR ROM32_INSTR_PT(862) + OR ROM32_INSTR_PT(870)); +MQQ1870:TEMPLATE(15) <= + (ROM32_INSTR_PT(8) OR ROM32_INSTR_PT(14) + OR ROM32_INSTR_PT(17) OR ROM32_INSTR_PT(26) + OR ROM32_INSTR_PT(34) OR ROM32_INSTR_PT(53) + OR ROM32_INSTR_PT(57) OR ROM32_INSTR_PT(74) + OR ROM32_INSTR_PT(79) OR ROM32_INSTR_PT(84) + OR ROM32_INSTR_PT(92) OR ROM32_INSTR_PT(102) + OR ROM32_INSTR_PT(111) OR ROM32_INSTR_PT(115) + OR ROM32_INSTR_PT(117) OR ROM32_INSTR_PT(122) + OR ROM32_INSTR_PT(123) OR ROM32_INSTR_PT(134) + OR ROM32_INSTR_PT(141) OR ROM32_INSTR_PT(148) + OR ROM32_INSTR_PT(159) OR ROM32_INSTR_PT(163) + OR ROM32_INSTR_PT(170) OR ROM32_INSTR_PT(173) + OR ROM32_INSTR_PT(174) OR ROM32_INSTR_PT(203) + OR ROM32_INSTR_PT(212) OR ROM32_INSTR_PT(214) + OR ROM32_INSTR_PT(215) OR ROM32_INSTR_PT(220) + OR ROM32_INSTR_PT(223) OR ROM32_INSTR_PT(235) + OR ROM32_INSTR_PT(240) OR ROM32_INSTR_PT(259) + OR ROM32_INSTR_PT(264) OR ROM32_INSTR_PT(271) + OR ROM32_INSTR_PT(276) OR ROM32_INSTR_PT(289) + OR ROM32_INSTR_PT(290) OR ROM32_INSTR_PT(294) + OR ROM32_INSTR_PT(297) OR ROM32_INSTR_PT(301) + OR ROM32_INSTR_PT(309) OR ROM32_INSTR_PT(346) + OR ROM32_INSTR_PT(350) OR ROM32_INSTR_PT(356) + OR ROM32_INSTR_PT(360) OR ROM32_INSTR_PT(368) + OR ROM32_INSTR_PT(376) OR ROM32_INSTR_PT(382) + OR ROM32_INSTR_PT(386) OR ROM32_INSTR_PT(392) + OR ROM32_INSTR_PT(395) OR ROM32_INSTR_PT(404) + OR ROM32_INSTR_PT(413) OR ROM32_INSTR_PT(422) + OR ROM32_INSTR_PT(430) OR ROM32_INSTR_PT(431) + OR ROM32_INSTR_PT(436) OR ROM32_INSTR_PT(438) + OR ROM32_INSTR_PT(439) OR ROM32_INSTR_PT(442) + OR ROM32_INSTR_PT(454) OR ROM32_INSTR_PT(459) + OR ROM32_INSTR_PT(471) OR ROM32_INSTR_PT(474) + OR ROM32_INSTR_PT(476) OR ROM32_INSTR_PT(477) + OR ROM32_INSTR_PT(503) OR ROM32_INSTR_PT(505) + OR ROM32_INSTR_PT(506) OR ROM32_INSTR_PT(517) + OR ROM32_INSTR_PT(522) OR ROM32_INSTR_PT(532) + OR ROM32_INSTR_PT(536) OR ROM32_INSTR_PT(538) + OR ROM32_INSTR_PT(554) OR ROM32_INSTR_PT(563) + OR ROM32_INSTR_PT(580) OR ROM32_INSTR_PT(581) + OR ROM32_INSTR_PT(593) OR ROM32_INSTR_PT(598) + OR ROM32_INSTR_PT(599) OR ROM32_INSTR_PT(607) + OR ROM32_INSTR_PT(608) OR ROM32_INSTR_PT(620) + OR ROM32_INSTR_PT(659) OR ROM32_INSTR_PT(664) + OR ROM32_INSTR_PT(689) OR ROM32_INSTR_PT(692) + OR ROM32_INSTR_PT(711) OR ROM32_INSTR_PT(726) + OR ROM32_INSTR_PT(829) OR ROM32_INSTR_PT(831) + OR ROM32_INSTR_PT(845) OR ROM32_INSTR_PT(853) + ); +MQQ1871:TEMPLATE(16) <= + (ROM32_INSTR_PT(4) OR ROM32_INSTR_PT(9) + OR ROM32_INSTR_PT(16) OR ROM32_INSTR_PT(18) + OR ROM32_INSTR_PT(20) OR ROM32_INSTR_PT(26) + OR ROM32_INSTR_PT(32) OR ROM32_INSTR_PT(34) + OR ROM32_INSTR_PT(38) OR ROM32_INSTR_PT(49) + OR ROM32_INSTR_PT(55) OR ROM32_INSTR_PT(67) + OR ROM32_INSTR_PT(77) OR ROM32_INSTR_PT(79) + OR ROM32_INSTR_PT(84) OR ROM32_INSTR_PT(95) + OR ROM32_INSTR_PT(99) OR ROM32_INSTR_PT(105) + OR ROM32_INSTR_PT(111) OR ROM32_INSTR_PT(114) + OR ROM32_INSTR_PT(115) OR ROM32_INSTR_PT(118) + OR ROM32_INSTR_PT(119) OR ROM32_INSTR_PT(122) + OR ROM32_INSTR_PT(127) OR ROM32_INSTR_PT(171) + OR ROM32_INSTR_PT(186) OR ROM32_INSTR_PT(189) + OR ROM32_INSTR_PT(200) OR ROM32_INSTR_PT(209) + OR ROM32_INSTR_PT(215) OR ROM32_INSTR_PT(219) + OR ROM32_INSTR_PT(220) OR ROM32_INSTR_PT(224) + OR ROM32_INSTR_PT(227) OR ROM32_INSTR_PT(250) + OR ROM32_INSTR_PT(251) OR ROM32_INSTR_PT(259) + OR ROM32_INSTR_PT(261) OR ROM32_INSTR_PT(262) + OR ROM32_INSTR_PT(264) OR ROM32_INSTR_PT(267) + OR ROM32_INSTR_PT(272) OR ROM32_INSTR_PT(273) + OR ROM32_INSTR_PT(278) OR ROM32_INSTR_PT(281) + OR ROM32_INSTR_PT(283) OR ROM32_INSTR_PT(301) + OR ROM32_INSTR_PT(313) OR ROM32_INSTR_PT(321) + OR ROM32_INSTR_PT(328) OR ROM32_INSTR_PT(345) + OR ROM32_INSTR_PT(360) OR ROM32_INSTR_PT(366) + OR ROM32_INSTR_PT(368) OR ROM32_INSTR_PT(371) + OR ROM32_INSTR_PT(390) OR ROM32_INSTR_PT(392) + OR ROM32_INSTR_PT(396) OR ROM32_INSTR_PT(398) + OR ROM32_INSTR_PT(401) OR ROM32_INSTR_PT(412) + OR ROM32_INSTR_PT(424) OR ROM32_INSTR_PT(433) + OR ROM32_INSTR_PT(446) OR ROM32_INSTR_PT(468) + OR ROM32_INSTR_PT(476) OR ROM32_INSTR_PT(478) + OR ROM32_INSTR_PT(502) OR ROM32_INSTR_PT(519) + OR ROM32_INSTR_PT(521) OR ROM32_INSTR_PT(522) + OR ROM32_INSTR_PT(524) OR ROM32_INSTR_PT(537) + OR ROM32_INSTR_PT(539) OR ROM32_INSTR_PT(554) + OR ROM32_INSTR_PT(556) OR ROM32_INSTR_PT(562) + OR ROM32_INSTR_PT(568) OR ROM32_INSTR_PT(581) + OR ROM32_INSTR_PT(583) OR ROM32_INSTR_PT(590) + OR ROM32_INSTR_PT(591) OR ROM32_INSTR_PT(595) + OR ROM32_INSTR_PT(602) OR ROM32_INSTR_PT(607) + OR ROM32_INSTR_PT(612) OR ROM32_INSTR_PT(614) + OR ROM32_INSTR_PT(626) OR ROM32_INSTR_PT(642) + OR ROM32_INSTR_PT(644) OR ROM32_INSTR_PT(736) + OR ROM32_INSTR_PT(762) OR ROM32_INSTR_PT(770) + OR ROM32_INSTR_PT(870)); +MQQ1872:TEMPLATE(17) <= + (ROM32_INSTR_PT(4) OR ROM32_INSTR_PT(16) + OR ROM32_INSTR_PT(18) OR ROM32_INSTR_PT(20) + OR ROM32_INSTR_PT(26) OR ROM32_INSTR_PT(32) + OR ROM32_INSTR_PT(34) OR ROM32_INSTR_PT(37) + OR ROM32_INSTR_PT(38) OR ROM32_INSTR_PT(43) + OR ROM32_INSTR_PT(49) OR ROM32_INSTR_PT(55) + OR ROM32_INSTR_PT(63) OR ROM32_INSTR_PT(73) + OR ROM32_INSTR_PT(79) OR ROM32_INSTR_PT(80) + OR ROM32_INSTR_PT(87) OR ROM32_INSTR_PT(90) + OR ROM32_INSTR_PT(95) OR ROM32_INSTR_PT(99) + OR ROM32_INSTR_PT(103) OR ROM32_INSTR_PT(105) + OR ROM32_INSTR_PT(112) OR ROM32_INSTR_PT(119) + OR ROM32_INSTR_PT(122) OR ROM32_INSTR_PT(127) + OR ROM32_INSTR_PT(173) OR ROM32_INSTR_PT(184) + OR ROM32_INSTR_PT(186) OR ROM32_INSTR_PT(187) + OR ROM32_INSTR_PT(189) OR ROM32_INSTR_PT(200) + OR ROM32_INSTR_PT(209) OR ROM32_INSTR_PT(216) + OR ROM32_INSTR_PT(224) OR ROM32_INSTR_PT(227) + OR ROM32_INSTR_PT(232) OR ROM32_INSTR_PT(235) + OR ROM32_INSTR_PT(238) OR ROM32_INSTR_PT(250) + OR ROM32_INSTR_PT(251) OR ROM32_INSTR_PT(259) + OR ROM32_INSTR_PT(262) OR ROM32_INSTR_PT(264) + OR ROM32_INSTR_PT(269) OR ROM32_INSTR_PT(270) + OR ROM32_INSTR_PT(272) OR ROM32_INSTR_PT(275) + OR ROM32_INSTR_PT(278) OR ROM32_INSTR_PT(280) + OR ROM32_INSTR_PT(281) OR ROM32_INSTR_PT(283) + OR ROM32_INSTR_PT(284) OR ROM32_INSTR_PT(288) + OR ROM32_INSTR_PT(299) OR ROM32_INSTR_PT(301) + OR ROM32_INSTR_PT(303) OR ROM32_INSTR_PT(321) + OR ROM32_INSTR_PT(326) OR ROM32_INSTR_PT(328) + OR ROM32_INSTR_PT(340) OR ROM32_INSTR_PT(345) + OR ROM32_INSTR_PT(348) OR ROM32_INSTR_PT(361) + OR ROM32_INSTR_PT(366) OR ROM32_INSTR_PT(378) + OR ROM32_INSTR_PT(379) OR ROM32_INSTR_PT(383) + OR ROM32_INSTR_PT(392) OR ROM32_INSTR_PT(396) + OR ROM32_INSTR_PT(398) OR ROM32_INSTR_PT(404) + OR ROM32_INSTR_PT(406) OR ROM32_INSTR_PT(416) + OR ROM32_INSTR_PT(418) OR ROM32_INSTR_PT(419) + OR ROM32_INSTR_PT(421) OR ROM32_INSTR_PT(424) + OR ROM32_INSTR_PT(446) OR ROM32_INSTR_PT(468) + OR ROM32_INSTR_PT(475) OR ROM32_INSTR_PT(476) + OR ROM32_INSTR_PT(477) OR ROM32_INSTR_PT(478) + OR ROM32_INSTR_PT(479) OR ROM32_INSTR_PT(480) + OR ROM32_INSTR_PT(481) OR ROM32_INSTR_PT(482) + OR ROM32_INSTR_PT(490) OR ROM32_INSTR_PT(494) + OR ROM32_INSTR_PT(497) OR ROM32_INSTR_PT(505) + OR ROM32_INSTR_PT(508) OR ROM32_INSTR_PT(520) + OR ROM32_INSTR_PT(521) OR ROM32_INSTR_PT(522) + OR ROM32_INSTR_PT(534) OR ROM32_INSTR_PT(535) + OR ROM32_INSTR_PT(537) OR ROM32_INSTR_PT(538) + OR ROM32_INSTR_PT(546) OR ROM32_INSTR_PT(547) + OR ROM32_INSTR_PT(550) OR ROM32_INSTR_PT(552) + OR ROM32_INSTR_PT(554) OR ROM32_INSTR_PT(562) + OR ROM32_INSTR_PT(574) OR ROM32_INSTR_PT(578) + OR ROM32_INSTR_PT(582) OR ROM32_INSTR_PT(583) + OR ROM32_INSTR_PT(585) OR ROM32_INSTR_PT(591) + OR ROM32_INSTR_PT(593) OR ROM32_INSTR_PT(598) + OR ROM32_INSTR_PT(602) OR ROM32_INSTR_PT(606) + OR ROM32_INSTR_PT(607) OR ROM32_INSTR_PT(608) + OR ROM32_INSTR_PT(630) OR ROM32_INSTR_PT(635) + OR ROM32_INSTR_PT(639) OR ROM32_INSTR_PT(642) + OR ROM32_INSTR_PT(644) OR ROM32_INSTR_PT(647) + OR ROM32_INSTR_PT(666) OR ROM32_INSTR_PT(677) + OR ROM32_INSTR_PT(680) OR ROM32_INSTR_PT(698) + OR ROM32_INSTR_PT(870)); +MQQ1873:TEMPLATE(18) <= + (ROM32_INSTR_PT(4) OR ROM32_INSTR_PT(18) + OR ROM32_INSTR_PT(20) OR ROM32_INSTR_PT(26) + OR ROM32_INSTR_PT(34) OR ROM32_INSTR_PT(38) + OR ROM32_INSTR_PT(49) OR ROM32_INSTR_PT(79) + OR ROM32_INSTR_PT(95) OR ROM32_INSTR_PT(97) + OR ROM32_INSTR_PT(111) OR ROM32_INSTR_PT(119) + OR ROM32_INSTR_PT(172) OR ROM32_INSTR_PT(224) + OR ROM32_INSTR_PT(251) OR ROM32_INSTR_PT(259) + OR ROM32_INSTR_PT(264) OR ROM32_INSTR_PT(278) + OR ROM32_INSTR_PT(281) OR ROM32_INSTR_PT(289) + OR ROM32_INSTR_PT(396) OR ROM32_INSTR_PT(398) + OR ROM32_INSTR_PT(424) OR ROM32_INSTR_PT(468) + OR ROM32_INSTR_PT(476) OR ROM32_INSTR_PT(521) + OR ROM32_INSTR_PT(522) OR ROM32_INSTR_PT(537) + OR ROM32_INSTR_PT(543) OR ROM32_INSTR_PT(554) + OR ROM32_INSTR_PT(562) OR ROM32_INSTR_PT(583) + OR ROM32_INSTR_PT(591) OR ROM32_INSTR_PT(642) + OR ROM32_INSTR_PT(720) OR ROM32_INSTR_PT(807) + OR ROM32_INSTR_PT(823)); +MQQ1874:TEMPLATE(19) <= + (ROM32_INSTR_PT(4) OR ROM32_INSTR_PT(14) + OR ROM32_INSTR_PT(18) OR ROM32_INSTR_PT(20) + OR ROM32_INSTR_PT(23) OR ROM32_INSTR_PT(26) + OR ROM32_INSTR_PT(34) OR ROM32_INSTR_PT(38) + OR ROM32_INSTR_PT(39) OR ROM32_INSTR_PT(42) + OR ROM32_INSTR_PT(45) OR ROM32_INSTR_PT(49) + OR ROM32_INSTR_PT(53) OR ROM32_INSTR_PT(57) + OR ROM32_INSTR_PT(79) OR ROM32_INSTR_PT(85) + OR ROM32_INSTR_PT(95) OR ROM32_INSTR_PT(97) + OR ROM32_INSTR_PT(101) OR ROM32_INSTR_PT(102) + OR ROM32_INSTR_PT(110) OR ROM32_INSTR_PT(119) + OR ROM32_INSTR_PT(141) OR ROM32_INSTR_PT(143) + OR ROM32_INSTR_PT(144) OR ROM32_INSTR_PT(158) + OR ROM32_INSTR_PT(178) OR ROM32_INSTR_PT(187) + OR ROM32_INSTR_PT(203) OR ROM32_INSTR_PT(205) + OR ROM32_INSTR_PT(206) OR ROM32_INSTR_PT(207) + OR ROM32_INSTR_PT(220) OR ROM32_INSTR_PT(224) + OR ROM32_INSTR_PT(232) OR ROM32_INSTR_PT(235) + OR ROM32_INSTR_PT(243) OR ROM32_INSTR_PT(251) + OR ROM32_INSTR_PT(252) OR ROM32_INSTR_PT(258) + OR ROM32_INSTR_PT(268) OR ROM32_INSTR_PT(271) + OR ROM32_INSTR_PT(278) OR ROM32_INSTR_PT(281) + OR ROM32_INSTR_PT(289) OR ROM32_INSTR_PT(294) + OR ROM32_INSTR_PT(306) OR ROM32_INSTR_PT(323) + OR ROM32_INSTR_PT(344) OR ROM32_INSTR_PT(376) + OR ROM32_INSTR_PT(378) OR ROM32_INSTR_PT(382) + OR ROM32_INSTR_PT(385) OR ROM32_INSTR_PT(386) + OR ROM32_INSTR_PT(387) OR ROM32_INSTR_PT(396) + OR ROM32_INSTR_PT(398) OR ROM32_INSTR_PT(405) + OR ROM32_INSTR_PT(416) OR ROM32_INSTR_PT(417) + OR ROM32_INSTR_PT(419) OR ROM32_INSTR_PT(422) + OR ROM32_INSTR_PT(424) OR ROM32_INSTR_PT(426) + OR ROM32_INSTR_PT(435) OR ROM32_INSTR_PT(436) + OR ROM32_INSTR_PT(452) OR ROM32_INSTR_PT(458) + OR ROM32_INSTR_PT(468) OR ROM32_INSTR_PT(476) + OR ROM32_INSTR_PT(486) OR ROM32_INSTR_PT(503) + OR ROM32_INSTR_PT(507) OR ROM32_INSTR_PT(517) + OR ROM32_INSTR_PT(521) OR ROM32_INSTR_PT(522) + OR ROM32_INSTR_PT(530) OR ROM32_INSTR_PT(532) + OR ROM32_INSTR_PT(537) OR ROM32_INSTR_PT(541) + OR ROM32_INSTR_PT(551) OR ROM32_INSTR_PT(554) + OR ROM32_INSTR_PT(569) OR ROM32_INSTR_PT(579) + OR ROM32_INSTR_PT(581) OR ROM32_INSTR_PT(583) + OR ROM32_INSTR_PT(591) OR ROM32_INSTR_PT(605) + OR ROM32_INSTR_PT(610) OR ROM32_INSTR_PT(615) + OR ROM32_INSTR_PT(616) OR ROM32_INSTR_PT(642) + OR ROM32_INSTR_PT(643) OR ROM32_INSTR_PT(674) + OR ROM32_INSTR_PT(684) OR ROM32_INSTR_PT(720) + OR ROM32_INSTR_PT(729) OR ROM32_INSTR_PT(763) + OR ROM32_INSTR_PT(807) OR ROM32_INSTR_PT(812) + OR ROM32_INSTR_PT(818) OR ROM32_INSTR_PT(819) + OR ROM32_INSTR_PT(823) OR ROM32_INSTR_PT(878) + ); +MQQ1875:TEMPLATE(20) <= + (ROM32_INSTR_PT(4) OR ROM32_INSTR_PT(12) + OR ROM32_INSTR_PT(20) OR ROM32_INSTR_PT(33) + OR ROM32_INSTR_PT(35) OR ROM32_INSTR_PT(38) + OR ROM32_INSTR_PT(42) OR ROM32_INSTR_PT(45) + OR ROM32_INSTR_PT(49) OR ROM32_INSTR_PT(56) + OR ROM32_INSTR_PT(95) OR ROM32_INSTR_PT(102) + OR ROM32_INSTR_PT(119) OR ROM32_INSTR_PT(141) + OR ROM32_INSTR_PT(155) OR ROM32_INSTR_PT(163) + OR ROM32_INSTR_PT(196) OR ROM32_INSTR_PT(205) + OR ROM32_INSTR_PT(218) OR ROM32_INSTR_PT(224) + OR ROM32_INSTR_PT(251) OR ROM32_INSTR_PT(257) + OR ROM32_INSTR_PT(258) OR ROM32_INSTR_PT(278) + OR ROM32_INSTR_PT(281) OR ROM32_INSTR_PT(289) + OR ROM32_INSTR_PT(294) OR ROM32_INSTR_PT(306) + OR ROM32_INSTR_PT(323) OR ROM32_INSTR_PT(350) + OR ROM32_INSTR_PT(362) OR ROM32_INSTR_PT(367) + OR ROM32_INSTR_PT(382) OR ROM32_INSTR_PT(386) + OR ROM32_INSTR_PT(387) OR ROM32_INSTR_PT(394) + OR ROM32_INSTR_PT(396) OR ROM32_INSTR_PT(398) + OR ROM32_INSTR_PT(402) OR ROM32_INSTR_PT(422) + OR ROM32_INSTR_PT(423) OR ROM32_INSTR_PT(424) + OR ROM32_INSTR_PT(431) OR ROM32_INSTR_PT(435) + OR ROM32_INSTR_PT(452) OR ROM32_INSTR_PT(454) + OR ROM32_INSTR_PT(456) OR ROM32_INSTR_PT(464) + OR ROM32_INSTR_PT(469) OR ROM32_INSTR_PT(472) + OR ROM32_INSTR_PT(476) OR ROM32_INSTR_PT(484) + OR ROM32_INSTR_PT(504) OR ROM32_INSTR_PT(514) + OR ROM32_INSTR_PT(516) OR ROM32_INSTR_PT(521) + OR ROM32_INSTR_PT(522) OR ROM32_INSTR_PT(537) + OR ROM32_INSTR_PT(541) OR ROM32_INSTR_PT(543) + OR ROM32_INSTR_PT(554) OR ROM32_INSTR_PT(563) + OR ROM32_INSTR_PT(577) OR ROM32_INSTR_PT(583) + OR ROM32_INSTR_PT(584) OR ROM32_INSTR_PT(591) + OR ROM32_INSTR_PT(611) OR ROM32_INSTR_PT(615) + OR ROM32_INSTR_PT(625) OR ROM32_INSTR_PT(634) + OR ROM32_INSTR_PT(638) OR ROM32_INSTR_PT(642) + OR ROM32_INSTR_PT(684) OR ROM32_INSTR_PT(690) + OR ROM32_INSTR_PT(718) OR ROM32_INSTR_PT(728) + OR ROM32_INSTR_PT(751) OR ROM32_INSTR_PT(753) + OR ROM32_INSTR_PT(763) OR ROM32_INSTR_PT(805) + OR ROM32_INSTR_PT(818)); +MQQ1876:TEMPLATE(21) <= + (ROM32_INSTR_PT(4) OR ROM32_INSTR_PT(5) + OR ROM32_INSTR_PT(8) OR ROM32_INSTR_PT(9) + OR ROM32_INSTR_PT(10) OR ROM32_INSTR_PT(17) + OR ROM32_INSTR_PT(20) OR ROM32_INSTR_PT(23) + OR ROM32_INSTR_PT(35) OR ROM32_INSTR_PT(38) + OR ROM32_INSTR_PT(43) OR ROM32_INSTR_PT(60) + OR ROM32_INSTR_PT(73) OR ROM32_INSTR_PT(74) + OR ROM32_INSTR_PT(78) OR ROM32_INSTR_PT(80) + OR ROM32_INSTR_PT(84) OR ROM32_INSTR_PT(87) + OR ROM32_INSTR_PT(93) OR ROM32_INSTR_PT(95) + OR ROM32_INSTR_PT(97) OR ROM32_INSTR_PT(115) + OR ROM32_INSTR_PT(118) OR ROM32_INSTR_PT(119) + OR ROM32_INSTR_PT(134) OR ROM32_INSTR_PT(148) + OR ROM32_INSTR_PT(154) OR ROM32_INSTR_PT(172) + OR ROM32_INSTR_PT(178) OR ROM32_INSTR_PT(179) + OR ROM32_INSTR_PT(186) OR ROM32_INSTR_PT(187) + OR ROM32_INSTR_PT(194) OR ROM32_INSTR_PT(202) + OR ROM32_INSTR_PT(206) OR ROM32_INSTR_PT(215) + OR ROM32_INSTR_PT(218) OR ROM32_INSTR_PT(223) + OR ROM32_INSTR_PT(224) OR ROM32_INSTR_PT(229) + OR ROM32_INSTR_PT(232) OR ROM32_INSTR_PT(235) + OR ROM32_INSTR_PT(244) OR ROM32_INSTR_PT(251) + OR ROM32_INSTR_PT(254) OR ROM32_INSTR_PT(256) + OR ROM32_INSTR_PT(257) OR ROM32_INSTR_PT(261) + OR ROM32_INSTR_PT(262) OR ROM32_INSTR_PT(267) + OR ROM32_INSTR_PT(270) OR ROM32_INSTR_PT(273) + OR ROM32_INSTR_PT(275) OR ROM32_INSTR_PT(278) + OR ROM32_INSTR_PT(281) OR ROM32_INSTR_PT(289) + OR ROM32_INSTR_PT(295) OR ROM32_INSTR_PT(297) + OR ROM32_INSTR_PT(310) OR ROM32_INSTR_PT(313) + OR ROM32_INSTR_PT(344) OR ROM32_INSTR_PT(360) + OR ROM32_INSTR_PT(362) OR ROM32_INSTR_PT(368) + OR ROM32_INSTR_PT(371) OR ROM32_INSTR_PT(378) + OR ROM32_INSTR_PT(385) OR ROM32_INSTR_PT(387) + OR ROM32_INSTR_PT(390) OR ROM32_INSTR_PT(396) + OR ROM32_INSTR_PT(398) OR ROM32_INSTR_PT(401) + OR ROM32_INSTR_PT(411) OR ROM32_INSTR_PT(412) + OR ROM32_INSTR_PT(416) OR ROM32_INSTR_PT(419) + OR ROM32_INSTR_PT(421) OR ROM32_INSTR_PT(424) + OR ROM32_INSTR_PT(426) OR ROM32_INSTR_PT(433) + OR ROM32_INSTR_PT(434) OR ROM32_INSTR_PT(453) + OR ROM32_INSTR_PT(454) OR ROM32_INSTR_PT(461) + OR ROM32_INSTR_PT(496) OR ROM32_INSTR_PT(502) + OR ROM32_INSTR_PT(506) OR ROM32_INSTR_PT(507) + OR ROM32_INSTR_PT(508) OR ROM32_INSTR_PT(516) + OR ROM32_INSTR_PT(519) OR ROM32_INSTR_PT(521) + OR ROM32_INSTR_PT(524) OR ROM32_INSTR_PT(530) + OR ROM32_INSTR_PT(531) OR ROM32_INSTR_PT(535) + OR ROM32_INSTR_PT(537) OR ROM32_INSTR_PT(539) + OR ROM32_INSTR_PT(543) OR ROM32_INSTR_PT(547) + OR ROM32_INSTR_PT(556) OR ROM32_INSTR_PT(558) + OR ROM32_INSTR_PT(568) OR ROM32_INSTR_PT(569) + OR ROM32_INSTR_PT(574) OR ROM32_INSTR_PT(575) + OR ROM32_INSTR_PT(578) OR ROM32_INSTR_PT(579) + OR ROM32_INSTR_PT(583) OR ROM32_INSTR_PT(585) + OR ROM32_INSTR_PT(588) OR ROM32_INSTR_PT(590) + OR ROM32_INSTR_PT(591) OR ROM32_INSTR_PT(611) + OR ROM32_INSTR_PT(612) OR ROM32_INSTR_PT(614) + OR ROM32_INSTR_PT(621) OR ROM32_INSTR_PT(625) + OR ROM32_INSTR_PT(626) OR ROM32_INSTR_PT(663) + OR ROM32_INSTR_PT(728) OR ROM32_INSTR_PT(751) + OR ROM32_INSTR_PT(753) OR ROM32_INSTR_PT(817) + ); +MQQ1877:TEMPLATE(22) <= + (ROM32_INSTR_PT(4) OR ROM32_INSTR_PT(7) + OR ROM32_INSTR_PT(8) OR ROM32_INSTR_PT(10) + OR ROM32_INSTR_PT(12) OR ROM32_INSTR_PT(14) + OR ROM32_INSTR_PT(17) OR ROM32_INSTR_PT(20) + OR ROM32_INSTR_PT(23) OR ROM32_INSTR_PT(29) + OR ROM32_INSTR_PT(35) OR ROM32_INSTR_PT(38) + OR ROM32_INSTR_PT(43) OR ROM32_INSTR_PT(53) + OR ROM32_INSTR_PT(56) OR ROM32_INSTR_PT(57) + OR ROM32_INSTR_PT(74) OR ROM32_INSTR_PT(78) + OR ROM32_INSTR_PT(80) OR ROM32_INSTR_PT(93) + OR ROM32_INSTR_PT(95) OR ROM32_INSTR_PT(97) + OR ROM32_INSTR_PT(101) OR ROM32_INSTR_PT(114) + OR ROM32_INSTR_PT(119) OR ROM32_INSTR_PT(122) + OR ROM32_INSTR_PT(131) OR ROM32_INSTR_PT(134) + OR ROM32_INSTR_PT(143) OR ROM32_INSTR_PT(148) + OR ROM32_INSTR_PT(155) OR ROM32_INSTR_PT(158) + OR ROM32_INSTR_PT(163) OR ROM32_INSTR_PT(164) + OR ROM32_INSTR_PT(171) OR ROM32_INSTR_PT(172) + OR ROM32_INSTR_PT(179) OR ROM32_INSTR_PT(186) + OR ROM32_INSTR_PT(196) OR ROM32_INSTR_PT(202) + OR ROM32_INSTR_PT(203) OR ROM32_INSTR_PT(205) + OR ROM32_INSTR_PT(207) OR ROM32_INSTR_PT(212) + OR ROM32_INSTR_PT(218) OR ROM32_INSTR_PT(220) + OR ROM32_INSTR_PT(223) OR ROM32_INSTR_PT(224) + OR ROM32_INSTR_PT(229) OR ROM32_INSTR_PT(243) + OR ROM32_INSTR_PT(244) OR ROM32_INSTR_PT(251) + OR ROM32_INSTR_PT(257) OR ROM32_INSTR_PT(262) + OR ROM32_INSTR_PT(271) OR ROM32_INSTR_PT(278) + OR ROM32_INSTR_PT(281) OR ROM32_INSTR_PT(289) + OR ROM32_INSTR_PT(295) OR ROM32_INSTR_PT(297) + OR ROM32_INSTR_PT(301) OR ROM32_INSTR_PT(310) + OR ROM32_INSTR_PT(323) OR ROM32_INSTR_PT(350) + OR ROM32_INSTR_PT(362) OR ROM32_INSTR_PT(367) + OR ROM32_INSTR_PT(376) OR ROM32_INSTR_PT(387) + OR ROM32_INSTR_PT(392) OR ROM32_INSTR_PT(394) + OR ROM32_INSTR_PT(396) OR ROM32_INSTR_PT(398) + OR ROM32_INSTR_PT(402) OR ROM32_INSTR_PT(411) + OR ROM32_INSTR_PT(423) OR ROM32_INSTR_PT(424) + OR ROM32_INSTR_PT(434) OR ROM32_INSTR_PT(435) + OR ROM32_INSTR_PT(436) OR ROM32_INSTR_PT(438) + OR ROM32_INSTR_PT(452) OR ROM32_INSTR_PT(453) + OR ROM32_INSTR_PT(454) OR ROM32_INSTR_PT(456) + OR ROM32_INSTR_PT(458) OR ROM32_INSTR_PT(461) + OR ROM32_INSTR_PT(464) OR ROM32_INSTR_PT(469) + OR ROM32_INSTR_PT(472) OR ROM32_INSTR_PT(478) + OR ROM32_INSTR_PT(484) OR ROM32_INSTR_PT(486) + OR ROM32_INSTR_PT(496) OR ROM32_INSTR_PT(503) + OR ROM32_INSTR_PT(506) OR ROM32_INSTR_PT(511) + OR ROM32_INSTR_PT(514) OR ROM32_INSTR_PT(516) + OR ROM32_INSTR_PT(517) OR ROM32_INSTR_PT(521) + OR ROM32_INSTR_PT(532) OR ROM32_INSTR_PT(537) + OR ROM32_INSTR_PT(539) OR ROM32_INSTR_PT(543) + OR ROM32_INSTR_PT(551) OR ROM32_INSTR_PT(558) + OR ROM32_INSTR_PT(566) OR ROM32_INSTR_PT(575) + OR ROM32_INSTR_PT(577) OR ROM32_INSTR_PT(580) + OR ROM32_INSTR_PT(581) OR ROM32_INSTR_PT(583) + OR ROM32_INSTR_PT(584) OR ROM32_INSTR_PT(588) + OR ROM32_INSTR_PT(591) OR ROM32_INSTR_PT(599) + OR ROM32_INSTR_PT(601) OR ROM32_INSTR_PT(605) + OR ROM32_INSTR_PT(607) OR ROM32_INSTR_PT(611) + OR ROM32_INSTR_PT(614) OR ROM32_INSTR_PT(622) + OR ROM32_INSTR_PT(625) OR ROM32_INSTR_PT(634) + OR ROM32_INSTR_PT(638) OR ROM32_INSTR_PT(643) + OR ROM32_INSTR_PT(654) OR ROM32_INSTR_PT(663) + OR ROM32_INSTR_PT(684) OR ROM32_INSTR_PT(693) + OR ROM32_INSTR_PT(708) OR ROM32_INSTR_PT(720) + OR ROM32_INSTR_PT(728) OR ROM32_INSTR_PT(751) + OR ROM32_INSTR_PT(753) OR ROM32_INSTR_PT(807) + OR ROM32_INSTR_PT(817) OR ROM32_INSTR_PT(819) + OR ROM32_INSTR_PT(823) OR ROM32_INSTR_PT(845) + OR ROM32_INSTR_PT(853)); +MQQ1878:TEMPLATE(23) <= + (ROM32_INSTR_PT(4) OR ROM32_INSTR_PT(5) + OR ROM32_INSTR_PT(12) OR ROM32_INSTR_PT(23) + OR ROM32_INSTR_PT(35) OR ROM32_INSTR_PT(38) + OR ROM32_INSTR_PT(56) OR ROM32_INSTR_PT(57) + OR ROM32_INSTR_PT(93) OR ROM32_INSTR_PT(95) + OR ROM32_INSTR_PT(100) OR ROM32_INSTR_PT(101) + OR ROM32_INSTR_PT(111) OR ROM32_INSTR_PT(124) + OR ROM32_INSTR_PT(135) OR ROM32_INSTR_PT(143) + OR ROM32_INSTR_PT(155) OR ROM32_INSTR_PT(158) + OR ROM32_INSTR_PT(163) OR ROM32_INSTR_PT(179) + OR ROM32_INSTR_PT(187) OR ROM32_INSTR_PT(194) + OR ROM32_INSTR_PT(202) OR ROM32_INSTR_PT(203) + OR ROM32_INSTR_PT(207) OR ROM32_INSTR_PT(218) + OR ROM32_INSTR_PT(220) OR ROM32_INSTR_PT(229) + OR ROM32_INSTR_PT(232) OR ROM32_INSTR_PT(235) + OR ROM32_INSTR_PT(243) OR ROM32_INSTR_PT(244) + OR ROM32_INSTR_PT(251) OR ROM32_INSTR_PT(254) + OR ROM32_INSTR_PT(256) OR ROM32_INSTR_PT(257) + OR ROM32_INSTR_PT(259) OR ROM32_INSTR_PT(260) + OR ROM32_INSTR_PT(264) OR ROM32_INSTR_PT(275) + OR ROM32_INSTR_PT(281) OR ROM32_INSTR_PT(282) + OR ROM32_INSTR_PT(293) OR ROM32_INSTR_PT(310) + OR ROM32_INSTR_PT(318) OR ROM32_INSTR_PT(350) + OR ROM32_INSTR_PT(362) OR ROM32_INSTR_PT(367) + OR ROM32_INSTR_PT(374) OR ROM32_INSTR_PT(376) + OR ROM32_INSTR_PT(378) OR ROM32_INSTR_PT(387) + OR ROM32_INSTR_PT(394) OR ROM32_INSTR_PT(398) + OR ROM32_INSTR_PT(402) OR ROM32_INSTR_PT(409) + OR ROM32_INSTR_PT(416) OR ROM32_INSTR_PT(419) + OR ROM32_INSTR_PT(423) OR ROM32_INSTR_PT(434) + OR ROM32_INSTR_PT(443) OR ROM32_INSTR_PT(453) + OR ROM32_INSTR_PT(454) OR ROM32_INSTR_PT(456) + OR ROM32_INSTR_PT(458) OR ROM32_INSTR_PT(464) + OR ROM32_INSTR_PT(469) OR ROM32_INSTR_PT(472) + OR ROM32_INSTR_PT(484) OR ROM32_INSTR_PT(486) + OR ROM32_INSTR_PT(501) OR ROM32_INSTR_PT(503) + OR ROM32_INSTR_PT(514) OR ROM32_INSTR_PT(516) + OR ROM32_INSTR_PT(531) OR ROM32_INSTR_PT(535) + OR ROM32_INSTR_PT(537) OR ROM32_INSTR_PT(544) + OR ROM32_INSTR_PT(547) OR ROM32_INSTR_PT(551) + OR ROM32_INSTR_PT(557) OR ROM32_INSTR_PT(558) + OR ROM32_INSTR_PT(562) OR ROM32_INSTR_PT(574) + OR ROM32_INSTR_PT(577) OR ROM32_INSTR_PT(581) + OR ROM32_INSTR_PT(588) OR ROM32_INSTR_PT(591) + OR ROM32_INSTR_PT(600) OR ROM32_INSTR_PT(605) + OR ROM32_INSTR_PT(609) OR ROM32_INSTR_PT(611) + OR ROM32_INSTR_PT(621) OR ROM32_INSTR_PT(625) + OR ROM32_INSTR_PT(643) OR ROM32_INSTR_PT(663) + OR ROM32_INSTR_PT(690) OR ROM32_INSTR_PT(713) + OR ROM32_INSTR_PT(720) OR ROM32_INSTR_PT(728) + OR ROM32_INSTR_PT(751) OR ROM32_INSTR_PT(753) + OR ROM32_INSTR_PT(807) OR ROM32_INSTR_PT(817) + OR ROM32_INSTR_PT(819) OR ROM32_INSTR_PT(823) + OR ROM32_INSTR_PT(845)); +MQQ1879:TEMPLATE(24) <= + (ROM32_INSTR_PT(3) OR ROM32_INSTR_PT(4) + OR ROM32_INSTR_PT(5) OR ROM32_INSTR_PT(10) + OR ROM32_INSTR_PT(13) OR ROM32_INSTR_PT(26) + OR ROM32_INSTR_PT(29) OR ROM32_INSTR_PT(34) + OR ROM32_INSTR_PT(35) OR ROM32_INSTR_PT(41) + OR ROM32_INSTR_PT(45) OR ROM32_INSTR_PT(51) + OR ROM32_INSTR_PT(79) OR ROM32_INSTR_PT(93) + OR ROM32_INSTR_PT(95) OR ROM32_INSTR_PT(100) + OR ROM32_INSTR_PT(106) OR ROM32_INSTR_PT(116) + OR ROM32_INSTR_PT(124) OR ROM32_INSTR_PT(135) + OR ROM32_INSTR_PT(139) OR ROM32_INSTR_PT(142) + OR ROM32_INSTR_PT(153) OR ROM32_INSTR_PT(159) + OR ROM32_INSTR_PT(170) OR ROM32_INSTR_PT(172) + OR ROM32_INSTR_PT(183) OR ROM32_INSTR_PT(194) + OR ROM32_INSTR_PT(204) OR ROM32_INSTR_PT(218) + OR ROM32_INSTR_PT(220) OR ROM32_INSTR_PT(229) + OR ROM32_INSTR_PT(241) OR ROM32_INSTR_PT(251) + OR ROM32_INSTR_PT(254) OR ROM32_INSTR_PT(256) + OR ROM32_INSTR_PT(257) OR ROM32_INSTR_PT(258) + OR ROM32_INSTR_PT(260) OR ROM32_INSTR_PT(275) + OR ROM32_INSTR_PT(276) OR ROM32_INSTR_PT(281) + OR ROM32_INSTR_PT(282) OR ROM32_INSTR_PT(290) + OR ROM32_INSTR_PT(293) OR ROM32_INSTR_PT(306) + OR ROM32_INSTR_PT(309) OR ROM32_INSTR_PT(318) + OR ROM32_INSTR_PT(344) OR ROM32_INSTR_PT(362) + OR ROM32_INSTR_PT(363) OR ROM32_INSTR_PT(374) + OR ROM32_INSTR_PT(385) OR ROM32_INSTR_PT(393) + OR ROM32_INSTR_PT(398) OR ROM32_INSTR_PT(409) + OR ROM32_INSTR_PT(415) OR ROM32_INSTR_PT(425) + OR ROM32_INSTR_PT(426) OR ROM32_INSTR_PT(428) + OR ROM32_INSTR_PT(430) OR ROM32_INSTR_PT(434) + OR ROM32_INSTR_PT(437) OR ROM32_INSTR_PT(443) + OR ROM32_INSTR_PT(451) OR ROM32_INSTR_PT(454) + OR ROM32_INSTR_PT(495) OR ROM32_INSTR_PT(501) + OR ROM32_INSTR_PT(509) OR ROM32_INSTR_PT(516) + OR ROM32_INSTR_PT(530) OR ROM32_INSTR_PT(531) + OR ROM32_INSTR_PT(535) OR ROM32_INSTR_PT(543) + OR ROM32_INSTR_PT(544) OR ROM32_INSTR_PT(547) + OR ROM32_INSTR_PT(555) OR ROM32_INSTR_PT(557) + OR ROM32_INSTR_PT(558) OR ROM32_INSTR_PT(563) + OR ROM32_INSTR_PT(574) OR ROM32_INSTR_PT(575) + OR ROM32_INSTR_PT(579) OR ROM32_INSTR_PT(581) + OR ROM32_INSTR_PT(587) OR ROM32_INSTR_PT(591) + OR ROM32_INSTR_PT(600) OR ROM32_INSTR_PT(609) + OR ROM32_INSTR_PT(611) OR ROM32_INSTR_PT(615) + OR ROM32_INSTR_PT(621) OR ROM32_INSTR_PT(624) + OR ROM32_INSTR_PT(625) OR ROM32_INSTR_PT(646) + OR ROM32_INSTR_PT(663) OR ROM32_INSTR_PT(690) + OR ROM32_INSTR_PT(700) OR ROM32_INSTR_PT(729) + OR ROM32_INSTR_PT(745) OR ROM32_INSTR_PT(763) + OR ROM32_INSTR_PT(817) OR ROM32_INSTR_PT(845) + ); +MQQ1880:TEMPLATE(25) <= + (ROM32_INSTR_PT(4) OR ROM32_INSTR_PT(5) + OR ROM32_INSTR_PT(12) OR ROM32_INSTR_PT(20) + OR ROM32_INSTR_PT(23) OR ROM32_INSTR_PT(35) + OR ROM32_INSTR_PT(42) OR ROM32_INSTR_PT(56) + OR ROM32_INSTR_PT(57) OR ROM32_INSTR_PT(95) + OR ROM32_INSTR_PT(97) OR ROM32_INSTR_PT(101) + OR ROM32_INSTR_PT(119) OR ROM32_INSTR_PT(125) + OR ROM32_INSTR_PT(132) OR ROM32_INSTR_PT(142) + OR ROM32_INSTR_PT(143) OR ROM32_INSTR_PT(155) + OR ROM32_INSTR_PT(158) OR ROM32_INSTR_PT(159) + OR ROM32_INSTR_PT(163) OR ROM32_INSTR_PT(170) + OR ROM32_INSTR_PT(172) OR ROM32_INSTR_PT(178) + OR ROM32_INSTR_PT(179) OR ROM32_INSTR_PT(187) + OR ROM32_INSTR_PT(194) OR ROM32_INSTR_PT(196) + OR ROM32_INSTR_PT(203) OR ROM32_INSTR_PT(207) + OR ROM32_INSTR_PT(218) OR ROM32_INSTR_PT(224) + OR ROM32_INSTR_PT(229) OR ROM32_INSTR_PT(232) + OR ROM32_INSTR_PT(235) OR ROM32_INSTR_PT(243) + OR ROM32_INSTR_PT(251) OR ROM32_INSTR_PT(256) + OR ROM32_INSTR_PT(257) OR ROM32_INSTR_PT(275) + OR ROM32_INSTR_PT(276) OR ROM32_INSTR_PT(278) + OR ROM32_INSTR_PT(281) OR ROM32_INSTR_PT(290) + OR ROM32_INSTR_PT(309) OR ROM32_INSTR_PT(335) + OR ROM32_INSTR_PT(344) OR ROM32_INSTR_PT(350) + OR ROM32_INSTR_PT(362) OR ROM32_INSTR_PT(363) + OR ROM32_INSTR_PT(367) OR ROM32_INSTR_PT(376) + OR ROM32_INSTR_PT(378) OR ROM32_INSTR_PT(385) + OR ROM32_INSTR_PT(394) OR ROM32_INSTR_PT(396) + OR ROM32_INSTR_PT(398) OR ROM32_INSTR_PT(402) + OR ROM32_INSTR_PT(416) OR ROM32_INSTR_PT(419) + OR ROM32_INSTR_PT(423) OR ROM32_INSTR_PT(424) + OR ROM32_INSTR_PT(426) OR ROM32_INSTR_PT(430) + OR ROM32_INSTR_PT(442) OR ROM32_INSTR_PT(454) + OR ROM32_INSTR_PT(456) OR ROM32_INSTR_PT(458) + OR ROM32_INSTR_PT(464) OR ROM32_INSTR_PT(469) + OR ROM32_INSTR_PT(472) OR ROM32_INSTR_PT(474) + OR ROM32_INSTR_PT(476) OR ROM32_INSTR_PT(484) + OR ROM32_INSTR_PT(486) OR ROM32_INSTR_PT(503) + OR ROM32_INSTR_PT(504) OR ROM32_INSTR_PT(514) + OR ROM32_INSTR_PT(521) OR ROM32_INSTR_PT(522) + OR ROM32_INSTR_PT(530) OR ROM32_INSTR_PT(531) + OR ROM32_INSTR_PT(535) OR ROM32_INSTR_PT(541) + OR ROM32_INSTR_PT(547) OR ROM32_INSTR_PT(551) + OR ROM32_INSTR_PT(554) OR ROM32_INSTR_PT(555) + OR ROM32_INSTR_PT(558) OR ROM32_INSTR_PT(574) + OR ROM32_INSTR_PT(575) OR ROM32_INSTR_PT(577) + OR ROM32_INSTR_PT(579) OR ROM32_INSTR_PT(588) + OR ROM32_INSTR_PT(591) OR ROM32_INSTR_PT(605) + OR ROM32_INSTR_PT(611) OR ROM32_INSTR_PT(620) + OR ROM32_INSTR_PT(629) OR ROM32_INSTR_PT(633) + OR ROM32_INSTR_PT(642) OR ROM32_INSTR_PT(643) + OR ROM32_INSTR_PT(654) OR ROM32_INSTR_PT(664) + OR ROM32_INSTR_PT(690) OR ROM32_INSTR_PT(697) + OR ROM32_INSTR_PT(708) OR ROM32_INSTR_PT(729) + OR ROM32_INSTR_PT(731) OR ROM32_INSTR_PT(745) + OR ROM32_INSTR_PT(792) OR ROM32_INSTR_PT(817) + OR ROM32_INSTR_PT(818) OR ROM32_INSTR_PT(819) + OR ROM32_INSTR_PT(829)); +MQQ1881:TEMPLATE(26) <= + (ROM32_INSTR_PT(3) OR ROM32_INSTR_PT(4) + OR ROM32_INSTR_PT(5) OR ROM32_INSTR_PT(6) + OR ROM32_INSTR_PT(8) OR ROM32_INSTR_PT(9) + OR ROM32_INSTR_PT(10) OR ROM32_INSTR_PT(12) + OR ROM32_INSTR_PT(13) OR ROM32_INSTR_PT(17) + OR ROM32_INSTR_PT(20) OR ROM32_INSTR_PT(23) + OR ROM32_INSTR_PT(26) OR ROM32_INSTR_PT(29) + OR ROM32_INSTR_PT(33) OR ROM32_INSTR_PT(35) + OR ROM32_INSTR_PT(37) OR ROM32_INSTR_PT(39) + OR ROM32_INSTR_PT(41) OR ROM32_INSTR_PT(43) + OR ROM32_INSTR_PT(45) OR ROM32_INSTR_PT(49) + OR ROM32_INSTR_PT(50) OR ROM32_INSTR_PT(51) + OR ROM32_INSTR_PT(52) OR ROM32_INSTR_PT(56) + OR ROM32_INSTR_PT(57) OR ROM32_INSTR_PT(59) + OR ROM32_INSTR_PT(60) OR ROM32_INSTR_PT(63) + OR ROM32_INSTR_PT(66) OR ROM32_INSTR_PT(72) + OR ROM32_INSTR_PT(73) OR ROM32_INSTR_PT(74) + OR ROM32_INSTR_PT(78) OR ROM32_INSTR_PT(80) + OR ROM32_INSTR_PT(83) OR ROM32_INSTR_PT(84) + OR ROM32_INSTR_PT(85) OR ROM32_INSTR_PT(87) + OR ROM32_INSTR_PT(90) OR ROM32_INSTR_PT(92) + OR ROM32_INSTR_PT(93) OR ROM32_INSTR_PT(95) + OR ROM32_INSTR_PT(96) OR ROM32_INSTR_PT(97) + OR ROM32_INSTR_PT(100) OR ROM32_INSTR_PT(101) + OR ROM32_INSTR_PT(102) OR ROM32_INSTR_PT(103) + OR ROM32_INSTR_PT(106) OR ROM32_INSTR_PT(109) + OR ROM32_INSTR_PT(110) OR ROM32_INSTR_PT(115) + OR ROM32_INSTR_PT(116) OR ROM32_INSTR_PT(117) + OR ROM32_INSTR_PT(118) OR ROM32_INSTR_PT(119) + OR ROM32_INSTR_PT(124) OR ROM32_INSTR_PT(130) + OR ROM32_INSTR_PT(134) OR ROM32_INSTR_PT(135) + OR ROM32_INSTR_PT(139) OR ROM32_INSTR_PT(141) + OR ROM32_INSTR_PT(142) OR ROM32_INSTR_PT(143) + OR ROM32_INSTR_PT(144) OR ROM32_INSTR_PT(148) + OR ROM32_INSTR_PT(153) OR ROM32_INSTR_PT(154) + OR ROM32_INSTR_PT(155) OR ROM32_INSTR_PT(158) + OR ROM32_INSTR_PT(159) OR ROM32_INSTR_PT(163) + OR ROM32_INSTR_PT(169) OR ROM32_INSTR_PT(172) + OR ROM32_INSTR_PT(174) OR ROM32_INSTR_PT(176) + OR ROM32_INSTR_PT(179) OR ROM32_INSTR_PT(180) + OR ROM32_INSTR_PT(181) OR ROM32_INSTR_PT(183) + OR ROM32_INSTR_PT(184) OR ROM32_INSTR_PT(186) + OR ROM32_INSTR_PT(192) OR ROM32_INSTR_PT(194) + OR ROM32_INSTR_PT(196) OR ROM32_INSTR_PT(199) + OR ROM32_INSTR_PT(202) OR ROM32_INSTR_PT(203) + OR ROM32_INSTR_PT(204) OR ROM32_INSTR_PT(206) + OR ROM32_INSTR_PT(207) OR ROM32_INSTR_PT(216) + OR ROM32_INSTR_PT(218) OR ROM32_INSTR_PT(220) + OR ROM32_INSTR_PT(223) OR ROM32_INSTR_PT(224) + OR ROM32_INSTR_PT(227) OR ROM32_INSTR_PT(233) + OR ROM32_INSTR_PT(238) OR ROM32_INSTR_PT(241) + OR ROM32_INSTR_PT(243) OR ROM32_INSTR_PT(244) + OR ROM32_INSTR_PT(249) OR ROM32_INSTR_PT(251) + OR ROM32_INSTR_PT(252) OR ROM32_INSTR_PT(254) + OR ROM32_INSTR_PT(256) OR ROM32_INSTR_PT(257) + OR ROM32_INSTR_PT(259) OR ROM32_INSTR_PT(260) + OR ROM32_INSTR_PT(261) OR ROM32_INSTR_PT(262) + OR ROM32_INSTR_PT(264) OR ROM32_INSTR_PT(266) + OR ROM32_INSTR_PT(267) OR ROM32_INSTR_PT(268) + OR ROM32_INSTR_PT(269) OR ROM32_INSTR_PT(270) + OR ROM32_INSTR_PT(273) OR ROM32_INSTR_PT(274) + OR ROM32_INSTR_PT(275) OR ROM32_INSTR_PT(278) + OR ROM32_INSTR_PT(280) OR ROM32_INSTR_PT(281) + OR ROM32_INSTR_PT(282) OR ROM32_INSTR_PT(284) + OR ROM32_INSTR_PT(288) OR ROM32_INSTR_PT(289) + OR ROM32_INSTR_PT(290) OR ROM32_INSTR_PT(293) + OR ROM32_INSTR_PT(294) OR ROM32_INSTR_PT(295) + OR ROM32_INSTR_PT(297) OR ROM32_INSTR_PT(299) + OR ROM32_INSTR_PT(301) OR ROM32_INSTR_PT(303) + OR ROM32_INSTR_PT(306) OR ROM32_INSTR_PT(309) + OR ROM32_INSTR_PT(310) OR ROM32_INSTR_PT(313) + OR ROM32_INSTR_PT(318) OR ROM32_INSTR_PT(335) + OR ROM32_INSTR_PT(344) OR ROM32_INSTR_PT(346) + OR ROM32_INSTR_PT(348) OR ROM32_INSTR_PT(350) + OR ROM32_INSTR_PT(353) OR ROM32_INSTR_PT(356) + OR ROM32_INSTR_PT(361) OR ROM32_INSTR_PT(362) + OR ROM32_INSTR_PT(364) OR ROM32_INSTR_PT(367) + OR ROM32_INSTR_PT(371) OR ROM32_INSTR_PT(373) + OR ROM32_INSTR_PT(374) OR ROM32_INSTR_PT(376) + OR ROM32_INSTR_PT(379) OR ROM32_INSTR_PT(381) + OR ROM32_INSTR_PT(382) OR ROM32_INSTR_PT(383) + OR ROM32_INSTR_PT(386) OR ROM32_INSTR_PT(387) + OR ROM32_INSTR_PT(390) OR ROM32_INSTR_PT(392) + OR ROM32_INSTR_PT(394) OR ROM32_INSTR_PT(396) + OR ROM32_INSTR_PT(398) OR ROM32_INSTR_PT(400) + OR ROM32_INSTR_PT(401) OR ROM32_INSTR_PT(402) + OR ROM32_INSTR_PT(405) OR ROM32_INSTR_PT(406) + OR ROM32_INSTR_PT(409) OR ROM32_INSTR_PT(411) + OR ROM32_INSTR_PT(412) OR ROM32_INSTR_PT(415) + OR ROM32_INSTR_PT(417) OR ROM32_INSTR_PT(421) + OR ROM32_INSTR_PT(422) OR ROM32_INSTR_PT(423) + OR ROM32_INSTR_PT(424) OR ROM32_INSTR_PT(425) + OR ROM32_INSTR_PT(426) OR ROM32_INSTR_PT(428) + OR ROM32_INSTR_PT(431) OR ROM32_INSTR_PT(433) + OR ROM32_INSTR_PT(434) OR ROM32_INSTR_PT(437) + OR ROM32_INSTR_PT(441) OR ROM32_INSTR_PT(443) + OR ROM32_INSTR_PT(451) OR ROM32_INSTR_PT(453) + OR ROM32_INSTR_PT(454) OR ROM32_INSTR_PT(458) + OR ROM32_INSTR_PT(459) OR ROM32_INSTR_PT(461) + OR ROM32_INSTR_PT(464) OR ROM32_INSTR_PT(469) + OR ROM32_INSTR_PT(472) OR ROM32_INSTR_PT(475) + OR ROM32_INSTR_PT(478) OR ROM32_INSTR_PT(479) + OR ROM32_INSTR_PT(481) OR ROM32_INSTR_PT(482) + OR ROM32_INSTR_PT(484) OR ROM32_INSTR_PT(486) + OR ROM32_INSTR_PT(490) OR ROM32_INSTR_PT(491) + OR ROM32_INSTR_PT(494) OR ROM32_INSTR_PT(495) + OR ROM32_INSTR_PT(496) OR ROM32_INSTR_PT(501) + OR ROM32_INSTR_PT(502) OR ROM32_INSTR_PT(503) + OR ROM32_INSTR_PT(506) OR ROM32_INSTR_PT(507) + OR ROM32_INSTR_PT(508) OR ROM32_INSTR_PT(509) + OR ROM32_INSTR_PT(514) OR ROM32_INSTR_PT(516) + OR ROM32_INSTR_PT(519) OR ROM32_INSTR_PT(520) + OR ROM32_INSTR_PT(521) OR ROM32_INSTR_PT(522) + OR ROM32_INSTR_PT(524) OR ROM32_INSTR_PT(530) + OR ROM32_INSTR_PT(531) OR ROM32_INSTR_PT(534) + OR ROM32_INSTR_PT(535) OR ROM32_INSTR_PT(539) + OR ROM32_INSTR_PT(543) OR ROM32_INSTR_PT(544) + OR ROM32_INSTR_PT(547) OR ROM32_INSTR_PT(550) + OR ROM32_INSTR_PT(551) OR ROM32_INSTR_PT(552) + OR ROM32_INSTR_PT(554) OR ROM32_INSTR_PT(555) + OR ROM32_INSTR_PT(556) OR ROM32_INSTR_PT(557) + OR ROM32_INSTR_PT(562) OR ROM32_INSTR_PT(563) + OR ROM32_INSTR_PT(568) OR ROM32_INSTR_PT(569) + OR ROM32_INSTR_PT(570) OR ROM32_INSTR_PT(574) + OR ROM32_INSTR_PT(575) OR ROM32_INSTR_PT(578) + OR ROM32_INSTR_PT(579) OR ROM32_INSTR_PT(581) + OR ROM32_INSTR_PT(582) OR ROM32_INSTR_PT(583) + OR ROM32_INSTR_PT(585) OR ROM32_INSTR_PT(588) + OR ROM32_INSTR_PT(590) OR ROM32_INSTR_PT(591) + OR ROM32_INSTR_PT(600) OR ROM32_INSTR_PT(602) + OR ROM32_INSTR_PT(603) OR ROM32_INSTR_PT(605) + OR ROM32_INSTR_PT(609) OR ROM32_INSTR_PT(610) + OR ROM32_INSTR_PT(611) OR ROM32_INSTR_PT(612) + OR ROM32_INSTR_PT(613) OR ROM32_INSTR_PT(614) + OR ROM32_INSTR_PT(615) OR ROM32_INSTR_PT(621) + OR ROM32_INSTR_PT(624) OR ROM32_INSTR_PT(625) + OR ROM32_INSTR_PT(626) OR ROM32_INSTR_PT(629) + OR ROM32_INSTR_PT(630) OR ROM32_INSTR_PT(639) + OR ROM32_INSTR_PT(640) OR ROM32_INSTR_PT(642) + OR ROM32_INSTR_PT(643) OR ROM32_INSTR_PT(654) + OR ROM32_INSTR_PT(660) OR ROM32_INSTR_PT(663) + OR ROM32_INSTR_PT(664) OR ROM32_INSTR_PT(666) + OR ROM32_INSTR_PT(674) OR ROM32_INSTR_PT(677) + OR ROM32_INSTR_PT(692) OR ROM32_INSTR_PT(697) + OR ROM32_INSTR_PT(708) OR ROM32_INSTR_PT(711) + OR ROM32_INSTR_PT(713) OR ROM32_INSTR_PT(718) + OR ROM32_INSTR_PT(719) OR ROM32_INSTR_PT(720) + OR ROM32_INSTR_PT(729) OR ROM32_INSTR_PT(755) + OR ROM32_INSTR_PT(763) OR ROM32_INSTR_PT(792) + OR ROM32_INSTR_PT(805) OR ROM32_INSTR_PT(807) + OR ROM32_INSTR_PT(812) OR ROM32_INSTR_PT(817) + OR ROM32_INSTR_PT(819) OR ROM32_INSTR_PT(823) + OR ROM32_INSTR_PT(829) OR ROM32_INSTR_PT(831) + OR ROM32_INSTR_PT(845) OR ROM32_INSTR_PT(854) + OR ROM32_INSTR_PT(855) OR ROM32_INSTR_PT(857) + OR ROM32_INSTR_PT(862) OR ROM32_INSTR_PT(870) + OR ROM32_INSTR_PT(872) OR ROM32_INSTR_PT(878) + ); +MQQ1882:TEMPLATE(27) <= + (ROM32_INSTR_PT(4) OR ROM32_INSTR_PT(5) + OR ROM32_INSTR_PT(6) OR ROM32_INSTR_PT(7) + OR ROM32_INSTR_PT(8) OR ROM32_INSTR_PT(9) + OR ROM32_INSTR_PT(10) OR ROM32_INSTR_PT(12) + OR ROM32_INSTR_PT(14) OR ROM32_INSTR_PT(17) + OR ROM32_INSTR_PT(20) OR ROM32_INSTR_PT(26) + OR ROM32_INSTR_PT(33) OR ROM32_INSTR_PT(37) + OR ROM32_INSTR_PT(39) OR ROM32_INSTR_PT(42) + OR ROM32_INSTR_PT(45) OR ROM32_INSTR_PT(49) + OR ROM32_INSTR_PT(52) OR ROM32_INSTR_PT(53) + OR ROM32_INSTR_PT(56) OR ROM32_INSTR_PT(57) + OR ROM32_INSTR_PT(59) OR ROM32_INSTR_PT(63) + OR ROM32_INSTR_PT(66) OR ROM32_INSTR_PT(72) + OR ROM32_INSTR_PT(74) OR ROM32_INSTR_PT(83) + OR ROM32_INSTR_PT(84) OR ROM32_INSTR_PT(85) + OR ROM32_INSTR_PT(90) OR ROM32_INSTR_PT(93) + OR ROM32_INSTR_PT(95) OR ROM32_INSTR_PT(96) + OR ROM32_INSTR_PT(101) OR ROM32_INSTR_PT(102) + OR ROM32_INSTR_PT(103) OR ROM32_INSTR_PT(109) + OR ROM32_INSTR_PT(110) OR ROM32_INSTR_PT(114) + OR ROM32_INSTR_PT(115) OR ROM32_INSTR_PT(117) + OR ROM32_INSTR_PT(118) OR ROM32_INSTR_PT(119) + OR ROM32_INSTR_PT(130) OR ROM32_INSTR_PT(131) + OR ROM32_INSTR_PT(134) OR ROM32_INSTR_PT(141) + OR ROM32_INSTR_PT(142) OR ROM32_INSTR_PT(143) + OR ROM32_INSTR_PT(144) OR ROM32_INSTR_PT(148) + OR ROM32_INSTR_PT(155) OR ROM32_INSTR_PT(158) + OR ROM32_INSTR_PT(159) OR ROM32_INSTR_PT(163) + OR ROM32_INSTR_PT(164) OR ROM32_INSTR_PT(169) + OR ROM32_INSTR_PT(170) OR ROM32_INSTR_PT(171) + OR ROM32_INSTR_PT(176) OR ROM32_INSTR_PT(178) + OR ROM32_INSTR_PT(179) OR ROM32_INSTR_PT(180) + OR ROM32_INSTR_PT(181) OR ROM32_INSTR_PT(184) + OR ROM32_INSTR_PT(187) OR ROM32_INSTR_PT(192) + OR ROM32_INSTR_PT(194) OR ROM32_INSTR_PT(196) + OR ROM32_INSTR_PT(199) OR ROM32_INSTR_PT(202) + OR ROM32_INSTR_PT(203) OR ROM32_INSTR_PT(205) + OR ROM32_INSTR_PT(206) OR ROM32_INSTR_PT(207) + OR ROM32_INSTR_PT(212) OR ROM32_INSTR_PT(216) + OR ROM32_INSTR_PT(220) OR ROM32_INSTR_PT(223) + OR ROM32_INSTR_PT(224) OR ROM32_INSTR_PT(227) + OR ROM32_INSTR_PT(232) OR ROM32_INSTR_PT(233) + OR ROM32_INSTR_PT(235) OR ROM32_INSTR_PT(238) + OR ROM32_INSTR_PT(240) OR ROM32_INSTR_PT(243) + OR ROM32_INSTR_PT(244) OR ROM32_INSTR_PT(249) + OR ROM32_INSTR_PT(251) OR ROM32_INSTR_PT(252) + OR ROM32_INSTR_PT(254) OR ROM32_INSTR_PT(256) + OR ROM32_INSTR_PT(259) OR ROM32_INSTR_PT(261) + OR ROM32_INSTR_PT(264) OR ROM32_INSTR_PT(266) + OR ROM32_INSTR_PT(267) OR ROM32_INSTR_PT(268) + OR ROM32_INSTR_PT(269) OR ROM32_INSTR_PT(271) + OR ROM32_INSTR_PT(274) OR ROM32_INSTR_PT(276) + OR ROM32_INSTR_PT(278) OR ROM32_INSTR_PT(280) + OR ROM32_INSTR_PT(281) OR ROM32_INSTR_PT(284) + OR ROM32_INSTR_PT(288) OR ROM32_INSTR_PT(290) + OR ROM32_INSTR_PT(294) OR ROM32_INSTR_PT(295) + OR ROM32_INSTR_PT(297) OR ROM32_INSTR_PT(299) + OR ROM32_INSTR_PT(301) OR ROM32_INSTR_PT(309) + OR ROM32_INSTR_PT(310) OR ROM32_INSTR_PT(323) + OR ROM32_INSTR_PT(335) OR ROM32_INSTR_PT(344) + OR ROM32_INSTR_PT(348) OR ROM32_INSTR_PT(350) + OR ROM32_INSTR_PT(361) OR ROM32_INSTR_PT(363) + OR ROM32_INSTR_PT(364) OR ROM32_INSTR_PT(367) + OR ROM32_INSTR_PT(371) OR ROM32_INSTR_PT(373) + OR ROM32_INSTR_PT(376) OR ROM32_INSTR_PT(378) + OR ROM32_INSTR_PT(379) OR ROM32_INSTR_PT(381) + OR ROM32_INSTR_PT(382) OR ROM32_INSTR_PT(383) + OR ROM32_INSTR_PT(386) OR ROM32_INSTR_PT(390) + OR ROM32_INSTR_PT(392) OR ROM32_INSTR_PT(394) + OR ROM32_INSTR_PT(395) OR ROM32_INSTR_PT(396) + OR ROM32_INSTR_PT(398) OR ROM32_INSTR_PT(400) + OR ROM32_INSTR_PT(402) OR ROM32_INSTR_PT(405) + OR ROM32_INSTR_PT(406) OR ROM32_INSTR_PT(411) + OR ROM32_INSTR_PT(416) OR ROM32_INSTR_PT(417) + OR ROM32_INSTR_PT(419) OR ROM32_INSTR_PT(422) + OR ROM32_INSTR_PT(423) OR ROM32_INSTR_PT(424) + OR ROM32_INSTR_PT(425) OR ROM32_INSTR_PT(426) + OR ROM32_INSTR_PT(430) OR ROM32_INSTR_PT(431) + OR ROM32_INSTR_PT(434) OR ROM32_INSTR_PT(435) + OR ROM32_INSTR_PT(436) OR ROM32_INSTR_PT(438) + OR ROM32_INSTR_PT(441) OR ROM32_INSTR_PT(442) + OR ROM32_INSTR_PT(452) OR ROM32_INSTR_PT(453) + OR ROM32_INSTR_PT(456) OR ROM32_INSTR_PT(458) + OR ROM32_INSTR_PT(464) OR ROM32_INSTR_PT(469) + OR ROM32_INSTR_PT(472) OR ROM32_INSTR_PT(474) + OR ROM32_INSTR_PT(475) OR ROM32_INSTR_PT(478) + OR ROM32_INSTR_PT(479) OR ROM32_INSTR_PT(481) + OR ROM32_INSTR_PT(482) OR ROM32_INSTR_PT(484) + OR ROM32_INSTR_PT(486) OR ROM32_INSTR_PT(494) + OR ROM32_INSTR_PT(503) OR ROM32_INSTR_PT(506) + OR ROM32_INSTR_PT(507) OR ROM32_INSTR_PT(511) + OR ROM32_INSTR_PT(514) OR ROM32_INSTR_PT(517) + OR ROM32_INSTR_PT(520) OR ROM32_INSTR_PT(521) + OR ROM32_INSTR_PT(522) OR ROM32_INSTR_PT(524) + OR ROM32_INSTR_PT(530) OR ROM32_INSTR_PT(531) + OR ROM32_INSTR_PT(532) OR ROM32_INSTR_PT(534) + OR ROM32_INSTR_PT(541) OR ROM32_INSTR_PT(550) + OR ROM32_INSTR_PT(551) OR ROM32_INSTR_PT(552) + OR ROM32_INSTR_PT(554) OR ROM32_INSTR_PT(555) + OR ROM32_INSTR_PT(562) OR ROM32_INSTR_PT(563) + OR ROM32_INSTR_PT(566) OR ROM32_INSTR_PT(569) + OR ROM32_INSTR_PT(570) OR ROM32_INSTR_PT(575) + OR ROM32_INSTR_PT(577) OR ROM32_INSTR_PT(579) + OR ROM32_INSTR_PT(580) OR ROM32_INSTR_PT(581) + OR ROM32_INSTR_PT(582) OR ROM32_INSTR_PT(583) + OR ROM32_INSTR_PT(584) OR ROM32_INSTR_PT(588) + OR ROM32_INSTR_PT(591) OR ROM32_INSTR_PT(599) + OR ROM32_INSTR_PT(601) OR ROM32_INSTR_PT(602) + OR ROM32_INSTR_PT(605) OR ROM32_INSTR_PT(610) + OR ROM32_INSTR_PT(615) OR ROM32_INSTR_PT(620) + OR ROM32_INSTR_PT(622) OR ROM32_INSTR_PT(626) + OR ROM32_INSTR_PT(629) OR ROM32_INSTR_PT(630) + OR ROM32_INSTR_PT(634) OR ROM32_INSTR_PT(638) + OR ROM32_INSTR_PT(639) OR ROM32_INSTR_PT(640) + OR ROM32_INSTR_PT(642) OR ROM32_INSTR_PT(643) + OR ROM32_INSTR_PT(654) OR ROM32_INSTR_PT(660) + OR ROM32_INSTR_PT(663) OR ROM32_INSTR_PT(664) + OR ROM32_INSTR_PT(666) OR ROM32_INSTR_PT(674) + OR ROM32_INSTR_PT(677) OR ROM32_INSTR_PT(684) + OR ROM32_INSTR_PT(693) OR ROM32_INSTR_PT(697) + OR ROM32_INSTR_PT(708) OR ROM32_INSTR_PT(719) + OR ROM32_INSTR_PT(720) OR ROM32_INSTR_PT(729) + OR ROM32_INSTR_PT(745) OR ROM32_INSTR_PT(755) + OR ROM32_INSTR_PT(763) OR ROM32_INSTR_PT(792) + OR ROM32_INSTR_PT(805) OR ROM32_INSTR_PT(807) + OR ROM32_INSTR_PT(812) OR ROM32_INSTR_PT(818) + OR ROM32_INSTR_PT(819) OR ROM32_INSTR_PT(823) + OR ROM32_INSTR_PT(829) OR ROM32_INSTR_PT(831) + OR ROM32_INSTR_PT(853) OR ROM32_INSTR_PT(854) + OR ROM32_INSTR_PT(855) OR ROM32_INSTR_PT(862) + OR ROM32_INSTR_PT(870) OR ROM32_INSTR_PT(878) + ); +MQQ1883:TEMPLATE(28) <= + (ROM32_INSTR_PT(3) OR ROM32_INSTR_PT(4) + OR ROM32_INSTR_PT(5) OR ROM32_INSTR_PT(8) + OR ROM32_INSTR_PT(9) OR ROM32_INSTR_PT(12) + OR ROM32_INSTR_PT(13) OR ROM32_INSTR_PT(16) + OR ROM32_INSTR_PT(17) OR ROM32_INSTR_PT(26) + OR ROM32_INSTR_PT(32) OR ROM32_INSTR_PT(37) + OR ROM32_INSTR_PT(39) OR ROM32_INSTR_PT(41) + OR ROM32_INSTR_PT(45) OR ROM32_INSTR_PT(51) + OR ROM32_INSTR_PT(52) OR ROM32_INSTR_PT(56) + OR ROM32_INSTR_PT(57) OR ROM32_INSTR_PT(59) + OR ROM32_INSTR_PT(63) OR ROM32_INSTR_PT(66) + OR ROM32_INSTR_PT(67) OR ROM32_INSTR_PT(72) + OR ROM32_INSTR_PT(73) OR ROM32_INSTR_PT(74) + OR ROM32_INSTR_PT(77) OR ROM32_INSTR_PT(83) + OR ROM32_INSTR_PT(84) OR ROM32_INSTR_PT(85) + OR ROM32_INSTR_PT(87) OR ROM32_INSTR_PT(90) + OR ROM32_INSTR_PT(93) OR ROM32_INSTR_PT(95) + OR ROM32_INSTR_PT(98) OR ROM32_INSTR_PT(99) + OR ROM32_INSTR_PT(100) OR ROM32_INSTR_PT(101) + OR ROM32_INSTR_PT(102) OR ROM32_INSTR_PT(103) + OR ROM32_INSTR_PT(106) OR ROM32_INSTR_PT(109) + OR ROM32_INSTR_PT(114) OR ROM32_INSTR_PT(115) + OR ROM32_INSTR_PT(116) OR ROM32_INSTR_PT(118) + OR ROM32_INSTR_PT(124) OR ROM32_INSTR_PT(125) + OR ROM32_INSTR_PT(127) OR ROM32_INSTR_PT(132) + OR ROM32_INSTR_PT(134) OR ROM32_INSTR_PT(135) + OR ROM32_INSTR_PT(139) OR ROM32_INSTR_PT(141) + OR ROM32_INSTR_PT(142) OR ROM32_INSTR_PT(143) + OR ROM32_INSTR_PT(148) OR ROM32_INSTR_PT(153) + OR ROM32_INSTR_PT(155) OR ROM32_INSTR_PT(158) + OR ROM32_INSTR_PT(159) OR ROM32_INSTR_PT(163) + OR ROM32_INSTR_PT(169) OR ROM32_INSTR_PT(171) + OR ROM32_INSTR_PT(179) OR ROM32_INSTR_PT(183) + OR ROM32_INSTR_PT(184) OR ROM32_INSTR_PT(192) + OR ROM32_INSTR_PT(194) OR ROM32_INSTR_PT(196) + OR ROM32_INSTR_PT(199) OR ROM32_INSTR_PT(200) + OR ROM32_INSTR_PT(202) OR ROM32_INSTR_PT(203) + OR ROM32_INSTR_PT(204) OR ROM32_INSTR_PT(207) + OR ROM32_INSTR_PT(216) OR ROM32_INSTR_PT(219) + OR ROM32_INSTR_PT(220) OR ROM32_INSTR_PT(223) + OR ROM32_INSTR_PT(227) OR ROM32_INSTR_PT(238) + OR ROM32_INSTR_PT(241) OR ROM32_INSTR_PT(243) + OR ROM32_INSTR_PT(249) OR ROM32_INSTR_PT(250) + OR ROM32_INSTR_PT(251) OR ROM32_INSTR_PT(254) + OR ROM32_INSTR_PT(256) OR ROM32_INSTR_PT(259) + OR ROM32_INSTR_PT(260) OR ROM32_INSTR_PT(261) + OR ROM32_INSTR_PT(264) OR ROM32_INSTR_PT(266) + OR ROM32_INSTR_PT(267) OR ROM32_INSTR_PT(268) + OR ROM32_INSTR_PT(269) OR ROM32_INSTR_PT(270) + OR ROM32_INSTR_PT(273) OR ROM32_INSTR_PT(280) + OR ROM32_INSTR_PT(281) OR ROM32_INSTR_PT(282) + OR ROM32_INSTR_PT(284) OR ROM32_INSTR_PT(288) + OR ROM32_INSTR_PT(290) OR ROM32_INSTR_PT(293) + OR ROM32_INSTR_PT(294) OR ROM32_INSTR_PT(295) + OR ROM32_INSTR_PT(297) OR ROM32_INSTR_PT(299) + OR ROM32_INSTR_PT(301) OR ROM32_INSTR_PT(303) + OR ROM32_INSTR_PT(306) OR ROM32_INSTR_PT(309) + OR ROM32_INSTR_PT(313) OR ROM32_INSTR_PT(318) + OR ROM32_INSTR_PT(328) OR ROM32_INSTR_PT(335) + OR ROM32_INSTR_PT(344) OR ROM32_INSTR_PT(348) + OR ROM32_INSTR_PT(350) OR ROM32_INSTR_PT(361) + OR ROM32_INSTR_PT(367) OR ROM32_INSTR_PT(371) + OR ROM32_INSTR_PT(374) OR ROM32_INSTR_PT(376) + OR ROM32_INSTR_PT(379) OR ROM32_INSTR_PT(381) + OR ROM32_INSTR_PT(382) OR ROM32_INSTR_PT(383) + OR ROM32_INSTR_PT(386) OR ROM32_INSTR_PT(390) + OR ROM32_INSTR_PT(392) OR ROM32_INSTR_PT(394) + OR ROM32_INSTR_PT(398) OR ROM32_INSTR_PT(401) + OR ROM32_INSTR_PT(402) OR ROM32_INSTR_PT(406) + OR ROM32_INSTR_PT(409) OR ROM32_INSTR_PT(411) + OR ROM32_INSTR_PT(412) OR ROM32_INSTR_PT(415) + OR ROM32_INSTR_PT(421) OR ROM32_INSTR_PT(422) + OR ROM32_INSTR_PT(423) OR ROM32_INSTR_PT(425) + OR ROM32_INSTR_PT(426) OR ROM32_INSTR_PT(428) + OR ROM32_INSTR_PT(431) OR ROM32_INSTR_PT(433) + OR ROM32_INSTR_PT(437) OR ROM32_INSTR_PT(443) + OR ROM32_INSTR_PT(451) OR ROM32_INSTR_PT(453) + OR ROM32_INSTR_PT(458) OR ROM32_INSTR_PT(464) + OR ROM32_INSTR_PT(469) OR ROM32_INSTR_PT(472) + OR ROM32_INSTR_PT(475) OR ROM32_INSTR_PT(478) + OR ROM32_INSTR_PT(479) OR ROM32_INSTR_PT(481) + OR ROM32_INSTR_PT(482) OR ROM32_INSTR_PT(484) + OR ROM32_INSTR_PT(486) OR ROM32_INSTR_PT(490) + OR ROM32_INSTR_PT(491) OR ROM32_INSTR_PT(494) + OR ROM32_INSTR_PT(495) OR ROM32_INSTR_PT(501) + OR ROM32_INSTR_PT(502) OR ROM32_INSTR_PT(503) + OR ROM32_INSTR_PT(504) OR ROM32_INSTR_PT(506) + OR ROM32_INSTR_PT(508) OR ROM32_INSTR_PT(509) + OR ROM32_INSTR_PT(514) OR ROM32_INSTR_PT(519) + OR ROM32_INSTR_PT(520) OR ROM32_INSTR_PT(522) + OR ROM32_INSTR_PT(524) OR ROM32_INSTR_PT(530) + OR ROM32_INSTR_PT(531) OR ROM32_INSTR_PT(534) + OR ROM32_INSTR_PT(544) OR ROM32_INSTR_PT(550) + OR ROM32_INSTR_PT(551) OR ROM32_INSTR_PT(552) + OR ROM32_INSTR_PT(554) OR ROM32_INSTR_PT(555) + OR ROM32_INSTR_PT(556) OR ROM32_INSTR_PT(557) + OR ROM32_INSTR_PT(562) OR ROM32_INSTR_PT(563) + OR ROM32_INSTR_PT(568) OR ROM32_INSTR_PT(578) + OR ROM32_INSTR_PT(579) OR ROM32_INSTR_PT(581) + OR ROM32_INSTR_PT(582) OR ROM32_INSTR_PT(585) + OR ROM32_INSTR_PT(588) OR ROM32_INSTR_PT(590) + OR ROM32_INSTR_PT(591) OR ROM32_INSTR_PT(595) + OR ROM32_INSTR_PT(600) OR ROM32_INSTR_PT(602) + OR ROM32_INSTR_PT(605) OR ROM32_INSTR_PT(609) + OR ROM32_INSTR_PT(612) OR ROM32_INSTR_PT(613) + OR ROM32_INSTR_PT(615) OR ROM32_INSTR_PT(621) + OR ROM32_INSTR_PT(624) OR ROM32_INSTR_PT(626) + OR ROM32_INSTR_PT(629) OR ROM32_INSTR_PT(630) + OR ROM32_INSTR_PT(639) OR ROM32_INSTR_PT(640) + OR ROM32_INSTR_PT(642) OR ROM32_INSTR_PT(643) + OR ROM32_INSTR_PT(644) OR ROM32_INSTR_PT(654) + OR ROM32_INSTR_PT(660) OR ROM32_INSTR_PT(664) + OR ROM32_INSTR_PT(666) OR ROM32_INSTR_PT(674) + OR ROM32_INSTR_PT(677) OR ROM32_INSTR_PT(697) + OR ROM32_INSTR_PT(708) OR ROM32_INSTR_PT(719) + OR ROM32_INSTR_PT(728) OR ROM32_INSTR_PT(729) + OR ROM32_INSTR_PT(731) OR ROM32_INSTR_PT(736) + OR ROM32_INSTR_PT(751) OR ROM32_INSTR_PT(753) + OR ROM32_INSTR_PT(755) OR ROM32_INSTR_PT(762) + OR ROM32_INSTR_PT(763) OR ROM32_INSTR_PT(770) + OR ROM32_INSTR_PT(792) OR ROM32_INSTR_PT(805) + OR ROM32_INSTR_PT(812) OR ROM32_INSTR_PT(819) + OR ROM32_INSTR_PT(829) OR ROM32_INSTR_PT(854) + OR ROM32_INSTR_PT(855) OR ROM32_INSTR_PT(862) + OR ROM32_INSTR_PT(870) OR ROM32_INSTR_PT(878) + ); +MQQ1884:TEMPLATE(29) <= + (ROM32_INSTR_PT(3) OR ROM32_INSTR_PT(4) + OR ROM32_INSTR_PT(5) OR ROM32_INSTR_PT(6) + OR ROM32_INSTR_PT(7) OR ROM32_INSTR_PT(8) + OR ROM32_INSTR_PT(9) OR ROM32_INSTR_PT(10) + OR ROM32_INSTR_PT(13) OR ROM32_INSTR_PT(14) + OR ROM32_INSTR_PT(16) OR ROM32_INSTR_PT(17) + OR ROM32_INSTR_PT(23) OR ROM32_INSTR_PT(26) + OR ROM32_INSTR_PT(27) OR ROM32_INSTR_PT(30) + OR ROM32_INSTR_PT(37) OR ROM32_INSTR_PT(41) + OR ROM32_INSTR_PT(49) OR ROM32_INSTR_PT(51) + OR ROM32_INSTR_PT(52) OR ROM32_INSTR_PT(53) + OR ROM32_INSTR_PT(59) OR ROM32_INSTR_PT(63) + OR ROM32_INSTR_PT(66) OR ROM32_INSTR_PT(67) + OR ROM32_INSTR_PT(73) OR ROM32_INSTR_PT(74) + OR ROM32_INSTR_PT(77) OR ROM32_INSTR_PT(78) + OR ROM32_INSTR_PT(84) OR ROM32_INSTR_PT(87) + OR ROM32_INSTR_PT(90) OR ROM32_INSTR_PT(93) + OR ROM32_INSTR_PT(97) OR ROM32_INSTR_PT(99) + OR ROM32_INSTR_PT(100) OR ROM32_INSTR_PT(103) + OR ROM32_INSTR_PT(106) OR ROM32_INSTR_PT(114) + OR ROM32_INSTR_PT(115) OR ROM32_INSTR_PT(116) + OR ROM32_INSTR_PT(117) OR ROM32_INSTR_PT(118) + OR ROM32_INSTR_PT(124) OR ROM32_INSTR_PT(127) + OR ROM32_INSTR_PT(130) OR ROM32_INSTR_PT(131) + OR ROM32_INSTR_PT(132) OR ROM32_INSTR_PT(134) + OR ROM32_INSTR_PT(135) OR ROM32_INSTR_PT(139) + OR ROM32_INSTR_PT(148) OR ROM32_INSTR_PT(153) + OR ROM32_INSTR_PT(159) OR ROM32_INSTR_PT(164) + OR ROM32_INSTR_PT(169) OR ROM32_INSTR_PT(171) + OR ROM32_INSTR_PT(172) OR ROM32_INSTR_PT(181) + OR ROM32_INSTR_PT(183) OR ROM32_INSTR_PT(184) + OR ROM32_INSTR_PT(187) OR ROM32_INSTR_PT(194) + OR ROM32_INSTR_PT(200) OR ROM32_INSTR_PT(204) + OR ROM32_INSTR_PT(205) OR ROM32_INSTR_PT(212) + OR ROM32_INSTR_PT(216) OR ROM32_INSTR_PT(219) + OR ROM32_INSTR_PT(220) OR ROM32_INSTR_PT(223) + OR ROM32_INSTR_PT(227) OR ROM32_INSTR_PT(229) + OR ROM32_INSTR_PT(232) OR ROM32_INSTR_PT(235) + OR ROM32_INSTR_PT(238) OR ROM32_INSTR_PT(241) + OR ROM32_INSTR_PT(244) OR ROM32_INSTR_PT(250) + OR ROM32_INSTR_PT(251) OR ROM32_INSTR_PT(256) + OR ROM32_INSTR_PT(259) OR ROM32_INSTR_PT(260) + OR ROM32_INSTR_PT(261) OR ROM32_INSTR_PT(264) + OR ROM32_INSTR_PT(267) OR ROM32_INSTR_PT(269) + OR ROM32_INSTR_PT(270) OR ROM32_INSTR_PT(271) + OR ROM32_INSTR_PT(273) OR ROM32_INSTR_PT(274) + OR ROM32_INSTR_PT(275) OR ROM32_INSTR_PT(280) + OR ROM32_INSTR_PT(281) OR ROM32_INSTR_PT(282) + OR ROM32_INSTR_PT(284) OR ROM32_INSTR_PT(288) + OR ROM32_INSTR_PT(289) OR ROM32_INSTR_PT(290) + OR ROM32_INSTR_PT(293) OR ROM32_INSTR_PT(295) + OR ROM32_INSTR_PT(297) OR ROM32_INSTR_PT(299) + OR ROM32_INSTR_PT(301) OR ROM32_INSTR_PT(303) + OR ROM32_INSTR_PT(306) OR ROM32_INSTR_PT(309) + OR ROM32_INSTR_PT(310) OR ROM32_INSTR_PT(313) + OR ROM32_INSTR_PT(318) OR ROM32_INSTR_PT(322) + OR ROM32_INSTR_PT(323) OR ROM32_INSTR_PT(328) + OR ROM32_INSTR_PT(337) OR ROM32_INSTR_PT(348) + OR ROM32_INSTR_PT(361) OR ROM32_INSTR_PT(371) + OR ROM32_INSTR_PT(374) OR ROM32_INSTR_PT(378) + OR ROM32_INSTR_PT(379) OR ROM32_INSTR_PT(381) + OR ROM32_INSTR_PT(383) OR ROM32_INSTR_PT(387) + OR ROM32_INSTR_PT(390) OR ROM32_INSTR_PT(392) + OR ROM32_INSTR_PT(393) OR ROM32_INSTR_PT(398) + OR ROM32_INSTR_PT(400) OR ROM32_INSTR_PT(401) + OR ROM32_INSTR_PT(406) OR ROM32_INSTR_PT(409) + OR ROM32_INSTR_PT(411) OR ROM32_INSTR_PT(412) + OR ROM32_INSTR_PT(415) OR ROM32_INSTR_PT(416) + OR ROM32_INSTR_PT(419) OR ROM32_INSTR_PT(421) + OR ROM32_INSTR_PT(425) OR ROM32_INSTR_PT(426) + OR ROM32_INSTR_PT(428) OR ROM32_INSTR_PT(433) + OR ROM32_INSTR_PT(434) OR ROM32_INSTR_PT(435) + OR ROM32_INSTR_PT(436) OR ROM32_INSTR_PT(437) + OR ROM32_INSTR_PT(438) OR ROM32_INSTR_PT(441) + OR ROM32_INSTR_PT(443) OR ROM32_INSTR_PT(451) + OR ROM32_INSTR_PT(452) OR ROM32_INSTR_PT(465) + OR ROM32_INSTR_PT(475) OR ROM32_INSTR_PT(478) + OR ROM32_INSTR_PT(479) OR ROM32_INSTR_PT(481) + OR ROM32_INSTR_PT(482) OR ROM32_INSTR_PT(490) + OR ROM32_INSTR_PT(494) OR ROM32_INSTR_PT(495) + OR ROM32_INSTR_PT(501) OR ROM32_INSTR_PT(502) + OR ROM32_INSTR_PT(506) OR ROM32_INSTR_PT(507) + OR ROM32_INSTR_PT(508) OR ROM32_INSTR_PT(509) + OR ROM32_INSTR_PT(511) OR ROM32_INSTR_PT(517) + OR ROM32_INSTR_PT(519) OR ROM32_INSTR_PT(520) + OR ROM32_INSTR_PT(522) OR ROM32_INSTR_PT(524) + OR ROM32_INSTR_PT(530) OR ROM32_INSTR_PT(531) + OR ROM32_INSTR_PT(532) OR ROM32_INSTR_PT(534) + OR ROM32_INSTR_PT(535) OR ROM32_INSTR_PT(543) + OR ROM32_INSTR_PT(544) OR ROM32_INSTR_PT(547) + OR ROM32_INSTR_PT(550) OR ROM32_INSTR_PT(552) + OR ROM32_INSTR_PT(554) OR ROM32_INSTR_PT(556) + OR ROM32_INSTR_PT(557) OR ROM32_INSTR_PT(558) + OR ROM32_INSTR_PT(562) OR ROM32_INSTR_PT(563) + OR ROM32_INSTR_PT(566) OR ROM32_INSTR_PT(568) + OR ROM32_INSTR_PT(570) OR ROM32_INSTR_PT(574) + OR ROM32_INSTR_PT(575) OR ROM32_INSTR_PT(578) + OR ROM32_INSTR_PT(579) OR ROM32_INSTR_PT(580) + OR ROM32_INSTR_PT(581) OR ROM32_INSTR_PT(582) + OR ROM32_INSTR_PT(584) OR ROM32_INSTR_PT(585) + OR ROM32_INSTR_PT(587) OR ROM32_INSTR_PT(590) + OR ROM32_INSTR_PT(595) OR ROM32_INSTR_PT(599) + OR ROM32_INSTR_PT(600) OR ROM32_INSTR_PT(601) + OR ROM32_INSTR_PT(602) OR ROM32_INSTR_PT(609) + OR ROM32_INSTR_PT(612) OR ROM32_INSTR_PT(622) + OR ROM32_INSTR_PT(624) OR ROM32_INSTR_PT(625) + OR ROM32_INSTR_PT(626) OR ROM32_INSTR_PT(629) + OR ROM32_INSTR_PT(630) OR ROM32_INSTR_PT(634) + OR ROM32_INSTR_PT(638) OR ROM32_INSTR_PT(639) + OR ROM32_INSTR_PT(640) OR ROM32_INSTR_PT(642) + OR ROM32_INSTR_PT(644) OR ROM32_INSTR_PT(663) + OR ROM32_INSTR_PT(664) OR ROM32_INSTR_PT(666) + OR ROM32_INSTR_PT(677) OR ROM32_INSTR_PT(684) + OR ROM32_INSTR_PT(693) OR ROM32_INSTR_PT(697) + OR ROM32_INSTR_PT(719) OR ROM32_INSTR_PT(726) + OR ROM32_INSTR_PT(728) OR ROM32_INSTR_PT(736) + OR ROM32_INSTR_PT(751) OR ROM32_INSTR_PT(753) + OR ROM32_INSTR_PT(755) OR ROM32_INSTR_PT(762) + OR ROM32_INSTR_PT(770) OR ROM32_INSTR_PT(792) + OR ROM32_INSTR_PT(829) OR ROM32_INSTR_PT(845) + OR ROM32_INSTR_PT(853) OR ROM32_INSTR_PT(855) + OR ROM32_INSTR_PT(862) OR ROM32_INSTR_PT(870) + ); +MQQ1885:TEMPLATE(30) <= + (ROM32_INSTR_PT(3) OR ROM32_INSTR_PT(4) + OR ROM32_INSTR_PT(6) OR ROM32_INSTR_PT(8) + OR ROM32_INSTR_PT(9) OR ROM32_INSTR_PT(13) + OR ROM32_INSTR_PT(16) OR ROM32_INSTR_PT(17) + OR ROM32_INSTR_PT(20) OR ROM32_INSTR_PT(26) + OR ROM32_INSTR_PT(32) OR ROM32_INSTR_PT(37) + OR ROM32_INSTR_PT(41) OR ROM32_INSTR_PT(45) + OR ROM32_INSTR_PT(49) OR ROM32_INSTR_PT(50) + OR ROM32_INSTR_PT(51) OR ROM32_INSTR_PT(52) + OR ROM32_INSTR_PT(55) OR ROM32_INSTR_PT(59) + OR ROM32_INSTR_PT(63) OR ROM32_INSTR_PT(66) + OR ROM32_INSTR_PT(67) OR ROM32_INSTR_PT(73) + OR ROM32_INSTR_PT(74) OR ROM32_INSTR_PT(77) + OR ROM32_INSTR_PT(78) OR ROM32_INSTR_PT(79) + OR ROM32_INSTR_PT(80) OR ROM32_INSTR_PT(84) + OR ROM32_INSTR_PT(85) OR ROM32_INSTR_PT(87) + OR ROM32_INSTR_PT(90) OR ROM32_INSTR_PT(92) + OR ROM32_INSTR_PT(99) OR ROM32_INSTR_PT(100) + OR ROM32_INSTR_PT(103) OR ROM32_INSTR_PT(105) + OR ROM32_INSTR_PT(106) OR ROM32_INSTR_PT(111) + OR ROM32_INSTR_PT(114) OR ROM32_INSTR_PT(115) + OR ROM32_INSTR_PT(116) OR ROM32_INSTR_PT(117) + OR ROM32_INSTR_PT(118) OR ROM32_INSTR_PT(119) + OR ROM32_INSTR_PT(122) OR ROM32_INSTR_PT(124) + OR ROM32_INSTR_PT(127) OR ROM32_INSTR_PT(130) + OR ROM32_INSTR_PT(134) OR ROM32_INSTR_PT(135) + OR ROM32_INSTR_PT(139) OR ROM32_INSTR_PT(142) + OR ROM32_INSTR_PT(148) OR ROM32_INSTR_PT(153) + OR ROM32_INSTR_PT(169) OR ROM32_INSTR_PT(171) + OR ROM32_INSTR_PT(176) OR ROM32_INSTR_PT(179) + OR ROM32_INSTR_PT(180) OR ROM32_INSTR_PT(181) + OR ROM32_INSTR_PT(183) OR ROM32_INSTR_PT(184) + OR ROM32_INSTR_PT(186) OR ROM32_INSTR_PT(194) + OR ROM32_INSTR_PT(200) OR ROM32_INSTR_PT(204) + OR ROM32_INSTR_PT(209) OR ROM32_INSTR_PT(214) + OR ROM32_INSTR_PT(215) OR ROM32_INSTR_PT(216) + OR ROM32_INSTR_PT(219) OR ROM32_INSTR_PT(220) + OR ROM32_INSTR_PT(222) OR ROM32_INSTR_PT(223) + OR ROM32_INSTR_PT(224) OR ROM32_INSTR_PT(227) + OR ROM32_INSTR_PT(229) OR ROM32_INSTR_PT(233) + OR ROM32_INSTR_PT(238) OR ROM32_INSTR_PT(241) + OR ROM32_INSTR_PT(250) OR ROM32_INSTR_PT(254) + OR ROM32_INSTR_PT(256) OR ROM32_INSTR_PT(259) + OR ROM32_INSTR_PT(260) OR ROM32_INSTR_PT(261) + OR ROM32_INSTR_PT(264) OR ROM32_INSTR_PT(267) + OR ROM32_INSTR_PT(269) OR ROM32_INSTR_PT(270) + OR ROM32_INSTR_PT(272) OR ROM32_INSTR_PT(273) + OR ROM32_INSTR_PT(274) OR ROM32_INSTR_PT(278) + OR ROM32_INSTR_PT(280) OR ROM32_INSTR_PT(282) + OR ROM32_INSTR_PT(283) OR ROM32_INSTR_PT(288) + OR ROM32_INSTR_PT(293) OR ROM32_INSTR_PT(295) + OR ROM32_INSTR_PT(297) OR ROM32_INSTR_PT(299) + OR ROM32_INSTR_PT(301) OR ROM32_INSTR_PT(303) + OR ROM32_INSTR_PT(306) OR ROM32_INSTR_PT(313) + OR ROM32_INSTR_PT(318) OR ROM32_INSTR_PT(321) + OR ROM32_INSTR_PT(328) OR ROM32_INSTR_PT(335) + OR ROM32_INSTR_PT(343) OR ROM32_INSTR_PT(345) + OR ROM32_INSTR_PT(346) OR ROM32_INSTR_PT(348) + OR ROM32_INSTR_PT(356) OR ROM32_INSTR_PT(361) + OR ROM32_INSTR_PT(364) OR ROM32_INSTR_PT(366) + OR ROM32_INSTR_PT(368) OR ROM32_INSTR_PT(371) + OR ROM32_INSTR_PT(373) OR ROM32_INSTR_PT(374) + OR ROM32_INSTR_PT(379) OR ROM32_INSTR_PT(383) + OR ROM32_INSTR_PT(390) OR ROM32_INSTR_PT(392) + OR ROM32_INSTR_PT(393) OR ROM32_INSTR_PT(396) + OR ROM32_INSTR_PT(400) OR ROM32_INSTR_PT(401) + OR ROM32_INSTR_PT(406) OR ROM32_INSTR_PT(409) + OR ROM32_INSTR_PT(411) OR ROM32_INSTR_PT(412) + OR ROM32_INSTR_PT(415) OR ROM32_INSTR_PT(421) + OR ROM32_INSTR_PT(424) OR ROM32_INSTR_PT(426) + OR ROM32_INSTR_PT(428) OR ROM32_INSTR_PT(431) + OR ROM32_INSTR_PT(433) OR ROM32_INSTR_PT(437) + OR ROM32_INSTR_PT(441) OR ROM32_INSTR_PT(443) + OR ROM32_INSTR_PT(451) OR ROM32_INSTR_PT(459) + OR ROM32_INSTR_PT(461) OR ROM32_INSTR_PT(475) + OR ROM32_INSTR_PT(476) OR ROM32_INSTR_PT(478) + OR ROM32_INSTR_PT(479) OR ROM32_INSTR_PT(481) + OR ROM32_INSTR_PT(482) OR ROM32_INSTR_PT(490) + OR ROM32_INSTR_PT(494) OR ROM32_INSTR_PT(495) + OR ROM32_INSTR_PT(501) OR ROM32_INSTR_PT(502) + OR ROM32_INSTR_PT(506) OR ROM32_INSTR_PT(507) + OR ROM32_INSTR_PT(508) OR ROM32_INSTR_PT(509) + OR ROM32_INSTR_PT(519) OR ROM32_INSTR_PT(520) + OR ROM32_INSTR_PT(521) OR ROM32_INSTR_PT(522) + OR ROM32_INSTR_PT(524) OR ROM32_INSTR_PT(534) + OR ROM32_INSTR_PT(539) OR ROM32_INSTR_PT(544) + OR ROM32_INSTR_PT(550) OR ROM32_INSTR_PT(552) + OR ROM32_INSTR_PT(554) OR ROM32_INSTR_PT(555) + OR ROM32_INSTR_PT(556) OR ROM32_INSTR_PT(557) + OR ROM32_INSTR_PT(558) OR ROM32_INSTR_PT(562) + OR ROM32_INSTR_PT(568) OR ROM32_INSTR_PT(570) + OR ROM32_INSTR_PT(575) OR ROM32_INSTR_PT(578) + OR ROM32_INSTR_PT(581) OR ROM32_INSTR_PT(582) + OR ROM32_INSTR_PT(583) OR ROM32_INSTR_PT(585) + OR ROM32_INSTR_PT(587) OR ROM32_INSTR_PT(588) + OR ROM32_INSTR_PT(590) OR ROM32_INSTR_PT(595) + OR ROM32_INSTR_PT(600) OR ROM32_INSTR_PT(602) + OR ROM32_INSTR_PT(603) OR ROM32_INSTR_PT(607) + OR ROM32_INSTR_PT(609) OR ROM32_INSTR_PT(612) + OR ROM32_INSTR_PT(615) OR ROM32_INSTR_PT(624) + OR ROM32_INSTR_PT(626) OR ROM32_INSTR_PT(629) + OR ROM32_INSTR_PT(630) OR ROM32_INSTR_PT(639) + OR ROM32_INSTR_PT(640) OR ROM32_INSTR_PT(642) + OR ROM32_INSTR_PT(644) OR ROM32_INSTR_PT(666) + OR ROM32_INSTR_PT(677) OR ROM32_INSTR_PT(683) + OR ROM32_INSTR_PT(685) OR ROM32_INSTR_PT(689) + OR ROM32_INSTR_PT(692) OR ROM32_INSTR_PT(711) + OR ROM32_INSTR_PT(719) OR ROM32_INSTR_PT(720) + OR ROM32_INSTR_PT(726) OR ROM32_INSTR_PT(728) + OR ROM32_INSTR_PT(729) OR ROM32_INSTR_PT(736) + OR ROM32_INSTR_PT(751) OR ROM32_INSTR_PT(753) + OR ROM32_INSTR_PT(755) OR ROM32_INSTR_PT(762) + OR ROM32_INSTR_PT(763) OR ROM32_INSTR_PT(770) + OR ROM32_INSTR_PT(807) OR ROM32_INSTR_PT(823) + OR ROM32_INSTR_PT(831) OR ROM32_INSTR_PT(845) + OR ROM32_INSTR_PT(855) OR ROM32_INSTR_PT(862) + OR ROM32_INSTR_PT(870)); +MQQ1886:TEMPLATE(31) <= + (ROM32_INSTR_PT(31) OR ROM32_INSTR_PT(62) + OR ROM32_INSTR_PT(81) OR ROM32_INSTR_PT(95) + OR ROM32_INSTR_PT(104) OR ROM32_INSTR_PT(145) + OR ROM32_INSTR_PT(147) OR ROM32_INSTR_PT(150) + OR ROM32_INSTR_PT(162) OR ROM32_INSTR_PT(175) + OR ROM32_INSTR_PT(185) OR ROM32_INSTR_PT(187) + OR ROM32_INSTR_PT(208) OR ROM32_INSTR_PT(210) + OR ROM32_INSTR_PT(225) OR ROM32_INSTR_PT(228) + OR ROM32_INSTR_PT(230) OR ROM32_INSTR_PT(232) + OR ROM32_INSTR_PT(235) OR ROM32_INSTR_PT(245) + OR ROM32_INSTR_PT(251) OR ROM32_INSTR_PT(279) + OR ROM32_INSTR_PT(285) OR ROM32_INSTR_PT(292) + OR ROM32_INSTR_PT(302) OR ROM32_INSTR_PT(307) + OR ROM32_INSTR_PT(312) OR ROM32_INSTR_PT(325) + OR ROM32_INSTR_PT(329) OR ROM32_INSTR_PT(338) + OR ROM32_INSTR_PT(378) OR ROM32_INSTR_PT(398) + OR ROM32_INSTR_PT(416) OR ROM32_INSTR_PT(419) + OR ROM32_INSTR_PT(463) OR ROM32_INSTR_PT(489) + OR ROM32_INSTR_PT(591) OR ROM32_INSTR_PT(629) + OR ROM32_INSTR_PT(632) OR ROM32_INSTR_PT(640) + OR ROM32_INSTR_PT(641) OR ROM32_INSTR_PT(653) + OR ROM32_INSTR_PT(672) OR ROM32_INSTR_PT(720) + OR ROM32_INSTR_PT(728) OR ROM32_INSTR_PT(751) + OR ROM32_INSTR_PT(752) OR ROM32_INSTR_PT(753) + OR ROM32_INSTR_PT(759) OR ROM32_INSTR_PT(774) + OR ROM32_INSTR_PT(787) OR ROM32_INSTR_PT(803) + OR ROM32_INSTR_PT(807) OR ROM32_INSTR_PT(823) + ); +MQQ1887:UCODE_END <= + (ROM32_INSTR_PT(198) OR ROM32_INSTR_PT(201) + OR ROM32_INSTR_PT(213) OR ROM32_INSTR_PT(384) + OR ROM32_INSTR_PT(438) OR ROM32_INSTR_PT(440) + OR ROM32_INSTR_PT(450) OR ROM32_INSTR_PT(513) + OR ROM32_INSTR_PT(515) OR ROM32_INSTR_PT(528) + OR ROM32_INSTR_PT(541) OR ROM32_INSTR_PT(548) + OR ROM32_INSTR_PT(553) OR ROM32_INSTR_PT(559) + OR ROM32_INSTR_PT(567) OR ROM32_INSTR_PT(573) + OR ROM32_INSTR_PT(576) OR ROM32_INSTR_PT(580) + OR ROM32_INSTR_PT(589) OR ROM32_INSTR_PT(599) + OR ROM32_INSTR_PT(600) OR ROM32_INSTR_PT(601) + OR ROM32_INSTR_PT(619) OR ROM32_INSTR_PT(663) + OR ROM32_INSTR_PT(668) OR ROM32_INSTR_PT(674) + OR ROM32_INSTR_PT(688) OR ROM32_INSTR_PT(694) + OR ROM32_INSTR_PT(699) OR ROM32_INSTR_PT(702) + OR ROM32_INSTR_PT(709) OR ROM32_INSTR_PT(714) + OR ROM32_INSTR_PT(733) OR ROM32_INSTR_PT(778) + OR ROM32_INSTR_PT(784) OR ROM32_INSTR_PT(812) + OR ROM32_INSTR_PT(818) OR ROM32_INSTR_PT(819) + OR ROM32_INSTR_PT(821) OR ROM32_INSTR_PT(824) + OR ROM32_INSTR_PT(840) OR ROM32_INSTR_PT(843) + OR ROM32_INSTR_PT(844) OR ROM32_INSTR_PT(847) + OR ROM32_INSTR_PT(853) OR ROM32_INSTR_PT(878) + ); +MQQ1888:UCODE_END_EARLY <= + (ROM32_INSTR_PT(372) OR ROM32_INSTR_PT(389) + OR ROM32_INSTR_PT(650) OR ROM32_INSTR_PT(673) + OR ROM32_INSTR_PT(681) OR ROM32_INSTR_PT(687) + OR ROM32_INSTR_PT(725) OR ROM32_INSTR_PT(734) + OR ROM32_INSTR_PT(750) OR ROM32_INSTR_PT(754) + OR ROM32_INSTR_PT(781) OR ROM32_INSTR_PT(782) + OR ROM32_INSTR_PT(794) OR ROM32_INSTR_PT(796) + OR ROM32_INSTR_PT(797) OR ROM32_INSTR_PT(802) + OR ROM32_INSTR_PT(808) OR ROM32_INSTR_PT(813) + OR ROM32_INSTR_PT(820) OR ROM32_INSTR_PT(827) + OR ROM32_INSTR_PT(873)); +MQQ1889:LOOP_BEGIN <= + (ROM32_INSTR_PT(24) OR ROM32_INSTR_PT(55) + OR ROM32_INSTR_PT(105) OR ROM32_INSTR_PT(124) + OR ROM32_INSTR_PT(147) OR ROM32_INSTR_PT(211) + OR ROM32_INSTR_PT(228) OR ROM32_INSTR_PT(230) + OR ROM32_INSTR_PT(239) OR ROM32_INSTR_PT(245) + OR ROM32_INSTR_PT(253) OR ROM32_INSTR_PT(304) + OR ROM32_INSTR_PT(308) OR ROM32_INSTR_PT(314) + OR ROM32_INSTR_PT(321) OR ROM32_INSTR_PT(345) + OR ROM32_INSTR_PT(366) OR ROM32_INSTR_PT(374) + OR ROM32_INSTR_PT(407) OR ROM32_INSTR_PT(408) + OR ROM32_INSTR_PT(432) OR ROM32_INSTR_PT(448) + OR ROM32_INSTR_PT(460) OR ROM32_INSTR_PT(483) + OR ROM32_INSTR_PT(490) OR ROM32_INSTR_PT(495) + OR ROM32_INSTR_PT(544) OR ROM32_INSTR_PT(557) + OR ROM32_INSTR_PT(571) OR ROM32_INSTR_PT(586) + OR ROM32_INSTR_PT(604)); +MQQ1890:LOOP_END <= + (ROM32_INSTR_PT(149) OR ROM32_INSTR_PT(156) + OR ROM32_INSTR_PT(372) OR ROM32_INSTR_PT(466) + OR ROM32_INSTR_PT(492) OR ROM32_INSTR_PT(500) + OR ROM32_INSTR_PT(564) OR ROM32_INSTR_PT(637) + OR ROM32_INSTR_PT(648) OR ROM32_INSTR_PT(655) + OR ROM32_INSTR_PT(679) OR ROM32_INSTR_PT(696) + OR ROM32_INSTR_PT(743) OR ROM32_INSTR_PT(769) + OR ROM32_INSTR_PT(773) OR ROM32_INSTR_PT(783) + OR ROM32_INSTR_PT(793) OR ROM32_INSTR_PT(802) + OR ROM32_INSTR_PT(809) OR ROM32_INSTR_PT(810) + OR ROM32_INSTR_PT(848) OR ROM32_INSTR_PT(861) + OR ROM32_INSTR_PT(874)); +MQQ1891:COUNT_SRC(0) <= + (ROM32_INSTR_PT(75) OR ROM32_INSTR_PT(744) + OR ROM32_INSTR_PT(761) OR ROM32_INSTR_PT(875) + OR ROM32_INSTR_PT(879) OR ROM32_INSTR_PT(880) + OR ROM32_INSTR_PT(883) OR ROM32_INSTR_PT(890) + OR ROM32_INSTR_PT(891) OR ROM32_INSTR_PT(892) + ); +MQQ1892:COUNT_SRC(1) <= + (ROM32_INSTR_PT(838) OR ROM32_INSTR_PT(875) + OR ROM32_INSTR_PT(880) OR ROM32_INSTR_PT(882) + OR ROM32_INSTR_PT(886) OR ROM32_INSTR_PT(891) + OR ROM32_INSTR_PT(892)); +MQQ1893:COUNT_SRC(2) <= + (ROM32_INSTR_PT(695) OR ROM32_INSTR_PT(744) + OR ROM32_INSTR_PT(761) OR ROM32_INSTR_PT(828) + OR ROM32_INSTR_PT(838) OR ROM32_INSTR_PT(890) + OR ROM32_INSTR_PT(891) OR ROM32_INSTR_PT(892) + ); +MQQ1894:EXTRT <= + (ROM32_INSTR_PT(3) OR ROM32_INSTR_PT(19) + OR ROM32_INSTR_PT(21) OR ROM32_INSTR_PT(25) + OR ROM32_INSTR_PT(40) OR ROM32_INSTR_PT(44) + OR ROM32_INSTR_PT(47) OR ROM32_INSTR_PT(69) + OR ROM32_INSTR_PT(72) OR ROM32_INSTR_PT(82) + OR ROM32_INSTR_PT(91) OR ROM32_INSTR_PT(94) + OR ROM32_INSTR_PT(95) OR ROM32_INSTR_PT(108) + OR ROM32_INSTR_PT(116) OR ROM32_INSTR_PT(121) + OR ROM32_INSTR_PT(131) OR ROM32_INSTR_PT(133) + OR ROM32_INSTR_PT(136) OR ROM32_INSTR_PT(139) + OR ROM32_INSTR_PT(151) OR ROM32_INSTR_PT(152) + OR ROM32_INSTR_PT(161) OR ROM32_INSTR_PT(164) + OR ROM32_INSTR_PT(168) OR ROM32_INSTR_PT(188) + OR ROM32_INSTR_PT(190) OR ROM32_INSTR_PT(197) + OR ROM32_INSTR_PT(221) OR ROM32_INSTR_PT(234) + OR ROM32_INSTR_PT(236) OR ROM32_INSTR_PT(247) + OR ROM32_INSTR_PT(251) OR ROM32_INSTR_PT(262) + OR ROM32_INSTR_PT(265) OR ROM32_INSTR_PT(266) + OR ROM32_INSTR_PT(277) OR ROM32_INSTR_PT(281) + OR ROM32_INSTR_PT(284) OR ROM32_INSTR_PT(296) + OR ROM32_INSTR_PT(300) OR ROM32_INSTR_PT(315) + OR ROM32_INSTR_PT(316) OR ROM32_INSTR_PT(317) + OR ROM32_INSTR_PT(327) OR ROM32_INSTR_PT(328) + OR ROM32_INSTR_PT(333) OR ROM32_INSTR_PT(336) + OR ROM32_INSTR_PT(349) OR ROM32_INSTR_PT(353) + OR ROM32_INSTR_PT(354) OR ROM32_INSTR_PT(380) + OR ROM32_INSTR_PT(381) OR ROM32_INSTR_PT(397) + OR ROM32_INSTR_PT(410) OR ROM32_INSTR_PT(415) + OR ROM32_INSTR_PT(420) OR ROM32_INSTR_PT(437) + OR ROM32_INSTR_PT(451) OR ROM32_INSTR_PT(457) + OR ROM32_INSTR_PT(461) OR ROM32_INSTR_PT(483) + OR ROM32_INSTR_PT(493) OR ROM32_INSTR_PT(525) + OR ROM32_INSTR_PT(529) OR ROM32_INSTR_PT(533) + OR ROM32_INSTR_PT(536) OR ROM32_INSTR_PT(587) + OR ROM32_INSTR_PT(591) OR ROM32_INSTR_PT(592) + OR ROM32_INSTR_PT(594) OR ROM32_INSTR_PT(623) + OR ROM32_INSTR_PT(627) OR ROM32_INSTR_PT(636) + OR ROM32_INSTR_PT(645) OR ROM32_INSTR_PT(656) + OR ROM32_INSTR_PT(665) OR ROM32_INSTR_PT(667) + OR ROM32_INSTR_PT(669) OR ROM32_INSTR_PT(671) + OR ROM32_INSTR_PT(686) OR ROM32_INSTR_PT(701) + OR ROM32_INSTR_PT(707) OR ROM32_INSTR_PT(712) + OR ROM32_INSTR_PT(721) OR ROM32_INSTR_PT(722) + OR ROM32_INSTR_PT(723) OR ROM32_INSTR_PT(730) + OR ROM32_INSTR_PT(735) OR ROM32_INSTR_PT(739) + OR ROM32_INSTR_PT(742) OR ROM32_INSTR_PT(746) + OR ROM32_INSTR_PT(756) OR ROM32_INSTR_PT(757) + OR ROM32_INSTR_PT(758) OR ROM32_INSTR_PT(760) + OR ROM32_INSTR_PT(764) OR ROM32_INSTR_PT(765) + OR ROM32_INSTR_PT(766) OR ROM32_INSTR_PT(767) + OR ROM32_INSTR_PT(768) OR ROM32_INSTR_PT(771) + OR ROM32_INSTR_PT(772) OR ROM32_INSTR_PT(775) + OR ROM32_INSTR_PT(776) OR ROM32_INSTR_PT(777) + OR ROM32_INSTR_PT(788) OR ROM32_INSTR_PT(789) + OR ROM32_INSTR_PT(791) OR ROM32_INSTR_PT(792) + OR ROM32_INSTR_PT(798) OR ROM32_INSTR_PT(804) + OR ROM32_INSTR_PT(806) OR ROM32_INSTR_PT(811) + OR ROM32_INSTR_PT(816) OR ROM32_INSTR_PT(826) + OR ROM32_INSTR_PT(833) OR ROM32_INSTR_PT(834) + OR ROM32_INSTR_PT(835) OR ROM32_INSTR_PT(837) + OR ROM32_INSTR_PT(841) OR ROM32_INSTR_PT(849) + OR ROM32_INSTR_PT(856) OR ROM32_INSTR_PT(858) + OR ROM32_INSTR_PT(859) OR ROM32_INSTR_PT(860) + OR ROM32_INSTR_PT(862) OR ROM32_INSTR_PT(863) + OR ROM32_INSTR_PT(864) OR ROM32_INSTR_PT(865) + OR ROM32_INSTR_PT(866) OR ROM32_INSTR_PT(867) + OR ROM32_INSTR_PT(870) OR ROM32_INSTR_PT(876) + OR ROM32_INSTR_PT(884) OR ROM32_INSTR_PT(885) + ); +MQQ1895:EXTS1 <= + (ROM32_INSTR_PT(3) OR ROM32_INSTR_PT(19) + OR ROM32_INSTR_PT(21) OR ROM32_INSTR_PT(28) + OR ROM32_INSTR_PT(36) OR ROM32_INSTR_PT(47) + OR ROM32_INSTR_PT(58) OR ROM32_INSTR_PT(82) + OR ROM32_INSTR_PT(91) OR ROM32_INSTR_PT(100) + OR ROM32_INSTR_PT(107) OR ROM32_INSTR_PT(135) + OR ROM32_INSTR_PT(136) OR ROM32_INSTR_PT(137) + OR ROM32_INSTR_PT(157) OR ROM32_INSTR_PT(167) + OR ROM32_INSTR_PT(193) OR ROM32_INSTR_PT(197) + OR ROM32_INSTR_PT(212) OR ROM32_INSTR_PT(226) + OR ROM32_INSTR_PT(231) OR ROM32_INSTR_PT(236) + OR ROM32_INSTR_PT(263) OR ROM32_INSTR_PT(277) + OR ROM32_INSTR_PT(286) OR ROM32_INSTR_PT(293) + OR ROM32_INSTR_PT(296) OR ROM32_INSTR_PT(298) + OR ROM32_INSTR_PT(315) OR ROM32_INSTR_PT(316) + OR ROM32_INSTR_PT(317) OR ROM32_INSTR_PT(324) + OR ROM32_INSTR_PT(327) OR ROM32_INSTR_PT(328) + OR ROM32_INSTR_PT(330) OR ROM32_INSTR_PT(336) + OR ROM32_INSTR_PT(346) OR ROM32_INSTR_PT(369) + OR ROM32_INSTR_PT(380) OR ROM32_INSTR_PT(397) + OR ROM32_INSTR_PT(410) OR ROM32_INSTR_PT(414) + OR ROM32_INSTR_PT(438) OR ROM32_INSTR_PT(447) + OR ROM32_INSTR_PT(457) OR ROM32_INSTR_PT(462) + OR ROM32_INSTR_PT(470) OR ROM32_INSTR_PT(488) + OR ROM32_INSTR_PT(493) OR ROM32_INSTR_PT(495) + OR ROM32_INSTR_PT(499) OR ROM32_INSTR_PT(526) + OR ROM32_INSTR_PT(542) OR ROM32_INSTR_PT(589) + OR ROM32_INSTR_PT(594) OR ROM32_INSTR_PT(599) + OR ROM32_INSTR_PT(623) OR ROM32_INSTR_PT(627) + OR ROM32_INSTR_PT(636) OR ROM32_INSTR_PT(645) + OR ROM32_INSTR_PT(651) OR ROM32_INSTR_PT(656) + OR ROM32_INSTR_PT(667) OR ROM32_INSTR_PT(669) + OR ROM32_INSTR_PT(670) OR ROM32_INSTR_PT(675) + OR ROM32_INSTR_PT(686) OR ROM32_INSTR_PT(691) + OR ROM32_INSTR_PT(692) OR ROM32_INSTR_PT(701) + OR ROM32_INSTR_PT(706) OR ROM32_INSTR_PT(707) + OR ROM32_INSTR_PT(710) OR ROM32_INSTR_PT(716) + OR ROM32_INSTR_PT(721) OR ROM32_INSTR_PT(722) + OR ROM32_INSTR_PT(730) OR ROM32_INSTR_PT(733) + OR ROM32_INSTR_PT(739) OR ROM32_INSTR_PT(741) + OR ROM32_INSTR_PT(742) OR ROM32_INSTR_PT(746) + OR ROM32_INSTR_PT(756) OR ROM32_INSTR_PT(757) + OR ROM32_INSTR_PT(758) OR ROM32_INSTR_PT(760) + OR ROM32_INSTR_PT(764) OR ROM32_INSTR_PT(765) + OR ROM32_INSTR_PT(767) OR ROM32_INSTR_PT(768) + OR ROM32_INSTR_PT(771) OR ROM32_INSTR_PT(775) + OR ROM32_INSTR_PT(776) OR ROM32_INSTR_PT(777) + OR ROM32_INSTR_PT(779) OR ROM32_INSTR_PT(788) + OR ROM32_INSTR_PT(789) OR ROM32_INSTR_PT(791) + OR ROM32_INSTR_PT(798) OR ROM32_INSTR_PT(801) + OR ROM32_INSTR_PT(804) OR ROM32_INSTR_PT(806) + OR ROM32_INSTR_PT(811) OR ROM32_INSTR_PT(812) + OR ROM32_INSTR_PT(816) OR ROM32_INSTR_PT(824) + OR ROM32_INSTR_PT(826) OR ROM32_INSTR_PT(830) + OR ROM32_INSTR_PT(832) OR ROM32_INSTR_PT(833) + OR ROM32_INSTR_PT(835) OR ROM32_INSTR_PT(837) + OR ROM32_INSTR_PT(841) OR ROM32_INSTR_PT(842) + OR ROM32_INSTR_PT(843) OR ROM32_INSTR_PT(846) + OR ROM32_INSTR_PT(847) OR ROM32_INSTR_PT(849) + OR ROM32_INSTR_PT(850) OR ROM32_INSTR_PT(852) + OR ROM32_INSTR_PT(858) OR ROM32_INSTR_PT(859) + OR ROM32_INSTR_PT(863) OR ROM32_INSTR_PT(865) + OR ROM32_INSTR_PT(867) OR ROM32_INSTR_PT(868) + OR ROM32_INSTR_PT(877) OR ROM32_INSTR_PT(878) + OR ROM32_INSTR_PT(888)); +MQQ1896:EXTS2 <= + (ROM32_INSTR_PT(21) OR ROM32_INSTR_PT(25) + OR ROM32_INSTR_PT(36) OR ROM32_INSTR_PT(44) + OR ROM32_INSTR_PT(47) OR ROM32_INSTR_PT(91) + OR ROM32_INSTR_PT(116) OR ROM32_INSTR_PT(136) + OR ROM32_INSTR_PT(137) OR ROM32_INSTR_PT(139) + OR ROM32_INSTR_PT(152) OR ROM32_INSTR_PT(167) + OR ROM32_INSTR_PT(178) OR ROM32_INSTR_PT(188) + OR ROM32_INSTR_PT(191) OR ROM32_INSTR_PT(212) + OR ROM32_INSTR_PT(217) OR ROM32_INSTR_PT(236) + OR ROM32_INSTR_PT(295) OR ROM32_INSTR_PT(317) + OR ROM32_INSTR_PT(327) OR ROM32_INSTR_PT(328) + OR ROM32_INSTR_PT(330) OR ROM32_INSTR_PT(333) + OR ROM32_INSTR_PT(336) OR ROM32_INSTR_PT(341) + OR ROM32_INSTR_PT(344) OR ROM32_INSTR_PT(346) + OR ROM32_INSTR_PT(354) OR ROM32_INSTR_PT(356) + OR ROM32_INSTR_PT(369) OR ROM32_INSTR_PT(375) + OR ROM32_INSTR_PT(381) OR ROM32_INSTR_PT(393) + OR ROM32_INSTR_PT(410) OR ROM32_INSTR_PT(415) + OR ROM32_INSTR_PT(429) OR ROM32_INSTR_PT(437) + OR ROM32_INSTR_PT(438) OR ROM32_INSTR_PT(447) + OR ROM32_INSTR_PT(451) OR ROM32_INSTR_PT(457) + OR ROM32_INSTR_PT(470) OR ROM32_INSTR_PT(493) + OR ROM32_INSTR_PT(518) OR ROM32_INSTR_PT(526) + OR ROM32_INSTR_PT(530) OR ROM32_INSTR_PT(579) + OR ROM32_INSTR_PT(587) OR ROM32_INSTR_PT(594) + OR ROM32_INSTR_PT(599) OR ROM32_INSTR_PT(624) + OR ROM32_INSTR_PT(627) OR ROM32_INSTR_PT(628) + OR ROM32_INSTR_PT(651) OR ROM32_INSTR_PT(656) + OR ROM32_INSTR_PT(692) OR ROM32_INSTR_PT(706) + OR ROM32_INSTR_PT(710) OR ROM32_INSTR_PT(714) + OR ROM32_INSTR_PT(721) OR ROM32_INSTR_PT(722) + OR ROM32_INSTR_PT(723) OR ROM32_INSTR_PT(730) + OR ROM32_INSTR_PT(735) OR ROM32_INSTR_PT(737) + OR ROM32_INSTR_PT(739) OR ROM32_INSTR_PT(742) + OR ROM32_INSTR_PT(746) OR ROM32_INSTR_PT(749) + OR ROM32_INSTR_PT(756) OR ROM32_INSTR_PT(760) + OR ROM32_INSTR_PT(764) OR ROM32_INSTR_PT(767) + OR ROM32_INSTR_PT(770) OR ROM32_INSTR_PT(779) + OR ROM32_INSTR_PT(789) OR ROM32_INSTR_PT(791) + OR ROM32_INSTR_PT(812) OR ROM32_INSTR_PT(819) + OR ROM32_INSTR_PT(822) OR ROM32_INSTR_PT(824) + OR ROM32_INSTR_PT(835) OR ROM32_INSTR_PT(841) + OR ROM32_INSTR_PT(842) OR ROM32_INSTR_PT(850) + OR ROM32_INSTR_PT(853) OR ROM32_INSTR_PT(858) + OR ROM32_INSTR_PT(863) OR ROM32_INSTR_PT(865) + OR ROM32_INSTR_PT(867) OR ROM32_INSTR_PT(868) + OR ROM32_INSTR_PT(876) OR ROM32_INSTR_PT(878) + OR ROM32_INSTR_PT(885)); +MQQ1897:EXTS3 <= + (ROM32_INSTR_PT(47) OR ROM32_INSTR_PT(58) + OR ROM32_INSTR_PT(126) OR ROM32_INSTR_PT(133) + OR ROM32_INSTR_PT(135) OR ROM32_INSTR_PT(168) + OR ROM32_INSTR_PT(190) OR ROM32_INSTR_PT(226) + OR ROM32_INSTR_PT(263) OR ROM32_INSTR_PT(293) + OR ROM32_INSTR_PT(318) OR ROM32_INSTR_PT(333) + OR ROM32_INSTR_PT(346) OR ROM32_INSTR_PT(381) + OR ROM32_INSTR_PT(397) OR ROM32_INSTR_PT(409) + OR ROM32_INSTR_PT(467) OR ROM32_INSTR_PT(487) + OR ROM32_INSTR_PT(526) OR ROM32_INSTR_PT(623) + OR ROM32_INSTR_PT(692) OR ROM32_INSTR_PT(707) + OR ROM32_INSTR_PT(710) OR ROM32_INSTR_PT(717) + OR ROM32_INSTR_PT(730) OR ROM32_INSTR_PT(771) + OR ROM32_INSTR_PT(792) OR ROM32_INSTR_PT(804) + OR ROM32_INSTR_PT(826) OR ROM32_INSTR_PT(837) + OR ROM32_INSTR_PT(866) OR ROM32_INSTR_PT(887) + ); +MQQ1898:SEL0_5 <= + (ROM32_INSTR_PT(651) OR ROM32_INSTR_PT(714) + ); +MQQ1899:SEL6_10(0) <= + (ROM32_INSTR_PT(40) OR ROM32_INSTR_PT(72) + OR ROM32_INSTR_PT(83) OR ROM32_INSTR_PT(94) + OR ROM32_INSTR_PT(108) OR ROM32_INSTR_PT(201) + OR ROM32_INSTR_PT(212) OR ROM32_INSTR_PT(266) + OR ROM32_INSTR_PT(384) OR ROM32_INSTR_PT(438) + OR ROM32_INSTR_PT(440) OR ROM32_INSTR_PT(450) + OR ROM32_INSTR_PT(512) OR ROM32_INSTR_PT(518) + OR ROM32_INSTR_PT(528) OR ROM32_INSTR_PT(529) + OR ROM32_INSTR_PT(536) OR ROM32_INSTR_PT(541) + OR ROM32_INSTR_PT(548) OR ROM32_INSTR_PT(559) + OR ROM32_INSTR_PT(566) OR ROM32_INSTR_PT(572) + OR ROM32_INSTR_PT(580) OR ROM32_INSTR_PT(599) + OR ROM32_INSTR_PT(601) OR ROM32_INSTR_PT(618) + OR ROM32_INSTR_PT(661) OR ROM32_INSTR_PT(693) + OR ROM32_INSTR_PT(702) OR ROM32_INSTR_PT(784) + OR ROM32_INSTR_PT(818) OR ROM32_INSTR_PT(853) + ); +MQQ1900:SEL6_10(1) <= + (ROM32_INSTR_PT(1) OR ROM32_INSTR_PT(2) + OR ROM32_INSTR_PT(40) OR ROM32_INSTR_PT(54) + OR ROM32_INSTR_PT(71) OR ROM32_INSTR_PT(72) + OR ROM32_INSTR_PT(80) OR ROM32_INSTR_PT(83) + OR ROM32_INSTR_PT(94) OR ROM32_INSTR_PT(108) + OR ROM32_INSTR_PT(121) OR ROM32_INSTR_PT(178) + OR ROM32_INSTR_PT(182) OR ROM32_INSTR_PT(262) + OR ROM32_INSTR_PT(266) OR ROM32_INSTR_PT(284) + OR ROM32_INSTR_PT(334) OR ROM32_INSTR_PT(344) + OR ROM32_INSTR_PT(346) OR ROM32_INSTR_PT(347) + OR ROM32_INSTR_PT(351) OR ROM32_INSTR_PT(356) + OR ROM32_INSTR_PT(375) OR ROM32_INSTR_PT(403) + OR ROM32_INSTR_PT(427) OR ROM32_INSTR_PT(432) + OR ROM32_INSTR_PT(455) OR ROM32_INSTR_PT(461) + OR ROM32_INSTR_PT(483) OR ROM32_INSTR_PT(485) + OR ROM32_INSTR_PT(529) OR ROM32_INSTR_PT(530) + OR ROM32_INSTR_PT(536) OR ROM32_INSTR_PT(539) + OR ROM32_INSTR_PT(579) OR ROM32_INSTR_PT(592) + OR ROM32_INSTR_PT(651) OR ROM32_INSTR_PT(658) + OR ROM32_INSTR_PT(691) OR ROM32_INSTR_PT(692) + OR ROM32_INSTR_PT(703) OR ROM32_INSTR_PT(710) + OR ROM32_INSTR_PT(714) OR ROM32_INSTR_PT(716) + OR ROM32_INSTR_PT(723) OR ROM32_INSTR_PT(724) + OR ROM32_INSTR_PT(732) OR ROM32_INSTR_PT(856) + OR ROM32_INSTR_PT(862) OR ROM32_INSTR_PT(870) + ); +MQQ1901:SEL11_15(0) <= + (ROM32_INSTR_PT(36) OR ROM32_INSTR_PT(133) + OR ROM32_INSTR_PT(193) OR ROM32_INSTR_PT(231) + OR ROM32_INSTR_PT(246) OR ROM32_INSTR_PT(286) + OR ROM32_INSTR_PT(369) OR ROM32_INSTR_PT(381) + OR ROM32_INSTR_PT(434) OR ROM32_INSTR_PT(444) + OR ROM32_INSTR_PT(462) OR ROM32_INSTR_PT(589) + OR ROM32_INSTR_PT(663) OR ROM32_INSTR_PT(733) + OR ROM32_INSTR_PT(792) OR ROM32_INSTR_PT(825) + ); +MQQ1902:SEL11_15(1) <= + (ROM32_INSTR_PT(22) OR ROM32_INSTR_PT(25) + OR ROM32_INSTR_PT(36) OR ROM32_INSTR_PT(44) + OR ROM32_INSTR_PT(48) OR ROM32_INSTR_PT(61) + OR ROM32_INSTR_PT(64) OR ROM32_INSTR_PT(65) + OR ROM32_INSTR_PT(69) OR ROM32_INSTR_PT(86) + OR ROM32_INSTR_PT(95) OR ROM32_INSTR_PT(106) + OR ROM32_INSTR_PT(116) OR ROM32_INSTR_PT(129) + OR ROM32_INSTR_PT(131) OR ROM32_INSTR_PT(139) + OR ROM32_INSTR_PT(140) OR ROM32_INSTR_PT(151) + OR ROM32_INSTR_PT(160) OR ROM32_INSTR_PT(164) + OR ROM32_INSTR_PT(188) OR ROM32_INSTR_PT(190) + OR ROM32_INSTR_PT(193) OR ROM32_INSTR_PT(201) + OR ROM32_INSTR_PT(221) OR ROM32_INSTR_PT(231) + OR ROM32_INSTR_PT(234) OR ROM32_INSTR_PT(247) + OR ROM32_INSTR_PT(251) OR ROM32_INSTR_PT(265) + OR ROM32_INSTR_PT(281) OR ROM32_INSTR_PT(286) + OR ROM32_INSTR_PT(300) OR ROM32_INSTR_PT(351) + OR ROM32_INSTR_PT(354) OR ROM32_INSTR_PT(369) + OR ROM32_INSTR_PT(384) OR ROM32_INSTR_PT(393) + OR ROM32_INSTR_PT(415) OR ROM32_INSTR_PT(420) + OR ROM32_INSTR_PT(429) OR ROM32_INSTR_PT(434) + OR ROM32_INSTR_PT(437) OR ROM32_INSTR_PT(440) + OR ROM32_INSTR_PT(450) OR ROM32_INSTR_PT(451) + OR ROM32_INSTR_PT(462) OR ROM32_INSTR_PT(518) + OR ROM32_INSTR_PT(523) OR ROM32_INSTR_PT(528) + OR ROM32_INSTR_PT(545) OR ROM32_INSTR_PT(548) + OR ROM32_INSTR_PT(559) OR ROM32_INSTR_PT(572) + OR ROM32_INSTR_PT(587) OR ROM32_INSTR_PT(589) + OR ROM32_INSTR_PT(591) OR ROM32_INSTR_PT(601) + OR ROM32_INSTR_PT(618) OR ROM32_INSTR_PT(624) + OR ROM32_INSTR_PT(631) OR ROM32_INSTR_PT(663) + OR ROM32_INSTR_PT(665) OR ROM32_INSTR_PT(693) + OR ROM32_INSTR_PT(702) OR ROM32_INSTR_PT(713) + OR ROM32_INSTR_PT(714) OR ROM32_INSTR_PT(727) + OR ROM32_INSTR_PT(780) OR ROM32_INSTR_PT(784) + OR ROM32_INSTR_PT(801) OR ROM32_INSTR_PT(812) + OR ROM32_INSTR_PT(819) OR ROM32_INSTR_PT(824) + OR ROM32_INSTR_PT(839) OR ROM32_INSTR_PT(843) + OR ROM32_INSTR_PT(847) OR ROM32_INSTR_PT(878) + ); +MQQ1903:SEL16_20(0) <= + (ROM32_INSTR_PT(5) OR ROM32_INSTR_PT(133) + OR ROM32_INSTR_PT(194) OR ROM32_INSTR_PT(254) + OR ROM32_INSTR_PT(256) OR ROM32_INSTR_PT(353) + OR ROM32_INSTR_PT(444) OR ROM32_INSTR_PT(533) + OR ROM32_INSTR_PT(792) OR ROM32_INSTR_PT(825) + ); +MQQ1904:SEL16_20(1) <= + (ROM32_INSTR_PT(3) OR ROM32_INSTR_PT(11) + OR ROM32_INSTR_PT(15) OR ROM32_INSTR_PT(28) + OR ROM32_INSTR_PT(40) OR ROM32_INSTR_PT(46) + OR ROM32_INSTR_PT(48) OR ROM32_INSTR_PT(72) + OR ROM32_INSTR_PT(76) OR ROM32_INSTR_PT(83) + OR ROM32_INSTR_PT(88) OR ROM32_INSTR_PT(94) + OR ROM32_INSTR_PT(100) OR ROM32_INSTR_PT(108) + OR ROM32_INSTR_PT(126) OR ROM32_INSTR_PT(131) + OR ROM32_INSTR_PT(133) OR ROM32_INSTR_PT(135) + OR ROM32_INSTR_PT(140) OR ROM32_INSTR_PT(161) + OR ROM32_INSTR_PT(164) OR ROM32_INSTR_PT(201) + OR ROM32_INSTR_PT(204) OR ROM32_INSTR_PT(226) + OR ROM32_INSTR_PT(248) OR ROM32_INSTR_PT(265) + OR ROM32_INSTR_PT(266) OR ROM32_INSTR_PT(277) + OR ROM32_INSTR_PT(293) OR ROM32_INSTR_PT(298) + OR ROM32_INSTR_PT(318) OR ROM32_INSTR_PT(320) + OR ROM32_INSTR_PT(334) OR ROM32_INSTR_PT(351) + OR ROM32_INSTR_PT(353) OR ROM32_INSTR_PT(359) + OR ROM32_INSTR_PT(384) OR ROM32_INSTR_PT(397) + OR ROM32_INSTR_PT(409) OR ROM32_INSTR_PT(420) + OR ROM32_INSTR_PT(443) OR ROM32_INSTR_PT(444) + OR ROM32_INSTR_PT(450) OR ROM32_INSTR_PT(467) + OR ROM32_INSTR_PT(487) OR ROM32_INSTR_PT(495) + OR ROM32_INSTR_PT(510) OR ROM32_INSTR_PT(523) + OR ROM32_INSTR_PT(528) OR ROM32_INSTR_PT(529) + OR ROM32_INSTR_PT(540) OR ROM32_INSTR_PT(548) + OR ROM32_INSTR_PT(559) OR ROM32_INSTR_PT(560) + OR ROM32_INSTR_PT(566) OR ROM32_INSTR_PT(571) + OR ROM32_INSTR_PT(572) OR ROM32_INSTR_PT(600) + OR ROM32_INSTR_PT(601) OR ROM32_INSTR_PT(609) + OR ROM32_INSTR_PT(618) OR ROM32_INSTR_PT(631) + OR ROM32_INSTR_PT(649) OR ROM32_INSTR_PT(661) + OR ROM32_INSTR_PT(693) OR ROM32_INSTR_PT(702) + OR ROM32_INSTR_PT(713) OR ROM32_INSTR_PT(766) + OR ROM32_INSTR_PT(784) OR ROM32_INSTR_PT(792) + OR ROM32_INSTR_PT(825) OR ROM32_INSTR_PT(836) + ); +MQQ1905:SEL21_25(0) <= + (ROM32_INSTR_PT(197)); +MQQ1906:SEL21_25(1) <= + (ROM32_INSTR_PT(15) OR ROM32_INSTR_PT(28) + OR ROM32_INSTR_PT(46) OR ROM32_INSTR_PT(48) + OR ROM32_INSTR_PT(65) OR ROM32_INSTR_PT(76) + OR ROM32_INSTR_PT(88) OR ROM32_INSTR_PT(140) + OR ROM32_INSTR_PT(201) OR ROM32_INSTR_PT(226) + OR ROM32_INSTR_PT(265) OR ROM32_INSTR_PT(320) + OR ROM32_INSTR_PT(351) OR ROM32_INSTR_PT(359) + OR ROM32_INSTR_PT(384) OR ROM32_INSTR_PT(420) + OR ROM32_INSTR_PT(450) OR ROM32_INSTR_PT(467) + OR ROM32_INSTR_PT(512) OR ROM32_INSTR_PT(528) + OR ROM32_INSTR_PT(540) OR ROM32_INSTR_PT(548) + OR ROM32_INSTR_PT(559) OR ROM32_INSTR_PT(571) + OR ROM32_INSTR_PT(572) OR ROM32_INSTR_PT(631) + OR ROM32_INSTR_PT(651) OR ROM32_INSTR_PT(702) + OR ROM32_INSTR_PT(714) OR ROM32_INSTR_PT(727) + OR ROM32_INSTR_PT(784)); +MQQ1907:SEL26_30 <= + (ROM32_INSTR_PT(15) OR ROM32_INSTR_PT(28) + OR ROM32_INSTR_PT(46) OR ROM32_INSTR_PT(48) + OR ROM32_INSTR_PT(65) OR ROM32_INSTR_PT(76) + OR ROM32_INSTR_PT(88) OR ROM32_INSTR_PT(140) + OR ROM32_INSTR_PT(201) OR ROM32_INSTR_PT(226) + OR ROM32_INSTR_PT(265) OR ROM32_INSTR_PT(320) + OR ROM32_INSTR_PT(351) OR ROM32_INSTR_PT(359) + OR ROM32_INSTR_PT(384) OR ROM32_INSTR_PT(420) + OR ROM32_INSTR_PT(450) OR ROM32_INSTR_PT(467) + OR ROM32_INSTR_PT(512) OR ROM32_INSTR_PT(528) + OR ROM32_INSTR_PT(540) OR ROM32_INSTR_PT(548) + OR ROM32_INSTR_PT(559) OR ROM32_INSTR_PT(571) + OR ROM32_INSTR_PT(572) OR ROM32_INSTR_PT(631) + OR ROM32_INSTR_PT(651) OR ROM32_INSTR_PT(702) + OR ROM32_INSTR_PT(714) OR ROM32_INSTR_PT(727) + OR ROM32_INSTR_PT(784)); +MQQ1908:SEL31 <= + (ROM32_INSTR_PT(15) OR ROM32_INSTR_PT(28) + OR ROM32_INSTR_PT(61) OR ROM32_INSTR_PT(65) + OR ROM32_INSTR_PT(76) OR ROM32_INSTR_PT(88) + OR ROM32_INSTR_PT(140) OR ROM32_INSTR_PT(201) + OR ROM32_INSTR_PT(265) OR ROM32_INSTR_PT(320) + OR ROM32_INSTR_PT(346) OR ROM32_INSTR_PT(351) + OR ROM32_INSTR_PT(356) OR ROM32_INSTR_PT(359) + OR ROM32_INSTR_PT(384) OR ROM32_INSTR_PT(420) + OR ROM32_INSTR_PT(450) OR ROM32_INSTR_PT(467) + OR ROM32_INSTR_PT(540) OR ROM32_INSTR_PT(541) + OR ROM32_INSTR_PT(559) OR ROM32_INSTR_PT(560) + OR ROM32_INSTR_PT(572) OR ROM32_INSTR_PT(631) + OR ROM32_INSTR_PT(651) OR ROM32_INSTR_PT(692) + OR ROM32_INSTR_PT(702) OR ROM32_INSTR_PT(710) + OR ROM32_INSTR_PT(714) OR ROM32_INSTR_PT(784) + OR ROM32_INSTR_PT(818)); +MQQ1909:CR_BF2FXM <= + (ROM32_INSTR_PT(713)); +MQQ1910:SKIP_COND <= + (ROM32_INSTR_PT(21) OR ROM32_INSTR_PT(32) + OR ROM32_INSTR_PT(82) OR ROM32_INSTR_PT(89) + OR ROM32_INSTR_PT(91) OR ROM32_INSTR_PT(127) + OR ROM32_INSTR_PT(217) OR ROM32_INSTR_PT(295) + OR ROM32_INSTR_PT(327) OR ROM32_INSTR_PT(328) + OR ROM32_INSTR_PT(341) OR ROM32_INSTR_PT(366) + OR ROM32_INSTR_PT(485) OR ROM32_INSTR_PT(662) + OR ROM32_INSTR_PT(667) OR ROM32_INSTR_PT(676) + OR ROM32_INSTR_PT(682) OR ROM32_INSTR_PT(722) + OR ROM32_INSTR_PT(736) OR ROM32_INSTR_PT(737) + OR ROM32_INSTR_PT(738) OR ROM32_INSTR_PT(739) + OR ROM32_INSTR_PT(740) OR ROM32_INSTR_PT(742) + OR ROM32_INSTR_PT(747) OR ROM32_INSTR_PT(748) + OR ROM32_INSTR_PT(749) OR ROM32_INSTR_PT(758) + OR ROM32_INSTR_PT(770) OR ROM32_INSTR_PT(775) + OR ROM32_INSTR_PT(776) OR ROM32_INSTR_PT(777) + OR ROM32_INSTR_PT(786) OR ROM32_INSTR_PT(788) + OR ROM32_INSTR_PT(789) OR ROM32_INSTR_PT(800) + OR ROM32_INSTR_PT(811) OR ROM32_INSTR_PT(814) + OR ROM32_INSTR_PT(815) OR ROM32_INSTR_PT(816) + OR ROM32_INSTR_PT(822) OR ROM32_INSTR_PT(842) + OR ROM32_INSTR_PT(858) OR ROM32_INSTR_PT(865) + ); +MQQ1911:SKIP_ZERO <= + (ROM32_INSTR_PT(318) OR ROM32_INSTR_PT(349) + OR ROM32_INSTR_PT(432) OR ROM32_INSTR_PT(457) + OR ROM32_INSTR_PT(483) OR ROM32_INSTR_PT(671) + OR ROM32_INSTR_PT(712)); +MQQ1912:LOOP_ADDR(0) <= + (ROM32_INSTR_PT(19) OR ROM32_INSTR_PT(36) + OR ROM32_INSTR_PT(58) OR ROM32_INSTR_PT(315) + OR ROM32_INSTR_PT(316) OR ROM32_INSTR_PT(349) + OR ROM32_INSTR_PT(369) OR ROM32_INSTR_PT(457) + OR ROM32_INSTR_PT(623) OR ROM32_INSTR_PT(627) + OR ROM32_INSTR_PT(656) OR ROM32_INSTR_PT(671) + OR ROM32_INSTR_PT(712) OR ROM32_INSTR_PT(721) + OR ROM32_INSTR_PT(730) OR ROM32_INSTR_PT(742) + OR ROM32_INSTR_PT(760) OR ROM32_INSTR_PT(771) + OR ROM32_INSTR_PT(777) OR ROM32_INSTR_PT(798) + OR ROM32_INSTR_PT(837) OR ROM32_INSTR_PT(863) + OR ROM32_INSTR_PT(865)); +MQQ1913:LOOP_ADDR(1) <= + (ROM32_INSTR_PT(315) OR ROM32_INSTR_PT(525) + OR ROM32_INSTR_PT(623) OR ROM32_INSTR_PT(627) + OR ROM32_INSTR_PT(656) OR ROM32_INSTR_PT(712) + OR ROM32_INSTR_PT(721) OR ROM32_INSTR_PT(730) + OR ROM32_INSTR_PT(742) OR ROM32_INSTR_PT(777) + OR ROM32_INSTR_PT(837) OR ROM32_INSTR_PT(858) + OR ROM32_INSTR_PT(865)); +MQQ1914:LOOP_ADDR(2) <= + (ROM32_INSTR_PT(58) OR ROM32_INSTR_PT(457) + OR ROM32_INSTR_PT(717) OR ROM32_INSTR_PT(740) + OR ROM32_INSTR_PT(747) OR ROM32_INSTR_PT(887) + ); +MQQ1915:LOOP_ADDR(3) <= + (ROM32_INSTR_PT(19) OR ROM32_INSTR_PT(58) + OR ROM32_INSTR_PT(136) OR ROM32_INSTR_PT(316) + OR ROM32_INSTR_PT(414) OR ROM32_INSTR_PT(457) + OR ROM32_INSTR_PT(623) OR ROM32_INSTR_PT(706) + OR ROM32_INSTR_PT(722) OR ROM32_INSTR_PT(730) + OR ROM32_INSTR_PT(756) OR ROM32_INSTR_PT(760) + OR ROM32_INSTR_PT(771) OR ROM32_INSTR_PT(798) + OR ROM32_INSTR_PT(837) OR ROM32_INSTR_PT(864) + OR ROM32_INSTR_PT(865)); +MQQ1916:LOOP_ADDR(4) <= + (ROM32_INSTR_PT(19) OR ROM32_INSTR_PT(36) + OR ROM32_INSTR_PT(58) OR ROM32_INSTR_PT(136) + OR ROM32_INSTR_PT(315) OR ROM32_INSTR_PT(349) + OR ROM32_INSTR_PT(369) OR ROM32_INSTR_PT(410) + OR ROM32_INSTR_PT(457) OR ROM32_INSTR_PT(470) + OR ROM32_INSTR_PT(717) OR ROM32_INSTR_PT(740) + OR ROM32_INSTR_PT(742) OR ROM32_INSTR_PT(747) + OR ROM32_INSTR_PT(777) OR ROM32_INSTR_PT(837) + OR ROM32_INSTR_PT(863) OR ROM32_INSTR_PT(865) + ); +MQQ1917:LOOP_ADDR(5) <= + (ROM32_INSTR_PT(36) OR ROM32_INSTR_PT(58) + OR ROM32_INSTR_PT(315) OR ROM32_INSTR_PT(623) + OR ROM32_INSTR_PT(656) OR ROM32_INSTR_PT(671) + OR ROM32_INSTR_PT(721) OR ROM32_INSTR_PT(722) + OR ROM32_INSTR_PT(735) OR ROM32_INSTR_PT(756) + OR ROM32_INSTR_PT(764) OR ROM32_INSTR_PT(771) + OR ROM32_INSTR_PT(798) OR ROM32_INSTR_PT(863) + ); +MQQ1918:LOOP_ADDR(6) <= + (ROM32_INSTR_PT(36) OR ROM32_INSTR_PT(136) + OR ROM32_INSTR_PT(315) OR ROM32_INSTR_PT(316) + OR ROM32_INSTR_PT(369) OR ROM32_INSTR_PT(380) + OR ROM32_INSTR_PT(457) OR ROM32_INSTR_PT(470) + OR ROM32_INSTR_PT(623) OR ROM32_INSTR_PT(671) + OR ROM32_INSTR_PT(721) OR ROM32_INSTR_PT(722) + OR ROM32_INSTR_PT(740) OR ROM32_INSTR_PT(742) + OR ROM32_INSTR_PT(756) OR ROM32_INSTR_PT(760) + OR ROM32_INSTR_PT(837) OR ROM32_INSTR_PT(858) + OR ROM32_INSTR_PT(887)); +MQQ1919:LOOP_ADDR(7) <= + (ROM32_INSTR_PT(19) OR ROM32_INSTR_PT(36) + OR ROM32_INSTR_PT(58) OR ROM32_INSTR_PT(316) + OR ROM32_INSTR_PT(349) OR ROM32_INSTR_PT(380) + OR ROM32_INSTR_PT(410) OR ROM32_INSTR_PT(414) + OR ROM32_INSTR_PT(623) OR ROM32_INSTR_PT(627) + OR ROM32_INSTR_PT(721) OR ROM32_INSTR_PT(722) + OR ROM32_INSTR_PT(730) OR ROM32_INSTR_PT(740) + OR ROM32_INSTR_PT(742) OR ROM32_INSTR_PT(765) + OR ROM32_INSTR_PT(771) OR ROM32_INSTR_PT(826) + OR ROM32_INSTR_PT(865)); +MQQ1920:LOOP_ADDR(8) <= + (ROM32_INSTR_PT(136) OR ROM32_INSTR_PT(410) + OR ROM32_INSTR_PT(414) OR ROM32_INSTR_PT(457) + OR ROM32_INSTR_PT(470) OR ROM32_INSTR_PT(488) + OR ROM32_INSTR_PT(706) OR ROM32_INSTR_PT(722) + OR ROM32_INSTR_PT(730) OR ROM32_INSTR_PT(740) + OR ROM32_INSTR_PT(742) OR ROM32_INSTR_PT(747) + OR ROM32_INSTR_PT(756) OR ROM32_INSTR_PT(863) + OR ROM32_INSTR_PT(887)); +MQQ1921:LOOP_ADDR(9) <= + (ROM32_INSTR_PT(19) OR ROM32_INSTR_PT(36) + OR ROM32_INSTR_PT(58) OR ROM32_INSTR_PT(191) + OR ROM32_INSTR_PT(316) OR ROM32_INSTR_PT(349) + OR ROM32_INSTR_PT(369) OR ROM32_INSTR_PT(525) + OR ROM32_INSTR_PT(623) OR ROM32_INSTR_PT(671) + OR ROM32_INSTR_PT(717) OR ROM32_INSTR_PT(721) + OR ROM32_INSTR_PT(760) OR ROM32_INSTR_PT(771) + OR ROM32_INSTR_PT(777) OR ROM32_INSTR_PT(837) + OR ROM32_INSTR_PT(887)); +MQQ1922:LOOP_INIT(0) <= + (ROM32_INSTR_PT(168) OR ROM32_INSTR_PT(236) + OR ROM32_INSTR_PT(315) OR ROM32_INSTR_PT(366) + OR ROM32_INSTR_PT(397) OR ROM32_INSTR_PT(686) + OR ROM32_INSTR_PT(717) OR ROM32_INSTR_PT(776) + OR ROM32_INSTR_PT(788) OR ROM32_INSTR_PT(811) + OR ROM32_INSTR_PT(816) OR ROM32_INSTR_PT(864) + ); +MQQ1923:LOOP_INIT(1) <= + (ROM32_INSTR_PT(893)); +MQQ1924:LOOP_INIT(2) <= + (ROM32_INSTR_PT(168) OR ROM32_INSTR_PT(776) + OR ROM32_INSTR_PT(811)); +MQQ1925:EP <= + (ROM32_INSTR_PT(44) OR ROM32_INSTR_PT(61) + OR ROM32_INSTR_PT(116) OR ROM32_INSTR_PT(135) + OR ROM32_INSTR_PT(277) OR ROM32_INSTR_PT(293) + OR ROM32_INSTR_PT(354) OR ROM32_INSTR_PT(393) + OR ROM32_INSTR_PT(397) OR ROM32_INSTR_PT(429) + OR ROM32_INSTR_PT(437) OR ROM32_INSTR_PT(443) + OR ROM32_INSTR_PT(523) OR ROM32_INSTR_PT(560) + ); + +end generate; +rom_addr_d <= rom_addr; +rom_data <= template & ucode_end & ucode_end_early & loop_begin & loop_end & count_src & extRT & extS1 & extS2 & extS3 & + sel0_5 & sel6_10 & sel11_15 & sel16_20 & sel21_25 & sel26_30 & sel31 & cr_bf2fxm & skip_cond & skip_zero & loop_addr & loop_init & ep; +rom_addr_latch: tri_rlmreg_p + generic map (width => rom_addr_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rom_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(rom_addr_offset to rom_addr_offset + rom_addr_l2'length-1), + scout => sov(rom_addr_offset to rom_addr_offset + rom_addr_l2'length-1), + din => rom_addr_d, + dout => rom_addr_l2); +siv(0 TO scan_right) <= sov(1 to scan_right) & scan_in; +scan_out <= sov(0); +END IUQ_UC_ROM; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/mmq.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/mmq.vhdl new file mode 100644 index 0000000..b3c7a4a --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/mmq.vhdl @@ -0,0 +1,4316 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; +use ieee.std_logic_1164.all; +library ibm; +use ibm.std_ulogic_unsigned.all; +use ibm.std_ulogic_function_support.all; +library support; +use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity mmq is + generic(thdid_width : integer := 4; + ttype_width : integer := 4; + state_width : integer := 4; + pid_width : integer := 14; + pid_width_erat : integer := 8; + lpid_width : integer := 8; + class_width : integer := 2; + extclass_width : integer := 2; + tlbsel_width : integer := 2; + epn_width : integer := 52; + req_epn_width : integer := 52; + vpn_width : integer := 61; + erat_cam_data_width : integer := 75; + erat_ary_data_width : integer := 73; + erat_rel_data_width : integer := 132; + ws_width : integer := 2; + rs_is_width : integer := 9; + ra_entry_width : integer := 12; + rs_data_width : integer := 64; + data_out_width : integer := 64; + error_width : integer := 3; + tlb_num_entry : natural := 512; + tlb_num_entry_log2 : natural := 9; + tlb_ways : natural := 4; + tlb_addr_width : natural := 7; + tlb_way_width : natural := 168; + tlb_word_width : natural := 84; + tlb_seq_width : integer := 6; + inv_seq_width : integer := 6; + por_seq_width : integer := 3; + watermark_width : integer := 4; + eptr_width : integer := 4; + lru_width : integer := 16; + mmucr0_width : integer := 20; + mmucr1_width : integer := 32; + mmucr2_width : integer := 32; + mmucr3_width : integer := 15; + spr_ctl_width : integer := 3; + spr_etid_width : integer := 2; + spr_addr_width : integer := 10; + spr_data_width : integer := 64; + debug_trace_width : integer := 88; + debug_event_width : integer := 16; + real_addr_width : integer := 42; + rpn_width : integer := 30; + pte_width : integer := 64; + lrat_num_entry_log2 : integer := 3; + tlb_tag_width : natural := 110; + mmq_spr_cswitch_0to3 : integer := 0; + mmq_tlb_cmp_cswitch_0to7 : integer := 0; + expand_tlb_type : integer := 2; + expand_type : integer := 2 ); +port( + vcs : inout power_logic; + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + +tc_ac_ccflush_dc : in std_ulogic; +tc_ac_scan_dis_dc_b : in std_ulogic; +tc_ac_scan_diag_dc : in std_ulogic; +tc_ac_lbist_en_dc : in std_ulogic; +pc_mm_gptr_sl_thold_3 : in std_ulogic; +pc_mm_time_sl_thold_3 : in std_ulogic; +pc_mm_repr_sl_thold_3 : in std_ulogic; +pc_mm_abst_sl_thold_3 : in std_ulogic; +pc_mm_abst_slp_sl_thold_3 : in std_ulogic; +pc_mm_func_sl_thold_3 : in std_ulogic_vector(0 to 1); +pc_mm_func_slp_sl_thold_3 : in std_ulogic_vector(0 to 1); +pc_mm_cfg_sl_thold_3 : in std_ulogic; +pc_mm_cfg_slp_sl_thold_3 : in std_ulogic; +pc_mm_func_nsl_thold_3 : in std_ulogic; +pc_mm_func_slp_nsl_thold_3 : in std_ulogic; +pc_mm_ary_nsl_thold_3 : in std_ulogic; +pc_mm_ary_slp_nsl_thold_3 : in std_ulogic; +pc_mm_sg_3 : in std_ulogic_vector(0 to 1); +pc_mm_fce_3 : in std_ulogic; +debug_bus_out : out std_ulogic_vector(0 to 87); +debug_bus_out_int : out std_ulogic_vector(0 to 7); +trace_triggers_out : out std_ulogic_vector(0 to 11); +debug_bus_in : in std_ulogic_vector(0 to 87); +trace_triggers_in : in std_ulogic_vector(0 to 11); +pc_mm_debug_mux1_ctrls : in std_ulogic_vector(0 to 15); +pc_mm_trace_bus_enable : in std_ulogic; +pc_mm_event_mux_ctrls : in std_ulogic_vector(0 to 39); +pc_mm_event_count_mode : in std_ulogic_vector(0 to 2); +rp_mm_event_bus_enable_q : in std_ulogic; +mm_pc_event_data : out std_ulogic_vector(0 to 7); +pc_mm_abist_dcomp_g6t_2r : in std_ulogic_vector(0 to 3); +pc_mm_abist_di_0 : in std_ulogic_vector(0 to 3); +pc_mm_abist_di_g6t_2r : in std_ulogic_vector(0 to 3); +pc_mm_abist_ena_dc : in std_ulogic; +pc_mm_abist_g6t_r_wb : in std_ulogic; +pc_mm_abist_g8t1p_renb_0 : in std_ulogic; +pc_mm_abist_g8t_bw_0 : in std_ulogic; +pc_mm_abist_g8t_bw_1 : in std_ulogic; +pc_mm_abist_g8t_dcomp : in std_ulogic_vector(0 to 3); +pc_mm_abist_g8t_wenb : in std_ulogic; +pc_mm_abist_raddr_0 : in std_ulogic_vector(0 to 9); +pc_mm_abist_raw_dc_b : in std_ulogic; +pc_mm_abist_waddr_0 : in std_ulogic_vector(0 to 9); +pc_mm_abist_wl128_comp_ena : in std_ulogic; +pc_mm_bolt_sl_thold_3 : in std_ulogic; +pc_mm_bo_enable_3 : in std_ulogic; +pc_mm_bo_reset : in std_ulogic; +pc_mm_bo_unload : in std_ulogic; +pc_mm_bo_repair : in std_ulogic; +pc_mm_bo_shdata : in std_ulogic; +pc_mm_bo_select : in std_ulogic_vector(0 to 4); +mm_pc_bo_fail : out std_ulogic_vector(0 to 4); +mm_pc_bo_diagout : out std_ulogic_vector(0 to 4); +iu_mm_ierat_req : in std_ulogic; +iu_mm_ierat_epn : in std_ulogic_vector(0 to 51); +iu_mm_ierat_thdid : in std_ulogic_vector(0 to thdid_width-1); +iu_mm_ierat_state : in std_ulogic_vector(0 to state_width-1); +iu_mm_ierat_tid : in std_ulogic_vector(0 to pid_width-1); +iu_mm_ierat_flush : in std_ulogic_vector(0 to thdid_width-1); +mm_iu_ierat_rel_val : out std_ulogic_vector(0 to 4); +mm_iu_ierat_rel_data : out std_ulogic_vector(0 to erat_rel_data_width-1); +mm_iu_ierat_snoop_coming : out std_ulogic; +mm_iu_ierat_snoop_val : out std_ulogic; +mm_iu_ierat_snoop_attr : out std_ulogic_vector(0 to 25); +mm_iu_ierat_snoop_vpn : out std_ulogic_vector(52-epn_width to 51); +iu_mm_ierat_snoop_ack : in std_ulogic; +mm_iu_ierat_pid0 : out std_ulogic_vector(0 to pid_width-1); +mm_iu_ierat_pid1 : out std_ulogic_vector(0 to pid_width-1); +mm_iu_ierat_pid2 : out std_ulogic_vector(0 to pid_width-1); +mm_iu_ierat_pid3 : out std_ulogic_vector(0 to pid_width-1); +mm_iu_ierat_mmucr0_0 : out std_ulogic_vector(0 to 19); +mm_iu_ierat_mmucr0_1 : out std_ulogic_vector(0 to 19); +mm_iu_ierat_mmucr0_2 : out std_ulogic_vector(0 to 19); +mm_iu_ierat_mmucr0_3 : out std_ulogic_vector(0 to 19); +iu_mm_ierat_mmucr0 : in std_ulogic_vector(0 to 17); +iu_mm_ierat_mmucr0_we : in std_ulogic_vector(0 to 3); +mm_iu_ierat_mmucr1 : out std_ulogic_vector(0 to 8); +iu_mm_ierat_mmucr1 : in std_ulogic_vector(0 to 3); +iu_mm_ierat_mmucr1_we : in std_ulogic; +xu_mm_derat_req : in std_ulogic; +xu_mm_derat_epn : in std_ulogic_vector(64-rs_data_width to 51); +xu_mm_derat_thdid : in std_ulogic_vector(0 to thdid_width-1); +xu_mm_derat_ttype : in std_ulogic_vector(0 to 1); +xu_mm_derat_state : in std_ulogic_vector(0 to state_width-1); +xu_mm_derat_lpid : in std_ulogic_vector(0 to lpid_width-1); +xu_mm_derat_tid : in std_ulogic_vector(0 to pid_width-1); +mm_xu_derat_rel_val : out std_ulogic_vector(0 to 4); +mm_xu_derat_rel_data : out std_ulogic_vector(0 to erat_rel_data_width-1); +mm_xu_derat_snoop_coming : out std_ulogic; +mm_xu_derat_snoop_val : out std_ulogic; +mm_xu_derat_snoop_attr : out std_ulogic_vector(0 to 25); +mm_xu_derat_snoop_vpn : out std_ulogic_vector(52-epn_width to 51); +xu_mm_derat_snoop_ack : in std_ulogic; +mm_xu_derat_pid0 : out std_ulogic_vector(0 to pid_width-1); +mm_xu_derat_pid1 : out std_ulogic_vector(0 to pid_width-1); +mm_xu_derat_pid2 : out std_ulogic_vector(0 to pid_width-1); +mm_xu_derat_pid3 : out std_ulogic_vector(0 to pid_width-1); +mm_xu_derat_mmucr0_0 : out std_ulogic_vector(0 to 19); +mm_xu_derat_mmucr0_1 : out std_ulogic_vector(0 to 19); +mm_xu_derat_mmucr0_2 : out std_ulogic_vector(0 to 19); +mm_xu_derat_mmucr0_3 : out std_ulogic_vector(0 to 19); +xu_mm_derat_mmucr0 : in std_ulogic_vector(0 to 17); +xu_mm_derat_mmucr0_we : in std_ulogic_vector(0 to 3); +mm_xu_derat_mmucr1 : out std_ulogic_vector(0 to 9); +xu_mm_derat_mmucr1 : in std_ulogic_vector(0 to 4); +xu_mm_derat_mmucr1_we : in std_ulogic; +xu_mm_rf1_val : in std_ulogic_vector(0 to 3); +xu_mm_rf1_is_tlbre : in std_ulogic; +xu_mm_rf1_is_tlbwe : in std_ulogic; +xu_mm_rf1_is_tlbsx : in std_ulogic; +xu_mm_rf1_is_tlbsxr : in std_ulogic; +xu_mm_rf1_is_tlbsrx : in std_ulogic; +xu_mm_rf1_is_tlbivax : in std_ulogic; +xu_mm_rf1_is_tlbilx : in std_ulogic; +xu_mm_rf1_is_erativax : in std_ulogic; +xu_mm_rf1_is_eratilx : in std_ulogic; +xu_mm_ex1_is_isync : in std_ulogic; +xu_mm_ex1_is_csync : in std_ulogic; +xu_mm_rf1_t : in std_ulogic_vector(0 to 2); +xu_mm_ex1_rs_is : in std_ulogic_vector(0 to 8); +xu_mm_ex2_eff_addr : in std_ulogic_vector(64-rs_data_width to 63); +xu_mm_msr_gs : in std_ulogic_vector(0 to thdid_width-1); +xu_mm_msr_pr : in std_ulogic_vector(0 to thdid_width-1); +xu_mm_msr_is : in std_ulogic_vector(0 to thdid_width-1); +xu_mm_msr_ds : in std_ulogic_vector(0 to thdid_width-1); +xu_mm_msr_cm : in std_ulogic_vector(0 to thdid_width-1); +xu_mm_spr_epcr_dmiuh : in std_ulogic_vector(0 to thdid_width-1); +xu_mm_spr_epcr_dgtmi : in std_ulogic_vector(0 to thdid_width-1); +xu_mm_hid_mmu_mode : in std_ulogic; +xu_mm_xucr4_mmu_mchk : in std_ulogic; +xu_mm_lmq_stq_empty : in std_ulogic; +iu_mm_lmq_empty : in std_ulogic; +xu_rf1_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_ex1_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_ex2_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_ex3_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_ex4_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_ex5_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_mm_ex4_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_mm_ex5_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_mm_ierat_miss : in std_ulogic_vector(0 to thdid_width-1); +xu_mm_ierat_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_mm_ex5_perf_dtlb : in std_ulogic_vector(0 to thdid_width-1); +xu_mm_ex5_perf_itlb : in std_ulogic_vector(0 to thdid_width-1); +mm_iu_barrier_done : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_eratmiss_done : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_cr0_eq : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_cr0_eq_valid : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_tlb_miss : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_lrat_miss : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_tlb_inelig : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_pt_fault : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_hv_priv : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_illeg_instr : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_esr_pt : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_esr_data : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_esr_epid : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_esr_st : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_quiesce : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_tlb_multihit_err : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_tlb_par_err : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_lru_par_err : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_local_snoop_reject : out std_ulogic_vector(0 to thdid_width-1); +xu_mm_hold_ack : in std_ulogic_vector(0 to thdid_width-1); +mm_xu_hold_req : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_hold_done : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_ex3_flush_req : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_lsu_req : out std_ulogic_vector(0 to 3); +mm_xu_lsu_ttype : out std_ulogic_vector(0 to 1); +mm_xu_lsu_wimge : out std_ulogic_vector(0 to 4); +mm_xu_lsu_u : out std_ulogic_vector(0 to 3); +mm_xu_lsu_addr : out std_ulogic_vector(64-real_addr_width to 63); +mm_xu_lsu_lpid : out std_ulogic_vector(0 to 7); +mm_xu_lsu_lpidr : out std_ulogic_vector(0 to 7); +mm_xu_lsu_gs : out std_ulogic; +mm_xu_lsu_ind : out std_ulogic; +mm_xu_lsu_lbit : out std_ulogic; +xu_mm_lsu_token :in std_ulogic; +slowspr_val_in : in std_ulogic; +slowspr_rw_in : in std_ulogic; +slowspr_etid_in : in std_ulogic_vector(0 to 1); +slowspr_addr_in : in std_ulogic_vector(0 to 9); +slowspr_data_in : in std_ulogic_vector(64-spr_data_width to 63); +slowspr_done_in : in std_ulogic; +slowspr_val_out : out std_ulogic; +slowspr_rw_out : out std_ulogic; +slowspr_etid_out : out std_ulogic_vector(0 to 1); +slowspr_addr_out : out std_ulogic_vector(0 to 9); +slowspr_data_out : out std_ulogic_vector(64-spr_data_width to 63); +slowspr_done_out : out std_ulogic; +gptr_scan_in :in std_ulogic; +time_scan_in :in std_ulogic; +repr_scan_in :in std_ulogic; +an_ac_abst_scan_in : in std_ulogic_vector(0 to 9); +an_ac_func_scan_in : in std_ulogic_vector(0 to 63); +an_ac_bcfg_scan_in : in std_ulogic_vector(0 to 4); +an_ac_dcfg_scan_in : in std_ulogic_vector(0 to 2); +ac_an_gptr_scan_out :out std_ulogic; +ac_an_time_scan_out :out std_ulogic; +ac_an_repr_scan_out :out std_ulogic; +bcfg_scan_out :out std_ulogic; +ccfg_scan_out :out std_ulogic; +dcfg_scan_out :out std_ulogic; +an_ac_back_inv : in std_ulogic; +an_ac_back_inv_target : in std_ulogic_vector(0 to 4); +an_ac_back_inv_addr : in std_ulogic_vector(64-real_addr_width to 63); +an_ac_back_inv_local : in std_ulogic; +an_ac_back_inv_lbit : in std_ulogic; +an_ac_back_inv_gs : in std_ulogic; +an_ac_back_inv_ind : in std_ulogic; +an_ac_back_inv_lpar_id : in std_ulogic_vector(0 to lpid_width-1); +ac_an_back_inv_reject : out std_ulogic; +ac_an_lpar_id : out std_ulogic_vector(0 to lpid_width-1); +an_ac_reld_core_tag : in std_ulogic_vector(0 to 4); +an_ac_reld_data : in std_ulogic_vector(0 to 127); +an_ac_reld_data_vld : in std_ulogic; +an_ac_reld_ecc_err : in std_ulogic; +an_ac_reld_ecc_err_ue : in std_ulogic; +an_ac_reld_qw : in std_ulogic_vector(57 to 59); +an_ac_reld_ditc : in std_ulogic; +an_ac_reld_crit_qw : in std_ulogic; +an_ac_reld_data_coming : in std_ulogic; +an_ac_reld_l1_dump : in std_ulogic; +an_ac_grffence_en_dc : in std_ulogic; +an_ac_stcx_complete : in std_ulogic_vector(0 to 3); +an_ac_abist_mode_dc : in std_ulogic; +an_ac_abist_start_test : in std_ulogic; +an_ac_atpg_en_dc : in std_ulogic; +an_ac_lbist_ary_wrt_thru_dc : in std_ulogic; +an_ac_ccflush_dc : in std_ulogic; +an_ac_reset_1_complete : in std_ulogic; +an_ac_reset_2_complete : in std_ulogic; +an_ac_reset_3_complete : in std_ulogic; +an_ac_reset_wd_complete : in std_ulogic; +an_ac_debug_stop : in std_ulogic; +an_ac_lbist_en_dc : in std_ulogic; +an_ac_pm_thread_stop : in std_ulogic_vector(0 to 3); +an_ac_regf_scan_in : in std_ulogic_vector(0 to 11); +an_ac_scan_diag_dc : in std_ulogic; +an_ac_scan_dis_dc_b : in std_ulogic; +an_ac_scom_cch : in std_ulogic; +an_ac_scom_dch : in std_ulogic; +an_ac_checkstop : in std_ulogic; +an_ac_back_inv_omm : out std_ulogic; +an_ac_back_inv_addr_omm : out std_ulogic_vector(64-real_addr_width to 63); +an_ac_back_inv_target_omm_iua : out std_ulogic_vector(0 to 1); +an_ac_back_inv_target_omm_iub : out std_ulogic_vector(3 to 4); +an_ac_reld_core_tag_omm : out std_ulogic_vector(0 to 4); +an_ac_reld_data_omm : out std_ulogic_vector(0 to 127); +an_ac_reld_data_vld_omm : out std_ulogic; +an_ac_reld_ecc_err_omm : out std_ulogic; +an_ac_reld_ecc_err_ue_omm : out std_ulogic; +an_ac_reld_qw_omm : out std_ulogic_vector(57 to 59); +an_ac_reld_ditc_omm : out std_ulogic; +an_ac_reld_crit_qw_omm : out std_ulogic; +an_ac_reld_data_coming_omm : out std_ulogic; +an_ac_reld_l1_dump_omm : out std_ulogic; +an_ac_grffence_en_dc_omm : out std_ulogic; +an_ac_stcx_complete_omm : out std_ulogic_vector(0 to 3); +an_ac_abist_mode_dc_omm : out std_ulogic; +an_ac_abist_start_test_omm : out std_ulogic; +an_ac_abst_scan_in_omm_iu : out std_ulogic_vector(0 to 4); +an_ac_abst_scan_in_omm_xu : out std_ulogic_vector(7 to 9); +an_ac_atpg_en_dc_omm : out std_ulogic; +an_ac_bcfg_scan_in_omm_bit1 : out std_ulogic; +an_ac_bcfg_scan_in_omm_bit3 : out std_ulogic; +an_ac_bcfg_scan_in_omm_bit4 : out std_ulogic; +an_ac_lbist_ary_wrt_thru_dc_omm : out std_ulogic; +an_ac_ccflush_dc_omm : out std_ulogic; +an_ac_reset_1_complete_omm : out std_ulogic; +an_ac_reset_2_complete_omm : out std_ulogic; +an_ac_reset_3_complete_omm : out std_ulogic; +an_ac_reset_wd_complete_omm : out std_ulogic; +an_ac_dcfg_scan_in_omm : out std_ulogic_vector(1 to 2); +an_ac_debug_stop_omm : out std_ulogic; +an_ac_func_scan_in_omm_iua : out std_ulogic_vector(0 to 21); +an_ac_func_scan_in_omm_iub : out std_ulogic_vector(60 to 63); +an_ac_func_scan_in_omm_xu : out std_ulogic_vector(31 to 58); +an_ac_lbist_en_dc_omm : out std_ulogic; +an_ac_pm_thread_stop_omm : out std_ulogic_vector(0 to 3); +an_ac_regf_scan_in_omm : out std_ulogic_vector(0 to 11); +an_ac_scan_diag_dc_omm : out std_ulogic; +an_ac_scan_dis_dc_b_omm : out std_ulogic; +an_ac_scom_cch_omm : out std_ulogic; +an_ac_scom_dch_omm : out std_ulogic; +an_ac_checkstop_omm : out std_ulogic; +ac_an_abst_scan_out_imm_iu : in std_ulogic_vector(0 to 4); +ac_an_abst_scan_out_imm_xu : in std_ulogic_vector(7 to 9); +ac_an_bcfg_scan_out_imm : in std_ulogic_vector(0 to 4); +ac_an_dcfg_scan_out_imm : in std_ulogic_vector(0 to 2); +ac_an_func_scan_out_imm_iua : in std_ulogic_vector(0 to 21); +ac_an_func_scan_out_imm_iub : in std_ulogic_vector(60 to 63); +ac_an_func_scan_out_imm_xu : in std_ulogic_vector(31 to 58); +ac_an_reld_ditc_pop_imm : in std_ulogic_vector(0 to 3); +ac_an_power_managed_imm : in std_ulogic; +ac_an_rvwinkle_mode_imm : in std_ulogic; +ac_an_fu_bypass_events_imm : in std_ulogic_vector(0 to 7); +ac_an_iu_bypass_events_imm : in std_ulogic_vector(0 to 7); +ac_an_mm_bypass_events_imm : in std_ulogic_vector(0 to 7); +ac_an_lsu_bypass_events_imm : in std_ulogic_vector(0 to 7); +ac_an_event_bus_imm : in std_ulogic_vector(0 to 7); +ac_an_pm_thread_running_imm : in std_ulogic_vector(0 to 3); +ac_an_recov_err_imm : in std_ulogic_vector(0 to 2); +ac_an_regf_scan_out_imm : in std_ulogic_vector(0 to 11); +ac_an_scom_cch_imm : in std_ulogic; +ac_an_scom_dch_imm : in std_ulogic; +ac_an_special_attn_imm : in std_ulogic_vector(0 to 3); +ac_an_checkstop_imm : in std_ulogic_vector(0 to 2); +ac_an_local_checkstop_imm : in std_ulogic_vector(0 to 2); +ac_an_trace_error_imm : in std_ulogic; +ac_an_abst_scan_out : out std_ulogic_vector(0 to 9); +ac_an_bcfg_scan_out : out std_ulogic_vector(0 to 4); +ac_an_dcfg_scan_out : out std_ulogic_vector(0 to 2); +ac_an_func_scan_out : out std_ulogic_vector(0 to 63); +ac_an_reld_ditc_pop : out std_ulogic_vector(0 to 3); +ac_an_power_managed : out std_ulogic; +ac_an_rvwinkle_mode : out std_ulogic; +ac_an_fu_bypass_events : out std_ulogic_vector(0 to 7); +ac_an_iu_bypass_events : out std_ulogic_vector(0 to 7); +ac_an_mm_bypass_events : out std_ulogic_vector(0 to 7); +ac_an_lsu_bypass_events : out std_ulogic_vector(0 to 7); +ac_an_event_bus : out std_ulogic_vector(0 to 7); +ac_an_pm_thread_running : out std_ulogic_vector(0 to 3); +ac_an_recov_err : out std_ulogic_vector(0 to 2); +ac_an_regf_scan_out : out std_ulogic_vector(0 to 11); +ac_an_scom_cch : out std_ulogic; +ac_an_scom_dch : out std_ulogic; +ac_an_special_attn : out std_ulogic_vector(0 to 3); +ac_an_checkstop : out std_ulogic_vector(0 to 2); +ac_an_local_checkstop : out std_ulogic_vector(0 to 2); +ac_an_trace_error : out std_ulogic; +an_ac_dcr_act : in std_ulogic; +an_ac_dcr_val : in std_ulogic; +an_ac_dcr_read : in std_ulogic; +an_ac_dcr_etid : in std_ulogic_vector(0 to 1); +an_ac_dcr_data : in std_ulogic_vector(64-spr_data_width to 63); +an_ac_dcr_done : in std_ulogic; +an_ac_crit_interrupt : in std_ulogic_vector(0 to thdid_width-1); +an_ac_ext_interrupt : in std_ulogic_vector(0 to thdid_width-1); +an_ac_flh2l2_gate : in std_ulogic; +an_ac_icbi_ack : in std_ulogic; +an_ac_icbi_ack_thread : in std_ulogic_vector(0 to 1); +an_ac_req_ld_pop : in std_ulogic; +an_ac_req_spare_ctrl_a1 : in std_ulogic_vector(0 to 3); +an_ac_req_st_gather : in std_ulogic; +an_ac_req_st_pop : in std_ulogic; +an_ac_req_st_pop_thrd : in std_ulogic_vector(0 to 2); +an_ac_reservation_vld : in std_ulogic_vector(0 to thdid_width-1); +an_ac_sleep_en : in std_ulogic_vector(0 to thdid_width-1); +an_ac_stcx_pass : in std_ulogic_vector(0 to 3); +an_ac_sync_ack : in std_ulogic_vector(0 to 3); +an_ac_ary_nsl_thold_7 : in std_ulogic; +an_ac_ccenable_dc : in std_ulogic; +an_ac_coreid : in std_ulogic_vector(0 to 7); +an_ac_external_mchk : in std_ulogic_vector(0 to 3); +an_ac_fce_7 : in std_ulogic; +an_ac_func_nsl_thold_7 : in std_ulogic; +an_ac_func_sl_thold_7 : in std_ulogic; +an_ac_gsd_test_enable_dc : in std_ulogic; +an_ac_gsd_test_acmode_dc : in std_ulogic; +an_ac_gptr_scan_in : in std_ulogic; +an_ac_hang_pulse : in std_ulogic_vector(0 to thdid_width-1); +an_ac_lbist_ac_mode_dc : in std_ulogic; +an_ac_lbist_ip_dc : in std_ulogic; +an_ac_malf_alert : in std_ulogic; +an_ac_perf_interrupt : in std_ulogic_vector(0 to thdid_width-1); +an_ac_psro_enable_dc : in std_ulogic_vector(0 to 2); +an_ac_repr_scan_in : in std_ulogic; +an_ac_rtim_sl_thold_7 : in std_ulogic; +an_ac_scan_type_dc : in std_ulogic_vector(0 to 8); +an_ac_scom_sat_id : in std_ulogic_vector(0 to 3); +an_ac_sg_7 : in std_ulogic; +an_ac_tb_update_enable : in std_ulogic; +an_ac_tb_update_pulse : in std_ulogic; +an_ac_time_scan_in : in std_ulogic; +an_ac_crit_interrupt_omm : out std_ulogic_vector(0 to thdid_width-1); +an_ac_ext_interrupt_omm : out std_ulogic_vector(0 to thdid_width-1); +an_ac_flh2l2_gate_omm : out std_ulogic; +an_ac_icbi_ack_omm : out std_ulogic; +an_ac_icbi_ack_thread_omm : out std_ulogic_vector(0 to 1); +an_ac_req_ld_pop_omm : out std_ulogic; +an_ac_req_spare_ctrl_a1_omm : out std_ulogic_vector(0 to 3); +an_ac_req_st_gather_omm : out std_ulogic; +an_ac_req_st_pop_omm : out std_ulogic; +an_ac_req_st_pop_thrd_omm : out std_ulogic_vector(0 to 2); +an_ac_reservation_vld_omm : out std_ulogic_vector(0 to thdid_width-1); +an_ac_sleep_en_omm : out std_ulogic_vector(0 to thdid_width-1); +an_ac_stcx_pass_omm : out std_ulogic_vector(0 to 3); +an_ac_sync_ack_omm : out std_ulogic_vector(0 to 3); +an_ac_ary_nsl_thold_7_omm : out std_ulogic; +an_ac_ccenable_dc_omm : out std_ulogic; +an_ac_coreid_omm : out std_ulogic_vector(0 to 7); +an_ac_external_mchk_omm : out std_ulogic_vector(0 to 3); +an_ac_fce_7_omm : out std_ulogic; +an_ac_func_nsl_thold_7_omm : out std_ulogic; +an_ac_func_sl_thold_7_omm : out std_ulogic; +an_ac_gsd_test_enable_dc_omm : out std_ulogic; +an_ac_gsd_test_acmode_dc_omm : out std_ulogic; +an_ac_gptr_scan_in_omm : out std_ulogic; +an_ac_hang_pulse_omm : out std_ulogic_vector(0 to thdid_width-1); +an_ac_lbist_ac_mode_dc_omm : out std_ulogic; +an_ac_lbist_ip_dc_omm : out std_ulogic; +an_ac_malf_alert_omm : out std_ulogic; +an_ac_perf_interrupt_omm : out std_ulogic_vector(0 to thdid_width-1); +an_ac_psro_enable_dc_omm : out std_ulogic_vector(0 to 2); +an_ac_repr_scan_in_omm : out std_ulogic; +an_ac_rtim_sl_thold_7_omm : out std_ulogic; +an_ac_scan_type_dc_omm : out std_ulogic_vector(0 to 8); +an_ac_scom_sat_id_omm : out std_ulogic_vector(0 to 3); +an_ac_sg_7_omm : out std_ulogic; +an_ac_tb_update_enable_omm : out std_ulogic; +an_ac_tb_update_pulse_omm : out std_ulogic; +an_ac_time_scan_in_omm : out std_ulogic; +ac_an_box_empty_imm : in std_ulogic_vector(0 to 3); +ac_an_machine_check_imm : in std_ulogic_vector(0 to thdid_width-1); +ac_an_req_imm : in std_ulogic; +ac_an_req_endian_imm : in std_ulogic; +ac_an_req_ld_core_tag_imm : in std_ulogic_vector(0 to 4); +ac_an_req_ld_xfr_len_imm : in std_ulogic_vector(0 to 2); +ac_an_req_pwr_token_imm : in std_ulogic; +ac_an_req_ra_imm : in std_ulogic_vector(64-real_addr_width to 63); +ac_an_req_spare_ctrl_a0_imm : in std_ulogic_vector(0 to 3); +ac_an_req_thread_imm : in std_ulogic_vector(0 to 2); +ac_an_req_ttype_imm : in std_ulogic_vector(0 to 5); +ac_an_req_user_defined_imm : in std_ulogic_vector(0 to 3); +ac_an_req_wimg_g_imm : in std_ulogic; +ac_an_req_wimg_i_imm : in std_ulogic; +ac_an_req_wimg_m_imm : in std_ulogic; +ac_an_req_wimg_w_imm : in std_ulogic; +ac_an_st_byte_enbl_imm : in std_ulogic_vector(0 to 31); +ac_an_st_data_imm : in std_ulogic_vector(0 to 255); +ac_an_st_data_pwr_token_imm : in std_ulogic; +ac_an_abist_done_dc_imm : in std_ulogic; +ac_an_debug_trigger_imm : in std_ulogic_vector(0 to thdid_width-1); +ac_an_psro_ringsig_imm : in std_ulogic; +ac_an_reset_1_request_imm : in std_ulogic; +ac_an_reset_2_request_imm : in std_ulogic; +ac_an_reset_3_request_imm : in std_ulogic; +ac_an_reset_wd_request_imm : in std_ulogic; +ac_an_box_empty : out std_ulogic_vector(0 to 3); +ac_an_machine_check : out std_ulogic_vector(0 to thdid_width-1); +ac_an_req : out std_ulogic; +ac_an_req_endian : out std_ulogic; +ac_an_req_ld_core_tag : out std_ulogic_vector(0 to 4); +ac_an_req_ld_xfr_len : out std_ulogic_vector(0 to 2); +ac_an_req_pwr_token : out std_ulogic; +ac_an_req_ra : out std_ulogic_vector(64-real_addr_width to 63); +ac_an_req_spare_ctrl_a0 : out std_ulogic_vector(0 to 3); +ac_an_req_thread : out std_ulogic_vector(0 to 2); +ac_an_req_ttype : out std_ulogic_vector(0 to 5); +ac_an_req_user_defined : out std_ulogic_vector(0 to 3); +ac_an_req_wimg_g : out std_ulogic; +ac_an_req_wimg_i : out std_ulogic; +ac_an_req_wimg_m : out std_ulogic; +ac_an_req_wimg_w : out std_ulogic; +ac_an_st_byte_enbl : out std_ulogic_vector(0 to 31); +ac_an_st_data : out std_ulogic_vector(0 to 255); +ac_an_st_data_pwr_token : out std_ulogic; +ac_an_abist_done_dc : out std_ulogic; +ac_an_debug_trigger : out std_ulogic_vector(0 to thdid_width-1); +ac_an_psro_ringsig : out std_ulogic; +ac_an_reset_1_request : out std_ulogic; +ac_an_reset_2_request : out std_ulogic; +ac_an_reset_3_request : out std_ulogic; +ac_an_reset_wd_request : out std_ulogic; +ac_an_dcr_act : out std_ulogic; +ac_an_dcr_val : out std_ulogic; +ac_an_dcr_read : out std_ulogic; +ac_an_dcr_user : out std_ulogic; +ac_an_dcr_etid : out std_ulogic_vector(0 to 1); +ac_an_dcr_addr : out std_ulogic_vector(11 to 20); +ac_an_dcr_data : out std_ulogic_vector(64-spr_data_width to 63); +bg_ac_an_func_scan_ns_imm : in std_ulogic_vector(60 to 69); +bg_ac_an_abst_scan_ns_imm : in std_ulogic_vector(10 to 11); +bg_ac_an_func_scan_ns : out std_ulogic_vector(60 to 69); +bg_ac_an_abst_scan_ns : out std_ulogic_vector(10 to 11); +bg_pc_l1p_abist_di_0_imm : in std_ulogic_vector(0 to 3); +bg_pc_l1p_abist_g8t1p_renb_0_imm : in std_ulogic; +bg_pc_l1p_abist_g8t_bw_0_imm : in std_ulogic; +bg_pc_l1p_abist_g8t_bw_1_imm : in std_ulogic; +bg_pc_l1p_abist_g8t_dcomp_imm : in std_ulogic_vector(0 to 3); +bg_pc_l1p_abist_g8t_wenb_imm : in std_ulogic; +bg_pc_l1p_abist_raddr_0_imm : in std_ulogic_vector(0 to 9); +bg_pc_l1p_abist_waddr_0_imm : in std_ulogic_vector(0 to 9); +bg_pc_l1p_abist_wl128_comp_ena_imm : in std_ulogic; +bg_pc_l1p_abist_wl32_comp_ena_imm : in std_ulogic; +bg_pc_l1p_abist_di_0 : out std_ulogic_vector(0 to 3); +bg_pc_l1p_abist_g8t1p_renb_0 : out std_ulogic; +bg_pc_l1p_abist_g8t_bw_0 : out std_ulogic; +bg_pc_l1p_abist_g8t_bw_1 : out std_ulogic; +bg_pc_l1p_abist_g8t_dcomp : out std_ulogic_vector(0 to 3); +bg_pc_l1p_abist_g8t_wenb : out std_ulogic; +bg_pc_l1p_abist_raddr_0 : out std_ulogic_vector(0 to 9); +bg_pc_l1p_abist_waddr_0 : out std_ulogic_vector(0 to 9); +bg_pc_l1p_abist_wl128_comp_ena : out std_ulogic; +bg_pc_l1p_abist_wl32_comp_ena : out std_ulogic; +bg_pc_l1p_gptr_sl_thold_2_imm : in std_ulogic; +bg_pc_l1p_time_sl_thold_2_imm : in std_ulogic; +bg_pc_l1p_repr_sl_thold_2_imm : in std_ulogic; +bg_pc_l1p_abst_sl_thold_2_imm : in std_ulogic; +bg_pc_l1p_func_sl_thold_2_imm : in std_ulogic_vector(0 to 1); +bg_pc_l1p_func_slp_sl_thold_2_imm : in std_ulogic; +bg_pc_l1p_bolt_sl_thold_2_imm : in std_ulogic; +bg_pc_l1p_ary_nsl_thold_2_imm : in std_ulogic; +bg_pc_l1p_sg_2_imm : in std_ulogic_vector(0 to 1); +bg_pc_l1p_fce_2_imm : in std_ulogic; +bg_pc_l1p_bo_enable_2_imm : in std_ulogic; +bg_pc_l1p_gptr_sl_thold_2 : out std_ulogic; +bg_pc_l1p_time_sl_thold_2 : out std_ulogic; +bg_pc_l1p_repr_sl_thold_2 : out std_ulogic; +bg_pc_l1p_abst_sl_thold_2 : out std_ulogic; +bg_pc_l1p_func_sl_thold_2 : out std_ulogic_vector(0 to 1); +bg_pc_l1p_func_slp_sl_thold_2 : out std_ulogic; +bg_pc_l1p_bolt_sl_thold_2 : out std_ulogic; +bg_pc_l1p_ary_nsl_thold_2 : out std_ulogic; +bg_pc_l1p_sg_2 : out std_ulogic_vector(0 to 1); +bg_pc_l1p_fce_2 : out std_ulogic; +bg_pc_l1p_bo_enable_2 : out std_ulogic; +bg_pc_bo_unload_imm : in std_ulogic; +bg_pc_bo_load_imm : in std_ulogic; +bg_pc_bo_repair_imm : in std_ulogic; +bg_pc_bo_reset_imm : in std_ulogic; +bg_pc_bo_shdata_imm : in std_ulogic; +bg_pc_bo_select_imm : in std_ulogic_vector(0 to 10); +bg_pc_l1p_ccflush_dc_imm : in std_ulogic; +bg_pc_l1p_abist_ena_dc_imm : in std_ulogic; +bg_pc_l1p_abist_raw_dc_b_imm : in std_ulogic; +bg_pc_bo_unload : out std_ulogic; +bg_pc_bo_load : out std_ulogic; +bg_pc_bo_repair : out std_ulogic; +bg_pc_bo_reset : out std_ulogic; +bg_pc_bo_shdata : out std_ulogic; +bg_pc_bo_select : out std_ulogic_vector(0 to 10); +bg_pc_l1p_ccflush_dc : out std_ulogic; +bg_pc_l1p_abist_ena_dc : out std_ulogic; +bg_pc_l1p_abist_raw_dc_b : out std_ulogic; +bg_an_ac_func_scan_sn : in std_ulogic_vector(60 to 69); +bg_an_ac_abst_scan_sn : in std_ulogic_vector(10 to 11); +bg_an_ac_func_scan_sn_omm : out std_ulogic_vector(60 to 69); +bg_an_ac_abst_scan_sn_omm : out std_ulogic_vector(10 to 11); +bg_pc_bo_fail : in std_ulogic_vector(0 to 10); +bg_pc_bo_diagout : in std_ulogic_vector(0 to 10); +bg_pc_bo_fail_omm : out std_ulogic_vector(0 to 10); +bg_pc_bo_diagout_omm : out std_ulogic_vector(0 to 10) +); +end mmq; +architecture mmq of mmq is +constant MMU_Mode_Value : std_ulogic := '0'; +constant TlbSel_Tlb : std_ulogic_vector(0 to 1) := "00"; +constant TlbSel_IErat : std_ulogic_vector(0 to 1) := "10"; +constant TlbSel_DErat : std_ulogic_vector(0 to 1) := "11"; +constant mmq_inval_offset : natural := 0; +constant mmq_spr_offset_0 : natural := mmq_inval_offset + 1; +constant scan_right_0 : natural := mmq_spr_offset_0; +constant tlb_cmp2_offset : natural := 0; +constant mmq_perf_offset : natural := tlb_cmp2_offset + 1; +constant mmq_dbg_offset : natural := mmq_perf_offset + 1; +constant scan_right_1 : natural := mmq_dbg_offset; +constant mmq_spr_bcfg_offset : natural := 0; +constant boot_scan_right : natural := mmq_spr_bcfg_offset + 1 - 1; +signal pid0_sig : std_ulogic_vector(0 to pid_width-1); +signal pid1_sig : std_ulogic_vector(0 to pid_width-1); +signal pid2_sig : std_ulogic_vector(0 to pid_width-1); +signal pid3_sig : std_ulogic_vector(0 to pid_width-1); +signal mmucr0_0_sig : std_ulogic_vector(0 to mmucr0_width-1); +signal mmucr0_1_sig : std_ulogic_vector(0 to mmucr0_width-1); +signal mmucr0_2_sig : std_ulogic_vector(0 to mmucr0_width-1); +signal mmucr0_3_sig : std_ulogic_vector(0 to mmucr0_width-1); +signal mmucr1_sig : std_ulogic_vector(0 to mmucr1_width-1); +signal mmucr2_sig : std_ulogic_vector(0 to mmucr2_width-1); +signal mmucr3_0_sig : std_ulogic_vector(64-mmucr3_width to 63); +signal mmucr3_1_sig : std_ulogic_vector(64-mmucr3_width to 63); +signal mmucr3_2_sig : std_ulogic_vector(64-mmucr3_width to 63); +signal mmucr3_3_sig : std_ulogic_vector(64-mmucr3_width to 63); +signal lpidr_sig : std_ulogic_vector(0 to lpid_width-1); +signal ac_an_lpar_id_sig : std_ulogic_vector(0 to lpid_width-1); +signal mm_iu_ierat_rel_val_sig : std_ulogic_vector(0 to 4); +signal mm_iu_ierat_rel_data_sig : std_ulogic_vector(0 to erat_rel_data_width-1); +signal mm_xu_derat_rel_val_sig : std_ulogic_vector(0 to 4); +signal mm_xu_derat_rel_data_sig : std_ulogic_vector(0 to erat_rel_data_width-1); +signal mm_xu_hold_req_sig : std_ulogic_vector(0 to thdid_width-1); +signal mm_xu_hold_done_sig : std_ulogic_vector(0 to thdid_width-1); +signal tlb_cmp_ierat_dup_val_sig : std_ulogic_vector(0 to 6); +signal tlb_cmp_derat_dup_val_sig : std_ulogic_vector(0 to 6); +signal tlb_cmp_erat_dup_wait_sig : std_ulogic_vector(0 to 1); +signal tlb_ctl_ex2_flush_req_sig : std_ulogic_vector(0 to thdid_width-1); +signal tlb_ctl_ex2_illeg_instr_sig : std_ulogic_vector(0 to thdid_width-1); +signal tlb_ctl_barrier_done_sig : std_ulogic_vector(0 to thdid_width-1); +signal mm_iu_barrier_done_sig : std_ulogic_vector(0 to thdid_width-1); +signal mm_xu_ex3_flush_req_sig : std_ulogic_vector(0 to thdid_width-1); +signal mm_xu_quiesce_sig : std_ulogic_vector(0 to thdid_width-1); +signal mm_xu_eratmiss_done_sig : std_ulogic_vector(0 to thdid_width-1); +signal mm_xu_tlb_miss_sig : std_ulogic_vector(0 to thdid_width-1); +signal mm_xu_lrat_miss_sig : std_ulogic_vector(0 to thdid_width-1); +signal mm_xu_pt_fault_sig : std_ulogic_vector(0 to thdid_width-1); +signal mm_xu_hv_priv_sig : std_ulogic_vector(0 to thdid_width-1); +signal mm_xu_illeg_instr_sig : std_ulogic_vector(0 to thdid_width-1); +signal mm_xu_tlb_inelig_sig : std_ulogic_vector(0 to thdid_width-1); +signal mm_xu_esr_pt_sig : std_ulogic_vector(0 to thdid_width-1); +signal mm_xu_esr_data_sig : std_ulogic_vector(0 to thdid_width-1); +signal mm_xu_esr_epid_sig : std_ulogic_vector(0 to thdid_width-1); +signal mm_xu_esr_st_sig : std_ulogic_vector(0 to thdid_width-1); +signal mm_xu_cr0_eq_sig : std_ulogic_vector(0 to thdid_width-1); +signal mm_xu_cr0_eq_valid_sig : std_ulogic_vector(0 to thdid_width-1); +signal mm_xu_local_snoop_reject_sig : std_ulogic_vector(0 to thdid_width-1); +signal tlb_req_quiesce_sig : std_ulogic_vector(0 to thdid_width-1); +signal tlb_ctl_quiesce_sig : std_ulogic_vector(0 to thdid_width-1); +signal htw_quiesce_sig : std_ulogic_vector(0 to thdid_width-1); +signal xu_mm_ccr2_notlb_b : std_ulogic_vector(1 to 12); +signal xu_mm_epcr_dgtmi_sig : std_ulogic_vector(0 to thdid_width-1); +signal xu_mm_xucr4_mmu_mchk_q : std_ulogic; +signal lru_write : std_ulogic_vector(0 to lru_width-1); +signal lru_wr_addr : std_ulogic_vector(0 to tlb_addr_width-1); +signal lru_rd_addr : std_ulogic_vector(0 to tlb_addr_width-1); +signal lru_datain : std_ulogic_vector(0 to lru_width-1); +signal lru_dataout : std_ulogic_vector(0 to lru_width-1); +signal tlb_tag2_sig : std_ulogic_vector(0 to tlb_tag_width-1); +signal tlb_addr2_sig : std_ulogic_vector(0 to tlb_addr_width-1); +signal tlb_write : std_ulogic_vector(0 to tlb_ways-1); +signal tlb_addr : std_ulogic_vector(0 to tlb_addr_width-1); +signal tlb_dataina : std_ulogic_vector(0 to tlb_way_width-1); +signal tlb_datainb : std_ulogic_vector(0 to tlb_way_width-1); +signal tlb_dataout : std_ulogic_vector(0 to tlb_way_width*tlb_ways-1); +signal lru_tag4_dataout : std_ulogic_vector(0 to 15); +signal tlb_tag4_esel : std_ulogic_vector(0 to 2); +signal tlb_tag4_wq : std_ulogic_vector(0 to 1); +signal tlb_tag4_is : std_ulogic_vector(0 to 1); +signal tlb_tag4_gs : std_ulogic; +signal tlb_tag4_pr : std_ulogic; +signal tlb_tag4_hes : std_ulogic; +signal tlb_tag4_atsel : std_ulogic; +signal tlb_tag4_pt : std_ulogic; +signal tlb_tag4_cmp_hit : std_ulogic; +signal tlb_tag4_way_ind : std_ulogic; +signal tlb_tag4_ptereload : std_ulogic; +signal tlb_tag4_endflag : std_ulogic; +signal tlb_tag4_parerr : std_ulogic; +signal tlb_tag5_except : std_ulogic_vector(0 to thdid_width-1); +signal ptereload_req_pte_lat : std_ulogic_vector(0 to pte_width-1); +signal ex6_illeg_instr : std_ulogic_vector(0 to 1); +signal tlb_ctl_tag2_flush_sig : std_ulogic_vector(0 to thdid_width-1); +signal tlb_ctl_tag3_flush_sig : std_ulogic_vector(0 to thdid_width-1); +signal tlb_ctl_tag4_flush_sig : std_ulogic_vector(0 to thdid_width-1); +signal tlb_resv_match_vec_sig : std_ulogic_vector(0 to thdid_width-1); +signal tlb_ctl_ex3_valid_sig : std_ulogic_vector(0 to thdid_width-1); +signal tlb_ctl_ex3_ttype_sig : std_ulogic_vector(0 to 4); +signal ierat_req_taken : std_ulogic; +signal derat_req_taken : std_ulogic; +signal tlb_seq_ierat_req : std_ulogic; +signal tlb_seq_derat_req : std_ulogic; +signal tlb_seq_ierat_done : std_ulogic; +signal tlb_seq_derat_done : std_ulogic; +signal tlb_seq_idle : std_ulogic; +signal ierat_req_epn : std_ulogic_vector(0 to req_epn_width-1); +signal ierat_req_pid : std_ulogic_vector(0 to pid_width-1); +signal ierat_req_state : std_ulogic_vector(0 to state_width-1); +signal ierat_req_thdid : std_ulogic_vector(0 to thdid_width-1); +signal ierat_req_dup : std_ulogic_vector(0 to 1); +signal derat_req_epn : std_ulogic_vector(0 to req_epn_width-1); +signal derat_req_pid : std_ulogic_vector(0 to pid_width-1); +signal derat_req_lpid : std_ulogic_vector(0 to lpid_width-1); +signal derat_req_state : std_ulogic_vector(0 to state_width-1); +signal derat_req_ttype : std_ulogic_vector(0 to 1); +signal derat_req_thdid : std_ulogic_vector(0 to thdid_width-1); +signal derat_req_dup : std_ulogic_vector(0 to 1); +signal ptereload_req_valid : std_ulogic; +signal ptereload_req_tag : std_ulogic_vector(0 to tlb_tag_width-1); +signal ptereload_req_pte : std_ulogic_vector(0 to pte_width-1); +signal ptereload_req_taken : std_ulogic; +signal tlb_htw_req_valid : std_ulogic; +signal tlb_htw_req_tag : std_ulogic_vector(0 to tlb_tag_width-1); +signal tlb_htw_req_way : std_ulogic_vector(tlb_word_width to tlb_way_width-1); +signal htw_lsu_req_valid : std_ulogic; +signal htw_lsu_thdid : std_ulogic_vector(0 to thdid_width-1); +signal htw_dbg_lsu_thdid : std_ulogic_vector(0 to 1); +signal htw_lsu_ttype : std_ulogic_vector(0 to 1); +signal htw_lsu_wimge : std_ulogic_vector(0 to 4); +signal htw_lsu_u : std_ulogic_vector(0 to 3); +signal htw_lsu_addr : std_ulogic_vector(64-real_addr_width to 63); +signal htw_lsu_req_taken : std_ulogic; +signal htw_req0_valid : std_ulogic; +signal htw_req0_thdid : std_ulogic_vector(0 to thdid_width-1); +signal htw_req0_type : std_ulogic_vector(0 to 1); +signal htw_req1_valid : std_ulogic; +signal htw_req1_thdid : std_ulogic_vector(0 to thdid_width-1); +signal htw_req1_type : std_ulogic_vector(0 to 1); +signal htw_req2_valid : std_ulogic; +signal htw_req2_thdid : std_ulogic_vector(0 to thdid_width-1); +signal htw_req2_type : std_ulogic_vector(0 to 1); +signal htw_req3_valid : std_ulogic; +signal htw_req3_thdid : std_ulogic_vector(0 to thdid_width-1); +signal htw_req3_type : std_ulogic_vector(0 to 1); +signal mm_xu_lsu_req_sig : std_ulogic_vector(0 to 3); +signal mm_xu_lsu_ttype_sig : std_ulogic_vector(0 to 1); +signal mm_xu_lsu_wimge_sig : std_ulogic_vector(0 to 4); +signal mm_xu_lsu_u_sig : std_ulogic_vector(0 to 3); +signal mm_xu_lsu_addr_sig : std_ulogic_vector(64-real_addr_width to 63); +signal mm_xu_lsu_lpid_sig : std_ulogic_vector(0 to 7); +signal mm_xu_lsu_gs_sig : std_ulogic; +signal mm_xu_lsu_ind_sig : std_ulogic; +signal mm_xu_lsu_lbit_sig : std_ulogic; +signal xu_mm_ex2_eff_addr_sig : std_ulogic_vector(64-rs_data_width to 63); +signal repr_scan_int : std_ulogic_vector(0 to 5); +signal time_scan_int : std_ulogic_vector(0 to 5); +signal abst_scan_int : std_ulogic_vector(0 to 6); +signal tlbwe_back_inv_valid_sig : std_ulogic; +signal tlbwe_back_inv_thdid_sig : std_ulogic_vector(0 to thdid_width-1); +signal tlbwe_back_inv_addr_sig : std_ulogic_vector(52-epn_width to 51); +signal tlbwe_back_inv_attr_sig : std_ulogic_vector(0 to 34); +signal tlbwe_back_inv_pending_sig : std_ulogic; +signal tlb_tag5_write : std_ulogic; +signal tlb_snoop_coming : std_ulogic; +signal tlb_snoop_val : std_ulogic; +signal tlb_snoop_attr : std_ulogic_vector(0 to 34); +signal tlb_snoop_vpn : std_ulogic_vector(52-epn_width to 51); +signal tlb_snoop_ack : std_ulogic; +signal mas0_0_atsel : std_ulogic; +signal mas0_0_esel : std_ulogic_vector(0 to 2); +signal mas0_0_hes : std_ulogic; +signal mas0_0_wq : std_ulogic_vector(0 to 1); +signal mas1_0_v : std_ulogic; +signal mas1_0_iprot : std_ulogic; +signal mas1_0_tid : std_ulogic_vector(0 to 13); +signal mas1_0_ind : std_ulogic; +signal mas1_0_ts : std_ulogic; +signal mas1_0_tsize : std_ulogic_vector(0 to 3); +signal mas2_0_epn : std_ulogic_vector(0 to 51); +signal mas2_0_wimge : std_ulogic_vector(0 to 4); +signal mas3_0_rpnl : std_ulogic_vector(32 to 52); +signal mas3_0_ubits : std_ulogic_vector(0 to 3); +signal mas3_0_usxwr : std_ulogic_vector(0 to 5); +signal mas5_0_sgs : std_ulogic; +signal mas5_0_slpid : std_ulogic_vector(0 to 7); +signal mas6_0_spid : std_ulogic_vector(0 to 13); +signal mas6_0_isize : std_ulogic_vector(0 to 3); +signal mas6_0_sind : std_ulogic; +signal mas6_0_sas : std_ulogic; +signal mas7_0_rpnu : std_ulogic_vector(22 to 31); +signal mas8_0_tgs : std_ulogic; +signal mas8_0_vf : std_ulogic; +signal mas8_0_tlpid : std_ulogic_vector(0 to 7); +signal mas0_1_atsel : std_ulogic; +signal mas0_1_esel : std_ulogic_vector(0 to 2); +signal mas0_1_hes : std_ulogic; +signal mas0_1_wq : std_ulogic_vector(0 to 1); +signal mas1_1_v : std_ulogic; +signal mas1_1_iprot : std_ulogic; +signal mas1_1_tid : std_ulogic_vector(0 to 13); +signal mas1_1_ind : std_ulogic; +signal mas1_1_ts : std_ulogic; +signal mas1_1_tsize : std_ulogic_vector(0 to 3); +signal mas2_1_epn : std_ulogic_vector(0 to 51); +signal mas2_1_wimge : std_ulogic_vector(0 to 4); +signal mas3_1_rpnl : std_ulogic_vector(32 to 52); +signal mas3_1_ubits : std_ulogic_vector(0 to 3); +signal mas3_1_usxwr : std_ulogic_vector(0 to 5); +signal mas5_1_sgs : std_ulogic; +signal mas5_1_slpid : std_ulogic_vector(0 to 7); +signal mas6_1_spid : std_ulogic_vector(0 to 13); +signal mas6_1_isize : std_ulogic_vector(0 to 3); +signal mas6_1_sind : std_ulogic; +signal mas6_1_sas : std_ulogic; +signal mas7_1_rpnu : std_ulogic_vector(22 to 31); +signal mas8_1_tgs : std_ulogic; +signal mas8_1_vf : std_ulogic; +signal mas8_1_tlpid : std_ulogic_vector(0 to 7); +signal mas0_2_atsel : std_ulogic; +signal mas0_2_esel : std_ulogic_vector(0 to 2); +signal mas0_2_hes : std_ulogic; +signal mas0_2_wq : std_ulogic_vector(0 to 1); +signal mas1_2_v : std_ulogic; +signal mas1_2_iprot : std_ulogic; +signal mas1_2_tid : std_ulogic_vector(0 to 13); +signal mas1_2_ind : std_ulogic; +signal mas1_2_ts : std_ulogic; +signal mas1_2_tsize : std_ulogic_vector(0 to 3); +signal mas2_2_epn : std_ulogic_vector(0 to 51); +signal mas2_2_wimge : std_ulogic_vector(0 to 4); +signal mas3_2_rpnl : std_ulogic_vector(32 to 52); +signal mas3_2_ubits : std_ulogic_vector(0 to 3); +signal mas3_2_usxwr : std_ulogic_vector(0 to 5); +signal mas5_2_sgs : std_ulogic; +signal mas5_2_slpid : std_ulogic_vector(0 to 7); +signal mas6_2_spid : std_ulogic_vector(0 to 13); +signal mas6_2_isize : std_ulogic_vector(0 to 3); +signal mas6_2_sind : std_ulogic; +signal mas6_2_sas : std_ulogic; +signal mas7_2_rpnu : std_ulogic_vector(22 to 31); +signal mas8_2_tgs : std_ulogic; +signal mas8_2_vf : std_ulogic; +signal mas8_2_tlpid : std_ulogic_vector(0 to 7); +signal mas0_3_atsel : std_ulogic; +signal mas0_3_esel : std_ulogic_vector(0 to 2); +signal mas0_3_hes : std_ulogic; +signal mas0_3_wq : std_ulogic_vector(0 to 1); +signal mas1_3_v : std_ulogic; +signal mas1_3_iprot : std_ulogic; +signal mas1_3_tid : std_ulogic_vector(0 to 13); +signal mas1_3_ind : std_ulogic; +signal mas1_3_ts : std_ulogic; +signal mas1_3_tsize : std_ulogic_vector(0 to 3); +signal mas2_3_epn : std_ulogic_vector(0 to 51); +signal mas2_3_wimge : std_ulogic_vector(0 to 4); +signal mas3_3_rpnl : std_ulogic_vector(32 to 52); +signal mas3_3_ubits : std_ulogic_vector(0 to 3); +signal mas3_3_usxwr : std_ulogic_vector(0 to 5); +signal mas5_3_sgs : std_ulogic; +signal mas5_3_slpid : std_ulogic_vector(0 to 7); +signal mas6_3_spid : std_ulogic_vector(0 to 13); +signal mas6_3_isize : std_ulogic_vector(0 to 3); +signal mas6_3_sind : std_ulogic; +signal mas6_3_sas : std_ulogic; +signal mas7_3_rpnu : std_ulogic_vector(22 to 31); +signal mas8_3_tgs : std_ulogic; +signal mas8_3_vf : std_ulogic; +signal mas8_3_tlpid : std_ulogic_vector(0 to 7); +signal mmucfg_lrat : std_ulogic; +signal mmucfg_twc : std_ulogic; +signal mmucsr0_tlb0fi : std_ulogic; +signal mmq_inval_tlb0fi_done : std_ulogic; +signal tlb0cfg_pt : std_ulogic; +signal tlb0cfg_ind : std_ulogic; +signal tlb0cfg_gtwe : std_ulogic; +signal tlb_mas0_esel : std_ulogic_vector(0 to 2); +signal tlb_mas1_v : std_ulogic; +signal tlb_mas1_iprot : std_ulogic; +signal tlb_mas1_tid : std_ulogic_vector(0 to pid_width-1); +signal tlb_mas1_tid_error : std_ulogic_vector(0 to pid_width-1); +signal tlb_mas1_ind : std_ulogic; +signal tlb_mas1_ts : std_ulogic; +signal tlb_mas1_ts_error : std_ulogic; +signal tlb_mas1_tsize : std_ulogic_vector(0 to 3); +signal tlb_mas2_epn : std_ulogic_vector(0 to 51); +signal tlb_mas2_epn_error : std_ulogic_vector(0 to 51); +signal tlb_mas2_wimge : std_ulogic_vector(0 to 4); +signal tlb_mas3_rpnl : std_ulogic_vector(32 to 51); +signal tlb_mas3_ubits : std_ulogic_vector(0 to 3); +signal tlb_mas3_usxwr : std_ulogic_vector(0 to 5); +signal tlb_mas6_spid : std_ulogic_vector(0 to pid_width-1); +signal tlb_mas6_isize : std_ulogic_vector(0 to 3); +signal tlb_mas6_sind : std_ulogic; +signal tlb_mas6_sas : std_ulogic; +signal tlb_mas7_rpnu : std_ulogic_vector(22 to 31); +signal tlb_mas8_tgs : std_ulogic; +signal tlb_mas8_vf : std_ulogic; +signal tlb_mas8_tlpid : std_ulogic_vector(0 to 7); +signal tlb_mmucr1_een : std_ulogic_vector(0 to 8); +signal tlb_mmucr1_we : std_ulogic; +signal tlb_mmucr3_thdid : std_ulogic_vector(0 to thdid_width-1); +signal tlb_mmucr3_resvattr : std_ulogic; +signal tlb_mmucr3_wlc : std_ulogic_vector(0 to 1); +signal tlb_mmucr3_class : std_ulogic_vector(0 to class_width-1); +signal tlb_mmucr3_extclass : std_ulogic_vector(0 to extclass_width-1); +signal tlb_mmucr3_rc : std_ulogic_vector(0 to 1); +signal tlb_mmucr3_x : std_ulogic; +signal tlb_mas_tlbre : std_ulogic; +signal tlb_mas_tlbsx_hit : std_ulogic; +signal tlb_mas_tlbsx_miss : std_ulogic; +signal tlb_mas_dtlb_error : std_ulogic; +signal tlb_mas_itlb_error : std_ulogic; +signal tlb_mas_thdid : std_ulogic_vector(0 to 3); +signal lrat_mas0_esel : std_ulogic_vector(0 to 2); +signal lrat_mas1_v : std_ulogic; +signal lrat_mas1_tsize : std_ulogic_vector(0 to 3); +signal lrat_mas2_epn : std_ulogic_vector(0 to 51); +signal lrat_mas3_rpnl : std_ulogic_vector(32 to 51); +signal lrat_mas7_rpnu : std_ulogic_vector(22 to 31); +signal lrat_mas8_tlpid : std_ulogic_vector(0 to lpid_width-1); +signal lrat_mmucr3_x : std_ulogic; +signal lrat_mas_tlbre : std_ulogic; +signal lrat_mas_tlbsx_hit : std_ulogic; +signal lrat_mas_tlbsx_miss : std_ulogic; +signal lrat_mas_thdid : std_ulogic_vector(0 to 3); +signal lrat_tag3_lpn : std_ulogic_vector(64-real_addr_width to 51); +signal lrat_tag3_rpn : std_ulogic_vector(64-real_addr_width to 51); +signal lrat_tag3_hit_status : std_ulogic_vector(0 to 3); +signal lrat_tag3_hit_entry : std_ulogic_vector(0 to lrat_num_entry_log2-1); +signal lrat_tag4_lpn : std_ulogic_vector(64-real_addr_width to 51); +signal lrat_tag4_rpn : std_ulogic_vector(64-real_addr_width to 51); +signal lrat_tag4_hit_status : std_ulogic_vector(0 to 3); +signal lrat_tag4_hit_entry : std_ulogic_vector(0 to lrat_num_entry_log2-1); +signal tlb_tag0_epn : std_ulogic_vector(52-epn_width to 51); +signal tlb_tag0_thdid : std_ulogic_vector(0 to thdid_width-1); +signal tlb_tag0_type : std_ulogic_vector(0 to 7); +signal tlb_tag0_lpid : std_ulogic_vector(0 to lpid_width-1); +signal tlb_tag0_atsel : std_ulogic; +signal tlb_tag0_size : std_ulogic_vector(0 to 3); +signal tlb_tag0_addr_cap : std_ulogic; +signal pte_tag0_lpn : std_ulogic_vector(64-real_addr_width to 51); +signal pte_tag0_lpid : std_ulogic_vector(0 to lpid_width-1); +signal tlb_lper_lpn : std_ulogic_vector(64-real_addr_width to 51); +signal tlb_lper_lps : std_ulogic_vector(60 to 63); +signal tlb_lper_we : std_ulogic_vector(0 to thdid_width-1); +signal ierat_req0_pid_sig : std_ulogic_vector(0 to pid_width-1); +signal ierat_req0_as_sig : std_ulogic; +signal ierat_req0_gs_sig : std_ulogic; +signal ierat_req0_epn_sig : std_ulogic_vector(0 to epn_width-1); +signal ierat_req0_thdid_sig : std_ulogic_vector(0 to thdid_width-1); +signal ierat_req0_valid_sig : std_ulogic; +signal ierat_req0_nonspec_sig : std_ulogic; +signal ierat_req1_pid_sig : std_ulogic_vector(0 to pid_width-1); +signal ierat_req1_as_sig : std_ulogic; +signal ierat_req1_gs_sig : std_ulogic; +signal ierat_req1_epn_sig : std_ulogic_vector(0 to epn_width-1); +signal ierat_req1_thdid_sig : std_ulogic_vector(0 to thdid_width-1); +signal ierat_req1_valid_sig : std_ulogic; +signal ierat_req1_nonspec_sig : std_ulogic; +signal ierat_req2_pid_sig : std_ulogic_vector(0 to pid_width-1); +signal ierat_req2_as_sig : std_ulogic; +signal ierat_req2_gs_sig : std_ulogic; +signal ierat_req2_epn_sig : std_ulogic_vector(0 to epn_width-1); +signal ierat_req2_thdid_sig : std_ulogic_vector(0 to thdid_width-1); +signal ierat_req2_valid_sig : std_ulogic; +signal ierat_req2_nonspec_sig : std_ulogic; +signal ierat_req3_pid_sig : std_ulogic_vector(0 to pid_width-1); +signal ierat_req3_as_sig : std_ulogic; +signal ierat_req3_gs_sig : std_ulogic; +signal ierat_req3_epn_sig : std_ulogic_vector(0 to epn_width-1); +signal ierat_req3_thdid_sig : std_ulogic_vector(0 to thdid_width-1); +signal ierat_req3_valid_sig : std_ulogic; +signal ierat_req3_nonspec_sig : std_ulogic; +signal ierat_iu4_pid_sig : std_ulogic_vector(0 to pid_width-1); +signal ierat_iu4_gs_sig : std_ulogic; +signal ierat_iu4_as_sig : std_ulogic; +signal ierat_iu4_epn_sig : std_ulogic_vector(0 to epn_width-1); +signal ierat_iu4_thdid_sig : std_ulogic_vector(0 to thdid_width-1); +signal ierat_iu4_valid_sig : std_ulogic; +signal derat_req0_lpid_sig : std_ulogic_vector(0 to lpid_width-1); +signal derat_req0_pid_sig : std_ulogic_vector(0 to pid_width-1); +signal derat_req0_as_sig : std_ulogic; +signal derat_req0_gs_sig : std_ulogic; +signal derat_req0_epn_sig : std_ulogic_vector(0 to epn_width-1); +signal derat_req0_thdid_sig : std_ulogic_vector(0 to thdid_width-1); +signal derat_req0_valid_sig : std_ulogic; +signal derat_req1_lpid_sig : std_ulogic_vector(0 to lpid_width-1); +signal derat_req1_pid_sig : std_ulogic_vector(0 to pid_width-1); +signal derat_req1_as_sig : std_ulogic; +signal derat_req1_gs_sig : std_ulogic; +signal derat_req1_epn_sig : std_ulogic_vector(0 to epn_width-1); +signal derat_req1_thdid_sig : std_ulogic_vector(0 to thdid_width-1); +signal derat_req1_valid_sig : std_ulogic; +signal derat_req2_lpid_sig : std_ulogic_vector(0 to lpid_width-1); +signal derat_req2_pid_sig : std_ulogic_vector(0 to pid_width-1); +signal derat_req2_as_sig : std_ulogic; +signal derat_req2_gs_sig : std_ulogic; +signal derat_req2_epn_sig : std_ulogic_vector(0 to epn_width-1); +signal derat_req2_thdid_sig : std_ulogic_vector(0 to thdid_width-1); +signal derat_req2_valid_sig : std_ulogic; +signal derat_req3_lpid_sig : std_ulogic_vector(0 to lpid_width-1); +signal derat_req3_pid_sig : std_ulogic_vector(0 to pid_width-1); +signal derat_req3_as_sig : std_ulogic; +signal derat_req3_gs_sig : std_ulogic; +signal derat_req3_epn_sig : std_ulogic_vector(0 to epn_width-1); +signal derat_req3_thdid_sig : std_ulogic_vector(0 to thdid_width-1); +signal derat_req3_valid_sig : std_ulogic; +signal derat_ex5_lpid_sig : std_ulogic_vector(0 to lpid_width-1); +signal derat_ex5_pid_sig : std_ulogic_vector(0 to pid_width-1); +signal derat_ex5_gs_sig : std_ulogic; +signal derat_ex5_as_sig : std_ulogic; +signal derat_ex5_epn_sig : std_ulogic_vector(0 to epn_width-1); +signal derat_ex5_thdid_sig : std_ulogic_vector(0 to thdid_width-1); +signal derat_ex5_valid_sig : std_ulogic; +signal tlb_cmp_perf_event_t0 : std_ulogic_vector(0 to 9); +signal tlb_cmp_perf_event_t1 : std_ulogic_vector(0 to 9); +signal tlb_cmp_perf_event_t2 : std_ulogic_vector(0 to 9); +signal tlb_cmp_perf_event_t3 : std_ulogic_vector(0 to 9); +signal tlb_cmp_perf_state : std_ulogic_vector(0 to 1); +signal tlb_cmp_perf_miss_direct : std_ulogic; +signal tlb_cmp_perf_hit_indirect : std_ulogic; +signal tlb_cmp_perf_hit_first_page : std_ulogic; +signal tlb_cmp_perf_ptereload_noexcep : std_ulogic; +signal tlb_cmp_perf_lrat_request : std_ulogic; +signal tlb_cmp_perf_lrat_miss : std_ulogic; +signal tlb_cmp_perf_pt_fault : std_ulogic; +signal tlb_cmp_perf_pt_inelig : std_ulogic; +signal tlb_ctl_perf_tlbwec_resv : std_ulogic; +signal tlb_ctl_perf_tlbwec_noresv : std_ulogic; +signal inval_perf_tlbilx : std_ulogic; +signal inval_perf_tlbivax : std_ulogic; +signal inval_perf_tlbivax_snoop : std_ulogic; +signal inval_perf_tlb_flush : std_ulogic; +signal spr_dbg_match_64b : std_ulogic; +signal spr_dbg_match_any_mmu : std_ulogic; +signal spr_dbg_match_any_mas : std_ulogic; +signal spr_dbg_match_pid : std_ulogic; +signal spr_dbg_match_lpidr : std_ulogic; +signal spr_dbg_match_mmucr0 : std_ulogic; +signal spr_dbg_match_mmucr1 : std_ulogic; +signal spr_dbg_match_mmucr2 : std_ulogic; +signal spr_dbg_match_mmucr3 : std_ulogic; +signal spr_dbg_match_mmucsr0 : std_ulogic; +signal spr_dbg_match_mmucfg : std_ulogic; +signal spr_dbg_match_tlb0cfg : std_ulogic; +signal spr_dbg_match_tlb0ps : std_ulogic; +signal spr_dbg_match_lratcfg : std_ulogic; +signal spr_dbg_match_lratps : std_ulogic; +signal spr_dbg_match_eptcfg : std_ulogic; +signal spr_dbg_match_lper : std_ulogic; +signal spr_dbg_match_lperu : std_ulogic; +signal spr_dbg_match_mas0 : std_ulogic; +signal spr_dbg_match_mas1 : std_ulogic; +signal spr_dbg_match_mas2 : std_ulogic; +signal spr_dbg_match_mas2u : std_ulogic; +signal spr_dbg_match_mas3 : std_ulogic; +signal spr_dbg_match_mas4 : std_ulogic; +signal spr_dbg_match_mas5 : std_ulogic; +signal spr_dbg_match_mas6 : std_ulogic; +signal spr_dbg_match_mas7 : std_ulogic; +signal spr_dbg_match_mas8 : std_ulogic; +signal spr_dbg_match_mas01_64b : std_ulogic; +signal spr_dbg_match_mas56_64b : std_ulogic; +signal spr_dbg_match_mas73_64b : std_ulogic; +signal spr_dbg_match_mas81_64b : std_ulogic; +signal spr_dbg_slowspr_val_int : std_ulogic; +signal spr_dbg_slowspr_rw_int : std_ulogic; +signal spr_dbg_slowspr_etid_int : std_ulogic_vector(0 to 1); +signal spr_dbg_slowspr_addr_int : std_ulogic_vector(0 to 9); +signal spr_dbg_slowspr_val_out : std_ulogic; +signal spr_dbg_slowspr_done_out : std_ulogic; +signal spr_dbg_slowspr_data_out : std_ulogic_vector(64-spr_data_width to 63); +signal inval_dbg_seq_q : std_ulogic_vector(0 to 4); +signal inval_dbg_seq_idle : std_ulogic; +signal inval_dbg_seq_snoop_inprogress : std_ulogic; +signal inval_dbg_seq_snoop_done : std_ulogic; +signal inval_dbg_seq_local_done : std_ulogic; +signal inval_dbg_seq_tlb0fi_done : std_ulogic; +signal inval_dbg_seq_tlbwe_snoop_done : std_ulogic; +signal inval_dbg_ex6_valid : std_ulogic; +signal inval_dbg_ex6_thdid : std_ulogic_vector(0 to 1); +signal inval_dbg_ex6_ttype : std_ulogic_vector(0 to 2); +signal inval_dbg_snoop_forme : std_ulogic; +signal inval_dbg_snoop_local_reject : std_ulogic; +signal inval_dbg_an_ac_back_inv_q : std_ulogic_vector(2 to 8); +signal inval_dbg_an_ac_back_inv_lpar_id_q : std_ulogic_vector(0 to 7); +signal inval_dbg_an_ac_back_inv_addr_q : std_ulogic_vector(22 to 63); +signal inval_dbg_snoop_valid_q : std_ulogic_vector(0 to 2); +signal inval_dbg_snoop_ack_q : std_ulogic_vector(0 to 2); +signal inval_dbg_snoop_attr_q : std_ulogic_vector(0 to 34); +signal inval_dbg_snoop_attr_tlb_spec_q : std_ulogic_vector(18 to 19); +signal inval_dbg_snoop_vpn_q : std_ulogic_vector(17 to 51); +signal inval_dbg_lsu_tokens_q : std_ulogic_vector(0 to 1); +signal tlb_req_dbg_ierat_iu5_valid_q : std_ulogic; +signal tlb_req_dbg_ierat_iu5_thdid : std_ulogic_vector(0 to 1); +signal tlb_req_dbg_ierat_iu5_state_q : std_ulogic_vector(0 to 3); +signal tlb_req_dbg_ierat_inptr_q : std_ulogic_vector(0 to 1); +signal tlb_req_dbg_ierat_outptr_q : std_ulogic_vector(0 to 1); +signal tlb_req_dbg_ierat_req_valid_q : std_ulogic_vector(0 to 3); +signal tlb_req_dbg_ierat_req_nonspec_q : std_ulogic_vector(0 to 3); +signal tlb_req_dbg_ierat_req_thdid : std_ulogic_vector(0 to 7); +signal tlb_req_dbg_ierat_req_dup_q : std_ulogic_vector(0 to 3); +signal tlb_req_dbg_derat_ex6_valid_q : std_ulogic; +signal tlb_req_dbg_derat_ex6_thdid : std_ulogic_vector(0 to 1); +signal tlb_req_dbg_derat_ex6_state_q : std_ulogic_vector(0 to 3); +signal tlb_req_dbg_derat_inptr_q : std_ulogic_vector(0 to 1); +signal tlb_req_dbg_derat_outptr_q : std_ulogic_vector(0 to 1); +signal tlb_req_dbg_derat_req_valid_q : std_ulogic_vector(0 to 3); +signal tlb_req_dbg_derat_req_thdid : std_ulogic_vector(0 to 7); +signal tlb_req_dbg_derat_req_ttype_q : std_ulogic_vector(0 to 7); +signal tlb_req_dbg_derat_req_dup_q : std_ulogic_vector(0 to 3); +signal tlb_ctl_dbg_seq_q : std_ulogic_vector(0 to 5); +signal tlb_ctl_dbg_seq_idle : std_ulogic; +signal tlb_ctl_dbg_seq_any_done_sig : std_ulogic; +signal tlb_ctl_dbg_seq_abort : std_ulogic; +signal tlb_ctl_dbg_any_tlb_req_sig : std_ulogic; +signal tlb_ctl_dbg_any_req_taken_sig : std_ulogic; +signal tlb_ctl_dbg_tag0_valid : std_ulogic; +signal tlb_ctl_dbg_tag0_thdid : std_ulogic_vector(0 to 1); +signal tlb_ctl_dbg_tag0_type : std_ulogic_vector(0 to 2); +signal tlb_ctl_dbg_tag0_wq : std_ulogic_vector(0 to 1); +signal tlb_ctl_dbg_tag0_gs : std_ulogic; +signal tlb_ctl_dbg_tag0_pr : std_ulogic; +signal tlb_ctl_dbg_tag0_atsel : std_ulogic; +signal tlb_ctl_dbg_tag5_tlb_write_q : std_ulogic_vector(0 to 3); +signal tlb_ctl_dbg_resv_valid : std_ulogic_vector(0 to 3); +signal tlb_ctl_dbg_set_resv : std_ulogic_vector(0 to 3); +signal tlb_ctl_dbg_resv_match_vec_q : std_ulogic_vector(0 to 3); +signal tlb_ctl_dbg_any_tag_flush_sig : std_ulogic; +signal tlb_ctl_dbg_resv0_tag0_lpid_match : std_ulogic; +signal tlb_ctl_dbg_resv0_tag0_pid_match : std_ulogic; +signal tlb_ctl_dbg_resv0_tag0_as_snoop_match : std_ulogic; +signal tlb_ctl_dbg_resv0_tag0_gs_snoop_match : std_ulogic; +signal tlb_ctl_dbg_resv0_tag0_as_tlbwe_match : std_ulogic; +signal tlb_ctl_dbg_resv0_tag0_gs_tlbwe_match : std_ulogic; +signal tlb_ctl_dbg_resv0_tag0_ind_match : std_ulogic; +signal tlb_ctl_dbg_resv0_tag0_epn_loc_match : std_ulogic; +signal tlb_ctl_dbg_resv0_tag0_epn_glob_match : std_ulogic; +signal tlb_ctl_dbg_resv0_tag0_class_match : std_ulogic; +signal tlb_ctl_dbg_resv1_tag0_lpid_match : std_ulogic; +signal tlb_ctl_dbg_resv1_tag0_pid_match : std_ulogic; +signal tlb_ctl_dbg_resv1_tag0_as_snoop_match : std_ulogic; +signal tlb_ctl_dbg_resv1_tag0_gs_snoop_match : std_ulogic; +signal tlb_ctl_dbg_resv1_tag0_as_tlbwe_match : std_ulogic; +signal tlb_ctl_dbg_resv1_tag0_gs_tlbwe_match : std_ulogic; +signal tlb_ctl_dbg_resv1_tag0_ind_match : std_ulogic; +signal tlb_ctl_dbg_resv1_tag0_epn_loc_match : std_ulogic; +signal tlb_ctl_dbg_resv1_tag0_epn_glob_match : std_ulogic; +signal tlb_ctl_dbg_resv1_tag0_class_match : std_ulogic; +signal tlb_ctl_dbg_resv2_tag0_lpid_match : std_ulogic; +signal tlb_ctl_dbg_resv2_tag0_pid_match : std_ulogic; +signal tlb_ctl_dbg_resv2_tag0_as_snoop_match : std_ulogic; +signal tlb_ctl_dbg_resv2_tag0_gs_snoop_match : std_ulogic; +signal tlb_ctl_dbg_resv2_tag0_as_tlbwe_match : std_ulogic; +signal tlb_ctl_dbg_resv2_tag0_gs_tlbwe_match : std_ulogic; +signal tlb_ctl_dbg_resv2_tag0_ind_match : std_ulogic; +signal tlb_ctl_dbg_resv2_tag0_epn_loc_match : std_ulogic; +signal tlb_ctl_dbg_resv2_tag0_epn_glob_match : std_ulogic; +signal tlb_ctl_dbg_resv2_tag0_class_match : std_ulogic; +signal tlb_ctl_dbg_resv3_tag0_lpid_match : std_ulogic; +signal tlb_ctl_dbg_resv3_tag0_pid_match : std_ulogic; +signal tlb_ctl_dbg_resv3_tag0_as_snoop_match : std_ulogic; +signal tlb_ctl_dbg_resv3_tag0_gs_snoop_match : std_ulogic; +signal tlb_ctl_dbg_resv3_tag0_as_tlbwe_match : std_ulogic; +signal tlb_ctl_dbg_resv3_tag0_gs_tlbwe_match : std_ulogic; +signal tlb_ctl_dbg_resv3_tag0_ind_match : std_ulogic; +signal tlb_ctl_dbg_resv3_tag0_epn_loc_match : std_ulogic; +signal tlb_ctl_dbg_resv3_tag0_epn_glob_match : std_ulogic; +signal tlb_ctl_dbg_resv3_tag0_class_match : std_ulogic; +signal tlb_ctl_dbg_clr_resv_q : std_ulogic_vector(0 to 3); +signal tlb_ctl_dbg_clr_resv_terms : std_ulogic_vector(0 to 3); +signal tlb_cmp_dbg_tag4 : std_ulogic_vector(0 to tlb_tag_width-1); +signal tlb_cmp_dbg_tag4_wayhit : std_ulogic_vector(0 to tlb_ways); +signal tlb_cmp_dbg_addr4 : std_ulogic_vector(0 to tlb_addr_width-1); +signal tlb_cmp_dbg_tag4_way : std_ulogic_vector(0 to tlb_way_width-1); +signal tlb_cmp_dbg_tag4_parerr : std_ulogic_vector(0 to 4); +signal tlb_cmp_dbg_tag4_lru_dataout_q : std_ulogic_vector(0 to lru_width-5); +signal tlb_cmp_dbg_tag5_tlb_datain_q : std_ulogic_vector(0 to tlb_way_width-1); +signal tlb_cmp_dbg_tag5_lru_datain_q : std_ulogic_vector(0 to lru_width-5); +signal tlb_cmp_dbg_tag5_lru_write : std_ulogic; +signal tlb_cmp_dbg_tag5_any_exception : std_ulogic; +signal tlb_cmp_dbg_tag5_except_type_q : std_ulogic_vector(0 to 3); +signal tlb_cmp_dbg_tag5_except_thdid_q : std_ulogic_vector(0 to 1); +signal tlb_cmp_dbg_tag5_erat_rel_val : std_ulogic_vector(0 to 9); +signal tlb_cmp_dbg_tag5_erat_rel_data : std_ulogic_vector(0 to 131); +signal tlb_cmp_dbg_erat_dup_q : std_ulogic_vector(0 to 19); +signal tlb_cmp_dbg_addr_enable : std_ulogic_vector(0 to 8); +signal tlb_cmp_dbg_pgsize_enable : std_ulogic; +signal tlb_cmp_dbg_class_enable : std_ulogic; +signal tlb_cmp_dbg_extclass_enable : std_ulogic_vector(0 to 1); +signal tlb_cmp_dbg_state_enable : std_ulogic_vector(0 to 1); +signal tlb_cmp_dbg_thdid_enable : std_ulogic; +signal tlb_cmp_dbg_pid_enable : std_ulogic; +signal tlb_cmp_dbg_lpid_enable : std_ulogic; +signal tlb_cmp_dbg_ind_enable : std_ulogic; +signal tlb_cmp_dbg_iprot_enable : std_ulogic; +signal tlb_cmp_dbg_way0_entry_v : std_ulogic; +signal tlb_cmp_dbg_way0_addr_match : std_ulogic; +signal tlb_cmp_dbg_way0_pgsize_match : std_ulogic; +signal tlb_cmp_dbg_way0_class_match : std_ulogic; +signal tlb_cmp_dbg_way0_extclass_match : std_ulogic; +signal tlb_cmp_dbg_way0_state_match : std_ulogic; +signal tlb_cmp_dbg_way0_thdid_match : std_ulogic; +signal tlb_cmp_dbg_way0_pid_match : std_ulogic; +signal tlb_cmp_dbg_way0_lpid_match : std_ulogic; +signal tlb_cmp_dbg_way0_ind_match : std_ulogic; +signal tlb_cmp_dbg_way0_iprot_match : std_ulogic; +signal tlb_cmp_dbg_way1_entry_v : std_ulogic; +signal tlb_cmp_dbg_way1_addr_match : std_ulogic; +signal tlb_cmp_dbg_way1_pgsize_match : std_ulogic; +signal tlb_cmp_dbg_way1_class_match : std_ulogic; +signal tlb_cmp_dbg_way1_extclass_match : std_ulogic; +signal tlb_cmp_dbg_way1_state_match : std_ulogic; +signal tlb_cmp_dbg_way1_thdid_match : std_ulogic; +signal tlb_cmp_dbg_way1_pid_match : std_ulogic; +signal tlb_cmp_dbg_way1_lpid_match : std_ulogic; +signal tlb_cmp_dbg_way1_ind_match : std_ulogic; +signal tlb_cmp_dbg_way1_iprot_match : std_ulogic; +signal tlb_cmp_dbg_way2_entry_v : std_ulogic; +signal tlb_cmp_dbg_way2_addr_match : std_ulogic; +signal tlb_cmp_dbg_way2_pgsize_match : std_ulogic; +signal tlb_cmp_dbg_way2_class_match : std_ulogic; +signal tlb_cmp_dbg_way2_extclass_match : std_ulogic; +signal tlb_cmp_dbg_way2_state_match : std_ulogic; +signal tlb_cmp_dbg_way2_thdid_match : std_ulogic; +signal tlb_cmp_dbg_way2_pid_match : std_ulogic; +signal tlb_cmp_dbg_way2_lpid_match : std_ulogic; +signal tlb_cmp_dbg_way2_ind_match : std_ulogic; +signal tlb_cmp_dbg_way2_iprot_match : std_ulogic; +signal tlb_cmp_dbg_way3_entry_v : std_ulogic; +signal tlb_cmp_dbg_way3_addr_match : std_ulogic; +signal tlb_cmp_dbg_way3_pgsize_match : std_ulogic; +signal tlb_cmp_dbg_way3_class_match : std_ulogic; +signal tlb_cmp_dbg_way3_extclass_match : std_ulogic; +signal tlb_cmp_dbg_way3_state_match : std_ulogic; +signal tlb_cmp_dbg_way3_thdid_match : std_ulogic; +signal tlb_cmp_dbg_way3_pid_match : std_ulogic; +signal tlb_cmp_dbg_way3_lpid_match : std_ulogic; +signal tlb_cmp_dbg_way3_ind_match : std_ulogic; +signal tlb_cmp_dbg_way3_iprot_match : std_ulogic; +signal lrat_dbg_tag1_addr_enable : std_ulogic; +signal lrat_dbg_tag2_matchline_q : std_ulogic_vector(0 to 7); +signal lrat_dbg_entry0_addr_match : std_ulogic; +signal lrat_dbg_entry0_lpid_match : std_ulogic; +signal lrat_dbg_entry0_entry_v : std_ulogic; +signal lrat_dbg_entry0_entry_x : std_ulogic; +signal lrat_dbg_entry0_size : std_ulogic_vector(0 to 3); +signal lrat_dbg_entry1_addr_match : std_ulogic; +signal lrat_dbg_entry1_lpid_match : std_ulogic; +signal lrat_dbg_entry1_entry_v : std_ulogic; +signal lrat_dbg_entry1_entry_x : std_ulogic; +signal lrat_dbg_entry1_size : std_ulogic_vector(0 to 3); +signal lrat_dbg_entry2_addr_match : std_ulogic; +signal lrat_dbg_entry2_lpid_match : std_ulogic; +signal lrat_dbg_entry2_entry_v : std_ulogic; +signal lrat_dbg_entry2_entry_x : std_ulogic; +signal lrat_dbg_entry2_size : std_ulogic_vector(0 to 3); +signal lrat_dbg_entry3_addr_match : std_ulogic; +signal lrat_dbg_entry3_lpid_match : std_ulogic; +signal lrat_dbg_entry3_entry_v : std_ulogic; +signal lrat_dbg_entry3_entry_x : std_ulogic; +signal lrat_dbg_entry3_size : std_ulogic_vector(0 to 3); +signal lrat_dbg_entry4_addr_match : std_ulogic; +signal lrat_dbg_entry4_lpid_match : std_ulogic; +signal lrat_dbg_entry4_entry_v : std_ulogic; +signal lrat_dbg_entry4_entry_x : std_ulogic; +signal lrat_dbg_entry4_size : std_ulogic_vector(0 to 3); +signal lrat_dbg_entry5_addr_match : std_ulogic; +signal lrat_dbg_entry5_lpid_match : std_ulogic; +signal lrat_dbg_entry5_entry_v : std_ulogic; +signal lrat_dbg_entry5_entry_x : std_ulogic; +signal lrat_dbg_entry5_size : std_ulogic_vector(0 to 3); +signal lrat_dbg_entry6_addr_match : std_ulogic; +signal lrat_dbg_entry6_lpid_match : std_ulogic; +signal lrat_dbg_entry6_entry_v : std_ulogic; +signal lrat_dbg_entry6_entry_x : std_ulogic; +signal lrat_dbg_entry6_size : std_ulogic_vector(0 to 3); +signal lrat_dbg_entry7_addr_match : std_ulogic; +signal lrat_dbg_entry7_lpid_match : std_ulogic; +signal lrat_dbg_entry7_entry_v : std_ulogic; +signal lrat_dbg_entry7_entry_x : std_ulogic; +signal lrat_dbg_entry7_size : std_ulogic_vector(0 to 3); +signal htw_dbg_seq_idle : std_ulogic; +signal htw_dbg_pte0_seq_idle : std_ulogic; +signal htw_dbg_pte1_seq_idle : std_ulogic; +signal htw_dbg_seq_q : std_ulogic_vector(0 to 1); +signal htw_dbg_inptr_q : std_ulogic_vector(0 to 1); +signal htw_dbg_pte0_seq_q : std_ulogic_vector(0 to 2); +signal htw_dbg_pte1_seq_q : std_ulogic_vector(0 to 2); +signal htw_dbg_ptereload_ptr_q : std_ulogic; +signal htw_dbg_lsuptr_q : std_ulogic_vector(0 to 1); +signal htw_dbg_req_valid_q : std_ulogic_vector(0 to 3); +signal htw_dbg_resv_valid_vec : std_ulogic_vector(0 to 3); +signal htw_dbg_tag4_clr_resv_q : std_ulogic_vector(0 to 3); +signal htw_dbg_tag4_clr_resv_terms : std_ulogic_vector(0 to 3); +signal htw_dbg_pte0_score_ptr_q : std_ulogic_vector(0 to 1); +signal htw_dbg_pte0_score_cl_offset_q : std_ulogic_vector(58 to 60); +signal htw_dbg_pte0_score_error_q : std_ulogic_vector(0 to 2); +signal htw_dbg_pte0_score_qwbeat_q : std_ulogic_vector(0 to 3); +signal htw_dbg_pte0_score_pending_q : std_ulogic; +signal htw_dbg_pte0_score_ibit_q : std_ulogic; +signal htw_dbg_pte0_score_dataval_q : std_ulogic; +signal htw_dbg_pte0_reld_for_me_tm1 : std_ulogic; +signal htw_dbg_pte1_score_ptr_q : std_ulogic_vector(0 to 1); +signal htw_dbg_pte1_score_cl_offset_q : std_ulogic_vector(58 to 60); +signal htw_dbg_pte1_score_error_q : std_ulogic_vector(0 to 2); +signal htw_dbg_pte1_score_qwbeat_q : std_ulogic_vector(0 to 3); +signal htw_dbg_pte1_score_pending_q : std_ulogic; +signal htw_dbg_pte1_score_ibit_q : std_ulogic; +signal htw_dbg_pte1_score_dataval_q : std_ulogic; +signal htw_dbg_pte1_reld_for_me_tm1 : std_ulogic; +signal tlb_delayed_act : std_ulogic_vector(9 to 32); +signal unused_dc : std_ulogic_vector(0 to 70); +-- synopsys translate_off +-- synopsys translate_on +signal lcb_clkoff_dc_b : std_ulogic; +signal lcb_act_dis_dc : std_ulogic; +signal lcb_d_mode_dc : std_ulogic; +signal lcb_delay_lclkr_dc : std_ulogic_vector(0 to 4); +signal lcb_mpw1_dc_b : std_ulogic_vector(0 to 4); +signal lcb_mpw2_dc_b : std_ulogic; +signal g6t_gptr_lcb_clkoff_dc_b : std_ulogic; +signal g6t_gptr_lcb_act_dis_dc : std_ulogic; +signal g6t_gptr_lcb_d_mode_dc : std_ulogic; +signal g6t_gptr_lcb_delay_lclkr_dc : std_ulogic_vector(0 to 4); +signal g6t_gptr_lcb_mpw1_dc_b : std_ulogic_vector(0 to 4); +signal g6t_gptr_lcb_mpw2_dc_b : std_ulogic; +signal g8t_gptr_lcb_clkoff_dc_b : std_ulogic; +signal g8t_gptr_lcb_act_dis_dc : std_ulogic; +signal g8t_gptr_lcb_d_mode_dc : std_ulogic; +signal g8t_gptr_lcb_delay_lclkr_dc : std_ulogic_vector(0 to 4); +signal g8t_gptr_lcb_mpw1_dc_b : std_ulogic_vector(0 to 4); +signal g8t_gptr_lcb_mpw2_dc_b : std_ulogic; +signal pc_func_sl_thold_2 : std_ulogic_vector(0 to 1); +signal pc_func_slp_sl_thold_2 : std_ulogic_vector(0 to 1); +signal pc_func_slp_nsl_thold_2 : std_ulogic; +signal pc_fce_2 : std_ulogic; +signal pc_cfg_sl_thold_2 : std_ulogic; +signal pc_cfg_slp_sl_thold_2 : std_ulogic; +signal pc_sg_2 : std_ulogic_vector(0 to 1); +signal pc_sg_1 : std_ulogic_vector(0 to 1); +signal pc_sg_0 : std_ulogic_vector(0 to 1); +signal pc_func_sl_thold_0 : std_ulogic_vector(0 to 1); +signal pc_func_sl_thold_0_b : std_ulogic_vector(0 to 1); +signal pc_func_slp_sl_thold_0 : std_ulogic_vector(0 to 1); +signal pc_func_slp_sl_thold_0_b : std_ulogic_vector(0 to 1); +signal pc_abst_sl_thold_0 : std_ulogic; +signal pc_abst_slp_sl_thold_0 : std_ulogic; +signal pc_repr_sl_thold_0 : std_ulogic; +signal pc_time_sl_thold_0 : std_ulogic; +signal pc_ary_nsl_thold_0 : std_ulogic; +signal pc_ary_slp_nsl_thold_0 : std_ulogic; +signal pc_mm_bolt_sl_thold_0 : std_ulogic; +signal pc_mm_bo_enable_2 : std_ulogic; +signal pc_mm_abist_g8t_wenb_q : std_ulogic; +signal pc_mm_abist_g8t1p_renb_0_q : std_ulogic; +signal pc_mm_abist_di_0_q : std_ulogic_vector(0 to 3); +signal pc_mm_abist_g8t_bw_1_q : std_ulogic; +signal pc_mm_abist_g8t_bw_0_q : std_ulogic; +signal pc_mm_abist_waddr_0_q : std_ulogic_vector(0 to 9); +signal pc_mm_abist_raddr_0_q : std_ulogic_vector(0 to 9); +signal pc_mm_abist_wl128_comp_ena_q : std_ulogic; +signal pc_mm_abist_g8t_dcomp_q : std_ulogic_vector(0 to 3); +signal pc_mm_abist_dcomp_g6t_2r_q : std_ulogic_vector(0 to 3); +signal pc_mm_abist_di_g6t_2r_q : std_ulogic_vector(0 to 3); +signal pc_mm_abist_g6t_r_wb_q : std_ulogic; +signal time_scan_in_int : std_ulogic; +signal time_scan_out_int : std_ulogic; +signal func_scan_in_int : std_ulogic_vector(0 to 9); +signal func_scan_out_int : std_ulogic_vector(0 to 9); +signal repr_scan_in_int : std_ulogic; +signal repr_scan_out_int : std_ulogic; +signal abst_scan_in_int : std_ulogic_vector(0 to 1); +signal abst_scan_out_int : std_ulogic_vector(0 to 1); +signal bcfg_scan_in_int : std_ulogic; +signal bcfg_scan_out_int : std_ulogic; +signal ccfg_scan_in_int : std_ulogic; +signal ccfg_scan_out_int : std_ulogic; +signal dcfg_scan_in_int : std_ulogic; +signal dcfg_scan_out_int : std_ulogic; +signal siv_0 : std_ulogic_vector(0 to scan_right_0); +signal sov_0 : std_ulogic_vector(0 to scan_right_0); +signal siv_1 : std_ulogic_vector(0 to scan_right_1); +signal sov_1 : std_ulogic_vector(0 to scan_right_1); +signal bsiv : std_ulogic_vector(0 to boot_scan_right); +signal bsov : std_ulogic_vector(0 to boot_scan_right); +signal tidn : std_ulogic; +signal ac_an_psro_ringsig_b : std_ulogic; +begin +tidn <= '0'; +ac_an_lpar_id <= ac_an_lpar_id_sig; +mm_xu_lsu_lpidr <= lpidr_sig; +mmq_inval: entity work.mmq_inval(mmq_inval) + generic map ( rs_data_width => rs_data_width, + epn_width => epn_width, + real_addr_width => real_addr_width, + lpid_width => lpid_width, + expand_type => expand_type ) + port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + tc_ccflush_dc => tc_ac_ccflush_dc, + tc_scan_dis_dc_b => tc_ac_scan_dis_dc_b, + tc_scan_diag_dc => tc_ac_scan_diag_dc, + tc_lbist_en_dc => tc_ac_lbist_en_dc, + + lcb_d_mode_dc => lcb_d_mode_dc, + lcb_clkoff_dc_b => lcb_clkoff_dc_b, + lcb_act_dis_dc => lcb_act_dis_dc, + lcb_mpw1_dc_b => lcb_mpw1_dc_b, + lcb_mpw2_dc_b => lcb_mpw2_dc_b, + lcb_delay_lclkr_dc => lcb_delay_lclkr_dc, + + ac_func_scan_in => siv_0(mmq_inval_offset), + ac_func_scan_out => sov_0(mmq_inval_offset), + + pc_sg_2 => pc_sg_2(0), + pc_func_sl_thold_2 => pc_func_sl_thold_2(0), + pc_func_slp_sl_thold_2 => pc_func_slp_sl_thold_2(0), + pc_func_slp_nsl_thold_2 => pc_func_slp_nsl_thold_2, + pc_fce_2 => pc_fce_2, + mmucr2_act_override => mmucr2_sig(7), + xu_mm_ccr2_notlb => xu_mm_hid_mmu_mode, + xu_mm_ccr2_notlb_b => xu_mm_ccr2_notlb_b, + + mm_iu_ierat_snoop_coming => mm_iu_ierat_snoop_coming, + mm_iu_ierat_snoop_val => mm_iu_ierat_snoop_val, + mm_iu_ierat_snoop_attr => mm_iu_ierat_snoop_attr, + mm_iu_ierat_snoop_vpn => mm_iu_ierat_snoop_vpn, + iu_mm_ierat_snoop_ack => iu_mm_ierat_snoop_ack, + + mm_xu_derat_snoop_coming => mm_xu_derat_snoop_coming, + mm_xu_derat_snoop_val => mm_xu_derat_snoop_val, + mm_xu_derat_snoop_attr => mm_xu_derat_snoop_attr, + mm_xu_derat_snoop_vpn => mm_xu_derat_snoop_vpn, + xu_mm_derat_snoop_ack => xu_mm_derat_snoop_ack, + + tlb_snoop_coming => tlb_snoop_coming, + tlb_snoop_val => tlb_snoop_val, + tlb_snoop_attr => tlb_snoop_attr, + tlb_snoop_vpn => tlb_snoop_vpn, + tlb_snoop_ack => tlb_snoop_ack, + + tlb_ctl_barrier_done => tlb_ctl_barrier_done_sig, + tlb_ctl_ex2_flush_req => tlb_ctl_ex2_flush_req_sig, + tlb_ctl_ex2_illeg_instr => tlb_ctl_ex2_illeg_instr_sig, + tlb_ctl_quiesce => tlb_ctl_quiesce_sig, + tlb_req_quiesce => tlb_req_quiesce_sig, + + mm_iu_barrier_done => mm_iu_barrier_done_sig, + mm_xu_ex3_flush_req => mm_xu_ex3_flush_req_sig, + mm_xu_illeg_instr => mm_xu_illeg_instr_sig, + mm_xu_local_snoop_reject => mm_xu_local_snoop_reject_sig, + + an_ac_back_inv => an_ac_back_inv, + an_ac_back_inv_target => an_ac_back_inv_target(2), + an_ac_back_inv_local => an_ac_back_inv_local, + an_ac_back_inv_lbit => an_ac_back_inv_lbit, + an_ac_back_inv_gs => an_ac_back_inv_gs, + an_ac_back_inv_ind => an_ac_back_inv_ind, + an_ac_back_inv_addr => an_ac_back_inv_addr, + an_ac_back_inv_lpar_id => an_ac_back_inv_lpar_id, + ac_an_back_inv_reject => ac_an_back_inv_reject, + ac_an_power_managed => ac_an_power_managed_imm, + mmucr0_0 => mmucr0_0_sig(2 to 19), + mmucr0_1 => mmucr0_1_sig(2 to 19), + mmucr0_2 => mmucr0_2_sig(2 to 19), + mmucr0_3 => mmucr0_3_sig(2 to 19), + mmucr1 => mmucr1_sig(12 to 19), + mmucr1_csinv => mmucr1_sig(4 to 5), + lpidr => lpidr_sig, + + mas5_0_sgs => mas5_0_sgs, + mas5_0_slpid => mas5_0_slpid, + mas6_0_spid => mas6_0_spid, + mas6_0_isize => mas6_0_isize, + mas6_0_sind => mas6_0_sind, + mas6_0_sas => mas6_0_sas, + mas5_1_sgs => mas5_1_sgs, + mas5_1_slpid => mas5_1_slpid, + mas6_1_spid => mas6_1_spid, + mas6_1_isize => mas6_1_isize, + mas6_1_sind => mas6_1_sind, + mas6_1_sas => mas6_1_sas, + mas5_2_sgs => mas5_2_sgs, + mas5_2_slpid => mas5_2_slpid, + mas6_2_spid => mas6_2_spid, + mas6_2_isize => mas6_2_isize, + mas6_2_sind => mas6_2_sind, + mas6_2_sas => mas6_2_sas, + mas5_3_sgs => mas5_3_sgs, + mas5_3_slpid => mas5_3_slpid, + mas6_3_spid => mas6_3_spid, + mas6_3_isize => mas6_3_isize, + mas6_3_sind => mas6_3_sind, + mas6_3_sas => mas6_3_sas, + mmucsr0_tlb0fi => mmucsr0_tlb0fi, + mmq_inval_tlb0fi_done => mmq_inval_tlb0fi_done, + + + xu_mm_rf1_val => xu_mm_rf1_val, + xu_mm_rf1_is_tlbivax => xu_mm_rf1_is_tlbivax, + xu_mm_rf1_is_tlbilx => xu_mm_rf1_is_tlbilx, + xu_mm_rf1_is_erativax => xu_mm_rf1_is_erativax, + xu_mm_rf1_is_eratilx => xu_mm_rf1_is_eratilx, + xu_mm_ex1_rs_is => xu_mm_ex1_rs_is, + xu_mm_ex1_is_isync => xu_mm_ex1_is_isync, + xu_mm_ex1_is_csync => xu_mm_ex1_is_csync, + xu_mm_ex2_eff_addr => xu_mm_ex2_eff_addr_sig, + xu_mm_rf1_t => xu_mm_rf1_t, + xu_mm_msr_gs => xu_mm_msr_gs, + xu_mm_msr_pr => xu_mm_msr_pr, + xu_mm_spr_epcr_dgtmi => xu_mm_spr_epcr_dgtmi, + xu_mm_epcr_dgtmi => xu_mm_epcr_dgtmi_sig, + xu_rf1_flush => xu_rf1_flush, + xu_ex1_flush => xu_ex1_flush, + xu_ex2_flush => xu_ex2_flush, + xu_ex3_flush => xu_ex3_flush, + xu_ex4_flush => xu_ex4_flush, + xu_ex5_flush => xu_ex5_flush, + xu_mm_lmq_stq_empty => xu_mm_lmq_stq_empty, + iu_mm_lmq_empty => iu_mm_lmq_empty, + mm_xu_hold_req => mm_xu_hold_req_sig, + xu_mm_hold_ack => xu_mm_hold_ack, + mm_xu_hold_done => mm_xu_hold_done_sig, + mm_xu_quiesce => mm_xu_quiesce_sig, + inval_perf_tlbilx => inval_perf_tlbilx, + inval_perf_tlbivax => inval_perf_tlbivax, + inval_perf_tlbivax_snoop => inval_perf_tlbivax_snoop, + inval_perf_tlb_flush => inval_perf_tlb_flush, + + htw_lsu_req_valid => htw_lsu_req_valid, + htw_lsu_thdid => htw_lsu_thdid, + htw_lsu_ttype => htw_lsu_ttype, + htw_lsu_wimge => htw_lsu_wimge, + htw_lsu_u => htw_lsu_u, + htw_lsu_addr => htw_lsu_addr, + htw_lsu_req_taken => htw_lsu_req_taken, + htw_quiesce => htw_quiesce_sig, + + tlbwe_back_inv_valid => tlbwe_back_inv_valid_sig, + tlbwe_back_inv_thdid => tlbwe_back_inv_thdid_sig, + tlbwe_back_inv_addr => tlbwe_back_inv_addr_sig, + tlbwe_back_inv_attr => tlbwe_back_inv_attr_sig, + tlbwe_back_inv_pending => tlbwe_back_inv_pending_sig, + tlb_tag5_write => tlb_tag5_write, + + mm_xu_lsu_req => mm_xu_lsu_req_sig, + mm_xu_lsu_ttype => mm_xu_lsu_ttype_sig, + mm_xu_lsu_wimge => mm_xu_lsu_wimge_sig, + mm_xu_lsu_u => mm_xu_lsu_u_sig, + mm_xu_lsu_addr => mm_xu_lsu_addr_sig, + mm_xu_lsu_lpid => mm_xu_lsu_lpid_sig, + mm_xu_lsu_gs => mm_xu_lsu_gs_sig, + mm_xu_lsu_ind => mm_xu_lsu_ind_sig, + mm_xu_lsu_lbit => mm_xu_lsu_lbit_sig, + xu_mm_lsu_token => xu_mm_lsu_token, + + inval_dbg_seq_q => inval_dbg_seq_q, + inval_dbg_seq_idle => inval_dbg_seq_idle, + inval_dbg_seq_snoop_inprogress => inval_dbg_seq_snoop_inprogress, + inval_dbg_seq_snoop_done => inval_dbg_seq_snoop_done, + inval_dbg_seq_local_done => inval_dbg_seq_local_done, + inval_dbg_seq_tlb0fi_done => inval_dbg_seq_tlb0fi_done, + inval_dbg_seq_tlbwe_snoop_done => inval_dbg_seq_tlbwe_snoop_done, + inval_dbg_ex6_valid => inval_dbg_ex6_valid, + inval_dbg_ex6_thdid => inval_dbg_ex6_thdid, + inval_dbg_ex6_ttype => inval_dbg_ex6_ttype, + inval_dbg_snoop_forme => inval_dbg_snoop_forme, + inval_dbg_snoop_local_reject => inval_dbg_snoop_local_reject, + inval_dbg_an_ac_back_inv_q => inval_dbg_an_ac_back_inv_q, + inval_dbg_an_ac_back_inv_lpar_id_q => inval_dbg_an_ac_back_inv_lpar_id_q, + inval_dbg_an_ac_back_inv_addr_q => inval_dbg_an_ac_back_inv_addr_q, + inval_dbg_snoop_valid_q => inval_dbg_snoop_valid_q, + inval_dbg_snoop_ack_q => inval_dbg_snoop_ack_q, + inval_dbg_snoop_attr_q => inval_dbg_snoop_attr_q, + inval_dbg_snoop_attr_tlb_spec_q => inval_dbg_snoop_attr_tlb_spec_q, + inval_dbg_snoop_vpn_q => inval_dbg_snoop_vpn_q, + inval_dbg_lsu_tokens_q => inval_dbg_lsu_tokens_q +); +mmq_spr: entity work.mmq_spr(mmq_spr) + generic map ( spr_data_width => spr_data_width, + expand_tlb_type => expand_tlb_type, + lpid_width => lpid_width, + real_addr_width => real_addr_width, + mmq_spr_cswitch_0to3 => mmq_spr_cswitch_0to3, + expand_type => expand_type ) + port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + tc_ccflush_dc => tc_ac_ccflush_dc, + tc_scan_dis_dc_b => tc_ac_scan_dis_dc_b, + tc_scan_diag_dc => tc_ac_scan_diag_dc, + tc_lbist_en_dc => tc_ac_lbist_en_dc, + + lcb_d_mode_dc => lcb_d_mode_dc, + lcb_clkoff_dc_b => lcb_clkoff_dc_b, + lcb_act_dis_dc => lcb_act_dis_dc, + lcb_mpw1_dc_b => lcb_mpw1_dc_b, + lcb_mpw2_dc_b => lcb_mpw2_dc_b, + lcb_delay_lclkr_dc => lcb_delay_lclkr_dc, + + ac_func_scan_in(0) => siv_0(mmq_spr_offset_0), + ac_func_scan_in(1) => func_scan_in_int(1), + ac_func_scan_out(0) => sov_0(mmq_spr_offset_0), + ac_func_scan_out(1) => func_scan_out_int(1), + ac_bcfg_scan_in => bsiv(mmq_spr_bcfg_offset), + ac_bcfg_scan_out => bsov(mmq_spr_bcfg_offset), + + +pc_sg_2 => pc_sg_2(0), + pc_func_sl_thold_2 => pc_func_sl_thold_2(0), + pc_func_slp_sl_thold_2 => pc_func_slp_sl_thold_2(0), + pc_func_slp_nsl_thold_2 => pc_func_slp_nsl_thold_2, + pc_cfg_sl_thold_2 => pc_cfg_sl_thold_2, + pc_cfg_slp_sl_thold_2 => pc_cfg_slp_sl_thold_2, + pc_fce_2 => pc_fce_2, + xu_mm_ccr2_notlb_b => xu_mm_ccr2_notlb_b(1), + mmucr2_act_override => mmucr2_sig(5 to 6), + + tlb_delayed_act => tlb_delayed_act(29 to 32), + + mm_iu_ierat_pid0 => mm_iu_ierat_pid0, + mm_iu_ierat_pid1 => mm_iu_ierat_pid1, + mm_iu_ierat_pid2 => mm_iu_ierat_pid2, + mm_iu_ierat_pid3 => mm_iu_ierat_pid3, + mm_iu_ierat_mmucr0_0 => mm_iu_ierat_mmucr0_0, + mm_iu_ierat_mmucr0_1 => mm_iu_ierat_mmucr0_1, + mm_iu_ierat_mmucr0_2 => mm_iu_ierat_mmucr0_2, + mm_iu_ierat_mmucr0_3 => mm_iu_ierat_mmucr0_3, + iu_mm_ierat_mmucr0 => iu_mm_ierat_mmucr0, + iu_mm_ierat_mmucr0_we => iu_mm_ierat_mmucr0_we, + mm_iu_ierat_mmucr1 => mm_iu_ierat_mmucr1, + iu_mm_ierat_mmucr1 => iu_mm_ierat_mmucr1, + iu_mm_ierat_mmucr1_we => iu_mm_ierat_mmucr1_we, + + mm_xu_derat_pid0 => mm_xu_derat_pid0, + mm_xu_derat_pid1 => mm_xu_derat_pid1, + mm_xu_derat_pid2 => mm_xu_derat_pid2, + mm_xu_derat_pid3 => mm_xu_derat_pid3, + mm_xu_derat_mmucr0_0 => mm_xu_derat_mmucr0_0, + mm_xu_derat_mmucr0_1 => mm_xu_derat_mmucr0_1, + mm_xu_derat_mmucr0_2 => mm_xu_derat_mmucr0_2, + mm_xu_derat_mmucr0_3 => mm_xu_derat_mmucr0_3, + xu_mm_derat_mmucr0 => xu_mm_derat_mmucr0, + xu_mm_derat_mmucr0_we => xu_mm_derat_mmucr0_we, + mm_xu_derat_mmucr1 => mm_xu_derat_mmucr1, + xu_mm_derat_mmucr1 => xu_mm_derat_mmucr1, + xu_mm_derat_mmucr1_we => xu_mm_derat_mmucr1_we, + + pid0 => pid0_sig, + pid1 => pid1_sig, + pid2 => pid2_sig, + pid3 => pid3_sig, + mmucr0_0 => mmucr0_0_sig, + mmucr0_1 => mmucr0_1_sig, + mmucr0_2 => mmucr0_2_sig, + mmucr0_3 => mmucr0_3_sig, + mmucr1 => mmucr1_sig, + mmucr2 => mmucr2_sig, + mmucr3_0 => mmucr3_0_sig, + mmucr3_1 => mmucr3_1_sig, + mmucr3_2 => mmucr3_2_sig, + mmucr3_3 => mmucr3_3_sig, + mmucfg_lrat => mmucfg_lrat, + mmucfg_twc => mmucfg_twc, + tlb0cfg_pt => tlb0cfg_pt, + tlb0cfg_ind => tlb0cfg_ind, + tlb0cfg_gtwe => tlb0cfg_gtwe, + mas0_0_atsel => mas0_0_atsel, + mas0_0_esel => mas0_0_esel, + mas0_0_hes => mas0_0_hes, + mas0_0_wq => mas0_0_wq, + mas1_0_v => mas1_0_v, + mas1_0_iprot => mas1_0_iprot, + mas1_0_tid => mas1_0_tid, + mas1_0_ind => mas1_0_ind, + mas1_0_ts => mas1_0_ts, + mas1_0_tsize => mas1_0_tsize, + mas2_0_epn => mas2_0_epn, + mas2_0_wimge => mas2_0_wimge, + mas3_0_rpnl => mas3_0_rpnl, + mas3_0_ubits => mas3_0_ubits, + mas3_0_usxwr => mas3_0_usxwr, + mas5_0_sgs => mas5_0_sgs, + mas5_0_slpid => mas5_0_slpid, + mas6_0_spid => mas6_0_spid, + mas6_0_isize => mas6_0_isize, + mas6_0_sind => mas6_0_sind, + mas6_0_sas => mas6_0_sas, + mas7_0_rpnu => mas7_0_rpnu, + mas8_0_tgs => mas8_0_tgs, + mas8_0_vf => mas8_0_vf, + mas8_0_tlpid => mas8_0_tlpid, + mas0_1_atsel => mas0_1_atsel, + mas0_1_esel => mas0_1_esel, + mas0_1_hes => mas0_1_hes, + mas0_1_wq => mas0_1_wq, + mas1_1_v => mas1_1_v, + mas1_1_iprot => mas1_1_iprot, + mas1_1_tid => mas1_1_tid, + mas1_1_ind => mas1_1_ind, + mas1_1_ts => mas1_1_ts, + mas1_1_tsize => mas1_1_tsize, + mas2_1_epn => mas2_1_epn, + mas2_1_wimge => mas2_1_wimge, + mas3_1_rpnl => mas3_1_rpnl, + mas3_1_ubits => mas3_1_ubits, + mas3_1_usxwr => mas3_1_usxwr, + mas5_1_sgs => mas5_1_sgs, + mas5_1_slpid => mas5_1_slpid, + mas6_1_spid => mas6_1_spid, + mas6_1_isize => mas6_1_isize, + mas6_1_sind => mas6_1_sind, + mas6_1_sas => mas6_1_sas, + mas7_1_rpnu => mas7_1_rpnu, + mas8_1_tgs => mas8_1_tgs, + mas8_1_vf => mas8_1_vf, + mas8_1_tlpid => mas8_1_tlpid, + mas0_2_atsel => mas0_2_atsel, + mas0_2_esel => mas0_2_esel, + mas0_2_hes => mas0_2_hes, + mas0_2_wq => mas0_2_wq, + mas1_2_v => mas1_2_v, + mas1_2_iprot => mas1_2_iprot, + mas1_2_tid => mas1_2_tid, + mas1_2_ind => mas1_2_ind, + mas1_2_ts => mas1_2_ts, + mas1_2_tsize => mas1_2_tsize, + mas2_2_epn => mas2_2_epn, + mas2_2_wimge => mas2_2_wimge, + mas3_2_rpnl => mas3_2_rpnl, + mas3_2_ubits => mas3_2_ubits, + mas3_2_usxwr => mas3_2_usxwr, + mas5_2_sgs => mas5_2_sgs, + mas5_2_slpid => mas5_2_slpid, + mas6_2_spid => mas6_2_spid, + mas6_2_isize => mas6_2_isize, + mas6_2_sind => mas6_2_sind, + mas6_2_sas => mas6_2_sas, + mas7_2_rpnu => mas7_2_rpnu, + mas8_2_tgs => mas8_2_tgs, + mas8_2_vf => mas8_2_vf, + mas8_2_tlpid => mas8_2_tlpid, + mas0_3_atsel => mas0_3_atsel, + mas0_3_esel => mas0_3_esel, + mas0_3_hes => mas0_3_hes, + mas0_3_wq => mas0_3_wq, + mas1_3_v => mas1_3_v, + mas1_3_iprot => mas1_3_iprot, + mas1_3_tid => mas1_3_tid, + mas1_3_ind => mas1_3_ind, + mas1_3_ts => mas1_3_ts, + mas1_3_tsize => mas1_3_tsize, + mas2_3_epn => mas2_3_epn, + mas2_3_wimge => mas2_3_wimge, + mas3_3_rpnl => mas3_3_rpnl, + mas3_3_ubits => mas3_3_ubits, + mas3_3_usxwr => mas3_3_usxwr, + mas5_3_sgs => mas5_3_sgs, + mas5_3_slpid => mas5_3_slpid, + mas6_3_spid => mas6_3_spid, + mas6_3_isize => mas6_3_isize, + mas6_3_sind => mas6_3_sind, + mas6_3_sas => mas6_3_sas, + mas7_3_rpnu => mas7_3_rpnu, + mas8_3_tgs => mas8_3_tgs, + mas8_3_vf => mas8_3_vf, + mas8_3_tlpid => mas8_3_tlpid, + tlb_mas0_esel => tlb_mas0_esel, + tlb_mas1_v => tlb_mas1_v, + tlb_mas1_iprot => tlb_mas1_iprot, + tlb_mas1_tid => tlb_mas1_tid, + tlb_mas1_tid_error => tlb_mas1_tid_error, + tlb_mas1_ind => tlb_mas1_ind, + tlb_mas1_ts => tlb_mas1_ts, + tlb_mas1_ts_error => tlb_mas1_ts_error, + tlb_mas1_tsize => tlb_mas1_tsize, + tlb_mas2_epn => tlb_mas2_epn, + tlb_mas2_epn_error => tlb_mas2_epn_error, + tlb_mas2_wimge => tlb_mas2_wimge, + tlb_mas3_rpnl => tlb_mas3_rpnl, + tlb_mas3_ubits => tlb_mas3_ubits, + tlb_mas3_usxwr => tlb_mas3_usxwr, + tlb_mas6_spid => tlb_mas6_spid, + tlb_mas6_isize => tlb_mas6_isize, + tlb_mas6_sind => tlb_mas6_sind, + tlb_mas6_sas => tlb_mas6_sas, + tlb_mas7_rpnu => tlb_mas7_rpnu, + tlb_mas8_tgs => tlb_mas8_tgs, + tlb_mas8_vf => tlb_mas8_vf, + tlb_mas8_tlpid => tlb_mas8_tlpid, + + tlb_mmucr1_een => tlb_mmucr1_een, + tlb_mmucr1_we => tlb_mmucr1_we, + tlb_mmucr3_thdid => tlb_mmucr3_thdid, + tlb_mmucr3_resvattr => tlb_mmucr3_resvattr, + tlb_mmucr3_wlc => tlb_mmucr3_wlc, + tlb_mmucr3_class => tlb_mmucr3_class, + tlb_mmucr3_extclass => tlb_mmucr3_extclass, + tlb_mmucr3_rc => tlb_mmucr3_rc, + tlb_mmucr3_x => tlb_mmucr3_x, + tlb_mas_tlbre => tlb_mas_tlbre, + tlb_mas_tlbsx_hit => tlb_mas_tlbsx_hit, + tlb_mas_tlbsx_miss => tlb_mas_tlbsx_miss, + tlb_mas_dtlb_error => tlb_mas_dtlb_error, + tlb_mas_itlb_error => tlb_mas_itlb_error, + tlb_mas_thdid => tlb_mas_thdid, + + mmucsr0_tlb0fi => mmucsr0_tlb0fi, + mmq_inval_tlb0fi_done => mmq_inval_tlb0fi_done, + + lrat_mmucr3_x => lrat_mmucr3_x, + lrat_mas0_esel => lrat_mas0_esel, + lrat_mas1_v => lrat_mas1_v, + lrat_mas1_tsize => lrat_mas1_tsize, + lrat_mas2_epn => lrat_mas2_epn, + lrat_mas3_rpnl => lrat_mas3_rpnl, + lrat_mas7_rpnu => lrat_mas7_rpnu, + lrat_mas8_tlpid => lrat_mas8_tlpid, + lrat_mas_tlbre => lrat_mas_tlbre, + lrat_mas_tlbsx_hit => lrat_mas_tlbsx_hit, + lrat_mas_tlbsx_miss => lrat_mas_tlbsx_miss, + lrat_mas_thdid => lrat_mas_thdid, + lrat_tag4_hit_entry => lrat_tag4_hit_entry, + + tlb_lper_lpn => tlb_lper_lpn, + tlb_lper_lps => tlb_lper_lps, + tlb_lper_we => tlb_lper_we, + + lpidr => lpidr_sig, + ac_an_lpar_id => ac_an_lpar_id_sig, + + spr_dbg_match_64b => spr_dbg_match_64b, + spr_dbg_match_any_mmu => spr_dbg_match_any_mmu, + spr_dbg_match_any_mas => spr_dbg_match_any_mas, + spr_dbg_match_pid => spr_dbg_match_pid, + spr_dbg_match_lpidr => spr_dbg_match_lpidr, + spr_dbg_match_mmucr0 => spr_dbg_match_mmucr0, + spr_dbg_match_mmucr1 => spr_dbg_match_mmucr1, + spr_dbg_match_mmucr2 => spr_dbg_match_mmucr2, + spr_dbg_match_mmucr3 => spr_dbg_match_mmucr3, + + spr_dbg_match_mmucsr0 => spr_dbg_match_mmucsr0, + spr_dbg_match_mmucfg => spr_dbg_match_mmucfg, + spr_dbg_match_tlb0cfg => spr_dbg_match_tlb0cfg, + spr_dbg_match_tlb0ps => spr_dbg_match_tlb0ps, + spr_dbg_match_lratcfg => spr_dbg_match_lratcfg, + spr_dbg_match_lratps => spr_dbg_match_lratps, + spr_dbg_match_eptcfg => spr_dbg_match_eptcfg, + spr_dbg_match_lper => spr_dbg_match_lper, + spr_dbg_match_lperu => spr_dbg_match_lperu, + + spr_dbg_match_mas0 => spr_dbg_match_mas0, + spr_dbg_match_mas1 => spr_dbg_match_mas1, + spr_dbg_match_mas2 => spr_dbg_match_mas2, + spr_dbg_match_mas2u => spr_dbg_match_mas2u, + spr_dbg_match_mas3 => spr_dbg_match_mas3, + spr_dbg_match_mas4 => spr_dbg_match_mas4, + spr_dbg_match_mas5 => spr_dbg_match_mas5, + spr_dbg_match_mas6 => spr_dbg_match_mas6, + spr_dbg_match_mas7 => spr_dbg_match_mas7, + spr_dbg_match_mas8 => spr_dbg_match_mas8, + spr_dbg_match_mas01_64b => spr_dbg_match_mas01_64b, + spr_dbg_match_mas56_64b => spr_dbg_match_mas56_64b, + spr_dbg_match_mas73_64b => spr_dbg_match_mas73_64b, + spr_dbg_match_mas81_64b => spr_dbg_match_mas81_64b, + + spr_dbg_slowspr_val_int => spr_dbg_slowspr_val_int, + spr_dbg_slowspr_rw_int => spr_dbg_slowspr_rw_int, + spr_dbg_slowspr_etid_int => spr_dbg_slowspr_etid_int, + spr_dbg_slowspr_addr_int => spr_dbg_slowspr_addr_int, + spr_dbg_slowspr_val_out => spr_dbg_slowspr_val_out, + spr_dbg_slowspr_done_out => spr_dbg_slowspr_done_out, + spr_dbg_slowspr_data_out => spr_dbg_slowspr_data_out, + + xu_mm_slowspr_val => slowspr_val_in, + xu_mm_slowspr_rw => slowspr_rw_in, + xu_mm_slowspr_etid => slowspr_etid_in, + xu_mm_slowspr_addr => slowspr_addr_in, + xu_mm_slowspr_data => slowspr_data_in, + xu_mm_slowspr_done => slowspr_done_in, + + mm_iu_slowspr_val => slowspr_val_out, + mm_iu_slowspr_rw => slowspr_rw_out, + mm_iu_slowspr_etid => slowspr_etid_out, + mm_iu_slowspr_addr => slowspr_addr_out, + mm_iu_slowspr_data => slowspr_data_out, + mm_iu_slowspr_done => slowspr_done_out + +); +mmq_dbg: entity work.mmq_dbg(mmq_dbg) + generic map ( tlb_tag_width => tlb_tag_width, + expand_type => expand_type ) + port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_func_slp_sl_thold_2 => pc_func_slp_sl_thold_2(0), + pc_func_slp_nsl_thold_2 => pc_func_slp_nsl_thold_2, + pc_sg_2 => pc_sg_2(0), + pc_fce_2 => pc_fce_2, + tc_ac_ccflush_dc => tc_ac_ccflush_dc, + lcb_clkoff_dc_b => lcb_clkoff_dc_b, + lcb_act_dis_dc => lcb_act_dis_dc, + lcb_d_mode_dc => lcb_d_mode_dc, + lcb_delay_lclkr_dc => lcb_delay_lclkr_dc(0), + lcb_mpw1_dc_b => lcb_mpw1_dc_b(0), + lcb_mpw2_dc_b => lcb_mpw2_dc_b, + scan_in => siv_1(mmq_dbg_offset), + scan_out => sov_1(mmq_dbg_offset), + + mmucr2 => mmucr2_sig(8 to 11), + pc_mm_trace_bus_enable => pc_mm_trace_bus_enable, + pc_mm_debug_mux1_ctrls => pc_mm_debug_mux1_ctrls, + + debug_bus_in => debug_bus_in, + trace_triggers_in => trace_triggers_in, + + debug_bus_out => debug_bus_out, + debug_bus_out_int => debug_bus_out_int, + trace_triggers_out => trace_triggers_out, + + spr_dbg_match_64b => spr_dbg_match_64b, + spr_dbg_match_any_mmu => spr_dbg_match_any_mmu, + spr_dbg_match_any_mas => spr_dbg_match_any_mas, + spr_dbg_match_pid => spr_dbg_match_pid, + spr_dbg_match_lpidr => spr_dbg_match_lpidr, + spr_dbg_match_mmucr0 => spr_dbg_match_mmucr0, + spr_dbg_match_mmucr1 => spr_dbg_match_mmucr1, + spr_dbg_match_mmucr2 => spr_dbg_match_mmucr2, + spr_dbg_match_mmucr3 => spr_dbg_match_mmucr3, + + spr_dbg_match_mmucsr0 => spr_dbg_match_mmucsr0, + spr_dbg_match_mmucfg => spr_dbg_match_mmucfg, + spr_dbg_match_tlb0cfg => spr_dbg_match_tlb0cfg, + spr_dbg_match_tlb0ps => spr_dbg_match_tlb0ps, + spr_dbg_match_lratcfg => spr_dbg_match_lratcfg, + spr_dbg_match_lratps => spr_dbg_match_lratps, + spr_dbg_match_eptcfg => spr_dbg_match_eptcfg, + spr_dbg_match_lper => spr_dbg_match_lper, + spr_dbg_match_lperu => spr_dbg_match_lperu, + + spr_dbg_match_mas0 => spr_dbg_match_mas0, + spr_dbg_match_mas1 => spr_dbg_match_mas1, + spr_dbg_match_mas2 => spr_dbg_match_mas2, + spr_dbg_match_mas2u => spr_dbg_match_mas2u, + spr_dbg_match_mas3 => spr_dbg_match_mas3, + spr_dbg_match_mas4 => spr_dbg_match_mas4, + spr_dbg_match_mas5 => spr_dbg_match_mas5, + spr_dbg_match_mas6 => spr_dbg_match_mas6, + spr_dbg_match_mas7 => spr_dbg_match_mas7, + spr_dbg_match_mas8 => spr_dbg_match_mas8, + spr_dbg_match_mas01_64b => spr_dbg_match_mas01_64b, + spr_dbg_match_mas56_64b => spr_dbg_match_mas56_64b, + spr_dbg_match_mas73_64b => spr_dbg_match_mas73_64b, + spr_dbg_match_mas81_64b => spr_dbg_match_mas81_64b, + + spr_dbg_slowspr_val_int => spr_dbg_slowspr_val_int, + spr_dbg_slowspr_rw_int => spr_dbg_slowspr_rw_int, + spr_dbg_slowspr_etid_int => spr_dbg_slowspr_etid_int, + spr_dbg_slowspr_addr_int => spr_dbg_slowspr_addr_int, + spr_dbg_slowspr_val_out => spr_dbg_slowspr_val_out, + spr_dbg_slowspr_done_out => spr_dbg_slowspr_done_out, + spr_dbg_slowspr_data_out => spr_dbg_slowspr_data_out, + inval_dbg_seq_q => inval_dbg_seq_q, + inval_dbg_seq_idle => inval_dbg_seq_idle, + inval_dbg_seq_snoop_inprogress => inval_dbg_seq_snoop_inprogress, + inval_dbg_seq_snoop_done => inval_dbg_seq_snoop_done, + inval_dbg_seq_local_done => inval_dbg_seq_local_done, + inval_dbg_seq_tlb0fi_done => inval_dbg_seq_tlb0fi_done, + inval_dbg_seq_tlbwe_snoop_done => inval_dbg_seq_tlbwe_snoop_done, + inval_dbg_ex6_valid => inval_dbg_ex6_valid, + inval_dbg_ex6_thdid => inval_dbg_ex6_thdid, + inval_dbg_ex6_ttype => inval_dbg_ex6_ttype, + inval_dbg_snoop_forme => inval_dbg_snoop_forme, + inval_dbg_snoop_local_reject => inval_dbg_snoop_local_reject, + inval_dbg_an_ac_back_inv_q => inval_dbg_an_ac_back_inv_q, + inval_dbg_an_ac_back_inv_lpar_id_q => inval_dbg_an_ac_back_inv_lpar_id_q, + inval_dbg_an_ac_back_inv_addr_q => inval_dbg_an_ac_back_inv_addr_q, + inval_dbg_snoop_valid_q => inval_dbg_snoop_valid_q, + inval_dbg_snoop_ack_q => inval_dbg_snoop_ack_q, + inval_dbg_snoop_attr_q => inval_dbg_snoop_attr_q, + inval_dbg_snoop_attr_tlb_spec_q => inval_dbg_snoop_attr_tlb_spec_q, + inval_dbg_snoop_vpn_q => inval_dbg_snoop_vpn_q, + inval_dbg_lsu_tokens_q => inval_dbg_lsu_tokens_q, + tlb_req_dbg_ierat_iu5_valid_q => tlb_req_dbg_ierat_iu5_valid_q, + tlb_req_dbg_ierat_iu5_thdid => tlb_req_dbg_ierat_iu5_thdid, + tlb_req_dbg_ierat_iu5_state_q => tlb_req_dbg_ierat_iu5_state_q, + tlb_req_dbg_ierat_inptr_q => tlb_req_dbg_ierat_inptr_q, + tlb_req_dbg_ierat_outptr_q => tlb_req_dbg_ierat_outptr_q, + tlb_req_dbg_ierat_req_valid_q => tlb_req_dbg_ierat_req_valid_q, + tlb_req_dbg_ierat_req_nonspec_q => tlb_req_dbg_ierat_req_nonspec_q, + tlb_req_dbg_ierat_req_thdid => tlb_req_dbg_ierat_req_thdid, + tlb_req_dbg_ierat_req_dup_q => tlb_req_dbg_ierat_req_dup_q, + tlb_req_dbg_derat_ex6_valid_q => tlb_req_dbg_derat_ex6_valid_q, + tlb_req_dbg_derat_ex6_thdid => tlb_req_dbg_derat_ex6_thdid, + tlb_req_dbg_derat_ex6_state_q => tlb_req_dbg_derat_ex6_state_q, + tlb_req_dbg_derat_inptr_q => tlb_req_dbg_derat_inptr_q, + tlb_req_dbg_derat_outptr_q => tlb_req_dbg_derat_outptr_q, + tlb_req_dbg_derat_req_valid_q => tlb_req_dbg_derat_req_valid_q, + tlb_req_dbg_derat_req_thdid => tlb_req_dbg_derat_req_thdid, + tlb_req_dbg_derat_req_ttype_q => tlb_req_dbg_derat_req_ttype_q, + tlb_req_dbg_derat_req_dup_q => tlb_req_dbg_derat_req_dup_q, + + tlb_ctl_dbg_seq_q => tlb_ctl_dbg_seq_q, + tlb_ctl_dbg_seq_idle => tlb_ctl_dbg_seq_idle, + tlb_ctl_dbg_seq_any_done_sig => tlb_ctl_dbg_seq_any_done_sig, + tlb_ctl_dbg_seq_abort => tlb_ctl_dbg_seq_abort, + tlb_ctl_dbg_any_tlb_req_sig => tlb_ctl_dbg_any_tlb_req_sig, + tlb_ctl_dbg_any_req_taken_sig => tlb_ctl_dbg_any_req_taken_sig, + tlb_ctl_dbg_tag0_valid => tlb_ctl_dbg_tag0_valid, + tlb_ctl_dbg_tag0_thdid => tlb_ctl_dbg_tag0_thdid, + tlb_ctl_dbg_tag0_type => tlb_ctl_dbg_tag0_type, + tlb_ctl_dbg_tag0_wq => tlb_ctl_dbg_tag0_wq, + tlb_ctl_dbg_tag0_gs => tlb_ctl_dbg_tag0_gs, + tlb_ctl_dbg_tag0_pr => tlb_ctl_dbg_tag0_pr, + tlb_ctl_dbg_tag0_atsel => tlb_ctl_dbg_tag0_atsel, + tlb_ctl_dbg_tag5_tlb_write_q => tlb_ctl_dbg_tag5_tlb_write_q, + tlb_ctl_dbg_resv_valid => tlb_ctl_dbg_resv_valid, + tlb_ctl_dbg_set_resv => tlb_ctl_dbg_set_resv, + tlb_ctl_dbg_resv_match_vec_q => tlb_ctl_dbg_resv_match_vec_q, + tlb_ctl_dbg_any_tag_flush_sig => tlb_ctl_dbg_any_tag_flush_sig, + tlb_ctl_dbg_resv0_tag0_lpid_match => tlb_ctl_dbg_resv0_tag0_lpid_match, + tlb_ctl_dbg_resv0_tag0_pid_match => tlb_ctl_dbg_resv0_tag0_pid_match, + tlb_ctl_dbg_resv0_tag0_as_snoop_match => tlb_ctl_dbg_resv0_tag0_as_snoop_match, + tlb_ctl_dbg_resv0_tag0_gs_snoop_match => tlb_ctl_dbg_resv0_tag0_gs_snoop_match, + tlb_ctl_dbg_resv0_tag0_as_tlbwe_match => tlb_ctl_dbg_resv0_tag0_as_tlbwe_match, + tlb_ctl_dbg_resv0_tag0_gs_tlbwe_match => tlb_ctl_dbg_resv0_tag0_gs_tlbwe_match, + tlb_ctl_dbg_resv0_tag0_ind_match => tlb_ctl_dbg_resv0_tag0_ind_match, + tlb_ctl_dbg_resv0_tag0_epn_loc_match => tlb_ctl_dbg_resv0_tag0_epn_loc_match, + tlb_ctl_dbg_resv0_tag0_epn_glob_match => tlb_ctl_dbg_resv0_tag0_epn_glob_match, + tlb_ctl_dbg_resv0_tag0_class_match => tlb_ctl_dbg_resv0_tag0_class_match, + tlb_ctl_dbg_resv1_tag0_lpid_match => tlb_ctl_dbg_resv1_tag0_lpid_match, + tlb_ctl_dbg_resv1_tag0_pid_match => tlb_ctl_dbg_resv1_tag0_pid_match, + tlb_ctl_dbg_resv1_tag0_as_snoop_match => tlb_ctl_dbg_resv1_tag0_as_snoop_match, + tlb_ctl_dbg_resv1_tag0_gs_snoop_match => tlb_ctl_dbg_resv1_tag0_gs_snoop_match, + tlb_ctl_dbg_resv1_tag0_as_tlbwe_match => tlb_ctl_dbg_resv1_tag0_as_tlbwe_match, + tlb_ctl_dbg_resv1_tag0_gs_tlbwe_match => tlb_ctl_dbg_resv1_tag0_gs_tlbwe_match, + tlb_ctl_dbg_resv1_tag0_ind_match => tlb_ctl_dbg_resv1_tag0_ind_match, + tlb_ctl_dbg_resv1_tag0_epn_loc_match => tlb_ctl_dbg_resv1_tag0_epn_loc_match, + tlb_ctl_dbg_resv1_tag0_epn_glob_match => tlb_ctl_dbg_resv1_tag0_epn_glob_match, + tlb_ctl_dbg_resv1_tag0_class_match => tlb_ctl_dbg_resv1_tag0_class_match , + tlb_ctl_dbg_resv2_tag0_lpid_match => tlb_ctl_dbg_resv2_tag0_lpid_match, + tlb_ctl_dbg_resv2_tag0_pid_match => tlb_ctl_dbg_resv2_tag0_pid_match, + tlb_ctl_dbg_resv2_tag0_as_snoop_match => tlb_ctl_dbg_resv2_tag0_as_snoop_match, + tlb_ctl_dbg_resv2_tag0_gs_snoop_match => tlb_ctl_dbg_resv2_tag0_gs_snoop_match, + tlb_ctl_dbg_resv2_tag0_as_tlbwe_match => tlb_ctl_dbg_resv2_tag0_as_tlbwe_match, + tlb_ctl_dbg_resv2_tag0_gs_tlbwe_match => tlb_ctl_dbg_resv2_tag0_gs_tlbwe_match, + tlb_ctl_dbg_resv2_tag0_ind_match => tlb_ctl_dbg_resv2_tag0_ind_match, + tlb_ctl_dbg_resv2_tag0_epn_loc_match => tlb_ctl_dbg_resv2_tag0_epn_loc_match, + tlb_ctl_dbg_resv2_tag0_epn_glob_match => tlb_ctl_dbg_resv2_tag0_epn_glob_match, + tlb_ctl_dbg_resv2_tag0_class_match => tlb_ctl_dbg_resv2_tag0_class_match, + tlb_ctl_dbg_resv3_tag0_lpid_match => tlb_ctl_dbg_resv3_tag0_lpid_match, + tlb_ctl_dbg_resv3_tag0_pid_match => tlb_ctl_dbg_resv3_tag0_pid_match, + tlb_ctl_dbg_resv3_tag0_as_snoop_match => tlb_ctl_dbg_resv3_tag0_as_snoop_match, + tlb_ctl_dbg_resv3_tag0_gs_snoop_match => tlb_ctl_dbg_resv3_tag0_gs_snoop_match, + tlb_ctl_dbg_resv3_tag0_as_tlbwe_match => tlb_ctl_dbg_resv3_tag0_as_tlbwe_match, + tlb_ctl_dbg_resv3_tag0_gs_tlbwe_match => tlb_ctl_dbg_resv3_tag0_gs_tlbwe_match, + tlb_ctl_dbg_resv3_tag0_ind_match => tlb_ctl_dbg_resv3_tag0_ind_match, + tlb_ctl_dbg_resv3_tag0_epn_loc_match => tlb_ctl_dbg_resv3_tag0_epn_loc_match, + tlb_ctl_dbg_resv3_tag0_epn_glob_match => tlb_ctl_dbg_resv3_tag0_epn_glob_match, + tlb_ctl_dbg_resv3_tag0_class_match => tlb_ctl_dbg_resv3_tag0_class_match, + tlb_ctl_dbg_clr_resv_q => tlb_ctl_dbg_clr_resv_q, + tlb_ctl_dbg_clr_resv_terms => tlb_ctl_dbg_clr_resv_terms, + tlb_cmp_dbg_tag4 => tlb_cmp_dbg_tag4, + tlb_cmp_dbg_tag4_wayhit => tlb_cmp_dbg_tag4_wayhit, + tlb_cmp_dbg_addr4 => tlb_cmp_dbg_addr4, + tlb_cmp_dbg_tag4_way => tlb_cmp_dbg_tag4_way, + tlb_cmp_dbg_tag4_parerr => tlb_cmp_dbg_tag4_parerr, + tlb_cmp_dbg_tag4_lru_dataout_q => tlb_cmp_dbg_tag4_lru_dataout_q, + tlb_cmp_dbg_tag5_tlb_datain_q => tlb_cmp_dbg_tag5_tlb_datain_q, + tlb_cmp_dbg_tag5_lru_datain_q => tlb_cmp_dbg_tag5_lru_datain_q, + tlb_cmp_dbg_tag5_lru_write => tlb_cmp_dbg_tag5_lru_write, + tlb_cmp_dbg_tag5_any_exception => tlb_cmp_dbg_tag5_any_exception, + tlb_cmp_dbg_tag5_except_type_q => tlb_cmp_dbg_tag5_except_type_q, + tlb_cmp_dbg_tag5_except_thdid_q => tlb_cmp_dbg_tag5_except_thdid_q, + tlb_cmp_dbg_tag5_erat_rel_val => tlb_cmp_dbg_tag5_erat_rel_val, + tlb_cmp_dbg_tag5_erat_rel_data => tlb_cmp_dbg_tag5_erat_rel_data, + tlb_cmp_dbg_erat_dup_q => tlb_cmp_dbg_erat_dup_q, + tlb_cmp_dbg_addr_enable => tlb_cmp_dbg_addr_enable, + tlb_cmp_dbg_pgsize_enable => tlb_cmp_dbg_pgsize_enable, + tlb_cmp_dbg_class_enable => tlb_cmp_dbg_class_enable, + tlb_cmp_dbg_extclass_enable => tlb_cmp_dbg_extclass_enable, + tlb_cmp_dbg_state_enable => tlb_cmp_dbg_state_enable, + tlb_cmp_dbg_thdid_enable => tlb_cmp_dbg_thdid_enable, + tlb_cmp_dbg_pid_enable => tlb_cmp_dbg_pid_enable, + tlb_cmp_dbg_lpid_enable => tlb_cmp_dbg_lpid_enable, + tlb_cmp_dbg_ind_enable => tlb_cmp_dbg_ind_enable, + tlb_cmp_dbg_iprot_enable => tlb_cmp_dbg_iprot_enable, + tlb_cmp_dbg_way0_entry_v => tlb_cmp_dbg_way0_entry_v, + tlb_cmp_dbg_way0_addr_match => tlb_cmp_dbg_way0_addr_match, + tlb_cmp_dbg_way0_pgsize_match => tlb_cmp_dbg_way0_pgsize_match, + tlb_cmp_dbg_way0_class_match => tlb_cmp_dbg_way0_class_match, + tlb_cmp_dbg_way0_extclass_match => tlb_cmp_dbg_way0_extclass_match, + tlb_cmp_dbg_way0_state_match => tlb_cmp_dbg_way0_state_match, + tlb_cmp_dbg_way0_thdid_match => tlb_cmp_dbg_way0_thdid_match, + tlb_cmp_dbg_way0_pid_match => tlb_cmp_dbg_way0_pid_match, + tlb_cmp_dbg_way0_lpid_match => tlb_cmp_dbg_way0_lpid_match, + tlb_cmp_dbg_way0_ind_match => tlb_cmp_dbg_way0_ind_match, + tlb_cmp_dbg_way0_iprot_match => tlb_cmp_dbg_way0_iprot_match, + tlb_cmp_dbg_way1_entry_v => tlb_cmp_dbg_way1_entry_v, + tlb_cmp_dbg_way1_addr_match => tlb_cmp_dbg_way1_addr_match, + tlb_cmp_dbg_way1_pgsize_match => tlb_cmp_dbg_way1_pgsize_match, + tlb_cmp_dbg_way1_class_match => tlb_cmp_dbg_way1_class_match, + tlb_cmp_dbg_way1_extclass_match => tlb_cmp_dbg_way1_extclass_match, + tlb_cmp_dbg_way1_state_match => tlb_cmp_dbg_way1_state_match, + tlb_cmp_dbg_way1_thdid_match => tlb_cmp_dbg_way1_thdid_match, + tlb_cmp_dbg_way1_pid_match => tlb_cmp_dbg_way1_pid_match, + tlb_cmp_dbg_way1_lpid_match => tlb_cmp_dbg_way1_lpid_match, + tlb_cmp_dbg_way1_ind_match => tlb_cmp_dbg_way1_ind_match, + tlb_cmp_dbg_way1_iprot_match => tlb_cmp_dbg_way1_iprot_match, + tlb_cmp_dbg_way2_entry_v => tlb_cmp_dbg_way2_entry_v, + tlb_cmp_dbg_way2_addr_match => tlb_cmp_dbg_way2_addr_match, + tlb_cmp_dbg_way2_pgsize_match => tlb_cmp_dbg_way2_pgsize_match, + tlb_cmp_dbg_way2_class_match => tlb_cmp_dbg_way2_class_match, + tlb_cmp_dbg_way2_extclass_match => tlb_cmp_dbg_way2_extclass_match, + tlb_cmp_dbg_way2_state_match => tlb_cmp_dbg_way2_state_match, + tlb_cmp_dbg_way2_thdid_match => tlb_cmp_dbg_way2_thdid_match, + tlb_cmp_dbg_way2_pid_match => tlb_cmp_dbg_way2_pid_match, + tlb_cmp_dbg_way2_lpid_match => tlb_cmp_dbg_way2_lpid_match, + tlb_cmp_dbg_way2_ind_match => tlb_cmp_dbg_way2_ind_match, + tlb_cmp_dbg_way2_iprot_match => tlb_cmp_dbg_way2_iprot_match, + tlb_cmp_dbg_way3_entry_v => tlb_cmp_dbg_way3_entry_v, + tlb_cmp_dbg_way3_addr_match => tlb_cmp_dbg_way3_addr_match, + tlb_cmp_dbg_way3_pgsize_match => tlb_cmp_dbg_way3_pgsize_match, + tlb_cmp_dbg_way3_class_match => tlb_cmp_dbg_way3_class_match, + tlb_cmp_dbg_way3_extclass_match => tlb_cmp_dbg_way3_extclass_match, + tlb_cmp_dbg_way3_state_match => tlb_cmp_dbg_way3_state_match, + tlb_cmp_dbg_way3_thdid_match => tlb_cmp_dbg_way3_thdid_match, + tlb_cmp_dbg_way3_pid_match => tlb_cmp_dbg_way3_pid_match, + tlb_cmp_dbg_way3_lpid_match => tlb_cmp_dbg_way3_lpid_match, + tlb_cmp_dbg_way3_ind_match => tlb_cmp_dbg_way3_ind_match, + tlb_cmp_dbg_way3_iprot_match => tlb_cmp_dbg_way3_iprot_match, + + lrat_dbg_tag1_addr_enable => lrat_dbg_tag1_addr_enable, + lrat_dbg_tag2_matchline_q => lrat_dbg_tag2_matchline_q, + lrat_dbg_entry0_addr_match => lrat_dbg_entry0_addr_match, + lrat_dbg_entry0_lpid_match => lrat_dbg_entry0_lpid_match, + lrat_dbg_entry0_entry_v => lrat_dbg_entry0_entry_v, + lrat_dbg_entry0_entry_x => lrat_dbg_entry0_entry_x, + lrat_dbg_entry0_size => lrat_dbg_entry0_size, + lrat_dbg_entry1_addr_match => lrat_dbg_entry1_addr_match, + lrat_dbg_entry1_lpid_match => lrat_dbg_entry1_lpid_match, + lrat_dbg_entry1_entry_v => lrat_dbg_entry1_entry_v, + lrat_dbg_entry1_entry_x => lrat_dbg_entry1_entry_x, + lrat_dbg_entry1_size => lrat_dbg_entry1_size, + lrat_dbg_entry2_addr_match => lrat_dbg_entry2_addr_match, + lrat_dbg_entry2_lpid_match => lrat_dbg_entry2_lpid_match, + lrat_dbg_entry2_entry_v => lrat_dbg_entry2_entry_v, + lrat_dbg_entry2_entry_x => lrat_dbg_entry2_entry_x, + lrat_dbg_entry2_size => lrat_dbg_entry2_size, + lrat_dbg_entry3_addr_match => lrat_dbg_entry3_addr_match, + lrat_dbg_entry3_lpid_match => lrat_dbg_entry3_lpid_match, + lrat_dbg_entry3_entry_v => lrat_dbg_entry3_entry_v, + lrat_dbg_entry3_entry_x => lrat_dbg_entry3_entry_x, + lrat_dbg_entry3_size => lrat_dbg_entry3_size, + lrat_dbg_entry4_addr_match => lrat_dbg_entry4_addr_match, + lrat_dbg_entry4_lpid_match => lrat_dbg_entry4_lpid_match, + lrat_dbg_entry4_entry_v => lrat_dbg_entry4_entry_v, + lrat_dbg_entry4_entry_x => lrat_dbg_entry4_entry_x, + lrat_dbg_entry4_size => lrat_dbg_entry4_size, + lrat_dbg_entry5_addr_match => lrat_dbg_entry5_addr_match, + lrat_dbg_entry5_lpid_match => lrat_dbg_entry5_lpid_match, + lrat_dbg_entry5_entry_v => lrat_dbg_entry5_entry_v, + lrat_dbg_entry5_entry_x => lrat_dbg_entry5_entry_x, + lrat_dbg_entry5_size => lrat_dbg_entry5_size, + lrat_dbg_entry6_addr_match => lrat_dbg_entry6_addr_match, + lrat_dbg_entry6_lpid_match => lrat_dbg_entry6_lpid_match, + lrat_dbg_entry6_entry_v => lrat_dbg_entry6_entry_v, + lrat_dbg_entry6_entry_x => lrat_dbg_entry6_entry_x, + lrat_dbg_entry6_size => lrat_dbg_entry6_size, + lrat_dbg_entry7_addr_match => lrat_dbg_entry7_addr_match, + lrat_dbg_entry7_lpid_match => lrat_dbg_entry7_lpid_match, + lrat_dbg_entry7_entry_v => lrat_dbg_entry7_entry_v, + lrat_dbg_entry7_entry_x => lrat_dbg_entry7_entry_x, + lrat_dbg_entry7_size => lrat_dbg_entry7_size, + htw_dbg_seq_idle => htw_dbg_seq_idle, + htw_dbg_pte0_seq_idle => htw_dbg_pte0_seq_idle, + htw_dbg_pte1_seq_idle => htw_dbg_pte1_seq_idle, + htw_dbg_seq_q => htw_dbg_seq_q, + htw_dbg_inptr_q => htw_dbg_inptr_q, + htw_dbg_pte0_seq_q => htw_dbg_pte0_seq_q, + htw_dbg_pte1_seq_q => htw_dbg_pte1_seq_q, + htw_dbg_ptereload_ptr_q => htw_dbg_ptereload_ptr_q, + htw_dbg_lsuptr_q => htw_dbg_lsuptr_q, + htw_dbg_req_valid_q => htw_dbg_req_valid_q, + htw_dbg_resv_valid_vec => htw_dbg_resv_valid_vec, + htw_dbg_tag4_clr_resv_q => htw_dbg_tag4_clr_resv_q, + htw_dbg_tag4_clr_resv_terms => htw_dbg_tag4_clr_resv_terms, + htw_dbg_pte0_score_ptr_q => htw_dbg_pte0_score_ptr_q, + htw_dbg_pte0_score_cl_offset_q => htw_dbg_pte0_score_cl_offset_q, + htw_dbg_pte0_score_error_q => htw_dbg_pte0_score_error_q, + htw_dbg_pte0_score_qwbeat_q => htw_dbg_pte0_score_qwbeat_q, + htw_dbg_pte0_score_pending_q => htw_dbg_pte0_score_pending_q, + htw_dbg_pte0_score_ibit_q => htw_dbg_pte0_score_ibit_q, + htw_dbg_pte0_score_dataval_q => htw_dbg_pte0_score_dataval_q, + htw_dbg_pte0_reld_for_me_tm1 => htw_dbg_pte0_reld_for_me_tm1, + htw_dbg_pte1_score_ptr_q => htw_dbg_pte1_score_ptr_q, + htw_dbg_pte1_score_cl_offset_q => htw_dbg_pte1_score_cl_offset_q, + htw_dbg_pte1_score_error_q => htw_dbg_pte1_score_error_q, + htw_dbg_pte1_score_qwbeat_q => htw_dbg_pte1_score_qwbeat_q, + htw_dbg_pte1_score_pending_q => htw_dbg_pte1_score_pending_q, + htw_dbg_pte1_score_ibit_q => htw_dbg_pte1_score_ibit_q, + htw_dbg_pte1_score_dataval_q => htw_dbg_pte1_score_dataval_q, + htw_dbg_pte1_reld_for_me_tm1 => htw_dbg_pte1_reld_for_me_tm1, + + mm_xu_lsu_req => mm_xu_lsu_req_sig, + mm_xu_lsu_ttype => mm_xu_lsu_ttype_sig, + mm_xu_lsu_wimge => mm_xu_lsu_wimge_sig, + mm_xu_lsu_u => mm_xu_lsu_u_sig, + mm_xu_lsu_addr => mm_xu_lsu_addr_sig, + mm_xu_lsu_lpid => mm_xu_lsu_lpid_sig, + mm_xu_lsu_gs => mm_xu_lsu_gs_sig, + mm_xu_lsu_ind => mm_xu_lsu_ind_sig, + mm_xu_lsu_lbit => mm_xu_lsu_lbit_sig, + xu_mm_lsu_token => xu_mm_lsu_token, + tlb_mas_tlbre => tlb_mas_tlbre, + tlb_mas_tlbsx_hit => tlb_mas_tlbsx_hit, + tlb_mas_tlbsx_miss => tlb_mas_tlbsx_miss, + tlb_mas_dtlb_error => tlb_mas_dtlb_error, + tlb_mas_itlb_error => tlb_mas_itlb_error, + tlb_mas_thdid => tlb_mas_thdid, + lrat_mas_tlbre => lrat_mas_tlbre, + lrat_mas_tlbsx_hit => lrat_mas_tlbsx_hit, + lrat_mas_tlbsx_miss => lrat_mas_tlbsx_miss, + lrat_mas_thdid => lrat_mas_thdid, + lrat_tag3_hit_status => lrat_tag3_hit_status, + lrat_tag3_hit_entry => lrat_tag3_hit_entry, + + tlb_seq_ierat_req => tlb_seq_ierat_req, + tlb_seq_derat_req => tlb_seq_derat_req, + mm_xu_hold_req => mm_xu_hold_req_sig, + xu_mm_hold_ack => xu_mm_hold_ack, + mm_xu_hold_done => mm_xu_hold_done_sig, + mmucsr0_tlb0fi => mmucsr0_tlb0fi, + tlbwe_back_inv_valid => tlbwe_back_inv_valid_sig, + tlbwe_back_inv_attr => tlbwe_back_inv_attr_sig(18 to 19), + xu_mm_lmq_stq_empty => xu_mm_lmq_stq_empty, + iu_mm_lmq_empty => iu_mm_lmq_empty, + mm_xu_eratmiss_done => mm_xu_eratmiss_done_sig, + mm_iu_barrier_done => mm_iu_barrier_done_sig, + mm_xu_ex3_flush_req => mm_xu_ex3_flush_req_sig, + mm_xu_illeg_instr => mm_xu_illeg_instr_sig, + lrat_tag4_hit_status => lrat_tag4_hit_status, + lrat_tag4_hit_entry => lrat_tag4_hit_entry, + mm_xu_cr0_eq => mm_xu_cr0_eq_sig, + mm_xu_cr0_eq_valid => mm_xu_cr0_eq_valid_sig, + tlb_htw_req_valid => tlb_htw_req_valid, + htw_lsu_req_valid => htw_lsu_req_valid, + htw_dbg_lsu_thdid => htw_dbg_lsu_thdid, + htw_lsu_ttype => htw_lsu_ttype, + htw_lsu_addr => htw_lsu_addr, + ptereload_req_taken => ptereload_req_taken, + ptereload_req_pte => ptereload_req_pte +); +mmq_perf: entity work.mmq_perf(mmq_perf) + generic map ( expand_type => expand_type ) + port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_func_sl_thold_2 => pc_func_sl_thold_2(0), + pc_func_slp_nsl_thold_2 => pc_func_slp_nsl_thold_2, + pc_sg_2 => pc_sg_2(0), + pc_fce_2 => pc_fce_2, + tc_ac_ccflush_dc => tc_ac_ccflush_dc, + lcb_clkoff_dc_b => lcb_clkoff_dc_b, + lcb_act_dis_dc => lcb_act_dis_dc, + lcb_d_mode_dc => lcb_d_mode_dc, + lcb_delay_lclkr_dc => lcb_delay_lclkr_dc(0), + lcb_mpw1_dc_b => lcb_mpw1_dc_b(0), + lcb_mpw2_dc_b => lcb_mpw2_dc_b, + scan_in => siv_1(mmq_perf_offset), + scan_out => sov_1(mmq_perf_offset), + + xu_mm_msr_gs => xu_mm_msr_gs, + xu_mm_msr_pr => xu_mm_msr_pr, + xu_mm_ccr2_notlb_b => xu_mm_ccr2_notlb_b(2), + + +xu_mm_ex5_perf_dtlb => xu_mm_ex5_perf_dtlb, + xu_mm_ex5_perf_itlb => xu_mm_ex5_perf_itlb, + + tlb_cmp_perf_event_t0 => tlb_cmp_perf_event_t0, + tlb_cmp_perf_event_t1 => tlb_cmp_perf_event_t1, + tlb_cmp_perf_event_t2 => tlb_cmp_perf_event_t2, + tlb_cmp_perf_event_t3 => tlb_cmp_perf_event_t3, + tlb_cmp_perf_state => tlb_cmp_perf_state, + + derat_req0_thdid => derat_req0_thdid_sig, + derat_req0_valid => derat_req0_valid_sig, + derat_req1_thdid => derat_req1_thdid_sig, + derat_req1_valid => derat_req1_valid_sig, + derat_req2_thdid => derat_req2_thdid_sig, + derat_req2_valid => derat_req2_valid_sig, + derat_req3_thdid => derat_req3_thdid_sig, + derat_req3_valid => derat_req3_valid_sig, + ierat_req0_thdid => ierat_req0_thdid_sig, + ierat_req0_valid => ierat_req0_valid_sig, + ierat_req0_nonspec => ierat_req0_nonspec_sig, + ierat_req1_thdid => ierat_req1_thdid_sig, + ierat_req1_valid => ierat_req1_valid_sig, + ierat_req1_nonspec => ierat_req1_nonspec_sig, + ierat_req2_thdid => ierat_req2_thdid_sig, + ierat_req2_valid => ierat_req2_valid_sig, + ierat_req2_nonspec => ierat_req2_nonspec_sig, + ierat_req3_thdid => ierat_req3_thdid_sig, + ierat_req3_valid => ierat_req3_valid_sig, + ierat_req3_nonspec => ierat_req3_nonspec_sig, + ierat_req_taken => ierat_req_taken, + derat_req_taken => derat_req_taken, + + tlb_tag0_thdid => tlb_tag0_thdid, + tlb_tag0_type => tlb_tag0_type(0 to 1), + tlb_seq_idle => tlb_seq_idle, + + inval_perf_tlbilx => inval_perf_tlbilx, + inval_perf_tlbivax => inval_perf_tlbivax, + inval_perf_tlbivax_snoop => inval_perf_tlbivax_snoop, + inval_perf_tlb_flush => inval_perf_tlb_flush, + + htw_req0_valid => htw_req0_valid, + htw_req0_thdid => htw_req0_thdid, + htw_req0_type => htw_req0_type, + htw_req1_valid => htw_req1_valid, + htw_req1_thdid => htw_req1_thdid, + htw_req1_type => htw_req1_type, + htw_req2_valid => htw_req2_valid, + htw_req2_thdid => htw_req2_thdid, + htw_req2_type => htw_req2_type, + htw_req3_valid => htw_req3_valid, + htw_req3_thdid => htw_req3_thdid, + htw_req3_type => htw_req3_type, + + tlb_cmp_perf_miss_direct => tlb_cmp_perf_miss_direct, + tlb_cmp_perf_hit_indirect => tlb_cmp_perf_hit_indirect, + tlb_cmp_perf_hit_first_page => tlb_cmp_perf_hit_first_page, + tlb_cmp_perf_ptereload_noexcep => tlb_cmp_perf_ptereload_noexcep, + tlb_cmp_perf_lrat_request => tlb_cmp_perf_lrat_request, + tlb_cmp_perf_lrat_miss => tlb_cmp_perf_lrat_miss, + tlb_cmp_perf_pt_fault => tlb_cmp_perf_pt_fault, + tlb_cmp_perf_pt_inelig => tlb_cmp_perf_pt_inelig, + tlb_ctl_perf_tlbwec_resv => tlb_ctl_perf_tlbwec_resv, + tlb_ctl_perf_tlbwec_noresv => tlb_ctl_perf_tlbwec_noresv, + + +pc_mm_event_mux_ctrls => pc_mm_event_mux_ctrls(0 to 39), + pc_mm_event_count_mode => pc_mm_event_count_mode(0 to 2), + rp_mm_event_bus_enable_q => rp_mm_event_bus_enable_q, + mm_pc_event_data => mm_pc_event_data(0 to 7) +); +mmq_perv : entity work.mmq_perv(mmq_perv) +generic map (expand_type => expand_type) +port map ( + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_mm_sg_3 => pc_mm_sg_3, + pc_mm_func_sl_thold_3 => pc_mm_func_sl_thold_3, + pc_mm_func_slp_sl_thold_3 => pc_mm_func_slp_sl_thold_3, + pc_mm_gptr_sl_thold_3 => pc_mm_gptr_sl_thold_3, + pc_mm_fce_3 => pc_mm_fce_3, + pc_mm_time_sl_thold_3 => pc_mm_time_sl_thold_3, + pc_mm_repr_sl_thold_3 => pc_mm_repr_sl_thold_3, + pc_mm_abst_sl_thold_3 => pc_mm_abst_sl_thold_3, + pc_mm_abst_slp_sl_thold_3 => pc_mm_abst_slp_sl_thold_3, + pc_mm_cfg_sl_thold_3 => pc_mm_cfg_sl_thold_3, + pc_mm_cfg_slp_sl_thold_3 => pc_mm_cfg_slp_sl_thold_3, + pc_mm_func_nsl_thold_3 => pc_mm_func_nsl_thold_3, + pc_mm_func_slp_nsl_thold_3 => pc_mm_func_slp_nsl_thold_3, + pc_mm_ary_nsl_thold_3 => pc_mm_ary_nsl_thold_3, + pc_mm_ary_slp_nsl_thold_3 => pc_mm_ary_slp_nsl_thold_3, + tc_ac_ccflush_dc => tc_ac_ccflush_dc, + tc_scan_diag_dc => tc_ac_scan_diag_dc, + tc_ac_scan_dis_dc_b => tc_ac_scan_dis_dc_b, + + pc_sg_0 => pc_sg_0, + pc_sg_1 => pc_sg_1, + pc_sg_2 => pc_sg_2, + pc_func_sl_thold_2 => pc_func_sl_thold_2, + pc_func_slp_sl_thold_2 => pc_func_slp_sl_thold_2, + pc_func_slp_nsl_thold_2 => pc_func_slp_nsl_thold_2, + pc_cfg_sl_thold_2 => pc_cfg_sl_thold_2, + pc_cfg_slp_sl_thold_2 => pc_cfg_slp_sl_thold_2, + pc_fce_2 => pc_fce_2, + pc_time_sl_thold_0 => pc_time_sl_thold_0, + pc_repr_sl_thold_0 => pc_repr_sl_thold_0, + pc_abst_sl_thold_0 => pc_abst_sl_thold_0, + pc_abst_slp_sl_thold_0 => pc_abst_slp_sl_thold_0, + pc_ary_nsl_thold_0 => pc_ary_nsl_thold_0, + pc_ary_slp_nsl_thold_0 => pc_ary_slp_nsl_thold_0, + pc_func_sl_thold_0 => pc_func_sl_thold_0, + pc_func_sl_thold_0_b => pc_func_sl_thold_0_b, + pc_func_slp_sl_thold_0 => pc_func_slp_sl_thold_0, + pc_func_slp_sl_thold_0_b => pc_func_slp_sl_thold_0_b, + lcb_clkoff_dc_b => lcb_clkoff_dc_b, + lcb_act_dis_dc => lcb_act_dis_dc, + lcb_d_mode_dc => lcb_d_mode_dc, + lcb_delay_lclkr_dc => lcb_delay_lclkr_dc, + lcb_mpw1_dc_b => lcb_mpw1_dc_b, + lcb_mpw2_dc_b => lcb_mpw2_dc_b, + g8t_gptr_lcb_clkoff_dc_b => g8t_gptr_lcb_clkoff_dc_b, + g8t_gptr_lcb_act_dis_dc => g8t_gptr_lcb_act_dis_dc, + g8t_gptr_lcb_d_mode_dc => g8t_gptr_lcb_d_mode_dc, + g8t_gptr_lcb_delay_lclkr_dc => g8t_gptr_lcb_delay_lclkr_dc, + g8t_gptr_lcb_mpw1_dc_b => g8t_gptr_lcb_mpw1_dc_b, + g8t_gptr_lcb_mpw2_dc_b => g8t_gptr_lcb_mpw2_dc_b, + g6t_gptr_lcb_clkoff_dc_b => g6t_gptr_lcb_clkoff_dc_b, + g6t_gptr_lcb_act_dis_dc => g6t_gptr_lcb_act_dis_dc, + g6t_gptr_lcb_d_mode_dc => g6t_gptr_lcb_d_mode_dc, + g6t_gptr_lcb_delay_lclkr_dc => g6t_gptr_lcb_delay_lclkr_dc, + g6t_gptr_lcb_mpw1_dc_b => g6t_gptr_lcb_mpw1_dc_b, + g6t_gptr_lcb_mpw2_dc_b => g6t_gptr_lcb_mpw2_dc_b, + + pc_mm_abist_dcomp_g6t_2r => pc_mm_abist_dcomp_g6t_2r, + pc_mm_abist_di_0 => pc_mm_abist_di_0, + pc_mm_abist_di_g6t_2r => pc_mm_abist_di_g6t_2r, + pc_mm_abist_ena_dc => pc_mm_abist_ena_dc, + pc_mm_abist_g6t_r_wb => pc_mm_abist_g6t_r_wb, + pc_mm_abist_g8t1p_renb_0 => pc_mm_abist_g8t1p_renb_0, + pc_mm_abist_g8t_bw_0 => pc_mm_abist_g8t_bw_0, + pc_mm_abist_g8t_bw_1 => pc_mm_abist_g8t_bw_1, + pc_mm_abist_g8t_dcomp => pc_mm_abist_g8t_dcomp, + pc_mm_abist_g8t_wenb => pc_mm_abist_g8t_wenb, + pc_mm_abist_raddr_0 => pc_mm_abist_raddr_0, + pc_mm_abist_waddr_0 => pc_mm_abist_waddr_0, + pc_mm_abist_wl128_comp_ena => pc_mm_abist_wl128_comp_ena, + + pc_mm_abist_g8t_wenb_q => pc_mm_abist_g8t_wenb_q, + pc_mm_abist_g8t1p_renb_0_q => pc_mm_abist_g8t1p_renb_0_q, + pc_mm_abist_di_0_q => pc_mm_abist_di_0_q, + pc_mm_abist_g8t_bw_1_q => pc_mm_abist_g8t_bw_1_q, + pc_mm_abist_g8t_bw_0_q => pc_mm_abist_g8t_bw_0_q, + pc_mm_abist_waddr_0_q => pc_mm_abist_waddr_0_q, + pc_mm_abist_raddr_0_q => pc_mm_abist_raddr_0_q, + pc_mm_abist_wl128_comp_ena_q => pc_mm_abist_wl128_comp_ena_q, + pc_mm_abist_g8t_dcomp_q => pc_mm_abist_g8t_dcomp_q, + pc_mm_abist_dcomp_g6t_2r_q => pc_mm_abist_dcomp_g6t_2r_q, + pc_mm_abist_di_g6t_2r_q => pc_mm_abist_di_g6t_2r_q, + pc_mm_abist_g6t_r_wb_q => pc_mm_abist_g6t_r_wb_q, + + pc_mm_bolt_sl_thold_3 => pc_mm_bolt_sl_thold_3, + pc_mm_bo_enable_3 => pc_mm_bo_enable_3, + pc_mm_bolt_sl_thold_0 => pc_mm_bolt_sl_thold_0, + pc_mm_bo_enable_2 => pc_mm_bo_enable_2, + + gptr_scan_in => gptr_scan_in, + gptr_scan_out => ac_an_gptr_scan_out, + + time_scan_in => time_scan_in, + time_scan_in_int => time_scan_in_int, + time_scan_out_int => time_scan_out_int, + time_scan_out => ac_an_time_scan_out, + + func_scan_in(0 to 8) => an_ac_func_scan_in(22 to 30), + func_scan_in(9) => an_ac_func_scan_in(59), + func_scan_in_int => func_scan_in_int, + func_scan_out_int => func_scan_out_int, + func_scan_out(0 to 8) => ac_an_func_scan_out(22 to 30), + func_scan_out(9) => ac_an_func_scan_out(59), + + repr_scan_in => repr_scan_in, + repr_scan_in_int => repr_scan_in_int, + repr_scan_out_int => repr_scan_out_int, + repr_scan_out => ac_an_repr_scan_out, + + abst_scan_in => an_ac_abst_scan_in(5 to 6), + abst_scan_in_int => abst_scan_in_int, + abst_scan_out_int => abst_scan_out_int, + abst_scan_out => ac_an_abst_scan_out(5 to 6), + + bcfg_scan_in => an_ac_bcfg_scan_in(2), + bcfg_scan_in_int => bcfg_scan_in_int, + bcfg_scan_out_int => bcfg_scan_out_int, + bcfg_scan_out => bcfg_scan_out, + + ccfg_scan_in => an_ac_bcfg_scan_in(0), + ccfg_scan_in_int => ccfg_scan_in_int, + ccfg_scan_out_int => ccfg_scan_out_int, + ccfg_scan_out => ccfg_scan_out, + + dcfg_scan_in => an_ac_dcfg_scan_in(0), + dcfg_scan_in_int => dcfg_scan_in_int, + dcfg_scan_out_int => dcfg_scan_out_int, + dcfg_scan_out => dcfg_scan_out + ); +eratonly_tieoffs_gen: if expand_tlb_type = 0 generate +mm_iu_ierat_rel_val_sig <= (others => '0'); +mm_iu_ierat_rel_data_sig <= (others => '0'); +mm_xu_derat_rel_val_sig <= (others => '0'); +mm_xu_derat_rel_data_sig <= (others => '0'); +tlb_cmp_ierat_dup_val_sig <= (others => '0'); +tlb_cmp_derat_dup_val_sig <= (others => '0'); +tlb_cmp_erat_dup_wait_sig <= (others => '0'); +tlb_ctl_barrier_done_sig <= (others => '0'); +tlb_ctl_ex2_flush_req_sig <= (others => '0'); +tlb_ctl_ex2_illeg_instr_sig <= (others => '0'); +tlb_req_quiesce_sig <= (others => '1'); +tlb_ctl_quiesce_sig <= (others => '1'); +htw_quiesce_sig <= (others => '1'); +tlb_cmp_perf_event_t0 <= (others => '0'); +tlb_cmp_perf_event_t1 <= (others => '0'); +tlb_cmp_perf_event_t2 <= (others => '0'); +tlb_cmp_perf_event_t3 <= (others => '0'); +tlb_cmp_perf_state <= (others => '0'); +derat_req0_thdid_sig <= (others => '0'); +derat_req0_valid_sig <= '0'; +derat_req1_thdid_sig <= (others => '0'); +derat_req1_valid_sig <= '0'; +derat_req2_thdid_sig <= (others => '0'); +derat_req2_valid_sig <= '0'; +derat_req3_thdid_sig <= (others => '0'); +derat_req3_valid_sig <= '0'; +ierat_req0_thdid_sig <= (others => '0'); +ierat_req0_valid_sig <= '0'; +ierat_req0_nonspec_sig <= '0'; +ierat_req1_thdid_sig <= (others => '0'); +ierat_req1_valid_sig <= '0'; +ierat_req1_nonspec_sig <= '0'; +ierat_req2_thdid_sig <= (others => '0'); +ierat_req2_valid_sig <= '0'; +ierat_req2_nonspec_sig <= '0'; +ierat_req3_thdid_sig <= (others => '0'); +ierat_req3_valid_sig <= '0'; +ierat_req3_nonspec_sig <= '0'; +tlb_tag0_thdid <= (others => '0'); +tlb_tag0_type <= (others => '0'); +tlb_seq_idle <= '0'; +htw_req0_valid <= '0'; +htw_req0_thdid <= (others => '0'); +htw_req0_type <= (others => '0'); +htw_req1_valid <= '0'; +htw_req1_thdid <= (others => '0'); +htw_req1_type <= (others => '0'); +htw_req2_valid <= '0'; +htw_req2_thdid <= (others => '0'); +htw_req2_type <= (others => '0'); +htw_req3_valid <= '0'; +htw_req3_thdid <= (others => '0'); +htw_req3_type <= (others => '0'); +tlb_cmp_perf_miss_direct <= '0'; +tlb_cmp_perf_hit_indirect <= '0'; +tlb_cmp_perf_hit_first_page <= '0'; +tlb_cmp_perf_ptereload_noexcep <= '0'; +tlb_cmp_perf_lrat_request <= '0'; +tlb_cmp_perf_lrat_miss <= '0'; +tlb_cmp_perf_pt_fault <= '0'; +tlb_cmp_perf_pt_inelig <= '0'; +tlb_ctl_perf_tlbwec_resv <= '0'; +tlb_ctl_perf_tlbwec_noresv <= '0'; +tlb_cmp_dbg_tag4 <= (others => '0'); +tlb_cmp_dbg_tag4_wayhit <= (others => '0'); +tlb_cmp_dbg_addr4 <= (others => '0'); +tlb_cmp_dbg_tag4_way <= (others => '0'); +mm_xu_eratmiss_done_sig <= (others => '0'); +mm_xu_tlb_miss_sig <= (others => '0'); +mm_xu_lrat_miss_sig <= (others => '0'); +mm_xu_tlb_inelig_sig <= (others => '0'); +mm_xu_pt_fault_sig <= (others => '0'); +mm_xu_hv_priv_sig <= (others => '0'); +mm_xu_cr0_eq_sig <= (others => '0'); +mm_xu_cr0_eq_valid_sig <= (others => '0'); +mm_xu_esr_pt_sig <= (others => '0'); +mm_xu_esr_data_sig <= (others => '0'); +mm_xu_esr_epid_sig <= (others => '0'); +mm_xu_esr_st_sig <= (others => '0'); +mm_xu_tlb_multihit_err <= (others => '0'); +mm_xu_tlb_par_err <= (others => '0'); +mm_xu_lru_par_err <= (others => '0'); +tlb_snoop_ack <= '0'; +end generate eratonly_tieoffs_gen; +mm_iu_ierat_rel_val <= mm_iu_ierat_rel_val_sig; +mm_iu_ierat_rel_data <= mm_iu_ierat_rel_data_sig; +mm_xu_derat_rel_val <= mm_xu_derat_rel_val_sig; +mm_xu_derat_rel_data <= mm_xu_derat_rel_data_sig; +mm_xu_hold_req <= mm_xu_hold_req_sig; +mm_xu_hold_done <= mm_xu_hold_done_sig; +mm_iu_barrier_done <= mm_iu_barrier_done_sig; +mm_xu_eratmiss_done <= mm_xu_eratmiss_done_sig; +mm_xu_tlb_miss <= mm_xu_tlb_miss_sig; +mm_xu_lrat_miss <= mm_xu_lrat_miss_sig; +mm_xu_tlb_inelig <= mm_xu_tlb_inelig_sig; +mm_xu_pt_fault <= mm_xu_pt_fault_sig; +mm_xu_hv_priv <= mm_xu_hv_priv_sig; +mm_xu_illeg_instr <= mm_xu_illeg_instr_sig; +mm_xu_esr_pt <= mm_xu_esr_pt_sig; +mm_xu_esr_data <= mm_xu_esr_data_sig; +mm_xu_esr_epid <= mm_xu_esr_epid_sig; +mm_xu_esr_st <= mm_xu_esr_st_sig; +mm_xu_cr0_eq <= mm_xu_cr0_eq_sig; +mm_xu_cr0_eq_valid <= mm_xu_cr0_eq_valid_sig; +mm_xu_quiesce <= mm_xu_quiesce_sig; +mm_xu_local_snoop_reject <= mm_xu_local_snoop_reject_sig; +mm_xu_ex3_flush_req <= mm_xu_ex3_flush_req_sig; +mm_xu_lsu_req <= mm_xu_lsu_req_sig; +mm_xu_lsu_ttype <= mm_xu_lsu_ttype_sig; +mm_xu_lsu_wimge <= mm_xu_lsu_wimge_sig; +mm_xu_lsu_u <= mm_xu_lsu_u_sig; +mm_xu_lsu_addr <= mm_xu_lsu_addr_sig; +mm_xu_lsu_lpid <= mm_xu_lsu_lpid_sig; +mm_xu_lsu_gs <= mm_xu_lsu_gs_sig; +mm_xu_lsu_ind <= mm_xu_lsu_ind_sig; +mm_xu_lsu_lbit <= mm_xu_lsu_lbit_sig; +tlb_gen_logic: if expand_tlb_type > 0 generate +mmq_tlb_req: entity work.mmq_tlb_req(mmq_tlb_req) + generic map ( pid_width => pid_width, + pid_width_erat => pid_width_erat, + lpid_width => lpid_width, + req_epn_width => req_epn_width, + rs_data_width => rs_data_width, + expand_type => expand_type ) + port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + tc_ccflush_dc => tc_ac_ccflush_dc, + tc_scan_dis_dc_b => tc_ac_scan_dis_dc_b, + tc_scan_diag_dc => tc_ac_scan_diag_dc, + tc_lbist_en_dc => tc_ac_lbist_en_dc, + + lcb_d_mode_dc => lcb_d_mode_dc, + lcb_clkoff_dc_b => lcb_clkoff_dc_b, + lcb_act_dis_dc => lcb_act_dis_dc, + lcb_mpw1_dc_b => lcb_mpw1_dc_b, + lcb_mpw2_dc_b => lcb_mpw2_dc_b, + lcb_delay_lclkr_dc => lcb_delay_lclkr_dc, + + ac_func_scan_in => func_scan_in_int(2), + ac_func_scan_out => func_scan_out_int(2), + + pc_sg_2 => pc_sg_2(1), + pc_func_sl_thold_2 => pc_func_sl_thold_2(1), + pc_func_slp_sl_thold_2 => pc_func_slp_sl_thold_2(1), + pid0 => pid0_sig, + pid1 => pid1_sig, + pid2 => pid2_sig, + pid3 => pid3_sig, + lpidr => lpidr_sig, + xu_mm_ccr2_notlb_b => xu_mm_ccr2_notlb_b(3), + mmucr2_act_override => mmucr2_sig(0), + iu_mm_ierat_req => iu_mm_ierat_req, + iu_mm_ierat_epn => iu_mm_ierat_epn, + iu_mm_ierat_thdid => iu_mm_ierat_thdid, + iu_mm_ierat_state => iu_mm_ierat_state, + iu_mm_ierat_tid => iu_mm_ierat_tid, + iu_mm_ierat_flush => iu_mm_ierat_flush, + + xu_mm_derat_req => xu_mm_derat_req, + xu_mm_derat_epn => xu_mm_derat_epn, + xu_mm_derat_thdid => xu_mm_derat_thdid, + xu_mm_derat_ttype => xu_mm_derat_ttype, + xu_mm_derat_state => xu_mm_derat_state, + xu_mm_derat_tid => xu_mm_derat_tid, + xu_mm_derat_lpid => xu_mm_derat_lpid, + + ierat_req0_pid => ierat_req0_pid_sig, + ierat_req0_as => ierat_req0_as_sig, + ierat_req0_gs => ierat_req0_gs_sig, + ierat_req0_epn => ierat_req0_epn_sig, + ierat_req0_thdid => ierat_req0_thdid_sig, + ierat_req0_valid => ierat_req0_valid_sig, + ierat_req0_nonspec => ierat_req0_nonspec_sig, + ierat_req1_pid => ierat_req1_pid_sig, + ierat_req1_as => ierat_req1_as_sig, + ierat_req1_gs => ierat_req1_gs_sig, + ierat_req1_epn => ierat_req1_epn_sig, + ierat_req1_thdid => ierat_req1_thdid_sig, + ierat_req1_valid => ierat_req1_valid_sig, + ierat_req1_nonspec => ierat_req1_nonspec_sig, + ierat_req2_pid => ierat_req2_pid_sig, + ierat_req2_as => ierat_req2_as_sig, + ierat_req2_gs => ierat_req2_gs_sig, + ierat_req2_epn => ierat_req2_epn_sig, + ierat_req2_thdid => ierat_req2_thdid_sig, + ierat_req2_valid => ierat_req2_valid_sig, + ierat_req2_nonspec => ierat_req2_nonspec_sig, + ierat_req3_pid => ierat_req3_pid_sig, + ierat_req3_as => ierat_req3_as_sig, + ierat_req3_gs => ierat_req3_gs_sig, + ierat_req3_epn => ierat_req3_epn_sig, + ierat_req3_thdid => ierat_req3_thdid_sig, + ierat_req3_valid => ierat_req3_valid_sig, + ierat_req3_nonspec => ierat_req3_nonspec_sig, + ierat_iu4_pid => ierat_iu4_pid_sig, + ierat_iu4_gs => ierat_iu4_gs_sig, + ierat_iu4_as => ierat_iu4_as_sig, + ierat_iu4_epn => ierat_iu4_epn_sig, + ierat_iu4_thdid => ierat_iu4_thdid_sig, + ierat_iu4_valid => ierat_iu4_valid_sig, + + derat_req0_lpid => derat_req0_lpid_sig, + derat_req0_pid => derat_req0_pid_sig, + derat_req0_as => derat_req0_as_sig, + derat_req0_gs => derat_req0_gs_sig, + derat_req0_epn => derat_req0_epn_sig, + derat_req0_thdid => derat_req0_thdid_sig, + derat_req0_valid => derat_req0_valid_sig, + derat_req1_lpid => derat_req1_lpid_sig, + derat_req1_pid => derat_req1_pid_sig, + derat_req1_as => derat_req1_as_sig, + derat_req1_gs => derat_req1_gs_sig, + derat_req1_epn => derat_req1_epn_sig, + derat_req1_thdid => derat_req1_thdid_sig, + derat_req1_valid => derat_req1_valid_sig, + derat_req2_lpid => derat_req2_lpid_sig, + derat_req2_pid => derat_req2_pid_sig, + derat_req2_as => derat_req2_as_sig, + derat_req2_gs => derat_req2_gs_sig, + derat_req2_epn => derat_req2_epn_sig, + derat_req2_thdid => derat_req2_thdid_sig, + derat_req2_valid => derat_req2_valid_sig, + derat_req3_lpid => derat_req3_lpid_sig, + derat_req3_pid => derat_req3_pid_sig, + derat_req3_as => derat_req3_as_sig, + derat_req3_gs => derat_req3_gs_sig, + derat_req3_epn => derat_req3_epn_sig, + derat_req3_thdid => derat_req3_thdid_sig, + derat_req3_valid => derat_req3_valid_sig, + derat_ex5_lpid => derat_ex5_lpid_sig, + derat_ex5_pid => derat_ex5_pid_sig, + derat_ex5_gs => derat_ex5_gs_sig, + derat_ex5_as => derat_ex5_as_sig, + derat_ex5_epn => derat_ex5_epn_sig, + derat_ex5_thdid => derat_ex5_thdid_sig, + derat_ex5_valid => derat_ex5_valid_sig, + + xu_ex3_flush => xu_ex3_flush, + xu_mm_ex4_flush => xu_mm_ex4_flush, + xu_mm_ex5_flush => xu_mm_ex5_flush, + xu_mm_ierat_flush => xu_mm_ierat_flush, + xu_mm_ierat_miss => xu_mm_ierat_miss, + + mm_xu_eratmiss_done => mm_xu_eratmiss_done_sig, + mm_xu_tlb_miss => mm_xu_tlb_miss_sig, + + tlb_cmp_ierat_dup_val => tlb_cmp_ierat_dup_val_sig, + tlb_cmp_derat_dup_val => tlb_cmp_derat_dup_val_sig, + + tlb_seq_ierat_req => tlb_seq_ierat_req, + tlb_seq_derat_req => tlb_seq_derat_req, + tlb_seq_ierat_done => tlb_seq_ierat_done, + tlb_seq_derat_done => tlb_seq_derat_done, + ierat_req_taken => ierat_req_taken, + derat_req_taken => derat_req_taken, + ierat_req_epn => ierat_req_epn, + ierat_req_pid => ierat_req_pid, + ierat_req_state => ierat_req_state, + ierat_req_thdid => ierat_req_thdid, + ierat_req_dup => ierat_req_dup, + derat_req_epn => derat_req_epn, + derat_req_pid => derat_req_pid, + derat_req_lpid => derat_req_lpid, + derat_req_state => derat_req_state, + derat_req_ttype => derat_req_ttype, + derat_req_thdid => derat_req_thdid, + derat_req_dup => derat_req_dup, + + tlb_req_quiesce => tlb_req_quiesce_sig, + + tlb_req_dbg_ierat_iu5_valid_q => tlb_req_dbg_ierat_iu5_valid_q, + tlb_req_dbg_ierat_iu5_thdid => tlb_req_dbg_ierat_iu5_thdid, + tlb_req_dbg_ierat_iu5_state_q => tlb_req_dbg_ierat_iu5_state_q, + tlb_req_dbg_ierat_inptr_q => tlb_req_dbg_ierat_inptr_q, + tlb_req_dbg_ierat_outptr_q => tlb_req_dbg_ierat_outptr_q, + tlb_req_dbg_ierat_req_valid_q => tlb_req_dbg_ierat_req_valid_q, + tlb_req_dbg_ierat_req_nonspec_q => tlb_req_dbg_ierat_req_nonspec_q, + tlb_req_dbg_ierat_req_thdid => tlb_req_dbg_ierat_req_thdid, + tlb_req_dbg_ierat_req_dup_q => tlb_req_dbg_ierat_req_dup_q, + tlb_req_dbg_derat_ex6_valid_q => tlb_req_dbg_derat_ex6_valid_q, + tlb_req_dbg_derat_ex6_thdid => tlb_req_dbg_derat_ex6_thdid, + tlb_req_dbg_derat_ex6_state_q => tlb_req_dbg_derat_ex6_state_q, + tlb_req_dbg_derat_inptr_q => tlb_req_dbg_derat_inptr_q, + tlb_req_dbg_derat_outptr_q => tlb_req_dbg_derat_outptr_q, + tlb_req_dbg_derat_req_valid_q => tlb_req_dbg_derat_req_valid_q, + tlb_req_dbg_derat_req_thdid => tlb_req_dbg_derat_req_thdid, + tlb_req_dbg_derat_req_ttype_q => tlb_req_dbg_derat_req_ttype_q, + tlb_req_dbg_derat_req_dup_q => tlb_req_dbg_derat_req_dup_q +); +mmq_tlb_ctl: entity work.mmq_tlb_ctl(mmq_tlb_ctl) + generic map ( epn_width => epn_width, + pid_width => pid_width, + real_addr_width => real_addr_width, + rs_data_width => rs_data_width, + data_out_width => data_out_width, + tlb_tag_width => tlb_tag_width, + expand_type => expand_type ) + port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + tc_ccflush_dc => tc_ac_ccflush_dc, + tc_scan_dis_dc_b => tc_ac_scan_dis_dc_b, + tc_scan_diag_dc => tc_ac_scan_diag_dc, + tc_lbist_en_dc => tc_ac_lbist_en_dc, + + lcb_d_mode_dc => lcb_d_mode_dc, + lcb_clkoff_dc_b => lcb_clkoff_dc_b, + lcb_act_dis_dc => lcb_act_dis_dc, + lcb_mpw1_dc_b => lcb_mpw1_dc_b, + lcb_mpw2_dc_b => lcb_mpw2_dc_b, + lcb_delay_lclkr_dc => lcb_delay_lclkr_dc, + + ac_func_scan_in => func_scan_in_int(3), + ac_func_scan_out => func_scan_out_int(3), + + pc_sg_2 => pc_sg_2(1), + pc_func_sl_thold_2 => pc_func_sl_thold_2(1), + pc_func_slp_sl_thold_2 => pc_func_slp_sl_thold_2(1), + pc_func_slp_nsl_thold_2 => pc_func_slp_nsl_thold_2, + pc_fce_2 => pc_fce_2, + xu_mm_rf1_val => xu_mm_rf1_val, + xu_mm_rf1_is_tlbre => xu_mm_rf1_is_tlbre, + xu_mm_rf1_is_tlbwe => xu_mm_rf1_is_tlbwe, + xu_mm_rf1_is_tlbsx => xu_mm_rf1_is_tlbsx, + xu_mm_rf1_is_tlbsxr => xu_mm_rf1_is_tlbsxr, + xu_mm_rf1_is_tlbsrx => xu_mm_rf1_is_tlbsrx, + xu_mm_ex2_epn => xu_mm_ex2_eff_addr_sig(64-rs_data_width to 51), + + xu_mm_msr_gs => xu_mm_msr_gs, + xu_mm_msr_pr => xu_mm_msr_pr, + xu_mm_msr_is => xu_mm_msr_is, + xu_mm_msr_ds => xu_mm_msr_ds, + xu_mm_msr_cm => xu_mm_msr_cm, + + xu_mm_ccr2_notlb_b => xu_mm_ccr2_notlb_b(4), + xu_mm_epcr_dgtmi => xu_mm_epcr_dgtmi_sig, + xu_mm_xucr4_mmu_mchk => xu_mm_xucr4_mmu_mchk, + xu_mm_xucr4_mmu_mchk_q => xu_mm_xucr4_mmu_mchk_q, + xu_rf1_flush => xu_rf1_flush, + xu_ex1_flush => xu_ex1_flush, + xu_ex2_flush => xu_ex2_flush, + xu_ex3_flush => xu_ex3_flush, + xu_ex4_flush => xu_ex4_flush, + xu_ex5_flush => xu_ex5_flush, + + tlb_ctl_ex3_valid => tlb_ctl_ex3_valid_sig, + tlb_ctl_ex3_ttype => tlb_ctl_ex3_ttype_sig, + + tlb_ctl_tag2_flush => tlb_ctl_tag2_flush_sig, + tlb_ctl_tag3_flush => tlb_ctl_tag3_flush_sig, + tlb_ctl_tag4_flush => tlb_ctl_tag4_flush_sig, + tlb_resv_match_vec => tlb_resv_match_vec_sig, + tlb_ctl_barrier_done => tlb_ctl_barrier_done_sig, + tlb_ctl_ex2_flush_req => tlb_ctl_ex2_flush_req_sig, + tlb_ctl_ex2_illeg_instr => tlb_ctl_ex2_illeg_instr_sig, + tlb_ctl_quiesce => tlb_ctl_quiesce_sig, + ex6_illeg_instr => ex6_illeg_instr, + + mm_xu_eratmiss_done => mm_xu_eratmiss_done_sig, + mm_xu_tlb_miss => mm_xu_tlb_miss_sig, + mm_xu_tlb_inelig => mm_xu_tlb_inelig_sig, + + tlbwe_back_inv_pending => tlbwe_back_inv_pending_sig, + pid0 => pid0_sig, + pid1 => pid1_sig, + pid2 => pid2_sig, + pid3 => pid3_sig, + mmucr1_tlbi_msb => mmucr1_sig(18), + mmucr1_tlbwe_binv => mmucr1_sig(17), + mmucr2 => mmucr2_sig, + mmucr3_0 => mmucr3_0_sig, + mmucr3_1 => mmucr3_1_sig, + mmucr3_2 => mmucr3_2_sig, + mmucr3_3 => mmucr3_3_sig, + lpidr => lpidr_sig, + mmucfg_lrat => mmucfg_lrat, + mmucfg_twc => mmucfg_twc, + mmucsr0_tlb0fi => mmucsr0_tlb0fi, + tlb0cfg_pt => tlb0cfg_pt, + tlb0cfg_ind => tlb0cfg_ind, + tlb0cfg_gtwe => tlb0cfg_gtwe, + + mas0_0_atsel => mas0_0_atsel, + mas0_0_esel => mas0_0_esel, + mas0_0_hes => mas0_0_hes, + mas0_0_wq => mas0_0_wq, + mas1_0_v => mas1_0_v, + mas1_0_iprot => mas1_0_iprot, + mas1_0_tid => mas1_0_tid, + mas1_0_ind => mas1_0_ind, + mas1_0_ts => mas1_0_ts, + mas1_0_tsize => mas1_0_tsize, + mas2_0_epn => mas2_0_epn, + mas2_0_wimge => mas2_0_wimge, + mas3_0_usxwr => mas3_0_usxwr(0 to 3), + mas5_0_sgs => mas5_0_sgs, + mas5_0_slpid => mas5_0_slpid, + mas6_0_spid => mas6_0_spid, + mas6_0_sind => mas6_0_sind, + mas6_0_sas => mas6_0_sas, + mas8_0_tgs => mas8_0_tgs, + mas8_0_tlpid => mas8_0_tlpid, + mas0_1_atsel => mas0_1_atsel, + mas0_1_esel => mas0_1_esel, + mas0_1_hes => mas0_1_hes, + mas0_1_wq => mas0_1_wq, + mas1_1_v => mas1_1_v, + mas1_1_iprot => mas1_1_iprot, + mas1_1_tid => mas1_1_tid, + mas1_1_ind => mas1_1_ind, + mas1_1_ts => mas1_1_ts, + mas1_1_tsize => mas1_1_tsize, + mas2_1_epn => mas2_1_epn, + mas2_1_wimge => mas2_1_wimge, + mas3_1_usxwr => mas3_1_usxwr(0 to 3), + mas5_1_sgs => mas5_1_sgs, + mas5_1_slpid => mas5_1_slpid, + mas6_1_spid => mas6_1_spid, + mas6_1_sind => mas6_1_sind, + mas6_1_sas => mas6_1_sas, + mas8_1_tgs => mas8_1_tgs, + mas8_1_tlpid => mas8_1_tlpid, + mas0_2_atsel => mas0_2_atsel, + mas0_2_esel => mas0_2_esel, + mas0_2_hes => mas0_2_hes, + mas0_2_wq => mas0_2_wq, + mas1_2_v => mas1_2_v, + mas1_2_iprot => mas1_2_iprot, + mas1_2_tid => mas1_2_tid, + mas1_2_ind => mas1_2_ind, + mas1_2_ts => mas1_2_ts, + mas1_2_tsize => mas1_2_tsize, + mas2_2_epn => mas2_2_epn, + mas2_2_wimge => mas2_2_wimge, + mas3_2_usxwr => mas3_2_usxwr(0 to 3), + mas5_2_sgs => mas5_2_sgs, + mas5_2_slpid => mas5_2_slpid, + mas6_2_spid => mas6_2_spid, + mas6_2_sind => mas6_2_sind, + mas6_2_sas => mas6_2_sas, + mas8_2_tgs => mas8_2_tgs, + mas8_2_tlpid => mas8_2_tlpid, + mas0_3_atsel => mas0_3_atsel, + mas0_3_esel => mas0_3_esel, + mas0_3_hes => mas0_3_hes, + mas0_3_wq => mas0_3_wq, + mas1_3_v => mas1_3_v, + mas1_3_iprot => mas1_3_iprot, + mas1_3_tid => mas1_3_tid, + mas1_3_ind => mas1_3_ind, + mas1_3_ts => mas1_3_ts, + mas1_3_tsize => mas1_3_tsize, + mas2_3_epn => mas2_3_epn, + mas2_3_wimge => mas2_3_wimge, + mas3_3_usxwr => mas3_3_usxwr(0 to 3), + mas5_3_sgs => mas5_3_sgs, + mas5_3_slpid => mas5_3_slpid, + mas6_3_spid => mas6_3_spid, + mas6_3_sind => mas6_3_sind, + mas6_3_sas => mas6_3_sas, + mas8_3_tgs => mas8_3_tgs, + mas8_3_tlpid => mas8_3_tlpid, + + tlb_seq_ierat_req => tlb_seq_ierat_req, + tlb_seq_derat_req => tlb_seq_derat_req, + tlb_seq_ierat_done => tlb_seq_ierat_done, + tlb_seq_derat_done => tlb_seq_derat_done, + tlb_seq_idle => tlb_seq_idle, + ierat_req_taken => ierat_req_taken, + derat_req_taken => derat_req_taken, + ierat_req_epn => ierat_req_epn, + ierat_req_pid => ierat_req_pid, + ierat_req_state => ierat_req_state, + ierat_req_thdid => ierat_req_thdid, + ierat_req_dup => ierat_req_dup, + derat_req_epn => derat_req_epn, + derat_req_pid => derat_req_pid, + derat_req_lpid => derat_req_lpid, + derat_req_state => derat_req_state, + derat_req_ttype => derat_req_ttype, + derat_req_thdid => derat_req_thdid, + derat_req_dup => derat_req_dup, + ptereload_req_valid => ptereload_req_valid, + ptereload_req_tag => ptereload_req_tag, + ptereload_req_pte => ptereload_req_pte, + ptereload_req_taken => ptereload_req_taken, + + tlb_snoop_coming => tlb_snoop_coming, + tlb_snoop_val => tlb_snoop_val, + tlb_snoop_attr => tlb_snoop_attr, + tlb_snoop_vpn => tlb_snoop_vpn, + tlb_snoop_ack => tlb_snoop_ack, + + lru_rd_addr => lru_rd_addr, + lru_tag4_dataout => lru_tag4_dataout, + tlb_tag4_esel => tlb_tag4_esel, + tlb_tag4_wq => tlb_tag4_wq, + tlb_tag4_is => tlb_tag4_is, + tlb_tag4_gs => tlb_tag4_gs, + tlb_tag4_pr => tlb_tag4_pr, + tlb_tag4_hes => tlb_tag4_hes, + tlb_tag4_atsel => tlb_tag4_atsel, + tlb_tag4_pt => tlb_tag4_pt, + tlb_tag4_cmp_hit => tlb_tag4_cmp_hit, + tlb_tag4_way_ind => tlb_tag4_way_ind, + tlb_tag4_ptereload => tlb_tag4_ptereload, + tlb_tag4_endflag => tlb_tag4_endflag, + tlb_tag4_parerr => tlb_tag4_parerr, + tlb_tag5_except => tlb_tag5_except, + tlb_cmp_erat_dup_wait => tlb_cmp_erat_dup_wait_sig, + + tlb_tag0_epn => tlb_tag0_epn, + tlb_tag0_thdid => tlb_tag0_thdid, + tlb_tag0_type => tlb_tag0_type, + tlb_tag0_lpid => tlb_tag0_lpid, + tlb_tag0_atsel => tlb_tag0_atsel, + tlb_tag0_size => tlb_tag0_size, + tlb_tag0_addr_cap => tlb_tag0_addr_cap, + + tlb_tag2 => tlb_tag2_sig, + tlb_addr2 => tlb_addr2_sig, + + tlb_ctl_perf_tlbwec_resv => tlb_ctl_perf_tlbwec_resv, + tlb_ctl_perf_tlbwec_noresv => tlb_ctl_perf_tlbwec_noresv, + + lrat_tag4_hit_status => lrat_tag4_hit_status, + + tlb_lper_lpn => tlb_lper_lpn, + tlb_lper_lps => tlb_lper_lps, + tlb_lper_we => tlb_lper_we, + + ptereload_req_pte_lat => ptereload_req_pte_lat, + pte_tag0_lpn => pte_tag0_lpn(64-real_addr_width to 51), + pte_tag0_lpid => pte_tag0_lpid, + + tlb_write => tlb_write, + tlb_addr => tlb_addr, + tlb_tag5_write => tlb_tag5_write, + tlb_delayed_act => tlb_delayed_act, + + tlb_ctl_dbg_seq_q => tlb_ctl_dbg_seq_q, + tlb_ctl_dbg_seq_idle => tlb_ctl_dbg_seq_idle, + tlb_ctl_dbg_seq_any_done_sig => tlb_ctl_dbg_seq_any_done_sig, + tlb_ctl_dbg_seq_abort => tlb_ctl_dbg_seq_abort, + tlb_ctl_dbg_any_tlb_req_sig => tlb_ctl_dbg_any_tlb_req_sig, + tlb_ctl_dbg_any_req_taken_sig => tlb_ctl_dbg_any_req_taken_sig, + tlb_ctl_dbg_tag0_valid => tlb_ctl_dbg_tag0_valid, + tlb_ctl_dbg_tag0_thdid => tlb_ctl_dbg_tag0_thdid, + tlb_ctl_dbg_tag0_type => tlb_ctl_dbg_tag0_type, + tlb_ctl_dbg_tag0_wq => tlb_ctl_dbg_tag0_wq, + tlb_ctl_dbg_tag0_gs => tlb_ctl_dbg_tag0_gs, + tlb_ctl_dbg_tag0_pr => tlb_ctl_dbg_tag0_pr, + tlb_ctl_dbg_tag0_atsel => tlb_ctl_dbg_tag0_atsel, + tlb_ctl_dbg_tag5_tlb_write_q => tlb_ctl_dbg_tag5_tlb_write_q, + tlb_ctl_dbg_resv_valid => tlb_ctl_dbg_resv_valid, + tlb_ctl_dbg_set_resv => tlb_ctl_dbg_set_resv, + tlb_ctl_dbg_resv_match_vec_q => tlb_ctl_dbg_resv_match_vec_q, + tlb_ctl_dbg_any_tag_flush_sig => tlb_ctl_dbg_any_tag_flush_sig, + tlb_ctl_dbg_resv0_tag0_lpid_match => tlb_ctl_dbg_resv0_tag0_lpid_match, + tlb_ctl_dbg_resv0_tag0_pid_match => tlb_ctl_dbg_resv0_tag0_pid_match, + tlb_ctl_dbg_resv0_tag0_as_snoop_match => tlb_ctl_dbg_resv0_tag0_as_snoop_match, + tlb_ctl_dbg_resv0_tag0_gs_snoop_match => tlb_ctl_dbg_resv0_tag0_gs_snoop_match, + tlb_ctl_dbg_resv0_tag0_as_tlbwe_match => tlb_ctl_dbg_resv0_tag0_as_tlbwe_match, + tlb_ctl_dbg_resv0_tag0_gs_tlbwe_match => tlb_ctl_dbg_resv0_tag0_gs_tlbwe_match, + tlb_ctl_dbg_resv0_tag0_ind_match => tlb_ctl_dbg_resv0_tag0_ind_match, + tlb_ctl_dbg_resv0_tag0_epn_loc_match => tlb_ctl_dbg_resv0_tag0_epn_loc_match, + tlb_ctl_dbg_resv0_tag0_epn_glob_match => tlb_ctl_dbg_resv0_tag0_epn_glob_match, + tlb_ctl_dbg_resv0_tag0_class_match => tlb_ctl_dbg_resv0_tag0_class_match, + tlb_ctl_dbg_resv1_tag0_lpid_match => tlb_ctl_dbg_resv1_tag0_lpid_match, + tlb_ctl_dbg_resv1_tag0_pid_match => tlb_ctl_dbg_resv1_tag0_pid_match, + tlb_ctl_dbg_resv1_tag0_as_snoop_match => tlb_ctl_dbg_resv1_tag0_as_snoop_match, + tlb_ctl_dbg_resv1_tag0_gs_snoop_match => tlb_ctl_dbg_resv1_tag0_gs_snoop_match, + tlb_ctl_dbg_resv1_tag0_as_tlbwe_match => tlb_ctl_dbg_resv1_tag0_as_tlbwe_match, + tlb_ctl_dbg_resv1_tag0_gs_tlbwe_match => tlb_ctl_dbg_resv1_tag0_gs_tlbwe_match, + tlb_ctl_dbg_resv1_tag0_ind_match => tlb_ctl_dbg_resv1_tag0_ind_match, + tlb_ctl_dbg_resv1_tag0_epn_loc_match => tlb_ctl_dbg_resv1_tag0_epn_loc_match, + tlb_ctl_dbg_resv1_tag0_epn_glob_match => tlb_ctl_dbg_resv1_tag0_epn_glob_match, + tlb_ctl_dbg_resv1_tag0_class_match => tlb_ctl_dbg_resv1_tag0_class_match , + tlb_ctl_dbg_resv2_tag0_lpid_match => tlb_ctl_dbg_resv2_tag0_lpid_match, + tlb_ctl_dbg_resv2_tag0_pid_match => tlb_ctl_dbg_resv2_tag0_pid_match, + tlb_ctl_dbg_resv2_tag0_as_snoop_match => tlb_ctl_dbg_resv2_tag0_as_snoop_match, + tlb_ctl_dbg_resv2_tag0_gs_snoop_match => tlb_ctl_dbg_resv2_tag0_gs_snoop_match, + tlb_ctl_dbg_resv2_tag0_as_tlbwe_match => tlb_ctl_dbg_resv2_tag0_as_tlbwe_match, + tlb_ctl_dbg_resv2_tag0_gs_tlbwe_match => tlb_ctl_dbg_resv2_tag0_gs_tlbwe_match, + tlb_ctl_dbg_resv2_tag0_ind_match => tlb_ctl_dbg_resv2_tag0_ind_match, + tlb_ctl_dbg_resv2_tag0_epn_loc_match => tlb_ctl_dbg_resv2_tag0_epn_loc_match, + tlb_ctl_dbg_resv2_tag0_epn_glob_match => tlb_ctl_dbg_resv2_tag0_epn_glob_match, + tlb_ctl_dbg_resv2_tag0_class_match => tlb_ctl_dbg_resv2_tag0_class_match, + tlb_ctl_dbg_resv3_tag0_lpid_match => tlb_ctl_dbg_resv3_tag0_lpid_match, + tlb_ctl_dbg_resv3_tag0_pid_match => tlb_ctl_dbg_resv3_tag0_pid_match, + tlb_ctl_dbg_resv3_tag0_as_snoop_match => tlb_ctl_dbg_resv3_tag0_as_snoop_match, + tlb_ctl_dbg_resv3_tag0_gs_snoop_match => tlb_ctl_dbg_resv3_tag0_gs_snoop_match, + tlb_ctl_dbg_resv3_tag0_as_tlbwe_match => tlb_ctl_dbg_resv3_tag0_as_tlbwe_match, + tlb_ctl_dbg_resv3_tag0_gs_tlbwe_match => tlb_ctl_dbg_resv3_tag0_gs_tlbwe_match, + tlb_ctl_dbg_resv3_tag0_ind_match => tlb_ctl_dbg_resv3_tag0_ind_match, + tlb_ctl_dbg_resv3_tag0_epn_loc_match => tlb_ctl_dbg_resv3_tag0_epn_loc_match, + tlb_ctl_dbg_resv3_tag0_epn_glob_match => tlb_ctl_dbg_resv3_tag0_epn_glob_match, + tlb_ctl_dbg_resv3_tag0_class_match => tlb_ctl_dbg_resv3_tag0_class_match, + tlb_ctl_dbg_clr_resv_q => tlb_ctl_dbg_clr_resv_q, + tlb_ctl_dbg_clr_resv_terms => tlb_ctl_dbg_clr_resv_terms +); +mmq_tlb_cmp: entity work.mmq_tlb_cmp(mmq_tlb_cmp) + generic map ( epn_width => epn_width, + pid_width => pid_width, + pid_width_erat => pid_width_erat, + tlb_tag_width => tlb_tag_width, + mmq_tlb_cmp_cswitch_0to7 => mmq_tlb_cmp_cswitch_0to7, + expand_type => expand_type ) + port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + tc_ccflush_dc => tc_ac_ccflush_dc, + tc_scan_dis_dc_b => tc_ac_scan_dis_dc_b, + tc_scan_diag_dc => tc_ac_scan_diag_dc, + tc_lbist_en_dc => tc_ac_lbist_en_dc, + + lcb_d_mode_dc => lcb_d_mode_dc, + lcb_clkoff_dc_b => lcb_clkoff_dc_b, + lcb_act_dis_dc => lcb_act_dis_dc, + lcb_mpw1_dc_b => lcb_mpw1_dc_b, + lcb_mpw2_dc_b => lcb_mpw2_dc_b, + lcb_delay_lclkr_dc => lcb_delay_lclkr_dc, + + ac_func_scan_in(0) => func_scan_in_int(4), + ac_func_scan_in(1) => func_scan_in_int(5), + ac_func_scan_in(2) => siv_1(tlb_cmp2_offset), + ac_func_scan_out(0) => func_scan_out_int(4), + ac_func_scan_out(1) => func_scan_out_int(5), + ac_func_scan_out(2) => sov_1(tlb_cmp2_offset), + + pc_sg_2 => pc_sg_2(1), + pc_func_sl_thold_2 => pc_func_sl_thold_2(1), + pc_func_slp_sl_thold_2 => pc_func_slp_sl_thold_2(1), + pc_func_slp_nsl_thold_2 => pc_func_slp_nsl_thold_2, + pc_fce_2 => pc_fce_2, + xu_mm_ccr2_notlb_b => xu_mm_ccr2_notlb_b(5), + xu_mm_spr_epcr_dmiuh => xu_mm_spr_epcr_dmiuh, + xu_mm_epcr_dgtmi => xu_mm_epcr_dgtmi_sig, + xu_mm_msr_gs => xu_mm_msr_gs, + xu_mm_msr_pr => xu_mm_msr_pr, + xu_mm_xucr4_mmu_mchk_q => xu_mm_xucr4_mmu_mchk_q, + lpidr => lpidr_sig, + mmucr1 => mmucr1_sig(10 to 18), + mmucr3_0 => mmucr3_0_sig, + mmucr3_1 => mmucr3_1_sig, + mmucr3_2 => mmucr3_2_sig, + mmucr3_3 => mmucr3_3_sig, + mm_iu_ierat_rel_val => mm_iu_ierat_rel_val_sig, + mm_iu_ierat_rel_data => mm_iu_ierat_rel_data_sig, + + mm_xu_derat_rel_val => mm_xu_derat_rel_val_sig, + mm_xu_derat_rel_data => mm_xu_derat_rel_data_sig, + tlb_cmp_ierat_dup_val => tlb_cmp_ierat_dup_val_sig, + tlb_cmp_derat_dup_val => tlb_cmp_derat_dup_val_sig, + tlb_cmp_erat_dup_wait => tlb_cmp_erat_dup_wait_sig, + ierat_req0_pid => ierat_req0_pid_sig, + ierat_req0_as => ierat_req0_as_sig, + ierat_req0_gs => ierat_req0_gs_sig, + ierat_req0_epn => ierat_req0_epn_sig, + ierat_req0_thdid => ierat_req0_thdid_sig, + ierat_req0_valid => ierat_req0_valid_sig, + ierat_req0_nonspec => ierat_req0_nonspec_sig, + ierat_req1_pid => ierat_req1_pid_sig, + ierat_req1_as => ierat_req1_as_sig, + ierat_req1_gs => ierat_req1_gs_sig, + ierat_req1_epn => ierat_req1_epn_sig, + ierat_req1_thdid => ierat_req1_thdid_sig, + ierat_req1_valid => ierat_req1_valid_sig, + ierat_req1_nonspec => ierat_req1_nonspec_sig, + ierat_req2_pid => ierat_req2_pid_sig, + ierat_req2_as => ierat_req2_as_sig, + ierat_req2_gs => ierat_req2_gs_sig, + ierat_req2_epn => ierat_req2_epn_sig, + ierat_req2_thdid => ierat_req2_thdid_sig, + ierat_req2_valid => ierat_req2_valid_sig, + ierat_req2_nonspec => ierat_req2_nonspec_sig, + ierat_req3_pid => ierat_req3_pid_sig, + ierat_req3_as => ierat_req3_as_sig, + ierat_req3_gs => ierat_req3_gs_sig, + ierat_req3_epn => ierat_req3_epn_sig, + ierat_req3_thdid => ierat_req3_thdid_sig, + ierat_req3_valid => ierat_req3_valid_sig, + ierat_req3_nonspec => ierat_req3_nonspec_sig, + ierat_iu4_pid => ierat_iu4_pid_sig, + ierat_iu4_gs => ierat_iu4_gs_sig, + ierat_iu4_as => ierat_iu4_as_sig, + ierat_iu4_epn => ierat_iu4_epn_sig, + ierat_iu4_thdid => ierat_iu4_thdid_sig, + ierat_iu4_valid => ierat_iu4_valid_sig, + + derat_req0_lpid => derat_req0_lpid_sig, + derat_req0_pid => derat_req0_pid_sig, + derat_req0_as => derat_req0_as_sig, + derat_req0_gs => derat_req0_gs_sig, + derat_req0_epn => derat_req0_epn_sig, + derat_req0_thdid => derat_req0_thdid_sig, + derat_req0_valid => derat_req0_valid_sig, + derat_req1_lpid => derat_req1_lpid_sig, + derat_req1_pid => derat_req1_pid_sig, + derat_req1_as => derat_req1_as_sig, + derat_req1_gs => derat_req1_gs_sig, + derat_req1_epn => derat_req1_epn_sig, + derat_req1_thdid => derat_req1_thdid_sig, + derat_req1_valid => derat_req1_valid_sig, + derat_req2_lpid => derat_req2_lpid_sig, + derat_req2_pid => derat_req2_pid_sig, + derat_req2_as => derat_req2_as_sig, + derat_req2_gs => derat_req2_gs_sig, + derat_req2_epn => derat_req2_epn_sig, + derat_req2_thdid => derat_req2_thdid_sig, + derat_req2_valid => derat_req2_valid_sig, + derat_req3_lpid => derat_req3_lpid_sig, + derat_req3_pid => derat_req3_pid_sig, + derat_req3_as => derat_req3_as_sig, + derat_req3_gs => derat_req3_gs_sig, + derat_req3_epn => derat_req3_epn_sig, + derat_req3_thdid => derat_req3_thdid_sig, + derat_req3_valid => derat_req3_valid_sig, + derat_ex5_lpid => derat_ex5_lpid_sig, + derat_ex5_pid => derat_ex5_pid_sig, + derat_ex5_gs => derat_ex5_gs_sig, + derat_ex5_as => derat_ex5_as_sig, + derat_ex5_epn => derat_ex5_epn_sig, + derat_ex5_thdid => derat_ex5_thdid_sig, + derat_ex5_valid => derat_ex5_valid_sig, + + tlb_tag2 => tlb_tag2_sig, + tlb_addr2 => tlb_addr2_sig, + ex6_illeg_instr => ex6_illeg_instr, + + ierat_req_taken => ierat_req_taken, + derat_req_taken => derat_req_taken, + ptereload_req_taken => ptereload_req_taken, + tlb_tag0_type => tlb_tag0_type(0 to 1), + + lru_dataout => lru_dataout(0 to 15), + tlb_dataout => tlb_dataout, + tlb_dataina => tlb_dataina, + tlb_datainb => tlb_datainb, + lru_write => lru_write(0 to 15), + lru_wr_addr => lru_wr_addr, + lru_datain => lru_datain(0 to 15), + lru_tag4_dataout => lru_tag4_dataout, + tlb_tag4_esel => tlb_tag4_esel, + tlb_tag4_wq => tlb_tag4_wq, + tlb_tag4_is => tlb_tag4_is, + tlb_tag4_gs => tlb_tag4_gs, + tlb_tag4_pr => tlb_tag4_pr, + tlb_tag4_hes => tlb_tag4_hes, + tlb_tag4_atsel => tlb_tag4_atsel, + tlb_tag4_pt => tlb_tag4_pt, + tlb_tag4_cmp_hit => tlb_tag4_cmp_hit, + tlb_tag4_way_ind => tlb_tag4_way_ind, + tlb_tag4_ptereload => tlb_tag4_ptereload, + tlb_tag4_endflag => tlb_tag4_endflag, + tlb_tag4_parerr => tlb_tag4_parerr, + tlb_tag5_except => tlb_tag5_except, + + mmucfg_twc => mmucfg_twc, + mmucfg_lrat => mmucfg_lrat, + tlb0cfg_pt => tlb0cfg_pt, + tlb0cfg_gtwe => tlb0cfg_gtwe, + tlb0cfg_ind => tlb0cfg_ind, + + mas2_0_wimge => mas2_0_wimge, + mas3_0_rpnl => mas3_0_rpnl, + mas3_0_ubits => mas3_0_ubits, + mas3_0_usxwr => mas3_0_usxwr, + mas7_0_rpnu => mas7_0_rpnu, + mas8_0_vf => mas8_0_vf, + mas2_1_wimge => mas2_1_wimge, + mas3_1_rpnl => mas3_1_rpnl, + mas3_1_ubits => mas3_1_ubits, + mas3_1_usxwr => mas3_1_usxwr, + mas7_1_rpnu => mas7_1_rpnu, + mas8_1_vf => mas8_1_vf, + mas2_2_wimge => mas2_2_wimge, + mas3_2_rpnl => mas3_2_rpnl, + mas3_2_ubits => mas3_2_ubits, + mas3_2_usxwr => mas3_2_usxwr, + mas7_2_rpnu => mas7_2_rpnu, + mas8_2_vf => mas8_2_vf, + mas2_3_wimge => mas2_3_wimge, + mas3_3_rpnl => mas3_3_rpnl, + mas3_3_ubits => mas3_3_ubits, + mas3_3_usxwr => mas3_3_usxwr, + mas7_3_rpnu => mas7_3_rpnu, + mas8_3_vf => mas8_3_vf, + + tlb_mas0_esel => tlb_mas0_esel, + tlb_mas1_v => tlb_mas1_v, + tlb_mas1_iprot => tlb_mas1_iprot, + tlb_mas1_tid => tlb_mas1_tid, + tlb_mas1_tid_error => tlb_mas1_tid_error, + tlb_mas1_ind => tlb_mas1_ind, + tlb_mas1_ts => tlb_mas1_ts, + tlb_mas1_ts_error => tlb_mas1_ts_error, + tlb_mas1_tsize => tlb_mas1_tsize, + tlb_mas2_epn => tlb_mas2_epn, + tlb_mas2_epn_error => tlb_mas2_epn_error, + tlb_mas2_wimge => tlb_mas2_wimge, + tlb_mas3_rpnl => tlb_mas3_rpnl, + tlb_mas3_ubits => tlb_mas3_ubits, + tlb_mas3_usxwr => tlb_mas3_usxwr, + tlb_mas6_spid => tlb_mas6_spid, + tlb_mas6_isize => tlb_mas6_isize, + tlb_mas6_sind => tlb_mas6_sind, + tlb_mas6_sas => tlb_mas6_sas, + tlb_mas7_rpnu => tlb_mas7_rpnu, + tlb_mas8_tgs => tlb_mas8_tgs, + tlb_mas8_vf => tlb_mas8_vf, + tlb_mas8_tlpid => tlb_mas8_tlpid, + + tlb_mmucr1_een => tlb_mmucr1_een, + tlb_mmucr1_we => tlb_mmucr1_we, + tlb_mmucr3_thdid => tlb_mmucr3_thdid, + tlb_mmucr3_resvattr => tlb_mmucr3_resvattr, + tlb_mmucr3_wlc => tlb_mmucr3_wlc, + tlb_mmucr3_class => tlb_mmucr3_class, + tlb_mmucr3_extclass => tlb_mmucr3_extclass, + tlb_mmucr3_rc => tlb_mmucr3_rc, + tlb_mmucr3_x => tlb_mmucr3_x, + tlb_mas_tlbre => tlb_mas_tlbre, + tlb_mas_tlbsx_hit => tlb_mas_tlbsx_hit, + tlb_mas_tlbsx_miss => tlb_mas_tlbsx_miss, + tlb_mas_dtlb_error => tlb_mas_dtlb_error, + tlb_mas_itlb_error => tlb_mas_itlb_error, + tlb_mas_thdid => tlb_mas_thdid, + lrat_tag3_lpn => lrat_tag3_lpn, + lrat_tag3_rpn => lrat_tag3_rpn, + lrat_tag3_hit_status => lrat_tag3_hit_status, + lrat_tag3_hit_entry => lrat_tag3_hit_entry, + lrat_tag4_lpn => lrat_tag4_lpn, + lrat_tag4_rpn => lrat_tag4_rpn, + lrat_tag4_hit_status => lrat_tag4_hit_status, + lrat_tag4_hit_entry => lrat_tag4_hit_entry, + + tlb_htw_req_valid => tlb_htw_req_valid, + tlb_htw_req_tag => tlb_htw_req_tag, + tlb_htw_req_way => tlb_htw_req_way, + + tlbwe_back_inv_valid => tlbwe_back_inv_valid_sig, + tlbwe_back_inv_thdid => tlbwe_back_inv_thdid_sig, + tlbwe_back_inv_addr => tlbwe_back_inv_addr_sig, + tlbwe_back_inv_attr => tlbwe_back_inv_attr_sig, + + ptereload_req_pte_lat => ptereload_req_pte_lat, + + tlb_ctl_tag2_flush => tlb_ctl_tag2_flush_sig, + tlb_ctl_tag3_flush => tlb_ctl_tag3_flush_sig, + tlb_ctl_tag4_flush => tlb_ctl_tag4_flush_sig, + tlb_resv_match_vec => tlb_resv_match_vec_sig, + + mm_xu_eratmiss_done => mm_xu_eratmiss_done_sig, + mm_xu_tlb_miss => mm_xu_tlb_miss_sig, + mm_xu_tlb_inelig => mm_xu_tlb_inelig_sig, + + mm_xu_lrat_miss => mm_xu_lrat_miss_sig, + mm_xu_pt_fault => mm_xu_pt_fault_sig, + mm_xu_hv_priv => mm_xu_hv_priv_sig, + + mm_xu_esr_pt => mm_xu_esr_pt_sig, + mm_xu_esr_data => mm_xu_esr_data_sig, + mm_xu_esr_epid => mm_xu_esr_epid_sig, + mm_xu_esr_st => mm_xu_esr_st_sig, + + mm_xu_cr0_eq => mm_xu_cr0_eq_sig, + mm_xu_cr0_eq_valid => mm_xu_cr0_eq_valid_sig, + + mm_xu_tlb_multihit_err => mm_xu_tlb_multihit_err, + mm_xu_tlb_par_err => mm_xu_tlb_par_err, + mm_xu_lru_par_err => mm_xu_lru_par_err, + + tlb_delayed_act => tlb_delayed_act(9 to 16), + + tlb_cmp_perf_event_t0 => tlb_cmp_perf_event_t0, + tlb_cmp_perf_event_t1 => tlb_cmp_perf_event_t1, + tlb_cmp_perf_event_t2 => tlb_cmp_perf_event_t2, + tlb_cmp_perf_event_t3 => tlb_cmp_perf_event_t3, + tlb_cmp_perf_state => tlb_cmp_perf_state, + + tlb_cmp_perf_miss_direct => tlb_cmp_perf_miss_direct, + tlb_cmp_perf_hit_indirect => tlb_cmp_perf_hit_indirect, + tlb_cmp_perf_hit_first_page => tlb_cmp_perf_hit_first_page, + tlb_cmp_perf_ptereload_noexcep => tlb_cmp_perf_ptereload_noexcep, + tlb_cmp_perf_lrat_request => tlb_cmp_perf_lrat_request, + tlb_cmp_perf_lrat_miss => tlb_cmp_perf_lrat_miss, + tlb_cmp_perf_pt_fault => tlb_cmp_perf_pt_fault, + tlb_cmp_perf_pt_inelig => tlb_cmp_perf_pt_inelig, + + tlb_cmp_dbg_tag4 => tlb_cmp_dbg_tag4, + tlb_cmp_dbg_tag4_wayhit => tlb_cmp_dbg_tag4_wayhit, + tlb_cmp_dbg_addr4 => tlb_cmp_dbg_addr4, + tlb_cmp_dbg_tag4_way => tlb_cmp_dbg_tag4_way, + tlb_cmp_dbg_tag4_parerr => tlb_cmp_dbg_tag4_parerr, + tlb_cmp_dbg_tag4_lru_dataout_q => tlb_cmp_dbg_tag4_lru_dataout_q, + tlb_cmp_dbg_tag5_tlb_datain_q => tlb_cmp_dbg_tag5_tlb_datain_q, + tlb_cmp_dbg_tag5_lru_datain_q => tlb_cmp_dbg_tag5_lru_datain_q, + tlb_cmp_dbg_tag5_lru_write => tlb_cmp_dbg_tag5_lru_write, + tlb_cmp_dbg_tag5_any_exception => tlb_cmp_dbg_tag5_any_exception, + tlb_cmp_dbg_tag5_except_type_q => tlb_cmp_dbg_tag5_except_type_q, + tlb_cmp_dbg_tag5_except_thdid_q => tlb_cmp_dbg_tag5_except_thdid_q, + tlb_cmp_dbg_tag5_erat_rel_val => tlb_cmp_dbg_tag5_erat_rel_val, + tlb_cmp_dbg_tag5_erat_rel_data => tlb_cmp_dbg_tag5_erat_rel_data, + tlb_cmp_dbg_erat_dup_q => tlb_cmp_dbg_erat_dup_q, + tlb_cmp_dbg_addr_enable => tlb_cmp_dbg_addr_enable, + tlb_cmp_dbg_pgsize_enable => tlb_cmp_dbg_pgsize_enable, + tlb_cmp_dbg_class_enable => tlb_cmp_dbg_class_enable, + tlb_cmp_dbg_extclass_enable => tlb_cmp_dbg_extclass_enable, + tlb_cmp_dbg_state_enable => tlb_cmp_dbg_state_enable, + tlb_cmp_dbg_thdid_enable => tlb_cmp_dbg_thdid_enable, + tlb_cmp_dbg_pid_enable => tlb_cmp_dbg_pid_enable, + tlb_cmp_dbg_lpid_enable => tlb_cmp_dbg_lpid_enable, + tlb_cmp_dbg_ind_enable => tlb_cmp_dbg_ind_enable, + tlb_cmp_dbg_iprot_enable => tlb_cmp_dbg_iprot_enable, + tlb_cmp_dbg_way0_entry_v => tlb_cmp_dbg_way0_entry_v, + tlb_cmp_dbg_way0_addr_match => tlb_cmp_dbg_way0_addr_match, + tlb_cmp_dbg_way0_pgsize_match => tlb_cmp_dbg_way0_pgsize_match, + tlb_cmp_dbg_way0_class_match => tlb_cmp_dbg_way0_class_match, + tlb_cmp_dbg_way0_extclass_match => tlb_cmp_dbg_way0_extclass_match, + tlb_cmp_dbg_way0_state_match => tlb_cmp_dbg_way0_state_match, + tlb_cmp_dbg_way0_thdid_match => tlb_cmp_dbg_way0_thdid_match, + tlb_cmp_dbg_way0_pid_match => tlb_cmp_dbg_way0_pid_match, + tlb_cmp_dbg_way0_lpid_match => tlb_cmp_dbg_way0_lpid_match, + tlb_cmp_dbg_way0_ind_match => tlb_cmp_dbg_way0_ind_match, + tlb_cmp_dbg_way0_iprot_match => tlb_cmp_dbg_way0_iprot_match, + tlb_cmp_dbg_way1_entry_v => tlb_cmp_dbg_way1_entry_v, + tlb_cmp_dbg_way1_addr_match => tlb_cmp_dbg_way1_addr_match, + tlb_cmp_dbg_way1_pgsize_match => tlb_cmp_dbg_way1_pgsize_match, + tlb_cmp_dbg_way1_class_match => tlb_cmp_dbg_way1_class_match, + tlb_cmp_dbg_way1_extclass_match => tlb_cmp_dbg_way1_extclass_match, + tlb_cmp_dbg_way1_state_match => tlb_cmp_dbg_way1_state_match, + tlb_cmp_dbg_way1_thdid_match => tlb_cmp_dbg_way1_thdid_match, + tlb_cmp_dbg_way1_pid_match => tlb_cmp_dbg_way1_pid_match, + tlb_cmp_dbg_way1_lpid_match => tlb_cmp_dbg_way1_lpid_match, + tlb_cmp_dbg_way1_ind_match => tlb_cmp_dbg_way1_ind_match, + tlb_cmp_dbg_way1_iprot_match => tlb_cmp_dbg_way1_iprot_match, + tlb_cmp_dbg_way2_entry_v => tlb_cmp_dbg_way2_entry_v, + tlb_cmp_dbg_way2_addr_match => tlb_cmp_dbg_way2_addr_match, + tlb_cmp_dbg_way2_pgsize_match => tlb_cmp_dbg_way2_pgsize_match, + tlb_cmp_dbg_way2_class_match => tlb_cmp_dbg_way2_class_match, + tlb_cmp_dbg_way2_extclass_match => tlb_cmp_dbg_way2_extclass_match, + tlb_cmp_dbg_way2_state_match => tlb_cmp_dbg_way2_state_match, + tlb_cmp_dbg_way2_thdid_match => tlb_cmp_dbg_way2_thdid_match, + tlb_cmp_dbg_way2_pid_match => tlb_cmp_dbg_way2_pid_match, + tlb_cmp_dbg_way2_lpid_match => tlb_cmp_dbg_way2_lpid_match, + tlb_cmp_dbg_way2_ind_match => tlb_cmp_dbg_way2_ind_match, + tlb_cmp_dbg_way2_iprot_match => tlb_cmp_dbg_way2_iprot_match, + tlb_cmp_dbg_way3_entry_v => tlb_cmp_dbg_way3_entry_v, + tlb_cmp_dbg_way3_addr_match => tlb_cmp_dbg_way3_addr_match, + tlb_cmp_dbg_way3_pgsize_match => tlb_cmp_dbg_way3_pgsize_match, + tlb_cmp_dbg_way3_class_match => tlb_cmp_dbg_way3_class_match, + tlb_cmp_dbg_way3_extclass_match => tlb_cmp_dbg_way3_extclass_match, + tlb_cmp_dbg_way3_state_match => tlb_cmp_dbg_way3_state_match, + tlb_cmp_dbg_way3_thdid_match => tlb_cmp_dbg_way3_thdid_match, + tlb_cmp_dbg_way3_pid_match => tlb_cmp_dbg_way3_pid_match, + tlb_cmp_dbg_way3_lpid_match => tlb_cmp_dbg_way3_lpid_match, + tlb_cmp_dbg_way3_ind_match => tlb_cmp_dbg_way3_ind_match, + tlb_cmp_dbg_way3_iprot_match => tlb_cmp_dbg_way3_iprot_match + +); +mmq_tlb_lrat: entity work.mmq_tlb_lrat(mmq_tlb_lrat) + generic map ( epn_width => epn_width, + spr_data_width => spr_data_width, + real_addr_width => real_addr_width, + rpn_width => rpn_width, + lpid_width => lpid_width, + expand_type => expand_type ) + port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + tc_ccflush_dc => tc_ac_ccflush_dc, + tc_scan_dis_dc_b => tc_ac_scan_dis_dc_b, + tc_scan_diag_dc => tc_ac_scan_diag_dc, + tc_lbist_en_dc => tc_ac_lbist_en_dc, + + lcb_d_mode_dc => lcb_d_mode_dc, + lcb_clkoff_dc_b => lcb_clkoff_dc_b, + lcb_act_dis_dc => lcb_act_dis_dc, + lcb_mpw1_dc_b => lcb_mpw1_dc_b, + lcb_mpw2_dc_b => lcb_mpw2_dc_b, + lcb_delay_lclkr_dc => lcb_delay_lclkr_dc, + + ac_func_scan_in => func_scan_in_int(6), + ac_func_scan_out => func_scan_out_int(6), + + pc_sg_2 => pc_sg_2(1), + pc_func_sl_thold_2 => pc_func_sl_thold_2(1), + pc_func_slp_sl_thold_2 => pc_func_slp_sl_thold_2(1), + + xu_mm_ccr2_notlb_b => xu_mm_ccr2_notlb_b(6), + tlb_delayed_act => tlb_delayed_act(20 to 23), + mmucr2_act_override => mmucr2_sig(3), + + tlb_ctl_ex3_valid => tlb_ctl_ex3_valid_sig, + tlb_ctl_ex3_ttype => tlb_ctl_ex3_ttype_sig, + xu_ex3_flush => xu_ex3_flush, + xu_ex4_flush => xu_ex4_flush, + xu_ex5_flush => xu_ex5_flush, + tlb_tag0_epn => tlb_tag0_epn(64-real_addr_width to 51), + tlb_tag0_thdid => tlb_tag0_thdid, + tlb_tag0_type => tlb_tag0_type, + tlb_tag0_lpid => tlb_tag0_lpid, + tlb_tag0_atsel => tlb_tag0_atsel, + tlb_tag0_size => tlb_tag0_size, + tlb_tag0_addr_cap => tlb_tag0_addr_cap, + ex6_illeg_instr => ex6_illeg_instr, + + pte_tag0_lpn => pte_tag0_lpn(64-real_addr_width to 51), + pte_tag0_lpid => pte_tag0_lpid, + mas0_0_atsel => mas0_0_atsel, + mas0_0_esel => mas0_0_esel, + mas0_0_hes => mas0_0_hes, + mas0_0_wq => mas0_0_wq, + mas1_0_v => mas1_0_v, + mas1_0_tsize => mas1_0_tsize, + mas2_0_epn => mas2_0_epn(64-real_addr_width to 51), + mas7_0_rpnu => mas7_0_rpnu, + mas3_0_rpnl => mas3_0_rpnl(32 to 51), + mas8_0_tlpid => mas8_0_tlpid, + mmucr3_0_x => mmucr3_0_sig(49), + mas0_1_atsel => mas0_1_atsel, + mas0_1_esel => mas0_1_esel, + mas0_1_hes => mas0_1_hes, + mas0_1_wq => mas0_1_wq, + mas1_1_v => mas1_1_v, + mas1_1_tsize => mas1_1_tsize, + mas2_1_epn => mas2_1_epn(64-real_addr_width to 51), + mas7_1_rpnu => mas7_1_rpnu, + mas3_1_rpnl => mas3_1_rpnl(32 to 51), + mas8_1_tlpid => mas8_1_tlpid, + mmucr3_1_x => mmucr3_1_sig(49), + mas0_2_atsel => mas0_2_atsel, + mas0_2_esel => mas0_2_esel, + mas0_2_hes => mas0_2_hes, + mas0_2_wq => mas0_2_wq, + mas1_2_v => mas1_2_v, + mas1_2_tsize => mas1_2_tsize, + mas2_2_epn => mas2_2_epn(64-real_addr_width to 51), + mas7_2_rpnu => mas7_2_rpnu, + mas3_2_rpnl => mas3_2_rpnl(32 to 51), + mas8_2_tlpid => mas8_2_tlpid, + mmucr3_2_x => mmucr3_2_sig(49), + mas0_3_atsel => mas0_3_atsel, + mas0_3_esel => mas0_3_esel, + mas0_3_hes => mas0_3_hes, + mas0_3_wq => mas0_3_wq, + mas1_3_v => mas1_3_v, + mas1_3_tsize => mas1_3_tsize, + mas2_3_epn => mas2_3_epn(64-real_addr_width to 51), + mas7_3_rpnu => mas7_3_rpnu, + mas3_3_rpnl => mas3_3_rpnl(32 to 51), + mas8_3_tlpid => mas8_3_tlpid, + mmucr3_3_x => mmucr3_3_sig(49), + + lrat_mmucr3_x => lrat_mmucr3_x, + lrat_mas0_esel => lrat_mas0_esel, + lrat_mas1_v => lrat_mas1_v, + lrat_mas1_tsize => lrat_mas1_tsize, + lrat_mas2_epn => lrat_mas2_epn, + lrat_mas3_rpnl => lrat_mas3_rpnl, + lrat_mas7_rpnu => lrat_mas7_rpnu, + lrat_mas8_tlpid => lrat_mas8_tlpid, + lrat_mas_tlbre => lrat_mas_tlbre, + lrat_mas_tlbsx_hit => lrat_mas_tlbsx_hit, + lrat_mas_tlbsx_miss => lrat_mas_tlbsx_miss, + lrat_mas_thdid => lrat_mas_thdid, + + lrat_tag3_lpn => lrat_tag3_lpn, + lrat_tag3_rpn => lrat_tag3_rpn, + lrat_tag3_hit_status => lrat_tag3_hit_status, + lrat_tag3_hit_entry => lrat_tag3_hit_entry, + lrat_tag4_lpn => lrat_tag4_lpn, + lrat_tag4_rpn => lrat_tag4_rpn, + lrat_tag4_hit_status => lrat_tag4_hit_status, + lrat_tag4_hit_entry => lrat_tag4_hit_entry, + + lrat_dbg_tag1_addr_enable => lrat_dbg_tag1_addr_enable, + lrat_dbg_tag2_matchline_q => lrat_dbg_tag2_matchline_q, + lrat_dbg_entry0_addr_match => lrat_dbg_entry0_addr_match, + lrat_dbg_entry0_lpid_match => lrat_dbg_entry0_lpid_match, + lrat_dbg_entry0_entry_v => lrat_dbg_entry0_entry_v, + lrat_dbg_entry0_entry_x => lrat_dbg_entry0_entry_x, + lrat_dbg_entry0_size => lrat_dbg_entry0_size, + lrat_dbg_entry1_addr_match => lrat_dbg_entry1_addr_match, + lrat_dbg_entry1_lpid_match => lrat_dbg_entry1_lpid_match, + lrat_dbg_entry1_entry_v => lrat_dbg_entry1_entry_v, + lrat_dbg_entry1_entry_x => lrat_dbg_entry1_entry_x, + lrat_dbg_entry1_size => lrat_dbg_entry1_size, + lrat_dbg_entry2_addr_match => lrat_dbg_entry2_addr_match, + lrat_dbg_entry2_lpid_match => lrat_dbg_entry2_lpid_match, + lrat_dbg_entry2_entry_v => lrat_dbg_entry2_entry_v, + lrat_dbg_entry2_entry_x => lrat_dbg_entry2_entry_x, + lrat_dbg_entry2_size => lrat_dbg_entry2_size, + lrat_dbg_entry3_addr_match => lrat_dbg_entry3_addr_match, + lrat_dbg_entry3_lpid_match => lrat_dbg_entry3_lpid_match, + lrat_dbg_entry3_entry_v => lrat_dbg_entry3_entry_v, + lrat_dbg_entry3_entry_x => lrat_dbg_entry3_entry_x, + lrat_dbg_entry3_size => lrat_dbg_entry3_size, + lrat_dbg_entry4_addr_match => lrat_dbg_entry4_addr_match, + lrat_dbg_entry4_lpid_match => lrat_dbg_entry4_lpid_match, + lrat_dbg_entry4_entry_v => lrat_dbg_entry4_entry_v, + lrat_dbg_entry4_entry_x => lrat_dbg_entry4_entry_x, + lrat_dbg_entry4_size => lrat_dbg_entry4_size, + lrat_dbg_entry5_addr_match => lrat_dbg_entry5_addr_match, + lrat_dbg_entry5_lpid_match => lrat_dbg_entry5_lpid_match, + lrat_dbg_entry5_entry_v => lrat_dbg_entry5_entry_v, + lrat_dbg_entry5_entry_x => lrat_dbg_entry5_entry_x, + lrat_dbg_entry5_size => lrat_dbg_entry5_size, + lrat_dbg_entry6_addr_match => lrat_dbg_entry6_addr_match, + lrat_dbg_entry6_lpid_match => lrat_dbg_entry6_lpid_match, + lrat_dbg_entry6_entry_v => lrat_dbg_entry6_entry_v, + lrat_dbg_entry6_entry_x => lrat_dbg_entry6_entry_x, + lrat_dbg_entry6_size => lrat_dbg_entry6_size, + lrat_dbg_entry7_addr_match => lrat_dbg_entry7_addr_match, + lrat_dbg_entry7_lpid_match => lrat_dbg_entry7_lpid_match, + lrat_dbg_entry7_entry_v => lrat_dbg_entry7_entry_v, + lrat_dbg_entry7_entry_x => lrat_dbg_entry7_entry_x, + lrat_dbg_entry7_size => lrat_dbg_entry7_size +); +mmq_htw: entity work.mmq_htw(mmq_htw) + generic map ( thdid_width => thdid_width, + pid_width => pid_width, + lpid_width => lpid_width, + epn_width => epn_width, + real_addr_width => real_addr_width, + rpn_width => rpn_width, + tlb_way_width => tlb_way_width, + tlb_word_width => tlb_word_width, + tlb_tag_width => tlb_tag_width, + pte_width => pte_width, + expand_type => expand_type ) + port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + tc_ccflush_dc => tc_ac_ccflush_dc, + tc_scan_dis_dc_b => tc_ac_scan_dis_dc_b, + tc_scan_diag_dc => tc_ac_scan_diag_dc, + tc_lbist_en_dc => tc_ac_lbist_en_dc, + + lcb_d_mode_dc => lcb_d_mode_dc, + lcb_clkoff_dc_b => lcb_clkoff_dc_b, + lcb_act_dis_dc => lcb_act_dis_dc, + lcb_mpw1_dc_b => lcb_mpw1_dc_b, + lcb_mpw2_dc_b => lcb_mpw2_dc_b, + lcb_delay_lclkr_dc => lcb_delay_lclkr_dc, + + ac_func_scan_in(0 to 1) => func_scan_in_int(7 to 8), + ac_func_scan_out(0 to 1) => func_scan_out_int(7 to 8), + + pc_sg_2 => pc_sg_2(1), + pc_func_sl_thold_2 => pc_func_sl_thold_2(1), + pc_func_slp_sl_thold_2 => pc_func_slp_sl_thold_2(1), + + xu_mm_ccr2_notlb_b => xu_mm_ccr2_notlb_b(7), + + tlb_delayed_act => tlb_delayed_act(24 to 28), + mmucr2_act_override => mmucr2_sig(4), + + tlb_ctl_tag2_flush => tlb_ctl_tag2_flush_sig, + tlb_ctl_tag3_flush => tlb_ctl_tag3_flush_sig, + tlb_ctl_tag4_flush => tlb_ctl_tag4_flush_sig, + + tlb_tag2 => tlb_tag2_sig, + tlb_tag5_except => tlb_tag5_except, + + tlb_htw_req_valid => tlb_htw_req_valid, + tlb_htw_req_tag => tlb_htw_req_tag, + tlb_htw_req_way => tlb_htw_req_way, + htw_lsu_req_valid => htw_lsu_req_valid, + htw_lsu_thdid => htw_lsu_thdid, + htw_dbg_lsu_thdid => htw_dbg_lsu_thdid, + htw_lsu_ttype => htw_lsu_ttype, + htw_lsu_wimge => htw_lsu_wimge, + htw_lsu_u => htw_lsu_u, + htw_lsu_addr => htw_lsu_addr, + htw_lsu_req_taken => htw_lsu_req_taken, + htw_quiesce => htw_quiesce_sig, + + htw_req0_valid => htw_req0_valid, + htw_req0_thdid => htw_req0_thdid, + htw_req0_type => htw_req0_type, + htw_req1_valid => htw_req1_valid, + htw_req1_thdid => htw_req1_thdid, + htw_req1_type => htw_req1_type, + htw_req2_valid => htw_req2_valid, + htw_req2_thdid => htw_req2_thdid, + htw_req2_type => htw_req2_type, + htw_req3_valid => htw_req3_valid, + htw_req3_thdid => htw_req3_thdid, + htw_req3_type => htw_req3_type, + ptereload_req_valid => ptereload_req_valid, + ptereload_req_tag => ptereload_req_tag, + ptereload_req_pte => ptereload_req_pte, + ptereload_req_taken => ptereload_req_taken, + an_ac_reld_core_tag => an_ac_reld_core_tag, + an_ac_reld_data => an_ac_reld_data, + an_ac_reld_data_vld => an_ac_reld_data_vld, + an_ac_reld_ecc_err => an_ac_reld_ecc_err, + an_ac_reld_ecc_err_ue => an_ac_reld_ecc_err_ue, + an_ac_reld_qw => an_ac_reld_qw(58 to 59), + an_ac_reld_ditc => an_ac_reld_ditc, + an_ac_reld_crit_qw => an_ac_reld_crit_qw, + + htw_dbg_seq_idle => htw_dbg_seq_idle, + htw_dbg_pte0_seq_idle => htw_dbg_pte0_seq_idle, + htw_dbg_pte1_seq_idle => htw_dbg_pte1_seq_idle, + htw_dbg_seq_q => htw_dbg_seq_q, + htw_dbg_inptr_q => htw_dbg_inptr_q, + htw_dbg_pte0_seq_q => htw_dbg_pte0_seq_q, + htw_dbg_pte1_seq_q => htw_dbg_pte1_seq_q, + htw_dbg_ptereload_ptr_q => htw_dbg_ptereload_ptr_q, + htw_dbg_lsuptr_q => htw_dbg_lsuptr_q, + htw_dbg_req_valid_q => htw_dbg_req_valid_q, + htw_dbg_resv_valid_vec => htw_dbg_resv_valid_vec, + htw_dbg_tag4_clr_resv_q => htw_dbg_tag4_clr_resv_q, + htw_dbg_tag4_clr_resv_terms => htw_dbg_tag4_clr_resv_terms, + htw_dbg_pte0_score_ptr_q => htw_dbg_pte0_score_ptr_q, + htw_dbg_pte0_score_cl_offset_q => htw_dbg_pte0_score_cl_offset_q, + htw_dbg_pte0_score_error_q => htw_dbg_pte0_score_error_q, + htw_dbg_pte0_score_qwbeat_q => htw_dbg_pte0_score_qwbeat_q, + htw_dbg_pte0_score_pending_q => htw_dbg_pte0_score_pending_q, + htw_dbg_pte0_score_ibit_q => htw_dbg_pte0_score_ibit_q, + htw_dbg_pte0_score_dataval_q => htw_dbg_pte0_score_dataval_q, + htw_dbg_pte0_reld_for_me_tm1 => htw_dbg_pte0_reld_for_me_tm1, + htw_dbg_pte1_score_ptr_q => htw_dbg_pte1_score_ptr_q, + htw_dbg_pte1_score_cl_offset_q => htw_dbg_pte1_score_cl_offset_q, + htw_dbg_pte1_score_error_q => htw_dbg_pte1_score_error_q, + htw_dbg_pte1_score_qwbeat_q => htw_dbg_pte1_score_qwbeat_q, + htw_dbg_pte1_score_pending_q => htw_dbg_pte1_score_pending_q, + htw_dbg_pte1_score_ibit_q => htw_dbg_pte1_score_ibit_q, + htw_dbg_pte1_score_dataval_q => htw_dbg_pte1_score_dataval_q, + htw_dbg_pte1_reld_for_me_tm1 => htw_dbg_pte1_reld_for_me_tm1 + + ); +end generate tlb_gen_logic; +tlb_gen_noarrays: if expand_tlb_type = 1 generate +tlb_dataout(0 to tlb_way_width-1) <= tlb_dataina; +tlb_dataout(tlb_way_width to 2*tlb_way_width-1) <= tlb_dataina; +tlb_dataout(2*tlb_way_width to 3*tlb_way_width-1) <= tlb_dataina; +tlb_dataout(3*tlb_way_width to 4*tlb_way_width-1) <= tlb_dataina; +lru_dataout <= lru_datain; +time_scan_int(1 to 5) <= (others => '0'); +repr_scan_int(1 to 5) <= (others => '0'); +abst_scan_int(1 to 6) <= (others => '0'); +end generate tlb_gen_noarrays; +tlb_gen_instance: if expand_tlb_type = 2 generate +tlb_array0: entity tri.tri_128x168_1w_0(tri_128x168_1w_0) + generic map ( expand_type => expand_type ) + port map( + gnd => gnd, + vdd => vdd, + vcs => vcs, + nclk => nclk, + act => tlb_delayed_act(17), + ccflush_dc => tc_ac_ccflush_dc, + scan_dis_dc_b => tc_ac_scan_dis_dc_b, + scan_diag_dc => tc_ac_scan_diag_dc, + repr_scan_in => repr_scan_int(0), + time_scan_in => time_scan_int(0), + abst_scan_in => abst_scan_int(0), + repr_scan_out => repr_scan_int(1), + time_scan_out => time_scan_int(1), + abst_scan_out => abst_scan_int(1), + lcb_d_mode_dc => g6t_gptr_lcb_d_mode_dc, + lcb_clkoff_dc_b => g6t_gptr_lcb_clkoff_dc_b, + lcb_act_dis_dc => g6t_gptr_lcb_act_dis_dc, + lcb_mpw1_dc_b => g6t_gptr_lcb_mpw1_dc_b, + lcb_mpw2_dc_b => g6t_gptr_lcb_mpw2_dc_b, + lcb_delay_lclkr_dc => g6t_gptr_lcb_delay_lclkr_dc, + + tri_lcb_mpw1_dc_b => lcb_mpw1_dc_b(0), + tri_lcb_mpw2_dc_b => lcb_mpw2_dc_b, + tri_lcb_delay_lclkr_dc => lcb_delay_lclkr_dc(0), + tri_lcb_clkoff_dc_b => lcb_clkoff_dc_b, + tri_lcb_act_dis_dc => lcb_act_dis_dc, + + lcb_sg_1 => pc_sg_1(0), + lcb_time_sg_0 => pc_sg_0(0), + lcb_repr_sg_0 => pc_sg_0(0), + lcb_abst_sl_thold_0 => pc_abst_sl_thold_0, + lcb_repr_sl_thold_0 => pc_repr_sl_thold_0, + lcb_time_sl_thold_0 => pc_time_sl_thold_0, + lcb_ary_nsl_thold_0 => pc_ary_slp_nsl_thold_0, + tc_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc, + abist_en_1 => pc_mm_abist_ena_dc, + din_abist => pc_mm_abist_di_g6t_2r_q, + abist_cmp_en => pc_mm_abist_wl128_comp_ena_q, + abist_raw_b_dc => pc_mm_abist_raw_dc_b, + data_cmp_abist => pc_mm_abist_dcomp_g6t_2r_q, + addr_abist => pc_mm_abist_raddr_0_q(3 to 9), + r_wb_abist => pc_mm_abist_g6t_r_wb_q, + lcb_bolt_sl_thold_0 => pc_mm_bolt_sl_thold_0, + pc_bo_enable_2 => pc_mm_bo_enable_2, + pc_bo_reset => pc_mm_bo_reset, + pc_bo_unload => pc_mm_bo_unload, + pc_bo_repair => pc_mm_bo_repair, + pc_bo_shdata => pc_mm_bo_shdata, + pc_bo_select => pc_mm_bo_select(0), + bo_pc_failout => mm_pc_bo_fail(0), + bo_pc_diagloop => mm_pc_bo_diagout(0), + + write_enable => tlb_write(0), + addr => tlb_addr, + data_in => tlb_dataina, + data_out => tlb_dataout(0 to tlb_way_width-1) +); +tlb_array1: entity tri.tri_128x168_1w_0(tri_128x168_1w_0) + generic map ( expand_type => expand_type ) + port map( + gnd => gnd, + vdd => vdd, + vcs => vcs, + nclk => nclk, + act => tlb_delayed_act(17), + + ccflush_dc => tc_ac_ccflush_dc, + scan_dis_dc_b => tc_ac_scan_dis_dc_b, + scan_diag_dc => tc_ac_scan_diag_dc, + repr_scan_in => repr_scan_int(1), + time_scan_in => time_scan_int(1), + abst_scan_in => abst_scan_int(1), + repr_scan_out => repr_scan_int(2), + time_scan_out => time_scan_int(2), + abst_scan_out => abst_scan_int(2), + lcb_d_mode_dc => g6t_gptr_lcb_d_mode_dc, + lcb_clkoff_dc_b => g6t_gptr_lcb_clkoff_dc_b, + lcb_act_dis_dc => g6t_gptr_lcb_act_dis_dc, + lcb_mpw1_dc_b => g6t_gptr_lcb_mpw1_dc_b, + lcb_mpw2_dc_b => g6t_gptr_lcb_mpw2_dc_b, + lcb_delay_lclkr_dc => g6t_gptr_lcb_delay_lclkr_dc, + + tri_lcb_mpw1_dc_b => lcb_mpw1_dc_b(0), + tri_lcb_mpw2_dc_b => lcb_mpw2_dc_b, + tri_lcb_delay_lclkr_dc => lcb_delay_lclkr_dc(0), + tri_lcb_clkoff_dc_b => lcb_clkoff_dc_b, + tri_lcb_act_dis_dc => lcb_act_dis_dc, + + lcb_sg_1 => pc_sg_1(0), + lcb_time_sg_0 => pc_sg_0(0), + lcb_repr_sg_0 => pc_sg_0(0), + lcb_abst_sl_thold_0 => pc_abst_sl_thold_0, + lcb_repr_sl_thold_0 => pc_repr_sl_thold_0, + lcb_time_sl_thold_0 => pc_time_sl_thold_0, + lcb_ary_nsl_thold_0 => pc_ary_slp_nsl_thold_0, + tc_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc, + abist_en_1 => pc_mm_abist_ena_dc, + din_abist => pc_mm_abist_di_g6t_2r_q, + abist_cmp_en => pc_mm_abist_wl128_comp_ena_q, + abist_raw_b_dc => pc_mm_abist_raw_dc_b, + data_cmp_abist => pc_mm_abist_dcomp_g6t_2r_q, + addr_abist => pc_mm_abist_raddr_0_q(3 to 9), + r_wb_abist => pc_mm_abist_g6t_r_wb_q, + lcb_bolt_sl_thold_0 => pc_mm_bolt_sl_thold_0, + pc_bo_enable_2 => pc_mm_bo_enable_2, + pc_bo_reset => pc_mm_bo_reset, + pc_bo_unload => pc_mm_bo_unload, + pc_bo_repair => pc_mm_bo_repair, + pc_bo_shdata => pc_mm_bo_shdata, + pc_bo_select => pc_mm_bo_select(1), + bo_pc_failout => mm_pc_bo_fail(1), + bo_pc_diagloop => mm_pc_bo_diagout(1), + + write_enable => tlb_write(1), + addr => tlb_addr, + data_in => tlb_dataina, + data_out => tlb_dataout(tlb_way_width to 2*tlb_way_width-1) +); +tlb_array2: entity tri.tri_128x168_1w_0(tri_128x168_1w_0) + generic map ( expand_type => expand_type ) + port map( + gnd => gnd, + vdd => vdd, + vcs => vcs, + nclk => nclk, + act => tlb_delayed_act(18), + ccflush_dc => tc_ac_ccflush_dc, + scan_dis_dc_b => tc_ac_scan_dis_dc_b, + scan_diag_dc => tc_ac_scan_diag_dc, + repr_scan_in => repr_scan_int(2), + time_scan_in => time_scan_int(2), + abst_scan_in => abst_scan_int(3), + repr_scan_out => repr_scan_int(3), + time_scan_out => time_scan_int(3), + abst_scan_out => abst_scan_int(4), + lcb_d_mode_dc => g6t_gptr_lcb_d_mode_dc, + lcb_clkoff_dc_b => g6t_gptr_lcb_clkoff_dc_b, + lcb_act_dis_dc => g6t_gptr_lcb_act_dis_dc, + lcb_mpw1_dc_b => g6t_gptr_lcb_mpw1_dc_b, + lcb_mpw2_dc_b => g6t_gptr_lcb_mpw2_dc_b, + lcb_delay_lclkr_dc => g6t_gptr_lcb_delay_lclkr_dc, + + tri_lcb_mpw1_dc_b => lcb_mpw1_dc_b(0), + tri_lcb_mpw2_dc_b => lcb_mpw2_dc_b, + tri_lcb_delay_lclkr_dc => lcb_delay_lclkr_dc(0), + tri_lcb_clkoff_dc_b => lcb_clkoff_dc_b, + tri_lcb_act_dis_dc => lcb_act_dis_dc, + + lcb_sg_1 => pc_sg_1(1), + lcb_time_sg_0 => pc_sg_0(1), + lcb_repr_sg_0 => pc_sg_0(1), + lcb_abst_sl_thold_0 => pc_abst_sl_thold_0, + lcb_repr_sl_thold_0 => pc_repr_sl_thold_0, + lcb_time_sl_thold_0 => pc_time_sl_thold_0, + lcb_ary_nsl_thold_0 => pc_ary_slp_nsl_thold_0, + tc_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc, + abist_en_1 => pc_mm_abist_ena_dc, + din_abist => pc_mm_abist_di_g6t_2r_q, + abist_cmp_en => pc_mm_abist_wl128_comp_ena_q, + abist_raw_b_dc => pc_mm_abist_raw_dc_b, + data_cmp_abist => pc_mm_abist_dcomp_g6t_2r_q, + addr_abist => pc_mm_abist_raddr_0_q(3 to 9), + r_wb_abist => pc_mm_abist_g6t_r_wb_q, + lcb_bolt_sl_thold_0 => pc_mm_bolt_sl_thold_0, + pc_bo_enable_2 => pc_mm_bo_enable_2, + pc_bo_reset => pc_mm_bo_reset, + pc_bo_unload => pc_mm_bo_unload, + pc_bo_repair => pc_mm_bo_repair, + pc_bo_shdata => pc_mm_bo_shdata, + pc_bo_select => pc_mm_bo_select(2), + bo_pc_failout => mm_pc_bo_fail(2), + bo_pc_diagloop => mm_pc_bo_diagout(2), + + write_enable => tlb_write(2), + addr => tlb_addr, + data_in => tlb_datainb, + data_out => tlb_dataout(2*tlb_way_width to 3*tlb_way_width-1) +); +tlb_array3: entity tri.tri_128x168_1w_0(tri_128x168_1w_0) + generic map ( expand_type => expand_type ) + port map( + gnd => gnd, + vdd => vdd, + vcs => vcs, + nclk => nclk, + act => tlb_delayed_act(18), + + ccflush_dc => tc_ac_ccflush_dc, + scan_dis_dc_b => tc_ac_scan_dis_dc_b, + scan_diag_dc => tc_ac_scan_diag_dc, + repr_scan_in => repr_scan_int(3), + time_scan_in => time_scan_int(3), + abst_scan_in => abst_scan_int(4), + repr_scan_out => repr_scan_int(4), + time_scan_out => time_scan_int(4), + abst_scan_out => abst_scan_int(5), + lcb_d_mode_dc => g6t_gptr_lcb_d_mode_dc, + lcb_clkoff_dc_b => g6t_gptr_lcb_clkoff_dc_b, + lcb_act_dis_dc => g6t_gptr_lcb_act_dis_dc, + lcb_mpw1_dc_b => g6t_gptr_lcb_mpw1_dc_b, + lcb_mpw2_dc_b => g6t_gptr_lcb_mpw2_dc_b, + lcb_delay_lclkr_dc => g6t_gptr_lcb_delay_lclkr_dc, + + tri_lcb_mpw1_dc_b => lcb_mpw1_dc_b(0), + tri_lcb_mpw2_dc_b => lcb_mpw2_dc_b, + tri_lcb_delay_lclkr_dc => lcb_delay_lclkr_dc(0), + tri_lcb_clkoff_dc_b => lcb_clkoff_dc_b, + tri_lcb_act_dis_dc => lcb_act_dis_dc, + + lcb_sg_1 => pc_sg_1(1), + lcb_time_sg_0 => pc_sg_0(1), + lcb_repr_sg_0 => pc_sg_0(1), + lcb_abst_sl_thold_0 => pc_abst_sl_thold_0, + lcb_repr_sl_thold_0 => pc_repr_sl_thold_0, + lcb_time_sl_thold_0 => pc_time_sl_thold_0, + lcb_ary_nsl_thold_0 => pc_ary_slp_nsl_thold_0, + tc_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc, + abist_en_1 => pc_mm_abist_ena_dc, + din_abist => pc_mm_abist_di_g6t_2r_q, + abist_cmp_en => pc_mm_abist_wl128_comp_ena_q, + abist_raw_b_dc => pc_mm_abist_raw_dc_b, + data_cmp_abist => pc_mm_abist_dcomp_g6t_2r_q, + addr_abist => pc_mm_abist_raddr_0_q(3 to 9), + r_wb_abist => pc_mm_abist_g6t_r_wb_q, + lcb_bolt_sl_thold_0 => pc_mm_bolt_sl_thold_0, + pc_bo_enable_2 => pc_mm_bo_enable_2, + pc_bo_reset => pc_mm_bo_reset, + pc_bo_unload => pc_mm_bo_unload, + pc_bo_repair => pc_mm_bo_repair, + pc_bo_shdata => pc_mm_bo_shdata, + pc_bo_select => pc_mm_bo_select(3), + bo_pc_failout => mm_pc_bo_fail(3), + bo_pc_diagloop => mm_pc_bo_diagout(3), + + write_enable => tlb_write(3), + addr => tlb_addr, + data_in => tlb_datainb, + data_out => tlb_dataout(3*tlb_way_width to 4*tlb_way_width-1) +); +lru_array0: entity tri.tri_128x16_1r1w_1(tri_128x16_1r1w_1) + generic map ( expand_type => expand_type ) + port map( + gnd => gnd, + vdd => vdd, + vcs => vcs, + nclk => nclk, + rd_act => tlb_delayed_act(19), + wr_act => tlb_delayed_act(19), + + lcb_d_mode_dc => g8t_gptr_lcb_d_mode_dc, + lcb_clkoff_dc_b => g8t_gptr_lcb_clkoff_dc_b, + lcb_mpw1_dc_b => g8t_gptr_lcb_mpw1_dc_b, + lcb_mpw2_dc_b => g8t_gptr_lcb_mpw2_dc_b, + lcb_delay_lclkr_dc => g8t_gptr_lcb_delay_lclkr_dc, + tri_lcb_mpw1_dc_b => lcb_mpw1_dc_b(0), + tri_lcb_mpw2_dc_b => lcb_mpw2_dc_b, + tri_lcb_delay_lclkr_dc => lcb_delay_lclkr_dc(0), + tri_lcb_clkoff_dc_b => lcb_clkoff_dc_b, + tri_lcb_act_dis_dc => lcb_act_dis_dc, + + ccflush_dc => tc_ac_ccflush_dc, + scan_dis_dc_b => tc_ac_scan_dis_dc_b, + scan_diag_dc => tc_ac_scan_diag_dc, + func_scan_in => tidn, + func_scan_out => open, + + lcb_sg_0 => pc_sg_0(1), + lcb_sl_thold_0_b => pc_func_slp_sl_thold_0_b(1), + + lcb_time_sl_thold_0 => pc_time_sl_thold_0, + lcb_abst_sl_thold_0 => pc_abst_sl_thold_0, + lcb_repr_sl_thold_0 => pc_repr_sl_thold_0, + lcb_ary_nsl_thold_0 => pc_ary_slp_nsl_thold_0, + + time_scan_in => time_scan_int(4), + time_scan_out => time_scan_int(5), + repr_scan_in => repr_scan_int(4), + repr_scan_out => repr_scan_int(5), + abst_scan_in => abst_scan_int(5), + abst_scan_out => abst_scan_int(6), + + abist_di => pc_mm_abist_di_0_q, + abist_bw_odd => pc_mm_abist_g8t_bw_1_q, + abist_bw_even => pc_mm_abist_g8t_bw_0_q, + abist_wr_adr => pc_mm_abist_waddr_0_q(3 TO 9), + wr_abst_act => pc_mm_abist_g8t_wenb_q, + abist_rd0_adr => pc_mm_abist_raddr_0_q(3 TO 9), + rd0_abst_act => pc_mm_abist_g8t1p_renb_0_q, + tc_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc, + abist_ena_1 => pc_mm_abist_ena_dc, + abist_g8t_rd0_comp_ena => pc_mm_abist_wl128_comp_ena_q, + abist_raw_dc_b => pc_mm_abist_raw_dc_b, + obs0_abist_cmp => pc_mm_abist_g8t_dcomp_q, + + lcb_bolt_sl_thold_0 => pc_mm_bolt_sl_thold_0, + pc_bo_enable_2 => pc_mm_bo_enable_2, + pc_bo_reset => pc_mm_bo_reset, + pc_bo_unload => pc_mm_bo_unload, + pc_bo_repair => pc_mm_bo_repair, + pc_bo_shdata => pc_mm_bo_shdata, + pc_bo_select => pc_mm_bo_select(4), + bo_pc_failout => mm_pc_bo_fail(4), + bo_pc_diagloop => mm_pc_bo_diagout(4), + + bw => lru_write(0 to lru_width-1), + wr_adr => lru_wr_addr, + rd_adr => lru_rd_addr, + di => lru_datain(0 to lru_width-1), + do => lru_dataout(0 to lru_width-1) +); +end generate tlb_gen_instance; +xu_mm_ex2_eff_addr_sig <= xu_mm_ex2_eff_addr; +siv_0(0 to scan_right_0) <= sov_0(1 to scan_right_0) & func_scan_in_int(0); +func_scan_out_int(0) <= sov_0(0); +siv_1(0 to scan_right_1) <= sov_1(1 to scan_right_1) & func_scan_in_int(9); +func_scan_out_int(9) <= sov_1(0); +time_scan_int(0) <= time_scan_in_int; +repr_scan_int(0) <= repr_scan_in_int; +abst_scan_int(0) <= abst_scan_in_int(0); +abst_scan_int(3) <= abst_scan_in_int(1); +abst_scan_out_int(0) <= abst_scan_int(2); +abst_scan_out_int(1) <= abst_scan_int(6); +time_scan_out_int <= time_scan_int(5); +repr_scan_out_int <= repr_scan_int(5); +bcfg_scan_out_int <= bcfg_scan_in_int; +dcfg_scan_out_int <= dcfg_scan_in_int; +bsiv(0) <= ccfg_scan_in_int; +ccfg_scan_out_int <= bsov(boot_scan_right); +unused_dc(0) <= PC_ABST_SLP_SL_THOLD_0; +unused_dc(1) <= pc_ary_nsl_thold_0; +unused_dc(2 to 3) <= PC_FUNC_SL_THOLD_0(0 TO 1); +unused_dc(4 to 5) <= PC_FUNC_SL_THOLD_0_B(0 TO 1); +unused_dc(6 to 7) <= PC_FUNC_SLP_SL_THOLD_0(0 TO 1); +unused_dc(8) <= G8T_GPTR_LCB_ACT_DIS_DC; +unused_dc(9 to 11) <= PC_MM_ABIST_RADDR_0_Q(0 TO 2); +unused_dc(12 to 14) <= PC_MM_ABIST_WADDR_0_Q(0 TO 2); +unused_dc(15) <= PC_FUNC_SLP_SL_THOLD_0_B(0); +unused_dc(16 to 17) <= MMUCR0_0_SIG(0 TO 1); +unused_dc(18 to 19) <= MMUCR0_1_SIG(0 TO 1); +unused_dc(20 to 21) <= MMUCR0_2_SIG(0 TO 1); +unused_dc(22 to 23) <= MMUCR0_3_SIG(0 TO 1); +unused_dc(24 to 27) <= MMUCR1_SIG(0 TO 3); +unused_dc(28 to 31) <= MMUCR1_SIG(6 TO 9); +unused_dc(32 to 43) <= MMUCR1_SIG(20 TO 31); +unused_dc(44 to 65) <= TLB_TAG0_EPN(0 TO 21); +unused_dc(66 to 70) <= XU_MM_CCR2_NOTLB_B(8 TO 12); +an_ac_back_inv_omm <= an_ac_back_inv; +an_ac_back_inv_addr_omm <= an_ac_back_inv_addr; +an_ac_back_inv_target_omm_iua <= an_ac_back_inv_target(0 to 1); +an_ac_back_inv_target_omm_iub <= an_ac_back_inv_target(3 to 4); +an_ac_reld_core_tag_omm <= an_ac_reld_core_tag; +an_ac_reld_data_omm <= an_ac_reld_data; +an_ac_reld_data_vld_omm <= an_ac_reld_data_vld; +an_ac_reld_ecc_err_omm <= an_ac_reld_ecc_err; +an_ac_reld_ecc_err_ue_omm <= an_ac_reld_ecc_err_ue; +an_ac_reld_qw_omm <= an_ac_reld_qw; +an_ac_reld_ditc_omm <= an_ac_reld_ditc; +an_ac_reld_crit_qw_omm <= an_ac_reld_crit_qw; +an_ac_reld_data_coming_omm <= an_ac_reld_data_coming; +an_ac_reld_l1_dump_omm <= an_ac_reld_l1_dump; +an_ac_grffence_en_dc_omm <= an_ac_grffence_en_dc; +an_ac_stcx_complete_omm <= an_ac_stcx_complete; +an_ac_abist_mode_dc_omm <= an_ac_abist_mode_dc; +an_ac_abist_start_test_omm <= an_ac_abist_start_test; +an_ac_abst_scan_in_omm_iu <= an_ac_abst_scan_in(0 to 4); +an_ac_abst_scan_in_omm_xu <= an_ac_abst_scan_in(7 to 9); +an_ac_atpg_en_dc_omm <= an_ac_atpg_en_dc; +an_ac_bcfg_scan_in_omm_bit1 <= an_ac_bcfg_scan_in(1); +an_ac_bcfg_scan_in_omm_bit3 <= an_ac_bcfg_scan_in(3); +an_ac_bcfg_scan_in_omm_bit4 <= an_ac_bcfg_scan_in(4); +an_ac_lbist_ary_wrt_thru_dc_omm <= an_ac_lbist_ary_wrt_thru_dc; +an_ac_ccflush_dc_omm <= an_ac_ccflush_dc; +an_ac_reset_1_complete_omm <= an_ac_reset_1_complete; +an_ac_reset_2_complete_omm <= an_ac_reset_2_complete; +an_ac_reset_3_complete_omm <= an_ac_reset_3_complete; +an_ac_reset_wd_complete_omm <= an_ac_reset_wd_complete; +an_ac_dcfg_scan_in_omm <= an_ac_dcfg_scan_in(1 to 2); +an_ac_debug_stop_omm <= an_ac_debug_stop; +an_ac_func_scan_in_omm_iua <= an_ac_func_scan_in(0 to 21); +an_ac_func_scan_in_omm_iub <= an_ac_func_scan_in(60 to 63); +an_ac_func_scan_in_omm_xu <= an_ac_func_scan_in(31 to 58); +an_ac_lbist_en_dc_omm <= an_ac_lbist_en_dc; +an_ac_pm_thread_stop_omm <= an_ac_pm_thread_stop; +an_ac_regf_scan_in_omm <= an_ac_regf_scan_in; +an_ac_scan_diag_dc_omm <= an_ac_scan_diag_dc; +an_ac_scan_dis_dc_b_omm <= an_ac_scan_dis_dc_b; +an_ac_scom_cch_omm <= an_ac_scom_cch; +an_ac_scom_dch_omm <= an_ac_scom_dch; +an_ac_checkstop_omm <= an_ac_checkstop; +an_ac_crit_interrupt_omm <= an_ac_crit_interrupt; +an_ac_ext_interrupt_omm <= an_ac_ext_interrupt; +an_ac_flh2l2_gate_omm <= an_ac_flh2l2_gate; +an_ac_icbi_ack_omm <= an_ac_icbi_ack; +an_ac_icbi_ack_thread_omm <= an_ac_icbi_ack_thread; +an_ac_req_ld_pop_omm <= an_ac_req_ld_pop; +an_ac_req_spare_ctrl_a1_omm <= an_ac_req_spare_ctrl_a1; +an_ac_req_st_gather_omm <= an_ac_req_st_gather; +an_ac_req_st_pop_omm <= an_ac_req_st_pop; +an_ac_req_st_pop_thrd_omm <= an_ac_req_st_pop_thrd; +an_ac_reservation_vld_omm <= an_ac_reservation_vld; +an_ac_sleep_en_omm <= an_ac_sleep_en; +an_ac_stcx_pass_omm <= an_ac_stcx_pass; +an_ac_sync_ack_omm <= an_ac_sync_ack; +an_ac_ary_nsl_thold_7_omm <= an_ac_ary_nsl_thold_7; +an_ac_ccenable_dc_omm <= an_ac_ccenable_dc; +an_ac_coreid_omm <= an_ac_coreid; +an_ac_external_mchk_omm <= an_ac_external_mchk; +an_ac_fce_7_omm <= an_ac_fce_7; +an_ac_func_nsl_thold_7_omm <= an_ac_func_nsl_thold_7; +an_ac_func_sl_thold_7_omm <= an_ac_func_sl_thold_7; +an_ac_gsd_test_enable_dc_omm <= an_ac_gsd_test_enable_dc; +an_ac_gsd_test_acmode_dc_omm <= an_ac_gsd_test_acmode_dc; +an_ac_gptr_scan_in_omm <= an_ac_gptr_scan_in; +an_ac_hang_pulse_omm <= an_ac_hang_pulse; +an_ac_lbist_ac_mode_dc_omm <= an_ac_lbist_ac_mode_dc; +an_ac_lbist_ip_dc_omm <= an_ac_lbist_ip_dc; +an_ac_malf_alert_omm <= an_ac_malf_alert; +an_ac_perf_interrupt_omm <= an_ac_perf_interrupt; +an_ac_psro_enable_dc_omm <= an_ac_psro_enable_dc; +an_ac_repr_scan_in_omm <= an_ac_repr_scan_in; +an_ac_rtim_sl_thold_7_omm <= an_ac_rtim_sl_thold_7; +an_ac_scan_type_dc_omm <= an_ac_scan_type_dc; +an_ac_scom_sat_id_omm <= an_ac_scom_sat_id; +an_ac_sg_7_omm <= an_ac_sg_7; +an_ac_tb_update_enable_omm <= an_ac_tb_update_enable; +an_ac_tb_update_pulse_omm <= an_ac_tb_update_pulse; +an_ac_time_scan_in_omm <= an_ac_time_scan_in; +ac_an_reld_ditc_pop <= ac_an_reld_ditc_pop_imm; +ac_an_power_managed <= ac_an_power_managed_imm; +ac_an_rvwinkle_mode <= ac_an_rvwinkle_mode_imm; +ac_an_fu_bypass_events <= ac_an_fu_bypass_events_imm; +ac_an_iu_bypass_events <= ac_an_iu_bypass_events_imm; +ac_an_mm_bypass_events <= ac_an_mm_bypass_events_imm; +ac_an_lsu_bypass_events <= ac_an_lsu_bypass_events_imm; +ac_an_event_bus <= ac_an_event_bus_imm; +ac_an_abst_scan_out(0 to 4) <= ac_an_abst_scan_out_imm_iu(0 to 4); +ac_an_abst_scan_out(7 to 9) <= ac_an_abst_scan_out_imm_xu(7 to 9); +ac_an_bcfg_scan_out <= ac_an_bcfg_scan_out_imm; +ac_an_dcfg_scan_out <= ac_an_dcfg_scan_out_imm; +ac_an_func_scan_out(0 to 21) <= ac_an_func_scan_out_imm_iua(0 to 21); +ac_an_func_scan_out(31 to 58) <= ac_an_func_scan_out_imm_xu(31 to 58); +ac_an_func_scan_out(60 to 63) <= ac_an_func_scan_out_imm_iub(60 to 63); +ac_an_regf_scan_out <= ac_an_regf_scan_out_imm; +ac_an_pm_thread_running <= ac_an_pm_thread_running_imm; +ac_an_recov_err <= ac_an_recov_err_imm; +ac_an_scom_cch <= ac_an_scom_cch_imm; +ac_an_scom_dch <= ac_an_scom_dch_imm; +ac_an_special_attn <= ac_an_special_attn_imm; +ac_an_checkstop <= ac_an_checkstop_imm; +ac_an_local_checkstop <= ac_an_local_checkstop_imm; +ac_an_trace_error <= ac_an_trace_error_imm; +ac_an_box_empty <= ac_an_box_empty_imm; +ac_an_machine_check <= ac_an_machine_check_imm; +ac_an_req <= ac_an_req_imm; +ac_an_req_endian <= ac_an_req_endian_imm; +ac_an_req_ld_core_tag <= ac_an_req_ld_core_tag_imm; +ac_an_req_ld_xfr_len <= ac_an_req_ld_xfr_len_imm; +ac_an_req_pwr_token <= ac_an_req_pwr_token_imm; +ac_an_req_ra <= ac_an_req_ra_imm; +ac_an_req_spare_ctrl_a0 <= ac_an_req_spare_ctrl_a0_imm; +ac_an_req_thread <= ac_an_req_thread_imm; +ac_an_req_ttype <= ac_an_req_ttype_imm; +ac_an_req_user_defined <= ac_an_req_user_defined_imm; +ac_an_req_wimg_g <= ac_an_req_wimg_g_imm; +ac_an_req_wimg_i <= ac_an_req_wimg_i_imm; +ac_an_req_wimg_m <= ac_an_req_wimg_m_imm; +ac_an_req_wimg_w <= ac_an_req_wimg_w_imm; +ac_an_st_byte_enbl <= ac_an_st_byte_enbl_imm; +ac_an_st_data <= ac_an_st_data_imm; +ac_an_st_data_pwr_token <= ac_an_st_data_pwr_token_imm; +ac_an_abist_done_dc <= ac_an_abist_done_dc_imm; +ac_an_debug_trigger <= ac_an_debug_trigger_imm; +psro_ringsig_inv1: ac_an_psro_ringsig_b <= not(ac_an_psro_ringsig_imm); +psro_ringsig_inv2: ac_an_psro_ringsig <= not(ac_an_psro_ringsig_b); +ac_an_reset_1_request <= ac_an_reset_1_request_imm; +ac_an_reset_2_request <= ac_an_reset_2_request_imm; +ac_an_reset_3_request <= ac_an_reset_3_request_imm; +ac_an_reset_wd_request <= ac_an_reset_wd_request_imm; +ac_an_dcr_act <= '0'; +ac_an_dcr_val <= '0'; +ac_an_dcr_read <= '0'; +ac_an_dcr_user <= '0'; +ac_an_dcr_etid <= (others => '0'); +ac_an_dcr_addr <= (others => '0'); +ac_an_dcr_data <= (others => '0'); +bg_ac_an_func_scan_ns <= bg_ac_an_func_scan_ns_imm; +bg_ac_an_abst_scan_ns <= bg_ac_an_abst_scan_ns_imm; +bg_pc_l1p_abist_di_0 <= bg_pc_l1p_abist_di_0_imm; +bg_pc_l1p_abist_g8t1p_renb_0 <= bg_pc_l1p_abist_g8t1p_renb_0_imm; +bg_pc_l1p_abist_g8t_bw_0 <= bg_pc_l1p_abist_g8t_bw_0_imm; +bg_pc_l1p_abist_g8t_bw_1 <= bg_pc_l1p_abist_g8t_bw_1_imm; +bg_pc_l1p_abist_g8t_dcomp <= bg_pc_l1p_abist_g8t_dcomp_imm; +bg_pc_l1p_abist_g8t_wenb <= bg_pc_l1p_abist_g8t_wenb_imm; +bg_pc_l1p_abist_raddr_0 <= bg_pc_l1p_abist_raddr_0_imm; +bg_pc_l1p_abist_waddr_0 <= bg_pc_l1p_abist_waddr_0_imm; +bg_pc_l1p_abist_wl128_comp_ena <= bg_pc_l1p_abist_wl128_comp_ena_imm; +bg_pc_l1p_abist_wl32_comp_ena <= bg_pc_l1p_abist_wl32_comp_ena_imm; +bg_pc_l1p_gptr_sl_thold_2 <= bg_pc_l1p_gptr_sl_thold_2_imm; +bg_pc_l1p_time_sl_thold_2 <= bg_pc_l1p_time_sl_thold_2_imm; +bg_pc_l1p_repr_sl_thold_2 <= bg_pc_l1p_repr_sl_thold_2_imm; +bg_pc_l1p_abst_sl_thold_2 <= bg_pc_l1p_abst_sl_thold_2_imm; +bg_pc_l1p_func_sl_thold_2 <= bg_pc_l1p_func_sl_thold_2_imm; +bg_pc_l1p_func_slp_sl_thold_2 <= bg_pc_l1p_func_slp_sl_thold_2_imm; +bg_pc_l1p_bolt_sl_thold_2 <= bg_pc_l1p_bolt_sl_thold_2_imm; +bg_pc_l1p_ary_nsl_thold_2 <= bg_pc_l1p_ary_nsl_thold_2_imm; +bg_pc_l1p_sg_2 <= bg_pc_l1p_sg_2_imm; +bg_pc_l1p_fce_2 <= bg_pc_l1p_fce_2_imm; +bg_pc_l1p_bo_enable_2 <= bg_pc_l1p_bo_enable_2_imm; +bg_pc_bo_unload <= bg_pc_bo_unload_imm; +bg_pc_bo_load <= bg_pc_bo_load_imm; +bg_pc_bo_repair <= bg_pc_bo_repair_imm; +bg_pc_bo_reset <= bg_pc_bo_reset_imm; +bg_pc_bo_shdata <= bg_pc_bo_shdata_imm; +bg_pc_bo_select <= bg_pc_bo_select_imm; +bg_pc_l1p_ccflush_dc <= bg_pc_l1p_ccflush_dc_imm; +bg_pc_l1p_abist_ena_dc <= bg_pc_l1p_abist_ena_dc_imm; +bg_pc_l1p_abist_raw_dc_b <= bg_pc_l1p_abist_raw_dc_b_imm; +bg_an_ac_func_scan_sn_omm <= bg_an_ac_func_scan_sn; +bg_an_ac_abst_scan_sn_omm <= bg_an_ac_abst_scan_sn; +bg_pc_bo_fail_omm <= bg_pc_bo_fail; +bg_pc_bo_diagout_omm <= bg_pc_bo_diagout; +end mmq; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/mmq_dbg.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/mmq_dbg.vhdl new file mode 100644 index 0000000..70db50b --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/mmq_dbg.vhdl @@ -0,0 +1,1573 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; +use ieee.std_logic_1164.all; + +library ibm,clib; +use ibm.std_ulogic_unsigned.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; + +library support; +use support.power_logic_pkg.all; + +library tri; +use tri.tri_latches_pkg.all; + +entity mmq_dbg is +generic(thdid_width : integer := 4; + tlb_ways : natural := 4; + tlb_addr_width : natural := 7; + tlb_way_width : natural := 168; + tlb_word_width : natural := 84; + tlb_tag_width : natural := 110; + lru_width : natural := 16; + expand_type : integer := 2 ); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + + pc_func_slp_sl_thold_2 : in std_ulogic; + pc_func_slp_nsl_thold_2 : in std_ulogic; + pc_sg_2 : in std_ulogic; + pc_fce_2 : in std_ulogic; + tc_ac_ccflush_dc : in std_ulogic; + + lcb_clkoff_dc_b : in std_ulogic; + lcb_act_dis_dc : in std_ulogic; + lcb_d_mode_dc : in std_ulogic; + lcb_delay_lclkr_dc : in std_ulogic; + lcb_mpw1_dc_b : in std_ulogic; + lcb_mpw2_dc_b : in std_ulogic; + + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + mmucr2 : in std_ulogic_vector(8 to 11); + + pc_mm_trace_bus_enable : in std_ulogic; + pc_mm_debug_mux1_ctrls : in std_ulogic_vector(0 to 15); + + debug_bus_in : in std_ulogic_vector(0 to 87); + trace_triggers_in : in std_ulogic_vector(0 to 11); + + debug_bus_out : out std_ulogic_vector(0 to 87); + debug_bus_out_int : out std_ulogic_vector(0 to 7); + trace_triggers_out : out std_ulogic_vector(0 to 11); + + spr_dbg_match_64b : in std_ulogic; + spr_dbg_match_any_mmu : in std_ulogic; + spr_dbg_match_any_mas : in std_ulogic; + spr_dbg_match_pid : in std_ulogic; + spr_dbg_match_lpidr : in std_ulogic; + spr_dbg_match_mmucr0 : in std_ulogic; + spr_dbg_match_mmucr1 : in std_ulogic; + spr_dbg_match_mmucr2 : in std_ulogic; + spr_dbg_match_mmucr3 : in std_ulogic; + + spr_dbg_match_mmucsr0 : in std_ulogic; + spr_dbg_match_mmucfg : in std_ulogic; + spr_dbg_match_tlb0cfg : in std_ulogic; + spr_dbg_match_tlb0ps : in std_ulogic; + spr_dbg_match_lratcfg : in std_ulogic; + spr_dbg_match_lratps : in std_ulogic; + spr_dbg_match_eptcfg : in std_ulogic; + spr_dbg_match_lper : in std_ulogic; + spr_dbg_match_lperu : in std_ulogic; + + spr_dbg_match_mas0 : in std_ulogic; + spr_dbg_match_mas1 : in std_ulogic; + spr_dbg_match_mas2 : in std_ulogic; + spr_dbg_match_mas2u : in std_ulogic; + spr_dbg_match_mas3 : in std_ulogic; + spr_dbg_match_mas4 : in std_ulogic; + spr_dbg_match_mas5 : in std_ulogic; + spr_dbg_match_mas6 : in std_ulogic; + spr_dbg_match_mas7 : in std_ulogic; + spr_dbg_match_mas8 : in std_ulogic; + spr_dbg_match_mas01_64b : in std_ulogic; + spr_dbg_match_mas56_64b : in std_ulogic; + spr_dbg_match_mas73_64b : in std_ulogic; + spr_dbg_match_mas81_64b : in std_ulogic; + + spr_dbg_slowspr_val_int : in std_ulogic; + spr_dbg_slowspr_rw_int : in std_ulogic; + spr_dbg_slowspr_etid_int : in std_ulogic_vector(0 to 1); + spr_dbg_slowspr_addr_int : in std_ulogic_vector(0 to 9); + spr_dbg_slowspr_val_out : in std_ulogic; + spr_dbg_slowspr_done_out : in std_ulogic; + spr_dbg_slowspr_data_out : in std_ulogic_vector(0 to 63); + + + inval_dbg_seq_q : in std_ulogic_vector(0 to 4); + inval_dbg_seq_idle : in std_ulogic; + inval_dbg_seq_snoop_inprogress : in std_ulogic; + inval_dbg_seq_snoop_done : in std_ulogic; + inval_dbg_seq_local_done : in std_ulogic; + inval_dbg_seq_tlb0fi_done : in std_ulogic; + inval_dbg_seq_tlbwe_snoop_done : in std_ulogic; + inval_dbg_ex6_valid : in std_ulogic; + inval_dbg_ex6_thdid : in std_ulogic_vector(0 to 1); + inval_dbg_ex6_ttype : in std_ulogic_vector(0 to 2); + inval_dbg_snoop_forme : in std_ulogic; + inval_dbg_snoop_local_reject : in std_ulogic; + inval_dbg_an_ac_back_inv_q : in std_ulogic_vector(2 to 8); + inval_dbg_an_ac_back_inv_lpar_id_q : in std_ulogic_vector(0 to 7); + inval_dbg_an_ac_back_inv_addr_q : in std_ulogic_vector(22 to 63); + inval_dbg_snoop_valid_q : in std_ulogic_vector(0 to 2); + inval_dbg_snoop_ack_q : in std_ulogic_vector(0 to 2); + inval_dbg_snoop_attr_q : in std_ulogic_vector(0 to 34); + inval_dbg_snoop_attr_tlb_spec_q : in std_ulogic_vector(18 to 19); + inval_dbg_snoop_vpn_q : in std_ulogic_vector(17 to 51); + inval_dbg_lsu_tokens_q : in std_ulogic_vector(0 to 1); + + tlb_req_dbg_ierat_iu5_valid_q : in std_ulogic; + tlb_req_dbg_ierat_iu5_thdid : in std_ulogic_vector(0 to 1); + tlb_req_dbg_ierat_iu5_state_q : in std_ulogic_vector(0 to 3); + tlb_req_dbg_ierat_inptr_q : in std_ulogic_vector(0 to 1); + tlb_req_dbg_ierat_outptr_q : in std_ulogic_vector(0 to 1); + tlb_req_dbg_ierat_req_valid_q : in std_ulogic_vector(0 to 3); + tlb_req_dbg_ierat_req_nonspec_q : in std_ulogic_vector(0 to 3); + tlb_req_dbg_ierat_req_thdid : in std_ulogic_vector(0 to 7); + tlb_req_dbg_ierat_req_dup_q : in std_ulogic_vector(0 to 3); + tlb_req_dbg_derat_ex6_valid_q : in std_ulogic; + tlb_req_dbg_derat_ex6_thdid : in std_ulogic_vector(0 to 1); + tlb_req_dbg_derat_ex6_state_q : in std_ulogic_vector(0 to 3); + tlb_req_dbg_derat_inptr_q : in std_ulogic_vector(0 to 1); + tlb_req_dbg_derat_outptr_q : in std_ulogic_vector(0 to 1); + tlb_req_dbg_derat_req_valid_q : in std_ulogic_vector(0 to 3); + tlb_req_dbg_derat_req_thdid : in std_ulogic_vector(0 to 7); + tlb_req_dbg_derat_req_ttype_q : in std_ulogic_vector(0 to 7); + tlb_req_dbg_derat_req_dup_q : in std_ulogic_vector(0 to 3); + + tlb_ctl_dbg_seq_q : in std_ulogic_vector(0 to 5); + tlb_ctl_dbg_seq_idle : in std_ulogic; + tlb_ctl_dbg_seq_any_done_sig : in std_ulogic; + tlb_ctl_dbg_seq_abort : in std_ulogic; + tlb_ctl_dbg_any_tlb_req_sig : in std_ulogic; + tlb_ctl_dbg_any_req_taken_sig : in std_ulogic; + tlb_ctl_dbg_tag0_valid : in std_ulogic; + tlb_ctl_dbg_tag0_thdid : in std_ulogic_vector(0 to 1); + tlb_ctl_dbg_tag0_type : in std_ulogic_vector(0 to 2); + tlb_ctl_dbg_tag0_wq : in std_ulogic_vector(0 to 1); + tlb_ctl_dbg_tag0_gs : in std_ulogic; + tlb_ctl_dbg_tag0_pr : in std_ulogic; + tlb_ctl_dbg_tag0_atsel : in std_ulogic; + tlb_ctl_dbg_tag5_tlb_write_q : in std_ulogic_vector(0 to 3); + tlb_ctl_dbg_resv_valid : in std_ulogic_vector(0 to 3); + tlb_ctl_dbg_set_resv : in std_ulogic_vector(0 to 3); + tlb_ctl_dbg_resv_match_vec_q : in std_ulogic_vector(0 to 3); + tlb_ctl_dbg_any_tag_flush_sig : in std_ulogic; + tlb_ctl_dbg_resv0_tag0_lpid_match : in std_ulogic; + tlb_ctl_dbg_resv0_tag0_pid_match : in std_ulogic; + tlb_ctl_dbg_resv0_tag0_as_snoop_match : in std_ulogic; + tlb_ctl_dbg_resv0_tag0_gs_snoop_match : in std_ulogic; + tlb_ctl_dbg_resv0_tag0_as_tlbwe_match : in std_ulogic; + tlb_ctl_dbg_resv0_tag0_gs_tlbwe_match : in std_ulogic; + tlb_ctl_dbg_resv0_tag0_ind_match : in std_ulogic; + tlb_ctl_dbg_resv0_tag0_epn_loc_match : in std_ulogic; + tlb_ctl_dbg_resv0_tag0_epn_glob_match : in std_ulogic; + tlb_ctl_dbg_resv0_tag0_class_match : in std_ulogic; + tlb_ctl_dbg_resv1_tag0_lpid_match : in std_ulogic; + tlb_ctl_dbg_resv1_tag0_pid_match : in std_ulogic; + tlb_ctl_dbg_resv1_tag0_as_snoop_match : in std_ulogic; + tlb_ctl_dbg_resv1_tag0_gs_snoop_match : in std_ulogic; + tlb_ctl_dbg_resv1_tag0_as_tlbwe_match : in std_ulogic; + tlb_ctl_dbg_resv1_tag0_gs_tlbwe_match : in std_ulogic; + tlb_ctl_dbg_resv1_tag0_ind_match : in std_ulogic; + tlb_ctl_dbg_resv1_tag0_epn_loc_match : in std_ulogic; + tlb_ctl_dbg_resv1_tag0_epn_glob_match : in std_ulogic; + tlb_ctl_dbg_resv1_tag0_class_match : in std_ulogic; + tlb_ctl_dbg_resv2_tag0_lpid_match : in std_ulogic; + tlb_ctl_dbg_resv2_tag0_pid_match : in std_ulogic; + tlb_ctl_dbg_resv2_tag0_as_snoop_match : in std_ulogic; + tlb_ctl_dbg_resv2_tag0_gs_snoop_match : in std_ulogic; + tlb_ctl_dbg_resv2_tag0_as_tlbwe_match : in std_ulogic; + tlb_ctl_dbg_resv2_tag0_gs_tlbwe_match : in std_ulogic; + tlb_ctl_dbg_resv2_tag0_ind_match : in std_ulogic; + tlb_ctl_dbg_resv2_tag0_epn_loc_match : in std_ulogic; + tlb_ctl_dbg_resv2_tag0_epn_glob_match : in std_ulogic; + tlb_ctl_dbg_resv2_tag0_class_match : in std_ulogic; + tlb_ctl_dbg_resv3_tag0_lpid_match : in std_ulogic; + tlb_ctl_dbg_resv3_tag0_pid_match : in std_ulogic; + tlb_ctl_dbg_resv3_tag0_as_snoop_match : in std_ulogic; + tlb_ctl_dbg_resv3_tag0_gs_snoop_match : in std_ulogic; + tlb_ctl_dbg_resv3_tag0_as_tlbwe_match : in std_ulogic; + tlb_ctl_dbg_resv3_tag0_gs_tlbwe_match : in std_ulogic; + tlb_ctl_dbg_resv3_tag0_ind_match : in std_ulogic; + tlb_ctl_dbg_resv3_tag0_epn_loc_match : in std_ulogic; + tlb_ctl_dbg_resv3_tag0_epn_glob_match : in std_ulogic; + tlb_ctl_dbg_resv3_tag0_class_match : in std_ulogic; + tlb_ctl_dbg_clr_resv_q : in std_ulogic_vector(0 to 3); + tlb_ctl_dbg_clr_resv_terms : in std_ulogic_vector(0 to 3); + + tlb_cmp_dbg_tag4 : in std_ulogic_vector(0 to tlb_tag_width-1); + tlb_cmp_dbg_tag4_wayhit : in std_ulogic_vector(0 to tlb_ways); + tlb_cmp_dbg_addr4 : in std_ulogic_vector(0 to tlb_addr_width-1); + tlb_cmp_dbg_tag4_way : in std_ulogic_vector(0 to tlb_way_width-1); + tlb_cmp_dbg_tag4_parerr : in std_ulogic_vector(0 to 4); + tlb_cmp_dbg_tag4_lru_dataout_q : in std_ulogic_vector(0 to lru_width-5); + tlb_cmp_dbg_tag5_tlb_datain_q : in std_ulogic_vector(0 to tlb_way_width-1); + tlb_cmp_dbg_tag5_lru_datain_q : in std_ulogic_vector(0 to lru_width-5); + tlb_cmp_dbg_tag5_lru_write : in std_ulogic; + tlb_cmp_dbg_tag5_any_exception : in std_ulogic; + tlb_cmp_dbg_tag5_except_type_q : in std_ulogic_vector(0 to 3); + tlb_cmp_dbg_tag5_except_thdid_q : in std_ulogic_vector(0 to 1); + tlb_cmp_dbg_tag5_erat_rel_val : in std_ulogic_vector(0 to 9); + tlb_cmp_dbg_tag5_erat_rel_data : in std_ulogic_vector(0 to 131); + tlb_cmp_dbg_erat_dup_q : in std_ulogic_vector(0 to 19); + + + tlb_cmp_dbg_addr_enable : in std_ulogic_vector(0 to 8); + tlb_cmp_dbg_pgsize_enable : in std_ulogic; + tlb_cmp_dbg_class_enable : in std_ulogic; + tlb_cmp_dbg_extclass_enable : in std_ulogic_vector(0 to 1); + tlb_cmp_dbg_state_enable : in std_ulogic_vector(0 to 1); + tlb_cmp_dbg_thdid_enable : in std_ulogic; + tlb_cmp_dbg_pid_enable : in std_ulogic; + tlb_cmp_dbg_lpid_enable : in std_ulogic; + tlb_cmp_dbg_ind_enable : in std_ulogic; + tlb_cmp_dbg_iprot_enable : in std_ulogic; + tlb_cmp_dbg_way0_entry_v : in std_ulogic; + tlb_cmp_dbg_way0_addr_match : in std_ulogic; + tlb_cmp_dbg_way0_pgsize_match : in std_ulogic; + tlb_cmp_dbg_way0_class_match : in std_ulogic; + tlb_cmp_dbg_way0_extclass_match : in std_ulogic; + tlb_cmp_dbg_way0_state_match : in std_ulogic; + tlb_cmp_dbg_way0_thdid_match : in std_ulogic; + tlb_cmp_dbg_way0_pid_match : in std_ulogic; + tlb_cmp_dbg_way0_lpid_match : in std_ulogic; + tlb_cmp_dbg_way0_ind_match : in std_ulogic; + tlb_cmp_dbg_way0_iprot_match : in std_ulogic; + tlb_cmp_dbg_way1_entry_v : in std_ulogic; + tlb_cmp_dbg_way1_addr_match : in std_ulogic; + tlb_cmp_dbg_way1_pgsize_match : in std_ulogic; + tlb_cmp_dbg_way1_class_match : in std_ulogic; + tlb_cmp_dbg_way1_extclass_match : in std_ulogic; + tlb_cmp_dbg_way1_state_match : in std_ulogic; + tlb_cmp_dbg_way1_thdid_match : in std_ulogic; + tlb_cmp_dbg_way1_pid_match : in std_ulogic; + tlb_cmp_dbg_way1_lpid_match : in std_ulogic; + tlb_cmp_dbg_way1_ind_match : in std_ulogic; + tlb_cmp_dbg_way1_iprot_match : in std_ulogic; + tlb_cmp_dbg_way2_entry_v : in std_ulogic; + tlb_cmp_dbg_way2_addr_match : in std_ulogic; + tlb_cmp_dbg_way2_pgsize_match : in std_ulogic; + tlb_cmp_dbg_way2_class_match : in std_ulogic; + tlb_cmp_dbg_way2_extclass_match : in std_ulogic; + tlb_cmp_dbg_way2_state_match : in std_ulogic; + tlb_cmp_dbg_way2_thdid_match : in std_ulogic; + tlb_cmp_dbg_way2_pid_match : in std_ulogic; + tlb_cmp_dbg_way2_lpid_match : in std_ulogic; + tlb_cmp_dbg_way2_ind_match : in std_ulogic; + tlb_cmp_dbg_way2_iprot_match : in std_ulogic; + tlb_cmp_dbg_way3_entry_v : in std_ulogic; + tlb_cmp_dbg_way3_addr_match : in std_ulogic; + tlb_cmp_dbg_way3_pgsize_match : in std_ulogic; + tlb_cmp_dbg_way3_class_match : in std_ulogic; + tlb_cmp_dbg_way3_extclass_match : in std_ulogic; + tlb_cmp_dbg_way3_state_match : in std_ulogic; + tlb_cmp_dbg_way3_thdid_match : in std_ulogic; + tlb_cmp_dbg_way3_pid_match : in std_ulogic; + tlb_cmp_dbg_way3_lpid_match : in std_ulogic; + tlb_cmp_dbg_way3_ind_match : in std_ulogic; + tlb_cmp_dbg_way3_iprot_match : in std_ulogic; + + lrat_dbg_tag1_addr_enable : in std_ulogic; + lrat_dbg_tag2_matchline_q : in std_ulogic_vector(0 to 7); + lrat_dbg_entry0_addr_match : in std_ulogic; + lrat_dbg_entry0_lpid_match : in std_ulogic; + lrat_dbg_entry0_entry_v : in std_ulogic; + lrat_dbg_entry0_entry_x : in std_ulogic; + lrat_dbg_entry0_size : in std_ulogic_vector(0 to 3); + lrat_dbg_entry1_addr_match : in std_ulogic; + lrat_dbg_entry1_lpid_match : in std_ulogic; + lrat_dbg_entry1_entry_v : in std_ulogic; + lrat_dbg_entry1_entry_x : in std_ulogic; + lrat_dbg_entry1_size : in std_ulogic_vector(0 to 3); + lrat_dbg_entry2_addr_match : in std_ulogic; + lrat_dbg_entry2_lpid_match : in std_ulogic; + lrat_dbg_entry2_entry_v : in std_ulogic; + lrat_dbg_entry2_entry_x : in std_ulogic; + lrat_dbg_entry2_size : in std_ulogic_vector(0 to 3); + lrat_dbg_entry3_addr_match : in std_ulogic; + lrat_dbg_entry3_lpid_match : in std_ulogic; + lrat_dbg_entry3_entry_v : in std_ulogic; + lrat_dbg_entry3_entry_x : in std_ulogic; + lrat_dbg_entry3_size : in std_ulogic_vector(0 to 3); + lrat_dbg_entry4_addr_match : in std_ulogic; + lrat_dbg_entry4_lpid_match : in std_ulogic; + lrat_dbg_entry4_entry_v : in std_ulogic; + lrat_dbg_entry4_entry_x : in std_ulogic; + lrat_dbg_entry4_size : in std_ulogic_vector(0 to 3); + lrat_dbg_entry5_addr_match : in std_ulogic; + lrat_dbg_entry5_lpid_match : in std_ulogic; + lrat_dbg_entry5_entry_v : in std_ulogic; + lrat_dbg_entry5_entry_x : in std_ulogic; + lrat_dbg_entry5_size : in std_ulogic_vector(0 to 3); + lrat_dbg_entry6_addr_match : in std_ulogic; + lrat_dbg_entry6_lpid_match : in std_ulogic; + lrat_dbg_entry6_entry_v : in std_ulogic; + lrat_dbg_entry6_entry_x : in std_ulogic; + lrat_dbg_entry6_size : in std_ulogic_vector(0 to 3); + lrat_dbg_entry7_addr_match : in std_ulogic; + lrat_dbg_entry7_lpid_match : in std_ulogic; + lrat_dbg_entry7_entry_v : in std_ulogic; + lrat_dbg_entry7_entry_x : in std_ulogic; + lrat_dbg_entry7_size : in std_ulogic_vector(0 to 3); + + htw_dbg_seq_idle : in std_ulogic; + htw_dbg_pte0_seq_idle : in std_ulogic; + htw_dbg_pte1_seq_idle : in std_ulogic; + htw_dbg_seq_q : in std_ulogic_vector(0 to 1); + htw_dbg_inptr_q : in std_ulogic_vector(0 to 1); + htw_dbg_pte0_seq_q : in std_ulogic_vector(0 to 2); + htw_dbg_pte1_seq_q : in std_ulogic_vector(0 to 2); + htw_dbg_ptereload_ptr_q : in std_ulogic; + htw_dbg_lsuptr_q : in std_ulogic_vector(0 to 1); + htw_dbg_req_valid_q : in std_ulogic_vector(0 to 3); + htw_dbg_resv_valid_vec : in std_ulogic_vector(0 to 3); + htw_dbg_tag4_clr_resv_q : in std_ulogic_vector(0 to 3); + htw_dbg_tag4_clr_resv_terms : in std_ulogic_vector(0 to 3); + htw_dbg_pte0_score_ptr_q : in std_ulogic_vector(0 to 1); + htw_dbg_pte0_score_cl_offset_q : in std_ulogic_vector(58 to 60); + htw_dbg_pte0_score_error_q : in std_ulogic_vector(0 to 2); + htw_dbg_pte0_score_qwbeat_q : in std_ulogic_vector(0 to 3); + htw_dbg_pte0_score_pending_q : in std_ulogic; + htw_dbg_pte0_score_ibit_q : in std_ulogic; + htw_dbg_pte0_score_dataval_q : in std_ulogic; + htw_dbg_pte0_reld_for_me_tm1 : in std_ulogic; + htw_dbg_pte1_score_ptr_q : in std_ulogic_vector(0 to 1); + htw_dbg_pte1_score_cl_offset_q : in std_ulogic_vector(58 to 60); + htw_dbg_pte1_score_error_q : in std_ulogic_vector(0 to 2); + htw_dbg_pte1_score_qwbeat_q : in std_ulogic_vector(0 to 3); + htw_dbg_pte1_score_pending_q : in std_ulogic; + htw_dbg_pte1_score_ibit_q : in std_ulogic; + htw_dbg_pte1_score_dataval_q : in std_ulogic; + htw_dbg_pte1_reld_for_me_tm1 : in std_ulogic; + + mm_xu_lsu_req : in std_ulogic_vector(0 to thdid_width-1); + mm_xu_lsu_ttype : in std_ulogic_vector(0 to 1); + mm_xu_lsu_wimge : in std_ulogic_vector(0 to 4); + mm_xu_lsu_u : in std_ulogic_vector(0 to 3); + mm_xu_lsu_addr : in std_ulogic_vector(22 to 63); + mm_xu_lsu_lpid : in std_ulogic_vector(0 to 7); + mm_xu_lsu_gs : in std_ulogic; + mm_xu_lsu_ind : in std_ulogic; + mm_xu_lsu_lbit : in std_ulogic; + xu_mm_lsu_token : in std_ulogic; + + + tlb_mas_tlbre : in std_ulogic; + tlb_mas_tlbsx_hit : in std_ulogic; + tlb_mas_tlbsx_miss : in std_ulogic; + tlb_mas_dtlb_error : in std_ulogic; + tlb_mas_itlb_error : in std_ulogic; + tlb_mas_thdid : in std_ulogic_vector(0 to 3); + lrat_mas_tlbre : in std_ulogic; + lrat_mas_tlbsx_hit : in std_ulogic; + lrat_mas_tlbsx_miss : in std_ulogic; + lrat_mas_thdid : in std_ulogic_vector(0 to 3); + lrat_tag3_hit_status : in std_ulogic_vector(0 to 3); + lrat_tag3_hit_entry : in std_ulogic_vector(0 to 2); + + tlb_seq_ierat_req : in std_ulogic; + tlb_seq_derat_req : in std_ulogic; + mm_xu_hold_req : in std_ulogic_vector(0 to 3); + xu_mm_hold_ack : in std_ulogic_vector(0 to 3); + mm_xu_hold_done : in std_ulogic_vector(0 to 3); + mmucsr0_tlb0fi : in std_ulogic; + tlbwe_back_inv_valid : in std_ulogic; + tlbwe_back_inv_attr : in std_ulogic_vector(18 to 19); + xu_mm_lmq_stq_empty : in std_ulogic; + iu_mm_lmq_empty : in std_ulogic; + mm_xu_eratmiss_done : in std_ulogic_vector(0 to 3); + mm_iu_barrier_done : in std_ulogic_vector(0 to 3); + mm_xu_ex3_flush_req : in std_ulogic_vector(0 to 3); + mm_xu_illeg_instr : in std_ulogic_vector(0 to 3); + lrat_tag4_hit_status : in std_ulogic_vector(0 to 3); + lrat_tag4_hit_entry : in std_ulogic_vector(0 to 2); + mm_xu_cr0_eq : in std_ulogic_vector(0 to 3); + mm_xu_cr0_eq_valid : in std_ulogic_vector(0 to 3); + tlb_htw_req_valid : in std_ulogic; + htw_lsu_req_valid : in std_ulogic; + htw_dbg_lsu_thdid : in std_ulogic_vector(0 to 1); + htw_lsu_ttype : in std_ulogic_vector(0 to 1); + htw_lsu_addr : in std_ulogic_vector(22 to 63); + ptereload_req_taken : in std_ulogic; + ptereload_req_pte : in std_ulogic_vector(0 to 63) + + + +); + + -- synopsys translate_off + + + -- synopsys translate_on +end mmq_dbg; + + +architecture mmq_dbg of mmq_dbg is + +constant tagpos_epn : natural := 0; +constant tagpos_pid : natural := 52; +constant tagpos_is : natural := 66; +constant tagpos_class : natural := 68; +constant tagpos_state : natural := 70; +constant tagpos_thdid : natural := 74; +constant tagpos_size : natural := 78; +constant tagpos_type : natural := 82; +constant tagpos_lpid : natural := 90; +constant tagpos_ind : natural := 98; +constant tagpos_atsel : natural := 99; +constant tagpos_esel : natural := 100; +constant tagpos_hes : natural := 103; +constant tagpos_wq : natural := 104; +constant tagpos_lrat : natural := 106; +constant tagpos_pt : natural := 107; +constant tagpos_recform : natural := 108; +constant tagpos_endflag : natural := 109; + +constant tagpos_type_derat : natural := tagpos_type; +constant tagpos_type_ierat : natural := tagpos_type+1; +constant tagpos_type_tlbsx : natural := tagpos_type+2; +constant tagpos_type_tlbsrx : natural := tagpos_type+3; +constant tagpos_type_snoop : natural := tagpos_type+4; +constant tagpos_type_tlbre : natural := tagpos_type+5; +constant tagpos_type_tlbwe : natural := tagpos_type+6; +constant tagpos_type_ptereload : natural := tagpos_type+7; +constant tagpos_pr : natural := tagpos_state; +constant tagpos_gs : natural := tagpos_state+1; +constant tagpos_as : natural := tagpos_state+2; +constant tagpos_cm : natural := tagpos_state+3; + +constant waypos_epn : natural := 0; +constant waypos_size : natural := 52; +constant waypos_thdid : natural := 56; +constant waypos_class : natural := 60; +constant waypos_extclass : natural := 62; +constant waypos_lpid : natural := 66; +constant waypos_xbit : natural := 84; +constant waypos_rpn : natural := 88; +constant waypos_rc : natural := 118; +constant waypos_wlc : natural := 120; +constant waypos_resvattr : natural := 122; +constant waypos_vf : natural := 123; +constant waypos_ind : natural := 124; +constant waypos_ubits : natural := 125; +constant waypos_wimge : natural := 129; +constant waypos_usxwr : natural := 134; +constant waypos_gs : natural := 140; +constant waypos_ts : natural := 141; +constant waypos_tid : natural := 144; + +constant eratpos_epn : natural := 0; +constant eratpos_x : natural := 52; +constant eratpos_size : natural := 53; +constant eratpos_v : natural := 56; +constant eratpos_thdid : natural := 57; +constant eratpos_class : natural := 61; +constant eratpos_extclass : natural := 63; +constant eratpos_wren : natural := 65; +constant eratpos_rpnrsvd : natural := 66; +constant eratpos_rpn : natural := 70; +constant eratpos_r : natural := 100; +constant eratpos_c : natural := 101; +constant eratpos_rsv : natural := 102; +constant eratpos_wlc : natural := 103; +constant eratpos_resvattr : natural := 105; +constant eratpos_vf : natural := 106; +constant eratpos_ubits : natural := 107; +constant eratpos_wimge : natural := 111; +constant eratpos_usxwr : natural := 116; +constant eratpos_gs : natural := 122; +constant eratpos_ts : natural := 123; +constant eratpos_tid : natural := 124; + +signal pc_mm_trace_bus_enable_q : std_ulogic; +signal pc_mm_debug_mux1_ctrls_q : std_ulogic_vector(0 to 15); +signal pc_mm_debug_mux1_ctrls_loc_d, pc_mm_debug_mux1_ctrls_loc_q : std_ulogic_vector(0 to 15); +signal trigger_data_out_d, trigger_data_out_q : std_ulogic_vector(0 to 11); +signal trace_data_out_d, trace_data_out_q : std_ulogic_vector(0 to 87); +signal trace_data_out_int_q : std_ulogic_vector(0 to 7); +signal debug_d, debug_q : std_ulogic_vector(0 to 371); +signal trigger_d, trigger_q : std_ulogic_vector(0 to 47); +signal debug_bus_in_q : std_ulogic_vector(0 to 87); +signal trace_triggers_in_q : std_ulogic_vector(0 to 11); + +constant trace_bus_enable_offset : integer := 0; +constant debug_mux1_ctrls_offset : integer := trace_bus_enable_offset + 1; +constant debug_mux1_ctrls_loc_offset : integer := debug_mux1_ctrls_offset + pc_mm_debug_mux1_ctrls_q'length; +constant trigger_data_out_offset : natural := debug_mux1_ctrls_loc_offset + pc_mm_debug_mux1_ctrls_loc_q'length; +constant trace_data_out_offset : natural := trigger_data_out_offset + trigger_data_out_q'length; +constant trace_data_out_int_offset : natural := trace_data_out_offset + trace_data_out_q'length; +constant scan_right : natural := trace_data_out_int_offset + trace_data_out_int_q'length-1; + +signal dbg_group0 : std_ulogic_vector(0 to 87); +signal dbg_group1 : std_ulogic_vector(0 to 87); +signal dbg_group2 : std_ulogic_vector(0 to 87); +signal dbg_group3 : std_ulogic_vector(0 to 87); +signal dbg_group4 : std_ulogic_vector(0 to 87); +signal dbg_group5 : std_ulogic_vector(0 to 87); +signal dbg_group6 : std_ulogic_vector(0 to 87); +signal dbg_group7 : std_ulogic_vector(0 to 87); +signal dbg_group8 : std_ulogic_vector(0 to 87); +signal dbg_group9 : std_ulogic_vector(0 to 87); + +signal dbg_group10a : std_ulogic_vector(0 to 87); +signal dbg_group11a : std_ulogic_vector(0 to 87); +signal dbg_group12a : std_ulogic_vector(0 to 87); +signal dbg_group13a : std_ulogic_vector(0 to 87); +signal dbg_group14a : std_ulogic_vector(0 to 87); +signal dbg_group15a : std_ulogic_vector(0 to 87); +signal dbg_group10b : std_ulogic_vector(0 to 87); +signal dbg_group11b : std_ulogic_vector(0 to 87); +signal dbg_group12b : std_ulogic_vector(0 to 87); +signal dbg_group13b : std_ulogic_vector(0 to 87); +signal dbg_group14b : std_ulogic_vector(0 to 87); +signal dbg_group15b : std_ulogic_vector(0 to 87); +signal dbg_group10 : std_ulogic_vector(0 to 87); +signal dbg_group11 : std_ulogic_vector(0 to 87); +signal dbg_group12 : std_ulogic_vector(0 to 87); +signal dbg_group13 : std_ulogic_vector(0 to 87); +signal dbg_group14 : std_ulogic_vector(0 to 87); +signal dbg_group15 : std_ulogic_vector(0 to 87); + +constant group12_offset : natural := 68; +constant group13_offset : natural := 112; + +signal trg_group0 : std_ulogic_vector(0 to 11); +signal trg_group1 : std_ulogic_vector(0 to 11); +signal trg_group2 : std_ulogic_vector(0 to 11); +signal trg_group3a : std_ulogic_vector(0 to 11); +signal trg_group3b : std_ulogic_vector(0 to 11); +signal trg_group3 : std_ulogic_vector(0 to 11); + +signal dbg_group0a : std_ulogic_vector(24 to 55); + +signal tlb_ctl_dbg_tag1_valid : std_ulogic; +signal tlb_ctl_dbg_tag1_thdid : std_ulogic_vector(0 to 1); +signal tlb_ctl_dbg_tag1_type : std_ulogic_vector(0 to 2); +signal tlb_ctl_dbg_tag1_wq : std_ulogic_vector(0 to 1); +signal tlb_ctl_dbg_tag1_gs : std_ulogic; +signal tlb_ctl_dbg_tag1_pr : std_ulogic; +signal tlb_ctl_dbg_tag1_atsel : std_ulogic; +signal tlb_cmp_dbg_tag4_thdid : std_ulogic_vector(0 to 1); +signal tlb_cmp_dbg_tag4_type : std_ulogic_vector(0 to 2); +signal tlb_cmp_dbg_tag4_valid : std_ulogic; +signal tlb_cmp_dbg_tag5_wayhit : std_ulogic_vector(0 to tlb_ways); +signal tlb_cmp_dbg_tag5_thdid : std_ulogic_vector(0 to 1); +signal tlb_cmp_dbg_tag5_type : std_ulogic_vector(0 to 2); +signal tlb_cmp_dbg_tag5_class : std_ulogic_vector(0 to 1); +signal tlb_cmp_dbg_tag5_iorderat_rel_val : std_ulogic; +signal tlb_cmp_dbg_tag5_iorderat_rel_hit : std_ulogic; +signal tlb_cmp_dbg_tag5_way : std_ulogic_vector(0 to 167); +signal tlb_cmp_dbg_tag5_lru_dataout : std_ulogic_vector(0 to 11); + + +signal unused_dc : std_ulogic_vector(0 to 11); +-- synopsys translate_off +-- synopsys translate_on + +signal pc_func_slp_sl_thold_1 : std_ulogic; +signal pc_func_slp_sl_thold_0 : std_ulogic; +signal pc_func_slp_sl_thold_0_b : std_ulogic; +signal pc_func_slp_sl_force : std_ulogic; +signal pc_func_slp_nsl_thold_1 : std_ulogic; +signal pc_func_slp_nsl_thold_0 : std_ulogic; +signal pc_func_slp_nsl_thold_0_b : std_ulogic; +signal pc_func_slp_nsl_force : std_ulogic; +signal pc_sg_1 : std_ulogic; +signal pc_sg_0 : std_ulogic; +signal pc_fce_1 : std_ulogic; +signal pc_fce_0 : std_ulogic; + +signal siv, sov : std_ulogic_vector(0 to scan_right); + +signal tidn : std_ulogic; +signal tiup : std_ulogic; + + + +begin + + +tidn <= '0'; +tiup <= '1'; + +pc_mm_debug_mux1_ctrls_loc_d <= pc_mm_debug_mux1_ctrls_q; + + +debug_d(12) <= tlb_ctl_dbg_tag0_valid; +debug_d(13 to 14) <= tlb_ctl_dbg_tag0_thdid(0 to 1); +debug_d(15 to 17) <= tlb_ctl_dbg_tag0_type(0 to 2); +debug_d(18 to 19) <= tlb_ctl_dbg_tag0_wq(0 to 1); +debug_d(20) <= tlb_ctl_dbg_tag0_gs; +debug_d(21) <= tlb_ctl_dbg_tag0_pr; +debug_d(22) <= tlb_ctl_dbg_tag0_atsel; +debug_d(23) <= '0'; + +tlb_ctl_dbg_tag1_valid <= debug_q(12); +tlb_ctl_dbg_tag1_thdid(0 to 1) <= debug_q(13 to 14); +tlb_ctl_dbg_tag1_type(0 to 2) <= debug_q(15 to 17); +tlb_ctl_dbg_tag1_wq(0 to 1) <= debug_q(18 to 19); +tlb_ctl_dbg_tag1_gs <= debug_q(20); +tlb_ctl_dbg_tag1_pr <= debug_q(21); +tlb_ctl_dbg_tag1_atsel <= debug_q(22); + + + +debug_d(192 to 275) <= TLB_CMP_DBG_TAG4_WAY(0 to 83); +tlb_cmp_dbg_tag5_way(0 to 83) <= debug_q(192 to 275); + +debug_d(276 to 359) <= TLB_CMP_DBG_TAG4_WAY(84 to 167); +tlb_cmp_dbg_tag5_way(84 to 167) <= debug_q(276 to 359); + +debug_d(360 to 371) <= tlb_cmp_dbg_tag4_lru_dataout_q(0 to 11); +tlb_cmp_dbg_tag5_lru_dataout(0 to 11) <= debug_q(360 to 371); + + +trigger_d(0 to 11) <= (others => '0'); +trigger_d(12 to 23) <= (others => '0'); +trigger_d(24 to 35) <= (others => '0'); +trigger_d(36 to 47) <= (others => '0'); + + +dbg_group0(0) <= spr_dbg_slowspr_val_int; +dbg_group0(1) <= spr_dbg_slowspr_rw_int; +dbg_group0(2 to 3) <= spr_dbg_slowspr_etid_int; +dbg_group0(4 to 13) <= spr_dbg_slowspr_addr_int; +dbg_group0(14) <= spr_dbg_slowspr_done_out; +dbg_group0(15) <= spr_dbg_match_any_mmu; +dbg_group0(16) <= spr_dbg_match_any_mas; +dbg_group0(17) <= spr_dbg_match_pid; +dbg_group0(18) <= spr_dbg_match_lpidr; +dbg_group0(19) <= spr_dbg_match_mas2; +dbg_group0(20) <= spr_dbg_match_mas01_64b; +dbg_group0(21) <= spr_dbg_match_mas56_64b; +dbg_group0(22) <= spr_dbg_match_mas73_64b; +dbg_group0(23) <= spr_dbg_match_mas81_64b; + +dbg_group0a(24) <= spr_dbg_match_mmucr0; +dbg_group0a(25) <= spr_dbg_match_mmucr1; +dbg_group0a(26) <= spr_dbg_match_mmucr2; +dbg_group0a(27) <= spr_dbg_match_mmucr3; +dbg_group0a(28) <= spr_dbg_match_mmucsr0; +dbg_group0a(29) <= spr_dbg_match_mmucfg; +dbg_group0a(30) <= spr_dbg_match_tlb0cfg; +dbg_group0a(31) <= spr_dbg_match_tlb0ps; +dbg_group0a(32) <= spr_dbg_match_lratcfg; +dbg_group0a(33) <= spr_dbg_match_lratps; +dbg_group0a(34) <= spr_dbg_match_eptcfg; +dbg_group0a(35) <= spr_dbg_match_lper; +dbg_group0a(36) <= spr_dbg_match_lperu; +dbg_group0a(37) <= spr_dbg_match_mas0; +dbg_group0a(38) <= spr_dbg_match_mas1; +dbg_group0a(39) <= spr_dbg_match_mas2u; +dbg_group0a(40) <= spr_dbg_match_mas3; +dbg_group0a(41) <= spr_dbg_match_mas4; +dbg_group0a(42) <= spr_dbg_match_mas5; +dbg_group0a(43) <= spr_dbg_match_mas6; +dbg_group0a(44) <= spr_dbg_match_mas7; +dbg_group0a(45) <= spr_dbg_match_mas8; +dbg_group0a(46) <= tlb_mas_tlbre; +dbg_group0a(47) <= tlb_mas_tlbsx_hit; +dbg_group0a(48) <= tlb_mas_tlbsx_miss; +dbg_group0a(49) <= tlb_mas_dtlb_error; +dbg_group0a(50) <= tlb_mas_itlb_error; +dbg_group0a(51) <= tlb_mas_thdid(2) or tlb_mas_thdid(3); +dbg_group0a(52) <= tlb_mas_thdid(1) or tlb_mas_thdid(3); +dbg_group0a(53) <= lrat_mas_tlbre; +dbg_group0a(54) <= lrat_mas_thdid(2) or lrat_mas_thdid(3); +dbg_group0a(55) <= lrat_mas_thdid(1) or lrat_mas_thdid(3); +dbg_group0(24 to 55) <= ((24 to 55 => spr_dbg_match_64b) and spr_dbg_slowspr_data_out(0 to 31)) or + ((24 to 55 => not(spr_dbg_match_64b)) and dbg_group0a(24 to 55)); +dbg_group0(56 to 87) <= spr_dbg_slowspr_data_out(32 to 63); + + + +dbg_group1(0 to 4) <= inval_dbg_seq_q(0 to 4); +dbg_group1(5) <= inval_dbg_ex6_valid; +dbg_group1(6 to 7) <= inval_dbg_ex6_thdid(0 to 1); +dbg_group1(8 to 9) <= inval_dbg_ex6_ttype(1 to 2); +dbg_group1(10) <= htw_lsu_req_valid; +dbg_group1(11) <= mmucsr0_tlb0fi; +dbg_group1(12) <= tlbwe_back_inv_valid; +dbg_group1(13) <= inval_dbg_snoop_forme; +dbg_group1(14) <= inval_dbg_an_ac_back_inv_q(4); +dbg_group1(15) <= inval_dbg_an_ac_back_inv_q(7); +dbg_group1(16 to 50) <= inval_dbg_snoop_attr_q(0 to 34); +dbg_group1(51 to 52) <= inval_dbg_snoop_attr_tlb_spec_q(18 to 19); +dbg_group1(53 to 87) <= inval_dbg_snoop_vpn_q(17 to 51); + + +dbg_group2(0 to 4) <= inval_dbg_seq_q(0 to 4); +dbg_group2(5) <= inval_dbg_snoop_forme; +dbg_group2(6) <= inval_dbg_snoop_local_reject; +dbg_group2(7 to 13) <= inval_dbg_an_ac_back_inv_q(2 to 8); +dbg_group2(14 to 21) <= inval_dbg_an_ac_back_inv_lpar_id_q(0 to 7); +dbg_group2(22 to 63) <= inval_dbg_an_ac_back_inv_addr_q(22 to 63); +dbg_group2(64 to 66) <= inval_dbg_snoop_valid_q(0 to 2); +dbg_group2(67 to 87) <= inval_dbg_snoop_attr_q(0 to 19) & inval_dbg_snoop_attr_q(34); + + +dbg_group3(0 to 4) <= inval_dbg_seq_q(0 to 4); +dbg_group3(5) <= inval_dbg_ex6_valid; +dbg_group3(6 to 7) <= inval_dbg_ex6_thdid(0 to 1); +dbg_group3(8 to 9) <= inval_dbg_ex6_ttype(1 to 2); +dbg_group3(10) <= inval_dbg_snoop_forme; +dbg_group3(11) <= inval_dbg_an_ac_back_inv_q(7); +dbg_group3(12) <= xu_mm_lmq_stq_empty; +dbg_group3(13) <= iu_mm_lmq_empty; +dbg_group3(14 to 15) <= htw_dbg_seq_q(0 to 1); +dbg_group3(16) <= htw_lsu_req_valid; +dbg_group3(17 to 18) <= htw_dbg_lsu_thdid(0 to 1); +dbg_group3(19 to 20) <= htw_lsu_ttype(0 to 1); +dbg_group3(21) <= xu_mm_lsu_token; +dbg_group3(22) <= inval_dbg_lsu_tokens_q(1); +dbg_group3(23) <= or_reduce(mm_xu_lsu_req); +dbg_group3(24 to 25) <= mm_xu_lsu_ttype; +dbg_group3(26 to 30) <= mm_xu_lsu_wimge; +dbg_group3(31) <= mm_xu_lsu_ind; +dbg_group3(32) <= mm_xu_lsu_gs; +dbg_group3(33) <= mm_xu_lsu_lbit; +dbg_group3(34 to 37) <= mm_xu_lsu_u; +dbg_group3(38 to 45) <= mm_xu_lsu_lpid; +dbg_group3(46 to 87) <= mm_xu_lsu_addr(22 to 63); + + + +tlb_cmp_dbg_tag5_iorderat_rel_val <= or_reduce(tlb_cmp_dbg_tag5_erat_rel_val(0 to 3) or tlb_cmp_dbg_tag5_erat_rel_val(5 to 8)); +tlb_cmp_dbg_tag5_iorderat_rel_hit <= tlb_cmp_dbg_tag5_erat_rel_val(4) or tlb_cmp_dbg_tag5_erat_rel_val(9); + +dbg_group4(0 to 5) <= tlb_ctl_dbg_seq_q(0 to 5); +dbg_group4(6 to 7) <= tlb_ctl_dbg_tag0_thdid(0 to 1); +dbg_group4(8 to 10) <= tlb_ctl_dbg_tag0_type(0 to 2); +dbg_group4(11) <= tlb_ctl_dbg_any_tag_flush_sig; +dbg_group4(12 to 15) <= tlb_cmp_dbg_tag4_wayhit(0 to 3); +dbg_group4(16 to 19) <= mm_xu_eratmiss_done(0 to 3); +dbg_group4(20 to 23) <= mm_iu_barrier_done(0 to 3); +dbg_group4(24 to 27) <= mm_xu_ex3_flush_req(0 to 3); +dbg_group4(28) <= tlb_cmp_dbg_tag5_iorderat_rel_val; +dbg_group4(29) <= tlb_cmp_dbg_tag5_iorderat_rel_hit; +dbg_group4(30 to 31) <= htw_dbg_seq_q(0 to 1); +dbg_group4(32 to 34) <= htw_dbg_pte0_seq_q(0 to 2); +dbg_group4(35 to 37) <= htw_dbg_pte1_seq_q(0 to 2); +dbg_group4(38 to 42) <= inval_dbg_seq_q(0 to 4); +dbg_group4(43) <= mmucsr0_tlb0fi; +dbg_group4(44) <= inval_dbg_ex6_valid; +dbg_group4(45 to 46) <= inval_dbg_ex6_thdid(0 to 1); +dbg_group4(47 to 49) <= inval_dbg_ex6_ttype(0 to 2); +dbg_group4(50) <= inval_dbg_snoop_forme; +dbg_group4(51 to 57) <= inval_dbg_an_ac_back_inv_q(2 to 8); +dbg_group4(58) <= xu_mm_lmq_stq_empty; +dbg_group4(59) <= iu_mm_lmq_empty; +dbg_group4(60 to 63) <= mm_xu_hold_req(0 to 3); +dbg_group4(64 to 67) <= xu_mm_hold_ack(0 to 3); +dbg_group4(68 to 71) <= mm_xu_hold_done(0 to 3); +dbg_group4(72 to 74) <= inval_dbg_snoop_valid_q(0 to 2); +dbg_group4(75 to 77) <= inval_dbg_snoop_ack_q(0 to 2); +dbg_group4(78) <= or_reduce(mm_xu_lsu_req); +dbg_group4(79 to 80) <= mm_xu_lsu_ttype; +dbg_group4(81) <= or_reduce(mm_xu_illeg_instr); +dbg_group4(82 to 85) <= tlb_cmp_dbg_tag5_except_type_q(0 to 3); +dbg_group4(86 to 87) <= tlb_cmp_dbg_tag5_except_thdid_q(0 to 1); + +dbg_group5(0) <= tlb_req_dbg_ierat_iu5_valid_q; +dbg_group5(1 to 2) <= tlb_req_dbg_ierat_iu5_thdid(0 to 1); +dbg_group5(3 to 6) <= tlb_req_dbg_ierat_iu5_state_q(0 to 3); +dbg_group5(7) <= tlb_seq_ierat_req; +dbg_group5(8 to 9) <= tlb_req_dbg_ierat_inptr_q(0 to 1); +dbg_group5(10 to 11) <= tlb_req_dbg_ierat_outptr_q(0 to 1); +dbg_group5(12 to 15) <= tlb_req_dbg_ierat_req_valid_q(0 to 3); +dbg_group5(16 to 19) <= tlb_req_dbg_ierat_req_nonspec_q(0 to 3); +dbg_group5(20 to 27) <= tlb_req_dbg_ierat_req_thdid(0 to 7); +dbg_group5(28 to 31) <= tlb_req_dbg_ierat_req_dup_q(0 to 3); +dbg_group5(32) <= tlb_req_dbg_derat_ex6_valid_q; +dbg_group5(33 to 34) <= tlb_req_dbg_derat_ex6_thdid(0 to 1); +dbg_group5(35 to 38) <= tlb_req_dbg_derat_ex6_state_q(0 to 3); +dbg_group5(39) <= tlb_seq_derat_req; +dbg_group5(40 to 41) <= tlb_req_dbg_derat_inptr_q(0 to 1); +dbg_group5(42 to 43) <= tlb_req_dbg_derat_outptr_q(0 to 1); +dbg_group5(44 to 47) <= tlb_req_dbg_derat_req_valid_q(0 to 3); +dbg_group5(48 to 55) <= tlb_req_dbg_derat_req_thdid(0 to 7); +dbg_group5(56 to 63) <= tlb_req_dbg_derat_req_ttype_q(0 to 7); +dbg_group5(64 to 67) <= tlb_req_dbg_derat_req_dup_q(0 to 3); +dbg_group5(68 to 87) <= tlb_cmp_dbg_erat_dup_q(0 to 19); + + +tlb_cmp_dbg_tag4_valid <= or_reduce(tlb_cmp_dbg_tag4(tagpos_thdid to tagpos_thdid+3)); + +tlb_cmp_dbg_tag4_thdid(0) <= (tlb_cmp_dbg_tag4(tagpos_thdid+2) or tlb_cmp_dbg_tag4(tagpos_thdid+3)); +tlb_cmp_dbg_tag4_thdid(1) <= (tlb_cmp_dbg_tag4(tagpos_thdid+1) or tlb_cmp_dbg_tag4(tagpos_thdid+3)); + +tlb_cmp_dbg_tag4_type(0) <= (tlb_cmp_dbg_tag4(tagpos_type_snoop) or tlb_cmp_dbg_tag4(tagpos_type_tlbre) or + tlb_cmp_dbg_tag4(tagpos_type_tlbwe) or tlb_cmp_dbg_tag4(tagpos_type_ptereload)); +tlb_cmp_dbg_tag4_type(1) <= (tlb_cmp_dbg_tag4(tagpos_type_tlbsx) or tlb_cmp_dbg_tag4(tagpos_type_tlbsrx) or + tlb_cmp_dbg_tag4(tagpos_type_tlbwe) or tlb_cmp_dbg_tag4(tagpos_type_ptereload)); +tlb_cmp_dbg_tag4_type(2) <= (tlb_cmp_dbg_tag4(tagpos_type_ierat) or tlb_cmp_dbg_tag4(tagpos_type_tlbsrx) or + tlb_cmp_dbg_tag4(tagpos_type_tlbre) or tlb_cmp_dbg_tag4(tagpos_type_ptereload)); + +dbg_group6(0) <= tlb_cmp_dbg_tag4_valid; +dbg_group6(1 to 2) <= tlb_cmp_dbg_tag4_thdid(0 to 1); +dbg_group6(3 to 5) <= tlb_cmp_dbg_tag4_type(0 to 2); +dbg_group6(6 to 7) <= tlb_cmp_dbg_tag4(tagpos_class to tagpos_class+1); +dbg_group6(8 to 9) <= tlb_cmp_dbg_tag4(tagpos_is to tagpos_is+1); +dbg_group6(10 to 12) <= tlb_cmp_dbg_tag4(tagpos_esel to tagpos_esel+2); +dbg_group6(13) <= tlb_cmp_dbg_tag4(tagpos_cm); +dbg_group6(14) <= tlb_cmp_dbg_tag4(tagpos_pr); +dbg_group6(15) <= tlb_cmp_dbg_tag4(tagpos_ind); +dbg_group6(16) <= tlb_cmp_dbg_tag4(tagpos_endflag); +dbg_group6(17 to 23) <= tlb_cmp_dbg_addr4(0 to 6); +dbg_group6(24 to 27) <= tlb_cmp_dbg_tag4_wayhit(0 to tlb_ways-1); +dbg_group6(28) <= tlb_cmp_dbg_tag4(tagpos_gs); +dbg_group6(29 to 36) <= tlb_cmp_dbg_tag4(tagpos_lpid to tagpos_lpid+7); +dbg_group6(37) <= tlb_cmp_dbg_tag4(tagpos_as); +dbg_group6(38 to 51) <= tlb_cmp_dbg_tag4(tagpos_pid to tagpos_pid+13); +dbg_group6(52 to 87) <= tlb_cmp_dbg_tag4(tagpos_epn+16 to tagpos_epn+51); + + + +dbg_group7(0) <= tlb_cmp_dbg_tag4_valid; +dbg_group7(1 to 2) <= tlb_cmp_dbg_tag4_thdid(0 to 1); +dbg_group7(3 to 5) <= tlb_cmp_dbg_tag4_type(0 to 2); +dbg_group7(6 to 7) <= tlb_cmp_dbg_tag4(tagpos_is to tagpos_is+1); +dbg_group7(8 to 9) <= tlb_cmp_dbg_tag4(tagpos_class to tagpos_class+1); +dbg_group7(10 to 12) <= tlb_cmp_dbg_tag4(tagpos_esel to tagpos_esel+2); +dbg_group7(13 to 19) <= tlb_cmp_dbg_addr4(0 to 6); +dbg_group7(20 to 23) <= tlb_cmp_dbg_tag4_wayhit(0 to 3); + +debug_d(24 to 32) <= tlb_cmp_dbg_addr_enable(0 to 8); +debug_d(33) <= tlb_cmp_dbg_pgsize_enable; +debug_d(34) <= tlb_cmp_dbg_class_enable; +debug_d(35 to 36) <= tlb_cmp_dbg_extclass_enable(0 to 1); +debug_d(37 to 38) <= tlb_cmp_dbg_state_enable(0 to 1); +debug_d(39) <= tlb_cmp_dbg_thdid_enable; +debug_d(40) <= tlb_cmp_dbg_pid_enable; +debug_d(41) <= tlb_cmp_dbg_lpid_enable; +debug_d(42) <= tlb_cmp_dbg_ind_enable; +debug_d(43) <= tlb_cmp_dbg_iprot_enable; +debug_d(44) <= tlb_cmp_dbg_way0_entry_v; +debug_d(45) <= tlb_cmp_dbg_way0_addr_match; +debug_d(46) <= tlb_cmp_dbg_way0_pgsize_match; +debug_d(47) <= tlb_cmp_dbg_way0_class_match; +debug_d(48) <= tlb_cmp_dbg_way0_extclass_match; +debug_d(49) <= tlb_cmp_dbg_way0_state_match; +debug_d(50) <= tlb_cmp_dbg_way0_thdid_match; +debug_d(51) <= tlb_cmp_dbg_way0_pid_match; +debug_d(52) <= tlb_cmp_dbg_way0_lpid_match; +debug_d(53) <= tlb_cmp_dbg_way0_ind_match; +debug_d(54) <= tlb_cmp_dbg_way0_iprot_match; +debug_d(55) <= tlb_cmp_dbg_way1_entry_v; +debug_d(56) <= tlb_cmp_dbg_way1_addr_match; +debug_d(57) <= tlb_cmp_dbg_way1_pgsize_match; +debug_d(58) <= tlb_cmp_dbg_way1_class_match; +debug_d(59) <= tlb_cmp_dbg_way1_extclass_match; +debug_d(60) <= tlb_cmp_dbg_way1_state_match; +debug_d(61) <= tlb_cmp_dbg_way1_thdid_match; +debug_d(62) <= tlb_cmp_dbg_way1_pid_match; +debug_d(63) <= tlb_cmp_dbg_way1_lpid_match; +debug_d(64) <= tlb_cmp_dbg_way1_ind_match; +debug_d(65) <= tlb_cmp_dbg_way1_iprot_match; +debug_d(66) <= tlb_cmp_dbg_way2_entry_v; +debug_d(67) <= tlb_cmp_dbg_way2_addr_match; +debug_d(68) <= tlb_cmp_dbg_way2_pgsize_match; +debug_d(69) <= tlb_cmp_dbg_way2_class_match; +debug_d(70) <= tlb_cmp_dbg_way2_extclass_match; +debug_d(71) <= tlb_cmp_dbg_way2_state_match; +debug_d(72) <= tlb_cmp_dbg_way2_thdid_match; +debug_d(73) <= tlb_cmp_dbg_way2_pid_match; +debug_d(74) <= tlb_cmp_dbg_way2_lpid_match; +debug_d(75) <= tlb_cmp_dbg_way2_ind_match; +debug_d(76) <= tlb_cmp_dbg_way2_iprot_match; +debug_d(77) <= tlb_cmp_dbg_way3_entry_v; +debug_d(78) <= tlb_cmp_dbg_way3_addr_match; +debug_d(79) <= tlb_cmp_dbg_way3_pgsize_match; +debug_d(80) <= tlb_cmp_dbg_way3_class_match; +debug_d(81) <= tlb_cmp_dbg_way3_extclass_match; +debug_d(82) <= tlb_cmp_dbg_way3_state_match; +debug_d(83) <= tlb_cmp_dbg_way3_thdid_match; +debug_d(84) <= tlb_cmp_dbg_way3_pid_match; +debug_d(85) <= tlb_cmp_dbg_way3_lpid_match; +debug_d(86) <= tlb_cmp_dbg_way3_ind_match; +debug_d(87) <= tlb_cmp_dbg_way3_iprot_match; + +dbg_group7(24 to 87) <= debug_q(24 to 87); + + +dbg_group8(0) <= tlb_cmp_dbg_tag4_valid; +dbg_group8(1 to 2) <= tlb_cmp_dbg_tag4_thdid(0 to 1); +dbg_group8(3 to 5) <= tlb_cmp_dbg_tag4_type(0 to 2); +dbg_group8(6 to 7) <= tlb_cmp_dbg_tag4(tagpos_class to tagpos_class+1); +dbg_group8(8) <= tlb_cmp_dbg_tag4(tagpos_cm); +dbg_group8(9) <= tlb_cmp_dbg_tag4(tagpos_gs); +dbg_group8(10) <= tlb_cmp_dbg_tag4(tagpos_pr); +dbg_group8(11) <= tlb_cmp_dbg_tag4(tagpos_endflag); +dbg_group8(12) <= tlb_cmp_dbg_tag4(tagpos_atsel); +dbg_group8(13 to 15) <= tlb_cmp_dbg_tag4(tagpos_esel to tagpos_esel+2); +dbg_group8(16 to 19) <= tlb_cmp_dbg_tag4(tagpos_size to tagpos_size+3); +dbg_group8(20 to 33) <= tlb_cmp_dbg_tag4(tagpos_pid to tagpos_pid+13); +dbg_group8(34 to 58) <= tlb_cmp_dbg_tag4(tagpos_epn+27 to tagpos_epn+51); +dbg_group8(59 to 65) <= tlb_cmp_dbg_addr4(0 to 6); +dbg_group8(66 to 69) <= tlb_cmp_dbg_tag4_wayhit(0 to tlb_ways-1); +dbg_group8(70) <= tlb_mas_dtlb_error; +dbg_group8(71) <= tlb_mas_itlb_error; +dbg_group8(72) <= tlb_mas_tlbsx_hit; +dbg_group8(73) <= tlb_mas_tlbsx_miss; +dbg_group8(74) <= tlb_mas_tlbre; +dbg_group8(75) <= lrat_mas_tlbre; +dbg_group8(76) <= lrat_mas_tlbsx_hit; +dbg_group8(77 ) <= lrat_mas_tlbsx_miss; +dbg_group8(78 to 80) <= lrat_tag4_hit_entry(0 to 2); +dbg_group8(81 to 85) <= tlb_cmp_dbg_tag4_parerr(0 to 4); +dbg_group8(86) <= or_reduce(mm_xu_cr0_eq_valid); +dbg_group8(87) <= or_reduce(mm_xu_cr0_eq and mm_xu_cr0_eq_valid); + + +dbg_group9(0) <= tlb_cmp_dbg_tag4_valid; +dbg_group9(1 to 2) <= tlb_cmp_dbg_tag4_thdid(0 to 1); +dbg_group9(3 to 5) <= tlb_cmp_dbg_tag4_type(0 to 2); +dbg_group9(6) <= tlb_cmp_dbg_tag4(tagpos_gs); +dbg_group9(7) <= tlb_cmp_dbg_tag4(tagpos_pr); +dbg_group9(8) <= tlb_cmp_dbg_tag4(tagpos_cm); +dbg_group9(9) <= tlb_cmp_dbg_tag4(tagpos_hes); +dbg_group9(10 to 11) <= tlb_cmp_dbg_tag4(tagpos_wq to tagpos_wq+1); +dbg_group9(12) <= tlb_cmp_dbg_tag4(tagpos_atsel); +dbg_group9(13 to 15) <= tlb_cmp_dbg_tag4(tagpos_esel to tagpos_esel+2); +dbg_group9(16 to 17) <= tlb_cmp_dbg_tag4(tagpos_is to tagpos_is+1); +dbg_group9(18) <= tlb_cmp_dbg_tag4(tagpos_pt); +dbg_group9(19) <= tlb_cmp_dbg_tag4(tagpos_recform); +dbg_group9(20) <= tlb_cmp_dbg_tag4(tagpos_ind); +dbg_group9(21 to 27) <= tlb_cmp_dbg_addr4(0 to 6); +dbg_group9(28 to 31) <= tlb_cmp_dbg_tag4_wayhit(0 to tlb_ways-1); +dbg_group9(32 to 43) <= tlb_cmp_dbg_tag4_lru_dataout_q(0 to 11); +dbg_group9(44 to 47) <= lrat_tag4_hit_status(0 to 3); +dbg_group9(48 to 50) <= lrat_tag4_hit_entry(0 to 2); +dbg_group9(51) <= or_reduce(mm_iu_barrier_done); +dbg_group9(52 to 55) <= tlb_ctl_dbg_resv_valid(0 to 3); +dbg_group9(56 to 59) <= tlb_ctl_dbg_resv_match_vec_q(0 to 3); +dbg_group9(60 to 63) <= tlb_ctl_dbg_tag5_tlb_write_q(0 to 3); +dbg_group9(64 to 75) <= tlb_cmp_dbg_tag5_lru_datain_q(0 to 11); +dbg_group9(76) <= tlb_cmp_dbg_tag5_lru_write; +dbg_group9(77) <= or_reduce(mm_xu_illeg_instr); +dbg_group9(78 to 81) <= tlb_cmp_dbg_tag5_except_type_q(0 to 3); +dbg_group9(82 to 83) <= tlb_cmp_dbg_tag5_except_thdid_q(0 to 1); +dbg_group9(84) <= tlbwe_back_inv_valid; +dbg_group9(85) <= tlbwe_back_inv_attr(18); +dbg_group9(86) <= tlbwe_back_inv_attr(19); +dbg_group9(87) <= '0'; + + + +debug_d(0 to 1) <= tlb_cmp_dbg_tag4_thdid; +debug_d(2 to 4) <= tlb_cmp_dbg_tag4_type; +debug_d(5 to 6) <= tlb_cmp_dbg_tag4(tagpos_class to tagpos_class+1); +debug_d(7 to 11) <= tlb_cmp_dbg_tag4_wayhit(0 to tlb_ways); + +tlb_cmp_dbg_tag5_thdid(0 to 1) <= debug_q(0 to 1); +tlb_cmp_dbg_tag5_type(0 to 2) <= debug_q(2 to 4); +tlb_cmp_dbg_tag5_class(0 to 1) <= debug_q(5 to 6); +tlb_cmp_dbg_tag5_wayhit(0 to 4) <= debug_q(7 to 11); + + +dbg_group10a(0) <= tlb_cmp_dbg_tag5_iorderat_rel_val; +dbg_group10a(1 to 2) <= tlb_cmp_dbg_tag5_thdid(0 to 1); +dbg_group10a(3 to 5) <= tlb_cmp_dbg_tag5_type(0 to 2); +dbg_group10a(6 to 7) <= tlb_cmp_dbg_tag5_class(0 to 1); +dbg_group10a(8 to 11) <= tlb_cmp_dbg_tag5_wayhit(0 to tlb_ways-1); +dbg_group10a(12 to 21) <= tlb_cmp_dbg_tag5_erat_rel_val(0 to 9); +dbg_group10a(22 to 87) <= tlb_cmp_dbg_tag5_erat_rel_data(eratpos_epn to eratpos_wren); + +dbg_group10b(0 to 83) <= tlb_cmp_dbg_tag5_tlb_datain_q(0 to 83); +dbg_group10b(84) <= Eq(tlb_cmp_dbg_tag5_type(0 to 2),"110") and or_reduce(tlb_ctl_dbg_tag5_tlb_write_q); +dbg_group10b(85) <= Eq(tlb_cmp_dbg_tag5_type(0 to 2),"111") and or_reduce(tlb_ctl_dbg_tag5_tlb_write_q); +dbg_group10b(86) <= (tlb_ctl_dbg_tag5_tlb_write_q(2) or tlb_ctl_dbg_tag5_tlb_write_q(3)); +dbg_group10b(87) <= (tlb_ctl_dbg_tag5_tlb_write_q(1) or tlb_ctl_dbg_tag5_tlb_write_q(3)); + +dbg_group10 <= dbg_group10b when mmucr2(8)='1' else dbg_group10a; + + +dbg_group11a(0) <= tlb_cmp_dbg_tag5_iorderat_rel_val; +dbg_group11a(1 to 2) <= tlb_cmp_dbg_tag5_thdid(0 to 1); +dbg_group11a(3 to 5) <= tlb_cmp_dbg_tag5_type(0 to 2); +dbg_group11a(6 to 7) <= tlb_cmp_dbg_tag5_class(0 to 1); +dbg_group11a(8 to 11) <= tlb_cmp_dbg_tag5_wayhit(0 to tlb_ways-1); +dbg_group11a(12 to 21) <= tlb_cmp_dbg_tag5_erat_rel_val(0 to 9); +dbg_group11a(22 to 87) <= tlb_cmp_dbg_tag5_erat_rel_data(eratpos_rpnrsvd to eratpos_tid+7); + +dbg_group11b(0 to 83) <= tlb_cmp_dbg_tag5_tlb_datain_q(84 to 167); +dbg_group11b(84) <= Eq(tlb_cmp_dbg_tag5_type(0 to 2),"110") and or_reduce(tlb_ctl_dbg_tag5_tlb_write_q); +dbg_group11b(85) <= Eq(tlb_cmp_dbg_tag5_type(0 to 2),"111") and or_reduce(tlb_ctl_dbg_tag5_tlb_write_q); +dbg_group11b(86) <= (tlb_ctl_dbg_tag5_tlb_write_q(2) or tlb_ctl_dbg_tag5_tlb_write_q(3)); +dbg_group11b(87) <= (tlb_ctl_dbg_tag5_tlb_write_q(1) or tlb_ctl_dbg_tag5_tlb_write_q(3)); + +dbg_group11 <= dbg_group11b when mmucr2(8)='1' else dbg_group11a; + +dbg_group12a(0) <= tlb_ctl_dbg_tag1_valid; +dbg_group12a(1 to 2) <= tlb_ctl_dbg_tag1_thdid(0 to 1); +dbg_group12a(3 to 5) <= tlb_ctl_dbg_tag1_type(0 to 2); +dbg_group12a(6 to 7) <= tlb_ctl_dbg_tag1_wq(0 to 1); + +dbg_group12a(8 to 11) <= tlb_ctl_dbg_resv_valid(0 to 3); +dbg_group12a(12 to 15) <= tlb_ctl_dbg_set_resv(0 to 3); +dbg_group12a(16 to 19) <= tlb_ctl_dbg_resv_match_vec_q(0 to 3); + +debug_d(group12_offset+20) <= tlb_ctl_dbg_resv0_tag0_lpid_match; +debug_d(group12_offset+21) <= tlb_ctl_dbg_resv0_tag0_pid_match; +debug_d(group12_offset+22) <= tlb_ctl_dbg_resv0_tag0_as_snoop_match; +debug_d(group12_offset+23) <= tlb_ctl_dbg_resv0_tag0_gs_snoop_match; +debug_d(group12_offset+24) <= tlb_ctl_dbg_resv0_tag0_as_tlbwe_match; +debug_d(group12_offset+25) <= tlb_ctl_dbg_resv0_tag0_gs_tlbwe_match; +debug_d(group12_offset+26) <= tlb_ctl_dbg_resv0_tag0_ind_match; +debug_d(group12_offset+27) <= tlb_ctl_dbg_resv0_tag0_epn_loc_match; +debug_d(group12_offset+28) <= tlb_ctl_dbg_resv0_tag0_epn_glob_match; +debug_d(group12_offset+29) <= tlb_ctl_dbg_resv0_tag0_class_match; +debug_d(group12_offset+30) <= tlb_ctl_dbg_resv1_tag0_lpid_match; +debug_d(group12_offset+31) <= tlb_ctl_dbg_resv1_tag0_pid_match; +debug_d(group12_offset+32) <= tlb_ctl_dbg_resv1_tag0_as_snoop_match; +debug_d(group12_offset+33) <= tlb_ctl_dbg_resv1_tag0_gs_snoop_match; +debug_d(group12_offset+34) <= tlb_ctl_dbg_resv1_tag0_as_tlbwe_match; +debug_d(group12_offset+35) <= tlb_ctl_dbg_resv1_tag0_gs_tlbwe_match; +debug_d(group12_offset+36) <= tlb_ctl_dbg_resv1_tag0_ind_match; +debug_d(group12_offset+37) <= tlb_ctl_dbg_resv1_tag0_epn_loc_match; +debug_d(group12_offset+38) <= tlb_ctl_dbg_resv1_tag0_epn_glob_match; +debug_d(group12_offset+39) <= tlb_ctl_dbg_resv1_tag0_class_match; +debug_d(group12_offset+40) <= tlb_ctl_dbg_resv2_tag0_lpid_match; +debug_d(group12_offset+41) <= tlb_ctl_dbg_resv2_tag0_pid_match; +debug_d(group12_offset+42) <= tlb_ctl_dbg_resv2_tag0_as_snoop_match; +debug_d(group12_offset+43) <= tlb_ctl_dbg_resv2_tag0_gs_snoop_match; +debug_d(group12_offset+44) <= tlb_ctl_dbg_resv2_tag0_as_tlbwe_match; +debug_d(group12_offset+45) <= tlb_ctl_dbg_resv2_tag0_gs_tlbwe_match; +debug_d(group12_offset+46) <= tlb_ctl_dbg_resv2_tag0_ind_match; +debug_d(group12_offset+47) <= tlb_ctl_dbg_resv2_tag0_epn_loc_match; +debug_d(group12_offset+48) <= tlb_ctl_dbg_resv2_tag0_epn_glob_match; +debug_d(group12_offset+49) <= tlb_ctl_dbg_resv2_tag0_class_match; +debug_d(group12_offset+50) <= tlb_ctl_dbg_resv3_tag0_lpid_match; +debug_d(group12_offset+51) <= tlb_ctl_dbg_resv3_tag0_pid_match; +debug_d(group12_offset+52) <= tlb_ctl_dbg_resv3_tag0_as_snoop_match; +debug_d(group12_offset+53) <= tlb_ctl_dbg_resv3_tag0_gs_snoop_match; +debug_d(group12_offset+54) <= tlb_ctl_dbg_resv3_tag0_as_tlbwe_match; +debug_d(group12_offset+55) <= tlb_ctl_dbg_resv3_tag0_gs_tlbwe_match; +debug_d(group12_offset+56) <= tlb_ctl_dbg_resv3_tag0_ind_match; +debug_d(group12_offset+57) <= tlb_ctl_dbg_resv3_tag0_epn_loc_match; +debug_d(group12_offset+58) <= tlb_ctl_dbg_resv3_tag0_epn_glob_match; +debug_d(group12_offset+59) <= tlb_ctl_dbg_resv3_tag0_class_match; + +dbg_group12a(20 to 59) <= debug_q(group12_offset+20 to group12_offset+59); + +dbg_group12a(60 to 63) <= tlb_ctl_dbg_clr_resv_q(0 to 3); +dbg_group12a(64 to 67) <= tlb_ctl_dbg_clr_resv_terms(0 to 3); + +dbg_group12a(68 to 71) <= htw_dbg_req_valid_q(0 to 3); +dbg_group12a(72 to 75) <= htw_dbg_resv_valid_vec(0 to 3); +dbg_group12a(76 to 79) <= htw_dbg_tag4_clr_resv_q(0 to 3); +dbg_group12a(80 to 83) <= htw_dbg_tag4_clr_resv_terms(0 to 3); +dbg_group12a(84 to 87) <= "0000"; + +dbg_group12b(0 to 83) <= tlb_cmp_dbg_tag5_way(0 to 83); +dbg_group12b(84) <= (tlb_cmp_dbg_tag5_lru_dataout(0) and tlb_cmp_dbg_tag5_wayhit(0)) or + (tlb_cmp_dbg_tag5_lru_dataout(1) and tlb_cmp_dbg_tag5_wayhit(1)) or + (tlb_cmp_dbg_tag5_lru_dataout(2) and tlb_cmp_dbg_tag5_wayhit(2)) or + (tlb_cmp_dbg_tag5_lru_dataout(3) and tlb_cmp_dbg_tag5_wayhit(3)); +dbg_group12b(85) <= (tlb_cmp_dbg_tag5_lru_dataout(8) and tlb_cmp_dbg_tag5_wayhit(0)) or + (tlb_cmp_dbg_tag5_lru_dataout(9) and tlb_cmp_dbg_tag5_wayhit(1)) or + (tlb_cmp_dbg_tag5_lru_dataout(10) and tlb_cmp_dbg_tag5_wayhit(2)) or + (tlb_cmp_dbg_tag5_lru_dataout(11) and tlb_cmp_dbg_tag5_wayhit(3)); +dbg_group12b(86) <= tlb_cmp_dbg_tag5_lru_dataout(4); +dbg_group12b(87) <= (not(tlb_cmp_dbg_tag5_lru_dataout(4)) and tlb_cmp_dbg_tag5_lru_dataout(5)) or + (tlb_cmp_dbg_tag5_lru_dataout(4) and tlb_cmp_dbg_tag5_lru_dataout(6)); + +dbg_group12 <= dbg_group12b when mmucr2(9)='1' else dbg_group12a; + + + +dbg_group13a(0) <= lrat_dbg_tag1_addr_enable; +dbg_group13a(1) <= tlb_ctl_dbg_tag1_valid; +dbg_group13a(2 to 3) <= tlb_ctl_dbg_tag1_thdid(0 to 1); +dbg_group13a(4 to 5) <= (tlb_ctl_dbg_tag1_type(0) and tlb_ctl_dbg_tag1_type(1)) & (tlb_ctl_dbg_tag1_type(0) and tlb_ctl_dbg_tag1_type(2)); +dbg_group13a(6) <= tlb_ctl_dbg_tag1_gs; +dbg_group13a(7) <= tlb_ctl_dbg_tag1_pr; +dbg_group13a(8) <= tlb_ctl_dbg_tag1_atsel; +dbg_group13a(9 to 11) <= lrat_tag3_hit_entry(0 to 2); +dbg_group13a(12 to 15) <= lrat_tag3_hit_status(0 to 3); + +debug_d(group13_offset+16) <= lrat_dbg_entry0_addr_match; +debug_d(group13_offset+17) <= lrat_dbg_entry0_lpid_match; +debug_d(group13_offset+18) <= lrat_dbg_entry0_entry_v; +debug_d(group13_offset+19) <= lrat_dbg_entry0_entry_x; +debug_d(group13_offset+20 to group13_offset+23) <= lrat_dbg_entry0_size(0 to 3); +debug_d(group13_offset+24) <= lrat_dbg_entry1_addr_match; +debug_d(group13_offset+25) <= lrat_dbg_entry1_lpid_match; +debug_d(group13_offset+26) <= lrat_dbg_entry1_entry_v; +debug_d(group13_offset+27) <= lrat_dbg_entry1_entry_x; +debug_d(group13_offset+28 to group13_offset+31) <= lrat_dbg_entry1_size(0 to 3); +debug_d(group13_offset+32) <= lrat_dbg_entry2_addr_match; +debug_d(group13_offset+33) <= lrat_dbg_entry2_lpid_match; +debug_d(group13_offset+34) <= lrat_dbg_entry2_entry_v; +debug_d(group13_offset+35) <= lrat_dbg_entry2_entry_x; +debug_d(group13_offset+36 to group13_offset+39) <= lrat_dbg_entry2_size(0 to 3); +debug_d(group13_offset+40) <= lrat_dbg_entry3_addr_match; +debug_d(group13_offset+41) <= lrat_dbg_entry3_lpid_match; +debug_d(group13_offset+42) <= lrat_dbg_entry3_entry_v; +debug_d(group13_offset+43) <= lrat_dbg_entry3_entry_x; +debug_d(group13_offset+44 to group13_offset+47) <= lrat_dbg_entry3_size(0 to 3); +debug_d(group13_offset+48) <= lrat_dbg_entry4_addr_match ; +debug_d(group13_offset+49) <= lrat_dbg_entry4_lpid_match; +debug_d(group13_offset+50) <= lrat_dbg_entry4_entry_v; +debug_d(group13_offset+51) <= lrat_dbg_entry4_entry_x; +debug_d(group13_offset+52 to group13_offset+55) <= lrat_dbg_entry4_size(0 to 3); +debug_d(group13_offset+56) <= lrat_dbg_entry5_addr_match ; +debug_d(group13_offset+57) <= lrat_dbg_entry5_lpid_match; +debug_d(group13_offset+58) <= lrat_dbg_entry5_entry_v; +debug_d(group13_offset+59) <= lrat_dbg_entry5_entry_x; +debug_d(group13_offset+60 to group13_offset+63) <= lrat_dbg_entry5_size(0 to 3); +debug_d(group13_offset+64) <= lrat_dbg_entry6_addr_match; +debug_d(group13_offset+65) <= lrat_dbg_entry6_lpid_match; +debug_d(group13_offset+66) <= lrat_dbg_entry6_entry_v; +debug_d(group13_offset+67) <= lrat_dbg_entry6_entry_x; +debug_d(group13_offset+68 to group13_offset+71) <= lrat_dbg_entry6_size(0 to 3); +debug_d(group13_offset+72) <= lrat_dbg_entry7_addr_match; +debug_d(group13_offset+73) <= lrat_dbg_entry7_lpid_match; +debug_d(group13_offset+74) <= lrat_dbg_entry7_entry_v; +debug_d(group13_offset+75) <= lrat_dbg_entry7_entry_x; +debug_d(group13_offset+76 to group13_offset+79) <= lrat_dbg_entry7_size(0 to 3); + +dbg_group13a(16 to 79) <= debug_q(group13_offset+16 to group13_offset+79); +dbg_group13a(80 to 87) <= lrat_dbg_tag2_matchline_q(0 to 7); + +dbg_group13b(0 to 83) <= tlb_cmp_dbg_tag5_way(84 to 167); +dbg_group13b(84) <= (tlb_cmp_dbg_tag5_lru_dataout(0) and tlb_cmp_dbg_tag5_wayhit(0)) or + (tlb_cmp_dbg_tag5_lru_dataout(1) and tlb_cmp_dbg_tag5_wayhit(1)) or + (tlb_cmp_dbg_tag5_lru_dataout(2) and tlb_cmp_dbg_tag5_wayhit(2)) or + (tlb_cmp_dbg_tag5_lru_dataout(3) and tlb_cmp_dbg_tag5_wayhit(3)); +dbg_group13b(85) <= (tlb_cmp_dbg_tag5_lru_dataout(8) and tlb_cmp_dbg_tag5_wayhit(0)) or + (tlb_cmp_dbg_tag5_lru_dataout(9) and tlb_cmp_dbg_tag5_wayhit(1)) or + (tlb_cmp_dbg_tag5_lru_dataout(10) and tlb_cmp_dbg_tag5_wayhit(2)) or + (tlb_cmp_dbg_tag5_lru_dataout(11) and tlb_cmp_dbg_tag5_wayhit(3)); +dbg_group13b(86) <= tlb_cmp_dbg_tag5_lru_dataout(4); +dbg_group13b(87) <= (not(tlb_cmp_dbg_tag5_lru_dataout(4)) and tlb_cmp_dbg_tag5_lru_dataout(5)) or + (tlb_cmp_dbg_tag5_lru_dataout(4) and tlb_cmp_dbg_tag5_lru_dataout(6)); + + +dbg_group13 <= dbg_group13b when mmucr2(9)='1' else dbg_group13a; + + +dbg_group14a(0 to 1) <= htw_dbg_seq_q(0 to 1); +dbg_group14a(2 to 3) <= htw_dbg_inptr_q(0 to 1); +dbg_group14a(4) <= htw_dbg_ptereload_ptr_q; +dbg_group14a(5 to 6) <= htw_dbg_lsuptr_q(0 to 1); +dbg_group14a(7) <= htw_lsu_ttype(1); +dbg_group14a(8 to 9) <= htw_dbg_lsu_thdid(0 to 1); +dbg_group14a(10 to 51) <= htw_lsu_addr(22 to 63); +dbg_group14a(52 to 54) <= htw_dbg_pte0_seq_q(0 to 2); +dbg_group14a(55 to 56) <= htw_dbg_pte0_score_ptr_q(0 to 1); +dbg_group14a(57 to 59) <= htw_dbg_pte0_score_cl_offset_q(58 to 60); +dbg_group14a(60 to 62) <= htw_dbg_pte0_score_error_q(0 to 2); +dbg_group14a(63 to 66) <= htw_dbg_pte0_score_qwbeat_q(0 to 3); +dbg_group14a(67) <= htw_dbg_pte0_score_pending_q; +dbg_group14a(68) <= htw_dbg_pte0_score_ibit_q; +dbg_group14a(69) <= htw_dbg_pte0_score_dataval_q; +dbg_group14a(70 to 72) <= htw_dbg_pte1_seq_q(0 to 2); +dbg_group14a(73 to 74) <= htw_dbg_pte1_score_ptr_q(0 to 1); +dbg_group14a(75 to 77) <= htw_dbg_pte1_score_cl_offset_q(58 to 60); +dbg_group14a(78 to 80) <= htw_dbg_pte1_score_error_q(0 to 2); +dbg_group14a(81 to 84) <= htw_dbg_pte1_score_qwbeat_q(0 to 3); +dbg_group14a(85) <= htw_dbg_pte1_score_pending_q; +dbg_group14a(86) <= htw_dbg_pte1_score_ibit_q; +dbg_group14a(87) <= htw_dbg_pte1_score_dataval_q; + + +dbg_group14b(0) <= (tlb_cmp_dbg_tag5_lru_dataout(0) and tlb_cmp_dbg_tag5_wayhit(0)) or + (tlb_cmp_dbg_tag5_lru_dataout(1) and tlb_cmp_dbg_tag5_wayhit(1)) or + (tlb_cmp_dbg_tag5_lru_dataout(2) and tlb_cmp_dbg_tag5_wayhit(2)) or + (tlb_cmp_dbg_tag5_lru_dataout(3) and tlb_cmp_dbg_tag5_wayhit(3)); +dbg_group14b(1) <= (tlb_cmp_dbg_tag5_lru_dataout(8) and tlb_cmp_dbg_tag5_wayhit(0)) or + (tlb_cmp_dbg_tag5_lru_dataout(9) and tlb_cmp_dbg_tag5_wayhit(1)) or + (tlb_cmp_dbg_tag5_lru_dataout(10) and tlb_cmp_dbg_tag5_wayhit(2)) or + (tlb_cmp_dbg_tag5_lru_dataout(11) and tlb_cmp_dbg_tag5_wayhit(3)); + +dbg_group14b(2) <= tlb_cmp_dbg_tag5_way(140); +dbg_group14b(3) <= tlb_cmp_dbg_tag5_way(141); +dbg_group14b(4 to 11) <= tlb_cmp_dbg_tag5_way(66 to 73); +dbg_group14b(12 to 25) <= tlb_cmp_dbg_tag5_way(144 to 157); +dbg_group14b(26 to 45) <= tlb_cmp_dbg_tag5_way(32 to 51); +dbg_group14b(46 to 49) <= tlb_cmp_dbg_tag5_way(52 to 55); +dbg_group14b(50 to 53) <= tlb_cmp_dbg_tag5_way(56 to 59); +dbg_group14b(54) <= tlb_cmp_dbg_tag5_way(84); +dbg_group14b(55) <= tlb_cmp_dbg_tag5_way(40); +dbg_group14b(56 to 57) <= tlb_cmp_dbg_tag5_way(60 to 61); +dbg_group14b(58 to 77) <= tlb_cmp_dbg_tag5_way(98 to 117); +dbg_group14b(78 to 81) <= tlb_cmp_dbg_tag5_way(130 to 133); +dbg_group14b(82 to 87) <= tlb_cmp_dbg_tag5_way(134 to 139); + +dbg_group14 <= dbg_group14b when mmucr2(10)='1' else dbg_group14a; + +dbg_group15a(0 to 1) <= htw_dbg_seq_q(0 to 1); +dbg_group15a(2 to 4) <= htw_dbg_pte0_seq_q(0 to 2); +dbg_group15a(5 to 7) <= htw_dbg_pte1_seq_q(0 to 2); +dbg_group15a(8) <= htw_lsu_req_valid; +dbg_group15a(9 to 21) <= htw_lsu_addr(48 to 60); +dbg_group15a(22) <= htw_dbg_ptereload_ptr_q; +dbg_group15a(23) <= ptereload_req_taken; +dbg_group15a(24 to 87) <= ptereload_req_pte(0 to 63); + + +dbg_group15b(0 to 73) <= tlb_cmp_dbg_tag5_way(0 to 73); +dbg_group15b(74 to 77) <= tlb_cmp_dbg_tag5_lru_dataout(0 to 3); +dbg_group15b(78 to 81) <= tlb_cmp_dbg_tag5_lru_dataout(8 to 11); +dbg_group15b(82) <= tlb_cmp_dbg_tag5_lru_dataout(4); +dbg_group15b(83) <= (not(tlb_cmp_dbg_tag5_lru_dataout(4)) and tlb_cmp_dbg_tag5_lru_dataout(5)) or + (tlb_cmp_dbg_tag5_lru_dataout(4) and tlb_cmp_dbg_tag5_lru_dataout(6)); +dbg_group15b(84 to 87) <= tlb_cmp_dbg_tag5_wayhit(0 to 3); + +dbg_group15 <= dbg_group15b when mmucr2(10)='1' else dbg_group15a; + + +trg_group0(0) <= not(tlb_ctl_dbg_seq_idle); +trg_group0(1 to 2) <= tlb_ctl_dbg_tag0_thdid(0 to 1); +trg_group0(3 to 5) <= tlb_ctl_dbg_tag0_type(0 to 2); +trg_group0(6) <= not(inval_dbg_seq_idle); +trg_group0(7) <= inval_dbg_seq_snoop_inprogress; +trg_group0(8) <= not(htw_dbg_seq_idle); +trg_group0(9) <= not(htw_dbg_pte0_seq_idle); +trg_group0(10) <= not(htw_dbg_pte1_seq_idle); +trg_group0(11) <= tlb_cmp_dbg_tag5_any_exception; + + +trg_group1(0 to 5) <= tlb_ctl_dbg_seq_q(0 to 5); +trg_group1(6 to 10) <= inval_dbg_seq_q(0 to 4); +trg_group1(11) <= tlb_ctl_dbg_seq_any_done_sig or tlb_ctl_dbg_seq_abort or inval_dbg_seq_snoop_done or inval_dbg_seq_local_done or inval_dbg_seq_tlb0fi_done or inval_dbg_seq_tlbwe_snoop_done; + + +trg_group2(0) <= tlb_req_dbg_ierat_iu5_valid_q; +trg_group2(1) <= tlb_req_dbg_derat_ex6_valid_q; +trg_group2(2) <= tlb_ctl_dbg_any_tlb_req_sig; +trg_group2(3) <= tlb_ctl_dbg_any_req_taken_sig; +trg_group2(4) <= tlb_ctl_dbg_seq_any_done_sig or tlb_ctl_dbg_seq_abort; +trg_group2(5) <= inval_dbg_ex6_valid; +trg_group2(6) <= mmucsr0_tlb0fi; +trg_group2(7) <= inval_dbg_snoop_forme; +trg_group2(8) <= tlbwe_back_inv_valid; +trg_group2(9) <= htw_lsu_req_valid; +trg_group2(10) <= inval_dbg_seq_snoop_done or inval_dbg_seq_local_done or inval_dbg_seq_tlb0fi_done or inval_dbg_seq_tlbwe_snoop_done; +trg_group2(11) <= or_reduce(mm_xu_lsu_req); + + +trg_group3a(0) <= spr_dbg_slowspr_val_int; +trg_group3a(1) <= spr_dbg_slowspr_rw_int; +trg_group3a(2 to 3) <= spr_dbg_slowspr_etid_int; +trg_group3a(4) <= spr_dbg_match_64b; +trg_group3a(5) <= spr_dbg_match_any_mmu; +trg_group3a(6) <= spr_dbg_match_any_mas; +trg_group3a(7) <= spr_dbg_match_mmucr0 or spr_dbg_match_mmucr1 or spr_dbg_match_mmucr2 or spr_dbg_match_mmucr3; +trg_group3a(8) <= spr_dbg_match_pid or spr_dbg_match_lpidr; +trg_group3a(9) <= spr_dbg_match_lper or spr_dbg_match_lperu; +trg_group3a(10) <= spr_dbg_slowspr_val_out; +trg_group3a(11) <= spr_dbg_slowspr_done_out; + +trg_group3b(0) <= tlb_htw_req_valid; +trg_group3b(1 to 2) <= htw_dbg_seq_q(0 to 1); +trg_group3b(3 to 5) <= htw_dbg_pte0_seq_q(0 to 2); +trg_group3b(6 to 8) <= htw_dbg_pte1_seq_q(0 to 2); +trg_group3b(9) <= htw_dbg_pte0_reld_for_me_tm1 or htw_dbg_pte1_reld_for_me_tm1; +trg_group3b(10) <= or_reduce(htw_dbg_pte0_score_error_q or htw_dbg_pte1_score_error_q); +trg_group3b(11) <= tlb_cmp_dbg_tag5_any_exception; + +trg_group3 <= trg_group3b when mmucr2(11)='1' else trg_group3a; + + + +dbg_mux0: entity clib.c_debug_mux16 + port map( + vd => vdd, + gd => gnd, + + select_bits => pc_mm_debug_mux1_ctrls_loc_q, + trace_data_in => debug_bus_in_q, + trigger_data_in => trace_triggers_in_q, + + dbg_group0 => dbg_group0, + dbg_group1 => dbg_group1, + dbg_group2 => dbg_group2, + dbg_group3 => dbg_group3, + dbg_group4 => dbg_group4, + dbg_group5 => dbg_group5, + dbg_group6 => dbg_group6, + dbg_group7 => dbg_group7, + dbg_group8 => dbg_group8, + dbg_group9 => dbg_group9, + dbg_group10 => dbg_group10, + dbg_group11 => dbg_group11, + dbg_group12 => dbg_group12, + dbg_group13 => dbg_group13, + dbg_group14 => dbg_group14, + dbg_group15 => dbg_group15, + + trg_group0 => trg_group0, + trg_group1 => trg_group1, + trg_group2 => trg_group2, + trg_group3 => trg_group3, + + trace_data_out => trace_data_out_d, + trigger_data_out => trigger_data_out_d +); + +trace_triggers_out <= trigger_data_out_q; +debug_bus_out <= trace_data_out_q; +debug_bus_out_int <= trace_data_out_int_q; + + +unused_dc(0) <= TLB_MAS_THDID(0); +unused_dc(1) <= LRAT_MAS_THDID(0); +unused_dc(2) <= LRAT_MAS_THDID(0); +unused_dc(3) <= INVAL_DBG_LSU_TOKENS_Q(0); +unused_dc(4) <= TLB_CMP_DBG_TAG4(82); +unused_dc(5) <= TLB_CMP_DBG_TAG4(106); + +unused_dc(6) <= or_reduce(TLB_CMP_DBG_TAG4(0 TO 7)); +unused_dc(7) <= or_reduce(TLB_CMP_DBG_TAG4(8 TO 15)); +unused_dc(8) <= TLB_CMP_DBG_TAG5_WAYHIT(4); + +unused_dc(9) <= DEBUG_Q(23); +unused_dc(10) <= or_reduce(TRIGGER_Q(0 to 47)); +unused_dc(11) <= tlb_cmp_dbg_tag5_lru_dataout(7); + + + +trace_bus_enable_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => pc_func_slp_sl_force, + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + scin => siv(trace_bus_enable_offset), + scout => sov(trace_bus_enable_offset), + din => pc_mm_trace_bus_enable, + dout => pc_mm_trace_bus_enable_q); +debug_mux1_ctrls_latch : tri_rlmreg_p + generic map (width => pc_mm_debug_mux1_ctrls_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => pc_mm_trace_bus_enable_q, + forcee => pc_func_slp_sl_force, + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + scin => siv(debug_mux1_ctrls_offset to debug_mux1_ctrls_offset + pc_mm_debug_mux1_ctrls_q'length-1), + scout => sov(debug_mux1_ctrls_offset to debug_mux1_ctrls_offset + pc_mm_debug_mux1_ctrls_q'length-1), + din => pc_mm_debug_mux1_ctrls, + dout => pc_mm_debug_mux1_ctrls_q); +debug_mux1_ctrls_loc_latch : tri_rlmreg_p + generic map (width => pc_mm_debug_mux1_ctrls_loc_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => pc_mm_trace_bus_enable_q, + forcee => pc_func_slp_sl_force, + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + scin => siv(debug_mux1_ctrls_loc_offset to debug_mux1_ctrls_loc_offset + pc_mm_debug_mux1_ctrls_loc_q'length-1), + scout => sov(debug_mux1_ctrls_loc_offset to debug_mux1_ctrls_loc_offset + pc_mm_debug_mux1_ctrls_loc_q'length-1), + din => pc_mm_debug_mux1_ctrls_loc_d, + dout => pc_mm_debug_mux1_ctrls_loc_q); +trigger_data_latch: tri_rlmreg_p + generic map (width => trigger_data_out_q'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => pc_mm_trace_bus_enable_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(trigger_data_out_offset to trigger_data_out_offset + trigger_data_out_q'length-1), + scout => sov(trigger_data_out_offset to trigger_data_out_offset + trigger_data_out_q'length-1), + din => trigger_data_out_d, + dout => trigger_data_out_q); + +trace_data_out_latch: tri_rlmreg_p + generic map (width => trace_data_out_q'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => pc_mm_trace_bus_enable_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(trace_data_out_offset to trace_data_out_offset + trace_data_out_q'length-1), + scout => sov(trace_data_out_offset to trace_data_out_offset + trace_data_out_q'length-1), + din => trace_data_out_d, + dout => trace_data_out_q); + +trace_data_out_int_latch: tri_rlmreg_p + generic map (width => trace_data_out_int_q'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => pc_mm_trace_bus_enable_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(trace_data_out_int_offset to trace_data_out_int_offset + trace_data_out_int_q'length-1), + scout => sov(trace_data_out_int_offset to trace_data_out_int_offset + trace_data_out_int_q'length-1), + din => trace_data_out_d(0 to 7), + dout => trace_data_out_int_q); + +debug_latch : tri_regk + generic map (width => debug_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => pc_mm_trace_bus_enable_q, + forcee => pc_func_slp_nsl_force, + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_nsl_thold_0_b, + din => debug_d, + dout => debug_q); + +trigger_latch : tri_regk + generic map (width => trigger_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => pc_mm_trace_bus_enable_q, + forcee => pc_func_slp_nsl_force, + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_nsl_thold_0_b, + din => trigger_d, + dout => trigger_q); + + +debug_bus_in_latch : tri_regk + generic map (width => debug_bus_in_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => pc_mm_trace_bus_enable_q, + forcee => pc_func_slp_nsl_force, + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_nsl_thold_0_b, + din => debug_bus_in, + dout => debug_bus_in_q); + +trace_triggers_in_latch : tri_regk + generic map (width => trace_triggers_in_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => pc_mm_trace_bus_enable_q, + forcee => pc_func_slp_nsl_force, + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_nsl_thold_0_b, + din => trace_triggers_in, + dout => trace_triggers_in_q); + + +perv_2to1_plat: tri_plat + generic map (width => 4, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_func_slp_sl_thold_2, + din(1) => pc_func_slp_nsl_thold_2, + din(2) => pc_sg_2, + din(3) => pc_fce_2, + q(0) => pc_func_slp_sl_thold_1, + q(1) => pc_func_slp_nsl_thold_1, + q(2) => pc_sg_1, + q(3) => pc_fce_1); + +perv_1to0_plat: tri_plat + generic map (width => 4, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_func_slp_sl_thold_1, + din(1) => pc_func_slp_nsl_thold_1, + din(2) => pc_sg_1, + din(3) => pc_fce_1, + q(0) => pc_func_slp_sl_thold_0, + q(1) => pc_func_slp_nsl_thold_0, + q(2) => pc_sg_0, + q(3) => pc_fce_0); + +perv_sl_lcbor: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b, + thold => pc_func_slp_sl_thold_0, + sg => pc_sg_0, + act_dis => lcb_act_dis_dc, + forcee => pc_func_slp_sl_force, + thold_b => pc_func_slp_sl_thold_0_b); + +perv_nsl_lcbor: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b, + thold => pc_func_slp_nsl_thold_0, + sg => pc_fce_0, + act_dis => tidn, + forcee => pc_func_slp_nsl_force, + thold_b => pc_func_slp_nsl_thold_0_b); + +siv(0 to scan_right) <= sov(1 to scan_right) & scan_in; +scan_out <= sov(0); + + +end mmq_dbg; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/mmq_htw.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/mmq_htw.vhdl new file mode 100644 index 0000000..da12982 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/mmq_htw.vhdl @@ -0,0 +1,2644 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; +use ieee.std_logic_1164.all; +library ibm; +use ibm.std_ulogic_unsigned.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_support.all; +library support; +use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity mmq_htw is + generic(thdid_width : integer := 4; + pid_width : integer := 14; + lpid_width : integer := 8; + htw_seq_width : integer := 2; + pte_seq_width : integer := 3; + tlb_way_width : natural := 168; + tlb_word_width : natural := 84; + real_addr_width : integer := 42; + epn_width : integer := 52; + rpn_width : integer := 30; + pte_width : integer := 64; + tlb_tag_width : natural := 110; + expand_type : integer := 2 ); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + +tc_ccflush_dc : in std_ulogic; +tc_scan_dis_dc_b : in std_ulogic; +tc_scan_diag_dc : in std_ulogic; +tc_lbist_en_dc : in std_ulogic; +lcb_d_mode_dc : in std_ulogic; +lcb_clkoff_dc_b : in std_ulogic; +lcb_act_dis_dc : in std_ulogic; +lcb_mpw1_dc_b : in std_ulogic_vector(0 to 4); +lcb_mpw2_dc_b : in std_ulogic; +lcb_delay_lclkr_dc : in std_ulogic_vector(0 to 4); +ac_func_scan_in :in std_ulogic_vector(0 to 1); +ac_func_scan_out :out std_ulogic_vector(0 to 1); +pc_sg_2 : in std_ulogic; +pc_func_sl_thold_2 : in std_ulogic; +pc_func_slp_sl_thold_2 : in std_ulogic; +xu_mm_ccr2_notlb_b : in std_ulogic; +mmucr2_act_override : in std_ulogic; +tlb_delayed_act : in std_ulogic_vector(24 to 28); +tlb_ctl_tag2_flush : in std_ulogic_vector(0 to thdid_width-1); +tlb_ctl_tag3_flush : in std_ulogic_vector(0 to thdid_width-1); +tlb_ctl_tag4_flush : in std_ulogic_vector(0 to thdid_width-1); +tlb_tag2 : in std_ulogic_vector(0 to tlb_tag_width-1); +tlb_tag5_except : in std_ulogic_vector(0 to thdid_width-1); +tlb_htw_req_valid : in std_ulogic; +tlb_htw_req_tag : in std_ulogic_vector(0 to tlb_tag_width-1); +tlb_htw_req_way : in std_ulogic_vector(tlb_word_width to tlb_way_width-1); +htw_lsu_req_valid : out std_ulogic; +htw_lsu_thdid : out std_ulogic_vector(0 to thdid_width-1); +htw_dbg_lsu_thdid : out std_ulogic_vector(0 to 1); +htw_lsu_ttype : out std_ulogic_vector(0 to 1); +htw_lsu_wimge : out std_ulogic_vector(0 to 4); +htw_lsu_u : out std_ulogic_vector(0 to 3); +htw_lsu_addr : out std_ulogic_vector(64-real_addr_width to 63); +htw_lsu_req_taken : in std_ulogic; +htw_quiesce : out std_ulogic_vector(0 to thdid_width-1); +htw_req0_valid : out std_ulogic; +htw_req0_thdid : out std_ulogic_vector(0 to thdid_width-1); +htw_req0_type : out std_ulogic_vector(0 to 1); +htw_req1_valid : out std_ulogic; +htw_req1_thdid : out std_ulogic_vector(0 to thdid_width-1); +htw_req1_type : out std_ulogic_vector(0 to 1); +htw_req2_valid : out std_ulogic; +htw_req2_thdid : out std_ulogic_vector(0 to thdid_width-1); +htw_req2_type : out std_ulogic_vector(0 to 1); +htw_req3_valid : out std_ulogic; +htw_req3_thdid : out std_ulogic_vector(0 to thdid_width-1); +htw_req3_type : out std_ulogic_vector(0 to 1); +ptereload_req_valid : out std_ulogic; +ptereload_req_tag : out std_ulogic_vector(0 to tlb_tag_width-1); +ptereload_req_pte : out std_ulogic_vector(0 to pte_width-1); +ptereload_req_taken : in std_ulogic; +an_ac_reld_core_tag : in std_ulogic_vector(0 to 4); +an_ac_reld_data : in std_ulogic_vector(0 to 127); +an_ac_reld_data_vld : in std_ulogic; +an_ac_reld_ecc_err : in std_ulogic; +an_ac_reld_ecc_err_ue : in std_ulogic; +an_ac_reld_qw : in std_ulogic_vector(58 to 59); +an_ac_reld_ditc : in std_ulogic; +an_ac_reld_crit_qw : in std_ulogic; +htw_dbg_seq_idle : out std_ulogic; +htw_dbg_pte0_seq_idle : out std_ulogic; +htw_dbg_pte1_seq_idle : out std_ulogic; +htw_dbg_seq_q : out std_ulogic_vector(0 to 1); +htw_dbg_inptr_q : out std_ulogic_vector(0 to 1); +htw_dbg_pte0_seq_q : out std_ulogic_vector(0 to 2); +htw_dbg_pte1_seq_q : out std_ulogic_vector(0 to 2); +htw_dbg_ptereload_ptr_q : out std_ulogic; +htw_dbg_lsuptr_q : out std_ulogic_vector(0 to 1); +htw_dbg_req_valid_q : out std_ulogic_vector(0 to 3); +htw_dbg_resv_valid_vec : out std_ulogic_vector(0 to 3); +htw_dbg_tag4_clr_resv_q : out std_ulogic_vector(0 to 3); +htw_dbg_tag4_clr_resv_terms : out std_ulogic_vector(0 to 3); +htw_dbg_pte0_score_ptr_q : out std_ulogic_vector(0 to 1); +htw_dbg_pte0_score_cl_offset_q : out std_ulogic_vector(58 to 60); +htw_dbg_pte0_score_error_q : out std_ulogic_vector(0 to 2); +htw_dbg_pte0_score_qwbeat_q : out std_ulogic_vector(0 to 3); +htw_dbg_pte0_score_pending_q : out std_ulogic; +htw_dbg_pte0_score_ibit_q : out std_ulogic; +htw_dbg_pte0_score_dataval_q : out std_ulogic; +htw_dbg_pte0_reld_for_me_tm1 : out std_ulogic; +htw_dbg_pte1_score_ptr_q : out std_ulogic_vector(0 to 1); +htw_dbg_pte1_score_cl_offset_q : out std_ulogic_vector(58 to 60); +htw_dbg_pte1_score_error_q : out std_ulogic_vector(0 to 2); +htw_dbg_pte1_score_qwbeat_q : out std_ulogic_vector(0 to 3); +htw_dbg_pte1_score_pending_q : out std_ulogic; +htw_dbg_pte1_score_ibit_q : out std_ulogic; +htw_dbg_pte1_score_dataval_q : out std_ulogic; +htw_dbg_pte1_reld_for_me_tm1 : out std_ulogic + +); +end mmq_htw; +ARCHITECTURE MMQ_HTW + OF MMQ_HTW + IS +constant MMU_Mode_Value : std_ulogic := '0'; +constant TlbSel_Tlb : std_ulogic_vector(0 to 1) := "00"; +constant TlbSel_IErat : std_ulogic_vector(0 to 1) := "10"; +constant TlbSel_DErat : std_ulogic_vector(0 to 1) := "11"; +constant Core_Tag0_Value : std_ulogic_vector(0 to 4) := "01100"; +constant Core_Tag1_Value : std_ulogic_vector(0 to 4) := "01101"; +constant ERAT_PgSize_1GB : std_ulogic_vector(0 to 2) := "110"; +constant ERAT_PgSize_16MB : std_ulogic_vector(0 to 2) := "111"; +constant ERAT_PgSize_1MB : std_ulogic_vector(0 to 2) := "101"; +constant ERAT_PgSize_64KB : std_ulogic_vector(0 to 2) := "011"; +constant ERAT_PgSize_4KB : std_ulogic_vector(0 to 2) := "001"; +constant TLB_PgSize_1GB : std_ulogic_vector(0 to 3) := "1010"; +constant TLB_PgSize_16MB : std_ulogic_vector(0 to 3) := "0111"; +constant TLB_PgSize_1MB : std_ulogic_vector(0 to 3) := "0101"; +constant TLB_PgSize_64KB : std_ulogic_vector(0 to 3) := "0011"; +constant TLB_PgSize_4KB : std_ulogic_vector(0 to 3) := "0001"; +constant ERAT_PgSize_256MB : std_ulogic_vector(0 to 2) := "100"; +constant TLB_PgSize_256MB : std_ulogic_vector(0 to 3) := "1001"; +constant HtwSeq_Idle : std_ulogic_vector(0 to 1) := "00"; +constant HtwSeq_Stg1 : std_ulogic_vector(0 to 1) := "01"; +constant HtwSeq_Stg2 : std_ulogic_vector(0 to 1) := "11"; +constant HtwSeq_Stg3 : std_ulogic_vector(0 to 1) := "10"; +constant PteSeq_Idle : std_ulogic_vector(0 to 2) := "000"; +constant PteSeq_Stg1 : std_ulogic_vector(0 to 2) := "001"; +constant PteSeq_Stg2 : std_ulogic_vector(0 to 2) := "011"; +constant PteSeq_Stg3 : std_ulogic_vector(0 to 2) := "010"; +constant PteSeq_Stg4 : std_ulogic_vector(0 to 2) := "110"; +constant PteSeq_Stg5 : std_ulogic_vector(0 to 2) := "111"; +constant PteSeq_Stg6 : std_ulogic_vector(0 to 2) := "101"; +constant PteSeq_Stg7 : std_ulogic_vector(0 to 2) := "100"; +constant tlb_htw_req0_valid_offset : natural := 0; +constant tlb_htw_req0_pending_offset : natural := tlb_htw_req0_valid_offset + 1; +constant tlb_htw_req0_tag_offset : natural := tlb_htw_req0_pending_offset + 1; +constant tlb_htw_req0_way_offset : natural := tlb_htw_req0_tag_offset + tlb_tag_width; +constant tlb_htw_req1_valid_offset : natural := tlb_htw_req0_way_offset + tlb_word_width; +constant tlb_htw_req1_pending_offset : natural := tlb_htw_req1_valid_offset + 1; +constant tlb_htw_req1_tag_offset : natural := tlb_htw_req1_pending_offset + 1; +constant tlb_htw_req1_way_offset : natural := tlb_htw_req1_tag_offset + tlb_tag_width; +constant tlb_htw_req2_valid_offset : natural := tlb_htw_req1_way_offset + tlb_word_width; +constant tlb_htw_req2_pending_offset : natural := tlb_htw_req2_valid_offset + 1; +constant tlb_htw_req2_tag_offset : natural := tlb_htw_req2_pending_offset + 1; +constant tlb_htw_req2_way_offset : natural := tlb_htw_req2_tag_offset + tlb_tag_width; +constant tlb_htw_req3_valid_offset : natural := tlb_htw_req2_way_offset + tlb_word_width; +constant tlb_htw_req3_pending_offset : natural := tlb_htw_req3_valid_offset + 1; +constant tlb_htw_req3_tag_offset : natural := tlb_htw_req3_pending_offset + 1; +constant tlb_htw_req3_way_offset : natural := tlb_htw_req3_tag_offset + tlb_tag_width; +constant spare_a_offset : natural := tlb_htw_req3_way_offset + tlb_word_width; +constant scan_right_0 : natural := spare_a_offset + 16 -1; +constant htw_seq_offset : natural := 0; +constant htw_inptr_offset : natural := htw_seq_offset + htw_seq_width; +constant htw_lsuptr_offset : natural := htw_inptr_offset + 2; +constant htw_lsu_ttype_offset : natural := htw_lsuptr_offset + 2; +constant htw_lsu_thdid_offset : natural := htw_lsu_ttype_offset + 2; +constant htw_lsu_wimge_offset : natural := htw_lsu_thdid_offset + thdid_width; +constant htw_lsu_u_offset : natural := htw_lsu_wimge_offset + 5; +constant htw_lsu_addr_offset : natural := htw_lsu_u_offset + 4; +constant pte0_seq_offset : natural := htw_lsu_addr_offset + real_addr_width; +constant pte0_score_ptr_offset : natural := pte0_seq_offset + pte_seq_width; +constant pte0_score_cl_offset_offset : natural := pte0_score_ptr_offset + 2; +constant pte0_score_error_offset : natural := pte0_score_cl_offset_offset + 3; +constant pte0_score_qwbeat_offset : natural := pte0_score_error_offset + 3; +constant pte0_score_ibit_offset : natural := pte0_score_qwbeat_offset + 4; +constant pte0_score_pending_offset : natural := pte0_score_ibit_offset + 1; +constant pte0_score_dataval_offset : natural := pte0_score_pending_offset + 1; +constant pte1_seq_offset : natural := pte0_score_dataval_offset + 1; +constant pte1_score_ptr_offset : natural := pte1_seq_offset + pte_seq_width; +constant pte1_score_cl_offset_offset : natural := pte1_score_ptr_offset + 2; +constant pte1_score_error_offset : natural := pte1_score_cl_offset_offset + 3; +constant pte1_score_qwbeat_offset : natural := pte1_score_error_offset + 3; +constant pte1_score_ibit_offset : natural := pte1_score_qwbeat_offset + 4; +constant pte1_score_pending_offset : natural := pte1_score_ibit_offset + 1; +constant pte1_score_dataval_offset : natural := pte1_score_pending_offset + 1; +constant pte_load_ptr_offset : natural := pte1_score_dataval_offset + 1; +constant ptereload_ptr_offset : natural := pte_load_ptr_offset + 1; +constant reld_core_tag_tm1_offset : natural := ptereload_ptr_offset + 1; +constant reld_qw_tm1_offset : natural := reld_core_tag_tm1_offset + 5; +constant reld_crit_qw_tm1_offset : natural := reld_qw_tm1_offset + 2; +constant reld_ditc_tm1_offset : natural := reld_crit_qw_tm1_offset + 1; +constant reld_data_vld_tm1_offset : natural := reld_ditc_tm1_offset + 1; +constant reld_core_tag_t_offset : natural := reld_data_vld_tm1_offset + 1; +constant reld_qw_t_offset : natural := reld_core_tag_t_offset + 5; +constant reld_crit_qw_t_offset : natural := reld_qw_t_offset + 2; +constant reld_ditc_t_offset : natural := reld_crit_qw_t_offset + 1; +constant reld_data_vld_t_offset : natural := reld_ditc_t_offset + 1; +constant reld_core_tag_tp1_offset : natural := reld_data_vld_t_offset + 1; +constant reld_qw_tp1_offset : natural := reld_core_tag_tp1_offset + 5; +constant reld_crit_qw_tp1_offset : natural := reld_qw_tp1_offset + 2; +constant reld_ditc_tp1_offset : natural := reld_crit_qw_tp1_offset + 1; +constant reld_data_vld_tp1_offset : natural := reld_ditc_tp1_offset + 1; +constant reld_core_tag_tp2_offset : natural := reld_data_vld_tp1_offset + 1; +constant reld_qw_tp2_offset : natural := reld_core_tag_tp2_offset + 5; +constant reld_crit_qw_tp2_offset : natural := reld_qw_tp2_offset + 2; +constant reld_ditc_tp2_offset : natural := reld_crit_qw_tp2_offset + 1; +constant reld_data_vld_tp2_offset : natural := reld_ditc_tp2_offset + 1; +constant reld_ecc_err_tp2_offset : natural := reld_data_vld_tp2_offset + 1; +constant reld_ecc_err_ue_tp2_offset : natural := reld_ecc_err_tp2_offset + 1; +constant reld_data_tp1_offset : natural := reld_ecc_err_ue_tp2_offset + 1; +constant reld_data_tp2_offset : natural := reld_data_tp1_offset + 128; +constant pte0_reld_data_tp3_offset : natural := reld_data_tp2_offset + 128; +constant pte1_reld_data_tp3_offset : natural := pte0_reld_data_tp3_offset + 64; +constant htw_tag3_offset : natural := pte1_reld_data_tp3_offset + 64; +constant htw_tag4_clr_resv_offset : natural := htw_tag3_offset + tlb_tag_width; +constant htw_tag5_clr_resv_offset : natural := htw_tag4_clr_resv_offset + thdid_width; +constant spare_b_offset : natural := htw_tag5_clr_resv_offset + thdid_width; +constant scan_right_1 : natural := spare_b_offset + 16 -1; +constant tagpos_epn : natural := 0; +constant tagpos_pid : natural := 52; +constant tagpos_is : natural := 66; +constant tagpos_class : natural := 68; +constant tagpos_state : natural := 70; +constant tagpos_thdid : natural := 74; +constant tagpos_size : natural := 78; +constant tagpos_type : natural := 82; +constant tagpos_lpid : natural := 90; +constant tagpos_ind : natural := 98; +constant tagpos_atsel : natural := 99; +constant tagpos_esel : natural := 100; +constant tagpos_hes : natural := 103; +constant tagpos_wq : natural := 104; +constant tagpos_ltwe : natural := 106; +constant tagpos_lpte : natural := 107; +constant tagpos_recform : natural := 108; +constant tagpos_endflag : natural := 109; +constant tagpos_type_derat : natural := tagpos_type; +constant tagpos_type_ierat : natural := tagpos_type+1; +constant tagpos_type_tlbsx : natural := tagpos_type+2; +constant tagpos_type_tlbsrx : natural := tagpos_type+3; +constant tagpos_type_snoop : natural := tagpos_type+4; +constant tagpos_type_tlbre : natural := tagpos_type+5; +constant tagpos_type_tlbwe : natural := tagpos_type+6; +constant tagpos_type_ptereload : natural := tagpos_type+7; +constant tagpos_pr : natural := tagpos_state; +constant tagpos_gs : natural := tagpos_state+1; +constant tagpos_as : natural := tagpos_state+2; +constant tagpos_cm : natural := tagpos_state+3; +constant waypos_epn : natural := 0; +constant waypos_size : natural := 52; +constant waypos_thdid : natural := 56; +constant waypos_class : natural := 60; +constant waypos_extclass : natural := 62; +constant waypos_lpid : natural := 66; +constant waypos_xbit : natural := 84; +constant waypos_rpn : natural := 88; +constant waypos_rc : natural := 118; +constant waypos_wlc : natural := 120; +constant waypos_resvattr : natural := 122; +constant waypos_vf : natural := 123; +constant waypos_ind : natural := 124; +constant waypos_ubits : natural := 125; +constant waypos_wimge : natural := 129; +constant waypos_usxwr : natural := 134; +constant waypos_gs : natural := 140; +constant waypos_ts : natural := 141; +constant waypos_tid : natural := 144; +constant ptepos_rpn : natural := 0; +constant ptepos_wimge : natural := 40; +constant ptepos_r : natural := 45; +constant ptepos_ubits : natural := 46; +constant ptepos_sw0 : natural := 50; +constant ptepos_c : natural := 51; +constant ptepos_size : natural := 52; +constant ptepos_usxwr : natural := 56; +constant ptepos_sw1 : natural := 62; +constant ptepos_valid : natural := 63; +signal htw_seq_d, htw_seq_q : std_ulogic_vector(0 to 1); +signal htw_inptr_d, htw_inptr_q : std_ulogic_vector(0 to 1); +signal htw_lsuptr_d, htw_lsuptr_q : std_ulogic_vector(0 to 1); +signal htw_lsu_ttype_d, htw_lsu_ttype_q : std_ulogic_vector(0 to 1); +signal htw_lsu_thdid_d, htw_lsu_thdid_q : std_ulogic_vector(0 to thdid_width-1); +signal htw_lsu_wimge_d, htw_lsu_wimge_q : std_ulogic_vector(0 to 4); +signal htw_lsu_u_d, htw_lsu_u_q : std_ulogic_vector(0 to 3); +signal htw_lsu_addr_d, htw_lsu_addr_q : std_ulogic_vector(64-real_addr_width to 63); +signal pte0_seq_d, pte0_seq_q : std_ulogic_vector(0 to 2); +signal pte0_score_ptr_d, pte0_score_ptr_q : std_ulogic_vector(0 to 1); +signal pte0_score_cl_offset_d, pte0_score_cl_offset_q : std_ulogic_vector(58 to 60); +signal pte0_score_error_d, pte0_score_error_q : std_ulogic_vector(0 to 2); +signal pte0_score_qwbeat_d, pte0_score_qwbeat_q : std_ulogic_vector(0 to 3); +signal pte0_score_pending_d, pte0_score_pending_q : std_ulogic; +signal pte0_score_ibit_d, pte0_score_ibit_q : std_ulogic; +signal pte0_score_dataval_d, pte0_score_dataval_q : std_ulogic; +signal pte1_seq_d, pte1_seq_q : std_ulogic_vector(0 to 2); +signal pte1_score_ptr_d, pte1_score_ptr_q : std_ulogic_vector(0 to 1); +signal pte1_score_cl_offset_d, pte1_score_cl_offset_q : std_ulogic_vector(58 to 60); +signal pte1_score_error_d, pte1_score_error_q : std_ulogic_vector(0 to 2); +signal pte1_score_qwbeat_d, pte1_score_qwbeat_q : std_ulogic_vector(0 to 3); +signal pte1_score_pending_d, pte1_score_pending_q : std_ulogic; +signal pte1_score_ibit_d, pte1_score_ibit_q : std_ulogic; +signal pte1_score_dataval_d, pte1_score_dataval_q : std_ulogic; +signal ptereload_ptr_d, ptereload_ptr_q : std_ulogic; +signal pte_load_ptr_d, pte_load_ptr_q : std_ulogic; +signal tlb_htw_req0_valid_d, tlb_htw_req0_valid_q : std_ulogic; +signal tlb_htw_req0_pending_d, tlb_htw_req0_pending_q : std_ulogic; +signal tlb_htw_req0_tag_d, tlb_htw_req0_tag_q : std_ulogic_vector(0 to tlb_tag_width-1); +signal tlb_htw_req0_way_d, tlb_htw_req0_way_q : std_ulogic_vector(tlb_word_width to tlb_way_width-1); +signal tlb_htw_req0_tag_act : std_ulogic; +signal tlb_htw_req1_valid_d, tlb_htw_req1_valid_q : std_ulogic; +signal tlb_htw_req1_pending_d, tlb_htw_req1_pending_q : std_ulogic; +signal tlb_htw_req1_tag_d, tlb_htw_req1_tag_q : std_ulogic_vector(0 to tlb_tag_width-1); +signal tlb_htw_req1_way_d, tlb_htw_req1_way_q : std_ulogic_vector(tlb_word_width to tlb_way_width-1); +signal tlb_htw_req1_tag_act : std_ulogic; +signal tlb_htw_req2_valid_d, tlb_htw_req2_valid_q : std_ulogic; +signal tlb_htw_req2_pending_d, tlb_htw_req2_pending_q : std_ulogic; +signal tlb_htw_req2_tag_d, tlb_htw_req2_tag_q : std_ulogic_vector(0 to tlb_tag_width-1); +signal tlb_htw_req2_way_d, tlb_htw_req2_way_q : std_ulogic_vector(tlb_word_width to tlb_way_width-1); +signal tlb_htw_req2_tag_act : std_ulogic; +signal tlb_htw_req3_valid_d, tlb_htw_req3_valid_q : std_ulogic; +signal tlb_htw_req3_pending_d, tlb_htw_req3_pending_q : std_ulogic; +signal tlb_htw_req3_tag_d, tlb_htw_req3_tag_q : std_ulogic_vector(0 to tlb_tag_width-1); +signal tlb_htw_req3_way_d, tlb_htw_req3_way_q : std_ulogic_vector(tlb_word_width to tlb_way_width-1); +signal tlb_htw_req3_tag_act : std_ulogic; +-- synopsys translate_off +-- synopsys translate_on +signal reld_core_tag_tm1_d, reld_core_tag_tm1_q : std_ulogic_vector(0 to 4); +signal reld_qw_tm1_d, reld_qw_tm1_q : std_ulogic_vector(0 to 1); +signal reld_crit_qw_tm1_d, reld_crit_qw_tm1_q : std_ulogic; +signal reld_ditc_tm1_d, reld_ditc_tm1_q : std_ulogic; +signal reld_data_vld_tm1_d, reld_data_vld_tm1_q : std_ulogic; +signal reld_core_tag_t_d, reld_core_tag_t_q : std_ulogic_vector(0 to 4); +signal reld_qw_t_d, reld_qw_t_q : std_ulogic_vector(0 to 1); +signal reld_crit_qw_t_d, reld_crit_qw_t_q : std_ulogic; +signal reld_ditc_t_d, reld_ditc_t_q : std_ulogic; +signal reld_data_vld_t_d, reld_data_vld_t_q : std_ulogic; +signal reld_core_tag_tp1_d, reld_core_tag_tp1_q : std_ulogic_vector(0 to 4); +signal reld_qw_tp1_d, reld_qw_tp1_q : std_ulogic_vector(0 to 1); +signal reld_crit_qw_tp1_d, reld_crit_qw_tp1_q : std_ulogic; +signal reld_ditc_tp1_d, reld_ditc_tp1_q : std_ulogic; +signal reld_data_vld_tp1_d, reld_data_vld_tp1_q : std_ulogic; +signal reld_data_tp1_d, reld_data_tp1_q : std_ulogic_vector(0 to 127); +signal reld_core_tag_tp2_d, reld_core_tag_tp2_q : std_ulogic_vector(0 to 4); +signal reld_qw_tp2_d, reld_qw_tp2_q : std_ulogic_vector(0 to 1); +signal reld_crit_qw_tp2_d, reld_crit_qw_tp2_q : std_ulogic; +signal reld_ditc_tp2_d, reld_ditc_tp2_q : std_ulogic; +signal reld_data_vld_tp2_d, reld_data_vld_tp2_q : std_ulogic; +signal reld_data_tp2_d, reld_data_tp2_q : std_ulogic_vector(0 to 127); +signal reld_ecc_err_tp2_d, reld_ecc_err_tp2_q : std_ulogic; +signal reld_ecc_err_ue_tp2_d, reld_ecc_err_ue_tp2_q : std_ulogic; +signal pte0_reld_data_tp3_d, pte0_reld_data_tp3_q : std_ulogic_vector(0 to 63); +signal pte1_reld_data_tp3_d, pte1_reld_data_tp3_q : std_ulogic_vector(0 to 63); +signal htw_tag3_d, htw_tag3_q : std_ulogic_vector(0 to tlb_tag_width-1); +signal htw_tag3_clr_resv_term2, htw_tag3_clr_resv_term4, htw_tag3_clr_resv_term5, htw_tag3_clr_resv_term6 : std_ulogic_vector(0 to thdid_width-1); +signal htw_tag3_clr_resv_term7, htw_tag3_clr_resv_term8, htw_tag3_clr_resv_term9, htw_tag3_clr_resv_term11 : std_ulogic_vector(0 to thdid_width-1); +signal htw_tag4_clr_resv_d, htw_tag4_clr_resv_q : std_ulogic_vector(0 to thdid_width-1); +signal htw_tag5_clr_resv_d, htw_tag5_clr_resv_q : std_ulogic_vector(0 to thdid_width-1); +signal spare_a_q, spare_b_q : std_ulogic_vector(0 to 15); +signal htw_seq_idle : std_ulogic; +signal htw_seq_load_pteaddr : std_ulogic; +signal htw_quiesce_b : std_ulogic_vector(0 to thdid_width-1); +signal tlb_htw_req_valid_vec : std_ulogic_vector(0 to thdid_width-1); +signal tlb_htw_req_valid_notpend_vec : std_ulogic_vector(0 to thdid_width-1); +signal tlb_htw_pte_machines_full : std_ulogic; +signal htw_lsuptr_alt_d : std_ulogic_vector(0 to 1); +-- synopsys translate_off +-- synopsys translate_on +signal pte0_seq_idle : std_ulogic; +signal pte0_reload_req_valid : std_ulogic; +signal pte0_reload_req_taken : std_ulogic; +signal pte0_reld_for_me_tm1 : std_ulogic; +signal pte0_reld_for_me_tp2 : std_ulogic; +signal pte0_reld_enable_lo_tp2 : std_ulogic; +signal pte0_reld_enable_hi_tp2 : std_ulogic; +signal pte0_seq_score_load : std_ulogic; +signal pte0_seq_score_done : std_ulogic; +signal pte0_seq_data_retry : std_ulogic; +signal pte0_seq_clr_resv_ue : std_ulogic; +signal pte1_seq_idle : std_ulogic; +signal pte1_reload_req_valid : std_ulogic; +signal pte1_reload_req_taken : std_ulogic; +signal pte1_reld_for_me_tm1 : std_ulogic; +signal pte1_reld_for_me_tp2 : std_ulogic; +signal pte1_reld_enable_lo_tp2 : std_ulogic; +signal pte1_reld_enable_hi_tp2 : std_ulogic; +signal pte1_seq_score_load : std_ulogic; +signal pte1_seq_score_done : std_ulogic; +signal pte1_seq_data_retry : std_ulogic; +signal pte1_seq_clr_resv_ue : std_ulogic; +signal pte_ra_0 : std_ulogic_vector(64-real_addr_width to 63); +signal pte_ra_0_spsize4K : std_ulogic_vector(64-real_addr_width to 63); +signal pte_ra_0_spsize64K : std_ulogic_vector(64-real_addr_width to 63); +signal pte_ra_1 : std_ulogic_vector(64-real_addr_width to 63); +signal pte_ra_1_spsize4K : std_ulogic_vector(64-real_addr_width to 63); +signal pte_ra_1_spsize64K : std_ulogic_vector(64-real_addr_width to 63); +signal pte_ra_2 : std_ulogic_vector(64-real_addr_width to 63); +signal pte_ra_2_spsize4K : std_ulogic_vector(64-real_addr_width to 63); +signal pte_ra_2_spsize64K : std_ulogic_vector(64-real_addr_width to 63); +signal pte_ra_3 : std_ulogic_vector(64-real_addr_width to 63); +signal pte_ra_3_spsize4K : std_ulogic_vector(64-real_addr_width to 63); +signal pte_ra_3_spsize64K : std_ulogic_vector(64-real_addr_width to 63); +-- synopsys translate_off +-- synopsys translate_on +signal htw_resv0_tag3_lpid_match : std_ulogic; +signal htw_resv0_tag3_pid_match : std_ulogic; +signal htw_resv0_tag3_as_match : std_ulogic; +signal htw_resv0_tag3_gs_match : std_ulogic; +signal htw_resv0_tag3_epn_loc_match : std_ulogic; +signal htw_resv0_tag3_epn_glob_match : std_ulogic; +signal tlb_htw_req0_clr_resv_ue : std_ulogic; +signal htw_resv1_tag3_lpid_match : std_ulogic; +signal htw_resv1_tag3_pid_match : std_ulogic; +signal htw_resv1_tag3_as_match : std_ulogic; +signal htw_resv1_tag3_gs_match : std_ulogic; +signal htw_resv1_tag3_epn_loc_match : std_ulogic; +signal htw_resv1_tag3_epn_glob_match : std_ulogic; +signal tlb_htw_req1_clr_resv_ue : std_ulogic; +signal htw_resv2_tag3_lpid_match : std_ulogic; +signal htw_resv2_tag3_pid_match : std_ulogic; +signal htw_resv2_tag3_as_match : std_ulogic; +signal htw_resv2_tag3_gs_match : std_ulogic; +signal htw_resv2_tag3_epn_loc_match : std_ulogic; +signal htw_resv2_tag3_epn_glob_match : std_ulogic; +signal tlb_htw_req2_clr_resv_ue : std_ulogic; +signal htw_resv3_tag3_lpid_match : std_ulogic; +signal htw_resv3_tag3_pid_match : std_ulogic; +signal htw_resv3_tag3_as_match : std_ulogic; +signal htw_resv3_tag3_gs_match : std_ulogic; +signal htw_resv3_tag3_epn_loc_match : std_ulogic; +signal htw_resv3_tag3_epn_glob_match : std_ulogic; +signal tlb_htw_req3_clr_resv_ue : std_ulogic; +signal htw_resv_valid_vec : std_ulogic_vector(0 to thdid_width-1); +signal htw_tag4_clr_resv_terms : std_ulogic_vector(0 to 3); +signal htw_lsu_act : std_ulogic; +signal pte0_score_act : std_ulogic; +signal pte1_score_act : std_ulogic; +signal reld_act : std_ulogic; +signal pte0_reld_act : std_ulogic; +signal pte1_reld_act : std_ulogic; +signal unused_dc : std_ulogic_vector(0 to 21); +-- synopsys translate_off +-- synopsys translate_on +signal pc_sg_1 : std_ulogic; +signal pc_sg_0 : std_ulogic; +signal pc_func_sl_thold_1 : std_ulogic; +signal pc_func_sl_thold_0 : std_ulogic; +signal pc_func_sl_thold_0_b : std_ulogic; +signal pc_func_slp_sl_thold_1 : std_ulogic; +signal pc_func_slp_sl_thold_0 : std_ulogic; +signal pc_func_slp_sl_thold_0_b : std_ulogic; +signal pc_func_sl_force : std_ulogic; +signal pc_func_slp_sl_force : std_ulogic; +signal siv_0 : std_ulogic_vector(0 to scan_right_0); +signal sov_0 : std_ulogic_vector(0 to scan_right_0); +signal siv_1 : std_ulogic_vector(0 to scan_right_1); +signal sov_1 : std_ulogic_vector(0 to scan_right_1); + BEGIN + +htw_quiesce_b(0 TO thdid_width-1) <= + ( (0 to thdid_width-1 => tlb_htw_req0_valid_q) and tlb_htw_req0_tag_q(tagpos_thdid to tagpos_thdid+thdid_width-1) ) or + ( (0 to thdid_width-1 => tlb_htw_req1_valid_q) and tlb_htw_req1_tag_q(tagpos_thdid to tagpos_thdid+thdid_width-1) ) or + ( (0 to thdid_width-1 => tlb_htw_req2_valid_q) and tlb_htw_req2_tag_q(tagpos_thdid to tagpos_thdid+thdid_width-1) ) or + ( (0 to thdid_width-1 => tlb_htw_req3_valid_q) and tlb_htw_req3_tag_q(tagpos_thdid to tagpos_thdid+thdid_width-1) ); +htw_quiesce <= not htw_quiesce_b; +tlb_htw_pte_machines_full <= '1' when (pte0_score_pending_q='1' and pte1_score_pending_q='1') + else '0'; +tlb_htw_req_valid_vec <= (tlb_htw_req0_valid_q and (pte0_score_pending_q='0' or pte0_score_ptr_q/="00") and (pte1_score_pending_q='0' or pte1_score_ptr_q/="00")) & + (tlb_htw_req1_valid_q and (pte0_score_pending_q='0' or pte0_score_ptr_q/="01") and (pte1_score_pending_q='0' or pte1_score_ptr_q/="01")) & + (tlb_htw_req2_valid_q and (pte0_score_pending_q='0' or pte0_score_ptr_q/="10") and (pte1_score_pending_q='0' or pte1_score_ptr_q/="10")) & + (tlb_htw_req3_valid_q and (pte0_score_pending_q='0' or pte0_score_ptr_q/="11") and (pte1_score_pending_q='0' or pte1_score_ptr_q/="11")); +Htw_Sequencer: PROCESS (htw_seq_q, tlb_htw_req_valid_vec, tlb_htw_pte_machines_full, htw_lsu_req_taken) +BEGIN +htw_seq_load_pteaddr <= '0'; +htw_lsu_req_valid <= '0'; +CASE htw_seq_q IS + WHEN HtwSeq_Idle => + if tlb_htw_req_valid_vec/="0000" and tlb_htw_pte_machines_full='0' then + htw_seq_d <= HtwSeq_Stg1; + else + htw_seq_d <= HtwSeq_Idle; + end if; + WHEN HtwSeq_Stg1 => + htw_seq_load_pteaddr <= '1'; + htw_seq_d <= HtwSeq_Stg2; + + WHEN HtwSeq_Stg2 => + htw_lsu_req_valid <= '1'; + if htw_lsu_req_taken='1' then + htw_seq_d <= HtwSeq_Idle; + else + htw_seq_d <= HtwSeq_Stg2; + end if; + + WHEN OTHERS => + htw_seq_d <= HtwSeq_Idle; + + END CASE; +END PROCESS Htw_Sequencer; +htw_seq_idle <= '1' when htw_seq_q=HtwSeq_Idle else '0'; +Pte0_Sequencer: PROCESS (pte0_seq_q, pte_load_ptr_q, ptereload_ptr_q, htw_lsu_req_taken, ptereload_req_taken, + pte0_score_pending_q, pte0_score_dataval_q, + pte0_score_error_q, pte0_score_qwbeat_q, pte0_score_ibit_q, spare_b_q(0 to 2)) +BEGIN +pte0_reload_req_valid <= '0'; +pte0_reload_req_taken <= '0'; +pte0_seq_score_load <= '0'; +pte0_seq_score_done <= '0'; +pte0_seq_data_retry <= '0'; +pte0_reld_enable_lo_tp2 <= '0'; +pte0_reld_enable_hi_tp2 <= '0'; +pte0_seq_clr_resv_ue <= '0'; +CASE pte0_seq_q IS + WHEN PteSeq_Idle => + if pte_load_ptr_q='0' and htw_lsu_req_taken='1' then + pte0_seq_score_load <= '1'; + pte0_seq_d <= PteSeq_Stg1; + else + pte0_seq_d <= PteSeq_Idle; + end if; + WHEN PteSeq_Stg1 => + if pte0_score_pending_q='1' and pte0_score_dataval_q='1' then + pte0_seq_d <= PteSeq_Stg2; + else + pte0_seq_d <= PteSeq_Stg1; + end if; + + WHEN PteSeq_Stg2 => + if pte0_score_error_q(1)='1' and spare_b_q(0)='1' and (pte0_score_qwbeat_q="1111" or pte0_score_ibit_q='1') then + pte0_seq_d <= PteSeq_Stg4; + elsif pte0_score_error_q(0)='1' and (pte0_score_error_q(2)='0' or spare_b_q(1)='1') and + (pte0_score_qwbeat_q="1111" or pte0_score_ibit_q='1') then + pte0_seq_data_retry <= '1'; + pte0_seq_d <= PteSeq_Stg1; + elsif pte0_score_error_q(1)='1' and (pte0_score_qwbeat_q="1111" or pte0_score_ibit_q='1') then + pte0_seq_d <= PteSeq_Stg4; + elsif pte0_score_error_q(1)='0' and (pte0_score_qwbeat_q="1111" or pte0_score_ibit_q='1') then + pte0_seq_d <= PteSeq_Stg3; + else + pte0_seq_d <= PteSeq_Stg2; + end if; + + WHEN PteSeq_Stg3 => + pte0_reload_req_valid <= '1'; + if ptereload_ptr_q='0' and ptereload_req_taken='1' then + pte0_seq_score_done <= '1'; + pte0_reload_req_taken <= '1'; + pte0_seq_d <= PteSeq_Idle; + else + pte0_seq_d <= PteSeq_Stg3; + end if; + + WHEN PteSeq_Stg4 => + pte0_seq_clr_resv_ue <= not spare_b_q(2); + pte0_seq_d <= PteSeq_Stg5; + + WHEN PteSeq_Stg5 => + pte0_reload_req_valid <= '1'; + if ptereload_ptr_q='0' and ptereload_req_taken='1' then + pte0_seq_score_done <= '1'; + pte0_reload_req_taken <= '1'; + pte0_seq_d <= PteSeq_Idle; + else + pte0_seq_d <= PteSeq_Stg5; + end if; + + WHEN OTHERS => + pte0_seq_d <= PteSeq_Idle; + + END CASE; +END PROCESS Pte0_Sequencer; +pte0_seq_idle <= '1' when pte0_seq_q=PteSeq_Idle else '0'; +Pte1_Sequencer: PROCESS (pte1_seq_q, pte_load_ptr_q, ptereload_ptr_q, htw_lsu_req_taken, ptereload_req_taken, + pte1_score_pending_q, pte1_score_dataval_q, + pte1_score_error_q, pte1_score_qwbeat_q, pte1_score_ibit_q, spare_b_q(0 to 2)) +BEGIN +pte1_reload_req_valid <= '0'; +pte1_reload_req_taken <= '0'; +pte1_seq_score_load <= '0'; +pte1_seq_score_done <= '0'; +pte1_seq_data_retry <= '0'; +pte1_reld_enable_lo_tp2 <= '0'; +pte1_reld_enable_hi_tp2 <= '0'; +pte1_seq_clr_resv_ue <= '0'; +CASE pte1_seq_q IS + WHEN PteSeq_Idle => + if pte_load_ptr_q='1' and htw_lsu_req_taken='1' then + pte1_seq_score_load <= '1'; + pte1_seq_d <= PteSeq_Stg1; + else + pte1_seq_d <= PteSeq_Idle; + end if; + WHEN PteSeq_Stg1 => + if pte1_score_pending_q='1' and pte1_score_dataval_q='1' then + pte1_seq_d <= PteSeq_Stg2; + else + pte1_seq_d <= PteSeq_Stg1; + end if; + + WHEN PteSeq_Stg2 => + if pte1_score_error_q(1)='1' and spare_b_q(0)='1' and (pte1_score_qwbeat_q="1111" or pte1_score_ibit_q='1') then + pte1_seq_d <= PteSeq_Stg4; + elsif pte1_score_error_q(0)='1' and (pte1_score_error_q(2)='0' or spare_b_q(1)='1') and + (pte1_score_qwbeat_q="1111" or pte1_score_ibit_q='1') then + pte1_seq_data_retry <= '1'; + pte1_seq_d <= PteSeq_Stg1; + elsif pte1_score_error_q(1)='1' and (pte1_score_qwbeat_q="1111" or pte1_score_ibit_q='1') then + pte1_seq_d <= PteSeq_Stg4; + elsif pte1_score_error_q(1)='0' and (pte1_score_qwbeat_q="1111" or pte1_score_ibit_q='1') then + pte1_seq_d <= PteSeq_Stg3; + else + pte1_seq_d <= PteSeq_Stg2; + end if; + + WHEN PteSeq_Stg3 => + pte1_reload_req_valid <= '1'; + if ptereload_ptr_q='1' and ptereload_req_taken='1' then + pte1_seq_score_done <= '1'; + pte1_reload_req_taken <= '1'; + pte1_seq_d <= PteSeq_Idle; + else + pte1_seq_d <= PteSeq_Stg3; + end if; + + WHEN PteSeq_Stg4 => + pte1_seq_clr_resv_ue <= not spare_b_q(2); + pte1_seq_d <= PteSeq_Stg5; + + WHEN PteSeq_Stg5 => + pte1_reload_req_valid <= '1'; + if ptereload_ptr_q='1' and ptereload_req_taken='1' then + pte1_seq_score_done <= '1'; + pte1_reload_req_taken <= '1'; + pte1_seq_d <= PteSeq_Idle; + else + pte1_seq_d <= PteSeq_Stg5; + end if; + + WHEN OTHERS => + pte1_seq_d <= PteSeq_Idle; + + END CASE; +END PROCESS Pte1_Sequencer; +pte1_seq_idle <= '1' when pte1_seq_q=PteSeq_Idle else '0'; +tlb_htw_req0_valid_d <= '1' when (tlb_htw_req_valid='1' and tlb_htw_req0_valid_q='0' and htw_inptr_q="00") + else '0' when (pte0_reload_req_taken='1' and tlb_htw_req0_valid_q='1' and pte0_score_ptr_q="00") + else '0' when (pte1_reload_req_taken='1' and tlb_htw_req0_valid_q='1' and pte1_score_ptr_q="00") + else tlb_htw_req0_valid_q; +tlb_htw_req0_pending_d <= '1' when (htw_lsu_req_taken='1' and tlb_htw_req0_pending_q='0' and htw_lsuptr_q="00") + else '0' when (pte0_reload_req_taken='1' and tlb_htw_req0_pending_q='1' and pte0_score_ptr_q="00") + else '0' when (pte1_reload_req_taken='1' and tlb_htw_req0_pending_q='1' and pte1_score_ptr_q="00") + else tlb_htw_req0_pending_q; +tlb_htw_req0_way_d <= tlb_htw_req_way when (tlb_htw_req_valid='1' and tlb_htw_req0_valid_q='0' and htw_inptr_q="00") + else tlb_htw_req0_way_q; +tlb_htw_req0_tag_d(0 TO tagpos_wq-1) <= tlb_htw_req_tag(0 to tagpos_wq-1) when (tlb_htw_req_valid='1' and tlb_htw_req0_valid_q='0' and htw_inptr_q="00") + else tlb_htw_req0_tag_q(0 to tagpos_wq-1); +tlb_htw_req0_tag_d(tagpos_wq+2 TO tlb_tag_width-1) <= tlb_htw_req_tag(tagpos_wq+2 to tlb_tag_width-1) when (tlb_htw_req_valid='1' and tlb_htw_req0_valid_q='0' and htw_inptr_q="00") + else tlb_htw_req0_tag_q(tagpos_wq+2 to tlb_tag_width-1); +tlb_htw_req0_tag_d(tagpos_wq) <= '0' when ((htw_tag5_clr_resv_q(0)='1' and tlb_tag5_except="0000") or tlb_htw_req0_clr_resv_ue='1') + else '1' when (tlb_htw_req_valid='1' and tlb_htw_req0_valid_q='0' and htw_inptr_q="00") + else '0' when (pte0_reload_req_taken='1' and tlb_htw_req0_valid_q='1' and pte0_score_ptr_q="00") + else '0' when (pte1_reload_req_taken='1' and tlb_htw_req0_valid_q='1' and pte1_score_ptr_q="00") + else tlb_htw_req0_tag_q(tagpos_wq); +tlb_htw_req0_tag_d(tagpos_wq+1) <= tlb_htw_req0_tag_q(tagpos_wq+1); +tlb_htw_req0_tag_act <= tlb_delayed_act(24+0) or tlb_htw_req0_valid_q; +tlb_htw_req0_clr_resv_ue <= (pte0_seq_clr_resv_ue and Eq(pte0_score_ptr_q,"00")) or + (pte1_seq_clr_resv_ue and Eq(pte1_score_ptr_q,"00")); +htw_req0_valid <= tlb_htw_req0_valid_q; +htw_req0_thdid <= tlb_htw_req0_tag_q(tagpos_thdid to tagpos_thdid+thdid_width-1); +htw_req0_type <= tlb_htw_req0_tag_q(tagpos_type_derat to tagpos_type_ierat); +pte_ra_0_spsize4K <= tlb_htw_req0_way_q(waypos_rpn to waypos_rpn+rpn_width-1) & + tlb_htw_req0_way_q(waypos_usxwr+5) & + tlb_htw_req0_tag_q(tagpos_epn+epn_width-8 to tagpos_epn+epn_width-1) & "000"; +pte_ra_0_spsize64K <= tlb_htw_req0_way_q(waypos_rpn to waypos_rpn+rpn_width-4) & + tlb_htw_req0_tag_q(tagpos_epn+epn_width-16 to tagpos_epn+epn_width-5) & "000"; +pte_ra_0 <= pte_ra_0_spsize64K when tlb_htw_req0_way_q(waypos_usxwr to waypos_usxwr+3)=TLB_PgSize_64KB + else pte_ra_0_spsize4K; +tlb_htw_req1_valid_d <= '1' when (tlb_htw_req_valid='1' and tlb_htw_req1_valid_q='0' and htw_inptr_q="01") + else '0' when (pte0_reload_req_taken='1' and tlb_htw_req1_valid_q='1' and pte0_score_ptr_q="01") + else '0' when (pte1_reload_req_taken='1' and tlb_htw_req1_valid_q='1' and pte1_score_ptr_q="01") + else tlb_htw_req1_valid_q; +tlb_htw_req1_pending_d <= '1' when (htw_lsu_req_taken='1' and tlb_htw_req1_pending_q='0' and htw_lsuptr_q="01") + else '0' when (pte0_reload_req_taken='1' and tlb_htw_req1_pending_q='1' and pte0_score_ptr_q="01") + else '0' when (pte1_reload_req_taken='1' and tlb_htw_req1_pending_q='1' and pte1_score_ptr_q="01") + else tlb_htw_req1_pending_q; +tlb_htw_req1_way_d <= tlb_htw_req_way when (tlb_htw_req_valid='1' and tlb_htw_req1_valid_q='0' and htw_inptr_q="01") + else tlb_htw_req1_way_q; +tlb_htw_req1_tag_d(0 TO tagpos_wq-1) <= tlb_htw_req_tag(0 to tagpos_wq-1) when (tlb_htw_req_valid='1' and tlb_htw_req1_valid_q='0' and htw_inptr_q="01") + else tlb_htw_req1_tag_q(0 to tagpos_wq-1); +tlb_htw_req1_tag_d(tagpos_wq+2 TO tlb_tag_width-1) <= tlb_htw_req_tag(tagpos_wq+2 to tlb_tag_width-1) when (tlb_htw_req_valid='1' and tlb_htw_req1_valid_q='0' and htw_inptr_q="01") + else tlb_htw_req1_tag_q(tagpos_wq+2 to tlb_tag_width-1); +tlb_htw_req1_tag_d(tagpos_wq) <= '0' when ((htw_tag5_clr_resv_q(1)='1' and tlb_tag5_except="0000") or tlb_htw_req1_clr_resv_ue='1') + else '1' when (tlb_htw_req_valid='1' and tlb_htw_req1_valid_q='0' and htw_inptr_q="01") + else '0' when (pte0_reload_req_taken='1' and tlb_htw_req1_valid_q='1' and pte0_score_ptr_q="01") + else '0' when (pte1_reload_req_taken='1' and tlb_htw_req1_valid_q='1' and pte1_score_ptr_q="01") + else tlb_htw_req1_tag_q(tagpos_wq); +tlb_htw_req1_tag_d(tagpos_wq+1) <= tlb_htw_req1_tag_q(tagpos_wq+1); +tlb_htw_req1_tag_act <= tlb_delayed_act(24+1) or tlb_htw_req1_valid_q; +tlb_htw_req1_clr_resv_ue <= (pte0_seq_clr_resv_ue and Eq(pte0_score_ptr_q,"01")) or + (pte1_seq_clr_resv_ue and Eq(pte1_score_ptr_q,"01")); +htw_req1_valid <= tlb_htw_req1_valid_q; +htw_req1_thdid <= tlb_htw_req1_tag_q(tagpos_thdid to tagpos_thdid+thdid_width-1); +htw_req1_type <= tlb_htw_req1_tag_q(tagpos_type_derat to tagpos_type_ierat); +pte_ra_1_spsize4K <= tlb_htw_req1_way_q(waypos_rpn to waypos_rpn+rpn_width-1) & + tlb_htw_req1_way_q(waypos_usxwr+5) & + tlb_htw_req1_tag_q(tagpos_epn+epn_width-8 to tagpos_epn+epn_width-1) & "000"; +pte_ra_1_spsize64K <= tlb_htw_req1_way_q(waypos_rpn to waypos_rpn+rpn_width-4) & + tlb_htw_req1_tag_q(tagpos_epn+epn_width-16 to tagpos_epn+epn_width-5) & "000"; +pte_ra_1 <= pte_ra_1_spsize64K when tlb_htw_req1_way_q(waypos_usxwr to waypos_usxwr+3)=TLB_PgSize_64KB + else pte_ra_1_spsize4K; +tlb_htw_req2_valid_d <= '1' when (tlb_htw_req_valid='1' and tlb_htw_req2_valid_q='0' and htw_inptr_q="10") + else '0' when (pte0_reload_req_taken='1' and tlb_htw_req2_valid_q='1' and pte0_score_ptr_q="10") + else '0' when (pte1_reload_req_taken='1' and tlb_htw_req2_valid_q='1' and pte1_score_ptr_q="10") + else tlb_htw_req2_valid_q; +tlb_htw_req2_pending_d <= '1' when (htw_lsu_req_taken='1' and tlb_htw_req2_pending_q='0' and htw_lsuptr_q="10") + else '0' when (pte0_reload_req_taken='1' and tlb_htw_req2_pending_q='1' and pte0_score_ptr_q="10") + else '0' when (pte1_reload_req_taken='1' and tlb_htw_req2_pending_q='1' and pte1_score_ptr_q="10") + else tlb_htw_req2_pending_q; +tlb_htw_req2_way_d <= tlb_htw_req_way when (tlb_htw_req_valid='1' and tlb_htw_req2_valid_q='0' and htw_inptr_q="10") + else tlb_htw_req2_way_q; +tlb_htw_req2_tag_d(0 TO tagpos_wq-1) <= tlb_htw_req_tag(0 to tagpos_wq-1) when (tlb_htw_req_valid='1' and tlb_htw_req2_valid_q='0' and htw_inptr_q="10") + else tlb_htw_req2_tag_q(0 to tagpos_wq-1); +tlb_htw_req2_tag_d(tagpos_wq+2 TO tlb_tag_width-1) <= tlb_htw_req_tag(tagpos_wq+2 to tlb_tag_width-1) when (tlb_htw_req_valid='1' and tlb_htw_req2_valid_q='0' and htw_inptr_q="10") + else tlb_htw_req2_tag_q(tagpos_wq+2 to tlb_tag_width-1); +tlb_htw_req2_tag_d(tagpos_wq) <= '0' when ((htw_tag5_clr_resv_q(2)='1' and tlb_tag5_except="0000") or tlb_htw_req2_clr_resv_ue='1') + else '1' when (tlb_htw_req_valid='1' and tlb_htw_req2_valid_q='0' and htw_inptr_q="10") + else '0' when (pte0_reload_req_taken='1' and tlb_htw_req2_valid_q='1' and pte0_score_ptr_q="10") + else '0' when (pte1_reload_req_taken='1' and tlb_htw_req2_valid_q='1' and pte1_score_ptr_q="10") + else tlb_htw_req2_tag_q(tagpos_wq); +tlb_htw_req2_tag_d(tagpos_wq+1) <= tlb_htw_req2_tag_q(tagpos_wq+1); +tlb_htw_req2_tag_act <= tlb_delayed_act(24+2) or tlb_htw_req2_valid_q; +tlb_htw_req2_clr_resv_ue <= (pte0_seq_clr_resv_ue and Eq(pte0_score_ptr_q,"10")) or + (pte1_seq_clr_resv_ue and Eq(pte1_score_ptr_q,"10")); +htw_req2_valid <= tlb_htw_req2_valid_q; +htw_req2_thdid <= tlb_htw_req2_tag_q(tagpos_thdid to tagpos_thdid+thdid_width-1); +htw_req2_type <= tlb_htw_req2_tag_q(tagpos_type_derat to tagpos_type_ierat); +pte_ra_2_spsize4K <= tlb_htw_req2_way_q(waypos_rpn to waypos_rpn+rpn_width-1) & + tlb_htw_req2_way_q(waypos_usxwr+5) & + tlb_htw_req2_tag_q(tagpos_epn+epn_width-8 to tagpos_epn+epn_width-1) & "000"; +pte_ra_2_spsize64K <= tlb_htw_req2_way_q(waypos_rpn to waypos_rpn+rpn_width-4) & + tlb_htw_req2_tag_q(tagpos_epn+epn_width-16 to tagpos_epn+epn_width-5) & "000"; +pte_ra_2 <= pte_ra_2_spsize64K when tlb_htw_req2_way_q(waypos_usxwr to waypos_usxwr+3)=TLB_PgSize_64KB + else pte_ra_2_spsize4K; +tlb_htw_req3_valid_d <= '1' when (tlb_htw_req_valid='1' and tlb_htw_req3_valid_q='0' and htw_inptr_q="11") + else '0' when (pte0_reload_req_taken='1' and tlb_htw_req3_valid_q='1' and pte0_score_ptr_q="11") + else '0' when (pte1_reload_req_taken='1' and tlb_htw_req3_valid_q='1' and pte1_score_ptr_q="11") + else tlb_htw_req3_valid_q; +tlb_htw_req3_pending_d <= '1' when (htw_lsu_req_taken='1' and tlb_htw_req3_pending_q='0' and htw_lsuptr_q="11") + else '0' when (pte0_reload_req_taken='1' and tlb_htw_req3_pending_q='1' and pte0_score_ptr_q="11") + else '0' when (pte1_reload_req_taken='1' and tlb_htw_req3_pending_q='1' and pte1_score_ptr_q="11") + else tlb_htw_req3_pending_q; +tlb_htw_req3_way_d <= tlb_htw_req_way when (tlb_htw_req_valid='1' and tlb_htw_req3_valid_q='0' and htw_inptr_q="11") + else tlb_htw_req3_way_q; +tlb_htw_req3_tag_d(0 TO tagpos_wq-1) <= tlb_htw_req_tag(0 to tagpos_wq-1) when (tlb_htw_req_valid='1' and tlb_htw_req3_valid_q='0' and htw_inptr_q="11") + else tlb_htw_req3_tag_q(0 to tagpos_wq-1); +tlb_htw_req3_tag_d(tagpos_wq+2 TO tlb_tag_width-1) <= tlb_htw_req_tag(tagpos_wq+2 to tlb_tag_width-1) when (tlb_htw_req_valid='1' and tlb_htw_req3_valid_q='0' and htw_inptr_q="11") + else tlb_htw_req3_tag_q(tagpos_wq+2 to tlb_tag_width-1); +tlb_htw_req3_tag_d(tagpos_wq) <= '0' when ((htw_tag5_clr_resv_q(3)='1' and tlb_tag5_except="0000") or tlb_htw_req3_clr_resv_ue='1') + else '1' when (tlb_htw_req_valid='1' and tlb_htw_req3_valid_q='0' and htw_inptr_q="11") + else '0' when (pte0_reload_req_taken='1' and tlb_htw_req3_valid_q='1' and pte0_score_ptr_q="11") + else '0' when (pte1_reload_req_taken='1' and tlb_htw_req3_valid_q='1' and pte1_score_ptr_q="11") + else tlb_htw_req3_tag_q(tagpos_wq); +tlb_htw_req3_tag_d(tagpos_wq+1) <= tlb_htw_req3_tag_q(tagpos_wq+1); +tlb_htw_req3_tag_act <= tlb_delayed_act(24+3) or tlb_htw_req3_valid_q; +tlb_htw_req3_clr_resv_ue <= (pte0_seq_clr_resv_ue and Eq(pte0_score_ptr_q,"11")) or + (pte1_seq_clr_resv_ue and Eq(pte1_score_ptr_q,"11")); +htw_req3_valid <= tlb_htw_req3_valid_q; +htw_req3_thdid <= tlb_htw_req3_tag_q(tagpos_thdid to tagpos_thdid+thdid_width-1); +htw_req3_type <= tlb_htw_req3_tag_q(tagpos_type_derat to tagpos_type_ierat); +pte_ra_3_spsize4K <= tlb_htw_req3_way_q(waypos_rpn to waypos_rpn+rpn_width-1) & + tlb_htw_req3_way_q(waypos_usxwr+5) & + tlb_htw_req3_tag_q(tagpos_epn+epn_width-8 to tagpos_epn+epn_width-1) & "000"; +pte_ra_3_spsize64K <= tlb_htw_req3_way_q(waypos_rpn to waypos_rpn+rpn_width-4) & + tlb_htw_req3_tag_q(tagpos_epn+epn_width-16 to tagpos_epn+epn_width-5) & "000"; +pte_ra_3 <= pte_ra_3_spsize64K when tlb_htw_req3_way_q(waypos_usxwr to waypos_usxwr+3)=TLB_PgSize_64KB + else pte_ra_3_spsize4K; +htw_tag3_d(0 TO tagpos_thdid-1) <= tlb_tag2(0 to tagpos_thdid-1); +htw_tag3_d(tagpos_thdid+thdid_width TO tlb_tag_width-1) <= tlb_tag2(tagpos_thdid+thdid_width to tlb_tag_width-1); +htw_tag3_d(tagpos_thdid TO tagpos_thdid+thdid_width-1) <= tlb_tag2(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag2_flush); +htw_tag3_clr_resv_term2(0) <= '1' when (htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000" and + htw_tag3_q(tagpos_type_snoop)='1' and htw_tag3_q(tagpos_is to tagpos_is+3)="0011" and + htw_resv0_tag3_lpid_match='1' and htw_resv0_tag3_pid_match='1' and htw_resv0_tag3_gs_match='1' and + htw_resv0_tag3_as_match='1' and htw_resv0_tag3_epn_glob_match='1' ) + else '0'; +htw_tag3_clr_resv_term4(0) <= '1' when (htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000" and + htw_tag3_q(tagpos_type_snoop)='1' and htw_tag3_q(tagpos_is to tagpos_is+3)="1000" and + htw_resv0_tag3_lpid_match='1' ) + else '0'; +htw_tag3_clr_resv_term5(0) <= '1' when (htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000" and + htw_tag3_q(tagpos_type_snoop)='1' and htw_tag3_q(tagpos_is to tagpos_is+3)="1001" and + htw_resv0_tag3_lpid_match='1' and htw_resv0_tag3_pid_match='1' ) + else '0'; +htw_tag3_clr_resv_term6(0) <= '1' when (htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000" and + htw_tag3_q(tagpos_type_snoop)='1' and htw_tag3_q(tagpos_is to tagpos_is+3)="1011" and + htw_resv0_tag3_lpid_match='1' and htw_resv0_tag3_pid_match='1' and htw_resv0_tag3_gs_match='1' and + htw_resv0_tag3_as_match='1' and htw_resv0_tag3_epn_loc_match='1' ) + else '0'; +htw_tag3_clr_resv_term7(0) <= '1' when ( (((htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag3_flush))/="0000" and htw_tag3_q(tagpos_wq to tagpos_wq+1)="01") or + ((htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag3_flush))/="0000" and htw_tag3_q(tagpos_wq to tagpos_wq+1)="00")) and + htw_tag3_q(tagpos_type_tlbwe)='1' and + htw_resv0_tag3_gs_match='1' and htw_resv0_tag3_as_match='1' and + htw_resv0_tag3_lpid_match='1' and htw_resv0_tag3_pid_match='1' and + htw_resv0_tag3_epn_loc_match='1' ) + else '0'; +htw_tag3_clr_resv_term8(0) <= '1' when ( htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000" and + htw_tag3_q(tagpos_type_ptereload)='1' and htw_tag3_q(tagpos_wq to tagpos_wq+1)="10" and + htw_resv0_tag3_gs_match='1' and htw_resv0_tag3_as_match='1' and + htw_resv0_tag3_lpid_match='1' and htw_resv0_tag3_pid_match='1' and + htw_resv0_tag3_epn_loc_match='1' ) + else '0'; +htw_tag3_clr_resv_term9(0) <= '1' when ( (((htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag3_flush))/="0000" and htw_tag3_q(tagpos_wq to tagpos_wq+1)="10") or + ((htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag3_flush))/="0000" and htw_tag3_q(tagpos_wq to tagpos_wq+1)="11")) and + htw_tag3_q(tagpos_type_tlbwe)='1' and + htw_resv0_tag3_gs_match='1' and htw_resv0_tag3_as_match='1' and + htw_resv0_tag3_lpid_match='1' and htw_resv0_tag3_pid_match='1' and + htw_resv0_tag3_epn_loc_match='1' ) + else '0'; +htw_tag3_clr_resv_term11(0) <= '1' when (htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000" and + htw_tag3_q(tagpos_type_snoop)='1' and htw_tag3_q(tagpos_is to tagpos_is+1)="11" ) + else '0'; +htw_tag4_clr_resv_d(0) <= htw_tag3_clr_resv_term2(0) or htw_tag3_clr_resv_term4(0) or htw_tag3_clr_resv_term5(0) or htw_tag3_clr_resv_term6(0) or + htw_tag3_clr_resv_term7(0) or htw_tag3_clr_resv_term8(0) or htw_tag3_clr_resv_term9(0) or + htw_tag3_clr_resv_term11(0); +htw_tag3_clr_resv_term2(1) <= '1' when (htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000" and + htw_tag3_q(tagpos_type_snoop)='1' and htw_tag3_q(tagpos_is to tagpos_is+3)="0011" and + htw_resv1_tag3_lpid_match='1' and htw_resv1_tag3_pid_match='1' and htw_resv1_tag3_gs_match='1' and + htw_resv1_tag3_as_match='1' and htw_resv1_tag3_epn_glob_match='1' ) + else '0'; +htw_tag3_clr_resv_term4(1) <= '1' when (htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000" and + htw_tag3_q(tagpos_type_snoop)='1' and htw_tag3_q(tagpos_is to tagpos_is+3)="1000" and + htw_resv1_tag3_lpid_match='1' ) + else '0'; +htw_tag3_clr_resv_term5(1) <= '1' when (htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000" and + htw_tag3_q(tagpos_type_snoop)='1' and htw_tag3_q(tagpos_is to tagpos_is+3)="1001" and + htw_resv1_tag3_lpid_match='1' and htw_resv1_tag3_pid_match='1' ) + else '0'; +htw_tag3_clr_resv_term6(1) <= '1' when (htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000" and + htw_tag3_q(tagpos_type_snoop)='1' and htw_tag3_q(tagpos_is to tagpos_is+3)="1011" and + htw_resv1_tag3_lpid_match='1' and htw_resv1_tag3_pid_match='1' and htw_resv1_tag3_gs_match='1' and + htw_resv1_tag3_as_match='1' and htw_resv1_tag3_epn_loc_match='1' ) + else '0'; +htw_tag3_clr_resv_term7(1) <= '1' when ( (((htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag3_flush))/="0000" and htw_tag3_q(tagpos_wq to tagpos_wq+1)="01") or + ((htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag3_flush))/="0000" and htw_tag3_q(tagpos_wq to tagpos_wq+1)="00")) and + htw_tag3_q(tagpos_type_tlbwe)='1' and + htw_resv1_tag3_gs_match='1' and htw_resv1_tag3_as_match='1' and + htw_resv1_tag3_lpid_match='1' and htw_resv1_tag3_pid_match='1' and + htw_resv1_tag3_epn_loc_match='1' ) + else '0'; +htw_tag3_clr_resv_term8(1) <= '1' when ( htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000" and + htw_tag3_q(tagpos_type_ptereload)='1' and htw_tag3_q(tagpos_wq to tagpos_wq+1)="10" and + htw_resv1_tag3_gs_match='1' and htw_resv1_tag3_as_match='1' and + htw_resv1_tag3_lpid_match='1' and htw_resv1_tag3_pid_match='1' and + htw_resv1_tag3_epn_loc_match='1' ) + else '0'; +htw_tag3_clr_resv_term9(1) <= '1' when ( (((htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag3_flush))/="0000" and htw_tag3_q(tagpos_wq to tagpos_wq+1)="10") or + ((htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag3_flush))/="0000" and htw_tag3_q(tagpos_wq to tagpos_wq+1)="11")) and + htw_tag3_q(tagpos_type_tlbwe)='1' and + htw_resv1_tag3_gs_match='1' and htw_resv1_tag3_as_match='1' and + htw_resv1_tag3_lpid_match='1' and htw_resv1_tag3_pid_match='1' and + htw_resv1_tag3_epn_loc_match='1' ) + else '0'; +htw_tag3_clr_resv_term11(1) <= '1' when (htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000" and + htw_tag3_q(tagpos_type_snoop)='1' and htw_tag3_q(tagpos_is to tagpos_is+1)="11" ) + else '0'; +htw_tag4_clr_resv_d(1) <= htw_tag3_clr_resv_term2(1) or htw_tag3_clr_resv_term4(1) or htw_tag3_clr_resv_term5(1) or htw_tag3_clr_resv_term6(1) or + htw_tag3_clr_resv_term7(1) or htw_tag3_clr_resv_term8(1) or htw_tag3_clr_resv_term9(1) or + htw_tag3_clr_resv_term11(1); +htw_tag3_clr_resv_term2(2) <= '1' when (htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000" and + htw_tag3_q(tagpos_type_snoop)='1' and htw_tag3_q(tagpos_is to tagpos_is+3)="0011" and + htw_resv2_tag3_lpid_match='1' and htw_resv2_tag3_pid_match='1' and htw_resv2_tag3_gs_match='1' and + htw_resv2_tag3_as_match='1' and htw_resv2_tag3_epn_glob_match='1' ) + else '0'; +htw_tag3_clr_resv_term4(2) <= '1' when (htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000" and + htw_tag3_q(tagpos_type_snoop)='1' and htw_tag3_q(tagpos_is to tagpos_is+3)="1000" and + htw_resv2_tag3_lpid_match='1' ) + else '0'; +htw_tag3_clr_resv_term5(2) <= '1' when (htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000" and + htw_tag3_q(tagpos_type_snoop)='1' and htw_tag3_q(tagpos_is to tagpos_is+3)="1001" and + htw_resv2_tag3_lpid_match='1' and htw_resv2_tag3_pid_match='1' ) + else '0'; +htw_tag3_clr_resv_term6(2) <= '1' when (htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000" and + htw_tag3_q(tagpos_type_snoop)='1' and htw_tag3_q(tagpos_is to tagpos_is+3)="1011" and + htw_resv2_tag3_lpid_match='1' and htw_resv2_tag3_pid_match='1' and htw_resv2_tag3_gs_match='1' and + htw_resv2_tag3_as_match='1' and htw_resv2_tag3_epn_loc_match='1' ) + else '0'; +htw_tag3_clr_resv_term7(2) <= '1' when ( (((htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag3_flush))/="0000" and htw_tag3_q(tagpos_wq to tagpos_wq+1)="01") or + ((htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag3_flush))/="0000" and htw_tag3_q(tagpos_wq to tagpos_wq+1)="00")) and + htw_tag3_q(tagpos_type_tlbwe)='1' and + htw_resv2_tag3_gs_match='1' and htw_resv2_tag3_as_match='1' and + htw_resv2_tag3_lpid_match='1' and htw_resv2_tag3_pid_match='1' and + htw_resv2_tag3_epn_loc_match='1' ) + else '0'; +htw_tag3_clr_resv_term8(2) <= '1' when ( htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000" and + htw_tag3_q(tagpos_type_ptereload)='1' and htw_tag3_q(tagpos_wq to tagpos_wq+1)="10" and + htw_resv2_tag3_gs_match='1' and htw_resv2_tag3_as_match='1' and + htw_resv2_tag3_lpid_match='1' and htw_resv2_tag3_pid_match='1' and + htw_resv2_tag3_epn_loc_match='1' ) + else '0'; +htw_tag3_clr_resv_term9(2) <= '1' when ( (((htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag3_flush))/="0000" and htw_tag3_q(tagpos_wq to tagpos_wq+1)="10") or + ((htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag3_flush))/="0000" and htw_tag3_q(tagpos_wq to tagpos_wq+1)="11")) and + htw_tag3_q(tagpos_type_tlbwe)='1' and + htw_resv2_tag3_gs_match='1' and htw_resv2_tag3_as_match='1' and + htw_resv2_tag3_lpid_match='1' and htw_resv2_tag3_pid_match='1' and + htw_resv2_tag3_epn_loc_match='1' ) + else '0'; +htw_tag3_clr_resv_term11(2) <= '1' when (htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000" and + htw_tag3_q(tagpos_type_snoop)='1' and htw_tag3_q(tagpos_is to tagpos_is+1)="11" ) + else '0'; +htw_tag4_clr_resv_d(2) <= htw_tag3_clr_resv_term2(2) or htw_tag3_clr_resv_term4(2) or htw_tag3_clr_resv_term5(2) or htw_tag3_clr_resv_term6(2) or + htw_tag3_clr_resv_term7(2) or htw_tag3_clr_resv_term8(2) or htw_tag3_clr_resv_term9(2) or + htw_tag3_clr_resv_term11(2); +htw_tag3_clr_resv_term2(3) <= '1' when (htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000" and + htw_tag3_q(tagpos_type_snoop)='1' and htw_tag3_q(tagpos_is to tagpos_is+3)="0011" and + htw_resv3_tag3_lpid_match='1' and htw_resv3_tag3_pid_match='1' and htw_resv3_tag3_gs_match='1' and + htw_resv3_tag3_as_match='1' and htw_resv3_tag3_epn_glob_match='1' ) + else '0'; +htw_tag3_clr_resv_term4(3) <= '1' when (htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000" and + htw_tag3_q(tagpos_type_snoop)='1' and htw_tag3_q(tagpos_is to tagpos_is+3)="1000" and + htw_resv3_tag3_lpid_match='1' ) + else '0'; +htw_tag3_clr_resv_term5(3) <= '1' when (htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000" and + htw_tag3_q(tagpos_type_snoop)='1' and htw_tag3_q(tagpos_is to tagpos_is+3)="1001" and + htw_resv3_tag3_lpid_match='1' and htw_resv3_tag3_pid_match='1' ) + else '0'; +htw_tag3_clr_resv_term6(3) <= '1' when (htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000" and + htw_tag3_q(tagpos_type_snoop)='1' and htw_tag3_q(tagpos_is to tagpos_is+3)="1011" and + htw_resv3_tag3_lpid_match='1' and htw_resv3_tag3_pid_match='1' and htw_resv3_tag3_gs_match='1' and + htw_resv3_tag3_as_match='1' and htw_resv3_tag3_epn_loc_match='1' ) + else '0'; +htw_tag3_clr_resv_term7(3) <= '1' when ( (((htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag3_flush))/="0000" and htw_tag3_q(tagpos_wq to tagpos_wq+1)="01") or + ((htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag3_flush))/="0000" and htw_tag3_q(tagpos_wq to tagpos_wq+1)="00")) and + htw_tag3_q(tagpos_type_tlbwe)='1' and + htw_resv3_tag3_gs_match='1' and htw_resv3_tag3_as_match='1' and + htw_resv3_tag3_lpid_match='1' and htw_resv3_tag3_pid_match='1' and + htw_resv3_tag3_epn_loc_match='1' ) + else '0'; +htw_tag3_clr_resv_term8(3) <= '1' when ( htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000" and + htw_tag3_q(tagpos_type_ptereload)='1' and htw_tag3_q(tagpos_wq to tagpos_wq+1)="10" and + htw_resv3_tag3_gs_match='1' and htw_resv3_tag3_as_match='1' and + htw_resv3_tag3_lpid_match='1' and htw_resv3_tag3_pid_match='1' and + htw_resv3_tag3_epn_loc_match='1' ) + else '0'; +htw_tag3_clr_resv_term9(3) <= '1' when ( (((htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag3_flush))/="0000" and htw_tag3_q(tagpos_wq to tagpos_wq+1)="10") or + ((htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag3_flush))/="0000" and htw_tag3_q(tagpos_wq to tagpos_wq+1)="11")) and + htw_tag3_q(tagpos_type_tlbwe)='1' and + htw_resv3_tag3_gs_match='1' and htw_resv3_tag3_as_match='1' and + htw_resv3_tag3_lpid_match='1' and htw_resv3_tag3_pid_match='1' and + htw_resv3_tag3_epn_loc_match='1' ) + else '0'; +htw_tag3_clr_resv_term11(3) <= '1' when (htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000" and + htw_tag3_q(tagpos_type_snoop)='1' and htw_tag3_q(tagpos_is to tagpos_is+1)="11" ) + else '0'; +htw_tag4_clr_resv_d(3) <= htw_tag3_clr_resv_term2(3) or htw_tag3_clr_resv_term4(3) or htw_tag3_clr_resv_term5(3) or htw_tag3_clr_resv_term6(3) or + htw_tag3_clr_resv_term7(3) or htw_tag3_clr_resv_term8(3) or htw_tag3_clr_resv_term9(3) or + htw_tag3_clr_resv_term11(3); +htw_tag5_clr_resv_d <= htw_tag4_clr_resv_q when + (tlb_htw_req_tag(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag4_flush))/="0000" + else "0000"; +htw_resv_valid_vec <= tlb_htw_req0_tag_q(tagpos_wq) & tlb_htw_req1_tag_q(tagpos_wq) & tlb_htw_req2_tag_q(tagpos_wq) & tlb_htw_req3_tag_q(tagpos_wq); +htw_resv0_tag3_lpid_match <= '1' when (htw_tag3_q(tagpos_lpid to tagpos_lpid+lpid_width-1)=tlb_htw_req0_tag_q(tagpos_lpid to tagpos_lpid+lpid_width-1)) else '0'; +htw_resv0_tag3_pid_match <= '1' when (htw_tag3_q(tagpos_pid to tagpos_pid+pid_width-1)=tlb_htw_req0_tag_q(tagpos_pid to tagpos_pid+pid_width-1)) else '0'; +htw_resv0_tag3_as_match <= '1' when (htw_tag3_q(tagpos_as)=tlb_htw_req0_tag_q(tagpos_as)) else '0'; +htw_resv0_tag3_gs_match <= '1' when (htw_tag3_q(tagpos_gs)=tlb_htw_req0_tag_q(tagpos_gs)) else '0'; +htw_resv0_tag3_epn_loc_match <= '1' when (htw_tag3_q(tagpos_epn to tagpos_epn+epn_width-1)=tlb_htw_req0_tag_q(tagpos_epn to tagpos_epn+epn_width-1) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_4KB) or + (htw_tag3_q(tagpos_epn to tagpos_epn+epn_width-5)=tlb_htw_req0_tag_q(tagpos_epn to tagpos_epn+epn_width-5) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_64KB) or + (htw_tag3_q(tagpos_epn to tagpos_epn+epn_width-9)=tlb_htw_req0_tag_q(tagpos_epn to tagpos_epn+epn_width-9) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1MB) or + (htw_tag3_q(tagpos_epn to tagpos_epn+epn_width-13)=tlb_htw_req0_tag_q(tagpos_epn to tagpos_epn+epn_width-13) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_16MB) or + (htw_tag3_q(tagpos_epn to tagpos_epn+epn_width-19)=tlb_htw_req0_tag_q(tagpos_epn to tagpos_epn+epn_width-19) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1GB) + else '0'; +htw_resv0_tag3_epn_glob_match <= '1' when (htw_tag3_q(tagpos_epn+31 to tagpos_epn+epn_width-1)=tlb_htw_req0_tag_q(tagpos_epn+31 to tagpos_epn+epn_width-1) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_4KB) or + (htw_tag3_q(tagpos_epn+31 to tagpos_epn+epn_width-5)=tlb_htw_req0_tag_q(tagpos_epn+31 to tagpos_epn+epn_width-5) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_64KB) or + (htw_tag3_q(tagpos_epn+31 to tagpos_epn+epn_width-9)=tlb_htw_req0_tag_q(tagpos_epn+31 to tagpos_epn+epn_width-9) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1MB) or + (htw_tag3_q(tagpos_epn+31 to tagpos_epn+epn_width-13)=tlb_htw_req0_tag_q(tagpos_epn+31 to tagpos_epn+epn_width-13) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_16MB) or + (htw_tag3_q(tagpos_epn+31 to tagpos_epn+epn_width-19)=tlb_htw_req0_tag_q(tagpos_epn+31 to tagpos_epn+epn_width-19) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1GB) + else '0'; +htw_resv1_tag3_lpid_match <= '1' when (htw_tag3_q(tagpos_lpid to tagpos_lpid+lpid_width-1)=tlb_htw_req1_tag_q(tagpos_lpid to tagpos_lpid+lpid_width-1)) else '0'; +htw_resv1_tag3_pid_match <= '1' when (htw_tag3_q(tagpos_pid to tagpos_pid+pid_width-1)=tlb_htw_req1_tag_q(tagpos_pid to tagpos_pid+pid_width-1)) else '0'; +htw_resv1_tag3_as_match <= '1' when (htw_tag3_q(tagpos_as)=tlb_htw_req1_tag_q(tagpos_as)) else '0'; +htw_resv1_tag3_gs_match <= '1' when (htw_tag3_q(tagpos_gs)=tlb_htw_req1_tag_q(tagpos_gs)) else '0'; +htw_resv1_tag3_epn_loc_match <= '1' when (htw_tag3_q(tagpos_epn to tagpos_epn+epn_width-1)=tlb_htw_req1_tag_q(tagpos_epn to tagpos_epn+epn_width-1) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_4KB) or + (htw_tag3_q(tagpos_epn to tagpos_epn+epn_width-5)=tlb_htw_req1_tag_q(tagpos_epn to tagpos_epn+epn_width-5) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_64KB) or + (htw_tag3_q(tagpos_epn to tagpos_epn+epn_width-9)=tlb_htw_req1_tag_q(tagpos_epn to tagpos_epn+epn_width-9) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1MB) or + (htw_tag3_q(tagpos_epn to tagpos_epn+epn_width-13)=tlb_htw_req1_tag_q(tagpos_epn to tagpos_epn+epn_width-13) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_16MB) or + (htw_tag3_q(tagpos_epn to tagpos_epn+epn_width-19)=tlb_htw_req1_tag_q(tagpos_epn to tagpos_epn+epn_width-19) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1GB) + else '0'; +htw_resv1_tag3_epn_glob_match <= '1' when (htw_tag3_q(tagpos_epn+31 to tagpos_epn+epn_width-1)=tlb_htw_req1_tag_q(tagpos_epn+31 to tagpos_epn+epn_width-1) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_4KB) or + (htw_tag3_q(tagpos_epn+31 to tagpos_epn+epn_width-5)=tlb_htw_req1_tag_q(tagpos_epn+31 to tagpos_epn+epn_width-5) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_64KB) or + (htw_tag3_q(tagpos_epn+31 to tagpos_epn+epn_width-9)=tlb_htw_req1_tag_q(tagpos_epn+31 to tagpos_epn+epn_width-9) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1MB) or + (htw_tag3_q(tagpos_epn+31 to tagpos_epn+epn_width-13)=tlb_htw_req1_tag_q(tagpos_epn+31 to tagpos_epn+epn_width-13) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_16MB) or + (htw_tag3_q(tagpos_epn+31 to tagpos_epn+epn_width-19)=tlb_htw_req1_tag_q(tagpos_epn+31 to tagpos_epn+epn_width-19) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1GB) + else '0'; +htw_resv2_tag3_lpid_match <= '1' when (htw_tag3_q(tagpos_lpid to tagpos_lpid+lpid_width-1)=tlb_htw_req2_tag_q(tagpos_lpid to tagpos_lpid+lpid_width-1)) else '0'; +htw_resv2_tag3_pid_match <= '1' when (htw_tag3_q(tagpos_pid to tagpos_pid+pid_width-1)=tlb_htw_req2_tag_q(tagpos_pid to tagpos_pid+pid_width-1)) else '0'; +htw_resv2_tag3_as_match <= '1' when (htw_tag3_q(tagpos_as)=tlb_htw_req2_tag_q(tagpos_as)) else '0'; +htw_resv2_tag3_gs_match <= '1' when (htw_tag3_q(tagpos_gs)=tlb_htw_req2_tag_q(tagpos_gs)) else '0'; +htw_resv2_tag3_epn_loc_match <= '1' when (htw_tag3_q(tagpos_epn to tagpos_epn+epn_width-1)=tlb_htw_req2_tag_q(tagpos_epn to tagpos_epn+epn_width-1) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_4KB) or + (htw_tag3_q(tagpos_epn to tagpos_epn+epn_width-5)=tlb_htw_req2_tag_q(tagpos_epn to tagpos_epn+epn_width-5) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_64KB) or + (htw_tag3_q(tagpos_epn to tagpos_epn+epn_width-9)=tlb_htw_req2_tag_q(tagpos_epn to tagpos_epn+epn_width-9) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1MB) or + (htw_tag3_q(tagpos_epn to tagpos_epn+epn_width-13)=tlb_htw_req2_tag_q(tagpos_epn to tagpos_epn+epn_width-13) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_16MB) or + (htw_tag3_q(tagpos_epn to tagpos_epn+epn_width-19)=tlb_htw_req2_tag_q(tagpos_epn to tagpos_epn+epn_width-19) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1GB) + else '0'; +htw_resv2_tag3_epn_glob_match <= '1' when (htw_tag3_q(tagpos_epn+31 to tagpos_epn+epn_width-1)=tlb_htw_req2_tag_q(tagpos_epn+31 to tagpos_epn+epn_width-1) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_4KB) or + (htw_tag3_q(tagpos_epn+31 to tagpos_epn+epn_width-5)=tlb_htw_req2_tag_q(tagpos_epn+31 to tagpos_epn+epn_width-5) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_64KB) or + (htw_tag3_q(tagpos_epn+31 to tagpos_epn+epn_width-9)=tlb_htw_req2_tag_q(tagpos_epn+31 to tagpos_epn+epn_width-9) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1MB) or + (htw_tag3_q(tagpos_epn+31 to tagpos_epn+epn_width-13)=tlb_htw_req2_tag_q(tagpos_epn+31 to tagpos_epn+epn_width-13) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_16MB) or + (htw_tag3_q(tagpos_epn+31 to tagpos_epn+epn_width-19)=tlb_htw_req2_tag_q(tagpos_epn+31 to tagpos_epn+epn_width-19) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1GB) + else '0'; +htw_resv3_tag3_lpid_match <= '1' when (htw_tag3_q(tagpos_lpid to tagpos_lpid+lpid_width-1)=tlb_htw_req3_tag_q(tagpos_lpid to tagpos_lpid+lpid_width-1)) else '0'; +htw_resv3_tag3_pid_match <= '1' when (htw_tag3_q(tagpos_pid to tagpos_pid+pid_width-1)=tlb_htw_req3_tag_q(tagpos_pid to tagpos_pid+pid_width-1)) else '0'; +htw_resv3_tag3_as_match <= '1' when (htw_tag3_q(tagpos_as)=tlb_htw_req3_tag_q(tagpos_as)) else '0'; +htw_resv3_tag3_gs_match <= '1' when (htw_tag3_q(tagpos_gs)=tlb_htw_req3_tag_q(tagpos_gs)) else '0'; +htw_resv3_tag3_epn_loc_match <= '1' when (htw_tag3_q(tagpos_epn to tagpos_epn+epn_width-1)=tlb_htw_req3_tag_q(tagpos_epn to tagpos_epn+epn_width-1) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_4KB) or + (htw_tag3_q(tagpos_epn to tagpos_epn+epn_width-5)=tlb_htw_req3_tag_q(tagpos_epn to tagpos_epn+epn_width-5) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_64KB) or + (htw_tag3_q(tagpos_epn to tagpos_epn+epn_width-9)=tlb_htw_req3_tag_q(tagpos_epn to tagpos_epn+epn_width-9) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1MB) or + (htw_tag3_q(tagpos_epn to tagpos_epn+epn_width-13)=tlb_htw_req3_tag_q(tagpos_epn to tagpos_epn+epn_width-13) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_16MB) or + (htw_tag3_q(tagpos_epn to tagpos_epn+epn_width-19)=tlb_htw_req3_tag_q(tagpos_epn to tagpos_epn+epn_width-19) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1GB) + else '0'; +htw_resv3_tag3_epn_glob_match <= '1' when (htw_tag3_q(tagpos_epn+31 to tagpos_epn+epn_width-1)=tlb_htw_req3_tag_q(tagpos_epn+31 to tagpos_epn+epn_width-1) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_4KB) or + (htw_tag3_q(tagpos_epn+31 to tagpos_epn+epn_width-5)=tlb_htw_req3_tag_q(tagpos_epn+31 to tagpos_epn+epn_width-5) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_64KB) or + (htw_tag3_q(tagpos_epn+31 to tagpos_epn+epn_width-9)=tlb_htw_req3_tag_q(tagpos_epn+31 to tagpos_epn+epn_width-9) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1MB) or + (htw_tag3_q(tagpos_epn+31 to tagpos_epn+epn_width-13)=tlb_htw_req3_tag_q(tagpos_epn+31 to tagpos_epn+epn_width-13) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_16MB) or + (htw_tag3_q(tagpos_epn+31 to tagpos_epn+epn_width-19)=tlb_htw_req3_tag_q(tagpos_epn+31 to tagpos_epn+epn_width-19) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1GB) + else '0'; +pte0_score_act <= (or_reduce(pte0_seq_q) or or_reduce(htw_seq_q) or mmucr2_act_override) and xu_mm_ccr2_notlb_b; +pte0_score_ptr_d <= htw_lsuptr_q when pte0_seq_score_load='1' + else pte0_score_ptr_q; +pte0_score_cl_offset_d <= pte_ra_0(58 to 60) when pte0_seq_score_load='1' and htw_lsuptr_q="00" + else pte_ra_1(58 to 60) when pte0_seq_score_load='1' and htw_lsuptr_q="01" + else pte_ra_2(58 to 60) when pte0_seq_score_load='1' and htw_lsuptr_q="10" + else pte_ra_3(58 to 60) when pte0_seq_score_load='1' and htw_lsuptr_q="11" + else pte0_score_cl_offset_q; +pte0_score_ibit_d <= tlb_htw_req0_way_q(waypos_wimge+1) when pte0_seq_score_load='1' and htw_lsuptr_q="00" + else tlb_htw_req1_way_q(waypos_wimge+1) when pte0_seq_score_load='1' and htw_lsuptr_q="01" + else tlb_htw_req2_way_q(waypos_wimge+1) when pte0_seq_score_load='1' and htw_lsuptr_q="10" + else tlb_htw_req3_way_q(waypos_wimge+1) when pte0_seq_score_load='1' and htw_lsuptr_q="11" + else pte0_score_ibit_q; +pte0_score_pending_d <= '1' when pte0_seq_score_load='1' + else '0' when pte0_seq_score_done='1' + else pte0_score_pending_q; +pte0_score_qwbeat_d(0) <= '0' when pte0_seq_score_load='1' or pte0_seq_data_retry='1' + else '1' when (pte0_score_pending_q='1' and reld_data_vld_tp2_q='1' and reld_ditc_tp2_q='0' + and reld_core_tag_tp2_q=Core_Tag0_Value and reld_qw_tp2_q="00") + else pte0_score_qwbeat_q(0); +pte0_score_qwbeat_d(1) <= '0' when pte0_seq_score_load='1' or pte0_seq_data_retry='1' + else '1' when (pte0_score_pending_q='1' and reld_data_vld_tp2_q='1' and reld_ditc_tp2_q='0' + and reld_core_tag_tp2_q=Core_Tag0_Value and reld_qw_tp2_q="01") + else pte0_score_qwbeat_q(1); +pte0_score_qwbeat_d(2) <= '0' when pte0_seq_score_load='1' or pte0_seq_data_retry='1' + else '1' when (pte0_score_pending_q='1' and reld_data_vld_tp2_q='1' and reld_ditc_tp2_q='0' + and reld_core_tag_tp2_q=Core_Tag0_Value and reld_qw_tp2_q="10") + else pte0_score_qwbeat_q(2); +pte0_score_qwbeat_d(3) <= '0' when pte0_seq_score_load='1' or pte0_seq_data_retry='1' + else '1' when (pte0_score_pending_q='1' and reld_data_vld_tp2_q='1' and reld_ditc_tp2_q='0' + and reld_core_tag_tp2_q=Core_Tag0_Value and reld_qw_tp2_q="11") + else pte0_score_qwbeat_q(3); +pte0_score_error_d(0) <= '0' when pte0_seq_score_load='1' + else '1' when (pte0_score_pending_q='1' and reld_data_vld_tp2_q='1' and reld_ditc_tp2_q='0' + and reld_core_tag_tp2_q=Core_Tag0_Value + and reld_ecc_err_tp2_q='1') + else pte0_score_error_q(0); +pte0_score_error_d(1) <= '0' when pte0_seq_score_load='1' + else '1' when (pte0_score_pending_q='1' and reld_data_vld_tp2_q='1' and reld_ditc_tp2_q='0' + and reld_core_tag_tp2_q=Core_Tag0_Value + and reld_ecc_err_ue_tp2_q='1') + else pte0_score_error_q(1); +pte0_score_error_d(2) <= '0' when pte0_seq_score_load='1' + else '1' when pte0_seq_data_retry='1' + else pte0_score_error_q(2); +pte0_score_dataval_d <= '0' when pte0_seq_score_load='1' or pte0_seq_data_retry='1' + else '1' when (pte0_score_pending_q='1' and reld_data_vld_tp2_q='1' and reld_ditc_tp2_q='0' + and reld_crit_qw_tp2_q='1' and reld_qw_tp2_q=pte0_score_cl_offset_q(58 to 59) + and reld_core_tag_tp2_q=Core_Tag0_Value) + else pte0_score_dataval_q; +pte1_score_act <= (or_reduce(pte1_seq_q) or or_reduce(htw_seq_q) or mmucr2_act_override) and xu_mm_ccr2_notlb_b; +pte1_score_ptr_d <= htw_lsuptr_q when pte1_seq_score_load='1' + else pte1_score_ptr_q; +pte1_score_cl_offset_d <= pte_ra_0(58 to 60) when pte1_seq_score_load='1' and htw_lsuptr_q="00" + else pte_ra_1(58 to 60) when pte1_seq_score_load='1' and htw_lsuptr_q="01" + else pte_ra_2(58 to 60) when pte1_seq_score_load='1' and htw_lsuptr_q="10" + else pte_ra_3(58 to 60) when pte1_seq_score_load='1' and htw_lsuptr_q="11" + else pte1_score_cl_offset_q; +pte1_score_ibit_d <= tlb_htw_req0_way_q(waypos_wimge+1) when pte1_seq_score_load='1' and htw_lsuptr_q="00" + else tlb_htw_req1_way_q(waypos_wimge+1) when pte1_seq_score_load='1' and htw_lsuptr_q="01" + else tlb_htw_req2_way_q(waypos_wimge+1) when pte1_seq_score_load='1' and htw_lsuptr_q="10" + else tlb_htw_req3_way_q(waypos_wimge+1) when pte1_seq_score_load='1' and htw_lsuptr_q="11" + else pte1_score_ibit_q; +pte1_score_pending_d <= '1' when pte1_seq_score_load='1' + else '0' when pte1_seq_score_done='1' + else pte1_score_pending_q; +pte1_score_qwbeat_d(0) <= '0' when pte1_seq_score_load='1' or pte1_seq_data_retry='1' + else '1' when (pte1_score_pending_q='1' and reld_data_vld_tp2_q='1' and reld_ditc_tp2_q='0' + and reld_core_tag_tp2_q=Core_Tag1_Value and reld_qw_tp2_q="00") + else pte1_score_qwbeat_q(0); +pte1_score_qwbeat_d(1) <= '0' when pte1_seq_score_load='1' or pte1_seq_data_retry='1' + else '1' when (pte1_score_pending_q='1' and reld_data_vld_tp2_q='1' and reld_ditc_tp2_q='0' + and reld_core_tag_tp2_q=Core_Tag1_Value and reld_qw_tp2_q="01") + else pte1_score_qwbeat_q(1); +pte1_score_qwbeat_d(2) <= '0' when pte1_seq_score_load='1' or pte1_seq_data_retry='1' + else '1' when (pte1_score_pending_q='1' and reld_data_vld_tp2_q='1' and reld_ditc_tp2_q='0' + and reld_core_tag_tp2_q=Core_Tag1_Value and reld_qw_tp2_q="10") + else pte1_score_qwbeat_q(2); +pte1_score_qwbeat_d(3) <= '0' when pte1_seq_score_load='1' or pte1_seq_data_retry='1' + else '1' when (pte1_score_pending_q='1' and reld_data_vld_tp2_q='1' and reld_ditc_tp2_q='0' + and reld_core_tag_tp2_q=Core_Tag1_Value and reld_qw_tp2_q="11") + else pte1_score_qwbeat_q(3); +pte1_score_error_d(0) <= '0' when pte1_seq_score_load='1' + else '1' when (pte1_score_pending_q='1' and reld_data_vld_tp2_q='1' and reld_ditc_tp2_q='0' + and reld_core_tag_tp2_q=Core_Tag1_Value + and reld_ecc_err_tp2_q='1') + else pte1_score_error_q(0); +pte1_score_error_d(1) <= '0' when pte1_seq_score_load='1' + else '1' when (pte1_score_pending_q='1' and reld_data_vld_tp2_q='1' and reld_ditc_tp2_q='0' + and reld_core_tag_tp2_q=Core_Tag1_Value + and reld_ecc_err_ue_tp2_q='1') + else pte1_score_error_q(1); +pte1_score_error_d(2) <= '0' when pte1_seq_score_load='1' + else '1' when pte1_seq_data_retry='1' + else pte1_score_error_q(2); +pte1_score_dataval_d <= '0' when pte1_seq_score_load='1' or pte1_seq_data_retry='1' + else '1' when (pte1_score_pending_q='1' and reld_data_vld_tp2_q='1' and reld_ditc_tp2_q='0' + and reld_crit_qw_tp2_q='1' and reld_qw_tp2_q=pte1_score_cl_offset_q(58 to 59) + and reld_core_tag_tp2_q=Core_Tag1_Value) + else pte1_score_dataval_q; +htw_inptr_d <= "01" when htw_inptr_q="00" and tlb_htw_req0_valid_q='0' and tlb_htw_req1_valid_q='0' and tlb_htw_req_valid='1' + else "10" when htw_inptr_q="00" and tlb_htw_req0_valid_q='0' and tlb_htw_req1_valid_q='1' and tlb_htw_req2_valid_q='0' and tlb_htw_req_valid='1' + else "11" when htw_inptr_q="00" and tlb_htw_req0_valid_q='0' and tlb_htw_req1_valid_q='1' and tlb_htw_req2_valid_q='1' and tlb_htw_req3_valid_q='0' and tlb_htw_req_valid='1' + else "10" when htw_inptr_q="01" and tlb_htw_req1_valid_q='0' and tlb_htw_req2_valid_q='0' and tlb_htw_req_valid='1' + else "11" when htw_inptr_q="01" and tlb_htw_req1_valid_q='0' and tlb_htw_req2_valid_q='1' and tlb_htw_req3_valid_q='0' and tlb_htw_req_valid='1' + else "00" when htw_inptr_q="01" and tlb_htw_req1_valid_q='0' and tlb_htw_req2_valid_q='1' and tlb_htw_req3_valid_q='1' and tlb_htw_req0_valid_q='0' and tlb_htw_req_valid='1' + else "11" when htw_inptr_q="10" and tlb_htw_req2_valid_q='0' and tlb_htw_req3_valid_q='0' and tlb_htw_req_valid='1' + else "00" when htw_inptr_q="10" and tlb_htw_req2_valid_q='0' and tlb_htw_req3_valid_q='1' and tlb_htw_req0_valid_q='0' and tlb_htw_req_valid='1' + else "01" when htw_inptr_q="10" and tlb_htw_req2_valid_q='0' and tlb_htw_req3_valid_q='1' and tlb_htw_req0_valid_q='1' and tlb_htw_req1_valid_q='0' and tlb_htw_req_valid='1' + else "00" when htw_inptr_q="11" and tlb_htw_req3_valid_q='0' and tlb_htw_req0_valid_q='0' and tlb_htw_req_valid='1' + else "01" when htw_inptr_q="11" and tlb_htw_req3_valid_q='0' and tlb_htw_req0_valid_q='1' and tlb_htw_req1_valid_q='0' and tlb_htw_req_valid='1' + else "10" when htw_inptr_q="11" and tlb_htw_req3_valid_q='0' and tlb_htw_req0_valid_q='1' and tlb_htw_req1_valid_q='1' and tlb_htw_req2_valid_q='0' and tlb_htw_req_valid='1' + else pte0_score_ptr_q when ptereload_ptr_q='0' and ptereload_req_taken='1' + else pte1_score_ptr_q when ptereload_ptr_q='1' and ptereload_req_taken='1' + else htw_inptr_q; +htw_lsuptr_d <= "01" when htw_lsuptr_q="00" and tlb_htw_req_valid_vec(0)='0' and tlb_htw_req_valid_vec(1)='1' + else "10" when htw_lsuptr_q="00" and tlb_htw_req_valid_vec(0)='0' and tlb_htw_req_valid_vec(1)='0' and tlb_htw_req_valid_vec(2)='1' + else "11" when htw_lsuptr_q="00" and tlb_htw_req_valid_vec(0)='0' and tlb_htw_req_valid_vec(1)='0' and tlb_htw_req_valid_vec(2)='0' and tlb_htw_req_valid_vec(3)='1' + else "10" when htw_lsuptr_q="01" and tlb_htw_req_valid_vec(1)='0' and tlb_htw_req_valid_vec(2)='1' + else "11" when htw_lsuptr_q="01" and tlb_htw_req_valid_vec(1)='0' and tlb_htw_req_valid_vec(2)='0' and tlb_htw_req_valid_vec(3)='1' + else "00" when htw_lsuptr_q="01" and tlb_htw_req_valid_vec(1)='0' and tlb_htw_req_valid_vec(2)='0' and tlb_htw_req_valid_vec(3)='0' and tlb_htw_req_valid_vec(0)='1' + else "11" when htw_lsuptr_q="10" and tlb_htw_req_valid_vec(2)='0' and tlb_htw_req_valid_vec(3)='1' + else "00" when htw_lsuptr_q="10" and tlb_htw_req_valid_vec(2)='0' and tlb_htw_req_valid_vec(3)='0' and tlb_htw_req_valid_vec(0)='1' + else "01" when htw_lsuptr_q="10" and tlb_htw_req_valid_vec(2)='0' and tlb_htw_req_valid_vec(3)='0' and tlb_htw_req_valid_vec(0)='0' and tlb_htw_req_valid_vec(1)='1' + else "00" when htw_lsuptr_q="11" and tlb_htw_req_valid_vec(3)='0' and tlb_htw_req_valid_vec(0)='1' + else "01" when htw_lsuptr_q="11" and tlb_htw_req_valid_vec(3)='0' and tlb_htw_req_valid_vec(0)='0' and tlb_htw_req_valid_vec(1)='1' + else "10" when htw_lsuptr_q="11" and tlb_htw_req_valid_vec(3)='0' and tlb_htw_req_valid_vec(0)='0' and tlb_htw_req_valid_vec(1)='0' and tlb_htw_req_valid_vec(2)='1' + else htw_lsuptr_q; +tlb_htw_req_valid_notpend_vec <= (tlb_htw_req0_valid_q and not tlb_htw_req0_pending_q) & + (tlb_htw_req1_valid_q and not tlb_htw_req1_pending_q) & + (tlb_htw_req2_valid_q and not tlb_htw_req2_pending_q) & + (tlb_htw_req3_valid_q and not tlb_htw_req3_pending_q); +htw_lsuptr_alt_d <= "01" when htw_lsuptr_q="00" and tlb_htw_req_valid_notpend_vec(0)='1' and htw_lsu_req_taken='1' + else "10" when htw_lsuptr_q="01" and tlb_htw_req_valid_notpend_vec(1)='1' and htw_lsu_req_taken='1' + else "11" when htw_lsuptr_q="10" and tlb_htw_req_valid_notpend_vec(2)='1' and htw_lsu_req_taken='1' + else "00" when htw_lsuptr_q="11" and tlb_htw_req_valid_notpend_vec(3)='1' and htw_lsu_req_taken='1' + else "01" when htw_lsuptr_q="00" and tlb_htw_req_valid_notpend_vec(0)='0' and tlb_htw_req_valid_notpend_vec(1)='1' + else "10" when htw_lsuptr_q="00" and tlb_htw_req_valid_notpend_vec(0)='0' and tlb_htw_req_valid_notpend_vec(1)='0' and tlb_htw_req_valid_notpend_vec(2)='1' + else "11" when htw_lsuptr_q="00" and tlb_htw_req_valid_notpend_vec(0)='0' and tlb_htw_req_valid_notpend_vec(1)='0' and tlb_htw_req_valid_notpend_vec(2)='0' and tlb_htw_req_valid_notpend_vec(3)='1' + else "10" when htw_lsuptr_q="01" and tlb_htw_req_valid_notpend_vec(1)='0' and tlb_htw_req_valid_notpend_vec(2)='1' + else "11" when htw_lsuptr_q="01" and tlb_htw_req_valid_notpend_vec(1)='0' and tlb_htw_req_valid_notpend_vec(2)='0' and tlb_htw_req_valid_notpend_vec(3)='1' + else "00" when htw_lsuptr_q="01" and tlb_htw_req_valid_notpend_vec(1)='0' and tlb_htw_req_valid_notpend_vec(2)='0' and tlb_htw_req_valid_notpend_vec(3)='0' and tlb_htw_req_valid_notpend_vec(0)='1' + else "11" when htw_lsuptr_q="10" and tlb_htw_req_valid_notpend_vec(2)='0' and tlb_htw_req_valid_notpend_vec(3)='1' + else "00" when htw_lsuptr_q="10" and tlb_htw_req_valid_notpend_vec(2)='0' and tlb_htw_req_valid_notpend_vec(3)='0' and tlb_htw_req_valid_notpend_vec(0)='1' + else "01" when htw_lsuptr_q="10" and tlb_htw_req_valid_notpend_vec(2)='0' and tlb_htw_req_valid_notpend_vec(3)='0' and tlb_htw_req_valid_notpend_vec(0)='0' and tlb_htw_req_valid_notpend_vec(1)='1' + else "00" when htw_lsuptr_q="11" and tlb_htw_req_valid_notpend_vec(3)='0' and tlb_htw_req_valid_notpend_vec(0)='1' + else "01" when htw_lsuptr_q="11" and tlb_htw_req_valid_notpend_vec(3)='0' and tlb_htw_req_valid_notpend_vec(0)='0' and tlb_htw_req_valid_notpend_vec(1)='1' + else "10" when htw_lsuptr_q="11" and tlb_htw_req_valid_notpend_vec(3)='0' and tlb_htw_req_valid_notpend_vec(0)='0' and tlb_htw_req_valid_notpend_vec(1)='0' and tlb_htw_req_valid_notpend_vec(2)='1' + else htw_lsuptr_q; +pte_load_ptr_d <= '1' when ptereload_ptr_q='1' and pte1_score_pending_q='1' and pte0_score_pending_d='1' and ptereload_req_taken='1' + else '0' when ptereload_ptr_q='0' and pte0_score_pending_q='1' and pte1_score_pending_d='1' and ptereload_req_taken='1' + else '1' when pte_load_ptr_q='0' and pte0_seq_score_load='1' and pte1_score_pending_q='0' + else '0' when pte_load_ptr_q='1' and pte1_seq_score_load='1' and pte0_score_pending_q='0' + else pte_load_ptr_q; +ptereload_ptr_d <= '1' when ptereload_ptr_q='0' and ptereload_req_taken='1' + else '1' when ptereload_ptr_q='0' and pte0_reload_req_valid='0' and pte1_reload_req_valid='1' + else '0' when ptereload_ptr_q='1' and ptereload_req_taken='1' + else '0' when ptereload_ptr_q='1' and pte0_reload_req_valid='1' and pte1_reload_req_valid='0' + else ptereload_ptr_q; +htw_lsu_ttype_d <= "11" when (pte_load_ptr_q='1' and htw_seq_load_pteaddr='1') + else "10" when htw_seq_load_pteaddr='1' + else htw_lsu_ttype_q; +htw_lsu_thdid_d <= tlb_htw_req0_tag_q(tagpos_thdid to tagpos_thdid+thdid_width-1) when htw_lsuptr_q="00" and tlb_htw_req0_valid_q='1' and htw_seq_load_pteaddr='1' + else tlb_htw_req1_tag_q(tagpos_thdid to tagpos_thdid+thdid_width-1) when htw_lsuptr_q="01" and tlb_htw_req1_valid_q='1' and htw_seq_load_pteaddr='1' + else tlb_htw_req2_tag_q(tagpos_thdid to tagpos_thdid+thdid_width-1) when htw_lsuptr_q="10" and tlb_htw_req2_valid_q='1' and htw_seq_load_pteaddr='1' + else tlb_htw_req3_tag_q(tagpos_thdid to tagpos_thdid+thdid_width-1) when htw_lsuptr_q="11" and tlb_htw_req3_valid_q='1' and htw_seq_load_pteaddr='1' + else htw_lsu_thdid_q; +htw_lsu_wimge_d <= tlb_htw_req0_way_q(waypos_wimge to waypos_wimge+4) when htw_lsuptr_q="00" and tlb_htw_req0_valid_q='1' and htw_seq_load_pteaddr='1' + else tlb_htw_req1_way_q(waypos_wimge to waypos_wimge+4) when htw_lsuptr_q="01" and tlb_htw_req1_valid_q='1' and htw_seq_load_pteaddr='1' + else tlb_htw_req2_way_q(waypos_wimge to waypos_wimge+4) when htw_lsuptr_q="10" and tlb_htw_req2_valid_q='1' and htw_seq_load_pteaddr='1' + else tlb_htw_req3_way_q(waypos_wimge to waypos_wimge+4) when htw_lsuptr_q="11" and tlb_htw_req3_valid_q='1' and htw_seq_load_pteaddr='1' + else htw_lsu_wimge_q; +htw_lsu_u_d <= tlb_htw_req0_way_q(waypos_ubits to waypos_ubits+3) when htw_lsuptr_q="00" and tlb_htw_req0_valid_q='1' and htw_seq_load_pteaddr='1' + else tlb_htw_req1_way_q(waypos_ubits to waypos_ubits+3) when htw_lsuptr_q="01" and tlb_htw_req1_valid_q='1' and htw_seq_load_pteaddr='1' + else tlb_htw_req2_way_q(waypos_ubits to waypos_ubits+3) when htw_lsuptr_q="10" and tlb_htw_req2_valid_q='1' and htw_seq_load_pteaddr='1' + else tlb_htw_req3_way_q(waypos_ubits to waypos_ubits+3) when htw_lsuptr_q="11" and tlb_htw_req3_valid_q='1' and htw_seq_load_pteaddr='1' + else htw_lsu_u_q; +htw_lsu_addr_d <= pte_ra_0 when htw_lsuptr_q="00" and tlb_htw_req0_valid_q='1' and htw_seq_load_pteaddr='1' + else pte_ra_1 when htw_lsuptr_q="01" and tlb_htw_req1_valid_q='1' and htw_seq_load_pteaddr='1' + else pte_ra_2 when htw_lsuptr_q="10" and tlb_htw_req2_valid_q='1' and htw_seq_load_pteaddr='1' + else pte_ra_3 when htw_lsuptr_q="11" and tlb_htw_req3_valid_q='1' and htw_seq_load_pteaddr='1' + else htw_lsu_addr_q; +htw_lsu_act <= (or_reduce(htw_seq_q) or mmucr2_act_override) and xu_mm_ccr2_notlb_b; +htw_lsu_thdid <= htw_lsu_thdid_q; +htw_dbg_lsu_thdid(0) <= htw_lsu_thdid_q(2) or htw_lsu_thdid_q(3); +htw_dbg_lsu_thdid(1) <= htw_lsu_thdid_q(1) or htw_lsu_thdid_q(3); +htw_lsu_ttype <= htw_lsu_ttype_q; +htw_lsu_wimge <= htw_lsu_wimge_q; +htw_lsu_u <= htw_lsu_u_q; +htw_lsu_addr <= htw_lsu_addr_q; +reld_core_tag_tm1_d <= an_ac_reld_core_tag; +reld_qw_tm1_d <= an_ac_reld_qw; +reld_crit_qw_tm1_d <= an_ac_reld_crit_qw; +reld_ditc_tm1_d <= an_ac_reld_ditc; +reld_data_vld_tm1_d <= an_ac_reld_data_vld; +reld_core_tag_t_d <= reld_core_tag_tm1_q; +reld_qw_t_d <= reld_qw_tm1_q; +reld_crit_qw_t_d <= reld_crit_qw_tm1_q; +reld_ditc_t_d <= reld_ditc_tm1_q; +reld_data_vld_t_d <= reld_data_vld_tm1_q; +pte0_reld_for_me_tm1 <= '1' when (reld_data_vld_tm1_q='1' and reld_ditc_tm1_q='0' and reld_crit_qw_tm1_q='1' + and reld_qw_tm1_q=pte0_score_cl_offset_q(58 to 59) and reld_core_tag_tm1_q=Core_Tag0_Value) + else '0'; +pte1_reld_for_me_tm1 <= '1' when (reld_data_vld_tm1_q='1' and reld_ditc_tm1_q='0' and reld_crit_qw_tm1_q='1' + and reld_qw_tm1_q=pte1_score_cl_offset_q(58 to 59) and reld_core_tag_tm1_q=Core_Tag1_Value) + else '0'; +reld_core_tag_tp1_d <= reld_core_tag_t_q; +reld_qw_tp1_d <= reld_qw_t_q; +reld_crit_qw_tp1_d <= reld_crit_qw_t_q; +reld_ditc_tp1_d <= reld_ditc_t_q; +reld_data_vld_tp1_d <= reld_data_vld_t_q; +reld_data_tp1_d <= an_ac_reld_data; +reld_core_tag_tp2_d <= reld_core_tag_tp1_q; +reld_qw_tp2_d <= reld_qw_tp1_q; +reld_crit_qw_tp2_d <= reld_crit_qw_tp1_q; +reld_ditc_tp2_d <= reld_ditc_tp1_q; +reld_data_vld_tp2_d <= reld_data_vld_tp1_q; +reld_data_tp2_d <= reld_data_tp1_q; +reld_ecc_err_tp2_d <= an_ac_reld_ecc_err; +reld_ecc_err_ue_tp2_d <= an_ac_reld_ecc_err_ue; +pte0_reld_for_me_tp2 <= '1' when (reld_data_vld_tp2_q='1' and reld_ditc_tp2_q='0' and reld_crit_qw_tp2_q='1' + and reld_qw_tp2_q=pte0_score_cl_offset_q(58 to 59) and reld_core_tag_tp2_q=Core_Tag0_Value) + else '0'; +pte0_reld_data_tp3_d <= reld_data_tp2_q(0 to 63) when (pte0_reld_for_me_tp2='1' and pte0_score_cl_offset_q(60)='0') + else reld_data_tp2_q(64 to 127) when (pte0_reld_for_me_tp2='1' and pte0_score_cl_offset_q(60)='1') + else pte0_reld_data_tp3_q; +pte1_reld_for_me_tp2 <= '1' when (reld_data_vld_tp2_q='1' and reld_ditc_tp2_q='0' and reld_crit_qw_tp2_q='1' + and reld_qw_tp2_q=pte1_score_cl_offset_q(58 to 59) and reld_core_tag_tp2_q=Core_Tag1_Value) + else '0'; +pte1_reld_data_tp3_d <= reld_data_tp2_q(0 to 63) when (pte1_reld_for_me_tp2='1' and pte1_score_cl_offset_q(60)='0') + else reld_data_tp2_q(64 to 127) when (pte1_reld_for_me_tp2='1' and pte1_score_cl_offset_q(60)='1') + else pte1_reld_data_tp3_q; +reld_act <= (or_reduce(pte0_seq_q) or or_reduce(pte1_seq_q) or mmucr2_act_override) and xu_mm_ccr2_notlb_b; +pte0_reld_act <= (or_reduce(pte0_seq_q) or mmucr2_act_override) and xu_mm_ccr2_notlb_b; +pte1_reld_act <= (or_reduce(pte1_seq_q) or mmucr2_act_override) and xu_mm_ccr2_notlb_b; +ptereload_req_valid <= '0' when (htw_tag4_clr_resv_q/="0000" or htw_tag5_clr_resv_q/="0000") + else pte1_reload_req_valid when ptereload_ptr_q='1' + else pte0_reload_req_valid; +ptereload_req_tag <= tlb_htw_req1_tag_q when ((ptereload_ptr_q='0' and pte0_score_ptr_q="01") or + (ptereload_ptr_q='1' and pte1_score_ptr_q="01")) + else tlb_htw_req2_tag_q when ((ptereload_ptr_q='0' and pte0_score_ptr_q="10") or + (ptereload_ptr_q='1' and pte1_score_ptr_q="10")) + else tlb_htw_req3_tag_q when ((ptereload_ptr_q='0' and pte0_score_ptr_q="11") or + (ptereload_ptr_q='1' and pte1_score_ptr_q="11")) + else tlb_htw_req0_tag_q; +ptereload_req_pte <= pte1_reld_data_tp3_q when ptereload_ptr_q='1' + else pte0_reld_data_tp3_q; +htw_tag4_clr_resv_terms <= (others => '0'); +htw_dbg_seq_idle <= htw_seq_idle; +htw_dbg_pte0_seq_idle <= pte0_seq_idle; +htw_dbg_pte1_seq_idle <= pte1_seq_idle; +htw_dbg_seq_q <= htw_seq_q; +htw_dbg_inptr_q <= htw_inptr_q; +htw_dbg_pte0_seq_q <= pte0_seq_q; +htw_dbg_pte1_seq_q <= pte1_seq_q; +htw_dbg_ptereload_ptr_q <= ptereload_ptr_q; +htw_dbg_lsuptr_q <= htw_lsuptr_q; +htw_dbg_req_valid_q <= tlb_htw_req0_valid_q & tlb_htw_req1_valid_q & tlb_htw_req2_valid_q & tlb_htw_req3_valid_q; +htw_dbg_resv_valid_vec <= htw_resv_valid_vec; +htw_dbg_tag4_clr_resv_q <= htw_tag4_clr_resv_q; +htw_dbg_tag4_clr_resv_terms <= htw_tag4_clr_resv_terms; +htw_dbg_pte0_score_ptr_q <= pte0_score_ptr_q; +htw_dbg_pte0_score_cl_offset_q <= pte0_score_cl_offset_q; +htw_dbg_pte0_score_error_q <= pte0_score_error_q; +htw_dbg_pte0_score_qwbeat_q <= pte0_score_qwbeat_q; +htw_dbg_pte0_score_pending_q <= pte0_score_pending_q; +htw_dbg_pte0_score_ibit_q <= pte0_score_ibit_q; +htw_dbg_pte0_score_dataval_q <= pte0_score_dataval_q; +htw_dbg_pte0_reld_for_me_tm1 <= pte0_reld_for_me_tm1; +htw_dbg_pte1_score_ptr_q <= pte1_score_ptr_q; +htw_dbg_pte1_score_cl_offset_q <= pte1_score_cl_offset_q; +htw_dbg_pte1_score_error_q <= pte1_score_error_q; +htw_dbg_pte1_score_qwbeat_q <= pte1_score_qwbeat_q; +htw_dbg_pte1_score_pending_q <= pte1_score_pending_q; +htw_dbg_pte1_score_ibit_q <= pte1_score_ibit_q; +htw_dbg_pte1_score_dataval_q <= pte1_score_dataval_q; +htw_dbg_pte1_reld_for_me_tm1 <= pte1_reld_for_me_tm1; +unused_dc(0) <= or_reduce(LCB_DELAY_LCLKR_DC(1 TO 4)); +unused_dc(1) <= or_reduce(LCB_MPW1_DC_B(1 TO 4)); +unused_dc(2) <= PC_FUNC_SL_FORCE; +unused_dc(3) <= PC_FUNC_SL_THOLD_0_B; +unused_dc(4) <= TC_SCAN_DIS_DC_B; +unused_dc(5) <= TC_SCAN_DIAG_DC; +unused_dc(6) <= TC_LBIST_EN_DC; +unused_dc(7) <= or_reduce(TLB_HTW_REQ_TAG(104 TO 105)); +unused_dc(8) <= HTW_TAG3_Q(70); +unused_dc(9) <= HTW_TAG3_Q(73); +unused_dc(10) <= or_reduce(HTW_TAG3_Q(82 TO 85)); +unused_dc(11) <= HTW_TAG3_Q(87); +unused_dc(12) <= or_reduce(HTW_TAG3_Q(98 TO 103)); +unused_dc(13) <= or_reduce(HTW_TAG3_Q(106 TO 109)); +unused_dc(14) <= PTE0_RELD_ENABLE_LO_TP2 or PTE0_RELD_ENABLE_HI_TP2; +unused_dc(15) <= PTE1_RELD_ENABLE_LO_TP2 or PTE1_RELD_ENABLE_HI_TP2; +unused_dc(16 TO 19) <= tlb_htw_req0_pending_q & tlb_htw_req1_pending_q & tlb_htw_req2_pending_q & tlb_htw_req3_pending_q; +unused_dc(20 TO 21) <= htw_lsuptr_alt_d; +tlb_htw_req0_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_htw_req0_valid_offset), + scout => sov_0(tlb_htw_req0_valid_offset), + din => tlb_htw_req0_valid_d, + dout => tlb_htw_req0_valid_q); +tlb_htw_req0_pending_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_htw_req0_pending_offset), + scout => sov_0(tlb_htw_req0_pending_offset), + din => tlb_htw_req0_pending_d, + dout => tlb_htw_req0_pending_q); +tlb_htw_req0_tag_latch: tri_rlmreg_p + generic map (width => tlb_htw_req0_tag_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_htw_req0_tag_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_htw_req0_tag_offset to tlb_htw_req0_tag_offset+tlb_htw_req0_tag_q'length-1), + scout => sov_0(tlb_htw_req0_tag_offset to tlb_htw_req0_tag_offset+tlb_htw_req0_tag_q'length-1), + din => tlb_htw_req0_tag_d, + dout => tlb_htw_req0_tag_q ); +tlb_htw_req0_way_latch: tri_rlmreg_p + generic map (width => tlb_htw_req0_way_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(24+0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_htw_req0_way_offset to tlb_htw_req0_way_offset+tlb_htw_req0_way_q'length-1), + scout => sov_0(tlb_htw_req0_way_offset to tlb_htw_req0_way_offset+tlb_htw_req0_way_q'length-1), + din => tlb_htw_req0_way_d, + dout => tlb_htw_req0_way_q ); +tlb_htw_req1_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_htw_req1_valid_offset), + scout => sov_0(tlb_htw_req1_valid_offset), + din => tlb_htw_req1_valid_d, + dout => tlb_htw_req1_valid_q); +tlb_htw_req1_pending_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_htw_req1_pending_offset), + scout => sov_0(tlb_htw_req1_pending_offset), + din => tlb_htw_req1_pending_d, + dout => tlb_htw_req1_pending_q); +tlb_htw_req1_tag_latch: tri_rlmreg_p + generic map (width => tlb_htw_req1_tag_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_htw_req1_tag_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_htw_req1_tag_offset to tlb_htw_req1_tag_offset+tlb_htw_req1_tag_q'length-1), + scout => sov_0(tlb_htw_req1_tag_offset to tlb_htw_req1_tag_offset+tlb_htw_req1_tag_q'length-1), + din => tlb_htw_req1_tag_d, + dout => tlb_htw_req1_tag_q ); +tlb_htw_req1_way_latch: tri_rlmreg_p + generic map (width => tlb_htw_req1_way_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(24+1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_htw_req1_way_offset to tlb_htw_req1_way_offset+tlb_htw_req1_way_q'length-1), + scout => sov_0(tlb_htw_req1_way_offset to tlb_htw_req1_way_offset+tlb_htw_req1_way_q'length-1), + din => tlb_htw_req1_way_d, + dout => tlb_htw_req1_way_q ); +tlb_htw_req2_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_htw_req2_valid_offset), + scout => sov_0(tlb_htw_req2_valid_offset), + din => tlb_htw_req2_valid_d, + dout => tlb_htw_req2_valid_q); +tlb_htw_req2_pending_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_htw_req2_pending_offset), + scout => sov_0(tlb_htw_req2_pending_offset), + din => tlb_htw_req2_pending_d, + dout => tlb_htw_req2_pending_q); +tlb_htw_req2_tag_latch: tri_rlmreg_p + generic map (width => tlb_htw_req2_tag_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_htw_req2_tag_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_htw_req2_tag_offset to tlb_htw_req2_tag_offset+tlb_htw_req2_tag_q'length-1), + scout => sov_0(tlb_htw_req2_tag_offset to tlb_htw_req2_tag_offset+tlb_htw_req2_tag_q'length-1), + din => tlb_htw_req2_tag_d, + dout => tlb_htw_req2_tag_q ); +tlb_htw_req2_way_latch: tri_rlmreg_p + generic map (width => tlb_htw_req2_way_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(24+2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_htw_req2_way_offset to tlb_htw_req2_way_offset+tlb_htw_req2_way_q'length-1), + scout => sov_0(tlb_htw_req2_way_offset to tlb_htw_req2_way_offset+tlb_htw_req2_way_q'length-1), + din => tlb_htw_req2_way_d, + dout => tlb_htw_req2_way_q ); +tlb_htw_req3_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_htw_req3_valid_offset), + scout => sov_0(tlb_htw_req3_valid_offset), + din => tlb_htw_req3_valid_d, + dout => tlb_htw_req3_valid_q); +tlb_htw_req3_pending_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_htw_req3_pending_offset), + scout => sov_0(tlb_htw_req3_pending_offset), + din => tlb_htw_req3_pending_d, + dout => tlb_htw_req3_pending_q); +tlb_htw_req3_tag_latch: tri_rlmreg_p + generic map (width => tlb_htw_req3_tag_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_htw_req3_tag_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_htw_req3_tag_offset to tlb_htw_req3_tag_offset+tlb_htw_req3_tag_q'length-1), + scout => sov_0(tlb_htw_req3_tag_offset to tlb_htw_req3_tag_offset+tlb_htw_req3_tag_q'length-1), + din => tlb_htw_req3_tag_d, + dout => tlb_htw_req3_tag_q ); +tlb_htw_req3_way_latch: tri_rlmreg_p + generic map (width => tlb_htw_req3_way_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(24+3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_htw_req3_way_offset to tlb_htw_req3_way_offset+tlb_htw_req3_way_q'length-1), + scout => sov_0(tlb_htw_req3_way_offset to tlb_htw_req3_way_offset+tlb_htw_req3_way_q'length-1), + din => tlb_htw_req3_way_d, + dout => tlb_htw_req3_way_q ); +spare_a_latch: tri_rlmreg_p + generic map (width => spare_a_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spare_a_offset to spare_a_offset+spare_a_q'length-1), + scout => sov_0(spare_a_offset to spare_a_offset+spare_a_q'length-1), + din => spare_a_q, + dout => spare_a_q ); +htw_seq_latch: tri_rlmreg_p + generic map (width => htw_seq_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(htw_seq_offset to htw_seq_offset+htw_seq_q'length-1), + scout => sov_1(htw_seq_offset to htw_seq_offset+htw_seq_q'length-1), + din => htw_seq_d(0 to htw_seq_width-1), + dout => htw_seq_q(0 to htw_seq_width-1) ); +htw_inptr_latch: tri_rlmreg_p + generic map (width => htw_inptr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(htw_inptr_offset to htw_inptr_offset+htw_inptr_q'length-1), + scout => sov_1(htw_inptr_offset to htw_inptr_offset+htw_inptr_q'length-1), + din => htw_inptr_d, + dout => htw_inptr_q ); +htw_lsuptr_latch: tri_rlmreg_p + generic map (width => htw_lsuptr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(htw_lsuptr_offset to htw_lsuptr_offset+htw_lsuptr_q'length-1), + scout => sov_1(htw_lsuptr_offset to htw_lsuptr_offset+htw_lsuptr_q'length-1), + din => htw_lsuptr_d, + dout => htw_lsuptr_q ); +htw_lsu_ttype_latch: tri_rlmreg_p + generic map (width => htw_lsu_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => htw_lsu_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(htw_lsu_ttype_offset to htw_lsu_ttype_offset+htw_lsu_ttype_q'length-1), + scout => sov_1(htw_lsu_ttype_offset to htw_lsu_ttype_offset+htw_lsu_ttype_q'length-1), + din => htw_lsu_ttype_d, + dout => htw_lsu_ttype_q ); +htw_lsu_thdid_latch: tri_rlmreg_p + generic map (width => htw_lsu_thdid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => htw_lsu_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(htw_lsu_thdid_offset to htw_lsu_thdid_offset+htw_lsu_thdid_q'length-1), + scout => sov_1(htw_lsu_thdid_offset to htw_lsu_thdid_offset+htw_lsu_thdid_q'length-1), + din => htw_lsu_thdid_d, + dout => htw_lsu_thdid_q ); +htw_lsu_wimge_latch: tri_rlmreg_p + generic map (width => htw_lsu_wimge_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => htw_lsu_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(htw_lsu_wimge_offset to htw_lsu_wimge_offset+htw_lsu_wimge_q'length-1), + scout => sov_1(htw_lsu_wimge_offset to htw_lsu_wimge_offset+htw_lsu_wimge_q'length-1), + din => htw_lsu_wimge_d, + dout => htw_lsu_wimge_q ); +htw_lsu_u_latch: tri_rlmreg_p + generic map (width => htw_lsu_u_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => htw_lsu_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(htw_lsu_u_offset to htw_lsu_u_offset+htw_lsu_u_q'length-1), + scout => sov_1(htw_lsu_u_offset to htw_lsu_u_offset+htw_lsu_u_q'length-1), + din => htw_lsu_u_d, + dout => htw_lsu_u_q ); +htw_lsu_addr_latch: tri_rlmreg_p + generic map (width => htw_lsu_addr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => htw_lsu_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(htw_lsu_addr_offset to htw_lsu_addr_offset+htw_lsu_addr_q'length-1), + scout => sov_1(htw_lsu_addr_offset to htw_lsu_addr_offset+htw_lsu_addr_q'length-1), + din => htw_lsu_addr_d, + dout => htw_lsu_addr_q ); +pte0_seq_latch: tri_rlmreg_p + generic map (width => pte0_seq_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(pte0_seq_offset to pte0_seq_offset+pte0_seq_q'length-1), + scout => sov_1(pte0_seq_offset to pte0_seq_offset+pte0_seq_q'length-1), + din => pte0_seq_d, + dout => pte0_seq_q ); +pte0_score_ptr_latch: tri_rlmreg_p + generic map (width => pte0_score_ptr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => pte0_score_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(pte0_score_ptr_offset to pte0_score_ptr_offset+pte0_score_ptr_q'length-1), + scout => sov_1(pte0_score_ptr_offset to pte0_score_ptr_offset+pte0_score_ptr_q'length-1), + din => pte0_score_ptr_d, + dout => pte0_score_ptr_q ); +pte0_score_cl_offset_latch: tri_rlmreg_p + generic map (width => pte0_score_cl_offset_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => pte0_score_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(pte0_score_cl_offset_offset to pte0_score_cl_offset_offset+pte0_score_cl_offset_q'length-1), + scout => sov_1(pte0_score_cl_offset_offset to pte0_score_cl_offset_offset+pte0_score_cl_offset_q'length-1), + din => pte0_score_cl_offset_d, + dout => pte0_score_cl_offset_q ); +pte0_score_error_latch: tri_rlmreg_p + generic map (width => pte0_score_error_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => pte0_score_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(pte0_score_error_offset to pte0_score_error_offset+pte0_score_error_q'length-1), + scout => sov_1(pte0_score_error_offset to pte0_score_error_offset+pte0_score_error_q'length-1), + din => pte0_score_error_d, + dout => pte0_score_error_q ); +pte0_score_qwbeat_latch: tri_rlmreg_p + generic map (width => pte0_score_qwbeat_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => pte0_score_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(pte0_score_qwbeat_offset to pte0_score_qwbeat_offset+pte0_score_qwbeat_q'length-1), + scout => sov_1(pte0_score_qwbeat_offset to pte0_score_qwbeat_offset+pte0_score_qwbeat_q'length-1), + din => pte0_score_qwbeat_d, + dout => pte0_score_qwbeat_q ); +pte0_score_ibit_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => pte0_score_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(pte0_score_ibit_offset), + scout => sov_1(pte0_score_ibit_offset), + din => pte0_score_ibit_d, + dout => pte0_score_ibit_q); +pte0_score_pending_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => pte0_score_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(pte0_score_pending_offset), + scout => sov_1(pte0_score_pending_offset), + din => pte0_score_pending_d, + dout => pte0_score_pending_q); +pte0_score_dataval_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => pte0_score_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(pte0_score_dataval_offset), + scout => sov_1(pte0_score_dataval_offset), + din => pte0_score_dataval_d, + dout => pte0_score_dataval_q); +pte1_seq_latch: tri_rlmreg_p + generic map (width => pte1_seq_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(pte1_seq_offset to pte1_seq_offset+pte1_seq_q'length-1), + scout => sov_1(pte1_seq_offset to pte1_seq_offset+pte1_seq_q'length-1), + din => pte1_seq_d, + dout => pte1_seq_q ); +pte1_score_ptr_latch: tri_rlmreg_p + generic map (width => pte1_score_ptr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => pte1_score_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(pte1_score_ptr_offset to pte1_score_ptr_offset+pte1_score_ptr_q'length-1), + scout => sov_1(pte1_score_ptr_offset to pte1_score_ptr_offset+pte1_score_ptr_q'length-1), + din => pte1_score_ptr_d, + dout => pte1_score_ptr_q ); +pte1_score_cl_offset_latch: tri_rlmreg_p + generic map (width => pte1_score_cl_offset_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => pte1_score_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(pte1_score_cl_offset_offset to pte1_score_cl_offset_offset+pte1_score_cl_offset_q'length-1), + scout => sov_1(pte1_score_cl_offset_offset to pte1_score_cl_offset_offset+pte1_score_cl_offset_q'length-1), + din => pte1_score_cl_offset_d, + dout => pte1_score_cl_offset_q ); +pte1_score_error_latch: tri_rlmreg_p + generic map (width => pte1_score_error_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => pte1_score_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(pte1_score_error_offset to pte1_score_error_offset+pte1_score_error_q'length-1), + scout => sov_1(pte1_score_error_offset to pte1_score_error_offset+pte1_score_error_q'length-1), + din => pte1_score_error_d, + dout => pte1_score_error_q ); +pte1_score_qwbeat_latch: tri_rlmreg_p + generic map (width => pte1_score_qwbeat_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => pte1_score_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(pte1_score_qwbeat_offset to pte1_score_qwbeat_offset+pte1_score_qwbeat_q'length-1), + scout => sov_1(pte1_score_qwbeat_offset to pte1_score_qwbeat_offset+pte1_score_qwbeat_q'length-1), + din => pte1_score_qwbeat_d, + dout => pte1_score_qwbeat_q ); +pte1_score_ibit_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => pte1_score_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(pte1_score_ibit_offset), + scout => sov_1(pte1_score_ibit_offset), + din => pte1_score_ibit_d, + dout => pte1_score_ibit_q); +pte1_score_pending_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => pte1_score_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(pte1_score_pending_offset), + scout => sov_1(pte1_score_pending_offset), + din => pte1_score_pending_d, + dout => pte1_score_pending_q); +pte1_score_dataval_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => pte1_score_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(pte1_score_dataval_offset), + scout => sov_1(pte1_score_dataval_offset), + din => pte1_score_dataval_d, + dout => pte1_score_dataval_q); +pte_load_ptr_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(pte_load_ptr_offset), + scout => sov_1(pte_load_ptr_offset), + din => pte_load_ptr_d, + dout => pte_load_ptr_q); +ptereload_ptr_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ptereload_ptr_offset), + scout => sov_1(ptereload_ptr_offset), + din => ptereload_ptr_d, + dout => ptereload_ptr_q); +reld_core_tag_tm1_latch: tri_rlmreg_p + generic map (width => reld_core_tag_tm1_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => reld_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(reld_core_tag_tm1_offset to reld_core_tag_tm1_offset+reld_core_tag_tm1_q'length-1), + scout => sov_1(reld_core_tag_tm1_offset to reld_core_tag_tm1_offset+reld_core_tag_tm1_q'length-1), + din => reld_core_tag_tm1_d, + dout => reld_core_tag_tm1_q ); +reld_qw_tm1_latch: tri_rlmreg_p + generic map (width => reld_qw_tm1_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => reld_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(reld_qw_tm1_offset to reld_qw_tm1_offset+reld_qw_tm1_q'length-1), + scout => sov_1(reld_qw_tm1_offset to reld_qw_tm1_offset+reld_qw_tm1_q'length-1), + din => reld_qw_tm1_d, + dout => reld_qw_tm1_q ); +reld_crit_qw_tm1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => reld_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(reld_crit_qw_tm1_offset), + scout => sov_1(reld_crit_qw_tm1_offset), + din => reld_crit_qw_tm1_d, + dout => reld_crit_qw_tm1_q); +reld_ditc_tm1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => reld_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(reld_ditc_tm1_offset), + scout => sov_1(reld_ditc_tm1_offset), + din => reld_ditc_tm1_d, + dout => reld_ditc_tm1_q); +reld_data_vld_tm1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => reld_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(reld_data_vld_tm1_offset), + scout => sov_1(reld_data_vld_tm1_offset), + din => reld_data_vld_tm1_d, + dout => reld_data_vld_tm1_q); +reld_core_tag_t_latch: tri_rlmreg_p + generic map (width => reld_core_tag_t_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => reld_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(reld_core_tag_t_offset to reld_core_tag_t_offset+reld_core_tag_t_q'length-1), + scout => sov_1(reld_core_tag_t_offset to reld_core_tag_t_offset+reld_core_tag_t_q'length-1), + din => reld_core_tag_t_d, + dout => reld_core_tag_t_q ); +reld_qw_t_latch: tri_rlmreg_p + generic map (width => reld_qw_t_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => reld_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(reld_qw_t_offset to reld_qw_t_offset+reld_qw_t_q'length-1), + scout => sov_1(reld_qw_t_offset to reld_qw_t_offset+reld_qw_t_q'length-1), + din => reld_qw_t_d, + dout => reld_qw_t_q ); +reld_crit_qw_t_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => reld_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(reld_crit_qw_t_offset), + scout => sov_1(reld_crit_qw_t_offset), + din => reld_crit_qw_t_d, + dout => reld_crit_qw_t_q); +reld_ditc_t_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => reld_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(reld_ditc_t_offset), + scout => sov_1(reld_ditc_t_offset), + din => reld_ditc_t_d, + dout => reld_ditc_t_q); +reld_data_vld_t_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => reld_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(reld_data_vld_t_offset), + scout => sov_1(reld_data_vld_t_offset), + din => reld_data_vld_t_d, + dout => reld_data_vld_t_q); +reld_core_tag_tp1_latch: tri_rlmreg_p + generic map (width => reld_core_tag_tp1_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => reld_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(reld_core_tag_tp1_offset to reld_core_tag_tp1_offset+reld_core_tag_tp1_q'length-1), + scout => sov_1(reld_core_tag_tp1_offset to reld_core_tag_tp1_offset+reld_core_tag_tp1_q'length-1), + din => reld_core_tag_tp1_d, + dout => reld_core_tag_tp1_q ); +reld_qw_tp1_latch: tri_rlmreg_p + generic map (width => reld_qw_tp1_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => reld_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(reld_qw_tp1_offset to reld_qw_tp1_offset+reld_qw_tp1_q'length-1), + scout => sov_1(reld_qw_tp1_offset to reld_qw_tp1_offset+reld_qw_tp1_q'length-1), + din => reld_qw_tp1_d, + dout => reld_qw_tp1_q ); +reld_crit_qw_tp1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => reld_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(reld_crit_qw_tp1_offset), + scout => sov_1(reld_crit_qw_tp1_offset), + din => reld_crit_qw_tp1_d, + dout => reld_crit_qw_tp1_q); +reld_ditc_tp1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => reld_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(reld_ditc_tp1_offset), + scout => sov_1(reld_ditc_tp1_offset), + din => reld_ditc_tp1_d, + dout => reld_ditc_tp1_q); +reld_data_vld_tp1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => reld_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(reld_data_vld_tp1_offset), + scout => sov_1(reld_data_vld_tp1_offset), + din => reld_data_vld_tp1_d, + dout => reld_data_vld_tp1_q); +reld_data_tp1_latch: tri_rlmreg_p + generic map (width => reld_data_tp1_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => reld_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(reld_data_tp1_offset to reld_data_tp1_offset+reld_data_tp1_q'length-1), + scout => sov_1(reld_data_tp1_offset to reld_data_tp1_offset+reld_data_tp1_q'length-1), + din => reld_data_tp1_d, + dout => reld_data_tp1_q ); +reld_core_tag_tp2_latch: tri_rlmreg_p + generic map (width => reld_core_tag_tp2_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => reld_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(reld_core_tag_tp2_offset to reld_core_tag_tp2_offset+reld_core_tag_tp2_q'length-1), + scout => sov_1(reld_core_tag_tp2_offset to reld_core_tag_tp2_offset+reld_core_tag_tp2_q'length-1), + din => reld_core_tag_tp2_d, + dout => reld_core_tag_tp2_q ); +reld_qw_tp2_latch: tri_rlmreg_p + generic map (width => reld_qw_tp2_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => reld_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(reld_qw_tp2_offset to reld_qw_tp2_offset+reld_qw_tp2_q'length-1), + scout => sov_1(reld_qw_tp2_offset to reld_qw_tp2_offset+reld_qw_tp2_q'length-1), + din => reld_qw_tp2_d, + dout => reld_qw_tp2_q ); +reld_crit_qw_tp2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => reld_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(reld_crit_qw_tp2_offset), + scout => sov_1(reld_crit_qw_tp2_offset), + din => reld_crit_qw_tp2_d, + dout => reld_crit_qw_tp2_q); +reld_ditc_tp2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => reld_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(reld_ditc_tp2_offset), + scout => sov_1(reld_ditc_tp2_offset), + din => reld_ditc_tp2_d, + dout => reld_ditc_tp2_q); +reld_data_vld_tp2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => reld_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(reld_data_vld_tp2_offset), + scout => sov_1(reld_data_vld_tp2_offset), + din => reld_data_vld_tp2_d, + dout => reld_data_vld_tp2_q); +reld_data_tp2_latch: tri_rlmreg_p + generic map (width => reld_data_tp2_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => reld_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(reld_data_tp2_offset to reld_data_tp2_offset+reld_data_tp2_q'length-1), + scout => sov_1(reld_data_tp2_offset to reld_data_tp2_offset+reld_data_tp2_q'length-1), + din => reld_data_tp2_d, + dout => reld_data_tp2_q ); +reld_ecc_err_tp2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => reld_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(reld_ecc_err_tp2_offset), + scout => sov_1(reld_ecc_err_tp2_offset), + din => reld_ecc_err_tp2_d, + dout => reld_ecc_err_tp2_q); +reld_ecc_err_ue_tp2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => reld_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(reld_ecc_err_ue_tp2_offset), + scout => sov_1(reld_ecc_err_ue_tp2_offset), + din => reld_ecc_err_ue_tp2_d, + dout => reld_ecc_err_ue_tp2_q); +pte0_reld_data_tp3_latch: tri_rlmreg_p + generic map (width => pte0_reld_data_tp3_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => pte0_reld_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(pte0_reld_data_tp3_offset to pte0_reld_data_tp3_offset+pte0_reld_data_tp3_q'length-1), + scout => sov_1(pte0_reld_data_tp3_offset to pte0_reld_data_tp3_offset+pte0_reld_data_tp3_q'length-1), + din => pte0_reld_data_tp3_d, + dout => pte0_reld_data_tp3_q ); +pte1_reld_data_tp3_latch: tri_rlmreg_p + generic map (width => pte1_reld_data_tp3_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => pte1_reld_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(pte1_reld_data_tp3_offset to pte1_reld_data_tp3_offset+pte1_reld_data_tp3_q'length-1), + scout => sov_1(pte1_reld_data_tp3_offset to pte1_reld_data_tp3_offset+pte1_reld_data_tp3_q'length-1), + din => pte1_reld_data_tp3_d, + dout => pte1_reld_data_tp3_q ); +htw_tag3_latch: tri_rlmreg_p + generic map (width => htw_tag3_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(28), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(htw_tag3_offset to htw_tag3_offset+htw_tag3_q'length-1), + scout => sov_1(htw_tag3_offset to htw_tag3_offset+htw_tag3_q'length-1), + din => htw_tag3_d, + dout => htw_tag3_q ); +htw_tag4_clr_resv_latch: tri_rlmreg_p + generic map (width => htw_tag4_clr_resv_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(28), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(htw_tag4_clr_resv_offset to htw_tag4_clr_resv_offset+htw_tag4_clr_resv_q'length-1), + scout => sov_1(htw_tag4_clr_resv_offset to htw_tag4_clr_resv_offset+htw_tag4_clr_resv_q'length-1), + din => htw_tag4_clr_resv_d, + dout => htw_tag4_clr_resv_q ); +htw_tag5_clr_resv_latch: tri_rlmreg_p + generic map (width => htw_tag5_clr_resv_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(28), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(htw_tag5_clr_resv_offset to htw_tag5_clr_resv_offset+htw_tag5_clr_resv_q'length-1), + scout => sov_1(htw_tag5_clr_resv_offset to htw_tag5_clr_resv_offset+htw_tag5_clr_resv_q'length-1), + din => htw_tag5_clr_resv_d, + dout => htw_tag5_clr_resv_q ); +spare_b_latch: tri_rlmreg_p + generic map (width => spare_b_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spare_b_offset to spare_b_offset+spare_b_q'length-1), + scout => sov_1(spare_b_offset to spare_b_offset+spare_b_q'length-1), + din => spare_b_q, + dout => spare_b_q ); +perv_2to1_reg: tri_plat + generic map (width => 3, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ccflush_dc, + din(0) => pc_func_sl_thold_2, + din(1) => pc_func_slp_sl_thold_2, + din(2) => pc_sg_2, + q(0) => pc_func_sl_thold_1, + q(1) => pc_func_slp_sl_thold_1, + q(2) => pc_sg_1); +perv_1to0_reg: tri_plat + generic map (width => 3, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ccflush_dc, + din(0) => pc_func_sl_thold_1, + din(1) => pc_func_slp_sl_thold_1, + din(2) => pc_sg_1, + q(0) => pc_func_sl_thold_0, + q(1) => pc_func_slp_sl_thold_0, + q(2) => pc_sg_0); +perv_lcbor_func_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b, + thold => pc_func_sl_thold_0, + sg => pc_sg_0, + act_dis => lcb_act_dis_dc, + forcee => pc_func_sl_force, + thold_b => pc_func_sl_thold_0_b); +perv_lcbor_func_slp_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b, + thold => pc_func_slp_sl_thold_0, + sg => pc_sg_0, + act_dis => lcb_act_dis_dc, + forcee => pc_func_slp_sl_force, + thold_b => pc_func_slp_sl_thold_0_b); +siv_0(0 TO scan_right_0) <= sov_0(1 to scan_right_0) & ac_func_scan_in(0); +ac_func_scan_out(0) <= sov_0(0); +siv_1(0 TO scan_right_1) <= sov_1(1 to scan_right_1) & ac_func_scan_in(1); +ac_func_scan_out(1) <= sov_1(0); +END MMQ_HTW; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/mmq_inval.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/mmq_inval.vhdl new file mode 100644 index 0000000..d0ad086 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/mmq_inval.vhdl @@ -0,0 +1,2845 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; +use ieee.std_logic_1164.all; +library ibm; +use ibm.std_ulogic_unsigned.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_support.all; +library support; +use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity mmq_inval is + generic(thdid_width : integer := 4; + ttype_width : integer := 6; + state_width : integer := 2; + pid_width : integer := 14; + lpid_width : integer := 8; + t_width : integer := 3; + rs_is_width : integer := 9; + rs_data_width : integer := 64; + epn_width : integer := 52; + real_addr_width : integer := 42; + rpn_width : integer := 30; + inv_seq_width : integer := 6; + tlb_ways : natural := 4; + tlb_addr_width : natural := 7; + tlb_way_width : natural := 168; + expand_type : integer := 2 ); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + + tc_ccflush_dc : in std_ulogic; + tc_scan_dis_dc_b : in std_ulogic; + tc_scan_diag_dc : in std_ulogic; + tc_lbist_en_dc : in std_ulogic; + + lcb_d_mode_dc : in std_ulogic; + lcb_clkoff_dc_b : in std_ulogic; + lcb_act_dis_dc : in std_ulogic; + lcb_mpw1_dc_b : in std_ulogic_vector(0 to 4); + lcb_mpw2_dc_b : in std_ulogic; + lcb_delay_lclkr_dc : in std_ulogic_vector(0 to 4); + + ac_func_scan_in : in std_ulogic; + ac_func_scan_out : out std_ulogic; + + pc_sg_2 : in std_ulogic; + pc_func_sl_thold_2 : in std_ulogic; + pc_func_slp_sl_thold_2 : in std_ulogic; + pc_func_slp_nsl_thold_2 : in std_ulogic; + pc_fce_2 : in std_ulogic; + mmucr2_act_override : in std_ulogic; + xu_mm_ccr2_notlb : in std_ulogic; + xu_mm_ccr2_notlb_b : out std_ulogic_vector(1 to 12); + + mm_iu_ierat_snoop_coming : out std_ulogic; + mm_iu_ierat_snoop_val : out std_ulogic; + mm_iu_ierat_snoop_attr : out std_ulogic_vector(0 to 25); + mm_iu_ierat_snoop_vpn : out std_ulogic_vector(52-epn_width to 51); + iu_mm_ierat_snoop_ack : in std_ulogic; + + mm_xu_derat_snoop_coming : out std_ulogic; + mm_xu_derat_snoop_val : out std_ulogic; + mm_xu_derat_snoop_attr : out std_ulogic_vector(0 to 25); + mm_xu_derat_snoop_vpn : out std_ulogic_vector(52-epn_width to 51); + xu_mm_derat_snoop_ack : in std_ulogic; + tlb_snoop_coming : out std_ulogic; + tlb_snoop_val : out std_ulogic; + tlb_snoop_attr : out std_ulogic_vector(0 to 34); + tlb_snoop_vpn : out std_ulogic_vector(52-epn_width to 51); + tlb_snoop_ack : in std_ulogic; + an_ac_back_inv : in std_ulogic; + an_ac_back_inv_target : in std_ulogic; + an_ac_back_inv_local : in std_ulogic; + an_ac_back_inv_lbit : in std_ulogic; + an_ac_back_inv_gs : in std_ulogic; + an_ac_back_inv_ind : in std_ulogic; + an_ac_back_inv_addr : in std_ulogic_vector(64-real_addr_width to 63); + an_ac_back_inv_lpar_id : in std_ulogic_vector(0 to lpid_width-1); + ac_an_power_managed : in std_ulogic; + ac_an_back_inv_reject : out std_ulogic; + mmucr0_0 : in std_ulogic_vector(2 to 19); + mmucr0_1 : in std_ulogic_vector(2 to 19); + mmucr0_2 : in std_ulogic_vector(2 to 19); + mmucr0_3 : in std_ulogic_vector(2 to 19); + mmucr1 : in std_ulogic_vector(12 to 19); + mmucr1_csinv : in std_ulogic_vector(0 to 1); + lpidr : in std_ulogic_vector(0 to lpid_width-1); + + mas5_0_sgs : in std_ulogic; + mas5_0_slpid : in std_ulogic_vector(0 to 7); + mas6_0_spid : in std_ulogic_vector(0 to 13); + mas6_0_isize : in std_ulogic_vector(0 to 3); + mas6_0_sind : in std_ulogic; + mas6_0_sas : in std_ulogic; + mas5_1_sgs : in std_ulogic; + mas5_1_slpid : in std_ulogic_vector(0 to 7); + mas6_1_spid : in std_ulogic_vector(0 to 13); + mas6_1_isize : in std_ulogic_vector(0 to 3); + mas6_1_sind : in std_ulogic; + mas6_1_sas : in std_ulogic; + mas5_2_sgs : in std_ulogic; + mas5_2_slpid : in std_ulogic_vector(0 to 7); + mas6_2_spid : in std_ulogic_vector(0 to 13); + mas6_2_isize : in std_ulogic_vector(0 to 3); + mas6_2_sind : in std_ulogic; + mas6_2_sas : in std_ulogic; + mas5_3_sgs : in std_ulogic; + mas5_3_slpid : in std_ulogic_vector(0 to 7); + mas6_3_spid : in std_ulogic_vector(0 to 13); + mas6_3_isize : in std_ulogic_vector(0 to 3); + mas6_3_sind : in std_ulogic; + mas6_3_sas : in std_ulogic; + mmucsr0_tlb0fi : in std_ulogic; + mmq_inval_tlb0fi_done : out std_ulogic; + + + xu_mm_rf1_val : in std_ulogic_vector(0 to thdid_width-1); + xu_mm_rf1_is_tlbivax : in std_ulogic; + xu_mm_rf1_is_tlbilx : in std_ulogic; + xu_mm_rf1_is_erativax : in std_ulogic; + xu_mm_rf1_is_eratilx : in std_ulogic; + xu_mm_ex1_rs_is : in std_ulogic_vector(0 to rs_is_width-1); + xu_mm_ex1_is_isync : in std_ulogic; + xu_mm_ex1_is_csync : in std_ulogic; + xu_mm_ex2_eff_addr : in std_ulogic_vector(64-rs_data_width to 63); + xu_mm_rf1_t : in std_ulogic_vector(0 to t_width-1); + xu_mm_msr_gs : in std_ulogic_vector(0 to thdid_width-1); + xu_mm_msr_pr : in std_ulogic_vector(0 to thdid_width-1); + xu_mm_spr_epcr_dgtmi : in std_ulogic_vector(0 to thdid_width-1); + xu_mm_epcr_dgtmi : out std_ulogic_vector(0 to thdid_width-1); + xu_rf1_flush : in std_ulogic_vector(0 to thdid_width-1); + xu_ex1_flush : in std_ulogic_vector(0 to thdid_width-1); + xu_ex2_flush : in std_ulogic_vector(0 to thdid_width-1); + xu_ex3_flush : in std_ulogic_vector(0 to thdid_width-1); + xu_ex4_flush : in std_ulogic_vector(0 to thdid_width-1); + xu_ex5_flush : in std_ulogic_vector(0 to thdid_width-1); + xu_mm_lmq_stq_empty : in std_ulogic; + xu_mm_hold_ack : in std_ulogic_vector(0 to thdid_width-1); + iu_mm_lmq_empty : in std_ulogic; + tlb_ctl_barrier_done : in std_ulogic_vector(0 to thdid_width-1); + tlb_ctl_ex2_flush_req : in std_ulogic_vector(0 to thdid_width-1); + tlb_ctl_ex2_illeg_instr : in std_ulogic_vector(0 to thdid_width-1); + tlb_ctl_quiesce : in std_ulogic_vector(0 to thdid_width-1); + tlb_req_quiesce : in std_ulogic_vector(0 to thdid_width-1); + + mm_iu_barrier_done : out std_ulogic_vector(0 to thdid_width-1); + mm_xu_ex3_flush_req : out std_ulogic_vector(0 to thdid_width-1); + mm_xu_hold_req : out std_ulogic_vector(0 to thdid_width-1); + mm_xu_hold_done : out std_ulogic_vector(0 to thdid_width-1); + mm_xu_illeg_instr : out std_ulogic_vector(0 to thdid_width-1); + mm_xu_local_snoop_reject : out std_ulogic_vector(0 to thdid_width-1); + mm_xu_quiesce : out std_ulogic_vector(0 to thdid_width-1); + + inval_perf_tlbilx : out std_ulogic; + inval_perf_tlbivax : out std_ulogic; + inval_perf_tlbivax_snoop : out std_ulogic; + inval_perf_tlb_flush : out std_ulogic; + + htw_lsu_req_valid : in std_ulogic; + htw_lsu_thdid : in std_ulogic_vector(0 to thdid_width-1); + htw_lsu_ttype : in std_ulogic_vector(0 to 1); + htw_lsu_wimge : in std_ulogic_vector(0 to 4); + htw_lsu_u : in std_ulogic_vector(0 to 3); + htw_lsu_addr : in std_ulogic_vector(64-real_addr_width to 63); + htw_lsu_req_taken : out std_ulogic; + htw_quiesce : in std_ulogic_vector(0 to thdid_width-1); + tlbwe_back_inv_valid : in std_ulogic; + tlbwe_back_inv_thdid : in std_ulogic_vector(0 to thdid_width-1); + tlbwe_back_inv_addr : in std_ulogic_vector(52-epn_width to 51); + tlbwe_back_inv_attr : in std_ulogic_vector(0 to 34); + tlb_tag5_write : in std_ulogic; + tlbwe_back_inv_pending : out std_ulogic; + + mm_xu_lsu_req : out std_ulogic_vector(0 to thdid_width-1); + mm_xu_lsu_ttype : out std_ulogic_vector(0 to 1); + mm_xu_lsu_wimge : out std_ulogic_vector(0 to 4); + mm_xu_lsu_u : out std_ulogic_vector(0 to 3); + mm_xu_lsu_addr : out std_ulogic_vector(64-real_addr_width to 63); + mm_xu_lsu_lpid : out std_ulogic_vector(0 to 7); + mm_xu_lsu_gs : out std_ulogic; + mm_xu_lsu_ind : out std_ulogic; + mm_xu_lsu_lbit : out std_ulogic; + xu_mm_lsu_token : in std_ulogic; + + inval_dbg_seq_q : out std_ulogic_vector(0 to 4); + inval_dbg_seq_idle : out std_ulogic; + inval_dbg_seq_snoop_inprogress : out std_ulogic; + inval_dbg_seq_snoop_done : out std_ulogic; + inval_dbg_seq_local_done : out std_ulogic; + inval_dbg_seq_tlb0fi_done : out std_ulogic; + inval_dbg_seq_tlbwe_snoop_done : out std_ulogic; + inval_dbg_ex6_valid : out std_ulogic; + inval_dbg_ex6_thdid : out std_ulogic_vector(0 to 1); + inval_dbg_ex6_ttype : out std_ulogic_vector(0 to 2); + inval_dbg_snoop_forme : out std_ulogic; + inval_dbg_snoop_local_reject : out std_ulogic; + inval_dbg_an_ac_back_inv_q : out std_ulogic_vector(2 to 8); + inval_dbg_an_ac_back_inv_lpar_id_q : out std_ulogic_vector(0 to 7); + inval_dbg_an_ac_back_inv_addr_q : out std_ulogic_vector(22 to 63); + inval_dbg_snoop_valid_q : out std_ulogic_vector(0 to 2); + inval_dbg_snoop_ack_q : out std_ulogic_vector(0 to 2); + inval_dbg_snoop_attr_q : out std_ulogic_vector(0 to 34); + inval_dbg_snoop_attr_tlb_spec_q : out std_ulogic_vector(18 to 19); + inval_dbg_snoop_vpn_q : out std_ulogic_vector(17 to 51); + inval_dbg_lsu_tokens_q : out std_ulogic_vector(0 to 1) +); +end mmq_inval; +architecture mmq_inval of mmq_inval is +constant MMU_Mode_Value : std_ulogic := '0'; +constant ERAT_Mode_Value : std_ulogic := '1'; +constant TlbSel_Tlb : std_ulogic_vector(0 to 1) := "00"; +constant TlbSel_IErat : std_ulogic_vector(0 to 1) := "10"; +constant TlbSel_DErat : std_ulogic_vector(0 to 1) := "11"; +constant TLB_PgSize_1GB : std_ulogic_vector(0 to 3) := "1010"; +constant TLB_PgSize_16MB : std_ulogic_vector(0 to 3) := "0111"; +constant TLB_PgSize_1MB : std_ulogic_vector(0 to 3) := "0101"; +constant TLB_PgSize_64KB : std_ulogic_vector(0 to 3) := "0011"; +constant TLB_PgSize_4KB : std_ulogic_vector(0 to 3) := "0001"; +constant TLB_PgSize_256MB : std_ulogic_vector(0 to 3) := "1001"; +constant InvSeq_Idle : std_ulogic_vector(0 to 5) := "000000"; +constant InvSeq_Stg1 : std_ulogic_vector(0 to 5) := "000001"; +constant InvSeq_Stg2 : std_ulogic_vector(0 to 5) := "000011"; +constant InvSeq_Stg3 : std_ulogic_vector(0 to 5) := "000010"; +constant InvSeq_Stg4 : std_ulogic_vector(0 to 5) := "000110"; +constant InvSeq_Stg5 : std_ulogic_vector(0 to 5) := "000100"; +constant InvSeq_Stg6 : std_ulogic_vector(0 to 5) := "000101"; +constant InvSeq_Stg7 : std_ulogic_vector(0 to 5) := "000111"; +constant InvSeq_Stg8 : std_ulogic_vector(0 to 5) := "001000"; +constant InvSeq_Stg9 : std_ulogic_vector(0 to 5) := "001001"; +constant InvSeq_Stg10 : std_ulogic_vector(0 to 5) := "001011"; +constant InvSeq_Stg11 : std_ulogic_vector(0 to 5) := "001010"; +constant InvSeq_Stg12 : std_ulogic_vector(0 to 5) := "001110"; +constant InvSeq_Stg13 : std_ulogic_vector(0 to 5) := "001100"; +constant InvSeq_Stg14 : std_ulogic_vector(0 to 5) := "001101"; +constant InvSeq_Stg15 : std_ulogic_vector(0 to 5) := "001111"; +constant InvSeq_Stg16 : std_ulogic_vector(0 to 5) := "010000"; +constant InvSeq_Stg17 : std_ulogic_vector(0 to 5) := "010001"; +constant InvSeq_Stg18 : std_ulogic_vector(0 to 5) := "010011"; +constant InvSeq_Stg19 : std_ulogic_vector(0 to 5) := "010010"; +constant InvSeq_Stg20 : std_ulogic_vector(0 to 5) := "010110"; +constant InvSeq_Stg21 : std_ulogic_vector(0 to 5) := "010100"; +constant InvSeq_Stg22 : std_ulogic_vector(0 to 5) := "010101"; +constant InvSeq_Stg23 : std_ulogic_vector(0 to 5) := "010111"; +constant InvSeq_Stg24 : std_ulogic_vector(0 to 5) := "011000"; +constant InvSeq_Stg25 : std_ulogic_vector(0 to 5) := "011001"; +constant InvSeq_Stg26 : std_ulogic_vector(0 to 5) := "011011"; +constant InvSeq_Stg27 : std_ulogic_vector(0 to 5) := "011010"; +constant InvSeq_Stg28 : std_ulogic_vector(0 to 5) := "011110"; +constant InvSeq_Stg29 : std_ulogic_vector(0 to 5) := "011100"; +constant InvSeq_Stg30 : std_ulogic_vector(0 to 5) := "011101"; +constant InvSeq_Stg31 : std_ulogic_vector(0 to 5) := "011111"; +constant InvSeq_Stg32 : std_ulogic_vector(0 to 5) := "100000"; +constant pos_ictid : natural := 12; +constant pos_ittid : natural := 13; +constant pos_dctid : natural := 14; +constant pos_dttid : natural := 15; +constant pos_tlbi_msb : natural := 18; +constant pos_tlbi_rej : natural := 19; +constant ex1_valid_offset : natural := 0; +constant ex1_ttype_offset : natural := ex1_valid_offset + thdid_width; +constant ex1_state_offset : natural := ex1_ttype_offset + ttype_width-2; +constant ex1_t_offset : natural := ex1_state_offset + state_width; +constant ex2_valid_offset : natural := ex1_t_offset + t_width; +constant ex2_ttype_offset : natural := ex2_valid_offset + thdid_width; +constant ex2_rs_is_offset : natural := ex2_ttype_offset + ttype_width; +constant ex2_state_offset : natural := ex2_rs_is_offset + rs_is_width; +constant ex2_t_offset : natural := ex2_state_offset + state_width; +constant ex3_valid_offset : natural := ex2_t_offset + t_width; +constant ex3_ttype_offset : natural := ex3_valid_offset + thdid_width; +constant ex3_rs_is_offset : natural := ex3_ttype_offset + ttype_width; +constant ex3_state_offset : natural := ex3_rs_is_offset + rs_is_width; +constant ex3_t_offset : natural := ex3_state_offset + state_width; +constant ex3_flush_req_offset : natural := ex3_t_offset + t_width; +constant ex3_ea_offset : natural := ex3_flush_req_offset + thdid_width; +constant ex4_valid_offset : natural := ex3_ea_offset + epn_width+12; +constant ex4_ttype_offset : natural := ex4_valid_offset + thdid_width; +constant ex4_rs_is_offset : natural := ex4_ttype_offset + ttype_width; +constant ex4_state_offset : natural := ex4_rs_is_offset + rs_is_width; +constant ex4_t_offset : natural := ex4_state_offset + state_width; +constant ex5_valid_offset : natural := ex4_t_offset + t_width; +constant ex5_ttype_offset : natural := ex5_valid_offset + thdid_width; +constant ex5_rs_is_offset : natural := ex5_ttype_offset + ttype_width; +constant ex5_state_offset : natural := ex5_rs_is_offset + rs_is_width; +constant ex5_t_offset : natural := ex5_state_offset + state_width; +constant ex6_valid_offset : natural := ex5_t_offset + t_width; +constant ex6_ttype_offset : natural := ex6_valid_offset + thdid_width; +constant ex6_isel_offset : natural := ex6_ttype_offset + ttype_width; +constant ex6_size_offset : natural := ex6_isel_offset + 3; +constant ex6_gs_offset : natural := ex6_size_offset + 4; +constant ex6_ts_offset : natural := ex6_gs_offset + 1; +constant ex6_ind_offset : natural := ex6_ts_offset + 1; +constant ex6_pid_offset : natural := ex6_ind_offset + 1; +constant ex6_lpid_offset : natural := ex6_pid_offset + pid_width; +constant inv_seq_offset : natural := ex6_lpid_offset + lpid_width; +constant hold_req_offset : natural := inv_seq_offset + inv_seq_width; +constant hold_ack_offset : natural := hold_req_offset + thdid_width; +constant hold_done_offset : natural := hold_ack_offset + thdid_width; +constant local_barrier_offset : natural := hold_done_offset + thdid_width; +constant global_barrier_offset : natural := local_barrier_offset + thdid_width; +constant barrier_done_offset : natural := global_barrier_offset + thdid_width; +constant illeg_instr_offset : natural := barrier_done_offset + thdid_width; +constant local_reject_offset : natural := illeg_instr_offset + thdid_width; +constant snoop_valid_offset : natural := local_reject_offset + thdid_width; +constant snoop_attr_offset : natural := snoop_valid_offset + 3; +constant snoop_vpn_offset : natural := snoop_attr_offset + 35; +constant snoop_attr_clone_offset : natural := snoop_vpn_offset + epn_width; +constant snoop_attr_tlb_spec_offset : natural := snoop_attr_clone_offset + 26; +constant snoop_vpn_clone_offset : natural := snoop_attr_tlb_spec_offset + 2; +constant snoop_ack_offset : natural := snoop_vpn_clone_offset + epn_width; +constant snoop_coming_offset : natural := snoop_ack_offset + 3; +constant mm_xu_quiesce_offset : natural := snoop_coming_offset + 5; +constant inv_seq_inprogress_offset : natural := mm_xu_quiesce_offset + thdid_width; +constant xu_mm_ccr2_notlb_offset : natural := inv_seq_inprogress_offset + 6; +constant spare_offset : natural := xu_mm_ccr2_notlb_offset + 13; +constant an_ac_back_inv_offset : natural := spare_offset + 16; +constant an_ac_back_inv_addr_offset : natural := an_ac_back_inv_offset + 9; +constant an_ac_back_inv_lpar_id_offset : natural := an_ac_back_inv_addr_offset + real_addr_width; +constant lsu_tokens_offset : natural := an_ac_back_inv_lpar_id_offset + lpid_width; +constant lsu_req_offset : natural := lsu_tokens_offset + 2; +constant lsu_ttype_offset : natural := lsu_req_offset + thdid_width; +constant lsu_ubits_offset : natural := lsu_ttype_offset + 2; +constant lsu_wimge_offset : natural := lsu_ubits_offset+ 4; +constant lsu_addr_offset : natural := lsu_wimge_offset + 5; +constant lsu_lpid_offset : natural := lsu_addr_offset + real_addr_width; +constant lsu_ind_offset : natural := lsu_lpid_offset + lpid_width; +constant lsu_gs_offset : natural := lsu_ind_offset + 1; +constant lsu_lbit_offset : natural := lsu_gs_offset + 1; +constant power_managed_offset : natural := lsu_lbit_offset + 1; +constant tlbwe_back_inv_offset : natural := power_managed_offset + 4; +constant tlbwe_back_inv_addr_offset : natural := tlbwe_back_inv_offset + thdid_width + 2; +constant tlbwe_back_inv_attr_offset : natural := tlbwe_back_inv_addr_offset + epn_width; +constant scan_right : natural := tlbwe_back_inv_attr_offset + 35 - 1; +signal ex1_valid_d, ex1_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal ex1_ttype_d, ex1_ttype_q : std_ulogic_vector(0 to ttype_width-3); +signal ex1_state_d, ex1_state_q : std_ulogic_vector(0 to state_width-1); +signal ex1_t_d, ex1_t_q : std_ulogic_vector(0 to t_width-1); +signal ex2_valid_d, ex2_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal ex2_ttype_d, ex2_ttype_q : std_ulogic_vector(0 to ttype_width-1); +signal ex2_rs_is_d, ex2_rs_is_q : std_ulogic_vector(0 to rs_is_width-1); +signal ex2_state_d, ex2_state_q : std_ulogic_vector(0 to state_width-1); +signal ex2_t_d, ex2_t_q : std_ulogic_vector(0 to t_width-1); +signal ex3_ea_d, ex3_ea_q : std_ulogic_vector(64-rs_data_width to 63); +signal ex3_valid_d, ex3_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal ex3_ttype_d, ex3_ttype_q : std_ulogic_vector(0 to ttype_width-1); +signal ex3_rs_is_d, ex3_rs_is_q : std_ulogic_vector(0 to rs_is_width-1); +signal ex3_state_d, ex3_state_q : std_ulogic_vector(0 to state_width-1); +signal ex3_t_d, ex3_t_q : std_ulogic_vector(0 to t_width-1); +signal ex3_flush_req_d, ex3_flush_req_q : std_ulogic_vector(0 to thdid_width-1); +signal ex4_valid_d, ex4_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal ex4_ttype_d, ex4_ttype_q : std_ulogic_vector(0 to ttype_width-1); +signal ex4_rs_is_d, ex4_rs_is_q : std_ulogic_vector(0 to rs_is_width-1); +signal ex4_state_d, ex4_state_q : std_ulogic_vector(0 to state_width-1); +signal ex4_t_d, ex4_t_q : std_ulogic_vector(0 to t_width-1); +signal ex5_valid_d, ex5_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal ex5_ttype_d, ex5_ttype_q : std_ulogic_vector(0 to ttype_width-1); +signal ex5_rs_is_d, ex5_rs_is_q : std_ulogic_vector(0 to rs_is_width-1); +signal ex5_state_d, ex5_state_q : std_ulogic_vector(0 to state_width-1); +signal ex5_t_d, ex5_t_q : std_ulogic_vector(0 to t_width-1); +signal ex6_valid_d, ex6_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal ex6_ttype_d, ex6_ttype_q : std_ulogic_vector(0 to ttype_width-1); +signal ex6_isel_d, ex6_isel_q : std_ulogic_vector(0 to 2); +signal ex6_size_d, ex6_size_q : std_ulogic_vector(0 to 3); +signal ex6_gs_d, ex6_gs_q : std_ulogic; +signal ex6_ts_d, ex6_ts_q : std_ulogic; +signal ex6_ind_d, ex6_ind_q : std_ulogic; +signal ex6_pid_d, ex6_pid_q : std_ulogic_vector(0 to pid_width-1); +signal ex6_lpid_d, ex6_lpid_q : std_ulogic_vector(0 to lpid_width-1); +signal inv_seq_d, inv_seq_q : std_ulogic_vector(0 to 5); +signal hold_req_d, hold_req_q : std_ulogic_vector(0 to thdid_width-1); +signal hold_ack_d, hold_ack_q : std_ulogic_vector(0 to thdid_width-1); +signal hold_done_d, hold_done_q : std_ulogic_vector(0 to thdid_width-1); +signal local_barrier_d, local_barrier_q : std_ulogic_vector(0 to thdid_width-1); +signal global_barrier_d, global_barrier_q : std_ulogic_vector(0 to thdid_width-1); +signal barrier_done_d, barrier_done_q : std_ulogic_vector(0 to thdid_width-1); +signal illeg_instr_d, illeg_instr_q : std_ulogic_vector(0 to thdid_width-1); +signal local_reject_d, local_reject_q : std_ulogic_vector(0 to thdid_width-1); +signal inv_seq_inprogress_d, inv_seq_inprogress_q : std_ulogic_vector(0 to 5); +signal snoop_valid_d, snoop_valid_q : std_ulogic_vector(0 to 2); +signal snoop_attr_d, snoop_attr_q : std_ulogic_vector(0 to 34); +signal snoop_vpn_d,snoop_vpn_q : std_ulogic_vector(52-epn_width to 51); +signal snoop_attr_clone_d, snoop_attr_clone_q : std_ulogic_vector(0 to 25); +signal snoop_attr_tlb_spec_d, snoop_attr_tlb_spec_q : std_ulogic_vector(18 to 19); +signal snoop_vpn_clone_d,snoop_vpn_clone_q : std_ulogic_vector(52-epn_width to 51); +signal snoop_ack_d,snoop_ack_q : std_ulogic_vector(0 to 2); +signal snoop_coming_d, snoop_coming_q : std_ulogic_vector(0 to 4); +signal an_ac_back_inv_d, an_ac_back_inv_q : std_ulogic_vector(0 to 8); +signal an_ac_back_inv_addr_d, an_ac_back_inv_addr_q : std_ulogic_vector(64-real_addr_width to 63); +signal an_ac_back_inv_lpar_id_d, an_ac_back_inv_lpar_id_q : std_ulogic_vector(0 to lpid_width-1); +signal lsu_tokens_d, lsu_tokens_q : std_ulogic_vector(0 to 1); +signal lsu_req_d, lsu_req_q : std_ulogic_vector(0 to thdid_width-1); +signal lsu_ttype_d, lsu_ttype_q : std_ulogic_vector(0 to 1); +signal lsu_ubits_d, lsu_ubits_q : std_ulogic_vector(0 to 3); +signal lsu_wimge_d, lsu_wimge_q : std_ulogic_vector(0 to 4); +signal lsu_addr_d, lsu_addr_q : std_ulogic_vector(64-real_addr_width to 63); +signal lsu_lpid_d, lsu_lpid_q : std_ulogic_vector(0 to lpid_width-1); +signal lsu_ind_d, lsu_ind_q : std_ulogic; +signal lsu_gs_d, lsu_gs_q : std_ulogic; +signal lsu_lbit_d, lsu_lbit_q : std_ulogic; +signal xu_mm_ccr2_notlb_d, xu_mm_ccr2_notlb_q : std_ulogic_vector(0 to 12); +signal xu_mm_epcr_dgtmi_q : std_ulogic_vector(0 to thdid_width-1); +signal lpidr_q : std_ulogic_vector(0 to lpid_width-1); +signal mmucr1_q : std_ulogic_vector(12 to 19); +signal mmucr1_csinv_q : std_ulogic_vector(0 to 1); +signal spare_q : std_ulogic_vector(0 to 15); +signal power_managed_d, power_managed_q : std_ulogic_vector(0 to 3); +signal mm_xu_quiesce_d, mm_xu_quiesce_q : std_ulogic_vector(0 to thdid_width-1); +signal inval_quiesce_b : std_ulogic_vector(0 to thdid_width-1); +signal inv_seq_local_done : std_ulogic; +signal inv_seq_snoop_done : std_ulogic; +signal inv_seq_hold_req : std_ulogic_vector(0 to thdid_width-1); +signal inv_seq_hold_done : std_ulogic_vector(0 to thdid_width-1); +signal inv_seq_tlbi_load : std_ulogic; +signal inv_seq_tlbi_complete : std_ulogic; +signal inv_seq_tlb_snoop_val : std_ulogic; +signal inv_seq_htw_load : std_ulogic; +signal inv_seq_ierat_snoop_val : std_ulogic; +signal inv_seq_derat_snoop_val : std_ulogic; +signal inv_seq_snoop_inprogress : std_ulogic; +signal inv_seq_snoop_inprogress_q : std_ulogic_vector(0 to 1); +signal inv_seq_local_inprogress : std_ulogic; +signal inv_seq_local_barrier_set : std_ulogic; +signal inv_seq_global_barrier_set : std_ulogic; +signal inv_seq_local_barrier_done : std_ulogic; +signal inv_seq_global_barrier_done : std_ulogic; +signal inv_seq_idle : std_ulogic; +signal inval_snoop_forme : std_ulogic; +signal inval_snoop_local_reject : std_ulogic; +signal ex6_size_large : std_ulogic; +signal inv_seq_tlb0fi_inprogress : std_ulogic; +signal inv_seq_tlb0fi_inprogress_q : std_ulogic_vector(0 to 1); +signal inv_seq_tlb0fi_done : std_ulogic; +signal ex3_ea_hold : std_ulogic; +signal htw_lsu_req_taken_sig : std_ulogic; +signal inv_seq_tlbwe_inprogress : std_ulogic; +signal inv_seq_tlbwe_inprogress_q : std_ulogic_vector(0 to 1); +signal inv_seq_tlbwe_snoop_done : std_ulogic; +signal tlbwe_back_inv_tid_nz : std_ulogic; +signal tlbwe_back_inv_d, tlbwe_back_inv_q : std_ulogic_vector(0 to thdid_width+1); +signal tlbwe_back_inv_addr_d, tlbwe_back_inv_addr_q : std_ulogic_vector(52-epn_width to 51); +signal tlbwe_back_inv_attr_d, tlbwe_back_inv_attr_q : std_ulogic_vector(0 to 34); +signal back_inv_tid_nz : std_ulogic; +signal ex6_tid_nz : std_ulogic; +signal ex2_rs_pgsize_not_supp : std_ulogic; +signal mas6_isize_not_supp : std_ulogic_vector(0 to thdid_width-1); +signal ex2_hv_state : std_ulogic; +signal ex2_priv_state : std_ulogic; +signal ex2_dgtmi_state : std_ulogic; +signal ex5_hv_state : std_ulogic; +signal ex5_priv_state : std_ulogic; +signal ex5_dgtmi_state : std_ulogic; +signal unused_dc : std_ulogic_vector(0 to 12); +-- synopsys translate_off +-- synopsys translate_on +signal pc_sg_1 : std_ulogic; +signal pc_sg_0 : std_ulogic; +signal pc_fce_1 : std_ulogic; +signal pc_fce_0 : std_ulogic; +signal pc_func_sl_thold_1 : std_ulogic; +signal pc_func_sl_thold_0 : std_ulogic; +signal pc_func_sl_thold_0_b : std_ulogic; +signal pc_func_slp_sl_thold_1 : std_ulogic; +signal pc_func_slp_sl_thold_0 : std_ulogic; +signal pc_func_slp_sl_thold_0_b : std_ulogic; +signal pc_func_slp_nsl_thold_1 : std_ulogic; +signal pc_func_slp_nsl_thold_0 : std_ulogic; +signal pc_func_slp_nsl_thold_0_b : std_ulogic; +signal pc_func_sl_force : std_ulogic; +signal pc_func_slp_sl_force : std_ulogic; +signal pc_func_slp_nsl_force : std_ulogic; +signal siv : std_ulogic_vector(0 to scan_right); +signal sov : std_ulogic_vector(0 to scan_right); +signal tidn : std_ulogic; +signal tiup : std_ulogic; +begin +tidn <= '0'; +tiup <= '1'; +xu_mm_ccr2_notlb_d <= (others => xu_mm_ccr2_notlb); +power_managed_d(0) <= ac_an_power_managed; +power_managed_d(1) <= power_managed_q(1); +power_managed_d(2) <= power_managed_q(2); +power_managed_d(3) <= power_managed_q(3); +mm_xu_quiesce <= mm_xu_quiesce_q; +mm_xu_quiesce_d <= tlb_req_quiesce and tlb_ctl_quiesce and + htw_quiesce and + not inval_quiesce_b; +inval_quiesce_b <= ( (0 to thdid_width-1 => or_reduce(inv_seq_q)) and ex6_valid_q(0 to thdid_width-1) ); +ex1_valid_d <= xu_mm_rf1_val and not(xu_rf1_flush); +ex1_ttype_d(0 to ttype_width-3) <= xu_mm_rf1_is_tlbilx & xu_mm_rf1_is_tlbivax & xu_mm_rf1_is_eratilx & xu_mm_rf1_is_erativax; +ex1_state_d(0) <= or_reduce(xu_mm_msr_gs and xu_mm_rf1_val); +ex1_state_d(1) <= or_reduce(xu_mm_msr_pr and xu_mm_rf1_val); +ex1_t_d <= xu_mm_rf1_t; +ex2_valid_d <= ex1_valid_q and not(xu_ex1_flush); +ex2_ttype_d(0 to ttype_width-3) <= ex1_ttype_q(0 to ttype_width-3); +ex2_ttype_d(ttype_width-2 to ttype_width-1) <= xu_mm_ex1_is_csync & xu_mm_ex1_is_isync; +ex2_rs_is_d <= xu_mm_ex1_rs_is; +ex2_state_d <= ex1_state_q; +ex2_t_d <= ex1_t_q; +ex3_ea_hold <= (or_reduce(ex3_valid_q) and or_reduce(ex3_ttype_q(0 to 3))) + or (or_reduce(ex4_valid_q) and or_reduce(ex4_ttype_q(0 to 3))) + or (or_reduce(ex5_valid_q) and or_reduce(ex5_ttype_q(0 to 3))) + or (or_reduce(ex6_valid_q) and or_reduce(ex6_ttype_q(0 to 3))); +ex3_ea_d <= (ex3_ea_q and (64-rs_data_width to 63 => ex3_ea_hold)) + or (xu_mm_ex2_eff_addr and (64-rs_data_width to 63 => not ex3_ea_hold)); +ex2_hv_state <= not ex2_state_q(0) and not ex2_state_q(1); +ex2_priv_state <= not ex2_state_q(1); +ex2_dgtmi_state <= or_reduce(ex2_valid_q and xu_mm_epcr_dgtmi_q); +ex3_valid_d <= ex2_valid_q and not(xu_ex2_flush); +ex3_ttype_d(0 to ttype_width-3) <= ex2_ttype_q(0 to ttype_width-3); +ex3_ttype_d(ttype_width-2) <= (ex2_ttype_q(ttype_width-2) and not mmucr1_csinv_q(0)); +ex3_ttype_d(ttype_width-1) <= (ex2_ttype_q(ttype_width-1) and not mmucr1_csinv_q(1)); +ex3_rs_is_d <= ex2_rs_is_q; +ex3_state_d <= ex2_state_q; +ex3_t_d <= ex2_t_q; +ex3_flush_req_d <= (ex2_valid_q and not(xu_ex2_flush)) + when ( ex2_ttype_q(0 to 3)/="0000" and + ( inv_seq_idle='0' or + (ex3_valid_q/="0000" and ex3_ttype_q(0 to 3)/="0000") or + (ex4_valid_q/="0000" and ex4_ttype_q(0 to 3)/="0000") or + (ex5_valid_q/="0000" and ex5_ttype_q(0 to 3)/="0000") or + (ex6_valid_q/="0000" and ex6_ttype_q(0 to 3)/="0000") ) ) + else tlb_ctl_ex2_flush_req; +ex4_valid_d <= ex3_valid_q and not(xu_ex3_flush); +ex4_ttype_d <= ex3_ttype_q; +ex4_rs_is_d <= ex3_rs_is_q; +ex4_state_d <= ex3_state_q; +ex4_t_d <= ex3_t_q; +ex5_valid_d <= ex4_valid_q and not(xu_ex4_flush); +ex5_ttype_d <= ex4_ttype_q; +ex5_rs_is_d <= ex4_rs_is_q; +ex5_state_d <= ex4_state_q; +ex5_t_d <= ex4_t_q; +ex5_hv_state <= not ex5_state_q(0) and not ex5_state_q(1); +ex5_priv_state <= not ex5_state_q(1); +ex5_dgtmi_state <= or_reduce(ex5_valid_q and xu_mm_epcr_dgtmi_q); +ex6_valid_d <= "0000" when inv_seq_local_done='1' + else (ex5_valid_q and not(xu_ex5_flush)) when ( ex6_valid_q="0000" and + ((ex5_ttype_q(0)='1' and ex5_priv_state='1' and ex5_dgtmi_state='0') or + (ex5_ttype_q(0)='1' and ex5_hv_state='1' and ex5_dgtmi_state='1') or + (or_reduce(ex5_ttype_q(1 to 3))='1' and ex5_hv_state='1')) ) + else ex6_valid_q; +ex6_ttype_d <= ex5_ttype_q when (ex5_valid_q /= "0000" and ex5_ttype_q(0 to 3)/="0000" and ex6_valid_q="0000") + else ex6_ttype_q; +ex6_isel_d <= '1' & ex5_rs_is_q(3 to 4) when (ex5_valid_q /= "0000" and ex5_ttype_q(3)='1' and ex5_rs_is_q(1 to 2)="10" and ex6_valid_q="0000") + else '0' & ex5_rs_is_q(1 to 2) when (ex5_valid_q /= "0000" and ex5_ttype_q(3)='1' and ex5_rs_is_q(1 to 2)/="10" and ex6_valid_q="0000") + else ex5_t_q(0 to 2) when (ex5_valid_q /= "0000" and ex5_ttype_q(2)='1' and ex6_valid_q="0000") + else "011" when (ex5_valid_q /= "0000" and ex5_ttype_q(1)='1' and ex6_valid_q="0000") + else ex5_t_q(0 to 2) when (ex5_valid_q /= "0000" and ex5_ttype_q(0)='1' and ex6_valid_q="0000") + else ex6_isel_q; +ex6_size_d <= ex5_rs_is_q(5 to 8) when (ex5_valid_q /= "0000" and ex5_ttype_q(3)='1' and ex6_valid_q="0000") + else "0000" when (ex5_valid_q /= "0000" and ex5_ttype_q(2)='1' and ex6_valid_q="0000") + else mas6_0_isize when (ex5_valid_q(0)='1' and ex5_ttype_q(0 to 1)/="00" and ex6_valid_q="0000") + else mas6_1_isize when (ex5_valid_q(1)='1' and ex5_ttype_q(0 to 1)/="00" and ex6_valid_q="0000") + else mas6_2_isize when (ex5_valid_q(2)='1' and ex5_ttype_q(0 to 1)/="00" and ex6_valid_q="0000") + else mas6_3_isize when (ex5_valid_q(3)='1' and ex5_ttype_q(0 to 1)/="00" and ex6_valid_q="0000") + else ex6_size_q; +ex6_size_large <= '1' when (ex6_size_q=TLB_PgSize_64KB or ex6_size_q=TLB_PgSize_1MB or + ex6_size_q=TLB_PgSize_16MB or ex6_size_q=TLB_PgSize_256MB or ex6_size_q=TLB_PgSize_1GB) + else '0'; +ex6_gs_d <= mmucr0_0(2) when (ex5_valid_q(0)='1' and ex5_ttype_q(2 to 3)/="00" and ex6_valid_q="0000") + else mmucr0_1(2) when (ex5_valid_q(1)='1' and ex5_ttype_q(2 to 3)/="00" and ex6_valid_q="0000") + else mmucr0_2(2) when (ex5_valid_q(2)='1' and ex5_ttype_q(2 to 3)/="00" and ex6_valid_q="0000") + else mmucr0_3(2) when (ex5_valid_q(3)='1' and ex5_ttype_q(2 to 3)/="00" and ex6_valid_q="0000") + else mas5_0_sgs when (ex5_valid_q(0)='1' and ex5_ttype_q(0 to 1)/="00" and ex6_valid_q="0000") + else mas5_1_sgs when (ex5_valid_q(1)='1' and ex5_ttype_q(0 to 1)/="00" and ex6_valid_q="0000") + else mas5_2_sgs when (ex5_valid_q(2)='1' and ex5_ttype_q(0 to 1)/="00" and ex6_valid_q="0000") + else mas5_3_sgs when (ex5_valid_q(3)='1' and ex5_ttype_q(0 to 1)/="00" and ex6_valid_q="0000") + else ex6_gs_q; +ex6_ts_d <= mmucr0_0(3) when (ex5_valid_q(0)='1' and ex5_ttype_q(2 to 3)/="00" and ex6_valid_q="0000") + else mmucr0_1(3) when (ex5_valid_q(1)='1' and ex5_ttype_q(2 to 3)/="00" and ex6_valid_q="0000") + else mmucr0_2(3) when (ex5_valid_q(2)='1' and ex5_ttype_q(2 to 3)/="00" and ex6_valid_q="0000") + else mmucr0_3(3) when (ex5_valid_q(3)='1' and ex5_ttype_q(2 to 3)/="00" and ex6_valid_q="0000") + else mas6_0_sas when (ex5_valid_q(0)='1' and ex5_ttype_q(0 to 1)/="00" and ex6_valid_q="0000") + else mas6_1_sas when (ex5_valid_q(1)='1' and ex5_ttype_q(0 to 1)/="00" and ex6_valid_q="0000") + else mas6_2_sas when (ex5_valid_q(2)='1' and ex5_ttype_q(0 to 1)/="00" and ex6_valid_q="0000") + else mas6_3_sas when (ex5_valid_q(3)='1' and ex5_ttype_q(0 to 1)/="00" and ex6_valid_q="0000") + else ex6_ts_q; +ex6_ind_d <= '0' when (ex5_valid_q(0)='1' and ex5_ttype_q(2 to 3)/="00" and ex6_valid_q="0000") + else '0' when (ex5_valid_q(1)='1' and ex5_ttype_q(2 to 3)/="00" and ex6_valid_q="0000") + else '0' when (ex5_valid_q(2)='1' and ex5_ttype_q(2 to 3)/="00" and ex6_valid_q="0000") + else '0' when (ex5_valid_q(3)='1' and ex5_ttype_q(2 to 3)/="00" and ex6_valid_q="0000") + else mas6_0_sind when (ex5_valid_q(0)='1' and ex5_ttype_q(0 to 1)/="00" and ex6_valid_q="0000") + else mas6_1_sind when (ex5_valid_q(1)='1' and ex5_ttype_q(0 to 1)/="00" and ex6_valid_q="0000") + else mas6_2_sind when (ex5_valid_q(2)='1' and ex5_ttype_q(0 to 1)/="00" and ex6_valid_q="0000") + else mas6_3_sind when (ex5_valid_q(3)='1' and ex5_ttype_q(0 to 1)/="00" and ex6_valid_q="0000") + else ex6_ind_q; +ex6_pid_d <= mmucr0_0(6 to 19) when (ex5_valid_q(0)='1' and ex5_ttype_q(2 to 3)/="00" and ex6_valid_q="0000") + else mmucr0_1(6 to 19) when (ex5_valid_q(1)='1' and ex5_ttype_q(2 to 3)/="00" and ex6_valid_q="0000") + else mmucr0_2(6 to 19) when (ex5_valid_q(2)='1' and ex5_ttype_q(2 to 3)/="00" and ex6_valid_q="0000") + else mmucr0_3(6 to 19) when (ex5_valid_q(3)='1' and ex5_ttype_q(2 to 3)/="00" and ex6_valid_q="0000") + else mas6_0_spid when (ex5_valid_q(0)='1' and ex5_ttype_q(0 to 1)/="00" and ex6_valid_q="0000") + else mas6_1_spid when (ex5_valid_q(1)='1' and ex5_ttype_q(0 to 1)/="00" and ex6_valid_q="0000") + else mas6_2_spid when (ex5_valid_q(2)='1' and ex5_ttype_q(0 to 1)/="00" and ex6_valid_q="0000") + else mas6_3_spid when (ex5_valid_q(3)='1' and ex5_ttype_q(0 to 1)/="00" and ex6_valid_q="0000") + else ex6_pid_q; +ex6_lpid_d <= lpidr_q when (ex5_valid_q(0)='1' and ex5_ttype_q(2 to 3)/="00" and ex6_valid_q="0000") + else lpidr_q when (ex5_valid_q(1)='1' and ex5_ttype_q(2 to 3)/="00" and ex6_valid_q="0000") + else lpidr_q when (ex5_valid_q(2)='1' and ex5_ttype_q(2 to 3)/="00" and ex6_valid_q="0000") + else lpidr_q when (ex5_valid_q(3)='1' and ex5_ttype_q(2 to 3)/="00" and ex6_valid_q="0000") + else mas5_0_slpid when (ex5_valid_q(0)='1' and ex5_ttype_q(0 to 1)/="00" and ex6_valid_q="0000") + else mas5_1_slpid when (ex5_valid_q(1)='1' and ex5_ttype_q(0 to 1)/="00" and ex6_valid_q="0000") + else mas5_2_slpid when (ex5_valid_q(2)='1' and ex5_ttype_q(0 to 1)/="00" and ex6_valid_q="0000") + else mas5_3_slpid when (ex5_valid_q(3)='1' and ex5_ttype_q(0 to 1)/="00" and ex6_valid_q="0000") + else ex6_lpid_q; +local_barrier_d <= (local_barrier_q and not(ex6_valid_q)) when inv_seq_local_barrier_done='1' + else (ex6_valid_q or local_barrier_q) when inv_seq_local_barrier_set='1' + else local_barrier_q; +global_barrier_d <= (others => '0') when ((inv_seq_global_barrier_done='1' and an_ac_back_inv_q(7)='1') or inval_snoop_local_reject='1') + else (ex6_valid_q or global_barrier_q) when inv_seq_global_barrier_set='1' + else global_barrier_q; +barrier_done_d <= (local_barrier_q and ex6_valid_q) when inv_seq_local_barrier_done='1' + else global_barrier_q when ((inv_seq_global_barrier_done='1' and an_ac_back_inv_q(7)='1') or inval_snoop_local_reject='1') + else tlb_ctl_barrier_done; +ex2_rs_pgsize_not_supp <= '0' when (ex2_rs_is_q(5 to 8)=TLB_PgSize_4KB or ex2_rs_is_q(5 to 8)=TLB_PgSize_64KB or + ex2_rs_is_q(5 to 8)=TLB_PgSize_1MB or ex2_rs_is_q(5 to 8)=TLB_PgSize_16MB or + ex2_rs_is_q(5 to 8)=TLB_PgSize_1GB ) else '1'; +mas6_isize_not_supp(0) <= '0' when ((mas6_0_isize=TLB_PgSize_4KB or mas6_0_isize=TLB_PgSize_64KB or + mas6_0_isize=TLB_PgSize_1MB or mas6_0_isize=TLB_PgSize_16MB or + mas6_0_isize=TLB_PgSize_1GB) and mas6_0_sind='0') + or ((mas6_0_isize=TLB_PgSize_1MB or mas6_0_isize=TLB_PgSize_256MB) and mas6_0_sind='1') + else '1'; +mas6_isize_not_supp(1) <= '0' when ((mas6_1_isize=TLB_PgSize_4KB or mas6_1_isize=TLB_PgSize_64KB or + mas6_1_isize=TLB_PgSize_1MB or mas6_1_isize=TLB_PgSize_16MB or + mas6_1_isize=TLB_PgSize_1GB) and mas6_1_sind='0') + or ((mas6_1_isize=TLB_PgSize_1MB or mas6_1_isize=TLB_PgSize_256MB) and mas6_1_sind='1') + else '1'; +mas6_isize_not_supp(2) <= '0' when ((mas6_2_isize=TLB_PgSize_4KB or mas6_2_isize=TLB_PgSize_64KB or + mas6_2_isize=TLB_PgSize_1MB or mas6_2_isize=TLB_PgSize_16MB or + mas6_2_isize=TLB_PgSize_1GB) and mas6_2_sind='0') + or ((mas6_2_isize=TLB_PgSize_1MB or mas6_2_isize=TLB_PgSize_256MB) and mas6_2_sind='1') + else '1'; +mas6_isize_not_supp(3) <= '0' when ((mas6_3_isize=TLB_PgSize_4KB or mas6_3_isize=TLB_PgSize_64KB or + mas6_3_isize=TLB_PgSize_1MB or mas6_3_isize=TLB_PgSize_16MB or + mas6_3_isize=TLB_PgSize_1GB) and mas6_3_sind='0') + or ((mas6_3_isize=TLB_PgSize_1MB or mas6_3_isize=TLB_PgSize_256MB) and mas6_3_sind='1') + else '1'; +illeg_instr_d <= ( ex2_valid_q and mas6_isize_not_supp and (0 to 3 => (ex2_ttype_q(1) and ex2_hv_state)) ) + or ( ex2_valid_q and mas6_isize_not_supp and (0 to 3 => (ex2_ttype_q(0) and Eq(ex2_t_q,"011") and + (ex2_hv_state or (ex2_priv_state and not ex2_dgtmi_state)))) ) + or ( ex2_valid_q and (0 to 3 => (ex2_ttype_q(3) and ex2_hv_state and ex2_rs_pgsize_not_supp)) ) + or ( ex2_valid_q and (0 to 3 => (ex2_ttype_q(2) and ex2_hv_state and ex2_t_q(0) and mmucr1_q(pos_ictid) and mmucr1_q(pos_dctid))) ) + or ( tlb_ctl_ex2_illeg_instr ); +Inv_Sequencer: PROCESS (inv_seq_q, inval_snoop_forme, xu_mm_lmq_stq_empty, iu_mm_lmq_empty, hold_ack_q, lsu_tokens_q, xu_mm_ccr2_notlb_q(0), + snoop_ack_q, ex6_valid_q, ex6_ttype_q(0 to 3), ex6_ind_q, ex6_isel_q, + mmucsr0_tlb0fi, + tlbwe_back_inv_q(thdid_width+1), + an_ac_back_inv_q(6), an_ac_back_inv_addr_q(54 to 55), htw_lsu_req_valid, lsu_req_q, + power_managed_q(0), power_managed_q(2), power_managed_q(3)) +BEGIN +inv_seq_idle <= '0'; +inv_seq_snoop_inprogress <= '0'; +inv_seq_local_inprogress <= '0'; +inv_seq_local_barrier_set <= '0'; +inv_seq_global_barrier_set <= '0'; +inv_seq_local_barrier_done <= '0'; +inv_seq_global_barrier_done <= '0'; +inv_seq_snoop_done <= '0'; +inv_seq_local_done <= '0'; +inv_seq_tlbi_load <= '0'; +inv_seq_tlbi_complete <= '0'; +inv_seq_htw_load <= '0'; +htw_lsu_req_taken_sig <= '0'; +inv_seq_hold_req(0 to 3) <= (others => '0'); +inv_seq_hold_done(0 to 3) <= (others => '0'); +inv_seq_tlb_snoop_val <= '0'; +inv_seq_ierat_snoop_val <= '0'; +inv_seq_derat_snoop_val <= '0'; +inv_seq_tlb0fi_inprogress <= '0'; +inv_seq_tlb0fi_done <= '0'; +inv_seq_tlbwe_snoop_done <= '0'; +inv_seq_tlbwe_inprogress <= '0'; +CASE inv_seq_q IS + WHEN InvSeq_Idle => + + inv_seq_idle <= '1'; + if inval_snoop_forme='1' then + inv_seq_snoop_inprogress <= '1'; + inv_seq_hold_req(0 to 3) <= "1111"; + inv_seq_d <= InvSeq_Stg8; + elsif htw_lsu_req_valid='1' then + inv_seq_d <= InvSeq_Stg31; + elsif ex6_valid_q/="0000" and (ex6_ttype_q(1)='1' or ex6_ttype_q(3)='1') then + inv_seq_local_inprogress <= '1'; + inv_seq_global_barrier_set <= '1'; + inv_seq_d <= InvSeq_Stg1; + elsif ex6_valid_q/="0000" and (ex6_ttype_q(0)='1' or ex6_ttype_q(2)='1') then + inv_seq_hold_req(0 to 3) <= "1111"; + inv_seq_local_inprogress <= '1'; + inv_seq_local_barrier_set <= '1'; + inv_seq_d <= InvSeq_Stg2; + elsif mmucsr0_tlb0fi='1' then + inv_seq_hold_req(0 to 3) <= "1111"; + inv_seq_tlb0fi_inprogress <= '1'; + inv_seq_d <= InvSeq_Stg16; + elsif tlbwe_back_inv_q(thdid_width+1)='1' then + inv_seq_hold_req(0 to 3) <= "1111"; + inv_seq_tlbwe_inprogress <= '1'; + inv_seq_d <= InvSeq_Stg24; + else + inv_seq_d <= InvSeq_Idle; + end if; + WHEN InvSeq_Stg1 => + inv_seq_local_inprogress <= '1'; + if lsu_tokens_q/="00" then + inv_seq_tlbi_load <= '1'; + inv_seq_local_done <= '1'; + inv_seq_d <= InvSeq_Idle; + else + inv_seq_d <= InvSeq_Stg1; + end if; + WHEN InvSeq_Stg2 => + inv_seq_local_inprogress <= '1'; + if hold_ack_q="1111" then + inv_seq_d <= InvSeq_Stg3; + elsif htw_lsu_req_valid='1' then + inv_seq_d <= InvSeq_Stg23; + else + inv_seq_d <= InvSeq_Stg2; + end if; + + WHEN InvSeq_Stg3 => + inv_seq_local_inprogress <= '1'; + if iu_mm_lmq_empty='1' and xu_mm_lmq_stq_empty='1' and xu_mm_ccr2_notlb_q(0)=MMU_Mode_Value and ex6_ttype_q(0)='1' then + inv_seq_d <= InvSeq_Stg4; + elsif iu_mm_lmq_empty='1' and xu_mm_lmq_stq_empty='1' then + inv_seq_d <= InvSeq_Stg6; + else + inv_seq_d <= InvSeq_Stg3; + end if; + + WHEN InvSeq_Stg4 => + inv_seq_local_inprogress <= '1'; + inv_seq_tlb_snoop_val <= '1'; + inv_seq_d <= InvSeq_Stg5; + + WHEN InvSeq_Stg5 => + inv_seq_local_inprogress <= '1'; + if snoop_ack_q(2)='1' then + inv_seq_d <= InvSeq_Stg6; + else + inv_seq_d <= InvSeq_Stg5; + end if; + + WHEN InvSeq_Stg6 => + inv_seq_local_inprogress <= '1'; + inv_seq_ierat_snoop_val <= not(ex6_ind_q and Eq(ex6_isel_q,"011")); + inv_seq_derat_snoop_val <= not(ex6_ind_q and Eq(ex6_isel_q,"011")); + inv_seq_d <= InvSeq_Stg7; + + WHEN InvSeq_Stg7 => + inv_seq_local_inprogress <= '1'; + if (snoop_ack_q(0 to 1)="11" or (ex6_ind_q and Eq(ex6_isel_q,"011"))='1') then + inv_seq_local_done <= '1'; + inv_seq_local_barrier_done <= '1'; + inv_seq_hold_done(0 to 3) <= "1111"; + inv_seq_d <= InvSeq_Idle; + else + inv_seq_d <= InvSeq_Stg7; + end if; + + WHEN InvSeq_Stg8 => + inv_seq_snoop_inprogress <= '1'; + if (hold_ack_q="1111" or (power_managed_q(0)='1' and power_managed_q(2)='1')) then + inv_seq_d <= InvSeq_Stg9; + elsif htw_lsu_req_valid='1' then + inv_seq_d <= InvSeq_Stg28; + else + inv_seq_d <= InvSeq_Stg8; + end if; + + WHEN InvSeq_Stg9 => + inv_seq_snoop_inprogress <= '1'; + inv_seq_d <= InvSeq_Stg10; + + WHEN InvSeq_Stg10 => + inv_seq_snoop_inprogress <= '1'; + if (power_managed_q(0)='1' and power_managed_q(3)='1') then + inv_seq_d <= InvSeq_Stg14; + elsif ( (iu_mm_lmq_empty='1' or power_managed_q(0)='1') and + (xu_mm_lmq_stq_empty='1' or (power_managed_q(0)='1' and power_managed_q(2)='1')) and + xu_mm_ccr2_notlb_q(0)=MMU_Mode_Value ) then + inv_seq_d <= InvSeq_Stg11; + elsif ( (iu_mm_lmq_empty='1' or power_managed_q(0)='1') and + (xu_mm_lmq_stq_empty='1' or (power_managed_q(0)='1' and power_managed_q(2)='1')) ) then + inv_seq_d <= InvSeq_Stg13; + else + inv_seq_d <= InvSeq_Stg10; + end if; + + WHEN InvSeq_Stg11 => + inv_seq_snoop_inprogress <= '1'; + inv_seq_tlb_snoop_val <= '1'; + inv_seq_d <= InvSeq_Stg12; + + WHEN InvSeq_Stg12 => + inv_seq_snoop_inprogress <= '1'; + if snoop_ack_q(2)='1' or (power_managed_q(0)='1' and power_managed_q(2)='1') then + inv_seq_d <= InvSeq_Stg13; + else + inv_seq_d <= InvSeq_Stg12; + end if; + + WHEN InvSeq_Stg13 => + inv_seq_snoop_inprogress <= '1'; + inv_seq_ierat_snoop_val <= not(an_ac_back_inv_q(6) and Eq(an_ac_back_inv_addr_q(54 to 55),"11")); + inv_seq_derat_snoop_val <= not(an_ac_back_inv_q(6) and Eq(an_ac_back_inv_addr_q(54 to 55),"11")); + inv_seq_d <= InvSeq_Stg14; + + WHEN InvSeq_Stg14 => + inv_seq_snoop_inprogress <= '1'; + if (power_managed_q(0)='1' and power_managed_q(2)='1') then + inv_seq_tlbi_complete <= '1'; + inv_seq_d <= InvSeq_Stg15; + elsif lsu_tokens_q/="00" and (snoop_ack_q(0 to 1)="11" or (an_ac_back_inv_q(6) and Eq(an_ac_back_inv_addr_q(54 to 55),"11"))='1') then + inv_seq_tlbi_complete <= '1'; + inv_seq_d <= InvSeq_Stg15; + else + inv_seq_d <= InvSeq_Stg14; + end if; + + WHEN InvSeq_Stg15 => + if (lsu_req_q="0000" and lsu_tokens_q/="00") or (power_managed_q(0)='1' and power_managed_q(2)='1') then + inv_seq_snoop_inprogress <= '0'; + inv_seq_snoop_done <= '1'; + inv_seq_hold_done(0 to 3) <= "1111"; + inv_seq_global_barrier_done <= '1'; + inv_seq_d <= InvSeq_Idle; + else + inv_seq_snoop_inprogress <= '1'; + inv_seq_d <= InvSeq_Stg15; + end if; + + + WHEN InvSeq_Stg16 => + inv_seq_tlb0fi_inprogress <= '1'; + if hold_ack_q="1111" then + inv_seq_d <= InvSeq_Stg17; + elsif htw_lsu_req_valid='1' then + inv_seq_d <= InvSeq_Stg22; + else + inv_seq_d <= InvSeq_Stg16; + end if; + + WHEN InvSeq_Stg17 => + inv_seq_tlb0fi_inprogress <= '1'; + if iu_mm_lmq_empty='1' and xu_mm_lmq_stq_empty='1' and xu_mm_ccr2_notlb_q(0)=MMU_Mode_Value then + inv_seq_d <= InvSeq_Stg18; + elsif iu_mm_lmq_empty='1' and xu_mm_lmq_stq_empty='1' then + inv_seq_d <= InvSeq_Stg20; + else + inv_seq_d <= InvSeq_Stg17; + end if; + + WHEN InvSeq_Stg18 => + inv_seq_tlb0fi_inprogress <= '1'; + inv_seq_tlb_snoop_val <= '1'; + inv_seq_d <= InvSeq_Stg19; + + WHEN InvSeq_Stg19 => + inv_seq_tlb0fi_inprogress <= '1'; + if snoop_ack_q(2)='1' then + inv_seq_d <= InvSeq_Stg20; + else + inv_seq_d <= InvSeq_Stg19; + end if; + + WHEN InvSeq_Stg20 => + inv_seq_tlb0fi_inprogress <= '1'; + inv_seq_ierat_snoop_val <= '1'; + inv_seq_derat_snoop_val <= '1'; + inv_seq_d <= InvSeq_Stg21; + + WHEN InvSeq_Stg21 => + if (snoop_ack_q(0 to 1)="11") then + inv_seq_tlb0fi_inprogress <= '0'; + inv_seq_tlb0fi_done <= '1'; + inv_seq_hold_done(0 to 3) <= "1111"; + inv_seq_d <= InvSeq_Idle; + else + inv_seq_tlb0fi_inprogress <= '1'; + inv_seq_d <= InvSeq_Stg21; + end if; + WHEN InvSeq_Stg22 => + inv_seq_tlb0fi_inprogress <= '1'; + if lsu_tokens_q/="00" then + inv_seq_htw_load <= '1'; + htw_lsu_req_taken_sig <= '1'; + inv_seq_d <= InvSeq_Stg16; + else + inv_seq_d <= InvSeq_Stg22; + end if; + + WHEN InvSeq_Stg23 => + inv_seq_local_inprogress <= '1'; + if lsu_tokens_q/="00" then + inv_seq_htw_load <= '1'; + htw_lsu_req_taken_sig <= '1'; + inv_seq_d <= InvSeq_Stg2; + else + inv_seq_d <= InvSeq_Stg23; + end if; + + WHEN InvSeq_Stg24 => + inv_seq_tlbwe_inprogress <= '1'; + if hold_ack_q="1111" then + inv_seq_d <= InvSeq_Stg25; + elsif htw_lsu_req_valid='1' then + inv_seq_d <= InvSeq_Stg29; + else + inv_seq_d <= InvSeq_Stg24; + end if; + + WHEN InvSeq_Stg25 => + inv_seq_tlbwe_inprogress <= '1'; + if iu_mm_lmq_empty='1' and xu_mm_lmq_stq_empty='1' then + inv_seq_d <= InvSeq_Stg26; + else + inv_seq_d <= InvSeq_Stg25; + end if; + + WHEN InvSeq_Stg26 => + inv_seq_tlbwe_inprogress <= '1'; + inv_seq_ierat_snoop_val <= '1'; + inv_seq_derat_snoop_val <= '1'; + inv_seq_d <= InvSeq_Stg27; + + WHEN InvSeq_Stg27 => + if (snoop_ack_q(0 to 1)="11") then + inv_seq_tlbwe_inprogress <= '0'; + inv_seq_tlbwe_snoop_done <= '1'; + inv_seq_hold_done(0 to 3) <= "1111"; + inv_seq_d <= InvSeq_Idle; + else + inv_seq_tlbwe_inprogress <= '1'; + inv_seq_d <= InvSeq_Stg27; + end if; + WHEN InvSeq_Stg29 => + inv_seq_tlbwe_inprogress <= '1'; + if lsu_tokens_q/="00" then + inv_seq_htw_load <= '1'; + htw_lsu_req_taken_sig <= '1'; + inv_seq_d <= InvSeq_Stg24; + else + inv_seq_d <= InvSeq_Stg29; + end if; + + WHEN InvSeq_Stg28 => + inv_seq_snoop_inprogress <= '1'; + if lsu_tokens_q/="00" then + inv_seq_htw_load <= '1'; + htw_lsu_req_taken_sig <= '1'; + inv_seq_d <= InvSeq_Stg8; + else + inv_seq_d <= InvSeq_Stg28; + end if; + WHEN InvSeq_Stg31 => + if lsu_tokens_q/="00" then + inv_seq_htw_load <= '1'; + htw_lsu_req_taken_sig <= '1'; + inv_seq_d <= InvSeq_Idle; + else + inv_seq_d <= InvSeq_Stg31; + end if; + WHEN OTHERS => + inv_seq_d <= InvSeq_Idle; + END CASE; +END PROCESS Inv_Sequencer; +hold_req_d <= inv_seq_hold_req; +hold_done_d <= inv_seq_hold_done; +inv_seq_inprogress_d(0) <= inv_seq_snoop_inprogress; +inv_seq_inprogress_d(1) <= inv_seq_snoop_inprogress; +inv_seq_inprogress_d(2) <= inv_seq_tlb0fi_inprogress; +inv_seq_inprogress_d(3) <= inv_seq_tlb0fi_inprogress; +inv_seq_inprogress_d(4) <= inv_seq_tlbwe_inprogress; +inv_seq_inprogress_d(5) <= inv_seq_tlbwe_inprogress; +inv_seq_snoop_inprogress_q(0) <= inv_seq_inprogress_q(0); +inv_seq_snoop_inprogress_q(1) <= inv_seq_inprogress_q(1); +inv_seq_tlb0fi_inprogress_q(0) <= inv_seq_inprogress_q(2); +inv_seq_tlb0fi_inprogress_q(1) <= inv_seq_inprogress_q(3); +inv_seq_tlbwe_inprogress_q(0) <= inv_seq_inprogress_q(4); +inv_seq_tlbwe_inprogress_q(1) <= inv_seq_inprogress_q(5); +hold_ack_d(0) <= '0' when (inv_seq_snoop_done='1' or inv_seq_local_done='1' or inv_seq_tlb0fi_done='1' or inv_seq_tlbwe_snoop_done='1') + else xu_mm_hold_ack(0) when hold_ack_q(0)='0' + else hold_ack_q(0); +hold_ack_d(1) <= '0' when (inv_seq_snoop_done='1' or inv_seq_local_done='1' or inv_seq_tlb0fi_done='1' or inv_seq_tlbwe_snoop_done='1') + else xu_mm_hold_ack(1) when hold_ack_q(1)='0' + else hold_ack_q(1); +hold_ack_d(2) <= '0' when (inv_seq_snoop_done='1' or inv_seq_local_done='1' or inv_seq_tlb0fi_done='1' or inv_seq_tlbwe_snoop_done='1') + else xu_mm_hold_ack(2) when hold_ack_q(2)='0' + else hold_ack_q(2); +hold_ack_d(3) <= '0' when (inv_seq_snoop_done='1' or inv_seq_local_done='1' or inv_seq_tlb0fi_done='1' or inv_seq_tlbwe_snoop_done='1') + else xu_mm_hold_ack(3) when hold_ack_q(3)='0' + else hold_ack_q(3); +mm_xu_hold_req <= hold_req_q; +mm_xu_hold_done <= hold_done_q; +mm_xu_ex3_flush_req <= ex3_flush_req_q; +mm_iu_barrier_done <= barrier_done_q; +mm_xu_illeg_instr <= illeg_instr_q; +mm_xu_local_snoop_reject <= local_reject_q; +mmq_inval_tlb0fi_done <= inv_seq_tlb0fi_done; +inval_snoop_forme <= ( an_ac_back_inv_q(2) and an_ac_back_inv_q(3) and not(power_managed_q(0) and power_managed_q(1)) and Eq(xu_mm_ccr2_notlb_q(0),MMU_Mode_Value) and not mmucr1_q(pos_tlbi_rej) ) + or ( an_ac_back_inv_q(2) and an_ac_back_inv_q(3) and not(power_managed_q(0) and power_managed_q(1)) and Eq(an_ac_back_inv_lpar_id_q,lpidr_q) ); +inval_snoop_local_reject <= ( an_ac_back_inv_q(2) and an_ac_back_inv_q(3) and not(power_managed_q(0) and power_managed_q(1)) and an_ac_back_inv_q(7) + and not Eq(an_ac_back_inv_lpar_id_q,lpidr_q) and (Eq(xu_mm_ccr2_notlb_q(0),ERAT_Mode_Value) or mmucr1_q(pos_tlbi_rej)) ); +local_reject_d <= (global_barrier_q and (0 to thdid_width-1 => inval_snoop_local_reject)); +an_ac_back_inv_d(0) <= an_ac_back_inv; +an_ac_back_inv_d(1) <= an_ac_back_inv_target; +an_ac_back_inv_d(2) <= an_ac_back_inv_q(0) when inval_snoop_forme='0' + else '0' when inv_seq_snoop_done='1' + else an_ac_back_inv_q(2); +an_ac_back_inv_d(3) <= an_ac_back_inv_q(1) when inval_snoop_forme='0' + else '0' when inv_seq_snoop_done='1' + else an_ac_back_inv_q(3); +an_ac_back_inv_d(4) <= an_ac_back_inv_lbit when inval_snoop_forme='0' + else an_ac_back_inv_q(4); +an_ac_back_inv_d(5) <= an_ac_back_inv_gs when inval_snoop_forme='0' + else an_ac_back_inv_q(5); +an_ac_back_inv_d(6) <= an_ac_back_inv_ind when inval_snoop_forme='0' + else an_ac_back_inv_q(6); +an_ac_back_inv_d(7) <= an_ac_back_inv_local when inval_snoop_forme='0' + else an_ac_back_inv_q(7); +an_ac_back_inv_d(8) <= ( an_ac_back_inv_q(2) and an_ac_back_inv_q(3) and not Eq(an_ac_back_inv_lpar_id_q,lpidr_q) + and (Eq(xu_mm_ccr2_notlb_q(0),ERAT_Mode_Value) or mmucr1_q(pos_tlbi_rej)) ) + or ( an_ac_back_inv_q(2) and an_ac_back_inv_q(3) and power_managed_q(0) and power_managed_q(1) ); +an_ac_back_inv_addr_d <= an_ac_back_inv_addr when inval_snoop_forme='0' + else an_ac_back_inv_addr_q; +an_ac_back_inv_lpar_id_d <= an_ac_back_inv_lpar_id when inval_snoop_forme='0' + else an_ac_back_inv_lpar_id_q; +ac_an_back_inv_reject <= an_ac_back_inv_q(8); +tlbwe_back_inv_d(0 to thdid_width-1) <= tlbwe_back_inv_thdid when tlbwe_back_inv_q(thdid_width)='0' + else (others => '0') when (tlbwe_back_inv_q(thdid_width)='1' and tlbwe_back_inv_q(thdid_width+1)='0' and tlb_tag5_write='0') + else (others => '0') when inv_seq_tlbwe_snoop_done='1' + else tlbwe_back_inv_q(0 to thdid_width-1); +tlbwe_back_inv_d(thdid_width) <= tlbwe_back_inv_valid when tlbwe_back_inv_q(thdid_width)='0' + else '0' when (tlbwe_back_inv_q(thdid_width)='1' and tlbwe_back_inv_q(thdid_width+1)='0' and tlb_tag5_write='0') + else '0' when inv_seq_tlbwe_snoop_done='1' + else tlbwe_back_inv_q(thdid_width); +tlbwe_back_inv_d(thdid_width+1) <= (tlbwe_back_inv_q(thdid_width) and tlb_tag5_write) when tlbwe_back_inv_q(thdid_width+1)='0' + else '0' when inv_seq_tlbwe_snoop_done='1' + else tlbwe_back_inv_q(thdid_width+1); +tlbwe_back_inv_addr_d <= tlbwe_back_inv_addr when tlbwe_back_inv_q(thdid_width)='0' + else tlbwe_back_inv_addr_q; +tlbwe_back_inv_attr_d <= tlbwe_back_inv_attr when tlbwe_back_inv_q(thdid_width)='0' + else tlbwe_back_inv_attr_q; +tlbwe_back_inv_pending <= or_reduce(tlbwe_back_inv_q(thdid_width to thdid_width+1)); +htw_lsu_req_taken <= htw_lsu_req_taken_sig; +lsu_tokens_d <= "01" when (xu_mm_lsu_token='1' and lsu_tokens_q="00") + else "10" when (xu_mm_lsu_token='1' and lsu_tokens_q="01") + else "11" when (xu_mm_lsu_token='1' and lsu_tokens_q="10") + else "10" when (lsu_req_q/="0000" and lsu_tokens_q="11") + else "01" when (lsu_req_q/="0000" and lsu_tokens_q="10") + else "00" when (lsu_req_q/="0000" and lsu_tokens_q="01") + else lsu_tokens_q; +lsu_req_d <= "0000" when lsu_tokens_q="00" + else "1000" when inv_seq_tlbi_complete='1' + else htw_lsu_thdid when inv_seq_htw_load='1' + else ex6_valid_q when inv_seq_tlbi_load='1' + else (others => '0'); +lsu_ttype_d <= "01" when inv_seq_tlbi_complete='1' + else htw_lsu_ttype when inv_seq_htw_load='1' + else (others => '0'); +lsu_wimge_d <= htw_lsu_wimge when inv_seq_htw_load='1' + else (others => '0'); +lsu_ubits_d <= htw_lsu_u when inv_seq_htw_load='1' + else (others => '0'); +lsu_addr_d(64-real_addr_width to 64-real_addr_width+4) <= + htw_lsu_addr(64-real_addr_width to 64-real_addr_width+4) when inv_seq_htw_load='1' + else ex6_pid_q(pid_width-13 to pid_width-9) when inv_seq_tlbi_load='1' + else lsu_addr_q(64-real_addr_width to 64-real_addr_width+4); +lsu_addr_d(64-real_addr_width+5 to 33) <= + htw_lsu_addr(64-real_addr_width+5 to 33) when inv_seq_htw_load='1' + else ex3_ea_q(64-real_addr_width+5 to 33) when inv_seq_tlbi_load='1' + else lsu_addr_q(64-real_addr_width+5 to 33); +lsu_addr_d(34 to 35) <= + htw_lsu_addr(34 to 35) when inv_seq_htw_load='1' + else ex3_ea_q(13 to 14) when (inv_seq_tlbi_load='1' and mmucr1(pos_tlbi_msb)='1' and ex6_size_q=TLB_PgSize_1GB) + else ex3_ea_q(17 to 18) when (inv_seq_tlbi_load='1' and mmucr1(pos_tlbi_msb)='0' and ex6_size_q=TLB_PgSize_1GB) + else ex3_ea_q(34 to 35) when inv_seq_tlbi_load='1' + else lsu_addr_q(34 to 35); +lsu_addr_d(36 to 39) <= + htw_lsu_addr(36 to 39) when inv_seq_htw_load='1' + else ex3_ea_q(15 to 18) when (inv_seq_tlbi_load='1' and mmucr1(pos_tlbi_msb)='1' and + (ex6_size_q=TLB_PgSize_1GB or ex6_size_q=TLB_PgSize_256MB)) + else ex3_ea_q(19 to 22) when (inv_seq_tlbi_load='1' and mmucr1(pos_tlbi_msb)='0' and + (ex6_size_q=TLB_PgSize_1GB or ex6_size_q=TLB_PgSize_256MB)) + else ex3_ea_q(36 to 39) when inv_seq_tlbi_load='1' + else lsu_addr_q(36 to 39); +lsu_addr_d(40 to 41) <= + htw_lsu_addr(40 to 41) when inv_seq_htw_load='1' + else ex3_ea_q(19 to 20) when (inv_seq_tlbi_load='1' and mmucr1(pos_tlbi_msb)='1' and + (ex6_size_q=TLB_PgSize_1GB or ex6_size_q=TLB_PgSize_256MB or ex6_size_q=TLB_PgSize_16MB)) + else ex3_ea_q(23 to 24) when (inv_seq_tlbi_load='1' and mmucr1(pos_tlbi_msb)='0' and + (ex6_size_q=TLB_PgSize_1GB or ex6_size_q=TLB_PgSize_256MB or ex6_size_q=TLB_PgSize_16MB)) + else ex3_ea_q(40 to 41) when inv_seq_tlbi_load='1' + else lsu_addr_q(40 to 41); +lsu_addr_d(42 to 43) <= + htw_lsu_addr(42 to 43) when inv_seq_htw_load='1' + else ex6_isel_q(1 to 2) when (ex6_isel_q(0)='1' and inv_seq_tlbi_load='1') + else ex3_ea_q(21 to 22) when (ex6_isel_q(0)='0' and inv_seq_tlbi_load='1' and mmucr1(pos_tlbi_msb)='1' and + (ex6_size_q=TLB_PgSize_1GB or ex6_size_q=TLB_PgSize_256MB or ex6_size_q=TLB_PgSize_16MB)) + else ex3_ea_q(25 to 26) when (ex6_isel_q(0)='0' and inv_seq_tlbi_load='1' and mmucr1(pos_tlbi_msb)='0' and + (ex6_size_q=TLB_PgSize_1GB or ex6_size_q=TLB_PgSize_256MB or ex6_size_q=TLB_PgSize_16MB)) + else ex3_ea_q(42 to 43) when (ex6_isel_q(0)='0' and inv_seq_tlbi_load='1') + else lsu_addr_q(42 to 43); +lsu_addr_d(44 to 47) <= + htw_lsu_addr(44 to 47) when inv_seq_htw_load='1' + else ex3_ea_q(23 to 26) when (inv_seq_tlbi_load='1' and mmucr1(pos_tlbi_msb)='1' and + (ex6_size_q=TLB_PgSize_1GB or ex6_size_q=TLB_PgSize_256MB or ex6_size_q=TLB_PgSize_16MB or ex6_size_q=TLB_PgSize_1MB)) + else ex3_ea_q(27 to 30) when (inv_seq_tlbi_load='1' and mmucr1(pos_tlbi_msb)='0' and + (ex6_size_q=TLB_PgSize_1GB or ex6_size_q=TLB_PgSize_256MB or ex6_size_q=TLB_PgSize_16MB or ex6_size_q=TLB_PgSize_1MB)) + else ex3_ea_q(44 to 47) when inv_seq_tlbi_load='1' + else lsu_addr_q(44 to 47); +lsu_addr_d(48 to 51) <= htw_lsu_addr(48 to 51) when inv_seq_htw_load='1' + else ex6_size_q(0 to 3) when inv_seq_tlbi_load='1' and ex6_size_large='1' + else ex3_ea_q(48 to 51) when inv_seq_tlbi_load='1' and ex6_size_large='0' + else lsu_addr_q(48 to 51); +lsu_addr_d(52) <= htw_lsu_addr(52) when inv_seq_htw_load='1' + else ex6_ts_q when inv_seq_tlbi_load='1' + else lsu_addr_q(52); +lsu_addr_d(53) <= htw_lsu_addr(53) when inv_seq_htw_load='1' + else ex6_pid_q(0) when inv_seq_tlbi_load='1' + else lsu_addr_q(53); +lsu_addr_d(54 to 55) <= htw_lsu_addr(54 to 55) when inv_seq_htw_load='1' + else ex6_isel_q(1 to 2) when (ex6_isel_q(0)='0' and inv_seq_tlbi_load='1') + else "10" when (ex6_isel_q(0)='1' and inv_seq_tlbi_load='1') + else lsu_addr_q(54 to 55); +lsu_addr_d(56 to 63) <= htw_lsu_addr(56 to 63) when inv_seq_htw_load='1' + else ex6_pid_q(pid_width-8 to pid_width-1) when inv_seq_tlbi_load='1' + else lsu_addr_q(56 to 63); +lsu_lpid_d <= ex6_lpid_q when inv_seq_tlbi_load='1' + else lsu_lpid_q; +lsu_ind_d <= ex6_ind_q when inv_seq_tlbi_load='1' + else lsu_ind_q; +lsu_gs_d <= ex6_gs_q when inv_seq_tlbi_load='1' + else lsu_gs_q; +lsu_lbit_d <= '1' when (inv_seq_tlbi_load='1' and ex6_size_large='1') + else '0' when (inv_seq_tlbi_load='1' and ex6_size_large='0') + else lsu_lbit_q; +mm_xu_lsu_req <= lsu_req_q; +mm_xu_lsu_ttype <= lsu_ttype_q; +mm_xu_lsu_wimge <= lsu_wimge_q; +mm_xu_lsu_u <= lsu_ubits_q; +mm_xu_lsu_addr <= lsu_addr_q; +mm_xu_lsu_lpid <= lsu_lpid_q; +mm_xu_lsu_ind <= lsu_ind_q; +mm_xu_lsu_gs <= lsu_gs_q; +mm_xu_lsu_lbit <= lsu_lbit_q; +snoop_valid_d(0) <= inv_seq_ierat_snoop_val; +snoop_valid_d(1) <= inv_seq_derat_snoop_val; +snoop_valid_d(2) <= inv_seq_tlb_snoop_val; +snoop_coming_d(0) <= + inv_seq_tlb0fi_inprogress or + inv_seq_tlbwe_inprogress or + inv_seq_local_inprogress or inv_seq_snoop_inprogress; +snoop_coming_d(1) <= snoop_coming_d(0); +snoop_coming_d(2) <= snoop_coming_d(0); +snoop_coming_d(3) <= snoop_coming_d(0) or mmucr2_act_override; +snoop_coming_d(4) <= snoop_coming_d(0) or mmucr2_act_override; +gen64_snoop_attr: if real_addr_width > 32 generate +ex6_tid_nz <= or_reduce(ex6_pid_q(0 to pid_width-1)); +back_inv_tid_nz <= or_reduce(an_ac_back_inv_addr_q(53) & an_ac_back_inv_addr_q(22 to 26) & an_ac_back_inv_addr_q(56 to 63)); +tlbwe_back_inv_tid_nz <= or_reduce(tlbwe_back_inv_attr_q(20 to 25) & tlbwe_back_inv_attr_q(6 to 13)); +snoop_attr_d(0) <= not inv_seq_snoop_inprogress_q(0); +snoop_attr_d(1 to 3) <= '1' & an_ac_back_inv_addr_q(42 to 43) + when inv_seq_snoop_inprogress_q(0)='1' and an_ac_back_inv_addr_q(54 to 55)="10" + else '0' & an_ac_back_inv_addr_q(54 to 55) + when inv_seq_snoop_inprogress_q(0)='1' and an_ac_back_inv_addr_q(54 to 55)/="10" + else "011" when inv_seq_tlbwe_inprogress_q(0)='1' + else (ex6_isel_q(0 to 2) and not(0 to 2 => inv_seq_tlb0fi_inprogress_q(0))); +snoop_attr_d(4 to 13) <= an_ac_back_inv_q(5) & an_ac_back_inv_addr_q(52) & an_ac_back_inv_addr_q(56 to 63) + when inv_seq_snoop_inprogress_q(0)='1' + else tlbwe_back_inv_attr_q(4 to 13) when inv_seq_tlbwe_inprogress_q(0)='1' + else ex6_gs_q & ex6_ts_q & ex6_pid_q(pid_width-8 to pid_width-1); +snoop_attr_d(14 to 17) <= "0001" when inv_seq_snoop_inprogress_q(0)='1' and an_ac_back_inv_q(4)='0' + else an_ac_back_inv_addr_q(48 to 51) when inv_seq_snoop_inprogress_q(0)='1' and an_ac_back_inv_q(4)='1' + else tlbwe_back_inv_attr_q(14 to 17) when inv_seq_tlbwe_inprogress_q(0)='1' + else ex6_size_q(0 to 3); +snoop_attr_d(18) <= not inv_seq_tlbwe_inprogress_q(0) or not tlbwe_back_inv_attr_q(18); +snoop_attr_d(19) <= back_inv_tid_nz when inv_seq_snoop_inprogress_q(0)='1' + else tlbwe_back_inv_tid_nz when inv_seq_tlbwe_inprogress_q(0)='1' + else ex6_tid_nz; +snoop_attr_tlb_spec_d(18) <= '0'; +snoop_attr_tlb_spec_d(19) <= inv_seq_tlb0fi_inprogress_q(0); +snoop_attr_d(20 to 25) <= an_ac_back_inv_addr_q(53) & an_ac_back_inv_addr_q(22 to 26) when inv_seq_snoop_inprogress_q(0)='1' + else tlbwe_back_inv_attr_q(20 to 25) when inv_seq_tlbwe_inprogress_q(0)='1' + else ex6_pid_q(pid_width-14 to pid_width-9); +snoop_attr_d(26 to 33) <= an_ac_back_inv_lpar_id_q when inv_seq_snoop_inprogress_q(0)='1' + else tlbwe_back_inv_attr_q(26 to 33) when inv_seq_tlbwe_inprogress_q(0)='1' + else lpidr_q when inv_seq_tlb0fi_inprogress_q(0)='1' + else ex6_lpid_q; +snoop_attr_d(34) <= an_ac_back_inv_q(6) when inv_seq_snoop_inprogress_q(0)='1' + else tlbwe_back_inv_attr_q(34) when inv_seq_tlbwe_inprogress_q(0)='1' + else ex6_ind_q; +snoop_attr_clone_d(0) <= not inv_seq_snoop_inprogress_q(1); +snoop_attr_clone_d(1 to 3) <= '1' & an_ac_back_inv_addr_q(42 to 43) + when inv_seq_snoop_inprogress_q(1)='1' and an_ac_back_inv_addr_q(54 to 55)="10" + else '0' & an_ac_back_inv_addr_q(54 to 55) + when inv_seq_snoop_inprogress_q(1)='1' and an_ac_back_inv_addr_q(54 to 55)/="10" + else "011" when inv_seq_tlbwe_inprogress_q(1)='1' + else (ex6_isel_q(0 to 2) and not(0 to 2 => inv_seq_tlb0fi_inprogress_q(1))); +snoop_attr_clone_d(4 to 13) <= an_ac_back_inv_q(5) & an_ac_back_inv_addr_q(52) & an_ac_back_inv_addr_q(56 to 63) + when inv_seq_snoop_inprogress_q(1)='1' + else tlbwe_back_inv_attr_q(4 to 13) when inv_seq_tlbwe_inprogress_q(1)='1' + else ex6_gs_q & ex6_ts_q & ex6_pid_q(pid_width-8 to pid_width-1); +snoop_attr_clone_d(14 to 17) <= "0001" when inv_seq_snoop_inprogress_q(1)='1' and an_ac_back_inv_q(4)='0' + else an_ac_back_inv_addr_q(48 to 51) when inv_seq_snoop_inprogress_q(1)='1' and an_ac_back_inv_q(4)='1' + else tlbwe_back_inv_attr_q(14 to 17) when inv_seq_tlbwe_inprogress_q(1)='1' + else ex6_size_q(0 to 3); +snoop_attr_clone_d(18) <= not inv_seq_tlbwe_inprogress_q(1) or not tlbwe_back_inv_attr_q(18); +snoop_attr_clone_d(19) <= back_inv_tid_nz when inv_seq_snoop_inprogress_q(1)='1' + else tlbwe_back_inv_tid_nz when inv_seq_tlbwe_inprogress_q(1)='1' + else ex6_tid_nz; +snoop_attr_clone_d(20 to 25) <= an_ac_back_inv_addr_q(53) & an_ac_back_inv_addr_q(22 to 26) when inv_seq_snoop_inprogress_q(1)='1' + else tlbwe_back_inv_attr_q(20 to 25) when inv_seq_tlbwe_inprogress_q(1)='1' + else ex6_pid_q(pid_width-14 to pid_width-9); +end generate gen64_snoop_attr; +gen32_snoop_attr: if real_addr_width < 33 generate +ex6_tid_nz <= or_reduce(ex6_pid_q(0 to pid_width-1)); +back_inv_tid_nz <= or_reduce(an_ac_back_inv_addr_q(56 to 63)); +tlbwe_back_inv_tid_nz <= or_reduce(tlbwe_back_inv_attr_q(20 to 25) & tlbwe_back_inv_attr_q(6 to 13)); +snoop_attr_d(0) <= not inv_seq_snoop_inprogress_q(0); +snoop_attr_d(1 to 3) <= '1' & an_ac_back_inv_addr_q(42 to 43) + when inv_seq_snoop_inprogress_q(0)='1' and an_ac_back_inv_addr_q(54 to 55)="10" + else '0' & an_ac_back_inv_addr_q(54 to 55) + when inv_seq_snoop_inprogress_q(0)='1' and an_ac_back_inv_addr_q(54 to 55)/="10" + else "011" when inv_seq_tlbwe_inprogress_q(0)='1' + else ex6_isel_q(0 to 2); +snoop_attr_d(4 to 13) <= an_ac_back_inv_q(5) & an_ac_back_inv_addr_q(52) & an_ac_back_inv_addr_q(56 to 63) + when inv_seq_snoop_inprogress_q(0)='1' + else tlbwe_back_inv_attr_q(4 to 13) when inv_seq_tlbwe_inprogress_q(0)='1' + else ex6_gs_q & ex6_ts_q & ex6_pid_q(pid_width-8 to pid_width-1); +snoop_attr_d(14 to 17) <= "0001" when inv_seq_snoop_inprogress_q(0)='1' and an_ac_back_inv_q(4)='0' + else an_ac_back_inv_addr_q(48 to 51) when inv_seq_snoop_inprogress_q(0)='1' and an_ac_back_inv_q(4)='1' + else tlbwe_back_inv_attr_q(14 to 17) when inv_seq_tlbwe_inprogress_q(0)='1' + else ex6_size_q(0 to 3); +snoop_attr_d(18) <= not inv_seq_tlbwe_inprogress_q(0) or not tlbwe_back_inv_attr_q(18); +snoop_attr_d(19) <= back_inv_tid_nz when inv_seq_snoop_inprogress_q(0)='1' + else tlbwe_back_inv_tid_nz when inv_seq_tlbwe_inprogress_q(0)='1' + else ex6_tid_nz; +snoop_attr_tlb_spec_d(18) <= '0'; +snoop_attr_tlb_spec_d(19) <= inv_seq_tlb0fi_inprogress_q(0); +snoop_attr_d(20 to 25) <= (others => '0') when inv_seq_snoop_inprogress_q(0)='1' + else tlbwe_back_inv_attr_q(20 to 25) when inv_seq_tlbwe_inprogress_q(0)='1' + else ex6_pid_q(pid_width-14 to pid_width-9); +snoop_attr_d(26 to 33) <= an_ac_back_inv_lpar_id_q when inv_seq_snoop_inprogress_q(0)='1' + else tlbwe_back_inv_attr_q(26 to 33) when inv_seq_tlbwe_inprogress_q(0)='1' + else lpidr_q when inv_seq_tlb0fi_inprogress_q(0)='1' + else ex6_lpid_q; +snoop_attr_d(34) <= an_ac_back_inv_q(6) when inv_seq_snoop_inprogress_q(0)='1' + else tlbwe_back_inv_attr_q(34) when inv_seq_tlbwe_inprogress_q(0)='1' + else ex6_ind_q; +snoop_attr_clone_d(0) <= not inv_seq_snoop_inprogress_q(1); +snoop_attr_clone_d(1 to 3) <= '1' & an_ac_back_inv_addr_q(42 to 43) + when inv_seq_snoop_inprogress_q(1)='1' and an_ac_back_inv_addr_q(54 to 55)="10" + else '0' & an_ac_back_inv_addr_q(54 to 55) + when inv_seq_snoop_inprogress_q(1)='1' and an_ac_back_inv_addr_q(54 to 55)/="10" + else "011" when inv_seq_tlbwe_inprogress_q(1)='1' + else ex6_isel_q(0 to 2); +snoop_attr_clone_d(4 to 13) <= an_ac_back_inv_q(5) & an_ac_back_inv_addr_q(52) & an_ac_back_inv_addr_q(56 to 63) + when inv_seq_snoop_inprogress_q(1)='1' + else tlbwe_back_inv_attr_q(4 to 13) when inv_seq_tlbwe_inprogress_q(1)='1' + else ex6_gs_q & ex6_ts_q & ex6_pid_q(pid_width-8 to pid_width-1); +snoop_attr_clone_d(14 to 17) <= "0001" when inv_seq_snoop_inprogress_q(1)='1' and an_ac_back_inv_q(4)='0' + else an_ac_back_inv_addr_q(48 to 51) when inv_seq_snoop_inprogress_q(1)='1' and an_ac_back_inv_q(4)='1' + else tlbwe_back_inv_attr_q(14 to 17) when inv_seq_tlbwe_inprogress_q(1)='1' + else ex6_size_q(0 to 3); +snoop_attr_clone_d(18) <= not inv_seq_tlbwe_inprogress_q(1) or not tlbwe_back_inv_attr_q(18); +snoop_attr_clone_d(19) <= back_inv_tid_nz when inv_seq_snoop_inprogress_q(1)='1' + else tlbwe_back_inv_tid_nz when inv_seq_tlbwe_inprogress_q(1)='1' + else ex6_tid_nz; +snoop_attr_clone_d(20 to 25) <= (others => '0') when inv_seq_snoop_inprogress_q(1)='1' + else tlbwe_back_inv_attr_q(20 to 25) when inv_seq_tlbwe_inprogress_q(1)='1' + else ex6_pid_q(pid_width-14 to pid_width-9); +end generate gen32_snoop_attr; +gen_rs_gte_epn_snoop_vpn: if (rs_data_width > epn_width-1) and (epn_width > real_addr_width) generate +snoop_vpn_d(52-epn_width to 12) <= (others => '0') when inv_seq_snoop_inprogress_q(0)='1' + else tlbwe_back_inv_addr_q(0 to 12) when inv_seq_tlbwe_inprogress_q(0)='1' + else ex3_ea_q(52-epn_width to 12); +snoop_vpn_d(13 to 14) <= an_ac_back_inv_addr_q(34 to 35) when (inv_seq_snoop_inprogress_q(0)='1' and an_ac_back_inv_q(4)='1' and + mmucr1_q(pos_tlbi_msb)='1' and an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_1GB) + else (others => '0') when inv_seq_snoop_inprogress_q(0)='1' + else tlbwe_back_inv_addr_q(13 to 14) when inv_seq_tlbwe_inprogress_q(0)='1' + else ex3_ea_q(13 to 14); +snoop_vpn_d(15 to 16) <= an_ac_back_inv_addr_q(36 to 37) when (inv_seq_snoop_inprogress_q(0)='1' and an_ac_back_inv_q(4)='1' and + mmucr1_q(pos_tlbi_msb)='1' and (an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_1GB or + an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_256MB)) + else (others => '0') when inv_seq_snoop_inprogress_q(0)='1' + else tlbwe_back_inv_addr_q(15 to 16) when inv_seq_tlbwe_inprogress_q(0)='1' + else ex3_ea_q(15 to 16); +snoop_vpn_d(17 to 18) <= an_ac_back_inv_addr_q(38 to 39) when (inv_seq_snoop_inprogress_q(0)='1' and an_ac_back_inv_q(4)='1' and + mmucr1_q(pos_tlbi_msb)='1' and (an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_1GB or + an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_256MB)) + else an_ac_back_inv_addr_q(34 to 35) when (inv_seq_snoop_inprogress_q(0)='1'and an_ac_back_inv_q(4)='1' and + mmucr1_q(pos_tlbi_msb)='0' and an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_1GB ) + else (others => '0') when inv_seq_snoop_inprogress_q(0)='1' + else tlbwe_back_inv_addr_q(17 to 18) when inv_seq_tlbwe_inprogress_q(0)='1' + else ex3_ea_q(17 to 18); +snoop_vpn_d(19 to 22) <= an_ac_back_inv_addr_q(40 to 43) when (inv_seq_snoop_inprogress_q(0)='1' and an_ac_back_inv_q(4)='1' and + mmucr1_q(pos_tlbi_msb)='1' and (an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_1GB or + an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_256MB or an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_16MB)) + else an_ac_back_inv_addr_q(36 to 39) when (inv_seq_snoop_inprogress_q(0)='1'and an_ac_back_inv_q(4)='1' and + mmucr1_q(pos_tlbi_msb)='0' and (an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_1GB or + an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_256MB)) + else (others => '0') when inv_seq_snoop_inprogress_q(0)='1' + else tlbwe_back_inv_addr_q(19 to 22) when inv_seq_tlbwe_inprogress_q(0)='1' + else ex3_ea_q(19 to 22); +snoop_vpn_d(23 to 26) <= an_ac_back_inv_addr_q(44 to 47) when (inv_seq_snoop_inprogress_q(0)='1' and an_ac_back_inv_q(4)='1' and + mmucr1_q(pos_tlbi_msb)='1' and (an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_1GB or + an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_256MB or an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_16MB or + an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_1MB)) + else an_ac_back_inv_addr_q(40 to 43) when (inv_seq_snoop_inprogress_q(0)='1' and an_ac_back_inv_q(4)='1' and + mmucr1_q(pos_tlbi_msb)='0' and (an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_1GB or + an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_256MB or an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_16MB)) + else (others => '0') when inv_seq_snoop_inprogress_q(0)='1' + else tlbwe_back_inv_addr_q(23 to 26) when inv_seq_tlbwe_inprogress_q(0)='1' + else ex3_ea_q(23 to 26); +snoop_vpn_d(27 to 30) <= an_ac_back_inv_addr_q(44 to 47) when (inv_seq_snoop_inprogress_q(0)='1' and an_ac_back_inv_q(4)='1' and + mmucr1_q(pos_tlbi_msb)='0' and (an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_1GB or + an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_256MB or an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_16MB or + an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_1MB)) + else an_ac_back_inv_addr_q(27 to 30) when inv_seq_snoop_inprogress_q(0)='1' + else tlbwe_back_inv_addr_q(27 to 30) when inv_seq_tlbwe_inprogress_q(0)='1' + else ex3_ea_q(27 to 30); +snoop_vpn_d(31) <= an_ac_back_inv_addr_q(31) when inv_seq_snoop_inprogress_q(0)='1' + else tlbwe_back_inv_addr_q(31) when inv_seq_tlbwe_inprogress_q(0)='1' + else ex3_ea_q(31); +snoop_vpn_clone_d(52-epn_width to 12) <= (others => '0') when inv_seq_snoop_inprogress_q(1)='1' + else tlbwe_back_inv_addr_q(0 to 12) when inv_seq_tlbwe_inprogress_q(1)='1' + else ex3_ea_q(52-epn_width to 12); +snoop_vpn_clone_d(13 to 14) <= an_ac_back_inv_addr_q(34 to 35) when (inv_seq_snoop_inprogress_q(1)='1' and an_ac_back_inv_q(4)='1' and + mmucr1_q(pos_tlbi_msb)='1' and an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_1GB) + else (others => '0') when inv_seq_snoop_inprogress_q(1)='1' + else tlbwe_back_inv_addr_q(13 to 14) when inv_seq_tlbwe_inprogress_q(1)='1' + else ex3_ea_q(13 to 14); +snoop_vpn_clone_d(15 to 16) <= an_ac_back_inv_addr_q(36 to 37) when (inv_seq_snoop_inprogress_q(1)='1' and an_ac_back_inv_q(4)='1' and + mmucr1_q(pos_tlbi_msb)='1' and (an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_1GB or + an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_256MB)) + else (others => '0') when inv_seq_snoop_inprogress_q(1)='1' + else tlbwe_back_inv_addr_q(15 to 16) when inv_seq_tlbwe_inprogress_q(1)='1' + else ex3_ea_q(15 to 16); +snoop_vpn_clone_d(17 to 18) <= an_ac_back_inv_addr_q(38 to 39) when (inv_seq_snoop_inprogress_q(1)='1' and an_ac_back_inv_q(4)='1' and + mmucr1_q(pos_tlbi_msb)='1' and (an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_1GB or + an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_256MB)) + else an_ac_back_inv_addr_q(34 to 35) when (inv_seq_snoop_inprogress_q(1)='1'and an_ac_back_inv_q(4)='1' and + mmucr1_q(pos_tlbi_msb)='0' and an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_1GB ) + else (others => '0') when inv_seq_snoop_inprogress_q(1)='1' + else tlbwe_back_inv_addr_q(17 to 18) when inv_seq_tlbwe_inprogress_q(1)='1' + else ex3_ea_q(17 to 18); +snoop_vpn_clone_d(19 to 22) <= an_ac_back_inv_addr_q(40 to 43) when (inv_seq_snoop_inprogress_q(1)='1' and an_ac_back_inv_q(4)='1' and + mmucr1_q(pos_tlbi_msb)='1' and (an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_1GB or + an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_256MB or an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_16MB)) + else an_ac_back_inv_addr_q(36 to 39) when (inv_seq_snoop_inprogress_q(1)='1'and an_ac_back_inv_q(4)='1' and + mmucr1_q(pos_tlbi_msb)='0' and (an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_1GB or + an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_256MB)) + else (others => '0') when inv_seq_snoop_inprogress_q(1)='1' + else tlbwe_back_inv_addr_q(19 to 22) when inv_seq_tlbwe_inprogress_q(1)='1' + else ex3_ea_q(19 to 22); +snoop_vpn_clone_d(23 to 26) <= an_ac_back_inv_addr_q(44 to 47) when (inv_seq_snoop_inprogress_q(1)='1' and an_ac_back_inv_q(4)='1' and + mmucr1_q(pos_tlbi_msb)='1' and (an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_1GB or + an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_256MB or an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_16MB or + an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_1MB)) + else an_ac_back_inv_addr_q(40 to 43) when (inv_seq_snoop_inprogress_q(1)='1' and an_ac_back_inv_q(4)='1' and + mmucr1_q(pos_tlbi_msb)='0' and (an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_1GB or + an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_256MB or an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_16MB)) + else (others => '0') when inv_seq_snoop_inprogress_q(1)='1' + else tlbwe_back_inv_addr_q(23 to 26) when inv_seq_tlbwe_inprogress_q(1)='1' + else ex3_ea_q(23 to 26); +snoop_vpn_clone_d(27 to 30) <= an_ac_back_inv_addr_q(44 to 47) when (inv_seq_snoop_inprogress_q(1)='1' and an_ac_back_inv_q(4)='1' and + mmucr1_q(pos_tlbi_msb)='0' and (an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_1GB or + an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_256MB or an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_16MB or + an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_1MB)) + else an_ac_back_inv_addr_q(27 to 30) when inv_seq_snoop_inprogress_q(1)='1' + else tlbwe_back_inv_addr_q(27 to 30) when inv_seq_tlbwe_inprogress_q(1)='1' + else ex3_ea_q(27 to 30); +snoop_vpn_clone_d(31) <= an_ac_back_inv_addr_q(31) when inv_seq_snoop_inprogress_q(1)='1' + else tlbwe_back_inv_addr_q(31) when inv_seq_tlbwe_inprogress_q(1)='1' + else ex3_ea_q(31); +end generate gen_rs_gte_epn_snoop_vpn; +gen_rs_gte_ra_snoop_vpn: if (rs_data_width > real_addr_width-1) generate +snoop_vpn_d(32 to 51) <= an_ac_back_inv_addr_q(32 to 51) when inv_seq_snoop_inprogress_q(0)='1' + else tlbwe_back_inv_addr_q(32 to 51) when inv_seq_tlbwe_inprogress_q(0)='1' + else ex3_ea_q(32 to 51); +snoop_vpn_clone_d(32 to 51) <= an_ac_back_inv_addr_q(32 to 51) when inv_seq_snoop_inprogress_q(1)='1' + else tlbwe_back_inv_addr_q(32 to 51) when inv_seq_tlbwe_inprogress_q(1)='1' + else ex3_ea_q(32 to 51); +end generate gen_rs_gte_ra_snoop_vpn; +gen_ra_gt_rs_snoop_vpn: if rs_data_width < real_addr_width generate +snoop_vpn_d(64-real_addr_width to 51) <= an_ac_back_inv_addr_q(64-real_addr_width to 51) when inv_seq_snoop_inprogress_q(0)='1' + else tlbwe_back_inv_addr_q(64-real_addr_width to 51) when inv_seq_tlbwe_inprogress_q(0)='1' + else (64-real_addr_width to 63-rs_data_width => '0') & ex3_ea_q(64-rs_data_width to 51); +snoop_vpn_clone_d(64-real_addr_width to 51) <= an_ac_back_inv_addr_q(64-real_addr_width to 51) when inv_seq_snoop_inprogress_q(1)='1' + else tlbwe_back_inv_addr_q(64-real_addr_width to 51) when inv_seq_tlbwe_inprogress_q(1)='1' + else (64-real_addr_width to 63-rs_data_width => '0') & ex3_ea_q(64-rs_data_width to 51); +end generate gen_ra_gt_rs_snoop_vpn; +gen_epn_gt_rs_snoop_vpn: if (epn_width > real_addr_width) and (rs_data_width < epn_width) generate +snoop_vpn_d(52-epn_width to 63-real_addr_width) <= (others => '0'); +snoop_vpn_clone_d(52-epn_width to 63-real_addr_width) <= (others => '0'); +end generate gen_epn_gt_rs_snoop_vpn; +snoop_ack_d(0) <= iu_mm_ierat_snoop_ack when snoop_ack_q(0)='0' + else '0' when (inv_seq_snoop_done='1' or inv_seq_local_done='1' or inv_seq_tlb0fi_done='1' or inv_seq_tlbwe_snoop_done='1') + else snoop_ack_q(0); +snoop_ack_d(1) <= xu_mm_derat_snoop_ack when snoop_ack_q(1)='0' + else '0' when (inv_seq_snoop_done='1' or inv_seq_local_done='1' or inv_seq_tlb0fi_done='1' or inv_seq_tlbwe_snoop_done='1') + else snoop_ack_q(1); +snoop_ack_d(2) <= tlb_snoop_ack when snoop_ack_q(2)='0' + else '0' when (inv_seq_snoop_done='1' or inv_seq_local_done='1' or inv_seq_tlb0fi_done='1' or inv_seq_tlbwe_snoop_done='1') + else snoop_ack_q(2); +mm_iu_ierat_snoop_coming <= snoop_coming_q(0); +mm_iu_ierat_snoop_val <= snoop_valid_q(0); +mm_iu_ierat_snoop_attr <= snoop_attr_q(0 to 25); +mm_iu_ierat_snoop_vpn <= snoop_vpn_q; +mm_xu_derat_snoop_coming <= snoop_coming_q(1); +mm_xu_derat_snoop_val <= snoop_valid_q(1); +mm_xu_derat_snoop_attr <= snoop_attr_clone_q(0 to 25); +mm_xu_derat_snoop_vpn <= snoop_vpn_clone_q; +tlb_snoop_coming <= snoop_coming_q(2); +tlb_snoop_val <= snoop_valid_q(2); +tlb_snoop_attr(0 to 17) <= snoop_attr_q(0 to 17); +tlb_snoop_attr(18 to 19) <= snoop_attr_tlb_spec_q(18 to 19); +tlb_snoop_attr(20 to 34) <= snoop_attr_q(20 to 34); +tlb_snoop_vpn <= snoop_vpn_q; +xu_mm_ccr2_notlb_b <= not xu_mm_ccr2_notlb_q(1 to 12); +xu_mm_epcr_dgtmi <= xu_mm_epcr_dgtmi_q; +inval_perf_tlbilx <= inv_seq_local_done and not inv_seq_tlbi_load; +inval_perf_tlbivax <= inv_seq_local_done and inv_seq_tlbi_load; +inval_perf_tlbivax_snoop <= inv_seq_snoop_done; +inval_perf_tlb_flush <= or_reduce(ex3_flush_req_q); +inval_dbg_seq_q <= inv_seq_q(1 to 5); +inval_dbg_seq_idle <= inv_seq_idle; +inval_dbg_seq_snoop_inprogress <= inv_seq_snoop_inprogress; +inval_dbg_seq_snoop_done <= inv_seq_snoop_done; +inval_dbg_seq_local_done <= inv_seq_local_done; +inval_dbg_seq_tlb0fi_done <= inv_seq_tlb0fi_done; +inval_dbg_seq_tlbwe_snoop_done <= inv_seq_tlbwe_snoop_done; +inval_dbg_ex6_valid <= or_reduce(ex6_valid_q); +inval_dbg_ex6_thdid(0) <= (ex6_valid_q(2) or ex6_valid_q(3)); +inval_dbg_ex6_thdid(1) <= (ex6_valid_q(1) or ex6_valid_q(3)); +inval_dbg_ex6_ttype(0) <= ex6_ttype_q(4) or ex6_ttype_q(5); +inval_dbg_ex6_ttype(1) <= ex6_ttype_q(2) or ex6_ttype_q(3); +inval_dbg_ex6_ttype(2) <= ex6_ttype_q(1) or ex6_ttype_q(3) or ex6_ttype_q(5); +inval_dbg_snoop_forme <= inval_snoop_forme; +inval_dbg_snoop_local_reject <= inval_snoop_local_reject; +inval_dbg_an_ac_back_inv_q <= an_ac_back_inv_q(2 to 8); +inval_dbg_an_ac_back_inv_lpar_id_q <= an_ac_back_inv_lpar_id_q; +inval_dbg_an_ac_back_inv_addr_q <= an_ac_back_inv_addr_q; +inval_dbg_snoop_valid_q <= snoop_valid_q; +inval_dbg_snoop_ack_q <= snoop_ack_q; +inval_dbg_snoop_attr_q <= snoop_attr_q; +inval_dbg_snoop_attr_tlb_spec_q <= snoop_attr_tlb_spec_q; +inval_dbg_snoop_vpn_q <= snoop_vpn_q(17 to 51); +inval_dbg_lsu_tokens_q <= lsu_tokens_q; +unused_dc(0) <= or_reduce(LCB_DELAY_LCLKR_DC(1 TO 4)); +unused_dc(1) <= or_reduce(LCB_MPW1_DC_B(1 TO 4)); +unused_dc(2) <= PC_FUNC_SL_FORCE; +unused_dc(3) <= PC_FUNC_SL_THOLD_0_B; +unused_dc(4) <= TC_SCAN_DIS_DC_B; +unused_dc(5) <= TC_SCAN_DIAG_DC; +unused_dc(6) <= TC_LBIST_EN_DC; +unused_dc(7) <= or_reduce(MMUCR0_0(4 TO 5)); +unused_dc(8) <= or_reduce(MMUCR0_1(4 TO 5)); +unused_dc(9) <= or_reduce(MMUCR0_2(4 TO 5)); +unused_dc(10) <= or_reduce(MMUCR0_3(4 TO 5)); +unused_dc(11) <= mmucr1_q(13) and or_reduce(mmucr1_q(15 to 17)); +unused_dc(12) <= EX5_RS_IS_Q(0); +ex1_valid_latch: tri_rlmreg_p + generic map (width => ex1_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex1_valid_offset to ex1_valid_offset+ex1_valid_q'length-1), + scout => sov(ex1_valid_offset to ex1_valid_offset+ex1_valid_q'length-1), + din => ex1_valid_d(0 to thdid_width-1), + dout => ex1_valid_q(0 to thdid_width-1) ); +ex1_ttype_latch: tri_rlmreg_p + generic map (width => ex1_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex1_ttype_offset to ex1_ttype_offset+ex1_ttype_q'length-1), + scout => sov(ex1_ttype_offset to ex1_ttype_offset+ex1_ttype_q'length-1), + din => ex1_ttype_d, + dout => ex1_ttype_q ); +ex1_state_latch: tri_rlmreg_p + generic map (width => ex1_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex1_state_offset to ex1_state_offset+ex1_state_q'length-1), + scout => sov(ex1_state_offset to ex1_state_offset+ex1_state_q'length-1), + din => ex1_state_d(0 to state_width-1), + dout => ex1_state_q(0 to state_width-1) ); +ex1_t_latch: tri_rlmreg_p + generic map (width => ex1_t_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex1_t_offset to ex1_t_offset+ex1_t_q'length-1), + scout => sov(ex1_t_offset to ex1_t_offset+ex1_t_q'length-1), + din => ex1_t_d(0 to t_width-1), + dout => ex1_t_q(0 to t_width-1) ); +ex2_valid_latch: tri_rlmreg_p + generic map (width => ex2_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex2_valid_offset to ex2_valid_offset+ex2_valid_q'length-1), + scout => sov(ex2_valid_offset to ex2_valid_offset+ex2_valid_q'length-1), + din => ex2_valid_d(0 to thdid_width-1), + dout => ex2_valid_q(0 to thdid_width-1) ); +ex2_ttype_latch: tri_rlmreg_p + generic map (width => ex2_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex2_ttype_offset to ex2_ttype_offset+ex2_ttype_q'length-1), + scout => sov(ex2_ttype_offset to ex2_ttype_offset+ex2_ttype_q'length-1), + din => ex2_ttype_d(0 to ttype_width-1), + dout => ex2_ttype_q(0 to ttype_width-1) ); +ex2_rs_is_latch: tri_rlmreg_p + generic map (width => ex2_rs_is_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex2_rs_is_offset to ex2_rs_is_offset+ex2_rs_is_q'length-1), + scout => sov(ex2_rs_is_offset to ex2_rs_is_offset+ex2_rs_is_q'length-1), + din => ex2_rs_is_d(0 to rs_is_width-1), + dout => ex2_rs_is_q(0 to rs_is_width-1) ); +ex2_state_latch: tri_rlmreg_p + generic map (width => ex2_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex2_state_offset to ex2_state_offset+ex2_state_q'length-1), + scout => sov(ex2_state_offset to ex2_state_offset+ex2_state_q'length-1), + din => ex2_state_d(0 to state_width-1), + dout => ex2_state_q(0 to state_width-1) ); +ex2_t_latch: tri_rlmreg_p + generic map (width => ex2_t_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex2_t_offset to ex2_t_offset+ex2_t_q'length-1), + scout => sov(ex2_t_offset to ex2_t_offset+ex2_t_q'length-1), + din => ex2_t_d(0 to t_width-1), + dout => ex2_t_q(0 to t_width-1) ); +ex3_valid_latch: tri_rlmreg_p + generic map (width => ex3_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex3_valid_offset to ex3_valid_offset+ex3_valid_q'length-1), + scout => sov(ex3_valid_offset to ex3_valid_offset+ex3_valid_q'length-1), + din => ex3_valid_d(0 to thdid_width-1), + dout => ex3_valid_q(0 to thdid_width-1) ); +ex3_ttype_latch: tri_rlmreg_p + generic map (width => ex3_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex3_ttype_offset to ex3_ttype_offset+ex3_ttype_q'length-1), + scout => sov(ex3_ttype_offset to ex3_ttype_offset+ex3_ttype_q'length-1), + din => ex3_ttype_d(0 to ttype_width-1), + dout => ex3_ttype_q(0 to ttype_width-1) ); +ex3_rs_is_latch: tri_rlmreg_p + generic map (width => ex3_rs_is_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex3_rs_is_offset to ex3_rs_is_offset+ex3_rs_is_q'length-1), + scout => sov(ex3_rs_is_offset to ex3_rs_is_offset+ex3_rs_is_q'length-1), + din => ex3_rs_is_d(0 to rs_is_width-1), + dout => ex3_rs_is_q(0 to rs_is_width-1) ); +ex3_state_latch: tri_rlmreg_p + generic map (width => ex3_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex3_state_offset to ex3_state_offset+ex3_state_q'length-1), + scout => sov(ex3_state_offset to ex3_state_offset+ex3_state_q'length-1), + din => ex3_state_d(0 to state_width-1), + dout => ex3_state_q(0 to state_width-1) ); +ex3_t_latch: tri_rlmreg_p + generic map (width => ex3_t_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex3_t_offset to ex3_t_offset+ex3_t_q'length-1), + scout => sov(ex3_t_offset to ex3_t_offset+ex3_t_q'length-1), + din => ex3_t_d(0 to t_width-1), + dout => ex3_t_q(0 to t_width-1) ); +ex3_flush_req_latch: tri_rlmreg_p + generic map (width => ex3_flush_req_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex3_flush_req_offset to ex3_flush_req_offset+ex3_flush_req_q'length-1), + scout => sov(ex3_flush_req_offset to ex3_flush_req_offset+ex3_flush_req_q'length-1), + din => ex3_flush_req_d(0 to thdid_width-1), + dout => ex3_flush_req_q(0 to thdid_width-1) ); +ex3_ea_latch: tri_rlmreg_p + generic map (width => ex3_ea_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex3_ea_offset to ex3_ea_offset+ex3_ea_q'length-1), + scout => sov(ex3_ea_offset to ex3_ea_offset+ex3_ea_q'length-1), + din => ex3_ea_d(64-rs_data_width to 63), + dout => ex3_ea_q(64-rs_data_width to 63) ); +ex4_valid_latch: tri_rlmreg_p + generic map (width => ex4_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex4_valid_offset to ex4_valid_offset+ex4_valid_q'length-1), + scout => sov(ex4_valid_offset to ex4_valid_offset+ex4_valid_q'length-1), + din => ex4_valid_d(0 to thdid_width-1), + dout => ex4_valid_q(0 to thdid_width-1) ); +ex4_ttype_latch: tri_rlmreg_p + generic map (width => ex4_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex4_ttype_offset to ex4_ttype_offset+ex4_ttype_q'length-1), + scout => sov(ex4_ttype_offset to ex4_ttype_offset+ex4_ttype_q'length-1), + din => ex4_ttype_d(0 to ttype_width-1), + dout => ex4_ttype_q(0 to ttype_width-1) ); +ex4_rs_is_latch: tri_rlmreg_p + generic map (width => ex4_rs_is_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex4_rs_is_offset to ex4_rs_is_offset+ex4_rs_is_q'length-1), + scout => sov(ex4_rs_is_offset to ex4_rs_is_offset+ex4_rs_is_q'length-1), + din => ex4_rs_is_d(0 to rs_is_width-1), + dout => ex4_rs_is_q(0 to rs_is_width-1) ); +ex4_state_latch: tri_rlmreg_p + generic map (width => ex4_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex4_state_offset to ex4_state_offset+ex4_state_q'length-1), + scout => sov(ex4_state_offset to ex4_state_offset+ex4_state_q'length-1), + din => ex4_state_d(0 to state_width-1), + dout => ex4_state_q(0 to state_width-1) ); +ex4_t_latch: tri_rlmreg_p + generic map (width => ex4_t_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex4_t_offset to ex4_t_offset+ex4_t_q'length-1), + scout => sov(ex4_t_offset to ex4_t_offset+ex4_t_q'length-1), + din => ex4_t_d(0 to t_width-1), + dout => ex4_t_q(0 to t_width-1) ); +ex5_valid_latch: tri_rlmreg_p + generic map (width => ex5_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex5_valid_offset to ex5_valid_offset+ex5_valid_q'length-1), + scout => sov(ex5_valid_offset to ex5_valid_offset+ex5_valid_q'length-1), + din => ex5_valid_d(0 to thdid_width-1), + dout => ex5_valid_q(0 to thdid_width-1) ); +ex5_ttype_latch: tri_rlmreg_p + generic map (width => ex5_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex5_ttype_offset to ex5_ttype_offset+ex5_ttype_q'length-1), + scout => sov(ex5_ttype_offset to ex5_ttype_offset+ex5_ttype_q'length-1), + din => ex5_ttype_d(0 to ttype_width-1), + dout => ex5_ttype_q(0 to ttype_width-1) ); +ex5_rs_is_latch: tri_rlmreg_p + generic map (width => ex5_rs_is_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex5_rs_is_offset to ex5_rs_is_offset+ex5_rs_is_q'length-1), + scout => sov(ex5_rs_is_offset to ex5_rs_is_offset+ex5_rs_is_q'length-1), + din => ex5_rs_is_d(0 to rs_is_width-1), + dout => ex5_rs_is_q(0 to rs_is_width-1) ); +ex5_state_latch: tri_rlmreg_p + generic map (width => ex5_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex5_state_offset to ex5_state_offset+ex5_state_q'length-1), + scout => sov(ex5_state_offset to ex5_state_offset+ex5_state_q'length-1), + din => ex5_state_d(0 to state_width-1), + dout => ex5_state_q(0 to state_width-1) ); +ex5_t_latch: tri_rlmreg_p + generic map (width => ex5_t_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex5_t_offset to ex5_t_offset+ex5_t_q'length-1), + scout => sov(ex5_t_offset to ex5_t_offset+ex5_t_q'length-1), + din => ex5_t_d(0 to t_width-1), + dout => ex5_t_q(0 to t_width-1) ); +ex6_valid_latch: tri_rlmreg_p + generic map (width => ex6_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex6_valid_offset to ex6_valid_offset+ex6_valid_q'length-1), + scout => sov(ex6_valid_offset to ex6_valid_offset+ex6_valid_q'length-1), + din => ex6_valid_d(0 to thdid_width-1), + dout => ex6_valid_q(0 to thdid_width-1) ); +ex6_ttype_latch: tri_rlmreg_p + generic map (width => ex6_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex6_ttype_offset to ex6_ttype_offset+ex6_ttype_q'length-1), + scout => sov(ex6_ttype_offset to ex6_ttype_offset+ex6_ttype_q'length-1), + din => ex6_ttype_d(0 to ttype_width-1), + dout => ex6_ttype_q(0 to ttype_width-1) ); +ex6_isel_latch: tri_rlmreg_p + generic map (width => ex6_isel_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex6_isel_offset to ex6_isel_offset+ex6_isel_q'length-1), + scout => sov(ex6_isel_offset to ex6_isel_offset+ex6_isel_q'length-1), + din => ex6_isel_d(0 to ex6_isel_d'length-1), + dout => ex6_isel_q(0 to ex6_isel_q'length-1) ); +ex6_size_latch: tri_rlmreg_p + generic map (width => ex6_size_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex6_size_offset to ex6_size_offset+ex6_size_q'length-1), + scout => sov(ex6_size_offset to ex6_size_offset+ex6_size_q'length-1), + din => ex6_size_d(0 to ex6_size_d'length-1), + dout => ex6_size_q(0 to ex6_size_q'length-1) ); +ex6_gs_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex6_gs_offset), + scout => sov(ex6_gs_offset), + din => ex6_gs_d, + dout => ex6_gs_q); +ex6_ts_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex6_ts_offset), + scout => sov(ex6_ts_offset), + din => ex6_ts_d, + dout => ex6_ts_q); +ex6_ind_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex6_ind_offset), + scout => sov(ex6_ind_offset), + din => ex6_ind_d, + dout => ex6_ind_q); +ex6_pid_latch: tri_rlmreg_p + generic map (width => ex6_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex6_pid_offset to ex6_pid_offset+ex6_pid_q'length-1), + scout => sov(ex6_pid_offset to ex6_pid_offset+ex6_pid_q'length-1), + din => ex6_pid_d(0 to pid_width-1), + dout => ex6_pid_q(0 to pid_width-1) ); +ex6_lpid_latch: tri_rlmreg_p + generic map (width => ex6_lpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex6_lpid_offset to ex6_lpid_offset+ex6_lpid_q'length-1), + scout => sov(ex6_lpid_offset to ex6_lpid_offset+ex6_lpid_q'length-1), + din => ex6_lpid_d(0 to lpid_width-1), + dout => ex6_lpid_q(0 to lpid_width-1) ); +inv_seq_latch: tri_rlmreg_p + generic map (width => inv_seq_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(inv_seq_offset to inv_seq_offset+inv_seq_q'length-1), + scout => sov(inv_seq_offset to inv_seq_offset+inv_seq_q'length-1), + din => inv_seq_d(0 to inv_seq_width-1), + dout => inv_seq_q(0 to inv_seq_width-1) ); +hold_req_latch: tri_rlmreg_p + generic map (width => hold_req_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(hold_req_offset to hold_req_offset+hold_req_q'length-1), + scout => sov(hold_req_offset to hold_req_offset+hold_req_q'length-1), + din => hold_req_d(0 to thdid_width-1), + dout => hold_req_q(0 to thdid_width-1) ); +hold_ack_latch: tri_rlmreg_p + generic map (width => hold_ack_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(hold_ack_offset to hold_ack_offset+hold_ack_q'length-1), + scout => sov(hold_ack_offset to hold_ack_offset+hold_ack_q'length-1), + din => hold_ack_d(0 to thdid_width-1), + dout => hold_ack_q(0 to thdid_width-1) ); +hold_done_latch: tri_rlmreg_p + generic map (width => hold_done_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(hold_done_offset to hold_done_offset+hold_done_q'length-1), + scout => sov(hold_done_offset to hold_done_offset+hold_done_q'length-1), + din => hold_done_d(0 to thdid_width-1), + dout => hold_done_q(0 to thdid_width-1) ); +local_barrier_latch: tri_rlmreg_p + generic map (width => local_barrier_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(local_barrier_offset to local_barrier_offset+local_barrier_q'length-1), + scout => sov(local_barrier_offset to local_barrier_offset+local_barrier_q'length-1), + din => local_barrier_d(0 to thdid_width-1), + dout => local_barrier_q(0 to thdid_width-1) ); +global_barrier_latch: tri_rlmreg_p + generic map (width => global_barrier_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(global_barrier_offset to global_barrier_offset+global_barrier_q'length-1), + scout => sov(global_barrier_offset to global_barrier_offset+global_barrier_q'length-1), + din => global_barrier_d(0 to thdid_width-1), + dout => global_barrier_q(0 to thdid_width-1) ); +barrier_done_latch: tri_rlmreg_p + generic map (width => barrier_done_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(barrier_done_offset to barrier_done_offset+barrier_done_q'length-1), + scout => sov(barrier_done_offset to barrier_done_offset+barrier_done_q'length-1), + din => barrier_done_d(0 to thdid_width-1), + dout => barrier_done_q(0 to thdid_width-1)); +illeg_instr_latch: tri_rlmreg_p + generic map (width => illeg_instr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(illeg_instr_offset to illeg_instr_offset+illeg_instr_q'length-1), + scout => sov(illeg_instr_offset to illeg_instr_offset+illeg_instr_q'length-1), + din => illeg_instr_d(0 to thdid_width-1), + dout => illeg_instr_q(0 to thdid_width-1)); +local_reject_latch: tri_rlmreg_p + generic map (width => local_reject_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(local_reject_offset to local_reject_offset+local_reject_q'length-1), + scout => sov(local_reject_offset to local_reject_offset+local_reject_q'length-1), + din => local_reject_d(0 to thdid_width-1), + dout => local_reject_q(0 to thdid_width-1)); +snoop_coming_latch: tri_rlmreg_p + generic map (width => snoop_coming_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(snoop_coming_offset to snoop_coming_offset+snoop_coming_q'length-1), + scout => sov(snoop_coming_offset to snoop_coming_offset+snoop_coming_q'length-1), + din => snoop_coming_d, + dout => snoop_coming_q ); +snoop_valid_latch: tri_rlmreg_p + generic map (width => snoop_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(snoop_valid_offset to snoop_valid_offset+snoop_valid_q'length-1), + scout => sov(snoop_valid_offset to snoop_valid_offset+snoop_valid_q'length-1), + din => snoop_valid_d, + dout => snoop_valid_q ); +snoop_attr_latch: tri_rlmreg_p + generic map (width => snoop_attr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => snoop_coming_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(snoop_attr_offset to snoop_attr_offset+snoop_attr_q'length-1), + scout => sov(snoop_attr_offset to snoop_attr_offset+snoop_attr_q'length-1), + din => snoop_attr_d, + dout => snoop_attr_q ); +snoop_vpn_latch: tri_rlmreg_p + generic map (width => snoop_vpn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => snoop_coming_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(snoop_vpn_offset to snoop_vpn_offset+snoop_vpn_q'length-1), + scout => sov(snoop_vpn_offset to snoop_vpn_offset+snoop_vpn_q'length-1), + din => snoop_vpn_d(52-epn_width to 51), + dout => snoop_vpn_q(52-epn_width to 51) ); +snoop_attr_clone_latch: tri_rlmreg_p + generic map (width => snoop_attr_clone_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => snoop_coming_q(4), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(snoop_attr_clone_offset to snoop_attr_clone_offset+snoop_attr_clone_q'length-1), + scout => sov(snoop_attr_clone_offset to snoop_attr_clone_offset+snoop_attr_clone_q'length-1), + din => snoop_attr_clone_d, + dout => snoop_attr_clone_q ); +snoop_attr_tlb_spec_latch: tri_rlmreg_p + generic map (width => snoop_attr_tlb_spec_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => snoop_coming_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(snoop_attr_tlb_spec_offset to snoop_attr_tlb_spec_offset+snoop_attr_tlb_spec_q'length-1), + scout => sov(snoop_attr_tlb_spec_offset to snoop_attr_tlb_spec_offset+snoop_attr_tlb_spec_q'length-1), + din => snoop_attr_tlb_spec_d, + dout => snoop_attr_tlb_spec_q ); +snoop_vpn_clone_latch: tri_rlmreg_p + generic map (width => snoop_vpn_clone_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => snoop_coming_q(4), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(snoop_vpn_clone_offset to snoop_vpn_clone_offset+snoop_vpn_clone_q'length-1), + scout => sov(snoop_vpn_clone_offset to snoop_vpn_clone_offset+snoop_vpn_clone_q'length-1), + din => snoop_vpn_clone_d(52-epn_width to 51), + dout => snoop_vpn_clone_q(52-epn_width to 51) ); +snoop_ack_latch: tri_rlmreg_p + generic map (width => snoop_ack_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(snoop_ack_offset to snoop_ack_offset+snoop_ack_q'length-1), + scout => sov(snoop_ack_offset to snoop_ack_offset+snoop_ack_q'length-1), + din => snoop_ack_d, + dout => snoop_ack_q ); +mm_xu_quiesce_latch: tri_rlmreg_p + generic map (width => mm_xu_quiesce_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(mm_xu_quiesce_offset to mm_xu_quiesce_offset+mm_xu_quiesce_q'length-1), + scout => sov(mm_xu_quiesce_offset to mm_xu_quiesce_offset+mm_xu_quiesce_q'length-1), + din => mm_xu_quiesce_d(0 to thdid_width-1), + dout => mm_xu_quiesce_q(0 to thdid_width-1) ); +an_ac_back_inv_latch: tri_rlmreg_p + generic map (width => an_ac_back_inv_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(an_ac_back_inv_offset to an_ac_back_inv_offset+an_ac_back_inv_q'length-1), + scout => sov(an_ac_back_inv_offset to an_ac_back_inv_offset+an_ac_back_inv_q'length-1), + din => an_ac_back_inv_d, + dout => an_ac_back_inv_q ); +an_ac_back_inv_addr_latch: tri_rlmreg_p + generic map (width => an_ac_back_inv_addr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(an_ac_back_inv_addr_offset to an_ac_back_inv_addr_offset+an_ac_back_inv_addr_q'length-1), + scout => sov(an_ac_back_inv_addr_offset to an_ac_back_inv_addr_offset+an_ac_back_inv_addr_q'length-1), + din => an_ac_back_inv_addr_d(64-real_addr_width to 63), + dout => an_ac_back_inv_addr_q(64-real_addr_width to 63) ); +an_ac_back_inv_lpar_id_latch: tri_rlmreg_p + generic map (width => an_ac_back_inv_lpar_id_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(an_ac_back_inv_lpar_id_offset to an_ac_back_inv_lpar_id_offset+an_ac_back_inv_lpar_id_q'length-1), + scout => sov(an_ac_back_inv_lpar_id_offset to an_ac_back_inv_lpar_id_offset+an_ac_back_inv_lpar_id_q'length-1), + din => an_ac_back_inv_lpar_id_d(0 to lpid_width-1), + dout => an_ac_back_inv_lpar_id_q(0 to lpid_width-1) ); +lsu_tokens_latch: tri_rlmreg_p + generic map (width => lsu_tokens_q'length, init => 1, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lsu_tokens_offset to lsu_tokens_offset+lsu_tokens_q'length-1), + scout => sov(lsu_tokens_offset to lsu_tokens_offset+lsu_tokens_q'length-1), + din => lsu_tokens_d(0 to 1), + dout => lsu_tokens_q(0 to 1) ); +lsu_req_latch: tri_rlmreg_p + generic map (width => lsu_req_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lsu_req_offset to lsu_req_offset+lsu_req_q'length-1), + scout => sov(lsu_req_offset to lsu_req_offset+lsu_req_q'length-1), + din => lsu_req_d(0 to thdid_width-1), + dout => lsu_req_q(0 to thdid_width-1) ); +lsu_ttype_latch: tri_rlmreg_p + generic map (width => lsu_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lsu_ttype_offset to lsu_ttype_offset+lsu_ttype_q'length-1), + scout => sov(lsu_ttype_offset to lsu_ttype_offset+lsu_ttype_q'length-1), + din => lsu_ttype_d(0 to 1), + dout => lsu_ttype_q(0 to 1) ); +lsu_ubits_latch: tri_rlmreg_p + generic map (width => lsu_ubits_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lsu_ubits_offset to lsu_ubits_offset+lsu_ubits_q'length-1), + scout => sov(lsu_ubits_offset to lsu_ubits_offset+lsu_ubits_q'length-1), + din => lsu_ubits_d(0 to 3), + dout => lsu_ubits_q(0 to 3) ); +lsu_wimge_latch: tri_rlmreg_p + generic map (width => lsu_wimge_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lsu_wimge_offset to lsu_wimge_offset+lsu_wimge_q'length-1), + scout => sov(lsu_wimge_offset to lsu_wimge_offset+lsu_wimge_q'length-1), + din => lsu_wimge_d(0 to 4), + dout => lsu_wimge_q(0 to 4) ); +lsu_addr_latch: tri_rlmreg_p + generic map (width => lsu_addr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lsu_addr_offset to lsu_addr_offset+lsu_addr_q'length-1), + scout => sov(lsu_addr_offset to lsu_addr_offset+lsu_addr_q'length-1), + din => lsu_addr_d(64-real_addr_width to 63), + dout => lsu_addr_q(64-real_addr_width to 63) ); +lsu_lpid_latch: tri_rlmreg_p + generic map (width => lsu_lpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lsu_lpid_offset to lsu_lpid_offset+lsu_lpid_q'length-1), + scout => sov(lsu_lpid_offset to lsu_lpid_offset+lsu_lpid_q'length-1), + din => lsu_lpid_d(0 to lpid_width-1), + dout => lsu_lpid_q(0 to lpid_width-1) ); +lsu_ind_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lsu_ind_offset), + scout => sov(lsu_ind_offset), + din => lsu_ind_d, + dout => lsu_ind_q); +lsu_gs_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lsu_gs_offset), + scout => sov(lsu_gs_offset), + din => lsu_gs_d, + dout => lsu_gs_q); +lsu_lbit_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lsu_lbit_offset), + scout => sov(lsu_lbit_offset), + din => lsu_lbit_d, + dout => lsu_lbit_q); +power_managed_latch: tri_rlmreg_p + generic map (width => power_managed_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(power_managed_offset to power_managed_offset+power_managed_q'length-1), + scout => sov(power_managed_offset to power_managed_offset+power_managed_q'length-1), + din => power_managed_d, + dout => power_managed_q ); +tlbwe_back_inv_latch: tri_rlmreg_p + generic map (width => tlbwe_back_inv_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlbwe_back_inv_offset to tlbwe_back_inv_offset+tlbwe_back_inv_q'length-1), + scout => sov(tlbwe_back_inv_offset to tlbwe_back_inv_offset+tlbwe_back_inv_q'length-1), + din => tlbwe_back_inv_d(0 to thdid_width+1), + dout => tlbwe_back_inv_q(0 to thdid_width+1) ); +tlbwe_back_inv_addr_latch: tri_rlmreg_p + generic map (width => tlbwe_back_inv_addr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlbwe_back_inv_addr_offset to tlbwe_back_inv_addr_offset+tlbwe_back_inv_addr_q'length-1), + scout => sov(tlbwe_back_inv_addr_offset to tlbwe_back_inv_addr_offset+tlbwe_back_inv_addr_q'length-1), + din => tlbwe_back_inv_addr_d(0 to epn_width-1), + dout => tlbwe_back_inv_addr_q(0 to epn_width-1) ); +tlbwe_back_inv_attr_latch: tri_rlmreg_p + generic map (width => tlbwe_back_inv_attr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlbwe_back_inv_attr_offset to tlbwe_back_inv_attr_offset+tlbwe_back_inv_attr_q'length-1), + scout => sov(tlbwe_back_inv_attr_offset to tlbwe_back_inv_attr_offset+tlbwe_back_inv_attr_q'length-1), + din => tlbwe_back_inv_attr_d, + dout => tlbwe_back_inv_attr_q ); +inv_seq_inprogress_latch: tri_rlmreg_p + generic map (width => inv_seq_inprogress_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(inv_seq_inprogress_offset to inv_seq_inprogress_offset+inv_seq_inprogress_q'length-1), + scout => sov(inv_seq_inprogress_offset to inv_seq_inprogress_offset+inv_seq_inprogress_q'length-1), + din => inv_seq_inprogress_d, + dout => inv_seq_inprogress_q); +xu_mm_ccr2_notlb_latch: tri_rlmreg_p + generic map (width => xu_mm_ccr2_notlb_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(xu_mm_ccr2_notlb_offset to xu_mm_ccr2_notlb_offset+xu_mm_ccr2_notlb_q'length-1), + scout => sov(xu_mm_ccr2_notlb_offset to xu_mm_ccr2_notlb_offset+xu_mm_ccr2_notlb_q'length-1), + din => xu_mm_ccr2_notlb_d, + dout => xu_mm_ccr2_notlb_q); +spare_latch: tri_rlmreg_p + generic map (width => spare_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(spare_offset to spare_offset+spare_q'length-1), + scout => sov(spare_offset to spare_offset+spare_q'length-1), + din => spare_q, + dout => spare_q); +epcr_dgtmi_latch : tri_regk + generic map (width => xu_mm_epcr_dgtmi_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => pc_func_slp_nsl_force, + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_nsl_thold_0_b, + din => xu_mm_spr_epcr_dgtmi, + dout => xu_mm_epcr_dgtmi_q); +lpidr_latch : tri_regk + generic map (width => lpidr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => pc_func_slp_nsl_force, + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_nsl_thold_0_b, + din => lpidr, + dout => lpidr_q); +mmucr1_latch : tri_regk + generic map (width => mmucr1_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => pc_func_slp_nsl_force, + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_nsl_thold_0_b, + din => mmucr1, + dout => mmucr1_q); +mmucr1_csinv_latch : tri_regk + generic map (width => mmucr1_csinv_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => pc_func_slp_nsl_force, + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_nsl_thold_0_b, + din => mmucr1_csinv, + dout => mmucr1_csinv_q); +perv_2to1_reg: tri_plat + generic map (width => 5, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ccflush_dc, + din(0) => pc_func_sl_thold_2, + din(1) => pc_func_slp_sl_thold_2, + din(2) => pc_func_slp_nsl_thold_2, + din(3) => pc_sg_2, + din(4) => pc_fce_2, + q(0) => pc_func_sl_thold_1, + q(1) => pc_func_slp_sl_thold_1, + q(2) => pc_func_slp_nsl_thold_1, + q(3) => pc_sg_1, + q(4) => pc_fce_1); +perv_1to0_reg: tri_plat + generic map (width => 5, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ccflush_dc, + din(0) => pc_func_sl_thold_1, + din(1) => pc_func_slp_sl_thold_1, + din(2) => pc_func_slp_nsl_thold_1, + din(3) => pc_sg_1, + din(4) => pc_fce_1, + q(0) => pc_func_sl_thold_0, + q(1) => pc_func_slp_sl_thold_0, + q(2) => pc_func_slp_nsl_thold_0, + q(3) => pc_sg_0, + q(4) => pc_fce_0); +perv_lcbor_func_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b, + thold => pc_func_sl_thold_0, + sg => pc_sg_0, + act_dis => lcb_act_dis_dc, + forcee => pc_func_sl_force, + thold_b => pc_func_sl_thold_0_b); +perv_lcbor_func_slp_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b, + thold => pc_func_slp_sl_thold_0, + sg => pc_sg_0, + act_dis => lcb_act_dis_dc, + forcee => pc_func_slp_sl_force, + thold_b => pc_func_slp_sl_thold_0_b); +perv_nsl_lcbor: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b, + thold => pc_func_slp_nsl_thold_0, + sg => pc_fce_0, + act_dis => tidn, + forcee => pc_func_slp_nsl_force, + thold_b => pc_func_slp_nsl_thold_0_b); +siv(0 to scan_right) <= sov(1 to scan_right) & ac_func_scan_in; +ac_func_scan_out <= sov(0); +end mmq_inval; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/mmq_perf.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/mmq_perf.vhdl new file mode 100644 index 0000000..7464521 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/mmq_perf.vhdl @@ -0,0 +1,595 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + + +library ieee; +use ieee.std_logic_1164.all; + +library ibm,clib; +use ibm.std_ulogic_unsigned.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; + +library support; +use support.power_logic_pkg.all; + +library tri; +use tri.tri_latches_pkg.all; + + +entity mmq_perf is +generic(thdid_width : integer := 4; + expand_type : integer := 2 ); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + + pc_func_sl_thold_2 : in std_ulogic; + pc_func_slp_nsl_thold_2 : in std_ulogic; + pc_sg_2 : in std_ulogic; + pc_fce_2 : in std_ulogic; + tc_ac_ccflush_dc : in std_ulogic; + + lcb_clkoff_dc_b : in std_ulogic; + lcb_act_dis_dc : in std_ulogic; + lcb_d_mode_dc : in std_ulogic; + lcb_delay_lclkr_dc : in std_ulogic; + lcb_mpw1_dc_b : in std_ulogic; + lcb_mpw2_dc_b : in std_ulogic; + + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + xu_mm_msr_gs : in std_ulogic_vector(0 to thdid_width-1); + xu_mm_msr_pr : in std_ulogic_vector(0 to thdid_width-1); + xu_mm_ccr2_notlb_b : in std_ulogic; + + xu_mm_ex5_perf_dtlb : in std_ulogic_vector(0 to thdid_width-1); + xu_mm_ex5_perf_itlb : in std_ulogic_vector(0 to thdid_width-1); + + tlb_cmp_perf_event_t0 : in std_ulogic_vector(0 to 9); + tlb_cmp_perf_event_t1 : in std_ulogic_vector(0 to 9); + tlb_cmp_perf_event_t2 : in std_ulogic_vector(0 to 9); + tlb_cmp_perf_event_t3 : in std_ulogic_vector(0 to 9); + tlb_cmp_perf_state : in std_ulogic_vector(0 to 1); + + tlb_cmp_perf_miss_direct : in std_ulogic; + tlb_cmp_perf_hit_indirect : in std_ulogic; + tlb_cmp_perf_hit_first_page : in std_ulogic; + tlb_cmp_perf_ptereload_noexcep : in std_ulogic; + tlb_cmp_perf_lrat_request : in std_ulogic; + tlb_cmp_perf_lrat_miss : in std_ulogic; + tlb_cmp_perf_pt_fault : in std_ulogic; + tlb_cmp_perf_pt_inelig : in std_ulogic; + tlb_ctl_perf_tlbwec_resv : in std_ulogic; + tlb_ctl_perf_tlbwec_noresv : in std_ulogic; + + derat_req0_thdid : in std_ulogic_vector(0 to thdid_width-1); + derat_req0_valid : in std_ulogic; + derat_req1_thdid : in std_ulogic_vector(0 to thdid_width-1); + derat_req1_valid : in std_ulogic; + derat_req2_thdid : in std_ulogic_vector(0 to thdid_width-1); + derat_req2_valid : in std_ulogic; + derat_req3_thdid : in std_ulogic_vector(0 to thdid_width-1); + derat_req3_valid : in std_ulogic; + + ierat_req0_thdid : in std_ulogic_vector(0 to thdid_width-1); + ierat_req0_valid : in std_ulogic; + ierat_req0_nonspec : in std_ulogic; + ierat_req1_thdid : in std_ulogic_vector(0 to thdid_width-1); + ierat_req1_valid : in std_ulogic; + ierat_req1_nonspec : in std_ulogic; + ierat_req2_thdid : in std_ulogic_vector(0 to thdid_width-1); + ierat_req2_valid : in std_ulogic; + ierat_req2_nonspec : in std_ulogic; + ierat_req3_thdid : in std_ulogic_vector(0 to thdid_width-1); + ierat_req3_valid : in std_ulogic; + ierat_req3_nonspec : in std_ulogic; + + ierat_req_taken : in std_ulogic; + derat_req_taken : in std_ulogic; + tlb_tag0_thdid : in std_ulogic_vector(0 to thdid_width-1); + tlb_tag0_type : in std_ulogic_vector(0 to 1); + tlb_seq_idle : in std_ulogic; + + inval_perf_tlbilx : in std_ulogic; + inval_perf_tlbivax : in std_ulogic; + inval_perf_tlbivax_snoop : in std_ulogic; + inval_perf_tlb_flush : in std_ulogic; + + htw_req0_valid : in std_ulogic; + htw_req0_thdid : in std_ulogic_vector(0 to thdid_width-1); + htw_req0_type : in std_ulogic_vector(0 to 1); + htw_req1_valid : in std_ulogic; + htw_req1_thdid : in std_ulogic_vector(0 to thdid_width-1); + htw_req1_type : in std_ulogic_vector(0 to 1); + htw_req2_valid : in std_ulogic; + htw_req2_thdid : in std_ulogic_vector(0 to thdid_width-1); + htw_req2_type : in std_ulogic_vector(0 to 1); + htw_req3_valid : in std_ulogic; + htw_req3_thdid : in std_ulogic_vector(0 to thdid_width-1); + htw_req3_type : in std_ulogic_vector(0 to 1); + + + pc_mm_event_mux_ctrls : in std_ulogic_vector(0 to 39); + pc_mm_event_count_mode : in std_ulogic_vector(0 to 2); + rp_mm_event_bus_enable_q : in std_ulogic; + + mm_pc_event_data : out std_ulogic_vector(0 to 7) + +); + -- synopsys translate_off + + + -- synopsys translate_on +end mmq_perf; + + +architecture mmq_perf of mmq_perf is +constant rp_mm_event_bus_enable_offset : natural := 0; +constant pc_mm_event_mux_ctrls_offset : natural := rp_mm_event_bus_enable_offset + 1; +constant pc_mm_event_count_mode_offset : natural := pc_mm_event_mux_ctrls_offset + 40; +constant xu_mm_msr_gs_offset : natural := pc_mm_event_count_mode_offset + 3; +constant xu_mm_msr_pr_offset : natural := xu_mm_msr_gs_offset + thdid_width; +constant event_data_offset : natural := xu_mm_msr_pr_offset + thdid_width; +constant scan_right : natural := event_data_offset + 8 -1; + +signal event_data_d : std_ulogic_vector(0 to 7); +signal event_data_q : std_ulogic_vector(0 to 7); +signal rp_mm_event_bus_enable_int_q : std_ulogic; +signal pc_mm_event_mux_ctrls_q : std_ulogic_vector(0 to 39); +signal pc_mm_event_count_mode_q : std_ulogic_vector(0 to 2); + +signal mm_perf_event_t0_d, mm_perf_event_t0_q : std_ulogic_vector(0 to 15); +signal mm_perf_event_t1_d, mm_perf_event_t1_q : std_ulogic_vector(0 to 15); +signal mm_perf_event_t2_d, mm_perf_event_t2_q : std_ulogic_vector(0 to 15); +signal mm_perf_event_t3_d, mm_perf_event_t3_q : std_ulogic_vector(0 to 15); + +signal xu_mm_msr_gs_q : std_ulogic_vector(0 to thdid_width-1); +signal xu_mm_msr_pr_q : std_ulogic_vector(0 to thdid_width-1); +signal event_en : std_ulogic_vector(0 to thdid_width); + +signal siv : std_ulogic_vector(0 to scan_right); +signal sov : std_ulogic_vector(0 to scan_right); + +signal tidn : std_ulogic; +signal tiup : std_ulogic; + +signal pc_func_sl_thold_1 : std_ulogic; +signal pc_func_sl_thold_0 : std_ulogic; +signal pc_func_sl_thold_0_b : std_ulogic; +signal pc_func_slp_nsl_thold_1 : std_ulogic; +signal pc_func_slp_nsl_thold_0 : std_ulogic; +signal pc_func_slp_nsl_thold_0_b : std_ulogic; +signal pc_func_slp_nsl_force : std_ulogic; +signal pc_sg_1 : std_ulogic; +signal pc_sg_0 : std_ulogic; +signal pc_fce_1 : std_ulogic; +signal pc_fce_0 : std_ulogic; +signal forcee : std_ulogic; + +begin + + +tidn <= '0'; +tiup <= '1'; + +event_en(0 to 3) <= ( xu_mm_msr_pr_q(0 to 3) and (0 to 3 => pc_mm_event_count_mode_q(0))) or + (not xu_mm_msr_pr_q(0 to 3) and xu_mm_msr_gs_q(0 to 3) and (0 to 3 => pc_mm_event_count_mode_q(1))) or + (not xu_mm_msr_pr_q(0 to 3) and not xu_mm_msr_gs_q(0 to 3) and (0 to 3 => pc_mm_event_count_mode_q(2))); + +event_en(4) <= (tlb_cmp_perf_state(1) and pc_mm_event_count_mode_q(0)) or + (not tlb_cmp_perf_state(1) and tlb_cmp_perf_state(0) and pc_mm_event_count_mode_q(1)) or + (not tlb_cmp_perf_state(1) and not tlb_cmp_perf_state(0) and pc_mm_event_count_mode_q(2)); + + + + + +mm_perf_event_t0_d(0 to 9) <= tlb_cmp_perf_event_t0(0 to 9) and (0 to 9 => event_en(0)); + +mm_perf_event_t0_d(10) <= (((ierat_req0_valid and ierat_req0_nonspec and ierat_req0_thdid(0)) or + (ierat_req1_valid and ierat_req1_nonspec and ierat_req1_thdid(0)) or + (ierat_req2_valid and ierat_req2_nonspec and ierat_req2_thdid(0)) or + (ierat_req3_valid and ierat_req3_nonspec and ierat_req3_thdid(0)) or + (not tlb_seq_idle and tlb_tag0_type(1) and tlb_tag0_thdid(0)) or + (htw_req0_valid and htw_req0_type(1) and htw_req0_thdid(0)) or + (htw_req1_valid and htw_req1_type(1) and htw_req1_thdid(0)) or + (htw_req2_valid and htw_req2_type(1) and htw_req2_thdid(0)) or + (htw_req3_valid and htw_req3_type(1) and htw_req3_thdid(0))) + and xu_mm_ccr2_notlb_b) + or (xu_mm_ex5_perf_itlb(0) and not xu_mm_ccr2_notlb_b); + +mm_perf_event_t0_d(11) <= (((derat_req0_valid and derat_req0_thdid(0)) or + (derat_req1_valid and derat_req1_thdid(0)) or + (derat_req2_valid and derat_req2_thdid(0)) or + (derat_req3_valid and derat_req3_thdid(0)) or + (not tlb_seq_idle and tlb_tag0_type(0) and tlb_tag0_thdid(0)) or + (htw_req0_valid and htw_req0_type(0) and htw_req0_thdid(0)) or + (htw_req1_valid and htw_req1_type(0) and htw_req1_thdid(0)) or + (htw_req2_valid and htw_req2_type(0) and htw_req2_thdid(0)) or + (htw_req3_valid and htw_req3_type(0) and htw_req3_thdid(0))) + and xu_mm_ccr2_notlb_b) + or (xu_mm_ex5_perf_dtlb(0) and not xu_mm_ccr2_notlb_b); + +mm_perf_event_t0_d(12) <= ierat_req_taken; + +mm_perf_event_t0_d(13) <= derat_req_taken; + +mm_perf_event_t0_d(14) <= tlb_cmp_perf_miss_direct and event_en(4); + +mm_perf_event_t0_d(15) <= tlb_cmp_perf_hit_first_page and event_en(4); + + + +mm_perf_event_t1_d(0 to 9) <= tlb_cmp_perf_event_t1(0 to 9) and (0 to 9 => event_en(1)); + +mm_perf_event_t1_d(10) <= (((ierat_req0_valid and ierat_req0_nonspec and ierat_req0_thdid(1)) or + (ierat_req1_valid and ierat_req1_nonspec and ierat_req1_thdid(1)) or + (ierat_req2_valid and ierat_req2_nonspec and ierat_req2_thdid(1)) or + (ierat_req3_valid and ierat_req3_nonspec and ierat_req3_thdid(1)) or + (not tlb_seq_idle and tlb_tag0_type(1) and tlb_tag0_thdid(1)) or + (htw_req0_valid and htw_req0_type(1) and htw_req0_thdid(1)) or + (htw_req1_valid and htw_req1_type(1) and htw_req1_thdid(1)) or + (htw_req2_valid and htw_req2_type(1) and htw_req2_thdid(1)) or + (htw_req3_valid and htw_req3_type(1) and htw_req3_thdid(1))) + and xu_mm_ccr2_notlb_b) + or (xu_mm_ex5_perf_itlb(1) and not xu_mm_ccr2_notlb_b); + +mm_perf_event_t1_d(11) <= (((derat_req0_valid and derat_req0_thdid(1)) or + (derat_req1_valid and derat_req1_thdid(1)) or + (derat_req2_valid and derat_req2_thdid(1)) or + (derat_req3_valid and derat_req3_thdid(1)) or + (not tlb_seq_idle and tlb_tag0_type(0) and tlb_tag0_thdid(1)) or + (htw_req0_valid and htw_req0_type(0) and htw_req0_thdid(1)) or + (htw_req1_valid and htw_req1_type(0) and htw_req1_thdid(1)) or + (htw_req2_valid and htw_req2_type(0) and htw_req2_thdid(1)) or + (htw_req3_valid and htw_req3_type(0) and htw_req3_thdid(1))) + and xu_mm_ccr2_notlb_b) + or (xu_mm_ex5_perf_dtlb(1) and not xu_mm_ccr2_notlb_b); + +mm_perf_event_t1_d(12) <= tlb_cmp_perf_hit_indirect and event_en(4); + +mm_perf_event_t1_d(13) <= tlb_cmp_perf_ptereload_noexcep and event_en(4); + +mm_perf_event_t1_d(14) <= tlb_cmp_perf_lrat_request and event_en(4); + +mm_perf_event_t1_d(15) <= tlb_cmp_perf_lrat_miss and event_en(4); + + +mm_perf_event_t2_d(0 to 9) <= tlb_cmp_perf_event_t2(0 to 9) and (0 to 9 => event_en(2)); + +mm_perf_event_t2_d(10) <= (((ierat_req0_valid and ierat_req0_nonspec and ierat_req0_thdid(2)) or + (ierat_req1_valid and ierat_req1_nonspec and ierat_req1_thdid(2)) or + (ierat_req2_valid and ierat_req2_nonspec and ierat_req2_thdid(2)) or + (ierat_req3_valid and ierat_req3_nonspec and ierat_req3_thdid(2)) or + (not tlb_seq_idle and tlb_tag0_type(1) and tlb_tag0_thdid(2)) or + (htw_req0_valid and htw_req0_type(1) and htw_req0_thdid(2)) or + (htw_req1_valid and htw_req1_type(1) and htw_req1_thdid(2)) or + (htw_req2_valid and htw_req2_type(1) and htw_req2_thdid(2)) or + (htw_req3_valid and htw_req3_type(1) and htw_req3_thdid(2))) + and xu_mm_ccr2_notlb_b) + or (xu_mm_ex5_perf_itlb(2) and not xu_mm_ccr2_notlb_b); + +mm_perf_event_t2_d(11) <= (((derat_req0_valid and derat_req0_thdid(2)) or + (derat_req1_valid and derat_req1_thdid(2)) or + (derat_req2_valid and derat_req2_thdid(2)) or + (derat_req3_valid and derat_req3_thdid(2)) or + (not tlb_seq_idle and tlb_tag0_type(0) and tlb_tag0_thdid(2)) or + (htw_req0_valid and htw_req0_type(0) and htw_req0_thdid(2)) or + (htw_req1_valid and htw_req1_type(0) and htw_req1_thdid(2)) or + (htw_req2_valid and htw_req2_type(0) and htw_req2_thdid(2)) or + (htw_req3_valid and htw_req3_type(0) and htw_req3_thdid(2))) + and xu_mm_ccr2_notlb_b) + or (xu_mm_ex5_perf_dtlb(2) and not xu_mm_ccr2_notlb_b); + +mm_perf_event_t2_d(12) <= tlb_cmp_perf_pt_fault and event_en(4); + +mm_perf_event_t2_d(13) <= tlb_cmp_perf_pt_inelig and event_en(4); + +mm_perf_event_t2_d(14) <= tlb_ctl_perf_tlbwec_noresv and event_en(4); + +mm_perf_event_t2_d(15) <= tlb_ctl_perf_tlbwec_resv and event_en(4); + + +mm_perf_event_t3_d(0 to 9) <= tlb_cmp_perf_event_t3(0 to 9) and (0 to 9 => event_en(3)); + +mm_perf_event_t3_d(10) <= (((ierat_req0_valid and ierat_req0_nonspec and ierat_req0_thdid(3)) or + (ierat_req1_valid and ierat_req1_nonspec and ierat_req1_thdid(3)) or + (ierat_req2_valid and ierat_req2_nonspec and ierat_req2_thdid(3)) or + (ierat_req3_valid and ierat_req3_nonspec and ierat_req3_thdid(3)) or + (not tlb_seq_idle and tlb_tag0_type(1) and tlb_tag0_thdid(3)) or + (htw_req0_valid and htw_req0_type(1) and htw_req0_thdid(3)) or + (htw_req1_valid and htw_req1_type(1) and htw_req1_thdid(3)) or + (htw_req2_valid and htw_req2_type(1) and htw_req2_thdid(3)) or + (htw_req3_valid and htw_req3_type(1) and htw_req3_thdid(3))) + and xu_mm_ccr2_notlb_b) + or (xu_mm_ex5_perf_itlb(3) and not xu_mm_ccr2_notlb_b); + +mm_perf_event_t3_d(11) <= (((derat_req0_valid and derat_req0_thdid(3)) or + (derat_req1_valid and derat_req1_thdid(3)) or + (derat_req2_valid and derat_req2_thdid(3)) or + (derat_req3_valid and derat_req3_thdid(3)) or + (not tlb_seq_idle and tlb_tag0_type(0) and tlb_tag0_thdid(3)) or + (htw_req0_valid and htw_req0_type(0) and htw_req0_thdid(3)) or + (htw_req1_valid and htw_req1_type(0) and htw_req1_thdid(3)) or + (htw_req2_valid and htw_req2_type(0) and htw_req2_thdid(3)) or + (htw_req3_valid and htw_req3_type(0) and htw_req3_thdid(3))) + and xu_mm_ccr2_notlb_b) + or (xu_mm_ex5_perf_dtlb(3) and not xu_mm_ccr2_notlb_b); + +mm_perf_event_t3_d(12) <= inval_perf_tlbilx; + +mm_perf_event_t3_d(13) <= inval_perf_tlbivax; + +mm_perf_event_t3_d(14) <= inval_perf_tlbivax_snoop; + +mm_perf_event_t3_d(15) <= inval_perf_tlb_flush; + + +event_mux1: entity clib.c_event_mux + generic map ( events_in => 64, + events_out => 8 ) + port map( + vd => vdd, + gd => gnd, + + t0_events => mm_perf_event_t0_q(0 to 15), + t1_events => mm_perf_event_t1_q(0 to 15), + t2_events => mm_perf_event_t2_q(0 to 15), + t3_events => mm_perf_event_t3_q(0 to 15), + + select_bits => pc_mm_event_mux_ctrls_q(0 to 39), + event_bits => event_data_d(0 to 7) +); + + +mm_pc_event_data <= event_data_q(0 to 7); + + + +rp_mm_event_bus_enable_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_sl_thold_0_b, + sg => pc_sg_0, + forcee => forcee, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(rp_mm_event_bus_enable_offset), + scout => sov(rp_mm_event_bus_enable_offset), + din => rp_mm_event_bus_enable_q, + dout => rp_mm_event_bus_enable_int_q); + +pc_mm_event_mux_ctrls_latch: tri_rlmreg_p + generic map (width => pc_mm_event_mux_ctrls_q'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_sl_thold_0_b, + sg => pc_sg_0, + forcee => forcee, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(pc_mm_event_mux_ctrls_offset to pc_mm_event_mux_ctrls_offset + pc_mm_event_mux_ctrls_q'length-1), + scout => sov(pc_mm_event_mux_ctrls_offset to pc_mm_event_mux_ctrls_offset + pc_mm_event_mux_ctrls_q'length-1), + din => pc_mm_event_mux_ctrls, + dout => pc_mm_event_mux_ctrls_q ); + +pc_mm_event_count_mode_latch: tri_rlmreg_p + generic map (width => pc_mm_event_count_mode_q'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_sl_thold_0_b, + sg => pc_sg_0, + forcee => forcee, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(pc_mm_event_count_mode_offset to pc_mm_event_count_mode_offset + pc_mm_event_count_mode_q'length-1), + scout => sov(pc_mm_event_count_mode_offset to pc_mm_event_count_mode_offset + pc_mm_event_count_mode_q'length-1), + din => pc_mm_event_count_mode, + dout => pc_mm_event_count_mode_q ); + +xu_mm_msr_gs_latch: tri_rlmreg_p + generic map (width => xu_mm_msr_gs_q'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rp_mm_event_bus_enable_int_q, + thold_b => pc_func_sl_thold_0_b, + sg => pc_sg_0, + forcee => forcee, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(xu_mm_msr_gs_offset to xu_mm_msr_gs_offset + xu_mm_msr_gs_q'length-1), + scout => sov(xu_mm_msr_gs_offset to xu_mm_msr_gs_offset + xu_mm_msr_gs_q'length-1), + din => xu_mm_msr_gs, + dout => xu_mm_msr_gs_q ); + +xu_mm_msr_pr_latch: tri_rlmreg_p + generic map (width => xu_mm_msr_pr_q'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rp_mm_event_bus_enable_int_q, + thold_b => pc_func_sl_thold_0_b, + sg => pc_sg_0, + forcee => forcee, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(xu_mm_msr_pr_offset to xu_mm_msr_pr_offset + xu_mm_msr_pr_q'length-1), + scout => sov(xu_mm_msr_pr_offset to xu_mm_msr_pr_offset + xu_mm_msr_pr_q'length-1), + din => xu_mm_msr_pr, + dout => xu_mm_msr_pr_q ); + + +event_data_latch: tri_rlmreg_p + generic map (width => event_data_q'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rp_mm_event_bus_enable_int_q, + thold_b => pc_func_sl_thold_0_b, + sg => pc_sg_0, + forcee => forcee, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(event_data_offset to event_data_offset + event_data_q'length-1), + scout => sov(event_data_offset to event_data_offset + event_data_q'length-1), + din => event_data_d, + dout => event_data_q ); + +mm_perf_event_t0_latch : tri_regk + generic map (width => mm_perf_event_t0_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rp_mm_event_bus_enable_int_q, + forcee => pc_func_slp_nsl_force, + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_nsl_thold_0_b, + din => mm_perf_event_t0_d, + dout => mm_perf_event_t0_q ); + +mm_perf_event_t1_latch : tri_regk + generic map (width => mm_perf_event_t1_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rp_mm_event_bus_enable_int_q, + forcee => pc_func_slp_nsl_force, + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_nsl_thold_0_b, + din => mm_perf_event_t1_d, + dout => mm_perf_event_t1_q ); + +mm_perf_event_t2_latch : tri_regk + generic map (width => mm_perf_event_t2_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rp_mm_event_bus_enable_int_q, + forcee => pc_func_slp_nsl_force, + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_nsl_thold_0_b, + din => mm_perf_event_t2_d, + dout => mm_perf_event_t2_q ); + +mm_perf_event_t3_latch : tri_regk + generic map (width => mm_perf_event_t3_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rp_mm_event_bus_enable_int_q, + forcee => pc_func_slp_nsl_force, + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_nsl_thold_0_b, + din => mm_perf_event_t3_d, + dout => mm_perf_event_t3_q ); + + + +perv_2to1_reg: tri_plat + generic map (width => 4, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_func_sl_thold_2, + din(1) => pc_func_slp_nsl_thold_2, + din(2) => pc_sg_2, + din(3) => pc_fce_2, + q(0) => pc_func_sl_thold_1, + q(1) => pc_func_slp_nsl_thold_1, + q(2) => pc_sg_1, + q(3) => pc_fce_1); + +perv_1to0_reg: tri_plat + generic map (width => 4, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_func_sl_thold_1, + din(1) => pc_func_slp_nsl_thold_1, + din(2) => pc_sg_1, + din(3) => pc_fce_1, + q(0) => pc_func_sl_thold_0, + q(1) => pc_func_slp_nsl_thold_0, + q(2) => pc_sg_0, + q(3) => pc_fce_0); + +perv_lcbor: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b, + thold => pc_func_sl_thold_0, + sg => pc_sg_0, + act_dis => lcb_act_dis_dc, + forcee => forcee, + thold_b => pc_func_sl_thold_0_b); + +perv_nsl_lcbor: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b, + thold => pc_func_slp_nsl_thold_0, + sg => pc_fce_0, + act_dis => tidn, + forcee => pc_func_slp_nsl_force, + thold_b => pc_func_slp_nsl_thold_0_b); + +siv(0 to scan_right) <= sov(1 to scan_right) & scan_in; +scan_out <= sov(0); + + +end mmq_perf; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/mmq_perv.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/mmq_perv.vhdl new file mode 100644 index 0000000..8a19af8 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/mmq_perv.vhdl @@ -0,0 +1,841 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + + +library ieee; +use ieee.std_logic_1164.all; + +library ibm; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; + +library support; +use support.power_logic_pkg.all; + +library tri; +use tri.tri_latches_pkg.all; + +entity mmq_perv is +generic(expand_type : integer := 2 ); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + pc_mm_sg_3 : in std_ulogic_vector(0 to 1); + pc_mm_func_sl_thold_3 : in std_ulogic_vector(0 to 1); + pc_mm_func_slp_sl_thold_3 : in std_ulogic_vector(0 to 1); + pc_mm_gptr_sl_thold_3 : in std_ulogic; + pc_mm_fce_3 : in std_ulogic; + + pc_mm_time_sl_thold_3 : in std_ulogic; + pc_mm_repr_sl_thold_3 : in std_ulogic; + pc_mm_abst_sl_thold_3 : in std_ulogic; + pc_mm_abst_slp_sl_thold_3 : in std_ulogic; + pc_mm_cfg_sl_thold_3 : in std_ulogic; + pc_mm_cfg_slp_sl_thold_3 : in std_ulogic; + pc_mm_func_nsl_thold_3 : in std_ulogic; + pc_mm_func_slp_nsl_thold_3 : in std_ulogic; + pc_mm_ary_nsl_thold_3 : in std_ulogic; + pc_mm_ary_slp_nsl_thold_3 : in std_ulogic; + + tc_ac_ccflush_dc : in std_ulogic; + tc_scan_diag_dc : in std_ulogic; + tc_ac_scan_dis_dc_b : in std_ulogic; + + pc_sg_0 : out std_ulogic_vector(0 to 1); + pc_sg_1 : out std_ulogic_vector(0 to 1); + pc_sg_2 : out std_ulogic_vector(0 to 1); + pc_func_sl_thold_2 : out std_ulogic_vector(0 to 1); + pc_func_slp_sl_thold_2 : out std_ulogic_vector(0 to 1); + pc_func_slp_nsl_thold_2 : out std_ulogic; + pc_cfg_sl_thold_2 : out std_ulogic; + pc_cfg_slp_sl_thold_2 : out std_ulogic; + pc_fce_2 : out std_ulogic; + + pc_time_sl_thold_0 : out std_ulogic; + pc_repr_sl_thold_0 : out std_ulogic; + pc_abst_sl_thold_0 : out std_ulogic; + pc_abst_slp_sl_thold_0 : out std_ulogic; + pc_ary_nsl_thold_0 : out std_ulogic; + pc_ary_slp_nsl_thold_0 : out std_ulogic; + pc_func_sl_thold_0 : out std_ulogic_vector(0 to 1); + pc_func_sl_thold_0_b : out std_ulogic_vector(0 to 1); + pc_func_slp_sl_thold_0 : out std_ulogic_vector(0 to 1); + pc_func_slp_sl_thold_0_b : out std_ulogic_vector(0 to 1); + + lcb_clkoff_dc_b : out std_ulogic; + lcb_act_dis_dc : out std_ulogic; + lcb_d_mode_dc : out std_ulogic; + lcb_delay_lclkr_dc : out std_ulogic_vector(0 to 4); + lcb_mpw1_dc_b : out std_ulogic_vector(0 to 4); + lcb_mpw2_dc_b : out std_ulogic; + g6t_gptr_lcb_clkoff_dc_b : out std_ulogic; + g6t_gptr_lcb_act_dis_dc : out std_ulogic; + g6t_gptr_lcb_d_mode_dc : out std_ulogic; + g6t_gptr_lcb_delay_lclkr_dc : out std_ulogic_vector(0 to 4); + g6t_gptr_lcb_mpw1_dc_b : out std_ulogic_vector(0 to 4); + g6t_gptr_lcb_mpw2_dc_b : out std_ulogic; + g8t_gptr_lcb_clkoff_dc_b : out std_ulogic; + g8t_gptr_lcb_act_dis_dc : out std_ulogic; + g8t_gptr_lcb_d_mode_dc : out std_ulogic; + g8t_gptr_lcb_delay_lclkr_dc : out std_ulogic_vector(0 to 4); + g8t_gptr_lcb_mpw1_dc_b : out std_ulogic_vector(0 to 4); + g8t_gptr_lcb_mpw2_dc_b : out std_ulogic; + + + pc_mm_abist_dcomp_g6t_2r : in std_ulogic_vector(0 to 3); + pc_mm_abist_di_0 : in std_ulogic_vector(0 to 3); + pc_mm_abist_di_g6t_2r : in std_ulogic_vector(0 to 3); + pc_mm_abist_ena_dc : in std_ulogic; + pc_mm_abist_g6t_r_wb : in std_ulogic; + pc_mm_abist_g8t1p_renb_0 : in std_ulogic; + pc_mm_abist_g8t_bw_0 : in std_ulogic; + pc_mm_abist_g8t_bw_1 : in std_ulogic; + pc_mm_abist_g8t_dcomp : in std_ulogic_vector(0 to 3); + pc_mm_abist_g8t_wenb : in std_ulogic; + pc_mm_abist_raddr_0 : in std_ulogic_vector(0 to 9); + pc_mm_abist_waddr_0 : in std_ulogic_vector(0 to 9); + pc_mm_abist_wl128_comp_ena : in std_ulogic; + + pc_mm_abist_g8t_wenb_q : out std_ulogic; + pc_mm_abist_g8t1p_renb_0_q : out std_ulogic; + pc_mm_abist_di_0_q : out std_ulogic_vector(0 to 3); + pc_mm_abist_g8t_bw_1_q : out std_ulogic; + pc_mm_abist_g8t_bw_0_q : out std_ulogic; + pc_mm_abist_waddr_0_q : out std_ulogic_vector(0 to 9); + pc_mm_abist_raddr_0_q : out std_ulogic_vector(0 to 9); + pc_mm_abist_wl128_comp_ena_q : out std_ulogic; + pc_mm_abist_g8t_dcomp_q : out std_ulogic_vector(0 to 3); + pc_mm_abist_dcomp_g6t_2r_q : out std_ulogic_vector(0 to 3); + pc_mm_abist_di_g6t_2r_q : out std_ulogic_vector(0 to 3); + pc_mm_abist_g6t_r_wb_q : out std_ulogic; + + pc_mm_bolt_sl_thold_3 : in std_ulogic; + pc_mm_bo_enable_3 : in std_ulogic; + pc_mm_bolt_sl_thold_0 : out std_ulogic; + pc_mm_bo_enable_2 : out std_ulogic; + + gptr_scan_in : in std_ulogic; + gptr_scan_out : out std_ulogic; + + time_scan_in : in std_ulogic; + time_scan_in_int : out std_ulogic; + time_scan_out_int : in std_ulogic; + time_scan_out : out std_ulogic; + + func_scan_in : in std_ulogic_vector(0 to 9); + func_scan_in_int : out std_ulogic_vector(0 to 9); + func_scan_out_int : in std_ulogic_vector(0 to 9); + func_scan_out : out std_ulogic_vector(0 to 9); + + repr_scan_in : in std_ulogic; + repr_scan_in_int : out std_ulogic; + repr_scan_out_int : in std_ulogic; + repr_scan_out : out std_ulogic; + + abst_scan_in : in std_ulogic_vector(0 to 1); + abst_scan_in_int : out std_ulogic_vector(0 to 1); + abst_scan_out_int : in std_ulogic_vector(0 to 1); + abst_scan_out : out std_ulogic_vector(0 to 1); + + bcfg_scan_in : in std_ulogic; + bcfg_scan_in_int : out std_ulogic; + bcfg_scan_out_int : in std_ulogic; + bcfg_scan_out : out std_ulogic; + + ccfg_scan_in : in std_ulogic; + ccfg_scan_in_int : out std_ulogic; + ccfg_scan_out_int : in std_ulogic; + ccfg_scan_out : out std_ulogic; + + dcfg_scan_in : in std_ulogic; + dcfg_scan_in_int : out std_ulogic; + dcfg_scan_out_int : in std_ulogic; + dcfg_scan_out : out std_ulogic + +); + + +-- synopsys translate_off + +-- synopsys translate_on + +end mmq_perv; +architecture mmq_perv of mmq_perv is + +signal tidn : std_logic; +signal tiup : std_logic; + +signal pc_func_sl_thold_2_int : std_ulogic_vector(0 to 1); +signal pc_func_slp_sl_thold_2_int : std_ulogic_vector(0 to 1); +signal pc_sg_2_int : std_ulogic_vector(0 to 1); +signal pc_gptr_sl_thold_2_int : std_ulogic; +signal pc_fce_2_int : std_ulogic; +signal pc_time_sl_thold_2_int : std_ulogic; +signal pc_repr_sl_thold_2_int : std_ulogic; +signal pc_abst_sl_thold_2_int : std_ulogic; +signal pc_abst_slp_sl_thold_2_int : std_ulogic; +signal pc_cfg_sl_thold_2_int : std_ulogic; +signal pc_cfg_slp_sl_thold_2_int : std_ulogic; +signal pc_func_nsl_thold_2_int : std_ulogic; +signal pc_func_slp_nsl_thold_2_int : std_ulogic; +signal pc_ary_nsl_thold_2_int : std_ulogic; +signal pc_ary_slp_nsl_thold_2_int : std_ulogic; +signal pc_mm_bolt_sl_thold_2_int : std_ulogic; + +signal pc_func_sl_thold_1_int : std_ulogic_vector(0 to 1); +signal pc_func_slp_sl_thold_1_int : std_ulogic_vector(0 to 1); +signal pc_sg_1_int : std_ulogic_vector(0 to 1); +signal pc_gptr_sl_thold_1_int : std_ulogic; +signal pc_fce_1_int : std_ulogic; +signal pc_time_sl_thold_1_int : std_ulogic; +signal pc_repr_sl_thold_1_int : std_ulogic; +signal pc_abst_sl_thold_1_int : std_ulogic; +signal pc_abst_slp_sl_thold_1_int : std_ulogic; +signal pc_cfg_sl_thold_1_int : std_ulogic; +signal pc_cfg_slp_sl_thold_1_int : std_ulogic; +signal pc_func_nsl_thold_1_int : std_ulogic; +signal pc_func_slp_nsl_thold_1_int : std_ulogic; +signal pc_ary_nsl_thold_1_int : std_ulogic; +signal pc_ary_slp_nsl_thold_1_int : std_ulogic; +signal pc_mm_bolt_sl_thold_1_int : std_ulogic; + +signal pc_func_sl_thold_0_int : std_ulogic_vector(0 to 1); +signal pc_func_slp_sl_thold_0_int : std_ulogic_vector(0 to 1); +signal pc_sg_0_int : std_ulogic_vector(0 to 1); +signal pc_gptr_sl_thold_0_int : std_ulogic; +signal pc_fce_0_int : std_ulogic; +signal pc_time_sl_thold_0_int : std_ulogic; +signal pc_repr_sl_thold_0_int : std_ulogic; +signal pc_abst_sl_thold_0_int : std_ulogic; +signal pc_abst_slp_sl_thold_0_int : std_ulogic; +signal pc_cfg_sl_thold_0_int : std_ulogic; +signal pc_cfg_slp_sl_thold_0_int : std_ulogic; +signal pc_func_nsl_thold_0_int : std_ulogic; +signal pc_func_slp_nsl_thold_0_int : std_ulogic; +signal pc_ary_nsl_thold_0_int : std_ulogic; +signal pc_ary_slp_nsl_thold_0_int : std_ulogic; + +signal pc_func_sl_thold_0_b_int : std_ulogic_vector(0 to 1); +signal pc_func_slp_sl_thold_0_b_int : std_ulogic_vector(0 to 1); +signal pc_func_slp_sl_force_int : std_ulogic_vector(0 to 1); +signal pc_func_sl_force_int : std_ulogic_vector(0 to 1); + +signal abst_scan_in_q :std_ulogic_vector(0 to 1); +signal abst_scan_out_q :std_ulogic_vector(0 to 1); +signal time_scan_in_q :std_ulogic; +signal time_scan_out_q :std_ulogic; +signal repr_scan_in_q :std_ulogic; +signal repr_scan_out_q :std_ulogic; +signal gptr_scan_in_q :std_ulogic; +signal gptr_scan_out_int :std_ulogic; +signal gptr_scan_out_q :std_ulogic; +signal gptr_scan_lcbctrl :std_ulogic_vector(0 to 1); +signal bcfg_scan_in_q :std_ulogic; +signal bcfg_scan_out_q :std_ulogic; +signal ccfg_scan_in_q :std_ulogic; +signal ccfg_scan_out_q :std_ulogic; +signal dcfg_scan_in_q :std_ulogic; +signal dcfg_scan_out_q :std_ulogic; +signal func_scan_in_q :std_ulogic_vector(0 to 9); +signal func_scan_out_q :std_ulogic_vector(0 to 9); + +signal slat_force :std_ulogic_vector(0 to 1); +signal abst_slat_thold_b :std_ulogic; +signal abst_slat_d2clk :std_ulogic; +signal abst_slat_lclk :clk_logic; +signal time_slat_thold_b :std_ulogic; +signal time_slat_d2clk :std_ulogic; +signal time_slat_lclk :clk_logic; +signal repr_slat_thold_b :std_ulogic; +signal repr_slat_d2clk :std_ulogic; +signal repr_slat_lclk :clk_logic; +signal gptr_slat_thold_b :std_ulogic; +signal gptr_slat_d2clk :std_ulogic; +signal gptr_slat_lclk :clk_logic; +signal bcfg_slat_thold_b :std_ulogic; +signal bcfg_slat_d2clk :std_ulogic; +signal bcfg_slat_lclk :clk_logic; +signal ccfg_slat_thold_b :std_ulogic; +signal ccfg_slat_d2clk :std_ulogic; +signal ccfg_slat_lclk :clk_logic; +signal dcfg_slat_thold_b :std_ulogic; +signal dcfg_slat_d2clk :std_ulogic; +signal dcfg_slat_lclk :clk_logic; +signal func_slat_thold_b :std_ulogic; +signal func_slat_d2clk :std_ulogic; +signal func_slat_lclk :clk_logic; + +signal pc_abst_sl_thold_0_b : std_ulogic; +signal pc_abst_sl_force : std_ulogic; +signal lcb_delay_lclkr_dc_int : std_ulogic_vector(0 to 4); +signal lcb_d_mode_dc_int : std_ulogic; +signal lcb_mpw1_dc_b_int : std_ulogic_vector(0 to 4); +signal lcb_mpw2_dc_b_int : std_ulogic; +signal lcb_clkoff_dc_b_int : std_ulogic; + +signal abist_siv :std_ulogic_vector(0 to 41); +signal abist_sov :std_ulogic_vector(0 to 41); + +signal unused_dc : std_ulogic_vector(0 to 5); +-- synopsys translate_off +-- synopsys translate_on + +begin + +tidn <= '0'; +tiup <= '1'; + +perv_3to2_reg: tri_plat + generic map (width => 20, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0 to 1) => pc_mm_func_sl_thold_3(0 to 1), + din(2 to 3) => pc_mm_func_slp_sl_thold_3(0 to 1), + din(4 to 5) => pc_mm_sg_3(0 to 1), + din(6) => pc_mm_gptr_sl_thold_3, + din(7) => pc_mm_fce_3, + din(8) => pc_mm_time_sl_thold_3, + din(9) => pc_mm_repr_sl_thold_3, + din(10) => pc_mm_abst_sl_thold_3, + din(11) => pc_mm_abst_slp_sl_thold_3, + din(12) => pc_mm_cfg_sl_thold_3, + din(13) => pc_mm_cfg_slp_sl_thold_3, + din(14) => pc_mm_func_nsl_thold_3, + din(15) => pc_mm_func_slp_nsl_thold_3, + din(16) => pc_mm_ary_nsl_thold_3, + din(17) => pc_mm_ary_slp_nsl_thold_3, + din(18) => pc_mm_bolt_sl_thold_3, + din(19) => pc_mm_bo_enable_3, + q(0 to 1) => pc_func_sl_thold_2_int(0 to 1), + q(2 to 3) => pc_func_slp_sl_thold_2_int(0 to 1), + q(4 to 5) => pc_sg_2_int(0 to 1), + q(6) => pc_gptr_sl_thold_2_int, + q(7) => pc_fce_2_int, + q(8) => pc_time_sl_thold_2_int, + q(9) => pc_repr_sl_thold_2_int, + q(10) => pc_abst_sl_thold_2_int, + q(11) => pc_abst_slp_sl_thold_2_int, + q(12) => pc_cfg_sl_thold_2_int, + q(13) => pc_cfg_slp_sl_thold_2_int, + q(14) => pc_func_nsl_thold_2_int, + q(15) => pc_func_slp_nsl_thold_2_int, + q(16) => pc_ary_nsl_thold_2_int, + q(17) => pc_ary_slp_nsl_thold_2_int, + q(18) => pc_mm_bolt_sl_thold_2_int, + q(19) => pc_mm_bo_enable_2); + + +perv_2to1_reg: tri_plat + generic map (width => 19, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0 to 1) => pc_func_sl_thold_2_int(0 to 1), + din(2 to 3) => pc_func_slp_sl_thold_2_int(0 to 1), + din(4 to 5) => pc_sg_2_int(0 to 1), + din(6) => pc_gptr_sl_thold_2_int, + din(7) => pc_fce_2_int, + din(8) => pc_time_sl_thold_2_int, + din(9) => pc_repr_sl_thold_2_int, + din(10) => pc_abst_sl_thold_2_int, + din(11) => pc_abst_slp_sl_thold_2_int, + din(12) => pc_cfg_sl_thold_2_int, + din(13) => pc_cfg_slp_sl_thold_2_int, + din(14) => pc_func_nsl_thold_2_int, + din(15) => pc_func_slp_nsl_thold_2_int, + din(16) => pc_ary_nsl_thold_2_int, + din(17) => pc_ary_slp_nsl_thold_2_int, + din(18) => pc_mm_bolt_sl_thold_2_int, + q(0 to 1) => pc_func_sl_thold_1_int(0 to 1), + q(2 to 3) => pc_func_slp_sl_thold_1_int(0 to 1), + q(4 to 5) => pc_sg_1_int(0 to 1), + q(6) => pc_gptr_sl_thold_1_int, + q(7) => pc_fce_1_int, + q(8) => pc_time_sl_thold_1_int, + q(9) => pc_repr_sl_thold_1_int, + q(10) => pc_abst_sl_thold_1_int, + q(11) => pc_abst_slp_sl_thold_1_int, + q(12) => pc_cfg_sl_thold_1_int, + q(13) => pc_cfg_slp_sl_thold_1_int, + q(14) => pc_func_nsl_thold_1_int, + q(15) => pc_func_slp_nsl_thold_1_int, + q(16) => pc_ary_nsl_thold_1_int, + q(17) => pc_ary_slp_nsl_thold_1_int, + q(18) => pc_mm_bolt_sl_thold_1_int); + +perv_1to0_reg: tri_plat + generic map (width => 19, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0 to 1) => pc_func_sl_thold_1_int(0 to 1), + din(2 to 3) => pc_func_slp_sl_thold_1_int(0 to 1), + din(4 to 5) => pc_sg_1_int(0 to 1), + din(6) => pc_gptr_sl_thold_1_int, + din(7) => pc_fce_1_int, + din(8) => pc_time_sl_thold_1_int, + din(9) => pc_repr_sl_thold_1_int, + din(10) => pc_abst_sl_thold_1_int, + din(11) => pc_abst_slp_sl_thold_1_int, + din(12) => pc_cfg_sl_thold_1_int, + din(13) => pc_cfg_slp_sl_thold_1_int, + din(14) => pc_func_nsl_thold_1_int, + din(15) => pc_func_slp_nsl_thold_1_int, + din(16) => pc_ary_nsl_thold_1_int, + din(17) => pc_ary_slp_nsl_thold_1_int, + din(18) => pc_mm_bolt_sl_thold_1_int, + q(0 to 1) => pc_func_sl_thold_0_int(0 to 1), + q(2 to 3) => pc_func_slp_sl_thold_0_int(0 to 1), + q(4 to 5) => pc_sg_0_int(0 to 1), + q(6) => pc_gptr_sl_thold_0_int, + q(7) => pc_fce_0_int, + q(8) => pc_time_sl_thold_0_int, + q(9) => pc_repr_sl_thold_0_int, + q(10) => pc_abst_sl_thold_0_int, + q(11) => pc_abst_slp_sl_thold_0_int, + q(12) => pc_cfg_sl_thold_0_int, + q(13) => pc_cfg_slp_sl_thold_0_int, + q(14) => pc_func_nsl_thold_0_int, + q(15) => pc_func_slp_nsl_thold_0_int, + q(16) => pc_ary_nsl_thold_0_int, + q(17) => pc_ary_slp_nsl_thold_0_int, + q(18) => pc_mm_bolt_sl_thold_0); + + +pc_time_sl_thold_0 <= pc_time_sl_thold_0_int; +pc_abst_sl_thold_0 <= pc_abst_sl_thold_0_int; +pc_abst_slp_sl_thold_0 <= pc_abst_slp_sl_thold_0_int; +pc_repr_sl_thold_0 <= pc_repr_sl_thold_0_int; +pc_ary_nsl_thold_0 <= pc_ary_nsl_thold_0_int; +pc_ary_slp_nsl_thold_0 <= pc_ary_slp_nsl_thold_0_int; + +pc_func_sl_thold_0 <= pc_func_sl_thold_0_int; +pc_func_sl_thold_0_b <= pc_func_sl_thold_0_b_int; +pc_func_slp_sl_thold_0 <= pc_func_slp_sl_thold_0_int; +pc_func_slp_sl_thold_0_b <= pc_func_slp_sl_thold_0_b_int; + +pc_sg_0 <= pc_sg_0_int; +pc_sg_1 <= pc_sg_1_int; +pc_sg_2 <= pc_sg_2_int; + +pc_func_sl_thold_2 <= pc_func_sl_thold_2_int; +pc_func_slp_sl_thold_2 <= pc_func_slp_sl_thold_2_int; +pc_func_slp_nsl_thold_2 <= pc_func_slp_nsl_thold_2_int; +pc_cfg_sl_thold_2 <= pc_cfg_sl_thold_2_int; +pc_cfg_slp_sl_thold_2 <= pc_cfg_slp_sl_thold_2_int; +pc_fce_2 <= pc_fce_2_int; + + +lcb_clkoff_dc_b <= lcb_clkoff_dc_b_int; +lcb_d_mode_dc <= lcb_d_mode_dc_int; +lcb_delay_lclkr_dc <= lcb_delay_lclkr_dc_int; +lcb_mpw1_dc_b <= lcb_mpw1_dc_b_int; +lcb_mpw2_dc_b <= lcb_mpw2_dc_b_int; + + + + +perv_lcbctrl: tri_lcbcntl_mac + generic map (expand_type => expand_type) + port map ( + vdd => vdd, + gnd => gnd, + sg => pc_sg_0_int(0), + nclk => nclk, + scan_in => gptr_scan_in_q, + scan_diag_dc => tc_scan_diag_dc, + thold => pc_gptr_sl_thold_0_int, + clkoff_dc_b => lcb_clkoff_dc_b_int, + delay_lclkr_dc => lcb_delay_lclkr_dc_int(0 to 4), + act_dis_dc => open, + d_mode_dc => lcb_d_mode_dc_int, + mpw1_dc_b => lcb_mpw1_dc_b_int(0 to 4), + mpw2_dc_b => lcb_mpw2_dc_b_int, + scan_out => gptr_scan_lcbctrl(0)); + +perv_g6t_gptr_lcbctrl: tri_lcbcntl_array_mac + generic map (expand_type => expand_type) + port map ( + vdd => vdd, + gnd => gnd, + sg => pc_sg_0_int(1), + nclk => nclk, + scan_in => gptr_scan_lcbctrl(0), + scan_diag_dc => tc_scan_diag_dc, + thold => pc_gptr_sl_thold_0_int, + clkoff_dc_b => g6t_gptr_lcb_clkoff_dc_b, + delay_lclkr_dc => g6t_gptr_lcb_delay_lclkr_dc(0 to 4), + act_dis_dc => open, + d_mode_dc => g6t_gptr_lcb_d_mode_dc, + mpw1_dc_b => g6t_gptr_lcb_mpw1_dc_b(0 to 4), + mpw2_dc_b => g6t_gptr_lcb_mpw2_dc_b, + scan_out => gptr_scan_lcbctrl(1)); + +perv_g8t_gptr_lcbctrl: tri_lcbcntl_array_mac + generic map (expand_type => expand_type) + port map ( + vdd => vdd, + gnd => gnd, + sg => pc_sg_0_int(1), + nclk => nclk, + scan_in => gptr_scan_lcbctrl(1), + scan_diag_dc => tc_scan_diag_dc, + thold => pc_gptr_sl_thold_0_int, + clkoff_dc_b => g8t_gptr_lcb_clkoff_dc_b, + delay_lclkr_dc => g8t_gptr_lcb_delay_lclkr_dc(0 to 4), + act_dis_dc => open, + d_mode_dc => g8t_gptr_lcb_d_mode_dc, + mpw1_dc_b => g8t_gptr_lcb_mpw1_dc_b(0 to 4), + mpw2_dc_b => g8t_gptr_lcb_mpw2_dc_b, + scan_out => gptr_scan_out_int); + +lcb_act_dis_dc <= '0'; +g8t_gptr_lcb_act_dis_dc <= '0'; +g6t_gptr_lcb_act_dis_dc <= '0'; + +time_scan_in_int <= time_scan_in_q; +repr_scan_in_int <= repr_scan_in_q; +func_scan_in_int <= func_scan_in_q; +bcfg_scan_in_int <= bcfg_scan_in_q; +ccfg_scan_in_int <= ccfg_scan_in_q; +dcfg_scan_in_int <= dcfg_scan_in_q; + +time_scan_out <= time_scan_out_q and tc_ac_scan_dis_dc_b; +gptr_scan_out <= gptr_scan_out_q and tc_ac_scan_dis_dc_b; +repr_scan_out <= repr_scan_out_q and tc_ac_scan_dis_dc_b; +func_scan_out <= func_scan_out_q and (0 to 9 => tc_ac_scan_dis_dc_b); +abst_scan_out <= abst_scan_out_q and (0 to 1 => tc_ac_scan_dis_dc_b); +bcfg_scan_out <= bcfg_scan_out_q and tc_ac_scan_dis_dc_b; +ccfg_scan_out <= ccfg_scan_out_q and tc_ac_scan_dis_dc_b; +dcfg_scan_out <= dcfg_scan_out_q and tc_ac_scan_dis_dc_b; + +slat_force <= pc_sg_0_int; +abst_slat_thold_b <= NOT pc_abst_sl_thold_0_int; +time_slat_thold_b <= NOT pc_time_sl_thold_0_int; +repr_slat_thold_b <= NOT pc_repr_sl_thold_0_int; +gptr_slat_thold_b <= NOT pc_gptr_sl_thold_0_int; +bcfg_slat_thold_b <= NOT pc_cfg_sl_thold_0_int; +ccfg_slat_thold_b <= NOT pc_cfg_sl_thold_0_int; +dcfg_slat_thold_b <= NOT pc_cfg_sl_thold_0_int; +func_slat_thold_b <= NOT pc_func_sl_thold_0_int(0); + +perv_lcbs_abst: tri_lcbs + generic map (expand_type => expand_type ) + port map ( + vd => vdd, + gd => gnd, + delay_lclkr => lcb_delay_lclkr_dc_int(0), + nclk => nclk, + forcee => slat_force(1), + thold_b => abst_slat_thold_b, + dclk => abst_slat_d2clk, + lclk => abst_slat_lclk ); + +perv_abst_stg: tri_slat_scan + generic map (width => 4, init => "0000", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => abst_slat_d2clk, + lclk => abst_slat_lclk, + scan_in(0 to 1) => abst_scan_in, + scan_in(2 to 3) => abst_scan_out_int, + scan_out(0 to 1) => abst_scan_in_q, + scan_out(2 to 3) => abst_scan_out_q ); + +perv_lcbs_time: tri_lcbs + generic map (expand_type => expand_type ) + port map ( + vd => vdd, + gd => gnd, + delay_lclkr => lcb_delay_lclkr_dc_int(0), + nclk => nclk, + forcee => slat_force(1), + thold_b => time_slat_thold_b, + dclk => time_slat_d2clk, + lclk => time_slat_lclk ); + +perv_time_stg: tri_slat_scan + generic map (width => 2, init => "00", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => time_slat_d2clk, + lclk => time_slat_lclk, + scan_in(0) => time_scan_in, + scan_in(1) => time_scan_out_int, + scan_out(0) => time_scan_in_q, + scan_out(1) => time_scan_out_q ); + +perv_lcbs_repr: tri_lcbs + generic map (expand_type => expand_type ) + port map ( + vd => vdd, + gd => gnd, + delay_lclkr => lcb_delay_lclkr_dc_int(0), + nclk => nclk, + forcee => slat_force(1), + thold_b => repr_slat_thold_b, + dclk => repr_slat_d2clk, + lclk => repr_slat_lclk ); + +perv_repr_stg: tri_slat_scan + generic map (width => 2, init => "00", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => repr_slat_d2clk, + lclk => repr_slat_lclk, + scan_in(0) => repr_scan_in, + scan_in(1) => repr_scan_out_int, + scan_out(0) => repr_scan_in_q, + scan_out(1) => repr_scan_out_q ); + +perv_lcbs_gptr: tri_lcbs + generic map (expand_type => expand_type ) + port map ( + vd => vdd, + gd => gnd, + delay_lclkr => tiup, + nclk => nclk, + forcee => slat_force(0), + thold_b => gptr_slat_thold_b, + dclk => gptr_slat_d2clk, + lclk => gptr_slat_lclk ); + +perv_gptr_stg: tri_slat_scan + generic map (width => 2, init => "00", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => gptr_slat_d2clk, + lclk => gptr_slat_lclk, + scan_in(0) => gptr_scan_in, + scan_in(1) => gptr_scan_out_int, + scan_out(0) => gptr_scan_in_q, + scan_out(1) => gptr_scan_out_q ); + +perv_lcbs_bcfg: tri_lcbs + generic map (expand_type => expand_type ) + port map ( + vd => vdd, + gd => gnd, + delay_lclkr => lcb_delay_lclkr_dc_int(0), + nclk => nclk, + forcee => slat_force(0), + thold_b => bcfg_slat_thold_b, + dclk => bcfg_slat_d2clk, + lclk => bcfg_slat_lclk ); + +perv_bcfg_stg: tri_slat_scan + generic map (width => 2, init => "00", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => bcfg_slat_d2clk, + lclk => bcfg_slat_lclk, + scan_in(0) => bcfg_scan_in, + scan_in(1) => bcfg_scan_out_int, + scan_out(0) => bcfg_scan_in_q, + scan_out(1) => bcfg_scan_out_q ); + +perv_lcbs_ccfg: tri_lcbs + generic map (expand_type => expand_type ) + port map ( + vd => vdd, + gd => gnd, + delay_lclkr => lcb_delay_lclkr_dc_int(0), + nclk => nclk, + forcee => slat_force(0), + thold_b => ccfg_slat_thold_b, + dclk => ccfg_slat_d2clk, + lclk => ccfg_slat_lclk ); + +perv_ccfg_stg: tri_slat_scan + generic map (width => 2, init => "00", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => ccfg_slat_d2clk, + lclk => ccfg_slat_lclk, + scan_in(0) => ccfg_scan_in, + scan_in(1) => ccfg_scan_out_int, + scan_out(0) => ccfg_scan_in_q, + scan_out(1) => ccfg_scan_out_q ); + +perv_lcbs_dcfg: tri_lcbs + generic map (expand_type => expand_type ) + port map ( + vd => vdd, + gd => gnd, + delay_lclkr => lcb_delay_lclkr_dc_int(0), + nclk => nclk, + forcee => slat_force(0), + thold_b => dcfg_slat_thold_b, + dclk => dcfg_slat_d2clk, + lclk => dcfg_slat_lclk ); + +perv_dcfg_stg: tri_slat_scan + generic map (width => 2, init => "00", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => dcfg_slat_d2clk, + lclk => dcfg_slat_lclk, + scan_in(0) => dcfg_scan_in, + scan_in(1) => dcfg_scan_out_int, + scan_out(0) => dcfg_scan_in_q, + scan_out(1) => dcfg_scan_out_q ); + +perv_lcbs_func: tri_lcbs + generic map (expand_type => expand_type ) + port map ( + vd => vdd, + gd => gnd, + delay_lclkr => lcb_delay_lclkr_dc_int(0), + nclk => nclk, + forcee => slat_force(0), + thold_b => func_slat_thold_b, + dclk => func_slat_d2clk, + lclk => func_slat_lclk ); + +perv_func_stg: tri_slat_scan + generic map (width => 20, init => "00000000000000000000", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => func_slat_d2clk, + lclk => func_slat_lclk, + scan_in(0 to 9) => func_scan_in, + scan_in(10 to 19) => func_scan_out_int, + scan_out(0 to 9) => func_scan_in_q, + scan_out(10 to 19) => func_scan_out_q ); + + +perv_lcbor_func_sl_0: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b_int, + thold => pc_func_sl_thold_0_int(0), + sg => pc_sg_0_int(0), + act_dis => tidn, + forcee => pc_func_sl_force_int(0), + thold_b => pc_func_sl_thold_0_b_int(0)); + +perv_lcbor_func_sl_1: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b_int, + thold => pc_func_sl_thold_0_int(1), + sg => pc_sg_0_int(1), + act_dis => tidn, + forcee => pc_func_sl_force_int(1), + thold_b => pc_func_sl_thold_0_b_int(1)); + +perv_lcbor_func_slp_sl_0: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b_int, + thold => pc_func_slp_sl_thold_0_int(0), + sg => pc_sg_0_int(0), + act_dis => tidn, + forcee => pc_func_slp_sl_force_int(0), + thold_b => pc_func_slp_sl_thold_0_b_int(0)); + +perv_lcbor_func_slp_sl_1: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b_int, + thold => pc_func_slp_sl_thold_0_int(1), + sg => pc_sg_0_int(1), + act_dis => tidn, + forcee => pc_func_slp_sl_force_int(1), + thold_b => pc_func_slp_sl_thold_0_b_int(1)); + +perv_lcbor_abst_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b_int, + thold => pc_abst_sl_thold_0_int, + sg => pc_sg_0_int(1), + act_dis => tidn, + forcee => pc_abst_sl_force, + thold_b => pc_abst_sl_thold_0_b); + + + + +abist_reg: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 42, needs_sreset => 0) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => pc_mm_abist_ena_dc, + thold_b => pc_abst_sl_thold_0_b, + sg => pc_sg_0_int(1), + forcee => pc_abst_sl_force, + delay_lclkr => lcb_delay_lclkr_dc_int(0), + mpw1_b => lcb_mpw1_dc_b_int(0), + mpw2_b => lcb_mpw2_dc_b_int, + d_mode => lcb_d_mode_dc_int, + scin => abist_siv(0 to 41), + scout => abist_sov(0 to 41), + din (0) => pc_mm_abist_g8t_wenb, + din (1) => pc_mm_abist_g8t1p_renb_0, + din (2 to 5) => pc_mm_abist_di_0, + din (6) => pc_mm_abist_g8t_bw_1, + din (7) => pc_mm_abist_g8t_bw_0, + din (8 to 17) => pc_mm_abist_waddr_0, + din (18 to 27) => pc_mm_abist_raddr_0, + din (28) => pc_mm_abist_wl128_comp_ena, + din (29 to 32) => pc_mm_abist_g8t_dcomp, + din (33 to 36) => pc_mm_abist_dcomp_g6t_2r, + din (37 to 40) => pc_mm_abist_di_g6t_2r, + din (41) => pc_mm_abist_g6t_r_wb, + dout(0) => pc_mm_abist_g8t_wenb_q, + dout(1) => pc_mm_abist_g8t1p_renb_0_q, + dout(2 to 5) => pc_mm_abist_di_0_q, + dout(6) => pc_mm_abist_g8t_bw_1_q, + dout(7) => pc_mm_abist_g8t_bw_0_q, + dout(8 to 17) => pc_mm_abist_waddr_0_q, + dout(18 to 27) => pc_mm_abist_raddr_0_q, + dout(28) => pc_mm_abist_wl128_comp_ena_q, + dout(29 to 32) => pc_mm_abist_g8t_dcomp_q, + dout(33 to 36) => pc_mm_abist_dcomp_g6t_2r_q, + dout(37 to 40) => pc_mm_abist_di_g6t_2r_q, + dout(41) => pc_mm_abist_g6t_r_wb_q); + +abist_siv <= abist_sov(1 to abist_sov'right) & abst_scan_in_q(0); +abst_scan_in_int(0) <= abist_sov(0); +abst_scan_in_int(1) <= abst_scan_in_q(1); + +unused_dc(0) <= PC_FCE_0_INT; +unused_dc(1) <= PC_CFG_SLP_SL_THOLD_0_INT; +unused_dc(2) <= PC_FUNC_NSL_THOLD_0_INT; +unused_dc(3) <= PC_FUNC_SLP_NSL_THOLD_0_INT; +unused_dc(4) <= or_reduce(PC_FUNC_SL_FORCE_INT); +unused_dc(5) <= or_reduce(PC_FUNC_SLP_SL_FORCE_INT); + + +end mmq_perv; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/mmq_spr.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/mmq_spr.vhdl new file mode 100644 index 0000000..881f156 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/mmq_spr.vhdl @@ -0,0 +1,6855 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library ibm; +use ibm.std_ulogic_unsigned.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_support.all; +library support; +use support.power_logic_pkg.all; + +library tri; +use tri.tri_latches_pkg.all; +entity mmq_spr is + generic(pid_width : integer := 14; + lpid_width : integer := 8; + epn_width : integer := 52; + thdid_width : integer := 4; + class_width : integer := 2; + extclass_width : integer := 2; + mmucr0_width : integer := 20; + mmucr1_width : integer := 32; + mmucr2_width : integer := 32; + mmucr3_width : integer := 15; + spr_ctl_width : integer := 3; + spr_etid_width : integer := 2; + spr_addr_width : integer := 10; + spr_data_width : integer := 64; + real_addr_width : integer := 42; + bcfg_mmucr1_value : integer := 201326592; + bcfg_mmucr2_value : integer := 685361; + bcfg_mmucr3_value : integer := 15; + bcfg_mmucfg_value : integer := 3; + bcfg_tlb0cfg_value : integer := 7; + mmq_spr_cswitch_0to3 : integer := 0; + expand_tlb_type : integer := 2; + expand_type : integer := 2 ); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + + + tc_ccflush_dc : in std_ulogic; + tc_scan_dis_dc_b : in std_ulogic; + tc_scan_diag_dc : in std_ulogic; + tc_lbist_en_dc : in std_ulogic; + + lcb_d_mode_dc : in std_ulogic; + lcb_clkoff_dc_b : in std_ulogic; + lcb_act_dis_dc : in std_ulogic; + lcb_mpw1_dc_b : in std_ulogic_vector(0 to 4); + lcb_mpw2_dc_b : in std_ulogic; + lcb_delay_lclkr_dc : in std_ulogic_vector(0 to 4); + + ac_func_scan_in :in std_ulogic_vector(0 to 1); + ac_func_scan_out :out std_ulogic_vector(0 to 1); + ac_bcfg_scan_in :in std_ulogic; + ac_bcfg_scan_out :out std_ulogic; + + pc_sg_2 : in std_ulogic; + pc_func_sl_thold_2 : in std_ulogic; + pc_func_slp_sl_thold_2 : in std_ulogic; + pc_func_slp_nsl_thold_2 : in std_ulogic; + pc_cfg_sl_thold_2 : in std_ulogic; + pc_cfg_slp_sl_thold_2 : in std_ulogic; + pc_fce_2 : in std_ulogic; + xu_mm_ccr2_notlb_b : in std_ulogic; + mmucr2_act_override : in std_ulogic_vector(5 to 6); + tlb_delayed_act : in std_ulogic_vector(29 to 32); + + mm_iu_ierat_pid0 : out std_ulogic_vector(0 to pid_width-1); + mm_iu_ierat_pid1 : out std_ulogic_vector(0 to pid_width-1); + mm_iu_ierat_pid2 : out std_ulogic_vector(0 to pid_width-1); + mm_iu_ierat_pid3 : out std_ulogic_vector(0 to pid_width-1); + mm_iu_ierat_mmucr0_0 : out std_ulogic_vector(0 to 19); + mm_iu_ierat_mmucr0_1 : out std_ulogic_vector(0 to 19); + mm_iu_ierat_mmucr0_2 : out std_ulogic_vector(0 to 19); + mm_iu_ierat_mmucr0_3 : out std_ulogic_vector(0 to 19); + iu_mm_ierat_mmucr0 : in std_ulogic_vector(0 to 17); + iu_mm_ierat_mmucr0_we : in std_ulogic_vector(0 to thdid_width-1); + mm_iu_ierat_mmucr1 : out std_ulogic_vector(0 to 8); + iu_mm_ierat_mmucr1 : in std_ulogic_vector(0 to 3); + iu_mm_ierat_mmucr1_we : in std_ulogic; + + mm_xu_derat_pid0 : out std_ulogic_vector(0 to pid_width-1); + mm_xu_derat_pid1 : out std_ulogic_vector(0 to pid_width-1); + mm_xu_derat_pid2 : out std_ulogic_vector(0 to pid_width-1); + mm_xu_derat_pid3 : out std_ulogic_vector(0 to pid_width-1); + mm_xu_derat_mmucr0_0 : out std_ulogic_vector(0 to 19); + mm_xu_derat_mmucr0_1 : out std_ulogic_vector(0 to 19); + mm_xu_derat_mmucr0_2 : out std_ulogic_vector(0 to 19); + mm_xu_derat_mmucr0_3 : out std_ulogic_vector(0 to 19); + xu_mm_derat_mmucr0 : in std_ulogic_vector(0 to 17); + xu_mm_derat_mmucr0_we : in std_ulogic_vector(0 to thdid_width-1); + mm_xu_derat_mmucr1 : out std_ulogic_vector(0 to 9); + xu_mm_derat_mmucr1 : in std_ulogic_vector(0 to 4); + xu_mm_derat_mmucr1_we : in std_ulogic; + + pid0 : out std_ulogic_vector(0 to pid_width-1); + pid1 : out std_ulogic_vector(0 to pid_width-1); + pid2 : out std_ulogic_vector(0 to pid_width-1); + pid3 : out std_ulogic_vector(0 to pid_width-1); + mmucr0_0 : out std_ulogic_vector(0 to mmucr0_width-1); + mmucr0_1 : out std_ulogic_vector(0 to mmucr0_width-1); + mmucr0_2 : out std_ulogic_vector(0 to mmucr0_width-1); + mmucr0_3 : out std_ulogic_vector(0 to mmucr0_width-1); + mmucr1 : out std_ulogic_vector(0 to mmucr1_width-1); + mmucr2 : out std_ulogic_vector(0 to mmucr2_width-1); + mmucr3_0 : out std_ulogic_vector(64-mmucr3_width to 63); + mmucr3_1 : out std_ulogic_vector(64-mmucr3_width to 63); + mmucr3_2 : out std_ulogic_vector(64-mmucr3_width to 63); + mmucr3_3 : out std_ulogic_vector(64-mmucr3_width to 63); + mmucfg_lrat : out std_ulogic; + mmucfg_twc : out std_ulogic; + tlb0cfg_pt : out std_ulogic; + tlb0cfg_ind : out std_ulogic; + tlb0cfg_gtwe : out std_ulogic; + + mas0_0_atsel : out std_ulogic; + mas0_0_esel : out std_ulogic_vector(0 to 2); + mas0_0_hes : out std_ulogic; + mas0_0_wq : out std_ulogic_vector(0 to 1); + mas1_0_v : out std_ulogic; + mas1_0_iprot : out std_ulogic; + mas1_0_tid : out std_ulogic_vector(0 to 13); + mas1_0_ind : out std_ulogic; + mas1_0_ts : out std_ulogic; + mas1_0_tsize : out std_ulogic_vector(0 to 3); + mas2_0_epn : out std_ulogic_vector(0 to 51); + mas2_0_wimge : out std_ulogic_vector(0 to 4); + mas3_0_rpnl : out std_ulogic_vector(32 to 52); + mas3_0_ubits : out std_ulogic_vector(0 to 3); + mas3_0_usxwr : out std_ulogic_vector(0 to 5); + mas5_0_sgs : out std_ulogic; + mas5_0_slpid : out std_ulogic_vector(0 to 7); + mas6_0_spid : out std_ulogic_vector(0 to 13); + mas6_0_isize : out std_ulogic_vector(0 to 3); + mas6_0_sind : out std_ulogic; + mas6_0_sas : out std_ulogic; + mas7_0_rpnu : out std_ulogic_vector(22 to 31); + mas8_0_tgs : out std_ulogic; + mas8_0_vf : out std_ulogic; + mas8_0_tlpid : out std_ulogic_vector(0 to 7); + mas0_1_atsel : out std_ulogic; + mas0_1_esel : out std_ulogic_vector(0 to 2); + mas0_1_hes : out std_ulogic; + mas0_1_wq : out std_ulogic_vector(0 to 1); + mas1_1_v : out std_ulogic; + mas1_1_iprot : out std_ulogic; + mas1_1_tid : out std_ulogic_vector(0 to 13); + mas1_1_ind : out std_ulogic; + mas1_1_ts : out std_ulogic; + mas1_1_tsize : out std_ulogic_vector(0 to 3); + mas2_1_epn : out std_ulogic_vector(0 to 51); + mas2_1_wimge : out std_ulogic_vector(0 to 4); + mas3_1_rpnl : out std_ulogic_vector(32 to 52); + mas3_1_ubits : out std_ulogic_vector(0 to 3); + mas3_1_usxwr : out std_ulogic_vector(0 to 5); + mas5_1_sgs : out std_ulogic; + mas5_1_slpid : out std_ulogic_vector(0 to 7); + mas6_1_spid : out std_ulogic_vector(0 to 13); + mas6_1_isize : out std_ulogic_vector(0 to 3); + mas6_1_sind : out std_ulogic; + mas6_1_sas : out std_ulogic; + mas7_1_rpnu : out std_ulogic_vector(22 to 31); + mas8_1_tgs : out std_ulogic; + mas8_1_vf : out std_ulogic; + mas8_1_tlpid : out std_ulogic_vector(0 to 7); + mas0_2_atsel : out std_ulogic; + mas0_2_esel : out std_ulogic_vector(0 to 2); + mas0_2_hes : out std_ulogic; + mas0_2_wq : out std_ulogic_vector(0 to 1); + mas1_2_v : out std_ulogic; + mas1_2_iprot : out std_ulogic; + mas1_2_tid : out std_ulogic_vector(0 to 13); + mas1_2_ind : out std_ulogic; + mas1_2_ts : out std_ulogic; + mas1_2_tsize : out std_ulogic_vector(0 to 3); + mas2_2_epn : out std_ulogic_vector(0 to 51); + mas2_2_wimge : out std_ulogic_vector(0 to 4); + mas3_2_rpnl : out std_ulogic_vector(32 to 52); + mas3_2_ubits : out std_ulogic_vector(0 to 3); + mas3_2_usxwr : out std_ulogic_vector(0 to 5); + mas5_2_sgs : out std_ulogic; + mas5_2_slpid : out std_ulogic_vector(0 to 7); + mas6_2_spid : out std_ulogic_vector(0 to 13); + mas6_2_isize : out std_ulogic_vector(0 to 3); + mas6_2_sind : out std_ulogic; + mas6_2_sas : out std_ulogic; + mas7_2_rpnu : out std_ulogic_vector(22 to 31); + mas8_2_tgs : out std_ulogic; + mas8_2_vf : out std_ulogic; + mas8_2_tlpid : out std_ulogic_vector(0 to 7); + mas0_3_atsel : out std_ulogic; + mas0_3_esel : out std_ulogic_vector(0 to 2); + mas0_3_hes : out std_ulogic; + mas0_3_wq : out std_ulogic_vector(0 to 1); + mas1_3_v : out std_ulogic; + mas1_3_iprot : out std_ulogic; + mas1_3_tid : out std_ulogic_vector(0 to 13); + mas1_3_ind : out std_ulogic; + mas1_3_ts : out std_ulogic; + mas1_3_tsize : out std_ulogic_vector(0 to 3); + mas2_3_epn : out std_ulogic_vector(0 to 51); + mas2_3_wimge : out std_ulogic_vector(0 to 4); + mas3_3_rpnl : out std_ulogic_vector(32 to 52); + mas3_3_ubits : out std_ulogic_vector(0 to 3); + mas3_3_usxwr : out std_ulogic_vector(0 to 5); + mas5_3_sgs : out std_ulogic; + mas5_3_slpid : out std_ulogic_vector(0 to 7); + mas6_3_spid : out std_ulogic_vector(0 to 13); + mas6_3_isize : out std_ulogic_vector(0 to 3); + mas6_3_sind : out std_ulogic; + mas6_3_sas : out std_ulogic; + mas7_3_rpnu : out std_ulogic_vector(22 to 31); + mas8_3_tgs : out std_ulogic; + mas8_3_vf : out std_ulogic; + mas8_3_tlpid : out std_ulogic_vector(0 to 7); + tlb_mas0_esel : in std_ulogic_vector(0 to 2); + tlb_mas1_v : in std_ulogic; + tlb_mas1_iprot : in std_ulogic; + tlb_mas1_tid : in std_ulogic_vector(0 to pid_width-1); + tlb_mas1_tid_error : in std_ulogic_vector(0 to pid_width-1); + tlb_mas1_ind : in std_ulogic; + tlb_mas1_ts : in std_ulogic; + tlb_mas1_ts_error : in std_ulogic; + tlb_mas1_tsize : in std_ulogic_vector(0 to 3); + tlb_mas2_epn : in std_ulogic_vector(0 to epn_width-1); + tlb_mas2_epn_error : in std_ulogic_vector(0 to epn_width-1); + tlb_mas2_wimge : in std_ulogic_vector(0 to 4); + tlb_mas3_rpnl : in std_ulogic_vector(32 to 51); + tlb_mas3_ubits : in std_ulogic_vector(0 to 3); + tlb_mas3_usxwr : in std_ulogic_vector(0 to 5); + tlb_mas6_spid : in std_ulogic_vector(0 to pid_width-1); + tlb_mas6_isize : in std_ulogic_vector(0 to 3); + tlb_mas6_sind : in std_ulogic; + tlb_mas6_sas : in std_ulogic; + tlb_mas7_rpnu : in std_ulogic_vector(22 to 31); + tlb_mas8_tgs : in std_ulogic; + tlb_mas8_vf : in std_ulogic; + tlb_mas8_tlpid : in std_ulogic_vector(0 to 7); + + tlb_mmucr1_een : in std_ulogic_vector(0 to 8); + tlb_mmucr1_we : in std_ulogic; + tlb_mmucr3_thdid : in std_ulogic_vector(0 to thdid_width-1); + tlb_mmucr3_resvattr : in std_ulogic; + tlb_mmucr3_wlc : in std_ulogic_vector(0 to 1); + tlb_mmucr3_class : in std_ulogic_vector(0 to class_width-1); + tlb_mmucr3_extclass : in std_ulogic_vector(0 to extclass_width-1); + tlb_mmucr3_rc : in std_ulogic_vector(0 to 1); + tlb_mmucr3_x : in std_ulogic; + tlb_mas_tlbre : in std_ulogic; + tlb_mas_tlbsx_hit : in std_ulogic; + tlb_mas_tlbsx_miss : in std_ulogic; + tlb_mas_dtlb_error : in std_ulogic; + tlb_mas_itlb_error : in std_ulogic; + tlb_mas_thdid : in std_ulogic_vector(0 to thdid_width-1); + + mmucsr0_tlb0fi : out std_ulogic; + mmq_inval_tlb0fi_done : in std_ulogic; + + lrat_mmucr3_x : in std_ulogic; + lrat_mas0_esel : in std_ulogic_vector(0 to 2); + lrat_mas1_v : in std_ulogic; + lrat_mas1_tsize : in std_ulogic_vector(0 to 3); + lrat_mas2_epn : in std_ulogic_vector(0 to 51); + lrat_mas3_rpnl : in std_ulogic_vector(32 to 51); + lrat_mas7_rpnu : in std_ulogic_vector(22 to 31); + lrat_mas8_tlpid : in std_ulogic_vector(0 to lpid_width-1); + lrat_mas_tlbre : in std_ulogic; + lrat_mas_tlbsx_hit : in std_ulogic; + lrat_mas_tlbsx_miss : in std_ulogic; + lrat_mas_thdid : in std_ulogic_vector(0 to thdid_width-1); + lrat_tag4_hit_entry : in std_ulogic_vector(0 to 2); + + tlb_lper_lpn : in std_ulogic_vector(64-real_addr_width to 51); + tlb_lper_lps : in std_ulogic_vector(60 to 63); + tlb_lper_we : in std_ulogic_vector(0 to thdid_width-1); + + lpidr : out std_ulogic_vector(0 to lpid_width-1); + ac_an_lpar_id : out std_ulogic_vector(0 to lpid_width-1); + + spr_dbg_match_64b : out std_ulogic; + spr_dbg_match_any_mmu : out std_ulogic; + spr_dbg_match_any_mas : out std_ulogic; + spr_dbg_match_pid : out std_ulogic; + spr_dbg_match_lpidr : out std_ulogic; + spr_dbg_match_mmucr0 : out std_ulogic; + spr_dbg_match_mmucr1 : out std_ulogic; + spr_dbg_match_mmucr2 : out std_ulogic; + spr_dbg_match_mmucr3 : out std_ulogic; + + spr_dbg_match_mmucsr0 : out std_ulogic; + spr_dbg_match_mmucfg : out std_ulogic; + spr_dbg_match_tlb0cfg : out std_ulogic; + spr_dbg_match_tlb0ps : out std_ulogic; + spr_dbg_match_lratcfg : out std_ulogic; + spr_dbg_match_lratps : out std_ulogic; + spr_dbg_match_eptcfg : out std_ulogic; + spr_dbg_match_lper : out std_ulogic; + spr_dbg_match_lperu : out std_ulogic; + + spr_dbg_match_mas0 : out std_ulogic; + spr_dbg_match_mas1 : out std_ulogic; + spr_dbg_match_mas2 : out std_ulogic; + spr_dbg_match_mas2u : out std_ulogic; + spr_dbg_match_mas3 : out std_ulogic; + spr_dbg_match_mas4 : out std_ulogic; + spr_dbg_match_mas5 : out std_ulogic; + spr_dbg_match_mas6 : out std_ulogic; + spr_dbg_match_mas7 : out std_ulogic; + spr_dbg_match_mas8 : out std_ulogic; + spr_dbg_match_mas01_64b : out std_ulogic; + spr_dbg_match_mas56_64b : out std_ulogic; + spr_dbg_match_mas73_64b : out std_ulogic; + spr_dbg_match_mas81_64b : out std_ulogic; + + spr_dbg_slowspr_val_int : out std_ulogic; + spr_dbg_slowspr_rw_int : out std_ulogic; + spr_dbg_slowspr_etid_int : out std_ulogic_vector(0 to 1); + spr_dbg_slowspr_addr_int : out std_ulogic_vector(0 to 9); + spr_dbg_slowspr_val_out : out std_ulogic; + spr_dbg_slowspr_done_out : out std_ulogic; + spr_dbg_slowspr_data_out : out std_ulogic_vector(64-spr_data_width to 63); + + xu_mm_slowspr_val : in std_ulogic; + xu_mm_slowspr_rw : in std_ulogic; + xu_mm_slowspr_etid : in std_ulogic_vector(0 to 1); + xu_mm_slowspr_addr : in std_ulogic_vector(0 to 9); + xu_mm_slowspr_data : in std_ulogic_vector(64-spr_data_width to 63); + xu_mm_slowspr_done : in std_ulogic; + + mm_iu_slowspr_val : out std_ulogic; + mm_iu_slowspr_rw : out std_ulogic; + mm_iu_slowspr_etid : out std_ulogic_vector(0 to 1); + mm_iu_slowspr_addr : out std_ulogic_vector(0 to 9); + mm_iu_slowspr_data : out std_ulogic_vector(64-spr_data_width to 63); + mm_iu_slowspr_done : out std_ulogic + + +); +end mmq_spr; +architecture mmq_spr of mmq_spr is +constant Spr_Addr_PID : std_ulogic_vector(0 to 9) := "0000110000"; +constant Spr_Addr_LPID : std_ulogic_vector(0 to 9) := "0101010010"; +constant Spr_Addr_MMUCR0 : std_ulogic_vector(0 to 9) := "1111111100"; +constant Spr_Addr_MMUCR1 : std_ulogic_vector(0 to 9) := "1111111101"; +constant Spr_Addr_MMUCR2 : std_ulogic_vector(0 to 9) := "1111111110"; +constant Spr_Addr_MMUCR3 : std_ulogic_vector(0 to 9) := "1111111111"; +constant Spr_RW_Write : std_ulogic := '0'; +constant Spr_RW_Read : std_ulogic := '1'; +constant Spr_Addr_MAS0 : std_ulogic_vector(0 to 9) := "1001110000"; +constant Spr_Addr_MAS1 : std_ulogic_vector(0 to 9) := "1001110001"; +constant Spr_Addr_MAS2 : std_ulogic_vector(0 to 9) := "1001110010"; +constant Spr_Addr_MAS2U : std_ulogic_vector(0 to 9) := "1001110111"; +constant Spr_Addr_MAS3 : std_ulogic_vector(0 to 9) := "1001110011"; +constant Spr_Addr_MAS4 : std_ulogic_vector(0 to 9) := "1001110100"; +constant Spr_Addr_MAS5 : std_ulogic_vector(0 to 9) := "0101010011"; +constant Spr_Addr_MAS6 : std_ulogic_vector(0 to 9) := "1001110110"; +constant Spr_Addr_MAS7 : std_ulogic_vector(0 to 9) := "1110110000"; +constant Spr_Addr_MAS8 : std_ulogic_vector(0 to 9) := "0101010101"; +constant Spr_Addr_MAS56_64b : std_ulogic_vector(0 to 9) := "0101011100"; +constant Spr_Addr_MAS81_64b : std_ulogic_vector(0 to 9) := "0101011101"; +constant Spr_Addr_MAS73_64b : std_ulogic_vector(0 to 9) := "0101110100"; +constant Spr_Addr_MAS01_64b : std_ulogic_vector(0 to 9) := "0101110101"; +constant Spr_Addr_MMUCFG : std_ulogic_vector(0 to 9) := "1111110111"; +constant Spr_Addr_MMUCSR0 : std_ulogic_vector(0 to 9) := "1111110100"; +constant Spr_Addr_TLB0CFG : std_ulogic_vector(0 to 9) := "1010110000"; +constant Spr_Addr_TLB0PS : std_ulogic_vector(0 to 9) := "0101011000"; +constant Spr_Addr_LRATCFG : std_ulogic_vector(0 to 9) := "0101010110"; +constant Spr_Addr_LRATPS : std_ulogic_vector(0 to 9) := "0101010111"; +constant Spr_Addr_EPTCFG : std_ulogic_vector(0 to 9) := "0101011110"; +constant Spr_Addr_LPER : std_ulogic_vector(0 to 9) := "0000111000"; +constant Spr_Addr_LPERU : std_ulogic_vector(0 to 9) := "0000111001"; +constant Spr_Data_MMUCFG : std_ulogic_vector(32 to 63) := "00001000010101011000001101000001"; +constant Spr_Data_TLB0CFG : std_ulogic_vector(32 to 63) := "00000100000000001010001000000000"; +constant Spr_Data_TLB0PS : std_ulogic_vector(32 to 63) := "00000000000100000100010001000100"; +constant Spr_Data_LRATCFG : std_ulogic_vector(32 to 63) := "00000000010101000010000000001000"; +constant Spr_Data_LRATPS : std_ulogic_vector(32 to 63) := "01010001010101000100010000000000"; +constant Spr_Data_EPTCFG : std_ulogic_vector(32 to 63) := "00000000000010010001100101000010"; +constant spr_ctl_in_offset : natural := 0; +constant spr_etid_in_offset : natural := spr_ctl_in_offset + spr_ctl_width; +constant spr_addr_in_offset : natural := spr_etid_in_offset + spr_etid_width; +constant spr_data_in_offset : natural := spr_addr_in_offset + spr_addr_width; +constant spr_ctl_int_offset : natural := spr_data_in_offset + spr_data_width; +constant spr_etid_int_offset : natural := spr_ctl_int_offset + spr_ctl_width; +constant spr_addr_int_offset : natural := spr_etid_int_offset + spr_etid_width; +constant spr_data_int_offset : natural := spr_addr_int_offset + spr_addr_width; +constant spr_ctl_out_offset : natural := spr_data_int_offset + spr_data_width; +constant spr_etid_out_offset : natural := spr_ctl_out_offset + spr_ctl_width; +constant spr_addr_out_offset : natural := spr_etid_out_offset + spr_etid_width; +constant spr_data_out_offset : natural := spr_addr_out_offset + spr_addr_width; +constant spr_match_any_mmu_offset : natural := spr_data_out_offset + spr_data_width; +constant spr_match_pid0_offset : natural := spr_match_any_mmu_offset + 1; +constant spr_match_pid1_offset : natural := spr_match_pid0_offset + 1; +constant spr_match_pid2_offset : natural := spr_match_pid1_offset + 1; +constant spr_match_pid3_offset : natural := spr_match_pid2_offset + 1; +constant spr_match_mmucr0_0_offset : natural := spr_match_pid3_offset + 1; +constant spr_match_mmucr0_1_offset : natural := spr_match_mmucr0_0_offset + 1; +constant spr_match_mmucr0_2_offset : natural := spr_match_mmucr0_1_offset + 1; +constant spr_match_mmucr0_3_offset : natural := spr_match_mmucr0_2_offset + 1; +constant spr_match_mmucr1_offset : natural := spr_match_mmucr0_3_offset + 1; +constant spr_match_mmucr2_offset : natural := spr_match_mmucr1_offset + 1; +constant spr_match_mmucr3_0_offset : natural := spr_match_mmucr2_offset + 1; +constant spr_match_mmucr3_1_offset : natural := spr_match_mmucr3_0_offset + 1; +constant spr_match_mmucr3_2_offset : natural := spr_match_mmucr3_1_offset + 1; +constant spr_match_mmucr3_3_offset : natural := spr_match_mmucr3_2_offset + 1; +constant spr_match_lpidr_offset : natural := spr_match_mmucr3_3_offset + 1; +constant pid0_offset : natural := spr_match_lpidr_offset + 1; +constant pid1_offset : natural := pid0_offset + pid_width; +constant pid2_offset : natural := pid1_offset + pid_width; +constant pid3_offset : natural := pid2_offset + pid_width; +constant mmucr0_0_offset : natural := pid3_offset + pid_width; +constant mmucr0_1_offset : natural := mmucr0_0_offset + mmucr0_width; +constant mmucr0_2_offset : natural := mmucr0_1_offset + mmucr0_width; +constant mmucr0_3_offset : natural := mmucr0_2_offset + mmucr0_width; +constant lpidr_offset : natural := mmucr0_3_offset + mmucr0_width; +constant spare_a_offset : natural := lpidr_offset + lpid_width; +constant spr_mmu_act_offset : natural := spare_a_offset + 32; +constant spr_val_act_offset : natural := spr_mmu_act_offset + thdid_width +1; +constant cswitch_offset : natural := spr_val_act_offset + 4; +constant scan_right_0 : natural := cswitch_offset + 4 -1; +constant spr_match_mmucsr0_offset : natural := 0; +constant spr_match_mmucfg_offset : natural := spr_match_mmucsr0_offset + 1; +constant spr_match_tlb0cfg_offset : natural := spr_match_mmucfg_offset + 1; +constant spr_match_tlb0ps_offset : natural := spr_match_tlb0cfg_offset + 1; +constant spr_match_lratcfg_offset : natural := spr_match_tlb0ps_offset + 1; +constant spr_match_lratps_offset : natural := spr_match_lratcfg_offset + 1; +constant spr_match_eptcfg_offset : natural := spr_match_lratps_offset + 1; +constant spr_match_lper_0_offset : natural := spr_match_eptcfg_offset + 1; +constant spr_match_lper_1_offset : natural := spr_match_lper_0_offset + 1; +constant spr_match_lper_2_offset : natural := spr_match_lper_1_offset + 1; +constant spr_match_lper_3_offset : natural := spr_match_lper_2_offset + 1; +constant spr_match_lperu_0_offset : natural := spr_match_lper_3_offset + 1; +constant spr_match_lperu_1_offset : natural := spr_match_lperu_0_offset + 1; +constant spr_match_lperu_2_offset : natural := spr_match_lperu_1_offset + 1; +constant spr_match_lperu_3_offset : natural := spr_match_lperu_2_offset + 1; +constant spr_match_mas0_0_offset : natural := spr_match_lperu_3_offset + 1; +constant spr_match_mas1_0_offset : natural := spr_match_mas0_0_offset + 1; +constant spr_match_mas2_0_offset : natural := spr_match_mas1_0_offset + 1; +constant spr_match_mas2u_0_offset : natural := spr_match_mas2_0_offset + 1; +constant spr_match_mas3_0_offset : natural := spr_match_mas2u_0_offset + 1; +constant spr_match_mas4_0_offset : natural := spr_match_mas3_0_offset + 1; +constant spr_match_mas5_0_offset : natural := spr_match_mas4_0_offset + 1; +constant spr_match_mas6_0_offset : natural := spr_match_mas5_0_offset + 1; +constant spr_match_mas7_0_offset : natural := spr_match_mas6_0_offset + 1; +constant spr_match_mas8_0_offset : natural := spr_match_mas7_0_offset + 1; +constant spr_match_mas01_64b_0_offset : natural := spr_match_mas8_0_offset + 1; +constant spr_match_mas56_64b_0_offset : natural := spr_match_mas01_64b_0_offset + 1; +constant spr_match_mas73_64b_0_offset : natural := spr_match_mas56_64b_0_offset + 1; +constant spr_match_mas81_64b_0_offset : natural := spr_match_mas73_64b_0_offset + 1; +constant spr_match_mas0_1_offset : natural := spr_match_mas81_64b_0_offset + 1; +constant spr_match_mas1_1_offset : natural := spr_match_mas0_1_offset + 1; +constant spr_match_mas2_1_offset : natural := spr_match_mas1_1_offset + 1; +constant spr_match_mas2u_1_offset : natural := spr_match_mas2_1_offset + 1; +constant spr_match_mas3_1_offset : natural := spr_match_mas2u_1_offset + 1; +constant spr_match_mas4_1_offset : natural := spr_match_mas3_1_offset + 1; +constant spr_match_mas5_1_offset : natural := spr_match_mas4_1_offset + 1; +constant spr_match_mas6_1_offset : natural := spr_match_mas5_1_offset + 1; +constant spr_match_mas7_1_offset : natural := spr_match_mas6_1_offset + 1; +constant spr_match_mas8_1_offset : natural := spr_match_mas7_1_offset + 1; +constant spr_match_mas01_64b_1_offset : natural := spr_match_mas8_1_offset + 1; +constant spr_match_mas56_64b_1_offset : natural := spr_match_mas01_64b_1_offset + 1; +constant spr_match_mas73_64b_1_offset : natural := spr_match_mas56_64b_1_offset + 1; +constant spr_match_mas81_64b_1_offset : natural := spr_match_mas73_64b_1_offset + 1; +constant spr_match_mas0_2_offset : natural := spr_match_mas81_64b_1_offset + 1; +constant spr_match_mas1_2_offset : natural := spr_match_mas0_2_offset + 1; +constant spr_match_mas2_2_offset : natural := spr_match_mas1_2_offset + 1; +constant spr_match_mas2u_2_offset : natural := spr_match_mas2_2_offset + 1; +constant spr_match_mas3_2_offset : natural := spr_match_mas2u_2_offset + 1; +constant spr_match_mas4_2_offset : natural := spr_match_mas3_2_offset + 1; +constant spr_match_mas5_2_offset : natural := spr_match_mas4_2_offset + 1; +constant spr_match_mas6_2_offset : natural := spr_match_mas5_2_offset + 1; +constant spr_match_mas7_2_offset : natural := spr_match_mas6_2_offset + 1; +constant spr_match_mas8_2_offset : natural := spr_match_mas7_2_offset + 1; +constant spr_match_mas01_64b_2_offset : natural := spr_match_mas8_2_offset + 1; +constant spr_match_mas56_64b_2_offset : natural := spr_match_mas01_64b_2_offset + 1; +constant spr_match_mas73_64b_2_offset : natural := spr_match_mas56_64b_2_offset + 1; +constant spr_match_mas81_64b_2_offset : natural := spr_match_mas73_64b_2_offset + 1; +constant spr_match_mas0_3_offset : natural := spr_match_mas81_64b_2_offset + 1; +constant spr_match_mas1_3_offset : natural := spr_match_mas0_3_offset + 1; +constant spr_match_mas2_3_offset : natural := spr_match_mas1_3_offset + 1; +constant spr_match_mas2u_3_offset : natural := spr_match_mas2_3_offset + 1; +constant spr_match_mas3_3_offset : natural := spr_match_mas2u_3_offset + 1; +constant spr_match_mas4_3_offset : natural := spr_match_mas3_3_offset + 1; +constant spr_match_mas5_3_offset : natural := spr_match_mas4_3_offset + 1; +constant spr_match_mas6_3_offset : natural := spr_match_mas5_3_offset + 1; +constant spr_match_mas7_3_offset : natural := spr_match_mas6_3_offset + 1; +constant spr_match_mas8_3_offset : natural := spr_match_mas7_3_offset + 1; +constant spr_match_mas01_64b_3_offset : natural := spr_match_mas8_3_offset + 1; +constant spr_match_mas56_64b_3_offset : natural := spr_match_mas01_64b_3_offset + 1; +constant spr_match_mas73_64b_3_offset : natural := spr_match_mas56_64b_3_offset + 1; +constant spr_match_mas81_64b_3_offset : natural := spr_match_mas73_64b_3_offset + 1; +constant spr_match_64b_offset : natural := spr_match_mas81_64b_3_offset + 1; +constant spr_addr_in_clone_offset : natural := spr_match_64b_offset + 1; +constant spr_mas_data_out_offset : natural := spr_addr_in_clone_offset + spr_addr_width; +constant spr_match_any_mas_offset : natural := spr_mas_data_out_offset + spr_data_width; +constant mas0_0_atsel_offset : natural := spr_match_any_mas_offset + 1; +constant mas0_0_esel_offset : natural := mas0_0_atsel_offset + 1; +constant mas0_0_hes_offset : natural := mas0_0_esel_offset + 3; +constant mas0_0_wq_offset : natural := mas0_0_hes_offset + 1; +constant mas1_0_v_offset : natural := mas0_0_wq_offset + 2; +constant mas1_0_iprot_offset : natural := mas1_0_v_offset + 1; +constant mas1_0_tid_offset : natural := mas1_0_iprot_offset + 1; +constant mas1_0_ind_offset : natural := mas1_0_tid_offset + 14; +constant mas1_0_ts_offset : natural := mas1_0_ind_offset + 1; +constant mas1_0_tsize_offset : natural := mas1_0_ts_offset + 1; +constant mas2_0_epn_offset : natural := mas1_0_tsize_offset + 4; +constant mas2_0_wimge_offset : natural := mas2_0_epn_offset + 52+spr_data_width-64; +constant mas3_0_rpnl_offset : natural := mas2_0_wimge_offset + 5; +constant mas3_0_ubits_offset : natural := mas3_0_rpnl_offset + 21; +constant mas3_0_usxwr_offset : natural := mas3_0_ubits_offset + 4; +constant mas5_0_sgs_offset : natural := mas3_0_usxwr_offset + 6; +constant mas5_0_slpid_offset : natural := mas5_0_sgs_offset + 1; +constant mas6_0_spid_offset : natural := mas5_0_slpid_offset + 8; +constant mas6_0_isize_offset : natural := mas6_0_spid_offset + 14; +constant mas6_0_sind_offset : natural := mas6_0_isize_offset + 4; +constant mas6_0_sas_offset : natural := mas6_0_sind_offset + 1; +constant mas7_0_rpnu_offset : natural := mas6_0_sas_offset + 1; +constant mas8_0_tgs_offset : natural := mas7_0_rpnu_offset + 10; +constant mas8_0_vf_offset : natural := mas8_0_tgs_offset + 1; +constant mas8_0_tlpid_offset : natural := mas8_0_vf_offset + 1; +constant mas0_1_atsel_offset : natural := mas8_0_tlpid_offset + 8; +constant mas0_1_esel_offset : natural := mas0_1_atsel_offset + 1; +constant mas0_1_hes_offset : natural := mas0_1_esel_offset + 3; +constant mas0_1_wq_offset : natural := mas0_1_hes_offset + 1; +constant mas1_1_v_offset : natural := mas0_1_wq_offset + 2; +constant mas1_1_iprot_offset : natural := mas1_1_v_offset + 1; +constant mas1_1_tid_offset : natural := mas1_1_iprot_offset + 1; +constant mas1_1_ind_offset : natural := mas1_1_tid_offset + 14; +constant mas1_1_ts_offset : natural := mas1_1_ind_offset + 1; +constant mas1_1_tsize_offset : natural := mas1_1_ts_offset + 1; +constant mas2_1_epn_offset : natural := mas1_1_tsize_offset + 4; +constant mas2_1_wimge_offset : natural := mas2_1_epn_offset + 52+spr_data_width-64; +constant mas3_1_rpnl_offset : natural := mas2_1_wimge_offset + 5; +constant mas3_1_ubits_offset : natural := mas3_1_rpnl_offset + 21; +constant mas3_1_usxwr_offset : natural := mas3_1_ubits_offset + 4; +constant mas5_1_sgs_offset : natural := mas3_1_usxwr_offset + 6; +constant mas5_1_slpid_offset : natural := mas5_1_sgs_offset + 1; +constant mas6_1_spid_offset : natural := mas5_1_slpid_offset + 8; +constant mas6_1_isize_offset : natural := mas6_1_spid_offset + 14; +constant mas6_1_sind_offset : natural := mas6_1_isize_offset + 4; +constant mas6_1_sas_offset : natural := mas6_1_sind_offset + 1; +constant mas7_1_rpnu_offset : natural := mas6_1_sas_offset + 1; +constant mas8_1_tgs_offset : natural := mas7_1_rpnu_offset + 10; +constant mas8_1_vf_offset : natural := mas8_1_tgs_offset + 1; +constant mas8_1_tlpid_offset : natural := mas8_1_vf_offset + 1; +constant mas0_2_atsel_offset : natural := mas8_1_tlpid_offset + 8; +constant mas0_2_esel_offset : natural := mas0_2_atsel_offset + 1; +constant mas0_2_hes_offset : natural := mas0_2_esel_offset + 3; +constant mas0_2_wq_offset : natural := mas0_2_hes_offset + 1; +constant mas1_2_v_offset : natural := mas0_2_wq_offset + 2; +constant mas1_2_iprot_offset : natural := mas1_2_v_offset + 1; +constant mas1_2_tid_offset : natural := mas1_2_iprot_offset + 1; +constant mas1_2_ind_offset : natural := mas1_2_tid_offset + 14; +constant mas1_2_ts_offset : natural := mas1_2_ind_offset + 1; +constant mas1_2_tsize_offset : natural := mas1_2_ts_offset + 1; +constant mas2_2_epn_offset : natural := mas1_2_tsize_offset + 4; +constant mas2_2_wimge_offset : natural := mas2_2_epn_offset + 52+spr_data_width-64; +constant mas3_2_rpnl_offset : natural := mas2_2_wimge_offset + 5; +constant mas3_2_ubits_offset : natural := mas3_2_rpnl_offset + 21; +constant mas3_2_usxwr_offset : natural := mas3_2_ubits_offset + 4; +constant mas5_2_sgs_offset : natural := mas3_2_usxwr_offset + 6; +constant mas5_2_slpid_offset : natural := mas5_2_sgs_offset + 1; +constant mas6_2_spid_offset : natural := mas5_2_slpid_offset + 8; +constant mas6_2_isize_offset : natural := mas6_2_spid_offset + 14; +constant mas6_2_sind_offset : natural := mas6_2_isize_offset + 4; +constant mas6_2_sas_offset : natural := mas6_2_sind_offset + 1; +constant mas7_2_rpnu_offset : natural := mas6_2_sas_offset + 1; +constant mas8_2_tgs_offset : natural := mas7_2_rpnu_offset + 10; +constant mas8_2_vf_offset : natural := mas8_2_tgs_offset + 1; +constant mas8_2_tlpid_offset : natural := mas8_2_vf_offset + 1; +constant mas0_3_atsel_offset : natural := mas8_2_tlpid_offset + 8; +constant mas0_3_esel_offset : natural := mas0_3_atsel_offset + 1; +constant mas0_3_hes_offset : natural := mas0_3_esel_offset + 3; +constant mas0_3_wq_offset : natural := mas0_3_hes_offset + 1; +constant mas1_3_v_offset : natural := mas0_3_wq_offset + 2; +constant mas1_3_iprot_offset : natural := mas1_3_v_offset + 1; +constant mas1_3_tid_offset : natural := mas1_3_iprot_offset + 1; +constant mas1_3_ind_offset : natural := mas1_3_tid_offset + 14; +constant mas1_3_ts_offset : natural := mas1_3_ind_offset + 1; +constant mas1_3_tsize_offset : natural := mas1_3_ts_offset + 1; +constant mas2_3_epn_offset : natural := mas1_3_tsize_offset + 4; +constant mas2_3_wimge_offset : natural := mas2_3_epn_offset + 52+spr_data_width-64; +constant mas3_3_rpnl_offset : natural := mas2_3_wimge_offset + 5; +constant mas3_3_ubits_offset : natural := mas3_3_rpnl_offset + 21; +constant mas3_3_usxwr_offset : natural := mas3_3_ubits_offset + 4; +constant mas5_3_sgs_offset : natural := mas3_3_usxwr_offset + 6; +constant mas5_3_slpid_offset : natural := mas5_3_sgs_offset + 1; +constant mas6_3_spid_offset : natural := mas5_3_slpid_offset + 8; +constant mas6_3_isize_offset : natural := mas6_3_spid_offset + 14; +constant mas6_3_sind_offset : natural := mas6_3_isize_offset + 4; +constant mas6_3_sas_offset : natural := mas6_3_sind_offset + 1; +constant mas7_3_rpnu_offset : natural := mas6_3_sas_offset + 1; +constant mas8_3_tgs_offset : natural := mas7_3_rpnu_offset + 10; +constant mas8_3_vf_offset : natural := mas8_3_tgs_offset + 1; +constant mas8_3_tlpid_offset : natural := mas8_3_vf_offset + 1; +constant mmucsr0_tlb0fi_offset : natural := mas8_3_tlpid_offset + 8; +constant scan_right_a : natural := mmucsr0_tlb0fi_offset + 1; +constant lper_0_alpn_offset : natural := scan_right_a; +constant lper_0_lps_offset : natural := lper_0_alpn_offset + real_addr_width-12; +constant lper_1_alpn_offset : natural := lper_0_lps_offset + 4; +constant lper_1_lps_offset : natural := lper_1_alpn_offset + real_addr_width-12; +constant lper_2_alpn_offset : natural := lper_1_lps_offset + 4; +constant lper_2_lps_offset : natural := lper_2_alpn_offset + real_addr_width-12; +constant lper_3_alpn_offset : natural := lper_2_lps_offset + 4; +constant lper_3_lps_offset : natural := lper_3_alpn_offset + real_addr_width-12; +constant spare_b_offset : natural := lper_3_lps_offset + 4; +constant cat_emf_act_offset : natural := spare_b_offset + 64; +constant scan_right_1 : natural := cat_emf_act_offset + thdid_width -1; +constant mmucfg_offset : natural := 0; +constant tlb0cfg_offset : natural := mmucfg_offset + 2; +constant mmucr1_offset : natural := tlb0cfg_offset + 3; +constant mmucr2_offset : natural := mmucr1_offset + mmucr1_width; +constant mmucr3_0_offset : natural := mmucr2_offset + mmucr2_width; +constant mmucr3_1_offset : natural := mmucr3_0_offset + mmucr3_width; +constant mmucr3_2_offset : natural := mmucr3_1_offset + mmucr3_width; +constant mmucr3_3_offset : natural := mmucr3_2_offset + mmucr3_width; +constant mas4_0_indd_offset : natural := mmucr3_3_offset + mmucr3_width; +constant mas4_0_tsized_offset : natural := mas4_0_indd_offset + 1; +constant mas4_0_wimged_offset : natural := mas4_0_tsized_offset + 4; +constant mas4_1_indd_offset : natural := mas4_0_wimged_offset + 5; +constant mas4_1_tsized_offset : natural := mas4_1_indd_offset + 1; +constant mas4_1_wimged_offset : natural := mas4_1_tsized_offset + 4; +constant mas4_2_indd_offset : natural := mas4_1_wimged_offset + 5; +constant mas4_2_tsized_offset : natural := mas4_2_indd_offset + 1; +constant mas4_2_wimged_offset : natural := mas4_2_tsized_offset + 4; +constant mas4_3_indd_offset : natural := mas4_2_wimged_offset + 5; +constant mas4_3_tsized_offset : natural := mas4_3_indd_offset + 1; +constant mas4_3_wimged_offset : natural := mas4_3_tsized_offset + 4; +constant bcfg_spare_offset : natural := mas4_3_wimged_offset + 5; +constant boot_scan_right : natural := bcfg_spare_offset + 16 - 1; +signal spr_match_any_mmu, spr_match_any_mmu_q : std_ulogic; +signal spr_match_pid0, spr_match_pid0_q : std_ulogic; +signal spr_match_pid1, spr_match_pid1_q : std_ulogic; +signal spr_match_pid2, spr_match_pid2_q : std_ulogic; +signal spr_match_pid3, spr_match_pid3_q : std_ulogic; +signal spr_match_mmucr0_0, spr_match_mmucr0_0_q : std_ulogic; +signal spr_match_mmucr0_1, spr_match_mmucr0_1_q : std_ulogic; +signal spr_match_mmucr0_2, spr_match_mmucr0_2_q : std_ulogic; +signal spr_match_mmucr0_3, spr_match_mmucr0_3_q : std_ulogic; +signal spr_match_mmucr1, spr_match_mmucr1_q : std_ulogic; +signal spr_match_mmucr2, spr_match_mmucr2_q : std_ulogic; +signal spr_match_mmucr3_0, spr_match_mmucr3_0_q : std_ulogic; +signal spr_match_mmucr3_1, spr_match_mmucr3_1_q : std_ulogic; +signal spr_match_mmucr3_2, spr_match_mmucr3_2_q : std_ulogic; +signal spr_match_mmucr3_3, spr_match_mmucr3_3_q : std_ulogic; +signal spr_match_lpidr, spr_match_lpidr_q : std_ulogic; +signal spr_match_mmucsr0, spr_match_mmucsr0_q : std_ulogic; +signal spr_match_mmucfg, spr_match_mmucfg_q : std_ulogic; +signal spr_match_tlb0cfg, spr_match_tlb0cfg_q : std_ulogic; +signal spr_match_tlb0ps, spr_match_tlb0ps_q : std_ulogic; +signal spr_match_lratcfg, spr_match_lratcfg_q : std_ulogic; +signal spr_match_lratps, spr_match_lratps_q : std_ulogic; +signal spr_match_eptcfg, spr_match_eptcfg_q : std_ulogic; +signal spr_match_lper_0, spr_match_lper_0_q : std_ulogic; +signal spr_match_lper_1, spr_match_lper_1_q : std_ulogic; +signal spr_match_lper_2, spr_match_lper_2_q : std_ulogic; +signal spr_match_lper_3, spr_match_lper_3_q : std_ulogic; +signal spr_match_lperu_0, spr_match_lperu_0_q : std_ulogic; +signal spr_match_lperu_1, spr_match_lperu_1_q : std_ulogic; +signal spr_match_lperu_2, spr_match_lperu_2_q : std_ulogic; +signal spr_match_lperu_3, spr_match_lperu_3_q : std_ulogic; +signal spr_match_mas0_0, spr_match_mas0_0_q : std_ulogic; +signal spr_match_mas1_0, spr_match_mas1_0_q : std_ulogic; +signal spr_match_mas2_0, spr_match_mas2_0_q : std_ulogic; +signal spr_match_mas2u_0, spr_match_mas2u_0_q : std_ulogic; +signal spr_match_mas3_0, spr_match_mas3_0_q : std_ulogic; +signal spr_match_mas4_0, spr_match_mas4_0_q : std_ulogic; +signal spr_match_mas5_0, spr_match_mas5_0_q : std_ulogic; +signal spr_match_mas6_0, spr_match_mas6_0_q : std_ulogic; +signal spr_match_mas7_0, spr_match_mas7_0_q : std_ulogic; +signal spr_match_mas8_0, spr_match_mas8_0_q : std_ulogic; +signal spr_match_mas01_64b_0, spr_match_mas01_64b_0_q : std_ulogic; +signal spr_match_mas56_64b_0, spr_match_mas56_64b_0_q : std_ulogic; +signal spr_match_mas73_64b_0, spr_match_mas73_64b_0_q : std_ulogic; +signal spr_match_mas81_64b_0, spr_match_mas81_64b_0_q : std_ulogic; +signal spr_match_mas0_1, spr_match_mas0_1_q : std_ulogic; +signal spr_match_mas1_1, spr_match_mas1_1_q : std_ulogic; +signal spr_match_mas2_1, spr_match_mas2_1_q : std_ulogic; +signal spr_match_mas2u_1, spr_match_mas2u_1_q : std_ulogic; +signal spr_match_mas3_1, spr_match_mas3_1_q : std_ulogic; +signal spr_match_mas4_1, spr_match_mas4_1_q : std_ulogic; +signal spr_match_mas5_1, spr_match_mas5_1_q : std_ulogic; +signal spr_match_mas6_1, spr_match_mas6_1_q : std_ulogic; +signal spr_match_mas7_1, spr_match_mas7_1_q : std_ulogic; +signal spr_match_mas8_1, spr_match_mas8_1_q : std_ulogic; +signal spr_match_mas01_64b_1, spr_match_mas01_64b_1_q : std_ulogic; +signal spr_match_mas56_64b_1, spr_match_mas56_64b_1_q : std_ulogic; +signal spr_match_mas73_64b_1, spr_match_mas73_64b_1_q : std_ulogic; +signal spr_match_mas81_64b_1, spr_match_mas81_64b_1_q : std_ulogic; +signal spr_match_mas0_2, spr_match_mas0_2_q : std_ulogic; +signal spr_match_mas1_2, spr_match_mas1_2_q : std_ulogic; +signal spr_match_mas2_2, spr_match_mas2_2_q : std_ulogic; +signal spr_match_mas2u_2, spr_match_mas2u_2_q : std_ulogic; +signal spr_match_mas3_2, spr_match_mas3_2_q : std_ulogic; +signal spr_match_mas4_2, spr_match_mas4_2_q : std_ulogic; +signal spr_match_mas5_2, spr_match_mas5_2_q : std_ulogic; +signal spr_match_mas6_2, spr_match_mas6_2_q : std_ulogic; +signal spr_match_mas7_2, spr_match_mas7_2_q : std_ulogic; +signal spr_match_mas8_2, spr_match_mas8_2_q : std_ulogic; +signal spr_match_mas01_64b_2, spr_match_mas01_64b_2_q : std_ulogic; +signal spr_match_mas56_64b_2, spr_match_mas56_64b_2_q : std_ulogic; +signal spr_match_mas73_64b_2, spr_match_mas73_64b_2_q : std_ulogic; +signal spr_match_mas81_64b_2, spr_match_mas81_64b_2_q : std_ulogic; +signal spr_match_mas0_3, spr_match_mas0_3_q : std_ulogic; +signal spr_match_mas1_3, spr_match_mas1_3_q : std_ulogic; +signal spr_match_mas2_3, spr_match_mas2_3_q : std_ulogic; +signal spr_match_mas2u_3, spr_match_mas2u_3_q : std_ulogic; +signal spr_match_mas3_3, spr_match_mas3_3_q : std_ulogic; +signal spr_match_mas4_3, spr_match_mas4_3_q : std_ulogic; +signal spr_match_mas5_3, spr_match_mas5_3_q : std_ulogic; +signal spr_match_mas6_3, spr_match_mas6_3_q : std_ulogic; +signal spr_match_mas7_3, spr_match_mas7_3_q : std_ulogic; +signal spr_match_mas8_3, spr_match_mas8_3_q : std_ulogic; +signal spr_match_mas01_64b_3, spr_match_mas01_64b_3_q : std_ulogic; +signal spr_match_mas56_64b_3, spr_match_mas56_64b_3_q : std_ulogic; +signal spr_match_mas73_64b_3, spr_match_mas73_64b_3_q : std_ulogic; +signal spr_match_mas81_64b_3, spr_match_mas81_64b_3_q : std_ulogic; +signal spr_mas_data_out, spr_mas_data_out_q : std_ulogic_vector(64-spr_data_width to 63); +signal spr_match_any_mas, spr_match_any_mas_q : std_ulogic; +signal spr_match_mas2_64b : std_ulogic; +signal spr_match_mas01_64b : std_ulogic; +signal spr_match_mas56_64b : std_ulogic; +signal spr_match_mas73_64b : std_ulogic; +signal spr_match_mas81_64b : std_ulogic; +signal spr_match_64b, spr_match_64b_q : std_ulogic; +signal spr_ctl_in_d, spr_ctl_in_q : std_ulogic_vector(0 to spr_ctl_width-1); +signal spr_etid_in_d, spr_etid_in_q : std_ulogic_vector(0 to spr_etid_width-1); +signal spr_addr_in_d, spr_addr_in_q : std_ulogic_vector(0 to spr_addr_width-1); +signal spr_data_in_d, spr_data_in_q : std_ulogic_vector(64-spr_data_width to 63); +signal spr_addr_in_clone_d, spr_addr_in_clone_q : std_ulogic_vector(0 to spr_addr_width-1); +signal spr_ctl_int_d, spr_ctl_int_q : std_ulogic_vector(0 to spr_ctl_width-1); +signal spr_etid_int_d, spr_etid_int_q : std_ulogic_vector(0 to spr_etid_width-1); +signal spr_addr_int_d, spr_addr_int_q : std_ulogic_vector(0 to spr_addr_width-1); +signal spr_data_int_d, spr_data_int_q : std_ulogic_vector(64-spr_data_width to 63); +signal spr_ctl_out_d, spr_ctl_out_q : std_ulogic_vector(0 to spr_ctl_width-1); +signal spr_etid_out_d, spr_etid_out_q : std_ulogic_vector(0 to spr_etid_width-1); +signal spr_addr_out_d, spr_addr_out_q : std_ulogic_vector(0 to spr_addr_width-1); +signal spr_data_out_d, spr_data_out_q : std_ulogic_vector(64-spr_data_width to 63); +signal pid0_d, pid0_q : std_ulogic_vector(0 to pid_width-1); +signal mmucr0_0_d, mmucr0_0_q : std_ulogic_vector(0 to mmucr0_width-1); +signal mmucr3_0_d, mmucr3_0_q : std_ulogic_vector(64-mmucr3_width to 63); +signal pid1_d, pid1_q : std_ulogic_vector(0 to pid_width-1); +signal mmucr0_1_d, mmucr0_1_q : std_ulogic_vector(0 to mmucr0_width-1); +signal mmucr3_1_d, mmucr3_1_q : std_ulogic_vector(64-mmucr3_width to 63); +signal pid2_d, pid2_q : std_ulogic_vector(0 to pid_width-1); +signal mmucr0_2_d, mmucr0_2_q : std_ulogic_vector(0 to mmucr0_width-1); +signal mmucr3_2_d, mmucr3_2_q : std_ulogic_vector(64-mmucr3_width to 63); +signal pid3_d, pid3_q : std_ulogic_vector(0 to pid_width-1); +signal mmucr0_3_d, mmucr0_3_q : std_ulogic_vector(0 to mmucr0_width-1); +signal mmucr3_3_d, mmucr3_3_q : std_ulogic_vector(64-mmucr3_width to 63); +signal mmucr1_d, mmucr1_q : std_ulogic_vector(0 to mmucr1_width-1); +signal mmucr2_d, mmucr2_q : std_ulogic_vector(0 to mmucr2_width-1); +signal lpidr_d, lpidr_q : std_ulogic_vector(0 to lpid_width-1); +signal mas0_0_atsel_d, mas0_0_atsel_q : std_ulogic; +signal mas0_0_esel_d, mas0_0_esel_q : std_ulogic_vector(0 to 2); +signal mas0_0_hes_d, mas0_0_hes_q : std_ulogic; +signal mas0_0_wq_d, mas0_0_wq_q : std_ulogic_vector(0 to 1); +signal mas1_0_v_d, mas1_0_v_q : std_ulogic; +signal mas1_0_iprot_d, mas1_0_iprot_q : std_ulogic; +signal mas1_0_tid_d, mas1_0_tid_q : std_ulogic_vector(0 to 13); +signal mas1_0_ind_d, mas1_0_ind_q : std_ulogic; +signal mas1_0_ts_d, mas1_0_ts_q : std_ulogic; +signal mas1_0_tsize_d, mas1_0_tsize_q : std_ulogic_vector(0 to 3); +signal mas2_0_epn_d, mas2_0_epn_q : std_ulogic_vector(64-spr_data_width to 51); +signal mas2_0_wimge_d, mas2_0_wimge_q : std_ulogic_vector(0 to 4); +signal mas3_0_rpnl_d, mas3_0_rpnl_q : std_ulogic_vector(32 to 52); +signal mas3_0_ubits_d, mas3_0_ubits_q : std_ulogic_vector(0 to 3); +signal mas3_0_usxwr_d, mas3_0_usxwr_q : std_ulogic_vector(0 to 5); +signal mas4_0_indd_d, mas4_0_indd_q : std_ulogic; +signal mas4_0_tsized_d, mas4_0_tsized_q : std_ulogic_vector(0 to 3); +signal mas4_0_wimged_d, mas4_0_wimged_q : std_ulogic_vector(0 to 4); +signal mas5_0_sgs_d, mas5_0_sgs_q : std_ulogic; +signal mas5_0_slpid_d, mas5_0_slpid_q : std_ulogic_vector(0 to 7); +signal mas6_0_spid_d, mas6_0_spid_q : std_ulogic_vector(0 to 13); +signal mas6_0_isize_d, mas6_0_isize_q : std_ulogic_vector(0 to 3); +signal mas6_0_sind_d, mas6_0_sind_q : std_ulogic; +signal mas6_0_sas_d, mas6_0_sas_q : std_ulogic; +signal mas7_0_rpnu_d, mas7_0_rpnu_q : std_ulogic_vector(22 to 31); +signal mas8_0_tgs_d, mas8_0_tgs_q : std_ulogic; +signal mas8_0_vf_d, mas8_0_vf_q : std_ulogic; +signal mas8_0_tlpid_d, mas8_0_tlpid_q : std_ulogic_vector(0 to 7); +signal mas0_1_atsel_d, mas0_1_atsel_q : std_ulogic; +signal mas0_1_esel_d, mas0_1_esel_q : std_ulogic_vector(0 to 2); +signal mas0_1_hes_d, mas0_1_hes_q : std_ulogic; +signal mas0_1_wq_d, mas0_1_wq_q : std_ulogic_vector(0 to 1); +signal mas1_1_v_d, mas1_1_v_q : std_ulogic; +signal mas1_1_iprot_d, mas1_1_iprot_q : std_ulogic; +signal mas1_1_tid_d, mas1_1_tid_q : std_ulogic_vector(0 to 13); +signal mas1_1_ind_d, mas1_1_ind_q : std_ulogic; +signal mas1_1_ts_d, mas1_1_ts_q : std_ulogic; +signal mas1_1_tsize_d, mas1_1_tsize_q : std_ulogic_vector(0 to 3); +signal mas2_1_epn_d, mas2_1_epn_q : std_ulogic_vector(64-spr_data_width to 51); +signal mas2_1_wimge_d, mas2_1_wimge_q : std_ulogic_vector(0 to 4); +signal mas3_1_rpnl_d, mas3_1_rpnl_q : std_ulogic_vector(32 to 52); +signal mas3_1_ubits_d, mas3_1_ubits_q : std_ulogic_vector(0 to 3); +signal mas3_1_usxwr_d, mas3_1_usxwr_q : std_ulogic_vector(0 to 5); +signal mas4_1_indd_d, mas4_1_indd_q : std_ulogic; +signal mas4_1_tsized_d, mas4_1_tsized_q : std_ulogic_vector(0 to 3); +signal mas4_1_wimged_d, mas4_1_wimged_q : std_ulogic_vector(0 to 4); +signal mas5_1_sgs_d, mas5_1_sgs_q : std_ulogic; +signal mas5_1_slpid_d, mas5_1_slpid_q : std_ulogic_vector(0 to 7); +signal mas6_1_spid_d, mas6_1_spid_q : std_ulogic_vector(0 to 13); +signal mas6_1_isize_d, mas6_1_isize_q : std_ulogic_vector(0 to 3); +signal mas6_1_sind_d, mas6_1_sind_q : std_ulogic; +signal mas6_1_sas_d, mas6_1_sas_q : std_ulogic; +signal mas7_1_rpnu_d, mas7_1_rpnu_q : std_ulogic_vector(22 to 31); +signal mas8_1_tgs_d, mas8_1_tgs_q : std_ulogic; +signal mas8_1_vf_d, mas8_1_vf_q : std_ulogic; +signal mas8_1_tlpid_d, mas8_1_tlpid_q : std_ulogic_vector(0 to 7); +signal mas0_2_atsel_d, mas0_2_atsel_q : std_ulogic; +signal mas0_2_esel_d, mas0_2_esel_q : std_ulogic_vector(0 to 2); +signal mas0_2_hes_d, mas0_2_hes_q : std_ulogic; +signal mas0_2_wq_d, mas0_2_wq_q : std_ulogic_vector(0 to 1); +signal mas1_2_v_d, mas1_2_v_q : std_ulogic; +signal mas1_2_iprot_d, mas1_2_iprot_q : std_ulogic; +signal mas1_2_tid_d, mas1_2_tid_q : std_ulogic_vector(0 to 13); +signal mas1_2_ind_d, mas1_2_ind_q : std_ulogic; +signal mas1_2_ts_d, mas1_2_ts_q : std_ulogic; +signal mas1_2_tsize_d, mas1_2_tsize_q : std_ulogic_vector(0 to 3); +signal mas2_2_epn_d, mas2_2_epn_q : std_ulogic_vector(64-spr_data_width to 51); +signal mas2_2_wimge_d, mas2_2_wimge_q : std_ulogic_vector(0 to 4); +signal mas3_2_rpnl_d, mas3_2_rpnl_q : std_ulogic_vector(32 to 52); +signal mas3_2_ubits_d, mas3_2_ubits_q : std_ulogic_vector(0 to 3); +signal mas3_2_usxwr_d, mas3_2_usxwr_q : std_ulogic_vector(0 to 5); +signal mas4_2_indd_d, mas4_2_indd_q : std_ulogic; +signal mas4_2_tsized_d, mas4_2_tsized_q : std_ulogic_vector(0 to 3); +signal mas4_2_wimged_d, mas4_2_wimged_q : std_ulogic_vector(0 to 4); +signal mas5_2_sgs_d, mas5_2_sgs_q : std_ulogic; +signal mas5_2_slpid_d, mas5_2_slpid_q : std_ulogic_vector(0 to 7); +signal mas6_2_spid_d, mas6_2_spid_q : std_ulogic_vector(0 to 13); +signal mas6_2_isize_d, mas6_2_isize_q : std_ulogic_vector(0 to 3); +signal mas6_2_sind_d, mas6_2_sind_q : std_ulogic; +signal mas6_2_sas_d, mas6_2_sas_q : std_ulogic; +signal mas7_2_rpnu_d, mas7_2_rpnu_q : std_ulogic_vector(22 to 31); +signal mas8_2_tgs_d, mas8_2_tgs_q : std_ulogic; +signal mas8_2_vf_d, mas8_2_vf_q : std_ulogic; +signal mas8_2_tlpid_d, mas8_2_tlpid_q : std_ulogic_vector(0 to 7); +signal mas0_3_atsel_d, mas0_3_atsel_q : std_ulogic; +signal mas0_3_esel_d, mas0_3_esel_q : std_ulogic_vector(0 to 2); +signal mas0_3_hes_d, mas0_3_hes_q : std_ulogic; +signal mas0_3_wq_d, mas0_3_wq_q : std_ulogic_vector(0 to 1); +signal mas1_3_v_d, mas1_3_v_q : std_ulogic; +signal mas1_3_iprot_d, mas1_3_iprot_q : std_ulogic; +signal mas1_3_tid_d, mas1_3_tid_q : std_ulogic_vector(0 to 13); +signal mas1_3_ind_d, mas1_3_ind_q : std_ulogic; +signal mas1_3_ts_d, mas1_3_ts_q : std_ulogic; +signal mas1_3_tsize_d, mas1_3_tsize_q : std_ulogic_vector(0 to 3); +signal mas2_3_epn_d, mas2_3_epn_q : std_ulogic_vector(64-spr_data_width to 51); +signal mas2_3_wimge_d, mas2_3_wimge_q : std_ulogic_vector(0 to 4); +signal mas3_3_rpnl_d, mas3_3_rpnl_q : std_ulogic_vector(32 to 52); +signal mas3_3_ubits_d, mas3_3_ubits_q : std_ulogic_vector(0 to 3); +signal mas3_3_usxwr_d, mas3_3_usxwr_q : std_ulogic_vector(0 to 5); +signal mas4_3_indd_d, mas4_3_indd_q : std_ulogic; +signal mas4_3_tsized_d, mas4_3_tsized_q : std_ulogic_vector(0 to 3); +signal mas4_3_wimged_d, mas4_3_wimged_q : std_ulogic_vector(0 to 4); +signal mas5_3_sgs_d, mas5_3_sgs_q : std_ulogic; +signal mas5_3_slpid_d, mas5_3_slpid_q : std_ulogic_vector(0 to 7); +signal mas6_3_spid_d, mas6_3_spid_q : std_ulogic_vector(0 to 13); +signal mas6_3_isize_d, mas6_3_isize_q : std_ulogic_vector(0 to 3); +signal mas6_3_sind_d, mas6_3_sind_q : std_ulogic; +signal mas6_3_sas_d, mas6_3_sas_q : std_ulogic; +signal mas7_3_rpnu_d, mas7_3_rpnu_q : std_ulogic_vector(22 to 31); +signal mas8_3_tgs_d, mas8_3_tgs_q : std_ulogic; +signal mas8_3_vf_d, mas8_3_vf_q : std_ulogic; +signal mas8_3_tlpid_d, mas8_3_tlpid_q : std_ulogic_vector(0 to 7); +signal mmucsr0_tlb0fi_d, mmucsr0_tlb0fi_q : std_ulogic; +signal lper_0_alpn_d, lper_0_alpn_q : std_ulogic_vector(64-real_addr_width to 51); +signal lper_0_lps_d, lper_0_lps_q : std_ulogic_vector(60 to 63); +signal lper_1_alpn_d, lper_1_alpn_q : std_ulogic_vector(64-real_addr_width to 51); +signal lper_1_lps_d, lper_1_lps_q : std_ulogic_vector(60 to 63); +signal lper_2_alpn_d, lper_2_alpn_q : std_ulogic_vector(64-real_addr_width to 51); +signal lper_2_lps_d, lper_2_lps_q : std_ulogic_vector(60 to 63); +signal lper_3_alpn_d, lper_3_alpn_q : std_ulogic_vector(64-real_addr_width to 51); +signal lper_3_lps_d, lper_3_lps_q : std_ulogic_vector(60 to 63); +signal iu_mm_ierat_mmucr0_q : std_ulogic_vector(0 to 17); +signal iu_mm_ierat_mmucr0_we_q : std_ulogic_vector(0 to thdid_width-1); +signal iu_mm_ierat_mmucr1_q : std_ulogic_vector(0 to 3); +signal iu_mm_ierat_mmucr1_we_q : std_ulogic; +signal xu_mm_derat_mmucr0_q : std_ulogic_vector(0 to 17); +signal xu_mm_derat_mmucr0_we_q : std_ulogic_vector(0 to thdid_width-1); +signal xu_mm_derat_mmucr1_q : std_ulogic_vector(0 to 4); +signal xu_mm_derat_mmucr1_we_q : std_ulogic; +signal spare_a_q : std_ulogic_vector(0 to 31); +signal spare_b_q : std_ulogic_vector(0 to 63); +signal unused_dc : std_ulogic_vector(0 to 13); +-- synopsys translate_off +-- synopsys translate_on +signal pc_sg_1 : std_ulogic; +signal pc_sg_0 : std_ulogic; +signal pc_fce_1 : std_ulogic; +signal pc_fce_0 : std_ulogic; +signal pc_func_sl_thold_1 : std_ulogic; +signal pc_func_sl_thold_0 : std_ulogic; +signal pc_func_sl_thold_0_b : std_ulogic; +signal pc_func_slp_sl_thold_1 : std_ulogic; +signal pc_func_slp_sl_thold_0 : std_ulogic; +signal pc_func_slp_sl_thold_0_b : std_ulogic; +signal pc_func_sl_force : std_ulogic; +signal pc_func_slp_sl_force : std_ulogic; +signal pc_cfg_sl_thold_1 : std_ulogic; +signal pc_cfg_sl_thold_0 : std_ulogic; +signal pc_cfg_sl_thold_0_b : std_ulogic; +signal pc_cfg_slp_sl_thold_1 : std_ulogic; +signal pc_cfg_slp_sl_thold_0 : std_ulogic; +signal pc_cfg_slp_sl_thold_0_b : std_ulogic; +signal pc_cfg_sl_force : std_ulogic; +signal pc_cfg_slp_sl_force : std_ulogic; +signal pc_func_slp_nsl_thold_1 : std_ulogic; +signal pc_func_slp_nsl_thold_0 : std_ulogic; +signal pc_func_slp_nsl_thold_0_b : std_ulogic; +signal pc_func_slp_nsl_force : std_ulogic; +signal lcb_dclk : std_ulogic; +signal lcb_lclk : clk_logic; +signal siv_0 : std_ulogic_vector(0 to scan_right_0); +signal sov_0 : std_ulogic_vector(0 to scan_right_0); +signal siv_1 : std_ulogic_vector(0 to scan_right_1); +signal sov_1 : std_ulogic_vector(0 to scan_right_1); +signal bsiv : std_ulogic_vector(0 to boot_scan_right); +signal bsov : std_ulogic_vector(0 to boot_scan_right); +signal mmucfg_q, mmucfg_q_b : std_ulogic_vector(47 to 48); +signal tlb0cfg_q, tlb0cfg_q_b : std_ulogic_vector(45 to 47); +signal bcfg_spare_q, bcfg_spare_q_b : std_ulogic_vector(0 to 15); +signal cat_emf_act_d, cat_emf_act_q : std_ulogic_vector(0 to thdid_width-1); +signal spr_mmu_act_d, spr_mmu_act_q : std_ulogic_vector(0 to thdid_width); +signal spr_val_act_d, spr_val_act_q : std_ulogic_vector(0 to 3); +signal spr_val_act, spr_match_act, spr_match_mas_act, spr_mas_data_out_act : std_ulogic; +signal cswitch_q : std_ulogic_vector(0 to 3); +signal tidn : std_ulogic; +signal tiup : std_ulogic; +begin +tidn <= '0'; +tiup <= '1'; +cat_emf_act_d(0) <= (spr_match_any_mmu and Eq(spr_etid_in_q, "00")) or mmucr2_act_override(6) or (tlb_delayed_act(29+0) and xu_mm_ccr2_notlb_b); +spr_mmu_act_d(0) <= (spr_match_any_mmu and Eq(spr_etid_in_q, "00")) or mmucr2_act_override(5); +cat_emf_act_d(1) <= (spr_match_any_mmu and Eq(spr_etid_in_q, "01")) or mmucr2_act_override(6) or (tlb_delayed_act(29+1) and xu_mm_ccr2_notlb_b); +spr_mmu_act_d(1) <= (spr_match_any_mmu and Eq(spr_etid_in_q, "01")) or mmucr2_act_override(5); +cat_emf_act_d(2) <= (spr_match_any_mmu and Eq(spr_etid_in_q, "10")) or mmucr2_act_override(6) or (tlb_delayed_act(29+2) and xu_mm_ccr2_notlb_b); +spr_mmu_act_d(2) <= (spr_match_any_mmu and Eq(spr_etid_in_q, "10")) or mmucr2_act_override(5); +cat_emf_act_d(3) <= (spr_match_any_mmu and Eq(spr_etid_in_q, "11")) or mmucr2_act_override(6) or (tlb_delayed_act(29+3) and xu_mm_ccr2_notlb_b); +spr_mmu_act_d(3) <= (spr_match_any_mmu and Eq(spr_etid_in_q, "11")) or mmucr2_act_override(5); +spr_mmu_act_d(thdid_width) <= spr_match_any_mmu or mmucr2_act_override(5); +spr_val_act_d(0) <= xu_mm_slowspr_val; +spr_val_act_d(1) <= spr_val_act_q(0); +spr_val_act_d(2) <= spr_val_act_q(1); +spr_val_act_d(3) <= spr_val_act_q(2); +spr_val_act <= spr_val_act_q(0) or spr_val_act_q(1) or spr_val_act_q(2) or spr_val_act_q(3) or mmucr2_act_override(5); +spr_match_act <= spr_val_act_q(0) or spr_val_act_q(1) or mmucr2_act_override(5); +spr_match_mas_act <= spr_val_act_q(0) or spr_val_act_q(1) or mmucr2_act_override(6); +spr_mas_data_out_act <= spr_val_act_q(0) or mmucr2_act_override(6); +spr_ctl_in_d(0) <= xu_mm_slowspr_val; +spr_ctl_in_d(1) <= xu_mm_slowspr_rw; +spr_ctl_in_d(2) <= xu_mm_slowspr_done; +spr_etid_in_d <= xu_mm_slowspr_etid; +spr_addr_in_d <= xu_mm_slowspr_addr; +spr_addr_in_clone_d <= xu_mm_slowspr_addr; +spr_data_in_d <= xu_mm_slowspr_data; +spr_ctl_int_d <= spr_ctl_in_q; +spr_etid_int_d <= spr_etid_in_q; +spr_addr_int_d <= spr_addr_in_q; +spr_data_int_d <= spr_data_in_q; +spr_match_any_mmu <= ( spr_ctl_in_q(0) and (Eq(spr_addr_in_q, Spr_Addr_PID) or Eq(spr_addr_in_q, Spr_Addr_MMUCR0) or + Eq(spr_addr_in_q, Spr_Addr_MMUCR1) or Eq(spr_addr_in_q, Spr_Addr_MMUCR2) or + Eq(spr_addr_in_q, Spr_Addr_MMUCR3) or Eq(spr_addr_in_q, Spr_Addr_LPID) or + Eq(spr_addr_in_clone_q, Spr_Addr_MAS0) or Eq(spr_addr_in_clone_q, Spr_Addr_MAS1) or + Eq(spr_addr_in_clone_q, Spr_Addr_MAS2) or Eq(spr_addr_in_clone_q, Spr_Addr_MAS3) or + Eq(spr_addr_in_clone_q, Spr_Addr_MAS4) or Eq(spr_addr_in_clone_q, Spr_Addr_MAS5) or + Eq(spr_addr_in_clone_q, Spr_Addr_MAS6) or Eq(spr_addr_in_clone_q, Spr_Addr_MAS7) or + Eq(spr_addr_in_clone_q, Spr_Addr_MAS8) or Eq(spr_addr_in_clone_q, Spr_Addr_MAS2U) or + Eq(spr_addr_in_clone_q, Spr_Addr_MAS01_64b) or Eq(spr_addr_in_clone_q, Spr_Addr_MAS56_64b) or + Eq(spr_addr_in_clone_q, Spr_Addr_MAS73_64b) or Eq(spr_addr_in_clone_q, Spr_Addr_MAS81_64b) or + Eq(spr_addr_in_clone_q, Spr_Addr_MMUCFG) or Eq(spr_addr_in_clone_q, Spr_Addr_MMUCSR0) or + Eq(spr_addr_in_clone_q, Spr_Addr_TLB0CFG) or Eq(spr_addr_in_clone_q, Spr_Addr_TLB0PS) or + Eq(spr_addr_in_clone_q, Spr_Addr_LRATCFG) or Eq(spr_addr_in_clone_q, Spr_Addr_LRATPS) or + Eq(spr_addr_in_clone_q, Spr_Addr_EPTCFG) or Eq(spr_addr_in_clone_q, Spr_Addr_LPER) or + Eq(spr_addr_in_clone_q, Spr_Addr_LPERU)) ); +spr_match_pid0 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "00") and Eq(spr_addr_in_q, Spr_Addr_PID)); +spr_match_pid1 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "01") and Eq(spr_addr_in_q, Spr_Addr_PID)); +spr_match_pid2 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "10") and Eq(spr_addr_in_q, Spr_Addr_PID)); +spr_match_pid3 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "11") and Eq(spr_addr_in_q, Spr_Addr_PID)); +spr_match_mmucr0_0 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "00") and Eq(spr_addr_in_q, Spr_Addr_MMUCR0)); +spr_match_mmucr0_1 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "01") and Eq(spr_addr_in_q, Spr_Addr_MMUCR0)); +spr_match_mmucr0_2 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "10") and Eq(spr_addr_in_q, Spr_Addr_MMUCR0)); +spr_match_mmucr0_3 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "11") and Eq(spr_addr_in_q, Spr_Addr_MMUCR0)); +spr_match_mmucr1 <= (spr_ctl_in_q(0) and Eq(spr_addr_in_q, Spr_Addr_MMUCR1)); +spr_match_mmucr2 <= (spr_ctl_in_q(0) and Eq(spr_addr_in_q, Spr_Addr_MMUCR2)); +spr_match_mmucr3_0 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "00") and Eq(spr_addr_in_q, Spr_Addr_MMUCR3)); +spr_match_mmucr3_1 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "01") and Eq(spr_addr_in_q, Spr_Addr_MMUCR3)); +spr_match_mmucr3_2 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "10") and Eq(spr_addr_in_q, Spr_Addr_MMUCR3)); +spr_match_mmucr3_3 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "11") and Eq(spr_addr_in_q, Spr_Addr_MMUCR3)); +spr_match_lpidr <= (spr_ctl_in_q(0) and Eq(spr_addr_in_q, Spr_Addr_LPID)); +spr_match_mmucsr0 <= (spr_ctl_in_q(0) and Eq(spr_addr_in_clone_q, Spr_Addr_MMUCSR0)); +spr_match_mmucfg <= (spr_ctl_in_q(0) and Eq(spr_addr_in_clone_q, Spr_Addr_MMUCFG)); +spr_match_tlb0cfg <= (spr_ctl_in_q(0) and Eq(spr_addr_in_clone_q, Spr_Addr_TLB0CFG)); +spr_match_tlb0ps <= (spr_ctl_in_q(0) and Eq(spr_addr_in_clone_q, Spr_Addr_TLB0PS)); +spr_match_lratcfg <= (spr_ctl_in_q(0) and Eq(spr_addr_in_clone_q, Spr_Addr_LRATCFG)); +spr_match_lratps <= (spr_ctl_in_q(0) and Eq(spr_addr_in_clone_q, Spr_Addr_LRATPS)); +spr_match_eptcfg <= (spr_ctl_in_q(0) and Eq(spr_addr_in_clone_q, Spr_Addr_EPTCFG)); +spr_match_lper_0 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "00") and Eq(spr_addr_in_clone_q, Spr_Addr_LPER)); +spr_match_lperu_0 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "00") and Eq(spr_addr_in_clone_q, Spr_Addr_LPERU)); +spr_match_lper_1 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "01") and Eq(spr_addr_in_clone_q, Spr_Addr_LPER)); +spr_match_lperu_1 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "01") and Eq(spr_addr_in_clone_q, Spr_Addr_LPERU)); +spr_match_lper_2 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "10") and Eq(spr_addr_in_clone_q, Spr_Addr_LPER)); +spr_match_lperu_2 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "10") and Eq(spr_addr_in_clone_q, Spr_Addr_LPERU)); +spr_match_lper_3 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "11") and Eq(spr_addr_in_clone_q, Spr_Addr_LPER)); +spr_match_lperu_3 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "11") and Eq(spr_addr_in_clone_q, Spr_Addr_LPERU)); +spr_match_any_mas <= ( spr_ctl_in_q(0) and (Eq(spr_addr_in_clone_q, Spr_Addr_MAS0) or Eq(spr_addr_in_clone_q, Spr_Addr_MAS1) or Eq(spr_addr_in_clone_q, Spr_Addr_MAS2) or Eq(spr_addr_in_clone_q, Spr_Addr_MAS2U) or + Eq(spr_addr_in_clone_q, Spr_Addr_MAS3) or Eq(spr_addr_in_clone_q, Spr_Addr_MAS4) or Eq(spr_addr_in_clone_q, Spr_Addr_MAS5) or Eq(spr_addr_in_clone_q, Spr_Addr_MAS6) or + Eq(spr_addr_in_clone_q, Spr_Addr_MAS7) or Eq(spr_addr_in_clone_q, Spr_Addr_MAS8) or Eq(spr_addr_in_clone_q, Spr_Addr_MAS01_64b) or Eq(spr_addr_in_clone_q, Spr_Addr_MAS56_64b) or + Eq(spr_addr_in_clone_q, Spr_Addr_MAS73_64b) or Eq(spr_addr_in_clone_q, Spr_Addr_MAS81_64b)) ); +spr_match_mas0_0 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "00") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS0)); +spr_match_mas1_0 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "00") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS1)); +spr_match_mas2_0 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "00") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS2)); +spr_match_mas2u_0 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "00") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS2U)); +spr_match_mas3_0 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "00") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS3)); +spr_match_mas4_0 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "00") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS4)); +spr_match_mas5_0 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "00") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS5)); +spr_match_mas6_0 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "00") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS6)); +spr_match_mas7_0 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "00") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS7)); +spr_match_mas8_0 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "00") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS8)); +spr_match_mas01_64b_0 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "00") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS01_64b)); +spr_match_mas56_64b_0 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "00") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS56_64b)); +spr_match_mas73_64b_0 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "00") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS73_64b)); +spr_match_mas81_64b_0 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "00") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS81_64b)); +spr_match_mas0_1 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "01") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS0)); +spr_match_mas1_1 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "01") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS1)); +spr_match_mas2_1 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "01") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS2)); +spr_match_mas2u_1 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "01") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS2U)); +spr_match_mas3_1 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "01") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS3)); +spr_match_mas4_1 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "01") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS4)); +spr_match_mas5_1 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "01") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS5)); +spr_match_mas6_1 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "01") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS6)); +spr_match_mas7_1 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "01") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS7)); +spr_match_mas8_1 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "01") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS8)); +spr_match_mas01_64b_1 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "01") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS01_64b)); +spr_match_mas56_64b_1 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "01") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS56_64b)); +spr_match_mas73_64b_1 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "01") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS73_64b)); +spr_match_mas81_64b_1 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "01") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS81_64b)); +spr_match_mas0_2 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "10") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS0)); +spr_match_mas1_2 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "10") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS1)); +spr_match_mas2_2 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "10") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS2)); +spr_match_mas2u_2 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "10") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS2U)); +spr_match_mas3_2 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "10") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS3)); +spr_match_mas4_2 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "10") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS4)); +spr_match_mas5_2 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "10") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS5)); +spr_match_mas6_2 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "10") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS6)); +spr_match_mas7_2 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "10") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS7)); +spr_match_mas8_2 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "10") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS8)); +spr_match_mas01_64b_2 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "10") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS01_64b)); +spr_match_mas56_64b_2 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "10") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS56_64b)); +spr_match_mas73_64b_2 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "10") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS73_64b)); +spr_match_mas81_64b_2 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "10") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS81_64b)); +spr_match_mas0_3 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "11") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS0)); +spr_match_mas1_3 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "11") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS1)); +spr_match_mas2_3 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "11") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS2)); +spr_match_mas2u_3 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "11") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS2U)); +spr_match_mas3_3 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "11") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS3)); +spr_match_mas4_3 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "11") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS4)); +spr_match_mas5_3 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "11") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS5)); +spr_match_mas6_3 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "11") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS6)); +spr_match_mas7_3 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "11") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS7)); +spr_match_mas8_3 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "11") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS8)); +spr_match_mas01_64b_3 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "11") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS01_64b)); +spr_match_mas56_64b_3 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "11") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS56_64b)); +spr_match_mas73_64b_3 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "11") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS73_64b)); +spr_match_mas81_64b_3 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "11") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS81_64b)); +spr_match_mas2_64b <= (spr_ctl_in_q(0) and Eq(spr_addr_in_clone_q, Spr_Addr_MAS2)); +spr_match_mas01_64b <= (spr_ctl_in_q(0) and Eq(spr_addr_in_clone_q, Spr_Addr_MAS01_64b)); +spr_match_mas56_64b <= (spr_ctl_in_q(0) and Eq(spr_addr_in_clone_q, Spr_Addr_MAS56_64b)); +spr_match_mas73_64b <= (spr_ctl_in_q(0) and Eq(spr_addr_in_clone_q, Spr_Addr_MAS73_64b)); +spr_match_mas81_64b <= (spr_ctl_in_q(0) and Eq(spr_addr_in_clone_q, Spr_Addr_MAS81_64b)); +spr_match_64b <= spr_match_mas2_64b or spr_match_mas01_64b or spr_match_mas56_64b or spr_match_mas73_64b or spr_match_mas81_64b; +pid0_d <= spr_data_int_q(64-pid_width to 63) when (spr_match_pid0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) else pid0_q; +pid1_d <= spr_data_int_q(64-pid_width to 63) when (spr_match_pid1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) else pid1_q; +pid2_d <= spr_data_int_q(64-pid_width to 63) when (spr_match_pid2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) else pid2_q; +pid3_d <= spr_data_int_q(64-pid_width to 63) when (spr_match_pid3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) else pid3_q; +mmucr0_0_d <= spr_data_int_q(32) & or_reduce(spr_data_int_q(50 to 63)) & spr_data_int_q(34 to 37) & spr_data_int_q(50 to 63) + when (spr_match_mmucr0_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else xu_mm_derat_mmucr0_q(0 to 3) & "11" & mmucr0_0_q(6 to 7) & xu_mm_derat_mmucr0_q(6 to 17) + when xu_mm_derat_mmucr0_we_q(0)='1' and mmucr1_q(14 to 15)="01" + else xu_mm_derat_mmucr0_q(0 to 3) & "11" & xu_mm_derat_mmucr0_q(4 to 5) & mmucr0_0_q(8 to 11) & xu_mm_derat_mmucr0_q(10 to 17) + when xu_mm_derat_mmucr0_we_q(0)='1' and mmucr1_q(14 to 15)="10" + else xu_mm_derat_mmucr0_q(0 to 3) & "11" & xu_mm_derat_mmucr0_q(4 to 17) + when xu_mm_derat_mmucr0_we_q(0)='1' and mmucr1_q(14 to 15)="11" + else xu_mm_derat_mmucr0_q(0 to 3) & "11" & mmucr0_0_q(6 to 11) & xu_mm_derat_mmucr0_q(10 to 17) + when xu_mm_derat_mmucr0_we_q(0)='1' + else iu_mm_ierat_mmucr0_q(0 to 3) & "11" & mmucr0_0_q(6 to 7) & iu_mm_ierat_mmucr0_q(6 to 17) + when iu_mm_ierat_mmucr0_we_q(0)='1' and mmucr1_q(12 to 13)="01" + else iu_mm_ierat_mmucr0_q(0 to 3) & "11" & iu_mm_ierat_mmucr0_q(4 to 5) & mmucr0_0_q(8 to 11) & iu_mm_ierat_mmucr0_q(10 to 17) + when iu_mm_ierat_mmucr0_we_q(0)='1' and mmucr1_q(12 to 13)="10" + else iu_mm_ierat_mmucr0_q(0 to 3) & "11" & iu_mm_ierat_mmucr0_q(4 to 17) + when iu_mm_ierat_mmucr0_we_q(0)='1' and mmucr1_q(12 to 13)="11" + else iu_mm_ierat_mmucr0_q(0 to 3) & "10" & mmucr0_0_q(6 to 11) & iu_mm_ierat_mmucr0_q(10 to 17) + when iu_mm_ierat_mmucr0_we_q(0)='1' + else mmucr0_0_q; +mmucr0_1_d <= spr_data_int_q(32) & or_reduce(spr_data_int_q(50 to 63)) & spr_data_int_q(34 to 37) & spr_data_int_q(50 to 63) + when (spr_match_mmucr0_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else xu_mm_derat_mmucr0_q(0 to 3) & "11" & mmucr0_1_q(6 to 7) & xu_mm_derat_mmucr0_q(6 to 17) + when xu_mm_derat_mmucr0_we_q(1)='1' and mmucr1_q(14 to 15)="01" + else xu_mm_derat_mmucr0_q(0 to 3) & "11" & xu_mm_derat_mmucr0_q(4 to 5) & mmucr0_1_q(8 to 11) & xu_mm_derat_mmucr0_q(10 to 17) + when xu_mm_derat_mmucr0_we_q(1)='1' and mmucr1_q(14 to 15)="10" + else xu_mm_derat_mmucr0_q(0 to 3) & "11" & xu_mm_derat_mmucr0_q(4 to 17) + when xu_mm_derat_mmucr0_we_q(1)='1' and mmucr1_q(14 to 15)="11" + else xu_mm_derat_mmucr0_q(0 to 3) & "11" & mmucr0_1_q(6 to 11) & xu_mm_derat_mmucr0_q(10 to 17) + when xu_mm_derat_mmucr0_we_q(1)='1' + else iu_mm_ierat_mmucr0_q(0 to 3) & "11" & mmucr0_1_q(6 to 7) & iu_mm_ierat_mmucr0_q(6 to 17) + when iu_mm_ierat_mmucr0_we_q(1)='1' and mmucr1_q(12 to 13)="01" + else iu_mm_ierat_mmucr0_q(0 to 3) & "11" & iu_mm_ierat_mmucr0_q(4 to 5) & mmucr0_1_q(8 to 11) & iu_mm_ierat_mmucr0_q(10 to 17) + when iu_mm_ierat_mmucr0_we_q(1)='1' and mmucr1_q(12 to 13)="10" + else iu_mm_ierat_mmucr0_q(0 to 3) & "11" & iu_mm_ierat_mmucr0_q(4 to 17) + when iu_mm_ierat_mmucr0_we_q(1)='1' and mmucr1_q(12 to 13)="11" + else iu_mm_ierat_mmucr0_q(0 to 3) & "10" & mmucr0_1_q(6 to 11) & iu_mm_ierat_mmucr0_q(10 to 17) + when iu_mm_ierat_mmucr0_we_q(1)='1' + else mmucr0_1_q; +mmucr0_2_d <= spr_data_int_q(32) & or_reduce(spr_data_int_q(50 to 63)) & spr_data_int_q(34 to 37) & spr_data_int_q(50 to 63) + when (spr_match_mmucr0_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else xu_mm_derat_mmucr0_q(0 to 3) & "11" & mmucr0_2_q(6 to 7) & xu_mm_derat_mmucr0_q(6 to 17) + when xu_mm_derat_mmucr0_we_q(2)='1' and mmucr1_q(14 to 15)="01" + else xu_mm_derat_mmucr0_q(0 to 3) & "11" & xu_mm_derat_mmucr0_q(4 to 5) & mmucr0_2_q(8 to 11) & xu_mm_derat_mmucr0_q(10 to 17) + when xu_mm_derat_mmucr0_we_q(2)='1' and mmucr1_q(14 to 15)="10" + else xu_mm_derat_mmucr0_q(0 to 3) & "11" & xu_mm_derat_mmucr0_q(4 to 17) + when xu_mm_derat_mmucr0_we_q(2)='1' and mmucr1_q(14 to 15)="11" + else xu_mm_derat_mmucr0_q(0 to 3) & "11" & mmucr0_2_q(6 to 11) & xu_mm_derat_mmucr0_q(10 to 17) + when xu_mm_derat_mmucr0_we_q(2)='1' + else iu_mm_ierat_mmucr0_q(0 to 3) & "11" & mmucr0_2_q(6 to 7) & iu_mm_ierat_mmucr0_q(6 to 17) + when iu_mm_ierat_mmucr0_we_q(2)='1' and mmucr1_q(12 to 13)="01" + else iu_mm_ierat_mmucr0_q(0 to 3) & "11" & iu_mm_ierat_mmucr0_q(4 to 5) & mmucr0_2_q(8 to 11) & iu_mm_ierat_mmucr0_q(10 to 17) + when iu_mm_ierat_mmucr0_we_q(2)='1' and mmucr1_q(12 to 13)="10" + else iu_mm_ierat_mmucr0_q(0 to 3) & "11" & iu_mm_ierat_mmucr0_q(4 to 17) + when iu_mm_ierat_mmucr0_we_q(2)='1' and mmucr1_q(12 to 13)="11" + else iu_mm_ierat_mmucr0_q(0 to 3) & "10" & mmucr0_2_q(6 to 11) & iu_mm_ierat_mmucr0_q(10 to 17) + when iu_mm_ierat_mmucr0_we_q(2)='1' + else mmucr0_2_q; +mmucr0_3_d <= spr_data_int_q(32) & or_reduce(spr_data_int_q(50 to 63)) & spr_data_int_q(34 to 37) & spr_data_int_q(50 to 63) + when (spr_match_mmucr0_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else xu_mm_derat_mmucr0_q(0 to 3) & "11" & mmucr0_3_q(6 to 7) & xu_mm_derat_mmucr0_q(6 to 17) + when xu_mm_derat_mmucr0_we_q(3)='1' and mmucr1_q(14 to 15)="01" + else xu_mm_derat_mmucr0_q(0 to 3) & "11" & xu_mm_derat_mmucr0_q(4 to 5) & mmucr0_3_q(8 to 11) & xu_mm_derat_mmucr0_q(10 to 17) + when xu_mm_derat_mmucr0_we_q(3)='1' and mmucr1_q(14 to 15)="10" + else xu_mm_derat_mmucr0_q(0 to 3) & "11" & xu_mm_derat_mmucr0_q(4 to 17) + when xu_mm_derat_mmucr0_we_q(3)='1' and mmucr1_q(14 to 15)="11" + else xu_mm_derat_mmucr0_q(0 to 3) & "11" & mmucr0_3_q(6 to 11) & xu_mm_derat_mmucr0_q(10 to 17) + when xu_mm_derat_mmucr0_we_q(3)='1' + else iu_mm_ierat_mmucr0_q(0 to 3) & "11" & mmucr0_3_q(6 to 7) & iu_mm_ierat_mmucr0_q(6 to 17) + when iu_mm_ierat_mmucr0_we_q(3)='1' and mmucr1_q(12 to 13)="01" + else iu_mm_ierat_mmucr0_q(0 to 3) & "11" & iu_mm_ierat_mmucr0_q(4 to 5) & mmucr0_3_q(8 to 11) & iu_mm_ierat_mmucr0_q(10 to 17) + when iu_mm_ierat_mmucr0_we_q(3)='1' and mmucr1_q(12 to 13)="10" + else iu_mm_ierat_mmucr0_q(0 to 3) & "11" & iu_mm_ierat_mmucr0_q(4 to 17) + when iu_mm_ierat_mmucr0_we_q(3)='1' and mmucr1_q(12 to 13)="11" + else iu_mm_ierat_mmucr0_q(0 to 3) & "10" & mmucr0_3_q(6 to 11) & iu_mm_ierat_mmucr0_q(10 to 17) + when iu_mm_ierat_mmucr0_we_q(3)='1' + else mmucr0_3_q; +mmucr1_d(0 to 16) <= spr_data_int_q(32 to 48) when (spr_match_mmucr1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) else mmucr1_q(0 to 16); +mmucr1_d(17) <= (spr_data_int_q(49) and not cswitch_q(1)) when (spr_match_mmucr1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) else mmucr1_q(17); +mmucr1_d(18 to 19) <= spr_data_int_q(50 to 51) when (spr_match_mmucr1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) else mmucr1_q(18 to 19); +mmucr1_d(20) <= '0' when (spr_match_mmucr1_q='1' and spr_ctl_int_q(1)=Spr_RW_Read and cswitch_q(0)='0') + else spr_data_int_q(52) when (spr_match_mmucr1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write and cswitch_q(0)='1') + else '1' when (iu_mm_ierat_mmucr1_we_q='1' and xu_mm_derat_mmucr1_we_q='0' and tlb_mmucr1_we='0' and mmucr1_q(20 to 22)="000") + else mmucr1_q(20); +mmucr1_d(21) <= '0' when (spr_match_mmucr1_q='1' and spr_ctl_int_q(1)=Spr_RW_Read and cswitch_q(0)='0') + else spr_data_int_q(53) when (spr_match_mmucr1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write and cswitch_q(0)='1') + else '1' when (xu_mm_derat_mmucr1_we_q='1' and tlb_mmucr1_we='0' and mmucr1_q(20 to 22)="000") + else mmucr1_q(21); +mmucr1_d(22) <= '0' when (spr_match_mmucr1_q='1' and spr_ctl_int_q(1)=Spr_RW_Read and cswitch_q(0)='0') + else spr_data_int_q(54) when (spr_match_mmucr1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write and cswitch_q(0)='1') + else '1' when (tlb_mmucr1_we='1' and mmucr1_q(20 to 22)="000") + else mmucr1_q(22); +mmucr1_d(23 to 31) <= (others => '0') when (spr_match_mmucr1_q='1' and spr_ctl_int_q(1)=Spr_RW_Read and cswitch_q(0)='0') + else spr_data_int_q(55 to 63) when (spr_match_mmucr1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write and cswitch_q(0)='1') + else tlb_mmucr1_een when (tlb_mmucr1_we='1' and mmucr1_q(20 to 22)="000") + else "0000" & xu_mm_derat_mmucr1_q when (xu_mm_derat_mmucr1_we_q='1' and mmucr1_q(20 to 22)="000") + else "00000" & iu_mm_ierat_mmucr1_q when (iu_mm_ierat_mmucr1_we_q='1' and mmucr1_q(20 to 22)="000") + else mmucr1_q(23 to 31); +mmucr2_d(0 to 31) <= spr_data_int_q(32 to 63) when (spr_match_mmucr2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) else mmucr2_q(0 to 31); +mmucr3_0_d <= spr_data_int_q(64-mmucr3_width to 63) when (spr_match_mmucr3_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mmucr3_x & tlb_mmucr3_rc & tlb_mmucr3_extclass & tlb_mmucr3_class & tlb_mmucr3_wlc & tlb_mmucr3_resvattr & '0' & tlb_mmucr3_thdid + when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(0)='1') + else lrat_mmucr3_x & "00" & '0' & '0' & "00" & "00" & '0' & '0' & "1111" + when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(0)='1') + else mmucr3_0_q; +mmucr3_1_d <= spr_data_int_q(64-mmucr3_width to 63) when (spr_match_mmucr3_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mmucr3_x & tlb_mmucr3_rc & tlb_mmucr3_extclass & tlb_mmucr3_class & tlb_mmucr3_wlc & tlb_mmucr3_resvattr & '0' & tlb_mmucr3_thdid + when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(1)='1') + else lrat_mmucr3_x & "00" & '0' & '0' & "00" & "00" & '0' & '0' & "1111" + when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(1)='1') + else mmucr3_1_q; +mmucr3_2_d <= spr_data_int_q(64-mmucr3_width to 63) when (spr_match_mmucr3_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mmucr3_x & tlb_mmucr3_rc & tlb_mmucr3_extclass & tlb_mmucr3_class & tlb_mmucr3_wlc & tlb_mmucr3_resvattr & '0' & tlb_mmucr3_thdid + when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(2)='1') + else lrat_mmucr3_x & "00" & '0' & '0' & "00" & "00" & '0' & '0' & "1111" + when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(2)='1') + else mmucr3_2_q; +mmucr3_3_d <= spr_data_int_q(64-mmucr3_width to 63) when (spr_match_mmucr3_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mmucr3_x & tlb_mmucr3_rc & tlb_mmucr3_extclass & tlb_mmucr3_class & tlb_mmucr3_wlc & tlb_mmucr3_resvattr & '0' & tlb_mmucr3_thdid + when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(3)='1') + else lrat_mmucr3_x & "00" & '0' & '0' & "00" & "00" & '0' & '0' & "1111" + when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(3)='1') + else mmucr3_3_q; +lpidr_d <= spr_data_int_q(64-lpid_width to 63) when (spr_match_lpidr_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) else lpidr_q; +mmucsr0_tlb0fi_d <= '1' when (mmucsr0_tlb0fi_q='0' and spr_match_mmucsr0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write and spr_data_int_q(61)='1') + else '0' when mmq_inval_tlb0fi_done='1' + else mmucsr0_tlb0fi_q; +lper_0_alpn_d(32 to 51) <= spr_data_int_q(32 to 51) when (spr_match_lper_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_lper_lpn(32 to 51) when tlb_lper_we(0)='1' + else lper_0_alpn_q(32 to 51); +gen64_lper_0_alpn: if spr_data_width = 64 generate +lper_0_alpn_d(64-real_addr_width to 31) <= spr_data_int_q(64-real_addr_width to 31) + when (spr_match_lper_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(64-real_addr_width+32 to 63) + when (spr_match_lperu_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_lper_lpn(64-real_addr_width to 31) when tlb_lper_we(0)='1' + else lper_0_alpn_q(64-real_addr_width to 31); +end generate gen64_lper_0_alpn; +gen32_lper_0_alpn: if spr_data_width = 32 generate +lper_0_alpn_d(64-real_addr_width to 31) <= spr_data_int_q(64-real_addr_width+32 to 63) + when (spr_match_lperu_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_lper_lpn(64-real_addr_width to 31) when tlb_lper_we(0)='1' + else lper_0_alpn_q(64-real_addr_width to 31); +end generate gen32_lper_0_alpn; +lper_0_lps_d <= spr_data_int_q(60 to 63) when (spr_match_lper_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_lper_lps(60 to 63) when tlb_lper_we(0)='1' + else lper_0_lps_q; +lper_1_alpn_d(32 to 51) <= spr_data_int_q(32 to 51) when (spr_match_lper_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_lper_lpn(32 to 51) when tlb_lper_we(1)='1' + else lper_1_alpn_q(32 to 51); +gen64_lper_1_alpn: if spr_data_width = 64 generate +lper_1_alpn_d(64-real_addr_width to 31) <= spr_data_int_q(64-real_addr_width to 31) + when (spr_match_lper_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(64-real_addr_width+32 to 63) + when (spr_match_lperu_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_lper_lpn(64-real_addr_width to 31) when tlb_lper_we(1)='1' + else lper_1_alpn_q(64-real_addr_width to 31); +end generate gen64_lper_1_alpn; +gen32_lper_1_alpn: if spr_data_width = 32 generate +lper_1_alpn_d(64-real_addr_width to 31) <= spr_data_int_q(64-real_addr_width+32 to 63) + when (spr_match_lperu_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_lper_lpn(64-real_addr_width to 31) when tlb_lper_we(1)='1' + else lper_1_alpn_q(64-real_addr_width to 31); +end generate gen32_lper_1_alpn; +lper_1_lps_d <= spr_data_int_q(60 to 63) when (spr_match_lper_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_lper_lps(60 to 63) when tlb_lper_we(1)='1' + else lper_1_lps_q; +lper_2_alpn_d(32 to 51) <= spr_data_int_q(32 to 51) when (spr_match_lper_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_lper_lpn(32 to 51) when tlb_lper_we(2)='1' + else lper_2_alpn_q(32 to 51); +gen64_lper_2_alpn: if spr_data_width = 64 generate +lper_2_alpn_d(64-real_addr_width to 31) <= spr_data_int_q(64-real_addr_width to 31) + when (spr_match_lper_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(64-real_addr_width+32 to 63) + when (spr_match_lperu_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_lper_lpn(64-real_addr_width to 31) when tlb_lper_we(2)='1' + else lper_2_alpn_q(64-real_addr_width to 31); +end generate gen64_lper_2_alpn; +gen32_lper_2_alpn: if spr_data_width = 32 generate +lper_2_alpn_d(64-real_addr_width to 31) <= spr_data_int_q(64-real_addr_width+32 to 63) + when (spr_match_lperu_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_lper_lpn(64-real_addr_width to 31) when tlb_lper_we(2)='1' + else lper_2_alpn_q(64-real_addr_width to 31); +end generate gen32_lper_2_alpn; +lper_2_lps_d <= spr_data_int_q(60 to 63) when (spr_match_lper_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_lper_lps(60 to 63) when tlb_lper_we(2)='1' + else lper_2_lps_q; +lper_3_alpn_d(32 to 51) <= spr_data_int_q(32 to 51) when (spr_match_lper_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_lper_lpn(32 to 51) when tlb_lper_we(3)='1' + else lper_3_alpn_q(32 to 51); +gen64_lper_3_alpn: if spr_data_width = 64 generate +lper_3_alpn_d(64-real_addr_width to 31) <= spr_data_int_q(64-real_addr_width to 31) + when (spr_match_lper_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(64-real_addr_width+32 to 63) + when (spr_match_lperu_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_lper_lpn(64-real_addr_width to 31) when tlb_lper_we(3)='1' + else lper_3_alpn_q(64-real_addr_width to 31); +end generate gen64_lper_3_alpn; +gen32_lper_3_alpn: if spr_data_width = 32 generate +lper_3_alpn_d(64-real_addr_width to 31) <= spr_data_int_q(64-real_addr_width+32 to 63) + when (spr_match_lperu_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_lper_lpn(64-real_addr_width to 31) when tlb_lper_we(3)='1' + else lper_3_alpn_q(64-real_addr_width to 31); +end generate gen32_lper_3_alpn; +lper_3_lps_d <= spr_data_int_q(60 to 63) when (spr_match_lper_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_lper_lps(60 to 63) when tlb_lper_we(3)='1' + else lper_3_lps_q; +mas1_0_v_d <= spr_data_int_q(32) when ((spr_match_mas1_0_q='1' or spr_match_mas01_64b_0_q='1' or spr_match_mas81_64b_0_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else '0' when (tlb_mas_tlbsx_miss='1' and tlb_mas_thdid(0)='1') + else '1' when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(0)='1') + else tlb_mas1_v when (tlb_mas_tlbre='1' and tlb_mas_thdid(0)='1') + else '0' when (lrat_mas_tlbsx_miss='1' and lrat_mas_thdid(0)='1') + else '1' when (lrat_mas_tlbsx_hit='1' and lrat_mas_thdid(0)='1') + else lrat_mas1_v when (lrat_mas_tlbre='1' and lrat_mas_thdid(0)='1') + else mas1_0_v_q; +mas1_0_iprot_d <= spr_data_int_q(33) when ((spr_match_mas1_0_q='1' or spr_match_mas01_64b_0_q='1' or spr_match_mas81_64b_0_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else '0' when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(0)='1') + else tlb_mas1_iprot when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(0)='1') + else '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(0)='1') + else mas1_0_iprot_q; +mas1_0_tid_d <= spr_data_int_q(34 to 47) when ((spr_match_mas1_0_q='1' or spr_match_mas01_64b_0_q='1' or spr_match_mas81_64b_0_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else mas6_0_spid_q when ( tlb_mas_tlbsx_miss='1' and tlb_mas_thdid(0)='1') + else tlb_mas1_tid_error when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(0)='1') + else tlb_mas1_tid when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(0)='1') + else (others => '0') when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(0)='1') + else mas1_0_tid_q; +mas1_0_ind_d <= spr_data_int_q(50) when ((spr_match_mas1_0_q='1' or spr_match_mas01_64b_0_q='1' or spr_match_mas81_64b_0_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_0_indd_q when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(0)='1') + else tlb_mas1_ind when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(0)='1') + else '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(0)='1') + else mas1_0_ind_q; +mas1_0_ts_d <= spr_data_int_q(51) when ((spr_match_mas1_0_q='1' or spr_match_mas01_64b_0_q='1' or spr_match_mas81_64b_0_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else mas6_0_sas_q when ( tlb_mas_tlbsx_miss='1' and tlb_mas_thdid(0)='1') + else tlb_mas1_ts_error when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(0)='1') + else tlb_mas1_ts when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(0)='1') + else '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(0)='1') + else mas1_0_ts_q; +mas1_0_tsize_d <= spr_data_int_q(52 to 55) when ((spr_match_mas1_0_q='1' or spr_match_mas01_64b_0_q='1' or spr_match_mas81_64b_0_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_0_tsized_q when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(0)='1') + else tlb_mas1_tsize when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(0)='1') + else lrat_mas1_tsize when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(0)='1') + else mas1_0_tsize_q; +mas2_0_epn_d(32 to 51) <= spr_data_int_q(32 to 51) when (spr_match_mas2_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas2_epn_error(32 to 51) when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(0)='1') + else tlb_mas2_epn(32 to 51) when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(0)='1') + else lrat_mas2_epn(32 to 51) when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(0)='1') + else mas2_0_epn_q(32 to 51); +mas2_0_wimge_d <= spr_data_int_q(59 to 63) when (spr_match_mas2_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_0_wimged_q when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(0)='1') + else tlb_mas2_wimge when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(0)='1') + else (others => '0') when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(0)='1') + else mas2_0_wimge_q; +mas3_0_rpnl_d <= spr_data_int_q(32 to 52) + when ((spr_match_mas3_0_q='1' or spr_match_mas73_64b_0_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else (others => '0') when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(0)='1') + else tlb_mas3_rpnl & (tlb_mas3_usxwr(5) and tlb_mas1_ind) + when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(0)='1') + else lrat_mas3_rpnl & '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(0)='1') + else mas3_0_rpnl_q; +mas3_0_ubits_d <= spr_data_int_q(54 to 57) when ((spr_match_mas3_0_q='1' or spr_match_mas73_64b_0_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else (others => '0') when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(0)='1') + else tlb_mas3_ubits when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(0)='1') + else (others => '0') when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(0)='1') + else mas3_0_ubits_q; +mas3_0_usxwr_d <= spr_data_int_q(58 to 63) when ((spr_match_mas3_0_q='1' or spr_match_mas73_64b_0_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else (others => '0') when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(0)='1') + else (tlb_mas3_usxwr(0 to 4) & (tlb_mas3_usxwr(5) and not tlb_mas1_ind)) when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(0)='1') + else (others => '0') when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(0)='1') + else mas3_0_usxwr_q; +mas4_0_indd_d <= spr_data_int_q(48) when (spr_match_mas4_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_0_indd_q; +mas4_0_tsized_d <= spr_data_int_q(52 to 55) when (spr_match_mas4_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_0_tsized_q; +mas4_0_wimged_d <= spr_data_int_q(59 to 63) when (spr_match_mas4_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_0_wimged_q; +mas6_0_spid_d <= spr_data_int_q(34 to 47) when ((spr_match_mas6_0_q='1' or spr_match_mas56_64b_0_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas6_spid when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(0)='1') + else mas6_0_spid_q; +mas6_0_isize_d <= spr_data_int_q(52 to 55) when ((spr_match_mas6_0_q='1' or spr_match_mas56_64b_0_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_0_tsized_q when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(0)='1') + else mas6_0_isize_q; +mas6_0_sind_d <= spr_data_int_q(62) when ((spr_match_mas6_0_q='1' or spr_match_mas56_64b_0_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_0_indd_q when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(0)='1') + else mas6_0_sind_q; +mas6_0_sas_d <= spr_data_int_q(63) when ((spr_match_mas6_0_q='1' or spr_match_mas56_64b_0_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas6_sas when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(0)='1') + else mas6_0_sas_q; +mas1_1_v_d <= spr_data_int_q(32) when ((spr_match_mas1_1_q='1' or spr_match_mas01_64b_1_q='1' or spr_match_mas81_64b_1_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else '0' when (tlb_mas_tlbsx_miss='1' and tlb_mas_thdid(1)='1') + else '1' when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(1)='1') + else tlb_mas1_v when (tlb_mas_tlbre='1' and tlb_mas_thdid(1)='1') + else '0' when (lrat_mas_tlbsx_miss='1' and lrat_mas_thdid(1)='1') + else '1' when (lrat_mas_tlbsx_hit='1' and lrat_mas_thdid(1)='1') + else lrat_mas1_v when (lrat_mas_tlbre='1' and lrat_mas_thdid(1)='1') + else mas1_1_v_q; +mas1_1_iprot_d <= spr_data_int_q(33) when ((spr_match_mas1_1_q='1' or spr_match_mas01_64b_1_q='1' or spr_match_mas81_64b_1_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else '0' when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(1)='1') + else tlb_mas1_iprot when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(1)='1') + else '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(1)='1') + else mas1_1_iprot_q; +mas1_1_tid_d <= spr_data_int_q(34 to 47) when ((spr_match_mas1_1_q='1' or spr_match_mas01_64b_1_q='1' or spr_match_mas81_64b_1_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else mas6_1_spid_q when ( tlb_mas_tlbsx_miss='1' and tlb_mas_thdid(1)='1') + else tlb_mas1_tid_error when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(1)='1') + else tlb_mas1_tid when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(1)='1') + else (others => '0') when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(1)='1') + else mas1_1_tid_q; +mas1_1_ind_d <= spr_data_int_q(50) when ((spr_match_mas1_1_q='1' or spr_match_mas01_64b_1_q='1' or spr_match_mas81_64b_1_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_1_indd_q when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(1)='1') + else tlb_mas1_ind when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(1)='1') + else '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(1)='1') + else mas1_1_ind_q; +mas1_1_ts_d <= spr_data_int_q(51) when ((spr_match_mas1_1_q='1' or spr_match_mas01_64b_1_q='1' or spr_match_mas81_64b_1_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else mas6_1_sas_q when ( tlb_mas_tlbsx_miss='1' and tlb_mas_thdid(1)='1') + else tlb_mas1_ts_error when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(1)='1') + else tlb_mas1_ts when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(1)='1') + else '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(1)='1') + else mas1_1_ts_q; +mas1_1_tsize_d <= spr_data_int_q(52 to 55) when ((spr_match_mas1_1_q='1' or spr_match_mas01_64b_1_q='1' or spr_match_mas81_64b_1_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_1_tsized_q when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(1)='1') + else tlb_mas1_tsize when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(1)='1') + else lrat_mas1_tsize when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(1)='1') + else mas1_1_tsize_q; +mas2_1_epn_d(32 to 51) <= spr_data_int_q(32 to 51) when (spr_match_mas2_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas2_epn_error(32 to 51) when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(1)='1') + else tlb_mas2_epn(32 to 51) when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(1)='1') + else lrat_mas2_epn(32 to 51) when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(1)='1') + else mas2_1_epn_q(32 to 51); +mas2_1_wimge_d <= spr_data_int_q(59 to 63) when (spr_match_mas2_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_1_wimged_q when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(1)='1') + else tlb_mas2_wimge when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(1)='1') + else (others => '0') when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(1)='1') + else mas2_1_wimge_q; +mas3_1_rpnl_d <= spr_data_int_q(32 to 52) + when ((spr_match_mas3_1_q='1' or spr_match_mas73_64b_1_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else (others => '0') when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(1)='1') + else tlb_mas3_rpnl & (tlb_mas3_usxwr(5) and tlb_mas1_ind) + when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(1)='1') + else lrat_mas3_rpnl & '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(1)='1') + else mas3_1_rpnl_q; +mas3_1_ubits_d <= spr_data_int_q(54 to 57) when ((spr_match_mas3_1_q='1' or spr_match_mas73_64b_1_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else (others => '0') when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(1)='1') + else tlb_mas3_ubits when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(1)='1') + else (others => '0') when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(1)='1') + else mas3_1_ubits_q; +mas3_1_usxwr_d <= spr_data_int_q(58 to 63) when ((spr_match_mas3_1_q='1' or spr_match_mas73_64b_1_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else (others => '0') when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(1)='1') + else (tlb_mas3_usxwr(0 to 4) & (tlb_mas3_usxwr(5) and not tlb_mas1_ind)) when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(1)='1') + else (others => '0') when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(1)='1') + else mas3_1_usxwr_q; +mas4_1_indd_d <= spr_data_int_q(48) when (spr_match_mas4_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_1_indd_q; +mas4_1_tsized_d <= spr_data_int_q(52 to 55) when (spr_match_mas4_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_1_tsized_q; +mas4_1_wimged_d <= spr_data_int_q(59 to 63) when (spr_match_mas4_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_1_wimged_q; +mas6_1_spid_d <= spr_data_int_q(34 to 47) when ((spr_match_mas6_1_q='1' or spr_match_mas56_64b_1_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas6_spid when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(1)='1') + else mas6_1_spid_q; +mas6_1_isize_d <= spr_data_int_q(52 to 55) when ((spr_match_mas6_1_q='1' or spr_match_mas56_64b_1_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_1_tsized_q when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(1)='1') + else mas6_1_isize_q; +mas6_1_sind_d <= spr_data_int_q(62) when ((spr_match_mas6_1_q='1' or spr_match_mas56_64b_1_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_1_indd_q when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(1)='1') + else mas6_1_sind_q; +mas6_1_sas_d <= spr_data_int_q(63) when ((spr_match_mas6_1_q='1' or spr_match_mas56_64b_1_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas6_sas when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(1)='1') + else mas6_1_sas_q; +mas1_2_v_d <= spr_data_int_q(32) when ((spr_match_mas1_2_q='1' or spr_match_mas01_64b_2_q='1' or spr_match_mas81_64b_2_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else '0' when (tlb_mas_tlbsx_miss='1' and tlb_mas_thdid(2)='1') + else '1' when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(2)='1') + else tlb_mas1_v when (tlb_mas_tlbre='1' and tlb_mas_thdid(2)='1') + else '0' when (lrat_mas_tlbsx_miss='1' and lrat_mas_thdid(2)='1') + else '1' when (lrat_mas_tlbsx_hit='1' and lrat_mas_thdid(2)='1') + else lrat_mas1_v when (lrat_mas_tlbre='1' and lrat_mas_thdid(2)='1') + else mas1_2_v_q; +mas1_2_iprot_d <= spr_data_int_q(33) when ((spr_match_mas1_2_q='1' or spr_match_mas01_64b_2_q='1' or spr_match_mas81_64b_2_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else '0' when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(2)='1') + else tlb_mas1_iprot when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(2)='1') + else '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(2)='1') + else mas1_2_iprot_q; +mas1_2_tid_d <= spr_data_int_q(34 to 47) when ((spr_match_mas1_2_q='1' or spr_match_mas01_64b_2_q='1' or spr_match_mas81_64b_2_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else mas6_2_spid_q when ( tlb_mas_tlbsx_miss='1' and tlb_mas_thdid(2)='1') + else tlb_mas1_tid_error when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(2)='1') + else tlb_mas1_tid when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(2)='1') + else (others => '0') when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(2)='1') + else mas1_2_tid_q; +mas1_2_ind_d <= spr_data_int_q(50) when ((spr_match_mas1_2_q='1' or spr_match_mas01_64b_2_q='1' or spr_match_mas81_64b_2_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_2_indd_q when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(2)='1') + else tlb_mas1_ind when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(2)='1') + else '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(2)='1') + else mas1_2_ind_q; +mas1_2_ts_d <= spr_data_int_q(51) when ((spr_match_mas1_2_q='1' or spr_match_mas01_64b_2_q='1' or spr_match_mas81_64b_2_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else mas6_2_sas_q when ( tlb_mas_tlbsx_miss='1' and tlb_mas_thdid(2)='1') + else tlb_mas1_ts_error when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(2)='1') + else tlb_mas1_ts when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(2)='1') + else '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(2)='1') + else mas1_2_ts_q; +mas1_2_tsize_d <= spr_data_int_q(52 to 55) when ((spr_match_mas1_2_q='1' or spr_match_mas01_64b_2_q='1' or spr_match_mas81_64b_2_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_2_tsized_q when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(2)='1') + else tlb_mas1_tsize when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(2)='1') + else lrat_mas1_tsize when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(2)='1') + else mas1_2_tsize_q; +mas2_2_epn_d(32 to 51) <= spr_data_int_q(32 to 51) when (spr_match_mas2_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas2_epn_error(32 to 51) when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(2)='1') + else tlb_mas2_epn(32 to 51) when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(2)='1') + else lrat_mas2_epn(32 to 51) when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(2)='1') + else mas2_2_epn_q(32 to 51); +mas2_2_wimge_d <= spr_data_int_q(59 to 63) when (spr_match_mas2_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_2_wimged_q when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(2)='1') + else tlb_mas2_wimge when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(2)='1') + else (others => '0') when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(2)='1') + else mas2_2_wimge_q; +mas3_2_rpnl_d <= spr_data_int_q(32 to 52) + when ((spr_match_mas3_2_q='1' or spr_match_mas73_64b_2_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else (others => '0') when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(2)='1') + else tlb_mas3_rpnl & (tlb_mas3_usxwr(5) and tlb_mas1_ind) + when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(2)='1') + else lrat_mas3_rpnl & '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(2)='1') + else mas3_2_rpnl_q; +mas3_2_ubits_d <= spr_data_int_q(54 to 57) when ((spr_match_mas3_2_q='1' or spr_match_mas73_64b_2_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else (others => '0') when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(2)='1') + else tlb_mas3_ubits when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(2)='1') + else (others => '0') when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(2)='1') + else mas3_2_ubits_q; +mas3_2_usxwr_d <= spr_data_int_q(58 to 63) when ((spr_match_mas3_2_q='1' or spr_match_mas73_64b_2_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else (others => '0') when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(2)='1') + else (tlb_mas3_usxwr(0 to 4) & (tlb_mas3_usxwr(5) and not tlb_mas1_ind)) when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(2)='1') + else (others => '0') when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(2)='1') + else mas3_2_usxwr_q; +mas4_2_indd_d <= spr_data_int_q(48) when (spr_match_mas4_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_2_indd_q; +mas4_2_tsized_d <= spr_data_int_q(52 to 55) when (spr_match_mas4_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_2_tsized_q; +mas4_2_wimged_d <= spr_data_int_q(59 to 63) when (spr_match_mas4_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_2_wimged_q; +mas6_2_spid_d <= spr_data_int_q(34 to 47) when ((spr_match_mas6_2_q='1' or spr_match_mas56_64b_2_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas6_spid when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(2)='1') + else mas6_2_spid_q; +mas6_2_isize_d <= spr_data_int_q(52 to 55) when ((spr_match_mas6_2_q='1' or spr_match_mas56_64b_2_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_2_tsized_q when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(2)='1') + else mas6_2_isize_q; +mas6_2_sind_d <= spr_data_int_q(62) when ((spr_match_mas6_2_q='1' or spr_match_mas56_64b_2_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_2_indd_q when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(2)='1') + else mas6_2_sind_q; +mas6_2_sas_d <= spr_data_int_q(63) when ((spr_match_mas6_2_q='1' or spr_match_mas56_64b_2_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas6_sas when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(2)='1') + else mas6_2_sas_q; +mas1_3_v_d <= spr_data_int_q(32) when ((spr_match_mas1_3_q='1' or spr_match_mas01_64b_3_q='1' or spr_match_mas81_64b_3_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else '0' when (tlb_mas_tlbsx_miss='1' and tlb_mas_thdid(3)='1') + else '1' when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(3)='1') + else tlb_mas1_v when (tlb_mas_tlbre='1' and tlb_mas_thdid(3)='1') + else '0' when (lrat_mas_tlbsx_miss='1' and lrat_mas_thdid(3)='1') + else '1' when (lrat_mas_tlbsx_hit='1' and lrat_mas_thdid(3)='1') + else lrat_mas1_v when (lrat_mas_tlbre='1' and lrat_mas_thdid(3)='1') + else mas1_3_v_q; +mas1_3_iprot_d <= spr_data_int_q(33) when ((spr_match_mas1_3_q='1' or spr_match_mas01_64b_3_q='1' or spr_match_mas81_64b_3_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else '0' when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(3)='1') + else tlb_mas1_iprot when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(3)='1') + else '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(3)='1') + else mas1_3_iprot_q; +mas1_3_tid_d <= spr_data_int_q(34 to 47) when ((spr_match_mas1_3_q='1' or spr_match_mas01_64b_3_q='1' or spr_match_mas81_64b_3_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else mas6_3_spid_q when ( tlb_mas_tlbsx_miss='1' and tlb_mas_thdid(3)='1') + else tlb_mas1_tid_error when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(3)='1') + else tlb_mas1_tid when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(3)='1') + else (others => '0') when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(3)='1') + else mas1_3_tid_q; +mas1_3_ind_d <= spr_data_int_q(50) when ((spr_match_mas1_3_q='1' or spr_match_mas01_64b_3_q='1' or spr_match_mas81_64b_3_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_3_indd_q when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(3)='1') + else tlb_mas1_ind when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(3)='1') + else '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(3)='1') + else mas1_3_ind_q; +mas1_3_ts_d <= spr_data_int_q(51) when ((spr_match_mas1_3_q='1' or spr_match_mas01_64b_3_q='1' or spr_match_mas81_64b_3_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else mas6_3_sas_q when ( tlb_mas_tlbsx_miss='1' and tlb_mas_thdid(3)='1') + else tlb_mas1_ts_error when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(3)='1') + else tlb_mas1_ts when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(3)='1') + else '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(3)='1') + else mas1_3_ts_q; +mas1_3_tsize_d <= spr_data_int_q(52 to 55) when ((spr_match_mas1_3_q='1' or spr_match_mas01_64b_3_q='1' or spr_match_mas81_64b_3_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_3_tsized_q when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(3)='1') + else tlb_mas1_tsize when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(3)='1') + else lrat_mas1_tsize when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(3)='1') + else mas1_3_tsize_q; +mas2_3_epn_d(32 to 51) <= spr_data_int_q(32 to 51) when (spr_match_mas2_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas2_epn_error(32 to 51) when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(3)='1') + else tlb_mas2_epn(32 to 51) when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(3)='1') + else lrat_mas2_epn(32 to 51) when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(3)='1') + else mas2_3_epn_q(32 to 51); +mas2_3_wimge_d <= spr_data_int_q(59 to 63) when (spr_match_mas2_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_3_wimged_q when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(3)='1') + else tlb_mas2_wimge when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(3)='1') + else (others => '0') when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(3)='1') + else mas2_3_wimge_q; +mas3_3_rpnl_d <= spr_data_int_q(32 to 52) + when ((spr_match_mas3_3_q='1' or spr_match_mas73_64b_3_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else (others => '0') when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(3)='1') + else tlb_mas3_rpnl & (tlb_mas3_usxwr(5) and tlb_mas1_ind) + when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(3)='1') + else lrat_mas3_rpnl & '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(3)='1') + else mas3_3_rpnl_q; +mas3_3_ubits_d <= spr_data_int_q(54 to 57) when ((spr_match_mas3_3_q='1' or spr_match_mas73_64b_3_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else (others => '0') when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(3)='1') + else tlb_mas3_ubits when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(3)='1') + else (others => '0') when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(3)='1') + else mas3_3_ubits_q; +mas3_3_usxwr_d <= spr_data_int_q(58 to 63) when ((spr_match_mas3_3_q='1' or spr_match_mas73_64b_3_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else (others => '0') when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(3)='1') + else (tlb_mas3_usxwr(0 to 4) & (tlb_mas3_usxwr(5) and not tlb_mas1_ind)) when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(3)='1') + else (others => '0') when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(3)='1') + else mas3_3_usxwr_q; +mas4_3_indd_d <= spr_data_int_q(48) when (spr_match_mas4_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_3_indd_q; +mas4_3_tsized_d <= spr_data_int_q(52 to 55) when (spr_match_mas4_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_3_tsized_q; +mas4_3_wimged_d <= spr_data_int_q(59 to 63) when (spr_match_mas4_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_3_wimged_q; +mas6_3_spid_d <= spr_data_int_q(34 to 47) when ((spr_match_mas6_3_q='1' or spr_match_mas56_64b_3_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas6_spid when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(3)='1') + else mas6_3_spid_q; +mas6_3_isize_d <= spr_data_int_q(52 to 55) when ((spr_match_mas6_3_q='1' or spr_match_mas56_64b_3_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_3_tsized_q when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(3)='1') + else mas6_3_isize_q; +mas6_3_sind_d <= spr_data_int_q(62) when ((spr_match_mas6_3_q='1' or spr_match_mas56_64b_3_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_3_indd_q when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(3)='1') + else mas6_3_sind_q; +mas6_3_sas_d <= spr_data_int_q(63) when ((spr_match_mas6_3_q='1' or spr_match_mas56_64b_3_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas6_sas when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(3)='1') + else mas6_3_sas_q; +gen32_mas_d: if spr_data_width = 32 generate +mas0_0_atsel_d <= spr_data_int_q(32) when (spr_match_mas0_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else '0' when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1' or + tlb_mas_tlbsx_hit='1' or tlb_mas_tlbsx_miss='1') and tlb_mas_thdid(0)='1') + else '1' when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbsx_miss='1') and lrat_mas_thdid(0)='1') + else mas0_0_atsel_q; +mas0_0_esel_d <= spr_data_int_q(45 to 47) when (spr_match_mas0_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas0_esel when ( (tlb_mas_tlbsx_hit='1') and tlb_mas_thdid(0)='1') + else (others => '0') when ((tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1' or + tlb_mas_tlbsx_miss='1') and tlb_mas_thdid(0)='1') + else lrat_mas0_esel when ( (lrat_mas_tlbsx_hit='1') and lrat_mas_thdid(0)='1') + else mas0_0_esel_q; +mas0_0_hes_d <= spr_data_int_q(49) when (spr_match_mas0_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else '1' when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1' or + tlb_mas_tlbsx_hit='1' or tlb_mas_tlbsx_miss='1') and tlb_mas_thdid(0)='1') + else mas0_0_hes_q; +mas0_0_wq_d <= spr_data_int_q(50 to 51) when (spr_match_mas0_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else "01" when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1' or + tlb_mas_tlbsx_hit='1' or tlb_mas_tlbsx_miss='1') and tlb_mas_thdid(0)='1') + else "00" when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbsx_miss='1') and lrat_mas_thdid(0)='1') + else mas0_0_wq_q; +mas5_0_sgs_d <= spr_data_int_q(32) when (spr_match_mas5_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas5_0_sgs_q; +mas5_0_slpid_d <= spr_data_int_q(56 to 63) when (spr_match_mas5_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas5_0_slpid_q; +mas7_0_rpnu_d <= spr_data_int_q(54 to 63) when (spr_match_mas7_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else (others => '0') when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(0)='1') + else tlb_mas7_rpnu when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(0)='1') + else lrat_mas7_rpnu when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(0)='1') + else mas7_0_rpnu_q; +mas8_0_tgs_d <= spr_data_int_q(32) when (spr_match_mas8_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas8_tgs when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(0)='1') + else '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(0)='1') + else mas8_0_tgs_q; +mas8_0_vf_d <= spr_data_int_q(33) when (spr_match_mas8_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas8_vf when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(0)='1') + else '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(0)='1') + else mas8_0_vf_q; +mas8_0_tlpid_d <= spr_data_int_q(56 to 63) when (spr_match_mas8_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas8_tlpid when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(0)='1') + else lrat_mas8_tlpid when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(0)='1') + else mas8_0_tlpid_q; +mas0_1_atsel_d <= spr_data_int_q(32) when (spr_match_mas0_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else '0' when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1' or + tlb_mas_tlbsx_hit='1' or tlb_mas_tlbsx_miss='1') and tlb_mas_thdid(1)='1') + else '1' when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbsx_miss='1') and lrat_mas_thdid(1)='1') + else mas0_1_atsel_q; +mas0_1_esel_d <= spr_data_int_q(45 to 47) when (spr_match_mas0_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas0_esel when ( (tlb_mas_tlbsx_hit='1') and tlb_mas_thdid(1)='1') + else (others => '0') when ((tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1' or + tlb_mas_tlbsx_miss='1') and tlb_mas_thdid(1)='1') + else lrat_mas0_esel when ( (lrat_mas_tlbsx_hit='1') and lrat_mas_thdid(1)='1') + else mas0_1_esel_q; +mas0_1_hes_d <= spr_data_int_q(49) when (spr_match_mas0_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else '1' when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1' or + tlb_mas_tlbsx_hit='1' or tlb_mas_tlbsx_miss='1') and tlb_mas_thdid(1)='1') + else mas0_1_hes_q; +mas0_1_wq_d <= spr_data_int_q(50 to 51) when (spr_match_mas0_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else "01" when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1' or + tlb_mas_tlbsx_hit='1' or tlb_mas_tlbsx_miss='1') and tlb_mas_thdid(1)='1') + else "00" when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbsx_miss='1') and lrat_mas_thdid(1)='1') + else mas0_1_wq_q; +mas5_1_sgs_d <= spr_data_int_q(32) when (spr_match_mas5_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas5_1_sgs_q; +mas5_1_slpid_d <= spr_data_int_q(56 to 63) when (spr_match_mas5_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas5_1_slpid_q; +mas7_1_rpnu_d <= spr_data_int_q(54 to 63) when (spr_match_mas7_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else (others => '0') when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(1)='1') + else tlb_mas7_rpnu when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(1)='1') + else lrat_mas7_rpnu when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(1)='1') + else mas7_1_rpnu_q; +mas8_1_tgs_d <= spr_data_int_q(32) when (spr_match_mas8_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas8_tgs when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(1)='1') + else '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(1)='1') + else mas8_1_tgs_q; +mas8_1_vf_d <= spr_data_int_q(33) when (spr_match_mas8_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas8_vf when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(1)='1') + else '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(1)='1') + else mas8_1_vf_q; +mas8_1_tlpid_d <= spr_data_int_q(56 to 63) when (spr_match_mas8_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas8_tlpid when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(1)='1') + else lrat_mas8_tlpid when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(1)='1') + else mas8_1_tlpid_q; +mas0_2_atsel_d <= spr_data_int_q(32) when (spr_match_mas0_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else '0' when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1' or + tlb_mas_tlbsx_hit='1' or tlb_mas_tlbsx_miss='1') and tlb_mas_thdid(2)='1') + else '1' when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbsx_miss='1') and lrat_mas_thdid(2)='1') + else mas0_2_atsel_q; +mas0_2_esel_d <= spr_data_int_q(45 to 47) when (spr_match_mas0_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas0_esel when ( (tlb_mas_tlbsx_hit='1') and tlb_mas_thdid(2)='1') + else (others => '0') when ((tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1' or + tlb_mas_tlbsx_miss='1') and tlb_mas_thdid(2)='1') + else lrat_mas0_esel when ( (lrat_mas_tlbsx_hit='1') and lrat_mas_thdid(2)='1') + else mas0_2_esel_q; +mas0_2_hes_d <= spr_data_int_q(49) when (spr_match_mas0_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else '1' when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1' or + tlb_mas_tlbsx_hit='1' or tlb_mas_tlbsx_miss='1') and tlb_mas_thdid(2)='1') + else mas0_2_hes_q; +mas0_2_wq_d <= spr_data_int_q(50 to 51) when (spr_match_mas0_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else "01" when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1' or + tlb_mas_tlbsx_hit='1' or tlb_mas_tlbsx_miss='1') and tlb_mas_thdid(2)='1') + else "00" when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbsx_miss='1') and lrat_mas_thdid(2)='1') + else mas0_2_wq_q; +mas5_2_sgs_d <= spr_data_int_q(32) when (spr_match_mas5_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas5_2_sgs_q; +mas5_2_slpid_d <= spr_data_int_q(56 to 63) when (spr_match_mas5_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas5_2_slpid_q; +mas7_2_rpnu_d <= spr_data_int_q(54 to 63) when (spr_match_mas7_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else (others => '0') when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(2)='1') + else tlb_mas7_rpnu when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(2)='1') + else lrat_mas7_rpnu when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(2)='1') + else mas7_2_rpnu_q; +mas8_2_tgs_d <= spr_data_int_q(32) when (spr_match_mas8_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas8_tgs when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(2)='1') + else '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(2)='1') + else mas8_2_tgs_q; +mas8_2_vf_d <= spr_data_int_q(33) when (spr_match_mas8_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas8_vf when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(2)='1') + else '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(2)='1') + else mas8_2_vf_q; +mas8_2_tlpid_d <= spr_data_int_q(56 to 63) when (spr_match_mas8_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas8_tlpid when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(2)='1') + else lrat_mas8_tlpid when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(2)='1') + else mas8_2_tlpid_q; +mas0_3_atsel_d <= spr_data_int_q(32) when (spr_match_mas0_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else '0' when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1' or + tlb_mas_tlbsx_hit='1' or tlb_mas_tlbsx_miss='1') and tlb_mas_thdid(3)='1') + else '1' when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbsx_miss='1') and lrat_mas_thdid(3)='1') + else mas0_3_atsel_q; +mas0_3_esel_d <= spr_data_int_q(45 to 47) when (spr_match_mas0_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas0_esel when ( (tlb_mas_tlbsx_hit='1') and tlb_mas_thdid(3)='1') + else (others => '0') when ((tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1' or + tlb_mas_tlbsx_miss='1') and tlb_mas_thdid(3)='1') + else lrat_mas0_esel when ( (lrat_mas_tlbsx_hit='1') and lrat_mas_thdid(3)='1') + else mas0_3_esel_q; +mas0_3_hes_d <= spr_data_int_q(49) when (spr_match_mas0_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else '1' when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1' or + tlb_mas_tlbsx_hit='1' or tlb_mas_tlbsx_miss='1') and tlb_mas_thdid(3)='1') + else mas0_3_hes_q; +mas0_3_wq_d <= spr_data_int_q(50 to 51) when (spr_match_mas0_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else "01" when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1' or + tlb_mas_tlbsx_hit='1' or tlb_mas_tlbsx_miss='1') and tlb_mas_thdid(3)='1') + else "00" when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbsx_miss='1') and lrat_mas_thdid(3)='1') + else mas0_3_wq_q; +mas5_3_sgs_d <= spr_data_int_q(32) when (spr_match_mas5_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas5_3_sgs_q; +mas5_3_slpid_d <= spr_data_int_q(56 to 63) when (spr_match_mas5_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas5_3_slpid_q; +mas7_3_rpnu_d <= spr_data_int_q(54 to 63) when (spr_match_mas7_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else (others => '0') when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(3)='1') + else tlb_mas7_rpnu when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(3)='1') + else lrat_mas7_rpnu when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(3)='1') + else mas7_3_rpnu_q; +mas8_3_tgs_d <= spr_data_int_q(32) when (spr_match_mas8_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas8_tgs when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(3)='1') + else '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(3)='1') + else mas8_3_tgs_q; +mas8_3_vf_d <= spr_data_int_q(33) when (spr_match_mas8_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas8_vf when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(3)='1') + else '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(3)='1') + else mas8_3_vf_q; +mas8_3_tlpid_d <= spr_data_int_q(56 to 63) when (spr_match_mas8_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas8_tlpid when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(3)='1') + else lrat_mas8_tlpid when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(3)='1') + else mas8_3_tlpid_q; +end generate gen32_mas_d; +gen64_mas_d: if spr_data_width = 64 generate +mas0_0_atsel_d <= spr_data_int_q(32) when (spr_match_mas0_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(0) when (spr_match_mas01_64b_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else '0' when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1' or + tlb_mas_tlbsx_hit='1' or tlb_mas_tlbsx_miss='1') and tlb_mas_thdid(0)='1') + else '1' when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbsx_miss='1') and lrat_mas_thdid(0)='1') + else mas0_0_atsel_q; +mas0_0_esel_d <= spr_data_int_q(45 to 47) when (spr_match_mas0_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(13 to 15) when (spr_match_mas01_64b_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas0_esel when ( (tlb_mas_tlbsx_hit='1') and tlb_mas_thdid(0)='1') + else (others => '0') when ((tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' + or tlb_mas_itlb_error='1') and tlb_mas_thdid(0)='1') + else lrat_mas0_esel when ( (lrat_mas_tlbsx_hit='1') and lrat_mas_thdid(0)='1') + else mas0_0_esel_q; +mas0_0_hes_d <= spr_data_int_q(49) when (spr_match_mas0_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(17) when (spr_match_mas01_64b_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else '1' when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1' or + tlb_mas_tlbsx_hit='1' or tlb_mas_tlbsx_miss='1') and tlb_mas_thdid(0)='1') + else mas0_0_hes_q; +mas0_0_wq_d <= spr_data_int_q(50 to 51) when (spr_match_mas0_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(18 to 19) when (spr_match_mas01_64b_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else "01" when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1' or + tlb_mas_tlbsx_hit='1' or tlb_mas_tlbsx_miss='1') and tlb_mas_thdid(0)='1') + else "00" when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbsx_miss='1') and lrat_mas_thdid(0)='1') + else mas0_0_wq_q; +mas2_0_epn_d(0 to 31) <= spr_data_int_q(32 to 63) when (spr_match_mas2u_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(0 to 31) when (spr_match_mas2_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas2_epn_error(0 to 31) when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(0)='1') + else tlb_mas2_epn(0 to 31) when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(0)='1') + else lrat_mas2_epn(0 to 31) when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(0)='1') + else mas2_0_epn_q(0 to 31); +mas5_0_sgs_d <= spr_data_int_q(32) when (spr_match_mas5_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(0) when (spr_match_mas56_64b_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas5_0_sgs_q; +mas5_0_slpid_d <= spr_data_int_q(56 to 63) when (spr_match_mas5_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(24 to 31) when (spr_match_mas56_64b_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas5_0_slpid_q; +mas7_0_rpnu_d <= spr_data_int_q(54 to 63) when (spr_match_mas7_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else (others => '0') when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(0)='1') + else spr_data_int_q(22 to 31) when (spr_match_mas73_64b_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas7_rpnu when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(0)='1') + else lrat_mas7_rpnu when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(0)='1') + else mas7_0_rpnu_q; +mas8_0_tgs_d <= spr_data_int_q(32) when (spr_match_mas8_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(0) when (spr_match_mas81_64b_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas8_tgs when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(0)='1') + else '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(0)='1') + else mas8_0_tgs_q; +mas8_0_vf_d <= spr_data_int_q(33) when (spr_match_mas8_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(1) when (spr_match_mas81_64b_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas8_vf when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(0)='1') + else '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(0)='1') + else mas8_0_vf_q; +mas8_0_tlpid_d <= spr_data_int_q(56 to 63) when (spr_match_mas8_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(24 to 31) when (spr_match_mas81_64b_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas8_tlpid when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(0)='1') + else lrat_mas8_tlpid when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(0)='1') + else mas8_0_tlpid_q; +mas0_1_atsel_d <= spr_data_int_q(32) when (spr_match_mas0_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(0) when (spr_match_mas01_64b_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else '0' when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1' or + tlb_mas_tlbsx_hit='1' or tlb_mas_tlbsx_miss='1') and tlb_mas_thdid(1)='1') + else '1' when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbsx_miss='1') and lrat_mas_thdid(1)='1') + else mas0_1_atsel_q; +mas0_1_esel_d <= spr_data_int_q(45 to 47) when (spr_match_mas0_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(13 to 15) when (spr_match_mas01_64b_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas0_esel when ( (tlb_mas_tlbsx_hit='1') and tlb_mas_thdid(1)='1') + else (others => '0') when ((tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' + or tlb_mas_itlb_error='1') and tlb_mas_thdid(1)='1') + else lrat_mas0_esel when ( (lrat_mas_tlbsx_hit='1') and lrat_mas_thdid(1)='1') + else mas0_1_esel_q; +mas0_1_hes_d <= spr_data_int_q(49) when (spr_match_mas0_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(17) when (spr_match_mas01_64b_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else '1' when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1' or + tlb_mas_tlbsx_hit='1' or tlb_mas_tlbsx_miss='1') and tlb_mas_thdid(1)='1') + else mas0_1_hes_q; +mas0_1_wq_d <= spr_data_int_q(50 to 51) when (spr_match_mas0_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(18 to 19) when (spr_match_mas01_64b_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else "01" when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1' or + tlb_mas_tlbsx_hit='1' or tlb_mas_tlbsx_miss='1') and tlb_mas_thdid(1)='1') + else "00" when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbsx_miss='1') and lrat_mas_thdid(1)='1') + else mas0_1_wq_q; +mas2_1_epn_d(0 to 31) <= spr_data_int_q(32 to 63) when (spr_match_mas2u_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(0 to 31) when (spr_match_mas2_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas2_epn_error(0 to 31) when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(1)='1') + else tlb_mas2_epn(0 to 31) when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(1)='1') + else lrat_mas2_epn(0 to 31) when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(1)='1') + else mas2_1_epn_q(0 to 31); +mas5_1_sgs_d <= spr_data_int_q(32) when (spr_match_mas5_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(0) when (spr_match_mas56_64b_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas5_1_sgs_q; +mas5_1_slpid_d <= spr_data_int_q(56 to 63) when (spr_match_mas5_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(24 to 31) when (spr_match_mas56_64b_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas5_1_slpid_q; +mas7_1_rpnu_d <= spr_data_int_q(54 to 63) when (spr_match_mas7_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else (others => '0') when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(1)='1') + else spr_data_int_q(22 to 31) when (spr_match_mas73_64b_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas7_rpnu when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(1)='1') + else lrat_mas7_rpnu when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(1)='1') + else mas7_1_rpnu_q; +mas8_1_tgs_d <= spr_data_int_q(32) when (spr_match_mas8_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(0) when (spr_match_mas81_64b_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas8_tgs when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(1)='1') + else '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(1)='1') + else mas8_1_tgs_q; +mas8_1_vf_d <= spr_data_int_q(33) when (spr_match_mas8_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(1) when (spr_match_mas81_64b_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas8_vf when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(1)='1') + else '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(1)='1') + else mas8_1_vf_q; +mas8_1_tlpid_d <= spr_data_int_q(56 to 63) when (spr_match_mas8_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(24 to 31) when (spr_match_mas81_64b_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas8_tlpid when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(1)='1') + else lrat_mas8_tlpid when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(1)='1') + else mas8_1_tlpid_q; +mas0_2_atsel_d <= spr_data_int_q(32) when (spr_match_mas0_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(0) when (spr_match_mas01_64b_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else '0' when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1' or + tlb_mas_tlbsx_hit='1' or tlb_mas_tlbsx_miss='1') and tlb_mas_thdid(2)='1') + else '1' when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbsx_miss='1') and lrat_mas_thdid(2)='1') + else mas0_2_atsel_q; +mas0_2_esel_d <= spr_data_int_q(45 to 47) when (spr_match_mas0_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(13 to 15) when (spr_match_mas01_64b_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas0_esel when ( (tlb_mas_tlbsx_hit='1') and tlb_mas_thdid(2)='1') + else (others => '0') when ((tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' + or tlb_mas_itlb_error='1') and tlb_mas_thdid(2)='1') + else lrat_mas0_esel when ( (lrat_mas_tlbsx_hit='1') and lrat_mas_thdid(2)='1') + else mas0_2_esel_q; +mas0_2_hes_d <= spr_data_int_q(49) when (spr_match_mas0_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(17) when (spr_match_mas01_64b_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else '1' when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1' or + tlb_mas_tlbsx_hit='1' or tlb_mas_tlbsx_miss='1') and tlb_mas_thdid(2)='1') + else mas0_2_hes_q; +mas0_2_wq_d <= spr_data_int_q(50 to 51) when (spr_match_mas0_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(18 to 19) when (spr_match_mas01_64b_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else "01" when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1' or + tlb_mas_tlbsx_hit='1' or tlb_mas_tlbsx_miss='1') and tlb_mas_thdid(2)='1') + else "00" when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbsx_miss='1') and lrat_mas_thdid(2)='1') + else mas0_2_wq_q; +mas2_2_epn_d(0 to 31) <= spr_data_int_q(32 to 63) when (spr_match_mas2u_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(0 to 31) when (spr_match_mas2_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas2_epn_error(0 to 31) when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(2)='1') + else tlb_mas2_epn(0 to 31) when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(2)='1') + else lrat_mas2_epn(0 to 31) when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(2)='1') + else mas2_2_epn_q(0 to 31); +mas5_2_sgs_d <= spr_data_int_q(32) when (spr_match_mas5_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(0) when (spr_match_mas56_64b_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas5_2_sgs_q; +mas5_2_slpid_d <= spr_data_int_q(56 to 63) when (spr_match_mas5_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(24 to 31) when (spr_match_mas56_64b_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas5_2_slpid_q; +mas7_2_rpnu_d <= spr_data_int_q(54 to 63) when (spr_match_mas7_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else (others => '0') when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(2)='1') + else spr_data_int_q(22 to 31) when (spr_match_mas73_64b_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas7_rpnu when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(2)='1') + else lrat_mas7_rpnu when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(2)='1') + else mas7_2_rpnu_q; +mas8_2_tgs_d <= spr_data_int_q(32) when (spr_match_mas8_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(0) when (spr_match_mas81_64b_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas8_tgs when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(2)='1') + else '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(2)='1') + else mas8_2_tgs_q; +mas8_2_vf_d <= spr_data_int_q(33) when (spr_match_mas8_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(1) when (spr_match_mas81_64b_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas8_vf when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(2)='1') + else '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(2)='1') + else mas8_2_vf_q; +mas8_2_tlpid_d <= spr_data_int_q(56 to 63) when (spr_match_mas8_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(24 to 31) when (spr_match_mas81_64b_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas8_tlpid when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(2)='1') + else lrat_mas8_tlpid when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(2)='1') + else mas8_2_tlpid_q; +mas0_3_atsel_d <= spr_data_int_q(32) when (spr_match_mas0_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(0) when (spr_match_mas01_64b_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else '0' when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1' or + tlb_mas_tlbsx_hit='1' or tlb_mas_tlbsx_miss='1') and tlb_mas_thdid(3)='1') + else '1' when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbsx_miss='1') and lrat_mas_thdid(3)='1') + else mas0_3_atsel_q; +mas0_3_esel_d <= spr_data_int_q(45 to 47) when (spr_match_mas0_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(13 to 15) when (spr_match_mas01_64b_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas0_esel when ( (tlb_mas_tlbsx_hit='1') and tlb_mas_thdid(3)='1') + else (others => '0') when ((tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' + or tlb_mas_itlb_error='1') and tlb_mas_thdid(3)='1') + else lrat_mas0_esel when ( (lrat_mas_tlbsx_hit='1') and lrat_mas_thdid(3)='1') + else mas0_3_esel_q; +mas0_3_hes_d <= spr_data_int_q(49) when (spr_match_mas0_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(17) when (spr_match_mas01_64b_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else '1' when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1' or + tlb_mas_tlbsx_hit='1' or tlb_mas_tlbsx_miss='1') and tlb_mas_thdid(3)='1') + else mas0_3_hes_q; +mas0_3_wq_d <= spr_data_int_q(50 to 51) when (spr_match_mas0_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(18 to 19) when (spr_match_mas01_64b_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else "01" when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1' or + tlb_mas_tlbsx_hit='1' or tlb_mas_tlbsx_miss='1') and tlb_mas_thdid(3)='1') + else "00" when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbsx_miss='1') and lrat_mas_thdid(3)='1') + else mas0_3_wq_q; +mas2_3_epn_d(0 to 31) <= spr_data_int_q(32 to 63) when (spr_match_mas2u_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(0 to 31) when (spr_match_mas2_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas2_epn_error(0 to 31) when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(3)='1') + else tlb_mas2_epn(0 to 31) when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(3)='1') + else lrat_mas2_epn(0 to 31) when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(3)='1') + else mas2_3_epn_q(0 to 31); +mas5_3_sgs_d <= spr_data_int_q(32) when (spr_match_mas5_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(0) when (spr_match_mas56_64b_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas5_3_sgs_q; +mas5_3_slpid_d <= spr_data_int_q(56 to 63) when (spr_match_mas5_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(24 to 31) when (spr_match_mas56_64b_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas5_3_slpid_q; +mas7_3_rpnu_d <= spr_data_int_q(54 to 63) when (spr_match_mas7_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else (others => '0') when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(3)='1') + else spr_data_int_q(22 to 31) when (spr_match_mas73_64b_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas7_rpnu when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(3)='1') + else lrat_mas7_rpnu when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(3)='1') + else mas7_3_rpnu_q; +mas8_3_tgs_d <= spr_data_int_q(32) when (spr_match_mas8_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(0) when (spr_match_mas81_64b_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas8_tgs when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(3)='1') + else '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(3)='1') + else mas8_3_tgs_q; +mas8_3_vf_d <= spr_data_int_q(33) when (spr_match_mas8_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(1) when (spr_match_mas81_64b_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas8_vf when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(3)='1') + else '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(3)='1') + else mas8_3_vf_q; +mas8_3_tlpid_d <= spr_data_int_q(56 to 63) when (spr_match_mas8_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(24 to 31) when (spr_match_mas81_64b_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas8_tlpid when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(3)='1') + else lrat_mas8_tlpid when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(3)='1') + else mas8_3_tlpid_q; +end generate gen64_mas_d; +spr_ctl_out_d(0) <= spr_ctl_int_q(0); +spr_ctl_out_d(1) <= spr_ctl_int_q(1); +spr_ctl_out_d(2) <= spr_ctl_int_q(2) or spr_match_any_mmu_q; +spr_etid_out_d <= spr_etid_int_q; +spr_addr_out_d <= spr_addr_int_q; +spr_data_out_d(32 to 63) <= + ( ((32 to 63-pid_width => '0') & pid0_q) and (32 to 63 => (spr_match_pid0_q and spr_ctl_int_q(1))) ) or + ( ((32 to 63-pid_width => '0') & pid1_q) and (32 to 63 => (spr_match_pid1_q and spr_ctl_int_q(1))) ) or + ( ((32 to 63-pid_width => '0') & pid2_q) and (32 to 63 => (spr_match_pid2_q and spr_ctl_int_q(1))) ) or + ( ((32 to 63-pid_width => '0') & pid3_q) and (32 to 63 => (spr_match_pid3_q and spr_ctl_int_q(1))) ) or + ( ((32 to 55 => '0') & lpidr_q) and (32 to 63 => (spr_match_lpidr_q and spr_ctl_int_q(1))) ) or + ( (mmucr0_0_q(0 to 5) & (38 to 49 => '0') & mmucr0_0_q(6 to 19)) and (32 to 63 => (spr_match_mmucr0_0_q and spr_ctl_int_q(1))) ) or + ( (mmucr0_1_q(0 to 5) & (38 to 49 => '0') & mmucr0_1_q(6 to 19)) and (32 to 63 => (spr_match_mmucr0_1_q and spr_ctl_int_q(1))) ) or + ( (mmucr0_2_q(0 to 5) & (38 to 49 => '0') & mmucr0_2_q(6 to 19)) and (32 to 63 => (spr_match_mmucr0_2_q and spr_ctl_int_q(1))) ) or + ( (mmucr0_3_q(0 to 5) & (38 to 49 => '0') & mmucr0_3_q(6 to 19)) and (32 to 63 => (spr_match_mmucr0_3_q and spr_ctl_int_q(1))) ) or + ( mmucr1_q and (32 to 63 => (spr_match_mmucr1_q and spr_ctl_int_q(1))) ) or + ( mmucr2_q and (32 to 63 => (spr_match_mmucr2_q and spr_ctl_int_q(1))) ) or + ( ((32 to 63-mmucr3_width => '0') & mmucr3_0_q(64-mmucr3_width to 58) & '0' & mmucr3_0_q(60 to 63)) and (32 to 63 => (spr_match_mmucr3_0_q and spr_ctl_int_q(1))) ) or + ( ((32 to 63-mmucr3_width => '0') & mmucr3_1_q(64-mmucr3_width to 58) & '0' & mmucr3_1_q(60 to 63)) and (32 to 63 => (spr_match_mmucr3_1_q and spr_ctl_int_q(1))) ) or + ( ((32 to 63-mmucr3_width => '0') & mmucr3_2_q(64-mmucr3_width to 58) & '0' & mmucr3_2_q(60 to 63)) and (32 to 63 => (spr_match_mmucr3_2_q and spr_ctl_int_q(1))) ) or + ( ((32 to 63-mmucr3_width => '0') & mmucr3_3_q(64-mmucr3_width to 58) & '0' & mmucr3_3_q(60 to 63)) and (32 to 63 => (spr_match_mmucr3_3_q and spr_ctl_int_q(1))) ) or + ( ((32 to 60 => '0') & mmucsr0_tlb0fi_q & "00") and (32 to 63 => (spr_match_mmucsr0_q and spr_ctl_int_q(1))) ) or + ( (Spr_Data_MMUCFG(32 to 46) & mmucfg_q(47 to 48) & Spr_Data_MMUCFG(49 to 63)) and (32 to 63 => (spr_match_mmucfg_q and spr_ctl_int_q(1))) ) or + ( (Spr_Data_TLB0CFG(32 to 44) & tlb0cfg_q(45 to 47) & Spr_Data_TLB0CFG(48 to 63)) and (32 to 63 => (spr_match_tlb0cfg_q and spr_ctl_int_q(1))) ) or + ( (Spr_Data_TLB0PS) and (32 to 63 => (spr_match_tlb0ps_q and spr_ctl_int_q(1))) ) or + ( (Spr_Data_LRATCFG) and (32 to 63 => (spr_match_lratcfg_q and spr_ctl_int_q(1))) ) or + ( (Spr_Data_LRATPS) and (32 to 63 => (spr_match_lratps_q and spr_ctl_int_q(1))) ) or + ( (Spr_Data_EPTCFG) and (32 to 63 => (spr_match_eptcfg_q and spr_ctl_int_q(1))) ) or + ( (lper_0_alpn_q(32 to 51) & (52 to 59 => '0') & lper_0_lps_q(60 to 63)) and (32 to 63 => (spr_match_lper_0_q and spr_ctl_int_q(1))) ) or + ( (lper_1_alpn_q(32 to 51) & (52 to 59 => '0') & lper_1_lps_q(60 to 63)) and (32 to 63 => (spr_match_lper_1_q and spr_ctl_int_q(1))) ) or + ( (lper_2_alpn_q(32 to 51) & (52 to 59 => '0') & lper_2_lps_q(60 to 63)) and (32 to 63 => (spr_match_lper_2_q and spr_ctl_int_q(1))) ) or + ( (lper_3_alpn_q(32 to 51) & (52 to 59 => '0') & lper_3_lps_q(60 to 63)) and (32 to 63 => (spr_match_lper_3_q and spr_ctl_int_q(1))) ) or + ( ((32 to 63-real_addr_width+32 => '0') & lper_0_alpn_q(64-real_addr_width to 31)) and (32 to 63 => (spr_match_lperu_0_q and spr_ctl_int_q(1))) ) or + ( ((32 to 63-real_addr_width+32 => '0') & lper_1_alpn_q(64-real_addr_width to 31)) and (32 to 63 => (spr_match_lperu_1_q and spr_ctl_int_q(1))) ) or + ( ((32 to 63-real_addr_width+32 => '0') & lper_2_alpn_q(64-real_addr_width to 31)) and (32 to 63 => (spr_match_lperu_2_q and spr_ctl_int_q(1))) ) or + ( ((32 to 63-real_addr_width+32 => '0') & lper_3_alpn_q(64-real_addr_width to 31)) and (32 to 63 => (spr_match_lperu_3_q and spr_ctl_int_q(1))) ) or + ( (spr_mas_data_out_q(32 to 63)) and (32 to 63 => (spr_match_any_mas_q and spr_ctl_int_q(1))) ) or + ( spr_data_int_q(32 to 63) and (32 to 63 => not spr_match_any_mmu_q) ); +spr_mas_data_out(32 to 63) <= + ( (mas0_0_atsel_q & (33 to 44 => '0') & mas0_0_esel_q & '0' & mas0_0_hes_q & mas0_0_wq_q & (52 to 63 => '0')) + and (32 to 63 => spr_match_mas0_0) ) or + ( (mas1_0_v_q & mas1_0_iprot_q & mas1_0_tid_q & "00" & mas1_0_ind_q & mas1_0_ts_q & mas1_0_tsize_q & "00000000") + and (32 to 63 => (spr_match_mas1_0 or spr_match_mas01_64b_0 or spr_match_mas81_64b_0)) ) or + ( (mas2_0_epn_q(32 to 51) & "0000000" & mas2_0_wimge_q) + and (32 to 63 => spr_match_mas2_0) ) or + ( (mas2_0_epn_q(0 to 31) ) + and (32 to 63 => spr_match_mas2u_0) ) or + ( (mas3_0_rpnl_q & '0' & mas3_0_ubits_q & mas3_0_usxwr_q) + and (32 to 63 => (spr_match_mas3_0 or spr_match_mas73_64b_0)) ) or + ( ((32 to 47 => '0') & mas4_0_indd_q & "000" & mas4_0_tsized_q & "000" & mas4_0_wimged_q) + and (32 to 63 => spr_match_mas4_0) ) or + ( (mas5_0_sgs_q & (33 to 55 => '0') & mas5_0_slpid_q) + and (32 to 63 => spr_match_mas5_0) ) or + ( ("00" & mas6_0_spid_q & "0000" & mas6_0_isize_q & "000000" & mas6_0_sind_q & mas6_0_sas_q) + and (32 to 63 => (spr_match_mas6_0 or spr_match_mas56_64b_0)) ) or + ( ((32 to 53 => '0') & mas7_0_rpnu_q) + and (32 to 63 => spr_match_mas7_0) ) or + ( (mas8_0_tgs_q & mas8_0_vf_q & (34 to 55 => '0') & mas8_0_tlpid_q) + and (32 to 63 => spr_match_mas8_0) ) or + ( (mas0_1_atsel_q & (33 to 44 => '0') & mas0_1_esel_q & '0' & mas0_1_hes_q & mas0_1_wq_q & (52 to 63 => '0')) + and (32 to 63 => spr_match_mas0_1) ) or + ( (mas1_1_v_q & mas1_1_iprot_q & mas1_1_tid_q & "00" & mas1_1_ind_q & mas1_1_ts_q & mas1_1_tsize_q & "00000000") + and (32 to 63 => (spr_match_mas1_1 or spr_match_mas01_64b_1 or spr_match_mas81_64b_1)) ) or + ( (mas2_1_epn_q(32 to 51) & "0000000" & mas2_1_wimge_q) + and (32 to 63 => spr_match_mas2_1) ) or + ( (mas2_1_epn_q(0 to 31) ) + and (32 to 63 => spr_match_mas2u_1) ) or + ( (mas3_1_rpnl_q & '0' & mas3_1_ubits_q & mas3_1_usxwr_q) + and (32 to 63 => (spr_match_mas3_1 or spr_match_mas73_64b_1)) ) or + ( ((32 to 47 => '0') & mas4_1_indd_q & "000" & mas4_1_tsized_q & "000" & mas4_1_wimged_q) + and (32 to 63 => spr_match_mas4_1) ) or + ( (mas5_1_sgs_q & (33 to 55 => '0') & mas5_1_slpid_q) + and (32 to 63 => spr_match_mas5_1) ) or + ( ("00" & mas6_1_spid_q & "0000" & mas6_1_isize_q & "000000" & mas6_1_sind_q & mas6_1_sas_q) + and (32 to 63 => (spr_match_mas6_1 or spr_match_mas56_64b_1)) ) or + ( ((32 to 53 => '0') & mas7_1_rpnu_q) + and (32 to 63 => spr_match_mas7_1) ) or + ( (mas8_1_tgs_q & mas8_1_vf_q & (34 to 55 => '0') & mas8_1_tlpid_q) + and (32 to 63 => spr_match_mas8_1) ) or + ( (mas0_2_atsel_q & (33 to 44 => '0') & mas0_2_esel_q & '0' & mas0_2_hes_q & mas0_2_wq_q & (52 to 63 => '0')) + and (32 to 63 => spr_match_mas0_2) ) or + ( (mas1_2_v_q & mas1_2_iprot_q & mas1_2_tid_q & "00" & mas1_2_ind_q & mas1_2_ts_q & mas1_2_tsize_q & "00000000") + and (32 to 63 => (spr_match_mas1_2 or spr_match_mas01_64b_2 or spr_match_mas81_64b_2)) ) or + ( (mas2_2_epn_q(32 to 51) & "0000000" & mas2_2_wimge_q) + and (32 to 63 => spr_match_mas2_2) ) or + ( (mas2_2_epn_q(0 to 31) ) + and (32 to 63 => spr_match_mas2u_2) ) or + ( (mas3_2_rpnl_q & '0' & mas3_2_ubits_q & mas3_2_usxwr_q) + and (32 to 63 => (spr_match_mas3_2 or spr_match_mas73_64b_2)) ) or + ( ((32 to 47 => '0') & mas4_2_indd_q & "000" & mas4_2_tsized_q & "000" & mas4_2_wimged_q) + and (32 to 63 => spr_match_mas4_2) ) or + ( (mas5_2_sgs_q & (33 to 55 => '0') & mas5_2_slpid_q) + and (32 to 63 => spr_match_mas5_2) ) or + ( ("00" & mas6_2_spid_q & "0000" & mas6_2_isize_q & "000000" & mas6_2_sind_q & mas6_2_sas_q) + and (32 to 63 => (spr_match_mas6_2 or spr_match_mas56_64b_2)) ) or + ( ((32 to 53 => '0') & mas7_2_rpnu_q) + and (32 to 63 => spr_match_mas7_2) ) or + ( (mas8_2_tgs_q & mas8_2_vf_q & (34 to 55 => '0') & mas8_2_tlpid_q) + and (32 to 63 => spr_match_mas8_2) ) or + ( (mas0_3_atsel_q & (33 to 44 => '0') & mas0_3_esel_q & '0' & mas0_3_hes_q & mas0_3_wq_q & (52 to 63 => '0')) + and (32 to 63 => spr_match_mas0_3) ) or + ( (mas1_3_v_q & mas1_3_iprot_q & mas1_3_tid_q & "00" & mas1_3_ind_q & mas1_3_ts_q & mas1_3_tsize_q & "00000000") + and (32 to 63 => (spr_match_mas1_3 or spr_match_mas01_64b_3 or spr_match_mas81_64b_3)) ) or + ( (mas2_3_epn_q(32 to 51) & "0000000" & mas2_3_wimge_q) + and (32 to 63 => spr_match_mas2_3) ) or + ( (mas2_3_epn_q(0 to 31) ) + and (32 to 63 => spr_match_mas2u_3) ) or + ( (mas3_3_rpnl_q & '0' & mas3_3_ubits_q & mas3_3_usxwr_q) + and (32 to 63 => (spr_match_mas3_3 or spr_match_mas73_64b_3)) ) or + ( ((32 to 47 => '0') & mas4_3_indd_q & "000" & mas4_3_tsized_q & "000" & mas4_3_wimged_q) + and (32 to 63 => spr_match_mas4_3) ) or + ( (mas5_3_sgs_q & (33 to 55 => '0') & mas5_3_slpid_q) + and (32 to 63 => spr_match_mas5_3) ) or + ( ("00" & mas6_3_spid_q & "0000" & mas6_3_isize_q & "000000" & mas6_3_sind_q & mas6_3_sas_q) + and (32 to 63 => (spr_match_mas6_3 or spr_match_mas56_64b_3)) ) or + ( ((32 to 53 => '0') & mas7_3_rpnu_q) + and (32 to 63 => spr_match_mas7_3) ) or + ( (mas8_3_tgs_q & mas8_3_vf_q & (34 to 55 => '0') & mas8_3_tlpid_q) + and (32 to 63 => spr_match_mas8_3) ); +gen64_spr_data: if spr_data_width = 64 generate +spr_mas_data_out(0 to 31) <= + ( mas2_0_epn_q(0 to 31) + and (0 to 31 => spr_match_mas2_0) ) or + ( (mas0_0_atsel_q & (1 to 12 => '0') & mas0_0_esel_q & '0' & mas0_0_hes_q & mas0_0_wq_q & (20 to 31 => '0')) + and (0 to 31 => spr_match_mas01_64b_0) ) or + ( (mas5_0_sgs_q & (1 to 23 => '0') & mas5_0_slpid_q) + and (0 to 31 => spr_match_mas56_64b_0) ) or + ( ((0 to 21 => '0') & mas7_0_rpnu_q) + and (0 to 31 => spr_match_mas73_64b_0) ) or + ( (mas8_0_tgs_q & mas8_0_vf_q & (34 to 55 => '0') & mas8_0_tlpid_q) + and (0 to 31 => spr_match_mas81_64b_0) ) or + ( mas2_1_epn_q(0 to 31) + and (0 to 31 => spr_match_mas2_1) ) or + ( (mas0_1_atsel_q & (1 to 12 => '0') & mas0_1_esel_q & '0' & mas0_1_hes_q & mas0_1_wq_q & (20 to 31 => '0')) + and (0 to 31 => spr_match_mas01_64b_1) ) or + ( (mas5_1_sgs_q & (1 to 23 => '0') & mas5_1_slpid_q) + and (0 to 31 => spr_match_mas56_64b_1) ) or + ( ((0 to 21 => '0') & mas7_1_rpnu_q) + and (0 to 31 => spr_match_mas73_64b_1) ) or + ( (mas8_1_tgs_q & mas8_1_vf_q & (34 to 55 => '0') & mas8_1_tlpid_q) + and (0 to 31 => spr_match_mas81_64b_1) ) or + ( mas2_2_epn_q(0 to 31) + and (0 to 31 => spr_match_mas2_2) ) or + ( (mas0_2_atsel_q & (1 to 12 => '0') & mas0_2_esel_q & '0' & mas0_2_hes_q & mas0_2_wq_q & (20 to 31 => '0')) + and (0 to 31 => spr_match_mas01_64b_2) ) or + ( (mas5_2_sgs_q & (1 to 23 => '0') & mas5_2_slpid_q) + and (0 to 31 => spr_match_mas56_64b_2) ) or + ( ((0 to 21 => '0') & mas7_2_rpnu_q) + and (0 to 31 => spr_match_mas73_64b_2) ) or + ( (mas8_2_tgs_q & mas8_2_vf_q & (34 to 55 => '0') & mas8_2_tlpid_q) + and (0 to 31 => spr_match_mas81_64b_2) ) or + ( mas2_3_epn_q(0 to 31) + and (0 to 31 => spr_match_mas2_3) ) or + ( (mas0_3_atsel_q & (1 to 12 => '0') & mas0_3_esel_q & '0' & mas0_3_hes_q & mas0_3_wq_q & (20 to 31 => '0')) + and (0 to 31 => spr_match_mas01_64b_3) ) or + ( (mas5_3_sgs_q & (1 to 23 => '0') & mas5_3_slpid_q) + and (0 to 31 => spr_match_mas56_64b_3) ) or + ( ((0 to 21 => '0') & mas7_3_rpnu_q) + and (0 to 31 => spr_match_mas73_64b_3) ) or + ( (mas8_3_tgs_q & mas8_3_vf_q & (34 to 55 => '0') & mas8_3_tlpid_q) + and (0 to 31 => spr_match_mas81_64b_3) ); +spr_data_out_d(0 to 31) <= ( ((0 to 63-real_addr_width => '0') & lper_0_alpn_q(64-real_addr_width to 31)) + and (0 to 31 => (spr_match_lper_0_q and spr_ctl_int_q(1))) ) or + ( ((0 to 63-real_addr_width => '0') & lper_1_alpn_q(64-real_addr_width to 31)) + and (0 to 31 => (spr_match_lper_1_q and spr_ctl_int_q(1))) ) or + ( ((0 to 63-real_addr_width => '0') & lper_2_alpn_q(64-real_addr_width to 31)) + and (0 to 31 => (spr_match_lper_2_q and spr_ctl_int_q(1))) ) or + ( ((0 to 63-real_addr_width => '0') & lper_3_alpn_q(64-real_addr_width to 31)) + and (0 to 31 => (spr_match_lper_3_q and spr_ctl_int_q(1))) ) or + ( spr_mas_data_out_q(0 to 31) and (0 to 31 => (spr_match_any_mas_q and spr_ctl_int_q(1))) ) or + ( spr_data_int_q(0 to 31) and (0 to 31 => (not(spr_match_any_mmu_q) or not(spr_ctl_int_q(1)))) ); +end generate gen64_spr_data; +mm_iu_slowspr_val <= spr_ctl_out_q(0); +mm_iu_slowspr_rw <= spr_ctl_out_q(1); +mm_iu_slowspr_etid <= spr_etid_out_q; +mm_iu_slowspr_addr <= spr_addr_out_q; +mm_iu_slowspr_data <= spr_data_out_q; +mm_iu_slowspr_done <= spr_ctl_out_q(2); +mm_iu_ierat_pid0 <= pid0_q; +mm_iu_ierat_pid1 <= pid1_q; +mm_iu_ierat_pid2 <= pid2_q; +mm_iu_ierat_pid3 <= pid3_q; +mm_iu_ierat_mmucr0_0 <= mmucr0_0_q; +mm_iu_ierat_mmucr0_1 <= mmucr0_1_q; +mm_iu_ierat_mmucr0_2 <= mmucr0_2_q; +mm_iu_ierat_mmucr0_3 <= mmucr0_3_q; +mm_iu_ierat_mmucr1 <= mmucr1_q(0) & mmucr1_q(2 to 5) & mmucr1_q(6 to 7) & mmucr1_q(12 to 13); +mm_xu_derat_pid0 <= pid0_q; +mm_xu_derat_pid1 <= pid1_q; +mm_xu_derat_pid2 <= pid2_q; +mm_xu_derat_pid3 <= pid3_q; +mm_xu_derat_mmucr0_0 <= mmucr0_0_q; +mm_xu_derat_mmucr0_1 <= mmucr0_1_q; +mm_xu_derat_mmucr0_2 <= mmucr0_2_q; +mm_xu_derat_mmucr0_3 <= mmucr0_3_q; +mm_xu_derat_mmucr1 <= mmucr1_q(1) & mmucr1_q(2 to 5) & mmucr1_q(8 to 9) & mmucr1_q(14 to 16); +pid0 <= pid0_q; +pid1 <= pid1_q; +pid2 <= pid2_q; +pid3 <= pid3_q; +mmucr0_0 <= mmucr0_0_q; +mmucr0_1 <= mmucr0_1_q; +mmucr0_2 <= mmucr0_2_q; +mmucr0_3 <= mmucr0_3_q; +mmucr1 <= mmucr1_q; +mmucr2 <= mmucr2_q; +mmucr3_0 <= mmucr3_0_q; +mmucr3_1 <= mmucr3_1_q; +mmucr3_2 <= mmucr3_2_q; +mmucr3_3 <= mmucr3_3_q; +lpidr <= lpidr_q; +ac_an_lpar_id <= lpidr_q; +mmucfg_lrat <= mmucfg_q(47); +mmucfg_twc <= mmucfg_q(48); +tlb0cfg_pt <= tlb0cfg_q(45); +tlb0cfg_ind <= tlb0cfg_q(46); +tlb0cfg_gtwe <= tlb0cfg_q(47); +mas0_0_atsel <= mas0_0_atsel_q; +mas0_0_esel <= mas0_0_esel_q; +mas0_0_hes <= mas0_0_hes_q; +mas0_0_wq <= mas0_0_wq_q; +mas1_0_v <= mas1_0_v_q; +mas1_0_iprot <= mas1_0_iprot_q; +mas1_0_tid <= mas1_0_tid_q; +mas1_0_ind <= mas1_0_ind_q; +mas1_0_ts <= mas1_0_ts_q; +mas1_0_tsize <= mas1_0_tsize_q; +gen32_mas2_0_epn: if spr_data_width = 32 generate +mas2_0_epn(0 to 31) <=(others => '0'); +mas2_0_epn(32 to 51) <= mas2_0_epn_q(32 to 51); +end generate gen32_mas2_0_epn; +gen64_mas2_0_epn: if spr_data_width = 64 generate +mas2_0_epn <= mas2_0_epn_q; +end generate gen64_mas2_0_epn; +mas2_0_wimge <= mas2_0_wimge_q; +mas3_0_rpnl <= mas3_0_rpnl_q; +mas3_0_ubits <= mas3_0_ubits_q; +mas3_0_usxwr <= mas3_0_usxwr_q; +mas5_0_sgs <= mas5_0_sgs_q; +mas5_0_slpid <= mas5_0_slpid_q; +mas6_0_spid <= mas6_0_spid_q; +mas6_0_isize <= mas6_0_isize_q; +mas6_0_sind <= mas6_0_sind_q; +mas6_0_sas <= mas6_0_sas_q; +mas7_0_rpnu <= mas7_0_rpnu_q; +mas8_0_tgs <= mas8_0_tgs_q; +mas8_0_vf <= mas8_0_vf_q; +mas8_0_tlpid <= mas8_0_tlpid_q; +mas0_1_atsel <= mas0_1_atsel_q; +mas0_1_esel <= mas0_1_esel_q; +mas0_1_hes <= mas0_1_hes_q; +mas0_1_wq <= mas0_1_wq_q; +mas1_1_v <= mas1_1_v_q; +mas1_1_iprot <= mas1_1_iprot_q; +mas1_1_tid <= mas1_1_tid_q; +mas1_1_ind <= mas1_1_ind_q; +mas1_1_ts <= mas1_1_ts_q; +mas1_1_tsize <= mas1_1_tsize_q; +gen32_mas2_1_epn: if spr_data_width = 32 generate +mas2_1_epn(0 to 31) <=(others => '0'); +mas2_1_epn(32 to 51) <= mas2_1_epn_q(32 to 51); +end generate gen32_mas2_1_epn; +gen64_mas2_1_epn: if spr_data_width = 64 generate +mas2_1_epn <= mas2_1_epn_q; +end generate gen64_mas2_1_epn; +mas2_1_wimge <= mas2_1_wimge_q; +mas3_1_rpnl <= mas3_1_rpnl_q; +mas3_1_ubits <= mas3_1_ubits_q; +mas3_1_usxwr <= mas3_1_usxwr_q; +mas5_1_sgs <= mas5_1_sgs_q; +mas5_1_slpid <= mas5_1_slpid_q; +mas6_1_spid <= mas6_1_spid_q; +mas6_1_isize <= mas6_1_isize_q; +mas6_1_sind <= mas6_1_sind_q; +mas6_1_sas <= mas6_1_sas_q; +mas7_1_rpnu <= mas7_1_rpnu_q; +mas8_1_tgs <= mas8_1_tgs_q; +mas8_1_vf <= mas8_1_vf_q; +mas8_1_tlpid <= mas8_1_tlpid_q; +mas0_2_atsel <= mas0_2_atsel_q; +mas0_2_esel <= mas0_2_esel_q; +mas0_2_hes <= mas0_2_hes_q; +mas0_2_wq <= mas0_2_wq_q; +mas1_2_v <= mas1_2_v_q; +mas1_2_iprot <= mas1_2_iprot_q; +mas1_2_tid <= mas1_2_tid_q; +mas1_2_ind <= mas1_2_ind_q; +mas1_2_ts <= mas1_2_ts_q; +mas1_2_tsize <= mas1_2_tsize_q; +gen32_mas2_2_epn: if spr_data_width = 32 generate +mas2_2_epn(0 to 31) <=(others => '0'); +mas2_2_epn(32 to 51) <= mas2_2_epn_q(32 to 51); +end generate gen32_mas2_2_epn; +gen64_mas2_2_epn: if spr_data_width = 64 generate +mas2_2_epn <= mas2_2_epn_q; +end generate gen64_mas2_2_epn; +mas2_2_wimge <= mas2_2_wimge_q; +mas3_2_rpnl <= mas3_2_rpnl_q; +mas3_2_ubits <= mas3_2_ubits_q; +mas3_2_usxwr <= mas3_2_usxwr_q; +mas5_2_sgs <= mas5_2_sgs_q; +mas5_2_slpid <= mas5_2_slpid_q; +mas6_2_spid <= mas6_2_spid_q; +mas6_2_isize <= mas6_2_isize_q; +mas6_2_sind <= mas6_2_sind_q; +mas6_2_sas <= mas6_2_sas_q; +mas7_2_rpnu <= mas7_2_rpnu_q; +mas8_2_tgs <= mas8_2_tgs_q; +mas8_2_vf <= mas8_2_vf_q; +mas8_2_tlpid <= mas8_2_tlpid_q; +mas0_3_atsel <= mas0_3_atsel_q; +mas0_3_esel <= mas0_3_esel_q; +mas0_3_hes <= mas0_3_hes_q; +mas0_3_wq <= mas0_3_wq_q; +mas1_3_v <= mas1_3_v_q; +mas1_3_iprot <= mas1_3_iprot_q; +mas1_3_tid <= mas1_3_tid_q; +mas1_3_ind <= mas1_3_ind_q; +mas1_3_ts <= mas1_3_ts_q; +mas1_3_tsize <= mas1_3_tsize_q; +gen32_mas2_3_epn: if spr_data_width = 32 generate +mas2_3_epn(0 to 31) <=(others => '0'); +mas2_3_epn(32 to 51) <= mas2_3_epn_q(32 to 51); +end generate gen32_mas2_3_epn; +gen64_mas2_3_epn: if spr_data_width = 64 generate +mas2_3_epn <= mas2_3_epn_q; +end generate gen64_mas2_3_epn; +mas2_3_wimge <= mas2_3_wimge_q; +mas3_3_rpnl <= mas3_3_rpnl_q; +mas3_3_ubits <= mas3_3_ubits_q; +mas3_3_usxwr <= mas3_3_usxwr_q; +mas5_3_sgs <= mas5_3_sgs_q; +mas5_3_slpid <= mas5_3_slpid_q; +mas6_3_spid <= mas6_3_spid_q; +mas6_3_isize <= mas6_3_isize_q; +mas6_3_sind <= mas6_3_sind_q; +mas6_3_sas <= mas6_3_sas_q; +mas7_3_rpnu <= mas7_3_rpnu_q; +mas8_3_tgs <= mas8_3_tgs_q; +mas8_3_vf <= mas8_3_vf_q; +mas8_3_tlpid <= mas8_3_tlpid_q; +mmucsr0_tlb0fi <= mmucsr0_tlb0fi_q; +spr_dbg_slowspr_val_int <= spr_ctl_int_q(0); +spr_dbg_slowspr_rw_int <= spr_ctl_int_q(1); +spr_dbg_slowspr_etid_int <= spr_etid_int_q; +spr_dbg_slowspr_addr_int <= spr_addr_int_q; +spr_dbg_slowspr_val_out <= spr_ctl_out_q(0); +spr_dbg_slowspr_done_out <= spr_ctl_out_q(2); +spr_dbg_slowspr_data_out <= spr_data_out_q; +spr_dbg_match_64b <= spr_match_64b_q; +spr_dbg_match_any_mmu <= spr_match_any_mmu_q; +spr_dbg_match_any_mas <= spr_match_any_mas_q; +spr_dbg_match_pid <= spr_match_pid0_q or spr_match_pid1_q or spr_match_pid2_q or spr_match_pid3_q; +spr_dbg_match_mmucr0 <= spr_match_mmucr0_0_q or spr_match_mmucr0_1_q or spr_match_mmucr0_2_q or spr_match_mmucr0_3_q; +spr_dbg_match_mmucr1 <= spr_match_mmucr1_q; +spr_dbg_match_mmucr2 <= spr_match_mmucr2_q; +spr_dbg_match_mmucr3 <= spr_match_mmucr3_0_q or spr_match_mmucr3_1_q or spr_match_mmucr3_2_q or spr_match_mmucr3_3_q; +spr_dbg_match_lpidr <= spr_match_lpidr_q; +spr_dbg_match_mmucsr0 <= spr_match_mmucsr0_q; +spr_dbg_match_mmucfg <= spr_match_mmucfg_q; +spr_dbg_match_tlb0cfg <= spr_match_tlb0cfg_q; +spr_dbg_match_tlb0ps <= spr_match_tlb0ps_q; +spr_dbg_match_lratcfg <= spr_match_lratcfg; +spr_dbg_match_lratps <= spr_match_lratps_q; +spr_dbg_match_eptcfg <= spr_match_eptcfg_q; +spr_dbg_match_lper <= spr_match_lper_0_q or spr_match_lper_1_q or spr_match_lper_2_q or spr_match_lper_3_q; +spr_dbg_match_lperu <= spr_match_lperu_0_q or spr_match_lperu_1_q or spr_match_lperu_2_q or spr_match_lperu_3_q; +spr_dbg_match_mas0 <= spr_match_mas0_0_q or spr_match_mas0_1_q or spr_match_mas0_2_q or spr_match_mas0_3_q; +spr_dbg_match_mas1 <= spr_match_mas1_0_q or spr_match_mas1_1_q or spr_match_mas1_2_q or spr_match_mas1_3_q; +spr_dbg_match_mas2 <= spr_match_mas2_0_q or spr_match_mas2_1_q or spr_match_mas2_2_q or spr_match_mas2_3_q; +spr_dbg_match_mas2u <= spr_match_mas2u_0_q or spr_match_mas2u_1_q or spr_match_mas2u_2_q or spr_match_mas2u_3_q; +spr_dbg_match_mas3 <= spr_match_mas3_0_q or spr_match_mas3_1_q or spr_match_mas3_2_q or spr_match_mas3_3_q; +spr_dbg_match_mas4 <= spr_match_mas4_0_q or spr_match_mas4_1_q or spr_match_mas4_2_q or spr_match_mas4_3_q; +spr_dbg_match_mas5 <= spr_match_mas5_0_q or spr_match_mas5_1_q or spr_match_mas5_2_q or spr_match_mas5_3_q; +spr_dbg_match_mas6 <= spr_match_mas6_0_q or spr_match_mas6_1_q or spr_match_mas6_2_q or spr_match_mas6_3_q; +spr_dbg_match_mas7 <= spr_match_mas7_0_q or spr_match_mas7_1_q or spr_match_mas7_2_q or spr_match_mas7_3_q; +spr_dbg_match_mas8 <= spr_match_mas8_0_q or spr_match_mas8_1_q or spr_match_mas8_2_q or spr_match_mas8_3_q; +spr_dbg_match_mas01_64b <= spr_match_mas01_64b_0_q or spr_match_mas01_64b_1_q or spr_match_mas01_64b_2_q or spr_match_mas01_64b_3_q; +spr_dbg_match_mas56_64b <= spr_match_mas56_64b_0_q or spr_match_mas56_64b_1_q or spr_match_mas56_64b_2_q or spr_match_mas56_64b_3_q; +spr_dbg_match_mas73_64b <= spr_match_mas73_64b_0_q or spr_match_mas73_64b_1_q or spr_match_mas73_64b_2_q or spr_match_mas73_64b_3_q; +spr_dbg_match_mas81_64b <= spr_match_mas81_64b_0_q or spr_match_mas81_64b_1_q or spr_match_mas81_64b_2_q or spr_match_mas81_64b_3_q; +unused_dc(0) <= or_reduce(LCB_DELAY_LCLKR_DC(1 TO 4)); +unused_dc(1) <= or_reduce(LCB_MPW1_DC_B(1 TO 4)); +unused_dc(2) <= PC_FUNC_SL_FORCE; +unused_dc(3) <= PC_FUNC_SL_THOLD_0_B; +unused_dc(4) <= TC_SCAN_DIS_DC_B; +unused_dc(5) <= TC_SCAN_DIAG_DC; +unused_dc(6) <= TC_LBIST_EN_DC; +unused_dc(7) <= or_reduce(MMUCFG_Q_B); +unused_dc(8) <= or_reduce(TLB0CFG_Q_B); +unused_dc(9) <= or_reduce(TLB_MAS6_ISIZE); +unused_dc(10) <= TLB_MAS6_SIND; +unused_dc(11) <= or_reduce(LRAT_TAG4_HIT_ENTRY); +unused_dc(12) <= or_reduce(bcfg_spare_q); +unused_dc(13) <= or_reduce(bcfg_spare_q_b); +spr_ctl_in_latch: tri_rlmreg_p + generic map (width => spr_ctl_in_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spr_ctl_in_offset to spr_ctl_in_offset+spr_ctl_in_q'length-1), + scout => sov_0(spr_ctl_in_offset to spr_ctl_in_offset+spr_ctl_in_q'length-1), + din => spr_ctl_in_d(0 to spr_ctl_width-1), + dout => spr_ctl_in_q(0 to spr_ctl_width-1) ); +spr_etid_in_latch: tri_rlmreg_p + generic map (width => spr_etid_in_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spr_etid_in_offset to spr_etid_in_offset+spr_etid_in_q'length-1), + scout => sov_0(spr_etid_in_offset to spr_etid_in_offset+spr_etid_in_q'length-1), + din => spr_etid_in_d(0 to spr_etid_width-1), + dout => spr_etid_in_q(0 to spr_etid_width-1) ); +spr_addr_in_latch: tri_rlmreg_p + generic map (width => spr_addr_in_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spr_addr_in_offset to spr_addr_in_offset+spr_addr_in_q'length-1), + scout => sov_0(spr_addr_in_offset to spr_addr_in_offset+spr_addr_in_q'length-1), + din => spr_addr_in_d(0 to spr_addr_width-1), + dout => spr_addr_in_q(0 to spr_addr_width-1) ); +spr_addr_in_clone_latch: tri_rlmreg_p + generic map (width => spr_addr_in_clone_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_addr_in_clone_offset to spr_addr_in_clone_offset+spr_addr_in_clone_q'length-1), + scout => sov_1(spr_addr_in_clone_offset to spr_addr_in_clone_offset+spr_addr_in_clone_q'length-1), + din => spr_addr_in_clone_d(0 to spr_addr_width-1), + dout => spr_addr_in_clone_q(0 to spr_addr_width-1) ); +spr_data_in_latch: tri_rlmreg_p + generic map (width => spr_data_in_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spr_data_in_offset to spr_data_in_offset+spr_data_in_q'length-1), + scout => sov_0(spr_data_in_offset to spr_data_in_offset+spr_data_in_q'length-1), + din => spr_data_in_d(64-spr_data_width to 63), + dout => spr_data_in_q(64-spr_data_width to 63) ); +spr_ctl_int_latch: tri_rlmreg_p + generic map (width => spr_ctl_int_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_val_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spr_ctl_int_offset to spr_ctl_int_offset+spr_ctl_int_q'length-1), + scout => sov_0(spr_ctl_int_offset to spr_ctl_int_offset+spr_ctl_int_q'length-1), + din => spr_ctl_int_d(0 to spr_ctl_width-1), + dout => spr_ctl_int_q(0 to spr_ctl_width-1) ); +spr_etid_int_latch: tri_rlmreg_p + generic map (width => spr_etid_int_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_val_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spr_etid_int_offset to spr_etid_int_offset+spr_etid_int_q'length-1), + scout => sov_0(spr_etid_int_offset to spr_etid_int_offset+spr_etid_int_q'length-1), + din => spr_etid_int_d(0 to spr_etid_width-1), + dout => spr_etid_int_q(0 to spr_etid_width-1) ); +spr_addr_int_latch: tri_rlmreg_p + generic map (width => spr_addr_int_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_val_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spr_addr_int_offset to spr_addr_int_offset+spr_addr_int_q'length-1), + scout => sov_0(spr_addr_int_offset to spr_addr_int_offset+spr_addr_int_q'length-1), + din => spr_addr_int_d(0 to spr_addr_width-1), + dout => spr_addr_int_q(0 to spr_addr_width-1) ); +spr_data_int_latch: tri_rlmreg_p + generic map (width => spr_data_int_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_val_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spr_data_int_offset to spr_data_int_offset+spr_data_int_q'length-1), + scout => sov_0(spr_data_int_offset to spr_data_int_offset+spr_data_int_q'length-1), + din => spr_data_int_d(64-spr_data_width to 63), + dout => spr_data_int_q(64-spr_data_width to 63) ); +spr_ctl_out_latch: tri_rlmreg_p + generic map (width => spr_ctl_out_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_val_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spr_ctl_out_offset to spr_ctl_out_offset+spr_ctl_out_q'length-1), + scout => sov_0(spr_ctl_out_offset to spr_ctl_out_offset+spr_ctl_out_q'length-1), + din => spr_ctl_out_d(0 to spr_ctl_width-1), + dout => spr_ctl_out_q(0 to spr_ctl_width-1) ); +spr_etid_out_latch: tri_rlmreg_p + generic map (width => spr_etid_out_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_val_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spr_etid_out_offset to spr_etid_out_offset+spr_etid_out_q'length-1), + scout => sov_0(spr_etid_out_offset to spr_etid_out_offset+spr_etid_out_q'length-1), + din => spr_etid_out_d(0 to spr_etid_width-1), + dout => spr_etid_out_q(0 to spr_etid_width-1) ); +spr_addr_out_latch: tri_rlmreg_p + generic map (width => spr_addr_out_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_val_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spr_addr_out_offset to spr_addr_out_offset+spr_addr_out_q'length-1), + scout => sov_0(spr_addr_out_offset to spr_addr_out_offset+spr_addr_out_q'length-1), + din => spr_addr_out_d(0 to spr_addr_width-1), + dout => spr_addr_out_q(0 to spr_addr_width-1) ); +spr_data_out_latch: tri_rlmreg_p + generic map (width => spr_data_out_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_val_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spr_data_out_offset to spr_data_out_offset+spr_data_out_q'length-1), + scout => sov_0(spr_data_out_offset to spr_data_out_offset+spr_data_out_q'length-1), + din => spr_data_out_d(64-spr_data_width to 63), + dout => spr_data_out_q(64-spr_data_width to 63) ); +spr_match_any_mmu_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spr_match_any_mmu_offset), + scout => sov_0(spr_match_any_mmu_offset), + din => spr_match_any_mmu, + dout => spr_match_any_mmu_q); +spr_match_pid0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spr_match_pid0_offset), + scout => sov_0(spr_match_pid0_offset), + din => spr_match_pid0, + dout => spr_match_pid0_q); +spr_match_pid1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spr_match_pid1_offset), + scout => sov_0(spr_match_pid1_offset), + din => spr_match_pid1, + dout => spr_match_pid1_q); +spr_match_pid2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spr_match_pid2_offset), + scout => sov_0(spr_match_pid2_offset), + din => spr_match_pid2, + dout => spr_match_pid2_q); +spr_match_pid3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spr_match_pid3_offset), + scout => sov_0(spr_match_pid3_offset), + din => spr_match_pid3, + dout => spr_match_pid3_q); +spr_match_mmucr0_0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spr_match_mmucr0_0_offset), + scout => sov_0(spr_match_mmucr0_0_offset), + din => spr_match_mmucr0_0, + dout => spr_match_mmucr0_0_q); +spr_match_mmucr0_1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spr_match_mmucr0_1_offset), + scout => sov_0(spr_match_mmucr0_1_offset), + din => spr_match_mmucr0_1, + dout => spr_match_mmucr0_1_q); +spr_match_mmucr0_2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spr_match_mmucr0_2_offset), + scout => sov_0(spr_match_mmucr0_2_offset), + din => spr_match_mmucr0_2, + dout => spr_match_mmucr0_2_q); +spr_match_mmucr0_3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spr_match_mmucr0_3_offset), + scout => sov_0(spr_match_mmucr0_3_offset), + din => spr_match_mmucr0_3, + dout => spr_match_mmucr0_3_q); +spr_match_mmucr1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spr_match_mmucr1_offset), + scout => sov_0(spr_match_mmucr1_offset), + din => spr_match_mmucr1, + dout => spr_match_mmucr1_q); +spr_match_mmucr2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spr_match_mmucr2_offset), + scout => sov_0(spr_match_mmucr2_offset), + din => spr_match_mmucr2, + dout => spr_match_mmucr2_q); +spr_match_mmucr3_0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spr_match_mmucr3_0_offset), + scout => sov_0(spr_match_mmucr3_0_offset), + din => spr_match_mmucr3_0, + dout => spr_match_mmucr3_0_q); +spr_match_mmucr3_1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spr_match_mmucr3_1_offset), + scout => sov_0(spr_match_mmucr3_1_offset), + din => spr_match_mmucr3_1, + dout => spr_match_mmucr3_1_q); +spr_match_mmucr3_2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spr_match_mmucr3_2_offset), + scout => sov_0(spr_match_mmucr3_2_offset), + din => spr_match_mmucr3_2, + dout => spr_match_mmucr3_2_q); +spr_match_mmucr3_3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spr_match_mmucr3_3_offset), + scout => sov_0(spr_match_mmucr3_3_offset), + din => spr_match_mmucr3_3, + dout => spr_match_mmucr3_3_q); +spr_match_lpidr_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spr_match_lpidr_offset), + scout => sov_0(spr_match_lpidr_offset), + din => spr_match_lpidr, + dout => spr_match_lpidr_q); +spr_match_mmucsr0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mmucsr0_offset), + scout => sov_1(spr_match_mmucsr0_offset), + din => spr_match_mmucsr0, + dout => spr_match_mmucsr0_q); +spr_match_mmucfg_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mmucfg_offset), + scout => sov_1(spr_match_mmucfg_offset), + din => spr_match_mmucfg, + dout => spr_match_mmucfg_q); +spr_match_tlb0cfg_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_tlb0cfg_offset), + scout => sov_1(spr_match_tlb0cfg_offset), + din => spr_match_tlb0cfg, + dout => spr_match_tlb0cfg_q); +spr_match_tlb0ps_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_tlb0ps_offset), + scout => sov_1(spr_match_tlb0ps_offset), + din => spr_match_tlb0ps, + dout => spr_match_tlb0ps_q); +spr_match_lratcfg_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_lratcfg_offset), + scout => sov_1(spr_match_lratcfg_offset), + din => spr_match_lratcfg, + dout => spr_match_lratcfg_q); +spr_match_lratps_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_lratps_offset), + scout => sov_1(spr_match_lratps_offset), + din => spr_match_lratps, + dout => spr_match_lratps_q); +spr_match_eptcfg_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_eptcfg_offset), + scout => sov_1(spr_match_eptcfg_offset), + din => spr_match_eptcfg, + dout => spr_match_eptcfg_q); +spr_match_lper_0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_lper_0_offset), + scout => sov_1(spr_match_lper_0_offset), + din => spr_match_lper_0, + dout => spr_match_lper_0_q); +spr_match_lper_1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_lper_1_offset), + scout => sov_1(spr_match_lper_1_offset), + din => spr_match_lper_1, + dout => spr_match_lper_1_q); +spr_match_lper_2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_lper_2_offset), + scout => sov_1(spr_match_lper_2_offset), + din => spr_match_lper_2, + dout => spr_match_lper_2_q); +spr_match_lper_3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_lper_3_offset), + scout => sov_1(spr_match_lper_3_offset), + din => spr_match_lper_3, + dout => spr_match_lper_3_q); +spr_match_lperu_0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_lperu_0_offset), + scout => sov_1(spr_match_lperu_0_offset), + din => spr_match_lperu_0, + dout => spr_match_lperu_0_q); +spr_match_lperu_1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_lperu_1_offset), + scout => sov_1(spr_match_lperu_1_offset), + din => spr_match_lperu_1, + dout => spr_match_lperu_1_q); +spr_match_lperu_2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_lperu_2_offset), + scout => sov_1(spr_match_lperu_2_offset), + din => spr_match_lperu_2, + dout => spr_match_lperu_2_q); +spr_match_lperu_3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_lperu_3_offset), + scout => sov_1(spr_match_lperu_3_offset), + din => spr_match_lperu_3, + dout => spr_match_lperu_3_q); +spr_match_mas0_0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas0_0_offset), + scout => sov_1(spr_match_mas0_0_offset), + din => spr_match_mas0_0, + dout => spr_match_mas0_0_q); +spr_match_mas0_1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas0_1_offset), + scout => sov_1(spr_match_mas0_1_offset), + din => spr_match_mas0_1, + dout => spr_match_mas0_1_q); +spr_match_mas0_2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas0_2_offset), + scout => sov_1(spr_match_mas0_2_offset), + din => spr_match_mas0_2, + dout => spr_match_mas0_2_q); +spr_match_mas0_3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas0_3_offset), + scout => sov_1(spr_match_mas0_3_offset), + din => spr_match_mas0_3, + dout => spr_match_mas0_3_q); +spr_match_mas1_0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas1_0_offset), + scout => sov_1(spr_match_mas1_0_offset), + din => spr_match_mas1_0, + dout => spr_match_mas1_0_q); +spr_match_mas1_1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas1_1_offset), + scout => sov_1(spr_match_mas1_1_offset), + din => spr_match_mas1_1, + dout => spr_match_mas1_1_q); +spr_match_mas1_2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas1_2_offset), + scout => sov_1(spr_match_mas1_2_offset), + din => spr_match_mas1_2, + dout => spr_match_mas1_2_q); +spr_match_mas1_3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas1_3_offset), + scout => sov_1(spr_match_mas1_3_offset), + din => spr_match_mas1_3, + dout => spr_match_mas1_3_q); +spr_match_mas2_0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas2_0_offset), + scout => sov_1(spr_match_mas2_0_offset), + din => spr_match_mas2_0, + dout => spr_match_mas2_0_q); +spr_match_mas2_1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas2_1_offset), + scout => sov_1(spr_match_mas2_1_offset), + din => spr_match_mas2_1, + dout => spr_match_mas2_1_q); +spr_match_mas2_2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas2_2_offset), + scout => sov_1(spr_match_mas2_2_offset), + din => spr_match_mas2_2, + dout => spr_match_mas2_2_q); +spr_match_mas2_3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas2_3_offset), + scout => sov_1(spr_match_mas2_3_offset), + din => spr_match_mas2_3, + dout => spr_match_mas2_3_q); +spr_match_mas3_0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas3_0_offset), + scout => sov_1(spr_match_mas3_0_offset), + din => spr_match_mas3_0, + dout => spr_match_mas3_0_q); +spr_match_mas3_1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas3_1_offset), + scout => sov_1(spr_match_mas3_1_offset), + din => spr_match_mas3_1, + dout => spr_match_mas3_1_q); +spr_match_mas3_2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas3_2_offset), + scout => sov_1(spr_match_mas3_2_offset), + din => spr_match_mas3_2, + dout => spr_match_mas3_2_q); +spr_match_mas3_3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas3_3_offset), + scout => sov_1(spr_match_mas3_3_offset), + din => spr_match_mas3_3, + dout => spr_match_mas3_3_q); +spr_match_mas4_0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas4_0_offset), + scout => sov_1(spr_match_mas4_0_offset), + din => spr_match_mas4_0, + dout => spr_match_mas4_0_q); +spr_match_mas4_1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas4_1_offset), + scout => sov_1(spr_match_mas4_1_offset), + din => spr_match_mas4_1, + dout => spr_match_mas4_1_q); +spr_match_mas4_2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas4_2_offset), + scout => sov_1(spr_match_mas4_2_offset), + din => spr_match_mas4_2, + dout => spr_match_mas4_2_q); +spr_match_mas4_3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas4_3_offset), + scout => sov_1(spr_match_mas4_3_offset), + din => spr_match_mas4_3, + dout => spr_match_mas4_3_q); +spr_match_mas5_0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas5_0_offset), + scout => sov_1(spr_match_mas5_0_offset), + din => spr_match_mas5_0, + dout => spr_match_mas5_0_q); +spr_match_mas5_1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas5_1_offset), + scout => sov_1(spr_match_mas5_1_offset), + din => spr_match_mas5_1, + dout => spr_match_mas5_1_q); +spr_match_mas5_2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas5_2_offset), + scout => sov_1(spr_match_mas5_2_offset), + din => spr_match_mas5_2, + dout => spr_match_mas5_2_q); +spr_match_mas5_3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas5_3_offset), + scout => sov_1(spr_match_mas5_3_offset), + din => spr_match_mas5_3, + dout => spr_match_mas5_3_q); +spr_match_mas6_0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas6_0_offset), + scout => sov_1(spr_match_mas6_0_offset), + din => spr_match_mas6_0, + dout => spr_match_mas6_0_q); +spr_match_mas6_1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas6_1_offset), + scout => sov_1(spr_match_mas6_1_offset), + din => spr_match_mas6_1, + dout => spr_match_mas6_1_q); +spr_match_mas6_2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas6_2_offset), + scout => sov_1(spr_match_mas6_2_offset), + din => spr_match_mas6_2, + dout => spr_match_mas6_2_q); +spr_match_mas6_3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas6_3_offset), + scout => sov_1(spr_match_mas6_3_offset), + din => spr_match_mas6_3, + dout => spr_match_mas6_3_q); +spr_match_mas7_0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas7_0_offset), + scout => sov_1(spr_match_mas7_0_offset), + din => spr_match_mas7_0, + dout => spr_match_mas7_0_q); +spr_match_mas7_1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas7_1_offset), + scout => sov_1(spr_match_mas7_1_offset), + din => spr_match_mas7_1, + dout => spr_match_mas7_1_q); +spr_match_mas7_2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas7_2_offset), + scout => sov_1(spr_match_mas7_2_offset), + din => spr_match_mas7_2, + dout => spr_match_mas7_2_q); +spr_match_mas7_3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas7_3_offset), + scout => sov_1(spr_match_mas7_3_offset), + din => spr_match_mas7_3, + dout => spr_match_mas7_3_q); +spr_match_mas8_0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas8_0_offset), + scout => sov_1(spr_match_mas8_0_offset), + din => spr_match_mas8_0, + dout => spr_match_mas8_0_q); +spr_match_mas8_1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas8_1_offset), + scout => sov_1(spr_match_mas8_1_offset), + din => spr_match_mas8_1, + dout => spr_match_mas8_1_q); +spr_match_mas8_2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas8_2_offset), + scout => sov_1(spr_match_mas8_2_offset), + din => spr_match_mas8_2, + dout => spr_match_mas8_2_q); +spr_match_mas8_3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas8_3_offset), + scout => sov_1(spr_match_mas8_3_offset), + din => spr_match_mas8_3, + dout => spr_match_mas8_3_q); +spr_match_mas2u_0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas2u_0_offset), + scout => sov_1(spr_match_mas2u_0_offset), + din => spr_match_mas2u_0, + dout => spr_match_mas2u_0_q); +spr_match_mas2u_1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas2u_1_offset), + scout => sov_1(spr_match_mas2u_1_offset), + din => spr_match_mas2u_1, + dout => spr_match_mas2u_1_q); +spr_match_mas2u_2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas2u_2_offset), + scout => sov_1(spr_match_mas2u_2_offset), + din => spr_match_mas2u_2, + dout => spr_match_mas2u_2_q); +spr_match_mas2u_3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas2u_3_offset), + scout => sov_1(spr_match_mas2u_3_offset), + din => spr_match_mas2u_3, + dout => spr_match_mas2u_3_q); +spr_match_mas01_64b_0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas01_64b_0_offset), + scout => sov_1(spr_match_mas01_64b_0_offset), + din => spr_match_mas01_64b_0, + dout => spr_match_mas01_64b_0_q); +spr_match_mas01_64b_1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas01_64b_1_offset), + scout => sov_1(spr_match_mas01_64b_1_offset), + din => spr_match_mas01_64b_1, + dout => spr_match_mas01_64b_1_q); +spr_match_mas01_64b_2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas01_64b_2_offset), + scout => sov_1(spr_match_mas01_64b_2_offset), + din => spr_match_mas01_64b_2, + dout => spr_match_mas01_64b_2_q); +spr_match_mas01_64b_3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas01_64b_3_offset), + scout => sov_1(spr_match_mas01_64b_3_offset), + din => spr_match_mas01_64b_3, + dout => spr_match_mas01_64b_3_q); +spr_match_mas56_64b_0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas56_64b_0_offset), + scout => sov_1(spr_match_mas56_64b_0_offset), + din => spr_match_mas56_64b_0, + dout => spr_match_mas56_64b_0_q); +spr_match_mas56_64b_1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas56_64b_1_offset), + scout => sov_1(spr_match_mas56_64b_1_offset), + din => spr_match_mas56_64b_1, + dout => spr_match_mas56_64b_1_q); +spr_match_mas56_64b_2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas56_64b_2_offset), + scout => sov_1(spr_match_mas56_64b_2_offset), + din => spr_match_mas56_64b_2, + dout => spr_match_mas56_64b_2_q); +spr_match_mas56_64b_3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas56_64b_3_offset), + scout => sov_1(spr_match_mas56_64b_3_offset), + din => spr_match_mas56_64b_3, + dout => spr_match_mas56_64b_3_q); +spr_match_mas73_64b_0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas73_64b_0_offset), + scout => sov_1(spr_match_mas73_64b_0_offset), + din => spr_match_mas73_64b_0, + dout => spr_match_mas73_64b_0_q); +spr_match_mas73_64b_1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas73_64b_1_offset), + scout => sov_1(spr_match_mas73_64b_1_offset), + din => spr_match_mas73_64b_1, + dout => spr_match_mas73_64b_1_q); +spr_match_mas73_64b_2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas73_64b_2_offset), + scout => sov_1(spr_match_mas73_64b_2_offset), + din => spr_match_mas73_64b_2, + dout => spr_match_mas73_64b_2_q); +spr_match_mas73_64b_3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas73_64b_3_offset), + scout => sov_1(spr_match_mas73_64b_3_offset), + din => spr_match_mas73_64b_3, + dout => spr_match_mas73_64b_3_q); +spr_match_mas81_64b_0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas81_64b_0_offset), + scout => sov_1(spr_match_mas81_64b_0_offset), + din => spr_match_mas81_64b_0, + dout => spr_match_mas81_64b_0_q); +spr_match_mas81_64b_1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas81_64b_1_offset), + scout => sov_1(spr_match_mas81_64b_1_offset), + din => spr_match_mas81_64b_1, + dout => spr_match_mas81_64b_1_q); +spr_match_mas81_64b_2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas81_64b_2_offset), + scout => sov_1(spr_match_mas81_64b_2_offset), + din => spr_match_mas81_64b_2, + dout => spr_match_mas81_64b_2_q); +spr_match_mas81_64b_3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas81_64b_3_offset), + scout => sov_1(spr_match_mas81_64b_3_offset), + din => spr_match_mas81_64b_3, + dout => spr_match_mas81_64b_3_q); +spr_match_64b_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_64b_offset), + scout => sov_1(spr_match_64b_offset), + din => spr_match_64b, + dout => spr_match_64b_q); +spr_mas_data_out_latch: tri_rlmreg_p + generic map (width => spr_mas_data_out_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_mas_data_out_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_mas_data_out_offset to spr_mas_data_out_offset+spr_mas_data_out_q'length-1), + scout => sov_1(spr_mas_data_out_offset to spr_mas_data_out_offset+spr_mas_data_out_q'length-1), + din => spr_mas_data_out(64-spr_data_width to 63), + dout => spr_mas_data_out_q(64-spr_data_width to 63) ); +spr_match_any_mas_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_any_mas_offset), + scout => sov_1(spr_match_any_mas_offset), + din => spr_match_any_mas, + dout => spr_match_any_mas_q); +pid0_latch: tri_rlmreg_p + generic map (width => pid0_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_mmu_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(pid0_offset to pid0_offset+pid0_q'length-1), + scout => sov_0(pid0_offset to pid0_offset+pid0_q'length-1), + din => pid0_d(0 to pid_width-1), + dout => pid0_q(0 to pid_width-1) ); +pid1_latch: tri_rlmreg_p + generic map (width => pid1_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_mmu_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(pid1_offset to pid1_offset+pid1_q'length-1), + scout => sov_0(pid1_offset to pid1_offset+pid1_q'length-1), + din => pid1_d(0 to pid_width-1), + dout => pid1_q(0 to pid_width-1) ); +pid2_latch: tri_rlmreg_p + generic map (width => pid2_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_mmu_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(pid2_offset to pid2_offset+pid2_q'length-1), + scout => sov_0(pid2_offset to pid2_offset+pid2_q'length-1), + din => pid2_d(0 to pid_width-1), + dout => pid2_q(0 to pid_width-1) ); +pid3_latch: tri_rlmreg_p + generic map (width => pid3_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_mmu_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(pid3_offset to pid3_offset+pid3_q'length-1), + scout => sov_0(pid3_offset to pid3_offset+pid3_q'length-1), + din => pid3_d(0 to pid_width-1), + dout => pid3_q(0 to pid_width-1) ); +mmucr0_0_latch: tri_rlmreg_p + generic map (width => mmucr0_0_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(mmucr0_0_offset to mmucr0_0_offset+mmucr0_0_q'length-1), + scout => sov_0(mmucr0_0_offset to mmucr0_0_offset+mmucr0_0_q'length-1), + din => mmucr0_0_d(0 to mmucr0_width-1), + dout => mmucr0_0_q(0 to mmucr0_width-1) ); +mmucr0_1_latch: tri_rlmreg_p + generic map (width => mmucr0_1_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(mmucr0_1_offset to mmucr0_1_offset+mmucr0_1_q'length-1), + scout => sov_0(mmucr0_1_offset to mmucr0_1_offset+mmucr0_1_q'length-1), + din => mmucr0_1_d(0 to mmucr0_width-1), + dout => mmucr0_1_q(0 to mmucr0_width-1) ); +mmucr0_2_latch: tri_rlmreg_p + generic map (width => mmucr0_2_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(mmucr0_2_offset to mmucr0_2_offset+mmucr0_2_q'length-1), + scout => sov_0(mmucr0_2_offset to mmucr0_2_offset+mmucr0_2_q'length-1), + din => mmucr0_2_d(0 to mmucr0_width-1), + dout => mmucr0_2_q(0 to mmucr0_width-1) ); +mmucr0_3_latch: tri_rlmreg_p + generic map (width => mmucr0_3_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(mmucr0_3_offset to mmucr0_3_offset+mmucr0_3_q'length-1), + scout => sov_0(mmucr0_3_offset to mmucr0_3_offset+mmucr0_3_q'length-1), + din => mmucr0_3_d(0 to mmucr0_width-1), + dout => mmucr0_3_q(0 to mmucr0_width-1) ); +mmucr1_latch: tri_rlmreg_p + generic map (width => mmucr1_q'length, init => bcfg_mmucr1_value, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(mmucr1_offset to mmucr1_offset+mmucr1_q'length-1), + scout => bsov(mmucr1_offset to mmucr1_offset+mmucr1_q'length-1), + din => mmucr1_d(0 to mmucr1_width-1), + dout => mmucr1_q(0 to mmucr1_width-1) ); +mmucr2_latch: tri_rlmreg_p + generic map (width => mmucr2_q'length, init => bcfg_mmucr2_value, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(mmucr2_offset to mmucr2_offset+mmucr2_q'length-1), + scout => bsov(mmucr2_offset to mmucr2_offset+mmucr2_q'length-1), + din => mmucr2_d(0 to mmucr2_width-1), + dout => mmucr2_q(0 to mmucr2_width-1) ); +mmucr3_0_latch: tri_rlmreg_p + generic map (width => mmucr3_0_q'length, init => bcfg_mmucr3_value, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(mmucr3_0_offset to mmucr3_0_offset+mmucr3_0_q'length-1), + scout => bsov(mmucr3_0_offset to mmucr3_0_offset+mmucr3_0_q'length-1), + din => mmucr3_0_d(64-mmucr3_width to 63), + dout => mmucr3_0_q(64-mmucr3_width to 63) ); +mmucr3_1_latch: tri_rlmreg_p + generic map (width => mmucr3_1_q'length, init => bcfg_mmucr3_value, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(mmucr3_1_offset to mmucr3_1_offset+mmucr3_1_q'length-1), + scout => bsov(mmucr3_1_offset to mmucr3_1_offset+mmucr3_1_q'length-1), + din => mmucr3_1_d(64-mmucr3_width to 63), + dout => mmucr3_1_q(64-mmucr3_width to 63) ); +mmucr3_2_latch: tri_rlmreg_p + generic map (width => mmucr3_2_q'length, init => bcfg_mmucr3_value, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(mmucr3_2_offset to mmucr3_2_offset+mmucr3_2_q'length-1), + scout => bsov(mmucr3_2_offset to mmucr3_2_offset+mmucr3_2_q'length-1), + din => mmucr3_2_d(64-mmucr3_width to 63), + dout => mmucr3_2_q(64-mmucr3_width to 63) ); +mmucr3_3_latch: tri_rlmreg_p + generic map (width => mmucr3_3_q'length, init => bcfg_mmucr3_value, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(mmucr3_3_offset to mmucr3_3_offset+mmucr3_3_q'length-1), + scout => bsov(mmucr3_3_offset to mmucr3_3_offset+mmucr3_3_q'length-1), + din => mmucr3_3_d(64-mmucr3_width to 63), + dout => mmucr3_3_q(64-mmucr3_width to 63) ); +lpidr_latch: tri_rlmreg_p + generic map (width => lpidr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_mmu_act_q(thdid_width), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(lpidr_offset to lpidr_offset+lpidr_q'length-1), + scout => sov_0(lpidr_offset to lpidr_offset+lpidr_q'length-1), + din => lpidr_d(0 to lpid_width-1), + dout => lpidr_q(0 to lpid_width-1) ); +mas0_0_atsel_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas0_0_atsel_offset), + scout => sov_1(mas0_0_atsel_offset), + din => mas0_0_atsel_d, + dout => mas0_0_atsel_q); +mas0_0_esel_latch: tri_rlmreg_p + generic map (width => mas0_0_esel_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas0_0_esel_offset to mas0_0_esel_offset+mas0_0_esel_q'length-1), + scout => sov_1(mas0_0_esel_offset to mas0_0_esel_offset+mas0_0_esel_q'length-1), + din => mas0_0_esel_d(0 to mas0_0_esel_d'length-1), + dout => mas0_0_esel_q(0 to mas0_0_esel_q'length-1) ); +mas0_0_hes_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas0_0_hes_offset), + scout => sov_1(mas0_0_hes_offset), + din => mas0_0_hes_d, + dout => mas0_0_hes_q); +mas0_0_wq_latch: tri_rlmreg_p + generic map (width => mas0_0_wq_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas0_0_wq_offset to mas0_0_wq_offset+mas0_0_wq_q'length-1), + scout => sov_1(mas0_0_wq_offset to mas0_0_wq_offset+mas0_0_wq_q'length-1), + din => mas0_0_wq_d(0 to mas0_0_wq_d'length-1), + dout => mas0_0_wq_q(0 to mas0_0_wq_q'length-1) ); +mas1_0_v_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas1_0_v_offset), + scout => sov_1(mas1_0_v_offset), + din => mas1_0_v_d, + dout => mas1_0_v_q); +mas1_0_iprot_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas1_0_iprot_offset), + scout => sov_1(mas1_0_iprot_offset), + din => mas1_0_iprot_d, + dout => mas1_0_iprot_q); +mas1_0_tid_latch: tri_rlmreg_p + generic map (width => mas1_0_tid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas1_0_tid_offset to mas1_0_tid_offset+mas1_0_tid_q'length-1), + scout => sov_1(mas1_0_tid_offset to mas1_0_tid_offset+mas1_0_tid_q'length-1), + din => mas1_0_tid_d(0 to mas1_0_tid_d'length-1), + dout => mas1_0_tid_q(0 to mas1_0_tid_q'length-1) ); +mas1_0_ind_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas1_0_ind_offset), + scout => sov_1(mas1_0_ind_offset), + din => mas1_0_ind_d, + dout => mas1_0_ind_q); +mas1_0_ts_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas1_0_ts_offset), + scout => sov_1(mas1_0_ts_offset), + din => mas1_0_ts_d, + dout => mas1_0_ts_q); +mas1_0_tsize_latch: tri_rlmreg_p + generic map (width => mas1_0_tsize_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas1_0_tsize_offset to mas1_0_tsize_offset+mas1_0_tsize_q'length-1), + scout => sov_1(mas1_0_tsize_offset to mas1_0_tsize_offset+mas1_0_tsize_q'length-1), + din => mas1_0_tsize_d(0 to mas1_0_tsize_d'length-1), + dout => mas1_0_tsize_q(0 to mas1_0_tsize_q'length-1) ); +mas2_0_epn_latch: tri_rlmreg_p + generic map (width => mas2_0_epn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas2_0_epn_offset to mas2_0_epn_offset+mas2_0_epn_q'length-1), + scout => sov_1(mas2_0_epn_offset to mas2_0_epn_offset+mas2_0_epn_q'length-1), + din => mas2_0_epn_d(52-mas2_0_epn_d'length to 51), + dout => mas2_0_epn_q(52-mas2_0_epn_q'length to 51) ); +mas2_0_wimge_latch: tri_rlmreg_p + generic map (width => mas2_0_wimge_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas2_0_wimge_offset to mas2_0_wimge_offset+mas2_0_wimge_q'length-1), + scout => sov_1(mas2_0_wimge_offset to mas2_0_wimge_offset+mas2_0_wimge_q'length-1), + din => mas2_0_wimge_d(0 to mas2_0_wimge_d'length-1), + dout => mas2_0_wimge_q(0 to mas2_0_wimge_q'length-1) ); +mas3_0_rpnl_latch: tri_rlmreg_p + generic map (width => mas3_0_rpnl_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas3_0_rpnl_offset to mas3_0_rpnl_offset+mas3_0_rpnl_q'length-1), + scout => sov_1(mas3_0_rpnl_offset to mas3_0_rpnl_offset+mas3_0_rpnl_q'length-1), + din => mas3_0_rpnl_d(32 to 32+mas3_0_rpnl_d'length-1), + dout => mas3_0_rpnl_q(32 to 32+mas3_0_rpnl_q'length-1) ); +mas3_0_ubits_latch: tri_rlmreg_p + generic map (width => mas3_0_ubits_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas3_0_ubits_offset to mas3_0_ubits_offset+mas3_0_ubits_q'length-1), + scout => sov_1(mas3_0_ubits_offset to mas3_0_ubits_offset+mas3_0_ubits_q'length-1), + din => mas3_0_ubits_d(0 to mas3_0_ubits_d'length-1), + dout => mas3_0_ubits_q(0 to mas3_0_ubits_q'length-1) ); +mas3_0_usxwr_latch: tri_rlmreg_p + generic map (width => mas3_0_usxwr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas3_0_usxwr_offset to mas3_0_usxwr_offset+mas3_0_usxwr_q'length-1), + scout => sov_1(mas3_0_usxwr_offset to mas3_0_usxwr_offset+mas3_0_usxwr_q'length-1), + din => mas3_0_usxwr_d(0 to mas3_0_usxwr_d'length-1), + dout => mas3_0_usxwr_q(0 to mas3_0_usxwr_q'length-1) ); +mas4_0_indd_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(mas4_0_indd_offset), + scout => bsov(mas4_0_indd_offset), + din => mas4_0_indd_d, + dout => mas4_0_indd_q); +mas4_0_tsized_latch: tri_rlmreg_p + generic map (width => mas4_0_tsized_q'length, init => 1, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(mas4_0_tsized_offset to mas4_0_tsized_offset+mas4_0_tsized_q'length-1), + scout => bsov(mas4_0_tsized_offset to mas4_0_tsized_offset+mas4_0_tsized_q'length-1), + din => mas4_0_tsized_d(0 to mas4_0_tsized_d'length-1), + dout => mas4_0_tsized_q(0 to mas4_0_tsized_q'length-1) ); +mas4_0_wimged_latch: tri_rlmreg_p + generic map (width => mas4_0_wimged_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(mas4_0_wimged_offset to mas4_0_wimged_offset+mas4_0_wimged_q'length-1), + scout => bsov(mas4_0_wimged_offset to mas4_0_wimged_offset+mas4_0_wimged_q'length-1), + din => mas4_0_wimged_d(0 to mas4_0_wimged_d'length-1), + dout => mas4_0_wimged_q(0 to mas4_0_wimged_q'length-1) ); +mas5_0_sgs_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas5_0_sgs_offset), + scout => sov_1(mas5_0_sgs_offset), + din => mas5_0_sgs_d, + dout => mas5_0_sgs_q); +mas5_0_slpid_latch: tri_rlmreg_p + generic map (width => mas5_0_slpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas5_0_slpid_offset to mas5_0_slpid_offset+mas5_0_slpid_q'length-1), + scout => sov_1(mas5_0_slpid_offset to mas5_0_slpid_offset+mas5_0_slpid_q'length-1), + din => mas5_0_slpid_d(0 to mas5_0_slpid_d'length-1), + dout => mas5_0_slpid_q(0 to mas5_0_slpid_q'length-1) ); +mas6_0_spid_latch: tri_rlmreg_p + generic map (width => mas6_0_spid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas6_0_spid_offset to mas6_0_spid_offset+mas6_0_spid_q'length-1), + scout => sov_1(mas6_0_spid_offset to mas6_0_spid_offset+mas6_0_spid_q'length-1), + din => mas6_0_spid_d(0 to mas6_0_spid_d'length-1), + dout => mas6_0_spid_q(0 to mas6_0_spid_q'length-1) ); +mas6_0_isize_latch: tri_rlmreg_p + generic map (width => mas6_0_isize_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas6_0_isize_offset to mas6_0_isize_offset+mas6_0_isize_q'length-1), + scout => sov_1(mas6_0_isize_offset to mas6_0_isize_offset+mas6_0_isize_q'length-1), + din => mas6_0_isize_d(0 to mas6_0_isize_d'length-1), + dout => mas6_0_isize_q(0 to mas6_0_isize_q'length-1) ); +mas6_0_sind_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas6_0_sind_offset), + scout => sov_1(mas6_0_sind_offset), + din => mas6_0_sind_d, + dout => mas6_0_sind_q); +mas6_0_sas_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas6_0_sas_offset), + scout => sov_1(mas6_0_sas_offset), + din => mas6_0_sas_d, + dout => mas6_0_sas_q); +mas7_0_rpnu_latch: tri_rlmreg_p + generic map (width => mas7_0_rpnu_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas7_0_rpnu_offset to mas7_0_rpnu_offset+mas7_0_rpnu_q'length-1), + scout => sov_1(mas7_0_rpnu_offset to mas7_0_rpnu_offset+mas7_0_rpnu_q'length-1), + din => mas7_0_rpnu_d(22 to 22+mas7_0_rpnu_d'length-1), + dout => mas7_0_rpnu_q(22 to 22+mas7_0_rpnu_q'length-1) ); +mas8_0_tgs_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas8_0_tgs_offset), + scout => sov_1(mas8_0_tgs_offset), + din => mas8_0_tgs_d, + dout => mas8_0_tgs_q); +mas8_0_vf_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas8_0_vf_offset), + scout => sov_1(mas8_0_vf_offset), + din => mas8_0_vf_d, + dout => mas8_0_vf_q); +mas8_0_tlpid_latch: tri_rlmreg_p + generic map (width => mas8_0_tlpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas8_0_tlpid_offset to mas8_0_tlpid_offset+mas8_0_tlpid_q'length-1), + scout => sov_1(mas8_0_tlpid_offset to mas8_0_tlpid_offset+mas8_0_tlpid_q'length-1), + din => mas8_0_tlpid_d(0 to mas8_0_tlpid_d'length-1), + dout => mas8_0_tlpid_q(0 to mas8_0_tlpid_q'length-1) ); +mas0_1_atsel_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas0_1_atsel_offset), + scout => sov_1(mas0_1_atsel_offset), + din => mas0_1_atsel_d, + dout => mas0_1_atsel_q); +mas0_1_esel_latch: tri_rlmreg_p + generic map (width => mas0_1_esel_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas0_1_esel_offset to mas0_1_esel_offset+mas0_1_esel_q'length-1), + scout => sov_1(mas0_1_esel_offset to mas0_1_esel_offset+mas0_1_esel_q'length-1), + din => mas0_1_esel_d(0 to mas0_1_esel_d'length-1), + dout => mas0_1_esel_q(0 to mas0_1_esel_q'length-1) ); +mas0_1_hes_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas0_1_hes_offset), + scout => sov_1(mas0_1_hes_offset), + din => mas0_1_hes_d, + dout => mas0_1_hes_q); +mas0_1_wq_latch: tri_rlmreg_p + generic map (width => mas0_1_wq_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas0_1_wq_offset to mas0_1_wq_offset+mas0_1_wq_q'length-1), + scout => sov_1(mas0_1_wq_offset to mas0_1_wq_offset+mas0_1_wq_q'length-1), + din => mas0_1_wq_d(0 to mas0_1_wq_d'length-1), + dout => mas0_1_wq_q(0 to mas0_1_wq_q'length-1) ); +mas1_1_v_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas1_1_v_offset), + scout => sov_1(mas1_1_v_offset), + din => mas1_1_v_d, + dout => mas1_1_v_q); +mas1_1_iprot_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas1_1_iprot_offset), + scout => sov_1(mas1_1_iprot_offset), + din => mas1_1_iprot_d, + dout => mas1_1_iprot_q); +mas1_1_tid_latch: tri_rlmreg_p + generic map (width => mas1_1_tid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas1_1_tid_offset to mas1_1_tid_offset+mas1_1_tid_q'length-1), + scout => sov_1(mas1_1_tid_offset to mas1_1_tid_offset+mas1_1_tid_q'length-1), + din => mas1_1_tid_d(0 to mas1_1_tid_d'length-1), + dout => mas1_1_tid_q(0 to mas1_1_tid_q'length-1) ); +mas1_1_ind_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas1_1_ind_offset), + scout => sov_1(mas1_1_ind_offset), + din => mas1_1_ind_d, + dout => mas1_1_ind_q); +mas1_1_ts_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas1_1_ts_offset), + scout => sov_1(mas1_1_ts_offset), + din => mas1_1_ts_d, + dout => mas1_1_ts_q); +mas1_1_tsize_latch: tri_rlmreg_p + generic map (width => mas1_1_tsize_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas1_1_tsize_offset to mas1_1_tsize_offset+mas1_1_tsize_q'length-1), + scout => sov_1(mas1_1_tsize_offset to mas1_1_tsize_offset+mas1_1_tsize_q'length-1), + din => mas1_1_tsize_d(0 to mas1_1_tsize_d'length-1), + dout => mas1_1_tsize_q(0 to mas1_1_tsize_q'length-1) ); +mas2_1_epn_latch: tri_rlmreg_p + generic map (width => mas2_1_epn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas2_1_epn_offset to mas2_1_epn_offset+mas2_1_epn_q'length-1), + scout => sov_1(mas2_1_epn_offset to mas2_1_epn_offset+mas2_1_epn_q'length-1), + din => mas2_1_epn_d(52-mas2_1_epn_d'length to 51), + dout => mas2_1_epn_q(52-mas2_1_epn_q'length to 51) ); +mas2_1_wimge_latch: tri_rlmreg_p + generic map (width => mas2_1_wimge_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas2_1_wimge_offset to mas2_1_wimge_offset+mas2_1_wimge_q'length-1), + scout => sov_1(mas2_1_wimge_offset to mas2_1_wimge_offset+mas2_1_wimge_q'length-1), + din => mas2_1_wimge_d(0 to mas2_1_wimge_d'length-1), + dout => mas2_1_wimge_q(0 to mas2_1_wimge_q'length-1) ); +mas3_1_rpnl_latch: tri_rlmreg_p + generic map (width => mas3_1_rpnl_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas3_1_rpnl_offset to mas3_1_rpnl_offset+mas3_1_rpnl_q'length-1), + scout => sov_1(mas3_1_rpnl_offset to mas3_1_rpnl_offset+mas3_1_rpnl_q'length-1), + din => mas3_1_rpnl_d(32 to 32+mas3_1_rpnl_d'length-1), + dout => mas3_1_rpnl_q(32 to 32+mas3_1_rpnl_q'length-1) ); +mas3_1_ubits_latch: tri_rlmreg_p + generic map (width => mas3_1_ubits_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas3_1_ubits_offset to mas3_1_ubits_offset+mas3_1_ubits_q'length-1), + scout => sov_1(mas3_1_ubits_offset to mas3_1_ubits_offset+mas3_1_ubits_q'length-1), + din => mas3_1_ubits_d(0 to mas3_1_ubits_d'length-1), + dout => mas3_1_ubits_q(0 to mas3_1_ubits_q'length-1) ); +mas3_1_usxwr_latch: tri_rlmreg_p + generic map (width => mas3_1_usxwr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas3_1_usxwr_offset to mas3_1_usxwr_offset+mas3_1_usxwr_q'length-1), + scout => sov_1(mas3_1_usxwr_offset to mas3_1_usxwr_offset+mas3_1_usxwr_q'length-1), + din => mas3_1_usxwr_d(0 to mas3_1_usxwr_d'length-1), + dout => mas3_1_usxwr_q(0 to mas3_1_usxwr_q'length-1) ); +mas4_1_indd_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(mas4_1_indd_offset), + scout => bsov(mas4_1_indd_offset), + din => mas4_1_indd_d, + dout => mas4_1_indd_q); +mas4_1_tsized_latch: tri_rlmreg_p + generic map (width => mas4_1_tsized_q'length, init => 1, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(mas4_1_tsized_offset to mas4_1_tsized_offset+mas4_1_tsized_q'length-1), + scout => bsov(mas4_1_tsized_offset to mas4_1_tsized_offset+mas4_1_tsized_q'length-1), + din => mas4_1_tsized_d(0 to mas4_1_tsized_d'length-1), + dout => mas4_1_tsized_q(0 to mas4_1_tsized_q'length-1) ); +mas4_1_wimged_latch: tri_rlmreg_p + generic map (width => mas4_1_wimged_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(mas4_1_wimged_offset to mas4_1_wimged_offset+mas4_1_wimged_q'length-1), + scout => bsov(mas4_1_wimged_offset to mas4_1_wimged_offset+mas4_1_wimged_q'length-1), + din => mas4_1_wimged_d(0 to mas4_1_wimged_d'length-1), + dout => mas4_1_wimged_q(0 to mas4_1_wimged_q'length-1) ); +mas5_1_sgs_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas5_1_sgs_offset), + scout => sov_1(mas5_1_sgs_offset), + din => mas5_1_sgs_d, + dout => mas5_1_sgs_q); +mas5_1_slpid_latch: tri_rlmreg_p + generic map (width => mas5_1_slpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas5_1_slpid_offset to mas5_1_slpid_offset+mas5_1_slpid_q'length-1), + scout => sov_1(mas5_1_slpid_offset to mas5_1_slpid_offset+mas5_1_slpid_q'length-1), + din => mas5_1_slpid_d(0 to mas5_1_slpid_d'length-1), + dout => mas5_1_slpid_q(0 to mas5_1_slpid_q'length-1) ); +mas6_1_spid_latch: tri_rlmreg_p + generic map (width => mas6_1_spid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas6_1_spid_offset to mas6_1_spid_offset+mas6_1_spid_q'length-1), + scout => sov_1(mas6_1_spid_offset to mas6_1_spid_offset+mas6_1_spid_q'length-1), + din => mas6_1_spid_d(0 to mas6_1_spid_d'length-1), + dout => mas6_1_spid_q(0 to mas6_1_spid_q'length-1) ); +mas6_1_isize_latch: tri_rlmreg_p + generic map (width => mas6_1_isize_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas6_1_isize_offset to mas6_1_isize_offset+mas6_1_isize_q'length-1), + scout => sov_1(mas6_1_isize_offset to mas6_1_isize_offset+mas6_1_isize_q'length-1), + din => mas6_1_isize_d(0 to mas6_1_isize_d'length-1), + dout => mas6_1_isize_q(0 to mas6_1_isize_q'length-1) ); +mas6_1_sind_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas6_1_sind_offset), + scout => sov_1(mas6_1_sind_offset), + din => mas6_1_sind_d, + dout => mas6_1_sind_q); +mas6_1_sas_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas6_1_sas_offset), + scout => sov_1(mas6_1_sas_offset), + din => mas6_1_sas_d, + dout => mas6_1_sas_q); +mas7_1_rpnu_latch: tri_rlmreg_p + generic map (width => mas7_1_rpnu_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas7_1_rpnu_offset to mas7_1_rpnu_offset+mas7_1_rpnu_q'length-1), + scout => sov_1(mas7_1_rpnu_offset to mas7_1_rpnu_offset+mas7_1_rpnu_q'length-1), + din => mas7_1_rpnu_d(22 to 22+mas7_1_rpnu_d'length-1), + dout => mas7_1_rpnu_q(22 to 22+mas7_1_rpnu_q'length-1) ); +mas8_1_tgs_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas8_1_tgs_offset), + scout => sov_1(mas8_1_tgs_offset), + din => mas8_1_tgs_d, + dout => mas8_1_tgs_q); +mas8_1_vf_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas8_1_vf_offset), + scout => sov_1(mas8_1_vf_offset), + din => mas8_1_vf_d, + dout => mas8_1_vf_q); +mas8_1_tlpid_latch: tri_rlmreg_p + generic map (width => mas8_1_tlpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas8_1_tlpid_offset to mas8_1_tlpid_offset+mas8_1_tlpid_q'length-1), + scout => sov_1(mas8_1_tlpid_offset to mas8_1_tlpid_offset+mas8_1_tlpid_q'length-1), + din => mas8_1_tlpid_d(0 to mas8_1_tlpid_d'length-1), + dout => mas8_1_tlpid_q(0 to mas8_1_tlpid_q'length-1) ); +mas0_2_atsel_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas0_2_atsel_offset), + scout => sov_1(mas0_2_atsel_offset), + din => mas0_2_atsel_d, + dout => mas0_2_atsel_q); +mas0_2_esel_latch: tri_rlmreg_p + generic map (width => mas0_2_esel_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas0_2_esel_offset to mas0_2_esel_offset+mas0_2_esel_q'length-1), + scout => sov_1(mas0_2_esel_offset to mas0_2_esel_offset+mas0_2_esel_q'length-1), + din => mas0_2_esel_d(0 to mas0_2_esel_d'length-1), + dout => mas0_2_esel_q(0 to mas0_2_esel_q'length-1) ); +mas0_2_hes_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas0_2_hes_offset), + scout => sov_1(mas0_2_hes_offset), + din => mas0_2_hes_d, + dout => mas0_2_hes_q); +mas0_2_wq_latch: tri_rlmreg_p + generic map (width => mas0_2_wq_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas0_2_wq_offset to mas0_2_wq_offset+mas0_2_wq_q'length-1), + scout => sov_1(mas0_2_wq_offset to mas0_2_wq_offset+mas0_2_wq_q'length-1), + din => mas0_2_wq_d(0 to mas0_2_wq_d'length-1), + dout => mas0_2_wq_q(0 to mas0_2_wq_q'length-1) ); +mas1_2_v_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas1_2_v_offset), + scout => sov_1(mas1_2_v_offset), + din => mas1_2_v_d, + dout => mas1_2_v_q); +mas1_2_iprot_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas1_2_iprot_offset), + scout => sov_1(mas1_2_iprot_offset), + din => mas1_2_iprot_d, + dout => mas1_2_iprot_q); +mas1_2_tid_latch: tri_rlmreg_p + generic map (width => mas1_2_tid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas1_2_tid_offset to mas1_2_tid_offset+mas1_2_tid_q'length-1), + scout => sov_1(mas1_2_tid_offset to mas1_2_tid_offset+mas1_2_tid_q'length-1), + din => mas1_2_tid_d(0 to mas1_2_tid_d'length-1), + dout => mas1_2_tid_q(0 to mas1_2_tid_q'length-1) ); +mas1_2_ind_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas1_2_ind_offset), + scout => sov_1(mas1_2_ind_offset), + din => mas1_2_ind_d, + dout => mas1_2_ind_q); +mas1_2_ts_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas1_2_ts_offset), + scout => sov_1(mas1_2_ts_offset), + din => mas1_2_ts_d, + dout => mas1_2_ts_q); +mas1_2_tsize_latch: tri_rlmreg_p + generic map (width => mas1_2_tsize_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas1_2_tsize_offset to mas1_2_tsize_offset+mas1_2_tsize_q'length-1), + scout => sov_1(mas1_2_tsize_offset to mas1_2_tsize_offset+mas1_2_tsize_q'length-1), + din => mas1_2_tsize_d(0 to mas1_2_tsize_d'length-1), + dout => mas1_2_tsize_q(0 to mas1_2_tsize_q'length-1) ); +mas2_2_epn_latch: tri_rlmreg_p + generic map (width => mas2_2_epn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas2_2_epn_offset to mas2_2_epn_offset+mas2_2_epn_q'length-1), + scout => sov_1(mas2_2_epn_offset to mas2_2_epn_offset+mas2_2_epn_q'length-1), + din => mas2_2_epn_d(52-mas2_2_epn_d'length to 51), + dout => mas2_2_epn_q(52-mas2_2_epn_q'length to 51) ); +mas2_2_wimge_latch: tri_rlmreg_p + generic map (width => mas2_2_wimge_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas2_2_wimge_offset to mas2_2_wimge_offset+mas2_2_wimge_q'length-1), + scout => sov_1(mas2_2_wimge_offset to mas2_2_wimge_offset+mas2_2_wimge_q'length-1), + din => mas2_2_wimge_d(0 to mas2_2_wimge_d'length-1), + dout => mas2_2_wimge_q(0 to mas2_2_wimge_q'length-1) ); +mas3_2_rpnl_latch: tri_rlmreg_p + generic map (width => mas3_2_rpnl_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas3_2_rpnl_offset to mas3_2_rpnl_offset+mas3_2_rpnl_q'length-1), + scout => sov_1(mas3_2_rpnl_offset to mas3_2_rpnl_offset+mas3_2_rpnl_q'length-1), + din => mas3_2_rpnl_d(32 to 32+mas3_2_rpnl_d'length-1), + dout => mas3_2_rpnl_q(32 to 32+mas3_2_rpnl_q'length-1) ); +mas3_2_ubits_latch: tri_rlmreg_p + generic map (width => mas3_2_ubits_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas3_2_ubits_offset to mas3_2_ubits_offset+mas3_2_ubits_q'length-1), + scout => sov_1(mas3_2_ubits_offset to mas3_2_ubits_offset+mas3_2_ubits_q'length-1), + din => mas3_2_ubits_d(0 to mas3_2_ubits_d'length-1), + dout => mas3_2_ubits_q(0 to mas3_2_ubits_q'length-1) ); +mas3_2_usxwr_latch: tri_rlmreg_p + generic map (width => mas3_2_usxwr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas3_2_usxwr_offset to mas3_2_usxwr_offset+mas3_2_usxwr_q'length-1), + scout => sov_1(mas3_2_usxwr_offset to mas3_2_usxwr_offset+mas3_2_usxwr_q'length-1), + din => mas3_2_usxwr_d(0 to mas3_2_usxwr_d'length-1), + dout => mas3_2_usxwr_q(0 to mas3_2_usxwr_q'length-1) ); +mas4_2_indd_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(mas4_2_indd_offset), + scout => bsov(mas4_2_indd_offset), + din => mas4_2_indd_d, + dout => mas4_2_indd_q); +mas4_2_tsized_latch: tri_rlmreg_p + generic map (width => mas4_2_tsized_q'length, init => 1, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(mas4_2_tsized_offset to mas4_2_tsized_offset+mas4_2_tsized_q'length-1), + scout => bsov(mas4_2_tsized_offset to mas4_2_tsized_offset+mas4_2_tsized_q'length-1), + din => mas4_2_tsized_d(0 to mas4_2_tsized_d'length-1), + dout => mas4_2_tsized_q(0 to mas4_2_tsized_q'length-1) ); +mas4_2_wimged_latch: tri_rlmreg_p + generic map (width => mas4_2_wimged_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(mas4_2_wimged_offset to mas4_2_wimged_offset+mas4_2_wimged_q'length-1), + scout => bsov(mas4_2_wimged_offset to mas4_2_wimged_offset+mas4_2_wimged_q'length-1), + din => mas4_2_wimged_d(0 to mas4_2_wimged_d'length-1), + dout => mas4_2_wimged_q(0 to mas4_2_wimged_q'length-1) ); +mas5_2_sgs_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas5_2_sgs_offset), + scout => sov_1(mas5_2_sgs_offset), + din => mas5_2_sgs_d, + dout => mas5_2_sgs_q); +mas5_2_slpid_latch: tri_rlmreg_p + generic map (width => mas5_2_slpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas5_2_slpid_offset to mas5_2_slpid_offset+mas5_2_slpid_q'length-1), + scout => sov_1(mas5_2_slpid_offset to mas5_2_slpid_offset+mas5_2_slpid_q'length-1), + din => mas5_2_slpid_d(0 to mas5_2_slpid_d'length-1), + dout => mas5_2_slpid_q(0 to mas5_2_slpid_q'length-1) ); +mas6_2_spid_latch: tri_rlmreg_p + generic map (width => mas6_2_spid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas6_2_spid_offset to mas6_2_spid_offset+mas6_2_spid_q'length-1), + scout => sov_1(mas6_2_spid_offset to mas6_2_spid_offset+mas6_2_spid_q'length-1), + din => mas6_2_spid_d(0 to mas6_2_spid_d'length-1), + dout => mas6_2_spid_q(0 to mas6_2_spid_q'length-1) ); +mas6_2_isize_latch: tri_rlmreg_p + generic map (width => mas6_2_isize_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas6_2_isize_offset to mas6_2_isize_offset+mas6_2_isize_q'length-1), + scout => sov_1(mas6_2_isize_offset to mas6_2_isize_offset+mas6_2_isize_q'length-1), + din => mas6_2_isize_d(0 to mas6_2_isize_d'length-1), + dout => mas6_2_isize_q(0 to mas6_2_isize_q'length-1) ); +mas6_2_sind_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas6_2_sind_offset), + scout => sov_1(mas6_2_sind_offset), + din => mas6_2_sind_d, + dout => mas6_2_sind_q); +mas6_2_sas_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas6_2_sas_offset), + scout => sov_1(mas6_2_sas_offset), + din => mas6_2_sas_d, + dout => mas6_2_sas_q); +mas7_2_rpnu_latch: tri_rlmreg_p + generic map (width => mas7_2_rpnu_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas7_2_rpnu_offset to mas7_2_rpnu_offset+mas7_2_rpnu_q'length-1), + scout => sov_1(mas7_2_rpnu_offset to mas7_2_rpnu_offset+mas7_2_rpnu_q'length-1), + din => mas7_2_rpnu_d(22 to 22+mas7_2_rpnu_d'length-1), + dout => mas7_2_rpnu_q(22 to 22+mas7_2_rpnu_q'length-1) ); +mas8_2_tgs_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas8_2_tgs_offset), + scout => sov_1(mas8_2_tgs_offset), + din => mas8_2_tgs_d, + dout => mas8_2_tgs_q); +mas8_2_vf_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas8_2_vf_offset), + scout => sov_1(mas8_2_vf_offset), + din => mas8_2_vf_d, + dout => mas8_2_vf_q); +mas8_2_tlpid_latch: tri_rlmreg_p + generic map (width => mas8_2_tlpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas8_2_tlpid_offset to mas8_2_tlpid_offset+mas8_2_tlpid_q'length-1), + scout => sov_1(mas8_2_tlpid_offset to mas8_2_tlpid_offset+mas8_2_tlpid_q'length-1), + din => mas8_2_tlpid_d(0 to mas8_2_tlpid_d'length-1), + dout => mas8_2_tlpid_q(0 to mas8_2_tlpid_q'length-1) ); +mas0_3_atsel_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas0_3_atsel_offset), + scout => sov_1(mas0_3_atsel_offset), + din => mas0_3_atsel_d, + dout => mas0_3_atsel_q); +mas0_3_esel_latch: tri_rlmreg_p + generic map (width => mas0_3_esel_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas0_3_esel_offset to mas0_3_esel_offset+mas0_3_esel_q'length-1), + scout => sov_1(mas0_3_esel_offset to mas0_3_esel_offset+mas0_3_esel_q'length-1), + din => mas0_3_esel_d(0 to mas0_3_esel_d'length-1), + dout => mas0_3_esel_q(0 to mas0_3_esel_q'length-1) ); +mas0_3_hes_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas0_3_hes_offset), + scout => sov_1(mas0_3_hes_offset), + din => mas0_3_hes_d, + dout => mas0_3_hes_q); +mas0_3_wq_latch: tri_rlmreg_p + generic map (width => mas0_3_wq_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas0_3_wq_offset to mas0_3_wq_offset+mas0_3_wq_q'length-1), + scout => sov_1(mas0_3_wq_offset to mas0_3_wq_offset+mas0_3_wq_q'length-1), + din => mas0_3_wq_d(0 to mas0_3_wq_d'length-1), + dout => mas0_3_wq_q(0 to mas0_3_wq_q'length-1) ); +mas1_3_v_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas1_3_v_offset), + scout => sov_1(mas1_3_v_offset), + din => mas1_3_v_d, + dout => mas1_3_v_q); +mas1_3_iprot_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas1_3_iprot_offset), + scout => sov_1(mas1_3_iprot_offset), + din => mas1_3_iprot_d, + dout => mas1_3_iprot_q); +mas1_3_tid_latch: tri_rlmreg_p + generic map (width => mas1_3_tid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas1_3_tid_offset to mas1_3_tid_offset+mas1_3_tid_q'length-1), + scout => sov_1(mas1_3_tid_offset to mas1_3_tid_offset+mas1_3_tid_q'length-1), + din => mas1_3_tid_d(0 to mas1_3_tid_d'length-1), + dout => mas1_3_tid_q(0 to mas1_3_tid_q'length-1) ); +mas1_3_ind_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas1_3_ind_offset), + scout => sov_1(mas1_3_ind_offset), + din => mas1_3_ind_d, + dout => mas1_3_ind_q); +mas1_3_ts_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas1_3_ts_offset), + scout => sov_1(mas1_3_ts_offset), + din => mas1_3_ts_d, + dout => mas1_3_ts_q); +mas1_3_tsize_latch: tri_rlmreg_p + generic map (width => mas1_3_tsize_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas1_3_tsize_offset to mas1_3_tsize_offset+mas1_3_tsize_q'length-1), + scout => sov_1(mas1_3_tsize_offset to mas1_3_tsize_offset+mas1_3_tsize_q'length-1), + din => mas1_3_tsize_d(0 to mas1_3_tsize_d'length-1), + dout => mas1_3_tsize_q(0 to mas1_3_tsize_q'length-1) ); +mas2_3_epn_latch: tri_rlmreg_p + generic map (width => mas2_3_epn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas2_3_epn_offset to mas2_3_epn_offset+mas2_3_epn_q'length-1), + scout => sov_1(mas2_3_epn_offset to mas2_3_epn_offset+mas2_3_epn_q'length-1), + din => mas2_3_epn_d(52-mas2_3_epn_d'length to 51), + dout => mas2_3_epn_q(52-mas2_3_epn_q'length to 51) ); +mas2_3_wimge_latch: tri_rlmreg_p + generic map (width => mas2_3_wimge_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas2_3_wimge_offset to mas2_3_wimge_offset+mas2_3_wimge_q'length-1), + scout => sov_1(mas2_3_wimge_offset to mas2_3_wimge_offset+mas2_3_wimge_q'length-1), + din => mas2_3_wimge_d(0 to mas2_3_wimge_d'length-1), + dout => mas2_3_wimge_q(0 to mas2_3_wimge_q'length-1) ); +mas3_3_rpnl_latch: tri_rlmreg_p + generic map (width => mas3_3_rpnl_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas3_3_rpnl_offset to mas3_3_rpnl_offset+mas3_3_rpnl_q'length-1), + scout => sov_1(mas3_3_rpnl_offset to mas3_3_rpnl_offset+mas3_3_rpnl_q'length-1), + din => mas3_3_rpnl_d(32 to 32+mas3_3_rpnl_d'length-1), + dout => mas3_3_rpnl_q(32 to 32+mas3_3_rpnl_q'length-1) ); +mas3_3_ubits_latch: tri_rlmreg_p + generic map (width => mas3_3_ubits_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas3_3_ubits_offset to mas3_3_ubits_offset+mas3_3_ubits_q'length-1), + scout => sov_1(mas3_3_ubits_offset to mas3_3_ubits_offset+mas3_3_ubits_q'length-1), + din => mas3_3_ubits_d(0 to mas3_3_ubits_d'length-1), + dout => mas3_3_ubits_q(0 to mas3_3_ubits_q'length-1) ); +mas3_3_usxwr_latch: tri_rlmreg_p + generic map (width => mas3_3_usxwr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas3_3_usxwr_offset to mas3_3_usxwr_offset+mas3_3_usxwr_q'length-1), + scout => sov_1(mas3_3_usxwr_offset to mas3_3_usxwr_offset+mas3_3_usxwr_q'length-1), + din => mas3_3_usxwr_d(0 to mas3_3_usxwr_d'length-1), + dout => mas3_3_usxwr_q(0 to mas3_3_usxwr_q'length-1) ); +mas4_3_indd_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(mas4_3_indd_offset), + scout => bsov(mas4_3_indd_offset), + din => mas4_3_indd_d, + dout => mas4_3_indd_q); +mas4_3_tsized_latch: tri_rlmreg_p + generic map (width => mas4_3_tsized_q'length, init => 1, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(mas4_3_tsized_offset to mas4_3_tsized_offset+mas4_3_tsized_q'length-1), + scout => bsov(mas4_3_tsized_offset to mas4_3_tsized_offset+mas4_3_tsized_q'length-1), + din => mas4_3_tsized_d(0 to mas4_3_tsized_d'length-1), + dout => mas4_3_tsized_q(0 to mas4_3_tsized_q'length-1) ); +mas4_3_wimged_latch: tri_rlmreg_p + generic map (width => mas4_3_wimged_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(mas4_3_wimged_offset to mas4_3_wimged_offset+mas4_3_wimged_q'length-1), + scout => bsov(mas4_3_wimged_offset to mas4_3_wimged_offset+mas4_3_wimged_q'length-1), + din => mas4_3_wimged_d(0 to mas4_3_wimged_d'length-1), + dout => mas4_3_wimged_q(0 to mas4_3_wimged_q'length-1) ); +mas5_3_sgs_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas5_3_sgs_offset), + scout => sov_1(mas5_3_sgs_offset), + din => mas5_3_sgs_d, + dout => mas5_3_sgs_q); +mas5_3_slpid_latch: tri_rlmreg_p + generic map (width => mas5_3_slpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas5_3_slpid_offset to mas5_3_slpid_offset+mas5_3_slpid_q'length-1), + scout => sov_1(mas5_3_slpid_offset to mas5_3_slpid_offset+mas5_3_slpid_q'length-1), + din => mas5_3_slpid_d(0 to mas5_3_slpid_d'length-1), + dout => mas5_3_slpid_q(0 to mas5_3_slpid_q'length-1) ); +mas6_3_spid_latch: tri_rlmreg_p + generic map (width => mas6_3_spid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas6_3_spid_offset to mas6_3_spid_offset+mas6_3_spid_q'length-1), + scout => sov_1(mas6_3_spid_offset to mas6_3_spid_offset+mas6_3_spid_q'length-1), + din => mas6_3_spid_d(0 to mas6_3_spid_d'length-1), + dout => mas6_3_spid_q(0 to mas6_3_spid_q'length-1) ); +mas6_3_isize_latch: tri_rlmreg_p + generic map (width => mas6_3_isize_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas6_3_isize_offset to mas6_3_isize_offset+mas6_3_isize_q'length-1), + scout => sov_1(mas6_3_isize_offset to mas6_3_isize_offset+mas6_3_isize_q'length-1), + din => mas6_3_isize_d(0 to mas6_3_isize_d'length-1), + dout => mas6_3_isize_q(0 to mas6_3_isize_q'length-1) ); +mas6_3_sind_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas6_3_sind_offset), + scout => sov_1(mas6_3_sind_offset), + din => mas6_3_sind_d, + dout => mas6_3_sind_q); +mas6_3_sas_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas6_3_sas_offset), + scout => sov_1(mas6_3_sas_offset), + din => mas6_3_sas_d, + dout => mas6_3_sas_q); +mas7_3_rpnu_latch: tri_rlmreg_p + generic map (width => mas7_3_rpnu_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas7_3_rpnu_offset to mas7_3_rpnu_offset+mas7_3_rpnu_q'length-1), + scout => sov_1(mas7_3_rpnu_offset to mas7_3_rpnu_offset+mas7_3_rpnu_q'length-1), + din => mas7_3_rpnu_d(22 to 22+mas7_3_rpnu_d'length-1), + dout => mas7_3_rpnu_q(22 to 22+mas7_3_rpnu_q'length-1) ); +mas8_3_tgs_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas8_3_tgs_offset), + scout => sov_1(mas8_3_tgs_offset), + din => mas8_3_tgs_d, + dout => mas8_3_tgs_q); +mas8_3_vf_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas8_3_vf_offset), + scout => sov_1(mas8_3_vf_offset), + din => mas8_3_vf_d, + dout => mas8_3_vf_q); +mas8_3_tlpid_latch: tri_rlmreg_p + generic map (width => mas8_3_tlpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas8_3_tlpid_offset to mas8_3_tlpid_offset+mas8_3_tlpid_q'length-1), + scout => sov_1(mas8_3_tlpid_offset to mas8_3_tlpid_offset+mas8_3_tlpid_q'length-1), + din => mas8_3_tlpid_d(0 to mas8_3_tlpid_d'length-1), + dout => mas8_3_tlpid_q(0 to mas8_3_tlpid_q'length-1) ); +mmucsr0_tlb0fi_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mmucsr0_tlb0fi_offset), + scout => sov_1(mmucsr0_tlb0fi_offset), + din => mmucsr0_tlb0fi_d, + dout => mmucsr0_tlb0fi_q); +lper_0_alpn_latch: tri_rlmreg_p + generic map (width => lper_0_alpn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(lper_0_alpn_offset to lper_0_alpn_offset+lper_0_alpn_q'length-1), + scout => sov_1(lper_0_alpn_offset to lper_0_alpn_offset+lper_0_alpn_q'length-1), + din => lper_0_alpn_d, + dout => lper_0_alpn_q ); +lper_0_lps_latch: tri_rlmreg_p + generic map (width => lper_0_lps_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(lper_0_lps_offset to lper_0_lps_offset+lper_0_lps_q'length-1), + scout => sov_1(lper_0_lps_offset to lper_0_lps_offset+lper_0_lps_q'length-1), + din => lper_0_lps_d, + dout => lper_0_lps_q ); +lper_1_alpn_latch: tri_rlmreg_p + generic map (width => lper_1_alpn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(lper_1_alpn_offset to lper_1_alpn_offset+lper_1_alpn_q'length-1), + scout => sov_1(lper_1_alpn_offset to lper_1_alpn_offset+lper_1_alpn_q'length-1), + din => lper_1_alpn_d, + dout => lper_1_alpn_q ); +lper_1_lps_latch: tri_rlmreg_p + generic map (width => lper_1_lps_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(lper_1_lps_offset to lper_1_lps_offset+lper_1_lps_q'length-1), + scout => sov_1(lper_1_lps_offset to lper_1_lps_offset+lper_1_lps_q'length-1), + din => lper_1_lps_d, + dout => lper_1_lps_q ); +lper_2_alpn_latch: tri_rlmreg_p + generic map (width => lper_2_alpn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(lper_2_alpn_offset to lper_2_alpn_offset+lper_2_alpn_q'length-1), + scout => sov_1(lper_2_alpn_offset to lper_2_alpn_offset+lper_2_alpn_q'length-1), + din => lper_2_alpn_d, + dout => lper_2_alpn_q ); +lper_2_lps_latch: tri_rlmreg_p + generic map (width => lper_2_lps_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(lper_2_lps_offset to lper_2_lps_offset+lper_2_lps_q'length-1), + scout => sov_1(lper_2_lps_offset to lper_2_lps_offset+lper_2_lps_q'length-1), + din => lper_2_lps_d, + dout => lper_2_lps_q ); +lper_3_alpn_latch: tri_rlmreg_p + generic map (width => lper_3_alpn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(lper_3_alpn_offset to lper_3_alpn_offset+lper_3_alpn_q'length-1), + scout => sov_1(lper_3_alpn_offset to lper_3_alpn_offset+lper_3_alpn_q'length-1), + din => lper_3_alpn_d, + dout => lper_3_alpn_q ); +lper_3_lps_latch: tri_rlmreg_p + generic map (width => lper_3_lps_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(lper_3_lps_offset to lper_3_lps_offset+lper_3_lps_q'length-1), + scout => sov_1(lper_3_lps_offset to lper_3_lps_offset+lper_3_lps_q'length-1), + din => lper_3_lps_d, + dout => lper_3_lps_q ); +spr_mmu_act_latch: tri_rlmreg_p + generic map (width => spr_mmu_act_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spr_mmu_act_offset to spr_mmu_act_offset+spr_mmu_act_q'length-1), + scout => sov_0(spr_mmu_act_offset to spr_mmu_act_offset+spr_mmu_act_q'length-1), + din => spr_mmu_act_d, + dout => spr_mmu_act_q ); +spr_val_act_latch: tri_rlmreg_p + generic map (width => spr_val_act_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spr_val_act_offset to spr_val_act_offset+spr_val_act_q'length-1), + scout => sov_0(spr_val_act_offset to spr_val_act_offset+spr_val_act_q'length-1), + din => spr_val_act_d, + dout => spr_val_act_q ); +cswitch_latch: tri_rlmreg_p + generic map (width => cswitch_q'length, init => mmq_spr_cswitch_0to3, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(cswitch_offset to cswitch_offset+cswitch_q'length-1), + scout => sov_0(cswitch_offset to cswitch_offset+cswitch_q'length-1), + din => cswitch_q, + dout => cswitch_q ); +cat_emf_act_latch: tri_rlmreg_p + generic map (width => cat_emf_act_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(cat_emf_act_offset to cat_emf_act_offset+cat_emf_act_q'length-1), + scout => sov_1(cat_emf_act_offset to cat_emf_act_offset+cat_emf_act_q'length-1), + din => cat_emf_act_d, + dout => cat_emf_act_q ); +spare_a_latch: tri_rlmreg_p + generic map (width => spare_a_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spare_a_offset to spare_a_offset+spare_a_q'length-1), + scout => sov_0(spare_a_offset to spare_a_offset+spare_a_q'length-1), + din => spare_a_q, + dout => spare_a_q ); +spare_b_latch: tri_rlmreg_p + generic map (width => spare_b_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spare_b_offset to spare_b_offset+spare_b_q'length-1), + scout => sov_1(spare_b_offset to spare_b_offset+spare_b_q'length-1), + din => spare_b_q, + dout => spare_b_q ); +iu_mm_ierat_mmucr0_latch : tri_regk + generic map (width => iu_mm_ierat_mmucr0_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => pc_func_slp_nsl_force, + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_nsl_thold_0_b, + din => iu_mm_ierat_mmucr0, + dout => iu_mm_ierat_mmucr0_q); +iu_mm_ierat_mmucr0_we_latch : tri_regk + generic map (width => iu_mm_ierat_mmucr0_we_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => pc_func_slp_nsl_force, + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_nsl_thold_0_b, + din => iu_mm_ierat_mmucr0_we, + dout => iu_mm_ierat_mmucr0_we_q); +iu_mm_ierat_mmucr1_latch : tri_regk + generic map (width => iu_mm_ierat_mmucr1_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => pc_func_slp_nsl_force, + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_nsl_thold_0_b, + din => iu_mm_ierat_mmucr1, + dout => iu_mm_ierat_mmucr1_q); +xu_mm_derat_mmucr0_latch : tri_regk + generic map (width => xu_mm_derat_mmucr0_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => pc_func_slp_nsl_force, + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_nsl_thold_0_b, + din => xu_mm_derat_mmucr0, + dout => xu_mm_derat_mmucr0_q); +xu_mm_derat_mmucr0_we_latch : tri_regk + generic map (width => xu_mm_derat_mmucr0_we_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => pc_func_slp_nsl_force, + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_nsl_thold_0_b, + din => xu_mm_derat_mmucr0_we, + dout => xu_mm_derat_mmucr0_we_q); +xu_mm_derat_mmucr1_latch : tri_regk + generic map (width => xu_mm_derat_mmucr1_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => pc_func_slp_nsl_force, + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_nsl_thold_0_b, + din => xu_mm_derat_mmucr1, + dout => xu_mm_derat_mmucr1_q); +mm_erat_mmucr1_we_latch : tri_regk + generic map (width => 2, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => pc_func_slp_nsl_force, + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_nsl_thold_0_b, + din(0) => iu_mm_ierat_mmucr1_we, + din(1) => xu_mm_derat_mmucr1_we, + dout(0) => iu_mm_ierat_mmucr1_we_q, + dout(1) => xu_mm_derat_mmucr1_we_q); +mpg_bcfg_gen: if expand_type /= 1 generate +mmucfg_47to48_latch: tri_slat_scan + generic map (width => 2, init => std_ulogic_vector( to_unsigned( bcfg_mmucfg_value, 2 ) ), + reset_inverts_scan => true, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + dclk => lcb_dclk, + lclk => lcb_lclk, + scan_in => bsiv(mmucfg_offset to mmucfg_offset+1), + scan_out => bsov(mmucfg_offset to mmucfg_offset+1), + q => mmucfg_q(47 to 48), + q_b => mmucfg_q_b(47 to 48) ); +tlb0cfg_45to47_latch: tri_slat_scan + generic map (width => 3, init => std_ulogic_vector( to_unsigned( bcfg_tlb0cfg_value, 3 ) ), + reset_inverts_scan => true, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + dclk => lcb_dclk, + lclk => lcb_lclk, + scan_in => bsiv(tlb0cfg_offset to tlb0cfg_offset+2), + scan_out => bsov(tlb0cfg_offset to tlb0cfg_offset+2), + q => tlb0cfg_q(45 to 47), + q_b => tlb0cfg_q_b(45 to 47) ); +bcfg_spare_latch: tri_slat_scan + generic map (width => 16, init => std_ulogic_vector( to_unsigned( 0, 16 ) ), + reset_inverts_scan => true, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + dclk => lcb_dclk, + lclk => lcb_lclk, + scan_in => bsiv(bcfg_spare_offset to bcfg_spare_offset+bcfg_spare_q'length-1), + scan_out => bsov(bcfg_spare_offset to bcfg_spare_offset+bcfg_spare_q'length-1), + q => bcfg_spare_q, + q_b => bcfg_spare_q_b ); +end generate mpg_bcfg_gen; +fpga_bcfg_gen: if expand_type = 1 generate +mmucfg_47to48_latch: tri_rlmreg_p + generic map (width => 2, init => bcfg_mmucfg_value, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(mmucfg_offset to mmucfg_offset+1), + scout => bsov(mmucfg_offset to mmucfg_offset+1), + din => mmucfg_q(47 to 48), + dout => mmucfg_q(47 to 48) ); +tlb0cfg_45to47_latch: tri_rlmreg_p + generic map (width => 3, init => bcfg_tlb0cfg_value, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(tlb0cfg_offset to tlb0cfg_offset+2), + scout => bsov(tlb0cfg_offset to tlb0cfg_offset+2), + din => tlb0cfg_q(45 to 47), + dout => tlb0cfg_q(45 to 47) ); +bcfg_spare_latch: tri_rlmreg_p + generic map (width => 16, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(bcfg_spare_offset to bcfg_spare_offset+bcfg_spare_q'length-1), + scout => bsov(bcfg_spare_offset to bcfg_spare_offset+bcfg_spare_q'length-1), + din => bcfg_spare_q, + dout => bcfg_spare_q ); +end generate fpga_bcfg_gen; +perv_2to1_reg: tri_plat + generic map (width => 7, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ccflush_dc, + din(0) => pc_func_sl_thold_2, + din(1) => pc_func_slp_sl_thold_2, + din(2) => pc_cfg_sl_thold_2, + din(3) => pc_cfg_slp_sl_thold_2, + din(4) => pc_func_slp_nsl_thold_2, + din(5) => pc_sg_2, + din(6) => pc_fce_2, + q(0) => pc_func_sl_thold_1, + q(1) => pc_func_slp_sl_thold_1, + q(2) => pc_cfg_sl_thold_1, + q(3) => pc_cfg_slp_sl_thold_1, + q(4) => pc_func_slp_nsl_thold_1, + q(5) => pc_sg_1, + q(6) => pc_fce_1); +perv_1to0_reg: tri_plat + generic map (width => 7, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ccflush_dc, + din(0) => pc_func_sl_thold_1, + din(1) => pc_func_slp_sl_thold_1, + din(2) => pc_cfg_sl_thold_1, + din(3) => pc_cfg_slp_sl_thold_1, + din(4) => pc_func_slp_nsl_thold_1, + din(5) => pc_sg_1, + din(6) => pc_fce_1, + q(0) => pc_func_sl_thold_0, + q(1) => pc_func_slp_sl_thold_0, + q(2) => pc_cfg_sl_thold_0, + q(3) => pc_cfg_slp_sl_thold_0, + q(4) => pc_func_slp_nsl_thold_0, + q(5) => pc_sg_0, + q(6) => pc_fce_0); +perv_lcbor_func_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b, + thold => pc_func_sl_thold_0, + sg => pc_sg_0, + act_dis => lcb_act_dis_dc, + forcee => pc_func_sl_force, + thold_b => pc_func_sl_thold_0_b); +perv_lcbor_func_slp_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b, + thold => pc_func_slp_sl_thold_0, + sg => pc_sg_0, + act_dis => lcb_act_dis_dc, + forcee => pc_func_slp_sl_force, + thold_b => pc_func_slp_sl_thold_0_b); +perv_lcbor_cfg_slp_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b, + thold => pc_cfg_slp_sl_thold_0, + sg => pc_sg_0, + act_dis => lcb_act_dis_dc, + forcee => pc_cfg_slp_sl_force, + thold_b => pc_cfg_slp_sl_thold_0_b); +perv_lcbor_func_slp_nsl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b, + thold => pc_func_slp_nsl_thold_0, + sg => pc_fce_0, + act_dis => tidn, + forcee => pc_func_slp_nsl_force, + thold_b => pc_func_slp_nsl_thold_0_b); +pc_cfg_sl_thold_0_b <= NOT pc_cfg_sl_thold_0; +pc_cfg_sl_force <= pc_sg_0; +bcfg_lcb: tri_lcbs + generic map (expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + delay_lclkr => lcb_delay_lclkr_dc(0), + nclk => nclk, + forcee => pc_cfg_sl_force, + thold_b => pc_cfg_sl_thold_0_b, + dclk => lcb_dclk, + lclk => lcb_lclk ); +siv_0(0 to scan_right_0) <= sov_0(1 to scan_right_0) & ac_func_scan_in(0); +ac_func_scan_out(0) <= sov_0(0); +siv_1(0 to scan_right_1) <= sov_1(1 to scan_right_1) & ac_func_scan_in(1); +ac_func_scan_out(1) <= sov_1(0); +bsiv(0 to boot_scan_right) <= bsov(1 to boot_scan_right) & ac_bcfg_scan_in; +ac_bcfg_scan_out <= bsov(0); +end mmq_spr; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/mmq_tlb_cmp.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/mmq_tlb_cmp.vhdl new file mode 100644 index 0000000..719283b --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/mmq_tlb_cmp.vhdl @@ -0,0 +1,5370 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; +use ieee.std_logic_1164.all; +library ibm; +use ibm.std_ulogic_unsigned.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_support.all; +library support; +use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity mmq_tlb_cmp is + generic(thdid_width : integer := 4; + ttype_width : integer := 4; + state_width : integer := 3; + pid_width : integer := 14; + pid_width_erat : integer := 8; + lpid_width : integer := 8; + class_width : integer := 2; + extclass_width : integer := 2; + tlbsel_width : integer := 2; + epn_width : integer := 52; + vpn_width : integer := 61; + erat_cam_data_width : integer := 75; + erat_ary_data_width : integer := 73; + erat_rel_data_width : integer := 132; + ws_width : integer := 2; + rs_is_width : integer := 9; + ra_entry_width : integer := 12; + rs_data_width : integer := 64; + data_out_width : integer := 64; + error_width : integer := 3; + tlb_num_entry : natural := 512; + tlb_num_entry_log2 : natural := 9; + tlb_ways : natural := 4; + tlb_addr_width : natural := 7; + tlb_way_width : natural := 168; + tlb_word_width : natural := 84; + tlb_seq_width : integer := 6; + inv_seq_width : integer := 5; + por_seq_width : integer := 3; + watermark_width : integer := 4; + eptr_width : integer := 4; + lru_width : integer := 16; + mmucr0_width : integer := 20; + mmucr1_width : integer := 32; + mmucr2_width : integer := 32; + mmucr3_width : integer := 15; + spr_ctl_width : integer := 3; + spr_etid_width : integer := 2; + spr_addr_width : integer := 10; + spr_data_width : integer := 64; + debug_trace_width : integer := 88; + debug_event_width : integer := 16; + real_addr_width : integer := 42; + rpn_width : integer := 30; + pte_width : integer := 64; + check_parity : integer := 1; + tlb_tag_width : natural := 110; + mmq_tlb_cmp_cswitch_0to7 : integer := 0; + expand_type : integer := 2 ); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + +tc_ccflush_dc : in std_ulogic; +tc_scan_dis_dc_b : in std_ulogic; +tc_scan_diag_dc : in std_ulogic; +tc_lbist_en_dc : in std_ulogic; +lcb_d_mode_dc : in std_ulogic; +lcb_clkoff_dc_b : in std_ulogic; +lcb_act_dis_dc : in std_ulogic; +lcb_mpw1_dc_b : in std_ulogic_vector(0 to 4); +lcb_mpw2_dc_b : in std_ulogic; +lcb_delay_lclkr_dc : in std_ulogic_vector(0 to 4); +ac_func_scan_in :in std_ulogic_vector(0 to 2); +ac_func_scan_out :out std_ulogic_vector(0 to 2); +pc_sg_2 : in std_ulogic; +pc_func_sl_thold_2 : in std_ulogic; +pc_func_slp_sl_thold_2 : in std_ulogic; +pc_func_slp_nsl_thold_2 : in std_ulogic; +pc_fce_2 : in std_ulogic; +xu_mm_ccr2_notlb_b : in std_ulogic; +xu_mm_spr_epcr_dmiuh : in std_ulogic_vector(0 to thdid_width-1); +xu_mm_epcr_dgtmi : in std_ulogic_vector(0 to thdid_width-1); +xu_mm_msr_gs : in std_ulogic_vector(0 to thdid_width-1); +xu_mm_msr_pr : in std_ulogic_vector(0 to thdid_width-1); +xu_mm_xucr4_mmu_mchk_q : in std_ulogic; +lpidr : in std_ulogic_vector(0 to lpid_width-1); +mmucr1 : in std_ulogic_vector(10 to 18); +mmucr3_0 : in std_ulogic_vector(64-mmucr3_width to 63); +mmucr3_1 : in std_ulogic_vector(64-mmucr3_width to 63); +mmucr3_2 : in std_ulogic_vector(64-mmucr3_width to 63); +mmucr3_3 : in std_ulogic_vector(64-mmucr3_width to 63); +mm_iu_ierat_rel_val : out std_ulogic_vector(0 to 4); +mm_iu_ierat_rel_data : out std_ulogic_vector(0 to erat_rel_data_width-1); +mm_xu_derat_rel_val : out std_ulogic_vector(0 to 4); +mm_xu_derat_rel_data : out std_ulogic_vector(0 to erat_rel_data_width-1); +tlb_cmp_ierat_dup_val : out std_ulogic_vector(0 to 6); +tlb_cmp_derat_dup_val : out std_ulogic_vector(0 to 6); +tlb_cmp_erat_dup_wait : out std_ulogic_vector(0 to 1); +ierat_req0_pid : in std_ulogic_vector(0 to pid_width-1); +ierat_req0_as : in std_ulogic; +ierat_req0_gs : in std_ulogic; +ierat_req0_epn : in std_ulogic_vector(0 to epn_width-1); +ierat_req0_thdid : in std_ulogic_vector(0 to thdid_width-1); +ierat_req0_valid : in std_ulogic; +ierat_req0_nonspec : in std_ulogic; +ierat_req1_pid : in std_ulogic_vector(0 to pid_width-1); +ierat_req1_as : in std_ulogic; +ierat_req1_gs : in std_ulogic; +ierat_req1_epn : in std_ulogic_vector(0 to epn_width-1); +ierat_req1_thdid : in std_ulogic_vector(0 to thdid_width-1); +ierat_req1_valid : in std_ulogic; +ierat_req1_nonspec : in std_ulogic; +ierat_req2_pid : in std_ulogic_vector(0 to pid_width-1); +ierat_req2_as : in std_ulogic; +ierat_req2_gs : in std_ulogic; +ierat_req2_epn : in std_ulogic_vector(0 to epn_width-1); +ierat_req2_thdid : in std_ulogic_vector(0 to thdid_width-1); +ierat_req2_valid : in std_ulogic; +ierat_req2_nonspec : in std_ulogic; +ierat_req3_pid : in std_ulogic_vector(0 to pid_width-1); +ierat_req3_as : in std_ulogic; +ierat_req3_gs : in std_ulogic; +ierat_req3_epn : in std_ulogic_vector(0 to epn_width-1); +ierat_req3_thdid : in std_ulogic_vector(0 to thdid_width-1); +ierat_req3_valid : in std_ulogic; +ierat_req3_nonspec : in std_ulogic; +ierat_iu4_pid : in std_ulogic_vector(0 to pid_width-1); +ierat_iu4_gs : in std_ulogic; +ierat_iu4_as : in std_ulogic; +ierat_iu4_epn : in std_ulogic_vector(0 to epn_width-1); +ierat_iu4_thdid : in std_ulogic_vector(0 to thdid_width-1); +ierat_iu4_valid : in std_ulogic; +derat_req0_lpid : in std_ulogic_vector(0 to lpid_width-1); +derat_req0_pid : in std_ulogic_vector(0 to pid_width-1); +derat_req0_as : in std_ulogic; +derat_req0_gs : in std_ulogic; +derat_req0_epn : in std_ulogic_vector(0 to epn_width-1); +derat_req0_thdid : in std_ulogic_vector(0 to thdid_width-1); +derat_req0_valid : in std_ulogic; +derat_req1_lpid : in std_ulogic_vector(0 to lpid_width-1); +derat_req1_pid : in std_ulogic_vector(0 to pid_width-1); +derat_req1_as : in std_ulogic; +derat_req1_gs : in std_ulogic; +derat_req1_epn : in std_ulogic_vector(0 to epn_width-1); +derat_req1_thdid : in std_ulogic_vector(0 to thdid_width-1); +derat_req1_valid : in std_ulogic; +derat_req2_lpid : in std_ulogic_vector(0 to lpid_width-1); +derat_req2_pid : in std_ulogic_vector(0 to pid_width-1); +derat_req2_as : in std_ulogic; +derat_req2_gs : in std_ulogic; +derat_req2_epn : in std_ulogic_vector(0 to epn_width-1); +derat_req2_thdid : in std_ulogic_vector(0 to thdid_width-1); +derat_req2_valid : in std_ulogic; +derat_req3_lpid : in std_ulogic_vector(0 to lpid_width-1); +derat_req3_pid : in std_ulogic_vector(0 to pid_width-1); +derat_req3_as : in std_ulogic; +derat_req3_gs : in std_ulogic; +derat_req3_epn : in std_ulogic_vector(0 to epn_width-1); +derat_req3_thdid : in std_ulogic_vector(0 to thdid_width-1); +derat_req3_valid : in std_ulogic; +derat_ex5_lpid : in std_ulogic_vector(0 to lpid_width-1); +derat_ex5_pid : in std_ulogic_vector(0 to pid_width-1); +derat_ex5_gs : in std_ulogic; +derat_ex5_as : in std_ulogic; +derat_ex5_epn : in std_ulogic_vector(0 to epn_width-1); +derat_ex5_thdid : in std_ulogic_vector(0 to thdid_width-1); +derat_ex5_valid : in std_ulogic; +tlb_tag2 : in std_ulogic_vector(0 to tlb_tag_width-1); +tlb_addr2 : in std_ulogic_vector(0 to tlb_addr_width-1); +ex6_illeg_instr : in std_ulogic_vector(0 to 1); +ierat_req_taken : in std_ulogic; +derat_req_taken : in std_ulogic; +ptereload_req_taken : in std_ulogic; +tlb_tag0_type : in std_ulogic_vector(0 to 1); +lrat_tag3_lpn : in std_ulogic_vector(64-real_addr_width to 51); +lrat_tag3_rpn : in std_ulogic_vector(64-real_addr_width to 51); +lrat_tag3_hit_status : in std_ulogic_vector(0 to 3); +lrat_tag3_hit_entry : in std_ulogic_vector(0 to 2); +lrat_tag4_lpn : in std_ulogic_vector(64-real_addr_width to 51); +lrat_tag4_rpn : in std_ulogic_vector(64-real_addr_width to 51); +lrat_tag4_hit_status : in std_ulogic_vector(0 to 3); +lrat_tag4_hit_entry : in std_ulogic_vector(0 to 2); +lru_dataout : in std_ulogic_vector(0 to 15); +tlb_dataout : in std_ulogic_vector(0 to tlb_way_width*tlb_ways-1); +tlb_dataina : out std_ulogic_vector(0 to tlb_way_width-1); +tlb_datainb : out std_ulogic_vector(0 to tlb_way_width-1); +lru_wr_addr : out std_ulogic_vector(0 to tlb_addr_width-1); +lru_write : out std_ulogic_vector(0 to 15); +lru_datain : out std_ulogic_vector(0 to 15); +lru_tag4_dataout : out std_ulogic_vector(0 to 15); +tlb_tag4_esel : out std_ulogic_vector(0 to 2); +tlb_tag4_wq : out std_ulogic_vector(0 to 1); +tlb_tag4_is : out std_ulogic_vector(0 to 1); +tlb_tag4_gs : out std_ulogic; +tlb_tag4_pr : out std_ulogic; +tlb_tag4_hes : out std_ulogic; +tlb_tag4_atsel : out std_ulogic; +tlb_tag4_pt : out std_ulogic; +tlb_tag4_cmp_hit : out std_ulogic; +tlb_tag4_way_ind : out std_ulogic; +tlb_tag4_ptereload : out std_ulogic; +tlb_tag4_endflag : out std_ulogic; +tlb_tag4_parerr : out std_ulogic; +tlb_tag5_except : out std_ulogic_vector(0 to thdid_width-1); +mmucfg_twc : in std_ulogic; +mmucfg_lrat : in std_ulogic; +tlb0cfg_pt : in std_ulogic; +tlb0cfg_gtwe : in std_ulogic; +tlb0cfg_ind : in std_ulogic; +mas2_0_wimge : in std_ulogic_vector(0 to 4); +mas3_0_rpnl : in std_ulogic_vector(32 to 52); +mas3_0_ubits : in std_ulogic_vector(0 to 3); +mas3_0_usxwr : in std_ulogic_vector(0 to 5); +mas7_0_rpnu : in std_ulogic_vector(22 to 31); +mas8_0_vf : in std_ulogic; +mas2_1_wimge : in std_ulogic_vector(0 to 4); +mas3_1_rpnl : in std_ulogic_vector(32 to 52); +mas3_1_ubits : in std_ulogic_vector(0 to 3); +mas3_1_usxwr : in std_ulogic_vector(0 to 5); +mas7_1_rpnu : in std_ulogic_vector(22 to 31); +mas8_1_vf : in std_ulogic; +mas2_2_wimge : in std_ulogic_vector(0 to 4); +mas3_2_rpnl : in std_ulogic_vector(32 to 52); +mas3_2_ubits : in std_ulogic_vector(0 to 3); +mas3_2_usxwr : in std_ulogic_vector(0 to 5); +mas7_2_rpnu : in std_ulogic_vector(22 to 31); +mas8_2_vf : in std_ulogic; +mas2_3_wimge : in std_ulogic_vector(0 to 4); +mas3_3_rpnl : in std_ulogic_vector(32 to 52); +mas3_3_ubits : in std_ulogic_vector(0 to 3); +mas3_3_usxwr : in std_ulogic_vector(0 to 5); +mas7_3_rpnu : in std_ulogic_vector(22 to 31); +mas8_3_vf : in std_ulogic; +tlb_mas0_esel : out std_ulogic_vector(0 to 2); +tlb_mas1_v : out std_ulogic; +tlb_mas1_iprot : out std_ulogic; +tlb_mas1_tid : out std_ulogic_vector(0 to pid_width-1); +tlb_mas1_tid_error : out std_ulogic_vector(0 to pid_width-1); +tlb_mas1_ind : out std_ulogic; +tlb_mas1_ts : out std_ulogic; +tlb_mas1_ts_error : out std_ulogic; +tlb_mas1_tsize : out std_ulogic_vector(0 to 3); +tlb_mas2_epn : out std_ulogic_vector(0 to epn_width-1); +tlb_mas2_epn_error : out std_ulogic_vector(0 to epn_width-1); +tlb_mas2_wimge : out std_ulogic_vector(0 to 4); +tlb_mas3_rpnl : out std_ulogic_vector(32 to 51); +tlb_mas3_ubits : out std_ulogic_vector(0 to 3); +tlb_mas3_usxwr : out std_ulogic_vector(0 to 5); +tlb_mas6_spid : out std_ulogic_vector(0 to pid_width-1); +tlb_mas6_isize : out std_ulogic_vector(0 to 3); +tlb_mas6_sind : out std_ulogic; +tlb_mas6_sas : out std_ulogic; +tlb_mas7_rpnu : out std_ulogic_vector(22 to 31); +tlb_mas8_tgs : out std_ulogic; +tlb_mas8_vf : out std_ulogic; +tlb_mas8_tlpid : out std_ulogic_vector(0 to 7); +tlb_mmucr1_een : out std_ulogic_vector(0 to 8); +tlb_mmucr1_we : out std_ulogic; +tlb_mmucr3_thdid : out std_ulogic_vector(0 to thdid_width-1); +tlb_mmucr3_resvattr : out std_ulogic; +tlb_mmucr3_wlc : out std_ulogic_vector(0 to 1); +tlb_mmucr3_class : out std_ulogic_vector(0 to class_width-1); +tlb_mmucr3_extclass : out std_ulogic_vector(0 to extclass_width-1); +tlb_mmucr3_rc : out std_ulogic_vector(0 to 1); +tlb_mmucr3_x : out std_ulogic; +tlb_mas_tlbre : out std_ulogic; +tlb_mas_tlbsx_hit : out std_ulogic; +tlb_mas_tlbsx_miss : out std_ulogic; +tlb_mas_dtlb_error : out std_ulogic; +tlb_mas_itlb_error : out std_ulogic; +tlb_mas_thdid : out std_ulogic_vector(0 to thdid_width-1); +tlb_htw_req_valid : out std_ulogic; +tlb_htw_req_tag : out std_ulogic_vector(0 to tlb_tag_width-1); +tlb_htw_req_way : out std_ulogic_vector(tlb_word_width to tlb_way_width-1); +tlbwe_back_inv_valid : out std_ulogic; +tlbwe_back_inv_thdid : out std_ulogic_vector(0 to thdid_width-1); +tlbwe_back_inv_addr : out std_ulogic_vector(52-epn_width to 51); +tlbwe_back_inv_attr : out std_ulogic_vector(0 to 34); +ptereload_req_pte_lat : in std_ulogic_vector(0 to pte_width-1); +tlb_ctl_tag2_flush : in std_ulogic_vector(0 to thdid_width-1); +tlb_ctl_tag3_flush : in std_ulogic_vector(0 to thdid_width-1); +tlb_ctl_tag4_flush : in std_ulogic_vector(0 to thdid_width-1); +tlb_resv_match_vec : in std_ulogic_vector(0 to thdid_width-1); +mm_xu_eratmiss_done : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_tlb_miss : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_tlb_inelig : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_lrat_miss : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_pt_fault : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_hv_priv : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_esr_pt : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_esr_data : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_esr_epid : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_esr_st : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_cr0_eq : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_cr0_eq_valid : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_tlb_multihit_err : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_tlb_par_err : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_lru_par_err : out std_ulogic_vector(0 to thdid_width-1); +tlb_delayed_act : in std_ulogic_vector(9 to 16); +tlb_cmp_perf_event_t0 : out std_ulogic_vector(0 to 9); +tlb_cmp_perf_event_t1 : out std_ulogic_vector(0 to 9); +tlb_cmp_perf_event_t2 : out std_ulogic_vector(0 to 9); +tlb_cmp_perf_event_t3 : out std_ulogic_vector(0 to 9); +tlb_cmp_perf_state : out std_ulogic_vector(0 to 1); +tlb_cmp_perf_miss_direct : out std_ulogic; +tlb_cmp_perf_hit_indirect : out std_ulogic; +tlb_cmp_perf_hit_first_page : out std_ulogic; +tlb_cmp_perf_ptereload_noexcep : out std_ulogic; +tlb_cmp_perf_lrat_request : out std_ulogic; +tlb_cmp_perf_lrat_miss : out std_ulogic; +tlb_cmp_perf_pt_fault : out std_ulogic; +tlb_cmp_perf_pt_inelig : out std_ulogic; +tlb_cmp_dbg_tag4 : out std_ulogic_vector(0 to tlb_tag_width-1); +tlb_cmp_dbg_tag4_wayhit : out std_ulogic_vector(0 to tlb_ways); +tlb_cmp_dbg_addr4 : out std_ulogic_vector(0 to tlb_addr_width-1); +tlb_cmp_dbg_tag4_way : out std_ulogic_vector(0 to tlb_way_width-1); +tlb_cmp_dbg_tag4_parerr : out std_ulogic_vector(0 to 4); +tlb_cmp_dbg_tag4_lru_dataout_q : out std_ulogic_vector(0 to 11); +tlb_cmp_dbg_tag5_tlb_datain_q : out std_ulogic_vector(0 to tlb_way_width-1); +tlb_cmp_dbg_tag5_lru_datain_q : out std_ulogic_vector(0 to 11); +tlb_cmp_dbg_tag5_lru_write : out std_ulogic; +tlb_cmp_dbg_tag5_any_exception : out std_ulogic; +tlb_cmp_dbg_tag5_except_type_q : out std_ulogic_vector(0 to 3); +tlb_cmp_dbg_tag5_except_thdid_q : out std_ulogic_vector(0 to 1); +tlb_cmp_dbg_tag5_erat_rel_val : out std_ulogic_vector(0 to 9); +tlb_cmp_dbg_tag5_erat_rel_data : out std_ulogic_vector(0 to 131); +tlb_cmp_dbg_erat_dup_q : out std_ulogic_vector(0 to 19); +tlb_cmp_dbg_addr_enable : out std_ulogic_vector(0 to 8); +tlb_cmp_dbg_pgsize_enable : out std_ulogic; +tlb_cmp_dbg_class_enable : out std_ulogic; +tlb_cmp_dbg_extclass_enable : out std_ulogic_vector(0 to 1); +tlb_cmp_dbg_state_enable : out std_ulogic_vector(0 to 1); +tlb_cmp_dbg_thdid_enable : out std_ulogic; +tlb_cmp_dbg_pid_enable : out std_ulogic; +tlb_cmp_dbg_lpid_enable : out std_ulogic; +tlb_cmp_dbg_ind_enable : out std_ulogic; +tlb_cmp_dbg_iprot_enable : out std_ulogic; +tlb_cmp_dbg_way0_entry_v : out std_ulogic; +tlb_cmp_dbg_way0_addr_match : out std_ulogic; +tlb_cmp_dbg_way0_pgsize_match : out std_ulogic; +tlb_cmp_dbg_way0_class_match : out std_ulogic; +tlb_cmp_dbg_way0_extclass_match : out std_ulogic; +tlb_cmp_dbg_way0_state_match : out std_ulogic; +tlb_cmp_dbg_way0_thdid_match : out std_ulogic; +tlb_cmp_dbg_way0_pid_match : out std_ulogic; +tlb_cmp_dbg_way0_lpid_match : out std_ulogic; +tlb_cmp_dbg_way0_ind_match : out std_ulogic; +tlb_cmp_dbg_way0_iprot_match : out std_ulogic; +tlb_cmp_dbg_way1_entry_v : out std_ulogic; +tlb_cmp_dbg_way1_addr_match : out std_ulogic; +tlb_cmp_dbg_way1_pgsize_match : out std_ulogic; +tlb_cmp_dbg_way1_class_match : out std_ulogic; +tlb_cmp_dbg_way1_extclass_match : out std_ulogic; +tlb_cmp_dbg_way1_state_match : out std_ulogic; +tlb_cmp_dbg_way1_thdid_match : out std_ulogic; +tlb_cmp_dbg_way1_pid_match : out std_ulogic; +tlb_cmp_dbg_way1_lpid_match : out std_ulogic; +tlb_cmp_dbg_way1_ind_match : out std_ulogic; +tlb_cmp_dbg_way1_iprot_match : out std_ulogic; +tlb_cmp_dbg_way2_entry_v : out std_ulogic; +tlb_cmp_dbg_way2_addr_match : out std_ulogic; +tlb_cmp_dbg_way2_pgsize_match : out std_ulogic; +tlb_cmp_dbg_way2_class_match : out std_ulogic; +tlb_cmp_dbg_way2_extclass_match : out std_ulogic; +tlb_cmp_dbg_way2_state_match : out std_ulogic; +tlb_cmp_dbg_way2_thdid_match : out std_ulogic; +tlb_cmp_dbg_way2_pid_match : out std_ulogic; +tlb_cmp_dbg_way2_lpid_match : out std_ulogic; +tlb_cmp_dbg_way2_ind_match : out std_ulogic; +tlb_cmp_dbg_way2_iprot_match : out std_ulogic; +tlb_cmp_dbg_way3_entry_v : out std_ulogic; +tlb_cmp_dbg_way3_addr_match : out std_ulogic; +tlb_cmp_dbg_way3_pgsize_match : out std_ulogic; +tlb_cmp_dbg_way3_class_match : out std_ulogic; +tlb_cmp_dbg_way3_extclass_match : out std_ulogic; +tlb_cmp_dbg_way3_state_match : out std_ulogic; +tlb_cmp_dbg_way3_thdid_match : out std_ulogic; +tlb_cmp_dbg_way3_pid_match : out std_ulogic; +tlb_cmp_dbg_way3_lpid_match : out std_ulogic; +tlb_cmp_dbg_way3_ind_match : out std_ulogic; +tlb_cmp_dbg_way3_iprot_match : out std_ulogic +); +end mmq_tlb_cmp; +ARCHITECTURE MMQ_TLB_CMP + OF MMQ_TLB_CMP + IS +SIGNAL LRU_UPDATE_DATA_PT : STD_ULOGIC_VECTOR(1 TO 175) := +(OTHERS=> 'U'); +component mmq_tlb_matchline + generic ( have_xbit : integer := 1; + num_pgsizes : integer := 5; + have_cmpmask : integer := 1; + cmpmask_width : integer := 5); +port( + vdd : inout power_logic; + gnd : inout power_logic; + addr_in : in std_ulogic_vector(0 to 51); + addr_enable : in std_ulogic_vector(0 to 8); + comp_pgsize : in std_ulogic_vector(0 to 3); + pgsize_enable : in std_ulogic; + entry_size : in std_ulogic_vector(0 to 3); + entry_cmpmask : in std_ulogic_vector(0 to cmpmask_width-1); + entry_xbit : in std_ulogic; + entry_xbitmask : in std_ulogic_vector(0 to cmpmask_width-1); + entry_epn : in std_ulogic_vector(0 to 51); + comp_class : in std_ulogic_vector(0 to 1); + entry_class : in std_ulogic_vector(0 to 1); + class_enable : in std_ulogic; + comp_extclass : in std_ulogic_vector(0 to 1); + entry_extclass : in std_ulogic_vector(0 to 1); + extclass_enable : in std_ulogic_vector(0 to 1); + comp_state : in std_ulogic_vector(0 to 1); + entry_gs : in std_ulogic; + entry_ts : in std_ulogic; + state_enable : in std_ulogic_vector(0 to 1); + entry_thdid : in std_ulogic_vector(0 to 3); + comp_thdid : in std_ulogic_vector(0 to 3); + thdid_enable : in std_ulogic; + entry_pid : in std_ulogic_vector(0 to 13); + comp_pid : in std_ulogic_vector(0 to 13); + pid_enable : in std_ulogic; + entry_lpid : in std_ulogic_vector(0 to 7); + comp_lpid : in std_ulogic_vector(0 to 7); + lpid_enable : in std_ulogic; + entry_ind : in std_ulogic; + comp_ind : in std_ulogic; + ind_enable : in std_ulogic; + entry_iprot : in std_ulogic; + comp_iprot : in std_ulogic; + iprot_enable : in std_ulogic; + entry_v : in std_ulogic; + comp_invalidate : in std_ulogic; + + match : out std_ulogic; + dbg_addr_match : out std_ulogic; + dbg_pgsize_match : out std_ulogic; + dbg_class_match : out std_ulogic; + dbg_extclass_match : out std_ulogic; + dbg_state_match : out std_ulogic; + dbg_thdid_match : out std_ulogic; + dbg_pid_match : out std_ulogic; + dbg_lpid_match : out std_ulogic; + dbg_ind_match : out std_ulogic; + dbg_iprot_match : out std_ulogic +); +end component; +constant MMU_Mode_Value : std_ulogic := '0'; +constant TlbSel_Tlb : std_ulogic_vector(0 to 1) := "00"; +constant TlbSel_IErat : std_ulogic_vector(0 to 1) := "10"; +constant TlbSel_DErat : std_ulogic_vector(0 to 1) := "11"; +constant ERAT_PgSize_1GB : std_ulogic_vector(0 to 2) := "110"; +constant ERAT_PgSize_16MB : std_ulogic_vector(0 to 2) := "111"; +constant ERAT_PgSize_1MB : std_ulogic_vector(0 to 2) := "101"; +constant ERAT_PgSize_64KB : std_ulogic_vector(0 to 2) := "011"; +constant ERAT_PgSize_4KB : std_ulogic_vector(0 to 2) := "001"; +constant TLB_PgSize_1GB : std_ulogic_vector(0 to 3) := "1010"; +constant TLB_PgSize_16MB : std_ulogic_vector(0 to 3) := "0111"; +constant TLB_PgSize_1MB : std_ulogic_vector(0 to 3) := "0101"; +constant TLB_PgSize_64KB : std_ulogic_vector(0 to 3) := "0011"; +constant TLB_PgSize_4KB : std_ulogic_vector(0 to 3) := "0001"; +constant ERAT_PgSize_256MB : std_ulogic_vector(0 to 2) := "100"; +constant TLB_PgSize_256MB : std_ulogic_vector(0 to 3) := "1001"; +constant tlb_way0_offset : natural := 0; +constant tlb_way1_offset : natural := tlb_way0_offset + tlb_way_width; +constant tlb_way0_cmpmask_offset : natural := tlb_way1_offset + tlb_way_width; +constant tlb_way1_cmpmask_offset : natural := tlb_way0_cmpmask_offset + 5; +constant tlb_way0_xbitmask_offset : natural := tlb_way1_cmpmask_offset + 5; +constant tlb_way1_xbitmask_offset : natural := tlb_way0_xbitmask_offset + 5; +constant tlb_tag3_cmpmask_offset : natural := tlb_way1_xbitmask_offset + 5; +constant tlb_tag3_clone1_offset : natural := tlb_tag3_cmpmask_offset + 5; +constant tlb_tag4_way_offset : natural := tlb_tag3_clone1_offset + tlb_tag_width; +constant tlb_tag4_way_rw_offset : natural := tlb_tag4_way_offset + tlb_way_width; +constant tlb_dataina_offset : natural := tlb_tag4_way_rw_offset + tlb_way_width; +constant tlb_erat_rel_offset : natural := tlb_dataina_offset + tlb_way_width; +constant mmucr1_offset : natural := tlb_erat_rel_offset + 132; +constant spare_a_offset : natural := mmucr1_offset + 9; +constant scan_right_0 : natural := spare_a_offset + 16 -1; +constant tlb_way2_offset : natural := 0; +constant tlb_way3_offset : natural := tlb_way2_offset + tlb_way_width; +constant tlb_way2_cmpmask_offset : natural := tlb_way3_offset + tlb_way_width; +constant tlb_way3_cmpmask_offset : natural := tlb_way2_cmpmask_offset + 5; +constant tlb_way2_xbitmask_offset : natural := tlb_way3_cmpmask_offset + 5; +constant tlb_way3_xbitmask_offset : natural := tlb_way2_xbitmask_offset + 5; +constant tlb_tag3_clone2_offset : natural := tlb_way3_xbitmask_offset + 5; +constant tlb_tag3_cmpmask_clone_offset : natural := tlb_tag3_clone2_offset + tlb_tag_width; +constant tlb_erat_rel_clone_offset : natural := tlb_tag3_cmpmask_clone_offset + 5; +constant tlb_tag4_way_clone_offset : natural := tlb_erat_rel_clone_offset + 132; +constant tlb_tag4_way_rw_clone_offset : natural := tlb_tag4_way_clone_offset + tlb_way_width; +constant tlb_datainb_offset : natural := tlb_tag4_way_rw_clone_offset + tlb_way_width; +constant mmucr1_clone_offset : natural := tlb_datainb_offset + tlb_way_width; +constant spare_b_offset : natural := mmucr1_clone_offset + 9; +constant scan_right_1 : natural := spare_b_offset + 16 -1; +constant tlb_tag3_offset : natural := 0; +constant tlb_addr3_offset : natural := tlb_tag3_offset + tlb_tag_width; +constant lru_tag3_dataout_offset : natural := tlb_addr3_offset + tlb_addr_width; +constant tlb_tag4_offset : natural := lru_tag3_dataout_offset + 16; +constant tlb_tag4_wayhit_offset : natural := tlb_tag4_offset + tlb_tag_width; +constant tlb_addr4_offset : natural := tlb_tag4_wayhit_offset + tlb_ways+1; +constant lru_tag4_dataout_offset : natural := tlb_addr4_offset + tlb_addr_width; +constant tlbwe_tag4_back_inv_offset : natural := lru_tag4_dataout_offset + 16; +constant tlbwe_tag4_back_inv_attr_offset : natural := tlbwe_tag4_back_inv_offset + thdid_width + 1; +constant tlb_erat_val_offset : natural := tlbwe_tag4_back_inv_attr_offset + 2; +constant tlb_erat_dup_offset : natural := tlb_erat_val_offset + 2*thdid_width+2; +constant lru_write_offset : natural := tlb_erat_dup_offset + 2*thdid_width+12; +constant lru_wr_addr_offset : natural := lru_write_offset + 16; +constant lru_datain_offset : natural := lru_wr_addr_offset + tlb_addr_width; +constant eratmiss_done_offset : natural := lru_datain_offset + 16; +constant tlb_miss_offset : natural := eratmiss_done_offset + thdid_width; +constant tlb_inelig_offset : natural := tlb_miss_offset + thdid_width; +constant lrat_miss_offset : natural := tlb_inelig_offset + thdid_width; +constant pt_fault_offset : natural := lrat_miss_offset + thdid_width; +constant hv_priv_offset : natural := pt_fault_offset + thdid_width; +constant tlb_tag5_except_offset : natural := hv_priv_offset + thdid_width; +constant tlb_dsi_offset : natural := tlb_tag5_except_offset + thdid_width; +constant tlb_isi_offset : natural := tlb_dsi_offset + thdid_width; +constant esr_pt_offset : natural := tlb_isi_offset + thdid_width; +constant esr_data_offset : natural := esr_pt_offset + thdid_width; +constant esr_epid_offset : natural := esr_data_offset + thdid_width; +constant esr_st_offset : natural := esr_epid_offset + thdid_width; +constant cr0_eq_offset : natural := esr_st_offset + thdid_width; +constant cr0_eq_valid_offset : natural := cr0_eq_offset + thdid_width; +constant tlb_multihit_err_offset : natural := cr0_eq_valid_offset + thdid_width; +constant tag4_parerr_offset : natural := tlb_multihit_err_offset + thdid_width; +constant tlb_par_err_offset : natural := tag4_parerr_offset + 5; +constant lru_par_err_offset : natural := tlb_par_err_offset + thdid_width; +constant cswitch_offset : natural := lru_par_err_offset + thdid_width; +constant spare_c_offset : natural := cswitch_offset + 8; +constant scan_right_2 : natural := spare_c_offset + 16 - 1; +constant tagpos_epn : natural := 0; +constant tagpos_pid : natural := 52; +constant tagpos_is : natural := 66; +constant tagpos_class : natural := 68; +constant tagpos_state : natural := 70; +constant tagpos_thdid : natural := 74; +constant tagpos_size : natural := 78; +constant tagpos_type : natural := 82; +constant tagpos_lpid : natural := 90; +constant tagpos_ind : natural := 98; +constant tagpos_atsel : natural := 99; +constant tagpos_esel : natural := 100; +constant tagpos_hes : natural := 103; +constant tagpos_wq : natural := 104; +constant tagpos_lrat : natural := 106; +constant tagpos_pt : natural := 107; +constant tagpos_recform : natural := 108; +constant tagpos_endflag : natural := 109; +constant tagpos_type_derat : natural := tagpos_type; +constant tagpos_type_ierat : natural := tagpos_type+1; +constant tagpos_type_tlbsx : natural := tagpos_type+2; +constant tagpos_type_tlbsrx : natural := tagpos_type+3; +constant tagpos_type_snoop : natural := tagpos_type+4; +constant tagpos_type_tlbre : natural := tagpos_type+5; +constant tagpos_type_tlbwe : natural := tagpos_type+6; +constant tagpos_type_ptereload : natural := tagpos_type+7; +constant tagpos_pr : natural := tagpos_state; +constant tagpos_gs : natural := tagpos_state+1; +constant tagpos_as : natural := tagpos_state+2; +constant tagpos_cm : natural := tagpos_state+3; +constant waypos_epn : natural := 0; +constant waypos_size : natural := 52; +constant waypos_thdid : natural := 56; +constant waypos_class : natural := 60; +constant waypos_extclass : natural := 62; +constant waypos_lpid : natural := 66; +constant waypos_xbit : natural := 84; +constant waypos_rpn : natural := 88; +constant waypos_rc : natural := 118; +constant waypos_wlc : natural := 120; +constant waypos_resvattr : natural := 122; +constant waypos_vf : natural := 123; +constant waypos_ind : natural := 124; +constant waypos_ubits : natural := 125; +constant waypos_wimge : natural := 129; +constant waypos_usxwr : natural := 134; +constant waypos_gs : natural := 140; +constant waypos_ts : natural := 141; +constant waypos_tid : natural := 144; +constant eratpos_epn : natural := 0; +constant eratpos_x : natural := 52; +constant eratpos_size : natural := 53; +constant eratpos_v : natural := 56; +constant eratpos_thdid : natural := 57; +constant eratpos_class : natural := 61; +constant eratpos_extclass : natural := 63; +constant eratpos_wren : natural := 65; +constant eratpos_rpnrsvd : natural := 66; +constant eratpos_rpn : natural := 70; +constant eratpos_r : natural := 100; +constant eratpos_c : natural := 101; +constant eratpos_relsoon : natural := 102; +constant eratpos_wlc : natural := 103; +constant eratpos_resvattr : natural := 105; +constant eratpos_vf : natural := 106; +constant eratpos_ubits : natural := 107; +constant eratpos_wimge : natural := 111; +constant eratpos_usxwr : natural := 116; +constant eratpos_gs : natural := 122; +constant eratpos_ts : natural := 123; +constant eratpos_tid : natural := 124; +constant ptepos_rpn : natural := 0; +constant ptepos_wimge : natural := 40; +constant ptepos_r : natural := 45; +constant ptepos_ubits : natural := 46; +constant ptepos_sw0 : natural := 50; +constant ptepos_c : natural := 51; +constant ptepos_size : natural := 52; +constant ptepos_usxwr : natural := 56; +constant ptepos_sw1 : natural := 62; +constant ptepos_valid : natural := 63; +constant pos_tlb_pei : natural := 10; +constant pos_lru_pei : natural := 11; +constant pos_ictid : natural := 12; +constant pos_ittid : natural := 13; +constant pos_dctid : natural := 14; +constant pos_dttid : natural := 15; +constant pos_dccd : natural := 16; +constant pos_tlbwe_binv : natural := 17; +constant pos_tlbi_msb : natural := 18; +constant pos_tlbi_rej : natural := 19; +signal tlb_way0_d, tlb_way0_q : std_ulogic_vector(0 to tlb_way_width-1); +signal tlb_way1_d, tlb_way1_q : std_ulogic_vector(0 to tlb_way_width-1); +signal tlb_way2_d, tlb_way2_q : std_ulogic_vector(0 to tlb_way_width-1); +signal tlb_way3_d, tlb_way3_q : std_ulogic_vector(0 to tlb_way_width-1); +signal tlb_tag3_d, tlb_tag3_q : std_ulogic_vector(0 to tlb_tag_width-1); +signal tlb_tag3_clone1_d, tlb_tag3_clone1_q : std_ulogic_vector(0 to tlb_tag_width-1); +signal tlb_tag3_clone2_d, tlb_tag3_clone2_q : std_ulogic_vector(0 to tlb_tag_width-1); +signal tlb_addr3_d, tlb_addr3_q : std_ulogic_vector(0 to tlb_addr_width-1); +signal lru_tag3_dataout_d, lru_tag3_dataout_q : std_ulogic_vector(0 to 15); +signal tlb_tag3_cmpmask_d, tlb_tag3_cmpmask_q : std_ulogic_vector(0 to 4); +signal tlb_tag3_cmpmask_clone_d, tlb_tag3_cmpmask_clone_q : std_ulogic_vector(0 to 4); +signal tlb_way0_cmpmask_d, tlb_way0_cmpmask_q : std_ulogic_vector(0 to 4); +signal tlb_way1_cmpmask_d, tlb_way1_cmpmask_q : std_ulogic_vector(0 to 4); +signal tlb_way2_cmpmask_d, tlb_way2_cmpmask_q : std_ulogic_vector(0 to 4); +signal tlb_way3_cmpmask_d, tlb_way3_cmpmask_q : std_ulogic_vector(0 to 4); +signal tlb_way0_xbitmask_d, tlb_way0_xbitmask_q : std_ulogic_vector(0 to 4); +signal tlb_way1_xbitmask_d, tlb_way1_xbitmask_q : std_ulogic_vector(0 to 4); +signal tlb_way2_xbitmask_d, tlb_way2_xbitmask_q : std_ulogic_vector(0 to 4); +signal tlb_way3_xbitmask_d, tlb_way3_xbitmask_q : std_ulogic_vector(0 to 4); +signal tlb_tag4_d, tlb_tag4_q : std_ulogic_vector(0 to tlb_tag_width-1); +signal tlb_tag4_wayhit_d, tlb_tag4_wayhit_q : std_ulogic_vector(0 to tlb_ways); +signal tlb_addr4_d, tlb_addr4_q : std_ulogic_vector(0 to tlb_addr_width-1); +signal tlb_dataina_d, tlb_dataina_q : std_ulogic_vector(0 to tlb_way_width-1); +signal tlb_datainb_d, tlb_datainb_q : std_ulogic_vector(0 to tlb_way_width-1); +signal lru_tag4_dataout_d, lru_tag4_dataout_q : std_ulogic_vector(0 to lru_width-1); +signal tlb_tag4_way_d, tlb_tag4_way_q : std_ulogic_vector(0 to tlb_way_width-1); +signal tlb_tag4_way_clone_d, tlb_tag4_way_clone_q : std_ulogic_vector(0 to tlb_way_width-1); +signal tlb_tag4_way_rw_d, tlb_tag4_way_rw_q : std_ulogic_vector(0 to tlb_way_width-1); +signal tlb_tag4_way_rw_clone_d, tlb_tag4_way_rw_clone_q : std_ulogic_vector(0 to tlb_way_width-1); +signal tlb_tag4_way_rw_or : std_ulogic_vector(0 to tlb_way_width-1); +signal tlbwe_tag4_back_inv_d, tlbwe_tag4_back_inv_q : std_ulogic_vector(0 to thdid_width); +signal tlbwe_tag4_back_inv_attr_d, tlbwe_tag4_back_inv_attr_q : std_ulogic_vector(18 to 19); +signal tlb_erat_val_d, tlb_erat_val_q : std_ulogic_vector(0 to 2*thdid_width+1); +signal tlb_erat_rel_d, tlb_erat_rel_q : std_ulogic_vector(0 to erat_rel_data_width-1); +signal tlb_erat_rel_clone_d, tlb_erat_rel_clone_q : std_ulogic_vector(0 to erat_rel_data_width-1); +signal tlb_erat_dup_d, tlb_erat_dup_q : std_ulogic_vector(0 to 2*thdid_width+11); +signal lru_write_d, lru_write_q : std_ulogic_vector(0 to 15); +signal lru_wr_addr_d, lru_wr_addr_q : std_ulogic_vector(0 to tlb_addr_width-1); +signal lru_datain_d, lru_datain_q : std_ulogic_vector(0 to 15); +signal eratmiss_done_d, eratmiss_done_q : std_ulogic_vector(0 to thdid_width-1); +signal tlb_miss_d, tlb_miss_q : std_ulogic_vector(0 to thdid_width-1); +signal tlb_inelig_d, tlb_inelig_q : std_ulogic_vector(0 to thdid_width-1); +signal lrat_miss_d, lrat_miss_q : std_ulogic_vector(0 to thdid_width-1); +signal pt_fault_d, pt_fault_q : std_ulogic_vector(0 to thdid_width-1); +signal hv_priv_d, hv_priv_q : std_ulogic_vector(0 to thdid_width-1); +signal tlb_tag5_except_d, tlb_tag5_except_q : std_ulogic_vector(0 to thdid_width-1); +signal tlb_dsi_d, tlb_dsi_q : std_ulogic_vector(0 to thdid_width-1); +signal tlb_isi_d, tlb_isi_q : std_ulogic_vector(0 to thdid_width-1); +signal esr_pt_d, esr_pt_q : std_ulogic_vector(0 to thdid_width-1); +signal esr_data_d, esr_data_q : std_ulogic_vector(0 to thdid_width-1); +signal esr_epid_d, esr_epid_q : std_ulogic_vector(0 to thdid_width-1); +signal esr_st_d, esr_st_q : std_ulogic_vector(0 to thdid_width-1); +signal tlb_multihit_err_d, tlb_multihit_err_q : std_ulogic_vector(0 to thdid_width-1); +signal tag4_parerr_d, tag4_parerr_q : std_ulogic_vector(0 to 4); +signal tlb_par_err_d, tlb_par_err_q : std_ulogic_vector(0 to thdid_width-1); +signal lru_par_err_d, lru_par_err_q : std_ulogic_vector(0 to thdid_width-1); +signal cr0_eq_d, cr0_eq_q : std_ulogic_vector(0 to thdid_width-1); +signal cr0_eq_valid_d, cr0_eq_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal mmucr1_q, mmucr1_clone_q : std_ulogic_vector(10 to 18); +signal epcr_dmiuh_q : std_ulogic_vector(0 to thdid_width-1); +signal msr_gs_q, msr_pr_q : std_ulogic_vector(0 to thdid_width-1); +signal spare_a_q, spare_b_q, spare_c_q : std_ulogic_vector(0 to 15); +signal spare_nsl_q, spare_nsl_clone_q : std_ulogic_vector(0 to 7); +signal cswitch_q : std_ulogic_vector(0 to 7); +signal pgsize_enable,class_enable,thdid_enable,pid_enable,lpid_enable,ind_enable,iprot_enable : std_ulogic; +signal state_enable,extclass_enable : std_ulogic_vector(0 to 1); +signal addr_enable : std_ulogic_vector(0 to 8); +signal comp_iprot : std_ulogic; +signal comp_extclass : std_ulogic_vector(0 to 1); +signal comp_ind : std_ulogic; +signal pgsize_enable_clone,class_enable_clone,thdid_enable_clone,pid_enable_clone,lpid_enable_clone,ind_enable_clone,iprot_enable_clone : std_ulogic; +signal state_enable_clone,extclass_enable_clone : std_ulogic_vector(0 to 1); +signal addr_enable_clone : std_ulogic_vector(0 to 8); +signal comp_iprot_clone : std_ulogic; +signal comp_extclass_clone : std_ulogic_vector(0 to 1); +signal comp_ind_clone : std_ulogic; +-- synopsys translate_off +-- synopsys translate_on +signal tlbwe_tag3_back_inv_enab : std_ulogic; +signal tlb_tag4_way_or : std_ulogic_vector(0 to tlb_way_width-1); +signal tlb_tag4_way_act : std_ulogic; +signal tlb_tag4_way_clone_act : std_ulogic; +signal tlb_tag4_way_rw_act : std_ulogic; +signal tlb_tag4_way_rw_clone_act : std_ulogic; +signal tlb_tag4_type_sig : std_ulogic_vector(0 to 7); +signal tlb_tag4_esel_sig : std_ulogic_vector(0 to 2); +signal tlb_tag4_hes_sig : std_ulogic; +signal tlb_tag4_wq_sig : std_ulogic_vector(0 to 1); +signal tlb_tag4_is_sig : std_ulogic_vector(0 to 3); +signal lru_update_data : std_ulogic_vector(0 to 2); +signal lru_update_data_enab, lru_update_clear_enab : std_ulogic; +signal tlb_tag4_hes1_mas1_v : std_ulogic_vector(0 to thdid_width-1); +signal tlb_tag4_hes0_mas1_v : std_ulogic_vector(0 to thdid_width-1); +signal tlb_tag4_hes1_mas1_iprot : std_ulogic_vector(0 to thdid_width-1); +signal tlb_tag4_hes0_mas1_iprot : std_ulogic_vector(0 to thdid_width-1); +signal tlb_tag4_ptereload_v : std_ulogic_vector(0 to thdid_width-1); +signal tlb_tag4_ptereload_iprot : std_ulogic_vector(0 to thdid_width-1); +signal tlb_tag4_ptereload_sig : std_ulogic; +signal tlb_tag4_erat_data_cap : std_ulogic; +signal tlb_wayhit : std_ulogic_vector(0 to tlb_ways-1); +signal multihit : std_ulogic; +signal erat_pgsize : std_ulogic_vector(0 to 2); +signal tlb_tag4_size_not_supp : std_ulogic; +signal tlb_tag4_hv_op : std_ulogic; +signal tlb_tag4_epcr_dgtmi : std_ulogic; +signal tlb_way0_addr_match : std_ulogic; +signal tlb_way0_pgsize_match : std_ulogic; +signal tlb_way0_class_match : std_ulogic; +signal tlb_way0_extclass_match : std_ulogic; +signal tlb_way0_state_match : std_ulogic; +signal tlb_way0_thdid_match : std_ulogic; +signal tlb_way0_pid_match : std_ulogic; +signal tlb_way0_lpid_match : std_ulogic; +signal tlb_way0_ind_match : std_ulogic; +signal tlb_way0_iprot_match : std_ulogic; +signal tlb_way1_addr_match : std_ulogic; +signal tlb_way1_pgsize_match : std_ulogic; +signal tlb_way1_class_match : std_ulogic; +signal tlb_way1_extclass_match : std_ulogic; +signal tlb_way1_state_match : std_ulogic; +signal tlb_way1_thdid_match : std_ulogic; +signal tlb_way1_pid_match : std_ulogic; +signal tlb_way1_lpid_match : std_ulogic; +signal tlb_way1_ind_match : std_ulogic; +signal tlb_way1_iprot_match : std_ulogic; +signal tlb_way2_addr_match : std_ulogic; +signal tlb_way2_pgsize_match : std_ulogic; +signal tlb_way2_class_match : std_ulogic; +signal tlb_way2_extclass_match : std_ulogic; +signal tlb_way2_state_match : std_ulogic; +signal tlb_way2_thdid_match : std_ulogic; +signal tlb_way2_pid_match : std_ulogic; +signal tlb_way2_lpid_match : std_ulogic; +signal tlb_way2_ind_match : std_ulogic; +signal tlb_way2_iprot_match : std_ulogic; +signal tlb_way3_addr_match : std_ulogic; +signal tlb_way3_pgsize_match : std_ulogic; +signal tlb_way3_class_match : std_ulogic; +signal tlb_way3_extclass_match : std_ulogic; +signal tlb_way3_state_match : std_ulogic; +signal tlb_way3_thdid_match : std_ulogic; +signal tlb_way3_pid_match : std_ulogic; +signal tlb_way3_lpid_match : std_ulogic; +signal tlb_way3_ind_match : std_ulogic; +signal tlb_way3_iprot_match : std_ulogic; +-- synopsys translate_off +-- synopsys translate_on +signal ierat_req0_tag4_pid_match : std_ulogic; +signal ierat_req0_tag4_as_match : std_ulogic; +signal ierat_req0_tag4_gs_match : std_ulogic; +signal ierat_req0_tag4_epn_match : std_ulogic; +signal ierat_req0_tag4_thdid_match : std_ulogic; +signal ierat_req1_tag4_pid_match : std_ulogic; +signal ierat_req1_tag4_as_match : std_ulogic; +signal ierat_req1_tag4_gs_match : std_ulogic; +signal ierat_req1_tag4_epn_match : std_ulogic; +signal ierat_req1_tag4_thdid_match : std_ulogic; +signal ierat_req2_tag4_pid_match : std_ulogic; +signal ierat_req2_tag4_as_match : std_ulogic; +signal ierat_req2_tag4_gs_match : std_ulogic; +signal ierat_req2_tag4_epn_match : std_ulogic; +signal ierat_req2_tag4_thdid_match : std_ulogic; +signal ierat_req3_tag4_pid_match : std_ulogic; +signal ierat_req3_tag4_as_match : std_ulogic; +signal ierat_req3_tag4_gs_match : std_ulogic; +signal ierat_req3_tag4_epn_match : std_ulogic; +signal ierat_req3_tag4_thdid_match : std_ulogic; +signal ierat_iu4_tag4_lpid_match : std_ulogic; +signal ierat_iu4_tag4_pid_match : std_ulogic; +signal ierat_iu4_tag4_as_match : std_ulogic; +signal ierat_iu4_tag4_gs_match : std_ulogic; +signal ierat_iu4_tag4_epn_match : std_ulogic; +signal ierat_iu4_tag4_thdid_match : std_ulogic; +signal derat_req0_tag4_lpid_match : std_ulogic; +signal derat_req0_tag4_pid_match : std_ulogic; +signal derat_req0_tag4_as_match : std_ulogic; +signal derat_req0_tag4_gs_match : std_ulogic; +signal derat_req0_tag4_epn_match : std_ulogic; +signal derat_req0_tag4_thdid_match : std_ulogic; +signal derat_req1_tag4_lpid_match : std_ulogic; +signal derat_req1_tag4_pid_match : std_ulogic; +signal derat_req1_tag4_as_match : std_ulogic; +signal derat_req1_tag4_gs_match : std_ulogic; +signal derat_req1_tag4_epn_match : std_ulogic; +signal derat_req1_tag4_thdid_match : std_ulogic; +signal derat_req2_tag4_lpid_match : std_ulogic; +signal derat_req2_tag4_pid_match : std_ulogic; +signal derat_req2_tag4_as_match : std_ulogic; +signal derat_req2_tag4_gs_match : std_ulogic; +signal derat_req2_tag4_epn_match : std_ulogic; +signal derat_req2_tag4_thdid_match : std_ulogic; +signal derat_req3_tag4_lpid_match : std_ulogic; +signal derat_req3_tag4_pid_match : std_ulogic; +signal derat_req3_tag4_as_match : std_ulogic; +signal derat_req3_tag4_gs_match : std_ulogic; +signal derat_req3_tag4_epn_match : std_ulogic; +signal derat_req3_tag4_thdid_match : std_ulogic; +signal derat_ex5_tag4_lpid_match : std_ulogic; +signal derat_ex5_tag4_pid_match : std_ulogic; +signal derat_ex5_tag4_as_match : std_ulogic; +signal derat_ex5_tag4_gs_match : std_ulogic; +signal derat_ex5_tag4_epn_match : std_ulogic; +signal derat_ex5_tag4_thdid_match : std_ulogic; +signal ierat_tag4_dup_thdid : std_ulogic_vector(0 to thdid_width-1); +signal derat_tag4_dup_thdid : std_ulogic_vector(0 to thdid_width-1); +signal tlb_way0_lo_calc_par : std_ulogic_vector(0 to 9); +signal tlb_way0_hi_calc_par : std_ulogic_vector(0 to 9); +signal tlb_way0_parerr : std_ulogic; +signal tlb_way1_lo_calc_par : std_ulogic_vector(0 to 9); +signal tlb_way1_hi_calc_par : std_ulogic_vector(0 to 9); +signal tlb_way1_parerr : std_ulogic; +signal tlb_way2_lo_calc_par : std_ulogic_vector(0 to 9); +signal tlb_way2_hi_calc_par : std_ulogic_vector(0 to 9); +signal tlb_way2_parerr : std_ulogic; +signal tlb_way3_lo_calc_par : std_ulogic_vector(0 to 9); +signal tlb_way3_hi_calc_par : std_ulogic_vector(0 to 9); +signal tlb_way3_parerr : std_ulogic; +signal lru_calc_par : std_ulogic_vector(0 to 1); +signal tlb_datain_lo_tlbwe_0_nopar : std_ulogic_vector(0 to tlb_word_width-10-1); +signal tlb_datain_lo_tlbwe_0_par : std_ulogic_vector(0 to 9); +signal tlb_datain_hi_hv_tlbwe_0_nopar : std_ulogic_vector(0 to tlb_word_width-10-1); +signal tlb_datain_hi_gs_tlbwe_0_nopar : std_ulogic_vector(0 to tlb_word_width-10-1); +signal tlb_datain_hi_hv_tlbwe_0_par : std_ulogic_vector(0 to 9); +signal tlb_datain_hi_gs_tlbwe_0_par : std_ulogic_vector(0 to 9); +signal tlb_datain_lo_tlbwe_1_nopar : std_ulogic_vector(0 to tlb_word_width-10-1); +signal tlb_datain_lo_tlbwe_1_par : std_ulogic_vector(0 to 9); +signal tlb_datain_hi_hv_tlbwe_1_nopar : std_ulogic_vector(0 to tlb_word_width-10-1); +signal tlb_datain_hi_gs_tlbwe_1_nopar : std_ulogic_vector(0 to tlb_word_width-10-1); +signal tlb_datain_hi_hv_tlbwe_1_par : std_ulogic_vector(0 to 9); +signal tlb_datain_hi_gs_tlbwe_1_par : std_ulogic_vector(0 to 9); +signal tlb_datain_lo_tlbwe_2_nopar : std_ulogic_vector(0 to tlb_word_width-10-1); +signal tlb_datain_lo_tlbwe_2_par : std_ulogic_vector(0 to 9); +signal tlb_datain_hi_hv_tlbwe_2_nopar : std_ulogic_vector(0 to tlb_word_width-10-1); +signal tlb_datain_hi_gs_tlbwe_2_nopar : std_ulogic_vector(0 to tlb_word_width-10-1); +signal tlb_datain_hi_hv_tlbwe_2_par : std_ulogic_vector(0 to 9); +signal tlb_datain_hi_gs_tlbwe_2_par : std_ulogic_vector(0 to 9); +signal tlb_datain_lo_tlbwe_3_nopar : std_ulogic_vector(0 to tlb_word_width-10-1); +signal tlb_datain_lo_tlbwe_3_par : std_ulogic_vector(0 to 9); +signal tlb_datain_hi_hv_tlbwe_3_nopar : std_ulogic_vector(0 to tlb_word_width-10-1); +signal tlb_datain_hi_gs_tlbwe_3_nopar : std_ulogic_vector(0 to tlb_word_width-10-1); +signal tlb_datain_hi_hv_tlbwe_3_par : std_ulogic_vector(0 to 9); +signal tlb_datain_hi_gs_tlbwe_3_par : std_ulogic_vector(0 to 9); +signal tlb_datain_lo_ptereload_nopar : std_ulogic_vector(0 to tlb_word_width-10-1); +signal tlb_datain_lo_ptereload_par : std_ulogic_vector(0 to 9); +signal tlb_datain_hi_hv_ptereload_nopar : std_ulogic_vector(0 to tlb_word_width-10-1); +signal tlb_datain_hi_gs_ptereload_nopar : std_ulogic_vector(0 to tlb_word_width-10-1); +signal tlb_datain_hi_hv_ptereload_par : std_ulogic_vector(0 to 9); +signal tlb_datain_hi_gs_ptereload_par : std_ulogic_vector(0 to 9); +signal ptereload_req_derived_usxwr : std_ulogic_vector(0 to 5); +signal lrat_tag3_lpn_sig : std_ulogic_vector(22 to 51); +signal lrat_tag3_rpn_sig : std_ulogic_vector(22 to 51); +signal lrat_tag4_lpn_sig : std_ulogic_vector(22 to 51); +signal lrat_tag4_rpn_sig : std_ulogic_vector(22 to 51); +-- synopsys translate_off +-- synopsys translate_on +signal lru_datain_alt_d : std_ulogic_vector(4 to 9); +signal lru_update_data_alt : std_ulogic_vector(0 to 2); +signal tlb_tag4_parerr_enab : std_ulogic; +signal tlb_tag4_tlbre_parerr : std_ulogic; +signal lru_update_data_snoophit_eco : std_ulogic_vector(0 to 2); +signal lru_update_data_erathit_eco : std_ulogic_vector(0 to 2); +-- synopsys translate_off +-- synopsys translate_on +signal unused_dc : std_ulogic_vector(0 to 38); +-- synopsys translate_off +-- synopsys translate_on +signal ECO107332_orred_tag4_thdid_flushed : std_ulogic; +signal ECO107332_tlb_par_err_d : std_ulogic_vector(0 to thdid_width-1); +signal ECO107332_lru_par_err_d : std_ulogic_vector(0 to thdid_width-1); +signal pc_sg_1 : std_ulogic; +signal pc_sg_0 : std_ulogic; +signal pc_fce_1 : std_ulogic; +signal pc_fce_0 : std_ulogic; +signal pc_func_sl_thold_1 : std_ulogic; +signal pc_func_sl_thold_0 : std_ulogic; +signal pc_func_sl_thold_0_b : std_ulogic; +signal pc_func_slp_sl_thold_1 : std_ulogic; +signal pc_func_slp_sl_thold_0 : std_ulogic; +signal pc_func_slp_sl_thold_0_b : std_ulogic; +signal pc_func_sl_force : std_ulogic; +signal pc_func_slp_sl_force : std_ulogic; +signal pc_func_slp_nsl_thold_1 : std_ulogic; +signal pc_func_slp_nsl_thold_0 : std_ulogic; +signal pc_func_slp_nsl_thold_0_b : std_ulogic_vector(0 to 1); +signal pc_func_slp_nsl_force : std_ulogic_vector(0 to 1); +signal siv_0, sov_0 : std_ulogic_vector(0 to scan_right_0); +signal siv_1, sov_1 : std_ulogic_vector(0 to scan_right_1); +signal siv_2, sov_2 : std_ulogic_vector(0 to scan_right_2); +signal tidn : std_ulogic; +signal tiup : std_ulogic; + BEGIN + +tidn <= '0'; +tiup <= '1'; +tlb_addr3_d <= tlb_addr2; +tlb_way0_d <= tlb_dataout(0 to tlb_way_width-1); +tlb_way1_d <= tlb_dataout(tlb_way_width to 2*tlb_way_width-1); +tlb_way2_d <= tlb_dataout(2*tlb_way_width to 3*tlb_way_width-1); +tlb_way3_d <= tlb_dataout(3*tlb_way_width to 4*tlb_way_width-1); +tlb_tag3_d(0 TO tagpos_thdid-1) <= tlb_tag2(0 to tagpos_thdid-1); +tlb_tag3_d(tagpos_thdid TO tagpos_thdid+thdid_width-1) <= + (others => '0') when ((tlb_tag4_wayhit_q(tlb_ways)='1' or tlb_tag4_q(tagpos_endflag)='1' or or_reduce(tag4_parerr_q(0 to 4))='1') and + tlb_tag4_q(tagpos_type_ptereload)='0' and + (tlb_tag4_q(tagpos_type_ierat)='1' or tlb_tag4_q(tagpos_type_derat)='1')) + else (others => '0') when ((tlb_tag4_wayhit_q(tlb_ways)='1' or tlb_tag4_q(tagpos_endflag)='1' or or_reduce(tag4_parerr_q(0 to 4))='1') and + (tlb_tag4_q(tagpos_type_tlbsx)='1' or tlb_tag4_q(tagpos_type_tlbsrx)='1')) + else (others => '0') when (tlb_tag4_q(tagpos_endflag)='1' and tlb_tag4_q(tagpos_type_snoop)='1') + else (others => '0') when ((tlb_tag4_q(tagpos_type_tlbre)='1' or tlb_tag4_q(tagpos_type_tlbwe)='1' or tlb_tag4_q(tagpos_type_ptereload)='1' ) and + tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000") + else tlb_tag2(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag2_flush); +tlb_tag3_d(tagpos_thdid+thdid_width TO tlb_tag_width-1) <= tlb_tag2(tagpos_thdid+thdid_width to tlb_tag_width-1); +tlb_tag3_clone1_d(0 TO tagpos_thdid-1) <= tlb_tag2(0 to tagpos_thdid-1); +tlb_tag3_clone1_d(tagpos_thdid TO tagpos_thdid+thdid_width-1) <= + (others => '0') when ((tlb_tag4_wayhit_q(tlb_ways)='1' or tlb_tag4_q(tagpos_endflag)='1' or or_reduce(tag4_parerr_q(0 to 4))='1') and + tlb_tag4_q(tagpos_type_ptereload)='0' and + (tlb_tag4_q(tagpos_type_ierat)='1' or tlb_tag4_q(tagpos_type_derat)='1')) + else (others => '0') when ((tlb_tag4_wayhit_q(tlb_ways)='1' or tlb_tag4_q(tagpos_endflag)='1' or or_reduce(tag4_parerr_q(0 to 4))='1') and + (tlb_tag4_q(tagpos_type_tlbsx)='1' or tlb_tag4_q(tagpos_type_tlbsrx)='1')) + else (others => '0') when (tlb_tag4_q(tagpos_endflag)='1' and tlb_tag4_q(tagpos_type_snoop)='1') + else (others => '0') when ((tlb_tag4_q(tagpos_type_tlbre)='1' or tlb_tag4_q(tagpos_type_tlbwe)='1' or tlb_tag4_q(tagpos_type_ptereload)='1' ) and + tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000") + else tlb_tag2(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag2_flush); +tlb_tag3_clone1_d(tagpos_thdid+thdid_width TO tlb_tag_width-1) <= tlb_tag2(tagpos_thdid+thdid_width to tlb_tag_width-1); +tlb_tag3_clone2_d(0 TO tagpos_thdid-1) <= tlb_tag2(0 to tagpos_thdid-1); +tlb_tag3_clone2_d(tagpos_thdid TO tagpos_thdid+thdid_width-1) <= + (others => '0') when ((tlb_tag4_wayhit_q(tlb_ways)='1' or tlb_tag4_q(tagpos_endflag)='1' or or_reduce(tag4_parerr_q(0 to 4))='1') and + tlb_tag4_q(tagpos_type_ptereload)='0' and + (tlb_tag4_q(tagpos_type_ierat)='1' or tlb_tag4_q(tagpos_type_derat)='1')) + else (others => '0') when ((tlb_tag4_wayhit_q(tlb_ways)='1' or tlb_tag4_q(tagpos_endflag)='1' or or_reduce(tag4_parerr_q(0 to 4))='1') and + (tlb_tag4_q(tagpos_type_tlbsx)='1' or tlb_tag4_q(tagpos_type_tlbsrx)='1')) + else (others => '0') when (tlb_tag4_q(tagpos_endflag)='1' and tlb_tag4_q(tagpos_type_snoop)='1') + else (others => '0') when ((tlb_tag4_q(tagpos_type_tlbre)='1' or tlb_tag4_q(tagpos_type_tlbwe)='1' or tlb_tag4_q(tagpos_type_ptereload)='1' ) and + tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000") + else tlb_tag2(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag2_flush); +tlb_tag3_clone2_d(tagpos_thdid+thdid_width TO tlb_tag_width-1) <= tlb_tag2(tagpos_thdid+thdid_width to tlb_tag_width-1); +tlb_tag3_cmpmask_d(0) <= Eq(tlb_tag2(tagpos_size to tagpos_size+3), TLB_PgSize_1GB); +tlb_tag3_cmpmask_d(1) <= Eq(tlb_tag2(tagpos_size to tagpos_size+3), TLB_PgSize_1GB) or + Eq(tlb_tag2(tagpos_size to tagpos_size+3), TLB_PgSize_256MB); +tlb_tag3_cmpmask_d(2) <= Eq(tlb_tag2(tagpos_size to tagpos_size+3), TLB_PgSize_1GB) or + Eq(tlb_tag2(tagpos_size to tagpos_size+3), TLB_PgSize_256MB) or + Eq(tlb_tag2(tagpos_size to tagpos_size+3), TLB_PgSize_16MB); +tlb_tag3_cmpmask_d(3) <= Eq(tlb_tag2(tagpos_size to tagpos_size+3), TLB_PgSize_1GB) or + Eq(tlb_tag2(tagpos_size to tagpos_size+3), TLB_PgSize_256MB) or + Eq(tlb_tag2(tagpos_size to tagpos_size+3), TLB_PgSize_16MB) or + Eq(tlb_tag2(tagpos_size to tagpos_size+3), TLB_PgSize_1MB); +tlb_tag3_cmpmask_d(4) <= Eq(tlb_tag2(tagpos_size to tagpos_size+3), TLB_PgSize_1GB) or + Eq(tlb_tag2(tagpos_size to tagpos_size+3), TLB_PgSize_256MB) or + Eq(tlb_tag2(tagpos_size to tagpos_size+3), TLB_PgSize_16MB) or + Eq(tlb_tag2(tagpos_size to tagpos_size+3), TLB_PgSize_1MB) or + Eq(tlb_tag2(tagpos_size to tagpos_size+3), TLB_PgSize_64KB); +tlb_tag3_cmpmask_clone_d(0) <= Eq(tlb_tag2(tagpos_size to tagpos_size+3), TLB_PgSize_1GB); +tlb_tag3_cmpmask_clone_d(1) <= Eq(tlb_tag2(tagpos_size to tagpos_size+3), TLB_PgSize_1GB) or + Eq(tlb_tag2(tagpos_size to tagpos_size+3), TLB_PgSize_256MB); +tlb_tag3_cmpmask_clone_d(2) <= Eq(tlb_tag2(tagpos_size to tagpos_size+3), TLB_PgSize_1GB) or + Eq(tlb_tag2(tagpos_size to tagpos_size+3), TLB_PgSize_256MB) or + Eq(tlb_tag2(tagpos_size to tagpos_size+3), TLB_PgSize_16MB); +tlb_tag3_cmpmask_clone_d(3) <= Eq(tlb_tag2(tagpos_size to tagpos_size+3), TLB_PgSize_1GB) or + Eq(tlb_tag2(tagpos_size to tagpos_size+3), TLB_PgSize_256MB) or + Eq(tlb_tag2(tagpos_size to tagpos_size+3), TLB_PgSize_16MB) or + Eq(tlb_tag2(tagpos_size to tagpos_size+3), TLB_PgSize_1MB); +tlb_tag3_cmpmask_clone_d(4) <= Eq(tlb_tag2(tagpos_size to tagpos_size+3), TLB_PgSize_1GB) or + Eq(tlb_tag2(tagpos_size to tagpos_size+3), TLB_PgSize_256MB) or + Eq(tlb_tag2(tagpos_size to tagpos_size+3), TLB_PgSize_16MB) or + Eq(tlb_tag2(tagpos_size to tagpos_size+3), TLB_PgSize_1MB) or + Eq(tlb_tag2(tagpos_size to tagpos_size+3), TLB_PgSize_64KB); +tlb_way0_cmpmask_d(0) <= Eq(tlb_dataout(0*tlb_way_width+waypos_size to 0*tlb_way_width+waypos_size+3), TLB_PgSize_1GB); +tlb_way0_cmpmask_d(1) <= Eq(tlb_dataout(0*tlb_way_width+waypos_size to 0*tlb_way_width+waypos_size+3), TLB_PgSize_1GB) or + Eq(tlb_dataout(0*tlb_way_width+waypos_size to 0*tlb_way_width+waypos_size+3), TLB_PgSize_256MB); +tlb_way0_cmpmask_d(2) <= Eq(tlb_dataout(0*tlb_way_width+waypos_size to 0*tlb_way_width+waypos_size+3), TLB_PgSize_1GB) or + Eq(tlb_dataout(0*tlb_way_width+waypos_size to 0*tlb_way_width+waypos_size+3), TLB_PgSize_256MB) or + Eq(tlb_dataout(0*tlb_way_width+waypos_size to 0*tlb_way_width+waypos_size+3), TLB_PgSize_16MB); +tlb_way0_cmpmask_d(3) <= Eq(tlb_dataout(0*tlb_way_width+waypos_size to 0*tlb_way_width+waypos_size+3), TLB_PgSize_1GB) or + Eq(tlb_dataout(0*tlb_way_width+waypos_size to 0*tlb_way_width+waypos_size+3), TLB_PgSize_256MB) or + Eq(tlb_dataout(0*tlb_way_width+waypos_size to 0*tlb_way_width+waypos_size+3), TLB_PgSize_16MB) or + Eq(tlb_dataout(0*tlb_way_width+waypos_size to 0*tlb_way_width+waypos_size+3), TLB_PgSize_1MB); +tlb_way0_cmpmask_d(4) <= Eq(tlb_dataout(0*tlb_way_width+waypos_size to 0*tlb_way_width+waypos_size+3), TLB_PgSize_1GB) or + Eq(tlb_dataout(0*tlb_way_width+waypos_size to 0*tlb_way_width+waypos_size+3), TLB_PgSize_256MB) or + Eq(tlb_dataout(0*tlb_way_width+waypos_size to 0*tlb_way_width+waypos_size+3), TLB_PgSize_16MB) or + Eq(tlb_dataout(0*tlb_way_width+waypos_size to 0*tlb_way_width+waypos_size+3), TLB_PgSize_1MB) or + Eq(tlb_dataout(0*tlb_way_width+waypos_size to 0*tlb_way_width+waypos_size+3), TLB_PgSize_64KB); +tlb_way0_xbitmask_d(0) <= Eq(tlb_dataout(0*tlb_way_width+waypos_size to 0*tlb_way_width+waypos_size+3), TLB_PgSize_1GB); +tlb_way0_xbitmask_d(1) <= Eq(tlb_dataout(0*tlb_way_width+waypos_size to 0*tlb_way_width+waypos_size+3), TLB_PgSize_256MB); +tlb_way0_xbitmask_d(2) <= Eq(tlb_dataout(0*tlb_way_width+waypos_size to 0*tlb_way_width+waypos_size+3), TLB_PgSize_16MB); +tlb_way0_xbitmask_d(3) <= Eq(tlb_dataout(0*tlb_way_width+waypos_size to 0*tlb_way_width+waypos_size+3), TLB_PgSize_1MB); +tlb_way0_xbitmask_d(4) <= Eq(tlb_dataout(0*tlb_way_width+waypos_size to 0*tlb_way_width+waypos_size+3), TLB_PgSize_64KB); +tlb_way1_cmpmask_d(0) <= Eq(tlb_dataout(1*tlb_way_width+waypos_size to 1*tlb_way_width+waypos_size+3), TLB_PgSize_1GB); +tlb_way1_cmpmask_d(1) <= Eq(tlb_dataout(1*tlb_way_width+waypos_size to 1*tlb_way_width+waypos_size+3), TLB_PgSize_1GB) or + Eq(tlb_dataout(1*tlb_way_width+waypos_size to 1*tlb_way_width+waypos_size+3), TLB_PgSize_256MB); +tlb_way1_cmpmask_d(2) <= Eq(tlb_dataout(1*tlb_way_width+waypos_size to 1*tlb_way_width+waypos_size+3), TLB_PgSize_1GB) or + Eq(tlb_dataout(1*tlb_way_width+waypos_size to 1*tlb_way_width+waypos_size+3), TLB_PgSize_256MB) or + Eq(tlb_dataout(1*tlb_way_width+waypos_size to 1*tlb_way_width+waypos_size+3), TLB_PgSize_16MB); +tlb_way1_cmpmask_d(3) <= Eq(tlb_dataout(1*tlb_way_width+waypos_size to 1*tlb_way_width+waypos_size+3), TLB_PgSize_1GB) or + Eq(tlb_dataout(1*tlb_way_width+waypos_size to 1*tlb_way_width+waypos_size+3), TLB_PgSize_256MB) or + Eq(tlb_dataout(1*tlb_way_width+waypos_size to 1*tlb_way_width+waypos_size+3), TLB_PgSize_16MB) or + Eq(tlb_dataout(1*tlb_way_width+waypos_size to 1*tlb_way_width+waypos_size+3), TLB_PgSize_1MB); +tlb_way1_cmpmask_d(4) <= Eq(tlb_dataout(1*tlb_way_width+waypos_size to 1*tlb_way_width+waypos_size+3), TLB_PgSize_1GB) or + Eq(tlb_dataout(1*tlb_way_width+waypos_size to 1*tlb_way_width+waypos_size+3), TLB_PgSize_256MB) or + Eq(tlb_dataout(1*tlb_way_width+waypos_size to 1*tlb_way_width+waypos_size+3), TLB_PgSize_16MB) or + Eq(tlb_dataout(1*tlb_way_width+waypos_size to 1*tlb_way_width+waypos_size+3), TLB_PgSize_1MB) or + Eq(tlb_dataout(1*tlb_way_width+waypos_size to 1*tlb_way_width+waypos_size+3), TLB_PgSize_64KB); +tlb_way1_xbitmask_d(0) <= Eq(tlb_dataout(1*tlb_way_width+waypos_size to 1*tlb_way_width+waypos_size+3), TLB_PgSize_1GB); +tlb_way1_xbitmask_d(1) <= Eq(tlb_dataout(1*tlb_way_width+waypos_size to 1*tlb_way_width+waypos_size+3), TLB_PgSize_256MB); +tlb_way1_xbitmask_d(2) <= Eq(tlb_dataout(1*tlb_way_width+waypos_size to 1*tlb_way_width+waypos_size+3), TLB_PgSize_16MB); +tlb_way1_xbitmask_d(3) <= Eq(tlb_dataout(1*tlb_way_width+waypos_size to 1*tlb_way_width+waypos_size+3), TLB_PgSize_1MB); +tlb_way1_xbitmask_d(4) <= Eq(tlb_dataout(1*tlb_way_width+waypos_size to 1*tlb_way_width+waypos_size+3), TLB_PgSize_64KB); +tlb_way2_cmpmask_d(0) <= Eq(tlb_dataout(2*tlb_way_width+waypos_size to 2*tlb_way_width+waypos_size+3), TLB_PgSize_1GB); +tlb_way2_cmpmask_d(1) <= Eq(tlb_dataout(2*tlb_way_width+waypos_size to 2*tlb_way_width+waypos_size+3), TLB_PgSize_1GB) or + Eq(tlb_dataout(2*tlb_way_width+waypos_size to 2*tlb_way_width+waypos_size+3), TLB_PgSize_256MB); +tlb_way2_cmpmask_d(2) <= Eq(tlb_dataout(2*tlb_way_width+waypos_size to 2*tlb_way_width+waypos_size+3), TLB_PgSize_1GB) or + Eq(tlb_dataout(2*tlb_way_width+waypos_size to 2*tlb_way_width+waypos_size+3), TLB_PgSize_256MB) or + Eq(tlb_dataout(2*tlb_way_width+waypos_size to 2*tlb_way_width+waypos_size+3), TLB_PgSize_16MB); +tlb_way2_cmpmask_d(3) <= Eq(tlb_dataout(2*tlb_way_width+waypos_size to 2*tlb_way_width+waypos_size+3), TLB_PgSize_1GB) or + Eq(tlb_dataout(2*tlb_way_width+waypos_size to 2*tlb_way_width+waypos_size+3), TLB_PgSize_256MB) or + Eq(tlb_dataout(2*tlb_way_width+waypos_size to 2*tlb_way_width+waypos_size+3), TLB_PgSize_16MB) or + Eq(tlb_dataout(2*tlb_way_width+waypos_size to 2*tlb_way_width+waypos_size+3), TLB_PgSize_1MB); +tlb_way2_cmpmask_d(4) <= Eq(tlb_dataout(2*tlb_way_width+waypos_size to 2*tlb_way_width+waypos_size+3), TLB_PgSize_1GB) or + Eq(tlb_dataout(2*tlb_way_width+waypos_size to 2*tlb_way_width+waypos_size+3), TLB_PgSize_256MB) or + Eq(tlb_dataout(2*tlb_way_width+waypos_size to 2*tlb_way_width+waypos_size+3), TLB_PgSize_16MB) or + Eq(tlb_dataout(2*tlb_way_width+waypos_size to 2*tlb_way_width+waypos_size+3), TLB_PgSize_1MB) or + Eq(tlb_dataout(2*tlb_way_width+waypos_size to 2*tlb_way_width+waypos_size+3), TLB_PgSize_64KB); +tlb_way2_xbitmask_d(0) <= Eq(tlb_dataout(2*tlb_way_width+waypos_size to 2*tlb_way_width+waypos_size+3), TLB_PgSize_1GB); +tlb_way2_xbitmask_d(1) <= Eq(tlb_dataout(2*tlb_way_width+waypos_size to 2*tlb_way_width+waypos_size+3), TLB_PgSize_256MB); +tlb_way2_xbitmask_d(2) <= Eq(tlb_dataout(2*tlb_way_width+waypos_size to 2*tlb_way_width+waypos_size+3), TLB_PgSize_16MB); +tlb_way2_xbitmask_d(3) <= Eq(tlb_dataout(2*tlb_way_width+waypos_size to 2*tlb_way_width+waypos_size+3), TLB_PgSize_1MB); +tlb_way2_xbitmask_d(4) <= Eq(tlb_dataout(2*tlb_way_width+waypos_size to 2*tlb_way_width+waypos_size+3), TLB_PgSize_64KB); +tlb_way3_cmpmask_d(0) <= Eq(tlb_dataout(3*tlb_way_width+waypos_size to 3*tlb_way_width+waypos_size+3), TLB_PgSize_1GB); +tlb_way3_cmpmask_d(1) <= Eq(tlb_dataout(3*tlb_way_width+waypos_size to 3*tlb_way_width+waypos_size+3), TLB_PgSize_1GB) or + Eq(tlb_dataout(3*tlb_way_width+waypos_size to 3*tlb_way_width+waypos_size+3), TLB_PgSize_256MB); +tlb_way3_cmpmask_d(2) <= Eq(tlb_dataout(3*tlb_way_width+waypos_size to 3*tlb_way_width+waypos_size+3), TLB_PgSize_1GB) or + Eq(tlb_dataout(3*tlb_way_width+waypos_size to 3*tlb_way_width+waypos_size+3), TLB_PgSize_256MB) or + Eq(tlb_dataout(3*tlb_way_width+waypos_size to 3*tlb_way_width+waypos_size+3), TLB_PgSize_16MB); +tlb_way3_cmpmask_d(3) <= Eq(tlb_dataout(3*tlb_way_width+waypos_size to 3*tlb_way_width+waypos_size+3), TLB_PgSize_1GB) or + Eq(tlb_dataout(3*tlb_way_width+waypos_size to 3*tlb_way_width+waypos_size+3), TLB_PgSize_256MB) or + Eq(tlb_dataout(3*tlb_way_width+waypos_size to 3*tlb_way_width+waypos_size+3), TLB_PgSize_16MB) or + Eq(tlb_dataout(3*tlb_way_width+waypos_size to 3*tlb_way_width+waypos_size+3), TLB_PgSize_1MB); +tlb_way3_cmpmask_d(4) <= Eq(tlb_dataout(3*tlb_way_width+waypos_size to 3*tlb_way_width+waypos_size+3), TLB_PgSize_1GB) or + Eq(tlb_dataout(3*tlb_way_width+waypos_size to 3*tlb_way_width+waypos_size+3), TLB_PgSize_256MB) or + Eq(tlb_dataout(3*tlb_way_width+waypos_size to 3*tlb_way_width+waypos_size+3), TLB_PgSize_16MB) or + Eq(tlb_dataout(3*tlb_way_width+waypos_size to 3*tlb_way_width+waypos_size+3), TLB_PgSize_1MB) or + Eq(tlb_dataout(3*tlb_way_width+waypos_size to 3*tlb_way_width+waypos_size+3), TLB_PgSize_64KB); +tlb_way3_xbitmask_d(0) <= Eq(tlb_dataout(3*tlb_way_width+waypos_size to 3*tlb_way_width+waypos_size+3), TLB_PgSize_1GB); +tlb_way3_xbitmask_d(1) <= Eq(tlb_dataout(3*tlb_way_width+waypos_size to 3*tlb_way_width+waypos_size+3), TLB_PgSize_256MB); +tlb_way3_xbitmask_d(2) <= Eq(tlb_dataout(3*tlb_way_width+waypos_size to 3*tlb_way_width+waypos_size+3), TLB_PgSize_16MB); +tlb_way3_xbitmask_d(3) <= Eq(tlb_dataout(3*tlb_way_width+waypos_size to 3*tlb_way_width+waypos_size+3), TLB_PgSize_1MB); +tlb_way3_xbitmask_d(4) <= Eq(tlb_dataout(3*tlb_way_width+waypos_size to 3*tlb_way_width+waypos_size+3), TLB_PgSize_64KB); +tlb_way0_lo_calc_par(0) <= xor_reduce(tlb_way0_q(0 to 7)); +tlb_way0_lo_calc_par(1) <= xor_reduce(tlb_way0_q(8 to 15)); +tlb_way0_lo_calc_par(2) <= xor_reduce(tlb_way0_q(16 to 23)); +tlb_way0_lo_calc_par(3) <= xor_reduce(tlb_way0_q(24 to 31)); +tlb_way0_lo_calc_par(4) <= xor_reduce(tlb_way0_q(32 to 39)); +tlb_way0_lo_calc_par(5) <= xor_reduce(tlb_way0_q(40 to 47)); +tlb_way0_lo_calc_par(6) <= xor_reduce(tlb_way0_q(48 to 51)); +tlb_way0_lo_calc_par(7) <= xor_reduce(tlb_way0_q(52 to 59)); +tlb_way0_lo_calc_par(8) <= xor_reduce(tlb_way0_q(60 to 65)); +tlb_way0_lo_calc_par(9) <= xor_reduce(tlb_way0_q(66 to 73)); +tlb_way1_lo_calc_par(0) <= xor_reduce(tlb_way1_q(0 to 7)); +tlb_way1_lo_calc_par(1) <= xor_reduce(tlb_way1_q(8 to 15)); +tlb_way1_lo_calc_par(2) <= xor_reduce(tlb_way1_q(16 to 23)); +tlb_way1_lo_calc_par(3) <= xor_reduce(tlb_way1_q(24 to 31)); +tlb_way1_lo_calc_par(4) <= xor_reduce(tlb_way1_q(32 to 39)); +tlb_way1_lo_calc_par(5) <= xor_reduce(tlb_way1_q(40 to 47)); +tlb_way1_lo_calc_par(6) <= xor_reduce(tlb_way1_q(48 to 51)); +tlb_way1_lo_calc_par(7) <= xor_reduce(tlb_way1_q(52 to 59)); +tlb_way1_lo_calc_par(8) <= xor_reduce(tlb_way1_q(60 to 65)); +tlb_way1_lo_calc_par(9) <= xor_reduce(tlb_way1_q(66 to 73)); +tlb_way2_lo_calc_par(0) <= xor_reduce(tlb_way2_q(0 to 7)); +tlb_way2_lo_calc_par(1) <= xor_reduce(tlb_way2_q(8 to 15)); +tlb_way2_lo_calc_par(2) <= xor_reduce(tlb_way2_q(16 to 23)); +tlb_way2_lo_calc_par(3) <= xor_reduce(tlb_way2_q(24 to 31)); +tlb_way2_lo_calc_par(4) <= xor_reduce(tlb_way2_q(32 to 39)); +tlb_way2_lo_calc_par(5) <= xor_reduce(tlb_way2_q(40 to 47)); +tlb_way2_lo_calc_par(6) <= xor_reduce(tlb_way2_q(48 to 51)); +tlb_way2_lo_calc_par(7) <= xor_reduce(tlb_way2_q(52 to 59)); +tlb_way2_lo_calc_par(8) <= xor_reduce(tlb_way2_q(60 to 65)); +tlb_way2_lo_calc_par(9) <= xor_reduce(tlb_way2_q(66 to 73)); +tlb_way3_lo_calc_par(0) <= xor_reduce(tlb_way3_q(0 to 7)); +tlb_way3_lo_calc_par(1) <= xor_reduce(tlb_way3_q(8 to 15)); +tlb_way3_lo_calc_par(2) <= xor_reduce(tlb_way3_q(16 to 23)); +tlb_way3_lo_calc_par(3) <= xor_reduce(tlb_way3_q(24 to 31)); +tlb_way3_lo_calc_par(4) <= xor_reduce(tlb_way3_q(32 to 39)); +tlb_way3_lo_calc_par(5) <= xor_reduce(tlb_way3_q(40 to 47)); +tlb_way3_lo_calc_par(6) <= xor_reduce(tlb_way3_q(48 to 51)); +tlb_way3_lo_calc_par(7) <= xor_reduce(tlb_way3_q(52 to 59)); +tlb_way3_lo_calc_par(8) <= xor_reduce(tlb_way3_q(60 to 65)); +tlb_way3_lo_calc_par(9) <= xor_reduce(tlb_way3_q(66 to 73)); +tlb_way0_hi_calc_par(0) <= xor_reduce(tlb_way0_q(tlb_word_width+0 to tlb_word_width+7)); +tlb_way0_hi_calc_par(1) <= xor_reduce(tlb_way0_q(tlb_word_width+8 to tlb_word_width+15)); +tlb_way0_hi_calc_par(2) <= xor_reduce(tlb_way0_q(tlb_word_width+16 to tlb_word_width+23)); +tlb_way0_hi_calc_par(3) <= xor_reduce(tlb_way0_q(tlb_word_width+24 to tlb_word_width+31)); +tlb_way0_hi_calc_par(4) <= xor_reduce(tlb_way0_q(tlb_word_width+32 to tlb_word_width+39)); +tlb_way0_hi_calc_par(5) <= xor_reduce(tlb_way0_q(tlb_word_width+40 to tlb_word_width+44)); +tlb_way0_hi_calc_par(6) <= xor_reduce(tlb_way0_q(tlb_word_width+45 to tlb_word_width+49)); +tlb_way0_hi_calc_par(7) <= xor_reduce(tlb_way0_q(tlb_word_width+50 to tlb_word_width+57)); +tlb_way0_hi_calc_par(8) <= xor_reduce(tlb_way0_q(tlb_word_width+58 to tlb_word_width+65)); +tlb_way0_hi_calc_par(9) <= xor_reduce(tlb_way0_q(tlb_word_width+66 to tlb_word_width+73)); +tlb_way1_hi_calc_par(0) <= xor_reduce(tlb_way1_q(tlb_word_width+0 to tlb_word_width+7)); +tlb_way1_hi_calc_par(1) <= xor_reduce(tlb_way1_q(tlb_word_width+8 to tlb_word_width+15)); +tlb_way1_hi_calc_par(2) <= xor_reduce(tlb_way1_q(tlb_word_width+16 to tlb_word_width+23)); +tlb_way1_hi_calc_par(3) <= xor_reduce(tlb_way1_q(tlb_word_width+24 to tlb_word_width+31)); +tlb_way1_hi_calc_par(4) <= xor_reduce(tlb_way1_q(tlb_word_width+32 to tlb_word_width+39)); +tlb_way1_hi_calc_par(5) <= xor_reduce(tlb_way1_q(tlb_word_width+40 to tlb_word_width+44)); +tlb_way1_hi_calc_par(6) <= xor_reduce(tlb_way1_q(tlb_word_width+45 to tlb_word_width+49)); +tlb_way1_hi_calc_par(7) <= xor_reduce(tlb_way1_q(tlb_word_width+50 to tlb_word_width+57)); +tlb_way1_hi_calc_par(8) <= xor_reduce(tlb_way1_q(tlb_word_width+58 to tlb_word_width+65)); +tlb_way1_hi_calc_par(9) <= xor_reduce(tlb_way1_q(tlb_word_width+66 to tlb_word_width+73)); +tlb_way2_hi_calc_par(0) <= xor_reduce(tlb_way2_q(tlb_word_width+0 to tlb_word_width+7)); +tlb_way2_hi_calc_par(1) <= xor_reduce(tlb_way2_q(tlb_word_width+8 to tlb_word_width+15)); +tlb_way2_hi_calc_par(2) <= xor_reduce(tlb_way2_q(tlb_word_width+16 to tlb_word_width+23)); +tlb_way2_hi_calc_par(3) <= xor_reduce(tlb_way2_q(tlb_word_width+24 to tlb_word_width+31)); +tlb_way2_hi_calc_par(4) <= xor_reduce(tlb_way2_q(tlb_word_width+32 to tlb_word_width+39)); +tlb_way2_hi_calc_par(5) <= xor_reduce(tlb_way2_q(tlb_word_width+40 to tlb_word_width+44)); +tlb_way2_hi_calc_par(6) <= xor_reduce(tlb_way2_q(tlb_word_width+45 to tlb_word_width+49)); +tlb_way2_hi_calc_par(7) <= xor_reduce(tlb_way2_q(tlb_word_width+50 to tlb_word_width+57)); +tlb_way2_hi_calc_par(8) <= xor_reduce(tlb_way2_q(tlb_word_width+58 to tlb_word_width+65)); +tlb_way2_hi_calc_par(9) <= xor_reduce(tlb_way2_q(tlb_word_width+66 to tlb_word_width+73)); +tlb_way3_hi_calc_par(0) <= xor_reduce(tlb_way3_q(tlb_word_width+0 to tlb_word_width+7)); +tlb_way3_hi_calc_par(1) <= xor_reduce(tlb_way3_q(tlb_word_width+8 to tlb_word_width+15)); +tlb_way3_hi_calc_par(2) <= xor_reduce(tlb_way3_q(tlb_word_width+16 to tlb_word_width+23)); +tlb_way3_hi_calc_par(3) <= xor_reduce(tlb_way3_q(tlb_word_width+24 to tlb_word_width+31)); +tlb_way3_hi_calc_par(4) <= xor_reduce(tlb_way3_q(tlb_word_width+32 to tlb_word_width+39)); +tlb_way3_hi_calc_par(5) <= xor_reduce(tlb_way3_q(tlb_word_width+40 to tlb_word_width+44)); +tlb_way3_hi_calc_par(6) <= xor_reduce(tlb_way3_q(tlb_word_width+45 to tlb_word_width+49)); +tlb_way3_hi_calc_par(7) <= xor_reduce(tlb_way3_q(tlb_word_width+50 to tlb_word_width+57)); +tlb_way3_hi_calc_par(8) <= xor_reduce(tlb_way3_q(tlb_word_width+58 to tlb_word_width+65)); +tlb_way3_hi_calc_par(9) <= xor_reduce(tlb_way3_q(tlb_word_width+66 to tlb_word_width+73)); +tlb_way0_parerr <= or_reduce(tlb_way0_lo_calc_par(0 to 9) xor tlb_way0_q(74 to 83)) or + or_reduce(tlb_way0_hi_calc_par(0 to 9) xor tlb_way0_q(tlb_word_width+74 to tlb_word_width+83)); +tlb_way1_parerr <= or_reduce(tlb_way1_lo_calc_par(0 to 9) xor tlb_way1_q(74 to 83)) or + or_reduce(tlb_way1_hi_calc_par(0 to 9) xor tlb_way1_q(tlb_word_width+74 to tlb_word_width+83)); +tlb_way2_parerr <= or_reduce(tlb_way2_lo_calc_par(0 to 9) xor tlb_way2_q(74 to 83)) or + or_reduce(tlb_way2_hi_calc_par(0 to 9) xor tlb_way2_q(tlb_word_width+74 to tlb_word_width+83)); +tlb_way3_parerr <= or_reduce(tlb_way3_lo_calc_par(0 to 9) xor tlb_way3_q(74 to 83)) or + or_reduce(tlb_way3_hi_calc_par(0 to 9) xor tlb_way3_q(tlb_word_width+74 to tlb_word_width+83)); +tag4_parerr_d(0) <= tlb_way0_parerr; +tag4_parerr_d(1) <= tlb_way1_parerr; +tag4_parerr_d(2) <= tlb_way2_parerr; +tag4_parerr_d(3) <= tlb_way3_parerr; +lru_tag3_dataout_d <= lru_dataout; +tlb_tag4_d(0 TO tagpos_thdid-1) <= tlb_tag3_q(0 to tagpos_thdid-1); +tlb_tag4_d(tagpos_thdid TO tagpos_thdid+thdid_width-1) <= + (others => '0') when ((tlb_tag4_wayhit_q(tlb_ways)='1' or tlb_tag4_q(tagpos_endflag)='1' or or_reduce(tag4_parerr_q(0 to 4))='1') and + tlb_tag4_q(tagpos_type_ptereload)='0' and + (tlb_tag4_q(tagpos_type_ierat)='1' or tlb_tag4_q(tagpos_type_derat)='1')) + else (others => '0') when ((tlb_tag4_wayhit_q(tlb_ways)='1' or tlb_tag4_q(tagpos_endflag)='1' or or_reduce(tag4_parerr_q(0 to 4))='1') and + (tlb_tag4_q(tagpos_type_tlbsx)='1' or tlb_tag4_q(tagpos_type_tlbsrx)='1')) + else (others => '0') when (tlb_tag4_q(tagpos_endflag)='1' and tlb_tag4_q(tagpos_type_snoop)='1') + else (others => '0') when ((tlb_tag4_q(tagpos_type_tlbre)='1' or tlb_tag4_q(tagpos_type_tlbwe)='1' or tlb_tag4_q(tagpos_type_ptereload)='1') and + tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000") + else tlb_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag3_flush); +tlb_tag4_d(tagpos_thdid+thdid_width TO tlb_tag_width-1) <= tlb_tag3_q(tagpos_thdid+thdid_width to tlb_tag_width-1); +tlb_addr4_d <= tlb_addr3_q; +tlb_tag4_way_d <= ( tlb_way0_q and (0 to tlb_way_width-1 => tlb_wayhit(0)) ) or + ( tlb_way1_q and (0 to tlb_way_width-1 => tlb_wayhit(1)) ); +tlb_tag4_way_clone_d <= ( tlb_way2_q and (0 to tlb_way_width-1 => tlb_wayhit(2)) ) or + ( tlb_way3_q and (0 to tlb_way_width-1 => tlb_wayhit(3)) ); +tlb_tag4_way_or <= tlb_tag4_way_q or tlb_tag4_way_clone_q; +tlb_tag4_way_rw_d <= ( tlb_way0_q and (0 to tlb_way_width-1 => (not tlb_tag3_clone1_q(tagpos_esel+1) and not tlb_tag3_clone1_q(tagpos_esel+2) and or_reduce(tlb_tag3_clone1_q(tagpos_thdid to tagpos_thdid+thdid_width-1)) and + (tlb_tag3_clone1_q(tagpos_type_tlbre) or (tlb_tag3_clone1_q(tagpos_type_tlbwe) and not tlb_tag3_clone1_q(tagpos_hes))) )) ) or + ( tlb_way1_q and (0 to tlb_way_width-1 => (not tlb_tag3_clone1_q(tagpos_esel+1) and tlb_tag3_clone1_q(tagpos_esel+2) and or_reduce(tlb_tag3_clone1_q(tagpos_thdid to tagpos_thdid+thdid_width-1)) and + (tlb_tag3_clone1_q(tagpos_type_tlbre) or (tlb_tag3_clone1_q(tagpos_type_tlbwe) and not tlb_tag3_clone1_q(tagpos_hes))) )) ) or + + ( tlb_way0_q and (0 to tlb_way_width-1 => (not lru_tag3_dataout_q(4) and not lru_tag3_dataout_q(5) and or_reduce(tlb_tag3_clone1_q(tagpos_thdid to tagpos_thdid+thdid_width-1)) and + (tlb_tag3_clone1_q(tagpos_type_ptereload) or (tlb_tag3_clone1_q(tagpos_type_tlbwe) and tlb_tag3_clone1_q(tagpos_hes))) )) ) or + ( tlb_way1_q and (0 to tlb_way_width-1 => (not lru_tag3_dataout_q(4) and lru_tag3_dataout_q(5) and or_reduce(tlb_tag3_clone1_q(tagpos_thdid to tagpos_thdid+thdid_width-1)) and + (tlb_tag3_clone1_q(tagpos_type_ptereload) or (tlb_tag3_clone1_q(tagpos_type_tlbwe) and tlb_tag3_clone1_q(tagpos_hes))) )) ); +tlb_tag4_way_rw_clone_d <= ( tlb_way2_q and (0 to tlb_way_width-1 => ( tlb_tag3_clone2_q(tagpos_esel+1) and not tlb_tag3_clone2_q(tagpos_esel+2) and or_reduce(tlb_tag3_clone2_q(tagpos_thdid to tagpos_thdid+thdid_width-1)) and + (tlb_tag3_clone2_q(tagpos_type_tlbre) or (tlb_tag3_clone2_q(tagpos_type_tlbwe) and not tlb_tag3_clone2_q(tagpos_hes))) )) ) or + ( tlb_way3_q and (0 to tlb_way_width-1 => ( tlb_tag3_clone2_q(tagpos_esel+1) and tlb_tag3_clone2_q(tagpos_esel+2) and or_reduce(tlb_tag3_clone2_q(tagpos_thdid to tagpos_thdid+thdid_width-1)) and + (tlb_tag3_clone2_q(tagpos_type_tlbre) or (tlb_tag3_clone2_q(tagpos_type_tlbwe) and not tlb_tag3_clone2_q(tagpos_hes))) )) ) or + + ( tlb_way2_q and (0 to tlb_way_width-1 => ( lru_tag3_dataout_q(4) and not lru_tag3_dataout_q(6) and or_reduce(tlb_tag3_clone2_q(tagpos_thdid to tagpos_thdid+thdid_width-1)) and + (tlb_tag3_clone2_q(tagpos_type_ptereload) or (tlb_tag3_clone2_q(tagpos_type_tlbwe) and tlb_tag3_clone2_q(tagpos_hes))) )) ) or + ( tlb_way3_q and (0 to tlb_way_width-1 => ( lru_tag3_dataout_q(4) and lru_tag3_dataout_q(6) and or_reduce(tlb_tag3_clone2_q(tagpos_thdid to tagpos_thdid+thdid_width-1)) and + (tlb_tag3_clone2_q(tagpos_type_ptereload) or (tlb_tag3_clone2_q(tagpos_type_tlbwe) and tlb_tag3_clone2_q(tagpos_hes))) )) ) ; +tlb_tag4_way_rw_or <= tlb_tag4_way_rw_q or tlb_tag4_way_rw_clone_q; +tlb_tag4_wayhit_d(0 TO tlb_ways-1) <= tlb_wayhit(0 to tlb_ways-1); +tlb_tag4_wayhit_d(tlb_ways) <= '1' when (tlb_tag4_wayhit_q(tlb_ways)='0' and tlb_wayhit(0 to tlb_ways-1) /= "0000" and + tlb_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000") + else '0'; +tlb_tag4_way_act <= or_reduce(tlb_tag3_clone1_q(tagpos_thdid to tagpos_thdid+thdid_width-1)) and not(tlb_tag4_wayhit_q(tlb_ways)) and not tlb_tag3_clone1_q(tagpos_type_ptereload) and + (tlb_tag3_clone1_q(tagpos_type_derat) or tlb_tag3_clone1_q(tagpos_type_ierat) or tlb_tag3_clone1_q(tagpos_type_tlbsx) or tlb_tag3_clone1_q(tagpos_type_tlbsrx)); +tlb_tag4_way_clone_act <= or_reduce(tlb_tag3_clone2_q(tagpos_thdid to tagpos_thdid+thdid_width-1)) and not(tlb_tag4_wayhit_q(tlb_ways)) and not tlb_tag3_clone2_q(tagpos_type_ptereload) and + (tlb_tag3_clone2_q(tagpos_type_derat) or tlb_tag3_clone2_q(tagpos_type_ierat) or tlb_tag3_clone2_q(tagpos_type_tlbsx) or tlb_tag3_clone2_q(tagpos_type_tlbsrx)); +tlb_tag4_way_rw_act <= or_reduce(tlb_tag3_clone1_q(tagpos_thdid to tagpos_thdid+thdid_width-1)) and + (tlb_tag3_clone1_q(tagpos_type_tlbre) or tlb_tag3_clone1_q(tagpos_type_tlbwe) or tlb_tag3_clone1_q(tagpos_type_ptereload)); +tlb_tag4_way_rw_clone_act <= or_reduce(tlb_tag3_clone2_q(tagpos_thdid to tagpos_thdid+thdid_width-1)) and + (tlb_tag3_clone2_q(tagpos_type_tlbre) or tlb_tag3_clone2_q(tagpos_type_tlbwe) or tlb_tag3_clone2_q(tagpos_type_ptereload)); +lru_tag4_dataout_d <= lru_tag3_dataout_q; +addr_enable(0) <= ( or_reduce(tlb_tag3_clone1_q(tagpos_type_derat to tagpos_type_tlbsrx)) and + not tlb_tag3_clone1_q(tagpos_type_ptereload) ) + or ( tlb_tag3_clone1_q(tagpos_type_snoop) and Eq(tlb_tag3_clone1_q(tagpos_is to tagpos_is+3),"1011") ); +addr_enable(1) <= ( or_reduce(tlb_tag3_clone1_q(tagpos_type_derat to tagpos_type_tlbsrx)) and + not tlb_tag3_clone1_q(tagpos_type_ptereload) ) + or ( tlb_tag3_clone1_q(tagpos_type_snoop) and Eq(tlb_tag3_clone1_q(tagpos_is to tagpos_is+3),"1011") ) + or ( tlb_tag3_clone1_q(tagpos_type_snoop) and Eq(tlb_tag3_clone1_q(tagpos_is to tagpos_is+3),"0011") and + mmucr1_q(pos_tlbi_msb) and tlb_tag3_cmpmask_q(0) ); +addr_enable(2) <= ( or_reduce(tlb_tag3_clone1_q(tagpos_type_derat to tagpos_type_tlbsrx)) and + not tlb_tag3_clone1_q(tagpos_type_ptereload) ) + or ( tlb_tag3_clone1_q(tagpos_type_snoop) and Eq(tlb_tag3_clone1_q(tagpos_is to tagpos_is+3),"1011") ) + or ( tlb_tag3_clone1_q(tagpos_type_snoop) and Eq(tlb_tag3_clone1_q(tagpos_is to tagpos_is+3),"0011") and + mmucr1_q(pos_tlbi_msb) and tlb_tag3_cmpmask_q(1) ); +addr_enable(3) <= ( or_reduce(tlb_tag3_clone1_q(tagpos_type_derat to tagpos_type_tlbsrx)) and + not tlb_tag3_clone1_q(tagpos_type_ptereload) ) + or ( tlb_tag3_clone1_q(tagpos_type_snoop) and Eq(tlb_tag3_clone1_q(tagpos_is to tagpos_is+3),"1011") ) + or ( tlb_tag3_clone1_q(tagpos_type_snoop) and Eq(tlb_tag3_clone1_q(tagpos_is to tagpos_is+3),"0011") and + mmucr1_q(pos_tlbi_msb) and tlb_tag3_cmpmask_q(1) ) + or ( tlb_tag3_clone1_q(tagpos_type_snoop) and Eq(tlb_tag3_clone1_q(tagpos_is to tagpos_is+3),"0011") and + not mmucr1_q(pos_tlbi_msb) and tlb_tag3_cmpmask_q(0) ); +addr_enable(4) <= ( or_reduce(tlb_tag3_clone1_q(tagpos_type_derat to tagpos_type_tlbsrx)) and + not tlb_tag3_clone1_q(tagpos_type_ptereload) ) + or ( tlb_tag3_clone1_q(tagpos_type_snoop) and Eq(tlb_tag3_clone1_q(tagpos_is to tagpos_is+3),"1011") ) + or ( tlb_tag3_clone1_q(tagpos_type_snoop) and Eq(tlb_tag3_clone1_q(tagpos_is to tagpos_is+3),"0011") and + mmucr1_q(pos_tlbi_msb) and tlb_tag3_cmpmask_q(2) ) + or ( tlb_tag3_clone1_q(tagpos_type_snoop) and Eq(tlb_tag3_clone1_q(tagpos_is to tagpos_is+3),"0011") and + not mmucr1_q(pos_tlbi_msb) and tlb_tag3_cmpmask_q(1) ); +addr_enable(5) <= ( or_reduce(tlb_tag3_clone1_q(tagpos_type_derat to tagpos_type_tlbsrx)) and + not tlb_tag3_clone1_q(tagpos_type_ptereload) ) + or ( tlb_tag3_clone1_q(tagpos_type_snoop) and Eq(tlb_tag3_clone1_q(tagpos_is to tagpos_is+3),"1011") ) + or ( tlb_tag3_clone1_q(tagpos_type_snoop) and Eq(tlb_tag3_clone1_q(tagpos_is to tagpos_is+3),"0011") and + mmucr1_q(pos_tlbi_msb) and tlb_tag3_cmpmask_q(3) ) + or ( tlb_tag3_clone1_q(tagpos_type_snoop) and Eq(tlb_tag3_clone1_q(tagpos_is to tagpos_is+3),"0011") and + not mmucr1_q(pos_tlbi_msb) and tlb_tag3_cmpmask_q(2) ); +addr_enable(6) <= ( or_reduce(tlb_tag3_clone1_q(tagpos_type_derat to tagpos_type_tlbsrx)) and + not tlb_tag3_clone1_q(tagpos_type_ptereload) ) + or ( tlb_tag3_clone1_q(tagpos_type_snoop) and Eq(tlb_tag3_clone1_q(tagpos_is to tagpos_is+3),"1011") ) + or ( tlb_tag3_clone1_q(tagpos_type_snoop) and Eq(tlb_tag3_clone1_q(tagpos_is to tagpos_is+3),"0011") and + mmucr1_q(pos_tlbi_msb) ) + or ( tlb_tag3_clone1_q(tagpos_type_snoop) and Eq(tlb_tag3_clone1_q(tagpos_is to tagpos_is+3),"0011") and + not mmucr1_q(pos_tlbi_msb) and tlb_tag3_cmpmask_q(3) ); +addr_enable(7) <= ( or_reduce(tlb_tag3_clone1_q(tagpos_type_derat to tagpos_type_tlbsrx)) and + not tlb_tag3_clone1_q(tagpos_type_ptereload) ) + or ( tlb_tag3_clone1_q(tagpos_type_snoop) and Eq(tlb_tag3_clone1_q(tagpos_is+1 to tagpos_is+3),"011") ); +addr_enable(8) <= ( or_reduce(tlb_tag3_clone1_q(tagpos_type_derat to tagpos_type_tlbsrx)) and + not tlb_tag3_clone1_q(tagpos_type_ptereload) ) + or ( tlb_tag3_clone1_q(tagpos_type_snoop) and Eq(tlb_tag3_clone1_q(tagpos_is+1 to tagpos_is+3),"011") ); +class_enable <= '1' when (tlb_tag3_clone1_q(tagpos_type_snoop)='1' and tlb_tag3_clone1_q(tagpos_is+1)='1') + else '0'; +pgsize_enable <= tlb_tag3_clone1_q(tagpos_type_snoop) and Eq(tlb_tag3_clone1_q(tagpos_is+1 to tagpos_is+3),"011"); +extclass_enable <= "00"; +thdid_enable <= or_reduce(tlb_tag3_clone1_q(tagpos_type_derat to tagpos_type_tlbsrx)) and not tlb_tag3_clone1_q(tagpos_type_ptereload); +pid_enable <= '1' when (tlb_tag3_clone1_q(tagpos_type_derat to tagpos_type_tlbsrx) /= "0000" and + tlb_tag3_clone1_q(tagpos_type_ptereload)='0') + else '1' when (tlb_tag3_clone1_q(tagpos_type_snoop)='1' and tlb_tag3_clone1_q(tagpos_is+1 to tagpos_is+3)="001") + else '1' when (tlb_tag3_clone1_q(tagpos_type_snoop)='1' and tlb_tag3_clone1_q(tagpos_is+1 to tagpos_is+3)="011") + else '0'; +state_enable(0) <= '1' when (tlb_tag3_clone1_q(tagpos_type_derat to tagpos_type_tlbsrx) /= "0000" and + tlb_tag3_clone1_q(tagpos_type_ptereload)='0') + else '1' when (tlb_tag3_clone1_q(tagpos_type_snoop)='1' and tlb_tag3_clone1_q(tagpos_is+1 to tagpos_is+3)="010" ) + else '1' when (tlb_tag3_clone1_q(tagpos_type_snoop)='1' and tlb_tag3_clone1_q(tagpos_is+1 to tagpos_is+3)="011" ) + else '0'; +state_enable(1) <= '1' when (tlb_tag3_clone1_q(tagpos_type_derat to tagpos_type_tlbsrx) /= "0000" and + tlb_tag3_clone1_q(tagpos_type_ptereload)='0') + else '1' when (tlb_tag3_clone1_q(tagpos_type_snoop)='1' and tlb_tag3_clone1_q(tagpos_is+1 to tagpos_is+3)="011" ) + else '0'; +lpid_enable <= '1' when (tlb_tag3_clone1_q(tagpos_type_derat to tagpos_type_tlbsrx) /= "0000" and + tlb_tag3_clone1_q(tagpos_type_ptereload)='0') + else not(tlb_tag3_clone1_q(tagpos_hes)) when (tlb_tag3_clone1_q(tagpos_type_snoop)='1') + else '0'; +ind_enable <= ( or_reduce(tlb_tag3_clone1_q(tagpos_type_derat to tagpos_type_tlbsrx)) and + not tlb_tag3_clone1_q(tagpos_type_ptereload) ) + or ( tlb_tag3_clone1_q(tagpos_type_snoop) and Eq(tlb_tag3_clone1_q(tagpos_is+1 to tagpos_is+3),"011") ) + or ( tlb_tag3_clone1_q(tagpos_type_snoop) and Eq(tlb_tag3_clone1_q(tagpos_is+1 to tagpos_is+3),"001") and tlb_tag3_clone1_q(tagpos_ind) ); +iprot_enable <= tlb_tag3_clone1_q(tagpos_type_snoop); +comp_extclass <= (others => '0'); +comp_iprot <= '0'; +comp_ind <= tlb_tag3_clone1_q(tagpos_ind) and not(tlb_tag3_clone1_q(tagpos_type_snoop) and Eq(tlb_tag3_clone1_q(tagpos_is+1 to tagpos_is+3),"001")); +addr_enable_clone(0) <= ( or_reduce(tlb_tag3_clone2_q(tagpos_type_derat to tagpos_type_tlbsrx)) and + not tlb_tag3_clone2_q(tagpos_type_ptereload) ) + or ( tlb_tag3_clone2_q(tagpos_type_snoop) and Eq(tlb_tag3_clone2_q(tagpos_is to tagpos_is+3),"1011") ); +addr_enable_clone(1) <= ( or_reduce(tlb_tag3_clone2_q(tagpos_type_derat to tagpos_type_tlbsrx)) and + not tlb_tag3_clone2_q(tagpos_type_ptereload) ) + or ( tlb_tag3_clone2_q(tagpos_type_snoop) and Eq(tlb_tag3_clone2_q(tagpos_is to tagpos_is+3),"1011") ) + or ( tlb_tag3_clone2_q(tagpos_type_snoop) and Eq(tlb_tag3_clone2_q(tagpos_is to tagpos_is+3),"0011") and + mmucr1_clone_q(pos_tlbi_msb) and tlb_tag3_cmpmask_clone_q(0) ); +addr_enable_clone(2) <= ( or_reduce(tlb_tag3_clone2_q(tagpos_type_derat to tagpos_type_tlbsrx)) and + not tlb_tag3_clone2_q(tagpos_type_ptereload) ) + or ( tlb_tag3_clone2_q(tagpos_type_snoop) and Eq(tlb_tag3_clone2_q(tagpos_is to tagpos_is+3),"1011") ) + or ( tlb_tag3_clone2_q(tagpos_type_snoop) and Eq(tlb_tag3_clone2_q(tagpos_is to tagpos_is+3),"0011") and + mmucr1_clone_q(pos_tlbi_msb) and tlb_tag3_cmpmask_clone_q(1) ); +addr_enable_clone(3) <= ( or_reduce(tlb_tag3_clone2_q(tagpos_type_derat to tagpos_type_tlbsrx)) and + not tlb_tag3_clone2_q(tagpos_type_ptereload) ) + or ( tlb_tag3_clone2_q(tagpos_type_snoop) and Eq(tlb_tag3_clone2_q(tagpos_is to tagpos_is+3),"1011") ) + or ( tlb_tag3_clone2_q(tagpos_type_snoop) and Eq(tlb_tag3_clone2_q(tagpos_is to tagpos_is+3),"0011") and + mmucr1_clone_q(pos_tlbi_msb) and tlb_tag3_cmpmask_clone_q(1) ) + or ( tlb_tag3_clone2_q(tagpos_type_snoop) and Eq(tlb_tag3_clone2_q(tagpos_is to tagpos_is+3),"0011") and + not mmucr1_clone_q(pos_tlbi_msb) and tlb_tag3_cmpmask_clone_q(0) ); +addr_enable_clone(4) <= ( or_reduce(tlb_tag3_clone2_q(tagpos_type_derat to tagpos_type_tlbsrx)) and + not tlb_tag3_clone2_q(tagpos_type_ptereload) ) + or ( tlb_tag3_clone2_q(tagpos_type_snoop) and Eq(tlb_tag3_clone2_q(tagpos_is to tagpos_is+3),"1011") ) + or ( tlb_tag3_clone2_q(tagpos_type_snoop) and Eq(tlb_tag3_clone2_q(tagpos_is to tagpos_is+3),"0011") and + mmucr1_clone_q(pos_tlbi_msb) and tlb_tag3_cmpmask_clone_q(2) ) + or ( tlb_tag3_clone2_q(tagpos_type_snoop) and Eq(tlb_tag3_clone2_q(tagpos_is to tagpos_is+3),"0011") and + not mmucr1_clone_q(pos_tlbi_msb) and tlb_tag3_cmpmask_clone_q(1) ); +addr_enable_clone(5) <= ( or_reduce(tlb_tag3_clone2_q(tagpos_type_derat to tagpos_type_tlbsrx)) and + not tlb_tag3_clone2_q(tagpos_type_ptereload) ) + or ( tlb_tag3_clone2_q(tagpos_type_snoop) and Eq(tlb_tag3_clone2_q(tagpos_is to tagpos_is+3),"1011") ) + or ( tlb_tag3_clone2_q(tagpos_type_snoop) and Eq(tlb_tag3_clone2_q(tagpos_is to tagpos_is+3),"0011") and + mmucr1_clone_q(pos_tlbi_msb) and tlb_tag3_cmpmask_clone_q(3) ) + or ( tlb_tag3_clone2_q(tagpos_type_snoop) and Eq(tlb_tag3_clone2_q(tagpos_is to tagpos_is+3),"0011") and + not mmucr1_clone_q(pos_tlbi_msb) and tlb_tag3_cmpmask_clone_q(2) ); +addr_enable_clone(6) <= ( or_reduce(tlb_tag3_clone2_q(tagpos_type_derat to tagpos_type_tlbsrx)) and + not tlb_tag3_clone2_q(tagpos_type_ptereload) ) + or ( tlb_tag3_clone2_q(tagpos_type_snoop) and Eq(tlb_tag3_clone2_q(tagpos_is to tagpos_is+3),"1011") ) + or ( tlb_tag3_clone2_q(tagpos_type_snoop) and Eq(tlb_tag3_clone2_q(tagpos_is to tagpos_is+3),"0011") and + mmucr1_clone_q(pos_tlbi_msb) ) + or ( tlb_tag3_clone2_q(tagpos_type_snoop) and Eq(tlb_tag3_clone2_q(tagpos_is to tagpos_is+3),"0011") and + not mmucr1_clone_q(pos_tlbi_msb) and tlb_tag3_cmpmask_clone_q(3) ); +addr_enable_clone(7) <= ( or_reduce(tlb_tag3_clone2_q(tagpos_type_derat to tagpos_type_tlbsrx)) and + not tlb_tag3_clone2_q(tagpos_type_ptereload) ) + or ( tlb_tag3_clone2_q(tagpos_type_snoop) and Eq(tlb_tag3_clone2_q(tagpos_is+1 to tagpos_is+3),"011") ); +addr_enable_clone(8) <= ( or_reduce(tlb_tag3_clone2_q(tagpos_type_derat to tagpos_type_tlbsrx)) and + not tlb_tag3_clone2_q(tagpos_type_ptereload) ) + or ( tlb_tag3_clone2_q(tagpos_type_snoop) and Eq(tlb_tag3_clone2_q(tagpos_is+1 to tagpos_is+3),"011") ); +class_enable_clone <= '1' when (tlb_tag3_clone2_q(tagpos_type_snoop)='1' and tlb_tag3_clone2_q(tagpos_is+1)='1') + else '0'; +pgsize_enable_clone <= tlb_tag3_clone2_q(tagpos_type_snoop) and Eq(tlb_tag3_clone2_q(tagpos_is+1 to tagpos_is+3),"011"); +extclass_enable_clone <= "00"; +thdid_enable_clone <= or_reduce(tlb_tag3_clone2_q(tagpos_type_derat to tagpos_type_tlbsrx)) and not tlb_tag3_clone2_q(tagpos_type_ptereload); +pid_enable_clone <= '1' when (tlb_tag3_clone2_q(tagpos_type_derat to tagpos_type_tlbsrx) /= "0000" and + tlb_tag3_clone2_q(tagpos_type_ptereload)='0') + else '1' when (tlb_tag3_clone2_q(tagpos_type_snoop)='1' and tlb_tag3_clone2_q(tagpos_is+1 to tagpos_is+3)="001") + else '1' when (tlb_tag3_clone2_q(tagpos_type_snoop)='1' and tlb_tag3_clone2_q(tagpos_is+1 to tagpos_is+3)="011") + else '0'; +state_enable_clone(0) <= '1' when (tlb_tag3_clone2_q(tagpos_type_derat to tagpos_type_tlbsrx) /= "0000" and + tlb_tag3_clone2_q(tagpos_type_ptereload)='0') + else '1' when (tlb_tag3_clone2_q(tagpos_type_snoop)='1' and tlb_tag3_clone2_q(tagpos_is+1 to tagpos_is+3)="010" ) + else '1' when (tlb_tag3_clone2_q(tagpos_type_snoop)='1' and tlb_tag3_clone2_q(tagpos_is+1 to tagpos_is+3)="011" ) + else '0'; +state_enable_clone(1) <= '1' when (tlb_tag3_clone2_q(tagpos_type_derat to tagpos_type_tlbsrx) /= "0000" and + tlb_tag3_clone2_q(tagpos_type_ptereload)='0') + else '1' when (tlb_tag3_clone2_q(tagpos_type_snoop)='1' and tlb_tag3_clone2_q(tagpos_is+1 to tagpos_is+3)="011" ) + else '0'; +lpid_enable_clone <= '1' when (tlb_tag3_clone2_q(tagpos_type_derat to tagpos_type_tlbsrx) /= "0000" and + tlb_tag3_clone2_q(tagpos_type_ptereload)='0') + else not(tlb_tag3_clone2_q(tagpos_hes)) when (tlb_tag3_clone2_q(tagpos_type_snoop)='1') + else '0'; +ind_enable_clone <= ( or_reduce(tlb_tag3_clone2_q(tagpos_type_derat to tagpos_type_tlbsrx)) and + not tlb_tag3_clone2_q(tagpos_type_ptereload) ) + or ( tlb_tag3_clone2_q(tagpos_type_snoop) and Eq(tlb_tag3_clone2_q(tagpos_is+1 to tagpos_is+3),"011") ) + or ( tlb_tag3_clone2_q(tagpos_type_snoop) and Eq(tlb_tag3_clone2_q(tagpos_is+1 to tagpos_is+3),"001") and tlb_tag3_clone2_q(tagpos_ind) ); +iprot_enable_clone <= tlb_tag3_clone2_q(tagpos_type_snoop); +comp_extclass_clone <= (others => '0'); +comp_iprot_clone <= '0'; +comp_ind_clone <= tlb_tag3_clone2_q(tagpos_ind) and not(tlb_tag3_clone2_q(tagpos_type_snoop) and Eq(tlb_tag3_clone2_q(tagpos_is+1 to tagpos_is+3),"001")); +tlb_tag4_type_sig(0 TO 7) <= tlb_tag4_q(tagpos_type to tagpos_type+7); +tlb_tag4_esel_sig(0 TO 2) <= tlb_tag4_q(tagpos_esel to tagpos_esel+2); +tlb_tag4_hes_sig <= tlb_tag4_q(tagpos_hes); +tlb_tag4_wq_sig(0 TO 1) <= tlb_tag4_q(tagpos_wq to tagpos_wq+1); +tlb_tag4_is_sig(0 TO 3) <= tlb_tag4_q(tagpos_is to tagpos_is+3); +tlb_tag4_hv_op <= or_reduce( not msr_gs_q and not msr_pr_q and tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) ); +multihit <= not(Eq(tlb_tag4_wayhit_q(0 to 3),"0000") or Eq(tlb_tag4_wayhit_q(0 to 3),"1000") or Eq(tlb_tag4_wayhit_q(0 to 3),"0100") + or Eq(tlb_tag4_wayhit_q(0 to 3),"0010") or Eq(tlb_tag4_wayhit_q(0 to 3),"0001")) + and or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1)); +tlb_tag4_hes1_mas1_v(0 TO thdid_width-1) <= + ( (tlb_tag4_q(tagpos_is) & lru_tag4_dataout_q(1 to 3)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+0) and tlb_tag4_q(tagpos_hes) and not lru_tag4_dataout_q(4) and not lru_tag4_dataout_q(5))) ) + or ( (lru_tag4_dataout_q(0) & tlb_tag4_q(tagpos_is) & lru_tag4_dataout_q(2 to 3)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+0) and tlb_tag4_q(tagpos_hes) and not lru_tag4_dataout_q(4) and lru_tag4_dataout_q(5))) ) + or ( (lru_tag4_dataout_q(0 to 1) & tlb_tag4_q(tagpos_is) & lru_tag4_dataout_q(3)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+0) and tlb_tag4_q(tagpos_hes) and lru_tag4_dataout_q(4) and not lru_tag4_dataout_q(6))) ) + or ( (lru_tag4_dataout_q(0 to 2) & tlb_tag4_q(tagpos_is)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+0) and tlb_tag4_q(tagpos_hes) and lru_tag4_dataout_q(4) and lru_tag4_dataout_q(6))) ) + + or ( (tlb_tag4_q(tagpos_is) & lru_tag4_dataout_q(1 to 3)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+1) and tlb_tag4_q(tagpos_hes) and not lru_tag4_dataout_q(4) and not lru_tag4_dataout_q(5))) ) + or ( (lru_tag4_dataout_q(0) & tlb_tag4_q(tagpos_is) & lru_tag4_dataout_q(2 to 3)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+1) and tlb_tag4_q(tagpos_hes) and not lru_tag4_dataout_q(4) and lru_tag4_dataout_q(5))) ) + or ( (lru_tag4_dataout_q(0 to 1) & tlb_tag4_q(tagpos_is) & lru_tag4_dataout_q(3)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+1) and tlb_tag4_q(tagpos_hes) and lru_tag4_dataout_q(4) and not lru_tag4_dataout_q(6))) ) + or ( (lru_tag4_dataout_q(0 to 2) & tlb_tag4_q(tagpos_is)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+1) and tlb_tag4_q(tagpos_hes) and lru_tag4_dataout_q(4) and lru_tag4_dataout_q(6))) ) + + or ( (tlb_tag4_q(tagpos_is) & lru_tag4_dataout_q(1 to 3)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+2) and tlb_tag4_q(tagpos_hes) and not lru_tag4_dataout_q(4) and not lru_tag4_dataout_q(5))) ) + or ( (lru_tag4_dataout_q(0) & tlb_tag4_q(tagpos_is) & lru_tag4_dataout_q(2 to 3)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+2) and tlb_tag4_q(tagpos_hes) and not lru_tag4_dataout_q(4) and lru_tag4_dataout_q(5))) ) + or ( (lru_tag4_dataout_q(0 to 1) & tlb_tag4_q(tagpos_is) & lru_tag4_dataout_q(3)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+2) and tlb_tag4_q(tagpos_hes) and lru_tag4_dataout_q(4) and not lru_tag4_dataout_q(6))) ) + or ( (lru_tag4_dataout_q(0 to 2) & tlb_tag4_q(tagpos_is)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+2) and tlb_tag4_q(tagpos_hes) and lru_tag4_dataout_q(4) and lru_tag4_dataout_q(6))) ) + + or ( (tlb_tag4_q(tagpos_is) & lru_tag4_dataout_q(1 to 3)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+3) and tlb_tag4_q(tagpos_hes) and not lru_tag4_dataout_q(4) and not lru_tag4_dataout_q(5))) ) + or ( (lru_tag4_dataout_q(0) & tlb_tag4_q(tagpos_is) & lru_tag4_dataout_q(2 to 3)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+3) and tlb_tag4_q(tagpos_hes) and not lru_tag4_dataout_q(4) and lru_tag4_dataout_q(5))) ) + or ( (lru_tag4_dataout_q(0 to 1) & tlb_tag4_q(tagpos_is) & lru_tag4_dataout_q(3)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+3) and tlb_tag4_q(tagpos_hes) and lru_tag4_dataout_q(4) and not lru_tag4_dataout_q(6))) ) + or ( (lru_tag4_dataout_q(0 to 2) & tlb_tag4_q(tagpos_is)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+3) and tlb_tag4_q(tagpos_hes) and lru_tag4_dataout_q(4) and lru_tag4_dataout_q(6))) ); +tlb_tag4_hes0_mas1_v(0 TO thdid_width-1) <= + ( (tlb_tag4_q(tagpos_is) & lru_tag4_dataout_q(1 to 3)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+0) and not tlb_tag4_q(tagpos_hes) and not tlb_tag4_q(tagpos_esel+1) and not tlb_tag4_q(tagpos_esel+2))) ) + or ( (lru_tag4_dataout_q(0) & tlb_tag4_q(tagpos_is) & lru_tag4_dataout_q(2 to 3)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+0) and not tlb_tag4_q(tagpos_hes) and not tlb_tag4_q(tagpos_esel+1) and tlb_tag4_q(tagpos_esel+2))) ) + or ( (lru_tag4_dataout_q(0 to 1) & tlb_tag4_q(tagpos_is) & lru_tag4_dataout_q(3)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+0) and not tlb_tag4_q(tagpos_hes) and tlb_tag4_q(tagpos_esel+1) and not tlb_tag4_q(tagpos_esel+2))) ) + or ( (lru_tag4_dataout_q(0 to 2) & tlb_tag4_q(tagpos_is)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+0) and not tlb_tag4_q(tagpos_hes) and tlb_tag4_q(tagpos_esel+1) and tlb_tag4_q(tagpos_esel+2))) ) + + or ( (tlb_tag4_q(tagpos_is) & lru_tag4_dataout_q(1 to 3)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+1) and not tlb_tag4_q(tagpos_hes) and not tlb_tag4_q(tagpos_esel+1) and not tlb_tag4_q(tagpos_esel+2))) ) + or ( (lru_tag4_dataout_q(0) & tlb_tag4_q(tagpos_is) & lru_tag4_dataout_q(2 to 3)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+1) and not tlb_tag4_q(tagpos_hes) and not tlb_tag4_q(tagpos_esel+1) and tlb_tag4_q(tagpos_esel+2))) ) + or ( (lru_tag4_dataout_q(0 to 1) & tlb_tag4_q(tagpos_is) & lru_tag4_dataout_q(3)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+1) and not tlb_tag4_q(tagpos_hes) and tlb_tag4_q(tagpos_esel+1) and not tlb_tag4_q(tagpos_esel+2))) ) + or ( (lru_tag4_dataout_q(0 to 2) & tlb_tag4_q(tagpos_is)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+1) and not tlb_tag4_q(tagpos_hes) and tlb_tag4_q(tagpos_esel+1) and tlb_tag4_q(tagpos_esel+2))) ) + + or ( (tlb_tag4_q(tagpos_is) & lru_tag4_dataout_q(1 to 3)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+2) and not tlb_tag4_q(tagpos_hes) and not tlb_tag4_q(tagpos_esel+1) and not tlb_tag4_q(tagpos_esel+2))) ) + or ( (lru_tag4_dataout_q(0) & tlb_tag4_q(tagpos_is) & lru_tag4_dataout_q(2 to 3)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+2) and not tlb_tag4_q(tagpos_hes) and not tlb_tag4_q(tagpos_esel+1) and tlb_tag4_q(tagpos_esel+2))) ) + or ( (lru_tag4_dataout_q(0 to 1) & tlb_tag4_q(tagpos_is) & lru_tag4_dataout_q(3)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+2) and not tlb_tag4_q(tagpos_hes) and tlb_tag4_q(tagpos_esel+1) and not tlb_tag4_q(tagpos_esel+2))) ) + or ( (lru_tag4_dataout_q(0 to 2) & tlb_tag4_q(tagpos_is)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+2) and not tlb_tag4_q(tagpos_hes) and tlb_tag4_q(tagpos_esel+1) and tlb_tag4_q(tagpos_esel+2))) ) + + or ( (tlb_tag4_q(tagpos_is) & lru_tag4_dataout_q(1 to 3)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+3) and not tlb_tag4_q(tagpos_hes) and not tlb_tag4_q(tagpos_esel+1) and not tlb_tag4_q(tagpos_esel+2))) ) + or ( (lru_tag4_dataout_q(0) & tlb_tag4_q(tagpos_is) & lru_tag4_dataout_q(2 to 3)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+3) and not tlb_tag4_q(tagpos_hes) and not tlb_tag4_q(tagpos_esel+1) and tlb_tag4_q(tagpos_esel+2))) ) + or ( (lru_tag4_dataout_q(0 to 1) & tlb_tag4_q(tagpos_is) & lru_tag4_dataout_q(3)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+3) and not tlb_tag4_q(tagpos_hes) and tlb_tag4_q(tagpos_esel+1) and not tlb_tag4_q(tagpos_esel+2))) ) + or ( (lru_tag4_dataout_q(0 to 2) & tlb_tag4_q(tagpos_is)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+3) and not tlb_tag4_q(tagpos_hes) and tlb_tag4_q(tagpos_esel+1) and tlb_tag4_q(tagpos_esel+2))) ); +tlb_tag4_hes1_mas1_iprot(0 TO thdid_width-1) <= + ( (tlb_tag4_q(tagpos_is+1) & lru_tag4_dataout_q(9 to 11)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+0) and tlb_tag4_q(tagpos_hes) and not lru_tag4_dataout_q(4) and not lru_tag4_dataout_q(5))) ) + or ( (lru_tag4_dataout_q(8) & tlb_tag4_q(tagpos_is+1) & lru_tag4_dataout_q(10 to 11)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+0) and tlb_tag4_q(tagpos_hes) and not lru_tag4_dataout_q(4) and lru_tag4_dataout_q(5))) ) + or ( (lru_tag4_dataout_q(8 to 9) & tlb_tag4_q(tagpos_is+1) & lru_tag4_dataout_q(11)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+0) and tlb_tag4_q(tagpos_hes) and lru_tag4_dataout_q(4) and not lru_tag4_dataout_q(6))) ) + or ( (lru_tag4_dataout_q(8 to 10) & tlb_tag4_q(tagpos_is+1)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+0) and tlb_tag4_q(tagpos_hes) and lru_tag4_dataout_q(4) and lru_tag4_dataout_q(6))) ) + + or ( (tlb_tag4_q(tagpos_is+1) & lru_tag4_dataout_q(9 to 11)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+1) and tlb_tag4_q(tagpos_hes) and not lru_tag4_dataout_q(4) and not lru_tag4_dataout_q(5))) ) + or ( (lru_tag4_dataout_q(8) & tlb_tag4_q(tagpos_is+1) & lru_tag4_dataout_q(10 to 11)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+1) and tlb_tag4_q(tagpos_hes) and not lru_tag4_dataout_q(4) and lru_tag4_dataout_q(5))) ) + or ( (lru_tag4_dataout_q(8 to 9) & tlb_tag4_q(tagpos_is+1) & lru_tag4_dataout_q(11)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+1) and tlb_tag4_q(tagpos_hes) and lru_tag4_dataout_q(4) and not lru_tag4_dataout_q(6))) ) + or ( (lru_tag4_dataout_q(8 to 10) & tlb_tag4_q(tagpos_is+1)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+1) and tlb_tag4_q(tagpos_hes) and lru_tag4_dataout_q(4) and lru_tag4_dataout_q(6))) ) + + or ( (tlb_tag4_q(tagpos_is+1) & lru_tag4_dataout_q(9 to 11)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+2) and tlb_tag4_q(tagpos_hes) and not lru_tag4_dataout_q(4) and not lru_tag4_dataout_q(5))) ) + or ( (lru_tag4_dataout_q(8) & tlb_tag4_q(tagpos_is+1) & lru_tag4_dataout_q(10 to 11)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+2) and tlb_tag4_q(tagpos_hes) and not lru_tag4_dataout_q(4) and lru_tag4_dataout_q(5))) ) + or ( (lru_tag4_dataout_q(8 to 9) & tlb_tag4_q(tagpos_is+1) & lru_tag4_dataout_q(11)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+2) and tlb_tag4_q(tagpos_hes) and lru_tag4_dataout_q(4) and not lru_tag4_dataout_q(6))) ) + or ( (lru_tag4_dataout_q(8 to 10) & tlb_tag4_q(tagpos_is+1)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+2) and tlb_tag4_q(tagpos_hes) and lru_tag4_dataout_q(4) and lru_tag4_dataout_q(6))) ) + + or ( (tlb_tag4_q(tagpos_is+1) & lru_tag4_dataout_q(9 to 11)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+3) and tlb_tag4_q(tagpos_hes) and not lru_tag4_dataout_q(4) and not lru_tag4_dataout_q(5))) ) + or ( (lru_tag4_dataout_q(8) & tlb_tag4_q(tagpos_is+1) & lru_tag4_dataout_q(10 to 11)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+3) and tlb_tag4_q(tagpos_hes) and not lru_tag4_dataout_q(4) and lru_tag4_dataout_q(5))) ) + or ( (lru_tag4_dataout_q(8 to 9) & tlb_tag4_q(tagpos_is+1) & lru_tag4_dataout_q(11)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+3) and tlb_tag4_q(tagpos_hes) and lru_tag4_dataout_q(4) and not lru_tag4_dataout_q(6))) ) + or ( (lru_tag4_dataout_q(8 to 10) & tlb_tag4_q(tagpos_is+1)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+3) and tlb_tag4_q(tagpos_hes) and lru_tag4_dataout_q(4) and lru_tag4_dataout_q(6))) ); +tlb_tag4_hes0_mas1_iprot(0 TO thdid_width-1) <= + ( (tlb_tag4_q(tagpos_is+1) & lru_tag4_dataout_q(9 to 11)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+0) and not tlb_tag4_q(tagpos_hes) and not tlb_tag4_q(tagpos_esel+1) and not tlb_tag4_q(tagpos_esel+2))) ) + or ( (lru_tag4_dataout_q(8) & tlb_tag4_q(tagpos_is+1) & lru_tag4_dataout_q(10 to 11)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+0) and not tlb_tag4_q(tagpos_hes) and not tlb_tag4_q(tagpos_esel+1) and tlb_tag4_q(tagpos_esel+2))) ) + or ( (lru_tag4_dataout_q(8 to 9) & tlb_tag4_q(tagpos_is+1) & lru_tag4_dataout_q(11)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+0) and not tlb_tag4_q(tagpos_hes) and tlb_tag4_q(tagpos_esel+1) and not tlb_tag4_q(tagpos_esel+2))) ) + or ( (lru_tag4_dataout_q(8 to 10) & tlb_tag4_q(tagpos_is+1)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+0) and not tlb_tag4_q(tagpos_hes) and tlb_tag4_q(tagpos_esel+1) and tlb_tag4_q(tagpos_esel+2))) ) + + or ( (tlb_tag4_q(tagpos_is+1) & lru_tag4_dataout_q(9 to 11)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+1) and not tlb_tag4_q(tagpos_hes) and not tlb_tag4_q(tagpos_esel+1) and not tlb_tag4_q(tagpos_esel+2))) ) + or ( (lru_tag4_dataout_q(8) & tlb_tag4_q(tagpos_is+1) & lru_tag4_dataout_q(10 to 11)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+1) and not tlb_tag4_q(tagpos_hes) and not tlb_tag4_q(tagpos_esel+1) and tlb_tag4_q(tagpos_esel+2))) ) + or ( (lru_tag4_dataout_q(8 to 9) & tlb_tag4_q(tagpos_is+1) & lru_tag4_dataout_q(11)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+1) and not tlb_tag4_q(tagpos_hes) and tlb_tag4_q(tagpos_esel+1) and not tlb_tag4_q(tagpos_esel+2))) ) + or ( (lru_tag4_dataout_q(8 to 10) & tlb_tag4_q(tagpos_is+1)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+1) and not tlb_tag4_q(tagpos_hes) and tlb_tag4_q(tagpos_esel+1) and tlb_tag4_q(tagpos_esel+2))) ) + + or ( (tlb_tag4_q(tagpos_is+1) & lru_tag4_dataout_q(9 to 11)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+2) and not tlb_tag4_q(tagpos_hes) and not tlb_tag4_q(tagpos_esel+1) and not tlb_tag4_q(tagpos_esel+2))) ) + or ( (lru_tag4_dataout_q(8) & tlb_tag4_q(tagpos_is+1) & lru_tag4_dataout_q(10 to 11)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+2) and not tlb_tag4_q(tagpos_hes) and not tlb_tag4_q(tagpos_esel+1) and tlb_tag4_q(tagpos_esel+2))) ) + or ( (lru_tag4_dataout_q(8 to 9) & tlb_tag4_q(tagpos_is+1) & lru_tag4_dataout_q(11)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+2) and not tlb_tag4_q(tagpos_hes) and tlb_tag4_q(tagpos_esel+1) and not tlb_tag4_q(tagpos_esel+2))) ) + or ( (lru_tag4_dataout_q(8 to 10) & tlb_tag4_q(tagpos_is+1)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+2) and not tlb_tag4_q(tagpos_hes) and tlb_tag4_q(tagpos_esel+1) and tlb_tag4_q(tagpos_esel+2))) ) + + or ( (tlb_tag4_q(tagpos_is+1) & lru_tag4_dataout_q(9 to 11)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+3) and not tlb_tag4_q(tagpos_hes) and not tlb_tag4_q(tagpos_esel+1) and not tlb_tag4_q(tagpos_esel+2))) ) + or ( (lru_tag4_dataout_q(8) & tlb_tag4_q(tagpos_is+1) & lru_tag4_dataout_q(10 to 11)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+3) and not tlb_tag4_q(tagpos_hes) and not tlb_tag4_q(tagpos_esel+1) and tlb_tag4_q(tagpos_esel+2))) ) + or ( (lru_tag4_dataout_q(8 to 9) & tlb_tag4_q(tagpos_is+1) & lru_tag4_dataout_q(11)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+3) and not tlb_tag4_q(tagpos_hes) and tlb_tag4_q(tagpos_esel+1) and not tlb_tag4_q(tagpos_esel+2))) ) + or ( (lru_tag4_dataout_q(8 to 10) & tlb_tag4_q(tagpos_is+1)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+3) and not tlb_tag4_q(tagpos_hes) and tlb_tag4_q(tagpos_esel+1) and tlb_tag4_q(tagpos_esel+2))) ); +tlb_tag4_ptereload_v(0 TO thdid_width-1) <= (ptereload_req_pte_lat(ptepos_valid) & lru_tag4_dataout_q(1 to 3)) + when (lru_tag4_dataout_q(4 to 5)="00") + else (lru_tag4_dataout_q(0) & ptereload_req_pte_lat(ptepos_valid) & lru_tag4_dataout_q(2 to 3)) + when (lru_tag4_dataout_q(4 to 5)="01") + else (lru_tag4_dataout_q(0 to 1) & ptereload_req_pte_lat(ptepos_valid) & lru_tag4_dataout_q(3)) + when (lru_tag4_dataout_q(4)='1' and lru_tag4_dataout_q(6)='0') + else (lru_tag4_dataout_q(0 to 2) & ptereload_req_pte_lat(ptepos_valid)) + when (lru_tag4_dataout_q(4)='1' and lru_tag4_dataout_q(6)='1') + else lru_tag4_dataout_q(0 to 3); +tlb_tag4_ptereload_iprot(0 TO thdid_width-1) <= ('0' & lru_tag4_dataout_q(9 to 11)) + when (lru_tag4_dataout_q(4 to 5)="00") + else (lru_tag4_dataout_q(8) & '0' & lru_tag4_dataout_q(10 to 11)) + when (lru_tag4_dataout_q(4 to 5)="01") + else (lru_tag4_dataout_q(8 to 9) & '0' & lru_tag4_dataout_q(11)) + when (lru_tag4_dataout_q(4)='1' and lru_tag4_dataout_q(6)='0') + else (lru_tag4_dataout_q(8 to 10) & '0') + when (lru_tag4_dataout_q(4)='1' and lru_tag4_dataout_q(6)='1') + else lru_tag4_dataout_q(8 to 11); +lru_write_d <= (others => '1') when ( (tlb_tag4_q(tagpos_type_derat)='1' or tlb_tag4_q(tagpos_type_ierat)='1') + and tlb_tag4_q(tagpos_type_ptereload)='0' + and tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000" + and ((tlb_tag4_wayhit_q(0 to 3) /= "0000" and multihit='0') or + (xu_mm_xucr4_mmu_mchk_q='0' and xu_mm_ccr2_notlb_b='1' and (multihit='1' or or_reduce(tag4_parerr_q(0 to 4))='1'))) ) + else (others => '1') when ( tlb_tag4_q(tagpos_type_snoop)='1' + and tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000" + and (tlb_tag4_wayhit_q(0 to 3) /= "0000" or tlb_tag4_q(tagpos_is+1 to tagpos_is+3)="000") ) + else (others => '1') when ( tlb_tag4_q(tagpos_type_tlbwe)='1' and tlb_tag4_q(tagpos_pr)='0' and ex6_illeg_instr(1)='0' + and (tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not tlb_ctl_tag4_flush)/="0000" + and ((or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and tlb_resv_match_vec)='1' + and tlb_tag4_q(tagpos_wq to tagpos_wq+1)="01" and mmucfg_twc='1') + or tlb_tag4_q(tagpos_wq to tagpos_wq+1)="00" or tlb_tag4_q(tagpos_wq to tagpos_wq+1)="11") + and ((tlb_tag4_q(tagpos_gs)='0' and tlb_tag4_q(tagpos_atsel)='0') or + (tlb_tag4_q(tagpos_gs)='1' and tlb_tag4_q(tagpos_hes)='1' and tlb_tag4_q(tagpos_is+1)='0' + and tlb0cfg_gtwe='1' and tlb_tag4_epcr_dgtmi='0' and lrat_tag4_hit_status="1100" + and (((lru_tag4_dataout_q(0)='0' or lru_tag4_dataout_q(8)='0') and lru_tag4_dataout_q(4 to 5)="00") + or ((lru_tag4_dataout_q(1)='0' or lru_tag4_dataout_q(9)='0') and lru_tag4_dataout_q(4 to 5)="01") + or ((lru_tag4_dataout_q(2)='0' or lru_tag4_dataout_q(10)='0') and lru_tag4_dataout_q(4)='1' and lru_tag4_dataout_q(6)='0') + or ((lru_tag4_dataout_q(3)='0' or lru_tag4_dataout_q(11)='0') and lru_tag4_dataout_q(4)='1' and lru_tag4_dataout_q(6)='1')))) ) + else (others => ptereload_req_pte_lat(ptepos_valid)) when ( tlb_tag4_q(tagpos_type_ptereload)='1' + and (tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000") + and (tlb_tag4_q(tagpos_gs)='0' or (tlb_tag4_q(tagpos_gs)='1' and lrat_tag4_hit_status="1100")) + and (tlb_tag4_q(tagpos_wq to tagpos_wq+1)="10") + and (tlb_tag4_q(tagpos_pt)='1') + and (((lru_tag4_dataout_q(0)='0' or lru_tag4_dataout_q(8)='0') and lru_tag4_dataout_q(4 to 5)="00") + or ((lru_tag4_dataout_q(1)='0' or lru_tag4_dataout_q(9)='0') and lru_tag4_dataout_q(4 to 5)="01") + or ((lru_tag4_dataout_q(2)='0' or lru_tag4_dataout_q(10)='0') and lru_tag4_dataout_q(4)='1' and lru_tag4_dataout_q(6)='0') + or ((lru_tag4_dataout_q(3)='0' or lru_tag4_dataout_q(11)='0') and lru_tag4_dataout_q(4)='1' and lru_tag4_dataout_q(6)='1')) ) + else (others => '0'); +lru_wr_addr_d <= tlb_addr4_q; +lru_update_clear_enab <= '1' when ( xu_mm_xucr4_mmu_mchk_q='0' and xu_mm_ccr2_notlb_b='1' and + ((tlb_tag4_q(tagpos_type_derat)='1' or tlb_tag4_q(tagpos_type_ierat)='1') and tlb_tag4_q(tagpos_type_ptereload)='0') and + (multihit='1' or or_reduce(tag4_parerr_q(0 to 4))='1') ) + else '0'; +lru_update_data_enab <= '1' when ( ((tlb_tag4_q(tagpos_type_derat)='1' or tlb_tag4_q(tagpos_type_ierat)='1') and tlb_tag4_q(tagpos_type_ptereload)='0' and + multihit='0' and or_reduce(tag4_parerr_q(0 to 4))='0') + or (tlb_tag4_q(tagpos_type_tlbwe)='1' and (tlb_tag4_q(tagpos_atsel)='0' or tlb_tag4_q(tagpos_gs)='1')) + or (tlb_tag4_q(tagpos_type_ptereload)='1') + or (tlb_tag4_q(tagpos_type_snoop)='1') ) + else '0'; +lru_datain_d(0 TO 3) <= (others => '0') when lru_update_clear_enab='1' + else ( lru_tag4_dataout_q(0 to 3) and + (lru_tag4_dataout_q(8 to 11) or not(tlb_tag4_wayhit_q(0 to 3))) ) + when tlb_tag4_q(tagpos_type_snoop)='1' + else tlb_tag4_hes1_mas1_v(0 to thdid_width-1) + when tlb_tag4_q(tagpos_type_tlbwe)='1' and tlb_tag4_q(tagpos_hes)='1' + else tlb_tag4_hes0_mas1_v(0 to thdid_width-1) + when tlb_tag4_q(tagpos_type_tlbwe)='1' and tlb_tag4_q(tagpos_hes)='0' + else tlb_tag4_ptereload_v(0 to thdid_width-1) + when tlb_tag4_q(tagpos_type_ptereload)='1' + else lru_tag4_dataout_q(0 to 3); +lru_datain_d(4 TO 6) <= (others => '0') when lru_update_clear_enab='1' + else lru_update_data when lru_update_data_enab='1' + else lru_tag4_dataout_q(4 to 6); +lru_datain_alt_d(4 TO 6) <= lru_update_data_alt when ((tlb_tag4_q(tagpos_type_derat)='1' or tlb_tag4_q(tagpos_type_ierat)='1' or + tlb_tag4_q(tagpos_type_snoop)='1') and tlb_tag4_q(tagpos_type_ptereload)='0') + else lru_update_data when (tlb_tag4_q(tagpos_type_tlbwe)='1' and (tlb_tag4_q(tagpos_atsel)='0' or tlb_tag4_q(tagpos_gs)='1')) + else lru_update_data when (tlb_tag4_q(tagpos_type_ptereload)='1') + else lru_tag4_dataout_q(4 to 6); +lru_update_data_alt <= (lru_tag4_dataout_q(4 to 6) and (4 to 6 => not tlb_tag4_wayhit_q(4))) or + (lru_update_data_snoophit_eco and (4 to 6 => tlb_tag4_wayhit_q(4) and tlb_tag4_q(tagpos_type_snoop))) or + (lru_update_data_erathit_eco and (4 to 6 => tlb_tag4_wayhit_q(4) and not tlb_tag4_q(tagpos_type_ptereload) + and (tlb_tag4_q(tagpos_type_derat) or tlb_tag4_q(tagpos_type_ierat)))); +lru_datain_alt_d(7) <= xor_reduce(lru_datain_d(0 to 3) & lru_datain_alt_d(4 to 6)); +lru_update_data_snoophit_eco(0 TO 2) <= "000" when (tlb_tag4_wayhit_q(0) and not lru_tag4_dataout_q(6) and not lru_tag4_dataout_q(8))='1' + else "001" when (tlb_tag4_wayhit_q(0) and lru_tag4_dataout_q(6) and not lru_tag4_dataout_q(8))='1' + else "010" when (tlb_tag4_wayhit_q(1) and not lru_tag4_dataout_q(6) and not lru_tag4_dataout_q(9))='1' + else "011" when (tlb_tag4_wayhit_q(1) and lru_tag4_dataout_q(6) and not lru_tag4_dataout_q(9))='1' + else "100" when (tlb_tag4_wayhit_q(2) and not lru_tag4_dataout_q(5) and not lru_tag4_dataout_q(10))='1' + else "110" when (tlb_tag4_wayhit_q(2) and lru_tag4_dataout_q(5) and not lru_tag4_dataout_q(10))='1' + else "101" when (tlb_tag4_wayhit_q(3) and not lru_tag4_dataout_q(5) and not lru_tag4_dataout_q(11))='1' + else "111" when (tlb_tag4_wayhit_q(3) and lru_tag4_dataout_q(5) and not lru_tag4_dataout_q(11))='1' + else lru_tag4_dataout_q(4 to 6); +lru_datain_alt_d(8) <= xor_reduce(lru_datain_d(0 to 3) & lru_update_data_snoophit_eco(0 to 2)); +lru_update_data_erathit_eco(0 TO 2) <= "01" & lru_tag4_dataout_q(6) when (tlb_tag4_wayhit_q(0) and not lru_tag4_dataout_q(9))='1' + else '1' & lru_tag4_dataout_q(5) & '0' when (tlb_tag4_wayhit_q(0) and not lru_tag4_dataout_q(10))='1' + else '1' & lru_tag4_dataout_q(5) & '1' when (tlb_tag4_wayhit_q(0) and not lru_tag4_dataout_q(11))='1' + else '1' & lru_tag4_dataout_q(5) & '0' when (tlb_tag4_wayhit_q(1) and not lru_tag4_dataout_q(10))='1' + else '1' & lru_tag4_dataout_q(5) & '1' when (tlb_tag4_wayhit_q(1) and not lru_tag4_dataout_q(11))='1' + else "00" & lru_tag4_dataout_q(6) when (tlb_tag4_wayhit_q(1) and not lru_tag4_dataout_q(8))='1' + else '1' & lru_tag4_dataout_q(5) & '1' when (tlb_tag4_wayhit_q(2) and not lru_tag4_dataout_q(11))='1' + else "00" & lru_tag4_dataout_q(6) when (tlb_tag4_wayhit_q(2) and not lru_tag4_dataout_q(8))='1' + else "01" & lru_tag4_dataout_q(6) when (tlb_tag4_wayhit_q(2) and not lru_tag4_dataout_q(9))='1' + else "00" & lru_tag4_dataout_q(6) when (tlb_tag4_wayhit_q(3) and not lru_tag4_dataout_q(8))='1' + else "01" & lru_tag4_dataout_q(6) when (tlb_tag4_wayhit_q(3) and not lru_tag4_dataout_q(9))='1' + else '1' & lru_tag4_dataout_q(5) & '0' when (tlb_tag4_wayhit_q(3) and not lru_tag4_dataout_q(10))='1' + else lru_tag4_dataout_q(4 to 6); +lru_datain_alt_d(9) <= xor_reduce(lru_datain_d(0 to 3) & lru_update_data_erathit_eco(0 to 2)); +lru_datain_d(8 TO 11) <= (others => '0') when lru_update_clear_enab='1' + else tlb_tag4_hes1_mas1_iprot(0 to thdid_width-1) + when tlb_tag4_q(tagpos_type_tlbwe)='1' and tlb_tag4_q(tagpos_hes)='1' + else tlb_tag4_hes0_mas1_iprot(0 to thdid_width-1) + when tlb_tag4_q(tagpos_type_tlbwe)='1' and tlb_tag4_q(tagpos_hes)='0' + else tlb_tag4_ptereload_iprot(0 to thdid_width-1) + when tlb_tag4_q(tagpos_type_ptereload)='1' + else lru_tag4_dataout_q(8 to 11); +lru_datain_d(12 TO 14) <= (others => '0'); +lru_datain_d(7) <= xor_reduce(lru_datain_d(0 to 6)); +lru_datain_d(15) <= xor_reduce(lru_datain_d(8 to 14) & mmucr1_q(pos_lru_pei)); +lru_calc_par(0) <= xor_reduce(lru_tag3_dataout_q(0 to 6)); +lru_calc_par(1) <= xor_reduce(lru_tag3_dataout_q(8 to 14)); +tag4_parerr_d(4) <= or_reduce(lru_calc_par(0 to 1) xor (lru_tag3_dataout_q(7) & lru_tag3_dataout_q(15))); +tlb_tag4_parerr_enab <= or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1)) and + (or_reduce(tlb_tag4_q(tagpos_type_derat to tagpos_type_tlbsrx)) or tlb_tag4_q(tagpos_type_tlbre)); +MQQ1:LRU_UPDATE_DATA_PT(1) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_WAYHIT_Q(3) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(8) & + LRU_TAG4_DATAOUT_Q(9) & LRU_TAG4_DATAOUT_Q(10) & + LRU_TAG4_DATAOUT_Q(11) ) , STD_ULOGIC_VECTOR'("011111110")); +MQQ2:LRU_UPDATE_DATA_PT(2) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_WAYHIT_Q(0) & + TLB_TAG4_WAYHIT_Q(3) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(9) & LRU_TAG4_DATAOUT_Q(10) & + LRU_TAG4_DATAOUT_Q(11) ) , STD_ULOGIC_VECTOR'("101111110")); +MQQ3:LRU_UPDATE_DATA_PT(3) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(3) & + LRU_TAG4_DATAOUT_Q(4) & LRU_TAG4_DATAOUT_Q(10) & + LRU_TAG4_DATAOUT_Q(11) ) , STD_ULOGIC_VECTOR'("111111010")); +MQQ4:LRU_UPDATE_DATA_PT(4) <= + Eq(( TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(3) & + LRU_TAG4_DATAOUT_Q(4) & LRU_TAG4_DATAOUT_Q(10) & + LRU_TAG4_DATAOUT_Q(11) ) , STD_ULOGIC_VECTOR'("1111010")); +MQQ5:LRU_UPDATE_DATA_PT(5) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_TYPE_SIG(6) & + TLB_TAG4_TYPE_SIG(7) & TLB_TAG4_WAYHIT_Q(0) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(3) & + LRU_TAG4_DATAOUT_Q(10) & LRU_TAG4_DATAOUT_Q(11) + ) , STD_ULOGIC_VECTOR'("0001111110")); +MQQ6:LRU_UPDATE_DATA_PT(6) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & TLB_TAG4_ESEL_SIG(2) & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(3) & + LRU_TAG4_DATAOUT_Q(10) & LRU_TAG4_DATAOUT_Q(11) + ) , STD_ULOGIC_VECTOR'("1000111110")); +MQQ7:LRU_UPDATE_DATA_PT(7) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_WAYHIT_Q(0) & + TLB_TAG4_WAYHIT_Q(1) & TLB_TAG4_WAYHIT_Q(3) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(10) & + LRU_TAG4_DATAOUT_Q(11) ) , STD_ULOGIC_VECTOR'("100111110")); +MQQ8:LRU_UPDATE_DATA_PT(8) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_TYPE_SIG(6) & + TLB_TAG4_TYPE_SIG(7) & TLB_TAG4_WAYHIT_Q(1) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(10) & + LRU_TAG4_DATAOUT_Q(11) ) , STD_ULOGIC_VECTOR'("000111110")); +MQQ9:LRU_UPDATE_DATA_PT(9) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & TLB_TAG4_ESEL_SIG(2) & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(10) & + LRU_TAG4_DATAOUT_Q(11) ) , STD_ULOGIC_VECTOR'("100111110")); +MQQ10:LRU_UPDATE_DATA_PT(10) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_TYPE_SIG(6) & + TLB_TAG4_TYPE_SIG(7) & TLB_TAG4_WAYHIT_Q(2) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(8) & + LRU_TAG4_DATAOUT_Q(9) & LRU_TAG4_DATAOUT_Q(11) + ) , STD_ULOGIC_VECTOR'("0001111110")); +MQQ11:LRU_UPDATE_DATA_PT(11) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(3) & + LRU_TAG4_DATAOUT_Q(4) & LRU_TAG4_DATAOUT_Q(6) & + LRU_TAG4_DATAOUT_Q(11) ) , STD_ULOGIC_VECTOR'("111111100")); +MQQ12:LRU_UPDATE_DATA_PT(12) <= + Eq(( TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(3) & + LRU_TAG4_DATAOUT_Q(4) & LRU_TAG4_DATAOUT_Q(6) & + LRU_TAG4_DATAOUT_Q(11) ) , STD_ULOGIC_VECTOR'("1111100")); +MQQ13:LRU_UPDATE_DATA_PT(13) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(3) & + LRU_TAG4_DATAOUT_Q(4) & LRU_TAG4_DATAOUT_Q(6) & + LRU_TAG4_DATAOUT_Q(11) ) , STD_ULOGIC_VECTOR'("1111010")); +MQQ14:LRU_UPDATE_DATA_PT(14) <= + Eq(( TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(3) & LRU_TAG4_DATAOUT_Q(4) & + LRU_TAG4_DATAOUT_Q(6) & LRU_TAG4_DATAOUT_Q(11) + ) , STD_ULOGIC_VECTOR'("111010")); +MQQ15:LRU_UPDATE_DATA_PT(15) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(6) & LRU_TAG4_DATAOUT_Q(11) + ) , STD_ULOGIC_VECTOR'("11110110")); +MQQ16:LRU_UPDATE_DATA_PT(16) <= + Eq(( TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(6) & LRU_TAG4_DATAOUT_Q(11) + ) , STD_ULOGIC_VECTOR'("110110")); +MQQ17:LRU_UPDATE_DATA_PT(17) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(6) & LRU_TAG4_DATAOUT_Q(11) + ) , STD_ULOGIC_VECTOR'("11101110")); +MQQ18:LRU_UPDATE_DATA_PT(18) <= + Eq(( TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(6) & LRU_TAG4_DATAOUT_Q(11) + ) , STD_ULOGIC_VECTOR'("101110")); +MQQ19:LRU_UPDATE_DATA_PT(19) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_TYPE_SIG(6) & + TLB_TAG4_TYPE_SIG(7) & TLB_TAG4_WAYHIT_Q(3) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(6) & + LRU_TAG4_DATAOUT_Q(11) ) , STD_ULOGIC_VECTOR'("0000110")); +MQQ20:LRU_UPDATE_DATA_PT(20) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(6) & LRU_TAG4_DATAOUT_Q(11) + ) , STD_ULOGIC_VECTOR'("100110")); +MQQ21:LRU_UPDATE_DATA_PT(21) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(3) & LRU_TAG4_DATAOUT_Q(4) & + LRU_TAG4_DATAOUT_Q(5) & LRU_TAG4_DATAOUT_Q(11) + ) , STD_ULOGIC_VECTOR'("1111111000")); +MQQ22:LRU_UPDATE_DATA_PT(22) <= + Eq(( TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(3) & LRU_TAG4_DATAOUT_Q(4) & + LRU_TAG4_DATAOUT_Q(5) & LRU_TAG4_DATAOUT_Q(11) + ) , STD_ULOGIC_VECTOR'("11111000")); +MQQ23:LRU_UPDATE_DATA_PT(23) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(11) ) , STD_ULOGIC_VECTOR'("1111100")); +MQQ24:LRU_UPDATE_DATA_PT(24) <= + Eq(( TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(11) ) , STD_ULOGIC_VECTOR'("11100")); +MQQ25:LRU_UPDATE_DATA_PT(25) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_WAYHIT_Q(0) & + TLB_TAG4_WAYHIT_Q(1) & TLB_TAG4_WAYHIT_Q(2) & + TLB_TAG4_WAYHIT_Q(3) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(11) ) , STD_ULOGIC_VECTOR'("100011110")); +MQQ26:LRU_UPDATE_DATA_PT(26) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & TLB_TAG4_ESEL_SIG(2) & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(11) + ) , STD_ULOGIC_VECTOR'("10101110")); +MQQ27:LRU_UPDATE_DATA_PT(27) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_WAYHIT_Q(1) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(3) & LRU_TAG4_DATAOUT_Q(8) & + LRU_TAG4_DATAOUT_Q(9) & LRU_TAG4_DATAOUT_Q(10) & + LRU_TAG4_DATAOUT_Q(11) ) , STD_ULOGIC_VECTOR'("011111011")); +MQQ28:LRU_UPDATE_DATA_PT(28) <= + Eq(( TLB_TAG4_HES_SIG & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(5) & LRU_TAG4_DATAOUT_Q(8) & + LRU_TAG4_DATAOUT_Q(10) & LRU_TAG4_DATAOUT_Q(11) + ) , STD_ULOGIC_VECTOR'("111111")); +MQQ29:LRU_UPDATE_DATA_PT(29) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(5) & LRU_TAG4_DATAOUT_Q(8) & + LRU_TAG4_DATAOUT_Q(10) & LRU_TAG4_DATAOUT_Q(11) + ) , STD_ULOGIC_VECTOR'("011111")); +MQQ30:LRU_UPDATE_DATA_PT(30) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & TLB_TAG4_ESEL_SIG(2) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(3) & LRU_TAG4_DATAOUT_Q(8) & + LRU_TAG4_DATAOUT_Q(10) & LRU_TAG4_DATAOUT_Q(11) + ) , STD_ULOGIC_VECTOR'("1001111111")); +MQQ31:LRU_UPDATE_DATA_PT(31) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_WAYHIT_Q(2) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(8) & LRU_TAG4_DATAOUT_Q(9) & + LRU_TAG4_DATAOUT_Q(10) ) , STD_ULOGIC_VECTOR'("0111110")); +MQQ32:LRU_UPDATE_DATA_PT(32) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_WAYHIT_Q(0) & + TLB_TAG4_WAYHIT_Q(2) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(9) & + LRU_TAG4_DATAOUT_Q(10) ) , STD_ULOGIC_VECTOR'("1011110")); +MQQ33:LRU_UPDATE_DATA_PT(33) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(3) & LRU_TAG4_DATAOUT_Q(4) & + LRU_TAG4_DATAOUT_Q(5) & LRU_TAG4_DATAOUT_Q(10) + ) , STD_ULOGIC_VECTOR'("1111111000")); +MQQ34:LRU_UPDATE_DATA_PT(34) <= + Eq(( TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(3) & LRU_TAG4_DATAOUT_Q(4) & + LRU_TAG4_DATAOUT_Q(5) & LRU_TAG4_DATAOUT_Q(10) + ) , STD_ULOGIC_VECTOR'("11111000")); +MQQ35:LRU_UPDATE_DATA_PT(35) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(3) & + LRU_TAG4_DATAOUT_Q(4) & LRU_TAG4_DATAOUT_Q(10) + ) , STD_ULOGIC_VECTOR'("11111100")); +MQQ36:LRU_UPDATE_DATA_PT(36) <= + Eq(( TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(3) & + LRU_TAG4_DATAOUT_Q(4) & LRU_TAG4_DATAOUT_Q(10) + ) , STD_ULOGIC_VECTOR'("111100")); +MQQ37:LRU_UPDATE_DATA_PT(37) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_TYPE_SIG(6) & + TLB_TAG4_TYPE_SIG(7) & TLB_TAG4_WAYHIT_Q(0) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(3) & + LRU_TAG4_DATAOUT_Q(10) ) , STD_ULOGIC_VECTOR'("000111110")); +MQQ38:LRU_UPDATE_DATA_PT(38) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & TLB_TAG4_ESEL_SIG(2) & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(3) & + LRU_TAG4_DATAOUT_Q(10) ) , STD_ULOGIC_VECTOR'("100011110")); +MQQ39:LRU_UPDATE_DATA_PT(39) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(10) + ) , STD_ULOGIC_VECTOR'("111100")); +MQQ40:LRU_UPDATE_DATA_PT(40) <= + Eq(( TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(10) + ) , STD_ULOGIC_VECTOR'("1100")); +MQQ41:LRU_UPDATE_DATA_PT(41) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(10) + ) , STD_ULOGIC_VECTOR'("111010")); +MQQ42:LRU_UPDATE_DATA_PT(42) <= + Eq(( TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(10) + ) , STD_ULOGIC_VECTOR'("1010")); +MQQ43:LRU_UPDATE_DATA_PT(43) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_WAYHIT_Q(0) & + TLB_TAG4_WAYHIT_Q(1) & TLB_TAG4_WAYHIT_Q(2) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(10) ) , STD_ULOGIC_VECTOR'("1001110")); +MQQ44:LRU_UPDATE_DATA_PT(44) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_TYPE_SIG(6) & + TLB_TAG4_TYPE_SIG(7) & TLB_TAG4_WAYHIT_Q(1) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(10) ) , STD_ULOGIC_VECTOR'("0001110")); +MQQ45:LRU_UPDATE_DATA_PT(45) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & TLB_TAG4_ESEL_SIG(2) & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(10) ) , STD_ULOGIC_VECTOR'("1001110")); +MQQ46:LRU_UPDATE_DATA_PT(46) <= + Eq(( TLB_TAG4_HES_SIG & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(6) & LRU_TAG4_DATAOUT_Q(8) & + LRU_TAG4_DATAOUT_Q(9) & LRU_TAG4_DATAOUT_Q(10) + ) , STD_ULOGIC_VECTOR'("111111")); +MQQ47:LRU_UPDATE_DATA_PT(47) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(6) & LRU_TAG4_DATAOUT_Q(8) & + LRU_TAG4_DATAOUT_Q(9) & LRU_TAG4_DATAOUT_Q(10) + ) , STD_ULOGIC_VECTOR'("011111")); +MQQ48:LRU_UPDATE_DATA_PT(48) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & TLB_TAG4_ESEL_SIG(2) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(8) & + LRU_TAG4_DATAOUT_Q(9) & LRU_TAG4_DATAOUT_Q(10) + ) , STD_ULOGIC_VECTOR'("1011111111")); +MQQ49:LRU_UPDATE_DATA_PT(49) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(4) & + LRU_TAG4_DATAOUT_Q(6) & LRU_TAG4_DATAOUT_Q(10) + ) , STD_ULOGIC_VECTOR'("111011")); +MQQ50:LRU_UPDATE_DATA_PT(50) <= + Eq(( TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(4) & LRU_TAG4_DATAOUT_Q(6) & + LRU_TAG4_DATAOUT_Q(10) ) , STD_ULOGIC_VECTOR'("11011")); +MQQ51:LRU_UPDATE_DATA_PT(51) <= + Eq(( LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(6) & LRU_TAG4_DATAOUT_Q(10) + ) , STD_ULOGIC_VECTOR'("0111")); +MQQ52:LRU_UPDATE_DATA_PT(52) <= + Eq(( LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(6) & LRU_TAG4_DATAOUT_Q(10) + ) , STD_ULOGIC_VECTOR'("0111")); +MQQ53:LRU_UPDATE_DATA_PT(53) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_TYPE_SIG(7) & + TLB_TAG4_WAYHIT_Q(3) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(6) & LRU_TAG4_DATAOUT_Q(10) + ) , STD_ULOGIC_VECTOR'("000111")); +MQQ54:LRU_UPDATE_DATA_PT(54) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_TYPE_SIG(7) & + TLB_TAG4_WAYHIT_Q(2) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(6) & LRU_TAG4_DATAOUT_Q(10) + ) , STD_ULOGIC_VECTOR'("001111")); +MQQ55:LRU_UPDATE_DATA_PT(55) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(6) & LRU_TAG4_DATAOUT_Q(10) + ) , STD_ULOGIC_VECTOR'("100111")); +MQQ56:LRU_UPDATE_DATA_PT(56) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_WAYHIT_Q(0) & + TLB_TAG4_WAYHIT_Q(1) & TLB_TAG4_WAYHIT_Q(2) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(3) & + LRU_TAG4_DATAOUT_Q(10) ) , STD_ULOGIC_VECTOR'("100111101")); +MQQ57:LRU_UPDATE_DATA_PT(57) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(3) & + LRU_TAG4_DATAOUT_Q(10) ) , STD_ULOGIC_VECTOR'("1111101")); +MQQ58:LRU_UPDATE_DATA_PT(58) <= + Eq(( TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(3) & + LRU_TAG4_DATAOUT_Q(10) ) , STD_ULOGIC_VECTOR'("11101")); +MQQ59:LRU_UPDATE_DATA_PT(59) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(4) & LRU_TAG4_DATAOUT_Q(8) & + LRU_TAG4_DATAOUT_Q(9) ) , STD_ULOGIC_VECTOR'("1111110")); +MQQ60:LRU_UPDATE_DATA_PT(60) <= + Eq(( TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(4) & LRU_TAG4_DATAOUT_Q(8) & + LRU_TAG4_DATAOUT_Q(9) ) , STD_ULOGIC_VECTOR'("11110")); +MQQ61:LRU_UPDATE_DATA_PT(61) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_TYPE_SIG(6) & + TLB_TAG4_TYPE_SIG(7) & TLB_TAG4_WAYHIT_Q(2) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(3) & + LRU_TAG4_DATAOUT_Q(8) & LRU_TAG4_DATAOUT_Q(9) + ) , STD_ULOGIC_VECTOR'("0001111110")); +MQQ62:LRU_UPDATE_DATA_PT(62) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_TYPE_SIG(6) & + TLB_TAG4_TYPE_SIG(7) & TLB_TAG4_WAYHIT_Q(3) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(3) & LRU_TAG4_DATAOUT_Q(8) & + LRU_TAG4_DATAOUT_Q(9) ) , STD_ULOGIC_VECTOR'("000111110")); +MQQ63:LRU_UPDATE_DATA_PT(63) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_WAYHIT_Q(1) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(3) & LRU_TAG4_DATAOUT_Q(8) & + LRU_TAG4_DATAOUT_Q(9) ) , STD_ULOGIC_VECTOR'("1111110")); +MQQ64:LRU_UPDATE_DATA_PT(64) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & TLB_TAG4_ESEL_SIG(2) & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(3) & + LRU_TAG4_DATAOUT_Q(8) & LRU_TAG4_DATAOUT_Q(9) + ) , STD_ULOGIC_VECTOR'("1010111110")); +MQQ65:LRU_UPDATE_DATA_PT(65) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & TLB_TAG4_ESEL_SIG(2) & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(8) & + LRU_TAG4_DATAOUT_Q(9) ) , STD_ULOGIC_VECTOR'("101111110")); +MQQ66:LRU_UPDATE_DATA_PT(66) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(3) & LRU_TAG4_DATAOUT_Q(4) & + LRU_TAG4_DATAOUT_Q(6) & LRU_TAG4_DATAOUT_Q(9) + ) , STD_ULOGIC_VECTOR'("1111111100")); +MQQ67:LRU_UPDATE_DATA_PT(67) <= + Eq(( TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(3) & LRU_TAG4_DATAOUT_Q(4) & + LRU_TAG4_DATAOUT_Q(6) & LRU_TAG4_DATAOUT_Q(9) + ) , STD_ULOGIC_VECTOR'("11111100")); +MQQ68:LRU_UPDATE_DATA_PT(68) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_TYPE_SIG(7) & + TLB_TAG4_WAYHIT_Q(0) & TLB_TAG4_WAYHIT_Q(1) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(6) & + LRU_TAG4_DATAOUT_Q(9) ) , STD_ULOGIC_VECTOR'("0011110")); +MQQ69:LRU_UPDATE_DATA_PT(69) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_WAYHIT_Q(0) & + TLB_TAG4_WAYHIT_Q(1) & LRU_TAG4_DATAOUT_Q(6) & + LRU_TAG4_DATAOUT_Q(9) ) , STD_ULOGIC_VECTOR'("10110")); +MQQ70:LRU_UPDATE_DATA_PT(70) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(3) & + LRU_TAG4_DATAOUT_Q(4) & LRU_TAG4_DATAOUT_Q(5) & + LRU_TAG4_DATAOUT_Q(9) ) , STD_ULOGIC_VECTOR'("111111000")); +MQQ71:LRU_UPDATE_DATA_PT(71) <= + Eq(( TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(3) & + LRU_TAG4_DATAOUT_Q(4) & LRU_TAG4_DATAOUT_Q(5) & + LRU_TAG4_DATAOUT_Q(9) ) , STD_ULOGIC_VECTOR'("1111000")); +MQQ72:LRU_UPDATE_DATA_PT(72) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(4) & LRU_TAG4_DATAOUT_Q(5) & + LRU_TAG4_DATAOUT_Q(9) ) , STD_ULOGIC_VECTOR'("1111110")); +MQQ73:LRU_UPDATE_DATA_PT(73) <= + Eq(( TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(4) & LRU_TAG4_DATAOUT_Q(5) & + LRU_TAG4_DATAOUT_Q(9) ) , STD_ULOGIC_VECTOR'("11110")); +MQQ74:LRU_UPDATE_DATA_PT(74) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_IS_SIG(0) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(3) & LRU_TAG4_DATAOUT_Q(5) & + LRU_TAG4_DATAOUT_Q(9) ) , STD_ULOGIC_VECTOR'("0111010")); +MQQ75:LRU_UPDATE_DATA_PT(75) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_TYPE_SIG(6) & + TLB_TAG4_TYPE_SIG(7) & TLB_TAG4_WAYHIT_Q(1) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(5) & + LRU_TAG4_DATAOUT_Q(9) ) , STD_ULOGIC_VECTOR'("0000110")); +MQQ76:LRU_UPDATE_DATA_PT(76) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(5) & LRU_TAG4_DATAOUT_Q(9) + ) , STD_ULOGIC_VECTOR'("101110")); +MQQ77:LRU_UPDATE_DATA_PT(77) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_TYPE_SIG(6) & + TLB_TAG4_TYPE_SIG(7) & TLB_TAG4_WAYHIT_Q(0) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(3) & LRU_TAG4_DATAOUT_Q(9) + ) , STD_ULOGIC_VECTOR'("00011110")); +MQQ78:LRU_UPDATE_DATA_PT(78) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & TLB_TAG4_ESEL_SIG(2) & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(3) & LRU_TAG4_DATAOUT_Q(9) + ) , STD_ULOGIC_VECTOR'("10001110")); +MQQ79:LRU_UPDATE_DATA_PT(79) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(9) ) , STD_ULOGIC_VECTOR'("11100")); +MQQ80:LRU_UPDATE_DATA_PT(80) <= + Eq(( TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(9) ) , STD_ULOGIC_VECTOR'("100")); +MQQ81:LRU_UPDATE_DATA_PT(81) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_WAYHIT_Q(0) & + TLB_TAG4_WAYHIT_Q(1) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(9) ) , STD_ULOGIC_VECTOR'("10110")); +MQQ82:LRU_UPDATE_DATA_PT(82) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_IS_SIG(0) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(3) & LRU_TAG4_DATAOUT_Q(5) & + LRU_TAG4_DATAOUT_Q(8) & LRU_TAG4_DATAOUT_Q(9) + ) , STD_ULOGIC_VECTOR'("01110111")); +MQQ83:LRU_UPDATE_DATA_PT(83) <= + Eq(( TLB_TAG4_HES_SIG & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(4) & + LRU_TAG4_DATAOUT_Q(8) & LRU_TAG4_DATAOUT_Q(9) + ) , STD_ULOGIC_VECTOR'("111111")); +MQQ84:LRU_UPDATE_DATA_PT(84) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(4) & + LRU_TAG4_DATAOUT_Q(8) & LRU_TAG4_DATAOUT_Q(9) + ) , STD_ULOGIC_VECTOR'("011111")); +MQQ85:LRU_UPDATE_DATA_PT(85) <= + Eq(( TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(3) & LRU_TAG4_DATAOUT_Q(8) & + LRU_TAG4_DATAOUT_Q(9) ) , STD_ULOGIC_VECTOR'("11011")); +MQQ86:LRU_UPDATE_DATA_PT(86) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(8) & + LRU_TAG4_DATAOUT_Q(9) ) , STD_ULOGIC_VECTOR'("1111011")); +MQQ87:LRU_UPDATE_DATA_PT(87) <= + Eq(( TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(8) & + LRU_TAG4_DATAOUT_Q(9) ) , STD_ULOGIC_VECTOR'("11011")); +MQQ88:LRU_UPDATE_DATA_PT(88) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_TYPE_SIG(6) & + TLB_TAG4_TYPE_SIG(7) & TLB_TAG4_WAYHIT_Q(3) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(8) & LRU_TAG4_DATAOUT_Q(9) + ) , STD_ULOGIC_VECTOR'("00011111")); +MQQ89:LRU_UPDATE_DATA_PT(89) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(8) & + LRU_TAG4_DATAOUT_Q(9) ) , STD_ULOGIC_VECTOR'("1011111")); +MQQ90:LRU_UPDATE_DATA_PT(90) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_WAYHIT_Q(0) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(4) & LRU_TAG4_DATAOUT_Q(9) + ) , STD_ULOGIC_VECTOR'("101111")); +MQQ91:LRU_UPDATE_DATA_PT(91) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_WAYHIT_Q(0) & + TLB_TAG4_WAYHIT_Q(1) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(3) & LRU_TAG4_DATAOUT_Q(9) + ) , STD_ULOGIC_VECTOR'("10111101")); +MQQ92:LRU_UPDATE_DATA_PT(92) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_WAYHIT_Q(0) & + TLB_TAG4_WAYHIT_Q(1) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(9) ) , STD_ULOGIC_VECTOR'("1011101")); +MQQ93:LRU_UPDATE_DATA_PT(93) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(3) & LRU_TAG4_DATAOUT_Q(4) & + LRU_TAG4_DATAOUT_Q(6) & LRU_TAG4_DATAOUT_Q(8) + ) , STD_ULOGIC_VECTOR'("1111111100")); +MQQ94:LRU_UPDATE_DATA_PT(94) <= + Eq(( TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(3) & LRU_TAG4_DATAOUT_Q(4) & + LRU_TAG4_DATAOUT_Q(6) & LRU_TAG4_DATAOUT_Q(8) + ) , STD_ULOGIC_VECTOR'("11111100")); +MQQ95:LRU_UPDATE_DATA_PT(95) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_WAYHIT_Q(0) & + LRU_TAG4_DATAOUT_Q(6) & LRU_TAG4_DATAOUT_Q(8) + ) , STD_ULOGIC_VECTOR'("1110")); +MQQ96:LRU_UPDATE_DATA_PT(96) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_TYPE_SIG(6) & + TLB_TAG4_TYPE_SIG(7) & TLB_TAG4_WAYHIT_Q(2) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(8) + ) , STD_ULOGIC_VECTOR'("00011110")); +MQQ97:LRU_UPDATE_DATA_PT(97) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & TLB_TAG4_ESEL_SIG(2) & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(8) + ) , STD_ULOGIC_VECTOR'("10101110")); +MQQ98:LRU_UPDATE_DATA_PT(98) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(3) & LRU_TAG4_DATAOUT_Q(5) & + LRU_TAG4_DATAOUT_Q(8) ) , STD_ULOGIC_VECTOR'("1111001")); +MQQ99:LRU_UPDATE_DATA_PT(99) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(4) & + LRU_TAG4_DATAOUT_Q(5) & LRU_TAG4_DATAOUT_Q(8) + ) , STD_ULOGIC_VECTOR'("111111")); +MQQ100:LRU_UPDATE_DATA_PT(100) <= + Eq(( TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(4) & LRU_TAG4_DATAOUT_Q(5) & + LRU_TAG4_DATAOUT_Q(8) ) , STD_ULOGIC_VECTOR'("11111")); +MQQ101:LRU_UPDATE_DATA_PT(101) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_TYPE_SIG(7) & + TLB_TAG4_WAYHIT_Q(1) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(5) & LRU_TAG4_DATAOUT_Q(8) + ) , STD_ULOGIC_VECTOR'("000111")); +MQQ102:LRU_UPDATE_DATA_PT(102) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(5) & LRU_TAG4_DATAOUT_Q(8) + ) , STD_ULOGIC_VECTOR'("101111")); +MQQ103:LRU_UPDATE_DATA_PT(103) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(5) & LRU_TAG4_DATAOUT_Q(8) + ) , STD_ULOGIC_VECTOR'("1111")); +MQQ104:LRU_UPDATE_DATA_PT(104) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_WAYHIT_Q(1) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(4) & LRU_TAG4_DATAOUT_Q(8) + ) , STD_ULOGIC_VECTOR'("101111")); +MQQ105:LRU_UPDATE_DATA_PT(105) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_WAYHIT_Q(0) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(3) & + LRU_TAG4_DATAOUT_Q(8) ) , STD_ULOGIC_VECTOR'("1111101")); +MQQ106:LRU_UPDATE_DATA_PT(106) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_WAYHIT_Q(0) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(8) + ) , STD_ULOGIC_VECTOR'("111101")); +MQQ107:LRU_UPDATE_DATA_PT(107) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_WAYHIT_Q(0) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(8) ) , STD_ULOGIC_VECTOR'("11101")); +MQQ108:LRU_UPDATE_DATA_PT(108) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(8) ) , STD_ULOGIC_VECTOR'("11101")); +MQQ109:LRU_UPDATE_DATA_PT(109) <= + Eq(( TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(8) ) , STD_ULOGIC_VECTOR'("101")); +MQQ110:LRU_UPDATE_DATA_PT(110) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(4) & + LRU_TAG4_DATAOUT_Q(6) ) , STD_ULOGIC_VECTOR'("11001")); +MQQ111:LRU_UPDATE_DATA_PT(111) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_TYPE_SIG(7) & + TLB_TAG4_WAYHIT_Q(0) & TLB_TAG4_WAYHIT_Q(1) & + TLB_TAG4_WAYHIT_Q(2) & TLB_TAG4_WAYHIT_Q(3) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(6) + ) , STD_ULOGIC_VECTOR'("00000011")); +MQQ112:LRU_UPDATE_DATA_PT(112) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_WAYHIT_Q(2) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(6) + ) , STD_ULOGIC_VECTOR'("1011")); +MQQ113:LRU_UPDATE_DATA_PT(113) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(6) ) , STD_ULOGIC_VECTOR'("11011")); +MQQ114:LRU_UPDATE_DATA_PT(114) <= + Eq(( LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(6) ) , STD_ULOGIC_VECTOR'("001")); +MQQ115:LRU_UPDATE_DATA_PT(115) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_IS_SIG(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(6) + ) , STD_ULOGIC_VECTOR'("1001")); +MQQ116:LRU_UPDATE_DATA_PT(116) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(2) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(6) ) , STD_ULOGIC_VECTOR'("10001")); +MQQ117:LRU_UPDATE_DATA_PT(117) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(6) ) , STD_ULOGIC_VECTOR'("10101")); +MQQ118:LRU_UPDATE_DATA_PT(118) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_TYPE_SIG(7) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(6) + ) , STD_ULOGIC_VECTOR'("0001")); +MQQ119:LRU_UPDATE_DATA_PT(119) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_IS_SIG(0) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(6) + ) , STD_ULOGIC_VECTOR'("1001")); +MQQ120:LRU_UPDATE_DATA_PT(120) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(2) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(6) ) , STD_ULOGIC_VECTOR'("10101")); +MQQ121:LRU_UPDATE_DATA_PT(121) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(6) ) , STD_ULOGIC_VECTOR'("10101")); +MQQ122:LRU_UPDATE_DATA_PT(122) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_TYPE_SIG(7) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(6) + ) , STD_ULOGIC_VECTOR'("0001")); +MQQ123:LRU_UPDATE_DATA_PT(123) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_WAYHIT_Q(0) & + TLB_TAG4_WAYHIT_Q(1) & TLB_TAG4_WAYHIT_Q(2) & + TLB_TAG4_WAYHIT_Q(3) & LRU_TAG4_DATAOUT_Q(6) + ) , STD_ULOGIC_VECTOR'("100001")); +MQQ124:LRU_UPDATE_DATA_PT(124) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & TLB_TAG4_IS_SIG(0) & + LRU_TAG4_DATAOUT_Q(6) ) , STD_ULOGIC_VECTOR'("10001")); +MQQ125:LRU_UPDATE_DATA_PT(125) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_ESEL_SIG(2) & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(3) & + LRU_TAG4_DATAOUT_Q(5) ) , STD_ULOGIC_VECTOR'("0011101")); +MQQ126:LRU_UPDATE_DATA_PT(126) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_ESEL_SIG(1) & + TLB_TAG4_ESEL_SIG(2) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(3) & + LRU_TAG4_DATAOUT_Q(5) ) , STD_ULOGIC_VECTOR'("0011101")); +MQQ127:LRU_UPDATE_DATA_PT(127) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_TYPE_SIG(6) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(3) & LRU_TAG4_DATAOUT_Q(5) + ) , STD_ULOGIC_VECTOR'("001101")); +MQQ128:LRU_UPDATE_DATA_PT(128) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_ESEL_SIG(2) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(5) + ) , STD_ULOGIC_VECTOR'("011101")); +MQQ129:LRU_UPDATE_DATA_PT(129) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_HES_SIG & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(5) + ) , STD_ULOGIC_VECTOR'("011101")); +MQQ130:LRU_UPDATE_DATA_PT(130) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_TYPE_SIG(6) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(5) + ) , STD_ULOGIC_VECTOR'("001101")); +MQQ131:LRU_UPDATE_DATA_PT(131) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & TLB_TAG4_ESEL_SIG(2) & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(5) ) , STD_ULOGIC_VECTOR'("1000101")); +MQQ132:LRU_UPDATE_DATA_PT(132) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_TYPE_SIG(7) & + TLB_TAG4_WAYHIT_Q(0) & TLB_TAG4_WAYHIT_Q(1) & + TLB_TAG4_WAYHIT_Q(2) & TLB_TAG4_WAYHIT_Q(3) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(5) + ) , STD_ULOGIC_VECTOR'("00000011")); +MQQ133:LRU_UPDATE_DATA_PT(133) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_WAYHIT_Q(0) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(5) + ) , STD_ULOGIC_VECTOR'("1011")); +MQQ134:LRU_UPDATE_DATA_PT(134) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_ESEL_SIG(1) & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(5) ) , STD_ULOGIC_VECTOR'("11011")); +MQQ135:LRU_UPDATE_DATA_PT(135) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(5) ) , STD_ULOGIC_VECTOR'("11011")); +MQQ136:LRU_UPDATE_DATA_PT(136) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_WAYHIT_Q(0) & + TLB_TAG4_WAYHIT_Q(1) & TLB_TAG4_WAYHIT_Q(2) & + TLB_TAG4_WAYHIT_Q(3) & LRU_TAG4_DATAOUT_Q(5) + ) , STD_ULOGIC_VECTOR'("100001")); +MQQ137:LRU_UPDATE_DATA_PT(137) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(4) + ) , STD_ULOGIC_VECTOR'("110101")); +MQQ138:LRU_UPDATE_DATA_PT(138) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_TYPE_SIG(7) & + TLB_TAG4_WAYHIT_Q(0) & TLB_TAG4_WAYHIT_Q(1) & + TLB_TAG4_WAYHIT_Q(2) & TLB_TAG4_WAYHIT_Q(3) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(4) ) , STD_ULOGIC_VECTOR'("000000111")); +MQQ139:LRU_UPDATE_DATA_PT(139) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_WAYHIT_Q(0) & + TLB_TAG4_WAYHIT_Q(1) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(4) + ) , STD_ULOGIC_VECTOR'("100111")); +MQQ140:LRU_UPDATE_DATA_PT(140) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(4) + ) , STD_ULOGIC_VECTOR'("110111")); +MQQ141:LRU_UPDATE_DATA_PT(141) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_WAYHIT_Q(0) & + TLB_TAG4_WAYHIT_Q(1) & TLB_TAG4_WAYHIT_Q(2) & + TLB_TAG4_WAYHIT_Q(3) & LRU_TAG4_DATAOUT_Q(4) + ) , STD_ULOGIC_VECTOR'("100001")); +MQQ142:LRU_UPDATE_DATA_PT(142) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(3) ) , STD_ULOGIC_VECTOR'("1111100")); +MQQ143:LRU_UPDATE_DATA_PT(143) <= + Eq(( TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(3) ) , STD_ULOGIC_VECTOR'("11100")); +MQQ144:LRU_UPDATE_DATA_PT(144) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(3) ) , STD_ULOGIC_VECTOR'("1111010")); +MQQ145:LRU_UPDATE_DATA_PT(145) <= + Eq(( TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(3) ) , STD_ULOGIC_VECTOR'("11010")); +MQQ146:LRU_UPDATE_DATA_PT(146) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(3) ) , STD_ULOGIC_VECTOR'("1110110")); +MQQ147:LRU_UPDATE_DATA_PT(147) <= + Eq(( TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(3) ) , STD_ULOGIC_VECTOR'("10110")); +MQQ148:LRU_UPDATE_DATA_PT(148) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_WAYHIT_Q(0) & + TLB_TAG4_WAYHIT_Q(1) & TLB_TAG4_WAYHIT_Q(2) & + TLB_TAG4_WAYHIT_Q(3) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(3) ) , STD_ULOGIC_VECTOR'("100011110")); +MQQ149:LRU_UPDATE_DATA_PT(149) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_TYPE_SIG(6) & + TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(3) ) , STD_ULOGIC_VECTOR'("0001110")); +MQQ150:LRU_UPDATE_DATA_PT(150) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & TLB_TAG4_ESEL_SIG(2) & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(3) + ) , STD_ULOGIC_VECTOR'("10001110")); +MQQ151:LRU_UPDATE_DATA_PT(151) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & TLB_TAG4_ESEL_SIG(2) & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(3) + ) , STD_ULOGIC_VECTOR'("10011110")); +MQQ152:LRU_UPDATE_DATA_PT(152) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & TLB_TAG4_ESEL_SIG(2) & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(3) + ) , STD_ULOGIC_VECTOR'("10101110")); +MQQ153:LRU_UPDATE_DATA_PT(153) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & TLB_TAG4_ESEL_SIG(2) & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(3) ) , STD_ULOGIC_VECTOR'("1000100")); +MQQ154:LRU_UPDATE_DATA_PT(154) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) + ) , STD_ULOGIC_VECTOR'("111100")); +MQQ155:LRU_UPDATE_DATA_PT(155) <= + Eq(( TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) + ) , STD_ULOGIC_VECTOR'("1100")); +MQQ156:LRU_UPDATE_DATA_PT(156) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) + ) , STD_ULOGIC_VECTOR'("111010")); +MQQ157:LRU_UPDATE_DATA_PT(157) <= + Eq(( TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) + ) , STD_ULOGIC_VECTOR'("1010")); +MQQ158:LRU_UPDATE_DATA_PT(158) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_WAYHIT_Q(0) & + TLB_TAG4_WAYHIT_Q(1) & TLB_TAG4_WAYHIT_Q(3) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(2) ) , STD_ULOGIC_VECTOR'("1001110")); +MQQ159:LRU_UPDATE_DATA_PT(159) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_WAYHIT_Q(0) & + TLB_TAG4_WAYHIT_Q(1) & TLB_TAG4_WAYHIT_Q(2) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(2) ) , STD_ULOGIC_VECTOR'("1001110")); +MQQ160:LRU_UPDATE_DATA_PT(160) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & TLB_TAG4_ESEL_SIG(2) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(2) ) , STD_ULOGIC_VECTOR'("1011110")); +MQQ161:LRU_UPDATE_DATA_PT(161) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_TYPE_SIG(6) & + TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) + ) , STD_ULOGIC_VECTOR'("000110")); +MQQ162:LRU_UPDATE_DATA_PT(162) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & TLB_TAG4_ESEL_SIG(2) & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(2) ) , STD_ULOGIC_VECTOR'("1000110")); +MQQ163:LRU_UPDATE_DATA_PT(163) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & TLB_TAG4_ESEL_SIG(2) & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(2) ) , STD_ULOGIC_VECTOR'("1000100")); +MQQ164:LRU_UPDATE_DATA_PT(164) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & TLB_TAG4_ESEL_SIG(2) & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(2) ) , STD_ULOGIC_VECTOR'("1001110")); +MQQ165:LRU_UPDATE_DATA_PT(165) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & TLB_TAG4_ESEL_SIG(2) & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) + ) , STD_ULOGIC_VECTOR'("10110111")); +MQQ166:LRU_UPDATE_DATA_PT(166) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) ) , STD_ULOGIC_VECTOR'("11100")); +MQQ167:LRU_UPDATE_DATA_PT(167) <= + Eq(( TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) ) , STD_ULOGIC_VECTOR'("100")); +MQQ168:LRU_UPDATE_DATA_PT(168) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_WAYHIT_Q(0) & + TLB_TAG4_WAYHIT_Q(3) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) ) , STD_ULOGIC_VECTOR'("10110")); +MQQ169:LRU_UPDATE_DATA_PT(169) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_WAYHIT_Q(0) & + TLB_TAG4_WAYHIT_Q(2) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) ) , STD_ULOGIC_VECTOR'("10110")); +MQQ170:LRU_UPDATE_DATA_PT(170) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_WAYHIT_Q(0) & + TLB_TAG4_WAYHIT_Q(1) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) ) , STD_ULOGIC_VECTOR'("10110")); +MQQ171:LRU_UPDATE_DATA_PT(171) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) ) , STD_ULOGIC_VECTOR'("10110")); +MQQ172:LRU_UPDATE_DATA_PT(172) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_TYPE_SIG(6) & + TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) ) , STD_ULOGIC_VECTOR'("00010")); +MQQ173:LRU_UPDATE_DATA_PT(173) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & TLB_TAG4_ESEL_SIG(2) & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(1) + ) , STD_ULOGIC_VECTOR'("100010")); +MQQ174:LRU_UPDATE_DATA_PT(174) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & TLB_TAG4_IS_SIG(0) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) + ) , STD_ULOGIC_VECTOR'("101011")); +MQQ175:LRU_UPDATE_DATA_PT(175) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & TLB_TAG4_ESEL_SIG(2) & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) + ) , STD_ULOGIC_VECTOR'("100101")); +MQQ176:LRU_UPDATE_DATA(0) <= + (LRU_UPDATE_DATA_PT(1) OR LRU_UPDATE_DATA_PT(2) + OR LRU_UPDATE_DATA_PT(3) OR LRU_UPDATE_DATA_PT(4) + OR LRU_UPDATE_DATA_PT(5) OR LRU_UPDATE_DATA_PT(6) + OR LRU_UPDATE_DATA_PT(7) OR LRU_UPDATE_DATA_PT(8) + OR LRU_UPDATE_DATA_PT(9) OR LRU_UPDATE_DATA_PT(10) + OR LRU_UPDATE_DATA_PT(15) OR LRU_UPDATE_DATA_PT(16) + OR LRU_UPDATE_DATA_PT(17) OR LRU_UPDATE_DATA_PT(18) + OR LRU_UPDATE_DATA_PT(25) OR LRU_UPDATE_DATA_PT(31) + OR LRU_UPDATE_DATA_PT(32) OR LRU_UPDATE_DATA_PT(35) + OR LRU_UPDATE_DATA_PT(36) OR LRU_UPDATE_DATA_PT(37) + OR LRU_UPDATE_DATA_PT(38) OR LRU_UPDATE_DATA_PT(39) + OR LRU_UPDATE_DATA_PT(40) OR LRU_UPDATE_DATA_PT(41) + OR LRU_UPDATE_DATA_PT(42) OR LRU_UPDATE_DATA_PT(43) + OR LRU_UPDATE_DATA_PT(44) OR LRU_UPDATE_DATA_PT(45) + OR LRU_UPDATE_DATA_PT(56) OR LRU_UPDATE_DATA_PT(82) + OR LRU_UPDATE_DATA_PT(83) OR LRU_UPDATE_DATA_PT(84) + OR LRU_UPDATE_DATA_PT(85) OR LRU_UPDATE_DATA_PT(86) + OR LRU_UPDATE_DATA_PT(87) OR LRU_UPDATE_DATA_PT(88) + OR LRU_UPDATE_DATA_PT(89) OR LRU_UPDATE_DATA_PT(90) + OR LRU_UPDATE_DATA_PT(91) OR LRU_UPDATE_DATA_PT(92) + OR LRU_UPDATE_DATA_PT(98) OR LRU_UPDATE_DATA_PT(104) + OR LRU_UPDATE_DATA_PT(105) OR LRU_UPDATE_DATA_PT(106) + OR LRU_UPDATE_DATA_PT(138) OR LRU_UPDATE_DATA_PT(139) + OR LRU_UPDATE_DATA_PT(140) OR LRU_UPDATE_DATA_PT(141) + OR LRU_UPDATE_DATA_PT(142) OR LRU_UPDATE_DATA_PT(143) + OR LRU_UPDATE_DATA_PT(144) OR LRU_UPDATE_DATA_PT(145) + OR LRU_UPDATE_DATA_PT(146) OR LRU_UPDATE_DATA_PT(147) + OR LRU_UPDATE_DATA_PT(148) OR LRU_UPDATE_DATA_PT(149) + OR LRU_UPDATE_DATA_PT(150) OR LRU_UPDATE_DATA_PT(151) + OR LRU_UPDATE_DATA_PT(152) OR LRU_UPDATE_DATA_PT(154) + OR LRU_UPDATE_DATA_PT(155) OR LRU_UPDATE_DATA_PT(156) + OR LRU_UPDATE_DATA_PT(157) OR LRU_UPDATE_DATA_PT(158) + OR LRU_UPDATE_DATA_PT(159) OR LRU_UPDATE_DATA_PT(160) + OR LRU_UPDATE_DATA_PT(161) OR LRU_UPDATE_DATA_PT(162) + OR LRU_UPDATE_DATA_PT(164) OR LRU_UPDATE_DATA_PT(174) + ); +MQQ177:LRU_UPDATE_DATA(1) <= + (LRU_UPDATE_DATA_PT(5) OR LRU_UPDATE_DATA_PT(6) + OR LRU_UPDATE_DATA_PT(21) OR LRU_UPDATE_DATA_PT(22) + OR LRU_UPDATE_DATA_PT(27) OR LRU_UPDATE_DATA_PT(28) + OR LRU_UPDATE_DATA_PT(29) OR LRU_UPDATE_DATA_PT(30) + OR LRU_UPDATE_DATA_PT(33) OR LRU_UPDATE_DATA_PT(34) + OR LRU_UPDATE_DATA_PT(37) OR LRU_UPDATE_DATA_PT(38) + OR LRU_UPDATE_DATA_PT(59) OR LRU_UPDATE_DATA_PT(60) + OR LRU_UPDATE_DATA_PT(61) OR LRU_UPDATE_DATA_PT(62) + OR LRU_UPDATE_DATA_PT(63) OR LRU_UPDATE_DATA_PT(64) + OR LRU_UPDATE_DATA_PT(65) OR LRU_UPDATE_DATA_PT(70) + OR LRU_UPDATE_DATA_PT(71) OR LRU_UPDATE_DATA_PT(72) + OR LRU_UPDATE_DATA_PT(73) OR LRU_UPDATE_DATA_PT(74) + OR LRU_UPDATE_DATA_PT(75) OR LRU_UPDATE_DATA_PT(76) + OR LRU_UPDATE_DATA_PT(77) OR LRU_UPDATE_DATA_PT(78) + OR LRU_UPDATE_DATA_PT(79) OR LRU_UPDATE_DATA_PT(80) + OR LRU_UPDATE_DATA_PT(81) OR LRU_UPDATE_DATA_PT(82) + OR LRU_UPDATE_DATA_PT(99) OR LRU_UPDATE_DATA_PT(100) + OR LRU_UPDATE_DATA_PT(101) OR LRU_UPDATE_DATA_PT(102) + OR LRU_UPDATE_DATA_PT(103) OR LRU_UPDATE_DATA_PT(107) + OR LRU_UPDATE_DATA_PT(108) OR LRU_UPDATE_DATA_PT(109) + OR LRU_UPDATE_DATA_PT(125) OR LRU_UPDATE_DATA_PT(126) + OR LRU_UPDATE_DATA_PT(127) OR LRU_UPDATE_DATA_PT(128) + OR LRU_UPDATE_DATA_PT(129) OR LRU_UPDATE_DATA_PT(130) + OR LRU_UPDATE_DATA_PT(131) OR LRU_UPDATE_DATA_PT(132) + OR LRU_UPDATE_DATA_PT(133) OR LRU_UPDATE_DATA_PT(134) + OR LRU_UPDATE_DATA_PT(135) OR LRU_UPDATE_DATA_PT(136) + OR LRU_UPDATE_DATA_PT(137) OR LRU_UPDATE_DATA_PT(153) + OR LRU_UPDATE_DATA_PT(163) OR LRU_UPDATE_DATA_PT(166) + OR LRU_UPDATE_DATA_PT(167) OR LRU_UPDATE_DATA_PT(168) + OR LRU_UPDATE_DATA_PT(169) OR LRU_UPDATE_DATA_PT(170) + OR LRU_UPDATE_DATA_PT(171) OR LRU_UPDATE_DATA_PT(172) + OR LRU_UPDATE_DATA_PT(173) OR LRU_UPDATE_DATA_PT(175) + ); +MQQ178:LRU_UPDATE_DATA(2) <= + (LRU_UPDATE_DATA_PT(1) OR LRU_UPDATE_DATA_PT(2) + OR LRU_UPDATE_DATA_PT(3) OR LRU_UPDATE_DATA_PT(4) + OR LRU_UPDATE_DATA_PT(5) OR LRU_UPDATE_DATA_PT(6) + OR LRU_UPDATE_DATA_PT(7) OR LRU_UPDATE_DATA_PT(8) + OR LRU_UPDATE_DATA_PT(9) OR LRU_UPDATE_DATA_PT(10) + OR LRU_UPDATE_DATA_PT(11) OR LRU_UPDATE_DATA_PT(12) + OR LRU_UPDATE_DATA_PT(13) OR LRU_UPDATE_DATA_PT(14) + OR LRU_UPDATE_DATA_PT(15) OR LRU_UPDATE_DATA_PT(16) + OR LRU_UPDATE_DATA_PT(17) OR LRU_UPDATE_DATA_PT(18) + OR LRU_UPDATE_DATA_PT(19) OR LRU_UPDATE_DATA_PT(20) + OR LRU_UPDATE_DATA_PT(23) OR LRU_UPDATE_DATA_PT(24) + OR LRU_UPDATE_DATA_PT(25) OR LRU_UPDATE_DATA_PT(26) + OR LRU_UPDATE_DATA_PT(46) OR LRU_UPDATE_DATA_PT(47) + OR LRU_UPDATE_DATA_PT(48) OR LRU_UPDATE_DATA_PT(49) + OR LRU_UPDATE_DATA_PT(50) OR LRU_UPDATE_DATA_PT(51) + OR LRU_UPDATE_DATA_PT(52) OR LRU_UPDATE_DATA_PT(53) + OR LRU_UPDATE_DATA_PT(54) OR LRU_UPDATE_DATA_PT(55) + OR LRU_UPDATE_DATA_PT(56) OR LRU_UPDATE_DATA_PT(57) + OR LRU_UPDATE_DATA_PT(58) OR LRU_UPDATE_DATA_PT(61) + OR LRU_UPDATE_DATA_PT(64) OR LRU_UPDATE_DATA_PT(66) + OR LRU_UPDATE_DATA_PT(67) OR LRU_UPDATE_DATA_PT(68) + OR LRU_UPDATE_DATA_PT(69) OR LRU_UPDATE_DATA_PT(91) + OR LRU_UPDATE_DATA_PT(93) OR LRU_UPDATE_DATA_PT(94) + OR LRU_UPDATE_DATA_PT(95) OR LRU_UPDATE_DATA_PT(96) + OR LRU_UPDATE_DATA_PT(97) OR LRU_UPDATE_DATA_PT(105) + OR LRU_UPDATE_DATA_PT(110) OR LRU_UPDATE_DATA_PT(111) + OR LRU_UPDATE_DATA_PT(112) OR LRU_UPDATE_DATA_PT(113) + OR LRU_UPDATE_DATA_PT(114) OR LRU_UPDATE_DATA_PT(115) + OR LRU_UPDATE_DATA_PT(116) OR LRU_UPDATE_DATA_PT(117) + OR LRU_UPDATE_DATA_PT(118) OR LRU_UPDATE_DATA_PT(119) + OR LRU_UPDATE_DATA_PT(120) OR LRU_UPDATE_DATA_PT(121) + OR LRU_UPDATE_DATA_PT(122) OR LRU_UPDATE_DATA_PT(123) + OR LRU_UPDATE_DATA_PT(124) OR LRU_UPDATE_DATA_PT(142) + OR LRU_UPDATE_DATA_PT(143) OR LRU_UPDATE_DATA_PT(144) + OR LRU_UPDATE_DATA_PT(145) OR LRU_UPDATE_DATA_PT(146) + OR LRU_UPDATE_DATA_PT(147) OR LRU_UPDATE_DATA_PT(148) + OR LRU_UPDATE_DATA_PT(149) OR LRU_UPDATE_DATA_PT(150) + OR LRU_UPDATE_DATA_PT(151) OR LRU_UPDATE_DATA_PT(152) + OR LRU_UPDATE_DATA_PT(165)); + +gen64_tlb_datain: if rs_data_width = 64 generate +tlb_datain_lo_tlbwe_0_nopar(0 TO tlb_word_width-10-1) <= + (tlb_tag4_q(tagpos_epn to tagpos_epn+31) and (0 to 31 => tlb_tag4_q(tagpos_cm))) & tlb_tag4_q(tagpos_epn+32 to tagpos_epn+51) & tlb_tag4_q(tagpos_size to tagpos_size+3) & mmucr3_0(60 to 63) & + mmucr3_0(54 to 55) & (mmucr3_0(52) and tlb_tag4_q(tagpos_is+1)) & or_reduce(tlb_tag4_q(tagpos_pid to tagpos_pid+pid_width-1)) & + "00" & tlb_tag4_q(tagpos_lpid to tagpos_lpid+lpid_width-1); +tlb_datain_lo_tlbwe_1_nopar(0 TO tlb_word_width-10-1) <= + (tlb_tag4_q(tagpos_epn to tagpos_epn+31) and (0 to 31 => tlb_tag4_q(tagpos_cm))) & tlb_tag4_q(tagpos_epn+32 to tagpos_epn+51) & tlb_tag4_q(tagpos_size to tagpos_size+3) & mmucr3_1(60 to 63) & + mmucr3_1(54 to 55) & (mmucr3_1(52) and tlb_tag4_q(tagpos_is+1)) & or_reduce(tlb_tag4_q(tagpos_pid to tagpos_pid+pid_width-1)) & + "00" & tlb_tag4_q(tagpos_lpid to tagpos_lpid+lpid_width-1); +tlb_datain_lo_tlbwe_2_nopar(0 TO tlb_word_width-10-1) <= + (tlb_tag4_q(tagpos_epn to tagpos_epn+31) and (0 to 31 => tlb_tag4_q(tagpos_cm))) & tlb_tag4_q(tagpos_epn+32 to tagpos_epn+51) & tlb_tag4_q(tagpos_size to tagpos_size+3) & mmucr3_2(60 to 63) & + mmucr3_2(54 to 55) & (mmucr3_2(52) and tlb_tag4_q(tagpos_is+1)) & or_reduce(tlb_tag4_q(tagpos_pid to tagpos_pid+pid_width-1)) & + "00" & tlb_tag4_q(tagpos_lpid to tagpos_lpid+lpid_width-1); +tlb_datain_lo_tlbwe_3_nopar(0 TO tlb_word_width-10-1) <= + (tlb_tag4_q(tagpos_epn to tagpos_epn+31) and (0 to 31 => tlb_tag4_q(tagpos_cm))) & tlb_tag4_q(tagpos_epn+32 to tagpos_epn+51) & tlb_tag4_q(tagpos_size to tagpos_size+3) & mmucr3_3(60 to 63) & + mmucr3_3(54 to 55) & (mmucr3_3(52) and tlb_tag4_q(tagpos_is+1)) & or_reduce(tlb_tag4_q(tagpos_pid to tagpos_pid+pid_width-1)) & + "00" & tlb_tag4_q(tagpos_lpid to tagpos_lpid+lpid_width-1); +tlb_datain_lo_ptereload_nopar(0 TO tlb_word_width-10-1) <= + tlb_tag4_q(tagpos_epn to tagpos_epn+epn_width-1) & '0' & ptereload_req_pte_lat(ptepos_size to ptepos_size+2) & tlb_tag4_q(tagpos_atsel) & tlb_tag4_q(tagpos_esel to tagpos_esel+2) & + tlb_tag4_q(tagpos_class) & (tlb_tag4_q(tagpos_class) and tlb_tag4_q(tagpos_class+1)) & '0' & or_reduce(tlb_tag4_q(tagpos_pid to tagpos_pid+pid_width-1)) & + "00" & tlb_tag4_q(tagpos_lpid to tagpos_lpid+lpid_width-1); +tlb_dataina_d(0 TO tlb_word_width-1) <= + tlb_datain_lo_tlbwe_0_nopar & tlb_datain_lo_tlbwe_0_par + when (tlb_tag4_q(tagpos_thdid+0)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1') else + tlb_datain_lo_tlbwe_1_nopar & tlb_datain_lo_tlbwe_1_par + when (tlb_tag4_q(tagpos_thdid+1)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1') else + tlb_datain_lo_tlbwe_2_nopar & tlb_datain_lo_tlbwe_2_par + when (tlb_tag4_q(tagpos_thdid+2)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1') else + tlb_datain_lo_tlbwe_3_nopar & tlb_datain_lo_tlbwe_3_par + when (tlb_tag4_q(tagpos_thdid+3)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1') else + tlb_datain_lo_ptereload_nopar & tlb_datain_lo_ptereload_par + when (tlb_tag4_ptereload_sig='1') else + tlb_dataina_q(0 to tlb_word_width-1); +tlb_datainb_d(0 TO tlb_word_width-1) <= + tlb_datain_lo_tlbwe_0_nopar & tlb_datain_lo_tlbwe_0_par + when (tlb_tag4_q(tagpos_thdid+0)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1') else + tlb_datain_lo_tlbwe_1_nopar & tlb_datain_lo_tlbwe_1_par + when (tlb_tag4_q(tagpos_thdid+1)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1') else + tlb_datain_lo_tlbwe_2_nopar & tlb_datain_lo_tlbwe_2_par + when (tlb_tag4_q(tagpos_thdid+2)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1') else + tlb_datain_lo_tlbwe_3_nopar & tlb_datain_lo_tlbwe_3_par + when (tlb_tag4_q(tagpos_thdid+3)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1') else + tlb_datain_lo_ptereload_nopar & tlb_datain_lo_ptereload_par + when (tlb_tag4_ptereload_sig='1') else + tlb_datainb_q(0 to tlb_word_width-1); +end generate gen64_tlb_datain; +gen32_tlb_datain: if rs_data_width = 32 generate +tlb_datain_lo_tlbwe_0_nopar(0 TO tlb_word_width-10-1) <= + (0 to 31 => '0') & tlb_tag4_q(tagpos_epn+32 to tagpos_epn+51) & tlb_tag4_q(tagpos_size to tagpos_size+3) & mmucr3_0(60 to 63) & + mmucr3_0(54 to 55) & (mmucr3_0(52) and tlb_tag4_q(tagpos_is+1)) & or_reduce(tlb_tag4_q(tagpos_pid to tagpos_pid+pid_width-1)) & + "00" & tlb_tag4_q(tagpos_lpid to tagpos_lpid+lpid_width-1); +tlb_datain_lo_tlbwe_1_nopar(0 TO tlb_word_width-10-1) <= + (0 to 31 => '0') & tlb_tag4_q(tagpos_epn+32 to tagpos_epn+51) & tlb_tag4_q(tagpos_size to tagpos_size+3) & mmucr3_1(60 to 63) & + mmucr3_1(54 to 55) & (mmucr3_1(52) and tlb_tag4_q(tagpos_is+1)) & or_reduce(tlb_tag4_q(tagpos_pid to tagpos_pid+pid_width-1)) & + "00" & tlb_tag4_q(tagpos_lpid to tagpos_lpid+lpid_width-1); +tlb_datain_lo_tlbwe_2_nopar(0 TO tlb_word_width-10-1) <= + (0 to 31 => '0') & tlb_tag4_q(tagpos_epn+32 to tagpos_epn+51) & tlb_tag4_q(tagpos_size to tagpos_size+3) & mmucr3_2(60 to 63) & + mmucr3_2(54 to 55) & (mmucr3_2(52) and tlb_tag4_q(tagpos_is+1)) & or_reduce(tlb_tag4_q(tagpos_pid to tagpos_pid+pid_width-1)) & + "00" & tlb_tag4_q(tagpos_lpid to tagpos_lpid+lpid_width-1); +tlb_datain_lo_tlbwe_3_nopar(0 TO tlb_word_width-10-1) <= + (0 to 31 => '0') & tlb_tag4_q(tagpos_epn+32 to tagpos_epn+51) & tlb_tag4_q(tagpos_size to tagpos_size+3) & mmucr3_3(60 to 63) & + mmucr3_3(54 to 55) & (mmucr3_3(52) and tlb_tag4_q(tagpos_is+1)) & or_reduce(tlb_tag4_q(tagpos_pid to tagpos_pid+pid_width-1)) & + "00" & tlb_tag4_q(tagpos_lpid to tagpos_lpid+lpid_width-1); +tlb_datain_lo_ptereload_nopar(0 TO tlb_word_width-10-1) <= + (0 to 31 => '0') & tlb_tag4_q(tagpos_epn+32 to tagpos_epn+epn_width+32-1) & '0' & ptereload_req_pte_lat(ptepos_size to ptepos_size+2) & "1111" & + tlb_tag4_q(tagpos_class to tagpos_class+1) & '0' & or_reduce(tlb_tag4_q(tagpos_pid to tagpos_pid+pid_width-1)) & + "00" & tlb_tag4_q(tagpos_lpid to tagpos_lpid+lpid_width-1); +tlb_dataina_d(0 TO tlb_word_width-1) <= + tlb_datain_lo_tlbwe_0_nopar & tlb_datain_lo_tlbwe_0_par + when (tlb_tag4_q(tagpos_thdid+0)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1') else + tlb_datain_lo_tlbwe_1_nopar & tlb_datain_lo_tlbwe_1_par + when (tlb_tag4_q(tagpos_thdid+1)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1') else + tlb_datain_lo_tlbwe_2_nopar & tlb_datain_lo_tlbwe_2_par + when (tlb_tag4_q(tagpos_thdid+2)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1') else + tlb_datain_lo_tlbwe_3_nopar & tlb_datain_lo_tlbwe_3_par + when (tlb_tag4_q(tagpos_thdid+3)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1') else + tlb_datain_lo_ptereload_nopar & tlb_datain_lo_ptereload_par + when (tlb_tag4_ptereload_sig='1') else + tlb_dataina_q(0 to tlb_word_width-1); +tlb_datainb_d(0 TO tlb_word_width-1) <= + tlb_datain_lo_tlbwe_0_nopar & tlb_datain_lo_tlbwe_0_par + when (tlb_tag4_q(tagpos_thdid+0)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1') else + tlb_datain_lo_tlbwe_1_nopar & tlb_datain_lo_tlbwe_1_par + when (tlb_tag4_q(tagpos_thdid+1)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1') else + tlb_datain_lo_tlbwe_2_nopar & tlb_datain_lo_tlbwe_2_par + when (tlb_tag4_q(tagpos_thdid+2)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1') else + tlb_datain_lo_tlbwe_3_nopar & tlb_datain_lo_tlbwe_3_par + when (tlb_tag4_q(tagpos_thdid+3)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1') else + tlb_datain_lo_ptereload_nopar & tlb_datain_lo_ptereload_par + when (tlb_tag4_ptereload_sig='1') else + tlb_datainb_q(0 to tlb_word_width-1); +end generate gen32_tlb_datain; +ptereload_req_derived_usxwr(0) <= ptereload_req_pte_lat(ptepos_usxwr+0) and ptereload_req_pte_lat(ptepos_r); +ptereload_req_derived_usxwr(1) <= ptereload_req_pte_lat(ptepos_usxwr+1) and ptereload_req_pte_lat(ptepos_r); +ptereload_req_derived_usxwr(2) <= ptereload_req_pte_lat(ptepos_usxwr+2) and ptereload_req_pte_lat(ptepos_r) and ptereload_req_pte_lat(ptepos_c); +ptereload_req_derived_usxwr(3) <= ptereload_req_pte_lat(ptepos_usxwr+3) and ptereload_req_pte_lat(ptepos_r) and ptereload_req_pte_lat(ptepos_c); +ptereload_req_derived_usxwr(4) <= ptereload_req_pte_lat(ptepos_usxwr+4) and ptereload_req_pte_lat(ptepos_r); +ptereload_req_derived_usxwr(5) <= ptereload_req_pte_lat(ptepos_usxwr+5) and ptereload_req_pte_lat(ptepos_r); +gen32_lrat_tag3_lpn: if real_addr_width < 42 generate +lrat_tag3_lpn_sig(22 TO 63-real_addr_width) <= (others => '0'); +lrat_tag3_lpn_sig(64-real_addr_width TO 51) <= lrat_tag3_lpn(64-real_addr_width to 51); +end generate gen32_lrat_tag3_lpn; +gen64_lrat_tag3_lpn: if real_addr_width > 41 generate +lrat_tag3_lpn_sig(64-real_addr_width TO 51) <= lrat_tag3_lpn(64-real_addr_width to 51); +end generate gen64_lrat_tag3_lpn; +gen32_lrat_tag3_rpn: if real_addr_width < 42 generate +lrat_tag3_rpn_sig(22 TO 63-real_addr_width) <= (others => '0'); +lrat_tag3_rpn_sig(64-real_addr_width TO 51) <= lrat_tag3_rpn(64-real_addr_width to 51); +end generate gen32_lrat_tag3_rpn; +gen64_lrat_tag3_rpn: if real_addr_width > 41 generate +lrat_tag3_rpn_sig(64-real_addr_width TO 51) <= lrat_tag3_rpn(64-real_addr_width to 51); +end generate gen64_lrat_tag3_rpn; +gen32_lrat_tag4_lpn: if real_addr_width < 42 generate +lrat_tag4_lpn_sig(22 TO 63-real_addr_width) <= (others => '0'); +lrat_tag4_lpn_sig(64-real_addr_width TO 51) <= lrat_tag4_lpn(64-real_addr_width to 51); +end generate gen32_lrat_tag4_lpn; +gen64_lrat_tag4_lpn: if real_addr_width > 41 generate +lrat_tag4_lpn_sig(64-real_addr_width TO 51) <= lrat_tag4_lpn(64-real_addr_width to 51); +end generate gen64_lrat_tag4_lpn; +gen32_lrat_tag4_rpn: if real_addr_width < 42 generate +lrat_tag4_rpn_sig(22 TO 63-real_addr_width) <= (others => '0'); +lrat_tag4_rpn_sig(64-real_addr_width TO 51) <= lrat_tag4_rpn(64-real_addr_width to 51); +end generate gen32_lrat_tag4_rpn; +gen64_lrat_tag4_rpn: if real_addr_width > 41 generate +lrat_tag4_rpn_sig(64-real_addr_width TO 51) <= lrat_tag4_rpn(64-real_addr_width to 51); +end generate gen64_lrat_tag4_rpn; +tlb_datain_hi_hv_tlbwe_0_nopar <= + mmucr3_0(49) & "000" & mas7_0_rpnu & mas3_0_rpnl(32 to 51) & mmucr3_0(50 to 51) & + mmucr3_0(56 to 58) & mas8_0_vf & (tlb_tag4_q(tagpos_ind) and tlb0cfg_ind) & mas3_0_ubits & mas2_0_wimge & + mas3_0_usxwr(0 to 3) & + (mas3_0_usxwr(4) and (not tlb_tag4_q(tagpos_ind) or not tlb0cfg_ind)) & + ((mas3_0_usxwr(5) and (not tlb_tag4_q(tagpos_ind) or not tlb0cfg_ind)) or (mas3_0_rpnl(52) and tlb_tag4_q(tagpos_ind) and tlb0cfg_ind)) & + tlb_tag4_q(tagpos_pt) & tlb_tag4_q(tagpos_recform) & "00" & tlb_tag4_q(tagpos_pid to tagpos_pid+pid_width-1); +tlb_datain_hi_hv_tlbwe_1_nopar <= + mmucr3_1(49) & "000" & mas7_1_rpnu & mas3_1_rpnl(32 to 51) & mmucr3_1(50 to 51) & + mmucr3_1(56 to 58) & mas8_1_vf & (tlb_tag4_q(tagpos_ind) and tlb0cfg_ind) & mas3_1_ubits & mas2_1_wimge & + mas3_1_usxwr(0 to 3) & + (mas3_1_usxwr(4) and (not tlb_tag4_q(tagpos_ind) or not tlb0cfg_ind)) & + ((mas3_1_usxwr(5) and (not tlb_tag4_q(tagpos_ind) or not tlb0cfg_ind)) or (mas3_1_rpnl(52) and tlb_tag4_q(tagpos_ind) and tlb0cfg_ind)) & + tlb_tag4_q(tagpos_pt) & tlb_tag4_q(tagpos_recform) & "00" & tlb_tag4_q(tagpos_pid to tagpos_pid+pid_width-1); +tlb_datain_hi_hv_tlbwe_2_nopar <= + mmucr3_2(49) & "000" & mas7_2_rpnu & mas3_2_rpnl(32 to 51) & mmucr3_2(50 to 51) & + mmucr3_2(56 to 58) & mas8_2_vf & (tlb_tag4_q(tagpos_ind) and tlb0cfg_ind) & mas3_2_ubits & mas2_2_wimge & + mas3_2_usxwr(0 to 3) & + (mas3_2_usxwr(4) and (not tlb_tag4_q(tagpos_ind) or not tlb0cfg_ind)) & + ((mas3_2_usxwr(5) and (not tlb_tag4_q(tagpos_ind) or not tlb0cfg_ind)) or (mas3_2_rpnl(52) and tlb_tag4_q(tagpos_ind) and tlb0cfg_ind)) & + tlb_tag4_q(tagpos_pt) & tlb_tag4_q(tagpos_recform) & "00" & tlb_tag4_q(tagpos_pid to tagpos_pid+pid_width-1); +tlb_datain_hi_hv_tlbwe_3_nopar <= + mmucr3_3(49) & "000" & mas7_3_rpnu & mas3_3_rpnl(32 to 51) & mmucr3_3(50 to 51) & + mmucr3_3(56 to 58) & mas8_3_vf & (tlb_tag4_q(tagpos_ind) and tlb0cfg_ind) & mas3_3_ubits & mas2_3_wimge & + mas3_3_usxwr(0 to 3) & + (mas3_3_usxwr(4) and (not tlb_tag4_q(tagpos_ind) or not tlb0cfg_ind)) & + ((mas3_3_usxwr(5) and (not tlb_tag4_q(tagpos_ind) or not tlb0cfg_ind)) or (mas3_3_rpnl(52) and tlb_tag4_q(tagpos_ind) and tlb0cfg_ind)) & + tlb_tag4_q(tagpos_pt) & tlb_tag4_q(tagpos_recform) & "00" & tlb_tag4_q(tagpos_pid to tagpos_pid+pid_width-1); +tlb_datain_hi_gs_tlbwe_0_nopar <= + mmucr3_0(49) & "000" & lrat_tag4_rpn_sig(22 to 51) & mmucr3_0(50 to 51) & + mmucr3_0(56 to 58) & mas8_0_vf & (tlb_tag4_q(tagpos_ind) and tlb0cfg_ind) & mas3_0_ubits & mas2_0_wimge & + mas3_0_usxwr(0 to 3) & + (mas3_0_usxwr(4) and (not tlb_tag4_q(tagpos_ind) or not tlb0cfg_ind)) & + ((mas3_0_usxwr(5) and (not tlb_tag4_q(tagpos_ind) or not tlb0cfg_ind)) or (mas3_0_rpnl(52) and tlb_tag4_q(tagpos_ind) and tlb0cfg_ind)) & + tlb_tag4_q(tagpos_pt) & tlb_tag4_q(tagpos_recform) & "00" & tlb_tag4_q(tagpos_pid to tagpos_pid+pid_width-1); +tlb_datain_hi_gs_tlbwe_1_nopar <= + mmucr3_1(49) & "000" & lrat_tag4_rpn_sig(22 to 51) & mmucr3_1(50 to 51) & + mmucr3_1(56 to 58) & mas8_1_vf & (tlb_tag4_q(tagpos_ind) and tlb0cfg_ind) & mas3_1_ubits & mas2_1_wimge & + mas3_1_usxwr(0 to 3) & + (mas3_1_usxwr(4) and (not tlb_tag4_q(tagpos_ind) or not tlb0cfg_ind)) & + ((mas3_1_usxwr(5) and (not tlb_tag4_q(tagpos_ind) or not tlb0cfg_ind)) or (mas3_1_rpnl(52) and tlb_tag4_q(tagpos_ind) and tlb0cfg_ind)) & + tlb_tag4_q(tagpos_pt) & tlb_tag4_q(tagpos_recform) & "00" & tlb_tag4_q(tagpos_pid to tagpos_pid+pid_width-1); +tlb_datain_hi_gs_tlbwe_2_nopar <= + mmucr3_2(49) & "000" & lrat_tag4_rpn_sig(22 to 51) & mmucr3_2(50 to 51) & + mmucr3_2(56 to 58) & mas8_2_vf & (tlb_tag4_q(tagpos_ind) and tlb0cfg_ind) & mas3_2_ubits & mas2_2_wimge & + mas3_2_usxwr(0 to 3) & + (mas3_2_usxwr(4) and (not tlb_tag4_q(tagpos_ind) or not tlb0cfg_ind)) & + ((mas3_2_usxwr(5) and (not tlb_tag4_q(tagpos_ind) or not tlb0cfg_ind)) or (mas3_2_rpnl(52) and tlb_tag4_q(tagpos_ind) and tlb0cfg_ind)) & + tlb_tag4_q(tagpos_pt) & tlb_tag4_q(tagpos_recform) & "00" & tlb_tag4_q(tagpos_pid to tagpos_pid+pid_width-1); +tlb_datain_hi_gs_tlbwe_3_nopar <= + mmucr3_3(49) & "000" & lrat_tag4_rpn_sig(22 to 51) & mmucr3_3(50 to 51) & + mmucr3_3(56 to 58) & mas8_3_vf & (tlb_tag4_q(tagpos_ind) and tlb0cfg_ind) & mas3_3_ubits & mas2_3_wimge & + mas3_3_usxwr(0 to 3) & + (mas3_3_usxwr(4) and (not tlb_tag4_q(tagpos_ind) or not tlb0cfg_ind)) & + ((mas3_3_usxwr(5) and (not tlb_tag4_q(tagpos_ind) or not tlb0cfg_ind)) or (mas3_3_rpnl(52) and tlb_tag4_q(tagpos_ind) and tlb0cfg_ind)) & + tlb_tag4_q(tagpos_pt) & tlb_tag4_q(tagpos_recform) & "00" & tlb_tag4_q(tagpos_pid to tagpos_pid+pid_width-1); +tlb_datain_hi_hv_ptereload_nopar <= + '0' & "000" & ptereload_req_pte_lat(ptepos_rpn+10 to ptepos_rpn+39) & ptereload_req_pte_lat(ptepos_r) & ptereload_req_pte_lat(ptepos_c) & + "00" & '0' & '0' & '0' & ptereload_req_pte_lat(ptepos_ubits to ptepos_ubits+3) & ptereload_req_pte_lat(ptepos_wimge to ptepos_wimge+4) & + ptereload_req_derived_usxwr(0 to 5) & + tlb_tag4_q(tagpos_gs) & tlb_tag4_q(tagpos_as) & "00" & tlb_tag4_q(tagpos_pid to tagpos_pid+pid_width-1); +tlb_datain_hi_gs_ptereload_nopar <= + '0' & "000" & lrat_tag4_rpn_sig(22 to 51) & ptereload_req_pte_lat(ptepos_r) & ptereload_req_pte_lat(ptepos_c) & + "00" & '0' & '0' & '0' & ptereload_req_pte_lat(ptepos_ubits to ptepos_ubits+3) & ptereload_req_pte_lat(ptepos_wimge to ptepos_wimge+4) & + ptereload_req_derived_usxwr(0 to 5) & + tlb_tag4_q(tagpos_gs) & tlb_tag4_q(tagpos_as) & "00" & tlb_tag4_q(tagpos_pid to tagpos_pid+pid_width-1); +tlb_dataina_d(tlb_word_width TO 2*tlb_word_width-1) <= + tlb_datain_hi_hv_tlbwe_0_nopar & tlb_datain_hi_hv_tlbwe_0_par + when (tlb_tag4_q(tagpos_thdid+0)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1' and (tlb_tag4_q(tagpos_gs)='0' or tlb_tag4_q(tagpos_is)='0')) else + tlb_datain_hi_hv_tlbwe_1_nopar & tlb_datain_hi_hv_tlbwe_1_par + when (tlb_tag4_q(tagpos_thdid+1)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1' and (tlb_tag4_q(tagpos_gs)='0' or tlb_tag4_q(tagpos_is)='0')) else + tlb_datain_hi_hv_tlbwe_2_nopar & tlb_datain_hi_hv_tlbwe_2_par + when (tlb_tag4_q(tagpos_thdid+2)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1' and (tlb_tag4_q(tagpos_gs)='0' or tlb_tag4_q(tagpos_is)='0')) else + tlb_datain_hi_hv_tlbwe_3_nopar & tlb_datain_hi_hv_tlbwe_3_par + when (tlb_tag4_q(tagpos_thdid+3)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1' and (tlb_tag4_q(tagpos_gs)='0' or tlb_tag4_q(tagpos_is)='0')) else + tlb_datain_hi_gs_tlbwe_0_nopar & tlb_datain_hi_gs_tlbwe_0_par + when (tlb_tag4_q(tagpos_thdid+0)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1' and tlb_tag4_q(tagpos_gs)='1' and tlb_tag4_q(tagpos_is)='1') else + tlb_datain_hi_gs_tlbwe_1_nopar & tlb_datain_hi_gs_tlbwe_1_par + when (tlb_tag4_q(tagpos_thdid+1)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1' and tlb_tag4_q(tagpos_gs)='1' and tlb_tag4_q(tagpos_is)='1') else + tlb_datain_hi_gs_tlbwe_2_nopar & tlb_datain_hi_gs_tlbwe_2_par + when (tlb_tag4_q(tagpos_thdid+2)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1' and tlb_tag4_q(tagpos_gs)='1' and tlb_tag4_q(tagpos_is)='1') else + tlb_datain_hi_gs_tlbwe_3_nopar & tlb_datain_hi_gs_tlbwe_3_par + when (tlb_tag4_q(tagpos_thdid+3)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1' and tlb_tag4_q(tagpos_gs)='1' and tlb_tag4_q(tagpos_is)='1') else + tlb_datain_hi_hv_ptereload_nopar & tlb_datain_hi_hv_ptereload_par + when (tlb_tag4_ptereload_sig='1' and tlb_tag4_q(tagpos_gs)='0') else + tlb_datain_hi_gs_ptereload_nopar & tlb_datain_hi_gs_ptereload_par + when (tlb_tag4_ptereload_sig='1' and tlb_tag4_q(tagpos_gs)='1') else + tlb_dataina_q(tlb_word_width to 2*tlb_word_width-1); +tlb_datainb_d(tlb_word_width TO 2*tlb_word_width-1) <= + tlb_datain_hi_hv_tlbwe_0_nopar & tlb_datain_hi_hv_tlbwe_0_par + when (tlb_tag4_q(tagpos_thdid+0)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1' and (tlb_tag4_q(tagpos_gs)='0' or tlb_tag4_q(tagpos_is)='0')) else + tlb_datain_hi_hv_tlbwe_1_nopar & tlb_datain_hi_hv_tlbwe_1_par + when (tlb_tag4_q(tagpos_thdid+1)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1' and (tlb_tag4_q(tagpos_gs)='0' or tlb_tag4_q(tagpos_is)='0')) else + tlb_datain_hi_hv_tlbwe_2_nopar & tlb_datain_hi_hv_tlbwe_2_par + when (tlb_tag4_q(tagpos_thdid+2)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1' and (tlb_tag4_q(tagpos_gs)='0' or tlb_tag4_q(tagpos_is)='0')) else + tlb_datain_hi_hv_tlbwe_3_nopar & tlb_datain_hi_hv_tlbwe_3_par + when (tlb_tag4_q(tagpos_thdid+3)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1' and (tlb_tag4_q(tagpos_gs)='0' or tlb_tag4_q(tagpos_is)='0')) else + tlb_datain_hi_gs_tlbwe_0_nopar & tlb_datain_hi_gs_tlbwe_0_par + when (tlb_tag4_q(tagpos_thdid+0)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1' and tlb_tag4_q(tagpos_gs)='1' and tlb_tag4_q(tagpos_is)='1') else + tlb_datain_hi_gs_tlbwe_1_nopar & tlb_datain_hi_gs_tlbwe_1_par + when (tlb_tag4_q(tagpos_thdid+1)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1' and tlb_tag4_q(tagpos_gs)='1' and tlb_tag4_q(tagpos_is)='1') else + tlb_datain_hi_gs_tlbwe_2_nopar & tlb_datain_hi_gs_tlbwe_2_par + when (tlb_tag4_q(tagpos_thdid+2)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1' and tlb_tag4_q(tagpos_gs)='1' and tlb_tag4_q(tagpos_is)='1') else + tlb_datain_hi_gs_tlbwe_3_nopar & tlb_datain_hi_gs_tlbwe_3_par + when (tlb_tag4_q(tagpos_thdid+3)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1' and tlb_tag4_q(tagpos_gs)='1' and tlb_tag4_q(tagpos_is)='1') else + tlb_datain_hi_hv_ptereload_nopar & tlb_datain_hi_hv_ptereload_par + when (tlb_tag4_ptereload_sig='1' and tlb_tag4_q(tagpos_gs)='0') else + tlb_datain_hi_gs_ptereload_nopar & tlb_datain_hi_gs_ptereload_par + when (tlb_tag4_ptereload_sig='1' and tlb_tag4_q(tagpos_gs)='1') else + tlb_datainb_q(tlb_word_width to 2*tlb_word_width-1); +tlb_datain_lo_tlbwe_0_par(0) <= xor_reduce(tlb_datain_lo_tlbwe_0_nopar(0 to 7)); +tlb_datain_lo_tlbwe_0_par(1) <= xor_reduce(tlb_datain_lo_tlbwe_0_nopar(8 to 15)); +tlb_datain_lo_tlbwe_0_par(2) <= xor_reduce(tlb_datain_lo_tlbwe_0_nopar(16 to 23)); +tlb_datain_lo_tlbwe_0_par(3) <= xor_reduce(tlb_datain_lo_tlbwe_0_nopar(24 to 31)); +tlb_datain_lo_tlbwe_0_par(4) <= xor_reduce(tlb_datain_lo_tlbwe_0_nopar(32 to 39)); +tlb_datain_lo_tlbwe_0_par(5) <= xor_reduce(tlb_datain_lo_tlbwe_0_nopar(40 to 47)); +tlb_datain_lo_tlbwe_0_par(7) <= xor_reduce(tlb_datain_lo_tlbwe_0_nopar(52 to 59)); +tlb_datain_lo_tlbwe_0_par(8) <= xor_reduce(tlb_datain_lo_tlbwe_0_nopar(60 to 65)); +tlb_datain_lo_tlbwe_0_par(9) <= xor_reduce(tlb_datain_lo_tlbwe_0_nopar(66 to 73)); +tlb_datain_lo_tlbwe_1_par(0) <= xor_reduce(tlb_datain_lo_tlbwe_1_nopar(0 to 7)); +tlb_datain_lo_tlbwe_1_par(1) <= xor_reduce(tlb_datain_lo_tlbwe_1_nopar(8 to 15)); +tlb_datain_lo_tlbwe_1_par(2) <= xor_reduce(tlb_datain_lo_tlbwe_1_nopar(16 to 23)); +tlb_datain_lo_tlbwe_1_par(3) <= xor_reduce(tlb_datain_lo_tlbwe_1_nopar(24 to 31)); +tlb_datain_lo_tlbwe_1_par(4) <= xor_reduce(tlb_datain_lo_tlbwe_1_nopar(32 to 39)); +tlb_datain_lo_tlbwe_1_par(5) <= xor_reduce(tlb_datain_lo_tlbwe_1_nopar(40 to 47)); +tlb_datain_lo_tlbwe_1_par(7) <= xor_reduce(tlb_datain_lo_tlbwe_1_nopar(52 to 59)); +tlb_datain_lo_tlbwe_1_par(8) <= xor_reduce(tlb_datain_lo_tlbwe_1_nopar(60 to 65)); +tlb_datain_lo_tlbwe_1_par(9) <= xor_reduce(tlb_datain_lo_tlbwe_1_nopar(66 to 73)); +tlb_datain_lo_tlbwe_2_par(0) <= xor_reduce(tlb_datain_lo_tlbwe_2_nopar(0 to 7)); +tlb_datain_lo_tlbwe_2_par(1) <= xor_reduce(tlb_datain_lo_tlbwe_2_nopar(8 to 15)); +tlb_datain_lo_tlbwe_2_par(2) <= xor_reduce(tlb_datain_lo_tlbwe_2_nopar(16 to 23)); +tlb_datain_lo_tlbwe_2_par(3) <= xor_reduce(tlb_datain_lo_tlbwe_2_nopar(24 to 31)); +tlb_datain_lo_tlbwe_2_par(4) <= xor_reduce(tlb_datain_lo_tlbwe_2_nopar(32 to 39)); +tlb_datain_lo_tlbwe_2_par(5) <= xor_reduce(tlb_datain_lo_tlbwe_2_nopar(40 to 47)); +tlb_datain_lo_tlbwe_2_par(7) <= xor_reduce(tlb_datain_lo_tlbwe_2_nopar(52 to 59)); +tlb_datain_lo_tlbwe_2_par(8) <= xor_reduce(tlb_datain_lo_tlbwe_2_nopar(60 to 65)); +tlb_datain_lo_tlbwe_2_par(9) <= xor_reduce(tlb_datain_lo_tlbwe_2_nopar(66 to 73)); +tlb_datain_lo_tlbwe_3_par(0) <= xor_reduce(tlb_datain_lo_tlbwe_3_nopar(0 to 7)); +tlb_datain_lo_tlbwe_3_par(1) <= xor_reduce(tlb_datain_lo_tlbwe_3_nopar(8 to 15)); +tlb_datain_lo_tlbwe_3_par(2) <= xor_reduce(tlb_datain_lo_tlbwe_3_nopar(16 to 23)); +tlb_datain_lo_tlbwe_3_par(3) <= xor_reduce(tlb_datain_lo_tlbwe_3_nopar(24 to 31)); +tlb_datain_lo_tlbwe_3_par(4) <= xor_reduce(tlb_datain_lo_tlbwe_3_nopar(32 to 39)); +tlb_datain_lo_tlbwe_3_par(5) <= xor_reduce(tlb_datain_lo_tlbwe_3_nopar(40 to 47)); +tlb_datain_lo_tlbwe_3_par(7) <= xor_reduce(tlb_datain_lo_tlbwe_3_nopar(52 to 59)); +tlb_datain_lo_tlbwe_3_par(8) <= xor_reduce(tlb_datain_lo_tlbwe_3_nopar(60 to 65)); +tlb_datain_lo_tlbwe_3_par(9) <= xor_reduce(tlb_datain_lo_tlbwe_3_nopar(66 to 73)); +tlb_datain_lo_tlbwe_0_par(6) <= xor_reduce(tlb_datain_lo_tlbwe_0_nopar(48 to 51) & mmucr1_q(pos_tlb_pei)); +tlb_datain_lo_tlbwe_1_par(6) <= xor_reduce(tlb_datain_lo_tlbwe_1_nopar(48 to 51) & mmucr1_q(pos_tlb_pei)); +tlb_datain_lo_tlbwe_2_par(6) <= xor_reduce(tlb_datain_lo_tlbwe_2_nopar(48 to 51) & mmucr1_clone_q(pos_tlb_pei)); +tlb_datain_lo_tlbwe_3_par(6) <= xor_reduce(tlb_datain_lo_tlbwe_3_nopar(48 to 51) & mmucr1_clone_q(pos_tlb_pei)); +tlb_datain_lo_ptereload_par(0) <= xor_reduce(tlb_datain_lo_ptereload_nopar(0 to 7)); +tlb_datain_lo_ptereload_par(1) <= xor_reduce(tlb_datain_lo_ptereload_nopar(8 to 15)); +tlb_datain_lo_ptereload_par(2) <= xor_reduce(tlb_datain_lo_ptereload_nopar(16 to 23)); +tlb_datain_lo_ptereload_par(3) <= xor_reduce(tlb_datain_lo_ptereload_nopar(24 to 31)); +tlb_datain_lo_ptereload_par(4) <= xor_reduce(tlb_datain_lo_ptereload_nopar(32 to 39)); +tlb_datain_lo_ptereload_par(5) <= xor_reduce(tlb_datain_lo_ptereload_nopar(40 to 47)); +tlb_datain_lo_ptereload_par(6) <= xor_reduce(tlb_datain_lo_ptereload_nopar(48 to 51)); +tlb_datain_lo_ptereload_par(7) <= xor_reduce(tlb_datain_lo_ptereload_nopar(52 to 59)); +tlb_datain_lo_ptereload_par(8) <= xor_reduce(tlb_datain_lo_ptereload_nopar(60 to 65)); +tlb_datain_lo_ptereload_par(9) <= xor_reduce(tlb_datain_lo_ptereload_nopar(66 to 73)); +tlb_datain_hi_hv_tlbwe_0_par(0) <= xor_reduce(tlb_datain_hi_hv_tlbwe_0_nopar(0 to 7)); +tlb_datain_hi_hv_tlbwe_0_par(1) <= xor_reduce(tlb_datain_hi_hv_tlbwe_0_nopar(8 to 15)); +tlb_datain_hi_hv_tlbwe_0_par(2) <= xor_reduce(tlb_datain_hi_hv_tlbwe_0_nopar(16 to 23)); +tlb_datain_hi_hv_tlbwe_0_par(3) <= xor_reduce(tlb_datain_hi_hv_tlbwe_0_nopar(24 to 31)); +tlb_datain_hi_hv_tlbwe_0_par(4) <= xor_reduce(tlb_datain_hi_hv_tlbwe_0_nopar(32 to 39)); +tlb_datain_hi_hv_tlbwe_0_par(5) <= xor_reduce(tlb_datain_hi_hv_tlbwe_0_nopar(40 to 44)); +tlb_datain_hi_hv_tlbwe_0_par(6) <= xor_reduce(tlb_datain_hi_hv_tlbwe_0_nopar(45 to 49)); +tlb_datain_hi_hv_tlbwe_0_par(7) <= xor_reduce(tlb_datain_hi_hv_tlbwe_0_nopar(50 to 57)); +tlb_datain_hi_hv_tlbwe_0_par(8) <= xor_reduce(tlb_datain_hi_hv_tlbwe_0_nopar(58 to 65)); +tlb_datain_hi_hv_tlbwe_0_par(9) <= xor_reduce(tlb_datain_hi_hv_tlbwe_0_nopar(66 to 73)); +tlb_datain_hi_hv_tlbwe_1_par(0) <= xor_reduce(tlb_datain_hi_hv_tlbwe_1_nopar(0 to 7)); +tlb_datain_hi_hv_tlbwe_1_par(1) <= xor_reduce(tlb_datain_hi_hv_tlbwe_1_nopar(8 to 15)); +tlb_datain_hi_hv_tlbwe_1_par(2) <= xor_reduce(tlb_datain_hi_hv_tlbwe_1_nopar(16 to 23)); +tlb_datain_hi_hv_tlbwe_1_par(3) <= xor_reduce(tlb_datain_hi_hv_tlbwe_1_nopar(24 to 31)); +tlb_datain_hi_hv_tlbwe_1_par(4) <= xor_reduce(tlb_datain_hi_hv_tlbwe_1_nopar(32 to 39)); +tlb_datain_hi_hv_tlbwe_1_par(5) <= xor_reduce(tlb_datain_hi_hv_tlbwe_1_nopar(40 to 44)); +tlb_datain_hi_hv_tlbwe_1_par(6) <= xor_reduce(tlb_datain_hi_hv_tlbwe_1_nopar(45 to 49)); +tlb_datain_hi_hv_tlbwe_1_par(7) <= xor_reduce(tlb_datain_hi_hv_tlbwe_1_nopar(50 to 57)); +tlb_datain_hi_hv_tlbwe_1_par(8) <= xor_reduce(tlb_datain_hi_hv_tlbwe_1_nopar(58 to 65)); +tlb_datain_hi_hv_tlbwe_1_par(9) <= xor_reduce(tlb_datain_hi_hv_tlbwe_1_nopar(66 to 73)); +tlb_datain_hi_hv_tlbwe_2_par(0) <= xor_reduce(tlb_datain_hi_hv_tlbwe_2_nopar(0 to 7)); +tlb_datain_hi_hv_tlbwe_2_par(1) <= xor_reduce(tlb_datain_hi_hv_tlbwe_2_nopar(8 to 15)); +tlb_datain_hi_hv_tlbwe_2_par(2) <= xor_reduce(tlb_datain_hi_hv_tlbwe_2_nopar(16 to 23)); +tlb_datain_hi_hv_tlbwe_2_par(3) <= xor_reduce(tlb_datain_hi_hv_tlbwe_2_nopar(24 to 31)); +tlb_datain_hi_hv_tlbwe_2_par(4) <= xor_reduce(tlb_datain_hi_hv_tlbwe_2_nopar(32 to 39)); +tlb_datain_hi_hv_tlbwe_2_par(5) <= xor_reduce(tlb_datain_hi_hv_tlbwe_2_nopar(40 to 44)); +tlb_datain_hi_hv_tlbwe_2_par(6) <= xor_reduce(tlb_datain_hi_hv_tlbwe_2_nopar(45 to 49)); +tlb_datain_hi_hv_tlbwe_2_par(7) <= xor_reduce(tlb_datain_hi_hv_tlbwe_2_nopar(50 to 57)); +tlb_datain_hi_hv_tlbwe_2_par(8) <= xor_reduce(tlb_datain_hi_hv_tlbwe_2_nopar(58 to 65)); +tlb_datain_hi_hv_tlbwe_2_par(9) <= xor_reduce(tlb_datain_hi_hv_tlbwe_2_nopar(66 to 73)); +tlb_datain_hi_hv_tlbwe_3_par(0) <= xor_reduce(tlb_datain_hi_hv_tlbwe_3_nopar(0 to 7)); +tlb_datain_hi_hv_tlbwe_3_par(1) <= xor_reduce(tlb_datain_hi_hv_tlbwe_3_nopar(8 to 15)); +tlb_datain_hi_hv_tlbwe_3_par(2) <= xor_reduce(tlb_datain_hi_hv_tlbwe_3_nopar(16 to 23)); +tlb_datain_hi_hv_tlbwe_3_par(3) <= xor_reduce(tlb_datain_hi_hv_tlbwe_3_nopar(24 to 31)); +tlb_datain_hi_hv_tlbwe_3_par(4) <= xor_reduce(tlb_datain_hi_hv_tlbwe_3_nopar(32 to 39)); +tlb_datain_hi_hv_tlbwe_3_par(5) <= xor_reduce(tlb_datain_hi_hv_tlbwe_3_nopar(40 to 44)); +tlb_datain_hi_hv_tlbwe_3_par(6) <= xor_reduce(tlb_datain_hi_hv_tlbwe_3_nopar(45 to 49)); +tlb_datain_hi_hv_tlbwe_3_par(7) <= xor_reduce(tlb_datain_hi_hv_tlbwe_3_nopar(50 to 57)); +tlb_datain_hi_hv_tlbwe_3_par(8) <= xor_reduce(tlb_datain_hi_hv_tlbwe_3_nopar(58 to 65)); +tlb_datain_hi_hv_tlbwe_3_par(9) <= xor_reduce(tlb_datain_hi_hv_tlbwe_3_nopar(66 to 73)); +tlb_datain_hi_gs_tlbwe_0_par(0) <= xor_reduce(tlb_datain_hi_gs_tlbwe_0_nopar(0 to 7)); +tlb_datain_hi_gs_tlbwe_0_par(1) <= xor_reduce(tlb_datain_hi_gs_tlbwe_0_nopar(8 to 15)); +tlb_datain_hi_gs_tlbwe_0_par(2) <= xor_reduce(tlb_datain_hi_gs_tlbwe_0_nopar(16 to 23)); +tlb_datain_hi_gs_tlbwe_0_par(3) <= xor_reduce(tlb_datain_hi_gs_tlbwe_0_nopar(24 to 31)); +tlb_datain_hi_gs_tlbwe_0_par(4) <= xor_reduce(tlb_datain_hi_gs_tlbwe_0_nopar(32 to 39)); +tlb_datain_hi_gs_tlbwe_0_par(5) <= xor_reduce(tlb_datain_hi_gs_tlbwe_0_nopar(40 to 44)); +tlb_datain_hi_gs_tlbwe_0_par(6) <= xor_reduce(tlb_datain_hi_gs_tlbwe_0_nopar(45 to 49)); +tlb_datain_hi_gs_tlbwe_0_par(7) <= xor_reduce(tlb_datain_hi_gs_tlbwe_0_nopar(50 to 57)); +tlb_datain_hi_gs_tlbwe_0_par(8) <= xor_reduce(tlb_datain_hi_gs_tlbwe_0_nopar(58 to 65)); +tlb_datain_hi_gs_tlbwe_0_par(9) <= xor_reduce(tlb_datain_hi_gs_tlbwe_0_nopar(66 to 73)); +tlb_datain_hi_gs_tlbwe_1_par(0) <= xor_reduce(tlb_datain_hi_gs_tlbwe_1_nopar(0 to 7)); +tlb_datain_hi_gs_tlbwe_1_par(1) <= xor_reduce(tlb_datain_hi_gs_tlbwe_1_nopar(8 to 15)); +tlb_datain_hi_gs_tlbwe_1_par(2) <= xor_reduce(tlb_datain_hi_gs_tlbwe_1_nopar(16 to 23)); +tlb_datain_hi_gs_tlbwe_1_par(3) <= xor_reduce(tlb_datain_hi_gs_tlbwe_1_nopar(24 to 31)); +tlb_datain_hi_gs_tlbwe_1_par(4) <= xor_reduce(tlb_datain_hi_gs_tlbwe_1_nopar(32 to 39)); +tlb_datain_hi_gs_tlbwe_1_par(5) <= xor_reduce(tlb_datain_hi_gs_tlbwe_1_nopar(40 to 44)); +tlb_datain_hi_gs_tlbwe_1_par(6) <= xor_reduce(tlb_datain_hi_gs_tlbwe_1_nopar(45 to 49)); +tlb_datain_hi_gs_tlbwe_1_par(7) <= xor_reduce(tlb_datain_hi_gs_tlbwe_1_nopar(50 to 57)); +tlb_datain_hi_gs_tlbwe_1_par(8) <= xor_reduce(tlb_datain_hi_gs_tlbwe_1_nopar(58 to 65)); +tlb_datain_hi_gs_tlbwe_1_par(9) <= xor_reduce(tlb_datain_hi_gs_tlbwe_1_nopar(66 to 73)); +tlb_datain_hi_gs_tlbwe_2_par(0) <= xor_reduce(tlb_datain_hi_gs_tlbwe_2_nopar(0 to 7)); +tlb_datain_hi_gs_tlbwe_2_par(1) <= xor_reduce(tlb_datain_hi_gs_tlbwe_2_nopar(8 to 15)); +tlb_datain_hi_gs_tlbwe_2_par(2) <= xor_reduce(tlb_datain_hi_gs_tlbwe_2_nopar(16 to 23)); +tlb_datain_hi_gs_tlbwe_2_par(3) <= xor_reduce(tlb_datain_hi_gs_tlbwe_2_nopar(24 to 31)); +tlb_datain_hi_gs_tlbwe_2_par(4) <= xor_reduce(tlb_datain_hi_gs_tlbwe_2_nopar(32 to 39)); +tlb_datain_hi_gs_tlbwe_2_par(5) <= xor_reduce(tlb_datain_hi_gs_tlbwe_2_nopar(40 to 44)); +tlb_datain_hi_gs_tlbwe_2_par(6) <= xor_reduce(tlb_datain_hi_gs_tlbwe_2_nopar(45 to 49)); +tlb_datain_hi_gs_tlbwe_2_par(7) <= xor_reduce(tlb_datain_hi_gs_tlbwe_2_nopar(50 to 57)); +tlb_datain_hi_gs_tlbwe_2_par(8) <= xor_reduce(tlb_datain_hi_gs_tlbwe_2_nopar(58 to 65)); +tlb_datain_hi_gs_tlbwe_2_par(9) <= xor_reduce(tlb_datain_hi_gs_tlbwe_2_nopar(66 to 73)); +tlb_datain_hi_gs_tlbwe_3_par(0) <= xor_reduce(tlb_datain_hi_gs_tlbwe_3_nopar(0 to 7)); +tlb_datain_hi_gs_tlbwe_3_par(1) <= xor_reduce(tlb_datain_hi_gs_tlbwe_3_nopar(8 to 15)); +tlb_datain_hi_gs_tlbwe_3_par(2) <= xor_reduce(tlb_datain_hi_gs_tlbwe_3_nopar(16 to 23)); +tlb_datain_hi_gs_tlbwe_3_par(3) <= xor_reduce(tlb_datain_hi_gs_tlbwe_3_nopar(24 to 31)); +tlb_datain_hi_gs_tlbwe_3_par(4) <= xor_reduce(tlb_datain_hi_gs_tlbwe_3_nopar(32 to 39)); +tlb_datain_hi_gs_tlbwe_3_par(5) <= xor_reduce(tlb_datain_hi_gs_tlbwe_3_nopar(40 to 44)); +tlb_datain_hi_gs_tlbwe_3_par(6) <= xor_reduce(tlb_datain_hi_gs_tlbwe_3_nopar(45 to 49)); +tlb_datain_hi_gs_tlbwe_3_par(7) <= xor_reduce(tlb_datain_hi_gs_tlbwe_3_nopar(50 to 57)); +tlb_datain_hi_gs_tlbwe_3_par(8) <= xor_reduce(tlb_datain_hi_gs_tlbwe_3_nopar(58 to 65)); +tlb_datain_hi_gs_tlbwe_3_par(9) <= xor_reduce(tlb_datain_hi_gs_tlbwe_3_nopar(66 to 73)); +tlb_datain_hi_hv_ptereload_par(0) <= xor_reduce(tlb_datain_hi_hv_ptereload_nopar(0 to 7)); +tlb_datain_hi_hv_ptereload_par(1) <= xor_reduce(tlb_datain_hi_hv_ptereload_nopar(8 to 15)); +tlb_datain_hi_hv_ptereload_par(2) <= xor_reduce(tlb_datain_hi_hv_ptereload_nopar(16 to 23)); +tlb_datain_hi_hv_ptereload_par(3) <= xor_reduce(tlb_datain_hi_hv_ptereload_nopar(24 to 31)); +tlb_datain_hi_hv_ptereload_par(4) <= xor_reduce(tlb_datain_hi_hv_ptereload_nopar(32 to 39)); +tlb_datain_hi_hv_ptereload_par(5) <= xor_reduce(tlb_datain_hi_hv_ptereload_nopar(40 to 44)); +tlb_datain_hi_hv_ptereload_par(6) <= xor_reduce(tlb_datain_hi_hv_ptereload_nopar(45 to 49)); +tlb_datain_hi_hv_ptereload_par(7) <= xor_reduce(tlb_datain_hi_hv_ptereload_nopar(50 to 57)); +tlb_datain_hi_hv_ptereload_par(8) <= xor_reduce(tlb_datain_hi_hv_ptereload_nopar(58 to 65)); +tlb_datain_hi_hv_ptereload_par(9) <= xor_reduce(tlb_datain_hi_hv_ptereload_nopar(66 to 73)); +tlb_datain_hi_gs_ptereload_par(0) <= xor_reduce(tlb_datain_hi_gs_ptereload_nopar(0 to 7)); +tlb_datain_hi_gs_ptereload_par(1) <= xor_reduce(tlb_datain_hi_gs_ptereload_nopar(8 to 15)); +tlb_datain_hi_gs_ptereload_par(2) <= xor_reduce(tlb_datain_hi_gs_ptereload_nopar(16 to 23)); +tlb_datain_hi_gs_ptereload_par(3) <= xor_reduce(tlb_datain_hi_gs_ptereload_nopar(24 to 31)); +tlb_datain_hi_gs_ptereload_par(4) <= xor_reduce(tlb_datain_hi_gs_ptereload_nopar(32 to 39)); +tlb_datain_hi_gs_ptereload_par(5) <= xor_reduce(tlb_datain_hi_gs_ptereload_nopar(40 to 44)); +tlb_datain_hi_gs_ptereload_par(6) <= xor_reduce(tlb_datain_hi_gs_ptereload_nopar(45 to 49)); +tlb_datain_hi_gs_ptereload_par(7) <= xor_reduce(tlb_datain_hi_gs_ptereload_nopar(50 to 57)); +tlb_datain_hi_gs_ptereload_par(8) <= xor_reduce(tlb_datain_hi_gs_ptereload_nopar(58 to 65)); +tlb_datain_hi_gs_ptereload_par(9) <= xor_reduce(tlb_datain_hi_gs_ptereload_nopar(66 to 73)); +tlb_dataina <= tlb_dataina_q; +tlb_datainb <= tlb_datainb_q; +tlb_cmp_dbg_tag5_tlb_datain_q <= tlb_dataina_q; +tlb_erat_rel_d(eratpos_epn TO epn_width-1) <= tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-1) + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_q(eratpos_epn to epn_width-1); +tlb_erat_rel_d(eratpos_x) <= tlb_tag4_way_or(waypos_xbit) + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_q(eratpos_x); +tlb_erat_rel_d(eratpos_size TO eratpos_size+2) <= erat_pgsize(0 to 2) + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_q(eratpos_size to eratpos_size+2); +tlb_erat_rel_d(eratpos_v) <= '1' + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_q(eratpos_v); +tlb_erat_rel_clone_d(eratpos_epn TO epn_width-1) <= tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-1) + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_clone_q(eratpos_epn to epn_width-1); +tlb_erat_rel_clone_d(eratpos_x) <= tlb_tag4_way_or(waypos_xbit) + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_clone_q(eratpos_x); +tlb_erat_rel_clone_d(eratpos_size TO eratpos_size+2) <= erat_pgsize(0 to 2) + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_clone_q(eratpos_size to eratpos_size+2); +tlb_erat_rel_clone_d(eratpos_v) <= '1' + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_clone_q(eratpos_v); +tlb_erat_rel_d(eratpos_thdid TO eratpos_thdid+thdid_width-1) <= + tlb_tag4_way_or(waypos_thdid to waypos_thdid+thdid_width-1) + when ((tlb_tag4_q(tagpos_type_ierat)='1' and tlb_tag4_q(tagpos_type_ptereload)='0' and mmucr1_q(pos_ittid)='0' and tlb_tag4_q(tagpos_ind)='0') or + (tlb_tag4_q(tagpos_type_derat)='1' and tlb_tag4_q(tagpos_type_ptereload)='0' and mmucr1_q(pos_dttid)='0' and tlb_tag4_q(tagpos_ind)='0')) + else tlb_tag4_way_or(waypos_tid+2 to waypos_tid+5) + when ((tlb_tag4_q(tagpos_type_ierat)='1' and tlb_tag4_q(tagpos_type_ptereload)='0' and mmucr1_q(pos_ittid)='1' and tlb_tag4_q(tagpos_ind)='0') or + (tlb_tag4_q(tagpos_type_derat)='1' and tlb_tag4_q(tagpos_type_ptereload)='0' and mmucr1_q(pos_dttid)='1' and tlb_tag4_q(tagpos_ind)='0')) + else (tlb_tag4_q(tagpos_atsel) & tlb_tag4_q(tagpos_esel to tagpos_esel+2)) + when ((tlb_tag4_q(tagpos_type_ierat)='1' and tlb_tag4_q(tagpos_type_ptereload)='1' and mmucr1_q(pos_ittid)='0' and tlb_tag4_q(tagpos_ind)='0') or + (tlb_tag4_q(tagpos_type_derat)='1' and tlb_tag4_q(tagpos_type_ptereload)='1' and mmucr1_q(pos_dttid)='0' and tlb_tag4_q(tagpos_ind)='0')) + else tlb_tag4_q(tagpos_pid+2 to tagpos_pid+5) + when ((tlb_tag4_q(tagpos_type_ierat)='1' and tlb_tag4_q(tagpos_type_ptereload)='1' and mmucr1_q(pos_ittid)='1' and tlb_tag4_q(tagpos_ind)='0') or + (tlb_tag4_q(tagpos_type_derat)='1' and tlb_tag4_q(tagpos_type_ptereload)='1' and mmucr1_q(pos_dttid)='1' and tlb_tag4_q(tagpos_ind)='0')) + else tlb_erat_rel_q(eratpos_thdid to eratpos_thdid+thdid_width-1); +tlb_erat_rel_clone_d(eratpos_thdid TO eratpos_thdid+thdid_width-1) <= + tlb_tag4_way_or(waypos_thdid to waypos_thdid+thdid_width-1) + when ((tlb_tag4_q(tagpos_type_ierat)='1' and tlb_tag4_q(tagpos_type_ptereload)='0' and mmucr1_clone_q(pos_ittid)='0' and tlb_tag4_q(tagpos_ind)='0') or + (tlb_tag4_q(tagpos_type_derat)='1' and tlb_tag4_q(tagpos_type_ptereload)='0' and mmucr1_clone_q(pos_dttid)='0' and tlb_tag4_q(tagpos_ind)='0')) + else tlb_tag4_way_or(waypos_tid+2 to waypos_tid+5) + when ((tlb_tag4_q(tagpos_type_ierat)='1' and tlb_tag4_q(tagpos_type_ptereload)='0' and mmucr1_clone_q(pos_ittid)='1' and tlb_tag4_q(tagpos_ind)='0') or + (tlb_tag4_q(tagpos_type_derat)='1' and tlb_tag4_q(tagpos_type_ptereload)='0' and mmucr1_clone_q(pos_dttid)='1' and tlb_tag4_q(tagpos_ind)='0')) + else (tlb_tag4_q(tagpos_atsel) & tlb_tag4_q(tagpos_esel to tagpos_esel+2)) + when ((tlb_tag4_q(tagpos_type_ierat)='1' and tlb_tag4_q(tagpos_type_ptereload)='1' and mmucr1_clone_q(pos_ittid)='0' and tlb_tag4_q(tagpos_ind)='0') or + (tlb_tag4_q(tagpos_type_derat)='1' and tlb_tag4_q(tagpos_type_ptereload)='1' and mmucr1_clone_q(pos_dttid)='0' and tlb_tag4_q(tagpos_ind)='0')) + else tlb_tag4_q(tagpos_pid+2 to tagpos_pid+5) + when ((tlb_tag4_q(tagpos_type_ierat)='1' and tlb_tag4_q(tagpos_type_ptereload)='1' and mmucr1_clone_q(pos_ittid)='1' and tlb_tag4_q(tagpos_ind)='0') or + (tlb_tag4_q(tagpos_type_derat)='1' and tlb_tag4_q(tagpos_type_ptereload)='1' and mmucr1_clone_q(pos_dttid)='1' and tlb_tag4_q(tagpos_ind)='0')) + else tlb_erat_rel_clone_q(eratpos_thdid to eratpos_thdid+thdid_width-1); +tlb_erat_rel_d(eratpos_class TO eratpos_class+class_width-1) <= + tlb_tag4_way_or(waypos_class to waypos_class+class_width-1) + when tlb_tag4_erat_data_cap='1' and + ((tlb_tag4_q(tagpos_type_ierat)='1' and tlb_tag4_q(tagpos_type_ptereload)='0' and mmucr1_q(pos_ictid)='0' and tlb_tag4_q(tagpos_ind)='0') or + (tlb_tag4_q(tagpos_type_derat)='1' and tlb_tag4_q(tagpos_type_ptereload)='0' and mmucr1_q(pos_dctid)='0' and mmucr1_q(pos_dccd)='1' and tlb_tag4_q(tagpos_ind)='0')) + else tlb_tag4_way_or(waypos_tid+0 to waypos_tid+1) + when tlb_tag4_erat_data_cap='1' and + ((tlb_tag4_q(tagpos_type_ierat)='1' and tlb_tag4_q(tagpos_type_ptereload)='0' and mmucr1_q(pos_ictid)='1' and tlb_tag4_q(tagpos_ind)='0') or + (tlb_tag4_q(tagpos_type_derat)='1' and tlb_tag4_q(tagpos_type_ptereload)='0' and mmucr1_q(pos_dctid)='1' and tlb_tag4_q(tagpos_ind)='0')) + else ( tlb_tag4_q(tagpos_class) & ((tlb_tag4_q(tagpos_class) and tlb_tag4_q(tagpos_class+1)) or (not(tlb_tag4_q(tagpos_class)) and tlb_tag4_way_or(waypos_class+1))) ) + when (tlb_tag4_erat_data_cap='1' and + tlb_tag4_q(tagpos_type_derat)='1' and tlb_tag4_q(tagpos_type_ptereload)='0' and mmucr1_q(pos_dctid)='0' and mmucr1_q(pos_dccd)='0' and tlb_tag4_q(tagpos_ind)='0') + else (tlb_tag4_q(tagpos_class) & (tlb_tag4_q(tagpos_class) and tlb_tag4_q(tagpos_class+1))) + when tlb_tag4_erat_data_cap='1' and + ((tlb_tag4_q(tagpos_type_ierat)='1' and tlb_tag4_q(tagpos_type_ptereload)='1' and mmucr1_q(pos_ictid)='0' and tlb_tag4_q(tagpos_ind)='0') or + (tlb_tag4_q(tagpos_type_derat)='1' and tlb_tag4_q(tagpos_type_ptereload)='1' and mmucr1_q(pos_dctid)='0' and tlb_tag4_q(tagpos_ind)='0')) + else tlb_tag4_q(tagpos_pid+0 to tagpos_pid+1) + when tlb_tag4_erat_data_cap='1' and + ((tlb_tag4_q(tagpos_type_ierat)='1' and tlb_tag4_q(tagpos_type_ptereload)='1' and mmucr1_q(pos_ictid)='1' and tlb_tag4_q(tagpos_ind)='0') or + (tlb_tag4_q(tagpos_type_derat)='1' and tlb_tag4_q(tagpos_type_ptereload)='1' and mmucr1_q(pos_dctid)='1' and tlb_tag4_q(tagpos_ind)='0')) + else tlb_erat_rel_q(eratpos_class to eratpos_class+class_width-1); +tlb_erat_rel_clone_d(eratpos_class TO eratpos_class+class_width-1) <= + tlb_tag4_way_or(waypos_class to waypos_class+class_width-1) + when tlb_tag4_erat_data_cap='1' and + ((tlb_tag4_q(tagpos_type_ierat)='1' and tlb_tag4_q(tagpos_type_ptereload)='0' and mmucr1_clone_q(pos_ictid)='0' and tlb_tag4_q(tagpos_ind)='0') or + (tlb_tag4_q(tagpos_type_derat)='1' and tlb_tag4_q(tagpos_type_ptereload)='0' and mmucr1_clone_q(pos_dctid)='0' and mmucr1_clone_q(pos_dccd)='1' and tlb_tag4_q(tagpos_ind)='0')) + else tlb_tag4_way_or(waypos_tid+0 to waypos_tid+1) + when tlb_tag4_erat_data_cap='1' and + ((tlb_tag4_q(tagpos_type_ierat)='1' and tlb_tag4_q(tagpos_type_ptereload)='0' and mmucr1_clone_q(pos_ictid)='1' and tlb_tag4_q(tagpos_ind)='0') or + (tlb_tag4_q(tagpos_type_derat)='1' and tlb_tag4_q(tagpos_type_ptereload)='0' and mmucr1_clone_q(pos_dctid)='1' and tlb_tag4_q(tagpos_ind)='0')) + else ( tlb_tag4_q(tagpos_class) & ((tlb_tag4_q(tagpos_class) and tlb_tag4_q(tagpos_class+1)) or (not(tlb_tag4_q(tagpos_class)) and tlb_tag4_way_or(waypos_class+1))) ) + when (tlb_tag4_erat_data_cap='1' and + tlb_tag4_q(tagpos_type_derat)='1' and tlb_tag4_q(tagpos_type_ptereload)='0' and mmucr1_clone_q(pos_dctid)='0' and mmucr1_clone_q(pos_dccd)='0' and tlb_tag4_q(tagpos_ind)='0') + else (tlb_tag4_q(tagpos_class) & (tlb_tag4_q(tagpos_class) and tlb_tag4_q(tagpos_class+1))) + when tlb_tag4_erat_data_cap='1' and + ((tlb_tag4_q(tagpos_type_ierat)='1' and tlb_tag4_q(tagpos_type_ptereload)='1' and mmucr1_clone_q(pos_ictid)='0' and tlb_tag4_q(tagpos_ind)='0') or + (tlb_tag4_q(tagpos_type_derat)='1' and tlb_tag4_q(tagpos_type_ptereload)='1' and mmucr1_clone_q(pos_dctid)='0' and tlb_tag4_q(tagpos_ind)='0')) + else tlb_tag4_q(tagpos_pid+0 to tagpos_pid+1) + when tlb_tag4_erat_data_cap='1' and + ((tlb_tag4_q(tagpos_type_ierat)='1' and tlb_tag4_q(tagpos_type_ptereload)='1' and mmucr1_clone_q(pos_ictid)='1' and tlb_tag4_q(tagpos_ind)='0') or + (tlb_tag4_q(tagpos_type_derat)='1' and tlb_tag4_q(tagpos_type_ptereload)='1' and mmucr1_clone_q(pos_dctid)='1' and tlb_tag4_q(tagpos_ind)='0')) + else tlb_erat_rel_clone_q(eratpos_class to eratpos_class+class_width-1); +tlb_erat_rel_d(eratpos_extclass TO eratpos_extclass+1) <= tlb_tag4_way_or(waypos_extclass to waypos_extclass+1) + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_q(eratpos_extclass to eratpos_extclass+1); +tlb_erat_rel_d(eratpos_wren) <= '1' when (tlb_tag4_erat_data_cap='1' and + (tlb_tag4_q(tagpos_type_ierat)='1' or tlb_tag4_q(tagpos_type_derat)='1') and + tlb_tag4_q(tagpos_type_ptereload)='0' and tlb_tag4_wayhit_q(tlb_ways)='1' and + tlb_tag4_q(tagpos_wq+1)='0' and tlb_tag4_q(tagpos_ind)='0' and multihit='0' + and or_reduce(tag4_parerr_q(0 to 4))='0') + else '0' when tlb_tag4_erat_data_cap='1' + else tlb_erat_rel_q(eratpos_wren); +tlb_erat_rel_d(eratpos_rpnrsvd TO eratpos_rpnrsvd+3) <= (others => '0'); +tlb_erat_rel_d(eratpos_rpn TO eratpos_rpn+rpn_width-1) <= tlb_tag4_way_or(waypos_rpn to waypos_rpn+rpn_width-1) + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_q(eratpos_rpn to eratpos_rpn+rpn_width-1); +tlb_erat_rel_d(eratpos_r TO eratpos_c) <= tlb_tag4_way_or(waypos_rc to waypos_rc+1) + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_q(eratpos_r to eratpos_c); +tlb_erat_rel_d(eratpos_relsoon) <= ierat_req_taken or ptereload_req_taken or tlb_tag0_type(1); +tlb_erat_rel_d(eratpos_wlc TO eratpos_wlc+1) <= tlb_tag4_way_or(waypos_wlc to waypos_wlc+1) + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_q(eratpos_wlc to eratpos_wlc+1); +tlb_erat_rel_d(eratpos_resvattr) <= tlb_tag4_way_or(waypos_resvattr) + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_q(eratpos_resvattr); +tlb_erat_rel_d(eratpos_vf) <= tlb_tag4_way_or(waypos_vf) + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_q(eratpos_vf); +tlb_erat_rel_d(eratpos_ubits TO eratpos_ubits+3) <= tlb_tag4_way_or(waypos_ubits to waypos_ubits+3) + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_q(eratpos_ubits to eratpos_ubits+3); +tlb_erat_rel_d(eratpos_wimge TO eratpos_wimge+4) <= tlb_tag4_way_or(waypos_wimge to waypos_wimge+4) + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_q(eratpos_wimge to eratpos_wimge+4); +tlb_erat_rel_d(eratpos_usxwr TO eratpos_usxwr+5) <= tlb_tag4_way_or(waypos_usxwr to waypos_usxwr+5) + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_q(eratpos_usxwr to eratpos_usxwr+5); +tlb_erat_rel_d(eratpos_gs) <= tlb_tag4_way_or(waypos_gs) + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_q(eratpos_gs); +tlb_erat_rel_d(eratpos_ts) <= tlb_tag4_way_or(waypos_ts) + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_q(eratpos_ts); +tlb_erat_rel_d(eratpos_tid TO eratpos_tid+pid_width_erat-1) <= tlb_tag4_way_or(waypos_tid+6 to waypos_tid+14-1) + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_q(eratpos_tid to eratpos_tid+pid_width_erat-1); +tlb_erat_rel_clone_d(eratpos_extclass TO eratpos_extclass+1) <= tlb_tag4_way_or(waypos_extclass to waypos_extclass+1) + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_clone_q(eratpos_extclass to eratpos_extclass+1); +tlb_erat_rel_clone_d(eratpos_wren) <= '1' when (tlb_tag4_erat_data_cap='1' and + (tlb_tag4_q(tagpos_type_ierat)='1' or tlb_tag4_q(tagpos_type_derat)='1') and + tlb_tag4_q(tagpos_type_ptereload)='0' and tlb_tag4_wayhit_q(tlb_ways)='1' and + tlb_tag4_q(tagpos_wq+1)='0' and tlb_tag4_q(tagpos_ind)='0' and multihit='0') + else '0' when tlb_tag4_erat_data_cap='1' + else tlb_erat_rel_clone_q(eratpos_wren); +tlb_erat_rel_clone_d(eratpos_rpnrsvd TO eratpos_rpnrsvd+3) <= (others => '0'); +tlb_erat_rel_clone_d(eratpos_rpn TO eratpos_rpn+rpn_width-1) <= tlb_tag4_way_or(waypos_rpn to waypos_rpn+rpn_width-1) + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_clone_q(eratpos_rpn to eratpos_rpn+rpn_width-1); +tlb_erat_rel_clone_d(eratpos_r TO eratpos_c) <= tlb_tag4_way_or(waypos_rc to waypos_rc+1) + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_clone_q(eratpos_r to eratpos_c); +tlb_erat_rel_clone_d(eratpos_relsoon) <= derat_req_taken or ptereload_req_taken or tlb_tag0_type(0); +tlb_erat_rel_clone_d(eratpos_wlc TO eratpos_wlc+1) <= tlb_tag4_way_or(waypos_wlc to waypos_wlc+1) + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_clone_q(eratpos_wlc to eratpos_wlc+1); +tlb_erat_rel_clone_d(eratpos_resvattr) <= tlb_tag4_way_or(waypos_resvattr) + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_clone_q(eratpos_resvattr); +tlb_erat_rel_clone_d(eratpos_vf) <= tlb_tag4_way_or(waypos_vf) + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_clone_q(eratpos_vf); +tlb_erat_rel_clone_d(eratpos_ubits TO eratpos_ubits+3) <= tlb_tag4_way_or(waypos_ubits to waypos_ubits+3) + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_clone_q(eratpos_ubits to eratpos_ubits+3); +tlb_erat_rel_clone_d(eratpos_wimge TO eratpos_wimge+4) <= tlb_tag4_way_or(waypos_wimge to waypos_wimge+4) + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_clone_q(eratpos_wimge to eratpos_wimge+4); +tlb_erat_rel_clone_d(eratpos_usxwr TO eratpos_usxwr+5) <= tlb_tag4_way_or(waypos_usxwr to waypos_usxwr+5) + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_clone_q(eratpos_usxwr to eratpos_usxwr+5); +tlb_erat_rel_clone_d(eratpos_gs) <= tlb_tag4_way_or(waypos_gs) + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_clone_q(eratpos_gs); +tlb_erat_rel_clone_d(eratpos_ts) <= tlb_tag4_way_or(waypos_ts) + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_clone_q(eratpos_ts); +tlb_erat_rel_clone_d(eratpos_tid TO eratpos_tid+pid_width_erat-1) <= tlb_tag4_way_or(waypos_tid+6 to waypos_tid+14-1) + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_clone_q(eratpos_tid to eratpos_tid+pid_width_erat-1); +tlb_tag4_erat_data_cap <= '1' when ((tlb_tag4_q(tagpos_type_ierat)='1' or tlb_tag4_q(tagpos_type_derat)='1') and + tlb_tag4_q(tagpos_type_ptereload)='0' and tlb_tag4_q(tagpos_ind)='0' and + (tlb_tag4_wayhit_q(tlb_ways)='1' or or_reduce(tag4_parerr_q(0 to 4))='1') and + (tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not tlb_ctl_tag4_flush)/="0000" ) + else '1' when ((tlb_tag4_q(tagpos_type_ierat)='1' or tlb_tag4_q(tagpos_type_derat)='1') and + tlb_tag4_q(tagpos_type_ptereload)='1' and tlb_tag4_q(tagpos_ind)='0' and + tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000" ) + else '0'; +erat_pgsize(0 TO 2) <= ERAT_PgSize_1GB when tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_1GB + else ERAT_PgSize_16MB when tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_16MB + else ERAT_PgSize_1MB when tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_1MB + else ERAT_PgSize_64KB when tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_64KB + else ERAT_PgSize_4KB; +tlb_erat_val_d(0 TO 3) <= (tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) or ierat_tag4_dup_thdid(0 to thdid_width-1)) + when (tlb_tag4_q(tagpos_type_ierat)='1' and tlb_tag4_q(tagpos_type_ptereload)='0' and + tlb_tag4_q(tagpos_ind)='0' and tlb_tag4_wayhit_q(tlb_ways)='1' and + or_reduce(tag4_parerr_q(0 to 4))='0' and + (tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not tlb_ctl_tag4_flush)/="0000") + else tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) + when (tlb_tag4_q(tagpos_type_ierat)='1' and tlb_tag4_q(tagpos_type_ptereload)='0' and + ((tlb_tag4_q(tagpos_endflag)='1' and tlb_tag4_wayhit_q(tlb_ways)='0') or or_reduce(tag4_parerr_q(0 to 4))='1') and + (tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not tlb_ctl_tag4_flush)/="0000") + else tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) + when (tlb_tag4_q(tagpos_type_ierat)='1' and tlb_tag4_q(tagpos_type_ptereload)='1') + else (others => '0'); +tlb_erat_val_d(4) <= tlb_tag4_q(tagpos_type_ierat) + when (tlb_tag4_q(tagpos_type_ptereload)='0' and tlb_tag4_q(tagpos_ind)='0' and + tlb_tag4_wayhit_q(tlb_ways)='1' and multihit='0' and + (tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not tlb_ctl_tag4_flush)/="0000") + else tlb_tag4_q(tagpos_type_ierat) + when (tlb_tag4_q(tagpos_type_ptereload)='1' and tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000") + else '0'; +tlb_erat_val_d(5 TO 8) <= (tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) or derat_tag4_dup_thdid(0 to thdid_width-1)) + when (tlb_tag4_q(tagpos_type_derat)='1' and tlb_tag4_q(tagpos_type_ptereload)='0' and + tlb_tag4_q(tagpos_ind)='0' and tlb_tag4_wayhit_q(tlb_ways)='1' and + or_reduce(tag4_parerr_q(0 to 4))='0' and + (tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not tlb_ctl_tag4_flush)/="0000") + else tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) + when (tlb_tag4_q(tagpos_type_derat)='1' and tlb_tag4_q(tagpos_type_ptereload)='0' and + ((tlb_tag4_q(tagpos_endflag)='1' and tlb_tag4_wayhit_q(tlb_ways)='0') or or_reduce(tag4_parerr_q(0 to 4))='1') and + (tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not tlb_ctl_tag4_flush)/="0000") + else tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) + when (tlb_tag4_q(tagpos_type_derat)='1' and tlb_tag4_q(tagpos_type_ptereload)='1') + else (others => '0'); +tlb_erat_val_d(9) <= tlb_tag4_q(tagpos_type_derat) + when (tlb_tag4_q(tagpos_type_ptereload)='0' and tlb_tag4_q(tagpos_ind)='0' and + tlb_tag4_wayhit_q(tlb_ways)='1' and multihit='0' and + (tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not tlb_ctl_tag4_flush)/="0000") + else tlb_tag4_q(tagpos_type_derat) + when (tlb_tag4_q(tagpos_type_ptereload)='1' and tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000") + else '0'; +ierat_req0_tag4_thdid_match <= '1' when or_reduce(tlb_tag4_way_or(waypos_thdid to waypos_thdid+thdid_width-1) and ierat_req0_thdid)='1' else '0'; +ierat_req0_tag4_pid_match <= '1' when (tlb_tag4_way_or(waypos_tid to waypos_tid+pid_width-1)=ierat_req0_pid or or_reduce(tlb_tag4_way_or(waypos_tid to waypos_tid+pid_width-1))='0') + else '0'; +ierat_req0_tag4_as_match <= '1' when (tlb_tag4_way_or(waypos_ts)=ierat_req0_as) else '0'; +ierat_req0_tag4_gs_match <= '1' when (tlb_tag4_way_or(waypos_gs)=ierat_req0_gs) else '0'; +ierat_req0_tag4_epn_match <= '1' when (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-1)=ierat_req0_epn(52-epn_width to 51) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_4KB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-5)=ierat_req0_epn(52-epn_width to 47) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_64KB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-9)=ierat_req0_epn(52-epn_width to 43) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_1MB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-13)=ierat_req0_epn(52-epn_width to 39) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_16MB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-19)=ierat_req0_epn(52-epn_width to 33) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_1GB) + else '0'; +tlb_erat_dup_d(0) <= '1' when (ierat_req0_tag4_pid_match='1' and + ierat_req0_tag4_as_match='1' and ierat_req0_tag4_gs_match='1' and + ierat_req0_tag4_epn_match='1' and ierat_req0_tag4_thdid_match='1' and + ierat_req0_valid='1' and (ierat_req0_nonspec='1' or (tlb_erat_dup_d(4)='0' and tlb_erat_dup_d(5)='1'))) else '0'; +ierat_req1_tag4_thdid_match <= '1' when or_reduce(tlb_tag4_way_or(waypos_thdid to waypos_thdid+thdid_width-1) and ierat_req1_thdid)='1' else '0'; +ierat_req1_tag4_pid_match <= '1' when (tlb_tag4_way_or(waypos_tid to waypos_tid+pid_width-1)=ierat_req1_pid or or_reduce(tlb_tag4_way_or(waypos_tid to waypos_tid+pid_width-1))='0') + else '0'; +ierat_req1_tag4_as_match <= '1' when (tlb_tag4_way_or(waypos_ts)=ierat_req1_as) else '0'; +ierat_req1_tag4_gs_match <= '1' when (tlb_tag4_way_or(waypos_gs)=ierat_req1_gs) else '0'; +ierat_req1_tag4_epn_match <= '1' when (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-1)=ierat_req1_epn(52-epn_width to 51) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_4KB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-5)=ierat_req1_epn(52-epn_width to 47) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_64KB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-9)=ierat_req1_epn(52-epn_width to 43) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_1MB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-13)=ierat_req1_epn(52-epn_width to 39) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_16MB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-19)=ierat_req1_epn(52-epn_width to 33) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_1GB) + else '0'; +tlb_erat_dup_d(1) <= '1' when (ierat_req1_tag4_pid_match='1' and + ierat_req1_tag4_as_match='1' and ierat_req1_tag4_gs_match='1' and + ierat_req1_tag4_epn_match='1' and ierat_req1_tag4_thdid_match='1' and + ierat_req1_valid='1' and (ierat_req1_nonspec='1' or (tlb_erat_dup_d(4)='0' and tlb_erat_dup_d(5)='1'))) else '0'; +ierat_req2_tag4_thdid_match <= '1' when or_reduce(tlb_tag4_way_or(waypos_thdid to waypos_thdid+thdid_width-1) and ierat_req2_thdid)='1' else '0'; +ierat_req2_tag4_pid_match <= '1' when (tlb_tag4_way_or(waypos_tid to waypos_tid+pid_width-1)=ierat_req2_pid or or_reduce(tlb_tag4_way_or(waypos_tid to waypos_tid+pid_width-1))='0') + else '0'; +ierat_req2_tag4_as_match <= '1' when (tlb_tag4_way_or(waypos_ts)=ierat_req2_as) else '0'; +ierat_req2_tag4_gs_match <= '1' when (tlb_tag4_way_or(waypos_gs)=ierat_req2_gs) else '0'; +ierat_req2_tag4_epn_match <= '1' when (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-1)=ierat_req2_epn(52-epn_width to 51) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_4KB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-5)=ierat_req2_epn(52-epn_width to 47) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_64KB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-9)=ierat_req2_epn(52-epn_width to 43) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_1MB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-13)=ierat_req2_epn(52-epn_width to 39) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_16MB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-19)=ierat_req2_epn(52-epn_width to 33) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_1GB) + else '0'; +tlb_erat_dup_d(2) <= '1' when (ierat_req2_tag4_pid_match='1' and + ierat_req2_tag4_as_match='1' and ierat_req2_tag4_gs_match='1' and + ierat_req2_tag4_epn_match='1' and ierat_req2_tag4_thdid_match='1' and + ierat_req2_valid='1' and (ierat_req2_nonspec='1' or (tlb_erat_dup_d(4)='0' and tlb_erat_dup_d(5)='1'))) else '0'; +ierat_req3_tag4_thdid_match <= '1' when or_reduce(tlb_tag4_way_or(waypos_thdid to waypos_thdid+thdid_width-1) and ierat_req3_thdid)='1' else '0'; +ierat_req3_tag4_pid_match <= '1' when (tlb_tag4_way_or(waypos_tid to waypos_tid+pid_width-1)=ierat_req3_pid or or_reduce(tlb_tag4_way_or(waypos_tid to waypos_tid+pid_width-1))='0') + else '0'; +ierat_req3_tag4_as_match <= '1' when (tlb_tag4_way_or(waypos_ts)=ierat_req3_as) else '0'; +ierat_req3_tag4_gs_match <= '1' when (tlb_tag4_way_or(waypos_gs)=ierat_req3_gs) else '0'; +ierat_req3_tag4_epn_match <= '1' when (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-1)=ierat_req3_epn(52-epn_width to 51) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_4KB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-5)=ierat_req3_epn(52-epn_width to 47) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_64KB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-9)=ierat_req3_epn(52-epn_width to 43) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_1MB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-13)=ierat_req3_epn(52-epn_width to 39) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_16MB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-19)=ierat_req3_epn(52-epn_width to 33) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_1GB) + else '0'; +tlb_erat_dup_d(3) <= '1' when (ierat_req3_tag4_pid_match='1' and + ierat_req3_tag4_as_match='1' and ierat_req3_tag4_gs_match='1' and + ierat_req3_tag4_epn_match='1' and ierat_req3_tag4_thdid_match='1' and + ierat_req3_valid='1' and (ierat_req3_nonspec='1' or (tlb_erat_dup_d(4)='0' and tlb_erat_dup_d(5)='1'))) else '0'; +ierat_iu4_tag4_thdid_match <= '1' when or_reduce(tlb_tag4_way_or(waypos_thdid to waypos_thdid+thdid_width-1) and ierat_iu4_thdid)='1' else '0'; +ierat_iu4_tag4_lpid_match <= '1' when (tlb_tag4_way_or(waypos_lpid to waypos_lpid+lpid_width-1)=lpidr or or_reduce(tlb_tag4_way_or(waypos_lpid to waypos_lpid+lpid_width-1))='0') else '0'; +ierat_iu4_tag4_pid_match <= '1' when (tlb_tag4_way_or(waypos_tid to waypos_tid+pid_width-1)=ierat_iu4_pid or or_reduce(tlb_tag4_way_or(waypos_tid to waypos_tid+pid_width-1))='0') else '0'; +ierat_iu4_tag4_as_match <= '1' when (tlb_tag4_way_or(waypos_ts)=ierat_iu4_as) else '0'; +ierat_iu4_tag4_gs_match <= '1' when (tlb_tag4_way_or(waypos_gs)=ierat_iu4_gs) else '0'; +ierat_iu4_tag4_epn_match <= '1' when (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-1)=ierat_iu4_epn(52-epn_width to 51) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_4KB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-5)=ierat_iu4_epn(52-epn_width to 47) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_64KB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-9)=ierat_iu4_epn(52-epn_width to 43) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_1MB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-13)=ierat_iu4_epn(52-epn_width to 39) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_16MB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-19)=ierat_iu4_epn(52-epn_width to 33) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_1GB) + else '0'; +derat_req0_tag4_thdid_match <= '1' when or_reduce(tlb_tag4_way_or(waypos_thdid to waypos_thdid+thdid_width-1) and derat_req0_thdid)='1' else '0'; +derat_req0_tag4_lpid_match <= '1' when (tlb_tag4_way_or(waypos_lpid to waypos_lpid+lpid_width-1)=derat_req0_lpid or or_reduce(tlb_tag4_way_or(waypos_lpid to waypos_lpid+lpid_width-1))='0') + else '0'; +derat_req0_tag4_pid_match <= '1' when (tlb_tag4_way_or(waypos_tid to waypos_tid+pid_width-1)=derat_req0_pid or or_reduce(tlb_tag4_way_or(waypos_tid to waypos_tid+pid_width-1))='0') + else '0'; +derat_req0_tag4_as_match <= '1' when (tlb_tag4_way_or(waypos_ts)=derat_req0_as) else '0'; +derat_req0_tag4_gs_match <= '1' when (tlb_tag4_way_or(waypos_gs)=derat_req0_gs) else '0'; +derat_req0_tag4_epn_match <= '1' when (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-1)=derat_req0_epn(52-epn_width to 51) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_4KB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-5)=derat_req0_epn(52-epn_width to 47) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_64KB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-9)=derat_req0_epn(52-epn_width to 43) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_1MB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-13)=derat_req0_epn(52-epn_width to 39) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_16MB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-19)=derat_req0_epn(52-epn_width to 33) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_1GB) + else '0'; +tlb_erat_dup_d(10) <= '1' when (derat_req0_tag4_lpid_match='1' and derat_req0_tag4_pid_match='1' and + derat_req0_tag4_as_match='1' and derat_req0_tag4_gs_match='1' and + derat_req0_tag4_epn_match='1' and derat_req0_tag4_thdid_match='1' and + derat_req0_valid='1') else '0'; +derat_req1_tag4_thdid_match <= '1' when or_reduce(tlb_tag4_way_or(waypos_thdid to waypos_thdid+thdid_width-1) and derat_req1_thdid)='1' else '0'; +derat_req1_tag4_lpid_match <= '1' when (tlb_tag4_way_or(waypos_lpid to waypos_lpid+lpid_width-1)=derat_req1_lpid or or_reduce(tlb_tag4_way_or(waypos_lpid to waypos_lpid+lpid_width-1))='0') + else '0'; +derat_req1_tag4_pid_match <= '1' when (tlb_tag4_way_or(waypos_tid to waypos_tid+pid_width-1)=derat_req1_pid or or_reduce(tlb_tag4_way_or(waypos_tid to waypos_tid+pid_width-1))='0') + else '0'; +derat_req1_tag4_as_match <= '1' when (tlb_tag4_way_or(waypos_ts)=derat_req1_as) else '0'; +derat_req1_tag4_gs_match <= '1' when (tlb_tag4_way_or(waypos_gs)=derat_req1_gs) else '0'; +derat_req1_tag4_epn_match <= '1' when (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-1)=derat_req1_epn(52-epn_width to 51) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_4KB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-5)=derat_req1_epn(52-epn_width to 47) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_64KB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-9)=derat_req1_epn(52-epn_width to 43) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_1MB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-13)=derat_req1_epn(52-epn_width to 39) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_16MB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-19)=derat_req1_epn(52-epn_width to 33) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_1GB) + else '0'; +tlb_erat_dup_d(11) <= '1' when (derat_req1_tag4_lpid_match='1' and derat_req1_tag4_pid_match='1' and + derat_req1_tag4_as_match='1' and derat_req1_tag4_gs_match='1' and + derat_req1_tag4_epn_match='1' and derat_req1_tag4_thdid_match='1' and + derat_req1_valid='1') else '0'; +derat_req2_tag4_thdid_match <= '1' when or_reduce(tlb_tag4_way_or(waypos_thdid to waypos_thdid+thdid_width-1) and derat_req2_thdid)='1' else '0'; +derat_req2_tag4_lpid_match <= '1' when (tlb_tag4_way_or(waypos_lpid to waypos_lpid+lpid_width-1)=derat_req2_lpid or or_reduce(tlb_tag4_way_or(waypos_lpid to waypos_lpid+lpid_width-1))='0') + else '0'; +derat_req2_tag4_pid_match <= '1' when (tlb_tag4_way_or(waypos_tid to waypos_tid+pid_width-1)=derat_req2_pid or or_reduce(tlb_tag4_way_or(waypos_tid to waypos_tid+pid_width-1))='0') + else '0'; +derat_req2_tag4_as_match <= '1' when (tlb_tag4_way_or(waypos_ts)=derat_req2_as) else '0'; +derat_req2_tag4_gs_match <= '1' when (tlb_tag4_way_or(waypos_gs)=derat_req2_gs) else '0'; +derat_req2_tag4_epn_match <= '1' when (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-1)=derat_req2_epn(52-epn_width to 51) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_4KB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-5)=derat_req2_epn(52-epn_width to 47) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_64KB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-9)=derat_req2_epn(52-epn_width to 43) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_1MB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-13)=derat_req2_epn(52-epn_width to 39) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_16MB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-19)=derat_req2_epn(52-epn_width to 33) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_1GB) + else '0'; +tlb_erat_dup_d(12) <= '1' when (derat_req2_tag4_lpid_match='1' and derat_req2_tag4_pid_match='1' and + derat_req2_tag4_as_match='1' and derat_req2_tag4_gs_match='1' and + derat_req2_tag4_epn_match='1' and derat_req2_tag4_thdid_match='1' and + derat_req2_valid='1') else '0'; +derat_req3_tag4_thdid_match <= '1' when or_reduce(tlb_tag4_way_or(waypos_thdid to waypos_thdid+thdid_width-1) and derat_req3_thdid)='1' else '0'; +derat_req3_tag4_lpid_match <= '1' when (tlb_tag4_way_or(waypos_lpid to waypos_lpid+lpid_width-1)=derat_req3_lpid or or_reduce(tlb_tag4_way_or(waypos_lpid to waypos_lpid+lpid_width-1))='0') + else '0'; +derat_req3_tag4_pid_match <= '1' when (tlb_tag4_way_or(waypos_tid to waypos_tid+pid_width-1)=derat_req3_pid or or_reduce(tlb_tag4_way_or(waypos_tid to waypos_tid+pid_width-1))='0') + else '0'; +derat_req3_tag4_as_match <= '1' when (tlb_tag4_way_or(waypos_ts)=derat_req3_as) else '0'; +derat_req3_tag4_gs_match <= '1' when (tlb_tag4_way_or(waypos_gs)=derat_req3_gs) else '0'; +derat_req3_tag4_epn_match <= '1' when (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-1)=derat_req3_epn(52-epn_width to 51) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_4KB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-5)=derat_req3_epn(52-epn_width to 47) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_64KB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-9)=derat_req3_epn(52-epn_width to 43) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_1MB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-13)=derat_req3_epn(52-epn_width to 39) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_16MB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-19)=derat_req3_epn(52-epn_width to 33) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_1GB) + else '0'; +tlb_erat_dup_d(13) <= '1' when (derat_req3_tag4_lpid_match='1' and derat_req3_tag4_pid_match='1' and + derat_req3_tag4_as_match='1' and derat_req3_tag4_gs_match='1' and + derat_req3_tag4_epn_match='1' and derat_req3_tag4_thdid_match='1' and + derat_req3_valid='1') else '0'; +derat_ex5_tag4_thdid_match <= '1' when or_reduce(tlb_tag4_way_or(waypos_thdid to waypos_thdid+thdid_width-1) and derat_ex5_thdid)='1' else '0'; +derat_ex5_tag4_lpid_match <= '1' when (tlb_tag4_way_or(waypos_lpid to waypos_lpid+lpid_width-1)=derat_ex5_lpid or or_reduce(tlb_tag4_way_or(waypos_lpid to waypos_lpid+lpid_width-1))='0') else '0'; +derat_ex5_tag4_pid_match <= '1' when (tlb_tag4_way_or(waypos_tid to waypos_tid+pid_width-1)=derat_ex5_pid or or_reduce(tlb_tag4_way_or(waypos_tid to waypos_tid+pid_width-1))='0') else '0'; +derat_ex5_tag4_as_match <= '1' when (tlb_tag4_way_or(waypos_ts)=derat_ex5_as) else '0'; +derat_ex5_tag4_gs_match <= '1' when (tlb_tag4_way_or(waypos_gs)=derat_ex5_gs) else '0'; +derat_ex5_tag4_epn_match <= '1' when (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-1)=derat_ex5_epn(52-epn_width to 51) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_4KB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-5)=derat_ex5_epn(52-epn_width to 47) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_64KB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-9)=derat_ex5_epn(52-epn_width to 43) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_1MB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-13)=derat_ex5_epn(52-epn_width to 39) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_16MB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-19)=derat_ex5_epn(52-epn_width to 33) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_1GB) + else '0'; +tlb_erat_dup_d(4) <= tlb_tag4_q(tagpos_type_ierat) + when (tlb_tag4_q(tagpos_type_ptereload)='0' and tlb_tag4_way_or(waypos_ind)='0' and + tlb_tag4_wayhit_q(tlb_ways)='1' and multihit='0' and + tlb_tag4_q(tagpos_wq+1)='0' and or_reduce(tag4_parerr_q(0 to 4))='0') + else '0'; +tlb_erat_dup_d(5) <= '1' when (tlb_erat_dup_d(4)='1' or tlb_erat_dup_q(4)='1') + else '1' when tlb_erat_dup_q(7 to 9)/="000" + else '0'; +tlb_erat_dup_d(6) <= tlb_tag4_q(tagpos_type_ierat) when + (ierat_iu4_tag4_lpid_match='1' and ierat_iu4_tag4_pid_match='1' and + ierat_iu4_tag4_as_match='1' and ierat_iu4_tag4_gs_match='1' and + ierat_iu4_tag4_epn_match='1' and ierat_iu4_tag4_thdid_match='1' and + ierat_iu4_valid='1' and tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000") else '0'; +tlb_erat_dup_d(7 TO 9) <= "001" when (tlb_erat_dup_q(4)='1' and tlb_erat_dup_q(7 to 9)="000") + else "010" when tlb_erat_dup_q(7 to 9)="001" + else "011" when tlb_erat_dup_q(7 to 9)="010" + else "100" when tlb_erat_dup_q(7 to 9)="011" + else "101" when tlb_erat_dup_q(7 to 9)="100" + else "110" when tlb_erat_dup_q(7 to 9)="101" + else "111" when tlb_erat_dup_q(7 to 9)="110" + else "000" when tlb_erat_dup_q(7 to 9)="111" + else tlb_erat_dup_q(7 to 9); +tlb_erat_dup_d(14) <= tlb_tag4_q(tagpos_type_derat) + when (tlb_tag4_q(tagpos_type_ptereload)='0' and tlb_tag4_way_or(waypos_ind)='0' and + tlb_tag4_wayhit_q(tlb_ways)='1' and multihit='0' and + tlb_tag4_q(tagpos_wq+1)='0' and or_reduce(tag4_parerr_q(0 to 4))='0') + else '0'; +tlb_erat_dup_d(15) <= '1' when (tlb_erat_dup_d(14)='1' or tlb_erat_dup_q(14)='1') + else '1' when tlb_erat_dup_q(17 to 19)/="000" + else '0'; +tlb_erat_dup_d(16) <= tlb_tag4_q(tagpos_type_derat) when + (derat_ex5_tag4_lpid_match='1' and derat_ex5_tag4_pid_match='1' and + derat_ex5_tag4_as_match='1' and derat_ex5_tag4_gs_match='1' and + derat_ex5_tag4_epn_match='1' and derat_ex5_tag4_thdid_match='1' and + derat_ex5_valid='1' and tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000") else '0'; +tlb_erat_dup_d(17 TO 19) <= "001" when (tlb_erat_dup_q(14)='1' and tlb_erat_dup_q(17 to 19)="000") + else "010" when tlb_erat_dup_q(17 to 19)="001" + else "011" when tlb_erat_dup_q(17 to 19)="010" + else "100" when tlb_erat_dup_q(17 to 19)="011" + else "101" when tlb_erat_dup_q(17 to 19)="100" + else "110" when tlb_erat_dup_q(17 to 19)="101" + else "111" when tlb_erat_dup_q(17 to 19)="110" + else "000" when tlb_erat_dup_q(17 to 19)="111" + else tlb_erat_dup_q(17 to 19); +ierat_tag4_dup_thdid <= ((0 to 3 => tlb_erat_dup_d(0)) and ierat_req0_thdid(0 to 3) and (0 to 3 => ierat_req0_nonspec) and (0 to 3 => not tlb_tag4_q(tagpos_wq+1))) or + ((0 to 3 => tlb_erat_dup_d(1)) and ierat_req1_thdid(0 to 3) and (0 to 3 => ierat_req1_nonspec) and (0 to 3 => not tlb_tag4_q(tagpos_wq+1))) or + ((0 to 3 => tlb_erat_dup_d(2)) and ierat_req2_thdid(0 to 3) and (0 to 3 => ierat_req2_nonspec) and (0 to 3 => not tlb_tag4_q(tagpos_wq+1))) or + ((0 to 3 => tlb_erat_dup_d(3)) and ierat_req3_thdid(0 to 3) and (0 to 3 => ierat_req3_nonspec) and (0 to 3 => not tlb_tag4_q(tagpos_wq+1))); +derat_tag4_dup_thdid <= ((0 to 3 => tlb_erat_dup_d(10)) and derat_req0_thdid(0 to 3) and (0 to 3 => not tlb_tag4_q(tagpos_wq+1))) or + ((0 to 3 => tlb_erat_dup_d(11)) and derat_req1_thdid(0 to 3) and (0 to 3 => not tlb_tag4_q(tagpos_wq+1))) or + ((0 to 3 => tlb_erat_dup_d(12)) and derat_req2_thdid(0 to 3) and (0 to 3 => not tlb_tag4_q(tagpos_wq+1))) or + ((0 to 3 => tlb_erat_dup_d(13)) and derat_req3_thdid(0 to 3) and (0 to 3 => not tlb_tag4_q(tagpos_wq+1))); +tlb_tag4_epcr_dgtmi <= or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and xu_mm_epcr_dgtmi); +tlb_tag4_size_not_supp <= '0' when (tlb_tag4_q(tagpos_size to tagpos_size+3)=TLB_PgSize_4KB or tlb_tag4_q(tagpos_size to tagpos_size+3)=TLB_PgSize_64KB or + tlb_tag4_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1MB or tlb_tag4_q(tagpos_size to tagpos_size+3)=TLB_PgSize_16MB or + tlb_tag4_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1GB or + (tlb_tag4_q(tagpos_size to tagpos_size+3)=TLB_PgSize_256MB and tlb_tag4_q(tagpos_ind)='1')) else '1'; +eratmiss_done_d <= tlb_erat_val_q(0 to 3) or tlb_erat_val_q(5 to 8); +tlb_miss_d <= tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) + when ((tlb_tag4_q(tagpos_type_ierat)='1' or tlb_tag4_q(tagpos_type_derat)='1') and tlb_tag4_q(tagpos_type_ptereload)='0' and + tlb_tag4_q(tagpos_endflag)='1' and tlb_tag4_wayhit_q(0 to 3) = "0000" + and or_reduce(tag4_parerr_q(0 to 4))='0') + else (others => '0'); +tlb_inelig_d <= tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) + when (tlb_tag4_q(tagpos_type_ptereload)='1' and tlb_tag4_q(tagpos_is)='1' and lru_tag4_dataout_q(0 to 3)="1111" and lru_tag4_dataout_q(8 to 11)="1111") + or (tlb_tag4_q(tagpos_type_ptereload)='1' and tlb_tag4_q(tagpos_is)='1' and tlb_tag4_size_not_supp='1') + or (tlb_tag4_q(tagpos_type_ptereload)='1' and tlb_tag4_q(tagpos_is)='1' and tlb_tag4_q(tagpos_pt)='0') + else (others => '0'); +lrat_miss_d <= (tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag4_flush)) + when ( ((or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and tlb_resv_match_vec)='1' + and tlb_tag4_q(tagpos_wq to tagpos_wq+1)="01" and mmucfg_twc='1') + or tlb_tag4_q(tagpos_wq to tagpos_wq+1)="00" or tlb_tag4_q(tagpos_wq to tagpos_wq+1)="11") and + tlb_tag4_q(tagpos_type_tlbwe)='1' and tlb_tag4_q(tagpos_gs)='1' and tlb_tag4_q(tagpos_pr)='0' and + tlb_tag4_epcr_dgtmi='0' and mmucfg_lrat='1' and + tlb_tag4_q(tagpos_is)='1' and lrat_tag4_hit_status(0 to 3)/="1100" ) + else tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) + when (tlb_tag4_q(tagpos_type_ptereload)='1' and tlb_tag4_q(tagpos_gs)='1' and mmucfg_lrat='1' and + tlb_tag4_q(tagpos_is)='1' and lrat_tag4_hit_status(0 to 3)/="1100" and + tlb_tag4_q(tagpos_wq to tagpos_wq+1)="10" and + tlb_tag4_q(tagpos_pt)='1') + else (others => '0'); +pt_fault_d <= tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) + when ( tlb_tag4_q(tagpos_type_ptereload)='1' and tlb_tag4_q(tagpos_is)='0' and + tlb_tag4_q(tagpos_wq to tagpos_wq+1)="10" and + tlb_tag4_q(tagpos_pt)='1' ) + else (others => '0'); +hv_priv_d <= (tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag4_flush)) + when ( tlb_tag4_q(tagpos_type_tlbwe)='1' and tlb_tag4_q(tagpos_gs)='1' and tlb_tag4_q(tagpos_pr)='0' and tlb0cfg_gtwe='0' ) or + ( tlb_tag4_q(tagpos_type_tlbwe)='1' and tlb_tag4_q(tagpos_gs)='1' and tlb_tag4_q(tagpos_pr)='0' and mmucfg_lrat='0' ) or + + ( tlb_tag4_q(tagpos_type_tlbwe)='1' and tlb_tag4_q(tagpos_gs)='1' and tlb_tag4_q(tagpos_pr)='0' and tlb_tag4_q(tagpos_hes)='1' + and (tlb_tag4_q(tagpos_wq to tagpos_wq+1)="00" or tlb_tag4_q(tagpos_wq to tagpos_wq+1)="11" or + (tlb_tag4_q(tagpos_wq to tagpos_wq+1)="01" and (or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and tlb_resv_match_vec)='1'))) and + ((lru_tag4_dataout_q(0)='1' and lru_tag4_dataout_q(4 to 5)="00" and lru_tag4_dataout_q(8)='1') or + (lru_tag4_dataout_q(1)='1' and lru_tag4_dataout_q(4 to 5)="01" and lru_tag4_dataout_q(9)='1') or + (lru_tag4_dataout_q(2)='1' and lru_tag4_dataout_q(4)='1' and lru_tag4_dataout_q(6)='0' and lru_tag4_dataout_q(10)='1') or + (lru_tag4_dataout_q(3)='1' and lru_tag4_dataout_q(4)='1' and lru_tag4_dataout_q(6)='1' and lru_tag4_dataout_q(11)='1')) ) or + ( tlb_tag4_q(tagpos_type_tlbwe)='1' and tlb_tag4_q(tagpos_gs)='1' and tlb_tag4_q(tagpos_pr)='0' and tlb_tag4_q(tagpos_hes)='1' + and (tlb_tag4_q(tagpos_wq to tagpos_wq+1)="00" or tlb_tag4_q(tagpos_wq to tagpos_wq+1)="11" or + (tlb_tag4_q(tagpos_wq to tagpos_wq+1)="01" and (or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and tlb_resv_match_vec)='1'))) and + tlb_tag4_q(tagpos_is+1)='1' ) or + + ( tlb_tag4_q(tagpos_type_tlbwe)='1' and tlb_tag4_q(tagpos_gs)='1' and tlb_tag4_q(tagpos_pr)='0' and tlb_tag4_q(tagpos_hes)='0' and tlb_tag4_q(tagpos_wq to tagpos_wq+1)/="10") + + else (others => '0'); +esr_pt_d <= (pt_fault_d or lrat_miss_d) and (0 to 3 => tlb_tag4_q(tagpos_type_ptereload)); +esr_data_d <= (tlb_miss_d or pt_fault_d or tlb_inelig_d or lrat_miss_d) and (0 to 3 => tlb_tag4_q(tagpos_type_derat)); +esr_st_d <= (tlb_miss_d or pt_fault_d or tlb_inelig_d or lrat_miss_d) and (0 to 3 => tlb_tag4_q(tagpos_type_derat)) and (0 to 3 => tlb_tag4_q(tagpos_class+1)); +esr_epid_d <= (tlb_miss_d or pt_fault_d or tlb_inelig_d or lrat_miss_d) and (0 to 3 => tlb_tag4_q(tagpos_type_derat)) and (0 to 3 => tlb_tag4_q(tagpos_class)); +cr0_eq_d <= tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) + when ( (tlb_tag4_q(tagpos_type_tlbsrx)='1' or (tlb_tag4_q(tagpos_type_tlbsx)='1' and tlb_tag4_q(tagpos_recform)='1')) and + tlb_tag4_wayhit_q(tlb_ways)='1' and multihit='0' and or_reduce(tag4_parerr_q(0 to 4))='0' ) + else (others => '0'); +cr0_eq_valid_d <= tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) + when ( (tlb_tag4_q(tagpos_type_tlbsrx)='1' or (tlb_tag4_q(tagpos_type_tlbsx)='1' and tlb_tag4_q(tagpos_recform)='1')) and + (tlb_tag4_q(tagpos_endflag)='1' or (tlb_tag4_wayhit_q(tlb_ways)='1' and multihit='0')) and or_reduce(tag4_parerr_q(0 to 4))='0' ) + else (others => '0'); +tlb_multihit_err_d <= tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) + when ( ((tlb_tag4_q(tagpos_type_derat to tagpos_type_ierat)/="00" and tlb_tag4_q(tagpos_type_ptereload)='0') or + (tlb_tag4_q(tagpos_type_tlbsx to tagpos_type_tlbsrx)/="00")) and + multihit='1' and (tlb_tag4_q(tagpos_endflag)='1' or tlb_tag4_wayhit_q(tlb_ways)='1')) + else (others => '0'); +parerr_gen0: if check_parity = 0 generate +tlb_par_err_d <= tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) + and (0 to 3 => tag4_parerr_q(0) and not(tag4_parerr_q(0)) and or_reduce(tlb_tag4_q(tagpos_type_derat to tagpos_type_tlbre))); +lru_par_err_d <= tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) + and (0 to 3 => tag4_parerr_q(2) and not(tag4_parerr_q(2)) and or_reduce(tlb_tag4_q(tagpos_type_derat to tagpos_type_tlbre))); +tlb_tag4_tlbre_parerr <= '0'; +ECO107332_tlb_par_err_d <= tlb_par_err_d; +ECO107332_lru_par_err_d <= lru_par_err_d; +end generate parerr_gen0; +parerr_gen1: if check_parity = 1 generate +tlb_par_err_d <= tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) + and ( 0 to 3 => (or_reduce(tag4_parerr_q(0 to 3)) and or_reduce(tlb_tag4_q(tagpos_type_derat to tagpos_type_tlbsrx))) or + (tag4_parerr_q(0) and tlb_tag4_q(tagpos_type_tlbre) and not tlb_tag4_q(tagpos_esel+1) and not tlb_tag4_q(tagpos_esel+2)) or + (tag4_parerr_q(1) and tlb_tag4_q(tagpos_type_tlbre) and not tlb_tag4_q(tagpos_esel+1) and tlb_tag4_q(tagpos_esel+2)) or + (tag4_parerr_q(2) and tlb_tag4_q(tagpos_type_tlbre) and tlb_tag4_q(tagpos_esel+1) and not tlb_tag4_q(tagpos_esel+2)) or + (tag4_parerr_q(3) and tlb_tag4_q(tagpos_type_tlbre) and tlb_tag4_q(tagpos_esel+1) and tlb_tag4_q(tagpos_esel+2)) ); +lru_par_err_d <= tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) + and (0 to 3 => tag4_parerr_q(4) and (or_reduce(tlb_tag4_q(tagpos_type_derat to tagpos_type_tlbsrx)) or tlb_tag4_q(tagpos_type_tlbre))); +ECO107332_tlb_par_err_d <= tlb_par_err_d and not(tlb_ctl_tag4_flush); +ECO107332_lru_par_err_d <= lru_par_err_d and not(tlb_ctl_tag4_flush); +tlb_tag4_tlbre_parerr <= (tag4_parerr_q(0) and tlb_tag4_q(tagpos_type_tlbre) and not tlb_tag4_q(tagpos_esel+1) and not tlb_tag4_q(tagpos_esel+2)) or + (tag4_parerr_q(1) and tlb_tag4_q(tagpos_type_tlbre) and not tlb_tag4_q(tagpos_esel+1) and tlb_tag4_q(tagpos_esel+2)) or + (tag4_parerr_q(2) and tlb_tag4_q(tagpos_type_tlbre) and tlb_tag4_q(tagpos_esel+1) and not tlb_tag4_q(tagpos_esel+2)) or + (tag4_parerr_q(3) and tlb_tag4_q(tagpos_type_tlbre) and tlb_tag4_q(tagpos_esel+1) and tlb_tag4_q(tagpos_esel+2)) or + (tag4_parerr_q(4) and tlb_tag4_q(tagpos_type_tlbre)); +end generate parerr_gen1; +tlb_tag5_except_d <= (hv_priv_d or lrat_miss_d or tlb_inelig_d or pt_fault_d or + tlb_multihit_err_d or tlb_par_err_d or lru_par_err_d); +tlb_isi_d <= tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) + when (tlb_tag4_q(tagpos_type_ierat)='1' and tlb_tag4_q(tagpos_type_ptereload)='0' and + tlb_tag4_wayhit_q(0 to 3) = "0000" and tlb_tag4_q(tagpos_endflag)='1') + else (others => '0'); +tlb_dsi_d <= tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) + when (tlb_tag4_q(tagpos_type_derat)='1' and tlb_tag4_q(tagpos_type_ptereload)='0' and + tlb_tag4_wayhit_q(0 to 3) = "0000" and tlb_tag4_q(tagpos_endflag)='1') + else (others => '0'); +matchline_comb0 : mmq_tlb_matchline + generic map (have_xbit => 1, num_pgsizes => 5, have_cmpmask => 1, cmpmask_width => 5) + port map ( + vdd => vdd, + gnd => gnd, + addr_in => tlb_tag3_clone1_q(tagpos_epn to tagpos_epn+epn_width-1), + addr_enable => addr_enable, + comp_pgsize => tlb_tag3_clone1_q(tagpos_size to tagpos_size+3), + pgsize_enable => pgsize_enable, + entry_size => tlb_way0_q(waypos_size to waypos_size+3), + entry_cmpmask => tlb_way0_cmpmask_q, + entry_xbit => tlb_way0_q(waypos_xbit), + entry_xbitmask => tlb_way0_xbitmask_q, + entry_epn => tlb_way0_q(waypos_epn to waypos_epn+epn_width-1), + comp_class => tlb_tag3_clone1_q(tagpos_class to tagpos_class+1), + entry_class => tlb_way0_q(waypos_class to waypos_class+1), + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => tlb_way0_q(waypos_extclass to waypos_extclass+1), + extclass_enable => extclass_enable, + comp_state => tlb_tag3_clone1_q(tagpos_state+1 to tagpos_state+2), + entry_gs => tlb_way0_q(waypos_gs), + entry_ts => tlb_way0_q(waypos_ts), + state_enable => state_enable, + entry_thdid => tlb_way0_q(waypos_thdid to waypos_thdid+thdid_width-1), + comp_thdid => tlb_tag3_clone1_q(tagpos_thdid to tagpos_thdid+thdid_width-1), + thdid_enable => thdid_enable, + entry_pid => tlb_way0_q(waypos_tid to waypos_tid+pid_width-1), + comp_pid => tlb_tag3_clone1_q(tagpos_pid to tagpos_pid+pid_width-1), + pid_enable => pid_enable, + entry_lpid => tlb_way0_q(waypos_lpid to waypos_lpid+lpid_width-1), + comp_lpid => tlb_tag3_clone1_q(tagpos_lpid to tagpos_lpid+lpid_width-1), + lpid_enable => lpid_enable, + entry_ind => tlb_way0_q(waypos_ind), + comp_ind => comp_ind, + ind_enable => ind_enable, + entry_iprot => lru_tag3_dataout_q(8), + comp_iprot => comp_iprot, + iprot_enable => iprot_enable, + entry_v => lru_tag3_dataout_q(0), + comp_invalidate => tlb_tag3_clone1_q(tagpos_type_snoop), + + match => tlb_wayhit(0), + dbg_addr_match => tlb_way0_addr_match, + dbg_pgsize_match => tlb_way0_pgsize_match, + dbg_class_match => tlb_way0_class_match, + dbg_extclass_match => tlb_way0_extclass_match, + dbg_state_match => tlb_way0_state_match, + dbg_thdid_match => tlb_way0_thdid_match, + dbg_pid_match => tlb_way0_pid_match, + dbg_lpid_match => tlb_way0_lpid_match, + dbg_ind_match => tlb_way0_ind_match, + dbg_iprot_match => tlb_way0_iprot_match + ); +matchline_comb1 : mmq_tlb_matchline + generic map (have_xbit => 1, num_pgsizes => 5, have_cmpmask => 1, cmpmask_width => 5) + port map ( + vdd => vdd, + gnd => gnd, + addr_in => tlb_tag3_clone1_q(tagpos_epn to tagpos_epn+epn_width-1), + addr_enable => addr_enable, + comp_pgsize => tlb_tag3_clone1_q(tagpos_size to tagpos_size+3), + pgsize_enable => pgsize_enable, + entry_size => tlb_way1_q(waypos_size to waypos_size+3), + entry_cmpmask => tlb_way1_cmpmask_q, + entry_xbit => tlb_way1_q(waypos_xbit), + entry_xbitmask => tlb_way1_xbitmask_q, + entry_epn => tlb_way1_q(waypos_epn to waypos_epn+epn_width-1), + comp_class => tlb_tag3_clone1_q(tagpos_class to tagpos_class+1), + entry_class => tlb_way1_q(waypos_class to waypos_class+1), + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => tlb_way1_q(waypos_extclass to waypos_extclass+1), + extclass_enable => extclass_enable, + comp_state => tlb_tag3_clone1_q(tagpos_state+1 to tagpos_state+2), + entry_gs => tlb_way1_q(waypos_gs), + entry_ts => tlb_way1_q(waypos_ts), + state_enable => state_enable, + entry_thdid => tlb_way1_q(waypos_thdid to waypos_thdid+thdid_width-1), + comp_thdid => tlb_tag3_clone1_q(tagpos_thdid to tagpos_thdid+thdid_width-1), + thdid_enable => thdid_enable, + entry_pid => tlb_way1_q(waypos_tid to waypos_tid+pid_width-1), + comp_pid => tlb_tag3_clone1_q(tagpos_pid to tagpos_pid+pid_width-1), + pid_enable => pid_enable, + entry_lpid => tlb_way1_q(waypos_lpid to waypos_lpid+lpid_width-1), + comp_lpid => tlb_tag3_clone1_q(tagpos_lpid to tagpos_lpid+lpid_width-1), + lpid_enable => lpid_enable, + entry_ind => tlb_way1_q(waypos_ind), + comp_ind => comp_ind, + ind_enable => ind_enable, + entry_iprot => lru_tag3_dataout_q(9), + comp_iprot => comp_iprot, + iprot_enable => iprot_enable, + entry_v => lru_tag3_dataout_q(1), + comp_invalidate => tlb_tag3_clone1_q(tagpos_type_snoop), + + match => tlb_wayhit(1), + dbg_addr_match => tlb_way1_addr_match, + dbg_pgsize_match => tlb_way1_pgsize_match, + dbg_class_match => tlb_way1_class_match, + dbg_extclass_match => tlb_way1_extclass_match, + dbg_state_match => tlb_way1_state_match, + dbg_thdid_match => tlb_way1_thdid_match, + dbg_pid_match => tlb_way1_pid_match, + dbg_lpid_match => tlb_way1_lpid_match, + dbg_ind_match => tlb_way1_ind_match, + dbg_iprot_match => tlb_way1_iprot_match + ); +matchline_comb2 : mmq_tlb_matchline + generic map (have_xbit => 1, num_pgsizes => 5, have_cmpmask => 1, cmpmask_width => 5) + port map ( + vdd => vdd, + gnd => gnd, + addr_in => tlb_tag3_clone2_q(tagpos_epn to tagpos_epn+epn_width-1), + addr_enable => addr_enable_clone, + comp_pgsize => tlb_tag3_clone2_q(tagpos_size to tagpos_size+3), + pgsize_enable => pgsize_enable_clone, + entry_size => tlb_way2_q(waypos_size to waypos_size+3), + entry_cmpmask => tlb_way2_cmpmask_q, + entry_xbit => tlb_way2_q(waypos_xbit), + entry_xbitmask => tlb_way2_xbitmask_q, + entry_epn => tlb_way2_q(waypos_epn to waypos_epn+epn_width-1), + comp_class => tlb_tag3_clone2_q(tagpos_class to tagpos_class+1), + entry_class => tlb_way2_q(waypos_class to waypos_class+1), + class_enable => class_enable_clone, + comp_extclass => comp_extclass_clone, + entry_extclass => tlb_way2_q(waypos_extclass to waypos_extclass+1), + extclass_enable => extclass_enable_clone, + comp_state => tlb_tag3_clone2_q(tagpos_state+1 to tagpos_state+2), + entry_gs => tlb_way2_q(waypos_gs), + entry_ts => tlb_way2_q(waypos_ts), + state_enable => state_enable_clone, + entry_thdid => tlb_way2_q(waypos_thdid to waypos_thdid+thdid_width-1), + comp_thdid => tlb_tag3_clone2_q(tagpos_thdid to tagpos_thdid+thdid_width-1), + thdid_enable => thdid_enable_clone, + entry_pid => tlb_way2_q(waypos_tid to waypos_tid+pid_width-1), + comp_pid => tlb_tag3_clone2_q(tagpos_pid to tagpos_pid+pid_width-1), + pid_enable => pid_enable_clone, + entry_lpid => tlb_way2_q(waypos_lpid to waypos_lpid+lpid_width-1), + comp_lpid => tlb_tag3_clone2_q(tagpos_lpid to tagpos_lpid+lpid_width-1), + lpid_enable => lpid_enable_clone, + entry_ind => tlb_way2_q(waypos_ind), + comp_ind => comp_ind_clone, + ind_enable => ind_enable_clone, + entry_iprot => lru_tag3_dataout_q(10), + comp_iprot => comp_iprot_clone, + iprot_enable => iprot_enable_clone, + entry_v => lru_tag3_dataout_q(2), + comp_invalidate => tlb_tag3_clone2_q(tagpos_type_snoop), + + match => tlb_wayhit(2), + + dbg_addr_match => tlb_way2_addr_match, + dbg_pgsize_match => tlb_way2_pgsize_match, + dbg_class_match => tlb_way2_class_match, + dbg_extclass_match => tlb_way2_extclass_match, + dbg_state_match => tlb_way2_state_match, + dbg_thdid_match => tlb_way2_thdid_match, + dbg_pid_match => tlb_way2_pid_match, + dbg_lpid_match => tlb_way2_lpid_match, + dbg_ind_match => tlb_way2_ind_match, + dbg_iprot_match => tlb_way2_iprot_match + ); +matchline_comb3 : mmq_tlb_matchline + generic map (have_xbit => 1, num_pgsizes => 5, have_cmpmask => 1, cmpmask_width => 5) + port map ( + vdd => vdd, + gnd => gnd, + addr_in => tlb_tag3_clone2_q(tagpos_epn to tagpos_epn+epn_width-1), + addr_enable => addr_enable_clone, + comp_pgsize => tlb_tag3_clone2_q(tagpos_size to tagpos_size+3), + pgsize_enable => pgsize_enable_clone, + entry_size => tlb_way3_q(waypos_size to waypos_size+3), + entry_cmpmask => tlb_way3_cmpmask_q, + entry_xbit => tlb_way3_q(waypos_xbit), + entry_xbitmask => tlb_way3_xbitmask_q, + entry_epn => tlb_way3_q(waypos_epn to waypos_epn+epn_width-1), + comp_class => tlb_tag3_clone2_q(tagpos_class to tagpos_class+1), + entry_class => tlb_way3_q(waypos_class to waypos_class+1), + class_enable => class_enable_clone, + comp_extclass => comp_extclass_clone, + entry_extclass => tlb_way3_q(waypos_extclass to waypos_extclass+1), + extclass_enable => extclass_enable_clone, + comp_state => tlb_tag3_clone2_q(tagpos_state+1 to tagpos_state+2), + entry_gs => tlb_way3_q(waypos_gs), + entry_ts => tlb_way3_q(waypos_ts), + state_enable => state_enable_clone, + entry_thdid => tlb_way3_q(waypos_thdid to waypos_thdid+thdid_width-1), + comp_thdid => tlb_tag3_clone2_q(tagpos_thdid to tagpos_thdid+thdid_width-1), + thdid_enable => thdid_enable_clone, + entry_pid => tlb_way3_q(waypos_tid to waypos_tid+pid_width-1), + comp_pid => tlb_tag3_clone2_q(tagpos_pid to tagpos_pid+pid_width-1), + pid_enable => pid_enable_clone, + entry_lpid => tlb_way3_q(waypos_lpid to waypos_lpid+lpid_width-1), + comp_lpid => tlb_tag3_clone2_q(tagpos_lpid to tagpos_lpid+lpid_width-1), + lpid_enable => lpid_enable_clone, + entry_ind => tlb_way3_q(waypos_ind), + comp_ind => comp_ind_clone, + ind_enable => ind_enable_clone, + entry_iprot => lru_tag3_dataout_q(11), + comp_iprot => comp_iprot_clone, + iprot_enable => iprot_enable_clone, + entry_v => lru_tag3_dataout_q(3), + comp_invalidate => tlb_tag3_clone2_q(tagpos_type_snoop), + + match => tlb_wayhit(3), + + dbg_addr_match => tlb_way3_addr_match, + dbg_pgsize_match => tlb_way3_pgsize_match, + dbg_class_match => tlb_way3_class_match, + dbg_extclass_match => tlb_way3_extclass_match, + dbg_state_match => tlb_way3_state_match, + dbg_thdid_match => tlb_way3_thdid_match, + dbg_pid_match => tlb_way3_pid_match, + dbg_lpid_match => tlb_way3_lpid_match, + dbg_ind_match => tlb_way3_ind_match, + dbg_iprot_match => tlb_way3_iprot_match + ); +tlb_cmp_ierat_dup_val(0 TO 6) <= tlb_erat_dup_q(0 to 6); +tlb_cmp_derat_dup_val(0 TO 6) <= tlb_erat_dup_q(10 to 16); +tlb_cmp_erat_dup_wait <= tlb_erat_dup_q(5) & tlb_erat_dup_q(15); +mm_iu_ierat_rel_val <= tlb_erat_val_q(0 to 4); +mm_iu_ierat_rel_data <= tlb_erat_rel_q; +mm_xu_derat_rel_val <= tlb_erat_val_q(5 to 9); +mm_xu_derat_rel_data <= tlb_erat_rel_clone_q; +mm_xu_eratmiss_done <= eratmiss_done_q; +mm_xu_tlb_miss <= tlb_miss_q; +mm_xu_tlb_inelig <= tlb_inelig_q; +mm_xu_lrat_miss <= lrat_miss_q; +mm_xu_pt_fault <= pt_fault_q; +mm_xu_hv_priv <= hv_priv_q; +mm_xu_esr_pt <= esr_pt_q; +mm_xu_esr_data <= esr_data_q; +mm_xu_esr_epid <= esr_epid_q; +mm_xu_esr_st <= esr_st_q; +mm_xu_cr0_eq <= cr0_eq_q; +mm_xu_cr0_eq_valid <= cr0_eq_valid_q; +mm_xu_tlb_multihit_err <= tlb_multihit_err_q; +mm_xu_tlb_par_err <= tlb_par_err_q; +mm_xu_lru_par_err <= lru_par_err_q; +tlb_tag5_except <= tlb_tag5_except_q; +tlb_tag4_esel <= tlb_tag4_q(tagpos_esel to tagpos_esel+2); +tlb_tag4_wq <= tlb_tag4_q(tagpos_wq to tagpos_wq+1); +tlb_tag4_is <= tlb_tag4_q(tagpos_is to tagpos_is+1); +tlb_tag4_hes <= tlb_tag4_q(tagpos_hes); +tlb_tag4_gs <= tlb_tag4_q(tagpos_gs); +tlb_tag4_pr <= tlb_tag4_q(tagpos_pr); +tlb_tag4_atsel <= tlb_tag4_q(tagpos_atsel); +tlb_tag4_pt <= tlb_tag4_q(tagpos_pt); +tlb_tag4_endflag <= tlb_tag4_q(tagpos_endflag) and or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1)); +lru_tag4_dataout <= lru_tag4_dataout_q(0 to 15); +tlb_tag4_cmp_hit <= tlb_tag4_wayhit_q(tlb_ways); +tlb_tag4_way_ind <= tlb_tag4_way_or(waypos_ind); +tlb_tag4_ptereload_sig <= tlb_tag4_q(tagpos_type_ptereload) and or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1)); +tlb_tag4_ptereload <= tlb_tag4_ptereload_sig; +tlb_tag4_parerr <= or_reduce(tag4_parerr_q(0 to 4)) and tlb_tag4_parerr_enab; +tlb_mas0_esel(0) <= '0'; +tlb_mas0_esel(1 TO 2) <= "01" when tlb_tag4_wayhit_q(0 to tlb_ways)="01001" + else "10" when tlb_tag4_wayhit_q(0 to tlb_ways)="00101" + else "11" when tlb_tag4_wayhit_q(0 to tlb_ways)="00011" + else "00"; +tlb_mas1_v <= lru_tag4_dataout_q(0) when + (tlb_tag4_q(tagpos_type_tlbre)='1' and tlb_tag4_q(tagpos_esel+1 to tagpos_esel+2)="00") + else lru_tag4_dataout_q(1) when + (tlb_tag4_q(tagpos_type_tlbre)='1' and tlb_tag4_q(tagpos_esel+1 to tagpos_esel+2)="01") + else lru_tag4_dataout_q(2) when + (tlb_tag4_q(tagpos_type_tlbre)='1' and tlb_tag4_q(tagpos_esel+1 to tagpos_esel+2)="10") + else lru_tag4_dataout_q(3) when + (tlb_tag4_q(tagpos_type_tlbre)='1' and tlb_tag4_q(tagpos_esel+1 to tagpos_esel+2)="11") + else tlb_tag4_wayhit_q(tlb_ways) when tlb_tag4_q(tagpos_type_tlbsx)='1' + else '0'; +tlb_mas1_iprot <= lru_tag4_dataout_q(8) when + (tlb_tag4_q(tagpos_type_tlbsx)='1' and tlb_tag4_wayhit_q(0 to tlb_ways)="10001") or + (tlb_tag4_q(tagpos_type_tlbre)='1' and tlb_tag4_q(tagpos_esel+1 to tagpos_esel+2)="00") + else lru_tag4_dataout_q(9) when + (tlb_tag4_q(tagpos_type_tlbsx)='1' and tlb_tag4_wayhit_q(0 to tlb_ways)="01001") or + (tlb_tag4_q(tagpos_type_tlbre)='1' and tlb_tag4_q(tagpos_esel+1 to tagpos_esel+2)="01") + else lru_tag4_dataout_q(10) when + (tlb_tag4_q(tagpos_type_tlbsx)='1' and tlb_tag4_wayhit_q(0 to tlb_ways)="00101") or + (tlb_tag4_q(tagpos_type_tlbre)='1' and tlb_tag4_q(tagpos_esel+1 to tagpos_esel+2)="10") + else lru_tag4_dataout_q(11) when + (tlb_tag4_q(tagpos_type_tlbsx)='1' and tlb_tag4_wayhit_q(0 to tlb_ways)="00011") or + (tlb_tag4_q(tagpos_type_tlbre)='1' and tlb_tag4_q(tagpos_esel+1 to tagpos_esel+2)="11") + else '0'; +tlb_mas1_tid <= tlb_tag4_way_rw_or(waypos_tid to waypos_tid+13) when ( or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1))='1' and + (tlb_tag4_q(tagpos_type_tlbre) or tlb_tag4_q(tagpos_type_tlbwe) or tlb_tag4_q(tagpos_type_ptereload))='1' ) + else tlb_tag4_way_or(waypos_tid to waypos_tid+13); +tlb_mas1_tid_error <= tlb_tag4_q(tagpos_pid to tagpos_pid+pid_width-1); +tlb_mas1_ind <= tlb_tag4_way_rw_or(waypos_ind) when ( or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1))='1' and + (tlb_tag4_q(tagpos_type_tlbre) or tlb_tag4_q(tagpos_type_tlbwe) or tlb_tag4_q(tagpos_type_ptereload))='1' ) + else tlb_tag4_way_or(waypos_ind); +tlb_mas1_ts <= tlb_tag4_way_rw_or(waypos_ts) when ( or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1))='1' and + (tlb_tag4_q(tagpos_type_tlbre) or tlb_tag4_q(tagpos_type_tlbwe) or tlb_tag4_q(tagpos_type_ptereload))='1' ) + else tlb_tag4_way_or(waypos_ts); +tlb_mas1_ts_error <= tlb_tag4_q(tagpos_state+2); +tlb_mas1_tsize <= tlb_tag4_way_rw_or(waypos_size to waypos_size+3) when ( or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1))='1' and + (tlb_tag4_q(tagpos_type_tlbre) or tlb_tag4_q(tagpos_type_tlbwe) or tlb_tag4_q(tagpos_type_ptereload))='1' ) + else tlb_tag4_way_or(waypos_size to waypos_size+3); +tlb_mas2_epn(0 TO 31) <= ( tlb_tag4_way_rw_or(waypos_epn to waypos_epn+31) and (0 to 31 => tlb_tag4_q(tagpos_cm))) + when ( or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1))='1' and + (tlb_tag4_q(tagpos_type_tlbre) or tlb_tag4_q(tagpos_type_tlbwe) or tlb_tag4_q(tagpos_type_ptereload))='1' ) + else tlb_tag4_way_or(waypos_epn to waypos_epn+31); +tlb_mas2_epn(32 TO epn_width-1) <= tlb_tag4_way_rw_or(waypos_epn+32 to waypos_epn+51) + when ( or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1))='1' and + (tlb_tag4_q(tagpos_type_tlbre) or tlb_tag4_q(tagpos_type_tlbwe) or tlb_tag4_q(tagpos_type_ptereload))='1' ) + else tlb_tag4_way_or(waypos_epn+32 to waypos_epn+51); +tlb_mas2_epn_error <= tlb_tag4_q(tagpos_epn to tagpos_epn+epn_width-1); +tlb_mas2_wimge <= tlb_tag4_way_rw_or(waypos_wimge to waypos_wimge+4) when ( or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1))='1' and + (tlb_tag4_q(tagpos_type_tlbre) or tlb_tag4_q(tagpos_type_tlbwe) or tlb_tag4_q(tagpos_type_ptereload))='1' ) + else tlb_tag4_way_or(waypos_wimge to waypos_wimge+4); +tlb_mas3_rpnl <= tlb_tag4_way_rw_or(waypos_rpn+10 to waypos_rpn+rpn_width-1) when ( or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1))='1' and + (tlb_tag4_q(tagpos_type_tlbre) or tlb_tag4_q(tagpos_type_tlbwe) or tlb_tag4_q(tagpos_type_ptereload))='1' ) + else tlb_tag4_way_or(waypos_rpn+10 to waypos_rpn+rpn_width-1); +tlb_mas3_ubits <= tlb_tag4_way_rw_or(waypos_ubits to waypos_ubits+3) when ( or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1))='1' and + (tlb_tag4_q(tagpos_type_tlbre) or tlb_tag4_q(tagpos_type_tlbwe) or tlb_tag4_q(tagpos_type_ptereload))='1' ) + else tlb_tag4_way_or(waypos_ubits to waypos_ubits+3); +tlb_mas3_usxwr <= tlb_tag4_way_rw_or(waypos_usxwr to waypos_usxwr+5) when ( or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1))='1' and + (tlb_tag4_q(tagpos_type_tlbre) or tlb_tag4_q(tagpos_type_tlbwe) or tlb_tag4_q(tagpos_type_ptereload))='1' ) + else tlb_tag4_way_or(waypos_usxwr to waypos_usxwr+5); +tlb_mas6_spid <= tlb_tag4_q(tagpos_pid to tagpos_pid+pid_width-1); +tlb_mas6_isize <= tlb_tag4_q(tagpos_size to tagpos_size+3); +tlb_mas6_sind <= tlb_tag4_q(tagpos_ind); +tlb_mas6_sas <= tlb_tag4_q(tagpos_state+2); +tlb_mas7_rpnu <= tlb_tag4_way_rw_or(waypos_rpn to waypos_rpn+9) when ( or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1))='1' and + (tlb_tag4_q(tagpos_type_tlbre) or tlb_tag4_q(tagpos_type_tlbwe) or tlb_tag4_q(tagpos_type_ptereload))='1' ) + else tlb_tag4_way_or(waypos_rpn to waypos_rpn+9); +tlb_mas8_tgs <= tlb_tag4_way_rw_or(waypos_gs) when ( or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1))='1' and + (tlb_tag4_q(tagpos_type_tlbre) or tlb_tag4_q(tagpos_type_tlbwe) or tlb_tag4_q(tagpos_type_ptereload))='1' ) + else tlb_tag4_way_or(waypos_gs); +tlb_mas8_vf <= tlb_tag4_way_rw_or(waypos_vf) when ( or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1))='1' and + (tlb_tag4_q(tagpos_type_tlbre) or tlb_tag4_q(tagpos_type_tlbwe) or tlb_tag4_q(tagpos_type_ptereload))='1' ) + else tlb_tag4_way_or(waypos_vf); +tlb_mas8_tlpid <= tlb_tag4_way_rw_or(waypos_lpid to waypos_lpid+lpid_width-1) when ( or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1))='1' and + (tlb_tag4_q(tagpos_type_tlbre) or tlb_tag4_q(tagpos_type_tlbwe) or tlb_tag4_q(tagpos_type_ptereload))='1' ) + else tlb_tag4_way_or(waypos_lpid to waypos_lpid+lpid_width-1); +tlb_mmucr3_thdid <= tlb_tag4_way_rw_or(waypos_thdid to waypos_thdid+thdid_width-1) when ( or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1))='1' and + (tlb_tag4_q(tagpos_type_tlbre) or tlb_tag4_q(tagpos_type_tlbwe) or tlb_tag4_q(tagpos_type_ptereload))='1' ) + else tlb_tag4_way_or(waypos_thdid to waypos_thdid+thdid_width-1); +tlb_mmucr3_resvattr <= tlb_tag4_way_rw_or(waypos_resvattr) when ( or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1))='1' and + (tlb_tag4_q(tagpos_type_tlbre) or tlb_tag4_q(tagpos_type_tlbwe) or tlb_tag4_q(tagpos_type_ptereload))='1' ) + else tlb_tag4_way_or(waypos_resvattr); +tlb_mmucr3_wlc <= tlb_tag4_way_rw_or(waypos_wlc to waypos_wlc+1) when ( or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1))='1' and + (tlb_tag4_q(tagpos_type_tlbre) or tlb_tag4_q(tagpos_type_tlbwe) or tlb_tag4_q(tagpos_type_ptereload))='1' ) + else tlb_tag4_way_or(waypos_wlc to waypos_wlc+1); +tlb_mmucr3_class <= tlb_tag4_way_rw_or(waypos_class to waypos_class+1) when ( or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1))='1' and + (tlb_tag4_q(tagpos_type_tlbre) or tlb_tag4_q(tagpos_type_tlbwe) or tlb_tag4_q(tagpos_type_ptereload))='1' ) + else tlb_tag4_way_or(waypos_class to waypos_class+1); +tlb_mmucr3_extclass <= tlb_tag4_way_rw_or(waypos_extclass to waypos_extclass+1) when ( or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1))='1' and + (tlb_tag4_q(tagpos_type_tlbre) or tlb_tag4_q(tagpos_type_tlbwe) or tlb_tag4_q(tagpos_type_ptereload))='1' ) + else tlb_tag4_way_or(waypos_extclass to waypos_extclass+1); +tlb_mmucr3_rc <= tlb_tag4_way_rw_or(waypos_rc to waypos_rc+1) when ( or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1))='1' and + (tlb_tag4_q(tagpos_type_tlbre) or tlb_tag4_q(tagpos_type_tlbwe) or tlb_tag4_q(tagpos_type_ptereload))='1' ) + else tlb_tag4_way_or(waypos_rc to waypos_rc+1); +tlb_mmucr3_x <= tlb_tag4_way_rw_or(waypos_xbit) when ( or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1))='1' and + (tlb_tag4_q(tagpos_type_tlbre) or tlb_tag4_q(tagpos_type_tlbwe) or tlb_tag4_q(tagpos_type_ptereload))='1' ) + else tlb_tag4_way_or(waypos_xbit); +tlb_mmucr1_een <= tlb_addr4_q & (tag4_parerr_q(2) or tag4_parerr_q(3)) & (tag4_parerr_q(1) or tag4_parerr_q(3)); +tlb_mmucr1_we <= ( ( (or_reduce(tag4_parerr_q(0 to 4)) and or_reduce(tlb_tag4_q(tagpos_type_derat to tagpos_type_tlbsrx)) and not tlb_tag4_q(tagpos_type_ptereload)) or tlb_tag4_tlbre_parerr ) + and ECO107332_orred_tag4_thdid_flushed ) + or ( multihit and tlb_tag4_wayhit_q(tlb_ways) and or_reduce(tlb_tag4_q(tagpos_type_derat to tagpos_type_tlbsrx)) and not tlb_tag4_q(tagpos_type_ptereload) ); +ECO107332_orred_tag4_thdid_flushed <= or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag4_flush)); +tlb_mas_dtlb_error <= tlb_tag4_q(tagpos_type_derat) and tlb_tag4_q(tagpos_endflag) and not tlb_tag4_wayhit_q(tlb_ways) and (not(or_reduce(tag4_parerr_q(0 to 4))) or cswitch_q(6)) and + or_reduce( (msr_gs_q or msr_pr_q or not epcr_dmiuh_q) and tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) ); +tlb_mas_itlb_error <= tlb_tag4_q(tagpos_type_ierat) and tlb_tag4_q(tagpos_endflag) and not tlb_tag4_wayhit_q(tlb_ways) and (not(or_reduce(tag4_parerr_q(0 to 4))) or cswitch_q(6)) and + or_reduce( (msr_gs_q or msr_pr_q or not epcr_dmiuh_q) and tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) ); +tlb_mas_tlbsx_hit <= tlb_tag4_q(tagpos_type_tlbsx) and tlb_tag4_wayhit_q(tlb_ways) and not multihit and tlb_tag4_hv_op and (not(or_reduce(tag4_parerr_q(0 to 4))) or cswitch_q(5)); +tlb_mas_tlbsx_miss <= tlb_tag4_q(tagpos_type_tlbsx) and tlb_tag4_q(tagpos_endflag) and not tlb_tag4_wayhit_q(tlb_ways) and tlb_tag4_hv_op and (not(or_reduce(tag4_parerr_q(0 to 4))) or cswitch_q(6)); +tlb_mas_tlbre <= tlb_tag4_q(tagpos_type_tlbre) and not tlb_tag4_q(tagpos_atsel) and tlb_tag4_hv_op and not ex6_illeg_instr(0) and (not(tlb_tag4_tlbre_parerr) or cswitch_q(7)); +tlb_mas_thdid <= tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag4_flush); +tlbwe_tag3_back_inv_enab <= + ( lru_tag3_dataout_q(0) and (lru_tag3_dataout_q(8) or not cswitch_q(0)) and (not(tlb_tag3_q(tagpos_is)) or not(cswitch_q(3))) and not tlb_tag3_q(tagpos_hes) and not tlb_tag3_q(tagpos_esel+1) and not tlb_tag3_q(tagpos_esel+2) ) or + ( lru_tag3_dataout_q(1) and (lru_tag3_dataout_q(9) or not cswitch_q(0)) and (not(tlb_tag3_q(tagpos_is)) or not(cswitch_q(3))) and not tlb_tag3_q(tagpos_hes) and not tlb_tag3_q(tagpos_esel+1) and tlb_tag3_q(tagpos_esel+2) ) or + ( lru_tag3_dataout_q(2) and (lru_tag3_dataout_q(10) or not cswitch_q(0)) and (not(tlb_tag3_q(tagpos_is)) or not(cswitch_q(3))) and not tlb_tag3_q(tagpos_hes) and tlb_tag3_q(tagpos_esel+1) and not tlb_tag3_q(tagpos_esel+2) ) or + ( lru_tag3_dataout_q(3) and (lru_tag3_dataout_q(11) or not cswitch_q(0)) and (not(tlb_tag3_q(tagpos_is)) or not(cswitch_q(3))) and not tlb_tag3_q(tagpos_hes) and tlb_tag3_q(tagpos_esel+1) and tlb_tag3_q(tagpos_esel+2) ) or + ( lru_tag3_dataout_q(0) and (lru_tag3_dataout_q(8) or not cswitch_q(0)) and (not(tlb_tag3_q(tagpos_is)) or not(cswitch_q(3))) and tlb_tag3_q(tagpos_hes) and cswitch_q(1) and not lru_tag3_dataout_q(4) and not lru_tag3_dataout_q(5) ) or + ( lru_tag3_dataout_q(1) and (lru_tag3_dataout_q(9) or not cswitch_q(0)) and (not(tlb_tag3_q(tagpos_is)) or not(cswitch_q(3))) and tlb_tag3_q(tagpos_hes) and cswitch_q(1) and not lru_tag3_dataout_q(4) and lru_tag3_dataout_q(5) ) or + ( lru_tag3_dataout_q(2) and (lru_tag3_dataout_q(10) or not cswitch_q(0)) and (not(tlb_tag3_q(tagpos_is)) or not(cswitch_q(3))) and tlb_tag3_q(tagpos_hes) and cswitch_q(1) and lru_tag3_dataout_q(4) and not lru_tag3_dataout_q(6) ) or + ( lru_tag3_dataout_q(3) and (lru_tag3_dataout_q(11) or not cswitch_q(0)) and (not(tlb_tag3_q(tagpos_is)) or not(cswitch_q(3))) and tlb_tag3_q(tagpos_hes) and cswitch_q(1) and lru_tag3_dataout_q(4) and lru_tag3_dataout_q(6) ); +tlbwe_tag4_back_inv_d(0 TO thdid_width-1) <= tlb_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag3_flush); +tlbwe_tag4_back_inv_d(thdid_width) <= ( tlbwe_tag3_back_inv_enab and tlb_tag3_q(tagpos_type_tlbwe) and not(Eq(tlb_tag3_q(tagpos_wq to tagpos_wq+1),"10")) and mmucr1_q(pos_tlbwe_binv) and + ((not(tlb_tag3_q(tagpos_gs)) and not(tlb_tag3_q(tagpos_atsel))) or + (tlb_tag3_q(tagpos_gs) and tlb_tag3_q(tagpos_hes) and lrat_tag3_hit_status(1) and not lrat_tag3_hit_status(2))) and + or_reduce(tlb_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag3_flush)) ); +tlbwe_tag4_back_inv_attr_d(18) <= + ( lru_tag3_dataout_q(0) and (lru_tag3_dataout_q(8) or not cswitch_q(2)) and not tlb_tag3_q(tagpos_hes) and not tlb_tag3_q(tagpos_esel+1) and not tlb_tag3_q(tagpos_esel+2) ) or + ( lru_tag3_dataout_q(1) and (lru_tag3_dataout_q(9) or not cswitch_q(2)) and not tlb_tag3_q(tagpos_hes) and not tlb_tag3_q(tagpos_esel+1) and tlb_tag3_q(tagpos_esel+2) ) or + ( lru_tag3_dataout_q(2) and (lru_tag3_dataout_q(10) or not cswitch_q(2)) and not tlb_tag3_q(tagpos_hes) and tlb_tag3_q(tagpos_esel+1) and not tlb_tag3_q(tagpos_esel+2) ) or + ( lru_tag3_dataout_q(3) and (lru_tag3_dataout_q(11) or not cswitch_q(2)) and not tlb_tag3_q(tagpos_hes) and tlb_tag3_q(tagpos_esel+1) and tlb_tag3_q(tagpos_esel+2) ) or + ( lru_tag3_dataout_q(0) and (lru_tag3_dataout_q(8) or not cswitch_q(2)) and tlb_tag3_q(tagpos_hes) and not lru_tag3_dataout_q(4) and not lru_tag3_dataout_q(5) ) or + ( lru_tag3_dataout_q(1) and (lru_tag3_dataout_q(9) or not cswitch_q(2)) and tlb_tag3_q(tagpos_hes) and not lru_tag3_dataout_q(4) and lru_tag3_dataout_q(5) ) or + ( lru_tag3_dataout_q(2) and (lru_tag3_dataout_q(10) or not cswitch_q(2)) and tlb_tag3_q(tagpos_hes) and lru_tag3_dataout_q(4) and not lru_tag3_dataout_q(6) ) or + ( lru_tag3_dataout_q(3) and (lru_tag3_dataout_q(11) or not cswitch_q(2)) and tlb_tag3_q(tagpos_hes) and lru_tag3_dataout_q(4) and lru_tag3_dataout_q(6) ); +tlbwe_tag4_back_inv_attr_d(19) <= '0'; +tlbwe_back_inv_valid <= tlbwe_tag4_back_inv_q(thdid_width) and (not(tlb_tag4_way_rw_or(waypos_ind)) or cswitch_q(4)); +tlbwe_back_inv_thdid <= tlbwe_tag4_back_inv_q(0 to thdid_width-1); +tlbwe_back_inv_addr <= tlb_tag4_way_rw_or(waypos_epn to waypos_epn+51); +tlbwe_back_inv_attr <= '1' & "011" & + tlb_tag4_way_rw_or(waypos_gs) & tlb_tag4_way_rw_or(waypos_ts) & + tlb_tag4_way_rw_or(waypos_tid+6 to waypos_tid+13) & + tlb_tag4_way_rw_or(waypos_size to waypos_size+3) & + tlbwe_tag4_back_inv_attr_q(18 to 19) & + tlb_tag4_way_rw_or(waypos_tid to waypos_tid+5) & + tlb_tag4_way_rw_or(waypos_lpid to waypos_lpid+lpid_width-1) & + tlb_tag4_way_rw_or(waypos_ind); +lru_write <= lru_write_q and (0 to lru_width-1 => not or_reduce(tlb_tag5_except_q)); +lru_wr_addr <= lru_wr_addr_q; +lru_datain <= lru_datain_q; +tlb_htw_req_valid <= '1' when (tlb_tag4_q(tagpos_type_derat to tagpos_type_ierat)/="00" and tlb_tag4_q(tagpos_type_ptereload)='0' and + tlb_tag4_q(tagpos_ind)='1' and tlb_tag4_wayhit_q(tlb_ways)='1' and multihit='0') + else '0'; +tlb_htw_req_way <= tlb_tag4_way_or(tlb_word_width to tlb_way_width-1); +tlb_htw_req_tag(0 TO epn_width-1) <= tlb_tag4_q(0 to epn_width-1); +tlb_htw_req_tag(tagpos_pid TO tagpos_pid+pid_width-1) <= tlb_tag4_way_or(waypos_tid to waypos_tid+pid_width-1); +tlb_htw_req_tag(tagpos_is TO tagpos_class+1) <= tlb_tag4_q(tagpos_is to tagpos_class+1); +tlb_htw_req_tag(tagpos_pr) <= tlb_tag4_q(tagpos_pr); +tlb_htw_req_tag(tagpos_gs) <= tlb_tag4_way_or(waypos_gs); +tlb_htw_req_tag(tagpos_as) <= tlb_tag4_way_or(waypos_ts); +tlb_htw_req_tag(tagpos_cm) <= tlb_tag4_q(tagpos_cm); +tlb_htw_req_tag(tagpos_thdid TO tagpos_lpid-1) <= tlb_tag4_q(tagpos_thdid to tagpos_lpid-1); +tlb_htw_req_tag(tagpos_lpid TO tagpos_lpid+lpid_width-1) <= tlb_tag4_way_or(waypos_lpid to waypos_lpid+lpid_width-1); +tlb_htw_req_tag(tagpos_ind) <= tlb_tag4_q(tagpos_ind); +tlb_htw_req_tag(tagpos_atsel) <= tlb_tag4_way_or(waypos_thdid); +tlb_htw_req_tag(tagpos_esel TO tagpos_esel+2) <= tlb_tag4_way_or(waypos_thdid+1 to waypos_thdid+3); +tlb_htw_req_tag(tagpos_hes TO tlb_tag_width-1) <= tlb_tag4_q(tagpos_hes to tlb_tag_width-1); +tlb_cmp_perf_event_t0(0) <= tlb_tag4_q(tagpos_thdid+0) and tlb_tag4_q(tagpos_type_ierat) and not tlb_tag4_q(tagpos_type_ptereload) and + not tlb_tag4_q(tagpos_ind) and tlb_tag4_wayhit_q(tlb_ways) and not multihit; +tlb_cmp_perf_event_t0(1) <= tlb_tag4_q(tagpos_thdid+0) and tlb_tag4_q(tagpos_type_ierat) and not tlb_tag4_q(tagpos_type_ptereload) and + not tlb_tag4_q(tagpos_ind) and not tlb_tag4_wayhit_q(tlb_ways) and + (tlb_tag3_q(tagpos_ind) or tlb_tag4_q(tagpos_endflag)); +tlb_cmp_perf_event_t0(2) <= tlb_tag4_q(tagpos_thdid+0) and tlb_tag4_q(tagpos_type_ierat) and not tlb_tag4_q(tagpos_type_ptereload) and + tlb_tag4_q(tagpos_ind) and not tlb_tag4_wayhit_q(tlb_ways) and + tlb_tag4_q(tagpos_endflag); +tlb_cmp_perf_event_t0(3) <= tlb_tag4_q(tagpos_thdid+0) and tlb_tag4_q(tagpos_type_ierat) and tlb_tag4_q(tagpos_type_ptereload) and + tlb_tag4_q(tagpos_is); +tlb_cmp_perf_event_t0(4) <= tlb_tag4_q(tagpos_thdid+0) and tlb_tag4_q(tagpos_type_ierat) and tlb_tag4_q(tagpos_type_ptereload) and + not tlb_tag4_q(tagpos_is); +tlb_cmp_perf_event_t0(5) <= tlb_tag4_q(tagpos_thdid+0) and tlb_tag4_q(tagpos_type_derat) and not tlb_tag4_q(tagpos_type_ptereload) and + not tlb_tag4_q(tagpos_ind) and tlb_tag4_wayhit_q(tlb_ways) and not multihit; +tlb_cmp_perf_event_t0(6) <= tlb_tag4_q(tagpos_thdid+0) and tlb_tag4_q(tagpos_type_derat) and not tlb_tag4_q(tagpos_type_ptereload) and + not tlb_tag4_q(tagpos_ind) and not tlb_tag4_wayhit_q(tlb_ways) and + (tlb_tag3_q(tagpos_ind) or tlb_tag4_q(tagpos_endflag)); +tlb_cmp_perf_event_t0(7) <= tlb_tag4_q(tagpos_thdid+0) and tlb_tag4_q(tagpos_type_derat) and not tlb_tag4_q(tagpos_type_ptereload) and + tlb_tag4_q(tagpos_ind) and not tlb_tag4_wayhit_q(tlb_ways) and + tlb_tag4_q(tagpos_endflag); +tlb_cmp_perf_event_t0(8) <= tlb_tag4_q(tagpos_thdid+0) and tlb_tag4_q(tagpos_type_derat) and tlb_tag4_q(tagpos_type_ptereload) and + tlb_tag4_q(tagpos_is); +tlb_cmp_perf_event_t0(9) <= tlb_tag4_q(tagpos_thdid+0) and tlb_tag4_q(tagpos_type_derat) and tlb_tag4_q(tagpos_type_ptereload) and + not tlb_tag4_q(tagpos_is); +tlb_cmp_perf_event_t1(0) <= tlb_tag4_q(tagpos_thdid+1) and tlb_tag4_q(tagpos_type_ierat) and not tlb_tag4_q(tagpos_type_ptereload) and + not tlb_tag4_q(tagpos_ind) and tlb_tag4_wayhit_q(tlb_ways) and not multihit; +tlb_cmp_perf_event_t1(1) <= tlb_tag4_q(tagpos_thdid+1) and tlb_tag4_q(tagpos_type_ierat) and not tlb_tag4_q(tagpos_type_ptereload) and + not tlb_tag4_q(tagpos_ind) and not tlb_tag4_wayhit_q(tlb_ways) and + (tlb_tag3_q(tagpos_ind) or tlb_tag4_q(tagpos_endflag)); +tlb_cmp_perf_event_t1(2) <= tlb_tag4_q(tagpos_thdid+1) and tlb_tag4_q(tagpos_type_ierat) and not tlb_tag4_q(tagpos_type_ptereload) and + tlb_tag4_q(tagpos_ind) and not tlb_tag4_wayhit_q(tlb_ways) and + tlb_tag4_q(tagpos_endflag); +tlb_cmp_perf_event_t1(3) <= tlb_tag4_q(tagpos_thdid+1) and tlb_tag4_q(tagpos_type_ierat) and tlb_tag4_q(tagpos_type_ptereload) and + tlb_tag4_q(tagpos_is); +tlb_cmp_perf_event_t1(4) <= tlb_tag4_q(tagpos_thdid+1) and tlb_tag4_q(tagpos_type_ierat) and tlb_tag4_q(tagpos_type_ptereload) and + not tlb_tag4_q(tagpos_is); +tlb_cmp_perf_event_t1(5) <= tlb_tag4_q(tagpos_thdid+1) and tlb_tag4_q(tagpos_type_derat) and not tlb_tag4_q(tagpos_type_ptereload) and + not tlb_tag4_q(tagpos_ind) and tlb_tag4_wayhit_q(tlb_ways) and not multihit; +tlb_cmp_perf_event_t1(6) <= tlb_tag4_q(tagpos_thdid+1) and tlb_tag4_q(tagpos_type_derat) and not tlb_tag4_q(tagpos_type_ptereload) and + not tlb_tag4_q(tagpos_ind) and not tlb_tag4_wayhit_q(tlb_ways) and + (tlb_tag3_q(tagpos_ind) or tlb_tag4_q(tagpos_endflag)); +tlb_cmp_perf_event_t1(7) <= tlb_tag4_q(tagpos_thdid+1) and tlb_tag4_q(tagpos_type_derat) and not tlb_tag4_q(tagpos_type_ptereload) and + tlb_tag4_q(tagpos_ind) and not tlb_tag4_wayhit_q(tlb_ways) and + tlb_tag4_q(tagpos_endflag); +tlb_cmp_perf_event_t1(8) <= tlb_tag4_q(tagpos_thdid+1) and tlb_tag4_q(tagpos_type_derat) and tlb_tag4_q(tagpos_type_ptereload) and + tlb_tag4_q(tagpos_is); +tlb_cmp_perf_event_t1(9) <= tlb_tag4_q(tagpos_thdid+1) and tlb_tag4_q(tagpos_type_derat) and tlb_tag4_q(tagpos_type_ptereload) and + not tlb_tag4_q(tagpos_is); +tlb_cmp_perf_event_t2(0) <= tlb_tag4_q(tagpos_thdid+2) and tlb_tag4_q(tagpos_type_ierat) and not tlb_tag4_q(tagpos_type_ptereload) and + not tlb_tag4_q(tagpos_ind) and tlb_tag4_wayhit_q(tlb_ways) and not multihit; +tlb_cmp_perf_event_t2(1) <= tlb_tag4_q(tagpos_thdid+2) and tlb_tag4_q(tagpos_type_ierat) and not tlb_tag4_q(tagpos_type_ptereload) and + not tlb_tag4_q(tagpos_ind) and not tlb_tag4_wayhit_q(tlb_ways) and + (tlb_tag3_q(tagpos_ind) or tlb_tag4_q(tagpos_endflag)); +tlb_cmp_perf_event_t2(2) <= tlb_tag4_q(tagpos_thdid+2) and tlb_tag4_q(tagpos_type_ierat) and not tlb_tag4_q(tagpos_type_ptereload) and + tlb_tag4_q(tagpos_ind) and not tlb_tag4_wayhit_q(tlb_ways) and + tlb_tag4_q(tagpos_endflag); +tlb_cmp_perf_event_t2(3) <= tlb_tag4_q(tagpos_thdid+2) and tlb_tag4_q(tagpos_type_ierat) and tlb_tag4_q(tagpos_type_ptereload) and + tlb_tag4_q(tagpos_is); +tlb_cmp_perf_event_t2(4) <= tlb_tag4_q(tagpos_thdid+2) and tlb_tag4_q(tagpos_type_ierat) and tlb_tag4_q(tagpos_type_ptereload) and + not tlb_tag4_q(tagpos_is); +tlb_cmp_perf_event_t2(5) <= tlb_tag4_q(tagpos_thdid+2) and tlb_tag4_q(tagpos_type_derat) and not tlb_tag4_q(tagpos_type_ptereload) and + not tlb_tag4_q(tagpos_ind) and tlb_tag4_wayhit_q(tlb_ways) and not multihit; +tlb_cmp_perf_event_t2(6) <= tlb_tag4_q(tagpos_thdid+2) and tlb_tag4_q(tagpos_type_derat) and not tlb_tag4_q(tagpos_type_ptereload) and + not tlb_tag4_q(tagpos_ind) and not tlb_tag4_wayhit_q(tlb_ways) and + (tlb_tag3_q(tagpos_ind) or tlb_tag4_q(tagpos_endflag)); +tlb_cmp_perf_event_t2(7) <= tlb_tag4_q(tagpos_thdid+2) and tlb_tag4_q(tagpos_type_derat) and not tlb_tag4_q(tagpos_type_ptereload) and + tlb_tag4_q(tagpos_ind) and not tlb_tag4_wayhit_q(tlb_ways) and + tlb_tag4_q(tagpos_endflag); +tlb_cmp_perf_event_t2(8) <= tlb_tag4_q(tagpos_thdid+2) and tlb_tag4_q(tagpos_type_derat) and tlb_tag4_q(tagpos_type_ptereload) and + tlb_tag4_q(tagpos_is); +tlb_cmp_perf_event_t2(9) <= tlb_tag4_q(tagpos_thdid+2) and tlb_tag4_q(tagpos_type_derat) and tlb_tag4_q(tagpos_type_ptereload) and + not tlb_tag4_q(tagpos_is); +tlb_cmp_perf_event_t3(0) <= tlb_tag4_q(tagpos_thdid+3) and tlb_tag4_q(tagpos_type_ierat) and not tlb_tag4_q(tagpos_type_ptereload) and + not tlb_tag4_q(tagpos_ind) and tlb_tag4_wayhit_q(tlb_ways) and not multihit; +tlb_cmp_perf_event_t3(1) <= tlb_tag4_q(tagpos_thdid+3) and tlb_tag4_q(tagpos_type_ierat) and not tlb_tag4_q(tagpos_type_ptereload) and + not tlb_tag4_q(tagpos_ind) and not tlb_tag4_wayhit_q(tlb_ways) and + (tlb_tag3_q(tagpos_ind) or tlb_tag4_q(tagpos_endflag)); +tlb_cmp_perf_event_t3(2) <= tlb_tag4_q(tagpos_thdid+3) and tlb_tag4_q(tagpos_type_ierat) and not tlb_tag4_q(tagpos_type_ptereload) and + tlb_tag4_q(tagpos_ind) and not tlb_tag4_wayhit_q(tlb_ways) and + tlb_tag4_q(tagpos_endflag); +tlb_cmp_perf_event_t3(3) <= tlb_tag4_q(tagpos_thdid+3) and tlb_tag4_q(tagpos_type_ierat) and tlb_tag4_q(tagpos_type_ptereload) and + tlb_tag4_q(tagpos_is); +tlb_cmp_perf_event_t3(4) <= tlb_tag4_q(tagpos_thdid+3) and tlb_tag4_q(tagpos_type_ierat) and tlb_tag4_q(tagpos_type_ptereload) and + not tlb_tag4_q(tagpos_is); +tlb_cmp_perf_event_t3(5) <= tlb_tag4_q(tagpos_thdid+3) and tlb_tag4_q(tagpos_type_derat) and not tlb_tag4_q(tagpos_type_ptereload) and + not tlb_tag4_q(tagpos_ind) and tlb_tag4_wayhit_q(tlb_ways) and not multihit; +tlb_cmp_perf_event_t3(6) <= tlb_tag4_q(tagpos_thdid+3) and tlb_tag4_q(tagpos_type_derat) and not tlb_tag4_q(tagpos_type_ptereload) and + not tlb_tag4_q(tagpos_ind) and not tlb_tag4_wayhit_q(tlb_ways) and + (tlb_tag3_q(tagpos_ind) or tlb_tag4_q(tagpos_endflag)); +tlb_cmp_perf_event_t3(7) <= tlb_tag4_q(tagpos_thdid+3) and tlb_tag4_q(tagpos_type_derat) and not tlb_tag4_q(tagpos_type_ptereload) and + tlb_tag4_q(tagpos_ind) and not tlb_tag4_wayhit_q(tlb_ways) and + tlb_tag4_q(tagpos_endflag); +tlb_cmp_perf_event_t3(8) <= tlb_tag4_q(tagpos_thdid+3) and tlb_tag4_q(tagpos_type_derat) and tlb_tag4_q(tagpos_type_ptereload) and + tlb_tag4_q(tagpos_is); +tlb_cmp_perf_event_t3(9) <= tlb_tag4_q(tagpos_thdid+3) and tlb_tag4_q(tagpos_type_derat) and tlb_tag4_q(tagpos_type_ptereload) and + not tlb_tag4_q(tagpos_is); +tlb_cmp_perf_state <= tlb_tag4_q(tagpos_gs) & tlb_tag4_q(tagpos_pr); +tlb_cmp_perf_miss_direct <= or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1)) and or_reduce(tlb_tag4_q(tagpos_type_derat to tagpos_type_ierat)) and + not tlb_tag4_q(tagpos_type_ptereload) and not tlb_tag4_q(tagpos_ind) and not tlb_tag4_wayhit_q(tlb_ways) and + (tlb_tag3_q(tagpos_ind) or tlb_tag4_q(tagpos_endflag)); +tlb_cmp_perf_hit_indirect <= or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1)) and or_reduce(tlb_tag4_q(tagpos_type_derat to tagpos_type_ierat)) and + not tlb_tag4_q(tagpos_type_ptereload) and tlb_tag4_q(tagpos_ind) and tlb_tag4_wayhit_q(tlb_ways) and not multihit; +tlb_cmp_perf_hit_first_page <= or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1)) and or_reduce(tlb_tag4_q(tagpos_type_derat to tagpos_type_ierat)) and + not tlb_tag4_q(tagpos_type_ptereload) and not tlb_tag4_q(tagpos_ind) and tlb_tag4_wayhit_q(tlb_ways) and not multihit and + Eq(tlb_tag4_q(tagpos_esel to tagpos_esel+2),"001"); +tlb_cmp_perf_pt_fault <= or_reduce(pt_fault_q); +tlb_cmp_perf_pt_inelig <= or_reduce(tlb_inelig_q); +tlb_cmp_perf_lrat_miss <= or_reduce(lrat_miss_q); +tlb_cmp_perf_ptereload_noexcep <= or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1)) + when ( tlb_tag4_q(tagpos_type_ptereload)='1' and tlb_tag4_q(tagpos_is)='1' and + tlb_tag4_q(tagpos_wq to tagpos_wq+1)="10" and + tlb_tag4_q(tagpos_pt)='1' and + or_reduce(pt_fault_d or tlb_inelig_d or lrat_miss_d)='0' ) + else '0'; +tlb_cmp_perf_lrat_request <= or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag4_flush)) + when ( ((or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and tlb_resv_match_vec)='1' + and tlb_tag4_q(tagpos_wq to tagpos_wq+1)="01" and mmucfg_twc='1') + or tlb_tag4_q(tagpos_wq to tagpos_wq+1)="00" or tlb_tag4_q(tagpos_wq to tagpos_wq+1)="11") and + tlb_tag4_q(tagpos_type_tlbwe)='1' and tlb_tag4_q(tagpos_gs)='1' and tlb_tag4_q(tagpos_pr)='0' and + tlb_tag4_epcr_dgtmi='0' and mmucfg_lrat='1' and + tlb_tag4_q(tagpos_is)='1' ) + else or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1)) + when (tlb_tag4_q(tagpos_type_ptereload)='1' and tlb_tag4_q(tagpos_gs)='1' and mmucfg_lrat='1' and + tlb_tag4_q(tagpos_is)='1' and + tlb_tag4_q(tagpos_wq to tagpos_wq+1)="10" and + tlb_tag4_q(tagpos_pt)='1') + else '0'; +tlb_cmp_dbg_tag4 <= tlb_tag4_q; +tlb_cmp_dbg_tag4_wayhit <= tlb_tag4_wayhit_q; +tlb_cmp_dbg_addr4 <= tlb_addr4_q; +tlb_cmp_dbg_tag4_way <= tlb_tag4_way_rw_or when ( or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1))='1' and + (tlb_tag4_q(tagpos_type_tlbre) or tlb_tag4_q(tagpos_type_tlbwe) or tlb_tag4_q(tagpos_type_ptereload))='1' ) + else tlb_tag4_way_or; +tlb_cmp_dbg_tag4_parerr <= tag4_parerr_q; +tlb_cmp_dbg_tag4_lru_dataout_q <= lru_tag4_dataout_q(0 to lru_width-5); +tlb_cmp_dbg_tag5_lru_datain_q <= lru_datain_q(0 to lru_width-5); +tlb_cmp_dbg_tag5_lru_write <= lru_write_q(0); +tlb_cmp_dbg_tag5_any_exception <= or_reduce(tlb_miss_q) or or_reduce(hv_priv_q) or or_reduce(lrat_miss_q) or or_reduce(pt_fault_q) or or_reduce(tlb_inelig_q); +tlb_cmp_dbg_tag5_except_type_q <= or_reduce(hv_priv_q) & or_reduce(lrat_miss_q) & or_reduce(pt_fault_q) & or_reduce(tlb_inelig_q); +tlb_cmp_dbg_tag5_except_thdid_q(0) <= hv_priv_q(2) or hv_priv_q(3) or lrat_miss_q(2) or lrat_miss_q(3) or + pt_fault_q(2) or pt_fault_q(3) or tlb_inelig_q(2) or tlb_inelig_q(3) or + tlb_miss_q(2) or tlb_miss_q(3); +tlb_cmp_dbg_tag5_except_thdid_q(1) <= hv_priv_q(1) or hv_priv_q(3) or lrat_miss_q(1) or lrat_miss_q(3) or + pt_fault_q(1) or pt_fault_q(3) or tlb_inelig_q(1) or tlb_inelig_q(3) or + tlb_miss_q(1) or tlb_miss_q(3); +tlb_cmp_dbg_tag5_erat_rel_val <= tlb_erat_val_q; +tlb_cmp_dbg_tag5_erat_rel_data <= tlb_erat_rel_q; +tlb_cmp_dbg_erat_dup_q <= tlb_erat_dup_q; +tlb_cmp_dbg_addr_enable <= addr_enable; +tlb_cmp_dbg_pgsize_enable <= pgsize_enable; +tlb_cmp_dbg_class_enable <= class_enable; +tlb_cmp_dbg_extclass_enable <= extclass_enable; +tlb_cmp_dbg_state_enable <= state_enable; +tlb_cmp_dbg_thdid_enable <= thdid_enable; +tlb_cmp_dbg_pid_enable <= pid_enable; +tlb_cmp_dbg_lpid_enable <= lpid_enable; +tlb_cmp_dbg_ind_enable <= ind_enable; +tlb_cmp_dbg_iprot_enable <= iprot_enable; +tlb_cmp_dbg_way0_entry_v <= lru_tag3_dataout_q(0); +tlb_cmp_dbg_way0_addr_match <= tlb_way0_addr_match; +tlb_cmp_dbg_way0_pgsize_match <= tlb_way0_pgsize_match; +tlb_cmp_dbg_way0_class_match <= tlb_way0_class_match; +tlb_cmp_dbg_way0_extclass_match <= tlb_way0_extclass_match; +tlb_cmp_dbg_way0_state_match <= tlb_way0_state_match; +tlb_cmp_dbg_way0_thdid_match <= tlb_way0_thdid_match; +tlb_cmp_dbg_way0_pid_match <= tlb_way0_pid_match; +tlb_cmp_dbg_way0_lpid_match <= tlb_way0_lpid_match; +tlb_cmp_dbg_way0_ind_match <= tlb_way0_ind_match; +tlb_cmp_dbg_way0_iprot_match <= tlb_way0_iprot_match; +tlb_cmp_dbg_way1_entry_v <= lru_tag3_dataout_q(1); +tlb_cmp_dbg_way1_addr_match <= tlb_way1_addr_match; +tlb_cmp_dbg_way1_pgsize_match <= tlb_way1_pgsize_match; +tlb_cmp_dbg_way1_class_match <= tlb_way1_class_match; +tlb_cmp_dbg_way1_extclass_match <= tlb_way1_extclass_match; +tlb_cmp_dbg_way1_state_match <= tlb_way1_state_match; +tlb_cmp_dbg_way1_thdid_match <= tlb_way1_thdid_match; +tlb_cmp_dbg_way1_pid_match <= tlb_way1_pid_match; +tlb_cmp_dbg_way1_lpid_match <= tlb_way1_lpid_match; +tlb_cmp_dbg_way1_ind_match <= tlb_way1_ind_match; +tlb_cmp_dbg_way1_iprot_match <= tlb_way1_iprot_match; +tlb_cmp_dbg_way2_entry_v <= lru_tag3_dataout_q(2); +tlb_cmp_dbg_way2_addr_match <= tlb_way2_addr_match; +tlb_cmp_dbg_way2_pgsize_match <= tlb_way2_pgsize_match; +tlb_cmp_dbg_way2_class_match <= tlb_way2_class_match; +tlb_cmp_dbg_way2_extclass_match <= tlb_way2_extclass_match; +tlb_cmp_dbg_way2_state_match <= tlb_way2_state_match; +tlb_cmp_dbg_way2_thdid_match <= tlb_way2_thdid_match; +tlb_cmp_dbg_way2_pid_match <= tlb_way2_pid_match; +tlb_cmp_dbg_way2_lpid_match <= tlb_way2_lpid_match; +tlb_cmp_dbg_way2_ind_match <= tlb_way2_ind_match; +tlb_cmp_dbg_way2_iprot_match <= tlb_way2_iprot_match; +tlb_cmp_dbg_way3_entry_v <= lru_tag3_dataout_q(3); +tlb_cmp_dbg_way3_addr_match <= tlb_way3_addr_match; +tlb_cmp_dbg_way3_pgsize_match <= tlb_way3_pgsize_match; +tlb_cmp_dbg_way3_class_match <= tlb_way3_class_match; +tlb_cmp_dbg_way3_extclass_match <= tlb_way3_extclass_match; +tlb_cmp_dbg_way3_state_match <= tlb_way3_state_match; +tlb_cmp_dbg_way3_thdid_match <= tlb_way3_thdid_match; +tlb_cmp_dbg_way3_pid_match <= tlb_way3_pid_match; +tlb_cmp_dbg_way3_lpid_match <= tlb_way3_lpid_match; +tlb_cmp_dbg_way3_ind_match <= tlb_way3_ind_match; +tlb_cmp_dbg_way3_iprot_match <= tlb_way3_iprot_match; +unused_dc(0) <= or_reduce(LCB_DELAY_LCLKR_DC(1 TO 4)); +unused_dc(1) <= or_reduce(LCB_MPW1_DC_B(1 TO 4)); +unused_dc(2) <= PC_FUNC_SL_FORCE; +unused_dc(3) <= PC_FUNC_SL_THOLD_0_B; +unused_dc(4) <= TC_SCAN_DIS_DC_B; +unused_dc(5) <= TC_SCAN_DIAG_DC; +unused_dc(6) <= TC_LBIST_EN_DC; +unused_dc(7) <= TLB_TAG3_CLONE1_Q(70); +unused_dc(8) <= TLB_TAG3_CLONE1_Q(73); +unused_dc(9) <= or_reduce(TLB_TAG3_CLONE1_Q(99 TO 100)); +unused_dc(10) <= or_reduce(TLB_TAG3_CLONE1_Q(104 TO 109)); +unused_dc(11) <= TLB_TAG3_CLONE2_Q(70); +unused_dc(12) <= TLB_TAG3_CLONE2_Q(73); +unused_dc(13) <= or_reduce(TLB_TAG3_CLONE2_Q(99 TO 100)); +unused_dc(14) <= or_reduce(TLB_TAG3_CLONE2_Q(104 TO 109)); +unused_dc(15) <= '0'; +unused_dc(16) <= TLB_TAG3_CMPMASK_Q(4); +unused_dc(17) <= TLB_TAG3_CMPMASK_CLONE_Q(4); +unused_dc(18) <= or_reduce(MMUCR1_CLONE_Q(11) & MMUCR1_CLONE_Q(17)); +unused_dc(19) <= or_reduce(TLB_TAG4_TYPE_SIG(0 TO 3) & TLB_TAG4_TYPE_SIG(5)); +unused_dc(20) <= TLB_TAG4_ESEL_SIG(0); +unused_dc(21) <= or_reduce(TLB_TAG4_WQ_SIG); +unused_dc(22) <= or_reduce(TLB_TAG4_IS_SIG(1 TO 3)); +unused_dc(23) <= or_reduce(PTERELOAD_REQ_PTE_LAT(0 TO 9)); +unused_dc(24) <= or_reduce(PTERELOAD_REQ_PTE_LAT(50) & PTERELOAD_REQ_PTE_LAT(55) & PTERELOAD_REQ_PTE_LAT(62)); +unused_dc(25) <= or_reduce(MMUCR3_0(53) & MMUCR3_0(59)); +unused_dc(26) <= or_reduce(MMUCR3_1(53) & MMUCR3_1(59)); +unused_dc(27) <= or_reduce(MMUCR3_2(53) & MMUCR3_2(59)); +unused_dc(28) <= or_reduce(MMUCR3_3(53) & MMUCR3_3(59)); +unused_dc(29) <= TLB0CFG_PT; +unused_dc(30) <= or_reduce(TLB_DSI_Q); +unused_dc(31) <= or_reduce(TLB_ISI_Q); +unused_dc(32) <= or_reduce(LRAT_TAG3_LPN_SIG); +unused_dc(33) <= or_reduce(LRAT_TAG3_RPN_SIG); +unused_dc(34) <= or_reduce(LRAT_TAG4_LPN_SIG); +unused_dc(35) <= LRAT_TAG3_HIT_STATUS(0); +unused_dc(36) <= LRAT_TAG3_HIT_STATUS(3); +unused_dc(37) <= or_reduce(LRAT_TAG3_HIT_ENTRY); +unused_dc(38) <= or_reduce(LRAT_TAG4_HIT_ENTRY); +tlb_way0_latch: tri_rlmreg_p + generic map (width => tlb_way0_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(12), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_way0_offset to tlb_way0_offset+tlb_way0_q'length-1), + scout => sov_0(tlb_way0_offset to tlb_way0_offset+tlb_way0_q'length-1), + din => tlb_way0_d(0 to tlb_way_width-1), + dout => tlb_way0_q(0 to tlb_way_width-1) ); +tlb_way1_latch: tri_rlmreg_p + generic map (width => tlb_way1_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(12), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_way1_offset to tlb_way1_offset+tlb_way1_q'length-1), + scout => sov_0(tlb_way1_offset to tlb_way1_offset+tlb_way1_q'length-1), + din => tlb_way1_d(0 to tlb_way_width-1), + dout => tlb_way1_q(0 to tlb_way_width-1) ); +tlb_way2_latch: tri_rlmreg_p + generic map (width => tlb_way2_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(13), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(tlb_way2_offset to tlb_way2_offset+tlb_way2_q'length-1), + scout => sov_1(tlb_way2_offset to tlb_way2_offset+tlb_way2_q'length-1), + din => tlb_way2_d(0 to tlb_way_width-1), + dout => tlb_way2_q(0 to tlb_way_width-1) ); +tlb_way3_latch: tri_rlmreg_p + generic map (width => tlb_way3_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(13), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(tlb_way3_offset to tlb_way3_offset+tlb_way3_q'length-1), + scout => sov_1(tlb_way3_offset to tlb_way3_offset+tlb_way3_q'length-1), + din => tlb_way3_d(0 to tlb_way_width-1), + dout => tlb_way3_q(0 to tlb_way_width-1) ); +tlb_tag3_latch: tri_rlmreg_p + generic map (width => tlb_tag3_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(9), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(tlb_tag3_offset to tlb_tag3_offset+tlb_tag3_q'length-1), + scout => sov_2(tlb_tag3_offset to tlb_tag3_offset+tlb_tag3_q'length-1), + din => tlb_tag3_d(0 to tlb_tag_width-1), + dout => tlb_tag3_q(0 to tlb_tag_width-1) ); +tlb_tag3_clone1_latch: tri_rlmreg_p + generic map (width => tlb_tag3_clone1_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(12), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_tag3_clone1_offset to tlb_tag3_clone1_offset+tlb_tag3_clone1_q'length-1), + scout => sov_0(tlb_tag3_clone1_offset to tlb_tag3_clone1_offset+tlb_tag3_clone1_q'length-1), + din => tlb_tag3_clone1_d(0 to tlb_tag_width-1), + dout => tlb_tag3_clone1_q(0 to tlb_tag_width-1) ); +tlb_tag3_clone2_latch: tri_rlmreg_p + generic map (width => tlb_tag3_clone2_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(13), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(tlb_tag3_clone2_offset to tlb_tag3_clone2_offset+tlb_tag3_clone2_q'length-1), + scout => sov_1(tlb_tag3_clone2_offset to tlb_tag3_clone2_offset+tlb_tag3_clone2_q'length-1), + din => tlb_tag3_clone2_d(0 to tlb_tag_width-1), + dout => tlb_tag3_clone2_q(0 to tlb_tag_width-1) ); +tlb_addr3_latch: tri_rlmreg_p + generic map (width => tlb_addr3_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(9), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(tlb_addr3_offset to tlb_addr3_offset+tlb_addr3_q'length-1), + scout => sov_2(tlb_addr3_offset to tlb_addr3_offset+tlb_addr3_q'length-1), + din => tlb_addr3_d(0 to tlb_addr_width-1), + dout => tlb_addr3_q(0 to tlb_addr_width-1) ); +lru_tag3_dataout_latch: tri_rlmreg_p + generic map (width => lru_tag3_dataout_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(9), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(lru_tag3_dataout_offset to lru_tag3_dataout_offset+lru_tag3_dataout_q'length-1), + scout => sov_2(lru_tag3_dataout_offset to lru_tag3_dataout_offset+lru_tag3_dataout_q'length-1), + din => lru_tag3_dataout_d(0 to 15), + dout => lru_tag3_dataout_q(0 to 15) ); +tlb_tag3_cmpmask_latch: tri_rlmreg_p + generic map (width => tlb_tag3_cmpmask_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(12), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_tag3_cmpmask_offset to tlb_tag3_cmpmask_offset+tlb_tag3_cmpmask_q'length-1), + scout => sov_0(tlb_tag3_cmpmask_offset to tlb_tag3_cmpmask_offset+tlb_tag3_cmpmask_q'length-1), + din => tlb_tag3_cmpmask_d, + dout => tlb_tag3_cmpmask_q ); +tlb_tag3_cmpmask_clone_latch: tri_rlmreg_p + generic map (width => tlb_tag3_cmpmask_clone_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(13), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(tlb_tag3_cmpmask_clone_offset to tlb_tag3_cmpmask_clone_offset+tlb_tag3_cmpmask_clone_q'length-1), + scout => sov_1(tlb_tag3_cmpmask_clone_offset to tlb_tag3_cmpmask_clone_offset+tlb_tag3_cmpmask_clone_q'length-1), + din => tlb_tag3_cmpmask_clone_d, + dout => tlb_tag3_cmpmask_clone_q ); +tlb_way0_cmpmask_latch: tri_rlmreg_p + generic map (width => tlb_way0_cmpmask_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(12), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_way0_cmpmask_offset to tlb_way0_cmpmask_offset+tlb_way0_cmpmask_q'length-1), + scout => sov_0(tlb_way0_cmpmask_offset to tlb_way0_cmpmask_offset+tlb_way0_cmpmask_q'length-1), + din => tlb_way0_cmpmask_d, + dout => tlb_way0_cmpmask_q ); +tlb_way1_cmpmask_latch: tri_rlmreg_p + generic map (width => tlb_way1_cmpmask_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(12), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_way1_cmpmask_offset to tlb_way1_cmpmask_offset+tlb_way1_cmpmask_q'length-1), + scout => sov_0(tlb_way1_cmpmask_offset to tlb_way1_cmpmask_offset+tlb_way1_cmpmask_q'length-1), + din => tlb_way1_cmpmask_d, + dout => tlb_way1_cmpmask_q ); +tlb_way2_cmpmask_latch: tri_rlmreg_p + generic map (width => tlb_way2_cmpmask_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(13), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(tlb_way2_cmpmask_offset to tlb_way2_cmpmask_offset+tlb_way2_cmpmask_q'length-1), + scout => sov_1(tlb_way2_cmpmask_offset to tlb_way2_cmpmask_offset+tlb_way2_cmpmask_q'length-1), + din => tlb_way2_cmpmask_d, + dout => tlb_way2_cmpmask_q ); +tlb_way3_cmpmask_latch: tri_rlmreg_p + generic map (width => tlb_way3_cmpmask_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(13), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(tlb_way3_cmpmask_offset to tlb_way3_cmpmask_offset+tlb_way3_cmpmask_q'length-1), + scout => sov_1(tlb_way3_cmpmask_offset to tlb_way3_cmpmask_offset+tlb_way3_cmpmask_q'length-1), + din => tlb_way3_cmpmask_d, + dout => tlb_way3_cmpmask_q ); +tlb_way0_xbitmask_latch: tri_rlmreg_p + generic map (width => tlb_way0_xbitmask_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(12), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_way0_xbitmask_offset to tlb_way0_xbitmask_offset+tlb_way0_xbitmask_q'length-1), + scout => sov_0(tlb_way0_xbitmask_offset to tlb_way0_xbitmask_offset+tlb_way0_xbitmask_q'length-1), + din => tlb_way0_xbitmask_d, + dout => tlb_way0_xbitmask_q ); +tlb_way1_xbitmask_latch: tri_rlmreg_p + generic map (width => tlb_way1_xbitmask_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(12), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_way1_xbitmask_offset to tlb_way1_xbitmask_offset+tlb_way1_xbitmask_q'length-1), + scout => sov_0(tlb_way1_xbitmask_offset to tlb_way1_xbitmask_offset+tlb_way1_xbitmask_q'length-1), + din => tlb_way1_xbitmask_d, + dout => tlb_way1_xbitmask_q ); +tlb_way2_xbitmask_latch: tri_rlmreg_p + generic map (width => tlb_way2_xbitmask_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(13), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(tlb_way2_xbitmask_offset to tlb_way2_xbitmask_offset+tlb_way2_xbitmask_q'length-1), + scout => sov_1(tlb_way2_xbitmask_offset to tlb_way2_xbitmask_offset+tlb_way2_xbitmask_q'length-1), + din => tlb_way2_xbitmask_d, + dout => tlb_way2_xbitmask_q ); +tlb_way3_xbitmask_latch: tri_rlmreg_p + generic map (width => tlb_way3_xbitmask_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(13), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(tlb_way3_xbitmask_offset to tlb_way3_xbitmask_offset+tlb_way3_xbitmask_q'length-1), + scout => sov_1(tlb_way3_xbitmask_offset to tlb_way3_xbitmask_offset+tlb_way3_xbitmask_q'length-1), + din => tlb_way3_xbitmask_d, + dout => tlb_way3_xbitmask_q ); +tlb_tag4_latch: tri_rlmreg_p + generic map (width => tlb_tag4_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(10), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(tlb_tag4_offset to tlb_tag4_offset+tlb_tag4_q'length-1), + scout => sov_2(tlb_tag4_offset to tlb_tag4_offset+tlb_tag4_q'length-1), + din => tlb_tag4_d(0 to tlb_tag_width-1), + dout => tlb_tag4_q(0 to tlb_tag_width-1) ); +tlb_tag4_wayhit_latch: tri_rlmreg_p + generic map (width => tlb_tag4_wayhit_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(10), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(tlb_tag4_wayhit_offset to tlb_tag4_wayhit_offset+tlb_tag4_wayhit_q'length-1), + scout => sov_2(tlb_tag4_wayhit_offset to tlb_tag4_wayhit_offset+tlb_tag4_wayhit_q'length-1), + din => tlb_tag4_wayhit_d(0 to tlb_ways), + dout => tlb_tag4_wayhit_q(0 to tlb_ways) ); +tlb_addr4_latch: tri_rlmreg_p + generic map (width => tlb_addr4_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(10), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(tlb_addr4_offset to tlb_addr4_offset+tlb_addr4_q'length-1), + scout => sov_2(tlb_addr4_offset to tlb_addr4_offset+tlb_addr4_q'length-1), + din => tlb_addr4_d(0 to tlb_addr_width-1), + dout => tlb_addr4_q(0 to tlb_addr_width-1) ); +tlb_dataina_latch: tri_rlmreg_p + generic map (width => tlb_dataina_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(14), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_dataina_offset to tlb_dataina_offset+tlb_dataina_q'length-1), + scout => sov_0(tlb_dataina_offset to tlb_dataina_offset+tlb_dataina_q'length-1), + din => tlb_dataina_d(0 to tlb_way_width-1), + dout => tlb_dataina_q(0 to tlb_way_width-1) ); +tlb_datainb_latch: tri_rlmreg_p + generic map (width => tlb_datainb_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(15), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(tlb_datainb_offset to tlb_datainb_offset+tlb_datainb_q'length-1), + scout => sov_1(tlb_datainb_offset to tlb_datainb_offset+tlb_datainb_q'length-1), + din => tlb_datainb_d(0 to tlb_way_width-1), + dout => tlb_datainb_q(0 to tlb_way_width-1) ); +lru_tag4_dataout_latch: tri_rlmreg_p + generic map (width => lru_tag4_dataout_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(10), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(lru_tag4_dataout_offset to lru_tag4_dataout_offset+lru_tag4_dataout_q'length-1), + scout => sov_2(lru_tag4_dataout_offset to lru_tag4_dataout_offset+lru_tag4_dataout_q'length-1), + din => lru_tag4_dataout_d(0 to 15), + dout => lru_tag4_dataout_q(0 to 15) ); +tlb_tag4_way_latch: tri_rlmreg_p + generic map (width => tlb_tag4_way_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_tag4_way_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_tag4_way_offset to tlb_tag4_way_offset+tlb_tag4_way_q'length-1), + scout => sov_0(tlb_tag4_way_offset to tlb_tag4_way_offset+tlb_tag4_way_q'length-1), + din => tlb_tag4_way_d(0 to tlb_way_width-1), + dout => tlb_tag4_way_q(0 to tlb_way_width-1) ); +tlb_tag4_way_clone_latch: tri_rlmreg_p + generic map (width => tlb_tag4_way_clone_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_tag4_way_clone_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(tlb_tag4_way_clone_offset to tlb_tag4_way_clone_offset+tlb_tag4_way_clone_q'length-1), + scout => sov_1(tlb_tag4_way_clone_offset to tlb_tag4_way_clone_offset+tlb_tag4_way_clone_q'length-1), + din => tlb_tag4_way_clone_d(0 to tlb_way_width-1), + dout => tlb_tag4_way_clone_q(0 to tlb_way_width-1) ); +tlb_tag4_way_rw_latch: tri_rlmreg_p + generic map (width => tlb_tag4_way_rw_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_tag4_way_rw_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_tag4_way_rw_offset to tlb_tag4_way_rw_offset+tlb_tag4_way_rw_q'length-1), + scout => sov_0(tlb_tag4_way_rw_offset to tlb_tag4_way_rw_offset+tlb_tag4_way_rw_q'length-1), + din => tlb_tag4_way_rw_d(0 to tlb_way_width-1), + dout => tlb_tag4_way_rw_q(0 to tlb_way_width-1) ); +tlb_tag4_way_rw_clone_latch: tri_rlmreg_p + generic map (width => tlb_tag4_way_rw_clone_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_tag4_way_rw_clone_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(tlb_tag4_way_rw_clone_offset to tlb_tag4_way_rw_clone_offset+tlb_tag4_way_rw_clone_q'length-1), + scout => sov_1(tlb_tag4_way_rw_clone_offset to tlb_tag4_way_rw_clone_offset+tlb_tag4_way_rw_clone_q'length-1), + din => tlb_tag4_way_rw_clone_d(0 to tlb_way_width-1), + dout => tlb_tag4_way_rw_clone_q(0 to tlb_way_width-1) ); +tlbwe_tag4_back_inv_latch: tri_rlmreg_p + generic map (width => tlbwe_tag4_back_inv_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(10), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(tlbwe_tag4_back_inv_offset to tlbwe_tag4_back_inv_offset+tlbwe_tag4_back_inv_q'length-1), + scout => sov_2(tlbwe_tag4_back_inv_offset to tlbwe_tag4_back_inv_offset+tlbwe_tag4_back_inv_q'length-1), + din => tlbwe_tag4_back_inv_d, + dout => tlbwe_tag4_back_inv_q ); +tlbwe_tag4_back_inv_attr_latch: tri_rlmreg_p + generic map (width => tlbwe_tag4_back_inv_attr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(10), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(tlbwe_tag4_back_inv_attr_offset to tlbwe_tag4_back_inv_attr_offset+tlbwe_tag4_back_inv_attr_q'length-1), + scout => sov_2(tlbwe_tag4_back_inv_attr_offset to tlbwe_tag4_back_inv_attr_offset+tlbwe_tag4_back_inv_attr_q'length-1), + din => tlbwe_tag4_back_inv_attr_d, + dout => tlbwe_tag4_back_inv_attr_q ); +tlb_erat_val_latch: tri_rlmreg_p + generic map (width => tlb_erat_val_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(14), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(tlb_erat_val_offset to tlb_erat_val_offset+tlb_erat_val_q'length-1), + scout => sov_2(tlb_erat_val_offset to tlb_erat_val_offset+tlb_erat_val_q'length-1), + din => tlb_erat_val_d(0 to 2*thdid_width+1), + dout => tlb_erat_val_q(0 to 2*thdid_width+1) ); +tlb_erat_rel_latch: tri_rlmreg_p + generic map (width => tlb_erat_rel_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(14), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_erat_rel_offset to tlb_erat_rel_offset+tlb_erat_rel_q'length-1), + scout => sov_0(tlb_erat_rel_offset to tlb_erat_rel_offset+tlb_erat_rel_q'length-1), + din => tlb_erat_rel_d(0 to erat_rel_data_width-1), + dout => tlb_erat_rel_q(0 to erat_rel_data_width-1) ); +tlb_erat_rel_clone_latch: tri_rlmreg_p + generic map (width => tlb_erat_rel_clone_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(15), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(tlb_erat_rel_clone_offset to tlb_erat_rel_clone_offset+tlb_erat_rel_clone_q'length-1), + scout => sov_1(tlb_erat_rel_clone_offset to tlb_erat_rel_clone_offset+tlb_erat_rel_clone_q'length-1), + din => tlb_erat_rel_clone_d(0 to erat_rel_data_width-1), + dout => tlb_erat_rel_clone_q(0 to erat_rel_data_width-1) ); +tlb_erat_dup_latch: tri_rlmreg_p + generic map (width => tlb_erat_dup_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(tlb_erat_dup_offset to tlb_erat_dup_offset+tlb_erat_dup_q'length-1), + scout => sov_2(tlb_erat_dup_offset to tlb_erat_dup_offset+tlb_erat_dup_q'length-1), + din => tlb_erat_dup_d, + dout => tlb_erat_dup_q ); +lru_write_latch: tri_rlmreg_p + generic map (width => lru_write_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(11), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(lru_write_offset to lru_write_offset+lru_write_q'length-1), + scout => sov_2(lru_write_offset to lru_write_offset+lru_write_q'length-1), + din => lru_write_d(0 to 15), + dout => lru_write_q(0 to 15) ); +lru_wr_addr_latch: tri_rlmreg_p + generic map (width => lru_wr_addr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(11), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(lru_wr_addr_offset to lru_wr_addr_offset+lru_wr_addr_q'length-1), + scout => sov_2(lru_wr_addr_offset to lru_wr_addr_offset+lru_wr_addr_q'length-1), + din => lru_wr_addr_d(0 to tlb_addr_width-1), + dout => lru_wr_addr_q(0 to tlb_addr_width-1) ); +lru_datain_latch: tri_rlmreg_p + generic map (width => lru_datain_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(11), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(lru_datain_offset to lru_datain_offset+lru_datain_q'length-1), + scout => sov_2(lru_datain_offset to lru_datain_offset+lru_datain_q'length-1), + din => lru_datain_d(0 to 15), + dout => lru_datain_q(0 to 15) ); +eratmiss_done_latch: tri_rlmreg_p + generic map (width => eratmiss_done_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(16), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(eratmiss_done_offset to eratmiss_done_offset+eratmiss_done_q'length-1), + scout => sov_2(eratmiss_done_offset to eratmiss_done_offset+eratmiss_done_q'length-1), + din => eratmiss_done_d(0 to thdid_width-1), + dout => eratmiss_done_q(0 to thdid_width-1)); +tlb_miss_latch: tri_rlmreg_p + generic map (width => tlb_miss_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(16), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(tlb_miss_offset to tlb_miss_offset+tlb_miss_q'length-1), + scout => sov_2(tlb_miss_offset to tlb_miss_offset+tlb_miss_q'length-1), + din => tlb_miss_d(0 to thdid_width-1), + dout => tlb_miss_q(0 to thdid_width-1)); +tlb_inelig_latch: tri_rlmreg_p + generic map (width => tlb_inelig_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(16), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(tlb_inelig_offset to tlb_inelig_offset+tlb_inelig_q'length-1), + scout => sov_2(tlb_inelig_offset to tlb_inelig_offset+tlb_inelig_q'length-1), + din => tlb_inelig_d(0 to thdid_width-1), + dout => tlb_inelig_q(0 to thdid_width-1)); +lrat_miss_latch: tri_rlmreg_p + generic map (width => lrat_miss_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(16), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(lrat_miss_offset to lrat_miss_offset+lrat_miss_q'length-1), + scout => sov_2(lrat_miss_offset to lrat_miss_offset+lrat_miss_q'length-1), + din => lrat_miss_d(0 to thdid_width-1), + dout => lrat_miss_q(0 to thdid_width-1)); +pt_fault_latch: tri_rlmreg_p + generic map (width => pt_fault_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(16), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(pt_fault_offset to pt_fault_offset+pt_fault_q'length-1), + scout => sov_2(pt_fault_offset to pt_fault_offset+pt_fault_q'length-1), + din => pt_fault_d(0 to thdid_width-1), + dout => pt_fault_q(0 to thdid_width-1)); +hv_priv_latch: tri_rlmreg_p + generic map (width => hv_priv_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(16), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(hv_priv_offset to hv_priv_offset+hv_priv_q'length-1), + scout => sov_2(hv_priv_offset to hv_priv_offset+hv_priv_q'length-1), + din => hv_priv_d(0 to thdid_width-1), + dout => hv_priv_q(0 to thdid_width-1)); +tlb_tag5_except_latch: tri_rlmreg_p + generic map (width => tlb_tag5_except_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(11), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(tlb_tag5_except_offset to tlb_tag5_except_offset+tlb_tag5_except_q'length-1), + scout => sov_2(tlb_tag5_except_offset to tlb_tag5_except_offset+tlb_tag5_except_q'length-1), + din => tlb_tag5_except_d(0 to thdid_width-1), + dout => tlb_tag5_except_q(0 to thdid_width-1)); +tlb_dsi_latch: tri_rlmreg_p + generic map (width => tlb_dsi_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(16), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(tlb_dsi_offset to tlb_dsi_offset+tlb_dsi_q'length-1), + scout => sov_2(tlb_dsi_offset to tlb_dsi_offset+tlb_dsi_q'length-1), + din => tlb_dsi_d(0 to thdid_width-1), + dout => tlb_dsi_q(0 to thdid_width-1)); +tlb_isi_latch: tri_rlmreg_p + generic map (width => tlb_isi_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(16), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(tlb_isi_offset to tlb_isi_offset+tlb_isi_q'length-1), + scout => sov_2(tlb_isi_offset to tlb_isi_offset+tlb_isi_q'length-1), + din => tlb_isi_d(0 to thdid_width-1), + dout => tlb_isi_q(0 to thdid_width-1)); +esr_pt_latch: tri_rlmreg_p + generic map (width => esr_pt_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(16), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(esr_pt_offset to esr_pt_offset+esr_pt_q'length-1), + scout => sov_2(esr_pt_offset to esr_pt_offset+esr_pt_q'length-1), + din => esr_pt_d(0 to thdid_width-1), + dout => esr_pt_q(0 to thdid_width-1)); +esr_data_latch: tri_rlmreg_p + generic map (width => esr_data_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(16), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(esr_data_offset to esr_data_offset+esr_data_q'length-1), + scout => sov_2(esr_data_offset to esr_data_offset+esr_data_q'length-1), + din => esr_data_d(0 to thdid_width-1), + dout => esr_data_q(0 to thdid_width-1)); +esr_st_latch: tri_rlmreg_p + generic map (width => esr_st_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(16), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(esr_st_offset to esr_st_offset+esr_st_q'length-1), + scout => sov_2(esr_st_offset to esr_st_offset+esr_st_q'length-1), + din => esr_st_d(0 to thdid_width-1), + dout => esr_st_q(0 to thdid_width-1)); +esr_epid_latch: tri_rlmreg_p + generic map (width => esr_epid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(16), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(esr_epid_offset to esr_epid_offset+esr_epid_q'length-1), + scout => sov_2(esr_epid_offset to esr_epid_offset+esr_epid_q'length-1), + din => esr_epid_d(0 to thdid_width-1), + dout => esr_epid_q(0 to thdid_width-1)); +cr0_eq_latch: tri_rlmreg_p + generic map (width => cr0_eq_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(16), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(cr0_eq_offset to cr0_eq_offset+cr0_eq_q'length-1), + scout => sov_2(cr0_eq_offset to cr0_eq_offset+cr0_eq_q'length-1), + din => cr0_eq_d(0 to thdid_width-1), + dout => cr0_eq_q(0 to thdid_width-1)); +cr0_eq_valid_latch: tri_rlmreg_p + generic map (width => cr0_eq_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(16), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(cr0_eq_valid_offset to cr0_eq_valid_offset+cr0_eq_valid_q'length-1), + scout => sov_2(cr0_eq_valid_offset to cr0_eq_valid_offset+cr0_eq_valid_q'length-1), + din => cr0_eq_valid_d(0 to thdid_width-1), + dout => cr0_eq_valid_q(0 to thdid_width-1)); +tlb_multihit_err_latch: tri_rlmreg_p + generic map (width => tlb_multihit_err_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(16), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(tlb_multihit_err_offset to tlb_multihit_err_offset+tlb_multihit_err_q'length-1), + scout => sov_2(tlb_multihit_err_offset to tlb_multihit_err_offset+tlb_multihit_err_q'length-1), + din => tlb_multihit_err_d(0 to thdid_width-1), + dout => tlb_multihit_err_q(0 to thdid_width-1)); +tag4_parerr_latch: tri_rlmreg_p + generic map (width => tag4_parerr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(10), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(tag4_parerr_offset to tag4_parerr_offset+tag4_parerr_q'length-1), + scout => sov_2(tag4_parerr_offset to tag4_parerr_offset+tag4_parerr_q'length-1), + din => tag4_parerr_d, + dout => tag4_parerr_q ); +tlb_par_err_latch: tri_rlmreg_p + generic map (width => tlb_par_err_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(16), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(tlb_par_err_offset to tlb_par_err_offset+tlb_par_err_q'length-1), + scout => sov_2(tlb_par_err_offset to tlb_par_err_offset+tlb_par_err_q'length-1), + din => ECO107332_tlb_par_err_d(0 to thdid_width-1), + dout => tlb_par_err_q(0 to thdid_width-1)); +lru_par_err_latch: tri_rlmreg_p + generic map (width => lru_par_err_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(16), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(lru_par_err_offset to lru_par_err_offset+lru_par_err_q'length-1), + scout => sov_2(lru_par_err_offset to lru_par_err_offset+lru_par_err_q'length-1), + din => ECO107332_lru_par_err_d(0 to thdid_width-1), + dout => lru_par_err_q(0 to thdid_width-1)); +mmucr1_latch: tri_rlmreg_p + generic map (width => mmucr1_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(mmucr1_offset to mmucr1_offset+mmucr1_q'length-1), + scout => sov_0(mmucr1_offset to mmucr1_offset+mmucr1_q'length-1), + din => mmucr1, + dout => mmucr1_q ); +mmucr1_clone_latch: tri_rlmreg_p + generic map (width => mmucr1_clone_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mmucr1_clone_offset to mmucr1_clone_offset+mmucr1_clone_q'length-1), + scout => sov_1(mmucr1_clone_offset to mmucr1_clone_offset+mmucr1_clone_q'length-1), + din => mmucr1, + dout => mmucr1_clone_q ); +spare_a_latch: tri_rlmreg_p + generic map (width => spare_a_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(14), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spare_a_offset to spare_a_offset+spare_a_q'length-1), + scout => sov_0(spare_a_offset to spare_a_offset+spare_a_q'length-1), + din => spare_a_q, + dout => spare_a_q ); +spare_b_latch: tri_rlmreg_p + generic map (width => spare_b_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(15), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spare_b_offset to spare_b_offset+spare_b_q'length-1), + scout => sov_1(spare_b_offset to spare_b_offset+spare_b_q'length-1), + din => spare_b_q, + dout => spare_b_q ); +cswitch_latch: tri_rlmreg_p + generic map (width => cswitch_q'length, init => mmq_tlb_cmp_cswitch_0to7, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(cswitch_offset to cswitch_offset+cswitch_q'length-1), + scout => sov_2(cswitch_offset to cswitch_offset+cswitch_q'length-1), + din => cswitch_q, + dout => cswitch_q ); +spare_c_latch: tri_rlmreg_p + generic map (width => spare_c_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(16), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(spare_c_offset to spare_c_offset+spare_c_q'length-1), + scout => sov_2(spare_c_offset to spare_c_offset+spare_c_q'length-1), + din => spare_c_q, + dout => spare_c_q ); +spare_nsl_latch : tri_regk + generic map (width => spare_nsl_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => xu_mm_ccr2_notlb_b, + forcee => pc_func_slp_nsl_force(0), + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_nsl_thold_0_b(0), + din => spare_nsl_q, + dout => spare_nsl_q); +spare_nsl_clone_latch : tri_regk + generic map (width => spare_nsl_clone_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => xu_mm_ccr2_notlb_b, + forcee => pc_func_slp_nsl_force(1), + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_nsl_thold_0_b(1), + din => spare_nsl_clone_q, + dout => spare_nsl_clone_q); +epcr_dmiuh_latch : tri_regk + generic map (width => epcr_dmiuh_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => xu_mm_ccr2_notlb_b, + forcee => pc_func_slp_nsl_force(0), + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_nsl_thold_0_b(0), + din => xu_mm_spr_epcr_dmiuh, + dout => epcr_dmiuh_q); +msr_gs_latch : tri_regk + generic map (width => msr_gs_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => xu_mm_ccr2_notlb_b, + forcee => pc_func_slp_nsl_force(0), + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_nsl_thold_0_b(0), + din => xu_mm_msr_gs, + dout => msr_gs_q); +msr_pr_latch : tri_regk + generic map (width => msr_pr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => xu_mm_ccr2_notlb_b, + forcee => pc_func_slp_nsl_force(0), + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_nsl_thold_0_b(0), + din => xu_mm_msr_pr, + dout => msr_pr_q); +perv_2to1_reg: tri_plat + generic map (width => 5, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ccflush_dc, + din(0) => pc_func_sl_thold_2, + din(1) => pc_func_slp_sl_thold_2, + din(2) => pc_func_slp_nsl_thold_2, + din(3) => pc_sg_2, + din(4) => pc_fce_2, + q(0) => pc_func_sl_thold_1, + q(1) => pc_func_slp_sl_thold_1, + q(2) => pc_func_slp_nsl_thold_1, + q(3) => pc_sg_1, + q(4) => pc_fce_1); +perv_1to0_reg: tri_plat + generic map (width => 5, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ccflush_dc, + din(0) => pc_func_sl_thold_1, + din(1) => pc_func_slp_sl_thold_1, + din(2) => pc_func_slp_nsl_thold_1, + din(3) => pc_sg_1, + din(4) => pc_fce_1, + q(0) => pc_func_sl_thold_0, + q(1) => pc_func_slp_sl_thold_0, + q(2) => pc_func_slp_nsl_thold_0, + q(3) => pc_sg_0, + q(4) => pc_fce_0); +perv_lcbor_func_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b, + thold => pc_func_sl_thold_0, + sg => pc_sg_0, + act_dis => lcb_act_dis_dc, + forcee => pc_func_sl_force, + thold_b => pc_func_sl_thold_0_b); +perv_lcbor_func_slp_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b, + thold => pc_func_slp_sl_thold_0, + sg => pc_sg_0, + act_dis => lcb_act_dis_dc, + forcee => pc_func_slp_sl_force, + thold_b => pc_func_slp_sl_thold_0_b); +perv_nsl_lcbor: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b, + thold => pc_func_slp_nsl_thold_0, + sg => pc_fce_0, + act_dis => tidn, + forcee => pc_func_slp_nsl_force(0), + thold_b => pc_func_slp_nsl_thold_0_b(0)); +perv_nsl_lcbor_clone: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b, + thold => pc_func_slp_nsl_thold_0, + sg => pc_fce_0, + act_dis => tidn, + forcee => pc_func_slp_nsl_force(1), + thold_b => pc_func_slp_nsl_thold_0_b(1)); +siv_0(0 TO scan_right_0) <= sov_0(1 to scan_right_0) & ac_func_scan_in(0); +ac_func_scan_out(0) <= sov_0(0); +siv_1(0 TO scan_right_1) <= sov_1(1 to scan_right_1) & ac_func_scan_in(1); +ac_func_scan_out(1) <= sov_1(0); +siv_2(0 TO scan_right_2) <= sov_2(1 to scan_right_2) & ac_func_scan_in(2); +ac_func_scan_out(2) <= sov_2(0); +END MMQ_TLB_CMP; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/mmq_tlb_ctl.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/mmq_tlb_ctl.vhdl new file mode 100644 index 0000000..f733f66 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/mmq_tlb_ctl.vhdl @@ -0,0 +1,4274 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; +use ieee.std_logic_1164.all; +library ibm; +use ibm.std_ulogic_unsigned.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_support.all; +library support; +use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity mmq_tlb_ctl is + generic(thdid_width : integer := 4; + ttype_width : integer := 5; + state_width : integer := 4; + pid_width : integer := 14; + lpid_width : integer := 8; + class_width : integer := 2; + extclass_width : integer := 2; + tlbsel_width : integer := 2; + epn_width : integer := 52; + req_epn_width : integer := 52; + vpn_width : integer := 61; + erat_cam_data_width : integer := 75; + erat_ary_data_width : integer := 73; + ws_width : integer := 2; + rs_is_width : integer := 9; + ra_entry_width : integer := 12; + rs_data_width : integer := 64; + data_out_width : integer := 64; + error_width : integer := 3; + tlb_num_entry : natural := 512; + tlb_num_entry_log2 : natural := 9; + tlb_ways : natural := 4; + tlb_addr_width : natural := 7; + tlb_way_width : natural := 168; + tlb_word_width : natural := 84; + tlb_seq_width : integer := 6; + inv_seq_width : integer := 5; + watermark_width : integer := 4; + eptr_width : integer := 4; + lru_width : integer := 26; + mmucr0_width : integer := 20; + mmucr1_width : integer := 32; + mmucr2_width : integer := 32; + mmucr3_width : integer := 15; + spr_ctl_width : integer := 3; + spr_etid_width : integer := 2; + spr_addr_width : integer := 10; + spr_data_width : integer := 64; + debug_trace_width : integer := 88; + debug_event_width : integer := 16; + real_addr_width : integer := 42; + rpn_width : integer := 30; + pte_width : integer := 64; + tlb_tag_width : natural := 110; + expand_type : integer := 2 ); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + +tc_ccflush_dc : in std_ulogic; +tc_scan_dis_dc_b : in std_ulogic; +tc_scan_diag_dc : in std_ulogic; +tc_lbist_en_dc : in std_ulogic; +lcb_d_mode_dc : in std_ulogic; +lcb_clkoff_dc_b : in std_ulogic; +lcb_act_dis_dc : in std_ulogic; +lcb_mpw1_dc_b : in std_ulogic_vector(0 to 4); +lcb_mpw2_dc_b : in std_ulogic; +lcb_delay_lclkr_dc : in std_ulogic_vector(0 to 4); +ac_func_scan_in :in std_ulogic; +ac_func_scan_out :out std_ulogic; +pc_sg_2 : in std_ulogic; +pc_func_sl_thold_2 : in std_ulogic; +pc_func_slp_sl_thold_2 : in std_ulogic; +pc_func_slp_nsl_thold_2 : in std_ulogic; +pc_fce_2 : in std_ulogic; +xu_mm_rf1_val : in std_ulogic_vector(0 to 3); +xu_mm_rf1_is_tlbre : in std_ulogic; +xu_mm_rf1_is_tlbwe : in std_ulogic; +xu_mm_rf1_is_tlbsx : in std_ulogic; +xu_mm_rf1_is_tlbsxr : in std_ulogic; +xu_mm_rf1_is_tlbsrx : in std_ulogic; +xu_mm_ex2_epn : in std_ulogic_vector(64-rs_data_width to 51); +xu_mm_msr_gs : in std_ulogic_vector(0 to thdid_width-1); +xu_mm_msr_pr : in std_ulogic_vector(0 to thdid_width-1); +xu_mm_msr_is : in std_ulogic_vector(0 to thdid_width-1); +xu_mm_msr_ds : in std_ulogic_vector(0 to thdid_width-1); +xu_mm_msr_cm : in std_ulogic_vector(0 to thdid_width-1); +xu_mm_ccr2_notlb_b : in std_ulogic; +xu_mm_epcr_dgtmi : in std_ulogic_vector(0 to thdid_width-1); +xu_mm_xucr4_mmu_mchk : in std_ulogic; +xu_mm_xucr4_mmu_mchk_q : out std_ulogic; +xu_rf1_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_ex1_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_ex2_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_ex3_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_ex4_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_ex5_flush : in std_ulogic_vector(0 to thdid_width-1); +tlb_ctl_ex3_valid : out std_ulogic_vector(0 to thdid_width-1); +tlb_ctl_ex3_ttype : out std_ulogic_vector(0 to ttype_width-1); +tlb_ctl_tag2_flush : out std_ulogic_vector(0 to thdid_width-1); +tlb_ctl_tag3_flush : out std_ulogic_vector(0 to thdid_width-1); +tlb_ctl_tag4_flush : out std_ulogic_vector(0 to thdid_width-1); +tlb_resv_match_vec : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_eratmiss_done : in std_ulogic_vector(0 to thdid_width-1); +mm_xu_tlb_miss : in std_ulogic_vector(0 to thdid_width-1); +mm_xu_tlb_inelig : in std_ulogic_vector(0 to thdid_width-1); +tlb_ctl_barrier_done : out std_ulogic_vector(0 to thdid_width-1); +tlb_ctl_ex2_flush_req : out std_ulogic_vector(0 to thdid_width-1); +tlb_ctl_quiesce : out std_ulogic_vector(0 to thdid_width-1); +tlb_ctl_ex2_illeg_instr : out std_ulogic_vector(0 to thdid_width-1); +ex6_illeg_instr : out std_ulogic_vector(0 to 1); +tlbwe_back_inv_pending : in std_ulogic; +pid0 : in std_ulogic_vector(0 to pid_width-1); +pid1 : in std_ulogic_vector(0 to pid_width-1); +pid2 : in std_ulogic_vector(0 to pid_width-1); +pid3 : in std_ulogic_vector(0 to pid_width-1); +mmucr1_tlbi_msb : in std_ulogic; +mmucr1_tlbwe_binv : in std_ulogic; +mmucr2 : in std_ulogic_vector(0 to mmucr2_width-1); +mmucr3_0 : in std_ulogic_vector(64-mmucr3_width to 63); +mmucr3_1 : in std_ulogic_vector(64-mmucr3_width to 63); +mmucr3_2 : in std_ulogic_vector(64-mmucr3_width to 63); +mmucr3_3 : in std_ulogic_vector(64-mmucr3_width to 63); +lpidr : in std_ulogic_vector(0 to lpid_width-1); +mmucfg_lrat : in std_ulogic; +mmucfg_twc : in std_ulogic; +tlb0cfg_pt : in std_ulogic; +tlb0cfg_ind : in std_ulogic; +tlb0cfg_gtwe : in std_ulogic; +mmucsr0_tlb0fi : in std_ulogic; +mas0_0_atsel : in std_ulogic; +mas0_0_esel : in std_ulogic_vector(0 to 2); +mas0_0_hes : in std_ulogic; +mas0_0_wq : in std_ulogic_vector(0 to 1); +mas1_0_v : in std_ulogic; +mas1_0_iprot : in std_ulogic; +mas1_0_tid : in std_ulogic_vector(0 to 13); +mas1_0_ind : in std_ulogic; +mas1_0_ts : in std_ulogic; +mas1_0_tsize : in std_ulogic_vector(0 to 3); +mas2_0_epn : in std_ulogic_vector(0 to 51); +mas2_0_wimge : in std_ulogic_vector(0 to 4); +mas3_0_usxwr : in std_ulogic_vector(0 to 3); +mas5_0_sgs : in std_ulogic; +mas5_0_slpid : in std_ulogic_vector(0 to 7); +mas6_0_spid : in std_ulogic_vector(0 to 13); +mas6_0_sind : in std_ulogic; +mas6_0_sas : in std_ulogic; +mas8_0_tgs : in std_ulogic; +mas8_0_tlpid : in std_ulogic_vector(0 to 7); +mas0_1_atsel : in std_ulogic; +mas0_1_esel : in std_ulogic_vector(0 to 2); +mas0_1_hes : in std_ulogic; +mas0_1_wq : in std_ulogic_vector(0 to 1); +mas1_1_v : in std_ulogic; +mas1_1_iprot : in std_ulogic; +mas1_1_tid : in std_ulogic_vector(0 to 13); +mas1_1_ind : in std_ulogic; +mas1_1_ts : in std_ulogic; +mas1_1_tsize : in std_ulogic_vector(0 to 3); +mas2_1_epn : in std_ulogic_vector(0 to 51); +mas2_1_wimge : in std_ulogic_vector(0 to 4); +mas3_1_usxwr : in std_ulogic_vector(0 to 3); +mas5_1_sgs : in std_ulogic; +mas5_1_slpid : in std_ulogic_vector(0 to 7); +mas6_1_spid : in std_ulogic_vector(0 to 13); +mas6_1_sind : in std_ulogic; +mas6_1_sas : in std_ulogic; +mas8_1_tgs : in std_ulogic; +mas8_1_tlpid : in std_ulogic_vector(0 to 7); +mas0_2_atsel : in std_ulogic; +mas0_2_esel : in std_ulogic_vector(0 to 2); +mas0_2_hes : in std_ulogic; +mas0_2_wq : in std_ulogic_vector(0 to 1); +mas1_2_v : in std_ulogic; +mas1_2_iprot : in std_ulogic; +mas1_2_tid : in std_ulogic_vector(0 to 13); +mas1_2_ind : in std_ulogic; +mas1_2_ts : in std_ulogic; +mas1_2_tsize : in std_ulogic_vector(0 to 3); +mas2_2_epn : in std_ulogic_vector(0 to 51); +mas2_2_wimge : in std_ulogic_vector(0 to 4); +mas3_2_usxwr : in std_ulogic_vector(0 to 3); +mas5_2_sgs : in std_ulogic; +mas5_2_slpid : in std_ulogic_vector(0 to 7); +mas6_2_spid : in std_ulogic_vector(0 to 13); +mas6_2_sind : in std_ulogic; +mas6_2_sas : in std_ulogic; +mas8_2_tgs : in std_ulogic; +mas8_2_tlpid : in std_ulogic_vector(0 to 7); +mas0_3_atsel : in std_ulogic; +mas0_3_esel : in std_ulogic_vector(0 to 2); +mas0_3_hes : in std_ulogic; +mas0_3_wq : in std_ulogic_vector(0 to 1); +mas1_3_v : in std_ulogic; +mas1_3_iprot : in std_ulogic; +mas1_3_tid : in std_ulogic_vector(0 to 13); +mas1_3_ind : in std_ulogic; +mas1_3_ts : in std_ulogic; +mas1_3_tsize : in std_ulogic_vector(0 to 3); +mas2_3_epn : in std_ulogic_vector(0 to 51); +mas2_3_wimge : in std_ulogic_vector(0 to 4); +mas3_3_usxwr : in std_ulogic_vector(0 to 3); +mas5_3_sgs : in std_ulogic; +mas5_3_slpid : in std_ulogic_vector(0 to 7); +mas6_3_spid : in std_ulogic_vector(0 to 13); +mas6_3_sind : in std_ulogic; +mas6_3_sas : in std_ulogic; +mas8_3_tgs : in std_ulogic; +mas8_3_tlpid : in std_ulogic_vector(0 to 7); +tlb_seq_ierat_req : in std_ulogic; +tlb_seq_derat_req : in std_ulogic; +tlb_seq_ierat_done : out std_ulogic; +tlb_seq_derat_done : out std_ulogic; +tlb_seq_idle : out std_ulogic; +ierat_req_taken : out std_ulogic; +derat_req_taken : out std_ulogic; +ierat_req_epn : in std_ulogic_vector(0 to req_epn_width-1); +ierat_req_pid : in std_ulogic_vector(0 to pid_width-1); +ierat_req_state : in std_ulogic_vector(0 to state_width-1); +ierat_req_thdid : in std_ulogic_vector(0 to thdid_width-1); +ierat_req_dup : in std_ulogic_vector(0 to 1); +derat_req_epn : in std_ulogic_vector(0 to req_epn_width-1); +derat_req_pid : in std_ulogic_vector(0 to pid_width-1); +derat_req_lpid : in std_ulogic_vector(0 to lpid_width-1); +derat_req_state : in std_ulogic_vector(0 to state_width-1); +derat_req_ttype : in std_ulogic_vector(0 to 1); +derat_req_thdid : in std_ulogic_vector(0 to thdid_width-1); +derat_req_dup : in std_ulogic_vector(0 to 1); +ptereload_req_valid : in std_ulogic; +ptereload_req_tag : in std_ulogic_vector(0 to tlb_tag_width-1); +ptereload_req_pte : in std_ulogic_vector(0 to pte_width-1); +ptereload_req_taken : out std_ulogic; +tlb_snoop_coming : in std_ulogic; +tlb_snoop_val : in std_ulogic; +tlb_snoop_attr : in std_ulogic_vector(0 to 34); +tlb_snoop_vpn : in std_ulogic_vector(52-epn_width to 51); +tlb_snoop_ack : out std_ulogic; +lru_rd_addr : out std_ulogic_vector(0 to tlb_addr_width-1); +lru_tag4_dataout : in std_ulogic_vector(0 to 15); +tlb_tag4_esel : in std_ulogic_vector(0 to 2); +tlb_tag4_wq : in std_ulogic_vector(0 to 1); +tlb_tag4_is : in std_ulogic_vector(0 to 1); +tlb_tag4_gs : in std_ulogic; +tlb_tag4_pr : in std_ulogic; +tlb_tag4_hes : in std_ulogic; +tlb_tag4_atsel : in std_ulogic; +tlb_tag4_pt : in std_ulogic; +tlb_tag4_cmp_hit : in std_ulogic; +tlb_tag4_way_ind : in std_ulogic; +tlb_tag4_ptereload : in std_ulogic; +tlb_tag4_endflag : in std_ulogic; +tlb_tag4_parerr : in std_ulogic; +tlb_tag5_except : in std_ulogic_vector(0 to thdid_width-1); +tlb_cmp_erat_dup_wait : in std_ulogic_vector(0 to 1); +tlb_tag0_epn : out std_ulogic_vector(52-epn_width to 51); +tlb_tag0_thdid : out std_ulogic_vector(0 to thdid_width-1); +tlb_tag0_type : out std_ulogic_vector(0 to 7); +tlb_tag0_lpid : out std_ulogic_vector(0 to lpid_width-1); +tlb_tag0_atsel : out std_ulogic; +tlb_tag0_size : out std_ulogic_vector(0 to 3); +tlb_tag0_addr_cap : out std_ulogic; +tlb_tag2 : out std_ulogic_vector(0 to tlb_tag_width-1); +tlb_addr2 : out std_ulogic_vector(0 to tlb_addr_width-1); +tlb_ctl_perf_tlbwec_resv : out std_ulogic; +tlb_ctl_perf_tlbwec_noresv : out std_ulogic; +lrat_tag4_hit_status : in std_ulogic_vector(0 to 3); +tlb_lper_lpn : out std_ulogic_vector(64-real_addr_width to 51); +tlb_lper_lps : out std_ulogic_vector(60 to 63); +tlb_lper_we : out std_ulogic_vector(0 to thdid_width-1); +ptereload_req_pte_lat : out std_ulogic_vector(0 to pte_width-1); +pte_tag0_lpn : out std_ulogic_vector(64-real_addr_width to 51); +pte_tag0_lpid : out std_ulogic_vector(0 to lpid_width-1); +tlb_write : out std_ulogic_vector(0 to tlb_ways-1); +tlb_addr : out std_ulogic_vector(0 to tlb_addr_width-1); +tlb_tag5_write : out std_ulogic; +tlb_delayed_act : out std_ulogic_vector(9 to 32); +tlb_ctl_dbg_seq_q : out std_ulogic_vector(0 to 5); +tlb_ctl_dbg_seq_idle : out std_ulogic; +tlb_ctl_dbg_seq_any_done_sig : out std_ulogic; +tlb_ctl_dbg_seq_abort : out std_ulogic; +tlb_ctl_dbg_any_tlb_req_sig : out std_ulogic; +tlb_ctl_dbg_any_req_taken_sig : out std_ulogic; +tlb_ctl_dbg_tag5_tlb_write_q : out std_ulogic_vector(0 to 3); +tlb_ctl_dbg_tag0_valid : out std_ulogic; +tlb_ctl_dbg_tag0_thdid : out std_ulogic_vector(0 to 1); +tlb_ctl_dbg_tag0_type : out std_ulogic_vector(0 to 2); +tlb_ctl_dbg_tag0_wq : out std_ulogic_vector(0 to 1); +tlb_ctl_dbg_tag0_gs : out std_ulogic; +tlb_ctl_dbg_tag0_pr : out std_ulogic; +tlb_ctl_dbg_tag0_atsel : out std_ulogic; +tlb_ctl_dbg_resv_valid : out std_ulogic_vector(0 to 3); +tlb_ctl_dbg_set_resv : out std_ulogic_vector(0 to 3); +tlb_ctl_dbg_resv_match_vec_q : out std_ulogic_vector(0 to 3); +tlb_ctl_dbg_any_tag_flush_sig : out std_ulogic; +tlb_ctl_dbg_resv0_tag0_lpid_match : out std_ulogic; +tlb_ctl_dbg_resv0_tag0_pid_match : out std_ulogic; +tlb_ctl_dbg_resv0_tag0_as_snoop_match : out std_ulogic; +tlb_ctl_dbg_resv0_tag0_gs_snoop_match : out std_ulogic; +tlb_ctl_dbg_resv0_tag0_as_tlbwe_match : out std_ulogic; +tlb_ctl_dbg_resv0_tag0_gs_tlbwe_match : out std_ulogic; +tlb_ctl_dbg_resv0_tag0_ind_match : out std_ulogic; +tlb_ctl_dbg_resv0_tag0_epn_loc_match : out std_ulogic; +tlb_ctl_dbg_resv0_tag0_epn_glob_match : out std_ulogic; +tlb_ctl_dbg_resv0_tag0_class_match : out std_ulogic; +tlb_ctl_dbg_resv1_tag0_lpid_match : out std_ulogic; +tlb_ctl_dbg_resv1_tag0_pid_match : out std_ulogic; +tlb_ctl_dbg_resv1_tag0_as_snoop_match : out std_ulogic; +tlb_ctl_dbg_resv1_tag0_gs_snoop_match : out std_ulogic; +tlb_ctl_dbg_resv1_tag0_as_tlbwe_match : out std_ulogic; +tlb_ctl_dbg_resv1_tag0_gs_tlbwe_match : out std_ulogic; +tlb_ctl_dbg_resv1_tag0_ind_match : out std_ulogic; +tlb_ctl_dbg_resv1_tag0_epn_loc_match : out std_ulogic; +tlb_ctl_dbg_resv1_tag0_epn_glob_match : out std_ulogic; +tlb_ctl_dbg_resv1_tag0_class_match : out std_ulogic; +tlb_ctl_dbg_resv2_tag0_lpid_match : out std_ulogic; +tlb_ctl_dbg_resv2_tag0_pid_match : out std_ulogic; +tlb_ctl_dbg_resv2_tag0_as_snoop_match : out std_ulogic; +tlb_ctl_dbg_resv2_tag0_gs_snoop_match : out std_ulogic; +tlb_ctl_dbg_resv2_tag0_as_tlbwe_match : out std_ulogic; +tlb_ctl_dbg_resv2_tag0_gs_tlbwe_match : out std_ulogic; +tlb_ctl_dbg_resv2_tag0_ind_match : out std_ulogic; +tlb_ctl_dbg_resv2_tag0_epn_loc_match : out std_ulogic; +tlb_ctl_dbg_resv2_tag0_epn_glob_match : out std_ulogic; +tlb_ctl_dbg_resv2_tag0_class_match : out std_ulogic; +tlb_ctl_dbg_resv3_tag0_lpid_match : out std_ulogic; +tlb_ctl_dbg_resv3_tag0_pid_match : out std_ulogic; +tlb_ctl_dbg_resv3_tag0_as_snoop_match : out std_ulogic; +tlb_ctl_dbg_resv3_tag0_gs_snoop_match : out std_ulogic; +tlb_ctl_dbg_resv3_tag0_as_tlbwe_match : out std_ulogic; +tlb_ctl_dbg_resv3_tag0_gs_tlbwe_match : out std_ulogic; +tlb_ctl_dbg_resv3_tag0_ind_match : out std_ulogic; +tlb_ctl_dbg_resv3_tag0_epn_loc_match : out std_ulogic; +tlb_ctl_dbg_resv3_tag0_epn_glob_match : out std_ulogic; +tlb_ctl_dbg_resv3_tag0_class_match : out std_ulogic; +tlb_ctl_dbg_clr_resv_q : out std_ulogic_vector(0 to 3); +tlb_ctl_dbg_clr_resv_terms : out std_ulogic_vector(0 to 3) +); +end mmq_tlb_ctl; +ARCHITECTURE MMQ_TLB_CTL + OF MMQ_TLB_CTL + IS +constant MMU_Mode_Value : std_ulogic := '0'; +constant TlbSel_Tlb : std_ulogic_vector(0 to 1) := "00"; +constant TlbSel_IErat : std_ulogic_vector(0 to 1) := "10"; +constant TlbSel_DErat : std_ulogic_vector(0 to 1) := "11"; +constant ERAT_PgSize_1GB : std_ulogic_vector(0 to 2) := "110"; +constant ERAT_PgSize_16MB : std_ulogic_vector(0 to 2) := "111"; +constant ERAT_PgSize_1MB : std_ulogic_vector(0 to 2) := "101"; +constant ERAT_PgSize_64KB : std_ulogic_vector(0 to 2) := "011"; +constant ERAT_PgSize_4KB : std_ulogic_vector(0 to 2) := "001"; +constant TLB_PgSize_1GB : std_ulogic_vector(0 to 3) := "1010"; +constant TLB_PgSize_16MB : std_ulogic_vector(0 to 3) := "0111"; +constant TLB_PgSize_1MB : std_ulogic_vector(0 to 3) := "0101"; +constant TLB_PgSize_64KB : std_ulogic_vector(0 to 3) := "0011"; +constant TLB_PgSize_4KB : std_ulogic_vector(0 to 3) := "0001"; +constant ERAT_PgSize_256MB : std_ulogic_vector(0 to 2) := "100"; +constant TLB_PgSize_256MB : std_ulogic_vector(0 to 3) := "1001"; +constant LRAT_PgSize_1TB : std_ulogic_vector(0 to 3) := "1111"; +constant LRAT_PgSize_256GB : std_ulogic_vector(0 to 3) := "1110"; +constant LRAT_PgSize_16GB : std_ulogic_vector(0 to 3) := "1100"; +constant LRAT_PgSize_4GB : std_ulogic_vector(0 to 3) := "1011"; +constant LRAT_PgSize_1GB : std_ulogic_vector(0 to 3) := "1010"; +constant LRAT_PgSize_256MB : std_ulogic_vector(0 to 3) := "1001"; +constant LRAT_PgSize_16MB : std_ulogic_vector(0 to 3) := "0111"; +constant LRAT_PgSize_1MB : std_ulogic_vector(0 to 3) := "0101"; +constant TlbSeq_Idle : std_ulogic_vector(0 to 5) := "000000"; +constant TlbSeq_Stg1 : std_ulogic_vector(0 to 5) := "000001"; +constant TlbSeq_Stg2 : std_ulogic_vector(0 to 5) := "000011"; +constant TlbSeq_Stg3 : std_ulogic_vector(0 to 5) := "000010"; +constant TlbSeq_Stg4 : std_ulogic_vector(0 to 5) := "000110"; +constant TlbSeq_Stg5 : std_ulogic_vector(0 to 5) := "000100"; +constant TlbSeq_Stg6 : std_ulogic_vector(0 to 5) := "000101"; +constant TlbSeq_Stg7 : std_ulogic_vector(0 to 5) := "000111"; +constant TlbSeq_Stg8 : std_ulogic_vector(0 to 5) := "001000"; +constant TlbSeq_Stg9 : std_ulogic_vector(0 to 5) := "001001"; +constant TlbSeq_Stg10 : std_ulogic_vector(0 to 5) := "001011"; +constant TlbSeq_Stg11 : std_ulogic_vector(0 to 5) := "001010"; +constant TlbSeq_Stg12 : std_ulogic_vector(0 to 5) := "001110"; +constant TlbSeq_Stg13 : std_ulogic_vector(0 to 5) := "001100"; +constant TlbSeq_Stg14 : std_ulogic_vector(0 to 5) := "001101"; +constant TlbSeq_Stg15 : std_ulogic_vector(0 to 5) := "001111"; +constant TlbSeq_Stg16 : std_ulogic_vector(0 to 5) := "010000"; +constant TlbSeq_Stg17 : std_ulogic_vector(0 to 5) := "010001"; +constant TlbSeq_Stg18 : std_ulogic_vector(0 to 5) := "010011"; +constant TlbSeq_Stg19 : std_ulogic_vector(0 to 5) := "010010"; +constant TlbSeq_Stg20 : std_ulogic_vector(0 to 5) := "010110"; +constant TlbSeq_Stg21 : std_ulogic_vector(0 to 5) := "010100"; +constant TlbSeq_Stg22 : std_ulogic_vector(0 to 5) := "010101"; +constant TlbSeq_Stg23 : std_ulogic_vector(0 to 5) := "010111"; +constant TlbSeq_Stg24 : std_ulogic_vector(0 to 5) := "011000"; +constant TlbSeq_Stg25 : std_ulogic_vector(0 to 5) := "011001"; +constant TlbSeq_Stg26 : std_ulogic_vector(0 to 5) := "011011"; +constant TlbSeq_Stg27 : std_ulogic_vector(0 to 5) := "011010"; +constant TlbSeq_Stg28 : std_ulogic_vector(0 to 5) := "011110"; +constant TlbSeq_Stg29 : std_ulogic_vector(0 to 5) := "011100"; +constant TlbSeq_Stg30 : std_ulogic_vector(0 to 5) := "011101"; +constant TlbSeq_Stg31 : std_ulogic_vector(0 to 5) := "011111"; +constant TlbSeq_Stg32 : std_ulogic_vector(0 to 5) := "100000"; +constant tagpos_epn : natural := 0; +constant tagpos_pid : natural := 52; +constant tagpos_is : natural := 66; +constant tagpos_class : natural := 68; +constant tagpos_state : natural := 70; +constant tagpos_thdid : natural := 74; +constant tagpos_size : natural := 78; +constant tagpos_type : natural := 82; +constant tagpos_lpid : natural := 90; +constant tagpos_ind : natural := 98; +constant tagpos_atsel : natural := 99; +constant tagpos_esel : natural := 100; +constant tagpos_hes : natural := 103; +constant tagpos_wq : natural := 104; +constant tagpos_lrat : natural := 106; +constant tagpos_pt : natural := 107; +constant tagpos_recform : natural := 108; +constant tagpos_endflag : natural := 109; +constant tagpos_type_derat : natural := tagpos_type; +constant tagpos_type_ierat : natural := tagpos_type+1; +constant tagpos_type_tlbsx : natural := tagpos_type+2; +constant tagpos_type_tlbsrx : natural := tagpos_type+3; +constant tagpos_type_snoop : natural := tagpos_type+4; +constant tagpos_type_tlbre : natural := tagpos_type+5; +constant tagpos_type_tlbwe : natural := tagpos_type+6; +constant tagpos_type_ptereload : natural := tagpos_type+7; +constant tagpos_pr : natural := tagpos_state; +constant tagpos_gs : natural := tagpos_state+1; +constant tagpos_as : natural := tagpos_state+2; +constant tagpos_cm : natural := tagpos_state+3; +constant waypos_epn : natural := 0; +constant waypos_size : natural := 52; +constant waypos_thdid : natural := 56; +constant waypos_class : natural := 60; +constant waypos_extclass : natural := 62; +constant waypos_lpid : natural := 66; +constant waypos_xbit : natural := 84; +constant waypos_rpn : natural := 88; +constant waypos_rc : natural := 118; +constant waypos_wlc : natural := 120; +constant waypos_resvattr : natural := 122; +constant waypos_vf : natural := 123; +constant waypos_ind : natural := 124; +constant waypos_ubits : natural := 125; +constant waypos_wimge : natural := 129; +constant waypos_usxwr : natural := 134; +constant waypos_gs : natural := 140; +constant waypos_ts : natural := 141; +constant waypos_tid : natural := 144; +constant ptepos_rpn : natural := 0; +constant ptepos_wimge : natural := 40; +constant ptepos_r : natural := 45; +constant ptepos_ubits : natural := 46; +constant ptepos_sw0 : natural := 50; +constant ptepos_c : natural := 51; +constant ptepos_size : natural := 52; +constant ptepos_usxwr : natural := 56; +constant ptepos_sw1 : natural := 62; +constant ptepos_valid : natural := 63; +constant xu_ex1_flush_offset : natural := 0; +constant ex1_valid_offset : natural := xu_ex1_flush_offset + thdid_width; +constant ex1_ttype_offset : natural := ex1_valid_offset + thdid_width; +constant ex1_state_offset : natural := ex1_ttype_offset + ttype_width; +constant ex1_pid_offset : natural := ex1_state_offset + state_width+1; +constant ex2_valid_offset : natural := ex1_pid_offset + pid_width; +constant ex2_flush_offset : natural := ex2_valid_offset + thdid_width; +constant ex2_flush_req_offset : natural := ex2_flush_offset + thdid_width; +constant ex2_ttype_offset : natural := ex2_flush_req_offset + thdid_width; +constant ex2_state_offset : natural := ex2_ttype_offset + ttype_width; +constant ex2_pid_offset : natural := ex2_state_offset + state_width+1; +constant ex3_valid_offset : natural := ex2_pid_offset + pid_width; +constant ex3_flush_offset : natural := ex3_valid_offset + thdid_width; +constant ex3_ttype_offset : natural := ex3_flush_offset + thdid_width; +constant ex3_state_offset : natural := ex3_ttype_offset + ttype_width; +constant ex3_pid_offset : natural := ex3_state_offset + state_width+1; +constant ex4_valid_offset : natural := ex3_pid_offset + pid_width; +constant ex4_flush_offset : natural := ex4_valid_offset + thdid_width; +constant ex4_ttype_offset : natural := ex4_flush_offset + thdid_width; +constant ex4_state_offset : natural := ex4_ttype_offset + ttype_width; +constant ex4_pid_offset : natural := ex4_state_offset + state_width+1; +constant ex5_valid_offset : natural := ex4_pid_offset + pid_width; +constant ex5_flush_offset : natural := ex5_valid_offset + thdid_width; +constant ex5_ttype_offset : natural := ex5_flush_offset + thdid_width; +constant ex5_state_offset : natural := ex5_ttype_offset + ttype_width; +constant ex5_pid_offset : natural := ex5_state_offset + state_width+1; +constant ex6_valid_offset : natural := ex5_pid_offset + pid_width; +constant ex6_flush_offset : natural := ex6_valid_offset + thdid_width; +constant ex6_ttype_offset : natural := ex6_flush_offset + thdid_width; +constant ex6_state_offset : natural := ex6_ttype_offset + ttype_width; +constant ex6_pid_offset : natural := ex6_state_offset + state_width+1; +constant tlb_addr_offset : natural := ex6_pid_offset + pid_width; +constant tlb_addr2_offset : natural := tlb_addr_offset + tlb_addr_width; +constant tlb_write_offset : natural := tlb_addr2_offset + tlb_addr_width; +constant tlb_tag0_offset : natural := tlb_write_offset + tlb_ways; +constant tlb_tag1_offset : natural := tlb_tag0_offset + tlb_tag_width; +constant tlb_tag2_offset : natural := tlb_tag1_offset + tlb_tag_width; +constant tlb_seq_offset : natural := tlb_tag2_offset + tlb_tag_width; +constant derat_taken_offset : natural := tlb_seq_offset + tlb_seq_width; +constant xucr4_mmu_mchk_offset : natural := derat_taken_offset + 1; +constant ex6_illeg_instr_offset : natural := xucr4_mmu_mchk_offset + 1; +constant snoop_val_offset : natural := ex6_illeg_instr_offset + 2; +constant snoop_attr_offset : natural := snoop_val_offset + 2; +constant snoop_vpn_offset : natural := snoop_attr_offset + 35; +constant tlb_clr_resv_offset : natural := snoop_vpn_offset + epn_width; +constant tlb_resv_match_vec_offset : natural := tlb_clr_resv_offset + thdid_width; +constant tlb_resv0_valid_offset : natural := tlb_resv_match_vec_offset + thdid_width; +constant tlb_resv0_epn_offset : natural := tlb_resv0_valid_offset + 1; +constant tlb_resv0_pid_offset : natural := tlb_resv0_epn_offset + epn_width; +constant tlb_resv0_lpid_offset : natural := tlb_resv0_pid_offset + pid_width; +constant tlb_resv0_as_offset : natural := tlb_resv0_lpid_offset + lpid_width; +constant tlb_resv0_gs_offset : natural := tlb_resv0_as_offset + 1; +constant tlb_resv0_ind_offset : natural := tlb_resv0_gs_offset + 1; +constant tlb_resv0_class_offset : natural := tlb_resv0_ind_offset + 1; +constant tlb_resv1_valid_offset : natural := tlb_resv0_class_offset + class_width; +constant tlb_resv1_epn_offset : natural := tlb_resv1_valid_offset + 1; +constant tlb_resv1_pid_offset : natural := tlb_resv1_epn_offset + epn_width; +constant tlb_resv1_lpid_offset : natural := tlb_resv1_pid_offset + pid_width; +constant tlb_resv1_as_offset : natural := tlb_resv1_lpid_offset + lpid_width; +constant tlb_resv1_gs_offset : natural := tlb_resv1_as_offset + 1; +constant tlb_resv1_ind_offset : natural := tlb_resv1_gs_offset + 1; +constant tlb_resv1_class_offset : natural := tlb_resv1_ind_offset + 1; +constant tlb_resv2_valid_offset : natural := tlb_resv1_class_offset + class_width; +constant tlb_resv2_epn_offset : natural := tlb_resv2_valid_offset + 1; +constant tlb_resv2_pid_offset : natural := tlb_resv2_epn_offset + epn_width; +constant tlb_resv2_lpid_offset : natural := tlb_resv2_pid_offset + pid_width; +constant tlb_resv2_as_offset : natural := tlb_resv2_lpid_offset + lpid_width; +constant tlb_resv2_gs_offset : natural := tlb_resv2_as_offset + 1; +constant tlb_resv2_ind_offset : natural := tlb_resv2_gs_offset + 1; +constant tlb_resv2_class_offset : natural := tlb_resv2_ind_offset + 1; +constant tlb_resv3_valid_offset : natural := tlb_resv2_class_offset + class_width; +constant tlb_resv3_epn_offset : natural := tlb_resv3_valid_offset + 1; +constant tlb_resv3_pid_offset : natural := tlb_resv3_epn_offset + epn_width; +constant tlb_resv3_lpid_offset : natural := tlb_resv3_pid_offset + pid_width; +constant tlb_resv3_as_offset : natural := tlb_resv3_lpid_offset + lpid_width; +constant tlb_resv3_gs_offset : natural := tlb_resv3_as_offset + 1; +constant tlb_resv3_ind_offset : natural := tlb_resv3_gs_offset + 1; +constant tlb_resv3_class_offset : natural := tlb_resv3_ind_offset + 1; +constant ptereload_req_pte_offset : natural := tlb_resv3_class_offset + class_width; +constant tlb_delayed_act_offset : natural := ptereload_req_pte_offset + pte_width; +constant tlb_ctl_spare_offset : natural := tlb_delayed_act_offset + 33; +constant scan_right : natural := tlb_ctl_spare_offset + 32 -1; +signal xu_ex1_flush_d, xu_ex1_flush_q : std_ulogic_vector(0 to thdid_width-1); +signal ex1_valid_d, ex1_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal ex1_ttype_d, ex1_ttype_q : std_ulogic_vector(0 to ttype_width-1); +signal ex1_state_d, ex1_state_q : std_ulogic_vector(0 to state_width); +signal ex1_pid_d, ex1_pid_q : std_ulogic_vector(0 to pid_width-1); +signal ex2_valid_d, ex2_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal ex2_flush_d, ex2_flush_q : std_ulogic_vector(0 to thdid_width-1); +signal ex2_flush_req_d, ex2_flush_req_q : std_ulogic_vector(0 to thdid_width-1); +signal ex2_ttype_d, ex2_ttype_q : std_ulogic_vector(0 to ttype_width-1); +signal ex2_state_d, ex2_state_q : std_ulogic_vector(0 to state_width); +signal ex2_pid_d, ex2_pid_q : std_ulogic_vector(0 to pid_width-1); +signal ex3_valid_d, ex3_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal ex3_flush_d, ex3_flush_q : std_ulogic_vector(0 to thdid_width-1); +signal ex3_ttype_d, ex3_ttype_q : std_ulogic_vector(0 to ttype_width-1); +signal ex3_state_d, ex3_state_q : std_ulogic_vector(0 to state_width); +signal ex3_pid_d, ex3_pid_q : std_ulogic_vector(0 to pid_width-1); +signal ex4_valid_d, ex4_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal ex4_flush_d, ex4_flush_q : std_ulogic_vector(0 to thdid_width-1); +signal ex4_ttype_d, ex4_ttype_q : std_ulogic_vector(0 to ttype_width-1); +signal ex4_state_d, ex4_state_q : std_ulogic_vector(0 to state_width); +signal ex4_pid_d, ex4_pid_q : std_ulogic_vector(0 to pid_width-1); +signal ex5_valid_d, ex5_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal ex5_flush_d, ex5_flush_q : std_ulogic_vector(0 to thdid_width-1); +signal ex5_ttype_d, ex5_ttype_q : std_ulogic_vector(0 to ttype_width-1); +signal ex5_state_d, ex5_state_q : std_ulogic_vector(0 to state_width); +signal ex5_pid_d, ex5_pid_q : std_ulogic_vector(0 to pid_width-1); +signal ex6_valid_d, ex6_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal ex6_flush_d, ex6_flush_q : std_ulogic_vector(0 to thdid_width-1); +signal ex6_ttype_d, ex6_ttype_q : std_ulogic_vector(0 to ttype_width-1); +signal ex6_state_d, ex6_state_q : std_ulogic_vector(0 to state_width); +signal ex6_pid_d, ex6_pid_q : std_ulogic_vector(0 to pid_width-1); +signal tlb_tag0_d, tlb_tag0_q : std_ulogic_vector(0 to tlb_tag_width-1); +signal tlb_tag1_d, tlb_tag1_q : std_ulogic_vector(0 to tlb_tag_width-1); +signal tlb_tag2_d, tlb_tag2_q : std_ulogic_vector(0 to tlb_tag_width-1); +signal tlb_addr_d, tlb_addr_q : std_ulogic_vector(0 to tlb_addr_width-1); +signal tlb_addr2_d, tlb_addr2_q : std_ulogic_vector(0 to tlb_addr_width-1); +signal tlb_write_d, tlb_write_q : std_ulogic_vector(0 to tlb_ways-1); +signal tlb_seq_d, tlb_seq_q : std_ulogic_vector(0 to 5); +signal derat_taken_d, derat_taken_q : std_ulogic; +signal ex6_illeg_instr_d, ex6_illeg_instr_q : std_ulogic_vector(0 to 1); +signal snoop_val_d, snoop_val_q : std_ulogic_vector(0 to 1); +signal snoop_attr_d, snoop_attr_q : std_ulogic_vector(0 to 34); +signal snoop_vpn_d,snoop_vpn_q : std_ulogic_vector(52-epn_width to 51); +signal tlb_resv0_valid_d, tlb_resv0_valid_q : std_ulogic; +signal tlb_resv0_epn_d, tlb_resv0_epn_q : std_ulogic_vector(52-epn_width to 51); +signal tlb_resv0_pid_d, tlb_resv0_pid_q : std_ulogic_vector(0 to pid_width-1); +signal tlb_resv0_lpid_d, tlb_resv0_lpid_q : std_ulogic_vector(0 to lpid_width-1); +signal tlb_resv0_as_d, tlb_resv0_as_q : std_ulogic; +signal tlb_resv0_gs_d, tlb_resv0_gs_q : std_ulogic; +signal tlb_resv0_ind_d, tlb_resv0_ind_q : std_ulogic; +signal tlb_resv0_class_d, tlb_resv0_class_q : std_ulogic_vector(0 to class_width-1); +signal tlb_resv1_valid_d, tlb_resv1_valid_q : std_ulogic; +signal tlb_resv1_epn_d, tlb_resv1_epn_q : std_ulogic_vector(52-epn_width to 51); +signal tlb_resv1_pid_d, tlb_resv1_pid_q : std_ulogic_vector(0 to pid_width-1); +signal tlb_resv1_lpid_d, tlb_resv1_lpid_q : std_ulogic_vector(0 to lpid_width-1); +signal tlb_resv1_as_d, tlb_resv1_as_q : std_ulogic; +signal tlb_resv1_gs_d, tlb_resv1_gs_q : std_ulogic; +signal tlb_resv1_ind_d, tlb_resv1_ind_q : std_ulogic; +signal tlb_resv1_class_d, tlb_resv1_class_q : std_ulogic_vector(0 to class_width-1); +signal tlb_resv2_valid_d, tlb_resv2_valid_q : std_ulogic; +signal tlb_resv2_epn_d, tlb_resv2_epn_q : std_ulogic_vector(52-epn_width to 51); +signal tlb_resv2_pid_d, tlb_resv2_pid_q : std_ulogic_vector(0 to pid_width-1); +signal tlb_resv2_lpid_d, tlb_resv2_lpid_q : std_ulogic_vector(0 to lpid_width-1); +signal tlb_resv2_as_d, tlb_resv2_as_q : std_ulogic; +signal tlb_resv2_gs_d, tlb_resv2_gs_q : std_ulogic; +signal tlb_resv2_ind_d, tlb_resv2_ind_q : std_ulogic; +signal tlb_resv2_class_d, tlb_resv2_class_q : std_ulogic_vector(0 to class_width-1); +signal tlb_resv3_valid_d, tlb_resv3_valid_q : std_ulogic; +signal tlb_resv3_epn_d, tlb_resv3_epn_q : std_ulogic_vector(52-epn_width to 51); +signal tlb_resv3_pid_d, tlb_resv3_pid_q : std_ulogic_vector(0 to pid_width-1); +signal tlb_resv3_lpid_d, tlb_resv3_lpid_q : std_ulogic_vector(0 to lpid_width-1); +signal tlb_resv3_as_d, tlb_resv3_as_q : std_ulogic; +signal tlb_resv3_gs_d, tlb_resv3_gs_q : std_ulogic; +signal tlb_resv3_ind_d, tlb_resv3_ind_q : std_ulogic; +signal tlb_resv3_class_d, tlb_resv3_class_q : std_ulogic_vector(0 to class_width-1); +signal ptereload_req_pte_d, ptereload_req_pte_q : std_ulogic_vector(0 to pte_width-1); +signal tlb_clr_resv_d, tlb_clr_resv_q : std_ulogic_vector(0 to thdid_width-1); +signal tlb_resv_match_vec_d, tlb_resv_match_vec_q : std_ulogic_vector(0 to thdid_width-1); +signal tlb_delayed_act_d, tlb_delayed_act_q : std_ulogic_vector(0 to 32); +signal tlb_ctl_spare_q : std_ulogic_vector(0 to 31); +signal tlb_seq_next : std_ulogic_vector(0 to 5); +signal tlb_resv0_tag0_lpid_match : std_ulogic; +signal tlb_resv0_tag0_pid_match : std_ulogic; +signal tlb_resv0_tag0_as_snoop_match : std_ulogic; +signal tlb_resv0_tag0_gs_snoop_match : std_ulogic; +signal tlb_resv0_tag0_as_tlbwe_match : std_ulogic; +signal tlb_resv0_tag0_gs_tlbwe_match : std_ulogic; +signal tlb_resv0_tag0_ind_match : std_ulogic; +signal tlb_resv0_tag0_epn_loc_match : std_ulogic; +signal tlb_resv0_tag0_epn_glob_match : std_ulogic; +signal tlb_resv0_tag0_class_match : std_ulogic; +signal tlb_resv1_tag0_lpid_match : std_ulogic; +signal tlb_resv1_tag0_pid_match : std_ulogic; +signal tlb_resv1_tag0_as_snoop_match : std_ulogic; +signal tlb_resv1_tag0_gs_snoop_match : std_ulogic; +signal tlb_resv1_tag0_as_tlbwe_match : std_ulogic; +signal tlb_resv1_tag0_gs_tlbwe_match : std_ulogic; +signal tlb_resv1_tag0_ind_match : std_ulogic; +signal tlb_resv1_tag0_epn_loc_match : std_ulogic; +signal tlb_resv1_tag0_epn_glob_match : std_ulogic; +signal tlb_resv1_tag0_class_match : std_ulogic; +signal tlb_resv2_tag0_lpid_match : std_ulogic; +signal tlb_resv2_tag0_pid_match : std_ulogic; +signal tlb_resv2_tag0_as_snoop_match : std_ulogic; +signal tlb_resv2_tag0_gs_snoop_match : std_ulogic; +signal tlb_resv2_tag0_as_tlbwe_match : std_ulogic; +signal tlb_resv2_tag0_gs_tlbwe_match : std_ulogic; +signal tlb_resv2_tag0_ind_match : std_ulogic; +signal tlb_resv2_tag0_epn_loc_match : std_ulogic; +signal tlb_resv2_tag0_epn_glob_match : std_ulogic; +signal tlb_resv2_tag0_class_match : std_ulogic; +signal tlb_resv3_tag0_lpid_match : std_ulogic; +signal tlb_resv3_tag0_pid_match : std_ulogic; +signal tlb_resv3_tag0_as_snoop_match : std_ulogic; +signal tlb_resv3_tag0_gs_snoop_match : std_ulogic; +signal tlb_resv3_tag0_as_tlbwe_match : std_ulogic; +signal tlb_resv3_tag0_gs_tlbwe_match : std_ulogic; +signal tlb_resv3_tag0_ind_match : std_ulogic; +signal tlb_resv3_tag0_epn_loc_match : std_ulogic; +signal tlb_resv3_tag0_epn_glob_match : std_ulogic; +signal tlb_resv3_tag0_class_match : std_ulogic; +signal tlb_resv0_tag1_lpid_match : std_ulogic; +signal tlb_resv0_tag1_pid_match : std_ulogic; +signal tlb_resv0_tag1_as_snoop_match : std_ulogic; +signal tlb_resv0_tag1_gs_snoop_match : std_ulogic; +signal tlb_resv0_tag1_as_tlbwe_match : std_ulogic; +signal tlb_resv0_tag1_gs_tlbwe_match : std_ulogic; +signal tlb_resv0_tag1_ind_match : std_ulogic; +signal tlb_resv0_tag1_epn_loc_match : std_ulogic; +signal tlb_resv0_tag1_epn_glob_match : std_ulogic; +signal tlb_resv0_tag1_class_match : std_ulogic; +signal tlb_resv1_tag1_lpid_match : std_ulogic; +signal tlb_resv1_tag1_pid_match : std_ulogic; +signal tlb_resv1_tag1_as_snoop_match : std_ulogic; +signal tlb_resv1_tag1_gs_snoop_match : std_ulogic; +signal tlb_resv1_tag1_as_tlbwe_match : std_ulogic; +signal tlb_resv1_tag1_gs_tlbwe_match : std_ulogic; +signal tlb_resv1_tag1_ind_match : std_ulogic; +signal tlb_resv1_tag1_epn_loc_match : std_ulogic; +signal tlb_resv1_tag1_epn_glob_match : std_ulogic; +signal tlb_resv1_tag1_class_match : std_ulogic; +signal tlb_resv2_tag1_lpid_match : std_ulogic; +signal tlb_resv2_tag1_pid_match : std_ulogic; +signal tlb_resv2_tag1_as_snoop_match : std_ulogic; +signal tlb_resv2_tag1_gs_snoop_match : std_ulogic; +signal tlb_resv2_tag1_as_tlbwe_match : std_ulogic; +signal tlb_resv2_tag1_gs_tlbwe_match : std_ulogic; +signal tlb_resv2_tag1_ind_match : std_ulogic; +signal tlb_resv2_tag1_epn_loc_match : std_ulogic; +signal tlb_resv2_tag1_epn_glob_match : std_ulogic; +signal tlb_resv2_tag1_class_match : std_ulogic; +signal tlb_resv3_tag1_lpid_match : std_ulogic; +signal tlb_resv3_tag1_pid_match : std_ulogic; +signal tlb_resv3_tag1_as_snoop_match : std_ulogic; +signal tlb_resv3_tag1_gs_snoop_match : std_ulogic; +signal tlb_resv3_tag1_as_tlbwe_match : std_ulogic; +signal tlb_resv3_tag1_gs_tlbwe_match : std_ulogic; +signal tlb_resv3_tag1_ind_match : std_ulogic; +signal tlb_resv3_tag1_epn_loc_match : std_ulogic; +signal tlb_resv3_tag1_epn_glob_match : std_ulogic; +signal tlb_resv3_tag1_class_match : std_ulogic; +signal tlb_resv_valid_vec : std_ulogic_vector(0 to thdid_width-1); +signal tlb_seq_set_resv : std_ulogic; +signal tlb_seq_snoop_resv : std_ulogic; +signal tlb_seq_snoop_resv_q : std_ulogic_vector(0 to thdid_width-1); +signal tlb_hashed_addr1 : std_ulogic_vector(0 to tlb_addr_width-1); +signal tlb_hashed_addr2 : std_ulogic_vector(0 to tlb_addr_width-1); +signal tlb_hashed_addr3 : std_ulogic_vector(0 to tlb_addr_width-1); +signal tlb_hashed_addr4 : std_ulogic_vector(0 to tlb_addr_width-1); +signal tlb_hashed_addr5 : std_ulogic_vector(0 to tlb_addr_width-1); +signal tlb_hashed_tid0_addr1 : std_ulogic_vector(0 to tlb_addr_width-1); +signal tlb_hashed_tid0_addr2 : std_ulogic_vector(0 to tlb_addr_width-1); +signal tlb_hashed_tid0_addr3 : std_ulogic_vector(0 to tlb_addr_width-1); +signal tlb_hashed_tid0_addr4 : std_ulogic_vector(0 to tlb_addr_width-1); +signal tlb_hashed_tid0_addr5 : std_ulogic_vector(0 to tlb_addr_width-1); +signal tlb_tag0_hashed_addr : std_ulogic_vector(0 to tlb_addr_width-1); +signal tlb_tag0_hashed_tid0_addr : std_ulogic_vector(0 to tlb_addr_width-1); +signal tlb_tag0_tid_notzero : std_ulogic; +signal size_4K_hashed_addr : std_ulogic_vector(0 to tlb_addr_width-1); +signal size_64K_hashed_addr : std_ulogic_vector(0 to tlb_addr_width-1); +signal size_1M_hashed_addr : std_ulogic_vector(0 to tlb_addr_width-1); +signal size_16M_hashed_addr : std_ulogic_vector(0 to tlb_addr_width-1); +signal size_1G_hashed_addr : std_ulogic_vector(0 to tlb_addr_width-1); +signal size_4K_hashed_tid0_addr : std_ulogic_vector(0 to tlb_addr_width-1); +signal size_64K_hashed_tid0_addr : std_ulogic_vector(0 to tlb_addr_width-1); +signal size_1M_hashed_tid0_addr : std_ulogic_vector(0 to tlb_addr_width-1); +signal size_16M_hashed_tid0_addr : std_ulogic_vector(0 to tlb_addr_width-1); +signal size_1G_hashed_tid0_addr : std_ulogic_vector(0 to tlb_addr_width-1); +signal size_256M_hashed_addr : std_ulogic_vector(0 to tlb_addr_width-1); +signal size_256M_hashed_tid0_addr : std_ulogic_vector(0 to tlb_addr_width-1); +signal tlb_seq_pgsize : std_ulogic_vector(0 to 3); +signal tlb_seq_addr : std_ulogic_vector(0 to tlb_addr_width-1); +signal tlb_seq_esel : std_ulogic_vector(0 to 2); +signal tlb_seq_is : std_ulogic_vector(0 to 1); +signal tlb_addr_p1 : std_ulogic_vector(0 to tlb_addr_width-1); +signal tlb_addr_maxcntm1 : std_ulogic; +signal tlb_seq_addr_incr : std_ulogic; +signal tlb_seq_addr_clr : std_ulogic; +signal tlb_seq_tag0_addr_cap : std_ulogic; +signal tlb_seq_addr_update : std_ulogic; +signal tlb_seq_lrat_enable : std_ulogic; +signal tlb_seq_idle_sig : std_ulogic; +signal tlb_seq_ind : std_ulogic; +signal tlb_seq_ierat_done_sig : std_ulogic; +signal tlb_seq_derat_done_sig : std_ulogic; +signal tlb_seq_snoop_done_sig : std_ulogic; +signal tlb_seq_search_done_sig : std_ulogic; +signal tlb_seq_searchresv_done_sig : std_ulogic; +signal tlb_seq_read_done_sig : std_ulogic; +signal tlb_seq_write_done_sig : std_ulogic; +signal tlb_seq_ptereload_done_sig : std_ulogic; +signal tlb_seq_any_done_sig : std_ulogic; +signal tlb_seq_endflag : std_ulogic; +signal tlb_search_req : std_ulogic; +signal tlb_searchresv_req : std_ulogic; +signal tlb_read_req : std_ulogic; +signal tlb_write_req : std_ulogic; +signal tlb_set_resv0 : std_ulogic; +-- synopsys translate_off +-- synopsys translate_on +signal tlb_set_resv1 : std_ulogic; +-- synopsys translate_off +-- synopsys translate_on +signal tlb_set_resv2 : std_ulogic; +-- synopsys translate_off +-- synopsys translate_on +signal tlb_set_resv3 : std_ulogic; +-- synopsys translate_off +-- synopsys translate_on +signal any_tlb_req_sig : std_ulogic; +signal any_req_taken_sig : std_ulogic; +signal ierat_req_taken_sig : std_ulogic; +signal derat_req_taken_sig : std_ulogic; +signal snoop_req_taken_sig : std_ulogic; +signal search_req_taken_sig : std_ulogic; +signal searchresv_req_taken_sig : std_ulogic; +signal read_req_taken_sig : std_ulogic; +signal write_req_taken_sig : std_ulogic; +signal ptereload_req_taken_sig : std_ulogic; +signal ex3_valid_32b : std_ulogic; +-- synopsys translate_off +-- synopsys translate_on +signal ex1_mas0_atsel : std_ulogic; +signal ex1_mas0_esel : std_ulogic_vector(0 to 2); +signal ex1_mas0_hes : std_ulogic; +signal ex1_mas0_wq : std_ulogic_vector(0 to 1); +signal ex1_mas1_v : std_ulogic; +signal ex1_mas1_iprot : std_ulogic; +signal ex1_mas1_ind : std_ulogic; +signal ex1_mas1_tid : std_ulogic_vector(0 to pid_width-1); +signal ex1_mas1_ts : std_ulogic; +signal ex1_mas1_tsize : std_ulogic_vector(0 to 3); +signal ex1_mas2_epn : std_ulogic_vector(52-epn_width to 51); +signal ex1_mas8_tgs : std_ulogic; +signal ex1_mas8_tlpid : std_ulogic_vector(0 to lpid_width-1); +signal ex1_mmucr3_class : std_ulogic_vector(0 to class_width-1); +signal ex2_mas0_atsel : std_ulogic; +signal ex2_mas0_esel : std_ulogic_vector(0 to 2); +signal ex2_mas0_hes : std_ulogic; +signal ex2_mas0_wq : std_ulogic_vector(0 to 1); +signal ex2_mas1_ind : std_ulogic; +signal ex2_mas1_tid : std_ulogic_vector(0 to pid_width-1); +signal ex2_mas5_slpid : std_ulogic_vector(0 to lpid_width-1); +signal ex2_mas5_1_state : std_ulogic_vector(0 to state_width-1); +signal ex2_mas5_6_state : std_ulogic_vector(0 to state_width-1); +signal ex2_mas6_sind : std_ulogic; +signal ex2_mas6_spid : std_ulogic_vector(0 to pid_width-1); +signal ex2_hv_state : std_ulogic; +signal ex6_hv_state : std_ulogic; +signal ex6_priv_state : std_ulogic; +signal ex6_dgtmi_state : std_ulogic; +signal tlb_ctl_tag1_flush_sig : std_ulogic_vector(0 to thdid_width-1); +signal tlb_ctl_tag2_flush_sig : std_ulogic_vector(0 to thdid_width-1); +signal tlb_ctl_tag3_flush_sig : std_ulogic_vector(0 to thdid_width-1); +signal tlb_ctl_tag4_flush_sig : std_ulogic_vector(0 to thdid_width-1); +signal tlb_ctl_any_tag_flush_sig : std_ulogic; +signal tlb_seq_abort : std_ulogic; +signal tlb_tag4_hit_or_parerr : std_ulogic; +signal tlb_ctl_quiesce_b : std_ulogic_vector(0 to thdid_width-1); +signal ex2_flush_req_local : std_ulogic_vector(0 to thdid_width-1); +signal tlbwe_back_inv_holdoff : std_ulogic; +signal pgsize1_valid : std_ulogic; +signal pgsize2_valid : std_ulogic; +signal pgsize3_valid : std_ulogic; +signal pgsize4_valid : std_ulogic; +signal pgsize5_valid : std_ulogic; +signal pgsize1_tid0_valid : std_ulogic; +signal pgsize2_tid0_valid : std_ulogic; +signal pgsize3_tid0_valid : std_ulogic; +signal pgsize4_tid0_valid : std_ulogic; +signal pgsize5_tid0_valid : std_ulogic; +signal pgsize_qty : std_ulogic_vector(0 to 2); +signal pgsize_tid0_qty : std_ulogic_vector(0 to 2); +signal tlb_tag1_pgsize_eq_16mb : std_ulogic; +signal tlb_tag1_pgsize_gte_1mb : std_ulogic; +signal tlb_tag1_pgsize_gte_64kb : std_ulogic; +signal mas1_tsize_direct : std_ulogic_vector(0 to thdid_width-1); +signal mas1_tsize_indirect : std_ulogic_vector(0 to thdid_width-1); +signal mas1_tsize_lrat : std_ulogic_vector(0 to thdid_width-1); +signal mas3_spsize_indirect : std_ulogic_vector(0 to thdid_width-1); +signal ex2_tlbre_mas1_tsize_not_supp : std_ulogic_vector(0 to thdid_width-1); +signal ex5_tlbre_mas1_tsize_not_supp : std_ulogic_vector(0 to thdid_width-1); +signal ex5_tlbwe_mas1_tsize_not_supp : std_ulogic_vector(0 to thdid_width-1); +signal ex6_tlbwe_mas1_tsize_not_supp : std_ulogic_vector(0 to thdid_width-1); +signal ex5_tlbwe_mas0_lrat_bad_selects : std_ulogic_vector(0 to thdid_width-1); +signal ex6_tlbwe_mas0_lrat_bad_selects : std_ulogic_vector(0 to thdid_width-1); +signal ex5_tlbwe_mas2_ind_bad_wimge : std_ulogic_vector(0 to thdid_width-1); +signal ex6_tlbwe_mas2_ind_bad_wimge : std_ulogic_vector(0 to thdid_width-1); +signal ex5_tlbwe_mas3_ind_bad_spsize : std_ulogic_vector(0 to thdid_width-1); +signal ex6_tlbwe_mas3_ind_bad_spsize : std_ulogic_vector(0 to thdid_width-1); +-- synopsys translate_off +-- synopsys translate_on +signal tlb_early_act : std_ulogic; +signal tlb_tag0_act : std_ulogic; +signal tlb_snoop_act : std_ulogic; +signal unused_dc : std_ulogic_vector(0 to 35); +-- synopsys translate_off +-- synopsys translate_on +signal pc_sg_1 : std_ulogic; +signal pc_sg_0 : std_ulogic; +signal pc_fce_1 : std_ulogic; +signal pc_fce_0 : std_ulogic; +signal pc_func_sl_thold_1 : std_ulogic; +signal pc_func_sl_thold_0 : std_ulogic; +signal pc_func_sl_thold_0_b : std_ulogic; +signal pc_func_slp_sl_thold_1 : std_ulogic; +signal pc_func_slp_sl_thold_0 : std_ulogic; +signal pc_func_slp_sl_thold_0_b : std_ulogic; +signal pc_func_sl_force : std_ulogic; +signal pc_func_slp_sl_force : std_ulogic; +signal pc_func_slp_nsl_thold_1 : std_ulogic; +signal pc_func_slp_nsl_thold_0 : std_ulogic; +signal pc_func_slp_nsl_thold_0_b : std_ulogic; +signal pc_func_slp_nsl_force : std_ulogic; +signal siv : std_ulogic_vector(0 to scan_right); +signal sov : std_ulogic_vector(0 to scan_right); +signal tidn : std_ulogic; +signal tiup : std_ulogic; + BEGIN + +tidn <= '0'; +tiup <= '1'; +tlb_ctl_quiesce_b(0 TO thdid_width-1) <= + ( (0 to thdid_width-1 => or_reduce(tlb_seq_q)) and tlb_tag0_q(tagpos_thdid to tagpos_thdid+thdid_width-1) ); +tlb_ctl_quiesce <= not tlb_ctl_quiesce_b; +xu_ex1_flush_d <= xu_rf1_flush; +ex1_valid_d <= xu_mm_rf1_val and not(xu_rf1_flush); +ex1_ttype_d <= xu_mm_rf1_is_tlbre & xu_mm_rf1_is_tlbwe & xu_mm_rf1_is_tlbsx & xu_mm_rf1_is_tlbsxr & xu_mm_rf1_is_tlbsrx; +ex1_state_d(0) <= or_reduce(xu_mm_msr_pr and xu_mm_rf1_val); +ex1_state_d(1) <= or_reduce(xu_mm_msr_gs and xu_mm_rf1_val); +ex1_state_d(2) <= or_reduce(xu_mm_msr_ds and xu_mm_rf1_val); +ex1_state_d(3) <= or_reduce(xu_mm_msr_cm and xu_mm_rf1_val); +ex1_state_d(4) <= or_reduce(xu_mm_msr_is and xu_mm_rf1_val); +ex1_pid_d <= (pid0 and (0 to pid_width-1 => xu_mm_rf1_val(0))) + or (pid1 and (0 to pid_width-1 => xu_mm_rf1_val(1))) + or (pid2 and (0 to pid_width-1 => xu_mm_rf1_val(2))) + or (pid3 and (0 to pid_width-1 => xu_mm_rf1_val(3))); +ex1_mas0_atsel <= (mas0_0_atsel and ex1_valid_q(0)) + or (mas0_1_atsel and ex1_valid_q(1)) + or (mas0_2_atsel and ex1_valid_q(2)) + or (mas0_3_atsel and ex1_valid_q(3)); +ex1_mas0_esel <= (mas0_0_esel and (0 to 2 => ex1_valid_q(0))) + or (mas0_1_esel and (0 to 2 => ex1_valid_q(1))) + or (mas0_2_esel and (0 to 2 => ex1_valid_q(2))) + or (mas0_3_esel and (0 to 2 => ex1_valid_q(3))); +ex1_mas0_hes <= (mas0_0_hes and ex1_valid_q(0)) + or (mas0_1_hes and ex1_valid_q(1)) + or (mas0_2_hes and ex1_valid_q(2)) + or (mas0_3_hes and ex1_valid_q(3)); +ex1_mas0_wq <= (mas0_0_wq and (0 to 1 => ex1_valid_q(0))) + or (mas0_1_wq and (0 to 1 => ex1_valid_q(1))) + or (mas0_2_wq and (0 to 1 => ex1_valid_q(2))) + or (mas0_3_wq and (0 to 1 => ex1_valid_q(3))); +ex1_mas1_tid <= (mas1_0_tid and (0 to pid_width-1 => ex1_valid_q(0))) + or (mas1_1_tid and (0 to pid_width-1 => ex1_valid_q(1))) + or (mas1_2_tid and (0 to pid_width-1 => ex1_valid_q(2))) + or (mas1_3_tid and (0 to pid_width-1 => ex1_valid_q(3))); +ex1_mas1_ts <= (mas1_0_ts and ex1_valid_q(0)) + or (mas1_1_ts and ex1_valid_q(1)) + or (mas1_2_ts and ex1_valid_q(2)) + or (mas1_3_ts and ex1_valid_q(3)); +ex1_mas1_tsize <= (mas1_0_tsize and (0 to 3 => ex1_valid_q(0))) + or (mas1_1_tsize and (0 to 3 => ex1_valid_q(1))) + or (mas1_2_tsize and (0 to 3 => ex1_valid_q(2))) + or (mas1_3_tsize and (0 to 3 => ex1_valid_q(3))); +ex1_mas1_ind <= (mas1_0_ind and ex1_valid_q(0)) + or (mas1_1_ind and ex1_valid_q(1)) + or (mas1_2_ind and ex1_valid_q(2)) + or (mas1_3_ind and ex1_valid_q(3)); +ex1_mas1_v <= (mas1_0_v and ex1_valid_q(0)) + or (mas1_1_v and ex1_valid_q(1)) + or (mas1_2_v and ex1_valid_q(2)) + or (mas1_3_v and ex1_valid_q(3)); +ex1_mas1_iprot <= (mas1_0_iprot and ex1_valid_q(0)) + or (mas1_1_iprot and ex1_valid_q(1)) + or (mas1_2_iprot and ex1_valid_q(2)) + or (mas1_3_iprot and ex1_valid_q(3)); +ex1_mas2_epn <= (mas2_0_epn(52-epn_width to 51) and (52-epn_width to 51 => ex1_valid_q(0))) + or (mas2_1_epn(52-epn_width to 51) and (52-epn_width to 51 => ex1_valid_q(1))) + or (mas2_2_epn(52-epn_width to 51) and (52-epn_width to 51 => ex1_valid_q(2))) + or (mas2_3_epn(52-epn_width to 51) and (52-epn_width to 51 => ex1_valid_q(3))); +ex1_mas8_tgs <= (mas8_0_tgs and ex1_valid_q(0)) + or (mas8_1_tgs and ex1_valid_q(1)) + or (mas8_2_tgs and ex1_valid_q(2)) + or (mas8_3_tgs and ex1_valid_q(3)); +ex1_mas8_tlpid <= (mas8_0_tlpid and (0 to lpid_width-1 => ex1_valid_q(0))) + or (mas8_1_tlpid and (0 to lpid_width-1 => ex1_valid_q(1))) + or (mas8_2_tlpid and (0 to lpid_width-1 => ex1_valid_q(2))) + or (mas8_3_tlpid and (0 to lpid_width-1 => ex1_valid_q(3))); +ex1_mmucr3_class <= (mmucr3_0(54 to 55) and (54 to 55 => ex1_valid_q(0))) + or (mmucr3_1(54 to 55) and (54 to 55 => ex1_valid_q(1))) + or (mmucr3_2(54 to 55) and (54 to 55 => ex1_valid_q(2))) + or (mmucr3_3(54 to 55) and (54 to 55 => ex1_valid_q(3))); +ex2_mas0_atsel <= (mas0_0_atsel and ex2_valid_q(0)) + or (mas0_1_atsel and ex2_valid_q(1)) + or (mas0_2_atsel and ex2_valid_q(2)) + or (mas0_3_atsel and ex2_valid_q(3)); +ex2_mas0_esel <= (mas0_0_esel and (0 to 2 => ex2_valid_q(0))) + or (mas0_1_esel and (0 to 2 => ex2_valid_q(1))) + or (mas0_2_esel and (0 to 2 => ex2_valid_q(2))) + or (mas0_3_esel and (0 to 2 => ex2_valid_q(3))); +ex2_mas0_hes <= (mas0_0_hes and ex2_valid_q(0)) + or (mas0_1_hes and ex2_valid_q(1)) + or (mas0_2_hes and ex2_valid_q(2)) + or (mas0_3_hes and ex2_valid_q(3)); +ex2_mas0_wq <= (mas0_0_wq and (0 to 1 => ex2_valid_q(0))) + or (mas0_1_wq and (0 to 1 => ex2_valid_q(1))) + or (mas0_2_wq and (0 to 1 => ex2_valid_q(2))) + or (mas0_3_wq and (0 to 1 => ex2_valid_q(3))); +ex2_mas1_ind <= (mas1_0_ind and ex2_valid_q(0)) + or (mas1_1_ind and ex2_valid_q(1)) + or (mas1_2_ind and ex2_valid_q(2)) + or (mas1_3_ind and ex2_valid_q(3)); +ex2_mas1_tid <= (mas1_0_tid and (0 to pid_width-1 => ex2_valid_q(0))) + or (mas1_1_tid and (0 to pid_width-1 => ex2_valid_q(1))) + or (mas1_2_tid and (0 to pid_width-1 => ex2_valid_q(2))) + or (mas1_3_tid and (0 to pid_width-1 => ex2_valid_q(3))); +ex2_mas5_1_state <= ((ex2_state_q(0) & mas5_0_sgs & mas1_0_ts & ex2_state_q(3)) and (0 to 3 => ex2_valid_q(0))) + or ((ex2_state_q(0) & mas5_1_sgs & mas1_1_ts & ex2_state_q(3)) and (0 to 3 => ex2_valid_q(1))) + or ((ex2_state_q(0) & mas5_2_sgs & mas1_2_ts & ex2_state_q(3)) and (0 to 3 => ex2_valid_q(2))) + or ((ex2_state_q(0) & mas5_3_sgs & mas1_3_ts & ex2_state_q(3)) and (0 to 3 => ex2_valid_q(3))); +ex2_mas5_6_state <= ((ex2_state_q(0) & mas5_0_sgs & mas6_0_sas & ex2_state_q(3)) and (0 to 3 => ex2_valid_q(0))) + or ((ex2_state_q(0) & mas5_1_sgs & mas6_1_sas & ex2_state_q(3)) and (0 to 3 => ex2_valid_q(1))) + or ((ex2_state_q(0) & mas5_2_sgs & mas6_2_sas & ex2_state_q(3)) and (0 to 3 => ex2_valid_q(2))) + or ((ex2_state_q(0) & mas5_3_sgs & mas6_3_sas & ex2_state_q(3)) and (0 to 3 => ex2_valid_q(3))); +ex2_mas5_slpid <= (mas5_0_slpid and (0 to lpid_width-1 => ex2_valid_q(0))) + or (mas5_1_slpid and (0 to lpid_width-1 => ex2_valid_q(1))) + or (mas5_2_slpid and (0 to lpid_width-1 => ex2_valid_q(2))) + or (mas5_3_slpid and (0 to lpid_width-1 => ex2_valid_q(3))); +ex2_mas6_spid <= (mas6_0_spid and (0 to pid_width-1 => ex2_valid_q(0))) + or (mas6_1_spid and (0 to pid_width-1 => ex2_valid_q(1))) + or (mas6_2_spid and (0 to pid_width-1 => ex2_valid_q(2))) + or (mas6_3_spid and (0 to pid_width-1 => ex2_valid_q(3))); +ex2_mas6_sind <= (mas6_0_sind and ex2_valid_q(0)) + or (mas6_1_sind and ex2_valid_q(1)) + or (mas6_2_sind and ex2_valid_q(2)) + or (mas6_3_sind and ex2_valid_q(3)); +ex2_valid_d <= ex1_valid_q and not(xu_ex1_flush); +ex2_flush_d <= (ex1_valid_q and xu_ex1_flush) when ex1_ttype_q/="00000" else "0000"; +ex2_flush_req_d <= (ex1_valid_q and not(xu_ex1_flush)) when (ex1_ttype_q(0 to 1)/="00" + and read_req_taken_sig='0' and write_req_taken_sig='0') + else "0000"; +ex2_ttype_d <= ex1_ttype_q; +ex2_state_d <= ex1_state_q; +ex2_pid_d <= ex1_pid_q; +ex2_flush_req_local <= ex2_valid_q when (ex2_ttype_q(2 to 4)/="000" and search_req_taken_sig='0' and searchresv_req_taken_sig='0') + else "0000"; +ex2_hv_state <= not ex2_state_q(0) and not ex2_state_q(1); +ex6_hv_state <= not ex6_state_q(0) and not ex6_state_q(1); +ex6_priv_state <= not ex6_state_q(0); +ex6_dgtmi_state <= or_reduce(ex6_valid_q and xu_mm_epcr_dgtmi); +ex3_valid_d <= ex2_valid_q and not(xu_ex2_flush) and not(ex2_flush_req_q) and not(ex2_flush_req_local); +ex3_flush_d <= ((ex2_valid_q and xu_ex2_flush) or ex2_flush_q or ex2_flush_req_q or ex2_flush_req_local) when ex2_ttype_q/="00000" else "0000"; +ex3_ttype_d <= ex2_ttype_q; +ex3_state_d <= ex2_state_q; +ex3_pid_d <= ex2_pid_q; +tlb_ctl_ex3_valid <= ex3_valid_q; +tlb_ctl_ex3_ttype <= ex3_ttype_q; +ex4_valid_d <= ex3_valid_q and not(xu_ex3_flush); +ex4_flush_d <= ((ex3_valid_q and xu_ex3_flush) or ex3_flush_q) when ex3_ttype_q/="00000" else "0000"; +ex4_ttype_d <= ex3_ttype_q; +ex4_state_d <= ex3_state_q; +ex4_pid_d <= ex3_pid_q; +ex5_valid_d <= ex4_valid_q and not(xu_ex4_flush); +ex5_flush_d <= ((ex4_valid_q and xu_ex4_flush) or ex4_flush_q) when ex4_ttype_q/="00000" else "0000"; +ex5_ttype_d <= ex4_ttype_q; +ex5_state_d <= ex4_state_q; +ex5_pid_d <= ex4_pid_q; +ex6_valid_d <= (others => '0') when (tlb_seq_read_done_sig='1' or tlb_seq_write_done_sig='1' or + tlb_seq_search_done_sig='1' or tlb_seq_searchresv_done_sig='1') + else (ex5_valid_q and not(xu_ex5_flush)) when (ex6_valid_q="0000" and ex5_ttype_q/="00000") + else ex6_valid_q; +ex6_flush_d <= ((ex5_valid_q and xu_ex5_flush) or ex5_flush_q) when ex5_ttype_q/="00000" else "0000"; +ex6_ttype_d <= ex5_ttype_q when ex6_valid_q="0000" + else ex6_ttype_q; +ex6_state_d <= ex5_state_q when ex6_valid_q="0000" + else ex6_state_q; +ex6_pid_d <= ex5_pid_q when ex6_valid_q="0000" + else ex6_pid_q; +tlb_ctl_barrier_done <= ex6_valid_q when (tlb_seq_search_done_sig='1' or tlb_seq_searchresv_done_sig='1' or + tlb_seq_read_done_sig='1' or tlb_seq_write_done_sig='1' ) + else (others => '0'); +tlb_set_resv0 <= '1' when (ex6_valid_q(0)='1' and ex6_ttype_q(4)='1' and tlb_seq_set_resv='1') + else '0'; +tlb_set_resv1 <= '1' when (ex6_valid_q(1)='1' and ex6_ttype_q(4)='1' and tlb_seq_set_resv='1') + else '0'; +tlb_set_resv2 <= '1' when (ex6_valid_q(2)='1' and ex6_ttype_q(4)='1' and tlb_seq_set_resv='1') + else '0'; +tlb_set_resv3 <= '1' when (ex6_valid_q(3)='1' and ex6_ttype_q(4)='1' and tlb_seq_set_resv='1') + else '0'; +tlb_clr_resv_d(0) <= + (tlb_seq_snoop_resv_q(0) and Eq(tlb_tag1_q(tagpos_is to tagpos_is+3),"0011") and tlb_resv0_tag1_lpid_match and + tlb_resv0_tag1_pid_match and tlb_resv0_tag1_gs_snoop_match and + tlb_resv0_tag1_as_snoop_match and tlb_resv0_tag1_epn_glob_match) + or (tlb_seq_snoop_resv_q(0) and Eq(tlb_tag1_q(tagpos_is to tagpos_is+3),"1000") and tlb_resv0_tag1_lpid_match) + or (tlb_seq_snoop_resv_q(0) and Eq(tlb_tag1_q(tagpos_is to tagpos_is+3),"1001") and + tlb_resv0_tag1_lpid_match and tlb_resv0_tag1_pid_match) + or (tlb_seq_snoop_resv_q(0) and Eq(tlb_tag1_q(tagpos_is to tagpos_is+3),"1011") and tlb_resv0_tag1_lpid_match and + tlb_resv0_tag1_pid_match and tlb_resv0_tag1_gs_snoop_match and + tlb_resv0_tag1_as_snoop_match and tlb_resv0_tag1_epn_loc_match) + or ( ((or_reduce(ex6_valid_q and tlb_resv_valid_vec) and Eq(tlb_tag4_wq,"01")) or + (or_reduce(ex6_valid_q) and Eq(tlb_tag4_wq,"00"))) and ex6_ttype_q(1) and + tlb_resv0_tag1_gs_tlbwe_match and tlb_resv0_tag1_as_tlbwe_match and + tlb_resv0_tag1_lpid_match and tlb_resv0_tag1_pid_match and + tlb_resv0_tag1_epn_loc_match and tlb_resv0_tag1_ind_match ) + or ( ex6_valid_q(0) and Eq(tlb_tag4_wq,"10") and ex6_ttype_q(1) ) + or ( tlb_tag4_ptereload and + tlb_resv0_tag1_gs_snoop_match and tlb_resv0_tag1_as_snoop_match and + tlb_resv0_tag1_lpid_match and tlb_resv0_tag1_pid_match and + tlb_resv0_tag1_epn_loc_match and tlb_resv0_tag1_ind_match ) + or ( ((or_reduce(ex6_valid_q) and Eq(tlb_tag4_wq,"10")) or + (or_reduce(ex6_valid_q) and Eq(tlb_tag4_wq,"11"))) and ex6_ttype_q(1) and + tlb_resv0_tag1_gs_tlbwe_match and tlb_resv0_tag1_as_tlbwe_match and + tlb_resv0_tag1_lpid_match and tlb_resv0_tag1_pid_match and + tlb_resv0_tag1_epn_loc_match and tlb_resv0_tag1_ind_match ) + or (tlb_seq_snoop_resv_q(0) and Eq(tlb_tag1_q(tagpos_is to tagpos_is+1),"11") and + tlb_resv0_tag1_class_match); +tlb_clr_resv_d(1) <= + (tlb_seq_snoop_resv_q(1) and Eq(tlb_tag1_q(tagpos_is to tagpos_is+3),"0011") and tlb_resv1_tag1_lpid_match and + tlb_resv1_tag1_pid_match and tlb_resv1_tag1_gs_snoop_match and + tlb_resv1_tag1_as_snoop_match and tlb_resv1_tag1_epn_glob_match) + or (tlb_seq_snoop_resv_q(1) and Eq(tlb_tag1_q(tagpos_is to tagpos_is+3),"1000") and tlb_resv1_tag1_lpid_match) + or (tlb_seq_snoop_resv_q(1) and Eq(tlb_tag1_q(tagpos_is to tagpos_is+3),"1001") and + tlb_resv1_tag1_lpid_match and tlb_resv1_tag1_pid_match) + or (tlb_seq_snoop_resv_q(1) and Eq(tlb_tag1_q(tagpos_is to tagpos_is+3),"1011") and tlb_resv1_tag1_lpid_match and + tlb_resv1_tag1_pid_match and tlb_resv1_tag1_gs_snoop_match and + tlb_resv1_tag1_as_snoop_match and tlb_resv1_tag1_epn_loc_match) + or ( ((or_reduce(ex6_valid_q and tlb_resv_valid_vec) and Eq(tlb_tag4_wq,"01")) or + (or_reduce(ex6_valid_q) and Eq(tlb_tag4_wq,"00"))) and ex6_ttype_q(1) and + tlb_resv1_tag1_gs_tlbwe_match and tlb_resv1_tag1_as_tlbwe_match and + tlb_resv1_tag1_lpid_match and tlb_resv1_tag1_pid_match and + tlb_resv1_tag1_epn_loc_match and tlb_resv1_tag1_ind_match ) + or ( ex6_valid_q(1) and Eq(tlb_tag4_wq,"10") and ex6_ttype_q(1) ) + or ( tlb_tag4_ptereload and + tlb_resv1_tag1_gs_snoop_match and tlb_resv1_tag1_as_snoop_match and + tlb_resv1_tag1_lpid_match and tlb_resv1_tag1_pid_match and + tlb_resv1_tag1_epn_loc_match and tlb_resv1_tag1_ind_match ) + or ( ((or_reduce(ex6_valid_q) and Eq(tlb_tag4_wq,"10")) or + (or_reduce(ex6_valid_q) and Eq(tlb_tag4_wq,"11"))) and ex6_ttype_q(1) and + tlb_resv1_tag1_gs_tlbwe_match and tlb_resv1_tag1_as_tlbwe_match and + tlb_resv1_tag1_lpid_match and tlb_resv1_tag1_pid_match and + tlb_resv1_tag1_epn_loc_match and tlb_resv1_tag1_ind_match ) + or (tlb_seq_snoop_resv_q(1) and Eq(tlb_tag1_q(tagpos_is to tagpos_is+1),"11") and + tlb_resv1_tag1_class_match); +tlb_clr_resv_d(2) <= + (tlb_seq_snoop_resv_q(2) and Eq(tlb_tag1_q(tagpos_is to tagpos_is+3),"0011") and tlb_resv2_tag1_lpid_match and + tlb_resv2_tag1_pid_match and tlb_resv2_tag1_gs_snoop_match and + tlb_resv2_tag1_as_snoop_match and tlb_resv2_tag1_epn_glob_match) + or (tlb_seq_snoop_resv_q(2) and Eq(tlb_tag1_q(tagpos_is to tagpos_is+3),"1000") and tlb_resv2_tag1_lpid_match) + or (tlb_seq_snoop_resv_q(2) and Eq(tlb_tag1_q(tagpos_is to tagpos_is+3),"1001") and + tlb_resv2_tag1_lpid_match and tlb_resv2_tag1_pid_match) + or (tlb_seq_snoop_resv_q(2) and Eq(tlb_tag1_q(tagpos_is to tagpos_is+3),"1011") and tlb_resv2_tag1_lpid_match and + tlb_resv2_tag1_pid_match and tlb_resv2_tag1_gs_snoop_match and + tlb_resv2_tag1_as_snoop_match and tlb_resv2_tag1_epn_loc_match) + or ( ((or_reduce(ex6_valid_q and tlb_resv_valid_vec) and Eq(tlb_tag4_wq,"01")) or + (or_reduce(ex6_valid_q) and Eq(tlb_tag4_wq,"00"))) and ex6_ttype_q(1) and + tlb_resv2_tag1_gs_tlbwe_match and tlb_resv2_tag1_as_tlbwe_match and + tlb_resv2_tag1_lpid_match and tlb_resv2_tag1_pid_match and + tlb_resv2_tag1_epn_loc_match and tlb_resv2_tag1_ind_match ) + or ( ex6_valid_q(2) and Eq(tlb_tag4_wq,"10") and ex6_ttype_q(1) ) + or ( tlb_tag4_ptereload and + tlb_resv2_tag1_gs_snoop_match and tlb_resv2_tag1_as_snoop_match and + tlb_resv2_tag1_lpid_match and tlb_resv2_tag1_pid_match and + tlb_resv2_tag1_epn_loc_match and tlb_resv2_tag1_ind_match ) + or ( ((or_reduce(ex6_valid_q) and Eq(tlb_tag4_wq,"10")) or + (or_reduce(ex6_valid_q) and Eq(tlb_tag4_wq,"11"))) and ex6_ttype_q(1) and + tlb_resv2_tag1_gs_tlbwe_match and tlb_resv2_tag1_as_tlbwe_match and + tlb_resv2_tag1_lpid_match and tlb_resv2_tag1_pid_match and + tlb_resv2_tag1_epn_loc_match and tlb_resv2_tag1_ind_match ) + or (tlb_seq_snoop_resv_q(2) and Eq(tlb_tag1_q(tagpos_is to tagpos_is+1),"11") and + tlb_resv2_tag1_class_match); +tlb_clr_resv_d(3) <= + (tlb_seq_snoop_resv_q(3) and Eq(tlb_tag1_q(tagpos_is to tagpos_is+3),"0011") and tlb_resv3_tag1_lpid_match and + tlb_resv3_tag1_pid_match and tlb_resv3_tag1_gs_snoop_match and + tlb_resv3_tag1_as_snoop_match and tlb_resv3_tag1_epn_glob_match) + or (tlb_seq_snoop_resv_q(3) and Eq(tlb_tag1_q(tagpos_is to tagpos_is+3),"1000") and tlb_resv3_tag1_lpid_match) + or (tlb_seq_snoop_resv_q(3) and Eq(tlb_tag1_q(tagpos_is to tagpos_is+3),"1001") and + tlb_resv3_tag1_lpid_match and tlb_resv3_tag1_pid_match) + or (tlb_seq_snoop_resv_q(3) and Eq(tlb_tag1_q(tagpos_is to tagpos_is+3),"1011") and tlb_resv3_tag1_lpid_match and + tlb_resv3_tag1_pid_match and tlb_resv3_tag1_gs_snoop_match and + tlb_resv3_tag1_as_snoop_match and tlb_resv3_tag1_epn_loc_match) + or ( ((or_reduce(ex6_valid_q and tlb_resv_valid_vec) and Eq(tlb_tag4_wq,"01")) or + (or_reduce(ex6_valid_q) and Eq(tlb_tag4_wq,"00"))) and ex6_ttype_q(1) and + tlb_resv3_tag1_gs_tlbwe_match and tlb_resv3_tag1_as_tlbwe_match and + tlb_resv3_tag1_lpid_match and tlb_resv3_tag1_pid_match and + tlb_resv3_tag1_epn_loc_match and tlb_resv3_tag1_ind_match ) + or ( ex6_valid_q(3) and Eq(tlb_tag4_wq,"10") and ex6_ttype_q(1) ) + or ( tlb_tag4_ptereload and + tlb_resv3_tag1_gs_snoop_match and tlb_resv3_tag1_as_snoop_match and + tlb_resv3_tag1_lpid_match and tlb_resv3_tag1_pid_match and + tlb_resv3_tag1_epn_loc_match and tlb_resv3_tag1_ind_match ) + or ( ((or_reduce(ex6_valid_q) and Eq(tlb_tag4_wq,"10")) or + (or_reduce(ex6_valid_q) and Eq(tlb_tag4_wq,"11"))) and ex6_ttype_q(1) and + tlb_resv3_tag1_gs_tlbwe_match and tlb_resv3_tag1_as_tlbwe_match and + tlb_resv3_tag1_lpid_match and tlb_resv3_tag1_pid_match and + tlb_resv3_tag1_epn_loc_match and tlb_resv3_tag1_ind_match ) + or (tlb_seq_snoop_resv_q(3) and Eq(tlb_tag1_q(tagpos_is to tagpos_is+1),"11") and + tlb_resv3_tag1_class_match); +tlb_resv_valid_vec <= tlb_resv0_valid_q & tlb_resv1_valid_q & tlb_resv2_valid_q & tlb_resv3_valid_q; +tlb_resv_match_vec <= tlb_resv_match_vec_q; +tlb_resv0_valid_d <= '0' when tlb_clr_resv_q(0)='1' and tlb_tag5_except(0)='0' + else ex6_valid_q(0) when tlb_set_resv0='1' + else tlb_resv0_valid_q; +tlb_resv0_epn_d <= tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-1) when (tlb_set_resv0='1') + else tlb_resv0_epn_q; +tlb_resv0_pid_d <= mas1_0_tid when (tlb_set_resv0='1') + else tlb_resv0_pid_q; +tlb_resv0_lpid_d <= mas5_0_slpid when (tlb_set_resv0='1') + else tlb_resv0_lpid_q; +tlb_resv0_as_d <= mas1_0_ts when (tlb_set_resv0='1') + else tlb_resv0_as_q; +tlb_resv0_gs_d <= mas5_0_sgs when (tlb_set_resv0='1') + else tlb_resv0_gs_q; +tlb_resv0_ind_d <= mas1_0_ind when (tlb_set_resv0='1') + else tlb_resv0_ind_q; +tlb_resv0_class_d <= mmucr3_0(54 to 55) when (tlb_set_resv0='1') + else tlb_resv0_class_q; +tlb_resv0_tag0_lpid_match <= '1' when (tlb_tag0_q(tagpos_lpid to tagpos_lpid+lpid_width-1)=tlb_resv0_lpid_q) else '0'; +tlb_resv0_tag0_pid_match <= '1' when (tlb_tag0_q(tagpos_pid to tagpos_pid+pid_width-1)=tlb_resv0_pid_q) else '0'; +tlb_resv0_tag0_gs_snoop_match <= '1' when (tlb_tag0_q(tagpos_gs)=tlb_resv0_gs_q) else '0'; +tlb_resv0_tag0_as_snoop_match <= '1' when (tlb_tag0_q(tagpos_as)=tlb_resv0_as_q) else '0'; +tlb_resv0_tag0_gs_tlbwe_match <= '1' when (tlb_tag0_q(tagpos_pt)=tlb_resv0_gs_q) else '0'; +tlb_resv0_tag0_as_tlbwe_match <= '1' when (tlb_tag0_q(tagpos_recform)=tlb_resv0_as_q) else '0'; +tlb_resv0_tag0_ind_match <= '1' when (tlb_tag0_q(tagpos_ind)=tlb_resv0_ind_q) else '0'; +tlb_resv0_tag0_class_match <= '1' when (tlb_tag0_q(tagpos_class to tagpos_class+1)=tlb_resv0_class_q) else '0'; +tlb_resv0_tag0_epn_loc_match <= '1' when (tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-1)=tlb_resv0_epn_q(52-epn_width to 51) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_4KB) or + (tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-5)=tlb_resv0_epn_q(52-epn_width to 47) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_64KB) or + (tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-9)=tlb_resv0_epn_q(52-epn_width to 43) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1MB) or + (tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-13)=tlb_resv0_epn_q(52-epn_width to 39) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_16MB) or + (tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-17)=tlb_resv0_epn_q(52-epn_width to 35) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_256MB) or + (tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-19)=tlb_resv0_epn_q(52-epn_width to 33) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1GB) + else '0'; +tlb_resv0_tag0_epn_glob_match <= '1' when (tlb_tag0_q(tagpos_epn+31 to tagpos_epn+epn_width-1)=tlb_resv0_epn_q(52-epn_width+31 to 51) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_4KB) or + (tlb_tag0_q(tagpos_epn+31 to tagpos_epn+epn_width-5)=tlb_resv0_epn_q(52-epn_width+31 to 47) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_64KB) or + (tlb_tag0_q(tagpos_epn+31 to tagpos_epn+epn_width-9)=tlb_resv0_epn_q(52-epn_width+31 to 43) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1MB) or + (tlb_tag0_q(tagpos_epn+31 to tagpos_epn+epn_width-13)=tlb_resv0_epn_q(52-epn_width+31 to 39) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_16MB) or + (tlb_tag0_q(tagpos_epn+31 to tagpos_epn+epn_width-17)=tlb_resv0_epn_q(52-epn_width+31 to 35) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_256MB) or + (tlb_tag0_q(tagpos_epn+31 to tagpos_epn+epn_width-19)=tlb_resv0_epn_q(52-epn_width+31 to 33) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1GB) + else '0'; +tlb_resv_match_vec_d(0) <= (tlb_resv0_valid_q and tlb_tag0_q(tagpos_type_snoop)='1' + and tlb_resv0_tag0_epn_loc_match and tlb_resv0_tag0_lpid_match and tlb_resv0_tag0_pid_match + and tlb_resv0_tag0_as_snoop_match and tlb_resv0_tag0_gs_snoop_match) or + (tlb_resv0_valid_q and tlb_tag0_q(tagpos_type_tlbwe)='1' + and tlb_resv0_tag0_epn_loc_match and tlb_resv0_tag0_lpid_match and tlb_resv0_tag0_pid_match + and tlb_resv0_tag0_as_tlbwe_match and tlb_resv0_tag0_gs_tlbwe_match and tlb_resv0_tag0_ind_match) or + (tlb_resv0_valid_q and tlb_tag0_q(tagpos_type_ptereload)='1' + and tlb_resv0_tag0_epn_loc_match and tlb_resv0_tag0_lpid_match and tlb_resv0_tag0_pid_match + and tlb_resv0_tag0_as_snoop_match and tlb_resv0_tag0_gs_snoop_match and tlb_resv0_tag0_ind_match); +tlb_resv1_valid_d <= '0' when tlb_clr_resv_q(1)='1' and tlb_tag5_except(1)='0' + else ex6_valid_q(1) when tlb_set_resv1='1' + else tlb_resv1_valid_q; +tlb_resv1_epn_d <= tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-1) when (tlb_set_resv1='1') + else tlb_resv1_epn_q; +tlb_resv1_pid_d <= mas1_1_tid when (tlb_set_resv1='1') + else tlb_resv1_pid_q; +tlb_resv1_lpid_d <= mas5_1_slpid when (tlb_set_resv1='1') + else tlb_resv1_lpid_q; +tlb_resv1_as_d <= mas1_1_ts when (tlb_set_resv1='1') + else tlb_resv1_as_q; +tlb_resv1_gs_d <= mas5_1_sgs when (tlb_set_resv1='1') + else tlb_resv1_gs_q; +tlb_resv1_ind_d <= mas1_1_ind when (tlb_set_resv1='1') + else tlb_resv1_ind_q; +tlb_resv1_class_d <= mmucr3_1(54 to 55) when (tlb_set_resv1='1') + else tlb_resv1_class_q; +tlb_resv1_tag0_lpid_match <= '1' when (tlb_tag0_q(tagpos_lpid to tagpos_lpid+lpid_width-1)=tlb_resv1_lpid_q) else '0'; +tlb_resv1_tag0_pid_match <= '1' when (tlb_tag0_q(tagpos_pid to tagpos_pid+pid_width-1)=tlb_resv1_pid_q) else '0'; +tlb_resv1_tag0_gs_snoop_match <= '1' when (tlb_tag0_q(tagpos_gs)=tlb_resv1_gs_q) else '0'; +tlb_resv1_tag0_as_snoop_match <= '1' when (tlb_tag0_q(tagpos_as)=tlb_resv1_as_q) else '0'; +tlb_resv1_tag0_gs_tlbwe_match <= '1' when (tlb_tag0_q(tagpos_pt)=tlb_resv1_gs_q) else '0'; +tlb_resv1_tag0_as_tlbwe_match <= '1' when (tlb_tag0_q(tagpos_recform)=tlb_resv1_as_q) else '0'; +tlb_resv1_tag0_ind_match <= '1' when (tlb_tag0_q(tagpos_ind)=tlb_resv1_ind_q) else '0'; +tlb_resv1_tag0_class_match <= '1' when (tlb_tag0_q(tagpos_class to tagpos_class+1)=tlb_resv1_class_q) else '0'; +tlb_resv1_tag0_epn_loc_match <= '1' when (tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-1)=tlb_resv1_epn_q(52-epn_width to 51) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_4KB) or + (tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-5)=tlb_resv1_epn_q(52-epn_width to 47) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_64KB) or + (tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-9)=tlb_resv1_epn_q(52-epn_width to 43) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1MB) or + (tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-13)=tlb_resv1_epn_q(52-epn_width to 39) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_16MB) or + (tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-17)=tlb_resv1_epn_q(52-epn_width to 35) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_256MB) or + (tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-19)=tlb_resv1_epn_q(52-epn_width to 33) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1GB) + else '0'; +tlb_resv1_tag0_epn_glob_match <= '1' when (tlb_tag0_q(tagpos_epn+31 to tagpos_epn+epn_width-1)=tlb_resv1_epn_q(52-epn_width+31 to 51) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_4KB) or + (tlb_tag0_q(tagpos_epn+31 to tagpos_epn+epn_width-5)=tlb_resv1_epn_q(52-epn_width+31 to 47) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_64KB) or + (tlb_tag0_q(tagpos_epn+31 to tagpos_epn+epn_width-9)=tlb_resv1_epn_q(52-epn_width+31 to 43) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1MB) or + (tlb_tag0_q(tagpos_epn+31 to tagpos_epn+epn_width-13)=tlb_resv1_epn_q(52-epn_width+31 to 39) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_16MB) or + (tlb_tag0_q(tagpos_epn+31 to tagpos_epn+epn_width-17)=tlb_resv1_epn_q(52-epn_width+31 to 35) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_256MB) or + (tlb_tag0_q(tagpos_epn+31 to tagpos_epn+epn_width-19)=tlb_resv1_epn_q(52-epn_width+31 to 33) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1GB) + else '0'; +tlb_resv_match_vec_d(1) <= (tlb_resv1_valid_q and tlb_tag0_q(tagpos_type_snoop)='1' + and tlb_resv1_tag0_epn_loc_match and tlb_resv1_tag0_lpid_match and tlb_resv1_tag0_pid_match + and tlb_resv1_tag0_as_snoop_match and tlb_resv1_tag0_gs_snoop_match) or + (tlb_resv1_valid_q and tlb_tag0_q(tagpos_type_tlbwe)='1' + and tlb_resv1_tag0_epn_loc_match and tlb_resv1_tag0_lpid_match and tlb_resv1_tag0_pid_match + and tlb_resv1_tag0_as_tlbwe_match and tlb_resv1_tag0_gs_tlbwe_match and tlb_resv1_tag0_ind_match) or + (tlb_resv1_valid_q and tlb_tag0_q(tagpos_type_ptereload)='1' + and tlb_resv1_tag0_epn_loc_match and tlb_resv1_tag0_lpid_match and tlb_resv1_tag0_pid_match + and tlb_resv1_tag0_as_snoop_match and tlb_resv1_tag0_gs_snoop_match and tlb_resv1_tag0_ind_match); +tlb_resv2_valid_d <= '0' when tlb_clr_resv_q(2)='1' and tlb_tag5_except(2)='0' + else ex6_valid_q(2) when tlb_set_resv2='1' + else tlb_resv2_valid_q; +tlb_resv2_epn_d <= tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-1) when (tlb_set_resv2='1') + else tlb_resv2_epn_q; +tlb_resv2_pid_d <= mas1_2_tid when (tlb_set_resv2='1') + else tlb_resv2_pid_q; +tlb_resv2_lpid_d <= mas5_2_slpid when (tlb_set_resv2='1') + else tlb_resv2_lpid_q; +tlb_resv2_as_d <= mas1_2_ts when (tlb_set_resv2='1') + else tlb_resv2_as_q; +tlb_resv2_gs_d <= mas5_2_sgs when (tlb_set_resv2='1') + else tlb_resv2_gs_q; +tlb_resv2_ind_d <= mas1_2_ind when (tlb_set_resv2='1') + else tlb_resv2_ind_q; +tlb_resv2_class_d <= mmucr3_2(54 to 55) when (tlb_set_resv2='1') + else tlb_resv2_class_q; +tlb_resv2_tag0_lpid_match <= '1' when (tlb_tag0_q(tagpos_lpid to tagpos_lpid+lpid_width-1)=tlb_resv2_lpid_q) else '0'; +tlb_resv2_tag0_pid_match <= '1' when (tlb_tag0_q(tagpos_pid to tagpos_pid+pid_width-1)=tlb_resv2_pid_q) else '0'; +tlb_resv2_tag0_gs_snoop_match <= '1' when (tlb_tag0_q(tagpos_gs)=tlb_resv2_gs_q) else '0'; +tlb_resv2_tag0_as_snoop_match <= '1' when (tlb_tag0_q(tagpos_as)=tlb_resv2_as_q) else '0'; +tlb_resv2_tag0_gs_tlbwe_match <= '1' when (tlb_tag0_q(tagpos_pt)=tlb_resv2_gs_q) else '0'; +tlb_resv2_tag0_as_tlbwe_match <= '1' when (tlb_tag0_q(tagpos_recform)=tlb_resv2_as_q) else '0'; +tlb_resv2_tag0_ind_match <= '1' when (tlb_tag0_q(tagpos_ind)=tlb_resv2_ind_q) else '0'; +tlb_resv2_tag0_class_match <= '1' when (tlb_tag0_q(tagpos_class to tagpos_class+1)=tlb_resv2_class_q) else '0'; +tlb_resv2_tag0_epn_loc_match <= '1' when (tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-1)=tlb_resv2_epn_q(52-epn_width to 51) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_4KB) or + (tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-5)=tlb_resv2_epn_q(52-epn_width to 47) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_64KB) or + (tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-9)=tlb_resv2_epn_q(52-epn_width to 43) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1MB) or + (tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-13)=tlb_resv2_epn_q(52-epn_width to 39) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_16MB) or + (tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-17)=tlb_resv2_epn_q(52-epn_width to 35) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_256MB) or + (tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-19)=tlb_resv2_epn_q(52-epn_width to 33) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1GB) + else '0'; +tlb_resv2_tag0_epn_glob_match <= '1' when (tlb_tag0_q(tagpos_epn+31 to tagpos_epn+epn_width-1)=tlb_resv2_epn_q(52-epn_width+31 to 51) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_4KB) or + (tlb_tag0_q(tagpos_epn+31 to tagpos_epn+epn_width-5)=tlb_resv2_epn_q(52-epn_width+31 to 47) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_64KB) or + (tlb_tag0_q(tagpos_epn+31 to tagpos_epn+epn_width-9)=tlb_resv2_epn_q(52-epn_width+31 to 43) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1MB) or + (tlb_tag0_q(tagpos_epn+31 to tagpos_epn+epn_width-13)=tlb_resv2_epn_q(52-epn_width+31 to 39) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_16MB) or + (tlb_tag0_q(tagpos_epn+31 to tagpos_epn+epn_width-17)=tlb_resv2_epn_q(52-epn_width+31 to 35) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_256MB) or + (tlb_tag0_q(tagpos_epn+31 to tagpos_epn+epn_width-19)=tlb_resv2_epn_q(52-epn_width+31 to 33) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1GB) + else '0'; +tlb_resv_match_vec_d(2) <= (tlb_resv2_valid_q and tlb_tag0_q(tagpos_type_snoop)='1' + and tlb_resv2_tag0_epn_loc_match and tlb_resv2_tag0_lpid_match and tlb_resv2_tag0_pid_match + and tlb_resv2_tag0_as_snoop_match and tlb_resv2_tag0_gs_snoop_match) or + (tlb_resv2_valid_q and tlb_tag0_q(tagpos_type_tlbwe)='1' + and tlb_resv2_tag0_epn_loc_match and tlb_resv2_tag0_lpid_match and tlb_resv2_tag0_pid_match + and tlb_resv2_tag0_as_tlbwe_match and tlb_resv2_tag0_gs_tlbwe_match and tlb_resv2_tag0_ind_match) or + (tlb_resv2_valid_q and tlb_tag0_q(tagpos_type_ptereload)='1' + and tlb_resv2_tag0_epn_loc_match and tlb_resv2_tag0_lpid_match and tlb_resv2_tag0_pid_match + and tlb_resv2_tag0_as_snoop_match and tlb_resv2_tag0_gs_snoop_match and tlb_resv2_tag0_ind_match); +tlb_resv3_valid_d <= '0' when tlb_clr_resv_q(3)='1' and tlb_tag5_except(3)='0' + else ex6_valid_q(3) when tlb_set_resv3='1' + else tlb_resv3_valid_q; +tlb_resv3_epn_d <= tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-1) when (tlb_set_resv3='1') + else tlb_resv3_epn_q; +tlb_resv3_pid_d <= mas1_3_tid when (tlb_set_resv3='1') + else tlb_resv3_pid_q; +tlb_resv3_lpid_d <= mas5_3_slpid when (tlb_set_resv3='1') + else tlb_resv3_lpid_q; +tlb_resv3_as_d <= mas1_3_ts when (tlb_set_resv3='1') + else tlb_resv3_as_q; +tlb_resv3_gs_d <= mas5_3_sgs when (tlb_set_resv3='1') + else tlb_resv3_gs_q; +tlb_resv3_ind_d <= mas1_3_ind when (tlb_set_resv3='1') + else tlb_resv3_ind_q; +tlb_resv3_class_d <= mmucr3_3(54 to 55) when (tlb_set_resv3='1') + else tlb_resv3_class_q; +tlb_resv3_tag0_lpid_match <= '1' when (tlb_tag0_q(tagpos_lpid to tagpos_lpid+lpid_width-1)=tlb_resv3_lpid_q) else '0'; +tlb_resv3_tag0_pid_match <= '1' when (tlb_tag0_q(tagpos_pid to tagpos_pid+pid_width-1)=tlb_resv3_pid_q) else '0'; +tlb_resv3_tag0_gs_snoop_match <= '1' when (tlb_tag0_q(tagpos_gs)=tlb_resv3_gs_q) else '0'; +tlb_resv3_tag0_as_snoop_match <= '1' when (tlb_tag0_q(tagpos_as)=tlb_resv3_as_q) else '0'; +tlb_resv3_tag0_gs_tlbwe_match <= '1' when (tlb_tag0_q(tagpos_pt)=tlb_resv3_gs_q) else '0'; +tlb_resv3_tag0_as_tlbwe_match <= '1' when (tlb_tag0_q(tagpos_recform)=tlb_resv3_as_q) else '0'; +tlb_resv3_tag0_ind_match <= '1' when (tlb_tag0_q(tagpos_ind)=tlb_resv3_ind_q) else '0'; +tlb_resv3_tag0_class_match <= '1' when (tlb_tag0_q(tagpos_class to tagpos_class+1)=tlb_resv3_class_q) else '0'; +tlb_resv3_tag0_epn_loc_match <= '1' when (tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-1)=tlb_resv3_epn_q(52-epn_width to 51) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_4KB) or + (tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-5)=tlb_resv3_epn_q(52-epn_width to 47) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_64KB) or + (tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-9)=tlb_resv3_epn_q(52-epn_width to 43) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1MB) or + (tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-13)=tlb_resv3_epn_q(52-epn_width to 39) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_16MB) or + (tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-17)=tlb_resv3_epn_q(52-epn_width to 35) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_256MB) or + (tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-19)=tlb_resv3_epn_q(52-epn_width to 33) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1GB) + else '0'; +tlb_resv3_tag0_epn_glob_match <= '1' when (tlb_tag0_q(tagpos_epn+31 to tagpos_epn+epn_width-1)=tlb_resv3_epn_q(52-epn_width+31 to 51) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_4KB) or + (tlb_tag0_q(tagpos_epn+31 to tagpos_epn+epn_width-5)=tlb_resv3_epn_q(52-epn_width+31 to 47) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_64KB) or + (tlb_tag0_q(tagpos_epn+31 to tagpos_epn+epn_width-9)=tlb_resv3_epn_q(52-epn_width+31 to 43) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1MB) or + (tlb_tag0_q(tagpos_epn+31 to tagpos_epn+epn_width-13)=tlb_resv3_epn_q(52-epn_width+31 to 39) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_16MB) or + (tlb_tag0_q(tagpos_epn+31 to tagpos_epn+epn_width-17)=tlb_resv3_epn_q(52-epn_width+31 to 35) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_256MB) or + (tlb_tag0_q(tagpos_epn+31 to tagpos_epn+epn_width-19)=tlb_resv3_epn_q(52-epn_width+31 to 33) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1GB) + else '0'; +tlb_resv_match_vec_d(3) <= (tlb_resv3_valid_q and tlb_tag0_q(tagpos_type_snoop)='1' + and tlb_resv3_tag0_epn_loc_match and tlb_resv3_tag0_lpid_match and tlb_resv3_tag0_pid_match + and tlb_resv3_tag0_as_snoop_match and tlb_resv3_tag0_gs_snoop_match) or + (tlb_resv3_valid_q and tlb_tag0_q(tagpos_type_tlbwe)='1' + and tlb_resv3_tag0_epn_loc_match and tlb_resv3_tag0_lpid_match and tlb_resv3_tag0_pid_match + and tlb_resv3_tag0_as_tlbwe_match and tlb_resv3_tag0_gs_tlbwe_match and tlb_resv3_tag0_ind_match) or + (tlb_resv3_valid_q and tlb_tag0_q(tagpos_type_ptereload)='1' + and tlb_resv3_tag0_epn_loc_match and tlb_resv3_tag0_lpid_match and tlb_resv3_tag0_pid_match + and tlb_resv3_tag0_as_snoop_match and tlb_resv3_tag0_gs_snoop_match and tlb_resv3_tag0_ind_match); +tlbaddrwidth7_gen: if tlb_addr_width = 7 generate +size_1G_hashed_addr(6) <= tlb_tag0_q(33) xor tlb_tag0_q(tagpos_pid+pid_width-1); +size_1G_hashed_addr(5) <= tlb_tag0_q(32) xor tlb_tag0_q(tagpos_pid+pid_width-2); +size_1G_hashed_addr(4) <= tlb_tag0_q(31) xor tlb_tag0_q(tagpos_pid+pid_width-3); +size_1G_hashed_addr(3) <= tlb_tag0_q(30) xor tlb_tag0_q(tagpos_pid+pid_width-4); +size_1G_hashed_addr(2) <= tlb_tag0_q(29) xor tlb_tag0_q(tagpos_pid+pid_width-5); +size_1G_hashed_addr(1) <= tlb_tag0_q(28) xor tlb_tag0_q(tagpos_pid+pid_width-6); +size_1G_hashed_addr(0) <= tlb_tag0_q(27) xor tlb_tag0_q(tagpos_pid+pid_width-7); +size_1G_hashed_tid0_addr(6) <= tlb_tag0_q(33); +size_1G_hashed_tid0_addr(5) <= tlb_tag0_q(32); +size_1G_hashed_tid0_addr(4) <= tlb_tag0_q(31); +size_1G_hashed_tid0_addr(3) <= tlb_tag0_q(30); +size_1G_hashed_tid0_addr(2) <= tlb_tag0_q(29); +size_1G_hashed_tid0_addr(1) <= tlb_tag0_q(28); +size_1G_hashed_tid0_addr(0) <= tlb_tag0_q(27); +size_256M_hashed_addr(6) <= tlb_tag0_q(35) xor tlb_tag0_q(tagpos_pid+pid_width-1); +size_256M_hashed_addr(5) <= tlb_tag0_q(34) xor tlb_tag0_q(tagpos_pid+pid_width-2); +size_256M_hashed_addr(4) <= tlb_tag0_q(33) xor tlb_tag0_q(tagpos_pid+pid_width-3); +size_256M_hashed_addr(3) <= tlb_tag0_q(32) xor tlb_tag0_q(tagpos_pid+pid_width-4); +size_256M_hashed_addr(2) <= tlb_tag0_q(31) xor tlb_tag0_q(tagpos_pid+pid_width-5); +size_256M_hashed_addr(1) <= tlb_tag0_q(30) xor tlb_tag0_q(28) xor tlb_tag0_q(tagpos_pid+pid_width-6); +size_256M_hashed_addr(0) <= tlb_tag0_q(29) xor tlb_tag0_q(27) xor tlb_tag0_q(tagpos_pid+pid_width-7); +size_256M_hashed_tid0_addr(6) <= tlb_tag0_q(35); +size_256M_hashed_tid0_addr(5) <= tlb_tag0_q(34); +size_256M_hashed_tid0_addr(4) <= tlb_tag0_q(33); +size_256M_hashed_tid0_addr(3) <= tlb_tag0_q(32); +size_256M_hashed_tid0_addr(2) <= tlb_tag0_q(31); +size_256M_hashed_tid0_addr(1) <= tlb_tag0_q(30) xor tlb_tag0_q(28); +size_256M_hashed_tid0_addr(0) <= tlb_tag0_q(29) xor tlb_tag0_q(27); +size_16M_hashed_addr(6) <= tlb_tag0_q(39) xor tlb_tag0_q(tagpos_pid+pid_width-1); +size_16M_hashed_addr(5) <= tlb_tag0_q(38) xor tlb_tag0_q(tagpos_pid+pid_width-2); +size_16M_hashed_addr(4) <= tlb_tag0_q(37) xor tlb_tag0_q(tagpos_pid+pid_width-3); +size_16M_hashed_addr(3) <= tlb_tag0_q(36) xor tlb_tag0_q(32) xor tlb_tag0_q(tagpos_pid+pid_width-4); +size_16M_hashed_addr(2) <= tlb_tag0_q(35) xor tlb_tag0_q(31) xor tlb_tag0_q(tagpos_pid+pid_width-5); +size_16M_hashed_addr(1) <= tlb_tag0_q(34) xor tlb_tag0_q(30) xor tlb_tag0_q(tagpos_pid+pid_width-6); +size_16M_hashed_addr(0) <= tlb_tag0_q(33) xor tlb_tag0_q(29) xor tlb_tag0_q(tagpos_pid+pid_width-7); +size_16M_hashed_tid0_addr(6) <= tlb_tag0_q(39); +size_16M_hashed_tid0_addr(5) <= tlb_tag0_q(38); +size_16M_hashed_tid0_addr(4) <= tlb_tag0_q(37); +size_16M_hashed_tid0_addr(3) <= tlb_tag0_q(36) xor tlb_tag0_q(32); +size_16M_hashed_tid0_addr(2) <= tlb_tag0_q(35) xor tlb_tag0_q(31); +size_16M_hashed_tid0_addr(1) <= tlb_tag0_q(34) xor tlb_tag0_q(30); +size_16M_hashed_tid0_addr(0) <= tlb_tag0_q(33) xor tlb_tag0_q(29); +size_1M_hashed_addr(6) <= tlb_tag0_q(43) xor tlb_tag0_q(36) xor tlb_tag0_q(tagpos_pid+pid_width-1); +size_1M_hashed_addr(5) <= tlb_tag0_q(42) xor tlb_tag0_q(35) xor tlb_tag0_q(tagpos_pid+pid_width-2); +size_1M_hashed_addr(4) <= tlb_tag0_q(41) xor tlb_tag0_q(34) xor tlb_tag0_q(tagpos_pid+pid_width-3); +size_1M_hashed_addr(3) <= tlb_tag0_q(40) xor tlb_tag0_q(33) xor tlb_tag0_q(tagpos_pid+pid_width-4); +size_1M_hashed_addr(2) <= tlb_tag0_q(39) xor tlb_tag0_q(32) xor tlb_tag0_q(tagpos_pid+pid_width-5); +size_1M_hashed_addr(1) <= tlb_tag0_q(38) xor tlb_tag0_q(31) xor tlb_tag0_q(tagpos_pid+pid_width-6); +size_1M_hashed_addr(0) <= tlb_tag0_q(37) xor tlb_tag0_q(30) xor tlb_tag0_q(tagpos_pid+pid_width-7); +size_1M_hashed_tid0_addr(6) <= tlb_tag0_q(43) xor tlb_tag0_q(36); +size_1M_hashed_tid0_addr(5) <= tlb_tag0_q(42) xor tlb_tag0_q(35); +size_1M_hashed_tid0_addr(4) <= tlb_tag0_q(41) xor tlb_tag0_q(34); +size_1M_hashed_tid0_addr(3) <= tlb_tag0_q(40) xor tlb_tag0_q(33); +size_1M_hashed_tid0_addr(2) <= tlb_tag0_q(39) xor tlb_tag0_q(32); +size_1M_hashed_tid0_addr(1) <= tlb_tag0_q(38) xor tlb_tag0_q(31); +size_1M_hashed_tid0_addr(0) <= tlb_tag0_q(37) xor tlb_tag0_q(30); +size_64K_hashed_addr(6) <= tlb_tag0_q(47) xor tlb_tag0_q(37) xor tlb_tag0_q(tagpos_pid+pid_width-1); +size_64K_hashed_addr(5) <= tlb_tag0_q(46) xor tlb_tag0_q(36) xor tlb_tag0_q(tagpos_pid+pid_width-2); +size_64K_hashed_addr(4) <= tlb_tag0_q(45) xor tlb_tag0_q(35) xor tlb_tag0_q(tagpos_pid+pid_width-3); +size_64K_hashed_addr(3) <= tlb_tag0_q(44) xor tlb_tag0_q(34) xor tlb_tag0_q(tagpos_pid+pid_width-4); +size_64K_hashed_addr(2) <= tlb_tag0_q(43) xor tlb_tag0_q(40) xor tlb_tag0_q(33) xor tlb_tag0_q(tagpos_pid+pid_width-5); +size_64K_hashed_addr(1) <= tlb_tag0_q(42) xor tlb_tag0_q(39) xor tlb_tag0_q(32) xor tlb_tag0_q(tagpos_pid+pid_width-6); +size_64K_hashed_addr(0) <= tlb_tag0_q(41) xor tlb_tag0_q(38) xor tlb_tag0_q(31) xor tlb_tag0_q(tagpos_pid+pid_width-7); +size_64K_hashed_tid0_addr(6) <= tlb_tag0_q(47) xor tlb_tag0_q(37); +size_64K_hashed_tid0_addr(5) <= tlb_tag0_q(46) xor tlb_tag0_q(36); +size_64K_hashed_tid0_addr(4) <= tlb_tag0_q(45) xor tlb_tag0_q(35); +size_64K_hashed_tid0_addr(3) <= tlb_tag0_q(44) xor tlb_tag0_q(34); +size_64K_hashed_tid0_addr(2) <= tlb_tag0_q(43) xor tlb_tag0_q(40) xor tlb_tag0_q(33); +size_64K_hashed_tid0_addr(1) <= tlb_tag0_q(42) xor tlb_tag0_q(39) xor tlb_tag0_q(32); +size_64K_hashed_tid0_addr(0) <= tlb_tag0_q(41) xor tlb_tag0_q(38) xor tlb_tag0_q(31); +size_4K_hashed_addr(6) <= tlb_tag0_q(51) xor tlb_tag0_q(44) xor tlb_tag0_q(37) xor tlb_tag0_q(tagpos_pid+pid_width-1); +size_4K_hashed_addr(5) <= tlb_tag0_q(50) xor tlb_tag0_q(43) xor tlb_tag0_q(36) xor tlb_tag0_q(tagpos_pid+pid_width-2); +size_4K_hashed_addr(4) <= tlb_tag0_q(49) xor tlb_tag0_q(42) xor tlb_tag0_q(35) xor tlb_tag0_q(tagpos_pid+pid_width-3); +size_4K_hashed_addr(3) <= tlb_tag0_q(48) xor tlb_tag0_q(41) xor tlb_tag0_q(34) xor tlb_tag0_q(tagpos_pid+pid_width-4); +size_4K_hashed_addr(2) <= tlb_tag0_q(47) xor tlb_tag0_q(40) xor tlb_tag0_q(33) xor tlb_tag0_q(tagpos_pid+pid_width-5); +size_4K_hashed_addr(1) <= tlb_tag0_q(46) xor tlb_tag0_q(39) xor tlb_tag0_q(32) xor tlb_tag0_q(tagpos_pid+pid_width-6); +size_4K_hashed_addr(0) <= tlb_tag0_q(45) xor tlb_tag0_q(38) xor tlb_tag0_q(31) xor tlb_tag0_q(tagpos_pid+pid_width-7); +size_4K_hashed_tid0_addr(6) <= tlb_tag0_q(51) xor tlb_tag0_q(44) xor tlb_tag0_q(37); +size_4K_hashed_tid0_addr(5) <= tlb_tag0_q(50) xor tlb_tag0_q(43) xor tlb_tag0_q(36); +size_4K_hashed_tid0_addr(4) <= tlb_tag0_q(49) xor tlb_tag0_q(42) xor tlb_tag0_q(35); +size_4K_hashed_tid0_addr(3) <= tlb_tag0_q(48) xor tlb_tag0_q(41) xor tlb_tag0_q(34); +size_4K_hashed_tid0_addr(2) <= tlb_tag0_q(47) xor tlb_tag0_q(40) xor tlb_tag0_q(33); +size_4K_hashed_tid0_addr(1) <= tlb_tag0_q(46) xor tlb_tag0_q(39) xor tlb_tag0_q(32); +size_4K_hashed_tid0_addr(0) <= tlb_tag0_q(45) xor tlb_tag0_q(38) xor tlb_tag0_q(31); +end generate tlbaddrwidth7_gen; +tlb_tag0_tid_notzero <= or_reduce(tlb_tag0_q(tagpos_pid to tagpos_pid+pid_width-1)); +tlb_tag0_hashed_addr <= size_1G_hashed_addr when tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1GB + else size_256M_hashed_addr when tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_256MB + else size_16M_hashed_addr when tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_16MB + else size_1M_hashed_addr when tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1MB + else size_64K_hashed_addr when tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_64KB + else size_4K_hashed_addr; +tlb_tag0_hashed_tid0_addr <= size_1G_hashed_tid0_addr when tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1GB + else size_256M_hashed_tid0_addr when tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_256MB + else size_16M_hashed_tid0_addr when tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_16MB + else size_1M_hashed_tid0_addr when tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1MB + else size_64K_hashed_tid0_addr when tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_64KB + else size_4K_hashed_tid0_addr; +tlb_hashed_addr1 <= size_1G_hashed_addr when mmucr2(28 to 31)=TLB_PgSize_1GB + else size_16M_hashed_addr when mmucr2(28 to 31)=TLB_PgSize_16MB + else size_1M_hashed_addr when mmucr2(28 to 31)=TLB_PgSize_1MB + else size_64K_hashed_addr when mmucr2(28 to 31)=TLB_PgSize_64KB + else size_4K_hashed_addr; +tlb_hashed_tid0_addr1 <= size_1G_hashed_tid0_addr when mmucr2(28 to 31)=TLB_PgSize_1GB + else size_16M_hashed_tid0_addr when mmucr2(28 to 31)=TLB_PgSize_16MB + else size_1M_hashed_tid0_addr when mmucr2(28 to 31)=TLB_PgSize_1MB + else size_64K_hashed_tid0_addr when mmucr2(28 to 31)=TLB_PgSize_64KB + else size_4K_hashed_tid0_addr; +tlb_hashed_addr2 <= size_1G_hashed_addr when mmucr2(24 to 27)=TLB_PgSize_1GB + else size_16M_hashed_addr when mmucr2(24 to 27)=TLB_PgSize_16MB + else size_1M_hashed_addr when mmucr2(24 to 27)=TLB_PgSize_1MB + else size_64K_hashed_addr when mmucr2(24 to 27)=TLB_PgSize_64KB + else size_4K_hashed_addr; +tlb_hashed_tid0_addr2 <= size_1G_hashed_tid0_addr when mmucr2(24 to 27)=TLB_PgSize_1GB + else size_16M_hashed_tid0_addr when mmucr2(24 to 27)=TLB_PgSize_16MB + else size_1M_hashed_tid0_addr when mmucr2(24 to 27)=TLB_PgSize_1MB + else size_64K_hashed_tid0_addr when mmucr2(24 to 27)=TLB_PgSize_64KB + else size_4K_hashed_tid0_addr; +tlb_hashed_addr3 <= size_1G_hashed_addr when mmucr2(20 to 23)=TLB_PgSize_1GB + else size_16M_hashed_addr when mmucr2(20 to 23)=TLB_PgSize_16MB + else size_1M_hashed_addr when mmucr2(20 to 23)=TLB_PgSize_1MB + else size_64K_hashed_addr when mmucr2(20 to 23)=TLB_PgSize_64KB + else size_4K_hashed_addr; +tlb_hashed_tid0_addr3 <= size_1G_hashed_tid0_addr when mmucr2(20 to 23)=TLB_PgSize_1GB + else size_16M_hashed_tid0_addr when mmucr2(20 to 23)=TLB_PgSize_16MB + else size_1M_hashed_tid0_addr when mmucr2(20 to 23)=TLB_PgSize_1MB + else size_64K_hashed_tid0_addr when mmucr2(20 to 23)=TLB_PgSize_64KB + else size_4K_hashed_tid0_addr; +tlb_hashed_addr4 <= size_1G_hashed_addr when mmucr2(16 to 19)=TLB_PgSize_1GB + else size_16M_hashed_addr when mmucr2(16 to 19)=TLB_PgSize_16MB + else size_1M_hashed_addr when mmucr2(16 to 19)=TLB_PgSize_1MB + else size_64K_hashed_addr when mmucr2(16 to 19)=TLB_PgSize_64KB + else size_4K_hashed_addr; +tlb_hashed_tid0_addr4 <= size_1G_hashed_tid0_addr when mmucr2(16 to 19)=TLB_PgSize_1GB + else size_16M_hashed_tid0_addr when mmucr2(16 to 19)=TLB_PgSize_16MB + else size_1M_hashed_tid0_addr when mmucr2(16 to 19)=TLB_PgSize_1MB + else size_64K_hashed_tid0_addr when mmucr2(16 to 19)=TLB_PgSize_64KB + else size_4K_hashed_tid0_addr; +tlb_hashed_addr5 <= size_1G_hashed_addr when mmucr2(12 to 15)=TLB_PgSize_1GB + else size_16M_hashed_addr when mmucr2(12 to 15)=TLB_PgSize_16MB + else size_1M_hashed_addr when mmucr2(12 to 15)=TLB_PgSize_1MB + else size_64K_hashed_addr when mmucr2(12 to 15)=TLB_PgSize_64KB + else size_4K_hashed_addr; +tlb_hashed_tid0_addr5 <= size_1G_hashed_tid0_addr when mmucr2(12 to 15)=TLB_PgSize_1GB + else size_16M_hashed_tid0_addr when mmucr2(12 to 15)=TLB_PgSize_16MB + else size_1M_hashed_tid0_addr when mmucr2(12 to 15)=TLB_PgSize_1MB + else size_64K_hashed_tid0_addr when mmucr2(12 to 15)=TLB_PgSize_64KB + else size_4K_hashed_tid0_addr; +pgsize1_valid <= '1' when mmucr2(28 to 31) /= "0000" else '0'; +pgsize2_valid <= '1' when mmucr2(24 to 27) /= "0000" else '0'; +pgsize3_valid <= '1' when mmucr2(20 to 23) /= "0000" else '0'; +pgsize4_valid <= '1' when mmucr2(16 to 19) /= "0000" else '0'; +pgsize5_valid <= '1' when mmucr2(12 to 15) /= "0000" else '0'; +pgsize1_tid0_valid <= '1' when mmucr2(28 to 31) /= "0000" else '0'; +pgsize2_tid0_valid <= '1' when mmucr2(24 to 27) /= "0000" else '0'; +pgsize3_tid0_valid <= '1' when mmucr2(20 to 23) /= "0000" else '0'; +pgsize4_tid0_valid <= '1' when mmucr2(16 to 19) /= "0000" else '0'; +pgsize5_tid0_valid <= '1' when mmucr2(12 to 15) /= "0000" else '0'; +pgsize_qty <= "101" when (pgsize5_valid='1' and pgsize4_valid='1' and pgsize3_valid='1' and pgsize2_valid='1' and pgsize1_valid='1') + else "100" when (pgsize4_valid='1' and pgsize3_valid='1' and pgsize2_valid='1' and pgsize1_valid='1') + else "011" when (pgsize3_valid='1' and pgsize2_valid='1' and pgsize1_valid='1') + else "010" when (pgsize2_valid='1' and pgsize1_valid='1') + else "001" when (pgsize1_valid='1') + else "000"; +pgsize_tid0_qty <= "101" when (pgsize5_tid0_valid='1' and pgsize4_tid0_valid='1' and pgsize3_tid0_valid='1' and pgsize2_tid0_valid='1' and pgsize1_tid0_valid='1') + else "100" when (pgsize4_tid0_valid='1' and pgsize3_tid0_valid='1' and pgsize2_tid0_valid='1' and pgsize1_tid0_valid='1') + else "011" when (pgsize3_tid0_valid='1' and pgsize2_tid0_valid='1' and pgsize1_tid0_valid='1') + else "010" when (pgsize2_tid0_valid='1' and pgsize1_tid0_valid='1') + else "001" when (pgsize1_tid0_valid='1') + else "000"; +derat_taken_d <= '1' when derat_req_taken_sig='1' + else '0' when ierat_req_taken_sig <= '1' + else derat_taken_q; +tlb_read_req <= '1' when (ex1_valid_q(0 to 3) /= "0000" and ex1_ttype_q(0)='1') else '0'; +tlb_write_req <= '1' when (ex1_valid_q(0 to 3) /= "0000" and ex1_ttype_q(1)='1') else '0'; +tlb_search_req <= '1' when (ex2_valid_q(0 to 3) /= "0000" and ex2_ttype_q(2 to 3)/="00") else '0'; +tlb_searchresv_req <= '1' when (ex2_valid_q(0 to 3) /= "0000" and ex2_ttype_q(4)='1') else '0'; +tlb_seq_idle_sig <= '1' when tlb_seq_q=TlbSeq_Idle else '0'; +tlbwe_back_inv_holdoff <= tlbwe_back_inv_pending and mmucr1_tlbwe_binv; +tlb_seq_any_done_sig <= tlb_seq_ierat_done_sig or tlb_seq_derat_done_sig or tlb_seq_snoop_done_sig or + tlb_seq_search_done_sig or tlb_seq_searchresv_done_sig or tlb_seq_read_done_sig or + tlb_seq_write_done_sig or tlb_seq_ptereload_done_sig; +any_tlb_req_sig <= snoop_val_q(0) or ptereload_req_valid or tlb_seq_ierat_req or tlb_seq_derat_req or + tlb_search_req or tlb_searchresv_req or tlb_write_req or tlb_read_req; +any_req_taken_sig <= ierat_req_taken_sig or derat_req_taken_sig or snoop_req_taken_sig or + search_req_taken_sig or searchresv_req_taken_sig or read_req_taken_sig or + write_req_taken_sig or ptereload_req_taken_sig; +tlb_tag4_hit_or_parerr <= tlb_tag4_cmp_hit or tlb_tag4_parerr; +tlb_seq_abort <= or_reduce( tlb_tag0_q(tagpos_thdid to tagpos_thdid+thdid_width-1) + and (tlb_ctl_tag1_flush_sig or tlb_ctl_tag2_flush_sig or tlb_ctl_tag3_flush_sig or tlb_ctl_tag4_flush_sig) ); +tlb_seq_d <= tlb_seq_next and (0 to 5 => not(tlb_seq_abort)); +Tlb_Sequencer: PROCESS (tlb_seq_q, tlb_tag0_q(tagpos_is+1 to tagpos_is+3), tlb_tag0_q(tagpos_size to tagpos_size+3), tlb_tag0_q(tagpos_type to tagpos_type+7), + tlb_tag0_q(tagpos_type to tagpos_type+7), tlb_tag1_q(tagpos_endflag), tlb_tag0_tid_notzero, + tlb_tag4_hit_or_parerr, tlb_tag4_way_ind, tlb_addr_maxcntm1, tlb_cmp_erat_dup_wait, + tlb_seq_ierat_req, tlb_seq_derat_req, tlb_search_req, tlb_searchresv_req, + snoop_val_q(0), tlb_read_req, tlb_write_req, ptereload_req_valid, mmucr2(12 to 31), derat_taken_q, + tlb_hashed_addr1, tlb_hashed_addr2, tlb_hashed_addr3, tlb_hashed_addr4, tlb_hashed_addr5, + tlb_hashed_tid0_addr1, tlb_hashed_tid0_addr2, tlb_hashed_tid0_addr3, tlb_hashed_tid0_addr4, tlb_hashed_tid0_addr5, + pgsize2_valid, pgsize3_valid, pgsize4_valid, pgsize5_valid, + pgsize2_tid0_valid, pgsize3_tid0_valid, pgsize4_tid0_valid, pgsize5_tid0_valid, + size_1M_hashed_addr,size_1M_hashed_tid0_addr,size_256M_hashed_addr,size_256M_hashed_tid0_addr, + tlb_tag0_hashed_addr, tlb_tag0_hashed_tid0_addr, tlb0cfg_ind, tlbwe_back_inv_holdoff) +BEGIN +tlb_seq_addr <= (others => '0'); +tlb_seq_pgsize <= mmucr2(28 to 31); +tlb_seq_ind <= '0'; +tlb_seq_esel <= (others => '0'); +tlb_seq_is <= (others => '0'); +tlb_seq_tag0_addr_cap <= '0'; +tlb_seq_addr_update <= '0'; +tlb_seq_addr_clr <= '0'; +tlb_seq_addr_incr <= '0'; +tlb_seq_lrat_enable <= '0'; +tlb_seq_endflag <= '0'; +tlb_seq_ierat_done_sig <= '0'; +tlb_seq_derat_done_sig <= '0'; +tlb_seq_snoop_done_sig <= '0'; +tlb_seq_search_done_sig <= '0'; +tlb_seq_searchresv_done_sig <= '0'; +tlb_seq_read_done_sig <= '0'; +tlb_seq_write_done_sig <= '0'; +tlb_seq_ptereload_done_sig <= '0'; +ierat_req_taken_sig <= '0'; +derat_req_taken_sig <= '0'; +search_req_taken_sig <= '0'; +searchresv_req_taken_sig <= '0'; +snoop_req_taken_sig <= '0'; +read_req_taken_sig <= '0'; +write_req_taken_sig <= '0'; +ptereload_req_taken_sig <= '0'; +tlb_seq_set_resv <= '0'; +tlb_seq_snoop_resv <= '0'; +CASE tlb_seq_q IS + WHEN TlbSeq_Idle => + if snoop_val_q(0)='1' then + tlb_seq_next <= TlbSeq_Stg24; snoop_req_taken_sig <= '1'; + elsif ptereload_req_valid='1' then + tlb_seq_next <= TlbSeq_Stg19; ptereload_req_taken_sig <= '1'; + elsif tlb_seq_ierat_req='1' and tlb_cmp_erat_dup_wait(0)='0' and (derat_taken_q='1' or tlb_seq_derat_req='0') then + tlb_seq_next <= TlbSeq_Stg1; ierat_req_taken_sig <= '1'; + elsif tlb_seq_derat_req='1' and tlb_cmp_erat_dup_wait(1)='0' then + tlb_seq_next <= TlbSeq_Stg1; derat_req_taken_sig <= '1'; + elsif tlb_search_req='1' then + tlb_seq_next <= TlbSeq_Stg1; search_req_taken_sig <= '1'; + elsif tlb_searchresv_req='1' then + tlb_seq_next <= TlbSeq_Stg1; searchresv_req_taken_sig <= '1'; + elsif (tlb_write_req='1' and tlbwe_back_inv_holdoff='0') then + tlb_seq_next <= TlbSeq_Stg19; write_req_taken_sig <= '1'; + elsif tlb_read_req='1' then + tlb_seq_next <= TlbSeq_Stg19; read_req_taken_sig <= '1'; + else + tlb_seq_next <= TlbSeq_Idle; + end if; + WHEN TlbSeq_Stg1 => + tlb_seq_tag0_addr_cap <= '1'; + tlb_seq_addr_update <= '1'; + tlb_seq_addr <= tlb_hashed_addr1; + tlb_seq_pgsize <= mmucr2(28 to 31); + tlb_seq_is <= "00"; + tlb_seq_esel <= "001"; + if pgsize2_valid='1' then + tlb_seq_next <= TlbSeq_Stg2; + else + tlb_seq_next <= TlbSeq_Stg6; + end if; + + WHEN TlbSeq_Stg2 => + tlb_seq_addr_update <= '1'; + tlb_seq_addr <= tlb_hashed_addr2; + tlb_seq_pgsize <= mmucr2(24 to 27); + tlb_seq_is <= "00"; + tlb_seq_esel <= "010"; + if pgsize3_valid='1' then + tlb_seq_next <= TlbSeq_Stg3; + else + tlb_seq_next <= TlbSeq_Stg6; + end if; + + WHEN TlbSeq_Stg3 => + tlb_seq_addr_update <= '1'; + tlb_seq_addr <= tlb_hashed_addr3; + tlb_seq_pgsize <= mmucr2(20 to 23); + tlb_seq_is <= "00"; + tlb_seq_esel <= "011"; + if pgsize4_valid='1' then + tlb_seq_next <= TlbSeq_Stg4; + else + tlb_seq_next <= TlbSeq_Stg6; + end if; + + WHEN TlbSeq_Stg4 => + tlb_seq_addr_update <= '1'; + tlb_seq_addr <= tlb_hashed_addr4; + tlb_seq_pgsize <= mmucr2(16 to 19); + tlb_seq_is <= "00"; + tlb_seq_esel <= "100"; + if pgsize5_valid='1' then + tlb_seq_next <= TlbSeq_Stg5; + else + tlb_seq_next <= TlbSeq_Stg6; + end if; + + WHEN TlbSeq_Stg5 => + tlb_seq_addr_update <= '1'; + tlb_seq_addr <= tlb_hashed_addr5; + tlb_seq_pgsize <= mmucr2(12 to 15); + tlb_seq_is <= "00"; + tlb_seq_esel <= "101"; + if tlb_tag4_hit_or_parerr='1' and or_reduce(tlb_tag0_q(tagpos_type_tlbsx to tagpos_type_tlbsrx))='1' then + tlb_seq_next <= TlbSeq_Stg30; + elsif tlb_tag4_hit_or_parerr='1' and tlb_tag4_way_ind='0' then + tlb_seq_next <= TlbSeq_Stg31; + else + tlb_seq_next <= TlbSeq_Stg6; + end if; + WHEN TlbSeq_Stg6 => + tlb_seq_addr_update <= '1'; + tlb_seq_addr <= tlb_hashed_tid0_addr1; + tlb_seq_pgsize <= mmucr2(28 to 31); + tlb_seq_is <= "01"; + tlb_seq_esel <= "001"; + if tlb_tag4_hit_or_parerr='1' and or_reduce(tlb_tag0_q(tagpos_type_tlbsx to tagpos_type_tlbsrx))='1' then + tlb_seq_next <= TlbSeq_Stg30; + elsif tlb_tag4_hit_or_parerr='1' and tlb_tag4_way_ind='0' then + tlb_seq_next <= TlbSeq_Stg31; + elsif pgsize2_tid0_valid='1' then + tlb_seq_next <= TlbSeq_Stg7; + elsif tlb0cfg_ind='1' then + tlb_seq_next <= TlbSeq_Stg11; + else + tlb_seq_endflag <= '1'; + tlb_seq_next <= TlbSeq_Stg15; + end if; + + WHEN TlbSeq_Stg7 => + tlb_seq_addr_update <= '1'; + tlb_seq_addr <= tlb_hashed_tid0_addr2; + tlb_seq_pgsize <= mmucr2(24 to 27); + tlb_seq_is <= "01"; + tlb_seq_esel <= "010"; + if tlb_tag4_hit_or_parerr='1' and or_reduce(tlb_tag0_q(tagpos_type_tlbsx to tagpos_type_tlbsrx))='1' then + tlb_seq_next <= TlbSeq_Stg30; + elsif tlb_tag4_hit_or_parerr='1' and tlb_tag4_way_ind='0' then + tlb_seq_next <= TlbSeq_Stg31; + elsif pgsize3_tid0_valid='1' then + tlb_seq_next <= TlbSeq_Stg8; + elsif tlb0cfg_ind='1' then + tlb_seq_next <= TlbSeq_Stg11; + else + tlb_seq_endflag <= '1'; + tlb_seq_next <= TlbSeq_Stg15; + end if; + + WHEN TlbSeq_Stg8 => + tlb_seq_addr_update <= '1'; + tlb_seq_addr <= tlb_hashed_tid0_addr3; + tlb_seq_pgsize <= mmucr2(20 to 23); + tlb_seq_is <= "01"; + tlb_seq_esel <= "011"; + if tlb_tag4_hit_or_parerr='1' and or_reduce(tlb_tag0_q(tagpos_type_tlbsx to tagpos_type_tlbsrx))='1' then + tlb_seq_next <= TlbSeq_Stg30; + elsif tlb_tag4_hit_or_parerr='1' and tlb_tag4_way_ind='0' then + tlb_seq_next <= TlbSeq_Stg31; + elsif pgsize4_tid0_valid='1' then + tlb_seq_next <= TlbSeq_Stg9; + elsif tlb0cfg_ind='1' then + tlb_seq_next <= TlbSeq_Stg11; + else + tlb_seq_endflag <= '1'; + tlb_seq_next <= TlbSeq_Stg15; + end if; + + + WHEN TlbSeq_Stg9 => + tlb_seq_addr_update <= '1'; + tlb_seq_addr <= tlb_hashed_tid0_addr4; + tlb_seq_pgsize <= mmucr2(16 to 19); + tlb_seq_is <= "01"; + tlb_seq_esel <= "100"; + if tlb_tag4_hit_or_parerr='1' and or_reduce(tlb_tag0_q(tagpos_type_tlbsx to tagpos_type_tlbsrx))='1' then + tlb_seq_next <= TlbSeq_Stg30; + elsif tlb_tag4_hit_or_parerr='1' and tlb_tag4_way_ind='0' then + tlb_seq_next <= TlbSeq_Stg31; + elsif pgsize5_tid0_valid='1' then + tlb_seq_next <= TlbSeq_Stg10; + elsif tlb0cfg_ind='1' then + tlb_seq_next <= TlbSeq_Stg11; + else + tlb_seq_endflag <= '1'; + tlb_seq_next <= TlbSeq_Stg15; + end if; + + + WHEN TlbSeq_Stg10 => + tlb_seq_addr_update <= '1'; + tlb_seq_addr <= tlb_hashed_tid0_addr5; + tlb_seq_pgsize <= mmucr2(12 to 15); + tlb_seq_is <= "01"; + tlb_seq_esel <= "101"; + if tlb_tag4_hit_or_parerr='1' and or_reduce(tlb_tag0_q(tagpos_type_tlbsx to tagpos_type_tlbsrx))='1' then + tlb_seq_next <= TlbSeq_Stg30; + elsif tlb_tag4_hit_or_parerr='1' and tlb_tag4_way_ind='0' then + tlb_seq_next <= TlbSeq_Stg31; + elsif tlb0cfg_ind='1' then + tlb_seq_next <= TlbSeq_Stg11; + else + tlb_seq_endflag <= '1'; + tlb_seq_next <= TlbSeq_Stg15; + end if; + + WHEN TlbSeq_Stg11 => + tlb_seq_ind <= '1'; + tlb_seq_addr_update <= '1'; + tlb_seq_addr <= size_1M_hashed_addr; + tlb_seq_pgsize <= TLB_PgSize_1MB; + tlb_seq_is <= "10"; + tlb_seq_esel <= "001"; + if tlb_tag4_hit_or_parerr='1' and or_reduce(tlb_tag0_q(tagpos_type_tlbsx to tagpos_type_tlbsrx))='1' then + tlb_seq_next <= TlbSeq_Stg30; + elsif tlb_tag4_hit_or_parerr='1' and tlb_tag4_way_ind='0' then + tlb_seq_next <= TlbSeq_Stg31; + else + tlb_seq_next <= TlbSeq_Stg12; + end if; + + WHEN TlbSeq_Stg12 => + tlb_seq_ind <= '1'; + tlb_seq_addr_update <= '1'; + tlb_seq_addr <= size_256M_hashed_addr; + tlb_seq_pgsize <= TLB_PgSize_256MB; + tlb_seq_is <= "10"; + tlb_seq_esel <= "010"; + if tlb_tag4_hit_or_parerr='1' and or_reduce(tlb_tag0_q(tagpos_type_tlbsx to tagpos_type_tlbsrx))='1' then + tlb_seq_next <= TlbSeq_Stg30; + elsif tlb_tag4_hit_or_parerr='1' and tlb_tag4_way_ind='0' then + tlb_seq_next <= TlbSeq_Stg31; + else + tlb_seq_next <= TlbSeq_Stg13; + end if; + + WHEN TlbSeq_Stg13 => + tlb_seq_ind <= '1'; + tlb_seq_addr_update <= '1'; + tlb_seq_addr <= size_1M_hashed_tid0_addr; + tlb_seq_pgsize <= TLB_PgSize_1MB; + tlb_seq_is <= "11"; + tlb_seq_esel <= "001"; + if tlb_tag4_hit_or_parerr='1' and or_reduce(tlb_tag0_q(tagpos_type_tlbsx to tagpos_type_tlbsrx))='1' then + tlb_seq_next <= TlbSeq_Stg30; + elsif tlb_tag4_hit_or_parerr='1' and tlb_tag4_way_ind='0' then + tlb_seq_next <= TlbSeq_Stg31; + else + tlb_seq_next <= TlbSeq_Stg14; + end if; + + WHEN TlbSeq_Stg14 => + tlb_seq_ind <= '1'; + tlb_seq_addr_update <= '1'; + tlb_seq_addr <= size_256M_hashed_tid0_addr; + tlb_seq_pgsize <= TLB_PgSize_256MB; + tlb_seq_is <= "11"; + tlb_seq_esel <= "010"; + if tlb_tag4_hit_or_parerr='1' and or_reduce(tlb_tag0_q(tagpos_type_tlbsx to tagpos_type_tlbsrx))='1' then + tlb_seq_next <= TlbSeq_Stg30; + elsif tlb_tag4_hit_or_parerr='1' and tlb_tag4_way_ind='0' then + tlb_seq_next <= TlbSeq_Stg31; + else + tlb_seq_endflag <= '1'; + tlb_seq_next <= TlbSeq_Stg15; + end if; + + WHEN TlbSeq_Stg15 => + tlb_seq_addr <= (others => '0'); + tlb_seq_pgsize <= (others => '0'); + if tlb_tag4_hit_or_parerr='1' and or_reduce(tlb_tag0_q(tagpos_type_tlbsx to tagpos_type_tlbsrx))='1' then + tlb_seq_next <= TlbSeq_Stg30; + elsif tlb_tag4_hit_or_parerr='1' and tlb_tag4_way_ind='0' then + tlb_seq_next <= TlbSeq_Stg31; + elsif tlb_tag4_hit_or_parerr='1' and tlb_tag4_way_ind='1' and + or_reduce(tlb_tag0_q(tagpos_type_derat to tagpos_type_ierat))='1' and tlb_tag0_q(tagpos_type_ptereload)='0' then + tlb_seq_next <= TlbSeq_Stg29; + else + tlb_seq_next <= TlbSeq_Stg16; + end if; + + WHEN TlbSeq_Stg16 => + tlb_seq_addr <= (others => '0'); + tlb_seq_pgsize <= (others => '0'); + if tlb_tag4_hit_or_parerr='1' and or_reduce(tlb_tag0_q(tagpos_type_tlbsx to tagpos_type_tlbsrx))='1' then + tlb_seq_next <= TlbSeq_Stg30; + elsif tlb_tag4_hit_or_parerr='1' and tlb_tag4_way_ind='0' then + tlb_seq_next <= TlbSeq_Stg31; + elsif tlb_tag4_hit_or_parerr='1' and tlb_tag4_way_ind='1' then + tlb_seq_next <= TlbSeq_Stg29; + else + tlb_seq_next <= TlbSeq_Stg17; + end if; + + WHEN TlbSeq_Stg17 => + tlb_seq_addr <= (others => '0'); + tlb_seq_pgsize <= (others => '0'); + if tlb_tag4_hit_or_parerr='1' and or_reduce(tlb_tag0_q(tagpos_type_tlbsx to tagpos_type_tlbsrx))='1' then + tlb_seq_next <= TlbSeq_Stg30; + elsif tlb_tag4_hit_or_parerr='1' and tlb_tag4_way_ind='0' then + tlb_seq_next <= TlbSeq_Stg31; + elsif tlb_tag4_hit_or_parerr='1' and tlb_tag4_way_ind='1' then + tlb_seq_next <= TlbSeq_Stg29; + else + tlb_seq_next <= TlbSeq_Stg18; + end if; + + WHEN TlbSeq_Stg18 => + tlb_seq_addr <= (others => '0'); + tlb_seq_pgsize <= (others => '0'); + if tlb_tag4_hit_or_parerr='1' and or_reduce(tlb_tag0_q(tagpos_type_tlbsx to tagpos_type_tlbsrx))='1' then + tlb_seq_next <= TlbSeq_Stg30; + elsif tlb_tag4_hit_or_parerr='1' and tlb_tag4_way_ind='0' then + tlb_seq_next <= TlbSeq_Stg31; + elsif tlb_tag4_hit_or_parerr='1' and tlb_tag4_way_ind='1' then + tlb_seq_next <= TlbSeq_Stg29; + else + tlb_seq_next <= TlbSeq_Stg30; + end if; + + WHEN TlbSeq_Stg19 => + tlb_seq_pgsize <= tlb_tag0_q(tagpos_size to tagpos_size+3); + tlb_seq_tag0_addr_cap <= '1'; + tlb_seq_addr_update <= '1'; + if tlb_tag0_tid_notzero='1' then + tlb_seq_addr <= tlb_tag0_hashed_addr; + else + tlb_seq_addr <= tlb_tag0_hashed_tid0_addr; + end if; + tlb_seq_next <= TlbSeq_Stg20; + + WHEN TlbSeq_Stg20 => + tlb_seq_addr <= (others => '0'); + tlb_seq_pgsize <= (others => '0'); + tlb_seq_next <= TlbSeq_Stg21; + + WHEN TlbSeq_Stg21 => + tlb_seq_lrat_enable <= tlb_tag0_q(tagpos_type_tlbwe) or tlb_tag0_q(tagpos_type_ptereload); + tlb_seq_addr <= (others => '0'); + tlb_seq_pgsize <= (others => '0'); + tlb_seq_next <= TlbSeq_Stg22; + + WHEN TlbSeq_Stg22 => + tlb_seq_addr <= (others => '0'); + tlb_seq_pgsize <= (others => '0'); + tlb_seq_next <= TlbSeq_Stg23; + + WHEN TlbSeq_Stg23 => + tlb_seq_addr <= (others => '0'); + tlb_seq_pgsize <= (others => '0'); + tlb_seq_read_done_sig <= tlb_tag0_q(tagpos_type_tlbre); + tlb_seq_write_done_sig <= tlb_tag0_q(tagpos_type_tlbwe); + tlb_seq_ptereload_done_sig <= tlb_tag0_q(tagpos_type_ptereload); + if tlb_tag0_q(tagpos_type_tlbre)='1' or tlb_tag0_q(tagpos_type_tlbwe)='1' then + tlb_seq_next <= TlbSeq_Idle; + else + tlb_seq_next <= TlbSeq_Stg31; + end if; + + + WHEN TlbSeq_Stg24 => + tlb_seq_pgsize <= tlb_tag0_q(tagpos_size to tagpos_size+3); + tlb_seq_tag0_addr_cap <= '1'; + tlb_seq_snoop_resv <= '1'; + if (tlb_tag0_q(tagpos_is+1 to tagpos_is+3)="011") then + tlb_seq_addr_update <= '1'; + tlb_seq_addr_clr <= '0'; + tlb_seq_endflag <= '1'; + else + tlb_seq_addr_update <= '0'; + tlb_seq_addr_clr <= '1'; + tlb_seq_endflag <= '0'; + end if; + if tlb_tag0_tid_notzero='1' then + tlb_seq_addr <= tlb_tag0_hashed_addr; + else + tlb_seq_addr <= tlb_tag0_hashed_tid0_addr; + end if; + tlb_seq_next <= TlbSeq_Stg25; + + WHEN TlbSeq_Stg25 => + tlb_seq_addr <= (others => '0'); + tlb_seq_pgsize <= (others => '0'); + if (tlb_tag0_q(tagpos_is+1 to tagpos_is+3)="011") then + tlb_seq_addr_incr <= '0'; + tlb_seq_endflag <= '0'; + else + tlb_seq_addr_incr <= '1'; + tlb_seq_endflag <= tlb_addr_maxcntm1; + end if; + if tlb_tag0_q(tagpos_is+1 to tagpos_is+3)/="011" and tlb_tag1_q(tagpos_endflag)='0' then + tlb_seq_next <= TlbSeq_Stg25; + else + tlb_seq_next <= TlbSeq_Stg26; + end if; + + WHEN TlbSeq_Stg26 => + tlb_seq_addr <= (others => '0'); + tlb_seq_pgsize <= (others => '0'); + tlb_seq_next <= TlbSeq_Stg27; + + WHEN TlbSeq_Stg27 => + tlb_seq_addr <= (others => '0'); + tlb_seq_pgsize <= (others => '0'); + tlb_seq_next <= TlbSeq_Stg28; + + WHEN TlbSeq_Stg28 => + tlb_seq_addr <= (others => '0'); + tlb_seq_pgsize <= (others => '0'); + tlb_seq_next <= TlbSeq_Stg31; + WHEN TlbSeq_Stg29 => + tlb_seq_derat_done_sig <= tlb_tag0_q(tagpos_type_derat) and not tlb_tag0_q(tagpos_type_ptereload); + tlb_seq_ierat_done_sig <= tlb_tag0_q(tagpos_type_ierat) and not tlb_tag0_q(tagpos_type_ptereload); + tlb_seq_addr <= (others => '0'); + tlb_seq_pgsize <= (others => '0'); + tlb_seq_next <= TlbSeq_Idle; + + WHEN TlbSeq_Stg30 => + tlb_seq_addr <= (others => '0'); + tlb_seq_pgsize <= (others => '0'); + tlb_seq_derat_done_sig <= tlb_tag0_q(tagpos_type_derat) and not tlb_tag0_q(tagpos_type_ptereload); + tlb_seq_ierat_done_sig <= tlb_tag0_q(tagpos_type_ierat) and not tlb_tag0_q(tagpos_type_ptereload); + tlb_seq_search_done_sig <= tlb_tag0_q(tagpos_type_tlbsx); + tlb_seq_searchresv_done_sig <= tlb_tag0_q(tagpos_type_tlbsrx); + tlb_seq_snoop_done_sig <= tlb_tag0_q(tagpos_type_snoop); + tlb_seq_set_resv <= tlb_tag0_q(tagpos_type_tlbsrx); + + tlb_seq_next <= TlbSeq_Idle; + + + WHEN TlbSeq_Stg31 => + tlb_seq_addr <= (others => '0'); + tlb_seq_pgsize <= (others => '0'); + tlb_seq_derat_done_sig <= tlb_tag0_q(tagpos_type_derat) and not tlb_tag0_q(tagpos_type_ptereload); + tlb_seq_ierat_done_sig <= tlb_tag0_q(tagpos_type_ierat) and not tlb_tag0_q(tagpos_type_ptereload); + tlb_seq_search_done_sig <= tlb_tag0_q(tagpos_type_tlbsx); + tlb_seq_searchresv_done_sig <= tlb_tag0_q(tagpos_type_tlbsrx); + tlb_seq_snoop_done_sig <= tlb_tag0_q(tagpos_type_snoop); + tlb_seq_set_resv <= tlb_tag0_q(tagpos_type_tlbsrx); + + if (tlb_tag0_q(tagpos_type_ierat)='1' or tlb_tag0_q(tagpos_type_derat)='1' + or tlb_tag0_q(tagpos_type_ptereload)='1') then + tlb_seq_next <= TlbSeq_Stg32; + else + tlb_seq_next <= TlbSeq_Idle; + end if; + + WHEN TlbSeq_Stg32 => + tlb_seq_addr <= (others => '0'); + tlb_seq_pgsize <= (others => '0'); + tlb_seq_next <= TlbSeq_Idle; + + WHEN OTHERS => + tlb_seq_next <= TlbSeq_Idle; + + END CASE; +END PROCESS Tlb_Sequencer; +ierat_req_taken <= ierat_req_taken_sig; +derat_req_taken <= derat_req_taken_sig; +tlb_seq_ierat_done <= tlb_seq_ierat_done_sig; +tlb_seq_derat_done <= tlb_seq_derat_done_sig; +ptereload_req_taken <= ptereload_req_taken_sig; +tlb_seq_idle <= tlb_seq_idle_sig; +snoop_val_d(0) <= tlb_snoop_val when snoop_val_q(0)='0' + else '0' when snoop_req_taken_sig='1' + else snoop_val_q(0); +snoop_val_d(1) <= tlb_seq_snoop_done_sig; +tlb_snoop_ack <= snoop_val_q(1); +snoop_attr_d <= tlb_snoop_attr when snoop_val_q(0)='0' + else snoop_attr_q; +snoop_vpn_d(52-epn_width TO 51) <= tlb_snoop_vpn when snoop_val_q(0)='0' + else snoop_vpn_q(52-epn_width to 51); +ptereload_req_pte_d <= ptereload_req_pte when ptereload_req_taken_sig='1' + else ptereload_req_pte_q; +ptereload_req_pte_lat <= ptereload_req_pte_q; +tlb_ctl_tag1_flush_sig <= ex3_flush_q when (tlb_tag0_q(tagpos_type_tlbre)='1' or tlb_tag0_q(tagpos_type_tlbwe)='1') + else ex4_flush_q when (tlb_tag0_q(tagpos_type_tlbsx)='1' or tlb_tag0_q(tagpos_type_tlbsrx)='1') + else (others => '0'); +tlb_ctl_tag2_flush_sig <= ex4_flush_q when (tlb_tag0_q(tagpos_type_tlbre)='1' or tlb_tag0_q(tagpos_type_tlbwe)='1') + else ex5_flush_q when (tlb_tag0_q(tagpos_type_tlbsx)='1' or tlb_tag0_q(tagpos_type_tlbsrx)='1') + else (others => '0'); +tlb_ctl_tag3_flush_sig <= ex5_flush_q when (tlb_tag0_q(tagpos_type_tlbre)='1' or tlb_tag0_q(tagpos_type_tlbwe)='1') + else ex6_flush_q when (tlb_tag0_q(tagpos_type_tlbsx)='1' or tlb_tag0_q(tagpos_type_tlbsrx)='1') + else (others => '0'); +tlb_ctl_tag4_flush_sig <= ex6_flush_q when (tlb_tag0_q(tagpos_type_tlbre)='1' or tlb_tag0_q(tagpos_type_tlbwe)='1') + else (others => '0'); +tlb_ctl_any_tag_flush_sig <= or_reduce(tlb_ctl_tag1_flush_sig or tlb_ctl_tag2_flush_sig or tlb_ctl_tag3_flush_sig or tlb_ctl_tag4_flush_sig); +tlb_ctl_tag2_flush <= tlb_ctl_tag2_flush_sig or tlb_ctl_tag3_flush_sig or tlb_ctl_tag4_flush_sig; +tlb_ctl_tag3_flush <= tlb_ctl_tag3_flush_sig or tlb_ctl_tag4_flush_sig; +tlb_ctl_tag4_flush <= tlb_ctl_tag4_flush_sig; +tlb_tag0_d(tagpos_type_derat) <= (derat_req_taken_sig) + or (ptereload_req_tag(tagpos_type_derat) and ptereload_req_taken_sig) + or (tlb_tag0_q(tagpos_type_derat) and not tlb_seq_any_done_sig and not tlb_seq_abort); +tlb_tag0_d(tagpos_type_ierat) <= (ierat_req_taken_sig) + or (ptereload_req_tag(tagpos_type_ierat) and ptereload_req_taken_sig) + or (tlb_tag0_q(tagpos_type_ierat) and not tlb_seq_any_done_sig and not tlb_seq_abort); +tlb_tag0_d(tagpos_type_tlbsx) <= (search_req_taken_sig) + or (tlb_tag0_q(tagpos_type_tlbsx) and not tlb_seq_any_done_sig and not tlb_seq_abort); +tlb_tag0_d(tagpos_type_tlbsrx) <= (searchresv_req_taken_sig) + or (tlb_tag0_q(tagpos_type_tlbsrx) and not tlb_seq_any_done_sig and not tlb_seq_abort); +tlb_tag0_d(tagpos_type_snoop) <= (snoop_req_taken_sig) + or (tlb_tag0_q(tagpos_type_snoop) and not tlb_seq_any_done_sig and not tlb_seq_abort); +tlb_tag0_d(tagpos_type_tlbre) <= (read_req_taken_sig) + or (tlb_tag0_q(tagpos_type_tlbre) and not tlb_seq_any_done_sig and not tlb_seq_abort); +tlb_tag0_d(tagpos_type_tlbwe) <= (write_req_taken_sig) + or (tlb_tag0_q(tagpos_type_tlbwe) and not tlb_seq_any_done_sig and not tlb_seq_abort); +tlb_tag0_d(tagpos_type_ptereload) <= (ptereload_req_taken_sig) + or (tlb_tag0_q(tagpos_type_ptereload) and not tlb_seq_any_done_sig and not tlb_seq_abort); +gen64_tag_epn: if rs_data_width = 64 generate +tlb_tag0_d(tagpos_epn TO tagpos_epn+epn_width-1) <= + ( ptereload_req_tag(tagpos_epn to tagpos_epn+epn_width-1) and (tagpos_epn to tagpos_epn+epn_width-1 => ptereload_req_taken_sig) ) + or ( ((ex1_mas2_epn(0 to 31) and (0 to 31 => ex1_state_q(3))) & ex1_mas2_epn(32 to epn_width-1)) and (tagpos_epn to tagpos_epn+epn_width-1 => write_req_taken_sig) ) + or ( ((ex1_mas2_epn(0 to 31) and (0 to 31 => ex1_state_q(3))) & ex1_mas2_epn(32 to epn_width-1)) and (tagpos_epn to tagpos_epn+epn_width-1 => read_req_taken_sig) ) + or ( snoop_vpn_q and (tagpos_epn to tagpos_epn+epn_width-1 => snoop_req_taken_sig) ) + or ( xu_mm_ex2_epn and (tagpos_epn to tagpos_epn+epn_width-1 => searchresv_req_taken_sig) ) + or ( xu_mm_ex2_epn and (tagpos_epn to tagpos_epn+epn_width-1 => search_req_taken_sig) ) + or ( ierat_req_epn and (tagpos_epn to tagpos_epn+epn_width-1 => ierat_req_taken_sig) ) + or ( derat_req_epn and (tagpos_epn to tagpos_epn+epn_width-1 => derat_req_taken_sig) ) + or ( tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-1) and (tagpos_epn to tagpos_epn+epn_width-1 => not any_req_taken_sig) ); +end generate gen64_tag_epn; +gen32_tag_epn: if rs_data_width = 32 generate +tlb_tag0_d(tagpos_epn TO tagpos_epn+epn_width-1) <= + ( ptereload_req_tag(tagpos_epn to tagpos_epn+epn_width-1) and (0 to epn_width-1 => ptereload_req_taken_sig) ) + or ( ex1_mas2_epn(52-epn_width to 51) and (0 to epn_width-1 => write_req_taken_sig) ) + or ( ex1_mas2_epn(52-epn_width to 51) and (0 to epn_width-1 => read_req_taken_sig) ) + or ( snoop_vpn_q(52-epn_width to 51) and (0 to epn_width-1 => snoop_req_taken_sig) ) + or ( xu_mm_ex2_epn(52-epn_width to 51) and (0 to epn_width-1 => searchresv_req_taken_sig) ) + or ( xu_mm_ex2_epn(52-epn_width to 51) and (0 to epn_width-1 => search_req_taken_sig) ) + or ( ierat_req_epn(52-epn_width to 51) and (0 to epn_width-1 => ierat_req_taken_sig) ) + or ( derat_req_epn(52-epn_width to 51) and (0 to epn_width-1 => derat_req_taken_sig) ) + or ( tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-1) and (0 to epn_width-1 => not any_req_taken_sig) ); +end generate gen32_tag_epn; +tlb_tag0_d(tagpos_pid TO tagpos_pid+pid_width-1) <= + ( ptereload_req_tag(tagpos_pid to tagpos_pid+pid_width-1) and (0 to pid_width-1 => ptereload_req_taken_sig) ) + or ( ex1_mas1_tid and (0 to pid_width-1 => write_req_taken_sig) ) + or ( ex1_mas1_tid and (0 to pid_width-1 => read_req_taken_sig) ) + or ( snoop_attr_q(20 to 25) & snoop_attr_q(6 to 13) and (0 to pid_width-1 => snoop_req_taken_sig) ) + or ( ex2_mas1_tid and (0 to pid_width-1 => searchresv_req_taken_sig) ) + or ( ex2_mas6_spid and (0 to pid_width-1 => search_req_taken_sig) ) + or ( ierat_req_pid and (0 to pid_width-1 => ierat_req_taken_sig) ) + or ( derat_req_pid and (0 to pid_width-1 => derat_req_taken_sig) ) + or ( tlb_tag0_q(tagpos_pid to tagpos_pid+pid_width-1) and (0 to pid_width-1 => not any_req_taken_sig) ); +tlb_tag0_d(tagpos_is TO tagpos_is+1) <= + ((ptereload_req_pte(ptepos_valid) & ptereload_req_tag(tagpos_is+1)) and (0 to 1 => ptereload_req_taken_sig)) + or ((ex1_mas1_v & ex1_mas1_iprot) and (0 to 1 => write_req_taken_sig)) + or (snoop_attr_q(0 to 1) and (0 to 1 => snoop_req_taken_sig)) + or (tlb_tag0_q(tagpos_is to tagpos_is+1) and (0 to 1 => not any_req_taken_sig)); +tlb_tag0_d(tagpos_class TO tagpos_class+1) <= + (ptereload_req_tag(tagpos_class to tagpos_class+1) and (0 to 1 => ptereload_req_taken_sig)) + or (ex1_mmucr3_class and (0 to 1 => write_req_taken_sig)) + or (snoop_attr_q(2 to 3) and (0 to 1 => snoop_req_taken_sig)) + or (derat_req_ttype and (0 to 1 => derat_req_taken_sig)) + or (tlb_tag0_q(tagpos_class to tagpos_class+1) and (0 to 1 => not any_req_taken_sig)); +tlb_tag0_d(tagpos_state TO tagpos_state+state_width-1) <= + (ptereload_req_tag(tagpos_state to tagpos_state+state_width-1) and (0 to state_width-1 => ptereload_req_taken_sig)) + or (ex1_state_q(0 to 3) and (0 to state_width-1 => write_req_taken_sig)) + or (ex1_state_q(0 to 3) and (0 to state_width-1 => read_req_taken_sig)) + or (('0' & snoop_attr_q(4 to 5) & '0') and (0 to state_width-1 => snoop_req_taken_sig)) + or (ex2_mas5_1_state and (0 to state_width-1 => searchresv_req_taken_sig)) + or (ex2_mas5_6_state and (0 to state_width-1 => search_req_taken_sig)) + or (ierat_req_state and (0 to state_width-1 => ierat_req_taken_sig)) + or (derat_req_state and (0 to state_width-1 => derat_req_taken_sig)) + or (tlb_tag0_q(tagpos_state to tagpos_state+state_width-1) and (0 to state_width-1 => not any_req_taken_sig)); +tlb_tag0_d(tagpos_thdid TO tagpos_thdid+thdid_width-1) <= + (ptereload_req_tag(tagpos_thdid to tagpos_thdid+thdid_width-1) and (0 to thdid_width-1 => ptereload_req_taken_sig)) + or (ex1_valid_q and (0 to thdid_width-1 => write_req_taken_sig)) + or (ex1_valid_q and (0 to thdid_width-1 => read_req_taken_sig)) + or ("1111" and (0 to thdid_width-1 => snoop_req_taken_sig)) + or (ex2_valid_q and (0 to thdid_width-1 => searchresv_req_taken_sig)) + or (ex2_valid_q and (0 to thdid_width-1 => search_req_taken_sig)) + or (ierat_req_thdid and (0 to thdid_width-1 => ierat_req_taken_sig)) + or (derat_req_thdid and (0 to thdid_width-1 => derat_req_taken_sig)) + or ( tlb_tag0_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag1_flush_sig) + and not(tlb_ctl_tag2_flush_sig) and not(tlb_ctl_tag3_flush_sig) and not(tlb_ctl_tag4_flush_sig) + and (0 to thdid_width-1 => (not tlb_seq_any_done_sig and not any_req_taken_sig and not tlb_seq_abort)) ); +tlb_tag0_d(tagpos_size TO tagpos_size+3) <= + (('0' & ptereload_req_pte(ptepos_size to ptepos_size+2)) and (0 to 3 => ptereload_req_taken_sig)) + or (ex1_mas1_tsize and (0 to 3 => write_req_taken_sig)) + or (ex1_mas1_tsize and (0 to 3 => read_req_taken_sig)) + or (snoop_attr_q(14 to 17) and (0 to 3 => snoop_req_taken_sig)) + or (mmucr2(28 to 31) and (0 to 3 => searchresv_req_taken_sig)) + or (mmucr2(28 to 31) and (0 to 3 => search_req_taken_sig)) + or (mmucr2(28 to 31) and (0 to 3 => ierat_req_taken_sig)) + or (mmucr2(28 to 31) and (0 to 3 => derat_req_taken_sig)) + or (tlb_tag0_q(tagpos_size to tagpos_size+3) and (0 to 3 => not any_req_taken_sig)); +tlb_tag0_d(tagpos_lpid TO tagpos_lpid+lpid_width-1) <= + (ptereload_req_tag(tagpos_lpid to tagpos_lpid+lpid_width-1) and (0 to lpid_width-1 => ptereload_req_taken_sig)) + or (ex1_mas8_tlpid and (0 to lpid_width-1 => write_req_taken_sig)) + or (ex1_mas8_tlpid and (0 to lpid_width-1 => read_req_taken_sig)) + or (snoop_attr_q(26 to 33) and (0 to lpid_width-1 => snoop_req_taken_sig)) + or (ex2_mas5_slpid and (0 to lpid_width-1 => searchresv_req_taken_sig)) + or (ex2_mas5_slpid and (0 to lpid_width-1 => search_req_taken_sig)) + or (lpidr and (0 to lpid_width-1 => ierat_req_taken_sig)) + or (derat_req_lpid and (0 to lpid_width-1 => derat_req_taken_sig)) + or (tlb_tag0_q(tagpos_lpid to tagpos_lpid+lpid_width-1) and (0 to lpid_width-1 => not any_req_taken_sig)); +tlb_tag0_d(tagpos_ind) <= + (ex1_mas1_ind and write_req_taken_sig) + or (ex1_mas1_ind and read_req_taken_sig) + or (snoop_attr_q(34) and snoop_req_taken_sig) + or (ex2_mas1_ind and searchresv_req_taken_sig) + or (ex2_mas6_sind and search_req_taken_sig) + or (tlb_tag0_q(tagpos_ind) and not any_req_taken_sig); +tlb_tag0_d(tagpos_atsel) <= + (ptereload_req_tag(tagpos_atsel) and ptereload_req_taken_sig) + or (ex1_mas0_atsel and write_req_taken_sig) + or (ex1_mas0_atsel and read_req_taken_sig) + or (ex2_mas0_atsel and searchresv_req_taken_sig) + or (ex2_mas0_atsel and search_req_taken_sig) + or (tlb_tag0_q(tagpos_atsel) and not any_req_taken_sig); +tlb_tag0_d(tagpos_esel TO tagpos_esel+2) <= + (ptereload_req_tag(tagpos_esel to tagpos_esel+2) and (0 to 2 => ptereload_req_taken_sig)) + or (ex1_mas0_esel and (0 to 2 => write_req_taken_sig)) + or (ex1_mas0_esel and (0 to 2 => read_req_taken_sig)) + or (ex2_mas0_esel and (0 to 2 => searchresv_req_taken_sig)) + or (ex2_mas0_esel and (0 to 2 => search_req_taken_sig)) + or (tlb_tag0_q(tagpos_esel to tagpos_esel+2) and (0 to 2 => not any_req_taken_sig)); +tlb_tag0_d(tagpos_hes) <= + (ptereload_req_tag(tagpos_hes) and ptereload_req_taken_sig) + or (ex1_mas0_hes and write_req_taken_sig) + or (ex1_mas0_hes and read_req_taken_sig) + or (snoop_attr_q(19) and snoop_req_taken_sig) + or (ex2_mas0_hes and searchresv_req_taken_sig) + or (ex2_mas0_hes and search_req_taken_sig) + or (ierat_req_taken_sig) + or (derat_req_taken_sig) + or (tlb_tag0_q(tagpos_hes) and not any_req_taken_sig); +tlb_tag0_d(tagpos_wq TO tagpos_wq+1) <= + (ptereload_req_tag(tagpos_wq to tagpos_wq+1) and (0 to 1 => ptereload_req_taken_sig)) + or (ex1_mas0_wq and (0 to 1 => write_req_taken_sig)) + or (ex1_mas0_wq and (0 to 1 => read_req_taken_sig)) + or (ex2_mas0_wq and (0 to 1 => searchresv_req_taken_sig)) + or (ex2_mas0_wq and (0 to 1 => search_req_taken_sig)) + or (ierat_req_dup and (0 to 1 => ierat_req_taken_sig)) + or (derat_req_dup and (0 to 1 => derat_req_taken_sig)) + or (tlb_tag0_q(tagpos_wq to tagpos_wq+1) and (0 to 1 => not any_req_taken_sig)); +tlb_tag0_d(tagpos_lrat) <= + (ptereload_req_tag(tagpos_lrat) and ptereload_req_taken_sig) + or (mmucfg_lrat and write_req_taken_sig) + or (mmucfg_lrat and read_req_taken_sig) + or (mmucfg_lrat and searchresv_req_taken_sig) + or (mmucfg_lrat and search_req_taken_sig) + or (mmucfg_lrat and ierat_req_taken_sig) + or (mmucfg_lrat and derat_req_taken_sig) + or (tlb_tag0_q(tagpos_lrat) and not any_req_taken_sig); +tlb_tag0_d(tagpos_pt) <= + (ptereload_req_tag(tagpos_pt) and ptereload_req_taken_sig) + or (ex1_mas8_tgs and write_req_taken_sig) + or (tlb0cfg_pt and read_req_taken_sig) + or (tlb0cfg_pt and searchresv_req_taken_sig) + or (tlb0cfg_pt and search_req_taken_sig) + or (tlb0cfg_pt and ierat_req_taken_sig) + or (tlb0cfg_pt and derat_req_taken_sig) + or (tlb_tag0_q(tagpos_pt) and not any_req_taken_sig); +tlb_tag0_d(tagpos_recform) <= + (ex1_mas1_ts and write_req_taken_sig) + or (searchresv_req_taken_sig) + or (ex2_ttype_q(3) and search_req_taken_sig) + or (tlb_tag0_q(tagpos_recform) and not any_req_taken_sig); +tlb_tag0_d(tagpos_endflag) <= '0'; +tlb_tag0_epn(52-epn_width TO 51) <= tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-1); +tlb_tag0_thdid <= tlb_tag0_q(tagpos_thdid to tagpos_thdid+thdid_width-1); +tlb_tag0_type <= tlb_tag0_q(tagpos_type to tagpos_type+7); +tlb_tag0_lpid <= tlb_tag0_q(tagpos_lpid to tagpos_lpid+lpid_width-1); +tlb_tag0_atsel <= tlb_tag0_q(tagpos_atsel); +tlb_tag0_size <= tlb_tag0_q(tagpos_size to tagpos_size+3); +tlb_tag0_addr_cap <= tlb_seq_tag0_addr_cap; +tlb_tag1_d(tagpos_epn TO tagpos_epn+epn_width-1) <= tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-1); +tlb_tag1_d(tagpos_pid TO tagpos_pid+pid_width-1) <= tlb_tag0_q(tagpos_pid to tagpos_pid+pid_width-1); +tlb_tag1_d(tagpos_is TO tagpos_is+1) <= ((0 to 1 => or_reduce(tlb_tag0_q(tagpos_type_derat to tagpos_type_tlbsrx)) and not tlb_tag0_q(tagpos_type_ptereload)) and tlb_seq_is) or + ((0 to 1 => or_reduce(tlb_tag0_q(tagpos_type_snoop to tagpos_type_ptereload))) and tlb_tag0_q(tagpos_is to tagpos_is+1)); +tlb_tag1_d(tagpos_class TO tagpos_class+1) <= tlb_tag0_q(tagpos_class to tagpos_class+1); +tlb_tag1_d(tagpos_state TO tagpos_state+state_width-1) <= tlb_tag0_q(tagpos_state to tagpos_state+state_width-1); +tlb_tag1_d(tagpos_thdid TO tagpos_thdid+thdid_width-1) <= + (others => '0') when + ( tlb_tag4_hit_or_parerr='1' and tlb_tag0_q(tagpos_type_ptereload)='0' and + (tlb_tag0_q(tagpos_type_ierat)='1' or tlb_tag0_q(tagpos_type_derat)='1' or + tlb_tag0_q(tagpos_type_tlbsx)='1' or tlb_tag0_q(tagpos_type_tlbsrx)='1') ) or + (tlb_tag4_endflag='1' and tlb_tag0_q(tagpos_type_snoop)='1') or + tlb_seq_any_done_sig ='1' or tlb_seq_abort='1' + else tlb_tag0_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag1_flush_sig) and + not(tlb_ctl_tag2_flush_sig) and not(tlb_ctl_tag3_flush_sig) and not(tlb_ctl_tag4_flush_sig); +tlb_tag1_d(tagpos_ind) <= (or_reduce(tlb_tag0_q(tagpos_type_derat to tagpos_type_ierat)) and tlb_seq_ind) or + (not or_reduce(tlb_tag0_q(tagpos_type_derat to tagpos_type_ierat)) and tlb_tag0_q(tagpos_ind)); +tlb_tag1_d(tagpos_esel TO tagpos_esel+2) <= ((0 to 2 => or_reduce(tlb_tag0_q(tagpos_type_derat to tagpos_type_tlbsrx)) and not tlb_tag0_q(tagpos_type_ptereload)) and tlb_seq_esel) or + ((0 to 2 => tlb_tag0_q(tagpos_type_ptereload) or not or_reduce(tlb_tag0_q(tagpos_type_derat to tagpos_type_tlbsrx))) and tlb_tag0_q(tagpos_esel to tagpos_esel+2)); +tlb_tag1_d(tagpos_lpid TO tagpos_lpid+lpid_width-1) <= tlb_tag0_q(tagpos_lpid to tagpos_lpid+lpid_width-1); +tlb_tag1_d(tagpos_atsel) <= tlb_tag0_q(tagpos_atsel); +tlb_tag1_d(tagpos_hes) <= tlb_tag0_q(tagpos_hes); +tlb_tag1_d(tagpos_wq TO tagpos_wq+1) <= tlb_tag0_q(tagpos_wq to tagpos_wq+1); +tlb_tag1_d(tagpos_lrat) <= tlb_tag0_q(tagpos_lrat); +tlb_tag1_d(tagpos_pt) <= tlb_tag0_q(tagpos_pt); +tlb_tag1_d(tagpos_recform) <= tlb_tag0_q(tagpos_recform); +tlb_tag1_d(tagpos_size TO tagpos_size+3) <= ((0 to 3 => or_reduce(tlb_tag0_q(tagpos_type_derat to tagpos_type_tlbsrx)) and not tlb_tag0_q(tagpos_type_ptereload)) and tlb_seq_pgsize) or + ((0 to 3 => tlb_tag0_q(tagpos_type_ptereload) or not or_reduce(tlb_tag0_q(tagpos_type_derat to tagpos_type_tlbsrx))) and tlb_tag0_q(tagpos_size to tagpos_size+3)); +tlb_tag1_d(tagpos_type TO tagpos_type+7) <= + "00000000" when (tlb_seq_ierat_done_sig='1' or tlb_seq_derat_done_sig='1' or tlb_seq_snoop_done_sig='1' or tlb_seq_search_done_sig='1' + or tlb_seq_searchresv_done_sig ='1' or tlb_seq_read_done_sig ='1' or tlb_seq_write_done_sig ='1' or tlb_seq_ptereload_done_sig ='1' + or tlb_seq_abort='1') + else tlb_tag0_q(tagpos_type to tagpos_type+7); +tlb_tag1_d(tagpos_endflag) <= tlb_seq_endflag; +tlb_addr_d <= (others => '0') when tlb_seq_addr_clr='1' + else tlb_addr_p1 when tlb_seq_addr_incr='1' + else tlb_seq_addr when tlb_seq_addr_update='1' + else tlb_addr_q; +tlb_addr_p1 <= "0000000" when tlb_addr_q="1111111" + else tlb_addr_q+1; +tlb_addr_maxcntm1 <= '1' when tlb_addr_q="1111110" else '0'; +tlb_tag1_pgsize_eq_16mb <= Eq(tlb_tag1_q(tagpos_size to tagpos_size+3),TLB_PgSize_16MB); +tlb_tag1_pgsize_gte_1mb <= Eq(tlb_tag1_q(tagpos_size to tagpos_size+3),TLB_PgSize_1MB) or + Eq(tlb_tag1_q(tagpos_size to tagpos_size+3),TLB_PgSize_16MB); +tlb_tag1_pgsize_gte_64kb <= Eq(tlb_tag1_q(tagpos_size to tagpos_size+3),TLB_PgSize_1MB) or + Eq(tlb_tag1_q(tagpos_size to tagpos_size+3),TLB_PgSize_16MB) or + Eq(tlb_tag1_q(tagpos_size to tagpos_size+3),TLB_PgSize_64KB); +tlb_tag2_d(tagpos_epn TO tagpos_epn+39) <= tlb_tag1_q(tagpos_epn to tagpos_epn+39); +tlb_tag2_d(tagpos_epn+40 TO tagpos_epn+43) <= tlb_tag1_q(tagpos_epn+40 to tagpos_epn+43) and (40 to 43 => (not tlb_tag1_pgsize_eq_16mb or not tlb_tag1_q(tagpos_type_ptereload))); +tlb_tag2_d(tagpos_epn+44 TO tagpos_epn+47) <= tlb_tag1_q(tagpos_epn+44 to tagpos_epn+47) and (44 to 47 => (not tlb_tag1_pgsize_gte_1mb or not tlb_tag1_q(tagpos_type_ptereload))); +tlb_tag2_d(tagpos_epn+48 TO tagpos_epn+51) <= tlb_tag1_q(tagpos_epn+48 to tagpos_epn+51) and (48 to 51 => (not tlb_tag1_pgsize_gte_64kb or not tlb_tag1_q(tagpos_type_ptereload))); +tlb_tag2_d(tagpos_pid TO tagpos_pid+pid_width-1) <= tlb_tag1_q(tagpos_pid to tagpos_pid+pid_width-1); +tlb_tag2_d(tagpos_is TO tagpos_is+1) <= tlb_tag1_q(tagpos_is to tagpos_is+1); +tlb_tag2_d(tagpos_class TO tagpos_class+1) <= tlb_tag1_q(tagpos_class to tagpos_class+1); +tlb_tag2_d(tagpos_state TO tagpos_state+state_width-1) <= tlb_tag1_q(tagpos_state to tagpos_state+state_width-1); +tlb_tag2_d(tagpos_thdid TO tagpos_thdid+thdid_width-1) <= (others => '0') when + ( tlb_tag4_hit_or_parerr='1' and tlb_tag2_q(tagpos_type_ptereload)='0' and + (tlb_tag2_q(tagpos_type_ierat)='1' or tlb_tag2_q(tagpos_type_derat)='1' or + tlb_tag2_q(tagpos_type_tlbsx)='1' or tlb_tag2_q(tagpos_type_tlbsrx)='1') ) or + (tlb_tag4_endflag='1' and tlb_tag0_q(tagpos_type_snoop)='1') or + tlb_seq_any_done_sig ='1' or tlb_seq_abort='1' + else tlb_tag1_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and + not(tlb_ctl_tag2_flush_sig) and not(tlb_ctl_tag3_flush_sig) and not(tlb_ctl_tag4_flush_sig); +tlb_tag2_d(tagpos_size TO tagpos_size+3) <= tlb_tag1_q(tagpos_size to tagpos_size+3); +tlb_tag2_d(tagpos_type TO tagpos_type+7) <= + "00000000" when (tlb_seq_ierat_done_sig='1' or tlb_seq_derat_done_sig='1' or tlb_seq_snoop_done_sig='1' or tlb_seq_search_done_sig='1' + or tlb_seq_searchresv_done_sig ='1' or tlb_seq_read_done_sig ='1' or tlb_seq_write_done_sig ='1' or tlb_seq_ptereload_done_sig ='1' + or tlb_seq_abort='1') + else tlb_tag1_q(tagpos_type to tagpos_type+7); +tlb_tag2_d(tagpos_lpid TO tagpos_lpid+lpid_width-1) <= tlb_tag1_q(tagpos_lpid to tagpos_lpid+lpid_width-1); +tlb_tag2_d(tagpos_ind) <= tlb_tag1_q(tagpos_ind); +tlb_tag2_d(tagpos_atsel) <= tlb_tag1_q(tagpos_atsel); +tlb_tag2_d(tagpos_esel TO tagpos_esel+2) <= tlb_tag1_q(tagpos_esel to tagpos_esel+2); +tlb_tag2_d(tagpos_hes) <= tlb_tag1_q(tagpos_hes); +tlb_tag2_d(tagpos_wq TO tagpos_wq+1) <= tlb_tag1_q(tagpos_wq to tagpos_wq+1); +tlb_tag2_d(tagpos_lrat) <= tlb_tag1_q(tagpos_lrat); +tlb_tag2_d(tagpos_pt) <= tlb_tag1_q(tagpos_pt); +tlb_tag2_d(tagpos_recform) <= tlb_tag1_q(tagpos_recform); +tlb_tag2_d(tagpos_endflag) <= tlb_tag1_q(tagpos_endflag); +lru_rd_addr <= tlb_addr_q; +tlb_addr <= tlb_addr_q; +tlb_addr2_d <= tlb_addr_q; +tlb_tag2 <= tlb_tag2_q; +tlb_addr2 <= tlb_addr2_q; +tlb_write_d <= "1000" when ( ex6_valid_q/="0000" and ex6_ttype_q(1)='1' and ex6_state_q(0)='0' and ex6_illeg_instr_q(1)='0' + and ( (ex6_state_q(1)='0' and tlb_tag4_atsel='0') or + (ex6_state_q(1)='1' and lrat_tag4_hit_status(0 to 3)="1100" and + (lru_tag4_dataout(0)='0' or lru_tag4_dataout(8)='0') and + tlb_tag4_is(1)='0' and tlb0cfg_gtwe='1' and ex6_dgtmi_state='0')) + and ((or_reduce(ex6_valid_q and tlb_resv_match_vec_q)='1' and tlb_tag4_wq="01" and mmucfg_twc='1') or tlb_tag4_wq="00" or tlb_tag4_wq="11") + and tlb_tag4_hes='1' and lru_tag4_dataout(4 to 5)="00" ) + else "0100" when ( ex6_valid_q/="0000" and ex6_ttype_q(1)='1' and ex6_state_q(0)='0' and ex6_illeg_instr_q(1)='0' + and ((ex6_state_q(1)='0' and tlb_tag4_atsel='0') or + (ex6_state_q(1)='1' and lrat_tag4_hit_status(0 to 3)="1100" and + (lru_tag4_dataout(1)='0' or lru_tag4_dataout(9)='0') and + tlb_tag4_is(1)='0' and tlb0cfg_gtwe='1' and ex6_dgtmi_state='0')) + and ((or_reduce(ex6_valid_q and tlb_resv_match_vec_q)='1' and tlb_tag4_wq="01" and mmucfg_twc='1') or tlb_tag4_wq="00" or tlb_tag4_wq="11") + and tlb_tag4_hes='1' and lru_tag4_dataout(4 to 5)="01" ) + else "0010" when ( ex6_valid_q/="0000" and ex6_ttype_q(1)='1' and ex6_state_q(0)='0' and ex6_illeg_instr_q(1)='0' + and ((ex6_state_q(1)='0' and tlb_tag4_atsel='0') or + (ex6_state_q(1)='1' and lrat_tag4_hit_status(0 to 3)="1100" and + (lru_tag4_dataout(2)='0' or lru_tag4_dataout(10)='0') and + tlb_tag4_is(1)='0' and tlb0cfg_gtwe='1' and ex6_dgtmi_state='0')) + and ((or_reduce(ex6_valid_q and tlb_resv_match_vec_q)='1' and tlb_tag4_wq="01" and mmucfg_twc='1') or tlb_tag4_wq="00" or tlb_tag4_wq="11") + and tlb_tag4_hes='1' and lru_tag4_dataout(4)='1' and lru_tag4_dataout(6)='0' ) + else "0001" when ( ex6_valid_q/="0000" and ex6_ttype_q(1)='1' and ex6_state_q(0)='0' and ex6_illeg_instr_q(1)='0' + and ((ex6_state_q(1)='0' and tlb_tag4_atsel='0') or + (ex6_state_q(1)='1' and lrat_tag4_hit_status(0 to 3)="1100" and + (lru_tag4_dataout(3)='0' or lru_tag4_dataout(11)='0') and + tlb_tag4_is(1)='0' and tlb0cfg_gtwe='1' and ex6_dgtmi_state='0')) + and ((or_reduce(ex6_valid_q and tlb_resv_match_vec_q)='1' and tlb_tag4_wq="01" and mmucfg_twc='1') or tlb_tag4_wq="00" or tlb_tag4_wq="11") + and tlb_tag4_hes='1' and lru_tag4_dataout(4)='1' and lru_tag4_dataout(6)='1' ) + else "1000" when ( ex6_valid_q/="0000" and ex6_ttype_q(1)='1' and ex6_state_q(0)='0' and ex6_illeg_instr_q(1)='0' + and ex6_state_q(1)='0' and tlb_tag4_atsel='0' + and ((or_reduce(ex6_valid_q and tlb_resv_match_vec_q)='1' and tlb_tag4_wq="01" and mmucfg_twc='1') or tlb_tag4_wq="00" or tlb_tag4_wq="11") + and tlb_tag4_hes='0' and tlb_tag4_esel(1 to 2)="00" ) + else "0100" when ( ex6_valid_q/="0000" and ex6_ttype_q(1)='1' and ex6_state_q(0)='0' and ex6_illeg_instr_q(1)='0' + and ex6_state_q(1)='0' and tlb_tag4_atsel='0' + and ((or_reduce(ex6_valid_q and tlb_resv_match_vec_q)='1' and tlb_tag4_wq="01" and mmucfg_twc='1') or tlb_tag4_wq="00" or tlb_tag4_wq="11") + and tlb_tag4_hes='0' and tlb_tag4_esel(1 to 2)="01") + else "0010" when ( ex6_valid_q/="0000" and ex6_ttype_q(1)='1' and ex6_state_q(0)='0' and ex6_illeg_instr_q(1)='0' + and ex6_state_q(1)='0' and tlb_tag4_atsel='0' + and ((or_reduce(ex6_valid_q and tlb_resv_match_vec_q)='1' and tlb_tag4_wq="01" and mmucfg_twc='1') or tlb_tag4_wq="00" or tlb_tag4_wq="11") + and tlb_tag4_hes='0' and tlb_tag4_esel(1 to 2)="10") + else "0001" when ( ex6_valid_q/="0000" and ex6_ttype_q(1)='1' and ex6_state_q(0)='0' and ex6_illeg_instr_q(1)='0' + and ex6_state_q(1)='0' and tlb_tag4_atsel='0' + and ((or_reduce(ex6_valid_q and tlb_resv_match_vec_q)='1' and tlb_tag4_wq="01" and mmucfg_twc='1') or tlb_tag4_wq="00" or tlb_tag4_wq="11") + and tlb_tag4_hes='0' and tlb_tag4_esel(1 to 2)="11") + else "1000" when ( tlb_tag4_ptereload='1' + and (tlb_tag4_gs='0' or (tlb_tag4_gs='1' and lrat_tag4_hit_status(0 to 3)="1100")) + and lru_tag4_dataout(4 to 5)="00" + and (lru_tag4_dataout(0)='0' or lru_tag4_dataout(8)='0') + and tlb_tag4_wq="10" and tlb_tag4_is(0)='1' and tlb_tag4_pt='1') + else "0100" when ( tlb_tag4_ptereload='1' + and (tlb_tag4_gs='0' or (tlb_tag4_gs='1' and lrat_tag4_hit_status(0 to 3)="1100")) + and lru_tag4_dataout(4 to 5)="01" + and (lru_tag4_dataout(1)='0' or lru_tag4_dataout(9)='0') + and tlb_tag4_wq="10" and tlb_tag4_is(0)='1' and tlb_tag4_pt='1') + else "0010" when ( tlb_tag4_ptereload='1' + and (tlb_tag4_gs='0' or (tlb_tag4_gs='1' and lrat_tag4_hit_status(0 to 3)="1100")) + and lru_tag4_dataout(4)='1' and lru_tag4_dataout(6)='0' + and (lru_tag4_dataout(2)='0' or lru_tag4_dataout(10)='0') + and tlb_tag4_wq="10" and tlb_tag4_is(0)='1' and tlb_tag4_pt='1') + else "0001" when ( tlb_tag4_ptereload='1' + and (tlb_tag4_gs='0' or (tlb_tag4_gs='1' and lrat_tag4_hit_status(0 to 3)="1100")) + and lru_tag4_dataout(4)='1' and lru_tag4_dataout(6)='1' + and (lru_tag4_dataout(3)='0' or lru_tag4_dataout(11)='0') + and tlb_tag4_wq="10" and tlb_tag4_is(0)='1' and tlb_tag4_pt='1') + else "0000"; +tlb_write <= tlb_write_q and (0 to tlb_ways-1 => not or_reduce(tlb_tag5_except)); +tlb_tag5_write <= or_reduce(tlb_write_q) and not or_reduce(tlb_tag5_except); +ex3_valid_32b <= or_reduce(ex3_valid_q and not(xu_mm_msr_cm)); +tlb_ctl_ex2_flush_req <= (ex2_valid_q and not(xu_ex2_flush)) + when (ex2_ttype_q(2 to 4)/="000" + and search_req_taken_sig='0' and searchresv_req_taken_sig='0') + else (ex2_valid_q and not(xu_ex2_flush)) when (ex2_flush_req_q/="0000") + else "0000"; +mas1_tsize_direct(0) <= ( Eq(mas1_0_tsize,TLB_PgSize_4KB) or Eq(mas1_0_tsize,TLB_PgSize_64KB) or + Eq(mas1_0_tsize,TLB_PgSize_1MB) or Eq(mas1_0_tsize,TLB_PgSize_16MB) or + Eq(mas1_0_tsize,TLB_PgSize_1GB) ); +mas1_tsize_indirect(0) <= ( Eq(mas1_0_tsize,TLB_PgSize_1MB) or Eq(mas1_0_tsize,TLB_PgSize_256MB) ); +mas1_tsize_lrat(0) <= ( Eq(mas1_0_tsize,LRAT_PgSize_1MB) or Eq(mas1_0_tsize,LRAT_PgSize_16MB) or + Eq(mas1_0_tsize,LRAT_PgSize_256MB) or Eq(mas1_0_tsize,LRAT_PgSize_1GB) or + Eq(mas1_0_tsize,LRAT_PgSize_4GB) or Eq(mas1_0_tsize,LRAT_PgSize_16GB) or + Eq(mas1_0_tsize,LRAT_PgSize_256GB) or Eq(mas1_0_tsize,LRAT_PgSize_1TB) ); +ex2_tlbre_mas1_tsize_not_supp(0) <= '1' when ( mas1_tsize_direct(0)='0' and (mas1_0_ind='0' or tlb0cfg_ind='0') and (mas0_0_atsel='0' or ex2_state_q(1)='1') ) or + ( mas1_tsize_indirect(0)='0' and mas1_0_ind='1' and tlb0cfg_ind='1' and (mas0_0_atsel='0' or ex2_state_q(1)='1') ) + else '0'; +ex5_tlbre_mas1_tsize_not_supp(0) <= '1' when ( mas1_tsize_direct(0)='0' and (mas1_0_ind='0' or tlb0cfg_ind='0') and (mas0_0_atsel='0' or ex5_state_q(1)='1') ) or + ( mas1_tsize_indirect(0)='0' and mas1_0_ind='1' and tlb0cfg_ind='1' and (mas0_0_atsel='0' or ex5_state_q(1)='1') ) + else '0'; +ex5_tlbwe_mas1_tsize_not_supp(0) <= '1' when ( mas1_tsize_direct(0)='0' and (mas1_0_ind='0' or tlb0cfg_ind='0') and mas0_0_wq/="10" and (mas0_0_atsel='0' or ex5_state_q(1)='1') ) or + ( mas1_tsize_indirect(0)='0' and mas1_0_ind='1' and tlb0cfg_ind='1' and mas0_0_wq/="10" and (mas0_0_atsel='0' or ex5_state_q(1)='1') ) or + ( mas1_tsize_lrat(0)='0' and mas0_0_atsel='1' and (mas0_0_wq="00" or mas0_0_wq="11") and ex5_state_q(1)='0' ) + else '0'; +ex6_tlbwe_mas1_tsize_not_supp(0) <= '1' when ( mas1_tsize_direct(0)='0' and (mas1_0_ind='0' or tlb0cfg_ind='0') and mas0_0_wq/="10" and (mas0_0_atsel='0' or ex6_state_q(1)='1') ) or + ( mas1_tsize_indirect(0)='0' and mas1_0_ind='1' and tlb0cfg_ind='1' and mas0_0_wq/="10" and (mas0_0_atsel='0' or ex6_state_q(1)='1') ) or + ( mas1_tsize_lrat(0)='0' and mas0_0_atsel='1' and (mas0_0_wq="00" or mas0_0_wq="11") and ex6_state_q(1)='0' ) + else '0'; +ex5_tlbwe_mas0_lrat_bad_selects(0) <= '1' when ( (mas0_0_hes='1' or mas0_0_wq="01" or mas0_0_wq="10") and mas0_0_atsel='1' and ex5_state_q(1)='0' ) + else '0'; +ex6_tlbwe_mas0_lrat_bad_selects(0) <= '1' when ( (mas0_0_hes='1' or mas0_0_wq="01" or mas0_0_wq="10") and mas0_0_atsel='1' and ex6_state_q(1)='0' ) + else '0'; +ex5_tlbwe_mas2_ind_bad_wimge(0) <= '1' when ( mas1_0_ind='1' and tlb0cfg_ind='1' and mas0_0_wq/="10" and + (mas2_0_wimge(1)='1' or mas2_0_wimge(2)='0' or mas2_0_wimge(3)='1' or mas2_0_wimge(4)='1') and + (mas0_0_atsel='0' or ex5_state_q(1)='1') ) + else '0'; +ex6_tlbwe_mas2_ind_bad_wimge(0) <= '1' when ( mas1_0_ind='1' and tlb0cfg_ind='1' and mas0_0_wq/="10" and + (mas2_0_wimge(1)='1' or mas2_0_wimge(2)='0' or mas2_0_wimge(3)='1' or mas2_0_wimge(4)='1') and + (mas0_0_atsel='0' or ex6_state_q(1)='1') ) + else '0'; +mas3_spsize_indirect(0) <= '1' when ((mas1_0_tsize=TLB_PgSize_1MB and mas3_0_usxwr(0 to 3)=TLB_PgSize_4KB) or + (mas1_0_tsize=TLB_PgSize_256MB and mas3_0_usxwr(0 to 3)=TLB_PgSize_64KB)) + else '0'; +ex5_tlbwe_mas3_ind_bad_spsize(0) <= '1' when ( mas1_0_ind='1' and tlb0cfg_ind='1' and mas0_0_wq/="10" and mas3_spsize_indirect(0)='0' and (mas0_0_atsel='0' or ex5_state_q(1)='1') ) + else '0'; +ex6_tlbwe_mas3_ind_bad_spsize(0) <= '1' when ( mas1_0_ind='1' and tlb0cfg_ind='1' and mas0_0_wq/="10" and mas3_spsize_indirect(0)='0' and (mas0_0_atsel='0' or ex6_state_q(1)='1') ) + else '0'; +mas1_tsize_direct(1) <= ( Eq(mas1_1_tsize,TLB_PgSize_4KB) or Eq(mas1_1_tsize,TLB_PgSize_64KB) or + Eq(mas1_1_tsize,TLB_PgSize_1MB) or Eq(mas1_1_tsize,TLB_PgSize_16MB) or + Eq(mas1_1_tsize,TLB_PgSize_1GB) ); +mas1_tsize_indirect(1) <= ( Eq(mas1_1_tsize,TLB_PgSize_1MB) or Eq(mas1_1_tsize,TLB_PgSize_256MB) ); +mas1_tsize_lrat(1) <= ( Eq(mas1_1_tsize,LRAT_PgSize_1MB) or Eq(mas1_1_tsize,LRAT_PgSize_16MB) or + Eq(mas1_1_tsize,LRAT_PgSize_256MB) or Eq(mas1_1_tsize,LRAT_PgSize_1GB) or + Eq(mas1_1_tsize,LRAT_PgSize_4GB) or Eq(mas1_1_tsize,LRAT_PgSize_16GB) or + Eq(mas1_1_tsize,LRAT_PgSize_256GB) or Eq(mas1_1_tsize,LRAT_PgSize_1TB) ); +ex2_tlbre_mas1_tsize_not_supp(1) <= '1' when ( mas1_tsize_direct(1)='0' and (mas1_1_ind='0' or tlb0cfg_ind='0') and (mas0_1_atsel='0' or ex2_state_q(1)='1') ) or + ( mas1_tsize_indirect(1)='0' and mas1_1_ind='1' and tlb0cfg_ind='1' and (mas0_1_atsel='0' or ex2_state_q(1)='1') ) + else '0'; +ex5_tlbre_mas1_tsize_not_supp(1) <= '1' when ( mas1_tsize_direct(1)='0' and (mas1_1_ind='0' or tlb0cfg_ind='0') and (mas0_1_atsel='0' or ex5_state_q(1)='1') ) or + ( mas1_tsize_indirect(1)='0' and mas1_1_ind='1' and tlb0cfg_ind='1' and (mas0_1_atsel='0' or ex5_state_q(1)='1') ) + else '0'; +ex5_tlbwe_mas1_tsize_not_supp(1) <= '1' when ( mas1_tsize_direct(1)='0' and (mas1_1_ind='0' or tlb0cfg_ind='0') and mas0_1_wq/="10" and (mas0_1_atsel='0' or ex5_state_q(1)='1') ) or + ( mas1_tsize_indirect(1)='0' and mas1_1_ind='1' and tlb0cfg_ind='1' and mas0_1_wq/="10" and (mas0_1_atsel='0' or ex5_state_q(1)='1') ) or + ( mas1_tsize_lrat(1)='0' and mas0_1_atsel='1' and (mas0_1_wq="00" or mas0_1_wq="11") and ex5_state_q(1)='0' ) + else '0'; +ex6_tlbwe_mas1_tsize_not_supp(1) <= '1' when ( mas1_tsize_direct(1)='0' and (mas1_1_ind='0' or tlb0cfg_ind='0') and mas0_1_wq/="10" and (mas0_1_atsel='0' or ex6_state_q(1)='1') ) or + ( mas1_tsize_indirect(1)='0' and mas1_1_ind='1' and tlb0cfg_ind='1' and mas0_1_wq/="10" and (mas0_1_atsel='0' or ex6_state_q(1)='1') ) or + ( mas1_tsize_lrat(1)='0' and mas0_1_atsel='1' and (mas0_1_wq="00" or mas0_1_wq="11") and ex6_state_q(1)='0' ) + else '0'; +ex5_tlbwe_mas0_lrat_bad_selects(1) <= '1' when ( (mas0_1_hes='1' or mas0_1_wq="01" or mas0_1_wq="10") and mas0_1_atsel='1' and ex5_state_q(1)='0' ) + else '0'; +ex6_tlbwe_mas0_lrat_bad_selects(1) <= '1' when ( (mas0_1_hes='1' or mas0_1_wq="01" or mas0_1_wq="10") and mas0_1_atsel='1' and ex6_state_q(1)='0' ) + else '0'; +ex5_tlbwe_mas2_ind_bad_wimge(1) <= '1' when ( mas1_1_ind='1' and tlb0cfg_ind='1' and mas0_1_wq/="10" and + (mas2_1_wimge(1)='1' or mas2_1_wimge(2)='0' or mas2_1_wimge(3)='1' or mas2_1_wimge(4)='1') and + (mas0_1_atsel='0' or ex5_state_q(1)='1') ) + else '0'; +ex6_tlbwe_mas2_ind_bad_wimge(1) <= '1' when ( mas1_1_ind='1' and tlb0cfg_ind='1' and mas0_1_wq/="10" and + (mas2_1_wimge(1)='1' or mas2_1_wimge(2)='0' or mas2_1_wimge(3)='1' or mas2_1_wimge(4)='1') and + (mas0_1_atsel='0' or ex6_state_q(1)='1') ) + else '0'; +mas3_spsize_indirect(1) <= '1' when ((mas1_1_tsize=TLB_PgSize_1MB and mas3_1_usxwr(0 to 3)=TLB_PgSize_4KB) or + (mas1_1_tsize=TLB_PgSize_256MB and mas3_1_usxwr(0 to 3)=TLB_PgSize_64KB)) + else '0'; +ex5_tlbwe_mas3_ind_bad_spsize(1) <= '1' when ( mas1_1_ind='1' and tlb0cfg_ind='1' and mas0_1_wq/="10" and mas3_spsize_indirect(1)='0' and (mas0_1_atsel='0' or ex5_state_q(1)='1') ) + else '0'; +ex6_tlbwe_mas3_ind_bad_spsize(1) <= '1' when ( mas1_1_ind='1' and tlb0cfg_ind='1' and mas0_1_wq/="10" and mas3_spsize_indirect(1)='0' and (mas0_1_atsel='0' or ex6_state_q(1)='1') ) + else '0'; +mas1_tsize_direct(2) <= ( Eq(mas1_2_tsize,TLB_PgSize_4KB) or Eq(mas1_2_tsize,TLB_PgSize_64KB) or + Eq(mas1_2_tsize,TLB_PgSize_1MB) or Eq(mas1_2_tsize,TLB_PgSize_16MB) or + Eq(mas1_2_tsize,TLB_PgSize_1GB) ); +mas1_tsize_indirect(2) <= ( Eq(mas1_2_tsize,TLB_PgSize_1MB) or Eq(mas1_2_tsize,TLB_PgSize_256MB) ); +mas1_tsize_lrat(2) <= ( Eq(mas1_2_tsize,LRAT_PgSize_1MB) or Eq(mas1_2_tsize,LRAT_PgSize_16MB) or + Eq(mas1_2_tsize,LRAT_PgSize_256MB) or Eq(mas1_2_tsize,LRAT_PgSize_1GB) or + Eq(mas1_2_tsize,LRAT_PgSize_4GB) or Eq(mas1_2_tsize,LRAT_PgSize_16GB) or + Eq(mas1_2_tsize,LRAT_PgSize_256GB) or Eq(mas1_2_tsize,LRAT_PgSize_1TB) ); +ex2_tlbre_mas1_tsize_not_supp(2) <= '1' when ( mas1_tsize_direct(2)='0' and (mas1_2_ind='0' or tlb0cfg_ind='0') and (mas0_2_atsel='0' or ex2_state_q(1)='1') ) or + ( mas1_tsize_indirect(2)='0' and mas1_2_ind='1' and tlb0cfg_ind='1' and (mas0_2_atsel='0' or ex2_state_q(1)='1') ) + else '0'; +ex5_tlbre_mas1_tsize_not_supp(2) <= '1' when ( mas1_tsize_direct(2)='0' and (mas1_2_ind='0' or tlb0cfg_ind='0') and (mas0_2_atsel='0' or ex5_state_q(1)='1') ) or + ( mas1_tsize_indirect(2)='0' and mas1_2_ind='1' and tlb0cfg_ind='1' and (mas0_2_atsel='0' or ex5_state_q(1)='1') ) + else '0'; +ex5_tlbwe_mas1_tsize_not_supp(2) <= '1' when ( mas1_tsize_direct(2)='0' and (mas1_2_ind='0' or tlb0cfg_ind='0') and mas0_2_wq/="10" and (mas0_2_atsel='0' or ex5_state_q(1)='1') ) or + ( mas1_tsize_indirect(2)='0' and mas1_2_ind='1' and tlb0cfg_ind='1' and mas0_2_wq/="10" and (mas0_2_atsel='0' or ex5_state_q(1)='1') ) or + ( mas1_tsize_lrat(2)='0' and mas0_2_atsel='1' and (mas0_2_wq="00" or mas0_2_wq="11") and ex5_state_q(1)='0' ) + else '0'; +ex6_tlbwe_mas1_tsize_not_supp(2) <= '1' when ( mas1_tsize_direct(2)='0' and (mas1_2_ind='0' or tlb0cfg_ind='0') and mas0_2_wq/="10" and (mas0_2_atsel='0' or ex6_state_q(1)='1') ) or + ( mas1_tsize_indirect(2)='0' and mas1_2_ind='1' and tlb0cfg_ind='1' and mas0_2_wq/="10" and (mas0_2_atsel='0' or ex6_state_q(1)='1') ) or + ( mas1_tsize_lrat(2)='0' and mas0_2_atsel='1' and (mas0_2_wq="00" or mas0_2_wq="11") and ex6_state_q(1)='0' ) + else '0'; +ex5_tlbwe_mas0_lrat_bad_selects(2) <= '1' when ( (mas0_2_hes='1' or mas0_2_wq="01" or mas0_2_wq="10") and mas0_2_atsel='1' and ex5_state_q(1)='0' ) + else '0'; +ex6_tlbwe_mas0_lrat_bad_selects(2) <= '1' when ( (mas0_2_hes='1' or mas0_2_wq="01" or mas0_2_wq="10") and mas0_2_atsel='1' and ex6_state_q(1)='0' ) + else '0'; +ex5_tlbwe_mas2_ind_bad_wimge(2) <= '1' when ( mas1_2_ind='1' and tlb0cfg_ind='1' and mas0_2_wq/="10" and + (mas2_2_wimge(1)='1' or mas2_2_wimge(2)='0' or mas2_2_wimge(3)='1' or mas2_2_wimge(4)='1') and + (mas0_2_atsel='0' or ex5_state_q(1)='1') ) + else '0'; +ex6_tlbwe_mas2_ind_bad_wimge(2) <= '1' when ( mas1_2_ind='1' and tlb0cfg_ind='1' and mas0_2_wq/="10" and + (mas2_2_wimge(1)='1' or mas2_2_wimge(2)='0' or mas2_2_wimge(3)='1' or mas2_2_wimge(4)='1') and + (mas0_2_atsel='0' or ex6_state_q(1)='1') ) + else '0'; +mas3_spsize_indirect(2) <= '1' when ((mas1_2_tsize=TLB_PgSize_1MB and mas3_2_usxwr(0 to 3)=TLB_PgSize_4KB) or + (mas1_2_tsize=TLB_PgSize_256MB and mas3_2_usxwr(0 to 3)=TLB_PgSize_64KB)) + else '0'; +ex5_tlbwe_mas3_ind_bad_spsize(2) <= '1' when ( mas1_2_ind='1' and tlb0cfg_ind='1' and mas0_2_wq/="10" and mas3_spsize_indirect(2)='0' and (mas0_2_atsel='0' or ex5_state_q(1)='1') ) + else '0'; +ex6_tlbwe_mas3_ind_bad_spsize(2) <= '1' when ( mas1_2_ind='1' and tlb0cfg_ind='1' and mas0_2_wq/="10" and mas3_spsize_indirect(2)='0' and (mas0_2_atsel='0' or ex6_state_q(1)='1') ) + else '0'; +mas1_tsize_direct(3) <= ( Eq(mas1_3_tsize,TLB_PgSize_4KB) or Eq(mas1_3_tsize,TLB_PgSize_64KB) or + Eq(mas1_3_tsize,TLB_PgSize_1MB) or Eq(mas1_3_tsize,TLB_PgSize_16MB) or + Eq(mas1_3_tsize,TLB_PgSize_1GB) ); +mas1_tsize_indirect(3) <= ( Eq(mas1_3_tsize,TLB_PgSize_1MB) or Eq(mas1_3_tsize,TLB_PgSize_256MB) ); +mas1_tsize_lrat(3) <= ( Eq(mas1_3_tsize,LRAT_PgSize_1MB) or Eq(mas1_3_tsize,LRAT_PgSize_16MB) or + Eq(mas1_3_tsize,LRAT_PgSize_256MB) or Eq(mas1_3_tsize,LRAT_PgSize_1GB) or + Eq(mas1_3_tsize,LRAT_PgSize_4GB) or Eq(mas1_3_tsize,LRAT_PgSize_16GB) or + Eq(mas1_3_tsize,LRAT_PgSize_256GB) or Eq(mas1_3_tsize,LRAT_PgSize_1TB) ); +ex2_tlbre_mas1_tsize_not_supp(3) <= '1' when ( mas1_tsize_direct(3)='0' and (mas1_3_ind='0' or tlb0cfg_ind='0') and (mas0_3_atsel='0' or ex2_state_q(1)='1') ) or + ( mas1_tsize_indirect(3)='0' and mas1_3_ind='1' and tlb0cfg_ind='1' and (mas0_3_atsel='0' or ex2_state_q(1)='1') ) + else '0'; +ex5_tlbre_mas1_tsize_not_supp(3) <= '1' when ( mas1_tsize_direct(3)='0' and (mas1_3_ind='0' or tlb0cfg_ind='0') and (mas0_3_atsel='0' or ex5_state_q(1)='1') ) or + ( mas1_tsize_indirect(3)='0' and mas1_3_ind='1' and tlb0cfg_ind='1' and (mas0_3_atsel='0' or ex5_state_q(1)='1') ) + else '0'; +ex5_tlbwe_mas1_tsize_not_supp(3) <= '1' when ( mas1_tsize_direct(3)='0' and (mas1_3_ind='0' or tlb0cfg_ind='0') and mas0_3_wq/="10" and (mas0_3_atsel='0' or ex5_state_q(1)='1') ) or + ( mas1_tsize_indirect(3)='0' and mas1_3_ind='1' and tlb0cfg_ind='1' and mas0_3_wq/="10" and (mas0_3_atsel='0' or ex5_state_q(1)='1') ) or + ( mas1_tsize_lrat(3)='0' and mas0_3_atsel='1' and (mas0_3_wq="00" or mas0_3_wq="11") and ex5_state_q(1)='0' ) + else '0'; +ex6_tlbwe_mas1_tsize_not_supp(3) <= '1' when ( mas1_tsize_direct(3)='0' and (mas1_3_ind='0' or tlb0cfg_ind='0') and mas0_3_wq/="10" and (mas0_3_atsel='0' or ex6_state_q(1)='1') ) or + ( mas1_tsize_indirect(3)='0' and mas1_3_ind='1' and tlb0cfg_ind='1' and mas0_3_wq/="10" and (mas0_3_atsel='0' or ex6_state_q(1)='1') ) or + ( mas1_tsize_lrat(3)='0' and mas0_3_atsel='1' and (mas0_3_wq="00" or mas0_3_wq="11") and ex6_state_q(1)='0' ) + else '0'; +ex5_tlbwe_mas0_lrat_bad_selects(3) <= '1' when ( (mas0_3_hes='1' or mas0_3_wq="01" or mas0_3_wq="10") and mas0_3_atsel='1' and ex5_state_q(1)='0' ) + else '0'; +ex6_tlbwe_mas0_lrat_bad_selects(3) <= '1' when ( (mas0_3_hes='1' or mas0_3_wq="01" or mas0_3_wq="10") and mas0_3_atsel='1' and ex6_state_q(1)='0' ) + else '0'; +ex5_tlbwe_mas2_ind_bad_wimge(3) <= '1' when ( mas1_3_ind='1' and tlb0cfg_ind='1' and mas0_3_wq/="10" and + (mas2_3_wimge(1)='1' or mas2_3_wimge(2)='0' or mas2_3_wimge(3)='1' or mas2_3_wimge(4)='1') and + (mas0_3_atsel='0' or ex5_state_q(1)='1') ) + else '0'; +ex6_tlbwe_mas2_ind_bad_wimge(3) <= '1' when ( mas1_3_ind='1' and tlb0cfg_ind='1' and mas0_3_wq/="10" and + (mas2_3_wimge(1)='1' or mas2_3_wimge(2)='0' or mas2_3_wimge(3)='1' or mas2_3_wimge(4)='1') and + (mas0_3_atsel='0' or ex6_state_q(1)='1') ) + else '0'; +mas3_spsize_indirect(3) <= '1' when ((mas1_3_tsize=TLB_PgSize_1MB and mas3_3_usxwr(0 to 3)=TLB_PgSize_4KB) or + (mas1_3_tsize=TLB_PgSize_256MB and mas3_3_usxwr(0 to 3)=TLB_PgSize_64KB)) + else '0'; +ex5_tlbwe_mas3_ind_bad_spsize(3) <= '1' when ( mas1_3_ind='1' and tlb0cfg_ind='1' and mas0_3_wq/="10" and mas3_spsize_indirect(3)='0' and (mas0_3_atsel='0' or ex5_state_q(1)='1') ) + else '0'; +ex6_tlbwe_mas3_ind_bad_spsize(3) <= '1' when ( mas1_3_ind='1' and tlb0cfg_ind='1' and mas0_3_wq/="10" and mas3_spsize_indirect(3)='0' and (mas0_3_atsel='0' or ex6_state_q(1)='1') ) + else '0'; +tlb_ctl_ex2_illeg_instr <= ( ex2_tlbre_mas1_tsize_not_supp and ex2_valid_q and not(xu_ex2_flush) and + (0 to 3 => (ex2_ttype_q(0) and ex2_hv_state and not ex2_mas0_atsel)) ) + or ( (ex6_tlbwe_mas1_tsize_not_supp or ex6_tlbwe_mas0_lrat_bad_selects or ex6_tlbwe_mas2_ind_bad_wimge or ex6_tlbwe_mas3_ind_bad_spsize) and ex6_valid_q and + (0 to 3 => (ex6_ttype_q(1) and (ex6_hv_state or (ex6_priv_state and not ex6_dgtmi_state)))) ); +ex6_illeg_instr_d(0) <= ex5_ttype_q(0) and or_reduce(ex5_tlbre_mas1_tsize_not_supp and ex5_valid_q); +ex6_illeg_instr_d(1) <= ex5_ttype_q(1) and or_reduce((ex5_tlbwe_mas1_tsize_not_supp or ex5_tlbwe_mas0_lrat_bad_selects or ex5_tlbwe_mas2_ind_bad_wimge or ex5_tlbwe_mas3_ind_bad_spsize) and ex5_valid_q); +ex6_illeg_instr <= ex6_illeg_instr_q; +tlb_lper_lpn <= ptereload_req_pte_q(ptepos_rpn+10 to ptepos_rpn+39); +tlb_lper_lps <= ptereload_req_pte_q(ptepos_size to ptepos_size+3); +tlb_lper_we <= tlb_tag0_q(tagpos_thdid to tagpos_thdid+thdid_width-1) + when (tlb_tag4_ptereload='1' and tlb_tag4_gs='1' and + mmucfg_lrat='1' and tlb_tag4_pt='1' and tlb_tag4_wq="10" and + tlb_tag4_is(0)='1' and lrat_tag4_hit_status(0 to 3)/="1100") + else (others => '0'); +pte_tag0_lpn <= ptereload_req_pte_q(ptepos_rpn+10 to ptepos_rpn+39); +pte_tag0_lpid <= tlb_tag0_q(tagpos_lpid to tagpos_lpid+lpid_width-1); +tlb_ctl_perf_tlbwec_resv <= or_reduce(ex6_valid_q and tlb_resv_match_vec_q) and ex6_ttype_q(1) and Eq(tlb_tag4_wq,"01"); +tlb_ctl_perf_tlbwec_noresv <= or_reduce(ex6_valid_q and not tlb_resv_match_vec_q) and ex6_ttype_q(1) and Eq(tlb_tag4_wq,"01"); +tlb_early_act <= xu_mm_ccr2_notlb_b and (any_tlb_req_sig or not(tlb_seq_idle_sig) or tlb_ctl_any_tag_flush_sig or tlb_seq_abort); +tlb_delayed_act_d(0 TO 1) <= "11" when tlb_early_act='1' + else "10" when tlb_delayed_act_q(0 to 1)="11" + else "01" when tlb_delayed_act_q(0 to 1)="10" + else "00"; +tlb_delayed_act_d(2 TO 8) <= (2 to 8 => tlb_early_act or tlb_delayed_act_q(0) or tlb_delayed_act_q(1) or mmucr2(1)); +tlb_delayed_act_d(9 TO 16) <= (9 to 16 => tlb_early_act or tlb_delayed_act_q(0) or tlb_delayed_act_q(1) or mmucr2(2)); +tlb_delayed_act_d(17 TO 19) <= (17 to 19 => tlb_early_act or tlb_delayed_act_q(0) or tlb_delayed_act_q(1) or mmucr2(2)); +tlb_delayed_act_d(20 TO 23) <= (20 to 23 => tlb_early_act or tlb_delayed_act_q(0) or tlb_delayed_act_q(1) or mmucr2(3)); +tlb_delayed_act_d(24 TO 28) <= (24 to 28 => tlb_early_act or tlb_delayed_act_q(0) or tlb_delayed_act_q(1) or mmucr2(4)); +tlb_delayed_act_d(29 TO 32) <= (29 to 32 => tlb_early_act or tlb_delayed_act_q(0) or tlb_delayed_act_q(1) or mmucr2(6)); +tlb_delayed_act(9 TO 32) <= tlb_delayed_act_q(9 to 32); +tlb_tag0_act <= tlb_early_act or mmucr2(1); +tlb_snoop_act <= (tlb_snoop_coming or mmucr2(1)) and xu_mm_ccr2_notlb_b; +tlb_ctl_dbg_seq_q <= tlb_seq_q; +tlb_ctl_dbg_seq_idle <= tlb_seq_idle_sig; +tlb_ctl_dbg_seq_any_done_sig <= tlb_seq_any_done_sig; +tlb_ctl_dbg_seq_abort <= tlb_seq_abort; +tlb_ctl_dbg_any_tlb_req_sig <= any_tlb_req_sig; +tlb_ctl_dbg_any_req_taken_sig <= any_req_taken_sig; +tlb_ctl_dbg_tag0_valid <= or_reduce(tlb_tag0_q(tagpos_thdid to tagpos_thdid+thdid_width-1)); +tlb_ctl_dbg_tag0_thdid(0) <= tlb_tag0_q(tagpos_thdid+2) or tlb_tag0_q(tagpos_thdid+3); +tlb_ctl_dbg_tag0_thdid(1) <= tlb_tag0_q(tagpos_thdid+1) or tlb_tag0_q(tagpos_thdid+3); +tlb_ctl_dbg_tag0_type(0) <= tlb_tag0_q(tagpos_type+4) or tlb_tag0_q(tagpos_type+5) or tlb_tag0_q(tagpos_type+6) or tlb_tag0_q(tagpos_type+7); +tlb_ctl_dbg_tag0_type(1) <= tlb_tag0_q(tagpos_type+2) or tlb_tag0_q(tagpos_type+3) or tlb_tag0_q(tagpos_type+6) or tlb_tag0_q(tagpos_type+7); +tlb_ctl_dbg_tag0_type(2) <= tlb_tag0_q(tagpos_type+1) or tlb_tag0_q(tagpos_type+3) or tlb_tag0_q(tagpos_type+5) or tlb_tag0_q(tagpos_type+7); +tlb_ctl_dbg_tag0_wq <= tlb_tag0_q(tagpos_wq to tagpos_wq+1); +tlb_ctl_dbg_tag0_gs <= tlb_tag0_q(tagpos_gs); +tlb_ctl_dbg_tag0_pr <= tlb_tag0_q(tagpos_pr); +tlb_ctl_dbg_tag0_atsel <= tlb_tag0_q(tagpos_atsel); +tlb_ctl_dbg_tag5_tlb_write_q <= tlb_write_q; +tlb_ctl_dbg_resv_valid <= tlb_resv_valid_vec; +tlb_ctl_dbg_set_resv <= tlb_set_resv0 & tlb_set_resv1 & tlb_set_resv2 & tlb_set_resv3; +tlb_ctl_dbg_resv_match_vec_q <= tlb_resv_match_vec_q; +tlb_ctl_dbg_any_tag_flush_sig <= tlb_ctl_any_tag_flush_sig; +tlb_ctl_dbg_resv0_tag0_lpid_match <= tlb_resv0_tag0_lpid_match; +tlb_ctl_dbg_resv0_tag0_pid_match <= tlb_resv0_tag0_pid_match; +tlb_ctl_dbg_resv0_tag0_as_snoop_match <= tlb_resv0_tag0_as_snoop_match; +tlb_ctl_dbg_resv0_tag0_gs_snoop_match <= tlb_resv0_tag0_gs_snoop_match; +tlb_ctl_dbg_resv0_tag0_as_tlbwe_match <= tlb_resv0_tag0_as_tlbwe_match; +tlb_ctl_dbg_resv0_tag0_gs_tlbwe_match <= tlb_resv0_tag0_gs_tlbwe_match; +tlb_ctl_dbg_resv0_tag0_ind_match <= tlb_resv0_tag0_ind_match; +tlb_ctl_dbg_resv0_tag0_epn_loc_match <= tlb_resv0_tag0_epn_loc_match; +tlb_ctl_dbg_resv0_tag0_epn_glob_match <= tlb_resv0_tag0_epn_glob_match; +tlb_ctl_dbg_resv0_tag0_class_match <= tlb_resv0_tag0_class_match; +tlb_ctl_dbg_resv1_tag0_lpid_match <= tlb_resv1_tag0_lpid_match; +tlb_ctl_dbg_resv1_tag0_pid_match <= tlb_resv1_tag0_pid_match; +tlb_ctl_dbg_resv1_tag0_as_snoop_match <= tlb_resv1_tag0_as_snoop_match; +tlb_ctl_dbg_resv1_tag0_gs_snoop_match <= tlb_resv1_tag0_gs_snoop_match; +tlb_ctl_dbg_resv1_tag0_as_tlbwe_match <= tlb_resv1_tag0_as_tlbwe_match; +tlb_ctl_dbg_resv1_tag0_gs_tlbwe_match <= tlb_resv1_tag0_gs_tlbwe_match; +tlb_ctl_dbg_resv1_tag0_ind_match <= tlb_resv1_tag0_ind_match; +tlb_ctl_dbg_resv1_tag0_epn_loc_match <= tlb_resv1_tag0_epn_loc_match; +tlb_ctl_dbg_resv1_tag0_epn_glob_match <= tlb_resv1_tag0_epn_glob_match; +tlb_ctl_dbg_resv1_tag0_class_match <= tlb_resv1_tag0_class_match ; +tlb_ctl_dbg_resv2_tag0_lpid_match <= tlb_resv2_tag0_lpid_match; +tlb_ctl_dbg_resv2_tag0_pid_match <= tlb_resv2_tag0_pid_match; +tlb_ctl_dbg_resv2_tag0_as_snoop_match <= tlb_resv2_tag0_as_snoop_match; +tlb_ctl_dbg_resv2_tag0_gs_snoop_match <= tlb_resv2_tag0_gs_snoop_match; +tlb_ctl_dbg_resv2_tag0_as_tlbwe_match <= tlb_resv2_tag0_as_tlbwe_match; +tlb_ctl_dbg_resv2_tag0_gs_tlbwe_match <= tlb_resv2_tag0_gs_tlbwe_match; +tlb_ctl_dbg_resv2_tag0_ind_match <= tlb_resv2_tag0_ind_match; +tlb_ctl_dbg_resv2_tag0_epn_loc_match <= tlb_resv2_tag0_epn_loc_match; +tlb_ctl_dbg_resv2_tag0_epn_glob_match <= tlb_resv2_tag0_epn_glob_match; +tlb_ctl_dbg_resv2_tag0_class_match <= tlb_resv2_tag0_class_match; +tlb_ctl_dbg_resv3_tag0_lpid_match <= tlb_resv3_tag0_lpid_match; +tlb_ctl_dbg_resv3_tag0_pid_match <= tlb_resv3_tag0_pid_match; +tlb_ctl_dbg_resv3_tag0_as_snoop_match <= tlb_resv3_tag0_as_snoop_match; +tlb_ctl_dbg_resv3_tag0_gs_snoop_match <= tlb_resv3_tag0_gs_snoop_match; +tlb_ctl_dbg_resv3_tag0_as_tlbwe_match <= tlb_resv3_tag0_as_tlbwe_match; +tlb_ctl_dbg_resv3_tag0_gs_tlbwe_match <= tlb_resv3_tag0_gs_tlbwe_match; +tlb_ctl_dbg_resv3_tag0_ind_match <= tlb_resv3_tag0_ind_match; +tlb_ctl_dbg_resv3_tag0_epn_loc_match <= tlb_resv3_tag0_epn_loc_match; +tlb_ctl_dbg_resv3_tag0_epn_glob_match <= tlb_resv3_tag0_epn_glob_match; +tlb_ctl_dbg_resv3_tag0_class_match <= tlb_resv3_tag0_class_match; +tlb_ctl_dbg_clr_resv_q <= tlb_clr_resv_q; +tlb_ctl_dbg_clr_resv_terms <= (others => '0'); +unused_dc(0) <= or_reduce(LCB_DELAY_LCLKR_DC(1 TO 4)); +unused_dc(1) <= or_reduce(LCB_MPW1_DC_B(1 TO 4)); +unused_dc(2) <= PC_FUNC_SL_FORCE; +unused_dc(3) <= PC_FUNC_SL_THOLD_0_B; +unused_dc(4) <= TC_SCAN_DIS_DC_B; +unused_dc(5) <= TC_SCAN_DIAG_DC; +unused_dc(6) <= TC_LBIST_EN_DC; +unused_dc(7) <= TLB_TAG0_Q(109); +unused_dc(8) <= or_reduce(MMUCR3_0(49 TO 53)); +unused_dc(9) <= or_reduce(MMUCR3_0(56 TO 63)); +unused_dc(10) <= or_reduce(MMUCR3_1(49 TO 53)); +unused_dc(11) <= or_reduce(MMUCR3_1(56 TO 63)); +unused_dc(12) <= or_reduce(MMUCR3_2(49 TO 53)); +unused_dc(13) <= or_reduce(MMUCR3_2(56 TO 63)); +unused_dc(14) <= or_reduce(MMUCR3_3(49 TO 53)); +unused_dc(15) <= or_reduce(MMUCR3_3(56 TO 63)); +unused_dc(16) <= or_reduce(PGSIZE_QTY); +unused_dc(17) <= or_reduce(PGSIZE_TID0_QTY); +unused_dc(18) <= PTERELOAD_REQ_TAG(66); +unused_dc(19) <= or_reduce(PTERELOAD_REQ_TAG(78 TO 81)); +unused_dc(20) <= or_reduce(PTERELOAD_REQ_TAG(84 TO 89)); +unused_dc(21) <= PTERELOAD_REQ_TAG(98); +unused_dc(22) <= or_reduce(PTERELOAD_REQ_TAG(108 TO 109)); +unused_dc(23) <= LRU_TAG4_DATAOUT(7); +unused_dc(24) <= or_reduce(LRU_TAG4_DATAOUT(12 TO 15)); +unused_dc(25) <= TLB_TAG4_ESEL(0); +unused_dc(26) <= EX3_VALID_32B; +unused_dc(27) <= MAS2_0_WIMGE(0) or MAS2_1_WIMGE(0) or MAS2_2_WIMGE(0) or MAS2_3_WIMGE(0); +unused_dc(28) <= or_reduce(XU_EX1_FLUSH_Q); +unused_dc(29) <= or_reduce(MM_XU_ERATMISS_DONE); +unused_dc(30) <= or_reduce(MM_XU_TLB_MISS); +unused_dc(31) <= or_reduce(MM_XU_TLB_INELIG); +unused_dc(32) <= MMUCR1_TLBI_MSB; +unused_dc(33) <= MMUCSR0_TLB0FI; +unused_dc(34) <= tlb_tag4_pr; +unused_dc(35) <= or_reduce(MMUCR2(0) & MMUCR2(5) & MMUCR2(7) & MMUCR2(8 to 11)); +xu_ex1_flush_latch: tri_rlmreg_p + generic map (width => xu_ex1_flush_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(xu_ex1_flush_offset to xu_ex1_flush_offset+xu_ex1_flush_q'length-1), + scout => sov(xu_ex1_flush_offset to xu_ex1_flush_offset+xu_ex1_flush_q'length-1), + din => xu_ex1_flush_d(0 to thdid_width-1), + dout => xu_ex1_flush_q(0 to thdid_width-1) ); +ex1_valid_latch: tri_rlmreg_p + generic map (width => ex1_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex1_valid_offset to ex1_valid_offset+ex1_valid_q'length-1), + scout => sov(ex1_valid_offset to ex1_valid_offset+ex1_valid_q'length-1), + din => ex1_valid_d(0 to thdid_width-1), + dout => ex1_valid_q(0 to thdid_width-1) ); +ex1_ttype_latch: tri_rlmreg_p + generic map (width => ex1_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex1_ttype_offset to ex1_ttype_offset+ex1_ttype_q'length-1), + scout => sov(ex1_ttype_offset to ex1_ttype_offset+ex1_ttype_q'length-1), + din => ex1_ttype_d(0 to ttype_width-1), + dout => ex1_ttype_q(0 to ttype_width-1) ); +ex1_state_latch: tri_rlmreg_p + generic map (width => ex1_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex1_state_offset to ex1_state_offset+ex1_state_q'length-1), + scout => sov(ex1_state_offset to ex1_state_offset+ex1_state_q'length-1), + din => ex1_state_d(0 to state_width), + dout => ex1_state_q(0 to state_width) ); +ex1_pid_latch: tri_rlmreg_p + generic map (width => ex1_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex1_pid_offset to ex1_pid_offset+ex1_pid_q'length-1), + scout => sov(ex1_pid_offset to ex1_pid_offset+ex1_pid_q'length-1), + din => ex1_pid_d(0 to pid_width-1), + dout => ex1_pid_q(0 to pid_width-1) ); +ex2_valid_latch: tri_rlmreg_p + generic map (width => ex2_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex2_valid_offset to ex2_valid_offset+ex2_valid_q'length-1), + scout => sov(ex2_valid_offset to ex2_valid_offset+ex2_valid_q'length-1), + din => ex2_valid_d(0 to thdid_width-1), + dout => ex2_valid_q(0 to thdid_width-1) ); +ex2_flush_latch: tri_rlmreg_p + generic map (width => ex2_flush_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex2_flush_offset to ex2_flush_offset+ex2_flush_q'length-1), + scout => sov(ex2_flush_offset to ex2_flush_offset+ex2_flush_q'length-1), + din => ex2_flush_d(0 to thdid_width-1), + dout => ex2_flush_q(0 to thdid_width-1) ); +ex2_flush_req_latch: tri_rlmreg_p + generic map (width => ex2_flush_req_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex2_flush_req_offset to ex2_flush_req_offset+ex2_flush_req_q'length-1), + scout => sov(ex2_flush_req_offset to ex2_flush_req_offset+ex2_flush_req_q'length-1), + din => ex2_flush_req_d(0 to thdid_width-1), + dout => ex2_flush_req_q(0 to thdid_width-1) ); +ex2_ttype_latch: tri_rlmreg_p + generic map (width => ex2_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex2_ttype_offset to ex2_ttype_offset+ex2_ttype_q'length-1), + scout => sov(ex2_ttype_offset to ex2_ttype_offset+ex2_ttype_q'length-1), + din => ex2_ttype_d(0 to ttype_width-1), + dout => ex2_ttype_q(0 to ttype_width-1) ); +ex2_state_latch: tri_rlmreg_p + generic map (width => ex2_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex2_state_offset to ex2_state_offset+ex2_state_q'length-1), + scout => sov(ex2_state_offset to ex2_state_offset+ex2_state_q'length-1), + din => ex2_state_d(0 to state_width), + dout => ex2_state_q(0 to state_width) ); +ex2_pid_latch: tri_rlmreg_p + generic map (width => ex2_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex2_pid_offset to ex2_pid_offset+ex2_pid_q'length-1), + scout => sov(ex2_pid_offset to ex2_pid_offset+ex2_pid_q'length-1), + din => ex2_pid_d(0 to pid_width-1), + dout => ex2_pid_q(0 to pid_width-1) ); +ex3_valid_latch: tri_rlmreg_p + generic map (width => ex3_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex3_valid_offset to ex3_valid_offset+ex3_valid_q'length-1), + scout => sov(ex3_valid_offset to ex3_valid_offset+ex3_valid_q'length-1), + din => ex3_valid_d(0 to thdid_width-1), + dout => ex3_valid_q(0 to thdid_width-1) ); +ex3_flush_latch: tri_rlmreg_p + generic map (width => ex3_flush_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex3_flush_offset to ex3_flush_offset+ex3_flush_q'length-1), + scout => sov(ex3_flush_offset to ex3_flush_offset+ex3_flush_q'length-1), + din => ex3_flush_d(0 to thdid_width-1), + dout => ex3_flush_q(0 to thdid_width-1) ); +ex3_ttype_latch: tri_rlmreg_p + generic map (width => ex3_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex3_ttype_offset to ex3_ttype_offset+ex3_ttype_q'length-1), + scout => sov(ex3_ttype_offset to ex3_ttype_offset+ex3_ttype_q'length-1), + din => ex3_ttype_d(0 to ttype_width-1), + dout => ex3_ttype_q(0 to ttype_width-1) ); +ex3_state_latch: tri_rlmreg_p + generic map (width => ex3_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex3_state_offset to ex3_state_offset+ex3_state_q'length-1), + scout => sov(ex3_state_offset to ex3_state_offset+ex3_state_q'length-1), + din => ex3_state_d(0 to state_width), + dout => ex3_state_q(0 to state_width) ); +ex3_pid_latch: tri_rlmreg_p + generic map (width => ex3_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex3_pid_offset to ex3_pid_offset+ex3_pid_q'length-1), + scout => sov(ex3_pid_offset to ex3_pid_offset+ex3_pid_q'length-1), + din => ex3_pid_d(0 to pid_width-1), + dout => ex3_pid_q(0 to pid_width-1) ); +ex4_valid_latch: tri_rlmreg_p + generic map (width => ex4_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex4_valid_offset to ex4_valid_offset+ex4_valid_q'length-1), + scout => sov(ex4_valid_offset to ex4_valid_offset+ex4_valid_q'length-1), + din => ex4_valid_d(0 to thdid_width-1), + dout => ex4_valid_q(0 to thdid_width-1) ); +ex4_flush_latch: tri_rlmreg_p + generic map (width => ex4_flush_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex4_flush_offset to ex4_flush_offset+ex4_flush_q'length-1), + scout => sov(ex4_flush_offset to ex4_flush_offset+ex4_flush_q'length-1), + din => ex4_flush_d(0 to thdid_width-1), + dout => ex4_flush_q(0 to thdid_width-1) ); +ex4_ttype_latch: tri_rlmreg_p + generic map (width => ex4_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex4_ttype_offset to ex4_ttype_offset+ex4_ttype_q'length-1), + scout => sov(ex4_ttype_offset to ex4_ttype_offset+ex4_ttype_q'length-1), + din => ex4_ttype_d(0 to ttype_width-1), + dout => ex4_ttype_q(0 to ttype_width-1) ); +ex4_state_latch: tri_rlmreg_p + generic map (width => ex4_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex4_state_offset to ex4_state_offset+ex4_state_q'length-1), + scout => sov(ex4_state_offset to ex4_state_offset+ex4_state_q'length-1), + din => ex4_state_d(0 to state_width), + dout => ex4_state_q(0 to state_width) ); +ex4_pid_latch: tri_rlmreg_p + generic map (width => ex4_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex4_pid_offset to ex4_pid_offset+ex4_pid_q'length-1), + scout => sov(ex4_pid_offset to ex4_pid_offset+ex4_pid_q'length-1), + din => ex4_pid_d(0 to pid_width-1), + dout => ex4_pid_q(0 to pid_width-1) ); +ex5_valid_latch: tri_rlmreg_p + generic map (width => ex5_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex5_valid_offset to ex5_valid_offset+ex5_valid_q'length-1), + scout => sov(ex5_valid_offset to ex5_valid_offset+ex5_valid_q'length-1), + din => ex5_valid_d(0 to thdid_width-1), + dout => ex5_valid_q(0 to thdid_width-1) ); +ex5_flush_latch: tri_rlmreg_p + generic map (width => ex5_flush_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex5_flush_offset to ex5_flush_offset+ex5_flush_q'length-1), + scout => sov(ex5_flush_offset to ex5_flush_offset+ex5_flush_q'length-1), + din => ex5_flush_d(0 to thdid_width-1), + dout => ex5_flush_q(0 to thdid_width-1) ); +ex5_ttype_latch: tri_rlmreg_p + generic map (width => ex5_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex5_ttype_offset to ex5_ttype_offset+ex5_ttype_q'length-1), + scout => sov(ex5_ttype_offset to ex5_ttype_offset+ex5_ttype_q'length-1), + din => ex5_ttype_d(0 to ttype_width-1), + dout => ex5_ttype_q(0 to ttype_width-1) ); +ex5_state_latch: tri_rlmreg_p + generic map (width => ex5_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex5_state_offset to ex5_state_offset+ex5_state_q'length-1), + scout => sov(ex5_state_offset to ex5_state_offset+ex5_state_q'length-1), + din => ex5_state_d(0 to state_width), + dout => ex5_state_q(0 to state_width) ); +ex5_pid_latch: tri_rlmreg_p + generic map (width => ex5_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex5_pid_offset to ex5_pid_offset+ex5_pid_q'length-1), + scout => sov(ex5_pid_offset to ex5_pid_offset+ex5_pid_q'length-1), + din => ex5_pid_d(0 to pid_width-1), + dout => ex5_pid_q(0 to pid_width-1) ); +ex6_valid_latch: tri_rlmreg_p + generic map (width => ex6_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex6_valid_offset to ex6_valid_offset+ex6_valid_q'length-1), + scout => sov(ex6_valid_offset to ex6_valid_offset+ex6_valid_q'length-1), + din => ex6_valid_d(0 to thdid_width-1), + dout => ex6_valid_q(0 to thdid_width-1) ); +ex6_flush_latch: tri_rlmreg_p + generic map (width => ex6_flush_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex6_flush_offset to ex6_flush_offset+ex6_flush_q'length-1), + scout => sov(ex6_flush_offset to ex6_flush_offset+ex6_flush_q'length-1), + din => ex6_flush_d(0 to thdid_width-1), + dout => ex6_flush_q(0 to thdid_width-1) ); +ex6_ttype_latch: tri_rlmreg_p + generic map (width => ex6_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex6_ttype_offset to ex6_ttype_offset+ex6_ttype_q'length-1), + scout => sov(ex6_ttype_offset to ex6_ttype_offset+ex6_ttype_q'length-1), + din => ex6_ttype_d(0 to ttype_width-1), + dout => ex6_ttype_q(0 to ttype_width-1) ); +ex6_state_latch: tri_rlmreg_p + generic map (width => ex6_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex6_state_offset to ex6_state_offset+ex6_state_q'length-1), + scout => sov(ex6_state_offset to ex6_state_offset+ex6_state_q'length-1), + din => ex6_state_d(0 to state_width), + dout => ex6_state_q(0 to state_width) ); +ex6_pid_latch: tri_rlmreg_p + generic map (width => ex6_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex6_pid_offset to ex6_pid_offset+ex6_pid_q'length-1), + scout => sov(ex6_pid_offset to ex6_pid_offset+ex6_pid_q'length-1), + din => ex6_pid_d(0 to pid_width-1), + dout => ex6_pid_q(0 to pid_width-1) ); +tlb_tag0_latch: tri_rlmreg_p + generic map (width => tlb_tag0_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_tag0_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_tag0_offset to tlb_tag0_offset+tlb_tag0_q'length-1), + scout => sov(tlb_tag0_offset to tlb_tag0_offset+tlb_tag0_q'length-1), + din => tlb_tag0_d(0 to tlb_tag_width-1), + dout => tlb_tag0_q(0 to tlb_tag_width-1) ); +tlb_tag1_latch: tri_rlmreg_p + generic map (width => tlb_tag1_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_tag1_offset to tlb_tag1_offset+tlb_tag1_q'length-1), + scout => sov(tlb_tag1_offset to tlb_tag1_offset+tlb_tag1_q'length-1), + din => tlb_tag1_d(0 to tlb_tag_width-1), + dout => tlb_tag1_q(0 to tlb_tag_width-1) ); +tlb_tag2_latch: tri_rlmreg_p + generic map (width => tlb_tag2_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_tag2_offset to tlb_tag2_offset+tlb_tag2_q'length-1), + scout => sov(tlb_tag2_offset to tlb_tag2_offset+tlb_tag2_q'length-1), + din => tlb_tag2_d(0 to tlb_tag_width-1), + dout => tlb_tag2_q(0 to tlb_tag_width-1) ); +tlb_addr_latch: tri_rlmreg_p + generic map (width => tlb_addr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(4), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_addr_offset to tlb_addr_offset+tlb_addr_q'length-1), + scout => sov(tlb_addr_offset to tlb_addr_offset+tlb_addr_q'length-1), + din => tlb_addr_d(0 to tlb_addr_width-1), + dout => tlb_addr_q(0 to tlb_addr_width-1) ); +tlb_addr2_latch: tri_rlmreg_p + generic map (width => tlb_addr2_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(4), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_addr2_offset to tlb_addr2_offset+tlb_addr2_q'length-1), + scout => sov(tlb_addr2_offset to tlb_addr2_offset+tlb_addr2_q'length-1), + din => tlb_addr2_d(0 to tlb_addr_width-1), + dout => tlb_addr2_q(0 to tlb_addr_width-1) ); +tlb_write_latch: tri_rlmreg_p + generic map (width => tlb_write_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(4), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_write_offset to tlb_write_offset+tlb_write_q'length-1), + scout => sov(tlb_write_offset to tlb_write_offset+tlb_write_q'length-1), + din => tlb_write_d(0 to tlb_ways-1), + dout => tlb_write_q(0 to tlb_ways-1) ); +ex6_illeg_instr_latch: tri_rlmreg_p + generic map (width => ex6_illeg_instr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(4), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex6_illeg_instr_offset to ex6_illeg_instr_offset+ex6_illeg_instr_q'length-1), + scout => sov(ex6_illeg_instr_offset to ex6_illeg_instr_offset+ex6_illeg_instr_q'length-1), + din => ex6_illeg_instr_d, + dout => ex6_illeg_instr_q ); +tlb_seq_latch: tri_rlmreg_p + generic map (width => tlb_seq_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_seq_offset to tlb_seq_offset+tlb_seq_q'length-1), + scout => sov(tlb_seq_offset to tlb_seq_offset+tlb_seq_q'length-1), + din => tlb_seq_d(0 to tlb_seq_width-1), + dout => tlb_seq_q(0 to tlb_seq_width-1) ); +derat_taken_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_taken_offset), + scout => sov(derat_taken_offset), + din => derat_taken_d, + dout => derat_taken_q); +xucr4_mmu_mchk_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(xucr4_mmu_mchk_offset), + scout => sov(xucr4_mmu_mchk_offset), + din => xu_mm_xucr4_mmu_mchk, + dout => xu_mm_xucr4_mmu_mchk_q); +snoop_val_latch: tri_rlmreg_p + generic map (width => snoop_val_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_snoop_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(snoop_val_offset to snoop_val_offset+snoop_val_q'length-1), + scout => sov(snoop_val_offset to snoop_val_offset+snoop_val_q'length-1), + din => snoop_val_d, + dout => snoop_val_q ); +snoop_attr_latch: tri_rlmreg_p + generic map (width => snoop_attr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_snoop_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(snoop_attr_offset to snoop_attr_offset+snoop_attr_q'length-1), + scout => sov(snoop_attr_offset to snoop_attr_offset+snoop_attr_q'length-1), + din => snoop_attr_d, + dout => snoop_attr_q ); +snoop_vpn_latch: tri_rlmreg_p + generic map (width => snoop_vpn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_snoop_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(snoop_vpn_offset to snoop_vpn_offset+snoop_vpn_q'length-1), + scout => sov(snoop_vpn_offset to snoop_vpn_offset+snoop_vpn_q'length-1), + din => snoop_vpn_d, + dout => snoop_vpn_q ); +tlb_clr_resv_latch: tri_rlmreg_p + generic map (width => tlb_clr_resv_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(4), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_clr_resv_offset to tlb_clr_resv_offset+tlb_clr_resv_q'length-1), + scout => sov(tlb_clr_resv_offset to tlb_clr_resv_offset+tlb_clr_resv_q'length-1), + din => tlb_clr_resv_d, + dout => tlb_clr_resv_q ); +tlb_resv_match_vec_latch: tri_rlmreg_p + generic map (width => tlb_resv_match_vec_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(4), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv_match_vec_offset to tlb_resv_match_vec_offset+tlb_resv_match_vec_q'length-1), + scout => sov(tlb_resv_match_vec_offset to tlb_resv_match_vec_offset+tlb_resv_match_vec_q'length-1), + din => tlb_resv_match_vec_d, + dout => tlb_resv_match_vec_q ); +tlb_resv0_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv0_valid_offset), + scout => sov(tlb_resv0_valid_offset), + din => tlb_resv0_valid_d, + dout => tlb_resv0_valid_q); +tlb_resv0_epn_latch: tri_rlmreg_p + generic map (width => tlb_resv0_epn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv0_epn_offset to tlb_resv0_epn_offset+tlb_resv0_epn_q'length-1), + scout => sov(tlb_resv0_epn_offset to tlb_resv0_epn_offset+tlb_resv0_epn_q'length-1), + din => tlb_resv0_epn_d, + dout => tlb_resv0_epn_q); +tlb_resv0_pid_latch: tri_rlmreg_p + generic map (width => tlb_resv0_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv0_pid_offset to tlb_resv0_pid_offset+tlb_resv0_pid_q'length-1), + scout => sov(tlb_resv0_pid_offset to tlb_resv0_pid_offset+tlb_resv0_pid_q'length-1), + din => tlb_resv0_pid_d(0 to pid_width-1), + dout => tlb_resv0_pid_q(0 to pid_width-1)); +tlb_resv0_lpid_latch: tri_rlmreg_p + generic map (width => tlb_resv0_lpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv0_lpid_offset to tlb_resv0_lpid_offset+tlb_resv0_lpid_q'length-1), + scout => sov(tlb_resv0_lpid_offset to tlb_resv0_lpid_offset+tlb_resv0_lpid_q'length-1), + din => tlb_resv0_lpid_d(0 to lpid_width-1), + dout => tlb_resv0_lpid_q(0 to lpid_width-1)); +tlb_resv0_as_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv0_as_offset), + scout => sov(tlb_resv0_as_offset), + din => tlb_resv0_as_d, + dout => tlb_resv0_as_q); +tlb_resv0_gs_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv0_gs_offset), + scout => sov(tlb_resv0_gs_offset), + din => tlb_resv0_gs_d, + dout => tlb_resv0_gs_q); +tlb_resv0_ind_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv0_ind_offset), + scout => sov(tlb_resv0_ind_offset), + din => tlb_resv0_ind_d, + dout => tlb_resv0_ind_q); +tlb_resv0_class_latch: tri_rlmreg_p + generic map (width => tlb_resv0_class_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv0_class_offset to tlb_resv0_class_offset+tlb_resv0_class_q'length-1), + scout => sov(tlb_resv0_class_offset to tlb_resv0_class_offset+tlb_resv0_class_q'length-1), + din => tlb_resv0_class_d(0 to class_width-1), + dout => tlb_resv0_class_q(0 to class_width-1)); +tlb_resv1_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv1_valid_offset), + scout => sov(tlb_resv1_valid_offset), + din => tlb_resv1_valid_d, + dout => tlb_resv1_valid_q); +tlb_resv1_epn_latch: tri_rlmreg_p + generic map (width => tlb_resv1_epn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv1_epn_offset to tlb_resv1_epn_offset+tlb_resv1_epn_q'length-1), + scout => sov(tlb_resv1_epn_offset to tlb_resv1_epn_offset+tlb_resv1_epn_q'length-1), + din => tlb_resv1_epn_d, + dout => tlb_resv1_epn_q); +tlb_resv1_pid_latch: tri_rlmreg_p + generic map (width => tlb_resv1_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv1_pid_offset to tlb_resv1_pid_offset+tlb_resv1_pid_q'length-1), + scout => sov(tlb_resv1_pid_offset to tlb_resv1_pid_offset+tlb_resv1_pid_q'length-1), + din => tlb_resv1_pid_d(0 to pid_width-1), + dout => tlb_resv1_pid_q(0 to pid_width-1)); +tlb_resv1_lpid_latch: tri_rlmreg_p + generic map (width => tlb_resv1_lpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv1_lpid_offset to tlb_resv1_lpid_offset+tlb_resv1_lpid_q'length-1), + scout => sov(tlb_resv1_lpid_offset to tlb_resv1_lpid_offset+tlb_resv1_lpid_q'length-1), + din => tlb_resv1_lpid_d(0 to lpid_width-1), + dout => tlb_resv1_lpid_q(0 to lpid_width-1)); +tlb_resv1_as_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv1_as_offset), + scout => sov(tlb_resv1_as_offset), + din => tlb_resv1_as_d, + dout => tlb_resv1_as_q); +tlb_resv1_gs_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv1_gs_offset), + scout => sov(tlb_resv1_gs_offset), + din => tlb_resv1_gs_d, + dout => tlb_resv1_gs_q); +tlb_resv1_ind_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv1_ind_offset), + scout => sov(tlb_resv1_ind_offset), + din => tlb_resv1_ind_d, + dout => tlb_resv1_ind_q); +tlb_resv1_class_latch: tri_rlmreg_p + generic map (width => tlb_resv1_class_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv1_class_offset to tlb_resv1_class_offset+tlb_resv1_class_q'length-1), + scout => sov(tlb_resv1_class_offset to tlb_resv1_class_offset+tlb_resv1_class_q'length-1), + din => tlb_resv1_class_d(0 to class_width-1), + dout => tlb_resv1_class_q(0 to class_width-1)); +tlb_resv2_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv2_valid_offset), + scout => sov(tlb_resv2_valid_offset), + din => tlb_resv2_valid_d, + dout => tlb_resv2_valid_q); +tlb_resv2_epn_latch: tri_rlmreg_p + generic map (width => tlb_resv2_epn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv2_epn_offset to tlb_resv2_epn_offset+tlb_resv2_epn_q'length-1), + scout => sov(tlb_resv2_epn_offset to tlb_resv2_epn_offset+tlb_resv2_epn_q'length-1), + din => tlb_resv2_epn_d, + dout => tlb_resv2_epn_q); +tlb_resv2_pid_latch: tri_rlmreg_p + generic map (width => tlb_resv2_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv2_pid_offset to tlb_resv2_pid_offset+tlb_resv2_pid_q'length-1), + scout => sov(tlb_resv2_pid_offset to tlb_resv2_pid_offset+tlb_resv2_pid_q'length-1), + din => tlb_resv2_pid_d(0 to pid_width-1), + dout => tlb_resv2_pid_q(0 to pid_width-1)); +tlb_resv2_lpid_latch: tri_rlmreg_p + generic map (width => tlb_resv2_lpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv2_lpid_offset to tlb_resv2_lpid_offset+tlb_resv2_lpid_q'length-1), + scout => sov(tlb_resv2_lpid_offset to tlb_resv2_lpid_offset+tlb_resv2_lpid_q'length-1), + din => tlb_resv2_lpid_d(0 to lpid_width-1), + dout => tlb_resv2_lpid_q(0 to lpid_width-1)); +tlb_resv2_as_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv2_as_offset), + scout => sov(tlb_resv2_as_offset), + din => tlb_resv2_as_d, + dout => tlb_resv2_as_q); +tlb_resv2_gs_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv2_gs_offset), + scout => sov(tlb_resv2_gs_offset), + din => tlb_resv2_gs_d, + dout => tlb_resv2_gs_q); +tlb_resv2_ind_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv2_ind_offset), + scout => sov(tlb_resv2_ind_offset), + din => tlb_resv2_ind_d, + dout => tlb_resv2_ind_q); +tlb_resv2_class_latch: tri_rlmreg_p + generic map (width => tlb_resv2_class_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv2_class_offset to tlb_resv2_class_offset+tlb_resv2_class_q'length-1), + scout => sov(tlb_resv2_class_offset to tlb_resv2_class_offset+tlb_resv2_class_q'length-1), + din => tlb_resv2_class_d(0 to class_width-1), + dout => tlb_resv2_class_q(0 to class_width-1)); +tlb_resv3_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv3_valid_offset), + scout => sov(tlb_resv3_valid_offset), + din => tlb_resv3_valid_d, + dout => tlb_resv3_valid_q); +tlb_resv3_epn_latch: tri_rlmreg_p + generic map (width => tlb_resv3_epn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv3_epn_offset to tlb_resv3_epn_offset+tlb_resv3_epn_q'length-1), + scout => sov(tlb_resv3_epn_offset to tlb_resv3_epn_offset+tlb_resv3_epn_q'length-1), + din => tlb_resv3_epn_d, + dout => tlb_resv3_epn_q); +tlb_resv3_pid_latch: tri_rlmreg_p + generic map (width => tlb_resv3_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv3_pid_offset to tlb_resv3_pid_offset+tlb_resv3_pid_q'length-1), + scout => sov(tlb_resv3_pid_offset to tlb_resv3_pid_offset+tlb_resv3_pid_q'length-1), + din => tlb_resv3_pid_d(0 to pid_width-1), + dout => tlb_resv3_pid_q(0 to pid_width-1)); +tlb_resv3_lpid_latch: tri_rlmreg_p + generic map (width => tlb_resv3_lpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv3_lpid_offset to tlb_resv3_lpid_offset+tlb_resv3_lpid_q'length-1), + scout => sov(tlb_resv3_lpid_offset to tlb_resv3_lpid_offset+tlb_resv3_lpid_q'length-1), + din => tlb_resv3_lpid_d(0 to lpid_width-1), + dout => tlb_resv3_lpid_q(0 to lpid_width-1)); +tlb_resv3_as_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv3_as_offset), + scout => sov(tlb_resv3_as_offset), + din => tlb_resv3_as_d, + dout => tlb_resv3_as_q); +tlb_resv3_gs_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv3_gs_offset), + scout => sov(tlb_resv3_gs_offset), + din => tlb_resv3_gs_d, + dout => tlb_resv3_gs_q); +tlb_resv3_ind_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv3_ind_offset), + scout => sov(tlb_resv3_ind_offset), + din => tlb_resv3_ind_d, + dout => tlb_resv3_ind_q); +tlb_resv3_class_latch: tri_rlmreg_p + generic map (width => tlb_resv3_class_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv3_class_offset to tlb_resv3_class_offset+tlb_resv3_class_q'length-1), + scout => sov(tlb_resv3_class_offset to tlb_resv3_class_offset+tlb_resv3_class_q'length-1), + din => tlb_resv3_class_d(0 to class_width-1), + dout => tlb_resv3_class_q(0 to class_width-1)); +ptereload_req_pte_latch: tri_rlmreg_p + generic map (width => ptereload_req_pte_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ptereload_req_valid, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ptereload_req_pte_offset to ptereload_req_pte_offset+ptereload_req_pte_q'length-1), + scout => sov(ptereload_req_pte_offset to ptereload_req_pte_offset+ptereload_req_pte_q'length-1), + din => ptereload_req_pte_d, + dout => ptereload_req_pte_q ); +tlb_delayed_act_latch: tri_rlmreg_p + generic map (width => tlb_delayed_act_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_delayed_act_offset to tlb_delayed_act_offset+tlb_delayed_act_q'length-1), + scout => sov(tlb_delayed_act_offset to tlb_delayed_act_offset+tlb_delayed_act_q'length-1), + din => tlb_delayed_act_d, + dout => tlb_delayed_act_q ); +tlb_ctl_spare_latch: tri_rlmreg_p + generic map (width => tlb_ctl_spare_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_ctl_spare_offset to tlb_ctl_spare_offset+tlb_ctl_spare_q'length-1), + scout => sov(tlb_ctl_spare_offset to tlb_ctl_spare_offset+tlb_ctl_spare_q'length-1), + din => tlb_ctl_spare_q, + dout => tlb_ctl_spare_q ); +tlb_resv0_tag1_match_latch : tri_regk + generic map (width => 11, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => xu_mm_ccr2_notlb_b, + forcee => pc_func_slp_nsl_force, + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_nsl_thold_0_b, + din(0) => tlb_resv0_tag0_lpid_match, + din(1) => tlb_resv0_tag0_pid_match, + din(2) => tlb_resv0_tag0_as_snoop_match, + din(3) => tlb_resv0_tag0_gs_snoop_match, + din(4) => tlb_resv0_tag0_as_tlbwe_match, + din(5) => tlb_resv0_tag0_gs_tlbwe_match, + din(6) => tlb_resv0_tag0_ind_match, + din(7) => tlb_resv0_tag0_epn_loc_match, + din(8) => tlb_resv0_tag0_epn_glob_match, + din(9) => tlb_resv0_tag0_class_match, + din(10) => tlb_seq_snoop_resv, + dout(0) => tlb_resv0_tag1_lpid_match, + dout(1) => tlb_resv0_tag1_pid_match, + dout(2) => tlb_resv0_tag1_as_snoop_match, + dout(3) => tlb_resv0_tag1_gs_snoop_match, + dout(4) => tlb_resv0_tag1_as_tlbwe_match, + dout(5) => tlb_resv0_tag1_gs_tlbwe_match, + dout(6) => tlb_resv0_tag1_ind_match, + dout(7) => tlb_resv0_tag1_epn_loc_match, + dout(8) => tlb_resv0_tag1_epn_glob_match, + dout(9) => tlb_resv0_tag1_class_match, + dout(10) => tlb_seq_snoop_resv_q(0)); +tlb_resv1_tag1_match_latch : tri_regk + generic map (width => 11, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => xu_mm_ccr2_notlb_b, + forcee => pc_func_slp_nsl_force, + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_nsl_thold_0_b, + din(0) => tlb_resv1_tag0_lpid_match, + din(1) => tlb_resv1_tag0_pid_match, + din(2) => tlb_resv1_tag0_as_snoop_match, + din(3) => tlb_resv1_tag0_gs_snoop_match, + din(4) => tlb_resv1_tag0_as_tlbwe_match, + din(5) => tlb_resv1_tag0_gs_tlbwe_match, + din(6) => tlb_resv1_tag0_ind_match, + din(7) => tlb_resv1_tag0_epn_loc_match, + din(8) => tlb_resv1_tag0_epn_glob_match, + din(9) => tlb_resv1_tag0_class_match, + din(10) => tlb_seq_snoop_resv, + dout(0) => tlb_resv1_tag1_lpid_match, + dout(1) => tlb_resv1_tag1_pid_match, + dout(2) => tlb_resv1_tag1_as_snoop_match, + dout(3) => tlb_resv1_tag1_gs_snoop_match, + dout(4) => tlb_resv1_tag1_as_tlbwe_match, + dout(5) => tlb_resv1_tag1_gs_tlbwe_match, + dout(6) => tlb_resv1_tag1_ind_match, + dout(7) => tlb_resv1_tag1_epn_loc_match, + dout(8) => tlb_resv1_tag1_epn_glob_match, + dout(9) => tlb_resv1_tag1_class_match, + dout(10) => tlb_seq_snoop_resv_q(1)); +tlb_resv2_tag1_match_latch : tri_regk + generic map (width => 11, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => xu_mm_ccr2_notlb_b, + forcee => pc_func_slp_nsl_force, + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_nsl_thold_0_b, + din(0) => tlb_resv2_tag0_lpid_match, + din(1) => tlb_resv2_tag0_pid_match, + din(2) => tlb_resv2_tag0_as_snoop_match, + din(3) => tlb_resv2_tag0_gs_snoop_match, + din(4) => tlb_resv2_tag0_as_tlbwe_match, + din(5) => tlb_resv2_tag0_gs_tlbwe_match, + din(6) => tlb_resv2_tag0_ind_match, + din(7) => tlb_resv2_tag0_epn_loc_match, + din(8) => tlb_resv2_tag0_epn_glob_match, + din(9) => tlb_resv2_tag0_class_match, + din(10) => tlb_seq_snoop_resv, + dout(0) => tlb_resv2_tag1_lpid_match, + dout(1) => tlb_resv2_tag1_pid_match, + dout(2) => tlb_resv2_tag1_as_snoop_match, + dout(3) => tlb_resv2_tag1_gs_snoop_match, + dout(4) => tlb_resv2_tag1_as_tlbwe_match, + dout(5) => tlb_resv2_tag1_gs_tlbwe_match, + dout(6) => tlb_resv2_tag1_ind_match, + dout(7) => tlb_resv2_tag1_epn_loc_match, + dout(8) => tlb_resv2_tag1_epn_glob_match, + dout(9) => tlb_resv2_tag1_class_match, + dout(10) => tlb_seq_snoop_resv_q(2)); +tlb_resv3_tag1_match_latch : tri_regk + generic map (width => 11, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => xu_mm_ccr2_notlb_b, + forcee => pc_func_slp_nsl_force, + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_nsl_thold_0_b, + din(0) => tlb_resv3_tag0_lpid_match, + din(1) => tlb_resv3_tag0_pid_match, + din(2) => tlb_resv3_tag0_as_snoop_match, + din(3) => tlb_resv3_tag0_gs_snoop_match, + din(4) => tlb_resv3_tag0_as_tlbwe_match, + din(5) => tlb_resv3_tag0_gs_tlbwe_match, + din(6) => tlb_resv3_tag0_ind_match, + din(7) => tlb_resv3_tag0_epn_loc_match, + din(8) => tlb_resv3_tag0_epn_glob_match, + din(9) => tlb_resv3_tag0_class_match, + din(10) => tlb_seq_snoop_resv, + dout(0) => tlb_resv3_tag1_lpid_match, + dout(1) => tlb_resv3_tag1_pid_match, + dout(2) => tlb_resv3_tag1_as_snoop_match, + dout(3) => tlb_resv3_tag1_gs_snoop_match, + dout(4) => tlb_resv3_tag1_as_tlbwe_match, + dout(5) => tlb_resv3_tag1_gs_tlbwe_match, + dout(6) => tlb_resv3_tag1_ind_match, + dout(7) => tlb_resv3_tag1_epn_loc_match, + dout(8) => tlb_resv3_tag1_epn_glob_match, + dout(9) => tlb_resv3_tag1_class_match, + dout(10) => tlb_seq_snoop_resv_q(3)); +perv_2to1_reg: tri_plat + generic map (width => 5, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ccflush_dc, + din(0) => pc_func_sl_thold_2, + din(1) => pc_func_slp_sl_thold_2, + din(2) => pc_func_slp_nsl_thold_2, + din(3) => pc_sg_2, + din(4) => pc_fce_2, + q(0) => pc_func_sl_thold_1, + q(1) => pc_func_slp_sl_thold_1, + q(2) => pc_func_slp_nsl_thold_1, + q(3) => pc_sg_1, + q(4) => pc_fce_1); +perv_1to0_reg: tri_plat + generic map (width => 5, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ccflush_dc, + din(0) => pc_func_sl_thold_1, + din(1) => pc_func_slp_sl_thold_1, + din(2) => pc_func_slp_nsl_thold_1, + din(3) => pc_sg_1, + din(4) => pc_fce_1, + q(0) => pc_func_sl_thold_0, + q(1) => pc_func_slp_sl_thold_0, + q(2) => pc_func_slp_nsl_thold_0, + q(3) => pc_sg_0, + q(4) => pc_fce_0); +perv_lcbor_func_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b, + thold => pc_func_sl_thold_0, + sg => pc_sg_0, + act_dis => lcb_act_dis_dc, + forcee => pc_func_sl_force, + thold_b => pc_func_sl_thold_0_b); +perv_lcbor_func_slp_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b, + thold => pc_func_slp_sl_thold_0, + sg => pc_sg_0, + act_dis => lcb_act_dis_dc, + forcee => pc_func_slp_sl_force, + thold_b => pc_func_slp_sl_thold_0_b); +perv_nsl_lcbor: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b, + thold => pc_func_slp_nsl_thold_0, + sg => pc_fce_0, + act_dis => tidn, + forcee => pc_func_slp_nsl_force, + thold_b => pc_func_slp_nsl_thold_0_b); +siv(0 TO scan_right) <= sov(1 to scan_right) & ac_func_scan_in; +ac_func_scan_out <= sov(0); +END MMQ_TLB_CTL; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/mmq_tlb_lrat.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/mmq_tlb_lrat.vhdl new file mode 100644 index 0000000..8f5b5c7 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/mmq_tlb_lrat.vhdl @@ -0,0 +1,4085 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; +use ieee.std_logic_1164.all; +library ibm; +use ibm.std_ulogic_unsigned.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_support.all; +library support; +use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity mmq_tlb_lrat is + generic(thdid_width : integer := 4; + ttype_width : integer := 5; + lpid_width : integer := 8; + spr_data_width : integer := 64; + real_addr_width : integer := 42; + rpn_width : integer := 30; + epn_width : integer := 52; + lrat_num_entry : natural := 8; + lrat_num_entry_log2 : natural := 3; + lrat_maxsize_log2 : integer := 40; + lrat_minsize_log2 : integer := 20; + expand_type : integer := 2 ); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + +tc_ccflush_dc : in std_ulogic; +tc_scan_dis_dc_b : in std_ulogic; +tc_scan_diag_dc : in std_ulogic; +tc_lbist_en_dc : in std_ulogic; +lcb_d_mode_dc : in std_ulogic; +lcb_clkoff_dc_b : in std_ulogic; +lcb_act_dis_dc : in std_ulogic; +lcb_mpw1_dc_b : in std_ulogic_vector(0 to 4); +lcb_mpw2_dc_b : in std_ulogic; +lcb_delay_lclkr_dc : in std_ulogic_vector(0 to 4); +ac_func_scan_in :in std_ulogic; +ac_func_scan_out :out std_ulogic; +pc_sg_2 : in std_ulogic; +pc_func_sl_thold_2 : in std_ulogic; +pc_func_slp_sl_thold_2 : in std_ulogic; +xu_mm_ccr2_notlb_b : in std_ulogic; +tlb_delayed_act : in std_ulogic_vector(20 to 23); +mmucr2_act_override : in std_ulogic; +tlb_ctl_ex3_valid : in std_ulogic_vector(0 to thdid_width-1); +tlb_ctl_ex3_ttype : in std_ulogic_vector(0 to ttype_width-1); +xu_ex3_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_ex4_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_ex5_flush : in std_ulogic_vector(0 to thdid_width-1); +tlb_tag0_epn : in std_ulogic_vector(64-real_addr_width to 51); +tlb_tag0_thdid : in std_ulogic_vector(0 to thdid_width-1); +tlb_tag0_type : in std_ulogic_vector(0 to 7); +tlb_tag0_lpid : in std_ulogic_vector(0 to lpid_width-1); +tlb_tag0_size : in std_ulogic_vector(0 to 3); +tlb_tag0_atsel : in std_ulogic; +tlb_tag0_addr_cap : in std_ulogic; +ex6_illeg_instr : in std_ulogic_vector(0 to 1); +pte_tag0_lpn : in std_ulogic_vector(64-real_addr_width to 51); +pte_tag0_lpid : in std_ulogic_vector(0 to lpid_width-1); +mas0_0_atsel : in std_ulogic; +mas0_0_esel : in std_ulogic_vector(0 to lrat_num_entry_log2-1); +mas0_0_hes : in std_ulogic; +mas0_0_wq : in std_ulogic_vector(0 to 1); +mas1_0_v : in std_ulogic; +mas1_0_tsize : in std_ulogic_vector(0 to 3); +mas2_0_epn : in std_ulogic_vector(64-real_addr_width to 51); +mas7_0_rpnu : in std_ulogic_vector(22 to 31); +mas3_0_rpnl : in std_ulogic_vector(32 to 51); +mas8_0_tlpid : in std_ulogic_vector(0 to lpid_width-1); +mmucr3_0_x : in std_ulogic; +mas0_1_atsel : in std_ulogic; +mas0_1_esel : in std_ulogic_vector(0 to lrat_num_entry_log2-1); +mas0_1_hes : in std_ulogic; +mas0_1_wq : in std_ulogic_vector(0 to 1); +mas1_1_v : in std_ulogic; +mas1_1_tsize : in std_ulogic_vector(0 to 3); +mas2_1_epn : in std_ulogic_vector(64-real_addr_width to 51); +mas7_1_rpnu : in std_ulogic_vector(22 to 31); +mas3_1_rpnl : in std_ulogic_vector(32 to 51); +mas8_1_tlpid : in std_ulogic_vector(0 to lpid_width-1); +mmucr3_1_x : in std_ulogic; +mas0_2_atsel : in std_ulogic; +mas0_2_esel : in std_ulogic_vector(0 to lrat_num_entry_log2-1); +mas0_2_hes : in std_ulogic; +mas0_2_wq : in std_ulogic_vector(0 to 1); +mas1_2_v : in std_ulogic; +mas1_2_tsize : in std_ulogic_vector(0 to 3); +mas2_2_epn : in std_ulogic_vector(64-real_addr_width to 51); +mas7_2_rpnu : in std_ulogic_vector(22 to 31); +mas3_2_rpnl : in std_ulogic_vector(32 to 51); +mas8_2_tlpid : in std_ulogic_vector(0 to lpid_width-1); +mmucr3_2_x : in std_ulogic; +mas0_3_atsel : in std_ulogic; +mas0_3_esel : in std_ulogic_vector(0 to lrat_num_entry_log2-1); +mas0_3_hes : in std_ulogic; +mas0_3_wq : in std_ulogic_vector(0 to 1); +mas1_3_v : in std_ulogic; +mas1_3_tsize : in std_ulogic_vector(0 to 3); +mas2_3_epn : in std_ulogic_vector(64-real_addr_width to 51); +mas7_3_rpnu : in std_ulogic_vector(22 to 31); +mas3_3_rpnl : in std_ulogic_vector(32 to 51); +mas8_3_tlpid : in std_ulogic_vector(0 to lpid_width-1); +mmucr3_3_x : in std_ulogic; +lrat_mmucr3_x : out std_ulogic; +lrat_mas0_esel : out std_ulogic_vector(0 to 2); +lrat_mas1_v : out std_ulogic; +lrat_mas1_tsize : out std_ulogic_vector(0 to 3); +lrat_mas2_epn : out std_ulogic_vector(0 to 51); +lrat_mas3_rpnl : out std_ulogic_vector(32 to 51); +lrat_mas7_rpnu : out std_ulogic_vector(22 to 31); +lrat_mas8_tlpid : out std_ulogic_vector(0 to lpid_width-1); +lrat_mas_tlbre : out std_ulogic; +lrat_mas_tlbsx_hit : out std_ulogic; +lrat_mas_tlbsx_miss : out std_ulogic; +lrat_mas_thdid : out std_ulogic_vector(0 to thdid_width-1); +lrat_tag3_lpn : out std_ulogic_vector(64-real_addr_width to 51); +lrat_tag3_rpn : out std_ulogic_vector(64-real_addr_width to 51); +lrat_tag3_hit_status : out std_ulogic_vector(0 to 3); +lrat_tag3_hit_entry : out std_ulogic_vector(0 to lrat_num_entry_log2-1); +lrat_tag4_lpn : out std_ulogic_vector(64-real_addr_width to 51); +lrat_tag4_rpn : out std_ulogic_vector(64-real_addr_width to 51); +lrat_tag4_hit_status : out std_ulogic_vector(0 to 3); +lrat_tag4_hit_entry : out std_ulogic_vector(0 to lrat_num_entry_log2-1); +lrat_dbg_tag1_addr_enable : out std_ulogic; +lrat_dbg_tag2_matchline_q : out std_ulogic_vector(0 to 7); +lrat_dbg_entry0_addr_match : out std_ulogic; +lrat_dbg_entry0_lpid_match : out std_ulogic; +lrat_dbg_entry0_entry_v : out std_ulogic; +lrat_dbg_entry0_entry_x : out std_ulogic; +lrat_dbg_entry0_size : out std_ulogic_vector(0 to 3); +lrat_dbg_entry1_addr_match : out std_ulogic; +lrat_dbg_entry1_lpid_match : out std_ulogic; +lrat_dbg_entry1_entry_v : out std_ulogic; +lrat_dbg_entry1_entry_x : out std_ulogic; +lrat_dbg_entry1_size : out std_ulogic_vector(0 to 3); +lrat_dbg_entry2_addr_match : out std_ulogic; +lrat_dbg_entry2_lpid_match : out std_ulogic; +lrat_dbg_entry2_entry_v : out std_ulogic; +lrat_dbg_entry2_entry_x : out std_ulogic; +lrat_dbg_entry2_size : out std_ulogic_vector(0 to 3); +lrat_dbg_entry3_addr_match : out std_ulogic; +lrat_dbg_entry3_lpid_match : out std_ulogic; +lrat_dbg_entry3_entry_v : out std_ulogic; +lrat_dbg_entry3_entry_x : out std_ulogic; +lrat_dbg_entry3_size : out std_ulogic_vector(0 to 3); +lrat_dbg_entry4_addr_match : out std_ulogic; +lrat_dbg_entry4_lpid_match : out std_ulogic; +lrat_dbg_entry4_entry_v : out std_ulogic; +lrat_dbg_entry4_entry_x : out std_ulogic; +lrat_dbg_entry4_size : out std_ulogic_vector(0 to 3); +lrat_dbg_entry5_addr_match : out std_ulogic; +lrat_dbg_entry5_lpid_match : out std_ulogic; +lrat_dbg_entry5_entry_v : out std_ulogic; +lrat_dbg_entry5_entry_x : out std_ulogic; +lrat_dbg_entry5_size : out std_ulogic_vector(0 to 3); +lrat_dbg_entry6_addr_match : out std_ulogic; +lrat_dbg_entry6_lpid_match : out std_ulogic; +lrat_dbg_entry6_entry_v : out std_ulogic; +lrat_dbg_entry6_entry_x : out std_ulogic; +lrat_dbg_entry6_size : out std_ulogic_vector(0 to 3); +lrat_dbg_entry7_addr_match : out std_ulogic; +lrat_dbg_entry7_lpid_match : out std_ulogic; +lrat_dbg_entry7_entry_v : out std_ulogic; +lrat_dbg_entry7_entry_x : out std_ulogic; +lrat_dbg_entry7_size : out std_ulogic_vector(0 to 3) +); +end mmq_tlb_lrat; +ARCHITECTURE MMQ_TLB_LRAT + OF MMQ_TLB_LRAT + IS +component mmq_tlb_lrat_matchline + generic (real_addr_width : integer := 42; + lpid_width : integer := 8; + lrat_maxsize_log2 : integer := 40; + lrat_minsize_log2 : integer := 20; + have_xbit : integer := 1; + num_pgsizes : integer := 8; + have_cmpmask : integer := 1; + cmpmask_width : integer := 7); +port( + vdd : inout power_logic; + gnd : inout power_logic; + addr_in : in std_ulogic_vector(64-real_addr_width to 64-lrat_minsize_log2-1); + addr_enable : in std_ulogic; + entry_size : in std_ulogic_vector(0 to 3); + entry_cmpmask : in std_ulogic_vector(0 to cmpmask_width-1); + entry_xbit : in std_ulogic; + entry_xbitmask : in std_ulogic_vector(0 to cmpmask_width-1); + entry_lpn : in std_ulogic_vector(64-real_addr_width to 64-lrat_minsize_log2-1); + entry_lpid : in std_ulogic_vector(0 to lpid_width-1); + comp_lpid : in std_ulogic_vector(0 to lpid_width-1); + lpid_enable : in std_ulogic; + entry_v : in std_ulogic; + + match : out std_ulogic; + dbg_addr_match : out std_ulogic; + dbg_lpid_match : out std_ulogic +); +end component; +constant MMU_Mode_Value : std_ulogic := '0'; +constant TLB_PgSize_1GB : std_ulogic_vector(0 to 3) := "1010"; +constant TLB_PgSize_256MB : std_ulogic_vector(0 to 3) := "1001"; +constant TLB_PgSize_16MB : std_ulogic_vector(0 to 3) := "0111"; +constant TLB_PgSize_1MB : std_ulogic_vector(0 to 3) := "0101"; +constant TLB_PgSize_64KB : std_ulogic_vector(0 to 3) := "0011"; +constant TLB_PgSize_4KB : std_ulogic_vector(0 to 3) := "0001"; +constant LRAT_PgSize_1TB : std_ulogic_vector(0 to 3) := "1111"; +constant LRAT_PgSize_256GB : std_ulogic_vector(0 to 3) := "1110"; +constant LRAT_PgSize_16GB : std_ulogic_vector(0 to 3) := "1100"; +constant LRAT_PgSize_4GB : std_ulogic_vector(0 to 3) := "1011"; +constant LRAT_PgSize_1GB : std_ulogic_vector(0 to 3) := "1010"; +constant LRAT_PgSize_256MB : std_ulogic_vector(0 to 3) := "1001"; +constant LRAT_PgSize_16MB : std_ulogic_vector(0 to 3) := "0111"; +constant LRAT_PgSize_1MB : std_ulogic_vector(0 to 3) := "0101"; +constant LRAT_PgSize_1TB_log2 : integer := 40; +constant LRAT_PgSize_256GB_log2 : integer := 38; +constant LRAT_PgSize_16GB_log2 : integer := 34; +constant LRAT_PgSize_4GB_log2 : integer := 32; +constant LRAT_PgSize_1GB_log2 : integer := 30; +constant LRAT_PgSize_256MB_log2 : integer := 28; +constant LRAT_PgSize_16MB_log2 : integer := 24; +constant LRAT_PgSize_1MB_log2 : integer := 20; +constant tagpos_type : natural := 0; +constant tagpos_type_derat : natural := tagpos_type; +constant tagpos_type_ierat : natural := tagpos_type+1; +constant tagpos_type_tlbsx : natural := tagpos_type+2; +constant tagpos_type_tlbsrx : natural := tagpos_type+3; +constant tagpos_type_snoop : natural := tagpos_type+4; +constant tagpos_type_tlbre : natural := tagpos_type+5; +constant tagpos_type_tlbwe : natural := tagpos_type+6; +constant tagpos_type_ptereload : natural := tagpos_type+7; +constant ex4_valid_offset : natural := 0; +constant ex4_ttype_offset : natural := ex4_valid_offset + thdid_width; +constant ex5_valid_offset : natural := ex4_ttype_offset + ttype_width; +constant ex5_ttype_offset : natural := ex5_valid_offset + thdid_width; +constant ex5_esel_offset : natural := ex5_ttype_offset + ttype_width; +constant ex5_atsel_offset : natural := ex5_esel_offset + 3; +constant ex5_wq_offset : natural := ex5_atsel_offset + 1; +constant ex5_hes_offset : natural := ex5_wq_offset + 2; +constant ex6_valid_offset : natural := ex5_hes_offset + 1; +constant ex6_ttype_offset : natural := ex6_valid_offset + thdid_width; +constant ex6_esel_offset : natural := ex6_ttype_offset + ttype_width; +constant ex6_atsel_offset : natural := ex6_esel_offset + 3; +constant ex6_wq_offset : natural := ex6_atsel_offset + 1; +constant ex6_hes_offset : natural := ex6_wq_offset + 2; +constant lrat_tag1_lpn_offset : natural := ex6_hes_offset + 1; +constant lrat_tag2_lpn_offset : natural := lrat_tag1_lpn_offset + rpn_width; +constant lrat_tag3_lpn_offset : natural := lrat_tag2_lpn_offset + rpn_width; +constant lrat_tag3_rpn_offset : natural := lrat_tag3_lpn_offset + rpn_width; +constant lrat_tag4_lpn_offset : natural := lrat_tag3_rpn_offset + rpn_width; +constant lrat_tag4_rpn_offset : natural := lrat_tag4_lpn_offset + rpn_width; +constant lrat_tag1_lpid_offset : natural := lrat_tag4_rpn_offset + rpn_width; +constant lrat_tag1_size_offset : natural := lrat_tag1_lpid_offset + lpid_width; +constant lrat_tag2_size_offset : natural := lrat_tag1_size_offset + 4; +constant lrat_tag2_entry_size_offset : natural := lrat_tag2_size_offset + 4; +constant lrat_tag2_matchline_offset : natural := lrat_tag2_entry_size_offset + 4; +constant lrat_tag3_hit_status_offset : natural := lrat_tag2_matchline_offset + lrat_num_entry; +constant lrat_tag3_hit_entry_offset : natural := lrat_tag3_hit_status_offset + 4; +constant lrat_tag4_hit_status_offset : natural := lrat_tag3_hit_entry_offset + lrat_num_entry_log2; +constant lrat_tag4_hit_entry_offset : natural := lrat_tag4_hit_status_offset + 4; +constant tlb_addr_cap_offset : natural := lrat_tag4_hit_entry_offset + lrat_num_entry_log2; +constant lrat_entry0_lpn_offset : natural := tlb_addr_cap_offset + 2; +constant lrat_entry0_rpn_offset : natural := lrat_entry0_lpn_offset + real_addr_width - lrat_minsize_log2; +constant lrat_entry0_lpid_offset : natural := lrat_entry0_rpn_offset + real_addr_width - lrat_minsize_log2; +constant lrat_entry0_size_offset : natural := lrat_entry0_lpid_offset + lpid_width; +constant lrat_entry0_cmpmask_offset : natural := lrat_entry0_size_offset + 4; +constant lrat_entry0_xbitmask_offset : natural := lrat_entry0_cmpmask_offset + 7; +constant lrat_entry0_xbit_offset : natural := lrat_entry0_xbitmask_offset + 7; +constant lrat_entry0_valid_offset : natural := lrat_entry0_xbit_offset + 1; +constant lrat_entry1_lpn_offset : natural := lrat_entry0_valid_offset + 1; +constant lrat_entry1_rpn_offset : natural := lrat_entry1_lpn_offset + real_addr_width - lrat_minsize_log2; +constant lrat_entry1_lpid_offset : natural := lrat_entry1_rpn_offset + real_addr_width - lrat_minsize_log2; +constant lrat_entry1_size_offset : natural := lrat_entry1_lpid_offset + lpid_width; +constant lrat_entry1_cmpmask_offset : natural := lrat_entry1_size_offset + 4; +constant lrat_entry1_xbitmask_offset : natural := lrat_entry1_cmpmask_offset + 7; +constant lrat_entry1_xbit_offset : natural := lrat_entry1_xbitmask_offset + 7; +constant lrat_entry1_valid_offset : natural := lrat_entry1_xbit_offset + 1; +constant lrat_entry2_lpn_offset : natural := lrat_entry1_valid_offset + 1; +constant lrat_entry2_rpn_offset : natural := lrat_entry2_lpn_offset + real_addr_width - lrat_minsize_log2; +constant lrat_entry2_lpid_offset : natural := lrat_entry2_rpn_offset + real_addr_width - lrat_minsize_log2; +constant lrat_entry2_size_offset : natural := lrat_entry2_lpid_offset + lpid_width; +constant lrat_entry2_cmpmask_offset : natural := lrat_entry2_size_offset + 4; +constant lrat_entry2_xbitmask_offset : natural := lrat_entry2_cmpmask_offset + 7; +constant lrat_entry2_xbit_offset : natural := lrat_entry2_xbitmask_offset + 7; +constant lrat_entry2_valid_offset : natural := lrat_entry2_xbit_offset + 1; +constant lrat_entry3_lpn_offset : natural := lrat_entry2_valid_offset + 1; +constant lrat_entry3_rpn_offset : natural := lrat_entry3_lpn_offset + real_addr_width - lrat_minsize_log2; +constant lrat_entry3_lpid_offset : natural := lrat_entry3_rpn_offset + real_addr_width - lrat_minsize_log2; +constant lrat_entry3_size_offset : natural := lrat_entry3_lpid_offset + lpid_width; +constant lrat_entry3_cmpmask_offset : natural := lrat_entry3_size_offset + 4; +constant lrat_entry3_xbitmask_offset : natural := lrat_entry3_cmpmask_offset + 7; +constant lrat_entry3_xbit_offset : natural := lrat_entry3_xbitmask_offset + 7; +constant lrat_entry3_valid_offset : natural := lrat_entry3_xbit_offset + 1; +constant lrat_entry4_lpn_offset : natural := lrat_entry3_valid_offset + 1; +constant lrat_entry4_rpn_offset : natural := lrat_entry4_lpn_offset + real_addr_width - lrat_minsize_log2; +constant lrat_entry4_lpid_offset : natural := lrat_entry4_rpn_offset + real_addr_width - lrat_minsize_log2; +constant lrat_entry4_size_offset : natural := lrat_entry4_lpid_offset + lpid_width; +constant lrat_entry4_cmpmask_offset : natural := lrat_entry4_size_offset + 4; +constant lrat_entry4_xbitmask_offset : natural := lrat_entry4_cmpmask_offset + 7; +constant lrat_entry4_xbit_offset : natural := lrat_entry4_xbitmask_offset + 7; +constant lrat_entry4_valid_offset : natural := lrat_entry4_xbit_offset + 1; +constant lrat_entry5_lpn_offset : natural := lrat_entry4_valid_offset + 1; +constant lrat_entry5_rpn_offset : natural := lrat_entry5_lpn_offset + real_addr_width - lrat_minsize_log2; +constant lrat_entry5_lpid_offset : natural := lrat_entry5_rpn_offset + real_addr_width - lrat_minsize_log2; +constant lrat_entry5_size_offset : natural := lrat_entry5_lpid_offset + lpid_width; +constant lrat_entry5_cmpmask_offset : natural := lrat_entry5_size_offset + 4; +constant lrat_entry5_xbitmask_offset : natural := lrat_entry5_cmpmask_offset + 7; +constant lrat_entry5_xbit_offset : natural := lrat_entry5_xbitmask_offset + 7; +constant lrat_entry5_valid_offset : natural := lrat_entry5_xbit_offset + 1; +constant lrat_entry6_lpn_offset : natural := lrat_entry5_valid_offset + 1; +constant lrat_entry6_rpn_offset : natural := lrat_entry6_lpn_offset + real_addr_width - lrat_minsize_log2; +constant lrat_entry6_lpid_offset : natural := lrat_entry6_rpn_offset + real_addr_width - lrat_minsize_log2; +constant lrat_entry6_size_offset : natural := lrat_entry6_lpid_offset + lpid_width; +constant lrat_entry6_cmpmask_offset : natural := lrat_entry6_size_offset + 4; +constant lrat_entry6_xbitmask_offset : natural := lrat_entry6_cmpmask_offset + 7; +constant lrat_entry6_xbit_offset : natural := lrat_entry6_xbitmask_offset + 7; +constant lrat_entry6_valid_offset : natural := lrat_entry6_xbit_offset + 1; +constant lrat_entry7_lpn_offset : natural := lrat_entry6_valid_offset + 1; +constant lrat_entry7_rpn_offset : natural := lrat_entry7_lpn_offset + real_addr_width - lrat_minsize_log2; +constant lrat_entry7_lpid_offset : natural := lrat_entry7_rpn_offset + real_addr_width - lrat_minsize_log2; +constant lrat_entry7_size_offset : natural := lrat_entry7_lpid_offset + lpid_width; +constant lrat_entry7_cmpmask_offset : natural := lrat_entry7_size_offset + 4; +constant lrat_entry7_xbitmask_offset : natural := lrat_entry7_cmpmask_offset + 7; +constant lrat_entry7_xbit_offset : natural := lrat_entry7_xbitmask_offset + 7; +constant lrat_entry7_valid_offset : natural := lrat_entry7_xbit_offset + 1; +constant lrat_datain_lpn_offset : natural := lrat_entry7_valid_offset + 1; +constant lrat_datain_rpn_offset : natural := lrat_datain_lpn_offset + real_addr_width - lrat_minsize_log2; +constant lrat_datain_lpid_offset : natural := lrat_datain_rpn_offset + real_addr_width - lrat_minsize_log2; +constant lrat_datain_size_offset : natural := lrat_datain_lpid_offset + lpid_width; +constant lrat_datain_xbit_offset : natural := lrat_datain_size_offset + 4; +constant lrat_datain_valid_offset : natural := lrat_datain_xbit_offset + 1; +constant lrat_mas1_v_offset : natural := lrat_datain_valid_offset + 1; +constant lrat_mas1_tsize_offset : natural := lrat_mas1_v_offset + 1; +constant lrat_mas2_epn_offset : natural := lrat_mas1_tsize_offset + 4; +constant lrat_mas3_rpnl_offset : natural := lrat_mas2_epn_offset + rpn_width; +constant lrat_mas7_rpnu_offset : natural := lrat_mas3_rpnl_offset + 20; +constant lrat_mas8_tlpid_offset : natural := lrat_mas7_rpnu_offset + 10; +constant lrat_mas_tlbre_offset : natural := lrat_mas8_tlpid_offset + lpid_width; +constant lrat_mas_tlbsx_hit_offset : natural := lrat_mas_tlbre_offset + 1; +constant lrat_mas_tlbsx_miss_offset : natural := lrat_mas_tlbsx_hit_offset + 1; +constant lrat_mas_thdid_offset : natural := lrat_mas_tlbsx_miss_offset + 1; +constant lrat_mmucr3_x_offset : natural := lrat_mas_thdid_offset + thdid_width; +constant lrat_entry_act_offset : natural := lrat_mmucr3_x_offset + 1; +constant lrat_mas_act_offset : natural := lrat_entry_act_offset + 8; +constant lrat_datain_act_offset : natural := lrat_mas_act_offset +3; +constant spare_offset : natural := lrat_datain_act_offset +2; +constant scan_right : natural := spare_offset + 64 -1; +constant const_lrat_maxsize_log2 : natural := real_addr_width-2; +signal ex4_valid_d, ex4_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal ex4_ttype_d, ex4_ttype_q : std_ulogic_vector(0 to ttype_width-1); +signal ex5_valid_d, ex5_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal ex5_ttype_d, ex5_ttype_q : std_ulogic_vector(0 to ttype_width-1); +signal ex5_esel_d, ex5_esel_q : std_ulogic_vector(0 to 2); +signal ex5_atsel_d, ex5_atsel_q : std_ulogic; +signal ex5_hes_d, ex5_hes_q : std_ulogic; +signal ex5_wq_d, ex5_wq_q : std_ulogic_vector(0 to 1); +signal ex6_valid_d, ex6_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal ex6_ttype_d, ex6_ttype_q : std_ulogic_vector(0 to ttype_width-1); +signal ex6_esel_d, ex6_esel_q : std_ulogic_vector(0 to 2); +signal ex6_atsel_d, ex6_atsel_q : std_ulogic; +signal ex6_hes_d, ex6_hes_q : std_ulogic; +signal ex6_wq_d, ex6_wq_q : std_ulogic_vector(0 to 1); +signal lrat_tag1_lpn_d, lrat_tag1_lpn_q : std_ulogic_vector(64-real_addr_width to 51); +signal lrat_tag2_lpn_d, lrat_tag2_lpn_q : std_ulogic_vector(64-real_addr_width to 51); +signal lrat_tag3_lpn_d, lrat_tag3_lpn_q : std_ulogic_vector(64-real_addr_width to 51); +signal lrat_tag3_rpn_d, lrat_tag3_rpn_q : std_ulogic_vector(64-real_addr_width to 51); +signal lrat_tag4_lpn_d, lrat_tag4_lpn_q : std_ulogic_vector(64-real_addr_width to 51); +signal lrat_tag4_rpn_d, lrat_tag4_rpn_q : std_ulogic_vector(64-real_addr_width to 51); +signal lrat_tag1_lpid_d, lrat_tag1_lpid_q : std_ulogic_vector(0 to lpid_width-1); +signal lrat_tag2_matchline_d, lrat_tag2_matchline_q : std_ulogic_vector(0 to lrat_num_entry-1); +signal lrat_tag1_size_d, lrat_tag1_size_q : std_ulogic_vector(0 to 3); +signal lrat_tag2_size_d, lrat_tag2_size_q : std_ulogic_vector(0 to 3); +signal lrat_tag2_entry_size_d, lrat_tag2_entry_size_q : std_ulogic_vector(0 to 3); +signal lrat_tag3_hit_status_d, lrat_tag3_hit_status_q : std_ulogic_vector(0 to 3); +signal lrat_tag3_hit_entry_d, lrat_tag3_hit_entry_q : std_ulogic_vector(0 to lrat_num_entry_log2-1); +signal lrat_tag4_hit_status_d, lrat_tag4_hit_status_q : std_ulogic_vector(0 to 3); +signal lrat_tag4_hit_entry_d, lrat_tag4_hit_entry_q : std_ulogic_vector(0 to lrat_num_entry_log2-1); +signal tlb_addr_cap_d, tlb_addr_cap_q : std_ulogic_vector(1 to 2); +signal lrat_entry0_lpn_d, lrat_entry0_lpn_q : std_ulogic_vector(64-real_addr_width to 64-lrat_minsize_log2-1); +signal lrat_entry0_rpn_d, lrat_entry0_rpn_q : std_ulogic_vector(64-real_addr_width to 64-lrat_minsize_log2-1); +signal lrat_entry0_lpid_d, lrat_entry0_lpid_q : std_ulogic_vector(0 to lpid_width-1); +signal lrat_entry0_size_d, lrat_entry0_size_q : std_ulogic_vector(0 to 3); +signal lrat_entry0_cmpmask_d, lrat_entry0_cmpmask_q : std_ulogic_vector(0 to 6); +signal lrat_entry0_xbitmask_d, lrat_entry0_xbitmask_q : std_ulogic_vector(0 to 6); +signal lrat_entry0_xbit_d, lrat_entry0_xbit_q : std_ulogic; +signal lrat_entry0_valid_d, lrat_entry0_valid_q : std_ulogic; +signal lrat_entry1_lpn_d, lrat_entry1_lpn_q : std_ulogic_vector(64-real_addr_width to 64-lrat_minsize_log2-1); +signal lrat_entry1_rpn_d, lrat_entry1_rpn_q : std_ulogic_vector(64-real_addr_width to 64-lrat_minsize_log2-1); +signal lrat_entry1_lpid_d, lrat_entry1_lpid_q : std_ulogic_vector(0 to lpid_width-1); +signal lrat_entry1_size_d, lrat_entry1_size_q : std_ulogic_vector(0 to 3); +signal lrat_entry1_cmpmask_d, lrat_entry1_cmpmask_q : std_ulogic_vector(0 to 6); +signal lrat_entry1_xbitmask_d, lrat_entry1_xbitmask_q : std_ulogic_vector(0 to 6); +signal lrat_entry1_xbit_d, lrat_entry1_xbit_q : std_ulogic; +signal lrat_entry1_valid_d, lrat_entry1_valid_q : std_ulogic; +signal lrat_entry2_lpn_d, lrat_entry2_lpn_q : std_ulogic_vector(64-real_addr_width to 64-lrat_minsize_log2-1); +signal lrat_entry2_rpn_d, lrat_entry2_rpn_q : std_ulogic_vector(64-real_addr_width to 64-lrat_minsize_log2-1); +signal lrat_entry2_lpid_d, lrat_entry2_lpid_q : std_ulogic_vector(0 to lpid_width-1); +signal lrat_entry2_size_d, lrat_entry2_size_q : std_ulogic_vector(0 to 3); +signal lrat_entry2_cmpmask_d, lrat_entry2_cmpmask_q : std_ulogic_vector(0 to 6); +signal lrat_entry2_xbitmask_d, lrat_entry2_xbitmask_q : std_ulogic_vector(0 to 6); +signal lrat_entry2_xbit_d, lrat_entry2_xbit_q : std_ulogic; +signal lrat_entry2_valid_d, lrat_entry2_valid_q : std_ulogic; +signal lrat_entry3_lpn_d, lrat_entry3_lpn_q : std_ulogic_vector(64-real_addr_width to 64-lrat_minsize_log2-1); +signal lrat_entry3_rpn_d, lrat_entry3_rpn_q : std_ulogic_vector(64-real_addr_width to 64-lrat_minsize_log2-1); +signal lrat_entry3_lpid_d, lrat_entry3_lpid_q : std_ulogic_vector(0 to lpid_width-1); +signal lrat_entry3_size_d, lrat_entry3_size_q : std_ulogic_vector(0 to 3); +signal lrat_entry3_cmpmask_d, lrat_entry3_cmpmask_q : std_ulogic_vector(0 to 6); +signal lrat_entry3_xbitmask_d, lrat_entry3_xbitmask_q : std_ulogic_vector(0 to 6); +signal lrat_entry3_xbit_d, lrat_entry3_xbit_q : std_ulogic; +signal lrat_entry3_valid_d, lrat_entry3_valid_q : std_ulogic; +signal lrat_entry4_lpn_d, lrat_entry4_lpn_q : std_ulogic_vector(64-real_addr_width to 64-lrat_minsize_log2-1); +signal lrat_entry4_rpn_d, lrat_entry4_rpn_q : std_ulogic_vector(64-real_addr_width to 64-lrat_minsize_log2-1); +signal lrat_entry4_lpid_d, lrat_entry4_lpid_q : std_ulogic_vector(0 to lpid_width-1); +signal lrat_entry4_size_d, lrat_entry4_size_q : std_ulogic_vector(0 to 3); +signal lrat_entry4_cmpmask_d, lrat_entry4_cmpmask_q : std_ulogic_vector(0 to 6); +signal lrat_entry4_xbitmask_d, lrat_entry4_xbitmask_q : std_ulogic_vector(0 to 6); +signal lrat_entry4_xbit_d, lrat_entry4_xbit_q : std_ulogic; +signal lrat_entry4_valid_d, lrat_entry4_valid_q : std_ulogic; +signal lrat_entry5_lpn_d, lrat_entry5_lpn_q : std_ulogic_vector(64-real_addr_width to 64-lrat_minsize_log2-1); +signal lrat_entry5_rpn_d, lrat_entry5_rpn_q : std_ulogic_vector(64-real_addr_width to 64-lrat_minsize_log2-1); +signal lrat_entry5_lpid_d, lrat_entry5_lpid_q : std_ulogic_vector(0 to lpid_width-1); +signal lrat_entry5_size_d, lrat_entry5_size_q : std_ulogic_vector(0 to 3); +signal lrat_entry5_cmpmask_d, lrat_entry5_cmpmask_q : std_ulogic_vector(0 to 6); +signal lrat_entry5_xbitmask_d, lrat_entry5_xbitmask_q : std_ulogic_vector(0 to 6); +signal lrat_entry5_xbit_d, lrat_entry5_xbit_q : std_ulogic; +signal lrat_entry5_valid_d, lrat_entry5_valid_q : std_ulogic; +signal lrat_entry6_lpn_d, lrat_entry6_lpn_q : std_ulogic_vector(64-real_addr_width to 64-lrat_minsize_log2-1); +signal lrat_entry6_rpn_d, lrat_entry6_rpn_q : std_ulogic_vector(64-real_addr_width to 64-lrat_minsize_log2-1); +signal lrat_entry6_lpid_d, lrat_entry6_lpid_q : std_ulogic_vector(0 to lpid_width-1); +signal lrat_entry6_size_d, lrat_entry6_size_q : std_ulogic_vector(0 to 3); +signal lrat_entry6_cmpmask_d, lrat_entry6_cmpmask_q : std_ulogic_vector(0 to 6); +signal lrat_entry6_xbitmask_d, lrat_entry6_xbitmask_q : std_ulogic_vector(0 to 6); +signal lrat_entry6_xbit_d, lrat_entry6_xbit_q : std_ulogic; +signal lrat_entry6_valid_d, lrat_entry6_valid_q : std_ulogic; +signal lrat_entry7_lpn_d, lrat_entry7_lpn_q : std_ulogic_vector(64-real_addr_width to 64-lrat_minsize_log2-1); +signal lrat_entry7_rpn_d, lrat_entry7_rpn_q : std_ulogic_vector(64-real_addr_width to 64-lrat_minsize_log2-1); +signal lrat_entry7_lpid_d, lrat_entry7_lpid_q : std_ulogic_vector(0 to lpid_width-1); +signal lrat_entry7_size_d, lrat_entry7_size_q : std_ulogic_vector(0 to 3); +signal lrat_entry7_cmpmask_d, lrat_entry7_cmpmask_q : std_ulogic_vector(0 to 6); +signal lrat_entry7_xbitmask_d, lrat_entry7_xbitmask_q : std_ulogic_vector(0 to 6); +signal lrat_entry7_xbit_d, lrat_entry7_xbit_q : std_ulogic; +signal lrat_entry7_valid_d, lrat_entry7_valid_q : std_ulogic; +signal lrat_datain_lpn_d, lrat_datain_lpn_q : std_ulogic_vector(64-real_addr_width to 64-lrat_minsize_log2-1); +signal lrat_datain_rpn_d, lrat_datain_rpn_q : std_ulogic_vector(64-real_addr_width to 64-lrat_minsize_log2-1); +signal lrat_datain_lpid_d, lrat_datain_lpid_q : std_ulogic_vector(0 to lpid_width-1); +signal lrat_datain_size_d, lrat_datain_size_q : std_ulogic_vector(0 to 3); +signal lrat_datain_xbit_d, lrat_datain_xbit_q : std_ulogic; +signal lrat_datain_valid_d, lrat_datain_valid_q : std_ulogic; +signal lrat_mas1_v_d, lrat_mas1_v_q : std_ulogic; +signal lrat_mas1_tsize_d, lrat_mas1_tsize_q : std_ulogic_vector(0 to 3); +signal lrat_mas2_epn_d,lrat_mas2_epn_q : std_ulogic_vector(64-real_addr_width to 51); +signal lrat_mas3_rpnl_d,lrat_mas3_rpnl_q : std_ulogic_vector(32 to 51); +signal lrat_mas7_rpnu_d, lrat_mas7_rpnu_q : std_ulogic_vector(22 to 31); +signal lrat_mas8_tlpid_d, lrat_mas8_tlpid_q : std_ulogic_vector(0 to lpid_width-1); +signal lrat_mas_tlbre_d, lrat_mas_tlbre_q : std_ulogic; +signal lrat_mas_tlbsx_hit_d, lrat_mas_tlbsx_hit_q : std_ulogic; +signal lrat_mas_tlbsx_miss_d, lrat_mas_tlbsx_miss_q : std_ulogic; +signal lrat_mas_thdid_d, lrat_mas_thdid_q : std_ulogic_vector(0 to thdid_width-1); +signal lrat_mmucr3_x_d, lrat_mmucr3_x_q : std_ulogic; +signal lrat_entry_act_d, lrat_entry_act_q : std_ulogic_vector(0 to 7); +signal lrat_mas_act_d, lrat_mas_act_q : std_ulogic_vector(0 to 2); +signal lrat_datain_act_d, lrat_datain_act_q : std_ulogic_vector(0 to 1); +signal spare_q : std_ulogic_vector(0 to 63); +signal multihit : std_ulogic; +signal addr_enable : std_ulogic; +signal lpid_enable : std_ulogic; +signal lrat_supp_pgsize : std_ulogic; +signal lrat_tag2_size_gt_entry_size : std_ulogic; +signal lrat_tag1_matchline : std_ulogic_vector(0 to lrat_num_entry-1); +signal lrat_entry0_addr_match : std_ulogic; +signal lrat_entry0_lpid_match : std_ulogic; +signal lrat_entry1_addr_match : std_ulogic; +signal lrat_entry1_lpid_match : std_ulogic; +signal lrat_entry2_addr_match : std_ulogic; +signal lrat_entry2_lpid_match : std_ulogic; +signal lrat_entry3_addr_match : std_ulogic; +signal lrat_entry3_lpid_match : std_ulogic; +signal lrat_entry4_addr_match : std_ulogic; +signal lrat_entry4_lpid_match : std_ulogic; +signal lrat_entry5_addr_match : std_ulogic; +signal lrat_entry5_lpid_match : std_ulogic; +signal lrat_entry6_addr_match : std_ulogic; +signal lrat_entry6_lpid_match : std_ulogic; +signal lrat_entry7_addr_match : std_ulogic; +signal lrat_entry7_lpid_match : std_ulogic; +signal unused_dc : std_ulogic_vector(0 to 13); +-- synopsys translate_off +-- synopsys translate_on +signal pc_sg_1 : std_ulogic; +signal pc_sg_0 : std_ulogic; +signal pc_func_sl_thold_1 : std_ulogic; +signal pc_func_sl_thold_0 : std_ulogic; +signal pc_func_sl_thold_0_b : std_ulogic; +signal pc_func_slp_sl_thold_1 : std_ulogic; +signal pc_func_slp_sl_thold_0 : std_ulogic; +signal pc_func_slp_sl_thold_0_b : std_ulogic; +signal pc_func_sl_force : std_ulogic; +signal pc_func_slp_sl_force : std_ulogic; +signal siv : std_ulogic_vector(0 to scan_right); +signal sov : std_ulogic_vector(0 to scan_right); +signal tiup : std_ulogic; + BEGIN + +tiup <= '1'; +tlb_addr_cap_d(1) <= tlb_tag0_addr_cap and ((tlb_tag0_type(tagpos_type_tlbsx) and tlb_tag0_atsel) or + tlb_tag0_type(tagpos_type_ptereload) or tlb_tag0_type(tagpos_type_tlbwe)); +lrat_tag1_size_d <= tlb_tag0_size when tlb_tag0_addr_cap='1' + else lrat_tag1_size_q; +gen32_lrat_tag1_lpn: if real_addr_width < 33 generate +lrat_tag1_lpn_d <= tlb_tag0_epn(64-real_addr_width to 51) when (tlb_tag0_addr_cap='1' and tlb_tag0_type(tagpos_type_tlbsx)='1') + else pte_tag0_lpn(64-real_addr_width to 51) when (tlb_tag0_addr_cap='1' and tlb_tag0_type(tagpos_type_ptereload)='1') + else mas3_3_rpnl when (tlb_tag0_addr_cap='1' and tlb_tag0_thdid(3)='1' and tlb_tag0_type(tagpos_type_tlbwe)='1') + else mas3_2_rpnl when (tlb_tag0_addr_cap='1' and tlb_tag0_thdid(2)='1' and tlb_tag0_type(tagpos_type_tlbwe)='1') + else mas3_1_rpnl when (tlb_tag0_addr_cap='1' and tlb_tag0_thdid(1)='1' and tlb_tag0_type(tagpos_type_tlbwe)='1') + else mas3_0_rpnl when (tlb_tag0_addr_cap='1' and tlb_tag0_thdid(0)='1' and tlb_tag0_type(tagpos_type_tlbwe)='1') + else lrat_tag1_lpn_q; +end generate gen32_lrat_tag1_lpn; +gen64_lrat_tag1_lpn: if real_addr_width > 32 generate +lrat_tag1_lpn_d <= tlb_tag0_epn(64-real_addr_width to 51) when (tlb_tag0_addr_cap='1' and tlb_tag0_type(tagpos_type_tlbsx)='1') + else pte_tag0_lpn(64-real_addr_width to 51) when (tlb_tag0_addr_cap='1' and tlb_tag0_type(tagpos_type_ptereload)='1') + else mas7_3_rpnu(64-real_addr_width to 31) & mas3_3_rpnl when (tlb_tag0_addr_cap='1' and tlb_tag0_thdid(3)='1' and tlb_tag0_type(tagpos_type_tlbwe)='1') + else mas7_2_rpnu(64-real_addr_width to 31) & mas3_2_rpnl when (tlb_tag0_addr_cap='1' and tlb_tag0_thdid(2)='1' and tlb_tag0_type(tagpos_type_tlbwe)='1') + else mas7_1_rpnu(64-real_addr_width to 31) & mas3_1_rpnl when (tlb_tag0_addr_cap='1' and tlb_tag0_thdid(1)='1' and tlb_tag0_type(tagpos_type_tlbwe)='1') + else mas7_0_rpnu(64-real_addr_width to 31) & mas3_0_rpnl when (tlb_tag0_addr_cap='1' and tlb_tag0_thdid(0)='1' and tlb_tag0_type(tagpos_type_tlbwe)='1') + else lrat_tag1_lpn_q; +end generate gen64_lrat_tag1_lpn; +lrat_tag1_lpid_d <= tlb_tag0_lpid when (tlb_tag0_addr_cap='1' and tlb_tag0_type(tagpos_type_tlbsx)='1') + else pte_tag0_lpid when (tlb_tag0_addr_cap='1' and tlb_tag0_type(tagpos_type_ptereload)='1') + else mas8_3_tlpid when (tlb_tag0_addr_cap='1' and tlb_tag0_thdid(3)='1' and tlb_tag0_type(tagpos_type_tlbwe)='1') + else mas8_2_tlpid when (tlb_tag0_addr_cap='1' and tlb_tag0_thdid(2)='1' and tlb_tag0_type(tagpos_type_tlbwe)='1') + else mas8_1_tlpid when (tlb_tag0_addr_cap='1' and tlb_tag0_thdid(1)='1' and tlb_tag0_type(tagpos_type_tlbwe)='1') + else mas8_0_tlpid when (tlb_tag0_addr_cap='1' and tlb_tag0_thdid(0)='1' and tlb_tag0_type(tagpos_type_tlbwe)='1') + else lrat_tag1_lpid_q; +ex4_valid_d <= tlb_ctl_ex3_valid and not(xu_ex3_flush); +ex4_ttype_d <= tlb_ctl_ex3_ttype; +addr_enable <= tlb_addr_cap_q(1); +lpid_enable <= tlb_addr_cap_q(1); +tlb_addr_cap_d(2) <= tlb_addr_cap_q(1); +lrat_tag2_lpn_d <= lrat_tag1_lpn_q; +lrat_tag2_matchline_d <= lrat_tag1_matchline; +lrat_tag2_size_d <= lrat_tag1_size_q; +lrat_tag2_entry_size_d <= + (lrat_entry0_size_q and (0 to 3 => lrat_tag1_matchline(0))) or + (lrat_entry1_size_q and (0 to 3 => lrat_tag1_matchline(1))) or + (lrat_entry2_size_q and (0 to 3 => lrat_tag1_matchline(2))) or + (lrat_entry3_size_q and (0 to 3 => lrat_tag1_matchline(3))) or + (lrat_entry4_size_q and (0 to 3 => lrat_tag1_matchline(4))) or + (lrat_entry5_size_q and (0 to 3 => lrat_tag1_matchline(5))) or + (lrat_entry6_size_q and (0 to 3 => lrat_tag1_matchline(6))) or + (lrat_entry7_size_q and (0 to 3 => lrat_tag1_matchline(7))); +ex5_valid_d <= ex4_valid_q and not(xu_ex4_flush); +ex5_ttype_d <= ex4_ttype_q; +ex5_esel_d <= mas0_1_esel when ex4_valid_q(1)='1' + else mas0_2_esel when ex4_valid_q(2)='1' + else mas0_3_esel when ex4_valid_q(3)='1' + else mas0_0_esel; +ex5_atsel_d <= mas0_1_atsel when ex4_valid_q(1)='1' + else mas0_2_atsel when ex4_valid_q(2)='1' + else mas0_3_atsel when ex4_valid_q(3)='1' + else mas0_0_atsel; +ex5_hes_d <= mas0_1_hes when ex4_valid_q(1)='1' + else mas0_2_hes when ex4_valid_q(2)='1' + else mas0_3_hes when ex4_valid_q(3)='1' + else mas0_0_hes; +ex5_wq_d <= mas0_1_wq when ex4_valid_q(1)='1' + else mas0_2_wq when ex4_valid_q(2)='1' + else mas0_3_wq when ex4_valid_q(3)='1' + else mas0_0_wq; +lrat_tag3_lpn_d <= lrat_tag2_lpn_q; +lrat_tag3_hit_status_d(0) <= tlb_addr_cap_q(2); +lrat_tag3_hit_status_d(1) <= tlb_addr_cap_q(2) and or_reduce(lrat_tag2_matchline_q(0 to lrat_num_entry-1)); +lrat_tag3_hit_status_d(2) <= tlb_addr_cap_q(2) and multihit; +lrat_tag3_hit_status_d(3) <= tlb_addr_cap_q(2) and (not(lrat_supp_pgsize) or lrat_tag2_size_gt_entry_size); +multihit <= '0' when (lrat_tag2_matchline_q(0 to lrat_num_entry-1)="00000000" or + lrat_tag2_matchline_q(0 to lrat_num_entry-1)="10000000" or + lrat_tag2_matchline_q(0 to lrat_num_entry-1)="01000000" or + lrat_tag2_matchline_q(0 to lrat_num_entry-1)="00100000" or + lrat_tag2_matchline_q(0 to lrat_num_entry-1)="00010000" or + lrat_tag2_matchline_q(0 to lrat_num_entry-1)="00001000" or + lrat_tag2_matchline_q(0 to lrat_num_entry-1)="00000100" or + lrat_tag2_matchline_q(0 to lrat_num_entry-1)="00000010" or + lrat_tag2_matchline_q(0 to lrat_num_entry-1)="00000001") + else '1'; +lrat_tag3_hit_entry_d <= "001" when lrat_tag2_matchline_q(0 to lrat_num_entry-1)="01000000" + else "010" when lrat_tag2_matchline_q(0 to lrat_num_entry-1)="00100000" + else "011" when lrat_tag2_matchline_q(0 to lrat_num_entry-1)="00010000" + else "100" when lrat_tag2_matchline_q(0 to lrat_num_entry-1)="00001000" + else "101" when lrat_tag2_matchline_q(0 to lrat_num_entry-1)="00000100" + else "110" when lrat_tag2_matchline_q(0 to lrat_num_entry-1)="00000010" + else "111" when lrat_tag2_matchline_q(0 to lrat_num_entry-1)="00000001" + else "000"; +lrat_tag2_size_gt_entry_size <= (Eq(lrat_tag2_size_q,TLB_PgSize_16MB) and Eq(lrat_tag2_entry_size_q,LRAT_PgSize_1MB)) or + (Eq(lrat_tag2_size_q,TLB_PgSize_1GB) and Eq(lrat_tag2_entry_size_q,LRAT_PgSize_1MB)) or + (Eq(lrat_tag2_size_q,TLB_PgSize_1GB) and Eq(lrat_tag2_entry_size_q,LRAT_PgSize_16MB)) or + (Eq(lrat_tag2_size_q,TLB_PgSize_1GB) and Eq(lrat_tag2_entry_size_q,LRAT_PgSize_256MB)); +lrat_supp_pgsize <= '1' when (lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB or lrat_tag2_entry_size_q=LRAT_PgSize_1GB or + lrat_tag2_entry_size_q=LRAT_PgSize_4GB or lrat_tag2_entry_size_q=LRAT_PgSize_16GB or + lrat_tag2_entry_size_q=LRAT_PgSize_256GB or lrat_tag2_entry_size_q=LRAT_PgSize_1TB) + else '0'; +lrat_tag3_rpn_d(64-LRAT_PgSize_1MB_log2 TO 51) <= lrat_tag2_lpn_q(64-LRAT_PgSize_1MB_log2 to 51); +lrat_tag3_rpn_d(64-LRAT_PgSize_16MB_log2 TO 64-LRAT_PgSize_1MB_log2-1) <= + lrat_entry0_rpn_q(64-LRAT_PgSize_16MB_log2 to 64-LRAT_PgSize_1MB_log2-1) + when (lrat_tag2_entry_size_q=LRAT_PgSize_1MB and lrat_tag2_matchline_q(0)='1') + else lrat_entry1_rpn_q(64-LRAT_PgSize_16MB_log2 to 64-LRAT_PgSize_1MB_log2-1) + when (lrat_tag2_entry_size_q=LRAT_PgSize_1MB and lrat_tag2_matchline_q(1)='1') + else lrat_entry2_rpn_q(64-LRAT_PgSize_16MB_log2 to 64-LRAT_PgSize_1MB_log2-1) + when (lrat_tag2_entry_size_q=LRAT_PgSize_1MB and lrat_tag2_matchline_q(2)='1') + else lrat_entry3_rpn_q(64-LRAT_PgSize_16MB_log2 to 64-LRAT_PgSize_1MB_log2-1) + when (lrat_tag2_entry_size_q=LRAT_PgSize_1MB and lrat_tag2_matchline_q(3)='1') + else lrat_entry4_rpn_q(64-LRAT_PgSize_16MB_log2 to 64-LRAT_PgSize_1MB_log2-1) + when (lrat_tag2_entry_size_q=LRAT_PgSize_1MB and lrat_tag2_matchline_q(4)='1') + else lrat_entry5_rpn_q(64-LRAT_PgSize_16MB_log2 to 64-LRAT_PgSize_1MB_log2-1) + when (lrat_tag2_entry_size_q=LRAT_PgSize_1MB and lrat_tag2_matchline_q(5)='1') + else lrat_entry6_rpn_q(64-LRAT_PgSize_16MB_log2 to 64-LRAT_PgSize_1MB_log2-1) + when (lrat_tag2_entry_size_q=LRAT_PgSize_1MB and lrat_tag2_matchline_q(6)='1') + else lrat_entry7_rpn_q(64-LRAT_PgSize_16MB_log2 to 64-LRAT_PgSize_1MB_log2-1) + when (lrat_tag2_entry_size_q=LRAT_PgSize_1MB and lrat_tag2_matchline_q(7)='1') + else lrat_tag2_lpn_q(64-LRAT_PgSize_16MB_log2 to 64-LRAT_PgSize_1MB_log2-1); +lrat_tag3_rpn_d(64-LRAT_PgSize_256MB_log2 TO 64-LRAT_PgSize_16MB_log2-1) <= + lrat_entry0_rpn_q(64-LRAT_PgSize_256MB_log2 to 64-LRAT_PgSize_16MB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB) and lrat_tag2_matchline_q(0)='1') + else lrat_entry1_rpn_q(64-LRAT_PgSize_256MB_log2 to 64-LRAT_PgSize_16MB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB) and lrat_tag2_matchline_q(1)='1') + else lrat_entry2_rpn_q(64-LRAT_PgSize_256MB_log2 to 64-LRAT_PgSize_16MB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB) and lrat_tag2_matchline_q(2)='1') + else lrat_entry3_rpn_q(64-LRAT_PgSize_256MB_log2 to 64-LRAT_PgSize_16MB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB) and lrat_tag2_matchline_q(3)='1') + else lrat_entry4_rpn_q(64-LRAT_PgSize_256MB_log2 to 64-LRAT_PgSize_16MB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB) and lrat_tag2_matchline_q(4)='1') + else lrat_entry5_rpn_q(64-LRAT_PgSize_256MB_log2 to 64-LRAT_PgSize_16MB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB) and lrat_tag2_matchline_q(5)='1') + else lrat_entry6_rpn_q(64-LRAT_PgSize_256MB_log2 to 64-LRAT_PgSize_16MB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB) and lrat_tag2_matchline_q(6)='1') + else lrat_entry7_rpn_q(64-LRAT_PgSize_256MB_log2 to 64-LRAT_PgSize_16MB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB) and lrat_tag2_matchline_q(7)='1') + else lrat_tag2_lpn_q(64-LRAT_PgSize_256MB_log2 to 64-LRAT_PgSize_16MB_log2-1); +lrat_tag3_rpn_d(64-LRAT_PgSize_1GB_log2 TO 64-LRAT_PgSize_256MB_log2-1) <= + lrat_entry0_rpn_q(64-LRAT_PgSize_1GB_log2 to 64-LRAT_PgSize_256MB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB) and lrat_tag2_matchline_q(0)='1') + else lrat_entry1_rpn_q(64-LRAT_PgSize_1GB_log2 to 64-LRAT_PgSize_256MB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB) and lrat_tag2_matchline_q(1)='1') + else lrat_entry2_rpn_q(64-LRAT_PgSize_1GB_log2 to 64-LRAT_PgSize_256MB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB) and lrat_tag2_matchline_q(2)='1') + else lrat_entry3_rpn_q(64-LRAT_PgSize_1GB_log2 to 64-LRAT_PgSize_256MB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB) and lrat_tag2_matchline_q(3)='1') + else lrat_entry4_rpn_q(64-LRAT_PgSize_1GB_log2 to 64-LRAT_PgSize_256MB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB) and lrat_tag2_matchline_q(4)='1') + else lrat_entry5_rpn_q(64-LRAT_PgSize_1GB_log2 to 64-LRAT_PgSize_256MB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB) and lrat_tag2_matchline_q(5)='1') + else lrat_entry6_rpn_q(64-LRAT_PgSize_1GB_log2 to 64-LRAT_PgSize_256MB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB) and lrat_tag2_matchline_q(6)='1') + else lrat_entry7_rpn_q(64-LRAT_PgSize_1GB_log2 to 64-LRAT_PgSize_256MB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB) and lrat_tag2_matchline_q(7)='1') + else lrat_tag2_lpn_q(64-LRAT_PgSize_1GB_log2 to 64-LRAT_PgSize_256MB_log2-1); +lrat_tag3_rpn_d(64-LRAT_PgSize_4GB_log2 TO 64-LRAT_PgSize_1GB_log2-1) <= + lrat_entry0_rpn_q(64-LRAT_PgSize_4GB_log2 to 64-LRAT_PgSize_1GB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB or lrat_tag2_entry_size_q=LRAT_PgSize_1GB) and lrat_tag2_matchline_q(0)='1') + else lrat_entry1_rpn_q(64-LRAT_PgSize_4GB_log2 to 64-LRAT_PgSize_1GB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB or lrat_tag2_entry_size_q=LRAT_PgSize_1GB) and lrat_tag2_matchline_q(1)='1') + else lrat_entry2_rpn_q(64-LRAT_PgSize_4GB_log2 to 64-LRAT_PgSize_1GB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB or lrat_tag2_entry_size_q=LRAT_PgSize_1GB) and lrat_tag2_matchline_q(2)='1') + else lrat_entry3_rpn_q(64-LRAT_PgSize_4GB_log2 to 64-LRAT_PgSize_1GB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB or lrat_tag2_entry_size_q=LRAT_PgSize_1GB) and lrat_tag2_matchline_q(3)='1') + else lrat_entry4_rpn_q(64-LRAT_PgSize_4GB_log2 to 64-LRAT_PgSize_1GB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB or lrat_tag2_entry_size_q=LRAT_PgSize_1GB) and lrat_tag2_matchline_q(4)='1') + else lrat_entry5_rpn_q(64-LRAT_PgSize_4GB_log2 to 64-LRAT_PgSize_1GB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB or lrat_tag2_entry_size_q=LRAT_PgSize_1GB) and lrat_tag2_matchline_q(5)='1') + else lrat_entry6_rpn_q(64-LRAT_PgSize_4GB_log2 to 64-LRAT_PgSize_1GB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB or lrat_tag2_entry_size_q=LRAT_PgSize_1GB) and lrat_tag2_matchline_q(6)='1') + else lrat_entry7_rpn_q(64-LRAT_PgSize_4GB_log2 to 64-LRAT_PgSize_1GB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB or lrat_tag2_entry_size_q=LRAT_PgSize_1GB) and lrat_tag2_matchline_q(7)='1') + else lrat_tag2_lpn_q(64-LRAT_PgSize_4GB_log2 to 64-LRAT_PgSize_1GB_log2-1); +gen64_lrat_tag3_rpn_34: if real_addr_width > 33 generate +lrat_tag3_rpn_d(64-LRAT_PgSize_16GB_log2 TO 64-LRAT_PgSize_4GB_log2-1) <= + lrat_entry0_rpn_q(64-LRAT_PgSize_16GB_log2 to 64-LRAT_PgSize_4GB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB or lrat_tag2_entry_size_q=LRAT_PgSize_1GB or + lrat_tag2_entry_size_q=LRAT_PgSize_4GB) and lrat_tag2_matchline_q(0)='1') + else lrat_entry1_rpn_q(64-LRAT_PgSize_16GB_log2 to 64-LRAT_PgSize_4GB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB or lrat_tag2_entry_size_q=LRAT_PgSize_1GB or + lrat_tag2_entry_size_q=LRAT_PgSize_4GB) and lrat_tag2_matchline_q(1)='1') + else lrat_entry2_rpn_q(64-LRAT_PgSize_16GB_log2 to 64-LRAT_PgSize_4GB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB or lrat_tag2_entry_size_q=LRAT_PgSize_1GB or + lrat_tag2_entry_size_q=LRAT_PgSize_4GB) and lrat_tag2_matchline_q(2)='1') + else lrat_entry3_rpn_q(64-LRAT_PgSize_16GB_log2 to 64-LRAT_PgSize_4GB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB or lrat_tag2_entry_size_q=LRAT_PgSize_1GB or + lrat_tag2_entry_size_q=LRAT_PgSize_4GB) and lrat_tag2_matchline_q(3)='1') + else lrat_entry4_rpn_q(64-LRAT_PgSize_16GB_log2 to 64-LRAT_PgSize_4GB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB or lrat_tag2_entry_size_q=LRAT_PgSize_1GB or + lrat_tag2_entry_size_q=LRAT_PgSize_4GB) and lrat_tag2_matchline_q(4)='1') + else lrat_entry5_rpn_q(64-LRAT_PgSize_16GB_log2 to 64-LRAT_PgSize_4GB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB or lrat_tag2_entry_size_q=LRAT_PgSize_1GB or + lrat_tag2_entry_size_q=LRAT_PgSize_4GB) and lrat_tag2_matchline_q(5)='1') + else lrat_entry6_rpn_q(64-LRAT_PgSize_16GB_log2 to 64-LRAT_PgSize_4GB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB or lrat_tag2_entry_size_q=LRAT_PgSize_1GB or + lrat_tag2_entry_size_q=LRAT_PgSize_4GB) and lrat_tag2_matchline_q(6)='1') + else lrat_entry7_rpn_q(64-LRAT_PgSize_16GB_log2 to 64-LRAT_PgSize_4GB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB or lrat_tag2_entry_size_q=LRAT_PgSize_1GB or + lrat_tag2_entry_size_q=LRAT_PgSize_4GB) and lrat_tag2_matchline_q(7)='1') + else lrat_tag2_lpn_q(64-LRAT_PgSize_16GB_log2 to 64-LRAT_PgSize_4GB_log2-1); +end generate gen64_lrat_tag3_rpn_34; +gen64_lrat_tag3_rpn_38: if real_addr_width > 37 generate +lrat_tag3_rpn_d(64-LRAT_PgSize_256GB_log2 TO 64-LRAT_PgSize_16GB_log2-1) <= + lrat_entry0_rpn_q(64-LRAT_PgSize_256GB_log2 to 64-LRAT_PgSize_16GB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB or lrat_tag2_entry_size_q=LRAT_PgSize_1GB or + lrat_tag2_entry_size_q=LRAT_PgSize_4GB or lrat_tag2_entry_size_q=LRAT_PgSize_16GB) and lrat_tag2_matchline_q(0)='1') + else lrat_entry1_rpn_q(64-LRAT_PgSize_256GB_log2 to 64-LRAT_PgSize_16GB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB or lrat_tag2_entry_size_q=LRAT_PgSize_1GB or + lrat_tag2_entry_size_q=LRAT_PgSize_4GB or lrat_tag2_entry_size_q=LRAT_PgSize_16GB) and lrat_tag2_matchline_q(1)='1') + else lrat_entry2_rpn_q(64-LRAT_PgSize_256GB_log2 to 64-LRAT_PgSize_16GB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB or lrat_tag2_entry_size_q=LRAT_PgSize_1GB or + lrat_tag2_entry_size_q=LRAT_PgSize_4GB or lrat_tag2_entry_size_q=LRAT_PgSize_16GB) and lrat_tag2_matchline_q(2)='1') + else lrat_entry3_rpn_q(64-LRAT_PgSize_256GB_log2 to 64-LRAT_PgSize_16GB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB or lrat_tag2_entry_size_q=LRAT_PgSize_1GB or + lrat_tag2_entry_size_q=LRAT_PgSize_4GB or lrat_tag2_entry_size_q=LRAT_PgSize_16GB) and lrat_tag2_matchline_q(3)='1') + else lrat_entry4_rpn_q(64-LRAT_PgSize_256GB_log2 to 64-LRAT_PgSize_16GB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB or lrat_tag2_entry_size_q=LRAT_PgSize_1GB or + lrat_tag2_entry_size_q=LRAT_PgSize_4GB or lrat_tag2_entry_size_q=LRAT_PgSize_16GB) and lrat_tag2_matchline_q(4)='1') + else lrat_entry5_rpn_q(64-LRAT_PgSize_256GB_log2 to 64-LRAT_PgSize_16GB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB or lrat_tag2_entry_size_q=LRAT_PgSize_1GB or + lrat_tag2_entry_size_q=LRAT_PgSize_4GB or lrat_tag2_entry_size_q=LRAT_PgSize_16GB) and lrat_tag2_matchline_q(5)='1') + else lrat_entry6_rpn_q(64-LRAT_PgSize_256GB_log2 to 64-LRAT_PgSize_16GB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB or lrat_tag2_entry_size_q=LRAT_PgSize_1GB or + lrat_tag2_entry_size_q=LRAT_PgSize_4GB or lrat_tag2_entry_size_q=LRAT_PgSize_16GB) and lrat_tag2_matchline_q(6)='1') + else lrat_entry7_rpn_q(64-LRAT_PgSize_256GB_log2 to 64-LRAT_PgSize_16GB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB or lrat_tag2_entry_size_q=LRAT_PgSize_1GB or + lrat_tag2_entry_size_q=LRAT_PgSize_4GB or lrat_tag2_entry_size_q=LRAT_PgSize_16GB) and lrat_tag2_matchline_q(7)='1') + else lrat_tag2_lpn_q(64-LRAT_PgSize_256GB_log2 to 64-LRAT_PgSize_16GB_log2-1); +end generate gen64_lrat_tag3_rpn_38; +gen64_lrat_tag3_rpn_40: if real_addr_width > 39 generate +lrat_tag3_rpn_d(64-LRAT_PgSize_1TB_log2 TO 64-LRAT_PgSize_256GB_log2-1) <= + lrat_entry0_rpn_q(64-LRAT_PgSize_1TB_log2 to 64-LRAT_PgSize_256GB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB or lrat_tag2_entry_size_q=LRAT_PgSize_1GB or + lrat_tag2_entry_size_q=LRAT_PgSize_4GB or lrat_tag2_entry_size_q=LRAT_PgSize_16GB or + lrat_tag2_entry_size_q=LRAT_PgSize_256GB) and lrat_tag2_matchline_q(0)='1') + else lrat_entry1_rpn_q(64-LRAT_PgSize_1TB_log2 to 64-LRAT_PgSize_256GB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB or lrat_tag2_entry_size_q=LRAT_PgSize_1GB or + lrat_tag2_entry_size_q=LRAT_PgSize_4GB or lrat_tag2_entry_size_q=LRAT_PgSize_16GB or + lrat_tag2_entry_size_q=LRAT_PgSize_256GB) and lrat_tag2_matchline_q(1)='1') + else lrat_entry2_rpn_q(64-LRAT_PgSize_1TB_log2 to 64-LRAT_PgSize_256GB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB or lrat_tag2_entry_size_q=LRAT_PgSize_1GB or + lrat_tag2_entry_size_q=LRAT_PgSize_4GB or lrat_tag2_entry_size_q=LRAT_PgSize_16GB or + lrat_tag2_entry_size_q=LRAT_PgSize_256GB) and lrat_tag2_matchline_q(2)='1') + else lrat_entry3_rpn_q(64-LRAT_PgSize_1TB_log2 to 64-LRAT_PgSize_256GB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB or lrat_tag2_entry_size_q=LRAT_PgSize_1GB or + lrat_tag2_entry_size_q=LRAT_PgSize_4GB or lrat_tag2_entry_size_q=LRAT_PgSize_16GB or + lrat_tag2_entry_size_q=LRAT_PgSize_256GB) and lrat_tag2_matchline_q(3)='1') + else lrat_entry4_rpn_q(64-LRAT_PgSize_1TB_log2 to 64-LRAT_PgSize_256GB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB or lrat_tag2_entry_size_q=LRAT_PgSize_1GB or + lrat_tag2_entry_size_q=LRAT_PgSize_4GB or lrat_tag2_entry_size_q=LRAT_PgSize_16GB or + lrat_tag2_entry_size_q=LRAT_PgSize_256GB) and lrat_tag2_matchline_q(4)='1') + else lrat_entry5_rpn_q(64-LRAT_PgSize_1TB_log2 to 64-LRAT_PgSize_256GB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB or lrat_tag2_entry_size_q=LRAT_PgSize_1GB or + lrat_tag2_entry_size_q=LRAT_PgSize_4GB or lrat_tag2_entry_size_q=LRAT_PgSize_16GB or + lrat_tag2_entry_size_q=LRAT_PgSize_256GB) and lrat_tag2_matchline_q(5)='1') + else lrat_entry6_rpn_q(64-LRAT_PgSize_1TB_log2 to 64-LRAT_PgSize_256GB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB or lrat_tag2_entry_size_q=LRAT_PgSize_1GB or + lrat_tag2_entry_size_q=LRAT_PgSize_4GB or lrat_tag2_entry_size_q=LRAT_PgSize_16GB or + lrat_tag2_entry_size_q=LRAT_PgSize_256GB) and lrat_tag2_matchline_q(6)='1') + else lrat_entry7_rpn_q(64-LRAT_PgSize_1TB_log2 to 64-LRAT_PgSize_256GB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB or lrat_tag2_entry_size_q=LRAT_PgSize_1GB or + lrat_tag2_entry_size_q=LRAT_PgSize_4GB or lrat_tag2_entry_size_q=LRAT_PgSize_16GB or + lrat_tag2_entry_size_q=LRAT_PgSize_256GB) and lrat_tag2_matchline_q(7)='1') + else lrat_tag2_lpn_q(64-LRAT_PgSize_1TB_log2 to 64-LRAT_PgSize_256GB_log2-1); +end generate gen64_lrat_tag3_rpn_40; +gen64_lrat_tag3_rpn_42: if real_addr_width > 41 generate +lrat_tag3_rpn_d(64-real_addr_width TO 64-lrat_maxsize_log2-1) <= + lrat_entry0_rpn_q(64-real_addr_width to 64-lrat_maxsize_log2-1) when lrat_tag2_matchline_q(0)='1' + else lrat_entry1_rpn_q(64-real_addr_width to 64-lrat_maxsize_log2-1) when lrat_tag2_matchline_q(1)='1' + else lrat_entry2_rpn_q(64-real_addr_width to 64-lrat_maxsize_log2-1) when lrat_tag2_matchline_q(2)='1' + else lrat_entry3_rpn_q(64-real_addr_width to 64-lrat_maxsize_log2-1) when lrat_tag2_matchline_q(3)='1' + else lrat_entry4_rpn_q(64-real_addr_width to 64-lrat_maxsize_log2-1) when lrat_tag2_matchline_q(4)='1' + else lrat_entry5_rpn_q(64-real_addr_width to 64-lrat_maxsize_log2-1) when lrat_tag2_matchline_q(5)='1' + else lrat_entry6_rpn_q(64-real_addr_width to 64-lrat_maxsize_log2-1) when lrat_tag2_matchline_q(6)='1' + else lrat_entry7_rpn_q(64-real_addr_width to 64-lrat_maxsize_log2-1) when lrat_tag2_matchline_q(7)='1' + else lrat_tag2_lpn_q(64-real_addr_width to 64-lrat_maxsize_log2-1); +end generate gen64_lrat_tag3_rpn_42; +ex6_valid_d <= ex5_valid_q and not(xu_ex5_flush); +ex6_ttype_d <= ex5_ttype_q; +ex6_esel_d <= ex5_esel_q; +ex6_atsel_d <= ex5_atsel_q; +ex6_hes_d <= ex5_hes_q; +ex6_wq_d <= ex5_wq_q; +lrat_tag4_lpn_d <= lrat_tag3_lpn_q; +lrat_tag4_rpn_d <= lrat_tag3_rpn_q; +lrat_tag4_hit_status_d <= lrat_tag3_hit_status_q; +lrat_tag4_hit_entry_d <= lrat_tag3_hit_entry_q; +lrat_datain_lpn_d <= mas2_0_epn(64-real_addr_width to 63-lrat_minsize_log2) when (ex5_valid_q(0)='1') + else mas2_1_epn(64-real_addr_width to 63-lrat_minsize_log2) when (ex5_valid_q(1)='1') + else mas2_2_epn(64-real_addr_width to 63-lrat_minsize_log2) when (ex5_valid_q(2)='1') + else mas2_3_epn(64-real_addr_width to 63-lrat_minsize_log2) when (ex5_valid_q(3)='1') + else lrat_datain_lpn_q; +gen64_lrat_datain_rpn: if real_addr_width > 32 generate +lrat_datain_rpn_d(64-real_addr_width TO 31) <= mas7_0_rpnu(64-real_addr_width to 31) when (ex5_valid_q(0)='1') + else mas7_1_rpnu(64-real_addr_width to 31) when (ex5_valid_q(1)='1') + else mas7_2_rpnu(64-real_addr_width to 31) when (ex5_valid_q(2)='1') + else mas7_3_rpnu(64-real_addr_width to 31) when (ex5_valid_q(3)='1') + else lrat_datain_rpn_q(64-real_addr_width to 31); +end generate gen64_lrat_datain_rpn; +lrat_datain_rpn_d(32 TO 63-lrat_minsize_log2) <= mas3_0_rpnl(32 to 63-lrat_minsize_log2) when (ex5_valid_q(0)='1') + else mas3_1_rpnl(32 to 63-lrat_minsize_log2) when (ex5_valid_q(1)='1') + else mas3_2_rpnl(32 to 63-lrat_minsize_log2) when (ex5_valid_q(2)='1') + else mas3_3_rpnl(32 to 63-lrat_minsize_log2) when (ex5_valid_q(3)='1') + else lrat_datain_rpn_q(32 to 63-lrat_minsize_log2); +lrat_datain_lpid_d <= mas8_0_tlpid when (ex5_valid_q(0)='1') + else mas8_1_tlpid when (ex5_valid_q(1)='1') + else mas8_2_tlpid when (ex5_valid_q(2)='1') + else mas8_3_tlpid when (ex5_valid_q(3)='1') + else lrat_datain_lpid_q; +lrat_datain_size_d <= mas1_0_tsize when (ex5_valid_q(0)='1') + else mas1_1_tsize when (ex5_valid_q(1)='1') + else mas1_2_tsize when (ex5_valid_q(2)='1') + else mas1_3_tsize when (ex5_valid_q(3)='1') + else lrat_datain_size_q; +lrat_datain_valid_d <= mas1_0_v when (ex5_valid_q(0)='1') + else mas1_1_v when (ex5_valid_q(1)='1') + else mas1_2_v when (ex5_valid_q(2)='1') + else mas1_3_v when (ex5_valid_q(3)='1') + else lrat_datain_valid_q; +lrat_datain_xbit_d <= mmucr3_0_x when (ex5_valid_q(0)='1') + else mmucr3_1_x when (ex5_valid_q(1)='1') + else mmucr3_2_x when (ex5_valid_q(2)='1') + else mmucr3_3_x when (ex5_valid_q(3)='1') + else lrat_datain_xbit_q; +lrat_mmucr3_x_d <= lrat_entry0_xbit_q when (ex5_valid_q/="0000" and ex5_esel_q="000") + else lrat_entry1_xbit_q when (ex5_valid_q/="0000" and ex5_esel_q="001") + else lrat_entry2_xbit_q when (ex5_valid_q/="0000" and ex5_esel_q="010") + else lrat_entry3_xbit_q when (ex5_valid_q/="0000" and ex5_esel_q="011") + else lrat_entry4_xbit_q when (ex5_valid_q/="0000" and ex5_esel_q="100") + else lrat_entry5_xbit_q when (ex5_valid_q/="0000" and ex5_esel_q="101") + else lrat_entry6_xbit_q when (ex5_valid_q/="0000" and ex5_esel_q="110") + else lrat_entry7_xbit_q when (ex5_valid_q/="0000" and ex5_esel_q="111") + else lrat_mmucr3_x_q; +lrat_mas1_v_d <= lrat_entry0_valid_q when (ex5_valid_q/="0000" and ex5_esel_q="000") + else lrat_entry1_valid_q when (ex5_valid_q/="0000" and ex5_esel_q="001") + else lrat_entry2_valid_q when (ex5_valid_q/="0000" and ex5_esel_q="010") + else lrat_entry3_valid_q when (ex5_valid_q/="0000" and ex5_esel_q="011") + else lrat_entry4_valid_q when (ex5_valid_q/="0000" and ex5_esel_q="100") + else lrat_entry5_valid_q when (ex5_valid_q/="0000" and ex5_esel_q="101") + else lrat_entry6_valid_q when (ex5_valid_q/="0000" and ex5_esel_q="110") + else lrat_entry7_valid_q when (ex5_valid_q/="0000" and ex5_esel_q="111") + else lrat_mas1_v_q; +lrat_mas1_tsize_d <= lrat_entry0_size_q when (ex5_valid_q/="0000" and ex5_esel_q="000") + else lrat_entry1_size_q when (ex5_valid_q/="0000" and ex5_esel_q="001") + else lrat_entry2_size_q when (ex5_valid_q/="0000" and ex5_esel_q="010") + else lrat_entry3_size_q when (ex5_valid_q/="0000" and ex5_esel_q="011") + else lrat_entry4_size_q when (ex5_valid_q/="0000" and ex5_esel_q="100") + else lrat_entry5_size_q when (ex5_valid_q/="0000" and ex5_esel_q="101") + else lrat_entry6_size_q when (ex5_valid_q/="0000" and ex5_esel_q="110") + else lrat_entry7_size_q when (ex5_valid_q/="0000" and ex5_esel_q="111") + else lrat_mas1_tsize_q; +lrat_mas2_epn_d(64-real_addr_width TO 64-lrat_minsize_log2-1) <= + lrat_entry0_lpn_q(64-real_addr_width to 64-lrat_minsize_log2-1) when (ex5_valid_q/="0000" and ex5_esel_q="000") + else lrat_entry1_lpn_q(64-real_addr_width to 64-lrat_minsize_log2-1) when (ex5_valid_q/="0000" and ex5_esel_q="001") + else lrat_entry2_lpn_q(64-real_addr_width to 64-lrat_minsize_log2-1) when (ex5_valid_q/="0000" and ex5_esel_q="010") + else lrat_entry3_lpn_q(64-real_addr_width to 64-lrat_minsize_log2-1) when (ex5_valid_q/="0000" and ex5_esel_q="011") + else lrat_entry4_lpn_q(64-real_addr_width to 64-lrat_minsize_log2-1) when (ex5_valid_q/="0000" and ex5_esel_q="100") + else lrat_entry5_lpn_q(64-real_addr_width to 64-lrat_minsize_log2-1) when (ex5_valid_q/="0000" and ex5_esel_q="101") + else lrat_entry6_lpn_q(64-real_addr_width to 64-lrat_minsize_log2-1) when (ex5_valid_q/="0000" and ex5_esel_q="110") + else lrat_entry7_lpn_q(64-real_addr_width to 64-lrat_minsize_log2-1) when (ex5_valid_q/="0000" and ex5_esel_q="111") + else lrat_mas2_epn_q(64-real_addr_width to 64-lrat_minsize_log2-1); +lrat_mas2_epn_d(64-lrat_minsize_log2 TO 51) <= + (others => '0') when (ex5_valid_q/="0000" and ex5_esel_q="000") + else (others => '0') when (ex5_valid_q/="0000" and ex5_esel_q="001") + else (others => '0') when (ex5_valid_q/="0000" and ex5_esel_q="010") + else (others => '0') when (ex5_valid_q/="0000" and ex5_esel_q="011") + else (others => '0') when (ex5_valid_q/="0000" and ex5_esel_q="100") + else (others => '0') when (ex5_valid_q/="0000" and ex5_esel_q="101") + else (others => '0') when (ex5_valid_q/="0000" and ex5_esel_q="110") + else (others => '0') when (ex5_valid_q/="0000" and ex5_esel_q="111") + else lrat_mas2_epn_q(64-lrat_minsize_log2 to 51); +lrat_mas3_rpnl_d(32 TO 64-lrat_minsize_log2-1) <= + lrat_entry0_rpn_q(32 to 64-lrat_minsize_log2-1) when (ex5_valid_q/="0000" and ex5_esel_q="000") + else lrat_entry1_rpn_q(32 to 64-lrat_minsize_log2-1) when (ex5_valid_q/="0000" and ex5_esel_q="001") + else lrat_entry2_rpn_q(32 to 64-lrat_minsize_log2-1) when (ex5_valid_q/="0000" and ex5_esel_q="010") + else lrat_entry3_rpn_q(32 to 64-lrat_minsize_log2-1) when (ex5_valid_q/="0000" and ex5_esel_q="011") + else lrat_entry4_rpn_q(32 to 64-lrat_minsize_log2-1) when (ex5_valid_q/="0000" and ex5_esel_q="100") + else lrat_entry5_rpn_q(32 to 64-lrat_minsize_log2-1) when (ex5_valid_q/="0000" and ex5_esel_q="101") + else lrat_entry6_rpn_q(32 to 64-lrat_minsize_log2-1) when (ex5_valid_q/="0000" and ex5_esel_q="110") + else lrat_entry7_rpn_q(32 to 64-lrat_minsize_log2-1) when (ex5_valid_q/="0000" and ex5_esel_q="111") + else lrat_mas3_rpnl_q(32 to 64-lrat_minsize_log2-1); +lrat_mas3_rpnl_d(64-lrat_minsize_log2 TO 51) <= + (others => '0') when (ex5_valid_q/="0000" and ex5_esel_q="000") + else (others => '0') when (ex5_valid_q/="0000" and ex5_esel_q="001") + else (others => '0') when (ex5_valid_q/="0000" and ex5_esel_q="010") + else (others => '0') when (ex5_valid_q/="0000" and ex5_esel_q="011") + else (others => '0') when (ex5_valid_q/="0000" and ex5_esel_q="100") + else (others => '0') when (ex5_valid_q/="0000" and ex5_esel_q="101") + else (others => '0') when (ex5_valid_q/="0000" and ex5_esel_q="110") + else (others => '0') when (ex5_valid_q/="0000" and ex5_esel_q="111") + else lrat_mas3_rpnl_q(64-lrat_minsize_log2 to 51); +lrat_mas7_rpnu_d(64-real_addr_width TO 31) <= + lrat_entry0_rpn_q(64-real_addr_width to 31) when (ex5_valid_q/="0000" and ex5_esel_q="000") + else lrat_entry1_rpn_q(64-real_addr_width to 31) when (ex5_valid_q/="0000" and ex5_esel_q="001") + else lrat_entry2_rpn_q(64-real_addr_width to 31) when (ex5_valid_q/="0000" and ex5_esel_q="010") + else lrat_entry3_rpn_q(64-real_addr_width to 31) when (ex5_valid_q/="0000" and ex5_esel_q="011") + else lrat_entry4_rpn_q(64-real_addr_width to 31) when (ex5_valid_q/="0000" and ex5_esel_q="100") + else lrat_entry5_rpn_q(64-real_addr_width to 31) when (ex5_valid_q/="0000" and ex5_esel_q="101") + else lrat_entry6_rpn_q(64-real_addr_width to 31) when (ex5_valid_q/="0000" and ex5_esel_q="110") + else lrat_entry7_rpn_q(64-real_addr_width to 31) when (ex5_valid_q/="0000" and ex5_esel_q="111") + else lrat_mas7_rpnu_q(64-real_addr_width to 31); +lrat_mas8_tlpid_d <= lrat_entry0_lpid_q when (ex5_valid_q/="0000" and ex5_esel_q="000") + else lrat_entry1_lpid_q when (ex5_valid_q/="0000" and ex5_esel_q="001") + else lrat_entry2_lpid_q when (ex5_valid_q/="0000" and ex5_esel_q="010") + else lrat_entry3_lpid_q when (ex5_valid_q/="0000" and ex5_esel_q="011") + else lrat_entry4_lpid_q when (ex5_valid_q/="0000" and ex5_esel_q="100") + else lrat_entry5_lpid_q when (ex5_valid_q/="0000" and ex5_esel_q="101") + else lrat_entry6_lpid_q when (ex5_valid_q/="0000" and ex5_esel_q="110") + else lrat_entry7_lpid_q when (ex5_valid_q/="0000" and ex5_esel_q="111") + else lrat_mas8_tlpid_q; +lrat_mas_tlbre_d <= '1' when ((ex5_valid_q and not(xu_ex5_flush))/="0000" + and ex5_ttype_q(0)='1' and ex5_atsel_q='1') + else '0'; +lrat_mas_tlbsx_hit_d <= '1' when (ex6_valid_q/="0000" and ex6_ttype_q(2 to 4)/="000" and ex6_ttype_q(0)='1' + and ex6_atsel_q='1' and lrat_tag3_hit_status_q(1)='1') + else '0'; +lrat_mas_tlbsx_miss_d <= '1' when (ex6_valid_q/="0000" and ex6_ttype_q(2 to 4)/="000" and ex6_ttype_q(0)='1' + and ex6_atsel_q='1' and lrat_tag3_hit_status_q(1)='0') + else '0'; +lrat_mas_thdid_d(0 TO thdid_width-1) <= (ex5_valid_q and (0 to thdid_width-1 => ex5_ttype_q(0))) + or (ex6_valid_q and (0 to thdid_width-1 => or_reduce(ex6_ttype_q(2 to 4)))); +lrat_mas_act_d(0) <= ((or_reduce(ex4_valid_q) and or_reduce(ex4_ttype_q)) or mmucr2_act_override) and xu_mm_ccr2_notlb_b; +lrat_mas_act_d(1) <= ((or_reduce(ex4_valid_q) and or_reduce(ex4_ttype_q)) or mmucr2_act_override) and xu_mm_ccr2_notlb_b; +lrat_mas_act_d(2) <= (((or_reduce(ex4_valid_q) and or_reduce(ex4_ttype_q)) or mmucr2_act_override) and xu_mm_ccr2_notlb_b) or + (((or_reduce(ex5_valid_q) and or_reduce(ex5_ttype_q)) or mmucr2_act_override) and xu_mm_ccr2_notlb_b) or + (((or_reduce(ex6_valid_q) and or_reduce(ex6_ttype_q)) or mmucr2_act_override) and xu_mm_ccr2_notlb_b); +lrat_datain_act_d(0) <= ((or_reduce(ex4_valid_q) and or_reduce(ex4_ttype_q)) or mmucr2_act_override) and xu_mm_ccr2_notlb_b; +lrat_datain_act_d(1) <= ((or_reduce(ex4_valid_q) and or_reduce(ex4_ttype_q)) or mmucr2_act_override) and xu_mm_ccr2_notlb_b; +lrat_entry0_lpn_d <= lrat_datain_lpn_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="000" and ex6_illeg_instr(1)='0') + else lrat_entry0_lpn_q; +lrat_entry0_rpn_d <= lrat_datain_rpn_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="000" and ex6_illeg_instr(1)='0') + else lrat_entry0_rpn_q; +lrat_entry0_lpid_d <= lrat_datain_lpid_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="000" and ex6_illeg_instr(1)='0') + else lrat_entry0_lpid_q; +lrat_entry0_size_d <= lrat_datain_size_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="000" and ex6_illeg_instr(1)='0') + else lrat_entry0_size_q; +lrat_entry0_xbit_d <= lrat_datain_xbit_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="000" and ex6_illeg_instr(1)='0') + else lrat_entry0_xbit_q; +lrat_entry0_valid_d <= lrat_datain_valid_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="000" and ex6_illeg_instr(1)='0') + else lrat_entry0_valid_q; +lrat_entry0_cmpmask_d(0) <= Eq(lrat_datain_size_q, LRAT_PgSize_1TB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="000" and ex6_illeg_instr(1)='0') + else lrat_entry0_cmpmask_q(0); +lrat_entry0_cmpmask_d(1) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="000" and ex6_illeg_instr(1)='0') + else lrat_entry0_cmpmask_q(1); +lrat_entry0_cmpmask_d(2) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="000" and ex6_illeg_instr(1)='0') + else lrat_entry0_cmpmask_q(2); +lrat_entry0_cmpmask_d(3) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="000" and ex6_illeg_instr(1)='0') + else lrat_entry0_cmpmask_q(3); +lrat_entry0_cmpmask_d(4) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_1GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="000" and ex6_illeg_instr(1)='0') + else lrat_entry0_cmpmask_q(4); +lrat_entry0_cmpmask_d(5) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_1GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256MB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="000" and ex6_illeg_instr(1)='0') + else lrat_entry0_cmpmask_q(5); +lrat_entry0_cmpmask_d(6) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_1GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256MB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16MB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="000" and ex6_illeg_instr(1)='0') + else lrat_entry0_cmpmask_q(6); +lrat_entry0_xbitmask_d(0) <= Eq(lrat_datain_size_q, LRAT_PgSize_1TB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="000" and ex6_illeg_instr(1)='0') + else lrat_entry0_xbitmask_q(0); +lrat_entry0_xbitmask_d(1) <= Eq(lrat_datain_size_q, LRAT_PgSize_256GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="000" and ex6_illeg_instr(1)='0') + else lrat_entry0_xbitmask_q(1); +lrat_entry0_xbitmask_d(2) <= Eq(lrat_datain_size_q, LRAT_PgSize_16GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="000" and ex6_illeg_instr(1)='0') + else lrat_entry0_xbitmask_q(2); +lrat_entry0_xbitmask_d(3) <= Eq(lrat_datain_size_q, LRAT_PgSize_4GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="000" and ex6_illeg_instr(1)='0') + else lrat_entry0_xbitmask_q(3); +lrat_entry0_xbitmask_d(4) <= Eq(lrat_datain_size_q, LRAT_PgSize_1GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="000" and ex6_illeg_instr(1)='0') + else lrat_entry0_xbitmask_q(4); +lrat_entry0_xbitmask_d(5) <= Eq(lrat_datain_size_q, LRAT_PgSize_256MB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="000" and ex6_illeg_instr(1)='0') + else lrat_entry0_xbitmask_q(5); +lrat_entry0_xbitmask_d(6) <= Eq(lrat_datain_size_q, LRAT_PgSize_16MB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="000" and ex6_illeg_instr(1)='0') + else lrat_entry0_xbitmask_q(6); +lrat_entry1_lpn_d <= lrat_datain_lpn_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="001" and ex6_illeg_instr(1)='0') + else lrat_entry1_lpn_q; +lrat_entry1_rpn_d <= lrat_datain_rpn_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="001" and ex6_illeg_instr(1)='0') + else lrat_entry1_rpn_q; +lrat_entry1_lpid_d <= lrat_datain_lpid_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="001" and ex6_illeg_instr(1)='0') + else lrat_entry1_lpid_q; +lrat_entry1_size_d <= lrat_datain_size_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="001" and ex6_illeg_instr(1)='0') + else lrat_entry1_size_q; +lrat_entry1_xbit_d <= lrat_datain_xbit_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="001" and ex6_illeg_instr(1)='0') + else lrat_entry1_xbit_q; +lrat_entry1_valid_d <= lrat_datain_valid_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="001" and ex6_illeg_instr(1)='0') + else lrat_entry1_valid_q; +lrat_entry1_cmpmask_d(0) <= Eq(lrat_datain_size_q, LRAT_PgSize_1TB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="001" and ex6_illeg_instr(1)='0') + else lrat_entry1_cmpmask_q(0); +lrat_entry1_cmpmask_d(1) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="001" and ex6_illeg_instr(1)='0') + else lrat_entry1_cmpmask_q(1); +lrat_entry1_cmpmask_d(2) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="001" and ex6_illeg_instr(1)='0') + else lrat_entry1_cmpmask_q(2); +lrat_entry1_cmpmask_d(3) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="001" and ex6_illeg_instr(1)='0') + else lrat_entry1_cmpmask_q(3); +lrat_entry1_cmpmask_d(4) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_1GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="001" and ex6_illeg_instr(1)='0') + else lrat_entry1_cmpmask_q(4); +lrat_entry1_cmpmask_d(5) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_1GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256MB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="001" and ex6_illeg_instr(1)='0') + else lrat_entry1_cmpmask_q(5); +lrat_entry1_cmpmask_d(6) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_1GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256MB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16MB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="001" and ex6_illeg_instr(1)='0') + else lrat_entry1_cmpmask_q(6); +lrat_entry1_xbitmask_d(0) <= Eq(lrat_datain_size_q, LRAT_PgSize_1TB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="001" and ex6_illeg_instr(1)='0') + else lrat_entry1_xbitmask_q(0); +lrat_entry1_xbitmask_d(1) <= Eq(lrat_datain_size_q, LRAT_PgSize_256GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="001" and ex6_illeg_instr(1)='0') + else lrat_entry1_xbitmask_q(1); +lrat_entry1_xbitmask_d(2) <= Eq(lrat_datain_size_q, LRAT_PgSize_16GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="001" and ex6_illeg_instr(1)='0') + else lrat_entry1_xbitmask_q(2); +lrat_entry1_xbitmask_d(3) <= Eq(lrat_datain_size_q, LRAT_PgSize_4GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="001" and ex6_illeg_instr(1)='0') + else lrat_entry1_xbitmask_q(3); +lrat_entry1_xbitmask_d(4) <= Eq(lrat_datain_size_q, LRAT_PgSize_1GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="001" and ex6_illeg_instr(1)='0') + else lrat_entry1_xbitmask_q(4); +lrat_entry1_xbitmask_d(5) <= Eq(lrat_datain_size_q, LRAT_PgSize_256MB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="001" and ex6_illeg_instr(1)='0') + else lrat_entry1_xbitmask_q(5); +lrat_entry1_xbitmask_d(6) <= Eq(lrat_datain_size_q, LRAT_PgSize_16MB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="001" and ex6_illeg_instr(1)='0') + else lrat_entry1_xbitmask_q(6); +lrat_entry2_lpn_d <= lrat_datain_lpn_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="010" and ex6_illeg_instr(1)='0') + else lrat_entry2_lpn_q; +lrat_entry2_rpn_d <= lrat_datain_rpn_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="010" and ex6_illeg_instr(1)='0') + else lrat_entry2_rpn_q; +lrat_entry2_lpid_d <= lrat_datain_lpid_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="010" and ex6_illeg_instr(1)='0') + else lrat_entry2_lpid_q; +lrat_entry2_size_d <= lrat_datain_size_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="010" and ex6_illeg_instr(1)='0') + else lrat_entry2_size_q; +lrat_entry2_xbit_d <= lrat_datain_xbit_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="010" and ex6_illeg_instr(1)='0') + else lrat_entry2_xbit_q; +lrat_entry2_valid_d <= lrat_datain_valid_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="010" and ex6_illeg_instr(1)='0') + else lrat_entry2_valid_q; +lrat_entry2_cmpmask_d(0) <= Eq(lrat_datain_size_q, LRAT_PgSize_1TB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="010" and ex6_illeg_instr(1)='0') + else lrat_entry2_cmpmask_q(0); +lrat_entry2_cmpmask_d(1) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="010" and ex6_illeg_instr(1)='0') + else lrat_entry2_cmpmask_q(1); +lrat_entry2_cmpmask_d(2) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="010" and ex6_illeg_instr(1)='0') + else lrat_entry2_cmpmask_q(2); +lrat_entry2_cmpmask_d(3) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="010" and ex6_illeg_instr(1)='0') + else lrat_entry2_cmpmask_q(3); +lrat_entry2_cmpmask_d(4) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_1GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="010" and ex6_illeg_instr(1)='0') + else lrat_entry2_cmpmask_q(4); +lrat_entry2_cmpmask_d(5) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_1GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256MB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="010" and ex6_illeg_instr(1)='0') + else lrat_entry2_cmpmask_q(5); +lrat_entry2_cmpmask_d(6) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_1GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256MB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16MB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="010" and ex6_illeg_instr(1)='0') + else lrat_entry2_cmpmask_q(6); +lrat_entry2_xbitmask_d(0) <= Eq(lrat_datain_size_q, LRAT_PgSize_1TB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="010" and ex6_illeg_instr(1)='0') + else lrat_entry2_xbitmask_q(0); +lrat_entry2_xbitmask_d(1) <= Eq(lrat_datain_size_q, LRAT_PgSize_256GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="010" and ex6_illeg_instr(1)='0') + else lrat_entry2_xbitmask_q(1); +lrat_entry2_xbitmask_d(2) <= Eq(lrat_datain_size_q, LRAT_PgSize_16GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="010" and ex6_illeg_instr(1)='0') + else lrat_entry2_xbitmask_q(2); +lrat_entry2_xbitmask_d(3) <= Eq(lrat_datain_size_q, LRAT_PgSize_4GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="010" and ex6_illeg_instr(1)='0') + else lrat_entry2_xbitmask_q(3); +lrat_entry2_xbitmask_d(4) <= Eq(lrat_datain_size_q, LRAT_PgSize_1GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="010" and ex6_illeg_instr(1)='0') + else lrat_entry2_xbitmask_q(4); +lrat_entry2_xbitmask_d(5) <= Eq(lrat_datain_size_q, LRAT_PgSize_256MB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="010" and ex6_illeg_instr(1)='0') + else lrat_entry2_xbitmask_q(5); +lrat_entry2_xbitmask_d(6) <= Eq(lrat_datain_size_q, LRAT_PgSize_16MB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="010" and ex6_illeg_instr(1)='0') + else lrat_entry2_xbitmask_q(6); +lrat_entry3_lpn_d <= lrat_datain_lpn_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="011" and ex6_illeg_instr(1)='0') + else lrat_entry3_lpn_q; +lrat_entry3_rpn_d <= lrat_datain_rpn_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="011" and ex6_illeg_instr(1)='0') + else lrat_entry3_rpn_q; +lrat_entry3_lpid_d <= lrat_datain_lpid_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="011" and ex6_illeg_instr(1)='0') + else lrat_entry3_lpid_q; +lrat_entry3_size_d <= lrat_datain_size_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="011" and ex6_illeg_instr(1)='0') + else lrat_entry3_size_q; +lrat_entry3_xbit_d <= lrat_datain_xbit_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="011" and ex6_illeg_instr(1)='0') + else lrat_entry3_xbit_q; +lrat_entry3_valid_d <= lrat_datain_valid_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="011" and ex6_illeg_instr(1)='0') + else lrat_entry3_valid_q; +lrat_entry3_cmpmask_d(0) <= Eq(lrat_datain_size_q, LRAT_PgSize_1TB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="011" and ex6_illeg_instr(1)='0') + else lrat_entry3_cmpmask_q(0); +lrat_entry3_cmpmask_d(1) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="011" and ex6_illeg_instr(1)='0') + else lrat_entry3_cmpmask_q(1); +lrat_entry3_cmpmask_d(2) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="011" and ex6_illeg_instr(1)='0') + else lrat_entry3_cmpmask_q(2); +lrat_entry3_cmpmask_d(3) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="011" and ex6_illeg_instr(1)='0') + else lrat_entry3_cmpmask_q(3); +lrat_entry3_cmpmask_d(4) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_1GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="011" and ex6_illeg_instr(1)='0') + else lrat_entry3_cmpmask_q(4); +lrat_entry3_cmpmask_d(5) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_1GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256MB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="011" and ex6_illeg_instr(1)='0') + else lrat_entry3_cmpmask_q(5); +lrat_entry3_cmpmask_d(6) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_1GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256MB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16MB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="011" and ex6_illeg_instr(1)='0') + else lrat_entry3_cmpmask_q(6); +lrat_entry3_xbitmask_d(0) <= Eq(lrat_datain_size_q, LRAT_PgSize_1TB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="011" and ex6_illeg_instr(1)='0') + else lrat_entry3_xbitmask_q(0); +lrat_entry3_xbitmask_d(1) <= Eq(lrat_datain_size_q, LRAT_PgSize_256GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="011" and ex6_illeg_instr(1)='0') + else lrat_entry3_xbitmask_q(1); +lrat_entry3_xbitmask_d(2) <= Eq(lrat_datain_size_q, LRAT_PgSize_16GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="011" and ex6_illeg_instr(1)='0') + else lrat_entry3_xbitmask_q(2); +lrat_entry3_xbitmask_d(3) <= Eq(lrat_datain_size_q, LRAT_PgSize_4GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="011" and ex6_illeg_instr(1)='0') + else lrat_entry3_xbitmask_q(3); +lrat_entry3_xbitmask_d(4) <= Eq(lrat_datain_size_q, LRAT_PgSize_1GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="011" and ex6_illeg_instr(1)='0') + else lrat_entry3_xbitmask_q(4); +lrat_entry3_xbitmask_d(5) <= Eq(lrat_datain_size_q, LRAT_PgSize_256MB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="011" and ex6_illeg_instr(1)='0') + else lrat_entry3_xbitmask_q(5); +lrat_entry3_xbitmask_d(6) <= Eq(lrat_datain_size_q, LRAT_PgSize_16MB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="011" and ex6_illeg_instr(1)='0') + else lrat_entry3_xbitmask_q(6); +lrat_entry4_lpn_d <= lrat_datain_lpn_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="100" and ex6_illeg_instr(1)='0') + else lrat_entry4_lpn_q; +lrat_entry4_rpn_d <= lrat_datain_rpn_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="100" and ex6_illeg_instr(1)='0') + else lrat_entry4_rpn_q; +lrat_entry4_lpid_d <= lrat_datain_lpid_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="100" and ex6_illeg_instr(1)='0') + else lrat_entry4_lpid_q; +lrat_entry4_size_d <= lrat_datain_size_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="100" and ex6_illeg_instr(1)='0') + else lrat_entry4_size_q; +lrat_entry4_xbit_d <= lrat_datain_xbit_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="100" and ex6_illeg_instr(1)='0') + else lrat_entry4_xbit_q; +lrat_entry4_valid_d <= lrat_datain_valid_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="100" and ex6_illeg_instr(1)='0') + else lrat_entry4_valid_q; +lrat_entry4_cmpmask_d(0) <= Eq(lrat_datain_size_q, LRAT_PgSize_1TB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="100" and ex6_illeg_instr(1)='0') + else lrat_entry4_cmpmask_q(0); +lrat_entry4_cmpmask_d(1) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="100" and ex6_illeg_instr(1)='0') + else lrat_entry4_cmpmask_q(1); +lrat_entry4_cmpmask_d(2) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="100" and ex6_illeg_instr(1)='0') + else lrat_entry4_cmpmask_q(2); +lrat_entry4_cmpmask_d(3) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="100" and ex6_illeg_instr(1)='0') + else lrat_entry4_cmpmask_q(3); +lrat_entry4_cmpmask_d(4) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_1GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="100" and ex6_illeg_instr(1)='0') + else lrat_entry4_cmpmask_q(4); +lrat_entry4_cmpmask_d(5) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_1GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256MB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="100" and ex6_illeg_instr(1)='0') + else lrat_entry4_cmpmask_q(5); +lrat_entry4_cmpmask_d(6) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_1GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256MB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16MB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="100" and ex6_illeg_instr(1)='0') + else lrat_entry4_cmpmask_q(6); +lrat_entry4_xbitmask_d(0) <= Eq(lrat_datain_size_q, LRAT_PgSize_1TB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="100" and ex6_illeg_instr(1)='0') + else lrat_entry4_xbitmask_q(0); +lrat_entry4_xbitmask_d(1) <= Eq(lrat_datain_size_q, LRAT_PgSize_256GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="100" and ex6_illeg_instr(1)='0') + else lrat_entry4_xbitmask_q(1); +lrat_entry4_xbitmask_d(2) <= Eq(lrat_datain_size_q, LRAT_PgSize_16GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="100" and ex6_illeg_instr(1)='0') + else lrat_entry4_xbitmask_q(2); +lrat_entry4_xbitmask_d(3) <= Eq(lrat_datain_size_q, LRAT_PgSize_4GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="100" and ex6_illeg_instr(1)='0') + else lrat_entry4_xbitmask_q(3); +lrat_entry4_xbitmask_d(4) <= Eq(lrat_datain_size_q, LRAT_PgSize_1GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="100" and ex6_illeg_instr(1)='0') + else lrat_entry4_xbitmask_q(4); +lrat_entry4_xbitmask_d(5) <= Eq(lrat_datain_size_q, LRAT_PgSize_256MB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="100" and ex6_illeg_instr(1)='0') + else lrat_entry4_xbitmask_q(5); +lrat_entry4_xbitmask_d(6) <= Eq(lrat_datain_size_q, LRAT_PgSize_16MB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="100" and ex6_illeg_instr(1)='0') + else lrat_entry4_xbitmask_q(6); +lrat_entry5_lpn_d <= lrat_datain_lpn_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="101" and ex6_illeg_instr(1)='0') + else lrat_entry5_lpn_q; +lrat_entry5_rpn_d <= lrat_datain_rpn_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="101" and ex6_illeg_instr(1)='0') + else lrat_entry5_rpn_q; +lrat_entry5_lpid_d <= lrat_datain_lpid_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="101" and ex6_illeg_instr(1)='0') + else lrat_entry5_lpid_q; +lrat_entry5_size_d <= lrat_datain_size_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="101" and ex6_illeg_instr(1)='0') + else lrat_entry5_size_q; +lrat_entry5_xbit_d <= lrat_datain_xbit_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="101" and ex6_illeg_instr(1)='0') + else lrat_entry5_xbit_q; +lrat_entry5_valid_d <= lrat_datain_valid_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="101" and ex6_illeg_instr(1)='0') + else lrat_entry5_valid_q; +lrat_entry5_cmpmask_d(0) <= Eq(lrat_datain_size_q, LRAT_PgSize_1TB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="101" and ex6_illeg_instr(1)='0') + else lrat_entry5_cmpmask_q(0); +lrat_entry5_cmpmask_d(1) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="101" and ex6_illeg_instr(1)='0') + else lrat_entry5_cmpmask_q(1); +lrat_entry5_cmpmask_d(2) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="101" and ex6_illeg_instr(1)='0') + else lrat_entry5_cmpmask_q(2); +lrat_entry5_cmpmask_d(3) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="101" and ex6_illeg_instr(1)='0') + else lrat_entry5_cmpmask_q(3); +lrat_entry5_cmpmask_d(4) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_1GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="101" and ex6_illeg_instr(1)='0') + else lrat_entry5_cmpmask_q(4); +lrat_entry5_cmpmask_d(5) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_1GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256MB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="101" and ex6_illeg_instr(1)='0') + else lrat_entry5_cmpmask_q(5); +lrat_entry5_cmpmask_d(6) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_1GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256MB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16MB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="101" and ex6_illeg_instr(1)='0') + else lrat_entry5_cmpmask_q(6); +lrat_entry5_xbitmask_d(0) <= Eq(lrat_datain_size_q, LRAT_PgSize_1TB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="101" and ex6_illeg_instr(1)='0') + else lrat_entry5_xbitmask_q(0); +lrat_entry5_xbitmask_d(1) <= Eq(lrat_datain_size_q, LRAT_PgSize_256GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="101" and ex6_illeg_instr(1)='0') + else lrat_entry5_xbitmask_q(1); +lrat_entry5_xbitmask_d(2) <= Eq(lrat_datain_size_q, LRAT_PgSize_16GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="101" and ex6_illeg_instr(1)='0') + else lrat_entry5_xbitmask_q(2); +lrat_entry5_xbitmask_d(3) <= Eq(lrat_datain_size_q, LRAT_PgSize_4GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="101" and ex6_illeg_instr(1)='0') + else lrat_entry5_xbitmask_q(3); +lrat_entry5_xbitmask_d(4) <= Eq(lrat_datain_size_q, LRAT_PgSize_1GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="101" and ex6_illeg_instr(1)='0') + else lrat_entry5_xbitmask_q(4); +lrat_entry5_xbitmask_d(5) <= Eq(lrat_datain_size_q, LRAT_PgSize_256MB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="101" and ex6_illeg_instr(1)='0') + else lrat_entry5_xbitmask_q(5); +lrat_entry5_xbitmask_d(6) <= Eq(lrat_datain_size_q, LRAT_PgSize_16MB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="101" and ex6_illeg_instr(1)='0') + else lrat_entry5_xbitmask_q(6); +lrat_entry6_lpn_d <= lrat_datain_lpn_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="110" and ex6_illeg_instr(1)='0') + else lrat_entry6_lpn_q; +lrat_entry6_rpn_d <= lrat_datain_rpn_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="110" and ex6_illeg_instr(1)='0') + else lrat_entry6_rpn_q; +lrat_entry6_lpid_d <= lrat_datain_lpid_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="110" and ex6_illeg_instr(1)='0') + else lrat_entry6_lpid_q; +lrat_entry6_size_d <= lrat_datain_size_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="110" and ex6_illeg_instr(1)='0') + else lrat_entry6_size_q; +lrat_entry6_xbit_d <= lrat_datain_xbit_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="110" and ex6_illeg_instr(1)='0') + else lrat_entry6_xbit_q; +lrat_entry6_valid_d <= lrat_datain_valid_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="110" and ex6_illeg_instr(1)='0') + else lrat_entry6_valid_q; +lrat_entry6_cmpmask_d(0) <= Eq(lrat_datain_size_q, LRAT_PgSize_1TB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="110" and ex6_illeg_instr(1)='0') + else lrat_entry6_cmpmask_q(0); +lrat_entry6_cmpmask_d(1) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="110" and ex6_illeg_instr(1)='0') + else lrat_entry6_cmpmask_q(1); +lrat_entry6_cmpmask_d(2) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="110" and ex6_illeg_instr(1)='0') + else lrat_entry6_cmpmask_q(2); +lrat_entry6_cmpmask_d(3) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="110" and ex6_illeg_instr(1)='0') + else lrat_entry6_cmpmask_q(3); +lrat_entry6_cmpmask_d(4) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_1GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="110" and ex6_illeg_instr(1)='0') + else lrat_entry6_cmpmask_q(4); +lrat_entry6_cmpmask_d(5) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_1GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256MB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="110" and ex6_illeg_instr(1)='0') + else lrat_entry6_cmpmask_q(5); +lrat_entry6_cmpmask_d(6) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_1GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256MB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16MB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="110" and ex6_illeg_instr(1)='0') + else lrat_entry6_cmpmask_q(6); +lrat_entry6_xbitmask_d(0) <= Eq(lrat_datain_size_q, LRAT_PgSize_1TB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="110" and ex6_illeg_instr(1)='0') + else lrat_entry6_xbitmask_q(0); +lrat_entry6_xbitmask_d(1) <= Eq(lrat_datain_size_q, LRAT_PgSize_256GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="110" and ex6_illeg_instr(1)='0') + else lrat_entry6_xbitmask_q(1); +lrat_entry6_xbitmask_d(2) <= Eq(lrat_datain_size_q, LRAT_PgSize_16GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="110" and ex6_illeg_instr(1)='0') + else lrat_entry6_xbitmask_q(2); +lrat_entry6_xbitmask_d(3) <= Eq(lrat_datain_size_q, LRAT_PgSize_4GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="110" and ex6_illeg_instr(1)='0') + else lrat_entry6_xbitmask_q(3); +lrat_entry6_xbitmask_d(4) <= Eq(lrat_datain_size_q, LRAT_PgSize_1GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="110" and ex6_illeg_instr(1)='0') + else lrat_entry6_xbitmask_q(4); +lrat_entry6_xbitmask_d(5) <= Eq(lrat_datain_size_q, LRAT_PgSize_256MB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="110" and ex6_illeg_instr(1)='0') + else lrat_entry6_xbitmask_q(5); +lrat_entry6_xbitmask_d(6) <= Eq(lrat_datain_size_q, LRAT_PgSize_16MB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="110" and ex6_illeg_instr(1)='0') + else lrat_entry6_xbitmask_q(6); +lrat_entry7_lpn_d <= lrat_datain_lpn_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="111" and ex6_illeg_instr(1)='0') + else lrat_entry7_lpn_q; +lrat_entry7_rpn_d <= lrat_datain_rpn_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="111" and ex6_illeg_instr(1)='0') + else lrat_entry7_rpn_q; +lrat_entry7_lpid_d <= lrat_datain_lpid_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="111" and ex6_illeg_instr(1)='0') + else lrat_entry7_lpid_q; +lrat_entry7_size_d <= lrat_datain_size_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="111" and ex6_illeg_instr(1)='0') + else lrat_entry7_size_q; +lrat_entry7_xbit_d <= lrat_datain_xbit_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="111" and ex6_illeg_instr(1)='0') + else lrat_entry7_xbit_q; +lrat_entry7_valid_d <= lrat_datain_valid_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="111" and ex6_illeg_instr(1)='0') + else lrat_entry7_valid_q; +lrat_entry7_cmpmask_d(0) <= Eq(lrat_datain_size_q, LRAT_PgSize_1TB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="111" and ex6_illeg_instr(1)='0') + else lrat_entry7_cmpmask_q(0); +lrat_entry7_cmpmask_d(1) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="111" and ex6_illeg_instr(1)='0') + else lrat_entry7_cmpmask_q(1); +lrat_entry7_cmpmask_d(2) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="111" and ex6_illeg_instr(1)='0') + else lrat_entry7_cmpmask_q(2); +lrat_entry7_cmpmask_d(3) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="111" and ex6_illeg_instr(1)='0') + else lrat_entry7_cmpmask_q(3); +lrat_entry7_cmpmask_d(4) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_1GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="111" and ex6_illeg_instr(1)='0') + else lrat_entry7_cmpmask_q(4); +lrat_entry7_cmpmask_d(5) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_1GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256MB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="111" and ex6_illeg_instr(1)='0') + else lrat_entry7_cmpmask_q(5); +lrat_entry7_cmpmask_d(6) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_1GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256MB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16MB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="111" and ex6_illeg_instr(1)='0') + else lrat_entry7_cmpmask_q(6); +lrat_entry7_xbitmask_d(0) <= Eq(lrat_datain_size_q, LRAT_PgSize_1TB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="111" and ex6_illeg_instr(1)='0') + else lrat_entry7_xbitmask_q(0); +lrat_entry7_xbitmask_d(1) <= Eq(lrat_datain_size_q, LRAT_PgSize_256GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="111" and ex6_illeg_instr(1)='0') + else lrat_entry7_xbitmask_q(1); +lrat_entry7_xbitmask_d(2) <= Eq(lrat_datain_size_q, LRAT_PgSize_16GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="111" and ex6_illeg_instr(1)='0') + else lrat_entry7_xbitmask_q(2); +lrat_entry7_xbitmask_d(3) <= Eq(lrat_datain_size_q, LRAT_PgSize_4GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="111" and ex6_illeg_instr(1)='0') + else lrat_entry7_xbitmask_q(3); +lrat_entry7_xbitmask_d(4) <= Eq(lrat_datain_size_q, LRAT_PgSize_1GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="111" and ex6_illeg_instr(1)='0') + else lrat_entry7_xbitmask_q(4); +lrat_entry7_xbitmask_d(5) <= Eq(lrat_datain_size_q, LRAT_PgSize_256MB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="111" and ex6_illeg_instr(1)='0') + else lrat_entry7_xbitmask_q(5); +lrat_entry7_xbitmask_d(6) <= Eq(lrat_datain_size_q, LRAT_PgSize_16MB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="111" and ex6_illeg_instr(1)='0') + else lrat_entry7_xbitmask_q(6); +lrat_entry_act_d(0 TO 7) <= (0 to 7 => ((or_reduce(ex5_valid_q) and ex5_atsel_q) or mmucr2_act_override) and xu_mm_ccr2_notlb_b); +matchline_comb0 : mmq_tlb_lrat_matchline + generic map (real_addr_width => real_addr_width, + lpid_width => 8, + lrat_maxsize_log2 => const_lrat_maxsize_log2, + lrat_minsize_log2 => 20, + have_xbit => 1, + num_pgsizes => 8, + have_cmpmask => 1, + cmpmask_width => 7) + port map ( + vdd => vdd, + gnd => gnd, + addr_in => lrat_tag1_lpn_q(64-real_addr_width to 64-lrat_minsize_log2-1), + addr_enable => addr_enable, + entry_size => lrat_entry0_size_q(0 to 3), + entry_cmpmask => lrat_entry0_cmpmask_q(0 to 6), + entry_xbit => lrat_entry0_xbit_q, + entry_xbitmask => lrat_entry0_xbitmask_q(0 to 6), + entry_lpn => lrat_entry0_lpn_q(64-real_addr_width to 64-lrat_minsize_log2-1), + entry_lpid => lrat_entry0_lpid_q(0 to lpid_width-1), + comp_lpid => lrat_tag1_lpid_q(0 to lpid_width-1), + lpid_enable => lpid_enable, + entry_v => lrat_entry0_valid_q, + + match => lrat_tag1_matchline(0), + + dbg_addr_match => lrat_entry0_addr_match, + dbg_lpid_match => lrat_entry0_lpid_match + + ); +matchline_comb1 : mmq_tlb_lrat_matchline + generic map (real_addr_width => real_addr_width, + lpid_width => 8, + lrat_maxsize_log2 => const_lrat_maxsize_log2, + lrat_minsize_log2 => 20, + have_xbit => 1, + num_pgsizes => 8, + have_cmpmask => 1, + cmpmask_width => 7) + port map ( + vdd => vdd, + gnd => gnd, + addr_in => lrat_tag1_lpn_q(64-real_addr_width to 64-lrat_minsize_log2-1), + addr_enable => addr_enable, + entry_size => lrat_entry1_size_q(0 to 3), + entry_cmpmask => lrat_entry1_cmpmask_q(0 to 6), + entry_xbit => lrat_entry1_xbit_q, + entry_xbitmask => lrat_entry1_xbitmask_q(0 to 6), + entry_lpn => lrat_entry1_lpn_q(64-real_addr_width to 64-lrat_minsize_log2-1), + entry_lpid => lrat_entry1_lpid_q(0 to lpid_width-1), + comp_lpid => lrat_tag1_lpid_q(0 to lpid_width-1), + lpid_enable => lpid_enable, + entry_v => lrat_entry1_valid_q, + + match => lrat_tag1_matchline(1), + + dbg_addr_match => lrat_entry1_addr_match, + dbg_lpid_match => lrat_entry1_lpid_match + + ); +matchline_comb2 : mmq_tlb_lrat_matchline + generic map (real_addr_width => real_addr_width, + lpid_width => 8, + lrat_maxsize_log2 => const_lrat_maxsize_log2, + lrat_minsize_log2 => 20, + have_xbit => 1, + num_pgsizes => 8, + have_cmpmask => 1, + cmpmask_width => 7) + port map ( + vdd => vdd, + gnd => gnd, + addr_in => lrat_tag1_lpn_q(64-real_addr_width to 64-lrat_minsize_log2-1), + addr_enable => addr_enable, + entry_size => lrat_entry2_size_q(0 to 3), + entry_cmpmask => lrat_entry2_cmpmask_q(0 to 6), + entry_xbit => lrat_entry2_xbit_q, + entry_xbitmask => lrat_entry2_xbitmask_q(0 to 6), + entry_lpn => lrat_entry2_lpn_q(64-real_addr_width to 64-lrat_minsize_log2-1), + entry_lpid => lrat_entry2_lpid_q(0 to lpid_width-1), + comp_lpid => lrat_tag1_lpid_q(0 to lpid_width-1), + lpid_enable => lpid_enable, + entry_v => lrat_entry2_valid_q, + + match => lrat_tag1_matchline(2), + + dbg_addr_match => lrat_entry2_addr_match, + dbg_lpid_match => lrat_entry2_lpid_match + + ); +matchline_comb3 : mmq_tlb_lrat_matchline + generic map (real_addr_width => real_addr_width, + lpid_width => 8, + lrat_maxsize_log2 => const_lrat_maxsize_log2, + lrat_minsize_log2 => 20, + have_xbit => 1, + num_pgsizes => 8, + have_cmpmask => 1, + cmpmask_width => 7) + port map ( + vdd => vdd, + gnd => gnd, + addr_in => lrat_tag1_lpn_q(64-real_addr_width to 64-lrat_minsize_log2-1), + addr_enable => addr_enable, + entry_size => lrat_entry3_size_q(0 to 3), + entry_cmpmask => lrat_entry3_cmpmask_q(0 to 6), + entry_xbit => lrat_entry3_xbit_q, + entry_xbitmask => lrat_entry3_xbitmask_q(0 to 6), + entry_lpn => lrat_entry3_lpn_q(64-real_addr_width to 64-lrat_minsize_log2-1), + entry_lpid => lrat_entry3_lpid_q(0 to lpid_width-1), + comp_lpid => lrat_tag1_lpid_q(0 to lpid_width-1), + lpid_enable => lpid_enable, + entry_v => lrat_entry3_valid_q, + + match => lrat_tag1_matchline(3), + + dbg_addr_match => lrat_entry3_addr_match, + dbg_lpid_match => lrat_entry3_lpid_match + + ); +matchline_comb4 : mmq_tlb_lrat_matchline + generic map (real_addr_width => real_addr_width, + lpid_width => 8, + lrat_maxsize_log2 => const_lrat_maxsize_log2, + lrat_minsize_log2 => 20, + have_xbit => 1, + num_pgsizes => 8, + have_cmpmask => 1, + cmpmask_width => 7) + port map ( + vdd => vdd, + gnd => gnd, + addr_in => lrat_tag1_lpn_q(64-real_addr_width to 64-lrat_minsize_log2-1), + addr_enable => addr_enable, + entry_size => lrat_entry4_size_q(0 to 3), + entry_cmpmask => lrat_entry4_cmpmask_q(0 to 6), + entry_xbit => lrat_entry4_xbit_q, + entry_xbitmask => lrat_entry4_xbitmask_q(0 to 6), + entry_lpn => lrat_entry4_lpn_q(64-real_addr_width to 64-lrat_minsize_log2-1), + entry_lpid => lrat_entry4_lpid_q(0 to lpid_width-1), + comp_lpid => lrat_tag1_lpid_q(0 to lpid_width-1), + lpid_enable => lpid_enable, + entry_v => lrat_entry4_valid_q, + + match => lrat_tag1_matchline(4), + + dbg_addr_match => lrat_entry4_addr_match, + dbg_lpid_match => lrat_entry4_lpid_match + + ); +matchline_comb5 : mmq_tlb_lrat_matchline + generic map (real_addr_width => real_addr_width, + lpid_width => 8, + lrat_maxsize_log2 => const_lrat_maxsize_log2, + lrat_minsize_log2 => 20, + have_xbit => 1, + num_pgsizes => 8, + have_cmpmask => 1, + cmpmask_width => 7) + port map ( + vdd => vdd, + gnd => gnd, + addr_in => lrat_tag1_lpn_q(64-real_addr_width to 64-lrat_minsize_log2-1), + addr_enable => addr_enable, + entry_size => lrat_entry5_size_q(0 to 3), + entry_cmpmask => lrat_entry5_cmpmask_q(0 to 6), + entry_xbit => lrat_entry5_xbit_q, + entry_xbitmask => lrat_entry5_xbitmask_q(0 to 6), + entry_lpn => lrat_entry5_lpn_q(64-real_addr_width to 64-lrat_minsize_log2-1), + entry_lpid => lrat_entry5_lpid_q(0 to lpid_width-1), + comp_lpid => lrat_tag1_lpid_q(0 to lpid_width-1), + lpid_enable => lpid_enable, + entry_v => lrat_entry5_valid_q, + + match => lrat_tag1_matchline(5), + + dbg_addr_match => lrat_entry5_addr_match, + dbg_lpid_match => lrat_entry5_lpid_match + + ); +matchline_comb6 : mmq_tlb_lrat_matchline + generic map (real_addr_width => real_addr_width, + lpid_width => 8, + lrat_maxsize_log2 => const_lrat_maxsize_log2, + lrat_minsize_log2 => 20, + have_xbit => 1, + num_pgsizes => 8, + have_cmpmask => 1, + cmpmask_width => 7) + port map ( + vdd => vdd, + gnd => gnd, + addr_in => lrat_tag1_lpn_q(64-real_addr_width to 64-lrat_minsize_log2-1), + addr_enable => addr_enable, + entry_size => lrat_entry6_size_q(0 to 3), + entry_cmpmask => lrat_entry6_cmpmask_q(0 to 6), + entry_xbit => lrat_entry6_xbit_q, + entry_xbitmask => lrat_entry6_xbitmask_q(0 to 6), + entry_lpn => lrat_entry6_lpn_q(64-real_addr_width to 64-lrat_minsize_log2-1), + entry_lpid => lrat_entry6_lpid_q(0 to lpid_width-1), + comp_lpid => lrat_tag1_lpid_q(0 to lpid_width-1), + lpid_enable => lpid_enable, + entry_v => lrat_entry6_valid_q, + + match => lrat_tag1_matchline(6), + + dbg_addr_match => lrat_entry6_addr_match, + dbg_lpid_match => lrat_entry6_lpid_match + + ); +matchline_comb7 : mmq_tlb_lrat_matchline + generic map (real_addr_width => real_addr_width, + lpid_width => 8, + lrat_maxsize_log2 => const_lrat_maxsize_log2, + lrat_minsize_log2 => 20, + have_xbit => 1, + num_pgsizes => 8, + have_cmpmask => 1, + cmpmask_width => 7) + port map ( + vdd => vdd, + gnd => gnd, + addr_in => lrat_tag1_lpn_q(64-real_addr_width to 64-lrat_minsize_log2-1), + addr_enable => addr_enable, + entry_size => lrat_entry7_size_q(0 to 3), + entry_cmpmask => lrat_entry7_cmpmask_q(0 to 6), + entry_xbit => lrat_entry7_xbit_q, + entry_xbitmask => lrat_entry7_xbitmask_q(0 to 6), + entry_lpn => lrat_entry7_lpn_q(64-real_addr_width to 64-lrat_minsize_log2-1), + entry_lpid => lrat_entry7_lpid_q(0 to lpid_width-1), + comp_lpid => lrat_tag1_lpid_q(0 to lpid_width-1), + lpid_enable => lpid_enable, + entry_v => lrat_entry7_valid_q, + + match => lrat_tag1_matchline(7), + + dbg_addr_match => lrat_entry7_addr_match, + dbg_lpid_match => lrat_entry7_lpid_match + + ); +lrat_tag3_lpn <= lrat_tag3_lpn_q(64-real_addr_width to 51); +lrat_tag3_rpn <= lrat_tag3_rpn_q(64-real_addr_width to 51); +lrat_tag3_hit_status <= lrat_tag3_hit_status_q; +lrat_tag3_hit_entry <= lrat_tag3_hit_entry_q; +lrat_tag4_lpn <= lrat_tag4_lpn_q(64-real_addr_width to 51); +lrat_tag4_rpn <= lrat_tag4_rpn_q(64-real_addr_width to 51); +lrat_tag4_hit_status <= lrat_tag4_hit_status_q; +lrat_tag4_hit_entry <= lrat_tag4_hit_entry_q; +lrat_mas0_esel <= lrat_tag4_hit_entry_q; +lrat_mas1_v <= lrat_mas1_v_q; +lrat_mas1_tsize <= lrat_mas1_tsize_q; +gen64_lrat_mas2_epn: if real_addr_width > 32 generate +lrat_mas2_epn(0 TO 63-real_addr_width) <= (others => '0'); +lrat_mas2_epn(64-real_addr_width TO 31) <= lrat_mas2_epn_q(64-real_addr_width to 31); +lrat_mas2_epn(32 TO 51) <= lrat_mas2_epn_q(32 to 51); +end generate gen64_lrat_mas2_epn; +gen32_lrat_mas2_epn: if real_addr_width < 33 generate +lrat_mas2_epn(0 TO 63-real_addr_width) <= (others => '0'); +lrat_mas2_epn(64-real_addr_width TO 51) <= lrat_mas2_epn_q(64-real_addr_width to 51); +end generate gen32_lrat_mas2_epn; +lrat_mas3_rpnl <= lrat_mas3_rpnl_q; +lrat_mas7_rpnu <= lrat_mas7_rpnu_q; +lrat_mas8_tlpid <= lrat_mas8_tlpid_q; +lrat_mas_tlbre <= lrat_mas_tlbre_q; +lrat_mas_tlbsx_hit <= lrat_mas_tlbsx_hit_q; +lrat_mas_tlbsx_miss <= lrat_mas_tlbsx_miss_q; +lrat_mas_thdid <= lrat_mas_thdid_q; +lrat_mmucr3_x <= lrat_mmucr3_x_q; +lrat_dbg_tag1_addr_enable <= addr_enable; +lrat_dbg_tag2_matchline_q <= lrat_tag2_matchline_q; +lrat_dbg_entry0_addr_match <= lrat_entry0_addr_match; +lrat_dbg_entry0_lpid_match <= lrat_entry0_lpid_match; +lrat_dbg_entry0_entry_v <= lrat_entry0_valid_q; +lrat_dbg_entry0_entry_x <= lrat_entry0_xbit_q; +lrat_dbg_entry0_size <= lrat_entry0_size_q; +lrat_dbg_entry1_addr_match <= lrat_entry1_addr_match; +lrat_dbg_entry1_lpid_match <= lrat_entry1_lpid_match; +lrat_dbg_entry1_entry_v <= lrat_entry1_valid_q; +lrat_dbg_entry1_entry_x <= lrat_entry1_xbit_q; +lrat_dbg_entry1_size <= lrat_entry1_size_q; +lrat_dbg_entry2_addr_match <= lrat_entry2_addr_match; +lrat_dbg_entry2_lpid_match <= lrat_entry2_lpid_match; +lrat_dbg_entry2_entry_v <= lrat_entry2_valid_q; +lrat_dbg_entry2_entry_x <= lrat_entry2_xbit_q; +lrat_dbg_entry2_size <= lrat_entry2_size_q; +lrat_dbg_entry3_addr_match <= lrat_entry3_addr_match; +lrat_dbg_entry3_lpid_match <= lrat_entry3_lpid_match; +lrat_dbg_entry3_entry_v <= lrat_entry3_valid_q; +lrat_dbg_entry3_entry_x <= lrat_entry3_xbit_q; +lrat_dbg_entry3_size <= lrat_entry3_size_q; +lrat_dbg_entry4_addr_match <= lrat_entry4_addr_match; +lrat_dbg_entry4_lpid_match <= lrat_entry4_lpid_match; +lrat_dbg_entry4_entry_v <= lrat_entry4_valid_q; +lrat_dbg_entry4_entry_x <= lrat_entry4_xbit_q; +lrat_dbg_entry4_size <= lrat_entry4_size_q; +lrat_dbg_entry5_addr_match <= lrat_entry5_addr_match; +lrat_dbg_entry5_lpid_match <= lrat_entry5_lpid_match; +lrat_dbg_entry5_entry_v <= lrat_entry5_valid_q; +lrat_dbg_entry5_entry_x <= lrat_entry5_xbit_q; +lrat_dbg_entry5_size <= lrat_entry5_size_q; +lrat_dbg_entry6_addr_match <= lrat_entry6_addr_match; +lrat_dbg_entry6_lpid_match <= lrat_entry6_lpid_match; +lrat_dbg_entry6_entry_v <= lrat_entry6_valid_q; +lrat_dbg_entry6_entry_x <= lrat_entry6_xbit_q; +lrat_dbg_entry6_size <= lrat_entry6_size_q; +lrat_dbg_entry7_addr_match <= lrat_entry7_addr_match; +lrat_dbg_entry7_lpid_match <= lrat_entry7_lpid_match; +lrat_dbg_entry7_entry_v <= lrat_entry7_valid_q; +lrat_dbg_entry7_entry_x <= lrat_entry7_xbit_q; +lrat_dbg_entry7_size <= lrat_entry7_size_q; +unused_dc(0) <= or_reduce(LCB_DELAY_LCLKR_DC(1 TO 4)); +unused_dc(1) <= or_reduce(LCB_MPW1_DC_B(1 TO 4)); +unused_dc(2) <= PC_FUNC_SL_FORCE; +unused_dc(3) <= PC_FUNC_SL_THOLD_0_B; +unused_dc(4) <= TC_SCAN_DIS_DC_B; +unused_dc(5) <= TC_SCAN_DIAG_DC; +unused_dc(6) <= TC_LBIST_EN_DC; +unused_dc(7) <= or_reduce(TLB_TAG0_TYPE(0 TO 1) & TLB_TAG0_TYPE(3 TO 5)); +unused_dc(8) <= EX6_TTYPE_Q(0); +unused_dc(9) <= or_reduce(MAS2_0_EPN(44 TO 51)); +unused_dc(10) <= or_reduce(MAS2_1_EPN(44 TO 51)); +unused_dc(11) <= or_reduce(MAS2_2_EPN(44 TO 51)); +unused_dc(12) <= or_reduce(MAS2_3_EPN(44 TO 51)); +unused_dc(13) <= ex6_illeg_instr(0); +ex4_valid_latch: tri_rlmreg_p + generic map (width => ex4_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex4_valid_offset to ex4_valid_offset+ex4_valid_q'length-1), + scout => sov(ex4_valid_offset to ex4_valid_offset+ex4_valid_q'length-1), + din => ex4_valid_d, + dout => ex4_valid_q ); +ex4_ttype_latch: tri_rlmreg_p + generic map (width => ex4_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex4_ttype_offset to ex4_ttype_offset+ex4_ttype_q'length-1), + scout => sov(ex4_ttype_offset to ex4_ttype_offset+ex4_ttype_q'length-1), + din => ex4_ttype_d, + dout => ex4_ttype_q ); +ex5_valid_latch: tri_rlmreg_p + generic map (width => ex5_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex5_valid_offset to ex5_valid_offset+ex5_valid_q'length-1), + scout => sov(ex5_valid_offset to ex5_valid_offset+ex5_valid_q'length-1), + din => ex5_valid_d, + dout => ex5_valid_q ); +ex5_ttype_latch: tri_rlmreg_p + generic map (width => ex5_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex5_ttype_offset to ex5_ttype_offset+ex5_ttype_q'length-1), + scout => sov(ex5_ttype_offset to ex5_ttype_offset+ex5_ttype_q'length-1), + din => ex5_ttype_d, + dout => ex5_ttype_q ); +ex6_valid_latch: tri_rlmreg_p + generic map (width => ex6_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex6_valid_offset to ex6_valid_offset+ex6_valid_q'length-1), + scout => sov(ex6_valid_offset to ex6_valid_offset+ex6_valid_q'length-1), + din => ex6_valid_d, + dout => ex6_valid_q ); +ex6_ttype_latch: tri_rlmreg_p + generic map (width => ex6_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex6_ttype_offset to ex6_ttype_offset+ex6_ttype_q'length-1), + scout => sov(ex6_ttype_offset to ex6_ttype_offset+ex6_ttype_q'length-1), + din => ex6_ttype_d, + dout => ex6_ttype_q ); +ex5_esel_latch: tri_rlmreg_p + generic map (width => ex5_esel_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex5_esel_offset to ex5_esel_offset+ex5_esel_q'length-1), + scout => sov(ex5_esel_offset to ex5_esel_offset+ex5_esel_q'length-1), + din => ex5_esel_d, + dout => ex5_esel_q ); +ex5_atsel_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex5_atsel_offset), + scout => sov(ex5_atsel_offset), + din => ex5_atsel_d, + dout => ex5_atsel_q); +ex5_hes_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex5_hes_offset), + scout => sov(ex5_hes_offset), + din => ex5_hes_d, + dout => ex5_hes_q); +ex5_wq_latch: tri_rlmreg_p + generic map (width => ex5_wq_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex5_wq_offset to ex5_wq_offset+ex5_wq_q'length-1), + scout => sov(ex5_wq_offset to ex5_wq_offset+ex5_wq_q'length-1), + din => ex5_wq_d, + dout => ex5_wq_q ); +ex6_esel_latch: tri_rlmreg_p + generic map (width => ex6_esel_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex6_esel_offset to ex6_esel_offset+ex6_esel_q'length-1), + scout => sov(ex6_esel_offset to ex6_esel_offset+ex6_esel_q'length-1), + din => ex6_esel_d, + dout => ex6_esel_q ); +ex6_atsel_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex6_atsel_offset), + scout => sov(ex6_atsel_offset), + din => ex6_atsel_d, + dout => ex6_atsel_q); +ex6_hes_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex6_hes_offset), + scout => sov(ex6_hes_offset), + din => ex6_hes_d, + dout => ex6_hes_q); +ex6_wq_latch: tri_rlmreg_p + generic map (width => ex6_wq_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex6_wq_offset to ex6_wq_offset+ex6_wq_q'length-1), + scout => sov(ex6_wq_offset to ex6_wq_offset+ex6_wq_q'length-1), + din => ex6_wq_d, + dout => ex6_wq_q ); +lrat_tag1_lpn_latch: tri_rlmreg_p + generic map (width => lrat_tag1_lpn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(20+0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_tag1_lpn_offset to lrat_tag1_lpn_offset+lrat_tag1_lpn_q'length-1), + scout => sov(lrat_tag1_lpn_offset to lrat_tag1_lpn_offset+lrat_tag1_lpn_q'length-1), + din => lrat_tag1_lpn_d(64-real_addr_width to 51), + dout => lrat_tag1_lpn_q(64-real_addr_width to 51) ); +lrat_tag2_lpn_latch: tri_rlmreg_p + generic map (width => lrat_tag2_lpn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(20+1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_tag2_lpn_offset to lrat_tag2_lpn_offset+lrat_tag2_lpn_q'length-1), + scout => sov(lrat_tag2_lpn_offset to lrat_tag2_lpn_offset+lrat_tag2_lpn_q'length-1), + din => lrat_tag2_lpn_d(64-real_addr_width to 51), + dout => lrat_tag2_lpn_q(64-real_addr_width to 51) ); +lrat_tag3_lpn_latch: tri_rlmreg_p + generic map (width => lrat_tag3_lpn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(20+2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_tag3_lpn_offset to lrat_tag3_lpn_offset+lrat_tag3_lpn_q'length-1), + scout => sov(lrat_tag3_lpn_offset to lrat_tag3_lpn_offset+lrat_tag3_lpn_q'length-1), + din => lrat_tag3_lpn_d(64-real_addr_width to 51), + dout => lrat_tag3_lpn_q(64-real_addr_width to 51) ); +lrat_tag4_lpn_latch: tri_rlmreg_p + generic map (width => lrat_tag4_lpn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(20+3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_tag4_lpn_offset to lrat_tag4_lpn_offset+lrat_tag4_lpn_q'length-1), + scout => sov(lrat_tag4_lpn_offset to lrat_tag4_lpn_offset+lrat_tag4_lpn_q'length-1), + din => lrat_tag4_lpn_d(64-real_addr_width to 51), + dout => lrat_tag4_lpn_q(64-real_addr_width to 51) ); +lrat_tag3_rpn_latch: tri_rlmreg_p + generic map (width => lrat_tag3_rpn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(20+2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_tag3_rpn_offset to lrat_tag3_rpn_offset+lrat_tag3_rpn_q'length-1), + scout => sov(lrat_tag3_rpn_offset to lrat_tag3_rpn_offset+lrat_tag3_rpn_q'length-1), + din => lrat_tag3_rpn_d(64-real_addr_width to 51), + dout => lrat_tag3_rpn_q(64-real_addr_width to 51) ); +lrat_tag4_rpn_latch: tri_rlmreg_p + generic map (width => lrat_tag4_rpn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(20+3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_tag4_rpn_offset to lrat_tag4_rpn_offset+lrat_tag4_rpn_q'length-1), + scout => sov(lrat_tag4_rpn_offset to lrat_tag4_rpn_offset+lrat_tag4_rpn_q'length-1), + din => lrat_tag4_rpn_d(64-real_addr_width to 51), + dout => lrat_tag4_rpn_q(64-real_addr_width to 51) ); +lrat_tag3_hit_status_latch: tri_rlmreg_p + generic map (width => lrat_tag3_hit_status_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(20+2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_tag3_hit_status_offset to lrat_tag3_hit_status_offset+lrat_tag3_hit_status_q'length-1), + scout => sov(lrat_tag3_hit_status_offset to lrat_tag3_hit_status_offset+lrat_tag3_hit_status_q'length-1), + din => lrat_tag3_hit_status_d, + dout => lrat_tag3_hit_status_q ); +lrat_tag3_hit_entry_latch: tri_rlmreg_p + generic map (width => lrat_tag3_hit_entry_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(20+2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_tag3_hit_entry_offset to lrat_tag3_hit_entry_offset+lrat_tag3_hit_entry_q'length-1), + scout => sov(lrat_tag3_hit_entry_offset to lrat_tag3_hit_entry_offset+lrat_tag3_hit_entry_q'length-1), + din => lrat_tag3_hit_entry_d, + dout => lrat_tag3_hit_entry_q ); +lrat_tag4_hit_status_latch: tri_rlmreg_p + generic map (width => lrat_tag4_hit_status_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(20+3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_tag4_hit_status_offset to lrat_tag4_hit_status_offset+lrat_tag4_hit_status_q'length-1), + scout => sov(lrat_tag4_hit_status_offset to lrat_tag4_hit_status_offset+lrat_tag4_hit_status_q'length-1), + din => lrat_tag4_hit_status_d, + dout => lrat_tag4_hit_status_q ); +lrat_tag4_hit_entry_latch: tri_rlmreg_p + generic map (width => lrat_tag4_hit_entry_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(20+3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_tag4_hit_entry_offset to lrat_tag4_hit_entry_offset+lrat_tag4_hit_entry_q'length-1), + scout => sov(lrat_tag4_hit_entry_offset to lrat_tag4_hit_entry_offset+lrat_tag4_hit_entry_q'length-1), + din => lrat_tag4_hit_entry_d, + dout => lrat_tag4_hit_entry_q ); +lrat_tag1_lpid_latch: tri_rlmreg_p + generic map (width => lrat_tag1_lpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(20), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_tag1_lpid_offset to lrat_tag1_lpid_offset+lrat_tag1_lpid_q'length-1), + scout => sov(lrat_tag1_lpid_offset to lrat_tag1_lpid_offset+lrat_tag1_lpid_q'length-1), + din => lrat_tag1_lpid_d, + dout => lrat_tag1_lpid_q ); +lrat_tag1_size_latch: tri_rlmreg_p + generic map (width => lrat_tag1_size_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(20), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_tag1_size_offset to lrat_tag1_size_offset+lrat_tag1_size_q'length-1), + scout => sov(lrat_tag1_size_offset to lrat_tag1_size_offset+lrat_tag1_size_q'length-1), + din => lrat_tag1_size_d, + dout => lrat_tag1_size_q ); +lrat_tag2_size_latch: tri_rlmreg_p + generic map (width => lrat_tag2_size_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(21), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_tag2_size_offset to lrat_tag2_size_offset+lrat_tag2_size_q'length-1), + scout => sov(lrat_tag2_size_offset to lrat_tag2_size_offset+lrat_tag2_size_q'length-1), + din => lrat_tag2_size_d, + dout => lrat_tag2_size_q ); +lrat_tag2_entry_size_latch: tri_rlmreg_p + generic map (width => lrat_tag2_entry_size_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(21), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_tag2_entry_size_offset to lrat_tag2_entry_size_offset+lrat_tag2_entry_size_q'length-1), + scout => sov(lrat_tag2_entry_size_offset to lrat_tag2_entry_size_offset+lrat_tag2_entry_size_q'length-1), + din => lrat_tag2_entry_size_d, + dout => lrat_tag2_entry_size_q ); +lrat_tag2_matchline_latch: tri_rlmreg_p + generic map (width => lrat_tag2_matchline_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(21), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_tag2_matchline_offset to lrat_tag2_matchline_offset+lrat_tag2_matchline_q'length-1), + scout => sov(lrat_tag2_matchline_offset to lrat_tag2_matchline_offset+lrat_tag2_matchline_q'length-1), + din => lrat_tag2_matchline_d, + dout => lrat_tag2_matchline_q ); +tlb_addr_cap_latch: tri_rlmreg_p + generic map (width => tlb_addr_cap_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(20), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_addr_cap_offset to tlb_addr_cap_offset+tlb_addr_cap_q'length-1), + scout => sov(tlb_addr_cap_offset to tlb_addr_cap_offset+tlb_addr_cap_q'length-1), + din => tlb_addr_cap_d, + dout => tlb_addr_cap_q ); +spare_latch: tri_rlmreg_p + generic map (width => spare_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(spare_offset to spare_offset+spare_q'length-1), + scout => sov(spare_offset to spare_offset+spare_q'length-1), + din => spare_q, + dout => spare_q ); +lrat_entry_act_latch: tri_rlmreg_p + generic map (width => lrat_entry_act_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry_act_offset to lrat_entry_act_offset+lrat_entry_act_q'length-1), + scout => sov(lrat_entry_act_offset to lrat_entry_act_offset+lrat_entry_act_q'length-1), + din => lrat_entry_act_d, + dout => lrat_entry_act_q ); +lrat_mas_act_latch: tri_rlmreg_p + generic map (width => lrat_mas_act_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_mas_act_offset to lrat_mas_act_offset+lrat_mas_act_q'length-1), + scout => sov(lrat_mas_act_offset to lrat_mas_act_offset+lrat_mas_act_q'length-1), + din => lrat_mas_act_d, + dout => lrat_mas_act_q ); +lrat_datain_act_latch: tri_rlmreg_p + generic map (width => lrat_datain_act_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_datain_act_offset to lrat_datain_act_offset+lrat_datain_act_q'length-1), + scout => sov(lrat_datain_act_offset to lrat_datain_act_offset+lrat_datain_act_q'length-1), + din => lrat_datain_act_d, + dout => lrat_datain_act_q ); +lrat_entry0_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry0_valid_offset), + scout => sov(lrat_entry0_valid_offset), + din => lrat_entry0_valid_d, + dout => lrat_entry0_valid_q); +lrat_entry0_xbit_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry0_xbit_offset), + scout => sov(lrat_entry0_xbit_offset), + din => lrat_entry0_xbit_d, + dout => lrat_entry0_xbit_q); +lrat_entry0_lpn_latch: tri_rlmreg_p + generic map (width => lrat_entry0_lpn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry0_lpn_offset to lrat_entry0_lpn_offset+lrat_entry0_lpn_q'length-1), + scout => sov(lrat_entry0_lpn_offset to lrat_entry0_lpn_offset+lrat_entry0_lpn_q'length-1), + din => lrat_entry0_lpn_d, + dout => lrat_entry0_lpn_q ); +lrat_entry0_rpn_latch: tri_rlmreg_p + generic map (width => lrat_entry0_rpn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry0_rpn_offset to lrat_entry0_rpn_offset+lrat_entry0_rpn_q'length-1), + scout => sov(lrat_entry0_rpn_offset to lrat_entry0_rpn_offset+lrat_entry0_rpn_q'length-1), + din => lrat_entry0_rpn_d, + dout => lrat_entry0_rpn_q ); +lrat_entry0_lpid_latch: tri_rlmreg_p + generic map (width => lrat_entry0_lpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry0_lpid_offset to lrat_entry0_lpid_offset+lrat_entry0_lpid_q'length-1), + scout => sov(lrat_entry0_lpid_offset to lrat_entry0_lpid_offset+lrat_entry0_lpid_q'length-1), + din => lrat_entry0_lpid_d, + dout => lrat_entry0_lpid_q ); +lrat_entry0_size_latch: tri_rlmreg_p + generic map (width => lrat_entry0_size_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry0_size_offset to lrat_entry0_size_offset+lrat_entry0_size_q'length-1), + scout => sov(lrat_entry0_size_offset to lrat_entry0_size_offset+lrat_entry0_size_q'length-1), + din => lrat_entry0_size_d, + dout => lrat_entry0_size_q ); +lrat_entry0_cmpmask_latch: tri_rlmreg_p + generic map (width => lrat_entry0_cmpmask_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry0_cmpmask_offset to lrat_entry0_cmpmask_offset+lrat_entry0_cmpmask_q'length-1), + scout => sov(lrat_entry0_cmpmask_offset to lrat_entry0_cmpmask_offset+lrat_entry0_cmpmask_q'length-1), + din => lrat_entry0_cmpmask_d, + dout => lrat_entry0_cmpmask_q ); +lrat_entry0_xbitmask_latch: tri_rlmreg_p + generic map (width => lrat_entry0_xbitmask_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry0_xbitmask_offset to lrat_entry0_xbitmask_offset+lrat_entry0_xbitmask_q'length-1), + scout => sov(lrat_entry0_xbitmask_offset to lrat_entry0_xbitmask_offset+lrat_entry0_xbitmask_q'length-1), + din => lrat_entry0_xbitmask_d, + dout => lrat_entry0_xbitmask_q ); +lrat_entry1_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry1_valid_offset), + scout => sov(lrat_entry1_valid_offset), + din => lrat_entry1_valid_d, + dout => lrat_entry1_valid_q); +lrat_entry1_xbit_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry1_xbit_offset), + scout => sov(lrat_entry1_xbit_offset), + din => lrat_entry1_xbit_d, + dout => lrat_entry1_xbit_q); +lrat_entry1_lpn_latch: tri_rlmreg_p + generic map (width => lrat_entry1_lpn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry1_lpn_offset to lrat_entry1_lpn_offset+lrat_entry1_lpn_q'length-1), + scout => sov(lrat_entry1_lpn_offset to lrat_entry1_lpn_offset+lrat_entry1_lpn_q'length-1), + din => lrat_entry1_lpn_d, + dout => lrat_entry1_lpn_q ); +lrat_entry1_rpn_latch: tri_rlmreg_p + generic map (width => lrat_entry1_rpn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry1_rpn_offset to lrat_entry1_rpn_offset+lrat_entry1_rpn_q'length-1), + scout => sov(lrat_entry1_rpn_offset to lrat_entry1_rpn_offset+lrat_entry1_rpn_q'length-1), + din => lrat_entry1_rpn_d, + dout => lrat_entry1_rpn_q ); +lrat_entry1_lpid_latch: tri_rlmreg_p + generic map (width => lrat_entry1_lpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry1_lpid_offset to lrat_entry1_lpid_offset+lrat_entry1_lpid_q'length-1), + scout => sov(lrat_entry1_lpid_offset to lrat_entry1_lpid_offset+lrat_entry1_lpid_q'length-1), + din => lrat_entry1_lpid_d, + dout => lrat_entry1_lpid_q ); +lrat_entry1_size_latch: tri_rlmreg_p + generic map (width => lrat_entry1_size_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry1_size_offset to lrat_entry1_size_offset+lrat_entry1_size_q'length-1), + scout => sov(lrat_entry1_size_offset to lrat_entry1_size_offset+lrat_entry1_size_q'length-1), + din => lrat_entry1_size_d, + dout => lrat_entry1_size_q ); +lrat_entry1_cmpmask_latch: tri_rlmreg_p + generic map (width => lrat_entry1_cmpmask_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry1_cmpmask_offset to lrat_entry1_cmpmask_offset+lrat_entry1_cmpmask_q'length-1), + scout => sov(lrat_entry1_cmpmask_offset to lrat_entry1_cmpmask_offset+lrat_entry1_cmpmask_q'length-1), + din => lrat_entry1_cmpmask_d, + dout => lrat_entry1_cmpmask_q ); +lrat_entry1_xbitmask_latch: tri_rlmreg_p + generic map (width => lrat_entry1_xbitmask_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry1_xbitmask_offset to lrat_entry1_xbitmask_offset+lrat_entry1_xbitmask_q'length-1), + scout => sov(lrat_entry1_xbitmask_offset to lrat_entry1_xbitmask_offset+lrat_entry1_xbitmask_q'length-1), + din => lrat_entry1_xbitmask_d, + dout => lrat_entry1_xbitmask_q ); +lrat_entry2_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry2_valid_offset), + scout => sov(lrat_entry2_valid_offset), + din => lrat_entry2_valid_d, + dout => lrat_entry2_valid_q); +lrat_entry2_xbit_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry2_xbit_offset), + scout => sov(lrat_entry2_xbit_offset), + din => lrat_entry2_xbit_d, + dout => lrat_entry2_xbit_q); +lrat_entry2_lpn_latch: tri_rlmreg_p + generic map (width => lrat_entry2_lpn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry2_lpn_offset to lrat_entry2_lpn_offset+lrat_entry2_lpn_q'length-1), + scout => sov(lrat_entry2_lpn_offset to lrat_entry2_lpn_offset+lrat_entry2_lpn_q'length-1), + din => lrat_entry2_lpn_d, + dout => lrat_entry2_lpn_q ); +lrat_entry2_rpn_latch: tri_rlmreg_p + generic map (width => lrat_entry2_rpn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry2_rpn_offset to lrat_entry2_rpn_offset+lrat_entry2_rpn_q'length-1), + scout => sov(lrat_entry2_rpn_offset to lrat_entry2_rpn_offset+lrat_entry2_rpn_q'length-1), + din => lrat_entry2_rpn_d, + dout => lrat_entry2_rpn_q ); +lrat_entry2_lpid_latch: tri_rlmreg_p + generic map (width => lrat_entry2_lpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry2_lpid_offset to lrat_entry2_lpid_offset+lrat_entry2_lpid_q'length-1), + scout => sov(lrat_entry2_lpid_offset to lrat_entry2_lpid_offset+lrat_entry2_lpid_q'length-1), + din => lrat_entry2_lpid_d, + dout => lrat_entry2_lpid_q ); +lrat_entry2_size_latch: tri_rlmreg_p + generic map (width => lrat_entry2_size_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry2_size_offset to lrat_entry2_size_offset+lrat_entry2_size_q'length-1), + scout => sov(lrat_entry2_size_offset to lrat_entry2_size_offset+lrat_entry2_size_q'length-1), + din => lrat_entry2_size_d, + dout => lrat_entry2_size_q ); +lrat_entry2_cmpmask_latch: tri_rlmreg_p + generic map (width => lrat_entry2_cmpmask_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry2_cmpmask_offset to lrat_entry2_cmpmask_offset+lrat_entry2_cmpmask_q'length-1), + scout => sov(lrat_entry2_cmpmask_offset to lrat_entry2_cmpmask_offset+lrat_entry2_cmpmask_q'length-1), + din => lrat_entry2_cmpmask_d, + dout => lrat_entry2_cmpmask_q ); +lrat_entry2_xbitmask_latch: tri_rlmreg_p + generic map (width => lrat_entry2_xbitmask_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry2_xbitmask_offset to lrat_entry2_xbitmask_offset+lrat_entry2_xbitmask_q'length-1), + scout => sov(lrat_entry2_xbitmask_offset to lrat_entry2_xbitmask_offset+lrat_entry2_xbitmask_q'length-1), + din => lrat_entry2_xbitmask_d, + dout => lrat_entry2_xbitmask_q ); +lrat_entry3_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry3_valid_offset), + scout => sov(lrat_entry3_valid_offset), + din => lrat_entry3_valid_d, + dout => lrat_entry3_valid_q); +lrat_entry3_xbit_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry3_xbit_offset), + scout => sov(lrat_entry3_xbit_offset), + din => lrat_entry3_xbit_d, + dout => lrat_entry3_xbit_q); +lrat_entry3_lpn_latch: tri_rlmreg_p + generic map (width => lrat_entry3_lpn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry3_lpn_offset to lrat_entry3_lpn_offset+lrat_entry3_lpn_q'length-1), + scout => sov(lrat_entry3_lpn_offset to lrat_entry3_lpn_offset+lrat_entry3_lpn_q'length-1), + din => lrat_entry3_lpn_d, + dout => lrat_entry3_lpn_q ); +lrat_entry3_rpn_latch: tri_rlmreg_p + generic map (width => lrat_entry3_rpn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry3_rpn_offset to lrat_entry3_rpn_offset+lrat_entry3_rpn_q'length-1), + scout => sov(lrat_entry3_rpn_offset to lrat_entry3_rpn_offset+lrat_entry3_rpn_q'length-1), + din => lrat_entry3_rpn_d, + dout => lrat_entry3_rpn_q ); +lrat_entry3_lpid_latch: tri_rlmreg_p + generic map (width => lrat_entry3_lpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry3_lpid_offset to lrat_entry3_lpid_offset+lrat_entry3_lpid_q'length-1), + scout => sov(lrat_entry3_lpid_offset to lrat_entry3_lpid_offset+lrat_entry3_lpid_q'length-1), + din => lrat_entry3_lpid_d, + dout => lrat_entry3_lpid_q ); +lrat_entry3_size_latch: tri_rlmreg_p + generic map (width => lrat_entry3_size_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry3_size_offset to lrat_entry3_size_offset+lrat_entry3_size_q'length-1), + scout => sov(lrat_entry3_size_offset to lrat_entry3_size_offset+lrat_entry3_size_q'length-1), + din => lrat_entry3_size_d, + dout => lrat_entry3_size_q ); +lrat_entry3_cmpmask_latch: tri_rlmreg_p + generic map (width => lrat_entry3_cmpmask_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry3_cmpmask_offset to lrat_entry3_cmpmask_offset+lrat_entry3_cmpmask_q'length-1), + scout => sov(lrat_entry3_cmpmask_offset to lrat_entry3_cmpmask_offset+lrat_entry3_cmpmask_q'length-1), + din => lrat_entry3_cmpmask_d, + dout => lrat_entry3_cmpmask_q ); +lrat_entry3_xbitmask_latch: tri_rlmreg_p + generic map (width => lrat_entry3_xbitmask_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry3_xbitmask_offset to lrat_entry3_xbitmask_offset+lrat_entry3_xbitmask_q'length-1), + scout => sov(lrat_entry3_xbitmask_offset to lrat_entry3_xbitmask_offset+lrat_entry3_xbitmask_q'length-1), + din => lrat_entry3_xbitmask_d, + dout => lrat_entry3_xbitmask_q ); +lrat_entry4_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(4), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry4_valid_offset), + scout => sov(lrat_entry4_valid_offset), + din => lrat_entry4_valid_d, + dout => lrat_entry4_valid_q); +lrat_entry4_xbit_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(4), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry4_xbit_offset), + scout => sov(lrat_entry4_xbit_offset), + din => lrat_entry4_xbit_d, + dout => lrat_entry4_xbit_q); +lrat_entry4_lpn_latch: tri_rlmreg_p + generic map (width => lrat_entry4_lpn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(4), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry4_lpn_offset to lrat_entry4_lpn_offset+lrat_entry4_lpn_q'length-1), + scout => sov(lrat_entry4_lpn_offset to lrat_entry4_lpn_offset+lrat_entry4_lpn_q'length-1), + din => lrat_entry4_lpn_d, + dout => lrat_entry4_lpn_q ); +lrat_entry4_rpn_latch: tri_rlmreg_p + generic map (width => lrat_entry4_rpn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(4), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry4_rpn_offset to lrat_entry4_rpn_offset+lrat_entry4_rpn_q'length-1), + scout => sov(lrat_entry4_rpn_offset to lrat_entry4_rpn_offset+lrat_entry4_rpn_q'length-1), + din => lrat_entry4_rpn_d, + dout => lrat_entry4_rpn_q ); +lrat_entry4_lpid_latch: tri_rlmreg_p + generic map (width => lrat_entry4_lpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(4), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry4_lpid_offset to lrat_entry4_lpid_offset+lrat_entry4_lpid_q'length-1), + scout => sov(lrat_entry4_lpid_offset to lrat_entry4_lpid_offset+lrat_entry4_lpid_q'length-1), + din => lrat_entry4_lpid_d, + dout => lrat_entry4_lpid_q ); +lrat_entry4_size_latch: tri_rlmreg_p + generic map (width => lrat_entry4_size_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(4), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry4_size_offset to lrat_entry4_size_offset+lrat_entry4_size_q'length-1), + scout => sov(lrat_entry4_size_offset to lrat_entry4_size_offset+lrat_entry4_size_q'length-1), + din => lrat_entry4_size_d, + dout => lrat_entry4_size_q ); +lrat_entry4_cmpmask_latch: tri_rlmreg_p + generic map (width => lrat_entry4_cmpmask_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(4), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry4_cmpmask_offset to lrat_entry4_cmpmask_offset+lrat_entry4_cmpmask_q'length-1), + scout => sov(lrat_entry4_cmpmask_offset to lrat_entry4_cmpmask_offset+lrat_entry4_cmpmask_q'length-1), + din => lrat_entry4_cmpmask_d, + dout => lrat_entry4_cmpmask_q ); +lrat_entry4_xbitmask_latch: tri_rlmreg_p + generic map (width => lrat_entry4_xbitmask_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(4), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry4_xbitmask_offset to lrat_entry4_xbitmask_offset+lrat_entry4_xbitmask_q'length-1), + scout => sov(lrat_entry4_xbitmask_offset to lrat_entry4_xbitmask_offset+lrat_entry4_xbitmask_q'length-1), + din => lrat_entry4_xbitmask_d, + dout => lrat_entry4_xbitmask_q ); +lrat_entry5_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(5), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry5_valid_offset), + scout => sov(lrat_entry5_valid_offset), + din => lrat_entry5_valid_d, + dout => lrat_entry5_valid_q); +lrat_entry5_xbit_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(5), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry5_xbit_offset), + scout => sov(lrat_entry5_xbit_offset), + din => lrat_entry5_xbit_d, + dout => lrat_entry5_xbit_q); +lrat_entry5_lpn_latch: tri_rlmreg_p + generic map (width => lrat_entry5_lpn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(5), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry5_lpn_offset to lrat_entry5_lpn_offset+lrat_entry5_lpn_q'length-1), + scout => sov(lrat_entry5_lpn_offset to lrat_entry5_lpn_offset+lrat_entry5_lpn_q'length-1), + din => lrat_entry5_lpn_d, + dout => lrat_entry5_lpn_q ); +lrat_entry5_rpn_latch: tri_rlmreg_p + generic map (width => lrat_entry5_rpn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(5), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry5_rpn_offset to lrat_entry5_rpn_offset+lrat_entry5_rpn_q'length-1), + scout => sov(lrat_entry5_rpn_offset to lrat_entry5_rpn_offset+lrat_entry5_rpn_q'length-1), + din => lrat_entry5_rpn_d, + dout => lrat_entry5_rpn_q ); +lrat_entry5_lpid_latch: tri_rlmreg_p + generic map (width => lrat_entry5_lpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(5), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry5_lpid_offset to lrat_entry5_lpid_offset+lrat_entry5_lpid_q'length-1), + scout => sov(lrat_entry5_lpid_offset to lrat_entry5_lpid_offset+lrat_entry5_lpid_q'length-1), + din => lrat_entry5_lpid_d, + dout => lrat_entry5_lpid_q ); +lrat_entry5_size_latch: tri_rlmreg_p + generic map (width => lrat_entry5_size_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(5), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry5_size_offset to lrat_entry5_size_offset+lrat_entry5_size_q'length-1), + scout => sov(lrat_entry5_size_offset to lrat_entry5_size_offset+lrat_entry5_size_q'length-1), + din => lrat_entry5_size_d, + dout => lrat_entry5_size_q ); +lrat_entry5_cmpmask_latch: tri_rlmreg_p + generic map (width => lrat_entry5_cmpmask_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(5), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry5_cmpmask_offset to lrat_entry5_cmpmask_offset+lrat_entry5_cmpmask_q'length-1), + scout => sov(lrat_entry5_cmpmask_offset to lrat_entry5_cmpmask_offset+lrat_entry5_cmpmask_q'length-1), + din => lrat_entry5_cmpmask_d, + dout => lrat_entry5_cmpmask_q ); +lrat_entry5_xbitmask_latch: tri_rlmreg_p + generic map (width => lrat_entry5_xbitmask_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(5), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry5_xbitmask_offset to lrat_entry5_xbitmask_offset+lrat_entry5_xbitmask_q'length-1), + scout => sov(lrat_entry5_xbitmask_offset to lrat_entry5_xbitmask_offset+lrat_entry5_xbitmask_q'length-1), + din => lrat_entry5_xbitmask_d, + dout => lrat_entry5_xbitmask_q ); +lrat_entry6_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(6), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry6_valid_offset), + scout => sov(lrat_entry6_valid_offset), + din => lrat_entry6_valid_d, + dout => lrat_entry6_valid_q); +lrat_entry6_xbit_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(6), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry6_xbit_offset), + scout => sov(lrat_entry6_xbit_offset), + din => lrat_entry6_xbit_d, + dout => lrat_entry6_xbit_q); +lrat_entry6_lpn_latch: tri_rlmreg_p + generic map (width => lrat_entry6_lpn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(6), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry6_lpn_offset to lrat_entry6_lpn_offset+lrat_entry6_lpn_q'length-1), + scout => sov(lrat_entry6_lpn_offset to lrat_entry6_lpn_offset+lrat_entry6_lpn_q'length-1), + din => lrat_entry6_lpn_d, + dout => lrat_entry6_lpn_q ); +lrat_entry6_rpn_latch: tri_rlmreg_p + generic map (width => lrat_entry6_rpn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(6), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry6_rpn_offset to lrat_entry6_rpn_offset+lrat_entry6_rpn_q'length-1), + scout => sov(lrat_entry6_rpn_offset to lrat_entry6_rpn_offset+lrat_entry6_rpn_q'length-1), + din => lrat_entry6_rpn_d, + dout => lrat_entry6_rpn_q ); +lrat_entry6_lpid_latch: tri_rlmreg_p + generic map (width => lrat_entry6_lpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(6), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry6_lpid_offset to lrat_entry6_lpid_offset+lrat_entry6_lpid_q'length-1), + scout => sov(lrat_entry6_lpid_offset to lrat_entry6_lpid_offset+lrat_entry6_lpid_q'length-1), + din => lrat_entry6_lpid_d, + dout => lrat_entry6_lpid_q ); +lrat_entry6_size_latch: tri_rlmreg_p + generic map (width => lrat_entry6_size_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(6), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry6_size_offset to lrat_entry6_size_offset+lrat_entry6_size_q'length-1), + scout => sov(lrat_entry6_size_offset to lrat_entry6_size_offset+lrat_entry6_size_q'length-1), + din => lrat_entry6_size_d, + dout => lrat_entry6_size_q ); +lrat_entry6_cmpmask_latch: tri_rlmreg_p + generic map (width => lrat_entry6_cmpmask_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(6), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry6_cmpmask_offset to lrat_entry6_cmpmask_offset+lrat_entry6_cmpmask_q'length-1), + scout => sov(lrat_entry6_cmpmask_offset to lrat_entry6_cmpmask_offset+lrat_entry6_cmpmask_q'length-1), + din => lrat_entry6_cmpmask_d, + dout => lrat_entry6_cmpmask_q ); +lrat_entry6_xbitmask_latch: tri_rlmreg_p + generic map (width => lrat_entry6_xbitmask_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(6), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry6_xbitmask_offset to lrat_entry6_xbitmask_offset+lrat_entry6_xbitmask_q'length-1), + scout => sov(lrat_entry6_xbitmask_offset to lrat_entry6_xbitmask_offset+lrat_entry6_xbitmask_q'length-1), + din => lrat_entry6_xbitmask_d, + dout => lrat_entry6_xbitmask_q ); +lrat_entry7_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(7), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry7_valid_offset), + scout => sov(lrat_entry7_valid_offset), + din => lrat_entry7_valid_d, + dout => lrat_entry7_valid_q); +lrat_entry7_xbit_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(7), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry7_xbit_offset), + scout => sov(lrat_entry7_xbit_offset), + din => lrat_entry7_xbit_d, + dout => lrat_entry7_xbit_q); +lrat_entry7_lpn_latch: tri_rlmreg_p + generic map (width => lrat_entry7_lpn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(7), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry7_lpn_offset to lrat_entry7_lpn_offset+lrat_entry7_lpn_q'length-1), + scout => sov(lrat_entry7_lpn_offset to lrat_entry7_lpn_offset+lrat_entry7_lpn_q'length-1), + din => lrat_entry7_lpn_d, + dout => lrat_entry7_lpn_q ); +lrat_entry7_rpn_latch: tri_rlmreg_p + generic map (width => lrat_entry7_rpn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(7), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry7_rpn_offset to lrat_entry7_rpn_offset+lrat_entry7_rpn_q'length-1), + scout => sov(lrat_entry7_rpn_offset to lrat_entry7_rpn_offset+lrat_entry7_rpn_q'length-1), + din => lrat_entry7_rpn_d, + dout => lrat_entry7_rpn_q ); +lrat_entry7_lpid_latch: tri_rlmreg_p + generic map (width => lrat_entry7_lpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(7), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry7_lpid_offset to lrat_entry7_lpid_offset+lrat_entry7_lpid_q'length-1), + scout => sov(lrat_entry7_lpid_offset to lrat_entry7_lpid_offset+lrat_entry7_lpid_q'length-1), + din => lrat_entry7_lpid_d, + dout => lrat_entry7_lpid_q ); +lrat_entry7_size_latch: tri_rlmreg_p + generic map (width => lrat_entry7_size_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(7), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry7_size_offset to lrat_entry7_size_offset+lrat_entry7_size_q'length-1), + scout => sov(lrat_entry7_size_offset to lrat_entry7_size_offset+lrat_entry7_size_q'length-1), + din => lrat_entry7_size_d, + dout => lrat_entry7_size_q ); +lrat_entry7_cmpmask_latch: tri_rlmreg_p + generic map (width => lrat_entry7_cmpmask_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(7), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry7_cmpmask_offset to lrat_entry7_cmpmask_offset+lrat_entry7_cmpmask_q'length-1), + scout => sov(lrat_entry7_cmpmask_offset to lrat_entry7_cmpmask_offset+lrat_entry7_cmpmask_q'length-1), + din => lrat_entry7_cmpmask_d, + dout => lrat_entry7_cmpmask_q ); +lrat_entry7_xbitmask_latch: tri_rlmreg_p + generic map (width => lrat_entry7_xbitmask_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(7), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry7_xbitmask_offset to lrat_entry7_xbitmask_offset+lrat_entry7_xbitmask_q'length-1), + scout => sov(lrat_entry7_xbitmask_offset to lrat_entry7_xbitmask_offset+lrat_entry7_xbitmask_q'length-1), + din => lrat_entry7_xbitmask_d, + dout => lrat_entry7_xbitmask_q ); +lrat_datain_lpn_latch: tri_rlmreg_p + generic map (width => lrat_datain_lpn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_datain_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_datain_lpn_offset to lrat_datain_lpn_offset+lrat_datain_lpn_q'length-1), + scout => sov(lrat_datain_lpn_offset to lrat_datain_lpn_offset+lrat_datain_lpn_q'length-1), + din => lrat_datain_lpn_d, + dout => lrat_datain_lpn_q ); +lrat_datain_rpn_latch: tri_rlmreg_p + generic map (width => lrat_datain_rpn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_datain_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_datain_rpn_offset to lrat_datain_rpn_offset+lrat_datain_rpn_q'length-1), + scout => sov(lrat_datain_rpn_offset to lrat_datain_rpn_offset+lrat_datain_rpn_q'length-1), + din => lrat_datain_rpn_d, + dout => lrat_datain_rpn_q ); +lrat_datain_lpid_latch: tri_rlmreg_p + generic map (width => lrat_datain_lpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_datain_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_datain_lpid_offset to lrat_datain_lpid_offset+lrat_datain_lpid_q'length-1), + scout => sov(lrat_datain_lpid_offset to lrat_datain_lpid_offset+lrat_datain_lpid_q'length-1), + din => lrat_datain_lpid_d, + dout => lrat_datain_lpid_q ); +lrat_datain_size_latch: tri_rlmreg_p + generic map (width => lrat_datain_size_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_datain_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_datain_size_offset to lrat_datain_size_offset+lrat_datain_size_q'length-1), + scout => sov(lrat_datain_size_offset to lrat_datain_size_offset+lrat_datain_size_q'length-1), + din => lrat_datain_size_d, + dout => lrat_datain_size_q ); +lrat_datain_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_datain_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_datain_valid_offset), + scout => sov(lrat_datain_valid_offset), + din => lrat_datain_valid_d, + dout => lrat_datain_valid_q); +lrat_datain_xbit_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_datain_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_datain_xbit_offset), + scout => sov(lrat_datain_xbit_offset), + din => lrat_datain_xbit_d, + dout => lrat_datain_xbit_q); +lrat_mas1_v_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_mas_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_mas1_v_offset), + scout => sov(lrat_mas1_v_offset), + din => lrat_mas1_v_d, + dout => lrat_mas1_v_q); +lrat_mmucr3_x_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_mas_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_mmucr3_x_offset), + scout => sov(lrat_mmucr3_x_offset), + din => lrat_mmucr3_x_d, + dout => lrat_mmucr3_x_q); +lrat_mas1_tsize_latch: tri_rlmreg_p + generic map (width => lrat_mas1_tsize_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_mas_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_mas1_tsize_offset to lrat_mas1_tsize_offset+lrat_mas1_tsize_q'length-1), + scout => sov(lrat_mas1_tsize_offset to lrat_mas1_tsize_offset+lrat_mas1_tsize_q'length-1), + din => lrat_mas1_tsize_d, + dout => lrat_mas1_tsize_q ); +lrat_mas2_epn_latch: tri_rlmreg_p + generic map (width => lrat_mas2_epn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_mas_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_mas2_epn_offset to lrat_mas2_epn_offset+lrat_mas2_epn_q'length-1), + scout => sov(lrat_mas2_epn_offset to lrat_mas2_epn_offset+lrat_mas2_epn_q'length-1), + din => lrat_mas2_epn_d, + dout => lrat_mas2_epn_q ); +lrat_mas3_rpnl_latch: tri_rlmreg_p + generic map (width => lrat_mas3_rpnl_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_mas_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_mas3_rpnl_offset to lrat_mas3_rpnl_offset+lrat_mas3_rpnl_q'length-1), + scout => sov(lrat_mas3_rpnl_offset to lrat_mas3_rpnl_offset+lrat_mas3_rpnl_q'length-1), + din => lrat_mas3_rpnl_d, + dout => lrat_mas3_rpnl_q ); +lrat_mas7_rpnu_latch: tri_rlmreg_p + generic map (width => lrat_mas7_rpnu_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_mas_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_mas7_rpnu_offset to lrat_mas7_rpnu_offset+lrat_mas7_rpnu_q'length-1), + scout => sov(lrat_mas7_rpnu_offset to lrat_mas7_rpnu_offset+lrat_mas7_rpnu_q'length-1), + din => lrat_mas7_rpnu_d, + dout => lrat_mas7_rpnu_q ); +lrat_mas8_tlpid_latch: tri_rlmreg_p + generic map (width => lrat_mas8_tlpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_mas_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_mas8_tlpid_offset to lrat_mas8_tlpid_offset+lrat_mas8_tlpid_q'length-1), + scout => sov(lrat_mas8_tlpid_offset to lrat_mas8_tlpid_offset+lrat_mas8_tlpid_q'length-1), + din => lrat_mas8_tlpid_d, + dout => lrat_mas8_tlpid_q ); +lrat_mas_thdid_latch: tri_rlmreg_p + generic map (width => lrat_mas_thdid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_mas_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_mas_thdid_offset to lrat_mas_thdid_offset+lrat_mas_thdid_q'length-1), + scout => sov(lrat_mas_thdid_offset to lrat_mas_thdid_offset+lrat_mas_thdid_q'length-1), + din => lrat_mas_thdid_d, + dout => lrat_mas_thdid_q ); +lrat_mas_tlbre_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_mas_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_mas_tlbre_offset), + scout => sov(lrat_mas_tlbre_offset), + din => lrat_mas_tlbre_d, + dout => lrat_mas_tlbre_q ); +lrat_mas_tlbsx_hit_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_mas_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_mas_tlbsx_hit_offset), + scout => sov(lrat_mas_tlbsx_hit_offset), + din => lrat_mas_tlbsx_hit_d, + dout => lrat_mas_tlbsx_hit_q ); +lrat_mas_tlbsx_miss_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_mas_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_mas_tlbsx_miss_offset), + scout => sov(lrat_mas_tlbsx_miss_offset), + din => lrat_mas_tlbsx_miss_d, + dout => lrat_mas_tlbsx_miss_q ); +perv_2to1_reg: tri_plat + generic map (width => 3, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ccflush_dc, + din(0) => pc_func_sl_thold_2, + din(1) => pc_func_slp_sl_thold_2, + din(2) => pc_sg_2, + q(0) => pc_func_sl_thold_1, + q(1) => pc_func_slp_sl_thold_1, + q(2) => pc_sg_1); +perv_1to0_reg: tri_plat + generic map (width => 3, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ccflush_dc, + din(0) => pc_func_sl_thold_1, + din(1) => pc_func_slp_sl_thold_1, + din(2) => pc_sg_1, + q(0) => pc_func_sl_thold_0, + q(1) => pc_func_slp_sl_thold_0, + q(2) => pc_sg_0); +perv_lcbor_func_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b, + thold => pc_func_sl_thold_0, + sg => pc_sg_0, + act_dis => lcb_act_dis_dc, + forcee => pc_func_sl_force, + thold_b => pc_func_sl_thold_0_b); +perv_lcbor_func_slp_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b, + thold => pc_func_slp_sl_thold_0, + sg => pc_sg_0, + act_dis => lcb_act_dis_dc, + forcee => pc_func_slp_sl_force, + thold_b => pc_func_slp_sl_thold_0_b); +siv(0 TO scan_right) <= sov(1 to scan_right) & ac_func_scan_in; +ac_func_scan_out <= sov(0); +END MMQ_TLB_LRAT; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/mmq_tlb_lrat_matchline.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/mmq_tlb_lrat_matchline.vhdl new file mode 100644 index 0000000..e9a66c8 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/mmq_tlb_lrat_matchline.vhdl @@ -0,0 +1,332 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +LIBRARY IEEE; +USE ieee.std_logic_1164.ALL ; +LIBRARY IBM; +USE ibm.std_ulogic_support.ALL; +USE ibm.std_ulogic_function_support.ALL; +library support; +use support.power_logic_pkg.all; + + +entity mmq_tlb_lrat_matchline is + generic (real_addr_width : integer := 42; + lpid_width : integer := 8; + lrat_maxsize_log2 : integer := 40; + lrat_minsize_log2 : integer := 20; + have_xbit : integer := 1; + num_pgsizes : integer := 8; + have_cmpmask : integer := 1; + cmpmask_width : integer := 7); + +port( + vdd : inout power_logic; + gnd : inout power_logic; + addr_in : in std_ulogic_vector(64-real_addr_width to 64-lrat_minsize_log2-1); + addr_enable : in std_ulogic; + entry_size : in std_ulogic_vector(0 to 3); + entry_cmpmask : in std_ulogic_vector(0 to cmpmask_width-1); + entry_xbit : in std_ulogic; + entry_xbitmask : in std_ulogic_vector(0 to cmpmask_width-1); + entry_lpn : in std_ulogic_vector(64-real_addr_width to 64-lrat_minsize_log2-1); + entry_lpid : in std_ulogic_vector(0 to lpid_width-1); + comp_lpid : in std_ulogic_vector(0 to lpid_width-1); + lpid_enable : in std_ulogic; + entry_v : in std_ulogic; + + match : out std_ulogic; + + dbg_addr_match : out std_ulogic; + dbg_lpid_match : out std_ulogic + +); + + -- synopsys translate_off + -- synopsys translate_on + +end mmq_tlb_lrat_matchline; + +architecture mmq_tlb_lrat_matchline of mmq_tlb_lrat_matchline is + + + + signal entry_lpn_b : std_ulogic_vector(64-lrat_maxsize_log2 to 64-lrat_minsize_log2-1); + signal function_24_43 : std_ulogic; + signal function_26_43 : std_ulogic; + signal function_30_43 : std_ulogic; + signal function_32_43 : std_ulogic; + signal function_34_43 : std_ulogic; + signal function_36_43 : std_ulogic; + signal function_40_43 : std_ulogic; + signal pgsize_eq_16M : std_ulogic; + signal pgsize_eq_256M : std_ulogic; + signal pgsize_eq_1G : std_ulogic; + signal pgsize_eq_4G : std_ulogic; + signal pgsize_eq_16G : std_ulogic; + signal pgsize_eq_256G : std_ulogic; + signal pgsize_eq_1T : std_ulogic; + signal pgsize_gte_16M : std_ulogic; + signal pgsize_gte_256M : std_ulogic; + signal pgsize_gte_1G : std_ulogic; + signal pgsize_gte_4G : std_ulogic; + signal pgsize_gte_16G : std_ulogic; + signal pgsize_gte_256G : std_ulogic; + signal pgsize_gte_1T : std_ulogic; + + signal comp_or_24_25 : std_ulogic; + signal comp_or_26_29 : std_ulogic; + signal comp_or_30_31 : std_ulogic; + signal comp_or_32_33 : std_ulogic; + signal comp_or_34_35 : std_ulogic; + signal comp_or_36_39 : std_ulogic; + signal comp_or_40_43 : std_ulogic; + + signal match_line : std_ulogic_vector(64-real_addr_width to 64-lrat_minsize_log2+lpid_width-1); + signal addr_match : std_ulogic; + signal lpid_match : std_ulogic; + +signal unused_dc : std_ulogic; +-- synopsys translate_off +-- synopsys translate_on + +begin + + match_line(64-real_addr_width to 64-lrat_minsize_log2+lpid_width-1) <= not( + (entry_lpn(64-real_addr_width to 64-lrat_minsize_log2-1) & entry_lpid(0 to lpid_width-1)) xor + (addr_in(64-real_addr_width to 64-lrat_minsize_log2-1) & comp_lpid(0 to lpid_width-1)) + ); + +numpgsz8 : if num_pgsizes = 8 generate + + entry_lpn_b(64-lrat_maxsize_log2 to 64-lrat_minsize_log2-1) <= not(entry_lpn(64-lrat_maxsize_log2 to 64-lrat_minsize_log2-1)); + + +gen_nocmpmask80 : if have_cmpmask = 0 generate + pgsize_eq_16M <= '1' when (entry_size="0111") + else '0'; + pgsize_eq_256M <= '1' when (entry_size="1001") + else '0'; + pgsize_eq_1G <= '1' when (entry_size="1010") + else '0'; + pgsize_eq_4G <= '1' when (entry_size="1011") + else '0'; + pgsize_eq_16G <= '1' when (entry_size="1100") + else '0'; + pgsize_eq_256G <= '1' when (entry_size="1110") + else '0'; + pgsize_eq_1T <= '1' when (entry_size="1111") + else '0'; + + pgsize_gte_16M <= '1' when (entry_size="0111" or + pgsize_gte_256M='1') + else '0'; + pgsize_gte_256M <= '1' when (entry_size="1001" or + pgsize_gte_1G='1') + else '0'; + pgsize_gte_1G <= '1' when (entry_size="1010" or + pgsize_gte_4G='1') + else '0'; + pgsize_gte_4G <= '1' when (entry_size="1011" or + pgsize_gte_16G='1') + else '0'; + pgsize_gte_16G <= '1' when (entry_size="1100" or + pgsize_gte_256G='1') + else '0'; + pgsize_gte_256G <= '1' when (entry_size="1110" or + pgsize_gte_1T='1') + else '0'; + pgsize_gte_1T <= '1' when (entry_size="1111") + else '0'; + +end generate gen_nocmpmask80; + +gen_cmpmask80 : if have_cmpmask = 1 generate + pgsize_gte_1T <= entry_cmpmask(0); + pgsize_gte_256G <= entry_cmpmask(1); + pgsize_gte_16G <= entry_cmpmask(2); + pgsize_gte_4G <= entry_cmpmask(3); + pgsize_gte_1G <= entry_cmpmask(4); + pgsize_gte_256M <= entry_cmpmask(5); + pgsize_gte_16M <= entry_cmpmask(6); + + pgsize_eq_1T <= entry_xbitmask(0); + pgsize_eq_256G <= entry_xbitmask(1); + pgsize_eq_16G <= entry_xbitmask(2); + pgsize_eq_4G <= entry_xbitmask(3); + pgsize_eq_1G <= entry_xbitmask(4); + pgsize_eq_256M <= entry_xbitmask(5); + pgsize_eq_16M <= entry_xbitmask(6); +end generate gen_cmpmask80; + + + +gen_noxbit80 : if have_xbit = 0 generate + function_24_43 <= '0'; + function_26_43 <= '0'; + function_30_43 <= '0'; + function_32_43 <= '0'; + function_34_43 <= '0'; + function_36_43 <= '0'; + function_40_43 <= '0'; +end generate gen_noxbit80; + +gen_xbit80 : if (have_xbit /= 0 and real_addr_width=42) generate + function_24_43 <= not(entry_xbit) or + not(pgsize_eq_1T) or + or_reduce(entry_lpn_b(24 to 43) and addr_in(24 to 43)); + function_26_43 <= not(entry_xbit) or + not(pgsize_eq_256G) or + or_reduce(entry_lpn_b(26 to 43) and addr_in(26 to 43)); + function_30_43 <= not(entry_xbit) or + not(pgsize_eq_16G) or + or_reduce(entry_lpn_b(30 to 43) and addr_in(30 to 43)); + function_32_43 <= not(entry_xbit) or + not(pgsize_eq_4G) or + or_reduce(entry_lpn_b(32 to 43) and addr_in(32 to 43)); + function_34_43 <= not(entry_xbit) or + not(pgsize_eq_1G) or + or_reduce(entry_lpn_b(34 to 43) and addr_in(34 to 43)); + function_36_43 <= not(entry_xbit) or + not(pgsize_eq_256M) or + or_reduce(entry_lpn_b(36 to 43) and addr_in(36 to 43)); + function_40_43 <= not(entry_xbit) or + not(pgsize_eq_16M) or + or_reduce(entry_lpn_b(40 to 43) and addr_in(40 to 43)); +end generate gen_xbit80; + +gen_xbit81 : if (have_xbit /= 0 and real_addr_width=32) generate + function_24_43 <= '1'; + function_26_43 <= '1'; + function_30_43 <= '1'; + function_32_43 <= '1'; + function_34_43 <= not(entry_xbit) or + not(pgsize_eq_1G) or + or_reduce(entry_lpn_b(34 to 43) and addr_in(34 to 43)); + function_36_43 <= not(entry_xbit) or + not(pgsize_eq_256M) or + or_reduce(entry_lpn_b(36 to 43) and addr_in(36 to 43)); + function_40_43 <= not(entry_xbit) or + not(pgsize_eq_16M) or + or_reduce(entry_lpn_b(40 to 43) and addr_in(40 to 43)); +end generate gen_xbit81; + +gen_comp80 : if real_addr_width=42 generate + comp_or_24_25 <= and_reduce(match_line(24 to 25)) or pgsize_gte_1T; + comp_or_26_29 <= and_reduce(match_line(26 to 29)) or pgsize_gte_256G; + comp_or_30_31 <= and_reduce(match_line(30 to 31)) or pgsize_gte_16G; + comp_or_32_33 <= and_reduce(match_line(32 to 33)) or pgsize_gte_4G; + comp_or_34_35 <= and_reduce(match_line(34 to 35)) or pgsize_gte_1G; + comp_or_36_39 <= and_reduce(match_line(36 to 39)) or pgsize_gte_256M; + comp_or_40_43 <= and_reduce(match_line(40 to 43)) or pgsize_gte_16M; +end generate gen_comp80; + +gen_comp81 : if real_addr_width=32 generate + comp_or_24_25 <= '1'; + comp_or_26_29 <= '1'; + comp_or_30_31 <= '1'; + comp_or_32_33 <= '1'; + comp_or_34_35 <= and_reduce(match_line(34 to 35)) or pgsize_gte_1G; + comp_or_36_39 <= and_reduce(match_line(36 to 39)) or pgsize_gte_256M; + comp_or_40_43 <= and_reduce(match_line(40 to 43)) or pgsize_gte_16M; +end generate gen_comp81; + +gen_noxbit81 : if (have_xbit = 0 and real_addr_width=42) generate + addr_match <= ( and_reduce(match_line(22 to 23)) and + comp_or_24_25 and + comp_or_26_29 and + comp_or_30_31 and + comp_or_32_33 and + comp_or_34_35 and + comp_or_36_39 and + comp_or_40_43 ) or + not(addr_enable); +end generate gen_noxbit81; + +gen_noxbit82 : if (have_xbit = 0 and real_addr_width=32) generate + addr_match <= ( and_reduce(match_line(32 to 33)) and + comp_or_34_35 and + comp_or_36_39 and + comp_or_40_43 ) or + not(addr_enable); +end generate gen_noxbit82; + +gen_xbit82 : if (have_xbit /= 0 and real_addr_width=42) generate + addr_match <= (and_reduce(match_line(22 to 23)) and + comp_or_24_25 and + comp_or_26_29 and + comp_or_30_31 and + comp_or_32_33 and + comp_or_34_35 and + comp_or_36_39 and + comp_or_40_43 and + function_24_43 and + function_26_43 and + function_30_43 and + function_32_43 and + function_34_43 and + function_36_43 and + function_40_43) or + not(addr_enable); +end generate gen_xbit82; + +gen_xbit83 : if (have_xbit /= 0 and real_addr_width=32) generate + addr_match <= (and_reduce(match_line(32 to 33)) and + comp_or_34_35 and + comp_or_36_39 and + comp_or_40_43 and + function_34_43 and + function_36_43 and + function_40_43) or + not(addr_enable); +end generate gen_xbit83; + +end generate numpgsz8; + + + lpid_match <= and_reduce(match_line(64-lrat_minsize_log2 to 64-lrat_minsize_log2+lpid_width-1)) or + not(or_reduce(entry_lpid(0 to 7))) or + not(lpid_enable); + + match <= addr_match and + lpid_match and + entry_v; + + dbg_addr_match <= addr_match; + dbg_lpid_match <= lpid_match; + +gen_unused0 : if have_cmpmask = 0 generate + unused_dc <= '0'; +end generate gen_unused0; +gen_unused1 : if have_cmpmask = 1 generate + unused_dc <= or_reduce(entry_size); +end generate gen_unused1; + +end mmq_tlb_lrat_matchline; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/mmq_tlb_matchline.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/mmq_tlb_matchline.vhdl new file mode 100644 index 0000000..80897e9 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/mmq_tlb_matchline.vhdl @@ -0,0 +1,572 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +LIBRARY IEEE; +USE ieee.std_logic_1164.ALL ; +LIBRARY IBM; +USE ibm.std_ulogic_support.ALL; +USE ibm.std_ulogic_function_support.ALL; +library support; +use support.power_logic_pkg.all; + + +entity mmq_tlb_matchline is + generic (have_xbit : integer := 1; + num_pgsizes : integer := 5; + have_cmpmask : integer := 1; + cmpmask_width : integer := 5); + +port( + vdd : inout power_logic; + gnd : inout power_logic; + addr_in : in std_ulogic_vector(0 to 51); + addr_enable : in std_ulogic_vector(0 to 8); + comp_pgsize : in std_ulogic_vector(0 to 3); + pgsize_enable : in std_ulogic; + entry_size : in std_ulogic_vector(0 to 3); + entry_cmpmask : in std_ulogic_vector(0 to cmpmask_width-1); + entry_xbit : in std_ulogic; + entry_xbitmask : in std_ulogic_vector(0 to cmpmask_width-1); + entry_epn : in std_ulogic_vector(0 to 51); + comp_class : in std_ulogic_vector(0 to 1); + entry_class : in std_ulogic_vector(0 to 1); + class_enable : in std_ulogic; + comp_extclass : in std_ulogic_vector(0 to 1); + entry_extclass : in std_ulogic_vector(0 to 1); + extclass_enable : in std_ulogic_vector(0 to 1); + comp_state : in std_ulogic_vector(0 to 1); + entry_gs : in std_ulogic; + entry_ts : in std_ulogic; + state_enable : in std_ulogic_vector(0 to 1); + entry_thdid : in std_ulogic_vector(0 to 3); + comp_thdid : in std_ulogic_vector(0 to 3); + thdid_enable : in std_ulogic; + entry_pid : in std_ulogic_vector(0 to 13); + comp_pid : in std_ulogic_vector(0 to 13); + pid_enable : in std_ulogic; + entry_lpid : in std_ulogic_vector(0 to 7); + comp_lpid : in std_ulogic_vector(0 to 7); + lpid_enable : in std_ulogic; + entry_ind : in std_ulogic; + comp_ind : in std_ulogic; + ind_enable : in std_ulogic; + entry_iprot : in std_ulogic; + comp_iprot : in std_ulogic; + iprot_enable : in std_ulogic; + entry_v : in std_ulogic; + comp_invalidate : in std_ulogic; + + match : out std_ulogic; + + dbg_addr_match : out std_ulogic; + dbg_pgsize_match : out std_ulogic; + dbg_class_match : out std_ulogic; + dbg_extclass_match : out std_ulogic; + dbg_state_match : out std_ulogic; + dbg_thdid_match : out std_ulogic; + dbg_pid_match : out std_ulogic; + dbg_lpid_match : out std_ulogic; + dbg_ind_match : out std_ulogic; + dbg_iprot_match : out std_ulogic + +); + + -- synopsys translate_off + -- synopsys translate_on + +end mmq_tlb_matchline; + +architecture mmq_tlb_matchline of mmq_tlb_matchline is + + + + signal entry_epn_b : std_ulogic_vector(30 to 51); + signal function_50_51 : std_ulogic; + signal function_48_51 : std_ulogic; + signal function_46_51 : std_ulogic; + signal function_44_51 : std_ulogic; + signal function_40_51 : std_ulogic; + signal function_36_51 : std_ulogic; + signal function_34_51 : std_ulogic; + signal pgsize_gte_16K : std_ulogic; + signal pgsize_gte_64K : std_ulogic; + signal pgsize_gte_256K : std_ulogic; + signal pgsize_gte_1M : std_ulogic; + signal pgsize_gte_16M : std_ulogic; + signal pgsize_gte_256M : std_ulogic; + signal pgsize_gte_1G : std_ulogic; + signal pgsize_eq_16K : std_ulogic; + signal pgsize_eq_64K : std_ulogic; + signal pgsize_eq_256K : std_ulogic; + signal pgsize_eq_1M : std_ulogic; + signal pgsize_eq_16M : std_ulogic; + signal pgsize_eq_256M : std_ulogic; + signal pgsize_eq_1G : std_ulogic; + signal comp_or_34_35 : std_ulogic; + signal comp_or_36_39 : std_ulogic; + signal comp_or_40_43 : std_ulogic; + signal comp_or_44_45 : std_ulogic; + signal comp_or_44_47 : std_ulogic; + signal comp_or_46_47 : std_ulogic; + signal comp_or_48_49 : std_ulogic; + signal comp_or_48_51 : std_ulogic; + signal comp_or_50_51 : std_ulogic; + signal match_line : std_ulogic_vector(0 to 85); + signal pgsize_match : std_ulogic; + signal addr_match : std_ulogic; + signal class_match : std_ulogic; + signal extclass_match : std_ulogic; + signal state_match : std_ulogic; + signal thdid_match : std_ulogic; + signal pid_match : std_ulogic; + signal lpid_match : std_ulogic; + signal ind_match : std_ulogic; + signal iprot_match : std_ulogic; + signal addr_match_xbit_contrib : std_ulogic; + signal addr_match_lsb_contrib : std_ulogic; + signal addr_match_msb_contrib : std_ulogic; + + signal unused_dc : std_ulogic_vector(0 to 4); +-- synopsys translate_off +-- synopsys translate_on + +begin + + match_line(0 to 85) <= not( + (entry_epn(0 to 51) & entry_size(0 to 3) & entry_class(0 to 1) & entry_extclass(0 to 1) & entry_gs & entry_ts & entry_pid(0 to 13) & entry_lpid(0 to 7) & entry_ind & entry_iprot) xor + (addr_in(0 to 51) & comp_pgsize(0 to 3) & comp_class(0 to 1) & comp_extclass(0 to 1) & comp_state(0 to 1) & comp_pid(0 to 13) & comp_lpid(0 to 7) & comp_ind & comp_iprot) + ); + +numpgsz8 : if num_pgsizes = 8 generate + + entry_epn_b(30 to 51) <= not(entry_epn(30 to 51)); + + unused_dc <= (others => '0'); + +gen_nocmpmask80 : if have_cmpmask = 0 generate + pgsize_gte_1G <= ( entry_size(0) and not(entry_size(1)) and entry_size(2) and not(entry_size(3)) ); + pgsize_gte_256M <= ( entry_size(0) and not(entry_size(1)) and not(entry_size(2)) and entry_size(3) ) or + pgsize_gte_1G; + pgsize_gte_16M <= (not(entry_size(0)) and entry_size(1) and entry_size(2) and entry_size(3) ) or + pgsize_gte_256M; + pgsize_gte_1M <= (not(entry_size(0)) and entry_size(1) and not(entry_size(2)) and entry_size(3) ) or + pgsize_gte_16M; + pgsize_gte_256K <= (not(entry_size(0)) and entry_size(1) and not(entry_size(2)) and not(entry_size(3)) ) or + pgsize_gte_1M; + pgsize_gte_64K <= (not(entry_size(0)) and not(entry_size(1)) and entry_size(2) and entry_size(3) ) or + pgsize_gte_256K; + pgsize_gte_16K <= (not(entry_size(0)) and not(entry_size(1)) and entry_size(2) and not(entry_size(3)) ) or + pgsize_gte_64K; +end generate gen_nocmpmask80; + +gen_cmpmask80 : if have_cmpmask = 1 generate + pgsize_gte_1G <= entry_cmpmask(0); + pgsize_gte_256M <= entry_cmpmask(1); + pgsize_gte_16M <= entry_cmpmask(2); + pgsize_gte_1M <= entry_cmpmask(3); + pgsize_gte_256K <= entry_cmpmask(4); + pgsize_gte_64K <= entry_cmpmask(5); + pgsize_gte_16K <= entry_cmpmask(6); + + pgsize_eq_1G <= entry_xbitmask(0); + pgsize_eq_256M <= entry_xbitmask(1); + pgsize_eq_16M <= entry_xbitmask(2); + pgsize_eq_1M <= entry_xbitmask(3); + pgsize_eq_256K <= entry_xbitmask(4); + pgsize_eq_64K <= entry_xbitmask(5); + pgsize_eq_16K <= entry_xbitmask(6); +end generate gen_cmpmask80; + +gen_noxbit80 : if have_xbit = 0 generate + function_34_51 <= '0'; + function_36_51 <= '0'; + function_40_51 <= '0'; + function_44_51 <= '0'; + function_46_51 <= '0'; + function_48_51 <= '0'; + function_50_51 <= '0'; +end generate gen_noxbit80; + +gen_xbit80 : if have_xbit /= 0 generate + + function_34_51 <= not(entry_xbit) or + not(pgsize_eq_1G) or + or_reduce(entry_epn_b(34 to 51) and addr_in(34 to 51)); + function_36_51 <= not(entry_xbit) or + not(pgsize_eq_256M) or + or_reduce(entry_epn_b(36 to 51) and addr_in(36 to 51)); + function_40_51 <= not(entry_xbit) or + not(pgsize_eq_16M) or + or_reduce(entry_epn_b(40 to 51) and addr_in(40 to 51)); + function_44_51 <= not(entry_xbit) or + not(pgsize_eq_1M) or + or_reduce(entry_epn_b(44 to 51) and addr_in(44 to 51)); + function_46_51 <= not(entry_xbit) or + not(pgsize_eq_256K) or + or_reduce(entry_epn_b(46 to 51) and addr_in(46 to 51)); + function_48_51 <= not(entry_xbit) or + not(pgsize_eq_64K) or + or_reduce(entry_epn_b(48 to 51) and addr_in(48 to 51)); + function_50_51 <= not(entry_xbit) or + not(pgsize_eq_16K) or + or_reduce(entry_epn_b(50 to 51) and addr_in(50 to 51)); +end generate gen_xbit80; + + + comp_or_50_51 <= and_reduce(match_line(50 to 51)) or pgsize_gte_16K; + comp_or_48_49 <= and_reduce(match_line(48 to 49)) or pgsize_gte_64K; + comp_or_46_47 <= and_reduce(match_line(46 to 47)) or pgsize_gte_256K; + comp_or_44_45 <= and_reduce(match_line(44 to 45)) or pgsize_gte_1M; + comp_or_40_43 <= and_reduce(match_line(40 to 43)) or pgsize_gte_16M; + comp_or_36_39 <= and_reduce(match_line(36 to 39)) or pgsize_gte_256M; + comp_or_34_35 <= and_reduce(match_line(34 to 35)) or pgsize_gte_1G; + +gen_noxbit81 : if have_xbit = 0 generate + addr_match <= ( comp_or_34_35 and + comp_or_36_39 and + comp_or_40_43 and + comp_or_44_45 and + comp_or_46_47 and + comp_or_48_49 and + (and_reduce(match_line(0 to 12)) or not(addr_enable(0))) and + (and_reduce(match_line(13 to 14)) or not(addr_enable(1))) and + (and_reduce(match_line(15 to 16)) or not(addr_enable(2))) and + (and_reduce(match_line(17 to 18)) or not(addr_enable(3))) and + (and_reduce(match_line(19 to 22)) or not(addr_enable(4))) and + (and_reduce(match_line(23 to 26)) or not(addr_enable(5))) and + (and_reduce(match_line(27 to 30)) or not(addr_enable(6))) and + (and_reduce(match_line(31 to 33)) or not(addr_enable(7))) + ) or + not(addr_enable(8)); + addr_match_xbit_contrib <= '0'; + + addr_match_lsb_contrib <= ( comp_or_34_35 and + comp_or_36_39 and + comp_or_40_43 and + comp_or_44_45 and + comp_or_46_47 and + comp_or_48_49 and + comp_or_50_51); + + addr_match_msb_contrib <= (and_reduce(match_line(0 to 12)) or not(addr_enable(0))) and + (and_reduce(match_line(13 to 14)) or not(addr_enable(1))) and + (and_reduce(match_line(15 to 16)) or not(addr_enable(2))) and + (and_reduce(match_line(17 to 18)) or not(addr_enable(3))) and + (and_reduce(match_line(19 to 22)) or not(addr_enable(4))) and + (and_reduce(match_line(23 to 26)) or not(addr_enable(5))) and + (and_reduce(match_line(27 to 30)) or not(addr_enable(6))) and + (and_reduce(match_line(31 to 33)) or not(addr_enable(7))) ; + +end generate gen_noxbit81; + +gen_xbit81 : if have_xbit /= 0 generate + addr_match <= ( function_50_51 and + function_48_51 and + function_46_51 and + function_44_51 and + function_40_51 and + function_36_51 and + function_34_51 and + comp_or_34_35 and + comp_or_36_39 and + comp_or_40_43 and + comp_or_44_45 and + comp_or_46_47 and + comp_or_48_49 and + comp_or_50_51 and + (and_reduce(match_line(0 to 12)) or not(addr_enable(0))) and + (and_reduce(match_line(13 to 14)) or not(addr_enable(1))) and + (and_reduce(match_line(15 to 16)) or not(addr_enable(2))) and + (and_reduce(match_line(17 to 18)) or not(addr_enable(3))) and + (and_reduce(match_line(19 to 22)) or not(addr_enable(4))) and + (and_reduce(match_line(23 to 26)) or not(addr_enable(5))) and + (and_reduce(match_line(27 to 30)) or not(addr_enable(6))) and + (and_reduce(match_line(31 to 33)) or not(addr_enable(7))) + ) or + not(addr_enable(8)); + + addr_match_xbit_contrib <= ( function_50_51 and + function_48_51 and + function_46_51 and + function_44_51 and + function_40_51 and + function_36_51 and + function_34_51 ); + + addr_match_lsb_contrib <= ( comp_or_34_35 and + comp_or_36_39 and + comp_or_40_43 and + comp_or_44_45 and + comp_or_46_47 and + comp_or_48_49 and + comp_or_50_51); + + addr_match_msb_contrib <= (and_reduce(match_line(0 to 12)) or not(addr_enable(0))) and + (and_reduce(match_line(13 to 14)) or not(addr_enable(1))) and + (and_reduce(match_line(15 to 16)) or not(addr_enable(2))) and + (and_reduce(match_line(17 to 18)) or not(addr_enable(3))) and + (and_reduce(match_line(19 to 22)) or not(addr_enable(4))) and + (and_reduce(match_line(23 to 26)) or not(addr_enable(5))) and + (and_reduce(match_line(27 to 30)) or not(addr_enable(6))) and + (and_reduce(match_line(31 to 33)) or not(addr_enable(7))) ; + +end generate gen_xbit81; + +end generate numpgsz8; + + +numpgsz5 : if num_pgsizes = 5 generate + + function_50_51 <= '0'; + function_46_51 <= '0'; + pgsize_gte_16K <= '0'; + pgsize_gte_256K <= '0'; + pgsize_eq_16K <= '0'; + pgsize_eq_256K <= '0'; + comp_or_44_45 <= '0'; + comp_or_46_47 <= '0'; + comp_or_48_49 <= '0'; + comp_or_50_51 <= '0'; + + entry_epn_b(30 to 51) <= not(entry_epn(30 to 51)); + +unused_dc(0) <= (pgsize_gte_16K and pgsize_gte_256K and pgsize_eq_16K and pgsize_eq_256K); +unused_dc(1) <= (function_50_51 and function_46_51); +unused_dc(2) <= (comp_or_44_45 and comp_or_46_47 and comp_or_48_49 and comp_or_50_51); +unused_dc(3) <= or_reduce(entry_epn_b(30 to 33)); +unused_dc(4) <= addr_match_xbit_contrib and addr_match_lsb_contrib and addr_match_msb_contrib; + +gen_nocmpmask50 : if have_cmpmask = 0 generate + pgsize_gte_1G <= ( entry_size(0) and not(entry_size(1)) and entry_size(2) and not(entry_size(3)) ); + + pgsize_gte_256M <= ( entry_size(0) and not(entry_size(1)) and not(entry_size(2)) and entry_size(3) ) or + pgsize_gte_1G; + pgsize_gte_16M <= (not(entry_size(0)) and entry_size(1) and entry_size(2) and entry_size(3)) or + pgsize_gte_256M; + pgsize_gte_1M <= (not(entry_size(0)) and entry_size(1) and not(entry_size(2)) and entry_size(3)) or + pgsize_gte_16M; + pgsize_gte_64K <= (not(entry_size(0)) and not(entry_size(1)) and entry_size(2) and entry_size(3)) or + pgsize_gte_1M; + + pgsize_eq_1G <= ( entry_size(0) and not(entry_size(1)) and entry_size(2) and not(entry_size(3)) ); + pgsize_eq_256M <= ( entry_size(0) and not(entry_size(1)) and not(entry_size(2)) and entry_size(3) ); + pgsize_eq_16M <= ( not(entry_size(0)) and entry_size(1) and entry_size(2) and entry_size(3) ); + pgsize_eq_1M <= ( not(entry_size(0)) and entry_size(1) and not(entry_size(2)) and entry_size(3) ); + pgsize_eq_64K <= ( not(entry_size(0)) and not(entry_size(1)) and entry_size(2) and entry_size(3) ); +end generate gen_nocmpmask50; + +gen_cmpmask50 : if have_cmpmask = 1 generate + pgsize_gte_1G <= entry_cmpmask(0); + pgsize_gte_256M <= entry_cmpmask(1); + pgsize_gte_16M <= entry_cmpmask(2); + pgsize_gte_1M <= entry_cmpmask(3); + pgsize_gte_64K <= entry_cmpmask(4); + + pgsize_eq_1G <= entry_xbitmask(0); + pgsize_eq_256M <= entry_xbitmask(1); + pgsize_eq_16M <= entry_xbitmask(2); + pgsize_eq_1M <= entry_xbitmask(3); + pgsize_eq_64K <= entry_xbitmask(4); +end generate gen_cmpmask50; + + +gen_noxbit50 : if have_xbit = 0 generate + function_34_51 <= '0'; + function_36_51 <= '0'; + function_40_51 <= '0'; + function_44_51 <= '0'; + function_48_51 <= '0'; +end generate gen_noxbit50; + +gen_xbit50 : if have_xbit /= 0 generate + function_34_51 <= not(entry_xbit) or + not(pgsize_eq_1G) or + or_reduce(entry_epn_b(34 to 51) and addr_in(34 to 51)); + function_36_51 <= not(entry_xbit) or + not(pgsize_eq_256M) or + or_reduce(entry_epn_b(36 to 51) and addr_in(36 to 51)); + function_40_51 <= not(entry_xbit) or + not(pgsize_eq_16M) or + or_reduce(entry_epn_b(40 to 51) and addr_in(40 to 51)); + function_44_51 <= not(entry_xbit) or + not(pgsize_eq_1M) or + or_reduce(entry_epn_b(44 to 51) and addr_in(44 to 51)); + function_48_51 <= not(entry_xbit) or + not(pgsize_eq_64K) or + or_reduce(entry_epn_b(48 to 51) and addr_in(48 to 51)); +end generate gen_xbit50; + + comp_or_48_51 <= and_reduce(match_line(48 to 51)) or pgsize_gte_64K; + comp_or_44_47 <= and_reduce(match_line(44 to 47)) or pgsize_gte_1M; + comp_or_40_43 <= and_reduce(match_line(40 to 43)) or pgsize_gte_16M; + comp_or_36_39 <= and_reduce(match_line(36 to 39)) or pgsize_gte_256M; + comp_or_34_35 <= and_reduce(match_line(34 to 35)) or pgsize_gte_1G; + +gen_noxbit51 : if have_xbit = 0 generate + addr_match <= ( comp_or_34_35 and + comp_or_36_39 and + comp_or_40_43 and + comp_or_44_47 and + comp_or_48_51 and + (and_reduce(match_line(0 to 12)) or not(addr_enable(0))) and + (and_reduce(match_line(13 to 14)) or not(addr_enable(1))) and + (and_reduce(match_line(15 to 16)) or not(addr_enable(2))) and + (and_reduce(match_line(17 to 18)) or not(addr_enable(3))) and + (and_reduce(match_line(19 to 22)) or not(addr_enable(4))) and + (and_reduce(match_line(23 to 26)) or not(addr_enable(5))) and + (and_reduce(match_line(27 to 30)) or not(addr_enable(6))) and + (and_reduce(match_line(31 to 33)) or not(addr_enable(7))) + ) or + not(addr_enable(8)); + addr_match_xbit_contrib <= '0'; + + addr_match_lsb_contrib <= ( comp_or_34_35 and + comp_or_36_39 and + comp_or_40_43 and + comp_or_44_47 and + comp_or_48_51); + + addr_match_msb_contrib <= (and_reduce(match_line(0 to 12)) or not(addr_enable(0))) and + (and_reduce(match_line(13 to 14)) or not(addr_enable(1))) and + (and_reduce(match_line(15 to 16)) or not(addr_enable(2))) and + (and_reduce(match_line(17 to 18)) or not(addr_enable(3))) and + (and_reduce(match_line(19 to 22)) or not(addr_enable(4))) and + (and_reduce(match_line(23 to 26)) or not(addr_enable(5))) and + (and_reduce(match_line(27 to 30)) or not(addr_enable(6))) and + (and_reduce(match_line(31 to 33)) or not(addr_enable(7))) ; + +end generate gen_noxbit51; + +gen_xbit51 : if have_xbit /= 0 generate + addr_match <= ( function_48_51 and + function_44_51 and + function_40_51 and + function_36_51 and + function_34_51 and + comp_or_34_35 and + comp_or_36_39 and + comp_or_40_43 and + comp_or_44_47 and + comp_or_48_51 and + (and_reduce(match_line(0 to 12)) or not(addr_enable(0))) and + (and_reduce(match_line(13 to 14)) or not(addr_enable(1))) and + (and_reduce(match_line(15 to 16)) or not(addr_enable(2))) and + (and_reduce(match_line(17 to 18)) or not(addr_enable(3))) and + (and_reduce(match_line(19 to 22)) or not(addr_enable(4))) and + (and_reduce(match_line(23 to 26)) or not(addr_enable(5))) and + (and_reduce(match_line(27 to 30)) or not(addr_enable(6))) and + (and_reduce(match_line(31 to 33)) or not(addr_enable(7))) + ) or + not(addr_enable(8)); + + addr_match_xbit_contrib <= ( function_48_51 and + function_44_51 and + function_40_51 and + function_36_51 and + function_34_51 ); + + addr_match_lsb_contrib <= ( comp_or_34_35 and + comp_or_36_39 and + comp_or_40_43 and + comp_or_44_47 and + comp_or_48_51); + + addr_match_msb_contrib <= (and_reduce(match_line(0 to 12)) or not(addr_enable(0))) and + (and_reduce(match_line(13 to 14)) or not(addr_enable(1))) and + (and_reduce(match_line(15 to 16)) or not(addr_enable(2))) and + (and_reduce(match_line(17 to 18)) or not(addr_enable(3))) and + (and_reduce(match_line(19 to 22)) or not(addr_enable(4))) and + (and_reduce(match_line(23 to 26)) or not(addr_enable(5))) and + (and_reduce(match_line(27 to 30)) or not(addr_enable(6))) and + (and_reduce(match_line(31 to 33)) or not(addr_enable(7))) ; + +end generate gen_xbit51; + +end generate numpgsz5; + + + pgsize_match <= and_reduce(match_line(52 to 55)) or + not(pgsize_enable); + + class_match <= and_reduce(match_line(56 to 57)) or + not(class_enable); + + extclass_match <= (match_line(58) or + not(extclass_enable(0))) and + (match_line(59) or + not(extclass_enable(1))); + + + state_match <= (match_line(60) or + not(state_enable(0))) and + (match_line(61) or + not(state_enable(1))); + + thdid_match <= or_reduce(entry_thdid(0 to 3) and comp_thdid(0 to 3)) or + not(thdid_enable); + + pid_match <= and_reduce(match_line(62 to 75)) or + (not(or_reduce(entry_pid(0 to 13))) and not comp_invalidate) or + not(pid_enable); + + lpid_match <= and_reduce(match_line(76 to 83)) or + (not(or_reduce(entry_lpid(0 to 7))) and not comp_invalidate) or + not(lpid_enable); + + ind_match <= match_line(84) or + not(ind_enable); + + iprot_match <= match_line(85) or + not(iprot_enable); + + match <= addr_match and + pgsize_match and + class_match and + extclass_match and + state_match and + thdid_match and + pid_match and + lpid_match and + ind_match and + iprot_match and + entry_v; + + dbg_addr_match <= addr_match; + dbg_pgsize_match <= pgsize_match; + dbg_class_match <= class_match; + dbg_extclass_match <= extclass_match; + dbg_state_match <= state_match; + dbg_thdid_match <= thdid_match; + dbg_pid_match <= pid_match; + dbg_lpid_match <= lpid_match; + dbg_ind_match <= ind_match; + dbg_iprot_match <= iprot_match; + +end mmq_tlb_matchline; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/mmq_tlb_req.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/mmq_tlb_req.vhdl new file mode 100644 index 0000000..f44f746 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/mmq_tlb_req.vhdl @@ -0,0 +1,2798 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; +use ieee.std_logic_1164.all; +library ibm; +use ibm.std_ulogic_unsigned.all; +use ibm.std_ulogic_function_support.all; +library support; +use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity mmq_tlb_req is + generic(thdid_width : integer := 4; + state_width : integer := 4; + pid_width : integer := 14; + pid_width_erat : integer := 8; + lpid_width : integer := 8; + req_epn_width : integer := 52; + rs_data_width : integer := 64; + expand_type : integer := 2 ); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + +tc_ccflush_dc : in std_ulogic; +tc_scan_dis_dc_b : in std_ulogic; +tc_scan_diag_dc : in std_ulogic; +tc_lbist_en_dc : in std_ulogic; +lcb_d_mode_dc : in std_ulogic; +lcb_clkoff_dc_b : in std_ulogic; +lcb_act_dis_dc : in std_ulogic; +lcb_mpw1_dc_b : in std_ulogic_vector(0 to 4); +lcb_mpw2_dc_b : in std_ulogic; +lcb_delay_lclkr_dc : in std_ulogic_vector(0 to 4); +ac_func_scan_in :in std_ulogic; +ac_func_scan_out :out std_ulogic; +pc_sg_2 : in std_ulogic; +pc_func_sl_thold_2 : in std_ulogic; +pc_func_slp_sl_thold_2 : in std_ulogic; +xu_mm_ccr2_notlb_b : in std_ulogic; +mmucr2_act_override : in std_ulogic; +pid0 : in std_ulogic_vector(0 to pid_width-1); +pid1 : in std_ulogic_vector(0 to pid_width-1); +pid2 : in std_ulogic_vector(0 to pid_width-1); +pid3 : in std_ulogic_vector(0 to pid_width-1); +lpidr : in std_ulogic_vector(0 to lpid_width-1); +iu_mm_ierat_req : in std_ulogic; +iu_mm_ierat_epn : in std_ulogic_vector(0 to 51); +iu_mm_ierat_thdid : in std_ulogic_vector(0 to thdid_width-1); +iu_mm_ierat_state : in std_ulogic_vector(0 to state_width-1); +iu_mm_ierat_tid : in std_ulogic_vector(0 to pid_width-1); +iu_mm_ierat_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_mm_derat_req : in std_ulogic; +xu_mm_derat_epn : in std_ulogic_vector(64-rs_data_width to 51); +xu_mm_derat_thdid : in std_ulogic_vector(0 to thdid_width-1); +xu_mm_derat_ttype : in std_ulogic_vector(0 to 1); +xu_mm_derat_state : in std_ulogic_vector(0 to state_width-1); +xu_mm_derat_tid : in std_ulogic_vector(0 to pid_width-1); +xu_mm_derat_lpid : in std_ulogic_vector(0 to lpid_width-1); +ierat_req0_pid : out std_ulogic_vector(0 to pid_width-1); +ierat_req0_as : out std_ulogic; +ierat_req0_gs : out std_ulogic; +ierat_req0_epn : out std_ulogic_vector(0 to req_epn_width-1); +ierat_req0_thdid : out std_ulogic_vector(0 to thdid_width-1); +ierat_req0_valid : out std_ulogic; +ierat_req0_nonspec : out std_ulogic; +ierat_req1_pid : out std_ulogic_vector(0 to pid_width-1); +ierat_req1_as : out std_ulogic; +ierat_req1_gs : out std_ulogic; +ierat_req1_epn : out std_ulogic_vector(0 to req_epn_width-1); +ierat_req1_thdid : out std_ulogic_vector(0 to thdid_width-1); +ierat_req1_valid : out std_ulogic; +ierat_req1_nonspec : out std_ulogic; +ierat_req2_pid : out std_ulogic_vector(0 to pid_width-1); +ierat_req2_as : out std_ulogic; +ierat_req2_gs : out std_ulogic; +ierat_req2_epn : out std_ulogic_vector(0 to req_epn_width-1); +ierat_req2_thdid : out std_ulogic_vector(0 to thdid_width-1); +ierat_req2_valid : out std_ulogic; +ierat_req2_nonspec : out std_ulogic; +ierat_req3_pid : out std_ulogic_vector(0 to pid_width-1); +ierat_req3_as : out std_ulogic; +ierat_req3_gs : out std_ulogic; +ierat_req3_epn : out std_ulogic_vector(0 to req_epn_width-1); +ierat_req3_thdid : out std_ulogic_vector(0 to thdid_width-1); +ierat_req3_valid : out std_ulogic; +ierat_req3_nonspec : out std_ulogic; +ierat_iu4_pid : out std_ulogic_vector(0 to pid_width-1); +ierat_iu4_gs : out std_ulogic; +ierat_iu4_as : out std_ulogic; +ierat_iu4_epn : out std_ulogic_vector(0 to req_epn_width-1); +ierat_iu4_thdid : out std_ulogic_vector(0 to thdid_width-1); +ierat_iu4_valid : out std_ulogic; +derat_req0_lpid : out std_ulogic_vector(0 to lpid_width-1); +derat_req0_pid : out std_ulogic_vector(0 to pid_width-1); +derat_req0_as : out std_ulogic; +derat_req0_gs : out std_ulogic; +derat_req0_epn : out std_ulogic_vector(0 to req_epn_width-1); +derat_req0_thdid : out std_ulogic_vector(0 to thdid_width-1); +derat_req0_valid : out std_ulogic; +derat_req1_lpid : out std_ulogic_vector(0 to lpid_width-1); +derat_req1_pid : out std_ulogic_vector(0 to pid_width-1); +derat_req1_as : out std_ulogic; +derat_req1_gs : out std_ulogic; +derat_req1_epn : out std_ulogic_vector(0 to req_epn_width-1); +derat_req1_thdid : out std_ulogic_vector(0 to thdid_width-1); +derat_req1_valid : out std_ulogic; +derat_req2_lpid : out std_ulogic_vector(0 to lpid_width-1); +derat_req2_pid : out std_ulogic_vector(0 to pid_width-1); +derat_req2_as : out std_ulogic; +derat_req2_gs : out std_ulogic; +derat_req2_epn : out std_ulogic_vector(0 to req_epn_width-1); +derat_req2_thdid : out std_ulogic_vector(0 to thdid_width-1); +derat_req2_valid : out std_ulogic; +derat_req3_lpid : out std_ulogic_vector(0 to lpid_width-1); +derat_req3_pid : out std_ulogic_vector(0 to pid_width-1); +derat_req3_as : out std_ulogic; +derat_req3_gs : out std_ulogic; +derat_req3_epn : out std_ulogic_vector(0 to req_epn_width-1); +derat_req3_thdid : out std_ulogic_vector(0 to thdid_width-1); +derat_req3_valid : out std_ulogic; +derat_ex5_lpid : out std_ulogic_vector(0 to lpid_width-1); +derat_ex5_pid : out std_ulogic_vector(0 to pid_width-1); +derat_ex5_gs : out std_ulogic; +derat_ex5_as : out std_ulogic; +derat_ex5_epn : out std_ulogic_vector(0 to req_epn_width-1); +derat_ex5_thdid : out std_ulogic_vector(0 to thdid_width-1); +derat_ex5_valid : out std_ulogic; +xu_ex3_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_mm_ex4_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_mm_ex5_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_mm_ierat_miss : in std_ulogic_vector(0 to thdid_width-1); +xu_mm_ierat_flush : in std_ulogic_vector(0 to thdid_width-1); +mm_xu_eratmiss_done : in std_ulogic_vector(0 to thdid_width-1); +mm_xu_tlb_miss : in std_ulogic_vector(0 to thdid_width-1); +tlb_cmp_ierat_dup_val : in std_ulogic_vector(0 to 6); +tlb_cmp_derat_dup_val : in std_ulogic_vector(0 to 6); +tlb_seq_ierat_req : out std_ulogic; +tlb_seq_derat_req : out std_ulogic; +tlb_seq_ierat_done : in std_ulogic; +tlb_seq_derat_done : in std_ulogic; +ierat_req_taken : in std_ulogic; +derat_req_taken : in std_ulogic; +ierat_req_epn : out std_ulogic_vector(0 to req_epn_width-1); +ierat_req_pid : out std_ulogic_vector(0 to pid_width-1); +ierat_req_state : out std_ulogic_vector(0 to state_width-1); +ierat_req_thdid : out std_ulogic_vector(0 to thdid_width-1); +ierat_req_dup : out std_ulogic_vector(0 to 1); +derat_req_epn : out std_ulogic_vector(0 to req_epn_width-1); +derat_req_pid : out std_ulogic_vector(0 to pid_width-1); +derat_req_lpid : out std_ulogic_vector(0 to lpid_width-1); +derat_req_state : out std_ulogic_vector(0 to state_width-1); +derat_req_ttype : out std_ulogic_vector(0 to 1); +derat_req_thdid : out std_ulogic_vector(0 to thdid_width-1); +derat_req_dup : out std_ulogic_vector(0 to 1); +tlb_req_quiesce : out std_ulogic_vector(0 to thdid_width-1); +tlb_req_dbg_ierat_iu5_valid_q : out std_ulogic; +tlb_req_dbg_ierat_iu5_thdid : out std_ulogic_vector(0 to 1); +tlb_req_dbg_ierat_iu5_state_q : out std_ulogic_vector(0 to 3); +tlb_req_dbg_ierat_inptr_q : out std_ulogic_vector(0 to 1); +tlb_req_dbg_ierat_outptr_q : out std_ulogic_vector(0 to 1); +tlb_req_dbg_ierat_req_valid_q : out std_ulogic_vector(0 to 3); +tlb_req_dbg_ierat_req_nonspec_q : out std_ulogic_vector(0 to 3); +tlb_req_dbg_ierat_req_thdid : out std_ulogic_vector(0 to 7); +tlb_req_dbg_ierat_req_dup_q : out std_ulogic_vector(0 to 3); +tlb_req_dbg_derat_ex6_valid_q : out std_ulogic; +tlb_req_dbg_derat_ex6_thdid : out std_ulogic_vector(0 to 1); +tlb_req_dbg_derat_ex6_state_q : out std_ulogic_vector(0 to 3); +tlb_req_dbg_derat_inptr_q : out std_ulogic_vector(0 to 1); +tlb_req_dbg_derat_outptr_q : out std_ulogic_vector(0 to 1); +tlb_req_dbg_derat_req_valid_q : out std_ulogic_vector(0 to 3); +tlb_req_dbg_derat_req_thdid : out std_ulogic_vector(0 to 7); +tlb_req_dbg_derat_req_ttype_q : out std_ulogic_vector(0 to 7); +tlb_req_dbg_derat_req_dup_q : out std_ulogic_vector(0 to 3) + +); +end mmq_tlb_req; +architecture mmq_tlb_req of mmq_tlb_req is +constant MMU_Mode_Value : std_ulogic := '0'; +constant TlbSel_Tlb : std_ulogic_vector(0 to 1) := "00"; +constant TlbSel_IErat : std_ulogic_vector(0 to 1) := "10"; +constant TlbSel_DErat : std_ulogic_vector(0 to 1) := "11"; +constant ierat_req0_valid_offset : natural := 0; +constant ierat_req0_nonspec_offset : natural := ierat_req0_valid_offset + 1; +constant ierat_req0_thdid_offset : natural := ierat_req0_nonspec_offset + 1; +constant ierat_req0_epn_offset : natural := ierat_req0_thdid_offset + thdid_width; +constant ierat_req0_state_offset : natural := ierat_req0_epn_offset + req_epn_width; +constant ierat_req0_pid_offset : natural := ierat_req0_state_offset + state_width; +constant ierat_req0_dup_offset : natural := ierat_req0_pid_offset + pid_width; +constant ierat_req1_valid_offset : natural := ierat_req0_dup_offset + 2; +constant ierat_req1_nonspec_offset : natural := ierat_req1_valid_offset + 1; +constant ierat_req1_thdid_offset : natural := ierat_req1_nonspec_offset + 1; +constant ierat_req1_epn_offset : natural := ierat_req1_thdid_offset + thdid_width; +constant ierat_req1_state_offset : natural := ierat_req1_epn_offset + req_epn_width; +constant ierat_req1_pid_offset : natural := ierat_req1_state_offset + state_width; +constant ierat_req1_dup_offset : natural := ierat_req1_pid_offset + pid_width; +constant ierat_req2_valid_offset : natural := ierat_req1_dup_offset + 2; +constant ierat_req2_nonspec_offset : natural := ierat_req2_valid_offset + 1; +constant ierat_req2_thdid_offset : natural := ierat_req2_nonspec_offset + 1; +constant ierat_req2_epn_offset : natural := ierat_req2_thdid_offset + thdid_width; +constant ierat_req2_state_offset : natural := ierat_req2_epn_offset + req_epn_width; +constant ierat_req2_pid_offset : natural := ierat_req2_state_offset + state_width; +constant ierat_req2_dup_offset : natural := ierat_req2_pid_offset + pid_width; +constant ierat_req3_valid_offset : natural := ierat_req2_dup_offset + 2; +constant ierat_req3_nonspec_offset : natural := ierat_req3_valid_offset + 1; +constant ierat_req3_thdid_offset : natural := ierat_req3_nonspec_offset + 1; +constant ierat_req3_epn_offset : natural := ierat_req3_thdid_offset + thdid_width; +constant ierat_req3_state_offset : natural := ierat_req3_epn_offset + req_epn_width; +constant ierat_req3_pid_offset : natural := ierat_req3_state_offset + state_width; +constant ierat_req3_dup_offset : natural := ierat_req3_pid_offset + pid_width; +constant ierat_inptr_offset : natural := ierat_req3_dup_offset + 2; +constant ierat_outptr_offset : natural := ierat_inptr_offset + 2; +constant tlb_seq_ierat_req_offset : natural := ierat_outptr_offset + 2; +constant ierat_iu3_flush_offset : natural := tlb_seq_ierat_req_offset + 1; +constant xu_mm_ierat_flush_offset : natural := ierat_iu3_flush_offset + thdid_width; +constant xu_mm_ierat_miss_offset : natural := xu_mm_ierat_flush_offset + thdid_width; +constant ierat_iu3_valid_offset : natural := xu_mm_ierat_miss_offset + thdid_width; +constant ierat_iu3_thdid_offset : natural := ierat_iu3_valid_offset + 1; +constant ierat_iu3_epn_offset : natural := ierat_iu3_thdid_offset + thdid_width; +constant ierat_iu3_state_offset : natural := ierat_iu3_epn_offset + req_epn_width; +constant ierat_iu3_pid_offset : natural := ierat_iu3_state_offset + state_width; +constant ierat_iu4_valid_offset : natural := ierat_iu3_pid_offset + pid_width; +constant ierat_iu4_thdid_offset : natural := ierat_iu4_valid_offset + 1; +constant ierat_iu4_epn_offset : natural := ierat_iu4_thdid_offset + thdid_width; +constant ierat_iu4_state_offset : natural := ierat_iu4_epn_offset + req_epn_width; +constant ierat_iu4_pid_offset : natural := ierat_iu4_state_offset + state_width; +constant ierat_iu5_valid_offset : natural := ierat_iu4_pid_offset + pid_width; +constant ierat_iu5_thdid_offset : natural := ierat_iu5_valid_offset + 1; +constant ierat_iu5_epn_offset : natural := ierat_iu5_thdid_offset + thdid_width; +constant ierat_iu5_state_offset : natural := ierat_iu5_epn_offset + req_epn_width; +constant ierat_iu5_pid_offset : natural := ierat_iu5_state_offset + state_width; +constant derat_req0_valid_offset : natural := ierat_iu5_pid_offset + pid_width; +constant derat_req0_thdid_offset : natural := derat_req0_valid_offset + 1; +constant derat_req0_epn_offset : natural := derat_req0_thdid_offset + thdid_width; +constant derat_req0_state_offset : natural := derat_req0_epn_offset + req_epn_width; +constant derat_req0_ttype_offset : natural := derat_req0_state_offset + state_width; +constant derat_req0_pid_offset : natural := derat_req0_ttype_offset + 2; +constant derat_req0_lpid_offset : natural := derat_req0_pid_offset + pid_width; +constant derat_req0_dup_offset : natural := derat_req0_lpid_offset + lpid_width; +constant derat_req1_valid_offset : natural := derat_req0_dup_offset + 2; +constant derat_req1_thdid_offset : natural := derat_req1_valid_offset + 1; +constant derat_req1_epn_offset : natural := derat_req1_thdid_offset + thdid_width; +constant derat_req1_state_offset : natural := derat_req1_epn_offset + req_epn_width; +constant derat_req1_ttype_offset : natural := derat_req1_state_offset + state_width; +constant derat_req1_pid_offset : natural := derat_req1_ttype_offset + 2; +constant derat_req1_lpid_offset : natural := derat_req1_pid_offset + pid_width; +constant derat_req1_dup_offset : natural := derat_req1_lpid_offset + lpid_width; +constant derat_req2_valid_offset : natural := derat_req1_dup_offset + 2; +constant derat_req2_thdid_offset : natural := derat_req2_valid_offset + 1; +constant derat_req2_epn_offset : natural := derat_req2_thdid_offset + thdid_width; +constant derat_req2_state_offset : natural := derat_req2_epn_offset + req_epn_width; +constant derat_req2_ttype_offset : natural := derat_req2_state_offset + state_width; +constant derat_req2_pid_offset : natural := derat_req2_ttype_offset + 2; +constant derat_req2_lpid_offset : natural := derat_req2_pid_offset + pid_width; +constant derat_req2_dup_offset : natural := derat_req2_lpid_offset + lpid_width; +constant derat_req3_valid_offset : natural := derat_req2_dup_offset + 2; +constant derat_req3_thdid_offset : natural := derat_req3_valid_offset + 1; +constant derat_req3_epn_offset : natural := derat_req3_thdid_offset + thdid_width; +constant derat_req3_state_offset : natural := derat_req3_epn_offset + req_epn_width; +constant derat_req3_ttype_offset : natural := derat_req3_state_offset + state_width; +constant derat_req3_pid_offset : natural := derat_req3_ttype_offset + 2; +constant derat_req3_lpid_offset : natural := derat_req3_pid_offset + pid_width; +constant derat_req3_dup_offset : natural := derat_req3_lpid_offset + lpid_width; +constant derat_inptr_offset : natural := derat_req3_dup_offset + 2; +constant derat_outptr_offset : natural := derat_inptr_offset + 2; +constant tlb_seq_derat_req_offset : natural := derat_outptr_offset + 2; +constant derat_ex4_valid_offset : natural := tlb_seq_derat_req_offset + 1; +constant derat_ex4_thdid_offset : natural := derat_ex4_valid_offset + 1; +constant derat_ex4_epn_offset : natural := derat_ex4_thdid_offset + thdid_width; +constant derat_ex4_state_offset : natural := derat_ex4_epn_offset + req_epn_width; +constant derat_ex4_ttype_offset : natural := derat_ex4_state_offset + state_width; +constant derat_ex4_pid_offset : natural := derat_ex4_ttype_offset + 2; +constant derat_ex4_lpid_offset : natural := derat_ex4_pid_offset + pid_width; +constant derat_ex5_valid_offset : natural := derat_ex4_lpid_offset + lpid_width; +constant derat_ex5_thdid_offset : natural := derat_ex5_valid_offset + 1; +constant derat_ex5_epn_offset : natural := derat_ex5_thdid_offset + thdid_width; +constant derat_ex5_state_offset : natural := derat_ex5_epn_offset + req_epn_width; +constant derat_ex5_ttype_offset : natural := derat_ex5_state_offset + state_width; +constant derat_ex5_pid_offset : natural := derat_ex5_ttype_offset + 2; +constant derat_ex5_lpid_offset : natural := derat_ex5_pid_offset + pid_width; +constant derat_ex6_valid_offset : natural := derat_ex5_lpid_offset + lpid_width; +constant derat_ex6_thdid_offset : natural := derat_ex6_valid_offset + 1; +constant derat_ex6_epn_offset : natural := derat_ex6_thdid_offset + thdid_width; +constant derat_ex6_state_offset : natural := derat_ex6_epn_offset + req_epn_width; +constant derat_ex6_ttype_offset : natural := derat_ex6_state_offset + state_width; +constant derat_ex6_pid_offset : natural := derat_ex6_ttype_offset + 2; +constant derat_ex6_lpid_offset : natural := derat_ex6_pid_offset + pid_width; +constant spare_offset : natural := derat_ex6_lpid_offset + lpid_width; +constant scan_right : natural := spare_offset + 32 -1; +signal ierat_req0_valid_d, ierat_req0_valid_q : std_ulogic; +signal ierat_req0_nonspec_d, ierat_req0_nonspec_q : std_ulogic; +signal ierat_req0_thdid_d, ierat_req0_thdid_q : std_ulogic_vector(0 to thdid_width-1); +signal ierat_req0_epn_d, ierat_req0_epn_q : std_ulogic_vector(0 to req_epn_width-1); +signal ierat_req0_state_d, ierat_req0_state_q : std_ulogic_vector(0 to state_width-1); +signal ierat_req0_pid_d, ierat_req0_pid_q : std_ulogic_vector(0 to pid_width-1); +signal ierat_req0_dup_d, ierat_req0_dup_q : std_ulogic_vector(0 to 1); +signal ierat_req1_valid_d, ierat_req1_valid_q : std_ulogic; +signal ierat_req1_nonspec_d, ierat_req1_nonspec_q : std_ulogic; +signal ierat_req1_thdid_d, ierat_req1_thdid_q : std_ulogic_vector(0 to thdid_width-1); +signal ierat_req1_epn_d, ierat_req1_epn_q : std_ulogic_vector(0 to req_epn_width-1); +signal ierat_req1_state_d, ierat_req1_state_q : std_ulogic_vector(0 to state_width-1); +signal ierat_req1_pid_d, ierat_req1_pid_q : std_ulogic_vector(0 to pid_width-1); +signal ierat_req1_dup_d, ierat_req1_dup_q : std_ulogic_vector(0 to 1); +signal ierat_req2_valid_d, ierat_req2_valid_q : std_ulogic; +signal ierat_req2_nonspec_d, ierat_req2_nonspec_q : std_ulogic; +signal ierat_req2_thdid_d, ierat_req2_thdid_q : std_ulogic_vector(0 to thdid_width-1); +signal ierat_req2_epn_d, ierat_req2_epn_q : std_ulogic_vector(0 to req_epn_width-1); +signal ierat_req2_state_d, ierat_req2_state_q : std_ulogic_vector(0 to state_width-1); +signal ierat_req2_pid_d, ierat_req2_pid_q : std_ulogic_vector(0 to pid_width-1); +signal ierat_req2_dup_d, ierat_req2_dup_q : std_ulogic_vector(0 to 1); +signal ierat_req3_valid_d, ierat_req3_valid_q : std_ulogic; +signal ierat_req3_nonspec_d, ierat_req3_nonspec_q : std_ulogic; +signal ierat_req3_thdid_d, ierat_req3_thdid_q : std_ulogic_vector(0 to thdid_width-1); +signal ierat_req3_epn_d, ierat_req3_epn_q : std_ulogic_vector(0 to req_epn_width-1); +signal ierat_req3_state_d, ierat_req3_state_q : std_ulogic_vector(0 to state_width-1); +signal ierat_req3_pid_d, ierat_req3_pid_q : std_ulogic_vector(0 to pid_width-1); +signal ierat_req3_dup_d, ierat_req3_dup_q : std_ulogic_vector(0 to 1); +signal ierat_iu3_valid_d, ierat_iu3_valid_q : std_ulogic; +signal ierat_iu3_thdid_d, ierat_iu3_thdid_q : std_ulogic_vector(0 to thdid_width-1); +signal ierat_iu3_epn_d, ierat_iu3_epn_q : std_ulogic_vector(0 to req_epn_width-1); +signal ierat_iu3_state_d, ierat_iu3_state_q : std_ulogic_vector(0 to state_width-1); +signal ierat_iu3_pid_d, ierat_iu3_pid_q : std_ulogic_vector(0 to pid_width-1); +signal ierat_iu4_valid_d, ierat_iu4_valid_q : std_ulogic; +signal ierat_iu4_thdid_d, ierat_iu4_thdid_q : std_ulogic_vector(0 to thdid_width-1); +signal ierat_iu4_epn_d, ierat_iu4_epn_q : std_ulogic_vector(0 to req_epn_width-1); +signal ierat_iu4_state_d, ierat_iu4_state_q : std_ulogic_vector(0 to state_width-1); +signal ierat_iu4_pid_d, ierat_iu4_pid_q : std_ulogic_vector(0 to pid_width-1); +signal ierat_iu5_valid_d, ierat_iu5_valid_q : std_ulogic; +signal ierat_iu5_thdid_d, ierat_iu5_thdid_q : std_ulogic_vector(0 to thdid_width-1); +signal ierat_iu5_epn_d, ierat_iu5_epn_q : std_ulogic_vector(0 to req_epn_width-1); +signal ierat_iu5_state_d, ierat_iu5_state_q : std_ulogic_vector(0 to state_width-1); +signal ierat_iu5_pid_d, ierat_iu5_pid_q : std_ulogic_vector(0 to pid_width-1); +signal ierat_iu3_flush_d, ierat_iu3_flush_q : std_ulogic_vector(0 to thdid_width-1); +signal xu_mm_ierat_flush_d, xu_mm_ierat_flush_q : std_ulogic_vector(0 to thdid_width-1); +signal xu_mm_ierat_miss_d, xu_mm_ierat_miss_q : std_ulogic_vector(0 to thdid_width-1); +signal ierat_inptr_d, ierat_inptr_q : std_ulogic_vector(0 to 1); +signal ierat_outptr_d, ierat_outptr_q : std_ulogic_vector(0 to 1); +signal tlb_seq_ierat_req_d, tlb_seq_ierat_req_q : std_ulogic; +signal derat_req0_valid_d, derat_req0_valid_q : std_ulogic; +signal derat_req0_thdid_d, derat_req0_thdid_q : std_ulogic_vector(0 to thdid_width-1); +signal derat_req0_epn_d, derat_req0_epn_q : std_ulogic_vector(0 to req_epn_width-1); +signal derat_req0_state_d, derat_req0_state_q : std_ulogic_vector(0 to state_width-1); +signal derat_req0_ttype_d, derat_req0_ttype_q : std_ulogic_vector(0 to 1); +signal derat_req0_pid_d, derat_req0_pid_q : std_ulogic_vector(0 to pid_width-1); +signal derat_req0_lpid_d, derat_req0_lpid_q : std_ulogic_vector(0 to lpid_width-1); +signal derat_req0_dup_d, derat_req0_dup_q : std_ulogic_vector(0 to 1); +signal derat_req1_valid_d, derat_req1_valid_q : std_ulogic; +signal derat_req1_thdid_d, derat_req1_thdid_q : std_ulogic_vector(0 to thdid_width-1); +signal derat_req1_epn_d, derat_req1_epn_q : std_ulogic_vector(0 to req_epn_width-1); +signal derat_req1_state_d, derat_req1_state_q : std_ulogic_vector(0 to state_width-1); +signal derat_req1_ttype_d, derat_req1_ttype_q : std_ulogic_vector(0 to 1); +signal derat_req1_pid_d, derat_req1_pid_q : std_ulogic_vector(0 to pid_width-1); +signal derat_req1_lpid_d, derat_req1_lpid_q : std_ulogic_vector(0 to lpid_width-1); +signal derat_req1_dup_d, derat_req1_dup_q : std_ulogic_vector(0 to 1); +signal derat_req2_valid_d, derat_req2_valid_q : std_ulogic; +signal derat_req2_thdid_d, derat_req2_thdid_q : std_ulogic_vector(0 to thdid_width-1); +signal derat_req2_epn_d, derat_req2_epn_q : std_ulogic_vector(0 to req_epn_width-1); +signal derat_req2_state_d, derat_req2_state_q : std_ulogic_vector(0 to state_width-1); +signal derat_req2_ttype_d, derat_req2_ttype_q : std_ulogic_vector(0 to 1); +signal derat_req2_pid_d, derat_req2_pid_q : std_ulogic_vector(0 to pid_width-1); +signal derat_req2_lpid_d, derat_req2_lpid_q : std_ulogic_vector(0 to lpid_width-1); +signal derat_req2_dup_d, derat_req2_dup_q : std_ulogic_vector(0 to 1); +signal derat_req3_valid_d, derat_req3_valid_q : std_ulogic; +signal derat_req3_thdid_d, derat_req3_thdid_q : std_ulogic_vector(0 to thdid_width-1); +signal derat_req3_epn_d, derat_req3_epn_q : std_ulogic_vector(0 to req_epn_width-1); +signal derat_req3_state_d, derat_req3_state_q : std_ulogic_vector(0 to state_width-1); +signal derat_req3_ttype_d, derat_req3_ttype_q : std_ulogic_vector(0 to 1); +signal derat_req3_pid_d, derat_req3_pid_q : std_ulogic_vector(0 to pid_width-1); +signal derat_req3_lpid_d, derat_req3_lpid_q : std_ulogic_vector(0 to lpid_width-1); +signal derat_req3_dup_d, derat_req3_dup_q : std_ulogic_vector(0 to 1); +signal derat_ex4_valid_d, derat_ex4_valid_q : std_ulogic; +signal derat_ex4_thdid_d, derat_ex4_thdid_q : std_ulogic_vector(0 to thdid_width-1); +signal derat_ex4_epn_d, derat_ex4_epn_q : std_ulogic_vector(0 to req_epn_width-1); +signal derat_ex4_state_d, derat_ex4_state_q : std_ulogic_vector(0 to state_width-1); +signal derat_ex4_ttype_d, derat_ex4_ttype_q : std_ulogic_vector(0 to 1); +signal derat_ex4_pid_d, derat_ex4_pid_q : std_ulogic_vector(0 to pid_width-1); +signal derat_ex4_lpid_d, derat_ex4_lpid_q : std_ulogic_vector(0 to lpid_width-1); +signal derat_ex5_valid_d, derat_ex5_valid_q : std_ulogic; +signal derat_ex5_thdid_d, derat_ex5_thdid_q : std_ulogic_vector(0 to thdid_width-1); +signal derat_ex5_epn_d, derat_ex5_epn_q : std_ulogic_vector(0 to req_epn_width-1); +signal derat_ex5_state_d, derat_ex5_state_q : std_ulogic_vector(0 to state_width-1); +signal derat_ex5_ttype_d, derat_ex5_ttype_q : std_ulogic_vector(0 to 1); +signal derat_ex5_pid_d, derat_ex5_pid_q : std_ulogic_vector(0 to pid_width-1); +signal derat_ex5_lpid_d, derat_ex5_lpid_q : std_ulogic_vector(0 to lpid_width-1); +signal derat_ex6_valid_d, derat_ex6_valid_q : std_ulogic; +signal derat_ex6_thdid_d, derat_ex6_thdid_q : std_ulogic_vector(0 to thdid_width-1); +signal derat_ex6_epn_d, derat_ex6_epn_q : std_ulogic_vector(0 to req_epn_width-1); +signal derat_ex6_state_d, derat_ex6_state_q : std_ulogic_vector(0 to state_width-1); +signal derat_ex6_ttype_d, derat_ex6_ttype_q : std_ulogic_vector(0 to 1); +signal derat_ex6_pid_d, derat_ex6_pid_q : std_ulogic_vector(0 to pid_width-1); +signal derat_ex6_lpid_d, derat_ex6_lpid_q : std_ulogic_vector(0 to lpid_width-1); +signal derat_inptr_d, derat_inptr_q : std_ulogic_vector(0 to 1); +signal derat_outptr_d, derat_outptr_q : std_ulogic_vector(0 to 1); +signal tlb_seq_derat_req_d, tlb_seq_derat_req_q : std_ulogic; +signal spare_q : std_ulogic_vector(0 to 31); +signal ierat_req_pid_mux : std_ulogic_vector(0 to pid_width-1); +signal tlb_req_quiesce_b : std_ulogic_vector(0 to thdid_width-1); +signal unused_dc : std_ulogic_vector(0 to 12); +-- synopsys translate_off +-- synopsys translate_on +signal pc_sg_1 : std_ulogic; +signal pc_sg_0 : std_ulogic; +signal pc_func_sl_thold_1 : std_ulogic; +signal pc_func_sl_thold_0 : std_ulogic; +signal pc_func_sl_thold_0_b : std_ulogic; +signal pc_func_slp_sl_thold_1 : std_ulogic; +signal pc_func_slp_sl_thold_0 : std_ulogic; +signal pc_func_slp_sl_thold_0_b : std_ulogic; +signal pc_func_sl_force : std_ulogic; +signal pc_func_slp_sl_force : std_ulogic; +signal siv : std_ulogic_vector(0 to scan_right); +signal sov : std_ulogic_vector(0 to scan_right); +begin +tlb_req_quiesce_b(0 to thdid_width-1) <= + ( (0 to thdid_width-1 => ierat_req0_valid_q) and ierat_req0_thdid_q(0 to thdid_width-1) ) or + ( (0 to thdid_width-1 => ierat_req1_valid_q) and ierat_req1_thdid_q(0 to thdid_width-1) ) or + ( (0 to thdid_width-1 => ierat_req2_valid_q) and ierat_req2_thdid_q(0 to thdid_width-1) ) or + ( (0 to thdid_width-1 => ierat_req3_valid_q) and ierat_req3_thdid_q(0 to thdid_width-1) ) or + ( (0 to thdid_width-1 => derat_req0_valid_q) and derat_req0_thdid_q(0 to thdid_width-1) ) or + ( (0 to thdid_width-1 => derat_req1_valid_q) and derat_req1_thdid_q(0 to thdid_width-1) ) or + ( (0 to thdid_width-1 => derat_req2_valid_q) and derat_req2_thdid_q(0 to thdid_width-1) ) or + ( (0 to thdid_width-1 => derat_req3_valid_q) and derat_req3_thdid_q(0 to thdid_width-1) ) or + ( (0 to thdid_width-1 => derat_ex4_valid_q) and derat_ex4_thdid_q(0 to thdid_width-1) ) or + ( (0 to thdid_width-1 => derat_ex5_valid_q) and derat_ex5_thdid_q(0 to thdid_width-1) ) or + ( (0 to thdid_width-1 => derat_ex6_valid_q) and derat_ex6_thdid_q(0 to thdid_width-1) ) or + ( (0 to thdid_width-1 => ierat_iu3_valid_q) and ierat_iu3_thdid_q(0 to thdid_width-1) ) or + ( (0 to thdid_width-1 => ierat_iu4_valid_q) and ierat_iu4_thdid_q(0 to thdid_width-1) ) or + ( (0 to thdid_width-1 => ierat_iu5_valid_q) and ierat_iu5_thdid_q(0 to thdid_width-1) ); +tlb_req_quiesce <= not tlb_req_quiesce_b; +xu_mm_ierat_flush_d <= xu_mm_ierat_flush; +xu_mm_ierat_miss_d <= xu_mm_ierat_miss; +ierat_iu3_flush_d <= iu_mm_ierat_flush; +ierat_iu3_valid_d <= iu_mm_ierat_req; +ierat_iu4_valid_d <= '1' when (ierat_iu3_valid_q='1' and or_reduce(ierat_iu3_thdid_q and not(ierat_iu3_flush_q) and not(xu_mm_ierat_flush_q))='1') + else '0'; +ierat_iu5_valid_d <= '1' when (ierat_iu4_valid_q='1' and or_reduce(ierat_iu4_thdid_q and not(ierat_iu3_flush_q) and not(xu_mm_ierat_flush_q))='1') + else '0'; +ierat_iu3_thdid_d <= iu_mm_ierat_thdid; +ierat_iu3_state_d <= iu_mm_ierat_state; +ierat_iu3_pid_d <= iu_mm_ierat_tid; +gen64_iu3_epn: if rs_data_width = 64 generate +ierat_iu3_epn_d <= iu_mm_ierat_epn; +end generate gen64_iu3_epn; +gen32_iu3_epn: if rs_data_width < 64 generate +ierat_iu3_epn_d <= (0 to 64-rs_data_width-1 => '0') & iu_mm_ierat_epn(64-rs_data_width to 51); +end generate gen32_iu3_epn; +ierat_iu4_thdid_d <= ierat_iu3_thdid_q; +ierat_iu4_epn_d <= ierat_iu3_epn_q; +ierat_iu4_state_d <= ierat_iu3_state_q; +ierat_iu4_pid_d <= ierat_iu3_pid_q; +ierat_iu5_thdid_d <= ierat_iu4_thdid_q; +ierat_iu5_epn_d <= ierat_iu4_epn_q; +ierat_iu5_state_d <= ierat_iu4_state_q; +ierat_iu5_pid_d <= ierat_iu4_pid_q; +ierat_inptr_d <= "00" when ierat_req0_valid_q='1' and ierat_req0_nonspec_q='0' and or_reduce(ierat_req0_thdid_q and (ierat_iu3_flush_q or xu_mm_ierat_flush_q))='1' + else "01" when ierat_req1_valid_q='1' and ierat_req1_nonspec_q='0' and or_reduce(ierat_req1_thdid_q and (ierat_iu3_flush_q or xu_mm_ierat_flush_q))='1' + else "10" when ierat_req2_valid_q='1' and ierat_req2_nonspec_q='0' and or_reduce(ierat_req2_thdid_q and (ierat_iu3_flush_q or xu_mm_ierat_flush_q))='1' + else "11" when ierat_req3_valid_q='1' and ierat_req3_nonspec_q='0' and or_reduce(ierat_req3_thdid_q and (ierat_iu3_flush_q or xu_mm_ierat_flush_q))='1' + else "01" when ierat_inptr_q="00" and ierat_req1_valid_q='0' and ierat_iu5_valid_q='1' and or_reduce(ierat_iu5_thdid_q and not(ierat_iu3_flush_q) and not(xu_mm_ierat_flush_q))='1' + else "10" when ierat_inptr_q="00" and ierat_req2_valid_q='0' and ierat_iu5_valid_q='1' and or_reduce(ierat_iu5_thdid_q and not(ierat_iu3_flush_q) and not(xu_mm_ierat_flush_q))='1' + else "11" when ierat_inptr_q="00" and ierat_req3_valid_q='0' and ierat_iu5_valid_q='1' and or_reduce(ierat_iu5_thdid_q and not(ierat_iu3_flush_q) and not(xu_mm_ierat_flush_q))='1' + else "10" when ierat_inptr_q="01" and ierat_req2_valid_q='0' and ierat_iu5_valid_q='1' and or_reduce(ierat_iu5_thdid_q and not(ierat_iu3_flush_q) and not(xu_mm_ierat_flush_q))='1' + else "11" when ierat_inptr_q="01" and ierat_req3_valid_q='0' and ierat_iu5_valid_q='1' and or_reduce(ierat_iu5_thdid_q and not(ierat_iu3_flush_q) and not(xu_mm_ierat_flush_q))='1' + else "00" when ierat_inptr_q="01" and ierat_req0_valid_q='0' and ierat_iu5_valid_q='1' and or_reduce(ierat_iu5_thdid_q and not(ierat_iu3_flush_q) and not(xu_mm_ierat_flush_q))='1' + else "11" when ierat_inptr_q="10" and ierat_req3_valid_q='0' and ierat_iu5_valid_q='1' and or_reduce(ierat_iu5_thdid_q and not(ierat_iu3_flush_q) and not(xu_mm_ierat_flush_q))='1' + else "00" when ierat_inptr_q="10" and ierat_req0_valid_q='0' and ierat_iu5_valid_q='1' and or_reduce(ierat_iu5_thdid_q and not(ierat_iu3_flush_q) and not(xu_mm_ierat_flush_q))='1' + else "01" when ierat_inptr_q="10" and ierat_req1_valid_q='0' and ierat_iu5_valid_q='1' and or_reduce(ierat_iu5_thdid_q and not(ierat_iu3_flush_q) and not(xu_mm_ierat_flush_q))='1' + else "00" when ierat_inptr_q="11" and ierat_req0_valid_q='0' and ierat_iu5_valid_q='1' and or_reduce(ierat_iu5_thdid_q and not(ierat_iu3_flush_q) and not(xu_mm_ierat_flush_q))='1' + else "01" when ierat_inptr_q="11" and ierat_req1_valid_q='0' and ierat_iu5_valid_q='1' and or_reduce(ierat_iu5_thdid_q and not(ierat_iu3_flush_q) and not(xu_mm_ierat_flush_q))='1' + else "10" when ierat_inptr_q="11" and ierat_req2_valid_q='0' and ierat_iu5_valid_q='1' and or_reduce(ierat_iu5_thdid_q and not(ierat_iu3_flush_q) and not(xu_mm_ierat_flush_q))='1' + else ierat_outptr_q when ierat_req_taken='1' + else ierat_inptr_q; +ierat_outptr_d <= "01" when ierat_outptr_q="00" and ierat_req0_valid_q='1' and ierat_req_taken='1' + else "10" when ierat_outptr_q="01" and ierat_req1_valid_q='1' and ierat_req_taken='1' + else "11" when ierat_outptr_q="10" and ierat_req2_valid_q='1' and ierat_req_taken='1' + else "00" when ierat_outptr_q="11" and ierat_req3_valid_q='1' and ierat_req_taken='1' + else "01" when ierat_outptr_q="00" and ierat_req0_valid_q='0' and ierat_req1_valid_q='1' + else "10" when ierat_outptr_q="00" and ierat_req0_valid_q='0' and ierat_req1_valid_q='0' and ierat_req2_valid_q='1' + else "11" when ierat_outptr_q="00" and ierat_req0_valid_q='0' and ierat_req1_valid_q='0' and ierat_req2_valid_q='0' and ierat_req3_valid_q='1' + else "10" when ierat_outptr_q="01" and ierat_req1_valid_q='0' and ierat_req2_valid_q='1' + else "11" when ierat_outptr_q="01" and ierat_req1_valid_q='0' and ierat_req2_valid_q='0' and ierat_req3_valid_q='1' + else "00" when ierat_outptr_q="01" and ierat_req1_valid_q='0' and ierat_req2_valid_q='0' and ierat_req3_valid_q='0' and ierat_req0_valid_q='1' + else "11" when ierat_outptr_q="10" and ierat_req2_valid_q='0' and ierat_req3_valid_q='1' + else "00" when ierat_outptr_q="10" and ierat_req2_valid_q='0' and ierat_req3_valid_q='0' and ierat_req0_valid_q='1' + else "01" when ierat_outptr_q="10" and ierat_req2_valid_q='0' and ierat_req3_valid_q='0' and ierat_req0_valid_q='0' and ierat_req1_valid_q='1' + else "00" when ierat_outptr_q="11" and ierat_req3_valid_q='0' and ierat_req0_valid_q='1' + else "01" when ierat_outptr_q="11" and ierat_req3_valid_q='0' and ierat_req0_valid_q='0' and ierat_req1_valid_q='1' + else "10" when ierat_outptr_q="11" and ierat_req3_valid_q='0' and ierat_req0_valid_q='0' and ierat_req1_valid_q='0' and ierat_req2_valid_q='1' + else ierat_outptr_q; +tlb_seq_ierat_req_d <= '1' when ((ierat_outptr_q="00" and ierat_req0_valid_q='1' and ierat_req0_nonspec_q='1' and or_reduce(ierat_req0_thdid_q and not(xu_mm_ierat_flush_q))='1') or + (ierat_outptr_q="01" and ierat_req1_valid_q='1' and ierat_req1_nonspec_q='1' and or_reduce(ierat_req1_thdid_q and not(xu_mm_ierat_flush_q))='1') or + (ierat_outptr_q="10" and ierat_req2_valid_q='1' and ierat_req2_nonspec_q='1' and or_reduce(ierat_req2_thdid_q and not(xu_mm_ierat_flush_q))='1') or + (ierat_outptr_q="11" and ierat_req3_valid_q='1' and ierat_req3_nonspec_q='1' and or_reduce(ierat_req3_thdid_q and not(xu_mm_ierat_flush_q))='1')) + else '0'; +tlb_seq_ierat_req <= tlb_seq_ierat_req_q; +ierat_req0_valid_d <= '1' when (ierat_iu5_valid_q='1' and or_reduce(ierat_iu5_thdid_q and not(ierat_iu3_flush_q) and not(xu_mm_ierat_flush_q))='1' + and ierat_req0_valid_q='0' and ierat_inptr_q="00") + else '0' when (ierat_req0_valid_q='1' and ierat_req0_nonspec_q='0' and or_reduce(ierat_req0_thdid_q and xu_mm_ierat_flush_q)='1') + else '0' when (ierat_req0_valid_q='1' and ierat_req0_nonspec_q='0' and or_reduce(ierat_req0_thdid_q and ierat_iu3_flush_q)='1') + else '0' when (ierat_req_taken='1' and ierat_req0_valid_q='1' and ierat_req0_nonspec_q='1' and ierat_outptr_q="00") + else '0' when (ierat_req0_nonspec_q='1' and tlb_cmp_ierat_dup_val(0)='1' and tlb_cmp_ierat_dup_val(4)='1') + else ierat_req0_valid_q; +ierat_req0_nonspec_d <= '1' when (ierat_req0_valid_q='1' and ierat_req0_nonspec_q='0' + and or_reduce(ierat_req0_thdid_q and xu_mm_ierat_miss_q and not(xu_mm_ierat_flush_q))='1') + else '0' when (ierat_req0_valid_q='1' and or_reduce(ierat_req0_thdid_q and xu_mm_ierat_flush_q)='1') + else '0' when (ierat_req_taken='1' and ierat_req0_valid_q='1' and ierat_req0_nonspec_q='1' and ierat_outptr_q="00") + else '0' when (ierat_req0_nonspec_q='1' and tlb_cmp_ierat_dup_val(0)='1' and tlb_cmp_ierat_dup_val(4)='1') + else ierat_req0_nonspec_q; +ierat_req0_thdid_d(0 to 3) <= ierat_iu5_thdid_q when (ierat_iu5_valid_q='1' and ierat_req0_valid_q='0' and ierat_inptr_q="00") + else ierat_req0_thdid_q(0 to 3); +ierat_req0_epn_d <= ierat_iu5_epn_q when (ierat_iu5_valid_q='1' and ierat_req0_valid_q='0' and ierat_inptr_q="00") + else ierat_req0_epn_q; +ierat_req0_state_d <= ierat_iu5_state_q when (ierat_iu5_valid_q='1' and ierat_req0_valid_q='0' and ierat_inptr_q="00") + else ierat_req0_state_q; +ierat_req0_pid_d <= ierat_iu5_pid_q when (ierat_iu5_valid_q='1' and ierat_req0_valid_q='0' and ierat_inptr_q="00") + else ierat_req0_pid_q; +ierat_req0_dup_d(0) <= '0'; +ierat_req0_dup_d(1) <= '0' when (ierat_req_taken='1' and ierat_req0_valid_q='1' and ierat_outptr_q="00") + else tlb_cmp_ierat_dup_val(6) when (ierat_iu5_valid_q='1' and ierat_req0_valid_q='0' and ierat_inptr_q="00") + else tlb_cmp_ierat_dup_val(0) when (ierat_req0_valid_q='1' and ierat_req0_dup_q(1)='0' and tlb_cmp_ierat_dup_val(4)='0' and tlb_cmp_ierat_dup_val(5)='1') + else ierat_req0_dup_q(1); +ierat_req1_valid_d <= '1' when (ierat_iu5_valid_q='1' and or_reduce(ierat_iu5_thdid_q and not(ierat_iu3_flush_q) and not(xu_mm_ierat_flush_q))='1' + and ierat_req1_valid_q='0' and ierat_inptr_q="01") + else '0' when (ierat_req1_valid_q='1' and ierat_req1_nonspec_q='0' and or_reduce(ierat_req1_thdid_q and xu_mm_ierat_flush_q)='1') + else '0' when (ierat_req1_valid_q='1' and ierat_req1_nonspec_q='0' and or_reduce(ierat_req1_thdid_q and ierat_iu3_flush_q)='1') + else '0' when (ierat_req_taken='1' and ierat_req1_valid_q='1' and ierat_req1_nonspec_q='1' and ierat_outptr_q="01") + else '0' when (ierat_req1_nonspec_q='1' and tlb_cmp_ierat_dup_val(1)='1' and tlb_cmp_ierat_dup_val(4)='1') + else ierat_req1_valid_q; +ierat_req1_nonspec_d <= '1' when (ierat_req1_valid_q='1' and ierat_req1_nonspec_q='0' + and or_reduce(ierat_req1_thdid_q and xu_mm_ierat_miss_q and not(xu_mm_ierat_flush_q))='1') + else '0' when (ierat_req1_valid_q='1' and or_reduce(ierat_req1_thdid_q and xu_mm_ierat_flush_q)='1') + else '0' when (ierat_req_taken='1' and ierat_req1_valid_q='1' and ierat_req1_nonspec_q='1' and ierat_outptr_q="01") + else '0' when (ierat_req1_nonspec_q='1' and tlb_cmp_ierat_dup_val(1)='1' and tlb_cmp_ierat_dup_val(4)='1') + else ierat_req1_nonspec_q; +ierat_req1_thdid_d(0 to 3) <= ierat_iu5_thdid_q when (ierat_iu5_valid_q='1' and ierat_req1_valid_q='0' and ierat_inptr_q="01") + else ierat_req1_thdid_q(0 to 3); +ierat_req1_epn_d <= ierat_iu5_epn_q when (ierat_iu5_valid_q='1' and ierat_req1_valid_q='0' and ierat_inptr_q="01") + else ierat_req1_epn_q; +ierat_req1_state_d <= ierat_iu5_state_q when (ierat_iu5_valid_q='1' and ierat_req1_valid_q='0' and ierat_inptr_q="01") + else ierat_req1_state_q; +ierat_req1_pid_d <= ierat_iu5_pid_q when (ierat_iu5_valid_q='1' and ierat_req1_valid_q='0' and ierat_inptr_q="01") + else ierat_req1_pid_q; +ierat_req1_dup_d(0) <= '0'; +ierat_req1_dup_d(1) <= '0' when (ierat_req_taken='1' and ierat_req1_valid_q='1' and ierat_outptr_q="01") + else tlb_cmp_ierat_dup_val(6) when (ierat_iu5_valid_q='1' and ierat_req1_valid_q='0' and ierat_inptr_q="01") + else tlb_cmp_ierat_dup_val(1) when (ierat_req1_valid_q='1' and ierat_req1_dup_q(1)='0' and tlb_cmp_ierat_dup_val(4)='0' and tlb_cmp_ierat_dup_val(5)='1') + else ierat_req1_dup_q(1); +ierat_req2_valid_d <= '1' when (ierat_iu5_valid_q='1' and or_reduce(ierat_iu5_thdid_q and not(ierat_iu3_flush_q) and not(xu_mm_ierat_flush_q))='1' + and ierat_req2_valid_q='0' and ierat_inptr_q="10") + else '0' when (ierat_req2_valid_q='1' and ierat_req2_nonspec_q='0' and or_reduce(ierat_req2_thdid_q and xu_mm_ierat_flush_q)='1') + else '0' when (ierat_req2_valid_q='1' and ierat_req2_nonspec_q='0' and or_reduce(ierat_req2_thdid_q and ierat_iu3_flush_q)='1') + else '0' when (ierat_req_taken='1' and ierat_req2_valid_q='1' and ierat_req2_nonspec_q='1' and ierat_outptr_q="10") + else '0' when (ierat_req2_nonspec_q='1' and tlb_cmp_ierat_dup_val(2)='1' and tlb_cmp_ierat_dup_val(4)='1') + else ierat_req2_valid_q; +ierat_req2_nonspec_d <= '1' when (ierat_req2_valid_q='1' and ierat_req2_nonspec_q='0' + and or_reduce(ierat_req2_thdid_q and xu_mm_ierat_miss_q and not(xu_mm_ierat_flush_q))='1') + else '0' when (ierat_req2_valid_q='1' and or_reduce(ierat_req2_thdid_q and xu_mm_ierat_flush_q)='1') + else '0' when (ierat_req_taken='1' and ierat_req2_valid_q='1' and ierat_req2_nonspec_q='1' and ierat_outptr_q="10") + else '0' when (ierat_req2_nonspec_q='1' and tlb_cmp_ierat_dup_val(2)='1' and tlb_cmp_ierat_dup_val(4)='1') + else ierat_req2_nonspec_q; +ierat_req2_thdid_d(0 to 3) <= ierat_iu5_thdid_q when (ierat_iu5_valid_q='1' and ierat_req2_valid_q='0' and ierat_inptr_q="10") + else ierat_req2_thdid_q(0 to 3); +ierat_req2_epn_d <= ierat_iu5_epn_q when (ierat_iu5_valid_q='1' and ierat_req2_valid_q='0' and ierat_inptr_q="10") + else ierat_req2_epn_q; +ierat_req2_state_d <= ierat_iu5_state_q when (ierat_iu5_valid_q='1' and ierat_req2_valid_q='0' and ierat_inptr_q="10") + else ierat_req2_state_q; +ierat_req2_pid_d <= ierat_iu5_pid_q when (ierat_iu5_valid_q='1' and ierat_req2_valid_q='0' and ierat_inptr_q="10") + else ierat_req2_pid_q; +ierat_req2_dup_d(0) <= '0'; +ierat_req2_dup_d(1) <= '0' when (ierat_req_taken='1' and ierat_req2_valid_q='1' and ierat_outptr_q="10") + else tlb_cmp_ierat_dup_val(6) when (ierat_iu5_valid_q='1' and ierat_req2_valid_q='0' and ierat_inptr_q="10") + else tlb_cmp_ierat_dup_val(2) when (ierat_req2_valid_q='1' and ierat_req2_dup_q(1)='0' and tlb_cmp_ierat_dup_val(4)='0' and tlb_cmp_ierat_dup_val(5)='1') + else ierat_req2_dup_q(1); +ierat_req3_valid_d <= '1' when (ierat_iu5_valid_q='1' and or_reduce(ierat_iu5_thdid_q and not(ierat_iu3_flush_q) and not(xu_mm_ierat_flush_q))='1' + and ierat_req3_valid_q='0' and ierat_inptr_q="11") + else '0' when (ierat_req3_valid_q='1' and ierat_req3_nonspec_q='0' and or_reduce(ierat_req3_thdid_q and xu_mm_ierat_flush_q)='1') + else '0' when (ierat_req3_valid_q='1' and ierat_req3_nonspec_q='0' and or_reduce(ierat_req3_thdid_q and ierat_iu3_flush_q)='1') + else '0' when (ierat_req_taken='1' and ierat_req3_valid_q='1' and ierat_req3_nonspec_q='1' and ierat_outptr_q="11") + else '0' when (ierat_req3_nonspec_q='1' and tlb_cmp_ierat_dup_val(3)='1' and tlb_cmp_ierat_dup_val(4)='1') + else ierat_req3_valid_q; +ierat_req3_nonspec_d <= '1' when (ierat_req3_valid_q='1' and ierat_req3_nonspec_q='0' + and or_reduce(ierat_req3_thdid_q and xu_mm_ierat_miss_q and not(xu_mm_ierat_flush_q))='1') + else '0' when (ierat_req3_valid_q='1' and or_reduce(ierat_req3_thdid_q and xu_mm_ierat_flush_q)='1') + else '0' when (ierat_req_taken='1' and ierat_req3_valid_q='1' and ierat_req3_nonspec_q='1' and ierat_outptr_q="11") + else '0' when (ierat_req3_nonspec_q='1' and tlb_cmp_ierat_dup_val(3)='1' and tlb_cmp_ierat_dup_val(4)='1') + else ierat_req3_nonspec_q; +ierat_req3_thdid_d(0 to 3) <= ierat_iu5_thdid_q when (ierat_iu5_valid_q='1' and ierat_req3_valid_q='0' and ierat_inptr_q="11") + else ierat_req3_thdid_q(0 to 3); +ierat_req3_epn_d <= ierat_iu5_epn_q when (ierat_iu5_valid_q='1' and ierat_req3_valid_q='0' and ierat_inptr_q="11") + else ierat_req3_epn_q; +ierat_req3_state_d <= ierat_iu5_state_q when (ierat_iu5_valid_q='1' and ierat_req3_valid_q='0' and ierat_inptr_q="11") + else ierat_req3_state_q; +ierat_req3_pid_d <= ierat_iu5_pid_q when (ierat_iu5_valid_q='1' and ierat_req3_valid_q='0' and ierat_inptr_q="11") + else ierat_req3_pid_q; +ierat_req3_dup_d(0) <= '0'; +ierat_req3_dup_d(1) <= '0' when (ierat_req_taken='1' and ierat_req3_valid_q='1' and ierat_outptr_q="11") + else tlb_cmp_ierat_dup_val(6) when (ierat_iu5_valid_q='1' and ierat_req3_valid_q='0' and ierat_inptr_q="11") + else tlb_cmp_ierat_dup_val(3) when (ierat_req3_valid_q='1' and ierat_req3_dup_q(1)='0' and tlb_cmp_ierat_dup_val(4)='0' and tlb_cmp_ierat_dup_val(5)='1') + else ierat_req3_dup_q(1); +ierat_req_pid_mux <= pid1 when iu_mm_ierat_thdid(1)='1' + else pid2 when iu_mm_ierat_thdid(2)='1' + else pid3 when iu_mm_ierat_thdid(3)='1' + else pid0; +derat_ex4_valid_d <= '1' when (xu_mm_derat_req='1' and or_reduce(xu_mm_derat_thdid and not(xu_ex3_flush))='1') + else '0'; +derat_ex5_valid_d <= '1' when (derat_ex4_valid_q='1' and or_reduce(derat_ex4_thdid_q and not(xu_mm_ex4_flush))='1') + else '0'; +derat_ex6_valid_d <= '1' when (derat_ex5_valid_q='1' and or_reduce(derat_ex5_thdid_q and not(xu_mm_ex5_flush))='1') + else '0'; +gen64_ex4_epn: if rs_data_width = 64 generate +derat_ex4_epn_d <= xu_mm_derat_epn; +end generate gen64_ex4_epn; +gen32_ex4_epn: if rs_data_width < 64 generate +derat_ex4_epn_d <= (0 to 64-rs_data_width-1 => '0') & xu_mm_derat_epn(64-rs_data_width to 51); +end generate gen32_ex4_epn; +derat_ex4_thdid_d <= xu_mm_derat_thdid; +derat_ex4_state_d <= xu_mm_derat_state; +derat_ex4_ttype_d <= xu_mm_derat_ttype; +derat_ex4_pid_d <= xu_mm_derat_tid; +derat_ex4_lpid_d <= xu_mm_derat_lpid; +derat_ex5_thdid_d <= derat_ex4_thdid_q; +derat_ex5_epn_d <= derat_ex4_epn_q; +derat_ex5_state_d <= derat_ex4_state_q; +derat_ex5_ttype_d <= derat_ex4_ttype_q; +derat_ex5_pid_d <= derat_ex4_pid_q; +derat_ex6_thdid_d <= derat_ex5_thdid_q; +derat_ex6_epn_d <= derat_ex5_epn_q; +derat_ex6_state_d <= derat_ex5_state_q; +derat_ex6_ttype_d <= derat_ex5_ttype_q; +derat_ex6_pid_d <= derat_ex5_pid_q; +derat_ex5_lpid_d <= derat_ex4_lpid_q when derat_ex4_valid_q='1' and derat_ex4_ttype_q(0)='1' + else lpidr; +derat_ex6_lpid_d <= derat_ex5_lpid_q when derat_ex5_valid_q='1' and derat_ex5_ttype_q(0)='1' + else lpidr; +derat_inptr_d <= "01" when derat_inptr_q="00" and derat_req1_valid_q='0' and derat_ex6_valid_q='1' + else "10" when derat_inptr_q="00" and derat_req2_valid_q='0' and derat_ex6_valid_q='1' + else "11" when derat_inptr_q="00" and derat_req3_valid_q='0' and derat_ex6_valid_q='1' + else "10" when derat_inptr_q="01" and derat_req2_valid_q='0' and derat_ex6_valid_q='1' + else "11" when derat_inptr_q="01" and derat_req3_valid_q='0' and derat_ex6_valid_q='1' + else "00" when derat_inptr_q="01" and derat_req0_valid_q='0' and derat_ex6_valid_q='1' + else "11" when derat_inptr_q="10" and derat_req3_valid_q='0' and derat_ex6_valid_q='1' + else "00" when derat_inptr_q="10" and derat_req0_valid_q='0' and derat_ex6_valid_q='1' + else "01" when derat_inptr_q="10" and derat_req1_valid_q='0' and derat_ex6_valid_q='1' + else "00" when derat_inptr_q="11" and derat_req0_valid_q='0' and derat_ex6_valid_q='1' + else "01" when derat_inptr_q="11" and derat_req1_valid_q='0' and derat_ex6_valid_q='1' + else "10" when derat_inptr_q="11" and derat_req2_valid_q='0' and derat_ex6_valid_q='1' + else derat_outptr_q when derat_req_taken='1' + else derat_inptr_q; +derat_outptr_d <= "01" when derat_outptr_q="00" and derat_req0_valid_q='1' and derat_req_taken='1' + else "10" when derat_outptr_q="01" and derat_req1_valid_q='1' and derat_req_taken='1' + else "11" when derat_outptr_q="10" and derat_req2_valid_q='1' and derat_req_taken='1' + else "00" when derat_outptr_q="11" and derat_req3_valid_q='1' and derat_req_taken='1' + else "01" when derat_outptr_q="00" and derat_req0_valid_q='0' and derat_req1_valid_q='1' + else "10" when derat_outptr_q="00" and derat_req0_valid_q='0' and derat_req1_valid_q='0' and derat_req2_valid_q='1' + else "11" when derat_outptr_q="00" and derat_req0_valid_q='0' and derat_req1_valid_q='0' and derat_req2_valid_q='0' and derat_req3_valid_q='1' + else "10" when derat_outptr_q="01" and derat_req1_valid_q='0' and derat_req2_valid_q='1' + else "11" when derat_outptr_q="01" and derat_req1_valid_q='0' and derat_req2_valid_q='0' and derat_req3_valid_q='1' + else "00" when derat_outptr_q="01" and derat_req1_valid_q='0' and derat_req2_valid_q='0' and derat_req3_valid_q='0' and derat_req0_valid_q='1' + else "11" when derat_outptr_q="10" and derat_req2_valid_q='0' and derat_req3_valid_q='1' + else "00" when derat_outptr_q="10" and derat_req2_valid_q='0' and derat_req3_valid_q='0' and derat_req0_valid_q='1' + else "01" when derat_outptr_q="10" and derat_req2_valid_q='0' and derat_req3_valid_q='0' and derat_req0_valid_q='0' and derat_req1_valid_q='1' + else "00" when derat_outptr_q="11" and derat_req3_valid_q='0' and derat_req0_valid_q='1' + else "01" when derat_outptr_q="11" and derat_req3_valid_q='0' and derat_req0_valid_q='0' and derat_req1_valid_q='1' + else "10" when derat_outptr_q="11" and derat_req3_valid_q='0' and derat_req0_valid_q='0' and derat_req1_valid_q='0' and derat_req2_valid_q='1' + else derat_outptr_q; +tlb_seq_derat_req_d <= '1' when ((derat_outptr_q="00" and derat_req0_valid_q='1') or + (derat_outptr_q="01" and derat_req1_valid_q='1') or + (derat_outptr_q="10" and derat_req2_valid_q='1') or + (derat_outptr_q="11" and derat_req3_valid_q='1')) + else '0'; +tlb_seq_derat_req <= tlb_seq_derat_req_q; +derat_req0_valid_d <= '1' when (derat_ex6_valid_q='1' and derat_req0_valid_q='0' and derat_inptr_q="00") + else '0' when (derat_req_taken='1' and derat_req0_valid_q='1' and derat_outptr_q="00") + else '0' when (tlb_cmp_derat_dup_val(0)='1' and tlb_cmp_derat_dup_val(4)='1') + else derat_req0_valid_q; +derat_req0_thdid_d(0 to 3) <= derat_ex6_thdid_q when (derat_ex6_valid_q='1' and derat_req0_valid_q='0' and derat_inptr_q="00") + else derat_req0_thdid_q(0 to 3); +derat_req0_epn_d <= derat_ex6_epn_q when (derat_ex6_valid_q='1' and derat_req0_valid_q='0' and derat_inptr_q="00") + else derat_req0_epn_q; +derat_req0_state_d <= derat_ex6_state_q when (derat_ex6_valid_q='1' and derat_req0_valid_q='0' and derat_inptr_q="00") + else derat_req0_state_q; +derat_req0_ttype_d <= derat_ex6_ttype_q when (derat_ex6_valid_q='1' and derat_req0_valid_q='0' and derat_inptr_q="00") + else derat_req0_ttype_q; +derat_req0_pid_d <= derat_ex6_pid_q when (derat_ex6_valid_q='1' and derat_req0_valid_q='0' and derat_inptr_q="00") + else derat_req0_pid_q; +derat_req0_lpid_d <= derat_ex6_lpid_q when (derat_ex6_valid_q='1' and derat_req0_valid_q='0' and derat_inptr_q="00") + else derat_req0_lpid_q; +derat_req0_dup_d(0) <= '0'; +derat_req0_dup_d(1) <= '0' when (derat_req_taken='1' and derat_req0_valid_q='1' and derat_outptr_q="00") + else tlb_cmp_derat_dup_val(6) when (derat_ex6_valid_q='1' and derat_req0_valid_q='0' and derat_inptr_q="00") + else tlb_cmp_derat_dup_val(0) when (derat_req0_valid_q='1' and derat_req0_dup_q(1)='0' and tlb_cmp_derat_dup_val(4)='0' and tlb_cmp_derat_dup_val(5)='1') + else derat_req0_dup_q(1); +derat_req1_valid_d <= '1' when (derat_ex6_valid_q='1' and derat_req1_valid_q='0' and derat_inptr_q="01") + else '0' when (derat_req_taken='1' and derat_req1_valid_q='1' and derat_outptr_q="01") + else '0' when (tlb_cmp_derat_dup_val(1)='1' and tlb_cmp_derat_dup_val(4)='1') + else derat_req1_valid_q; +derat_req1_thdid_d(0 to 3) <= derat_ex6_thdid_q when (derat_ex6_valid_q='1' and derat_req1_valid_q='0' and derat_inptr_q="01") + else derat_req1_thdid_q(0 to 3); +derat_req1_epn_d <= derat_ex6_epn_q when (derat_ex6_valid_q='1' and derat_req1_valid_q='0' and derat_inptr_q="01") + else derat_req1_epn_q; +derat_req1_state_d <= derat_ex6_state_q when (derat_ex6_valid_q='1' and derat_req1_valid_q='0' and derat_inptr_q="01") + else derat_req1_state_q; +derat_req1_ttype_d <= derat_ex6_ttype_q when (derat_ex6_valid_q='1' and derat_req1_valid_q='0' and derat_inptr_q="01") + else derat_req1_ttype_q; +derat_req1_pid_d <= derat_ex6_pid_q when (derat_ex6_valid_q='1' and derat_req1_valid_q='0' and derat_inptr_q="01") + else derat_req1_pid_q; +derat_req1_lpid_d <= derat_ex6_lpid_q when (derat_ex6_valid_q='1' and derat_req1_valid_q='0' and derat_inptr_q="01") + else derat_req1_lpid_q; +derat_req1_dup_d(0) <= '0'; +derat_req1_dup_d(1) <= '0' when (derat_req_taken='1' and derat_req1_valid_q='1' and derat_outptr_q="01") + else tlb_cmp_derat_dup_val(6) when (derat_ex6_valid_q='1' and derat_req1_valid_q='0' and derat_inptr_q="01") + else tlb_cmp_derat_dup_val(1) when (derat_req1_valid_q='1' and derat_req1_dup_q(1)='0' and tlb_cmp_derat_dup_val(4)='0' and tlb_cmp_derat_dup_val(5)='1') + else derat_req1_dup_q(1); +derat_req2_valid_d <= '1' when (derat_ex6_valid_q='1' and derat_req2_valid_q='0' and derat_inptr_q="10") + else '0' when (derat_req_taken='1' and derat_req2_valid_q='1' and derat_outptr_q="10") + else '0' when (tlb_cmp_derat_dup_val(2)='1' and tlb_cmp_derat_dup_val(4)='1') + else derat_req2_valid_q; +derat_req2_thdid_d(0 to 3) <= derat_ex6_thdid_q when (derat_ex6_valid_q='1' and derat_req2_valid_q='0' and derat_inptr_q="10") + else derat_req2_thdid_q(0 to 3); +derat_req2_epn_d <= derat_ex6_epn_q when (derat_ex6_valid_q='1' and derat_req2_valid_q='0' and derat_inptr_q="10") + else derat_req2_epn_q; +derat_req2_state_d <= derat_ex6_state_q when (derat_ex6_valid_q='1' and derat_req2_valid_q='0' and derat_inptr_q="10") + else derat_req2_state_q; +derat_req2_ttype_d <= derat_ex6_ttype_q when (derat_ex6_valid_q='1' and derat_req2_valid_q='0' and derat_inptr_q="10") + else derat_req2_ttype_q; +derat_req2_pid_d <= derat_ex6_pid_q when (derat_ex6_valid_q='1' and derat_req2_valid_q='0' and derat_inptr_q="10") + else derat_req2_pid_q; +derat_req2_lpid_d <= derat_ex6_lpid_q when (derat_ex6_valid_q='1' and derat_req2_valid_q='0' and derat_inptr_q="10") + else derat_req2_lpid_q; +derat_req2_dup_d(0) <= '0'; +derat_req2_dup_d(1) <= '0' when (derat_req_taken='1' and derat_req2_valid_q='1' and derat_outptr_q="10") + else tlb_cmp_derat_dup_val(6) when (derat_ex6_valid_q='1' and derat_req2_valid_q='0' and derat_inptr_q="10") + else tlb_cmp_derat_dup_val(2) when (derat_req2_valid_q='1' and derat_req2_dup_q(1)='0' and tlb_cmp_derat_dup_val(4)='0' and tlb_cmp_derat_dup_val(5)='1') + else derat_req2_dup_q(1); +derat_req3_valid_d <= '1' when (derat_ex6_valid_q='1' and derat_req3_valid_q='0' and derat_inptr_q="11") + else '0' when (derat_req_taken='1' and derat_req3_valid_q='1' and derat_outptr_q="11") + else '0' when (tlb_cmp_derat_dup_val(3)='1' and tlb_cmp_derat_dup_val(4)='1') + else derat_req3_valid_q; +derat_req3_thdid_d(0 to 3) <= derat_ex6_thdid_q when (derat_ex6_valid_q='1' and derat_req3_valid_q='0' and derat_inptr_q="11") + else derat_req3_thdid_q(0 to 3); +derat_req3_epn_d <= derat_ex6_epn_q when (derat_ex6_valid_q='1' and derat_req3_valid_q='0' and derat_inptr_q="11") + else derat_req3_epn_q; +derat_req3_state_d <= derat_ex6_state_q when (derat_ex6_valid_q='1' and derat_req3_valid_q='0' and derat_inptr_q="11") + else derat_req3_state_q; +derat_req3_ttype_d <= derat_ex6_ttype_q when (derat_ex6_valid_q='1' and derat_req3_valid_q='0' and derat_inptr_q="11") + else derat_req3_ttype_q; +derat_req3_pid_d <= derat_ex6_pid_q when (derat_ex6_valid_q='1' and derat_req3_valid_q='0' and derat_inptr_q="11") + else derat_req3_pid_q; +derat_req3_lpid_d <= derat_ex6_lpid_q when (derat_ex6_valid_q='1' and derat_req3_valid_q='0' and derat_inptr_q="11") + else derat_req3_lpid_q; +derat_req3_dup_d(0) <= '0'; +derat_req3_dup_d(1) <= '0' when (derat_req_taken='1' and derat_req3_valid_q='1' and derat_outptr_q="11") + else tlb_cmp_derat_dup_val(6) when (derat_ex6_valid_q='1' and derat_req3_valid_q='0' and derat_inptr_q="11") + else tlb_cmp_derat_dup_val(3) when (derat_req3_valid_q='1' and derat_req3_dup_q(1)='0' and tlb_cmp_derat_dup_val(4)='0' and tlb_cmp_derat_dup_val(5)='1') + else derat_req3_dup_q(1); +ierat_req_epn <= ierat_req1_epn_q when (ierat_outptr_q="01") + else ierat_req2_epn_q when (ierat_outptr_q="10") + else ierat_req3_epn_q when (ierat_outptr_q="11") + else ierat_req0_epn_q; +ierat_req_pid <= ierat_req1_pid_q when (ierat_outptr_q="01") + else ierat_req2_pid_q when (ierat_outptr_q="10") + else ierat_req3_pid_q when (ierat_outptr_q="11") + else ierat_req0_pid_q; +ierat_req_state <= ierat_req1_state_q when (ierat_outptr_q="01") + else ierat_req2_state_q when (ierat_outptr_q="10") + else ierat_req3_state_q when (ierat_outptr_q="11") + else ierat_req0_state_q; +ierat_req_thdid <= ierat_req1_thdid_q(0 to thdid_width-1) when (ierat_outptr_q="01") + else ierat_req2_thdid_q(0 to thdid_width-1) when (ierat_outptr_q="10") + else ierat_req3_thdid_q(0 to thdid_width-1) when (ierat_outptr_q="11") + else ierat_req0_thdid_q(0 to thdid_width-1); +ierat_req_dup <= ierat_req1_dup_q(0 to 1) when (ierat_outptr_q="01") + else ierat_req2_dup_q(0 to 1) when (ierat_outptr_q="10") + else ierat_req3_dup_q(0 to 1) when (ierat_outptr_q="11") + else ierat_req0_dup_q(0 to 1); +derat_req_epn <= derat_req1_epn_q when (derat_outptr_q="01") + else derat_req2_epn_q when (derat_outptr_q="10") + else derat_req3_epn_q when (derat_outptr_q="11") + else derat_req0_epn_q; +derat_req_pid <= derat_req1_pid_q when (derat_outptr_q="01") + else derat_req2_pid_q when (derat_outptr_q="10") + else derat_req3_pid_q when (derat_outptr_q="11") + else derat_req0_pid_q; +derat_req_lpid <= derat_req1_lpid_q when (derat_outptr_q="01") + else derat_req2_lpid_q when (derat_outptr_q="10") + else derat_req3_lpid_q when (derat_outptr_q="11") + else derat_req0_lpid_q; +derat_req_state <= derat_req1_state_q when (derat_outptr_q="01") + else derat_req2_state_q when (derat_outptr_q="10") + else derat_req3_state_q when (derat_outptr_q="11") + else derat_req0_state_q; +derat_req_ttype <= derat_req1_ttype_q when (derat_outptr_q="01") + else derat_req2_ttype_q when (derat_outptr_q="10") + else derat_req3_ttype_q when (derat_outptr_q="11") + else derat_req0_ttype_q; +derat_req_thdid <= derat_req1_thdid_q(0 to thdid_width-1) when (derat_outptr_q="01") + else derat_req2_thdid_q(0 to thdid_width-1) when (derat_outptr_q="10") + else derat_req3_thdid_q(0 to thdid_width-1) when (derat_outptr_q="11") + else derat_req0_thdid_q(0 to thdid_width-1); +derat_req_dup <= derat_req1_dup_q(0 to 1) when (derat_outptr_q="01") + else derat_req2_dup_q(0 to 1) when (derat_outptr_q="10") + else derat_req3_dup_q(0 to 1) when (derat_outptr_q="11") + else derat_req0_dup_q(0 to 1); +ierat_req0_pid <= ierat_req0_pid_q; +ierat_req0_gs <= ierat_req0_state_q(1); +ierat_req0_as <= ierat_req0_state_q(2); +ierat_req0_epn <= ierat_req0_epn_q; +ierat_req0_thdid <= ierat_req0_thdid_q; +ierat_req0_valid <= ierat_req0_valid_q; +ierat_req0_nonspec <= ierat_req0_nonspec_q; +ierat_req1_pid <= ierat_req1_pid_q; +ierat_req1_gs <= ierat_req1_state_q(1); +ierat_req1_as <= ierat_req1_state_q(2); +ierat_req1_epn <= ierat_req1_epn_q; +ierat_req1_thdid <= ierat_req1_thdid_q; +ierat_req1_valid <= ierat_req1_valid_q; +ierat_req1_nonspec <= ierat_req1_nonspec_q; +ierat_req2_pid <= ierat_req2_pid_q; +ierat_req2_gs <= ierat_req2_state_q(1); +ierat_req2_as <= ierat_req2_state_q(2); +ierat_req2_epn <= ierat_req2_epn_q; +ierat_req2_thdid <= ierat_req2_thdid_q; +ierat_req2_valid <= ierat_req2_valid_q; +ierat_req2_nonspec <= ierat_req2_nonspec_q; +ierat_req3_pid <= ierat_req3_pid_q; +ierat_req3_gs <= ierat_req3_state_q(1); +ierat_req3_as <= ierat_req3_state_q(2); +ierat_req3_epn <= ierat_req3_epn_q; +ierat_req3_thdid <= ierat_req3_thdid_q; +ierat_req3_valid <= ierat_req3_valid_q; +ierat_req3_nonspec <= ierat_req3_nonspec_q; +ierat_iu4_pid <= ierat_iu4_pid_q; +ierat_iu4_gs <= ierat_iu4_state_q(1); +ierat_iu4_as <= ierat_iu4_state_q(2); +ierat_iu4_epn <= ierat_iu4_epn_q; +ierat_iu4_thdid <= ierat_iu4_thdid_q; +ierat_iu4_valid <= ierat_iu4_valid_q; +derat_req0_lpid <= derat_req0_lpid_q; +derat_req0_pid <= derat_req0_pid_q; +derat_req0_gs <= derat_req0_state_q(1); +derat_req0_as <= derat_req0_state_q(2); +derat_req0_epn <= derat_req0_epn_q; +derat_req0_thdid <= derat_req0_thdid_q; +derat_req0_valid <= derat_req0_valid_q; +derat_req1_lpid <= derat_req1_lpid_q; +derat_req1_pid <= derat_req1_pid_q; +derat_req1_gs <= derat_req1_state_q(1); +derat_req1_as <= derat_req1_state_q(2); +derat_req1_epn <= derat_req1_epn_q; +derat_req1_thdid <= derat_req1_thdid_q; +derat_req1_valid <= derat_req1_valid_q; +derat_req2_lpid <= derat_req2_lpid_q; +derat_req2_pid <= derat_req2_pid_q; +derat_req2_gs <= derat_req2_state_q(1); +derat_req2_as <= derat_req2_state_q(2); +derat_req2_epn <= derat_req2_epn_q; +derat_req2_thdid <= derat_req2_thdid_q; +derat_req2_valid <= derat_req2_valid_q; +derat_req3_lpid <= derat_req3_lpid_q; +derat_req3_pid <= derat_req3_pid_q; +derat_req3_gs <= derat_req3_state_q(1); +derat_req3_as <= derat_req3_state_q(2); +derat_req3_epn <= derat_req3_epn_q; +derat_req3_thdid <= derat_req3_thdid_q; +derat_req3_valid <= derat_req3_valid_q; +derat_ex5_lpid <= derat_ex5_lpid_q; +derat_ex5_pid <= derat_ex5_pid_q; +derat_ex5_gs <= derat_ex5_state_q(1); +derat_ex5_as <= derat_ex5_state_q(2); +derat_ex5_epn <= derat_ex5_epn_q; +derat_ex5_thdid <= derat_ex5_thdid_q; +derat_ex5_valid <= derat_ex5_valid_q; +tlb_req_dbg_ierat_iu5_valid_q <= ierat_iu5_valid_q; +tlb_req_dbg_ierat_iu5_thdid(0) <= ierat_iu5_thdid_q(2) or ierat_iu5_thdid_q(3); +tlb_req_dbg_ierat_iu5_thdid(1) <= ierat_iu5_thdid_q(1) or ierat_iu5_thdid_q(3); +tlb_req_dbg_ierat_iu5_state_q <= ierat_iu5_state_q; +tlb_req_dbg_ierat_inptr_q <= ierat_inptr_q; +tlb_req_dbg_ierat_outptr_q <= ierat_outptr_q; +tlb_req_dbg_ierat_req_valid_q <= ierat_req0_valid_q & ierat_req1_valid_q & ierat_req2_valid_q & ierat_req3_valid_q; +tlb_req_dbg_ierat_req_nonspec_q <= ierat_req0_nonspec_q & ierat_req1_nonspec_q & ierat_req2_nonspec_q & ierat_req3_nonspec_q; +tlb_req_dbg_ierat_req_thdid(0) <= ierat_req0_thdid_q(2) or ierat_req0_thdid_q(3); +tlb_req_dbg_ierat_req_thdid(1) <= ierat_req0_thdid_q(1) or ierat_req0_thdid_q(3); +tlb_req_dbg_ierat_req_thdid(2) <= ierat_req1_thdid_q(2) or ierat_req1_thdid_q(3); +tlb_req_dbg_ierat_req_thdid(3) <= ierat_req1_thdid_q(1) or ierat_req1_thdid_q(3); +tlb_req_dbg_ierat_req_thdid(4) <= ierat_req2_thdid_q(2) or ierat_req2_thdid_q(3); +tlb_req_dbg_ierat_req_thdid(5) <= ierat_req2_thdid_q(1) or ierat_req2_thdid_q(3); +tlb_req_dbg_ierat_req_thdid(6) <= ierat_req3_thdid_q(2) or ierat_req3_thdid_q(3); +tlb_req_dbg_ierat_req_thdid(7) <= ierat_req3_thdid_q(1) or ierat_req3_thdid_q(3); +tlb_req_dbg_ierat_req_dup_q <= ierat_req0_dup_q(1) & ierat_req1_dup_q(1) & ierat_req2_dup_q(1) & ierat_req3_dup_q(1); +tlb_req_dbg_derat_ex6_valid_q <= derat_ex6_valid_q; +tlb_req_dbg_derat_ex6_thdid(0) <= derat_ex6_thdid_q(2) or derat_ex6_thdid_q(3); +tlb_req_dbg_derat_ex6_thdid(1) <= derat_ex6_thdid_q(1) or derat_ex6_thdid_q(3); +tlb_req_dbg_derat_ex6_state_q <= derat_ex6_state_q; +tlb_req_dbg_derat_inptr_q <= derat_inptr_q; +tlb_req_dbg_derat_outptr_q <= derat_outptr_q; +tlb_req_dbg_derat_req_valid_q <= derat_req0_valid_q & derat_req1_valid_q & derat_req2_valid_q & derat_req3_valid_q; +tlb_req_dbg_derat_req_thdid(0) <= derat_req0_thdid_q(2) or derat_req0_thdid_q(3); +tlb_req_dbg_derat_req_thdid(1) <= derat_req0_thdid_q(1) or derat_req0_thdid_q(3); +tlb_req_dbg_derat_req_thdid(2) <= derat_req1_thdid_q(2) or derat_req1_thdid_q(3); +tlb_req_dbg_derat_req_thdid(3) <= derat_req1_thdid_q(1) or derat_req1_thdid_q(3); +tlb_req_dbg_derat_req_thdid(4) <= derat_req2_thdid_q(2) or derat_req2_thdid_q(3); +tlb_req_dbg_derat_req_thdid(5) <= derat_req2_thdid_q(1) or derat_req2_thdid_q(3); +tlb_req_dbg_derat_req_thdid(6) <= derat_req3_thdid_q(2) or derat_req3_thdid_q(3); +tlb_req_dbg_derat_req_thdid(7) <= derat_req3_thdid_q(1) or derat_req3_thdid_q(3); +tlb_req_dbg_derat_req_ttype_q(0 to 1) <= derat_req0_ttype_q(0 to 1); +tlb_req_dbg_derat_req_ttype_q(2 to 3) <= derat_req1_ttype_q(0 to 1); +tlb_req_dbg_derat_req_ttype_q(4 to 5) <= derat_req2_ttype_q(0 to 1); +tlb_req_dbg_derat_req_ttype_q(6 to 7) <= derat_req3_ttype_q(0 to 1); +tlb_req_dbg_derat_req_dup_q <= derat_req0_dup_q(1) & derat_req1_dup_q(1) & derat_req2_dup_q(1) & derat_req3_dup_q(1); +unused_dc(0) <= or_reduce(LCB_DELAY_LCLKR_DC(1 TO 4)); +unused_dc(1) <= or_reduce(LCB_MPW1_DC_B(1 TO 4)); +unused_dc(2) <= PC_FUNC_SL_FORCE; +unused_dc(3) <= PC_FUNC_SL_THOLD_0_B; +unused_dc(4) <= TC_SCAN_DIS_DC_B; +unused_dc(5) <= TC_SCAN_DIAG_DC; +unused_dc(6) <= TC_LBIST_EN_DC; +unused_dc(7) <= or_reduce(IERAT_REQ_PID_MUX); +unused_dc(8) <= or_reduce(MM_XU_ERATMISS_DONE); +unused_dc(9) <= or_reduce(MM_XU_TLB_MISS); +unused_dc(10) <= TLB_SEQ_IERAT_DONE; +unused_dc(11) <= TLB_SEQ_DERAT_DONE; +unused_dc(12) <= mmucr2_act_override; +ierat_req0_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_req0_valid_offset), + scout => sov(ierat_req0_valid_offset), + din => ierat_req0_valid_d, + dout => ierat_req0_valid_q); +ierat_req0_nonspec_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_req0_nonspec_offset), + scout => sov(ierat_req0_nonspec_offset), + din => ierat_req0_nonspec_d, + dout => ierat_req0_nonspec_q); +ierat_req0_thdid_latch: tri_rlmreg_p + generic map (width => ierat_req0_thdid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_req0_thdid_offset to ierat_req0_thdid_offset+ierat_req0_thdid_q'length-1), + scout => sov(ierat_req0_thdid_offset to ierat_req0_thdid_offset+ierat_req0_thdid_q'length-1), + din => ierat_req0_thdid_d(0 to thdid_width-1), + dout => ierat_req0_thdid_q(0 to thdid_width-1) ); +ierat_req0_epn_latch: tri_rlmreg_p + generic map (width => ierat_req0_epn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_req0_epn_offset to ierat_req0_epn_offset+ierat_req0_epn_q'length-1), + scout => sov(ierat_req0_epn_offset to ierat_req0_epn_offset+ierat_req0_epn_q'length-1), + din => ierat_req0_epn_d(0 to req_epn_width-1), + dout => ierat_req0_epn_q(0 to req_epn_width-1) ); +ierat_req0_state_latch: tri_rlmreg_p + generic map (width => ierat_req0_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_req0_state_offset to ierat_req0_state_offset+ierat_req0_state_q'length-1), + scout => sov(ierat_req0_state_offset to ierat_req0_state_offset+ierat_req0_state_q'length-1), + din => ierat_req0_state_d(0 to state_width-1), + dout => ierat_req0_state_q(0 to state_width-1) ); +ierat_req0_pid_latch: tri_rlmreg_p + generic map (width => ierat_req0_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_req0_pid_offset to ierat_req0_pid_offset+ierat_req0_pid_q'length-1), + scout => sov(ierat_req0_pid_offset to ierat_req0_pid_offset+ierat_req0_pid_q'length-1), + din => ierat_req0_pid_d(0 to pid_width-1), + dout => ierat_req0_pid_q(0 to pid_width-1) ); +ierat_req0_dup_latch: tri_rlmreg_p + generic map (width => ierat_req0_dup_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_req0_dup_offset to ierat_req0_dup_offset+ierat_req0_dup_q'length-1), + scout => sov(ierat_req0_dup_offset to ierat_req0_dup_offset+ierat_req0_dup_q'length-1), + din => ierat_req0_dup_d, + dout => ierat_req0_dup_q ); +ierat_req1_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_req1_valid_offset), + scout => sov(ierat_req1_valid_offset), + din => ierat_req1_valid_d, + dout => ierat_req1_valid_q); +ierat_req1_nonspec_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_req1_nonspec_offset), + scout => sov(ierat_req1_nonspec_offset), + din => ierat_req1_nonspec_d, + dout => ierat_req1_nonspec_q); +ierat_req1_thdid_latch: tri_rlmreg_p + generic map (width => ierat_req1_thdid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_req1_thdid_offset to ierat_req1_thdid_offset+ierat_req1_thdid_q'length-1), + scout => sov(ierat_req1_thdid_offset to ierat_req1_thdid_offset+ierat_req1_thdid_q'length-1), + din => ierat_req1_thdid_d(0 to thdid_width-1), + dout => ierat_req1_thdid_q(0 to thdid_width-1) ); +ierat_req1_epn_latch: tri_rlmreg_p + generic map (width => ierat_req1_epn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_req1_epn_offset to ierat_req1_epn_offset+ierat_req1_epn_q'length-1), + scout => sov(ierat_req1_epn_offset to ierat_req1_epn_offset+ierat_req1_epn_q'length-1), + din => ierat_req1_epn_d(0 to req_epn_width-1), + dout => ierat_req1_epn_q(0 to req_epn_width-1) ); +ierat_req1_state_latch: tri_rlmreg_p + generic map (width => ierat_req1_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_req1_state_offset to ierat_req1_state_offset+ierat_req1_state_q'length-1), + scout => sov(ierat_req1_state_offset to ierat_req1_state_offset+ierat_req1_state_q'length-1), + din => ierat_req1_state_d(0 to state_width-1), + dout => ierat_req1_state_q(0 to state_width-1) ); +ierat_req1_pid_latch: tri_rlmreg_p + generic map (width => ierat_req1_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_req1_pid_offset to ierat_req1_pid_offset+ierat_req1_pid_q'length-1), + scout => sov(ierat_req1_pid_offset to ierat_req1_pid_offset+ierat_req1_pid_q'length-1), + din => ierat_req1_pid_d(0 to pid_width-1), + dout => ierat_req1_pid_q(0 to pid_width-1) ); +ierat_req1_dup_latch: tri_rlmreg_p + generic map (width => ierat_req1_dup_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_req1_dup_offset to ierat_req1_dup_offset+ierat_req1_dup_q'length-1), + scout => sov(ierat_req1_dup_offset to ierat_req1_dup_offset+ierat_req1_dup_q'length-1), + din => ierat_req1_dup_d, + dout => ierat_req1_dup_q ); +ierat_req2_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_req2_valid_offset), + scout => sov(ierat_req2_valid_offset), + din => ierat_req2_valid_d, + dout => ierat_req2_valid_q); +ierat_req2_nonspec_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_req2_nonspec_offset), + scout => sov(ierat_req2_nonspec_offset), + din => ierat_req2_nonspec_d, + dout => ierat_req2_nonspec_q); +ierat_req2_thdid_latch: tri_rlmreg_p + generic map (width => ierat_req2_thdid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_req2_thdid_offset to ierat_req2_thdid_offset+ierat_req2_thdid_q'length-1), + scout => sov(ierat_req2_thdid_offset to ierat_req2_thdid_offset+ierat_req2_thdid_q'length-1), + din => ierat_req2_thdid_d(0 to thdid_width-1), + dout => ierat_req2_thdid_q(0 to thdid_width-1) ); +ierat_req2_epn_latch: tri_rlmreg_p + generic map (width => ierat_req2_epn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_req2_epn_offset to ierat_req2_epn_offset+ierat_req2_epn_q'length-1), + scout => sov(ierat_req2_epn_offset to ierat_req2_epn_offset+ierat_req2_epn_q'length-1), + din => ierat_req2_epn_d(0 to req_epn_width-1), + dout => ierat_req2_epn_q(0 to req_epn_width-1) ); +ierat_req2_state_latch: tri_rlmreg_p + generic map (width => ierat_req2_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_req2_state_offset to ierat_req2_state_offset+ierat_req2_state_q'length-1), + scout => sov(ierat_req2_state_offset to ierat_req2_state_offset+ierat_req2_state_q'length-1), + din => ierat_req2_state_d(0 to state_width-1), + dout => ierat_req2_state_q(0 to state_width-1) ); +ierat_req2_pid_latch: tri_rlmreg_p + generic map (width => ierat_req2_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_req2_pid_offset to ierat_req2_pid_offset+ierat_req2_pid_q'length-1), + scout => sov(ierat_req2_pid_offset to ierat_req2_pid_offset+ierat_req2_pid_q'length-1), + din => ierat_req2_pid_d(0 to pid_width-1), + dout => ierat_req2_pid_q(0 to pid_width-1) ); +ierat_req2_dup_latch: tri_rlmreg_p + generic map (width => ierat_req2_dup_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_req2_dup_offset to ierat_req2_dup_offset+ierat_req2_dup_q'length-1), + scout => sov(ierat_req2_dup_offset to ierat_req2_dup_offset+ierat_req2_dup_q'length-1), + din => ierat_req2_dup_d, + dout => ierat_req2_dup_q ); +ierat_req3_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_req3_valid_offset), + scout => sov(ierat_req3_valid_offset), + din => ierat_req3_valid_d, + dout => ierat_req3_valid_q); +ierat_req3_nonspec_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_req3_nonspec_offset), + scout => sov(ierat_req3_nonspec_offset), + din => ierat_req3_nonspec_d, + dout => ierat_req3_nonspec_q); +ierat_req3_thdid_latch: tri_rlmreg_p + generic map (width => ierat_req3_thdid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_req3_thdid_offset to ierat_req3_thdid_offset+ierat_req3_thdid_q'length-1), + scout => sov(ierat_req3_thdid_offset to ierat_req3_thdid_offset+ierat_req3_thdid_q'length-1), + din => ierat_req3_thdid_d(0 to thdid_width-1), + dout => ierat_req3_thdid_q(0 to thdid_width-1) ); +ierat_req3_epn_latch: tri_rlmreg_p + generic map (width => ierat_req3_epn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_req3_epn_offset to ierat_req3_epn_offset+ierat_req3_epn_q'length-1), + scout => sov(ierat_req3_epn_offset to ierat_req3_epn_offset+ierat_req3_epn_q'length-1), + din => ierat_req3_epn_d(0 to req_epn_width-1), + dout => ierat_req3_epn_q(0 to req_epn_width-1) ); +ierat_req3_state_latch: tri_rlmreg_p + generic map (width => ierat_req3_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_req3_state_offset to ierat_req3_state_offset+ierat_req3_state_q'length-1), + scout => sov(ierat_req3_state_offset to ierat_req3_state_offset+ierat_req3_state_q'length-1), + din => ierat_req3_state_d(0 to state_width-1), + dout => ierat_req3_state_q(0 to state_width-1) ); +ierat_req3_pid_latch: tri_rlmreg_p + generic map (width => ierat_req3_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_req3_pid_offset to ierat_req3_pid_offset+ierat_req3_pid_q'length-1), + scout => sov(ierat_req3_pid_offset to ierat_req3_pid_offset+ierat_req3_pid_q'length-1), + din => ierat_req3_pid_d(0 to pid_width-1), + dout => ierat_req3_pid_q(0 to pid_width-1) ); +ierat_req3_dup_latch: tri_rlmreg_p + generic map (width => ierat_req3_dup_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_req3_dup_offset to ierat_req3_dup_offset+ierat_req3_dup_q'length-1), + scout => sov(ierat_req3_dup_offset to ierat_req3_dup_offset+ierat_req3_dup_q'length-1), + din => ierat_req3_dup_d, + dout => ierat_req3_dup_q ); +ierat_inptr_latch: tri_rlmreg_p + generic map (width => ierat_inptr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_inptr_offset to ierat_inptr_offset+ierat_inptr_q'length-1), + scout => sov(ierat_inptr_offset to ierat_inptr_offset+ierat_inptr_q'length-1), + din => ierat_inptr_d, + dout => ierat_inptr_q ); +ierat_outptr_latch: tri_rlmreg_p + generic map (width => ierat_outptr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_outptr_offset to ierat_outptr_offset+ierat_outptr_q'length-1), + scout => sov(ierat_outptr_offset to ierat_outptr_offset+ierat_outptr_q'length-1), + din => ierat_outptr_d, + dout => ierat_outptr_q ); +ierat_iu3_flush_latch: tri_rlmreg_p + generic map (width => ierat_iu3_flush_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_iu3_flush_offset to ierat_iu3_flush_offset+ierat_iu3_flush_q'length-1), + scout => sov(ierat_iu3_flush_offset to ierat_iu3_flush_offset+ierat_iu3_flush_q'length-1), + din => ierat_iu3_flush_d, + dout => ierat_iu3_flush_q ); +tlb_seq_ierat_req_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_seq_ierat_req_offset), + scout => sov(tlb_seq_ierat_req_offset), + din => tlb_seq_ierat_req_d, + dout => tlb_seq_ierat_req_q); +xu_mm_ierat_flush_latch: tri_rlmreg_p + generic map (width => xu_mm_ierat_flush_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(xu_mm_ierat_flush_offset to xu_mm_ierat_flush_offset+xu_mm_ierat_flush_q'length-1), + scout => sov(xu_mm_ierat_flush_offset to xu_mm_ierat_flush_offset+xu_mm_ierat_flush_q'length-1), + din => xu_mm_ierat_flush_d, + dout => xu_mm_ierat_flush_q ); +xu_mm_ierat_miss_latch: tri_rlmreg_p + generic map (width => xu_mm_ierat_miss_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(xu_mm_ierat_miss_offset to xu_mm_ierat_miss_offset+xu_mm_ierat_miss_q'length-1), + scout => sov(xu_mm_ierat_miss_offset to xu_mm_ierat_miss_offset+xu_mm_ierat_miss_q'length-1), + din => xu_mm_ierat_miss_d, + dout => xu_mm_ierat_miss_q ); +ierat_iu3_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_iu3_valid_offset), + scout => sov(ierat_iu3_valid_offset), + din => ierat_iu3_valid_d, + dout => ierat_iu3_valid_q); +ierat_iu3_thdid_latch: tri_rlmreg_p + generic map (width => ierat_iu3_thdid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_iu3_thdid_offset to ierat_iu3_thdid_offset+ierat_iu3_thdid_q'length-1), + scout => sov(ierat_iu3_thdid_offset to ierat_iu3_thdid_offset+ierat_iu3_thdid_q'length-1), + din => ierat_iu3_thdid_d(0 to thdid_width-1), + dout => ierat_iu3_thdid_q(0 to thdid_width-1) ); +ierat_iu3_epn_latch: tri_rlmreg_p + generic map (width => ierat_iu3_epn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_iu3_epn_offset to ierat_iu3_epn_offset+ierat_iu3_epn_q'length-1), + scout => sov(ierat_iu3_epn_offset to ierat_iu3_epn_offset+ierat_iu3_epn_q'length-1), + din => ierat_iu3_epn_d(0 to req_epn_width-1), + dout => ierat_iu3_epn_q(0 to req_epn_width-1) ); +ierat_iu3_state_latch: tri_rlmreg_p + generic map (width => ierat_iu3_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_iu3_state_offset to ierat_iu3_state_offset+ierat_iu3_state_q'length-1), + scout => sov(ierat_iu3_state_offset to ierat_iu3_state_offset+ierat_iu3_state_q'length-1), + din => ierat_iu3_state_d(0 to state_width-1), + dout => ierat_iu3_state_q(0 to state_width-1) ); +ierat_iu3_pid_latch: tri_rlmreg_p + generic map (width => ierat_iu3_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_iu3_pid_offset to ierat_iu3_pid_offset+ierat_iu3_pid_q'length-1), + scout => sov(ierat_iu3_pid_offset to ierat_iu3_pid_offset+ierat_iu3_pid_q'length-1), + din => ierat_iu3_pid_d(0 to pid_width-1), + dout => ierat_iu3_pid_q(0 to pid_width-1) ); +ierat_iu4_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_iu4_valid_offset), + scout => sov(ierat_iu4_valid_offset), + din => ierat_iu4_valid_d, + dout => ierat_iu4_valid_q); +ierat_iu4_thdid_latch: tri_rlmreg_p + generic map (width => ierat_iu4_thdid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_iu4_thdid_offset to ierat_iu4_thdid_offset+ierat_iu4_thdid_q'length-1), + scout => sov(ierat_iu4_thdid_offset to ierat_iu4_thdid_offset+ierat_iu4_thdid_q'length-1), + din => ierat_iu4_thdid_d(0 to thdid_width-1), + dout => ierat_iu4_thdid_q(0 to thdid_width-1) ); +ierat_iu4_epn_latch: tri_rlmreg_p + generic map (width => ierat_iu4_epn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_iu4_epn_offset to ierat_iu4_epn_offset+ierat_iu4_epn_q'length-1), + scout => sov(ierat_iu4_epn_offset to ierat_iu4_epn_offset+ierat_iu4_epn_q'length-1), + din => ierat_iu4_epn_d(0 to req_epn_width-1), + dout => ierat_iu4_epn_q(0 to req_epn_width-1) ); +ierat_iu4_state_latch: tri_rlmreg_p + generic map (width => ierat_iu4_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_iu4_state_offset to ierat_iu4_state_offset+ierat_iu4_state_q'length-1), + scout => sov(ierat_iu4_state_offset to ierat_iu4_state_offset+ierat_iu4_state_q'length-1), + din => ierat_iu4_state_d(0 to state_width-1), + dout => ierat_iu4_state_q(0 to state_width-1) ); +ierat_iu4_pid_latch: tri_rlmreg_p + generic map (width => ierat_iu4_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_iu4_pid_offset to ierat_iu4_pid_offset+ierat_iu4_pid_q'length-1), + scout => sov(ierat_iu4_pid_offset to ierat_iu4_pid_offset+ierat_iu4_pid_q'length-1), + din => ierat_iu4_pid_d(0 to pid_width-1), + dout => ierat_iu4_pid_q(0 to pid_width-1) ); +ierat_iu5_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_iu5_valid_offset), + scout => sov(ierat_iu5_valid_offset), + din => ierat_iu5_valid_d, + dout => ierat_iu5_valid_q); +ierat_iu5_thdid_latch: tri_rlmreg_p + generic map (width => ierat_iu5_thdid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_iu5_thdid_offset to ierat_iu5_thdid_offset+ierat_iu5_thdid_q'length-1), + scout => sov(ierat_iu5_thdid_offset to ierat_iu5_thdid_offset+ierat_iu5_thdid_q'length-1), + din => ierat_iu5_thdid_d(0 to thdid_width-1), + dout => ierat_iu5_thdid_q(0 to thdid_width-1) ); +ierat_iu5_epn_latch: tri_rlmreg_p + generic map (width => ierat_iu5_epn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_iu5_epn_offset to ierat_iu5_epn_offset+ierat_iu5_epn_q'length-1), + scout => sov(ierat_iu5_epn_offset to ierat_iu5_epn_offset+ierat_iu5_epn_q'length-1), + din => ierat_iu5_epn_d(0 to req_epn_width-1), + dout => ierat_iu5_epn_q(0 to req_epn_width-1) ); +ierat_iu5_state_latch: tri_rlmreg_p + generic map (width => ierat_iu5_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_iu5_state_offset to ierat_iu5_state_offset+ierat_iu5_state_q'length-1), + scout => sov(ierat_iu5_state_offset to ierat_iu5_state_offset+ierat_iu5_state_q'length-1), + din => ierat_iu5_state_d(0 to state_width-1), + dout => ierat_iu5_state_q(0 to state_width-1) ); +ierat_iu5_pid_latch: tri_rlmreg_p + generic map (width => ierat_iu5_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_iu5_pid_offset to ierat_iu5_pid_offset+ierat_iu5_pid_q'length-1), + scout => sov(ierat_iu5_pid_offset to ierat_iu5_pid_offset+ierat_iu5_pid_q'length-1), + din => ierat_iu5_pid_d(0 to pid_width-1), + dout => ierat_iu5_pid_q(0 to pid_width-1) ); +derat_req0_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req0_valid_offset), + scout => sov(derat_req0_valid_offset), + din => derat_req0_valid_d, + dout => derat_req0_valid_q); +derat_req0_thdid_latch: tri_rlmreg_p + generic map (width => derat_req0_thdid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req0_thdid_offset to derat_req0_thdid_offset+derat_req0_thdid_q'length-1), + scout => sov(derat_req0_thdid_offset to derat_req0_thdid_offset+derat_req0_thdid_q'length-1), + din => derat_req0_thdid_d(0 to thdid_width-1), + dout => derat_req0_thdid_q(0 to thdid_width-1) ); +derat_req0_epn_latch: tri_rlmreg_p + generic map (width => derat_req0_epn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req0_epn_offset to derat_req0_epn_offset+derat_req0_epn_q'length-1), + scout => sov(derat_req0_epn_offset to derat_req0_epn_offset+derat_req0_epn_q'length-1), + din => derat_req0_epn_d(0 to req_epn_width-1), + dout => derat_req0_epn_q(0 to req_epn_width-1) ); +derat_req0_state_latch: tri_rlmreg_p + generic map (width => derat_req0_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req0_state_offset to derat_req0_state_offset+derat_req0_state_q'length-1), + scout => sov(derat_req0_state_offset to derat_req0_state_offset+derat_req0_state_q'length-1), + din => derat_req0_state_d(0 to state_width-1), + dout => derat_req0_state_q(0 to state_width-1) ); +derat_req0_ttype_latch: tri_rlmreg_p + generic map (width => derat_req0_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req0_ttype_offset to derat_req0_ttype_offset+derat_req0_ttype_q'length-1), + scout => sov(derat_req0_ttype_offset to derat_req0_ttype_offset+derat_req0_ttype_q'length-1), + din => derat_req0_ttype_d, + dout => derat_req0_ttype_q ); +derat_req0_pid_latch: tri_rlmreg_p + generic map (width => derat_req0_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req0_pid_offset to derat_req0_pid_offset+derat_req0_pid_q'length-1), + scout => sov(derat_req0_pid_offset to derat_req0_pid_offset+derat_req0_pid_q'length-1), + din => derat_req0_pid_d(0 to pid_width-1), + dout => derat_req0_pid_q(0 to pid_width-1) ); +derat_req0_lpid_latch: tri_rlmreg_p + generic map (width => derat_req0_lpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req0_lpid_offset to derat_req0_lpid_offset+derat_req0_lpid_q'length-1), + scout => sov(derat_req0_lpid_offset to derat_req0_lpid_offset+derat_req0_lpid_q'length-1), + din => derat_req0_lpid_d(0 to lpid_width-1), + dout => derat_req0_lpid_q(0 to lpid_width-1) ); +derat_req0_dup_latch: tri_rlmreg_p + generic map (width => derat_req0_dup_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req0_dup_offset to derat_req0_dup_offset+derat_req0_dup_q'length-1), + scout => sov(derat_req0_dup_offset to derat_req0_dup_offset+derat_req0_dup_q'length-1), + din => derat_req0_dup_d, + dout => derat_req0_dup_q ); +derat_req1_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req1_valid_offset), + scout => sov(derat_req1_valid_offset), + din => derat_req1_valid_d, + dout => derat_req1_valid_q); +derat_req1_thdid_latch: tri_rlmreg_p + generic map (width => derat_req1_thdid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req1_thdid_offset to derat_req1_thdid_offset+derat_req1_thdid_q'length-1), + scout => sov(derat_req1_thdid_offset to derat_req1_thdid_offset+derat_req1_thdid_q'length-1), + din => derat_req1_thdid_d(0 to thdid_width-1), + dout => derat_req1_thdid_q(0 to thdid_width-1) ); +derat_req1_epn_latch: tri_rlmreg_p + generic map (width => derat_req1_epn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req1_epn_offset to derat_req1_epn_offset+derat_req1_epn_q'length-1), + scout => sov(derat_req1_epn_offset to derat_req1_epn_offset+derat_req1_epn_q'length-1), + din => derat_req1_epn_d(0 to req_epn_width-1), + dout => derat_req1_epn_q(0 to req_epn_width-1) ); +derat_req1_state_latch: tri_rlmreg_p + generic map (width => derat_req1_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req1_state_offset to derat_req1_state_offset+derat_req1_state_q'length-1), + scout => sov(derat_req1_state_offset to derat_req1_state_offset+derat_req1_state_q'length-1), + din => derat_req1_state_d(0 to state_width-1), + dout => derat_req1_state_q(0 to state_width-1) ); +derat_req1_ttype_latch: tri_rlmreg_p + generic map (width => derat_req1_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req1_ttype_offset to derat_req1_ttype_offset+derat_req1_ttype_q'length-1), + scout => sov(derat_req1_ttype_offset to derat_req1_ttype_offset+derat_req1_ttype_q'length-1), + din => derat_req1_ttype_d, + dout => derat_req1_ttype_q ); +derat_req1_pid_latch: tri_rlmreg_p + generic map (width => derat_req1_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req1_pid_offset to derat_req1_pid_offset+derat_req1_pid_q'length-1), + scout => sov(derat_req1_pid_offset to derat_req1_pid_offset+derat_req1_pid_q'length-1), + din => derat_req1_pid_d(0 to pid_width-1), + dout => derat_req1_pid_q(0 to pid_width-1) ); +derat_req1_lpid_latch: tri_rlmreg_p + generic map (width => derat_req1_lpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req1_lpid_offset to derat_req1_lpid_offset+derat_req1_lpid_q'length-1), + scout => sov(derat_req1_lpid_offset to derat_req1_lpid_offset+derat_req1_lpid_q'length-1), + din => derat_req1_lpid_d(0 to lpid_width-1), + dout => derat_req1_lpid_q(0 to lpid_width-1) ); +derat_req1_dup_latch: tri_rlmreg_p + generic map (width => derat_req1_dup_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req1_dup_offset to derat_req1_dup_offset+derat_req1_dup_q'length-1), + scout => sov(derat_req1_dup_offset to derat_req1_dup_offset+derat_req1_dup_q'length-1), + din => derat_req1_dup_d, + dout => derat_req1_dup_q ); +derat_req2_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req2_valid_offset), + scout => sov(derat_req2_valid_offset), + din => derat_req2_valid_d, + dout => derat_req2_valid_q); +derat_req2_thdid_latch: tri_rlmreg_p + generic map (width => derat_req2_thdid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req2_thdid_offset to derat_req2_thdid_offset+derat_req2_thdid_q'length-1), + scout => sov(derat_req2_thdid_offset to derat_req2_thdid_offset+derat_req2_thdid_q'length-1), + din => derat_req2_thdid_d(0 to thdid_width-1), + dout => derat_req2_thdid_q(0 to thdid_width-1) ); +derat_req2_epn_latch: tri_rlmreg_p + generic map (width => derat_req2_epn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req2_epn_offset to derat_req2_epn_offset+derat_req2_epn_q'length-1), + scout => sov(derat_req2_epn_offset to derat_req2_epn_offset+derat_req2_epn_q'length-1), + din => derat_req2_epn_d(0 to req_epn_width-1), + dout => derat_req2_epn_q(0 to req_epn_width-1) ); +derat_req2_state_latch: tri_rlmreg_p + generic map (width => derat_req2_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req2_state_offset to derat_req2_state_offset+derat_req2_state_q'length-1), + scout => sov(derat_req2_state_offset to derat_req2_state_offset+derat_req2_state_q'length-1), + din => derat_req2_state_d(0 to state_width-1), + dout => derat_req2_state_q(0 to state_width-1) ); +derat_req2_ttype_latch: tri_rlmreg_p + generic map (width => derat_req2_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req2_ttype_offset to derat_req2_ttype_offset+derat_req2_ttype_q'length-1), + scout => sov(derat_req2_ttype_offset to derat_req2_ttype_offset+derat_req2_ttype_q'length-1), + din => derat_req2_ttype_d, + dout => derat_req2_ttype_q ); +derat_req2_pid_latch: tri_rlmreg_p + generic map (width => derat_req2_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req2_pid_offset to derat_req2_pid_offset+derat_req2_pid_q'length-1), + scout => sov(derat_req2_pid_offset to derat_req2_pid_offset+derat_req2_pid_q'length-1), + din => derat_req2_pid_d(0 to pid_width-1), + dout => derat_req2_pid_q(0 to pid_width-1) ); +derat_req2_lpid_latch: tri_rlmreg_p + generic map (width => derat_req2_lpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req2_lpid_offset to derat_req2_lpid_offset+derat_req2_lpid_q'length-1), + scout => sov(derat_req2_lpid_offset to derat_req2_lpid_offset+derat_req2_lpid_q'length-1), + din => derat_req2_lpid_d(0 to lpid_width-1), + dout => derat_req2_lpid_q(0 to lpid_width-1) ); +derat_req2_dup_latch: tri_rlmreg_p + generic map (width => derat_req2_dup_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req2_dup_offset to derat_req2_dup_offset+derat_req2_dup_q'length-1), + scout => sov(derat_req2_dup_offset to derat_req2_dup_offset+derat_req2_dup_q'length-1), + din => derat_req2_dup_d, + dout => derat_req2_dup_q ); +derat_req3_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req3_valid_offset), + scout => sov(derat_req3_valid_offset), + din => derat_req3_valid_d, + dout => derat_req3_valid_q); +derat_req3_thdid_latch: tri_rlmreg_p + generic map (width => derat_req3_thdid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req3_thdid_offset to derat_req3_thdid_offset+derat_req3_thdid_q'length-1), + scout => sov(derat_req3_thdid_offset to derat_req3_thdid_offset+derat_req3_thdid_q'length-1), + din => derat_req3_thdid_d(0 to thdid_width-1), + dout => derat_req3_thdid_q(0 to thdid_width-1) ); +derat_req3_epn_latch: tri_rlmreg_p + generic map (width => derat_req3_epn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req3_epn_offset to derat_req3_epn_offset+derat_req3_epn_q'length-1), + scout => sov(derat_req3_epn_offset to derat_req3_epn_offset+derat_req3_epn_q'length-1), + din => derat_req3_epn_d(0 to req_epn_width-1), + dout => derat_req3_epn_q(0 to req_epn_width-1) ); +derat_req3_state_latch: tri_rlmreg_p + generic map (width => derat_req3_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req3_state_offset to derat_req3_state_offset+derat_req3_state_q'length-1), + scout => sov(derat_req3_state_offset to derat_req3_state_offset+derat_req3_state_q'length-1), + din => derat_req3_state_d(0 to state_width-1), + dout => derat_req3_state_q(0 to state_width-1) ); +derat_req3_ttype_latch: tri_rlmreg_p + generic map (width => derat_req3_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req3_ttype_offset to derat_req3_ttype_offset+derat_req3_ttype_q'length-1), + scout => sov(derat_req3_ttype_offset to derat_req3_ttype_offset+derat_req3_ttype_q'length-1), + din => derat_req3_ttype_d, + dout => derat_req3_ttype_q ); +derat_req3_pid_latch: tri_rlmreg_p + generic map (width => derat_req3_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req3_pid_offset to derat_req3_pid_offset+derat_req3_pid_q'length-1), + scout => sov(derat_req3_pid_offset to derat_req3_pid_offset+derat_req3_pid_q'length-1), + din => derat_req3_pid_d(0 to pid_width-1), + dout => derat_req3_pid_q(0 to pid_width-1) ); +derat_req3_lpid_latch: tri_rlmreg_p + generic map (width => derat_req3_lpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req3_lpid_offset to derat_req3_lpid_offset+derat_req3_lpid_q'length-1), + scout => sov(derat_req3_lpid_offset to derat_req3_lpid_offset+derat_req3_lpid_q'length-1), + din => derat_req3_lpid_d(0 to lpid_width-1), + dout => derat_req3_lpid_q(0 to lpid_width-1) ); +derat_req3_dup_latch: tri_rlmreg_p + generic map (width => derat_req3_dup_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req3_dup_offset to derat_req3_dup_offset+derat_req3_dup_q'length-1), + scout => sov(derat_req3_dup_offset to derat_req3_dup_offset+derat_req3_dup_q'length-1), + din => derat_req3_dup_d, + dout => derat_req3_dup_q ); +derat_inptr_latch: tri_rlmreg_p + generic map (width => derat_inptr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_inptr_offset to derat_inptr_offset+derat_inptr_q'length-1), + scout => sov(derat_inptr_offset to derat_inptr_offset+derat_inptr_q'length-1), + din => derat_inptr_d, + dout => derat_inptr_q ); +derat_outptr_latch: tri_rlmreg_p + generic map (width => derat_outptr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_outptr_offset to derat_outptr_offset+derat_outptr_q'length-1), + scout => sov(derat_outptr_offset to derat_outptr_offset+derat_outptr_q'length-1), + din => derat_outptr_d, + dout => derat_outptr_q ); +tlb_seq_derat_req_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_seq_derat_req_offset), + scout => sov(tlb_seq_derat_req_offset), + din => tlb_seq_derat_req_d, + dout => tlb_seq_derat_req_q); +derat_ex4_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_ex4_valid_offset), + scout => sov(derat_ex4_valid_offset), + din => derat_ex4_valid_d, + dout => derat_ex4_valid_q); +derat_ex4_thdid_latch: tri_rlmreg_p + generic map (width => derat_ex4_thdid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_ex4_thdid_offset to derat_ex4_thdid_offset+derat_ex4_thdid_q'length-1), + scout => sov(derat_ex4_thdid_offset to derat_ex4_thdid_offset+derat_ex4_thdid_q'length-1), + din => derat_ex4_thdid_d(0 to thdid_width-1), + dout => derat_ex4_thdid_q(0 to thdid_width-1) ); +derat_ex4_epn_latch: tri_rlmreg_p + generic map (width => derat_ex4_epn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_ex4_epn_offset to derat_ex4_epn_offset+derat_ex4_epn_q'length-1), + scout => sov(derat_ex4_epn_offset to derat_ex4_epn_offset+derat_ex4_epn_q'length-1), + din => derat_ex4_epn_d(0 to req_epn_width-1), + dout => derat_ex4_epn_q(0 to req_epn_width-1) ); +derat_ex4_state_latch: tri_rlmreg_p + generic map (width => derat_ex4_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_ex4_state_offset to derat_ex4_state_offset+derat_ex4_state_q'length-1), + scout => sov(derat_ex4_state_offset to derat_ex4_state_offset+derat_ex4_state_q'length-1), + din => derat_ex4_state_d(0 to state_width-1), + dout => derat_ex4_state_q(0 to state_width-1) ); +derat_ex4_ttype_latch: tri_rlmreg_p + generic map (width => derat_ex4_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_ex4_ttype_offset to derat_ex4_ttype_offset+derat_ex4_ttype_q'length-1), + scout => sov(derat_ex4_ttype_offset to derat_ex4_ttype_offset+derat_ex4_ttype_q'length-1), + din => derat_ex4_ttype_d, + dout => derat_ex4_ttype_q ); +derat_ex4_pid_latch: tri_rlmreg_p + generic map (width => derat_ex4_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_ex4_pid_offset to derat_ex4_pid_offset+derat_ex4_pid_q'length-1), + scout => sov(derat_ex4_pid_offset to derat_ex4_pid_offset+derat_ex4_pid_q'length-1), + din => derat_ex4_pid_d(0 to pid_width-1), + dout => derat_ex4_pid_q(0 to pid_width-1) ); +derat_ex4_lpid_latch: tri_rlmreg_p + generic map (width => derat_ex4_lpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_ex4_lpid_offset to derat_ex4_lpid_offset+derat_ex4_lpid_q'length-1), + scout => sov(derat_ex4_lpid_offset to derat_ex4_lpid_offset+derat_ex4_lpid_q'length-1), + din => derat_ex4_lpid_d(0 to lpid_width-1), + dout => derat_ex4_lpid_q(0 to lpid_width-1) ); +derat_ex5_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_ex5_valid_offset), + scout => sov(derat_ex5_valid_offset), + din => derat_ex5_valid_d, + dout => derat_ex5_valid_q); +derat_ex5_thdid_latch: tri_rlmreg_p + generic map (width => derat_ex5_thdid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_ex5_thdid_offset to derat_ex5_thdid_offset+derat_ex5_thdid_q'length-1), + scout => sov(derat_ex5_thdid_offset to derat_ex5_thdid_offset+derat_ex5_thdid_q'length-1), + din => derat_ex5_thdid_d(0 to thdid_width-1), + dout => derat_ex5_thdid_q(0 to thdid_width-1) ); +derat_ex5_epn_latch: tri_rlmreg_p + generic map (width => derat_ex5_epn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_ex5_epn_offset to derat_ex5_epn_offset+derat_ex5_epn_q'length-1), + scout => sov(derat_ex5_epn_offset to derat_ex5_epn_offset+derat_ex5_epn_q'length-1), + din => derat_ex5_epn_d(0 to req_epn_width-1), + dout => derat_ex5_epn_q(0 to req_epn_width-1) ); +derat_ex5_state_latch: tri_rlmreg_p + generic map (width => derat_ex5_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_ex5_state_offset to derat_ex5_state_offset+derat_ex5_state_q'length-1), + scout => sov(derat_ex5_state_offset to derat_ex5_state_offset+derat_ex5_state_q'length-1), + din => derat_ex5_state_d(0 to state_width-1), + dout => derat_ex5_state_q(0 to state_width-1) ); +derat_ex5_ttype_latch: tri_rlmreg_p + generic map (width => derat_ex5_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_ex5_ttype_offset to derat_ex5_ttype_offset+derat_ex5_ttype_q'length-1), + scout => sov(derat_ex5_ttype_offset to derat_ex5_ttype_offset+derat_ex5_ttype_q'length-1), + din => derat_ex5_ttype_d, + dout => derat_ex5_ttype_q ); +derat_ex5_pid_latch: tri_rlmreg_p + generic map (width => derat_ex5_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_ex5_pid_offset to derat_ex5_pid_offset+derat_ex5_pid_q'length-1), + scout => sov(derat_ex5_pid_offset to derat_ex5_pid_offset+derat_ex5_pid_q'length-1), + din => derat_ex5_pid_d(0 to pid_width-1), + dout => derat_ex5_pid_q(0 to pid_width-1) ); +derat_ex5_lpid_latch: tri_rlmreg_p + generic map (width => derat_ex5_lpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_ex5_lpid_offset to derat_ex5_lpid_offset+derat_ex5_lpid_q'length-1), + scout => sov(derat_ex5_lpid_offset to derat_ex5_lpid_offset+derat_ex5_lpid_q'length-1), + din => derat_ex5_lpid_d(0 to lpid_width-1), + dout => derat_ex5_lpid_q(0 to lpid_width-1) ); +derat_ex6_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_ex6_valid_offset), + scout => sov(derat_ex6_valid_offset), + din => derat_ex6_valid_d, + dout => derat_ex6_valid_q); +derat_ex6_thdid_latch: tri_rlmreg_p + generic map (width => derat_ex6_thdid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_ex6_thdid_offset to derat_ex6_thdid_offset+derat_ex6_thdid_q'length-1), + scout => sov(derat_ex6_thdid_offset to derat_ex6_thdid_offset+derat_ex6_thdid_q'length-1), + din => derat_ex6_thdid_d(0 to thdid_width-1), + dout => derat_ex6_thdid_q(0 to thdid_width-1) ); +derat_ex6_epn_latch: tri_rlmreg_p + generic map (width => derat_ex6_epn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_ex6_epn_offset to derat_ex6_epn_offset+derat_ex6_epn_q'length-1), + scout => sov(derat_ex6_epn_offset to derat_ex6_epn_offset+derat_ex6_epn_q'length-1), + din => derat_ex6_epn_d(0 to req_epn_width-1), + dout => derat_ex6_epn_q(0 to req_epn_width-1) ); +derat_ex6_state_latch: tri_rlmreg_p + generic map (width => derat_ex6_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_ex6_state_offset to derat_ex6_state_offset+derat_ex6_state_q'length-1), + scout => sov(derat_ex6_state_offset to derat_ex6_state_offset+derat_ex6_state_q'length-1), + din => derat_ex6_state_d(0 to state_width-1), + dout => derat_ex6_state_q(0 to state_width-1) ); +derat_ex6_ttype_latch: tri_rlmreg_p + generic map (width => derat_ex6_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_ex6_ttype_offset to derat_ex6_ttype_offset+derat_ex6_ttype_q'length-1), + scout => sov(derat_ex6_ttype_offset to derat_ex6_ttype_offset+derat_ex6_ttype_q'length-1), + din => derat_ex6_ttype_d, + dout => derat_ex6_ttype_q ); +derat_ex6_pid_latch: tri_rlmreg_p + generic map (width => derat_ex6_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_ex6_pid_offset to derat_ex6_pid_offset+derat_ex6_pid_q'length-1), + scout => sov(derat_ex6_pid_offset to derat_ex6_pid_offset+derat_ex6_pid_q'length-1), + din => derat_ex6_pid_d(0 to pid_width-1), + dout => derat_ex6_pid_q(0 to pid_width-1) ); +derat_ex6_lpid_latch: tri_rlmreg_p + generic map (width => derat_ex6_lpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_ex6_lpid_offset to derat_ex6_lpid_offset+derat_ex6_lpid_q'length-1), + scout => sov(derat_ex6_lpid_offset to derat_ex6_lpid_offset+derat_ex6_lpid_q'length-1), + din => derat_ex6_lpid_d(0 to lpid_width-1), + dout => derat_ex6_lpid_q(0 to lpid_width-1) ); +spare_latch: tri_rlmreg_p + generic map (width => spare_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(spare_offset to spare_offset+spare_q'length-1), + scout => sov(spare_offset to spare_offset+spare_q'length-1), + din => spare_q, + dout => spare_q ); +perv_2to1_reg: tri_plat + generic map (width => 3, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ccflush_dc, + din(0) => pc_func_sl_thold_2, + din(1) => pc_func_slp_sl_thold_2, + din(2) => pc_sg_2, + q(0) => pc_func_sl_thold_1, + q(1) => pc_func_slp_sl_thold_1, + q(2) => pc_sg_1); +perv_1to0_reg: tri_plat + generic map (width => 3, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ccflush_dc, + din(0) => pc_func_sl_thold_1, + din(1) => pc_func_slp_sl_thold_1, + din(2) => pc_sg_1, + q(0) => pc_func_sl_thold_0, + q(1) => pc_func_slp_sl_thold_0, + q(2) => pc_sg_0); +perv_lcbor_func_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b, + thold => pc_func_sl_thold_0, + sg => pc_sg_0, + act_dis => lcb_act_dis_dc, + forcee => pc_func_sl_force, + thold_b => pc_func_sl_thold_0_b); +perv_lcbor_func_slp_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b, + thold => pc_func_slp_sl_thold_0, + sg => pc_sg_0, + act_dis => lcb_act_dis_dc, + forcee => pc_func_slp_sl_force, + thold_b => pc_func_slp_sl_thold_0_b); +siv(0 to scan_right) <= sov(1 to scan_right) & ac_func_scan_in; +ac_func_scan_out <= sov(0); +end mmq_tlb_req; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/pcq.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/pcq.vhdl new file mode 100644 index 0000000..310ea3d --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/pcq.vhdl @@ -0,0 +1,1265 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee; +use ieee.std_logic_1164.all; +library ibm,clib; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +library support; +use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + + +entity pcq is +generic(expand_type : integer := 2; + regmode : integer := 6 +); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + + an_ac_scom_sat_id : in std_ulogic_vector(0 to 3); + an_ac_scom_dch : in std_ulogic; + an_ac_scom_cch : in std_ulogic; + ac_an_scom_dch : out std_ulogic; + ac_an_scom_cch : out std_ulogic; + slowspr_val_in : in std_ulogic; + slowspr_rw_in : in std_ulogic; + slowspr_etid_in : in std_ulogic_vector(0 to 1); + slowspr_addr_in : in std_ulogic_vector(0 to 9); + slowspr_data_in : in std_ulogic_vector(64-(2**regmode) to 63); + slowspr_done_in : in std_ulogic; + slowspr_val_out : out std_ulogic; + slowspr_rw_out : out std_ulogic; + slowspr_etid_out : out std_ulogic_vector(0 to 1); + slowspr_addr_out : out std_ulogic_vector(0 to 9); + slowspr_data_out : out std_ulogic_vector(64-(2**regmode) to 63); + slowspr_done_out : out std_ulogic; + + ac_an_special_attn : out std_ulogic_vector(0 to 3); + ac_an_checkstop : out std_ulogic_vector(0 to 2); + ac_an_local_checkstop : out std_ulogic_vector(0 to 2); + ac_an_recov_err : out std_ulogic_vector(0 to 2); + ac_an_trace_error : out std_ulogic; + an_ac_checkstop : in std_ulogic; + an_ac_malf_alert : in std_ulogic; + iu_pc_err_icache_parity : in std_ulogic; + iu_pc_err_icachedir_parity : in std_ulogic; + iu_pc_err_icachedir_multihit : in std_ulogic; + iu_pc_err_ucode_illegal : in std_ulogic_vector(0 to 3); + xu_pc_err_dcache_parity : in std_ulogic; + xu_pc_err_dcachedir_parity : in std_ulogic; + xu_pc_err_dcachedir_multihit : in std_ulogic; + xu_pc_err_mcsr_summary : in std_ulogic_vector(0 to 3); + xu_pc_err_ierat_parity : in std_ulogic; + xu_pc_err_derat_parity : in std_ulogic; + xu_pc_err_tlb_parity : in std_ulogic; + xu_pc_err_tlb_lru_parity : in std_ulogic; + xu_pc_err_ierat_multihit : in std_ulogic; + xu_pc_err_derat_multihit : in std_ulogic; + xu_pc_err_tlb_multihit : in std_ulogic; + xu_pc_err_ext_mchk : in std_ulogic; + xu_pc_err_ditc_overrun : in std_ulogic; + xu_pc_err_local_snoop_reject : in std_ulogic; + xu_pc_err_sprg_ecc : in std_ulogic_vector(0 to 3); + xu_pc_err_sprg_ue : in std_ulogic_vector(0 to 3); + xu_pc_err_regfile_parity : in std_ulogic_vector(0 to 3); + xu_pc_err_regfile_ue : in std_ulogic_vector(0 to 3); + xu_pc_err_llbust_attempt : in std_ulogic_vector(0 to 3); + xu_pc_err_llbust_failed : in std_ulogic_vector(0 to 3); + xu_pc_err_l2intrf_ecc : in std_ulogic; + xu_pc_err_l2intrf_ue : in std_ulogic; + xu_pc_err_l2credit_overrun : in std_ulogic; + xu_pc_err_wdt_reset : in std_ulogic_vector(0 to 3); + xu_pc_err_attention_instr : in std_ulogic_vector(0 to 3); + xu_pc_err_debug_event : in std_ulogic_vector(0 to 3); + xu_pc_err_nia_miscmpr : in std_ulogic_vector(0 to 3); + xu_pc_err_invld_reld : in std_ulogic; + xu_pc_err_mchk_disabled : in std_ulogic; + bx_pc_err_inbox_ecc : in std_ulogic; + bx_pc_err_inbox_ue : in std_ulogic; + bx_pc_err_outbox_ecc : in std_ulogic; + bx_pc_err_outbox_ue : in std_ulogic; + fu_pc_err_regfile_parity : in std_ulogic_vector(0 to 3); + fu_pc_err_regfile_ue : in std_ulogic_vector(0 to 3); + pc_iu_inj_icache_parity : out std_ulogic; + pc_iu_inj_icachedir_parity : out std_ulogic; + pc_xu_inj_dcache_parity : out std_ulogic; + pc_xu_inj_dcachedir_parity : out std_ulogic; + pc_xu_inj_sprg_ecc : out std_ulogic_vector(0 to 3); + pc_xu_inj_regfile_parity : out std_ulogic_vector(0 to 3); + pc_fu_inj_regfile_parity : out std_ulogic_vector(0 to 3); + pc_bx_inj_inbox_ecc : out std_ulogic; + pc_bx_inj_outbox_ecc : out std_ulogic; + pc_xu_inj_llbust_attempt : out std_ulogic_vector(0 to 3); + pc_xu_inj_llbust_failed : out std_ulogic_vector(0 to 3); + pc_xu_inj_wdt_reset : out std_ulogic_vector(0 to 3); + pc_iu_inj_icachedir_multihit : out std_ulogic; + pc_xu_inj_dcachedir_multihit : out std_ulogic; + + pc_iu_ram_instr : out std_ulogic_vector(0 to 31); + pc_iu_ram_instr_ext : out std_ulogic_vector(0 to 3); + pc_iu_ram_mode : out std_ulogic; + pc_iu_ram_thread : out std_ulogic_vector(0 to 1); + pc_xu_ram_execute : out std_ulogic; + pc_xu_ram_mode : out std_ulogic; + pc_xu_ram_thread : out std_ulogic_vector(0 to 1); + xu_pc_ram_interrupt : in std_ulogic; + xu_pc_ram_done : in std_ulogic; + xu_pc_ram_data : in std_ulogic_vector(64-(2**regmode) to 63); + pc_fu_ram_mode : out std_ulogic; + pc_fu_ram_thread : out std_ulogic_vector(0 to 1); + fu_pc_ram_done : in std_ulogic; + fu_pc_ram_data : in std_ulogic_vector(0 to 63); + pc_xu_msrovride_enab : out std_ulogic; + pc_xu_msrovride_pr : out std_ulogic; + pc_xu_msrovride_gs : out std_ulogic; + pc_xu_msrovride_de : out std_ulogic; + pc_iu_ram_force_cmplt : out std_ulogic; + pc_xu_ram_flush_thread : out std_ulogic; + xu_pc_running : in std_ulogic_vector(0 to 3); + xu_pc_stop_dbg_event : in std_ulogic_vector(0 to 3); + xu_pc_step_done : in std_ulogic_vector(0 to 3); + pc_xu_stop : out std_ulogic_vector(0 to 3); + pc_xu_step : out std_ulogic_vector(0 to 3); + pc_xu_force_ude : out std_ulogic_vector(0 to 3); + pc_xu_extirpts_dis_on_stop : out std_ulogic; + pc_xu_timebase_dis_on_stop : out std_ulogic; + pc_xu_decrem_dis_on_stop : out std_ulogic; + an_ac_debug_stop : in std_ulogic; + pc_xu_dbg_action : out std_ulogic_vector(0 to 11); + + debug_bus_out : out std_ulogic_vector(0 to 87); + trace_triggers_out : out std_ulogic_vector(0 to 11); + debug_bus_in : in std_ulogic_vector(0 to 87); + trace_triggers_in : in std_ulogic_vector(0 to 11); + pc_fu_trace_bus_enable : out std_ulogic; + pc_bx_trace_bus_enable : out std_ulogic; + pc_iu_trace_bus_enable : out std_ulogic; + pc_mm_trace_bus_enable : out std_ulogic; + pc_xu_trace_bus_enable : out std_ulogic; + pc_fu_debug_mux1_ctrls : out std_ulogic_vector(0 to 15); + pc_bx_debug_mux1_ctrls : out std_ulogic_vector(0 to 15); + pc_iu_debug_mux1_ctrls : out std_ulogic_vector(0 to 15); + pc_iu_debug_mux2_ctrls : out std_ulogic_vector(0 to 15); + pc_mm_debug_mux1_ctrls : out std_ulogic_vector(0 to 15); + pc_xu_debug_mux1_ctrls : out std_ulogic_vector(0 to 15); + pc_xu_debug_mux2_ctrls : out std_ulogic_vector(0 to 15); + pc_xu_debug_mux3_ctrls : out std_ulogic_vector(0 to 15); + pc_xu_debug_mux4_ctrls : out std_ulogic_vector(0 to 15); + + ac_an_event_bus : out std_ulogic_vector(0 to 7); + ac_an_fu_bypass_events : out std_ulogic_vector(0 to 7); + ac_an_iu_bypass_events : out std_ulogic_vector(0 to 7); + ac_an_mm_bypass_events : out std_ulogic_vector(0 to 7); + ac_an_lsu_bypass_events : out std_ulogic_vector(0 to 7); + fu_pc_event_data : in std_ulogic_vector(0 to 7); + iu_pc_event_data : in std_ulogic_vector(0 to 7); + mm_pc_event_data : in std_ulogic_vector(0 to 7); + xu_pc_event_data : in std_ulogic_vector(0 to 7); + lsu_pc_event_data : in std_ulogic_vector(0 to 7); + ac_pc_trace_to_perfcntr : in std_ulogic_vector(0 to 7); + pc_xu_cache_par_err_event : out std_ulogic; + pc_fu_instr_trace_mode : out std_ulogic; + pc_fu_instr_trace_tid : out std_ulogic_vector(0 to 1); + pc_xu_instr_trace_mode : out std_ulogic; + pc_xu_instr_trace_tid : out std_ulogic_vector(0 to 1); + pc_fu_event_count_mode : out std_ulogic_vector(0 to 2); + pc_iu_event_count_mode : out std_ulogic_vector(0 to 2); + pc_mm_event_count_mode : out std_ulogic_vector(0 to 2); + pc_xu_event_count_mode : out std_ulogic_vector(0 to 2); + pc_fu_event_mux_ctrls : out std_ulogic_vector(0 to 31); + pc_iu_event_mux_ctrls : out std_ulogic_vector(0 to 47); + pc_mm_event_mux_ctrls : out std_ulogic_vector(0 to 39); + pc_xu_event_mux_ctrls : out std_ulogic_vector(0 to 47); + pc_xu_lsu_event_mux_ctrls : out std_ulogic_vector(0 to 47); + pc_fu_event_bus_enable : out std_ulogic; + pc_iu_event_bus_enable : out std_ulogic; + pc_rp_event_bus_enable : out std_ulogic; + pc_xu_event_bus_enable : out std_ulogic; + + an_ac_reset_1_complete : in std_ulogic; + an_ac_reset_2_complete : in std_ulogic; + an_ac_reset_3_complete : in std_ulogic; + an_ac_reset_wd_complete : in std_ulogic; + pc_xu_reset_1_cmplt : out std_ulogic; + pc_xu_reset_2_cmplt : out std_ulogic; + pc_xu_reset_3_cmplt : out std_ulogic; + pc_xu_reset_wd_cmplt : out std_ulogic; + pc_xu_init_reset : out std_ulogic; + pc_iu_init_reset : out std_ulogic; + + ac_an_pm_thread_running : out std_ulogic_vector(0 to 3); + an_ac_pm_thread_stop : in std_ulogic_vector(0 to 3); + ac_an_power_managed : out std_ulogic; + ac_an_rvwinkle_mode : out std_ulogic; + xu_pc_spr_ccr0_pme : in std_ulogic_vector(0 to 1); + xu_pc_spr_ccr0_we : in std_ulogic_vector(0 to 3); + + an_ac_gsd_test_enable_dc : in std_ulogic; + an_ac_gsd_test_acmode_dc : in std_ulogic; + an_ac_ccflush_dc : in std_ulogic; + an_ac_ccenable_dc : in std_ulogic; + an_ac_lbist_en_dc : in std_ulogic; + an_ac_lbist_ip_dc : in std_ulogic; + an_ac_lbist_ac_mode_dc : in std_ulogic; + an_ac_abist_mode_dc : in std_ulogic; + an_ac_abist_start_test : in std_ulogic; + an_ac_scan_diag_dc : in std_ulogic; + an_ac_scan_dis_dc_b : in std_ulogic; + an_ac_scan_diag_dc_opc : out std_ulogic; + an_ac_scan_dis_dc_b_opc : out std_ulogic; + an_ac_rtim_sl_thold_6 : in std_ulogic; + an_ac_func_sl_thold_6 : in std_ulogic; + an_ac_func_nsl_thold_6 : in std_ulogic; + an_ac_ary_nsl_thold_6 : in std_ulogic; + an_ac_sg_6 : in std_ulogic; + an_ac_fce_6 : in std_ulogic; + an_ac_scan_type_dc : in std_ulogic_vector(0 to 8); + pc_xu_ccflush_dc : out std_ulogic; + pc_xu_gptr_sl_thold_3 : out std_ulogic; + pc_xu_time_sl_thold_3 : out std_ulogic; + pc_xu_repr_sl_thold_3 : out std_ulogic; + pc_xu_abst_sl_thold_3 : out std_ulogic; + pc_xu_abst_slp_sl_thold_3 : out std_ulogic; + pc_xu_bolt_sl_thold_3 : out std_ulogic; + pc_xu_regf_sl_thold_3 : out std_ulogic; + pc_xu_regf_slp_sl_thold_3 : out std_ulogic; + pc_xu_func_sl_thold_3 : out std_ulogic_vector(0 to 4); + pc_xu_func_slp_sl_thold_3 : out std_ulogic_vector(0 to 4); + pc_xu_cfg_sl_thold_3 : out std_ulogic; + pc_xu_cfg_slp_sl_thold_3 : out std_ulogic; + pc_xu_func_nsl_thold_3 : out std_ulogic; + pc_xu_func_slp_nsl_thold_3 : out std_ulogic; + pc_xu_ary_nsl_thold_3 : out std_ulogic; + pc_xu_ary_slp_nsl_thold_3 : out std_ulogic; + pc_xu_sg_3 : out std_ulogic_vector(0 to 4); + pc_xu_fce_3 : out std_ulogic_vector(0 to 1); + pc_bx_ccflush_dc : out std_ulogic; + pc_bx_func_sl_thold_3 : out std_ulogic; + pc_bx_func_slp_sl_thold_3 : out std_ulogic; + pc_bx_gptr_sl_thold_3 : out std_ulogic; + pc_bx_time_sl_thold_3 : out std_ulogic; + pc_bx_repr_sl_thold_3 : out std_ulogic; + pc_bx_abst_sl_thold_3 : out std_ulogic; + pc_bx_bolt_sl_thold_3 : out std_ulogic; + pc_bx_ary_nsl_thold_3 : out std_ulogic; + pc_bx_ary_slp_nsl_thold_3 : out std_ulogic; + pc_bx_sg_3 : out std_ulogic; + pc_mm_ccflush_dc : out std_ulogic; + pc_iu_ccflush_dc : out std_ulogic; + pc_iu_gptr_sl_thold_4 : out std_ulogic; + pc_iu_time_sl_thold_4 : out std_ulogic; + pc_iu_repr_sl_thold_4 : out std_ulogic; + pc_iu_abst_sl_thold_4 : out std_ulogic; + pc_iu_abst_slp_sl_thold_4 : out std_ulogic; + pc_iu_bolt_sl_thold_4 : out std_ulogic; + pc_iu_regf_slp_sl_thold_4 : out std_ulogic; + pc_iu_func_sl_thold_4 : out std_ulogic; + pc_iu_func_slp_sl_thold_4 : out std_ulogic; + pc_iu_cfg_sl_thold_4 : out std_ulogic; + pc_iu_cfg_slp_sl_thold_4 : out std_ulogic; + pc_iu_func_nsl_thold_4 : out std_ulogic; + pc_iu_func_slp_nsl_thold_4 : out std_ulogic; + pc_iu_ary_nsl_thold_4 : out std_ulogic; + pc_iu_ary_slp_nsl_thold_4 : out std_ulogic; + pc_iu_sg_4 : out std_ulogic; + pc_iu_fce_4 : out std_ulogic; + pc_fu_ccflush_dc : out std_ulogic; + pc_fu_gptr_sl_thold_3 : out std_ulogic; + pc_fu_time_sl_thold_3 : out std_ulogic; + pc_fu_repr_sl_thold_3 : out std_ulogic; + pc_fu_abst_sl_thold_3 : out std_ulogic; + pc_fu_abst_slp_sl_thold_3 : out std_ulogic; + pc_fu_bolt_sl_thold_3 : out std_ulogic; + pc_fu_func_sl_thold_3 : out std_ulogic_vector(0 to 1); + pc_fu_func_slp_sl_thold_3 : out std_ulogic_vector(0 to 1); + pc_fu_cfg_sl_thold_3 : out std_ulogic; + pc_fu_cfg_slp_sl_thold_3 : out std_ulogic; + pc_fu_func_nsl_thold_3 : out std_ulogic; + pc_fu_func_slp_nsl_thold_3 : out std_ulogic; + pc_fu_ary_nsl_thold_3 : out std_ulogic; + pc_fu_ary_slp_nsl_thold_3 : out std_ulogic; + pc_fu_sg_3 : out std_ulogic_vector(0 to 1); + pc_fu_fce_3 : out std_ulogic; + + an_ac_psro_enable_dc : in std_ulogic_vector(0 to 2); + ac_an_psro_ringsig : out std_ulogic; + + ac_an_abist_done_dc : out std_ulogic; + pc_bx_abist_di_0 : Out std_ulogic_vector(0 to 3); + pc_bx_abist_ena_dc : Out std_ulogic; + pc_bx_abist_g8t1p_renb_0 : Out std_ulogic; + pc_bx_abist_g8t_bw_0 : Out std_ulogic; + pc_bx_abist_g8t_bw_1 : Out std_ulogic; + pc_bx_abist_g8t_dcomp : Out std_ulogic_vector(0 to 3); + pc_bx_abist_g8t_wenb : Out std_ulogic; + pc_bx_abist_raddr_0 : Out std_ulogic_vector(0 to 9); + pc_bx_abist_raw_dc_b : Out std_ulogic; + pc_bx_abist_waddr_0 : Out std_ulogic_vector(0 to 9); + pc_bx_abist_wl64_g8t_comp_ena : Out std_ulogic; + pc_fu_abist_di_0 : Out std_ulogic_vector(0 to 3); + pc_fu_abist_di_1 : Out std_ulogic_vector(0 to 3); + pc_fu_abist_ena_dc : Out std_ulogic; + pc_fu_abist_grf_renb_0 : Out std_ulogic; + pc_fu_abist_grf_renb_1 : Out std_ulogic; + pc_fu_abist_grf_wenb_0 : Out std_ulogic; + pc_fu_abist_grf_wenb_1 : Out std_ulogic; + pc_fu_abist_raddr_0 : Out std_ulogic_vector(0 to 9); + pc_fu_abist_raddr_1 : Out std_ulogic_vector(0 to 9); + pc_fu_abist_raw_dc_b : Out std_ulogic; + pc_fu_abist_waddr_0 : Out std_ulogic_vector(0 to 9); + pc_fu_abist_waddr_1 : Out std_ulogic_vector(0 to 9); + pc_fu_abist_wl144_comp_ena : Out std_ulogic; + pc_iu_abist_dcomp_g6t_2r : Out std_ulogic_vector(0 to 3); + pc_iu_abist_di_0 : Out std_ulogic_vector(0 to 3); + pc_iu_abist_di_g6t_2r : Out std_ulogic_vector(0 to 3); + pc_iu_abist_ena_dc : Out std_ulogic; + pc_iu_abist_g6t_bw : Out std_ulogic_vector(0 to 1); + pc_iu_abist_g6t_r_wb : Out std_ulogic; + pc_iu_abist_g8t1p_renb_0 : Out std_ulogic; + pc_iu_abist_g8t_bw_0 : Out std_ulogic; + pc_iu_abist_g8t_bw_1 : Out std_ulogic; + pc_iu_abist_g8t_dcomp : Out std_ulogic_vector(0 to 3); + pc_iu_abist_g8t_wenb : Out std_ulogic; + pc_iu_abist_raddr_0 : Out std_ulogic_vector(0 to 9); + pc_iu_abist_raw_dc_b : Out std_ulogic; + pc_iu_abist_waddr_0 : Out std_ulogic_vector(0 to 9); + pc_iu_abist_wl128_g8t_comp_ena : Out std_ulogic; + pc_iu_abist_wl256_comp_ena : Out std_ulogic; + pc_iu_abist_wl64_g8t_comp_ena : Out std_ulogic; + pc_mm_abist_dcomp_g6t_2r : Out std_ulogic_vector(0 to 3); + pc_mm_abist_di_0 : Out std_ulogic_vector(0 to 3); + pc_mm_abist_di_g6t_2r : Out std_ulogic_vector(0 to 3); + pc_mm_abist_ena_dc : Out std_ulogic; + pc_mm_abist_g6t_r_wb : Out std_ulogic; + pc_mm_abist_g8t1p_renb_0 : Out std_ulogic; + pc_mm_abist_g8t_bw_0 : Out std_ulogic; + pc_mm_abist_g8t_bw_1 : Out std_ulogic; + pc_mm_abist_g8t_dcomp : Out std_ulogic_vector(0 to 3); + pc_mm_abist_g8t_wenb : Out std_ulogic; + pc_mm_abist_raddr_0 : Out std_ulogic_vector(0 to 9); + pc_mm_abist_raw_dc_b : Out std_ulogic; + pc_mm_abist_waddr_0 : Out std_ulogic_vector(0 to 9); + pc_mm_abist_wl128_g8t_comp_ena : Out std_ulogic; + pc_xu_abist_dcomp_g6t_2r : Out std_ulogic_vector(0 to 3); + pc_xu_abist_di_0 : Out std_ulogic_vector(0 to 3); + pc_xu_abist_di_1 : Out std_ulogic_vector(0 to 3); + pc_xu_abist_di_g6t_2r : Out std_ulogic_vector(0 to 3); + pc_xu_abist_ena_dc : Out std_ulogic; + pc_xu_abist_g6t_bw : Out std_ulogic_vector(0 to 1); + pc_xu_abist_g6t_r_wb : Out std_ulogic; + pc_xu_abist_g8t1p_renb_0 : Out std_ulogic; + pc_xu_abist_g8t_bw_0 : Out std_ulogic; + pc_xu_abist_g8t_bw_1 : Out std_ulogic; + pc_xu_abist_g8t_dcomp : Out std_ulogic_vector(0 to 3); + pc_xu_abist_g8t_wenb : Out std_ulogic; + pc_xu_abist_grf_renb_0 : Out std_ulogic; + pc_xu_abist_grf_renb_1 : Out std_ulogic; + pc_xu_abist_grf_wenb_0 : Out std_ulogic; + pc_xu_abist_grf_wenb_1 : Out std_ulogic; + pc_xu_abist_raddr_0 : Out std_ulogic_vector(0 to 9); + pc_xu_abist_raddr_1 : Out std_ulogic_vector(0 to 9); + pc_xu_abist_raw_dc_b : Out std_ulogic; + pc_xu_abist_waddr_0 : Out std_ulogic_vector(0 to 9); + pc_xu_abist_waddr_1 : Out std_ulogic_vector(0 to 9); + pc_xu_abist_wl144_comp_ena : Out std_ulogic; + pc_xu_abist_wl32_g8t_comp_ena : Out std_ulogic; + pc_xu_abist_wl512_comp_ena : Out std_ulogic; + + an_ac_bo_enable : in std_ulogic; + an_ac_bo_go : in std_ulogic; + an_ac_bo_cntlclk : in std_ulogic; + an_ac_bo_ccflush : in std_ulogic; + an_ac_bo_reset : in std_ulogic; + an_ac_bo_data : in std_ulogic; + an_ac_bo_shcntl : in std_ulogic; + an_ac_bo_shdata : in std_ulogic; + an_ac_bo_sysrepair : in std_ulogic; + an_ac_bo_exe : in std_ulogic; + an_ac_bo_donein : in std_ulogic; + an_ac_bo_sdin : in std_ulogic; + an_ac_bo_waitin : in std_ulogic; + an_ac_bo_failin : in std_ulogic; + an_ac_bo_fcshdata : in std_ulogic; + an_ac_bo_fcreset : in std_ulogic; + ac_an_bo_doneout : out std_ulogic; + ac_an_bo_sdout : out std_ulogic; + ac_an_bo_diagloopout : out std_ulogic; + ac_an_bo_waitout : out std_ulogic; + ac_an_bo_failout : out std_ulogic; + pc_bx_bo_enable_3 : out std_ulogic; + pc_bx_bo_unload : out std_ulogic; + pc_bx_bo_repair : out std_ulogic; + pc_bx_bo_reset : out std_ulogic; + pc_bx_bo_shdata : out std_ulogic; + pc_bx_bo_select : out std_ulogic_vector(0 to 3); + bx_pc_bo_fail : in std_ulogic_vector(0 to 3); + bx_pc_bo_diagout : in std_ulogic_vector(0 to 3); + pc_fu_bo_enable_3 : out std_ulogic; + pc_fu_bo_unload : out std_ulogic; + pc_fu_bo_load : out std_ulogic; + pc_fu_bo_reset : out std_ulogic; + pc_fu_bo_shdata : out std_ulogic; + pc_fu_bo_select : out std_ulogic_vector(0 to 1); + fu_pc_bo_fail : in std_ulogic_vector(0 to 1); + fu_pc_bo_diagout : in std_ulogic_vector(0 to 1); + pc_iu_bo_enable_4 : out std_ulogic; + pc_iu_bo_unload : out std_ulogic; + pc_iu_bo_repair : out std_ulogic; + pc_iu_bo_reset : out std_ulogic; + pc_iu_bo_shdata : out std_ulogic; + pc_iu_bo_select : out std_ulogic_vector(0 to 4); + iu_pc_bo_fail : in std_ulogic_vector(0 to 4); + iu_pc_bo_diagout : in std_ulogic_vector(0 to 4); + pc_mm_bo_enable_4 : out std_ulogic; + pc_mm_bo_unload : out std_ulogic; + pc_mm_bo_repair : out std_ulogic; + pc_mm_bo_reset : out std_ulogic; + pc_mm_bo_shdata : out std_ulogic; + pc_mm_bo_select : out std_ulogic_vector(0 to 4); + mm_pc_bo_fail : in std_ulogic_vector(0 to 4); + mm_pc_bo_diagout : in std_ulogic_vector(0 to 4); + pc_xu_bo_enable_3 : out std_ulogic; + pc_xu_bo_unload : out std_ulogic; + pc_xu_bo_load : out std_ulogic; + pc_xu_bo_repair : out std_ulogic; + pc_xu_bo_reset : out std_ulogic; + pc_xu_bo_shdata : out std_ulogic; + pc_xu_bo_select : out std_ulogic_vector(0 to 8); + xu_pc_bo_fail : in std_ulogic_vector(0 to 8); + xu_pc_bo_diagout : in std_ulogic_vector(0 to 8); + + gptr_scan_in : in std_ulogic; + ccfg_scan_in : in std_ulogic; + bcfg_scan_in : in std_ulogic; + dcfg_scan_in : in std_ulogic; + abst_scan_in : in std_ulogic; + func_scan_in : in std_ulogic_vector(0 to 1); + gptr_scan_out : out std_ulogic; + ccfg_scan_out : out std_ulogic; + bcfg_scan_out : out std_ulogic; + dcfg_scan_out : out std_ulogic; + abst_scan_out : out std_ulogic; + func_scan_out : out std_ulogic_vector(0 to 1) +); +-- synopsys translate_off + + + + +-- synopsys translate_on +end pcq; + +architecture pcq of pcq is +signal ct_db_func_scan_out : std_ulogic; +signal db_ss_func_scan_out : std_ulogic; +signal lcbctrl_gptr_scan_out : std_ulogic; +signal ct_rg_power_managed : std_ulogic_vector(0 to 3); +signal ct_ck_pm_raise_tholds : std_ulogic; +signal ct_ck_pm_ccflush_disable : std_ulogic; +signal ct_rg_pm_thread_stop : std_ulogic_vector(0 to 3); +signal rg_ct_dis_pwr_savings : std_ulogic; +signal rg_ck_fast_xstop : std_ulogic; +signal sp_db_event_mux_ctrls : std_ulogic_vector(0 to 23); +signal sp_db_event_bus_enable : std_ulogic; +signal ct_rg_hold_during_init : std_ulogic; +signal d_mode_dc : std_ulogic; +signal clkoff_dc_b : std_ulogic; +signal act_dis_dc : std_ulogic; +signal delay_lclkr_dc : std_ulogic_vector(0 to 4); +signal mpw1_dc_b : std_ulogic_vector(0 to 4); +signal mpw2_dc_b : std_ulogic; +signal pc_pc_ccflush_dc : std_ulogic; +signal pc_pc_gptr_sl_thold_0 : std_ulogic; +signal pc_pc_abst_sl_thold_0 : std_ulogic; +signal pc_pc_func_sl_thold_0 : std_ulogic; +signal pc_pc_func_slp_sl_thold_0 : std_ulogic; +signal pc_pc_cfg_sl_thold_0 : std_ulogic; +signal pc_pc_cfg_slp_sl_thold_0 : std_ulogic; +signal pc_pc_sg_0 : std_ulogic; +signal sp_rg_trace_bus_enable : std_ulogic; +signal rg_db_trace_bus_enable : std_ulogic; +signal rg_db_debug_mux_ctrls : std_ulogic_vector(0 to 15); +signal ck_db_dbg_clks_ctrls : std_ulogic_vector(0 to 13); +signal rg_db_dbg_scom_rdata : std_ulogic_vector(0 to 63); +signal rg_db_dbg_scom_wdata : std_ulogic_vector(0 to 63); +signal rg_db_dbg_scom_decaddr : std_ulogic_vector(0 to 63); +signal rg_db_dbg_scom_misc : std_ulogic_vector(0 to 8); +signal rg_db_dbg_ram_thrctl : std_ulogic_vector(0 to 20); +signal rg_db_dbg_fir0_err : std_ulogic_vector(0 to 31); +signal rg_db_dbg_fir1_err : std_ulogic_vector(0 to 30); +signal rg_db_dbg_fir2_err : std_ulogic_vector(0 to 21); +signal rg_db_dbg_fir_misc : std_ulogic_vector(0 to 35); +signal ct_db_dbg_ctrls : std_ulogic_vector(0 to 36); +signal rg_db_dbg_spr : std_ulogic_vector(0 to 46); +signal pc_bo_unload_out : std_ulogic; +signal pc_bo_load_out : std_ulogic; +signal pc_bo_repair_out : std_ulogic; +signal pc_bo_reset_out : std_ulogic; +signal pc_bo_shdata_out : std_ulogic; +signal pc_bo_select_out : std_ulogic_vector(0 to 39); +signal pc_bo_fail_in : std_ulogic_vector(0 to 39); +signal pc_bo_diagout_in : std_ulogic_vector(0 to 39); +signal abist_done_int : std_ulogic; +signal abst_eng_si : std_ulogic; +signal abst_scan_out_int : std_ulogic; +signal an_ac_abist_start_test_int : std_ulogic; +signal an_ac_abist_mode_dc_int : std_ulogic; +signal bo_pc_abst_sl_thold_6 : std_ulogic; +signal bo_pc_pc_abst_sl_thold_6 : std_ulogic; +signal bo_pc_ary_nsl_thold_6 : std_ulogic; +signal bo_pc_func_sl_thold_6 : std_ulogic; +signal bo_pc_time_sl_thold_6 : std_ulogic; +signal bo_pc_repr_sl_thold_6 : std_ulogic; +signal bo_pc_sg_6 : std_ulogic; +signal pc_pc_bo_go_0 : std_ulogic; +signal pc_pc_bo_enable_0 : std_ulogic; +signal pc_pc_bo_cntlclk_0 : std_ulogic; +signal pc_pc_bo_reset_0 : std_ulogic; +signal pc_pc_bo_fcshdata_0 : std_ulogic; +signal pc_pc_bo_fcreset_0 : std_ulogic; +signal pc_pc_bolt_sl_thold_6 : std_ulogic; +signal pc_pc_bolt_sl_thold_0 : std_ulogic; +signal unused_signals : std_ulogic; + +signal pcq_psro_ringsig_out : std_ulogic; +signal pcq_psro_ringsig_i : std_ulogic; + + + + + +begin + +unused_signals <= or_reduce(pc_bo_select_out(25 TO 39)); + +an_ac_scan_diag_dc_opc <= an_ac_scan_diag_dc; +an_ac_scan_dis_dc_b_opc <= an_ac_scan_dis_dc_b; +ac_an_abist_done_dc <= abist_done_int; + + + +pcq_regs : entity work.pcq_regs +generic map(expand_type => expand_type, + regmode => regmode ) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + scan_dis_dc_b => an_ac_scan_dis_dc_b, + lcb_clkoff_dc_b => clkoff_dc_b, + lcb_d_mode_dc => d_mode_dc, + lcb_mpw1_dc_b => mpw1_dc_b(0), + lcb_mpw2_dc_b => mpw2_dc_b, + lcb_delay_lclkr_dc => delay_lclkr_dc(0), + lcb_act_dis_dc => act_dis_dc, + lcb_func_slp_sl_thold_0 => pc_pc_func_slp_sl_thold_0, + lcb_cfg_sl_thold_0 => pc_pc_cfg_sl_thold_0, + lcb_cfg_slp_sl_thold_0 => pc_pc_cfg_slp_sl_thold_0, + lcb_sg_0 => pc_pc_sg_0, + ccfg_scan_in => ccfg_scan_in, + bcfg_scan_in => bcfg_scan_in, + dcfg_scan_in => dcfg_scan_in, + func_scan_in => func_scan_in(0), + ccfg_scan_out => ccfg_scan_out, + bcfg_scan_out => bcfg_scan_out, + dcfg_scan_out => dcfg_scan_out, + func_scan_out => func_scan_out(0), + an_ac_scom_sat_id => an_ac_scom_sat_id, + an_ac_scom_dch => an_ac_scom_dch, + an_ac_scom_cch => an_ac_scom_cch, + ac_an_scom_dch => ac_an_scom_dch, + ac_an_scom_cch => ac_an_scom_cch, + ac_an_special_attn => ac_an_special_attn, + ac_an_checkstop => ac_an_checkstop, + ac_an_local_checkstop => ac_an_local_checkstop, + ac_an_recov_err => ac_an_recov_err, + ac_an_trace_error => ac_an_trace_error, + an_ac_checkstop => an_ac_checkstop, + an_ac_malf_alert => an_ac_malf_alert, + rg_ck_fast_xstop => rg_ck_fast_xstop, + iu_pc_err_icache_parity => iu_pc_err_icache_parity, + iu_pc_err_icachedir_parity => iu_pc_err_icachedir_parity, + iu_pc_err_icachedir_multihit => iu_pc_err_icachedir_multihit, + iu_pc_err_ucode_illegal => iu_pc_err_ucode_illegal, + xu_pc_err_dcache_parity => xu_pc_err_dcache_parity, + xu_pc_err_dcachedir_parity => xu_pc_err_dcachedir_parity, + xu_pc_err_dcachedir_multihit => xu_pc_err_dcachedir_multihit, + xu_pc_err_mcsr_summary => xu_pc_err_mcsr_summary, + xu_pc_err_ierat_parity => xu_pc_err_ierat_parity, + xu_pc_err_derat_parity => xu_pc_err_derat_parity, + xu_pc_err_tlb_parity => xu_pc_err_tlb_parity, + xu_pc_err_tlb_lru_parity => xu_pc_err_tlb_lru_parity, + xu_pc_err_ierat_multihit => xu_pc_err_ierat_multihit, + xu_pc_err_derat_multihit => xu_pc_err_derat_multihit, + xu_pc_err_tlb_multihit => xu_pc_err_tlb_multihit, + xu_pc_err_ext_mchk => xu_pc_err_ext_mchk, + xu_pc_err_ditc_overrun => xu_pc_err_ditc_overrun, + xu_pc_err_local_snoop_reject => xu_pc_err_local_snoop_reject, + xu_pc_err_sprg_ecc => xu_pc_err_sprg_ecc, + xu_pc_err_sprg_ue => xu_pc_err_sprg_ue, + xu_pc_err_regfile_parity => xu_pc_err_regfile_parity, + xu_pc_err_regfile_ue => xu_pc_err_regfile_ue, + xu_pc_err_llbust_attempt => xu_pc_err_llbust_attempt, + xu_pc_err_llbust_failed => xu_pc_err_llbust_failed, + xu_pc_err_l2intrf_ecc => xu_pc_err_l2intrf_ecc, + xu_pc_err_l2intrf_ue => xu_pc_err_l2intrf_ue, + xu_pc_err_l2credit_overrun => xu_pc_err_l2credit_overrun, + xu_pc_err_wdt_reset => xu_pc_err_wdt_reset, + xu_pc_err_attention_instr => xu_pc_err_attention_instr, + xu_pc_err_debug_event => xu_pc_err_debug_event, + xu_pc_err_nia_miscmpr => xu_pc_err_nia_miscmpr, + xu_pc_err_invld_reld => xu_pc_err_invld_reld, + xu_pc_err_mchk_disabled => xu_pc_err_mchk_disabled, + bx_pc_err_inbox_ecc => bx_pc_err_inbox_ecc, + bx_pc_err_inbox_ue => bx_pc_err_inbox_ue, + bx_pc_err_outbox_ecc => bx_pc_err_outbox_ecc, + bx_pc_err_outbox_ue => bx_pc_err_outbox_ue, + fu_pc_err_regfile_parity => fu_pc_err_regfile_parity, + fu_pc_err_regfile_ue => fu_pc_err_regfile_ue, + pc_iu_inj_icache_parity => pc_iu_inj_icache_parity, + pc_iu_inj_icachedir_parity => pc_iu_inj_icachedir_parity, + pc_xu_inj_dcache_parity => pc_xu_inj_dcache_parity, + pc_xu_inj_dcachedir_parity => pc_xu_inj_dcachedir_parity, + pc_xu_inj_sprg_ecc => pc_xu_inj_sprg_ecc, + pc_xu_inj_regfile_parity => pc_xu_inj_regfile_parity, + pc_fu_inj_regfile_parity => pc_fu_inj_regfile_parity, + pc_bx_inj_inbox_ecc => pc_bx_inj_inbox_ecc, + pc_bx_inj_outbox_ecc => pc_bx_inj_outbox_ecc, + pc_xu_inj_llbust_attempt => pc_xu_inj_llbust_attempt, + pc_xu_inj_llbust_failed => pc_xu_inj_llbust_failed, + pc_xu_inj_wdt_reset => pc_xu_inj_wdt_reset, + pc_iu_inj_icachedir_multihit => pc_iu_inj_icachedir_multihit, + pc_xu_inj_dcachedir_multihit => pc_xu_inj_dcachedir_multihit, + pc_xu_cache_par_err_event => pc_xu_cache_par_err_event, + pc_iu_ram_instr => pc_iu_ram_instr, + pc_iu_ram_instr_ext => pc_iu_ram_instr_ext, + pc_iu_ram_mode => pc_iu_ram_mode, + pc_iu_ram_thread => pc_iu_ram_thread, + pc_xu_ram_execute => pc_xu_ram_execute, + pc_xu_ram_mode => pc_xu_ram_mode, + pc_xu_ram_thread => pc_xu_ram_thread, + xu_pc_ram_interrupt => xu_pc_ram_interrupt, + xu_pc_ram_done => xu_pc_ram_done, + xu_pc_ram_data => xu_pc_ram_data, + pc_fu_ram_mode => pc_fu_ram_mode, + pc_fu_ram_thread => pc_fu_ram_thread, + fu_pc_ram_done => fu_pc_ram_done, + fu_pc_ram_data => fu_pc_ram_data, + pc_xu_msrovride_enab => pc_xu_msrovride_enab, + pc_xu_msrovride_pr => pc_xu_msrovride_pr, + pc_xu_msrovride_gs => pc_xu_msrovride_gs, + pc_xu_msrovride_de => pc_xu_msrovride_de, + pc_iu_ram_force_cmplt => pc_iu_ram_force_cmplt, + pc_xu_ram_flush_thread => pc_xu_ram_flush_thread, + xu_pc_running => xu_pc_running, + xu_pc_stop_dbg_event => xu_pc_stop_dbg_event, + xu_pc_step_done => xu_pc_step_done, + pc_xu_stop => pc_xu_stop, + pc_xu_step => pc_xu_step, + pc_xu_force_ude => pc_xu_force_ude, + ct_rg_power_managed => ct_rg_power_managed, + ct_rg_pm_thread_stop => ct_rg_pm_thread_stop, + ac_an_pm_thread_running => ac_an_pm_thread_running, + pc_xu_extirpts_dis_on_stop => pc_xu_extirpts_dis_on_stop, + pc_xu_timebase_dis_on_stop => pc_xu_timebase_dis_on_stop, + pc_xu_decrem_dis_on_stop => pc_xu_decrem_dis_on_stop, + ct_rg_hold_during_init => ct_rg_hold_during_init, + an_ac_debug_stop => an_ac_debug_stop, + pc_xu_dbg_action => pc_xu_dbg_action, + rg_ct_dis_pwr_savings => rg_ct_dis_pwr_savings, + sp_rg_trace_bus_enable => sp_rg_trace_bus_enable, + rg_db_trace_bus_enable => rg_db_trace_bus_enable, + pc_fu_trace_bus_enable => pc_fu_trace_bus_enable, + pc_bx_trace_bus_enable => pc_bx_trace_bus_enable, + pc_iu_trace_bus_enable => pc_iu_trace_bus_enable, + pc_mm_trace_bus_enable => pc_mm_trace_bus_enable, + pc_xu_trace_bus_enable => pc_xu_trace_bus_enable, + rg_db_debug_mux_ctrls => rg_db_debug_mux_ctrls, + pc_fu_debug_mux1_ctrls => pc_fu_debug_mux1_ctrls, + pc_bx_debug_mux1_ctrls => pc_bx_debug_mux1_ctrls, + pc_iu_debug_mux1_ctrls => pc_iu_debug_mux1_ctrls, + pc_iu_debug_mux2_ctrls => pc_iu_debug_mux2_ctrls, + pc_mm_debug_mux1_ctrls => pc_mm_debug_mux1_ctrls, + pc_xu_debug_mux1_ctrls => pc_xu_debug_mux1_ctrls, + pc_xu_debug_mux2_ctrls => pc_xu_debug_mux2_ctrls, + pc_xu_debug_mux3_ctrls => pc_xu_debug_mux3_ctrls, + pc_xu_debug_mux4_ctrls => pc_xu_debug_mux4_ctrls, + dbg_scom_rdata => rg_db_dbg_scom_rdata, + dbg_scom_wdata => rg_db_dbg_scom_wdata, + dbg_scom_decaddr => rg_db_dbg_scom_decaddr, + dbg_scom_misc => rg_db_dbg_scom_misc, + dbg_ram_thrctl => rg_db_dbg_ram_thrctl, + dbg_fir0_err => rg_db_dbg_fir0_err, + dbg_fir1_err => rg_db_dbg_fir1_err, + dbg_fir2_err => rg_db_dbg_fir2_err, + dbg_fir_misc => rg_db_dbg_fir_misc +); + + +pcq_ctrl : entity work.pcq_ctrl +generic map(expand_type => expand_type) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + scan_dis_dc_b => an_ac_scan_dis_dc_b, + lcb_clkoff_dc_b => clkoff_dc_b, + lcb_mpw1_dc_b => mpw1_dc_b(1), + lcb_mpw2_dc_b => mpw2_dc_b, + lcb_delay_lclkr_dc => delay_lclkr_dc(1), + lcb_act_dis_dc => act_dis_dc, + pc_pc_func_slp_sl_thold_0 => pc_pc_func_slp_sl_thold_0, + pc_pc_sg_0 => pc_pc_sg_0, + func_scan_in => func_scan_in(1), + func_scan_out => ct_db_func_scan_out, + an_ac_reset_1_complete => an_ac_reset_1_complete, + an_ac_reset_2_complete => an_ac_reset_2_complete, + an_ac_reset_3_complete => an_ac_reset_3_complete, + an_ac_reset_wd_complete => an_ac_reset_wd_complete, + pc_xu_reset_1_cmplt => pc_xu_reset_1_cmplt, + pc_xu_reset_2_cmplt => pc_xu_reset_2_cmplt, + pc_xu_reset_3_cmplt => pc_xu_reset_3_cmplt, + pc_xu_reset_wd_cmplt => pc_xu_reset_wd_cmplt, + pc_xu_init_reset => pc_xu_init_reset, + pc_iu_init_reset => pc_iu_init_reset, + ct_rg_hold_during_init => ct_rg_hold_during_init, + ct_rg_power_managed => ct_rg_power_managed, + ct_rg_pm_thread_stop => ct_rg_pm_thread_stop, + an_ac_pm_thread_stop => an_ac_pm_thread_stop, + ac_an_power_managed => ac_an_power_managed, + ac_an_rvwinkle_mode => ac_an_rvwinkle_mode, + ct_ck_pm_ccflush_disable => ct_ck_pm_ccflush_disable, + ct_ck_pm_raise_tholds => ct_ck_pm_raise_tholds, + rg_ct_dis_pwr_savings => rg_ct_dis_pwr_savings, + xu_pc_spr_ccr0_pme => xu_pc_spr_ccr0_pme, + xu_pc_spr_ccr0_we => xu_pc_spr_ccr0_we, + dbg_ctrls => ct_db_dbg_ctrls +); + + +pcq_dbg : entity work.pcq_dbg +generic map(expand_type => expand_type) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + scan_dis_dc_b => an_ac_scan_dis_dc_b, + lcb_clkoff_dc_b => clkoff_dc_b, + lcb_mpw1_dc_b => mpw1_dc_b(2), + lcb_mpw2_dc_b => mpw2_dc_b, + lcb_delay_lclkr_dc => delay_lclkr_dc(2), + lcb_act_dis_dc => act_dis_dc, + pc_pc_func_slp_sl_thold_0 => pc_pc_func_slp_sl_thold_0, + pc_pc_sg_0 => pc_pc_sg_0, + func_scan_in => ct_db_func_scan_out, + func_scan_out => db_ss_func_scan_out, + debug_bus_out => debug_bus_out, + trace_triggers_out => trace_triggers_out, + debug_bus_in => debug_bus_in, + trace_triggers_in => trace_triggers_in, + rg_db_trace_bus_enable => rg_db_trace_bus_enable, + rg_db_debug_mux_ctrls => rg_db_debug_mux_ctrls, + ck_db_dbg_clks_ctrls => ck_db_dbg_clks_ctrls, + rg_db_dbg_scom_rdata => rg_db_dbg_scom_rdata, + rg_db_dbg_scom_wdata => rg_db_dbg_scom_wdata, + rg_db_dbg_scom_decaddr => rg_db_dbg_scom_decaddr, + rg_db_dbg_scom_misc => rg_db_dbg_scom_misc, + rg_db_dbg_ram_thrctl => rg_db_dbg_ram_thrctl, + rg_db_dbg_fir0_err => rg_db_dbg_fir0_err, + rg_db_dbg_fir1_err => rg_db_dbg_fir1_err, + rg_db_dbg_fir2_err => rg_db_dbg_fir2_err, + rg_db_dbg_fir_misc => rg_db_dbg_fir_misc, + ct_db_dbg_ctrls => ct_db_dbg_ctrls, + rg_db_dbg_spr => rg_db_dbg_spr, + ac_an_event_bus => ac_an_event_bus, + ac_an_fu_bypass_events => ac_an_fu_bypass_events, + ac_an_iu_bypass_events => ac_an_iu_bypass_events, + ac_an_mm_bypass_events => ac_an_mm_bypass_events, + ac_an_lsu_bypass_events => ac_an_lsu_bypass_events, + rg_db_event_bus_enable => sp_db_event_bus_enable, + rg_db_event_mux_ctrls => sp_db_event_mux_ctrls, + fu_pc_event_data => fu_pc_event_data, + iu_pc_event_data => iu_pc_event_data, + mm_pc_event_data => mm_pc_event_data, + xu_pc_event_data => xu_pc_event_data, + lsu_pc_event_data => lsu_pc_event_data, + ac_pc_trace_to_perfcntr => ac_pc_trace_to_perfcntr +); + + +pcq_spr : entity work.pcq_spr +generic map(expand_type => expand_type, + regmode => regmode ) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + scan_dis_dc_b => an_ac_scan_dis_dc_b, + lcb_clkoff_dc_b => clkoff_dc_b, + lcb_mpw1_dc_b => mpw1_dc_b(0), + lcb_mpw2_dc_b => mpw2_dc_b, + lcb_delay_lclkr_dc => delay_lclkr_dc(0), + lcb_act_dis_dc => act_dis_dc, + pc_pc_func_sl_thold_0 => pc_pc_func_sl_thold_0, + pc_pc_sg_0 => pc_pc_sg_0, + func_scan_in => db_ss_func_scan_out, + func_scan_out => func_scan_out(1), + slowspr_val_in => slowspr_val_in, + slowspr_rw_in => slowspr_rw_in, + slowspr_etid_in => slowspr_etid_in, + slowspr_addr_in => slowspr_addr_in, + slowspr_data_in => slowspr_data_in(64-(2**regmode) to 63), + slowspr_done_in => slowspr_done_in, + + slowspr_val_out => slowspr_val_out, + slowspr_rw_out => slowspr_rw_out, + slowspr_etid_out => slowspr_etid_out, + slowspr_addr_out => slowspr_addr_out, + slowspr_data_out => slowspr_data_out(64-(2**regmode) to 63), + slowspr_done_out => slowspr_done_out, + sp_rg_trace_bus_enable => sp_rg_trace_bus_enable, + pc_fu_instr_trace_mode => pc_fu_instr_trace_mode, + pc_fu_instr_trace_tid => pc_fu_instr_trace_tid, + pc_xu_instr_trace_mode => pc_xu_instr_trace_mode, + pc_xu_instr_trace_tid => pc_xu_instr_trace_tid, + pc_fu_event_count_mode => pc_fu_event_count_mode, + pc_iu_event_count_mode => pc_iu_event_count_mode, + pc_mm_event_count_mode => pc_mm_event_count_mode, + pc_xu_event_count_mode => pc_xu_event_count_mode, + pc_fu_event_mux_ctrls => pc_fu_event_mux_ctrls, + pc_iu_event_mux_ctrls => pc_iu_event_mux_ctrls, + pc_mm_event_mux_ctrls => pc_mm_event_mux_ctrls, + pc_xu_event_mux_ctrls => pc_xu_event_mux_ctrls, + pc_xu_lsu_event_mux_ctrls => pc_xu_lsu_event_mux_ctrls, + sp_db_event_mux_ctrls => sp_db_event_mux_ctrls, + pc_fu_event_bus_enable => pc_fu_event_bus_enable, + pc_iu_event_bus_enable => pc_iu_event_bus_enable, + pc_rp_event_bus_enable => pc_rp_event_bus_enable, + pc_xu_event_bus_enable => pc_xu_event_bus_enable, + sp_db_event_bus_enable => sp_db_event_bus_enable, + dbg_spr => rg_db_dbg_spr +); + + +pcq_clks : entity work.pcq_clks +generic map(expand_type => expand_type) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + rtim_sl_thold_6 => an_ac_rtim_sl_thold_6, + func_sl_thold_6 => an_ac_func_sl_thold_6, + func_nsl_thold_6 => an_ac_func_nsl_thold_6, + ary_nsl_thold_6 => an_ac_ary_nsl_thold_6, + sg_6 => an_ac_sg_6, + fce_6 => an_ac_fce_6, + gsd_test_enable_dc => an_ac_gsd_test_enable_dc, + gsd_test_acmode_dc => an_ac_gsd_test_acmode_dc, + ccflush_dc => an_ac_ccflush_dc, + ccenable_dc => an_ac_ccenable_dc, + scan_type_dc => an_ac_scan_type_dc, + lbist_en_dc => an_ac_lbist_en_dc, + lbist_ip_dc => an_ac_lbist_ip_dc, + rg_ck_fast_xstop => rg_ck_fast_xstop, + ct_ck_pm_ccflush_disable => ct_ck_pm_ccflush_disable, + ct_ck_pm_raise_tholds => ct_ck_pm_raise_tholds, + bolton_enable_dc => an_ac_bo_enable, + bolton_enable_sync => pc_pc_bo_enable_0, + bolton_ccflush => an_ac_bo_ccflush, + bc_cntlclk_sync => pc_pc_bo_cntlclk_0, + bolton_fcshdata => pc_pc_bo_fcshdata_0, + bolton_fcreset => pc_pc_bo_fcreset_0, + bo_pc_abst_sl_thold_6 => bo_pc_abst_sl_thold_6, + bo_pc_pc_abst_sl_thold_6 => bo_pc_pc_abst_sl_thold_6, + bo_pc_ary_nsl_thold_6 => bo_pc_ary_nsl_thold_6, + bo_pc_func_sl_thold_6 => bo_pc_func_sl_thold_6, + bo_pc_time_sl_thold_6 => bo_pc_time_sl_thold_6, + bo_pc_repr_sl_thold_6 => bo_pc_repr_sl_thold_6, + bo_pc_sg_6 => bo_pc_sg_6, + pc_xu_ccflush_dc => pc_xu_ccflush_dc, + pc_xu_gptr_sl_thold_3 => pc_xu_gptr_sl_thold_3, + pc_xu_time_sl_thold_3 => pc_xu_time_sl_thold_3, + pc_xu_repr_sl_thold_3 => pc_xu_repr_sl_thold_3, + pc_xu_abst_sl_thold_3 => pc_xu_abst_sl_thold_3, + pc_xu_abst_slp_sl_thold_3 => pc_xu_abst_slp_sl_thold_3, + pc_xu_bolt_sl_thold_3 => pc_xu_bolt_sl_thold_3, + pc_xu_regf_sl_thold_3 => pc_xu_regf_sl_thold_3, + pc_xu_regf_slp_sl_thold_3 => pc_xu_regf_slp_sl_thold_3, + pc_xu_func_sl_thold_3 => pc_xu_func_sl_thold_3, + pc_xu_func_slp_sl_thold_3 => pc_xu_func_slp_sl_thold_3, + pc_xu_cfg_sl_thold_3 => pc_xu_cfg_sl_thold_3, + pc_xu_cfg_slp_sl_thold_3 => pc_xu_cfg_slp_sl_thold_3, + pc_xu_func_nsl_thold_3 => pc_xu_func_nsl_thold_3, + pc_xu_func_slp_nsl_thold_3 => pc_xu_func_slp_nsl_thold_3, + pc_xu_ary_nsl_thold_3 => pc_xu_ary_nsl_thold_3, + pc_xu_ary_slp_nsl_thold_3 => pc_xu_ary_slp_nsl_thold_3, + pc_xu_sg_3 => pc_xu_sg_3, + pc_xu_fce_3 => pc_xu_fce_3, + pc_bx_ccflush_dc => pc_bx_ccflush_dc, + pc_bx_func_sl_thold_3 => pc_bx_func_sl_thold_3, + pc_bx_func_slp_sl_thold_3 => pc_bx_func_slp_sl_thold_3, + pc_bx_gptr_sl_thold_3 => pc_bx_gptr_sl_thold_3, + pc_bx_time_sl_thold_3 => pc_bx_time_sl_thold_3, + pc_bx_repr_sl_thold_3 => pc_bx_repr_sl_thold_3, + pc_bx_abst_sl_thold_3 => pc_bx_abst_sl_thold_3, + pc_bx_bolt_sl_thold_3 => pc_bx_bolt_sl_thold_3, + pc_bx_ary_nsl_thold_3 => pc_bx_ary_nsl_thold_3, + pc_bx_ary_slp_nsl_thold_3 => pc_bx_ary_slp_nsl_thold_3, + pc_bx_sg_3 => pc_bx_sg_3, + pc_mm_ccflush_dc => pc_mm_ccflush_dc, + pc_iu_ccflush_dc => pc_iu_ccflush_dc, + pc_iu_gptr_sl_thold_4 => pc_iu_gptr_sl_thold_4, + pc_iu_time_sl_thold_4 => pc_iu_time_sl_thold_4, + pc_iu_repr_sl_thold_4 => pc_iu_repr_sl_thold_4, + pc_iu_abst_sl_thold_4 => pc_iu_abst_sl_thold_4, + pc_iu_abst_slp_sl_thold_4 => pc_iu_abst_slp_sl_thold_4, + pc_iu_bolt_sl_thold_4 => pc_iu_bolt_sl_thold_4, + pc_iu_regf_slp_sl_thold_4 => pc_iu_regf_slp_sl_thold_4, + pc_iu_func_sl_thold_4 => pc_iu_func_sl_thold_4, + pc_iu_func_slp_sl_thold_4 => pc_iu_func_slp_sl_thold_4, + pc_iu_cfg_sl_thold_4 => pc_iu_cfg_sl_thold_4, + pc_iu_cfg_slp_sl_thold_4 => pc_iu_cfg_slp_sl_thold_4, + pc_iu_func_nsl_thold_4 => pc_iu_func_nsl_thold_4, + pc_iu_func_slp_nsl_thold_4 => pc_iu_func_slp_nsl_thold_4, + pc_iu_ary_nsl_thold_4 => pc_iu_ary_nsl_thold_4, + pc_iu_ary_slp_nsl_thold_4 => pc_iu_ary_slp_nsl_thold_4, + pc_iu_sg_4 => pc_iu_sg_4, + pc_iu_fce_4 => pc_iu_fce_4, + pc_fu_ccflush_dc => pc_fu_ccflush_dc, + pc_fu_gptr_sl_thold_3 => pc_fu_gptr_sl_thold_3, + pc_fu_time_sl_thold_3 => pc_fu_time_sl_thold_3, + pc_fu_repr_sl_thold_3 => pc_fu_repr_sl_thold_3, + pc_fu_abst_sl_thold_3 => pc_fu_abst_sl_thold_3, + pc_fu_abst_slp_sl_thold_3 => pc_fu_abst_slp_sl_thold_3, + pc_fu_bolt_sl_thold_3 => pc_fu_bolt_sl_thold_3, + pc_fu_func_sl_thold_3 => pc_fu_func_sl_thold_3, + pc_fu_func_slp_sl_thold_3 => pc_fu_func_slp_sl_thold_3, + pc_fu_cfg_sl_thold_3 => pc_fu_cfg_sl_thold_3, + pc_fu_cfg_slp_sl_thold_3 => pc_fu_cfg_slp_sl_thold_3, + pc_fu_func_nsl_thold_3 => pc_fu_func_nsl_thold_3, + pc_fu_func_slp_nsl_thold_3 => pc_fu_func_slp_nsl_thold_3, + pc_fu_ary_nsl_thold_3 => pc_fu_ary_nsl_thold_3, + pc_fu_ary_slp_nsl_thold_3 => pc_fu_ary_slp_nsl_thold_3, + pc_fu_sg_3 => pc_fu_sg_3, + pc_fu_fce_3 => pc_fu_fce_3, + pc_pc_ccflush_dc => pc_pc_ccflush_dc, + pc_pc_gptr_sl_thold_0 => pc_pc_gptr_sl_thold_0, + pc_pc_abst_sl_thold_0 => pc_pc_abst_sl_thold_0, + pc_pc_bolt_sl_thold_6 => pc_pc_bolt_sl_thold_6, + pc_pc_bolt_sl_thold_0 => pc_pc_bolt_sl_thold_0, + pc_pc_func_sl_thold_0 => pc_pc_func_sl_thold_0, + pc_pc_func_slp_sl_thold_0 => pc_pc_func_slp_sl_thold_0, + pc_pc_cfg_sl_thold_0 => pc_pc_cfg_sl_thold_0, + pc_pc_cfg_slp_sl_thold_0 => pc_pc_cfg_slp_sl_thold_0, + pc_pc_sg_0 => pc_pc_sg_0, + dbg_clks_ctrls => ck_db_dbg_clks_ctrls +); + + + +pcq_abist : entity work.pcq_abist +generic map(expand_type => expand_type) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + scan_dis_dc_b => an_ac_scan_dis_dc_b, + lcb_clkoff_dc_b => clkoff_dc_b, + lcb_mpw1_dc_b => mpw1_dc_b(3), + lcb_mpw2_dc_b => mpw2_dc_b, + lcb_delay_lclkr_dc => delay_lclkr_dc(3), + lcb_delay_lclkr_np_dc => delay_lclkr_dc(4), + lcb_act_dis_dc => act_dis_dc, + lcb_d_mode_dc => d_mode_dc, + gptr_thold => pc_pc_gptr_sl_thold_0, + gptr_scan_in => lcbctrl_gptr_scan_out, + gptr_scan_out => gptr_scan_out, + abist_thold => pc_pc_abst_sl_thold_0, + abist_sg => pc_pc_sg_0, + abist_scan_in => abst_scan_in, + abist_scan_out => abst_scan_out_int, + bo_enable => pc_pc_bo_enable_0, + bo_abist_eng_si => abst_eng_si, + abist_done_in_dc => '1', + abist_done_out_dc => abist_done_int, + abist_mode_dc => an_ac_abist_mode_dc_int, + abist_start_test => an_ac_abist_start_test_int, + lbist_mode_dc => an_ac_lbist_en_dc, + lbist_ac_mode_dc => an_ac_lbist_ac_mode_dc, + pc_bx_abist_di_0 => pc_bx_abist_di_0(0 to 3), + pc_bx_abist_ena_dc => pc_bx_abist_ena_dc, + pc_bx_abist_g8t1p_renb_0 => pc_bx_abist_g8t1p_renb_0, + pc_bx_abist_g8t_bw_0 => pc_bx_abist_g8t_bw_0, + pc_bx_abist_g8t_bw_1 => pc_bx_abist_g8t_bw_1, + pc_bx_abist_g8t_dcomp => pc_bx_abist_g8t_dcomp(0 to 3), + pc_bx_abist_g8t_wenb => pc_bx_abist_g8t_wenb, + pc_bx_abist_raddr_0 => pc_bx_abist_raddr_0(0 to 9), + pc_bx_abist_raw_dc_b => pc_bx_abist_raw_dc_b, + pc_bx_abist_waddr_0 => pc_bx_abist_waddr_0(0 to 9), + pc_bx_abist_wl64_g8t_comp_ena => pc_bx_abist_wl64_g8t_comp_ena, + pc_fu_abist_di_0 => pc_fu_abist_di_0(0 to 3), + pc_fu_abist_di_1 => pc_fu_abist_di_1(0 to 3), + pc_fu_abist_ena_dc => pc_fu_abist_ena_dc, + pc_fu_abist_grf_renb_0 => pc_fu_abist_grf_renb_0, + pc_fu_abist_grf_renb_1 => pc_fu_abist_grf_renb_1, + pc_fu_abist_grf_wenb_0 => pc_fu_abist_grf_wenb_0, + pc_fu_abist_grf_wenb_1 => pc_fu_abist_grf_wenb_1, + pc_fu_abist_raddr_0 => pc_fu_abist_raddr_0(0 to 9), + pc_fu_abist_raddr_1 => pc_fu_abist_raddr_1(0 to 9), + pc_fu_abist_raw_dc_b => pc_fu_abist_raw_dc_b, + pc_fu_abist_waddr_0 => pc_fu_abist_waddr_0(0 to 9), + pc_fu_abist_waddr_1 => pc_fu_abist_waddr_1(0 to 9), + pc_fu_abist_wl144_comp_ena => pc_fu_abist_wl144_comp_ena, + pc_iu_abist_dcomp_g6t_2r => pc_iu_abist_dcomp_g6t_2r(0 to 3), + pc_iu_abist_di_0 => pc_iu_abist_di_0(0 to 3), + pc_iu_abist_di_g6t_2r => pc_iu_abist_di_g6t_2r(0 to 3), + pc_iu_abist_ena_dc => pc_iu_abist_ena_dc, + pc_iu_abist_g6t_bw => pc_iu_abist_g6t_bw(0 to 1), + pc_iu_abist_g6t_r_wb => pc_iu_abist_g6t_r_wb, + pc_iu_abist_g8t1p_renb_0 => pc_iu_abist_g8t1p_renb_0, + pc_iu_abist_g8t_bw_0 => pc_iu_abist_g8t_bw_0, + pc_iu_abist_g8t_bw_1 => pc_iu_abist_g8t_bw_1, + pc_iu_abist_g8t_dcomp => pc_iu_abist_g8t_dcomp(0 to 3), + pc_iu_abist_g8t_wenb => pc_iu_abist_g8t_wenb, + pc_iu_abist_raddr_0 => pc_iu_abist_raddr_0(0 to 9), + pc_iu_abist_raw_dc_b => pc_iu_abist_raw_dc_b, + pc_iu_abist_waddr_0 => pc_iu_abist_waddr_0(0 to 9), + pc_iu_abist_wl128_g8t_comp_ena => pc_iu_abist_wl128_g8t_comp_ena, + pc_iu_abist_wl256_comp_ena => pc_iu_abist_wl256_comp_ena, + pc_iu_abist_wl64_g8t_comp_ena => pc_iu_abist_wl64_g8t_comp_ena, + pc_mm_abist_dcomp_g6t_2r => pc_mm_abist_dcomp_g6t_2r(0 to 3), + pc_mm_abist_di_0 => pc_mm_abist_di_0(0 to 3), + pc_mm_abist_di_g6t_2r => pc_mm_abist_di_g6t_2r(0 to 3), + pc_mm_abist_ena_dc => pc_mm_abist_ena_dc, + pc_mm_abist_g6t_r_wb => pc_mm_abist_g6t_r_wb, + pc_mm_abist_g8t1p_renb_0 => pc_mm_abist_g8t1p_renb_0, + pc_mm_abist_g8t_bw_0 => pc_mm_abist_g8t_bw_0, + pc_mm_abist_g8t_bw_1 => pc_mm_abist_g8t_bw_1, + pc_mm_abist_g8t_dcomp => pc_mm_abist_g8t_dcomp(0 to 3), + pc_mm_abist_g8t_wenb => pc_mm_abist_g8t_wenb, + pc_mm_abist_raddr_0 => pc_mm_abist_raddr_0(0 to 9), + pc_mm_abist_raw_dc_b => pc_mm_abist_raw_dc_b, + pc_mm_abist_waddr_0 => pc_mm_abist_waddr_0(0 to 9), + pc_mm_abist_wl128_g8t_comp_ena => pc_mm_abist_wl128_g8t_comp_ena, + pc_xu_abist_dcomp_g6t_2r => pc_xu_abist_dcomp_g6t_2r(0 to 3), + pc_xu_abist_di_0 => pc_xu_abist_di_0(0 to 3), + pc_xu_abist_di_1 => pc_xu_abist_di_1(0 to 3), + pc_xu_abist_di_g6t_2r => pc_xu_abist_di_g6t_2r(0 to 3), + pc_xu_abist_ena_dc => pc_xu_abist_ena_dc, + pc_xu_abist_g6t_bw => pc_xu_abist_g6t_bw(0 to 1), + pc_xu_abist_g6t_r_wb => pc_xu_abist_g6t_r_wb, + pc_xu_abist_g8t1p_renb_0 => pc_xu_abist_g8t1p_renb_0, + pc_xu_abist_g8t_bw_0 => pc_xu_abist_g8t_bw_0, + pc_xu_abist_g8t_bw_1 => pc_xu_abist_g8t_bw_1, + pc_xu_abist_g8t_dcomp => pc_xu_abist_g8t_dcomp(0 to 3), + pc_xu_abist_g8t_wenb => pc_xu_abist_g8t_wenb, + pc_xu_abist_grf_renb_0 => pc_xu_abist_grf_renb_0, + pc_xu_abist_grf_renb_1 => pc_xu_abist_grf_renb_1, + pc_xu_abist_grf_wenb_0 => pc_xu_abist_grf_wenb_0, + pc_xu_abist_grf_wenb_1 => pc_xu_abist_grf_wenb_1, + pc_xu_abist_raddr_0 => pc_xu_abist_raddr_0(0 to 9), + pc_xu_abist_raddr_1 => pc_xu_abist_raddr_1(0 to 9), + pc_xu_abist_raw_dc_b => pc_xu_abist_raw_dc_b, + pc_xu_abist_waddr_0 => pc_xu_abist_waddr_0(0 to 9), + pc_xu_abist_waddr_1 => pc_xu_abist_waddr_1(0 to 9), + pc_xu_abist_wl144_comp_ena => pc_xu_abist_wl144_comp_ena, + pc_xu_abist_wl32_g8t_comp_ena => pc_xu_abist_wl32_g8t_comp_ena, + pc_xu_abist_wl512_comp_ena => pc_xu_abist_wl512_comp_ena +); + + +pcq_bolton : entity work.pcq_abist_bolton_frontend +generic map ( expand_type => expand_type, + num_backends => 40 ) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + bcreset => pc_pc_bo_reset_0, + bcdata => an_ac_bo_data, + bcshcntl => an_ac_bo_shcntl, + bcshdata => an_ac_bo_shdata, + bcexe => an_ac_bo_exe, + bcsysrepair => an_ac_bo_sysrepair, + bo_enable => pc_pc_bo_enable_0, + bo_go => pc_pc_bo_go_0, + donein => an_ac_bo_donein, + sdin => an_ac_bo_sdin, + doneout => ac_an_bo_doneout, + sdout => ac_an_bo_sdout, + diagloop_out => ac_an_bo_diagloopout, + waitin => an_ac_bo_waitin, + failin => an_ac_bo_failin, + waitout => ac_an_bo_waitout, + failout => ac_an_bo_failout, + abist_done => abist_done_int, + abist_si => abst_eng_si, + abist_start_test_int => an_ac_abist_start_test_int, + abist_start_test => an_ac_abist_start_test, + abist_mode_dc => an_ac_abist_mode_dc, + abist_mode_dc_int => an_ac_abist_mode_dc_int, + bo_unload => pc_bo_unload_out, + bo_load => pc_bo_load_out, + bo_repair => pc_bo_repair_out, + bo_reset => pc_bo_reset_out, + bo_shdata => pc_bo_shdata_out, + bo_select => pc_bo_select_out, + bo_fail => pc_bo_fail_in, + bo_diagout => pc_bo_diagout_in, + lbist_ac_mode_dc => an_ac_lbist_ac_mode_dc, + ck_bo_sl_thold_6 => pc_pc_bolt_sl_thold_6, + ck_bo_sl_thold_0 => pc_pc_bolt_sl_thold_0, + ck_bo_sg_0 => pc_pc_sg_0, + lcb_clkoff_dc_b => clkoff_dc_b, + lcb_mpw1_dc_b => mpw1_dc_b(4), + lcb_mpw2_dc_b => mpw2_dc_b, + lcb_delay_lclkr_dc => delay_lclkr_dc(4), + lcb_act_dis_dc => act_dis_dc, + scan_in => abst_scan_out_int, + scan_out => abst_scan_out, + bo_pc_abst_sl_thold_6 => bo_pc_abst_sl_thold_6, + bo_pc_pc_abst_sl_thold_6 => bo_pc_pc_abst_sl_thold_6, + bo_pc_ary_nsl_thold_6 => bo_pc_ary_nsl_thold_6, + bo_pc_func_sl_thold_6 => bo_pc_func_sl_thold_6, + bo_pc_time_sl_thold_6 => bo_pc_time_sl_thold_6, + bo_pc_repr_sl_thold_6 => bo_pc_repr_sl_thold_6, + bo_pc_sg_6 => bo_pc_sg_6 +); + + +pcq_bolton_stg : entity work.pcq_abist_bolton_stg +generic map( expand_type => expand_type) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_pc_ccflush_dc => pc_pc_ccflush_dc, + + pu_pc_bo_enable => an_ac_bo_enable, + pu_pc_bo_go => an_ac_bo_go, + pu_pc_bo_cntlclk => an_ac_bo_cntlclk, + pu_pc_bo_reset => an_ac_bo_reset, + pu_pc_bo_fcshdata => an_ac_bo_fcshdata, + pu_pc_bo_fcreset => an_ac_bo_fcreset, + + pc_bx_bo_enable_3 => pc_bx_bo_enable_3, + pc_fu_bo_enable_3 => pc_fu_bo_enable_3, + pc_iu_bo_enable_4 => pc_iu_bo_enable_4, + pc_mm_bo_enable_4 => pc_mm_bo_enable_4, + pc_xu_bo_enable_3 => pc_xu_bo_enable_3, + pc_pc_bo_go_0 => pc_pc_bo_go_0, + pc_pc_bo_enable_0 => pc_pc_bo_enable_0, + pc_pc_bo_cntlclk_0 => pc_pc_bo_cntlclk_0, + pc_pc_bo_reset_0 => pc_pc_bo_reset_0, + pc_pc_bo_fcshdata_0 => pc_pc_bo_fcshdata_0, + pc_pc_bo_fcreset_0 => pc_pc_bo_fcreset_0 +); + + +pc_bx_bo_unload <= pc_bo_unload_out; +pc_fu_bo_unload <= pc_bo_unload_out; +pc_iu_bo_unload <= pc_bo_unload_out; +pc_mm_bo_unload <= pc_bo_unload_out; +pc_xu_bo_unload <= pc_bo_unload_out; + +pc_fu_bo_load <= pc_bo_load_out; +pc_xu_bo_load <= pc_bo_load_out; + +pc_bx_bo_repair <= pc_bo_repair_out; +pc_iu_bo_repair <= pc_bo_repair_out; +pc_mm_bo_repair <= pc_bo_repair_out; +pc_xu_bo_repair <= pc_bo_repair_out; + +pc_bx_bo_reset <= pc_bo_reset_out; +pc_fu_bo_reset <= pc_bo_reset_out; +pc_iu_bo_reset <= pc_bo_reset_out; +pc_mm_bo_reset <= pc_bo_reset_out; +pc_xu_bo_reset <= pc_bo_reset_out; + +pc_bx_bo_shdata <= pc_bo_shdata_out; +pc_fu_bo_shdata <= pc_bo_shdata_out; +pc_iu_bo_shdata <= pc_bo_shdata_out; +pc_mm_bo_shdata <= pc_bo_shdata_out; +pc_xu_bo_shdata <= pc_bo_shdata_out; + +pc_bx_bo_select(0 to 3) <= pc_bo_select_out(0 to 3); +pc_fu_bo_select(0 to 1) <= pc_bo_select_out(4 to 5); +pc_iu_bo_select(0 to 4) <= pc_bo_select_out(6 to 10); +pc_mm_bo_select(0 to 4) <= pc_bo_select_out(11 to 15); +pc_xu_bo_select(0 to 8) <= pc_bo_select_out(16 to 24); + +pc_bo_fail_in(0 to 39) <= bx_pc_bo_fail(0 to 3) & fu_pc_bo_fail(0 to 1) & + iu_pc_bo_fail(0 to 4) & mm_pc_bo_fail(0 to 4) & + xu_pc_bo_fail(0 to 8) & x"000" & "000"; + +pc_bo_diagout_in(0 to 39) <= bx_pc_bo_diagout(0 to 3) & fu_pc_bo_diagout(0 to 1) & + iu_pc_bo_diagout(0 to 4) & mm_pc_bo_diagout(0 to 4) & + xu_pc_bo_diagout(0 to 8) & x"000" & "000" ; + + +pcq_psro : entity work.pcq_psro_soft +port map( + vdd => vdd, + gnd => gnd, + pcq_psro_enable => an_ac_psro_enable_dc(0 to 2), + psro_pcq_ringsig => pcq_psro_ringsig_out +); + +u_pcq_psro_rsig_i: pcq_psro_ringsig_i <= not( pcq_psro_ringsig_out ); +u_pcq_psro_rsig_ii: ac_an_psro_ringsig <= not( pcq_psro_ringsig_i ); + + +lcbctrl : entity tri.tri_lcbcntl_mac + generic map( expand_type => expand_type ) + port map( + vdd => vdd, + gnd => gnd, + sg => pc_pc_sg_0, + nclk => nclk, + scan_in => gptr_scan_in, + scan_diag_dc => an_ac_scan_diag_dc, + thold => pc_pc_gptr_sl_thold_0, + clkoff_dc_b => clkoff_dc_b, + delay_lclkr_dc => delay_lclkr_dc(0 to 4), + act_dis_dc => open, + d_mode_dc => d_mode_dc, + mpw1_dc_b => mpw1_dc_b(0 to 4), + mpw2_dc_b => mpw2_dc_b, + scan_out => lcbctrl_gptr_scan_out + ); + + act_dis_dc <= '0'; + + +end pcq; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/pcq_abist.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/pcq_abist.vhdl new file mode 100644 index 0000000..257964e --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/pcq_abist.vhdl @@ -0,0 +1,586 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee, ibm; +use ieee.std_logic_1164.all; +use ibm.std_ulogic_support.all; +library support; +USE support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity pcq_abist is +generic(expand_type : integer := 2 ); +Port (vdd : INOUT power_logic; + gnd : INOUT power_logic; + nclk : In clk_logic; + scan_dis_dc_b : In std_ulogic; + lcb_clkoff_dc_b : In std_ulogic; + lcb_mpw1_dc_b : In std_ulogic; + lcb_mpw2_dc_b : In std_ulogic; + lcb_delay_lclkr_dc : In std_ulogic; + lcb_delay_lclkr_np_dc : In std_ulogic; + lcb_act_dis_dc : In std_ulogic; + lcb_d_mode_dc : In std_ulogic; + gptr_thold : In std_ulogic; + gptr_scan_in : In std_ulogic; + gptr_scan_out : Out std_ulogic; + abist_thold : In std_ulogic; + abist_sg : In std_ulogic; + abist_scan_in : In std_ulogic; + abist_scan_out : Out std_ulogic; + bo_enable : in std_ulogic; + bo_abist_eng_si : in std_ulogic; + abist_done_in_dc : In std_ulogic; + abist_done_out_dc : Out std_ulogic; + abist_mode_dc : In std_ulogic; + abist_start_test : In std_ulogic; + lbist_mode_dc : In std_ulogic; + lbist_ac_mode_dc : In std_ulogic; + pc_bx_abist_di_0 : Out std_ulogic_vector(0 to 3); + pc_bx_abist_ena_dc : Out std_ulogic; + pc_bx_abist_g8t1p_renb_0 : Out std_ulogic; + pc_bx_abist_g8t_bw_0 : Out std_ulogic; + pc_bx_abist_g8t_bw_1 : Out std_ulogic; + pc_bx_abist_g8t_dcomp : Out std_ulogic_vector(0 to 3); + pc_bx_abist_g8t_wenb : Out std_ulogic; + pc_bx_abist_raddr_0 : Out std_ulogic_vector(0 to 9); + pc_bx_abist_raw_dc_b : Out std_ulogic; + pc_bx_abist_waddr_0 : Out std_ulogic_vector(0 to 9); + pc_bx_abist_wl64_g8t_comp_ena : Out std_ulogic; + pc_fu_abist_di_0 : Out std_ulogic_vector(0 to 3); + pc_fu_abist_di_1 : Out std_ulogic_vector(0 to 3); + pc_fu_abist_ena_dc : Out std_ulogic; + pc_fu_abist_grf_renb_0 : Out std_ulogic; + pc_fu_abist_grf_renb_1 : Out std_ulogic; + pc_fu_abist_grf_wenb_0 : Out std_ulogic; + pc_fu_abist_grf_wenb_1 : Out std_ulogic; + pc_fu_abist_raddr_0 : Out std_ulogic_vector(0 to 9); + pc_fu_abist_raddr_1 : Out std_ulogic_vector(0 to 9); + pc_fu_abist_raw_dc_b : Out std_ulogic; + pc_fu_abist_waddr_0 : Out std_ulogic_vector(0 to 9); + pc_fu_abist_waddr_1 : Out std_ulogic_vector(0 to 9); + pc_fu_abist_wl144_comp_ena : Out std_ulogic; + pc_iu_abist_dcomp_g6t_2r : Out std_ulogic_vector(0 to 3); + pc_iu_abist_di_0 : Out std_ulogic_vector(0 to 3); + pc_iu_abist_di_g6t_2r : Out std_ulogic_vector(0 to 3); + pc_iu_abist_ena_dc : Out std_ulogic; + pc_iu_abist_g6t_bw : Out std_ulogic_vector(0 to 1); + pc_iu_abist_g6t_r_wb : Out std_ulogic; + pc_iu_abist_g8t1p_renb_0 : Out std_ulogic; + pc_iu_abist_g8t_bw_0 : Out std_ulogic; + pc_iu_abist_g8t_bw_1 : Out std_ulogic; + pc_iu_abist_g8t_dcomp : Out std_ulogic_vector(0 to 3); + pc_iu_abist_g8t_wenb : Out std_ulogic; + pc_iu_abist_raddr_0 : Out std_ulogic_vector(0 to 9); + pc_iu_abist_raw_dc_b : Out std_ulogic; + pc_iu_abist_waddr_0 : Out std_ulogic_vector(0 to 9); + pc_iu_abist_wl128_g8t_comp_ena : Out std_ulogic; + pc_iu_abist_wl256_comp_ena : Out std_ulogic; + pc_iu_abist_wl64_g8t_comp_ena : Out std_ulogic; + pc_mm_abist_dcomp_g6t_2r : Out std_ulogic_vector(0 to 3); + pc_mm_abist_di_0 : Out std_ulogic_vector(0 to 3); + pc_mm_abist_di_g6t_2r : Out std_ulogic_vector(0 to 3); + pc_mm_abist_ena_dc : Out std_ulogic; + pc_mm_abist_g6t_r_wb : Out std_ulogic; + pc_mm_abist_g8t1p_renb_0 : Out std_ulogic; + pc_mm_abist_g8t_bw_0 : Out std_ulogic; + pc_mm_abist_g8t_bw_1 : Out std_ulogic; + pc_mm_abist_g8t_dcomp : Out std_ulogic_vector(0 to 3); + pc_mm_abist_g8t_wenb : Out std_ulogic; + pc_mm_abist_raddr_0 : Out std_ulogic_vector(0 to 9); + pc_mm_abist_raw_dc_b : Out std_ulogic; + pc_mm_abist_waddr_0 : Out std_ulogic_vector(0 to 9); + pc_mm_abist_wl128_g8t_comp_ena : Out std_ulogic; + pc_xu_abist_dcomp_g6t_2r : Out std_ulogic_vector(0 to 3); + pc_xu_abist_di_0 : Out std_ulogic_vector(0 to 3); + pc_xu_abist_di_1 : Out std_ulogic_vector(0 to 3); + pc_xu_abist_di_g6t_2r : Out std_ulogic_vector(0 to 3); + pc_xu_abist_ena_dc : Out std_ulogic; + pc_xu_abist_g6t_bw : Out std_ulogic_vector(0 to 1); + pc_xu_abist_g6t_r_wb : Out std_ulogic; + pc_xu_abist_g8t1p_renb_0 : Out std_ulogic; + pc_xu_abist_g8t_bw_0 : Out std_ulogic; + pc_xu_abist_g8t_bw_1 : Out std_ulogic; + pc_xu_abist_g8t_dcomp : Out std_ulogic_vector(0 to 3); + pc_xu_abist_g8t_wenb : Out std_ulogic; + pc_xu_abist_grf_renb_0 : Out std_ulogic; + pc_xu_abist_grf_renb_1 : Out std_ulogic; + pc_xu_abist_grf_wenb_0 : Out std_ulogic; + pc_xu_abist_grf_wenb_1 : Out std_ulogic; + pc_xu_abist_raddr_0 : Out std_ulogic_vector(0 to 9); + pc_xu_abist_raddr_1 : Out std_ulogic_vector(0 to 9); + pc_xu_abist_raw_dc_b : Out std_ulogic; + pc_xu_abist_waddr_0 : Out std_ulogic_vector(0 to 9); + pc_xu_abist_waddr_1 : Out std_ulogic_vector(0 to 9); + pc_xu_abist_wl144_comp_ena : Out std_ulogic; + pc_xu_abist_wl32_g8t_comp_ena : Out std_ulogic; + pc_xu_abist_wl512_comp_ena : Out std_ulogic +); + +-- synopsys translate_off + + + + +-- synopsys translate_on +end pcq_abist; + +architecture pcq_abist of pcq_abist is + + +constant staging1_size : positive := 1; +constant staging2_size : positive := 73; +constant staging3_size : positive := 42; +constant staging4_size : positive := 44; +constant staging1_offset : natural := 0; +constant staging2_offset : natural := staging1_offset + staging1_size; +constant staging3_offset : natural := staging2_offset + staging2_size; +constant staging4_offset : natural := staging3_offset + staging3_size; +constant abst_right : natural := staging4_offset + staging4_size - 1; + +signal abist_start_test_q : std_ulogic; +signal force_abist : std_ulogic; +signal abist_thold_b : std_ulogic; +signal abist_engine_so : std_ulogic; +signal abst_siv, abst_sov : std_ulogic_vector(0 to abst_right); + +signal abist_raddr_0 : std_ulogic_vector(0 to 9); +signal abist_raddr_1 : std_ulogic_vector(0 to 9); +signal abist_grf_renb_0 : std_ulogic; +signal abist_grf_renb_1 : std_ulogic; +signal abist_g8t1p_renb_0 : std_ulogic; +signal abist_waddr_0 : std_ulogic_vector(0 to 9); +signal abist_waddr_1 : std_ulogic_vector(0 to 9); +signal abist_grf_wenb_0 : std_ulogic; +signal abist_grf_wenb_1 : std_ulogic; +signal abist_g8t_wenb : std_ulogic; +signal abist_di_0 : std_ulogic_vector(0 to 3); +signal abist_di_1 : std_ulogic_vector(0 to 3); +signal abist_di_g6t_2r : std_ulogic_vector(0 to 3); +signal abist_g6t_r_wb : std_ulogic; +signal abist_dcomp : std_ulogic_vector(0 to 3); +signal abist_dcomp_g6t_2r : std_ulogic_vector(0 to 3); +signal abist_wl32_g8t_comp_ena : std_ulogic; +signal abist_wl64_g8t_comp_ena : std_ulogic; +signal abist_wl128_g8t_comp_ena : std_ulogic; +signal abist_wl144_comp_ena : std_ulogic; +signal abist_wl256_comp_ena : std_ulogic; +signal abist_wl512_comp_ena : std_ulogic; +signal abist_bw_0 : std_ulogic; +signal abist_bw_1 : std_ulogic; + +signal abist_raddr_0_q : std_ulogic_vector(0 to 9); +signal abist_raddr_1_q : std_ulogic_vector(0 to 9); +signal abist_grf_renb_0_q : std_ulogic; +signal abist_grf_renb_1_q : std_ulogic; +signal abist_g8t1p_renb_0_q : std_ulogic; +signal abist_waddr_0_q : std_ulogic_vector(0 to 9); +signal abist_waddr_1_q : std_ulogic_vector(0 to 9); +signal abist_grf_wenb_0_q : std_ulogic; +signal abist_grf_wenb_1_q : std_ulogic; +signal abist_g8t_wenb_q : std_ulogic; +signal abist_di_0_q : std_ulogic_vector(0 to 3); +signal abist_di_1_q : std_ulogic_vector(0 to 3); +signal abist_di_g6t_2r_q : std_ulogic_vector(0 to 3); +signal abist_g6t_r_wb_q : std_ulogic; +signal abist_dcomp_q : std_ulogic_vector(0 to 3); +signal abist_dcomp_g6t_2r_q : std_ulogic_vector(0 to 3); +signal abist_wl32_g8t_comp_ena_q : std_ulogic; +signal abist_wl64_g8t_comp_ena_q : std_ulogic; +signal abist_wl144_comp_ena_q : std_ulogic; +signal abist_wl512_comp_ena_q : std_ulogic; +signal abist_bw_0_q : std_ulogic; +signal abist_bw_1_q : std_ulogic; +signal abist_ena_dc : std_ulogic; +signal abist_raw_dc_b : std_ulogic; + +signal mm_abist_waddr_0_q : std_ulogic_vector(0 to 9); +signal mm_abist_g8t_wenb_q : std_ulogic; +signal mm_abist_raddr_0_q : std_ulogic_vector(0 to 9); +signal mm_abist_g8t1p_renb_0_q : std_ulogic; +signal mm_abist_g6t_r_wb_q : std_ulogic; +signal mm_abist_di_0_q : std_ulogic_vector(0 to 3); +signal mm_abist_di_g6t_2r_q : std_ulogic_vector(0 to 3); +signal mm_abist_bw_0_q : std_ulogic; +signal mm_abist_bw_1_q : std_ulogic; +signal mm_abist_wl128_g8t_comp_ena_q : std_ulogic; +signal mm_abist_dcomp_q : std_ulogic_vector(0 to 3); +signal mm_abist_dcomp_g6t_2r_q : std_ulogic_vector(0 to 3); + +signal iu_abist_waddr_0_q : std_ulogic_vector(0 to 9); +signal iu_abist_g8t_wenb_q : std_ulogic; +signal iu_abist_raddr_0_q : std_ulogic_vector(0 to 9); +signal iu_abist_g8t1p_renb_0_q : std_ulogic; +signal iu_abist_g6t_r_wb_q : std_ulogic; +signal iu_abist_di_0_q : std_ulogic_vector(0 to 3); +signal iu_abist_di_g6t_2r_q : std_ulogic_vector(0 to 3); +signal iu_abist_bw_0_q : std_ulogic; +signal iu_abist_bw_1_q : std_ulogic; +signal iu_abist_wl64_g8t_comp_ena_q : std_ulogic; +signal iu_abist_wl128_g8t_comp_ena_q : std_ulogic; +signal iu_abist_wl256_comp_ena_q : std_ulogic; +signal iu_abist_dcomp_q : std_ulogic_vector(0 to 3); +signal iu_abist_dcomp_g6t_2r_q : std_ulogic_vector(0 to 3); + + +begin + + +abist_engine: entity tri.tri_caa_prism_abist + port map ( abist_done_in_dc => abist_done_in_dc + , abist_done_out_dc => abist_done_out_dc + , abist_mode_dc => abist_mode_dc + , lbist_mode_dc => lbist_mode_dc + , lbist_ac_mode_dc => lbist_ac_mode_dc + + , abist_waddr_0 => abist_waddr_0(0 to 9) + , abist_waddr_1 => abist_waddr_1(0 to 9) + , abist_grf_wenb_0 => abist_grf_wenb_0 + , abist_grf_wenb_1 => abist_grf_wenb_1 + , abist_raddr_0 => abist_raddr_0(0 to 9) + , abist_raddr_1 => abist_raddr_1(0 to 9) + , abist_grf_renb_0 => abist_grf_renb_0 + , abist_grf_renb_1 => abist_grf_renb_1 + , abist_g8t_wenb => abist_g8t_wenb + , abist_g8t1p_renb_0 => abist_g8t1p_renb_0 + , abist_g6t_r_wb => abist_g6t_r_wb + , abist_di_g6t_2r => abist_di_g6t_2r(0 to 3) + , abist_di_0 => abist_di_0(0 to 3) + , abist_di_1 => abist_di_1(0 to 3) + , abist_dcomp => abist_dcomp(0 to 3) + , abist_dcomp_g6t_2r => abist_dcomp_g6t_2r(0 to 3) + , abist_bw_0 => abist_bw_0 + , abist_bw_1 => abist_bw_1 + , abist_wl32_g8t_comp_ena => abist_wl32_g8t_comp_ena + , abist_wl64_g8t_comp_ena => abist_wl64_g8t_comp_ena + , abist_wl128_g8t_comp_ena => abist_wl128_g8t_comp_ena + , abist_wl144_comp_ena => abist_wl144_comp_ena + , abist_wl256_comp_ena => abist_wl256_comp_ena + , abist_wl512_comp_ena => abist_wl512_comp_ena + , abist_ena_dc => abist_ena_dc + , abist_raw_dc_b => abist_raw_dc_b + + , lcb_clkoff_dc_b => lcb_clkoff_dc_b + , lcb_act_dis_dc => lcb_act_dis_dc + , lcb_d_mode_dc => lcb_d_mode_dc + , lcb_delay_lclkr_dc => lcb_delay_lclkr_dc + , lcb_delay_lclkr_np_dc => lcb_delay_lclkr_np_dc + , lcb_mpw1_dc_b => lcb_mpw1_dc_b + , lcb_mpw2_dc_b => lcb_mpw2_dc_b + , abist_scan_in => abst_sov(abst_right) + , abist_scan_out => abist_engine_so + , abist_sg => abist_sg + , abist_thold => abist_thold + , gptr_scan_in => gptr_scan_in + , gptr_scan_out => gptr_scan_out + , gptr_thold => gptr_thold + , nclk => nclk + , abist_start_test => abist_start_test_q + , scan_dis_dc_b => scan_dis_dc_b + , vdd => vdd + , gnd => gnd + ); + + + lcbor_abist: tri_lcbor + generic map (expand_type => expand_type ) + port map ( clkoff_b => lcb_clkoff_dc_b, + thold => abist_thold, + sg => abist_sg, + act_dis => lcb_act_dis_dc, + forcee => force_abist, + thold_b => abist_thold_b ); + + abist_start_repower: tri_rlmreg_p + generic map (width => staging1_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => '1', + thold_b => abist_thold_b, + sg => abist_sg, + forcee => force_abist, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => abst_siv(staging1_offset to staging1_offset + staging1_size-1), + scout => abst_sov(staging1_offset to staging1_offset + staging1_size-1), + din(0) => abist_start_test, + dout(0) => abist_start_test_q ); + + abist_eng_repower: tri_rlmreg_p + generic map (width => staging2_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => abist_mode_dc, + thold_b => abist_thold_b, + sg => abist_sg, + forcee => force_abist, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => abst_siv(staging2_offset to staging2_offset + staging2_size-1), + scout => abst_sov(staging2_offset to staging2_offset + staging2_size-1), + din(0) => abist_grf_wenb_0, + din(1) => abist_grf_wenb_1, + din(2) => abist_g8t_wenb, + din(3) => abist_grf_renb_0, + din(4) => abist_grf_renb_1, + din(5) => abist_g8t1p_renb_0, + din(6) => abist_g6t_r_wb, + din(7) => abist_bw_0, + din(8) => abist_bw_1, + din(9) => abist_wl32_g8t_comp_ena, + din(10) => abist_wl64_g8t_comp_ena, + din(11) => abist_wl144_comp_ena, + din(12) => abist_wl512_comp_ena, + din(13 to 22) => abist_waddr_0, + din(23 to 32) => abist_waddr_1, + din(33 to 42) => abist_raddr_0, + din(43 to 52) => abist_raddr_1, + din(53 to 56) => abist_di_0, + din(57 to 60) => abist_di_1, + din(61 to 64) => abist_di_g6t_2r, + din(65 to 68) => abist_dcomp, + din(69 to 72) => abist_dcomp_g6t_2r, + dout(0) => abist_grf_wenb_0_q, + dout(1) => abist_grf_wenb_1_q, + dout(2) => abist_g8t_wenb_q, + dout(3) => abist_grf_renb_0_q, + dout(4) => abist_grf_renb_1_q, + dout(5) => abist_g8t1p_renb_0_q, + dout(6) => abist_g6t_r_wb_q, + dout(7) => abist_bw_0_q, + dout(8) => abist_bw_1_q, + dout(9) => abist_wl32_g8t_comp_ena_q, + dout(10) => abist_wl64_g8t_comp_ena_q, + dout(11) => abist_wl144_comp_ena_q, + dout(12) => abist_wl512_comp_ena_q, + dout(13 to 22) => abist_waddr_0_q, + dout(23 to 32) => abist_waddr_1_q, + dout(33 to 42) => abist_raddr_0_q, + dout(43 to 52) => abist_raddr_1_q, + dout(53 to 56) => abist_di_0_q, + dout(57 to 60) => abist_di_1_q, + dout(61 to 64) => abist_di_g6t_2r_q, + dout(65 to 68) => abist_dcomp_q, + dout(69 to 72) => abist_dcomp_g6t_2r_q ); + + abist_mm_repower: tri_rlmreg_p + generic map (width => staging3_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => abist_mode_dc, + thold_b => abist_thold_b, + sg => abist_sg, + forcee => force_abist, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => abst_siv(staging3_offset to staging3_offset + staging3_size-1), + scout => abst_sov(staging3_offset to staging3_offset + staging3_size-1), + din(0) => abist_g8t_wenb, + din(1) => abist_g8t1p_renb_0, + din(2) => abist_g6t_r_wb, + din(3) => abist_bw_0, + din(4) => abist_bw_1, + din(5) => abist_wl128_g8t_comp_ena, + din(6 to 15) => abist_waddr_0, + din(16 to 25) => abist_raddr_0, + din(26 to 29) => abist_di_0, + din(30 to 33) => abist_di_g6t_2r, + din(34 to 37) => abist_dcomp, + din(38 to 41) => abist_dcomp_g6t_2r, + dout(0) => mm_abist_g8t_wenb_q, + dout(1) => mm_abist_g8t1p_renb_0_q, + dout(2) => mm_abist_g6t_r_wb_q, + dout(3) => mm_abist_bw_0_q, + dout(4) => mm_abist_bw_1_q, + dout(5) => mm_abist_wl128_g8t_comp_ena_q, + dout(6 to 15) => mm_abist_waddr_0_q, + dout(16 to 25) => mm_abist_raddr_0_q, + dout(26 to 29) => mm_abist_di_0_q, + dout(30 to 33) => mm_abist_di_g6t_2r_q, + dout(34 to 37) => mm_abist_dcomp_q, + dout(38 to 41) => mm_abist_dcomp_g6t_2r_q ); + + abist_iu_repower: tri_rlmreg_p + generic map (width => staging4_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => abist_mode_dc, + thold_b => abist_thold_b, + sg => abist_sg, + forcee => force_abist, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => abst_siv(staging4_offset to staging4_offset + staging4_size-1), + scout => abst_sov(staging4_offset to staging4_offset + staging4_size-1), + din(0) => abist_g8t_wenb, + din(1) => abist_g8t1p_renb_0, + din(2) => abist_g6t_r_wb, + din(3) => abist_bw_0, + din(4) => abist_bw_1, + din(5) => abist_wl64_g8t_comp_ena, + din(6) => abist_wl128_g8t_comp_ena, + din(7) => abist_wl256_comp_ena, + din(8 to 17) => abist_waddr_0, + din(18 to 27) => abist_raddr_0, + din(28 to 31) => abist_di_0, + din(32 to 35) => abist_di_g6t_2r, + din(36 to 39) => abist_dcomp, + din(40 to 43) => abist_dcomp_g6t_2r, + dout(0) => iu_abist_g8t_wenb_q, + dout(1) => iu_abist_g8t1p_renb_0_q, + dout(2) => iu_abist_g6t_r_wb_q, + dout(3) => iu_abist_bw_0_q, + dout(4) => iu_abist_bw_1_q, + dout(5) => iu_abist_wl64_g8t_comp_ena_q, + dout(6) => iu_abist_wl128_g8t_comp_ena_q, + dout(7) => iu_abist_wl256_comp_ena_q, + dout(8 to 17) => iu_abist_waddr_0_q, + dout(18 to 27) => iu_abist_raddr_0_q, + dout(28 to 31) => iu_abist_di_0_q, + dout(32 to 35) => iu_abist_di_g6t_2r_q, + dout(36 to 39) => iu_abist_dcomp_q, + dout(40 to 43) => iu_abist_dcomp_g6t_2r_q ); + + abst_siv(0 TO abst_right-1) <= (abist_scan_in and not bo_enable) & abst_sov(0 to abst_right-2); + abst_siv(abst_right) <= bo_abist_eng_si when bo_enable='1' else abst_sov(abst_right-1); + abist_scan_out <= abist_engine_so and scan_dis_dc_b; + + + + pc_bx_abist_waddr_0 <= abist_waddr_0_q(0 to 9); + pc_iu_abist_waddr_0 <= iu_abist_waddr_0_q(0 to 9); + pc_fu_abist_waddr_0 <= abist_waddr_0_q(0 to 9); + pc_mm_abist_waddr_0 <= mm_abist_waddr_0_q(0 to 9); + pc_xu_abist_waddr_0 <= abist_waddr_0_q(0 to 9); + + pc_fu_abist_waddr_1 <= abist_waddr_1_q(0 to 9); + pc_xu_abist_waddr_1 <= abist_waddr_1_q(0 to 9); + + pc_fu_abist_grf_wenb_0 <= abist_grf_wenb_0_q; + pc_xu_abist_grf_wenb_0 <= abist_grf_wenb_0_q; + + pc_fu_abist_grf_wenb_1 <= abist_grf_wenb_1_q; + pc_xu_abist_grf_wenb_1 <= abist_grf_wenb_1_q; + + pc_bx_abist_g8t_wenb <= abist_g8t_wenb_q; + pc_iu_abist_g8t_wenb <= iu_abist_g8t_wenb_q; + pc_mm_abist_g8t_wenb <= mm_abist_g8t_wenb_q; + pc_xu_abist_g8t_wenb <= abist_g8t_wenb_q; + + pc_bx_abist_raddr_0 <= abist_raddr_0_q(0 to 9); + pc_iu_abist_raddr_0 <= iu_abist_raddr_0_q(0 to 9); + pc_fu_abist_raddr_0 <= abist_raddr_0_q(0 to 9); + pc_mm_abist_raddr_0 <= mm_abist_raddr_0_q(0 to 9); + pc_xu_abist_raddr_0 <= abist_raddr_0_q(0 to 9); + + pc_fu_abist_raddr_1 <= abist_raddr_1_q(0 to 9); + pc_xu_abist_raddr_1 <= abist_raddr_1_q(0 to 9); + + pc_fu_abist_grf_renb_0 <= abist_grf_renb_0_q; + pc_xu_abist_grf_renb_0 <= abist_grf_renb_0_q; + + pc_fu_abist_grf_renb_1 <= abist_grf_renb_1_q; + pc_xu_abist_grf_renb_1 <= abist_grf_renb_1_q; + + pc_bx_abist_g8t1p_renb_0 <= abist_g8t1p_renb_0_q; + pc_iu_abist_g8t1p_renb_0 <= iu_abist_g8t1p_renb_0_q; + pc_mm_abist_g8t1p_renb_0 <= mm_abist_g8t1p_renb_0_q; + pc_xu_abist_g8t1p_renb_0 <= abist_g8t1p_renb_0_q; + + pc_iu_abist_g6t_r_wb <= iu_abist_g6t_r_wb_q; + pc_mm_abist_g6t_r_wb <= mm_abist_g6t_r_wb_q; + pc_xu_abist_g6t_r_wb <= abist_g6t_r_wb_q; + + pc_bx_abist_di_0 <= abist_di_0_q(0 to 3); + pc_iu_abist_di_0 <= iu_abist_di_0_q(0 to 3); + pc_fu_abist_di_0 <= abist_di_0_q(0 to 3); + pc_mm_abist_di_0 <= mm_abist_di_0_q(0 to 3); + pc_xu_abist_di_0 <= abist_di_0_q(0 to 3); + + pc_fu_abist_di_1 <= abist_di_1_q(0 to 3); + pc_xu_abist_di_1 <= abist_di_1_q(0 to 3); + + pc_iu_abist_di_g6t_2r <= iu_abist_di_g6t_2r_q(0 to 3); + pc_mm_abist_di_g6t_2r <= mm_abist_di_g6t_2r_q(0 to 3); + pc_xu_abist_di_g6t_2r <= abist_di_g6t_2r_q(0 to 3); + + pc_bx_abist_g8t_bw_0 <= abist_bw_0_q; + pc_iu_abist_g8t_bw_0 <= iu_abist_bw_0_q; + pc_mm_abist_g8t_bw_0 <= mm_abist_bw_0_q; + pc_xu_abist_g8t_bw_0 <= abist_bw_0_q; + + pc_bx_abist_g8t_bw_1 <= abist_bw_1_q; + pc_iu_abist_g8t_bw_1 <= iu_abist_bw_1_q; + pc_mm_abist_g8t_bw_1 <= mm_abist_bw_1_q; + pc_xu_abist_g8t_bw_1 <= abist_bw_1_q; + + pc_iu_abist_g6t_bw <= iu_abist_bw_0_q & iu_abist_bw_1_q; + pc_xu_abist_g6t_bw <= abist_bw_0_q & abist_bw_1_q; + + pc_xu_abist_wl32_g8t_comp_ena <= abist_wl32_g8t_comp_ena_q; + pc_bx_abist_wl64_g8t_comp_ena <= abist_wl64_g8t_comp_ena_q; + pc_iu_abist_wl64_g8t_comp_ena <= iu_abist_wl64_g8t_comp_ena_q; + pc_iu_abist_wl128_g8t_comp_ena <= iu_abist_wl128_g8t_comp_ena_q; + pc_mm_abist_wl128_g8t_comp_ena <= mm_abist_wl128_g8t_comp_ena_q; + pc_fu_abist_wl144_comp_ena <= abist_wl144_comp_ena_q; + pc_xu_abist_wl144_comp_ena <= abist_wl144_comp_ena_q; + pc_iu_abist_wl256_comp_ena <= iu_abist_wl256_comp_ena_q; + pc_xu_abist_wl512_comp_ena <= abist_wl512_comp_ena_q; + + pc_bx_abist_g8t_dcomp <= abist_dcomp_q(0 to 3); + pc_iu_abist_g8t_dcomp <= iu_abist_dcomp_q(0 to 3); + pc_mm_abist_g8t_dcomp <= mm_abist_dcomp_q(0 to 3); + pc_xu_abist_g8t_dcomp <= abist_dcomp_q(0 to 3); + + pc_iu_abist_dcomp_g6t_2r <= iu_abist_dcomp_g6t_2r_q(0 to 3); + pc_mm_abist_dcomp_g6t_2r <= mm_abist_dcomp_g6t_2r_q(0 to 3); + pc_xu_abist_dcomp_g6t_2r <= abist_dcomp_g6t_2r_q(0 to 3); + + pc_bx_abist_ena_dc <= abist_ena_dc; + pc_iu_abist_ena_dc <= abist_ena_dc; + pc_fu_abist_ena_dc <= abist_ena_dc; + pc_mm_abist_ena_dc <= abist_ena_dc; + pc_xu_abist_ena_dc <= abist_ena_dc; + + pc_bx_abist_raw_dc_b <= abist_raw_dc_b; + pc_iu_abist_raw_dc_b <= abist_raw_dc_b; + pc_fu_abist_raw_dc_b <= abist_raw_dc_b; + pc_mm_abist_raw_dc_b <= abist_raw_dc_b; + pc_xu_abist_raw_dc_b <= abist_raw_dc_b; + + +end pcq_abist; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/pcq_abist_bolton_frontend.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/pcq_abist_bolton_frontend.vhdl new file mode 100644 index 0000000..0f24cc9 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/pcq_abist_bolton_frontend.vhdl @@ -0,0 +1,774 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee; +use ieee.std_logic_1164.all; +library ibm; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; +library support; +use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity pcq_abist_bolton_frontend is + generic( + expand_type : integer := 2; + num_backends : integer := 44); + port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + + bcreset : in std_ulogic; + bcdata : in std_ulogic; + bcshcntl : in std_ulogic; + bcshdata : in std_ulogic; + bcexe : in std_ulogic; + bcsysrepair : in std_ulogic; + bo_enable : in std_ulogic; + bo_go : in std_ulogic; + + donein : in std_ulogic; + sdin : in std_ulogic; + doneout : out std_ulogic; + sdout : out std_ulogic; + diagloop_out : out std_ulogic; + waitin : in std_ulogic; + failin : in std_ulogic; + waitout : out std_ulogic; + failout : out std_ulogic; + + abist_done : in std_ulogic; + abist_start_test_int : out std_ulogic; + abist_start_test : in std_ulogic; + abist_si : out std_ulogic; + abist_mode_dc : in std_ulogic; + abist_mode_dc_int : out std_ulogic; + + bo_unload : out std_ulogic; + bo_load : out std_ulogic; + bo_repair : out std_ulogic; + bo_reset : out std_ulogic; + bo_shdata : out std_ulogic; + bo_select : out std_ulogic_vector(0 to num_backends-1); + bo_fail : in std_ulogic_vector(0 to num_backends-1); + bo_diagout : in std_ulogic_vector(0 to num_backends-1); + + lbist_ac_mode_dc : in std_ulogic; + ck_bo_sl_thold_6 : in std_ulogic; + ck_bo_sl_thold_0 : in std_ulogic; + ck_bo_sg_0 : in std_ulogic; + lcb_mpw1_dc_b : in std_ulogic; + lcb_mpw2_dc_b : in std_ulogic; + lcb_delay_lclkr_dc : in std_ulogic; + lcb_clkoff_dc_b : in std_ulogic; + lcb_act_dis_dc : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + bo_pc_abst_sl_thold_6 : out std_ulogic; + bo_pc_pc_abst_sl_thold_6 : out std_ulogic; + bo_pc_ary_nsl_thold_6 : out std_ulogic; + bo_pc_func_sl_thold_6 : out std_ulogic; + bo_pc_time_sl_thold_6 : out std_ulogic; + bo_pc_repr_sl_thold_6 : out std_ulogic; + bo_pc_sg_6 : out std_ulogic); + +-- synopsys translate_off + + +-- synopsys translate_on +end pcq_abist_bolton_frontend; + +architecture pcq_abist_bolton_frontend of pcq_abist_bolton_frontend is + + subtype Rstate is integer range 0 to 13; + subtype Tstate is std_ulogic_vector(Rstate); + subtype Renum is integer range 0 to 11; + subtype Tenum is std_ulogic_vector(Renum); + subtype Rinstruction is integer range 0 to 19; + subtype Tinstruction is std_ulogic_vector(Rinstruction); + subtype Rmode is integer range Rinstruction'right-19 to Rinstruction'right-17; + subtype Tmode is std_ulogic_vector(Rmode); + + constant Rkind : integer := Rinstruction'right-16; + constant Rloop : integer := Rinstruction'right-10; + constant Raccumulate : integer := Rinstruction'right-7; + constant RFARR : integer := Rinstruction'right-1; + constant Rmfctmode : integer := Rinstruction'right; + + subtype Tkind is std_ulogic; + subtype Raddr is integer range Rinstruction'right-15 to Rinstruction'right-4; + subtype Taddr is std_ulogic_vector(Raddr); + subtype Rw_addr is integer range Rinstruction'right-3 to Rinstruction'right; + subtype Tw_addr is std_ulogic_vector(0 to 3); + subtype Rr_addr is integer range Rinstruction'right-7 to Rinstruction'right; + subtype Tr_addr is std_ulogic_vector(0 to 7); + subtype Tshuttle is std_ulogic_vector(bo_fail'range); + subtype Tmemmask is Tshuttle; + subtype Tcounter is std_ulogic_vector(0 to 11); + subtype Tdiagptr is std_ulogic_vector(0 to 7); + + constant Rdiagptr_enable : integer := 0; + constant Rdiagptr_override : integer := 7; + + subtype Rbackend_select is integer range 1 to 6; + subtype Tdiagdecr is std_ulogic_vector(0 to 31); + subtype Rdiagdecr is integer range Tdiagdecr'right-29 to Tdiagdecr'right; + constant Rdiagdecr_enable : integer := Tdiagdecr'right-30; + constant Rdiagdecr_evs : integer := Tdiagdecr'right-31; + + constant type_num : std_ulogic_vector(0 to 11) := X"129"; + constant fareg_length : Tcounter := X"020"; + constant max_sticky_length : Tcounter := X"240"; + constant warmup_length : Tcounter := X"010"; + + constant scan_offset_0 : integer := 0; + constant scan_offset_1 : integer := scan_offset_0 + 7; + constant scan_offset_2 : integer := scan_offset_1 + 3; + constant scan_offset_3 : integer := scan_offset_2 + Tstate'length + 3; + constant scan_offset_4 : integer := scan_offset_3 + Tenum'length; + constant scan_offset_5 : integer := scan_offset_4 + Tinstruction'length; + constant scan_offset_6 : integer := scan_offset_5 + Tshuttle'length; + constant scan_offset_7 : integer := scan_offset_6 + Tcounter'length; + constant scan_offset_8 : integer := scan_offset_7 + Tdiagptr'length; + constant scan_offset_9 : integer := scan_offset_8 + 1; + constant scan_offset_10 : integer := scan_offset_9 + Tmemmask'length; + constant scan_offset_11 : integer := scan_offset_10 + 1; + constant scan_offset_12 : integer := scan_offset_11 + Tdiagdecr'length; + constant scan_offset_13 : integer := scan_offset_12 + 2; + constant scan_offset_14 : integer := scan_offset_13 + bo_fail'length; + subtype Tint_scan is std_ulogic_vector(0 to scan_offset_14-1); + + type sul_bool is array(boolean) of std_ulogic; + constant pos : sul_bool := ( + false => '0' , + true => '1'); + + constant SC_IDLE : integer := 0; + constant SC_ENUM : integer := 1; + constant SC_WRITE : integer := 2; + constant SC_READ : integer := 3; + constant SC_IRLOAD : integer := 4; + constant SC_DIAGROT : integer := 5; + constant SC_0 : integer := 6; + constant SC_1 : integer := 7; + constant SC_2 : integer := 8; + constant SC_3PRE : integer := 9; + constant SC_3 : integer := 10; + constant SC_4 : integer := 11; + constant SC_RUNBST : integer := 12; + constant SC_CLEAR : integer := 13; + constant SM_IDLE : Tstate := "10000000000000"; + constant SM_ENUM : Tstate := "01000000000000"; + constant SM_WRITE : Tstate := "00100000000000"; + constant SM_READ : Tstate := "00010000000000"; + constant SM_IRLOAD : Tstate := "00001000000000"; + constant SM_DIAGROT : Tstate := "00000100000000"; + constant SM_0 : Tstate := "00000010000000"; + constant SM_1 : Tstate := "00000001000000"; + constant SM_2 : Tstate := "00000000100000"; + constant SM_3PRE : Tstate := "00000000010000"; + constant SM_3 : Tstate := "00000000001000"; + constant SM_4 : Tstate := "00000000000100"; + constant SM_RUNBST : Tstate := "00000000000010"; + constant SM_CLEAR : Tstate := "00000000000001"; + constant MODE_RUN : Tmode := "000"; + constant MODE_ENUM : Tmode := "001"; + constant MODE_READ : Tmode := "010"; + constant MODE_WRITE : Tmode := "011"; + constant ADDR_BISTMASK : Tw_addr := X"0"; + constant ADDR_MEMMASK : Tw_addr := X"1"; + constant ADDR_DIAGPTR : Tw_addr := X"2"; + constant ADDR_RBISTMASK : Tr_addr := X"00"; + constant ADDR_RMEMMASK : Tr_addr := X"01"; + constant ADDR_RDIAGPTR : Tr_addr := X"02"; + constant ADDR_ABIST : Tw_addr := X"B"; + constant ADDR_TIMING : Tw_addr := X"C"; + constant ADDR_SIGNATURE : Tw_addr := X"D"; + constant ADDR_DIAGCOUNT : Tw_addr := X"E"; + constant ADDR_RDIAGCOUNT : Tr_addr := X"0E"; + constant ADDR_TYPE : Tr_addr := X"10"; + constant ADDR_ENUM : Tr_addr := X"11"; + constant ADDR_BISTDONE : Tr_addr := X"12"; + constant ADDR_WAIT : Tr_addr := X"13"; + constant ADDR_FAIL : Tr_addr := X"14"; + + + + signal state_q, state_d : Tstate; + signal instruction_d, instruction_q : Tinstruction; + signal shift_instruction, shift_write : std_ulogic; + signal shuttle_select, shuttle_d, shuttle_q : Tshuttle; + signal shift_shuttle : std_ulogic; + signal enum_d, enum_q : Tenum; + signal clear_enum, count_enum : std_ulogic; + signal mode : Tmode; + signal kind : Tkind; + signal addr : Taddr; + signal w_reg_addr : Tw_addr; + signal r_reg_addr : Tr_addr; + signal reg_select : std_ulogic; + signal s_idle, s_enum, s_write, s_read, s_irload, + s_diagrot, s_0, s_1, s_2, s_3pre, s_3, s_4, s_runbst, s_clear : std_ulogic; + signal s_3pre_delayed, s_3_delayed, s_4_delayed : std_ulogic; + signal bistmask_d, bistmask_q, shift_bistmask : std_ulogic; + signal bistdone_q, bistdone_d : std_ulogic; + signal memmask_d, memmask_q : Tmemmask; + signal shift_memmask : std_ulogic; + + signal done_d, done_q, wait_d, wait_q, fail_d, fail_q : std_ulogic; + signal bcshctrl_ff, bcdata_ff, bcshdata_ff, bcexe_ff, bcreset_ff, bo_go_ff, bcsysrepair_ff : std_ulogic; + signal write_signature, write_timing : std_ulogic; + signal int_scan_in, int_scan_out : Tint_scan; + signal ck_bo_sl_thold_0_b : std_ulogic; + signal force_func : std_ulogic; + signal count_d, count_q : Tcounter; + signal count_done : std_ulogic; + + signal diagptr_q, diagptr_d : Tdiagptr; + signal shift_diagptr : std_ulogic; + signal diagmux_and : std_ulogic_vector(bo_diagout'range); + signal bo_select_int : std_ulogic_vector(bo_select'range); + signal sg_int : std_ulogic; + signal diagdecr_q, diagdecr_d : Tdiagdecr; + signal shift_diagcount, diagdecr_zero : std_ulogic; + signal diagloop_out_d, diagloop_out_int : std_ulogic; + signal write_abist_q, write_abist_d : std_ulogic; + signal bo_fail_ff, bo_fail_pre : std_ulogic_vector(0 to num_backends-1); + +begin + + sg_int <= '0' when bo_enable = '1' else ck_bo_sg_0; + + shift_shuttle <= bcshdata_ff and ((s_idle and pos(mode = MODE_READ)) or (s_idle and pos(mode = MODE_RUN)) or s_diagrot or s_read) and bo_enable; + + shuttle : process (bistdone_q, bistmask_q, bo_fail_ff, diagdecr_q, diagptr_q, + enum_q, memmask_q, r_reg_addr) is + begin + shuttle_select <= (others => '0'); + case r_reg_addr is + when ADDR_RBISTMASK => shuttle_select(Tshuttle'right) <= bistmask_q; + when ADDR_RMEMMASK => shuttle_select <= memmask_q; + when ADDR_RDIAGPTR => shuttle_select(Tshuttle'right-diagptr_q'right to Tshuttle'right) <= diagptr_q; + when ADDR_RDIAGCOUNT=> shuttle_select(Tshuttle'right-Tdiagdecr'right to Tshuttle'right) <= diagdecr_q; + when ADDR_TYPE => shuttle_select(Tshuttle'right-type_num'right to Tshuttle'right) <= type_num; + when ADDR_ENUM => shuttle_select(Tshuttle'right-Tenum'right to Tshuttle'right) <= enum_q; + when ADDR_BISTDONE => shuttle_select(Tshuttle'right) <= bistdone_q; + when ADDR_FAIL => shuttle_select <= bo_fail_ff; + when others => null; + end case; + end process; + + shuttle_d <= shuttle_q(1 to shuttle_q'right) & sdin when (shift_shuttle and not s_diagrot) = '1' else + shuttle_q(1 to shuttle_q'right) & diagloop_out_int when (shift_shuttle and s_diagrot) = '1' + else shuttle_select; + sdout <= shuttle_q(shuttle_d'left); + + diagmux : for i in bo_diagout'range generate + begin + diagmux_and(i) <= bo_diagout(i) and bo_select_int(i); + end generate; + diagloop_out_int <= or_reduce(diagmux_and) and diagptr_q(Rdiagptr_enable) and s_diagrot; + diagloop_out_d <= diagloop_out_int and not lbist_ac_mode_dc; + + shift_instruction <= bcshctrl_ff and (s_idle or s_irload) and bo_enable; + instruction_d <= instruction_q(1 to instruction_q'right) & bcdata_ff; + abist_si <= bcdata_ff and not bcreset_ff; + shift_write <= ((s_idle and pos(mode = MODE_WRITE)) or s_write) and bcshdata_ff and bo_enable; + shift_diagptr <= shift_write and reg_select and pos(w_reg_addr = ADDR_DIAGPTR) and bo_enable; + diagptr_d <= diagptr_q(1 to diagptr_q'right) & bcdata_ff; + + shift_diagcount <= shift_write and reg_select and pos(w_reg_addr = ADDR_DIAGCOUNT) and bo_enable; + diagdecr_d <= diagdecr_q(1 to diagdecr_q'right) & bcdata_ff + when shift_diagcount = '1' else + diagdecr_q(diagdecr_q'left to Rdiagdecr'left-1) & (diagdecr_q(Rdiagdecr) - 1) + when s_runbst = '1' and diagdecr_q(Rdiagdecr_enable) = '1' else + diagdecr_q; + diagdecr_zero <= pos(diagdecr_q(Rdiagdecr) = 0) and diagdecr_q(Rdiagdecr_enable); + + shift_bistmask <= shift_write and reg_select and pos(w_reg_addr = ADDR_BISTMASK) and bo_enable; + bistmask_d <= bcdata_ff; + + shift_memmask <= shift_write and reg_select and pos(w_reg_addr = ADDR_MEMMASK) and bo_enable; + memmask_d <= memmask_q(1 to memmask_q'right) & bcdata_ff; + + write_timing <= shift_write and reg_select and pos(w_reg_addr = ADDR_TIMING); + write_signature <= shift_write and reg_select and pos(w_reg_addr = ADDR_SIGNATURE); + write_abist_d <= shift_write and reg_select and pos(w_reg_addr = ADDR_ABIST) and not lbist_ac_mode_dc; + + bo_select_decoder : for i in bo_select'range generate + begin + bo_select_int(i) <= (diagptr_q(Rdiagptr_override) or pos(diagptr_q(Rbackend_select) = i)) + and diagptr_q(Rdiagptr_enable); + end generate; + bo_select <= (others => '0') when lbist_ac_mode_dc = '1' else bo_select_int when (shift_write and reg_select) = '1' else not memmask_q; + + bo_repair <= s_4 and not lbist_ac_mode_dc; + bo_unload <= (s_3 or s_3pre) and not lbist_ac_mode_dc; + bo_reset <= bcreset_ff or s_clear or (s_runbst and abist_done) or (s_3pre and count_done) or (s_3 and count_done) or lbist_ac_mode_dc; + bo_shdata <= '0' when lbist_ac_mode_dc = '1' else shuttle_d(shuttle_d'left) when s_diagrot = '1' else bcdata_ff and not bcreset_ff; + bo_load <= (write_signature) and not lbist_ac_mode_dc; + bo_fail_pre <= (others => '0') when lbist_ac_mode_dc = '1' else bo_fail; + + count_done <= pos(count_q = X"000"); + bistdone_d <= '0' when s_0 = '1' or s_clear = '1' else '1' when (s_4 = '1' and count_done = '1') or diagdecr_zero = '1' else bistdone_q; + + clear_enum <= s_idle and bcexe_ff and pos(mode = MODE_ENUM); + count_enum <= s_enum; + enum_d <= (others => '0') when clear_enum = '1' else enum_q + 1 when count_enum = '1' else enum_q; + + done_d <= donein and (bistmask_q or bistdone_q or (s_idle and pos(mode = MODE_ENUM)) or s_enum); + wait_d <= waitin and bistdone_q and diagdecr_q(Rdiagdecr_evs); + fail_d <= failin or (not bistmask_q and s_idle and or_reduce(bo_fail_ff and memmask_q)); + + bo_pc_abst_sl_thold_6 <= ck_bo_sl_thold_6 when (bcreset_ff or s_3_delayed or s_clear)='1' + else '0' when (s_1 or s_2 or s_runbst)='1' and diagdecr_zero='0' + else '1'; + bo_pc_ary_nsl_thold_6 <= not(bcreset_ff or s_2 or s_runbst); + bo_pc_func_sl_thold_6 <= not(s_0 or s_1 or s_2 or s_runbst); + bo_pc_time_sl_thold_6 <= ck_bo_sl_thold_6 when (write_timing)='1' else '1'; + bo_pc_repr_sl_thold_6 <= ck_bo_sl_thold_6 when (s_4_delayed or s_3pre_delayed)='1' else '1'; + + bo_pc_sg_6 <= bcreset_ff or write_abist_q or write_timing or s_4_delayed or s_3_delayed or s_3pre_delayed or s_clear; + abist_start_test_int <= s_runbst and not abist_done when bo_enable='1' else abist_start_test; + bo_pc_pc_abst_sl_thold_6 <= ck_bo_sl_thold_6 when write_abist_q='1' else '0' when (s_1 or s_2 or bcreset_ff or s_runbst)='1' else '1'; + abist_mode_dc_int <= s_0 or s_1 or s_2 or s_runbst when bo_enable='1' else abist_mode_dc; + + trans : process (abist_done, bcexe_ff, bcreset_ff, bcshctrl_ff, bcshdata_ff, + bo_go_ff, count_done, count_q, diagdecr_q(Rdiagdecr_evs), diagdecr_zero, + done_q, instruction_q(Raccumulate), instruction_q(RFARR), + instruction_q(Rloop), mode, state_q, bcsysrepair_ff) is + begin + state_d <= state_q; + count_d <= count_q - 1; + case state_q is + when SM_IDLE => + if (bcshctrl_ff = '1') then + state_d <= SM_IRLOAD; + else + case mode is + when MODE_ENUM => if bcexe_ff = '1' then state_d <= SM_ENUM; end if; + when MODE_READ => if bcshdata_ff = '1' then state_d <= SM_READ; end if; + when MODE_WRITE => if bcshdata_ff = '1' then state_d <= SM_WRITE; end if; + when MODE_RUN => + if bo_go_ff = '1' then + if instruction_q(Raccumulate)='1' then + state_d <= SM_0; + count_d <= warmup_length; + else + state_d <= SM_CLEAR; + count_d <= max_sticky_length; + end if; + elsif bcshdata_ff = '1' then + state_d <= SM_DIAGROT; + end if; + when others => null; + end case; + end if; + when SM_IRLOAD => + if (bcshctrl_ff = '0') then + state_d <= SM_IDLE; + end if; + when SM_ENUM => + if (done_q = '1') then + state_d <= SM_IDLE; + end if; + when SM_READ => + if (bcshdata_ff = '0') then + state_d <= SM_IDLE; + end if; + when SM_WRITE => + if (bcshdata_ff = '0') then + state_d <= SM_IDLE; + end if; + when SM_DIAGROT => + if (bcshdata_ff = '0') then + state_d <= SM_IDLE; + end if; + when SM_CLEAR => + if (count_done = '1') then + state_d <= SM_0; + count_d <= warmup_length; + end if; + when SM_0 => + if (count_done = '1') then + state_d <= SM_1; + count_d <= warmup_length; + end if; + when SM_1 => + if (count_done = '1') then + state_d <= SM_2; + end if; + when SM_2 => + if (bcexe_ff = '1') then + state_d <= SM_RUNBST; + end if; + when SM_RUNBST => + if (abist_done = '1') then + state_d <= SM_3PRE; + end if; + if diagdecr_zero = '1' then + state_d <= SM_IDLE; + end if; + count_d <= fareg_length; + when SM_3PRE => + if (count_done = '1') then + state_d <= SM_3; + count_d <= max_sticky_length; + end if; + when SM_3 => + if (count_done = '1') then + if (diagdecr_q(Rdiagdecr_evs) = '0' or instruction_q(RFARR)='1' or bcsysrepair_ff='1') then + state_d <= SM_4; + else + state_d <= SM_IDLE; + end if; + count_d <= fareg_length; + end if; + when SM_4 => + if (count_done = '1') then + if instruction_q(Rloop) = '1' then + state_d <= SM_0; + else + state_d <= SM_IDLE; + end if; + end if; + when others => state_d <= SM_IDLE; + end case; + if bcreset_ff = '1' then + state_d <= SM_IDLE; + end if; + end process; + +input_reg: entity tri.tri_boltreg_p + generic map (width => scan_offset_1 - scan_offset_0, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => bo_enable, + thold_b => ck_bo_sl_thold_0_b, + sg => sg_int, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => int_scan_in(scan_offset_0 to scan_offset_1-1), + scout => int_scan_out(scan_offset_0 to scan_offset_1-1), + din(0) => bcdata, + din(1) => bcshcntl, + din(2) => bcshdata, + din(3) => bcexe, + din(4) => bcreset, + din(5) => bo_go, + din(6) => bcsysrepair, + dout(0) => bcdata_ff, + dout(1) => bcshctrl_ff, + dout(2) => bcshdata_ff, + dout(3) => bcexe_ff, + dout(4) => bcreset_ff, + dout(5) => bo_go_ff, + dout(6) => bcsysrepair_ff); + +daisy_reg: entity tri.tri_boltreg_p + generic map (width => scan_offset_2 - scan_offset_1, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => bo_enable, + thold_b => ck_bo_sl_thold_0_b, + sg => sg_int, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => int_scan_in(scan_offset_1 to scan_offset_2-1), + scout => int_scan_out(scan_offset_1 to scan_offset_2-1), + din(0) => done_d, + din(1) => wait_d, + din(2) => fail_d, + dout(0) => done_q, + dout(1) => wait_q, + dout(2) => fail_q ); + +doneout <= done_q; +waitout <= wait_q; +failout <= fail_q; + +state_reg: entity tri.tri_boltreg_p + generic map (width => scan_offset_3 - scan_offset_2, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => bo_enable, + thold_b => ck_bo_sl_thold_0_b, + sg => sg_int, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => int_scan_in(scan_offset_2 to scan_offset_3-1), + scout => int_scan_out(scan_offset_2 to scan_offset_3-1), + din(Tstate'range) => state_d, + din(Tstate'right + 1) => s_3pre, + din(Tstate'right + 2) => s_3, + din(Tstate'right + 3) => s_4, + dout(Tstate'range) => state_q, + dout(Tstate'right + 1) => s_3pre_delayed, + dout(Tstate'right + 2) => s_3_delayed, + dout(Tstate'right + 3) => s_4_delayed); + + s_idle <= state_q(SC_IDLE); + s_enum <= state_q(SC_ENUM); + s_write <= state_q(SC_WRITE); + s_read <= state_q(SC_READ); + s_irload <= state_q(SC_IRLOAD); + s_diagrot <= state_q(SC_DIAGROT); + s_0 <= state_q(SC_0); + s_1 <= state_q(SC_1); + s_2 <= state_q(SC_2); + s_3pre <= state_q(SC_3PRE); + s_3 <= state_q(SC_3); + s_4 <= state_q(SC_4); + s_runbst <= state_q(SC_RUNBST); + s_clear <= state_q(SC_CLEAR); + +enum_reg: entity tri.tri_boltreg_p + generic map (width => enum_d'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => bo_enable, + thold_b => ck_bo_sl_thold_0_b, + sg => sg_int, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => int_scan_in(scan_offset_3 to scan_offset_4-1), + scout => int_scan_out(scan_offset_3 to scan_offset_4-1), + din => enum_d, + dout => enum_q ); + +instr_reg: entity tri.tri_boltreg_p + generic map (width => instruction_d'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => shift_instruction, + thold_b => ck_bo_sl_thold_0_b, + sg => sg_int, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => int_scan_in(scan_offset_4 to scan_offset_5-1), + scout => int_scan_out(scan_offset_4 to scan_offset_5-1), + din => instruction_d, + dout => instruction_q ); + +mode <= instruction_q(Rmode); +kind <= instruction_q(Rkind); +addr <= instruction_q(Raddr); +w_reg_addr <= instruction_q(Rw_addr); +r_reg_addr <= instruction_q(Rr_addr); +reg_select <= '1' when addr = X"000" or (kind = '1' and addr = type_num) or (kind = '0' and addr = enum_q) else '0'; + +shuttle_reg: entity tri.tri_boltreg_p + generic map (width => shuttle_d'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => bo_enable, + thold_b => ck_bo_sl_thold_0_b, + sg => sg_int, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => int_scan_in(scan_offset_5 to scan_offset_6-1), + scout => int_scan_out(scan_offset_5 to scan_offset_6-1), + din => shuttle_d, + dout => shuttle_q ); + +count_reg: entity tri.tri_boltreg_p + generic map (width => count_d'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => bo_enable, + thold_b => ck_bo_sl_thold_0_b, + sg => sg_int, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => int_scan_in(scan_offset_6 to scan_offset_7-1), + scout => int_scan_out(scan_offset_6 to scan_offset_7-1), + din => count_d, + dout => count_q ); + +diagptr_reg: entity tri.tri_boltreg_p + generic map (width => diagptr_d'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => shift_diagptr, + thold_b => ck_bo_sl_thold_0_b, + sg => sg_int, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => int_scan_in(scan_offset_7 to scan_offset_8-1), + scout => int_scan_out(scan_offset_7 to scan_offset_8-1), + din => diagptr_d, + dout => diagptr_q ); + +bistmask_reg: entity tri.tri_boltreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => shift_bistmask, + thold_b => ck_bo_sl_thold_0_b, + sg => sg_int, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => int_scan_in(scan_offset_8 to scan_offset_9-1), + scout => int_scan_out(scan_offset_8 to scan_offset_9-1), + din(0) => bistmask_d, + dout(0) => bistmask_q ); + +memmask_reg: entity tri.tri_boltreg_p + generic map (width => memmask_d'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => shift_memmask, + thold_b => ck_bo_sl_thold_0_b, + sg => sg_int, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => int_scan_in(scan_offset_9 to scan_offset_10-1), + scout => int_scan_out(scan_offset_9 to scan_offset_10-1), + din => memmask_d, + dout => memmask_q ); + +bistdone_reg: entity tri.tri_boltreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => bo_enable, + thold_b => ck_bo_sl_thold_0_b, + sg => sg_int, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => int_scan_in(scan_offset_10 to scan_offset_11-1), + scout => int_scan_out(scan_offset_10 to scan_offset_11-1), + din(0) => bistdone_d, + dout(0) => bistdone_q ); + +diagdecr_reg: entity tri.tri_boltreg_p + generic map (width => diagdecr_d'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => bo_enable, + thold_b => ck_bo_sl_thold_0_b, + sg => sg_int, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => int_scan_in(scan_offset_11 to scan_offset_12-1), + scout => int_scan_out(scan_offset_11 to scan_offset_12-1), + din => diagdecr_d, + dout => diagdecr_q ); + +out_reg: entity tri.tri_boltreg_p + generic map (width => scan_offset_13 - scan_offset_12, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => bo_enable, + thold_b => ck_bo_sl_thold_0_b, + sg => sg_int, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => int_scan_in(scan_offset_12 to scan_offset_13-1), + scout => int_scan_out(scan_offset_12 to scan_offset_13-1), + din(0) => diagloop_out_d, + din(1) => write_abist_d, + dout(0) => diagloop_out, + dout(1) => write_abist_q ); + +fail_reg: entity tri.tri_boltreg_p + generic map (width => scan_offset_14 - scan_offset_13, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => bo_enable, + thold_b => ck_bo_sl_thold_0_b, + sg => sg_int, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => int_scan_in(scan_offset_13 to scan_offset_14-1), + scout => int_scan_out(scan_offset_13 to scan_offset_14-1), + din => bo_fail_pre, + dout => bo_fail_ff ); + + +int_scan_in(0) <= scan_in and not bo_enable; +int_scan_in(1 to int_scan_in'right) <= int_scan_out(0 to int_scan_out'right-1); +scan_out <= int_scan_out(int_scan_out'right); + +lcbor_func: entity tri.tri_lcbor +generic map (expand_type => expand_type ) +port map ( + clkoff_b => lcb_clkoff_dc_b, + thold => ck_bo_sl_thold_0, + sg => sg_int, + act_dis => lcb_act_dis_dc, + forcee => force_func, + thold_b => ck_bo_sl_thold_0_b ); + +end pcq_abist_bolton_frontend; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/pcq_abist_bolton_stg.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/pcq_abist_bolton_stg.vhdl new file mode 100644 index 0000000..fae93b6 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/pcq_abist_bolton_stg.vhdl @@ -0,0 +1,204 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee; +use ieee.std_logic_1164.all; +library ibm,clib; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +library support; +use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity pcq_abist_bolton_stg is +generic(expand_type : integer := 2); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + pc_pc_ccflush_dc : in std_ulogic; + + pu_pc_bo_enable : in std_ulogic; + pu_pc_bo_go : in std_ulogic; + pu_pc_bo_cntlclk : in std_ulogic; + pu_pc_bo_reset : in std_ulogic; + pu_pc_bo_fcshdata : in std_ulogic; + pu_pc_bo_fcreset : in std_ulogic; + + pc_bx_bo_enable_3 : out std_ulogic; + pc_fu_bo_enable_3 : out std_ulogic; + pc_iu_bo_enable_4 : out std_ulogic; + pc_mm_bo_enable_4 : out std_ulogic; + pc_xu_bo_enable_3 : out std_ulogic; + pc_pc_bo_go_0 : out std_ulogic; + pc_pc_bo_enable_0 : out std_ulogic; + pc_pc_bo_cntlclk_0 : out std_ulogic; + pc_pc_bo_reset_0 : out std_ulogic; + pc_pc_bo_fcshdata_0 : out std_ulogic; + pc_pc_bo_fcreset_0 : out std_ulogic); + +-- synopsys translate_off + + + +-- synopsys translate_on +end pcq_abist_bolton_stg; + +architecture pcq_abist_bolton_stg of pcq_abist_bolton_stg is + +signal pc_all_bolton_enable_5 : std_ulogic; +signal pc_all_bolton_enable_4 : std_ulogic; +signal pc_all_bolton_enable_3_int : std_ulogic; +signal pc_pc_bolton_enable_2 : std_ulogic; +signal pc_pc_bolton_enable_1 : std_ulogic; +signal pc_pc_bolton_go_1 : std_ulogic; +signal pc_pc_bc_cntlclk_1 : std_ulogic; +signal pc_pc_bc_reset_1 : std_ulogic; +signal pc_pc_bc_fcshdata_1 : std_ulogic; +signal pc_pc_bc_fcreset_1 : std_ulogic; + +begin + + bolton_enable_sync_meta : entity tri.tri_plat + generic map( + width => 6, + expand_type => expand_type) + port map( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_dc, + din(0) => pu_pc_bo_enable, + din(1) => pu_pc_bo_go, + din(2) => pu_pc_bo_cntlclk, + din(3) => pu_pc_bo_reset, + din(4) => pu_pc_bo_fcshdata, + din(5) => pu_pc_bo_fcreset, + q(0) => pc_all_bolton_enable_5, + q(1) => pc_pc_bolton_go_1, + q(2) => pc_pc_bc_cntlclk_1, + q(3) => pc_pc_bc_reset_1, + q(4) => pc_pc_bc_fcshdata_1, + q(5) => pc_pc_bc_fcreset_1); + + bolton_enable_sync : entity tri.tri_plat + generic map( + width => 6, + expand_type => expand_type) + port map( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_dc, + din(0) => pc_all_bolton_enable_5, + din(1) => pc_pc_bolton_go_1, + din(2) => pc_pc_bc_cntlclk_1, + din(3) => pc_pc_bc_reset_1, + din(4) => pc_pc_bc_fcshdata_1, + din(5) => pc_pc_bc_fcreset_1, + q(0) => pc_all_bolton_enable_4, + q(1) => pc_pc_bo_go_0, + q(2) => pc_pc_bo_cntlclk_0, + q(3) => pc_pc_bo_reset_0, + q(4) => pc_pc_bo_fcshdata_0, + q(5) => pc_pc_bo_fcreset_0); + + + bolton_enable_sync_2 : entity tri.tri_plat + generic map( + width => 4, + expand_type => expand_type) + port map( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_dc, + din(0) => pc_all_bolton_enable_4, + din(1) => pc_all_bolton_enable_3_int, + din(2) => pc_pc_bolton_enable_2, + din(3) => pc_pc_bolton_enable_1, + q(0) => pc_all_bolton_enable_3_int, + q(1) => pc_pc_bolton_enable_2, + q(2) => pc_pc_bolton_enable_1, + q(3) => pc_pc_bo_enable_0); + + + bx_bolton_enable_4_3 : entity tri.tri_plat + generic map( width => 1, expand_type => expand_type) + port map( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_dc, + din(0) => pc_all_bolton_enable_4, + q(0) => pc_bx_bo_enable_3 ); + + fu_bolton_enable_4_3 : entity tri.tri_plat + generic map( width => 1, expand_type => expand_type) + port map( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_dc, + din(0) => pc_all_bolton_enable_4, + q(0) => pc_fu_bo_enable_3 ); + + xu_bolton_enable_4_3 : entity tri.tri_plat + generic map( width => 1, expand_type => expand_type) + port map( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_dc, + din(0) => pc_all_bolton_enable_4, + q(0) => pc_xu_bo_enable_3 ); + + + iu_bolton_enable_5_4 : entity tri.tri_plat + generic map( width => 1, expand_type => expand_type) + port map( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_dc, + din(0) => pc_all_bolton_enable_5, + q(0) => pc_iu_bo_enable_4 ); + + mm_bolton_enable_5_4 : entity tri.tri_plat + generic map( width => 1, expand_type => expand_type) + port map( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_dc, + din(0) => pc_all_bolton_enable_5, + q(0) => pc_mm_bo_enable_4 ); + + +end architecture pcq_abist_bolton_stg; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/pcq_clks.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/pcq_clks.vhdl new file mode 100644 index 0000000..9196313 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/pcq_clks.vhdl @@ -0,0 +1,451 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee; +use ieee.std_logic_1164.all; +library support; +use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity pcq_clks is +generic(expand_type : integer := 2 +); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + rtim_sl_thold_6 : in std_ulogic; + func_sl_thold_6 : in std_ulogic; + func_nsl_thold_6 : in std_ulogic; + ary_nsl_thold_6 : in std_ulogic; + sg_6 : in std_ulogic; + fce_6 : in std_ulogic; + gsd_test_enable_dc : in std_ulogic; + gsd_test_acmode_dc : in std_ulogic; + ccflush_dc : in std_ulogic; + ccenable_dc : in std_ulogic; + scan_type_dc : in std_ulogic_vector(0 to 8); + lbist_en_dc : in std_ulogic; + lbist_ip_dc : in std_ulogic; + rg_ck_fast_xstop : in std_ulogic; + ct_ck_pm_ccflush_disable : in std_ulogic; + ct_ck_pm_raise_tholds : in std_ulogic; + bolton_enable_dc : in std_ulogic; + bolton_enable_sync : in std_ulogic; + bolton_ccflush : in std_ulogic; + bolton_fcshdata : in std_ulogic; + bolton_fcreset : in std_ulogic; + bc_cntlclk_sync : in std_ulogic; + bo_pc_abst_sl_thold_6 : in std_ulogic; + bo_pc_pc_abst_sl_thold_6 : in std_ulogic; + bo_pc_ary_nsl_thold_6 : in std_ulogic; + bo_pc_func_sl_thold_6 : in std_ulogic; + bo_pc_time_sl_thold_6 : in std_ulogic; + bo_pc_repr_sl_thold_6 : in std_ulogic; + bo_pc_sg_6 : in std_ulogic; + pc_xu_ccflush_dc : out std_ulogic; + pc_xu_gptr_sl_thold_3 : out std_ulogic; + pc_xu_time_sl_thold_3 : out std_ulogic; + pc_xu_repr_sl_thold_3 : out std_ulogic; + pc_xu_abst_sl_thold_3 : out std_ulogic; + pc_xu_abst_slp_sl_thold_3 : out std_ulogic; + pc_xu_bolt_sl_thold_3 : out std_ulogic; + pc_xu_regf_sl_thold_3 : out std_ulogic; + pc_xu_regf_slp_sl_thold_3 : out std_ulogic; + pc_xu_func_sl_thold_3 : out std_ulogic_vector(0 to 4); + pc_xu_func_slp_sl_thold_3 : out std_ulogic_vector(0 to 4); + pc_xu_cfg_sl_thold_3 : out std_ulogic; + pc_xu_cfg_slp_sl_thold_3 : out std_ulogic; + pc_xu_func_nsl_thold_3 : out std_ulogic; + pc_xu_func_slp_nsl_thold_3 : out std_ulogic; + pc_xu_ary_nsl_thold_3 : out std_ulogic; + pc_xu_ary_slp_nsl_thold_3 : out std_ulogic; + pc_xu_sg_3 : out std_ulogic_vector(0 to 4); + pc_xu_fce_3 : out std_ulogic_vector(0 to 1); + pc_bx_ccflush_dc : out std_ulogic; + pc_bx_func_sl_thold_3 : out std_ulogic; + pc_bx_func_slp_sl_thold_3 : out std_ulogic; + pc_bx_gptr_sl_thold_3 : out std_ulogic; + pc_bx_time_sl_thold_3 : out std_ulogic; + pc_bx_repr_sl_thold_3 : out std_ulogic; + pc_bx_abst_sl_thold_3 : out std_ulogic; + pc_bx_bolt_sl_thold_3 : out std_ulogic; + pc_bx_ary_nsl_thold_3 : out std_ulogic; + pc_bx_ary_slp_nsl_thold_3 : out std_ulogic; + pc_bx_sg_3 : out std_ulogic; + pc_mm_ccflush_dc : out std_ulogic; + pc_iu_ccflush_dc : out std_ulogic; + pc_iu_gptr_sl_thold_4 : out std_ulogic; + pc_iu_time_sl_thold_4 : out std_ulogic; + pc_iu_repr_sl_thold_4 : out std_ulogic; + pc_iu_abst_sl_thold_4 : out std_ulogic; + pc_iu_abst_slp_sl_thold_4 : out std_ulogic; + pc_iu_bolt_sl_thold_4 : out std_ulogic; + pc_iu_regf_slp_sl_thold_4 : out std_ulogic; + pc_iu_func_sl_thold_4 : out std_ulogic; + pc_iu_func_slp_sl_thold_4 : out std_ulogic; + pc_iu_cfg_sl_thold_4 : out std_ulogic; + pc_iu_cfg_slp_sl_thold_4 : out std_ulogic; + pc_iu_func_nsl_thold_4 : out std_ulogic; + pc_iu_func_slp_nsl_thold_4 : out std_ulogic; + pc_iu_ary_nsl_thold_4 : out std_ulogic; + pc_iu_ary_slp_nsl_thold_4 : out std_ulogic; + pc_iu_sg_4 : out std_ulogic; + pc_iu_fce_4 : out std_ulogic; + pc_fu_ccflush_dc : out std_ulogic; + pc_fu_gptr_sl_thold_3 : out std_ulogic; + pc_fu_time_sl_thold_3 : out std_ulogic; + pc_fu_repr_sl_thold_3 : out std_ulogic; + pc_fu_abst_sl_thold_3 : out std_ulogic; + pc_fu_abst_slp_sl_thold_3 : out std_ulogic; + pc_fu_bolt_sl_thold_3 : out std_ulogic; + pc_fu_func_sl_thold_3 : out std_ulogic_vector(0 to 1); + pc_fu_func_slp_sl_thold_3 : out std_ulogic_vector(0 to 1); + pc_fu_cfg_sl_thold_3 : out std_ulogic; + pc_fu_cfg_slp_sl_thold_3 : out std_ulogic; + pc_fu_func_nsl_thold_3 : out std_ulogic; + pc_fu_func_slp_nsl_thold_3 : out std_ulogic; + pc_fu_ary_nsl_thold_3 : out std_ulogic; + pc_fu_ary_slp_nsl_thold_3 : out std_ulogic; + pc_fu_sg_3 : out std_ulogic_vector(0 to 1); + pc_fu_fce_3 : out std_ulogic; + pc_pc_ccflush_dc : out std_ulogic; + pc_pc_gptr_sl_thold_0 : out std_ulogic; + pc_pc_abst_sl_thold_0 : out std_ulogic; + pc_pc_bolt_sl_thold_6 : out std_ulogic; + pc_pc_bolt_sl_thold_0 : out std_ulogic; + pc_pc_func_sl_thold_0 : out std_ulogic; + pc_pc_func_slp_sl_thold_0 : out std_ulogic; + pc_pc_cfg_sl_thold_0 : out std_ulogic; + pc_pc_cfg_slp_sl_thold_0 : out std_ulogic; + pc_pc_sg_0 : out std_ulogic; + dbg_clks_ctrls : out std_ulogic_vector(0 to 13) +); + + +-- synopsys translate_off + +-- synopsys translate_on +end pcq_clks; + +architecture pcq_clks of pcq_clks is +signal rtim_sl_thold_5 : std_ulogic; +signal func_sl_thold_5 : std_ulogic; +signal func_nsl_thold_5 : std_ulogic; +signal ary_nsl_thold_5 : std_ulogic; +signal sg_5 : std_ulogic; +signal fce_5 : std_ulogic; +signal pc_pc_ccflush_out_dc : std_ulogic; +signal pc_pc_gptr_sl_thold_4 : std_ulogic; +signal pc_pc_time_sl_thold_4 : std_ulogic; +signal pc_pc_repr_sl_thold_4 : std_ulogic; +signal pc_pc_abst_sl_thold_4 : std_ulogic; +signal pc_pc_abst_slp_sl_thold_4 : std_ulogic; +signal pc_pc_regf_sl_thold_4 : std_ulogic; +signal pc_pc_regf_slp_sl_thold_4 : std_ulogic; +signal pc_pc_func_sl_thold_4 : std_ulogic_vector(0 to 1); +signal pc_pc_func_slp_sl_thold_4 : std_ulogic_vector(0 to 1); +signal pc_pc_cfg_sl_thold_4 : std_ulogic; +signal pc_pc_cfg_slp_sl_thold_4 : std_ulogic; +signal pc_pc_func_nsl_thold_4 : std_ulogic; +signal pc_pc_func_slp_nsl_thold_4 : std_ulogic; +signal pc_pc_ary_nsl_thold_4 : std_ulogic; +signal pc_pc_ary_slp_nsl_thold_4 : std_ulogic; +signal pc_pc_rtim_sl_thold_4 : std_ulogic; +signal pc_pc_sg_4 : std_ulogic_vector(0 to 1); +signal pc_pc_fce_4 : std_ulogic_vector(0 to 1); +signal bo_pc_sg_5 : std_ulogic; +signal bo_pc_bolt_sl_thold_6 : std_ulogic; +signal bo_pc_abst_sl_thold_5 : std_ulogic; +signal bo_pc_pc_abst_sl_thold_5 : std_ulogic; +signal bo_pc_bolt_sl_thold_5 : std_ulogic; +signal bo_pc_ary_nsl_thold_5 : std_ulogic; +signal bo_pc_func_sl_thold_5 : std_ulogic; +signal bo_pc_time_sl_thold_5 : std_ulogic; +signal bo_pc_repr_sl_thold_5 : std_ulogic; +signal bo_pc_sg_4 : std_ulogic; +signal bo_pc_abst_sl_thold_4 : std_ulogic; +signal bo_pc_pc_abst_sl_thold_4 : std_ulogic; +signal bo_pc_bolt_sl_thold_4 : std_ulogic; +signal bo_pc_ary_nsl_thold_4 : std_ulogic; +signal bo_pc_func_sl_thold_4 : std_ulogic; +signal bo_pc_time_sl_thold_4 : std_ulogic; +signal bo_pc_repr_sl_thold_4 : std_ulogic; +signal bc_cntlclk_sync_2 : std_ulogic; +signal bc_cntlclk_sync_3 : std_ulogic; +signal ccflush_dc_int : std_ulogic; + + + +begin + +ccflush_dc_int <= ccflush_dc or (bolton_enable_dc and bolton_ccflush); + +clkctrl : entity work.pcq_clks_ctrl +generic map (expand_type => expand_type) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + rtim_sl_thold_5 => rtim_sl_thold_5, + func_sl_thold_5 => func_sl_thold_5, + func_nsl_thold_5 => func_nsl_thold_5, + ary_nsl_thold_5 => ary_nsl_thold_5, + sg_5 => sg_5, + fce_5 => fce_5, + gsd_test_enable_dc => gsd_test_enable_dc, + gsd_test_acmode_dc => gsd_test_acmode_dc, + ccflush_dc => ccflush_dc_int, + ccenable_dc => ccenable_dc, + scan_type_dc => scan_type_dc, + lbist_en_dc => lbist_en_dc, + lbist_ip_dc => lbist_ip_dc, + rg_ck_fast_xstop => rg_ck_fast_xstop, + ct_ck_pm_ccflush_disable => ct_ck_pm_ccflush_disable, + ct_ck_pm_raise_tholds => ct_ck_pm_raise_tholds, + pc_pc_ccflush_out_dc => pc_pc_ccflush_out_dc, + pc_pc_gptr_sl_thold_4 => pc_pc_gptr_sl_thold_4, + pc_pc_time_sl_thold_4 => pc_pc_time_sl_thold_4, + pc_pc_repr_sl_thold_4 => pc_pc_repr_sl_thold_4, + pc_pc_cfg_sl_thold_4 => pc_pc_cfg_sl_thold_4, + pc_pc_cfg_slp_sl_thold_4 => pc_pc_cfg_slp_sl_thold_4, + pc_pc_abst_sl_thold_4 => pc_pc_abst_sl_thold_4, + pc_pc_abst_slp_sl_thold_4 => pc_pc_abst_slp_sl_thold_4, + pc_pc_regf_sl_thold_4 => pc_pc_regf_sl_thold_4, + pc_pc_regf_slp_sl_thold_4 => pc_pc_regf_slp_sl_thold_4, + pc_pc_func_sl_thold_4 => pc_pc_func_sl_thold_4, + pc_pc_func_slp_sl_thold_4 => pc_pc_func_slp_sl_thold_4, + pc_pc_func_nsl_thold_4 => pc_pc_func_nsl_thold_4, + pc_pc_func_slp_nsl_thold_4 => pc_pc_func_slp_nsl_thold_4, + pc_pc_ary_nsl_thold_4 => pc_pc_ary_nsl_thold_4, + pc_pc_ary_slp_nsl_thold_4 => pc_pc_ary_slp_nsl_thold_4, + pc_pc_rtim_sl_thold_4 => pc_pc_rtim_sl_thold_4, + pc_pc_sg_4 => pc_pc_sg_4, + pc_pc_fce_4 => pc_pc_fce_4 +); + +clkstg : entity work.pcq_clks_stg +generic map (expand_type => expand_type) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_pc_ccflush_out_dc => pc_pc_ccflush_out_dc, + pc_pc_gptr_sl_thold_4 => pc_pc_gptr_sl_thold_4, + pc_pc_time_sl_thold_4 => pc_pc_time_sl_thold_4, + pc_pc_repr_sl_thold_4 => pc_pc_repr_sl_thold_4, + pc_pc_cfg_sl_thold_4 => pc_pc_cfg_sl_thold_4, + pc_pc_cfg_slp_sl_thold_4 => pc_pc_cfg_slp_sl_thold_4, + pc_pc_abst_sl_thold_4 => pc_pc_abst_sl_thold_4, + pc_pc_abst_slp_sl_thold_4 => pc_pc_abst_slp_sl_thold_4, + pc_pc_regf_sl_thold_4 => pc_pc_regf_sl_thold_4, + pc_pc_regf_slp_sl_thold_4 => pc_pc_regf_slp_sl_thold_4, + pc_pc_func_sl_thold_4 => pc_pc_func_sl_thold_4, + pc_pc_func_slp_sl_thold_4 => pc_pc_func_slp_sl_thold_4, + pc_pc_func_nsl_thold_4 => pc_pc_func_nsl_thold_4, + pc_pc_func_slp_nsl_thold_4 => pc_pc_func_slp_nsl_thold_4, + pc_pc_ary_nsl_thold_4 => pc_pc_ary_nsl_thold_4, + pc_pc_ary_slp_nsl_thold_4 => pc_pc_ary_slp_nsl_thold_4, + pc_pc_rtim_sl_thold_4 => pc_pc_rtim_sl_thold_4, + pc_pc_sg_4 => pc_pc_sg_4, + pc_pc_fce_4 => pc_pc_fce_4, + bolton_enable => bolton_enable_sync, + bolton_fcshdata => bolton_fcshdata, + bolton_fcreset => bolton_fcreset, + bo_pc_abst_sl_thold_4 => bo_pc_abst_sl_thold_4, + bo_pc_pc_abst_sl_thold_4 => bo_pc_pc_abst_sl_thold_4, + bo_pc_bolt_sl_thold_4 => bo_pc_bolt_sl_thold_4, + bo_pc_ary_nsl_thold_4 => bo_pc_ary_nsl_thold_4, + bo_pc_func_sl_thold_4 => bo_pc_func_sl_thold_4, + bo_pc_time_sl_thold_4 => bo_pc_time_sl_thold_4, + bo_pc_repr_sl_thold_4 => bo_pc_repr_sl_thold_4, + bo_pc_sg_4 => bo_pc_sg_4, + pc_xu_ccflush_dc => pc_xu_ccflush_dc, + pc_xu_gptr_sl_thold_3 => pc_xu_gptr_sl_thold_3, + pc_xu_time_sl_thold_3 => pc_xu_time_sl_thold_3, + pc_xu_repr_sl_thold_3 => pc_xu_repr_sl_thold_3, + pc_xu_abst_sl_thold_3 => pc_xu_abst_sl_thold_3, + pc_xu_abst_slp_sl_thold_3 => pc_xu_abst_slp_sl_thold_3, + pc_xu_bolt_sl_thold_3 => pc_xu_bolt_sl_thold_3, + pc_xu_regf_sl_thold_3 => pc_xu_regf_sl_thold_3, + pc_xu_regf_slp_sl_thold_3 => pc_xu_regf_slp_sl_thold_3, + pc_xu_func_sl_thold_3 => pc_xu_func_sl_thold_3, + pc_xu_func_slp_sl_thold_3 => pc_xu_func_slp_sl_thold_3, + pc_xu_cfg_sl_thold_3 => pc_xu_cfg_sl_thold_3, + pc_xu_cfg_slp_sl_thold_3 => pc_xu_cfg_slp_sl_thold_3, + pc_xu_func_nsl_thold_3 => pc_xu_func_nsl_thold_3, + pc_xu_func_slp_nsl_thold_3 => pc_xu_func_slp_nsl_thold_3, + pc_xu_ary_nsl_thold_3 => pc_xu_ary_nsl_thold_3, + pc_xu_ary_slp_nsl_thold_3 => pc_xu_ary_slp_nsl_thold_3, + pc_xu_sg_3 => pc_xu_sg_3, + pc_xu_fce_3 => pc_xu_fce_3, + pc_bx_ccflush_dc => pc_bx_ccflush_dc, + pc_bx_func_sl_thold_3 => pc_bx_func_sl_thold_3, + pc_bx_func_slp_sl_thold_3 => pc_bx_func_slp_sl_thold_3, + pc_bx_gptr_sl_thold_3 => pc_bx_gptr_sl_thold_3, + pc_bx_time_sl_thold_3 => pc_bx_time_sl_thold_3, + pc_bx_repr_sl_thold_3 => pc_bx_repr_sl_thold_3, + pc_bx_abst_sl_thold_3 => pc_bx_abst_sl_thold_3, + pc_bx_bolt_sl_thold_3 => pc_bx_bolt_sl_thold_3, + pc_bx_ary_nsl_thold_3 => pc_bx_ary_nsl_thold_3, + pc_bx_ary_slp_nsl_thold_3 => pc_bx_ary_slp_nsl_thold_3, + pc_bx_sg_3 => pc_bx_sg_3, + pc_mm_ccflush_dc => pc_mm_ccflush_dc, + pc_iu_ccflush_dc => pc_iu_ccflush_dc, + pc_iu_gptr_sl_thold_4 => pc_iu_gptr_sl_thold_4, + pc_iu_time_sl_thold_4 => pc_iu_time_sl_thold_4, + pc_iu_repr_sl_thold_4 => pc_iu_repr_sl_thold_4, + pc_iu_abst_sl_thold_4 => pc_iu_abst_sl_thold_4, + pc_iu_abst_slp_sl_thold_4 => pc_iu_abst_slp_sl_thold_4, + pc_iu_bolt_sl_thold_4 => pc_iu_bolt_sl_thold_4, + pc_iu_regf_slp_sl_thold_4 => pc_iu_regf_slp_sl_thold_4, + pc_iu_func_sl_thold_4 => pc_iu_func_sl_thold_4, + pc_iu_func_slp_sl_thold_4 => pc_iu_func_slp_sl_thold_4, + pc_iu_cfg_sl_thold_4 => pc_iu_cfg_sl_thold_4, + pc_iu_cfg_slp_sl_thold_4 => pc_iu_cfg_slp_sl_thold_4, + pc_iu_func_nsl_thold_4 => pc_iu_func_nsl_thold_4, + pc_iu_func_slp_nsl_thold_4 => pc_iu_func_slp_nsl_thold_4, + pc_iu_ary_nsl_thold_4 => pc_iu_ary_nsl_thold_4, + pc_iu_ary_slp_nsl_thold_4 => pc_iu_ary_slp_nsl_thold_4, + pc_iu_sg_4 => pc_iu_sg_4, + pc_iu_fce_4 => pc_iu_fce_4, + pc_fu_ccflush_dc => pc_fu_ccflush_dc, + pc_fu_gptr_sl_thold_3 => pc_fu_gptr_sl_thold_3, + pc_fu_time_sl_thold_3 => pc_fu_time_sl_thold_3, + pc_fu_repr_sl_thold_3 => pc_fu_repr_sl_thold_3, + pc_fu_abst_sl_thold_3 => pc_fu_abst_sl_thold_3, + pc_fu_abst_slp_sl_thold_3 => pc_fu_abst_slp_sl_thold_3, + pc_fu_bolt_sl_thold_3 => pc_fu_bolt_sl_thold_3, + pc_fu_func_sl_thold_3 => pc_fu_func_sl_thold_3, + pc_fu_func_slp_sl_thold_3 => pc_fu_func_slp_sl_thold_3, + pc_fu_cfg_sl_thold_3 => pc_fu_cfg_sl_thold_3, + pc_fu_cfg_slp_sl_thold_3 => pc_fu_cfg_slp_sl_thold_3, + pc_fu_func_nsl_thold_3 => pc_fu_func_nsl_thold_3, + pc_fu_func_slp_nsl_thold_3 => pc_fu_func_slp_nsl_thold_3, + pc_fu_ary_nsl_thold_3 => pc_fu_ary_nsl_thold_3, + pc_fu_ary_slp_nsl_thold_3 => pc_fu_ary_slp_nsl_thold_3, + pc_fu_sg_3 => pc_fu_sg_3, + pc_fu_fce_3 => pc_fu_fce_3, + pc_pc_ccflush_dc => pc_pc_ccflush_dc, + pc_pc_gptr_sl_thold_0 => pc_pc_gptr_sl_thold_0, + pc_pc_abst_sl_thold_0 => pc_pc_abst_sl_thold_0, + pc_pc_bolt_sl_thold_0 => pc_pc_bolt_sl_thold_0, + pc_pc_func_sl_thold_0 => pc_pc_func_sl_thold_0, + pc_pc_func_slp_sl_thold_0 => pc_pc_func_slp_sl_thold_0, + pc_pc_cfg_sl_thold_0 => pc_pc_cfg_sl_thold_0, + pc_pc_cfg_slp_sl_thold_0 => pc_pc_cfg_slp_sl_thold_0, + pc_pc_sg_0 => pc_pc_sg_0 +); + +bolton_thold_gen: tri_plat + generic map( width => 2, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => ccflush_dc_int, + din( 0) => bc_cntlclk_sync, + din( 1) => bc_cntlclk_sync_2, + q( 0) => bc_cntlclk_sync_2, + q( 1) => bc_cntlclk_sync_3 + ); + +bo_pc_bolt_sl_thold_6 <= not bolton_ccflush and not (bc_cntlclk_sync_2 and (bc_cntlclk_sync_2 xor bc_cntlclk_sync_3)) ; +pc_pc_bolt_sl_thold_6 <= bo_pc_bolt_sl_thold_6; + +lvl6to5_plat: tri_plat + generic map( width => 14, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => ccflush_dc_int, + din( 0) => rtim_sl_thold_6, + din( 1) => func_sl_thold_6, + din( 2) => func_nsl_thold_6, + din( 3) => ary_nsl_thold_6, + din( 4) => sg_6, + din( 5) => fce_6, + din( 6) => bo_pc_sg_6, + din( 7) => bo_pc_bolt_sl_thold_6, + din( 8) => bo_pc_abst_sl_thold_6, + din( 9) => bo_pc_pc_abst_sl_thold_6, + din(10) => bo_pc_ary_nsl_thold_6, + din(11) => bo_pc_func_sl_thold_6, + din(12) => bo_pc_time_sl_thold_6, + din(13) => bo_pc_repr_sl_thold_6, + q( 0) => rtim_sl_thold_5, + q( 1) => func_sl_thold_5, + q( 2) => func_nsl_thold_5, + q( 3) => ary_nsl_thold_5, + q( 4) => sg_5, + q( 5) => fce_5, + q( 6) => bo_pc_sg_5, + q( 7) => bo_pc_bolt_sl_thold_5, + q( 8) => bo_pc_abst_sl_thold_5, + q( 9) => bo_pc_pc_abst_sl_thold_5, + q(10) => bo_pc_ary_nsl_thold_5, + q(11) => bo_pc_func_sl_thold_5, + q(12) => bo_pc_time_sl_thold_5, + q(13) => bo_pc_repr_sl_thold_5 + ); + +lvl5to4_plat: tri_plat + generic map( width => 8, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => ccflush_dc_int, + din( 0) => bo_pc_sg_5, + din( 1) => bo_pc_bolt_sl_thold_5, + din( 2) => bo_pc_abst_sl_thold_5, + din( 3) => bo_pc_pc_abst_sl_thold_5, + din( 4) => bo_pc_ary_nsl_thold_5, + din( 5) => bo_pc_func_sl_thold_5, + din( 6) => bo_pc_time_sl_thold_5, + din( 7) => bo_pc_repr_sl_thold_5, + q( 0) => bo_pc_sg_4, + q( 1) => bo_pc_bolt_sl_thold_4, + q( 2) => bo_pc_abst_sl_thold_4, + q( 3) => bo_pc_pc_abst_sl_thold_4, + q( 4) => bo_pc_ary_nsl_thold_4, + q( 5) => bo_pc_func_sl_thold_4, + q( 6) => bo_pc_time_sl_thold_4, + q( 7) => bo_pc_repr_sl_thold_4 + ); + + + dbg_clks_ctrls <= ccenable_dc & + gsd_test_enable_dc & + gsd_test_acmode_dc & + lbist_en_dc & + lbist_ip_dc & + scan_type_dc(0 to 7) & + rg_ck_fast_xstop ; + +end pcq_clks; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/pcq_clks_ctrl.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/pcq_clks_ctrl.vhdl new file mode 100644 index 0000000..a466d0d --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/pcq_clks_ctrl.vhdl @@ -0,0 +1,274 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee; +use ieee.std_logic_1164.all; +library ibm; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +library support; +use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity pcq_clks_ctrl is +generic(expand_type : integer := 2 +); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + rtim_sl_thold_5 : in std_ulogic; + func_sl_thold_5 : in std_ulogic; + func_nsl_thold_5 : in std_ulogic; + ary_nsl_thold_5 : in std_ulogic; + sg_5 : in std_ulogic; + fce_5 : in std_ulogic; + gsd_test_enable_dc : in std_ulogic; + gsd_test_acmode_dc : in std_ulogic; + ccflush_dc : in std_ulogic; + ccenable_dc : in std_ulogic; + scan_type_dc : in std_ulogic_vector(0 to 8); + lbist_en_dc : in std_ulogic; + lbist_ip_dc : in std_ulogic; + rg_ck_fast_xstop : in std_ulogic; + ct_ck_pm_ccflush_disable : in std_ulogic; + ct_ck_pm_raise_tholds : in std_ulogic; + pc_pc_ccflush_out_dc : out std_ulogic; + pc_pc_gptr_sl_thold_4 : out std_ulogic; + pc_pc_time_sl_thold_4 : out std_ulogic; + pc_pc_repr_sl_thold_4 : out std_ulogic; + pc_pc_cfg_sl_thold_4 : out std_ulogic; + pc_pc_cfg_slp_sl_thold_4 : out std_ulogic; + pc_pc_abst_sl_thold_4 : out std_ulogic; + pc_pc_abst_slp_sl_thold_4 : out std_ulogic; + pc_pc_regf_sl_thold_4 : out std_ulogic; + pc_pc_regf_slp_sl_thold_4 : out std_ulogic; + pc_pc_func_sl_thold_4 : out std_ulogic_vector(0 to 1); + pc_pc_func_slp_sl_thold_4 : out std_ulogic_vector(0 to 1); + pc_pc_func_nsl_thold_4 : out std_ulogic; + pc_pc_func_slp_nsl_thold_4 : out std_ulogic; + pc_pc_ary_nsl_thold_4 : out std_ulogic; + pc_pc_ary_slp_nsl_thold_4 : out std_ulogic; + pc_pc_rtim_sl_thold_4 : out std_ulogic; + pc_pc_sg_4 : out std_ulogic_vector(0 to 1); + pc_pc_fce_4 : out std_ulogic_vector(0 to 1) +); +-- synopsys translate_off + +-- synopsys translate_on +end pcq_clks_ctrl; + +architecture pcq_clks_ctrl of pcq_clks_ctrl is +constant scantype_func : natural := 0; +constant scantype_mode : natural := 1; +constant scantype_ccfg : natural := 2; +constant scantype_gptr : natural := 2; +constant scantype_regf : natural := 3; +constant scantype_fuse : natural := 3; +constant scantype_lbst : natural := 4; +constant scantype_abst : natural := 5; +constant scantype_repr : natural := 6; +constant scantype_time : natural := 7; +constant scantype_bndy : natural := 8; +constant scantype_fary : natural := 9; + +signal scan_type_b : std_ulogic_vector(0 to 8); +signal fast_xstop_gated_staged : std_ulogic; +signal fce_in, sg_in : std_ulogic; +signal ary_nsl_thold, func_nsl_thold : std_ulogic; +signal rtim_sl_thold, func_sl_thold : std_ulogic; +signal gptr_sl_thold_in : std_ulogic; +signal time_sl_thold_in : std_ulogic; +signal repr_sl_thold_in : std_ulogic; +signal rtim_sl_thold_in : std_ulogic; +signal cfg_run_sl_thold_in : std_ulogic; +signal cfg_slp_sl_thold_in : std_ulogic; +signal abst_run_sl_thold_in : std_ulogic; +signal abst_slp_sl_thold_in : std_ulogic; +signal regf_run_sl_thold_in : std_ulogic; +signal regf_slp_sl_thold_in : std_ulogic; +signal func_run_sl_thold_in : std_ulogic; +signal func_slp_sl_thold_in : std_ulogic; +signal func_run_nsl_thold_in : std_ulogic; +signal func_slp_nsl_thold_in : std_ulogic; +signal ary_run_nsl_thold_in : std_ulogic; +signal ary_slp_nsl_thold_in : std_ulogic; +signal pm_ccflush_disable_dc : std_ulogic; +signal ccflush_out_dc_int : std_ulogic; +signal testdc : std_ulogic; +signal thold_overide_ctrl : std_ulogic; + +signal unused_signals : std_ulogic; + + + + +begin + + +unused_signals <= or_reduce(scan_type_b(2) & scan_type_b(4) & scan_type_b(6 to 8) & lbist_ip_dc); + +testdc <= gsd_test_enable_dc and not gsd_test_acmode_dc; + +sg_in <= sg_5 and ccenable_dc; +fce_in <= fce_5 and ccenable_dc; + +scan_type_b <= GATE_AND(sg_in, not scan_type_dc); + +thold_overide_ctrl <= fast_xstop_gated_staged and not sg_in and not lbist_en_dc and not gsd_test_enable_dc; + +rtim_sl_thold <= rtim_sl_thold_5; +func_sl_thold <= func_sl_thold_5 OR thold_overide_ctrl; +func_nsl_thold <= func_nsl_thold_5 OR thold_overide_ctrl; +ary_nsl_thold <= ary_nsl_thold_5 OR thold_overide_ctrl; + +pm_ccflush_disable_dc <= ct_ck_pm_ccflush_disable; + +ccflush_out_dc_int <= ccflush_dc AND (NOT pm_ccflush_disable_dc OR lbist_en_dc OR testdc); +pc_pc_ccflush_out_dc <= ccflush_out_dc_int; + + +gptr_sl_thold_in <= func_sl_thold or not scan_type_dc(scantype_gptr) or not ccenable_dc; + +time_sl_thold_in <= func_sl_thold or not scan_type_dc(scantype_time) or not ccenable_dc; + +repr_sl_thold_in <= func_sl_thold or not scan_type_dc(scantype_repr) or not ccenable_dc; + + +cfg_run_sl_thold_in <= func_sl_thold or scan_type_b(scantype_mode) or + (ct_ck_pm_raise_tholds and not sg_in and not lbist_en_dc and not gsd_test_enable_dc); + +cfg_slp_sl_thold_in <= func_sl_thold or scan_type_b(scantype_mode); + + +abst_run_sl_thold_in <= func_sl_thold or scan_type_b(scantype_abst) or + (ct_ck_pm_raise_tholds and not sg_in and not lbist_en_dc and not gsd_test_enable_dc); + +abst_slp_sl_thold_in <= func_sl_thold or scan_type_b(scantype_abst); + + +regf_run_sl_thold_in <= func_sl_thold or scan_type_b(scantype_regf) or + (ct_ck_pm_raise_tholds and not sg_in and not lbist_en_dc and not gsd_test_enable_dc); + +regf_slp_sl_thold_in <= func_sl_thold or scan_type_b(scantype_regf); + + +func_run_sl_thold_in <= func_sl_thold or scan_type_b(scantype_func) or + (ct_ck_pm_raise_tholds and not sg_in and not lbist_en_dc and not gsd_test_enable_dc); + +func_slp_sl_thold_in <= func_sl_thold or scan_type_b(scantype_func); + + +func_run_nsl_thold_in <= func_nsl_thold or + (ct_ck_pm_raise_tholds and not fce_in and not lbist_en_dc and not gsd_test_enable_dc); + +func_slp_nsl_thold_in <= func_nsl_thold; + + +ary_run_nsl_thold_in <= ary_nsl_thold or + (ct_ck_pm_raise_tholds and not fce_in and not lbist_en_dc and not gsd_test_enable_dc); + +ary_slp_nsl_thold_in <= ary_nsl_thold; + + +rtim_sl_thold_in <= rtim_sl_thold; + + +fast_stop_staging: tri_plat + generic map( width => 1, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => ccflush_out_dc_int, + din(0) => rg_ck_fast_xstop, + q(0) => fast_xstop_gated_staged + ); + +sg_fce_plat: tri_plat + generic map(width => 4, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => ccflush_out_dc_int, + din(0) => sg_in, + din(1) => sg_in, + din(2) => fce_in, + din(3) => fce_in, + q(0) => pc_pc_sg_4(0), + q(1) => pc_pc_sg_4(1), + q(2) => pc_pc_fce_4(0), + q(3) => pc_pc_fce_4(1) + ); + +thold_plat: tri_plat + generic map( width => 18, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => ccflush_out_dc_int, + din( 0) => gptr_sl_thold_in, + din( 1) => time_sl_thold_in, + din( 2) => repr_sl_thold_in, + din( 3) => cfg_run_sl_thold_in, + din( 4) => cfg_slp_sl_thold_in, + din( 5) => abst_run_sl_thold_in, + din( 6) => abst_slp_sl_thold_in, + din( 7) => regf_run_sl_thold_in, + din( 8) => regf_slp_sl_thold_in, + din( 9) => func_run_sl_thold_in, + din(10) => func_run_sl_thold_in, + din(11) => func_slp_sl_thold_in, + din(12) => func_slp_sl_thold_in, + din(13) => func_run_nsl_thold_in, + din(14) => func_slp_nsl_thold_in, + din(15) => ary_run_nsl_thold_in, + din(16) => ary_slp_nsl_thold_in, + din(17) => rtim_sl_thold_in, + q( 0) => pc_pc_gptr_sl_thold_4, + q( 1) => pc_pc_time_sl_thold_4, + q( 2) => pc_pc_repr_sl_thold_4, + q( 3) => pc_pc_cfg_sl_thold_4, + q( 4) => pc_pc_cfg_slp_sl_thold_4, + q( 5) => pc_pc_abst_sl_thold_4, + q( 6) => pc_pc_abst_slp_sl_thold_4, + q( 7) => pc_pc_regf_sl_thold_4, + q( 8) => pc_pc_regf_slp_sl_thold_4, + q( 9) => pc_pc_func_sl_thold_4(0), + q(10) => pc_pc_func_sl_thold_4(1), + q(11) => pc_pc_func_slp_sl_thold_4(0), + q(12) => pc_pc_func_slp_sl_thold_4(1), + q(13) => pc_pc_func_nsl_thold_4, + q(14) => pc_pc_func_slp_nsl_thold_4, + q(15) => pc_pc_ary_nsl_thold_4, + q(16) => pc_pc_ary_slp_nsl_thold_4, + q(17) => pc_pc_rtim_sl_thold_4 + ); + +end pcq_clks_ctrl; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/pcq_clks_stg.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/pcq_clks_stg.vhdl new file mode 100644 index 0000000..834cb27 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/pcq_clks_stg.vhdl @@ -0,0 +1,677 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee; +use ieee.std_logic_1164.all; +library support; +use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity pcq_clks_stg is +generic(expand_type : integer := 2 +); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + pc_pc_ccflush_out_dc : in std_ulogic; + pc_pc_gptr_sl_thold_4 : in std_ulogic; + pc_pc_time_sl_thold_4 : in std_ulogic; + pc_pc_repr_sl_thold_4 : in std_ulogic; + pc_pc_cfg_sl_thold_4 : in std_ulogic; + pc_pc_cfg_slp_sl_thold_4 : in std_ulogic; + pc_pc_abst_sl_thold_4 : in std_ulogic; + pc_pc_abst_slp_sl_thold_4 : in std_ulogic; + pc_pc_regf_sl_thold_4 : in std_ulogic; + pc_pc_regf_slp_sl_thold_4 : in std_ulogic; + pc_pc_func_sl_thold_4 : in std_ulogic_vector(0 to 1); + pc_pc_func_slp_sl_thold_4 : in std_ulogic_vector(0 to 1); + pc_pc_func_nsl_thold_4 : in std_ulogic; + pc_pc_func_slp_nsl_thold_4 : in std_ulogic; + pc_pc_ary_nsl_thold_4 : in std_ulogic; + pc_pc_ary_slp_nsl_thold_4 : in std_ulogic; + pc_pc_rtim_sl_thold_4 : in std_ulogic; + pc_pc_sg_4 : in std_ulogic_vector(0 to 1); + pc_pc_fce_4 : in std_ulogic_vector(0 to 1); + bolton_enable : in std_ulogic; + bolton_fcshdata : in std_ulogic; + bolton_fcreset : in std_ulogic; + bo_pc_abst_sl_thold_4 : in std_ulogic; + bo_pc_pc_abst_sl_thold_4 : in std_ulogic; + bo_pc_bolt_sl_thold_4 : in std_ulogic; + bo_pc_ary_nsl_thold_4 : in std_ulogic; + bo_pc_func_sl_thold_4 : in std_ulogic; + bo_pc_time_sl_thold_4 : in std_ulogic; + bo_pc_repr_sl_thold_4 : in std_ulogic; + bo_pc_sg_4 : in std_ulogic; + pc_xu_ccflush_dc : out std_ulogic; + pc_xu_gptr_sl_thold_3 : out std_ulogic; + pc_xu_time_sl_thold_3 : out std_ulogic; + pc_xu_repr_sl_thold_3 : out std_ulogic; + pc_xu_abst_sl_thold_3 : out std_ulogic; + pc_xu_abst_slp_sl_thold_3 : out std_ulogic; + pc_xu_bolt_sl_thold_3 : out std_ulogic; + pc_xu_regf_sl_thold_3 : out std_ulogic; + pc_xu_regf_slp_sl_thold_3 : out std_ulogic; + pc_xu_func_sl_thold_3 : out std_ulogic_vector(0 to 4); + pc_xu_func_slp_sl_thold_3 : out std_ulogic_vector(0 to 4); + pc_xu_cfg_sl_thold_3 : out std_ulogic; + pc_xu_cfg_slp_sl_thold_3 : out std_ulogic; + pc_xu_func_nsl_thold_3 : out std_ulogic; + pc_xu_func_slp_nsl_thold_3 : out std_ulogic; + pc_xu_ary_nsl_thold_3 : out std_ulogic; + pc_xu_ary_slp_nsl_thold_3 : out std_ulogic; + pc_xu_sg_3 : out std_ulogic_vector(0 to 4); + pc_xu_fce_3 : out std_ulogic_vector(0 to 1); + pc_bx_ccflush_dc : out std_ulogic; + pc_bx_func_sl_thold_3 : out std_ulogic; + pc_bx_func_slp_sl_thold_3 : out std_ulogic; + pc_bx_gptr_sl_thold_3 : out std_ulogic; + pc_bx_time_sl_thold_3 : out std_ulogic; + pc_bx_repr_sl_thold_3 : out std_ulogic; + pc_bx_abst_sl_thold_3 : out std_ulogic; + pc_bx_bolt_sl_thold_3 : out std_ulogic; + pc_bx_ary_nsl_thold_3 : out std_ulogic; + pc_bx_ary_slp_nsl_thold_3 : out std_ulogic; + pc_bx_sg_3 : out std_ulogic; + pc_mm_ccflush_dc : out std_ulogic; + pc_iu_ccflush_dc : out std_ulogic; + pc_iu_gptr_sl_thold_4 : out std_ulogic; + pc_iu_time_sl_thold_4 : out std_ulogic; + pc_iu_repr_sl_thold_4 : out std_ulogic; + pc_iu_abst_sl_thold_4 : out std_ulogic; + pc_iu_abst_slp_sl_thold_4 : out std_ulogic; + pc_iu_bolt_sl_thold_4 : out std_ulogic; + pc_iu_regf_slp_sl_thold_4 : out std_ulogic; + pc_iu_func_sl_thold_4 : out std_ulogic; + pc_iu_func_slp_sl_thold_4 : out std_ulogic; + pc_iu_cfg_sl_thold_4 : out std_ulogic; + pc_iu_cfg_slp_sl_thold_4 : out std_ulogic; + pc_iu_func_nsl_thold_4 : out std_ulogic; + pc_iu_func_slp_nsl_thold_4 : out std_ulogic; + pc_iu_ary_nsl_thold_4 : out std_ulogic; + pc_iu_ary_slp_nsl_thold_4 : out std_ulogic; + pc_iu_sg_4 : out std_ulogic; + pc_iu_fce_4 : out std_ulogic; + pc_fu_ccflush_dc : out std_ulogic; + pc_fu_gptr_sl_thold_3 : out std_ulogic; + pc_fu_time_sl_thold_3 : out std_ulogic; + pc_fu_repr_sl_thold_3 : out std_ulogic; + pc_fu_abst_sl_thold_3 : out std_ulogic; + pc_fu_abst_slp_sl_thold_3 : out std_ulogic; + pc_fu_bolt_sl_thold_3 : out std_ulogic; + pc_fu_func_sl_thold_3 : out std_ulogic_vector(0 to 1); + pc_fu_func_slp_sl_thold_3 : out std_ulogic_vector(0 to 1); + pc_fu_cfg_sl_thold_3 : out std_ulogic; + pc_fu_cfg_slp_sl_thold_3 : out std_ulogic; + pc_fu_func_nsl_thold_3 : out std_ulogic; + pc_fu_func_slp_nsl_thold_3 : out std_ulogic; + pc_fu_ary_nsl_thold_3 : out std_ulogic; + pc_fu_ary_slp_nsl_thold_3 : out std_ulogic; + pc_fu_sg_3 : out std_ulogic_vector(0 to 1); + pc_fu_fce_3 : out std_ulogic; + pc_pc_ccflush_dc : out std_ulogic; + pc_pc_gptr_sl_thold_0 : out std_ulogic; + pc_pc_abst_sl_thold_0 : out std_ulogic; + pc_pc_bolt_sl_thold_0 : out std_ulogic; + pc_pc_func_sl_thold_0 : out std_ulogic; + pc_pc_func_slp_sl_thold_0 : out std_ulogic; + pc_pc_cfg_sl_thold_0 : out std_ulogic; + pc_pc_cfg_slp_sl_thold_0 : out std_ulogic; + pc_pc_sg_0 : out std_ulogic +); + + +-- synopsys translate_off + +-- synopsys translate_on +end pcq_clks_stg; + +architecture pcq_clks_stg of pcq_clks_stg is +signal pc_pc_gptr_sl_thold_3 : std_ulogic; +signal pc_pc_abst_sl_thold_3 : std_ulogic; +signal pc_pc_bolt_sl_thold_3 : std_ulogic; +signal pc_pc_func_sl_thold_3 : std_ulogic; +signal pc_pc_func_slp_sl_thold_3 : std_ulogic; +signal pc_pc_cfg_slp_sl_thold_3 : std_ulogic; +signal pc_pc_cfg_sl_thold_3 : std_ulogic; +signal pc_pc_sg_3 : std_ulogic; +signal pc_pc_gptr_sl_thold_2 : std_ulogic; +signal pc_pc_abst_sl_thold_2 : std_ulogic; +signal pc_pc_bolt_sl_thold_2 : std_ulogic; +signal pc_pc_func_sl_thold_2 : std_ulogic; +signal pc_pc_func_slp_sl_thold_2 : std_ulogic; +signal pc_pc_cfg_slp_sl_thold_2 : std_ulogic; +signal pc_pc_cfg_sl_thold_2 : std_ulogic; +signal pc_pc_sg_2 : std_ulogic; +signal pc_pc_gptr_sl_thold_1 : std_ulogic; +signal pc_pc_abst_sl_thold_1 : std_ulogic; +signal pc_pc_bolt_sl_thold_1 : std_ulogic; +signal pc_pc_func_sl_thold_1 : std_ulogic; +signal pc_pc_func_slp_sl_thold_1 : std_ulogic; +signal pc_pc_cfg_slp_sl_thold_1 : std_ulogic; +signal pc_pc_cfg_sl_thold_1 : std_ulogic; +signal pc_pc_sg_1 : std_ulogic; +signal pc_pc_sg_4_int : std_ulogic_vector(0 to 1); +signal pc_pc_time_sl_thold_4_int : std_ulogic; +signal pc_pc_repr_sl_thold_4_int : std_ulogic; +signal bo_pc_abst_sl_thold_4_int : std_ulogic; +signal pc_pc_abst_sl_thold_4_int : std_ulogic; +signal pc_pc_abst_slp_sl_thold_4_int : std_ulogic; +signal pc_pc_regf_sl_thold_4_int : std_ulogic; +signal pc_pc_regf_slp_sl_thold_4_int : std_ulogic; +signal pc_pc_ary_nsl_thold_4_int : std_ulogic; +signal pc_pc_ary_slp_nsl_thold_4_int : std_ulogic; +signal pc_pc_func_sl_thold_4_int : std_ulogic_vector(0 to 1); +signal pc_pc_bolt_sl_thold_4_int : std_ulogic; +signal pc_pc_func_slp_sl_thold_4_int : std_ulogic_vector(0 to 1); +signal pc_pc_func_nsl_thold_4_int : std_ulogic; +signal pc_pc_func_slp_nsl_thold_4_int : std_ulogic; +signal unused_signals : std_ulogic; + + +begin + + unused_signals <= pc_pc_rtim_sl_thold_4; + + + pc_xu_ccflush_dc <= pc_pc_ccflush_out_dc; + pc_bx_ccflush_dc <= pc_pc_ccflush_out_dc; + pc_iu_ccflush_dc <= pc_pc_ccflush_out_dc; + pc_fu_ccflush_dc <= pc_pc_ccflush_out_dc; + pc_mm_ccflush_dc <= pc_pc_ccflush_out_dc; + pc_pc_ccflush_dc <= pc_pc_ccflush_out_dc; + + +pc_pc_sg_4_int(0) <= bo_pc_sg_4 or bolton_fcshdata when bolton_enable='1' else pc_pc_sg_4(0); +pc_pc_sg_4_int(1) <= bo_pc_sg_4 or bolton_fcshdata when bolton_enable='1' else pc_pc_sg_4(1); + +pc_pc_func_sl_thold_4_int(0) <= bo_pc_func_sl_thold_4 when bolton_enable='1' else pc_pc_func_sl_thold_4(0); +pc_pc_func_sl_thold_4_int(1) <= bo_pc_func_sl_thold_4 when bolton_enable='1' else pc_pc_func_sl_thold_4(1); +pc_pc_func_slp_sl_thold_4_int(0) <= bo_pc_func_sl_thold_4 when bolton_enable='1' else pc_pc_func_slp_sl_thold_4(0); +pc_pc_func_slp_sl_thold_4_int(1) <= bo_pc_func_sl_thold_4 when bolton_enable='1' else pc_pc_func_slp_sl_thold_4(1); + +pc_pc_func_nsl_thold_4_int <= bo_pc_func_sl_thold_4 when bolton_enable='1' else pc_pc_func_nsl_thold_4; +pc_pc_func_slp_nsl_thold_4_int <= bo_pc_func_sl_thold_4 when bolton_enable='1' else pc_pc_func_slp_nsl_thold_4; + +pc_pc_time_sl_thold_4_int <= bo_pc_time_sl_thold_4 when bolton_enable='1' else pc_pc_time_sl_thold_4; + +pc_pc_repr_sl_thold_4_int <= bo_pc_bolt_sl_thold_4 when (bolton_fcshdata or bolton_fcreset)='1' and bolton_enable='1' else + bo_pc_repr_sl_thold_4 when bolton_enable='1' else + pc_pc_repr_sl_thold_4; + +pc_pc_abst_sl_thold_4_int <= bo_pc_abst_sl_thold_4 when bolton_enable='1' else pc_pc_abst_sl_thold_4; +bo_pc_abst_sl_thold_4_int <= bo_pc_pc_abst_sl_thold_4 when bolton_enable='1' else pc_pc_abst_sl_thold_4; +pc_pc_abst_slp_sl_thold_4_int <= bo_pc_abst_sl_thold_4 when bolton_enable='1' else pc_pc_abst_slp_sl_thold_4; + +pc_pc_regf_sl_thold_4_int <= pc_pc_regf_sl_thold_4; +pc_pc_regf_slp_sl_thold_4_int <= pc_pc_regf_slp_sl_thold_4; + +pc_pc_ary_nsl_thold_4_int <= bo_pc_ary_nsl_thold_4 when bolton_enable='1' else pc_pc_ary_nsl_thold_4; +pc_pc_ary_slp_nsl_thold_4_int <= bo_pc_ary_nsl_thold_4 when bolton_enable='1' else pc_pc_ary_slp_nsl_thold_4; + +pc_pc_bolt_sl_thold_4_int <= bo_pc_bolt_sl_thold_4 when bolton_enable='1' else pc_pc_abst_sl_thold_4; + + +pc_iu_gptr_sl_thold_4 <= pc_pc_gptr_sl_thold_4; +pc_iu_time_sl_thold_4 <= pc_pc_time_sl_thold_4_int; +pc_iu_repr_sl_thold_4 <= pc_pc_repr_sl_thold_4_int; +pc_iu_abst_sl_thold_4 <= pc_pc_abst_sl_thold_4_int; +pc_iu_abst_slp_sl_thold_4 <= pc_pc_abst_slp_sl_thold_4_int; +pc_iu_bolt_sl_thold_4 <= pc_pc_bolt_sl_thold_4_int; +pc_iu_regf_slp_sl_thold_4 <= pc_pc_regf_slp_sl_thold_4_int; +pc_iu_func_sl_thold_4 <= pc_pc_func_sl_thold_4_int(1); +pc_iu_func_slp_sl_thold_4 <= pc_pc_func_slp_sl_thold_4_int(1); +pc_iu_cfg_sl_thold_4 <= pc_pc_cfg_sl_thold_4; +pc_iu_cfg_slp_sl_thold_4 <= pc_pc_cfg_slp_sl_thold_4; +pc_iu_func_nsl_thold_4 <= pc_pc_func_nsl_thold_4_int; +pc_iu_func_slp_nsl_thold_4 <= pc_pc_func_slp_nsl_thold_4_int; +pc_iu_ary_nsl_thold_4 <= pc_pc_ary_nsl_thold_4_int; +pc_iu_ary_slp_nsl_thold_4 <= pc_pc_ary_slp_nsl_thold_4_int; +pc_iu_sg_4 <= pc_pc_sg_4_int(1); +pc_iu_fce_4 <= pc_pc_fce_4(1); + + +xu_func_stg4to3: tri_plat + generic map( width => 14, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_out_dc, + din( 0) => pc_pc_func_sl_thold_4_int(0), + din( 1) => pc_pc_func_sl_thold_4_int(0), + din( 2) => pc_pc_func_sl_thold_4_int(0), + din( 3) => pc_pc_func_sl_thold_4_int(0), + din( 4) => pc_pc_func_sl_thold_4_int(0), + din( 5) => pc_pc_func_slp_sl_thold_4_int(0), + din( 6) => pc_pc_func_slp_sl_thold_4_int(0), + din( 7) => pc_pc_func_slp_sl_thold_4_int(0), + din( 8) => pc_pc_func_slp_sl_thold_4_int(0), + din( 9) => pc_pc_func_slp_sl_thold_4_int(0), + din(10) => pc_pc_cfg_sl_thold_4, + din(11) => pc_pc_cfg_slp_sl_thold_4, + din(12) => pc_pc_func_nsl_thold_4_int, + din(13) => pc_pc_func_slp_nsl_thold_4_int, + q( 0) => pc_xu_func_sl_thold_3(0), + q( 1) => pc_xu_func_sl_thold_3(1), + q( 2) => pc_xu_func_sl_thold_3(2), + q( 3) => pc_xu_func_sl_thold_3(3), + q( 4) => pc_xu_func_sl_thold_3(4), + q( 5) => pc_xu_func_slp_sl_thold_3(0), + q( 6) => pc_xu_func_slp_sl_thold_3(1), + q( 7) => pc_xu_func_slp_sl_thold_3(2), + q( 8) => pc_xu_func_slp_sl_thold_3(3), + q( 9) => pc_xu_func_slp_sl_thold_3(4), + q(10) => pc_xu_cfg_sl_thold_3, + q(11) => pc_xu_cfg_slp_sl_thold_3, + q(12) => pc_xu_func_nsl_thold_3, + q(13) => pc_xu_func_slp_nsl_thold_3 + ); + +xu_ctrl_stg4to3: tri_plat + generic map( width => 8, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_out_dc, + din( 0) => pc_pc_gptr_sl_thold_4, + din( 1) => pc_pc_sg_4_int(0), + din( 2) => pc_pc_sg_4_int(0), + din( 3) => pc_pc_sg_4_int(0), + din( 4) => pc_pc_sg_4_int(0), + din( 5) => pc_pc_sg_4_int(0), + din( 6) => pc_pc_fce_4(0), + din( 7) => pc_pc_fce_4(0), + q( 0) => pc_xu_gptr_sl_thold_3, + q( 1) => pc_xu_sg_3(0), + q( 2) => pc_xu_sg_3(1), + q( 3) => pc_xu_sg_3(2), + q( 4) => pc_xu_sg_3(3), + q( 5) => pc_xu_sg_3(4), + q( 6) => pc_xu_fce_3(0), + q( 7) => pc_xu_fce_3(1) + ); + +xu_arry_stg4to3: tri_plat + generic map( width => 9, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_out_dc, + din( 0) => pc_pc_time_sl_thold_4_int, + din( 1) => pc_pc_repr_sl_thold_4_int, + din( 2) => pc_pc_abst_sl_thold_4_int, + din( 3) => pc_pc_abst_slp_sl_thold_4_int, + din( 4) => pc_pc_bolt_sl_thold_4_int, + din( 5) => pc_pc_regf_sl_thold_4_int, + din( 6) => pc_pc_regf_slp_sl_thold_4_int, + din( 7) => pc_pc_ary_nsl_thold_4_int, + din( 8) => pc_pc_ary_slp_nsl_thold_4_int, + q( 0) => pc_xu_time_sl_thold_3, + q( 1) => pc_xu_repr_sl_thold_3, + q( 2) => pc_xu_abst_sl_thold_3, + q( 3) => pc_xu_abst_slp_sl_thold_3, + q( 4) => pc_xu_bolt_sl_thold_3, + q( 5) => pc_xu_regf_sl_thold_3, + q( 6) => pc_xu_regf_slp_sl_thold_3, + q( 7) => pc_xu_ary_nsl_thold_3, + q( 8) => pc_xu_ary_slp_nsl_thold_3 + ); + + +bx_ctrls_stg4to3: tri_plat + generic map( width => 10, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_out_dc, + din( 0) => pc_pc_func_sl_thold_4_int(0), + din( 1) => pc_pc_func_slp_sl_thold_4_int(0), + din( 2) => pc_pc_gptr_sl_thold_4, + din( 3) => pc_pc_time_sl_thold_4_int, + din( 4) => pc_pc_repr_sl_thold_4_int, + din( 5) => pc_pc_abst_sl_thold_4_int, + din( 6) => pc_pc_bolt_sl_thold_4_int, + din( 7) => pc_pc_ary_nsl_thold_4_int, + din( 8) => pc_pc_ary_slp_nsl_thold_4_int, + din( 9) => pc_pc_sg_4_int(0), + q( 0) => pc_bx_func_sl_thold_3, + q( 1) => pc_bx_func_slp_sl_thold_3, + q( 2) => pc_bx_gptr_sl_thold_3, + q( 3) => pc_bx_time_sl_thold_3, + q( 4) => pc_bx_repr_sl_thold_3, + q( 5) => pc_bx_abst_sl_thold_3, + q( 6) => pc_bx_bolt_sl_thold_3, + q( 7) => pc_bx_ary_nsl_thold_3, + q( 8) => pc_bx_ary_slp_nsl_thold_3, + q( 9) => pc_bx_sg_3 + ); + + +fu_func_stg4to3: tri_plat + generic map( width => 8, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_out_dc, + din( 0) => pc_pc_func_sl_thold_4_int(1), + din( 1) => pc_pc_func_sl_thold_4_int(1), + din( 2) => pc_pc_func_slp_sl_thold_4_int(1), + din( 3) => pc_pc_func_slp_sl_thold_4_int(1), + din( 4) => pc_pc_cfg_sl_thold_4, + din( 5) => pc_pc_cfg_slp_sl_thold_4, + din( 6) => pc_pc_func_nsl_thold_4_int, + din( 7) => pc_pc_func_slp_nsl_thold_4_int, + q( 0) => pc_fu_func_sl_thold_3(0), + q( 1) => pc_fu_func_sl_thold_3(1), + q( 2) => pc_fu_func_slp_sl_thold_3(0), + q( 3) => pc_fu_func_slp_sl_thold_3(1), + q( 4) => pc_fu_cfg_sl_thold_3, + q( 5) => pc_fu_cfg_slp_sl_thold_3, + q( 6) => pc_fu_func_nsl_thold_3, + q( 7) => pc_fu_func_slp_nsl_thold_3 + ); + +fu_ctrl_stg4to3: tri_plat + generic map( width => 4, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_out_dc, + din( 0) => pc_pc_gptr_sl_thold_4, + din( 1) => pc_pc_sg_4_int(1), + din( 2) => pc_pc_sg_4_int(1), + din( 3) => pc_pc_fce_4(1), + q( 0) => pc_fu_gptr_sl_thold_3, + q( 1) => pc_fu_sg_3(0), + q( 2) => pc_fu_sg_3(1), + q( 3) => pc_fu_fce_3 + ); + +fu_arry_stg4to3: tri_plat + generic map( width => 7, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_out_dc, + din( 0) => pc_pc_time_sl_thold_4_int, + din( 1) => pc_pc_repr_sl_thold_4_int, + din( 2) => pc_pc_abst_sl_thold_4_int, + din( 3) => pc_pc_abst_slp_sl_thold_4_int, + din( 4) => pc_pc_bolt_sl_thold_4_int, + din( 5) => pc_pc_ary_nsl_thold_4_int, + din( 6) => pc_pc_ary_slp_nsl_thold_4_int, + q( 0) => pc_fu_time_sl_thold_3, + q( 1) => pc_fu_repr_sl_thold_3, + q( 2) => pc_fu_abst_sl_thold_3, + q( 3) => pc_fu_abst_slp_sl_thold_3, + q( 4) => pc_fu_bolt_sl_thold_3, + q( 5) => pc_fu_ary_nsl_thold_3, + q( 6) => pc_fu_ary_slp_nsl_thold_3 + ); + + +pc_func_stg4to3: tri_plat + generic map( width => 4, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_out_dc, + din( 0) => pc_pc_func_sl_thold_4_int(1), + din( 1) => pc_pc_func_slp_sl_thold_4_int(1), + din( 2) => pc_pc_cfg_sl_thold_4, + din( 3) => pc_pc_cfg_slp_sl_thold_4, + q( 0) => pc_pc_func_sl_thold_3, + q( 1) => pc_pc_func_slp_sl_thold_3, + q( 2) => pc_pc_cfg_sl_thold_3, + q( 3) => pc_pc_cfg_slp_sl_thold_3 + ); + +pc_ctrl_stg4to3: tri_plat + generic map( width => 4, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_out_dc, + din( 0) => pc_pc_gptr_sl_thold_4, + din( 1) => bo_pc_abst_sl_thold_4_int, + din( 2) => pc_pc_bolt_sl_thold_4_int, + din( 3) => pc_pc_sg_4_int(1), + q( 0) => pc_pc_gptr_sl_thold_3, + q( 1) => pc_pc_abst_sl_thold_3, + q( 2) => pc_pc_bolt_sl_thold_3, + q( 3) => pc_pc_sg_3 + ); + + +func_3_2: tri_plat + generic map( width => 1, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_out_dc, + din(0) => pc_pc_func_sl_thold_3, + q(0) => pc_pc_func_sl_thold_2 + ); +func_2_1: tri_plat + generic map( width => 1, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_out_dc, + din(0) => pc_pc_func_sl_thold_2, + q(0) => pc_pc_func_sl_thold_1 + ); +func_1_0: tri_plat + generic map( width => 1, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_out_dc, + din(0) => pc_pc_func_sl_thold_1, + q(0) => pc_pc_func_sl_thold_0 + ); + +func_slp_3_2: tri_plat + generic map( width => 1, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_out_dc, + din(0) => pc_pc_func_slp_sl_thold_3, + q(0) => pc_pc_func_slp_sl_thold_2 + ); +func_slp_2_1: tri_plat + generic map( width => 1, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_out_dc, + din(0) => pc_pc_func_slp_sl_thold_2, + q(0) => pc_pc_func_slp_sl_thold_1 + ); +func_slp_1_0: tri_plat + generic map( width => 1, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_out_dc, + din(0) => pc_pc_func_slp_sl_thold_1, + q(0) => pc_pc_func_slp_sl_thold_0 + ); + +cfg_3_2: tri_plat + generic map( width => 1, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_out_dc, + din(0) => pc_pc_cfg_sl_thold_3, + q(0) => pc_pc_cfg_sl_thold_2 + ); +cfg_2_1: tri_plat + generic map( width => 1, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_out_dc, + din(0) => pc_pc_cfg_sl_thold_2, + q(0) => pc_pc_cfg_sl_thold_1 + ); +cfg_1_0: tri_plat + generic map( width => 1, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_out_dc, + din(0) => pc_pc_cfg_sl_thold_1, + q(0) => pc_pc_cfg_sl_thold_0 + ); + +cfg_slp_3_2: tri_plat + generic map( width => 1, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_out_dc, + din(0) => pc_pc_cfg_slp_sl_thold_3, + q(0) => pc_pc_cfg_slp_sl_thold_2 + ); +cfg_slp_2_1: tri_plat + generic map( width => 1, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_out_dc, + din(0) => pc_pc_cfg_slp_sl_thold_2, + q(0) => pc_pc_cfg_slp_sl_thold_1 + ); +cfg_slp_1_0: tri_plat + generic map( width => 1, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_out_dc, + din(0) => pc_pc_cfg_slp_sl_thold_1, + q(0) => pc_pc_cfg_slp_sl_thold_0 + ); + +abst_3_2: tri_plat + generic map( width => 2, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_out_dc, + din(0) => pc_pc_abst_sl_thold_3, + din(1) => pc_pc_bolt_sl_thold_3, + q(0) => pc_pc_abst_sl_thold_2, + q(1) => pc_pc_bolt_sl_thold_2 + ); +abst_2_1: tri_plat + generic map( width => 2, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_out_dc, + din(0) => pc_pc_abst_sl_thold_2, + din(1) => pc_pc_bolt_sl_thold_2, + q(0) => pc_pc_abst_sl_thold_1, + q(1) => pc_pc_bolt_sl_thold_1 + ); +abst_1_0: tri_plat + generic map( width => 2, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_out_dc, + din(0) => pc_pc_abst_sl_thold_1, + din(1) => pc_pc_bolt_sl_thold_1, + q(0) => pc_pc_abst_sl_thold_0, + q(1) => pc_pc_bolt_sl_thold_0 + ); + +gptr_3_2: tri_plat + generic map( width => 1, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_out_dc, + din(0) => pc_pc_gptr_sl_thold_3, + q(0) => pc_pc_gptr_sl_thold_2 + ); +gptr_2_1: tri_plat + generic map( width => 1, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_out_dc, + din(0) => pc_pc_gptr_sl_thold_2, + q(0) => pc_pc_gptr_sl_thold_1 + ); +gptr_1_0: tri_plat + generic map( width => 1, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_out_dc, + din(0) => pc_pc_gptr_sl_thold_1, + q(0) => pc_pc_gptr_sl_thold_0 + ); + +sg_3_2: tri_plat + generic map( width => 1, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_out_dc, + din(0) => pc_pc_sg_3, + q(0) => pc_pc_sg_2 + ); +sg_2_1: tri_plat + generic map( width => 1, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_out_dc, + din(0) => pc_pc_sg_2, + q(0) => pc_pc_sg_1 + ); +sg_1_0: tri_plat + generic map( width => 1, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_out_dc, + din(0) => pc_pc_sg_1, + q(0) => pc_pc_sg_0 + ); + + +end pcq_clks_stg; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/pcq_ctrl.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/pcq_ctrl.vhdl new file mode 100644 index 0000000..375044d --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/pcq_ctrl.vhdl @@ -0,0 +1,378 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee; +use ieee.std_logic_1164.all; +library ibm; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; +library support; +use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity pcq_ctrl is +generic(expand_type : integer := 2 +); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + scan_dis_dc_b : in std_ulogic; + lcb_clkoff_dc_b : in std_ulogic; + lcb_mpw1_dc_b : in std_ulogic; + lcb_mpw2_dc_b : in std_ulogic; + lcb_delay_lclkr_dc : in std_ulogic; + lcb_act_dis_dc : in std_ulogic; + pc_pc_func_slp_sl_thold_0 : in std_ulogic; + pc_pc_sg_0 : in std_ulogic; + func_scan_in : in std_ulogic; + func_scan_out : out std_ulogic; + an_ac_reset_1_complete : in std_ulogic; + an_ac_reset_2_complete : in std_ulogic; + an_ac_reset_3_complete : in std_ulogic; + an_ac_reset_wd_complete : in std_ulogic; + pc_xu_reset_1_cmplt : out std_ulogic; + pc_xu_reset_2_cmplt : out std_ulogic; + pc_xu_reset_3_cmplt : out std_ulogic; + pc_xu_reset_wd_cmplt : out std_ulogic; + pc_xu_init_reset : out std_ulogic; + pc_iu_init_reset : out std_ulogic; + ct_rg_hold_during_init : out std_ulogic; + ct_rg_power_managed : out std_ulogic_vector(0 to 3); + ct_rg_pm_thread_stop : out std_ulogic_vector(0 to 3); + an_ac_pm_thread_stop : in std_ulogic_vector(0 to 3); + ac_an_power_managed : out std_ulogic; + ac_an_rvwinkle_mode : out std_ulogic; + ct_ck_pm_ccflush_disable : out std_ulogic; + ct_ck_pm_raise_tholds : out std_ulogic; + rg_ct_dis_pwr_savings : in std_ulogic; + xu_pc_spr_ccr0_pme : in std_ulogic_vector(0 to 1); + xu_pc_spr_ccr0_we : in std_ulogic_vector(0 to 3); + dbg_ctrls : out std_ulogic_vector(0 to 36) +); +-- synopsys translate_off + + +-- synopsys translate_on +end pcq_ctrl; + +architecture pcq_ctrl of pcq_ctrl is +constant initactive_size : positive := 1; +constant resetsm_size : positive := 5; +constant initerat_size : positive := 1; +constant pmstate_size : positive := 14; +constant sprccr0_size : positive := 6; +constant pmstop_size : positive := 4; +constant resetstat_size : positive := 4; +constant sparectrl_size : positive := 6; + +constant initactive_offset : natural := 0; +constant resetsm_offset : natural := initactive_offset + initactive_size; +constant initerat_offset : natural := resetsm_offset + resetsm_size; +constant pmstate_offset : natural := initerat_offset + initerat_size; +constant sprccr0_offset : natural := pmstate_offset + pmstate_size; +constant pmstop_offset : natural := sprccr0_offset + sprccr0_size; +constant resetstat_offset : natural := pmstop_offset + pmstop_size; +constant sparectrl_offset : natural := resetstat_offset + resetstat_size; +constant func_right : natural := sparectrl_offset + sparectrl_size - 1; + +constant ResSM_Idle : std_ulogic_vector(0 to 4) := "00000"; +constant ResSM_Start : std_ulogic_vector(0 to 4) := "00001"; +constant ResSM_InitErat : std_ulogic_vector(0 to 4) := "00111"; +constant ResSM_Return : std_ulogic_vector(0 to 4) := "10111"; + +signal tiup : std_ulogic; +signal func_siv, func_sov : std_ulogic_vector(0 to func_right); +signal pc_pc_func_slp_sl_thold_0_b : std_ulogic; +signal force_funcslp : std_ulogic; +signal resetsm_active : std_ulogic; +signal resetsm_act_ctrl : std_ulogic; +signal spr_ccr0_pme_q : std_ulogic_vector(0 to 1); +signal spr_ccr0_we_q : std_ulogic_vector(0 to 3); +signal pm_sleep_enable : std_ulogic; +signal pm_rvw_enable : std_ulogic; +signal thread_stopped : std_ulogic_vector(0 to 3); +signal resetsm_d, resetsm_q : std_ulogic_vector(0 to resetsm_size-1); +signal init_active_d, init_active_q : std_ulogic; +signal initerat_d, initerat_q : std_ulogic; +signal pmstate_d, pmstate_q : std_ulogic_vector(0 to 3); +signal pmstate_all_d, pmstate_all_q : std_ulogic; +signal pmclkctrl_dly_d, pmclkctrl_dly_q : std_ulogic_vector(0 to 7); +signal rvwinkled_d, rvwinkled_q : std_ulogic; +signal pmstop_q : std_ulogic_vector(0 to pmstop_size-1); +signal reset_complete_q : std_ulogic_vector(0 to resetstat_size-1); +signal pm_ccflush_disable_int : std_ulogic; +signal pm_raise_tholds_int : std_ulogic; +signal spare_ctrl_wrapped_q : std_ulogic_vector(0 to sparectrl_size-1); + + +begin + + +tiup <= '1'; + + + resetsm_d <= (others=>'0') when (resetsm_q=ResSM_Idle and init_active_q='0') else + ResSM_Start when (resetsm_q=ResSM_Idle and init_active_q='1') else + ResSM_Idle when init_active_q='0' else + resetsm_q + "00001"; + + resetsm_active <= or_reduce(resetsm_q); + resetsm_act_ctrl <= init_active_q or resetsm_active; + + initerat_d <= '0' when resetsm_q=ResSM_Idle else + '0' when resetsm_q=ResSM_Return else + '1' when resetsm_q=ResSM_InitErat else + initerat_q; + + init_active_d <= '0' when resetsm_q(0 to 1)="11" else init_active_q; + + + pm_sleep_enable <= not spr_ccr0_pme_q(0) and spr_ccr0_pme_q(1); + + pm_rvw_enable <= spr_ccr0_pme_q(0) and not spr_ccr0_pme_q(1); + + thread_stopped <= spr_ccr0_we_q; + + + + pmstate_d <= gate_and((pm_sleep_enable or pm_rvw_enable) and not resetsm_active, + thread_stopped(0 to 3)); + + pmstate_all_d <= and_reduce(pmstate_q); + + pmclkctrl_dly_d(0 to 7) <= pmstate_all_q & pmclkctrl_dly_q(0 to 6); + + rvwinkled_d <= pmclkctrl_dly_q(6) and pm_rvw_enable; + + + ct_rg_hold_during_init <= init_active_q; + + pc_iu_init_reset <= initerat_q; + pc_xu_init_reset <= initerat_q; + + pc_xu_reset_1_cmplt <= reset_complete_q(0); + pc_xu_reset_2_cmplt <= reset_complete_q(1); + pc_xu_reset_3_cmplt <= reset_complete_q(2); + pc_xu_reset_wd_cmplt <= reset_complete_q(3); + + ct_rg_pm_thread_stop <= pmstop_q; + + ct_rg_power_managed <= pmstate_q; + + ac_an_rvwinkle_mode <= rvwinkled_q; + ac_an_power_managed <= pmclkctrl_dly_q(7); + + pm_ccflush_disable_int <= pmstate_all_q or pmclkctrl_dly_q(7); + ct_ck_pm_ccflush_disable <= pm_ccflush_disable_int and not rg_ct_dis_pwr_savings; + pm_raise_tholds_int <= pmstate_all_q and pmclkctrl_dly_q(7); + ct_ck_pm_raise_tholds <= pm_raise_tholds_int and not rg_ct_dis_pwr_savings; + + + dbg_ctrls <= init_active_q & + resetsm_q(0 to 4) & + initerat_q & + reset_complete_q(0 to 3) & + pmstop_q(0 to 3) & + pmstate_q(0 to 3) & + rvwinkled_q & + spr_ccr0_pme_q(0 to 1) & + spr_ccr0_we_q(0 to 3) & + pmclkctrl_dly_q(0 to 7) & + rg_ct_dis_pwr_savings & + pm_ccflush_disable_int & + pm_raise_tholds_int ; + + +initactive: tri_rlmlatch_p + generic map (init => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_pc_func_slp_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_funcslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(initactive_offset), + scout => func_sov(initactive_offset), + din => init_active_d, + dout => init_active_q); + +resetsm: tri_rlmreg_p + generic map (width => resetsm_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => resetsm_act_ctrl, + thold_b => pc_pc_func_slp_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_funcslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(resetsm_offset to resetsm_offset + resetsm_size-1), + scout => func_sov(resetsm_offset to resetsm_offset + resetsm_size-1), + din => resetsm_d, + dout => resetsm_q ); + +initerat: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => resetsm_active, + thold_b => pc_pc_func_slp_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_funcslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(initerat_offset), + scout => func_sov(initerat_offset), + din => initerat_d, + dout => initerat_q ); + +pmstate: tri_rlmreg_p + generic map (width => pmstate_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_pc_func_slp_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_funcslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(pmstate_offset to pmstate_offset + pmstate_size-1), + scout => func_sov(pmstate_offset to pmstate_offset + pmstate_size-1), + din(0 to 3) => pmstate_d, + din(4) => pmstate_all_d, + din(5) => rvwinkled_d, + din(6 to 13) => pmclkctrl_dly_d, + dout(0 to 3) => pmstate_q, + dout(4) => pmstate_all_q, + dout(5) => rvwinkled_q, + dout(6 to 13) => pmclkctrl_dly_q ); + +sprccr0: tri_rlmreg_p + generic map (width => sprccr0_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_pc_func_slp_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_funcslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(sprccr0_offset to sprccr0_offset + sprccr0_size-1), + scout => func_sov(sprccr0_offset to sprccr0_offset + sprccr0_size-1), + din(0 to 1) => xu_pc_spr_ccr0_pme, + din(2 to 5) => xu_pc_spr_ccr0_we, + dout(0 to 1) => spr_ccr0_pme_q, + dout(2 to 5) => spr_ccr0_we_q ); + +pmstop: tri_rlmreg_p + generic map (width => pmstop_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_pc_func_slp_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_funcslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(pmstop_offset to pmstop_offset + pmstop_size-1), + scout => func_sov(pmstop_offset to pmstop_offset + pmstop_size-1), + din => an_ac_pm_thread_stop, + dout => pmstop_q ); + +resetstat: tri_rlmreg_p + generic map (width => resetstat_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_pc_func_slp_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_funcslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(resetstat_offset to resetstat_offset + resetstat_size-1), + scout => func_sov(resetstat_offset to resetstat_offset + resetstat_size-1), + din(0) => an_ac_reset_1_complete, + din(1) => an_ac_reset_2_complete, + din(2) => an_ac_reset_3_complete, + din(3) => an_ac_reset_wd_complete, + dout => reset_complete_q ); + +sparectrl: tri_rlmreg_p + generic map (width => sparectrl_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_pc_func_slp_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_funcslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(sparectrl_offset to sparectrl_offset + sparectrl_size-1), + scout => func_sov(sparectrl_offset to sparectrl_offset + sparectrl_size-1), + din => spare_ctrl_wrapped_q, + dout => spare_ctrl_wrapped_q ); + + +lcbor_funcslp: tri_lcbor +generic map (expand_type => expand_type ) +port map ( + clkoff_b => lcb_clkoff_dc_b, + thold => pc_pc_func_slp_sl_thold_0, + sg => pc_pc_sg_0, + act_dis => lcb_act_dis_dc, + forcee => force_funcslp, + thold_b => pc_pc_func_slp_sl_thold_0_b ); + + +func_siv(0 TO func_right) <= func_scan_in & func_sov(0 to func_right-1); +func_scan_out <= func_sov(func_right) and scan_dis_dc_b; + + +end pcq_ctrl; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/pcq_dbg.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/pcq_dbg.vhdl new file mode 100644 index 0000000..375d529 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/pcq_dbg.vhdl @@ -0,0 +1,803 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee; +use ieee.std_logic_1164.all; +library ibm,clib; +use ibm.std_ulogic_function_support.all; +library support; +use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity pcq_dbg is +generic(expand_type : integer := 2 +); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + scan_dis_dc_b : in std_ulogic; + lcb_clkoff_dc_b : in std_ulogic; + lcb_mpw1_dc_b : in std_ulogic; + lcb_mpw2_dc_b : in std_ulogic; + lcb_delay_lclkr_dc : in std_ulogic; + lcb_act_dis_dc : in std_ulogic; + pc_pc_func_slp_sl_thold_0 : in std_ulogic; + pc_pc_sg_0 : in std_ulogic; + func_scan_in : in std_ulogic; + func_scan_out : out std_ulogic; + debug_bus_out : out std_ulogic_vector(0 to 87); + trace_triggers_out : out std_ulogic_vector(0 to 11); + debug_bus_in : in std_ulogic_vector(0 to 87); + trace_triggers_in : in std_ulogic_vector(0 to 11); + rg_db_trace_bus_enable : in std_ulogic; + rg_db_debug_mux_ctrls : in std_ulogic_vector(0 to 15); + ck_db_dbg_clks_ctrls : in std_ulogic_vector(0 to 13); + rg_db_dbg_scom_rdata : in std_ulogic_vector(0 to 63); + rg_db_dbg_scom_wdata : in std_ulogic_vector(0 to 63); + rg_db_dbg_scom_decaddr : in std_ulogic_vector(0 to 63); + rg_db_dbg_scom_misc : in std_ulogic_vector(0 to 8); + rg_db_dbg_ram_thrctl : in std_ulogic_vector(0 to 20); + rg_db_dbg_fir0_err : in std_ulogic_vector(0 to 31); + rg_db_dbg_fir1_err : in std_ulogic_vector(0 to 30); + rg_db_dbg_fir2_err : in std_ulogic_vector(0 to 21); + rg_db_dbg_fir_misc : in std_ulogic_vector(0 to 35); + ct_db_dbg_ctrls : in std_ulogic_vector(0 to 36); + rg_db_dbg_spr : in std_ulogic_vector(0 to 46); + ac_an_event_bus : out std_ulogic_vector(0 to 7); + ac_an_fu_bypass_events : out std_ulogic_vector(0 to 7); + ac_an_iu_bypass_events : out std_ulogic_vector(0 to 7); + ac_an_mm_bypass_events : out std_ulogic_vector(0 to 7); + ac_an_lsu_bypass_events : out std_ulogic_vector(0 to 7); + rg_db_event_bus_enable : in std_ulogic; + rg_db_event_mux_ctrls : in std_ulogic_vector(0 to 23); + fu_pc_event_data : in std_ulogic_vector(0 to 7); + iu_pc_event_data : in std_ulogic_vector(0 to 7); + mm_pc_event_data : in std_ulogic_vector(0 to 7); + xu_pc_event_data : in std_ulogic_vector(0 to 7); + lsu_pc_event_data : in std_ulogic_vector(0 to 7); + ac_pc_trace_to_perfcntr : in std_ulogic_vector(0 to 7) +); +-- synopsys translate_off + + +-- synopsys translate_on +end pcq_dbg; + +architecture pcq_dbg of pcq_dbg is +constant fuevents_size : positive := 8; +constant iuevents_size : positive := 8; +constant mmevents_size : positive := 8; +constant xuevents_size : positive := 8; +constant lsuevents_size : positive := 8; +constant trcevents_size : positive := 8; +constant eventbus_size : positive := 8; +constant scrdata_size : positive := 64; +constant scwdata_size : positive := 64; +constant scmisc_size : positive := 3; +constant ramthrctl_size : positive := 4; +constant traceout_size : positive := 88; +constant triggout_size : positive := 12; + +constant fuevents_offset : natural := 0; +constant fubypass_offset : natural := fuevents_offset + fuevents_size; +constant iuevents_offset : natural := fubypass_offset + fuevents_size; +constant iubypass_offset : natural := iuevents_offset + iuevents_size; +constant mmevents_offset : natural := iubypass_offset + iuevents_size; +constant mmbypass_offset : natural := mmevents_offset + mmevents_size; +constant xuevents_offset : natural := mmbypass_offset + mmevents_size; +constant lsuevents_offset : natural := xuevents_offset + xuevents_size; +constant lsubypass_offset : natural := lsuevents_offset + lsuevents_size; +constant trcevents_offset : natural := lsubypass_offset + lsuevents_size; +constant eventbus_offset : natural := trcevents_offset + trcevents_size; +constant scrdata_offset : natural := eventbus_offset + eventbus_size; +constant scwdata_offset : natural := scrdata_offset + scrdata_size; +constant scmisc_offset : natural := scwdata_offset + scwdata_size; +constant ramthrctl_offset : natural := scmisc_offset + scmisc_size; +constant traceout_offset : natural := ramthrctl_offset + ramthrctl_size; +constant triggout_offset : natural := traceout_offset + traceout_size; +constant func_right : natural := triggout_offset + triggout_size - 1; + +signal func_siv, func_sov : std_ulogic_vector(0 to func_right); +signal pc_pc_func_slp_sl_thold_0_b : std_ulogic; +signal force_func : std_ulogic; +signal debug_group_0 : std_ulogic_vector(0 to traceout_size-1); +signal debug_group_1 : std_ulogic_vector(0 to traceout_size-1); +signal debug_group_2 : std_ulogic_vector(0 to traceout_size-1); +signal debug_group_3 : std_ulogic_vector(0 to traceout_size-1); +signal debug_group_4 : std_ulogic_vector(0 to traceout_size-1); +signal debug_group_5 : std_ulogic_vector(0 to traceout_size-1); +signal debug_group_6 : std_ulogic_vector(0 to traceout_size-1); +signal debug_group_7 : std_ulogic_vector(0 to traceout_size-1); +signal trigg_group_0 : std_ulogic_vector(0 to triggout_size-1); +signal trigg_group_1 : std_ulogic_vector(0 to triggout_size-1); +signal trigg_group_2 : std_ulogic_vector(0 to triggout_size-1); +signal trigg_group_3 : std_ulogic_vector(0 to triggout_size-1); +signal fir_icache_parity_q : std_ulogic; +signal fir_icachedir_parity_q : std_ulogic; +signal fir_dcache_parity_q : std_ulogic; +signal fir_dcachedir_parity_q : std_ulogic; +signal fir_sprg_ecc_q : std_ulogic_vector(0 to 3); +signal fir_xu_regf_parity_q : std_ulogic_vector(0 to 3); +signal fir_fu_regf_parity_q : std_ulogic_vector(0 to 3); +signal fir_mcsr_summary_q : std_ulogic_vector(0 to 3); +signal fir_ierat_parity_q : std_ulogic; +signal fir_derat_parity_q : std_ulogic; +signal fir_tlb_parity_q : std_ulogic; +signal fir_tlb_lru_parity_q : std_ulogic; +signal fir_ierat_multihit_q : std_ulogic; +signal fir_derat_multihit_q : std_ulogic; +signal fir_tlb_multihit_q : std_ulogic; +signal fir_external_mchk_q : std_ulogic; +signal fir_ditc_overrun_q : std_ulogic; +signal fir_local_snoop_rej_q : std_ulogic; +signal fir_inbox_ecc_q : std_ulogic; +signal fir_outbox_ecc_q : std_ulogic; +signal fir_scom_reg_parity_q : std_ulogic; +signal fir_scom_ack_err_q : std_ulogic; +signal fir_icachedir_multi_q : std_ulogic; +signal fir_dcachedir_multi_q : std_ulogic; +signal fir_wdt_reset_q : std_ulogic_vector(0 to 3); +signal fir_llbust_attempt_q : std_ulogic_vector(0 to 3); +signal fir_llbust_failed_q : std_ulogic_vector(0 to 3); +signal fir_max_recov_cntr_q : std_ulogic; +signal fir_l2intrf_ecc_q : std_ulogic; +signal fir_l2intrf_ue_q : std_ulogic; +signal fir_l2credit_overrun_q : std_ulogic; +signal fir_sprg_ue_q : std_ulogic; +signal fir_xu_regf_ue_q : std_ulogic; +signal fir_fu_regf_ue_q : std_ulogic; +signal fir_nia_miscmpr_q : std_ulogic; +signal fir_debug_event_q : std_ulogic_vector(0 to 3); +signal fir_inbox_ue_q : std_ulogic; +signal fir_outbox_ue_q : std_ulogic; +signal fir_invld_reld_q : std_ulogic; +signal fir_ucode_illegal_q : std_ulogic; +signal fir_attention_instr_q : std_ulogic_vector(0 to 3); +signal fir_xstop_err_q : std_ulogic_vector(0 to 2); +signal fir_recov_err_q : std_ulogic_vector(0 to 2); +signal fir_scom_err_report_q : std_ulogic_vector(0 to 17); +signal fir_xstop_per_thread_d : std_ulogic_vector(0 to 3); +signal fir_xstop_per_thread_q : std_ulogic_vector(0 to 3); +signal fir_block_ram_mode_q : std_ulogic; +signal fir0_recov_err_pulse_q : std_ulogic; +signal fir1_recov_err_pulse_q : std_ulogic; +signal fir2_recov_err_pulse_q : std_ulogic; +signal scom_rdata_d, scom_rdata_q : std_ulogic_vector(0 to 63); +signal scom_wdata_d, scom_wdata_q : std_ulogic_vector(0 to 63); +signal scom_decaddr_q : std_ulogic_vector(0 to 63); +signal scom_misc_sc_act_d : std_ulogic; +signal scom_misc_sc_act_q : std_ulogic; +signal scom_misc_sc_req_q : std_ulogic; +signal scom_misc_sc_wr_q : std_ulogic; +signal scom_misc_sc_nvld_q : std_ulogic_vector(0 to 2); +signal scom_misc_scaddr_fir_d : std_ulogic; +signal scom_misc_scaddr_fir_q : std_ulogic; +signal scom_misc_sc_par_inj_q : std_ulogic; +signal scom_misc_sc_wparity_d : std_ulogic; +signal scom_misc_sc_wparity_q : std_ulogic; +signal ram_execute_q : std_ulogic; +signal ram_interrupt_q : std_ulogic; +signal ram_error_q : std_ulogic; +signal ram_done_q : std_ulogic; +signal ram_thread_q : std_ulogic_vector(0 to 1); +signal ram_mode_q : std_ulogic; +signal ram_xu_done_in_q : std_ulogic; +signal ram_fu_done_in_q : std_ulogic; +signal thrctl_stop_out_q : std_ulogic_vector(0 to 3); +signal thrctl_step_out_q : std_ulogic_vector(0 to 3); +signal thrctl_run_in_q : std_ulogic_vector(0 to 3); +signal ctrls_init_active_q : std_ulogic; +signal ctrls_resetsm_q : std_ulogic_vector(0 to 4); +signal ctrls_initerat_q : std_ulogic; +signal ctrls_reset_cmplt_q : std_ulogic_vector(0 to 3); +signal ctrls_pm_stop_q : std_ulogic_vector(0 to 3); +signal ctrls_pm_state_q : std_ulogic_vector(0 to 3); +signal ctrls_pm_rvwinkled_q : std_ulogic; +signal ctrls_ccr0_pme_q : std_ulogic_vector(0 to 1); +signal ctrls_ccr0_we_q : std_ulogic_vector(0 to 3); +signal ctrls_pmclkctrl_dly_q : std_ulogic_vector(0 to 7); +signal ctrls_dis_pwr_sav_q : std_ulogic; +signal ctrls_ccflush_dis_q : std_ulogic; +signal ctrls_raise_tholds_q : std_ulogic; +signal clks_ccenable_dc : std_ulogic; +signal clks_fast_xstop : std_ulogic; +signal clks_scan_type_dc : std_ulogic_vector(0 to 7); +signal clks_gsd_tst_en_dc : std_ulogic; +signal clks_gsd_tst_ac_dc : std_ulogic; +signal clks_lbist_en_dc : std_ulogic; +signal clks_lbist_ip_dc : std_ulogic; +signal spr_slowspr_val_l2 : std_ulogic; +signal spr_slowspr_rw_l2 : std_ulogic; +signal spr_slowspr_etid_l2 : std_ulogic_vector(0 to 1); +signal spr_slowspr_addr_l2 : std_ulogic_vector(0 to 9); +signal spr_slowspr_data_l2 : std_ulogic_vector(0 to 31); +signal spr_pc_done_l2 : std_ulogic; + +signal fu_events_d, fu_events_q : std_ulogic_vector(0 to fuevents_size-1); +signal fu_bypass_q : std_ulogic_vector(0 to fuevents_size-1); +signal iu_events_d, iu_events_q : std_ulogic_vector(0 to iuevents_size-1); +signal iu_bypass_q : std_ulogic_vector(0 to iuevents_size-1); +signal mm_events_d, mm_events_q : std_ulogic_vector(0 to mmevents_size-1); +signal mm_bypass_q : std_ulogic_vector(0 to mmevents_size-1); +signal xu_events_d, xu_events_q : std_ulogic_vector(0 to xuevents_size-1); +signal lsu_events_d, lsu_events_q : std_ulogic_vector(0 to lsuevents_size-1); +signal lsu_bypass_q : std_ulogic_vector(0 to lsuevents_size-1); +signal trc_events_d, trc_events_q : std_ulogic_vector(0 to trcevents_size-1); +signal event_bus_d, event_bus_q : std_ulogic_vector(0 to eventbus_size-1); +signal trace_data_out_d : std_ulogic_vector(0 to traceout_size-1); +signal trace_data_out_q : std_ulogic_vector(0 to traceout_size-1); +signal trigg_data_out_d : std_ulogic_vector(0 to triggout_size-1); +signal trigg_data_out_q : std_ulogic_vector(0 to triggout_size-1); +signal unused_signals : std_ulogic; + + +begin + + unused_signals <= or_reduce(rg_db_dbg_fir2_err(14 to 19) ); + + + fu_events_d <= fu_pc_event_data; + iu_events_d <= iu_pc_event_data; + mm_events_d <= mm_pc_event_data; + xu_events_d <= xu_pc_event_data; + lsu_events_d <= lsu_pc_event_data; + trc_events_d <= ac_pc_trace_to_perfcntr; + + +event_mux: entity work.pcq_dbg_event + generic map( expand_type => expand_type ) + port map + ( vd => vdd + , gd => gnd + , event_mux_ctrls => rg_db_event_mux_ctrls + , fu_event_data => fu_events_q + , iu_event_data => iu_events_q + , mm_event_data => mm_events_q + , xu_event_data => xu_events_q + , lsu_event_data => lsu_events_q + , trace_bus_data => trc_events_q + , event_bus => event_bus_d + ); + + + fir_icache_parity_q <= rg_db_dbg_fir0_err(0); + fir_icachedir_parity_q <= rg_db_dbg_fir0_err(1); + fir_dcache_parity_q <= rg_db_dbg_fir0_err(2); + fir_dcachedir_parity_q <= rg_db_dbg_fir0_err(3); + fir_sprg_ecc_q <= rg_db_dbg_fir0_err(4 to 7); + fir_xu_regf_parity_q <= rg_db_dbg_fir0_err(8 to 11); + fir_fu_regf_parity_q <= rg_db_dbg_fir0_err(12 to 15); + fir_inbox_ecc_q <= rg_db_dbg_fir0_err(16); + fir_outbox_ecc_q <= rg_db_dbg_fir0_err(17); + fir_scom_reg_parity_q <= rg_db_dbg_fir0_err(18); + fir_scom_ack_err_q <= rg_db_dbg_fir0_err(19); + fir_wdt_reset_q <= rg_db_dbg_fir0_err(20 to 23); + fir_llbust_attempt_q <= rg_db_dbg_fir0_err(24 to 27); + fir_llbust_failed_q <= rg_db_dbg_fir0_err(28 to 31); + fir_max_recov_cntr_q <= rg_db_dbg_fir1_err(0); + fir_l2intrf_ecc_q <= rg_db_dbg_fir1_err(1); + fir_l2intrf_ue_q <= rg_db_dbg_fir1_err(2); + fir_l2credit_overrun_q <= rg_db_dbg_fir1_err(3); + fir_sprg_ue_q <= or_reduce(rg_db_dbg_fir1_err(4 to 7)); + fir_xu_regf_ue_q <= or_reduce(rg_db_dbg_fir1_err(8 to 11)); + fir_fu_regf_ue_q <= or_reduce(rg_db_dbg_fir1_err(12 to 15)); + fir_nia_miscmpr_q <= or_reduce(rg_db_dbg_fir1_err(16 to 19)); + fir_debug_event_q <= rg_db_dbg_fir1_err(20 to 23); + fir_ucode_illegal_q <= or_reduce(rg_db_dbg_fir1_err(24 to 27)); + fir_inbox_ue_q <= rg_db_dbg_fir1_err(28); + fir_outbox_ue_q <= rg_db_dbg_fir1_err(29); + fir_invld_reld_q <= rg_db_dbg_fir1_err(30); + fir_mcsr_summary_q <= rg_db_dbg_fir2_err(0 to 3); + fir_ierat_parity_q <= rg_db_dbg_fir2_err(4); + fir_derat_parity_q <= rg_db_dbg_fir2_err(5); + fir_tlb_parity_q <= rg_db_dbg_fir2_err(6); + fir_tlb_lru_parity_q <= rg_db_dbg_fir2_err(7); + fir_ierat_multihit_q <= rg_db_dbg_fir2_err(8); + fir_derat_multihit_q <= rg_db_dbg_fir2_err(9); + fir_tlb_multihit_q <= rg_db_dbg_fir2_err(10); + fir_external_mchk_q <= rg_db_dbg_fir2_err(11); + fir_local_snoop_rej_q <= rg_db_dbg_fir2_err(12); + fir_ditc_overrun_q <= rg_db_dbg_fir2_err(13); + fir_icachedir_multi_q <= rg_db_dbg_fir2_err(20); + fir_dcachedir_multi_q <= rg_db_dbg_fir2_err(21); + fir_attention_instr_q <= rg_db_dbg_fir_misc(0 to 3); + fir_xstop_err_q <= rg_db_dbg_fir_misc(4 to 6); + fir_recov_err_q <= rg_db_dbg_fir_misc(7 to 9); + fir_scom_err_report_q <= rg_db_dbg_fir_misc(10 to 27); + fir_xstop_per_thread_d <= rg_db_dbg_fir_misc(28 to 31); + fir_block_ram_mode_q <= rg_db_dbg_fir_misc(32); + fir0_recov_err_pulse_q <= rg_db_dbg_fir_misc(33); + fir1_recov_err_pulse_q <= rg_db_dbg_fir_misc(34); + fir2_recov_err_pulse_q <= rg_db_dbg_fir_misc(35); + scom_rdata_d <= rg_db_dbg_scom_rdata(0 to 63); + scom_wdata_d <= rg_db_dbg_scom_wdata(0 to 63); + scom_decaddr_q <= rg_db_dbg_scom_decaddr(0 to 63); + scom_misc_sc_act_d <= rg_db_dbg_scom_misc(0); + scom_misc_sc_req_q <= rg_db_dbg_scom_misc(1); + scom_misc_sc_wr_q <= rg_db_dbg_scom_misc(2); + scom_misc_sc_nvld_q <= rg_db_dbg_scom_misc(3 to 5); + scom_misc_scaddr_fir_d <= rg_db_dbg_scom_misc(6); + scom_misc_sc_par_inj_q <= rg_db_dbg_scom_misc(7); + scom_misc_sc_wparity_d <= rg_db_dbg_scom_misc(8); + ram_execute_q <= rg_db_dbg_ram_thrctl(0); + ram_interrupt_q <= rg_db_dbg_ram_thrctl(1); + ram_error_q <= rg_db_dbg_ram_thrctl(2); + ram_done_q <= rg_db_dbg_ram_thrctl(3); + ram_thread_q <= rg_db_dbg_ram_thrctl(4 to 5); + ram_mode_q <= rg_db_dbg_ram_thrctl(6); + ram_xu_done_in_q <= rg_db_dbg_ram_thrctl(7); + ram_fu_done_in_q <= rg_db_dbg_ram_thrctl(8); + thrctl_stop_out_q <= rg_db_dbg_ram_thrctl(9 to 12); + thrctl_step_out_q <= rg_db_dbg_ram_thrctl(13 to 16); + thrctl_run_in_q <= rg_db_dbg_ram_thrctl(17 to 20); + ctrls_init_active_q <= ct_db_dbg_ctrls(0); + ctrls_resetsm_q <= ct_db_dbg_ctrls(1 to 5); + ctrls_initerat_q <= ct_db_dbg_ctrls(6); + ctrls_reset_cmplt_q <= ct_db_dbg_ctrls(7 to 10); + ctrls_pm_stop_q <= ct_db_dbg_ctrls(11 to 14); + ctrls_pm_state_q <= ct_db_dbg_ctrls(15 to 18); + ctrls_pm_rvwinkled_q <= ct_db_dbg_ctrls(19); + ctrls_ccr0_pme_q <= ct_db_dbg_ctrls(20 to 21); + ctrls_ccr0_we_q <= ct_db_dbg_ctrls(22 to 25); + ctrls_pmclkctrl_dly_q <= ct_db_dbg_ctrls(26 to 33); + ctrls_dis_pwr_sav_q <= ct_db_dbg_ctrls(34); + ctrls_ccflush_dis_q <= ct_db_dbg_ctrls(35); + ctrls_raise_tholds_q <= ct_db_dbg_ctrls(36); + clks_ccenable_dc <= ck_db_dbg_clks_ctrls(0); + clks_gsd_tst_en_dc <= ck_db_dbg_clks_ctrls(1); + clks_gsd_tst_ac_dc <= ck_db_dbg_clks_ctrls(2); + clks_lbist_en_dc <= ck_db_dbg_clks_ctrls(3); + clks_lbist_ip_dc <= ck_db_dbg_clks_ctrls(4); + clks_scan_type_dc <= ck_db_dbg_clks_ctrls(5 to 12); + clks_fast_xstop <= ck_db_dbg_clks_ctrls(13); + spr_slowspr_val_l2 <= rg_db_dbg_spr(0); + spr_slowspr_rw_l2 <= rg_db_dbg_spr(1); + spr_slowspr_etid_l2 <= rg_db_dbg_spr(2 to 3); + spr_slowspr_addr_l2 <= rg_db_dbg_spr(4 to 13); + spr_slowspr_data_l2 <= rg_db_dbg_spr(14 to 45); + spr_pc_done_l2 <= rg_db_dbg_spr(46); + + + debug_group_0 <= fir_icache_parity_q & fir_icachedir_parity_q & fir_dcache_parity_q & + fir_dcachedir_parity_q & fir_sprg_ecc_q(0 to 3) & fir_nia_miscmpr_q & + fir_l2intrf_ue_q & fir_sprg_ue_q & fir_invld_reld_q & fir_xu_regf_ue_q & + fir_fu_regf_ue_q & fir_inbox_ue_q & fir_outbox_ue_q & fir_l2credit_overrun_q & + fir_ucode_illegal_q & scom_wdata_q(0 to 63) & "000000"; + + debug_group_1 <= scom_misc_sc_act_q & scom_misc_sc_req_q & scom_misc_sc_wr_q & + scom_misc_sc_nvld_q(0 to 2) & scom_misc_scaddr_fir_q & scom_misc_sc_wparity_q & + scom_misc_sc_par_inj_q & fir_block_ram_mode_q & ram_mode_q & ram_thread_q(0 to 1) & + ram_execute_q & ram_interrupt_q & ram_error_q & ram_done_q & ram_xu_done_in_q & + ram_fu_done_in_q & scom_rdata_q(0 to 63) & "00000"; + + debug_group_2 <= fir_fu_regf_parity_q(0 to 3) & fir_xu_regf_parity_q(0 to 3) & ctrls_init_active_q & + ctrls_resetsm_q(0 to 4) & ctrls_initerat_q & ctrls_reset_cmplt_q(0 to 3) & + scom_decaddr_q(0 to 63) & "00000"; + + debug_group_3 <= fir_mcsr_summary_q(0 to 3) & fir_ierat_parity_q & fir_derat_parity_q & + fir_tlb_parity_q & fir_tlb_lru_parity_q & fir_scom_err_report_q(0 to 17) & + thrctl_run_in_q(0 to 3) & thrctl_stop_out_q(0 to 3) & + thrctl_step_out_q(0 to 3) & fir_attention_instr_q(0 to 3) & + fir_scom_reg_parity_q & fir_scom_ack_err_q & fir_recov_err_q(0 to 2) & + fir_xstop_err_q(0 to 2) & fir_xstop_per_thread_q(0 to 3) & x"00000000" & "00"; + + debug_group_4 <= fir_ierat_multihit_q & fir_derat_multihit_q & fir_tlb_multihit_q & + fir_external_mchk_q & fir_local_snoop_rej_q & fir_ditc_overrun_q & + ctrls_pm_stop_q(0 to 3) & ctrls_pm_state_q(0 to 3) & ctrls_ccr0_pme_q(0 to 1) & + ctrls_ccr0_we_q(0 to 3) & ctrls_pm_rvwinkled_q & clks_ccenable_dc & + clks_scan_type_dc(0 to 7) & clks_gsd_tst_en_dc & clks_gsd_tst_ac_dc & + clks_lbist_en_dc & clks_lbist_ip_dc & clks_fast_xstop & + ctrls_pmclkctrl_dly_q(0 to 7) & ctrls_ccflush_dis_q & ctrls_dis_pwr_sav_q & + ctrls_raise_tholds_q & x"0000000000" & "00"; + + debug_group_5 <= fir_icachedir_multi_q & fir_dcachedir_multi_q & fir_inbox_ecc_q & + fir_outbox_ecc_q & fir_l2intrf_ecc_q & fir0_recov_err_pulse_q & + fir1_recov_err_pulse_q & fir2_recov_err_pulse_q & fir_max_recov_cntr_q & + x"0000000000000000000" & "000"; + + debug_group_6 <= fir_llbust_attempt_q(0 to 3) & fir_llbust_failed_q(0 to 3) & + x"00000000000000000000"; + + debug_group_7 <= fir_wdt_reset_q(0 to 3) & fir_debug_event_q(0 to 3) & + spr_slowspr_val_l2 & spr_slowspr_rw_l2 & spr_pc_done_l2 & + spr_slowspr_etid_l2(0 to 1) & spr_slowspr_addr_l2(0 to 9) & + spr_slowspr_data_l2(0 to 31) & x"00000000" & "0"; + + + trigg_group_0 <= scom_misc_sc_act_q & scom_misc_sc_req_q & scom_misc_sc_wr_q & + scom_misc_sc_nvld_q(0 to 2) & scom_misc_scaddr_fir_q & + thrctl_stop_out_q(0 to 3) & ctrls_initerat_q; + + trigg_group_1 <= ram_mode_q & ram_execute_q & ram_interrupt_q & ram_error_q & + ram_done_q & ctrls_pm_stop_q(0 to 3) & ctrls_ccr0_pme_q(0 to 1) & + ctrls_ccflush_dis_q; + + trigg_group_2 <= fir_xstop_err_q(0 to 2) & fir_recov_err_q(0 to 2) & + fir_mcsr_summary_q(0 to 3) & fir_external_mchk_q & + fir_l2intrf_ecc_q; + + trigg_group_3 <= fir_wdt_reset_q(0 to 3) & fir_llbust_attempt_q(0 to 3) & + thrctl_run_in_q(0 to 3); + + + + +debug_mux: entity clib.c_debug_mux8 + port map + ( vd => vdd + ,gd => gnd + + ,select_bits => rg_db_debug_mux_ctrls + ,trace_data_in => debug_bus_in + ,trigger_data_in => trace_triggers_in + + ,dbg_group0 => debug_group_0 + ,dbg_group1 => debug_group_1 + ,dbg_group2 => debug_group_2 + ,dbg_group3 => debug_group_3 + ,dbg_group4 => debug_group_4 + ,dbg_group5 => debug_group_5 + ,dbg_group6 => debug_group_6 + ,dbg_group7 => debug_group_7 + + ,trg_group0 => trigg_group_0 + ,trg_group1 => trigg_group_1 + ,trg_group2 => trigg_group_2 + ,trg_group3 => trigg_group_3 + + ,trace_data_out => trace_data_out_d + ,trigger_data_out => trigg_data_out_d + ); + + + ac_an_event_bus <= event_bus_q; + ac_an_fu_bypass_events <= fu_bypass_q; + ac_an_iu_bypass_events <= iu_bypass_q; + ac_an_mm_bypass_events <= mm_bypass_q; + ac_an_lsu_bypass_events <= lsu_bypass_q; + + + debug_bus_out <= trace_data_out_q; + + trace_triggers_out <= trigg_data_out_q; + + +fuevents: tri_rlmreg_p + generic map (width => fuevents_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rg_db_event_bus_enable, + thold_b => pc_pc_func_slp_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(fuevents_offset to fuevents_offset + fuevents_size-1), + scout => func_sov(fuevents_offset to fuevents_offset + fuevents_size-1), + din => fu_events_d, + dout => fu_events_q ); + +fubypass: tri_rlmreg_p + generic map (width => fuevents_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rg_db_event_bus_enable, + thold_b => pc_pc_func_slp_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(fubypass_offset to fubypass_offset + fuevents_size-1), + scout => func_sov(fubypass_offset to fubypass_offset + fuevents_size-1), + din => fu_events_q, + dout => fu_bypass_q ); + +iuevents: tri_rlmreg_p + generic map (width => iuevents_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rg_db_event_bus_enable, + thold_b => pc_pc_func_slp_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(iuevents_offset to iuevents_offset + iuevents_size-1), + scout => func_sov(iuevents_offset to iuevents_offset + iuevents_size-1), + din => iu_events_d, + dout => iu_events_q ); + +iubypass: tri_rlmreg_p + generic map (width => iuevents_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rg_db_event_bus_enable, + thold_b => pc_pc_func_slp_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(iubypass_offset to iubypass_offset + iuevents_size-1), + scout => func_sov(iubypass_offset to iubypass_offset + iuevents_size-1), + din => iu_events_q, + dout => iu_bypass_q ); + +mmevents: tri_rlmreg_p + generic map (width => mmevents_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rg_db_event_bus_enable, + thold_b => pc_pc_func_slp_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(mmevents_offset to mmevents_offset + mmevents_size-1), + scout => func_sov(mmevents_offset to mmevents_offset + mmevents_size-1), + din => mm_events_d, + dout => mm_events_q ); + +mmbypass: tri_rlmreg_p + generic map (width => mmevents_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rg_db_event_bus_enable, + thold_b => pc_pc_func_slp_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(mmbypass_offset to mmbypass_offset + mmevents_size-1), + scout => func_sov(mmbypass_offset to mmbypass_offset + mmevents_size-1), + din => mm_events_q, + dout => mm_bypass_q ); + +xuevents: tri_rlmreg_p + generic map (width => xuevents_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rg_db_event_bus_enable, + thold_b => pc_pc_func_slp_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(xuevents_offset to xuevents_offset + xuevents_size-1), + scout => func_sov(xuevents_offset to xuevents_offset + xuevents_size-1), + din => xu_events_d, + dout => xu_events_q ); + +lsuevents: tri_rlmreg_p + generic map (width => lsuevents_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rg_db_event_bus_enable, + thold_b => pc_pc_func_slp_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(lsuevents_offset to lsuevents_offset + lsuevents_size-1), + scout => func_sov(lsuevents_offset to lsuevents_offset + lsuevents_size-1), + din => lsu_events_d, + dout => lsu_events_q ); + +lsubypass: tri_rlmreg_p + generic map (width => lsuevents_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rg_db_event_bus_enable, + thold_b => pc_pc_func_slp_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(lsubypass_offset to lsubypass_offset + lsuevents_size-1), + scout => func_sov(lsubypass_offset to lsubypass_offset + lsuevents_size-1), + din => lsu_events_q, + dout => lsu_bypass_q ); + +trcevents: tri_rlmreg_p + generic map (width => trcevents_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rg_db_event_bus_enable, + thold_b => pc_pc_func_slp_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(trcevents_offset to trcevents_offset + trcevents_size-1), + scout => func_sov(trcevents_offset to trcevents_offset + trcevents_size-1), + din => trc_events_d, + dout => trc_events_q ); + +eventbus: tri_rlmreg_p + generic map (width => eventbus_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rg_db_event_bus_enable, + thold_b => pc_pc_func_slp_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(eventbus_offset to eventbus_offset + eventbus_size-1), + scout => func_sov(eventbus_offset to eventbus_offset + eventbus_size-1), + din => event_bus_d, + dout => event_bus_q ); + +scrdata: tri_rlmreg_p + generic map (width => scrdata_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rg_db_trace_bus_enable, + thold_b => pc_pc_func_slp_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(scrdata_offset to scrdata_offset + scrdata_size-1), + scout => func_sov(scrdata_offset to scrdata_offset + scrdata_size-1), + din => scom_rdata_d, + dout => scom_rdata_q ); + +scwdata: tri_rlmreg_p + generic map (width => scwdata_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rg_db_trace_bus_enable, + thold_b => pc_pc_func_slp_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(scwdata_offset to scwdata_offset + scwdata_size-1), + scout => func_sov(scwdata_offset to scwdata_offset + scwdata_size-1), + din => scom_wdata_d, + dout => scom_wdata_q ); + +scmisc: tri_rlmreg_p + generic map (width => scmisc_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rg_db_trace_bus_enable, + thold_b => pc_pc_func_slp_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(scmisc_offset to scmisc_offset + scmisc_size-1), + scout => func_sov(scmisc_offset to scmisc_offset + scmisc_size-1), + din(0) => scom_misc_sc_act_d, + din(1) => scom_misc_scaddr_fir_d, + din(2) => scom_misc_sc_wparity_d, + dout(0) => scom_misc_sc_act_q, + dout(1) => scom_misc_scaddr_fir_q, + dout(2) => scom_misc_sc_wparity_q ); + +ramthrctl: tri_rlmreg_p + generic map (width => ramthrctl_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rg_db_trace_bus_enable, + thold_b => pc_pc_func_slp_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(ramthrctl_offset to ramthrctl_offset + ramthrctl_size-1), + scout => func_sov(ramthrctl_offset to ramthrctl_offset + ramthrctl_size-1), + din(0 to 3) => fir_xstop_per_thread_d, + dout(0 to 3) => fir_xstop_per_thread_q ); + + +traceout: tri_rlmreg_p + generic map (width => traceout_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rg_db_trace_bus_enable, + thold_b => pc_pc_func_slp_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(traceout_offset to traceout_offset + traceout_size-1), + scout => func_sov(traceout_offset to traceout_offset + traceout_size-1), + din => trace_data_out_d, + dout => trace_data_out_q ); + +triggout: tri_rlmreg_p + generic map (width => triggout_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rg_db_trace_bus_enable, + thold_b => pc_pc_func_slp_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(triggout_offset to triggout_offset + triggout_size-1), + scout => func_sov(triggout_offset to triggout_offset + triggout_size-1), + din => trigg_data_out_d, + dout => trigg_data_out_q ); + + +lcbor_func0: tri_lcbor +generic map (expand_type => expand_type ) +port map ( + clkoff_b => lcb_clkoff_dc_b, + thold => pc_pc_func_slp_sl_thold_0, + sg => pc_pc_sg_0, + act_dis => lcb_act_dis_dc, + forcee => force_func, + thold_b => pc_pc_func_slp_sl_thold_0_b ); + + +func_siv(0 TO func_right) <= func_scan_in & func_sov(0 to func_right-1); +func_scan_out <= func_sov(func_right) and scan_dis_dc_b; + + +end pcq_dbg; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/pcq_dbg_event.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/pcq_dbg_event.vhdl new file mode 100644 index 0000000..962a5a0 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/pcq_dbg_event.vhdl @@ -0,0 +1,148 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee; +use ieee.std_logic_1164.all; +library support; +use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity pcq_dbg_event is +generic(expand_type : integer := 2 +); +port( + vd : inout power_logic; + gd : inout power_logic; + event_mux_ctrls : in std_ulogic_vector(0 to 23); + fu_event_data : in std_ulogic_vector(0 to 7); + iu_event_data : in std_ulogic_vector(0 to 7); + mm_event_data : in std_ulogic_vector(0 to 7); + xu_event_data : in std_ulogic_vector(0 to 7); + lsu_event_data : in std_ulogic_vector(0 to 7); + trace_bus_data : in std_ulogic_vector(0 to 7); + event_bus : out std_ulogic_vector(0 to 7) +); +-- synopsys translate_off + +-- synopsys translate_on +end pcq_dbg_event; + +architecture pcq_dbg_event of pcq_dbg_event is +signal event_signals_per_bit : std_ulogic_vector(0 to 7); + + +begin + + + with event_mux_ctrls(0 to 2) select + event_signals_per_bit(0) <= xu_event_data(0) when "000", + iu_event_data(0) when "001", + fu_event_data(0) when "010", + mm_event_data(0) when "011", + lsu_event_data(0) when "100", + xu_event_data(4) when "101", + iu_event_data(4) when "110", + trace_bus_data(0) when others; + + with event_mux_ctrls(3 to 5) select + event_signals_per_bit(1) <= xu_event_data(1) when "000", + iu_event_data(1) when "001", + fu_event_data(1) when "010", + mm_event_data(1) when "011", + lsu_event_data(1) when "100", + xu_event_data(5) when "101", + iu_event_data(5) when "110", + trace_bus_data(1) when others; + + with event_mux_ctrls(6 to 8) select + event_signals_per_bit(2) <= xu_event_data(2) when "000", + iu_event_data(2) when "001", + fu_event_data(2) when "010", + mm_event_data(2) when "011", + lsu_event_data(2) when "100", + xu_event_data(6) when "101", + iu_event_data(6) when "110", + trace_bus_data(2) when others; + + with event_mux_ctrls(9 to 11) select + event_signals_per_bit(3) <= xu_event_data(3) when "000", + iu_event_data(3) when "001", + fu_event_data(3) when "010", + mm_event_data(3) when "011", + lsu_event_data(3) when "100", + xu_event_data(7) when "101", + iu_event_data(7) when "110", + trace_bus_data(3) when others; + + with event_mux_ctrls(12 to 14) select + event_signals_per_bit(4) <= xu_event_data(4) when "000", + iu_event_data(4) when "001", + fu_event_data(4) when "010", + mm_event_data(4) when "011", + lsu_event_data(4) when "100", + xu_event_data(0) when "101", + iu_event_data(0) when "110", + trace_bus_data(4) when others; + + with event_mux_ctrls(15 to 17) select + event_signals_per_bit(5) <= xu_event_data(5) when "000", + iu_event_data(5) when "001", + fu_event_data(5) when "010", + mm_event_data(5) when "011", + lsu_event_data(5) when "100", + xu_event_data(1) when "101", + iu_event_data(1) when "110", + trace_bus_data(5) when others; + + with event_mux_ctrls(18 to 20) select + event_signals_per_bit(6) <= xu_event_data(6) when "000", + iu_event_data(6) when "001", + fu_event_data(6) when "010", + mm_event_data(6) when "011", + lsu_event_data(6) when "100", + xu_event_data(2) when "101", + iu_event_data(2) when "110", + trace_bus_data(6) when others; + + with event_mux_ctrls(21 to 23) select + event_signals_per_bit(7) <= xu_event_data(7) when "000", + iu_event_data(7) when "001", + fu_event_data(7) when "010", + mm_event_data(7) when "011", + lsu_event_data(7) when "100", + xu_event_data(3) when "101", + iu_event_data(3) when "110", + trace_bus_data(7) when others; + + + event_bus(0 to 7) <= event_signals_per_bit(0 to 7); + + +end pcq_dbg_event; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/pcq_local_fir2.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/pcq_local_fir2.vhdl new file mode 100644 index 0000000..13509ab --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/pcq_local_fir2.vhdl @@ -0,0 +1,534 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee; +use ieee.std_logic_1164.all; +library ibm; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +library support; +use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + + +entity pcq_local_fir2 is + generic(width : positive := 1; + expand_type : integer := 2; + impl_lxstop_mchk : boolean := false; + use_recov_reset : boolean := false; + fir_init : std_ulogic_vector := "0"; + fir_mask_init : std_ulogic_vector := "0"; + fir_mask_par_init : std_ulogic_vector := "0"; + fir_action0_init : std_ulogic_vector := "0"; + fir_action0_par_init : std_ulogic_vector := "0"; + fir_action1_init : std_ulogic_vector := "0"; + fir_action1_par_init : std_ulogic_vector := "0"); + port + ( nclk : in clk_logic + ; vd : inout power_logic + ; gd : inout power_logic + ; lcb_clkoff_dc_b : in std_ulogic + ; lcb_mpw1_dc_b : in std_ulogic + ; lcb_mpw2_dc_b : in std_ulogic + ; lcb_delay_lclkr_dc : in std_ulogic + ; lcb_act_dis_dc : in std_ulogic + ; lcb_sg_0 : in std_ulogic + ; lcb_func_slp_sl_thold_0 : in std_ulogic := '0' + ; lcb_cfg_slp_sl_thold_0 : in std_ulogic := '0' + ; mode_scan_siv : in std_ulogic_vector(0 to 3*(width+1)+width-1) + ; mode_scan_sov : out std_ulogic_vector(0 to 3*(width+1)+width-1) + ; func_scan_siv : in std_ulogic_vector(0 to 4) + ; func_scan_sov : out std_ulogic_vector(0 to 4) + ; sys_xstop_in : in std_ulogic := '0' + ; error_in : in std_ulogic_vector(0 to width-1) + ; xstop_err : out std_ulogic + ; recov_err : out std_ulogic + ; lxstop_mchk : out std_ulogic + ; trace_error : out std_ulogic + ; recov_reset : in std_ulogic := '0' + ; fir_out : out std_ulogic_vector(0 to width-1) + ; act0_out : out std_ulogic_vector(0 to width-1) + ; act1_out : out std_ulogic_vector(0 to width-1) + ; mask_out : out std_ulogic_vector(0 to width-1) + ; sc_parity_error_inject : in std_ulogic + ; sc_active : in std_ulogic + ; sc_wr_q : in std_ulogic + ; sc_addr_v : in std_ulogic_vector(0 to 8) + ; sc_wdata : in std_ulogic_vector(0 to width-1) + ; sc_wparity : in std_ulogic + ; sc_rdata : out std_ulogic_vector(0 to width-1) + ; fir_parity_check : out std_ulogic_vector(0 to 2) + ); + + + +end pcq_local_fir2; + + +architecture pcq_local_fir2 of pcq_local_fir2 is + signal func_d1clk : std_ulogic; + signal func_d2clk : std_ulogic; + signal func_lclk : clk_logic; + signal mode_d1clk : std_ulogic; + signal mode_d2clk : std_ulogic; + signal mode_lclk : clk_logic; + signal scom_mode_d1clk : std_ulogic; + signal scom_mode_d2clk : std_ulogic; + signal scom_mode_lclk : clk_logic; + signal func_thold_b : std_ulogic; + signal func_force : std_ulogic; + signal mode_thold_b : std_ulogic; + signal mode_force : std_ulogic; + signal data_ones : std_ulogic_vector(0 to width-1); + signal or_fir : std_ulogic_vector(0 to width-1); + signal and_fir : std_ulogic_vector(0 to width-1); + signal or_mask : std_ulogic_vector(0 to width-1); + signal and_mask : std_ulogic_vector(0 to width-1); + signal fir_mask_in : std_ulogic_vector(0 to width-1); + signal fir_mask_lt : std_ulogic_vector(0 to width-1); + signal masked : std_ulogic_vector(0 to width-1); + signal fir_mask_par_in : std_ulogic; + signal fir_mask_par_lt : std_ulogic; + signal fir_mask_par_err : std_ulogic; + signal fir_action0_in : std_ulogic_vector(0 to width-1); + signal fir_action0_lt : std_ulogic_vector(0 to width-1); + signal fir_action0_par_in : std_ulogic; + signal fir_action0_par_lt : std_ulogic; + signal fir_action0_par_err : std_ulogic; + signal fir_action1_in : std_ulogic_vector(0 to width-1); + signal fir_action1_lt : std_ulogic_vector(0 to width-1); + signal fir_action1_par_in : std_ulogic; + signal fir_action1_par_lt : std_ulogic; + signal fir_action1_par_err : std_ulogic; + signal fir_reset : std_ulogic_vector(0 to width-1); + signal error_input : std_ulogic_vector(0 to width-1); + signal fir_error_in_reef : std_ulogic_vector(0 to width-1); + signal fir_in : std_ulogic_vector(0 to width-1); + signal fir_lt : std_ulogic_vector(0 to width-1); + signal block_fir : std_ulogic; + signal or_fir_load : std_ulogic; + signal and_fir_ones : std_ulogic; + signal and_fir_load : std_ulogic; + signal or_mask_load : std_ulogic; + signal and_mask_ones : std_ulogic; + signal and_mask_load : std_ulogic; + signal sys_xstop_lt : std_ulogic; + signal recov_in : std_ulogic; + signal recov_lt : std_ulogic; + signal xstop_in : std_ulogic; + signal xstop_lt : std_ulogic; + signal trace_error_in : std_ulogic; + signal trace_error_lt : std_ulogic; + signal tieup : std_ulogic; + signal mode_si, mode_so : std_ulogic_vector(0 to 3*(width+1)+width-1); + signal func_si, func_so : std_ulogic_vector(0 to 4); + signal unused_signals : std_ulogic; + + +begin + tieup <= '1'; + data_ones <= (others => '1'); +unused_signals <= or_reduce(recov_reset & sc_addr_v(5)); + + assert (fir_action0_init'length = width) + report "fir_action0_init width error, fir_action0_init must be same width as the component instantiation" + severity error; + + assert (fir_action1_init'length = width) + report "fir_action1_init width error, fir_action1_init must be same width as the component instantiation" + severity error; + + assert (fir_mask_init'length = width) + report "fir_mask_init width error, fir_mask_init must be same width as the component instantiation" + severity error; + + verify_action0: if (fir_action0_init'length /= width) generate + fir_in(0 to 95) <= fir_lt(0 to width); + end generate verify_action0; + + verify_action1: if (fir_action1_init'length /= width) generate + fir_in(0 to 95) <= fir_lt(0 to width); + end generate verify_action1; + + verify_action2: if (fir_mask_init'length /= width) generate + fir_in(0 to 95) <= fir_lt(0 to width); + end generate verify_action2; + + + func_lcbor: entity tri.tri_lcbor + generic map (expand_type => expand_type ) + port map( clkoff_b => lcb_clkoff_dc_b, + thold => lcb_func_slp_sl_thold_0, + sg => lcb_sg_0, + act_dis => lcb_act_dis_dc, + forcee => func_force, + thold_b => func_thold_b + ); + + func_lcb: entity tri.tri_lcbnd + generic map (expand_type => expand_type ) + port map( act => tieup, + vd => vd, + gd => gd, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + nclk => nclk, + forcee => func_force, + sg => lcb_sg_0, + thold_b => func_thold_b, + d1clk => func_d1clk, + d2clk => func_d2clk, + lclk => func_lclk + ); + + + mode_lcbor: entity tri.tri_lcbor + generic map (expand_type => expand_type ) + port map( clkoff_b => lcb_clkoff_dc_b, + thold => lcb_cfg_slp_sl_thold_0, + sg => lcb_sg_0, + act_dis => lcb_act_dis_dc, + forcee => mode_force, + thold_b => mode_thold_b + ); + + mode_lcb: entity tri.tri_lcbnd + generic map (expand_type => expand_type ) + port map( act => tieup, + vd => vd, + gd => gd, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + nclk => nclk, + forcee => mode_force, + sg => lcb_sg_0, + thold_b => mode_thold_b, + d1clk => mode_d1clk, + d2clk => mode_d2clk, + lclk => mode_lclk + ); + + scom_mode_lcb: entity tri.tri_lcbnd + generic map (expand_type => expand_type ) + port map( act => sc_active, + vd => vd, + gd => gd, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + nclk => nclk, + forcee => mode_force, + sg => lcb_sg_0, + thold_b => mode_thold_b, + d1clk => scom_mode_d1clk, + d2clk => scom_mode_d2clk, + lclk => scom_mode_lclk + ); + + fir_action0 : entity tri.tri_nlat_scan + generic map( width => width, init => fir_action0_init, expand_type => expand_type ) + port map + ( vd => vd + , gd => gd + , d1clk => scom_mode_d1clk + , d2clk => scom_mode_d2clk + , lclk => scom_mode_lclk + , scan_in => mode_si(0 to width-1) + , scan_out => mode_so(0 to width-1) + , din => fir_action0_in + , q => fir_action0_lt + ); + + fir_action0_par : entity tri.tri_nlat_scan + generic map( width => 1, init => fir_action0_par_init, expand_type => expand_type ) + port map + ( vd => vd + , gd => gd + , d1clk => scom_mode_d1clk + , d2clk => scom_mode_d2clk + , lclk => scom_mode_lclk + , scan_in => mode_si(width to width) + , scan_out => mode_so(width to width) + , din(0) => fir_action0_par_in + , q(0) => fir_action0_par_lt + ); + + fir_action1 : entity tri.tri_nlat_scan + generic map( width => width, init => fir_action1_init, expand_type => expand_type ) + port map + ( vd => vd + , gd => gd + , d1clk => scom_mode_d1clk + , d2clk => scom_mode_d2clk + , lclk => scom_mode_lclk + , scan_in => mode_si(width+1 to 2*width) + , scan_out => mode_so(width+1 to 2*width) + , din => fir_action1_in + , q => fir_action1_lt + ); + + fir_action1_par : entity tri.tri_nlat_scan + generic map( width => 1, init => fir_action1_par_init, expand_type => expand_type ) + port map + ( vd => vd + , gd => gd + , d1clk => scom_mode_d1clk + , d2clk => scom_mode_d2clk + , lclk => scom_mode_lclk + , scan_in => mode_si(2*width+1 to 2*width+1) + , scan_out => mode_so(2*width+1 to 2*width+1) + , din(0) => fir_action1_par_in + , q(0) => fir_action1_par_lt + ); + + + fir_mask : ENTITY tri.tri_nlat_scan + GENERIC MAP( width => width, init => fir_mask_init, expand_type => expand_type ) + port map + ( vd => vd + , gd => gd + , d1clk => scom_mode_d1clk + , d2clk => scom_mode_d2clk + , lclk => scom_mode_lclk + , scan_in => mode_si(2*width+2 to 3*width+1) + , scan_out => mode_so(2*width+2 to 3*width+1) + , din => fir_mask_in + , q => fir_mask_lt + ); + + fir_mask_par : entity tri.tri_nlat_scan + generic map( width => 1, init => fir_mask_par_init, expand_type => expand_type ) + port map + ( vd => vd + , gd => gd + , d1clk => scom_mode_d1clk + , d2clk => scom_mode_d2clk + , lclk => scom_mode_lclk + , scan_in => mode_si(3*width+2 to 3*width+2) + , scan_out => mode_so(3*width+2 to 3*width+2) + , din(0) => fir_mask_par_in + , q(0) => fir_mask_par_lt + ); + + fir : entity tri.tri_nlat_scan + generic map( width => width, init => fir_init, expand_type => expand_type ) + port map + ( vd => vd + , gd => gd + , d1clk => mode_d1clk + , d2clk => mode_d2clk + , lclk => mode_lclk + , scan_in => mode_si(3*width+3 to 4*width+2) + , scan_out => mode_so(3*width+3 to 4*width+2) + , din => fir_in + , q => fir_lt + ); + + + sys_xstop : entity tri.tri_nlat + generic map( width => 1, init => "0", expand_type => expand_type ) + port map + ( vd => vd + , gd => gd + , d1clk => func_d1clk + , d2clk => func_d2clk + , lclk => func_lclk + , scan_in => func_si(1) + , scan_out => func_so(1) + , din(0) => sys_xstop_in + , q(0) => sys_xstop_lt + ); + + recov : entity tri.tri_nlat + generic map( width => 1, init => "0", expand_type => expand_type ) + port map + ( vd => vd + , gd => gd + , d1clk => func_d1clk + , d2clk => func_d2clk + , lclk => func_lclk + , scan_in => func_si(2) + , scan_out => func_so(2) + , din(0) => recov_in + , q(0) => recov_lt + ); + + xstop : entity tri.tri_nlat + generic map( width => 1, init => "0", expand_type => expand_type ) + port map + ( vd => vd + , gd => gd + , d1clk => func_d1clk + , d2clk => func_d2clk + , lclk => func_lclk + , scan_in => func_si(3) + , scan_out => func_so(3) + , din(0) => xstop_in + , q(0) => xstop_lt + ); + + trace_err : entity tri.tri_nlat + generic map( width => 1, init => "0", expand_type => expand_type ) + port map + ( vd => vd + , gd => gd + , d1clk => func_d1clk + , d2clk => func_d2clk + , lclk => func_lclk + , scan_in => func_si(4) + , scan_out => func_so(4) + , din(0) => trace_error_in + , q(0) => trace_error_lt + ); + + + use_recov_reset_yes: if (use_recov_reset = true) generate + fir_reset <= NOT gate_AND(recov_reset, NOT fir_action0_lt AND fir_action1_lt); + end generate use_recov_reset_yes; + + use_recov_reset_no: if (use_recov_reset = false) generate + fir_reset <= (others => '1') ; + end generate use_recov_reset_no; + + + or_fir_load <= (sc_addr_v(0) or sc_addr_v(2)) and sc_wr_q; + and_fir_ones <= not((sc_addr_v(0) or sc_addr_v(1)) and sc_wr_q); + and_fir_load <= sc_addr_v(1) and sc_wr_q; + + or_fir <= gate_and( or_fir_load, sc_wdata); + + and_fir <= gate_and(and_fir_load, sc_wdata) or + gate_and(and_fir_ones, data_ones ); + + fir_in <= gate_and(not block_fir, error_input) or or_fir or (fir_lt and and_fir and fir_reset); + + + fir_error_in_reef <= error_in; + error_input <= fir_error_in_reef; + + + or_mask_load <= (sc_addr_v(6) or sc_addr_v(8)) and sc_wr_q; + and_mask_ones <= not((sc_addr_v(6) or sc_addr_v(7)) and sc_wr_q); + and_mask_load <= sc_addr_v(7) and sc_wr_q; + + or_mask <= gate_and( or_mask_load, sc_wdata); + and_mask <= gate_and(and_mask_load, sc_wdata) or gate_and(and_mask_ones, data_ones); + + fir_mask_in <= or_mask or (fir_mask_lt and and_mask); + fir_mask_par_in <= parity_gen_even(fir_mask_in) when (gate_and(sc_wr_q, or_reduce(sc_addr_v(6 to 8))))='1' else + fir_mask_par_lt; + + fir_mask_par_err <= (xor_reduce(fir_mask_lt) xor fir_mask_par_lt) or + (sc_wr_q and or_reduce(sc_addr_v(6 to 8)) and sc_parity_error_inject); + + masked <= fir_mask_lt; + + + fir_action0_in <= sc_wdata when (sc_addr_v(3) and sc_wr_q) = '1' else fir_action0_lt; + fir_action0_par_in <= sc_wparity when (sc_addr_v(3) and sc_wr_q) = '1' else fir_action0_par_lt; + fir_action0_par_err <= xor_reduce(fir_action0_lt) xor fir_action0_par_lt; + + fir_action1_in <= sc_wdata when (sc_addr_v(4) and sc_wr_q) = '1' else fir_action1_lt; + fir_action1_par_in <= sc_wparity when (sc_addr_v(4) and sc_wr_q) = '1' else fir_action1_par_lt; + fir_action1_par_err <= xor_reduce(fir_action1_lt) xor fir_action1_par_lt; + + + xstop_in <= or_reduce(fir_lt and fir_action0_lt and not fir_action1_lt and not masked); + recov_in <= or_reduce(fir_lt and not fir_action0_lt and fir_action1_lt and not masked); + + block_fir <= xstop_lt or sys_xstop_lt; + + xstop_err <= xstop_lt; + recov_err <= recov_lt; + trace_error <= trace_error_lt; + + fir_out <= fir_lt; + act0_out <= fir_action0_lt; + act1_out <= fir_action1_lt; + mask_out <= fir_mask_lt; + + fir_parity_check <= fir_action0_par_err & fir_action1_par_err & fir_mask_par_err; + + + + sc_rdata <= gate_and(sc_addr_v(0), fir_lt ) or + gate_and(sc_addr_v(3), fir_action0_lt) or + gate_and(sc_addr_v(4), fir_action1_lt) or + gate_and(sc_addr_v(6), fir_mask_lt ) ; + + + mchkgen: if (impl_lxstop_mchk = true) generate + yes: block + signal lxstop_mchk_in : std_ulogic; + signal lxstop_mchk_lt : std_ulogic; + begin + + lxstop_mchk_in <= or_reduce(fir_lt and fir_action0_lt and fir_action1_lt and not masked); + lxstop_mchk <= lxstop_mchk_lt; + + trace_error_in <= xstop_in or recov_in or lxstop_mchk_in; + + mchk : entity tri.tri_nlat + generic map( width => 1, init => "0", expand_type => expand_type ) + port map + ( d1clk => func_d1clk + , vd => vd + , gd => gd + , lclk => func_lclk + , d2clk => func_d2clk + , scan_in => func_si(0) + , scan_out => func_so(0) + , din(0) => lxstop_mchk_in + , q(0) => lxstop_mchk_lt + ); + end block yes; + end generate mchkgen; + + nomchk: if (impl_lxstop_mchk = false) generate + trace_error_in <= xstop_in or recov_in; + lxstop_mchk <= '0'; + func_so(0) <= func_si(0); + end generate nomchk; + + + mode_si <= mode_scan_siv; + mode_scan_sov <= mode_so; + + func_si <= func_scan_siv; + func_scan_sov <= func_so; + + +end pcq_local_fir2; + + + + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/pcq_psro_soft.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/pcq_psro_soft.vhdl new file mode 100644 index 0000000..88f9e18 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/pcq_psro_soft.vhdl @@ -0,0 +1,57 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee; +use ieee.std_logic_1164.all ; +library support; +use support.power_logic_pkg.all; +library tri; + + +entity pcq_psro_soft is + port ( + vdd : inout power_logic; + gnd : inout power_logic; + pcq_psro_enable : in std_ulogic_vector(0 to 2); + psro_pcq_ringsig : out std_ulogic + ); + +end pcq_psro_soft; + + +architecture pcq_psro_soft of pcq_psro_soft is +begin + + pcq_init: entity tri.tri_psro_soft + port map + ( vdd => vdd , + gnd => gnd , + psro_enable => pcq_psro_enable(0 to 2) , + psro_ringsig => psro_pcq_ringsig ); + +end pcq_psro_soft; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/pcq_regs.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/pcq_regs.vhdl new file mode 100644 index 0000000..41869d4 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/pcq_regs.vhdl @@ -0,0 +1,1822 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee; +use ieee.std_logic_1164.all; +library ibm,clib; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; +library support; +use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity pcq_regs is +generic(expand_type : integer := 2; + regmode : integer := 6 +); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + scan_dis_dc_b : in std_ulogic; + lcb_clkoff_dc_b : in std_ulogic; + lcb_d_mode_dc : in std_ulogic; + lcb_mpw1_dc_b : in std_ulogic; + lcb_mpw2_dc_b : in std_ulogic; + lcb_delay_lclkr_dc : in std_ulogic; + lcb_act_dis_dc : in std_ulogic; + lcb_func_slp_sl_thold_0 : in std_ulogic; + lcb_cfg_sl_thold_0 : in std_ulogic; + lcb_cfg_slp_sl_thold_0 : in std_ulogic; + lcb_sg_0 : in std_ulogic; + ccfg_scan_in : in std_ulogic; + bcfg_scan_in : in std_ulogic; + dcfg_scan_in : in std_ulogic; + func_scan_in : in std_ulogic; + ccfg_scan_out : out std_ulogic; + bcfg_scan_out : out std_ulogic; + dcfg_scan_out : out std_ulogic; + func_scan_out : out std_ulogic; + an_ac_scom_sat_id : in std_ulogic_vector(0 to 3); + an_ac_scom_dch : in std_ulogic; + an_ac_scom_cch : in std_ulogic; + ac_an_scom_dch : out std_ulogic; + ac_an_scom_cch : out std_ulogic; + ac_an_special_attn : out std_ulogic_vector(0 to 3); + ac_an_checkstop : out std_ulogic_vector(0 to 2); + ac_an_local_checkstop : out std_ulogic_vector(0 to 2); + ac_an_recov_err : out std_ulogic_vector(0 to 2); + ac_an_trace_error : out std_ulogic; + an_ac_checkstop : in std_ulogic; + an_ac_malf_alert : in std_ulogic; + rg_ck_fast_xstop : out std_ulogic; + iu_pc_err_icache_parity : in std_ulogic; + iu_pc_err_icachedir_parity : in std_ulogic; + iu_pc_err_icachedir_multihit : in std_ulogic; + iu_pc_err_ucode_illegal : in std_ulogic_vector(0 to 3); + xu_pc_err_dcache_parity : in std_ulogic; + xu_pc_err_dcachedir_parity : in std_ulogic; + xu_pc_err_dcachedir_multihit : in std_ulogic; + xu_pc_err_mcsr_summary : in std_ulogic_vector(0 to 3); + xu_pc_err_ierat_parity : in std_ulogic; + xu_pc_err_derat_parity : in std_ulogic; + xu_pc_err_tlb_parity : in std_ulogic; + xu_pc_err_tlb_lru_parity : in std_ulogic; + xu_pc_err_ierat_multihit : in std_ulogic; + xu_pc_err_derat_multihit : in std_ulogic; + xu_pc_err_tlb_multihit : in std_ulogic; + xu_pc_err_ext_mchk : in std_ulogic; + xu_pc_err_ditc_overrun : in std_ulogic; + xu_pc_err_local_snoop_reject : in std_ulogic; + xu_pc_err_sprg_ecc : in std_ulogic_vector(0 to 3); + xu_pc_err_sprg_ue : in std_ulogic_vector(0 to 3); + xu_pc_err_regfile_parity : in std_ulogic_vector(0 to 3); + xu_pc_err_regfile_ue : in std_ulogic_vector(0 to 3); + xu_pc_err_llbust_attempt : in std_ulogic_vector(0 to 3); + xu_pc_err_llbust_failed : in std_ulogic_vector(0 to 3); + xu_pc_err_l2intrf_ecc : in std_ulogic; + xu_pc_err_l2intrf_ue : in std_ulogic; + xu_pc_err_l2credit_overrun : in std_ulogic; + xu_pc_err_wdt_reset : in std_ulogic_vector(0 to 3); + xu_pc_err_attention_instr : in std_ulogic_vector(0 to 3); + xu_pc_err_debug_event : in std_ulogic_vector(0 to 3); + xu_pc_err_nia_miscmpr : in std_ulogic_vector(0 to 3); + xu_pc_err_invld_reld : in std_ulogic; + xu_pc_err_mchk_disabled : in std_ulogic; + bx_pc_err_inbox_ecc : in std_ulogic; + bx_pc_err_inbox_ue : in std_ulogic; + bx_pc_err_outbox_ecc : in std_ulogic; + bx_pc_err_outbox_ue : in std_ulogic; + fu_pc_err_regfile_parity : in std_ulogic_vector(0 to 3); + fu_pc_err_regfile_ue : in std_ulogic_vector(0 to 3); + pc_iu_inj_icache_parity : out std_ulogic; + pc_iu_inj_icachedir_parity : out std_ulogic; + pc_xu_inj_dcache_parity : out std_ulogic; + pc_xu_inj_dcachedir_parity : out std_ulogic; + pc_xu_inj_sprg_ecc : out std_ulogic_vector(0 to 3); + pc_xu_inj_regfile_parity : out std_ulogic_vector(0 to 3); + pc_fu_inj_regfile_parity : out std_ulogic_vector(0 to 3); + pc_bx_inj_inbox_ecc : out std_ulogic; + pc_bx_inj_outbox_ecc : out std_ulogic; + pc_xu_inj_llbust_attempt : out std_ulogic_vector(0 to 3); + pc_xu_inj_llbust_failed : out std_ulogic_vector(0 to 3); + pc_xu_inj_wdt_reset : out std_ulogic_vector(0 to 3); + pc_iu_inj_icachedir_multihit : out std_ulogic; + pc_xu_inj_dcachedir_multihit : out std_ulogic; + pc_xu_cache_par_err_event : out std_ulogic; + pc_iu_ram_instr : out std_ulogic_vector(0 to 31); + pc_iu_ram_instr_ext : out std_ulogic_vector(0 to 3); + pc_iu_ram_mode : out std_ulogic; + pc_iu_ram_thread : out std_ulogic_vector(0 to 1); + pc_xu_ram_execute : out std_ulogic; + pc_xu_ram_mode : out std_ulogic; + pc_xu_ram_thread : out std_ulogic_vector(0 to 1); + xu_pc_ram_interrupt : in std_ulogic; + xu_pc_ram_done : in std_ulogic; + xu_pc_ram_data : in std_ulogic_vector(64-(2**regmode) to 63); + pc_fu_ram_mode : out std_ulogic; + pc_fu_ram_thread : out std_ulogic_vector(0 to 1); + fu_pc_ram_done : in std_ulogic; + fu_pc_ram_data : in std_ulogic_vector(0 to 63); + pc_xu_msrovride_enab : out std_ulogic; + pc_xu_msrovride_pr : out std_ulogic; + pc_xu_msrovride_gs : out std_ulogic; + pc_xu_msrovride_de : out std_ulogic; + pc_iu_ram_force_cmplt : out std_ulogic; + pc_xu_ram_flush_thread : out std_ulogic; + pc_xu_stop : out std_ulogic_vector(0 to 3); + pc_xu_step : out std_ulogic_vector(0 to 3); + pc_xu_force_ude : out std_ulogic_vector(0 to 3); + pc_xu_dbg_action : out std_ulogic_vector(0 to 11); + xu_pc_running : in std_ulogic_vector(0 to 3); + xu_pc_stop_dbg_event : in std_ulogic_vector(0 to 3); + xu_pc_step_done : in std_ulogic_vector(0 to 3); + ct_rg_power_managed : in std_ulogic_vector(0 to 3); + ct_rg_pm_thread_stop : in std_ulogic_vector(0 to 3); + ac_an_pm_thread_running : out std_ulogic_vector(0 to 3); + an_ac_debug_stop : in std_ulogic; + pc_xu_extirpts_dis_on_stop : out std_ulogic; + pc_xu_timebase_dis_on_stop : out std_ulogic; + pc_xu_decrem_dis_on_stop : out std_ulogic; + ct_rg_hold_during_init : in std_ulogic; + rg_ct_dis_pwr_savings : out std_ulogic; + sp_rg_trace_bus_enable : in std_ulogic; + rg_db_trace_bus_enable : out std_ulogic; + pc_fu_trace_bus_enable : out std_ulogic; + pc_bx_trace_bus_enable : out std_ulogic; + pc_iu_trace_bus_enable : out std_ulogic; + pc_mm_trace_bus_enable : out std_ulogic; + pc_xu_trace_bus_enable : out std_ulogic; + rg_db_debug_mux_ctrls : out std_ulogic_vector(0 to 15); + pc_fu_debug_mux1_ctrls : out std_ulogic_vector(0 to 15); + pc_bx_debug_mux1_ctrls : out std_ulogic_vector(0 to 15); + pc_iu_debug_mux1_ctrls : out std_ulogic_vector(0 to 15); + pc_iu_debug_mux2_ctrls : out std_ulogic_vector(0 to 15); + pc_mm_debug_mux1_ctrls : out std_ulogic_vector(0 to 15); + pc_xu_debug_mux1_ctrls : out std_ulogic_vector(0 to 15); + pc_xu_debug_mux2_ctrls : out std_ulogic_vector(0 to 15); + pc_xu_debug_mux3_ctrls : out std_ulogic_vector(0 to 15); + pc_xu_debug_mux4_ctrls : out std_ulogic_vector(0 to 15); + dbg_scom_rdata : out std_ulogic_vector(0 to 63); + dbg_scom_wdata : out std_ulogic_vector(0 to 63); + dbg_scom_decaddr : out std_ulogic_vector(0 to 63); + dbg_scom_misc : out std_ulogic_vector(0 to 8); + dbg_ram_thrctl : out std_ulogic_vector(0 to 20); + dbg_fir0_err : out std_ulogic_vector(0 to 31); + dbg_fir1_err : out std_ulogic_vector(0 to 30); + dbg_fir2_err : out std_ulogic_vector(0 to 21); + dbg_fir_misc : out std_ulogic_vector(0 to 35) +); + +-- synopsys translate_off + + +-- synopsys translate_on +end pcq_regs; + +architecture pcq_regs of pcq_regs is + +constant rami_size : positive := 32; +constant ramc_size : positive := 20; +constant ramd_size : positive := 64; +constant thrctl1_size : positive := 16; +constant thrctl2_size : positive := 12; +constant pccr0_size : positive := 24; +constant recerrcntr_size : positive := 4; +constant spattn_size : positive := 4; +constant abdsr_size : positive := 32; +constant idsr_size : positive := 32; +constant mpdsr_size : positive := 32; +constant xdsr1_size : positive := 32; +constant xdsr2_size : positive := 32; +constant errinj_size : positive := 19; +constant parity_size : positive := 1; +constant scom_misc_size : positive := 6; +constant dcfg_stage1_size : positive := 5; +constant bcfg_stage1_size : positive := 13; +constant bcfg_stage2_size : positive := 15; +constant func_stage1_size : positive := 2; +constant func_stage2_size : positive := 32; +constant func_stage3_size : positive := 11; +constant fu_ram_din_size : positive := 64; +constant xu_ram_din_size : positive := 2**regmode+1; +constant abdsr_offset : natural := 0; +constant abdsr_par_offset : natural := abdsr_offset + abdsr_size; +constant idsr_offset : natural := abdsr_par_offset + parity_size; +constant idsr_par_offset : natural := idsr_offset + idsr_size; +constant mpdsr_offset : natural := idsr_par_offset + parity_size; +constant mpdsr_par_offset : natural := mpdsr_offset + mpdsr_size; +constant xdsr1_offset : natural := mpdsr_par_offset + parity_size; +constant xdsr1_par_offset : natural := xdsr1_offset + xdsr1_size; +constant xdsr2_offset : natural := xdsr1_par_offset + parity_size; +constant xdsr2_par_offset : natural := xdsr2_offset + xdsr2_size; +constant pccr0_offset : natural := xdsr2_par_offset + parity_size; +constant recerrcntr_offset : natural := pccr0_offset + pccr0_size; +constant pccr0_par_offset : natural := recerrcntr_offset + recerrcntr_size; +constant dcfg_stage1_offset : natural := pccr0_par_offset + parity_size; +constant dcfg_right : natural := dcfg_stage1_offset + dcfg_stage1_size - 1; +constant scommode_offset : natural := 0; +constant thrctl1_offset : natural := scommode_offset + 2; +constant thrctl2_offset : natural := thrctl1_offset + thrctl1_size; +constant spattn1_offset : natural := thrctl2_offset + thrctl2_size; +constant spattn2_offset : natural := spattn1_offset + spattn_size; +constant spattn_par_offset : natural := spattn2_offset + spattn_size; +constant bcfg_stage1_offset : natural := spattn_par_offset + parity_size; +constant bcfg_stage2_offset : natural := bcfg_stage1_offset + bcfg_stage1_size; +constant bcfg_right : natural := bcfg_stage2_offset + bcfg_stage2_size - 1; +constant rami_offset : natural := 0; +constant ramc_offset : natural := rami_offset + rami_size; +constant ramd_offset : natural := ramc_offset + ramc_size; +constant fu_ram_din_offset : natural := ramd_offset + ramd_size; +constant xu_ram_din_offset : natural := fu_ram_din_offset + fu_ram_din_size; +constant errinj_offset : natural := xu_ram_din_offset + xu_ram_din_size; +constant sc_misc_offset : natural := errinj_offset + errinj_size; +constant scaddr_dec_offset : natural := sc_misc_offset + scom_misc_size; +constant func_stage1_offset : natural := scaddr_dec_offset + 64; +constant func_stage2_offset : natural := func_stage1_offset + func_stage1_size; +constant func_stage3_offset : natural := func_stage2_offset + func_stage2_size; +constant scomfunc_offset : natural := func_stage3_offset + func_stage3_size; +constant func_right : natural := scomfunc_offset + 177 - 1; + +constant scom_width : positive := 64; +constant use_addr : std_ulogic_vector := "1111111111111110111111111011100000000000111111111111111110011111"; +constant addr_is_rdable : std_ulogic_vector := "1001111001100110100110011010000000000000111001111001001000011111"; +constant addr_is_wrable : std_ulogic_vector := "1111101111111110111011111011100000000000111111111111111110011111"; + +signal tidn, tiup : std_ulogic; +signal tidn_32 : std_ulogic_vector(0 to 31); +signal bcfg_siv, bcfg_sov : std_ulogic_vector(0 to bcfg_right); +signal dcfg_siv, dcfg_sov : std_ulogic_vector(0 to dcfg_right); +signal func_siv, func_sov : std_ulogic_vector(0 to func_right); +signal lcb_func_slp_sl_thold_0_b : std_ulogic; +signal lcb_cfg_slp_sl_thold_0_b : std_ulogic; +signal force_cfgslp : std_ulogic; +signal force_funcslp : std_ulogic; +signal cfgslp_d1clk : std_ulogic; +signal cfgslp_d2clk : std_ulogic; +signal cfgslp_lclk : clk_logic; +signal cfg_slat_force : std_ulogic; +signal cfg_slat_d2clk : std_ulogic; +signal cfg_slat_lclk : clk_logic; +signal cfg_slat_thold_b : std_ulogic; +signal scom_cch_q, scom_dch_q : std_ulogic; +signal scom_act, scom_local_act : std_ulogic; +signal sc_r_nw : std_ulogic; +signal sc_ack : std_ulogic; +signal sc_rdata, sc_wdata : std_ulogic_vector(0 to 63); +signal sc_ack_info : std_ulogic_vector(0 to 1); +signal sc_wparity_out : std_ulogic; +signal sc_wparity : std_ulogic; +signal scom_fsm_err : std_ulogic; +signal scom_ack_err : std_ulogic; +signal scaddr_predecode : std_ulogic_vector(0 to 5); +signal scaddr_dec_d : std_ulogic_vector(0 to 63); +signal scaddr_v : std_ulogic_vector(0 to 63); +signal andmask_ones : std_ulogic_vector(0 to 63); +signal sc_req_d, sc_req_q : std_ulogic; +signal sc_wr_d, sc_wr_q : std_ulogic; +signal scaddr_v_d, scaddr_v_q : std_ulogic_vector(0 to 63); +signal scaddr_nvld_d, scaddr_nvld_q : std_ulogic; +signal sc_wr_nvld_d, sc_wr_nvld_q : std_ulogic; +signal sc_rd_nvld_d, sc_rd_nvld_q : std_ulogic; +signal ramc_instr_in : std_ulogic_vector(0 to 3); +signal ramc_mode_in : std_ulogic_vector(0 to 2); +signal ramc_force_cmplt_in : std_ulogic; +signal ramc_force_flush_in : std_ulogic; +signal ramc_msr_de_ovrid_in : std_ulogic; +signal ramc_spare_in : std_ulogic_vector(0 to 2); +signal ramc_msr_ovrid_in : std_ulogic_vector(0 to 2); +signal ramc_execute_in : std_ulogic; +signal ramc_status_in : std_ulogic_vector(0 to 2); +signal or_ramc_load : std_ulogic; +signal and_ramc_ones : std_ulogic; +signal and_ramc_load : std_ulogic; +signal or_ramc : std_ulogic_vector(0 to 63); +signal and_ramc : std_ulogic_vector(0 to 63); +signal rami_d, rami_q : std_ulogic_vector(0 to rami_size-1); +signal rami_out : std_ulogic_vector(0 to 63); +signal ramc_d, ramc_q : std_ulogic_vector(0 to ramc_size-1); +signal ramc_out : std_ulogic_vector(0 to 63); +signal ramic_out : std_ulogic_vector(0 to 63); +signal ramd_d, ramd_q : std_ulogic_vector(0 to ramd_size-1); +signal ramdh_out, ramdl_out : std_ulogic_vector(0 to 63); +signal rg_rg_ram_mode : std_ulogic; +signal ramd_xu_load_zeros : std_ulogic_vector(0 to 64-(2**regmode)); +signal xu_ramd_load_data_d : std_ulogic_vector(0 to 64); +signal xu_ramd_load_data_q : std_ulogic_vector(0 to 64); +signal xu_ramd_load_data : std_ulogic_vector(0 to 63); +signal fu_ramd_load_data_d : std_ulogic_vector(0 to 63); +signal fu_ramd_load_data_q : std_ulogic_vector(0 to 63); +signal xu_ram_done_q : std_ulogic; +signal fu_ram_done_q : std_ulogic; +signal ram_mode_d, ram_mode_q : std_ulogic; +signal ram_execute_d, ram_execute_q : std_ulogic; +signal ram_thread_d, ram_thread_q : std_ulogic_vector(0 to 1); +signal ram_msrovren_d, ram_msrovren_q : std_ulogic; +signal ram_msrovrpr_d, ram_msrovrpr_q : std_ulogic; +signal ram_msrovrgs_d, ram_msrovrgs_q : std_ulogic; +signal ram_msrovrde_d, ram_msrovrde_q : std_ulogic; +signal ram_force_d, ram_force_q : std_ulogic; +signal ram_flush_d, ram_flush_q : std_ulogic; +signal or_thrctl_load : std_ulogic; +signal and_thrctl_ones : std_ulogic; +signal and_thrctl_load : std_ulogic; +signal or_thrctl : std_ulogic_vector(0 to 63); +signal and_thrctl : std_ulogic_vector(0 to 63); +signal thrctl_out : std_ulogic_vector(0 to 63); +signal thrctl1_d, thrctl1_q : std_ulogic_vector(0 to thrctl1_size-1); +signal thrctl2_d, thrctl2_q : std_ulogic_vector(0 to thrctl2_size-1); +signal thrctl_stop_in : std_ulogic_vector(0 to 3); +signal thrctl_step_in : std_ulogic_vector(0 to 3); +signal thrctl_run_in : std_ulogic_vector(0 to 3); +signal thrctl_pm_in : std_ulogic_vector(0 to 3); +signal thrctl_misc_dbg_in : std_ulogic_vector(0 to 6); +signal thrctl_spare_in : std_ulogic_vector(0 to 4); +signal tx_stop_d, tx_stop_q : std_ulogic_vector(0 to 3); +signal tx_step_d, tx_step_q : std_ulogic_vector(0 to 3); +signal tx_ude_d, tx_ude_q : std_ulogic_vector(0 to 3); +signal ude_dly_d, ude_dly_q : std_ulogic_vector(0 to 3); +signal force_ude_pulse : std_ulogic_vector(0 to 3); +signal extirpts_dis_d, extirpts_dis_q : std_ulogic; +signal timebase_dis_d, timebase_dis_q : std_ulogic; +signal decrem_dis_d, decrem_dis_q : std_ulogic; +signal ext_debug_stop_q : std_ulogic; +signal external_debug_stop : std_ulogic_vector(0 to 3); +signal stop_dbg_event_q : std_ulogic_vector(0 to 3); +signal step_done_q : std_ulogic_vector(0 to 3); +signal or_pccr0_load : std_ulogic; +signal and_pccr0_ones : std_ulogic; +signal and_pccr0_load : std_ulogic; +signal or_pccr0 : std_ulogic_vector(0 to 63); +signal and_pccr0 : std_ulogic_vector(0 to 63); +signal pccr0_out : std_ulogic_vector(0 to 63); +signal pccr0_par_err : std_ulogic; +signal pccr0_par_in : std_ulogic_vector(0 to pccr0_size+4-1); +signal pccr0_d, pccr0_q : std_ulogic_vector(0 to pccr0_size-1); +signal pccr0_par_d, pccr0_par_q : std_ulogic_vector(0 to 0); +signal debug_mode_d, debug_mode_q : std_ulogic; +signal debug_mode_act : std_ulogic; +signal trace_bus_enable_d : std_ulogic; +signal trace_bus_enable_q : std_ulogic; +signal ram_enab_d, ram_enab_q : std_ulogic; +signal ram_enab_act : std_ulogic; +signal ram_enab_scom_act : std_ulogic; +signal errinj_enab_d, errinj_enab_q : std_ulogic; +signal errinj_enab_act : std_ulogic; +signal errinj_enab_scom_act : std_ulogic; +signal rg_rg_xstop_report_ovride : std_ulogic; +signal rg_rg_fast_xstop_enable : std_ulogic; +signal rg_rg_maxRecErrCntrValue : std_ulogic; +signal rg_rg_gateRecErrCntr : std_ulogic; +signal recErrCntr_pargen : std_ulogic; +signal incr_recErrCntr : std_ulogic_vector(0 to 3); +signal recErrCntr_in : std_ulogic_vector(0 to 3); +signal recErrCntr_q : std_ulogic_vector(0 to 3); +signal pccr0_pervModes_in : std_ulogic_vector(0 to 6); +signal pccr0_spare_in : std_ulogic_vector(0 to 4); +signal pccr0_dbgActSel_in : std_ulogic_vector(0 to 11); +signal or_spattn_load : std_ulogic; +signal and_spattn_ones : std_ulogic; +signal and_spattn_load : std_ulogic; +signal or_spattn : std_ulogic_vector(0 to 63); +signal and_spattn : std_ulogic_vector(0 to 63); +signal spattn_out : std_ulogic_vector(0 to 63); +signal spattn_par_err : std_ulogic; +signal spattn_par_d, spattn_par_q : std_ulogic_vector(0 to 0); +signal spattn_data_d, spattn_data_q : std_ulogic_vector(0 to spattn_size-1); +signal spattn_mask_d, spattn_mask_q : std_ulogic_vector(0 to spattn_size-1); +signal spattn_unused : std_ulogic_vector(spattn_size to 15); +signal spattn_attn_instr_in : std_ulogic_vector(0 to 3); +signal spattn_out_masked : std_ulogic_vector(0 to spattn_size-1); +signal abdsr_data_in : std_ulogic_vector(0 to abdsr_size-1); +signal abdsr_out : std_ulogic_vector(0 to 63); +signal abdsr_par_err : std_ulogic; +signal abdsr_d, abdsr_q : std_ulogic_vector(0 to abdsr_size-1); +signal abdsr_par_d, abdsr_par_q : std_ulogic_vector(0 to 0); +signal idsr_data_in : std_ulogic_vector(0 to idsr_size-1); +signal idsr_out : std_ulogic_vector(0 to 63); +signal idsr_par_err : std_ulogic; +signal idsr_d, idsr_q : std_ulogic_vector(0 to idsr_size-1); +signal idsr_par_d, idsr_par_q : std_ulogic_vector(0 to 0); +signal mpdsr_data_in : std_ulogic_vector(0 to mpdsr_size-1); +signal mpdsr_out : std_ulogic_vector(0 to 63); +signal mpdsr_par_err : std_ulogic; +signal mpdsr_d, mpdsr_q : std_ulogic_vector(0 to mpdsr_size-1); +signal mpdsr_par_d, mpdsr_par_q : std_ulogic_vector(0 to 0); +signal xdsr1_data_in : std_ulogic_vector(0 to xdsr1_size-1); +signal xdsr1_out : std_ulogic_vector(0 to 63); +signal xdsr1_par_err_d : std_ulogic; +signal xdsr1_par_err_q : std_ulogic; +signal xdsr1_d, xdsr1_q : std_ulogic_vector(0 to xdsr1_size-1); +signal xdsr1_par_d, xdsr1_par_q : std_ulogic_vector(0 to 0); +signal xdsr2_data_in : std_ulogic_vector(0 to xdsr2_size-1); +signal xdsr2_out : std_ulogic_vector(0 to 63); +signal xdsr2_par_err : std_ulogic; +signal xdsr2_d, xdsr2_q : std_ulogic_vector(0 to xdsr2_size-1); +signal xdsr2_par_d, xdsr2_par_q : std_ulogic_vector(0 to 0); +signal errinj_out : std_ulogic_vector(0 to 63); +signal errinj_thread_in : std_ulogic_vector(0 to 3); +signal errinj_errtype_in : std_ulogic_vector(0 to 14); +signal errinj_d, errinj_q : std_ulogic_vector(0 to errinj_size-1); +signal attn_instr_int : std_ulogic_vector(0 to 3); +signal rg_rg_ram_mode_xstop : std_ulogic; +signal rg_rg_xstop_err : std_ulogic_vector(0 to 3); +signal rg_rg_any_fir_xstop : std_ulogic; +signal scom_reg_par_checks : std_ulogic_vector(0 to 6); +signal scaddr_fir : std_ulogic; +signal fir_func_si, fir_func_so : std_ulogic; +signal fir_mode_si, fir_mode_so : std_ulogic; +signal fir_data_out : std_ulogic_vector(0 to 63); +signal rg_rg_errinj_shutoff : std_ulogic_vector(0 to 14); +signal sc_parity_error_inject : std_ulogic; +signal inj_icache_parity_d : std_ulogic; +signal inj_icache_parity_q : std_ulogic; +signal inj_icachedir_parity_d : std_ulogic; +signal inj_icachedir_parity_q : std_ulogic; +signal inj_dcache_parity_d : std_ulogic; +signal inj_dcache_parity_q : std_ulogic; +signal inj_dcachedir_parity_d : std_ulogic; +signal inj_dcachedir_parity_q : std_ulogic; +signal inj_xuregfile_parity_d : std_ulogic_vector(0 to 3); +signal inj_xuregfile_parity_q : std_ulogic_vector(0 to 3); +signal inj_furegfile_parity_d : std_ulogic_vector(0 to 3); +signal inj_furegfile_parity_q : std_ulogic_vector(0 to 3); +signal inj_icachedir_multihit_d : std_ulogic; +signal inj_icachedir_multihit_q : std_ulogic; +signal inj_dcachedir_multihit_d : std_ulogic; +signal inj_dcachedir_multihit_q : std_ulogic; +signal inj_sprg_ecc_d : std_ulogic_vector(0 to 3); +signal inj_sprg_ecc_q : std_ulogic_vector(0 to 3); +signal inj_inbox_ecc_d : std_ulogic; +signal inj_inbox_ecc_q : std_ulogic; +signal inj_outbox_ecc_d : std_ulogic; +signal inj_outbox_ecc_q : std_ulogic; +signal inj_llbust_attempt_d : std_ulogic_vector(0 to 3); +signal inj_llbust_attempt_q : std_ulogic_vector(0 to 3); +signal inj_llbust_failed_d : std_ulogic_vector(0 to 3); +signal inj_llbust_failed_q : std_ulogic_vector(0 to 3); +signal inj_wdt_reset_d : std_ulogic_vector(0 to 3); +signal inj_wdt_reset_q : std_ulogic_vector(0 to 3); +signal unused_signals : std_ulogic; + + + + +begin + + + tidn <= '0'; + tidn_32 <= (others => '0'); + tiup <= '1'; + +unused_signals <= or_reduce(or_ramc(0 to 31) & or_ramc(36 to 43) & or_ramc(56 to 60) & + and_ramc(0 to 31) & and_ramc(36 to 43) & and_ramc(47) & + and_ramc(52) & and_ramc(56 to 60) & + or_thrctl(0 to 31) & or_thrctl(40 to 47) & or_thrctl(60 to 63) & + and_thrctl(0 to 31) & and_thrctl(40 to 47) & and_thrctl(60 to 63) & + or_pccr0(0 to 31) & or_pccr0(44 to 51) & + and_pccr0(0 to 31) & and_pccr0(44 to 51) & + or_spattn(0 to 31) & or_spattn(36 to 47) & or_spattn(52 to 63) & + and_spattn(0 to 31) & and_spattn(36 to 47) & and_spattn(52 to 63) & + xu_ramd_load_data_q(0)); + + + + scomsat: entity tri.tri_serial_scom2 + generic map(width => scom_width, + internal_addr_decode => false, + pipeline_paritychk => false, + expand_type => expand_type ) + port map( + nclk => nclk + , vd => vdd + , gd => gnd + , scom_func_thold => lcb_func_slp_sl_thold_0 + , sg => lcb_sg_0 + , act_dis_dc => lcb_act_dis_dc + , clkoff_dc_b => lcb_clkoff_dc_b + , mpw1_dc_b => lcb_mpw1_dc_b + , mpw2_dc_b => lcb_mpw2_dc_b + , d_mode_dc => lcb_d_mode_dc + , delay_lclkr_dc => lcb_delay_lclkr_dc + , func_scan_in => func_siv(scomfunc_offset to scomfunc_offset + scom_width+2*((scom_width-1)/16+1)+104) + , func_scan_out => func_sov(scomfunc_offset to scomfunc_offset + scom_width+2*((scom_width-1)/16+1)+104) + , dcfg_scan_dclk => cfg_slat_d2clk + , dcfg_scan_lclk => cfg_slat_lclk + , dcfg_d1clk => cfgslp_d1clk + , dcfg_d2clk => cfgslp_d2clk + , dcfg_lclk => cfgslp_lclk + , dcfg_scan_in => bcfg_siv(scommode_offset to scommode_offset + 1) + , dcfg_scan_out => bcfg_sov(scommode_offset to scommode_offset + 1) + , scom_local_act => scom_local_act + , sat_id => an_ac_scom_sat_id + , scom_dch_in => scom_dch_q + , scom_cch_in => scom_cch_q + , scom_dch_out => ac_an_scom_dch + , scom_cch_out => ac_an_scom_cch + , sc_req => sc_req_d + , sc_ack => sc_ack + , sc_ack_info => sc_ack_info + , sc_r_nw => sc_r_nw + , sc_addr => scaddr_predecode + , sc_rdata => sc_rdata + , sc_wdata => sc_wdata + , sc_wparity => sc_wparity_out + , scom_err => scom_fsm_err + , fsm_reset => tidn + ); + + + scaddr: entity clib.c_scom_addr_decode + generic map( use_addr => use_addr + , addr_is_rdable => addr_is_rdable + , addr_is_wrable => addr_is_wrable + ) + port map( sc_addr => scaddr_predecode + , scaddr_dec => scaddr_dec_d + , sc_req => sc_req_d + , sc_r_nw => sc_r_nw + , scaddr_nvld => scaddr_nvld_d + , sc_wr_nvld => sc_wr_nvld_d + , sc_rd_nvld => sc_rd_nvld_d + , vd => vdd + , gd => gnd + ); + + scom_act <= sc_req_d or sc_req_q or scom_local_act; + + sc_wr_d <= not sc_r_nw; + + scaddr_v_d <= gate_and(sc_req_d, scaddr_dec_d); + scaddr_v <= scaddr_v_q; + + sc_ack <= (sc_req_d and not sc_r_nw) or (sc_req_q and sc_r_nw); + + sc_ack_info <= gate_and(not sc_r_nw, (sc_wr_nvld_d or sc_rd_nvld_d) & scaddr_nvld_d) or + gate_and(sc_r_nw, (sc_wr_nvld_q or sc_rd_nvld_q) & scaddr_nvld_q) ; + + scom_ack_err <= or_reduce(sc_ack_info); + + sc_wparity <= sc_wparity_out xor sc_parity_error_inject; + + + andmask_ones <= (others => '1'); + + + rami_d(0 to 31) <= sc_wdata(0 to 31) when (scaddr_v(40) and sc_wr_q) = '1' else + sc_wdata(32 to 63) when (scaddr_v(41) and sc_wr_q) = '1' else + rami_q(0 to 31); + + rami_out <= tidn_32 & rami_q(0 to 31); + + ramic_out <= rami_out(32 to 63) & ramc_out(32 to 63); + + + + or_ramc_load <= (scaddr_v(40) or scaddr_v(42) or scaddr_v(44)) and sc_wr_q; + and_ramc_ones <= not((scaddr_v(40) or scaddr_v(42) or scaddr_v(43)) and sc_wr_q); + and_ramc_load <= scaddr_v(43) and sc_wr_q; + + or_ramc <= gate_and(or_ramc_load, sc_wdata); + and_ramc <= gate_and(and_ramc_load, sc_wdata) or gate_and(and_ramc_ones, andmask_ones); + + + ramc_instr_in <= or_ramc(32 to 35) or (ramc_out(32 to 35) and and_ramc(32 to 35)); + + ramc_mode_in <= or_ramc(44 to 46) or (ramc_out(44 to 46) and and_ramc(44 to 46)); + + ramc_execute_in <= or_ramc(47); + + ramc_msr_ovrid_in <= or_ramc(48 to 50) or (ramc_out(48 to 50) and and_ramc(48 to 50)); + + ramc_force_cmplt_in <= or_ramc(51) or (ramc_out(51) and and_ramc(51)); + + ramc_force_flush_in <= or_ramc(52); + + ramc_msr_de_ovrid_in <= or_ramc(53) or (ramc_out(53) and and_ramc(53)); + + ramc_spare_in <= or_ramc(54 to 56) or (ramc_out(54 to 56) and and_ramc(54 to 56)); + + ramc_status_in(0) <= xu_pc_ram_interrupt or or_ramc(61) or (ramc_out(61) and and_ramc(61)); + + ramc_status_in(1) <= rg_rg_ram_mode_xstop or or_ramc(62) or (ramc_out(62) and and_ramc(62)); + + ramc_status_in(2) <= xu_ram_done_q or fu_ram_done_q or or_ramc(63) or + (ramc_out(63) and and_ramc(63) and not ramc_out(47)); + + + ramc_d <= ramc_instr_in & ramc_mode_in & ramc_execute_in & ramc_msr_ovrid_in & ramc_force_cmplt_in & + ramc_force_flush_in & ramc_msr_de_ovrid_in & ramc_spare_in & ramc_status_in; + + ramc_out <= tidn_32 & ramc_q(0 to 3) & x"00" & ramc_q(4 to 7) & ramc_q(8 to 13) & + ramc_q(14 to 16) & "0000" & ramc_q(17 to 19); + + + + + fu_ramd_load_data_d <= fu_pc_ram_data(0 to 63); + + ramd_xu_load_zeros(0 to 64-(2**regmode)) <= (others => '0'); + xu_ramd_load_data_d(0 to 64) <= ramd_xu_load_zeros & xu_pc_ram_data(64-(2**regmode) to 63); + xu_ramd_load_data(0 to 63) <= xu_ramd_load_data_q(1 to 64); + + ramd_d(0 to 31) <= sc_wdata(0 to 31) when (scaddr_v(45) and sc_wr_q) = '1' else + sc_wdata(32 to 63) when (scaddr_v(46) and sc_wr_q) = '1' else + fu_ramd_load_data_q(0 to 31) when fu_ram_done_q = '1' else + xu_ramd_load_data(0 to 31) when xu_ram_done_q = '1' else + ramd_q(0 to 31); + + ramd_d(32 to 63) <= sc_wdata(32 to 63) when (scaddr_v(45) and sc_wr_q) = '1' else + sc_wdata(32 to 63) when (scaddr_v(47) and sc_wr_q) = '1' else + fu_ramd_load_data_q(32 to 63) when fu_ram_done_q = '1' else + xu_ramd_load_data(32 to 63) when xu_ram_done_q = '1' else + ramd_q(32 to 63); + + ramdh_out <= tidn_32 & ramd_q(0 to 31); + + ramdl_out <= tidn_32 & ramd_q(32 to 63); + + + + or_thrctl_load <= (scaddr_v(48) or scaddr_v(50)) and sc_wr_q; + and_thrctl_ones <= not((scaddr_v(48) or scaddr_v(49)) and sc_wr_q); + and_thrctl_load <= scaddr_v(49) and sc_wr_q; + + or_thrctl <= gate_and(or_thrctl_load, sc_wdata); + and_thrctl <= gate_and(and_thrctl_load, sc_wdata) or gate_and(and_thrctl_ones, andmask_ones); + + + thrctl_stop_in <= stop_dbg_event_q(0 to 3) or attn_instr_int(0 to 3) or + rg_rg_xstop_err(0 to 3) or + or_thrctl(32 to 35) or (thrctl_out(32 to 35) and and_thrctl(32 to 35)) ; + + thrctl_step_in <= or_thrctl(36 to 39) or + (thrctl_out(36 to 39) and and_thrctl(36 to 39) and not step_done_q(0 to 3)); + + thrctl_run_in <= xu_pc_running(0 to 3); + + thrctl_pm_in <= ct_rg_power_managed(0 to 3) or ct_rg_pm_thread_stop(0 to 3); + + thrctl_misc_dbg_in <= or_thrctl(48 to 54) or (thrctl_out(48 to 54) and and_thrctl(48 to 54)); + + thrctl_spare_in <= or_thrctl(55 to 59) or (thrctl_out(55 to 59) and and_thrctl(55 to 59)); + + + thrctl1_d <= thrctl_stop_in & thrctl_step_in & thrctl_run_in & thrctl_pm_in; + thrctl2_d <= thrctl_misc_dbg_in & thrctl_spare_in; + + thrctl_out <= tidn_32 & thrctl1_q(0 to 3) & thrctl1_q(4 to 7) & thrctl1_q(8 to 11) & + thrctl1_q(12 to 15) & thrctl2_q(0 to 6) & thrctl2_q(7 to 11) & x"0"; + + + + or_pccr0_load <= (scaddr_v(51) or scaddr_v(53)) and sc_wr_q; + and_pccr0_ones <= not((scaddr_v(51) or scaddr_v(52)) and sc_wr_q); + and_pccr0_load <= scaddr_v(52) and sc_wr_q; + + or_pccr0 <= gate_and(or_pccr0_load, sc_wdata); + and_pccr0 <= gate_and(and_pccr0_load, sc_wdata) or gate_and(and_pccr0_ones, andmask_ones); + + + pccr0_pervModes_in <= or_pccr0(32 to 38) or (pccr0_out(32 to 38) and and_pccr0(32 to 38)); + + pccr0_spare_in <= or_pccr0(39 to 43) or (pccr0_out(39 to 43) and and_pccr0(39 to 43)); + + + incr_recErrCntr <= recErrCntr_q(0 to 3) + "0001"; + recErrCntr_pargen <= xor_reduce(incr_recErrCntr & pccr0_out(32 to 43) & pccr0_out(52 to 63)); + + recErrCntr_in <= sc_wdata(48 to 51) when (scaddr_v(51) and sc_wr_q) = '1' else + incr_recErrCntr when rg_rg_gateRecErrCntr = '1' else + recErrCntr_q(0 to 3); + + + pccr0_dbgActSel_in <= or_pccr0(52 to 63) or (pccr0_out(52 to 63) and and_pccr0(52 to 63)); + + + pccr0_d <= pccr0_pervModes_in & pccr0_spare_in & pccr0_dbgActSel_in; + + pccr0_out <= tidn_32 & pccr0_q(0 to 11) & x"0" & recErrCntr_q & pccr0_q(12 to pccr0_size-1); + + pccr0_par_in <= pccr0_d & recErrCntr_in(0 to 3); + pccr0_par_d(0) <= parity_gen_even(pccr0_par_in) when (gate_and(sc_wr_q, or_reduce(scaddr_v(51 to 53))))='1' else + recErrCntr_pargen when rg_rg_gateRecErrCntr = '1' else + pccr0_par_q(0); + + pccr0_par_err <= (xor_reduce(pccr0_out) xor pccr0_par_q(0)) or + (sc_wr_q and or_reduce(scaddr_v(51 to 53)) and sc_parity_error_inject); + + + + + or_spattn_load <= (scaddr_v(54) or scaddr_v(56)) and sc_wr_q; + and_spattn_ones <= not((scaddr_v(54) or scaddr_v(55)) and sc_wr_q); + and_spattn_load <= scaddr_v(55) and sc_wr_q; + + or_spattn <= gate_and(or_spattn_load, sc_wdata); + and_spattn <= gate_and(and_spattn_load, sc_wdata) or gate_and(and_spattn_ones, andmask_ones); + + spattn_unused <= (others => '0'); + + + spattn_attn_instr_in <= attn_instr_int(0 to 3) or or_spattn(32 to 35) or + (spattn_out(32 to 35) and and_spattn(32 to 35)) ; + + + + spattn_data_d <= spattn_attn_instr_in; + + + spattn_mask_d <= or_spattn(48 to (48 + spattn_size-1)) or + (spattn_out(48 to (48 + spattn_size-1)) and and_spattn(48 to (48 + spattn_size-1))); + + spattn_out <= tidn_32 & spattn_data_q & spattn_unused & spattn_mask_q & spattn_unused ; + + + spattn_par_d(0) <= parity_gen_even(spattn_mask_d) when (gate_and(sc_wr_q, or_reduce(scaddr_v(54 to 56))))='1' else + spattn_par_q(0); + + spattn_par_err <= (xor_reduce(spattn_mask_q) xor spattn_par_q(0)) or + (sc_wr_q and or_reduce(scaddr_v(54 to 56)) and sc_parity_error_inject); + + + + abdsr_data_in <= sc_wdata(32 to 63) when (scaddr_v(59) and sc_wr_q) = '1' else abdsr_out(32 to 63); + abdsr_d <= abdsr_data_in; + abdsr_out <= tidn_32 & abdsr_q(0 to 31); + abdsr_par_d(0) <= sc_wparity when (scaddr_v(59) and sc_wr_q) = '1' else abdsr_par_q(0); + abdsr_par_err <= xor_reduce(abdsr_q) xor abdsr_par_q(0); + + + idsr_data_in <= sc_wdata(32 to 63) when (scaddr_v(60) and sc_wr_q) = '1' else idsr_out(32 to 63); + idsr_d <= idsr_data_in; + idsr_out <= tidn_32 & idsr_q(0 to 31); + idsr_par_d(0) <= sc_wparity when (scaddr_v(60) and sc_wr_q) = '1' else idsr_par_q(0); + idsr_par_err <= xor_reduce(idsr_q) xor idsr_par_q(0); + + + mpdsr_data_in <= sc_wdata(32 to 63) when (scaddr_v(61) and sc_wr_q) = '1' else mpdsr_out(32 to 63); + mpdsr_d <= mpdsr_data_in; + mpdsr_out <= tidn_32 & mpdsr_q(0 to 31); + mpdsr_par_d(0) <= sc_wparity when (scaddr_v(61) and sc_wr_q) = '1' else mpdsr_par_q(0); + mpdsr_par_err <= xor_reduce(mpdsr_q) xor mpdsr_par_q(0); + + + xdsr1_data_in <= sc_wdata(32 to 63) when (scaddr_v(62) and sc_wr_q) = '1' else xdsr1_out(32 to 63); + xdsr1_d <= xdsr1_data_in; + xdsr1_out <= tidn_32 & xdsr1_q(0 to 31); + xdsr1_par_d(0) <= sc_wparity when (scaddr_v(62) and sc_wr_q) = '1' else xdsr1_par_q(0); + xdsr1_par_err_d <= xor_reduce(xdsr1_q) xor xdsr1_par_q(0); + + + xdsr2_data_in <= sc_wdata(32 to 63) when (scaddr_v(63) and sc_wr_q) = '1' else xdsr2_out(32 to 63); + xdsr2_d <= xdsr2_data_in; + xdsr2_out <= tidn_32 & xdsr2_q(0 to 31); + xdsr2_par_d(0) <= sc_wparity when (scaddr_v(63) and sc_wr_q) = '1' else xdsr2_par_q(0); + xdsr2_par_err <= xor_reduce(xdsr2_q) xor xdsr2_par_q(0); + + + errinj_thread_in <= sc_wdata(32 to 35) when (scaddr_v(9) and sc_wr_q) = '1' else + errinj_out(32 to 35); + + errinj_errtype_in <= sc_wdata(40 to 54) when (scaddr_v(9) and sc_wr_q) = '1' else + (errinj_out(40 to 54) and not rg_rg_errinj_shutoff); + + errinj_d <= errinj_thread_in & errinj_errtype_in; + + errinj_out <= tidn_32 & errinj_q(0 to 3) & "0000" & errinj_q(4 to 18) & (55 to 63 => '0'); + + + scaddr_fir <= scaddr_v(0) or scaddr_v(3) or scaddr_v(4) or scaddr_v(6) or + scaddr_v(5) or scaddr_v(19) or + scaddr_v(10) or scaddr_v(13) or scaddr_v(14) or scaddr_v(16) or + scaddr_v(20) or scaddr_v(23) or scaddr_v(24) or scaddr_v(26); + + sc_rdata <= gate_and(scaddr_v(40), ramic_out) or + gate_and(scaddr_v(41), rami_out) or + gate_and(scaddr_v(42), ramc_out) or + gate_and(scaddr_v(45), ramd_q(0 to 63)) or + gate_and(scaddr_v(46), ramdh_out) or + gate_and(scaddr_v(47), ramdl_out) or + gate_and(scaddr_v(48), thrctl_out) or + gate_and(scaddr_v(51), pccr0_out) or + gate_and(scaddr_v(54), spattn_out) or + gate_and(scaddr_v(59), abdsr_out) or + gate_and(scaddr_v(60), idsr_out) or + gate_and(scaddr_v(61), mpdsr_out) or + gate_and(scaddr_v(62), xdsr1_out) or + gate_and(scaddr_v(63), xdsr2_out) or + gate_and(scaddr_v(9), errinj_out) or + gate_and(scaddr_fir, fir_data_out) ; + + + + ram_mode_d <= ram_enab_d and ramc_out(44); + ram_execute_d <= ram_mode_d and ramc_out(47); + ram_thread_d <= ramc_out(45 to 46); + + pc_iu_ram_instr <= rami_out(32 to 63); + pc_iu_ram_instr_ext <= ramc_out(32 to 35); + pc_iu_ram_mode <= ram_mode_q; + pc_iu_ram_thread <= ram_thread_q(0 to 1); + + pc_xu_ram_mode <= ram_mode_q; + pc_xu_ram_thread <= ram_thread_q(0 to 1); + pc_xu_ram_execute <= ram_execute_q; + + pc_fu_ram_mode <= ram_mode_q; + pc_fu_ram_thread <= ram_thread_q(0 to 1); + + rg_rg_ram_mode <= ram_mode_q; + + + ram_msrovren_d <= ram_mode_d and ramc_out(48); + pc_xu_msrovride_enab <= ram_msrovren_q; + + ram_msrovrpr_d <= ram_mode_d and ramc_out(49); + pc_xu_msrovride_pr <= ram_msrovrpr_q; + + ram_msrovrgs_d <= ram_mode_d and ramc_out(50); + pc_xu_msrovride_gs <= ram_msrovrgs_q; + + ram_force_d <= ram_mode_d and ramc_out(51); + pc_iu_ram_force_cmplt <= ram_force_q; + + ram_flush_d <= ram_enab_d and ramc_out(52); + pc_xu_ram_flush_thread <= ram_flush_q; + + ram_msrovrde_d <= ram_mode_d and ramc_out(53); + pc_xu_msrovride_de <= ram_msrovrde_q; + + external_debug_stop <= gate_and(pccr0_out(35), (0 to 3=> ext_debug_stop_q)); + + tx_stop_d <= ct_rg_pm_thread_stop or external_debug_stop or + (0 to 3 => ct_rg_hold_during_init) or + (thrctl_out(32 to 35) and not tx_step_d(0 to 3)); + pc_xu_stop <= tx_stop_q(0 to 3); + + tx_step_d <= gate_and(debug_mode_d, thrctl_out(36 to 39)); + pc_xu_step <= tx_step_q(0 to 3); + + ac_an_pm_thread_running <= thrctl_out(40 to 43); + + ude_dly_d(0 to 3) <= thrctl_out(48 to 51); + force_ude_pulse(0 to 3) <= thrctl_out(48 to 51) and not ude_dly_q(0 to 3); + tx_ude_d <= gate_and(debug_mode_d, force_ude_pulse(0 to 3)); + pc_xu_force_ude <= tx_ude_q(0 to 3); + + extirpts_dis_d <= debug_mode_d and thrctl_out(52); + pc_xu_extirpts_dis_on_stop <= extirpts_dis_q; + + timebase_dis_d <= debug_mode_d and thrctl_out(53); + pc_xu_timebase_dis_on_stop <= timebase_dis_q; + + decrem_dis_d <= debug_mode_d and thrctl_out(54); + pc_xu_decrem_dis_on_stop <= decrem_dis_q; + + trace_bus_enable_d <= pccr0_out(32) or sp_rg_trace_bus_enable; + + pc_fu_trace_bus_enable <= trace_bus_enable_q; + pc_bx_trace_bus_enable <= trace_bus_enable_q; + pc_iu_trace_bus_enable <= trace_bus_enable_q; + pc_mm_trace_bus_enable <= trace_bus_enable_q; + pc_xu_trace_bus_enable <= trace_bus_enable_q; + rg_db_trace_bus_enable <= trace_bus_enable_q; + + debug_mode_d <= pccr0_out(32); + debug_mode_act <= debug_mode_d or debug_mode_q; + + ram_enab_d <= pccr0_out(33); + ram_enab_act <= ram_enab_d or ram_enab_q; + ram_enab_scom_act <= ram_enab_act or scom_act; + + errinj_enab_d <= pccr0_out(34); + errinj_enab_act <= errinj_enab_d or errinj_enab_q; + errinj_enab_scom_act <= errinj_enab_act or scom_act; + + rg_rg_xstop_report_ovride <= pccr0_out(36); + + rg_rg_fast_xstop_enable <= debug_mode_d and pccr0_out(37); + + rg_ct_dis_pwr_savings <= pccr0_out(38); + + + rg_rg_maxRecErrCntrValue <= and_reduce(recErrCntr_q(0 to 3)); + + pc_xu_dbg_action <= pccr0_out(52 to 63); + + + spattn_out_masked <= spattn_data_q and not spattn_mask_q ; + + ac_an_special_attn(0) <= spattn_out_masked(0); + ac_an_special_attn(1) <= spattn_out_masked(1); + ac_an_special_attn(2) <= spattn_out_masked(2); + ac_an_special_attn(3) <= spattn_out_masked(3); + + pc_fu_debug_mux1_ctrls <= abdsr_out(32 to 47); + pc_bx_debug_mux1_ctrls <= abdsr_out(48 to 63); + + pc_mm_debug_mux1_ctrls <= mpdsr_out(32 to 47); + rg_db_debug_mux_ctrls <= mpdsr_out(48 to 63); + + pc_iu_debug_mux1_ctrls <= idsr_out(32 to 47); + pc_iu_debug_mux2_ctrls <= idsr_out(48 to 63); + + pc_xu_debug_mux1_ctrls <= xdsr1_out(32 to 47); + pc_xu_debug_mux2_ctrls <= xdsr1_out(48 to 63); + pc_xu_debug_mux3_ctrls <= xdsr2_out(32 to 47); + pc_xu_debug_mux4_ctrls <= xdsr2_out(48 to 63); + + inj_icache_parity_d <= errinj_enab_d and errinj_out(40); + inj_icachedir_parity_d <= errinj_enab_d and errinj_out(41); + inj_dcache_parity_d <= errinj_enab_d and errinj_out(42); + inj_dcachedir_parity_d <= errinj_enab_d and errinj_out(43); + inj_xuregfile_parity_d(0 to 3) <= gate_and(errinj_enab_d and errinj_out(44), errinj_out(32 to 35)); + inj_furegfile_parity_d(0 to 3) <= gate_and(errinj_enab_d and errinj_out(45), errinj_out(32 to 35)); + inj_sprg_ecc_d(0 to 3) <= gate_and(errinj_enab_d and errinj_out(46), errinj_out(32 to 35)); + inj_inbox_ecc_d <= errinj_enab_d and errinj_out(47); + inj_outbox_ecc_d <= errinj_enab_d and errinj_out(48); + inj_llbust_attempt_d(0 to 3) <= gate_and(errinj_enab_d and errinj_out(49), errinj_out(32 to 35)); + inj_llbust_failed_d(0 to 3) <= gate_and(errinj_enab_d and errinj_out(50), errinj_out(32 to 35)); + inj_wdt_reset_d(0 to 3) <= gate_and(errinj_enab_d and errinj_out(51), errinj_out(32 to 35)); + inj_icachedir_multihit_d <= errinj_enab_d and errinj_out(53); + inj_dcachedir_multihit_d <= errinj_enab_d and errinj_out(54); + + pc_iu_inj_icache_parity <= inj_icache_parity_q; + pc_iu_inj_icachedir_parity <= inj_icachedir_parity_q; + pc_xu_inj_dcache_parity <= inj_dcache_parity_q; + pc_xu_inj_dcachedir_parity <= inj_dcachedir_parity_q; + pc_xu_inj_regfile_parity(0 to 3) <= inj_xuregfile_parity_q(0 to 3); + pc_fu_inj_regfile_parity(0 to 3) <= inj_furegfile_parity_q(0 to 3); + pc_xu_inj_sprg_ecc(0 to 3) <= inj_sprg_ecc_q(0 to 3); + pc_bx_inj_inbox_ecc <= inj_inbox_ecc_q; + pc_bx_inj_outbox_ecc <= inj_outbox_ecc_q; + pc_xu_inj_llbust_attempt(0 to 3) <= inj_llbust_attempt_q(0 to 3); + pc_xu_inj_llbust_failed(0 to 3) <= inj_llbust_failed_q(0 to 3); + pc_xu_inj_wdt_reset(0 to 3) <= inj_wdt_reset_q(0 to 3); + sc_parity_error_inject <= errinj_enab_d and errinj_out(52); + pc_iu_inj_icachedir_multihit <= inj_icachedir_multihit_q; + pc_xu_inj_dcachedir_multihit <= inj_dcachedir_multihit_q; + + +fir_regs: entity work.pcq_regs_fir + generic map( expand_type => expand_type ) + port map + ( vdd => vdd + , gnd => gnd + , nclk => nclk + , lcb_clkoff_dc_b => lcb_clkoff_dc_b + , lcb_mpw1_dc_b => lcb_mpw1_dc_b + , lcb_mpw2_dc_b => lcb_mpw2_dc_b + , lcb_delay_lclkr_dc => lcb_delay_lclkr_dc + , lcb_act_dis_dc => lcb_act_dis_dc + , lcb_sg_0 => lcb_sg_0 + , lcb_func_slp_sl_thold_0 => lcb_func_slp_sl_thold_0 + , lcb_cfg_slp_sl_thold_0 => lcb_cfg_slp_sl_thold_0 + , cfgslp_d1clk => cfgslp_d1clk + , cfgslp_d2clk => cfgslp_d2clk + , cfgslp_lclk => cfgslp_lclk + , cfg_slat_d2clk => cfg_slat_d2clk + , cfg_slat_lclk => cfg_slat_lclk + , bcfg_scan_in => fir_mode_si + , func_scan_in => fir_func_si + , bcfg_scan_out => fir_mode_so + , func_scan_out => fir_func_so + , sc_active => scom_act + , sc_wr_q => sc_wr_q + , sc_addr_v => scaddr_v + , sc_wdata => sc_wdata + , sc_wparity => sc_wparity + , sc_rdata => fir_data_out + , ac_an_special_attn => attn_instr_int + , ac_an_checkstop => ac_an_checkstop + , ac_an_local_checkstop => ac_an_local_checkstop + , ac_an_recov_err => ac_an_recov_err + , ac_an_trace_error => ac_an_trace_error + , an_ac_checkstop => an_ac_checkstop + , an_ac_malf_alert => an_ac_malf_alert + , rg_rg_any_fir_xstop => rg_rg_any_fir_xstop + , iu_pc_err_icache_parity => iu_pc_err_icache_parity + , iu_pc_err_icachedir_parity => iu_pc_err_icachedir_parity + , iu_pc_err_icachedir_multihit => iu_pc_err_icachedir_multihit + , iu_pc_err_ucode_illegal => iu_pc_err_ucode_illegal + , xu_pc_err_dcache_parity => xu_pc_err_dcache_parity + , xu_pc_err_dcachedir_parity => xu_pc_err_dcachedir_parity + , xu_pc_err_dcachedir_multihit => xu_pc_err_dcachedir_multihit + , xu_pc_err_mcsr_summary => xu_pc_err_mcsr_summary + , xu_pc_err_ierat_parity => xu_pc_err_ierat_parity + , xu_pc_err_derat_parity => xu_pc_err_derat_parity + , xu_pc_err_tlb_parity => xu_pc_err_tlb_parity + , xu_pc_err_tlb_lru_parity => xu_pc_err_tlb_lru_parity + , xu_pc_err_ierat_multihit => xu_pc_err_ierat_multihit + , xu_pc_err_derat_multihit => xu_pc_err_derat_multihit + , xu_pc_err_tlb_multihit => xu_pc_err_tlb_multihit + , xu_pc_err_ext_mchk => xu_pc_err_ext_mchk + , xu_pc_err_ditc_overrun => xu_pc_err_ditc_overrun + , xu_pc_err_local_snoop_reject => xu_pc_err_local_snoop_reject + , xu_pc_err_sprg_ecc => xu_pc_err_sprg_ecc + , xu_pc_err_sprg_ue => xu_pc_err_sprg_ue + , xu_pc_err_regfile_parity => xu_pc_err_regfile_parity + , xu_pc_err_regfile_ue => xu_pc_err_regfile_ue + , xu_pc_err_llbust_attempt => xu_pc_err_llbust_attempt + , xu_pc_err_llbust_failed => xu_pc_err_llbust_failed + , xu_pc_err_l2intrf_ecc => xu_pc_err_l2intrf_ecc + , xu_pc_err_l2intrf_ue => xu_pc_err_l2intrf_ue + , xu_pc_err_l2credit_overrun => xu_pc_err_l2credit_overrun + , xu_pc_err_wdt_reset => xu_pc_err_wdt_reset + , xu_pc_err_attention_instr => xu_pc_err_attention_instr + , xu_pc_err_debug_event => xu_pc_err_debug_event + , xu_pc_err_nia_miscmpr => xu_pc_err_nia_miscmpr + , xu_pc_err_invld_reld => xu_pc_err_invld_reld + , xu_pc_err_mchk_disabled => xu_pc_err_mchk_disabled + , bx_pc_err_inbox_ecc => bx_pc_err_inbox_ecc + , bx_pc_err_inbox_ue => bx_pc_err_inbox_ue + , bx_pc_err_outbox_ecc => bx_pc_err_outbox_ecc + , bx_pc_err_outbox_ue => bx_pc_err_outbox_ue + , fu_pc_err_regfile_parity => fu_pc_err_regfile_parity + , fu_pc_err_regfile_ue => fu_pc_err_regfile_ue + , scom_reg_par_checks => scom_reg_par_checks + , scom_sat_fsm_error => scom_fsm_err + , scom_ack_error => scom_ack_err + , sc_parity_error_inject => sc_parity_error_inject + , rg_rg_xstop_report_ovride => rg_rg_xstop_report_ovride + , rg_rg_ram_mode => rg_rg_ram_mode + , rg_rg_ram_mode_xstop => rg_rg_ram_mode_xstop + , rg_rg_xstop_err => rg_rg_xstop_err + , rg_rg_errinj_shutoff => rg_rg_errinj_shutoff + , rg_rg_maxRecErrCntrValue => rg_rg_maxRecErrCntrValue + , rg_rg_gateRecErrCntr => rg_rg_gateRecErrCntr + , pc_xu_cache_par_err_event => pc_xu_cache_par_err_event + , dbg_fir0_err => dbg_fir0_err + , dbg_fir1_err => dbg_fir1_err + , dbg_fir2_err => dbg_fir2_err + , dbg_fir_misc => dbg_fir_misc + ); + + + scom_reg_par_checks <= abdsr_par_err & idsr_par_err & mpdsr_par_err & + xdsr1_par_err_q & xdsr2_par_err & pccr0_par_err & + spattn_par_err ; + + + rg_ck_fast_xstop <= rg_rg_fast_xstop_enable and rg_rg_any_fir_xstop ; + + + dbg_scom_rdata <= sc_rdata(0 to 63); + + dbg_scom_wdata <= sc_wdata(0 to 63); + + dbg_scom_decaddr <= scaddr_v_q(0 to 63); + + dbg_scom_misc <= scom_act & + sc_req_q & + sc_wr_q & + scaddr_nvld_q & + sc_wr_nvld_q & + sc_rd_nvld_q & + scaddr_fir & + sc_parity_error_inject & + sc_wparity ; + + dbg_ram_thrctl <= ramc_out(47) & + ramc_out(61) & + ramc_out(62) & + ramc_out(63) & + ramc_out(45 to 46) & + ram_mode_q & + xu_ram_done_q & + fu_ram_done_q & + tx_stop_q & + tx_step_q & + thrctl_out(40 to 43) ; + + +axbx_dbgsel_reg: tri_rlmreg_p + generic map (width => abdsr_q'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => scom_act, + thold_b => lcb_cfg_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_cfgslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => dcfg_siv(abdsr_offset to abdsr_offset + abdsr_q'length-1), + scout => dcfg_sov(abdsr_offset to abdsr_offset + abdsr_q'length-1), + din => abdsr_d, + dout => abdsr_q ); + +axbx_dbgsel_par: tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => scom_act, + thold_b => lcb_cfg_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_cfgslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => dcfg_siv(abdsr_par_offset to abdsr_par_offset), + scout => dcfg_sov(abdsr_par_offset to abdsr_par_offset), + din => abdsr_par_d, + dout => abdsr_par_q ); + +iu_dbgsel_reg: tri_rlmreg_p + generic map (width => idsr_q'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => scom_act, + thold_b => lcb_cfg_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_cfgslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => dcfg_siv(idsr_offset to idsr_offset + idsr_q'length-1), + scout => dcfg_sov(idsr_offset to idsr_offset + idsr_q'length-1), + din => idsr_d, + dout => idsr_q ); + +iu_dbgsel_par: tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => scom_act, + thold_b => lcb_cfg_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_cfgslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => dcfg_siv(idsr_par_offset to idsr_par_offset), + scout => dcfg_sov(idsr_par_offset to idsr_par_offset), + din => idsr_par_d, + dout => idsr_par_q ); + +mmpc_dbgsel_reg: tri_rlmreg_p + generic map (width => mpdsr_q'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => scom_act, + thold_b => lcb_cfg_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_cfgslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => dcfg_siv(mpdsr_offset to mpdsr_offset + mpdsr_q'length-1), + scout => dcfg_sov(mpdsr_offset to mpdsr_offset + mpdsr_q'length-1), + din => mpdsr_d, + dout => mpdsr_q ); + +mmpc_dbgsel_par: tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => scom_act, + thold_b => lcb_cfg_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_cfgslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => dcfg_siv(mpdsr_par_offset to mpdsr_par_offset), + scout => dcfg_sov(mpdsr_par_offset to mpdsr_par_offset), + din => mpdsr_par_d, + dout => mpdsr_par_q ); + +xu_dbgsel1_reg: tri_rlmreg_p + generic map (width => xdsr1_q'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => scom_act, + thold_b => lcb_cfg_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_cfgslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => dcfg_siv(xdsr1_offset to xdsr1_offset + xdsr1_q'length-1), + scout => dcfg_sov(xdsr1_offset to xdsr1_offset + xdsr1_q'length-1), + din => xdsr1_d, + dout => xdsr1_q ); + +xu_dbgsel1_par: tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => scom_act, + thold_b => lcb_cfg_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_cfgslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => dcfg_siv(xdsr1_par_offset to xdsr1_par_offset), + scout => dcfg_sov(xdsr1_par_offset to xdsr1_par_offset), + din => xdsr1_par_d, + dout => xdsr1_par_q ); + +xu_dbgsel2_reg: tri_rlmreg_p + generic map (width => xdsr2_q'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => scom_act, + thold_b => lcb_cfg_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_cfgslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => dcfg_siv(xdsr2_offset to xdsr2_offset + xdsr2_q'length-1), + scout => dcfg_sov(xdsr2_offset to xdsr2_offset + xdsr2_q'length-1), + din => xdsr2_d, + dout => xdsr2_q ); + +xu_dbgsel2_par: tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => scom_act, + thold_b => lcb_cfg_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_cfgslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => dcfg_siv(xdsr2_par_offset to xdsr2_par_offset), + scout => dcfg_sov(xdsr2_par_offset to xdsr2_par_offset), + din => xdsr2_par_d, + dout => xdsr2_par_q ); + +pccr0_reg: tri_rlmreg_p + generic map (width => pccr0_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => scom_act, + thold_b => lcb_cfg_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_cfgslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => dcfg_siv(pccr0_offset to pccr0_offset + pccr0_size-1), + scout => dcfg_sov(pccr0_offset to pccr0_offset + pccr0_size-1), + din => pccr0_d, + dout => pccr0_q ); + +rec_err_cntr: tri_rlmreg_p + generic map (width => recerrcntr_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => lcb_cfg_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_cfgslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => dcfg_siv(recerrcntr_offset to recerrcntr_offset + recerrcntr_size-1), + scout => dcfg_sov(recerrcntr_offset to recerrcntr_offset + recerrcntr_size-1), + din => recErrCntr_in, + dout => recErrCntr_q ); + +pccr0_par: tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => lcb_cfg_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_cfgslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => dcfg_siv(pccr0_par_offset to pccr0_par_offset), + scout => dcfg_sov(pccr0_par_offset to pccr0_par_offset), + din => pccr0_par_d, + dout => pccr0_par_q ); + +dcfg_stage1: tri_rlmreg_p + generic map (width => dcfg_stage1_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => lcb_cfg_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_cfgslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => dcfg_siv(dcfg_stage1_offset to dcfg_stage1_offset + dcfg_stage1_size-1), + scout => dcfg_sov(dcfg_stage1_offset to dcfg_stage1_offset + dcfg_stage1_size-1), + din(0) => debug_mode_d, + din(1) => ram_enab_d, + din(2) => errinj_enab_d, + din(3) => trace_bus_enable_d, + din(4) => xdsr1_par_err_d, + dout(0) => debug_mode_q, + dout(1) => ram_enab_q, + dout(2) => errinj_enab_q, + dout(3) => trace_bus_enable_q, + dout(4) => xdsr1_par_err_q ); +thrctl1_reg: tri_rlmreg_p + generic map (width => thrctl1_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => lcb_cfg_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_cfgslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => bcfg_siv(thrctl1_offset to thrctl1_offset + thrctl1_size-1), + scout => bcfg_sov(thrctl1_offset to thrctl1_offset + thrctl1_size-1), + din => thrctl1_d, + dout => thrctl1_q ); + +thrctl2_reg: tri_rlmreg_p + generic map (width => thrctl2_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => scom_act, + thold_b => lcb_cfg_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_cfgslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => bcfg_siv(thrctl2_offset to thrctl2_offset + thrctl2_size-1), + scout => bcfg_sov(thrctl2_offset to thrctl2_offset + thrctl2_size-1), + din => thrctl2_d, + dout => thrctl2_q ); + +spattn_data_reg: tri_rlmreg_p + generic map (width => spattn_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => lcb_cfg_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_cfgslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => bcfg_siv(spattn1_offset to spattn1_offset + spattn_size-1), + scout => bcfg_sov(spattn1_offset to spattn1_offset + spattn_size-1), + din => spattn_data_d, + dout => spattn_data_q ); + +spattn_mask_reg: tri_rlmreg_p + generic map (width => spattn_size, init => 15, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => scom_act, + thold_b => lcb_cfg_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_cfgslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => bcfg_siv(spattn2_offset to spattn2_offset + spattn_size-1), + scout => bcfg_sov(spattn2_offset to spattn2_offset + spattn_size-1), + din => spattn_mask_d, + dout => spattn_mask_q ); + +spattn_par: tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => scom_act, + thold_b => lcb_cfg_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_cfgslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => bcfg_siv(spattn_par_offset to spattn_par_offset), + scout => bcfg_sov(spattn_par_offset to spattn_par_offset), + din => spattn_par_d, + dout => spattn_par_q ); + +bcfg_stage1: tri_rlmreg_p + generic map (width => bcfg_stage1_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => lcb_cfg_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_cfgslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => bcfg_siv(bcfg_stage1_offset to bcfg_stage1_offset + bcfg_stage1_size-1), + scout => bcfg_sov(bcfg_stage1_offset to bcfg_stage1_offset + bcfg_stage1_size-1), + din(0 to 3) => tx_stop_d, + din(4) => an_ac_debug_stop, + din(5 to 8) => xu_pc_stop_dbg_event, + din(9 to 12) => xu_pc_step_done, + dout(0 to 3) => tx_stop_q, + dout(4) => ext_debug_stop_q, + dout(5 to 8) => stop_dbg_event_q, + dout(9 to 12) => step_done_q ); + +bcfg_stage2: tri_ser_rlmreg_p + generic map (width => bcfg_stage2_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => debug_mode_act, + thold_b => lcb_cfg_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_cfgslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => bcfg_siv(bcfg_stage2_offset to bcfg_stage2_offset + bcfg_stage2_size-1), + scout => bcfg_sov(bcfg_stage2_offset to bcfg_stage2_offset + bcfg_stage2_size-1), + din(0 to 3) => tx_step_d, + din(4) => extirpts_dis_d, + din(5) => timebase_dis_d, + din(6) => decrem_dis_d, + din(7 to 10) => ude_dly_d, + din(11 to 14) => tx_ude_d, + dout(0 to 3) => tx_step_q, + dout(4) => extirpts_dis_q, + dout(5) => timebase_dis_q, + dout(6) => decrem_dis_q, + dout(7 to 10) => ude_dly_q, + dout(11 to 14) => tx_ude_q ); +ccfg_repwr: tri_slat_scan + generic map (width => 1, init => "0", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => cfg_slat_d2clk, + lclk => cfg_slat_lclk, + scan_in(0) => ccfg_scan_in, + scan_out(0) => ccfg_scan_out ); +rami_reg: tri_rlmreg_p + generic map (width => rami_q'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ram_enab_scom_act, + thold_b => lcb_func_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_funcslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(rami_offset to rami_offset + rami_q'length-1), + scout => func_sov(rami_offset to rami_offset + rami_q'length-1), + din => rami_d, + dout => rami_q ); + +ramc_reg: tri_rlmreg_p + generic map (width => ramc_q'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ram_enab_scom_act, + thold_b => lcb_func_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_funcslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(ramc_offset to ramc_offset + ramc_q'length-1), + scout => func_sov(ramc_offset to ramc_offset + ramc_q'length-1), + din => ramc_d, + dout => ramc_q ); + +ramd_reg: tri_rlmreg_p + generic map (width => ramd_q'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ram_enab_scom_act, + thold_b => lcb_func_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_funcslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(ramd_offset to ramd_offset + ramd_q'length-1), + scout => func_sov(ramd_offset to ramd_offset + ramd_q'length-1), + din => ramd_d, + dout => ramd_q ); + +fu_ram_din: tri_rlmreg_p + generic map (width => fu_ram_din_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ram_enab_act, + thold_b => lcb_func_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_funcslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(fu_ram_din_offset to fu_ram_din_offset + fu_ram_din_size-1), + scout => func_sov(fu_ram_din_offset to fu_ram_din_offset + fu_ram_din_size-1), + din => fu_ramd_load_data_d, + dout => fu_ramd_load_data_q ); + +xu_ram_din: tri_rlmreg_p + generic map (width => xu_ram_din_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ram_enab_act, + thold_b => lcb_func_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_funcslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(xu_ram_din_offset to xu_ram_din_offset + xu_ram_din_size-1), + scout => func_sov(xu_ram_din_offset to xu_ram_din_offset + xu_ram_din_size-1), + din => xu_ramd_load_data_d, + dout => xu_ramd_load_data_q ); + +errinj_reg: tri_rlmreg_p + generic map (width => errinj_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => errinj_enab_scom_act, + thold_b => lcb_func_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_funcslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(errinj_offset to errinj_offset + errinj_size-1), + scout => func_sov(errinj_offset to errinj_offset + errinj_size-1), + din => errinj_d, + dout => errinj_q ); + +sc_misc: tri_ser_rlmreg_p + generic map (width => scom_misc_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => scom_act, + thold_b => lcb_func_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_funcslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(sc_misc_offset to sc_misc_offset + scom_misc_size-1), + scout => func_sov(sc_misc_offset to sc_misc_offset + scom_misc_size-1), + din(0) => sc_req_d, + din(1) => scaddr_nvld_d, + din(2) => sc_wr_nvld_d, + din(3) => sc_rd_nvld_d, + din(4) => sc_wr_d, + din(5) => ram_flush_d, + dout(0) => sc_req_q, + dout(1) => scaddr_nvld_q, + dout(2) => sc_wr_nvld_q, + dout(3) => sc_rd_nvld_q, + dout(4) => sc_wr_q, + dout(5) => ram_flush_q); + + +scaddr_dec: tri_rlmreg_p + generic map (width => scaddr_v_q'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => scom_act, + thold_b => lcb_func_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_funcslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(scaddr_dec_offset to scaddr_dec_offset + scaddr_v_q'length-1), + scout => func_sov(scaddr_dec_offset to scaddr_dec_offset + scaddr_v_q'length-1), + din => scaddr_v_d, + dout => scaddr_v_q ); + +func_stage1: tri_rlmreg_p + generic map (width => func_stage1_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => lcb_func_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_funcslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(func_stage1_offset to func_stage1_offset + func_stage1_size-1), + scout => func_sov(func_stage1_offset to func_stage1_offset + func_stage1_size-1), + din(0) => an_ac_scom_cch, + din(1) => an_ac_scom_dch, + dout(0) => scom_cch_q, + dout(1) => scom_dch_q ); + + +func_stage2: tri_ser_rlmreg_p + generic map (width => func_stage2_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => errinj_enab_act, + thold_b => lcb_func_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_funcslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(func_stage2_offset to func_stage2_offset + func_stage2_size-1), + scout => func_sov(func_stage2_offset to func_stage2_offset + func_stage2_size-1), + din(0) => inj_icache_parity_d, + din(1) => inj_icachedir_parity_d, + din(2) => inj_dcache_parity_d, + din(3) => inj_dcachedir_parity_d, + din(4 to 7) => inj_xuregfile_parity_d(0 to 3), + din(8 to 11) => inj_furegfile_parity_d(0 to 3), + din(12 to 15) => inj_sprg_ecc_d(0 to 3), + din(16) => inj_inbox_ecc_d, + din(17) => inj_outbox_ecc_d, + din(18 to 21) => inj_llbust_attempt_d(0 to 3), + din(22 to 25) => inj_llbust_failed_d(0 to 3), + din(26 to 29) => inj_wdt_reset_d(0 to 3), + din(30) => inj_icachedir_multihit_d, + din(31) => inj_dcachedir_multihit_d, + dout(0) => inj_icache_parity_q, + dout(1) => inj_icachedir_parity_q, + dout(2) => inj_dcache_parity_q, + dout(3) => inj_dcachedir_parity_q, + dout(4 to 7) => inj_xuregfile_parity_q(0 to 3), + dout(8 to 11) => inj_furegfile_parity_q(0 to 3), + dout(12 to 15) => inj_sprg_ecc_q(0 to 3), + dout(16) => inj_inbox_ecc_q, + dout(17) => inj_outbox_ecc_q, + dout(18 to 21) => inj_llbust_attempt_q(0 to 3), + dout(22 to 25) => inj_llbust_failed_q(0 to 3), + dout(26 to 29) => inj_wdt_reset_q(0 to 3), + dout(30) => inj_icachedir_multihit_q, + dout(31) => inj_dcachedir_multihit_q ); + +func_stage3: tri_ser_rlmreg_p + generic map (width => func_stage3_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ram_enab_act, + thold_b => lcb_func_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_funcslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(func_stage3_offset to func_stage3_offset + func_stage3_size-1), + scout => func_sov(func_stage3_offset to func_stage3_offset + func_stage3_size-1), + din(0) => ram_mode_d, + din(1) => ram_execute_d, + din(2) => ram_msrovren_d, + din(3) => ram_msrovrpr_d, + din(4) => ram_msrovrgs_d, + din(5) => ram_msrovrde_d, + din(6) => ram_force_d, + din(7) => xu_pc_ram_done, + din(8) => fu_pc_ram_done, + din(9 to 10) => ram_thread_d(0 to 1), + dout(0) => ram_mode_q, + dout(1) => ram_execute_q, + dout(2) => ram_msrovren_q, + dout(3) => ram_msrovrpr_q, + dout(4) => ram_msrovrgs_q, + dout(5) => ram_msrovrde_q, + dout(6) => ram_force_q, + dout(7) => xu_ram_done_q, + dout(8) => fu_ram_done_q, + dout(9 to 10) => ram_thread_q(0 to 1) ); + +cfg_slat_thold_b <= NOT lcb_cfg_sl_thold_0; +cfg_slat_force <= lcb_sg_0; + +lcbs_cfg: tri_lcbs + generic map (expand_type => expand_type ) + port map ( + vd => vdd, + gd => gnd, + delay_lclkr => lcb_delay_lclkr_dc, + nclk => nclk, + forcee => cfg_slat_force, + thold_b => cfg_slat_thold_b, + dclk => cfg_slat_d2clk, + lclk => cfg_slat_lclk ); + + +lcbor_cfgslp: tri_lcbor +generic map (expand_type => expand_type ) +port map ( + clkoff_b => lcb_clkoff_dc_b, + thold => lcb_cfg_slp_sl_thold_0, + sg => lcb_sg_0, + act_dis => lcb_act_dis_dc, + forcee => force_cfgslp, + thold_b => lcb_cfg_slp_sl_thold_0_b ); + +lcbn_cfgslp: tri_lcbnd +generic map (expand_type => expand_type ) +port map ( + vd => vdd, + gd => gnd, + act => tiup, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + nclk => nclk, + forcee => force_cfgslp, + sg => lcb_sg_0, + thold_b => lcb_cfg_slp_sl_thold_0_b, + d1clk => cfgslp_d1clk, + d2clk => cfgslp_d2clk, + lclk => cfgslp_lclk ); + + +lcbor_funcslp: tri_lcbor +generic map (expand_type => expand_type ) +port map ( + clkoff_b => lcb_clkoff_dc_b, + thold => lcb_func_slp_sl_thold_0, + sg => lcb_sg_0, + act_dis => lcb_act_dis_dc, + forcee => force_funcslp, + thold_b => lcb_func_slp_sl_thold_0_b ); + + + +bcfg_siv(0 TO bcfg_right) <= bcfg_scan_in & bcfg_sov(0 to bcfg_right-1); +fir_mode_si <= bcfg_sov(bcfg_right); +bcfg_scan_out <= fir_mode_so and scan_dis_dc_b; + +func_siv(0 TO func_right) <= func_scan_in & func_sov(0 to func_right-1); +fir_func_si <= func_sov(func_right); +func_scan_out <= fir_func_so and scan_dis_dc_b; + +dcfg_siv(0 TO dcfg_right) <= dcfg_scan_in & dcfg_sov(0 to dcfg_right-1); +dcfg_scan_out <= dcfg_sov(dcfg_right) and scan_dis_dc_b; + + +end pcq_regs; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/pcq_regs_fir.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/pcq_regs_fir.vhdl new file mode 100644 index 0000000..a747241 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/pcq_regs_fir.vhdl @@ -0,0 +1,866 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee; +use ieee.std_logic_1164.all; +library ibm,clib; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; +library support; +use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + + +entity pcq_regs_fir is +generic(expand_type : integer := 2); + +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + lcb_clkoff_dc_b : in std_ulogic; + lcb_mpw1_dc_b : in std_ulogic; + lcb_mpw2_dc_b : in std_ulogic; + lcb_delay_lclkr_dc : in std_ulogic; + lcb_act_dis_dc : in std_ulogic; + lcb_sg_0 : in std_ulogic; + lcb_func_slp_sl_thold_0 : in std_ulogic; + lcb_cfg_slp_sl_thold_0 : in std_ulogic; + cfgslp_d1clk : in std_ulogic; + cfgslp_d2clk : in std_ulogic; + cfgslp_lclk : in clk_logic; + cfg_slat_d2clk : in std_ulogic; + cfg_slat_lclk : in clk_logic; + bcfg_scan_in : in std_ulogic; + bcfg_scan_out : out std_ulogic; + func_scan_in : in std_ulogic; + func_scan_out : out std_ulogic; + sc_active : in std_ulogic; + sc_wr_q : in std_ulogic; + sc_addr_v : in std_ulogic_vector(0 to 63); + sc_wdata : in std_ulogic_vector(0 to 63); + sc_wparity : in std_ulogic; + sc_rdata : out std_ulogic_vector(0 to 63); + ac_an_special_attn : out std_ulogic_vector(0 to 3); + ac_an_checkstop : out std_ulogic_vector(0 to 2); + ac_an_local_checkstop : out std_ulogic_vector(0 to 2); + ac_an_recov_err : out std_ulogic_vector(0 to 2); + ac_an_trace_error : out std_ulogic; + rg_rg_any_fir_xstop : out std_ulogic; + an_ac_checkstop : in std_ulogic; + an_ac_malf_alert : in std_ulogic; + iu_pc_err_icache_parity : in std_ulogic; + iu_pc_err_icachedir_parity : in std_ulogic; + iu_pc_err_icachedir_multihit : in std_ulogic; + iu_pc_err_ucode_illegal : in std_ulogic_vector(0 to 3); + xu_pc_err_dcache_parity : in std_ulogic; + xu_pc_err_dcachedir_parity : in std_ulogic; + xu_pc_err_dcachedir_multihit : in std_ulogic; + xu_pc_err_mcsr_summary : in std_ulogic_vector(0 to 3); + xu_pc_err_ierat_parity : in std_ulogic; + xu_pc_err_derat_parity : in std_ulogic; + xu_pc_err_tlb_parity : in std_ulogic; + xu_pc_err_tlb_lru_parity : in std_ulogic; + xu_pc_err_ierat_multihit : in std_ulogic; + xu_pc_err_derat_multihit : in std_ulogic; + xu_pc_err_tlb_multihit : in std_ulogic; + xu_pc_err_ext_mchk : in std_ulogic; + xu_pc_err_ditc_overrun : in std_ulogic; + xu_pc_err_local_snoop_reject : in std_ulogic; + xu_pc_err_sprg_ecc : in std_ulogic_vector(0 to 3); + xu_pc_err_sprg_ue : in std_ulogic_vector(0 to 3); + xu_pc_err_regfile_parity : in std_ulogic_vector(0 to 3); + xu_pc_err_regfile_ue : in std_ulogic_vector(0 to 3); + xu_pc_err_llbust_attempt : in std_ulogic_vector(0 to 3); + xu_pc_err_llbust_failed : in std_ulogic_vector(0 to 3); + xu_pc_err_l2intrf_ecc : in std_ulogic; + xu_pc_err_l2intrf_ue : in std_ulogic; + xu_pc_err_l2credit_overrun : in std_ulogic; + xu_pc_err_wdt_reset : in std_ulogic_vector(0 to 3); + xu_pc_err_attention_instr : in std_ulogic_vector(0 to 3); + xu_pc_err_debug_event : in std_ulogic_vector(0 to 3); + xu_pc_err_nia_miscmpr : in std_ulogic_vector(0 to 3); + xu_pc_err_invld_reld : in std_ulogic; + xu_pc_err_mchk_disabled : in std_ulogic; + bx_pc_err_inbox_ecc : in std_ulogic; + bx_pc_err_inbox_ue : in std_ulogic; + bx_pc_err_outbox_ecc : in std_ulogic; + bx_pc_err_outbox_ue : in std_ulogic; + fu_pc_err_regfile_parity : in std_ulogic_vector(0 to 3); + fu_pc_err_regfile_ue : in std_ulogic_vector(0 to 3); + scom_reg_par_checks : in std_ulogic_vector(0 to 6); + scom_sat_fsm_error : in std_ulogic; + scom_ack_error : in std_ulogic; + sc_parity_error_inject : in std_ulogic; + rg_rg_xstop_report_ovride : in std_ulogic; + rg_rg_ram_mode : in std_ulogic; + rg_rg_ram_mode_xstop : out std_ulogic; + rg_rg_xstop_err : out std_ulogic_vector(0 to 3); + rg_rg_errinj_shutoff : out std_ulogic_vector(0 to 14); + rg_rg_maxRecErrCntrValue : in std_ulogic; + rg_rg_gateRecErrCntr : out std_ulogic; + pc_xu_cache_par_err_event : out std_ulogic; + dbg_fir0_err : out std_ulogic_vector(0 to 31); + dbg_fir1_err : out std_ulogic_vector(0 to 30); + dbg_fir2_err : out std_ulogic_vector(0 to 21); + dbg_fir_misc : out std_ulogic_vector(0 to 35) +); + +-- synopsys translate_off + + +-- synopsys translate_on +end pcq_regs_fir; + +architecture pcq_regs_fir of pcq_regs_fir is +constant fir0_width : positive := 32; +constant fir0_init : std_ulogic_vector := x"00000000"; +constant fir0mask_init : std_ulogic_vector := x"FFFFFFFF"; +constant fir0mask_par_init : std_ulogic_vector := "0"; +constant fir0act0_init : std_ulogic_vector := x"00000F00"; +constant fir0act0_par_init : std_ulogic_vector := "0"; +constant fir0act1_init : std_ulogic_vector := x"FFFFF0FF"; +constant fir0act1_par_init : std_ulogic_vector := "0"; +constant fir1_width : positive := 32; +constant fir1_init : std_ulogic_vector := x"00000000"; +constant fir1mask_init : std_ulogic_vector := x"FFFFFFFF"; +constant fir1mask_par_init : std_ulogic_vector := "0"; +constant fir1act0_init : std_ulogic_vector := x"3FFFFFFF"; +constant fir1act0_par_init : std_ulogic_vector := "0"; +constant fir1act1_init : std_ulogic_vector := x"C0000000"; +constant fir1act1_par_init : std_ulogic_vector := "0"; +constant fir2_width : positive := 22; +constant fir2_init : std_ulogic_vector := x"00000" & "00"; +constant fir2mask_init : std_ulogic_vector := x"FFFE0" & "11"; +constant fir2mask_par_init : std_ulogic_vector := "1"; +constant fir2act0_init : std_ulogic_vector := x"00020" & "00"; +constant fir2act0_par_init : std_ulogic_vector := "1"; +constant fir2act1_init : std_ulogic_vector := x"0FFC0" & "11"; +constant fir2act1_par_init : std_ulogic_vector := "0"; +constant scpar_err_rpt_width : positive := 16; +constant scpar_rpt_reset_value : std_ulogic_vector := x"0000"; +constant scack_err_rpt_width : positive := 2; +constant scack_rpt_reset_value : std_ulogic_vector := "00"; + +constant FIR0_bcfg_size : positive := 3*(fir0_width+1)+fir0_width; +constant FIR1_bcfg_size : positive := 3*(fir1_width+1)+fir1_width; +constant FIR2_bcfg_size : positive := 3*(fir2_width+1)+fir2_width; +constant FIR0_func_size : positive := 5; +constant FIR1_func_size : positive := 5; +constant FIR2_func_size : positive := 5; +constant attent_func_size : positive := 4; +constant errout_func_size : positive := 34; +constant bcfg_fir0_offset : natural := 0; +constant bcfg_fir1_offset : natural := bcfg_fir0_offset + FIR0_bcfg_size; +constant bcfg_fir2_offset : natural := bcfg_fir1_offset + FIR1_bcfg_size; +constant bcfg_erpt1_hld_offset : natural := bcfg_fir2_offset + FIR2_bcfg_size; +constant bcfg_erpt1_msk_offset : natural := bcfg_erpt1_hld_offset + scpar_err_rpt_width; +constant bcfg_erpt2_hld_offset : natural := bcfg_erpt1_msk_offset + scpar_err_rpt_width; +constant bcfg_erpt2_msk_offset : natural := bcfg_erpt2_hld_offset + scack_err_rpt_width; +constant bcfg_right : natural := bcfg_erpt2_msk_offset + scack_err_rpt_width - 1; +constant func_fir0_offset : natural := 0; +constant func_fir1_offset : natural := func_fir0_offset + FIR0_func_size; +constant func_fir2_offset : natural := func_fir1_offset + FIR1_func_size; +constant func_attent_offset : natural := func_fir2_offset + FIR2_func_size; +constant func_errout_offset : natural := func_attent_offset + attent_func_size; +constant func_f0err_offset : natural := func_errout_offset + errout_func_size; +constant func_f1err_offset : natural := func_f0err_offset + fir0_width; +constant func_f2err_offset : natural := func_f1err_offset + fir1_width; +constant func_right : natural := func_f2err_offset + fir2_width - 1; + +signal tidn, tiup : std_ulogic; +signal tidn_32 : std_ulogic_vector(0 to 31); +signal func_d1clk : std_ulogic; +signal func_d2clk : std_ulogic; +signal func_lclk : clk_logic; +signal func_thold_b : std_ulogic; +signal func_force : std_ulogic; +signal scom_err_rpt_held : std_ulogic_vector(0 to 63); +signal sc_reg_par_err_in : std_ulogic_vector(0 to scpar_err_rpt_width-1); +signal sc_reg_par_err_out : std_ulogic_vector(0 to scpar_err_rpt_width-1); +signal sc_reg_par_err_out_q : std_ulogic_vector(0 to scpar_err_rpt_width-1); +signal sc_reg_par_err_hold : std_ulogic_vector(0 to scpar_err_rpt_width-1); +signal scom_reg_parity_err : std_ulogic; +signal fir_regs_parity_err : std_ulogic; +signal sc_reg_ack_err_in : std_ulogic_vector(0 to scack_err_rpt_width-1); +signal sc_reg_ack_err_out : std_ulogic_vector(0 to scack_err_rpt_width-1); +signal sc_reg_ack_err_out_q : std_ulogic_vector(0 to scack_err_rpt_width-1); +signal sc_reg_ack_err_hold : std_ulogic_vector(0 to scack_err_rpt_width-1); +signal scom_reg_ack_err : std_ulogic; +signal fir0_errors : std_ulogic_vector(0 to fir0_width-1); +signal fir0_errors_q : std_ulogic_vector(0 to fir0_width-1); +signal fir0_fir_out : std_ulogic_vector(0 to fir0_width-1); +signal fir0_act0_out : std_ulogic_vector(0 to fir0_width-1); +signal fir0_act1_out : std_ulogic_vector(0 to fir0_width-1); +signal fir0_mask_out : std_ulogic_vector(0 to fir0_width-1); +signal fir0_scrdata : std_ulogic_vector(0 to fir0_width-1); +signal fir0_xstop_err : std_ulogic; +signal fir0_recov_err : std_ulogic; +signal fir0_lxstop_mchk : std_ulogic; +signal fir0_trace_error : std_ulogic; +signal fir0_block_on_checkstop : std_ulogic; +signal fir0_fir_parity_check : std_ulogic_vector(0 to 2); +signal fir0_recoverable_errors : std_ulogic_vector(0 to fir0_width-1); +signal fir0_recov_err_in : std_ulogic_vector(0 to 1); +signal fir0_recov_err_q : std_ulogic_vector(0 to 1); +signal fir0_recov_err_pulse : std_ulogic; +signal fir0_enabled_checkstops : std_ulogic_vector(32 to 32 + fir0_width-1); +signal fir1_errors : std_ulogic_vector(0 to fir1_width-1); +signal fir1_errors_q : std_ulogic_vector(0 to fir1_width-1); +signal fir1_fir_out : std_ulogic_vector(0 to fir1_width-1); +signal fir1_act0_out : std_ulogic_vector(0 to fir1_width-1); +signal fir1_act1_out : std_ulogic_vector(0 to fir1_width-1); +signal fir1_mask_out : std_ulogic_vector(0 to fir1_width-1); +signal fir1_scrdata : std_ulogic_vector(0 to fir1_width-1); +signal fir1_xstop_err : std_ulogic; +signal fir1_recov_err : std_ulogic; +signal fir1_lxstop_mchk : std_ulogic; +signal fir1_trace_error : std_ulogic; +signal fir1_block_on_checkstop : std_ulogic; +signal fir1_fir_parity_check : std_ulogic_vector(0 to 2); +signal fir1_recoverable_errors : std_ulogic_vector(0 to fir1_width-1); +signal fir1_recov_err_in : std_ulogic_vector(0 to 1); +signal fir1_recov_err_q : std_ulogic_vector(0 to 1); +signal fir1_recov_err_pulse : std_ulogic; +signal fir1_enabled_checkstops : std_ulogic_vector(32 to 32 + fir1_width-1); +signal fir2_errors : std_ulogic_vector(0 to fir2_width-1); +signal fir2_errors_q : std_ulogic_vector(0 to fir2_width-1); +signal fir2_fir_out : std_ulogic_vector(0 to fir2_width-1); +signal fir2_act0_out : std_ulogic_vector(0 to fir2_width-1); +signal fir2_act1_out : std_ulogic_vector(0 to fir2_width-1); +signal fir2_mask_out : std_ulogic_vector(0 to fir2_width-1); +signal fir2_scrdata : std_ulogic_vector(0 to fir2_width-1); +signal fir2_xstop_err : std_ulogic; +signal fir2_recov_err : std_ulogic; +signal fir2_lxstop_mchk : std_ulogic; +signal fir2_trace_error : std_ulogic; +signal fir2_block_on_checkstop : std_ulogic; +signal fir2_fir_parity_check : std_ulogic_vector(0 to 2); +signal fir2_recoverable_errors : std_ulogic_vector(0 to fir2_width-1); +signal fir2_recov_err_in : std_ulogic_vector(0 to 1); +signal fir2_recov_err_q : std_ulogic_vector(0 to 1); +signal fir2_recov_err_pulse : std_ulogic; +signal fir2_enabled_checkstops : std_ulogic_vector(36 to 32 + fir2_width-1); +signal injoff_icache_parity : std_ulogic; +signal injoff_icachedir_parity : std_ulogic; +signal injoff_dcache_parity : std_ulogic; +signal injoff_dcachedir_parity : std_ulogic; +signal injoff_xuregfile_parity : std_ulogic; +signal injoff_furegfile_parity : std_ulogic; +signal injoff_sprg_ecc : std_ulogic; +signal injoff_inbox_ecc : std_ulogic; +signal injoff_outbox_ecc : std_ulogic; +signal injoff_llbust_attempt : std_ulogic; +signal injoff_llbust_failed : std_ulogic; +signal injoff_wdt_reset : std_ulogic; +signal injoff_scomreg_parity : std_ulogic; +signal injoff_icachedir_multihit : std_ulogic; +signal injoff_dcachedir_multihit : std_ulogic; +signal error_inject_shutoff : std_ulogic_vector(0 to 14); +signal xstop_err_int, xstop_err_q : std_ulogic_vector(0 to 2); +signal xstop_out_d, xstop_out_q : std_ulogic_vector(0 to 2); +signal lxstop_err_int, lxstop_err_q : std_ulogic_vector(0 to 2); +signal xstop_err_per_thread : std_ulogic_vector(0 to 3); +signal xstop_err_common : std_ulogic; +signal an_ac_checkstop_q : std_ulogic; +signal maxRecErrCntrValue_errrpt : std_ulogic; +signal block_xstop_in_ram_mode : std_ulogic; +signal atten_instr_q : std_ulogic_vector(0 to 3); +signal bcfg_siv, bcfg_sov : std_ulogic_vector(0 to bcfg_right); +signal func_siv, func_sov : std_ulogic_vector(0 to func_right); +signal unused_signals : std_ulogic; + +begin + + + tiup <= '1'; + tidn <= '0'; + tidn_32 <= (others => '0'); + + unused_signals <= or_reduce( fir0_scrdata & fir1_scrdata & fir2_scrdata & + fir1_recoverable_errors(0) & sc_addr_v(9) & + sc_addr_v(29 to 63) & sc_wdata & an_ac_malf_alert ); + + + +FIR0: entity work.pcq_local_fir2 + generic map( width => fir0_width, + expand_type => expand_type, + impl_lxstop_mchk => false, + use_recov_reset => false, + fir_init => fir0_init, + fir_mask_init => fir0mask_init, + fir_mask_par_init => fir0mask_par_init, + fir_action0_init => fir0act0_init, + fir_action0_par_init => fir0act0_par_init, + fir_action1_init => fir0act1_init, + fir_action1_par_init => fir0act1_par_init + ) + port map + ( nclk => nclk + , vd => vdd + , gd => gnd + , lcb_clkoff_dc_b => lcb_clkoff_dc_b + , lcb_mpw1_dc_b => lcb_mpw1_dc_b + , lcb_mpw2_dc_b => lcb_mpw2_dc_b + , lcb_delay_lclkr_dc => lcb_delay_lclkr_dc + , lcb_act_dis_dc => lcb_act_dis_dc + , lcb_sg_0 => lcb_sg_0 + , lcb_func_slp_sl_thold_0 => lcb_func_slp_sl_thold_0 + , lcb_cfg_slp_sl_thold_0 => lcb_cfg_slp_sl_thold_0 + , mode_scan_siv => bcfg_siv(bcfg_fir0_offset to bcfg_fir0_offset + FIR0_bcfg_size-1) + , mode_scan_sov => bcfg_sov(bcfg_fir0_offset to bcfg_fir0_offset + FIR0_bcfg_size-1) + , func_scan_siv => func_siv(func_fir0_offset to func_fir0_offset + FIR0_func_size-1) + , func_scan_sov => func_sov(func_fir0_offset to func_fir0_offset + FIR0_func_size-1) + , error_in => fir0_errors_q + , xstop_err => fir0_xstop_err + , recov_err => fir0_recov_err + , lxstop_mchk => fir0_lxstop_mchk + , trace_error => fir0_trace_error + , sys_xstop_in => fir0_block_on_checkstop + , recov_reset => tidn + , fir_out => fir0_fir_out + , act0_out => fir0_act0_out + , act1_out => fir0_act1_out + , mask_out => fir0_mask_out + , sc_parity_error_inject => sc_parity_error_inject + , sc_active => sc_active + , sc_wr_q => sc_wr_q + , sc_addr_v => sc_addr_v(0 to 8) + , sc_wdata => sc_wdata(32 to 32+fir0_width-1) + , sc_wparity => sc_wparity + , sc_rdata => fir0_scrdata + , fir_parity_check => fir0_fir_parity_check + ); + + fir0_errors <= + iu_pc_err_icache_parity & iu_pc_err_icachedir_parity & + xu_pc_err_dcache_parity & xu_pc_err_dcachedir_parity & + xu_pc_err_sprg_ecc(0 to 3) & xu_pc_err_regfile_parity(0 to 3) & + fu_pc_err_regfile_parity(0 to 3) & bx_pc_err_inbox_ecc & + bx_pc_err_outbox_ecc & scom_reg_parity_err & + scom_reg_ack_err & xu_pc_err_wdt_reset(0 to 3) & + xu_pc_err_llbust_attempt(0 to 3) & xu_pc_err_llbust_failed(0 to 3) ; + + fir0_block_on_checkstop <= an_ac_checkstop_q or xstop_err_q(1) or xstop_err_q(2); + + +FIR1: entity work.pcq_local_fir2 + generic map( width => fir1_width, + expand_type => expand_type, + impl_lxstop_mchk => false, + use_recov_reset => false, + fir_init => fir1_init, + fir_mask_init => fir1mask_init, + fir_mask_par_init => fir1mask_par_init, + fir_action0_init => fir1act0_init, + fir_action0_par_init => fir1act0_par_init, + fir_action1_init => fir1act1_init, + fir_action1_par_init => fir1act1_par_init + ) + port map + ( nclk => nclk + , vd => vdd + , gd => gnd + , lcb_clkoff_dc_b => lcb_clkoff_dc_b + , lcb_mpw1_dc_b => lcb_mpw1_dc_b + , lcb_mpw2_dc_b => lcb_mpw2_dc_b + , lcb_delay_lclkr_dc => lcb_delay_lclkr_dc + , lcb_act_dis_dc => lcb_act_dis_dc + , lcb_sg_0 => lcb_sg_0 + , lcb_func_slp_sl_thold_0 => lcb_func_slp_sl_thold_0 + , lcb_cfg_slp_sl_thold_0 => lcb_cfg_slp_sl_thold_0 + , mode_scan_siv => bcfg_siv(bcfg_fir1_offset to bcfg_fir1_offset + FIR1_bcfg_size-1) + , mode_scan_sov => bcfg_sov(bcfg_fir1_offset to bcfg_fir1_offset + FIR1_bcfg_size-1) + , func_scan_siv => func_siv(func_fir1_offset to func_fir1_offset + FIR1_func_size-1) + , func_scan_sov => func_sov(func_fir1_offset to func_fir1_offset + FIR1_func_size-1) + , error_in => fir1_errors_q + , xstop_err => fir1_xstop_err + , recov_err => fir1_recov_err + , lxstop_mchk => fir1_lxstop_mchk + , trace_error => fir1_trace_error + , sys_xstop_in => fir1_block_on_checkstop + , recov_reset => tidn + , fir_out => fir1_fir_out + , act0_out => fir1_act0_out + , act1_out => fir1_act1_out + , mask_out => fir1_mask_out + , sc_parity_error_inject => sc_parity_error_inject + , sc_active => sc_active + , sc_wr_q => sc_wr_q + , sc_addr_v => sc_addr_v(10 to 18) + , sc_wdata => sc_wdata(32 to 32+fir1_width-1) + , sc_wparity => sc_wparity + , sc_rdata => fir1_scrdata + , fir_parity_check => fir1_fir_parity_check + ); + + fir1_errors <= + maxRecErrCntrValue_errrpt & xu_pc_err_l2intrf_ecc & + xu_pc_err_l2intrf_ue & xu_pc_err_l2credit_overrun & + xu_pc_err_sprg_ue(0 to 3) & xu_pc_err_regfile_ue(0 to 3) & + fu_pc_err_regfile_ue(0 to 3) & xu_pc_err_nia_miscmpr(0 to 3) & + xu_pc_err_debug_event(0 to 3) & iu_pc_err_ucode_illegal(0 to 3) & + bx_pc_err_inbox_ue & bx_pc_err_outbox_ue & + xu_pc_err_invld_reld & fir_regs_parity_err ; + + + fir1_block_on_checkstop <= an_ac_checkstop_q or xstop_err_q(0) or xstop_err_q(2); + + +FIR2: entity work.pcq_local_fir2 + generic map( width => fir2_width, + expand_type => expand_type, + impl_lxstop_mchk => false, + use_recov_reset => false, + fir_init => fir2_init, + fir_mask_init => fir2mask_init, + fir_mask_par_init => fir2mask_par_init, + fir_action0_init => fir2act0_init, + fir_action0_par_init => fir2act0_par_init, + fir_action1_init => fir2act1_init, + fir_action1_par_init => fir2act1_par_init + ) + port map + ( nclk => nclk + , vd => vdd + , gd => gnd + , lcb_clkoff_dc_b => lcb_clkoff_dc_b + , lcb_mpw1_dc_b => lcb_mpw1_dc_b + , lcb_mpw2_dc_b => lcb_mpw2_dc_b + , lcb_delay_lclkr_dc => lcb_delay_lclkr_dc + , lcb_act_dis_dc => lcb_act_dis_dc + , lcb_sg_0 => lcb_sg_0 + , lcb_func_slp_sl_thold_0 => lcb_func_slp_sl_thold_0 + , lcb_cfg_slp_sl_thold_0 => lcb_cfg_slp_sl_thold_0 + , mode_scan_siv => bcfg_siv(bcfg_fir2_offset to bcfg_fir2_offset + FIR2_bcfg_size-1) + , mode_scan_sov => bcfg_sov(bcfg_fir2_offset to bcfg_fir2_offset + FIR2_bcfg_size-1) + , func_scan_siv => func_siv(func_fir2_offset to func_fir2_offset + FIR2_func_size-1) + , func_scan_sov => func_sov(func_fir2_offset to func_fir2_offset + FIR2_func_size-1) + , error_in => fir2_errors_q + , xstop_err => fir2_xstop_err + , recov_err => fir2_recov_err + , lxstop_mchk => fir2_lxstop_mchk + , trace_error => fir2_trace_error + , sys_xstop_in => fir2_block_on_checkstop + , recov_reset => tidn + , fir_out => fir2_fir_out + , act0_out => fir2_act0_out + , act1_out => fir2_act1_out + , mask_out => fir2_mask_out + , sc_parity_error_inject => sc_parity_error_inject + , sc_active => sc_active + , sc_wr_q => sc_wr_q + , sc_addr_v => sc_addr_v(20 to 28) + , sc_wdata => sc_wdata(32 to 32+fir2_width-1) + , sc_wparity => sc_wparity + , sc_rdata => fir2_scrdata + , fir_parity_check => fir2_fir_parity_check + ); + + + fir2_errors <= + xu_pc_err_mcsr_summary(0 to 3) & + xu_pc_err_ierat_parity & xu_pc_err_derat_parity & + xu_pc_err_tlb_parity & xu_pc_err_tlb_lru_parity & + xu_pc_err_ierat_multihit & xu_pc_err_derat_multihit & + xu_pc_err_tlb_multihit & xu_pc_err_ext_mchk & + xu_pc_err_local_snoop_reject & xu_pc_err_ditc_overrun & + xu_pc_err_mchk_disabled & fir2_errors_q(15 to 19) & + iu_pc_err_icachedir_multihit & xu_pc_err_dcachedir_multihit ; + + + fir2_block_on_checkstop <= an_ac_checkstop_q or xstop_err_q(0) or xstop_err_q(1); + + + scom_err_rpt_held <= sc_reg_par_err_hold(0 to scpar_err_rpt_width-1) & + sc_reg_ack_err_hold(0 to scack_err_rpt_width-1) & + (scpar_err_rpt_width+scack_err_rpt_width to 63 => '0'); + + sc_rdata <= gate_and(sc_addr_v(0), tidn_32 & fir0_fir_out) or + gate_and(sc_addr_v(3), tidn_32 & fir0_act0_out) or + gate_and(sc_addr_v(4), tidn_32 & fir0_act1_out) or + gate_and(sc_addr_v(6), tidn_32 & fir0_mask_out) or + gate_and(sc_addr_v(10), tidn_32 & fir1_fir_out) or + gate_and(sc_addr_v(13), tidn_32 & fir1_act0_out) or + gate_and(sc_addr_v(14), tidn_32 & fir1_act1_out) or + gate_and(sc_addr_v(16), tidn_32 & fir1_mask_out) or + gate_and(sc_addr_v(20), tidn_32 & fir2_fir_out & "0000000000") or + gate_and(sc_addr_v(23), tidn_32 & fir2_act0_out & "0000000000") or + gate_and(sc_addr_v(24), tidn_32 & fir2_act1_out & "0000000000") or + gate_and(sc_addr_v(26), tidn_32 & fir2_mask_out & "0000000000") or + gate_and(sc_addr_v(5), scom_err_rpt_held) or + gate_and(sc_addr_v(19), fir0_fir_out & fir1_fir_out) ; + + + sc_reg_par_err_in <= scom_reg_par_checks & fir0_fir_parity_check & + fir1_fir_parity_check & fir2_fir_parity_check ; + + scom_reg_parity_err <= or_reduce(sc_reg_par_err_out(0 to 6)); + fir_regs_parity_err <= or_reduce(sc_reg_par_err_out(7 to 15)); + + scom_err : entity tri.tri_err_rpt + generic map + ( width => scpar_err_rpt_width + , mask_reset_value => scpar_rpt_reset_value + , inline => false + , expand_type => expand_type + ) + port map + ( vd => vdd + , gd => gnd + , err_d1clk => cfgslp_d1clk + , err_d2clk => cfgslp_d2clk + , err_lclk => cfgslp_lclk + , err_scan_in => bcfg_siv(bcfg_erpt1_hld_offset to bcfg_erpt1_hld_offset + scpar_err_rpt_width-1) + , err_scan_out => bcfg_sov(bcfg_erpt1_hld_offset to bcfg_erpt1_hld_offset + scpar_err_rpt_width-1) + , mode_dclk => cfg_slat_d2clk + , mode_lclk => cfg_slat_lclk + , mode_scan_in => bcfg_siv(bcfg_erpt1_msk_offset to bcfg_erpt1_msk_offset + scpar_err_rpt_width-1) + , mode_scan_out => bcfg_sov(bcfg_erpt1_msk_offset to bcfg_erpt1_msk_offset + scpar_err_rpt_width-1) + , err_in => sc_reg_par_err_in + , err_out => sc_reg_par_err_out + , hold_out => sc_reg_par_err_hold + ); + + sc_reg_ack_err_in <= scom_ack_error & scom_sat_fsm_error; + scom_reg_ack_err <= or_reduce(sc_reg_ack_err_out); + + sc_ack_err : entity tri.tri_err_rpt + generic map + ( width => scack_err_rpt_width + , mask_reset_value => scack_rpt_reset_value + , inline => false + , expand_type => expand_type + ) + port map + ( vd => vdd + , gd => gnd + , err_d1clk => cfgslp_d1clk + , err_d2clk => cfgslp_d2clk + , err_lclk => cfgslp_lclk + , err_scan_in => bcfg_siv(bcfg_erpt2_hld_offset to bcfg_erpt2_hld_offset + scack_err_rpt_width-1) + , err_scan_out => bcfg_sov(bcfg_erpt2_hld_offset to bcfg_erpt2_hld_offset + scack_err_rpt_width-1) + , mode_dclk => cfg_slat_d2clk + , mode_lclk => cfg_slat_lclk + , mode_scan_in => bcfg_siv(bcfg_erpt2_msk_offset to bcfg_erpt2_msk_offset + scack_err_rpt_width-1) + , mode_scan_out => bcfg_sov(bcfg_erpt2_msk_offset to bcfg_erpt2_msk_offset + scack_err_rpt_width-1) + , err_in => sc_reg_ack_err_in + , err_out => sc_reg_ack_err_out + , hold_out => sc_reg_ack_err_hold + ); + + + misc_dir_err : entity tri.tri_direct_err_rpt + generic map + ( width => 1 + , expand_type => expand_type + ) + port map + ( vd => vdd + , gd => gnd + , err_in(0) => rg_rg_maxRecErrCntrValue + , err_out(0) => maxRecErrCntrValue_errrpt + ); + + + fir0_recoverable_errors <= fir0_errors_q and fir0_act1_out and not fir0_mask_out; + fir0_recov_err_in(0) <= or_reduce(fir0_recoverable_errors); + fir0_recov_err_in(1) <= fir0_recov_err_q(0); + fir0_recov_err_pulse <= fir0_recov_err_q(0) and not fir0_recov_err_q(1); + + + fir1_recoverable_errors <= fir1_errors_q and fir1_act1_out and not fir1_mask_out; + fir1_recov_err_in(0) <= or_reduce(fir1_recoverable_errors(1 to fir1_width-1)); + fir1_recov_err_in(1) <= fir1_recov_err_q(0); + fir1_recov_err_pulse <= fir1_recov_err_q(0) and not fir1_recov_err_q(1); + + + fir2_recoverable_errors <= fir2_errors_q and fir2_act1_out and not fir2_mask_out; + fir2_recov_err_in(0) <= or_reduce(fir2_recoverable_errors); + fir2_recov_err_in(1) <= fir2_recov_err_q(0); + fir2_recov_err_pulse <= fir2_recov_err_q(0) and not fir2_recov_err_q(1); + + + fir0_enabled_checkstops <= fir0_fir_out and fir0_act0_out and not fir0_act1_out and not fir0_mask_out; + fir1_enabled_checkstops <= fir1_fir_out and fir1_act0_out and not fir1_act1_out and not fir1_mask_out; + fir2_enabled_checkstops <= fir2_fir_out(4 to fir2_width-1) and + fir2_act0_out(4 to fir2_width-1) and not + fir2_act1_out(4 to fir2_width-1) and not + fir2_mask_out(4 to fir2_width-1) ; + + xstop_err_common <= or_reduce(fir0_enabled_checkstops(32 to 35) & fir0_enabled_checkstops(48 to 51)) or + or_reduce(fir1_enabled_checkstops(32 to 35) & fir1_enabled_checkstops(60 to 63)) or + or_reduce(fir2_enabled_checkstops(52 to 53)); + + xstop_err_per_thread(0) <= fir0_enabled_checkstops(36) or fir0_enabled_checkstops(40) or + fir0_enabled_checkstops(44) or fir0_enabled_checkstops(52) or + fir0_enabled_checkstops(56) or fir0_enabled_checkstops(60) or + fir1_enabled_checkstops(36) or fir1_enabled_checkstops(40) or + fir1_enabled_checkstops(44) or fir1_enabled_checkstops(48) or + fir1_enabled_checkstops(52) or fir1_enabled_checkstops(56) or + (fir2_fir_out(0) and or_reduce(fir2_enabled_checkstops(36 to 51))) or + xstop_err_common; + + xstop_err_per_thread(1) <= fir0_enabled_checkstops(37) or fir0_enabled_checkstops(41) or + fir0_enabled_checkstops(45) or fir0_enabled_checkstops(53) or + fir0_enabled_checkstops(57) or fir0_enabled_checkstops(61) or + fir1_enabled_checkstops(37) or fir1_enabled_checkstops(41) or + fir1_enabled_checkstops(45) or fir1_enabled_checkstops(49) or + fir1_enabled_checkstops(53) or fir1_enabled_checkstops(57) or + (fir2_fir_out(1) and or_reduce(fir2_enabled_checkstops(36 to 51))) or + xstop_err_common; + + xstop_err_per_thread(2) <= fir0_enabled_checkstops(38) or fir0_enabled_checkstops(42) or + fir0_enabled_checkstops(46) or fir0_enabled_checkstops(54) or + fir0_enabled_checkstops(58) or fir0_enabled_checkstops(62) or + fir1_enabled_checkstops(38) or fir1_enabled_checkstops(42) or + fir1_enabled_checkstops(46) or fir1_enabled_checkstops(50) or + fir1_enabled_checkstops(54) or fir1_enabled_checkstops(58) or + (fir2_fir_out(2) and or_reduce(fir2_enabled_checkstops(36 to 51))) or + xstop_err_common; + + xstop_err_per_thread(3) <= fir0_enabled_checkstops(39) or fir0_enabled_checkstops(43) or + fir0_enabled_checkstops(47) or fir0_enabled_checkstops(55) or + fir0_enabled_checkstops(59) or fir0_enabled_checkstops(63) or + fir1_enabled_checkstops(39) or fir1_enabled_checkstops(43) or + fir1_enabled_checkstops(47) or fir1_enabled_checkstops(51) or + fir1_enabled_checkstops(55) or fir1_enabled_checkstops(59) or + (fir2_fir_out(3) and or_reduce(fir2_enabled_checkstops(36 to 51))) or + xstop_err_common; + + xstop_err_int(0) <= fir0_xstop_err; + xstop_err_int(1) <= fir1_xstop_err; + xstop_err_int(2) <= fir2_xstop_err; + + rg_rg_any_fir_xstop <= or_reduce(xstop_err_int(0 to 2)); + + lxstop_err_int(0) <= fir0_lxstop_mchk; + lxstop_err_int(1) <= fir1_lxstop_mchk; + lxstop_err_int(2) <= fir2_lxstop_mchk; + + block_xstop_in_ram_mode <= rg_rg_xstop_report_ovride and rg_rg_ram_mode; + xstop_out_d(0 to 2) <= gate_and(not block_xstop_in_ram_mode, xstop_err_int(0 to 2)); + + injoff_icache_parity <= fir0_errors_q(0); + injoff_icachedir_parity <= fir0_errors_q(1); + injoff_dcache_parity <= fir0_errors_q(2); + injoff_dcachedir_parity <= fir0_errors_q(3); + injoff_sprg_ecc <= or_reduce(fir0_errors_q(4 to 7)); + injoff_xuregfile_parity <= or_reduce(fir0_errors_q(8 to 11)); + injoff_furegfile_parity <= or_reduce(fir0_errors_q(12 to 15)); + injoff_inbox_ecc <= fir0_errors_q(16); + injoff_outbox_ecc <= fir0_errors_q(17); + injoff_scomreg_parity <= fir0_errors_q(18); + injoff_wdt_reset <= or_reduce(fir0_errors_q(20 to 23)); + injoff_llbust_attempt <= or_reduce(fir0_errors_q(24 to 27)); + injoff_llbust_failed <= or_reduce(fir0_errors_q(28 to 31)); + injoff_icachedir_multihit <= fir2_errors_q(20); + injoff_dcachedir_multihit <= fir2_errors_q(21); + + + error_inject_shutoff <= injoff_icache_parity & injoff_icachedir_parity & + injoff_dcache_parity & injoff_dcachedir_parity & + injoff_xuregfile_parity & injoff_furegfile_parity & + injoff_sprg_ecc & injoff_inbox_ecc & + injoff_outbox_ecc & injoff_llbust_attempt & + injoff_llbust_failed & injoff_wdt_reset & + injoff_scomreg_parity & injoff_icachedir_multihit & + injoff_dcachedir_multihit ; + + + ac_an_special_attn <= atten_instr_q(0 to 3); + + ac_an_checkstop <= xstop_out_q(0 to 2); + + ac_an_local_checkstop <= lxstop_err_q(0 to 2); + + ac_an_recov_err <= fir0_recov_err & fir1_recov_err & fir2_recov_err; + + ac_an_trace_error <= fir0_trace_error or fir1_trace_error or fir2_trace_error; + + rg_rg_xstop_err <= xstop_err_per_thread(0 to 3); + + rg_rg_ram_mode_xstop <= rg_rg_ram_mode and (fir0_xstop_err or fir1_xstop_err or fir2_xstop_err); + + rg_rg_errinj_shutoff <= error_inject_shutoff; + + rg_rg_gateRecErrCntr <= fir0_recov_err_pulse or fir1_recov_err_pulse or fir2_recov_err_pulse; + + pc_xu_cache_par_err_event <= or_reduce(fir0_errors_q(0 to 3)); + + + dbg_fir0_err <= fir0_errors_q; + + dbg_fir1_err <= fir1_errors_q(0 to 30); + + dbg_fir2_err <= fir2_errors_q; + + dbg_fir_misc <= atten_instr_q(0 to 3) & + fir0_xstop_err & + fir1_xstop_err & + fir2_xstop_err & + fir0_recov_err & + fir1_recov_err & + fir2_recov_err & + sc_reg_par_err_out_q(0 to 15) & + sc_reg_ack_err_out_q(0 to 1) & + xstop_err_per_thread(0 to 3) & + block_xstop_in_ram_mode & + fir0_recov_err_pulse & + fir1_recov_err_pulse & + fir2_recov_err_pulse ; + + + + atten_instr : entity tri.tri_nlat_scan + generic map( width => attent_func_size, init => "0000", expand_type => expand_type ) + port map + ( d1clk => func_d1clk + , vd => vdd + , gd => gnd + , lclk => func_lclk + , d2clk => func_d2clk + , scan_in => func_siv(func_attent_offset to func_attent_offset + attent_func_size-1) + , scan_out => func_sov(func_attent_offset to func_attent_offset + attent_func_size-1) + , din => xu_pc_err_attention_instr + , q => atten_instr_q + ); + + error_out : entity tri.tri_nlat_scan + generic map( width => errout_func_size, init => x"00000000" & "00", expand_type => expand_type ) + port map + ( d1clk => func_d1clk + , vd => vdd + , gd => gnd + , lclk => func_lclk + , d2clk => func_d2clk + , scan_in => func_siv(func_errout_offset to func_errout_offset + errout_func_size-1) + , scan_out => func_sov(func_errout_offset to func_errout_offset + errout_func_size-1) + , din(0 to 2) => xstop_err_int + , din(3 to 5) => xstop_out_d + , din(6 to 8) => lxstop_err_int + , din(9 to 10) => fir0_recov_err_in + , din(11 to 12) => fir1_recov_err_in + , din(13 to 14) => fir2_recov_err_in + , din(15) => an_ac_checkstop + , din(16 to 31) => sc_reg_par_err_out + , din(32 to 33) => sc_reg_ack_err_out + , q(0 to 2) => xstop_err_q + , q(3 to 5) => xstop_out_q + , q(6 to 8) => lxstop_err_q + , q(9 to 10) => fir0_recov_err_q + , q(11 to 12) => fir1_recov_err_q + , q(13 to 14) => fir2_recov_err_q + , q(15) => an_ac_checkstop_q + , q(16 to 31) => sc_reg_par_err_out_q + , q(32 to 33) => sc_reg_ack_err_out_q + ); + + f0err_out : entity tri.tri_nlat_scan + generic map( width => fir0_width, init => fir0_init, expand_type => expand_type ) + port map + ( d1clk => func_d1clk + , vd => vdd + , gd => gnd + , lclk => func_lclk + , d2clk => func_d2clk + , scan_in => func_siv(func_f0err_offset to func_f0err_offset + fir0_width-1) + , scan_out => func_sov(func_f0err_offset to func_f0err_offset + fir0_width-1) + , din => fir0_errors + , q => fir0_errors_q + ); + + f1err_out : entity tri.tri_nlat_scan + generic map( width => fir1_width, init => fir1_init, expand_type => expand_type ) + port map + ( d1clk => func_d1clk + , vd => vdd + , gd => gnd + , lclk => func_lclk + , d2clk => func_d2clk + , scan_in => func_siv(func_f1err_offset to func_f1err_offset + fir1_width-1) + , scan_out => func_sov(func_f1err_offset to func_f1err_offset + fir1_width-1) + , din => fir1_errors + , q => fir1_errors_q + ); + + f2err_out : entity tri.tri_nlat_scan + generic map( width => fir2_width, init => fir2_init, expand_type => expand_type ) + port map + ( d1clk => func_d1clk + , vd => vdd + , gd => gnd + , lclk => func_lclk + , d2clk => func_d2clk + , scan_in => func_siv(func_f2err_offset to func_f2err_offset + fir2_width-1) + , scan_out => func_sov(func_f2err_offset to func_f2err_offset + fir2_width-1) + , din => fir2_errors + , q => fir2_errors_q + ); + + + func_lcbor: entity tri.tri_lcbor + generic map (expand_type => expand_type ) + port map( clkoff_b => lcb_clkoff_dc_b, + thold => lcb_func_slp_sl_thold_0, + sg => lcb_sg_0, + act_dis => lcb_act_dis_dc, + forcee => func_force, + thold_b => func_thold_b + ); + + func_lcb: entity tri.tri_lcbnd + generic map (expand_type => expand_type ) + port map( act => tiup, + vd => vdd, + gd => gnd, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + nclk => nclk, + forcee => func_force, + sg => lcb_sg_0, + thold_b => func_thold_b, + d1clk => func_d1clk, + d2clk => func_d2clk, + lclk => func_lclk + ); + + + bcfg_siv(0 to bcfg_right) <= bcfg_scan_in & bcfg_sov(0 to bcfg_right-1); + bcfg_scan_out <= bcfg_sov(bcfg_right); + + func_siv(0 to func_right) <= func_scan_in & func_sov(0 to func_right-1); + func_scan_out <= func_sov(func_right); + + +end pcq_regs_fir; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/pcq_spr.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/pcq_spr.vhdl new file mode 100644 index 0000000..bfd3aaa --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/pcq_spr.vhdl @@ -0,0 +1,777 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee; +use ieee.std_logic_1164.all; +library ibm; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; +library support; +use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + + +entity pcq_spr is +generic(regmode : integer := 6; + expand_type : integer := 2 ); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + scan_dis_dc_b : in std_ulogic; + lcb_clkoff_dc_b : in std_ulogic; + lcb_mpw1_dc_b : in std_ulogic; + lcb_mpw2_dc_b : in std_ulogic; + lcb_delay_lclkr_dc : in std_ulogic; + lcb_act_dis_dc : in std_ulogic; + pc_pc_func_sl_thold_0 : in std_ulogic; + pc_pc_sg_0 : in std_ulogic; + func_scan_in : in std_ulogic; + func_scan_out : out std_ulogic; + slowspr_val_in : in std_ulogic; + slowspr_rw_in : in std_ulogic; + slowspr_etid_in : in std_ulogic_vector(0 to 1); + slowspr_addr_in : in std_ulogic_vector(0 to 9); + slowspr_data_in : in std_ulogic_vector(64-(2**regmode) to 63); + slowspr_done_in : in std_ulogic; + slowspr_val_out : out std_ulogic; + slowspr_rw_out : out std_ulogic; + slowspr_etid_out : out std_ulogic_vector(0 to 1); + slowspr_addr_out : out std_ulogic_vector(0 to 9); + slowspr_data_out : out std_ulogic_vector(64-(2**regmode) to 63); + slowspr_done_out : out std_ulogic; + sp_rg_trace_bus_enable : out std_ulogic; + pc_fu_instr_trace_mode : out std_ulogic; + pc_fu_instr_trace_tid : out std_ulogic_vector(0 to 1); + pc_xu_instr_trace_mode : out std_ulogic; + pc_xu_instr_trace_tid : out std_ulogic_vector(0 to 1); + pc_fu_event_count_mode : out std_ulogic_vector(0 to 2); + pc_iu_event_count_mode : out std_ulogic_vector(0 to 2); + pc_mm_event_count_mode : out std_ulogic_vector(0 to 2); + pc_xu_event_count_mode : out std_ulogic_vector(0 to 2); + pc_fu_event_mux_ctrls : out std_ulogic_vector(0 to 31); + pc_iu_event_mux_ctrls : out std_ulogic_vector(0 to 47); + pc_mm_event_mux_ctrls : out std_ulogic_vector(0 to 39); + pc_xu_event_mux_ctrls : out std_ulogic_vector(0 to 47); + pc_xu_lsu_event_mux_ctrls : out std_ulogic_vector(0 to 47); + sp_db_event_mux_ctrls : out std_ulogic_vector(0 to 23); + pc_fu_event_bus_enable : out std_ulogic; + pc_iu_event_bus_enable : out std_ulogic; + pc_rp_event_bus_enable : out std_ulogic; + pc_xu_event_bus_enable : out std_ulogic; + sp_db_event_bus_enable : out std_ulogic; + dbg_spr : out std_ulogic_vector(0 to 46) +); + +-- synopsys translate_off + + +-- synopsys translate_on +end pcq_spr; + + +architecture pcq_spr of pcq_spr is +constant cesr_size : positive := 32; +constant aesr_size : positive := 32; +constant iesr1_size : positive := 24; +constant iesr2_size : positive := 24; +constant mesr1_size : positive := 20; +constant mesr2_size : positive := 20; +constant xesr1_size : positive := 24; +constant xesr2_size : positive := 24; +constant xesr3_size : positive := 24; +constant xesr4_size : positive := 24; +constant pc_data_size : positive := 2**regmode; + +constant slowspr_val_offset : natural := 0; +constant slowspr_rw_offset : natural := slowspr_val_offset + 1; +constant slowspr_etid_offset : natural := slowspr_rw_offset + 1; +constant slowspr_addr_offset : natural := slowspr_etid_offset + 2; +constant slowspr_data_offset : natural := slowspr_addr_offset + 10; +constant slowspr_done_offset : natural := slowspr_data_offset + 2**regmode; +constant pc_val_offset : natural := slowspr_done_offset + 1; +constant pc_rw_offset : natural := pc_val_offset + 1; +constant pc_etid_offset : natural := pc_rw_offset + 1; +constant pc_addr_offset : natural := pc_etid_offset + 2; +constant pc_data_offset : natural := pc_addr_offset + 10; +constant pc_done_offset : natural := pc_data_offset + 2**regmode; +constant cesr_offset : natural := pc_done_offset + 1; +constant aesr_offset : natural := cesr_offset + cesr_size; +constant iesr1_offset : natural := aesr_offset + aesr_size; +constant iesr2_offset : natural := iesr1_offset + iesr1_size; +constant mesr1_offset : natural := iesr2_offset + iesr2_size; +constant mesr2_offset : natural := mesr1_offset + mesr1_size; +constant xesr1_offset : natural := mesr2_offset + mesr2_size; +constant xesr2_offset : natural := xesr1_offset + xesr1_size; +constant xesr3_offset : natural := xesr2_offset + xesr2_size; +constant xesr4_offset : natural := xesr3_offset + xesr3_size; +constant func_right : natural := xesr4_offset + xesr4_size - 1; + +constant CESR_MASK : std_ulogic_vector(32 to 63) := "11111111111111111111111111111111"; +constant EVENTMUX_32_MASK : std_ulogic_vector(32 to 63) := "11111111111111111111111111111111"; +constant EVENTMUX_64_MASK : std_ulogic_vector(32 to 63) := "11111111111111111111000000000000"; +constant EVENTMUX_128_MASK : std_ulogic_vector(32 to 63) := "11111111111111111111111100000000"; + +signal slowspr_val_d : std_ulogic; +signal slowspr_val_l2 : std_ulogic; +signal slowspr_rw_d : std_ulogic; +signal slowspr_rw_l2 : std_ulogic; +signal slowspr_etid_d : std_ulogic_vector(0 to 1); +signal slowspr_etid_l2 : std_ulogic_vector(0 to 1); +signal slowspr_addr_d : std_ulogic_vector(0 to 9); +signal slowspr_addr_l2 : std_ulogic_vector(0 to 9); +signal slowspr_data_d : std_ulogic_vector(64-(2**regmode) to 63); +signal slowspr_data_l2 : std_ulogic_vector(64-(2**regmode) to 63); +signal slowspr_done_d : std_ulogic; +signal slowspr_done_l2 : std_ulogic; + +signal pc_val_d : std_ulogic; +signal pc_val_l2 : std_ulogic; +signal pc_rw_d : std_ulogic; +signal pc_rw_l2 : std_ulogic; +signal pc_etid_d : std_ulogic_vector(0 to 1); +signal pc_etid_l2 : std_ulogic_vector(0 to 1); +signal pc_addr_d : std_ulogic_vector(0 to 9); +signal pc_addr_l2 : std_ulogic_vector(0 to 9); +signal pc_done_d : std_ulogic; +signal pc_done_l2 : std_ulogic; +signal pc_data_d : std_ulogic_vector(64-(2**regmode) to 63); +signal pc_data_l2 : std_ulogic_vector(64-(2**regmode) to 63); +signal pc_done_int : std_ulogic; +signal pc_data_int : std_ulogic_vector(64-(2**regmode) to 63); +signal pc_reg_data : std_ulogic_vector(32 to 63); + +signal cesr_sel : std_ulogic; +signal cesr_wren : std_ulogic; +signal cesr_rden : std_ulogic; +signal cesr_d : std_ulogic_vector(32 to 32+cesr_size-1); +signal cesr_l2 : std_ulogic_vector(32 to 32+cesr_size-1); +signal cesr_out : std_ulogic_vector(32 to 63); + +signal aesr_sel : std_ulogic; +signal aesr_wren : std_ulogic; +signal aesr_rden : std_ulogic; +signal aesr_d : std_ulogic_vector(32 to 32+aesr_size-1); +signal aesr_l2 : std_ulogic_vector(32 to 32+aesr_size-1); +signal aesr_out : std_ulogic_vector(32 to 63); + +signal iesr1_sel : std_ulogic; +signal iesr1_wren : std_ulogic; +signal iesr1_rden : std_ulogic; +signal iesr1_d : std_ulogic_vector(32 to 32+iesr1_size-1); +signal iesr1_l2 : std_ulogic_vector(32 to 32+iesr1_size-1); +signal iesr1_out : std_ulogic_vector(32 to 63); + +signal iesr2_sel : std_ulogic; +signal iesr2_wren : std_ulogic; +signal iesr2_rden : std_ulogic; +signal iesr2_d : std_ulogic_vector(32 to 32+iesr2_size-1); +signal iesr2_l2 : std_ulogic_vector(32 to 32+iesr2_size-1); +signal iesr2_out : std_ulogic_vector(32 to 63); + +signal mesr1_sel : std_ulogic; +signal mesr1_wren : std_ulogic; +signal mesr1_rden : std_ulogic; +signal mesr1_d : std_ulogic_vector(32 to 32+mesr1_size-1); +signal mesr1_l2 : std_ulogic_vector(32 to 32+mesr1_size-1); +signal mesr1_out : std_ulogic_vector(32 to 63); + +signal mesr2_sel : std_ulogic; +signal mesr2_wren : std_ulogic; +signal mesr2_rden : std_ulogic; +signal mesr2_d : std_ulogic_vector(32 to 32+mesr2_size-1); +signal mesr2_l2 : std_ulogic_vector(32 to 32+mesr2_size-1); +signal mesr2_out : std_ulogic_vector(32 to 63); + +signal xesr1_sel : std_ulogic; +signal xesr1_wren : std_ulogic; +signal xesr1_rden : std_ulogic; +signal xesr1_d : std_ulogic_vector(32 to 32+xesr1_size-1); +signal xesr1_l2 : std_ulogic_vector(32 to 32+xesr1_size-1); +signal xesr1_out : std_ulogic_vector(32 to 63); + +signal xesr2_sel : std_ulogic; +signal xesr2_wren : std_ulogic; +signal xesr2_rden : std_ulogic; +signal xesr2_d : std_ulogic_vector(32 to 32+xesr2_size-1); +signal xesr2_l2 : std_ulogic_vector(32 to 32+xesr2_size-1); +signal xesr2_out : std_ulogic_vector(32 to 63); + +signal xesr3_sel : std_ulogic; +signal xesr3_wren : std_ulogic; +signal xesr3_rden : std_ulogic; +signal xesr3_d : std_ulogic_vector(32 to 32+xesr3_size-1); +signal xesr3_l2 : std_ulogic_vector(32 to 32+xesr3_size-1); +signal xesr3_out : std_ulogic_vector(32 to 63); + +signal xesr4_sel : std_ulogic; +signal xesr4_wren : std_ulogic; +signal xesr4_rden : std_ulogic; +signal xesr4_d : std_ulogic_vector(32 to 32+xesr4_size-1); +signal xesr4_l2 : std_ulogic_vector(32 to 32+xesr4_size-1); +signal xesr4_out : std_ulogic_vector(32 to 63); + +signal tiup : std_ulogic; +signal pc_pc_func_sl_thold_0_b : std_ulogic; +signal force_func : std_ulogic; +signal func_siv : std_ulogic_vector(0 to func_right); +signal func_sov : std_ulogic_vector(0 to func_right); + + +begin + +tiup <= '1'; + +slowspr_val_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_pc_func_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(slowspr_val_offset), + scout => func_sov(slowspr_val_offset), + din => slowspr_val_d, + dout => slowspr_val_l2); + +slowspr_rw_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => slowspr_val_d, + thold_b => pc_pc_func_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(slowspr_rw_offset), + scout => func_sov(slowspr_rw_offset), + din => slowspr_rw_d, + dout => slowspr_rw_l2); + +slowspr_etid_reg: tri_rlmreg_p + generic map (width => slowspr_etid_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => slowspr_val_d, + thold_b => pc_pc_func_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(slowspr_etid_offset to slowspr_etid_offset + slowspr_etid_l2'length-1), + scout => func_sov(slowspr_etid_offset to slowspr_etid_offset + slowspr_etid_l2'length-1), + din => slowspr_etid_d, + dout => slowspr_etid_l2); + +slowspr_addr_reg: tri_rlmreg_p + generic map (width => slowspr_addr_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => slowspr_val_d, + thold_b => pc_pc_func_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(slowspr_addr_offset to slowspr_addr_offset + slowspr_addr_l2'length-1), + scout => func_sov(slowspr_addr_offset to slowspr_addr_offset + slowspr_addr_l2'length-1), + din => slowspr_addr_d, + dout => slowspr_addr_l2); + +slowspr_data_reg: tri_rlmreg_p + generic map (width => slowspr_data_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => slowspr_val_d, + thold_b => pc_pc_func_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(slowspr_data_offset to slowspr_data_offset + slowspr_data_l2'length-1), + scout => func_sov(slowspr_data_offset to slowspr_data_offset + slowspr_data_l2'length-1), + din => slowspr_data_d, + dout => slowspr_data_l2); + +slowspr_done_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => slowspr_val_d, + thold_b => pc_pc_func_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(slowspr_done_offset), + scout => func_sov(slowspr_done_offset), + din => slowspr_done_d, + dout => slowspr_done_l2); + +pc_val_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_pc_func_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(pc_val_offset), + scout => func_sov(pc_val_offset), + din => pc_val_d, + dout => pc_val_l2); + +pc_rw_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => pc_val_d, + thold_b => pc_pc_func_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(pc_rw_offset), + scout => func_sov(pc_rw_offset), + din => pc_rw_d, + dout => pc_rw_l2); + +pc_etid_reg: tri_rlmreg_p + generic map (width => pc_etid_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => pc_val_d, + thold_b => pc_pc_func_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(pc_etid_offset to pc_etid_offset + pc_etid_l2'length-1), + scout => func_sov(pc_etid_offset to pc_etid_offset + pc_etid_l2'length-1), + din => pc_etid_d, + dout => pc_etid_l2); + +pc_addr_reg: tri_rlmreg_p + generic map (width => pc_addr_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => pc_val_d, + thold_b => pc_pc_func_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(pc_addr_offset to pc_addr_offset + pc_addr_l2'length-1), + scout => func_sov(pc_addr_offset to pc_addr_offset + pc_addr_l2'length-1), + din => pc_addr_d, + dout => pc_addr_l2); + +pc_data_reg: tri_rlmreg_p + generic map (width => pc_data_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => pc_val_d, + thold_b => pc_pc_func_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(pc_data_offset to pc_data_offset + pc_data_size-1), + scout => func_sov(pc_data_offset to pc_data_offset + pc_data_size-1), + din => pc_data_d, + dout => pc_data_l2); + +pc_done_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_pc_func_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(pc_done_offset), + scout => func_sov(pc_done_offset), + din => pc_done_d, + dout => pc_done_l2); + +cesr_reg: tri_ser_rlmreg_p + generic map (width => cesr_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cesr_wren, + thold_b => pc_pc_func_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(cesr_offset to cesr_offset + cesr_size-1), + scout => func_sov(cesr_offset to cesr_offset + cesr_size-1), + din => cesr_d, + dout => cesr_l2); + +aesr_reg: tri_ser_rlmreg_p + generic map (width => aesr_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => aesr_wren, + thold_b => pc_pc_func_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(aesr_offset to aesr_offset + aesr_size-1), + scout => func_sov(aesr_offset to aesr_offset + aesr_size-1), + din => aesr_d, + dout => aesr_l2); + +iesr1_reg: tri_ser_rlmreg_p + generic map (width => iesr1_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iesr1_wren, + thold_b => pc_pc_func_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(iesr1_offset to iesr1_offset + iesr1_size-1), + scout => func_sov(iesr1_offset to iesr1_offset + iesr1_size-1), + din => iesr1_d, + dout => iesr1_l2); + +iesr2_reg: tri_ser_rlmreg_p + generic map (width => iesr2_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iesr2_wren, + thold_b => pc_pc_func_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(iesr2_offset to iesr2_offset + iesr2_size-1), + scout => func_sov(iesr2_offset to iesr2_offset + iesr2_size-1), + din => iesr2_d, + dout => iesr2_l2); + +mesr1_reg: tri_ser_rlmreg_p + generic map (width => mesr1_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => mesr1_wren, + thold_b => pc_pc_func_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(mesr1_offset to mesr1_offset + mesr1_size-1), + scout => func_sov(mesr1_offset to mesr1_offset + mesr1_size-1), + din => mesr1_d, + dout => mesr1_l2); + +mesr2_reg: tri_ser_rlmreg_p + generic map (width => mesr2_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => mesr2_wren, + thold_b => pc_pc_func_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(mesr2_offset to mesr2_offset + mesr2_size-1), + scout => func_sov(mesr2_offset to mesr2_offset + mesr2_size-1), + din => mesr2_d, + dout => mesr2_l2); + +xesr1_reg: tri_ser_rlmreg_p + generic map (width => xesr1_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xesr1_wren, + thold_b => pc_pc_func_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(xesr1_offset to xesr1_offset + xesr1_size-1), + scout => func_sov(xesr1_offset to xesr1_offset + xesr1_size-1), + din => xesr1_d, + dout => xesr1_l2); + +xesr2_reg: tri_ser_rlmreg_p + generic map (width => xesr2_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xesr2_wren, + thold_b => pc_pc_func_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(xesr2_offset to xesr2_offset + xesr2_size-1), + scout => func_sov(xesr2_offset to xesr2_offset + xesr2_size-1), + din => xesr2_d, + dout => xesr2_l2); + +xesr3_reg: tri_ser_rlmreg_p + generic map (width => xesr3_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xesr3_wren, + thold_b => pc_pc_func_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(xesr3_offset to xesr3_offset + xesr3_size-1), + scout => func_sov(xesr3_offset to xesr3_offset + xesr3_size-1), + din => xesr3_d, + dout => xesr3_l2); + +xesr4_reg: tri_ser_rlmreg_p + generic map (width => xesr4_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xesr4_wren, + thold_b => pc_pc_func_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(xesr4_offset to xesr4_offset + xesr4_size-1), + scout => func_sov(xesr4_offset to xesr4_offset + xesr4_size-1), + din => xesr4_d, + dout => xesr4_l2); + +slowspr_val_d <= slowspr_val_in; +slowspr_rw_d <= slowspr_rw_in; +slowspr_etid_d <= slowspr_etid_in; +slowspr_addr_d <= slowspr_addr_in; +slowspr_data_d <= slowspr_data_in; +slowspr_done_d <= slowspr_done_in; + +pc_val_d <= slowspr_val_l2; +pc_rw_d <= slowspr_rw_l2; +pc_etid_d <= slowspr_etid_l2; +pc_addr_d <= slowspr_addr_l2; +pc_data_d <= slowspr_data_l2 or pc_data_int; +pc_done_d <= slowspr_done_l2 or pc_done_int; + + +slowspr_val_out <= pc_val_l2; +slowspr_rw_out <= pc_rw_l2; +slowspr_etid_out <= pc_etid_l2; +slowspr_addr_out <= pc_addr_l2; +slowspr_data_out <= pc_data_l2; +slowspr_done_out <= pc_done_l2; + +sp_rg_trace_bus_enable <= cesr_out(36); + +pc_fu_instr_trace_mode <= cesr_out(37); +pc_fu_instr_trace_tid <= cesr_out(38 to 39); +pc_xu_instr_trace_mode <= cesr_out(37); +pc_xu_instr_trace_tid <= cesr_out(38 to 39); + +pc_fu_event_count_mode <= cesr_out(33 to 35); +pc_iu_event_count_mode <= cesr_out(33 to 35); +pc_mm_event_count_mode <= cesr_out(33 to 35); +pc_xu_event_count_mode <= cesr_out(33 to 35); + +pc_fu_event_bus_enable <= cesr_out(32); +pc_iu_event_bus_enable <= cesr_out(32); +pc_rp_event_bus_enable <= cesr_out(32); +pc_xu_event_bus_enable <= cesr_out(32); +sp_db_event_bus_enable <= cesr_out(32); + +pc_fu_event_mux_ctrls <= aesr_out(32 to 63); +pc_iu_event_mux_ctrls <= iesr1_out(32 to 55) & iesr2_out(32 to 55); +pc_mm_event_mux_ctrls <= mesr1_out(32 to 51) & mesr2_out(32 to 51); +pc_xu_event_mux_ctrls <= xesr1_out(32 to 55) & xesr2_out(32 to 55); +pc_xu_lsu_event_mux_ctrls <= xesr3_out(32 to 55) & xesr4_out(32 to 55); +sp_db_event_mux_ctrls <= cesr_out(40 to 63); + + +cesr_sel <= slowspr_val_l2 and slowspr_addr_l2 = "1110010000"; +aesr_sel <= slowspr_val_l2 and slowspr_addr_l2 = "1110010001"; +iesr1_sel <= slowspr_val_l2 and slowspr_addr_l2 = "1110010010"; +iesr2_sel <= slowspr_val_l2 and slowspr_addr_l2 = "1110010011"; +mesr1_sel <= slowspr_val_l2 and slowspr_addr_l2 = "1110010100"; +mesr2_sel <= slowspr_val_l2 and slowspr_addr_l2 = "1110010101"; +xesr1_sel <= slowspr_val_l2 and slowspr_addr_l2 = "1110010110"; +xesr2_sel <= slowspr_val_l2 and slowspr_addr_l2 = "1110010111"; +xesr3_sel <= slowspr_val_l2 and slowspr_addr_l2 = "1110011000"; +xesr4_sel <= slowspr_val_l2 and slowspr_addr_l2 = "1110011001"; + +pc_done_int <= cesr_sel or aesr_sel or iesr1_sel or iesr2_sel or + mesr1_sel or mesr2_sel or xesr1_sel or xesr2_sel or + xesr3_sel or xesr4_sel; + + +cesr_wren <= cesr_sel and slowspr_rw_l2 = '0'; +aesr_wren <= aesr_sel and slowspr_rw_l2 = '0'; +iesr1_wren <= iesr1_sel and slowspr_rw_l2 = '0'; +iesr2_wren <= iesr2_sel and slowspr_rw_l2 = '0'; +mesr1_wren <= mesr1_sel and slowspr_rw_l2 = '0'; +mesr2_wren <= mesr2_sel and slowspr_rw_l2 = '0'; +xesr1_wren <= xesr1_sel and slowspr_rw_l2 = '0'; +xesr2_wren <= xesr2_sel and slowspr_rw_l2 = '0'; +xesr3_wren <= xesr3_sel and slowspr_rw_l2 = '0'; +xesr4_wren <= xesr4_sel and slowspr_rw_l2 = '0'; + +cesr_d <= CESR_MASK(32 to 32+cesr_size-1) and slowspr_data_l2(32 to 32+cesr_size-1); +aesr_d <= EVENTMUX_32_MASK(32 to 32+aesr_size-1) and slowspr_data_l2(32 to 32+aesr_size-1); +iesr1_d <= EVENTMUX_128_MASK(32 to 32+iesr1_size-1) and slowspr_data_l2(32 to 32+iesr1_size-1); +iesr2_d <= EVENTMUX_128_MASK(32 to 32+iesr2_size-1) and slowspr_data_l2(32 to 32+iesr2_size-1); +mesr1_d <= EVENTMUX_64_MASK(32 to 32+mesr1_size-1) and slowspr_data_l2(32 to 32+mesr1_size-1); +mesr2_d <= EVENTMUX_64_MASK(32 to 32+mesr2_size-1) and slowspr_data_l2(32 to 32+mesr2_size-1); +xesr1_d <= EVENTMUX_128_MASK(32 to 32+xesr1_size-1) and slowspr_data_l2(32 to 32+xesr1_size-1); +xesr2_d <= EVENTMUX_128_MASK(32 to 32+xesr2_size-1) and slowspr_data_l2(32 to 32+xesr2_size-1); +xesr3_d <= EVENTMUX_128_MASK(32 to 32+xesr3_size-1) and slowspr_data_l2(32 to 32+xesr3_size-1); +xesr4_d <= EVENTMUX_128_MASK(32 to 32+xesr4_size-1) and slowspr_data_l2(32 to 32+xesr4_size-1); + + +cesr_rden <= cesr_sel and slowspr_rw_l2 = '1'; +aesr_rden <= aesr_sel and slowspr_rw_l2 = '1'; +iesr1_rden <= iesr1_sel and slowspr_rw_l2 = '1'; +iesr2_rden <= iesr2_sel and slowspr_rw_l2 = '1'; +mesr1_rden <= mesr1_sel and slowspr_rw_l2 = '1'; +mesr2_rden <= mesr2_sel and slowspr_rw_l2 = '1'; +xesr1_rden <= xesr1_sel and slowspr_rw_l2 = '1'; +xesr2_rden <= xesr2_sel and slowspr_rw_l2 = '1'; +xesr3_rden <= xesr3_sel and slowspr_rw_l2 = '1'; +xesr4_rden <= xesr4_sel and slowspr_rw_l2 = '1'; + +cesr_out(32 to 63) <= cesr_l2; +aesr_out(32 to 63) <= aesr_l2; +iesr1_out(32 to 63) <= iesr1_l2 & (32+iesr1_size to 63 => '0'); +iesr2_out(32 to 63) <= iesr2_l2 & (32+iesr2_size to 63 => '0'); +mesr1_out(32 to 63) <= mesr1_l2 & (32+mesr1_size to 63 => '0'); +mesr2_out(32 to 63) <= mesr2_l2 & (32+mesr2_size to 63 => '0'); +xesr1_out(32 to 63) <= xesr1_l2 & (32+xesr1_size to 63 => '0'); +xesr2_out(32 to 63) <= xesr2_l2 & (32+xesr2_size to 63 => '0'); +xesr3_out(32 to 63) <= xesr3_l2 & (32+xesr3_size to 63 => '0'); +xesr4_out(32 to 63) <= xesr4_l2 & (32+xesr4_size to 63 => '0'); + +pc_reg_data(32 to 63) <= cesr_out when cesr_rden = '1' else + aesr_out when aesr_rden = '1' else + iesr1_out when iesr1_rden = '1' else + iesr2_out when iesr2_rden = '1' else + mesr1_out when mesr1_rden = '1' else + mesr2_out when mesr2_rden = '1' else + xesr1_out when xesr1_rden = '1' else + xesr2_out when xesr2_rden = '1' else + xesr3_out when xesr3_rden = '1' else + xesr4_out when xesr4_rden = '1' else + (others => '0'); + + +r64: if (regmode > 5) generate begin +pc_data_int(0 to 31) <= (others => '0'); +end generate; +pc_data_int(32 to 63) <= pc_reg_data(32 to 63); + + + dbg_spr <= slowspr_val_l2 & + slowspr_rw_l2 & + slowspr_etid_l2(0 to 1) & + slowspr_addr_l2(0 to 9) & + slowspr_data_l2(32 to 63) & + pc_done_l2 ; + + +lcbor_funcslp: tri_lcbor +generic map (expand_type => expand_type ) +port map ( + clkoff_b => lcb_clkoff_dc_b, + thold => pc_pc_func_sl_thold_0, + sg => pc_pc_sg_0, + act_dis => lcb_act_dis_dc, + forcee => force_func, + thold_b => pc_pc_func_sl_thold_0_b ); + + +func_siv(0 TO func_right) <= func_scan_in & func_sov(0 to func_right-1); +func_scan_out <= func_sov(func_right) and scan_dis_dc_b; + + +end pcq_spr; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq.vhdl new file mode 100644 index 0000000..0b2817b --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq.vhdl @@ -0,0 +1,2110 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee,ibm,support,work; +use ieee.std_logic_1164.all; +use support.power_logic_pkg.all; +use work.xuq_pkg.mark_unused; + +library tri; +use tri.tri_latches_pkg.all; +entity xuq is + generic ( + expand_type : integer := 2; + threads : integer := 4; + eff_ifar : integer := 62; + uc_ifar : integer := 21; + l_endian_m : integer := 1; + real_data_add : integer := 42; + lmq_entries : integer := 8; + regmode : integer := 6; + hvmode : integer := 1; + a2mode : integer := 1; + dc_size : natural := 14; + cl_size : natural := 6; + load_credits : integer := 4; + store_credits : integer := 20; + st_data_32B_mode : integer := 1; + bcfg_epn_0to15 : integer := 0; + bcfg_epn_16to31 : integer := 0; + bcfg_epn_32to47 : integer := (2**16)-1; + bcfg_epn_48to51 : integer := (2**4)-1; + bcfg_rpn_22to31 : integer := (2**10)-1; + bcfg_rpn_32to47 : integer := (2**16)-1; + bcfg_rpn_48to51 : integer := (2**4)-1; + spr_xucr0_init_mod : integer := 0); + port ( + + an_ac_coreid : in std_ulogic_vector(54 to 61); + spr_pvr_version_dc : in std_ulogic_vector(8 to 15); + spr_pvr_revision_dc : in std_ulogic_vector(12 to 15); + an_ac_ext_interrupt : in std_ulogic_vector(0 to threads-1); + an_ac_crit_interrupt : in std_ulogic_vector(0 to threads-1); + an_ac_perf_interrupt : in std_ulogic_vector(0 to threads-1); + an_ac_tb_update_enable : in std_ulogic; + an_ac_tb_update_pulse : in std_ulogic; + an_ac_hang_pulse : in std_ulogic_vector(0 to threads-1); + an_ac_sleep_en : in std_ulogic_vector(0 to threads-1); + ac_tc_debug_trigger : out std_ulogic_vector(0 to threads-1); + an_ac_external_mchk : in std_ulogic_vector(0 to threads-1); + ac_tc_machine_check : out std_ulogic_vector(0 to threads-1); + an_ac_reservation_vld : in std_ulogic_vector(0 to threads-1); + an_ac_grffence_en_dc : in std_ulogic; + + iu_xu_is2_vld : in std_ulogic; + iu_xu_is2_instr : in std_ulogic_vector(0 to 31); + iu_xu_is2_match : in std_ulogic; + iu_xu_is2_ta : in std_ulogic_vector(0 to 5); + iu_xu_is2_ta_vld : in std_ulogic; + iu_xu_is2_s1 : in std_ulogic_vector(0 to 5); + iu_xu_is2_s1_vld : in std_ulogic; + iu_xu_is2_s2 : in std_ulogic_vector(0 to 5); + iu_xu_is2_s2_vld : in std_ulogic; + iu_xu_is2_s3 : in std_ulogic_vector(0 to 5); + iu_xu_is2_s3_vld : in std_ulogic; + iu_xu_is2_pred_update : in std_ulogic; + iu_xu_is2_pred_taken_cnt : in std_ulogic_vector(0 to 1); + iu_xu_is2_error : in std_ulogic_vector(0 to 2); + iu_xu_is2_tid : in std_ulogic_vector(0 to 3); + iu_xu_is2_ifar : in std_ulogic_vector(62-eff_ifar to 61); + iu_xu_is2_is_ucode : in std_ulogic; + iu_xu_is2_gshare : in std_ulogic_vector(0 to 3); + iu_xu_is2_axu_ld_or_st : in std_ulogic; + iu_xu_is2_axu_store : in std_ulogic; + iu_xu_is2_axu_ldst_size : in std_ulogic_vector(0 to 5); + iu_xu_is2_axu_ldst_update : in std_ulogic; + iu_xu_is2_axu_mftgpr : in std_ulogic; + iu_xu_is2_axu_mffgpr : in std_ulogic; + iu_xu_is2_axu_movedp : in std_ulogic; + iu_xu_is2_axu_instr_type : in std_ulogic_vector(0 to 2); + iu_xu_is2_axu_ldst_extpid : in std_ulogic; + iu_xu_is2_axu_ldst_tag : in std_ulogic_vector(0 to 8); + iu_xu_is2_axu_ldst_indexed : in std_ulogic; + iu_xu_is2_axu_ldst_forcealign : in std_ulogic; + iu_xu_is2_axu_ldst_forceexcept : in std_ulogic; + iu_xu_is2_ucode_vld : in std_ulogic; + + iu_xu_request : in std_ulogic; + iu_xu_thread : in std_ulogic_vector(0 to 3); + iu_xu_ra : in std_ulogic_vector(64-real_data_add to 59); + iu_xu_wimge : in std_ulogic_vector(0 to 4); + iu_xu_userdef : in std_ulogic_vector(0 to 3); + + an_ac_reld_data_vld : in std_ulogic; + an_ac_reld_core_tag : in std_ulogic_vector(0 to 4); + an_ac_reld_data : in std_ulogic_vector(0 to 127); + an_ac_reld_qw : in std_ulogic_vector(57 to 59); + an_ac_reld_ecc_err : in std_ulogic; + an_ac_reld_ecc_err_ue : in std_ulogic; + an_ac_reld_data_coming : in std_ulogic; + an_ac_reld_ditc : in std_ulogic; + an_ac_reld_crit_qw : in std_ulogic; + an_ac_reld_l1_dump : in std_ulogic; + + an_ac_req_ld_pop : in std_ulogic; + an_ac_req_st_pop : in std_ulogic; + an_ac_req_st_pop_thrd : in std_ulogic_vector(0 to 2); + an_ac_req_st_gather : in std_ulogic; + + an_ac_req_spare_ctrl_a1 : in std_ulogic_vector(0 to 3); + an_ac_flh2l2_gate : in std_ulogic; + + lsu_reld_data_vld : out std_ulogic; + lsu_reld_core_tag : out std_ulogic_vector(3 to 4); + lsu_reld_qw : out std_ulogic_vector(58 to 59); + lsu_reld_ditc : out std_ulogic; + lsu_reld_ecc_err : out std_ulogic; + lsu_reld_data : out std_ulogic_vector(0 to 127); + + lsu_req_st_pop : out std_ulogic; + lsu_req_st_pop_thrd : out std_ulogic_vector(0 to 2); + + mm_xu_cr0_eq_valid : in std_ulogic_vector(0 to 3); + mm_xu_cr0_eq : in std_ulogic_vector(0 to 3); + mm_xu_lsu_req : in std_ulogic_vector(0 to 3); + mm_xu_lsu_ttype : in std_ulogic_vector(0 to 1); + mm_xu_lsu_wimge : in std_ulogic_vector(0 to 4); + mm_xu_lsu_u : in std_ulogic_vector(0 to 3); + mm_xu_lsu_addr : in std_ulogic_vector(64-real_data_add to 63); + mm_xu_lsu_lpid : in std_ulogic_vector(0 to 7); + mm_xu_lsu_lpidr : in std_ulogic_vector(0 to 7); + mm_xu_lsu_gs : in std_ulogic; + mm_xu_lsu_ind : in std_ulogic; + mm_xu_lsu_lbit : in std_ulogic; + xu_mm_lsu_token : out std_ulogic; + + ac_an_reld_ditc_pop_int : in std_ulogic_vector(0 to 3); + ac_an_reld_ditc_pop_q : out std_ulogic_vector(0 to 3); + bx_ib_empty_int : in std_ulogic_vector(0 to 3); + bx_ib_empty_q : out std_ulogic_vector(0 to 3); + + an_ac_back_inv : in std_ulogic; + an_ac_back_inv_addr : in std_ulogic_vector(64-real_data_add to 63); + an_ac_back_inv_target_bit1 : in std_ulogic; + an_ac_back_inv_target_bit3 : in std_ulogic; + an_ac_back_inv_target_bit4 : in std_ulogic; + + an_ac_stcx_complete : in std_ulogic_vector(0 to 3); + an_ac_stcx_pass : in std_ulogic_vector(0 to 3); + xu_iu_stcx_complete : out std_ulogic_vector(0 to 3); + + xu_iu_ex4_loadmiss_target_type : out std_ulogic_vector(0 to 1); + xu_iu_ex4_loadmiss_tid : out std_ulogic_vector(0 to 3); + xu_iu_ex4_loadmiss_qentry : out std_ulogic_vector(0 to lmq_entries-1); + xu_iu_ex4_loadmiss_target : out std_ulogic_vector(0 to 8); + xu_iu_ex5_loadmiss_target_type : out std_ulogic_vector(0 to 1); + xu_iu_ex5_loadmiss_tid : out std_ulogic_vector(0 to 3); + xu_iu_ex5_loadmiss_qentry : out std_ulogic_vector(0 to lmq_entries-1); + xu_iu_ex5_loadmiss_target : out std_ulogic_vector(0 to 8); + xu_iu_complete_target_type : out std_ulogic_vector(0 to 1); + xu_iu_complete_tid : out std_ulogic_vector(0 to 3); + xu_iu_complete_qentry : out std_ulogic_vector(0 to lmq_entries-1); + xu_iu_larx_done_tid : out std_ulogic_vector(0 to 3); + xu_iu_set_barr_tid : out std_ulogic_vector(0 to 3); + xu_iu_ex6_icbi_val : out std_ulogic_vector(0 to 3); + xu_iu_ex6_icbi_addr : out std_ulogic_vector(64-real_data_add to 57); + + xu_iu_membar_tid : out std_ulogic_vector(0 to 3); + + xu_n_is2_flush : out std_ulogic_vector(0 to threads-1); + xu_n_rf0_flush : out std_ulogic_vector(0 to threads-1); + xu_n_rf1_flush : out std_ulogic_vector(0 to threads-1); + xu_n_ex1_flush : out std_ulogic_vector(0 to threads-1); + xu_n_ex2_flush : out std_ulogic_vector(0 to threads-1); + xu_n_ex3_flush : out std_ulogic_vector(0 to threads-1); + xu_n_ex4_flush : out std_ulogic_vector(0 to threads-1); + xu_n_ex5_flush : out std_ulogic_vector(0 to threads-1); + + xu_s_rf1_flush : out std_ulogic_vector(0 to threads-1); + xu_s_ex1_flush : out std_ulogic_vector(0 to threads-1); + xu_s_ex2_flush : out std_ulogic_vector(0 to threads-1); + xu_s_ex3_flush : out std_ulogic_vector(0 to threads-1); + xu_s_ex4_flush : out std_ulogic_vector(0 to threads-1); + xu_s_ex5_flush : out std_ulogic_vector(0 to threads-1); + + xu_wu_rf1_flush : out std_ulogic_vector(0 to threads-1); + xu_wu_ex1_flush : out std_ulogic_vector(0 to threads-1); + xu_wu_ex2_flush : out std_ulogic_vector(0 to threads-1); + xu_wu_ex3_flush : out std_ulogic_vector(0 to threads-1); + xu_wu_ex4_flush : out std_ulogic_vector(0 to threads-1); + xu_wu_ex5_flush : out std_ulogic_vector(0 to threads-1); + + xu_wl_rf1_flush : out std_ulogic_vector(0 to threads-1); + xu_wl_ex1_flush : out std_ulogic_vector(0 to threads-1); + xu_wl_ex2_flush : out std_ulogic_vector(0 to threads-1); + xu_wl_ex3_flush : out std_ulogic_vector(0 to threads-1); + xu_wl_ex4_flush : out std_ulogic_vector(0 to threads-1); + xu_wl_ex5_flush : out std_ulogic_vector(0 to threads-1); + + xu_mm_ex4_flush : out std_ulogic_vector(0 to threads-1); + xu_mm_ex5_flush : out std_ulogic_vector(0 to threads-1); + xu_mm_ierat_flush : out std_ulogic_vector(0 to threads-1); + xu_mm_ierat_miss : out std_ulogic_vector(0 to threads-1); + xu_mm_ex5_perf_itlb : out std_ulogic_vector(0 to threads-1); + xu_mm_ex5_perf_dtlb : out std_ulogic_vector(0 to threads-1); + + xu_iu_run_thread : out std_ulogic_vector(0 to 3); + xu_iu_u_flush : out std_ulogic_vector(0 to 3); + xu_iu_l_flush : out std_ulogic_vector(0 to 3); + xu_iu_flush_2ucode : out std_ulogic_vector(0 to 3); + xu_iu_flush_2ucode_type : out std_ulogic_vector(0 to 3); + xu_iu_ucode_restart : out std_ulogic_vector(0 to 3); + xu_iu_ex5_ppc_cpl : out std_ulogic_vector(0 to threads-1); + xu_iu_iu0_flush_ifar0 : out std_ulogic_vector(62-eff_ifar to 61); + xu_iu_iu0_flush_ifar1 : out std_ulogic_vector(62-eff_ifar to 61); + xu_iu_iu0_flush_ifar2 : out std_ulogic_vector(62-eff_ifar to 61); + xu_iu_iu0_flush_ifar3 : out std_ulogic_vector(62-eff_ifar to 61); + xu_iu_uc_flush_ifar0 : out std_ulogic_vector(62-uc_ifar to 61); + xu_iu_uc_flush_ifar1 : out std_ulogic_vector(62-uc_ifar to 61); + xu_iu_uc_flush_ifar2 : out std_ulogic_vector(62-uc_ifar to 61); + xu_iu_uc_flush_ifar3 : out std_ulogic_vector(62-uc_ifar to 61); + + xu_iu_ici : out std_ulogic; + + xu_iu_ex5_ifar : out std_ulogic_vector(62-eff_ifar to 61); + xu_iu_ex5_val : out std_ulogic; + xu_iu_ex5_tid : out std_ulogic_vector(0 to threads-1); + xu_iu_ex5_br_update : out std_ulogic; + xu_iu_ex5_br_hist : out std_ulogic_vector(0 to 1); + xu_iu_ex5_br_taken : out std_ulogic; + xu_iu_ex5_bclr : out std_ulogic; + xu_iu_ex5_lk : out std_ulogic; + xu_iu_ex5_bh : out std_ulogic_vector(0 to 1); + + iu_xu_quiesce : in std_ulogic_vector(0 to threads-1); + xu_iu_ex6_pri : out std_ulogic_vector(0 to 2); + xu_iu_ex6_pri_val : out std_ulogic_vector(0 to 3); + xu_iu_single_instr_mode : out std_ulogic_vector(0 to threads-1); + xu_iu_raise_iss_pri : out std_ulogic_vector(0 to threads-1); + xu_iu_multdiv_done : out std_ulogic_vector(0 to threads-1); + xu_iu_slowspr_done : out std_ulogic_vector(0 to 3); + xu_iu_need_hole : out std_ulogic; + xu_iu_ex5_gshare : out std_ulogic_vector(0 to 3); + xu_iu_ex5_getNIA : out std_ulogic; + + fu_xu_rf1_act : in std_ulogic_vector(0 to threads-1); + fu_xu_ex2_ifar_val : in std_ulogic_vector(0 to threads-1); + fu_xu_ex2_ifar_issued : in std_ulogic_vector(0 to threads-1); + fu_xu_ex1_ifar0 : in std_ulogic_vector(62-eff_ifar to 61); + fu_xu_ex1_ifar1 : in std_ulogic_vector(62-eff_ifar to 61); + fu_xu_ex1_ifar2 : in std_ulogic_vector(62-eff_ifar to 61); + fu_xu_ex1_ifar3 : in std_ulogic_vector(62-eff_ifar to 61); + fu_xu_ex2_instr_type : in std_ulogic_vector(0 to 3*threads-1); + fu_xu_ex2_instr_match : in std_ulogic_vector(0 to threads-1); + fu_xu_ex2_is_ucode : in std_ulogic_vector(0 to threads-1); + fu_xu_ex3_trap : in std_ulogic_vector(0 to threads-1); + fu_xu_ex3_ap_int_req : in std_ulogic_vector(0 to threads-1); + fu_xu_ex3_n_flush : in std_ulogic_vector(0 to threads-1); + fu_xu_ex3_np1_flush : in std_ulogic_vector(0 to threads-1); + fu_xu_ex3_flush2ucode : in std_ulogic_vector(0 to threads-1); + fu_xu_ex2_async_block : in std_ulogic_vector(0 to threads-1); + + fu_xu_ex4_cr_val : in std_ulogic_vector(0 to threads-1); + fu_xu_ex4_cr_noflush : in std_ulogic_vector(0 to threads-1); + fu_xu_ex4_cr0 : in std_ulogic_vector(0 to 3); + fu_xu_ex4_cr0_bf : in std_ulogic_vector(0 to 2); + fu_xu_ex4_cr1 : in std_ulogic_vector(0 to 3); + fu_xu_ex4_cr1_bf : in std_ulogic_vector(0 to 2); + fu_xu_ex4_cr2 : in std_ulogic_vector(0 to 3); + fu_xu_ex4_cr2_bf : in std_ulogic_vector(0 to 2); + fu_xu_ex4_cr3 : in std_ulogic_vector(0 to 3); + fu_xu_ex4_cr3_bf : in std_ulogic_vector(0 to 2); + + xu_fu_ex3_eff_addr : out std_ulogic_vector(59 to 63); + xu_fu_ex5_reload_val : out std_ulogic; + xu_fu_ex5_load_le : out std_ulogic; + xu_fu_ex5_load_val : out std_ulogic_vector(0 to threads-1); + xu_fu_ex5_load_tag : out std_ulogic_vector(0 to 8); + xu_fu_ex6_load_data : out std_ulogic_vector(0 to 255); + + fu_xu_ex2_store_data_val : in std_ulogic; + fu_xu_ex2_store_data : in std_ulogic_vector(0 to 255); + + ac_an_req_pwr_token : out std_ulogic; + ac_an_req : out std_ulogic; + ac_an_req_ra : out std_ulogic_vector(64-real_data_add to 63); + ac_an_req_ttype : out std_ulogic_vector(0 to 5); + ac_an_req_thread : out std_ulogic_vector(0 to 2); + ac_an_req_wimg_w : out std_ulogic; + ac_an_req_wimg_i : out std_ulogic; + ac_an_req_wimg_m : out std_ulogic; + ac_an_req_wimg_g : out std_ulogic; + ac_an_req_user_defined : out std_ulogic_vector(0 to 3); + ac_an_req_spare_ctrl_a0 : out std_ulogic_vector(0 to 3); + ac_an_req_ld_core_tag : out std_ulogic_vector(0 to 4); + ac_an_req_ld_xfr_len : out std_ulogic_vector(0 to 2); + ac_an_st_byte_enbl : out std_ulogic_vector(0 to 15+(st_data_32B_mode*16)); + ac_an_st_data : out std_ulogic_vector(0 to 127+(st_data_32B_mode*128)); + ac_an_req_endian : out std_ulogic; + ac_an_st_data_pwr_token : out std_ulogic; + + xu_mm_rf1_val : out std_ulogic_vector(0 to 3); + xu_mm_rf1_is_tlbre : out std_ulogic; + xu_mm_rf1_is_tlbwe : out std_ulogic; + xu_mm_rf1_is_tlbsx : out std_ulogic; + xu_mm_rf1_is_tlbsrx : out std_ulogic; + xu_mm_rf1_is_tlbivax : out std_ulogic; + xu_mm_rf1_is_tlbilx : out std_ulogic; + xu_mm_rf1_is_erativax : out std_ulogic; + xu_mm_rf1_is_eratilx : out std_ulogic; + xu_mm_ex1_is_isync : out std_ulogic; + xu_mm_ex1_is_csync : out std_ulogic; + xu_mm_rf1_t : out std_ulogic_vector(0 to 2); + xu_mm_ex1_rs_is : out std_ulogic_vector(0 to 8); + xu_mm_ex2_eff_addr : out std_ulogic_vector(64-(2**regmode) to 63); + + xu_iu_rf1_val : out std_ulogic_vector(0 to 3); + xu_iu_rf1_is_eratre : out std_ulogic; + xu_iu_rf1_is_eratwe : out std_ulogic; + xu_iu_rf1_is_eratsx : out std_ulogic; + xu_iu_rf1_is_eratilx : out std_ulogic; + xu_iu_ex1_is_isync : out std_ulogic; + xu_iu_ex1_is_csync : out std_ulogic; + xu_iu_rf1_ws : out std_ulogic_vector(0 to 1); + xu_iu_rf1_t : out std_ulogic_vector(0 to 2); + xu_iu_ex1_rs_is : out std_ulogic_vector(0 to 8); + xu_iu_ex1_ra_entry : out std_ulogic_vector(8 to 11); + xu_iu_ex1_rb : out std_ulogic_vector(64-(2**regmode) to 51); + xu_iu_ex4_rs_data : out std_ulogic_vector(64-(2**regmode) to 63); + iu_xu_ex4_tlb_data : in std_ulogic_vector(64-(2**regmode) to 63); + + mm_xu_illeg_instr : in std_ulogic_vector(0 to threads-1); + + mm_xu_tlb_miss : in std_ulogic_vector(0 to threads-1); + mm_xu_eratmiss_done : in std_ulogic_vector(0 to threads-1); + + mm_xu_hold_req : in std_ulogic_vector(0 to threads-1); + mm_xu_hold_done : in std_ulogic_vector(0 to threads-1); + xu_mm_hold_ack : out std_ulogic_vector(0 to threads-1); + + mm_xu_pt_fault : in std_ulogic_vector(0 to threads-1); + mm_xu_tlb_inelig : in std_ulogic_vector(0 to threads-1); + mm_xu_lrat_miss : in std_ulogic_vector(0 to threads-1); + mm_xu_hv_priv : in std_ulogic_vector(0 to threads-1); + mm_xu_esr_pt : in std_ulogic_vector(0 to threads-1); + mm_xu_esr_data : in std_ulogic_vector(0 to threads-1); + mm_xu_esr_epid : in std_ulogic_vector(0 to threads-1); + mm_xu_esr_st : in std_ulogic_vector(0 to threads-1); + mm_xu_ex3_flush_req : in std_ulogic_vector(0 to threads-1); + xu_mm_rf1_is_tlbsxr : out std_ulogic; + + xu_mm_lmq_stq_empty : out std_ulogic; + mm_xu_quiesce : in std_ulogic_vector(0 to threads-1); + + xu_mm_derat_req : out std_ulogic; + xu_mm_derat_epn : out std_ulogic_vector(62-eff_ifar to 51); + xu_mm_derat_thdid : out std_ulogic_vector(0 to 3); + xu_mm_derat_state : out std_ulogic_vector(0 to 3); + xu_mm_derat_ttype : out std_ulogic_vector(0 to 1); + xu_mm_derat_tid : out std_ulogic_vector(0 to 13); + xu_mm_derat_lpid : out std_ulogic_vector(0 to 7); + + mm_xu_local_snoop_reject : in std_ulogic_vector(0 to threads-1); + mm_xu_lru_par_err : in std_ulogic_vector(0 to threads-1); + mm_xu_tlb_par_err : in std_ulogic_vector(0 to threads-1); + mm_xu_tlb_multihit_err : in std_ulogic_vector(0 to threads-1); + + mm_xu_derat_rel_val : in std_ulogic_vector(0 to 4); + mm_xu_derat_rel_data : in std_ulogic_vector(0 to 131); + + mm_xu_derat_snoop_coming : in std_ulogic; + mm_xu_derat_snoop_val : in std_ulogic; + mm_xu_derat_snoop_attr : in std_ulogic_vector(0 to 25); + mm_xu_derat_snoop_vpn : in std_ulogic_vector(64-(2**REGMODE) to 51); + xu_mm_derat_snoop_ack : out std_ulogic; + + mm_xu_derat_pid0 : in std_ulogic_vector(0 to 13); + mm_xu_derat_pid1 : in std_ulogic_vector(0 to 13); + mm_xu_derat_pid2 : in std_ulogic_vector(0 to 13); + mm_xu_derat_pid3 : in std_ulogic_vector(0 to 13); + mm_xu_derat_mmucr0_0 : in std_ulogic_vector(0 to 19); + mm_xu_derat_mmucr0_1 : in std_ulogic_vector(0 to 19); + mm_xu_derat_mmucr0_2 : in std_ulogic_vector(0 to 19); + mm_xu_derat_mmucr0_3 : in std_ulogic_vector(0 to 19); + xu_mm_derat_mmucr0 : out std_ulogic_vector(0 to 17); + xu_mm_derat_mmucr0_we : out std_ulogic_vector(0 to 3); + mm_xu_derat_mmucr1 : in std_ulogic_vector(0 to 9); + xu_mm_derat_mmucr1 : out std_ulogic_vector(0 to 4); + xu_mm_derat_mmucr1_we : out std_ulogic; + + xu_mm_spr_epcr_dmiuh : out std_ulogic_vector(0 to threads-1); + xu_mm_spr_epcr_dgtmi : out std_ulogic_vector(0 to threads-1); + xu_iu_spr_ccr2_ifratsc : out std_ulogic_vector(0 to 8); + xu_iu_spr_ccr2_ifrat : out std_ulogic; + xu_bx_ccr2_en_ditc : out std_ulogic; + xu_iu_spr_xer0 : out std_ulogic_vector(57 to 63); + xu_iu_spr_xer1 : out std_ulogic_vector(57 to 63); + xu_iu_spr_xer2 : out std_ulogic_vector(57 to 63); + xu_iu_spr_xer3 : out std_ulogic_vector(57 to 63); + xu_iu_msr_gs : out std_ulogic_vector(0 to threads-1); + xu_iu_msr_hv : out std_ulogic_vector(0 to threads-1); + xu_iu_msr_pr : out std_ulogic_vector(0 to threads-1); + xu_iu_msr_is : out std_ulogic_vector(0 to threads-1); + xu_iu_msr_cm : out std_ulogic_vector(0 to threads-1); + xu_iu_hid_mmu_mode : out std_ulogic; + xu_iu_xucr0_rel : out std_ulogic; + xu_mm_msr_gs : out std_ulogic_vector(0 to threads-1); + xu_mm_msr_pr : out std_ulogic_vector(0 to threads-1); + xu_mm_msr_is : out std_ulogic_vector(0 to threads-1); + xu_mm_msr_ds : out std_ulogic_vector(0 to threads-1); + xu_mm_msr_cm : out std_ulogic_vector(0 to threads-1); + xu_mm_hid_mmu_mode : out std_ulogic; + xu_fu_msr_pr : out std_ulogic_vector(0 to threads-1); + xu_fu_msr_gs : out std_ulogic_vector(0 to threads-1); + xu_fu_msr_fp : out std_ulogic_vector(0 to threads-1); + xu_fu_msr_spv : out std_ulogic_vector(0 to threads-1); + xu_fu_ccr2_ap : out std_ulogic_vector(0 to threads-1); + xu_iu_xucr4_mmu_mchk : out std_ulogic; + xu_mm_xucr4_mmu_mchk : out std_ulogic; + + slowspr_val_out : out std_ulogic; + slowspr_rw_out : out std_ulogic; + slowspr_etid_out : out std_ulogic_vector(0 to 1); + slowspr_addr_out : out std_ulogic_vector(0 to 9); + slowspr_data_out : out std_ulogic_vector(64-(2**regmode) to 63); + slowspr_done_out : out std_ulogic; + slowspr_val_in : in std_ulogic; + slowspr_rw_in : in std_ulogic; + slowspr_etid_in : in std_ulogic_vector(0 to 1); + slowspr_addr_in : in std_ulogic_vector(0 to 9); + slowspr_data_in : in std_ulogic_vector(64-(2**regmode) to 63); + slowspr_done_in : in std_ulogic; + + xu_iu_spr_ccr2_en_dcr : out std_ulogic; + + xu_bx_ex1_mtdp_val : out std_ulogic; + xu_bx_ex1_mfdp_val : out std_ulogic; + xu_bx_ex1_ipc_thrd : out std_ulogic_vector(0 to 1); + xu_bx_ex2_ipc_ba : out std_ulogic_vector(0 to 4); + xu_bx_ex2_ipc_sz : out std_ulogic_vector(0 to 1); + xu_bx_ex4_256st_data : out std_ulogic_vector(128 to 255); + bx_xu_ex4_mtdp_cr_status : in std_ulogic; + bx_xu_ex4_mfdp_cr_status : in std_ulogic; + bx_xu_ex5_dp_data : in std_ulogic_vector(0 to 127); + bx_xu_quiesce : in std_ulogic_vector(0 to 3); + bx_lsu_ob_pwr_tok : in std_ulogic; + bx_lsu_ob_req_val : in std_ulogic; + bx_lsu_ob_ditc_val : in std_ulogic; + bx_lsu_ob_thrd : in std_ulogic_vector(0 to 1); + bx_lsu_ob_qw : in std_ulogic_vector(58 to 59); + bx_lsu_ob_dest : in std_ulogic_vector(0 to 14); + bx_lsu_ob_data : in std_ulogic_vector(0 to 127); + bx_lsu_ob_addr : in std_ulogic_vector(64-real_data_add to 57); + lsu_bx_cmd_avail : out std_ulogic; + lsu_bx_cmd_sent : out std_ulogic; + lsu_bx_cmd_stall : out std_ulogic; + + xu_iu_reld_core_tag :out std_ulogic_vector(0 to 4); + xu_iu_reld_core_tag_clone :out std_ulogic_vector(1 to 4); + xu_iu_reld_data :out std_ulogic_vector(0 to 127); + xu_iu_reld_data_coming_clone :out std_ulogic; + xu_iu_reld_data_vld :out std_ulogic; + xu_iu_reld_data_vld_clone :out std_ulogic; + xu_iu_reld_ditc_clone :out std_ulogic; + xu_iu_reld_ecc_err :out std_ulogic; + xu_iu_reld_ecc_err_ue :out std_ulogic; + xu_iu_reld_qw :out std_ulogic_vector(57 to 59); + + + xu_pc_err_mcsr_summary : out std_ulogic_vector(0 to threads-1); + xu_pc_err_local_snoop_reject : out std_ulogic; + xu_pc_err_tlb_lru_parity : out std_ulogic; + xu_pc_err_ext_mchk : out std_ulogic; + xu_pc_err_ierat_multihit : out std_ulogic; + xu_pc_err_derat_multihit : out std_ulogic; + xu_pc_err_tlb_multihit : out std_ulogic; + xu_pc_err_ierat_parity : out std_ulogic; + xu_pc_err_derat_parity : out std_ulogic; + xu_pc_err_tlb_parity : out std_ulogic; + xu_pc_err_mchk_disabled : out std_ulogic; + xu_pc_err_ditc_overrun : out std_ulogic; + xu_pc_err_dcache_parity : out std_ulogic; + xu_pc_err_dcachedir_parity : out std_ulogic; + xu_pc_err_dcachedir_multihit : out std_ulogic; + xu_pc_err_sprg_ecc : out std_ulogic_vector(0 to threads-1); + xu_pc_err_regfile_parity : out std_ulogic_vector(0 to threads-1); + xu_pc_err_llbust_attempt : out std_ulogic_vector(0 to threads-1); + xu_pc_err_llbust_failed : out std_ulogic_vector(0 to threads-1); + xu_pc_err_l2intrf_ecc : out std_ulogic; + xu_pc_err_l2intrf_ue : out std_ulogic; + xu_pc_err_attention_instr : out std_ulogic_vector(0 to threads-1); + xu_pc_err_nia_miscmpr : out std_ulogic_vector(0 to threads-1); + xu_pc_err_wdt_reset : out std_ulogic_vector(0 to threads-1); + xu_pc_err_debug_event : out std_ulogic_vector(0 to threads-1); + xu_pc_err_invld_reld : out std_ulogic; + xu_pc_err_l2credit_overrun : out std_ulogic; + + pc_xu_inj_dcache_parity : in std_ulogic; + pc_xu_inj_dcachedir_parity : in std_ulogic; + pc_xu_inj_dcachedir_multihit : in std_ulogic; + pc_xu_inj_llbust_attempt : in std_ulogic_vector(0 to threads-1); + pc_xu_inj_llbust_failed : in std_ulogic_vector(0 to threads-1); + pc_xu_inj_wdt_reset : in std_ulogic_vector(0 to threads-1); + + pc_xu_ram_mode : in std_ulogic; + pc_xu_ram_thread : in std_ulogic_vector(0 to 1); + pc_xu_ram_execute : in std_ulogic; + pc_xu_ram_flush_thread : in std_ulogic; + xu_iu_ram_issue : out std_ulogic_vector(0 to threads-1); + xu_pc_ram_interrupt : out std_ulogic; + xu_pc_ram_done : out std_ulogic; + xu_pc_ram_data : out std_ulogic_vector(64-(2**regmode) to 63); + + pc_xu_stop : in std_ulogic_vector(0 to 3); + pc_xu_step : in std_ulogic_vector(0 to 3); + pc_xu_dbg_action : in std_ulogic_vector(0 to 11); + pc_xu_force_ude : in std_ulogic_vector(0 to threads-1); + xu_pc_step_done : out std_ulogic_vector(0 to threads-1); + xu_pc_running : out std_ulogic_vector(0 to 3); + xu_pc_spr_ccr0_we : out std_ulogic_vector(0 to threads-1); + xu_pc_stop_dbg_event : out std_ulogic_vector(0 to threads-1); + xu_pc_spr_ccr0_pme : out std_ulogic_vector(0 to 1); + pc_xu_msrovride_enab : in std_ulogic; + pc_xu_msrovride_pr : in std_ulogic; + pc_xu_msrovride_gs : in std_ulogic; + pc_xu_msrovride_de : in std_ulogic; + + pc_xu_extirpts_dis_on_stop : in std_ulogic; + pc_xu_timebase_dis_on_stop : in std_ulogic; + pc_xu_decrem_dis_on_stop : in std_ulogic; + + pc_xu_trace_bus_enable : in std_ulogic; + pc_xu_debug_mux1_ctrls : in std_ulogic_vector(0 to 15); + pc_xu_debug_mux2_ctrls : in std_ulogic_vector(0 to 15); + pc_xu_debug_mux3_ctrls : in std_ulogic_vector(0 to 15); + pc_xu_debug_mux4_ctrls : in std_ulogic_vector(0 to 15); + trigger_data_in : in std_ulogic_vector(0 to 11); + debug_data_in : in std_ulogic_vector(0 to 87); + trigger_data_out : out std_ulogic_vector(0 to 11); + debug_data_out : out std_ulogic_vector(0 to 87); + + pc_xu_event_bus_enable : in std_ulogic; + xu_pc_lsu_event_data : out std_ulogic_vector(0 to 7); + xu_pc_event_data : out std_ulogic_vector(0 to 7); + pc_xu_event_mux_ctrls : in std_ulogic_vector(0 to 47); + pc_xu_lsu_event_mux_ctrls : in std_ulogic_vector(0 to 47); + pc_xu_cache_par_err_event : in std_ulogic; + + pc_xu_instr_trace_mode : in std_ulogic; + pc_xu_instr_trace_tid : in std_ulogic_vector(0 to 1); + pc_xu_event_count_mode : in std_ulogic_vector(0 to 2); + + ac_tc_reset_1_request : out std_ulogic; + ac_tc_reset_2_request : out std_ulogic; + ac_tc_reset_3_request : out std_ulogic; + ac_tc_reset_wd_request : out std_ulogic; + + pc_xu_ccflush_dc : in std_ulogic; + an_ac_scan_diag_dc : in std_ulogic; + an_ac_scan_dis_dc_b : in std_ulogic; + an_ac_atpg_en_dc : in std_ulogic; + + pc_xu_gptr_sl_thold_3 : in std_ulogic; + pc_xu_time_sl_thold_3 : in std_ulogic; + pc_xu_repr_sl_thold_3 : in std_ulogic; + pc_xu_abst_sl_thold_3 : in std_ulogic; + pc_xu_abst_slp_sl_thold_3 : in std_ulogic; + pc_xu_regf_sl_thold_3 : in std_ulogic; + pc_xu_regf_slp_sl_thold_3 : in std_ulogic; + pc_xu_func_sl_thold_3 : in std_ulogic_vector(0 to 4); + pc_xu_func_slp_sl_thold_3 : in std_ulogic_vector(0 to 4); + pc_xu_cfg_sl_thold_3 : in std_ulogic; + pc_xu_cfg_slp_sl_thold_3 : in std_ulogic; + pc_xu_func_nsl_thold_3 : in std_ulogic; + pc_xu_func_slp_nsl_thold_3 : in std_ulogic; + pc_xu_ary_nsl_thold_3 : in std_ulogic; + pc_xu_ary_slp_nsl_thold_3 : in std_ulogic; + pc_xu_sg_3 : in std_ulogic_vector(0 to 4); + pc_xu_fce_3 : in std_ulogic_vector(0 to 1); + pc_xu_bolt_sl_thold_3 : in std_ulogic; + + gptr_scan_in : in std_ulogic; + time_scan_in : in std_ulogic; + repr_scan_in : in std_ulogic; + abst_scan_in : in std_ulogic_vector(0 to 2); + func_scan_in : in std_ulogic_vector(31 to 58); + bcfg_scan_in : in std_ulogic; + ccfg_scan_in : in std_ulogic; + dcfg_scan_in : in std_ulogic; + regf_scan_in : in std_ulogic_vector(0 to 6); + + gptr_scan_out : out std_ulogic; + time_scan_out : out std_ulogic; + repr_scan_out : out std_ulogic; + abst_scan_out : out std_ulogic_vector(0 to 2); + func_scan_out : out std_ulogic_vector(31 to 58); + bcfg_scan_out : out std_ulogic; + ccfg_scan_out : out std_ulogic; + dcfg_scan_out : out std_ulogic; + regf_scan_out : out std_ulogic_vector(0 to 6); + + pc_xu_init_reset : in std_ulogic; + pc_xu_reset_wd_complete : in std_ulogic; + pc_xu_reset_1_complete : in std_ulogic; + pc_xu_reset_2_complete : in std_ulogic; + pc_xu_reset_3_complete : in std_ulogic; + + xu_pc_err_sprg_ue : out std_ulogic_vector(0 to 3); + xu_pc_err_regfile_ue : out std_ulogic_vector(0 to 3); + + iu_xu_ierat_ex2_flush_req : in std_ulogic_vector(0 to threads-1); + iu_xu_ierat_ex3_par_err : in std_ulogic_vector(0 to threads-1); + iu_xu_ierat_ex4_par_err : in std_ulogic_vector(0 to threads-1); + pc_xu_inj_sprg_ecc : in std_ulogic_vector(0 to 3); + pc_xu_inj_regfile_parity : in std_ulogic_vector(0 to 3); + fu_xu_ex3_regfile_err_det : in std_ulogic_vector(0 to threads-1); + xu_fu_regfile_seq_beg : out std_ulogic; + fu_xu_regfile_seq_end : in std_ulogic; + + nclk : in clk_logic; + vdd : inout power_logic; + gnd : inout power_logic; + vcs : inout power_logic; + + an_ac_lbist_ary_wrt_thru_dc : in std_ulogic; + xu_fu_lbist_ary_wrt_thru_dc : out std_ulogic; + pc_xu_abist_dcomp_g6t_2r : in std_ulogic_vector(0 to 3); + pc_xu_abist_di_g6t_2r : in std_ulogic_vector(0 to 3); + pc_xu_abist_g6t_bw : in std_ulogic_vector(0 to 1); + pc_xu_abist_g6t_r_wb : in std_ulogic; + pc_xu_abist_g8t1p_renb_0 : in std_ulogic; + pc_xu_abist_g8t_bw_0 : in std_ulogic; + pc_xu_abist_g8t_bw_1 : in std_ulogic; + pc_xu_abist_g8t_dcomp : in std_ulogic_vector(0 to 3); + pc_xu_abist_g8t_wenb : in std_ulogic; + pc_xu_abist_wl32_comp_ena : in std_ulogic; + pc_xu_abist_wl512_comp_ena : in std_ulogic; + an_ac_lbist_en_dc : in std_ulogic; + xu_fu_lbist_en_dc : out std_ulogic; + pc_xu_abist_raddr_0 : in std_ulogic_vector(0 to 9); + pc_xu_abist_raddr_1 : in std_ulogic_vector(0 to 9); + pc_xu_abist_grf_renb_0 : in std_ulogic; + pc_xu_abist_grf_renb_1 : in std_ulogic; + pc_xu_abist_ena_dc : in std_ulogic; + pc_xu_abist_waddr_0 : in std_ulogic_vector(0 to 9); + pc_xu_abist_waddr_1 : in std_ulogic_vector(0 to 9); + pc_xu_abist_grf_wenb_0 : in std_ulogic; + pc_xu_abist_grf_wenb_1 : in std_ulogic; + pc_xu_abist_di_0 : in std_ulogic_vector(0 to 3); + pc_xu_abist_di_1 : in std_ulogic_vector(0 to 3); + pc_xu_abist_wl144_comp_ena : in std_ulogic; + pc_xu_abist_raw_dc_b : in std_ulogic; + + pc_xu_bo_enable_3 : in std_ulogic; + pc_xu_bo_unload : in std_ulogic; + pc_xu_bo_load : in std_ulogic; + pc_xu_bo_repair : in std_ulogic; + pc_xu_bo_reset : in std_ulogic; + pc_xu_bo_shdata : in std_ulogic; + pc_xu_bo_select : in std_ulogic_vector(0 to 8); + xu_pc_bo_fail : out std_ulogic_vector(0 to 8); + xu_pc_bo_diagout : out std_ulogic_vector(0 to 8) + + ); +-- synopsys translate_off +-- synopsys translate_on +end xuq; + +architecture xuq of xuq is + +constant tidn : std_ulogic_vector(0 to 63) := (others=>'0'); +constant regsize : integer := 2**regmode; + +signal xu_lsu_ex1_store_data :std_ulogic_vector(64-(2**regmode) to 63); +signal xu_lsu_ex1_eff_addr :std_ulogic_vector(64-(dc_size-3) to 63); +signal lsu_xu_rel_ta_gpr :std_ulogic_vector(0 to 7); +signal lsu_xu_rot_ex6_data_b :std_ulogic_vector(64-(2**regmode) to 63); +signal lsu_xu_rel_wren :std_ulogic; +signal lsu_xu_rot_rel_data :std_ulogic_vector(64-(2**regmode) to 63); +signal is2_flush :std_ulogic_vector(0 to threads-1); +signal rf0_flush :std_ulogic_vector(0 to threads-1); +signal rf1_flush :std_ulogic_vector(0 to threads-1); +signal ex1_flush :std_ulogic_vector(0 to threads-1); +signal ex2_flush :std_ulogic_vector(0 to threads-1); +signal ex3_flush :std_ulogic_vector(0 to threads-1); +signal ex4_flush :std_ulogic_vector(0 to threads-1); +signal ex5_flush :std_ulogic_vector(0 to threads-1); +signal xu_lsu_ex4_flush_local :std_ulogic_vector(0 to threads-1); +signal xu_iu_iu0_flush_ifar :std_ulogic_vector(0 to eff_ifar*threads-1); +signal xu_iu_uc_flush_ifar :std_ulogic_vector(0 to uc_ifar*threads-1); +signal xu_lsu_rf0_derat_val :std_ulogic_vector(0 to threads-1); +signal xu_lsu_rf1_data_act :std_ulogic; +signal xu_lsu_rf0_derat_is_extload :std_ulogic; +signal xu_lsu_rf0_derat_is_extstore :std_ulogic; +signal xu_rf1_val :std_ulogic_vector(0 to 3); +signal xu_rf1_is_eratilx :std_ulogic; +signal xu_ex1_is_isync :std_ulogic; +signal xu_ex1_is_csync :std_ulogic; +signal xu_rf1_ws :std_ulogic_vector(0 to 1); +signal xu_rf1_t :std_ulogic_vector(0 to 2); +signal xu_ex1_rs_is :std_ulogic_vector(0 to 8); +signal xu_ex1_ra_entry :std_ulogic_vector(8 to 11); +signal xu_ex4_rs_data :std_ulogic_vector(64-(2**regmode) to 63); +signal xu_msr_gs :std_ulogic_vector(0 to threads-1); +signal xu_msr_pr :std_ulogic_vector(0 to threads-1); +signal xu_msr_is :std_ulogic_vector(0 to threads-1); +signal xu_msr_ds :std_ulogic_vector(0 to threads-1); +signal cpl_msr_gs :std_ulogic_vector(0 to threads-1); +signal cpl_msr_pr :std_ulogic_vector(0 to threads-1); +signal cpl_msr_fp :std_ulogic_vector(0 to threads-1); +signal cpl_msr_spv :std_ulogic_vector(0 to threads-1); +signal cpl_ccr2_ap :std_ulogic_vector(0 to threads-1); +signal xu_msr_cm :std_ulogic_vector(0 to threads-1); +signal xu_lsu_hid_mmu_mode :std_ulogic; +signal xu_iu_spr_xer :std_ulogic_vector(0 to 7*threads-1); +signal xu_lsu_rf1_axu_ldst_falign :std_ulogic; +signal fu_xu_ex1_ifar :std_ulogic_vector(0 to eff_ifar*threads-1); +signal xu_lsu_ex1_rotsel_ovrd :std_ulogic_vector(0 to 4); +signal xu_lsu_ici :std_ulogic; +signal lsu_xu_ldq_barr_done :std_ulogic_vector(0 to threads-1); +signal lsu_xu_barr_done :std_ulogic_vector(0 to threads-1); +signal lsu_xu_rel_dvc_thrd_id :std_ulogic_vector(0 to 3); +signal lsu_xu_ex2_dvc1_st_cmp :std_ulogic_vector(0 to ((2**regmode)/8)-1); +signal lsu_xu_ex8_dvc1_ld_cmp :std_ulogic_vector(0 to ((2**regmode)/8)-1); +signal lsu_xu_rel_dvc1_en :std_ulogic; +signal lsu_xu_rel_dvc1_cmp :std_ulogic_vector(0 to ((2**regmode)/8)-1); +signal lsu_xu_ex2_dvc2_st_cmp :std_ulogic_vector(0 to ((2**regmode)/8)-1); +signal lsu_xu_ex8_dvc2_ld_cmp :std_ulogic_vector(0 to ((2**regmode)/8)-1); +signal lsu_xu_rel_dvc2_en :std_ulogic; +signal lsu_xu_rel_dvc2_cmp :std_ulogic_vector(0 to ((2**regmode)/8)-1); +signal xu_ex2_eff_addr :std_ulogic_vector(64-(2**regmode) to 63); +signal spr_debug_mux_ctrls :std_ulogic_vector(0 to 15); +signal cpl_debug_mux_ctrls :std_ulogic_vector(0 to 15); +signal fxu_debug_mux_ctrls :std_ulogic_vector(0 to 15); +signal lsu_debug_mux_ctrls :std_ulogic_vector(0 to 15); +signal lsudat_debug_mux_ctrls :std_ulogic_vector(0 to 1); +signal lsu_xu_data_debug0 :std_ulogic_vector(0 to 87); +signal lsu_xu_data_debug1 :std_ulogic_vector(0 to 87); +signal lsu_xu_data_debug2 :std_ulogic_vector(0 to 87); +signal sg_2 :std_ulogic_vector(0 to 3); +signal func_sl_thold_2 :std_ulogic_vector(0 to 3); +signal func_nsl_thold_2 :std_ulogic; +signal func_slp_sl_thold_2 :std_ulogic_vector(0 to 1); +signal ary_nsl_thold_2 :std_ulogic; +signal time_sl_thold_2 :std_ulogic; +signal abst_sl_thold_2 :std_ulogic; +signal repr_sl_thold_2 :std_ulogic; +signal gptr_sl_thold_2 :std_ulogic; +signal cfg_sl_thold_2 :std_ulogic; +signal cfg_slp_sl_thold_2 :std_ulogic; +signal regf_slp_sl_thold_2 :std_ulogic; +signal fce_2 :std_ulogic_vector(0 to 1); +signal clkoff_dc_b :std_ulogic; +signal d_mode_dc :std_ulogic; +signal delay_lclkr_dc :std_ulogic_vector(0 to 4); +signal mpw1_dc_b :std_ulogic_vector(0 to 4); +signal mpw2_dc_b :std_ulogic; +signal g6t_clkoff_dc_b :std_ulogic; +signal g6t_d_mode_dc :std_ulogic; +signal g6t_delay_lclkr_dc :std_ulogic_vector(0 to 4); +signal g6t_mpw1_dc_b :std_ulogic_vector(0 to 4); +signal g6t_mpw2_dc_b :std_ulogic; + +signal fxa_fxb_rf0_val :std_ulogic_vector(0 to threads-1); +signal fxa_fxb_rf0_issued :std_ulogic_vector(0 to threads-1); +signal fxa_fxb_rf0_ucode_val :std_ulogic_vector(0 to threads-1); +signal fxa_fxb_rf0_act :std_ulogic; +signal fxa_fxb_ex1_hold_ctr_flush :std_ulogic; +signal fxa_fxb_rf0_instr :std_ulogic_vector(0 to 31); +signal fxa_fxb_rf0_tid :std_ulogic_vector(0 to threads-1); +signal fxa_fxb_rf0_ta_vld :std_ulogic; +signal fxa_fxb_rf0_ta :std_ulogic_vector(0 to 7); +signal fxa_fxb_rf0_error :std_ulogic_vector(0 to 2); +signal fxa_fxb_rf0_match :std_ulogic; +signal fxa_fxb_rf0_is_ucode :std_ulogic; +signal fxa_fxb_rf0_gshare :std_ulogic_vector(0 to 3); +signal fxa_fxb_rf0_ifar :std_ulogic_vector(62-eff_ifar to 61); +signal fxa_fxb_rf0_s1_vld :std_ulogic; +signal fxa_fxb_rf0_s1 :std_ulogic_vector(0 to 7); +signal fxa_fxb_rf0_s2_vld :std_ulogic; +signal fxa_fxb_rf0_s2 :std_ulogic_vector(0 to 7); +signal fxa_fxb_rf0_s3_vld :std_ulogic; +signal fxa_fxb_rf0_s3 :std_ulogic_vector(0 to 7); +signal fxa_fxb_rf0_axu_instr_type :std_ulogic_vector(0 to 2); +signal fxa_fxb_rf0_axu_ld_or_st :std_ulogic; +signal fxa_fxb_rf0_axu_store :std_ulogic; +signal fxa_fxb_rf0_axu_ldst_forcealign :std_ulogic; +signal fxa_fxb_rf0_axu_ldst_forceexcept :std_ulogic; +signal fxa_fxb_rf0_axu_ldst_indexed :std_ulogic; +signal fxa_fxb_rf0_axu_ldst_tag :std_ulogic_vector(0 to 8); +signal fxa_fxb_rf0_axu_mftgpr :std_ulogic; +signal fxa_fxb_rf0_axu_mffgpr :std_ulogic; +signal fxa_fxb_rf0_axu_movedp :std_ulogic; +signal fxa_fxb_rf0_axu_ldst_size :std_ulogic_vector(0 to 5); +signal fxa_fxb_rf0_axu_ldst_update :std_ulogic; +signal fxa_fxb_rf0_pred_update :std_ulogic; +signal fxa_fxb_rf0_pred_taken_cnt :std_ulogic_vector(0 to 1); +signal fxa_fxb_rf0_mc_dep_chk_val :std_ulogic_vector(0 to threads-1); +signal fxa_fxb_rf1_mul_val :std_ulogic; +signal fxa_fxb_rf1_div_val :std_ulogic; +signal fxa_fxb_rf1_div_ctr :std_ulogic_vector(0 to 7); +signal fxa_fxb_rf0_xu_epid_instr :std_ulogic; +signal fxa_fxb_rf0_axu_is_extload :std_ulogic; +signal fxa_fxb_rf0_axu_is_extstore :std_ulogic; +signal fxa_fxb_rf0_is_mfocrf :std_ulogic; +signal fxa_fxb_rf0_3src_instr :std_ulogic; +signal fxa_fxb_rf0_gpr0_zero :std_ulogic; +signal fxa_fxb_rf0_use_imm :std_ulogic; +signal fxa_fxb_rf1_muldiv_coll :std_ulogic; +signal fxa_cpl_ex2_div_coll :std_ulogic_vector(0 to threads-1); +signal fxb_fxa_ex7_we0 :std_ulogic; +signal fxb_fxa_ex7_wa0 :std_ulogic_vector(0 to 7); +signal fxb_fxa_ex7_wd0 :std_ulogic_vector(64-regsize to 63); +signal fxa_fxb_rf1_do0 :std_ulogic_vector(64-regsize to 63); +signal fxa_fxb_rf1_do1 :std_ulogic_vector(64-regsize to 63); +signal fxa_fxb_rf1_do2 :std_ulogic_vector(64-regsize to 63); +signal fxb_fxa_ex6_clear_barrier :std_ulogic_vector(0 to threads-1); +signal dec_cpl_ex3_mc_dep_chk_val :std_ulogic_vector(0 to threads-1); +signal spr_ccr2_notlb :std_ulogic; +signal fxa_fxb_rf0_spr_tid :std_ulogic_vector(0 to threads-1); +signal fxa_fxb_rf0_cpl_tid :std_ulogic_vector(0 to threads-1); +signal fxa_fxb_rf0_cpl_act :std_ulogic; +signal gpr_cpl_ex3_regfile_err_det :std_ulogic; +signal cpl_gpr_regfile_seq_beg :std_ulogic; +signal gpr_cpl_regfile_seq_end :std_ulogic; +signal fxa_cpl_debug :std_ulogic_vector(0 to 272); +signal cpl_fxa_ex5_set_barr :std_ulogic_vector(0 to threads-1); +signal fxa_iu_set_barr_tid :std_ulogic_vector(0 to threads-1); +signal cpl_iu_set_barr_tid :std_ulogic_vector(0 to threads-1); +signal spr_xucr4_div_barr_thres :std_ulogic_vector(0 to 7); +signal ex4_256st_data :std_ulogic_vector(0 to 255); +signal ex6_ld_par_err :std_ulogic; +signal lsu_xu_ex6_datc_par_err :std_ulogic; +signal ex1_optype1 :std_ulogic; +signal ex1_optype2 :std_ulogic; +signal ex1_optype4 :std_ulogic; +signal ex1_optype8 :std_ulogic; +signal ex1_optype16 :std_ulogic; +signal ex1_optype32 :std_ulogic; +signal ex1_saxu_instr :std_ulogic; +signal ex1_sdp_instr :std_ulogic; +signal ex1_stgpr_instr :std_ulogic; +signal ex1_store_instr :std_ulogic; +signal ex1_axu_op_val :std_ulogic; +signal ex3_algebraic :std_ulogic; +signal ex3_data_swap :std_ulogic; +signal ex3_thrd_id :std_ulogic_vector(0 to 3); +signal rel_upd_dcarr_val :std_ulogic; +signal dcarr_up_way_addr :std_ulogic_vector(0 to 2); +signal ex4_load_op_hit :std_ulogic; +signal ex4_store_hit :std_ulogic; +signal ex4_axu_op_val :std_ulogic; +signal spr_dvc1_act :std_ulogic; +signal spr_dvc2_act :std_ulogic; +signal spr_dvc1_dbg :std_ulogic_vector(64-(2**regmode) to 63); +signal spr_dvc2_dbg :std_ulogic_vector(64-(2**regmode) to 63); +signal ldq_rel_data_val_early :std_ulogic; +signal ldq_rel_op_size :std_ulogic_vector(0 to 5); +signal ldq_rel_addr :std_ulogic_vector(64-(dc_size-3) to 58); +signal ldq_rel_data_val :std_ulogic; +signal ldq_rel_rot_sel :std_ulogic_vector(0 to 4); +signal ldq_rel_axu_val :std_ulogic; +signal ldq_rel_ci :std_ulogic; +signal ldq_rel_thrd_id :std_ulogic_vector(0 to 3); +signal ldq_rel_le_mode :std_ulogic; +signal ldq_rel_algebraic :std_ulogic; +signal ldq_rel_256_data :std_ulogic_vector(0 to 255); +signal ldq_rel_dvc1_en :std_ulogic; +signal ldq_rel_dvc2_en :std_ulogic; +signal ldq_rel_beat_crit_qw :std_ulogic; +signal ldq_rel_beat_crit_qw_block :std_ulogic; +signal dec_spr_rf0_instr :std_ulogic_vector(0 to 31); +signal ctlspr_time_scan_in :std_ulogic; +signal ctlspr_time_scan_out :std_ulogic; +signal ctlspr_repr_scan_in :std_ulogic; +signal ctlspr_repr_scan_out :std_ulogic; +signal ctlspr_gptr_scan_in :std_ulogic; +signal ctlspr_gptr_scan_out :std_ulogic; +signal fxadat_time_scan_in :std_ulogic; +signal fxadat_time_scan_out :std_ulogic; +signal fxadat_repr_scan_in :std_ulogic; +signal fxadat_repr_scan_out :std_ulogic; +signal fxadat_gptr_scan_in :std_ulogic; +signal fxadat_gptr_scan_out :std_ulogic; +signal xu_lsu_spr_xucr0_dcdis :std_ulogic; +signal spr_xucr0_clkg_ctl_b0 :std_ulogic; +signal fxa_perf_muldiv_in_use :std_ulogic; +signal bolt_sl_thold_2 :std_ulogic; +signal bo_enable_2 :std_ulogic; +signal abst_scan_2 :std_ulogic; +signal xu_w_rf1_flush :std_ulogic_vector(0 to threads-1); +signal xu_w_ex1_flush :std_ulogic_vector(0 to threads-1); +signal xu_w_ex2_flush :std_ulogic_vector(0 to threads-1); +signal xu_w_ex3_flush :std_ulogic_vector(0 to threads-1); +signal xu_w_ex4_flush :std_ulogic_vector(0 to threads-1); +signal xu_w_ex5_flush :std_ulogic_vector(0 to threads-1); +signal xu_iu_flush :std_ulogic_vector(0 to 3); +signal spr_xucr4_mmu_mchk :std_ulogic; + +begin + + +fu_xu_ex1_ifar <= fu_xu_ex1_ifar0 & fu_xu_ex1_ifar1 & fu_xu_ex1_ifar2 & fu_xu_ex1_ifar3; +xu_iu_ici <= xu_lsu_ici; + +xu_mm_rf1_val <= xu_rf1_val; +xu_mm_rf1_is_eratilx <= xu_rf1_is_eratilx; +xu_mm_ex1_is_isync <= xu_ex1_is_isync; +xu_mm_ex1_is_csync <= xu_ex1_is_csync; +xu_mm_rf1_t <= xu_rf1_t; +xu_mm_ex1_rs_is <= xu_ex1_rs_is; +xu_mm_ex2_eff_addr <= xu_ex2_eff_addr; + +xu_iu_rf1_is_eratilx <= xu_rf1_is_eratilx; +xu_iu_ex1_is_isync <= xu_ex1_is_isync; +xu_iu_ex1_is_csync <= xu_ex1_is_csync; +xu_iu_rf1_ws <= xu_rf1_ws; +xu_iu_rf1_t <= xu_rf1_t; +xu_iu_ex1_rs_is <= xu_ex1_rs_is; +xu_iu_ex1_ra_entry <= xu_ex1_ra_entry(8 to 11); +xu_iu_ex4_rs_data <= xu_ex4_rs_data; + +xu_lsu_hid_mmu_mode <= spr_ccr2_notlb; +xu_iu_msr_gs <= xu_msr_gs; +xu_iu_msr_hv <= xu_msr_gs; +xu_iu_msr_pr <= xu_msr_pr; +xu_iu_msr_is <= xu_msr_is; +xu_iu_msr_cm <= xu_msr_cm; +xu_iu_hid_mmu_mode <= spr_ccr2_notlb; +xu_mm_msr_gs <= xu_msr_gs; +xu_mm_msr_pr <= xu_msr_pr; +xu_mm_msr_is <= xu_msr_is; +xu_mm_msr_ds <= xu_msr_ds; +xu_mm_msr_cm <= xu_msr_cm; +xu_mm_hid_mmu_mode <= spr_ccr2_notlb; +xu_fu_msr_gs <= cpl_msr_gs; +xu_fu_msr_pr <= cpl_msr_pr; +xu_fu_msr_fp <= cpl_msr_fp; +xu_fu_msr_spv <= cpl_msr_spv; +xu_fu_ccr2_ap <= cpl_ccr2_ap; + +xu_iu_xucr4_mmu_mchk <= spr_xucr4_mmu_mchk; +xu_mm_xucr4_mmu_mchk <= spr_xucr4_mmu_mchk; + +xu_n_is2_flush <= is2_flush; +xu_n_rf0_flush <= rf0_flush; +xu_n_rf1_flush <= rf1_flush; +xu_n_ex1_flush <= ex1_flush; +xu_n_ex2_flush <= ex2_flush; +xu_n_ex3_flush <= ex3_flush; +xu_n_ex4_flush <= ex4_flush; +xu_n_ex5_flush <= ex5_flush; + +xu_wu_rf1_flush <= xu_w_rf1_flush; +xu_wu_ex1_flush <= xu_w_ex1_flush; +xu_wu_ex2_flush <= xu_w_ex2_flush; +xu_wu_ex3_flush <= xu_w_ex3_flush; +xu_wu_ex4_flush <= xu_w_ex4_flush; +xu_wu_ex5_flush <= xu_w_ex5_flush; + +xu_wl_rf1_flush <= xu_w_rf1_flush; +xu_wl_ex1_flush <= xu_w_ex1_flush; +xu_wl_ex2_flush <= xu_w_ex2_flush; +xu_wl_ex3_flush <= xu_w_ex3_flush; +xu_wl_ex4_flush <= xu_w_ex4_flush; +xu_wl_ex5_flush <= xu_w_ex5_flush; + +xu_iu_u_flush <= xu_iu_flush; +xu_iu_l_flush <= xu_iu_flush; + +xu_iu_iu0_flush_ifar0 <= xu_iu_iu0_flush_ifar(0 to 1*eff_ifar-1); +xu_iu_iu0_flush_ifar1 <= xu_iu_iu0_flush_ifar(1*eff_ifar to 2*eff_ifar-1); +xu_iu_iu0_flush_ifar2 <= xu_iu_iu0_flush_ifar(2*eff_ifar to 3*eff_ifar-1); +xu_iu_iu0_flush_ifar3 <= xu_iu_iu0_flush_ifar(3*eff_ifar to 4*eff_ifar-1); +xu_iu_uc_flush_ifar0 <= xu_iu_uc_flush_ifar(0 to 1*uc_ifar-1); +xu_iu_uc_flush_ifar1 <= xu_iu_uc_flush_ifar(1*uc_ifar to 2*uc_ifar-1); +xu_iu_uc_flush_ifar2 <= xu_iu_uc_flush_ifar(2*uc_ifar to 3*uc_ifar-1); +xu_iu_uc_flush_ifar3 <= xu_iu_uc_flush_ifar(3*uc_ifar to 4*uc_ifar-1); +xu_iu_spr_xer0 <= xu_iu_spr_xer(0 to 6); +xu_iu_spr_xer1 <= xu_iu_spr_xer(7 to 13); +xu_iu_spr_xer2 <= xu_iu_spr_xer(14 to 20); +xu_iu_spr_xer3 <= xu_iu_spr_xer(21 to 27); + +xu_iu_set_barr_tid <= cpl_iu_set_barr_tid or fxa_iu_set_barr_tid; + +xu_iu_reld_core_tag <= an_ac_reld_core_tag(0 to 4); +xu_iu_reld_data <= an_ac_reld_data(0 to 127); +xu_iu_reld_data_vld <= an_ac_reld_data_vld; +xu_iu_reld_ecc_err <= an_ac_reld_ecc_err; +xu_iu_reld_ecc_err_ue <= an_ac_reld_ecc_err_ue; +xu_iu_reld_qw <= an_ac_reld_qw(57 to 59); + + +xu_fu_lbist_ary_wrt_thru_dc <= an_ac_lbist_ary_wrt_thru_dc; +xu_fu_lbist_en_dc <= an_ac_lbist_en_dc; + +fxu_debug_mux_ctrls <= pc_xu_debug_mux1_ctrls; +cpl_debug_mux_ctrls <= pc_xu_debug_mux2_ctrls; +lsu_debug_mux_ctrls <= pc_xu_debug_mux3_ctrls; +lsudat_debug_mux_ctrls <= pc_xu_debug_mux4_ctrls(2 to 3); +spr_debug_mux_ctrls <= pc_xu_debug_mux4_ctrls; + + + + + + +ctlspr : entity work.xuq_ctrl_spr(xuq_ctrl_spr) +generic map( + expand_type => expand_type, + threads => threads, + eff_ifar => eff_ifar, + uc_ifar => uc_ifar, + regsize => regsize, + hvmode => hvmode, + regmode => regmode, + dc_size => dc_size, + cl_size => cl_size, + real_data_add => real_data_add, + a2mode => a2mode, + lmq_entries => lmq_entries, + l_endian_m => l_endian_m, + load_credits => load_credits, + store_credits => store_credits, + st_data_32B_mode => st_data_32B_mode, + spr_xucr0_init_mod => spr_xucr0_init_mod, + bcfg_epn_0to15 => bcfg_epn_0to15, + bcfg_epn_16to31 => bcfg_epn_16to31, + bcfg_epn_32to47 => bcfg_epn_32to47, + bcfg_epn_48to51 => bcfg_epn_48to51, + bcfg_rpn_22to31 => bcfg_rpn_22to31, + bcfg_rpn_32to47 => bcfg_rpn_32to47, + bcfg_rpn_48to51 => bcfg_rpn_48to51) +port map( + + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b, + an_ac_lbist_en_dc => an_ac_lbist_en_dc, + pc_xu_abist_raddr_0 => pc_xu_abist_raddr_0(4 to 9), + pc_xu_abist_ena_dc => pc_xu_abist_ena_dc, + pc_xu_abist_waddr_0 => pc_xu_abist_waddr_0(4 to 9), + pc_xu_abist_di_0 => pc_xu_abist_di_0, + pc_xu_abist_raw_dc_b => pc_xu_abist_raw_dc_b, + pc_xu_ccflush_dc => pc_xu_ccflush_dc, + clkoff_dc_b => clkoff_dc_b, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc, + mpw1_dc_b => mpw1_dc_b, + mpw2_dc_b => mpw2_dc_b, + g6t_clkoff_dc_b => g6t_clkoff_dc_b, + g6t_d_mode_dc => g6t_d_mode_dc, + g6t_delay_lclkr_dc => g6t_delay_lclkr_dc, + g6t_mpw1_dc_b => g6t_mpw1_dc_b, + g6t_mpw2_dc_b => g6t_mpw2_dc_b, + pc_xu_sg_3 => pc_xu_sg_3, + pc_xu_func_sl_thold_3 => pc_xu_func_sl_thold_3, + pc_xu_func_slp_sl_thold_3 => pc_xu_func_slp_sl_thold_3, + pc_xu_func_nsl_thold_3 => pc_xu_func_nsl_thold_3, + pc_xu_func_slp_nsl_thold_3 => pc_xu_func_slp_nsl_thold_3, + pc_xu_gptr_sl_thold_3 => pc_xu_gptr_sl_thold_3, + pc_xu_abst_sl_thold_3 => pc_xu_abst_sl_thold_3, + pc_xu_abst_slp_sl_thold_3 => pc_xu_abst_slp_sl_thold_3, + pc_xu_regf_sl_thold_3 => pc_xu_regf_sl_thold_3, + pc_xu_regf_slp_sl_thold_3 => pc_xu_regf_slp_sl_thold_3, + pc_xu_time_sl_thold_3 => pc_xu_time_sl_thold_3, + pc_xu_cfg_sl_thold_3 => pc_xu_cfg_sl_thold_3, + pc_xu_cfg_slp_sl_thold_3 => pc_xu_cfg_slp_sl_thold_3, + pc_xu_ary_nsl_thold_3 => pc_xu_ary_nsl_thold_3, + pc_xu_ary_slp_nsl_thold_3 => pc_xu_ary_slp_nsl_thold_3, + pc_xu_repr_sl_thold_3 => pc_xu_repr_sl_thold_3, + pc_xu_fce_3 => pc_xu_fce_3, + an_ac_scan_diag_dc => an_ac_scan_diag_dc, + sg_2 => sg_2, + fce_2 => fce_2, + func_sl_thold_2 => func_sl_thold_2, + func_slp_sl_thold_2 => func_slp_sl_thold_2, + func_nsl_thold_2 => func_nsl_thold_2, + abst_sl_thold_2 => abst_sl_thold_2, + time_sl_thold_2 => time_sl_thold_2, + ary_nsl_thold_2 => ary_nsl_thold_2, + repr_sl_thold_2 => repr_sl_thold_2, + gptr_sl_thold_2 => gptr_sl_thold_2, + cfg_sl_thold_2 => cfg_sl_thold_2, + cfg_slp_sl_thold_2 => cfg_slp_sl_thold_2, + regf_slp_sl_thold_2 => regf_slp_sl_thold_2, + pc_xu_bolt_sl_thold_3 => pc_xu_bolt_sl_thold_3, + pc_xu_bo_enable_3 => pc_xu_bo_enable_3, + bolt_sl_thold_2 => bolt_sl_thold_2, + bo_enable_2 => bo_enable_2, + pc_xu_bo_unload => pc_xu_bo_unload, + pc_xu_bo_repair => pc_xu_bo_repair, + pc_xu_bo_reset => pc_xu_bo_reset, + pc_xu_bo_shdata => pc_xu_bo_shdata, + pc_xu_bo_select => pc_xu_bo_select(0 to 4), + xu_pc_bo_fail => xu_pc_bo_fail(0 to 4), + xu_pc_bo_diagout => xu_pc_bo_diagout(0 to 4), + + fxa_fxb_rf0_val => fxa_fxb_rf0_val, + fxa_fxb_rf0_issued => fxa_fxb_rf0_issued, + fxa_fxb_rf0_ucode_val => fxa_fxb_rf0_ucode_val, + fxa_fxb_rf0_act => fxa_fxb_rf0_act, + fxa_fxb_ex1_hold_ctr_flush => fxa_fxb_ex1_hold_ctr_flush, + fxa_fxb_rf0_instr => fxa_fxb_rf0_instr, + fxa_fxb_rf0_tid => fxa_fxb_rf0_tid, + fxa_fxb_rf0_ta_vld => fxa_fxb_rf0_ta_vld, + fxa_fxb_rf0_ta => fxa_fxb_rf0_ta, + fxa_fxb_rf0_error => fxa_fxb_rf0_error, + fxa_fxb_rf0_match => fxa_fxb_rf0_match, + fxa_fxb_rf0_is_ucode => fxa_fxb_rf0_is_ucode, + fxa_fxb_rf0_gshare => fxa_fxb_rf0_gshare, + fxa_fxb_rf0_ifar => fxa_fxb_rf0_ifar, + fxa_fxb_rf0_s1_vld => fxa_fxb_rf0_s1_vld, + fxa_fxb_rf0_s1 => fxa_fxb_rf0_s1, + fxa_fxb_rf0_s2_vld => fxa_fxb_rf0_s2_vld, + fxa_fxb_rf0_s2 => fxa_fxb_rf0_s2, + fxa_fxb_rf0_s3_vld => fxa_fxb_rf0_s3_vld, + fxa_fxb_rf0_s3 => fxa_fxb_rf0_s3, + fxa_fxb_rf0_axu_instr_type => fxa_fxb_rf0_axu_instr_type, + fxa_fxb_rf0_axu_ld_or_st => fxa_fxb_rf0_axu_ld_or_st, + fxa_fxb_rf0_axu_store => fxa_fxb_rf0_axu_store, + fxa_fxb_rf0_axu_ldst_forcealign => fxa_fxb_rf0_axu_ldst_forcealign, + fxa_fxb_rf0_axu_ldst_forceexcept => fxa_fxb_rf0_axu_ldst_forceexcept, + fxa_fxb_rf0_axu_ldst_indexed => fxa_fxb_rf0_axu_ldst_indexed, + fxa_fxb_rf0_axu_ldst_tag => fxa_fxb_rf0_axu_ldst_tag, + fxa_fxb_rf0_axu_mftgpr => fxa_fxb_rf0_axu_mftgpr, + fxa_fxb_rf0_axu_mffgpr => fxa_fxb_rf0_axu_mffgpr, + fxa_fxb_rf0_axu_movedp => fxa_fxb_rf0_axu_movedp, + fxa_fxb_rf0_axu_ldst_size => fxa_fxb_rf0_axu_ldst_size, + fxa_fxb_rf0_axu_ldst_update => fxa_fxb_rf0_axu_ldst_update, + fxa_fxb_rf0_pred_update => fxa_fxb_rf0_pred_update, + fxa_fxb_rf0_pred_taken_cnt => fxa_fxb_rf0_pred_taken_cnt, + fxa_fxb_rf0_mc_dep_chk_val => fxa_fxb_rf0_mc_dep_chk_val, + fxa_fxb_rf1_mul_val => fxa_fxb_rf1_mul_val, + fxa_fxb_rf1_div_val => fxa_fxb_rf1_div_val, + fxa_fxb_rf1_div_ctr => fxa_fxb_rf1_div_ctr, + fxa_fxb_rf0_xu_epid_instr => fxa_fxb_rf0_xu_epid_instr, + fxa_fxb_rf0_axu_is_extload => fxa_fxb_rf0_axu_is_extload, + fxa_fxb_rf0_axu_is_extstore => fxa_fxb_rf0_axu_is_extstore, + fxa_fxb_rf0_is_mfocrf => fxa_fxb_rf0_is_mfocrf, + fxa_fxb_rf0_3src_instr => fxa_fxb_rf0_3src_instr, + fxa_fxb_rf0_gpr0_zero => fxa_fxb_rf0_gpr0_zero, + fxa_fxb_rf0_use_imm => fxa_fxb_rf0_use_imm, + fxa_fxb_rf1_muldiv_coll => fxa_fxb_rf1_muldiv_coll, + fxa_cpl_ex2_div_coll => fxa_cpl_ex2_div_coll, + fxb_fxa_ex7_we0 => fxb_fxa_ex7_we0, + fxb_fxa_ex7_wa0 => fxb_fxa_ex7_wa0, + fxb_fxa_ex7_wd0 => fxb_fxa_ex7_wd0, + fxa_fxb_rf1_do0 => fxa_fxb_rf1_do0, + fxa_fxb_rf1_do1 => fxa_fxb_rf1_do1, + fxa_fxb_rf1_do2 => fxa_fxb_rf1_do2, + + xu_bx_ex1_mtdp_val => xu_bx_ex1_mtdp_val, + xu_bx_ex1_mfdp_val => xu_bx_ex1_mfdp_val, + xu_bx_ex1_ipc_thrd => xu_bx_ex1_ipc_thrd, + xu_bx_ex2_ipc_ba => xu_bx_ex2_ipc_ba, + xu_bx_ex2_ipc_sz => xu_bx_ex2_ipc_sz, + + xu_mm_derat_epn => xu_mm_derat_epn, + + xu_mm_rf1_is_tlbsxr => xu_mm_rf1_is_tlbsxr, + mm_xu_cr0_eq_valid => mm_xu_cr0_eq_valid, + mm_xu_cr0_eq => mm_xu_cr0_eq, + + fu_xu_ex4_cr_val => fu_xu_ex4_cr_val, + fu_xu_ex4_cr_noflush => fu_xu_ex4_cr_noflush, + fu_xu_ex4_cr0 => fu_xu_ex4_cr0, + fu_xu_ex4_cr0_bf => fu_xu_ex4_cr0_bf, + fu_xu_ex4_cr1 => fu_xu_ex4_cr1, + fu_xu_ex4_cr1_bf => fu_xu_ex4_cr1_bf, + fu_xu_ex4_cr2 => fu_xu_ex4_cr2, + fu_xu_ex4_cr2_bf => fu_xu_ex4_cr2_bf, + fu_xu_ex4_cr3 => fu_xu_ex4_cr3, + fu_xu_ex4_cr3_bf => fu_xu_ex4_cr3_bf, + + pc_xu_ram_mode => pc_xu_ram_mode, + pc_xu_ram_thread => pc_xu_ram_thread, + pc_xu_ram_execute => pc_xu_ram_execute, + pc_xu_ram_flush_thread => pc_xu_ram_flush_thread, + xu_iu_ram_issue => xu_iu_ram_issue, + xu_pc_ram_interrupt => xu_pc_ram_interrupt, + xu_pc_ram_done => xu_pc_ram_done, + xu_pc_ram_data => xu_pc_ram_data, + + pc_xu_msrovride_enab => pc_xu_msrovride_enab, + pc_xu_msrovride_gs => pc_xu_msrovride_gs, + pc_xu_msrovride_de => pc_xu_msrovride_de, + + xu_iu_ex5_val => xu_iu_ex5_val, + xu_iu_ex5_tid => xu_iu_ex5_tid, + xu_iu_ex5_br_update => xu_iu_ex5_br_update, + xu_iu_ex5_br_hist => xu_iu_ex5_br_hist, + xu_iu_ex5_bclr => xu_iu_ex5_bclr, + xu_iu_ex5_lk => xu_iu_ex5_lk, + xu_iu_ex5_bh => xu_iu_ex5_bh, + xu_iu_ex6_pri => xu_iu_ex6_pri, + xu_iu_ex6_pri_val => xu_iu_ex6_pri_val, + xu_iu_spr_xer => xu_iu_spr_xer, + xu_iu_slowspr_done => xu_iu_slowspr_done, + xu_iu_need_hole => xu_iu_need_hole, + fxb_fxa_ex6_clear_barrier => fxb_fxa_ex6_clear_barrier, + xu_iu_ex5_gshare => xu_iu_ex5_gshare, + xu_iu_ex5_getNIA => xu_iu_ex5_getNIA, + + an_ac_stcx_complete => an_ac_stcx_complete, + an_ac_stcx_pass => an_ac_stcx_pass, + xu_iu_stcx_complete => xu_iu_stcx_complete, + xu_iu_reld_core_tag_clone => xu_iu_reld_core_tag_clone, + xu_iu_reld_data_coming_clone => xu_iu_reld_data_coming_clone, + xu_iu_reld_data_vld_clone => xu_iu_reld_data_vld_clone, + xu_iu_reld_ditc_clone => xu_iu_reld_ditc_clone, + + slowspr_val_in => slowspr_val_in, + slowspr_rw_in => slowspr_rw_in, + slowspr_etid_in => slowspr_etid_in, + slowspr_addr_in => slowspr_addr_in, + slowspr_data_in => slowspr_data_in, + slowspr_done_in => slowspr_done_in, + slowspr_val_out => slowspr_val_out, + slowspr_rw_out => slowspr_rw_out, + slowspr_etid_out => slowspr_etid_out, + slowspr_addr_out => slowspr_addr_out, + slowspr_data_out => slowspr_data_out, + slowspr_done_out => slowspr_done_out, + + an_ac_dcr_act => tidn(0), + an_ac_dcr_val => tidn(0), + an_ac_dcr_read => tidn(0), + an_ac_dcr_etid => tidn(0 to 1), + an_ac_dcr_data => tidn(64-(2**regmode) to 63), + an_ac_dcr_done => tidn(0), + + lsu_xu_ex4_mtdp_cr_status => bx_xu_ex4_mtdp_cr_status, + lsu_xu_ex4_mfdp_cr_status => bx_xu_ex4_mfdp_cr_status, + dec_cpl_ex3_mc_dep_chk_val => dec_cpl_ex3_mc_dep_chk_val, + + fxa_perf_muldiv_in_use => fxa_perf_muldiv_in_use, + xu_pc_event_data => xu_pc_event_data, + + pc_xu_event_count_mode => pc_xu_event_count_mode, + pc_xu_event_mux_ctrls => pc_xu_event_mux_ctrls, + + spr_debug_mux_ctrls => spr_debug_mux_ctrls, + fxu_debug_mux_ctrls => fxu_debug_mux_ctrls, + cpl_debug_mux_ctrls => cpl_debug_mux_ctrls, + lsu_debug_mux_ctrls => lsu_debug_mux_ctrls, + trigger_data_in => trigger_data_in, + trigger_data_out => trigger_data_out, + debug_data_in => debug_data_in, + debug_data_out => debug_data_out, + lsu_xu_data_debug0 => lsu_xu_data_debug0, + lsu_xu_data_debug1 => lsu_xu_data_debug1, + lsu_xu_data_debug2 => lsu_xu_data_debug2, + fxa_cpl_debug => fxa_cpl_debug, + + ac_tc_debug_trigger => ac_tc_debug_trigger, + + dec_cpl_rf0_act => fxa_fxb_rf0_cpl_act, + dec_cpl_rf0_tid => fxa_fxb_rf0_cpl_tid, + + fu_xu_rf1_act => fu_xu_rf1_act, + fu_xu_ex1_ifar => fu_xu_ex1_ifar, + fu_xu_ex2_ifar_val => fu_xu_ex2_ifar_val, + fu_xu_ex2_ifar_issued => fu_xu_ex2_ifar_issued, + fu_xu_ex2_instr_type => fu_xu_ex2_instr_type, + fu_xu_ex2_instr_match => fu_xu_ex2_instr_match, + fu_xu_ex2_is_ucode => fu_xu_ex2_is_ucode, + + pc_xu_stop => pc_xu_stop, + pc_xu_step => pc_xu_step, + pc_xu_dbg_action => pc_xu_dbg_action, + pc_xu_force_ude => pc_xu_force_ude, + xu_pc_step_done => xu_pc_step_done, + pc_xu_init_reset => pc_xu_init_reset, + + mm_xu_local_snoop_reject => mm_xu_local_snoop_reject, + mm_xu_lru_par_err => mm_xu_lru_par_err, + mm_xu_tlb_par_err => mm_xu_tlb_par_err, + mm_xu_tlb_multihit_err => mm_xu_tlb_multihit_err, + an_ac_external_mchk => an_ac_external_mchk, + + xu_pc_err_attention_instr => xu_pc_err_attention_instr, + xu_pc_err_nia_miscmpr => xu_pc_err_nia_miscmpr, + xu_pc_err_debug_event => xu_pc_err_debug_event, + + xu_pc_stop_dbg_event => xu_pc_stop_dbg_event, + + mm_xu_illeg_instr => mm_xu_illeg_instr, + mm_xu_tlb_miss => mm_xu_tlb_miss, + mm_xu_pt_fault => mm_xu_pt_fault, + mm_xu_tlb_inelig => mm_xu_tlb_inelig, + mm_xu_lrat_miss => mm_xu_lrat_miss, + mm_xu_hv_priv => mm_xu_hv_priv, + mm_xu_esr_pt => mm_xu_esr_pt, + mm_xu_esr_data => mm_xu_esr_data, + mm_xu_esr_epid => mm_xu_esr_epid, + mm_xu_esr_st => mm_xu_esr_st, + mm_xu_hold_req => mm_xu_hold_req, + mm_xu_hold_done => mm_xu_hold_done, + xu_mm_hold_ack => xu_mm_hold_ack, + mm_xu_eratmiss_done => mm_xu_eratmiss_done, + mm_xu_ex3_flush_req => mm_xu_ex3_flush_req, + + fu_xu_ex3_ap_int_req => fu_xu_ex3_ap_int_req, + fu_xu_ex3_trap => fu_xu_ex3_trap, + fu_xu_ex3_n_flush => fu_xu_ex3_n_flush, + fu_xu_ex3_np1_flush => fu_xu_ex3_np1_flush, + fu_xu_ex3_flush2ucode => fu_xu_ex3_flush2ucode, + fu_xu_ex2_async_block => fu_xu_ex2_async_block, + + xu_iu_ex5_br_taken => xu_iu_ex5_br_taken, + xu_iu_ex5_ifar => xu_iu_ex5_ifar, + xu_iu_flush => xu_iu_flush, + xu_iu_iu0_flush_ifar => xu_iu_iu0_flush_ifar, + xu_iu_uc_flush_ifar => xu_iu_uc_flush_ifar, + xu_iu_flush_2ucode => xu_iu_flush_2ucode, + xu_iu_flush_2ucode_type => xu_iu_flush_2ucode_type, + xu_iu_ucode_restart => xu_iu_ucode_restart, + xu_iu_ex5_ppc_cpl => xu_iu_ex5_ppc_cpl, + + xu_n_is2_flush => is2_flush, + xu_n_rf0_flush => rf0_flush, + xu_n_rf1_flush => rf1_flush, + xu_n_ex1_flush => ex1_flush, + xu_n_ex2_flush => ex2_flush, + xu_n_ex3_flush => ex3_flush, + xu_n_ex4_flush => ex4_flush, + xu_n_ex5_flush => ex5_flush, + + xu_s_rf1_flush => xu_s_rf1_flush, + xu_s_ex1_flush => xu_s_ex1_flush, + xu_s_ex2_flush => xu_s_ex2_flush, + xu_s_ex3_flush => xu_s_ex3_flush, + xu_s_ex4_flush => xu_s_ex4_flush, + xu_s_ex5_flush => xu_s_ex5_flush, + + xu_w_rf1_flush => xu_w_rf1_flush, + xu_w_ex1_flush => xu_w_ex1_flush, + xu_w_ex2_flush => xu_w_ex2_flush, + xu_w_ex3_flush => xu_w_ex3_flush, + xu_w_ex4_flush => xu_w_ex4_flush, + xu_w_ex5_flush => xu_w_ex5_flush, + + xu_lsu_ex4_flush_local => xu_lsu_ex4_flush_local, + xu_mm_ex4_flush => xu_mm_ex4_flush, + xu_mm_ex5_flush => xu_mm_ex5_flush, + xu_mm_ierat_flush => xu_mm_ierat_flush, + xu_mm_ierat_miss => xu_mm_ierat_miss, + xu_mm_ex5_perf_itlb => xu_mm_ex5_perf_itlb, + xu_mm_ex5_perf_dtlb => xu_mm_ex5_perf_dtlb, + + spr_xucr4_div_barr_thres => spr_xucr4_div_barr_thres, + + iu_xu_ierat_ex2_flush_req => iu_xu_ierat_ex2_flush_req, + iu_xu_ierat_ex3_par_err => iu_xu_ierat_ex3_par_err, + iu_xu_ierat_ex4_par_err => iu_xu_ierat_ex4_par_err, + + fu_xu_ex3_regfile_err_det => fu_xu_ex3_regfile_err_det, + xu_fu_regfile_seq_beg => xu_fu_regfile_seq_beg, + fu_xu_regfile_seq_end => fu_xu_regfile_seq_end, + gpr_cpl_ex3_regfile_err_det => gpr_cpl_ex3_regfile_err_det, + cpl_gpr_regfile_seq_beg => cpl_gpr_regfile_seq_beg, + gpr_cpl_regfile_seq_end => gpr_cpl_regfile_seq_end, + xu_pc_err_mcsr_summary => xu_pc_err_mcsr_summary, + xu_pc_err_ditc_overrun => xu_pc_err_ditc_overrun, + xu_pc_err_local_snoop_reject => xu_pc_err_local_snoop_reject, + xu_pc_err_tlb_lru_parity => xu_pc_err_tlb_lru_parity, + xu_pc_err_ext_mchk => xu_pc_err_ext_mchk, + xu_pc_err_ierat_multihit => xu_pc_err_ierat_multihit, + xu_pc_err_derat_multihit => xu_pc_err_derat_multihit, + xu_pc_err_tlb_multihit => xu_pc_err_tlb_multihit, + xu_pc_err_ierat_parity => xu_pc_err_ierat_parity, + xu_pc_err_derat_parity => xu_pc_err_derat_parity, + xu_pc_err_tlb_parity => xu_pc_err_tlb_parity, + xu_pc_err_mchk_disabled => xu_pc_err_mchk_disabled, + + xu_iu_rf1_val => xu_iu_rf1_val, + xu_rf1_val => xu_rf1_val, + xu_rf1_is_tlbre => xu_mm_rf1_is_tlbre, + xu_rf1_is_tlbwe => xu_mm_rf1_is_tlbwe, + xu_rf1_is_tlbsx => xu_mm_rf1_is_tlbsx, + xu_rf1_is_tlbsrx => xu_mm_rf1_is_tlbsrx, + xu_rf1_is_tlbilx => xu_mm_rf1_is_tlbilx, + xu_rf1_is_tlbivax => xu_mm_rf1_is_tlbivax, + xu_rf1_is_eratre => xu_iu_rf1_is_eratre, + xu_rf1_is_eratwe => xu_iu_rf1_is_eratwe, + xu_rf1_is_eratsx => xu_iu_rf1_is_eratsx, + xu_rf1_is_eratilx => xu_rf1_is_eratilx, + xu_rf1_is_erativax => xu_mm_rf1_is_erativax, + xu_ex1_is_isync => xu_ex1_is_isync, + xu_ex1_is_csync => xu_ex1_is_csync, + xu_rf1_ws => xu_rf1_ws, + xu_rf1_t => xu_rf1_t, + xu_ex1_rs_is => xu_ex1_rs_is, + xu_ex1_ra_entry => xu_ex1_ra_entry, + xu_ex4_rs_data => xu_ex4_rs_data, + + xu_lsu_rf1_data_act => xu_lsu_rf1_data_act, + xu_lsu_rf1_axu_ldst_falign => xu_lsu_rf1_axu_ldst_falign, + xu_lsu_ex1_store_data => xu_lsu_ex1_store_data, + xu_lsu_ex1_rotsel_ovrd => xu_lsu_ex1_rotsel_ovrd, + xu_lsu_ex1_eff_addr => xu_lsu_ex1_eff_addr, + + cpl_fxa_ex5_set_barr => cpl_fxa_ex5_set_barr, + cpl_iu_set_barr_tid => cpl_iu_set_barr_tid, + + lsu_xu_ex6_datc_par_err => lsu_xu_ex6_datc_par_err, + + lsu_xu_rel_dvc1_en => lsu_xu_rel_dvc1_en, + lsu_xu_rel_dvc2_en => lsu_xu_rel_dvc2_en, + lsu_xu_ex2_dvc1_st_cmp => lsu_xu_ex2_dvc1_st_cmp, + lsu_xu_ex2_dvc2_st_cmp => lsu_xu_ex2_dvc2_st_cmp, + lsu_xu_ex8_dvc1_ld_cmp => lsu_xu_ex8_dvc1_ld_cmp, + lsu_xu_ex8_dvc2_ld_cmp => lsu_xu_ex8_dvc2_ld_cmp, + lsu_xu_rel_dvc_thrd_id => lsu_xu_rel_dvc_thrd_id, + lsu_xu_rel_dvc1_cmp => lsu_xu_rel_dvc1_cmp, + lsu_xu_rel_dvc2_cmp => lsu_xu_rel_dvc2_cmp, + + lsu_xu_rot_ex6_data_b => lsu_xu_rot_ex6_data_b, + lsu_xu_rot_rel_data => lsu_xu_rot_rel_data, + pc_xu_trace_bus_enable => pc_xu_trace_bus_enable, + pc_xu_instr_trace_mode => pc_xu_instr_trace_mode, + pc_xu_instr_trace_tid => pc_xu_instr_trace_tid, + iu_xu_ex4_tlb_data => iu_xu_ex4_tlb_data, + + pc_xu_inj_dcachedir_parity => pc_xu_inj_dcachedir_parity, + pc_xu_inj_dcachedir_multihit => pc_xu_inj_dcachedir_multihit, + + ex4_256st_data => ex4_256st_data, + an_ac_flh2l2_gate => an_ac_flh2l2_gate, + + xu_lsu_rf0_derat_val => xu_lsu_rf0_derat_val, + xu_lsu_rf0_derat_is_extload => xu_lsu_rf0_derat_is_extload, + xu_lsu_rf0_derat_is_extstore => xu_lsu_rf0_derat_is_extstore, + xu_lsu_hid_mmu_mode => xu_lsu_hid_mmu_mode, + ex6_ld_par_err => ex6_ld_par_err, + + xu_mm_derat_req => xu_mm_derat_req, + xu_mm_derat_thdid => xu_mm_derat_thdid, + xu_mm_derat_state => xu_mm_derat_state, + xu_mm_derat_tid => xu_mm_derat_tid, + xu_mm_derat_lpid => xu_mm_derat_lpid, + xu_mm_derat_ttype => xu_mm_derat_ttype, + mm_xu_derat_rel_val => mm_xu_derat_rel_val, + mm_xu_derat_rel_data => mm_xu_derat_rel_data, + mm_xu_derat_pid0 => mm_xu_derat_pid0, + mm_xu_derat_pid1 => mm_xu_derat_pid1, + mm_xu_derat_pid2 => mm_xu_derat_pid2, + mm_xu_derat_pid3 => mm_xu_derat_pid3, + mm_xu_derat_mmucr0_0 => mm_xu_derat_mmucr0_0, + mm_xu_derat_mmucr0_1 => mm_xu_derat_mmucr0_1, + mm_xu_derat_mmucr0_2 => mm_xu_derat_mmucr0_2, + mm_xu_derat_mmucr0_3 => mm_xu_derat_mmucr0_3, + xu_mm_derat_mmucr0 => xu_mm_derat_mmucr0, + xu_mm_derat_mmucr0_we => xu_mm_derat_mmucr0_we, + mm_xu_derat_mmucr1 => mm_xu_derat_mmucr1, + xu_mm_derat_mmucr1 => xu_mm_derat_mmucr1, + xu_mm_derat_mmucr1_we => xu_mm_derat_mmucr1_we, + mm_xu_derat_snoop_coming => mm_xu_derat_snoop_coming, + mm_xu_derat_snoop_val => mm_xu_derat_snoop_val, + mm_xu_derat_snoop_attr => mm_xu_derat_snoop_attr, + mm_xu_derat_snoop_vpn => mm_xu_derat_snoop_vpn, + xu_mm_derat_snoop_ack => xu_mm_derat_snoop_ack, + + ex1_optype1 => ex1_optype1, + ex1_optype2 => ex1_optype2, + ex1_optype4 => ex1_optype4, + ex1_optype8 => ex1_optype8, + ex1_optype16 => ex1_optype16, + ex1_optype32 => ex1_optype32, + ex1_saxu_instr => ex1_saxu_instr, + ex1_sdp_instr => ex1_sdp_instr, + ex1_stgpr_instr => ex1_stgpr_instr, + ex1_store_instr => ex1_store_instr, + ex1_axu_op_val => ex1_axu_op_val, + + ex3_algebraic => ex3_algebraic, + ex3_data_swap => ex3_data_swap, + ex3_thrd_id => ex3_thrd_id, + xu_fu_ex3_eff_addr => xu_fu_ex3_eff_addr, + xu_lsu_ici => xu_lsu_ici, + + rel_upd_dcarr_val => rel_upd_dcarr_val, + + xu_fu_ex5_reload_val => xu_fu_ex5_reload_val, + xu_fu_ex5_load_val => xu_fu_ex5_load_val, + xu_fu_ex5_load_tag => xu_fu_ex5_load_tag, + + dcarr_up_way_addr => dcarr_up_way_addr, + + ex4_load_op_hit => ex4_load_op_hit, + ex4_store_hit => ex4_store_hit, + ex4_axu_op_val => ex4_axu_op_val, + spr_dvc1_act => spr_dvc1_act, + spr_dvc2_act => spr_dvc2_act, + spr_dvc1_dbg => spr_dvc1_dbg, + spr_dvc2_dbg => spr_dvc2_dbg, + + an_ac_req_ld_pop => an_ac_req_ld_pop, + an_ac_req_st_pop => an_ac_req_st_pop, + an_ac_req_st_gather => an_ac_req_st_gather, + an_ac_req_st_pop_thrd => an_ac_req_st_pop_thrd, + an_ac_reld_data_vld => an_ac_reld_data_vld, + an_ac_reld_core_tag => an_ac_reld_core_tag, + an_ac_reld_qw => an_ac_reld_qw, + an_ac_reld_data => an_ac_reld_data, + an_ac_reld_data_coming => an_ac_reld_data_coming, + an_ac_reld_ditc => an_ac_reld_ditc, + an_ac_reld_crit_qw => an_ac_reld_crit_qw, + an_ac_reld_l1_dump => an_ac_reld_l1_dump, + an_ac_reld_ecc_err => an_ac_reld_ecc_err, + an_ac_reld_ecc_err_ue => an_ac_reld_ecc_err_ue, + an_ac_back_inv => an_ac_back_inv, + an_ac_back_inv_addr => an_ac_back_inv_addr, + an_ac_back_inv_target_bit1 => an_ac_back_inv_target_bit1, + an_ac_back_inv_target_bit3 => an_ac_back_inv_target_bit3, + an_ac_back_inv_target_bit4 => an_ac_back_inv_target_bit4, + an_ac_req_spare_ctrl_a1 => an_ac_req_spare_ctrl_a1, + + lsu_reld_data_vld => lsu_reld_data_vld, + lsu_reld_core_tag => lsu_reld_core_tag, + lsu_reld_qw => lsu_reld_qw, + lsu_reld_ditc => lsu_reld_ditc, + lsu_reld_ecc_err => lsu_reld_ecc_err, + lsu_reld_data => lsu_reld_data, + + lsu_req_st_pop => lsu_req_st_pop, + lsu_req_st_pop_thrd => lsu_req_st_pop_thrd, + + ac_an_reld_ditc_pop_int => ac_an_reld_ditc_pop_int, + ac_an_reld_ditc_pop_q => ac_an_reld_ditc_pop_q , + bx_ib_empty_int => bx_ib_empty_int , + bx_ib_empty_q => bx_ib_empty_q , + + iu_xu_ra => iu_xu_ra, + iu_xu_request => iu_xu_request, + iu_xu_wimge => iu_xu_wimge, + iu_xu_thread => iu_xu_thread, + iu_xu_userdef => iu_xu_userdef, + + mm_xu_lsu_req => mm_xu_lsu_req, + mm_xu_lsu_ttype => mm_xu_lsu_ttype, + mm_xu_lsu_wimge => mm_xu_lsu_wimge, + mm_xu_lsu_u => mm_xu_lsu_u, + mm_xu_lsu_addr => mm_xu_lsu_addr, + mm_xu_lsu_lpid => mm_xu_lsu_lpid, + mm_xu_lsu_lpidr => mm_xu_lsu_lpidr, + mm_xu_lsu_gs => mm_xu_lsu_gs, + mm_xu_lsu_ind => mm_xu_lsu_ind, + mm_xu_lsu_lbit => mm_xu_lsu_lbit, + xu_mm_lsu_token => xu_mm_lsu_token, + + bx_lsu_ob_pwr_tok => bx_lsu_ob_pwr_tok, + bx_lsu_ob_req_val => bx_lsu_ob_req_val, + bx_lsu_ob_ditc_val => bx_lsu_ob_ditc_val, + bx_lsu_ob_thrd => bx_lsu_ob_thrd, + bx_lsu_ob_qw => bx_lsu_ob_qw, + bx_lsu_ob_dest => bx_lsu_ob_dest, + bx_lsu_ob_data => bx_lsu_ob_data, + bx_lsu_ob_addr => bx_lsu_ob_addr, + lsu_bx_cmd_avail => lsu_bx_cmd_avail, + lsu_bx_cmd_sent => lsu_bx_cmd_sent, + lsu_bx_cmd_stall => lsu_bx_cmd_stall, + + lsu_xu_ldq_barr_done => lsu_xu_ldq_barr_done, + lsu_xu_barr_done => lsu_xu_barr_done, + + ldq_rel_data_val_early => ldq_rel_data_val_early, + ldq_rel_op_size => ldq_rel_op_size, + ldq_rel_addr => ldq_rel_addr, + ldq_rel_data_val => ldq_rel_data_val, + ldq_rel_rot_sel => ldq_rel_rot_sel, + ldq_rel_axu_val => ldq_rel_axu_val, + ldq_rel_ci => ldq_rel_ci, + ldq_rel_thrd_id => ldq_rel_thrd_id, + ldq_rel_le_mode => ldq_rel_le_mode, + ldq_rel_algebraic => ldq_rel_algebraic, + ldq_rel_256_data => ldq_rel_256_data, + ldq_rel_dvc1_en => ldq_rel_dvc1_en, + ldq_rel_dvc2_en => ldq_rel_dvc2_en, + ldq_rel_beat_crit_qw => ldq_rel_beat_crit_qw, + ldq_rel_beat_crit_qw_block => ldq_rel_beat_crit_qw_block, + lsu_xu_rel_wren => lsu_xu_rel_wren, + lsu_xu_rel_ta_gpr => lsu_xu_rel_ta_gpr, + + xu_iu_ex4_loadmiss_qentry => xu_iu_ex4_loadmiss_qentry, + xu_iu_ex4_loadmiss_target => xu_iu_ex4_loadmiss_target, + xu_iu_ex4_loadmiss_target_type => xu_iu_ex4_loadmiss_target_type, + xu_iu_ex4_loadmiss_tid => xu_iu_ex4_loadmiss_tid, + xu_iu_ex5_loadmiss_qentry => xu_iu_ex5_loadmiss_qentry, + xu_iu_ex5_loadmiss_target => xu_iu_ex5_loadmiss_target, + xu_iu_ex5_loadmiss_target_type => xu_iu_ex5_loadmiss_target_type, + xu_iu_ex5_loadmiss_tid => xu_iu_ex5_loadmiss_tid, + xu_iu_complete_qentry => xu_iu_complete_qentry, + xu_iu_complete_tid => xu_iu_complete_tid, + xu_iu_complete_target_type => xu_iu_complete_target_type, + + xu_iu_ex6_icbi_val => xu_iu_ex6_icbi_val, + xu_iu_ex6_icbi_addr => xu_iu_ex6_icbi_addr, + + xu_iu_larx_done_tid => xu_iu_larx_done_tid, + xu_mm_lmq_stq_empty => xu_mm_lmq_stq_empty, + + xu_ex1_rb => xu_iu_ex1_rb, + xu_ex2_eff_addr => xu_ex2_eff_addr, + + ac_an_req_pwr_token => ac_an_req_pwr_token, + ac_an_req => ac_an_req, + ac_an_req_ra => ac_an_req_ra, + ac_an_req_ttype => ac_an_req_ttype, + ac_an_req_thread => ac_an_req_thread, + ac_an_req_wimg_w => ac_an_req_wimg_w, + ac_an_req_wimg_i => ac_an_req_wimg_i, + ac_an_req_wimg_m => ac_an_req_wimg_m, + ac_an_req_wimg_g => ac_an_req_wimg_g, + ac_an_req_endian => ac_an_req_endian, + ac_an_req_user_defined => ac_an_req_user_defined, + ac_an_req_spare_ctrl_a0 => ac_an_req_spare_ctrl_a0, + ac_an_req_ld_core_tag => ac_an_req_ld_core_tag, + ac_an_req_ld_xfr_len => ac_an_req_ld_xfr_len, + ac_an_st_byte_enbl => ac_an_st_byte_enbl, + ac_an_st_data => ac_an_st_data, + ac_an_st_data_pwr_token => ac_an_st_data_pwr_token, + + xu_pc_err_dcachedir_parity => xu_pc_err_dcachedir_parity, + xu_pc_err_dcachedir_multihit => xu_pc_err_dcachedir_multihit, + xu_pc_err_l2intrf_ecc => xu_pc_err_l2intrf_ecc, + xu_pc_err_l2intrf_ue => xu_pc_err_l2intrf_ue, + xu_pc_err_invld_reld => xu_pc_err_invld_reld, + xu_pc_err_l2credit_overrun => xu_pc_err_l2credit_overrun, + + pc_xu_event_bus_enable => pc_xu_event_bus_enable, + pc_xu_lsu_event_mux_ctrls => pc_xu_lsu_event_mux_ctrls, + pc_xu_cache_par_err_event => pc_xu_cache_par_err_event, + xu_pc_lsu_event_data => xu_pc_lsu_event_data, + + + dec_spr_rf0_tid => fxa_fxb_rf0_spr_tid, + dec_spr_rf0_instr => dec_spr_rf0_instr, + + ac_an_dcr_act => open, + ac_an_dcr_val => open, + ac_an_dcr_read => open, + ac_an_dcr_user => open, + ac_an_dcr_etid => open, + ac_an_dcr_addr => open, + ac_an_dcr_data => open, + + xu_pc_running => xu_pc_running, + xu_iu_run_thread => xu_iu_run_thread, + xu_iu_single_instr_mode => xu_iu_single_instr_mode, + xu_iu_raise_iss_pri => xu_iu_raise_iss_pri, + xu_pc_spr_ccr0_we => xu_pc_spr_ccr0_we, + + iu_xu_quiesce => iu_xu_quiesce, + mm_xu_quiesce => mm_xu_quiesce, + bx_xu_quiesce => bx_xu_quiesce, + + pc_xu_extirpts_dis_on_stop => pc_xu_extirpts_dis_on_stop, + pc_xu_timebase_dis_on_stop => pc_xu_timebase_dis_on_stop, + pc_xu_decrem_dis_on_stop => pc_xu_decrem_dis_on_stop, + + pc_xu_msrovride_pr => pc_xu_msrovride_pr, + + xu_pc_err_llbust_attempt => xu_pc_err_llbust_attempt, + xu_pc_err_llbust_failed => xu_pc_err_llbust_failed, + + pc_xu_reset_wd_complete => pc_xu_reset_wd_complete, + pc_xu_reset_1_complete => pc_xu_reset_1_complete, + pc_xu_reset_2_complete => pc_xu_reset_2_complete, + pc_xu_reset_3_complete => pc_xu_reset_3_complete, + ac_tc_reset_1_request => ac_tc_reset_1_request, + ac_tc_reset_2_request => ac_tc_reset_2_request, + ac_tc_reset_3_request => ac_tc_reset_3_request, + ac_tc_reset_wd_request => ac_tc_reset_wd_request, + + pc_xu_inj_llbust_attempt => pc_xu_inj_llbust_attempt, + pc_xu_inj_llbust_failed => pc_xu_inj_llbust_failed, + pc_xu_inj_wdt_reset => pc_xu_inj_wdt_reset, + xu_pc_err_wdt_reset => xu_pc_err_wdt_reset, + + pc_xu_inj_sprg_ecc => pc_xu_inj_sprg_ecc, + xu_pc_err_sprg_ecc => xu_pc_err_sprg_ecc, + xu_pc_err_sprg_ue => xu_pc_err_sprg_ue, + + spr_msr_cm => xu_msr_cm, + spr_msr_gs => xu_msr_gs, + spr_msr_pr => xu_msr_pr, + spr_msr_is => xu_msr_is, + spr_msr_ds => xu_msr_ds, + spr_ccr2_en_dcr => xu_iu_spr_ccr2_en_dcr, + spr_ccr2_notlb => spr_ccr2_notlb, + spr_ccr2_en_ditc => xu_bx_ccr2_en_ditc, + xu_lsu_spr_xucr0_dcdis => xu_lsu_spr_xucr0_dcdis, + xu_lsu_spr_xucr0_rel => xu_iu_xucr0_rel, + xu_pc_spr_ccr0_pme => xu_pc_spr_ccr0_pme, + xu_iu_spr_ccr2_ifratsc => xu_iu_spr_ccr2_ifratsc, + xu_iu_spr_ccr2_ifrat => xu_iu_spr_ccr2_ifrat, + spr_xucr0_clkg_ctl_b0 => spr_xucr0_clkg_ctl_b0, + xu_mm_spr_epcr_dmiuh => xu_mm_spr_epcr_dmiuh, + xu_mm_spr_epcr_dgtmi => xu_mm_spr_epcr_dgtmi, + cpl_msr_gs => cpl_msr_gs, + cpl_msr_pr => cpl_msr_pr, + cpl_msr_fp => cpl_msr_fp, + cpl_msr_spv => cpl_msr_spv, + cpl_ccr2_ap => cpl_ccr2_ap, + spr_xucr4_mmu_mchk => spr_xucr4_mmu_mchk, + + an_ac_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc, + ac_tc_machine_check => ac_tc_machine_check, + pc_xu_abist_g8t_wenb => pc_xu_abist_g8t_wenb, + pc_xu_abist_g8t1p_renb_0 => pc_xu_abist_g8t1p_renb_0, + pc_xu_abist_g8t_bw_1 => pc_xu_abist_g8t_bw_1, + pc_xu_abist_g8t_bw_0 => pc_xu_abist_g8t_bw_0, + pc_xu_abist_wl32_comp_ena => pc_xu_abist_wl32_comp_ena, + pc_xu_abist_g8t_dcomp => pc_xu_abist_g8t_dcomp, + + vcs => vcs, + vdd => vdd, + gnd => gnd, + nclk => nclk, + an_ac_coreid => an_ac_coreid, + spr_pvr_version_dc => spr_pvr_version_dc, + spr_pvr_revision_dc => spr_pvr_revision_dc, + an_ac_atpg_en_dc => an_ac_atpg_en_dc, + an_ac_ext_interrupt => an_ac_ext_interrupt, + an_ac_crit_interrupt => an_ac_crit_interrupt, + an_ac_perf_interrupt => an_ac_perf_interrupt, + an_ac_reservation_vld => an_ac_reservation_vld, + an_ac_tb_update_pulse => an_ac_tb_update_pulse, + an_ac_hang_pulse => an_ac_hang_pulse, + an_ac_tb_update_enable => an_ac_tb_update_enable, + an_ac_sleep_en => an_ac_sleep_en, + an_ac_grffence_en_dc => an_ac_grffence_en_dc, + + func_scan_in => func_scan_in(35 to 58), + func_scan_out => func_scan_out(35 to 58), + gptr_scan_in => ctlspr_gptr_scan_in, + gptr_scan_out => ctlspr_gptr_scan_out, + bcfg_scan_in => bcfg_scan_in, + bcfg_scan_out => bcfg_scan_out, + dcfg_scan_in => dcfg_scan_in, + dcfg_scan_out => dcfg_scan_out, + ccfg_scan_in => ccfg_scan_in, + ccfg_scan_out => ccfg_scan_out, + regf_scan_in => regf_scan_in, + regf_scan_out => regf_scan_out, + time_scan_in => ctlspr_time_scan_in, + time_scan_out => ctlspr_time_scan_out, + abst_scan_in(0) => abst_scan_in(0), + abst_scan_in(1) => abst_scan_in(2), + abst_scan_out(0) => abst_scan_out(0), + abst_scan_out(1) => abst_scan_2, + repr_scan_in => ctlspr_repr_scan_in, + repr_scan_out => ctlspr_repr_scan_out +); + + +fxadat : entity work.xuq_fxua_data(xuq_fxua_data) +generic map( + expand_type => expand_type, + regmode => regmode, + dc_size => dc_size, + cl_size => cl_size, + l_endian_m => l_endian_m, + threads => threads, + eff_ifar => eff_ifar, + regsize => regsize, + a2mode => a2mode, + hvmode => hvmode, + real_data_add => real_data_add) +port map( + + pc_xu_abist_raddr_0 => pc_xu_abist_raddr_0(1 to 9), + pc_xu_abist_raddr_1 => pc_xu_abist_raddr_1(2 to 9), + pc_xu_abist_grf_renb_0 => pc_xu_abist_grf_renb_0, + pc_xu_abist_grf_renb_1 => pc_xu_abist_grf_renb_1, + pc_xu_abist_ena_dc => pc_xu_abist_ena_dc, + pc_xu_abist_waddr_0 => pc_xu_abist_waddr_0(2 to 9), + pc_xu_abist_waddr_1 => pc_xu_abist_waddr_1(2 to 9), + pc_xu_abist_grf_wenb_0 => pc_xu_abist_grf_wenb_0, + pc_xu_abist_grf_wenb_1 => pc_xu_abist_grf_wenb_1, + pc_xu_abist_di_0 => pc_xu_abist_di_0, + pc_xu_abist_di_1 => pc_xu_abist_di_1, + pc_xu_abist_wl144_comp_ena => pc_xu_abist_wl144_comp_ena, + pc_xu_abist_raw_dc_b => pc_xu_abist_raw_dc_b, + pc_xu_ccflush_dc => pc_xu_ccflush_dc, + clkoff_dc_b => clkoff_dc_b, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc(4 to 4), + mpw1_dc_b => mpw1_dc_b(4 to 4), + mpw2_dc_b => mpw2_dc_b, + g6t_clkoff_dc_b => g6t_clkoff_dc_b, + g6t_d_mode_dc => g6t_d_mode_dc, + g6t_delay_lclkr_dc => g6t_delay_lclkr_dc, + g6t_mpw1_dc_b => g6t_mpw1_dc_b, + g6t_mpw2_dc_b => g6t_mpw2_dc_b, + an_ac_scan_diag_dc => an_ac_scan_diag_dc, + an_ac_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc, + sg_2 => sg_2(0 to 2), + fce_2 => fce_2(0 to 0), + func_sl_thold_2 => func_sl_thold_2, + func_nsl_thold_2 => func_nsl_thold_2, + abst_sl_thold_2 => abst_sl_thold_2, + time_sl_thold_2 => time_sl_thold_2, + ary_nsl_thold_2 => ary_nsl_thold_2, + repr_sl_thold_2 => repr_sl_thold_2, + gptr_sl_thold_2 => gptr_sl_thold_2, + bolt_sl_thold_2 => bolt_sl_thold_2, + bo_enable_2 => bo_enable_2, + pc_xu_bo_unload => pc_xu_bo_unload, + pc_xu_bo_load => pc_xu_bo_load, + pc_xu_bo_repair => pc_xu_bo_repair, + pc_xu_bo_reset => pc_xu_bo_reset, + pc_xu_bo_shdata => pc_xu_bo_shdata, + pc_xu_bo_select => pc_xu_bo_select(5 to 8), + xu_pc_bo_fail => xu_pc_bo_fail(5 to 8), + xu_pc_bo_diagout => xu_pc_bo_diagout(5 to 8), + + iu_xu_is2_vld => iu_xu_is2_vld, + iu_xu_is2_ifar => iu_xu_is2_ifar, + iu_xu_is2_tid => iu_xu_is2_tid, + iu_xu_is2_instr => iu_xu_is2_instr, + iu_xu_is2_ta_vld => iu_xu_is2_ta_vld, + iu_xu_is2_ta => iu_xu_is2_ta, + iu_xu_is2_s1_vld => iu_xu_is2_s1_vld, + iu_xu_is2_s1 => iu_xu_is2_s1, + iu_xu_is2_s2_vld => iu_xu_is2_s2_vld, + iu_xu_is2_s2 => iu_xu_is2_s2, + iu_xu_is2_s3_vld => iu_xu_is2_s3_vld, + iu_xu_is2_s3 => iu_xu_is2_s3, + iu_xu_is2_axu_ld_or_st => iu_xu_is2_axu_ld_or_st, + iu_xu_is2_axu_store => iu_xu_is2_axu_store, + iu_xu_is2_axu_ldst_size => iu_xu_is2_axu_ldst_size, + iu_xu_is2_axu_ldst_update => iu_xu_is2_axu_ldst_update, + iu_xu_is2_axu_ldst_forcealign => iu_xu_is2_axu_ldst_forcealign, + iu_xu_is2_axu_ldst_forceexcept => iu_xu_is2_axu_ldst_forceexcept, + iu_xu_is2_axu_ldst_extpid => iu_xu_is2_axu_ldst_extpid, + iu_xu_is2_axu_ldst_indexed => iu_xu_is2_axu_ldst_indexed, + iu_xu_is2_axu_ldst_tag => iu_xu_is2_axu_ldst_tag, + iu_xu_is2_axu_mftgpr => iu_xu_is2_axu_mftgpr, + iu_xu_is2_axu_mffgpr => iu_xu_is2_axu_mffgpr, + iu_xu_is2_axu_movedp => iu_xu_is2_axu_movedp, + iu_xu_is2_axu_instr_type => iu_xu_is2_axu_instr_type, + iu_xu_is2_pred_update => iu_xu_is2_pred_update, + iu_xu_is2_pred_taken_cnt => iu_xu_is2_pred_taken_cnt, + iu_xu_is2_error => iu_xu_is2_error, + iu_xu_is2_match => iu_xu_is2_match, + iu_xu_is2_is_ucode => iu_xu_is2_is_ucode, + iu_xu_is2_ucode_vld => iu_xu_is2_ucode_vld, + iu_xu_is2_gshare => iu_xu_is2_gshare, + xu_iu_multdiv_done => xu_iu_multdiv_done, + xu_iu_membar_tid => xu_iu_membar_tid, + + lsu_xu_ldq_barr_done => lsu_xu_ldq_barr_done, + lsu_xu_barr_done => lsu_xu_barr_done, + + fxa_fxb_rf0_val => fxa_fxb_rf0_val, + fxa_fxb_rf0_issued => fxa_fxb_rf0_issued, + fxa_fxb_rf0_ucode_val => fxa_fxb_rf0_ucode_val, + fxa_fxb_rf0_act => fxa_fxb_rf0_act, + fxa_fxb_ex1_hold_ctr_flush => fxa_fxb_ex1_hold_ctr_flush, + fxa_fxb_rf0_instr => fxa_fxb_rf0_instr, + fxa_fxb_rf0_tid => fxa_fxb_rf0_tid, + fxa_fxb_rf0_ta_vld => fxa_fxb_rf0_ta_vld, + fxa_fxb_rf0_ta => fxa_fxb_rf0_ta, + fxa_fxb_rf0_error => fxa_fxb_rf0_error, + fxa_fxb_rf0_match => fxa_fxb_rf0_match, + fxa_fxb_rf0_is_ucode => fxa_fxb_rf0_is_ucode, + fxa_fxb_rf0_gshare => fxa_fxb_rf0_gshare, + fxa_fxb_rf0_ifar => fxa_fxb_rf0_ifar, + fxa_fxb_rf0_s1_vld => fxa_fxb_rf0_s1_vld, + fxa_fxb_rf0_s1 => fxa_fxb_rf0_s1, + fxa_fxb_rf0_s2_vld => fxa_fxb_rf0_s2_vld, + fxa_fxb_rf0_s2 => fxa_fxb_rf0_s2, + fxa_fxb_rf0_s3_vld => fxa_fxb_rf0_s3_vld, + fxa_fxb_rf0_s3 => fxa_fxb_rf0_s3, + fxa_fxb_rf0_axu_instr_type => fxa_fxb_rf0_axu_instr_type, + fxa_fxb_rf0_axu_ld_or_st => fxa_fxb_rf0_axu_ld_or_st, + fxa_fxb_rf0_axu_store => fxa_fxb_rf0_axu_store, + fxa_fxb_rf0_axu_mftgpr => fxa_fxb_rf0_axu_mftgpr, + fxa_fxb_rf0_axu_mffgpr => fxa_fxb_rf0_axu_mffgpr, + fxa_fxb_rf0_axu_movedp => fxa_fxb_rf0_axu_movedp, + fxa_fxb_rf0_axu_ldst_size => fxa_fxb_rf0_axu_ldst_size, + fxa_fxb_rf0_axu_ldst_update => fxa_fxb_rf0_axu_ldst_update, + fxa_fxb_rf0_axu_ldst_forcealign => fxa_fxb_rf0_axu_ldst_forcealign, + fxa_fxb_rf0_axu_ldst_forceexcept => fxa_fxb_rf0_axu_ldst_forceexcept, + fxa_fxb_rf0_axu_ldst_indexed => fxa_fxb_rf0_axu_ldst_indexed, + fxa_fxb_rf0_axu_ldst_tag => fxa_fxb_rf0_axu_ldst_tag, + fxa_fxb_rf0_pred_update => fxa_fxb_rf0_pred_update, + fxa_fxb_rf0_pred_taken_cnt => fxa_fxb_rf0_pred_taken_cnt, + fxa_fxb_rf0_mc_dep_chk_val => fxa_fxb_rf0_mc_dep_chk_val, + fxa_fxb_rf1_mul_val => fxa_fxb_rf1_mul_val, + fxa_fxb_rf1_muldiv_coll => fxa_fxb_rf1_muldiv_coll, + fxa_fxb_rf1_div_val => fxa_fxb_rf1_div_val, + fxa_fxb_rf1_div_ctr => fxa_fxb_rf1_div_ctr, + fxa_fxb_rf0_xu_epid_instr => fxa_fxb_rf0_xu_epid_instr, + fxa_fxb_rf0_axu_is_extload => fxa_fxb_rf0_axu_is_extload, + fxa_fxb_rf0_axu_is_extstore => fxa_fxb_rf0_axu_is_extstore, + fxa_fxb_rf0_spr_tid => fxa_fxb_rf0_spr_tid, + fxa_fxb_rf0_cpl_tid => fxa_fxb_rf0_cpl_tid, + fxa_fxb_rf0_cpl_act => fxa_fxb_rf0_cpl_act, + fxa_fxb_rf0_is_mfocrf => fxa_fxb_rf0_is_mfocrf, + fxa_fxb_rf0_3src_instr => fxa_fxb_rf0_3src_instr, + fxa_fxb_rf0_gpr0_zero => fxa_fxb_rf0_gpr0_zero, + fxa_fxb_rf0_use_imm => fxa_fxb_rf0_use_imm, + dec_cpl_ex3_mc_dep_chk_val => dec_cpl_ex3_mc_dep_chk_val, + fxb_fxa_ex7_we0 => fxb_fxa_ex7_we0, + fxb_fxa_ex7_wa0 => fxb_fxa_ex7_wa0, + fxb_fxa_ex7_wd0 => fxb_fxa_ex7_wd0, + fxa_fxb_rf1_do0 => fxa_fxb_rf1_do0, + fxa_fxb_rf1_do1 => fxa_fxb_rf1_do1, + fxa_fxb_rf1_do2 => fxa_fxb_rf1_do2, + fxb_fxa_ex6_clear_barrier => fxb_fxa_ex6_clear_barrier, + fxa_perf_muldiv_in_use => fxa_perf_muldiv_in_use, + + xu_is2_flush => is2_flush, + xu_rf0_flush => rf0_flush, + xu_rf1_flush => rf1_flush, + xu_ex1_flush => ex1_flush, + xu_ex2_flush => ex2_flush, + xu_ex3_flush => ex3_flush, + xu_ex4_flush => ex4_flush, + xu_ex5_flush => ex5_flush, + fxa_cpl_ex2_div_coll => fxa_cpl_ex2_div_coll, + cpl_fxa_ex5_set_barr => cpl_fxa_ex5_set_barr, + fxa_iu_set_barr_tid => fxa_iu_set_barr_tid, + spr_xucr4_div_barr_thres => spr_xucr4_div_barr_thres, + + an_ac_back_inv => an_ac_back_inv, + an_ac_back_inv_addr => an_ac_back_inv_addr(62 to 63), + an_ac_back_inv_target_bit3 => an_ac_back_inv_target_bit3, + + dec_spr_rf0_instr => dec_spr_rf0_instr, + + pc_xu_inj_regfile_parity => pc_xu_inj_regfile_parity, + xu_pc_err_regfile_parity => xu_pc_err_regfile_parity, + xu_pc_err_regfile_ue => xu_pc_err_regfile_ue, + gpr_cpl_ex3_regfile_err_det => gpr_cpl_ex3_regfile_err_det, + cpl_gpr_regfile_seq_beg => cpl_gpr_regfile_seq_beg, + gpr_cpl_regfile_seq_end => gpr_cpl_regfile_seq_end, + + xu_lsu_rf0_derat_val => xu_lsu_rf0_derat_val, + xu_lsu_rf0_derat_is_extload => xu_lsu_rf0_derat_is_extload, + xu_lsu_rf0_derat_is_extstore => xu_lsu_rf0_derat_is_extstore, + lsu_xu_rel_wren => lsu_xu_rel_wren, + lsu_xu_rel_ta_gpr => lsu_xu_rel_ta_gpr, + fxa_cpl_debug => fxa_cpl_debug, + + xu_lsu_rf1_data_act => xu_lsu_rf1_data_act, + xu_lsu_rf1_axu_ldst_falign => xu_lsu_rf1_axu_ldst_falign, + xu_lsu_ex1_store_data => xu_lsu_ex1_store_data, + xu_lsu_ex1_eff_addr => xu_lsu_ex1_eff_addr, + xu_lsu_ex1_rotsel_ovrd => xu_lsu_ex1_rotsel_ovrd, + ex1_optype1 => ex1_optype1, + ex1_optype2 => ex1_optype2, + ex1_optype4 => ex1_optype4, + ex1_optype8 => ex1_optype8, + ex1_optype16 => ex1_optype16, + ex1_optype32 => ex1_optype32, + ex1_saxu_instr => ex1_saxu_instr, + ex1_sdp_instr => ex1_sdp_instr, + ex1_stgpr_instr => ex1_stgpr_instr, + ex1_store_instr => ex1_store_instr, + ex1_axu_op_val => ex1_axu_op_val, + + fu_xu_ex2_store_data_val => fu_xu_ex2_store_data_val, + fu_xu_ex2_store_data => fu_xu_ex2_store_data, + + ex3_algebraic => ex3_algebraic, + ex3_data_swap => ex3_data_swap, + ex3_thrd_id => ex3_thrd_id, + bx_xu_ex5_dp_data => bx_xu_ex5_dp_data, + + ex4_load_op_hit => ex4_load_op_hit, + ex4_store_hit => ex4_store_hit, + ex4_axu_op_val => ex4_axu_op_val, + spr_dvc1_act => spr_dvc1_act, + spr_dvc2_act => spr_dvc2_act, + spr_dvc1_dbg => spr_dvc1_dbg, + spr_dvc2_dbg => spr_dvc2_dbg, + + rel_upd_dcarr_val => rel_upd_dcarr_val, + + xu_lsu_ex4_flush_local => xu_lsu_ex4_flush_local, + + xu_pc_err_dcache_parity => xu_pc_err_dcache_parity, + pc_xu_inj_dcache_parity => pc_xu_inj_dcache_parity, + + xu_lsu_spr_xucr0_dcdis => xu_lsu_spr_xucr0_dcdis, + spr_xucr0_clkg_ctl_b0 => spr_xucr0_clkg_ctl_b0, + + ldq_rel_data_val_early => ldq_rel_data_val_early, + ldq_rel_op_size => ldq_rel_op_size, + ldq_rel_addr => ldq_rel_addr, + ldq_rel_data_val => ldq_rel_data_val, + ldq_rel_rot_sel => ldq_rel_rot_sel, + ldq_rel_axu_val => ldq_rel_axu_val, + ldq_rel_ci => ldq_rel_ci, + ldq_rel_thrd_id => ldq_rel_thrd_id, + ldq_rel_le_mode => ldq_rel_le_mode, + ldq_rel_algebraic => ldq_rel_algebraic, + ldq_rel_256_data => ldq_rel_256_data, + ldq_rel_dvc1_en => ldq_rel_dvc1_en, + ldq_rel_dvc2_en => ldq_rel_dvc2_en, + ldq_rel_beat_crit_qw => ldq_rel_beat_crit_qw, + ldq_rel_beat_crit_qw_block => ldq_rel_beat_crit_qw_block, + + dcarr_up_way_addr => dcarr_up_way_addr, + + ex4_256st_data => ex4_256st_data, + ex6_ld_par_err => ex6_ld_par_err, + lsu_xu_ex6_datc_par_err => lsu_xu_ex6_datc_par_err, + + ex6_xu_ld_data_b => lsu_xu_rot_ex6_data_b, + rel_xu_ld_data => lsu_xu_rot_rel_data, + xu_fu_ex6_load_data => xu_fu_ex6_load_data, + xu_fu_ex5_load_le => xu_fu_ex5_load_le, + + lsu_xu_ex2_dvc1_st_cmp => lsu_xu_ex2_dvc1_st_cmp, + lsu_xu_ex2_dvc2_st_cmp => lsu_xu_ex2_dvc2_st_cmp, + lsu_xu_ex8_dvc1_ld_cmp => lsu_xu_ex8_dvc1_ld_cmp, + lsu_xu_ex8_dvc2_ld_cmp => lsu_xu_ex8_dvc2_ld_cmp, + lsu_xu_rel_dvc_thrd_id => lsu_xu_rel_dvc_thrd_id, + lsu_xu_rel_dvc1_en => lsu_xu_rel_dvc1_en, + lsu_xu_rel_dvc1_cmp => lsu_xu_rel_dvc1_cmp, + lsu_xu_rel_dvc2_en => lsu_xu_rel_dvc2_en, + lsu_xu_rel_dvc2_cmp => lsu_xu_rel_dvc2_cmp, + + pc_xu_trace_bus_enable => pc_xu_trace_bus_enable, + lsudat_debug_mux_ctrls => lsudat_debug_mux_ctrls, + lsu_xu_data_debug0 => lsu_xu_data_debug0, + lsu_xu_data_debug1 => lsu_xu_data_debug1, + lsu_xu_data_debug2 => lsu_xu_data_debug2, + + vdd => vdd, + gnd => gnd, + vcs => vcs, + nclk => nclk, + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b, + + pc_xu_abist_g6t_bw => pc_xu_abist_g6t_bw, + pc_xu_abist_di_g6t_2r => pc_xu_abist_di_g6t_2r, + pc_xu_abist_wl512_comp_ena => pc_xu_abist_wl512_comp_ena, + pc_xu_abist_dcomp_g6t_2r => pc_xu_abist_dcomp_g6t_2r, + pc_xu_abist_g6t_r_wb => pc_xu_abist_g6t_r_wb, + + gptr_scan_in => fxadat_gptr_scan_in, + gptr_scan_out => fxadat_gptr_scan_out, + abst_scan_in(0) => abst_scan_in(1), + abst_scan_in(1) => abst_scan_2, + abst_scan_out(0) => abst_scan_out(1), + abst_scan_out(1) => abst_scan_out(2), + repr_scan_in => fxadat_repr_scan_in, + time_scan_in => fxadat_time_scan_in, + func_scan_in => func_scan_in(31 to 34), + repr_scan_out => fxadat_repr_scan_out, + time_scan_out => fxadat_time_scan_out, + func_scan_out => func_scan_out(31 to 34) +); + + +ctlspr_time_scan_in <= fxadat_time_scan_out; +ctlspr_repr_scan_in <= fxadat_repr_scan_out; +ctlspr_gptr_scan_in <= fxadat_gptr_scan_out; +fxadat_time_scan_in <= time_scan_in; +fxadat_repr_scan_in <= repr_scan_in; +fxadat_gptr_scan_in <= gptr_scan_in; +time_scan_out <= ctlspr_time_scan_out; +repr_scan_out <= ctlspr_repr_scan_out; +gptr_scan_out <= ctlspr_gptr_scan_out; +xu_bx_ex4_256st_data <= ex4_256st_data(128 to 255); + +mark_unused(delay_lclkr_dc(0 to 3)); +mark_unused(mpw1_dc_b(0 to 3)); +mark_unused(sg_2(3)); +mark_unused(fce_2(1)); +mark_unused(func_slp_sl_thold_2); +mark_unused(cfg_sl_thold_2); +mark_unused(cfg_slp_sl_thold_2); +mark_unused(regf_slp_sl_thold_2); +mark_unused(pc_xu_abist_raddr_1(0 to 1)); +mark_unused(pc_xu_abist_waddr_1(0 to 1)); +mark_unused(pc_xu_abist_raddr_0(0)); +mark_unused(pc_xu_abist_waddr_0(0 to 1)); + + +end xuq; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_add.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_add.vhdl new file mode 100644 index 0000000..c965edb --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_add.vhdl @@ -0,0 +1,267 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + +entity xuq_add is +generic( expand_type : integer := 2 ); +port( + x_b :in std_ulogic_vector(0 to 63) ; + y_b :in std_ulogic_vector(0 to 63) ; + ci :in std_ulogic_vector(8 to 8) ; + + sum :out std_ulogic_vector(0 to 63); + cout_32 :out std_ulogic ; + cout_0 :out std_ulogic +); + + + +end xuq_add; + +architecture xuq_add of xuq_add is + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal g01, g01_b :std_ulogic_vector(0 to 63); + signal t01, t01_b :std_ulogic_vector(0 to 63); + signal sum_0, sum_1 :std_ulogic_vector(0 to 63); + signal g08 :std_ulogic_vector(0 to 7); + signal t08 :std_ulogic_vector(0 to 7); + signal c64_b :std_ulogic_vector(0 to 7); + signal cout_32x , cout_32y_b :std_ulogic; + signal ci_cp1_lv1_b , ci_cp1_lv2 , ci_cp1_lv3_b , ci_cp1_lv4 :std_ulogic; + signal ci_cp2_lv2 , ci_cp2_lv3_b :std_ulogic; + + + + + + + + + + + + +begin + + + +u_ci_11: ci_cp1_lv1_b <= not ci(8) ; +u_ci_12: ci_cp1_lv2 <= not ci_cp1_lv1_b ; +u_ci_13: ci_cp1_lv3_b <= not ci_cp1_lv2 ; +u_ci_14: ci_cp1_lv4 <= not ci_cp1_lv3_b ; + +u_ci_22: ci_cp2_lv2 <= not ci_cp1_lv1_b ; +u_ci_23: ci_cp2_lv3_b <= not ci_cp2_lv2 ; + + + + u_g01: g01(0 to 63) <= not( x_b(0 to 63) or y_b(0 to 63) ); + u_t01: t01(0 to 63) <= not( x_b(0 to 63) and y_b(0 to 63) ); + u_g01b: g01_b(0 to 63) <= not g01(0 to 63); + u_t01b: t01_b(0 to 63) <= not t01(0 to 63); + + + + loc_0: entity work.xuq_add_loc(xuq_add_loc) port map( + g01_b(0 to 7) => g01_b(0 to 7) , + t01_b(0 to 7) => t01_b(0 to 7) , + sum_0(0 to 7) => sum_0(0 to 7) , + sum_1(0 to 7) => sum_1(0 to 7) ); + + loc_1: entity work.xuq_add_loc(xuq_add_loc) port map( + g01_b(0 to 7) => g01_b(8 to 15) , + t01_b(0 to 7) => t01_b(8 to 15) , + sum_0(0 to 7) => sum_0(8 to 15) , + sum_1(0 to 7) => sum_1(8 to 15) ); + + loc_2: entity work.xuq_add_loc(xuq_add_loc) port map( + g01_b(0 to 7) => g01_b(16 to 23) , + t01_b(0 to 7) => t01_b(16 to 23) , + sum_0(0 to 7) => sum_0(16 to 23) , + sum_1(0 to 7) => sum_1(16 to 23) ); + + loc_3: entity work.xuq_add_loc(xuq_add_loc) port map( + g01_b(0 to 7) => g01_b(24 to 31) , + t01_b(0 to 7) => t01_b(24 to 31) , + sum_0(0 to 7) => sum_0(24 to 31) , + sum_1(0 to 7) => sum_1(24 to 31) ); + + loc_4: entity work.xuq_add_loc(xuq_add_loc) port map( + g01_b(0 to 7) => g01_b(32 to 39) , + t01_b(0 to 7) => t01_b(32 to 39) , + sum_0(0 to 7) => sum_0(32 to 39) , + sum_1(0 to 7) => sum_1(32 to 39) ); + + loc_5: entity work.xuq_add_loc(xuq_add_loc) port map( + g01_b(0 to 7) => g01_b(40 to 47) , + t01_b(0 to 7) => t01_b(40 to 47) , + sum_0(0 to 7) => sum_0(40 to 47) , + sum_1(0 to 7) => sum_1(40 to 47) ); + + loc_6: entity work.xuq_add_loc(xuq_add_loc) port map( + g01_b(0 to 7) => g01_b(48 to 55) , + t01_b(0 to 7) => t01_b(48 to 55) , + sum_0(0 to 7) => sum_0(48 to 55) , + sum_1(0 to 7) => sum_1(48 to 55) ); + + loc_7: entity work.xuq_add_loc(xuq_add_loc) port map( + g01_b(0 to 7) => g01_b(56 to 63) , + t01_b(0 to 7) => t01_b(56 to 63) , + sum_0(0 to 7) => sum_0(56 to 63) , + sum_1(0 to 7) => sum_1(56 to 63) ); + + + + gclc_0: entity work.xuq_add_glbloc(xuq_add_glbloc) port map( + g01(0 to 7) => g01(0 to 7) , + t01(0 to 7) => t01(0 to 7) , + g08 => g08(0) , + t08 => t08(0) ); + + gclc_1: entity work.xuq_add_glbloc(xuq_add_glbloc) port map( + g01(0 to 7) => g01(8 to 15) , + t01(0 to 7) => t01(8 to 15) , + g08 => g08(1) , + t08 => t08(1) ); + + gclc_2: entity work.xuq_add_glbloc(xuq_add_glbloc) port map( + g01(0 to 7) => g01(16 to 23) , + t01(0 to 7) => t01(16 to 23) , + g08 => g08(2) , + t08 => t08(2) ); + + gclc_3: entity work.xuq_add_glbloc(xuq_add_glbloc) port map( + g01(0 to 7) => g01(24 to 31) , + t01(0 to 7) => t01(24 to 31) , + g08 => g08(3) , + t08 => t08(3) ); + + gclc_4: entity work.xuq_add_glbloc(xuq_add_glbloc) port map( + g01(0 to 7) => g01(32 to 39) , + t01(0 to 7) => t01(32 to 39) , + g08 => g08(4) , + t08 => t08(4) ); + + gclc_5: entity work.xuq_add_glbloc(xuq_add_glbloc) port map( + g01(0 to 7) => g01(40 to 47) , + t01(0 to 7) => t01(40 to 47) , + g08 => g08(5) , + t08 => t08(5) ); + + gclc_6: entity work.xuq_add_glbloc(xuq_add_glbloc) port map( + g01(0 to 7) => g01(48 to 55) , + t01(0 to 7) => t01(48 to 55) , + g08 => g08(6) , + t08 => t08(6) ); + + gclc_7: entity work.xuq_add_glbloc(xuq_add_glbloc) port map( + g01(0 to 7) => g01(56 to 63) , + t01(0 to 7) => t01(56 to 63) , + g08 => g08(7) , + t08 => t08(7) ); + + + + gc: entity work.xuq_add_glbglbci(xuq_add_glbglbci) port map( + g08(0 to 7) => g08(0 to 7) , + t08(0 to 7) => t08(0 to 7) , + ci => ci_cp1_lv4 , + c64_b(0 to 7) => c64_b(0 to 7) ); + + u_c32x: cout_32x <= not c64_b(4) ; + u_c32y: cout_32y_b <= not cout_32x ; + u_c32: cout_32 <= not cout_32y_b ; + + u_c64: cout_0 <= not c64_b(0) ; + + + fm_0: entity work.xuq_add_csmux(xuq_add_csmux) port map( + ci_b => c64_b(1) , + sum_0(0 to 7) => sum_0(0 to 7) , + sum_1(0 to 7) => sum_1(0 to 7) , + sum (0 to 7) => sum (0 to 7) ); + + fm_1: entity work.xuq_add_csmux(xuq_add_csmux) port map( + ci_b => c64_b(2) , + sum_0(0 to 7) => sum_0(8 to 15) , + sum_1(0 to 7) => sum_1(8 to 15) , + sum (0 to 7) => sum (8 to 15) ); + + fm_2: entity work.xuq_add_csmux(xuq_add_csmux) port map( + ci_b => c64_b(3) , + sum_0(0 to 7) => sum_0(16 to 23) , + sum_1(0 to 7) => sum_1(16 to 23) , + sum (0 to 7) => sum (16 to 23) ); + + fm_3: entity work.xuq_add_csmux(xuq_add_csmux) port map( + ci_b => c64_b(4) , + sum_0(0 to 7) => sum_0(24 to 31) , + sum_1(0 to 7) => sum_1(24 to 31) , + sum (0 to 7) => sum (24 to 31) ); + + fm_4: entity work.xuq_add_csmux(xuq_add_csmux) port map( + ci_b => c64_b(5) , + sum_0(0 to 7) => sum_0(32 to 39) , + sum_1(0 to 7) => sum_1(32 to 39) , + sum (0 to 7) => sum (32 to 39) ); + + fm_5: entity work.xuq_add_csmux(xuq_add_csmux) port map( + ci_b => c64_b(6) , + sum_0(0 to 7) => sum_0(40 to 47) , + sum_1(0 to 7) => sum_1(40 to 47) , + sum (0 to 7) => sum (40 to 47) ); + + fm_6: entity work.xuq_add_csmux(xuq_add_csmux) port map( + ci_b => c64_b(7) , + sum_0(0 to 7) => sum_0(48 to 55) , + sum_1(0 to 7) => sum_1(48 to 55) , + sum (0 to 7) => sum (48 to 55) ); + + fm_7: entity work.xuq_add_csmux(xuq_add_csmux) port map( + ci_b => ci_cp2_lv3_b , + sum_0(0 to 7) => sum_0(56 to 63) , + sum_1(0 to 7) => sum_1(56 to 63) , + sum (0 to 7) => sum (56 to 63) ); + +end; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_add_csmux.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_add_csmux.vhdl new file mode 100644 index 0000000..935c932 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_add_csmux.vhdl @@ -0,0 +1,98 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; use ieee.std_logic_1164.all ; +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + +entity xuq_add_csmux is port( + sum_0 :in std_ulogic_vector(0 to 7) ; + sum_1 :in std_ulogic_vector(0 to 7) ; + ci_b :in std_ulogic ; + sum :out std_ulogic_vector(0 to 7) + ); +END xuq_add_csmux; + + +ARCHITECTURE xuq_add_csmux OF xuq_add_csmux IS + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal sum0_b, sum1_b :std_ulogic_vector(0 to 7); + signal int_ci, int_ci_t, int_ci_b :std_ulogic; + + + + + + + + +BEGIN + + u_ci: int_ci <= not ci_b; + u_cit: int_ci_t <= not ci_b; + u_cib: int_ci_b <= not int_ci_t; + + u_sum0_0: sum0_b(0) <= not( sum_0(0) and int_ci_b ); + u_sum0_1: sum0_b(1) <= not( sum_0(1) and int_ci_b ); + u_sum0_2: sum0_b(2) <= not( sum_0(2) and int_ci_b ); + u_sum0_3: sum0_b(3) <= not( sum_0(3) and int_ci_b ); + u_sum0_4: sum0_b(4) <= not( sum_0(4) and int_ci_b ); + u_sum0_5: sum0_b(5) <= not( sum_0(5) and int_ci_b ); + u_sum0_6: sum0_b(6) <= not( sum_0(6) and int_ci_b ); + u_sum0_7: sum0_b(7) <= not( sum_0(7) and int_ci_b ); + + u_sum1_0: sum1_b(0) <= not( sum_1(0) and int_ci ); + u_sum1_1: sum1_b(1) <= not( sum_1(1) and int_ci ); + u_sum1_2: sum1_b(2) <= not( sum_1(2) and int_ci ); + u_sum1_3: sum1_b(3) <= not( sum_1(3) and int_ci ); + u_sum1_4: sum1_b(4) <= not( sum_1(4) and int_ci ); + u_sum1_5: sum1_b(5) <= not( sum_1(5) and int_ci ); + u_sum1_6: sum1_b(6) <= not( sum_1(6) and int_ci ); + u_sum1_7: sum1_b(7) <= not( sum_1(7) and int_ci ); + + u_sum_0: sum(0) <= not( sum0_b(0) and sum1_b(0) ); + u_sum_1: sum(1) <= not( sum0_b(1) and sum1_b(1) ); + u_sum_2: sum(2) <= not( sum0_b(2) and sum1_b(2) ); + u_sum_3: sum(3) <= not( sum0_b(3) and sum1_b(3) ); + u_sum_4: sum(4) <= not( sum0_b(4) and sum1_b(4) ); + u_sum_5: sum(5) <= not( sum0_b(5) and sum1_b(5) ); + u_sum_6: sum(6) <= not( sum0_b(6) and sum1_b(6) ); + u_sum_7: sum(7) <= not( sum0_b(7) and sum1_b(7) ); + + +END; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_add_glbglbci.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_add_glbglbci.vhdl new file mode 100644 index 0000000..f2d28f5 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_add_glbglbci.vhdl @@ -0,0 +1,227 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; use ieee.std_logic_1164.all ; +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + +entity xuq_add_glbglbci is port( + g08 :in std_ulogic_vector(0 to 7) ; + t08 :in std_ulogic_vector(0 to 7) ; + ci :in std_ulogic ; + c64_b :out std_ulogic_vector(0 to 7) + ); +END xuq_add_glbglbci; + + +ARCHITECTURE xuq_add_glbglbci OF xuq_add_glbglbci IS + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal b0_g16_b :std_ulogic_vector(0 to 3); + signal b0_t16_b :std_ulogic_vector(0 to 2); + signal b0_g32 :std_ulogic_vector(0 to 1); + signal b0_t32 :std_ulogic_vector(0 to 0); + signal b1_g16_b :std_ulogic_vector(0 to 3); + signal b1_t16_b :std_ulogic_vector(0 to 2); + signal b1_g32 :std_ulogic_vector(0 to 1); + signal b1_t32 :std_ulogic_vector(0 to 0); + signal b2_g16_b :std_ulogic_vector(0 to 3); + signal b2_t16_b :std_ulogic_vector(0 to 2); + signal b2_g32 :std_ulogic_vector(0 to 1); + signal b2_t32 :std_ulogic_vector(0 to 0); + signal b3_g16_b :std_ulogic_vector(0 to 3); + signal b3_t16_b :std_ulogic_vector(0 to 2); + signal b3_g32 :std_ulogic_vector(0 to 1); + signal b3_t32 :std_ulogic_vector(0 to 0); + signal b4_g16_b :std_ulogic_vector(0 to 3); + signal b4_t16_b :std_ulogic_vector(0 to 2); + signal b4_g32 :std_ulogic_vector(0 to 1); + signal b4_t32 :std_ulogic_vector(0 to 0); + signal b5_g16_b :std_ulogic_vector(0 to 2); + signal b5_t16_b :std_ulogic_vector(0 to 1); + signal b5_g32 :std_ulogic_vector(0 to 1); + signal b5_t32 :std_ulogic_vector(0 to 0); + signal b6_g16_b :std_ulogic_vector(0 to 1); + signal b6_t16_b :std_ulogic_vector(0 to 0); + signal b6_g32 :std_ulogic_vector(0 to 0); + signal b7_g16_b :std_ulogic_vector(0 to 0); + signal b7_g32 :std_ulogic_vector(0 to 0); + signal b0_g56_b, b0_c64 :std_ulogic ; + signal g08_b, t08_b :std_ulogic_vector(0 to 0) ; + + + + + + + + + + + + + +BEGIN + + + u0_g16_0: b0_g16_b(0) <= not( g08(1) or ( t08(1) and g08(2) ) ); + u0_g16_1: b0_g16_b(1) <= not( g08(3) or ( t08(3) and g08(4) ) ); + u0_g16_2: b0_g16_b(2) <= not( g08(5) or ( t08(5) and g08(6) ) ); + u0_g16_3: b0_g16_b(3) <= not( g08(7) or ( t08(7) and ci ) ); + + u0_t16_0: b0_t16_b(0) <= not( t08(1) and t08(2) ); + u0_t16_1: b0_t16_b(1) <= not( t08(3) and t08(4) ); + u0_t16_2: b0_t16_b(2) <= not( t08(5) and t08(6) ); + + u0_g32_0: b0_g32(0) <= not( b0_g16_b(0) and ( b0_t16_b(0) or b0_g16_b(1) ) ) ; + u0_g32_1: b0_g32(1) <= not( b0_g16_b(2) and ( b0_t16_b(2) or b0_g16_b(3) ) ) ; + u0_t32_0: b0_t32(0) <= not( b0_t16_b(0) or b0_t16_b(1) ) ; + + + u0_g08b: g08_b(0) <= not g08(0) ; + u0_t08b: t08_b(0) <= not t08(0) ; + + u0_g56_0: b0_g56_b <= not( b0_g32(0) or (b0_t32(0) and b0_g32(1) ) ); + + u0_c64_0: b0_c64 <= not( g08_b(0) and ( t08_b(0) or b0_g56_b ) ) ; + + u0_g64_0: c64_b(0) <= not( b0_c64 ); + + + u1_g16_0: b1_g16_b(0) <= not( g08(1) or ( t08(1) and g08(2) ) ); + u1_g16_1: b1_g16_b(1) <= not( g08(3) or ( t08(3) and g08(4) ) ); + u1_g16_2: b1_g16_b(2) <= not( g08(5) or ( t08(5) and g08(6) ) ); + u1_g16_3: b1_g16_b(3) <= not( g08(7) or (t08(7) and ci) ); + + u1_t16_0: b1_t16_b(0) <= not( t08(1) and t08(2) ); + u1_t16_1: b1_t16_b(1) <= not( t08(3) and t08(4) ); + u1_t16_2: b1_t16_b(2) <= not( t08(5) and t08(6) ); + + u1_g32_0: b1_g32(0) <= not( b1_g16_b(0) and ( b1_t16_b(0) or b1_g16_b(1) ) ) ; + u1_g32_1: b1_g32(1) <= not( b1_g16_b(2) and ( b1_t16_b(2) or b1_g16_b(3) ) ) ; + u1_t32_0: b1_t32(0) <= not( b1_t16_b(0) or b1_t16_b(1) ) ; + + u1_g64_0: c64_b(1) <= not( b1_g32(0) or (b1_t32(0) and b1_g32(1) ) ); + + + + u2_g16_0: b2_g16_b(0) <= not( g08(2) or ( t08(2) and g08(3) ) ); + u2_g16_1: b2_g16_b(1) <= not( g08(4) or ( t08(4) and g08(5) ) ); + u2_g16_2: b2_g16_b(2) <= not( g08(6) ); + u2_g16_3: b2_g16_b(3) <= not( g08(7) or (t08(7) and ci) ); + + u2_t16_0: b2_t16_b(0) <= not( t08(2) and t08(3) ); + u2_t16_1: b2_t16_b(1) <= not( t08(4) and t08(5) ); + u2_t16_2: b2_t16_b(2) <= not( t08(6) ); + + u2_g32_0: b2_g32(0) <= not( b2_g16_b(0) and ( b2_t16_b(0) or b2_g16_b(1) ) ) ; + u2_g32_1: b2_g32(1) <= not( b2_g16_b(2) and ( b2_t16_b(2) or b2_g16_b(3) ) ) ; + u2_t32_0: b2_t32(0) <= not( b2_t16_b(0) or b2_t16_b(1) ) ; + + u2_g64_0: c64_b(2) <= not( b2_g32(0) or (b2_t32(0) and b2_g32(1) ) ); + + + + u3_g16_0: b3_g16_b(0) <= not( g08(3) or ( t08(3) and g08(4) ) ); + u3_g16_1: b3_g16_b(1) <= not( g08(5) ); + u3_g16_2: b3_g16_b(2) <= not( g08(6) ); + u3_g16_3: b3_g16_b(3) <= not( g08(7) or (t08(7) and ci) ); + + u3_t16_0: b3_t16_b(0) <= not( t08(3) and t08(4) ); + u3_t16_1: b3_t16_b(1) <= not( t08(5) ); + u3_t16_2: b3_t16_b(2) <= not( t08(6) ); + + u3_g32_0: b3_g32(0) <= not( b3_g16_b(0) and ( b3_t16_b(0) or b3_g16_b(1) ) ) ; + u3_g32_1: b3_g32(1) <= not( b3_g16_b(2) and ( b3_t16_b(2) or b3_g16_b(3) ) ) ; + u3_t32_0: b3_t32(0) <= not( b3_t16_b(0) or b3_t16_b(1) ) ; + + u3_g64_0: c64_b(3) <= not( b3_g32(0) or (b3_t32(0) and b3_g32(1) ) ); + + + + u4_g16_0: b4_g16_b(0) <= not( g08(4) ); + u4_g16_1: b4_g16_b(1) <= not( g08(5) ); + u4_g16_2: b4_g16_b(2) <= not( g08(6) ); + u4_g16_3: b4_g16_b(3) <= not( g08(7) or (t08(7) and ci) ); + + u4_t16_0: b4_t16_b(0) <= not( t08(4) ); + u4_t16_1: b4_t16_b(1) <= not( t08(5) ); + u4_t16_2: b4_t16_b(2) <= not( t08(6) ); + + u4_g32_0: b4_g32(0) <= not( b4_g16_b(0) and ( b4_t16_b(0) or b4_g16_b(1) ) ) ; + u4_g32_1: b4_g32(1) <= not( b4_g16_b(2) and ( b4_t16_b(2) or b4_g16_b(3) ) ) ; + u4_t32_0: b4_t32(0) <= not( b4_t16_b(0) or b4_t16_b(1) ) ; + + u4_g64_0: c64_b(4) <= not( b4_g32(0) or (b4_t32(0) and b4_g32(1) ) ); + + + + u5_g16_0: b5_g16_b(0) <= not( g08(5) ); + u5_g16_1: b5_g16_b(1) <= not( g08(6) ); + u5_g16_2: b5_g16_b(2) <= not( g08(7) or (t08(7) and ci) ); + + u5_t16_0: b5_t16_b(0) <= not( t08(5) ); + u5_t16_1: b5_t16_b(1) <= not( t08(6) ); + + u5_g32_0: b5_g32(0) <= not( b5_g16_b(0) and ( b5_t16_b(0) or b5_g16_b(1) ) ) ; + u5_g32_1: b5_g32(1) <= not( b5_g16_b(2) ) ; + u5_t32_0: b5_t32(0) <= not( b5_t16_b(0) or b5_t16_b(1) ) ; + + u5_g64_0: c64_b(5) <= not( b5_g32(0) or (b5_t32(0) and b5_g32(1) ) ); + + + + u6_g16_0: b6_g16_b(0) <= not( g08(6) ); + u6_g16_1: b6_g16_b(1) <= not( g08(7) or (t08(7) and ci) ); + + u6_t16_0: b6_t16_b(0) <= not( t08(6) ); + + + u6_g32_0: b6_g32(0) <= not( b6_g16_b(0) and ( b6_t16_b(0) or b6_g16_b(1) ) ) ; + + + u6_g64_0: c64_b(6) <= not( b6_g32(0) ) ; + + + u7_g16_0: b7_g16_b(0) <= not( g08(7) or (t08(7) and ci) ); + + u7_g32_0: b7_g32(0) <= not( b7_g16_b(0) ); + + u7_g64_0: c64_b(7) <= not( b7_g32(0) ) ; + + +END; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_add_glbloc.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_add_glbloc.vhdl new file mode 100644 index 0000000..a145c9f --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_add_glbloc.vhdl @@ -0,0 +1,96 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; use ieee.std_logic_1164.all ; +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + +entity xuq_add_glbloc is port( + g01 :in std_ulogic_vector(0 to 7) ; + t01 :in std_ulogic_vector(0 to 7) ; + g08 :out std_ulogic ; + t08 :out std_ulogic + ); +END xuq_add_glbloc; + + +ARCHITECTURE xuq_add_glbloc OF xuq_add_glbloc IS + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal g02_b, t02_b :std_ulogic_vector(0 to 3); + signal g04, t04 :std_ulogic_vector(0 to 1); + signal g08_b, t08_b :std_ulogic; + + + + + + + +BEGIN + + u_g02_0: g02_b(0) <= not ( g01(0) or ( t01(0) and g01(1) ) ); + u_g02_1: g02_b(1) <= not ( g01(2) or ( t01(2) and g01(3) ) ); + u_g02_2: g02_b(2) <= not ( g01(4) or ( t01(4) and g01(5) ) ); + u_g02_3: g02_b(3) <= not ( g01(6) or ( t01(6) and g01(7) ) ); + + u_t02_0: t02_b(0) <= not ( t01(0) and t01(1) ) ; + u_t02_1: t02_b(1) <= not ( t01(2) and t01(3) ) ; + u_t02_2: t02_b(2) <= not ( t01(4) and t01(5) ) ; + u_t02_3: t02_b(3) <= not ( t01(6) and t01(7) ) ; + + + + u_g04_0: g04(0) <= not ( g02_b(0) and ( t02_b(0) or g02_b(1) ) ) ; + u_g04_1: g04(1) <= not ( g02_b(2) and ( t02_b(2) or g02_b(3) ) ) ; + + u_t04_0: t04(0) <= not ( t02_b(0) or t02_b(1) ) ; + u_t04_1: t04(1) <= not ( t02_b(2) or t02_b(3) ) ; + + + + u_g08_y: g08_b <= not ( g04(0) or ( t04(0) and g04(1) ) ) ; + + u_t08_y: t08_b <= not ( ( t04(0) and t04(1)) ) ; + + + + u_g08_x: g08 <= not ( g08_b ) ; + + u_t08_x: t08 <= not ( t08_b ) ; + +END; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_add_loc.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_add_loc.vhdl new file mode 100644 index 0000000..58dbcec --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_add_loc.vhdl @@ -0,0 +1,188 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; use ieee.std_logic_1164.all ; +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + +entity xuq_add_loc is port( + g01_b :in std_ulogic_vector(0 to 7) ; + t01_b :in std_ulogic_vector(0 to 7) ; + sum_0 :out std_ulogic_vector(0 to 7) ; + sum_1 :out std_ulogic_vector(0 to 7) + ); +END xuq_add_loc; + + +ARCHITECTURE xuq_add_loc OF xuq_add_loc IS + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + + signal g01_t :std_ulogic_vector(0 to 7); + signal g01_not :std_ulogic_vector(0 to 7); + signal z01_b :std_ulogic_vector(0 to 7); + signal p01 :std_ulogic_vector(0 to 7); + signal p01_b :std_ulogic_vector(0 to 7); + signal g02, t02, g04_b, t04_b, g08, t08 , g08_b , t08_b :std_ulogic_vector(0 to 7); + + + + + + + + + + + + + + + +BEGIN + + + u_g01t : g01_t (0 to 7) <= not g01_b(0 to 7) ; + u_g01not: g01_not(0 to 7) <= not g01_t(0 to 7) ; + u_z01b: z01_b (0 to 7) <= not t01_b(0 to 7) ; + u_p01b: p01_b (0 to 7) <= not( g01_not(0 to 7) and z01_b(0 to 7) ); + u_p01: p01 (0 to 7) <= not( p01_b(0 to 7) ); + + + + u_g08i_0: g08_b(0) <= not g08(0) ; + u_g08i_1: g08_b(1) <= not g08(1) ; + u_g08i_2: g08_b(2) <= not g08(2) ; + u_g08i_3: g08_b(3) <= not g08(3) ; + u_g08i_4: g08_b(4) <= not g08(4) ; + u_g08i_5: g08_b(5) <= not g08(5) ; + u_g08i_6: g08_b(6) <= not g08(6) ; + u_g08i_7: g08_b(7) <= not g08(7) ; + + u_t08i_0: t08_b(0) <= not t08(0) ; + u_t08i_1: t08_b(1) <= not t08(1) ; + u_t08i_2: t08_b(2) <= not t08(2) ; + u_t08i_3: t08_b(3) <= not t08(3) ; + u_t08i_4: t08_b(4) <= not t08(4) ; + u_t08i_5: t08_b(5) <= not t08(5) ; + u_t08i_6: t08_b(6) <= not t08(6) ; + u_t08i_7: t08_b(7) <= not t08(7) ; + + + u_sum_0_0: sum_0(0) <= not( ( p01(0) and g08(1) ) or ( p01_b(0) and g08_b(1) ) ); + u_sum_0_1: sum_0(1) <= not( ( p01(1) and g08(2) ) or ( p01_b(1) and g08_b(2) ) ); + u_sum_0_2: sum_0(2) <= not( ( p01(2) and g08(3) ) or ( p01_b(2) and g08_b(3) ) ); + u_sum_0_3: sum_0(3) <= not( ( p01(3) and g08(4) ) or ( p01_b(3) and g08_b(4) ) ); + u_sum_0_4: sum_0(4) <= not( ( p01(4) and g08(5) ) or ( p01_b(4) and g08_b(5) ) ); + u_sum_0_5: sum_0(5) <= not( ( p01(5) and g08(6) ) or ( p01_b(5) and g08_b(6) ) ); + u_sum_0_6: sum_0(6) <= not( ( p01(6) and g08(7) ) or ( p01_b(6) and g08_b(7) ) ); + u_sum_0_7: sum_0(7) <= not( p01_b(7) ); + + u_sum_1_0: sum_1(0) <= not( ( p01(0) and t08(1) ) or ( p01_b(0) and t08_b(1) ) ); + u_sum_1_1: sum_1(1) <= not( ( p01(1) and t08(2) ) or ( p01_b(1) and t08_b(2) ) ); + u_sum_1_2: sum_1(2) <= not( ( p01(2) and t08(3) ) or ( p01_b(2) and t08_b(3) ) ); + u_sum_1_3: sum_1(3) <= not( ( p01(3) and t08(4) ) or ( p01_b(3) and t08_b(4) ) ); + u_sum_1_4: sum_1(4) <= not( ( p01(4) and t08(5) ) or ( p01_b(4) and t08_b(5) ) ); + u_sum_1_5: sum_1(5) <= not( ( p01(5) and t08(6) ) or ( p01_b(5) and t08_b(6) ) ); + u_sum_1_6: sum_1(6) <= not( ( p01(6) and t08(7) ) or ( p01_b(6) and t08_b(7) ) ); + u_sum_1_7: sum_1(7) <= not( p01(7) ); + + + + u_g02_0: g02(0) <= not( g01_b(0) and ( t01_b(0) or g01_b(1) ) ) ; + u_g02_1: g02(1) <= not( g01_b(1) and ( t01_b(1) or g01_b(2) ) ) ; + u_g02_2: g02(2) <= not( g01_b(2) and ( t01_b(2) or g01_b(3) ) ) ; + u_g02_3: g02(3) <= not( g01_b(3) and ( t01_b(3) or g01_b(4) ) ) ; + u_g02_4: g02(4) <= not( g01_b(4) and ( t01_b(4) or g01_b(5) ) ) ; + u_g02_5: g02(5) <= not( g01_b(5) and ( t01_b(5) or g01_b(6) ) ) ; + u_g02_6: g02(6) <= not( g01_b(6) and ( t01_b(6) or g01_b(7) ) ) ; + u_g02_7: g02(7) <= not( g01_b(7) ) ; + + u_t02_0: t02(0) <= not( t01_b(0) or t01_b(1) ) ; + u_t02_1: t02(1) <= not( t01_b(1) or t01_b(2) ) ; + u_t02_2: t02(2) <= not( t01_b(2) or t01_b(3) ) ; + u_t02_3: t02(3) <= not( t01_b(3) or t01_b(4) ) ; + u_t02_4: t02(4) <= not( t01_b(4) or t01_b(5) ) ; + u_t02_5: t02(5) <= not( t01_b(5) or t01_b(6) ) ; + u_t02_6: t02(6) <= not( g01_b(6) and ( t01_b(6) or t01_b(7) ) ) ; + u_t02_7: t02(7) <= not( t01_b(7) ) ; + + + + u_g04_0: g04_b(0) <= not( g02(0) or ( t02(0) and g02(2) ) ) ; + u_g04_1: g04_b(1) <= not( g02(1) or ( t02(1) and g02(3) ) ) ; + u_g04_2: g04_b(2) <= not( g02(2) or ( t02(2) and g02(4) ) ) ; + u_g04_3: g04_b(3) <= not( g02(3) or ( t02(3) and g02(5) ) ) ; + u_g04_4: g04_b(4) <= not( g02(4) or ( t02(4) and g02(6) ) ) ; + u_g04_5: g04_b(5) <= not( g02(5) or ( t02(5) and g02(7) ) ) ; + u_g04_6: g04_b(6) <= not( g02(6) ) ; + u_g04_7: g04_b(7) <= not( g02(7) ) ; + + u_t04_0: t04_b(0) <= not( t02(0) and t02(2) ) ; + u_t04_1: t04_b(1) <= not( t02(1) and t02(3) ) ; + u_t04_2: t04_b(2) <= not( t02(2) and t02(4) ) ; + u_t04_3: t04_b(3) <= not( t02(3) and t02(5) ) ; + u_t04_4: t04_b(4) <= not( g02(4) or ( t02(4) and t02(6) ) ) ; + u_t04_5: t04_b(5) <= not( g02(5) or ( t02(5) and t02(7) ) ) ; + u_t04_6: t04_b(6) <= not( t02(6) ) ; + u_t04_7: t04_b(7) <= not( t02(7) ) ; + + + + u_g08_0: g08(0) <= not( g04_b(0) and ( t04_b(0) or g04_b(4) ) ) ; + u_g08_1: g08(1) <= not( g04_b(1) and ( t04_b(1) or g04_b(5) ) ) ; + u_g08_2: g08(2) <= not( g04_b(2) and ( t04_b(2) or g04_b(6) ) ) ; + u_g08_3: g08(3) <= not( g04_b(3) and ( t04_b(3) or g04_b(7) ) ) ; + u_g08_4: g08(4) <= not( g04_b(4) ) ; + u_g08_5: g08(5) <= not( g04_b(5) ) ; + u_g08_6: g08(6) <= not( g04_b(6) ) ; + u_g08_7: g08(7) <= not( g04_b(7) ) ; + + u_t08_0: t08(0) <= not( g04_b(0) and ( t04_b(0) or t04_b(4) ) ) ; + u_t08_1: t08(1) <= not( g04_b(1) and ( t04_b(1) or t04_b(5) ) ) ; + u_t08_2: t08(2) <= not( g04_b(2) and ( t04_b(2) or t04_b(6) ) ) ; + u_t08_3: t08(3) <= not( g04_b(3) and ( t04_b(3) or t04_b(7) ) ) ; + u_t08_4: t08(4) <= not( t04_b(4) ) ; + u_t08_5: t08(5) <= not( t04_b(5) ) ; + u_t08_6: t08(6) <= not( t04_b(6) ) ; + u_t08_7: t08(7) <= not( t04_b(7) ) ; + + + + + +END; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_agen.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_agen.vhdl new file mode 100644 index 0000000..7d3ec0e --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_agen.vhdl @@ -0,0 +1,334 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + +entity xuq_agen is +generic( expand_type : integer := 2 ); +port( + x :in std_ulogic_vector(0 to 63) ; + y :in std_ulogic_vector(0 to 63) ; + snoop_addr :in std_ulogic_vector(0 to 51) ; + snoop_sel :in std_ulogic ; + binv_val :in std_ulogic ; + mode64 :in std_ulogic ; + dir_ig_57_b :in std_ulogic ; + + + sum_non_erat :out std_ulogic_vector(0 to 63) ; + sum :out std_ulogic_vector(0 to 51) ; + sum_arr_dir01 :out std_ulogic_vector(53 to 57) ; + sum_arr_dir23 :out std_ulogic_vector(53 to 57) ; + sum_arr_dir45 :out std_ulogic_vector(53 to 57) ; + sum_arr_dir67 :out std_ulogic_vector(53 to 57) ; + + z :in std_ulogic_vector(53 to 57) ; + way :in std_ulogic_vector(0 to 7) ; + inv1_val_b :in std_ulogic ; + ex1_cache_acc_b :in std_ulogic ; + rel3_val :in std_ulogic ; + ary_write_act_01 :out std_ulogic ; + ary_write_act_23 :out std_ulogic ; + ary_write_act_45 :out std_ulogic ; + ary_write_act_67 :out std_ulogic ; + ary_write_act :out std_ulogic_vector(0 to 3) ; + match_oth :out std_ulogic ; + vdd :inout power_logic; + gnd :inout power_logic + +); + + + + +end xuq_agen; + +architecture xuq_agen of xuq_agen is + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + + + signal sum_int, sum_non_erat_b :std_ulogic_vector(0 to 51); + signal sum_0 :std_ulogic_vector(0 to 51); + signal sum_1 :std_ulogic_vector(0 to 51); + signal g08 :std_ulogic_vector(1 to 7); + signal t08 :std_ulogic_vector(1 to 6); + signal c64_b :std_ulogic_vector(1 to 7); + signal x_b, y_b :std_ulogic_vector(0 to 63); + + + + + + signal addr_sel, addr_nsel, addr_sel_64, addr_nsel_64 :std_ulogic; + + signal sum_arr :std_ulogic_vector(53 to 57); + signal sum_arr_lv1_0_b :std_ulogic_vector(53 to 57); + signal sum_arr_lv1_1_b :std_ulogic_vector(53 to 57); + + + + + + + +begin + + + addr_nsel_64 <= mode64 and not (snoop_sel and not binv_val) ; + addr_nsel <= not (snoop_sel and not binv_val) ; + addr_sel_64 <= (snoop_sel and not binv_val) ; + addr_sel <= (snoop_sel and not binv_val) ; + + + + u_xi: x_b(0 to 63) <= not( x(0 to 63) ); + u_yi: y_b(0 to 63) <= not( y(0 to 63) ); + + + loc_0: entity work.xuq_agen_loca(xuq_agen_loca) port map( + addr_sel => addr_sel_64 , + addr_nsel => addr_nsel_64 , + addr(0 to 7) => snoop_addr(0 to 7) , + x_b(0 to 7) => x_b(0 to 7) , + y_b(0 to 7) => y_b(0 to 7) , + sum_0(0 to 7) => sum_0(0 to 7) , + sum_1(0 to 7) => sum_1(0 to 7) ); + + loc_1: entity work.xuq_agen_loca(xuq_agen_loca) port map( + addr_sel => addr_sel_64 , + addr_nsel => addr_nsel_64 , + addr(0 to 7) => snoop_addr(8 to 15) , + x_b(0 to 7) => x_b(8 to 15) , + y_b(0 to 7) => y_b(8 to 15) , + sum_0(0 to 7) => sum_0(8 to 15) , + sum_1(0 to 7) => sum_1(8 to 15) ); + + loc_2: entity work.xuq_agen_loca(xuq_agen_loca) port map( + addr_sel => addr_sel_64 , + addr_nsel => addr_nsel_64 , + addr(0 to 7) => snoop_addr(16 to 23) , + x_b(0 to 7) => x_b(16 to 23) , + y_b(0 to 7) => y_b(16 to 23) , + sum_0(0 to 7) => sum_0(16 to 23) , + sum_1(0 to 7) => sum_1(16 to 23) ); + + loc_3: entity work.xuq_agen_loca(xuq_agen_loca) port map( + addr_sel => addr_sel_64 , + addr_nsel => addr_nsel_64 , + addr(0 to 7) => snoop_addr(24 to 31) , + x_b(0 to 7) => x_b(24 to 31) , + y_b(0 to 7) => y_b(24 to 31) , + sum_0(0 to 7) => sum_0(24 to 31) , + sum_1(0 to 7) => sum_1(24 to 31) ); + + loc_4: entity work.xuq_agen_loca(xuq_agen_loca) port map( + addr_sel => addr_sel , + addr_nsel => addr_nsel , + addr(0 to 7) => snoop_addr(32 to 39) , + x_b(0 to 7) => x_b(32 to 39) , + y_b(0 to 7) => y_b(32 to 39) , + sum_0(0 to 7) => sum_0(32 to 39) , + sum_1(0 to 7) => sum_1(32 to 39) ); + + loc_5: entity work.xuq_agen_loca(xuq_agen_loca) port map( + addr_sel => addr_sel , + addr_nsel => addr_nsel , + addr(0 to 7) => snoop_addr(40 to 47) , + x_b(0 to 7) => x_b(40 to 47) , + y_b(0 to 7) => y_b(40 to 47) , + sum_0(0 to 7) => sum_0(40 to 47) , + sum_1(0 to 7) => sum_1(40 to 47) ); + + loc_6: entity work.xuq_agen_locae(xuq_agen_locae) port map( + addr_sel => addr_sel , + addr_nsel => addr_nsel , + addr(0 to 3) => snoop_addr(48 to 51) , + x_b(0 to 7) => x_b(48 to 55) , + y_b(0 to 7) => y_b(48 to 55) , + sum_0(0 to 3) => sum_0(48 to 51) , + sum_1(0 to 3) => sum_1(48 to 51) ); + + + + + + gclc_1: entity work.xuq_agen_glbloc(xuq_agen_glbloc) port map( + x_b(0 to 7) => x_b(8 to 15) , + y_b(0 to 7) => y_b(8 to 15) , + g08 => g08(1) , + t08 => t08(1) ); + + gclc_2: entity work.xuq_agen_glbloc(xuq_agen_glbloc) port map( + x_b(0 to 7) => x_b(16 to 23) , + y_b(0 to 7) => y_b(16 to 23) , + g08 => g08(2) , + t08 => t08(2) ); + + gclc_3: entity work.xuq_agen_glbloc(xuq_agen_glbloc) port map( + x_b(0 to 7) => x_b(24 to 31) , + y_b(0 to 7) => y_b(24 to 31) , + g08 => g08(3) , + t08 => t08(3) ); + + gclc_4: entity work.xuq_agen_glbloc(xuq_agen_glbloc) port map( + x_b(0 to 7) => x_b(32 to 39) , + y_b(0 to 7) => y_b(32 to 39) , + g08 => g08(4) , + t08 => t08(4) ); + + gclc_5: entity work.xuq_agen_glbloc(xuq_agen_glbloc) port map( + x_b(0 to 7) => x_b(40 to 47) , + y_b(0 to 7) => y_b(40 to 47) , + g08 => g08(5) , + t08 => t08(5) ); + + gclc_6: entity work.xuq_agen_glbloc(xuq_agen_glbloc) port map( + x_b(0 to 7) => x_b(48 to 55) , + y_b(0 to 7) => y_b(48 to 55) , + g08 => g08(6) , + t08 => t08(6) ); + + gclc_7: entity work.xuq_agen_glbloc_lsb(xuq_agen_glbloc_lsb) port map( + x_b(0 to 7) => x_b(56 to 63) , + y_b(0 to 7) => y_b(56 to 63) , + g08 => g08(7) ); + + + + gc: entity work.xuq_agen_glbglb(xuq_agen_glbglb) port map( + g08(1 to 7) => g08(1 to 7) , + t08(1 to 6) => t08(1 to 6) , + c64_b(1 to 7) => c64_b(1 to 7) ); + + + + + fm_0: entity work.xuq_agen_csmux(xuq_agen_csmux) port map( + ci_b => c64_b(1) , + sum_0(0 to 7) => sum_0 (0 to 7) , + sum_1(0 to 7) => sum_1 (0 to 7) , + sum (0 to 7) => sum_int (0 to 7) ); + + fm_1: entity work.xuq_agen_csmux(xuq_agen_csmux) port map( + ci_b => c64_b(2) , + sum_0(0 to 7) => sum_0 (8 to 15) , + sum_1(0 to 7) => sum_1 (8 to 15) , + sum (0 to 7) => sum_int (8 to 15) ); + + fm_2: entity work.xuq_agen_csmux(xuq_agen_csmux) port map( + ci_b => c64_b(3) , + sum_0(0 to 7) => sum_0 (16 to 23) , + sum_1(0 to 7) => sum_1 (16 to 23) , + sum (0 to 7) => sum_int (16 to 23) ); + + fm_3: entity work.xuq_agen_csmux(xuq_agen_csmux) port map( + ci_b => c64_b(4) , + sum_0(0 to 7) => sum_0 (24 to 31) , + sum_1(0 to 7) => sum_1 (24 to 31) , + sum (0 to 7) => sum_int (24 to 31) ); + + fm_4: entity work.xuq_agen_csmux(xuq_agen_csmux) port map( + ci_b => c64_b(5) , + sum_0(0 to 7) => sum_0 (32 to 39) , + sum_1(0 to 7) => sum_1 (32 to 39) , + sum (0 to 7) => sum_int (32 to 39) ); + + fm_5: entity work.xuq_agen_csmux(xuq_agen_csmux) port map( + ci_b => c64_b(6) , + sum_0(0 to 7) => sum_0 (40 to 47) , + sum_1(0 to 7) => sum_1 (40 to 47) , + sum (0 to 7) => sum_int (40 to 47) ); + + + fm_6: entity work.xuq_agen_csmuxe(xuq_agen_csmuxe) port map( + ci_b => c64_b(7) , + sum_0(0 to 3) => sum_0 (48 to 51) , + sum_1(0 to 3) => sum_1 (48 to 51) , + sum (0 to 3) => sum_int (48 to 51) ); + + kog: entity work.xuq_agen_lo(xuq_agen_lo) port map( + dir_ig_57_b => dir_ig_57_b , + x_b (0 to 11) => x_b (52 to 63) , + y_b (0 to 11) => y_b (52 to 63) , + sum (0 to 11) => sum_non_erat(52 to 63) , + sum_arr(1 to 5) => sum_arr (53 to 57) ); + + + u_non_b: sum_non_erat_b(0 to 51) <= not( sum_int(0 to 51) ); + u_non: sum_non_erat (0 to 51) <= not( sum_non_erat_b(0 to 51) ); + + sum(0 to 51) <= sum_int(0 to 51) ; + + + + + u_sum_lv1_1: sum_arr_lv1_1_b(53 to 57) <= not( sum_arr (53 to 57) ); + u_sum_lv2_0: sum_arr_dir01(53 to 57) <= not( sum_arr_lv1_1_b(53 to 57) ); + u_sum_lv2_1: sum_arr_dir45(53 to 57) <= not( sum_arr_lv1_1_b(53 to 57) ); + + + u_sum_lv1_0: sum_arr_lv1_0_b(53 to 57) <= not( sum_arr (53 to 57) ); + u_sum_lv2_2: sum_arr_dir23(53 to 57) <= not( sum_arr_lv1_0_b(53 to 57) ); + u_sum_lv2_3: sum_arr_dir67(53 to 57) <= not( sum_arr_lv1_0_b(53 to 57) ); + + + + agcmp: entity work.xuq_agen_cmp(xuq_agen_cmp) port map( + x_b(53 to 63) => x_b(53 to 63) , + y_b(53 to 63) => y_b(53 to 63) , + z (53 to 57) => z (53 to 57) , + inv1_val_b => inv1_val_b , + ex1_cache_acc_b => ex1_cache_acc_b , + dir_ig_57_b => dir_ig_57_b , + rel3_val => rel3_val , + way(0 to 7) => way(0 to 7) , + ary_write_act_01 => ary_write_act_01 , + ary_write_act_23 => ary_write_act_23 , + ary_write_act_45 => ary_write_act_45 , + ary_write_act_67 => ary_write_act_67 , + ary_write_act => ary_write_act , + match_oth => match_oth , + vdd => vdd , + gnd => gnd); + + +end; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_agen_cmp.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_agen_cmp.vhdl new file mode 100644 index 0000000..9114846 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_agen_cmp.vhdl @@ -0,0 +1,296 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee,ibm,support,tri, work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; +library clib ; + + + +entity xuq_agen_cmp is port( + x_b :in std_ulogic_vector(53 to 63) ; + y_b :in std_ulogic_vector(53 to 63) ; + z :in std_ulogic_vector(53 to 57) ; + + inv1_val_b :in std_ulogic; + ex1_cache_acc_b :in std_ulogic; + dir_ig_57_b :in std_ulogic; + rel3_val :in std_ulogic; + way :in std_ulogic_vector(0 to 7); + + ary_write_act_01 :out std_ulogic ; + ary_write_act_23 :out std_ulogic ; + ary_write_act_45 :out std_ulogic ; + ary_write_act_67 :out std_ulogic ; + ary_write_act :out std_ulogic_vector(0 to 3); + + match_oth :out std_ulogic ; + vdd :inout power_logic; + gnd :inout power_logic + ); + + +END xuq_agen_cmp; + + +ARCHITECTURE xuq_agen_cmp OF xuq_agen_cmp IS + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal unused_car :std_ulogic; + signal sum :std_ulogic_vector(0 to 4); + signal car :std_ulogic_vector(0 to 3); + + signal x :std_ulogic_vector(0 to 4); + signal y :std_ulogic_vector(0 to 4); + signal z_b :std_ulogic_vector(0 to 4); + + signal g1 :std_ulogic_vector(4 to 10); + signal t1 :std_ulogic_vector(4 to 9); + + + signal g_4_b :std_ulogic; + signal g_4e :std_ulogic; + signal t_4e_b :std_ulogic; + signal t_4e :std_ulogic; + signal g_5t7_0_b :std_ulogic; + signal g_5t7_1_b :std_ulogic; + signal g_5t7_2_b :std_ulogic; + signal g_5t7 :std_ulogic; + signal t_5t7_b :std_ulogic; + signal t_5t7 :std_ulogic; + signal g_8t10_0_b :std_ulogic; + signal g_8t10_1_b :std_ulogic; + signal g_8t10_2_b :std_ulogic; + signal g_8t10 :std_ulogic; + signal g_4t10_0_b :std_ulogic; + signal g_4t10_1_b :std_ulogic; + signal g_4t10_2_b :std_ulogic; + signal g_4t10 :std_ulogic; + + + signal dir_ig_57 :std_ulogic; + signal xorcmp :std_ulogic_vector(0 to 3); + signal ulp_0_b :std_ulogic; + signal ulp_1_b :std_ulogic; + signal ulp :std_ulogic; + signal enable_part :std_ulogic; + signal gp1_a_b :std_ulogic; + signal gp2_a_b :std_ulogic; + signal gp12_a :std_ulogic; + signal gp3 :std_ulogic; + signal match_arr_b :std_ulogic; + signal match :std_ulogic; + + signal rel3_val_01 :std_ulogic; + signal rel3_val_23 :std_ulogic; + signal rel3_val_45 :std_ulogic; + signal rel3_val_67 :std_ulogic; + + signal match_lv0_i0 :std_ulogic; + signal match_lv1_i0_b :std_ulogic; + signal match_lv1_i1_b :std_ulogic; + signal ary_write_act_01_b :std_ulogic; + signal ary_write_act_45_b :std_ulogic; + signal ary_write_act_23_b :std_ulogic; + signal ary_write_act_67_b :std_ulogic; + + signal ary_write_act_cpy :std_ulogic_vector(0 to 3); + +BEGIN + + dir_ig_57 <= not dir_ig_57_b ; + + + u_x1_0: x(0) <= not x_b(53) ; + u_x1_1: x(1) <= not x_b(54) ; + u_x1_2: x(2) <= not x_b(55) ; + u_x1_3: x(3) <= not x_b(56) ; + u_x1_4: x(4) <= not x_b(57) ; + + u_y1_0: y(0) <= not y_b(53) ; + u_y1_1: y(1) <= not y_b(54) ; + u_y1_2: y(2) <= not y_b(55) ; + u_y1_3: y(3) <= not y_b(56) ; + u_y1_4: y(4) <= not y_b(57) ; + + u_z1_0: z_b(0) <= not( z(53) ); + u_z1_1: z_b(1) <= not( z(54) ); + u_z1_2: z_b(2) <= not( z(55) ); + u_z1_3: z_b(3) <= not( z(56) ); + u_z1_4: z_b(4) <= not( z(57) ); + + u_g1_4: g1(4) <= not( x_b(57) or y_b(57) ); + u_g1_5: g1(5) <= not( x_b(58) or y_b(58) ); + u_g1_6: g1(6) <= not( x_b(59) or y_b(59) ); + u_g1_7: g1(7) <= not( x_b(60) or y_b(60) ); + u_g1_8: g1(8) <= not( x_b(61) or y_b(61) ); + u_g1_9: g1(9) <= not( x_b(62) or y_b(62) ); + u_g1_10: g1(10) <= not( x_b(63) or y_b(63) ); + + u_t1_4: t1(4) <= not( x_b(57) and y_b(57) ); + u_t1_5: t1(5) <= not( x_b(58) and y_b(58) ); + u_t1_6: t1(6) <= not( x_b(59) and y_b(59) ); + u_t1_7: t1(7) <= not( x_b(60) and y_b(60) ); + u_t1_8: t1(8) <= not( x_b(61) and y_b(61) ); + u_t1_9: t1(9) <= not( x_b(62) and y_b(62) ); + + + + u_ac_csa_0: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => x(0) , + b => y(0) , + c => z_b(0) , + sum => sum(0) , + car => unused_car ); + + u_ac_csa_1: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => x(1) , + b => y(1) , + c => z_b(1) , + sum => sum(1) , + car => car(0) ); + + u_ac_csa_2: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => x(2) , + b => y(2) , + c => z_b(2) , + sum => sum(2) , + car => car(1) ); + + u_ac_csa_3: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => x(3) , + b => y(3) , + c => z_b(3) , + sum => sum(3) , + car => car(2) ); + + u_ac_csa_4: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => x(4) , + b => y(4) , + c => z_b(4) , + sum => sum(4) , + car => car(3) ); + + + + u_g_4: g_4_b <= not( g1(4) ); + u_g_4e: g_4e <= not( g_4_b or dir_ig_57_b); + u_t_4: t_4e_b <= not( t1(4) or dir_ig_57_b); + u_t_4e: t_4e <= not( t_4e_b ); + + u_g_5t7_0: g_5t7_0_b <= not( g1(5) ); + u_g_5t7_1: g_5t7_1_b <= not( t1(5) and g1(6) ); + u_g_5t7_2: g_5t7_2_b <= not( t1(5) and t1(6) and g1(7) ); + u_g_5t7: g_5t7 <= not( g_5t7_0_b and g_5t7_1_b and g_5t7_2_b ); + u_t_5t7_0: t_5t7_b <= not( t1(5) and t1(6) and t1(7) ); + u_t_5t7: t_5t7 <= not( t_5t7_b ); + + u_g_8t10_0: g_8t10_0_b <= not( g1(8) ); + u_g_8t10_1: g_8t10_1_b <= not( t1(8) and g1(9) ); + u_g_8t10_2: g_8t10_2_b <= not( t1(8) and t1(9) and g1(10) ); + u_g_8t10: g_8t10 <= not( g_8t10_0_b and g_8t10_1_b and g_8t10_2_b ); + + u_g_4t10_0: g_4t10_0_b <= not( g_4e ) ; + u_g_4t10_1: g_4t10_1_b <= not( t_4e and g_5t7 ) ; + u_g_4t10_2: g_4t10_2_b <= not( t_4e and t_5t7 and g_8t10 ) ; + u_g_4t10: g_4t10 <= not( g_4t10_0_b and g_4t10_1_b and g_4t10_2_b ); + + + + + u_xorcmp_0: xorcmp(0) <= sum(0) xor car(0) ; + u_xorcmp_1: xorcmp(1) <= sum(1) xor car(1) ; + u_xorcmp_2: xorcmp(2) <= sum(2) xor car(2) ; + u_xorcmp_3: xorcmp(3) <= sum(3) xor car(3) ; + + u_ulp_0: ulp_0_b <= not( sum(3) and dir_ig_57 ); + u_ulp_1: ulp_1_b <= not( sum(4) and dir_ig_57_b ); + u_ulp: ulp <= not( ulp_0_b and ulp_1_b ); + + + u_en_part: enable_part <= not( inv1_val_b and ex1_cache_acc_b ); + + + u_gp1_a: gp1_a_b <= not( xorcmp(0) and xorcmp(1) and xorcmp(2) ); + u_gp2_a: gp2_a_b <= not( enable_part and ( xorcmp(3) or dir_ig_57 ) ); + u_gp12_a: gp12_a <= not( gp1_a_b or gp2_a_b ); + + u_gp3: gp3 <= ulp xor g_4t10 ; + + u_match_a: match_arr_b <= not( gp12_a and gp3 ); + u_match_i: match <= not( match_arr_b ); + match_oth <= match ; + + + + + rel3_val_01 <= rel3_val and ( way(0) or way(1) ); + rel3_val_23 <= rel3_val and ( way(2) or way(3) ); + rel3_val_45 <= rel3_val and ( way(4) or way(5) ); + rel3_val_67 <= rel3_val and ( way(6) or way(7) ); + + + u_match_lv0_i0: match_lv0_i0 <= not( match_arr_b ); + + u_match_lv1_i0: match_lv1_i0_b <= not( match_lv0_i0 ); + u_match_lv1_i1: match_lv1_i1_b <= not( match_lv0_i0 ); + + u_wact_01b: ary_write_act_01_b <= not( match_lv1_i0_b and rel3_val_01 ) ; + u_wact_45b: ary_write_act_45_b <= not( match_lv1_i0_b and rel3_val_45 ) ; + u_wact_23b: ary_write_act_23_b <= not( match_lv1_i1_b and rel3_val_23 ) ; + u_wact_67b: ary_write_act_67_b <= not( match_lv1_i1_b and rel3_val_67 ) ; + + u_wact_01: ary_write_act_01 <= not( ary_write_act_01_b ) ; + u_wact_45: ary_write_act_45 <= not( ary_write_act_45_b ) ; + u_wact_23: ary_write_act_23 <= not( ary_write_act_23_b ) ; + u_wact_67: ary_write_act_67 <= not( ary_write_act_67_b ) ; + + u_wact: ary_write_act_cpy <= not (ary_write_act_01_b & ary_write_act_23_b & ary_write_act_45_b & ary_write_act_67_b); + ary_write_act <= ary_write_act_cpy; +END; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_agen_csmux.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_agen_csmux.vhdl new file mode 100644 index 0000000..ebfe28d --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_agen_csmux.vhdl @@ -0,0 +1,100 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; use ieee.std_logic_1164.all ; +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + +entity xuq_agen_csmux is port( + sum_0 :in std_ulogic_vector(0 to 7) ; + sum_1 :in std_ulogic_vector(0 to 7) ; + ci_b :in std_ulogic ; + sum :out std_ulogic_vector(0 to 7) + ); + + +END xuq_agen_csmux; + + +ARCHITECTURE xuq_agen_csmux OF xuq_agen_csmux IS + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal sum0_b, sum1_b :std_ulogic_vector(0 to 7); + signal int_ci, int_ci_t, int_ci_b :std_ulogic; + + + + + + + + +BEGIN + + u_ci: int_ci <= not ci_b; + u_cit: int_ci_t <= not ci_b; + u_cib: int_ci_b <= not int_ci_t; + + u_sum0_0: sum0_b(0) <= not( sum_0(0) and int_ci_b ); + u_sum0_1: sum0_b(1) <= not( sum_0(1) and int_ci_b ); + u_sum0_2: sum0_b(2) <= not( sum_0(2) and int_ci_b ); + u_sum0_3: sum0_b(3) <= not( sum_0(3) and int_ci_b ); + u_sum0_4: sum0_b(4) <= not( sum_0(4) and int_ci_b ); + u_sum0_5: sum0_b(5) <= not( sum_0(5) and int_ci_b ); + u_sum0_6: sum0_b(6) <= not( sum_0(6) and int_ci_b ); + u_sum0_7: sum0_b(7) <= not( sum_0(7) and int_ci_b ); + + u_sum1_0: sum1_b(0) <= not( sum_1(0) and int_ci ); + u_sum1_1: sum1_b(1) <= not( sum_1(1) and int_ci ); + u_sum1_2: sum1_b(2) <= not( sum_1(2) and int_ci ); + u_sum1_3: sum1_b(3) <= not( sum_1(3) and int_ci ); + u_sum1_4: sum1_b(4) <= not( sum_1(4) and int_ci ); + u_sum1_5: sum1_b(5) <= not( sum_1(5) and int_ci ); + u_sum1_6: sum1_b(6) <= not( sum_1(6) and int_ci ); + u_sum1_7: sum1_b(7) <= not( sum_1(7) and int_ci ); + + u_sum_0: sum(0) <= not( sum0_b(0) and sum1_b(0) ); + u_sum_1: sum(1) <= not( sum0_b(1) and sum1_b(1) ); + u_sum_2: sum(2) <= not( sum0_b(2) and sum1_b(2) ); + u_sum_3: sum(3) <= not( sum0_b(3) and sum1_b(3) ); + u_sum_4: sum(4) <= not( sum0_b(4) and sum1_b(4) ); + u_sum_5: sum(5) <= not( sum0_b(5) and sum1_b(5) ); + u_sum_6: sum(6) <= not( sum0_b(6) and sum1_b(6) ); + u_sum_7: sum(7) <= not( sum0_b(7) and sum1_b(7) ); + + +END; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_agen_csmuxe.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_agen_csmuxe.vhdl new file mode 100644 index 0000000..760641e --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_agen_csmuxe.vhdl @@ -0,0 +1,88 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; use ieee.std_logic_1164.all ; +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + +entity xuq_agen_csmuxe is port( + sum_0 :in std_ulogic_vector(0 to 3) ; + sum_1 :in std_ulogic_vector(0 to 3) ; + ci_b :in std_ulogic ; + sum :out std_ulogic_vector(0 to 3) + ); + + +END xuq_agen_csmuxe; + + +ARCHITECTURE xuq_agen_csmuxe OF xuq_agen_csmuxe IS + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal sum0_b, sum1_b :std_ulogic_vector(0 to 3); + signal int_ci, int_ci_t, int_ci_b :std_ulogic; + + + + + + + + +BEGIN + + u_ci: int_ci <= not ci_b; + u_cit: int_ci_t <= not ci_b; + u_cib: int_ci_b <= not int_ci_t; + + u_sum0_0: sum0_b(0) <= not( sum_0(0) and int_ci_b ); + u_sum0_1: sum0_b(1) <= not( sum_0(1) and int_ci_b ); + u_sum0_2: sum0_b(2) <= not( sum_0(2) and int_ci_b ); + u_sum0_3: sum0_b(3) <= not( sum_0(3) and int_ci_b ); + + u_sum1_0: sum1_b(0) <= not( sum_1(0) and int_ci ); + u_sum1_1: sum1_b(1) <= not( sum_1(1) and int_ci ); + u_sum1_2: sum1_b(2) <= not( sum_1(2) and int_ci ); + u_sum1_3: sum1_b(3) <= not( sum_1(3) and int_ci ); + + u_sum_0: sum(0) <= not( sum0_b(0) and sum1_b(0) ); + u_sum_1: sum(1) <= not( sum0_b(1) and sum1_b(1) ); + u_sum_2: sum(2) <= not( sum0_b(2) and sum1_b(2) ); + u_sum_3: sum(3) <= not( sum0_b(3) and sum1_b(3) ); + + +END; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_agen_glbglb.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_agen_glbglb.vhdl new file mode 100644 index 0000000..96acf68 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_agen_glbglb.vhdl @@ -0,0 +1,209 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; use ieee.std_logic_1164.all ; +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + +entity xuq_agen_glbglb is port( + g08 :in std_ulogic_vector(1 to 7) ; + t08 :in std_ulogic_vector(1 to 6) ; + c64_b :out std_ulogic_vector(1 to 7) + ); + + + +END xuq_agen_glbglb; + + +ARCHITECTURE xuq_agen_glbglb OF xuq_agen_glbglb IS + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal b1_g16_b :std_ulogic_vector(0 to 3); + signal b1_t16_b :std_ulogic_vector(0 to 2); + signal b1_g32 :std_ulogic_vector(0 to 1); + signal b1_t32 :std_ulogic_vector(0 to 0); + signal b2_g16_b :std_ulogic_vector(0 to 3); + signal b2_t16_b :std_ulogic_vector(0 to 2); + signal b2_g32 :std_ulogic_vector(0 to 1); + signal b2_t32 :std_ulogic_vector(0 to 0); + signal b3_g16_b :std_ulogic_vector(0 to 3); + signal b3_t16_b :std_ulogic_vector(0 to 2); + signal b3_g32 :std_ulogic_vector(0 to 1); + signal b3_t32 :std_ulogic_vector(0 to 0); + signal b4_g16_b :std_ulogic_vector(0 to 3); + signal b4_t16_b :std_ulogic_vector(0 to 2); + signal b4_g32 :std_ulogic_vector(0 to 1); + signal b4_t32 :std_ulogic_vector(0 to 0); + signal b5_g16_b :std_ulogic_vector(0 to 2); + signal b5_t16_b :std_ulogic_vector(0 to 1); + signal b5_g32 :std_ulogic_vector(0 to 1); + signal b5_t32 :std_ulogic_vector(0 to 0); + signal b6_g16_b :std_ulogic_vector(0 to 1); + signal b6_t16_b :std_ulogic_vector(0 to 0); + signal b6_g32 :std_ulogic_vector(0 to 0); + signal b7_g16_b :std_ulogic_vector(0 to 0); + signal b7_g32 :std_ulogic_vector(0 to 0); + + + + + + + + + + + +BEGIN + + + + u1_g16_0: b1_g16_b(0) <= not( g08(1) or ( t08(1) and g08(2) ) ); + u1_g16_1: b1_g16_b(1) <= not( g08(3) or ( t08(3) and g08(4) ) ); + u1_g16_2: b1_g16_b(2) <= not( g08(5) or ( t08(5) and g08(6) ) ); + u1_g16_3: b1_g16_b(3) <= not( g08(7) ); + + u1_t16_0: b1_t16_b(0) <= not( t08(1) and t08(2) ); + u1_t16_1: b1_t16_b(1) <= not( t08(3) and t08(4) ); + u1_t16_2: b1_t16_b(2) <= not( t08(5) and t08(6) ); + + u1_g32_0: b1_g32(0) <= not( b1_g16_b(0) and ( b1_t16_b(0) or b1_g16_b(1) ) ) ; + u1_g32_1: b1_g32(1) <= not( b1_g16_b(2) and ( b1_t16_b(2) or b1_g16_b(3) ) ) ; + u1_t32_0: b1_t32(0) <= not( b1_t16_b(0) or b1_t16_b(1) ) ; + + u1_g64_0: c64_b(1) <= not( b1_g32(0) or (b1_t32(0) and b1_g32(1) ) ); + + + + u2_g16_0: b2_g16_b(0) <= not( g08(2) or ( t08(2) and g08(3) ) ); + u2_g16_1: b2_g16_b(1) <= not( g08(4) or ( t08(4) and g08(5) ) ); + u2_g16_2: b2_g16_b(2) <= not( g08(6) ); + u2_g16_3: b2_g16_b(3) <= not( g08(7) ); + + u2_t16_0: b2_t16_b(0) <= not( t08(2) and t08(3) ); + u2_t16_1: b2_t16_b(1) <= not( t08(4) and t08(5) ); + u2_t16_2: b2_t16_b(2) <= not( t08(6) ); + + u2_g32_0: b2_g32(0) <= not( b2_g16_b(0) and ( b2_t16_b(0) or b2_g16_b(1) ) ) ; + u2_g32_1: b2_g32(1) <= not( b2_g16_b(2) and ( b2_t16_b(2) or b2_g16_b(3) ) ) ; + u2_t32_0: b2_t32(0) <= not( b2_t16_b(0) or b2_t16_b(1) ) ; + + u2_g64_0: c64_b(2) <= not( b2_g32(0) or (b2_t32(0) and b2_g32(1) ) ); + + + + u3_g16_0: b3_g16_b(0) <= not( g08(3) or ( t08(3) and g08(4) ) ); + u3_g16_1: b3_g16_b(1) <= not( g08(5) ); + u3_g16_2: b3_g16_b(2) <= not( g08(6) ); + u3_g16_3: b3_g16_b(3) <= not( g08(7) ); + + u3_t16_0: b3_t16_b(0) <= not( t08(3) and t08(4) ); + u3_t16_1: b3_t16_b(1) <= not( t08(5) ); + u3_t16_2: b3_t16_b(2) <= not( t08(6) ); + + u3_g32_0: b3_g32(0) <= not( b3_g16_b(0) and ( b3_t16_b(0) or b3_g16_b(1) ) ) ; + u3_g32_1: b3_g32(1) <= not( b3_g16_b(2) and ( b3_t16_b(2) or b3_g16_b(3) ) ) ; + u3_t32_0: b3_t32(0) <= not( b3_t16_b(0) or b3_t16_b(1) ) ; + + u3_g64_0: c64_b(3) <= not( b3_g32(0) or (b3_t32(0) and b3_g32(1) ) ); + + + + u4_g16_0: b4_g16_b(0) <= not( g08(4) ); + u4_g16_1: b4_g16_b(1) <= not( g08(5) ); + u4_g16_2: b4_g16_b(2) <= not( g08(6) ); + u4_g16_3: b4_g16_b(3) <= not( g08(7) ); + + u4_t16_0: b4_t16_b(0) <= not( t08(4) ); + u4_t16_1: b4_t16_b(1) <= not( t08(5) ); + u4_t16_2: b4_t16_b(2) <= not( t08(6) ); + + u4_g32_0: b4_g32(0) <= not( b4_g16_b(0) and ( b4_t16_b(0) or b4_g16_b(1) ) ) ; + u4_g32_1: b4_g32(1) <= not( b4_g16_b(2) and ( b4_t16_b(2) or b4_g16_b(3) ) ) ; + u4_t32_0: b4_t32(0) <= not( b4_t16_b(0) or b4_t16_b(1) ) ; + + u4_g64_0: c64_b(4) <= not( b4_g32(0) or (b4_t32(0) and b4_g32(1) ) ); + + + + u5_g16_0: b5_g16_b(0) <= not( g08(5) ); + u5_g16_1: b5_g16_b(1) <= not( g08(6) ); + u5_g16_2: b5_g16_b(2) <= not( g08(7) ); + + u5_t16_0: b5_t16_b(0) <= not( t08(5) ); + u5_t16_1: b5_t16_b(1) <= not( t08(6) ); + + u5_g32_0: b5_g32(0) <= not( b5_g16_b(0) and ( b5_t16_b(0) or b5_g16_b(1) ) ) ; + u5_g32_1: b5_g32(1) <= not( b5_g16_b(2) ) ; + u5_t32_0: b5_t32(0) <= not( b5_t16_b(0) or b5_t16_b(1) ) ; + + u5_g64_0: c64_b(5) <= not( b5_g32(0) or (b5_t32(0) and b5_g32(1) ) ); + + + + u6_g16_0: b6_g16_b(0) <= not( g08(6) ); + u6_g16_1: b6_g16_b(1) <= not( g08(7) ); + + u6_t16_0: b6_t16_b(0) <= not( t08(6) ); + + + u6_g32_0: b6_g32(0) <= not( b6_g16_b(0) and ( b6_t16_b(0) or b6_g16_b(1) ) ) ; + + + u6_g64_0: c64_b(6) <= not( b6_g32(0) ) ; + + + u7_g16_0: b7_g16_b(0) <= not( g08(7) ); + + u7_g32_0: b7_g32(0) <= not( b7_g16_b(0) ); + + u7_g64_0: c64_b(7) <= not( b7_g32(0) ) ; + + +END; + + + + + + + + + + + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_agen_glbloc.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_agen_glbloc.vhdl new file mode 100644 index 0000000..9b9a3b2 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_agen_glbloc.vhdl @@ -0,0 +1,121 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; use ieee.std_logic_1164.all ; +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + +entity xuq_agen_glbloc is port( + x_b :in std_ulogic_vector(0 to 7) ; + y_b :in std_ulogic_vector(0 to 7) ; + g08 :out std_ulogic ; + t08 :out std_ulogic + ); + + + +END xuq_agen_glbloc; + + +ARCHITECTURE xuq_agen_glbloc OF xuq_agen_glbloc IS + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal g01, t01 :std_ulogic_vector(0 to 7); + signal g02_b, t02_b :std_ulogic_vector(0 to 3); + signal g04, t04 :std_ulogic_vector(0 to 1); + signal g08_b, t08_b :std_ulogic; + + + + + + + + + +BEGIN + + u_g01_0: g01(0) <= not( x_b(0) or y_b(0) ); + u_g01_1: g01(1) <= not( x_b(1) or y_b(1) ); + u_g01_2: g01(2) <= not( x_b(2) or y_b(2) ); + u_g01_3: g01(3) <= not( x_b(3) or y_b(3) ); + u_g01_4: g01(4) <= not( x_b(4) or y_b(4) ); + u_g01_5: g01(5) <= not( x_b(5) or y_b(5) ); + u_g01_6: g01(6) <= not( x_b(6) or y_b(6) ); + u_g01_7: g01(7) <= not( x_b(7) or y_b(7) ); + + u_t01_0: t01(0) <= not( x_b(0) and y_b(0) ); + u_t01_1: t01(1) <= not( x_b(1) and y_b(1) ); + u_t01_2: t01(2) <= not( x_b(2) and y_b(2) ); + u_t01_3: t01(3) <= not( x_b(3) and y_b(3) ); + u_t01_4: t01(4) <= not( x_b(4) and y_b(4) ); + u_t01_5: t01(5) <= not( x_b(5) and y_b(5) ); + u_t01_6: t01(6) <= not( x_b(6) and y_b(6) ); + u_t01_7: t01(7) <= not( x_b(7) and y_b(7) ); + + + u_g02_0: g02_b(0) <= not ( g01(0) or ( t01(0) and g01(1) ) ); + u_g02_1: g02_b(1) <= not ( g01(2) or ( t01(2) and g01(3) ) ); + u_g02_2: g02_b(2) <= not ( g01(4) or ( t01(4) and g01(5) ) ); + u_g02_3: g02_b(3) <= not ( g01(6) or ( t01(6) and g01(7) ) ); + + u_t02_0: t02_b(0) <= not ( t01(0) and t01(1) ) ; + u_t02_1: t02_b(1) <= not ( t01(2) and t01(3) ) ; + u_t02_2: t02_b(2) <= not ( t01(4) and t01(5) ) ; + u_t02_3: t02_b(3) <= not ( t01(6) and t01(7) ) ; + + + + u_g04_0: g04(0) <= not ( g02_b(0) and ( t02_b(0) or g02_b(1) ) ) ; + u_g04_1: g04(1) <= not ( g02_b(2) and ( t02_b(2) or g02_b(3) ) ) ; + + u_t04_0: t04(0) <= not ( t02_b(0) or t02_b(1) ) ; + u_t04_1: t04(1) <= not ( t02_b(2) or t02_b(3) ) ; + + + + u_g08_y: g08_b <= not ( g04(0) or ( t04(0) and g04(1) ) ) ; + + u_t08_y: t08_b <= not ( ( t04(0) and t04(1)) ) ; + + + + u_g08_x: g08 <= not ( g08_b ) ; + + u_t08_x: t08 <= not ( t08_b ) ; + +END; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_agen_glbloc_lsb.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_agen_glbloc_lsb.vhdl new file mode 100644 index 0000000..077bc8a --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_agen_glbloc_lsb.vhdl @@ -0,0 +1,111 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; use ieee.std_logic_1164.all ; +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + +entity xuq_agen_glbloc_lsb is port( + x_b :in std_ulogic_vector(0 to 7) ; + y_b :in std_ulogic_vector(0 to 7) ; + g08 :out std_ulogic + ); + + + +END xuq_agen_glbloc_lsb; + + +ARCHITECTURE xuq_agen_glbloc_lsb OF xuq_agen_glbloc_lsb IS + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal g01 :std_ulogic_vector(0 to 7); + signal t01 :std_ulogic_vector(0 to 6); + signal g02_b :std_ulogic_vector(0 to 3); + signal t02_b :std_ulogic_vector(0 to 2); + signal g04 :std_ulogic_vector(0 to 1); + signal t04 :std_ulogic_vector(0 to 0); + signal g08_b :std_ulogic; + + + + + + + + +BEGIN + + u_g01_0: g01(0) <= not( x_b(0) or y_b(0) ); + u_g01_1: g01(1) <= not( x_b(1) or y_b(1) ); + u_g01_2: g01(2) <= not( x_b(2) or y_b(2) ); + u_g01_3: g01(3) <= not( x_b(3) or y_b(3) ); + u_g01_4: g01(4) <= not( x_b(4) or y_b(4) ); + u_g01_5: g01(5) <= not( x_b(5) or y_b(5) ); + u_g01_6: g01(6) <= not( x_b(6) or y_b(6) ); + u_g01_7: g01(7) <= not( x_b(7) or y_b(7) ); + + u_t01_0: t01(0) <= not( x_b(0) and y_b(0) ); + u_t01_1: t01(1) <= not( x_b(1) and y_b(1) ); + u_t01_2: t01(2) <= not( x_b(2) and y_b(2) ); + u_t01_3: t01(3) <= not( x_b(3) and y_b(3) ); + u_t01_4: t01(4) <= not( x_b(4) and y_b(4) ); + u_t01_5: t01(5) <= not( x_b(5) and y_b(5) ); + u_t01_6: t01(6) <= not( x_b(6) and y_b(6) ); + + + u_g02_0: g02_b(0) <= not ( g01(0) or ( t01(0) and g01(1) ) ); + u_g02_1: g02_b(1) <= not ( g01(2) or ( t01(2) and g01(3) ) ); + u_g02_2: g02_b(2) <= not ( g01(4) or ( t01(4) and g01(5) ) ); + u_g02_3: g02_b(3) <= not ( g01(6) or ( t01(6) and g01(7) ) ); + + u_t02_0: t02_b(0) <= not ( t01(0) and t01(1) ) ; + u_t02_1: t02_b(1) <= not ( t01(2) and t01(3) ) ; + u_t02_2: t02_b(2) <= not ( t01(4) and t01(5) ) ; + + + + u_g04_0: g04(0) <= not ( g02_b(0) and ( t02_b(0) or g02_b(1) ) ) ; + u_g04_1: g04(1) <= not ( g02_b(2) and ( t02_b(2) or g02_b(3) ) ) ; + + u_t04_0: t04(0) <= not ( t02_b(0) or t02_b(1) ) ; + + u_g08_y: g08_b <= not ( g04(0) or ( t04(0) and g04(1) ) ) ; + u_g08_x: g08 <= not ( g08_b ) ; + + +END; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_agen_lo.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_agen_lo.vhdl new file mode 100644 index 0000000..2a6b8f4 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_agen_lo.vhdl @@ -0,0 +1,213 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; use ieee.std_logic_1164.all ; +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + +entity xuq_agen_lo is port( + x_b :in std_ulogic_vector(0 to 11) ; + y_b :in std_ulogic_vector(0 to 11) ; + sum :out std_ulogic_vector(0 to 11) ; + sum_arr :out std_ulogic_vector(1 to 5) ; + dir_ig_57_b :in std_ulogic + ); + + + + +END xuq_agen_lo; + + +ARCHITECTURE xuq_agen_lo OF xuq_agen_lo IS + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal p01_b, p01 :std_ulogic_vector(0 to 11); + signal g01 :std_ulogic_vector(1 to 11); + signal t01 :std_ulogic_vector(1 to 10); + signal sum_x, sum_b :std_ulogic_vector(0 to 11); + signal sum_x_11_b :std_ulogic; + signal g12_x_b, g02_b, g04 ,c :std_ulogic_vector(1 to 11); + signal g12_y_b :std_ulogic_vector(1 to 7); + signal g12_z_b :std_ulogic_vector(1 to 3); + signal t02_b :std_ulogic_vector(1 to 9); + signal t04 :std_ulogic_vector(1 to 7); + + + + + + + + + + + + + + + + + + + + + + + + + + + + +BEGIN + + + u_g01: g01 (1 to 11) <= not( x_b(1 to 11) or y_b(1 to 11) ); + u_t01: t01 (1 to 10) <= not( x_b(1 to 10) and y_b(1 to 10) ); + u_p01b: p01_b(0 to 11) <= not( x_b(0 to 11) xor y_b(0 to 11) ); + u_p01: p01 (0 to 11) <= not( p01_b(0 to 11) ); + + + u_sumx: sum_x(0 to 10) <= p01(0 to 10) xor c(1 to 11); + u_sumx11b: sum_x_11_b <= not( p01(11) ); + u_sumx11: sum_x(11) <= not( sum_x_11_b ); + + + u_sum_b: sum_b (0 to 11) <= not( sum_x(0 to 11) ); + u_sum: sum (0 to 11) <= not( sum_b(0 to 11) ); + u_sum_arr1: sum_arr(1) <= not( sum_b(1) ); + u_sum_arr2: sum_arr(2) <= not( sum_b(2) ); + u_sum_arr3: sum_arr(3) <= not( sum_b(3) ); + u_sum_arr4: sum_arr(4) <= not( sum_b(4) ); + u_sum_arr5: sum_arr(5) <= not( sum_b(5) and dir_ig_57_b ); + + + + u_g02_1: g02_b( 1) <= not( g01( 1) or ( t01( 1) and g01( 2) ) ); + u_g02_2: g02_b( 2) <= not( g01( 2) or ( t01( 2) and g01( 3) ) ); + u_g02_3: g02_b( 3) <= not( g01( 3) or ( t01( 3) and g01( 4) ) ); + u_g02_4: g02_b( 4) <= not( g01( 4) or ( t01( 4) and g01( 5) ) ); + u_g02_5: g02_b( 5) <= not( g01( 5) or ( t01( 5) and g01( 6) ) ); + u_g02_6: g02_b( 6) <= not( g01( 6) or ( t01( 6) and g01( 7) ) ); + u_g02_7: g02_b( 7) <= not( g01( 7) or ( t01( 7) and g01( 8) ) ); + u_g02_8: g02_b( 8) <= not( g01( 8) or ( t01( 8) and g01( 9) ) ); + u_g02_9: g02_b( 9) <= not( g01( 9) or ( t01( 9) and g01(10) ) ); + u_g02_10: g02_b(10) <= not( g01(10) or ( t01(10) and g01(11) ) ); + u_g02_11: g02_b(11) <= not( g01(11) ); + + + u_t02_1: t02_b( 1) <= not( t01( 1) and t01( 2) ); + u_t02_2: t02_b( 2) <= not( t01( 2) and t01( 3) ); + u_t02_3: t02_b( 3) <= not( t01( 3) and t01( 4) ); + u_t02_4: t02_b( 4) <= not( t01( 4) and t01( 5) ); + u_t02_5: t02_b( 5) <= not( t01( 5) and t01( 6) ); + u_t02_6: t02_b( 6) <= not( t01( 6) and t01( 7) ); + u_t02_7: t02_b( 7) <= not( t01( 7) and t01( 8) ); + u_t02_8: t02_b( 8) <= not( t01( 8) and t01( 9) ); + u_t02_9: t02_b( 9) <= not( t01( 9) and t01(10) ); + + + + u_g04_1: g04 ( 1) <= not( g02_b( 1) and ( t02_b( 1) or g02_b( 3) ) ); + u_g04_2: g04 ( 2) <= not( g02_b( 2) and ( t02_b( 2) or g02_b( 4) ) ); + u_g04_3: g04 ( 3) <= not( g02_b( 3) and ( t02_b( 3) or g02_b( 5) ) ); + u_g04_4: g04 ( 4) <= not( g02_b( 4) and ( t02_b( 4) or g02_b( 6) ) ); + u_g04_5: g04 ( 5) <= not( g02_b( 5) and ( t02_b( 5) or g02_b( 7) ) ); + u_g04_6: g04 ( 6) <= not( g02_b( 6) and ( t02_b( 6) or g02_b( 8) ) ); + u_g04_7: g04 ( 7) <= not( g02_b( 7) and ( t02_b( 7) or g02_b( 9) ) ); + u_g04_8: g04 ( 8) <= not( g02_b( 8) and ( t02_b( 8) or g02_b(10) ) ); + u_g04_9: g04 ( 9) <= not( g02_b( 9) and ( t02_b( 9) or g02_b(11) ) ); + u_g04_10: g04 (10) <= not( g02_b(10) ); + u_g04_11: g04 (11) <= not( g02_b(11) ); + + + u_t04_1: t04 ( 1) <= not( t02_b( 1) or t02_b( 3) ); + u_t04_2: t04 ( 2) <= not( t02_b( 2) or t02_b( 4) ); + u_t04_3: t04 ( 3) <= not( t02_b( 3) or t02_b( 5) ); + u_t04_4: t04 ( 4) <= not( t02_b( 4) or t02_b( 6) ); + u_t04_5: t04 ( 5) <= not( t02_b( 5) or t02_b( 7) ); + u_t04_6: t04 ( 6) <= not( t02_b( 6) or t02_b( 8) ); + u_t04_7: t04 ( 7) <= not( t02_b( 7) or t02_b( 9) ); + + + u_g12x_1: g12_x_b( 1) <= not( g04( 1) ); + u_g12y_1: g12_y_b( 1) <= not( t04( 1) and g04( 5) ); + u_g12z_1: g12_z_b( 1) <= not( t04( 1) and t04( 5) and g04( 9) ); + u_c_1: c( 1) <= not( g12_x_b( 1) and g12_y_b( 1) and g12_z_b( 1) ); + + u_g12x_2: g12_x_b( 2) <= not( g04( 2) ); + u_g12y_2: g12_y_b( 2) <= not( t04( 2) and g04( 6) ); + u_g12z_2: g12_z_b( 2) <= not( t04( 2) and t04( 6) and g04(10) ); + u_c_2: c( 2) <= not( g12_x_b( 2) and g12_y_b( 2) and g12_z_b( 2) ); + + u_g12x_3: g12_x_b( 3) <= not( g04( 3) ); + u_g12y_3: g12_y_b( 3) <= not( t04( 3) and g04( 7) ); + u_g12z_3: g12_z_b( 3) <= not( t04( 3) and t04( 7) and g04(11) ); + u_c_3: c( 3) <= not( g12_x_b( 3) and g12_y_b( 3) and g12_z_b( 3) ); + + u_g12x_4: g12_x_b( 4) <= not( g04( 4) ); + u_g12y_4: g12_y_b( 4) <= not( t04( 4) and g04( 8) ); + u_c_4: c( 4) <= not( g12_x_b( 4) and g12_y_b( 4) ); + + u_g12x_5: g12_x_b( 5) <= not( g04( 5) ); + u_g12y_5: g12_y_b( 5) <= not( t04( 5) and g04( 9) ); + u_c_5: c( 5) <= not( g12_x_b( 5) and g12_y_b( 5) ); + + u_g12x_6: g12_x_b( 6) <= not( g04( 6) ); + u_g12y_6: g12_y_b( 6) <= not( t04( 6) and g04(10) ); + u_c_6: c( 6) <= not( g12_x_b( 6) and g12_y_b( 6) ); + + u_g12x_7: g12_x_b( 7) <= not( g04( 7) ); + u_g12y_7: g12_y_b( 7) <= not( t04( 7) and g04(11) ); + u_c_7: c( 7) <= not( g12_x_b( 7) and g12_y_b( 7) ); + + u_g12x_8: g12_x_b( 8) <= not( g04( 8) ); + u_c_8: c( 8) <= not( g12_x_b( 8) ); + + u_g12x_9: g12_x_b( 9) <= not( g04( 9) ); + u_c_9: c( 9) <= not( g12_x_b( 9) ); + + u_g12x_10: g12_x_b(10) <= not( g04(10) ); + u_c_10: c(10) <= not( g12_x_b(10) ); + + u_g12x_11: g12_x_b(11) <= not( g04(11) ); + u_c_11: c(11) <= not( g12_x_b(11) ); + + + + +END; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_agen_loca.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_agen_loca.vhdl new file mode 100644 index 0000000..6efe389 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_agen_loca.vhdl @@ -0,0 +1,217 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; use ieee.std_logic_1164.all ; +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + +entity xuq_agen_loca is port( + addr_sel :in std_ulogic ; + addr_nsel :in std_ulogic ; + addr :in std_ulogic_vector(0 to 7) ; + x_b :in std_ulogic_vector(0 to 7) ; + y_b :in std_ulogic_vector(0 to 7) ; + sum_0 :out std_ulogic_vector(0 to 7) ; + sum_1 :out std_ulogic_vector(0 to 7) + ); + + + +END xuq_agen_loca; + + +ARCHITECTURE xuq_agen_loca OF xuq_agen_loca IS + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + + signal h01, h01_b :std_ulogic_vector(0 to 7); + signal x :std_ulogic_vector(0 to 7); + signal y :std_ulogic_vector(0 to 7); + signal g01_b :std_ulogic_vector(1 to 7); + signal t01_b :std_ulogic_vector(1 to 7); + signal p01 :std_ulogic_vector(0 to 7); + signal p01_b :std_ulogic_vector(0 to 7); + + + signal g08_b, g08, g04_b, g02 :std_ulogic_vector(1 to 7); + signal t02 :std_ulogic_vector(1 to 7); + signal t04_b :std_ulogic_vector(1 to 7); + signal t08 :std_ulogic_vector(1 to 7); + signal t08_b :std_ulogic_vector(1 to 7); + + + + + + + + + + + + + + + + + + + + + + + + + +BEGIN + + + + u_xi: x(0 to 7) <= not x_b(0 to 7) ; + u_yi: y(0 to 7) <= not y_b(0 to 7) ; + + + u_g01: g01_b(1 to 7) <= not( x(1 to 7) and y(1 to 7) ); + u_t01: t01_b(1 to 7) <= not( x(1 to 7) or y(1 to 7) ); + u_p01b: p01_b(0 to 7) <= not( x(0 to 7) xor y(0 to 7) ); + u_p01: p01 (0 to 7) <= not( p01_b(0 to 7) ); + + + u_h01: h01 (0 to 7) <= not( (p01_b(0 to 7) and (0 to 7=> addr_nsel) ) or + (addr (0 to 7) and (0 to 7=> addr_sel ) ) ); + + u_h01b: h01_b(0 to 7) <= not( (p01 (0 to 7) and (0 to 7=> addr_nsel) ) or + (addr (0 to 7) and (0 to 7=> addr_sel ) ) ); + + + + u_g02_1: g02(1) <= not( g01_b(1) and ( t01_b(1) or g01_b(2) ) ) ; + u_g02_2: g02(2) <= not( g01_b(2) and ( t01_b(2) or g01_b(3) ) ) ; + u_g02_3: g02(3) <= not( g01_b(3) and ( t01_b(3) or g01_b(4) ) ) ; + u_g02_4: g02(4) <= not( g01_b(4) and ( t01_b(4) or g01_b(5) ) ) ; + u_g02_5: g02(5) <= not( g01_b(5) and ( t01_b(5) or g01_b(6) ) ) ; + u_g02_6: g02(6) <= not( g01_b(6) and ( t01_b(6) or g01_b(7) ) ) ; + u_g02_7: g02(7) <= not( g01_b(7) ) ; + + u_t02_1: t02(1) <= not( t01_b(1) or t01_b(2) ) ; + u_t02_2: t02(2) <= not( t01_b(2) or t01_b(3) ) ; + u_t02_3: t02(3) <= not( t01_b(3) or t01_b(4) ) ; + u_t02_4: t02(4) <= not( t01_b(4) or t01_b(5) ) ; + u_t02_5: t02(5) <= not( t01_b(5) or t01_b(6) ) ; + u_t02_6: t02(6) <= not( g01_b(6) and ( t01_b(6) or t01_b(7) ) ) ; + u_t02_7: t02(7) <= not( t01_b(7) ) ; + + + + u_g04_1: g04_b(1) <= not( g02(1) or ( t02(1) and g02(3) ) ) ; + u_g04_2: g04_b(2) <= not( g02(2) or ( t02(2) and g02(4) ) ) ; + u_g04_3: g04_b(3) <= not( g02(3) or ( t02(3) and g02(5) ) ) ; + u_g04_4: g04_b(4) <= not( g02(4) or ( t02(4) and g02(6) ) ) ; + u_g04_5: g04_b(5) <= not( g02(5) or ( t02(5) and g02(7) ) ) ; + u_g04_6: g04_b(6) <= not( g02(6) ) ; + u_g04_7: g04_b(7) <= not( g02(7) ) ; + + u_t04_1: t04_b(1) <= not( t02(1) and t02(3) ) ; + u_t04_2: t04_b(2) <= not( t02(2) and t02(4) ) ; + u_t04_3: t04_b(3) <= not( t02(3) and t02(5) ) ; + u_t04_4: t04_b(4) <= not( g02(4) or ( t02(4) and t02(6) ) ) ; + u_t04_5: t04_b(5) <= not( g02(5) or ( t02(5) and t02(7) ) ) ; + u_t04_6: t04_b(6) <= not( t02(6) ) ; + u_t04_7: t04_b(7) <= not( t02(7) ) ; + + + + u_g08_1: g08(1) <= not( g04_b(1) and ( t04_b(1) or g04_b(5) ) ) ; + u_g08_2: g08(2) <= not( g04_b(2) and ( t04_b(2) or g04_b(6) ) ) ; + u_g08_3: g08(3) <= not( g04_b(3) and ( t04_b(3) or g04_b(7) ) ) ; + u_g08_4: g08(4) <= not( g04_b(4) ) ; + u_g08_5: g08(5) <= not( g04_b(5) ) ; + u_g08_6: g08(6) <= not( g04_b(6) ) ; + u_g08_7: g08(7) <= not( g04_b(7) ) ; + + u_t08_1: t08(1) <= not( g04_b(1) and ( t04_b(1) or t04_b(5) ) ) ; + u_t08_2: t08(2) <= not( g04_b(2) and ( t04_b(2) or t04_b(6) ) ) ; + u_t08_3: t08(3) <= not( g04_b(3) and ( t04_b(3) or t04_b(7) ) ) ; + u_t08_4: t08(4) <= not( t04_b(4) ) ; + u_t08_5: t08(5) <= not( t04_b(5) ) ; + u_t08_6: t08(6) <= not( t04_b(6) ) ; + u_t08_7: t08(7) <= not( t04_b(7) ) ; + + + + + + u_g08i_1: g08_b(1) <= not g08(1) ; + u_g08i_2: g08_b(2) <= not g08(2) ; + u_g08i_3: g08_b(3) <= not g08(3) ; + u_g08i_4: g08_b(4) <= not g08(4) ; + u_g08i_5: g08_b(5) <= not g08(5) ; + u_g08i_6: g08_b(6) <= not g08(6) ; + u_g08i_7: g08_b(7) <= not g08(7) ; + + u_t08i_1: t08_b(1) <= not t08(1) ; + u_t08i_2: t08_b(2) <= not t08(2) ; + u_t08i_3: t08_b(3) <= not t08(3) ; + u_t08i_4: t08_b(4) <= not t08(4) ; + u_t08i_5: t08_b(5) <= not t08(5) ; + u_t08i_6: t08_b(6) <= not t08(6) ; + u_t08i_7: t08_b(7) <= not t08(7) ; + + + u_sum_0_0: sum_0(0) <= not( ( h01(0) and g08(1) ) or ( h01_b(0) and g08_b(1) ) ); + u_sum_0_1: sum_0(1) <= not( ( h01(1) and g08(2) ) or ( h01_b(1) and g08_b(2) ) ); + u_sum_0_2: sum_0(2) <= not( ( h01(2) and g08(3) ) or ( h01_b(2) and g08_b(3) ) ); + u_sum_0_3: sum_0(3) <= not( ( h01(3) and g08(4) ) or ( h01_b(3) and g08_b(4) ) ); + u_sum_0_4: sum_0(4) <= not( ( h01(4) and g08(5) ) or ( h01_b(4) and g08_b(5) ) ); + u_sum_0_5: sum_0(5) <= not( ( h01(5) and g08(6) ) or ( h01_b(5) and g08_b(6) ) ); + u_sum_0_6: sum_0(6) <= not( ( h01(6) and g08(7) ) or ( h01_b(6) and g08_b(7) ) ); + u_sum_0_7: sum_0(7) <= not( h01_b(7) ); + + + u_sum_1_0: sum_1(0) <= not( ( h01(0) and t08(1) ) or ( h01_b(0) and t08_b(1) ) ); + u_sum_1_1: sum_1(1) <= not( ( h01(1) and t08(2) ) or ( h01_b(1) and t08_b(2) ) ); + u_sum_1_2: sum_1(2) <= not( ( h01(2) and t08(3) ) or ( h01_b(2) and t08_b(3) ) ); + u_sum_1_3: sum_1(3) <= not( ( h01(3) and t08(4) ) or ( h01_b(3) and t08_b(4) ) ); + u_sum_1_4: sum_1(4) <= not( ( h01(4) and t08(5) ) or ( h01_b(4) and t08_b(5) ) ); + u_sum_1_5: sum_1(5) <= not( ( h01(5) and t08(6) ) or ( h01_b(5) and t08_b(6) ) ); + u_sum_1_6: sum_1(6) <= not( ( h01(6) and t08(7) ) or ( h01_b(6) and t08_b(7) ) ); + u_sum_1_7: sum_1(7) <= not( h01(7) ); + + + + +END; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_agen_locae.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_agen_locae.vhdl new file mode 100644 index 0000000..d74d841 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_agen_locae.vhdl @@ -0,0 +1,199 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; use ieee.std_logic_1164.all ; +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + + +entity xuq_agen_locae is port( + addr_sel :in std_ulogic ; + addr_nsel :in std_ulogic ; + addr :in std_ulogic_vector(0 to 3) ; + x_b :in std_ulogic_vector(0 to 7) ; + y_b :in std_ulogic_vector(0 to 7) ; + sum_0 :out std_ulogic_vector(0 to 3) ; + sum_1 :out std_ulogic_vector(0 to 3) + ); + + + +END xuq_agen_locae; + + +ARCHITECTURE xuq_agen_locae OF xuq_agen_locae IS + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + + signal x :std_ulogic_vector(0 to 7); + signal y :std_ulogic_vector(0 to 7); + signal g01_b :std_ulogic_vector(1 to 7); + signal t01_b :std_ulogic_vector(1 to 7); + signal p01 :std_ulogic_vector(0 to 3); + signal p01_b :std_ulogic_vector(0 to 3); + + + signal g08_b :std_ulogic_vector(1 to 4); + signal g08 :std_ulogic_vector(1 to 4); + signal g04_b :std_ulogic_vector(1 to 7); + signal g02 :std_ulogic_vector(1 to 7); + signal t02 :std_ulogic_vector(1 to 7); + signal t04_b :std_ulogic_vector(1 to 7); + signal t08 :std_ulogic_vector(1 to 4); + signal t08_b :std_ulogic_vector(1 to 4); + + + + + + + + + + + + + + + + + + + signal h01, h01_b :std_ulogic_vector(0 to 3); + + + + + +BEGIN + + + + u_xi: x(0 to 7) <= not x_b(0 to 7) ; + u_yi: y(0 to 7) <= not y_b(0 to 7) ; + + + u_g01: g01_b(1 to 7) <= not( x(1 to 7) and y(1 to 7) ); + u_t01: t01_b(1 to 7) <= not( x(1 to 7) or y(1 to 7) ); + u_p01b: p01_b(0 to 3) <= not( x(0 to 3) xor y(0 to 3) ); + u_p01: p01 (0 to 3) <= not( p01_b(0 to 3) ); + + + u_g02_1: g02(1) <= not( g01_b(1) and ( t01_b(1) or g01_b(2) ) ) ; + u_g02_2: g02(2) <= not( g01_b(2) and ( t01_b(2) or g01_b(3) ) ) ; + u_g02_3: g02(3) <= not( g01_b(3) and ( t01_b(3) or g01_b(4) ) ) ; + u_g02_4: g02(4) <= not( g01_b(4) and ( t01_b(4) or g01_b(5) ) ) ; + u_g02_5: g02(5) <= not( g01_b(5) and ( t01_b(5) or g01_b(6) ) ) ; + u_g02_6: g02(6) <= not( g01_b(6) and ( t01_b(6) or g01_b(7) ) ) ; + u_g02_7: g02(7) <= not( g01_b(7) ) ; + + u_t02_1: t02(1) <= not( t01_b(1) or t01_b(2) ) ; + u_t02_2: t02(2) <= not( t01_b(2) or t01_b(3) ) ; + u_t02_3: t02(3) <= not( t01_b(3) or t01_b(4) ) ; + u_t02_4: t02(4) <= not( t01_b(4) or t01_b(5) ) ; + u_t02_5: t02(5) <= not( t01_b(5) or t01_b(6) ) ; + u_t02_6: t02(6) <= not( g01_b(6) and ( t01_b(6) or t01_b(7) ) ) ; + u_t02_7: t02(7) <= not( t01_b(7) ) ; + + + + u_g04_1: g04_b(1) <= not( g02(1) or ( t02(1) and g02(3) ) ) ; + u_g04_2: g04_b(2) <= not( g02(2) or ( t02(2) and g02(4) ) ) ; + u_g04_3: g04_b(3) <= not( g02(3) or ( t02(3) and g02(5) ) ) ; + u_g04_4: g04_b(4) <= not( g02(4) or ( t02(4) and g02(6) ) ) ; + u_g04_5: g04_b(5) <= not( g02(5) or ( t02(5) and g02(7) ) ) ; + u_g04_6: g04_b(6) <= not( g02(6) ) ; + u_g04_7: g04_b(7) <= not( g02(7) ) ; + + u_t04_1: t04_b(1) <= not( t02(1) and t02(3) ) ; + u_t04_2: t04_b(2) <= not( t02(2) and t02(4) ) ; + u_t04_3: t04_b(3) <= not( t02(3) and t02(5) ) ; + u_t04_4: t04_b(4) <= not( g02(4) or ( t02(4) and t02(6) ) ) ; + u_t04_5: t04_b(5) <= not( g02(5) or ( t02(5) and t02(7) ) ) ; + u_t04_6: t04_b(6) <= not( t02(6) ) ; + u_t04_7: t04_b(7) <= not( t02(7) ) ; + + + + u_g08_1: g08(1) <= not( g04_b(1) and ( t04_b(1) or g04_b(5) ) ) ; + u_g08_2: g08(2) <= not( g04_b(2) and ( t04_b(2) or g04_b(6) ) ) ; + u_g08_3: g08(3) <= not( g04_b(3) and ( t04_b(3) or g04_b(7) ) ) ; + u_g08_4: g08(4) <= not( g04_b(4) ) ; + + u_t08_1: t08(1) <= not( g04_b(1) and ( t04_b(1) or t04_b(5) ) ) ; + u_t08_2: t08(2) <= not( g04_b(2) and ( t04_b(2) or t04_b(6) ) ) ; + u_t08_3: t08(3) <= not( g04_b(3) and ( t04_b(3) or t04_b(7) ) ) ; + u_t08_4: t08(4) <= not( t04_b(4) ) ; + + + + + + u_g08i_1: g08_b(1) <= not g08(1) ; + u_g08i_2: g08_b(2) <= not g08(2) ; + u_g08i_3: g08_b(3) <= not g08(3) ; + u_g08i_4: g08_b(4) <= not g08(4) ; + + u_t08i_1: t08_b(1) <= not t08(1) ; + u_t08i_2: t08_b(2) <= not t08(2) ; + u_t08i_3: t08_b(3) <= not t08(3) ; + u_t08i_4: t08_b(4) <= not t08(4) ; + + + + u_h01: h01 (0 to 3) <= not( (p01_b(0 to 3) and (0 to 3=> addr_nsel) ) or + (addr (0 to 3) and (0 to 3=> addr_sel ) ) ); + + u_h01b: h01_b(0 to 3) <= not( (p01 (0 to 3) and (0 to 3=> addr_nsel) ) or + (addr (0 to 3) and (0 to 3=> addr_sel ) ) ); + + + u_sum_0_0: sum_0(0) <= not( ( h01(0) and g08(1) ) or ( h01_b(0) and g08_b(1) ) ); + u_sum_0_1: sum_0(1) <= not( ( h01(1) and g08(2) ) or ( h01_b(1) and g08_b(2) ) ); + u_sum_0_2: sum_0(2) <= not( ( h01(2) and g08(3) ) or ( h01_b(2) and g08_b(3) ) ); + u_sum_0_3: sum_0(3) <= not( ( h01(3) and g08(4) ) or ( h01_b(3) and g08_b(4) ) ); + + + u_sum_1_0: sum_1(0) <= not( ( h01(0) and t08(1) ) or ( h01_b(0) and t08_b(1) ) ); + u_sum_1_1: sum_1(1) <= not( ( h01(1) and t08(2) ) or ( h01_b(1) and t08_b(2) ) ); + u_sum_1_2: sum_1(2) <= not( ( h01(2) and t08(3) ) or ( h01_b(2) and t08_b(3) ) ); + u_sum_1_3: sum_1(3) <= not( ( h01(3) and t08(4) ) or ( h01_b(3) and t08_b(4) ) ); + + + + +END; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_alu.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_alu.vhdl new file mode 100644 index 0000000..3396de2 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_alu.vhdl @@ -0,0 +1,533 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +LIBRARY ieee; USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY ibm; + USE ibm.std_ulogic_support.all; + USE ibm.std_ulogic_unsigned.all; + USE ibm.std_ulogic_function_support.all; +LIBRARY support; + USE support.power_logic_pkg.all; +LIBRARY tri; USE tri.tri_latches_pkg.all; +LIBRARY work; USE work.xuq_pkg.all; + +entity xuq_alu is + generic( + expand_type : integer := 2; + regmode : integer := 6; + a2mode : integer := 1; + threads : integer := 4; + dc_size : natural := 14; + fxu_synth : integer := 0); + port( + nclk : in clk_logic; + + d_mode_dc : in std_ulogic; + delay_lclkr_dc : in std_ulogic; + mpw1_dc_b : in std_ulogic; + mpw2_dc_b : in std_ulogic; + func_sl_force : in std_ulogic; + func_sl_thold_0_b : in std_ulogic; + sg_0 : in std_ulogic; + scan_in : in std_ulogic_vector(0 to 1); + scan_out : out std_ulogic_vector(0 to 1); + + vdd : inout power_logic; + gnd : inout power_logic; + + spr_msr_cm : in std_ulogic_vector(0 to threads-1); + + dec_alu_rf1_act : in std_ulogic; + dec_alu_ex1_act : in std_ulogic; + dec_alu_rf1_sel : in std_ulogic_vector(0 to 3); + dec_alu_rf1_add_rs0_inv : in std_ulogic_vector(64-(2**regmode) to 63); + dec_alu_rf1_add_ci : in std_ulogic; + dec_alu_rf1_is_cmpl : in std_ulogic; + dec_alu_rf1_tw_cmpsel : in std_ulogic_vector(0 to 5); + dec_ex2_tid : in std_ulogic_vector(0 to threads-1); + dec_ex4_tid : in std_ulogic_vector(0 to threads-1); + dec_alu_rf1_mul_recform : in std_ulogic; + dec_alu_rf1_mul_val : in std_ulogic; + dec_alu_rf1_mul_ret : in std_ulogic; + dec_alu_rf1_mul_sign : in std_ulogic; + dec_alu_rf1_mul_size : in std_ulogic; + dec_alu_rf1_mul_imm : in std_ulogic; + fxa_fxb_rf1_div_ctr : in std_ulogic_vector(0 to 7); + dec_alu_rf1_div_val : in std_ulogic; + dec_alu_rf1_div_sign : in std_ulogic; + dec_alu_rf1_div_size : in std_ulogic; + dec_alu_rf1_div_extd : in std_ulogic; + dec_alu_rf1_div_recform : in std_ulogic; + dec_alu_ex1_is_cmp : in std_ulogic; + dec_alu_rf1_select_64bmode : in std_ulogic; + fxa_fxb_ex1_hold_ctr_flush : in std_ulogic; + + byp_alu_ex1_rs0 : in std_ulogic_vector(64-(2**regmode) to 63); + byp_alu_ex1_rs1 : in std_ulogic_vector(64-(2**regmode) to 63); + byp_alu_ex1_mulsrc_0 : in std_ulogic_vector(64-(2**regmode) to 63); + byp_alu_ex1_mulsrc_1 : in std_ulogic_vector(64-(2**regmode) to 63); + byp_alu_ex1_divsrc_0 : in std_ulogic_vector(64-(2**regmode) to 63); + byp_alu_ex1_divsrc_1 : in std_ulogic_vector(64-(2**regmode) to 63); + + xu_ex1_eff_addr_int : out std_ulogic_vector(64-(dc_size-3) to 63); + xu_ex2_eff_addr : out std_ulogic_vector(64-(2**regmode) to 63); + + alu_byp_ex5_mul_rt : out std_ulogic_vector(64-(2**regmode) to 63); + alu_byp_ex3_div_rt : out std_ulogic_vector(64-(2**regmode) to 63); + alu_ex2_div_done : out std_ulogic; + alu_dec_ex1_ipb_ba : out std_ulogic_vector(27 to 31); + alu_dec_ex1_ipb_sz : out std_ulogic_vector(18 to 19); + alu_dec_div_need_hole : out std_ulogic; + alu_ex3_mul_done : out std_ulogic; + alu_ex4_mul_done : out std_ulogic; + alu_cpl_ex3_trap_val : out std_ulogic; + alu_byp_ex2_rt : out std_ulogic_vector(64-(2**regmode) to 63); + alu_byp_ex1_log_rt : out std_ulogic_vector(64-(2**regmode) to 63); + + dec_alu_rf1_xer_ov_update : in std_ulogic; + dec_alu_rf1_xer_ca_update : in std_ulogic; + dec_alu_rf1_sh_right : in std_ulogic; + dec_alu_rf1_sh_word : in std_ulogic; + dec_alu_rf1_sgnxtd_byte : in std_ulogic; + dec_alu_rf1_sgnxtd_half : in std_ulogic; + dec_alu_rf1_sgnxtd_wd : in std_ulogic; + dec_alu_rf1_sra_dw : in std_ulogic; + dec_alu_rf1_sra_wd : in std_ulogic; + dec_alu_rf1_chk_shov_dw : in std_ulogic; + dec_alu_rf1_chk_shov_wd : in std_ulogic; + dec_alu_rf1_use_me_ins_hi : in std_ulogic; + dec_alu_rf1_use_me_ins_lo : in std_ulogic; + dec_alu_rf1_use_mb_ins_hi : in std_ulogic; + dec_alu_rf1_use_mb_ins_lo : in std_ulogic; + dec_alu_rf1_use_me_rb_hi : in std_ulogic; + dec_alu_rf1_use_me_rb_lo : in std_ulogic; + dec_alu_rf1_use_mb_rb_hi : in std_ulogic; + dec_alu_rf1_use_mb_rb_lo : in std_ulogic; + dec_alu_rf1_use_rb_amt_hi : in std_ulogic; + dec_alu_rf1_use_rb_amt_lo : in std_ulogic; + dec_alu_rf1_zm_ins : in std_ulogic; + byp_alu_rf1_isel_fcn : in std_ulogic_vector(0 to 3); + dec_alu_rf1_log_fcn : in std_ulogic_vector(0 to 3); + dec_alu_rf1_me_ins_b : in std_ulogic_vector(0 to 5); + dec_alu_rf1_mb_ins : in std_ulogic_vector(0 to 5); + dec_alu_rf1_sh_amt : in std_ulogic_vector(0 to 5); + dec_alu_rf1_mb_gt_me : in std_ulogic; + alu_byp_ex2_xer : out std_ulogic_vector(0 to 3); + alu_byp_ex5_xer_mul : out std_ulogic_vector(0 to 3); + alu_byp_ex3_xer_div : out std_ulogic_vector(0 to 3); + + alu_byp_ex2_cr_recform : out std_ulogic_vector(0 to 3); + alu_byp_ex5_cr_mul : out std_ulogic_vector(0 to 4); + alu_byp_ex3_cr_div : out std_ulogic_vector(0 to 4) + ); + -- synopsys translate_off + -- synopsys translate_on +end xuq_alu; + +architecture xuq_alu of xuq_alu is + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + constant regsize : integer := 2**regmode; + + signal add_log_ex1_add_rt : std_ulogic_vector(64-regsize to 63); + signal rf1_is_add_op : std_ulogic; + signal rf1_is_rot_op : std_ulogic; + signal rf1_is_cmpb_op : std_ulogic; + signal ex2_add_xer_ov : std_ulogic; + signal ex2_add_xer_ca : std_ulogic; + signal ex2_rot_xer_ca : std_ulogic; + signal ex3_div_xer_ov : std_ulogic; + signal ex3_div_xer_ov_update : std_ulogic; + signal ex2_spr_msr_cm : std_ulogic; + signal ex4_spr_msr_cm : std_ulogic; + signal ex2_cr_recform : std_ulogic_vector(0 to 3); + signal log_add_ex2_rt : std_ulogic_vector(64-(2**regmode) to 63); + signal ex2_xer_ca : std_ulogic; + signal rf1_sel_rot_log : std_ulogic; + signal byp_alu_ex1_rs0_b, byp_alu_ex1_rs1_b : std_ulogic_vector(64-(2**regmode) to 63); + + signal ex1_xer_ov_update_q : std_ulogic; + signal ex2_xer_ov_update_q, ex2_xer_ov_update_d : std_ulogic; + signal ex1_xer_ca_update_q : std_ulogic; + signal ex2_xer_ca_update_q, ex2_xer_ca_update_d : std_ulogic; + signal ex1_is_add_op_q : std_ulogic; + signal ex1_is_rot_op_q : std_ulogic; + signal ex2_is_rot_op_q : std_ulogic; + signal spr_msr_cm_q : std_ulogic_vector(0 to threads-1); + + constant ex1_xer_ov_update_offset : integer := 3; + constant ex2_xer_ov_update_offset : integer := ex1_xer_ov_update_offset + 1; + constant ex1_xer_ca_update_offset : integer := ex2_xer_ov_update_offset + 1; + constant ex2_xer_ca_update_offset : integer := ex1_xer_ca_update_offset + 1; + constant ex1_is_add_op_offset : integer := ex2_xer_ca_update_offset + 1; + constant ex1_is_rot_op_offset : integer := ex1_is_add_op_offset + 1; + constant ex2_is_rot_op_offset : integer := ex1_is_rot_op_offset + 1; + constant spr_msr_cm_offset : integer := ex2_is_rot_op_offset + 1; + constant scan_right : integer := spr_msr_cm_offset + spr_msr_cm_q'length; + signal siv : std_ulogic_vector(0 to scan_right-1); + signal sov : std_ulogic_vector(0 to scan_right-1); + + + + +begin + + u_s0i: byp_alu_ex1_rs0_b <= not byp_alu_ex1_rs0; + u_s1i: byp_alu_ex1_rs1_b <= not byp_alu_ex1_rs1; + + ex2_spr_msr_cm <= or_reduce(spr_msr_cm_q and dec_ex2_tid); + ex4_spr_msr_cm <= or_reduce(spr_msr_cm_q and dec_ex4_tid); + + rf1_sel_rot_log <= not dec_alu_rf1_sel(0); + + rf1_is_add_op <= dec_alu_rf1_sel(0); + rf1_is_rot_op <= dec_alu_rf1_sel(1); + rf1_is_cmpb_op <= dec_alu_rf1_sel(3); + + alu_dec_ex1_ipb_ba <= byp_alu_ex1_rs0(59 to 63); + alu_dec_ex1_ipb_sz <= byp_alu_ex1_rs0(50 to 51); + + + ex2_xer_ca_update_d <= ex1_xer_ca_update_q and (ex1_is_add_op_q or ex1_is_rot_op_q); + ex2_xer_ov_update_d <= ex1_xer_ov_update_q and ex1_is_add_op_q; + + with ex2_is_rot_op_q select + ex2_xer_ca <= ex2_rot_xer_ca when '1', + ex2_add_xer_ca when others; + + alu_byp_ex2_xer <= ex2_add_xer_ov & ex2_xer_ca & ex2_xer_ov_update_q & ex2_xer_ca_update_q; + alu_byp_ex3_xer_div <= ex3_div_xer_ov & tidn & ex3_div_xer_ov_update & tidn; + + alu_byp_ex2_cr_recform <= ex2_cr_recform(0 to 2) & (ex2_cr_recform(3) and ex2_xer_ov_update_q); + + xu_alu_add : entity work.xuq_alu_add(xuq_alu_add) + generic map( + expand_type => expand_type, + dc_size => dc_size, + regsize => regsize, + fxu_synth => fxu_synth) + port map( + nclk => nclk, + vdd => vdd, + gnd => gnd, + dec_alu_rf1_add_act => dec_alu_rf1_act, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc, + mpw1_dc_b => mpw1_dc_b, + mpw2_dc_b => mpw2_dc_b, + func_sl_force => func_sl_force, + func_sl_thold_0_b => func_sl_thold_0_b, + sg_0 => sg_0, + scan_in => siv(0), + scan_out => sov(0), + dec_alu_rf1_select_64bmode => dec_alu_rf1_select_64bmode, + dec_alu_rf1_add_rs0_inv => dec_alu_rf1_add_rs0_inv, + dec_alu_rf1_add_ci => dec_alu_rf1_add_ci, + dec_alu_rf1_is_cmpl => dec_alu_rf1_is_cmpl, + dec_alu_rf1_tw_cmpsel => dec_alu_rf1_tw_cmpsel, + dec_alu_ex1_is_cmp => dec_alu_ex1_is_cmp, + byp_alu_ex1_rs0 => byp_alu_ex1_rs0, + byp_alu_ex1_rs1 => byp_alu_ex1_rs1, + log_add_ex2_rt => log_add_ex2_rt, + alu_byp_ex2_rt => alu_byp_ex2_rt, + add_log_ex1_add_rt => add_log_ex1_add_rt, + xu_ex1_eff_addr_int => xu_ex1_eff_addr_int, + xu_ex2_eff_addr => xu_ex2_eff_addr, + ex2_cr_recform => ex2_cr_recform, + ex3_trap_val => alu_cpl_ex3_trap_val, + ex2_add_xer_ov => ex2_add_xer_ov, + ex2_add_xer_ca => ex2_add_xer_ca); + + xu_alu_mult : entity work.xuq_alu_mult(xuq_alu_mult) + generic map( + expand_type => expand_type, + regmode => regmode, + a2mode => a2mode, + threads => threads, + fxu_synth => fxu_synth) + port map( + nclk => nclk, + vdd => vdd, + gnd => gnd, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc, + mpw1_dc_b => mpw1_dc_b, + mpw2_dc_b => mpw2_dc_b, + func_sl_force => func_sl_force, + func_sl_thold_0_b => func_sl_thold_0_b, + sg_0 => sg_0, + scan_in => siv(1), + scan_out => sov(1), + dec_alu_rf1_mul_recform => dec_alu_rf1_mul_recform, + dec_alu_rf1_mul_val => dec_alu_rf1_mul_val, + dec_alu_rf1_mul_ret => dec_alu_rf1_mul_ret, + dec_alu_rf1_mul_sign => dec_alu_rf1_mul_sign, + dec_alu_rf1_mul_size => dec_alu_rf1_mul_size, + dec_alu_rf1_mul_imm => dec_alu_rf1_mul_imm, + dec_alu_rf1_xer_ov_update => dec_alu_rf1_xer_ov_update, + fxa_fxb_ex1_hold_ctr_flush => fxa_fxb_ex1_hold_ctr_flush, + ex4_spr_msr_cm => ex4_spr_msr_cm, + byp_alu_ex1_mulsrc_0 => byp_alu_ex1_mulsrc_0, + byp_alu_ex1_mulsrc_1 => byp_alu_ex1_mulsrc_1, + alu_ex3_mul_done => alu_ex3_mul_done, + alu_ex4_mul_done => alu_ex4_mul_done, + alu_byp_ex5_mul_rt => alu_byp_ex5_mul_rt, + alu_byp_ex5_xer_mul => alu_byp_ex5_xer_mul, + alu_byp_ex5_cr_mul => alu_byp_ex5_cr_mul); + + xuq_alu_div : entity work.xuq_alu_div(xuq_alu_div) + generic map( + expand_type => expand_type, + regsize => regsize) + port map( + nclk => nclk, + vdd => vdd, + gnd => gnd, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc, + mpw1_dc_b => mpw1_dc_b, + mpw2_dc_b => mpw2_dc_b, + func_sl_force => func_sl_force, + func_sl_thold_0_b => func_sl_thold_0_b, + sg_0 => sg_0, + scan_in => scan_in(0), + scan_out => scan_out(0), + fxa_fxb_rf1_div_ctr => fxa_fxb_rf1_div_ctr, + dec_alu_rf1_div_val => dec_alu_rf1_div_val, + dec_alu_rf1_div_sign => dec_alu_rf1_div_sign, + dec_alu_rf1_div_size => dec_alu_rf1_div_size, + dec_alu_rf1_div_extd => dec_alu_rf1_div_extd, + dec_alu_rf1_div_recform => dec_alu_rf1_div_recform, + byp_alu_ex1_divsrc_0 => byp_alu_ex1_divsrc_0, + byp_alu_ex1_divsrc_1 => byp_alu_ex1_divsrc_1, + fxa_fxb_ex1_hold_ctr_flush => fxa_fxb_ex1_hold_ctr_flush, + dec_alu_rf1_xer_ov_update => dec_alu_rf1_xer_ov_update, + alu_dec_div_need_hole => alu_dec_div_need_hole, + alu_byp_ex3_div_rt => alu_byp_ex3_div_rt, + alu_ex2_div_done => alu_ex2_div_done, + ex3_div_xer_ov => ex3_div_xer_ov, + ex3_div_xer_ov_update => ex3_div_xer_ov_update, + alu_byp_ex3_cr_div => alu_byp_ex3_cr_div, + ex2_spr_msr_cm => ex2_spr_msr_cm); + + xuq_alu_mrg : entity work.xuq_alu_mrg(xuq_alu_mrg) + generic map( + expand_type => expand_type) + port map( + nclk => nclk, + vdd => vdd, + gnd => gnd, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc, + mpw1_dc_b => mpw1_dc_b, + mpw2_dc_b => mpw2_dc_b, + func_sl_force => func_sl_force, + func_sl_thold_0_b => func_sl_thold_0_b, + sg_0 => sg_0, + scan_in => siv(2), + scan_out => sov(2), + rf1_act => dec_alu_rf1_act, + ex1_act => dec_alu_ex1_act, + dec_alu_rf1_zm_ins => dec_alu_rf1_zm_ins, + dec_alu_rf1_mb_ins => dec_alu_rf1_mb_ins, + dec_alu_rf1_me_ins_b => dec_alu_rf1_me_ins_b, + dec_alu_rf1_sh_amt => dec_alu_rf1_sh_amt, + dec_alu_rf1_sh_right => dec_alu_rf1_sh_right, + dec_alu_rf1_sh_word => dec_alu_rf1_sh_word, + dec_alu_rf1_use_rb_amt_hi => dec_alu_rf1_use_rb_amt_hi, + dec_alu_rf1_use_rb_amt_lo => dec_alu_rf1_use_rb_amt_lo, + dec_alu_rf1_use_me_rb_hi => dec_alu_rf1_use_me_rb_hi, + dec_alu_rf1_use_me_rb_lo => dec_alu_rf1_use_me_rb_lo, + dec_alu_rf1_use_mb_rb_hi => dec_alu_rf1_use_mb_rb_hi, + dec_alu_rf1_use_mb_rb_lo => dec_alu_rf1_use_mb_rb_lo, + dec_alu_rf1_use_me_ins_hi => dec_alu_rf1_use_me_ins_hi, + dec_alu_rf1_use_me_ins_lo => dec_alu_rf1_use_me_ins_lo, + dec_alu_rf1_use_mb_ins_hi => dec_alu_rf1_use_mb_ins_hi, + dec_alu_rf1_use_mb_ins_lo => dec_alu_rf1_use_mb_ins_lo, + dec_alu_rf1_chk_shov_wd => dec_alu_rf1_chk_shov_wd, + dec_alu_rf1_chk_shov_dw => dec_alu_rf1_chk_shov_dw, + dec_alu_rf1_mb_gt_me => dec_alu_rf1_mb_gt_me, + dec_alu_rf1_cmp_byt => rf1_is_cmpb_op, + dec_alu_rf1_sgnxtd_byte => dec_alu_rf1_sgnxtd_byte, + dec_alu_rf1_sgnxtd_half => dec_alu_rf1_sgnxtd_half, + dec_alu_rf1_sgnxtd_wd => dec_alu_rf1_sgnxtd_wd, + dec_alu_rf1_sra_wd => dec_alu_rf1_sra_wd, + dec_alu_rf1_sra_dw => dec_alu_rf1_sra_dw, + byp_alu_rf1_isel_fcn => byp_alu_rf1_isel_fcn, + dec_alu_rf1_log_fcn => dec_alu_rf1_log_fcn, + dec_alu_rf1_sel_rot_log => rf1_sel_rot_log, + byp_alu_ex1_rs0_b => byp_alu_ex1_rs0_b, + byp_alu_ex1_rs1_b => byp_alu_ex1_rs1_b, + add_mrg_ex1_add_rt => add_log_ex1_add_rt, + alu_byp_ex1_log_rt => alu_byp_ex1_log_rt, + mrg_add_ex2_rt => log_add_ex2_rt, + ex2_mrg_xer_ca => ex2_rot_xer_ca); + + + mark_unused(dec_alu_rf1_sel(2)); + ex1_xer_ov_update_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_xer_ov_update_offset), + scout => sov(ex1_xer_ov_update_offset), + din => dec_alu_rf1_xer_ov_update, + dout => ex1_xer_ov_update_q); + ex2_xer_ov_update_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_xer_ov_update_offset), + scout => sov(ex2_xer_ov_update_offset), + din => ex2_xer_ov_update_d, + dout => ex2_xer_ov_update_q); + ex1_xer_ca_update_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_xer_ca_update_offset), + scout => sov(ex1_xer_ca_update_offset), + din => dec_alu_rf1_xer_ca_update, + dout => ex1_xer_ca_update_q); + ex2_xer_ca_update_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_xer_ca_update_offset), + scout => sov(ex2_xer_ca_update_offset), + din => ex2_xer_ca_update_d, + dout => ex2_xer_ca_update_q); + ex1_is_add_op_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_add_op_offset), + scout => sov(ex1_is_add_op_offset), + din => rf1_is_add_op, + dout => ex1_is_add_op_q); + ex1_is_rot_op_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_rot_op_offset), + scout => sov(ex1_is_rot_op_offset), + din => rf1_is_rot_op, + dout => ex1_is_rot_op_q); + ex2_is_rot_op_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_is_rot_op_offset), + scout => sov(ex2_is_rot_op_offset), + din => ex1_is_rot_op_q, + dout => ex2_is_rot_op_q); + spr_msr_cm_latch : tri_rlmreg_p + generic map (width => spr_msr_cm_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(spr_msr_cm_offset to spr_msr_cm_offset + spr_msr_cm_q'length-1), + scout => sov(spr_msr_cm_offset to spr_msr_cm_offset + spr_msr_cm_q'length-1), + din => spr_msr_cm, + dout => spr_msr_cm_q); + siv(0 to siv'right) <= sov(1 to siv'right) & scan_in(1); + scan_out(1) <= sov(0); + +end architecture xuq_alu; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_alu_add.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_alu_add.vhdl new file mode 100644 index 0000000..b04ade3 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_alu_add.vhdl @@ -0,0 +1,604 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +LIBRARY ieee; USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY ibm; + USE ibm.std_ulogic_support.all; + USE ibm.std_ulogic_unsigned.all; + USE ibm.std_ulogic_function_support.all; +LIBRARY support; + USE support.power_logic_pkg.all; +LIBRARY tri; USE tri.tri_latches_pkg.all; + +entity xuq_alu_add is + generic( + expand_type : integer := 2; + dc_size : natural := 14; + regsize : integer := 64; + fxu_synth : integer := 0); + port( + nclk : in clk_logic; + + vdd : inout power_logic; + gnd : inout power_logic; + + dec_alu_rf1_add_act : in std_ulogic; + d_mode_dc : in std_ulogic; + delay_lclkr_dc : in std_ulogic; + mpw1_dc_b : in std_ulogic; + mpw2_dc_b : in std_ulogic; + func_sl_force : in std_ulogic; + func_sl_thold_0_b : in std_ulogic; + sg_0 : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + dec_alu_rf1_select_64bmode : in std_ulogic; + + dec_alu_rf1_add_rs0_inv : in std_ulogic_vector(64-regsize to 63); + dec_alu_rf1_add_ci : in std_ulogic; + dec_alu_rf1_is_cmpl : in std_ulogic; + dec_alu_rf1_tw_cmpsel : in std_ulogic_vector(0 to 5); + dec_alu_ex1_is_cmp : in std_ulogic; + + byp_alu_ex1_rs0 : in std_ulogic_vector(64-regsize to 63); + byp_alu_ex1_rs1 : in std_ulogic_vector(64-regsize to 63); + + log_add_ex2_rt :in std_ulogic_vector(64-regsize to 63); + alu_byp_ex2_rt :out std_ulogic_vector(64-regsize to 63); + + add_log_ex1_add_rt : out std_ulogic_vector(64-regsize to 63); + ex2_cr_recform : out std_ulogic_vector(0 to 3); + + xu_ex1_eff_addr_int : out std_ulogic_vector(64-(dc_size-3) to 63); + xu_ex2_eff_addr : out std_ulogic_vector(64-regsize to 63); + + ex3_trap_val : out std_ulogic; + + ex2_add_xer_ov : out std_ulogic; + ex2_add_xer_ca : out std_ulogic + ); + -- synopsys translate_off + + -- synopsys translate_on + + + +end xuq_alu_add; +architecture xuq_alu_add of xuq_alu_add is + constant msb : integer := 64-regsize; + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal ex1_add_act_q : std_ulogic; + signal ex1_rs0_inv_q, ex1_rs0_inv_q_b : std_ulogic_vector(64-regsize to 63); + signal ex1_add_ci_q : std_ulogic; + signal ex1_is_cmpl_q : std_ulogic; + signal ex1_tw_cmpsel_q : std_ulogic_vector(0 to 5); + signal ex2_add_xer_ca_q, ex2_add_xer_ca_d : std_ulogic; + signal ex2_rs0_msb_q, ex2_rs0_msb_d : std_ulogic; + signal ex2_rs1_msb_q, ex2_rs1_msb_d : std_ulogic; + signal ex2_is_cmpl_q : std_ulogic; + signal ex2_overflow_q : std_ulogic; + signal ex2_tw_cmpsel_q : std_ulogic_vector(0 to 5); + signal ex2_is_cmp_q : std_ulogic; + signal ex2_eff_addr_q, ex2_eff_addr_q_b, ex2_eff_addr_d : std_ulogic_vector(64-regsize to 63); + signal ex3_trap_val_q, ex3_trap_val_d : std_ulogic; + signal ex1_select_64bmode_q : std_ulogic; + signal ex2_select_32bcmp_q, ex1_select_32bcmp : std_ulogic; + constant ex1_add_act_offset : integer := 0; + constant ex1_rs0_inv_offset : integer := ex1_add_act_offset + 1; + constant ex1_add_ci_offset : integer := ex1_rs0_inv_offset + ex1_rs0_inv_q'length; + constant ex1_is_cmpl_offset : integer := ex1_add_ci_offset + 1; + constant ex1_tw_cmpsel_offset : integer := ex1_is_cmpl_offset + 1; + constant ex2_add_xer_ca_offset : integer := ex1_tw_cmpsel_offset + ex1_tw_cmpsel_q'length; + constant ex2_rs0_msb_offset : integer := ex2_add_xer_ca_offset + 1; + constant ex2_rs1_msb_offset : integer := ex2_rs0_msb_offset + 1; + constant ex2_is_cmpl_offset : integer := ex2_rs1_msb_offset + 1; + constant ex2_overflow_offset : integer := ex2_is_cmpl_offset + 1; + constant ex2_tw_cmpsel_offset : integer := ex2_overflow_offset + 1; + constant ex2_is_cmp_offset : integer := ex2_tw_cmpsel_offset + ex2_tw_cmpsel_q'length; + constant ex2_eff_addr_offset : integer := ex2_is_cmp_offset + 1; + constant ex3_trap_val_offset : integer := ex2_eff_addr_offset + ex2_eff_addr_q'length; + constant ex1_select_64bmode_offset : integer := ex3_trap_val_offset + 1; + constant ex2_select_32bcmp_offset : integer := ex1_select_64bmode_offset + 1; + constant scan_right : integer := ex2_select_32bcmp_offset + 1; + signal siv : std_ulogic_vector(0 to scan_right-1); + signal sov : std_ulogic_vector(0 to scan_right-1); + signal ex1_lclk_int : clk_logic; + signal ex1_d1clk_int, ex1_d2clk_int : std_ulogic; + signal ex2_lclk_int : clk_logic; + signal ex2_d1clk_int, ex2_d2clk_int : std_ulogic; + signal ex1_aop_00 : std_ulogic; + signal ex1_bop_00 : std_ulogic; + signal ex1_aop_32 : std_ulogic; + signal ex1_bop_32 : std_ulogic; + signal ex1_x_b, ex1_y_b , ex1_y : std_ulogic_vector(64-regsize to 63); + signal aop_rep_b , bop_rep_b : std_ulogic_vector(64-regsize to 63); + signal ex1_add_rslt : std_ulogic_vector(64-regsize to 63); + signal ex1_cout_32 : std_ulogic; + signal ex1_cout_00 : std_ulogic; + signal ex2_diff_sign : std_ulogic; + signal ex2_cmp0_eq : std_ulogic; + signal ex2_rslt_gt_s : std_ulogic; + signal ex2_rslt_lt_s : std_ulogic; + signal ex2_rslt_gt_u : std_ulogic; + signal ex2_rslt_lt_u : std_ulogic; + signal ex2_cmp_eq : std_ulogic; + signal ex2_cmp_gt : std_ulogic; + signal ex2_cmp_lt : std_ulogic; + signal ex2_sign_cmp : std_ulogic; + signal ex2_rt_msb : std_ulogic; + signal ex1_overflow : std_ulogic; + signal ex2_cmp0_lo , ex2_cmp0_hi : std_ulogic; + signal ex1_sgn00_32, ex1_sgn11_32 : std_ulogic; + signal ex1_sgn00_64, ex1_sgn11_64 : std_ulogic; + signal ex1_ovf32_00_b, ex1_ovf32_11_b : std_ulogic; + signal ex1_ovf64_00_b, ex1_ovf64_11_b : std_ulogic; + + signal eff0_b, eff0, eff1_b, eff1 : std_ulogic_vector(64-(dc_size-3) to 63); + signal alu_byp_ex2_rt_b : std_ulogic_vector(64-regsize to 63); + + + + + + + + + +begin + + + ex1_select_32bcmp <= not ex1_select_64bmode_q; + + aop_rep_b <= not( byp_alu_ex1_rs0 ) ; + bop_rep_b <= not( byp_alu_ex1_rs1 ) ; + + u_aop_xor: ex1_x_b <= aop_rep_b xor ex1_rs0_inv_q ; + u_bop_i: ex1_y <= not bop_rep_b ; + u_bop_ii: ex1_y_b <= not ex1_y ; + u_aop_slow00: ex1_aop_00 <= not ex1_x_b(msb); + u_aop_slow32: ex1_aop_32 <= not ex1_x_b(32) ; + u_bop_slow00: ex1_bop_00 <= not ex1_y_b(msb); + u_bop_slow32: ex1_bop_32 <= not ex1_y_b(32) ; + + + csa: entity work.xuq_add(xuq_add) + port map( + x_b(0 to 63) => ex1_x_b, + y_b(0 to 63) => ex1_y_b, + ci(8) => ex1_add_ci_q, + sum(0 to 63) => ex1_add_rslt, + cout_32 => ex1_cout_32, + cout_0 => ex1_cout_00); + + ex1_sgn00_32 <= not ex1_select_64bmode_q and not ex1_aop_32 and not ex1_bop_32 ; + ex1_sgn11_32 <= not ex1_select_64bmode_q and ex1_aop_32 and ex1_bop_32 ; + ex1_sgn00_64 <= ex1_select_64bmode_q and not ex1_aop_00 and not ex1_bop_00 ; + ex1_sgn11_64 <= ex1_select_64bmode_q and ex1_aop_00 and ex1_bop_00 ; + + ex1_ovf32_00_b <= not( ex1_add_rslt(32) and ex1_sgn00_32 ); + ex1_ovf32_11_b <= not( not ex1_add_rslt(32) and ex1_sgn11_32 ); + ex1_ovf64_00_b <= not( ex1_add_rslt(msb) and ex1_sgn00_64 ); + ex1_ovf64_11_b <= not( not ex1_add_rslt(msb) and ex1_sgn11_64 ); + + ex1_overflow <= not ( ex1_ovf64_00_b and + ex1_ovf64_11_b and + ex1_ovf32_00_b and + ex1_ovf32_11_b ); + + + + ex2_add_xer_ov <= ex2_overflow_q; + + + +add_64b_compare : if regsize = 64 generate + + or3232: entity work.xuq_alu_or3232(xuq_alu_or3232) + generic map (expand_type => expand_type) + port map( + d => log_add_ex2_rt(0 to 63) , + or_hi_b => ex2_cmp0_hi , + or_lo_b => ex2_cmp0_lo ); + + ex2_cmp0_eq <= (ex2_cmp0_hi or ex2_select_32bcmp_q) and ex2_cmp0_lo; + + with ex1_select_32bcmp select + ex2_rs0_msb_d <= byp_alu_ex1_rs0(32) when '1', + byp_alu_ex1_rs0(0) when others; + with ex1_select_32bcmp select + ex2_rs1_msb_d <= byp_alu_ex1_rs1(32) when '1', + byp_alu_ex1_rs1(0) when others; + with ex2_select_32bcmp_q select + ex2_rt_msb <= log_add_ex2_rt(32) when '1', + log_add_ex2_rt(0) when others; +end generate; + + + u_ex2_rt_bufi: alu_byp_ex2_rt_b <= not log_add_ex2_rt ; + u_ex2_rt_buf: alu_byp_ex2_rt <= not alu_byp_ex2_rt_b ; + +add_32b_compare : if regsize = 32 generate + ex2_cmp0_lo <= not or_reduce(log_add_ex2_rt(32 to 63)); + ex2_cmp0_hi <= '1'; + ex2_cmp0_eq <= ex2_cmp0_lo; + ex2_rs0_msb_d <= byp_alu_ex1_rs0(32); + ex2_rs1_msb_d <= byp_alu_ex1_rs1(32); + ex2_rt_msb <= log_add_ex2_rt(32); +end generate; + + ex2_diff_sign <= (ex2_rs0_msb_q xor ex2_rs1_msb_q) and ex2_is_cmp_q; + + with ex2_is_cmp_q select + ex2_sign_cmp <= ex2_add_xer_ca_q when '1', + ex2_rt_msb when others; + + ex2_rslt_gt_s <= ((ex2_rs1_msb_q and ex2_diff_sign) or (not ex2_sign_cmp and not ex2_diff_sign)) and not ex2_cmp0_eq; + ex2_rslt_lt_s <= ((ex2_rs0_msb_q and ex2_diff_sign) or ( ex2_sign_cmp and not ex2_diff_sign)) and not ex2_cmp0_eq; + + ex2_rslt_gt_u <= ((ex2_rs0_msb_q and ex2_diff_sign) or (not ex2_sign_cmp and not ex2_diff_sign)) and not ex2_cmp0_eq; + ex2_rslt_lt_u <= ((ex2_rs1_msb_q and ex2_diff_sign) or ( ex2_sign_cmp and not ex2_diff_sign)) and not ex2_cmp0_eq; + + ex2_cmp_eq <= ex2_cmp0_eq; + ex2_cmp_gt <= (not ex2_is_cmpl_q and ex2_rslt_gt_s) or (ex2_is_cmpl_q and ex2_rslt_gt_u); + ex2_cmp_lt <= (not ex2_is_cmpl_q and ex2_rslt_lt_s) or (ex2_is_cmpl_q and ex2_rslt_lt_u); + + ex2_cr_recform <= ex2_cmp_lt & ex2_cmp_gt & ex2_cmp_eq & ex2_overflow_q; + + ex3_trap_val_d <= ex2_tw_cmpsel_q(0) and ( + (ex2_tw_cmpsel_q(1) and ex2_rslt_lt_s) or + (ex2_tw_cmpsel_q(2) and ex2_rslt_gt_s) or + (ex2_tw_cmpsel_q(3) and ex2_cmp_eq) or + (ex2_tw_cmpsel_q(4) and ex2_rslt_lt_u) or + (ex2_tw_cmpsel_q(5) and ex2_rslt_gt_u)); + + ex3_trap_val <= ex3_trap_val_q; + + with ex1_select_32bcmp select + ex2_add_xer_ca_d <= ex1_cout_32 when '1', + ex1_cout_00 when others; + + ex2_add_xer_ca <= ex2_add_xer_ca_q; + +add_64b_retval : if regsize = 64 generate + add_log_ex1_add_rt <= ex1_add_rslt; + ex2_eff_addr_d <= (ex1_add_rslt(0 to 31) and (0 to 31 => ex1_select_64bmode_q)) & ex1_add_rslt(32 to 63); +end generate; +add_32b_retval : if regsize = 32 generate + add_log_ex1_add_rt <= ex1_add_rslt(32 to 63); + ex2_eff_addr_d <= ex1_add_rslt(32 to 63); +end generate; + + u_eff0_inv1: eff0_b <= not byp_alu_ex1_rs0(64-(dc_size-3) to 63) ; + u_eff0_inv2: eff0 <= not eff0_b ; + u_eff1_inv1: eff1_b <= not byp_alu_ex1_rs1(64-(dc_size-3) to 63) ; + u_eff1_inv2: eff1 <= not eff1_b ; + + xu_ex1_eff_addr_int <= std_ulogic_vector( unsigned(eff0) + unsigned(eff1) ); + + xu_ex2_eff_addr <= ex2_eff_addr_q; + + ex1_add_act_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_add_act_offset), + scout => sov(ex1_add_act_offset), + din => dec_alu_rf1_add_act, + dout => ex1_add_act_q); + ex1_add_ci_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => dec_alu_rf1_add_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_add_ci_offset), + scout => sov(ex1_add_ci_offset), + din => dec_alu_rf1_add_ci, + dout => ex1_add_ci_q); + ex1_is_cmpl_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => dec_alu_rf1_add_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_cmpl_offset), + scout => sov(ex1_is_cmpl_offset), + din => dec_alu_rf1_is_cmpl, + dout => ex1_is_cmpl_q); + ex1_tw_cmpsel_latch : tri_rlmreg_p + generic map (width => ex1_tw_cmpsel_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => dec_alu_rf1_add_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_tw_cmpsel_offset to ex1_tw_cmpsel_offset + ex1_tw_cmpsel_q'length-1), + scout => sov(ex1_tw_cmpsel_offset to ex1_tw_cmpsel_offset + ex1_tw_cmpsel_q'length-1), + din => dec_alu_rf1_tw_cmpsel, + dout => ex1_tw_cmpsel_q); + ex2_add_xer_ca_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => ex1_add_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_add_xer_ca_offset), + scout => sov(ex2_add_xer_ca_offset), + din => ex2_add_xer_ca_d, + dout => ex2_add_xer_ca_q); + ex2_rs0_msb_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_rs0_msb_offset), + scout => sov(ex2_rs0_msb_offset), + din => ex2_rs0_msb_d, + dout => ex2_rs0_msb_q); + ex2_rs1_msb_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_rs1_msb_offset), + scout => sov(ex2_rs1_msb_offset), + din => ex2_rs1_msb_d, + dout => ex2_rs1_msb_q); + ex2_is_cmpl_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_is_cmpl_offset), + scout => sov(ex2_is_cmpl_offset), + din => ex1_is_cmpl_q, + dout => ex2_is_cmpl_q); + ex2_overflow_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_overflow_offset), + scout => sov(ex2_overflow_offset), + din => ex1_overflow, + dout => ex2_overflow_q); + ex2_tw_cmpsel_latch : tri_rlmreg_p + generic map (width => ex2_tw_cmpsel_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_tw_cmpsel_offset to ex2_tw_cmpsel_offset + ex2_tw_cmpsel_q'length-1), + scout => sov(ex2_tw_cmpsel_offset to ex2_tw_cmpsel_offset + ex2_tw_cmpsel_q'length-1), + din => ex1_tw_cmpsel_q, + dout => ex2_tw_cmpsel_q); + ex2_is_cmp_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_is_cmp_offset), + scout => sov(ex2_is_cmp_offset), + din => dec_alu_ex1_is_cmp, + dout => ex2_is_cmp_q); + ex3_trap_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_trap_val_offset), + scout => sov(ex3_trap_val_offset), + din => ex3_trap_val_d, + dout => ex3_trap_val_q); + ex1_select_64bmode_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_select_64bmode_offset), + scout => sov(ex1_select_64bmode_offset), + din => dec_alu_rf1_select_64bmode, + dout => ex1_select_64bmode_q); + ex2_select_32bcmp_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_select_32bcmp_offset), + scout => sov(ex2_select_32bcmp_offset), + din => ex1_select_32bcmp, + dout => ex2_select_32bcmp_q); + + + +ex2_lcb: entity tri.tri_lcbnd(tri_lcbnd) + port map(vd => vdd, + gd => gnd, + act => ex1_add_act_q, + nclk => nclk, + forcee => func_sl_force, + thold_b => func_sl_thold_0_b, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + sg => sg_0, + lclk => ex2_lclk_int, + d1clk => ex2_d1clk_int, + d2clk => ex2_d2clk_int); + +ex1_lcb: entity tri.tri_lcbnd(tri_lcbnd) + port map(vd => vdd, + gd => gnd, + act => dec_alu_rf1_add_act, + nclk => nclk, + forcee => func_sl_force, + thold_b => func_sl_thold_0_b, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + sg => sg_0, + lclk => ex1_lclk_int, + d1clk => ex1_d1clk_int, + d2clk => ex1_d2clk_int); + + + ex2_eff_addr_lat: entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width => ex2_eff_addr_q'length, expand_type => expand_type, btr => "NLI0001_X1_A12TH", init=>(ex2_eff_addr_q'range=>'0')) + port map (vd => vdd, gd => gnd, + LCLK => ex2_lclk_int, + D1CLK => ex2_d1clk_int, + D2CLK => ex2_d2clk_int, + SCANIN => siv(ex2_eff_addr_offset to ex2_eff_addr_offset + ex2_eff_addr_q'length-1), + SCANOUT => sov(ex2_eff_addr_offset to ex2_eff_addr_offset + ex2_eff_addr_q'length-1), + D => ex2_eff_addr_d, + QB => ex2_eff_addr_q_b ); + + u_ex2_eff_addr_q: ex2_eff_addr_q <= not ex2_eff_addr_q_b ; + + ex1_rs0_inv_lat: entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width => ex1_rs0_inv_q'length, expand_type => expand_type, btr => "NLI0001_X1_A12TH", init=>(ex1_rs0_inv_q'range=>'0')) + port map (vd => vdd, gd => gnd, + LCLK => ex1_lclk_int, + D1CLK => ex1_d1clk_int, + D2CLK => ex1_d2clk_int, + SCANIN => siv(ex1_rs0_inv_offset to ex1_rs0_inv_offset + ex1_rs0_inv_q'length-1), + SCANOUT => sov(ex1_rs0_inv_offset to ex1_rs0_inv_offset + ex1_rs0_inv_q'length-1), + D => dec_alu_rf1_add_rs0_inv, + QB => ex1_rs0_inv_q_b ); + + u_ex1_rs0_inv_q: ex1_rs0_inv_q <= not ex1_rs0_inv_q_b ; + + + + siv(0 to siv'right) <= sov(1 to siv'right) & scan_in; + scan_out <= sov(0); + +end architecture xuq_alu_add; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_alu_caor.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_alu_caor.vhdl new file mode 100644 index 0000000..85ebeb3 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_alu_caor.vhdl @@ -0,0 +1,150 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +LIBRARY ieee; USE ieee.std_logic_1164.all; + use ieee.numeric_std.all; +LIBRARY ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; +LIBRARY support; + use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity xuq_alu_caor is generic(expand_type: integer := 2 ); port ( + + + + ca_root_b :in std_ulogic_vector(0 to 63) ; + ca_or_hi :out std_ulogic ; + ca_or_lo :out std_ulogic +); + +-- synopsys translate_off +-- synopsys translate_on +end xuq_alu_caor; + +architecture xuq_alu_caor of xuq_alu_caor is + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + + signal ca_or_lv1 :std_ulogic_vector(0 to 31) ; + signal ca_or_lv2_b :std_ulogic_vector(0 to 15) ; + signal ca_or_lv3 :std_ulogic_vector(0 to 7) ; + signal ca_or_lv4_b :std_ulogic_vector(0 to 3) ; + signal ca_or_lv5 :std_ulogic_vector(0 to 1) ; + + + + + + + + + +begin + + + + u_ca_or_00: ca_or_lv1 ( 0) <= not( ca_root_b ( 0) and ca_root_b ( 1) ); + u_ca_or_02: ca_or_lv1 ( 1) <= not( ca_root_b ( 2) and ca_root_b ( 3) ); + u_ca_or_04: ca_or_lv1 ( 2) <= not( ca_root_b ( 4) and ca_root_b ( 5) ); + u_ca_or_06: ca_or_lv1 ( 3) <= not( ca_root_b ( 6) and ca_root_b ( 7) ); + u_ca_or_08: ca_or_lv1 ( 4) <= not( ca_root_b ( 8) and ca_root_b ( 9) ); + u_ca_or_10: ca_or_lv1 ( 5) <= not( ca_root_b (10) and ca_root_b (11) ); + u_ca_or_12: ca_or_lv1 ( 6) <= not( ca_root_b (12) and ca_root_b (13) ); + u_ca_or_14: ca_or_lv1 ( 7) <= not( ca_root_b (14) and ca_root_b (15) ); + u_ca_or_16: ca_or_lv1 ( 8) <= not( ca_root_b (16) and ca_root_b (17) ); + u_ca_or_18: ca_or_lv1 ( 9) <= not( ca_root_b (18) and ca_root_b (19) ); + u_ca_or_20: ca_or_lv1 (10) <= not( ca_root_b (20) and ca_root_b (21) ); + u_ca_or_22: ca_or_lv1 (11) <= not( ca_root_b (22) and ca_root_b (23) ); + u_ca_or_24: ca_or_lv1 (12) <= not( ca_root_b (24) and ca_root_b (25) ); + u_ca_or_26: ca_or_lv1 (13) <= not( ca_root_b (26) and ca_root_b (27) ); + u_ca_or_28: ca_or_lv1 (14) <= not( ca_root_b (28) and ca_root_b (29) ); + u_ca_or_30: ca_or_lv1 (15) <= not( ca_root_b (30) and ca_root_b (31) ); + u_ca_or_32: ca_or_lv1 (16) <= not( ca_root_b (32) and ca_root_b (33) ); + u_ca_or_34: ca_or_lv1 (17) <= not( ca_root_b (34) and ca_root_b (35) ); + u_ca_or_36: ca_or_lv1 (18) <= not( ca_root_b (36) and ca_root_b (37) ); + u_ca_or_38: ca_or_lv1 (19) <= not( ca_root_b (38) and ca_root_b (39) ); + u_ca_or_40: ca_or_lv1 (20) <= not( ca_root_b (40) and ca_root_b (41) ); + u_ca_or_42: ca_or_lv1 (21) <= not( ca_root_b (42) and ca_root_b (43) ); + u_ca_or_44: ca_or_lv1 (22) <= not( ca_root_b (44) and ca_root_b (45) ); + u_ca_or_46: ca_or_lv1 (23) <= not( ca_root_b (46) and ca_root_b (47) ); + u_ca_or_48: ca_or_lv1 (24) <= not( ca_root_b (48) and ca_root_b (49) ); + u_ca_or_50: ca_or_lv1 (25) <= not( ca_root_b (50) and ca_root_b (51) ); + u_ca_or_52: ca_or_lv1 (26) <= not( ca_root_b (52) and ca_root_b (53) ); + u_ca_or_54: ca_or_lv1 (27) <= not( ca_root_b (54) and ca_root_b (55) ); + u_ca_or_56: ca_or_lv1 (28) <= not( ca_root_b (56) and ca_root_b (57) ); + u_ca_or_58: ca_or_lv1 (29) <= not( ca_root_b (58) and ca_root_b (59) ); + u_ca_or_60: ca_or_lv1 (30) <= not( ca_root_b (60) and ca_root_b (61) ); + u_ca_or_62: ca_or_lv1 (31) <= not( ca_root_b (62) and ca_root_b (63) ); + + u_ca_or_01: ca_or_lv2_b( 0) <= not( ca_or_lv1 ( 0) or ca_or_lv1 ( 1) ); + u_ca_or_05: ca_or_lv2_b( 1) <= not( ca_or_lv1 ( 2) or ca_or_lv1 ( 3) ); + u_ca_or_09: ca_or_lv2_b( 2) <= not( ca_or_lv1 ( 4) or ca_or_lv1 ( 5) ); + u_ca_or_13: ca_or_lv2_b( 3) <= not( ca_or_lv1 ( 6) or ca_or_lv1 ( 7) ); + u_ca_or_17: ca_or_lv2_b( 4) <= not( ca_or_lv1 ( 8) or ca_or_lv1 ( 9) ); + u_ca_or_21: ca_or_lv2_b( 5) <= not( ca_or_lv1 (10) or ca_or_lv1 (11) ); + u_ca_or_25: ca_or_lv2_b( 6) <= not( ca_or_lv1 (12) or ca_or_lv1 (13) ); + u_ca_or_29: ca_or_lv2_b( 7) <= not( ca_or_lv1 (14) or ca_or_lv1 (15) ); + u_ca_or_33: ca_or_lv2_b( 8) <= not( ca_or_lv1 (16) or ca_or_lv1 (17) ); + u_ca_or_37: ca_or_lv2_b( 9) <= not( ca_or_lv1 (18) or ca_or_lv1 (19) ); + u_ca_or_41: ca_or_lv2_b(10) <= not( ca_or_lv1 (20) or ca_or_lv1 (21) ); + u_ca_or_45: ca_or_lv2_b(11) <= not( ca_or_lv1 (22) or ca_or_lv1 (23) ); + u_ca_or_49: ca_or_lv2_b(12) <= not( ca_or_lv1 (24) or ca_or_lv1 (25) ); + u_ca_or_53: ca_or_lv2_b(13) <= not( ca_or_lv1 (26) or ca_or_lv1 (27) ); + u_ca_or_57: ca_or_lv2_b(14) <= not( ca_or_lv1 (28) or ca_or_lv1 (29) ); + u_ca_or_61: ca_or_lv2_b(15) <= not( ca_or_lv1 (30) or ca_or_lv1 (31) ); + + u_ca_or_03: ca_or_lv3 ( 0) <= not( ca_or_lv2_b( 0) and ca_or_lv2_b( 1) ); + u_ca_or_11: ca_or_lv3 ( 1) <= not( ca_or_lv2_b( 2) and ca_or_lv2_b( 3) ); + u_ca_or_19: ca_or_lv3 ( 2) <= not( ca_or_lv2_b( 4) and ca_or_lv2_b( 5) ); + u_ca_or_27: ca_or_lv3 ( 3) <= not( ca_or_lv2_b( 6) and ca_or_lv2_b( 7) ); + u_ca_or_35: ca_or_lv3 ( 4) <= not( ca_or_lv2_b( 8) and ca_or_lv2_b( 9) ); + u_ca_or_43: ca_or_lv3 ( 5) <= not( ca_or_lv2_b(10) and ca_or_lv2_b(11) ); + u_ca_or_51: ca_or_lv3 ( 6) <= not( ca_or_lv2_b(12) and ca_or_lv2_b(13) ); + u_ca_or_59: ca_or_lv3 ( 7) <= not( ca_or_lv2_b(14) and ca_or_lv2_b(15) ); + + u_ca_or_07: ca_or_lv4_b( 0) <= not( ca_or_lv3 ( 0) or ca_or_lv3 ( 1) ); + u_ca_or_23: ca_or_lv4_b( 1) <= not( ca_or_lv3 ( 2) or ca_or_lv3 ( 3) ); + u_ca_or_39: ca_or_lv4_b( 2) <= not( ca_or_lv3 ( 4) or ca_or_lv3 ( 5) ); + u_ca_or_55: ca_or_lv4_b( 3) <= not( ca_or_lv3 ( 6) or ca_or_lv3 ( 7) ); + + u_ca_or_15: ca_or_lv5 ( 0) <= not( ca_or_lv4_b( 0) and ca_or_lv4_b( 1) ); + u_ca_or_47: ca_or_lv5 ( 1) <= not( ca_or_lv4_b( 2) and ca_or_lv4_b( 3) ); + + ca_or_hi <= ca_or_lv5(0); + ca_or_lo <= ca_or_lv5(1); + + + + +end architecture xuq_alu_caor; + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_alu_div.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_alu_div.vhdl new file mode 100644 index 0000000..b291e94 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_alu_div.vhdl @@ -0,0 +1,1046 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee,ibm,support,tri,work; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ibm.std_ulogic_function_support.all; +use support.power_logic_pkg.all; +use tri.tri_latches_pkg.all; +use work.xuq_pkg.all; + +entity xuq_alu_div is + generic( + expand_type : integer := 2; + regsize : integer := 64); + port( + nclk : in clk_logic; + + vdd : inout power_logic; + gnd : inout power_logic; + + d_mode_dc : in std_ulogic; + delay_lclkr_dc : in std_ulogic; + mpw1_dc_b : in std_ulogic; + mpw2_dc_b : in std_ulogic; + func_sl_force : in std_ulogic; + func_sl_thold_0_b : in std_ulogic; + sg_0 : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + fxa_fxb_rf1_div_ctr : in std_ulogic_vector(0 to 7); + dec_alu_rf1_div_val : in std_ulogic; + dec_alu_rf1_div_sign : in std_ulogic; + dec_alu_rf1_div_size : in std_ulogic; + dec_alu_rf1_div_extd : in std_ulogic; + dec_alu_rf1_div_recform : in std_ulogic; + dec_alu_rf1_xer_ov_update : in std_ulogic; + + byp_alu_ex1_divsrc_0 : in std_ulogic_vector(64-regsize to 63); + byp_alu_ex1_divsrc_1 : in std_ulogic_vector(64-regsize to 63); + + fxa_fxb_ex1_hold_ctr_flush : in std_ulogic; + + alu_dec_div_need_hole : out std_ulogic; + alu_byp_ex3_div_rt : out std_ulogic_vector(64-regsize to 63); + alu_ex2_div_done : out std_ulogic; + + ex3_div_xer_ov : out std_ulogic; + ex3_div_xer_ov_update : out std_ulogic; + + alu_byp_ex3_cr_div : out std_ulogic_vector(0 to 4); + + ex2_spr_msr_cm : in std_ulogic + ); +-- synopsys translate_off + +-- synopsys translate_on +end xuq_alu_div; + +architecture xuq_alu_div of xuq_alu_div is + constant msb : integer := 64-regsize; + subtype s2 is std_ulogic_vector(0 to 1); + signal ex1_div_ctr_q : std_ulogic_vector(0 to 7); + signal ex1_div_val_q : std_ulogic; + signal ex1_div_sign_q : std_ulogic; + signal ex1_div_size_q : std_ulogic; + signal ex1_div_extd_q : std_ulogic; + signal ex1_div_recform_q : std_ulogic; + signal ex1_xer_ov_update_q : std_ulogic; + signal ex2_div_val_q : std_ulogic; + signal ex1_cycle_act, ex2_cycle_act_q : std_ulogic; + signal ex2_cycles_d, ex2_cycles_q : std_ulogic_vector(0 to 7); + signal ex2_denom_d, ex2_denom_q : std_ulogic_vector(msb to 63); + signal ex2_numer_d, ex2_numer_q : std_ulogic_vector(msb to 64); + signal ex2_dmask_d, ex2_dmask_q : std_ulogic_vector(msb to 63); + signal ex2_div_ovf_q : std_ulogic; + signal ex2_xer_ov_update_q : std_ulogic; + signal ex2_div_recform_q : std_ulogic; + signal ex2_div_size_q : std_ulogic; + signal ex2_div_sign_q : std_ulogic; + signal ex2_div_extd_q : std_ulogic; + signal ex2_2s_rslt_q : std_ulogic; + signal ex2_div_done_q : std_ulogic; + signal ex3_div_val_q : std_ulogic; + signal ex3_cycle_watch_d, ex3_cycle_watch_q : std_ulogic; + signal ex3_quot_watch_d, ex3_quot_watch_q : std_ulogic; + signal ex3_div_ovf_d, ex3_div_ovf_q : std_ulogic; + signal ex3_xer_ov_update_q : std_ulogic; + signal ex3_div_done_q : std_ulogic; + signal ex3_quotient_d, ex3_quotient_q : std_ulogic_vector(msb to 63); + signal ex3_div_recform_q : std_ulogic; + signal ex3_div_size_q : std_ulogic; + signal ex3_2s_rslt_q : std_ulogic; + signal ex3_div_rt_d, ex3_div_rt_q : std_ulogic_vector(msb to 63); + signal ex2_numer_eq_zero_q, ex2_numer_eq_zero_d : std_ulogic; + signal ex2_div_ovf_cond3, ex3_div_ovf_cond3_q : std_ulogic; + signal ex3_spr_msr_cm_q : std_ulogic; + signal need_hole_q, need_hole_d : std_ulogic; + constant ex1_div_ctr_offset : integer := 0; + constant ex1_div_val_offset : integer := ex1_div_ctr_offset + ex1_div_ctr_q'length; + constant ex1_div_sign_offset : integer := ex1_div_val_offset + 1; + constant ex1_div_size_offset : integer := ex1_div_sign_offset + 1; + constant ex1_div_extd_offset : integer := ex1_div_size_offset + 1; + constant ex1_div_recform_offset : integer := ex1_div_extd_offset + 1; + constant ex1_xer_ov_update_offset : integer := ex1_div_recform_offset + 1; + constant ex2_div_val_offset : integer := ex1_xer_ov_update_offset + 1; + constant ex2_cycle_act_offset : integer := ex2_div_val_offset + 1; + constant ex2_cycles_offset : integer := ex2_cycle_act_offset + 1; + constant ex2_denom_offset : integer := ex2_cycles_offset + ex2_cycles_q'length; + constant ex2_numer_offset : integer := ex2_denom_offset + ex2_denom_q'length; + constant ex2_dmask_offset : integer := ex2_numer_offset + ex2_numer_q'length; + constant ex2_div_ovf_offset : integer := ex2_dmask_offset + ex2_dmask_q'length; + constant ex2_xer_ov_update_offset : integer := ex2_div_ovf_offset + 1; + constant ex2_div_recform_offset : integer := ex2_xer_ov_update_offset + 1; + constant ex2_div_size_offset : integer := ex2_div_recform_offset + 1; + constant ex2_div_sign_offset : integer := ex2_div_size_offset + 1; + constant ex2_div_extd_offset : integer := ex2_div_sign_offset + 1; + constant ex2_2s_rslt_offset : integer := ex2_div_extd_offset + 1; + constant ex2_div_done_offset : integer := ex2_2s_rslt_offset + 1; + constant ex3_div_val_offset : integer := ex2_div_done_offset + 1; + constant ex3_cycle_watch_offset : integer := ex3_div_val_offset + 1; + constant ex3_quot_watch_offset : integer := ex3_cycle_watch_offset + 1; + constant ex3_div_ovf_offset : integer := ex3_quot_watch_offset + 1; + constant ex3_xer_ov_update_offset : integer := ex3_div_ovf_offset + 1; + constant ex3_div_done_offset : integer := ex3_xer_ov_update_offset + 1; + constant ex3_quotient_offset : integer := ex3_div_done_offset + 1; + constant ex3_div_recform_offset : integer := ex3_quotient_offset + ex3_quotient_q'length; + constant ex3_div_size_offset : integer := ex3_div_recform_offset + 1; + constant ex3_2s_rslt_offset : integer := ex3_div_size_offset + 1; + constant ex3_div_rt_offset : integer := ex3_2s_rslt_offset + 1; + constant ex2_numer_eq_zero_offset : integer := ex3_div_rt_offset + ex3_div_rt_q'length; + constant ex3_div_ovf_cond3_offset : integer := ex2_numer_eq_zero_offset + 1; + constant ex3_spr_msr_cm_offset : integer := ex3_div_ovf_cond3_offset + 1; + constant need_hole_offset : integer := ex3_spr_msr_cm_offset + 1; + constant scan_right : integer := need_hole_offset + 1; + signal sov,siv : std_ulogic_vector(0 to scan_right-1); + signal ex2_denom_shift : std_ulogic_vector(msb to 63); + signal ex2_denom_shift_ctrl : std_ulogic; + signal ex2_sub_or_restore : std_ulogic_vector(msb to 64); + signal ex2_sub_or_restore_ctrl : std_ulogic_vector(0 to 1); + signal ex2_sub_rslt_shift : std_ulogic_vector(msb to 64); + signal ex2_numer_shift : std_ulogic_vector(msb to 64); + signal ex1_denom : std_ulogic_vector(msb to 63); + signal ex1_numer : std_ulogic_vector(msb to 63); + signal mask : std_ulogic_vector(msb to 63); + signal ex2_sub_rslt : std_ulogic_vector(msb to 64); + signal ex1_div_done : std_ulogic; + signal ex1_num_cmp0_lo_nomsb, ex1_num_cmp0_hi_nomsb : std_ulogic; + signal ex1_num_cmp0_lo, ex1_num_cmp0_hi : std_ulogic; + signal ex1_den_cmp0_lo, ex1_den_cmp0_hi : std_ulogic; + signal ex1_den_cmp1_lo, ex1_den_cmp1_hi : std_ulogic; + signal ex3_qot_cmp0_lo, ex3_qot_cmp0_hi : std_ulogic; + signal ex1_div_ovf_cond1_wd, ex1_div_ovf_cond1_dw : std_ulogic; + signal ex1_div_ovf_cond1 : std_ulogic; + signal ex1_div_ovf_cond2 : std_ulogic; + signal ex2_div_ovf_cond4 : std_ulogic; + signal ex2_rslt_sign : std_ulogic; + signal ex2_den_eq_num, ex2_den_gte_num : std_ulogic; + signal ex1_div_ovf : std_ulogic; + signal ex1_divsrc_0, ex1_divsrc_0_2s : std_ulogic_vector(msb to 63); + signal ex1_divsrc_1, ex1_divsrc_1_2s : std_ulogic_vector(msb to 63); + signal ex1_2s_rslt : std_ulogic; + signal ex1_src0_sign, ex1_src1_sign : std_ulogic; + signal ex1_div_cnt_done : std_ulogic; + signal ex3_cmp0_undef : std_ulogic; + signal ex3_cmp0_eq : std_ulogic; + signal ex3_cmp0_gt : std_ulogic; + signal ex3_cmp0_lt : std_ulogic; + signal ex3_quotient_2s : std_ulogic_vector(msb to 63); + signal ex2_cycles_din : std_ulogic_vector(0 to 7); + signal ex2_cycles_gt_64, ex2_cycles_gt_32 : std_ulogic; + signal ex3_lt : std_ulogic; + signal ex2_quot_pushbit : std_ulogic; + signal ex2_denom_rot : std_ulogic_vector(msb to 63); + signal ex3_div_rt : std_ulogic_vector(msb to 63); + signal ex2_numer_act, ex2_denom_act : std_ulogic; + signal tiup, tidn : std_ulogic; + +begin + + +tiup <= '1'; +tidn <= '0'; + +with ex1_div_val_q select + ex2_cycles_din <= ex1_div_ctr_q when '1', + std_ulogic_vector(unsigned(ex2_cycles_q) - 1) when others; + +ex2_cycles_d <= gate(ex2_cycles_din,not(fxa_fxb_ex1_hold_ctr_flush)); + +ex1_cycle_act <= ex1_div_val_q or (ex2_cycle_act_q and or_reduce(ex2_cycles_q)); + +ex1_div_cnt_done <= '1' when ex2_cycles_q = "00000001" else '0'; + +ex1_div_done <= ex1_div_cnt_done and not fxa_fxb_ex1_hold_ctr_flush; + +alu_ex2_div_done <= ex2_div_done_q; + +ex1_divsrc_0_2s <= std_ulogic_vector(unsigned(not byp_alu_ex1_divsrc_0) + 1); +ex1_divsrc_1_2s <= std_ulogic_vector(unsigned(not byp_alu_ex1_divsrc_1) + 1); + +div_64b_2scomp : if regsize = 64 generate + with ex1_div_size_q select + ex1_2s_rslt <= (byp_alu_ex1_divsrc_0(0) xor byp_alu_ex1_divsrc_1(0) ) and ex1_div_sign_q when '1', + (byp_alu_ex1_divsrc_0(32) xor byp_alu_ex1_divsrc_1(32)) and ex1_div_sign_q when others; + + with ex1_div_size_q select + ex1_src0_sign <= byp_alu_ex1_divsrc_0(0) when '1', + byp_alu_ex1_divsrc_0(32) when others; + + with ex1_div_size_q select + ex1_src1_sign <= byp_alu_ex1_divsrc_1(0) when '1', + byp_alu_ex1_divsrc_1(32) when others; +end generate; +div_32b_2scomp : if regsize = 32 generate + ex1_2s_rslt <= (byp_alu_ex1_divsrc_0(32) xor byp_alu_ex1_divsrc_1(32)) and ex1_div_sign_q; + ex1_src0_sign <= byp_alu_ex1_divsrc_0(32); + ex1_src1_sign <= byp_alu_ex1_divsrc_1(32); +end generate; + + +with (ex1_div_sign_q and ex1_src0_sign) select + ex1_divsrc_0 <= ex1_divsrc_0_2s when '1', + byp_alu_ex1_divsrc_0 when others; + +with (ex1_div_sign_q and ex1_src1_sign) select + ex1_divsrc_1 <= ex1_divsrc_1_2s when '1', + byp_alu_ex1_divsrc_1 when others; + + +div_setup_64b : if regsize = 64 generate + + with ex1_div_size_q select + ex1_denom(0 to 31) <= ex1_divsrc_1(0 to 31) when '1', + ex1_divsrc_1(32 to 63) when others; + + ex1_denom(32 to 63) <= gate(ex1_divsrc_1(32 to 63),ex1_div_size_q); + + + with ex1_div_size_q select + ex1_numer(0 to 31) <= ex1_divsrc_0(0 to 31) when '1', + ex1_divsrc_0(32 to 63) when others; + + ex1_numer(32 to 63) <= gate(ex1_divsrc_0(32 to 63),ex1_div_size_q); + + + mask <= (0 to 31=>tiup) & (32 to 63=>ex1_div_size_q); + + + with ex1_div_size_q select + ex2_denom_rot(0) <= ex2_denom_q(63) when '1', + ex2_denom_q(31) when others; + + ex2_denom_rot(1 to 31) <= ex2_denom_q(msb to 30); + ex2_denom_rot(32 to 63) <= gate(ex2_denom_q(31 to 62),ex2_div_size_q); + +end generate; +div_setup_32b : if regsize = 32 generate + + ex1_denom <= ex1_divsrc_1; + ex1_numer <= ex1_divsrc_0; + + mask <= (32 to 63=>tiup); + + ex2_denom_rot <= ex2_denom_q(63) & ex2_denom_q(msb to 62); + +end generate; + +with ex1_div_val_q select + ex2_denom_d <= ex1_denom when '1', + ex2_denom_shift when others; + +with ex1_div_val_q select + ex2_dmask_d <= mask when '1', + '0' & ex2_dmask_q(msb to 62) when others; + +ex2_denom_shift_ctrl <= or_reduce(ex2_denom_q and ex2_dmask_q); + + +with ex2_denom_shift_ctrl select + ex2_denom_shift <= ex2_denom_rot when '1', + ex2_denom_q when others; + +ex2_denom_act <= ex1_div_val_q or ex2_denom_shift_ctrl; + +with ex1_div_val_q select + ex2_numer_d <= '0' & ex1_numer when '1', + ex2_sub_or_restore when others; + + +ex2_numer_act <= ex1_div_val_q or ex1_cycle_act; + +ex2_sub_rslt <= std_ulogic_vector(unsigned(ex2_numer_q) - unsigned('0' & ex2_denom_q)); + + + +ex2_sub_rslt_shift <= ex2_sub_rslt(msb+1 to 64) & '0'; +ex2_numer_shift <= ex2_numer_q(msb+1 to 64) & ex2_numer_q(msb); + + +ex2_sub_or_restore_ctrl <= (not ex2_denom_shift_ctrl) & ex2_sub_rslt(msb); + +with ex2_sub_or_restore_ctrl select + ex2_sub_or_restore <= ex2_sub_rslt_shift when "10", + ex2_numer_shift when "11", + ex2_numer_q when others; + +ex2_quot_pushbit <= not ex2_denom_shift_ctrl and not ex2_sub_rslt(msb); + +with ex2_div_val_q select + ex3_quotient_d <= (msb to 63=>tidn) when '1', + ex3_quotient_q(msb+1 to 63) & ex2_quot_pushbit when others; + +ex3_quotient_2s <= std_ulogic_vector(unsigned(not ex3_quotient_q) + 1); + +need_hole_d <= '1' when ex2_cycles_q = "00000111" else '0'; +alu_dec_div_need_hole <= need_hole_q; + +with ex3_2s_rslt_q select + ex3_div_rt_d <= ex3_quotient_2s when '1', + ex3_quotient_q when others; + +with ex2_div_size_q select + ex2_rslt_sign <= ex3_div_rt_d(msb) when '1', + ex3_div_rt_d(32) when others; + +div_rslt_64b : if regsize = 64 generate + ex3_div_rt(0 to 31) <= gate(ex3_div_rt_q(0 to 31),not(ex3_div_ovf_q or not ex3_div_size_q)); +end generate; + ex3_div_rt(32 to 63) <= gate(ex3_div_rt_q(32 to 63),not(ex3_div_ovf_q)); + +alu_byp_ex3_div_rt <= ex3_div_rt; + + + + ex1_num_cmp0_lo_nomsb <= not or_reduce(byp_alu_ex1_divsrc_0(33 to 63)); + ex1_den_cmp0_lo <= not or_reduce(byp_alu_ex1_divsrc_1(32 to 63)); + ex1_den_cmp1_lo <= and_reduce(byp_alu_ex1_divsrc_1(32 to 63)); + ex3_qot_cmp0_lo <= not or_reduce(ex3_div_rt_q(32 to 63)); + ex1_num_cmp0_lo <= not byp_alu_ex1_divsrc_0(32) and ex1_num_cmp0_lo_nomsb; + ex1_div_ovf_cond1_wd <= byp_alu_ex1_divsrc_0(32) and ex1_num_cmp0_lo_nomsb and ex1_den_cmp1_lo; + +div_64b_oflow : if regsize = 64 generate + + ex1_num_cmp0_hi_nomsb <= not or_reduce(byp_alu_ex1_divsrc_0(1 to 31)); + ex1_den_cmp0_hi <= not or_reduce(byp_alu_ex1_divsrc_1(0 to 31)); + ex1_den_cmp1_hi <= and_reduce(byp_alu_ex1_divsrc_1(0 to 31)); + ex3_qot_cmp0_hi <= not or_reduce(ex3_div_rt_q(0 to 31)); + ex1_num_cmp0_hi <= not byp_alu_ex1_divsrc_0(0) and ex1_num_cmp0_hi_nomsb; + ex1_div_ovf_cond1_dw <= byp_alu_ex1_divsrc_0(0) and ex1_num_cmp0_hi_nomsb and + not byp_alu_ex1_divsrc_0(32) and ex1_num_cmp0_lo_nomsb and ex1_den_cmp1_lo and ex1_den_cmp1_hi; + +end generate; +div_32b_oflow : if regsize = 32 generate + + ex1_num_cmp0_hi_nomsb <= '1'; + ex1_den_cmp0_hi <= '1'; + ex1_den_cmp1_hi <= '1'; + ex1_div_ovf_cond1_dw <= '1'; + ex1_num_cmp0_hi <= '1'; + ex3_qot_cmp0_hi <= '1'; + +end generate; + + +with ex1_div_size_q select + ex1_div_ovf_cond1 <= ex1_div_ovf_cond1_dw when '1', + ex1_div_ovf_cond1_wd when others; + +ex1_div_ovf_cond2 <= ex1_den_cmp0_lo and (ex1_den_cmp0_hi or not ex1_div_size_q); + +ex1_div_ovf <= (ex1_div_ovf_cond1 and ex1_div_sign_q) or + ex1_div_ovf_cond2; + +ex2_den_eq_num <= and_reduce(ex2_denom_q xnor ex2_numer_q(msb+1 to 64)); +ex2_den_gte_num <= not(ex2_sub_rslt(msb)) or ex2_den_eq_num; +ex2_div_ovf_cond3 <= ex2_den_gte_num and not ex2_div_sign_q and ex2_div_extd_q; + +ex2_cycles_gt_64 <= '1' when (unsigned(ex2_cycles_q) > 64) else '0'; +ex2_cycles_gt_32 <= '1' when (unsigned(ex2_cycles_q) > 32) else '0'; + +with ex2_div_size_q select + ex3_cycle_watch_d <= ex2_cycles_gt_64 when '1', + ex2_cycles_gt_32 when others; + +ex3_quot_watch_d <= (ex3_quot_watch_q or (ex3_cycle_watch_q and ex3_quotient_q(63))) and not ex3_div_val_q; + +ex2_numer_eq_zero_d <= ex1_num_cmp0_lo and (ex1_num_cmp0_hi or not ex1_div_size_q); + +ex2_div_ovf_cond4 <= ex3_quot_watch_q or + ((ex2_rslt_sign xor ex2_2s_rslt_q) and not ex2_numer_eq_zero_q) or + ( ex2_rslt_sign and ex2_numer_eq_zero_q); + +ex3_div_ovf_d <= ex2_div_ovf_q or ex3_div_ovf_cond3_q or (ex2_div_ovf_cond4 and (ex2_div_sign_q and ex2_div_extd_q)); + +ex3_div_xer_ov_update <= ex3_xer_ov_update_q and ex3_div_done_q; +ex3_div_xer_ov <= ex3_div_ovf_q; + +ex3_cmp0_undef <= ex3_div_ovf_q or + (not ex3_div_size_q and ex3_spr_msr_cm_q); + +with ex3_spr_msr_cm_q select + ex3_lt <= ex3_div_rt_q(msb) when '1', + ex3_div_rt_q(32) when others; + +ex3_cmp0_eq <= (ex3_qot_cmp0_lo and + (ex3_qot_cmp0_hi or not ex3_spr_msr_cm_q)) and not ex3_cmp0_undef; + +ex3_cmp0_lt <= ex3_lt and not ex3_cmp0_eq and not ex3_cmp0_undef; +ex3_cmp0_gt <= not ex3_lt and not ex3_cmp0_eq and not ex3_cmp0_undef; + +alu_byp_ex3_cr_div <= ex3_cmp0_lt & ex3_cmp0_gt & ex3_cmp0_eq & (ex3_div_ovf_q and ex3_xer_ov_update_q) & (ex3_div_recform_q and ex3_div_done_q); + + ex1_div_ctr_latch : tri_rlmreg_p + generic map (width => ex1_div_ctr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => dec_alu_rf1_div_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_div_ctr_offset to ex1_div_ctr_offset + ex1_div_ctr_q'length-1), + scout => sov(ex1_div_ctr_offset to ex1_div_ctr_offset + ex1_div_ctr_q'length-1), + din => fxa_fxb_rf1_div_ctr, + dout => ex1_div_ctr_q); + ex1_div_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_div_val_offset), + scout => sov(ex1_div_val_offset), + din => dec_alu_rf1_div_val, + dout => ex1_div_val_q); + ex1_div_sign_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => dec_alu_rf1_div_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_div_sign_offset), + scout => sov(ex1_div_sign_offset), + din => dec_alu_rf1_div_sign, + dout => ex1_div_sign_q); + ex1_div_size_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => dec_alu_rf1_div_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_div_size_offset), + scout => sov(ex1_div_size_offset), + din => dec_alu_rf1_div_size, + dout => ex1_div_size_q); + ex1_div_extd_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => dec_alu_rf1_div_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_div_extd_offset), + scout => sov(ex1_div_extd_offset), + din => dec_alu_rf1_div_extd, + dout => ex1_div_extd_q); + ex1_div_recform_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => dec_alu_rf1_div_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_div_recform_offset), + scout => sov(ex1_div_recform_offset), + din => dec_alu_rf1_div_recform, + dout => ex1_div_recform_q); + ex1_xer_ov_update_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => dec_alu_rf1_div_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_xer_ov_update_offset), + scout => sov(ex1_xer_ov_update_offset), + din => dec_alu_rf1_xer_ov_update, + dout => ex1_xer_ov_update_q); + ex2_div_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_div_val_offset), + scout => sov(ex2_div_val_offset), + din => ex1_div_val_q, + dout => ex2_div_val_q); + ex2_cycle_act_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_cycle_act_offset), + scout => sov(ex2_cycle_act_offset), + din => ex1_cycle_act, + dout => ex2_cycle_act_q); + ex2_cycles_latch : tri_rlmreg_p + generic map (width => ex2_cycles_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => ex1_cycle_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_cycles_offset to ex2_cycles_offset + ex2_cycles_q'length-1), + scout => sov(ex2_cycles_offset to ex2_cycles_offset + ex2_cycles_q'length-1), + din => ex2_cycles_d, + dout => ex2_cycles_q); + ex2_denom_latch : tri_rlmreg_p + generic map (width => ex2_denom_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => ex2_denom_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_denom_offset to ex2_denom_offset + ex2_denom_q'length-1), + scout => sov(ex2_denom_offset to ex2_denom_offset + ex2_denom_q'length-1), + din => ex2_denom_d, + dout => ex2_denom_q); + ex2_numer_latch : tri_rlmreg_p + generic map (width => ex2_numer_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => ex2_numer_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_numer_offset to ex2_numer_offset + ex2_numer_q'length-1), + scout => sov(ex2_numer_offset to ex2_numer_offset + ex2_numer_q'length-1), + din => ex2_numer_d, + dout => ex2_numer_q); + ex2_dmask_latch : tri_rlmreg_p + generic map (width => ex2_dmask_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => ex2_denom_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_dmask_offset to ex2_dmask_offset + ex2_dmask_q'length-1), + scout => sov(ex2_dmask_offset to ex2_dmask_offset + ex2_dmask_q'length-1), + din => ex2_dmask_d, + dout => ex2_dmask_q); + ex2_div_ovf_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => ex1_div_val_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_div_ovf_offset), + scout => sov(ex2_div_ovf_offset), + din => ex1_div_ovf, + dout => ex2_div_ovf_q); + ex2_xer_ov_update_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_xer_ov_update_offset), + scout => sov(ex2_xer_ov_update_offset), + din => ex1_xer_ov_update_q, + dout => ex2_xer_ov_update_q); + ex2_div_recform_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_div_recform_offset), + scout => sov(ex2_div_recform_offset), + din => ex1_div_recform_q, + dout => ex2_div_recform_q); + ex2_div_size_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => ex1_div_val_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_div_size_offset), + scout => sov(ex2_div_size_offset), + din => ex1_div_size_q, + dout => ex2_div_size_q); + ex2_div_sign_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => ex1_div_val_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_div_sign_offset), + scout => sov(ex2_div_sign_offset), + din => ex1_div_sign_q, + dout => ex2_div_sign_q); + ex2_div_extd_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => ex1_div_val_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_div_extd_offset), + scout => sov(ex2_div_extd_offset), + din => ex1_div_extd_q, + dout => ex2_div_extd_q); + ex2_2s_rslt_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => ex1_div_val_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_2s_rslt_offset), + scout => sov(ex2_2s_rslt_offset), + din => ex1_2s_rslt, + dout => ex2_2s_rslt_q); + ex2_div_done_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_div_done_offset), + scout => sov(ex2_div_done_offset), + din => ex1_div_done, + dout => ex2_div_done_q); + ex3_div_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_div_val_offset), + scout => sov(ex3_div_val_offset), + din => ex2_div_val_q, + dout => ex3_div_val_q); + ex3_cycle_watch_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_cycle_watch_offset), + scout => sov(ex3_cycle_watch_offset), + din => ex3_cycle_watch_d, + dout => ex3_cycle_watch_q); + ex3_quot_watch_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_quot_watch_offset), + scout => sov(ex3_quot_watch_offset), + din => ex3_quot_watch_d, + dout => ex3_quot_watch_q); + ex3_div_ovf_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_div_ovf_offset), + scout => sov(ex3_div_ovf_offset), + din => ex3_div_ovf_d, + dout => ex3_div_ovf_q); + ex3_xer_ov_update_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_xer_ov_update_offset), + scout => sov(ex3_xer_ov_update_offset), + din => ex2_xer_ov_update_q, + dout => ex3_xer_ov_update_q); + ex3_div_done_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_div_done_offset), + scout => sov(ex3_div_done_offset), + din => ex2_div_done_q, + dout => ex3_div_done_q); + ex3_quotient_latch : tri_rlmreg_p + generic map (width => ex3_quotient_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => ex2_cycle_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_quotient_offset to ex3_quotient_offset + ex3_quotient_q'length-1), + scout => sov(ex3_quotient_offset to ex3_quotient_offset + ex3_quotient_q'length-1), + din => ex3_quotient_d, + dout => ex3_quotient_q); + ex3_div_recform_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_div_recform_offset), + scout => sov(ex3_div_recform_offset), + din => ex2_div_recform_q, + dout => ex3_div_recform_q); + ex3_div_size_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_div_size_offset), + scout => sov(ex3_div_size_offset), + din => ex2_div_size_q, + dout => ex3_div_size_q); + ex3_2s_rslt_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_2s_rslt_offset), + scout => sov(ex3_2s_rslt_offset), + din => ex2_2s_rslt_q, + dout => ex3_2s_rslt_q); + ex3_div_rt_latch : tri_rlmreg_p + generic map (width => ex3_div_rt_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => ex2_div_done_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_div_rt_offset to ex3_div_rt_offset + ex3_div_rt_q'length-1), + scout => sov(ex3_div_rt_offset to ex3_div_rt_offset + ex3_div_rt_q'length-1), + din => ex3_div_rt_d, + dout => ex3_div_rt_q); + ex3_div_ovf_cond3_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_div_val_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_div_ovf_cond3_offset), + scout => sov(ex3_div_ovf_cond3_offset), + din => ex2_div_ovf_cond3, + dout => ex3_div_ovf_cond3_q); + ex3_spr_msr_cm_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_spr_msr_cm_offset), + scout => sov(ex3_spr_msr_cm_offset), + din => ex2_spr_msr_cm, + dout => ex3_spr_msr_cm_q); + ex2_numer_eq_zero_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => ex1_div_val_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_numer_eq_zero_offset), + scout => sov(ex2_numer_eq_zero_offset), + din => ex2_numer_eq_zero_d, + dout => ex2_numer_eq_zero_q); + need_hole_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(need_hole_offset), + scout => sov(need_hole_offset), + din => need_hole_d, + dout => need_hole_q); + siv(0 to siv'right) <= sov(1 to siv'right) & scan_in; + scan_out <= sov(0); +end architecture xuq_alu_div; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_alu_ins.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_alu_ins.vhdl new file mode 100644 index 0000000..149c1c8 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_alu_ins.vhdl @@ -0,0 +1,231 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +LIBRARY ieee; USE ieee.std_logic_1164.all; + use ieee.numeric_std.all; +LIBRARY ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; +LIBRARY support; + use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity xuq_alu_ins is generic(expand_type: integer := 2 ); port ( + + ins_log_fcn :in std_ulogic_vector(0 to 3) ; + + ins_cmp_byt :in std_ulogic ; + ins_sra_wd :in std_ulogic ; + ins_sra_dw :in std_ulogic ; + + ins_xtd_byte :in std_ulogic ; + ins_xtd_half :in std_ulogic ; + ins_xtd_wd :in std_ulogic ; + + + data0_i :in std_ulogic_vector(0 to 63) ; + data1_i :in std_ulogic_vector(0 to 63) ; + mrg_byp_log :out std_ulogic_vector(0 to 63) ; + res_ins :out std_ulogic_vector(0 to 63) +); + +-- synopsys translate_off +-- synopsys translate_on +end xuq_alu_ins; + +architecture xuq_alu_ins of xuq_alu_ins is + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal mrg_byp_log_b :std_ulogic_vector(0 to 63); + + signal res_log :std_ulogic_vector(0 to 63); + signal byt_cmp, byt_cmp_b :std_ulogic_vector(0 to 7); + signal byt_cmp_bus, sign_xtd_bus :std_ulogic_vector(0 to 63); + signal xtd_byte_bus, xtd_half_bus, xtd_wd_bus, sra_dw_bus, sra_wd_bus :std_ulogic_vector(0 to 63); + signal res_ins0_b, res_ins1_b, res_ins2_b :std_ulogic_vector(0 to 63); + signal res_log0_b, res_log1_b, res_log2_b, res_log3_b :std_ulogic_vector(0 to 63); + signal res_log_o0, res_log_o1, res_log_b :std_ulogic_vector(0 to 63); + signal byt0_cmp2_b :std_ulogic_vector(0 to 3) ; + signal byt1_cmp2_b :std_ulogic_vector(0 to 3) ; + signal byt2_cmp2_b :std_ulogic_vector(0 to 3) ; + signal byt3_cmp2_b :std_ulogic_vector(0 to 3) ; + signal byt4_cmp2_b :std_ulogic_vector(0 to 3) ; + signal byt5_cmp2_b :std_ulogic_vector(0 to 3) ; + signal byt6_cmp2_b :std_ulogic_vector(0 to 3) ; + signal byt7_cmp2_b :std_ulogic_vector(0 to 3) ; + + signal byt0_cmp4 :std_ulogic_vector(0 to 1) ; + signal byt1_cmp4 :std_ulogic_vector(0 to 1) ; + signal byt2_cmp4 :std_ulogic_vector(0 to 1) ; + signal byt3_cmp4 :std_ulogic_vector(0 to 1) ; + signal byt4_cmp4 :std_ulogic_vector(0 to 1) ; + signal byt5_cmp4 :std_ulogic_vector(0 to 1) ; + signal byt6_cmp4 :std_ulogic_vector(0 to 1) ; + signal byt7_cmp4 :std_ulogic_vector(0 to 1) ; + + signal sel_cmp_byt,sel_cmp_byt_b : std_ulogic_vector(0 to 63); + + signal data0_b, data1_b : std_ulogic_vector(0 to 63); + signal data0, data1 : std_ulogic_vector(0 to 63); + + + + + + + +begin + + u_log_s0i: data0_b <= not data0_i; + u_log_s1i: data1_b <= not data1_i; + u_log_s0: data0 <= not data0_b; + u_log_s1: data1 <= not data1_b; + + u_reslog0: res_log0_b(0 to 63) <= not( (0 to 63=> ins_log_fcn(0)) and data0_b(0 to 63) and data1_b(0 to 63) ); + u_reslog1: res_log1_b(0 to 63) <= not( (0 to 63=> ins_log_fcn(1)) and data0_b(0 to 63) and data1(0 to 63) ); + u_reslog2: res_log2_b(0 to 63) <= not( (0 to 63=> ins_log_fcn(2)) and data0(0 to 63) and data1_b(0 to 63) ); + u_reslog3: res_log3_b(0 to 63) <= not( (0 to 63=> ins_log_fcn(3)) and data0(0 to 63) and data1(0 to 63) ); + u_reslog_o0: res_log_o0(0 to 63) <= not( res_log0_b(0 to 63) and res_log1_b(0 to 63) ); + u_reslog_o1: res_log_o1(0 to 63) <= not( res_log2_b(0 to 63) and res_log3_b(0 to 63) ); + u_reslogb: res_log_b (0 to 63) <= not( res_log_o0(0 to 63) or res_log_o1(0 to 63) ); + u_reslog: res_log (0 to 63) <= not( res_log_b(0 to 63) ); + + u_mrg_byp_log_b: mrg_byp_log_b(0 to 63) <= not( res_log (0 to 63) ); + u_mrg_byp_log: mrg_byp_log (0 to 63) <= not( mrg_byp_log_b(0 to 63) ); + + u_byt0cmp2_0: byt0_cmp2_b(0) <= not( res_log(0) and res_log(1) ); + u_byt0cmp2_1: byt0_cmp2_b(1) <= not( res_log(2) and res_log(3) ); + u_byt0cmp2_2: byt0_cmp2_b(2) <= not( res_log(4) and res_log(5) ); + u_byt0cmp2_3: byt0_cmp2_b(3) <= not( res_log(6) and res_log(7) ); + u_byt1cmp2_0: byt1_cmp2_b(0) <= not( res_log(8) and res_log(9) ); + u_byt1cmp2_1: byt1_cmp2_b(1) <= not( res_log(10) and res_log(11) ); + u_byt1cmp2_2: byt1_cmp2_b(2) <= not( res_log(12) and res_log(13) ); + u_byt1cmp2_3: byt1_cmp2_b(3) <= not( res_log(14) and res_log(15) ); + u_byt2cmp2_0: byt2_cmp2_b(0) <= not( res_log(16) and res_log(17) ); + u_byt2cmp2_1: byt2_cmp2_b(1) <= not( res_log(18) and res_log(19) ); + u_byt2cmp2_2: byt2_cmp2_b(2) <= not( res_log(20) and res_log(21) ); + u_byt2cmp2_3: byt2_cmp2_b(3) <= not( res_log(22) and res_log(23) ); + u_byt3cmp2_0: byt3_cmp2_b(0) <= not( res_log(24) and res_log(25) ); + u_byt3cmp2_1: byt3_cmp2_b(1) <= not( res_log(26) and res_log(27) ); + u_byt3cmp2_2: byt3_cmp2_b(2) <= not( res_log(28) and res_log(29) ); + u_byt3cmp2_3: byt3_cmp2_b(3) <= not( res_log(30) and res_log(31) ); + u_byt4cmp2_0: byt4_cmp2_b(0) <= not( res_log(32) and res_log(33) ); + u_byt4cmp2_1: byt4_cmp2_b(1) <= not( res_log(34) and res_log(35) ); + u_byt4cmp2_2: byt4_cmp2_b(2) <= not( res_log(36) and res_log(37) ); + u_byt4cmp2_3: byt4_cmp2_b(3) <= not( res_log(38) and res_log(39) ); + u_byt5cmp2_0: byt5_cmp2_b(0) <= not( res_log(40) and res_log(41) ); + u_byt5cmp2_1: byt5_cmp2_b(1) <= not( res_log(42) and res_log(43) ); + u_byt5cmp2_2: byt5_cmp2_b(2) <= not( res_log(44) and res_log(45) ); + u_byt5cmp2_3: byt5_cmp2_b(3) <= not( res_log(46) and res_log(47) ); + u_byt6cmp2_0: byt6_cmp2_b(0) <= not( res_log(48) and res_log(49) ); + u_byt6cmp2_1: byt6_cmp2_b(1) <= not( res_log(50) and res_log(51) ); + u_byt6cmp2_2: byt6_cmp2_b(2) <= not( res_log(52) and res_log(53) ); + u_byt6cmp2_3: byt6_cmp2_b(3) <= not( res_log(54) and res_log(55) ); + u_byt7cmp2_0: byt7_cmp2_b(0) <= not( res_log(56) and res_log(57) ); + u_byt7cmp2_1: byt7_cmp2_b(1) <= not( res_log(58) and res_log(59) ); + u_byt7cmp2_2: byt7_cmp2_b(2) <= not( res_log(60) and res_log(61) ); + u_byt7cmp2_3: byt7_cmp2_b(3) <= not( res_log(62) and res_log(63) ); + + + u_byt0cmp4_0: byt0_cmp4(0) <= not( byt0_cmp2_b(0) or byt0_cmp2_b(1) ); + u_byt0cmp4_1: byt0_cmp4(1) <= not( byt0_cmp2_b(2) or byt0_cmp2_b(3) ); + u_byt1cmp4_0: byt1_cmp4(0) <= not( byt1_cmp2_b(0) or byt1_cmp2_b(1) ); + u_byt1cmp4_1: byt1_cmp4(1) <= not( byt1_cmp2_b(2) or byt1_cmp2_b(3) ); + u_byt2cmp4_0: byt2_cmp4(0) <= not( byt2_cmp2_b(0) or byt2_cmp2_b(1) ); + u_byt2cmp4_1: byt2_cmp4(1) <= not( byt2_cmp2_b(2) or byt2_cmp2_b(3) ); + u_byt3cmp4_0: byt3_cmp4(0) <= not( byt3_cmp2_b(0) or byt3_cmp2_b(1) ); + u_byt3cmp4_1: byt3_cmp4(1) <= not( byt3_cmp2_b(2) or byt3_cmp2_b(3) ); + u_byt4cmp4_0: byt4_cmp4(0) <= not( byt4_cmp2_b(0) or byt4_cmp2_b(1) ); + u_byt4cmp4_1: byt4_cmp4(1) <= not( byt4_cmp2_b(2) or byt4_cmp2_b(3) ); + u_byt5cmp4_0: byt5_cmp4(0) <= not( byt5_cmp2_b(0) or byt5_cmp2_b(1) ); + u_byt5cmp4_1: byt5_cmp4(1) <= not( byt5_cmp2_b(2) or byt5_cmp2_b(3) ); + u_byt6cmp4_0: byt6_cmp4(0) <= not( byt6_cmp2_b(0) or byt6_cmp2_b(1) ); + u_byt6cmp4_1: byt6_cmp4(1) <= not( byt6_cmp2_b(2) or byt6_cmp2_b(3) ); + u_byt7cmp4_0: byt7_cmp4(0) <= not( byt7_cmp2_b(0) or byt7_cmp2_b(1) ); + u_byt7cmp4_1: byt7_cmp4(1) <= not( byt7_cmp2_b(2) or byt7_cmp2_b(3) ); + + u_byt0cmp8b: byt_cmp_b(0) <= not( byt0_cmp4(0) and byt0_cmp4(1) ); + u_byt1cmp8b: byt_cmp_b(1) <= not( byt1_cmp4(0) and byt1_cmp4(1) ); + u_byt2cmp8b: byt_cmp_b(2) <= not( byt2_cmp4(0) and byt2_cmp4(1) ); + u_byt3cmp8b: byt_cmp_b(3) <= not( byt3_cmp4(0) and byt3_cmp4(1) ); + u_byt4cmp8b: byt_cmp_b(4) <= not( byt4_cmp4(0) and byt4_cmp4(1) ); + u_byt5cmp8b: byt_cmp_b(5) <= not( byt5_cmp4(0) and byt5_cmp4(1) ); + u_byt6cmp8b: byt_cmp_b(6) <= not( byt6_cmp4(0) and byt6_cmp4(1) ); + u_byt7cmp8b: byt_cmp_b(7) <= not( byt7_cmp4(0) and byt7_cmp4(1) ); + + + u_byt0cmp8: byt_cmp(0) <= not( byt_cmp_b(0) ); + u_byt1cmp8: byt_cmp(1) <= not( byt_cmp_b(1) ); + u_byt2cmp8: byt_cmp(2) <= not( byt_cmp_b(2) ); + u_byt3cmp8: byt_cmp(3) <= not( byt_cmp_b(3) ); + u_byt4cmp8: byt_cmp(4) <= not( byt_cmp_b(4) ); + u_byt5cmp8: byt_cmp(5) <= not( byt_cmp_b(5) ); + u_byt6cmp8: byt_cmp(6) <= not( byt_cmp_b(6) ); + u_byt7cmp8: byt_cmp(7) <= not( byt_cmp_b(7) ); + + + byt_cmp_bus( 0 to 7) <= ( 0 to 7=> byt_cmp(0) ); + byt_cmp_bus( 8 to 15) <= ( 8 to 15=> byt_cmp(1) ); + byt_cmp_bus(16 to 23) <= (16 to 23=> byt_cmp(2) ); + byt_cmp_bus(24 to 31) <= (24 to 31=> byt_cmp(3) ); + byt_cmp_bus(32 to 39) <= (32 to 39=> byt_cmp(4) ); + byt_cmp_bus(40 to 47) <= (40 to 47=> byt_cmp(5) ); + byt_cmp_bus(48 to 55) <= (48 to 55=> byt_cmp(6) ); + byt_cmp_bus(56 to 63) <= (56 to 63=> byt_cmp(7) ); + + + + xtd_byte_bus(0 to 63) <= (0 to 56 => data0(56) ) & data0(57 to 63) ; + xtd_half_bus(0 to 63) <= (0 to 48 => data0(48) ) & data0(49 to 63) ; + xtd_wd_bus (0 to 63) <= (0 to 32 => data0(32) ) & data0(33 to 63) ; + sra_wd_bus (0 to 63) <= (0 to 63 => data0(32) ); + sra_dw_bus (0 to 63) <= (0 to 63 => data0(0) ); + + + sign_xtd_bus(0 to 63) <= + ( (0 to 63=> ins_xtd_byte) and xtd_byte_bus(0 to 63) ) or + ( (0 to 63=> ins_xtd_half) and xtd_half_bus(0 to 63) ) or + ( (0 to 63=> ins_xtd_wd ) and xtd_wd_bus (0 to 63) ) or + ( (0 to 63=> ins_sra_wd ) and sra_wd_bus (0 to 63) ) or + ( (0 to 63=> ins_sra_dw ) and sra_dw_bus (0 to 63) ) ; + + sel_cmp_byt <= (0 to 63=> ins_cmp_byt); + sel_cmp_byt_b <= (0 to 63=> not(ins_cmp_byt)); + + u_res_ins0: res_ins0_b(0 to 63) <= not( sel_cmp_byt and byt_cmp_bus(0 to 63) ); + u_res_ins1: res_ins1_b(0 to 63) <= not( sel_cmp_byt_b and res_log(0 to 63) ); + u_res_ins2: res_ins2_b(0 to 63) <= not( sign_xtd_bus(0 to 63) ); + + u_res_ins : res_ins (0 to 63) <= not( res_ins0_b(0 to 63) and res_ins1_b(0 to 63) and res_ins2_b(0 to 63) ); + + +end architecture xuq_alu_ins; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_alu_mask.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_alu_mask.vhdl new file mode 100644 index 0000000..de23c4d --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_alu_mask.vhdl @@ -0,0 +1,369 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +LIBRARY ieee; USE ieee.std_logic_1164.all; + use ieee.numeric_std.all; +LIBRARY ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; +LIBRARY support; + use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity xuq_alu_mask is generic(expand_type: integer := 2 ); port ( + mb :in std_ulogic_vector(0 to 5); + me_b :in std_ulogic_vector(0 to 5); + zm :in std_ulogic; + mb_gt_me :in std_ulogic; + mask :out std_ulogic_vector(0 to 63) +); + +-- synopsys translate_off +-- synopsys translate_on +end xuq_alu_mask; + +architecture xuq_alu_mask of xuq_alu_mask is + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal mask_en_and, mask_en_mb, mask_en_me :std_ulogic ; + signal mask0_b, mask1_b, mask2_b :std_ulogic_vector(0 to 63); + signal mb_mask, me_mask :std_ulogic_vector(0 to 63) ; + + signal mb_msk45, mb_msk45_b :std_ulogic_vector(0 to 2); + signal mb_msk23, mb_msk23_b :std_ulogic_vector(0 to 2); + signal mb_msk01, mb_msk01_b :std_ulogic_vector(0 to 2); + signal mb_msk25, mb_msk25_b :std_ulogic_vector(0 to 14); + signal mb_msk01bb, mb_msk01bbb :std_ulogic_vector(0 to 2); + signal me_msk01, me_msk01_b :std_ulogic_vector( 1 to 3); + signal me_msk23, me_msk23_b :std_ulogic_vector( 1 to 3); + signal me_msk45, me_msk45_b :std_ulogic_vector( 1 to 3); + signal me_msk25, me_msk25_b :std_ulogic_vector(1 to 15); + signal me_msk01bbb, me_msk01bb :std_ulogic_vector(1 to 3); + + + + + + + + + + + + + + + +begin + + + + u_mb_msk45_0: mb_msk45(0) <= not( mb(4) or mb(5) ); + u_mb_msk45_1: mb_msk45(1) <= not( mb(4) ); + u_mb_msk45_2: mb_msk45(2) <= not( mb(4) and mb(5) ); + u_mb_msk23_0: mb_msk23(0) <= not( mb(2) or mb(3) ); + u_mb_msk23_1: mb_msk23(1) <= not( mb(2) ); + u_mb_msk23_2: mb_msk23(2) <= not( mb(2) and mb(3) ); + u_mb_msk01_0: mb_msk01(0) <= not( mb(0) or mb(1) ); + u_mb_msk01_1: mb_msk01(1) <= not( mb(0) ); + u_mb_msk01_2: mb_msk01(2) <= not( mb(0) and mb(1) ); + + u_mb_msk45b0: mb_msk45_b(0) <= not( mb_msk45(0) ); + u_mb_msk45b1: mb_msk45_b(1) <= not( mb_msk45(1) ); + u_mb_msk45b2: mb_msk45_b(2) <= not( mb_msk45(2) ); + u_mb_msk23b0: mb_msk23_b(0) <= not( mb_msk23(0) ); + u_mb_msk23b1: mb_msk23_b(1) <= not( mb_msk23(1) ); + u_mb_msk23b2: mb_msk23_b(2) <= not( mb_msk23(2) ); + u_mb_msk01b0: mb_msk01_b(0) <= not( mb_msk01(0) ); + u_mb_msk01b1: mb_msk01_b(1) <= not( mb_msk01(1) ); + u_mb_msk01b2: mb_msk01_b(2) <= not( mb_msk01(2) ); + + + + u_mb_msk25_0: mb_msk25(0) <= not( mb_msk23_b(0) or mb_msk45_b(0) ); + u_mb_msk25_1: mb_msk25(1) <= not( mb_msk23_b(0) or mb_msk45_b(1) ); + u_mb_msk25_2: mb_msk25(2) <= not( mb_msk23_b(0) or mb_msk45_b(2) ); + u_mb_msk25_3: mb_msk25(3) <= not( mb_msk23_b(0) ); + u_mb_msk25_4: mb_msk25(4) <= not( mb_msk23_b(0) and ( mb_msk23_b(1) or mb_msk45_b(0) ) ); + u_mb_msk25_5: mb_msk25(5) <= not( mb_msk23_b(0) and ( mb_msk23_b(1) or mb_msk45_b(1) ) ); + u_mb_msk25_6: mb_msk25(6) <= not( mb_msk23_b(0) and ( mb_msk23_b(1) or mb_msk45_b(2) ) ); + u_mb_msk25_7: mb_msk25(7) <= not( mb_msk23_b(1) ); + u_mb_msk25_8: mb_msk25(8) <= not( mb_msk23_b(1) and ( mb_msk23_b(2) or mb_msk45_b(0) ) ); + u_mb_msk25_9: mb_msk25(9) <= not( mb_msk23_b(1) and ( mb_msk23_b(2) or mb_msk45_b(1) ) ); + u_mb_msk25_10: mb_msk25(10) <= not( mb_msk23_b(1) and ( mb_msk23_b(2) or mb_msk45_b(2) ) ); + u_mb_msk25_11: mb_msk25(11) <= not( mb_msk23_b(2) ); + u_mb_msk25_12: mb_msk25(12) <= not( mb_msk23_b(2) and mb_msk45_b(0) ); + u_mb_msk25_13: mb_msk25(13) <= not( mb_msk23_b(2) and mb_msk45_b(1) ); + u_mb_msk25_14: mb_msk25(14) <= not( mb_msk23_b(2) and mb_msk45_b(2) ); + + u_mb_msk01bb0: mb_msk01bb(0) <= not( mb_msk01_b(0) ); + u_mb_msk01bb1: mb_msk01bb(1) <= not( mb_msk01_b(1) ); + u_mb_msk01bb2: mb_msk01bb(2) <= not( mb_msk01_b(2) ); + + + u_mb_msk25b0: mb_msk25_b(0) <= not( mb_msk25(0) ); + u_mb_msk25b1: mb_msk25_b(1) <= not( mb_msk25(1) ); + u_mb_msk25b2: mb_msk25_b(2) <= not( mb_msk25(2) ); + u_mb_msk25b3: mb_msk25_b(3) <= not( mb_msk25(3) ); + u_mb_msk25b4: mb_msk25_b(4) <= not( mb_msk25(4) ); + u_mb_msk25b5: mb_msk25_b(5) <= not( mb_msk25(5) ); + u_mb_msk25b6: mb_msk25_b(6) <= not( mb_msk25(6) ); + u_mb_msk25b7: mb_msk25_b(7) <= not( mb_msk25(7) ); + u_mb_msk25b8: mb_msk25_b(8) <= not( mb_msk25(8) ); + u_mb_msk25b9: mb_msk25_b(9) <= not( mb_msk25(9) ); + u_mb_msk25b10: mb_msk25_b(10) <= not( mb_msk25(10) ); + u_mb_msk25b11: mb_msk25_b(11) <= not( mb_msk25(11) ); + u_mb_msk25b12: mb_msk25_b(12) <= not( mb_msk25(12) ); + u_mb_msk25b13: mb_msk25_b(13) <= not( mb_msk25(13) ); + u_mb_msk25b14: mb_msk25_b(14) <= not( mb_msk25(14) ); + + u_mb_msk01bbb0: mb_msk01bbb(0) <= not( mb_msk01bb(0) ); + u_mb_msk01bbb1: mb_msk01bbb(1) <= not( mb_msk01bb(1) ); + u_mb_msk01bbb2: mb_msk01bbb(2) <= not( mb_msk01bb(2) ); + + u_mb_mask_0: mb_mask(0) <= not( mb_msk01bbb(0) or mb_msk25_b(0) ); + u_mb_mask_1: mb_mask(1) <= not( mb_msk01bbb(0) or mb_msk25_b(1) ); + u_mb_mask_2: mb_mask(2) <= not( mb_msk01bbb(0) or mb_msk25_b(2) ); + u_mb_mask_3: mb_mask(3) <= not( mb_msk01bbb(0) or mb_msk25_b(3) ); + u_mb_mask_4: mb_mask(4) <= not( mb_msk01bbb(0) or mb_msk25_b(4) ); + u_mb_mask_5: mb_mask(5) <= not( mb_msk01bbb(0) or mb_msk25_b(5) ); + u_mb_mask_6: mb_mask(6) <= not( mb_msk01bbb(0) or mb_msk25_b(6) ); + u_mb_mask_7: mb_mask(7) <= not( mb_msk01bbb(0) or mb_msk25_b(7) ); + u_mb_mask_8: mb_mask(8) <= not( mb_msk01bbb(0) or mb_msk25_b(8) ); + u_mb_mask_9: mb_mask(9) <= not( mb_msk01bbb(0) or mb_msk25_b(9) ); + u_mb_mask_10: mb_mask(10) <= not( mb_msk01bbb(0) or mb_msk25_b(10) ); + u_mb_mask_11: mb_mask(11) <= not( mb_msk01bbb(0) or mb_msk25_b(11) ); + u_mb_mask_12: mb_mask(12) <= not( mb_msk01bbb(0) or mb_msk25_b(12) ); + u_mb_mask_13: mb_mask(13) <= not( mb_msk01bbb(0) or mb_msk25_b(13) ); + u_mb_mask_14: mb_mask(14) <= not( mb_msk01bbb(0) or mb_msk25_b(14) ); + u_mb_mask_15: mb_mask(15) <= not( mb_msk01bbb(0) ); + u_mb_mask_16: mb_mask(16) <= not( mb_msk01bbb(0) and ( mb_msk01bbb(1) or mb_msk25_b(0) ) ); + u_mb_mask_17: mb_mask(17) <= not( mb_msk01bbb(0) and ( mb_msk01bbb(1) or mb_msk25_b(1) ) ); + u_mb_mask_18: mb_mask(18) <= not( mb_msk01bbb(0) and ( mb_msk01bbb(1) or mb_msk25_b(2) ) ); + u_mb_mask_19: mb_mask(19) <= not( mb_msk01bbb(0) and ( mb_msk01bbb(1) or mb_msk25_b(3) ) ); + u_mb_mask_20: mb_mask(20) <= not( mb_msk01bbb(0) and ( mb_msk01bbb(1) or mb_msk25_b(4) ) ); + u_mb_mask_21: mb_mask(21) <= not( mb_msk01bbb(0) and ( mb_msk01bbb(1) or mb_msk25_b(5) ) ); + u_mb_mask_22: mb_mask(22) <= not( mb_msk01bbb(0) and ( mb_msk01bbb(1) or mb_msk25_b(6) ) ); + u_mb_mask_23: mb_mask(23) <= not( mb_msk01bbb(0) and ( mb_msk01bbb(1) or mb_msk25_b(7) ) ); + u_mb_mask_24: mb_mask(24) <= not( mb_msk01bbb(0) and ( mb_msk01bbb(1) or mb_msk25_b(8) ) ); + u_mb_mask_25: mb_mask(25) <= not( mb_msk01bbb(0) and ( mb_msk01bbb(1) or mb_msk25_b(9) ) ); + u_mb_mask_26: mb_mask(26) <= not( mb_msk01bbb(0) and ( mb_msk01bbb(1) or mb_msk25_b(10)) ); + u_mb_mask_27: mb_mask(27) <= not( mb_msk01bbb(0) and ( mb_msk01bbb(1) or mb_msk25_b(11)) ); + u_mb_mask_28: mb_mask(28) <= not( mb_msk01bbb(0) and ( mb_msk01bbb(1) or mb_msk25_b(12)) ); + u_mb_mask_29: mb_mask(29) <= not( mb_msk01bbb(0) and ( mb_msk01bbb(1) or mb_msk25_b(13)) ); + u_mb_mask_30: mb_mask(30) <= not( mb_msk01bbb(0) and ( mb_msk01bbb(1) or mb_msk25_b(14)) ); + u_mb_mask_31: mb_mask(31) <= not( mb_msk01bbb(1) ); + u_mb_mask_32: mb_mask(32) <= not( mb_msk01bbb(1) and ( mb_msk01bbb(2) or mb_msk25_b(0) ) ); + u_mb_mask_33: mb_mask(33) <= not( mb_msk01bbb(1) and ( mb_msk01bbb(2) or mb_msk25_b(1) ) ); + u_mb_mask_34: mb_mask(34) <= not( mb_msk01bbb(1) and ( mb_msk01bbb(2) or mb_msk25_b(2) ) ); + u_mb_mask_35: mb_mask(35) <= not( mb_msk01bbb(1) and ( mb_msk01bbb(2) or mb_msk25_b(3) ) ); + u_mb_mask_36: mb_mask(36) <= not( mb_msk01bbb(1) and ( mb_msk01bbb(2) or mb_msk25_b(4) ) ); + u_mb_mask_37: mb_mask(37) <= not( mb_msk01bbb(1) and ( mb_msk01bbb(2) or mb_msk25_b(5) ) ); + u_mb_mask_38: mb_mask(38) <= not( mb_msk01bbb(1) and ( mb_msk01bbb(2) or mb_msk25_b(6) ) ); + u_mb_mask_39: mb_mask(39) <= not( mb_msk01bbb(1) and ( mb_msk01bbb(2) or mb_msk25_b(7) ) ); + u_mb_mask_40: mb_mask(40) <= not( mb_msk01bbb(1) and ( mb_msk01bbb(2) or mb_msk25_b(8) ) ); + u_mb_mask_41: mb_mask(41) <= not( mb_msk01bbb(1) and ( mb_msk01bbb(2) or mb_msk25_b(9) ) ); + u_mb_mask_42: mb_mask(42) <= not( mb_msk01bbb(1) and ( mb_msk01bbb(2) or mb_msk25_b(10)) ); + u_mb_mask_43: mb_mask(43) <= not( mb_msk01bbb(1) and ( mb_msk01bbb(2) or mb_msk25_b(11)) ); + u_mb_mask_44: mb_mask(44) <= not( mb_msk01bbb(1) and ( mb_msk01bbb(2) or mb_msk25_b(12)) ); + u_mb_mask_45: mb_mask(45) <= not( mb_msk01bbb(1) and ( mb_msk01bbb(2) or mb_msk25_b(13)) ); + u_mb_mask_46: mb_mask(46) <= not( mb_msk01bbb(1) and ( mb_msk01bbb(2) or mb_msk25_b(14)) ); + u_mb_mask_47: mb_mask(47) <= not( mb_msk01bbb(2) ); + u_mb_mask_48: mb_mask(48) <= not( mb_msk01bbb(2) and mb_msk25_b(0) ); + u_mb_mask_49: mb_mask(49) <= not( mb_msk01bbb(2) and mb_msk25_b(1) ); + u_mb_mask_50: mb_mask(50) <= not( mb_msk01bbb(2) and mb_msk25_b(2) ); + u_mb_mask_51: mb_mask(51) <= not( mb_msk01bbb(2) and mb_msk25_b(3) ); + u_mb_mask_52: mb_mask(52) <= not( mb_msk01bbb(2) and mb_msk25_b(4) ); + u_mb_mask_53: mb_mask(53) <= not( mb_msk01bbb(2) and mb_msk25_b(5) ); + u_mb_mask_54: mb_mask(54) <= not( mb_msk01bbb(2) and mb_msk25_b(6) ); + u_mb_mask_55: mb_mask(55) <= not( mb_msk01bbb(2) and mb_msk25_b(7) ); + u_mb_mask_56: mb_mask(56) <= not( mb_msk01bbb(2) and mb_msk25_b(8) ); + u_mb_mask_57: mb_mask(57) <= not( mb_msk01bbb(2) and mb_msk25_b(9) ); + u_mb_mask_58: mb_mask(58) <= not( mb_msk01bbb(2) and mb_msk25_b(10) ); + u_mb_mask_59: mb_mask(59) <= not( mb_msk01bbb(2) and mb_msk25_b(11) ); + u_mb_mask_60: mb_mask(60) <= not( mb_msk01bbb(2) and mb_msk25_b(12) ); + u_mb_mask_61: mb_mask(61) <= not( mb_msk01bbb(2) and mb_msk25_b(13) ); + u_mb_mask_62: mb_mask(62) <= not( mb_msk01bbb(2) and mb_msk25_b(14) ); + mb_mask(63) <= tiup ; + + + + + + u_me_msk45_1: me_msk45(1) <= not( me_b(4) and me_b(5) ); + u_me_msk45_2: me_msk45(2) <= not( me_b(4) ); + u_me_msk45_3: me_msk45(3) <= not( me_b(4) or me_b(5) ); + + u_me_msk23_1: me_msk23(1) <= not( me_b(2) and me_b(3) ); + u_me_msk23_2: me_msk23(2) <= not( me_b(2) ); + u_me_msk23_3: me_msk23(3) <= not( me_b(2) or me_b(3) ); + + u_me_msk01_1: me_msk01(1) <= not( me_b(0) and me_b(1) ); + u_me_msk01_2: me_msk01(2) <= not( me_b(0) ); + u_me_msk01_3: me_msk01(3) <= not( me_b(0) or me_b(1) ); + + + u_me_msk45b1: me_msk45_b(1) <= not( me_msk45(1) ); + u_me_msk45b2: me_msk45_b(2) <= not( me_msk45(2) ); + u_me_msk45b3: me_msk45_b(3) <= not( me_msk45(3) ); + u_me_msk23b1: me_msk23_b(1) <= not( me_msk23(1) ); + u_me_msk23b2: me_msk23_b(2) <= not( me_msk23(2) ); + u_me_msk23b3: me_msk23_b(3) <= not( me_msk23(3) ); + u_me_msk01b1: me_msk01_b(1) <= not( me_msk01(1) ); + u_me_msk01b2: me_msk01_b(2) <= not( me_msk01(2) ); + u_me_msk01b3: me_msk01_b(3) <= not( me_msk01(3) ); + + + + + u_me_msk25_1: me_msk25(1) <= not( me_msk23_b(1) and me_msk45_b(1) ); + u_me_msk25_2: me_msk25(2) <= not( me_msk23_b(1) and me_msk45_b(2) ); + u_me_msk25_3: me_msk25(3) <= not( me_msk23_b(1) and me_msk45_b(3) ); + u_me_msk25_4: me_msk25(4) <= not( me_msk23_b(1) ); + u_me_msk25_5: me_msk25(5) <= not( me_msk23_b(2) and ( me_msk23_b(1) or me_msk45_b(1) ) ); + u_me_msk25_6: me_msk25(6) <= not( me_msk23_b(2) and ( me_msk23_b(1) or me_msk45_b(2) ) ); + u_me_msk25_7: me_msk25(7) <= not( me_msk23_b(2) and ( me_msk23_b(1) or me_msk45_b(3) ) ); + u_me_msk25_8: me_msk25(8) <= not( me_msk23_b(2) ); + u_me_msk25_9: me_msk25(9) <= not( me_msk23_b(3) and ( me_msk23_b(2) or me_msk45_b(1) ) ); + u_me_msk25_10: me_msk25(10) <= not( me_msk23_b(3) and ( me_msk23_b(2) or me_msk45_b(2) ) ); + u_me_msk25_11: me_msk25(11) <= not( me_msk23_b(3) and ( me_msk23_b(2) or me_msk45_b(3) ) ); + u_me_msk25_12: me_msk25(12) <= not( me_msk23_b(3) ); + u_me_msk25_13: me_msk25(13) <= not( me_msk23_b(3) or me_msk45_b(1) ); + u_me_msk25_14: me_msk25(14) <= not( me_msk23_b(3) or me_msk45_b(2) ); + u_me_msk25_15: me_msk25(15) <= not( me_msk23_b(3) or me_msk45_b(3) ); + + u_me_msk01bb1: me_msk01bb(1) <= not( me_msk01_b(1) ); + u_me_msk01bb2: me_msk01bb(2) <= not( me_msk01_b(2) ); + u_me_msk01bb3: me_msk01bb(3) <= not( me_msk01_b(3) ); + + + u_me_msk25b1: me_msk25_b(1) <= not( me_msk25(1) ); + u_me_msk25b2: me_msk25_b(2) <= not( me_msk25(2) ); + u_me_msk25b3: me_msk25_b(3) <= not( me_msk25(3) ); + u_me_msk25b4: me_msk25_b(4) <= not( me_msk25(4) ); + u_me_msk25b5: me_msk25_b(5) <= not( me_msk25(5) ); + u_me_msk25b6: me_msk25_b(6) <= not( me_msk25(6) ); + u_me_msk25b7: me_msk25_b(7) <= not( me_msk25(7) ); + u_me_msk25b8: me_msk25_b(8) <= not( me_msk25(8) ); + u_me_msk25b9: me_msk25_b(9) <= not( me_msk25(9) ); + u_me_msk25b10: me_msk25_b(10) <= not( me_msk25(10) ); + u_me_msk25b11: me_msk25_b(11) <= not( me_msk25(11) ); + u_me_msk25b12: me_msk25_b(12) <= not( me_msk25(12) ); + u_me_msk25b13: me_msk25_b(13) <= not( me_msk25(13) ); + u_me_msk25b14: me_msk25_b(14) <= not( me_msk25(14) ); + u_me_msk25b15: me_msk25_b(15) <= not( me_msk25(15) ); + + u_me_msk01bbb1: me_msk01bbb(1) <= not( me_msk01bb(1) ); + u_me_msk01bbb2: me_msk01bbb(2) <= not( me_msk01bb(2) ); + u_me_msk01bbb3: me_msk01bbb(3) <= not( me_msk01bb(3) ); + + + + me_mask(0) <= tiup ; + u_me_mask_1: me_mask(1) <= not( me_msk01bbb(1) and me_msk25_b(1) ); + u_me_mask_2: me_mask(2) <= not( me_msk01bbb(1) and me_msk25_b(2) ); + u_me_mask_3: me_mask(3) <= not( me_msk01bbb(1) and me_msk25_b(3) ); + u_me_mask_4: me_mask(4) <= not( me_msk01bbb(1) and me_msk25_b(4) ); + u_me_mask_5: me_mask(5) <= not( me_msk01bbb(1) and me_msk25_b(5) ); + u_me_mask_6: me_mask(6) <= not( me_msk01bbb(1) and me_msk25_b(6) ); + u_me_mask_7: me_mask(7) <= not( me_msk01bbb(1) and me_msk25_b(7) ); + u_me_mask_8: me_mask(8) <= not( me_msk01bbb(1) and me_msk25_b(8) ); + u_me_mask_9: me_mask(9) <= not( me_msk01bbb(1) and me_msk25_b(9) ); + u_me_mask_10: me_mask(10) <= not( me_msk01bbb(1) and me_msk25_b(10) ); + u_me_mask_11: me_mask(11) <= not( me_msk01bbb(1) and me_msk25_b(11) ); + u_me_mask_12: me_mask(12) <= not( me_msk01bbb(1) and me_msk25_b(12) ); + u_me_mask_13: me_mask(13) <= not( me_msk01bbb(1) and me_msk25_b(13) ); + u_me_mask_14: me_mask(14) <= not( me_msk01bbb(1) and me_msk25_b(14) ); + u_me_mask_15: me_mask(15) <= not( me_msk01bbb(1) and me_msk25_b(15) ); + u_me_mask_16: me_mask(16) <= not( me_msk01bbb(1) ); + u_me_mask_17: me_mask(17) <= not( me_msk01bbb(2) and ( me_msk01bbb(1) or me_msk25_b(1) ) ); + u_me_mask_18: me_mask(18) <= not( me_msk01bbb(2) and ( me_msk01bbb(1) or me_msk25_b(2) ) ); + u_me_mask_19: me_mask(19) <= not( me_msk01bbb(2) and ( me_msk01bbb(1) or me_msk25_b(3) ) ); + u_me_mask_20: me_mask(20) <= not( me_msk01bbb(2) and ( me_msk01bbb(1) or me_msk25_b(4) ) ); + u_me_mask_21: me_mask(21) <= not( me_msk01bbb(2) and ( me_msk01bbb(1) or me_msk25_b(5) ) ); + u_me_mask_22: me_mask(22) <= not( me_msk01bbb(2) and ( me_msk01bbb(1) or me_msk25_b(6) ) ); + u_me_mask_23: me_mask(23) <= not( me_msk01bbb(2) and ( me_msk01bbb(1) or me_msk25_b(7) ) ); + u_me_mask_24: me_mask(24) <= not( me_msk01bbb(2) and ( me_msk01bbb(1) or me_msk25_b(8) ) ); + u_me_mask_25: me_mask(25) <= not( me_msk01bbb(2) and ( me_msk01bbb(1) or me_msk25_b(9) ) ); + u_me_mask_26: me_mask(26) <= not( me_msk01bbb(2) and ( me_msk01bbb(1) or me_msk25_b(10)) ); + u_me_mask_27: me_mask(27) <= not( me_msk01bbb(2) and ( me_msk01bbb(1) or me_msk25_b(11)) ); + u_me_mask_28: me_mask(28) <= not( me_msk01bbb(2) and ( me_msk01bbb(1) or me_msk25_b(12)) ); + u_me_mask_29: me_mask(29) <= not( me_msk01bbb(2) and ( me_msk01bbb(1) or me_msk25_b(13)) ); + u_me_mask_30: me_mask(30) <= not( me_msk01bbb(2) and ( me_msk01bbb(1) or me_msk25_b(14)) ); + u_me_mask_31: me_mask(31) <= not( me_msk01bbb(2) and ( me_msk01bbb(1) or me_msk25_b(15)) ); + u_me_mask_32: me_mask(32) <= not( me_msk01bbb(2) ); + u_me_mask_33: me_mask(33) <= not( me_msk01bbb(3) and ( me_msk01bbb(2) or me_msk25_b(1) ) ); + u_me_mask_34: me_mask(34) <= not( me_msk01bbb(3) and ( me_msk01bbb(2) or me_msk25_b(2) ) ); + u_me_mask_35: me_mask(35) <= not( me_msk01bbb(3) and ( me_msk01bbb(2) or me_msk25_b(3) ) ); + u_me_mask_36: me_mask(36) <= not( me_msk01bbb(3) and ( me_msk01bbb(2) or me_msk25_b(4) ) ); + u_me_mask_37: me_mask(37) <= not( me_msk01bbb(3) and ( me_msk01bbb(2) or me_msk25_b(5) ) ); + u_me_mask_38: me_mask(38) <= not( me_msk01bbb(3) and ( me_msk01bbb(2) or me_msk25_b(6) ) ); + u_me_mask_39: me_mask(39) <= not( me_msk01bbb(3) and ( me_msk01bbb(2) or me_msk25_b(7) ) ); + u_me_mask_40: me_mask(40) <= not( me_msk01bbb(3) and ( me_msk01bbb(2) or me_msk25_b(8) ) ); + u_me_mask_41: me_mask(41) <= not( me_msk01bbb(3) and ( me_msk01bbb(2) or me_msk25_b(9) ) ); + u_me_mask_42: me_mask(42) <= not( me_msk01bbb(3) and ( me_msk01bbb(2) or me_msk25_b(10)) ); + u_me_mask_43: me_mask(43) <= not( me_msk01bbb(3) and ( me_msk01bbb(2) or me_msk25_b(11)) ); + u_me_mask_44: me_mask(44) <= not( me_msk01bbb(3) and ( me_msk01bbb(2) or me_msk25_b(12)) ); + u_me_mask_45: me_mask(45) <= not( me_msk01bbb(3) and ( me_msk01bbb(2) or me_msk25_b(13)) ); + u_me_mask_46: me_mask(46) <= not( me_msk01bbb(3) and ( me_msk01bbb(2) or me_msk25_b(14)) ); + u_me_mask_47: me_mask(47) <= not( me_msk01bbb(3) and ( me_msk01bbb(2) or me_msk25_b(15)) ); + u_me_mask_48: me_mask(48) <= not( me_msk01bbb(3) ); + u_me_mask_49: me_mask(49) <= not( me_msk01bbb(3) or me_msk25_b(1) ); + u_me_mask_50: me_mask(50) <= not( me_msk01bbb(3) or me_msk25_b(2) ); + u_me_mask_51: me_mask(51) <= not( me_msk01bbb(3) or me_msk25_b(3) ); + u_me_mask_52: me_mask(52) <= not( me_msk01bbb(3) or me_msk25_b(4) ); + u_me_mask_53: me_mask(53) <= not( me_msk01bbb(3) or me_msk25_b(5) ); + u_me_mask_54: me_mask(54) <= not( me_msk01bbb(3) or me_msk25_b(6) ); + u_me_mask_55: me_mask(55) <= not( me_msk01bbb(3) or me_msk25_b(7) ); + u_me_mask_56: me_mask(56) <= not( me_msk01bbb(3) or me_msk25_b(8) ); + u_me_mask_57: me_mask(57) <= not( me_msk01bbb(3) or me_msk25_b(9) ); + u_me_mask_58: me_mask(58) <= not( me_msk01bbb(3) or me_msk25_b(10) ); + u_me_mask_59: me_mask(59) <= not( me_msk01bbb(3) or me_msk25_b(11) ); + u_me_mask_60: me_mask(60) <= not( me_msk01bbb(3) or me_msk25_b(12) ); + u_me_mask_61: me_mask(61) <= not( me_msk01bbb(3) or me_msk25_b(13) ); + u_me_mask_62: me_mask(62) <= not( me_msk01bbb(3) or me_msk25_b(14) ); + u_me_mask_63: me_mask(63) <= not( me_msk01bbb(3) or me_msk25_b(15) ); + + + + mask_en_and <= not mb_gt_me and not zm ; + mask_en_mb <= mb_gt_me and not zm ; + mask_en_me <= mb_gt_me and not zm ; + + u_mask0: mask0_b(0 to 63) <= not( mb_mask(0 to 63) and me_mask(0 to 63) and (0 to 63=> mask_en_and) ); + u_mask1: mask1_b(0 to 63) <= not( mb_mask(0 to 63) and (0 to 63=> mask_en_mb) ); + u_mask2: mask2_b(0 to 63) <= not( me_mask(0 to 63) and (0 to 63=> mask_en_me) ); + + u_mask: mask(0 to 63) <= not( mask0_b(0 to 63) and mask1_b(0 to 63) and mask2_b(0 to 63) ); + + +end architecture xuq_alu_mask; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_alu_mrg.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_alu_mrg.vhdl new file mode 100644 index 0000000..2164089 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_alu_mrg.vhdl @@ -0,0 +1,799 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library work,ieee,ibm,support,tri; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_unsigned.all; +use ibm.std_ulogic_function_support.all; +use support.power_logic_pkg.all; +use tri.tri_latches_pkg.all; + +entity xuq_alu_mrg is + generic( + expand_type : integer := 2); + port ( + nclk : in clk_logic; + vdd : inout power_logic; + gnd : inout power_logic; + d_mode_dc : in std_ulogic; + delay_lclkr_dc : in std_ulogic; + mpw1_dc_b : in std_ulogic; + mpw2_dc_b : in std_ulogic; + func_sl_force : in std_ulogic; + func_sl_thold_0_b : in std_ulogic; + sg_0 : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + rf1_act : in std_ulogic; + ex1_act : in std_ulogic; + + dec_alu_rf1_zm_ins : in std_ulogic ; + dec_alu_rf1_mb_ins : in std_ulogic_vector(0 to 5); + dec_alu_rf1_me_ins_b : in std_ulogic_vector(0 to 5); + dec_alu_rf1_sh_amt : in std_ulogic_vector(0 to 5); + dec_alu_rf1_sh_right : in std_ulogic; + dec_alu_rf1_sh_word : in std_ulogic; + + + dec_alu_rf1_use_rb_amt_hi : in std_ulogic; + dec_alu_rf1_use_rb_amt_lo : in std_ulogic; + dec_alu_rf1_use_me_rb_hi : in std_ulogic; + dec_alu_rf1_use_me_rb_lo : in std_ulogic; + dec_alu_rf1_use_mb_rb_hi : in std_ulogic; + dec_alu_rf1_use_mb_rb_lo : in std_ulogic; + dec_alu_rf1_use_me_ins_hi : in std_ulogic; + dec_alu_rf1_use_me_ins_lo : in std_ulogic; + dec_alu_rf1_use_mb_ins_hi : in std_ulogic; + dec_alu_rf1_use_mb_ins_lo : in std_ulogic; + + dec_alu_rf1_chk_shov_wd : in std_ulogic; + dec_alu_rf1_chk_shov_dw : in std_ulogic; + dec_alu_rf1_mb_gt_me : in std_ulogic; + + dec_alu_rf1_cmp_byt : in std_ulogic; + + dec_alu_rf1_sgnxtd_byte : in std_ulogic; + dec_alu_rf1_sgnxtd_half : in std_ulogic; + dec_alu_rf1_sgnxtd_wd : in std_ulogic; + dec_alu_rf1_sra_wd : in std_ulogic; + dec_alu_rf1_sra_dw : in std_ulogic; + + byp_alu_rf1_isel_fcn : in std_ulogic_vector(0 to 3); + dec_alu_rf1_log_fcn : in std_ulogic_vector(0 to 3); + dec_alu_rf1_sel_rot_log : in std_ulogic; + + byp_alu_ex1_rs0_b : in std_ulogic_vector(0 to 63); + byp_alu_ex1_rs1_b : in std_ulogic_vector(0 to 63); + add_mrg_ex1_add_rt : in std_ulogic_vector(0 to 63); + mrg_add_ex2_rt : out std_ulogic_vector(0 to 63); + alu_byp_ex1_log_rt : out std_ulogic_vector(0 to 63); + + ex2_mrg_xer_ca : out std_ulogic + + ); +-- synopsys translate_off +-- synopsys translate_on + +end xuq_alu_mrg; + +architecture xuq_alu_mrg of xuq_alu_mrg is + +signal ex1_mb_ins_q : std_ulogic_vector(0 to 5); +signal ex1_me_ins_b_q : std_ulogic_vector(0 to 5); +signal ex1_sh_amt_q : std_ulogic_vector(0 to 5); +signal ex1_sh_right_q, rf1_sh_right : std_ulogic_vector(0 to 2); +signal ex1_sh_word_q, rf1_sh_word : std_ulogic_vector(0 to 1); +signal ex1_zm_ins_q : std_ulogic; +signal ex1_chk_shov_wd_q : std_ulogic; +signal ex1_chk_shov_dw_q : std_ulogic; +signal ex1_use_sh_amt_hi_q, rf1_use_sh_amt_hi : std_ulogic; +signal ex1_use_sh_amt_lo_q, rf1_use_sh_amt_lo : std_ulogic; +signal ex1_use_rb_amt_hi_q : std_ulogic; +signal ex1_use_rb_amt_lo_q : std_ulogic; +signal ex1_use_me_rb_hi_q : std_ulogic; +signal ex1_use_me_rb_lo_q : std_ulogic; +signal ex1_use_mb_rb_hi_q : std_ulogic; +signal ex1_use_mb_rb_lo_q : std_ulogic; +signal ex1_use_me_ins_hi_q : std_ulogic; +signal ex1_use_me_ins_lo_q : std_ulogic; +signal ex1_use_mb_ins_hi_q : std_ulogic; +signal ex1_use_mb_ins_lo_q : std_ulogic; +signal ex1_mb_gt_me_q : std_ulogic; +signal ex1_cmp_byte_q : std_ulogic; +signal ex1_sgnxtd_byte_q : std_ulogic; +signal ex1_sgnxtd_half_q : std_ulogic; +signal ex1_sgnxtd_wd_q : std_ulogic; +signal ex1_sra_wd_q : std_ulogic; +signal ex1_sra_dw_q : std_ulogic; +signal ex1_log_fcn_q, rf1_log_fcn : std_ulogic_vector(0 to 3); +signal ex1_sel_rot_log_q : std_ulogic; +signal ex2_sh_word_q : std_ulogic; +signal ex2_rotate_b_q, ex1_result : std_ulogic_vector(0 to 63); +signal ex2_result_b_q, ex1_rotate : std_ulogic_vector(0 to 63); +signal ex2_mask_b_q, ex1_mask : std_ulogic_vector(0 to 63); +signal ex2_sra_se_q, ex1_sra_se_b : std_ulogic_vector(0 to 0); +signal dummy_q : std_ulogic_vector(0 to 0); +constant ex1_mb_ins_offset : integer := 0; +constant ex1_me_ins_b_offset : integer := ex1_mb_ins_offset + ex1_mb_ins_q'length; +constant ex1_sh_amt_offset : integer := ex1_me_ins_b_offset + ex1_me_ins_b_q'length; +constant ex1_sh_right_offset : integer := ex1_sh_amt_offset + ex1_sh_amt_q'length; +constant ex1_sh_word_offset : integer := ex1_sh_right_offset + ex1_sh_right_q'length; +constant ex1_zm_ins_offset : integer := ex1_sh_word_offset + ex1_sh_word_q'length; +constant ex1_chk_shov_wd_offset : integer := ex1_zm_ins_offset + 1; +constant ex1_chk_shov_dw_offset : integer := ex1_chk_shov_wd_offset + 1; +constant ex1_use_sh_amt_hi_offset : integer := ex1_chk_shov_dw_offset + 1; +constant ex1_use_sh_amt_lo_offset : integer := ex1_use_sh_amt_hi_offset + 1; +constant ex1_use_rb_amt_hi_offset : integer := ex1_use_sh_amt_lo_offset + 1; +constant ex1_use_rb_amt_lo_offset : integer := ex1_use_rb_amt_hi_offset + 1; +constant ex1_use_me_rb_hi_offset : integer := ex1_use_rb_amt_lo_offset + 1; +constant ex1_use_me_rb_lo_offset : integer := ex1_use_me_rb_hi_offset + 1; +constant ex1_use_mb_rb_hi_offset : integer := ex1_use_me_rb_lo_offset + 1; +constant ex1_use_mb_rb_lo_offset : integer := ex1_use_mb_rb_hi_offset + 1; +constant ex1_use_me_ins_hi_offset : integer := ex1_use_mb_rb_lo_offset + 1; +constant ex1_use_me_ins_lo_offset : integer := ex1_use_me_ins_hi_offset + 1; +constant ex1_use_mb_ins_hi_offset : integer := ex1_use_me_ins_lo_offset + 1; +constant ex1_use_mb_ins_lo_offset : integer := ex1_use_mb_ins_hi_offset + 1; +constant ex1_mb_gt_me_offset : integer := ex1_use_mb_ins_lo_offset + 1; +constant ex1_cmp_byte_offset : integer := ex1_mb_gt_me_offset + 1; +constant ex1_sgnxtd_byte_offset : integer := ex1_cmp_byte_offset + 1; +constant ex1_sgnxtd_half_offset : integer := ex1_sgnxtd_byte_offset + 1; +constant ex1_sgnxtd_wd_offset : integer := ex1_sgnxtd_half_offset + 1; +constant ex1_sra_wd_offset : integer := ex1_sgnxtd_wd_offset + 1; +constant ex1_sra_dw_offset : integer := ex1_sra_wd_offset + 1; +constant ex1_log_fcn_offset : integer := ex1_sra_dw_offset + 1; +constant ex1_sel_rot_log_offset : integer := ex1_log_fcn_offset + ex1_log_fcn_q'length; +constant ex2_sh_word_offset : integer := ex1_sel_rot_log_offset + 1; +constant ex2_rotate_b_offset : integer := ex2_sh_word_offset + 1; +constant ex2_result_b_offset : integer := ex2_rotate_b_offset + ex2_rotate_b_q'length; +constant ex2_mask_b_offset : integer := ex2_result_b_offset + ex2_result_b_q'length; +constant ex2_sra_se_offset : integer := ex2_mask_b_offset + ex2_mask_b_q'length; +constant dummy_offset : integer := ex2_sra_se_offset + ex2_sra_se_q'length; +constant scan_right : integer := dummy_offset + dummy_q'length; +signal siv : std_ulogic_vector(0 to scan_right-1); +signal sov : std_ulogic_vector(0 to scan_right-1); +signal tidn : std_ulogic; +signal rot_lclk_int : clk_logic; +signal rot_d1clk_int, rot_d2clk_int : std_ulogic; +signal ex1_zm : std_ulogic; +signal ex1_use_sh_amt, ex1_use_rb_amt : std_ulogic_vector(0 to 5); +signal ex1_use_me_rb, ex1_use_mb_rb : std_ulogic_vector(0 to 5); +signal ex1_use_me_ins, ex1_use_mb_ins : std_ulogic_vector(0 to 5); +signal ex1_sh_amt0_b, ex1_sh_amt1_b, ex1_sh_amt : std_ulogic_vector(0 to 5); +signal ex1_mb0_b, ex1_mb1_b, ex1_mb : std_ulogic_vector(0 to 5); +signal ex1_me0, ex1_me1, ex1_me_b : std_ulogic_vector(0 to 5); +signal ex1_mask_b, ex1_insert : std_ulogic_vector(0 to 63); +signal ex1_sel_add : std_ulogic; +signal ex1_msk_rot_b, ex1_msk_ins_b, ex1_msk_rot : std_ulogic_vector(0 to 63); +signal ex1_msk_ins : std_ulogic_vector(0 to 63); +signal ex1_result_0_b, ex1_result_1_b, ex1_result_2_b : std_ulogic_vector(0 to 63); +signal ca_root_b : std_ulogic_vector(0 to 63); +signal ca_or_hi, ca_or_lo : std_ulogic; +signal ex1_act_unqiue : std_ulogic; +signal ex1_ins_rs0, ex1_ins_rs1, ex1_rot_rs0 : std_ulogic_vector(0 to 63); +signal ex1_rot_rs1 : std_ulogic_vector(57 to 63); +signal ex2_result_q, ex2_rotate_q : std_ulogic_vector(0 to 63); + + + + + + + + + + + +begin + +tidn <= '0'; + +rf1_sh_right <= (0 to 2=>dec_alu_rf1_sh_right); +rf1_sh_word <= (0 to 1=>dec_alu_rf1_sh_word); +rf1_use_sh_amt_hi <= not dec_alu_rf1_use_rb_amt_hi; +rf1_use_sh_amt_lo <= not dec_alu_rf1_use_rb_amt_lo; + +u_rot_s0_pass: ex1_ins_rs0 <= not byp_alu_ex1_rs0_b; +u_rot_s1_pass: ex1_ins_rs1 <= not byp_alu_ex1_rs1_b; +u_rot_s0: ex1_rot_rs0 <= not byp_alu_ex1_rs0_b; +u_rot_s1: ex1_rot_rs1 <= not byp_alu_ex1_rs1_b(57 to 63); + +ex1_use_sh_amt <= ex1_use_sh_amt_hi_q & (1 to 5=>ex1_use_sh_amt_lo_q); +ex1_use_rb_amt <= ex1_use_rb_amt_hi_q & (1 to 5=>ex1_use_rb_amt_lo_q); +ex1_use_me_rb <= ex1_use_me_rb_hi_q & (1 to 5=>ex1_use_me_rb_lo_q); +ex1_use_mb_rb <= ex1_use_mb_rb_hi_q & (1 to 5=>ex1_use_mb_rb_lo_q); +ex1_use_me_ins <= ex1_use_me_ins_hi_q & (1 to 5=>ex1_use_me_ins_lo_q); +ex1_use_mb_ins <= ex1_use_mb_ins_hi_q & (1 to 5=>ex1_use_mb_ins_lo_q); + +ex1_zm <= (ex1_zm_ins_q ) or + (ex1_chk_shov_wd_q and ex1_rot_rs1(58)) or + (ex1_chk_shov_dw_q and ex1_rot_rs1(57)); + + +u_shamt0: ex1_sh_amt0_b <= ex1_rot_rs1(58 to 63) nand ex1_use_rb_amt; +u_shamt1: ex1_sh_amt1_b <= ex1_sh_amt_q nand ex1_use_sh_amt; + +u_shamt: ex1_sh_amt <= ex1_sh_amt0_b nand ex1_sh_amt1_b; + + +u_mbamt0: ex1_mb0_b <= ex1_rot_rs1(58 to 63) nand ex1_use_mb_rb; +u_mbamt1: ex1_mb1_b <= ex1_mb_ins_q nand ex1_use_mb_ins; + +u_mbamt: ex1_mb <= ex1_mb0_b nand ex1_mb1_b; + + +u_meamt0: ex1_me0 <= ex1_rot_rs1(58 to 63) nand ex1_use_me_rb; +u_meamt1: ex1_me1 <= ex1_me_ins_b_q nand ex1_use_me_ins; + +u_meamt: ex1_me_b <= ex1_me0 nand ex1_me1; + + +msk: entity work.xuq_alu_mask(xuq_alu_mask) + generic map (expand_type => expand_type) + port map( + mb => ex1_mb, + me_b => ex1_me_b, + zm => ex1_zm, + mb_gt_me => ex1_mb_gt_me_q, + mask => ex1_mask); + +rf1_log_fcn <= dec_alu_rf1_log_fcn or byp_alu_rf1_isel_fcn; + +ins: entity work.xuq_alu_ins(xuq_alu_ins) + generic map (expand_type => expand_type) + port map( + ins_log_fcn => ex1_log_fcn_q, + ins_cmp_byt => ex1_cmp_byte_q, + ins_sra_dw => ex1_sra_dw_q, + ins_sra_wd => ex1_sra_wd_q, + ins_xtd_byte => ex1_sgnxtd_byte_q, + ins_xtd_half => ex1_sgnxtd_half_q, + ins_xtd_wd => ex1_sgnxtd_wd_q, + data0_i => ex1_ins_rs0, + data1_i => ex1_ins_rs1, + mrg_byp_log => alu_byp_ex1_log_rt, + res_ins => ex1_insert ); + +rol64: entity work.xuq_alu_rol64(xuq_alu_rol64) + generic map (expand_type => expand_type) + port map( + word => ex1_sh_word_q, + right => ex1_sh_right_q, + amt => ex1_sh_amt, + data_i => ex1_rot_rs0, + res_rot => ex1_rotate); + + +u_msk_inv: ex1_mask_b <= not ex1_mask; +u_seladd: ex1_sel_add <= not ex1_sel_rot_log_q; + +u_selrotb: ex1_msk_rot_b <= ex1_mask nand (0 to 63=> ex1_sel_rot_log_q); +u_selinsb: ex1_msk_ins_b <= ex1_mask_b nand (0 to 63=> ex1_sel_rot_log_q); + +u_selrot: ex1_msk_rot <= not ex1_msk_rot_b; +u_selins: ex1_msk_ins <= not ex1_msk_ins_b; + +u_res_din0: ex1_result_0_b <= ex1_rotate nand ex1_msk_rot; +u_res_din1: ex1_result_1_b <= ex1_insert nand ex1_msk_ins; +u_res_din2: ex1_result_2_b <= add_mrg_ex1_add_rt nand (0 to 63=> ex1_sel_add); +u_res_din: ex1_result <= not(ex1_result_0_b and ex1_result_1_b and ex1_result_2_b); + +u_res_q: ex2_result_q <= not ex2_result_b_q; + +mrg_add_ex2_rt <= ex2_result_q; + +caor: entity work.xuq_alu_caor(xuq_alu_caor) + generic map (expand_type => expand_type) + port map( + ca_root_b => ca_root_b, + ca_or_hi => ca_or_hi, + ca_or_lo => ca_or_lo); + +u_rot_inv: ex2_rotate_q <= not ex2_rotate_b_q; +u_ca_root: ca_root_b <= not(ex2_rotate_q and ex2_mask_b_q); + +ex1_sra_se_b(0)<= not((ex1_ins_rs0(0) and not ex1_sh_word_q(0)) or + (ex1_ins_rs0(32) and ex1_sh_word_q(0))); + +ex2_mrg_xer_ca <= ( ca_or_lo and ex2_sra_se_q(0) and ex2_sh_word_q) or + ((ca_or_lo or ca_or_hi) and ex2_sra_se_q(0) and not ex2_sh_word_q); + + +ex1_act_unqiue <= ex1_act or dummy_q(0); + +ex1_mb_ins_latch : tri_rlmreg_p + generic map (width => ex1_mb_ins_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_mb_ins_offset to ex1_mb_ins_offset + ex1_mb_ins_q'length-1), + scout => sov(ex1_mb_ins_offset to ex1_mb_ins_offset + ex1_mb_ins_q'length-1), + din => dec_alu_rf1_mb_ins, + dout => ex1_mb_ins_q); +ex1_me_ins_b_latch : tri_rlmreg_p + generic map (width => ex1_me_ins_b_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_me_ins_b_offset to ex1_me_ins_b_offset + ex1_me_ins_b_q'length-1), + scout => sov(ex1_me_ins_b_offset to ex1_me_ins_b_offset + ex1_me_ins_b_q'length-1), + din => dec_alu_rf1_me_ins_b, + dout => ex1_me_ins_b_q); +ex1_sh_amt_latch : tri_rlmreg_p + generic map (width => ex1_sh_amt_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_sh_amt_offset to ex1_sh_amt_offset + ex1_sh_amt_q'length-1), + scout => sov(ex1_sh_amt_offset to ex1_sh_amt_offset + ex1_sh_amt_q'length-1), + din => dec_alu_rf1_sh_amt, + dout => ex1_sh_amt_q); +ex1_sh_right_latch : tri_rlmreg_p + generic map (width => ex1_sh_right_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_sh_right_offset to ex1_sh_right_offset + ex1_sh_right_q'length-1), + scout => sov(ex1_sh_right_offset to ex1_sh_right_offset + ex1_sh_right_q'length-1), + din => rf1_sh_right, + dout => ex1_sh_right_q); +ex1_sh_word_latch : tri_rlmreg_p + generic map (width => ex1_sh_word_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_sh_word_offset to ex1_sh_word_offset + ex1_sh_word_q'length-1), + scout => sov(ex1_sh_word_offset to ex1_sh_word_offset + ex1_sh_word_q'length-1), + din => rf1_sh_word, + dout => ex1_sh_word_q); +ex1_zm_ins_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_zm_ins_offset), + scout => sov(ex1_zm_ins_offset), + din => dec_alu_rf1_zm_ins, + dout => ex1_zm_ins_q); +ex1_chk_shov_wd_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_chk_shov_wd_offset), + scout => sov(ex1_chk_shov_wd_offset), + din => dec_alu_rf1_chk_shov_wd, + dout => ex1_chk_shov_wd_q); +ex1_chk_shov_dw_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_chk_shov_dw_offset), + scout => sov(ex1_chk_shov_dw_offset), + din => dec_alu_rf1_chk_shov_dw, + dout => ex1_chk_shov_dw_q); +ex1_use_sh_amt_hi_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_use_sh_amt_hi_offset), + scout => sov(ex1_use_sh_amt_hi_offset), + din => rf1_use_sh_amt_hi, + dout => ex1_use_sh_amt_hi_q); +ex1_use_sh_amt_lo_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_use_sh_amt_lo_offset), + scout => sov(ex1_use_sh_amt_lo_offset), + din => rf1_use_sh_amt_lo, + dout => ex1_use_sh_amt_lo_q); +ex1_use_rb_amt_hi_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_use_rb_amt_hi_offset), + scout => sov(ex1_use_rb_amt_hi_offset), + din => dec_alu_rf1_use_rb_amt_hi, + dout => ex1_use_rb_amt_hi_q); +ex1_use_rb_amt_lo_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_use_rb_amt_lo_offset), + scout => sov(ex1_use_rb_amt_lo_offset), + din => dec_alu_rf1_use_rb_amt_lo, + dout => ex1_use_rb_amt_lo_q); +ex1_use_me_rb_hi_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_use_me_rb_hi_offset), + scout => sov(ex1_use_me_rb_hi_offset), + din => dec_alu_rf1_use_me_rb_hi, + dout => ex1_use_me_rb_hi_q); +ex1_use_me_rb_lo_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_use_me_rb_lo_offset), + scout => sov(ex1_use_me_rb_lo_offset), + din => dec_alu_rf1_use_me_rb_lo, + dout => ex1_use_me_rb_lo_q); +ex1_use_mb_rb_hi_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_use_mb_rb_hi_offset), + scout => sov(ex1_use_mb_rb_hi_offset), + din => dec_alu_rf1_use_mb_rb_hi, + dout => ex1_use_mb_rb_hi_q); +ex1_use_mb_rb_lo_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_use_mb_rb_lo_offset), + scout => sov(ex1_use_mb_rb_lo_offset), + din => dec_alu_rf1_use_mb_rb_lo, + dout => ex1_use_mb_rb_lo_q); +ex1_use_me_ins_hi_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_use_me_ins_hi_offset), + scout => sov(ex1_use_me_ins_hi_offset), + din => dec_alu_rf1_use_me_ins_hi, + dout => ex1_use_me_ins_hi_q); +ex1_use_me_ins_lo_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_use_me_ins_lo_offset), + scout => sov(ex1_use_me_ins_lo_offset), + din => dec_alu_rf1_use_me_ins_lo, + dout => ex1_use_me_ins_lo_q); +ex1_use_mb_ins_hi_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_use_mb_ins_hi_offset), + scout => sov(ex1_use_mb_ins_hi_offset), + din => dec_alu_rf1_use_mb_ins_hi, + dout => ex1_use_mb_ins_hi_q); +ex1_use_mb_ins_lo_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_use_mb_ins_lo_offset), + scout => sov(ex1_use_mb_ins_lo_offset), + din => dec_alu_rf1_use_mb_ins_lo, + dout => ex1_use_mb_ins_lo_q); +ex1_mb_gt_me_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_mb_gt_me_offset), + scout => sov(ex1_mb_gt_me_offset), + din => dec_alu_rf1_mb_gt_me, + dout => ex1_mb_gt_me_q); +ex1_cmp_byte_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_cmp_byte_offset), + scout => sov(ex1_cmp_byte_offset), + din => dec_alu_rf1_cmp_byt, + dout => ex1_cmp_byte_q); +ex1_sgnxtd_byte_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_sgnxtd_byte_offset), + scout => sov(ex1_sgnxtd_byte_offset), + din => dec_alu_rf1_sgnxtd_byte, + dout => ex1_sgnxtd_byte_q); +ex1_sgnxtd_half_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_sgnxtd_half_offset), + scout => sov(ex1_sgnxtd_half_offset), + din => dec_alu_rf1_sgnxtd_half, + dout => ex1_sgnxtd_half_q); +ex1_sgnxtd_wd_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_sgnxtd_wd_offset), + scout => sov(ex1_sgnxtd_wd_offset), + din => dec_alu_rf1_sgnxtd_wd, + dout => ex1_sgnxtd_wd_q); +ex1_sra_wd_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_sra_wd_offset), + scout => sov(ex1_sra_wd_offset), + din => dec_alu_rf1_sra_wd, + dout => ex1_sra_wd_q); +ex1_sra_dw_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_sra_dw_offset), + scout => sov(ex1_sra_dw_offset), + din => dec_alu_rf1_sra_dw, + dout => ex1_sra_dw_q); +ex1_log_fcn_latch : tri_rlmreg_p + generic map (width => ex1_log_fcn_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_log_fcn_offset to ex1_log_fcn_offset + ex1_log_fcn_q'length-1), + scout => sov(ex1_log_fcn_offset to ex1_log_fcn_offset + ex1_log_fcn_q'length-1), + din => rf1_log_fcn, + dout => ex1_log_fcn_q); +ex1_sel_rot_log_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_sel_rot_log_offset), + scout => sov(ex1_sel_rot_log_offset), + din => dec_alu_rf1_sel_rot_log, + dout => ex1_sel_rot_log_q); +ex2_sh_word_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_sh_word_offset), + scout => sov(ex2_sh_word_offset), + din => ex1_sh_word_q(1), + dout => ex2_sh_word_q); +ex2_mrg_lcb: entity tri.tri_lcbnd(tri_lcbnd) + port map(vd => vdd, + gd => gnd, + act => ex1_act_unqiue, + nclk => nclk, + forcee => func_sl_force, + thold_b => func_sl_thold_0_b, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + sg => sg_0, + lclk => rot_lclk_int, + d1clk => rot_d1clk_int, + d2clk => rot_d2clk_int); + +rot_lat : entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width => ex2_rotate_b_q'length, expand_type => expand_type, btr => "NLI0001_X1_A12TH", init=>(ex2_rotate_b_q'range=>'0')) + port map (vd => vdd, gd => gnd, + LCLK => rot_lclk_int, + D1CLK => rot_d1clk_int, + D2CLK => rot_d2clk_int, + SCANIN => siv(ex2_rotate_b_offset to ex2_rotate_b_offset + ex2_rotate_b_q'length-1), + SCANOUT => sov(ex2_rotate_b_offset to ex2_rotate_b_offset + ex2_rotate_b_q'length-1), + D => ex1_rotate, + QB => ex2_rotate_b_q); +res_lat : entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width => ex2_result_b_q'length, expand_type => expand_type, btr => "NLI0001_X2_A12TH", init=>(ex2_result_b_q'range=>'0')) + port map (vd => vdd, gd => gnd, + LCLK => rot_lclk_int, + D1CLK => rot_d1clk_int, + D2CLK => rot_d2clk_int, + SCANIN => siv(ex2_result_b_offset to ex2_result_b_offset + ex2_result_b_q'length-1), + SCANOUT => sov(ex2_result_b_offset to ex2_result_b_offset + ex2_result_b_q'length-1), + D => ex1_result, + QB => ex2_result_b_q); +msk_lat : entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width => ex2_mask_b_q'length, expand_type => expand_type, btr => "NLI0001_X1_A12TH", init=>(ex2_mask_b_q'range=>'0')) + port map (vd => vdd, gd => gnd, + LCLK => rot_lclk_int, + D1CLK => rot_d1clk_int, + D2CLK => rot_d2clk_int, + SCANIN => siv(ex2_mask_b_offset to ex2_mask_b_offset + ex2_mask_b_q'length-1), + SCANOUT => sov(ex2_mask_b_offset to ex2_mask_b_offset + ex2_mask_b_q'length-1), + D => ex1_mask, + QB => ex2_mask_b_q); +ex2_sra_se_latch : entity tri.tri_inv_nlats_wlcb(tri_inv_nlats_wlcb) + generic map (width => ex2_sra_se_q'length, init => 0, expand_type => expand_type, needs_sreset => 1, btr => "NLI0001_X1_A12TH") + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_sra_se_offset to ex2_sra_se_offset + ex2_sra_se_q'length-1), + scout => sov(ex2_sra_se_offset to ex2_sra_se_offset + ex2_sra_se_q'length-1), + D => ex1_sra_se_b, + QB => ex2_sra_se_q); + +dummy_latch : tri_rlmreg_p + generic map (width => dummy_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tidn, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dummy_offset to dummy_offset + dummy_q'length-1), + scout => sov(dummy_offset to dummy_offset + dummy_q'length-1), + din => dummy_q, + dout => dummy_q); + +siv(0 to scan_right-1) <= sov(1 to scan_right-1) & scan_in; +scan_out <= sov(0); + + +end architecture xuq_alu_mrg; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_alu_mult.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_alu_mult.vhdl new file mode 100644 index 0000000..0adaa7e --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_alu_mult.vhdl @@ -0,0 +1,1444 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +LIBRARY ieee; USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY ibm; + USE ibm.std_ulogic_support.all; + USE ibm.std_ulogic_unsigned.all; + USE ibm.std_ulogic_function_support.all; +LIBRARY support; + USE support.power_logic_pkg.all; +LIBRARY tri; USE tri.tri_latches_pkg.all; +LIBRARY work; USE work.xuq_pkg.all; + +entity xuq_alu_mult is + generic ( + expand_type : integer := 2; + regmode : integer := 6; + a2mode : integer := 1; + threads : integer := 4; + fxu_synth : integer := 0); + port ( + nclk : in clk_logic; + vdd : inout power_logic; + gnd : inout power_logic; + + d_mode_dc : in std_ulogic; + delay_lclkr_dc : in std_ulogic; + mpw1_dc_b : in std_ulogic; + mpw2_dc_b : in std_ulogic; + func_sl_force : in std_ulogic; + func_sl_thold_0_b : in std_ulogic; + sg_0 : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + dec_alu_rf1_mul_recform : in std_ulogic; + dec_alu_rf1_mul_val : in std_ulogic; + dec_alu_rf1_mul_ret : in std_ulogic; + dec_alu_rf1_mul_sign : in std_ulogic; + dec_alu_rf1_mul_size : in std_ulogic; + dec_alu_rf1_mul_imm : in std_ulogic; + dec_alu_rf1_xer_ov_update : in std_ulogic; + fxa_fxb_ex1_hold_ctr_flush : in std_ulogic; + + ex4_spr_msr_cm : in std_ulogic; + + byp_alu_ex1_mulsrc_0 : in std_ulogic_vector(0 to 2**regmode-1); + byp_alu_ex1_mulsrc_1 : in std_ulogic_vector(0 to 2**regmode-1); + alu_byp_ex5_xer_mul : out std_ulogic_vector(0 to 3); + alu_byp_ex5_cr_mul : out std_ulogic_vector(0 to 4); + + alu_byp_ex5_mul_rt : out std_ulogic_vector(0 to 2**regmode-1); + + alu_ex3_mul_done : out std_ulogic; + alu_ex4_mul_done : out std_ulogic + ); + -- synopsys translate_off + -- synopsys translate_on +end xuq_alu_mult; + +architecture xuq_alu_mult of xuq_alu_mult is + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + subtype s2 is std_ulogic_vector(0 to 1); + subtype s4 is std_ulogic_vector(0 to 3); + subtype s5 is std_ulogic_vector(0 to 4); + subtype s6 is std_ulogic_vector(0 to 5); + + signal ex1_mulstage, ex1_mulstage_shift : std_ulogic_vector(0 to 3); + signal ex1_mul_val : std_ulogic; + signal ex2_ready_stage : std_ulogic_vector(0 to 3); + signal ex5_cmp0_eq : std_ulogic; + signal ex5_cmp0_gt : std_ulogic; + signal ex5_cmp0_lt : std_ulogic; + signal ex5_mul_cr_valid : std_ulogic; + signal ex5_xer_ov : std_ulogic; + signal ex3_recycle_s : std_ulogic_vector(196 to 264); + signal ex3_recycle_c : std_ulogic_vector(196 to 264); + signal ex4_pp5_0s : std_ulogic_vector(196 to 264); + signal ex4_pp5_0c : std_ulogic_vector(196 to 264); + signal ex3_recyc_sh00 : std_ulogic; + signal ex3_recyc_sh32 : std_ulogic; + signal ex3_xtd : std_ulogic; + signal ex3_xtd_196_or : std_ulogic; + signal ex3_xtd_196_and : std_ulogic; + signal ex3_xtd_197_or : std_ulogic; + signal ex3_xtd_197_and : std_ulogic; + signal ex3_xtd_ge1 : std_ulogic; + signal ex3_xtd_ge2 : std_ulogic; + signal ex3_xtd_ge3 : std_ulogic; + signal ex1_bs_sign : std_ulogic; + signal ex1_bd_sign : std_ulogic; + signal ex4_xi : std_ulogic_vector(0 to 63); + signal ex4_yi : std_ulogic_vector(0 to 63); + signal ex4_p : std_ulogic_vector(0 to 63); + signal ex4_g : std_ulogic_vector(1 to 63); + signal ex4_t : std_ulogic_vector(1 to 63); + signal ex4_res : std_ulogic_vector(0 to 63); + signal rslt_lo_act : std_ulogic; + signal ex4_ret_mulhw : std_ulogic; + signal ex4_ret_mullw : std_ulogic; + signal ex4_ret_mulli : std_ulogic; + signal ex4_ret_mulld : std_ulogic; + signal ex4_ret_mulldo : std_ulogic; + signal ex4_ret_mulhd : std_ulogic; + + signal ex5_result : std_ulogic_vector(0 to 63); + signal ex4_all0_test : std_ulogic_vector(0 to 63); + signal ex4_all0_test_mid : std_ulogic; + signal ex4_all1_test : std_ulogic_vector(0 to 63); + signal ex4_all1_test_mid : std_ulogic; + signal ex4_all0 : std_ulogic; + signal ex4_all1 : std_ulogic; + signal ex4_all0_lo : std_ulogic; + signal ex4_all0_hi : std_ulogic; + signal ex4_all1_hi : std_ulogic; + signal ex5_sign_rt_cmp0 : std_ulogic; + signal ex5_eq : std_ulogic; + signal ex4_cout_32 : std_ulogic; + signal ex4_xi_b : std_ulogic_vector(0 to 63); + signal ex4_yi_b : std_ulogic_vector(0 to 63); + signal ex1_mulsrc0_act, ex1_mulsrc1_act : std_ulogic; + signal ex2_bs_lo, ex2_bd_lo : std_ulogic_vector(32 to 63); + signal ex2_act, ex3_act, ex4_act : std_ulogic; + + signal ex1_mul_val_q : std_ulogic; + signal ex2_mulstage_q : std_ulogic_vector(0 to 3); + signal ex3_mulstage_q : std_ulogic_vector(0 to 3); + signal ex4_mulstage_q : std_ulogic_vector(0 to 3); + signal ex5_mulstage_q : std_ulogic_vector(0 to 3); + signal ex1_is_recform_q : std_ulogic; + signal ex2_is_recform_q : std_ulogic; + signal ex3_is_recform_q : std_ulogic; + signal ex4_is_recform_q : std_ulogic; + signal ex5_is_recform_q : std_ulogic; + signal ex1_retsel_q, ex1_retsel_d : std_ulogic_vector(0 to 2); + signal ex2_retsel_q : std_ulogic_vector(0 to 2); + signal ex3_retsel_q : std_ulogic_vector(0 to 2); + signal ex4_retsel_q : std_ulogic_vector(0 to 2); + signal ex1_mul_size_q : std_ulogic; + signal ex1_mul_sign_q : std_ulogic; + signal ex3_mul_done_q, ex3_mul_done_d : std_ulogic; + signal ex4_mul_done_q : std_ulogic; + signal ex5_mul_done_q : std_ulogic; + signal ex1_xer_ov_update_q : std_ulogic; + signal ex2_xer_ov_update_q : std_ulogic; + signal ex3_xer_ov_update_q : std_ulogic; + signal ex4_xer_ov_update_q : std_ulogic; + signal ex5_xer_ov_update_q : std_ulogic; + signal ex2_bs_lo_sign_q, ex2_bs_lo_sign_d : std_ulogic; + signal ex2_bd_lo_sign_q, ex2_bd_lo_sign_d : std_ulogic; + signal ex4_ci_q, ex4_ci_d : std_ulogic; + signal ex5_res_q : std_ulogic_vector(0 to 63); + signal ex5_all0_q : std_ulogic; + signal ex5_all1_q : std_ulogic; + signal ex5_all0_lo_q : std_ulogic; + signal ex5_all0_hi_q : std_ulogic; + signal ex5_all1_hi_q : std_ulogic; + signal carry_32_dly1_q : std_ulogic; + signal all0_lo_dly1_q : std_ulogic; + signal all0_lo_dly2_q : std_ulogic; + signal all0_lo_dly3_q : std_ulogic; + signal rslt_lo_q, rslt_lo_d : std_ulogic_vector(0 to 31); + signal rslt_lo_dly_q, rslt_lo_dly_d : std_ulogic_vector(0 to 31); + signal ex2_mulsrc_0_q, ex1_mulsrc_0 : std_ulogic_vector(0 to 63); + signal ex2_mulsrc_1_q, ex1_mulsrc_1 : std_ulogic_vector(0 to 63); + signal ex5_rslt_hw_q, ex5_rslt_hw_d : std_ulogic_vector(0 to 7); + signal ex5_rslt_ld_li_q, ex5_rslt_ld_li_d : std_ulogic_vector(0 to 7); + signal ex5_rslt_ldo_q, ex5_rslt_ldo_d : std_ulogic_vector(0 to 7); + signal ex5_rslt_lw_hd_q, ex5_rslt_lw_hd_d : std_ulogic_vector(0 to 7); + signal ex5_cmp0_sel_reshi_q, ex5_cmp0_sel_reshi_d : std_ulogic; + signal ex5_cmp0_sel_reslo_q, ex5_cmp0_sel_reslo_d : std_ulogic; + signal ex5_cmp0_sel_reslodly_q, ex5_cmp0_sel_reslodly_d : std_ulogic; + signal ex5_cmp0_sel_reslodly2_q, ex5_cmp0_sel_reslodly2_d : std_ulogic; + signal ex5_eq_sel_all0_b_q, ex5_eq_sel_all0_b_d : std_ulogic; + signal ex5_eq_sel_all0_hi_b_q, ex5_eq_sel_all0_hi_b_d : std_ulogic; + signal ex5_eq_sel_all0_lo_b_q, ex5_eq_sel_all0_lo_b_d : std_ulogic; + signal ex5_eq_sel_all0_lo1_b_q, ex5_eq_sel_all0_lo1_b_d : std_ulogic; + signal ex5_eq_sel_all0_lo2_b_q, ex5_eq_sel_all0_lo2_b_d : std_ulogic; + signal ex5_eq_sel_all0_lo3_b_q, ex5_eq_sel_all0_lo3_b_d : std_ulogic; + signal ex5_ret_mullw_q : std_ulogic; + signal ex5_ret_mulldo_q : std_ulogic; + signal ex5_cmp0_undef_q, ex5_cmp0_undef_d : std_ulogic; + constant ex1_mul_val_offset : integer := 1; + constant ex2_mulstage_offset : integer := ex1_mul_val_offset + 1; + constant ex3_mulstage_offset : integer := ex2_mulstage_offset + ex2_mulstage_q'length; + constant ex4_mulstage_offset : integer := ex3_mulstage_offset + ex3_mulstage_q'length; + constant ex5_mulstage_offset : integer := ex4_mulstage_offset + ex4_mulstage_q'length; + constant ex1_retsel_offset : integer := ex5_mulstage_offset + ex5_mulstage_q'length; + constant ex2_retsel_offset : integer := ex1_retsel_offset + ex1_retsel_q'length; + constant ex3_retsel_offset : integer := ex2_retsel_offset + ex2_retsel_q'length; + constant ex4_retsel_offset : integer := ex3_retsel_offset + ex3_retsel_q'length; + constant ex3_mul_done_offset : integer := ex4_retsel_offset + ex4_retsel_q'length; + constant ex4_mul_done_offset : integer := ex3_mul_done_offset + 1; + constant ex5_mul_done_offset : integer := ex4_mul_done_offset + 1; + constant ex1_is_recform_offset : integer := ex5_mul_done_offset + 1; + constant ex2_is_recform_offset : integer := ex1_is_recform_offset + 1; + constant ex3_is_recform_offset : integer := ex2_is_recform_offset + 1; + constant ex4_is_recform_offset : integer := ex3_is_recform_offset + 1; + constant ex5_is_recform_offset : integer := ex4_is_recform_offset + 1; + constant ex1_xer_ov_update_offset : integer := ex5_is_recform_offset + 1; + constant ex2_xer_ov_update_offset : integer := ex1_xer_ov_update_offset + 1; + constant ex3_xer_ov_update_offset : integer := ex2_xer_ov_update_offset + 1; + constant ex4_xer_ov_update_offset : integer := ex3_xer_ov_update_offset + 1; + constant ex5_xer_ov_update_offset : integer := ex4_xer_ov_update_offset + 1; + constant ex1_mul_size_offset : integer := ex5_xer_ov_update_offset + 1; + constant ex1_mul_sign_offset : integer := ex1_mul_size_offset + 1; + constant ex2_bs_lo_sign_offset : integer := ex1_mul_sign_offset + 1; + constant ex2_bd_lo_sign_offset : integer := ex2_bs_lo_sign_offset + 1; + constant ex5_all0_offset : integer := ex2_bd_lo_sign_offset + 1; + constant ex5_all1_offset : integer := ex5_all0_offset + 1; + constant ex5_all0_lo_offset : integer := ex5_all1_offset + 1; + constant ex5_all0_hi_offset : integer := ex5_all0_lo_offset + 1; + constant ex5_all1_hi_offset : integer := ex5_all0_hi_offset + 1; + constant ex4_ci_offset : integer := ex5_all1_hi_offset + 1; + constant ex5_res_offset : integer := ex4_ci_offset + 1; + constant carry_32_dly1_offset : integer := ex5_res_offset + ex5_res_q'length; + constant all0_lo_dly1_offset : integer := carry_32_dly1_offset + 1; + constant all0_lo_dly2_offset : integer := all0_lo_dly1_offset + 1; + constant all0_lo_dly3_offset : integer := all0_lo_dly2_offset + 1; + constant rslt_lo_offset : integer := all0_lo_dly3_offset + 1; + constant rslt_lo_dly_offset : integer := rslt_lo_offset + rslt_lo_q'length; + constant ex2_mulsrc_0_offset : integer := rslt_lo_dly_offset + rslt_lo_dly_q'length; + constant ex2_mulsrc_1_offset : integer := ex2_mulsrc_0_offset + ex2_mulsrc_0_q'length; + constant ex5_rslt_hw_offset : integer := ex2_mulsrc_1_offset + ex2_mulsrc_1_q'length; + constant ex5_rslt_ld_li_offset : integer := ex5_rslt_hw_offset + ex5_rslt_hw_q'length; + constant ex5_rslt_ldo_offset : integer := ex5_rslt_ld_li_offset + ex5_rslt_ld_li_q'length; + constant ex5_rslt_lw_hd_offset : integer := ex5_rslt_ldo_offset + ex5_rslt_ldo_q'length; + constant ex5_cmp0_sel_reshi_offset : integer := ex5_rslt_lw_hd_offset + ex5_rslt_lw_hd_q'length; + constant ex5_cmp0_sel_reslo_offset : integer := ex5_cmp0_sel_reshi_offset + 1; + constant ex5_cmp0_sel_reslodly_offset : integer := ex5_cmp0_sel_reslo_offset + 1; + constant ex5_cmp0_sel_reslodly2_offset : integer := ex5_cmp0_sel_reslodly_offset + 1; + constant ex5_eq_sel_all0_b_offset : integer := ex5_cmp0_sel_reslodly2_offset + 1; + constant ex5_eq_sel_all0_hi_b_offset : integer := ex5_eq_sel_all0_b_offset + 1; + constant ex5_eq_sel_all0_lo_b_offset : integer := ex5_eq_sel_all0_hi_b_offset + 1; + constant ex5_eq_sel_all0_lo1_b_offset : integer := ex5_eq_sel_all0_lo_b_offset + 1; + constant ex5_eq_sel_all0_lo2_b_offset : integer := ex5_eq_sel_all0_lo1_b_offset + 1; + constant ex5_eq_sel_all0_lo3_b_offset : integer := ex5_eq_sel_all0_lo2_b_offset + 1; + constant ex5_ret_mullw_offset : integer := ex5_eq_sel_all0_lo3_b_offset + 1; + constant ex5_ret_mulldo_offset : integer := ex5_ret_mullw_offset + 1; + constant ex5_cmp0_undef_offset : integer := ex5_ret_mulldo_offset + 1; + constant scan_right : integer := ex5_cmp0_undef_offset + 1; + + signal siv : std_ulogic_vector(0 to scan_right-1); + signal sov : std_ulogic_vector(0 to scan_right-1); + +begin + + ex1_retsel_d <= dec_alu_rf1_mul_ret & dec_alu_rf1_mul_size & dec_alu_rf1_mul_imm; + ex5_mul_cr_valid <= ex5_is_recform_q and ex5_mul_done_q; + + ex1_mul_val <= ex1_mul_val_q and not fxa_fxb_ex1_hold_ctr_flush; + ex1_mulstage_shift <= tidn & gate(ex2_mulstage_q(0 to 2),not(fxa_fxb_ex1_hold_ctr_flush)); + +mult_64b_stagecnt : if regmode = 6 generate + with ex1_mul_val select + ex1_mulstage <= "1000" when '1', + ex1_mulstage_shift when others; +end generate; +mult_32b_stagecnt : if regmode = 5 generate + ex1_mulstage <= "0000"; +end generate; + + + + + + ex2_bs_lo_sign_d <= ((ex1_bs_sign and ex1_mul_sign_q and (ex1_mulstage(1) or ex1_mulstage(3))) and ex1_mul_size_q ) or + ( ex1_bs_sign and ex1_mul_sign_q and not ex1_mul_size_q ) or + ( ex1_bs_sign and ex1_mul_sign_q and ex1_mulstage(1) and ex1_retsel_q(2)); + ex2_bd_lo_sign_d <= ((ex1_bd_sign and ex1_mul_sign_q and (ex1_mulstage(2) or ex1_mulstage(3))) and ex1_mul_size_q ) or + ( ex1_bd_sign and ex1_mul_sign_q and not ex1_mul_size_q ) or + ( ex1_bd_sign and ex1_mul_sign_q and ex1_retsel_q(2)); + + ex1_mulsrc0_act <= or_reduce(ex1_mulstage); + ex1_mulsrc1_act <= ex1_mulstage(0) or ex1_mulstage(2); + + with ex1_mul_val_q select + ex1_mulsrc_0(0 to 63) <= byp_alu_ex1_mulsrc_0(0 to 63) when '1', + ex2_mulsrc_0_q(32 to 63) & ex2_mulsrc_0_q(0 to 31) when others; + + + with ex1_mul_val_q select + ex1_mulsrc_1(0 to 63) <= byp_alu_ex1_mulsrc_1(0 to 63) when '1', + ex2_mulsrc_1_q(32 to 63) & ex2_mulsrc_1_q(0 to 31) when others; + + with (ex1_mulstage(1) or ex1_mulstage(3)) select + ex1_bd_sign <= ex2_mulsrc_1_q(32) when '1', + ex1_mulsrc_1(32) when others; + + + ex1_bs_sign <= ex1_mulsrc_0(32); + ex2_bs_lo <= ex2_mulsrc_0_q(32 to 63); + ex2_bd_lo <= ex2_mulsrc_1_q(32 to 63); + + + mcore : entity work.xuq_alu_mult_core(xuq_alu_mult_core) + generic map (expand_type => expand_type) + port map ( + nclk => nclk, + vdd => vdd, + gnd => gnd, + delay_lclkr_dc => delay_lclkr_dc, + mpw1_dc_b => mpw1_dc_b, + mpw2_dc_b => mpw2_dc_b, + func_sl_force => func_sl_force, + func_sl_thold_0_b => func_sl_thold_0_b, + sg_0 => sg_0, + scan_in => siv(0), + scan_out => sov(0), + ex2_act => ex2_act, + ex3_act => ex3_act, + ex2_bs_lo_sign => ex2_bs_lo_sign_q, + ex2_bd_lo_sign => ex2_bd_lo_sign_q, + ex2_bs_lo => ex2_bs_lo, + ex2_bd_lo => ex2_bd_lo, + ex3_recycle_s => ex3_recycle_s(196 to 264), + ex3_recycle_c => ex3_recycle_c(196 to 263), + ex4_pp5_0s_out => ex4_pp5_0s, + ex4_pp5_0c_out => ex4_pp5_0c(196 to 263)); + + ex4_pp5_0c(264) <= tidn; + + ex2_act <= or_reduce(ex2_mulstage_q); + ex3_act <= or_reduce(ex3_mulstage_q); + ex4_act <= or_reduce(ex4_mulstage_q); + + + ex4_ci_d <= (carry_32_dly1_q and ex3_mulstage_q(2) ) or + (ex4_cout_32 and ((ex3_mulstage_q(3) and ex3_retsel_q(1)) or + (ex3_mulstage_q(1) and ex3_retsel_q(2))) ); + + ex4_xi <= ex4_pp5_0s(200 to 263); + ex4_yi <= ex4_pp5_0c(200 to 263); + + ex4_p <= ex4_xi(0 to 63) xor ex4_yi(0 to 63); + ex4_g <= ex4_xi(1 to 63) and ex4_yi(1 to 63); + ex4_t <= ex4_xi(1 to 63) or ex4_yi(1 to 63); + + ex4_xi_b(0 to 63) <= not ex4_xi(0 to 63) ; + ex4_yi_b(0 to 63) <= not ex4_yi(0 to 63) ; + + cla64ci: entity work.xuq_add(xuq_add) + port map( + x_b(0 to 63) => ex4_xi_b(0 to 63), + y_b(0 to 63) => ex4_yi_b(0 to 63), + ci(8) => ex4_ci_q, + sum(0 to 63) => ex4_res(0 to 63), + cout_32 => ex4_cout_32, + cout_0 => open); + + ex3_recyc_sh32 <= ex3_retsel_q(1) and (ex3_mulstage_q(1) or ex3_mulstage_q(3)); + ex3_recyc_sh00 <= ex3_retsel_q(1) and (ex3_mulstage_q(2)) ; + + ex3_xtd_196_or <= ex4_pp5_0s(196) or ex4_pp5_0c(196); + ex3_xtd_196_and <= ex4_pp5_0s(196) and ex4_pp5_0c(196); + ex3_xtd_197_or <= ex4_pp5_0s(197) or ex4_pp5_0c(197); + ex3_xtd_197_and <= ex4_pp5_0s(197) and ex4_pp5_0c(197); + + ex3_xtd_ge1 <= ex3_xtd_196_or or ex3_xtd_197_or; + ex3_xtd_ge2 <= ex3_xtd_196_or or ex3_xtd_197_and; + ex3_xtd_ge3 <= ex3_xtd_196_and or (ex3_xtd_196_or and ex3_xtd_197_or); + + + ex3_xtd <= (ex3_mulstage_q(1) and ex3_retsel_q(1) and not ex3_xtd_ge1) or + (ex3_mulstage_q(2) and ex3_retsel_q(1) and not ex3_xtd_ge2) or + (ex3_mulstage_q(3) and ex3_retsel_q(1) and not ex3_xtd_ge3) ; + + ex3_recycle_s(196) <= ex4_pp5_0s(196) and (ex3_retsel_q(1) and not ex3_mulstage_q(0)); + ex3_recycle_c(196) <= ex4_pp5_0c(196) and (ex3_retsel_q(1) and not ex3_mulstage_q(0)) ; + + ex3_recycle_s(197) <= ex4_pp5_0s(197) and (ex3_retsel_q(1) and not ex3_mulstage_q(0)) ; + ex3_recycle_c(197) <= ex4_pp5_0c(197) and (ex3_retsel_q(1) and not ex3_mulstage_q(0)) ; + + ex3_recycle_s(198 to 264) <= ( (198 to 264=> ex3_recyc_sh00) and ( ex4_pp5_0s(198 to 264) ) ) or + ( (198 to 264=> ex3_recyc_sh32) and ( (0 to 31=> ex3_xtd) & ex4_pp5_0s(198 to 231) & tidn ) ) ; + + ex3_recycle_c(198 to 264) <= ( (198 to 264=> ex3_recyc_sh00) and ( ex4_pp5_0c(198 to 264) ) ) or + ( (198 to 264=> ex3_recyc_sh32) and ( (0 to 31=> tidn) & ex4_pp5_0c(198 to 231) & tidn ) ) ; + + rslt_lo_act <= ex5_mulstage_q(0) or ex5_mulstage_q(2); + + rslt_lo_d <= ex5_res_q(32 to 63); + rslt_lo_dly_d <= rslt_lo_q; + + + ex4_ret_mulhw <= ex4_retsel_q(0) and not ex4_retsel_q(1) and not ex4_retsel_q(2) ; + ex4_ret_mullw <= not ex4_retsel_q(0) and not ex4_retsel_q(1) and not ex4_retsel_q(2) ; + ex4_ret_mulli <= ex4_retsel_q(2) ; + ex4_ret_mulld <= not ex4_retsel_q(0) and ex4_retsel_q(1) and not ex4_retsel_q(2) and not ex4_xer_ov_update_q; + ex4_ret_mulldo <= not ex4_retsel_q(0) and ex4_retsel_q(1) and not ex4_retsel_q(2) and ex4_xer_ov_update_q; + ex4_ret_mulhd <= ex4_retsel_q(0) and ex4_retsel_q(1) and not ex4_retsel_q(2) ; + + ex5_rslt_hw_d <= (others=>(ex4_ret_mulhw )); + ex5_rslt_ld_li_d <= (others=>(ex4_ret_mulli or ex4_ret_mulld)); + ex5_rslt_ldo_d <= (others=>(ex4_ret_mulldo )); + ex5_rslt_lw_hd_d <= (others=>(ex4_ret_mullw or ex4_ret_mulhd)); + + ex5_result <= (((0 to 31 => '0') & ex5_res_q(0 to 31)) and fanout(ex5_rslt_hw_q ,64)) or + ((ex5_res_q(32 to 63) & rslt_lo_q ) and fanout(ex5_rslt_ld_li_q,64)) or + ((rslt_lo_q & rslt_lo_dly_q ) and fanout(ex5_rslt_ldo_q ,64)) or + ((ex5_res_q ) and fanout(ex5_rslt_lw_hd_q,64)); + + ex4_all0_test(0 to 62) <= ( not ex4_p(0 to 62) and not ex4_t(1 to 63) ) or + ( ex4_p(0 to 62) and ex4_t(1 to 63) ) ; + ex4_all0_test(63) <= ( not ex4_p(63) and not ex4_ci_q ) or + ( ex4_p(63) and ex4_ci_q ) ; + ex4_all0_test_mid <= ( not ex4_p(31) and not ex4_cout_32 ) or + ( ex4_p(31) and ex4_cout_32 ) ; + + ex4_all1_test(0 to 62) <= ( ex4_p(0 to 62) and not ex4_g(1 to 63) ) or + ( not ex4_p(0 to 62) and ex4_g(1 to 63) ); + ex4_all1_test(63) <= ( ex4_p(63) and not ex4_ci_q ) or + ( not ex4_p(63) and ex4_ci_q ); + ex4_all1_test_mid <= ( ex4_p(31) and not ex4_cout_32 ) or + ( not ex4_p(31) and ex4_cout_32 ); + + ex4_all0 <= and_reduce( ex4_all0_test(0 to 63) ); + ex4_all1 <= and_reduce( ex4_all1_test(0 to 63) ); + ex4_all0_lo <= and_reduce( ex4_all0_test(32 to 63) ); + ex4_all0_hi <= and_reduce( ex4_all0_test(0 to 30) & ex4_all0_test_mid ); + ex4_all1_hi <= and_reduce( ex4_all1_test(0 to 30) & ex4_all1_test_mid ); + + + + + ex5_cmp0_undef_d <= ex4_ret_mulhw and ex4_spr_msr_cm; + + ex5_cmp0_sel_reshi_d <= ( ex4_ret_mulhw ) or + ((ex4_ret_mullw or ex4_ret_mulhd) and ex4_spr_msr_cm); + ex5_cmp0_sel_reslo_d <= ((ex4_ret_mullw or ex4_ret_mulhd) and not ex4_spr_msr_cm) or + ( ex4_ret_mulld and ex4_spr_msr_cm); + ex5_cmp0_sel_reslodly_d <= ( ex4_ret_mulld and not ex4_spr_msr_cm) or + ( ex4_ret_mulldo and ex4_spr_msr_cm); + ex5_cmp0_sel_reslodly2_d <= ( ex4_ret_mulldo and not ex4_spr_msr_cm); + + ex5_sign_rt_cmp0 <=(ex5_cmp0_sel_reshi_q and ex5_res_q(0) ) or + (ex5_cmp0_sel_reslo_q and ex5_res_q(32) ) or + (ex5_cmp0_sel_reslodly_q and rslt_lo_q(0) ) or + (ex5_cmp0_sel_reslodly2_q and rslt_lo_dly_q(0) ); + + + + + ex5_eq_sel_all0_hi_b_d <= not( ex4_ret_mulhw ); + + ex5_eq_sel_all0_b_d <= not((ex4_ret_mullw and ex4_spr_msr_cm) or + (ex4_ret_mulhd and ex4_spr_msr_cm)); + + ex5_eq_sel_all0_lo_b_d <= not((ex4_ret_mullw and not ex4_spr_msr_cm) or + (ex4_ret_mulhd and not ex4_spr_msr_cm) or + (ex4_ret_mulld and ex4_spr_msr_cm)); + + ex5_eq_sel_all0_lo1_b_d <= not((ex4_ret_mulldo and ex4_spr_msr_cm)); + + ex5_eq_sel_all0_lo2_b_d <= not( ex4_ret_mulld ); + + ex5_eq_sel_all0_lo3_b_d <= not( ex4_ret_mulldo ); + + + ex5_eq <= (ex5_eq_sel_all0_b_q or ex5_all0_q ) and + (ex5_eq_sel_all0_lo_b_q or ex5_all0_lo_q ) and + (ex5_eq_sel_all0_lo1_b_q or all0_lo_dly1_q) and + (ex5_eq_sel_all0_lo2_b_q or all0_lo_dly2_q) and + (ex5_eq_sel_all0_lo3_b_q or all0_lo_dly3_q) and + (ex5_eq_sel_all0_hi_b_q or ex5_all0_hi_q ); + + ex5_cmp0_eq <= ex5_eq and not ex5_cmp0_undef_q; + ex5_cmp0_gt <= not ex5_sign_rt_cmp0 and not ex5_eq and not ex5_cmp0_undef_q; + ex5_cmp0_lt <= ex5_sign_rt_cmp0 and not ex5_eq and not ex5_cmp0_undef_q; + + + + ex5_xer_ov <= (ex5_ret_mullw_q and ((not ex5_res_q(32) and not ex5_all0_hi_q) or + ( ex5_res_q(32) and not ex5_all1_hi_q))) or + (ex5_ret_mulldo_q and ((not rslt_lo_q(0) and not ex5_all0_q ) or + ( rslt_lo_q(0) and not ex5_all1_q ))); + + + alu_byp_ex5_mul_rt <= ex5_result; + alu_byp_ex5_cr_mul <= ex5_cmp0_lt & ex5_cmp0_gt & ex5_cmp0_eq & (ex5_xer_ov and ex5_xer_ov_update_q) & ex5_mul_cr_valid; + alu_byp_ex5_xer_mul <= ex5_xer_ov & tidn & ex5_xer_ov_update_q & tidn; + + + + ex2_ready_stage(0) <= ( not ex2_retsel_q(1) and not ex2_retsel_q(2) ) ; + ex2_ready_stage(1) <= ( ex2_retsel_q(2) ) ; + ex2_ready_stage(2) <= (not ex2_retsel_q(0) and ex2_retsel_q(1) and not ex2_retsel_q(2) and not ex2_xer_ov_update_q) ; + ex2_ready_stage(3) <= (not ex2_retsel_q(0) and ex2_retsel_q(1) and not ex2_retsel_q(2) and ex2_xer_ov_update_q) or + ( ex2_retsel_q(0) and ex2_retsel_q(1) and not ex2_retsel_q(2) ) ; + + + ex3_mul_done_d <= or_reduce(ex2_ready_stage and ex2_mulstage_q); + + alu_ex3_mul_done <= ex3_mul_done_q; + alu_ex4_mul_done <= ex4_mul_done_q; + + + mark_unused(ex3_recycle_c(264)); + mark_unused(ex5_mulstage_q(1)); + mark_unused(ex5_mulstage_q(3)); + + ex1_mul_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_mul_val_offset), + scout => sov(ex1_mul_val_offset), + din => dec_alu_rf1_mul_val, + dout => ex1_mul_val_q); + ex2_mulstage_latch : tri_rlmreg_p + generic map (width => ex2_mulstage_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_mulstage_offset to ex2_mulstage_offset + ex2_mulstage_q'length-1), + scout => sov(ex2_mulstage_offset to ex2_mulstage_offset + ex2_mulstage_q'length-1), + din => ex1_mulstage, + dout => ex2_mulstage_q); + ex3_mulstage_latch : tri_rlmreg_p + generic map (width => ex3_mulstage_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_mulstage_offset to ex3_mulstage_offset + ex3_mulstage_q'length-1), + scout => sov(ex3_mulstage_offset to ex3_mulstage_offset + ex3_mulstage_q'length-1), + din => ex2_mulstage_q, + dout => ex3_mulstage_q); + ex4_mulstage_latch : tri_rlmreg_p + generic map (width => ex4_mulstage_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_mulstage_offset to ex4_mulstage_offset + ex4_mulstage_q'length-1), + scout => sov(ex4_mulstage_offset to ex4_mulstage_offset + ex4_mulstage_q'length-1), + din => ex3_mulstage_q, + dout => ex4_mulstage_q); + ex5_mulstage_latch : tri_rlmreg_p + generic map (width => ex5_mulstage_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_mulstage_offset to ex5_mulstage_offset + ex5_mulstage_q'length-1), + scout => sov(ex5_mulstage_offset to ex5_mulstage_offset + ex5_mulstage_q'length-1), + din => ex4_mulstage_q, + dout => ex5_mulstage_q); + ex1_retsel_latch : tri_rlmreg_p + generic map (width => ex1_retsel_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => dec_alu_rf1_mul_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_retsel_offset to ex1_retsel_offset + ex1_retsel_q'length-1), + scout => sov(ex1_retsel_offset to ex1_retsel_offset + ex1_retsel_q'length-1), + din => ex1_retsel_d, + dout => ex1_retsel_q); + ex2_retsel_latch : tri_rlmreg_p + generic map (width => ex2_retsel_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => ex1_mul_val_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_retsel_offset to ex2_retsel_offset + ex2_retsel_q'length-1), + scout => sov(ex2_retsel_offset to ex2_retsel_offset + ex2_retsel_q'length-1), + din => ex1_retsel_q, + dout => ex2_retsel_q); + ex3_retsel_latch : tri_rlmreg_p + generic map (width => ex3_retsel_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_retsel_offset to ex3_retsel_offset + ex3_retsel_q'length-1), + scout => sov(ex3_retsel_offset to ex3_retsel_offset + ex3_retsel_q'length-1), + din => ex2_retsel_q, + dout => ex3_retsel_q); + ex4_retsel_latch : tri_rlmreg_p + generic map (width => ex4_retsel_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_retsel_offset to ex4_retsel_offset + ex4_retsel_q'length-1), + scout => sov(ex4_retsel_offset to ex4_retsel_offset + ex4_retsel_q'length-1), + din => ex3_retsel_q, + dout => ex4_retsel_q); + ex3_mul_done_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_mul_done_offset), + scout => sov(ex3_mul_done_offset), + din => ex3_mul_done_d, + dout => ex3_mul_done_q); + ex4_mul_done_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_mul_done_offset), + scout => sov(ex4_mul_done_offset), + din => ex3_mul_done_q, + dout => ex4_mul_done_q); + ex5_mul_done_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_mul_done_offset), + scout => sov(ex5_mul_done_offset), + din => ex4_mul_done_q, + dout => ex5_mul_done_q); + ex1_is_recform_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => dec_alu_rf1_mul_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_recform_offset), + scout => sov(ex1_is_recform_offset), + din => dec_alu_rf1_mul_recform, + dout => ex1_is_recform_q); + ex2_is_recform_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_is_recform_offset), + scout => sov(ex2_is_recform_offset), + din => ex1_is_recform_q, + dout => ex2_is_recform_q); + ex3_is_recform_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_recform_offset), + scout => sov(ex3_is_recform_offset), + din => ex2_is_recform_q, + dout => ex3_is_recform_q); + ex4_is_recform_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_is_recform_offset), + scout => sov(ex4_is_recform_offset), + din => ex3_is_recform_q, + dout => ex4_is_recform_q); + ex5_is_recform_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_is_recform_offset), + scout => sov(ex5_is_recform_offset), + din => ex4_is_recform_q, + dout => ex5_is_recform_q); + ex1_xer_ov_update_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => dec_alu_rf1_mul_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_xer_ov_update_offset), + scout => sov(ex1_xer_ov_update_offset), + din => dec_alu_rf1_xer_ov_update, + dout => ex1_xer_ov_update_q); + ex2_xer_ov_update_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_xer_ov_update_offset), + scout => sov(ex2_xer_ov_update_offset), + din => ex1_xer_ov_update_q, + dout => ex2_xer_ov_update_q); + ex3_xer_ov_update_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_xer_ov_update_offset), + scout => sov(ex3_xer_ov_update_offset), + din => ex2_xer_ov_update_q, + dout => ex3_xer_ov_update_q); + ex4_xer_ov_update_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_xer_ov_update_offset), + scout => sov(ex4_xer_ov_update_offset), + din => ex3_xer_ov_update_q, + dout => ex4_xer_ov_update_q); + ex5_xer_ov_update_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_xer_ov_update_offset), + scout => sov(ex5_xer_ov_update_offset), + din => ex4_xer_ov_update_q, + dout => ex5_xer_ov_update_q); + ex1_mul_size_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => dec_alu_rf1_mul_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_mul_size_offset), + scout => sov(ex1_mul_size_offset), + din => dec_alu_rf1_mul_size, + dout => ex1_mul_size_q); + ex1_mul_sign_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => dec_alu_rf1_mul_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_mul_sign_offset), + scout => sov(ex1_mul_sign_offset), + din => dec_alu_rf1_mul_sign, + dout => ex1_mul_sign_q); + ex2_bs_lo_sign_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_bs_lo_sign_offset), + scout => sov(ex2_bs_lo_sign_offset), + din => ex2_bs_lo_sign_d, + dout => ex2_bs_lo_sign_q); + ex2_bd_lo_sign_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_bd_lo_sign_offset), + scout => sov(ex2_bd_lo_sign_offset), + din => ex2_bd_lo_sign_d, + dout => ex2_bd_lo_sign_q); + ex5_all0_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_all0_offset), + scout => sov(ex5_all0_offset), + din => ex4_all0, + dout => ex5_all0_q); + ex5_all1_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_all1_offset), + scout => sov(ex5_all1_offset), + din => ex4_all1, + dout => ex5_all1_q); + ex5_all0_lo_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_all0_lo_offset), + scout => sov(ex5_all0_lo_offset), + din => ex4_all0_lo, + dout => ex5_all0_lo_q); + ex5_all0_hi_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_all0_hi_offset), + scout => sov(ex5_all0_hi_offset), + din => ex4_all0_hi, + dout => ex5_all0_hi_q); + ex5_all1_hi_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_all1_hi_offset), + scout => sov(ex5_all1_hi_offset), + din => ex4_all1_hi, + dout => ex5_all1_hi_q); + ex4_ci_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_ci_offset), + scout => sov(ex4_ci_offset), + din => ex4_ci_d, + dout => ex4_ci_q); + ex5_res_latch : tri_rlmreg_p + generic map (width => ex5_res_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => ex4_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_res_offset to ex5_res_offset + ex5_res_q'length-1), + scout => sov(ex5_res_offset to ex5_res_offset + ex5_res_q'length-1), + din => ex4_res, + dout => ex5_res_q); + carry_32_dly1_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(carry_32_dly1_offset), + scout => sov(carry_32_dly1_offset), + din => ex4_cout_32, + dout => carry_32_dly1_q); + all0_lo_dly1_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(all0_lo_dly1_offset), + scout => sov(all0_lo_dly1_offset), + din => ex5_all0_lo_q, + dout => all0_lo_dly1_q); + all0_lo_dly2_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(all0_lo_dly2_offset), + scout => sov(all0_lo_dly2_offset), + din => all0_lo_dly1_q, + dout => all0_lo_dly2_q); + all0_lo_dly3_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(all0_lo_dly3_offset), + scout => sov(all0_lo_dly3_offset), + din => all0_lo_dly2_q, + dout => all0_lo_dly3_q); + rslt_lo_latch : tri_rlmreg_p + generic map (width => rslt_lo_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => rslt_lo_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rslt_lo_offset to rslt_lo_offset + rslt_lo_q'length-1), + scout => sov(rslt_lo_offset to rslt_lo_offset + rslt_lo_q'length-1), + din => rslt_lo_d, + dout => rslt_lo_q); + rslt_lo_dly_latch : tri_rlmreg_p + generic map (width => rslt_lo_dly_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rslt_lo_dly_offset to rslt_lo_dly_offset + rslt_lo_dly_q'length-1), + scout => sov(rslt_lo_dly_offset to rslt_lo_dly_offset + rslt_lo_dly_q'length-1), + din => rslt_lo_dly_d, + dout => rslt_lo_dly_q); + ex2_mulsrc_0_latch : tri_rlmreg_p + generic map (width => ex2_mulsrc_0_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_mulsrc0_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_mulsrc_0_offset to ex2_mulsrc_0_offset + ex2_mulsrc_0_q'length-1), + scout => sov(ex2_mulsrc_0_offset to ex2_mulsrc_0_offset + ex2_mulsrc_0_q'length-1), + din => ex1_mulsrc_0, + dout => ex2_mulsrc_0_q); + ex2_mulsrc_1_latch : tri_rlmreg_p + generic map (width => ex2_mulsrc_1_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_mulsrc1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_mulsrc_1_offset to ex2_mulsrc_1_offset + ex2_mulsrc_1_q'length-1), + scout => sov(ex2_mulsrc_1_offset to ex2_mulsrc_1_offset + ex2_mulsrc_1_q'length-1), + din => ex1_mulsrc_1, + dout => ex2_mulsrc_1_q); + ex5_rslt_hw_latch : tri_rlmreg_p + generic map (width => ex5_rslt_hw_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_mul_done_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_rslt_hw_offset to ex5_rslt_hw_offset + ex5_rslt_hw_q'length-1), + scout => sov(ex5_rslt_hw_offset to ex5_rslt_hw_offset + ex5_rslt_hw_q'length-1), + din => ex5_rslt_hw_d, + dout => ex5_rslt_hw_q); + ex5_rslt_ld_li_latch : tri_rlmreg_p + generic map (width => ex5_rslt_ld_li_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_mul_done_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_rslt_ld_li_offset to ex5_rslt_ld_li_offset + ex5_rslt_ld_li_q'length-1), + scout => sov(ex5_rslt_ld_li_offset to ex5_rslt_ld_li_offset + ex5_rslt_ld_li_q'length-1), + din => ex5_rslt_ld_li_d, + dout => ex5_rslt_ld_li_q); + ex5_rslt_ldo_latch : tri_rlmreg_p + generic map (width => ex5_rslt_ldo_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_mul_done_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_rslt_ldo_offset to ex5_rslt_ldo_offset + ex5_rslt_ldo_q'length-1), + scout => sov(ex5_rslt_ldo_offset to ex5_rslt_ldo_offset + ex5_rslt_ldo_q'length-1), + din => ex5_rslt_ldo_d, + dout => ex5_rslt_ldo_q); + ex5_rslt_lw_hd_latch : tri_rlmreg_p + generic map (width => ex5_rslt_lw_hd_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_mul_done_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_rslt_lw_hd_offset to ex5_rslt_lw_hd_offset + ex5_rslt_lw_hd_q'length-1), + scout => sov(ex5_rslt_lw_hd_offset to ex5_rslt_lw_hd_offset + ex5_rslt_lw_hd_q'length-1), + din => ex5_rslt_lw_hd_d, + dout => ex5_rslt_lw_hd_q); + ex5_cmp0_sel_reshi_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_mul_done_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_cmp0_sel_reshi_offset), + scout => sov(ex5_cmp0_sel_reshi_offset), + din => ex5_cmp0_sel_reshi_d, + dout => ex5_cmp0_sel_reshi_q); + ex5_cmp0_sel_reslo_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_mul_done_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_cmp0_sel_reslo_offset), + scout => sov(ex5_cmp0_sel_reslo_offset), + din => ex5_cmp0_sel_reslo_d, + dout => ex5_cmp0_sel_reslo_q); + ex5_cmp0_sel_reslodly_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_mul_done_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_cmp0_sel_reslodly_offset), + scout => sov(ex5_cmp0_sel_reslodly_offset), + din => ex5_cmp0_sel_reslodly_d, + dout => ex5_cmp0_sel_reslodly_q); + ex5_cmp0_sel_reslodly2_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_mul_done_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_cmp0_sel_reslodly2_offset), + scout => sov(ex5_cmp0_sel_reslodly2_offset), + din => ex5_cmp0_sel_reslodly2_d, + dout => ex5_cmp0_sel_reslodly2_q); + ex5_eq_sel_all0_b_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_mul_done_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_eq_sel_all0_b_offset), + scout => sov(ex5_eq_sel_all0_b_offset), + din => ex5_eq_sel_all0_b_d, + dout => ex5_eq_sel_all0_b_q); + ex5_eq_sel_all0_lo_b_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_mul_done_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_eq_sel_all0_lo_b_offset), + scout => sov(ex5_eq_sel_all0_lo_b_offset), + din => ex5_eq_sel_all0_lo_b_d, + dout => ex5_eq_sel_all0_lo_b_q); + ex5_eq_sel_all0_hi_b_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_mul_done_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_eq_sel_all0_hi_b_offset), + scout => sov(ex5_eq_sel_all0_hi_b_offset), + din => ex5_eq_sel_all0_hi_b_d, + dout => ex5_eq_sel_all0_hi_b_q); + ex5_eq_sel_all0_lo1_b_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_mul_done_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_eq_sel_all0_lo1_b_offset), + scout => sov(ex5_eq_sel_all0_lo1_b_offset), + din => ex5_eq_sel_all0_lo1_b_d, + dout => ex5_eq_sel_all0_lo1_b_q); + ex5_eq_sel_all0_lo2_b_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_mul_done_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_eq_sel_all0_lo2_b_offset), + scout => sov(ex5_eq_sel_all0_lo2_b_offset), + din => ex5_eq_sel_all0_lo2_b_d, + dout => ex5_eq_sel_all0_lo2_b_q); + ex5_eq_sel_all0_lo3_b_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_mul_done_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_eq_sel_all0_lo3_b_offset), + scout => sov(ex5_eq_sel_all0_lo3_b_offset), + din => ex5_eq_sel_all0_lo3_b_d, + dout => ex5_eq_sel_all0_lo3_b_q); + ex5_ret_mullw_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_mul_done_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_ret_mullw_offset), + scout => sov(ex5_ret_mullw_offset), + din => ex4_ret_mullw, + dout => ex5_ret_mullw_q); + ex5_ret_mulldo_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_mul_done_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_ret_mulldo_offset), + scout => sov(ex5_ret_mulldo_offset), + din => ex4_ret_mulldo, + dout => ex5_ret_mulldo_q); + ex5_cmp0_undef_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_mul_done_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_cmp0_undef_offset), + scout => sov(ex5_cmp0_undef_offset), + din => ex5_cmp0_undef_d, + dout => ex5_cmp0_undef_q); + + siv(0 to siv'right) <= sov(1 to siv'right) & scan_in; + scan_out <= sov(0); + +end architecture xuq_alu_mult; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_alu_mult_boothdcd.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_alu_mult_boothdcd.vhdl new file mode 100644 index 0000000..46ad50a --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_alu_mult_boothdcd.vhdl @@ -0,0 +1,105 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; +use ieee.std_logic_1164.all; +library ibm; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_ao_support.all; +use ibm.std_ulogic_mux_support.all; + +entity xuq_alu_mult_boothdcd is + port( + i0 : in std_ulogic; + i1 : in std_ulogic; + i2 : in std_ulogic; + s_neg : out std_ulogic; + s_x : out std_ulogic; + s_x2 : out std_ulogic); + + + + + +end xuq_alu_mult_boothdcd; + +architecture xuq_alu_mult_boothdcd of xuq_alu_mult_boothdcd is + + + signal s_add :std_ulogic; + signal sx1_a0_b :std_ulogic; + signal sx1_a1_b :std_ulogic; + signal sx1_t :std_ulogic; + signal sx1_i :std_ulogic; + signal sx2_a0_b :std_ulogic; + signal sx2_a1_b :std_ulogic; + signal sx2_t :std_ulogic; + signal sx2_i :std_ulogic; + signal i0_b, i1_b, i2_b :std_ulogic; + + + + + + + + + +begin + + + +u_0i: i0_b <= not( i0 ); +u_1i: i1_b <= not( i1 ); +u_2i: i2_b <= not( i2 ); + + +u_add: s_add <= not( i0 ); +u_sub: s_neg <= not( s_add ); + +u_sx1_a0: sx1_a0_b <= not( i1_b and i2 ) ; +u_sx1_a1: sx1_a1_b <= not( i1 and i2_b ) ; +u_sx1_t: sx1_t <= not( sx1_a0_b and sx1_a1_b ) ; +u_sx1_i: sx1_i <= not( sx1_t ); +u_sx1_ii: s_x <= not( sx1_i ); + +u_sx2_a0: sx2_a0_b <= not( i0 and i1_b and i2_b ) ; +u_sx2_a1: sx2_a1_b <= not( i0_b and i1 and i2 ) ; +u_sx2_t: sx2_t <= not( sx2_a0_b and sx2_a1_b ) ; +u_sx2_i: sx2_i <= not( sx2_t ); +u_sx2_ii: s_x2 <= not( sx2_i ); + + + + + +end; + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_alu_mult_boothrow.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_alu_mult_boothrow.vhdl new file mode 100644 index 0000000..9994ded --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_alu_mult_boothrow.vhdl @@ -0,0 +1,437 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +LIBRARY ieee; USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY ibm; + USE ibm.std_ulogic_support.all; + USE ibm.std_ulogic_unsigned.all; + USE ibm.std_ulogic_function_support.all; +LIBRARY support; + USE support.power_logic_pkg.all; +LIBRARY tri; USE tri.tri_latches_pkg.all; +LIBRARY clib; + +entity xuq_alu_mult_boothrow is + port( + s_neg : in std_ulogic; + s_x : in std_ulogic; + s_x2 : in std_ulogic; + sign_bit_adj : in std_ulogic; + x : in std_ulogic_vector(0 to 31); + q : out std_ulogic_vector(0 to 32); + hot_one : out std_ulogic; + vdd : inout power_logic; + gnd : inout power_logic + ); +-- synopsys translate_off +-- synopsys translate_on +end xuq_alu_mult_boothrow; + +architecture xuq_alu_mult_boothrow of xuq_alu_mult_boothrow is + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal left : std_ulogic_vector(1 to 32); + + + + + +begin + + + + u00: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => sign_bit_adj, + RIGHT => left(1), + LEFT => open, + Q => q(0)); + + u01: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(0), + RIGHT => left(2), + LEFT => left(1), + Q => q(1)); + + u02: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(1), + RIGHT => left(3), + LEFT => left(2), + Q => q(2)); + + u03: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(2), + RIGHT => left(4), + LEFT => left(3), + Q => q(3)); + + u04: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(3), + RIGHT => left(5), + LEFT => left(4), + Q => q(4)); + + u05: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(4), + RIGHT => left(6), + LEFT => left(5), + Q => q(5)); + + u06: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(5), + RIGHT => left(7), + LEFT => left(6), + Q => q(6)); + + u07: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(6), + RIGHT => left(8), + LEFT => left(7), + Q => q(7)); + + u08: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(7), + RIGHT => left(9), + LEFT => left(8), + Q => q(8)); + + u09: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(8), + RIGHT => left(10), + LEFT => left(9), + Q => q(9)); + + u10: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(9), + RIGHT => left(11), + LEFT => left(10), + Q => q(10)); + + u11: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(10), + RIGHT => left(12), + LEFT => left(11), + Q => q(11)); + + u12: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(11), + RIGHT => left(13), + LEFT => left(12), + Q => q(12)); + + u13: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(12), + RIGHT => left(14), + LEFT => left(13), + Q => q(13)); + + u14: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(13), + RIGHT => left(15), + LEFT => left(14), + Q => q(14)); + + u15: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(14), + RIGHT => left(16), + LEFT => left(15), + Q => q(15)); + + u16: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(15), + RIGHT => left(17), + LEFT => left(16), + Q => q(16)); + + u17: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(16), + RIGHT => left(18), + LEFT => left(17), + Q => q(17)); + + u18: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(17), + RIGHT => left(19), + LEFT => left(18), + Q => q(18)); + + u19: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(18), + RIGHT => left(20), + LEFT => left(19), + Q => q(19)); + + u20: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(19), + RIGHT => left(21), + LEFT => left(20), + Q => q(20)); + + u21: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(20), + RIGHT => left(22), + LEFT => left(21), + Q => q(21)); + + u22: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(21), + RIGHT => left(23), + LEFT => left(22), + Q => q(22)); + + u23: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(22), + RIGHT => left(24), + LEFT => left(23), + Q => q(23)); + + u24: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(23), + RIGHT => left(25), + LEFT => left(24), + Q => q(24)); + + u25: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(24), + RIGHT => left(26), + LEFT => left(25), + Q => q(25)); + + u26: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(25), + RIGHT => left(27), + LEFT => left(26), + Q => q(26)); + + u27: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(26), + RIGHT => left(28), + LEFT => left(27), + Q => q(27)); + + u28: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(27), + RIGHT => left(29), + LEFT => left(28), + Q => q(28)); + + u29: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(28), + RIGHT => left(30), + LEFT => left(29), + Q => q(29)); + + u30: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(29), + RIGHT => left(31), + LEFT => left(30), + Q => q(30)); + + u31: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(30), + RIGHT => left(32), + LEFT => left(31), + Q => q(31)); + + u32: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(31), + RIGHT => s_neg, + LEFT => left(32), + Q => q(32)); + + + u33: hot_one <= s_neg and (s_x or s_x2) ; +end; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_alu_mult_core.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_alu_mult_core.vhdl new file mode 100644 index 0000000..26b8c9e --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_alu_mult_core.vhdl @@ -0,0 +1,5736 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +LIBRARY ieee; USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY ibm; + USE ibm.std_ulogic_support.all; + USE ibm.std_ulogic_unsigned.all; + USE ibm.std_ulogic_function_support.all; +LIBRARY support; + USE support.power_logic_pkg.all; +LIBRARY tri; USE tri.tri_latches_pkg.all; +LIBRARY clib ; +LIBRARY work; USE work.xuq_pkg.all; + + + +entity xuq_alu_mult_core is generic ( expand_type: integer := 2 ); port ( + + nclk :in clk_logic; + vdd :inout power_logic; + gnd :inout power_logic; + delay_lclkr_dc :in std_ulogic; + mpw1_dc_b :in std_ulogic; + mpw2_dc_b :in std_ulogic; + func_sl_force :in std_ulogic; + func_sl_thold_0_b :in std_ulogic; + sg_0 :in std_ulogic; + scan_in :in std_ulogic; + scan_out :out std_ulogic; + + ex2_act :in std_ulogic; + ex3_act :in std_ulogic; + + ex2_bs_lo_sign :in std_ulogic; + ex2_bd_lo_sign :in std_ulogic; + ex2_bd_lo :in std_ulogic_vector(0 to 31); + ex2_bs_lo :in std_ulogic_vector(0 to 31); + + ex3_recycle_s :in std_ulogic_vector(196 to 264); + ex3_recycle_c :in std_ulogic_vector(196 to 263); + + ex4_pp5_0s_out :out std_ulogic_vector(196 to 264); + ex4_pp5_0c_out :out std_ulogic_vector(196 to 263) + ); + -- synopsys translate_off + -- synopsys translate_on +end xuq_alu_mult_core; + +architecture xuq_alu_mult_core of xuq_alu_mult_core is + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal ex3_d1clk, ex4_d1clk :std_ulogic ; + signal ex3_d2clk, ex4_d2clk :std_ulogic ; + signal ex3_lclk , ex4_lclk :clk_logic ; + + + signal ex3_pp2_0c_din, ex3_pp2_0c, ex3_pp2_0c_q_b, ex3_pp2_0c_lat_so , ex3_pp2_0c_lat_si :std_ulogic_vector(198 to 240) ; + signal ex3_pp2_0s_din, ex3_pp2_0s, ex3_pp2_0s_q_b, ex3_pp2_0s_lat_so , ex3_pp2_0s_lat_si :std_ulogic_vector(198 to 242) ; + signal ex3_pp2_1c_din, ex3_pp2_1c, ex3_pp2_1c_x, ex3_pp2_1c_x_b, ex3_pp2_1c_q_b, ex3_pp2_1c_lat_so , ex3_pp2_1c_lat_si :std_ulogic_vector(208 to 252) ; + signal ex3_pp2_1s_din, ex3_pp2_1s, ex3_pp2_1s_x, ex3_pp2_1s_x_b, ex3_pp2_1s_q_b, ex3_pp2_1s_lat_so , ex3_pp2_1s_lat_si :std_ulogic_vector(208 to 254) ; + signal ex3_pp2_2c_din, ex3_pp2_2c, ex3_pp2_2c_x, ex3_pp2_2c_x_b, ex3_pp2_2c_q_b, ex3_pp2_2c_lat_so , ex3_pp2_2c_lat_si :std_ulogic_vector(220 to 263) ; + signal ex3_pp2_2s_din, ex3_pp2_2s, ex3_pp2_2s_x, ex3_pp2_2s_x_b, ex3_pp2_2s_q_b, ex3_pp2_2s_lat_so , ex3_pp2_2s_lat_si :std_ulogic_vector(220 to 264) ; + + + signal ex4_pp5_0s_din, ex4_pp5_0s, ex4_pp5_0s_q_b, ex4_pp5_0s_lat_so , ex4_pp5_0s_lat_si :std_ulogic_vector(196 to 264); + signal ex4_pp5_0c_din, ex4_pp5_0c, ex4_pp5_0c_q_b, ex4_pp5_0c_lat_so , ex4_pp5_0c_lat_si :std_ulogic_vector(196 to 263); + + signal ex2_bd_neg, ex2_bd_sh0, ex2_bd_sh1 :std_ulogic_vector(0 to 16) ; + + signal ex2_br_00_out :std_ulogic_vector(0 to 32); + signal ex2_br_01_out :std_ulogic_vector(0 to 32); + signal ex2_br_02_out :std_ulogic_vector(0 to 32); + signal ex2_br_03_out :std_ulogic_vector(0 to 32); + signal ex2_br_04_out :std_ulogic_vector(0 to 32); + signal ex2_br_05_out :std_ulogic_vector(0 to 32); + signal ex2_br_06_out :std_ulogic_vector(0 to 32); + signal ex2_br_07_out :std_ulogic_vector(0 to 32); + signal ex2_br_08_out :std_ulogic_vector(0 to 32); + signal ex2_br_09_out :std_ulogic_vector(0 to 32); + signal ex2_br_10_out :std_ulogic_vector(0 to 32); + signal ex2_br_11_out :std_ulogic_vector(0 to 32); + signal ex2_br_12_out :std_ulogic_vector(0 to 32); + signal ex2_br_13_out :std_ulogic_vector(0 to 32); + signal ex2_br_14_out :std_ulogic_vector(0 to 32); + signal ex2_br_15_out :std_ulogic_vector(0 to 32); + signal ex2_br_16_out :std_ulogic_vector(0 to 32); + signal ex2_hot_one :std_ulogic_vector(0 to 16); + + + signal ex2_pp1_0c :std_ulogic_vector(199 to 234) ; + signal ex2_pp1_0s :std_ulogic_vector(198 to 236) ; + signal ex2_pp1_1c :std_ulogic_vector(203 to 240) ; + signal ex2_pp1_1s :std_ulogic_vector(202 to 242) ; + signal ex2_pp1_2c :std_ulogic_vector(209 to 246) ; + signal ex2_pp1_2s :std_ulogic_vector(208 to 248) ; + signal ex2_pp1_3c :std_ulogic_vector(215 to 252) ; + signal ex2_pp1_3s :std_ulogic_vector(214 to 254) ; + signal ex2_pp1_4c :std_ulogic_vector(221 to 258) ; + signal ex2_pp1_4s :std_ulogic_vector(220 to 260) ; + signal ex2_pp1_5c :std_ulogic_vector(227 to 264) ; + signal ex2_pp1_5s :std_ulogic_vector(226 to 264) ; + + + + + + + signal ex2_pp2_0c :std_ulogic_vector(198 to 240) ; + signal ex2_pp2_0s :std_ulogic_vector(198 to 242) ; + signal ex2_pp2_1c :std_ulogic_vector(208 to 252) ; + signal ex2_pp2_1s :std_ulogic_vector(208 to 254) ; + signal ex2_pp2_2c :std_ulogic_vector(220 to 263) ; + signal ex2_pp2_2s :std_ulogic_vector(220 to 264) ; + + signal ex2_pp2_0k :std_ulogic_vector(201 to 234) ; + signal ex2_pp2_1k :std_ulogic_vector(213 to 246) ; + signal ex2_pp2_2k :std_ulogic_vector(225 to 258) ; + + + signal ex3_pp3_0c :std_ulogic_vector(197 to 242) ; + signal ex3_pp3_0s :std_ulogic_vector(198 to 252) ; + signal ex3_pp3_1c :std_ulogic_vector(219 to 262) ; + signal ex3_pp3_1s :std_ulogic_vector(208 to 264) ; + + signal ex3_pp4_0k :std_ulogic_vector(207 to 242); + signal ex3_pp4_0c :std_ulogic_vector(197 to 262); + signal ex3_pp4_0s :std_ulogic_vector(197 to 264); + + signal ex3_pp5_0k :std_ulogic_vector(196 to 262); + signal ex3_pp5_0c :std_ulogic_vector(195 to 263); + signal ex3_pp5_0s :std_ulogic_vector(196 to 264); + signal ex2_br_00_add :std_ulogic; + signal ex2_br_01_add :std_ulogic; + signal ex2_br_02_add :std_ulogic; + signal ex2_br_03_add :std_ulogic; + signal ex2_br_04_add :std_ulogic; + signal ex2_br_05_add :std_ulogic; + signal ex2_br_06_add :std_ulogic; + signal ex2_br_07_add :std_ulogic; + signal ex2_br_08_add :std_ulogic; + signal ex2_br_09_add :std_ulogic; + signal ex2_br_10_add :std_ulogic; + signal ex2_br_11_add :std_ulogic; + signal ex2_br_12_add :std_ulogic; + signal ex2_br_13_add :std_ulogic; + signal ex2_br_14_add :std_ulogic; + signal ex2_br_15_add :std_ulogic; + signal ex2_br_16_add :std_ulogic; + signal ex2_br_16_sub :std_ulogic; + + signal ex2_pp0_00 :std_ulogic_vector(198 to 234) ; + signal ex2_pp0_01 :std_ulogic_vector(200 to 236) ; + signal ex2_pp0_02 :std_ulogic_vector(202 to 238) ; + signal ex2_pp0_03 :std_ulogic_vector(204 to 240) ; + signal ex2_pp0_04 :std_ulogic_vector(206 to 242) ; + signal ex2_pp0_05 :std_ulogic_vector(208 to 244) ; + signal ex2_pp0_06 :std_ulogic_vector(210 to 246) ; + signal ex2_pp0_07 :std_ulogic_vector(212 to 248) ; + signal ex2_pp0_08 :std_ulogic_vector(214 to 250) ; + signal ex2_pp0_09 :std_ulogic_vector(216 to 252) ; + signal ex2_pp0_10 :std_ulogic_vector(218 to 254) ; + signal ex2_pp0_11 :std_ulogic_vector(220 to 256) ; + signal ex2_pp0_12 :std_ulogic_vector(222 to 258) ; + signal ex2_pp0_13 :std_ulogic_vector(224 to 260) ; + signal ex2_pp0_14 :std_ulogic_vector(226 to 262) ; + signal ex2_pp0_15 :std_ulogic_vector(228 to 264) ; + signal ex2_pp0_16 :std_ulogic_vector(229 to 264) ; + signal ex2_pp0_17 :std_ulogic_vector(232 to 232) ; + + signal ex2_br_00_sign_xor :std_ulogic; + signal ex2_br_01_sign_xor :std_ulogic; + signal ex2_br_02_sign_xor :std_ulogic; + signal ex2_br_03_sign_xor :std_ulogic; + signal ex2_br_04_sign_xor :std_ulogic; + signal ex2_br_05_sign_xor :std_ulogic; + signal ex2_br_06_sign_xor :std_ulogic; + signal ex2_br_07_sign_xor :std_ulogic; + signal ex2_br_08_sign_xor :std_ulogic; + signal ex2_br_09_sign_xor :std_ulogic; + signal ex2_br_10_sign_xor :std_ulogic; + signal ex2_br_11_sign_xor :std_ulogic; + signal ex2_br_12_sign_xor :std_ulogic; + signal ex2_br_13_sign_xor :std_ulogic; + signal ex2_br_14_sign_xor :std_ulogic; + signal ex2_br_15_sign_xor :std_ulogic; + signal ex2_br_16_sign_xor :std_ulogic; + + + + + + + + + + + signal version :std_ulogic_vector(0 to 7) ; + +begin + + version <= "00010001" ; + + + bd_00: entity work.xuq_alu_mult_boothdcd port map ( + i0 => ex2_bd_lo_sign , + i1 => ex2_bd_lo(0) , + i2 => ex2_bd_lo(1) , + s_neg => ex2_bd_neg(0) , + s_x => ex2_bd_sh0(0) , + s_x2 => ex2_bd_sh1(0) ); + bd_01: entity work.xuq_alu_mult_boothdcd port map ( + i0 => ex2_bd_lo(1) , + i1 => ex2_bd_lo(2) , + i2 => ex2_bd_lo(3) , + s_neg => ex2_bd_neg(1) , + s_x => ex2_bd_sh0(1) , + s_x2 => ex2_bd_sh1(1) ); + bd_02: entity work.xuq_alu_mult_boothdcd port map ( + i0 => ex2_bd_lo(3) , + i1 => ex2_bd_lo(4) , + i2 => ex2_bd_lo(5) , + s_neg => ex2_bd_neg(2) , + s_x => ex2_bd_sh0(2) , + s_x2 => ex2_bd_sh1(2) ); + bd_03: entity work.xuq_alu_mult_boothdcd port map ( + i0 => ex2_bd_lo(5) , + i1 => ex2_bd_lo(6) , + i2 => ex2_bd_lo(7) , + s_neg => ex2_bd_neg(3) , + s_x => ex2_bd_sh0(3) , + s_x2 => ex2_bd_sh1(3) ); + bd_04: entity work.xuq_alu_mult_boothdcd port map ( + i0 => ex2_bd_lo(7) , + i1 => ex2_bd_lo(8) , + i2 => ex2_bd_lo(9) , + s_neg => ex2_bd_neg(4) , + s_x => ex2_bd_sh0(4) , + s_x2 => ex2_bd_sh1(4) ); + bd_05: entity work.xuq_alu_mult_boothdcd port map ( + i0 => ex2_bd_lo(9) , + i1 => ex2_bd_lo(10) , + i2 => ex2_bd_lo(11) , + s_neg => ex2_bd_neg(5) , + s_x => ex2_bd_sh0(5) , + s_x2 => ex2_bd_sh1(5) ); + bd_06: entity work.xuq_alu_mult_boothdcd port map ( + i0 => ex2_bd_lo(11) , + i1 => ex2_bd_lo(12) , + i2 => ex2_bd_lo(13) , + s_neg => ex2_bd_neg(6) , + s_x => ex2_bd_sh0(6) , + s_x2 => ex2_bd_sh1(6) ); + bd_07: entity work.xuq_alu_mult_boothdcd port map ( + i0 => ex2_bd_lo(13) , + i1 => ex2_bd_lo(14) , + i2 => ex2_bd_lo(15) , + s_neg => ex2_bd_neg(7) , + s_x => ex2_bd_sh0(7) , + s_x2 => ex2_bd_sh1(7) ); + bd_08: entity work.xuq_alu_mult_boothdcd port map ( + i0 => ex2_bd_lo(15) , + i1 => ex2_bd_lo(16) , + i2 => ex2_bd_lo(17) , + s_neg => ex2_bd_neg(8) , + s_x => ex2_bd_sh0(8) , + s_x2 => ex2_bd_sh1(8) ); + bd_09: entity work.xuq_alu_mult_boothdcd port map ( + i0 => ex2_bd_lo(17) , + i1 => ex2_bd_lo(18) , + i2 => ex2_bd_lo(19) , + s_neg => ex2_bd_neg(9) , + s_x => ex2_bd_sh0(9) , + s_x2 => ex2_bd_sh1(9) ); + bd_10: entity work.xuq_alu_mult_boothdcd port map ( + i0 => ex2_bd_lo(19) , + i1 => ex2_bd_lo(20) , + i2 => ex2_bd_lo(21) , + s_neg => ex2_bd_neg(10) , + s_x => ex2_bd_sh0(10) , + s_x2 => ex2_bd_sh1(10) ); + bd_11: entity work.xuq_alu_mult_boothdcd port map ( + i0 => ex2_bd_lo(21) , + i1 => ex2_bd_lo(22) , + i2 => ex2_bd_lo(23) , + s_neg => ex2_bd_neg(11) , + s_x => ex2_bd_sh0(11) , + s_x2 => ex2_bd_sh1(11) ); + bd_12: entity work.xuq_alu_mult_boothdcd port map ( + i0 => ex2_bd_lo(23) , + i1 => ex2_bd_lo(24) , + i2 => ex2_bd_lo(25) , + s_neg => ex2_bd_neg(12) , + s_x => ex2_bd_sh0(12) , + s_x2 => ex2_bd_sh1(12) ); + bd_13: entity work.xuq_alu_mult_boothdcd port map ( + i0 => ex2_bd_lo(25) , + i1 => ex2_bd_lo(26) , + i2 => ex2_bd_lo(27) , + s_neg => ex2_bd_neg(13) , + s_x => ex2_bd_sh0(13) , + s_x2 => ex2_bd_sh1(13) ); + bd_14: entity work.xuq_alu_mult_boothdcd port map ( + i0 => ex2_bd_lo(27) , + i1 => ex2_bd_lo(28) , + i2 => ex2_bd_lo(29) , + s_neg => ex2_bd_neg(14) , + s_x => ex2_bd_sh0(14) , + s_x2 => ex2_bd_sh1(14) ); + bd_15: entity work.xuq_alu_mult_boothdcd port map ( + i0 => ex2_bd_lo(29) , + i1 => ex2_bd_lo(30) , + i2 => ex2_bd_lo(31) , + s_neg => ex2_bd_neg(15) , + s_x => ex2_bd_sh0(15) , + s_x2 => ex2_bd_sh1(15) ); + bd_16: entity work.xuq_alu_mult_boothdcd port map ( + i0 => ex2_bd_lo(31) , + i1 => tidn , + i2 => tidn , + s_neg => ex2_bd_neg(16) , + s_x => ex2_bd_sh0(16) , + s_x2 => ex2_bd_sh1(16) ); + + +br_00: entity work.xuq_alu_mult_boothrow port map ( + vdd => vdd, + gnd => gnd, + s_neg => ex2_bd_neg(0) , + s_x => ex2_bd_sh0(0) , + s_x2 => ex2_bd_sh1(0) , + sign_bit_adj => ex2_bs_lo_sign , + x => ex2_bs_lo(0 to 31) , + q => ex2_br_00_out(0 to 32) , + hot_one => ex2_hot_one(0) ); + br_01: entity work.xuq_alu_mult_boothrow port map ( + vdd => vdd, + gnd => gnd, + s_neg => ex2_bd_neg(1) , + s_x => ex2_bd_sh0(1) , + s_x2 => ex2_bd_sh1(1) , + sign_bit_adj => ex2_bs_lo_sign , + x => ex2_bs_lo(0 to 31) , + q => ex2_br_01_out(0 to 32) , + hot_one => ex2_hot_one(1) ); + br_02: entity work.xuq_alu_mult_boothrow port map ( + vdd => vdd, + gnd => gnd, + s_neg => ex2_bd_neg(2) , + s_x => ex2_bd_sh0(2) , + s_x2 => ex2_bd_sh1(2) , + sign_bit_adj => ex2_bs_lo_sign , + x => ex2_bs_lo(0 to 31) , + q => ex2_br_02_out(0 to 32) , + hot_one => ex2_hot_one(2) ); + br_03: entity work.xuq_alu_mult_boothrow port map ( + vdd => vdd, + gnd => gnd, + s_neg => ex2_bd_neg(3) , + s_x => ex2_bd_sh0(3) , + s_x2 => ex2_bd_sh1(3) , + sign_bit_adj => ex2_bs_lo_sign , + x => ex2_bs_lo(0 to 31) , + q => ex2_br_03_out(0 to 32) , + hot_one => ex2_hot_one(3) ); + br_04: entity work.xuq_alu_mult_boothrow port map ( + vdd => vdd, + gnd => gnd, + s_neg => ex2_bd_neg(4) , + s_x => ex2_bd_sh0(4) , + s_x2 => ex2_bd_sh1(4) , + sign_bit_adj => ex2_bs_lo_sign , + x => ex2_bs_lo(0 to 31) , + q => ex2_br_04_out(0 to 32) , + hot_one => ex2_hot_one(4) ); + br_05: entity work.xuq_alu_mult_boothrow port map ( + vdd => vdd, + gnd => gnd, + s_neg => ex2_bd_neg(5) , + s_x => ex2_bd_sh0(5) , + s_x2 => ex2_bd_sh1(5) , + sign_bit_adj => ex2_bs_lo_sign , + x => ex2_bs_lo(0 to 31) , + q => ex2_br_05_out(0 to 32) , + hot_one => ex2_hot_one(5) ); + br_06: entity work.xuq_alu_mult_boothrow port map ( + vdd => vdd, + gnd => gnd, + s_neg => ex2_bd_neg(6) , + s_x => ex2_bd_sh0(6) , + s_x2 => ex2_bd_sh1(6) , + sign_bit_adj => ex2_bs_lo_sign , + x => ex2_bs_lo(0 to 31) , + q => ex2_br_06_out(0 to 32) , + hot_one => ex2_hot_one(6) ); + br_07: entity work.xuq_alu_mult_boothrow port map ( + vdd => vdd, + gnd => gnd, + s_neg => ex2_bd_neg(7) , + s_x => ex2_bd_sh0(7) , + s_x2 => ex2_bd_sh1(7) , + sign_bit_adj => ex2_bs_lo_sign , + x => ex2_bs_lo(0 to 31) , + q => ex2_br_07_out(0 to 32) , + hot_one => ex2_hot_one(7) ); + br_08: entity work.xuq_alu_mult_boothrow port map ( + vdd => vdd, + gnd => gnd, + s_neg => ex2_bd_neg(8) , + s_x => ex2_bd_sh0(8) , + s_x2 => ex2_bd_sh1(8) , + sign_bit_adj => ex2_bs_lo_sign , + x => ex2_bs_lo(0 to 31) , + q => ex2_br_08_out(0 to 32) , + hot_one => ex2_hot_one(8) ); + br_09: entity work.xuq_alu_mult_boothrow port map ( + vdd => vdd, + gnd => gnd, + s_neg => ex2_bd_neg(9) , + s_x => ex2_bd_sh0(9) , + s_x2 => ex2_bd_sh1(9) , + sign_bit_adj => ex2_bs_lo_sign , + x => ex2_bs_lo(0 to 31) , + q => ex2_br_09_out(0 to 32) , + hot_one => ex2_hot_one(9) ); + br_10: entity work.xuq_alu_mult_boothrow port map ( + vdd => vdd, + gnd => gnd, + s_neg => ex2_bd_neg(10) , + s_x => ex2_bd_sh0(10) , + s_x2 => ex2_bd_sh1(10) , + sign_bit_adj => ex2_bs_lo_sign , + x => ex2_bs_lo(0 to 31) , + q => ex2_br_10_out(0 to 32) , + hot_one => ex2_hot_one(10) ); + br_11: entity work.xuq_alu_mult_boothrow port map ( + vdd => vdd, + gnd => gnd, + s_neg => ex2_bd_neg(11) , + s_x => ex2_bd_sh0(11) , + s_x2 => ex2_bd_sh1(11) , + sign_bit_adj => ex2_bs_lo_sign , + x => ex2_bs_lo(0 to 31) , + q => ex2_br_11_out(0 to 32) , + hot_one => ex2_hot_one(11) ); + br_12: entity work.xuq_alu_mult_boothrow port map ( + vdd => vdd, + gnd => gnd, + s_neg => ex2_bd_neg(12) , + s_x => ex2_bd_sh0(12) , + s_x2 => ex2_bd_sh1(12) , + sign_bit_adj => ex2_bs_lo_sign , + x => ex2_bs_lo(0 to 31) , + q => ex2_br_12_out(0 to 32) , + hot_one => ex2_hot_one(12) ); + br_13: entity work.xuq_alu_mult_boothrow port map ( + vdd => vdd, + gnd => gnd, + s_neg => ex2_bd_neg(13) , + s_x => ex2_bd_sh0(13) , + s_x2 => ex2_bd_sh1(13) , + sign_bit_adj => ex2_bs_lo_sign , + x => ex2_bs_lo(0 to 31) , + q => ex2_br_13_out(0 to 32) , + hot_one => ex2_hot_one(13) ); + br_14: entity work.xuq_alu_mult_boothrow port map ( + vdd => vdd, + gnd => gnd, + s_neg => ex2_bd_neg(14) , + s_x => ex2_bd_sh0(14) , + s_x2 => ex2_bd_sh1(14) , + sign_bit_adj => ex2_bs_lo_sign , + x => ex2_bs_lo(0 to 31) , + q => ex2_br_14_out(0 to 32) , + hot_one => ex2_hot_one(14) ); + br_15: entity work.xuq_alu_mult_boothrow port map ( + vdd => vdd, + gnd => gnd, + s_neg => ex2_bd_neg(15) , + s_x => ex2_bd_sh0(15) , + s_x2 => ex2_bd_sh1(15) , + sign_bit_adj => ex2_bs_lo_sign , + x => ex2_bs_lo(0 to 31) , + q => ex2_br_15_out(0 to 32) , + hot_one => ex2_hot_one(15) ); + br_16: entity work.xuq_alu_mult_boothrow port map ( + vdd => vdd, + gnd => gnd, + s_neg => ex2_bd_neg(16) , + s_x => ex2_bd_sh0(16) , + s_x2 => ex2_bd_sh1(16) , + sign_bit_adj => ex2_bs_lo_sign , + x => ex2_bs_lo(0 to 31) , + q => ex2_br_16_out(0 to 32) , + hot_one => ex2_hot_one(16) ); + + + + + + + + u_br_00_sx: ex2_br_00_sign_xor <= ex2_bs_lo_sign xor ex2_bd_neg(0) ; + u_br_01_sx: ex2_br_01_sign_xor <= ex2_bs_lo_sign xor ex2_bd_neg(1) ; + u_br_02_sx: ex2_br_02_sign_xor <= ex2_bs_lo_sign xor ex2_bd_neg(2) ; + u_br_03_sx: ex2_br_03_sign_xor <= ex2_bs_lo_sign xor ex2_bd_neg(3) ; + u_br_04_sx: ex2_br_04_sign_xor <= ex2_bs_lo_sign xor ex2_bd_neg(4) ; + u_br_05_sx: ex2_br_05_sign_xor <= ex2_bs_lo_sign xor ex2_bd_neg(5) ; + u_br_06_sx: ex2_br_06_sign_xor <= ex2_bs_lo_sign xor ex2_bd_neg(6) ; + u_br_07_sx: ex2_br_07_sign_xor <= ex2_bs_lo_sign xor ex2_bd_neg(7) ; + u_br_08_sx: ex2_br_08_sign_xor <= ex2_bs_lo_sign xor ex2_bd_neg(8) ; + u_br_09_sx: ex2_br_09_sign_xor <= ex2_bs_lo_sign xor ex2_bd_neg(9) ; + u_br_10_sx: ex2_br_10_sign_xor <= ex2_bs_lo_sign xor ex2_bd_neg(10) ; + u_br_11_sx: ex2_br_11_sign_xor <= ex2_bs_lo_sign xor ex2_bd_neg(11) ; + u_br_12_sx: ex2_br_12_sign_xor <= ex2_bs_lo_sign xor ex2_bd_neg(12) ; + u_br_13_sx: ex2_br_13_sign_xor <= ex2_bs_lo_sign xor ex2_bd_neg(13) ; + u_br_14_sx: ex2_br_14_sign_xor <= ex2_bs_lo_sign xor ex2_bd_neg(14) ; + u_br_15_sx: ex2_br_15_sign_xor <= ex2_bs_lo_sign xor ex2_bd_neg(15) ; + u_br_16_sx: ex2_br_16_sign_xor <= ex2_bs_lo_sign xor ex2_bd_neg(16) ; + + + + u_br_00_add: ex2_br_00_add <= not( ex2_br_00_sign_xor and (ex2_bd_sh0(0) or ex2_bd_sh1(0) ) ) ; + u_br_01_add: ex2_br_01_add <= not( ex2_br_01_sign_xor and (ex2_bd_sh0(1) or ex2_bd_sh1(1) ) ) ; + u_br_02_add: ex2_br_02_add <= not( ex2_br_02_sign_xor and (ex2_bd_sh0(2) or ex2_bd_sh1(2) ) ) ; + u_br_03_add: ex2_br_03_add <= not( ex2_br_03_sign_xor and (ex2_bd_sh0(3) or ex2_bd_sh1(3) ) ) ; + u_br_04_add: ex2_br_04_add <= not( ex2_br_04_sign_xor and (ex2_bd_sh0(4) or ex2_bd_sh1(4) ) ) ; + u_br_05_add: ex2_br_05_add <= not( ex2_br_05_sign_xor and (ex2_bd_sh0(5) or ex2_bd_sh1(5) ) ) ; + u_br_06_add: ex2_br_06_add <= not( ex2_br_06_sign_xor and (ex2_bd_sh0(6) or ex2_bd_sh1(6) ) ) ; + u_br_07_add: ex2_br_07_add <= not( ex2_br_07_sign_xor and (ex2_bd_sh0(7) or ex2_bd_sh1(7) ) ) ; + u_br_08_add: ex2_br_08_add <= not( ex2_br_08_sign_xor and (ex2_bd_sh0(8) or ex2_bd_sh1(8) ) ) ; + u_br_09_add: ex2_br_09_add <= not( ex2_br_09_sign_xor and (ex2_bd_sh0(9) or ex2_bd_sh1(9) ) ) ; + u_br_10_add: ex2_br_10_add <= not( ex2_br_10_sign_xor and (ex2_bd_sh0(10) or ex2_bd_sh1(10) ) ) ; + u_br_11_add: ex2_br_11_add <= not( ex2_br_11_sign_xor and (ex2_bd_sh0(11) or ex2_bd_sh1(11) ) ) ; + u_br_12_add: ex2_br_12_add <= not( ex2_br_12_sign_xor and (ex2_bd_sh0(12) or ex2_bd_sh1(12) ) ) ; + u_br_13_add: ex2_br_13_add <= not( ex2_br_13_sign_xor and (ex2_bd_sh0(13) or ex2_bd_sh1(13) ) ) ; + u_br_14_add: ex2_br_14_add <= not( ex2_br_14_sign_xor and (ex2_bd_sh0(14) or ex2_bd_sh1(14) ) ) ; + u_br_15_add: ex2_br_15_add <= not( ex2_br_15_sign_xor and (ex2_bd_sh0(15) or ex2_bd_sh1(15) ) ) ; + u_br_16_add: ex2_br_16_add <= not( ex2_br_16_sign_xor and (ex2_bd_sh0(16) or ex2_bd_sh1(16) ) ) ; + u_br_16_sub: ex2_br_16_sub <= ex2_br_16_sign_xor and (ex2_bd_sh0(16) or ex2_bd_sh1(16) ) ; + + + + ex2_pp0_00(198) <= tiup ; + ex2_pp0_00(199) <= ex2_br_00_add ; + ex2_pp0_00(200 to 232) <= ex2_br_00_out(0 to 32) ; + ex2_pp0_00(233) <= tidn ; + ex2_pp0_00(234) <= ex2_hot_one(1) ; + + ex2_pp0_01(200) <= tiup ; + ex2_pp0_01(201) <= ex2_br_01_add ; + ex2_pp0_01(202 to 234) <= ex2_br_01_out(0 to 32) ; + ex2_pp0_01(235) <= tidn ; + ex2_pp0_01(236) <= ex2_hot_one(2) ; + + ex2_pp0_02(202) <= tiup ; + ex2_pp0_02(203) <= ex2_br_02_add ; + ex2_pp0_02(204 to 236) <= ex2_br_02_out(0 to 32) ; + ex2_pp0_02(237) <= tidn ; + ex2_pp0_02(238) <= ex2_hot_one(3) ; + + ex2_pp0_03(204) <= tiup ; + ex2_pp0_03(205) <= ex2_br_03_add ; + ex2_pp0_03(206 to 238) <= ex2_br_03_out(0 to 32) ; + ex2_pp0_03(239) <= tidn ; + ex2_pp0_03(240) <= ex2_hot_one(4) ; + + ex2_pp0_04(206) <= tiup ; + ex2_pp0_04(207) <= ex2_br_04_add ; + ex2_pp0_04(208 to 240) <= ex2_br_04_out(0 to 32) ; + ex2_pp0_04(241) <= tidn ; + ex2_pp0_04(242) <= ex2_hot_one(5) ; + + ex2_pp0_05(208) <= tiup ; + ex2_pp0_05(209) <= ex2_br_05_add ; + ex2_pp0_05(210 to 242) <= ex2_br_05_out(0 to 32) ; + ex2_pp0_05(243) <= tidn ; + ex2_pp0_05(244) <= ex2_hot_one(6) ; + + ex2_pp0_06(210) <= tiup ; + ex2_pp0_06(211) <= ex2_br_06_add ; + ex2_pp0_06(212 to 244) <= ex2_br_06_out(0 to 32) ; + ex2_pp0_06(245) <= tidn ; + ex2_pp0_06(246) <= ex2_hot_one(7) ; + + ex2_pp0_07(212) <= tiup ; + ex2_pp0_07(213) <= ex2_br_07_add ; + ex2_pp0_07(214 to 246) <= ex2_br_07_out(0 to 32) ; + ex2_pp0_07(247) <= tidn ; + ex2_pp0_07(248) <= ex2_hot_one(8) ; + + ex2_pp0_08(214) <= tiup ; + ex2_pp0_08(215) <= ex2_br_08_add ; + ex2_pp0_08(216 to 248) <= ex2_br_08_out(0 to 32) ; + ex2_pp0_08(249) <= tidn ; + ex2_pp0_08(250) <= ex2_hot_one(9) ; + + ex2_pp0_09(216) <= tiup ; + ex2_pp0_09(217) <= ex2_br_09_add ; + ex2_pp0_09(218 to 250) <= ex2_br_09_out(0 to 32) ; + ex2_pp0_09(251) <= tidn ; + ex2_pp0_09(252) <= ex2_hot_one(10) ; + + ex2_pp0_10(218) <= tiup ; + ex2_pp0_10(219) <= ex2_br_10_add ; + ex2_pp0_10(220 to 252) <= ex2_br_10_out(0 to 32) ; + ex2_pp0_10(253) <= tidn ; + ex2_pp0_10(254) <= ex2_hot_one(11) ; + + ex2_pp0_11(220) <= tiup ; + ex2_pp0_11(221) <= ex2_br_11_add ; + ex2_pp0_11(222 to 254) <= ex2_br_11_out(0 to 32) ; + ex2_pp0_11(255) <= tidn ; + ex2_pp0_11(256) <= ex2_hot_one(12) ; + + ex2_pp0_12(222) <= tiup ; + ex2_pp0_12(223) <= ex2_br_12_add ; + ex2_pp0_12(224 to 256) <= ex2_br_12_out(0 to 32) ; + ex2_pp0_12(257) <= tidn ; + ex2_pp0_12(258) <= ex2_hot_one(13) ; + + ex2_pp0_13(224) <= tiup ; + ex2_pp0_13(225) <= ex2_br_13_add ; + ex2_pp0_13(226 to 258) <= ex2_br_13_out(0 to 32) ; + ex2_pp0_13(259) <= tidn ; + ex2_pp0_13(260) <= ex2_hot_one(14) ; + + ex2_pp0_14(226) <= tiup ; + ex2_pp0_14(227) <= ex2_br_14_add ; + ex2_pp0_14(228 to 260) <= ex2_br_14_out(0 to 32) ; + ex2_pp0_14(261) <= tidn ; + ex2_pp0_14(262) <= ex2_hot_one(15) ; + + ex2_pp0_15(228) <= tiup ; + ex2_pp0_15(229) <= ex2_br_15_add ; + ex2_pp0_15(230 to 262) <= ex2_br_15_out(0 to 32) ; + ex2_pp0_15(263) <= tidn ; + ex2_pp0_15(264) <= ex2_hot_one(16) ; + + ex2_pp0_16(229) <= ex2_br_16_add ; + ex2_pp0_16(230) <= ex2_br_16_sub ; + ex2_pp0_16(231) <= ex2_br_16_sub ; + ex2_pp0_16(232 to 264) <= ex2_br_16_out(0 to 32) ; + + ex2_pp0_17(232) <= ex2_hot_one(0) ; + + + + + + + + ex2_pp1_0s(236) <= ex2_pp0_01(236) ; + ex2_pp1_0s(235) <= tidn ; + ex2_pp1_0c(234) <= ex2_pp0_01(234) ; + ex2_pp1_0s(234) <= ex2_pp0_00(234) ; + ex2_pp1_0c(233) <= tidn ; + ex2_pp1_0s(233) <= ex2_pp0_01(233) ; + ex2_pp1_0c(232) <= tidn ; + + + csa1_0_232: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_00(232) , + b => ex2_pp0_01(232) , + c => ex2_pp0_17(232) , + sum => ex2_pp1_0s(232) , + car => ex2_pp1_0c(231) ); + csa1_0_231: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(231) , + b => ex2_pp0_01(231) , + sum => ex2_pp1_0s(231) , + car => ex2_pp1_0c(230) ); + csa1_0_230: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(230) , + b => ex2_pp0_01(230) , + sum => ex2_pp1_0s(230) , + car => ex2_pp1_0c(229) ); + csa1_0_229: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(229) , + b => ex2_pp0_01(229) , + sum => ex2_pp1_0s(229) , + car => ex2_pp1_0c(228) ); + csa1_0_228: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(228) , + b => ex2_pp0_01(228) , + sum => ex2_pp1_0s(228) , + car => ex2_pp1_0c(227) ); + csa1_0_227: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(227) , + b => ex2_pp0_01(227) , + sum => ex2_pp1_0s(227) , + car => ex2_pp1_0c(226) ); + csa1_0_226: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(226) , + b => ex2_pp0_01(226) , + sum => ex2_pp1_0s(226) , + car => ex2_pp1_0c(225) ); + csa1_0_225: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(225) , + b => ex2_pp0_01(225) , + sum => ex2_pp1_0s(225) , + car => ex2_pp1_0c(224) ); + csa1_0_224: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(224) , + b => ex2_pp0_01(224) , + sum => ex2_pp1_0s(224) , + car => ex2_pp1_0c(223) ); + csa1_0_223: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(223) , + b => ex2_pp0_01(223) , + sum => ex2_pp1_0s(223) , + car => ex2_pp1_0c(222) ); + csa1_0_222: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(222) , + b => ex2_pp0_01(222) , + sum => ex2_pp1_0s(222) , + car => ex2_pp1_0c(221) ); + csa1_0_221: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(221) , + b => ex2_pp0_01(221) , + sum => ex2_pp1_0s(221) , + car => ex2_pp1_0c(220) ); + csa1_0_220: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(220) , + b => ex2_pp0_01(220) , + sum => ex2_pp1_0s(220) , + car => ex2_pp1_0c(219) ); + csa1_0_219: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(219) , + b => ex2_pp0_01(219) , + sum => ex2_pp1_0s(219) , + car => ex2_pp1_0c(218) ); + csa1_0_218: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(218) , + b => ex2_pp0_01(218) , + sum => ex2_pp1_0s(218) , + car => ex2_pp1_0c(217) ); + csa1_0_217: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(217) , + b => ex2_pp0_01(217) , + sum => ex2_pp1_0s(217) , + car => ex2_pp1_0c(216) ); + csa1_0_216: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(216) , + b => ex2_pp0_01(216) , + sum => ex2_pp1_0s(216) , + car => ex2_pp1_0c(215) ); + csa1_0_215: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(215) , + b => ex2_pp0_01(215) , + sum => ex2_pp1_0s(215) , + car => ex2_pp1_0c(214) ); + csa1_0_214: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(214) , + b => ex2_pp0_01(214) , + sum => ex2_pp1_0s(214) , + car => ex2_pp1_0c(213) ); + csa1_0_213: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(213) , + b => ex2_pp0_01(213) , + sum => ex2_pp1_0s(213) , + car => ex2_pp1_0c(212) ); + csa1_0_212: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(212) , + b => ex2_pp0_01(212) , + sum => ex2_pp1_0s(212) , + car => ex2_pp1_0c(211) ); + csa1_0_211: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(211) , + b => ex2_pp0_01(211) , + sum => ex2_pp1_0s(211) , + car => ex2_pp1_0c(210) ); + csa1_0_210: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(210) , + b => ex2_pp0_01(210) , + sum => ex2_pp1_0s(210) , + car => ex2_pp1_0c(209) ); + csa1_0_209: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(209) , + b => ex2_pp0_01(209) , + sum => ex2_pp1_0s(209) , + car => ex2_pp1_0c(208) ); + csa1_0_208: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(208) , + b => ex2_pp0_01(208) , + sum => ex2_pp1_0s(208) , + car => ex2_pp1_0c(207) ); + csa1_0_207: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(207) , + b => ex2_pp0_01(207) , + sum => ex2_pp1_0s(207) , + car => ex2_pp1_0c(206) ); + csa1_0_206: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(206) , + b => ex2_pp0_01(206) , + sum => ex2_pp1_0s(206) , + car => ex2_pp1_0c(205) ); + csa1_0_205: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(205) , + b => ex2_pp0_01(205) , + sum => ex2_pp1_0s(205) , + car => ex2_pp1_0c(204) ); + csa1_0_204: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(204) , + b => ex2_pp0_01(204) , + sum => ex2_pp1_0s(204) , + car => ex2_pp1_0c(203) ); + csa1_0_203: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(203) , + b => ex2_pp0_01(203) , + sum => ex2_pp1_0s(203) , + car => ex2_pp1_0c(202) ); + csa1_0_202: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(202) , + b => ex2_pp0_01(202) , + sum => ex2_pp1_0s(202) , + car => ex2_pp1_0c(201) ); + csa1_0_201: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(201) , + b => ex2_pp0_01(201) , + sum => ex2_pp1_0s(201) , + car => ex2_pp1_0c(200) ); + csa1_0_200: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(200) , + b => ex2_pp0_01(200) , + sum => ex2_pp1_0s(200) , + car => ex2_pp1_0c(199) ); + ex2_pp1_0s(199) <= ex2_pp0_00(199) ; + ex2_pp1_0s(198) <= ex2_pp0_00(198) ; + + + + + + + ex2_pp1_1s(242) <= ex2_pp0_04(242) ; + ex2_pp1_1s(241) <= tidn ; + ex2_pp1_1c(240) <= ex2_pp0_04(240) ; + ex2_pp1_1s(240) <= ex2_pp0_03(240) ; + ex2_pp1_1c(239) <= tidn ; + ex2_pp1_1s(239) <= ex2_pp0_04(239) ; + ex2_pp1_1c(238) <= tidn ; + csa1_1_238: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(238) , + b => ex2_pp0_03(238) , + c => ex2_pp0_04(238) , + sum => ex2_pp1_1s(238) , + car => ex2_pp1_1c(237) ); + csa1_1_237: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_03(237) , + b => ex2_pp0_04(237) , + sum => ex2_pp1_1s(237) , + car => ex2_pp1_1c(236) ); + csa1_1_236: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(236) , + b => ex2_pp0_03(236) , + c => ex2_pp0_04(236) , + sum => ex2_pp1_1s(236) , + car => ex2_pp1_1c(235) ); + csa1_1_235: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(235) , + b => ex2_pp0_03(235) , + c => ex2_pp0_04(235) , + sum => ex2_pp1_1s(235) , + car => ex2_pp1_1c(234) ); + csa1_1_234: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(234) , + b => ex2_pp0_03(234) , + c => ex2_pp0_04(234) , + sum => ex2_pp1_1s(234) , + car => ex2_pp1_1c(233) ); + csa1_1_233: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(233) , + b => ex2_pp0_03(233) , + c => ex2_pp0_04(233) , + sum => ex2_pp1_1s(233) , + car => ex2_pp1_1c(232) ); + csa1_1_232: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(232) , + b => ex2_pp0_03(232) , + c => ex2_pp0_04(232) , + sum => ex2_pp1_1s(232) , + car => ex2_pp1_1c(231) ); + csa1_1_231: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(231) , + b => ex2_pp0_03(231) , + c => ex2_pp0_04(231) , + sum => ex2_pp1_1s(231) , + car => ex2_pp1_1c(230) ); + csa1_1_230: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(230) , + b => ex2_pp0_03(230) , + c => ex2_pp0_04(230) , + sum => ex2_pp1_1s(230) , + car => ex2_pp1_1c(229) ); + csa1_1_229: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(229) , + b => ex2_pp0_03(229) , + c => ex2_pp0_04(229) , + sum => ex2_pp1_1s(229) , + car => ex2_pp1_1c(228) ); + csa1_1_228: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(228) , + b => ex2_pp0_03(228) , + c => ex2_pp0_04(228) , + sum => ex2_pp1_1s(228) , + car => ex2_pp1_1c(227) ); + csa1_1_227: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(227) , + b => ex2_pp0_03(227) , + c => ex2_pp0_04(227) , + sum => ex2_pp1_1s(227) , + car => ex2_pp1_1c(226) ); + csa1_1_226: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(226) , + b => ex2_pp0_03(226) , + c => ex2_pp0_04(226) , + sum => ex2_pp1_1s(226) , + car => ex2_pp1_1c(225) ); + csa1_1_225: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(225) , + b => ex2_pp0_03(225) , + c => ex2_pp0_04(225) , + sum => ex2_pp1_1s(225) , + car => ex2_pp1_1c(224) ); + csa1_1_224: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(224) , + b => ex2_pp0_03(224) , + c => ex2_pp0_04(224) , + sum => ex2_pp1_1s(224) , + car => ex2_pp1_1c(223) ); + csa1_1_223: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(223) , + b => ex2_pp0_03(223) , + c => ex2_pp0_04(223) , + sum => ex2_pp1_1s(223) , + car => ex2_pp1_1c(222) ); + csa1_1_222: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(222) , + b => ex2_pp0_03(222) , + c => ex2_pp0_04(222) , + sum => ex2_pp1_1s(222) , + car => ex2_pp1_1c(221) ); + csa1_1_221: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(221) , + b => ex2_pp0_03(221) , + c => ex2_pp0_04(221) , + sum => ex2_pp1_1s(221) , + car => ex2_pp1_1c(220) ); + csa1_1_220: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(220) , + b => ex2_pp0_03(220) , + c => ex2_pp0_04(220) , + sum => ex2_pp1_1s(220) , + car => ex2_pp1_1c(219) ); + csa1_1_219: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(219) , + b => ex2_pp0_03(219) , + c => ex2_pp0_04(219) , + sum => ex2_pp1_1s(219) , + car => ex2_pp1_1c(218) ); + csa1_1_218: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(218) , + b => ex2_pp0_03(218) , + c => ex2_pp0_04(218) , + sum => ex2_pp1_1s(218) , + car => ex2_pp1_1c(217) ); + csa1_1_217: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(217) , + b => ex2_pp0_03(217) , + c => ex2_pp0_04(217) , + sum => ex2_pp1_1s(217) , + car => ex2_pp1_1c(216) ); + csa1_1_216: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(216) , + b => ex2_pp0_03(216) , + c => ex2_pp0_04(216) , + sum => ex2_pp1_1s(216) , + car => ex2_pp1_1c(215) ); + csa1_1_215: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(215) , + b => ex2_pp0_03(215) , + c => ex2_pp0_04(215) , + sum => ex2_pp1_1s(215) , + car => ex2_pp1_1c(214) ); + csa1_1_214: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(214) , + b => ex2_pp0_03(214) , + c => ex2_pp0_04(214) , + sum => ex2_pp1_1s(214) , + car => ex2_pp1_1c(213) ); + csa1_1_213: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(213) , + b => ex2_pp0_03(213) , + c => ex2_pp0_04(213) , + sum => ex2_pp1_1s(213) , + car => ex2_pp1_1c(212) ); + csa1_1_212: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(212) , + b => ex2_pp0_03(212) , + c => ex2_pp0_04(212) , + sum => ex2_pp1_1s(212) , + car => ex2_pp1_1c(211) ); + csa1_1_211: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(211) , + b => ex2_pp0_03(211) , + c => ex2_pp0_04(211) , + sum => ex2_pp1_1s(211) , + car => ex2_pp1_1c(210) ); + csa1_1_210: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(210) , + b => ex2_pp0_03(210) , + c => ex2_pp0_04(210) , + sum => ex2_pp1_1s(210) , + car => ex2_pp1_1c(209) ); + csa1_1_209: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(209) , + b => ex2_pp0_03(209) , + c => ex2_pp0_04(209) , + sum => ex2_pp1_1s(209) , + car => ex2_pp1_1c(208) ); + csa1_1_208: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(208) , + b => ex2_pp0_03(208) , + c => ex2_pp0_04(208) , + sum => ex2_pp1_1s(208) , + car => ex2_pp1_1c(207) ); + csa1_1_207: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(207) , + b => ex2_pp0_03(207) , + c => ex2_pp0_04(207) , + sum => ex2_pp1_1s(207) , + car => ex2_pp1_1c(206) ); + csa1_1_206: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(206) , + b => ex2_pp0_03(206) , + c => ex2_pp0_04(206) , + sum => ex2_pp1_1s(206) , + car => ex2_pp1_1c(205) ); + csa1_1_205: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_02(205) , + b => ex2_pp0_03(205) , + sum => ex2_pp1_1s(205) , + car => ex2_pp1_1c(204) ); + csa1_1_204: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_02(204) , + b => ex2_pp0_03(204) , + sum => ex2_pp1_1s(204) , + car => ex2_pp1_1c(203) ); + ex2_pp1_1s(203) <= ex2_pp0_02(203) ; + ex2_pp1_1s(202) <= ex2_pp0_02(202) ; + + + + + ex2_pp1_2s(248) <= ex2_pp0_07(248) ; + ex2_pp1_2s(247) <= tidn ; + ex2_pp1_2c(246) <= ex2_pp0_07(246) ; + ex2_pp1_2s(246) <= ex2_pp0_06(246) ; + ex2_pp1_2c(245) <= tidn ; + ex2_pp1_2s(245) <= ex2_pp0_07(245) ; + ex2_pp1_2c(244) <= tidn ; + csa1_2_244: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(244) , + b => ex2_pp0_06(244) , + c => ex2_pp0_07(244) , + sum => ex2_pp1_2s(244) , + car => ex2_pp1_2c(243) ); + csa1_2_243: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_06(243) , + b => ex2_pp0_07(243) , + sum => ex2_pp1_2s(243) , + car => ex2_pp1_2c(242) ); + csa1_2_242: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(242) , + b => ex2_pp0_06(242) , + c => ex2_pp0_07(242) , + sum => ex2_pp1_2s(242) , + car => ex2_pp1_2c(241) ); + csa1_2_241: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(241) , + b => ex2_pp0_06(241) , + c => ex2_pp0_07(241) , + sum => ex2_pp1_2s(241) , + car => ex2_pp1_2c(240) ); + csa1_2_240: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(240) , + b => ex2_pp0_06(240) , + c => ex2_pp0_07(240) , + sum => ex2_pp1_2s(240) , + car => ex2_pp1_2c(239) ); + csa1_2_239: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(239) , + b => ex2_pp0_06(239) , + c => ex2_pp0_07(239) , + sum => ex2_pp1_2s(239) , + car => ex2_pp1_2c(238) ); + csa1_2_238: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(238) , + b => ex2_pp0_06(238) , + c => ex2_pp0_07(238) , + sum => ex2_pp1_2s(238) , + car => ex2_pp1_2c(237) ); + csa1_2_237: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(237) , + b => ex2_pp0_06(237) , + c => ex2_pp0_07(237) , + sum => ex2_pp1_2s(237) , + car => ex2_pp1_2c(236) ); + csa1_2_236: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(236) , + b => ex2_pp0_06(236) , + c => ex2_pp0_07(236) , + sum => ex2_pp1_2s(236) , + car => ex2_pp1_2c(235) ); + csa1_2_235: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(235) , + b => ex2_pp0_06(235) , + c => ex2_pp0_07(235) , + sum => ex2_pp1_2s(235) , + car => ex2_pp1_2c(234) ); + csa1_2_234: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(234) , + b => ex2_pp0_06(234) , + c => ex2_pp0_07(234) , + sum => ex2_pp1_2s(234) , + car => ex2_pp1_2c(233) ); + csa1_2_233: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(233) , + b => ex2_pp0_06(233) , + c => ex2_pp0_07(233) , + sum => ex2_pp1_2s(233) , + car => ex2_pp1_2c(232) ); + csa1_2_232: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(232) , + b => ex2_pp0_06(232) , + c => ex2_pp0_07(232) , + sum => ex2_pp1_2s(232) , + car => ex2_pp1_2c(231) ); + csa1_2_231: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(231) , + b => ex2_pp0_06(231) , + c => ex2_pp0_07(231) , + sum => ex2_pp1_2s(231) , + car => ex2_pp1_2c(230) ); + csa1_2_230: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(230) , + b => ex2_pp0_06(230) , + c => ex2_pp0_07(230) , + sum => ex2_pp1_2s(230) , + car => ex2_pp1_2c(229) ); + csa1_2_229: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(229) , + b => ex2_pp0_06(229) , + c => ex2_pp0_07(229) , + sum => ex2_pp1_2s(229) , + car => ex2_pp1_2c(228) ); + csa1_2_228: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(228) , + b => ex2_pp0_06(228) , + c => ex2_pp0_07(228) , + sum => ex2_pp1_2s(228) , + car => ex2_pp1_2c(227) ); + csa1_2_227: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(227) , + b => ex2_pp0_06(227) , + c => ex2_pp0_07(227) , + sum => ex2_pp1_2s(227) , + car => ex2_pp1_2c(226) ); + csa1_2_226: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(226) , + b => ex2_pp0_06(226) , + c => ex2_pp0_07(226) , + sum => ex2_pp1_2s(226) , + car => ex2_pp1_2c(225) ); + csa1_2_225: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(225) , + b => ex2_pp0_06(225) , + c => ex2_pp0_07(225) , + sum => ex2_pp1_2s(225) , + car => ex2_pp1_2c(224) ); + csa1_2_224: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(224) , + b => ex2_pp0_06(224) , + c => ex2_pp0_07(224) , + sum => ex2_pp1_2s(224) , + car => ex2_pp1_2c(223) ); + csa1_2_223: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(223) , + b => ex2_pp0_06(223) , + c => ex2_pp0_07(223) , + sum => ex2_pp1_2s(223) , + car => ex2_pp1_2c(222) ); + csa1_2_222: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(222) , + b => ex2_pp0_06(222) , + c => ex2_pp0_07(222) , + sum => ex2_pp1_2s(222) , + car => ex2_pp1_2c(221) ); + csa1_2_221: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(221) , + b => ex2_pp0_06(221) , + c => ex2_pp0_07(221) , + sum => ex2_pp1_2s(221) , + car => ex2_pp1_2c(220) ); + csa1_2_220: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(220) , + b => ex2_pp0_06(220) , + c => ex2_pp0_07(220) , + sum => ex2_pp1_2s(220) , + car => ex2_pp1_2c(219) ); + csa1_2_219: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(219) , + b => ex2_pp0_06(219) , + c => ex2_pp0_07(219) , + sum => ex2_pp1_2s(219) , + car => ex2_pp1_2c(218) ); + csa1_2_218: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(218) , + b => ex2_pp0_06(218) , + c => ex2_pp0_07(218) , + sum => ex2_pp1_2s(218) , + car => ex2_pp1_2c(217) ); + csa1_2_217: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(217) , + b => ex2_pp0_06(217) , + c => ex2_pp0_07(217) , + sum => ex2_pp1_2s(217) , + car => ex2_pp1_2c(216) ); + csa1_2_216: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(216) , + b => ex2_pp0_06(216) , + c => ex2_pp0_07(216) , + sum => ex2_pp1_2s(216) , + car => ex2_pp1_2c(215) ); + csa1_2_215: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(215) , + b => ex2_pp0_06(215) , + c => ex2_pp0_07(215) , + sum => ex2_pp1_2s(215) , + car => ex2_pp1_2c(214) ); + csa1_2_214: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(214) , + b => ex2_pp0_06(214) , + c => ex2_pp0_07(214) , + sum => ex2_pp1_2s(214) , + car => ex2_pp1_2c(213) ); + csa1_2_213: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(213) , + b => ex2_pp0_06(213) , + c => ex2_pp0_07(213) , + sum => ex2_pp1_2s(213) , + car => ex2_pp1_2c(212) ); + csa1_2_212: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(212) , + b => ex2_pp0_06(212) , + c => ex2_pp0_07(212) , + sum => ex2_pp1_2s(212) , + car => ex2_pp1_2c(211) ); + csa1_2_211: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_05(211) , + b => ex2_pp0_06(211) , + sum => ex2_pp1_2s(211) , + car => ex2_pp1_2c(210) ); + csa1_2_210: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_05(210) , + b => ex2_pp0_06(210) , + sum => ex2_pp1_2s(210) , + car => ex2_pp1_2c(209) ); + ex2_pp1_2s(209) <= ex2_pp0_05(209) ; + ex2_pp1_2s(208) <= ex2_pp0_05(208) ; + + + + + + ex2_pp1_3s(254) <= ex2_pp0_10(254) ; + ex2_pp1_3s(253) <= tidn ; + ex2_pp1_3c(252) <= ex2_pp0_10(252) ; + ex2_pp1_3s(252) <= ex2_pp0_09(252) ; + ex2_pp1_3c(251) <= tidn ; + ex2_pp1_3s(251) <= ex2_pp0_10(251) ; + ex2_pp1_3c(250) <= tidn ; + csa1_3_250: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(250) , + b => ex2_pp0_09(250) , + c => ex2_pp0_10(250) , + sum => ex2_pp1_3s(250) , + car => ex2_pp1_3c(249) ); + csa1_3_249: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_09(249) , + b => ex2_pp0_10(249) , + sum => ex2_pp1_3s(249) , + car => ex2_pp1_3c(248) ); + csa1_3_248: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(248) , + b => ex2_pp0_09(248) , + c => ex2_pp0_10(248) , + sum => ex2_pp1_3s(248) , + car => ex2_pp1_3c(247) ); + csa1_3_247: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(247) , + b => ex2_pp0_09(247) , + c => ex2_pp0_10(247) , + sum => ex2_pp1_3s(247) , + car => ex2_pp1_3c(246) ); + csa1_3_246: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(246) , + b => ex2_pp0_09(246) , + c => ex2_pp0_10(246) , + sum => ex2_pp1_3s(246) , + car => ex2_pp1_3c(245) ); + csa1_3_245: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(245) , + b => ex2_pp0_09(245) , + c => ex2_pp0_10(245) , + sum => ex2_pp1_3s(245) , + car => ex2_pp1_3c(244) ); + csa1_3_244: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(244) , + b => ex2_pp0_09(244) , + c => ex2_pp0_10(244) , + sum => ex2_pp1_3s(244) , + car => ex2_pp1_3c(243) ); + csa1_3_243: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(243) , + b => ex2_pp0_09(243) , + c => ex2_pp0_10(243) , + sum => ex2_pp1_3s(243) , + car => ex2_pp1_3c(242) ); + csa1_3_242: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(242) , + b => ex2_pp0_09(242) , + c => ex2_pp0_10(242) , + sum => ex2_pp1_3s(242) , + car => ex2_pp1_3c(241) ); + csa1_3_241: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(241) , + b => ex2_pp0_09(241) , + c => ex2_pp0_10(241) , + sum => ex2_pp1_3s(241) , + car => ex2_pp1_3c(240) ); + csa1_3_240: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(240) , + b => ex2_pp0_09(240) , + c => ex2_pp0_10(240) , + sum => ex2_pp1_3s(240) , + car => ex2_pp1_3c(239) ); + csa1_3_239: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(239) , + b => ex2_pp0_09(239) , + c => ex2_pp0_10(239) , + sum => ex2_pp1_3s(239) , + car => ex2_pp1_3c(238) ); + csa1_3_238: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(238) , + b => ex2_pp0_09(238) , + c => ex2_pp0_10(238) , + sum => ex2_pp1_3s(238) , + car => ex2_pp1_3c(237) ); + csa1_3_237: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(237) , + b => ex2_pp0_09(237) , + c => ex2_pp0_10(237) , + sum => ex2_pp1_3s(237) , + car => ex2_pp1_3c(236) ); + csa1_3_236: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(236) , + b => ex2_pp0_09(236) , + c => ex2_pp0_10(236) , + sum => ex2_pp1_3s(236) , + car => ex2_pp1_3c(235) ); + csa1_3_235: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(235) , + b => ex2_pp0_09(235) , + c => ex2_pp0_10(235) , + sum => ex2_pp1_3s(235) , + car => ex2_pp1_3c(234) ); + csa1_3_234: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(234) , + b => ex2_pp0_09(234) , + c => ex2_pp0_10(234) , + sum => ex2_pp1_3s(234) , + car => ex2_pp1_3c(233) ); + csa1_3_233: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(233) , + b => ex2_pp0_09(233) , + c => ex2_pp0_10(233) , + sum => ex2_pp1_3s(233) , + car => ex2_pp1_3c(232) ); + csa1_3_232: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(232) , + b => ex2_pp0_09(232) , + c => ex2_pp0_10(232) , + sum => ex2_pp1_3s(232) , + car => ex2_pp1_3c(231) ); + csa1_3_231: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(231) , + b => ex2_pp0_09(231) , + c => ex2_pp0_10(231) , + sum => ex2_pp1_3s(231) , + car => ex2_pp1_3c(230) ); + csa1_3_230: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(230) , + b => ex2_pp0_09(230) , + c => ex2_pp0_10(230) , + sum => ex2_pp1_3s(230) , + car => ex2_pp1_3c(229) ); + csa1_3_229: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(229) , + b => ex2_pp0_09(229) , + c => ex2_pp0_10(229) , + sum => ex2_pp1_3s(229) , + car => ex2_pp1_3c(228) ); + csa1_3_228: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(228) , + b => ex2_pp0_09(228) , + c => ex2_pp0_10(228) , + sum => ex2_pp1_3s(228) , + car => ex2_pp1_3c(227) ); + csa1_3_227: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(227) , + b => ex2_pp0_09(227) , + c => ex2_pp0_10(227) , + sum => ex2_pp1_3s(227) , + car => ex2_pp1_3c(226) ); + csa1_3_226: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(226) , + b => ex2_pp0_09(226) , + c => ex2_pp0_10(226) , + sum => ex2_pp1_3s(226) , + car => ex2_pp1_3c(225) ); + csa1_3_225: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(225) , + b => ex2_pp0_09(225) , + c => ex2_pp0_10(225) , + sum => ex2_pp1_3s(225) , + car => ex2_pp1_3c(224) ); + csa1_3_224: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(224) , + b => ex2_pp0_09(224) , + c => ex2_pp0_10(224) , + sum => ex2_pp1_3s(224) , + car => ex2_pp1_3c(223) ); + csa1_3_223: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(223) , + b => ex2_pp0_09(223) , + c => ex2_pp0_10(223) , + sum => ex2_pp1_3s(223) , + car => ex2_pp1_3c(222) ); + csa1_3_222: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(222) , + b => ex2_pp0_09(222) , + c => ex2_pp0_10(222) , + sum => ex2_pp1_3s(222) , + car => ex2_pp1_3c(221) ); + csa1_3_221: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(221) , + b => ex2_pp0_09(221) , + c => ex2_pp0_10(221) , + sum => ex2_pp1_3s(221) , + car => ex2_pp1_3c(220) ); + csa1_3_220: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(220) , + b => ex2_pp0_09(220) , + c => ex2_pp0_10(220) , + sum => ex2_pp1_3s(220) , + car => ex2_pp1_3c(219) ); + csa1_3_219: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(219) , + b => ex2_pp0_09(219) , + c => ex2_pp0_10(219) , + sum => ex2_pp1_3s(219) , + car => ex2_pp1_3c(218) ); + csa1_3_218: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(218) , + b => ex2_pp0_09(218) , + c => ex2_pp0_10(218) , + sum => ex2_pp1_3s(218) , + car => ex2_pp1_3c(217) ); + csa1_3_217: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_08(217) , + b => ex2_pp0_09(217) , + sum => ex2_pp1_3s(217) , + car => ex2_pp1_3c(216) ); + csa1_3_216: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_08(216) , + b => ex2_pp0_09(216) , + sum => ex2_pp1_3s(216) , + car => ex2_pp1_3c(215) ); + ex2_pp1_3s(215) <= ex2_pp0_08(215) ; + ex2_pp1_3s(214) <= ex2_pp0_08(214) ; + + + + + ex2_pp1_4s(260) <= ex2_pp0_13(260) ; + ex2_pp1_4s(259) <= tidn ; + ex2_pp1_4c(258) <= ex2_pp0_13(258) ; + ex2_pp1_4s(258) <= ex2_pp0_12(258) ; + ex2_pp1_4c(257) <= tidn ; + ex2_pp1_4s(257) <= ex2_pp0_13(257) ; + ex2_pp1_4c(256) <= tidn ; + csa1_4_256: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(256) , + b => ex2_pp0_12(256) , + c => ex2_pp0_13(256) , + sum => ex2_pp1_4s(256) , + car => ex2_pp1_4c(255) ); + csa1_4_255: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_12(255) , + b => ex2_pp0_13(255) , + sum => ex2_pp1_4s(255) , + car => ex2_pp1_4c(254) ); + csa1_4_254: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(254) , + b => ex2_pp0_12(254) , + c => ex2_pp0_13(254) , + sum => ex2_pp1_4s(254) , + car => ex2_pp1_4c(253) ); + csa1_4_253: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(253) , + b => ex2_pp0_12(253) , + c => ex2_pp0_13(253) , + sum => ex2_pp1_4s(253) , + car => ex2_pp1_4c(252) ); + csa1_4_252: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(252) , + b => ex2_pp0_12(252) , + c => ex2_pp0_13(252) , + sum => ex2_pp1_4s(252) , + car => ex2_pp1_4c(251) ); + csa1_4_251: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(251) , + b => ex2_pp0_12(251) , + c => ex2_pp0_13(251) , + sum => ex2_pp1_4s(251) , + car => ex2_pp1_4c(250) ); + csa1_4_250: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(250) , + b => ex2_pp0_12(250) , + c => ex2_pp0_13(250) , + sum => ex2_pp1_4s(250) , + car => ex2_pp1_4c(249) ); + csa1_4_249: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(249) , + b => ex2_pp0_12(249) , + c => ex2_pp0_13(249) , + sum => ex2_pp1_4s(249) , + car => ex2_pp1_4c(248) ); + csa1_4_248: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(248) , + b => ex2_pp0_12(248) , + c => ex2_pp0_13(248) , + sum => ex2_pp1_4s(248) , + car => ex2_pp1_4c(247) ); + csa1_4_247: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(247) , + b => ex2_pp0_12(247) , + c => ex2_pp0_13(247) , + sum => ex2_pp1_4s(247) , + car => ex2_pp1_4c(246) ); + csa1_4_246: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(246) , + b => ex2_pp0_12(246) , + c => ex2_pp0_13(246) , + sum => ex2_pp1_4s(246) , + car => ex2_pp1_4c(245) ); + csa1_4_245: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(245) , + b => ex2_pp0_12(245) , + c => ex2_pp0_13(245) , + sum => ex2_pp1_4s(245) , + car => ex2_pp1_4c(244) ); + csa1_4_244: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(244) , + b => ex2_pp0_12(244) , + c => ex2_pp0_13(244) , + sum => ex2_pp1_4s(244) , + car => ex2_pp1_4c(243) ); + csa1_4_243: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(243) , + b => ex2_pp0_12(243) , + c => ex2_pp0_13(243) , + sum => ex2_pp1_4s(243) , + car => ex2_pp1_4c(242) ); + csa1_4_242: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(242) , + b => ex2_pp0_12(242) , + c => ex2_pp0_13(242) , + sum => ex2_pp1_4s(242) , + car => ex2_pp1_4c(241) ); + csa1_4_241: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(241) , + b => ex2_pp0_12(241) , + c => ex2_pp0_13(241) , + sum => ex2_pp1_4s(241) , + car => ex2_pp1_4c(240) ); + csa1_4_240: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(240) , + b => ex2_pp0_12(240) , + c => ex2_pp0_13(240) , + sum => ex2_pp1_4s(240) , + car => ex2_pp1_4c(239) ); + csa1_4_239: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(239) , + b => ex2_pp0_12(239) , + c => ex2_pp0_13(239) , + sum => ex2_pp1_4s(239) , + car => ex2_pp1_4c(238) ); + csa1_4_238: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(238) , + b => ex2_pp0_12(238) , + c => ex2_pp0_13(238) , + sum => ex2_pp1_4s(238) , + car => ex2_pp1_4c(237) ); + csa1_4_237: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(237) , + b => ex2_pp0_12(237) , + c => ex2_pp0_13(237) , + sum => ex2_pp1_4s(237) , + car => ex2_pp1_4c(236) ); + csa1_4_236: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(236) , + b => ex2_pp0_12(236) , + c => ex2_pp0_13(236) , + sum => ex2_pp1_4s(236) , + car => ex2_pp1_4c(235) ); + csa1_4_235: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(235) , + b => ex2_pp0_12(235) , + c => ex2_pp0_13(235) , + sum => ex2_pp1_4s(235) , + car => ex2_pp1_4c(234) ); + csa1_4_234: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(234) , + b => ex2_pp0_12(234) , + c => ex2_pp0_13(234) , + sum => ex2_pp1_4s(234) , + car => ex2_pp1_4c(233) ); + csa1_4_233: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(233) , + b => ex2_pp0_12(233) , + c => ex2_pp0_13(233) , + sum => ex2_pp1_4s(233) , + car => ex2_pp1_4c(232) ); + csa1_4_232: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(232) , + b => ex2_pp0_12(232) , + c => ex2_pp0_13(232) , + sum => ex2_pp1_4s(232) , + car => ex2_pp1_4c(231) ); + csa1_4_231: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(231) , + b => ex2_pp0_12(231) , + c => ex2_pp0_13(231) , + sum => ex2_pp1_4s(231) , + car => ex2_pp1_4c(230) ); + csa1_4_230: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(230) , + b => ex2_pp0_12(230) , + c => ex2_pp0_13(230) , + sum => ex2_pp1_4s(230) , + car => ex2_pp1_4c(229) ); + csa1_4_229: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(229) , + b => ex2_pp0_12(229) , + c => ex2_pp0_13(229) , + sum => ex2_pp1_4s(229) , + car => ex2_pp1_4c(228) ); + csa1_4_228: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(228) , + b => ex2_pp0_12(228) , + c => ex2_pp0_13(228) , + sum => ex2_pp1_4s(228) , + car => ex2_pp1_4c(227) ); + csa1_4_227: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(227) , + b => ex2_pp0_12(227) , + c => ex2_pp0_13(227) , + sum => ex2_pp1_4s(227) , + car => ex2_pp1_4c(226) ); + csa1_4_226: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(226) , + b => ex2_pp0_12(226) , + c => ex2_pp0_13(226) , + sum => ex2_pp1_4s(226) , + car => ex2_pp1_4c(225) ); + csa1_4_225: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(225) , + b => ex2_pp0_12(225) , + c => ex2_pp0_13(225) , + sum => ex2_pp1_4s(225) , + car => ex2_pp1_4c(224) ); + csa1_4_224: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(224) , + b => ex2_pp0_12(224) , + c => ex2_pp0_13(224) , + sum => ex2_pp1_4s(224) , + car => ex2_pp1_4c(223) ); + csa1_4_223: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_11(223) , + b => ex2_pp0_12(223) , + sum => ex2_pp1_4s(223) , + car => ex2_pp1_4c(222) ); + csa1_4_222: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_11(222) , + b => ex2_pp0_12(222) , + sum => ex2_pp1_4s(222) , + car => ex2_pp1_4c(221) ); + ex2_pp1_4s(221) <= ex2_pp0_11(221) ; + ex2_pp1_4s(220) <= ex2_pp0_11(220) ; + + + + ex2_pp1_5c(264) <= ex2_pp0_16(264) ; + ex2_pp1_5s(264) <= ex2_pp0_15(264) ; + ex2_pp1_5c(263) <= tidn ; + ex2_pp1_5s(263) <= ex2_pp0_16(263) ; + ex2_pp1_5c(262) <= tidn ; + csa1_5_262: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(262) , + b => ex2_pp0_15(262) , + c => ex2_pp0_16(262) , + sum => ex2_pp1_5s(262) , + car => ex2_pp1_5c(261) ); + csa1_5_261: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_15(261) , + b => ex2_pp0_16(261) , + sum => ex2_pp1_5s(261) , + car => ex2_pp1_5c(260) ); + csa1_5_260: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(260) , + b => ex2_pp0_15(260) , + c => ex2_pp0_16(260) , + sum => ex2_pp1_5s(260) , + car => ex2_pp1_5c(259) ); + csa1_5_259: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(259) , + b => ex2_pp0_15(259) , + c => ex2_pp0_16(259) , + sum => ex2_pp1_5s(259) , + car => ex2_pp1_5c(258) ); + csa1_5_258: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(258) , + b => ex2_pp0_15(258) , + c => ex2_pp0_16(258) , + sum => ex2_pp1_5s(258) , + car => ex2_pp1_5c(257) ); + csa1_5_257: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(257) , + b => ex2_pp0_15(257) , + c => ex2_pp0_16(257) , + sum => ex2_pp1_5s(257) , + car => ex2_pp1_5c(256) ); + csa1_5_256: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(256) , + b => ex2_pp0_15(256) , + c => ex2_pp0_16(256) , + sum => ex2_pp1_5s(256) , + car => ex2_pp1_5c(255) ); + csa1_5_255: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(255) , + b => ex2_pp0_15(255) , + c => ex2_pp0_16(255) , + sum => ex2_pp1_5s(255) , + car => ex2_pp1_5c(254) ); + csa1_5_254: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(254) , + b => ex2_pp0_15(254) , + c => ex2_pp0_16(254) , + sum => ex2_pp1_5s(254) , + car => ex2_pp1_5c(253) ); + csa1_5_253: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(253) , + b => ex2_pp0_15(253) , + c => ex2_pp0_16(253) , + sum => ex2_pp1_5s(253) , + car => ex2_pp1_5c(252) ); + csa1_5_252: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(252) , + b => ex2_pp0_15(252) , + c => ex2_pp0_16(252) , + sum => ex2_pp1_5s(252) , + car => ex2_pp1_5c(251) ); + csa1_5_251: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(251) , + b => ex2_pp0_15(251) , + c => ex2_pp0_16(251) , + sum => ex2_pp1_5s(251) , + car => ex2_pp1_5c(250) ); + csa1_5_250: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(250) , + b => ex2_pp0_15(250) , + c => ex2_pp0_16(250) , + sum => ex2_pp1_5s(250) , + car => ex2_pp1_5c(249) ); + csa1_5_249: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(249) , + b => ex2_pp0_15(249) , + c => ex2_pp0_16(249) , + sum => ex2_pp1_5s(249) , + car => ex2_pp1_5c(248) ); + csa1_5_248: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(248) , + b => ex2_pp0_15(248) , + c => ex2_pp0_16(248) , + sum => ex2_pp1_5s(248) , + car => ex2_pp1_5c(247) ); + csa1_5_247: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(247) , + b => ex2_pp0_15(247) , + c => ex2_pp0_16(247) , + sum => ex2_pp1_5s(247) , + car => ex2_pp1_5c(246) ); + csa1_5_246: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(246) , + b => ex2_pp0_15(246) , + c => ex2_pp0_16(246) , + sum => ex2_pp1_5s(246) , + car => ex2_pp1_5c(245) ); + csa1_5_245: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(245) , + b => ex2_pp0_15(245) , + c => ex2_pp0_16(245) , + sum => ex2_pp1_5s(245) , + car => ex2_pp1_5c(244) ); + csa1_5_244: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(244) , + b => ex2_pp0_15(244) , + c => ex2_pp0_16(244) , + sum => ex2_pp1_5s(244) , + car => ex2_pp1_5c(243) ); + csa1_5_243: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(243) , + b => ex2_pp0_15(243) , + c => ex2_pp0_16(243) , + sum => ex2_pp1_5s(243) , + car => ex2_pp1_5c(242) ); + csa1_5_242: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(242) , + b => ex2_pp0_15(242) , + c => ex2_pp0_16(242) , + sum => ex2_pp1_5s(242) , + car => ex2_pp1_5c(241) ); + csa1_5_241: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(241) , + b => ex2_pp0_15(241) , + c => ex2_pp0_16(241) , + sum => ex2_pp1_5s(241) , + car => ex2_pp1_5c(240) ); + csa1_5_240: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(240) , + b => ex2_pp0_15(240) , + c => ex2_pp0_16(240) , + sum => ex2_pp1_5s(240) , + car => ex2_pp1_5c(239) ); + csa1_5_239: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(239) , + b => ex2_pp0_15(239) , + c => ex2_pp0_16(239) , + sum => ex2_pp1_5s(239) , + car => ex2_pp1_5c(238) ); + csa1_5_238: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(238) , + b => ex2_pp0_15(238) , + c => ex2_pp0_16(238) , + sum => ex2_pp1_5s(238) , + car => ex2_pp1_5c(237) ); + csa1_5_237: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(237) , + b => ex2_pp0_15(237) , + c => ex2_pp0_16(237) , + sum => ex2_pp1_5s(237) , + car => ex2_pp1_5c(236) ); + csa1_5_236: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(236) , + b => ex2_pp0_15(236) , + c => ex2_pp0_16(236) , + sum => ex2_pp1_5s(236) , + car => ex2_pp1_5c(235) ); + csa1_5_235: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(235) , + b => ex2_pp0_15(235) , + c => ex2_pp0_16(235) , + sum => ex2_pp1_5s(235) , + car => ex2_pp1_5c(234) ); + csa1_5_234: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(234) , + b => ex2_pp0_15(234) , + c => ex2_pp0_16(234) , + sum => ex2_pp1_5s(234) , + car => ex2_pp1_5c(233) ); + csa1_5_233: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(233) , + b => ex2_pp0_15(233) , + c => ex2_pp0_16(233) , + sum => ex2_pp1_5s(233) , + car => ex2_pp1_5c(232) ); + csa1_5_232: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(232) , + b => ex2_pp0_15(232) , + c => ex2_pp0_16(232) , + sum => ex2_pp1_5s(232) , + car => ex2_pp1_5c(231) ); + csa1_5_231: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(231) , + b => ex2_pp0_15(231) , + c => ex2_pp0_16(231) , + sum => ex2_pp1_5s(231) , + car => ex2_pp1_5c(230) ); + csa1_5_230: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(230) , + b => ex2_pp0_15(230) , + c => ex2_pp0_16(230) , + sum => ex2_pp1_5s(230) , + car => ex2_pp1_5c(229) ); + csa1_5_229: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(229) , + b => ex2_pp0_15(229) , + c => ex2_pp0_16(229) , + sum => ex2_pp1_5s(229) , + car => ex2_pp1_5c(228) ); + csa1_5_228: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_14(228) , + b => ex2_pp0_15(228) , + sum => ex2_pp1_5s(228) , + car => ex2_pp1_5c(227) ); + ex2_pp1_5s(227) <= ex2_pp0_14(227) ; + ex2_pp1_5s(226) <= ex2_pp0_14(226) ; + + + + + + + + + ex2_pp2_0s(242) <= ex2_pp1_1s(242) ; + ex2_pp2_0s(241) <= tidn ; + ex2_pp2_0c(240) <= ex2_pp1_1s(240) ; + ex2_pp2_0s(240) <= ex2_pp1_1c(240) ; + ex2_pp2_0c(239) <= tidn ; + ex2_pp2_0s(239) <= ex2_pp1_1s(239) ; + ex2_pp2_0c(238) <= tidn ; + ex2_pp2_0s(238) <= ex2_pp1_1s(238) ; + ex2_pp2_0c(237) <= ex2_pp1_1s(237) ; + ex2_pp2_0s(237) <= ex2_pp1_1c(237) ; + ex2_pp2_0c(236) <= tidn ; + csa2_0_236: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0s(236) , + b => ex2_pp1_1c(236) , + c => ex2_pp1_1s(236) , + sum => ex2_pp2_0s(236) , + car => ex2_pp2_0c(235) ); + csa2_0_235: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp1_1c(235) , + b => ex2_pp1_1s(235) , + sum => ex2_pp2_0s(235) , + car => ex2_pp2_0c(234) ); + ex2_pp2_0k(234) <= tidn ; + csa2_0_234: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(234) , + b => ex2_pp1_0s(234) , + c => ex2_pp1_1c(234) , + d => ex2_pp1_1s(234) , + ki => ex2_pp2_0k(234) , + ko => ex2_pp2_0k(233) , + sum => ex2_pp2_0s(234) , + car => ex2_pp2_0c(233) ); + csa2_0_233: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0s(233) , + b => ex2_pp1_1c(233) , + c => ex2_pp1_1s(233) , + d => tidn , + ki => ex2_pp2_0k(233) , + ko => ex2_pp2_0k(232) , + sum => ex2_pp2_0s(233) , + car => ex2_pp2_0c(232) ); + csa2_0_232: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0s(232) , + b => ex2_pp1_1c(232) , + c => ex2_pp1_1s(232) , + d => tidn , + ki => ex2_pp2_0k(232) , + ko => ex2_pp2_0k(231) , + sum => ex2_pp2_0s(232) , + car => ex2_pp2_0c(231) ); + csa2_0_231: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(231) , + b => ex2_pp1_0s(231) , + c => ex2_pp1_1c(231) , + d => ex2_pp1_1s(231) , + ki => ex2_pp2_0k(231) , + ko => ex2_pp2_0k(230) , + sum => ex2_pp2_0s(231) , + car => ex2_pp2_0c(230) ); + csa2_0_230: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(230) , + b => ex2_pp1_0s(230) , + c => ex2_pp1_1c(230) , + d => ex2_pp1_1s(230) , + ki => ex2_pp2_0k(230) , + ko => ex2_pp2_0k(229) , + sum => ex2_pp2_0s(230) , + car => ex2_pp2_0c(229) ); + csa2_0_229: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(229) , + b => ex2_pp1_0s(229) , + c => ex2_pp1_1c(229) , + d => ex2_pp1_1s(229) , + ki => ex2_pp2_0k(229) , + ko => ex2_pp2_0k(228) , + sum => ex2_pp2_0s(229) , + car => ex2_pp2_0c(228) ); + csa2_0_228: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(228) , + b => ex2_pp1_0s(228) , + c => ex2_pp1_1c(228) , + d => ex2_pp1_1s(228) , + ki => ex2_pp2_0k(228) , + ko => ex2_pp2_0k(227) , + sum => ex2_pp2_0s(228) , + car => ex2_pp2_0c(227) ); + csa2_0_227: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(227) , + b => ex2_pp1_0s(227) , + c => ex2_pp1_1c(227) , + d => ex2_pp1_1s(227) , + ki => ex2_pp2_0k(227) , + ko => ex2_pp2_0k(226) , + sum => ex2_pp2_0s(227) , + car => ex2_pp2_0c(226) ); + csa2_0_226: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(226) , + b => ex2_pp1_0s(226) , + c => ex2_pp1_1c(226) , + d => ex2_pp1_1s(226) , + ki => ex2_pp2_0k(226) , + ko => ex2_pp2_0k(225) , + sum => ex2_pp2_0s(226) , + car => ex2_pp2_0c(225) ); + csa2_0_225: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(225) , + b => ex2_pp1_0s(225) , + c => ex2_pp1_1c(225) , + d => ex2_pp1_1s(225) , + ki => ex2_pp2_0k(225) , + ko => ex2_pp2_0k(224) , + sum => ex2_pp2_0s(225) , + car => ex2_pp2_0c(224) ); + csa2_0_224: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(224) , + b => ex2_pp1_0s(224) , + c => ex2_pp1_1c(224) , + d => ex2_pp1_1s(224) , + ki => ex2_pp2_0k(224) , + ko => ex2_pp2_0k(223) , + sum => ex2_pp2_0s(224) , + car => ex2_pp2_0c(223) ); + csa2_0_223: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(223) , + b => ex2_pp1_0s(223) , + c => ex2_pp1_1c(223) , + d => ex2_pp1_1s(223) , + ki => ex2_pp2_0k(223) , + ko => ex2_pp2_0k(222) , + sum => ex2_pp2_0s(223) , + car => ex2_pp2_0c(222) ); + csa2_0_222: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(222) , + b => ex2_pp1_0s(222) , + c => ex2_pp1_1c(222) , + d => ex2_pp1_1s(222) , + ki => ex2_pp2_0k(222) , + ko => ex2_pp2_0k(221) , + sum => ex2_pp2_0s(222) , + car => ex2_pp2_0c(221) ); + csa2_0_221: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(221) , + b => ex2_pp1_0s(221) , + c => ex2_pp1_1c(221) , + d => ex2_pp1_1s(221) , + ki => ex2_pp2_0k(221) , + ko => ex2_pp2_0k(220) , + sum => ex2_pp2_0s(221) , + car => ex2_pp2_0c(220) ); + csa2_0_220: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(220) , + b => ex2_pp1_0s(220) , + c => ex2_pp1_1c(220) , + d => ex2_pp1_1s(220) , + ki => ex2_pp2_0k(220) , + ko => ex2_pp2_0k(219) , + sum => ex2_pp2_0s(220) , + car => ex2_pp2_0c(219) ); + csa2_0_219: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(219) , + b => ex2_pp1_0s(219) , + c => ex2_pp1_1c(219) , + d => ex2_pp1_1s(219) , + ki => ex2_pp2_0k(219) , + ko => ex2_pp2_0k(218) , + sum => ex2_pp2_0s(219) , + car => ex2_pp2_0c(218) ); + csa2_0_218: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(218) , + b => ex2_pp1_0s(218) , + c => ex2_pp1_1c(218) , + d => ex2_pp1_1s(218) , + ki => ex2_pp2_0k(218) , + ko => ex2_pp2_0k(217) , + sum => ex2_pp2_0s(218) , + car => ex2_pp2_0c(217) ); + csa2_0_217: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(217) , + b => ex2_pp1_0s(217) , + c => ex2_pp1_1c(217) , + d => ex2_pp1_1s(217) , + ki => ex2_pp2_0k(217) , + ko => ex2_pp2_0k(216) , + sum => ex2_pp2_0s(217) , + car => ex2_pp2_0c(216) ); + csa2_0_216: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(216) , + b => ex2_pp1_0s(216) , + c => ex2_pp1_1c(216) , + d => ex2_pp1_1s(216) , + ki => ex2_pp2_0k(216) , + ko => ex2_pp2_0k(215) , + sum => ex2_pp2_0s(216) , + car => ex2_pp2_0c(215) ); + csa2_0_215: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(215) , + b => ex2_pp1_0s(215) , + c => ex2_pp1_1c(215) , + d => ex2_pp1_1s(215) , + ki => ex2_pp2_0k(215) , + ko => ex2_pp2_0k(214) , + sum => ex2_pp2_0s(215) , + car => ex2_pp2_0c(214) ); + csa2_0_214: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(214) , + b => ex2_pp1_0s(214) , + c => ex2_pp1_1c(214) , + d => ex2_pp1_1s(214) , + ki => ex2_pp2_0k(214) , + ko => ex2_pp2_0k(213) , + sum => ex2_pp2_0s(214) , + car => ex2_pp2_0c(213) ); + csa2_0_213: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(213) , + b => ex2_pp1_0s(213) , + c => ex2_pp1_1c(213) , + d => ex2_pp1_1s(213) , + ki => ex2_pp2_0k(213) , + ko => ex2_pp2_0k(212) , + sum => ex2_pp2_0s(213) , + car => ex2_pp2_0c(212) ); + csa2_0_212: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(212) , + b => ex2_pp1_0s(212) , + c => ex2_pp1_1c(212) , + d => ex2_pp1_1s(212) , + ki => ex2_pp2_0k(212) , + ko => ex2_pp2_0k(211) , + sum => ex2_pp2_0s(212) , + car => ex2_pp2_0c(211) ); + csa2_0_211: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(211) , + b => ex2_pp1_0s(211) , + c => ex2_pp1_1c(211) , + d => ex2_pp1_1s(211) , + ki => ex2_pp2_0k(211) , + ko => ex2_pp2_0k(210) , + sum => ex2_pp2_0s(211) , + car => ex2_pp2_0c(210) ); + csa2_0_210: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(210) , + b => ex2_pp1_0s(210) , + c => ex2_pp1_1c(210) , + d => ex2_pp1_1s(210) , + ki => ex2_pp2_0k(210) , + ko => ex2_pp2_0k(209) , + sum => ex2_pp2_0s(210) , + car => ex2_pp2_0c(209) ); + csa2_0_209: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(209) , + b => ex2_pp1_0s(209) , + c => ex2_pp1_1c(209) , + d => ex2_pp1_1s(209) , + ki => ex2_pp2_0k(209) , + ko => ex2_pp2_0k(208) , + sum => ex2_pp2_0s(209) , + car => ex2_pp2_0c(208) ); + csa2_0_208: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(208) , + b => ex2_pp1_0s(208) , + c => ex2_pp1_1c(208) , + d => ex2_pp1_1s(208) , + ki => ex2_pp2_0k(208) , + ko => ex2_pp2_0k(207) , + sum => ex2_pp2_0s(208) , + car => ex2_pp2_0c(207) ); + csa2_0_207: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(207) , + b => ex2_pp1_0s(207) , + c => ex2_pp1_1c(207) , + d => ex2_pp1_1s(207) , + ki => ex2_pp2_0k(207) , + ko => ex2_pp2_0k(206) , + sum => ex2_pp2_0s(207) , + car => ex2_pp2_0c(206) ); + csa2_0_206: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(206) , + b => ex2_pp1_0s(206) , + c => ex2_pp1_1c(206) , + d => ex2_pp1_1s(206) , + ki => ex2_pp2_0k(206) , + ko => ex2_pp2_0k(205) , + sum => ex2_pp2_0s(206) , + car => ex2_pp2_0c(205) ); + csa2_0_205: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(205) , + b => ex2_pp1_0s(205) , + c => ex2_pp1_1c(205) , + d => ex2_pp1_1s(205) , + ki => ex2_pp2_0k(205) , + ko => ex2_pp2_0k(204) , + sum => ex2_pp2_0s(205) , + car => ex2_pp2_0c(204) ); + csa2_0_204: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(204) , + b => ex2_pp1_0s(204) , + c => ex2_pp1_1c(204) , + d => ex2_pp1_1s(204) , + ki => ex2_pp2_0k(204) , + ko => ex2_pp2_0k(203) , + sum => ex2_pp2_0s(204) , + car => ex2_pp2_0c(203) ); + csa2_0_203: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(203) , + b => ex2_pp1_0s(203) , + c => ex2_pp1_1c(203) , + d => ex2_pp1_1s(203) , + ki => ex2_pp2_0k(203) , + ko => ex2_pp2_0k(202) , + sum => ex2_pp2_0s(203) , + car => ex2_pp2_0c(202) ); + csa2_0_202: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(202) , + b => ex2_pp1_0s(202) , + c => ex2_pp1_1s(202) , + d => tidn , + ki => ex2_pp2_0k(202) , + ko => ex2_pp2_0k(201) , + sum => ex2_pp2_0s(202) , + car => ex2_pp2_0c(201) ); + csa2_0_201: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(201) , + b => ex2_pp1_0s(201) , + c => ex2_pp2_0k(201) , + sum => ex2_pp2_0s(201) , + car => ex2_pp2_0c(200) ); + csa2_0_200: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp1_0c(200) , + b => ex2_pp1_0s(200) , + sum => ex2_pp2_0s(200) , + car => ex2_pp2_0c(199) ); + csa2_0_199: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp1_0c(199) , + b => ex2_pp1_0s(199) , + sum => ex2_pp2_0s(199) , + car => ex2_pp2_0c(198) ); + ex2_pp2_0s(198) <= ex2_pp1_0s(198) ; + + + + ex2_pp2_1s(254) <= ex2_pp1_3s(254) ; + ex2_pp2_1s(253) <= tidn ; + ex2_pp2_1c(252) <= ex2_pp1_3s(252) ; + ex2_pp2_1s(252) <= ex2_pp1_3c(252) ; + ex2_pp2_1c(251) <= tidn ; + ex2_pp2_1s(251) <= ex2_pp1_3s(251) ; + ex2_pp2_1c(250) <= tidn ; + ex2_pp2_1s(250) <= ex2_pp1_3s(250) ; + ex2_pp2_1c(249) <= ex2_pp1_3s(249) ; + ex2_pp2_1s(249) <= ex2_pp1_3c(249) ; + ex2_pp2_1c(248) <= tidn ; + csa2_1_248: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2s(248) , + b => ex2_pp1_3c(248) , + c => ex2_pp1_3s(248) , + sum => ex2_pp2_1s(248) , + car => ex2_pp2_1c(247) ); + csa2_1_247: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp1_3c(247) , + b => ex2_pp1_3s(247) , + sum => ex2_pp2_1s(247) , + car => ex2_pp2_1c(246) ); + ex2_pp2_1k(246) <= tidn ; + csa2_1_246: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(246) , + b => ex2_pp1_2s(246) , + c => ex2_pp1_3c(246) , + d => ex2_pp1_3s(246) , + ki => ex2_pp2_1k(246) , + ko => ex2_pp2_1k(245) , + sum => ex2_pp2_1s(246) , + car => ex2_pp2_1c(245) ); + csa2_1_245: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2s(245) , + b => ex2_pp1_3c(245) , + c => ex2_pp1_3s(245) , + d => tidn , + ki => ex2_pp2_1k(245) , + ko => ex2_pp2_1k(244) , + sum => ex2_pp2_1s(245) , + car => ex2_pp2_1c(244) ); + csa2_1_244: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2s(244) , + b => ex2_pp1_3c(244) , + c => ex2_pp1_3s(244) , + d => tidn , + ki => ex2_pp2_1k(244) , + ko => ex2_pp2_1k(243) , + sum => ex2_pp2_1s(244) , + car => ex2_pp2_1c(243) ); + csa2_1_243: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(243) , + b => ex2_pp1_2s(243) , + c => ex2_pp1_3c(243) , + d => ex2_pp1_3s(243) , + ki => ex2_pp2_1k(243) , + ko => ex2_pp2_1k(242) , + sum => ex2_pp2_1s(243) , + car => ex2_pp2_1c(242) ); + csa2_1_242: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(242) , + b => ex2_pp1_2s(242) , + c => ex2_pp1_3c(242) , + d => ex2_pp1_3s(242) , + ki => ex2_pp2_1k(242) , + ko => ex2_pp2_1k(241) , + sum => ex2_pp2_1s(242) , + car => ex2_pp2_1c(241) ); + csa2_1_241: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(241) , + b => ex2_pp1_2s(241) , + c => ex2_pp1_3c(241) , + d => ex2_pp1_3s(241) , + ki => ex2_pp2_1k(241) , + ko => ex2_pp2_1k(240) , + sum => ex2_pp2_1s(241) , + car => ex2_pp2_1c(240) ); + csa2_1_240: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(240) , + b => ex2_pp1_2s(240) , + c => ex2_pp1_3c(240) , + d => ex2_pp1_3s(240) , + ki => ex2_pp2_1k(240) , + ko => ex2_pp2_1k(239) , + sum => ex2_pp2_1s(240) , + car => ex2_pp2_1c(239) ); + csa2_1_239: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(239) , + b => ex2_pp1_2s(239) , + c => ex2_pp1_3c(239) , + d => ex2_pp1_3s(239) , + ki => ex2_pp2_1k(239) , + ko => ex2_pp2_1k(238) , + sum => ex2_pp2_1s(239) , + car => ex2_pp2_1c(238) ); + csa2_1_238: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(238) , + b => ex2_pp1_2s(238) , + c => ex2_pp1_3c(238) , + d => ex2_pp1_3s(238) , + ki => ex2_pp2_1k(238) , + ko => ex2_pp2_1k(237) , + sum => ex2_pp2_1s(238) , + car => ex2_pp2_1c(237) ); + csa2_1_237: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(237) , + b => ex2_pp1_2s(237) , + c => ex2_pp1_3c(237) , + d => ex2_pp1_3s(237) , + ki => ex2_pp2_1k(237) , + ko => ex2_pp2_1k(236) , + sum => ex2_pp2_1s(237) , + car => ex2_pp2_1c(236) ); + csa2_1_236: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(236) , + b => ex2_pp1_2s(236) , + c => ex2_pp1_3c(236) , + d => ex2_pp1_3s(236) , + ki => ex2_pp2_1k(236) , + ko => ex2_pp2_1k(235) , + sum => ex2_pp2_1s(236) , + car => ex2_pp2_1c(235) ); + csa2_1_235: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(235) , + b => ex2_pp1_2s(235) , + c => ex2_pp1_3c(235) , + d => ex2_pp1_3s(235) , + ki => ex2_pp2_1k(235) , + ko => ex2_pp2_1k(234) , + sum => ex2_pp2_1s(235) , + car => ex2_pp2_1c(234) ); + csa2_1_234: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(234) , + b => ex2_pp1_2s(234) , + c => ex2_pp1_3c(234) , + d => ex2_pp1_3s(234) , + ki => ex2_pp2_1k(234) , + ko => ex2_pp2_1k(233) , + sum => ex2_pp2_1s(234) , + car => ex2_pp2_1c(233) ); + csa2_1_233: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(233) , + b => ex2_pp1_2s(233) , + c => ex2_pp1_3c(233) , + d => ex2_pp1_3s(233) , + ki => ex2_pp2_1k(233) , + ko => ex2_pp2_1k(232) , + sum => ex2_pp2_1s(233) , + car => ex2_pp2_1c(232) ); + csa2_1_232: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(232) , + b => ex2_pp1_2s(232) , + c => ex2_pp1_3c(232) , + d => ex2_pp1_3s(232) , + ki => ex2_pp2_1k(232) , + ko => ex2_pp2_1k(231) , + sum => ex2_pp2_1s(232) , + car => ex2_pp2_1c(231) ); + csa2_1_231: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(231) , + b => ex2_pp1_2s(231) , + c => ex2_pp1_3c(231) , + d => ex2_pp1_3s(231) , + ki => ex2_pp2_1k(231) , + ko => ex2_pp2_1k(230) , + sum => ex2_pp2_1s(231) , + car => ex2_pp2_1c(230) ); + csa2_1_230: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(230) , + b => ex2_pp1_2s(230) , + c => ex2_pp1_3c(230) , + d => ex2_pp1_3s(230) , + ki => ex2_pp2_1k(230) , + ko => ex2_pp2_1k(229) , + sum => ex2_pp2_1s(230) , + car => ex2_pp2_1c(229) ); + csa2_1_229: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(229) , + b => ex2_pp1_2s(229) , + c => ex2_pp1_3c(229) , + d => ex2_pp1_3s(229) , + ki => ex2_pp2_1k(229) , + ko => ex2_pp2_1k(228) , + sum => ex2_pp2_1s(229) , + car => ex2_pp2_1c(228) ); + csa2_1_228: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(228) , + b => ex2_pp1_2s(228) , + c => ex2_pp1_3c(228) , + d => ex2_pp1_3s(228) , + ki => ex2_pp2_1k(228) , + ko => ex2_pp2_1k(227) , + sum => ex2_pp2_1s(228) , + car => ex2_pp2_1c(227) ); + csa2_1_227: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(227) , + b => ex2_pp1_2s(227) , + c => ex2_pp1_3c(227) , + d => ex2_pp1_3s(227) , + ki => ex2_pp2_1k(227) , + ko => ex2_pp2_1k(226) , + sum => ex2_pp2_1s(227) , + car => ex2_pp2_1c(226) ); + csa2_1_226: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(226) , + b => ex2_pp1_2s(226) , + c => ex2_pp1_3c(226) , + d => ex2_pp1_3s(226) , + ki => ex2_pp2_1k(226) , + ko => ex2_pp2_1k(225) , + sum => ex2_pp2_1s(226) , + car => ex2_pp2_1c(225) ); + csa2_1_225: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(225) , + b => ex2_pp1_2s(225) , + c => ex2_pp1_3c(225) , + d => ex2_pp1_3s(225) , + ki => ex2_pp2_1k(225) , + ko => ex2_pp2_1k(224) , + sum => ex2_pp2_1s(225) , + car => ex2_pp2_1c(224) ); + csa2_1_224: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(224) , + b => ex2_pp1_2s(224) , + c => ex2_pp1_3c(224) , + d => ex2_pp1_3s(224) , + ki => ex2_pp2_1k(224) , + ko => ex2_pp2_1k(223) , + sum => ex2_pp2_1s(224) , + car => ex2_pp2_1c(223) ); + csa2_1_223: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(223) , + b => ex2_pp1_2s(223) , + c => ex2_pp1_3c(223) , + d => ex2_pp1_3s(223) , + ki => ex2_pp2_1k(223) , + ko => ex2_pp2_1k(222) , + sum => ex2_pp2_1s(223) , + car => ex2_pp2_1c(222) ); + csa2_1_222: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(222) , + b => ex2_pp1_2s(222) , + c => ex2_pp1_3c(222) , + d => ex2_pp1_3s(222) , + ki => ex2_pp2_1k(222) , + ko => ex2_pp2_1k(221) , + sum => ex2_pp2_1s(222) , + car => ex2_pp2_1c(221) ); + csa2_1_221: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(221) , + b => ex2_pp1_2s(221) , + c => ex2_pp1_3c(221) , + d => ex2_pp1_3s(221) , + ki => ex2_pp2_1k(221) , + ko => ex2_pp2_1k(220) , + sum => ex2_pp2_1s(221) , + car => ex2_pp2_1c(220) ); + csa2_1_220: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(220) , + b => ex2_pp1_2s(220) , + c => ex2_pp1_3c(220) , + d => ex2_pp1_3s(220) , + ki => ex2_pp2_1k(220) , + ko => ex2_pp2_1k(219) , + sum => ex2_pp2_1s(220) , + car => ex2_pp2_1c(219) ); + csa2_1_219: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(219) , + b => ex2_pp1_2s(219) , + c => ex2_pp1_3c(219) , + d => ex2_pp1_3s(219) , + ki => ex2_pp2_1k(219) , + ko => ex2_pp2_1k(218) , + sum => ex2_pp2_1s(219) , + car => ex2_pp2_1c(218) ); + csa2_1_218: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(218) , + b => ex2_pp1_2s(218) , + c => ex2_pp1_3c(218) , + d => ex2_pp1_3s(218) , + ki => ex2_pp2_1k(218) , + ko => ex2_pp2_1k(217) , + sum => ex2_pp2_1s(218) , + car => ex2_pp2_1c(217) ); + csa2_1_217: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(217) , + b => ex2_pp1_2s(217) , + c => ex2_pp1_3c(217) , + d => ex2_pp1_3s(217) , + ki => ex2_pp2_1k(217) , + ko => ex2_pp2_1k(216) , + sum => ex2_pp2_1s(217) , + car => ex2_pp2_1c(216) ); + csa2_1_216: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(216) , + b => ex2_pp1_2s(216) , + c => ex2_pp1_3c(216) , + d => ex2_pp1_3s(216) , + ki => ex2_pp2_1k(216) , + ko => ex2_pp2_1k(215) , + sum => ex2_pp2_1s(216) , + car => ex2_pp2_1c(215) ); + csa2_1_215: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(215) , + b => ex2_pp1_2s(215) , + c => ex2_pp1_3c(215) , + d => ex2_pp1_3s(215) , + ki => ex2_pp2_1k(215) , + ko => ex2_pp2_1k(214) , + sum => ex2_pp2_1s(215) , + car => ex2_pp2_1c(214) ); + csa2_1_214: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(214) , + b => ex2_pp1_2s(214) , + c => ex2_pp1_3s(214) , + d => tidn , + ki => ex2_pp2_1k(214) , + ko => ex2_pp2_1k(213) , + sum => ex2_pp2_1s(214) , + car => ex2_pp2_1c(213) ); + csa2_1_213: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(213) , + b => ex2_pp1_2s(213) , + c => ex2_pp2_1k(213) , + sum => ex2_pp2_1s(213) , + car => ex2_pp2_1c(212) ); + csa2_1_212: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp1_2c(212) , + b => ex2_pp1_2s(212) , + sum => ex2_pp2_1s(212) , + car => ex2_pp2_1c(211) ); + csa2_1_211: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp1_2c(211) , + b => ex2_pp1_2s(211) , + sum => ex2_pp2_1s(211) , + car => ex2_pp2_1c(210) ); + csa2_1_210: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp1_2c(210) , + b => ex2_pp1_2s(210) , + sum => ex2_pp2_1s(210) , + car => ex2_pp2_1c(209) ); + csa2_1_209: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp1_2c(209) , + b => ex2_pp1_2s(209) , + sum => ex2_pp2_1s(209) , + car => ex2_pp2_1c(208) ); + ex2_pp2_1s(208) <= ex2_pp1_2s(208) ; + + + + + csa2_2_264: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp1_5c(264) , + b => ex2_pp1_5s(264) , + sum => ex2_pp2_2s(264) , + car => ex2_pp2_2c(263) ); + ex2_pp2_2s(263) <= ex2_pp1_5s(263) ; + ex2_pp2_2c(262) <= tidn ; + ex2_pp2_2s(262) <= ex2_pp1_5s(262) ; + ex2_pp2_2c(261) <= ex2_pp1_5s(261) ; + ex2_pp2_2s(261) <= ex2_pp1_5c(261) ; + ex2_pp2_2c(260) <= tidn ; + csa2_2_260: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4s(260) , + b => ex2_pp1_5c(260) , + c => ex2_pp1_5s(260) , + sum => ex2_pp2_2s(260) , + car => ex2_pp2_2c(259) ); + csa2_2_259: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp1_5c(259) , + b => ex2_pp1_5s(259) , + sum => ex2_pp2_2s(259) , + car => ex2_pp2_2c(258) ); + ex2_pp2_2k(258) <= tidn ; + csa2_2_258: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(258) , + b => ex2_pp1_4s(258) , + c => ex2_pp1_5c(258) , + d => ex2_pp1_5s(258) , + ki => ex2_pp2_2k(258) , + ko => ex2_pp2_2k(257) , + sum => ex2_pp2_2s(258) , + car => ex2_pp2_2c(257) ); + csa2_2_257: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4s(257) , + b => ex2_pp1_5c(257) , + c => ex2_pp1_5s(257) , + d => tidn , + ki => ex2_pp2_2k(257) , + ko => ex2_pp2_2k(256) , + sum => ex2_pp2_2s(257) , + car => ex2_pp2_2c(256) ); + csa2_2_256: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4s(256) , + b => ex2_pp1_5c(256) , + c => ex2_pp1_5s(256) , + d => tidn , + ki => ex2_pp2_2k(256) , + ko => ex2_pp2_2k(255) , + sum => ex2_pp2_2s(256) , + car => ex2_pp2_2c(255) ); + csa2_2_255: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(255) , + b => ex2_pp1_4s(255) , + c => ex2_pp1_5c(255) , + d => ex2_pp1_5s(255) , + ki => ex2_pp2_2k(255) , + ko => ex2_pp2_2k(254) , + sum => ex2_pp2_2s(255) , + car => ex2_pp2_2c(254) ); + csa2_2_254: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(254) , + b => ex2_pp1_4s(254) , + c => ex2_pp1_5c(254) , + d => ex2_pp1_5s(254) , + ki => ex2_pp2_2k(254) , + ko => ex2_pp2_2k(253) , + sum => ex2_pp2_2s(254) , + car => ex2_pp2_2c(253) ); + csa2_2_253: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(253) , + b => ex2_pp1_4s(253) , + c => ex2_pp1_5c(253) , + d => ex2_pp1_5s(253) , + ki => ex2_pp2_2k(253) , + ko => ex2_pp2_2k(252) , + sum => ex2_pp2_2s(253) , + car => ex2_pp2_2c(252) ); + csa2_2_252: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(252) , + b => ex2_pp1_4s(252) , + c => ex2_pp1_5c(252) , + d => ex2_pp1_5s(252) , + ki => ex2_pp2_2k(252) , + ko => ex2_pp2_2k(251) , + sum => ex2_pp2_2s(252) , + car => ex2_pp2_2c(251) ); + csa2_2_251: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(251) , + b => ex2_pp1_4s(251) , + c => ex2_pp1_5c(251) , + d => ex2_pp1_5s(251) , + ki => ex2_pp2_2k(251) , + ko => ex2_pp2_2k(250) , + sum => ex2_pp2_2s(251) , + car => ex2_pp2_2c(250) ); + csa2_2_250: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(250) , + b => ex2_pp1_4s(250) , + c => ex2_pp1_5c(250) , + d => ex2_pp1_5s(250) , + ki => ex2_pp2_2k(250) , + ko => ex2_pp2_2k(249) , + sum => ex2_pp2_2s(250) , + car => ex2_pp2_2c(249) ); + csa2_2_249: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(249) , + b => ex2_pp1_4s(249) , + c => ex2_pp1_5c(249) , + d => ex2_pp1_5s(249) , + ki => ex2_pp2_2k(249) , + ko => ex2_pp2_2k(248) , + sum => ex2_pp2_2s(249) , + car => ex2_pp2_2c(248) ); + csa2_2_248: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(248) , + b => ex2_pp1_4s(248) , + c => ex2_pp1_5c(248) , + d => ex2_pp1_5s(248) , + ki => ex2_pp2_2k(248) , + ko => ex2_pp2_2k(247) , + sum => ex2_pp2_2s(248) , + car => ex2_pp2_2c(247) ); + csa2_2_247: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(247) , + b => ex2_pp1_4s(247) , + c => ex2_pp1_5c(247) , + d => ex2_pp1_5s(247) , + ki => ex2_pp2_2k(247) , + ko => ex2_pp2_2k(246) , + sum => ex2_pp2_2s(247) , + car => ex2_pp2_2c(246) ); + csa2_2_246: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(246) , + b => ex2_pp1_4s(246) , + c => ex2_pp1_5c(246) , + d => ex2_pp1_5s(246) , + ki => ex2_pp2_2k(246) , + ko => ex2_pp2_2k(245) , + sum => ex2_pp2_2s(246) , + car => ex2_pp2_2c(245) ); + csa2_2_245: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(245) , + b => ex2_pp1_4s(245) , + c => ex2_pp1_5c(245) , + d => ex2_pp1_5s(245) , + ki => ex2_pp2_2k(245) , + ko => ex2_pp2_2k(244) , + sum => ex2_pp2_2s(245) , + car => ex2_pp2_2c(244) ); + csa2_2_244: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(244) , + b => ex2_pp1_4s(244) , + c => ex2_pp1_5c(244) , + d => ex2_pp1_5s(244) , + ki => ex2_pp2_2k(244) , + ko => ex2_pp2_2k(243) , + sum => ex2_pp2_2s(244) , + car => ex2_pp2_2c(243) ); + csa2_2_243: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(243) , + b => ex2_pp1_4s(243) , + c => ex2_pp1_5c(243) , + d => ex2_pp1_5s(243) , + ki => ex2_pp2_2k(243) , + ko => ex2_pp2_2k(242) , + sum => ex2_pp2_2s(243) , + car => ex2_pp2_2c(242) ); + csa2_2_242: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(242) , + b => ex2_pp1_4s(242) , + c => ex2_pp1_5c(242) , + d => ex2_pp1_5s(242) , + ki => ex2_pp2_2k(242) , + ko => ex2_pp2_2k(241) , + sum => ex2_pp2_2s(242) , + car => ex2_pp2_2c(241) ); + csa2_2_241: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(241) , + b => ex2_pp1_4s(241) , + c => ex2_pp1_5c(241) , + d => ex2_pp1_5s(241) , + ki => ex2_pp2_2k(241) , + ko => ex2_pp2_2k(240) , + sum => ex2_pp2_2s(241) , + car => ex2_pp2_2c(240) ); + csa2_2_240: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(240) , + b => ex2_pp1_4s(240) , + c => ex2_pp1_5c(240) , + d => ex2_pp1_5s(240) , + ki => ex2_pp2_2k(240) , + ko => ex2_pp2_2k(239) , + sum => ex2_pp2_2s(240) , + car => ex2_pp2_2c(239) ); + csa2_2_239: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(239) , + b => ex2_pp1_4s(239) , + c => ex2_pp1_5c(239) , + d => ex2_pp1_5s(239) , + ki => ex2_pp2_2k(239) , + ko => ex2_pp2_2k(238) , + sum => ex2_pp2_2s(239) , + car => ex2_pp2_2c(238) ); + csa2_2_238: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(238) , + b => ex2_pp1_4s(238) , + c => ex2_pp1_5c(238) , + d => ex2_pp1_5s(238) , + ki => ex2_pp2_2k(238) , + ko => ex2_pp2_2k(237) , + sum => ex2_pp2_2s(238) , + car => ex2_pp2_2c(237) ); + csa2_2_237: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(237) , + b => ex2_pp1_4s(237) , + c => ex2_pp1_5c(237) , + d => ex2_pp1_5s(237) , + ki => ex2_pp2_2k(237) , + ko => ex2_pp2_2k(236) , + sum => ex2_pp2_2s(237) , + car => ex2_pp2_2c(236) ); + csa2_2_236: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(236) , + b => ex2_pp1_4s(236) , + c => ex2_pp1_5c(236) , + d => ex2_pp1_5s(236) , + ki => ex2_pp2_2k(236) , + ko => ex2_pp2_2k(235) , + sum => ex2_pp2_2s(236) , + car => ex2_pp2_2c(235) ); + csa2_2_235: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(235) , + b => ex2_pp1_4s(235) , + c => ex2_pp1_5c(235) , + d => ex2_pp1_5s(235) , + ki => ex2_pp2_2k(235) , + ko => ex2_pp2_2k(234) , + sum => ex2_pp2_2s(235) , + car => ex2_pp2_2c(234) ); + csa2_2_234: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(234) , + b => ex2_pp1_4s(234) , + c => ex2_pp1_5c(234) , + d => ex2_pp1_5s(234) , + ki => ex2_pp2_2k(234) , + ko => ex2_pp2_2k(233) , + sum => ex2_pp2_2s(234) , + car => ex2_pp2_2c(233) ); + csa2_2_233: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(233) , + b => ex2_pp1_4s(233) , + c => ex2_pp1_5c(233) , + d => ex2_pp1_5s(233) , + ki => ex2_pp2_2k(233) , + ko => ex2_pp2_2k(232) , + sum => ex2_pp2_2s(233) , + car => ex2_pp2_2c(232) ); + csa2_2_232: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(232) , + b => ex2_pp1_4s(232) , + c => ex2_pp1_5c(232) , + d => ex2_pp1_5s(232) , + ki => ex2_pp2_2k(232) , + ko => ex2_pp2_2k(231) , + sum => ex2_pp2_2s(232) , + car => ex2_pp2_2c(231) ); + csa2_2_231: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(231) , + b => ex2_pp1_4s(231) , + c => ex2_pp1_5c(231) , + d => ex2_pp1_5s(231) , + ki => ex2_pp2_2k(231) , + ko => ex2_pp2_2k(230) , + sum => ex2_pp2_2s(231) , + car => ex2_pp2_2c(230) ); + csa2_2_230: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(230) , + b => ex2_pp1_4s(230) , + c => ex2_pp1_5c(230) , + d => ex2_pp1_5s(230) , + ki => ex2_pp2_2k(230) , + ko => ex2_pp2_2k(229) , + sum => ex2_pp2_2s(230) , + car => ex2_pp2_2c(229) ); + csa2_2_229: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(229) , + b => ex2_pp1_4s(229) , + c => ex2_pp1_5c(229) , + d => ex2_pp1_5s(229) , + ki => ex2_pp2_2k(229) , + ko => ex2_pp2_2k(228) , + sum => ex2_pp2_2s(229) , + car => ex2_pp2_2c(228) ); + csa2_2_228: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(228) , + b => ex2_pp1_4s(228) , + c => ex2_pp1_5c(228) , + d => ex2_pp1_5s(228) , + ki => ex2_pp2_2k(228) , + ko => ex2_pp2_2k(227) , + sum => ex2_pp2_2s(228) , + car => ex2_pp2_2c(227) ); + csa2_2_227: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(227) , + b => ex2_pp1_4s(227) , + c => ex2_pp1_5c(227) , + d => ex2_pp1_5s(227) , + ki => ex2_pp2_2k(227) , + ko => ex2_pp2_2k(226) , + sum => ex2_pp2_2s(227) , + car => ex2_pp2_2c(226) ); + csa2_2_226: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(226) , + b => ex2_pp1_4s(226) , + c => ex2_pp1_5s(226) , + d => tidn , + ki => ex2_pp2_2k(226) , + ko => ex2_pp2_2k(225) , + sum => ex2_pp2_2s(226) , + car => ex2_pp2_2c(225) ); + csa2_2_225: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(225) , + b => ex2_pp1_4s(225) , + c => ex2_pp2_2k(225) , + sum => ex2_pp2_2s(225) , + car => ex2_pp2_2c(224) ); + csa2_2_224: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp1_4c(224) , + b => ex2_pp1_4s(224) , + sum => ex2_pp2_2s(224) , + car => ex2_pp2_2c(223) ); + csa2_2_223: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp1_4c(223) , + b => ex2_pp1_4s(223) , + sum => ex2_pp2_2s(223) , + car => ex2_pp2_2c(222) ); + csa2_2_222: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp1_4c(222) , + b => ex2_pp1_4s(222) , + sum => ex2_pp2_2s(222) , + car => ex2_pp2_2c(221) ); + csa2_2_221: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp1_4c(221) , + b => ex2_pp1_4s(221) , + sum => ex2_pp2_2s(221) , + car => ex2_pp2_2c(220) ); + ex2_pp2_2s(220) <= ex2_pp1_4s(220) ; + + + + + + ex3_pp2_0s_din(198 to 242) <= ex2_pp2_0s(198 to 242) ; + ex3_pp2_0c_din(198 to 240) <= ex2_pp2_0c(198 to 240) ; + ex3_pp2_1s_din(208 to 254) <= ex2_pp2_1s(208 to 254) ; + ex3_pp2_1c_din(208 to 252) <= ex2_pp2_1c(208 to 252) ; + ex3_pp2_2s_din(220 to 264) <= ex2_pp2_2s(220 to 264) ; + ex3_pp2_2c_din(220 to 263) <= ex2_pp2_2c(220 to 263) ; + + + + u_0s_qi: ex3_pp2_0s (198 to 242) <= not ex3_pp2_0s_q_b(198 to 242) ; + u_0c_qi: ex3_pp2_0c (198 to 240) <= not ex3_pp2_0c_q_b(198 to 240) ; + + u_1s_qi: ex3_pp2_1s_x (208 to 254) <= not ex3_pp2_1s_q_b(208 to 254) ; + u_1c_qi: ex3_pp2_1c_x (208 to 252) <= not ex3_pp2_1c_q_b(208 to 252) ; + u_2s_qi: ex3_pp2_2s_x (220 to 264) <= not ex3_pp2_2s_q_b(220 to 264) ; + u_2c_qi: ex3_pp2_2c_x (220 to 263) <= not ex3_pp2_2c_q_b(220 to 263) ; + + u_1s_mini: ex3_pp2_1s_x_b(208 to 254) <= not ex3_pp2_1s_x (208 to 254) ; + u_1c_mini: ex3_pp2_1c_x_b(208 to 252) <= not ex3_pp2_1c_x (208 to 252) ; + u_2s_mini: ex3_pp2_2s_x_b(220 to 264) <= not ex3_pp2_2s_x (220 to 264) ; + u_2c_mini: ex3_pp2_2c_x_b(220 to 263) <= not ex3_pp2_2c_x (220 to 263) ; + + u_1s_mind: ex3_pp2_1s (208 to 254) <= not ex3_pp2_1s_x_b(208 to 254) ; + u_1c_mind: ex3_pp2_1c (208 to 252) <= not ex3_pp2_1c_x_b(208 to 252) ; + u_2s_mind: ex3_pp2_2s (220 to 264) <= not ex3_pp2_2s_x_b(220 to 264) ; + u_2c_mind: ex3_pp2_2c (220 to 263) <= not ex3_pp2_2c_x_b(220 to 263) ; + + + + + + + + + + ex3_pp3_0s(252) <= ex3_pp2_1c(252) ; + ex3_pp3_0s(251) <= tidn ; + ex3_pp3_0s(250) <= tidn ; + ex3_pp3_0s(249) <= ex3_pp2_1c(249) ; + ex3_pp3_0s(248) <= tidn ; + ex3_pp3_0s(247) <= ex3_pp2_1c(247) ; + ex3_pp3_0s(246) <= ex3_pp2_1c(246) ; + ex3_pp3_0s(245) <= ex3_pp2_1c(245) ; + ex3_pp3_0s(244) <= ex3_pp2_1c(244) ; + ex3_pp3_0s(243) <= ex3_pp2_1c(243) ; + ex3_pp3_0c(242) <= ex3_pp2_1c(242) ; + ex3_pp3_0s(242) <= ex3_pp2_0s(242) ; + ex3_pp3_0c(241) <= tidn ; + ex3_pp3_0s(241) <= ex3_pp2_1c(241) ; + ex3_pp3_0c(240) <= tidn ; + csa3_0_240: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_0c(240) , + b => ex3_pp2_0s(240) , + c => ex3_pp2_1c(240) , + sum => ex3_pp3_0s(240) , + car => ex3_pp3_0c(239) ); + csa3_0_239: entity work.xuq_alu_mult_csa22 port map( + a => ex3_pp2_0s(239) , + b => ex3_pp2_1c(239) , + sum => ex3_pp3_0s(239) , + car => ex3_pp3_0c(238) ); + csa3_0_238: entity work.xuq_alu_mult_csa22 port map( + a => ex3_pp2_0s(238) , + b => ex3_pp2_1c(238) , + sum => ex3_pp3_0s(238) , + car => ex3_pp3_0c(237) ); + csa3_0_237: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_0c(237) , + b => ex3_pp2_0s(237) , + c => ex3_pp2_1c(237) , + sum => ex3_pp3_0s(237) , + car => ex3_pp3_0c(236) ); + csa3_0_236: entity work.xuq_alu_mult_csa22 port map( + a => ex3_pp2_0s(236) , + b => ex3_pp2_1c(236) , + sum => ex3_pp3_0s(236) , + car => ex3_pp3_0c(235) ); + csa3_0_235: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_0c(235) , + b => ex3_pp2_0s(235) , + c => ex3_pp2_1c(235) , + sum => ex3_pp3_0s(235) , + car => ex3_pp3_0c(234) ); + csa3_0_234: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_0c(234) , + b => ex3_pp2_0s(234) , + c => ex3_pp2_1c(234) , + sum => ex3_pp3_0s(234) , + car => ex3_pp3_0c(233) ); + csa3_0_233: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_0c(233) , + b => ex3_pp2_0s(233) , + c => ex3_pp2_1c(233) , + sum => ex3_pp3_0s(233) , + car => ex3_pp3_0c(232) ); + csa3_0_232: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_0c(232) , + b => ex3_pp2_0s(232) , + c => ex3_pp2_1c(232) , + sum => ex3_pp3_0s(232) , + car => ex3_pp3_0c(231) ); + csa3_0_231: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_0c(231) , + b => ex3_pp2_0s(231) , + c => ex3_pp2_1c(231) , + sum => ex3_pp3_0s(231) , + car => ex3_pp3_0c(230) ); + csa3_0_230: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_0c(230) , + b => ex3_pp2_0s(230) , + c => ex3_pp2_1c(230) , + sum => ex3_pp3_0s(230) , + car => ex3_pp3_0c(229) ); + csa3_0_229: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_0c(229) , + b => ex3_pp2_0s(229) , + c => ex3_pp2_1c(229) , + sum => ex3_pp3_0s(229) , + car => ex3_pp3_0c(228) ); + csa3_0_228: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_0c(228) , + b => ex3_pp2_0s(228) , + c => ex3_pp2_1c(228) , + sum => ex3_pp3_0s(228) , + car => ex3_pp3_0c(227) ); + csa3_0_227: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_0c(227) , + b => ex3_pp2_0s(227) , + c => ex3_pp2_1c(227) , + sum => ex3_pp3_0s(227) , + car => ex3_pp3_0c(226) ); + csa3_0_226: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_0c(226) , + b => ex3_pp2_0s(226) , + c => ex3_pp2_1c(226) , + sum => ex3_pp3_0s(226) , + car => ex3_pp3_0c(225) ); + csa3_0_225: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_0c(225) , + b => ex3_pp2_0s(225) , + c => ex3_pp2_1c(225) , + sum => ex3_pp3_0s(225) , + car => ex3_pp3_0c(224) ); + csa3_0_224: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_0c(224) , + b => ex3_pp2_0s(224) , + c => ex3_pp2_1c(224) , + sum => ex3_pp3_0s(224) , + car => ex3_pp3_0c(223) ); + csa3_0_223: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_0c(223) , + b => ex3_pp2_0s(223) , + c => ex3_pp2_1c(223) , + sum => ex3_pp3_0s(223) , + car => ex3_pp3_0c(222) ); + csa3_0_222: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_0c(222) , + b => ex3_pp2_0s(222) , + c => ex3_pp2_1c(222) , + sum => ex3_pp3_0s(222) , + car => ex3_pp3_0c(221) ); + csa3_0_221: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_0c(221) , + b => ex3_pp2_0s(221) , + c => ex3_pp2_1c(221) , + sum => ex3_pp3_0s(221) , + car => ex3_pp3_0c(220) ); + csa3_0_220: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_0c(220) , + b => ex3_pp2_0s(220) , + c => ex3_pp2_1c(220) , + sum => ex3_pp3_0s(220) , + car => ex3_pp3_0c(219) ); + csa3_0_219: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_0c(219) , + b => ex3_pp2_0s(219) , + c => ex3_pp2_1c(219) , + sum => ex3_pp3_0s(219) , + car => ex3_pp3_0c(218) ); + csa3_0_218: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_0c(218) , + b => ex3_pp2_0s(218) , + c => ex3_pp2_1c(218) , + sum => ex3_pp3_0s(218) , + car => ex3_pp3_0c(217) ); + csa3_0_217: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_0c(217) , + b => ex3_pp2_0s(217) , + c => ex3_pp2_1c(217) , + sum => ex3_pp3_0s(217) , + car => ex3_pp3_0c(216) ); + csa3_0_216: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_0c(216) , + b => ex3_pp2_0s(216) , + c => ex3_pp2_1c(216) , + sum => ex3_pp3_0s(216) , + car => ex3_pp3_0c(215) ); + csa3_0_215: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_0c(215) , + b => ex3_pp2_0s(215) , + c => ex3_pp2_1c(215) , + sum => ex3_pp3_0s(215) , + car => ex3_pp3_0c(214) ); + csa3_0_214: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_0c(214) , + b => ex3_pp2_0s(214) , + c => ex3_pp2_1c(214) , + sum => ex3_pp3_0s(214) , + car => ex3_pp3_0c(213) ); + csa3_0_213: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_0c(213) , + b => ex3_pp2_0s(213) , + c => ex3_pp2_1c(213) , + sum => ex3_pp3_0s(213) , + car => ex3_pp3_0c(212) ); + csa3_0_212: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_0c(212) , + b => ex3_pp2_0s(212) , + c => ex3_pp2_1c(212) , + sum => ex3_pp3_0s(212) , + car => ex3_pp3_0c(211) ); + csa3_0_211: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_0c(211) , + b => ex3_pp2_0s(211) , + c => ex3_pp2_1c(211) , + sum => ex3_pp3_0s(211) , + car => ex3_pp3_0c(210) ); + csa3_0_210: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_0c(210) , + b => ex3_pp2_0s(210) , + c => ex3_pp2_1c(210) , + sum => ex3_pp3_0s(210) , + car => ex3_pp3_0c(209) ); + csa3_0_209: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_0c(209) , + b => ex3_pp2_0s(209) , + c => ex3_pp2_1c(209) , + sum => ex3_pp3_0s(209) , + car => ex3_pp3_0c(208) ); + csa3_0_208: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_0c(208) , + b => ex3_pp2_0s(208) , + c => ex3_pp2_1c(208) , + sum => ex3_pp3_0s(208) , + car => ex3_pp3_0c(207) ); + csa3_0_207: entity work.xuq_alu_mult_csa22 port map( + a => ex3_pp2_0c(207) , + b => ex3_pp2_0s(207) , + sum => ex3_pp3_0s(207) , + car => ex3_pp3_0c(206) ); + csa3_0_206: entity work.xuq_alu_mult_csa22 port map( + a => ex3_pp2_0c(206) , + b => ex3_pp2_0s(206) , + sum => ex3_pp3_0s(206) , + car => ex3_pp3_0c(205) ); + csa3_0_205: entity work.xuq_alu_mult_csa22 port map( + a => ex3_pp2_0c(205) , + b => ex3_pp2_0s(205) , + sum => ex3_pp3_0s(205) , + car => ex3_pp3_0c(204) ); + csa3_0_204: entity work.xuq_alu_mult_csa22 port map( + a => ex3_pp2_0c(204) , + b => ex3_pp2_0s(204) , + sum => ex3_pp3_0s(204) , + car => ex3_pp3_0c(203) ); + csa3_0_203: entity work.xuq_alu_mult_csa22 port map( + a => ex3_pp2_0c(203) , + b => ex3_pp2_0s(203) , + sum => ex3_pp3_0s(203) , + car => ex3_pp3_0c(202) ); + csa3_0_202: entity work.xuq_alu_mult_csa22 port map( + a => ex3_pp2_0c(202) , + b => ex3_pp2_0s(202) , + sum => ex3_pp3_0s(202) , + car => ex3_pp3_0c(201) ); + csa3_0_201: entity work.xuq_alu_mult_csa22 port map( + a => ex3_pp2_0c(201) , + b => ex3_pp2_0s(201) , + sum => ex3_pp3_0s(201) , + car => ex3_pp3_0c(200) ); + csa3_0_200: entity work.xuq_alu_mult_csa22 port map( + a => ex3_pp2_0c(200) , + b => ex3_pp2_0s(200) , + sum => ex3_pp3_0s(200) , + car => ex3_pp3_0c(199) ); + csa3_0_199: entity work.xuq_alu_mult_csa22 port map( + a => ex3_pp2_0c(199) , + b => ex3_pp2_0s(199) , + sum => ex3_pp3_0s(199) , + car => ex3_pp3_0c(198) ); + csa3_0_198: entity work.xuq_alu_mult_csa22 port map( + a => ex3_pp2_0c(198) , + b => ex3_pp2_0s(198) , + sum => ex3_pp3_0s(198) , + car => ex3_pp3_0c(197) ); + + + + ex3_pp3_1s(264) <= ex3_pp2_2s(264) ; + csa3_1_263: entity work.xuq_alu_mult_csa22 port map( + a => ex3_pp2_2c(263) , + b => ex3_pp2_2s(263) , + sum => ex3_pp3_1s(263) , + car => ex3_pp3_1c(262) ); + ex3_pp3_1s(262) <= ex3_pp2_2s(262) ; + ex3_pp3_1c(261) <= ex3_pp2_2s(261) ; + ex3_pp3_1s(261) <= ex3_pp2_2c(261) ; + ex3_pp3_1c(260) <= tidn ; + ex3_pp3_1s(260) <= ex3_pp2_2s(260) ; + ex3_pp3_1c(259) <= ex3_pp2_2s(259) ; + ex3_pp3_1s(259) <= ex3_pp2_2c(259) ; + ex3_pp3_1c(258) <= ex3_pp2_2s(258) ; + ex3_pp3_1s(258) <= ex3_pp2_2c(258) ; + ex3_pp3_1c(257) <= ex3_pp2_2s(257) ; + ex3_pp3_1s(257) <= ex3_pp2_2c(257) ; + ex3_pp3_1c(256) <= ex3_pp2_2s(256) ; + ex3_pp3_1s(256) <= ex3_pp2_2c(256) ; + ex3_pp3_1c(255) <= ex3_pp2_2s(255) ; + ex3_pp3_1s(255) <= ex3_pp2_2c(255) ; + ex3_pp3_1c(254) <= tidn ; + csa3_1_254: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(254) , + b => ex3_pp2_2c(254) , + c => ex3_pp2_2s(254) , + sum => ex3_pp3_1s(254) , + car => ex3_pp3_1c(253) ); + csa3_1_253: entity work.xuq_alu_mult_csa22 port map( + a => ex3_pp2_2c(253) , + b => ex3_pp2_2s(253) , + sum => ex3_pp3_1s(253) , + car => ex3_pp3_1c(252) ); + csa3_1_252: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(252) , + b => ex3_pp2_2c(252) , + c => ex3_pp2_2s(252) , + sum => ex3_pp3_1s(252) , + car => ex3_pp3_1c(251) ); + csa3_1_251: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(251) , + b => ex3_pp2_2c(251) , + c => ex3_pp2_2s(251) , + sum => ex3_pp3_1s(251) , + car => ex3_pp3_1c(250) ); + csa3_1_250: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(250) , + b => ex3_pp2_2c(250) , + c => ex3_pp2_2s(250) , + sum => ex3_pp3_1s(250) , + car => ex3_pp3_1c(249) ); + csa3_1_249: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(249) , + b => ex3_pp2_2c(249) , + c => ex3_pp2_2s(249) , + sum => ex3_pp3_1s(249) , + car => ex3_pp3_1c(248) ); + csa3_1_248: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(248) , + b => ex3_pp2_2c(248) , + c => ex3_pp2_2s(248) , + sum => ex3_pp3_1s(248) , + car => ex3_pp3_1c(247) ); + csa3_1_247: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(247) , + b => ex3_pp2_2c(247) , + c => ex3_pp2_2s(247) , + sum => ex3_pp3_1s(247) , + car => ex3_pp3_1c(246) ); + csa3_1_246: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(246) , + b => ex3_pp2_2c(246) , + c => ex3_pp2_2s(246) , + sum => ex3_pp3_1s(246) , + car => ex3_pp3_1c(245) ); + csa3_1_245: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(245) , + b => ex3_pp2_2c(245) , + c => ex3_pp2_2s(245) , + sum => ex3_pp3_1s(245) , + car => ex3_pp3_1c(244) ); + csa3_1_244: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(244) , + b => ex3_pp2_2c(244) , + c => ex3_pp2_2s(244) , + sum => ex3_pp3_1s(244) , + car => ex3_pp3_1c(243) ); + csa3_1_243: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(243) , + b => ex3_pp2_2c(243) , + c => ex3_pp2_2s(243) , + sum => ex3_pp3_1s(243) , + car => ex3_pp3_1c(242) ); + csa3_1_242: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(242) , + b => ex3_pp2_2c(242) , + c => ex3_pp2_2s(242) , + sum => ex3_pp3_1s(242) , + car => ex3_pp3_1c(241) ); + csa3_1_241: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(241) , + b => ex3_pp2_2c(241) , + c => ex3_pp2_2s(241) , + sum => ex3_pp3_1s(241) , + car => ex3_pp3_1c(240) ); + csa3_1_240: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(240) , + b => ex3_pp2_2c(240) , + c => ex3_pp2_2s(240) , + sum => ex3_pp3_1s(240) , + car => ex3_pp3_1c(239) ); + csa3_1_239: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(239) , + b => ex3_pp2_2c(239) , + c => ex3_pp2_2s(239) , + sum => ex3_pp3_1s(239) , + car => ex3_pp3_1c(238) ); + csa3_1_238: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(238) , + b => ex3_pp2_2c(238) , + c => ex3_pp2_2s(238) , + sum => ex3_pp3_1s(238) , + car => ex3_pp3_1c(237) ); + csa3_1_237: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(237) , + b => ex3_pp2_2c(237) , + c => ex3_pp2_2s(237) , + sum => ex3_pp3_1s(237) , + car => ex3_pp3_1c(236) ); + csa3_1_236: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(236) , + b => ex3_pp2_2c(236) , + c => ex3_pp2_2s(236) , + sum => ex3_pp3_1s(236) , + car => ex3_pp3_1c(235) ); + csa3_1_235: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(235) , + b => ex3_pp2_2c(235) , + c => ex3_pp2_2s(235) , + sum => ex3_pp3_1s(235) , + car => ex3_pp3_1c(234) ); + csa3_1_234: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(234) , + b => ex3_pp2_2c(234) , + c => ex3_pp2_2s(234) , + sum => ex3_pp3_1s(234) , + car => ex3_pp3_1c(233) ); + csa3_1_233: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(233) , + b => ex3_pp2_2c(233) , + c => ex3_pp2_2s(233) , + sum => ex3_pp3_1s(233) , + car => ex3_pp3_1c(232) ); + csa3_1_232: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(232) , + b => ex3_pp2_2c(232) , + c => ex3_pp2_2s(232) , + sum => ex3_pp3_1s(232) , + car => ex3_pp3_1c(231) ); + csa3_1_231: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(231) , + b => ex3_pp2_2c(231) , + c => ex3_pp2_2s(231) , + sum => ex3_pp3_1s(231) , + car => ex3_pp3_1c(230) ); + csa3_1_230: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(230) , + b => ex3_pp2_2c(230) , + c => ex3_pp2_2s(230) , + sum => ex3_pp3_1s(230) , + car => ex3_pp3_1c(229) ); + csa3_1_229: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(229) , + b => ex3_pp2_2c(229) , + c => ex3_pp2_2s(229) , + sum => ex3_pp3_1s(229) , + car => ex3_pp3_1c(228) ); + csa3_1_228: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(228) , + b => ex3_pp2_2c(228) , + c => ex3_pp2_2s(228) , + sum => ex3_pp3_1s(228) , + car => ex3_pp3_1c(227) ); + csa3_1_227: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(227) , + b => ex3_pp2_2c(227) , + c => ex3_pp2_2s(227) , + sum => ex3_pp3_1s(227) , + car => ex3_pp3_1c(226) ); + csa3_1_226: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(226) , + b => ex3_pp2_2c(226) , + c => ex3_pp2_2s(226) , + sum => ex3_pp3_1s(226) , + car => ex3_pp3_1c(225) ); + csa3_1_225: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(225) , + b => ex3_pp2_2c(225) , + c => ex3_pp2_2s(225) , + sum => ex3_pp3_1s(225) , + car => ex3_pp3_1c(224) ); + csa3_1_224: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(224) , + b => ex3_pp2_2c(224) , + c => ex3_pp2_2s(224) , + sum => ex3_pp3_1s(224) , + car => ex3_pp3_1c(223) ); + csa3_1_223: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(223) , + b => ex3_pp2_2c(223) , + c => ex3_pp2_2s(223) , + sum => ex3_pp3_1s(223) , + car => ex3_pp3_1c(222) ); + csa3_1_222: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(222) , + b => ex3_pp2_2c(222) , + c => ex3_pp2_2s(222) , + sum => ex3_pp3_1s(222) , + car => ex3_pp3_1c(221) ); + csa3_1_221: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(221) , + b => ex3_pp2_2c(221) , + c => ex3_pp2_2s(221) , + sum => ex3_pp3_1s(221) , + car => ex3_pp3_1c(220) ); + csa3_1_220: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(220) , + b => ex3_pp2_2c(220) , + c => ex3_pp2_2s(220) , + sum => ex3_pp3_1s(220) , + car => ex3_pp3_1c(219) ); + ex3_pp3_1s(219) <= ex3_pp2_1s(219) ; + ex3_pp3_1s(218) <= ex3_pp2_1s(218) ; + ex3_pp3_1s(217) <= ex3_pp2_1s(217) ; + ex3_pp3_1s(216) <= ex3_pp2_1s(216) ; + ex3_pp3_1s(215) <= ex3_pp2_1s(215) ; + ex3_pp3_1s(214) <= ex3_pp2_1s(214) ; + ex3_pp3_1s(213) <= ex3_pp2_1s(213) ; + ex3_pp3_1s(212) <= ex3_pp2_1s(212) ; + ex3_pp3_1s(211) <= ex3_pp2_1s(211) ; + ex3_pp3_1s(210) <= ex3_pp2_1s(210) ; + ex3_pp3_1s(209) <= ex3_pp2_1s(209) ; + ex3_pp3_1s(208) <= ex3_pp2_1s(208) ; + + + + + + + + ex3_pp4_0s(264) <= ex3_pp3_1s(264) ; + ex3_pp4_0s(263) <= ex3_pp3_1s(263) ; + ex3_pp4_0c(262) <= ex3_pp3_1s(262) ; + ex3_pp4_0s(262) <= ex3_pp3_1c(262) ; + ex3_pp4_0c(261) <= ex3_pp3_1s(261) ; + ex3_pp4_0s(261) <= ex3_pp3_1c(261) ; + ex3_pp4_0c(260) <= tidn ; + ex3_pp4_0s(260) <= ex3_pp3_1s(260) ; + ex3_pp4_0c(259) <= ex3_pp3_1s(259) ; + ex3_pp4_0s(259) <= ex3_pp3_1c(259) ; + ex3_pp4_0c(258) <= ex3_pp3_1s(258) ; + ex3_pp4_0s(258) <= ex3_pp3_1c(258) ; + ex3_pp4_0c(257) <= ex3_pp3_1s(257) ; + ex3_pp4_0s(257) <= ex3_pp3_1c(257) ; + ex3_pp4_0c(256) <= ex3_pp3_1s(256) ; + ex3_pp4_0s(256) <= ex3_pp3_1c(256) ; + ex3_pp4_0c(255) <= ex3_pp3_1s(255) ; + ex3_pp4_0s(255) <= ex3_pp3_1c(255) ; + ex3_pp4_0c(254) <= tidn ; + ex3_pp4_0s(254) <= ex3_pp3_1s(254) ; + ex3_pp4_0c(253) <= ex3_pp3_1s(253) ; + ex3_pp4_0s(253) <= ex3_pp3_1c(253) ; + ex3_pp4_0c(252) <= tidn ; + csa4_0_252: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0s(252) , + b => ex3_pp3_1c(252) , + c => ex3_pp3_1s(252) , + sum => ex3_pp4_0s(252) , + car => ex3_pp4_0c(251) ); + csa4_0_251: entity work.xuq_alu_mult_csa22 port map( + a => ex3_pp3_1c(251) , + b => ex3_pp3_1s(251) , + sum => ex3_pp4_0s(251) , + car => ex3_pp4_0c(250) ); + csa4_0_250: entity work.xuq_alu_mult_csa22 port map( + a => ex3_pp3_1c(250) , + b => ex3_pp3_1s(250) , + sum => ex3_pp4_0s(250) , + car => ex3_pp4_0c(249) ); + csa4_0_249: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0s(249) , + b => ex3_pp3_1c(249) , + c => ex3_pp3_1s(249) , + sum => ex3_pp4_0s(249) , + car => ex3_pp4_0c(248) ); + csa4_0_248: entity work.xuq_alu_mult_csa22 port map( + a => ex3_pp3_1c(248) , + b => ex3_pp3_1s(248) , + sum => ex3_pp4_0s(248) , + car => ex3_pp4_0c(247) ); + csa4_0_247: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0s(247) , + b => ex3_pp3_1c(247) , + c => ex3_pp3_1s(247) , + sum => ex3_pp4_0s(247) , + car => ex3_pp4_0c(246) ); + csa4_0_246: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0s(246) , + b => ex3_pp3_1c(246) , + c => ex3_pp3_1s(246) , + sum => ex3_pp4_0s(246) , + car => ex3_pp4_0c(245) ); + csa4_0_245: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0s(245) , + b => ex3_pp3_1c(245) , + c => ex3_pp3_1s(245) , + sum => ex3_pp4_0s(245) , + car => ex3_pp4_0c(244) ); + csa4_0_244: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0s(244) , + b => ex3_pp3_1c(244) , + c => ex3_pp3_1s(244) , + sum => ex3_pp4_0s(244) , + car => ex3_pp4_0c(243) ); + csa4_0_243: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0s(243) , + b => ex3_pp3_1c(243) , + c => ex3_pp3_1s(243) , + sum => ex3_pp4_0s(243) , + car => ex3_pp4_0c(242) ); + ex3_pp4_0k(242) <= tidn ; + csa4_0_242: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(242) , + b => ex3_pp3_0s(242) , + c => ex3_pp3_1c(242) , + d => ex3_pp3_1s(242) , + ki => ex3_pp4_0k(242) , + ko => ex3_pp4_0k(241) , + sum => ex3_pp4_0s(242) , + car => ex3_pp4_0c(241) ); + csa4_0_241: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0s(241) , + b => ex3_pp3_1c(241) , + c => ex3_pp3_1s(241) , + d => tidn , + ki => ex3_pp4_0k(241) , + ko => ex3_pp4_0k(240) , + sum => ex3_pp4_0s(241) , + car => ex3_pp4_0c(240) ); + csa4_0_240: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0s(240) , + b => ex3_pp3_1c(240) , + c => ex3_pp3_1s(240) , + d => tidn , + ki => ex3_pp4_0k(240) , + ko => ex3_pp4_0k(239) , + sum => ex3_pp4_0s(240) , + car => ex3_pp4_0c(239) ); + csa4_0_239: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(239) , + b => ex3_pp3_0s(239) , + c => ex3_pp3_1c(239) , + d => ex3_pp3_1s(239) , + ki => ex3_pp4_0k(239) , + ko => ex3_pp4_0k(238) , + sum => ex3_pp4_0s(239) , + car => ex3_pp4_0c(238) ); + csa4_0_238: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(238) , + b => ex3_pp3_0s(238) , + c => ex3_pp3_1c(238) , + d => ex3_pp3_1s(238) , + ki => ex3_pp4_0k(238) , + ko => ex3_pp4_0k(237) , + sum => ex3_pp4_0s(238) , + car => ex3_pp4_0c(237) ); + csa4_0_237: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(237) , + b => ex3_pp3_0s(237) , + c => ex3_pp3_1c(237) , + d => ex3_pp3_1s(237) , + ki => ex3_pp4_0k(237) , + ko => ex3_pp4_0k(236) , + sum => ex3_pp4_0s(237) , + car => ex3_pp4_0c(236) ); + csa4_0_236: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(236) , + b => ex3_pp3_0s(236) , + c => ex3_pp3_1c(236) , + d => ex3_pp3_1s(236) , + ki => ex3_pp4_0k(236) , + ko => ex3_pp4_0k(235) , + sum => ex3_pp4_0s(236) , + car => ex3_pp4_0c(235) ); + csa4_0_235: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(235) , + b => ex3_pp3_0s(235) , + c => ex3_pp3_1c(235) , + d => ex3_pp3_1s(235) , + ki => ex3_pp4_0k(235) , + ko => ex3_pp4_0k(234) , + sum => ex3_pp4_0s(235) , + car => ex3_pp4_0c(234) ); + csa4_0_234: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(234) , + b => ex3_pp3_0s(234) , + c => ex3_pp3_1c(234) , + d => ex3_pp3_1s(234) , + ki => ex3_pp4_0k(234) , + ko => ex3_pp4_0k(233) , + sum => ex3_pp4_0s(234) , + car => ex3_pp4_0c(233) ); + csa4_0_233: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(233) , + b => ex3_pp3_0s(233) , + c => ex3_pp3_1c(233) , + d => ex3_pp3_1s(233) , + ki => ex3_pp4_0k(233) , + ko => ex3_pp4_0k(232) , + sum => ex3_pp4_0s(233) , + car => ex3_pp4_0c(232) ); + csa4_0_232: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(232) , + b => ex3_pp3_0s(232) , + c => ex3_pp3_1c(232) , + d => ex3_pp3_1s(232) , + ki => ex3_pp4_0k(232) , + ko => ex3_pp4_0k(231) , + sum => ex3_pp4_0s(232) , + car => ex3_pp4_0c(231) ); + csa4_0_231: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(231) , + b => ex3_pp3_0s(231) , + c => ex3_pp3_1c(231) , + d => ex3_pp3_1s(231) , + ki => ex3_pp4_0k(231) , + ko => ex3_pp4_0k(230) , + sum => ex3_pp4_0s(231) , + car => ex3_pp4_0c(230) ); + csa4_0_230: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(230) , + b => ex3_pp3_0s(230) , + c => ex3_pp3_1c(230) , + d => ex3_pp3_1s(230) , + ki => ex3_pp4_0k(230) , + ko => ex3_pp4_0k(229) , + sum => ex3_pp4_0s(230) , + car => ex3_pp4_0c(229) ); + csa4_0_229: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(229) , + b => ex3_pp3_0s(229) , + c => ex3_pp3_1c(229) , + d => ex3_pp3_1s(229) , + ki => ex3_pp4_0k(229) , + ko => ex3_pp4_0k(228) , + sum => ex3_pp4_0s(229) , + car => ex3_pp4_0c(228) ); + csa4_0_228: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(228) , + b => ex3_pp3_0s(228) , + c => ex3_pp3_1c(228) , + d => ex3_pp3_1s(228) , + ki => ex3_pp4_0k(228) , + ko => ex3_pp4_0k(227) , + sum => ex3_pp4_0s(228) , + car => ex3_pp4_0c(227) ); + csa4_0_227: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(227) , + b => ex3_pp3_0s(227) , + c => ex3_pp3_1c(227) , + d => ex3_pp3_1s(227) , + ki => ex3_pp4_0k(227) , + ko => ex3_pp4_0k(226) , + sum => ex3_pp4_0s(227) , + car => ex3_pp4_0c(226) ); + csa4_0_226: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(226) , + b => ex3_pp3_0s(226) , + c => ex3_pp3_1c(226) , + d => ex3_pp3_1s(226) , + ki => ex3_pp4_0k(226) , + ko => ex3_pp4_0k(225) , + sum => ex3_pp4_0s(226) , + car => ex3_pp4_0c(225) ); + csa4_0_225: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(225) , + b => ex3_pp3_0s(225) , + c => ex3_pp3_1c(225) , + d => ex3_pp3_1s(225) , + ki => ex3_pp4_0k(225) , + ko => ex3_pp4_0k(224) , + sum => ex3_pp4_0s(225) , + car => ex3_pp4_0c(224) ); + csa4_0_224: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(224) , + b => ex3_pp3_0s(224) , + c => ex3_pp3_1c(224) , + d => ex3_pp3_1s(224) , + ki => ex3_pp4_0k(224) , + ko => ex3_pp4_0k(223) , + sum => ex3_pp4_0s(224) , + car => ex3_pp4_0c(223) ); + csa4_0_223: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(223) , + b => ex3_pp3_0s(223) , + c => ex3_pp3_1c(223) , + d => ex3_pp3_1s(223) , + ki => ex3_pp4_0k(223) , + ko => ex3_pp4_0k(222) , + sum => ex3_pp4_0s(223) , + car => ex3_pp4_0c(222) ); + csa4_0_222: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(222) , + b => ex3_pp3_0s(222) , + c => ex3_pp3_1c(222) , + d => ex3_pp3_1s(222) , + ki => ex3_pp4_0k(222) , + ko => ex3_pp4_0k(221) , + sum => ex3_pp4_0s(222) , + car => ex3_pp4_0c(221) ); + csa4_0_221: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(221) , + b => ex3_pp3_0s(221) , + c => ex3_pp3_1c(221) , + d => ex3_pp3_1s(221) , + ki => ex3_pp4_0k(221) , + ko => ex3_pp4_0k(220) , + sum => ex3_pp4_0s(221) , + car => ex3_pp4_0c(220) ); + csa4_0_220: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(220) , + b => ex3_pp3_0s(220) , + c => ex3_pp3_1c(220) , + d => ex3_pp3_1s(220) , + ki => ex3_pp4_0k(220) , + ko => ex3_pp4_0k(219) , + sum => ex3_pp4_0s(220) , + car => ex3_pp4_0c(219) ); + csa4_0_219: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(219) , + b => ex3_pp3_0s(219) , + c => ex3_pp3_1c(219) , + d => ex3_pp3_1s(219) , + ki => ex3_pp4_0k(219) , + ko => ex3_pp4_0k(218) , + sum => ex3_pp4_0s(219) , + car => ex3_pp4_0c(218) ); + csa4_0_218: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(218) , + b => ex3_pp3_0s(218) , + c => ex3_pp3_1s(218) , + d => tidn , + ki => ex3_pp4_0k(218) , + ko => ex3_pp4_0k(217) , + sum => ex3_pp4_0s(218) , + car => ex3_pp4_0c(217) ); + csa4_0_217: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(217) , + b => ex3_pp3_0s(217) , + c => ex3_pp3_1s(217) , + d => tidn , + ki => ex3_pp4_0k(217) , + ko => ex3_pp4_0k(216) , + sum => ex3_pp4_0s(217) , + car => ex3_pp4_0c(216) ); + csa4_0_216: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(216) , + b => ex3_pp3_0s(216) , + c => ex3_pp3_1s(216) , + d => tidn , + ki => ex3_pp4_0k(216) , + ko => ex3_pp4_0k(215) , + sum => ex3_pp4_0s(216) , + car => ex3_pp4_0c(215) ); + csa4_0_215: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(215) , + b => ex3_pp3_0s(215) , + c => ex3_pp3_1s(215) , + d => tidn , + ki => ex3_pp4_0k(215) , + ko => ex3_pp4_0k(214) , + sum => ex3_pp4_0s(215) , + car => ex3_pp4_0c(214) ); + csa4_0_214: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(214) , + b => ex3_pp3_0s(214) , + c => ex3_pp3_1s(214) , + d => tidn , + ki => ex3_pp4_0k(214) , + ko => ex3_pp4_0k(213) , + sum => ex3_pp4_0s(214) , + car => ex3_pp4_0c(213) ); + csa4_0_213: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(213) , + b => ex3_pp3_0s(213) , + c => ex3_pp3_1s(213) , + d => tidn , + ki => ex3_pp4_0k(213) , + ko => ex3_pp4_0k(212) , + sum => ex3_pp4_0s(213) , + car => ex3_pp4_0c(212) ); + csa4_0_212: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(212) , + b => ex3_pp3_0s(212) , + c => ex3_pp3_1s(212) , + d => tidn , + ki => ex3_pp4_0k(212) , + ko => ex3_pp4_0k(211) , + sum => ex3_pp4_0s(212) , + car => ex3_pp4_0c(211) ); + csa4_0_211: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(211) , + b => ex3_pp3_0s(211) , + c => ex3_pp3_1s(211) , + d => tidn , + ki => ex3_pp4_0k(211) , + ko => ex3_pp4_0k(210) , + sum => ex3_pp4_0s(211) , + car => ex3_pp4_0c(210) ); + csa4_0_210: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(210) , + b => ex3_pp3_0s(210) , + c => ex3_pp3_1s(210) , + d => tidn , + ki => ex3_pp4_0k(210) , + ko => ex3_pp4_0k(209) , + sum => ex3_pp4_0s(210) , + car => ex3_pp4_0c(209) ); + csa4_0_209: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(209) , + b => ex3_pp3_0s(209) , + c => ex3_pp3_1s(209) , + d => tidn , + ki => ex3_pp4_0k(209) , + ko => ex3_pp4_0k(208) , + sum => ex3_pp4_0s(209) , + car => ex3_pp4_0c(208) ); + csa4_0_208: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(208) , + b => ex3_pp3_0s(208) , + c => ex3_pp3_1s(208) , + d => tidn , + ki => ex3_pp4_0k(208) , + ko => ex3_pp4_0k(207) , + sum => ex3_pp4_0s(208) , + car => ex3_pp4_0c(207) ); + csa4_0_207: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(207) , + b => ex3_pp3_0s(207) , + c => ex3_pp4_0k(207) , + sum => ex3_pp4_0s(207) , + car => ex3_pp4_0c(206) ); + csa4_0_206: entity work.xuq_alu_mult_csa22 port map( + a => ex3_pp3_0c(206) , + b => ex3_pp3_0s(206) , + sum => ex3_pp4_0s(206) , + car => ex3_pp4_0c(205) ); + csa4_0_205: entity work.xuq_alu_mult_csa22 port map( + a => ex3_pp3_0c(205) , + b => ex3_pp3_0s(205) , + sum => ex3_pp4_0s(205) , + car => ex3_pp4_0c(204) ); + csa4_0_204: entity work.xuq_alu_mult_csa22 port map( + a => ex3_pp3_0c(204) , + b => ex3_pp3_0s(204) , + sum => ex3_pp4_0s(204) , + car => ex3_pp4_0c(203) ); + csa4_0_203: entity work.xuq_alu_mult_csa22 port map( + a => ex3_pp3_0c(203) , + b => ex3_pp3_0s(203) , + sum => ex3_pp4_0s(203) , + car => ex3_pp4_0c(202) ); + csa4_0_202: entity work.xuq_alu_mult_csa22 port map( + a => ex3_pp3_0c(202) , + b => ex3_pp3_0s(202) , + sum => ex3_pp4_0s(202) , + car => ex3_pp4_0c(201) ); + csa4_0_201: entity work.xuq_alu_mult_csa22 port map( + a => ex3_pp3_0c(201) , + b => ex3_pp3_0s(201) , + sum => ex3_pp4_0s(201) , + car => ex3_pp4_0c(200) ); + csa4_0_200: entity work.xuq_alu_mult_csa22 port map( + a => ex3_pp3_0c(200) , + b => ex3_pp3_0s(200) , + sum => ex3_pp4_0s(200) , + car => ex3_pp4_0c(199) ); + csa4_0_199: entity work.xuq_alu_mult_csa22 port map( + a => ex3_pp3_0c(199) , + b => ex3_pp3_0s(199) , + sum => ex3_pp4_0s(199) , + car => ex3_pp4_0c(198) ); + csa4_0_198: entity work.xuq_alu_mult_csa22 port map( + a => ex3_pp3_0c(198) , + b => ex3_pp3_0s(198) , + sum => ex3_pp4_0s(198) , + car => ex3_pp4_0c(197) ); + ex3_pp4_0s(197) <= ex3_pp3_0c(197) ; + + + + + + + + + + csa5_0_264: entity work.xuq_alu_mult_csa22 port map( + a => ex3_pp4_0s(264) , + b => ex3_recycle_s(264) , + sum => ex3_pp5_0s(264) , + car => ex3_pp5_0c(263) ); + csa5_0_263: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0s(263) , + b => ex3_recycle_c(263) , + c => ex3_recycle_s(263) , + sum => ex3_pp5_0s(263) , + car => ex3_pp5_0c(262) ); + ex3_pp5_0k(262) <= tidn ; + csa5_0_262: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(262) , + b => ex3_pp4_0s(262) , + c => ex3_recycle_c(262) , + d => ex3_recycle_s(262) , + ki => ex3_pp5_0k(262) , + ko => ex3_pp5_0k(261) , + sum => ex3_pp5_0s(262) , + car => ex3_pp5_0c(261) ); + csa5_0_261: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(261) , + b => ex3_pp4_0s(261) , + c => ex3_recycle_c(261) , + d => ex3_recycle_s(261) , + ki => ex3_pp5_0k(261) , + ko => ex3_pp5_0k(260) , + sum => ex3_pp5_0s(261) , + car => ex3_pp5_0c(260) ); + csa5_0_260: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0s(260) , + b => ex3_recycle_c(260) , + c => ex3_recycle_s(260) , + d => tidn , + ki => ex3_pp5_0k(260) , + ko => ex3_pp5_0k(259) , + sum => ex3_pp5_0s(260) , + car => ex3_pp5_0c(259) ); + csa5_0_259: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(259) , + b => ex3_pp4_0s(259) , + c => ex3_recycle_c(259) , + d => ex3_recycle_s(259) , + ki => ex3_pp5_0k(259) , + ko => ex3_pp5_0k(258) , + sum => ex3_pp5_0s(259) , + car => ex3_pp5_0c(258) ); + csa5_0_258: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(258) , + b => ex3_pp4_0s(258) , + c => ex3_recycle_c(258) , + d => ex3_recycle_s(258) , + ki => ex3_pp5_0k(258) , + ko => ex3_pp5_0k(257) , + sum => ex3_pp5_0s(258) , + car => ex3_pp5_0c(257) ); + csa5_0_257: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(257) , + b => ex3_pp4_0s(257) , + c => ex3_recycle_c(257) , + d => ex3_recycle_s(257) , + ki => ex3_pp5_0k(257) , + ko => ex3_pp5_0k(256) , + sum => ex3_pp5_0s(257) , + car => ex3_pp5_0c(256) ); + csa5_0_256: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(256) , + b => ex3_pp4_0s(256) , + c => ex3_recycle_c(256) , + d => ex3_recycle_s(256) , + ki => ex3_pp5_0k(256) , + ko => ex3_pp5_0k(255) , + sum => ex3_pp5_0s(256) , + car => ex3_pp5_0c(255) ); + csa5_0_255: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(255) , + b => ex3_pp4_0s(255) , + c => ex3_recycle_c(255) , + d => ex3_recycle_s(255) , + ki => ex3_pp5_0k(255) , + ko => ex3_pp5_0k(254) , + sum => ex3_pp5_0s(255) , + car => ex3_pp5_0c(254) ); + csa5_0_254: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0s(254) , + b => ex3_recycle_c(254) , + c => ex3_recycle_s(254) , + d => tidn , + ki => ex3_pp5_0k(254) , + ko => ex3_pp5_0k(253) , + sum => ex3_pp5_0s(254) , + car => ex3_pp5_0c(253) ); + csa5_0_253: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(253) , + b => ex3_pp4_0s(253) , + c => ex3_recycle_c(253) , + d => ex3_recycle_s(253) , + ki => ex3_pp5_0k(253) , + ko => ex3_pp5_0k(252) , + sum => ex3_pp5_0s(253) , + car => ex3_pp5_0c(252) ); + csa5_0_252: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0s(252) , + b => ex3_recycle_c(252) , + c => ex3_recycle_s(252) , + d => tidn , + ki => ex3_pp5_0k(252) , + ko => ex3_pp5_0k(251) , + sum => ex3_pp5_0s(252) , + car => ex3_pp5_0c(251) ); + csa5_0_251: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(251) , + b => ex3_pp4_0s(251) , + c => ex3_recycle_c(251) , + d => ex3_recycle_s(251) , + ki => ex3_pp5_0k(251) , + ko => ex3_pp5_0k(250) , + sum => ex3_pp5_0s(251) , + car => ex3_pp5_0c(250) ); + csa5_0_250: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(250) , + b => ex3_pp4_0s(250) , + c => ex3_recycle_c(250) , + d => ex3_recycle_s(250) , + ki => ex3_pp5_0k(250) , + ko => ex3_pp5_0k(249) , + sum => ex3_pp5_0s(250) , + car => ex3_pp5_0c(249) ); + csa5_0_249: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(249) , + b => ex3_pp4_0s(249) , + c => ex3_recycle_c(249) , + d => ex3_recycle_s(249) , + ki => ex3_pp5_0k(249) , + ko => ex3_pp5_0k(248) , + sum => ex3_pp5_0s(249) , + car => ex3_pp5_0c(248) ); + csa5_0_248: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(248) , + b => ex3_pp4_0s(248) , + c => ex3_recycle_c(248) , + d => ex3_recycle_s(248) , + ki => ex3_pp5_0k(248) , + ko => ex3_pp5_0k(247) , + sum => ex3_pp5_0s(248) , + car => ex3_pp5_0c(247) ); + csa5_0_247: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(247) , + b => ex3_pp4_0s(247) , + c => ex3_recycle_c(247) , + d => ex3_recycle_s(247) , + ki => ex3_pp5_0k(247) , + ko => ex3_pp5_0k(246) , + sum => ex3_pp5_0s(247) , + car => ex3_pp5_0c(246) ); + csa5_0_246: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(246) , + b => ex3_pp4_0s(246) , + c => ex3_recycle_c(246) , + d => ex3_recycle_s(246) , + ki => ex3_pp5_0k(246) , + ko => ex3_pp5_0k(245) , + sum => ex3_pp5_0s(246) , + car => ex3_pp5_0c(245) ); + csa5_0_245: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(245) , + b => ex3_pp4_0s(245) , + c => ex3_recycle_c(245) , + d => ex3_recycle_s(245) , + ki => ex3_pp5_0k(245) , + ko => ex3_pp5_0k(244) , + sum => ex3_pp5_0s(245) , + car => ex3_pp5_0c(244) ); + csa5_0_244: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(244) , + b => ex3_pp4_0s(244) , + c => ex3_recycle_c(244) , + d => ex3_recycle_s(244) , + ki => ex3_pp5_0k(244) , + ko => ex3_pp5_0k(243) , + sum => ex3_pp5_0s(244) , + car => ex3_pp5_0c(243) ); + csa5_0_243: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(243) , + b => ex3_pp4_0s(243) , + c => ex3_recycle_c(243) , + d => ex3_recycle_s(243) , + ki => ex3_pp5_0k(243) , + ko => ex3_pp5_0k(242) , + sum => ex3_pp5_0s(243) , + car => ex3_pp5_0c(242) ); + csa5_0_242: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(242) , + b => ex3_pp4_0s(242) , + c => ex3_recycle_c(242) , + d => ex3_recycle_s(242) , + ki => ex3_pp5_0k(242) , + ko => ex3_pp5_0k(241) , + sum => ex3_pp5_0s(242) , + car => ex3_pp5_0c(241) ); + csa5_0_241: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(241) , + b => ex3_pp4_0s(241) , + c => ex3_recycle_c(241) , + d => ex3_recycle_s(241) , + ki => ex3_pp5_0k(241) , + ko => ex3_pp5_0k(240) , + sum => ex3_pp5_0s(241) , + car => ex3_pp5_0c(240) ); + csa5_0_240: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(240) , + b => ex3_pp4_0s(240) , + c => ex3_recycle_c(240) , + d => ex3_recycle_s(240) , + ki => ex3_pp5_0k(240) , + ko => ex3_pp5_0k(239) , + sum => ex3_pp5_0s(240) , + car => ex3_pp5_0c(239) ); + csa5_0_239: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(239) , + b => ex3_pp4_0s(239) , + c => ex3_recycle_c(239) , + d => ex3_recycle_s(239) , + ki => ex3_pp5_0k(239) , + ko => ex3_pp5_0k(238) , + sum => ex3_pp5_0s(239) , + car => ex3_pp5_0c(238) ); + csa5_0_238: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(238) , + b => ex3_pp4_0s(238) , + c => ex3_recycle_c(238) , + d => ex3_recycle_s(238) , + ki => ex3_pp5_0k(238) , + ko => ex3_pp5_0k(237) , + sum => ex3_pp5_0s(238) , + car => ex3_pp5_0c(237) ); + csa5_0_237: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(237) , + b => ex3_pp4_0s(237) , + c => ex3_recycle_c(237) , + d => ex3_recycle_s(237) , + ki => ex3_pp5_0k(237) , + ko => ex3_pp5_0k(236) , + sum => ex3_pp5_0s(237) , + car => ex3_pp5_0c(236) ); + csa5_0_236: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(236) , + b => ex3_pp4_0s(236) , + c => ex3_recycle_c(236) , + d => ex3_recycle_s(236) , + ki => ex3_pp5_0k(236) , + ko => ex3_pp5_0k(235) , + sum => ex3_pp5_0s(236) , + car => ex3_pp5_0c(235) ); + csa5_0_235: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(235) , + b => ex3_pp4_0s(235) , + c => ex3_recycle_c(235) , + d => ex3_recycle_s(235) , + ki => ex3_pp5_0k(235) , + ko => ex3_pp5_0k(234) , + sum => ex3_pp5_0s(235) , + car => ex3_pp5_0c(234) ); + csa5_0_234: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(234) , + b => ex3_pp4_0s(234) , + c => ex3_recycle_c(234) , + d => ex3_recycle_s(234) , + ki => ex3_pp5_0k(234) , + ko => ex3_pp5_0k(233) , + sum => ex3_pp5_0s(234) , + car => ex3_pp5_0c(233) ); + csa5_0_233: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(233) , + b => ex3_pp4_0s(233) , + c => ex3_recycle_c(233) , + d => ex3_recycle_s(233) , + ki => ex3_pp5_0k(233) , + ko => ex3_pp5_0k(232) , + sum => ex3_pp5_0s(233) , + car => ex3_pp5_0c(232) ); + csa5_0_232: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(232) , + b => ex3_pp4_0s(232) , + c => ex3_recycle_c(232) , + d => ex3_recycle_s(232) , + ki => ex3_pp5_0k(232) , + ko => ex3_pp5_0k(231) , + sum => ex3_pp5_0s(232) , + car => ex3_pp5_0c(231) ); + csa5_0_231: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(231) , + b => ex3_pp4_0s(231) , + c => ex3_recycle_c(231) , + d => ex3_recycle_s(231) , + ki => ex3_pp5_0k(231) , + ko => ex3_pp5_0k(230) , + sum => ex3_pp5_0s(231) , + car => ex3_pp5_0c(230) ); + csa5_0_230: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(230) , + b => ex3_pp4_0s(230) , + c => ex3_recycle_c(230) , + d => ex3_recycle_s(230) , + ki => ex3_pp5_0k(230) , + ko => ex3_pp5_0k(229) , + sum => ex3_pp5_0s(230) , + car => ex3_pp5_0c(229) ); + csa5_0_229: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(229) , + b => ex3_pp4_0s(229) , + c => ex3_recycle_c(229) , + d => ex3_recycle_s(229) , + ki => ex3_pp5_0k(229) , + ko => ex3_pp5_0k(228) , + sum => ex3_pp5_0s(229) , + car => ex3_pp5_0c(228) ); + csa5_0_228: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(228) , + b => ex3_pp4_0s(228) , + c => ex3_recycle_c(228) , + d => ex3_recycle_s(228) , + ki => ex3_pp5_0k(228) , + ko => ex3_pp5_0k(227) , + sum => ex3_pp5_0s(228) , + car => ex3_pp5_0c(227) ); + csa5_0_227: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(227) , + b => ex3_pp4_0s(227) , + c => ex3_recycle_c(227) , + d => ex3_recycle_s(227) , + ki => ex3_pp5_0k(227) , + ko => ex3_pp5_0k(226) , + sum => ex3_pp5_0s(227) , + car => ex3_pp5_0c(226) ); + csa5_0_226: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(226) , + b => ex3_pp4_0s(226) , + c => ex3_recycle_c(226) , + d => ex3_recycle_s(226) , + ki => ex3_pp5_0k(226) , + ko => ex3_pp5_0k(225) , + sum => ex3_pp5_0s(226) , + car => ex3_pp5_0c(225) ); + csa5_0_225: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(225) , + b => ex3_pp4_0s(225) , + c => ex3_recycle_c(225) , + d => ex3_recycle_s(225) , + ki => ex3_pp5_0k(225) , + ko => ex3_pp5_0k(224) , + sum => ex3_pp5_0s(225) , + car => ex3_pp5_0c(224) ); + csa5_0_224: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(224) , + b => ex3_pp4_0s(224) , + c => ex3_recycle_c(224) , + d => ex3_recycle_s(224) , + ki => ex3_pp5_0k(224) , + ko => ex3_pp5_0k(223) , + sum => ex3_pp5_0s(224) , + car => ex3_pp5_0c(223) ); + csa5_0_223: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(223) , + b => ex3_pp4_0s(223) , + c => ex3_recycle_c(223) , + d => ex3_recycle_s(223) , + ki => ex3_pp5_0k(223) , + ko => ex3_pp5_0k(222) , + sum => ex3_pp5_0s(223) , + car => ex3_pp5_0c(222) ); + csa5_0_222: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(222) , + b => ex3_pp4_0s(222) , + c => ex3_recycle_c(222) , + d => ex3_recycle_s(222) , + ki => ex3_pp5_0k(222) , + ko => ex3_pp5_0k(221) , + sum => ex3_pp5_0s(222) , + car => ex3_pp5_0c(221) ); + csa5_0_221: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(221) , + b => ex3_pp4_0s(221) , + c => ex3_recycle_c(221) , + d => ex3_recycle_s(221) , + ki => ex3_pp5_0k(221) , + ko => ex3_pp5_0k(220) , + sum => ex3_pp5_0s(221) , + car => ex3_pp5_0c(220) ); + csa5_0_220: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(220) , + b => ex3_pp4_0s(220) , + c => ex3_recycle_c(220) , + d => ex3_recycle_s(220) , + ki => ex3_pp5_0k(220) , + ko => ex3_pp5_0k(219) , + sum => ex3_pp5_0s(220) , + car => ex3_pp5_0c(219) ); + csa5_0_219: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(219) , + b => ex3_pp4_0s(219) , + c => ex3_recycle_c(219) , + d => ex3_recycle_s(219) , + ki => ex3_pp5_0k(219) , + ko => ex3_pp5_0k(218) , + sum => ex3_pp5_0s(219) , + car => ex3_pp5_0c(218) ); + csa5_0_218: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(218) , + b => ex3_pp4_0s(218) , + c => ex3_recycle_c(218) , + d => ex3_recycle_s(218) , + ki => ex3_pp5_0k(218) , + ko => ex3_pp5_0k(217) , + sum => ex3_pp5_0s(218) , + car => ex3_pp5_0c(217) ); + csa5_0_217: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(217) , + b => ex3_pp4_0s(217) , + c => ex3_recycle_c(217) , + d => ex3_recycle_s(217) , + ki => ex3_pp5_0k(217) , + ko => ex3_pp5_0k(216) , + sum => ex3_pp5_0s(217) , + car => ex3_pp5_0c(216) ); + csa5_0_216: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(216) , + b => ex3_pp4_0s(216) , + c => ex3_recycle_c(216) , + d => ex3_recycle_s(216) , + ki => ex3_pp5_0k(216) , + ko => ex3_pp5_0k(215) , + sum => ex3_pp5_0s(216) , + car => ex3_pp5_0c(215) ); + csa5_0_215: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(215) , + b => ex3_pp4_0s(215) , + c => ex3_recycle_c(215) , + d => ex3_recycle_s(215) , + ki => ex3_pp5_0k(215) , + ko => ex3_pp5_0k(214) , + sum => ex3_pp5_0s(215) , + car => ex3_pp5_0c(214) ); + csa5_0_214: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(214) , + b => ex3_pp4_0s(214) , + c => ex3_recycle_c(214) , + d => ex3_recycle_s(214) , + ki => ex3_pp5_0k(214) , + ko => ex3_pp5_0k(213) , + sum => ex3_pp5_0s(214) , + car => ex3_pp5_0c(213) ); + csa5_0_213: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(213) , + b => ex3_pp4_0s(213) , + c => ex3_recycle_c(213) , + d => ex3_recycle_s(213) , + ki => ex3_pp5_0k(213) , + ko => ex3_pp5_0k(212) , + sum => ex3_pp5_0s(213) , + car => ex3_pp5_0c(212) ); + csa5_0_212: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(212) , + b => ex3_pp4_0s(212) , + c => ex3_recycle_c(212) , + d => ex3_recycle_s(212) , + ki => ex3_pp5_0k(212) , + ko => ex3_pp5_0k(211) , + sum => ex3_pp5_0s(212) , + car => ex3_pp5_0c(211) ); + csa5_0_211: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(211) , + b => ex3_pp4_0s(211) , + c => ex3_recycle_c(211) , + d => ex3_recycle_s(211) , + ki => ex3_pp5_0k(211) , + ko => ex3_pp5_0k(210) , + sum => ex3_pp5_0s(211) , + car => ex3_pp5_0c(210) ); + csa5_0_210: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(210) , + b => ex3_pp4_0s(210) , + c => ex3_recycle_c(210) , + d => ex3_recycle_s(210) , + ki => ex3_pp5_0k(210) , + ko => ex3_pp5_0k(209) , + sum => ex3_pp5_0s(210) , + car => ex3_pp5_0c(209) ); + csa5_0_209: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(209) , + b => ex3_pp4_0s(209) , + c => ex3_recycle_c(209) , + d => ex3_recycle_s(209) , + ki => ex3_pp5_0k(209) , + ko => ex3_pp5_0k(208) , + sum => ex3_pp5_0s(209) , + car => ex3_pp5_0c(208) ); + csa5_0_208: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(208) , + b => ex3_pp4_0s(208) , + c => ex3_recycle_c(208) , + d => ex3_recycle_s(208) , + ki => ex3_pp5_0k(208) , + ko => ex3_pp5_0k(207) , + sum => ex3_pp5_0s(208) , + car => ex3_pp5_0c(207) ); + csa5_0_207: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(207) , + b => ex3_pp4_0s(207) , + c => ex3_recycle_c(207) , + d => ex3_recycle_s(207) , + ki => ex3_pp5_0k(207) , + ko => ex3_pp5_0k(206) , + sum => ex3_pp5_0s(207) , + car => ex3_pp5_0c(206) ); + csa5_0_206: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(206) , + b => ex3_pp4_0s(206) , + c => ex3_recycle_c(206) , + d => ex3_recycle_s(206) , + ki => ex3_pp5_0k(206) , + ko => ex3_pp5_0k(205) , + sum => ex3_pp5_0s(206) , + car => ex3_pp5_0c(205) ); + csa5_0_205: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(205) , + b => ex3_pp4_0s(205) , + c => ex3_recycle_c(205) , + d => ex3_recycle_s(205) , + ki => ex3_pp5_0k(205) , + ko => ex3_pp5_0k(204) , + sum => ex3_pp5_0s(205) , + car => ex3_pp5_0c(204) ); + csa5_0_204: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(204) , + b => ex3_pp4_0s(204) , + c => ex3_recycle_c(204) , + d => ex3_recycle_s(204) , + ki => ex3_pp5_0k(204) , + ko => ex3_pp5_0k(203) , + sum => ex3_pp5_0s(204) , + car => ex3_pp5_0c(203) ); + csa5_0_203: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(203) , + b => ex3_pp4_0s(203) , + c => ex3_recycle_c(203) , + d => ex3_recycle_s(203) , + ki => ex3_pp5_0k(203) , + ko => ex3_pp5_0k(202) , + sum => ex3_pp5_0s(203) , + car => ex3_pp5_0c(202) ); + csa5_0_202: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(202) , + b => ex3_pp4_0s(202) , + c => ex3_recycle_c(202) , + d => ex3_recycle_s(202) , + ki => ex3_pp5_0k(202) , + ko => ex3_pp5_0k(201) , + sum => ex3_pp5_0s(202) , + car => ex3_pp5_0c(201) ); + csa5_0_201: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(201) , + b => ex3_pp4_0s(201) , + c => ex3_recycle_c(201) , + d => ex3_recycle_s(201) , + ki => ex3_pp5_0k(201) , + ko => ex3_pp5_0k(200) , + sum => ex3_pp5_0s(201) , + car => ex3_pp5_0c(200) ); + csa5_0_200: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(200) , + b => ex3_pp4_0s(200) , + c => ex3_recycle_c(200) , + d => ex3_recycle_s(200) , + ki => ex3_pp5_0k(200) , + ko => ex3_pp5_0k(199) , + sum => ex3_pp5_0s(200) , + car => ex3_pp5_0c(199) ); + csa5_0_199: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(199) , + b => ex3_pp4_0s(199) , + c => ex3_recycle_c(199) , + d => ex3_recycle_s(199) , + ki => ex3_pp5_0k(199) , + ko => ex3_pp5_0k(198) , + sum => ex3_pp5_0s(199) , + car => ex3_pp5_0c(198) ); + csa5_0_198: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(198) , + b => ex3_pp4_0s(198) , + c => ex3_recycle_c(198) , + d => ex3_recycle_s(198) , + ki => ex3_pp5_0k(198) , + ko => ex3_pp5_0k(197) , + sum => ex3_pp5_0s(198) , + car => ex3_pp5_0c(197) ); + csa5_0_197: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(197) , + b => ex3_pp4_0s(197) , + c => ex3_recycle_c(197) , + d => ex3_recycle_s(197) , + ki => ex3_pp5_0k(197) , + ko => ex3_pp5_0k(196) , + sum => ex3_pp5_0s(197) , + car => ex3_pp5_0c(196) ); + csa5_0_196: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_recycle_c(196) , + b => ex3_recycle_s(196) , + c => ex3_pp5_0k(196) , + sum => ex3_pp5_0s(196) , + car => ex3_pp5_0c(195) ); + + + + + ex4_pp5_0s_din(196 to 264) <= ex3_pp5_0s(196 to 264); + ex4_pp5_0c_din(196 to 263) <= ex3_pp5_0c(196 to 263); + + + u_sum_qi: ex4_pp5_0s(196 to 264) <= not ex4_pp5_0s_q_b(196 to 264) ; + u_car_qi: ex4_pp5_0c(196 to 263) <= not ex4_pp5_0c_q_b(196 to 263) ; + + ex4_pp5_0s_out(196 to 264) <= ex4_pp5_0s(196 to 264) ; + ex4_pp5_0c_out(196 to 263) <= ex4_pp5_0c(196 to 263) ; + + + + + ex3_lcb: tri_lcbnd generic map (expand_type => expand_type) port map ( + delay_lclkr => delay_lclkr_dc , + mpw1_b => mpw1_dc_b , + mpw2_b => mpw2_dc_b , + forcee => func_sl_force , + nclk => nclk , + vd => vdd , + gd => gnd , + act => ex2_act , + sg => sg_0 , + thold_b => func_sl_thold_0_b , + d1clk => ex3_d1clk , + d2clk => ex3_d2clk , + lclk => ex3_lclk ); + + ex4_lcb: tri_lcbnd generic map (expand_type => expand_type) port map ( + delay_lclkr => delay_lclkr_dc , + mpw1_b => mpw1_dc_b , + mpw2_b => mpw2_dc_b , + forcee => func_sl_force , + nclk => nclk , + vd => vdd , + gd => gnd , + act => ex3_act , + sg => sg_0 , + thold_b => func_sl_thold_0_b , + d1clk => ex4_d1clk , + d2clk => ex4_d2clk , + lclk => ex4_lclk ); + + + + ex3_pp2_0s_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 45,btr => "NLI0001_X1_A12TH", expand_type => expand_type, needs_sreset => 0, init=>(1 to 45=>'0')) port map ( + VD => vdd , + GD => gnd , + LCLK => ex3_lclk , + D1CLK => ex3_d1clk , + D2CLK => ex3_d2clk , + SCANIN => ex3_pp2_0s_lat_si , + SCANOUT => ex3_pp2_0s_lat_so , + D => ex3_pp2_0s_din(198 to 242) , + QB => ex3_pp2_0s_q_b(198 to 242) ); + ex3_pp2_0c_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 43,btr => "NLI0001_X1_A12TH", expand_type => expand_type, needs_sreset => 0, init=>(1 to 43=>'0') ) port map ( + VD => vdd , + GD => gnd , + LCLK => ex3_lclk , + D1CLK => ex3_d1clk , + D2CLK => ex3_d2clk , + SCANIN => ex3_pp2_0c_lat_si , + SCANOUT => ex3_pp2_0c_lat_so , + D => ex3_pp2_0c_din(198 to 240) , + QB => ex3_pp2_0c_q_b(198 to 240) ); + + ex3_pp2_1s_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 47,btr => "NLI0001_X1_A12TH", expand_type => expand_type, needs_sreset => 0, init=>(1 to 47=>'0') ) port map ( + VD => vdd , + GD => gnd , + LCLK => ex3_lclk , + D1CLK => ex3_d1clk , + D2CLK => ex3_d2clk , + SCANIN => ex3_pp2_1s_lat_si , + SCANOUT => ex3_pp2_1s_lat_so , + D => ex3_pp2_1s_din(208 to 254) , + QB => ex3_pp2_1s_q_b(208 to 254) ); + + ex3_pp2_1c_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 45,btr => "NLI0001_X1_A12TH", expand_type => expand_type, needs_sreset => 0, init=>(1 to 45=>'0') ) port map ( + VD => vdd , + GD => gnd , + LCLK => ex3_lclk , + D1CLK => ex3_d1clk , + D2CLK => ex3_d2clk , + SCANIN => ex3_pp2_1c_lat_si , + SCANOUT => ex3_pp2_1c_lat_so , + D => ex3_pp2_1c_din(208 to 252) , + QB => ex3_pp2_1c_q_b(208 to 252) ); + + ex3_pp2_2s_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 45,btr => "NLI0001_X1_A12TH", expand_type => expand_type, needs_sreset => 0, init=>(1 to 45=>'0') ) port map ( + VD => vdd , + GD => gnd , + LCLK => ex3_lclk , + D1CLK => ex3_d1clk , + D2CLK => ex3_d2clk , + SCANIN => ex3_pp2_2s_lat_si , + SCANOUT => ex3_pp2_2s_lat_so , + D => ex3_pp2_2s_din(220 to 264) , + QB => ex3_pp2_2s_q_b(220 to 264) ); + + ex3_pp2_2c_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 44,btr => "NLI0001_X1_A12TH", expand_type => expand_type, needs_sreset => 0, init=>(1 to 44=>'0') ) port map ( + VD => vdd , + GD => gnd , + LCLK => ex3_lclk , + D1CLK => ex3_d1clk , + D2CLK => ex3_d2clk , + SCANIN => ex3_pp2_2c_lat_si , + SCANOUT => ex3_pp2_2c_lat_so , + D => ex3_pp2_2c_din(220 to 263) , + QB => ex3_pp2_2c_q_b(220 to 263) ); + + + ex4_pp5_0s_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 69,btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0, init=>(1 to 69=>'0') ) port map ( + VD => vdd , + GD => gnd , + LCLK => ex4_lclk , + D1CLK => ex4_d1clk , + D2CLK => ex4_d2clk , + SCANIN => ex4_pp5_0s_lat_si , + SCANOUT => ex4_pp5_0s_lat_so , + D => ex4_pp5_0s_din(196 to 264) , + QB => ex4_pp5_0s_q_b(196 to 264) ); + + ex4_pp5_0c_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 68,btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0, init=>(1 to 68=>'0') ) port map ( + VD => vdd , + GD => gnd , + LCLK => ex4_lclk , + D1CLK => ex4_d1clk , + D2CLK => ex4_d2clk , + SCANIN => ex4_pp5_0c_lat_si , + SCANOUT => ex4_pp5_0c_lat_so , + D => ex4_pp5_0c_din(196 to 263) , + QB => ex4_pp5_0c_q_b(196 to 263) ); + + + + + + + ex3_pp2_0s_lat_si(198 to 242) <= scan_in & ex3_pp2_0s_lat_so(198 to 241) ; + ex3_pp2_0c_lat_si(198 to 240) <= ex3_pp2_0c_lat_so(199 to 240) & ex3_pp2_0s_lat_so(242); + ex3_pp2_1s_lat_si(208 to 254) <= ex3_pp2_0c_lat_so(198) & ex3_pp2_1s_lat_so(208 to 253); + ex3_pp2_1c_lat_si(208 to 252) <= ex3_pp2_1c_lat_so(209 to 252) & ex3_pp2_1s_lat_so(254); + ex3_pp2_2s_lat_si(220 to 264) <= ex3_pp2_1c_lat_so(208) & ex3_pp2_2s_lat_so(220 to 263); + ex3_pp2_2c_lat_si(220 to 263) <= ex3_pp2_2c_lat_so(221 to 263) & ex3_pp2_2s_lat_so(264); + + ex4_pp5_0s_lat_si(196 to 264) <= ex3_pp2_2c_lat_so(220) & ex4_pp5_0s_lat_so(196 to 263); + ex4_pp5_0c_lat_si(196 to 263) <= ex4_pp5_0c_lat_so(197 to 263) & ex4_pp5_0s_lat_so(264); + + scan_out <= ex4_pp5_0c_lat_so(196) ; + + + mark_unused(ex2_pp1_1s(241)); + mark_unused(ex2_pp1_1c(238)); + mark_unused(ex2_pp1_1c(239)); + mark_unused(ex2_pp1_2s(247)); + mark_unused(ex2_pp1_2c(244)); + mark_unused(ex2_pp1_2c(245)); + mark_unused(ex2_pp1_3s(253)); + mark_unused(ex2_pp1_3c(250)); + mark_unused(ex2_pp1_3c(251)); + mark_unused(ex2_pp1_4s(259)); + mark_unused(ex2_pp1_4c(256)); + mark_unused(ex2_pp1_4c(257)); + mark_unused(ex2_pp1_5c(262)); + mark_unused(ex2_pp1_5c(263)); + mark_unused(ex3_pp2_0s(241)); + mark_unused(ex3_pp2_0c(236)); + mark_unused(ex3_pp2_0c(238)); + mark_unused(ex3_pp2_0c(239)); + mark_unused(ex3_pp2_1s(253)); + mark_unused(ex3_pp2_1c(248)); + mark_unused(ex3_pp2_1c(250)); + mark_unused(ex3_pp2_1c(251)); + mark_unused(ex3_pp2_2c(260)); + mark_unused(ex3_pp2_2c(262)); + mark_unused(ex3_pp2_1s_x(253)); + mark_unused(ex3_pp2_1c_x(248)); + mark_unused(ex3_pp2_1c_x(250)); + mark_unused(ex3_pp2_1c_x(251)); + mark_unused(ex3_pp2_2c_x(260)); + mark_unused(ex3_pp2_2c_x(262)); + mark_unused(ex3_pp2_1s_x_b(253)); + mark_unused(ex3_pp2_1c_x_b(248)); + mark_unused(ex3_pp2_1c_x_b(250)); + mark_unused(ex3_pp2_1c_x_b(251)); + mark_unused(ex3_pp2_2c_x_b(260)); + mark_unused(ex3_pp2_2c_x_b(262)); + mark_unused(ex3_pp3_0s(248)); + mark_unused(ex3_pp3_0s(250)); + mark_unused(ex3_pp3_0s(251)); + mark_unused(ex3_pp3_0c(240)); + mark_unused(ex3_pp3_0c(241)); + mark_unused(ex3_pp3_1c(254)); + mark_unused(ex3_pp3_1c(260)); + mark_unused(ex3_pp4_0c(252)); + mark_unused(ex3_pp4_0c(254)); + mark_unused(ex3_pp4_0c(260)); + mark_unused(ex2_pp1_0c(232)); + mark_unused(ex2_pp1_0c(233)); + mark_unused(ex2_pp0_00(233)); + mark_unused(ex2_pp0_01(235)); + mark_unused(ex2_pp0_02(237)); + mark_unused(ex2_pp0_03(239)); + mark_unused(ex2_pp0_04(241)); + mark_unused(ex2_pp0_05(243)); + mark_unused(ex2_pp0_06(245)); + mark_unused(ex2_pp0_07(247)); + mark_unused(ex2_pp0_08(249)); + mark_unused(ex2_pp0_09(251)); + mark_unused(ex2_pp0_10(253)); + mark_unused(ex2_pp0_11(255)); + mark_unused(ex2_pp0_12(257)); + mark_unused(ex2_pp0_13(259)); + mark_unused(ex2_pp0_14(261)); + mark_unused(ex2_pp0_15(263)); + mark_unused(ex2_pp1_0s(235)); + mark_unused(ex3_pp5_0c(195)); + mark_unused(version(0 to 7)); + + + +end architecture xuq_alu_mult_core; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_alu_mult_csa22.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_alu_mult_csa22.vhdl new file mode 100644 index 0000000..8fb8ce2 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_alu_mult_csa22.vhdl @@ -0,0 +1,61 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; use ieee.std_logic_1164.all ; +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + +ENTITY xuq_alu_mult_csa22 IS + PORT( + a : IN std_ulogic; + b : IN std_ulogic; + car : OUT std_ulogic; + sum : OUT std_ulogic + ); +END xuq_alu_mult_csa22; + +ARCHITECTURE xuq_alu_mult_csa22 OF xuq_alu_mult_csa22 IS + + signal car_b, sum_b : std_ulogic; + + + +BEGIN + + u_22nandc: car_b <= not( a and b ); + u_22nands: sum_b <= not( car_b and (a or b) ); + u_22invc: car <= not car_b; + u_22invs: sum <= not sum_b ; + +END; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_alu_or3232.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_alu_or3232.vhdl new file mode 100644 index 0000000..9f221c8 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_alu_or3232.vhdl @@ -0,0 +1,141 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +LIBRARY ieee; USE ieee.std_logic_1164.all; + use ieee.numeric_std.all; +LIBRARY ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; +LIBRARY support; + use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity xuq_alu_or3232 is generic(expand_type: integer := 2 ); port ( + + d :in std_ulogic_vector(0 to 63) ; + or_hi_b :out std_ulogic ; + or_lo_b :out std_ulogic +); + +-- synopsys translate_off +-- synopsys translate_on +end xuq_alu_or3232; + +architecture xuq_alu_or3232 of xuq_alu_or3232 is + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal or_lv1_b :std_ulogic_vector(0 to 31) ; + signal or_lv2 :std_ulogic_vector(0 to 15) ; + signal or_lv3_b :std_ulogic_vector(0 to 7) ; + signal or_lv4 :std_ulogic_vector(0 to 3) ; + signal or_lv5_b :std_ulogic_vector(0 to 1) ; + + + + + + + + +begin + + + + u_or_00: or_lv1_b( 0) <= not( d ( 0) or d ( 1) ); + u_or_02: or_lv1_b( 1) <= not( d ( 2) or d ( 3) ); + u_or_04: or_lv1_b( 2) <= not( d ( 4) or d ( 5) ); + u_or_06: or_lv1_b( 3) <= not( d ( 6) or d ( 7) ); + u_or_08: or_lv1_b( 4) <= not( d ( 8) or d ( 9) ); + u_or_10: or_lv1_b( 5) <= not( d (10) or d (11) ); + u_or_12: or_lv1_b( 6) <= not( d (12) or d (13) ); + u_or_14: or_lv1_b( 7) <= not( d (14) or d (15) ); + u_or_16: or_lv1_b( 8) <= not( d (16) or d (17) ); + u_or_18: or_lv1_b( 9) <= not( d (18) or d (19) ); + u_or_20: or_lv1_b(10) <= not( d (20) or d (21) ); + u_or_22: or_lv1_b(11) <= not( d (22) or d (23) ); + u_or_24: or_lv1_b(12) <= not( d (24) or d (25) ); + u_or_26: or_lv1_b(13) <= not( d (26) or d (27) ); + u_or_28: or_lv1_b(14) <= not( d (28) or d (29) ); + u_or_30: or_lv1_b(15) <= not( d (30) or d (31) ); + u_or_32: or_lv1_b(16) <= not( d (32) or d (33) ); + u_or_34: or_lv1_b(17) <= not( d (34) or d (35) ); + u_or_36: or_lv1_b(18) <= not( d (36) or d (37) ); + u_or_38: or_lv1_b(19) <= not( d (38) or d (39) ); + u_or_40: or_lv1_b(20) <= not( d (40) or d (41) ); + u_or_42: or_lv1_b(21) <= not( d (42) or d (43) ); + u_or_44: or_lv1_b(22) <= not( d (44) or d (45) ); + u_or_46: or_lv1_b(23) <= not( d (46) or d (47) ); + u_or_48: or_lv1_b(24) <= not( d (48) or d (49) ); + u_or_50: or_lv1_b(25) <= not( d (50) or d (51) ); + u_or_52: or_lv1_b(26) <= not( d (52) or d (53) ); + u_or_54: or_lv1_b(27) <= not( d (54) or d (55) ); + u_or_56: or_lv1_b(28) <= not( d (56) or d (57) ); + u_or_58: or_lv1_b(29) <= not( d (58) or d (59) ); + u_or_60: or_lv1_b(30) <= not( d (60) or d (61) ); + u_or_62: or_lv1_b(31) <= not( d (62) or d (63) ); + + u_or_01: or_lv2 ( 0) <= not( or_lv1_b( 0) and or_lv1_b( 1) ); + u_or_05: or_lv2 ( 1) <= not( or_lv1_b( 2) and or_lv1_b( 3) ); + u_or_09: or_lv2 ( 2) <= not( or_lv1_b( 4) and or_lv1_b( 5) ); + u_or_13: or_lv2 ( 3) <= not( or_lv1_b( 6) and or_lv1_b( 7) ); + u_or_17: or_lv2 ( 4) <= not( or_lv1_b( 8) and or_lv1_b( 9) ); + u_or_21: or_lv2 ( 5) <= not( or_lv1_b(10) and or_lv1_b(11) ); + u_or_25: or_lv2 ( 6) <= not( or_lv1_b(12) and or_lv1_b(13) ); + u_or_29: or_lv2 ( 7) <= not( or_lv1_b(14) and or_lv1_b(15) ); + u_or_33: or_lv2 ( 8) <= not( or_lv1_b(16) and or_lv1_b(17) ); + u_or_37: or_lv2 ( 9) <= not( or_lv1_b(18) and or_lv1_b(19) ); + u_or_41: or_lv2 (10) <= not( or_lv1_b(20) and or_lv1_b(21) ); + u_or_45: or_lv2 (11) <= not( or_lv1_b(22) and or_lv1_b(23) ); + u_or_49: or_lv2 (12) <= not( or_lv1_b(24) and or_lv1_b(25) ); + u_or_53: or_lv2 (13) <= not( or_lv1_b(26) and or_lv1_b(27) ); + u_or_57: or_lv2 (14) <= not( or_lv1_b(28) and or_lv1_b(29) ); + u_or_61: or_lv2 (15) <= not( or_lv1_b(30) and or_lv1_b(31) ); + + u_or_03: or_lv3_b( 0) <= not( or_lv2 ( 0) or or_lv2 ( 1) ); + u_or_11: or_lv3_b( 1) <= not( or_lv2 ( 2) or or_lv2 ( 3) ); + u_or_19: or_lv3_b( 2) <= not( or_lv2 ( 4) or or_lv2 ( 5) ); + u_or_27: or_lv3_b( 3) <= not( or_lv2 ( 6) or or_lv2 ( 7) ); + u_or_35: or_lv3_b( 4) <= not( or_lv2 ( 8) or or_lv2 ( 9) ); + u_or_43: or_lv3_b( 5) <= not( or_lv2 (10) or or_lv2 (11) ); + u_or_51: or_lv3_b( 6) <= not( or_lv2 (12) or or_lv2 (13) ); + u_or_59: or_lv3_b( 7) <= not( or_lv2 (14) or or_lv2 (15) ); + + u_or_07: or_lv4 ( 0) <= not( or_lv3_b( 0) and or_lv3_b( 1) ); + u_or_23: or_lv4 ( 1) <= not( or_lv3_b( 2) and or_lv3_b( 3) ); + u_or_39: or_lv4 ( 2) <= not( or_lv3_b( 4) and or_lv3_b( 5) ); + u_or_55: or_lv4 ( 3) <= not( or_lv3_b( 6) and or_lv3_b( 7) ); + + u_or_15: or_lv5_b( 0) <= not( or_lv4 ( 0) or or_lv4 ( 1) ); + u_or_47: or_lv5_b( 1) <= not( or_lv4 ( 2) or or_lv4 ( 3) ); + + or_hi_b <= or_lv5_b(0); + or_lo_b <= or_lv5_b(1); + +end architecture xuq_alu_or3232; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_alu_rol64.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_alu_rol64.vhdl new file mode 100644 index 0000000..70aa445 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_alu_rol64.vhdl @@ -0,0 +1,247 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +LIBRARY ieee; USE ieee.std_logic_1164.all; + use ieee.numeric_std.all; +LIBRARY ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; +LIBRARY support; + use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity xuq_alu_rol64 is generic(expand_type: integer := 2 ); port ( + word :in std_ulogic_vector(0 to 1); + right :in std_ulogic_vector(0 to 2); + amt :in std_ulogic_vector(0 to 5); + data_i :in std_ulogic_vector(0 to 63); + res_rot :out std_ulogic_vector(0 to 63) +); + +-- synopsys translate_off +-- synopsys translate_on + +end xuq_alu_rol64; + +architecture xuq_alu_rol64 of xuq_alu_rol64 is + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal right_b :std_ulogic_vector(0 to 2); + signal amt_b :std_ulogic_vector(0 to 5); + signal word_b :std_ulogic_vector(0 to 1); + signal word_bus, word_bus_b :std_ulogic_vector(0 to 31 ); + signal data_i0_adj_b :std_ulogic_vector(0 to 31 ); + signal data_i_adj, data_i1_adj_b :std_ulogic_vector(0 to 63); + + signal rolx16_0, rolx16_1, rolx16_2, rolx16_3 :std_ulogic_vector(0 to 63); + signal rolx04_0, rolx04_1, rolx04_2, rolx04_3 :std_ulogic_vector(0 to 63); + signal rolx01_0, rolx01_1, rolx01_2, rolx01_3, rolx01_4 :std_ulogic_vector(0 to 63); + signal shd16, shd16_0_b, shd16_1_b :std_ulogic_vector(0 to 63) ; + signal shd04, shd04_0_b, shd04_1_b :std_ulogic_vector(0 to 63) ; + signal shd01_0_b, shd01_1_b, shd01_2_b :std_ulogic_vector(0 to 63) ; + signal x16_lft_b, x16_rgt_b, lftx16 :std_ulogic_vector(0 to 3); + signal x04_lft_b, x04_rgt_b, lftx04 :std_ulogic_vector(0 to 3); + signal x01_lft_b, x01_rgt_b :std_ulogic_vector(0 to 3); + signal lftx01 :std_ulogic_vector(0 to 4); + + + signal lftx01_inv, lftx01_buf0, lftx01_buf1 :std_ulogic_vector(0 to 4); + signal lftx04_inv, lftx04_buf0, lftx04_buf1 :std_ulogic_vector(0 to 3); + signal lftx16_inv, lftx16_buf0, lftx16_buf1 :std_ulogic_vector(0 to 3); + signal lftx16_0_bus, lftx16_1_bus, lftx16_2_bus, lftx16_3_bus :std_ulogic_vector(0 to 63); + signal lftx04_0_bus, lftx04_1_bus, lftx04_2_bus, lftx04_3_bus :std_ulogic_vector(0 to 63); + signal lftx01_0_bus, lftx01_1_bus, lftx01_2_bus, lftx01_3_bus, lftx01_4_bus :std_ulogic_vector(0 to 63); + + + + + + + +begin + + + word_b(0 to 1) <= not word(0 to 1) ; + + word_bus_b( 0 to 15) <= (0 to 15 => word_b(0) ); + word_bus_b(16 to 31) <= (16 to 31 => word_b(1) ); + word_bus ( 0 to 15) <= (0 to 15 => word (0) ); + word_bus (16 to 31) <= (16 to 31 => word (1) ); + + + u_dhi0adj: data_i0_adj_b(0 to 31) <= not( data_i( 0 to 31) and word_bus_b(0 to 31) ); + u_dhi1adj: data_i1_adj_b(0 to 31) <= not( data_i(32 to 63) and word_bus (0 to 31) ); + u_dhiadj: data_i_adj (0 to 31) <= not( data_i0_adj_b(0 to 31) and data_i1_adj_b(0 to 31) ); + + u_dlo0adj: data_i1_adj_b(32 to 63) <= not( data_i(32 to 63) ); + u_dloadj: data_i_adj (32 to 63) <= not( data_i1_adj_b(32 to 63) ); + + + right_b(0 to 2) <= not right(0 to 2) ; + u_amt_b: amt_b(0 to 5) <= not amt(0 to 5) ; + + u_x16lft_0: x16_lft_b(0) <= not( right_b(0) and amt_b(0) and amt_b(1) ); + u_x16lft_1: x16_lft_b(1) <= not( right_b(0) and amt_b(0) and amt (1) ); + u_x16lft_2: x16_lft_b(2) <= not( right_b(0) and amt (0) and amt_b(1) ); + u_x16lft_3: x16_lft_b(3) <= not( right_b(0) and amt (0) and amt (1) ); + + u_x16rgt_0: x16_rgt_b(0) <= not( right (0) and amt_b(0) and amt_b(1) ); + u_x16rgt_1: x16_rgt_b(1) <= not( right (0) and amt_b(0) and amt (1) ); + u_x16rgt_2: x16_rgt_b(2) <= not( right (0) and amt (0) and amt_b(1) ); + u_x16rgt_3: x16_rgt_b(3) <= not( right (0) and amt (0) and amt (1) ); + + u_lftx16_0: lftx16(0) <= not( x16_lft_b(0) and x16_rgt_b(3) ) ; + u_lftx16_1: lftx16(1) <= not( x16_lft_b(1) and x16_rgt_b(2) ) ; + u_lftx16_2: lftx16(2) <= not( x16_lft_b(2) and x16_rgt_b(1) ) ; + u_lftx16_3: lftx16(3) <= not( x16_lft_b(3) and x16_rgt_b(0) ) ; + + + + u_x04lft_0: x04_lft_b(0) <= not( right_b(1) and amt_b(2) and amt_b(3) ); + u_x04lft_1: x04_lft_b(1) <= not( right_b(1) and amt_b(2) and amt (3) ); + u_x04lft_2: x04_lft_b(2) <= not( right_b(1) and amt (2) and amt_b(3) ); + u_x04lft_3: x04_lft_b(3) <= not( right_b(1) and amt (2) and amt (3) ); + + u_x04rgt_0: x04_rgt_b(0) <= not( right (1) and amt_b(2) and amt_b(3) ); + u_x04rgt_1: x04_rgt_b(1) <= not( right (1) and amt_b(2) and amt (3) ); + u_x04rgt_2: x04_rgt_b(2) <= not( right (1) and amt (2) and amt_b(3) ); + u_x04rgt_3: x04_rgt_b(3) <= not( right (1) and amt (2) and amt (3) ); + + u_lftx04_0: lftx04(0) <= not( x04_lft_b(0) and x04_rgt_b(3) ) ; + u_lftx04_1: lftx04(1) <= not( x04_lft_b(1) and x04_rgt_b(2) ) ; + u_lftx04_2: lftx04(2) <= not( x04_lft_b(2) and x04_rgt_b(1) ) ; + u_lftx04_3: lftx04(3) <= not( x04_lft_b(3) and x04_rgt_b(0) ) ; + + + + u_x01lft_0: x01_lft_b(0) <= not( right_b(2) and amt_b(4) and amt_b(5) ); + u_x01lft_1: x01_lft_b(1) <= not( right_b(2) and amt_b(4) and amt (5) ); + u_x01lft_2: x01_lft_b(2) <= not( right_b(2) and amt (4) and amt_b(5) ); + u_x01lft_3: x01_lft_b(3) <= not( right_b(2) and amt (4) and amt (5) ); + + u_x01rgt_0: x01_rgt_b(0) <= not( right (2) and amt_b(4) and amt_b(5) ); + u_x01rgt_1: x01_rgt_b(1) <= not( right (2) and amt_b(4) and amt (5) ); + u_x01rgt_2: x01_rgt_b(2) <= not( right (2) and amt (4) and amt_b(5) ); + u_x01rgt_3: x01_rgt_b(3) <= not( right (2) and amt (4) and amt (5) ); + + u_lftx01_0: lftx01(0) <= not( x01_lft_b(0) ) ; + u_lftx01_1: lftx01(1) <= not( x01_lft_b(1) and x01_rgt_b(3) ) ; + u_lftx01_2: lftx01(2) <= not( x01_lft_b(2) and x01_rgt_b(2) ) ; + u_lftx01_3: lftx01(3) <= not( x01_lft_b(3) and x01_rgt_b(1) ) ; + u_lftx01_4: lftx01(4) <= not( x01_rgt_b(0) ) ; + + u_lftx16_inv: lftx16_inv (0 to 3) <= not( lftx16 (0 to 3) ); + u_lftx16_buf0: lftx16_buf0(0 to 3) <= not( lftx16_inv(0 to 3) ); + u_lftx16_buf1: lftx16_buf1(0 to 3) <= not( lftx16_inv(0 to 3) ); + + u_lftx04_inv: lftx04_inv (0 to 3) <= not( lftx04 (0 to 3) ); + u_lftx04_buf0: lftx04_buf0(0 to 3) <= not( lftx04_inv(0 to 3) ); + u_lftx04_buf1: lftx04_buf1(0 to 3) <= not( lftx04_inv(0 to 3) ); + + u_lftx01_inv: lftx01_inv (0 to 4) <= not( lftx01 (0 to 4) ); + u_lftx01_buf0: lftx01_buf0(0 to 4) <= not( lftx01_inv(0 to 4) ); + u_lftx01_buf1: lftx01_buf1(0 to 4) <= not( lftx01_inv(0 to 4) ); + + + lftx16_0_bus( 0 to 31) <= ( 0 to 31 => lftx16_buf0(0) ); + lftx16_0_bus(32 to 63) <= (32 to 63 => lftx16_buf1(0) ); + lftx16_1_bus( 0 to 31) <= ( 0 to 31 => lftx16_buf0(1) ); + lftx16_1_bus(32 to 63) <= (32 to 63 => lftx16_buf1(1) ); + lftx16_2_bus( 0 to 31) <= ( 0 to 31 => lftx16_buf0(2) ); + lftx16_2_bus(32 to 63) <= (32 to 63 => lftx16_buf1(2) ); + lftx16_3_bus( 0 to 31) <= ( 0 to 31 => lftx16_buf0(3) ); + lftx16_3_bus(32 to 63) <= (32 to 63 => lftx16_buf1(3) ); + + lftx04_0_bus( 0 to 31) <= ( 0 to 31 => lftx04_buf0(0) ); + lftx04_0_bus(32 to 63) <= (32 to 63 => lftx04_buf1(0) ); + lftx04_1_bus( 0 to 31) <= ( 0 to 31 => lftx04_buf0(1) ); + lftx04_1_bus(32 to 63) <= (32 to 63 => lftx04_buf1(1) ); + lftx04_2_bus( 0 to 31) <= ( 0 to 31 => lftx04_buf0(2) ); + lftx04_2_bus(32 to 63) <= (32 to 63 => lftx04_buf1(2) ); + lftx04_3_bus( 0 to 31) <= ( 0 to 31 => lftx04_buf0(3) ); + lftx04_3_bus(32 to 63) <= (32 to 63 => lftx04_buf1(3) ); + + lftx01_0_bus( 0 to 31) <= ( 0 to 31 => lftx01_buf0(0) ); + lftx01_0_bus(32 to 63) <= (32 to 63 => lftx01_buf1(0) ); + lftx01_1_bus( 0 to 31) <= ( 0 to 31 => lftx01_buf0(1) ); + lftx01_1_bus(32 to 63) <= (32 to 63 => lftx01_buf1(1) ); + lftx01_2_bus( 0 to 31) <= ( 0 to 31 => lftx01_buf0(2) ); + lftx01_2_bus(32 to 63) <= (32 to 63 => lftx01_buf1(2) ); + lftx01_3_bus( 0 to 31) <= ( 0 to 31 => lftx01_buf0(3) ); + lftx01_3_bus(32 to 63) <= (32 to 63 => lftx01_buf1(3) ); + lftx01_4_bus( 0 to 31) <= ( 0 to 31 => lftx01_buf0(4) ); + lftx01_4_bus(32 to 63) <= (32 to 63 => lftx01_buf1(4) ); + + + + + + rolx16_0(0 to 63) <= data_i_adj( 0 to 63) ; + rolx16_1(0 to 63) <= data_i_adj(16 to 63) & data_i_adj(0 to 15) ; + rolx16_2(0 to 63) <= data_i_adj(32 to 63) & data_i_adj(0 to 31) ; + rolx16_3(0 to 63) <= data_i_adj(48 to 63) & data_i_adj(0 to 47) ; + + + u_shd16_0: shd16_0_b(0 to 63) <= not( ( lftx16_0_bus(0 to 63) and rolx16_0(0 to 63) ) or + ( lftx16_1_bus(0 to 63) and rolx16_1(0 to 63) ) ); + u_shd16_1: shd16_1_b(0 to 63) <= not( ( lftx16_2_bus(0 to 63) and rolx16_2(0 to 63) ) or + ( lftx16_3_bus(0 to 63) and rolx16_3(0 to 63) ) ); + u_shd16: shd16 (0 to 63) <= not( shd16_0_b(0 to 63) and shd16_1_b(0 to 63) ); + + + rolx04_0(0 to 63) <= shd16( 0 to 63); + rolx04_1(0 to 63) <= shd16( 4 to 63) & shd16( 0 to 3); + rolx04_2(0 to 63) <= shd16( 8 to 63) & shd16( 0 to 7); + rolx04_3(0 to 63) <= shd16(12 to 63) & shd16( 0 to 11); + + u_shd04_0: shd04_0_b(0 to 63) <= not( ( lftx04_0_bus(0 to 63) and rolx04_0(0 to 63) ) or + ( lftx04_1_bus(0 to 63) and rolx04_1(0 to 63) ) ); + u_shd04_1: shd04_1_b(0 to 63) <= not( ( lftx04_2_bus(0 to 63) and rolx04_2(0 to 63) ) or + ( lftx04_3_bus(0 to 63) and rolx04_3(0 to 63) ) ); + u_shd04: shd04 (0 to 63) <= not( shd04_0_b(0 to 63) and shd04_1_b(0 to 63) ); + + rolx01_0(0 to 63) <= shd04(0 to 63); + rolx01_1(0 to 63) <= shd04(1 to 63) & shd04( 0 ); + rolx01_2(0 to 63) <= shd04(2 to 63) & shd04( 0 to 1); + rolx01_3(0 to 63) <= shd04(3 to 63) & shd04( 0 to 2); + rolx01_4(0 to 63) <= shd04(4 to 63) & shd04( 0 to 3); + + + + u_shd01_0: shd01_0_b(0 to 63) <= not( ( lftx01_0_bus(0 to 63) and rolx01_0(0 to 63) ) or + ( lftx01_1_bus(0 to 63) and rolx01_1(0 to 63) ) ); + u_shd01_1: shd01_1_b(0 to 63) <= not( ( lftx01_2_bus(0 to 63) and rolx01_2(0 to 63) ) or + ( lftx01_3_bus(0 to 63) and rolx01_3(0 to 63) ) ); + u_shd01_2: shd01_2_b(0 to 63) <= not( lftx01_4_bus(0 to 63) and rolx01_4(0 to 63) ); + u_shd01: res_rot (0 to 63) <= not( shd01_0_b(0 to 63) and shd01_1_b(0 to 63) and shd01_2_b(0 to 63) ); + +end architecture xuq_alu_rol64; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_byp.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_byp.vhdl new file mode 100644 index 0000000..85f9fcb --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_byp.vhdl @@ -0,0 +1,499 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee,ibm,support,tri; +use ieee.std_logic_1164.all; +use ibm.std_ulogic_function_support.all; +use tri.tri_latches_pkg.all; +use support.power_logic_pkg.all; +use work.xuq_pkg.all; + +entity xuq_byp is +generic ( + threads : integer := 4; + expand_type : integer := 2; + regsize : integer := 64; + eff_ifar : integer := 62); +port ( + nclk : in clk_logic; + + vdd : inout power_logic; + gnd : inout power_logic; + + d_mode_dc : in std_ulogic; + delay_lclkr_dc : in std_ulogic; + mpw1_dc_b : in std_ulogic; + mpw2_dc_b : in std_ulogic; + func_sl_force : in std_ulogic; + func_sl_thold_0_b : in std_ulogic; + func_nsl_force : in std_ulogic; + func_nsl_thold_0_b : in std_ulogic; + func_slp_sl_force : in std_ulogic; + func_slp_sl_thold_0_b : in std_ulogic; + sg_0 : in std_ulogic; + scan_in : in std_ulogic_vector(0 to 1); + scan_out : out std_ulogic_vector(0 to 1); + + pc_xu_trace_bus_enable : in std_ulogic; + dec_byp_ex3_instr_trace_val : in std_ulogic; + dec_byp_ex3_instr_trace_gate : in std_ulogic; + + xu_ex3_flush : in std_ulogic_vector(0 to threads-1); + xu_ex4_flush : in std_ulogic_vector(0 to threads-1); + xu_ex5_flush : in std_ulogic_vector(0 to threads-1); + + dec_rf1_tid : in std_ulogic_vector(0 to threads-1); + dec_ex1_tid : in std_ulogic_vector(0 to threads-1); + dec_ex2_tid : in std_ulogic_vector(0 to threads-1); + dec_ex3_tid : in std_ulogic_vector(0 to threads-1); + dec_ex5_tid : in std_ulogic_vector(0 to threads-1); + + dec_alu_rf1_sel : in std_ulogic_vector(2 to 2); + dec_byp_rf1_rs0_sel : in std_ulogic_vector(1 to 9); + dec_byp_rf1_rs1_sel : in std_ulogic_vector(1 to 10); + dec_byp_rf1_rs2_sel : in std_ulogic_vector(1 to 9); + dec_byp_rf1_instr : in std_ulogic_vector(6 to 25); + dec_byp_rf1_cr_so_update : in std_ulogic_vector(0 to 1); + dec_byp_ex3_val : in std_ulogic_vector(0 to threads-1); + dec_byp_rf1_cr_we : in std_ulogic; + dec_byp_rf1_is_mcrf : in std_ulogic; + dec_byp_rf1_use_crfld0 : in std_ulogic; + dec_byp_rf1_alu_cmp : in std_ulogic; + dec_byp_rf1_is_mtcrf : in std_ulogic; + dec_byp_rf1_is_mtocrf : in std_ulogic; + dec_byp_rf1_is_isel : in std_ulogic; + dec_byp_rf1_byp_val : in std_ulogic_vector(1 to 3); + dec_byp_ex4_is_eratsxr : in std_ulogic; + dec_byp_rf1_ca_used : in std_ulogic; + dec_byp_rf1_ov_used : in std_ulogic; + dec_byp_ex4_dp_instr : in std_ulogic; + dec_byp_ex4_mtdp_val : in std_ulogic; + dec_byp_ex4_mfdp_val : in std_ulogic; + dec_byp_rf0_act : in std_ulogic; + fxa_fxb_rf0_is_mfocrf : in std_ulogic; + + dec_byp_ex1_spr_sel : in std_ulogic; + lsu_xu_ex5_wren : in std_ulogic; + dec_byp_ex4_is_mfcr : in std_ulogic; + spr_byp_ex4_is_mfxer : in std_ulogic_vector(0 to 3); + dec_byp_ex3_tlb_sel : in std_ulogic_vector(0 to 1); + alu_ex2_div_done : in std_ulogic; + + slowspr_val_in : in std_ulogic; + slowspr_rw_in : in std_ulogic; + slowspr_etid_in : in std_ulogic_vector(0 to 1); + slowspr_addr_in : in std_ulogic_vector(0 to 9); + slowspr_done_in : in std_ulogic; + + dec_byp_ex4_dcr_ack : in std_ulogic; + an_ac_dcr_act : in std_ulogic; + an_ac_dcr_read : in std_ulogic; + an_ac_dcr_etid : in std_ulogic_vector(0 to 1); + an_ac_dcr_data : in std_ulogic_vector(64-regsize to 63); + an_ac_dcr_done : in std_ulogic; + + xu_iu_slowspr_done : out std_ulogic_vector(0 to 3); + mux_cpl_slowspr_done : out std_ulogic_vector(0 to 3); + mux_cpl_slowspr_flush : out std_ulogic_vector(0 to 3); + + dec_byp_rf1_imm : in std_ulogic_vector(64-regsize to 63); + fxa_fxb_rf1_do0 : in std_ulogic_vector(64-regsize to 63); + fxa_fxb_rf1_do1 : in std_ulogic_vector(64-regsize to 63); + fxa_fxb_rf1_do2 : in std_ulogic_vector(64-regsize to 63); + + alu_byp_ex1_log_rt : in std_ulogic_vector(64-regsize to 63); + alu_byp_ex2_rt : in std_ulogic_vector(64-regsize to 63); + alu_byp_ex3_div_rt : in std_ulogic_vector(64-regsize to 63); + cpl_byp_ex3_spr_rt : in std_ulogic_vector(64-regsize to 63); + spr_byp_ex3_spr_rt : in std_ulogic_vector(64-regsize to 63); + fspr_byp_ex3_spr_rt : in std_ulogic_vector(64-regsize to 63); + lsu_xu_ex4_tlb_data : in std_ulogic_vector(64-regsize to 63); + iu_xu_ex4_tlb_data : in std_ulogic_vector(64-regsize to 63); + alu_byp_ex5_mul_rt : in std_ulogic_vector(64-regsize to 63); + lsu_xu_rot_ex6_data_b : in std_ulogic_vector(64-regsize to 63); + lsu_xu_rot_rel_data : in std_ulogic_vector(64-regsize to 63); + slowspr_data_in : in std_ulogic_vector(64-regsize to 63); + + byp_dec_rf1_xer_ca : out std_ulogic; + byp_alu_ex1_rs0 : out std_ulogic_vector(64-regsize to 63); + byp_alu_ex1_rs1 : out std_ulogic_vector(64-regsize to 63); + byp_alu_ex1_mulsrc_0 : out std_ulogic_vector(64-regsize to 63); + byp_alu_ex1_mulsrc_1 : out std_ulogic_vector(64-regsize to 63); + byp_alu_ex1_divsrc_0 : out std_ulogic_vector(64-regsize to 63); + byp_alu_ex1_divsrc_1 : out std_ulogic_vector(64-regsize to 63); + xu_lsu_ex1_add_src0 : out std_ulogic_vector(64-regsize to 63); + xu_lsu_ex1_add_src1 : out std_ulogic_vector(64-regsize to 63); + + xu_ex1_rs_is : out std_ulogic_vector(0 to 8); + xu_ex1_ra_entry : out std_ulogic_vector(7 to 11); + xu_ex1_rb : out std_ulogic_vector(64-regsize to 51); + xu_ex4_rs_data : out std_ulogic_vector(64-regsize to 63); + xu_mm_derat_epn : out std_ulogic_vector(62-eff_ifar to 51); + xu_pc_ram_data : out std_ulogic_vector(64-regsize to 63); + mux_spr_ex6_rt : out std_ulogic_vector(64-regsize to 63); + byp_xer_si : out std_ulogic_vector(0 to 7*threads-1); + + fu_xu_ex4_cr_val : in std_ulogic_vector(0 to threads-1); + fu_xu_ex4_cr_noflush : in std_ulogic_vector(0 to threads-1); + fu_xu_ex4_cr0 : in std_ulogic_vector(0 to 3); + fu_xu_ex4_cr0_bf : in std_ulogic_vector(0 to 2); + fu_xu_ex4_cr1 : in std_ulogic_vector(0 to 3); + fu_xu_ex4_cr1_bf : in std_ulogic_vector(0 to 2); + fu_xu_ex4_cr2 : in std_ulogic_vector(0 to 3); + fu_xu_ex4_cr2_bf : in std_ulogic_vector(0 to 2); + fu_xu_ex4_cr3 : in std_ulogic_vector(0 to 3); + fu_xu_ex4_cr3_bf : in std_ulogic_vector(0 to 2); + + mm_xu_cr0_eq_valid : in std_ulogic_vector(0 to threads-1); + mm_xu_cr0_eq : in std_ulogic_vector(0 to threads-1); + + an_ac_stcx_complete : in std_ulogic_vector(0 to threads-1); + an_ac_stcx_pass : in std_ulogic_vector(0 to threads-1); + + an_ac_back_inv : in std_ulogic; + an_ac_back_inv_addr : in std_ulogic_vector(58 to 63); + an_ac_back_inv_target_bit3 : in std_ulogic; + + lsu_xu_ex4_mtdp_cr_status : in std_ulogic; + lsu_xu_ex4_mfdp_cr_status : in std_ulogic; + + dec_byp_ex4_is_wchkall : in std_ulogic; + lsu_xu_ex4_cr_upd : in std_ulogic; + lsu_xu_ex5_cr_rslt : in std_ulogic; + + alu_byp_ex2_cr_recform : in std_ulogic_vector(0 to 3); + alu_byp_ex5_cr_mul : in std_ulogic_vector(0 to 4); + alu_byp_ex3_cr_div : in std_ulogic_vector(0 to 4); + alu_byp_ex2_xer : in std_ulogic_vector(0 to 3); + alu_byp_ex5_xer_mul : in std_ulogic_vector(0 to 3); + alu_byp_ex3_xer_div : in std_ulogic_vector(0 to 3); + alu_ex4_mul_done : in std_ulogic; + spr_byp_ex4_is_mtxer : in std_ulogic_vector(0 to threads-1); + byp_cpl_ex1_cr_bit : out std_ulogic; + + byp_alu_rf1_isel_fcn : out std_ulogic_vector(0 to 3); + + spr_msr_cm : in std_ulogic_vector(0 to threads-1); + dec_byp_ex5_instr : in std_ulogic_vector(12 to 19); + + byp_perf_tx_events : out std_ulogic_vector(0 to 3*threads-1); + + mux_cpl_ex4_rt : out std_ulogic_vector(64-regsize to 63); + byp_spr_ex6_rt : out std_ulogic_vector(64-regsize to 63); + xu_lsu_ex1_store_data : out std_ulogic_vector(64-regsize to 63); + fxu_spr_ex1_rs2 : out std_ulogic_vector(42 to 55); + fxu_spr_ex1_rs1 : out std_ulogic_vector(54 to 63); + fxu_spr_ex1_rs0 : out std_ulogic_vector(52 to 63); + fxb_fxa_ex7_wd0 : out std_ulogic_vector(64-regsize to 63); + + byp_grp0_debug : out std_ulogic_vector( 0 to 87); + byp_grp1_debug : out std_ulogic_vector( 0 to 87); + byp_grp2_debug : out std_ulogic_vector( 0 to 87); + byp_grp3_debug : out std_ulogic_vector(15 to 87); + byp_grp4_debug : out std_ulogic_vector(14 to 87); + byp_grp5_debug : out std_ulogic_vector(15 to 87); + byp_grp6_debug : out std_ulogic_vector(0 to 87); + byp_grp7_debug : out std_ulogic_vector(0 to 87); + byp_grp8_debug : out std_ulogic_vector(22 to 87) + ); + +-- synopsys translate_off +-- synopsys translate_on + +end xuq_byp; +architecture xuq_byp of xuq_byp is + +constant tidn : std_ulogic := '0'; + +signal siv, sov : std_ulogic_vector(0 to 1); +signal byp_ex5_cr_rt : std_ulogic_vector(32 to 63); +signal byp_ex5_xer_rt : std_ulogic_vector(54 to 63); +signal ex1_mfocrf_rt : std_ulogic_vector(64-regsize to 63); +signal byp_ex5_mtcrxer : std_ulogic_vector(32 to 63); +signal byp_ex5_tlb_rt : std_ulogic_vector(51 to 51); +signal byp_xer_so : std_ulogic_vector(0 to threads-1); +signal xer_cr_ex1_xer_ov_in_pipe : std_ulogic; +signal xer_cr_ex2_xer_ov_in_pipe : std_ulogic; +signal xer_cr_ex3_xer_ov_in_pipe : std_ulogic; +signal xer_cr_ex5_xer_ov_in_pipe : std_ulogic; +signal trace_bus_enable : std_ulogic; + +begin + +xu_byp_gpr : entity work.xuq_byp_gpr(xuq_byp_gpr) +generic map( + threads => threads, + expand_type => expand_type, + regsize => regsize, + eff_ifar => eff_ifar) +port map( + nclk => nclk, + vdd => vdd, + gnd => gnd, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc, + mpw1_dc_b => mpw1_dc_b, + mpw2_dc_b => mpw2_dc_b, + func_sl_force => func_sl_force, + func_sl_thold_0_b => func_sl_thold_0_b, + func_slp_sl_force => func_slp_sl_force, + func_slp_sl_thold_0_b => func_slp_sl_thold_0_b, + func_nsl_force => func_nsl_force, + func_nsl_thold_0_b => func_nsl_thold_0_b, + sg_0 => sg_0, + scan_in => scan_in(0), + scan_out => scan_out(0), + pc_xu_trace_bus_enable => pc_xu_trace_bus_enable, + dec_byp_ex3_instr_trace_val => dec_byp_ex3_instr_trace_val, + dec_byp_ex3_instr_trace_gate => dec_byp_ex3_instr_trace_gate, + trace_bus_enable => trace_bus_enable, + dec_rf1_tid => dec_rf1_tid, + dec_ex2_tid => dec_ex2_tid, + dec_byp_rf0_act => dec_byp_rf0_act, + dec_alu_rf1_sel => dec_alu_rf1_sel, + dec_byp_rf1_rs0_sel => dec_byp_rf1_rs0_sel, + dec_byp_rf1_rs1_sel => dec_byp_rf1_rs1_sel, + dec_byp_rf1_rs2_sel => dec_byp_rf1_rs2_sel, + fxa_fxb_rf0_is_mfocrf => fxa_fxb_rf0_is_mfocrf, + dec_byp_ex1_spr_sel => dec_byp_ex1_spr_sel, + alu_ex2_div_done => alu_ex2_div_done, + dec_byp_ex3_tlb_sel => dec_byp_ex3_tlb_sel, + alu_ex4_mul_done => alu_ex4_mul_done, + dec_byp_ex4_is_mfcr => dec_byp_ex4_is_mfcr, + spr_byp_ex4_is_mfxer => spr_byp_ex4_is_mfxer, + lsu_xu_ex5_wren => lsu_xu_ex5_wren, + slowspr_val_in => slowspr_val_in, + slowspr_rw_in => slowspr_rw_in, + slowspr_etid_in => slowspr_etid_in, + slowspr_addr_in => slowspr_addr_in, + slowspr_done_in => slowspr_done_in, + dec_byp_ex4_dcr_ack => dec_byp_ex4_dcr_ack, + an_ac_dcr_act => an_ac_dcr_act, + an_ac_dcr_read => an_ac_dcr_read, + an_ac_dcr_etid => an_ac_dcr_etid, + an_ac_dcr_data => an_ac_dcr_data, + an_ac_dcr_done => an_ac_dcr_done, + xu_iu_slowspr_done => xu_iu_slowspr_done, + mux_cpl_slowspr_done => mux_cpl_slowspr_done, + mux_cpl_slowspr_flush => mux_cpl_slowspr_flush, + dec_byp_rf1_imm => dec_byp_rf1_imm, + fxa_fxb_rf1_do0 => fxa_fxb_rf1_do0, + fxa_fxb_rf1_do1 => fxa_fxb_rf1_do1, + fxa_fxb_rf1_do2 => fxa_fxb_rf1_do2, + alu_byp_ex1_log_rt => alu_byp_ex1_log_rt, + alu_byp_ex2_rt => alu_byp_ex2_rt, + alu_byp_ex3_div_rt => alu_byp_ex3_div_rt, + cpl_byp_ex3_spr_rt => cpl_byp_ex3_spr_rt, + spr_byp_ex3_spr_rt => spr_byp_ex3_spr_rt, + fspr_byp_ex3_spr_rt => fspr_byp_ex3_spr_rt, + lsu_xu_ex4_tlb_data => lsu_xu_ex4_tlb_data, + iu_xu_ex4_tlb_data => iu_xu_ex4_tlb_data, + alu_byp_ex5_mul_rt => alu_byp_ex5_mul_rt, + lsu_xu_rot_ex6_data_b => lsu_xu_rot_ex6_data_b, + lsu_xu_rot_rel_data => lsu_xu_rot_rel_data, + slowspr_data_in => slowspr_data_in, + byp_ex5_cr_rt => byp_ex5_cr_rt, + byp_ex5_xer_rt => byp_ex5_xer_rt, + ex1_mfocrf_rt => ex1_mfocrf_rt, + byp_alu_ex1_rs0 => byp_alu_ex1_rs0, + byp_alu_ex1_rs1 => byp_alu_ex1_rs1, + byp_alu_ex1_mulsrc_0 => byp_alu_ex1_mulsrc_0, + byp_alu_ex1_mulsrc_1 => byp_alu_ex1_mulsrc_1, + byp_alu_ex1_divsrc_0 => byp_alu_ex1_divsrc_0, + byp_alu_ex1_divsrc_1 => byp_alu_ex1_divsrc_1, + xu_lsu_ex1_add_src0 => xu_lsu_ex1_add_src0, + xu_lsu_ex1_add_src1 => xu_lsu_ex1_add_src1, + xu_ex1_rs_is => xu_ex1_rs_is, + xu_ex1_ra_entry => xu_ex1_ra_entry, + xu_ex1_rb => xu_ex1_rb, + xu_ex4_rs_data => xu_ex4_rs_data, + xu_mm_derat_epn => xu_mm_derat_epn, + xu_pc_ram_data => xu_pc_ram_data, + mux_spr_ex6_rt => mux_spr_ex6_rt, + spr_msr_cm => spr_msr_cm, + mux_cpl_ex4_rt => mux_cpl_ex4_rt, + byp_spr_ex6_rt => byp_spr_ex6_rt, + xu_lsu_ex1_store_data => xu_lsu_ex1_store_data, + fxu_spr_ex1_rs2 => fxu_spr_ex1_rs2, + fxu_spr_ex1_rs1 => fxu_spr_ex1_rs1, + fxu_spr_ex1_rs0 => fxu_spr_ex1_rs0, + fxb_fxa_ex7_wd0 => fxb_fxa_ex7_wd0, + byp_ex5_mtcrxer => byp_ex5_mtcrxer, + byp_ex5_tlb_rt => byp_ex5_tlb_rt, + byp_grp0_debug => byp_grp0_debug, + byp_grp1_debug => byp_grp1_debug, + byp_grp2_debug => byp_grp2_debug, + byp_grp3_debug => byp_grp3_debug, + byp_grp4_debug => byp_grp4_debug, + byp_grp5_debug => byp_grp5_debug + ); + + +xu_byp_cr : entity work.xuq_byp_cr(xuq_byp_cr) +generic map( + threads => threads, + expand_type => expand_type, + regsize => regsize) +port map( + nclk => nclk, + vdd => vdd, + gnd => gnd, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc, + mpw1_dc_b => mpw1_dc_b, + mpw2_dc_b => mpw2_dc_b, + func_sl_force => func_sl_force, + func_sl_thold_0_b => func_sl_thold_0_b, + func_nsl_force => func_nsl_force, + func_nsl_thold_0_b => func_nsl_thold_0_b, + func_slp_sl_force => func_slp_sl_force, + func_slp_sl_thold_0_b => func_slp_sl_thold_0_b, + sg_0 => sg_0, + scan_in => siv(0), + scan_out => sov(0), + trace_bus_enable => trace_bus_enable, + dec_byp_ex3_val => dec_byp_ex3_val, + xu_ex3_flush => xu_ex3_flush, + xu_ex4_flush => xu_ex4_flush, + xu_ex5_flush => xu_ex5_flush, + rf1_tid => dec_rf1_tid, + ex1_tid => dec_ex1_tid, + ex2_tid => dec_ex2_tid, + ex3_tid => dec_ex3_tid, + ex5_tid => dec_ex5_tid, + rf1_instr => dec_byp_rf1_instr, + dec_byp_rf1_cr_so_update => dec_byp_rf1_cr_so_update, + dec_byp_rf1_cr_we => dec_byp_rf1_cr_we, + dec_byp_rf1_is_mcrf => dec_byp_rf1_is_mcrf, + dec_byp_rf1_use_crfld0 => dec_byp_rf1_use_crfld0, + dec_byp_rf1_alu_cmp => dec_byp_rf1_alu_cmp, + dec_byp_rf1_is_mtcrf => dec_byp_rf1_is_mtcrf, + dec_byp_rf1_is_mtocrf => dec_byp_rf1_is_mtocrf, + fxa_fxb_rf0_is_mfocrf => fxa_fxb_rf0_is_mfocrf, + dec_byp_rf1_is_isel => dec_byp_rf1_is_isel, + dec_byp_rf1_byp_val => dec_byp_rf1_byp_val, + dec_byp_rf0_act => dec_byp_rf0_act, + dec_byp_ex4_is_eratsxr => dec_byp_ex4_is_eratsxr, + dec_byp_ex4_dp_instr => dec_byp_ex4_dp_instr, + dec_byp_ex4_mtdp_val => dec_byp_ex4_mtdp_val, + dec_byp_ex4_mfdp_val => dec_byp_ex4_mfdp_val, + lsu_xu_ex4_mtdp_cr_status => lsu_xu_ex4_mtdp_cr_status, + lsu_xu_ex4_mfdp_cr_status => lsu_xu_ex4_mfdp_cr_status, + dec_byp_ex4_is_wchkall => dec_byp_ex4_is_wchkall, + lsu_xu_ex4_cr_upd => lsu_xu_ex4_cr_upd, + lsu_xu_ex5_cr_rslt => lsu_xu_ex5_cr_rslt, + byp_cpl_ex1_cr_bit => byp_cpl_ex1_cr_bit, + byp_alu_rf1_isel_fcn => byp_alu_rf1_isel_fcn, + alu_byp_ex2_cr_recform => alu_byp_ex2_cr_recform, + alu_byp_ex5_cr_mul => alu_byp_ex5_cr_mul, + alu_byp_ex3_cr_div => alu_byp_ex3_cr_div, + alu_ex2_div_done => alu_ex2_div_done, + fu_xu_ex4_cr_val => fu_xu_ex4_cr_val, + fu_xu_ex4_cr_noflush => fu_xu_ex4_cr_noflush, + fu_xu_ex4_cr0 => fu_xu_ex4_cr0, + fu_xu_ex4_cr0_bf => fu_xu_ex4_cr0_bf, + fu_xu_ex4_cr1 => fu_xu_ex4_cr1, + fu_xu_ex4_cr1_bf => fu_xu_ex4_cr1_bf, + fu_xu_ex4_cr2 => fu_xu_ex4_cr2, + fu_xu_ex4_cr2_bf => fu_xu_ex4_cr2_bf, + fu_xu_ex4_cr3 => fu_xu_ex4_cr3, + fu_xu_ex4_cr3_bf => fu_xu_ex4_cr3_bf, + mm_xu_cr0_eq_valid => mm_xu_cr0_eq_valid, + mm_xu_cr0_eq => mm_xu_cr0_eq, + an_ac_stcx_complete => an_ac_stcx_complete, + an_ac_stcx_pass => an_ac_stcx_pass, + an_ac_back_inv => an_ac_back_inv, + an_ac_back_inv_addr => an_ac_back_inv_addr, + an_ac_back_inv_target_bit3 => an_ac_back_inv_target_bit3, + byp_ex5_mtcrxer => byp_ex5_mtcrxer, + byp_ex5_tlb_rt => byp_ex5_tlb_rt, + ex5_cr_rt => byp_ex5_cr_rt, + ex1_mfocrf_rt => ex1_mfocrf_rt, + dec_cr_ex5_instr => dec_byp_ex5_instr, + byp_perf_tx_events => byp_perf_tx_events, + byp_xer_so => byp_xer_so, + xer_cr_ex1_xer_ov_in_pipe => xer_cr_ex1_xer_ov_in_pipe, + xer_cr_ex2_xer_ov_in_pipe => xer_cr_ex2_xer_ov_in_pipe, + xer_cr_ex3_xer_ov_in_pipe => xer_cr_ex3_xer_ov_in_pipe, + xer_cr_ex5_xer_ov_in_pipe => xer_cr_ex5_xer_ov_in_pipe, + cr_grp0_debug => byp_grp6_debug, + cr_grp1_debug => byp_grp7_debug + ); + +xu_byp_xer : entity work.xuq_byp_xer(xuq_byp_xer) +generic map( + threads => threads, + expand_type => expand_type, + regsize => regsize) +port map( + nclk => nclk, + vdd => vdd, + gnd => gnd, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc, + mpw1_dc_b => mpw1_dc_b, + mpw2_dc_b => mpw2_dc_b, + func_sl_force => func_sl_force, + func_sl_thold_0_b => func_sl_thold_0_b, + func_slp_sl_force => func_slp_sl_force, + func_slp_sl_thold_0_b => func_slp_sl_thold_0_b, + sg_0 => sg_0, + scan_in => siv(1), + scan_out => sov(1), + trace_bus_enable => trace_bus_enable, + dec_byp_rf1_ca_used => dec_byp_rf1_ca_used, + dec_byp_rf1_ov_used => dec_byp_rf1_ov_used, + rf1_tid => dec_rf1_tid, + ex5_tid => dec_ex5_tid, + dec_byp_ex3_val => dec_byp_ex3_val, + dec_byp_rf1_byp_val => dec_byp_rf1_byp_val(2 to 3), + xu_ex3_flush => xu_ex3_flush, + xu_ex4_flush => xu_ex4_flush, + xu_ex5_flush => xu_ex5_flush, + byp_ex5_xer_rt => byp_ex5_xer_rt, + alu_ex4_mul_done => alu_ex4_mul_done, + alu_ex2_div_done => alu_ex2_div_done, + alu_byp_ex2_xer => alu_byp_ex2_xer, + alu_byp_ex5_xer_mul => alu_byp_ex5_xer_mul, + alu_byp_ex3_xer_div => alu_byp_ex3_xer_div, + spr_byp_ex4_is_mtxer => spr_byp_ex4_is_mtxer, + byp_ex5_mtcrxer => byp_ex5_mtcrxer, + byp_xer_si => byp_xer_si, + byp_xer_so => byp_xer_so, + xer_cr_ex1_xer_ov_in_pipe => xer_cr_ex1_xer_ov_in_pipe, + xer_cr_ex2_xer_ov_in_pipe => xer_cr_ex2_xer_ov_in_pipe, + xer_cr_ex3_xer_ov_in_pipe => xer_cr_ex3_xer_ov_in_pipe, + xer_cr_ex5_xer_ov_in_pipe => xer_cr_ex5_xer_ov_in_pipe, + byp_dec_rf1_xer_ca => byp_dec_rf1_xer_ca, + xer_debug => byp_grp8_debug); + + +siv(0 to siv'right) <= sov(1 to siv'right) & scan_in(1); +scan_out(1) <= sov(0); + +end architecture xuq_byp; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_byp_cr.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_byp_cr.vhdl new file mode 100644 index 0000000..4f8742a --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_byp_cr.vhdl @@ -0,0 +1,1605 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee,ibm,support,tri,clib,work; +use ieee.std_logic_1164.all; +use ibm.std_ulogic_function_support.all; +use tri.tri_latches_pkg.all; +use support.power_logic_pkg.all; +use work.xuq_pkg.all; + +entity xuq_byp_cr is + generic ( + threads : integer := 4; + expand_type : integer := 2; + regsize : integer := 64); + port ( + nclk : in clk_logic; + + vdd : inout power_logic; + gnd : inout power_logic; + + d_mode_dc : in std_ulogic; + delay_lclkr_dc : in std_ulogic; + mpw1_dc_b : in std_ulogic; + mpw2_dc_b : in std_ulogic; + func_sl_force : in std_ulogic; + func_sl_thold_0_b : in std_ulogic; + func_nsl_force : in std_ulogic; + func_nsl_thold_0_b : in std_ulogic; + func_slp_sl_force : in std_ulogic; + func_slp_sl_thold_0_b : in std_ulogic; + sg_0 : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + trace_bus_enable : in std_ulogic; + + dec_byp_ex3_val : in std_ulogic_vector(0 to threads-1); + + xu_ex3_flush : in std_ulogic_vector(0 to threads-1); + xu_ex4_flush : in std_ulogic_vector(0 to threads-1); + xu_ex5_flush : in std_ulogic_vector(0 to threads-1); + + rf1_tid : in std_ulogic_vector(0 to threads-1); + ex1_tid : in std_ulogic_vector(0 to threads-1); + ex2_tid : in std_ulogic_vector(0 to threads-1); + ex3_tid : in std_ulogic_vector(0 to threads-1); + ex5_tid : in std_ulogic_vector(0 to threads-1); + rf1_instr : in std_ulogic_vector(6 to 25); + + fxa_fxb_rf0_is_mfocrf : in std_ulogic; + dec_byp_rf1_cr_so_update : in std_ulogic_vector(0 to 1); + dec_byp_rf1_cr_we : in std_ulogic; + dec_byp_rf1_is_mcrf : in std_ulogic; + dec_byp_rf1_use_crfld0 : in std_ulogic; + dec_byp_rf1_alu_cmp : in std_ulogic; + dec_byp_rf1_is_mtcrf : in std_ulogic; + dec_byp_rf1_is_mtocrf : in std_ulogic; + dec_byp_rf1_is_isel : in std_ulogic; + dec_byp_rf1_byp_val : in std_ulogic_vector(1 to 3); + dec_byp_rf0_act : in std_ulogic; + dec_byp_ex4_is_eratsxr : in std_ulogic; + + dec_byp_ex4_dp_instr : in std_ulogic; + dec_byp_ex4_mtdp_val : in std_ulogic; + dec_byp_ex4_mfdp_val : in std_ulogic; + lsu_xu_ex4_mtdp_cr_status : in std_ulogic; + lsu_xu_ex4_mfdp_cr_status : in std_ulogic; + + dec_byp_ex4_is_wchkall : in std_ulogic; + lsu_xu_ex4_cr_upd : in std_ulogic; + lsu_xu_ex5_cr_rslt : in std_ulogic; + + byp_cpl_ex1_cr_bit : out std_ulogic; + byp_alu_rf1_isel_fcn : out std_ulogic_vector(0 to 3); + + alu_byp_ex2_cr_recform : in std_ulogic_vector(0 to 3); + alu_byp_ex5_cr_mul : in std_ulogic_vector(0 to 4); + alu_byp_ex3_cr_div : in std_ulogic_vector(0 to 4); + alu_ex2_div_done : in std_ulogic; + + fu_xu_ex4_cr_val : in std_ulogic_vector(0 to threads-1); + fu_xu_ex4_cr_noflush : in std_ulogic_vector(0 to threads-1); + fu_xu_ex4_cr0 : in std_ulogic_vector(0 to 3); + fu_xu_ex4_cr0_bf : in std_ulogic_vector(0 to 2); + fu_xu_ex4_cr1 : in std_ulogic_vector(0 to 3); + fu_xu_ex4_cr1_bf : in std_ulogic_vector(0 to 2); + fu_xu_ex4_cr2 : in std_ulogic_vector(0 to 3); + fu_xu_ex4_cr2_bf : in std_ulogic_vector(0 to 2); + fu_xu_ex4_cr3 : in std_ulogic_vector(0 to 3); + fu_xu_ex4_cr3_bf : in std_ulogic_vector(0 to 2); + + mm_xu_cr0_eq_valid : in std_ulogic_vector(0 to threads-1); + mm_xu_cr0_eq : in std_ulogic_vector(0 to threads-1); + + an_ac_stcx_complete : in std_ulogic_vector(0 to threads-1); + an_ac_stcx_pass : in std_ulogic_vector(0 to threads-1); + + an_ac_back_inv : in std_ulogic; + an_ac_back_inv_addr : in std_ulogic_vector(58 to 63); + an_ac_back_inv_target_bit3 : in std_ulogic; + + byp_ex5_mtcrxer : in std_ulogic_vector(32 to 63); + byp_ex5_tlb_rt : in std_ulogic_vector(51 to 51); + ex5_cr_rt : out std_ulogic_vector(32 to 63); + ex1_mfocrf_rt : out std_ulogic_vector(64-regsize to 63); + + dec_cr_ex5_instr : in std_ulogic_vector(12 to 19); + + byp_perf_tx_events : out std_ulogic_vector(0 to 3*threads-1); + + byp_xer_so : in std_ulogic_vector(0 to threads-1); + xer_cr_ex1_xer_ov_in_pipe : in std_ulogic; + xer_cr_ex2_xer_ov_in_pipe : in std_ulogic; + xer_cr_ex3_xer_ov_in_pipe : in std_ulogic; + xer_cr_ex5_xer_ov_in_pipe : in std_ulogic; + + cr_grp0_debug : out std_ulogic_vector(0 to 87); + cr_grp1_debug : out std_ulogic_vector(0 to 87) + ); + +-- synopsys translate_off + +-- synopsys translate_on +end xuq_byp_cr; +architecture xuq_byp_cr of xuq_byp_cr is + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + type CR_ARY is array (0 to threads-1) of std_ulogic_vector(0 to 7); + subtype s2 is std_ulogic_vector(0 to 1); + subtype s5 is std_ulogic_vector(0 to 4); + + signal rf1_is_mfocrf_q : std_ulogic; + signal ex1_alu_cmp_q : std_ulogic; + signal ex1_any_mtcrf_q, ex1_any_mtcrf_d : std_ulogic; + signal ex1_cr0_q : std_ulogic_vector(0 to 3); + signal ex1_cr0_bit_q, rf1_cr0_bit : std_ulogic; + signal ex1_cr1_q : std_ulogic_vector(0 to 3); + signal ex1_cr1_bit_q, rf1_cr1_bit_i : std_ulogic; + signal ex1_cr_so_update_q : std_ulogic_vector(0 to 1); + signal ex1_cr_we_q : std_ulogic; + signal ex1_crt_q, rf1_crt : std_ulogic_vector(0 to 3); + signal ex1_crt_mask_q, rf1_crt_mask : std_ulogic_vector(0 to 3); + signal ex1_instr_q : std_ulogic_vector(6 to 19); + signal ex1_instr_2_q : std_ulogic_vector(22 to 25); + signal ex1_is_mcrf_q : std_ulogic; + signal ex1_use_crfld0_q : std_ulogic; + signal ex2_alu_cmp_q : std_ulogic; + signal ex2_any_mtcrf_q : std_ulogic; + signal ex2_cr_q : std_ulogic_vector(0 to 7); + signal ex2_cr_we_q : std_ulogic; + signal ex2_instr_q : std_ulogic_vector(6 to 8); + signal ex2_use_crfld0_q : std_ulogic; + signal ex3_any_mtcrf_q : std_ulogic; + signal ex3_cr_q : std_ulogic_vector(0 to 7); + signal ex3_div_done_q : std_ulogic; + signal ex3_instr_q : std_ulogic_vector(6 to 8); + signal ex4_any_mtcrf_q : std_ulogic; + signal ex4_cr_q : std_ulogic_vector(0 to 7); + signal ex4_instr_q : std_ulogic_vector(6 to 8); + signal ex4_val_q, ex3_val : std_ulogic_vector(0 to threads-1); + signal ex5_any_mtcrf_q : std_ulogic; + signal ex5_axu_val_q, ex4_axu_val : std_ulogic_vector(0 to threads-1); + signal ex5_cr_q : std_ulogic_vector(0 to 7); + signal ex5_dp_instr_q : std_ulogic; + signal ex5_fu_cr0_q : std_ulogic_vector(0 to 3); + signal ex5_fu_cr0_bf_q : std_ulogic_vector(0 to 2); + signal ex5_fu_cr1_q : std_ulogic_vector(0 to 3); + signal ex5_fu_cr1_bf_q : std_ulogic_vector(0 to 2); + signal ex5_fu_cr2_q : std_ulogic_vector(0 to 3); + signal ex5_fu_cr2_bf_q : std_ulogic_vector(0 to 2); + signal ex5_fu_cr3_q : std_ulogic_vector(0 to 3); + signal ex5_fu_cr3_bf_q : std_ulogic_vector(0 to 2); + signal ex5_fu_cr_noflush_q : std_ulogic_vector(0 to threads-1); + signal ex5_fu_cr_val_q : std_ulogic_vector(0 to threads-1); + signal ex5_is_eratsxr_q : std_ulogic; + signal ex5_mfdp_cr_status_q : std_ulogic; + signal ex5_mfdp_val_q : std_ulogic; + signal ex5_mtdp_cr_status_q : std_ulogic; + signal ex5_mtdp_val_q : std_ulogic; + signal ex5_val_q, ex4_val : std_ulogic_vector(0 to threads-1); + signal ex5_watch_we_q, ex5_watch_we_d : std_ulogic; + signal ex5_wchkall_fld_q, ex5_wchkall_fld_d : std_ulogic_vector(0 to 2); + signal an_ac_back_inv_q : std_ulogic; + signal an_ac_back_inv_addr_q : std_ulogic_vector(58 to 63); + signal an_ac_back_inv_target_bit3_q : std_ulogic; + signal back_inv_val_q, back_inv_val_d : std_ulogic; + signal cr_barrier_we_q, cr_barrier_we_d : std_ulogic_vector(0 to threads-1); + signal exx_act_q, exx_act_d : std_ulogic_vector(0 to 4); + signal mmu_cr0_eq_q : std_ulogic_vector(0 to threads-1); + signal mmu_cr0_eq_valid_q : std_ulogic_vector(0 to threads-1); + signal stcx_complete_q : std_ulogic_vector(0 to threads-1); + signal stcx_pass_q : std_ulogic_vector(0 to threads-1); + signal ex1_cr0_byp_pri_dbg_q : std_ulogic_vector(1 to 6); + signal ex1_cr1_byp_pri_dbg_q : std_ulogic_vector(1 to 6); + signal ex1_crt_byp_pri_dbg_q : std_ulogic_vector(1 to 6); + signal ex6_val_dbg_q : std_ulogic_vector(0 to threads-1); + + constant ex1_alu_cmp_offset : integer := 0; + constant ex1_any_mtcrf_offset : integer := ex1_alu_cmp_offset + 1; + constant ex1_cr0_offset : integer := ex1_any_mtcrf_offset + 1; + constant ex1_cr0_bit_offset : integer := ex1_cr0_offset + ex1_cr0_q'length; + constant ex1_cr1_offset : integer := ex1_cr0_bit_offset + 1; + constant ex1_cr1_bit_offset : integer := ex1_cr1_offset + ex1_cr1_q'length; + constant ex1_cr_so_update_offset : integer := ex1_cr1_bit_offset + 1; + constant ex1_cr_we_offset : integer := ex1_cr_so_update_offset + ex1_cr_so_update_q'length; + constant ex1_crt_offset : integer := ex1_cr_we_offset + 1; + constant ex1_crt_mask_offset : integer := ex1_crt_offset + ex1_crt_q'length; + constant ex1_instr_offset : integer := ex1_crt_mask_offset + ex1_crt_mask_q'length; + constant ex1_instr_2_offset : integer := ex1_instr_offset + ex1_instr_q'length; + constant ex1_is_mcrf_offset : integer := ex1_instr_2_offset + ex1_instr_2_q'length; + constant ex1_use_crfld0_offset : integer := ex1_is_mcrf_offset + 1; + constant ex3_any_mtcrf_offset : integer := ex1_use_crfld0_offset + 1; + constant ex3_cr_offset : integer := ex3_any_mtcrf_offset + 1; + constant ex3_div_done_offset : integer := ex3_cr_offset + ex3_cr_q'length; + constant ex3_instr_offset : integer := ex3_div_done_offset + 1; + constant ex5_any_mtcrf_offset : integer := ex3_instr_offset + ex3_instr_q'length; + constant ex5_axu_val_offset : integer := ex5_any_mtcrf_offset + 1; + constant ex5_cr_offset : integer := ex5_axu_val_offset + ex5_axu_val_q'length; + constant ex5_dp_instr_offset : integer := ex5_cr_offset + ex5_cr_q'length; + constant ex5_fu_cr0_offset : integer := ex5_dp_instr_offset + 1; + constant ex5_fu_cr0_bf_offset : integer := ex5_fu_cr0_offset + ex5_fu_cr0_q'length; + constant ex5_fu_cr1_offset : integer := ex5_fu_cr0_bf_offset + ex5_fu_cr0_bf_q'length; + constant ex5_fu_cr1_bf_offset : integer := ex5_fu_cr1_offset + ex5_fu_cr1_q'length; + constant ex5_fu_cr2_offset : integer := ex5_fu_cr1_bf_offset + ex5_fu_cr1_bf_q'length; + constant ex5_fu_cr2_bf_offset : integer := ex5_fu_cr2_offset + ex5_fu_cr2_q'length; + constant ex5_fu_cr3_offset : integer := ex5_fu_cr2_bf_offset + ex5_fu_cr2_bf_q'length; + constant ex5_fu_cr3_bf_offset : integer := ex5_fu_cr3_offset + ex5_fu_cr3_q'length; + constant ex5_fu_cr_noflush_offset : integer := ex5_fu_cr3_bf_offset + ex5_fu_cr3_bf_q'length; + constant ex5_fu_cr_val_offset : integer := ex5_fu_cr_noflush_offset + ex5_fu_cr_noflush_q'length; + constant ex5_is_eratsxr_offset : integer := ex5_fu_cr_val_offset + ex5_fu_cr_val_q'length; + constant ex5_mfdp_cr_status_offset : integer := ex5_is_eratsxr_offset + 1; + constant ex5_mfdp_val_offset : integer := ex5_mfdp_cr_status_offset + 1; + constant ex5_mtdp_cr_status_offset : integer := ex5_mfdp_val_offset + 1; + constant ex5_mtdp_val_offset : integer := ex5_mtdp_cr_status_offset + 1; + constant ex5_val_offset : integer := ex5_mtdp_val_offset + 1; + constant ex5_watch_we_offset : integer := ex5_val_offset + ex5_val_q'length; + constant ex5_wchkall_fld_offset : integer := ex5_watch_we_offset + 1; + constant an_ac_back_inv_offset : integer := ex5_wchkall_fld_offset + ex5_wchkall_fld_q'length; + constant an_ac_back_inv_addr_offset : integer := an_ac_back_inv_offset + 1; + constant an_ac_back_inv_target_bit3_offset : integer := an_ac_back_inv_addr_offset + an_ac_back_inv_addr_q'length; + constant back_inv_val_offset : integer := an_ac_back_inv_target_bit3_offset + 1; + constant cr_barrier_we_offset : integer := back_inv_val_offset + 1; + constant exx_act_offset : integer := cr_barrier_we_offset + cr_barrier_we_q'length; + constant mmu_cr0_eq_offset : integer := exx_act_offset + exx_act_q'length; + constant mmu_cr0_eq_valid_offset : integer := mmu_cr0_eq_offset + mmu_cr0_eq_q'length; + constant stcx_complete_offset : integer := mmu_cr0_eq_valid_offset + mmu_cr0_eq_valid_q'length; + constant stcx_pass_offset : integer := stcx_complete_offset + stcx_complete_q'length; + constant ex1_cr0_byp_pri_dbg_offset : integer := stcx_pass_offset + stcx_pass_q'length; + constant ex1_cr1_byp_pri_dbg_offset : integer := ex1_cr0_byp_pri_dbg_offset + ex1_cr0_byp_pri_dbg_q'length; + constant ex1_crt_byp_pri_dbg_offset : integer := ex1_cr1_byp_pri_dbg_offset + ex1_cr1_byp_pri_dbg_q'length; + constant ex6_val_dbg_offset : integer := ex1_crt_byp_pri_dbg_offset + ex1_crt_byp_pri_dbg_q'length; + constant cr_barrier_offset : integer := ex6_val_dbg_offset + ex6_val_dbg_q'length; + constant cr_offset : integer := cr_barrier_offset + 4*threads; + constant scan_right : integer := cr_offset + 32*threads; + signal siv : std_ulogic_vector(0 to scan_right-1); + signal sov : std_ulogic_vector(0 to scan_right-1); + signal rf1_cr0 : std_ulogic_vector(0 to 3); + signal rf1_cr1 : std_ulogic_vector(0 to 3); + signal rf1_cr0_cmp, rf1_cr1_cmp : std_ulogic_vector(1 to 5); + signal rf1_cr0_byp_pri, rf1_cr1_byp_pri : std_ulogic_vector(1 to 6); + signal rf1_crt_cmp : std_ulogic_vector(1 to 5); + signal rf1_crt_byp_pri : std_ulogic_vector(1 to 6); + signal rf1_cr1_val : std_ulogic_vector(1 to 5); + signal rf1_cr0_val : std_ulogic_vector(1 to 5); + signal rf1_crt_val : std_ulogic_vector(1 to 5); + signal rf1_byp_val : std_ulogic_vector(1 to 5); + signal rf1_axu_byp_val : std_ulogic_vector(4 to 5); + signal rf1_isel_fcn : std_ulogic_vector(0 to 3); + signal ex1_xer_so : std_ulogic; + signal ex2_xer_so : std_ulogic; + signal ex3_xer_so : std_ulogic; + signal ex5_xer_so : std_ulogic; + signal ex1_cr_so : std_ulogic; + signal ex2_cr_recform : std_ulogic_vector(0 to 7); + signal ex3_cr_div : std_ulogic_vector(0 to 7); + signal ex5_cr_mul : std_ulogic_vector(0 to 7); + signal ex5_cr_dp : std_ulogic_vector(0 to 7); + signal ex1_cr : std_ulogic_vector(0 to 7); + signal ex3_cr : std_ulogic_vector(0 to 7); + signal ex2_cr : std_ulogic_vector(0 to 7); + signal ex4_cr : std_ulogic_vector(0 to 7); + signal ex5_cr, ex5_cr_fu : std_ulogic_vector(0 to 7); + signal ex5_val, ex5_axu_val : std_ulogic_vector(0 to threads-1); + signal cr_out : std_ulogic_vector(0 to 32*threads-1); + signal cr_mux : std_ulogic_vector(0 to 31); + signal cr0_out, cr1_out : std_ulogic_vector(0 to 3); + signal crt_out : std_ulogic_vector(0 to 3); + signal ex1_cr_mcrf : std_ulogic_vector(0 to 7); + signal ex1_cr_not_mcrf : std_ulogic_vector(0 to 7); + signal rf1_mfocrf_src : std_ulogic_vector(0 to 2); + signal rf1_cr0_source : std_ulogic_vector(0 to 2); + signal rf1_cr1_source : std_ulogic_vector(0 to 4); + signal icswx_tid : std_ulogic_vector(0 to threads-1); + signal ex5_eratsxr_we : std_ulogic_vector(0 to threads-1); + signal ex5_cr_we : std_ulogic_vector(0 to threads-1); + signal ex5_cr_act : std_ulogic_vector(0 to threads-1); + signal ex1_log_cr_bit : std_ulogic; + signal ex1_log_cr : std_ulogic_vector(0 to 3); + signal ex5_fu_cr : CR_ARY; + signal ex5_fu_cr_val : std_ulogic_vector(0 to threads-1); + signal ex5_cr_watch : std_ulogic_vector(0 to 7); + signal ex5_cr_instr : std_ulogic_vector(0 to 7); + signal ex5_cr_instr_update_b : std_ulogic; + signal ex5_instr_cr_dec : std_ulogic_vector(0 to 7); + signal ex5_fu_cr_valid : std_ulogic; + signal ex5_instr_cr_val : std_ulogic_vector(0 to threads-1); + signal ex5_mtcr_val : std_ulogic_vector(0 to threads-1); + signal ex5_icswx_we : std_ulogic_vector(0 to threads-1); + signal cr_grp0_debug_int : std_ulogic_vector(0 to 87); + signal exx_act : std_ulogic_vector(0 to 4); + signal ex4_axu_act : std_ulogic; + +begin + + exx_act_d <= dec_byp_rf0_act & exx_act_q(0 to 3); + + exx_act(0) <= exx_act_q(0); + exx_act(1) <= exx_act_q(1); + exx_act(2) <= exx_act_q(2); + exx_act(3) <= exx_act_q(3); + exx_act(4) <= exx_act_q(4); + + ex4_axu_act <= '1'; + + ex1_any_mtcrf_d <= (dec_byp_rf1_is_mtcrf or dec_byp_rf1_is_mtocrf); + + ex3_val <= dec_byp_ex3_val and not xu_ex3_flush; + ex4_val <= ex4_val_q and not xu_ex4_flush; + ex5_val <= ex5_val_q and not xu_ex5_flush; + + ex4_axu_val <= fu_xu_ex4_cr_val and not (xu_ex4_flush and not fu_xu_ex4_cr_noflush); + ex5_axu_val <= ex5_axu_val_q and not (xu_ex5_flush and not ex5_fu_cr_noflush_q); + + + ex1_xer_so <= or_reduce(byp_xer_so and ex1_tid) or xer_cr_ex1_xer_ov_in_pipe; + ex2_xer_so <= or_reduce(byp_xer_so and ex2_tid) or xer_cr_ex2_xer_ov_in_pipe; + ex3_xer_so <= or_reduce(byp_xer_so and ex3_tid) or xer_cr_ex3_xer_ov_in_pipe; + ex5_xer_so <= or_reduce(byp_xer_so and ex5_tid) or xer_cr_ex5_xer_ov_in_pipe; + + with ex1_cr_so_update_q select + ex1_cr_so <= (ex1_xer_so or ex1_log_cr(3)) when "01", + ex1_log_cr(3) when "10", + ex1_xer_so when others; + + + ex1_cr_mcrf <= ex1_cr1_q & + ex1_instr_q(6 to 8)& + ex1_cr_we_q; + + ex1_cr_not_mcrf <= ex1_log_cr(0 to 2) & ex1_cr_so & + ex1_instr_q(6 to 8) & + ex1_cr_we_q; + + with ex1_is_mcrf_q select + ex1_cr <= ex1_cr_not_mcrf when '0', + ex1_cr_mcrf when others; + + ex2_cr_recform <= alu_byp_ex2_cr_recform(0 to 2) & (alu_byp_ex2_cr_recform(3) or ex2_xer_so) & + (ex2_instr_q(6 to 8) and (6 to 8 => not ex2_use_crfld0_q)) & + ex2_cr_we_q; + + with ex2_alu_cmp_q select + ex2_cr <= ex2_cr_recform when '1', + ex2_cr_q when others; + + ex3_cr_div <= alu_byp_ex3_cr_div(0 to 2) & (alu_byp_ex3_cr_div(3) or ex3_xer_so) & + (4 to 6 => tidn) & + alu_byp_ex3_cr_div(4); + + + with ex3_div_done_q select + ex3_cr <= ex3_cr_div when '1', + ex3_cr_q when others; + + ex4_cr <= ex4_cr_q; + + ex5_cr_dp <= "00" & + ((ex5_mtdp_cr_status_q and ex5_mtdp_val_q) or + (ex5_mfdp_cr_status_q and ex5_mfdp_val_q)) & + ex5_xer_so & + (4 to 6 => tidn) & + ex5_dp_instr_q; + + ex5_cr_mul <= alu_byp_ex5_cr_mul(0 to 2) & (alu_byp_ex5_cr_mul(3) or ex5_xer_so) & + (4 to 6 => tidn) & + alu_byp_ex5_cr_mul(4); + + + ex5_wchkall_fld_d <= gate(ex4_instr_q(6 to 8),dec_byp_ex4_is_wchkall); + ex5_watch_we_d <= dec_byp_ex4_is_wchkall or lsu_xu_ex4_cr_upd; + + ex5_cr_watch <=("00" & lsu_xu_ex5_cr_rslt & ex5_xer_so) & + ex5_wchkall_fld_q & + ex5_watch_we_q; + + ex5_fu_cr(0) <= ex5_fu_cr0_q & ex5_fu_cr0_bf_q & ex5_fu_cr_val_q(0); + ex5_fu_cr(1) <= ex5_fu_cr1_q & ex5_fu_cr1_bf_q & ex5_fu_cr_val_q(1); + ex5_fu_cr(2) <= ex5_fu_cr2_q & ex5_fu_cr2_bf_q & ex5_fu_cr_val_q(2); + ex5_fu_cr(3) <= ex5_fu_cr3_q & ex5_fu_cr3_bf_q & ex5_fu_cr_val_q(3); + + ex5_fu_cr_valid <= or_reduce(rf1_tid and ex5_fu_cr_val_q); + ex5_cr_instr_update_b <= not(ex5_cr_dp(7) or ex5_cr_mul(7) or ex5_cr_watch(7)); + + ex5_cr_fu <= gate(ex5_fu_cr(0), rf1_tid(0)) or + gate(ex5_fu_cr(1), rf1_tid(1)) or + gate(ex5_fu_cr(2), rf1_tid(2)) or + gate(ex5_fu_cr(3), rf1_tid(3)); + + + ex5_cr_instr <= gate(ex5_cr_dp, ex5_cr_dp(7) ) or + gate(ex5_cr_mul, ex5_cr_mul(7) ) or + gate(ex5_cr_watch, ex5_cr_watch(7) ) or + gate(ex5_cr_q, ex5_cr_instr_update_b); + + ex5_cr <= gate(ex5_cr_instr, not(ex5_fu_cr_valid)) or + gate(ex5_cr_fu, ex5_fu_cr_valid ); + + with rf1_instr(12 to 19) select + rf1_mfocrf_src <= "000" when "10000000", + "001" when "01000000", + "010" when "00100000", + "011" when "00010000", + "100" when "00001000", + "101" when "00000100", + "110" when "00000010", + "111" when "00000001", + "000" when others; + + with rf1_is_mfocrf_q select + rf1_cr0_source <= rf1_mfocrf_src when '1', + rf1_instr(16 to 18) when others; + + with dec_byp_rf1_is_isel select + rf1_cr1_source <= rf1_instr(21 to 25) when '1', + rf1_instr(11 to 15) when others; + + rf1_axu_byp_val(4) <= or_reduce(rf1_tid and ex4_val_q); + rf1_axu_byp_val(5) <= or_reduce(rf1_tid and (ex5_val_q or ex5_fu_cr_val_q)); + + rf1_byp_val(1) <= ex1_cr(7) and dec_byp_rf1_byp_val(1); + rf1_byp_val(2) <= ex2_cr(7) and dec_byp_rf1_byp_val(2); + rf1_byp_val(3) <= ex3_cr(7) and dec_byp_rf1_byp_val(3); + rf1_byp_val(4) <= ex4_cr(7) and rf1_axu_byp_val(4); + rf1_byp_val(5) <= ex5_cr(7) and rf1_axu_byp_val(5); + + rf1_cr0_cmp(1) <= '1' when rf1_cr0_source = ex1_cr(4 to 6) else '0'; + rf1_cr0_cmp(2) <= '1' when rf1_cr0_source = ex2_cr(4 to 6) else '0'; + rf1_cr0_cmp(3) <= '1' when rf1_cr0_source = ex3_cr(4 to 6) else '0'; + rf1_cr0_cmp(4) <= '1' when rf1_cr0_source = ex4_cr(4 to 6) else '0'; + rf1_cr0_cmp(5) <= '1' when rf1_cr0_source = ex5_cr(4 to 6) else '0'; + + rf1_cr0_val <= rf1_cr0_cmp and rf1_byp_val; + + rf1_cr0_byp_pri(1) <= rf1_cr0_val(1); + rf1_cr0_byp_pri(2) <= not rf1_cr0_val(1) and rf1_cr0_val(2); + rf1_cr0_byp_pri(3) <= not or_reduce(rf1_cr0_val(1 to 2)) and rf1_cr0_val(3); + rf1_cr0_byp_pri(4) <= not or_reduce(rf1_cr0_val(1 to 3)) and rf1_cr0_val(4); + rf1_cr0_byp_pri(5) <= not or_reduce(rf1_cr0_val(1 to 4)) and rf1_cr0_val(5); + rf1_cr0_byp_pri(6) <= not or_reduce(rf1_cr0_val(1 to 5)); + + rf1_cr1_cmp(1) <= '1' when rf1_cr1_source(0 to 2) = ex1_cr(4 to 6) else '0'; + rf1_cr1_cmp(2) <= '1' when rf1_cr1_source(0 to 2) = ex2_cr(4 to 6) else '0'; + rf1_cr1_cmp(3) <= '1' when rf1_cr1_source(0 to 2) = ex3_cr(4 to 6) else '0'; + rf1_cr1_cmp(4) <= '1' when rf1_cr1_source(0 to 2) = ex4_cr(4 to 6) else '0'; + rf1_cr1_cmp(5) <= '1' when rf1_cr1_source(0 to 2) = ex5_cr(4 to 6) else '0'; + + rf1_cr1_val <= rf1_cr1_cmp and rf1_byp_val; + + rf1_cr1_byp_pri(1) <= rf1_cr1_val(1); + rf1_cr1_byp_pri(2) <= not rf1_cr1_val(1) and rf1_cr1_val(2); + rf1_cr1_byp_pri(3) <= not or_reduce(rf1_cr1_val(1 to 2)) and rf1_cr1_val(3); + rf1_cr1_byp_pri(4) <= not or_reduce(rf1_cr1_val(1 to 3)) and rf1_cr1_val(4); + rf1_cr1_byp_pri(5) <= not or_reduce(rf1_cr1_val(1 to 4)) and rf1_cr1_val(5); + rf1_cr1_byp_pri(6) <= not or_reduce(rf1_cr1_val(1 to 5)); + + rf1_crt_cmp(1) <= '1' when rf1_instr(6 to 8) = ex1_cr(4 to 6) else '0'; + rf1_crt_cmp(2) <= '1' when rf1_instr(6 to 8) = ex2_cr(4 to 6) else '0'; + rf1_crt_cmp(3) <= '1' when rf1_instr(6 to 8) = ex3_cr(4 to 6) else '0'; + rf1_crt_cmp(4) <= '1' when rf1_instr(6 to 8) = ex4_cr(4 to 6) else '0'; + rf1_crt_cmp(5) <= '1' when rf1_instr(6 to 8) = ex5_cr(4 to 6) else '0'; + + rf1_crt_val <= rf1_crt_cmp and rf1_byp_val; + + rf1_crt_byp_pri(1) <= rf1_crt_val(1); + rf1_crt_byp_pri(2) <= not rf1_crt_val(1) and rf1_crt_val(2); + rf1_crt_byp_pri(3) <= not or_reduce(rf1_crt_val(1 to 2)) and rf1_crt_val(3); + rf1_crt_byp_pri(4) <= not or_reduce(rf1_crt_val(1 to 3)) and rf1_crt_val(4); + rf1_crt_byp_pri(5) <= not or_reduce(rf1_crt_val(1 to 4)) and rf1_crt_val(5); + rf1_crt_byp_pri(6) <= not or_reduce(rf1_crt_val(1 to 5)); + + + rf1_cr0 <= gate(ex1_cr(0 to 3), rf1_cr0_byp_pri(1)) or + gate(ex2_cr(0 to 3), rf1_cr0_byp_pri(2)) or + gate(ex3_cr(0 to 3), rf1_cr0_byp_pri(3)) or + gate(ex4_cr(0 to 3), rf1_cr0_byp_pri(4)) or + gate(ex5_cr(0 to 3), rf1_cr0_byp_pri(5)) or + gate(cr0_out(0 to 3), rf1_cr0_byp_pri(6)); + + with rf1_instr(19 to 20) select + rf1_cr0_bit <= rf1_cr0(0) when "00", + rf1_cr0(1) when "01", + rf1_cr0(2) when "10", + rf1_cr0(3) when others; + + rf1_cr1 <= gate(ex1_cr(0 to 3), rf1_cr1_byp_pri(1)) or + gate(ex2_cr(0 to 3), rf1_cr1_byp_pri(2)) or + gate(ex3_cr(0 to 3), rf1_cr1_byp_pri(3)) or + gate(ex4_cr(0 to 3), rf1_cr1_byp_pri(4)) or + gate(ex5_cr(0 to 3), rf1_cr1_byp_pri(5)) or + gate(cr1_out(0 to 3), rf1_cr1_byp_pri(6)); + + with rf1_cr1_source(3 to 4) select + rf1_cr1_bit_i <= rf1_cr1(0) when "00", + rf1_cr1(1) when "01", + rf1_cr1(2) when "10", + rf1_cr1(3) when others; + + rf1_crt <= gate(ex1_cr(0 to 3), rf1_crt_byp_pri(1)) or + gate(ex2_cr(0 to 3), rf1_crt_byp_pri(2)) or + gate(ex3_cr(0 to 3), rf1_crt_byp_pri(3)) or + gate(ex4_cr(0 to 3), rf1_crt_byp_pri(4)) or + gate(ex5_cr(0 to 3), rf1_crt_byp_pri(5)) or + gate(crt_out(0 to 3), rf1_crt_byp_pri(6)); + + rf1_isel_fcn <= '0' & not(rf1_cr1_bit_i) & rf1_cr1_bit_i & '1'; + + byp_alu_rf1_isel_fcn <= gate(rf1_isel_fcn,dec_byp_rf1_is_isel); + + with rf1_instr(9 to 10) select + rf1_crt_mask <= "1000" when "00", + "0100" when "01", + "0010" when "10", + "0001" when others; + + ex1_log_cr_bit <= + (ex1_instr_2_q(25) and not ex1_cr1_bit_q and not ex1_cr0_bit_q) or + (ex1_instr_2_q(24) and not ex1_cr1_bit_q and ex1_cr0_bit_q) or + (ex1_instr_2_q(23) and ex1_cr1_bit_q and not ex1_cr0_bit_q) or + (ex1_instr_2_q(22) and ex1_cr1_bit_q and ex1_cr0_bit_q); + + ex1_log_cr(0) <= (ex1_crt_q(0) and not ex1_crt_mask_q(0)) or (ex1_log_cr_bit and ex1_crt_mask_q(0)); + ex1_log_cr(1) <= (ex1_crt_q(1) and not ex1_crt_mask_q(1)) or (ex1_log_cr_bit and ex1_crt_mask_q(1)); + ex1_log_cr(2) <= (ex1_crt_q(2) and not ex1_crt_mask_q(2)) or (ex1_log_cr_bit and ex1_crt_mask_q(2)); + ex1_log_cr(3) <= (ex1_crt_q(3) and not ex1_crt_mask_q(3)) or (ex1_log_cr_bit and ex1_crt_mask_q(3)); + + byp_cpl_ex1_cr_bit <= ex1_cr1_bit_q; + + + with ex5_cr_instr(4 to 6) select + ex5_instr_cr_dec <= "10000000" when "000", + "01000000" when "001", + "00100000" when "010", + "00010000" when "011", + "00001000" when "100", + "00000100" when "101", + "00000010" when "110", + "00000001" when others; + + + with an_ac_back_inv_addr_q(62 to 63) select + icswx_tid <= "1000" when "00", + "0100" when "01", + "0010" when "10", + "0001" when others; + + back_inv_val_d <= an_ac_back_inv_q and an_ac_back_inv_target_bit3_q; + ex5_icswx_we <= gate(icswx_tid, back_inv_val_q); + + cr_barrier_we_d <= stcx_complete_q or mmu_cr0_eq_valid_q or ex5_icswx_we; + + xuq_byp_cr_gen : for t in 0 to threads-1 generate + + signal cr_q, cr_d : std_ulogic_vector(32 to 63); + signal cr_barrier_q, cr_barrier_d : std_ulogic_vector(32 to 35); + + signal ex5_fu_cr_dec : std_ulogic_vector(0 to 7); + signal ex5_fu_we : std_ulogic_vector(0 to 7); + signal ex5_instr_we : std_ulogic_vector(0 to 7); + signal ex5_mtcr_we : std_ulogic_vector(0 to 7); + + begin + + with ex5_fu_cr(t)(4 to 6) select + ex5_fu_cr_dec <= "10000000" when "000", + "01000000" when "001", + "00100000" when "010", + "00010000" when "011", + "00001000" when "100", + "00000100" when "101", + "00000010" when "110", + "00000001" when others; + + ex5_fu_cr_val(t) <= ex5_fu_cr(t)(7) and ex5_axu_val(t); + ex5_fu_we <= gate(ex5_fu_cr_dec,ex5_fu_cr_val(t)); + + ex5_instr_cr_val(t) <= ex5_cr_instr(7) and ex5_val(t); + ex5_instr_we <= gate(ex5_instr_cr_dec,ex5_instr_cr_val(t)); + + ex5_mtcr_val(t) <= ex5_any_mtcrf_q and ex5_val(t); + ex5_mtcr_we <= gate(dec_cr_ex5_instr(12 to 19),ex5_mtcr_val(t)); + + ex5_eratsxr_we(t) <= ex5_is_eratsxr_q and ex5_val(t); + + + with s3'(stcx_complete_q(t) & mmu_cr0_eq_valid_q(t) & ex5_icswx_we(t)) select + cr_barrier_d(32 to 35) <= "00" & stcx_pass_q(t) & byp_xer_so(t) when "100", + "00" & mmu_cr0_eq_q(t) & tidn when "010", + an_ac_back_inv_addr_q(58 to 60) & tidn when others; + + + with s5'(ex5_eratsxr_we(t) & ex5_mtcr_we(0) & ex5_instr_we(0) & ex5_fu_we(0) & cr_barrier_we_q(t)) select + cr_d(32 to 35) <= "00" & byp_ex5_tlb_rt(51) & tidn when "10000", + byp_ex5_mtcrxer(32 to 35) when "01000", + ex5_cr_instr(0 to 3) when "00100", + ex5_fu_cr(t)(0 to 3) when "00010", + cr_barrier_q when "00001", + cr_q(32 to 35) when others; + + xuq_byp_cr_field_gen : for f in 1 to 7 generate + + with s3'(ex5_mtcr_we(f) & ex5_instr_we(f) & ex5_fu_we(f)) select + cr_d(32+f*4 to 35+f*4) <= byp_ex5_mtcrxer(32+f*4 to 35+f*4) when "100", + ex5_cr_instr(0 to 3) when "010", + ex5_fu_cr(t)(0 to 3) when "001", + cr_q(32+f*4 to 35+f*4) when others; + + end generate; + + ex5_cr_act(t) <= ex5_val_q(t) or ex5_axu_val_q(t) or cr_barrier_we_q(t); + + + ex5_cr_we(t) <= ex5_eratsxr_we(t) or + cr_barrier_we_q(t) or + or_reduce(ex5_mtcr_we or ex5_instr_we or ex5_fu_we) or + (ex5_val(t) and ex5_any_mtcrf_q); + + cr_out(t*32 to t*32+31) <= cr_q; + + byp_perf_tx_events(0+3*t) <= stcx_complete_q(t) and not stcx_pass_q(t); + byp_perf_tx_events(1+3*t) <= ex5_icswx_we(t) and not an_ac_back_inv_addr_q(59); + byp_perf_tx_events(2+3*t) <= ex5_icswx_we(t) and an_ac_back_inv_addr_q(59); + + + cr_barrier_latch : tri_rlmreg_p + generic map (width => cr_barrier_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(cr_barrier_offset + cr_barrier_q'length*t to cr_barrier_offset + cr_barrier_q'length*(t+1)-1), + scout => sov(cr_barrier_offset + cr_barrier_q'length*t to cr_barrier_offset + cr_barrier_q'length*(t+1)-1), + din => cr_barrier_d, + dout => cr_barrier_q); + cr_latch : tri_rlmreg_p + generic map (width => cr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => ex5_cr_act(t), + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(cr_offset + cr_q'length*t to cr_offset + cr_q'length*(t+1)-1), + scout => sov(cr_offset + cr_q'length*t to cr_offset + cr_q'length*(t+1)-1), + din => cr_d, + dout => cr_q); + end generate; + + xuq_byp_cr_mfocr : for t in 0 to 7 generate + ex1_mfocrf_rt(t*4+32 to t*4+35) <= gate(ex1_cr0_q,ex1_instr_q(t+12)); + end generate; + xuq_byp_cr_mfocr_z : if regsize > 32 generate + ex1_mfocrf_rt(0 to 31) <= (others=>'0'); + end generate; + + ex5_cr_rt <= mux_t(cr_out,ex5_tid); + + cr_mux <= mux_t(cr_out,rf1_tid); + + with rf1_cr0_source select + cr0_out <= cr_mux(0 to 3) when "000", + cr_mux(4 to 7) when "001", + cr_mux(8 to 11) when "010", + cr_mux(12 to 15) when "011", + cr_mux(16 to 19) when "100", + cr_mux(20 to 23) when "101", + cr_mux(24 to 27) when "110", + cr_mux(28 to 31) when others; + + with rf1_cr1_source(0 to 2) select + cr1_out <= cr_mux(0 to 3) when "000", + cr_mux(4 to 7) when "001", + cr_mux(8 to 11) when "010", + cr_mux(12 to 15) when "011", + cr_mux(16 to 19) when "100", + cr_mux(20 to 23) when "101", + cr_mux(24 to 27) when "110", + cr_mux(28 to 31) when others; + + with rf1_instr(6 to 8) select + crt_out <= cr_mux(0 to 3) when "000", + cr_mux(4 to 7) when "001", + cr_mux(8 to 11) when "010", + cr_mux(12 to 15) when "011", + cr_mux(16 to 19) when "100", + cr_mux(20 to 23) when "101", + cr_mux(24 to 27) when "110", + cr_mux(28 to 31) when others; + + + mark_unused(ex5_cr_we); + mark_unused(ex1_instr_q(9 to 11)); + mark_unused(an_ac_back_inv_addr_q(61)); + + cr_grp0_debug <= cr_grp0_debug_int; + cr_grp0_debug_int <= ex6_val_dbg_q & + ex5_fu_cr_val_q & + ex5_fu_cr_noflush_q & + ex1_cr_so_update_q(0 to 1) & + ex1_is_mcrf_q & + ex2_alu_cmp_q & + ex3_div_done_q & + ex5_watch_we_q & + ex5_dp_instr_q & + alu_byp_ex5_cr_mul(4) & + ex5_any_mtcrf_q & + ex5_is_eratsxr_q & + stcx_complete_q(0 to 3) & + mmu_cr0_eq_valid_q(0 to 3) & + ex1_cr1_bit_q & + an_ac_back_inv_q & + an_ac_back_inv_target_bit3_q & + an_ac_back_inv_addr_q(62 to 63) & + ex5_fu_cr(0)(4 to 6) & + ex5_fu_cr(1)(4 to 6) & + ex5_fu_cr(2)(4 to 6) & + ex5_fu_cr(3)(4 to 6) & + ex5_cr_instr(4 to 6) & + dec_cr_ex5_instr(12 to 19) & + ex1_cr0_q(0 to 3) & + ex1_cr1_q(0 to 3) & + ex1_crt_q(0 to 3) & + ex1_cr0_byp_pri_dbg_q(1 to 6) & + ex1_cr1_byp_pri_dbg_q(1 to 6) & + ex1_crt_byp_pri_dbg_q(1 to 6); + + cr_grp1_debug <= cr_grp0_debug_int(0 to 71) & + ex3_cr_q(0 to 7) & + ex5_cr_q(0 to 7); + +rf1_is_mfocrf_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => fxa_fxb_rf0_is_mfocrf , + dout(0) => rf1_is_mfocrf_q); +ex1_alu_cmp_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_alu_cmp_offset), + scout => sov(ex1_alu_cmp_offset), + din => dec_byp_rf1_alu_cmp , + dout => ex1_alu_cmp_q); +ex1_any_mtcrf_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_any_mtcrf_offset), + scout => sov(ex1_any_mtcrf_offset), + din => ex1_any_mtcrf_d, + dout => ex1_any_mtcrf_q); +ex1_cr0_latch : tri_rlmreg_p + generic map (width => ex1_cr0_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_cr0_offset to ex1_cr0_offset + ex1_cr0_q'length-1), + scout => sov(ex1_cr0_offset to ex1_cr0_offset + ex1_cr0_q'length-1), + din => rf1_cr0 , + dout => ex1_cr0_q); +ex1_cr0_bit_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_cr0_bit_offset), + scout => sov(ex1_cr0_bit_offset), + din => rf1_cr0_bit, + dout => ex1_cr0_bit_q); +ex1_cr1_latch : tri_rlmreg_p + generic map (width => ex1_cr1_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_cr1_offset to ex1_cr1_offset + ex1_cr1_q'length-1), + scout => sov(ex1_cr1_offset to ex1_cr1_offset + ex1_cr1_q'length-1), + din => rf1_cr1 , + dout => ex1_cr1_q); +ex1_cr1_bit_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_cr1_bit_offset), + scout => sov(ex1_cr1_bit_offset), + din => rf1_cr1_bit_i, + dout => ex1_cr1_bit_q); +ex1_cr_so_update_latch : tri_rlmreg_p + generic map (width => ex1_cr_so_update_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_cr_so_update_offset to ex1_cr_so_update_offset + ex1_cr_so_update_q'length-1), + scout => sov(ex1_cr_so_update_offset to ex1_cr_so_update_offset + ex1_cr_so_update_q'length-1), + din => dec_byp_rf1_cr_so_update , + dout => ex1_cr_so_update_q); +ex1_cr_we_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_cr_we_offset), + scout => sov(ex1_cr_we_offset), + din => dec_byp_rf1_cr_we , + dout => ex1_cr_we_q); +ex1_crt_latch : tri_rlmreg_p + generic map (width => ex1_crt_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_crt_offset to ex1_crt_offset + ex1_crt_q'length-1), + scout => sov(ex1_crt_offset to ex1_crt_offset + ex1_crt_q'length-1), + din => rf1_crt, + dout => ex1_crt_q); +ex1_crt_mask_latch : tri_rlmreg_p + generic map (width => ex1_crt_mask_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_crt_mask_offset to ex1_crt_mask_offset + ex1_crt_mask_q'length-1), + scout => sov(ex1_crt_mask_offset to ex1_crt_mask_offset + ex1_crt_mask_q'length-1), + din => rf1_crt_mask, + dout => ex1_crt_mask_q); +ex1_instr_latch : tri_rlmreg_p + generic map (width => ex1_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_instr_offset to ex1_instr_offset + ex1_instr_q'length-1), + scout => sov(ex1_instr_offset to ex1_instr_offset + ex1_instr_q'length-1), + din => rf1_instr(6 to 19), + dout => ex1_instr_q); +ex1_instr_2_latch : tri_rlmreg_p + generic map (width => ex1_instr_2_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_instr_2_offset to ex1_instr_2_offset + ex1_instr_2_q'length-1), + scout => sov(ex1_instr_2_offset to ex1_instr_2_offset + ex1_instr_2_q'length-1), + din => rf1_instr(22 to 25), + dout => ex1_instr_2_q); +ex1_is_mcrf_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_mcrf_offset), + scout => sov(ex1_is_mcrf_offset), + din => dec_byp_rf1_is_mcrf , + dout => ex1_is_mcrf_q); +ex1_use_crfld0_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_use_crfld0_offset), + scout => sov(ex1_use_crfld0_offset), + din => dec_byp_rf1_use_crfld0 , + dout => ex1_use_crfld0_q); +ex2_alu_cmp_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_alu_cmp_q , + dout(0) => ex2_alu_cmp_q); +ex2_any_mtcrf_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_any_mtcrf_q , + dout(0) => ex2_any_mtcrf_q); +ex2_cr_latch : tri_regk + generic map (width => ex2_cr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex1_cr , + dout => ex2_cr_q); +ex2_cr_we_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_cr_we_q , + dout(0) => ex2_cr_we_q); +ex2_instr_latch : tri_regk + generic map (width => ex2_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex1_instr_q(6 to 8), + dout => ex2_instr_q); +ex2_use_crfld0_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_use_crfld0_q , + dout(0) => ex2_use_crfld0_q); +ex3_any_mtcrf_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_any_mtcrf_offset), + scout => sov(ex3_any_mtcrf_offset), + din => ex2_any_mtcrf_q , + dout => ex3_any_mtcrf_q); +ex3_cr_latch : tri_rlmreg_p + generic map (width => ex3_cr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_cr_offset to ex3_cr_offset + ex3_cr_q'length-1), + scout => sov(ex3_cr_offset to ex3_cr_offset + ex3_cr_q'length-1), + din => ex2_cr , + dout => ex3_cr_q); +ex3_div_done_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_div_done_offset), + scout => sov(ex3_div_done_offset), + din => alu_ex2_div_done , + dout => ex3_div_done_q); +ex3_instr_latch : tri_rlmreg_p + generic map (width => ex3_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_instr_offset to ex3_instr_offset + ex3_instr_q'length-1), + scout => sov(ex3_instr_offset to ex3_instr_offset + ex3_instr_q'length-1), + din => ex2_instr_q , + dout => ex3_instr_q); +ex4_any_mtcrf_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_any_mtcrf_q , + dout(0) => ex4_any_mtcrf_q); +ex4_cr_latch : tri_regk + generic map (width => ex4_cr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex3_cr , + dout => ex4_cr_q); +ex4_instr_latch : tri_regk + generic map (width => ex4_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex3_instr_q , + dout => ex4_instr_q); +ex4_val_latch : tri_regk + generic map (width => ex4_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex3_val, + dout => ex4_val_q); +ex5_any_mtcrf_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_any_mtcrf_offset), + scout => sov(ex5_any_mtcrf_offset), + din => ex4_any_mtcrf_q , + dout => ex5_any_mtcrf_q); +ex5_axu_val_latch : tri_rlmreg_p + generic map (width => ex5_axu_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_axu_val_offset to ex5_axu_val_offset + ex5_axu_val_q'length-1), + scout => sov(ex5_axu_val_offset to ex5_axu_val_offset + ex5_axu_val_q'length-1), + din => ex4_axu_val, + dout => ex5_axu_val_q); +ex5_cr_latch : tri_rlmreg_p + generic map (width => ex5_cr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_cr_offset to ex5_cr_offset + ex5_cr_q'length-1), + scout => sov(ex5_cr_offset to ex5_cr_offset + ex5_cr_q'length-1), + din => ex4_cr , + dout => ex5_cr_q); +ex5_dp_instr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_dp_instr_offset), + scout => sov(ex5_dp_instr_offset), + din => dec_byp_ex4_dp_instr , + dout => ex5_dp_instr_q); +ex5_fu_cr0_latch : tri_rlmreg_p + generic map (width => ex5_fu_cr0_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_axu_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_fu_cr0_offset to ex5_fu_cr0_offset + ex5_fu_cr0_q'length-1), + scout => sov(ex5_fu_cr0_offset to ex5_fu_cr0_offset + ex5_fu_cr0_q'length-1), + din => fu_xu_ex4_cr0 , + dout => ex5_fu_cr0_q); +ex5_fu_cr0_bf_latch : tri_rlmreg_p + generic map (width => ex5_fu_cr0_bf_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_axu_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_fu_cr0_bf_offset to ex5_fu_cr0_bf_offset + ex5_fu_cr0_bf_q'length-1), + scout => sov(ex5_fu_cr0_bf_offset to ex5_fu_cr0_bf_offset + ex5_fu_cr0_bf_q'length-1), + din => fu_xu_ex4_cr0_bf , + dout => ex5_fu_cr0_bf_q); +ex5_fu_cr1_latch : tri_rlmreg_p + generic map (width => ex5_fu_cr1_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_axu_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_fu_cr1_offset to ex5_fu_cr1_offset + ex5_fu_cr1_q'length-1), + scout => sov(ex5_fu_cr1_offset to ex5_fu_cr1_offset + ex5_fu_cr1_q'length-1), + din => fu_xu_ex4_cr1 , + dout => ex5_fu_cr1_q); +ex5_fu_cr1_bf_latch : tri_rlmreg_p + generic map (width => ex5_fu_cr1_bf_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_axu_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_fu_cr1_bf_offset to ex5_fu_cr1_bf_offset + ex5_fu_cr1_bf_q'length-1), + scout => sov(ex5_fu_cr1_bf_offset to ex5_fu_cr1_bf_offset + ex5_fu_cr1_bf_q'length-1), + din => fu_xu_ex4_cr1_bf , + dout => ex5_fu_cr1_bf_q); +ex5_fu_cr2_latch : tri_rlmreg_p + generic map (width => ex5_fu_cr2_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_axu_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_fu_cr2_offset to ex5_fu_cr2_offset + ex5_fu_cr2_q'length-1), + scout => sov(ex5_fu_cr2_offset to ex5_fu_cr2_offset + ex5_fu_cr2_q'length-1), + din => fu_xu_ex4_cr2 , + dout => ex5_fu_cr2_q); +ex5_fu_cr2_bf_latch : tri_rlmreg_p + generic map (width => ex5_fu_cr2_bf_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_axu_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_fu_cr2_bf_offset to ex5_fu_cr2_bf_offset + ex5_fu_cr2_bf_q'length-1), + scout => sov(ex5_fu_cr2_bf_offset to ex5_fu_cr2_bf_offset + ex5_fu_cr2_bf_q'length-1), + din => fu_xu_ex4_cr2_bf , + dout => ex5_fu_cr2_bf_q); +ex5_fu_cr3_latch : tri_rlmreg_p + generic map (width => ex5_fu_cr3_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_axu_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_fu_cr3_offset to ex5_fu_cr3_offset + ex5_fu_cr3_q'length-1), + scout => sov(ex5_fu_cr3_offset to ex5_fu_cr3_offset + ex5_fu_cr3_q'length-1), + din => fu_xu_ex4_cr3 , + dout => ex5_fu_cr3_q); +ex5_fu_cr3_bf_latch : tri_rlmreg_p + generic map (width => ex5_fu_cr3_bf_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_axu_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_fu_cr3_bf_offset to ex5_fu_cr3_bf_offset + ex5_fu_cr3_bf_q'length-1), + scout => sov(ex5_fu_cr3_bf_offset to ex5_fu_cr3_bf_offset + ex5_fu_cr3_bf_q'length-1), + din => fu_xu_ex4_cr3_bf , + dout => ex5_fu_cr3_bf_q); +ex5_fu_cr_noflush_latch : tri_rlmreg_p + generic map (width => ex5_fu_cr_noflush_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_fu_cr_noflush_offset to ex5_fu_cr_noflush_offset + ex5_fu_cr_noflush_q'length-1), + scout => sov(ex5_fu_cr_noflush_offset to ex5_fu_cr_noflush_offset + ex5_fu_cr_noflush_q'length-1), + din => fu_xu_ex4_cr_noflush , + dout => ex5_fu_cr_noflush_q); +ex5_fu_cr_val_latch : tri_rlmreg_p + generic map (width => ex5_fu_cr_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_fu_cr_val_offset to ex5_fu_cr_val_offset + ex5_fu_cr_val_q'length-1), + scout => sov(ex5_fu_cr_val_offset to ex5_fu_cr_val_offset + ex5_fu_cr_val_q'length-1), + din => fu_xu_ex4_cr_val , + dout => ex5_fu_cr_val_q); +ex5_is_eratsxr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_is_eratsxr_offset), + scout => sov(ex5_is_eratsxr_offset), + din => dec_byp_ex4_is_eratsxr , + dout => ex5_is_eratsxr_q); +ex5_mfdp_cr_status_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_mfdp_cr_status_offset), + scout => sov(ex5_mfdp_cr_status_offset), + din => lsu_xu_ex4_mfdp_cr_status , + dout => ex5_mfdp_cr_status_q); +ex5_mfdp_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_mfdp_val_offset), + scout => sov(ex5_mfdp_val_offset), + din => dec_byp_ex4_mfdp_val , + dout => ex5_mfdp_val_q); +ex5_mtdp_cr_status_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_mtdp_cr_status_offset), + scout => sov(ex5_mtdp_cr_status_offset), + din => lsu_xu_ex4_mtdp_cr_status , + dout => ex5_mtdp_cr_status_q); +ex5_mtdp_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_mtdp_val_offset), + scout => sov(ex5_mtdp_val_offset), + din => dec_byp_ex4_mtdp_val , + dout => ex5_mtdp_val_q); +ex5_val_latch : tri_rlmreg_p + generic map (width => ex5_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_val_offset to ex5_val_offset + ex5_val_q'length-1), + scout => sov(ex5_val_offset to ex5_val_offset + ex5_val_q'length-1), + din => ex4_val, + dout => ex5_val_q); +ex5_watch_we_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_watch_we_offset), + scout => sov(ex5_watch_we_offset), + din => ex5_watch_we_d, + dout => ex5_watch_we_q); +ex5_wchkall_fld_latch : tri_rlmreg_p + generic map (width => ex5_wchkall_fld_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_wchkall_fld_offset to ex5_wchkall_fld_offset + ex5_wchkall_fld_q'length-1), + scout => sov(ex5_wchkall_fld_offset to ex5_wchkall_fld_offset + ex5_wchkall_fld_q'length-1), + din => ex5_wchkall_fld_d, + dout => ex5_wchkall_fld_q); +an_ac_back_inv_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(an_ac_back_inv_offset), + scout => sov(an_ac_back_inv_offset), + din => an_ac_back_inv , + dout => an_ac_back_inv_q); +an_ac_back_inv_addr_latch : tri_rlmreg_p + generic map (width => an_ac_back_inv_addr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(an_ac_back_inv_addr_offset to an_ac_back_inv_addr_offset + an_ac_back_inv_addr_q'length-1), + scout => sov(an_ac_back_inv_addr_offset to an_ac_back_inv_addr_offset + an_ac_back_inv_addr_q'length-1), + din => an_ac_back_inv_addr , + dout => an_ac_back_inv_addr_q); +an_ac_back_inv_target_bit3_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(an_ac_back_inv_target_bit3_offset), + scout => sov(an_ac_back_inv_target_bit3_offset), + din => an_ac_back_inv_target_bit3 , + dout => an_ac_back_inv_target_bit3_q); +back_inv_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(back_inv_val_offset), + scout => sov(back_inv_val_offset), + din => back_inv_val_d, + dout => back_inv_val_q); +cr_barrier_we_latch : tri_rlmreg_p + generic map (width => cr_barrier_we_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(cr_barrier_we_offset to cr_barrier_we_offset + cr_barrier_we_q'length-1), + scout => sov(cr_barrier_we_offset to cr_barrier_we_offset + cr_barrier_we_q'length-1), + din => cr_barrier_we_d, + dout => cr_barrier_we_q); +exx_act_latch : tri_rlmreg_p + generic map (width => exx_act_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(exx_act_offset to exx_act_offset + exx_act_q'length-1), + scout => sov(exx_act_offset to exx_act_offset + exx_act_q'length-1), + din => exx_act_d, + dout => exx_act_q); +mmu_cr0_eq_latch : tri_rlmreg_p + generic map (width => mmu_cr0_eq_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(mmu_cr0_eq_offset to mmu_cr0_eq_offset + mmu_cr0_eq_q'length-1), + scout => sov(mmu_cr0_eq_offset to mmu_cr0_eq_offset + mmu_cr0_eq_q'length-1), + din => mm_xu_cr0_eq , + dout => mmu_cr0_eq_q); +mmu_cr0_eq_valid_latch : tri_rlmreg_p + generic map (width => mmu_cr0_eq_valid_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(mmu_cr0_eq_valid_offset to mmu_cr0_eq_valid_offset + mmu_cr0_eq_valid_q'length-1), + scout => sov(mmu_cr0_eq_valid_offset to mmu_cr0_eq_valid_offset + mmu_cr0_eq_valid_q'length-1), + din => mm_xu_cr0_eq_valid , + dout => mmu_cr0_eq_valid_q); +stcx_complete_latch : tri_rlmreg_p + generic map (width => stcx_complete_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(stcx_complete_offset to stcx_complete_offset + stcx_complete_q'length-1), + scout => sov(stcx_complete_offset to stcx_complete_offset + stcx_complete_q'length-1), + din => an_ac_stcx_complete , + dout => stcx_complete_q); +stcx_pass_latch : tri_rlmreg_p + generic map (width => stcx_pass_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(stcx_pass_offset to stcx_pass_offset + stcx_pass_q'length-1), + scout => sov(stcx_pass_offset to stcx_pass_offset + stcx_pass_q'length-1), + din => an_ac_stcx_pass , + dout => stcx_pass_q); +ex1_cr0_byp_pri_dbg_latch : tri_rlmreg_p + generic map (width => ex1_cr0_byp_pri_dbg_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_cr0_byp_pri_dbg_offset to ex1_cr0_byp_pri_dbg_offset + ex1_cr0_byp_pri_dbg_q'length-1), + scout => sov(ex1_cr0_byp_pri_dbg_offset to ex1_cr0_byp_pri_dbg_offset + ex1_cr0_byp_pri_dbg_q'length-1), + din => rf1_cr0_byp_pri , + dout => ex1_cr0_byp_pri_dbg_q); +ex1_cr1_byp_pri_dbg_latch : tri_rlmreg_p + generic map (width => ex1_cr1_byp_pri_dbg_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_cr1_byp_pri_dbg_offset to ex1_cr1_byp_pri_dbg_offset + ex1_cr1_byp_pri_dbg_q'length-1), + scout => sov(ex1_cr1_byp_pri_dbg_offset to ex1_cr1_byp_pri_dbg_offset + ex1_cr1_byp_pri_dbg_q'length-1), + din => rf1_cr1_byp_pri , + dout => ex1_cr1_byp_pri_dbg_q); +ex1_crt_byp_pri_dbg_latch : tri_rlmreg_p + generic map (width => ex1_crt_byp_pri_dbg_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_crt_byp_pri_dbg_offset to ex1_crt_byp_pri_dbg_offset + ex1_crt_byp_pri_dbg_q'length-1), + scout => sov(ex1_crt_byp_pri_dbg_offset to ex1_crt_byp_pri_dbg_offset + ex1_crt_byp_pri_dbg_q'length-1), + din => rf1_crt_byp_pri , + dout => ex1_crt_byp_pri_dbg_q); +ex6_val_dbg_latch : tri_rlmreg_p + generic map (width => ex6_val_dbg_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_val_dbg_offset to ex6_val_dbg_offset + ex6_val_dbg_q'length-1), + scout => sov(ex6_val_dbg_offset to ex6_val_dbg_offset + ex6_val_dbg_q'length-1), + din => ex5_val , + dout => ex6_val_dbg_q); + +siv(0 to siv'right) <= sov(1 to siv'right) & scan_in; +scan_out <= sov(0); + + +end architecture xuq_byp_cr; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_byp_gpr.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_byp_gpr.vhdl new file mode 100644 index 0000000..5307ab3 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_byp_gpr.vhdl @@ -0,0 +1,1598 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee,ibm,support,tri; +use ieee.std_logic_1164.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use tri.tri_latches_pkg.all; +use support.power_logic_pkg.all; +use work.xuq_pkg.all; + +entity xuq_byp_gpr is +generic ( + threads : integer := 4; + expand_type : integer := 2; + regsize : integer := 64; + eff_ifar : integer := 62); +port ( + nclk : in clk_logic; + vdd : inout power_logic; + gnd : inout power_logic; + d_mode_dc : in std_ulogic; + delay_lclkr_dc : in std_ulogic; + mpw1_dc_b : in std_ulogic; + mpw2_dc_b : in std_ulogic; + func_sl_force : in std_ulogic; + func_sl_thold_0_b : in std_ulogic; + func_slp_sl_force : in std_ulogic; + func_slp_sl_thold_0_b : in std_ulogic; + func_nsl_force : in std_ulogic; + func_nsl_thold_0_b : in std_ulogic; + sg_0 : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + dec_byp_ex3_instr_trace_val : in std_ulogic; + dec_byp_ex3_instr_trace_gate : in std_ulogic; + pc_xu_trace_bus_enable : in std_ulogic; + trace_bus_enable : out std_ulogic; + + dec_rf1_tid : in std_ulogic_vector(0 to threads-1); + dec_ex2_tid : in std_ulogic_vector(0 to threads-1); + dec_byp_rf0_act : in std_ulogic; + + dec_byp_rf1_rs0_sel : in std_ulogic_vector(1 to 9); + dec_byp_rf1_rs1_sel : in std_ulogic_vector(1 to 10); + dec_byp_rf1_rs2_sel : in std_ulogic_vector(1 to 9); + + dec_alu_rf1_sel : in std_ulogic_vector(2 to 2); + fxa_fxb_rf0_is_mfocrf : in std_ulogic; + dec_byp_ex1_spr_sel : in std_ulogic; + alu_ex2_div_done : in std_ulogic; + dec_byp_ex3_tlb_sel : in std_ulogic_vector(0 to 1); + alu_ex4_mul_done : in std_ulogic; + dec_byp_ex4_is_mfcr : in std_ulogic; + spr_byp_ex4_is_mfxer : in std_ulogic_vector(0 to 3); + lsu_xu_ex5_wren : in std_ulogic; + + slowspr_val_in : in std_ulogic; + slowspr_rw_in : in std_ulogic; + slowspr_addr_in : in std_ulogic_vector(0 to 9); + slowspr_etid_in : in std_ulogic_vector(0 to 1); + slowspr_done_in : in std_ulogic; + + dec_byp_ex4_dcr_ack : in std_ulogic; + an_ac_dcr_act : in std_ulogic; + an_ac_dcr_read : in std_ulogic; + an_ac_dcr_etid : in std_ulogic_vector(0 to 1); + an_ac_dcr_done : in std_ulogic; + + xu_iu_slowspr_done : out std_ulogic_vector(0 to 3); + mux_cpl_slowspr_done : out std_ulogic_vector(0 to 3); + mux_cpl_slowspr_flush : out std_ulogic_vector(0 to threads-1); + + + dec_byp_rf1_imm : in std_ulogic_vector(64-regsize to 63); + fxa_fxb_rf1_do0 : in std_ulogic_vector(64-regsize to 63); + fxa_fxb_rf1_do1 : in std_ulogic_vector(64-regsize to 63); + fxa_fxb_rf1_do2 : in std_ulogic_vector(64-regsize to 63); + + alu_byp_ex1_log_rt : in std_ulogic_vector(64-regsize to 63); + alu_byp_ex2_rt : in std_ulogic_vector(64-regsize to 63); + alu_byp_ex3_div_rt : in std_ulogic_vector(64-regsize to 63); + cpl_byp_ex3_spr_rt : in std_ulogic_vector(64-regsize to 63); + spr_byp_ex3_spr_rt : in std_ulogic_vector(64-regsize to 63); + fspr_byp_ex3_spr_rt : in std_ulogic_vector(64-regsize to 63); + lsu_xu_ex4_tlb_data : in std_ulogic_vector(64-regsize to 63); + iu_xu_ex4_tlb_data : in std_ulogic_vector(64-regsize to 63); + alu_byp_ex5_mul_rt : in std_ulogic_vector(64-regsize to 63); + lsu_xu_rot_ex6_data_b : in std_ulogic_vector(64-regsize to 63); + lsu_xu_rot_rel_data : in std_ulogic_vector(64-regsize to 63); + slowspr_data_in : in std_ulogic_vector(64-regsize to 63); + an_ac_dcr_data : in std_ulogic_vector(64-regsize to 63); + + byp_ex5_cr_rt : in std_ulogic_vector(32 to 63); + byp_ex5_xer_rt : in std_ulogic_vector(54 to 63); + ex1_mfocrf_rt : in std_ulogic_vector(64-regsize to 63); + + byp_alu_ex1_rs0 : out std_ulogic_vector(64-regsize to 63); + byp_alu_ex1_rs1 : out std_ulogic_vector(64-regsize to 63); + byp_alu_ex1_mulsrc_0 : out std_ulogic_vector(64-regsize to 63); + byp_alu_ex1_mulsrc_1 : out std_ulogic_vector(64-regsize to 63); + byp_alu_ex1_divsrc_0 : out std_ulogic_vector(64-regsize to 63); + byp_alu_ex1_divsrc_1 : out std_ulogic_vector(64-regsize to 63); + xu_lsu_ex1_add_src0 : out std_ulogic_vector(64-regsize to 63); + xu_lsu_ex1_add_src1 : out std_ulogic_vector(64-regsize to 63); + + xu_ex1_rs_is : out std_ulogic_vector(0 to 8); + xu_ex1_ra_entry : out std_ulogic_vector(7 to 11); + xu_ex1_rb : out std_ulogic_vector(64-regsize to 51); + xu_ex4_rs_data : out std_ulogic_vector(64-regsize to 63); + xu_mm_derat_epn : out std_ulogic_vector(62-eff_ifar to 51); + xu_pc_ram_data : out std_ulogic_vector(64-regsize to 63); + mux_spr_ex6_rt : out std_ulogic_vector(64-regsize to 63); + + spr_msr_cm : in std_ulogic_vector(0 to threads-1); + + mux_cpl_ex4_rt : out std_ulogic_vector(64-regsize to 63); + byp_ex5_mtcrxer : out std_ulogic_vector(32 to 63); + byp_ex5_tlb_rt : out std_ulogic_vector(51 to 51); + byp_spr_ex6_rt : out std_ulogic_vector(64-regsize to 63); + xu_lsu_ex1_store_data : out std_ulogic_vector(64-regsize to 63); + fxu_spr_ex1_rs2 : out std_ulogic_vector(42 to 55); + fxu_spr_ex1_rs1 : out std_ulogic_vector(54 to 63); + fxu_spr_ex1_rs0 : out std_ulogic_vector(52 to 63); + fxb_fxa_ex7_wd0 : out std_ulogic_vector(64-regsize to 63); + + byp_grp0_debug : out std_ulogic_vector( 0 to 87); + byp_grp1_debug : out std_ulogic_vector( 0 to 87); + byp_grp2_debug : out std_ulogic_vector( 0 to 87); + byp_grp3_debug : out std_ulogic_vector(15 to 87); + byp_grp4_debug : out std_ulogic_vector(14 to 87); + byp_grp5_debug : out std_ulogic_vector(15 to 87) + ); + +-- synopsys translate_off +-- synopsys translate_on +end xuq_byp_gpr; +architecture xuq_byp_gpr of xuq_byp_gpr is + +signal exx_act_q, exx_act_d : std_ulogic_vector(0 to 6); +signal rf1_act_q : std_ulogic; +signal rf1_is_mfocrf_q : std_ulogic; +signal ex1_rs0_u_b_q, rf1_rs0_u : std_ulogic_vector(64-regsize to 63); +signal ex1_rs0_l_b_q, rf1_rs0_l : std_ulogic_vector(64-regsize to 63); +signal ex1_rs1_u_b_q, rf1_rs1_u : std_ulogic_vector(64-regsize to 63); +signal ex1_rs1_l_b_q, rf1_rs1_l : std_ulogic_vector(64-regsize to 63); +signal ex1_rs1_nimm_b_q, rf1_rs1_nimm : std_ulogic_vector(59 to 63); +signal ex1_rs2_q, rf1_rs2 : std_ulogic_vector(64-regsize to 63); +signal ex1_do2_q : std_ulogic_vector(64-regsize to 63); +signal ex1_rs2_gpr_sel_q, ex1_rs2_gpr_sel_d : std_ulogic_vector(0 to regsize/8-1); +signal ex1_rs2_rot_sel_q, ex1_rs2_rot_sel_d : std_ulogic_vector(0 to regsize/8-1); +signal ex1_log_sel_q : std_ulogic; +signal ex1_msr_cm_q, rf1_msr_cm : std_ulogic_vector(0 to 3); +signal ex2_rt_sel_q, ex1_rt_sel : std_ulogic_vector(0 to regsize/8-1); +signal ex2_rt_q, ex1_rt : std_ulogic_vector(64-regsize to 63); +signal ex3_rt_q, ex2_rt : std_ulogic_vector(64-regsize to 63); +signal ex4_rt_q, ex3_rt : std_ulogic_vector(64-regsize to 63); +signal ex5_rt_q, ex4_rt : std_ulogic_vector(64-regsize to 63); +signal ex6_rt_q, ex5_rt : std_ulogic_vector(64-regsize to 63); +signal ex7_rt_q, ex7_rt_q_b, ex6_rt : std_ulogic_vector(64-regsize to 63); +signal ex7_rot_rt_q, ex6_rot_rtu_b : std_ulogic_vector(64-regsize to 63); +signal ex1_is_mfocrf_q, ex1_is_mfocrf_d : std_ulogic_vector(0 to regsize/8-1); +signal ex2_spr_sel_q : std_ulogic; +signal ex3_spr_sel_q : std_ulogic; +signal ex3_div_done_q, ex3_div_done_d : std_ulogic_vector(0 to regsize/8-1); +signal ex4_spr_sel_q, ex4_spr_sel_d : std_ulogic_vector(0 to regsize/8-1); +signal ex4_spr_rt_q, ex4_spr_rt_d : std_ulogic_vector(64-regsize to 63); +signal ex4_tlb_sel_q : std_ulogic_vector(0 to 1); +signal ex5_is_mfxer_q, ex5_is_mfxer_d : std_ulogic_vector(0 to regsize/8-1); +signal ex5_is_mfcr_q, ex5_is_mfcr_d : std_ulogic_vector(0 to regsize/8-1); +signal ex5_mul_done_q, ex5_mul_done_d : std_ulogic_vector(0 to regsize/8-1); +signal ex5_dtlb_sel_q, ex5_dtlb_sel_d : std_ulogic_vector(0 to regsize/8-1); +signal ex5_itlb_sel_q, ex5_itlb_sel_d : std_ulogic_vector(0 to regsize/8-1); +signal ex5_tlb_data_iu_q : std_ulogic_vector(64-regsize to 63); +signal ex5_tlb_data_lsu_q : std_ulogic_vector(64-regsize to 63); +signal ex5_slowspr_sel_q, ex5_slowspr_sel_d : std_ulogic_vector(0 to regsize/8-1); +signal ex5_ones_sel_q, ex5_ones_sel_d : std_ulogic_vector(0 to regsize/8-1); +signal ex5_slowspr_val_q : std_ulogic; +signal ex5_slowspr_data_q : std_ulogic_vector(64-regsize to 63); +signal ex5_slowspr_tid_q, ex5_slowspr_tid_d : std_ulogic_vector(0 to 3); +signal ex5_slowspr_addr_q : std_ulogic_vector(0 to 9); +signal ex5_slowspr_wr_val_q,ex5_slowspr_wr_val_d : std_ulogic; +signal ex6_slowspr_flush_q,ex6_slowspr_flush_d : std_ulogic_vector(0 to threads-1); +signal ex4_dcr_act_q : std_ulogic; +signal ex5_dcr_sel_q, ex5_dcr_sel_d : std_ulogic_vector(0 to regsize/8-1); +signal ex5_dcr_ack_q : std_ulogic; +signal ex5_dcr_data_q : std_ulogic_vector(64-regsize to 63); +signal ex5_dcr_tid_q, ex5_dcr_tid_d : std_ulogic_vector(0 to 3); +signal ex6_lsu_wren_q, ex6_lsu_wren_d : std_ulogic_vector(0 to regsize/8); +signal ex3_derat_epn_q, ex3_derat_epn_d : std_ulogic_vector(62-eff_ifar to 51); +signal spr_msr_cm_q : std_ulogic_vector(0 to threads-1); +signal trace_bus_enable_q : std_ulogic; +signal ex4_instr_trace_val_q : std_ulogic; +signal ex5_instr_trace_val_q : std_ulogic; +signal ex4_instr_trace_gate_q : std_ulogic; +signal ex5_instr_trace_gate_q, ex5_instr_trace_gate_d : std_ulogic_vector(0 to 3); +signal ex1_rs0_sel_dbg_q : std_ulogic_vector(1 to 9); +signal ex1_rs1_sel_dbg_q : std_ulogic_vector(1 to 10); +signal ex1_rs2_sel_dbg_q : std_ulogic_vector(1 to 9); +signal spare_0_q, spare_0_d : std_ulogic_vector(0 to 15); +signal spare_1_q, spare_1_d : std_ulogic_vector(0 to 15); +signal spare_2_q, spare_2_d : std_ulogic_vector(0 to 15); +signal spare_3_q, spare_3_d : std_ulogic_vector(0 to 15); +signal spare_4_q, spare_4_d : std_ulogic_vector(0 to 15); + +constant exx_act_offset : integer := 0; +constant rf1_act_offset : integer := exx_act_offset + exx_act_q'length; +constant rf1_is_mfocrf_offset : integer := rf1_act_offset + 1; +constant ex1_rs0_u_b_offset : integer := rf1_is_mfocrf_offset + 1; +constant ex1_rs0_l_b_offset : integer := ex1_rs0_u_b_offset + ex1_rs0_u_b_q'length; +constant ex1_rs1_u_b_offset : integer := ex1_rs0_l_b_offset + ex1_rs0_l_b_q'length; +constant ex1_rs1_l_b_offset : integer := ex1_rs1_u_b_offset + ex1_rs1_u_b_q'length; +constant ex1_rs1_nimm_b_offset : integer := ex1_rs1_l_b_offset + ex1_rs1_l_b_q'length; +constant ex1_rs2_offset : integer := ex1_rs1_nimm_b_offset + ex1_rs1_nimm_b_q'length; +constant ex1_do2_offset : integer := ex1_rs2_offset + ex1_rs2_q'length; +constant ex1_rs2_gpr_sel_offset : integer := ex1_do2_offset + ex1_do2_q'length; +constant ex1_rs2_rot_sel_offset : integer := ex1_rs2_gpr_sel_offset + ex1_rs2_gpr_sel_q'length; +constant ex1_log_sel_offset : integer := ex1_rs2_rot_sel_offset + ex1_rs2_rot_sel_q'length; +constant ex1_msr_cm_offset : integer := ex1_log_sel_offset + 1; +constant ex3_rt_offset : integer := ex1_msr_cm_offset + ex1_msr_cm_q'length; +constant ex5_rt_offset : integer := ex3_rt_offset + ex3_rt_q'length; +constant ex7_rt_offset : integer := ex5_rt_offset + ex5_rt_q'length; +constant ex7_rot_rt_offset : integer := ex7_rt_offset + ex7_rt_q'length; +constant ex1_is_mfocrf_offset : integer := ex7_rot_rt_offset + ex7_rot_rt_q'length; +constant ex2_spr_sel_offset : integer := ex1_is_mfocrf_offset + ex1_is_mfocrf_q'length; +constant ex3_spr_sel_offset : integer := ex2_spr_sel_offset + 1; +constant ex3_div_done_offset : integer := ex3_spr_sel_offset + 1; +constant ex5_is_mfxer_offset : integer := ex3_div_done_offset + ex3_div_done_q'length; +constant ex5_is_mfcr_offset : integer := ex5_is_mfxer_offset + ex5_is_mfxer_q'length; +constant ex5_mul_done_offset : integer := ex5_is_mfcr_offset + ex5_is_mfcr_q'length; +constant ex5_dtlb_sel_offset : integer := ex5_mul_done_offset + ex5_mul_done_q'length; +constant ex5_itlb_sel_offset : integer := ex5_dtlb_sel_offset + ex5_dtlb_sel_q'length; +constant ex5_tlb_data_iu_offset : integer := ex5_itlb_sel_offset + ex5_itlb_sel_q'length; +constant ex5_tlb_data_lsu_offset : integer := ex5_tlb_data_iu_offset + ex5_tlb_data_iu_q'length; +constant ex5_slowspr_sel_offset : integer := ex5_tlb_data_lsu_offset + ex5_tlb_data_lsu_q'length; +constant ex5_ones_sel_offset : integer := ex5_slowspr_sel_offset + ex5_slowspr_sel_q'length; +constant ex5_slowspr_val_offset : integer := ex5_ones_sel_offset + ex5_ones_sel_q'length; +constant ex5_slowspr_data_offset : integer := ex5_slowspr_val_offset + 1; +constant ex5_slowspr_tid_offset : integer := ex5_slowspr_data_offset + ex5_slowspr_data_q'length; +constant ex5_slowspr_addr_offset : integer := ex5_slowspr_tid_offset + ex5_slowspr_tid_q'length; +constant ex5_slowspr_wr_val_offset : integer := ex5_slowspr_addr_offset + ex5_slowspr_addr_q'length; +constant ex6_slowspr_flush_offset : integer := ex5_slowspr_wr_val_offset + 1; +constant ex4_dcr_act_offset : integer := ex6_slowspr_flush_offset + ex6_slowspr_flush_q'length; +constant ex5_dcr_sel_offset : integer := ex4_dcr_act_offset + 1; +constant ex5_dcr_ack_offset : integer := ex5_dcr_sel_offset + ex5_dcr_sel_q'length; +constant ex5_dcr_data_offset : integer := ex5_dcr_ack_offset + 1; +constant ex5_dcr_tid_offset : integer := ex5_dcr_data_offset + ex5_dcr_data_q'length; +constant ex3_derat_epn_offset : integer := ex5_dcr_tid_offset + ex5_dcr_tid_q'length; +constant spr_msr_cm_offset : integer := ex3_derat_epn_offset + ex3_derat_epn_q'length; +constant trace_bus_enable_offset : integer := spr_msr_cm_offset + spr_msr_cm_q'length; +constant ex4_instr_trace_val_offset : integer := trace_bus_enable_offset + 1; +constant ex5_instr_trace_val_offset : integer := ex4_instr_trace_val_offset + 1; +constant ex4_instr_trace_gate_offset : integer := ex5_instr_trace_val_offset + 1; +constant ex5_instr_trace_gate_offset : integer := ex4_instr_trace_gate_offset + 1; +constant ex1_rs0_sel_dbg_offset : integer := ex5_instr_trace_gate_offset + ex5_instr_trace_gate_q'length; +constant ex1_rs1_sel_dbg_offset : integer := ex1_rs0_sel_dbg_offset + ex1_rs0_sel_dbg_q'length; +constant ex1_rs2_sel_dbg_offset : integer := ex1_rs1_sel_dbg_offset + ex1_rs1_sel_dbg_q'length; +constant spare_0_offset : integer := ex1_rs2_sel_dbg_offset + ex1_rs2_sel_dbg_q'length; +constant spare_1_offset : integer := spare_0_offset + spare_0_q'length; +constant spare_2_offset : integer := spare_1_offset + spare_1_q'length; +constant spare_3_offset : integer := spare_2_offset + spare_2_q'length; +constant spare_4_offset : integer := spare_3_offset + spare_3_q'length; +constant scan_right : integer := spare_4_offset + spare_4_q'length; + +signal siv : std_ulogic_vector(0 to scan_right-1); +signal sov : std_ulogic_vector(0 to scan_right-1); +signal tiup : std_ulogic; +signal tidn : std_ulogic_vector(0 to 63); +signal spare_0_lclk : clk_logic; +signal spare_1_lclk : clk_logic; +signal spare_2_lclk : clk_logic; +signal spare_3_lclk : clk_logic; +signal spare_4_lclk : clk_logic; +signal spare_0_d1clk, spare_0_d2clk : std_ulogic; +signal spare_1_d1clk, spare_1_d2clk : std_ulogic; +signal spare_2_d1clk, spare_2_d2clk : std_ulogic; +signal spare_3_d1clk, spare_3_d2clk : std_ulogic; +signal spare_4_d1clk, spare_4_d2clk : std_ulogic; +signal ex1x_d1clk, ex1x_d2clk :std_ulogic ; +signal ex1x_lclk :clk_logic ; +signal ex1_d1clk, ex1_d2clk :std_ulogic ; +signal ex1_lclk :clk_logic ; +signal ex1_slp_d1clk, ex1_slp_d2clk :std_ulogic ; +signal ex1_slp_lclk :clk_logic ; +signal ex7_d1clk, ex7_d2clk :std_ulogic ; +signal ex7_lclk :clk_logic ; +signal exx_act : std_ulogic_vector(0 to 6); +signal rf1_rot_rs0_sel_b : std_ulogic_vector(64-regsize to 63); +signal rf1_rot_rs1_sel_b : std_ulogic_vector(64-regsize to 63); +signal rf1_rot_nimm_rs1_sel_b : std_ulogic_vector(59 to 63); +signal rf1_oth_rs0, rf1_oth_rs0_b : std_ulogic_vector(64-regsize to 63); +signal rf1_oth_rs1, rf1_oth_rs1_b : std_ulogic_vector(64-regsize to 63); +signal rf1_nlsu_rs0, rf1_nlsu_rs0_b : std_ulogic_vector(64-regsize to 63); +signal rf1_nlsu_rs1, rf1_nlsu_rs1_b : std_ulogic_vector(64-regsize to 63); +signal rf1_nimm_rs1, rf1_nimm_rs1_b : std_ulogic_vector(59 to 63); +signal rf1_gpr_rs0_b : std_ulogic_vector(64-regsize to 63); +signal rf1_gpr_rs1_b : std_ulogic_vector(64-regsize to 63); +signal rf1_imm_rs1_b : std_ulogic_vector(64-regsize to 63); +signal rf1_gpr_nimm_rs1_b, rf1_oth_nimm_rs1_b : std_ulogic_vector(59 to 63); +signal ex1_lsu_src0_i1 : std_ulogic_vector(64-regsize to 63); +signal ex1_lsu_src1_i1 : std_ulogic_vector(64-regsize to 63); +signal ex1_lsu_src0_i1_b : std_ulogic_vector(64-regsize to 63); +signal ex1_lsu_src1_i1_b : std_ulogic_vector(64-regsize to 63); +signal ex6_rot_rtl_b , ex6_rot_rt : std_ulogic_vector(64-regsize to 63); +signal ex1_rs2 : std_ulogic_vector(64-regsize to 63); +signal ex4_ones_sel : std_ulogic; +signal ex4_slowspr_sel : std_ulogic; +signal ex4_dcr_sel : std_ulogic; +signal ex5_rt_sel, ex5_nospr_rt_sel : std_ulogic_vector(0 to regsize/8-1); +signal ex5_tlb_rt : std_ulogic_vector(64-regsize to 63); +signal ex5_spr_rt, ex5_nospr_rt : std_ulogic_vector(64-regsize to 63); +signal ex5_cr : std_ulogic_vector(64-regsize to 64); +signal ex5_xer : std_ulogic_vector(64-regsize to 64); +signal ex6_xu_rt, ex6_xu_rt_b : std_ulogic_vector(64-regsize to 63); +signal ex6_lsu_wren_b : std_ulogic_vector(64-regsize to 63); +signal ex5_slowop_done : std_ulogic_vector(0 to 3); +signal ex2_msr_cm : std_ulogic; +signal byp_rs0_debug, byp_rs1_debug, byp_rs2_debug : std_ulogic_vector(0 to 63); +signal byp_gpr_sel_debug : std_ulogic_vector(0 to 19); +signal dec_ex2_tid_int : std_ulogic_vector(0 to threads-1); +signal ex4_slowspr_act : std_ulogic; +signal ex5_slowspr_csync : std_ulogic; +signal ex5_rt_gated : std_ulogic_vector(64-regsize to 63); + + + + +begin + + +tiup <= '1'; +tidn <= (others=>'0'); + +exx_act_d <= dec_byp_rf0_act & exx_act(0 to 5); + +exx_act(0) <= exx_act_q(0); +exx_act(1) <= exx_act_q(1); +exx_act(2) <= exx_act_q(2) or alu_ex2_div_done; +exx_act(3) <= exx_act_q(3); +exx_act(4) <= exx_act_q(4) or alu_ex4_mul_done or dec_byp_ex4_dcr_ack; +exx_act(5) <= exx_act_q(5) or ex5_slowspr_val_q; +exx_act(6) <= exx_act_q(6); + +ex4_slowspr_act <= '1'; + + +ex5_cr <= tidn(0 to regsize-32) & byp_ex5_cr_rt; +ex5_xer <= tidn(0 to regsize-32) & byp_ex5_xer_rt(54 to 56) & tidn(35 to 56) & byp_ex5_xer_rt(57 to 63); + +ex4_spr_rt_d <= spr_byp_ex3_spr_rt or cpl_byp_ex3_spr_rt or fspr_byp_ex3_spr_rt; + +ex1_rt <= (ex1_mfocrf_rt and fanout(ex1_is_mfocrf_q,regsize)) or + (alu_byp_ex1_log_rt and not fanout(ex1_is_mfocrf_q,regsize)); + +ex1_rt_sel <= (0 to regsize/8-1=>ex1_log_sel_q) or ex1_is_mfocrf_q; + +ex2_rt <= (ex2_rt_q and fanout(ex2_rt_sel_q,regsize)) or + (alu_byp_ex2_rt and not fanout(ex2_rt_sel_q,regsize)); + +ex3_rt <= (alu_byp_ex3_div_rt and fanout(ex3_div_done_q,regsize)) or + (ex3_rt_q and not fanout(ex3_div_done_q,regsize)); + +ex4_rt <= (ex4_spr_rt_q and fanout(ex4_spr_sel_q, regsize)) or + (ex4_rt_q and not fanout(ex4_spr_sel_q, regsize)); + + +ex5_rt_sel <= not (ex5_dtlb_sel_q or + ex5_itlb_sel_q or + ex5_is_mfxer_q or + ex5_is_mfcr_q or + ex5_mul_done_q); + +ex5_nospr_rt_sel <= not (ex5_slowspr_sel_q or + ex5_dcr_sel_q); + +ex5_tlb_rt <= (ex5_tlb_data_lsu_q and fanout(ex5_dtlb_sel_q,regsize)) or + (ex5_tlb_data_iu_q and fanout(ex5_itlb_sel_q,regsize)); + +ex5_nospr_rt <= ex5_tlb_rt or + (ex5_xer(65-regsize to 64) and fanout(ex5_is_mfxer_q,regsize)) or + (ex5_cr(65-regsize to 64) and fanout(ex5_is_mfcr_q, regsize)) or + (alu_byp_ex5_mul_rt and fanout(ex5_mul_done_q,regsize)) or + (ex5_rt_q and fanout(ex5_rt_sel, regsize)); + +ex5_spr_rt <= (ex5_nospr_rt and fanout(ex5_nospr_rt_sel, regsize)) or + (ex5_slowspr_data_q and fanout(ex5_slowspr_sel_q,regsize)) or + (ex5_dcr_data_q and fanout(ex5_dcr_sel_q, regsize)); + +ex5_rt <= ex5_spr_rt or fanout(ex5_ones_sel_q,regsize); + +ex6_lsu_wren_b <= not fanout(ex6_lsu_wren_q(0 to 7),regsize); +ex6_xu_rt <= (ex6_rt_q and ex6_lsu_wren_b); +ex6_xu_rt_b <= not ex6_xu_rt; + +u_ex6_rt: ex6_rt <= (ex6_rot_rtu_b or ex6_lsu_wren_b) nand ex6_xu_rt_b; + +mux_cpl_ex4_rt <= ex4_rt; +byp_ex5_mtcrxer <= ex5_rt_q(32 to 63); +byp_ex5_tlb_rt <= ex5_tlb_rt(51 to 51); +byp_spr_ex6_rt <= ex6_rt_q; +fxb_fxa_ex7_wd0 <= ex7_rt_q; + +xu_pc_ram_data <= ex6_rt_q; +mux_spr_ex6_rt <= ex6_rt_q; +xu_ex4_rs_data <= ex4_rt_q; + +ex2_msr_cm <= or_reduce(spr_msr_cm_q and dec_ex2_tid); +ex3_derat_epn_d(62-eff_ifar to 31) <= gate(ex2_rt(62-eff_ifar to 31),ex2_msr_cm); +ex3_derat_epn_d(32 to 51) <= ex2_rt(32 to 51); +xu_mm_derat_epn <= ex3_derat_epn_q; + + +with slowspr_etid_in select + ex5_slowspr_tid_d <= "1000" when "00", + "0100" when "01", + "0010" when "10", + "0001" when others; + +with an_ac_dcr_etid select + ex5_dcr_tid_d <= "1000" when "00", + "0100" when "01", + "0010" when "10", + "0001" when others; + +ex4_slowspr_sel <= slowspr_val_in and slowspr_rw_in and slowspr_done_in; +ex4_dcr_sel <= dec_byp_ex4_dcr_ack and an_ac_dcr_read and an_ac_dcr_done; + +ex4_ones_sel <=(slowspr_val_in and slowspr_rw_in and not slowspr_done_in) or + (dec_byp_ex4_dcr_ack and an_ac_dcr_read and not an_ac_dcr_done); + +ex5_slowop_done <=(ex5_slowspr_tid_q and (0 to 3=> ex5_slowspr_val_q)) or + (ex5_dcr_tid_q and (0 to 3=> ex5_dcr_ack_q)); + +ex5_slowspr_wr_val_d <= slowspr_val_in and not slowspr_rw_in and slowspr_done_in; + +ex5_slowspr_csync <=(ex5_slowspr_addr_q(0 to 9) = "1111111101") or + (ex5_slowspr_addr_q(0 to 9) = "0000110000") or + (ex5_slowspr_addr_q(0 to 9) = "0101010010"); + +ex6_slowspr_flush_d <= gate(ex5_slowspr_tid_q,(ex5_slowspr_wr_val_q and ex5_slowspr_csync)); + +xu_iu_slowspr_done <= ex5_slowop_done; +mux_cpl_slowspr_done <= ex5_slowop_done; +mux_cpl_slowspr_flush <= ex6_slowspr_flush_q; + +ex1_is_mfocrf_d <= (others=>rf1_is_mfocrf_q); +ex4_spr_sel_d <= (others=>ex3_spr_sel_q); +ex3_div_done_d <= (others=>alu_ex2_div_done); +ex5_dtlb_sel_d <= (others=>ex4_tlb_sel_q(0)); +ex5_itlb_sel_d <= (others=>ex4_tlb_sel_q(1)); +ex5_is_mfxer_d <= (others=>or_reduce(spr_byp_ex4_is_mfxer)); +ex5_is_mfcr_d <= (others=>dec_byp_ex4_is_mfcr); +ex5_mul_done_d <= (others=>alu_ex4_mul_done); +ex5_slowspr_sel_d <= (others=>ex4_slowspr_sel); +ex5_dcr_sel_d <= (others=>ex4_dcr_sel); +ex5_ones_sel_d <= (others=>ex4_ones_sel); +ex6_lsu_wren_d <= (others=>lsu_xu_ex5_wren); +ex5_instr_trace_gate_d <= (others=>ex4_instr_trace_gate_q); + +ex1_rs2_gpr_sel_d <= (others=>dec_byp_rf1_rs2_sel(9)); +ex1_rs2_rot_sel_d <= (others=>(ex6_lsu_wren_q(8) and dec_byp_rf1_rs2_sel(6))); + + +rf1_oth_rs0 <= gate(ex1_rt, dec_byp_rf1_rs0_sel(1)) or + gate(ex2_rt, dec_byp_rf1_rs0_sel(2)) or + gate(ex3_rt, dec_byp_rf1_rs0_sel(3)) or + gate(ex4_rt, dec_byp_rf1_rs0_sel(4)) or + gate(ex5_rt, dec_byp_rf1_rs0_sel(5)) or + gate(ex6_xu_rt, dec_byp_rf1_rs0_sel(6)) or + gate(ex7_rt_q, dec_byp_rf1_rs0_sel(7)) or + gate(lsu_xu_rot_rel_data, dec_byp_rf1_rs0_sel(8)); + +rf1_oth_rs0_b <= not rf1_oth_rs0; + +rf1_rot_rs0_sel_b <= (others=>(ex6_lsu_wren_q(8) nand dec_byp_rf1_rs0_sel(6))); + + +u_rf1_gpr_rs0_b: rf1_gpr_rs0_b <= fxa_fxb_rf1_do0 nand (0 to 63=> dec_byp_rf1_rs0_sel(9)); + +u_rf1_nlsu_rs0: rf1_nlsu_rs0 <= rf1_gpr_rs0_b nand rf1_oth_rs0_b; + +u_rf1_nlsu_rs0_b: rf1_nlsu_rs0_b <= not(rf1_nlsu_rs0); + +u_rf1_rs0_u_sel: rf1_rs0_u <= (ex6_rot_rtu_b or rf1_rot_rs0_sel_b) nand rf1_nlsu_rs0_b; +u_rf1_rs0_l_sel: rf1_rs0_l <= (ex6_rot_rtl_b or rf1_rot_rs0_sel_b) nand rf1_nlsu_rs0_b; + +rf1_oth_rs1 <= gate(ex1_rt, dec_byp_rf1_rs1_sel(1)) or + gate(ex2_rt, dec_byp_rf1_rs1_sel(2)) or + gate(ex3_rt, dec_byp_rf1_rs1_sel(3)) or + gate(ex4_rt, dec_byp_rf1_rs1_sel(4)) or + gate(ex5_rt, dec_byp_rf1_rs1_sel(5)) or + gate(ex6_xu_rt, dec_byp_rf1_rs1_sel(6)) or + gate(ex7_rt_q, dec_byp_rf1_rs1_sel(7)) or + gate(lsu_xu_rot_rel_data, dec_byp_rf1_rs1_sel(8)); + +rf1_rot_nimm_rs1_sel_b <= (others=>not((ex6_lsu_wren_q(8) and dec_byp_rf1_rs1_sel(6)))); +rf1_rot_rs1_sel_b <= (others=>not((ex6_lsu_wren_q(8) and dec_byp_rf1_rs1_sel(6) and not dec_byp_rf1_rs1_sel(10)))); + +u_rf1_oth_nimm_rs1_b: + rf1_oth_nimm_rs1_b <= not(rf1_oth_rs1(59 to 63)); +u_rf1_oth_rs1_b: rf1_oth_rs1_b <= rf1_oth_rs1 nand (0 to 63=>not(dec_byp_rf1_rs1_sel(10))); + +u_rf1_gpr_nimm_rs1_b: + rf1_gpr_nimm_rs1_b <= fxa_fxb_rf1_do1(59 to 63) nand (59 to 63=> dec_byp_rf1_rs1_sel(9)); +u_rf1_gpr_rs1_b: rf1_gpr_rs1_b <= fxa_fxb_rf1_do1 nand (0 to 63=>(dec_byp_rf1_rs1_sel(9) and not dec_byp_rf1_rs1_sel(10))); + +u_rf1_imm_rs1_b: rf1_imm_rs1_b <= dec_byp_rf1_imm nand (0 to 63=> dec_byp_rf1_rs1_sel(10)); + +u_rf1_nimm_rs1: rf1_nimm_rs1 <= not(rf1_gpr_nimm_rs1_b(59 to 63) and rf1_oth_nimm_rs1_b(59 to 63)); +u_rf1_nlsu_rs1: rf1_nlsu_rs1 <= not(rf1_gpr_rs1_b and rf1_oth_rs1_b and rf1_imm_rs1_b); + +u_rf1_nimm_rs1_b: rf1_nimm_rs1_b <= not(rf1_nimm_rs1); +u_rf1_nlsu_rs1_b: rf1_nlsu_rs1_b <= not(rf1_nlsu_rs1); + +u_rf1_rs1_u_sel: rf1_rs1_u <= (ex6_rot_rtu_b or rf1_rot_rs1_sel_b) nand rf1_nlsu_rs1_b; +u_rf1_rs1_l_sel: rf1_rs1_l <= (ex6_rot_rtl_b or rf1_rot_rs1_sel_b) nand rf1_nlsu_rs1_b; + +u_rf1_rs1_nimm: rf1_rs1_nimm <= (ex6_rot_rtu_b(59 to 63) or rf1_rot_nimm_rs1_sel_b(59 to 63)) nand rf1_nimm_rs1_b(59 to 63); + +rf1_rs2 <= gate(ex1_rt, dec_byp_rf1_rs2_sel(1)) or + gate(ex2_rt, dec_byp_rf1_rs2_sel(2)) or + gate(ex3_rt, dec_byp_rf1_rs2_sel(3)) or + gate(ex4_rt, dec_byp_rf1_rs2_sel(4)) or + gate(ex5_rt, dec_byp_rf1_rs2_sel(5)) or + gate(ex6_xu_rt, dec_byp_rf1_rs2_sel(6)) or + gate(ex7_rt_q, dec_byp_rf1_rs2_sel(7)) or + gate(lsu_xu_rot_rel_data, dec_byp_rf1_rs2_sel(8)); + +ex1_rs2 <= (ex1_do2_q and fanout(ex1_rs2_gpr_sel_q,regsize)) or + (ex7_rot_rt_q and fanout(ex1_rs2_rot_sel_q,regsize)) or + ex1_rs2_q; + +xu_ex1_rs_is <= ex1_rs2(55 to 63); +xu_lsu_ex1_store_data <= ex1_rs2; +fxu_spr_ex1_rs2 <= ex1_rs2(42 to 55); +xu_ex1_ra_entry <= not ex1_rs1_nimm_b_q(59 to 63); + +rf1_msr_cm <=(others=>or_reduce(spr_msr_cm_q and dec_rf1_tid)); +xu_ex1_rb(64-regsize to 31) <=(not ex1_rs1_u_b_q(64-regsize to 31)) and fanout(ex1_msr_cm_q,32); +xu_ex1_rb(32 to 51) <= not ex1_rs1_u_b_q(32 to 51); + +u_rot_rt_i1: ex6_rot_rt <= not lsu_xu_rot_ex6_data_b; +u_rot_rt_i2u: ex6_rot_rtu_b <= not ex6_rot_rt ; +u_rot_rt_i2l: ex6_rot_rtl_b <= not ex6_rot_rt ; + +u_rs0_i1: byp_alu_ex1_rs0 <= not ex1_rs0_u_b_q; +u_rs1_i1: byp_alu_ex1_rs1 <= not ex1_rs1_u_b_q; + + +u_lsu_src0_i1: ex1_lsu_src0_i1 <= not ex1_rs0_l_b_q; + xu_lsu_ex1_add_src0 <= ex1_lsu_src0_i1; +u_lsu_src0_i2: ex1_lsu_src0_i1_b <= not ex1_lsu_src0_i1; + byp_alu_ex1_mulsrc_0 <= not ex1_lsu_src0_i1_b; + byp_alu_ex1_divsrc_0 <= not ex1_lsu_src0_i1_b; + fxu_spr_ex1_rs0 <= not ex1_lsu_src0_i1_b(52 to 63); + + +u_lsu_src1_i1: ex1_lsu_src1_i1 <= not ex1_rs1_l_b_q; + xu_lsu_ex1_add_src1 <= ex1_lsu_src1_i1; +u_lsu_src1_i2: ex1_lsu_src1_i1_b <= not ex1_lsu_src1_i1; + byp_alu_ex1_mulsrc_1 <= not ex1_lsu_src1_i1_b; + byp_alu_ex1_divsrc_1 <= not ex1_lsu_src1_i1_b; + fxu_spr_ex1_rs1 <= not ex1_lsu_src1_i1_b(54 to 63); + +byp_rs0_debug <= not ex1_rs0_u_b_q; +byp_rs1_debug <= not ex1_rs1_u_b_q; +byp_rs2_debug <= ex1_rs2; + +byp_gpr_sel_debug <= ex1_is_mfocrf_q(0) & + ex1_log_sel_q & + ex2_rt_sel_q(0) & + ex3_div_done_q(0) & + ex4_spr_sel_q(0) & + ex5_dtlb_sel_q(0) & + ex5_itlb_sel_q(0) & + ex5_is_mfxer_q(0) & + ex5_is_mfcr_q(0) & + ex5_mul_done_q(0) & + ex5_slowspr_sel_q(0) & + ex5_dcr_sel_q(0) & + ex5_ones_sel_q(0) & + ex6_lsu_wren_q(0) & + ex5_dcr_ack_q & + ex5_slowspr_val_q & + ex5_slowop_done; + +dec_ex2_tid_int(0) <= dec_ex2_tid(0) and not ex5_instr_trace_val_q; +dec_ex2_tid_int(1 to 2) <= dec_ex2_tid(1 to 2); +dec_ex2_tid_int(3) <= dec_ex2_tid(3) or ex5_instr_trace_val_q; + +ex5_rt_gated(0 to 31) <= ex5_rt_q(0 to 31) and not fanout(ex5_instr_trace_gate_q,regsize/2); +ex5_rt_gated(32 to 63) <= ex5_rt_q(32 to 63); + +byp_grp0_debug <= ex3_rt_q & dec_ex2_tid & byp_gpr_sel_debug; +byp_grp1_debug <= ex5_rt_gated & dec_ex2_tid_int & byp_gpr_sel_debug; +byp_grp2_debug <= ex7_rt_q & dec_ex2_tid & byp_gpr_sel_debug; +byp_grp3_debug <= ex1_rs0_sel_dbg_q & byp_rs0_debug; +byp_grp4_debug <= ex1_rs1_sel_dbg_q & byp_rs1_debug; +byp_grp5_debug <= ex1_rs2_sel_dbg_q & byp_rs2_debug; + +trace_bus_enable <= trace_bus_enable_q; + +mark_unused(ex5_cr(64-regsize)); +mark_unused(ex5_xer(64-regsize)); +mark_unused(ex1_mfocrf_rt(64-regsize)); +mark_unused(tidn(0 to 63)); + +exx_act_latch : tri_rlmreg_p + generic map (width => exx_act_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(exx_act_offset to exx_act_offset + exx_act_q'length-1), + scout => sov(exx_act_offset to exx_act_offset + exx_act_q'length-1), + din => exx_act_d, + dout => exx_act_q); +rf1_act_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(rf1_act_offset), + scout => sov(rf1_act_offset), + din => dec_byp_rf0_act, + dout => rf1_act_q); +rf1_is_mfocrf_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf1_is_mfocrf_offset), + scout => sov(rf1_is_mfocrf_offset), + din => fxa_fxb_rf0_is_mfocrf, + dout => rf1_is_mfocrf_q); + + ex1_rs0_u_b_lat: entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width=> ex1_rs0_l_b_q'length, btr => "NLI0001_X4_A12TH", expand_type => expand_type, needs_sreset => 1, init => (ex1_rs0_l_b_q'range=>'0') ) port map ( + VD => vdd , + GD => gnd , + LCLK => ex1_lclk , + D1CLK => ex1_d1clk , + D2CLK => ex1_d2clk , + SCANIN => siv(ex1_rs0_u_b_offset to ex1_rs0_u_b_offset + ex1_rs0_u_b_q'length-1) , + SCANOUT => sov(ex1_rs0_u_b_offset to ex1_rs0_u_b_offset + ex1_rs0_u_b_q'length-1) , + D => rf1_rs0_u , + QB => ex1_rs0_u_b_q ); + + ex1_rs0_l_b_lat: entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width=> ex1_rs0_l_b_q'length, btr => "NLI0001_X4_A12TH", expand_type => expand_type, needs_sreset => 1, init => (ex1_rs0_l_b_q'range=>'0') ) port map ( + VD => vdd , + GD => gnd , + LCLK => ex1_slp_lclk , + D1CLK => ex1_slp_d1clk , + D2CLK => ex1_slp_d2clk , + SCANIN => siv(ex1_rs0_l_b_offset to ex1_rs0_l_b_offset + ex1_rs0_l_b_q'length-1) , + SCANOUT => sov(ex1_rs0_l_b_offset to ex1_rs0_l_b_offset + ex1_rs0_l_b_q'length-1) , + D => rf1_rs0_l , + QB => ex1_rs0_l_b_q ); + + ex1_rs1_u_b_lat: entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width=> ex1_rs1_l_b_q'length, btr => "NLI0001_X4_A12TH", expand_type => expand_type, needs_sreset => 1, init => (ex1_rs1_l_b_q'range=>'0') ) port map ( + VD => vdd , + GD => gnd , + LCLK => ex1_lclk , + D1CLK => ex1_d1clk , + D2CLK => ex1_d2clk , + SCANIN => siv(ex1_rs1_u_b_offset to ex1_rs1_u_b_offset + ex1_rs1_u_b_q'length-1) , + SCANOUT => sov(ex1_rs1_u_b_offset to ex1_rs1_u_b_offset + ex1_rs1_u_b_q'length-1) , + D => rf1_rs1_u , + QB => ex1_rs1_u_b_q ); + + ex1_rs1_l_b_lat: entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width=> ex1_rs1_l_b_q'length, btr => "NLI0001_X4_A12TH", expand_type => expand_type, needs_sreset => 1, init => (ex1_rs1_l_b_q'range=>'0') ) port map ( + VD => vdd , + GD => gnd , + LCLK => ex1_slp_lclk , + D1CLK => ex1_slp_d1clk , + D2CLK => ex1_slp_d2clk , + SCANIN => siv(ex1_rs1_l_b_offset to ex1_rs1_l_b_offset + ex1_rs1_l_b_q'length-1) , + SCANOUT => sov(ex1_rs1_l_b_offset to ex1_rs1_l_b_offset + ex1_rs1_l_b_q'length-1) , + D => rf1_rs1_l , + QB => ex1_rs1_l_b_q ); + + ex1_rs1_nimm_b_lat: entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width=> ex1_rs1_nimm_b_q'length, btr => "NLI0001_X1_A12TH", expand_type => expand_type, needs_sreset => 1, init => (ex1_rs1_nimm_b_q'range=>'0') ) port map ( + VD => vdd , + GD => gnd , + LCLK => ex1x_lclk , + D1CLK => ex1x_d1clk , + D2CLK => ex1x_d2clk , + SCANIN => siv(ex1_rs1_nimm_b_offset to ex1_rs1_nimm_b_offset + ex1_rs1_nimm_b_q'length-1) , + SCANOUT => sov(ex1_rs1_nimm_b_offset to ex1_rs1_nimm_b_offset + ex1_rs1_nimm_b_q'length-1) , + D => rf1_rs1_nimm , + QB => ex1_rs1_nimm_b_q ); + +ex1_rs2_latch : tri_rlmreg_p + generic map (width => ex1_rs2_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_rs2_offset to ex1_rs2_offset + ex1_rs2_q'length-1), + scout => sov(ex1_rs2_offset to ex1_rs2_offset + ex1_rs2_q'length-1), + din => rf1_rs2, + dout => ex1_rs2_q); +ex1_do2_latch : tri_rlmreg_p + generic map (width => ex1_do2_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_do2_offset to ex1_do2_offset + ex1_do2_q'length-1), + scout => sov(ex1_do2_offset to ex1_do2_offset + ex1_do2_q'length-1), + din => fxa_fxb_rf1_do2, + dout => ex1_do2_q); +ex1_rs2_gpr_sel_latch : tri_rlmreg_p + generic map (width => ex1_rs2_gpr_sel_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_rs2_gpr_sel_offset to ex1_rs2_gpr_sel_offset + ex1_rs2_gpr_sel_q'length-1), + scout => sov(ex1_rs2_gpr_sel_offset to ex1_rs2_gpr_sel_offset + ex1_rs2_gpr_sel_q'length-1), + din => ex1_rs2_gpr_sel_d, + dout => ex1_rs2_gpr_sel_q); +ex1_log_sel_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_log_sel_offset), + scout => sov(ex1_log_sel_offset), + din => dec_alu_rf1_sel(2), + dout => ex1_log_sel_q); +ex1_rs2_rot_sel_latch : tri_rlmreg_p + generic map (width => ex1_rs2_rot_sel_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_rs2_rot_sel_offset to ex1_rs2_rot_sel_offset + ex1_rs2_rot_sel_q'length-1), + scout => sov(ex1_rs2_rot_sel_offset to ex1_rs2_rot_sel_offset + ex1_rs2_rot_sel_q'length-1), + din => ex1_rs2_rot_sel_d, + dout => ex1_rs2_rot_sel_q); +ex1_msr_cm_latch : tri_rlmreg_p + generic map (width => ex1_msr_cm_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_msr_cm_offset to ex1_msr_cm_offset + ex1_msr_cm_q'length-1), + scout => sov(ex1_msr_cm_offset to ex1_msr_cm_offset + ex1_msr_cm_q'length-1), + din => rf1_msr_cm, + dout => ex1_msr_cm_q); +ex2_rt_sel_latch : tri_regk + generic map (width => ex2_rt_sel_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1), + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex1_rt_sel, + dout => ex2_rt_sel_q); +ex2_rt_latch : tri_regk + generic map (width => ex2_rt_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1), + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex1_rt, + dout => ex2_rt_q); +ex3_rt_latch : tri_rlmreg_p + generic map (width => ex3_rt_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_rt_offset to ex3_rt_offset + ex3_rt_q'length-1), + scout => sov(ex3_rt_offset to ex3_rt_offset + ex3_rt_q'length-1), + din => ex2_rt, + dout => ex3_rt_q); +ex4_rt_latch : tri_regk + generic map (width => ex4_rt_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3), + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex3_rt, + dout => ex4_rt_q); +ex5_rt_latch : tri_rlmreg_p + generic map (width => ex5_rt_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_rt_offset to ex5_rt_offset + ex5_rt_q'length-1), + scout => sov(ex5_rt_offset to ex5_rt_offset + ex5_rt_q'length-1), + din => ex4_rt, + dout => ex5_rt_q); +ex6_rt_latch : tri_regk + generic map (width => ex6_rt_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(5), + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex5_rt, + dout => ex6_rt_q); + + ex7_rt_lat: entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width=> ex7_rot_rt_q'length, btr => "NLI0001_X1_A12TH", expand_type => expand_type, needs_sreset => 1, init => (ex7_rot_rt_q'range=>'0') ) port map ( + VD => vdd , + GD => gnd , + LCLK => ex7_lclk , + D1CLK => ex7_d1clk , + D2CLK => ex7_d2clk , + SCANIN => siv(ex7_rt_offset to ex7_rt_offset + ex7_rt_q'length-1) , + SCANOUT => sov(ex7_rt_offset to ex7_rt_offset + ex7_rt_q'length-1) , + D => ex6_rt , + QB => ex7_rt_q_b ); + + ex7_rt_q <= not ex7_rt_q_b ; + + ex7_rot_rt_lat: entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width=> ex7_rot_rt_q'length, btr => "NLI0001_X1_A12TH", expand_type => expand_type, needs_sreset => 1, init => (ex7_rot_rt_q'range=>'0') ) port map ( + VD => vdd , + GD => gnd , + LCLK => ex7_lclk , + D1CLK => ex7_d1clk , + D2CLK => ex7_d2clk , + SCANIN => siv(ex7_rot_rt_offset to ex7_rot_rt_offset + ex7_rot_rt_q'length-1), + SCANOUT => sov(ex7_rot_rt_offset to ex7_rot_rt_offset + ex7_rot_rt_q'length-1), + D => ex6_rot_rtu_b , + QB => ex7_rot_rt_q ); + + + +ex1_is_mfocrf_latch : tri_rlmreg_p + generic map (width => ex1_is_mfocrf_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_mfocrf_offset to ex1_is_mfocrf_offset + ex1_is_mfocrf_q'length-1), + scout => sov(ex1_is_mfocrf_offset to ex1_is_mfocrf_offset + ex1_is_mfocrf_q'length-1), + din => ex1_is_mfocrf_d, + dout => ex1_is_mfocrf_q); +ex2_spr_sel_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_spr_sel_offset), + scout => sov(ex2_spr_sel_offset), + din => dec_byp_ex1_spr_sel, + dout => ex2_spr_sel_q); +ex3_spr_sel_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_spr_sel_offset), + scout => sov(ex3_spr_sel_offset), + din => ex2_spr_sel_q, + dout => ex3_spr_sel_q); +ex3_div_done_latch : tri_rlmreg_p + generic map (width => ex3_div_done_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_div_done_offset to ex3_div_done_offset + ex3_div_done_q'length-1), + scout => sov(ex3_div_done_offset to ex3_div_done_offset + ex3_div_done_q'length-1), + din => ex3_div_done_d, + dout => ex3_div_done_q); +ex4_spr_sel_latch : tri_regk + generic map (width => ex4_spr_sel_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3), + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex4_spr_sel_d, + dout => ex4_spr_sel_q); +ex4_spr_rt_latch : tri_regk + generic map (width => ex4_spr_rt_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3), + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex4_spr_rt_d, + dout => ex4_spr_rt_q); +ex4_tlb_sel_latch : tri_regk + generic map (width => ex4_tlb_sel_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => dec_byp_ex3_tlb_sel, + dout => ex4_tlb_sel_q); +ex5_is_mfxer_latch : tri_rlmreg_p + generic map (width => ex5_is_mfxer_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_is_mfxer_offset to ex5_is_mfxer_offset + ex5_is_mfxer_q'length-1), + scout => sov(ex5_is_mfxer_offset to ex5_is_mfxer_offset + ex5_is_mfxer_q'length-1), + din => ex5_is_mfxer_d, + dout => ex5_is_mfxer_q); +ex5_is_mfcr_latch : tri_rlmreg_p + generic map (width => ex5_is_mfcr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_is_mfcr_offset to ex5_is_mfcr_offset + ex5_is_mfcr_q'length-1), + scout => sov(ex5_is_mfcr_offset to ex5_is_mfcr_offset + ex5_is_mfcr_q'length-1), + din => ex5_is_mfcr_d, + dout => ex5_is_mfcr_q); +ex5_mul_done_latch : tri_rlmreg_p + generic map (width => ex5_mul_done_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_mul_done_offset to ex5_mul_done_offset + ex5_mul_done_q'length-1), + scout => sov(ex5_mul_done_offset to ex5_mul_done_offset + ex5_mul_done_q'length-1), + din => ex5_mul_done_d, + dout => ex5_mul_done_q); +ex5_dtlb_sel_latch : tri_rlmreg_p + generic map (width => ex5_dtlb_sel_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_dtlb_sel_offset to ex5_dtlb_sel_offset + ex5_dtlb_sel_q'length-1), + scout => sov(ex5_dtlb_sel_offset to ex5_dtlb_sel_offset + ex5_dtlb_sel_q'length-1), + din => ex5_dtlb_sel_d, + dout => ex5_dtlb_sel_q); +ex5_itlb_sel_latch : tri_rlmreg_p + generic map (width => ex5_itlb_sel_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_itlb_sel_offset to ex5_itlb_sel_offset + ex5_itlb_sel_q'length-1), + scout => sov(ex5_itlb_sel_offset to ex5_itlb_sel_offset + ex5_itlb_sel_q'length-1), + din => ex5_itlb_sel_d, + dout => ex5_itlb_sel_q); +ex5_tlb_data_iu_latch : tri_rlmreg_p + generic map (width => ex5_tlb_data_iu_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_tlb_data_iu_offset to ex5_tlb_data_iu_offset + ex5_tlb_data_iu_q'length-1), + scout => sov(ex5_tlb_data_iu_offset to ex5_tlb_data_iu_offset + ex5_tlb_data_iu_q'length-1), + din => iu_xu_ex4_tlb_data, + dout => ex5_tlb_data_iu_q); +ex5_tlb_data_lsu_latch : tri_rlmreg_p + generic map (width => ex5_tlb_data_lsu_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_tlb_data_lsu_offset to ex5_tlb_data_lsu_offset + ex5_tlb_data_lsu_q'length-1), + scout => sov(ex5_tlb_data_lsu_offset to ex5_tlb_data_lsu_offset + ex5_tlb_data_lsu_q'length-1), + din => lsu_xu_ex4_tlb_data, + dout => ex5_tlb_data_lsu_q); +ex5_slowspr_sel_latch : tri_rlmreg_p + generic map (width => ex5_slowspr_sel_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_slowspr_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_slowspr_sel_offset to ex5_slowspr_sel_offset + ex5_slowspr_sel_q'length-1), + scout => sov(ex5_slowspr_sel_offset to ex5_slowspr_sel_offset + ex5_slowspr_sel_q'length-1), + din => ex5_slowspr_sel_d, + dout => ex5_slowspr_sel_q); +ex5_ones_sel_latch : tri_rlmreg_p + generic map (width => ex5_ones_sel_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_slowspr_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_ones_sel_offset to ex5_ones_sel_offset + ex5_ones_sel_q'length-1), + scout => sov(ex5_ones_sel_offset to ex5_ones_sel_offset + ex5_ones_sel_q'length-1), + din => ex5_ones_sel_d, + dout => ex5_ones_sel_q); +ex5_slowspr_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_slowspr_val_offset), + scout => sov(ex5_slowspr_val_offset), + din => slowspr_val_in, + dout => ex5_slowspr_val_q); +ex5_slowspr_data_latch : tri_rlmreg_p + generic map (width => ex5_slowspr_data_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_slowspr_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_slowspr_data_offset to ex5_slowspr_data_offset + ex5_slowspr_data_q'length-1), + scout => sov(ex5_slowspr_data_offset to ex5_slowspr_data_offset + ex5_slowspr_data_q'length-1), + din => slowspr_data_in, + dout => ex5_slowspr_data_q); +ex5_slowspr_tid_latch : tri_rlmreg_p + generic map (width => ex5_slowspr_tid_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_slowspr_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_slowspr_tid_offset to ex5_slowspr_tid_offset + ex5_slowspr_tid_q'length-1), + scout => sov(ex5_slowspr_tid_offset to ex5_slowspr_tid_offset + ex5_slowspr_tid_q'length-1), + din => ex5_slowspr_tid_d, + dout => ex5_slowspr_tid_q); +ex5_slowspr_addr_latch : tri_rlmreg_p + generic map (width => ex5_slowspr_addr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_slowspr_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_slowspr_addr_offset to ex5_slowspr_addr_offset + ex5_slowspr_addr_q'length-1), + scout => sov(ex5_slowspr_addr_offset to ex5_slowspr_addr_offset + ex5_slowspr_addr_q'length-1), + din => slowspr_addr_in, + dout => ex5_slowspr_addr_q); +ex5_slowspr_wr_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_slowspr_wr_val_offset), + scout => sov(ex5_slowspr_wr_val_offset), + din => ex5_slowspr_wr_val_d, + dout => ex5_slowspr_wr_val_q); +ex6_slowspr_flush_latch : tri_rlmreg_p + generic map (width => ex6_slowspr_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_slowspr_flush_offset to ex6_slowspr_flush_offset + ex6_slowspr_flush_q'length-1), + scout => sov(ex6_slowspr_flush_offset to ex6_slowspr_flush_offset + ex6_slowspr_flush_q'length-1), + din => ex6_slowspr_flush_d, + dout => ex6_slowspr_flush_q); +ex4_dcr_act_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_dcr_act_offset), + scout => sov(ex4_dcr_act_offset), + din => an_ac_dcr_act, + dout => ex4_dcr_act_q); +ex5_dcr_sel_latch : tri_rlmreg_p + generic map (width => ex5_dcr_sel_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_dcr_sel_offset to ex5_dcr_sel_offset + ex5_dcr_sel_q'length-1), + scout => sov(ex5_dcr_sel_offset to ex5_dcr_sel_offset + ex5_dcr_sel_q'length-1), + din => ex5_dcr_sel_d, + dout => ex5_dcr_sel_q); +ex5_dcr_ack_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_dcr_ack_offset), + scout => sov(ex5_dcr_ack_offset), + din => dec_byp_ex4_dcr_ack, + dout => ex5_dcr_ack_q); +ex5_dcr_data_latch : tri_rlmreg_p + generic map (width => ex5_dcr_data_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_dcr_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_dcr_data_offset to ex5_dcr_data_offset + ex5_dcr_data_q'length-1), + scout => sov(ex5_dcr_data_offset to ex5_dcr_data_offset + ex5_dcr_data_q'length-1), + din => an_ac_dcr_data, + dout => ex5_dcr_data_q); +ex5_dcr_tid_latch : tri_rlmreg_p + generic map (width => ex5_dcr_tid_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_dcr_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_dcr_tid_offset to ex5_dcr_tid_offset + ex5_dcr_tid_q'length-1), + scout => sov(ex5_dcr_tid_offset to ex5_dcr_tid_offset + ex5_dcr_tid_q'length-1), + din => ex5_dcr_tid_d, + dout => ex5_dcr_tid_q); +ex6_lsu_wren_latch : tri_regk + generic map (width => ex6_lsu_wren_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(5), + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex6_lsu_wren_d, + dout => ex6_lsu_wren_q); +ex3_derat_epn_latch : tri_rlmreg_p + generic map (width => ex3_derat_epn_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_derat_epn_offset to ex3_derat_epn_offset + ex3_derat_epn_q'length-1), + scout => sov(ex3_derat_epn_offset to ex3_derat_epn_offset + ex3_derat_epn_q'length-1), + din => ex3_derat_epn_d, + dout => ex3_derat_epn_q); +spr_msr_cm_latch : tri_rlmreg_p + generic map (width => spr_msr_cm_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(spr_msr_cm_offset to spr_msr_cm_offset + spr_msr_cm_q'length-1), + scout => sov(spr_msr_cm_offset to spr_msr_cm_offset + spr_msr_cm_q'length-1), + din => spr_msr_cm, + dout => spr_msr_cm_q); +trace_bus_enable_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(trace_bus_enable_offset), + scout => sov(trace_bus_enable_offset), + din => pc_xu_trace_bus_enable, + dout => trace_bus_enable_q); +ex4_instr_trace_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_instr_trace_val_offset), + scout => sov(ex4_instr_trace_val_offset), + din => dec_byp_ex3_instr_trace_val, + dout => ex4_instr_trace_val_q); +ex5_instr_trace_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_instr_trace_val_offset), + scout => sov(ex5_instr_trace_val_offset), + din => ex4_instr_trace_val_q, + dout => ex5_instr_trace_val_q); +ex4_instr_trace_gate_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_instr_trace_gate_offset), + scout => sov(ex4_instr_trace_gate_offset), + din => dec_byp_ex3_instr_trace_gate, + dout => ex4_instr_trace_gate_q); +ex5_instr_trace_gate_latch : tri_rlmreg_p + generic map (width => ex5_instr_trace_gate_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_instr_trace_gate_offset to ex5_instr_trace_gate_offset + ex5_instr_trace_gate_q'length-1), + scout => sov(ex5_instr_trace_gate_offset to ex5_instr_trace_gate_offset + ex5_instr_trace_gate_q'length-1), + din => ex5_instr_trace_gate_d, + dout => ex5_instr_trace_gate_q); +ex1_rs0_sel_dbg_latch : tri_rlmreg_p + generic map (width => ex1_rs0_sel_dbg_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_rs0_sel_dbg_offset to ex1_rs0_sel_dbg_offset + ex1_rs0_sel_dbg_q'length-1), + scout => sov(ex1_rs0_sel_dbg_offset to ex1_rs0_sel_dbg_offset + ex1_rs0_sel_dbg_q'length-1), + din => dec_byp_rf1_rs0_sel, + dout => ex1_rs0_sel_dbg_q); +ex1_rs1_sel_dbg_latch : tri_rlmreg_p + generic map (width => ex1_rs1_sel_dbg_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_rs1_sel_dbg_offset to ex1_rs1_sel_dbg_offset + ex1_rs1_sel_dbg_q'length-1), + scout => sov(ex1_rs1_sel_dbg_offset to ex1_rs1_sel_dbg_offset + ex1_rs1_sel_dbg_q'length-1), + din => dec_byp_rf1_rs1_sel, + dout => ex1_rs1_sel_dbg_q); +ex1_rs2_sel_dbg_latch : tri_rlmreg_p + generic map (width => ex1_rs2_sel_dbg_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_rs2_sel_dbg_offset to ex1_rs2_sel_dbg_offset + ex1_rs2_sel_dbg_q'length-1), + scout => sov(ex1_rs2_sel_dbg_offset to ex1_rs2_sel_dbg_offset + ex1_rs2_sel_dbg_q'length-1), + din => dec_byp_rf1_rs2_sel, + dout => ex1_rs2_sel_dbg_q); + + +spare_0_lcb: entity tri.tri_lcbnd(tri_lcbnd) + port map(vd => vdd, + gd => gnd, + act => tidn(0), + nclk => nclk, + forcee => func_sl_force, + thold_b => func_sl_thold_0_b, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + sg => sg_0, + lclk => spare_0_lclk, + d1clk => spare_0_d1clk, + d2clk => spare_0_d2clk); +spare_0_latch : entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width => spare_0_q'length, expand_type => expand_type, btr => "NLI0001_X2_A12TH", init=>(spare_0_q'range=>'0')) + port map (vd => vdd, gd => gnd, + LCLK => spare_0_lclk, + D1CLK => spare_0_d1clk, + D2CLK => spare_0_d2clk, + SCANIN => siv(spare_0_offset to spare_0_offset + spare_0_q'length-1), + SCANOUT => sov(spare_0_offset to spare_0_offset + spare_0_q'length-1), + D => spare_0_d, + QB => spare_0_q); +spare_0_d <= not spare_0_q; +mark_unused(spare_0_q); + +spare_1_lcb: entity tri.tri_lcbnd(tri_lcbnd) + port map(vd => vdd, + gd => gnd, + act => tidn(0), + nclk => nclk, + forcee => func_sl_force, + thold_b => func_sl_thold_0_b, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + sg => sg_0, + lclk => spare_1_lclk, + d1clk => spare_1_d1clk, + d2clk => spare_1_d2clk); +spare_1_latch : entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width => spare_1_q'length, expand_type => expand_type, btr => "NLI0001_X2_A12TH", init=>(spare_1_q'range=>'0')) + port map (vd => vdd, gd => gnd, + LCLK => spare_1_lclk, + D1CLK => spare_1_d1clk, + D2CLK => spare_1_d2clk, + SCANIN => siv(spare_1_offset to spare_1_offset + spare_1_q'length-1), + SCANOUT => sov(spare_1_offset to spare_1_offset + spare_1_q'length-1), + D => spare_1_d, + QB => spare_1_q); +spare_1_d <= not spare_1_q; +mark_unused(spare_1_q); + +spare_2_lcb: entity tri.tri_lcbnd(tri_lcbnd) + port map(vd => vdd, + gd => gnd, + act => tidn(0), + nclk => nclk, + forcee => func_sl_force, + thold_b => func_sl_thold_0_b, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + sg => sg_0, + lclk => spare_2_lclk, + d1clk => spare_2_d1clk, + d2clk => spare_2_d2clk); +spare_2_latch : entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width => spare_2_q'length, expand_type => expand_type, btr => "NLI0001_X2_A12TH", init=>(spare_2_q'range=>'0')) + port map (vd => vdd, gd => gnd, + LCLK => spare_2_lclk, + D1CLK => spare_2_d1clk, + D2CLK => spare_2_d2clk, + SCANIN => siv(spare_2_offset to spare_2_offset + spare_2_q'length-1), + SCANOUT => sov(spare_2_offset to spare_2_offset + spare_2_q'length-1), + D => spare_2_d, + QB => spare_2_q); +spare_2_d <= not spare_2_q; +mark_unused(spare_2_q); + +spare_3_lcb: entity tri.tri_lcbnd(tri_lcbnd) + port map(vd => vdd, + gd => gnd, + act => tidn(0), + nclk => nclk, + forcee => func_sl_force, + thold_b => func_sl_thold_0_b, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + sg => sg_0, + lclk => spare_3_lclk, + d1clk => spare_3_d1clk, + d2clk => spare_3_d2clk); +spare_3_latch : entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width => spare_3_q'length, expand_type => expand_type, btr => "NLI0001_X2_A12TH", init=>(spare_3_q'range=>'0')) + port map (vd => vdd, gd => gnd, + LCLK => spare_3_lclk, + D1CLK => spare_3_d1clk, + D2CLK => spare_3_d2clk, + SCANIN => siv(spare_3_offset to spare_3_offset + spare_3_q'length-1), + SCANOUT => sov(spare_3_offset to spare_3_offset + spare_3_q'length-1), + D => spare_3_d, + QB => spare_3_q); +spare_3_d <= not spare_3_q; +mark_unused(spare_3_q); + +spare_4_lcb: entity tri.tri_lcbnd(tri_lcbnd) + port map(vd => vdd, + gd => gnd, + act => tidn(0), + nclk => nclk, + forcee => func_sl_force, + thold_b => func_sl_thold_0_b, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + sg => sg_0, + lclk => spare_4_lclk, + d1clk => spare_4_d1clk, + d2clk => spare_4_d2clk); +spare_4_latch : entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width => spare_4_q'length, expand_type => expand_type, btr => "NLI0001_X2_A12TH", init=>(spare_4_q'range=>'0')) + port map (vd => vdd, gd => gnd, + LCLK => spare_4_lclk, + D1CLK => spare_4_d1clk, + D2CLK => spare_4_d2clk, + SCANIN => siv(spare_4_offset to spare_4_offset + spare_4_q'length-1), + SCANOUT => sov(spare_4_offset to spare_4_offset + spare_4_q'length-1), + D => spare_4_d, + QB => spare_4_q); +spare_4_d <= not spare_4_q; +mark_unused(spare_4_q); + + + + +siv(0 to siv'right) <= sov(1 to siv'right) & scan_in; +scan_out <= sov(0); + + + + ex1x_lcb: tri_lcbnd generic map (expand_type => expand_type) port map ( + delay_lclkr => delay_lclkr_dc , + mpw1_b => mpw1_dc_b , + mpw2_b => mpw2_dc_b , + forcee => func_sl_force , + nclk => nclk , + vd => vdd , + gd => gnd , + act => rf1_act_q , + sg => sg_0 , + thold_b => func_sl_thold_0_b , + d1clk => ex1x_d1clk , + d2clk => ex1x_d2clk , + lclk => ex1x_lclk ); + + + ex1_lcb: tri_lcbnd generic map (expand_type => expand_type) port map ( + delay_lclkr => delay_lclkr_dc , + mpw1_b => mpw1_dc_b , + mpw2_b => mpw2_dc_b , + forcee => func_sl_force , + nclk => nclk , + vd => vdd , + gd => gnd , + act => rf1_act_q , + sg => sg_0 , + thold_b => func_sl_thold_0_b , + d1clk => ex1_d1clk , + d2clk => ex1_d2clk , + lclk => ex1_lclk ); + + ex1_slp_lcb: tri_lcbnd generic map (expand_type => expand_type) port map ( + delay_lclkr => delay_lclkr_dc , + mpw1_b => mpw1_dc_b , + mpw2_b => mpw2_dc_b , + forcee => func_slp_sl_force , + nclk => nclk , + vd => vdd , + gd => gnd , + act => rf1_act_q , + sg => sg_0 , + thold_b => func_slp_sl_thold_0_b, + d1clk => ex1_slp_d1clk , + d2clk => ex1_slp_d2clk , + lclk => ex1_slp_lclk ); + + + ex7_lcb: tri_lcbnd generic map (expand_type => expand_type) port map ( + delay_lclkr => delay_lclkr_dc , + mpw1_b => mpw1_dc_b , + mpw2_b => mpw2_dc_b , + forcee => func_sl_force , + nclk => nclk , + vd => vdd , + gd => gnd , + act => exx_act(6) , + sg => sg_0 , + thold_b => func_sl_thold_0_b , + d1clk => ex7_d1clk , + d2clk => ex7_d2clk , + lclk => ex7_lclk ); + + +end architecture xuq_byp_gpr; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_byp_xer.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_byp_xer.vhdl new file mode 100644 index 0000000..4f02f77 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_byp_xer.vhdl @@ -0,0 +1,746 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee,ibm,support,tri,work; +use ieee.std_logic_1164.all; +use ibm.std_ulogic_function_support.all; +use tri.tri_latches_pkg.all; +use support.power_logic_pkg.all; +use work.xuq_pkg.all; + +entity xuq_byp_xer is + generic ( + threads : integer := 4; + expand_type : integer := 2; + regsize : integer := 64); + port ( + nclk : in clk_logic; + + vdd : inout power_logic; + gnd : inout power_logic; + + trace_bus_enable : in std_ulogic; + + d_mode_dc : in std_ulogic; + delay_lclkr_dc : in std_ulogic; + mpw1_dc_b : in std_ulogic; + mpw2_dc_b : in std_ulogic; + func_sl_force : in std_ulogic; + func_sl_thold_0_b : in std_ulogic; + func_slp_sl_force : in std_ulogic; + func_slp_sl_thold_0_b : in std_ulogic; + sg_0 : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + dec_byp_rf1_ca_used : in std_ulogic; + dec_byp_rf1_ov_used : in std_ulogic; + + rf1_tid : in std_ulogic_vector(0 to threads-1); + ex5_tid : in std_ulogic_vector(0 to threads-1); + + dec_byp_ex3_val : in std_ulogic_vector(0 to threads-1); + dec_byp_rf1_byp_val : in std_ulogic_vector(2 to 3); + + xu_ex3_flush : in std_ulogic_vector(0 to threads-1); + xu_ex4_flush : in std_ulogic_vector(0 to threads-1); + xu_ex5_flush : in std_ulogic_vector(0 to threads-1); + + byp_ex5_xer_rt : out std_ulogic_vector(54 to 63); + + alu_ex2_div_done : in std_ulogic; + alu_ex4_mul_done : in std_ulogic; + + alu_byp_ex2_xer : in std_ulogic_vector(0 to 3); + alu_byp_ex5_xer_mul : in std_ulogic_vector(0 to 3); + alu_byp_ex3_xer_div : in std_ulogic_vector(0 to 3); + spr_byp_ex4_is_mtxer : in std_ulogic_vector(0 to threads-1); + byp_ex5_mtcrxer : in std_ulogic_vector(32 to 63); + + byp_xer_si : out std_ulogic_vector(0 to 7*threads-1); + byp_xer_so : out std_ulogic_vector(0 to threads-1); + xer_cr_ex1_xer_ov_in_pipe : out std_ulogic; + xer_cr_ex2_xer_ov_in_pipe : out std_ulogic; + xer_cr_ex3_xer_ov_in_pipe : out std_ulogic; + xer_cr_ex5_xer_ov_in_pipe : out std_ulogic; + byp_dec_rf1_xer_ca : out std_ulogic; + + xer_debug : out std_ulogic_vector(22 to 87) + ); + +-- synopsys translate_off + +-- synopsys translate_on +end xuq_byp_xer; +architecture xuq_byp_xer of xuq_byp_xer is + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + subtype s2 is std_ulogic_vector(0 to 1); + + signal ex2_xer : std_ulogic_vector(0 to 3); + signal ex3_xer : std_ulogic_vector(0 to 3); + signal ex4_xer : std_ulogic_vector(0 to 3); + signal ex5_xer : std_ulogic_vector(0 to 3); + signal ex3_val : std_ulogic_vector(0 to threads-1); + signal ex4_val : std_ulogic_vector(0 to threads-1); + signal ex5_val : std_ulogic_vector(0 to threads-1); + signal xer_out : std_ulogic_vector(0 to 10*threads-1); + signal rf1_byp_val : std_ulogic_vector(4 to 5); + signal rf1_byp_val_ov : std_ulogic_vector(2 to 5); + signal rf1_byp_ov_pri : std_ulogic_vector(2 to 6); + signal rf1_byp_val_ca : std_ulogic_vector(2 to 5); + signal rf1_byp_ca_pri : std_ulogic_vector(2 to 6); + signal xer_ex5_mux : std_ulogic_vector(54 to 63); + signal xer_rf1_mux : std_ulogic_vector(54 to 63); + signal rf1_ov_byp_from_reg : std_ulogic; + signal rf1_ov : std_ulogic; + signal rf1_ca : std_ulogic; + signal rf1_xer_ov_in_pipe : std_ulogic; + + signal ex3_xer_q : std_ulogic_vector(0 to 3); + signal ex4_xer_q : std_ulogic_vector(0 to 3); + signal ex5_xer_q : std_ulogic_vector(0 to 3); + signal ex4_val_q : std_ulogic_vector(0 to threads-1); + signal ex5_val_q : std_ulogic_vector(0 to threads-1); + signal ex1_xer_ov_bypassed_q : std_ulogic; + signal ex2_xer_ov_bypassed_q : std_ulogic; + signal ex3_xer_ov_bypassed_q : std_ulogic; + signal ex4_xer_ov_bypassed_q : std_ulogic; + signal ex5_xer_ov_bypassed_q : std_ulogic; + signal ex1_ov_byp_from_reg_q : std_ulogic; + signal ex2_ov_byp_from_reg_q : std_ulogic; + signal ex3_ov_byp_from_reg_q : std_ulogic; + signal ex4_ov_byp_from_reg_q : std_ulogic; + signal ex5_ov_byp_from_reg_q : std_ulogic; + signal ex1_xer_ov_in_pipe_q : std_ulogic; + signal ex2_xer_ov_in_pipe_q : std_ulogic; + signal ex3_xer_ov_in_pipe_q : std_ulogic; + signal ex4_xer_ov_in_pipe_q : std_ulogic; + signal ex5_xer_ov_in_pipe_q : std_ulogic; + signal ex5_is_mtxer_q : std_ulogic_vector(0 to threads-1); + signal ex3_div_done_q : std_ulogic; + signal ex5_mul_done_q : std_ulogic; + signal debug_q, debug_d : std_ulogic_vector(0 to 31); + + constant ex3_xer_offset : integer := 0; + constant ex4_xer_offset : integer := ex3_xer_offset + ex3_xer_q'length; + constant ex5_xer_offset : integer := ex4_xer_offset + ex4_xer_q'length; + constant ex4_val_offset : integer := ex5_xer_offset + ex5_xer_q'length; + constant ex5_val_offset : integer := ex4_val_offset + ex4_val_q'length; + constant ex1_xer_ov_bypassed_offset : integer := ex5_val_offset + ex5_val_q'length; + constant ex2_xer_ov_bypassed_offset : integer := ex1_xer_ov_bypassed_offset + 1; + constant ex3_xer_ov_bypassed_offset : integer := ex2_xer_ov_bypassed_offset + 1; + constant ex4_xer_ov_bypassed_offset : integer := ex3_xer_ov_bypassed_offset + 1; + constant ex5_xer_ov_bypassed_offset : integer := ex4_xer_ov_bypassed_offset + 1; + constant ex1_ov_byp_from_reg_offset : integer := ex5_xer_ov_bypassed_offset + 1; + constant ex2_ov_byp_from_reg_offset : integer := ex1_ov_byp_from_reg_offset + 1; + constant ex3_ov_byp_from_reg_offset : integer := ex2_ov_byp_from_reg_offset + 1; + constant ex4_ov_byp_from_reg_offset : integer := ex3_ov_byp_from_reg_offset + 1; + constant ex5_ov_byp_from_reg_offset : integer := ex4_ov_byp_from_reg_offset + 1; + constant ex1_xer_ov_in_pipe_offset : integer := ex5_ov_byp_from_reg_offset + 1; + constant ex2_xer_ov_in_pipe_offset : integer := ex1_xer_ov_in_pipe_offset + 1; + constant ex3_xer_ov_in_pipe_offset : integer := ex2_xer_ov_in_pipe_offset + 1; + constant ex4_xer_ov_in_pipe_offset : integer := ex3_xer_ov_in_pipe_offset + 1; + constant ex5_xer_ov_in_pipe_offset : integer := ex4_xer_ov_in_pipe_offset + 1; + constant ex5_is_mtxer_offset : integer := ex5_xer_ov_in_pipe_offset + 1; + constant xer_offset : integer := ex5_is_mtxer_offset + ex5_is_mtxer_q'length; + constant ex3_div_done_offset : integer := xer_offset + 10*threads; + constant ex5_mul_done_offset : integer := ex3_div_done_offset + 1; + constant debug_offset : integer := ex5_mul_done_offset + 1; + constant scan_right : integer := debug_offset + debug_q'length; + signal siv : std_ulogic_vector(0 to scan_right-1); + signal sov : std_ulogic_vector(0 to scan_right-1); +begin + + ex3_val <= dec_byp_ex3_val and not xu_ex3_flush; + ex4_val <= ex4_val_q and not xu_ex4_flush; + ex5_val <= ex5_val_q and not xu_ex5_flush; + + ex2_xer <= alu_byp_ex2_xer; + + with ex3_div_done_q select + ex3_xer <= alu_byp_ex3_xer_div when '1', + ex3_xer_q when others; + + ex4_xer <= ex4_xer_q; + + with ex5_mul_done_q select + ex5_xer <= alu_byp_ex5_xer_mul when '1', + ex5_xer_q when others; + + xer_ex5_mux <= mux_t(xer_out,ex5_tid); + byp_ex5_xer_rt <= (xer_ex5_mux(54) or (ex5_xer_ov_bypassed_q and not ex5_ov_byp_from_reg_q)) & + (xer_ex5_mux(55) or ex5_xer_ov_bypassed_q) & + xer_ex5_mux(56 to 63); + + rf1_byp_val(4) <= '1' when rf1_tid = ex4_val_q else '0'; + rf1_byp_val(5) <= '1' when rf1_tid = ex5_val_q else '0'; + + rf1_byp_val_ov(2) <= ex2_xer(2) and dec_byp_rf1_byp_val(2) and dec_byp_rf1_ov_used; + rf1_byp_val_ov(3) <= ex3_xer(2) and dec_byp_rf1_byp_val(3) and dec_byp_rf1_ov_used; + rf1_byp_val_ov(4) <= ex4_xer(2) and rf1_byp_val(4) and dec_byp_rf1_ov_used; + rf1_byp_val_ov(5) <= ex5_xer(2) and rf1_byp_val(5) and dec_byp_rf1_ov_used; + + rf1_byp_ov_pri(2) <= rf1_byp_val_ov(2); + rf1_byp_ov_pri(3) <= not rf1_byp_val_ov(2) and rf1_byp_val_ov(3); + rf1_byp_ov_pri(4) <= not or_reduce(rf1_byp_val_ov(2 to 3)) and rf1_byp_val_ov(4); + rf1_byp_ov_pri(5) <= not or_reduce(rf1_byp_val_ov(2 to 4)) and rf1_byp_val_ov(5); + rf1_byp_ov_pri(6) <= not or_reduce(rf1_byp_val_ov(2 to 5)); + + rf1_byp_val_ca(2) <= ex2_xer(3) and dec_byp_rf1_byp_val(2) and dec_byp_rf1_ca_used; + rf1_byp_val_ca(3) <= ex3_xer(3) and dec_byp_rf1_byp_val(3) and dec_byp_rf1_ca_used; + rf1_byp_val_ca(4) <= ex4_xer(3) and rf1_byp_val(4) and dec_byp_rf1_ca_used; + rf1_byp_val_ca(5) <= ex5_xer(3) and rf1_byp_val(5) and dec_byp_rf1_ca_used; + + rf1_byp_ca_pri(2) <= rf1_byp_val_ca(2); + rf1_byp_ca_pri(3) <= not rf1_byp_val_ca(2) and rf1_byp_val_ca(3); + rf1_byp_ca_pri(4) <= not or_reduce(rf1_byp_val_ca(2 to 3)) and rf1_byp_val_ca(4); + rf1_byp_ca_pri(5) <= not or_reduce(rf1_byp_val_ca(2 to 4)) and rf1_byp_val_ca(5); + rf1_byp_ca_pri(6) <= not or_reduce(rf1_byp_val_ca(2 to 5)); + + rf1_ov <= (ex2_xer(0) and rf1_byp_ov_pri(2)) or + (ex3_xer(0) and rf1_byp_ov_pri(3)) or + (ex4_xer(0) and rf1_byp_ov_pri(4)) or + (ex5_xer(0) and rf1_byp_ov_pri(5)) or + (xer_rf1_mux(55) and rf1_byp_ov_pri(6)); + + rf1_ca <= (ex2_xer(1) and rf1_byp_ca_pri(2)) or + (ex3_xer(1) and rf1_byp_ca_pri(3)) or + (ex4_xer(1) and rf1_byp_ca_pri(4)) or + (ex5_xer(1) and rf1_byp_ca_pri(5)) or + (xer_rf1_mux(56) and rf1_byp_ca_pri(6)); + + xer_rf1_mux <= mux_t(xer_out,rf1_tid); + rf1_ov_byp_from_reg <= rf1_byp_ov_pri(6); + + xuq_byp_xer_gen : for t in 0 to threads-1 generate + signal xer_d, xer_q : std_ulogic_vector(54 to 63); + signal ex5_mtxer_we : std_ulogic; + signal ex5_ca_we : std_ulogic; + signal ex5_ov_we : std_ulogic; + signal ex5_so_sel : std_ulogic_vector(0 to 2); + signal ex5_ov_sel : std_ulogic_vector(0 to 2); + signal ex5_ca_sel : std_ulogic_vector(0 to 2); + begin + ex5_mtxer_we <= ex5_val(t) and ex5_is_mtxer_q(t); + ex5_ov_we <= ex5_val(t) and ex5_xer(2); + ex5_ca_we <= ex5_val(t) and ex5_xer(3); + + ex5_so_sel(0 to 1) <= ex5_mtxer_we & (ex5_ov_we and ex5_xer(0)); + ex5_so_sel(2) <= not (ex5_so_sel(0) or ex5_so_sel(1)); + + ex5_ov_sel(0 to 1) <= ex5_mtxer_we & ex5_ov_we; + ex5_ov_sel(2) <= not (ex5_ov_sel(0) or ex5_ov_sel(1)); + + ex5_ca_sel(0 to 1) <= ex5_mtxer_we & ex5_ca_we; + ex5_ca_sel(2) <= not (ex5_ca_sel(0) or ex5_ca_sel(1)); + + xer_d(54) <= (byp_ex5_mtcrxer(32) and ex5_so_sel(0)) or + ( ex5_so_sel(1)) or + (xer_q(54) and ex5_so_sel(2)); + xer_d(55) <= (byp_ex5_mtcrxer(33) and ex5_ov_sel(0)) or + (ex5_xer(0) and ex5_ov_sel(1)) or + (xer_q(55) and ex5_ov_sel(2)); + xer_d(56) <= (byp_ex5_mtcrxer(34) and ex5_ca_sel(0)) or + (ex5_xer(1) and ex5_ca_sel(1)) or + (xer_q(56) and ex5_ca_sel(2)); + xer_d(57 to 63) <= byp_ex5_mtcrxer(57 to 63) when ex5_mtxer_we = '1' else + xer_q(57 to 63); + + xer_out(t*10 to t*10+9) <= xer_q; + byp_xer_si(t*7 to t*7+6) <= xer_q(57 to 63); + byp_xer_so(t) <= xer_q(54); + + xer_latch : tri_rlmreg_p + generic map (width => xer_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xer_offset + xer_q'length*t to xer_offset + xer_q'length*(t+1)-1), + scout => sov(xer_offset + xer_q'length*t to xer_offset + xer_q'length*(t+1)-1), + din => xer_d, + dout => xer_q); + end generate; + + byp_dec_rf1_xer_ca <= rf1_ca; + + rf1_xer_ov_in_pipe <= (ex2_xer(0) and ex2_xer(2) and dec_byp_rf1_byp_val(2)) or + (ex3_xer(0) and ex3_xer(2) and dec_byp_rf1_byp_val(3)) or + (ex4_xer(0) and ex4_xer(2) and rf1_byp_val(4) ) or + (ex5_xer(0) and ex5_xer(2) and rf1_byp_val(5) ); + + xer_cr_ex1_xer_ov_in_pipe <= ex1_xer_ov_in_pipe_q; + xer_cr_ex2_xer_ov_in_pipe <= ex2_xer_ov_in_pipe_q; + xer_cr_ex3_xer_ov_in_pipe <= ex3_xer_ov_in_pipe_q; + xer_cr_ex5_xer_ov_in_pipe <= ex5_xer_ov_in_pipe_q; + + mark_unused(xer_rf1_mux(54)); + mark_unused(xer_rf1_mux(57 to 63)); + mark_unused(byp_ex5_mtcrxer(35 to 56)); + + debug_d(0 to 31) <= ex5_val & + dec_byp_rf1_ov_used & + dec_byp_rf1_ca_used & + rf1_byp_ov_pri(2 to 6) & + rf1_byp_ca_pri(2 to 6) & + ex2_xer(0 to 3) & + ex3_xer(0 to 3) & + ex4_xer(0 to 3) & + ex5_xer(0 to 3); + + + xer_debug(22 to 87) <= debug_q & + ex3_div_done_q & + ex5_mul_done_q & + ex5_is_mtxer_q(0 to 3) & + ex1_xer_ov_bypassed_q & + ex2_xer_ov_bypassed_q & + ex3_xer_ov_bypassed_q & + ex4_xer_ov_bypassed_q & + ex5_xer_ov_bypassed_q & + ex1_ov_byp_from_reg_q & + ex2_ov_byp_from_reg_q & + ex3_ov_byp_from_reg_q & + ex4_ov_byp_from_reg_q & + ex5_ov_byp_from_reg_q & + ex1_xer_ov_in_pipe_q & + ex2_xer_ov_in_pipe_q & + ex3_xer_ov_in_pipe_q & + ex4_xer_ov_in_pipe_q & + ex5_xer_ov_in_pipe_q & + xer_out( 7 to 9) & + xer_out(17 to 19) & + xer_out(27 to 29) & + xer_out(37 to 39) & + '0'; + + ex3_xer_latch : tri_rlmreg_p + generic map (width => ex3_xer_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_xer_offset to ex3_xer_offset + ex3_xer_q'length-1), + scout => sov(ex3_xer_offset to ex3_xer_offset + ex3_xer_q'length-1), + din => ex2_xer, + dout => ex3_xer_q); + ex4_xer_latch : tri_rlmreg_p + generic map (width => ex4_xer_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_xer_offset to ex4_xer_offset + ex4_xer_q'length-1), + scout => sov(ex4_xer_offset to ex4_xer_offset + ex4_xer_q'length-1), + din => ex3_xer, + dout => ex4_xer_q); + ex5_xer_latch : tri_rlmreg_p + generic map (width => ex5_xer_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_xer_offset to ex5_xer_offset + ex5_xer_q'length-1), + scout => sov(ex5_xer_offset to ex5_xer_offset + ex5_xer_q'length-1), + din => ex4_xer, + dout => ex5_xer_q); + ex4_val_latch : tri_rlmreg_p + generic map (width => ex4_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_val_offset to ex4_val_offset + ex4_val_q'length-1), + scout => sov(ex4_val_offset to ex4_val_offset + ex4_val_q'length-1), + din => ex3_val, + dout => ex4_val_q); + ex5_val_latch : tri_rlmreg_p + generic map (width => ex5_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_val_offset to ex5_val_offset + ex5_val_q'length-1), + scout => sov(ex5_val_offset to ex5_val_offset + ex5_val_q'length-1), + din => ex4_val, + dout => ex5_val_q); + ex1_xer_ov_bypassed_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_xer_ov_bypassed_offset), + scout => sov(ex1_xer_ov_bypassed_offset), + din => rf1_ov, + dout => ex1_xer_ov_bypassed_q); + ex2_xer_ov_bypassed_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_xer_ov_bypassed_offset), + scout => sov(ex2_xer_ov_bypassed_offset), + din => ex1_xer_ov_bypassed_q, + dout => ex2_xer_ov_bypassed_q); + ex3_xer_ov_bypassed_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_xer_ov_bypassed_offset), + scout => sov(ex3_xer_ov_bypassed_offset), + din => ex2_xer_ov_bypassed_q, + dout => ex3_xer_ov_bypassed_q); + ex4_xer_ov_bypassed_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_xer_ov_bypassed_offset), + scout => sov(ex4_xer_ov_bypassed_offset), + din => ex3_xer_ov_bypassed_q, + dout => ex4_xer_ov_bypassed_q); + ex5_xer_ov_bypassed_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_xer_ov_bypassed_offset), + scout => sov(ex5_xer_ov_bypassed_offset), + din => ex4_xer_ov_bypassed_q, + dout => ex5_xer_ov_bypassed_q); + ex1_ov_byp_from_reg_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_ov_byp_from_reg_offset), + scout => sov(ex1_ov_byp_from_reg_offset), + din => rf1_ov_byp_from_reg, + dout => ex1_ov_byp_from_reg_q); + ex2_ov_byp_from_reg_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_ov_byp_from_reg_offset), + scout => sov(ex2_ov_byp_from_reg_offset), + din => ex1_ov_byp_from_reg_q, + dout => ex2_ov_byp_from_reg_q); + ex3_ov_byp_from_reg_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_ov_byp_from_reg_offset), + scout => sov(ex3_ov_byp_from_reg_offset), + din => ex2_ov_byp_from_reg_q, + dout => ex3_ov_byp_from_reg_q); + ex4_ov_byp_from_reg_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_ov_byp_from_reg_offset), + scout => sov(ex4_ov_byp_from_reg_offset), + din => ex3_ov_byp_from_reg_q, + dout => ex4_ov_byp_from_reg_q); + ex5_ov_byp_from_reg_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_ov_byp_from_reg_offset), + scout => sov(ex5_ov_byp_from_reg_offset), + din => ex4_ov_byp_from_reg_q, + dout => ex5_ov_byp_from_reg_q); + ex1_xer_ov_in_pipe_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_xer_ov_in_pipe_offset), + scout => sov(ex1_xer_ov_in_pipe_offset), + din => rf1_xer_ov_in_pipe, + dout => ex1_xer_ov_in_pipe_q); + ex2_xer_ov_in_pipe_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_xer_ov_in_pipe_offset), + scout => sov(ex2_xer_ov_in_pipe_offset), + din => ex1_xer_ov_in_pipe_q, + dout => ex2_xer_ov_in_pipe_q); + ex3_xer_ov_in_pipe_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_xer_ov_in_pipe_offset), + scout => sov(ex3_xer_ov_in_pipe_offset), + din => ex2_xer_ov_in_pipe_q, + dout => ex3_xer_ov_in_pipe_q); + ex4_xer_ov_in_pipe_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_xer_ov_in_pipe_offset), + scout => sov(ex4_xer_ov_in_pipe_offset), + din => ex3_xer_ov_in_pipe_q, + dout => ex4_xer_ov_in_pipe_q); + ex5_xer_ov_in_pipe_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_xer_ov_in_pipe_offset), + scout => sov(ex5_xer_ov_in_pipe_offset), + din => ex4_xer_ov_in_pipe_q, + dout => ex5_xer_ov_in_pipe_q); + ex5_is_mtxer_latch : tri_rlmreg_p + generic map (width => ex5_is_mtxer_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_is_mtxer_offset to ex5_is_mtxer_offset+ex5_is_mtxer_q'length-1), + scout => sov(ex5_is_mtxer_offset to ex5_is_mtxer_offset+ex5_is_mtxer_q'length-1), + din => spr_byp_ex4_is_mtxer, + dout => ex5_is_mtxer_q); + ex3_div_done_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_div_done_offset), + scout => sov(ex3_div_done_offset), + din => alu_ex2_div_done, + dout => ex3_div_done_q); + ex5_mul_done_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_mul_done_offset), + scout => sov(ex5_mul_done_offset), + din => alu_ex4_mul_done, + dout => ex5_mul_done_q); + debug_latch : tri_rlmreg_p + generic map (width => debug_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(debug_offset to debug_offset + debug_q'length-1), + scout => sov(debug_offset to debug_offset + debug_q'length-1), + din => debug_d, + dout => debug_q); + + siv(0 to siv'right) <= sov(1 to siv'right) & scan_in; + scan_out <= sov(0); + +end architecture xuq_byp_xer; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_cpl.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_cpl.vhdl new file mode 100644 index 0000000..a5aba86 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_cpl.vhdl @@ -0,0 +1,10535 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee,ibm,support,work,tri,clib; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use support.power_logic_pkg.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use tri.tri_latches_pkg.all; +use work.xuq_pkg.all; + +entity xuq_cpl is +generic( + expand_type : integer := 2; + threads : integer := 4; + eff_ifar : integer := 62; + uc_ifar : integer := 21; + regsize : integer := 64; + hvmode : integer := 1; + a2mode : integer := 1); +port( + nclk : in clk_logic; + + ac_tc_debug_trigger : out std_ulogic_vector(0 to threads-1); + + an_ac_scan_dis_dc_b : in std_ulogic; + pc_xu_ccflush_dc : in std_ulogic; + clkoff_dc_b : in std_ulogic; + d_mode_dc : in std_ulogic; + delay_lclkr_dc : in std_ulogic; + mpw1_dc_b : in std_ulogic; + mpw2_dc_b : in std_ulogic; + func_sl_thold_2 : in std_ulogic; + func_nsl_thold_2 : in std_ulogic; + func_slp_sl_thold_2 : in std_ulogic; + func_slp_nsl_thold_2 : in std_ulogic; + cfg_sl_thold_2 : in std_ulogic; + cfg_slp_sl_thold_2 : in std_ulogic; + sg_2 : in std_ulogic; + fce_2 : in std_ulogic; + func_scan_in : in std_ulogic_vector(50 to 53); + func_scan_out : out std_ulogic_vector(50 to 53); + bcfg_scan_in : in std_ulogic; + bcfg_scan_out : out std_ulogic; + ccfg_scan_in : in std_ulogic; + ccfg_scan_out : out std_ulogic; + dcfg_scan_in : in std_ulogic; + dcfg_scan_out : out std_ulogic; + + dec_cpl_rf0_act : in std_ulogic; + dec_cpl_rf0_tid : in std_ulogic_vector(0 to threads-1); + dec_cpl_rf1_val : in std_ulogic_vector(0 to threads-1); + dec_cpl_rf1_issued : in std_ulogic_vector(0 to threads-1); + + dec_cpl_ex2_error : in std_ulogic_vector(0 to 2); + dec_cpl_ex2_match : in std_ulogic; + + fu_xu_rf1_act : in std_ulogic_vector(0 to threads-1); + fu_xu_ex1_ifar : in std_ulogic_vector(0 to eff_ifar*threads-1); + fu_xu_ex2_ifar_issued : in std_ulogic_vector(0 to threads-1); + fu_xu_ex2_ifar_val : in std_ulogic_vector(0 to threads-1); + fu_xu_ex2_instr_type : in std_ulogic_vector(0 to 3*threads-1); + fu_xu_ex2_instr_match : in std_ulogic_vector(0 to threads-1); + fu_xu_ex2_is_ucode : in std_ulogic_vector(0 to threads-1); + + pc_xu_step : in std_ulogic_vector(0 to threads-1); + pc_xu_stop : in std_ulogic_vector(0 to threads-1); + pc_xu_dbg_action : in std_ulogic_vector(0 to 3*threads-1); + pc_xu_force_ude : in std_ulogic_vector(0 to threads-1); + xu_pc_step_done : out std_ulogic_vector(0 to threads-1); + pc_xu_init_reset : in std_ulogic; + + byp_cpl_ex1_cr_bit : in std_ulogic; + + dec_cpl_rf1_pred_taken_cnt : in std_ulogic; + dec_cpl_rf1_instr : in std_ulogic_vector(0 to 31); + dec_cpl_ex3_is_any_store : in std_ulogic; + dec_cpl_ex2_is_any_store_dac : in std_ulogic; + dec_cpl_ex2_is_any_load_dac : in std_ulogic; + dec_cpl_ex3_instr_priv : in std_ulogic; + dec_cpl_ex3_instr_hypv : in std_ulogic; + dec_cpl_ex1_epid_instr : in std_ulogic; + dec_cpl_ex3_tlb_illeg : in std_ulogic; + dec_cpl_ex3_axu_instr_type : in std_ulogic_vector(0 to 2); + dec_cpl_rf1_ucode_val : in std_ulogic_vector(0 to threads-1); + dec_cpl_ex3_mtdp_nr : in std_ulogic; + lsu_xu_ex4_mtdp_cr_status : in std_ulogic; + dec_cpl_ex3_mc_dep_chk_val : in std_ulogic_vector(0 to threads-1); + dec_cpl_ex2_illegal_op : in std_ulogic; + dec_cpl_ex3_mult_coll : in std_ulogic; + fxa_cpl_ex2_div_coll : in std_ulogic_vector(0 to threads-1); + + spr_cpl_ext_interrupt : in std_ulogic_vector(0 to threads-1); + spr_cpl_udec_interrupt : in std_ulogic_vector(0 to threads-1); + spr_cpl_perf_interrupt : in std_ulogic_vector(0 to threads-1); + spr_cpl_dec_interrupt : in std_ulogic_vector(0 to threads-1); + spr_cpl_fit_interrupt : in std_ulogic_vector(0 to threads-1); + spr_cpl_crit_interrupt : in std_ulogic_vector(0 to threads-1); + spr_cpl_wdog_interrupt : in std_ulogic_vector(0 to threads-1); + spr_cpl_dbell_interrupt : in std_ulogic_vector(0 to threads-1); + spr_cpl_cdbell_interrupt : in std_ulogic_vector(0 to threads-1); + spr_cpl_gdbell_interrupt : in std_ulogic_vector(0 to threads-1); + spr_cpl_gcdbell_interrupt : in std_ulogic_vector(0 to threads-1); + spr_cpl_gmcdbell_interrupt : in std_ulogic_vector(0 to threads-1); + + cpl_spr_ex5_dbell_taken : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_cdbell_taken : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_gdbell_taken : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_gcdbell_taken : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_gmcdbell_taken : out std_ulogic_vector(0 to threads-1); + + dec_cpl_rf1_ifar : in std_ulogic_vector(62-eff_ifar to 61); + + spr_cpl_iac1_en : in std_ulogic_vector(0 to threads-1); + spr_cpl_iac2_en : in std_ulogic_vector(0 to threads-1); + spr_cpl_iac3_en : in std_ulogic_vector(0 to threads-1); + spr_cpl_iac4_en : in std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac1r_cmpr_async : in std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac2r_cmpr_async : in std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac1r_cmpr : in std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac2r_cmpr : in std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac3r_cmpr : in std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac4r_cmpr : in std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac1w_cmpr : in std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac2w_cmpr : in std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac3w_cmpr : in std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac4w_cmpr : in std_ulogic_vector(0 to threads-1); + + cpl_spr_ex5_act : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_int : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_gint : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_cint : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_mcint : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_nia : out std_ulogic_vector(0 to eff_ifar*threads-1); + cpl_spr_ex5_esr : out std_ulogic_vector(0 to 17*threads-1); + cpl_spr_ex5_mcsr : out std_ulogic_vector(0 to 15*threads-1); + cpl_spr_ex5_dbsr : out std_ulogic_vector(0 to 19*threads-1); + cpl_spr_ex5_dear_save : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_dear_update_saved : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_dear_update : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_dbsr_update : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_esr_update : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_srr0_dec : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_force_gsrr : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_dbsr_ide : out std_ulogic_vector(0 to threads-1); + spr_cpl_dbsr_ide : in std_ulogic_vector(0 to threads-1); + + alu_cpl_ex1_eff_addr : in std_ulogic_vector(62 to 63); + + mm_xu_local_snoop_reject : in std_ulogic_vector(0 to threads-1); + mm_xu_lru_par_err : in std_ulogic_vector(0 to threads-1); + mm_xu_tlb_par_err : in std_ulogic_vector(0 to threads-1); + mm_xu_tlb_multihit_err : in std_ulogic_vector(0 to threads-1); + lsu_xu_ex3_derat_par_err : in std_ulogic_vector(0 to threads-1); + lsu_xu_ex4_derat_par_err : in std_ulogic_vector(0 to threads-1); + lsu_xu_ex3_derat_multihit_err : in std_ulogic_vector(0 to threads-1); + lsu_xu_ex3_l2_uc_ecc_err : in std_ulogic_vector(0 to threads-1); + lsu_xu_ex3_ddir_par_err : in std_ulogic; + lsu_xu_ex4_n_lsu_ddmh_flush : in std_ulogic_vector(0 to 3); + lsu_xu_ex6_datc_par_err : in std_ulogic; + spr_cpl_external_mchk : in std_ulogic_vector(0 to threads-1); + + xu_pc_err_attention_instr : out std_ulogic_vector(0 to threads-1); + xu_pc_err_nia_miscmpr : out std_ulogic_vector(0 to threads-1); + xu_pc_err_debug_event : out std_ulogic_vector(0 to threads-1); + + lsu_xu_ex3_dsi : in std_ulogic_vector(0 to threads-1); + derat_xu_ex3_dsi : in std_ulogic_vector(0 to threads-1); + spr_cpl_ex3_ct_le : in std_ulogic_vector(0 to threads-1); + spr_cpl_ex3_ct_be : in std_ulogic_vector(0 to threads-1); + + lsu_xu_ex3_align : in std_ulogic_vector(0 to threads-1); + + spr_cpl_ex3_spr_illeg : in std_ulogic; + spr_cpl_ex3_spr_priv : in std_ulogic; + alu_cpl_ex3_trap_val : in std_ulogic; + + spr_cpl_ex3_spr_hypv : in std_logic; + + derat_xu_ex3_miss : in std_ulogic_vector(0 to threads-1); + + dec_cpl_ex2_is_ucode : in std_ulogic; + + pc_xu_ram_mode : in std_ulogic; + pc_xu_ram_thread : in std_ulogic_vector(0 to 1); + pc_xu_ram_execute : in std_ulogic; + xu_iu_ram_issue : out std_ulogic_vector(0 to threads-1); + xu_pc_ram_interrupt : out std_ulogic; + xu_pc_ram_done : out std_ulogic; + pc_xu_ram_flush_thread : in std_ulogic; + + cpl_spr_stop : out std_ulogic_vector(0 to threads-1); + xu_pc_stop_dbg_event : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_instr_cpl : out std_ulogic_vector(0 to threads-1); + spr_cpl_quiesce : in std_ulogic_vector(0 to threads-1); + cpl_spr_quiesce : out std_ulogic_vector(0 to threads-1); + spr_cpl_ex2_run_ctl_flush : in std_ulogic_vector(0 to threads-1); + + mm_xu_illeg_instr : in std_ulogic_vector(0 to threads-1); + mm_xu_tlb_miss : in std_ulogic_vector(0 to threads-1); + mm_xu_pt_fault : in std_ulogic_vector(0 to threads-1); + mm_xu_tlb_inelig : in std_ulogic_vector(0 to threads-1); + mm_xu_lrat_miss : in std_ulogic_vector(0 to threads-1); + mm_xu_hv_priv : in std_ulogic_vector(0 to threads-1); + mm_xu_esr_pt : in std_ulogic_vector(0 to threads-1); + mm_xu_esr_data : in std_ulogic_vector(0 to threads-1); + mm_xu_esr_epid : in std_ulogic_vector(0 to threads-1); + mm_xu_esr_st : in std_ulogic_vector(0 to threads-1); + mm_xu_hold_req : in std_ulogic_vector(0 to threads-1); + mm_xu_hold_done : in std_ulogic_vector(0 to threads-1); + xu_mm_hold_ack : out std_ulogic_vector(0 to threads-1); + mm_xu_eratmiss_done : in std_ulogic_vector(0 to threads-1); + mm_xu_ex3_flush_req : in std_ulogic_vector(0 to threads-1); + + lsu_xu_l2_ecc_err_flush : in std_ulogic_vector(0 to threads-1); + lsu_xu_datc_perr_recovery : in std_ulogic; + lsu_xu_ex3_dep_flush : in std_ulogic; + lsu_xu_ex3_n_flush_req : in std_ulogic; + lsu_xu_ex3_ldq_hit_flush : in std_ulogic; + lsu_xu_ex4_ldq_full_flush : in std_ulogic; + derat_xu_ex3_n_flush_req : in std_ulogic_vector(0 to threads-1); + lsu_xu_ex3_inval_align_2ucode : in std_ulogic; + lsu_xu_ex3_attr : in std_ulogic_vector(0 to 8); + lsu_xu_ex3_derat_vf : in std_ulogic; + + fu_xu_ex3_ap_int_req : in std_ulogic_vector(0 to threads-1); + fu_xu_ex3_trap : in std_ulogic_vector(0 to threads-1); + fu_xu_ex3_n_flush : in std_ulogic_vector(0 to threads-1); + fu_xu_ex3_np1_flush : in std_ulogic_vector(0 to threads-1); + fu_xu_ex3_flush2ucode : in std_ulogic_vector(0 to threads-1); + fu_xu_ex2_async_block : in std_ulogic_vector(0 to threads-1); + + xu_iu_ex5_br_taken : out std_ulogic; + xu_iu_ex5_ifar : out std_ulogic_vector(62-eff_ifar to 61); + xu_iu_flush : out std_ulogic_vector(0 to threads-1); + xu_iu_iu0_flush_ifar : out std_ulogic_vector(0 to eff_ifar*threads-1); + xu_iu_uc_flush_ifar : out std_ulogic_vector(0 to uc_ifar*threads-1); + xu_iu_flush_2ucode : out std_ulogic_vector(0 to threads-1); + xu_iu_flush_2ucode_type : out std_ulogic_vector(0 to threads-1); + xu_iu_ucode_restart : out std_ulogic_vector(0 to threads-1); + xu_iu_ex5_ppc_cpl : out std_ulogic_vector(0 to threads-1); + + xu_rf0_flush : out std_ulogic_vector(0 to threads-1); + xu_rf1_flush : out std_ulogic_vector(0 to threads-1); + xu_ex1_flush : out std_ulogic_vector(0 to threads-1); + xu_ex2_flush : out std_ulogic_vector(0 to threads-1); + xu_ex3_flush : out std_ulogic_vector(0 to threads-1); + xu_ex4_flush : out std_ulogic_vector(0 to threads-1); + xu_ex5_flush : out std_ulogic_vector(0 to threads-1); + + xu_n_is2_flush : out std_ulogic_vector(0 to threads-1); + xu_n_rf0_flush : out std_ulogic_vector(0 to threads-1); + xu_n_rf1_flush : out std_ulogic_vector(0 to threads-1); + xu_n_ex1_flush : out std_ulogic_vector(0 to threads-1); + xu_n_ex2_flush : out std_ulogic_vector(0 to threads-1); + xu_n_ex3_flush : out std_ulogic_vector(0 to threads-1); + xu_n_ex4_flush : out std_ulogic_vector(0 to threads-1); + xu_n_ex5_flush : out std_ulogic_vector(0 to threads-1); + + xu_s_rf1_flush : out std_ulogic_vector(0 to threads-1); + xu_s_ex1_flush : out std_ulogic_vector(0 to threads-1); + xu_s_ex2_flush : out std_ulogic_vector(0 to threads-1); + xu_s_ex3_flush : out std_ulogic_vector(0 to threads-1); + xu_s_ex4_flush : out std_ulogic_vector(0 to threads-1); + xu_s_ex5_flush : out std_ulogic_vector(0 to threads-1); + + xu_w_rf1_flush : out std_ulogic_vector(0 to threads-1); + xu_w_ex1_flush : out std_ulogic_vector(0 to threads-1); + xu_w_ex2_flush : out std_ulogic_vector(0 to threads-1); + xu_w_ex3_flush : out std_ulogic_vector(0 to threads-1); + xu_w_ex4_flush : out std_ulogic_vector(0 to threads-1); + xu_w_ex5_flush : out std_ulogic_vector(0 to threads-1); + + xu_lsu_ex4_val : out std_ulogic_vector(0 to threads-1); + xu_lsu_ex4_flush_local : out std_ulogic_vector(0 to threads-1); + xu_mm_ex4_flush : out std_ulogic_vector(0 to threads-1); + xu_mm_ex5_flush : out std_ulogic_vector(0 to threads-1); + xu_mm_ierat_flush : out std_ulogic_vector(0 to threads-1); + xu_mm_ierat_miss : out std_ulogic_vector(0 to threads-1); + + xu_lsu_ex5_set_barr : out std_ulogic_vector(0 to threads-1); + cpl_fxa_ex5_set_barr : out std_ulogic_vector(0 to threads-1); + cpl_iu_set_barr_tid : out std_ulogic_vector(0 to threads-1); + + cpl_byp_ex3_spr_rt : out std_ulogic_vector(64-regsize to 63); + mux_cpl_ex4_rt : in std_ulogic_vector(64-regsize to 63); + + spr_bit_act : in std_ulogic; + cpl_spr_dbcr0_edm : out std_ulogic_vector(0 to threads-1); + spr_cpl_fp_precise : in std_ulogic_vector(0 to threads-1); + spr_xucr0_mddp : in std_ulogic; + spr_xucr0_mdcp : in std_ulogic; + spr_msr_de : in std_ulogic_vector(0 to threads-1); + spr_msr_spv : in std_ulogic_vector(0 to threads-1); + spr_msr_fp : in std_ulogic_vector(0 to threads-1); + spr_msr_pr : in std_ulogic_vector(0 to threads-1); + spr_msr_gs : in std_ulogic_vector(0 to threads-1); + spr_msr_me : in std_ulogic_vector(0 to threads-1); + spr_msr_cm : in std_ulogic_vector(0 to threads-1); + spr_msr_ucle : in std_ulogic_vector(0 to threads-1); + spr_msrp_uclep : in std_ulogic_vector(0 to threads-1); + spr_ccr2_notlb : in std_ulogic; + spr_ccr2_ucode_dis : in std_ulogic; + spr_ccr2_ap : in std_ulogic_vector(0 to threads-1); + spr_dbcr0_idm : in std_ulogic_vector(0 to threads-1); + spr_dbcr0_icmp : in std_ulogic_vector(0 to threads-1); + spr_dbcr0_brt : in std_ulogic_vector(0 to threads-1); + spr_dbcr0_trap : in std_ulogic_vector(0 to threads-1); + spr_dbcr0_ret : in std_ulogic_vector(0 to threads-1); + spr_dbcr0_irpt : in std_ulogic_vector(0 to threads-1); + spr_dbcr3_ivc : in std_ulogic_vector(0 to threads-1); + spr_epcr_dsigs : in std_ulogic_vector(0 to threads-1); + spr_epcr_isigs : in std_ulogic_vector(0 to threads-1); + spr_epcr_extgs : in std_ulogic_vector(0 to threads-1); + spr_epcr_dtlbgs : in std_ulogic_vector(0 to threads-1); + spr_epcr_itlbgs : in std_ulogic_vector(0 to threads-1); + spr_xucr4_div_barr_thres : out std_ulogic_vector(0 to 7); + spr_ccr0_we : in std_ulogic_vector(0 to threads-1); + spr_dbcr1_iac12m : in std_ulogic_vector(0 to threads-1); + spr_dbcr1_iac34m : in std_ulogic_vector(0 to threads-1); + spr_epcr_duvd : in std_ulogic_vector(0 to threads-1); + spr_xucr0_clkg_ctl : in std_ulogic_vector(2 to 2); + spr_xucr4_mmu_mchk : out std_ulogic; + + cpl_msr_gs : out std_ulogic_vector(0 to threads-1); + cpl_msr_pr : out std_ulogic_vector(0 to threads-1); + cpl_msr_fp : out std_ulogic_vector(0 to threads-1); + cpl_msr_spv : out std_ulogic_vector(0 to threads-1); + cpl_ccr2_ap : out std_ulogic_vector(0 to threads-1); + + mux_cpl_slowspr_flush : in std_ulogic_vector(0 to threads-1); + mux_cpl_slowspr_done : in std_ulogic_vector(0 to threads-1); + dec_cpl_ex1_is_slowspr_wr : in std_ulogic; + dec_cpl_ex3_ddmh_en : in std_ulogic; + dec_cpl_ex3_back_inv : in std_ulogic; + + xu_lsu_ici : out std_ulogic; + xu_lsu_dci : out std_ulogic; + + pc_xu_event_bus_enable : in std_ulogic; + cpl_perf_tx_events : out std_ulogic_vector(0 to 75); + spr_cpl_async_int : in std_ulogic_vector(0 to 3*threads-1); + xu_mm_ex5_perf_itlb : out std_ulogic_vector(0 to threads-1); + xu_mm_ex5_perf_dtlb : out std_ulogic_vector(0 to threads-1); + + spr_cpl_ex3_sprg_ce : in std_ulogic; + spr_cpl_ex3_sprg_ue : in std_ulogic; + iu_xu_ierat_ex2_flush_req : in std_ulogic_vector(0 to threads-1); + iu_xu_ierat_ex3_par_err : in std_ulogic_vector(0 to threads-1); + iu_xu_ierat_ex4_par_err : in std_ulogic_vector(0 to threads-1); + + fu_xu_ex3_regfile_err_det : in std_ulogic_vector(0 to threads-1); + xu_fu_regfile_seq_beg : out std_ulogic; + fu_xu_regfile_seq_end : in std_ulogic; + gpr_cpl_ex3_regfile_err_det : in std_ulogic; + cpl_gpr_regfile_seq_beg : out std_ulogic; + gpr_cpl_regfile_seq_end : in std_ulogic; + xu_pc_err_mcsr_summary : out std_ulogic_vector(0 to threads-1); + xu_pc_err_ditc_overrun : out std_ulogic; + xu_pc_err_local_snoop_reject : out std_ulogic; + xu_pc_err_tlb_lru_parity : out std_ulogic; + xu_pc_err_ext_mchk : out std_ulogic; + xu_pc_err_ierat_multihit : out std_ulogic; + xu_pc_err_derat_multihit : out std_ulogic; + xu_pc_err_tlb_multihit : out std_ulogic; + xu_pc_err_ierat_parity : out std_ulogic; + xu_pc_err_derat_parity : out std_ulogic; + xu_pc_err_tlb_parity : out std_ulogic; + xu_pc_err_mchk_disabled : out std_ulogic; + xu_pc_err_sprg_ue : out std_ulogic_vector(0 to threads-1); + + pc_xu_instr_trace_mode : in std_ulogic; + pc_xu_trace_bus_enable : in std_ulogic; + dec_cpl_rf1_instr_trace_val : in std_ulogic; + dec_cpl_rf1_instr_trace_type : in std_ulogic_vector(0 to 1); + dec_cpl_ex3_instr_trace_val : in std_ulogic; + cpl_dec_in_ucode : out std_ulogic_vector(0 to threads-1); + cpl_debug_mux_ctrls : in std_ulogic_vector(0 to 15); + cpl_debug_data_in : in std_ulogic_vector(0 to 87); + cpl_debug_data_out : out std_ulogic_vector(0 to 87); + cpl_trigger_data_in : in std_ulogic_vector(0 to 11); + cpl_trigger_data_out : out std_ulogic_vector(0 to 11); + fxa_cpl_debug : in std_ulogic_vector(0 to 272); + + vdd : inout power_logic; + gnd : inout power_logic +); + +-- synopsys translate_off + +-- synopsys translate_on +end xuq_cpl; +architecture xuq_cpl of xuq_cpl is + +constant ivos : integer := 26; +constant ifar_repwr : integer := (eff_ifar+2)/8; +constant MSL : integer := 1274; + +constant PREVn : integer := 0; +constant BTAn : integer := 1; +constant DEPn : integer := 2; +constant IMISSn : integer := 3; +constant IMCHKn : integer := 4; +constant DBG0n : integer := 5; +constant ITLBn : integer := 6; +constant ISTORn : integer := 7; +constant ILRATn : integer := 8; +constant FPEn : integer := 9; +constant PROG0n : integer := 10; +constant PROG1n : integer := 11; +constant UNAVAILn : integer := 12; +constant PROG2n : integer := 13; +constant PROG3n : integer := 14; +constant HPRIVn : integer := 15; +constant PROG0An : integer := 16; +constant DMCHKn : integer := 17; +constant DTLBn : integer := 18; +constant DMISSn : integer := 19; +constant DSTORn : integer := 20; +constant ALIGNn : integer := 21; +constant DLRATn : integer := 22; +constant DBG1n : integer := 23; +constant F2Un : integer := 24; +constant FwBSn : integer := 25; +constant Fn : integer := 26; +constant INSTRnp1 : integer := 27; +constant MCHKnp1 : integer := 28; +constant GDBMCHKnp1 : integer := 29; +constant DBG3np1 : integer := 30; +constant CRITnp1 : integer := 31; +constant WDOGnp1 : integer := 32; +constant CDBELLnp1 : integer := 33; +constant GCDBELLnp1 : integer := 34; +constant EXTnp1 : integer := 35; +constant FITnp1 : integer := 36; +constant DECnp1 : integer := 37; +constant DBELLnp1 : integer := 38; +constant GDBELLnp1 : integer := 39; +constant UDECnp1 : integer := 40; +constant PERFnp1 : integer := 41; +constant Fnp1 : integer := 42; +constant TRAP : integer := 0; +constant SC : integer := 1; +constant RFI : integer := 2; +constant FP : integer := 0; +constant AP : integer := 1; +constant VEC : integer := 2; +constant DLK : integer := 0; +constant PT : integer := 1; +constant VF : integer := 2; +constant TLBI : integer := 3; +constant RW : integer := 4; +constant UCT : integer := 5; +constant APENA : integer := 0; +constant FPENA : integer := 1; +type TID_ARR is array (0 to ifar_repwr-1) of std_ulogic_vector(0 to threads-1); +type DAC is array (1 to 4) of std_ulogic_vector(0 to threads-1); +type DAC_A is array (1 to 2) of std_ulogic_vector(0 to threads-1); +type ARY3 is array (0 to threads-1) of std_ulogic_vector(0 to 2); +type ARY4 is array (0 to threads-1) of std_ulogic_vector(0 to 3); +type ARY5 is array (0 to threads-1) of std_ulogic_vector(0 to 4); +type ARY6 is array (0 to threads-1) of std_ulogic_vector(0 to 5); +type ARY7 is array (0 to threads-1) of std_ulogic_vector(0 to 6); +type ARY9 is array (0 to threads-1) of std_ulogic_vector(0 to 8); +type ARY64 is array (0 to threads-1) of std_ulogic_vector(0 to 63); +type ARY_FPRI is array (0 to threads-1) of std_ulogic_vector(0 to Fnp1); +type ARY_IFAR is array (0 to threads-1) of std_ulogic_vector(0 to 61); +type ARY_BLOCK is array (0 to threads-1) of std_ulogic_vector(1 to 7); +subtype IFAR is std_ulogic_vector(62-eff_ifar to 61); +subtype IFAR_UC is std_ulogic_vector(62-uc_ifar to 61); +subtype TID is std_ulogic_vector(0 to threads-1); +signal is2_flush_q : std_ulogic_vector(0 to threads-1); +signal rf0_flush_q : std_ulogic_vector(0 to threads-1); +signal rf1_flush_q : std_ulogic_vector(0 to threads-1); +signal rf1_tid_q : std_ulogic_vector(0 to threads-1); +signal ex1_axu_act_q : std_ulogic_vector(0 to threads-1); +signal ex1_byte_rev_q, rf1_byte_rev : std_ulogic; +signal ex1_flush_q : std_ulogic_vector(0 to threads-1); +signal ex1_is_any_ldstmw_q, rf1_is_any_ldstmw : std_ulogic; +signal ex1_is_attn_q, rf1_is_attn : std_ulogic; +signal ex1_is_dci_q, ex1_is_dci_d : std_ulogic; +signal ex1_is_dlock_q, rf1_is_dlock : std_ulogic; +signal ex1_is_ehpriv_q, rf1_is_ehpriv : std_ulogic; +signal ex1_is_erativax_q, rf1_is_erativax : std_ulogic; +signal ex1_is_ici_q, ex1_is_ici_d : std_ulogic; +signal ex1_is_icswx_q, rf1_is_icswx : std_ulogic; +signal ex1_is_ilock_q, rf1_is_ilock : std_ulogic; +signal ex1_is_isync_q, rf1_is_isync : std_ulogic; +signal ex1_is_mfspr_q, rf1_is_mfspr : std_ulogic; +signal ex1_is_mtmsr_q, rf1_is_mtmsr : std_ulogic; +signal ex1_is_mtspr_q, rf1_is_mtspr : std_ulogic; +signal ex1_is_rfci_q, rf1_is_rfci : std_ulogic; +signal ex1_is_rfgi_q, rf1_is_rfgi : std_ulogic; +signal ex1_is_rfi_q, rf1_is_rfi : std_ulogic; +signal ex1_is_rfmci_q, rf1_is_rfmci : std_ulogic; +signal ex1_is_sc_q, rf1_is_sc : std_ulogic; +signal ex1_is_tlbivax_q, rf1_is_tlbivax : std_ulogic; +signal ex1_is_wrtee_q, rf1_is_wrtee : std_ulogic; +signal ex1_is_wrteei_q, rf1_is_wrteei : std_ulogic; +signal ex1_is_mtxucr0_q, rf1_is_mtxucr0 : std_ulogic; +signal ex1_is_tlbwe_q, rf1_is_tlbwe : std_ulogic; +signal ex1_sc_lev_q, rf1_sc_lev : std_ulogic; +signal ex1_ucode_val_q : std_ulogic_vector(0 to threads-1); +signal ex1_xu_val_q : std_ulogic_vector(0 to threads-1); +signal ex2_axu_act_q : std_ulogic_vector(0 to threads-1); +signal ex2_any_wrtee_q, ex2_any_wrtee_d : std_ulogic; +signal ex2_br_taken_q : std_ulogic; +signal ex2_br_update_q : std_ulogic; +signal ex2_byte_rev_q : std_ulogic; +signal ex2_ctr_dec_update_q : std_ulogic; +signal ex2_epid_instr_q : std_ulogic; +signal ex2_flush_q : std_ulogic_vector(0 to threads-1); +signal ex2_is_attn_q : std_ulogic; +signal ex2_is_dci_q : std_ulogic; +signal ex2_is_dlock_q : std_ulogic; +signal ex2_is_ehpriv_q : std_ulogic; +signal ex2_is_erativax_q : std_ulogic; +signal ex2_is_ici_q : std_ulogic; +signal ex2_is_icswx_q : std_ulogic; +signal ex2_is_ilock_q : std_ulogic; +signal ex2_is_isync_q : std_ulogic; +signal ex2_is_mtmsr_q : std_ulogic; +signal ex2_is_rfci_q : std_ulogic; +signal ex2_is_rfgi_q : std_ulogic; +signal ex2_is_rfi_q : std_ulogic; +signal ex2_is_rfmci_q : std_ulogic; +signal ex2_is_sc_q : std_ulogic; +signal ex2_is_slowspr_wr_q : std_ulogic; +signal ex2_is_tlbivax_q : std_ulogic; +signal ex2_is_tlbwe_q : std_ulogic; +signal ex2_lr_update_q : std_ulogic; +signal ex2_n_align_int_q, ex2_n_align_int_d : std_ulogic; +signal ex2_sc_lev_q : std_ulogic; +signal ex2_taken_bclr_q : std_ulogic; +signal ex2_ucode_val_q : std_ulogic_vector(0 to threads-1); +signal ex2_xu_val_q : std_ulogic_vector(0 to threads-1); +signal ex2_is_mtxucr0_q : std_ulogic; +signal ex3_async_int_block_q, ex3_async_int_block_d : std_ulogic_vector(0 to threads-1); +signal ex3_axu_instr_match_q : std_ulogic_vector(0 to threads-1); +signal ex3_axu_instr_type_q : std_ulogic_vector(0 to 3*threads-1); +signal ex3_axu_is_ucode_q : std_ulogic_vector(0 to threads-1); +signal ex3_axu_val_q : std_ulogic_vector(0 to threads-1); +signal ex3_br_flush_ifar_q : std_ulogic_vector(62-eff_ifar to 61); +signal ex3_br_taken_q : std_ulogic; +signal ex3_br_update_q : std_ulogic; +signal ex3_byte_rev_q : std_ulogic; +signal ex3_ctr_dec_update_q : std_ulogic; +signal ex3_div_coll_q, ex3_div_coll_d : std_ulogic_vector(0 to threads-1); +signal ex3_epid_instr_q : std_ulogic; +signal ex3_flush_q : std_ulogic_vector(0 to threads-1); +signal ex3_ierat_flush_req_q : std_ulogic_vector(0 to threads-1); +signal ex3_illegal_op_q : std_ulogic; +signal ex3_is_any_load_dac_q : std_ulogic; +signal ex3_is_any_store_dac_q : std_ulogic; +signal ex3_is_attn_q : std_ulogic; +signal ex3_is_dci_q : std_ulogic; +signal ex3_is_dlock_q : std_ulogic; +signal ex3_is_ehpriv_q : std_ulogic; +signal ex3_is_ici_q : std_ulogic; +signal ex3_is_icswx_q : std_ulogic; +signal ex3_is_ilock_q : std_ulogic; +signal ex3_is_isync_q : std_ulogic; +signal ex3_is_mtmsr_q : std_ulogic; +signal ex3_is_rfci_q : std_ulogic; +signal ex3_is_rfgi_q : std_ulogic; +signal ex3_is_rfi_q : std_ulogic; +signal ex3_is_rfmci_q : std_ulogic; +signal ex3_is_sc_q : std_ulogic; +signal ex3_is_tlbwe_q : std_ulogic; +signal ex3_is_slowspr_wr_q : std_ulogic; +signal ex3_iu_error_q, ex3_iu_error_d : std_ulogic_vector(1 to 7); +signal ex3_lr_update_q : std_ulogic; +signal ex3_lrat_miss_q : std_ulogic_vector(0 to threads-1); +signal ex3_mmu_esr_data_q : std_ulogic_vector(0 to threads-1); +signal ex3_mmu_esr_epid_q : std_ulogic_vector(0 to threads-1); +signal ex3_mmu_esr_pt_q : std_ulogic_vector(0 to threads-1); +signal ex3_mmu_esr_st_q : std_ulogic_vector(0 to threads-1); +signal ex3_mmu_hv_priv_q : std_ulogic_vector(0 to threads-1); +signal ex3_mtiar_q, ex2_mtiar : std_ulogic; +signal ex3_n_align_int_q : std_ulogic; +signal ex3_n_dcpe_flush_q, ex3_n_dcpe_flush_d : std_ulogic_vector(0 to threads-1); +signal ex3_n_l2_ecc_err_flush_q : std_ulogic_vector(0 to threads-1); +signal ex3_np1_run_ctl_flush_q : std_ulogic_vector(0 to threads-1); +signal ex3_sc_lev_q : std_ulogic; +signal ex3_taken_bclr_q : std_ulogic; +signal ex3_tlb_inelig_q : std_ulogic_vector(0 to threads-1); +signal ex3_tlb_local_snoop_reject_q : std_ulogic_vector(0 to threads-1); +signal ex3_tlb_lru_par_err_q : std_ulogic_vector(0 to threads-1); +signal ex3_tlb_illeg_q : std_ulogic_vector(0 to threads-1); +signal ex3_tlb_miss_q : std_ulogic_vector(0 to threads-1); +signal ex3_tlb_multihit_err_q : std_ulogic_vector(0 to threads-1); +signal ex3_tlb_par_err_q : std_ulogic_vector(0 to threads-1); +signal ex3_tlb_pt_fault_q : std_ulogic_vector(0 to threads-1); +signal ex3_ucode_val_q : std_ulogic_vector(0 to threads-1); +signal ex3_xu_instr_match_q : std_ulogic; +signal ex3_xu_is_ucode_q : std_ulogic; +signal ex3_xu_val_q : std_ulogic_vector(0 to threads-1); +signal ex3_axu_async_block_q : std_ulogic_vector(0 to threads-1); +signal ex3_is_mtxucr0_q : std_ulogic; +signal ex3_np1_instr_flush_q, ex3_np1_instr_flush_d : std_ulogic; +signal ex4_apena_prog_int_q, ex3_n_apena_prog_int : std_ulogic_vector(0 to threads-1); +signal ex4_axu_is_ucode_q : std_ulogic_vector(0 to threads-1); +signal ex4_axu_trap_q : std_ulogic_vector(0 to threads-1); +signal ex4_axu_val_q : std_ulogic_vector(0 to threads-1); +signal ex4_base_int_block_q : std_ulogic_vector(0 to threads-1); +signal ex4_br_flush_ifar_q : std_ulogic_vector(62-eff_ifar to 61); +signal ex4_br_taken_q : std_ulogic; +signal ex4_br_update_q : std_ulogic; +signal ex4_byte_rev_q : std_ulogic; +signal ex4_ctr_dec_update_q : std_ulogic; +signal ex4_debug_flush_en_q, ex4_debug_flush_en_d : std_ulogic_vector(0 to threads-1); +signal ex4_debug_int_en_q, ex3_debug_int_en : std_ulogic_vector(0 to threads-1); +signal ex4_flush_q : std_ulogic_vector(0 to threads-1); +signal ex4_fpena_prog_int_q, ex3_n_fpena_prog_int : std_ulogic_vector(0 to threads-1); +signal ex4_iac1_cmpr_q, ex3_iac1_cmpr : std_ulogic_vector(0 to threads-1); +signal ex4_iac2_cmpr_q, ex3_iac2_cmpr : std_ulogic_vector(0 to threads-1); +signal ex4_iac3_cmpr_q, ex3_iac3_cmpr : std_ulogic_vector(0 to threads-1); +signal ex4_iac4_cmpr_q, ex3_iac4_cmpr : std_ulogic_vector(0 to threads-1); +signal ex4_instr_cpl_q, ex4_instr_cpl_d : std_ulogic_vector(0 to threads-1); +signal ex4_is_any_load_dac_q : std_ulogic; +signal ex4_is_any_store_dac_q : std_ulogic; +signal ex4_is_attn_q : std_ulogic; +signal ex4_is_dci_q : std_ulogic; +signal ex4_is_ehpriv_q : std_ulogic; +signal ex4_is_ici_q : std_ulogic; +signal ex4_is_isync_q : std_ulogic; +signal ex4_is_mtmsr_q : std_ulogic; +signal ex4_is_tlbwe_q : std_ulogic; +signal ex4_is_slowspr_wr_q : std_ulogic; +signal ex4_lr_update_q : std_ulogic; +signal ex4_mcsr_q, ex4_mcsr_d : std_ulogic_vector(0 to 14*threads-1); +signal ex4_mem_attr_q : std_ulogic_vector(lsu_xu_ex3_attr'range); +signal ex4_mmu_esr_data_q : std_ulogic_vector(0 to threads-1); +signal ex4_mmu_esr_epid_q : std_ulogic_vector(0 to threads-1); +signal ex4_mmu_esr_pt_q : std_ulogic_vector(0 to threads-1); +signal ex4_mmu_esr_st_q : std_ulogic_vector(0 to threads-1); +signal ex4_mmu_esr_val_q, ex4_mmu_esr_val_d : std_ulogic_vector(0 to threads-1); +signal ex4_mmu_hold_val_q, ex3_mmu_hold_val : std_ulogic_vector(0 to threads-1); +signal ex4_mtdp_nr_q : std_ulogic; +signal ex4_mtiar_q : std_ulogic; +signal ex4_n_2ucode_flush_q, ex3_n_2ucode_flush : std_ulogic_vector(0 to threads-1); +signal ex4_n_align_int_q, ex3_n_align_int : std_ulogic_vector(0 to threads-1); +signal ex4_n_any_hpriv_int_q, ex4_n_any_hpriv_int_d : std_ulogic_vector(0 to threads-1); +signal ex4_n_any_unavail_int_q, ex3_n_any_unavail_int : std_ulogic_vector(0 to threads-1); +signal ex4_n_ap_unavail_int_q, ex3_n_ap_unavail_int : std_ulogic_vector(0 to threads-1); +signal ex4_n_barr_flush_q, ex3_n_barr_flush : std_ulogic_vector(0 to threads-1); +signal ex4_n_bclr_ta_miscmpr_flush_q,ex3_n_bclr_ta_miscmpr_flush : std_ulogic_vector(0 to threads-1); +signal ex4_n_brt_dbg_cint_q, ex3_n_brt_dbg_cint : std_ulogic_vector(0 to threads-1); +signal ex4_n_dac_dbg_cint_q, ex3_n_dac_dbg_cint : std_ulogic_vector(0 to threads-1); +signal ex4_n_ddmh_mchk_en_q, ex4_n_ddmh_mchk_en_d : std_ulogic_vector(0 to threads-1); +signal ex4_n_dep_flush_q, ex3_n_dep_flush : std_ulogic_vector(0 to threads-1); +signal ex4_n_deratre_par_mchk_mcint_q,ex3_n_deratre_par_mchk_mcint : std_ulogic_vector(0 to threads-1); +signal ex4_n_dlk0_dstor_int_q, ex3_n_dlk0_dstor_int : std_ulogic_vector(0 to threads-1); +signal ex4_n_dlk1_dstor_int_q, ex3_n_dlk1_dstor_int : std_ulogic_vector(0 to threads-1); +signal ex4_n_dlrat_int_q, ex3_n_dlrat_int : std_ulogic_vector(0 to threads-1); +signal ex4_n_dmchk_mcint_q, ex3_n_dmchk_mcint : std_ulogic_vector(0 to threads-1); +signal ex4_n_dmiss_flush_q, ex3_n_dmiss_flush : std_ulogic_vector(0 to threads-1); +signal ex4_n_dstor_int_q, ex3_n_dstor_int : std_ulogic_vector(0 to threads-1); +signal ex4_n_dtlb_int_q, ex3_n_dtlb_int : std_ulogic_vector(0 to threads-1); +signal ex4_n_ena_prog_int_q, ex3_n_ena_prog_int : std_ulogic_vector(0 to threads-1); +signal ex4_n_flush_q, ex3_n_flush : std_ulogic_vector(0 to threads-1); +signal ex4_n_pe_flush_q, ex3_n_pe_flush : std_ulogic_vector(0 to threads-1); +signal ex4_n_tlb_mchk_flush_q, ex3_n_tlb_mchk_flush : std_ulogic_vector(0 to threads-1); +signal ex4_n_fp_unavail_int_q, ex3_n_fp_unavail_int : std_ulogic_vector(0 to threads-1); +signal ex4_n_fu_rfpe_flush_q, ex4_n_fu_rfpe_flush_d : std_ulogic_vector(0 to threads-1); +signal ex4_n_iac_dbg_cint_q, ex3_n_iac_dbg_cint : std_ulogic_vector(0 to threads-1); +signal ex4_n_ieratre_par_mchk_mcint_q,ex3_n_ieratre_par_mchk_mcint : std_ulogic_vector(0 to threads-1); +signal ex4_n_ilrat_int_q, ex3_n_ilrat_int : std_ulogic_vector(0 to threads-1); +signal ex4_n_imchk_mcint_q, ex3_n_imchk_mcint : std_ulogic_vector(0 to threads-1); +signal ex4_n_imiss_flush_q, ex3_n_imiss_flush : std_ulogic_vector(0 to threads-1); +signal ex4_n_instr_dbg_cint_q, ex3_n_instr_dbg_cint : std_ulogic_vector(0 to threads-1); +signal ex4_n_istor_int_q, ex3_n_istor_int : std_ulogic_vector(0 to threads-1); +signal ex4_n_itlb_int_q, ex3_n_itlb_int : std_ulogic_vector(0 to threads-1); +signal ex4_n_ivc_dbg_cint_q, ex3_n_ivc_dbg_cint : std_ulogic_vector(0 to threads-1); +signal ex4_n_ivc_dbg_match_q, ex3_n_ivc_dbg_match : std_ulogic_vector(0 to threads-1); +signal ex4_n_ldq_hit_flush_q, ex3_n_ldq_hit_flush : std_ulogic_vector(0 to threads-1); +signal ex4_n_lsu_ddmh_flush_en_q, ex4_n_lsu_ddmh_flush_en_d : std_ulogic_vector(0 to threads-1); +signal ex4_n_lsu_flush_q, ex3_n_lsu_flush : std_ulogic_vector(0 to threads-1); +signal ex4_n_memattr_miscmpr_flush_q,ex3_n_memattr_miscmpr_flush : std_ulogic_vector(0 to threads-1); +signal ex4_n_mmu_hpriv_int_q, ex3_n_mmu_hpriv_int : std_ulogic_vector(0 to threads-1); +signal ex4_n_pil_prog_int_q, ex3_n_pil_prog_int : std_ulogic_vector(0 to threads-1); +signal ex4_n_ppr_prog_int_q, ex3_n_ppr_prog_int : std_ulogic_vector(0 to threads-1); +signal ex4_n_ptemiss_dlrat_int_q, ex3_n_ptemiss_dlrat_int : std_ulogic_vector(0 to threads-1); +signal ex4_n_puo_prog_int_q, ex3_n_puo_prog_int : std_ulogic_vector(0 to threads-1); +signal ex4_n_ret_dbg_cint_q, ex3_n_ret_dbg_cint : std_ulogic_vector(0 to threads-1); +signal ex4_n_thrctl_stop_flush_q, ex3_n_thrctl_stop_flush : std_ulogic_vector(0 to threads-1); +signal ex4_n_tlbwemiss_dlrat_int_q,ex3_n_tlbwemiss_dlrat_int : std_ulogic_vector(0 to threads-1); +signal ex4_n_tlbwe_pil_prog_int_q,ex3_n_tlbwe_pil_prog_int : std_ulogic_vector(0 to threads-1); +signal ex4_n_trap_dbg_cint_q, ex3_n_trap_dbg_cint : std_ulogic_vector(0 to threads-1); +signal ex4_n_uct_dstor_int_q, ex3_n_uct_dstor_int : std_ulogic_vector(0 to threads-1); +signal ex4_n_vec_unavail_int_q, ex3_n_vec_unavail_int : std_ulogic_vector(0 to threads-1); +signal ex4_n_vf_dstor_int_q, ex3_n_vf_dstor_int : std_ulogic_vector(0 to threads-1); +signal ex4_n_xu_rfpe_flush_q, ex4_n_xu_rfpe_flush_d : std_ulogic_vector(0 to threads-1); +signal ex4_np1_cdbell_cint_q, ex3_np1_cdbell_cint : std_ulogic_vector(0 to threads-1); +signal ex4_np1_crit_cint_q, ex3_np1_crit_cint : std_ulogic_vector(0 to threads-1); +signal ex4_np1_dbell_int_q, ex3_np1_dbell_int : std_ulogic_vector(0 to threads-1); +signal ex4_np1_dec_int_q, ex3_np1_dec_int : std_ulogic_vector(0 to threads-1); +signal ex4_np1_ext_int_q, ex3_np1_ext_int : std_ulogic_vector(0 to threads-1); +signal ex4_np1_ext_mchk_mcint_q, ex3_np1_ext_mchk_mcint : std_ulogic_vector(0 to threads-1); +signal ex4_np1_fit_int_q, ex3_np1_fit_int : std_ulogic_vector(0 to threads-1); +signal ex4_np1_flush_q, ex3_np1_flush : std_ulogic_vector(0 to threads-1); +signal ex4_np1_gcdbell_cint_q, ex3_np1_gcdbell_cint : std_ulogic_vector(0 to threads-1); +signal ex4_np1_gdbell_int_q, ex3_np1_gdbell_int : std_ulogic_vector(0 to threads-1); +signal ex4_np1_gmcdbell_cint_q, ex3_np1_gmcdbell_cint : std_ulogic_vector(0 to threads-1); +signal ex4_np1_ide_dbg_cint_q, ex3_np1_ide_dbg_cint : std_ulogic_vector(0 to threads-1); +signal ex4_np1_instr_int_q, ex3_np1_instr_int : std_ulogic_vector(0 to threads-1); +signal ex4_np1_perf_int_q, ex3_np1_perf_int : std_ulogic_vector(0 to threads-1); +signal ex4_np1_ptr_prog_int_q, ex3_np1_ptr_prog_int : std_ulogic_vector(0 to threads-1); +signal ex4_np1_rfi_q, ex3_np1_rfi : std_ulogic_vector(0 to threads-1); +signal ex4_np1_run_ctl_flush_q, ex3_np1_run_ctl_flush : std_ulogic_vector(0 to threads-1); +signal ex4_np1_sc_int_q, ex3_np1_sc_int : std_ulogic_vector(0 to threads-1); +signal ex4_np1_ude_dbg_cint_q, ex3_np1_ude_dbg_cint : std_ulogic_vector(0 to threads-1); +signal ex4_np1_ude_dbg_event_q, ex3_np1_ude_dbg_event : std_ulogic_vector(0 to threads-1); +signal ex4_np1_udec_int_q, ex3_np1_udec_int : std_ulogic_vector(0 to threads-1); +signal ex4_np1_wdog_cint_q, ex3_np1_wdog_cint : std_ulogic_vector(0 to threads-1); +signal ex4_np1_fu_flush_q, ex3_np1_fu_flush : std_ulogic_vector(0 to threads-1); +signal ex4_n_ieratsx_par_mchk_mcint_q,ex3_n_ieratsx_par_mchk_mcint : std_ulogic_vector(0 to threads-1); +signal ex4_n_tlbmh_mchk_mcint_q : std_ulogic_vector(0 to threads-1); +signal ex4_n_sprg_ue_flush_q : std_ulogic_vector(0 to threads-1); +signal ex4_n_rwaccess_dstor_int_q, ex3_n_rwaccess_dstor_int : std_ulogic_vector(0 to threads-1); +signal ex4_n_exaccess_istor_int_q, ex3_n_exaccess_istor_int : std_ulogic_vector(0 to threads-1); +signal ex4_sc_lev_q : std_ulogic; +signal ex4_siar_sel_q, ex4_siar_sel_d : std_ulogic_vector(0 to 1); +signal ex4_step_q, ex4_step_d : std_ulogic_vector(0 to threads-1); +signal ex4_taken_bclr_q : std_ulogic; +signal ex4_tlb_inelig_q : std_ulogic_vector(0 to threads-1); +signal ex4_ucode_val_q : std_ulogic_vector(0 to threads-1); +signal ex4_xu_is_ucode_q : std_ulogic; +signal ex4_xu_val_q : std_ulogic_vector(0 to threads-1); +signal ex4_cia_act_q, ex3_cia_act : std_ulogic_vector(0 to threads-1); +signal ex4_n_async_dacr_dbg_cint_q, ex3_n_async_dacr_dbg_cint : std_ulogic_vector(0 to threads-1); +signal ex4_dac1r_cmpr_async_q, ex4_dac1r_cmpr_async_d : std_ulogic_vector(0 to threads-1); +signal ex4_dac2r_cmpr_async_q, ex4_dac2r_cmpr_async_d : std_ulogic_vector(0 to threads-1); +signal ex4_thread_stop_q, ex3_thread_stop : std_ulogic_vector(0 to threads-1); +signal ex5_icmp_event_on_int_ok_q, ex4_icmp_event_on_int_ok : std_ulogic_vector(0 to threads-1); +signal ex5_any_val_q : std_ulogic_vector(0 to threads-1); +signal ex5_attn_flush_q, ex4_attn_flush : std_ulogic_vector(0 to threads-1); +signal ex5_axu_trap_pie_q, ex5_axu_trap_pie_d : std_ulogic_vector(0 to threads-1); +signal ex5_br_taken_q : std_ulogic; +signal ex5_cdbell_taken_q, ex5_cdbell_taken_d : std_ulogic_vector(0 to threads-1); +signal ex5_check_bclr_q, ex5_check_bclr_d : std_ulogic_vector(0 to threads-1); +signal ex5_cia_p1_q, ex5_cia_p1_d : std_ulogic_vector(62-eff_ifar to 61); +signal ex5_dbell_taken_q, ex5_dbell_taken_d : std_ulogic_vector(0 to threads-1); +signal ex5_dbsr_update_q, ex4_dbsr_update : std_ulogic_vector(0 to threads-1); +signal ex5_dear_update_saved_q, ex5_dear_update_saved_d : std_ulogic_vector(0 to threads-1); +signal ex5_deratre_par_err_q : std_ulogic_vector(0 to threads-1); +signal ex5_div_set_barr_q, ex5_div_set_barr_d : std_ulogic_vector(0 to threads-1); +signal ex5_dsigs_q, ex5_dsigs_d : std_ulogic_vector(0 to threads-1); +signal ex5_dtlbgs_q, ex5_dtlbgs_d : std_ulogic_vector(0 to threads-1); +signal ex5_err_nia_miscmpr_q, ex5_err_nia_miscmpr_d : std_ulogic_vector(0 to threads-1); +signal ex5_ext_dbg_err_q, ex5_ext_dbg_err_d : std_ulogic_vector(0 to threads-1); +signal ex5_ext_dbg_ext_q, ex5_ext_dbg_ext_d : std_ulogic_vector(0 to threads-1); +signal ex5_extgs_q, ex5_extgs_d : std_ulogic_vector(0 to threads-1); +signal ex5_flush_q : std_ulogic_vector(0 to threads-1); +signal ex5_force_gsrr_q, ex5_force_gsrr_d : std_ulogic_vector(0 to threads-1); +signal ex5_gcdbell_taken_q, ex5_gcdbell_taken_d : std_ulogic_vector(0 to threads-1); +signal ex5_gdbell_taken_q, ex5_gdbell_taken_d : std_ulogic_vector(0 to threads-1); +signal ex5_gmcdbell_taken_q, ex5_gmcdbell_taken_d : std_ulogic_vector(0 to threads-1); +signal ex5_ieratre_par_err_q : std_ulogic_vector(0 to threads-1); +signal ex5_in_ucode_q, ex5_in_ucode_d : std_ulogic_vector(0 to threads-1); +signal ex5_instr_cpl_q, ex4_instr_cpl : std_ulogic_vector(0 to threads-1); +signal ex5_is_any_rfi_q, ex4_is_any_rfi : std_ulogic_vector(0 to threads-1); +signal ex5_is_attn_q, ex5_is_attn_d : std_ulogic_vector(0 to threads-1); +signal ex5_is_crit_int_q : std_ulogic_vector(0 to threads-1); +signal ex5_is_mchk_int_q : std_ulogic_vector(0 to threads-1); +signal ex5_is_mtmsr_q : std_ulogic; +signal ex5_is_isync_q : std_ulogic; +signal ex5_is_tlbwe_q : std_ulogic; +signal ex5_isigs_q, ex5_isigs_d : std_ulogic_vector(0 to threads-1); +signal ex5_itlbgs_q, ex5_itlbgs_d : std_ulogic_vector(0 to threads-1); +signal ex5_lsu_set_barr_q, ex5_lsu_set_barr_d : std_ulogic_vector(0 to threads-1); +signal ex5_mem_attr_val_q, ex4_mem_attr_val : std_ulogic_vector(0 to threads-1); +signal ex5_mmu_hold_val_q : std_ulogic_vector(0 to threads-1); +signal ex5_n_dmiss_flush_q, ex4_n_dmiss_flush : std_ulogic_vector(0 to threads-1); +signal ex5_n_ext_dbg_stopc_flush_q,ex5_n_ext_dbg_stopc_flush_d : std_ulogic; +signal ex5_n_ext_dbg_stopt_flush_q,ex5_n_ext_dbg_stopt_flush_d : std_ulogic_vector(0 to threads-1); +signal ex5_n_imiss_flush_q, ex4_n_imiss_flush : std_ulogic_vector(0 to threads-1); +signal ex5_n_ptemiss_dlrat_int_q : std_ulogic_vector(0 to threads-1); +signal ex5_np1_icmp_dbg_cint_q, ex5_np1_icmp_dbg_cint_d : std_ulogic_vector(0 to threads-1); +signal ex5_np1_icmp_dbg_event_q, ex5_np1_icmp_dbg_event_d : std_ulogic_vector(0 to threads-1); +signal ex5_np1_run_ctl_flush_q, ex4_np1_run_ctl_flush : std_ulogic_vector(0 to threads-1); +signal ex5_dbsr_ide_q, ex5_dbsr_ide_d : std_ulogic_vector(0 to threads-1); +signal ex5_perf_dtlb_q, ex5_perf_dtlb_d : std_ulogic_vector(0 to threads-1); +signal ex5_perf_itlb_q, ex5_perf_itlb_d : std_ulogic_vector(0 to threads-1); +signal ex5_ram_done_q, ex5_ram_done_d : std_ulogic; +signal ex5_ram_issue_q, ex5_ram_issue_d : std_ulogic_vector(0 to threads-1); +signal ex5_rt_q : std_ulogic_vector(64-regsize to 63); +signal ex5_sel_rt_q, ex5_sel_rt_d : std_ulogic_vector(0 to threads-1); +signal ex5_srr0_dec_q, ex5_srr0_dec_d : std_ulogic_vector(0 to threads-1); +signal ex5_tlb_inelig_q : std_ulogic_vector(0 to threads-1); +signal ex5_uc_cia_val_q, ex5_uc_cia_val_d : std_ulogic_vector(0 to threads-1); +signal ex5_xu_ifar_q, ex5_xu_ifar_d : IFAR; +signal ex5_xu_val_q : std_ulogic_vector(0 to threads-1); +signal ex5_n_flush_sprg_ue_flush_q, ex4_n_flush_sprg_ue_flush : std_ulogic_vector(0 to threads-1); +signal ex5_mcsr_act_q : std_ulogic_vector(0 to threads-1); +signal ex6_mcsr_act_q, ex6_mcsr_act_d : std_ulogic; +signal ex6_late_flush_q : std_ulogic_vector(0 to threads-1); +signal ex6_mmu_hold_val_q : std_ulogic_vector(0 to threads-1); +signal ex6_ram_done_q : std_ulogic; +signal ex6_ram_interrupt_q, ex6_ram_interrupt_d : std_ulogic; +signal ex6_ram_issue_q, ex6_ram_issue_d : std_ulogic_vector(0 to threads-1); +signal ex7_ram_issue_q : std_ulogic_vector(0 to threads-1); +signal ex8_ram_issue_q : std_ulogic_vector(0 to threads-1); +signal ex6_set_barr_q, ex6_set_barr_d : std_ulogic_vector(0 to threads-1); +signal ex6_step_done_q, ex5_step_done : std_ulogic_vector(0 to threads-1); +signal ex6_xu_val_q : std_ulogic_vector(0 to threads-1); +signal ex6_is_tlbwe_q : std_ulogic; +signal ex7_is_tlbwe_q, ex7_is_tlbwe_d : std_ulogic_vector(0 to threads-1); +signal ex8_is_tlbwe_q : std_ulogic_vector(0 to threads-1); +signal ccr2_ap_q : std_ulogic_vector(0 to threads-1); +signal cpl_quiesced_q, cpl_quiesced_d : std_ulogic_vector(0 to threads-1); +signal dbcr0_idm_q : std_ulogic_vector(0 to threads-1); +signal dci_val_q, dci_val_d : std_ulogic; +signal debug_event_en_q, debug_event_en_d : std_ulogic_vector(0 to threads-1); +signal derat_hold_present_q, derat_hold_present_d : std_ulogic_vector(0 to threads-1); +signal ext_dbg_act_err_q, ext_dbg_act_err_d : std_ulogic_vector(0 to threads-1); +signal ext_dbg_act_ext_q, ext_dbg_act_ext_d : std_ulogic_vector(0 to threads-1); +signal ext_dbg_stop_core_q, ext_dbg_stop_core_d : std_ulogic_vector(0 to threads-1); +signal ext_dbg_stop_n_q, ext_dbg_stop_n_d : std_ulogic_vector(0 to threads-1); +signal external_mchk_q : std_ulogic_vector(0 to threads-1); +signal exx_instr_async_block_q, exx_instr_async_block_d : ARY_BLOCK; +signal exx_multi_flush_q, exx_multi_flush_d : std_ulogic_vector(0 to threads-1); +signal force_ude_q : std_ulogic_vector(0 to threads-1); +signal fu_rf_seq_end_q : std_ulogic; +signal fu_rfpe_ack_q, fu_rfpe_ack_d : std_ulogic_vector(0 to 1); +signal fu_rfpe_hold_present_q, fu_rfpe_hold_present_d : std_ulogic; +signal ici_hold_present_q, ici_hold_present_d : std_ulogic_vector(0 to 2); +signal ici_val_q, ici_val_d : std_ulogic; +signal ierat_hold_present_q, ierat_hold_present_d : std_ulogic_vector(0 to threads-1); +signal mmu_eratmiss_done_q : std_ulogic_vector(0 to threads-1); +signal mmu_hold_present_q, mmu_hold_present_d : std_ulogic_vector(0 to threads-1); +signal mmu_hold_request_q, mmu_hold_request_d : std_ulogic_vector(0 to threads-1); +signal msr_cm_q : std_ulogic_vector(0 to threads-1); +signal msr_de_q : std_ulogic_vector(0 to threads-1); +signal msr_fp_q : std_ulogic_vector(0 to threads-1); +signal msr_gs_q : std_ulogic_vector(0 to threads-1); +signal msr_me_q : std_ulogic_vector(0 to threads-1); +signal msr_pr_q : std_ulogic_vector(0 to threads-1); +signal msr_spv_q : std_ulogic_vector(0 to threads-1); +signal msr_ucle_q : std_ulogic_vector(0 to threads-1); +signal msrp_uclep_q : std_ulogic_vector(0 to threads-1); +signal pc_dbg_action_q : std_ulogic_vector(0 to 3*threads-1); +signal pc_dbg_stop_q, pc_dbg_stop_d : std_ulogic_vector(0 to threads-1); +signal pc_dbg_stop_2_q, pc_dbg_stop : std_ulogic_vector(0 to threads-1); +signal pc_err_mcsr_rpt_q, pc_err_mcsr_rpt_d : std_ulogic_vector(0 to 10); +signal pc_err_mcsr_summary_q, pc_err_mcsr_summary_d : std_ulogic_vector(0 to threads-1); +signal pc_init_reset_q : std_ulogic; +signal quiesced_q, quiesced_d : std_ulogic; +signal ram_flush_q, ram_flush_d : std_ulogic_vector(0 to threads-1); +signal ram_ip_q, ram_ip_d : std_ulogic_vector(0 to threads-1); +signal ram_mode_q, ram_mode_d : std_ulogic_vector(0 to threads-1); +signal slowspr_flush_q : std_ulogic_vector(0 to threads-1); +signal spr_cpl_async_int_q : std_ulogic_vector(0 to 3*threads-1); +signal ram_execute_q, ram_execute_d : std_ulogic_vector(0 to threads-1); +signal ssprwr_ip_q, ssprwr_ip_d : std_ulogic_vector(0 to threads-1); +signal exx_cm_hold_q : std_ulogic_vector(0 to threads-1); +signal xu_ex1_n_flush_q : std_ulogic_vector(0 to threads-1); +signal xu_ex1_s_flush_q : std_ulogic_vector(0 to threads-1); +signal xu_ex1_w_flush_q : std_ulogic_vector(0 to threads-1); +signal xu_ex2_n_flush_q : std_ulogic_vector(0 to threads-1); +signal xu_ex2_s_flush_q : std_ulogic_vector(0 to threads-1); +signal xu_ex2_w_flush_q : std_ulogic_vector(0 to threads-1); +signal xu_ex3_n_flush_q : std_ulogic_vector(0 to threads-1); +signal xu_ex3_s_flush_q : std_ulogic_vector(0 to threads-1); +signal xu_ex3_w_flush_q : std_ulogic_vector(0 to threads-1); +signal xu_ex4_n_flush_q : std_ulogic_vector(0 to threads-1); +signal xu_ex4_s_flush_q : std_ulogic_vector(0 to threads-1); +signal xu_ex4_w_flush_q : std_ulogic_vector(0 to threads-1); +signal xu_ex5_n_flush_q : std_ulogic_vector(0 to threads-1); +signal xu_ex5_s_flush_q : std_ulogic_vector(0 to threads-1); +signal xu_ex5_w_flush_q : std_ulogic_vector(0 to threads-1); +signal xu_is2_n_flush_q : std_ulogic_vector(0 to threads-1); +signal xu_rf0_n_flush_q : std_ulogic_vector(0 to threads-1); +signal xu_rf1_n_flush_q : std_ulogic_vector(0 to threads-1); +signal xu_rf1_s_flush_q : std_ulogic_vector(0 to threads-1); +signal xu_rf1_w_flush_q : std_ulogic_vector(0 to threads-1); +signal ex5_np1_irpt_dbg_cint_q, ex4_np1_irpt_dbg_cint : std_ulogic_vector(0 to threads-1); +signal ex6_np1_irpt_dbg_cint_q, ex6_np1_irpt_dbg_cint_d : std_ulogic_vector(0 to threads-1); +signal ex5_np1_irpt_dbg_event_q, ex4_np1_irpt_dbg_event : std_ulogic_vector(0 to threads-1); +signal ex6_np1_irpt_dbg_event_q, ex6_np1_irpt_dbg_event_d : std_ulogic_vector(0 to threads-1); +signal clkg_ctl_q : std_ulogic; +signal xu_rf_seq_end_q : std_ulogic; +signal xu_rfpe_ack_q, xu_rfpe_ack_d : std_ulogic_vector(0 to 1); +signal xu_rfpe_hold_present_q, xu_rfpe_hold_present_d : std_ulogic; +signal exx_act_q, exx_act_d : std_ulogic_vector(0 to 4); +signal ex4_mchk_int_en_q, ex3_mchk_int_en : std_ulogic_vector(0 to threads-1); +signal ex5_mchk_int_en_q : std_ulogic_vector(0 to threads-1); +signal trace_bus_enable_q : std_ulogic; +signal ex1_instr_trace_type_q : std_ulogic_vector(0 to 1); +signal ex1_instr_trace_val_q : std_ulogic; +signal ex1_xu_issued_q : std_ulogic_vector(0 to threads-1); +signal ex2_xu_issued_q : std_ulogic_vector(0 to threads-1); +signal ex3_xu_issued_q : std_ulogic_vector(0 to threads-1); +signal ex4_xu_issued_q, ex3_xu_issued : std_ulogic_vector(0 to threads-1); +signal ex3_axu_issued_q : std_ulogic_vector(0 to threads-1); +signal ex4_axu_issued_q : std_ulogic_vector(0 to threads-1); +signal ex2_instr_dbg_q : std_ulogic_vector(0 to 31); +signal ex2_instr_trace_type_q : std_ulogic_vector(0 to 1); +signal ex4_instr_trace_val_q : std_ulogic; +signal ex5_axu_val_dbg_q : std_ulogic_vector(0 to threads-1); +signal ex5_instr_cpl_dbg_q : std_ulogic_vector(0 to threads-1); +signal ex5_instr_trace_val_q : std_ulogic; +signal ex5_siar_q, ex5_siar_d : std_ulogic_vector(62-eff_ifar to 61); +signal ex5_siar_cpl_q, ex5_siar_cpl_d : std_ulogic; +signal ex5_siar_gs_q, ex5_siar_gs_d : std_ulogic; +signal ex5_siar_issued_q, ex5_siar_issued_d : std_ulogic; +signal ex5_siar_pr_q, ex5_siar_pr_d : std_ulogic; +signal ex5_siar_tid_q, ex5_siar_tid_d : std_ulogic_vector(0 to 1); +signal ex5_ucode_end_dbg_q : std_ulogic_vector(0 to threads-1); +signal ex5_ucode_val_dbg_q : std_ulogic_vector(0 to threads-1); +signal instr_trace_mode_q : std_ulogic; +signal debug_data_out_q, debug_data_out_d : std_ulogic_vector(0 to 87); +signal debug_mux_ctrls_q : std_ulogic_vector(0 to 15); +signal debug_mux_ctrls_int_q, debug_mux_ctrls_int : std_ulogic_vector(0 to 15); +signal trigger_data_out_q, trigger_data_out_d : std_ulogic_vector(0 to 11); +signal event_bus_enable_q : std_ulogic; +signal ex2_perf_event_q, ex2_perf_event_d : std_ulogic_vector(0 to 2); +signal ex3_perf_event_q : std_ulogic_vector(0 to 2); +signal ex4_perf_event_q, ex4_perf_event_d : std_ulogic_vector(0 to 3); +signal ex5_perf_event_q, ex5_perf_event_d : std_ulogic_vector(0 to 14*threads-1); +signal spr_bit_act_q : std_ulogic; +signal clk_override_q : std_ulogic; + +signal spare_0_q, spare_0_d : std_ulogic_vector(0 to 15); +signal spare_1_q, spare_1_d : std_ulogic_vector(0 to 15); +signal spare_2_q, spare_2_d : std_ulogic_vector(0 to 15); +signal spare_3_q, spare_3_d : std_ulogic_vector(0 to 15); +signal spare_4_q, spare_4_d : std_ulogic_vector(0 to 7); +signal spare_5_q, spare_5_d : std_ulogic_vector(0 to 3); + +signal ex2_ifar_b_q : std_ulogic_vector(0 to eff_ifar*threads-1); +signal ex3_ifar_q : std_ulogic_vector(0 to eff_ifar*threads-1); +signal ex4_ifar_q : std_ulogic_vector(0 to eff_ifar*threads-1); +signal ex5_nia_b_q : std_ulogic_vector(0 to eff_ifar*threads-1); +signal ex4_epid_instr_q : std_ulogic_vector(0 to threads-1); +signal ex4_is_any_store_q : std_ulogic_vector(0 to threads-1); +signal ex5_flush_2ucode_q, ex5_flush_2ucode_d : std_ulogic_vector(0 to threads-1); +signal ex5_ucode_restart_q, ex5_ucode_restart_d : std_ulogic_vector(0 to threads-1); +signal ex5_mem_attr_le_q, ex5_mem_attr_le_d : std_ulogic_vector(0 to threads-1); +signal ex4_dacr_cmpr_q, ex4_dacr_cmpr_d : DAC; +signal ex4_dacw_cmpr_q, ex4_dacw_cmpr_d : DAC; +signal ex5_late_flush_q, ex5_late_flush_d : TID_ARR; +signal ex5_esr_q, ex5_esr_d : std_ulogic_vector(0 to 17*threads-1); +signal ex5_dbsr_q, ex5_dbsr_d : std_ulogic_vector(0 to 19*threads-1); +signal ex5_mcsr_q, ex5_mcsr_d : std_ulogic_vector(0 to 15*threads-1); +signal dbg_flushcond_q, dbg_flushcond_d : ARY64; + +constant is2_flush_offset : integer := 0; +constant rf0_flush_offset : integer := is2_flush_offset + is2_flush_q'length; +constant rf1_flush_offset : integer := rf0_flush_offset + rf0_flush_q'length; +constant rf1_tid_offset : integer := rf1_flush_offset + rf1_flush_q'length; +constant ex1_axu_act_offset : integer := rf1_tid_offset + rf1_tid_q'length; +constant ex1_byte_rev_offset : integer := ex1_axu_act_offset + ex1_axu_act_q'length; +constant ex1_flush_offset : integer := ex1_byte_rev_offset + 1; +constant ex1_is_any_ldstmw_offset : integer := ex1_flush_offset + ex1_flush_q'length; +constant ex1_is_attn_offset : integer := ex1_is_any_ldstmw_offset + 1; +constant ex1_is_dci_offset : integer := ex1_is_attn_offset + 1; +constant ex1_is_dlock_offset : integer := ex1_is_dci_offset + 1; +constant ex1_is_ehpriv_offset : integer := ex1_is_dlock_offset + 1; +constant ex1_is_erativax_offset : integer := ex1_is_ehpriv_offset + 1; +constant ex1_is_ici_offset : integer := ex1_is_erativax_offset + 1; +constant ex1_is_icswx_offset : integer := ex1_is_ici_offset + 1; +constant ex1_is_ilock_offset : integer := ex1_is_icswx_offset + 1; +constant ex1_is_isync_offset : integer := ex1_is_ilock_offset + 1; +constant ex1_is_mfspr_offset : integer := ex1_is_isync_offset + 1; +constant ex1_is_mtmsr_offset : integer := ex1_is_mfspr_offset + 1; +constant ex1_is_mtspr_offset : integer := ex1_is_mtmsr_offset + 1; +constant ex1_is_rfci_offset : integer := ex1_is_mtspr_offset + 1; +constant ex1_is_rfgi_offset : integer := ex1_is_rfci_offset + 1; +constant ex1_is_rfi_offset : integer := ex1_is_rfgi_offset + 1; +constant ex1_is_rfmci_offset : integer := ex1_is_rfi_offset + 1; +constant ex1_is_sc_offset : integer := ex1_is_rfmci_offset + 1; +constant ex1_is_tlbivax_offset : integer := ex1_is_sc_offset + 1; +constant ex1_is_wrtee_offset : integer := ex1_is_tlbivax_offset + 1; +constant ex1_is_wrteei_offset : integer := ex1_is_wrtee_offset + 1; +constant ex1_is_mtxucr0_offset : integer := ex1_is_wrteei_offset + 1; +constant ex1_is_tlbwe_offset : integer := ex1_is_mtxucr0_offset + 1; +constant ex1_sc_lev_offset : integer := ex1_is_tlbwe_offset + 1; +constant ex1_ucode_val_offset : integer := ex1_sc_lev_offset + 1; +constant ex1_xu_val_offset : integer := ex1_ucode_val_offset + ex1_ucode_val_q'length; +constant ex2_flush_offset : integer := ex1_xu_val_offset + ex1_xu_val_q'length; +constant ex2_ucode_val_offset : integer := ex2_flush_offset + ex2_flush_q'length; +constant ex2_xu_val_offset : integer := ex2_ucode_val_offset + ex2_ucode_val_q'length; +constant ex3_async_int_block_offset : integer := ex2_xu_val_offset + ex2_xu_val_q'length; +constant ex3_axu_instr_match_offset : integer := ex3_async_int_block_offset + ex3_async_int_block_q'length; +constant ex3_axu_instr_type_offset : integer := ex3_axu_instr_match_offset + ex3_axu_instr_match_q'length; +constant ex3_axu_is_ucode_offset : integer := ex3_axu_instr_type_offset + ex3_axu_instr_type_q'length; +constant ex3_axu_val_offset : integer := ex3_axu_is_ucode_offset + ex3_axu_is_ucode_q'length; +constant ex3_br_flush_ifar_offset : integer := ex3_axu_val_offset + ex3_axu_val_q'length; +constant ex3_br_taken_offset : integer := ex3_br_flush_ifar_offset + ex3_br_flush_ifar_q'length; +constant ex3_br_update_offset : integer := ex3_br_taken_offset + 1; +constant ex3_byte_rev_offset : integer := ex3_br_update_offset + 1; +constant ex3_ctr_dec_update_offset : integer := ex3_byte_rev_offset + 1; +constant ex3_div_coll_offset : integer := ex3_ctr_dec_update_offset + 1; +constant ex3_epid_instr_offset : integer := ex3_div_coll_offset + ex3_div_coll_q'length; +constant ex3_flush_offset : integer := ex3_epid_instr_offset + 1; +constant ex3_ierat_flush_req_offset : integer := ex3_flush_offset + ex3_flush_q'length; +constant ex3_illegal_op_offset : integer := ex3_ierat_flush_req_offset + ex3_ierat_flush_req_q'length; +constant ex3_is_any_load_dac_offset : integer := ex3_illegal_op_offset + 1; +constant ex3_is_any_store_dac_offset : integer := ex3_is_any_load_dac_offset + 1; +constant ex3_is_attn_offset : integer := ex3_is_any_store_dac_offset + 1; +constant ex3_is_dci_offset : integer := ex3_is_attn_offset + 1; +constant ex3_is_dlock_offset : integer := ex3_is_dci_offset + 1; +constant ex3_is_ehpriv_offset : integer := ex3_is_dlock_offset + 1; +constant ex3_is_ici_offset : integer := ex3_is_ehpriv_offset + 1; +constant ex3_is_icswx_offset : integer := ex3_is_ici_offset + 1; +constant ex3_is_ilock_offset : integer := ex3_is_icswx_offset + 1; +constant ex3_is_isync_offset : integer := ex3_is_ilock_offset + 1; +constant ex3_is_mtmsr_offset : integer := ex3_is_isync_offset + 1; +constant ex3_is_rfci_offset : integer := ex3_is_mtmsr_offset + 1; +constant ex3_is_rfgi_offset : integer := ex3_is_rfci_offset + 1; +constant ex3_is_rfi_offset : integer := ex3_is_rfgi_offset + 1; +constant ex3_is_rfmci_offset : integer := ex3_is_rfi_offset + 1; +constant ex3_is_sc_offset : integer := ex3_is_rfmci_offset + 1; +constant ex3_is_tlbwe_offset : integer := ex3_is_sc_offset + 1; +constant ex3_is_slowspr_wr_offset : integer := ex3_is_tlbwe_offset + 1; +constant ex3_iu_error_offset : integer := ex3_is_slowspr_wr_offset + 1; +constant ex3_lr_update_offset : integer := ex3_iu_error_offset + ex3_iu_error_q'length; +constant ex3_lrat_miss_offset : integer := ex3_lr_update_offset + 1; +constant ex3_mmu_esr_data_offset : integer := ex3_lrat_miss_offset + ex3_lrat_miss_q'length; +constant ex3_mmu_esr_epid_offset : integer := ex3_mmu_esr_data_offset + ex3_mmu_esr_data_q'length; +constant ex3_mmu_esr_pt_offset : integer := ex3_mmu_esr_epid_offset + ex3_mmu_esr_epid_q'length; +constant ex3_mmu_esr_st_offset : integer := ex3_mmu_esr_pt_offset + ex3_mmu_esr_pt_q'length; +constant ex3_mmu_hv_priv_offset : integer := ex3_mmu_esr_st_offset + ex3_mmu_esr_st_q'length; +constant ex3_mtiar_offset : integer := ex3_mmu_hv_priv_offset + ex3_mmu_hv_priv_q'length; +constant ex3_n_align_int_offset : integer := ex3_mtiar_offset + 1; +constant ex3_n_dcpe_flush_offset : integer := ex3_n_align_int_offset + 1; +constant ex3_n_l2_ecc_err_flush_offset : integer := ex3_n_dcpe_flush_offset + ex3_n_dcpe_flush_q'length; +constant ex3_np1_run_ctl_flush_offset : integer := ex3_n_l2_ecc_err_flush_offset + ex3_n_l2_ecc_err_flush_q'length; +constant ex3_sc_lev_offset : integer := ex3_np1_run_ctl_flush_offset + ex3_np1_run_ctl_flush_q'length; +constant ex3_taken_bclr_offset : integer := ex3_sc_lev_offset + 1; +constant ex3_tlb_inelig_offset : integer := ex3_taken_bclr_offset + 1; +constant ex3_tlb_local_snoop_reject_offset : integer := ex3_tlb_inelig_offset + ex3_tlb_inelig_q'length; +constant ex3_tlb_lru_par_err_offset : integer := ex3_tlb_local_snoop_reject_offset + ex3_tlb_local_snoop_reject_q'length; +constant ex3_tlb_illeg_offset : integer := ex3_tlb_lru_par_err_offset + ex3_tlb_lru_par_err_q'length; +constant ex3_tlb_miss_offset : integer := ex3_tlb_illeg_offset + ex3_tlb_illeg_q'length; +constant ex3_tlb_multihit_err_offset : integer := ex3_tlb_miss_offset + ex3_tlb_miss_q'length; +constant ex3_tlb_par_err_offset : integer := ex3_tlb_multihit_err_offset + ex3_tlb_multihit_err_q'length; +constant ex3_tlb_pt_fault_offset : integer := ex3_tlb_par_err_offset + ex3_tlb_par_err_q'length; +constant ex3_ucode_val_offset : integer := ex3_tlb_pt_fault_offset + ex3_tlb_pt_fault_q'length; +constant ex3_xu_instr_match_offset : integer := ex3_ucode_val_offset + ex3_ucode_val_q'length; +constant ex3_xu_is_ucode_offset : integer := ex3_xu_instr_match_offset + 1; +constant ex3_xu_val_offset : integer := ex3_xu_is_ucode_offset + 1; +constant ex3_axu_async_block_offset : integer := ex3_xu_val_offset + ex3_xu_val_q'length; +constant ex3_is_mtxucr0_offset : integer := ex3_axu_async_block_offset + ex3_axu_async_block_q'length; +constant ex3_np1_instr_flush_offset : integer := ex3_is_mtxucr0_offset + 1; +constant ex4_apena_prog_int_offset : integer := ex3_np1_instr_flush_offset + 1; +constant ex4_axu_is_ucode_offset : integer := ex4_apena_prog_int_offset + ex4_apena_prog_int_q'length; +constant ex4_axu_trap_offset : integer := ex4_axu_is_ucode_offset + ex4_axu_is_ucode_q'length; +constant ex4_axu_val_offset : integer := ex4_axu_trap_offset + ex4_axu_trap_q'length; +constant ex4_base_int_block_offset : integer := ex4_axu_val_offset + ex4_axu_val_q'length; +constant ex4_br_flush_ifar_offset : integer := ex4_base_int_block_offset + ex4_base_int_block_q'length; +constant ex4_br_taken_offset : integer := ex4_br_flush_ifar_offset + ex4_br_flush_ifar_q'length; +constant ex4_br_update_offset : integer := ex4_br_taken_offset + 1; +constant ex4_byte_rev_offset : integer := ex4_br_update_offset + 1; +constant ex4_ctr_dec_update_offset : integer := ex4_byte_rev_offset + 1; +constant ex4_debug_flush_en_offset : integer := ex4_ctr_dec_update_offset + 1; +constant ex4_debug_int_en_offset : integer := ex4_debug_flush_en_offset + ex4_debug_flush_en_q'length; +constant ex4_flush_offset : integer := ex4_debug_int_en_offset + ex4_debug_int_en_q'length; +constant ex4_fpena_prog_int_offset : integer := ex4_flush_offset + ex4_flush_q'length; +constant ex4_iac1_cmpr_offset : integer := ex4_fpena_prog_int_offset + ex4_fpena_prog_int_q'length; +constant ex4_iac2_cmpr_offset : integer := ex4_iac1_cmpr_offset + ex4_iac1_cmpr_q'length; +constant ex4_iac3_cmpr_offset : integer := ex4_iac2_cmpr_offset + ex4_iac2_cmpr_q'length; +constant ex4_iac4_cmpr_offset : integer := ex4_iac3_cmpr_offset + ex4_iac3_cmpr_q'length; +constant ex4_instr_cpl_offset : integer := ex4_iac4_cmpr_offset + ex4_iac4_cmpr_q'length; +constant ex4_is_any_load_dac_offset : integer := ex4_instr_cpl_offset + ex4_instr_cpl_q'length; +constant ex4_is_any_store_dac_offset : integer := ex4_is_any_load_dac_offset + 1; +constant ex4_is_attn_offset : integer := ex4_is_any_store_dac_offset + 1; +constant ex4_is_dci_offset : integer := ex4_is_attn_offset + 1; +constant ex4_is_ehpriv_offset : integer := ex4_is_dci_offset + 1; +constant ex4_is_ici_offset : integer := ex4_is_ehpriv_offset + 1; +constant ex4_is_isync_offset : integer := ex4_is_ici_offset + 1; +constant ex4_is_mtmsr_offset : integer := ex4_is_isync_offset + 1; +constant ex4_is_tlbwe_offset : integer := ex4_is_mtmsr_offset + 1; +constant ex4_is_slowspr_wr_offset : integer := ex4_is_tlbwe_offset + 1; +constant ex4_lr_update_offset : integer := ex4_is_slowspr_wr_offset + 1; +constant ex4_mcsr_offset : integer := ex4_lr_update_offset + 1; +constant ex4_mem_attr_offset : integer := ex4_mcsr_offset + ex4_mcsr_q'length; +constant ex4_mmu_esr_data_offset : integer := ex4_mem_attr_offset + ex4_mem_attr_q'length; +constant ex4_mmu_esr_epid_offset : integer := ex4_mmu_esr_data_offset + ex4_mmu_esr_data_q'length; +constant ex4_mmu_esr_pt_offset : integer := ex4_mmu_esr_epid_offset + ex4_mmu_esr_epid_q'length; +constant ex4_mmu_esr_st_offset : integer := ex4_mmu_esr_pt_offset + ex4_mmu_esr_pt_q'length; +constant ex4_mmu_esr_val_offset : integer := ex4_mmu_esr_st_offset + ex4_mmu_esr_st_q'length; +constant ex4_mmu_hold_val_offset : integer := ex4_mmu_esr_val_offset + ex4_mmu_esr_val_q'length; +constant ex4_mtdp_nr_offset : integer := ex4_mmu_hold_val_offset + ex4_mmu_hold_val_q'length; +constant ex4_mtiar_offset : integer := ex4_mtdp_nr_offset + 1; +constant ex4_n_2ucode_flush_offset : integer := ex4_mtiar_offset + 1; +constant ex4_n_align_int_offset : integer := ex4_n_2ucode_flush_offset + ex4_n_2ucode_flush_q'length; +constant ex4_n_any_hpriv_int_offset : integer := ex4_n_align_int_offset + ex4_n_align_int_q'length; +constant ex4_n_any_unavail_int_offset : integer := ex4_n_any_hpriv_int_offset + ex4_n_any_hpriv_int_q'length; +constant ex4_n_ap_unavail_int_offset : integer := ex4_n_any_unavail_int_offset + ex4_n_any_unavail_int_q'length; +constant ex4_n_barr_flush_offset : integer := ex4_n_ap_unavail_int_offset + ex4_n_ap_unavail_int_q'length; +constant ex4_n_bclr_ta_miscmpr_flush_offset : integer := ex4_n_barr_flush_offset + ex4_n_barr_flush_q'length; +constant ex4_n_brt_dbg_cint_offset : integer := ex4_n_bclr_ta_miscmpr_flush_offset + ex4_n_bclr_ta_miscmpr_flush_q'length; +constant ex4_n_dac_dbg_cint_offset : integer := ex4_n_brt_dbg_cint_offset + ex4_n_brt_dbg_cint_q'length; +constant ex4_n_ddmh_mchk_en_offset : integer := ex4_n_dac_dbg_cint_offset + ex4_n_dac_dbg_cint_q'length; +constant ex4_n_dep_flush_offset : integer := ex4_n_ddmh_mchk_en_offset + ex4_n_ddmh_mchk_en_q'length; +constant ex4_n_deratre_par_mchk_mcint_offset : integer := ex4_n_dep_flush_offset + ex4_n_dep_flush_q'length; +constant ex4_n_dlk0_dstor_int_offset : integer := ex4_n_deratre_par_mchk_mcint_offset + ex4_n_deratre_par_mchk_mcint_q'length; +constant ex4_n_dlk1_dstor_int_offset : integer := ex4_n_dlk0_dstor_int_offset + ex4_n_dlk0_dstor_int_q'length; +constant ex4_n_dlrat_int_offset : integer := ex4_n_dlk1_dstor_int_offset + ex4_n_dlk1_dstor_int_q'length; +constant ex4_n_dmchk_mcint_offset : integer := ex4_n_dlrat_int_offset + ex4_n_dlrat_int_q'length; +constant ex4_n_dmiss_flush_offset : integer := ex4_n_dmchk_mcint_offset + ex4_n_dmchk_mcint_q'length; +constant ex4_n_dstor_int_offset : integer := ex4_n_dmiss_flush_offset + ex4_n_dmiss_flush_q'length; +constant ex4_n_dtlb_int_offset : integer := ex4_n_dstor_int_offset + ex4_n_dstor_int_q'length; +constant ex4_n_ena_prog_int_offset : integer := ex4_n_dtlb_int_offset + ex4_n_dtlb_int_q'length; +constant ex4_n_flush_offset : integer := ex4_n_ena_prog_int_offset + ex4_n_ena_prog_int_q'length; +constant ex4_n_pe_flush_offset : integer := ex4_n_flush_offset + ex4_n_flush_q'length; +constant ex4_n_tlb_mchk_flush_offset : integer := ex4_n_pe_flush_offset + ex4_n_pe_flush_q'length; +constant ex4_n_fp_unavail_int_offset : integer := ex4_n_tlb_mchk_flush_offset + ex4_n_tlb_mchk_flush_q'length; +constant ex4_n_fu_rfpe_flush_offset : integer := ex4_n_fp_unavail_int_offset + ex4_n_fp_unavail_int_q'length; +constant ex4_n_iac_dbg_cint_offset : integer := ex4_n_fu_rfpe_flush_offset + ex4_n_fu_rfpe_flush_q'length; +constant ex4_n_ieratre_par_mchk_mcint_offset : integer := ex4_n_iac_dbg_cint_offset + ex4_n_iac_dbg_cint_q'length; +constant ex4_n_ilrat_int_offset : integer := ex4_n_ieratre_par_mchk_mcint_offset + ex4_n_ieratre_par_mchk_mcint_q'length; +constant ex4_n_imchk_mcint_offset : integer := ex4_n_ilrat_int_offset + ex4_n_ilrat_int_q'length; +constant ex4_n_imiss_flush_offset : integer := ex4_n_imchk_mcint_offset + ex4_n_imchk_mcint_q'length; +constant ex4_n_instr_dbg_cint_offset : integer := ex4_n_imiss_flush_offset + ex4_n_imiss_flush_q'length; +constant ex4_n_istor_int_offset : integer := ex4_n_instr_dbg_cint_offset + ex4_n_instr_dbg_cint_q'length; +constant ex4_n_itlb_int_offset : integer := ex4_n_istor_int_offset + ex4_n_istor_int_q'length; +constant ex4_n_ivc_dbg_cint_offset : integer := ex4_n_itlb_int_offset + ex4_n_itlb_int_q'length; +constant ex4_n_ivc_dbg_match_offset : integer := ex4_n_ivc_dbg_cint_offset + ex4_n_ivc_dbg_cint_q'length; +constant ex4_n_ldq_hit_flush_offset : integer := ex4_n_ivc_dbg_match_offset + ex4_n_ivc_dbg_match_q'length; +constant ex4_n_lsu_ddmh_flush_en_offset : integer := ex4_n_ldq_hit_flush_offset + ex4_n_ldq_hit_flush_q'length; +constant ex4_n_lsu_flush_offset : integer := ex4_n_lsu_ddmh_flush_en_offset + ex4_n_lsu_ddmh_flush_en_q'length; +constant ex4_n_memattr_miscmpr_flush_offset : integer := ex4_n_lsu_flush_offset + ex4_n_lsu_flush_q'length; +constant ex4_n_mmu_hpriv_int_offset : integer := ex4_n_memattr_miscmpr_flush_offset + ex4_n_memattr_miscmpr_flush_q'length; +constant ex4_n_pil_prog_int_offset : integer := ex4_n_mmu_hpriv_int_offset + ex4_n_mmu_hpriv_int_q'length; +constant ex4_n_ppr_prog_int_offset : integer := ex4_n_pil_prog_int_offset + ex4_n_pil_prog_int_q'length; +constant ex4_n_ptemiss_dlrat_int_offset : integer := ex4_n_ppr_prog_int_offset + ex4_n_ppr_prog_int_q'length; +constant ex4_n_puo_prog_int_offset : integer := ex4_n_ptemiss_dlrat_int_offset + ex4_n_ptemiss_dlrat_int_q'length; +constant ex4_n_ret_dbg_cint_offset : integer := ex4_n_puo_prog_int_offset + ex4_n_puo_prog_int_q'length; +constant ex4_n_thrctl_stop_flush_offset : integer := ex4_n_ret_dbg_cint_offset + ex4_n_ret_dbg_cint_q'length; +constant ex4_n_tlbwemiss_dlrat_int_offset : integer := ex4_n_thrctl_stop_flush_offset + ex4_n_thrctl_stop_flush_q'length; +constant ex4_n_tlbwe_pil_prog_int_offset : integer := ex4_n_tlbwemiss_dlrat_int_offset + ex4_n_tlbwemiss_dlrat_int_q'length; +constant ex4_n_trap_dbg_cint_offset : integer := ex4_n_tlbwe_pil_prog_int_offset + ex4_n_tlbwe_pil_prog_int_q'length; +constant ex4_n_uct_dstor_int_offset : integer := ex4_n_trap_dbg_cint_offset + ex4_n_trap_dbg_cint_q'length; +constant ex4_n_vec_unavail_int_offset : integer := ex4_n_uct_dstor_int_offset + ex4_n_uct_dstor_int_q'length; +constant ex4_n_vf_dstor_int_offset : integer := ex4_n_vec_unavail_int_offset + ex4_n_vec_unavail_int_q'length; +constant ex4_n_xu_rfpe_flush_offset : integer := ex4_n_vf_dstor_int_offset + ex4_n_vf_dstor_int_q'length; +constant ex4_np1_cdbell_cint_offset : integer := ex4_n_xu_rfpe_flush_offset + ex4_n_xu_rfpe_flush_q'length; +constant ex4_np1_crit_cint_offset : integer := ex4_np1_cdbell_cint_offset + ex4_np1_cdbell_cint_q'length; +constant ex4_np1_dbell_int_offset : integer := ex4_np1_crit_cint_offset + ex4_np1_crit_cint_q'length; +constant ex4_np1_dec_int_offset : integer := ex4_np1_dbell_int_offset + ex4_np1_dbell_int_q'length; +constant ex4_np1_ext_int_offset : integer := ex4_np1_dec_int_offset + ex4_np1_dec_int_q'length; +constant ex4_np1_ext_mchk_mcint_offset : integer := ex4_np1_ext_int_offset + ex4_np1_ext_int_q'length; +constant ex4_np1_fit_int_offset : integer := ex4_np1_ext_mchk_mcint_offset + ex4_np1_ext_mchk_mcint_q'length; +constant ex4_np1_flush_offset : integer := ex4_np1_fit_int_offset + ex4_np1_fit_int_q'length; +constant ex4_np1_gcdbell_cint_offset : integer := ex4_np1_flush_offset + ex4_np1_flush_q'length; +constant ex4_np1_gdbell_int_offset : integer := ex4_np1_gcdbell_cint_offset + ex4_np1_gcdbell_cint_q'length; +constant ex4_np1_gmcdbell_cint_offset : integer := ex4_np1_gdbell_int_offset + ex4_np1_gdbell_int_q'length; +constant ex4_np1_ide_dbg_cint_offset : integer := ex4_np1_gmcdbell_cint_offset + ex4_np1_gmcdbell_cint_q'length; +constant ex4_np1_instr_int_offset : integer := ex4_np1_ide_dbg_cint_offset + ex4_np1_ide_dbg_cint_q'length; +constant ex4_np1_perf_int_offset : integer := ex4_np1_instr_int_offset + ex4_np1_instr_int_q'length; +constant ex4_np1_ptr_prog_int_offset : integer := ex4_np1_perf_int_offset + ex4_np1_perf_int_q'length; +constant ex4_np1_rfi_offset : integer := ex4_np1_ptr_prog_int_offset + ex4_np1_ptr_prog_int_q'length; +constant ex4_np1_run_ctl_flush_offset : integer := ex4_np1_rfi_offset + ex4_np1_rfi_q'length; +constant ex4_np1_sc_int_offset : integer := ex4_np1_run_ctl_flush_offset + ex4_np1_run_ctl_flush_q'length; +constant ex4_np1_ude_dbg_cint_offset : integer := ex4_np1_sc_int_offset + ex4_np1_sc_int_q'length; +constant ex4_np1_ude_dbg_event_offset : integer := ex4_np1_ude_dbg_cint_offset + ex4_np1_ude_dbg_cint_q'length; +constant ex4_np1_udec_int_offset : integer := ex4_np1_ude_dbg_event_offset + ex4_np1_ude_dbg_event_q'length; +constant ex4_np1_wdog_cint_offset : integer := ex4_np1_udec_int_offset + ex4_np1_udec_int_q'length; +constant ex4_np1_fu_flush_offset : integer := ex4_np1_wdog_cint_offset + ex4_np1_wdog_cint_q'length; +constant ex4_n_ieratsx_par_mchk_mcint_offset : integer := ex4_np1_fu_flush_offset + ex4_np1_fu_flush_q'length; +constant ex4_n_tlbmh_mchk_mcint_offset : integer := ex4_n_ieratsx_par_mchk_mcint_offset + ex4_n_ieratsx_par_mchk_mcint_q'length; +constant ex4_n_sprg_ue_flush_offset : integer := ex4_n_tlbmh_mchk_mcint_offset + ex4_n_tlbmh_mchk_mcint_q'length; +constant ex4_n_rwaccess_dstor_int_offset : integer := ex4_n_sprg_ue_flush_offset + ex4_n_sprg_ue_flush_q'length; +constant ex4_n_exaccess_istor_int_offset : integer := ex4_n_rwaccess_dstor_int_offset + ex4_n_rwaccess_dstor_int_q'length; +constant ex4_sc_lev_offset : integer := ex4_n_exaccess_istor_int_offset + ex4_n_exaccess_istor_int_q'length; +constant ex4_siar_sel_offset : integer := ex4_sc_lev_offset + 1; +constant ex4_step_offset : integer := ex4_siar_sel_offset + ex4_siar_sel_q'length; +constant ex4_taken_bclr_offset : integer := ex4_step_offset + ex4_step_q'length; +constant ex4_tlb_inelig_offset : integer := ex4_taken_bclr_offset + 1; +constant ex4_ucode_val_offset : integer := ex4_tlb_inelig_offset + ex4_tlb_inelig_q'length; +constant ex4_xu_is_ucode_offset : integer := ex4_ucode_val_offset + ex4_ucode_val_q'length; +constant ex4_xu_val_offset : integer := ex4_xu_is_ucode_offset + 1; +constant ex4_cia_act_offset : integer := ex4_xu_val_offset + ex4_xu_val_q'length; +constant ex4_n_async_dacr_dbg_cint_offset : integer := ex4_cia_act_offset + ex4_cia_act_q'length; +constant ex4_dac1r_cmpr_async_offset : integer := ex4_n_async_dacr_dbg_cint_offset + ex4_n_async_dacr_dbg_cint_q'length; +constant ex4_dac2r_cmpr_async_offset : integer := ex4_dac1r_cmpr_async_offset + ex4_dac1r_cmpr_async_q'length; +constant ex4_thread_stop_offset : integer := ex4_dac2r_cmpr_async_offset + ex4_dac2r_cmpr_async_q'length; +constant ex5_icmp_event_on_int_ok_offset : integer := ex4_thread_stop_offset + ex4_thread_stop_q'length; +constant ex5_any_val_offset : integer := ex5_icmp_event_on_int_ok_offset + ex5_icmp_event_on_int_ok_q'length; +constant ex5_attn_flush_offset : integer := ex5_any_val_offset + ex5_any_val_q'length; +constant ex5_axu_trap_pie_offset : integer := ex5_attn_flush_offset + ex5_attn_flush_q'length; +constant ex5_br_taken_offset : integer := ex5_axu_trap_pie_offset + ex5_axu_trap_pie_q'length; +constant ex5_cdbell_taken_offset : integer := ex5_br_taken_offset + 1; +constant ex5_check_bclr_offset : integer := ex5_cdbell_taken_offset + ex5_cdbell_taken_q'length; +constant ex5_cia_p1_offset : integer := ex5_check_bclr_offset + ex5_check_bclr_q'length; +constant ex5_dbell_taken_offset : integer := ex5_cia_p1_offset + ex5_cia_p1_q'length; +constant ex5_dbsr_update_offset : integer := ex5_dbell_taken_offset + ex5_dbell_taken_q'length; +constant ex5_dear_update_saved_offset : integer := ex5_dbsr_update_offset + ex5_dbsr_update_q'length; +constant ex5_deratre_par_err_offset : integer := ex5_dear_update_saved_offset + ex5_dear_update_saved_q'length; +constant ex5_div_set_barr_offset : integer := ex5_deratre_par_err_offset + ex5_deratre_par_err_q'length; +constant ex5_dsigs_offset : integer := ex5_div_set_barr_offset + ex5_div_set_barr_q'length; +constant ex5_dtlbgs_offset : integer := ex5_dsigs_offset + ex5_dsigs_q'length; +constant ex5_err_nia_miscmpr_offset : integer := ex5_dtlbgs_offset + ex5_dtlbgs_q'length; +constant ex5_ext_dbg_err_offset : integer := ex5_err_nia_miscmpr_offset + ex5_err_nia_miscmpr_q'length; +constant ex5_ext_dbg_ext_offset : integer := ex5_ext_dbg_err_offset + ex5_ext_dbg_err_q'length; +constant ex5_extgs_offset : integer := ex5_ext_dbg_ext_offset + ex5_ext_dbg_ext_q'length; +constant ex5_flush_offset : integer := ex5_extgs_offset + ex5_extgs_q'length; +constant ex5_force_gsrr_offset : integer := ex5_flush_offset + ex5_flush_q'length; +constant ex5_gcdbell_taken_offset : integer := ex5_force_gsrr_offset + ex5_force_gsrr_q'length; +constant ex5_gdbell_taken_offset : integer := ex5_gcdbell_taken_offset + ex5_gcdbell_taken_q'length; +constant ex5_gmcdbell_taken_offset : integer := ex5_gdbell_taken_offset + ex5_gdbell_taken_q'length; +constant ex5_ieratre_par_err_offset : integer := ex5_gmcdbell_taken_offset + ex5_gmcdbell_taken_q'length; +constant ex5_in_ucode_offset : integer := ex5_ieratre_par_err_offset + ex5_ieratre_par_err_q'length; +constant ex5_instr_cpl_offset : integer := ex5_in_ucode_offset + ex5_in_ucode_q'length; +constant ex5_is_any_rfi_offset : integer := ex5_instr_cpl_offset + ex5_instr_cpl_q'length; +constant ex5_is_attn_offset : integer := ex5_is_any_rfi_offset + ex5_is_any_rfi_q'length; +constant ex5_is_crit_int_offset : integer := ex5_is_attn_offset + ex5_is_attn_q'length; +constant ex5_is_mchk_int_offset : integer := ex5_is_crit_int_offset + ex5_is_crit_int_q'length; +constant ex5_is_mtmsr_offset : integer := ex5_is_mchk_int_offset + ex5_is_mchk_int_q'length; +constant ex5_is_isync_offset : integer := ex5_is_mtmsr_offset + 1; +constant ex5_is_tlbwe_offset : integer := ex5_is_isync_offset + 1; +constant ex5_isigs_offset : integer := ex5_is_tlbwe_offset + 1; +constant ex5_itlbgs_offset : integer := ex5_isigs_offset + ex5_isigs_q'length; +constant ex5_lsu_set_barr_offset : integer := ex5_itlbgs_offset + ex5_itlbgs_q'length; +constant ex5_mem_attr_val_offset : integer := ex5_lsu_set_barr_offset + ex5_lsu_set_barr_q'length; +constant ex5_mmu_hold_val_offset : integer := ex5_mem_attr_val_offset + ex5_mem_attr_val_q'length; +constant ex5_n_dmiss_flush_offset : integer := ex5_mmu_hold_val_offset + ex5_mmu_hold_val_q'length; +constant ex5_n_ext_dbg_stopc_flush_offset : integer := ex5_n_dmiss_flush_offset + ex5_n_dmiss_flush_q'length; +constant ex5_n_ext_dbg_stopt_flush_offset : integer := ex5_n_ext_dbg_stopc_flush_offset + 1; +constant ex5_n_imiss_flush_offset : integer := ex5_n_ext_dbg_stopt_flush_offset + ex5_n_ext_dbg_stopt_flush_q'length; +constant ex5_n_ptemiss_dlrat_int_offset : integer := ex5_n_imiss_flush_offset + ex5_n_imiss_flush_q'length; +constant ex5_np1_icmp_dbg_cint_offset : integer := ex5_n_ptemiss_dlrat_int_offset + ex5_n_ptemiss_dlrat_int_q'length; +constant ex5_np1_icmp_dbg_event_offset : integer := ex5_np1_icmp_dbg_cint_offset + ex5_np1_icmp_dbg_cint_q'length; +constant ex5_np1_run_ctl_flush_offset : integer := ex5_np1_icmp_dbg_event_offset + ex5_np1_icmp_dbg_event_q'length; +constant ex5_dbsr_ide_offset : integer := ex5_np1_run_ctl_flush_offset + ex5_np1_run_ctl_flush_q'length; +constant ex5_perf_dtlb_offset : integer := ex5_dbsr_ide_offset + ex5_dbsr_ide_q'length; +constant ex5_perf_itlb_offset : integer := ex5_perf_dtlb_offset + ex5_perf_dtlb_q'length; +constant ex5_ram_done_offset : integer := ex5_perf_itlb_offset + ex5_perf_itlb_q'length; +constant ex5_ram_issue_offset : integer := ex5_ram_done_offset + 1; +constant ex5_rt_offset : integer := ex5_ram_issue_offset + ex5_ram_issue_q'length; +constant ex5_sel_rt_offset : integer := ex5_rt_offset + ex5_rt_q'length; +constant ex5_srr0_dec_offset : integer := ex5_sel_rt_offset + ex5_sel_rt_q'length; +constant ex5_tlb_inelig_offset : integer := ex5_srr0_dec_offset + ex5_srr0_dec_q'length; +constant ex5_uc_cia_val_offset : integer := ex5_tlb_inelig_offset + ex5_tlb_inelig_q'length; +constant ex5_xu_ifar_offset : integer := ex5_uc_cia_val_offset + ex5_uc_cia_val_q'length; +constant ex5_xu_val_offset : integer := ex5_xu_ifar_offset + ex5_xu_ifar_q'length; +constant ex5_n_flush_sprg_ue_flush_offset : integer := ex5_xu_val_offset + ex5_xu_val_q'length; +constant ex5_mcsr_act_offset : integer := ex5_n_flush_sprg_ue_flush_offset + ex5_n_flush_sprg_ue_flush_q'length; +constant ex6_mcsr_act_offset : integer := ex5_mcsr_act_offset + ex5_mcsr_act_q'length; +constant ex6_ram_done_offset : integer := ex6_mcsr_act_offset + 1; +constant ex6_ram_interrupt_offset : integer := ex6_ram_done_offset + 1; +constant ex6_ram_issue_offset : integer := ex6_ram_interrupt_offset + 1; +constant ex7_ram_issue_offset : integer := ex6_ram_issue_offset + ex6_ram_issue_q'length; +constant ex8_ram_issue_offset : integer := ex7_ram_issue_offset + ex7_ram_issue_q'length; +constant ex6_step_done_offset : integer := ex8_ram_issue_offset + ex8_ram_issue_q'length; +constant ex6_xu_val_offset : integer := ex6_step_done_offset + ex6_step_done_q'length; +constant ex7_is_tlbwe_offset : integer := ex6_xu_val_offset + ex6_xu_val_q'length; +constant ex8_is_tlbwe_offset : integer := ex7_is_tlbwe_offset + ex7_is_tlbwe_q'length; +constant ccr2_ap_offset : integer := ex8_is_tlbwe_offset + ex8_is_tlbwe_q'length; +constant cpl_quiesced_offset : integer := ccr2_ap_offset + ccr2_ap_q'length; +constant dbcr0_idm_offset : integer := cpl_quiesced_offset + cpl_quiesced_q'length; +constant dci_val_offset : integer := dbcr0_idm_offset + dbcr0_idm_q'length; +constant debug_event_en_offset : integer := dci_val_offset + 1; +constant derat_hold_present_offset : integer := debug_event_en_offset + debug_event_en_q'length; +constant ext_dbg_act_err_offset : integer := derat_hold_present_offset + derat_hold_present_q'length; +constant ext_dbg_act_ext_offset : integer := ext_dbg_act_err_offset + ext_dbg_act_err_q'length; +constant ext_dbg_stop_core_offset : integer := ext_dbg_act_ext_offset + ext_dbg_act_ext_q'length; +constant ext_dbg_stop_n_offset : integer := ext_dbg_stop_core_offset + ext_dbg_stop_core_q'length; +constant external_mchk_offset : integer := ext_dbg_stop_n_offset + ext_dbg_stop_n_q'length; +constant exx_multi_flush_offset : integer := external_mchk_offset + external_mchk_q'length; +constant force_ude_offset : integer := exx_multi_flush_offset + exx_multi_flush_q'length; +constant fu_rf_seq_end_offset : integer := force_ude_offset + force_ude_q'length; +constant fu_rfpe_ack_offset : integer := fu_rf_seq_end_offset + 1; +constant fu_rfpe_hold_present_offset : integer := fu_rfpe_ack_offset + fu_rfpe_ack_q'length; +constant ici_hold_present_offset : integer := fu_rfpe_hold_present_offset + 1; +constant ici_val_offset : integer := ici_hold_present_offset + ici_hold_present_q'length; +constant ierat_hold_present_offset : integer := ici_val_offset + 1; +constant mmu_eratmiss_done_offset : integer := ierat_hold_present_offset + ierat_hold_present_q'length; +constant mmu_hold_present_offset : integer := mmu_eratmiss_done_offset + mmu_eratmiss_done_q'length; +constant mmu_hold_request_offset : integer := mmu_hold_present_offset + mmu_hold_present_q'length; +constant msr_cm_offset : integer := mmu_hold_request_offset + mmu_hold_request_q'length; +constant msr_de_offset : integer := msr_cm_offset + msr_cm_q'length; +constant msr_fp_offset : integer := msr_de_offset + msr_de_q'length; +constant msr_gs_offset : integer := msr_fp_offset + msr_fp_q'length; +constant msr_me_offset : integer := msr_gs_offset + msr_gs_q'length; +constant msr_pr_offset : integer := msr_me_offset + msr_me_q'length; +constant msr_spv_offset : integer := msr_pr_offset + msr_pr_q'length; +constant msr_ucle_offset : integer := msr_spv_offset + msr_spv_q'length; +constant msrp_uclep_offset : integer := msr_ucle_offset + msr_ucle_q'length; +constant pc_dbg_action_offset : integer := msrp_uclep_offset + msrp_uclep_q'length; +constant pc_dbg_stop_offset : integer := pc_dbg_action_offset + pc_dbg_action_q'length; +constant pc_dbg_stop_2_offset : integer := pc_dbg_stop_offset + pc_dbg_stop_q'length; +constant pc_err_mcsr_rpt_offset : integer := pc_dbg_stop_2_offset + pc_dbg_stop_2_q'length; +constant pc_err_mcsr_summary_offset : integer := pc_err_mcsr_rpt_offset + pc_err_mcsr_rpt_q'length; +constant pc_init_reset_offset : integer := pc_err_mcsr_summary_offset + pc_err_mcsr_summary_q'length; +constant quiesced_offset : integer := pc_init_reset_offset + 1; +constant ram_flush_offset : integer := quiesced_offset + 1; +constant ram_ip_offset : integer := ram_flush_offset + ram_flush_q'length; +constant ram_mode_offset : integer := ram_ip_offset + ram_ip_q'length; +constant slowspr_flush_offset : integer := ram_mode_offset + ram_mode_q'length; +constant spr_cpl_async_int_offset : integer := slowspr_flush_offset + slowspr_flush_q'length; +constant ram_execute_offset : integer := spr_cpl_async_int_offset + spr_cpl_async_int_q'length; +constant ssprwr_ip_offset : integer := ram_execute_offset + ram_execute_q'length; +constant exx_cm_hold_offset : integer := ssprwr_ip_offset + ssprwr_ip_q'length; +constant xu_ex1_n_flush_offset : integer := exx_cm_hold_offset + exx_cm_hold_q'length; +constant xu_ex1_s_flush_offset : integer := xu_ex1_n_flush_offset + xu_ex1_n_flush_q'length; +constant xu_ex1_w_flush_offset : integer := xu_ex1_s_flush_offset + xu_ex1_s_flush_q'length; +constant xu_ex2_n_flush_offset : integer := xu_ex1_w_flush_offset + xu_ex1_w_flush_q'length; +constant xu_ex2_s_flush_offset : integer := xu_ex2_n_flush_offset + xu_ex2_n_flush_q'length; +constant xu_ex2_w_flush_offset : integer := xu_ex2_s_flush_offset + xu_ex2_s_flush_q'length; +constant xu_ex3_n_flush_offset : integer := xu_ex2_w_flush_offset + xu_ex2_w_flush_q'length; +constant xu_ex3_s_flush_offset : integer := xu_ex3_n_flush_offset + xu_ex3_n_flush_q'length; +constant xu_ex3_w_flush_offset : integer := xu_ex3_s_flush_offset + xu_ex3_s_flush_q'length; +constant xu_ex4_n_flush_offset : integer := xu_ex3_w_flush_offset + xu_ex3_w_flush_q'length; +constant xu_ex4_s_flush_offset : integer := xu_ex4_n_flush_offset + xu_ex4_n_flush_q'length; +constant xu_ex4_w_flush_offset : integer := xu_ex4_s_flush_offset + xu_ex4_s_flush_q'length; +constant xu_ex5_n_flush_offset : integer := xu_ex4_w_flush_offset + xu_ex4_w_flush_q'length; +constant xu_ex5_s_flush_offset : integer := xu_ex5_n_flush_offset + xu_ex5_n_flush_q'length; +constant xu_ex5_w_flush_offset : integer := xu_ex5_s_flush_offset + xu_ex5_s_flush_q'length; +constant xu_is2_n_flush_offset : integer := xu_ex5_w_flush_offset + xu_ex5_w_flush_q'length; +constant xu_rf0_n_flush_offset : integer := xu_is2_n_flush_offset + xu_is2_n_flush_q'length; +constant xu_rf1_n_flush_offset : integer := xu_rf0_n_flush_offset + xu_rf0_n_flush_q'length; +constant xu_rf1_s_flush_offset : integer := xu_rf1_n_flush_offset + xu_rf1_n_flush_q'length; +constant xu_rf1_w_flush_offset : integer := xu_rf1_s_flush_offset + xu_rf1_s_flush_q'length; +constant ex5_np1_irpt_dbg_cint_offset : integer := xu_rf1_w_flush_offset + xu_rf1_w_flush_q'length; +constant ex6_np1_irpt_dbg_cint_offset : integer := ex5_np1_irpt_dbg_cint_offset + ex5_np1_irpt_dbg_cint_q'length; +constant ex5_np1_irpt_dbg_event_offset : integer := ex6_np1_irpt_dbg_cint_offset + ex6_np1_irpt_dbg_cint_q'length; +constant ex6_np1_irpt_dbg_event_offset : integer := ex5_np1_irpt_dbg_event_offset + ex5_np1_irpt_dbg_event_q'length; +constant clkg_ctl_offset : integer := ex6_np1_irpt_dbg_event_offset + ex6_np1_irpt_dbg_event_q'length; +constant xu_rf_seq_end_offset : integer := clkg_ctl_offset + 1; +constant xu_rfpe_ack_offset : integer := xu_rf_seq_end_offset + 1; +constant xu_rfpe_hold_present_offset : integer := xu_rfpe_ack_offset + xu_rfpe_ack_q'length; +constant exx_act_offset : integer := xu_rfpe_hold_present_offset + 1; +constant ex4_mchk_int_en_offset : integer := exx_act_offset + exx_act_q'length; +constant ex5_mchk_int_en_offset : integer := ex4_mchk_int_en_offset + ex4_mchk_int_en_q'length; +constant trace_bus_enable_offset : integer := ex5_mchk_int_en_offset + ex5_mchk_int_en_q'length; +constant ex1_instr_trace_type_offset : integer := trace_bus_enable_offset + 1; +constant ex1_instr_trace_val_offset : integer := ex1_instr_trace_type_offset + ex1_instr_trace_type_q'length; +constant ex1_xu_issued_offset : integer := ex1_instr_trace_val_offset + 1; +constant ex2_xu_issued_offset : integer := ex1_xu_issued_offset + ex1_xu_issued_q'length; +constant ex3_xu_issued_offset : integer := ex2_xu_issued_offset + ex2_xu_issued_q'length; +constant ex4_xu_issued_offset : integer := ex3_xu_issued_offset + ex3_xu_issued_q'length; +constant ex3_axu_issued_offset : integer := ex4_xu_issued_offset + ex4_xu_issued_q'length; +constant ex4_axu_issued_offset : integer := ex3_axu_issued_offset + ex3_axu_issued_q'length; +constant ex2_instr_dbg_offset : integer := ex4_axu_issued_offset + ex4_axu_issued_q'length; +constant ex2_instr_trace_type_offset : integer := ex2_instr_dbg_offset + ex2_instr_dbg_q'length; +constant ex4_instr_trace_val_offset : integer := ex2_instr_trace_type_offset + ex2_instr_trace_type_q'length; +constant ex5_instr_trace_val_offset : integer := ex4_instr_trace_val_offset + 1; +constant ex5_siar_offset : integer := ex5_instr_trace_val_offset + 1; +constant ex5_siar_cpl_offset : integer := ex5_siar_offset + ex5_siar_q'length; +constant ex5_siar_gs_offset : integer := ex5_siar_cpl_offset + 1; +constant ex5_siar_issued_offset : integer := ex5_siar_gs_offset + 1; +constant ex5_siar_pr_offset : integer := ex5_siar_issued_offset + 1; +constant ex5_siar_tid_offset : integer := ex5_siar_pr_offset + 1; +constant ex5_ucode_end_dbg_offset : integer := ex5_siar_tid_offset + ex5_siar_tid_q'length; +constant ex5_ucode_val_dbg_offset : integer := ex5_ucode_end_dbg_offset + ex5_ucode_end_dbg_q'length; +constant instr_trace_mode_offset : integer := ex5_ucode_val_dbg_offset + ex5_ucode_val_dbg_q'length; +constant debug_data_out_offset : integer := instr_trace_mode_offset + 1; +constant debug_mux_ctrls_offset : integer := debug_data_out_offset + debug_data_out_q'length; +constant debug_mux_ctrls_int_offset : integer := debug_mux_ctrls_offset + debug_mux_ctrls_q'length; +constant trigger_data_out_offset : integer := debug_mux_ctrls_int_offset + debug_mux_ctrls_int_q'length; +constant event_bus_enable_offset : integer := trigger_data_out_offset + trigger_data_out_q'length; +constant ex3_perf_event_offset : integer := event_bus_enable_offset + 1; +constant ex5_perf_event_offset : integer := ex3_perf_event_offset + ex3_perf_event_q'length; +constant spr_bit_act_offset : integer := ex5_perf_event_offset + ex5_perf_event_q'length; +constant spare_0_offset : integer := spr_bit_act_offset + 1; +constant spare_1_offset : integer := spare_0_offset + spare_0_q'length; +constant spare_2_offset : integer := spare_1_offset + spare_1_q'length; +constant spare_3_offset : integer := spare_2_offset + spare_2_q'length; +constant spare_4_offset : integer := spare_3_offset + spare_3_q'length; +constant spare_5_offset : integer := spare_4_offset + spare_4_q'length; + +constant exx_instr_async_block_offset : integer := spare_5_offset + spare_5_q'length; +constant ex5_late_flush_offset : integer := exx_instr_async_block_offset + exx_instr_async_block_q(0)'length*threads; +constant ex5_esr_offset : integer := ex5_late_flush_offset + ifar_repwr*threads; +constant ex5_dbsr_offset : integer := ex5_esr_offset + ex5_esr_q'length; +constant ex5_mcsr_offset : integer := ex5_dbsr_offset + ex5_dbsr_q'length; +constant ex4_uc_cia_offset : integer := ex5_mcsr_offset + ex5_mcsr_q'length; +constant ex4_axu_instr_type_offset : integer := ex4_uc_cia_offset + IFAR_UC'length*threads; +constant ex5_mem_attr_offset : integer := ex4_axu_instr_type_offset + 3*threads; +constant ex5_ivo_sel_offset : integer := ex5_mem_attr_offset + ex4_mem_attr_q'length*threads; +constant ex5_nia_b_offset : integer := ex5_ivo_sel_offset + ivos*threads; +constant ex2_ifar_b_offset : integer := ex5_nia_b_offset + eff_ifar*threads; +constant ex3_ifar_offset : integer := ex2_ifar_b_offset + eff_ifar*threads; +constant ex4_ifar_offset : integer := ex3_ifar_offset + eff_ifar*threads; +constant ex4_epid_instr_offset : integer := ex4_ifar_offset + eff_ifar*threads; +constant ex4_is_any_store_offset : integer := ex4_epid_instr_offset + ex4_epid_instr_q'length; +constant ex5_flush_2ucode_offset : integer := ex4_is_any_store_offset + ex4_is_any_store_q'length; +constant ex5_ucode_restart_offset : integer := ex5_flush_2ucode_offset + ex5_flush_2ucode_q'length; +constant ex5_mem_attr_le_offset : integer := ex5_ucode_restart_offset + ex5_ucode_restart_q'length; +constant ex5_cm_hold_cond_offset : integer := ex5_mem_attr_le_offset + ex5_mem_attr_le_q'length; +constant ex3_async_int_block_cond_offset : integer := ex5_cm_hold_cond_offset + 1; +constant ex3_base_int_block_offset : integer := ex3_async_int_block_cond_offset+ 1; +constant ex3_mchk_int_block_offset : integer := ex3_base_int_block_offset + 1; +constant exx_thread_stop_mcflush_offset : integer := ex3_mchk_int_block_offset + 1; +constant exx_lateflush_mcflush_offset : integer := exx_thread_stop_mcflush_offset + 1; +constant exx_csi_mcflush_offset : integer := exx_lateflush_mcflush_offset + 1; +constant exx_hold0_mcflush_offset : integer := exx_csi_mcflush_offset + 1; +constant exx_hold1_mcflush_offset : integer := exx_hold0_mcflush_offset + 1; +constant exx_barr_mcflush_offset : integer := exx_hold1_mcflush_offset + 1; +constant rfpe_quiesce_offset : integer := exx_barr_mcflush_offset + 1; +constant scan_right : integer := rfpe_quiesce_offset + 1; +signal siv : std_ulogic_vector(0 to scan_right-1); +signal sov : std_ulogic_vector(0 to scan_right-1); +signal siv_3 : std_ulogic_vector(0 to 1); +signal sov_3 : std_ulogic_vector(0 to 1); +constant dd1_clk_override_offset_ccfg : integer := 0; +constant scan_right_ccfg : integer := dd1_clk_override_offset_ccfg + 1; +signal siv_ccfg : std_ulogic_vector(0 to scan_right_ccfg-1); +signal sov_ccfg : std_ulogic_vector(0 to scan_right_ccfg-1); +constant ex4_cia_b_offset_bcfg : integer := 0; +constant mcsr_rpt_offset_bcfg : integer := ex4_cia_b_offset_bcfg + IFAR'length*threads; +constant mcsr_rpt2_offset_bcfg : integer := mcsr_rpt_offset_bcfg + pc_err_mcsr_rpt_q'length*threads; +constant scan_right_bcfg : integer := mcsr_rpt2_offset_bcfg + pc_err_mcsr_rpt_q'length*threads; +signal siv_bcfg : std_ulogic_vector(0 to scan_right_bcfg-1); +signal sov_bcfg : std_ulogic_vector(0 to scan_right_bcfg-1); +constant scan_right_dcfg : integer := 1; +signal siv_dcfg : std_ulogic_vector(0 to scan_right_dcfg-1); +signal sov_dcfg : std_ulogic_vector(0 to scan_right_dcfg-1); +signal tiup, tidn : std_ulogic; +signal rf1_xu_val : std_ulogic_vector(0 to threads-1); +signal ex1_xu_val : std_ulogic_vector(0 to threads-1); +signal ex2_xu_val : std_ulogic_vector(0 to threads-1); +signal ex3_xu_val : std_ulogic_vector(0 to threads-1); +signal ex4_xu_val : std_ulogic_vector(0 to threads-1); +signal ex2_axu_val : std_ulogic_vector(0 to threads-1); +signal ex3_axu_val : std_ulogic_vector(0 to threads-1); +signal ex4_axu_val : std_ulogic_vector(0 to threads-1); +signal ex3_any_val : std_ulogic_vector(0 to threads-1); +signal ex4_any_val : std_ulogic_vector(0 to threads-1); +signal ex3_anyuc_val : std_ulogic_vector(0 to threads-1); +signal ex4_anyuc_val : std_ulogic_vector(0 to threads-1); +signal ex3_anyuc_val_q : std_ulogic_vector(0 to threads-1); +signal ex4_anyuc_val_q : std_ulogic_vector(0 to threads-1); +signal rf1_ucode_val : std_ulogic_vector(0 to threads-1); +signal ex1_ucode_val : std_ulogic_vector(0 to threads-1); +signal ex2_ucode_val : std_ulogic_vector(0 to threads-1); +signal ex3_ucode_val : std_ulogic_vector(0 to threads-1); +signal ex4_ucode_val : std_ulogic_vector(0 to threads-1); +signal ex3_xuuc_val_q : std_ulogic_vector(0 to threads-1); +signal ex4_xuuc_val_q : std_ulogic_vector(0 to threads-1); +signal ex3_xuuc_val : std_ulogic_vector(0 to threads-1); +signal ex4_xuuc_val : std_ulogic_vector(0 to threads-1); +signal ex3_dep_val : std_ulogic_vector(0 to threads-1); +signal iu_flush : std_ulogic_vector(0 to threads-1); +signal any_flush : std_ulogic_vector(0 to threads-1); +signal is2_flush : std_ulogic_vector(0 to threads-1); +signal rf0_flush : std_ulogic_vector(0 to threads-1); +signal rf1_flush : std_ulogic_vector(0 to threads-1); +signal ex1_flush : std_ulogic_vector(0 to threads-1); +signal ex2_flush : std_ulogic_vector(0 to threads-1); +signal ex3_flush : std_ulogic_vector(0 to threads-1); +signal ex4_flush : std_ulogic_vector(0 to threads-1); +signal spare_0_lclk : clk_logic; +signal spare_1_lclk : clk_logic; +signal spare_2_lclk : clk_logic; +signal spare_3_lclk : clk_logic; +signal spare_4_lclk : clk_logic; +signal spare_5_lclk : clk_logic; +signal spare_0_d1clk, spare_0_d2clk : std_ulogic; +signal spare_1_d1clk, spare_1_d2clk : std_ulogic; +signal spare_2_d1clk, spare_2_d2clk : std_ulogic; +signal spare_3_d1clk, spare_3_d2clk : std_ulogic; +signal spare_4_d1clk, spare_4_d2clk : std_ulogic; +signal spare_5_d1clk, spare_5_d2clk : std_ulogic; +signal func_scan_rpwr2_in : std_ulogic_vector(3 to 3); +signal func_scan_rpwr_in, func_scan_rpwr_out : std_ulogic_vector(0 to 3); +signal func_scan_out_gate : std_ulogic_vector(50 to 53); +signal ccfg_scan_rpwr_in, ccfg_scan_rpwr_out : std_ulogic_vector(0 to 0); +signal ccfg_scan_out_gate : std_ulogic_vector(0 to 0); +signal bcfg_scan_rpwr_in, bcfg_scan_rpwr_out : std_ulogic_vector(0 to 0); +signal bcfg_scan_out_gate : std_ulogic_vector(0 to 0); +signal dcfg_scan_rpwr_in, dcfg_scan_rpwr_out : std_ulogic_vector(0 to 0); +signal dcfg_scan_out_gate : std_ulogic_vector(0 to 0); +signal mcsr_bcfg_slp_sl_d1clk : std_ulogic; +signal mcsr_bcfg_slp_sl_d2clk : std_ulogic; +signal mcsr_bcfg_slp_sl_lclk : clk_logic; +signal bcfg_so_d2clk : std_ulogic; +signal bcfg_so_lclk : clk_logic; +signal func_slp_sl_thold_1 : std_ulogic; +signal func_slp_nsl_thold_1 : std_ulogic; +signal func_sl_thold_1 : std_ulogic; +signal func_nsl_thold_1 : std_ulogic; +signal cfg_sl_thold_1 : std_ulogic; +signal cfg_slp_sl_thold_1 : std_ulogic; +signal fce_1 : std_ulogic; +signal sg_1 : std_ulogic; +signal func_slp_sl_thold_0 : std_ulogic; +signal func_slp_nsl_thold_0 : std_ulogic; +signal func_sl_thold_0 : std_ulogic; +signal func_nsl_thold_0 : std_ulogic; +signal cfg_sl_thold_0 : std_ulogic; +signal cfg_slp_sl_thold_0 : std_ulogic; +signal fce_0 : std_ulogic; +signal sg_0 : std_ulogic; +signal cfg_sl_force : std_ulogic; +signal cfg_sl_thold_0_b : std_ulogic; +signal bcfg_sl_force : std_ulogic; +signal bcfg_sl_thold_0_b : std_ulogic; +signal dcfg_sl_force : std_ulogic; +signal dcfg_sl_thold_0_b : std_ulogic; +signal cfg_slp_sl_force : std_ulogic; +signal cfg_slp_sl_thold_0_b : std_ulogic; +signal bcfg_slp_sl_force : std_ulogic; +signal bcfg_slp_sl_thold_0_b : std_ulogic; +signal func_sl_force : std_ulogic; +signal func_sl_thold_0_b : std_ulogic; +signal func_nsl_force : std_ulogic; +signal func_nsl_thold_0_b : std_ulogic; +signal func_slp_sl_force : std_ulogic; +signal func_slp_sl_thold_0_b : std_ulogic; +signal func_slp_nsl_force : std_ulogic; +signal func_slp_nsl_thold_0_b : std_ulogic; +signal so_force : std_ulogic; +signal ccfg_so_thold_0_b : std_ulogic; +signal bcfg_so_thold_0_b : std_ulogic; +signal dcfg_so_thold_0_b : std_ulogic; +signal func_so_thold_0_b : std_ulogic; +signal rf1_is_ldbrx, rf1_is_lwbrx, rf1_is_lhbrx : std_ulogic; +signal rf1_is_stdbrx, rf1_is_stwbrx, rf1_is_sthbrx : std_ulogic; +signal rf1_is_icblc, rf1_is_icbtls : std_ulogic; +signal rf1_is_dcblc, rf1_is_dcbtls, rf1_is_dcbtstls : std_ulogic; +signal rf1_is_wait, rf1_is_eratre : std_ulogic; +signal ex4_np1_mtiar_flush, ex3_np1_mtiar_flush : std_ulogic_vector(0 to threads-1); +signal ex1_instr : std_ulogic_vector(0 to 31); +signal ex1_branch,ex1_br_mispred,ex1_br_taken : std_ulogic; +signal ex1_br_update, ex1_is_bclr : std_ulogic; +signal ex1_lr_update, ex1_ctr_dec_update : std_ulogic; +signal ex1_taken_bclr : std_ulogic; +signal ex1_xu_ifar : IFAR; +signal ex1_ifar_sel, ex1_ifar_sel_b : std_ulogic_vector(ex2_ifar_b_q'range); +signal ex2_br_flush : std_ulogic_vector(0 to threads-1); +signal ex2_br_flush_ifar : IFAR; +signal ex2_ifar : std_ulogic_vector(ex2_ifar_b_q'range); +signal ex4_cia_cmpr : std_ulogic_vector(0 to threads-1); +signal ex3_lr_cmprh, ex3_lr_cmprl : std_ulogic_vector(0 to threads-1); +signal ex3_cia_cmprh, ex3_cia_cmprl : std_ulogic_vector(0 to threads-1); +signal ex4_cia_cmprh, ex4_cia_cmprl : std_ulogic_vector(0 to threads-1); +signal ex3_bclr_cmpr_b : std_ulogic_vector(0 to threads-1); +signal ex4_taken_bclr, ex5_check_bclr : std_ulogic_vector(0 to threads-1); +signal ex4_ucode_end : std_ulogic_vector(0 to threads-1); +signal ex3_async_int_block : std_ulogic_vector(0 to threads-1); +signal ex3_async_int_block_noaxu : std_ulogic_vector(0 to threads-1); +signal ex3_base_int_block : std_ulogic_vector(0 to threads-1); +signal ex3_mchk_int_block : std_ulogic_vector(0 to threads-1); +signal ex3_esr_bit_act : std_ulogic_vector(0 to threads-1); +signal ex4_n_flush : std_ulogic_vector(0 to threads-1); +signal ex4_np1_flush : std_ulogic_vector(0 to threads-1); +signal ex4_cia_p1_out : std_ulogic_vector(0 to eff_ifar*threads-1); +signal ex5_ram_interrupt : std_ulogic_vector(0 to threads-1); +signal ex4_check_cia : std_ulogic_vector(0 to threads-1); +signal ex3_ct : std_ulogic_vector(0 to threads-1); +signal ex4_is_base_int,ex4_is_crit_int,ex4_is_mchk_int: std_ulogic_vector(0 to threads-1); +signal ex5_is_base_hint,ex5_is_base_gint : std_ulogic_vector(0 to threads-1); +signal ex3_np1_step_flush : std_ulogic_vector(0 to threads-1); +signal ex4_clear_bclr_chk : std_ulogic_vector(0 to threads-1); +signal ex5_is_any_int,ex5_is_any_gint,ex5_is_any_hint : std_ulogic_vector(0 to threads-1); +signal ex3_lr_cmpr, ex3_cia_cmpr : std_ulogic_vector(0 to threads-1); +signal ex3_mem_attr_chk : std_ulogic_vector(0 to threads-1); +signal ex3_mem_attr_cmpr : std_ulogic_vector(0 to threads-1); +signal ex4_mem_attr_act : std_ulogic_vector(0 to threads-1); +signal ex4_is_any_store : std_ulogic_vector(0 to threads-1); +signal ex4_epid_instr : std_ulogic_vector(0 to threads-1); +signal ex4_flush_act : std_ulogic_vector(0 to threads-1); +signal ex4_ucode_restart : std_ulogic_vector(0 to threads-1); +signal ex4_uc_cia_val : std_ulogic_vector(0 to threads-1); +signal ex5_flush_update : std_ulogic_vector(0 to threads-1); +signal ex4_cm : std_ulogic_vector(0 to threads-1); +signal exx_multi_flush : std_ulogic_vector(0 to threads-1); +signal hold_state_0, hold_state_1 : std_ulogic_vector(0 to threads-1); +signal spr_givpr : std_ulogic_vector(62-eff_ifar to 51); +signal spr_ivpr : std_ulogic_vector(62-eff_ifar to 51); +signal spr_ctr : std_ulogic_vector(0 to (regsize)*threads-1); +signal spr_lr : std_ulogic_vector(0 to (regsize)*threads-1); +signal spr_iar : std_ulogic_vector(0 to (eff_ifar)*threads-1); +signal spr_xucr3_cm_hold_dly : std_ulogic_vector(0 to 3); +signal spr_xucr3_stop_dly : std_ulogic_vector(0 to 3); +signal spr_xucr3_hold0_dly : std_ulogic_vector(0 to 3); +signal spr_xucr3_hold1_dly : std_ulogic_vector(0 to 3); +signal spr_xucr3_csi_dly : std_ulogic_vector(0 to 3); +signal spr_xucr3_int_dly : std_ulogic_vector(0 to 3); +signal spr_xucr3_asyncblk_dly : std_ulogic_vector(0 to 3); +signal spr_xucr3_flush_dly : std_ulogic_vector(0 to 3); +signal spr_xucr4_barr_dly : std_ulogic_vector(0 to 3); +signal spr_xucr4_lsu_bar_dis : std_ulogic; +signal spr_xucr4_div_bar_dis : std_ulogic; +signal spr_xucr4_mddmh : std_ulogic; +signal spr_xucr4_mmu_mchk_int : std_ulogic; +signal ex3_np1_mtxucr0_flush : std_ulogic_vector(0 to threads-1); +signal ex4_n_lsu_flush : std_ulogic_vector(0 to threads-1); +signal ex4_n_lsu_ddmh_flush : std_ulogic_vector(0 to threads-1); +signal ex3_div_coll : std_ulogic_vector(0 to threads-1); +signal ex3_non_uc_val : std_ulogic_vector(0 to threads-1); +signal ex3_n_ieratmiss_itlb_int : std_ulogic_vector(0 to threads-1); +signal ex3_n_tlbmiss_itlb_int : std_ulogic_vector(0 to threads-1); +signal ex3_n_iemh_mchk_mcint_xuuc : std_ulogic_vector(0 to threads-1); +signal ex3_n_iepe_mchk_mcint_xuuc : std_ulogic_vector(0 to threads-1); +signal ex3_n_il2ecc_mchk_mcint_xuuc : std_ulogic_vector(0 to threads-1); +signal ex3_n_dpovr_mchk_mcint : std_ulogic_vector(0 to threads-1); +signal ex3_n_demh_mchk_mcint_xu : std_ulogic_vector(0 to threads-1); +signal ex3_n_depe_mchk_mcint_xu : std_ulogic_vector(0 to threads-1); +signal ex3_n_dl2ecc_mchk_mcint : std_ulogic_vector(0 to threads-1); +signal ex3_n_ddpe_mchk_mcint_xu : std_ulogic_vector(0 to threads-1); +signal ex3_n_dcpe_mchk_mcint : std_ulogic_vector(0 to threads-1); +signal ex3_n_tlbmh_mchk_mcint : std_ulogic_vector(0 to threads-1); +signal ex3_n_tlbpe_mchk_mcint : std_ulogic_vector(0 to threads-1); +signal ex3_n_tlblru_mchk_mcint : std_ulogic_vector(0 to threads-1); +signal ex3_n_tlbsrej_mchk_mcint : std_ulogic_vector(0 to threads-1); +signal ex3_n_i1w1lock_dstor_int : std_ulogic_vector(0 to threads-1); +signal ex3_n_tlbi_dstor_int : std_ulogic_vector(0 to threads-1); +signal ex3_n_pt_dstor_int : std_ulogic_vector(0 to threads-1); +signal ex3_n_tlbi_istor_int : std_ulogic_vector(0 to threads-1); +signal ex3_n_pt_istor_int : std_ulogic_vector(0 to threads-1); +signal ex3_n_ldstmw_align_int : std_ulogic_vector(0 to threads-1); +signal ex3_n_ldst_align_int : std_ulogic_vector(0 to threads-1); +signal ex3_n_sprpil_prog_int_xu : std_ulogic_vector(0 to threads-1); +signal ex3_n_tlbpil_prog_int_xu : std_ulogic_vector(0 to threads-1); +signal ex3_n_mmupil_prog_int_xu : std_ulogic_vector(0 to threads-1); +signal ex3_n_iupil_prog_int_xuuc : std_ulogic_vector(0 to threads-1); +signal ex3_n_xupil_prog_int_xuuc : std_ulogic_vector(0 to threads-1); +signal ex3_n_ppr_prog_int_en : std_ulogic_vector(0 to threads-1); +signal ex3_n_sprppr_prog_int_xuuc : std_ulogic_vector(0 to threads-1); +signal ex3_n_instrppr_prog_int_xuuc : std_ulogic_vector(0 to threads-1); +signal ex3_n_fu_fp_unavail_int_axu : std_ulogic_vector(0 to threads-1); +signal ex3_n_xu_fp_unavail_int_xuuc : std_ulogic_vector(0 to threads-1); +signal ex3_n_fu_ap_unavail_int_axu : std_ulogic_vector(0 to threads-1); +signal ex3_n_xu_ap_unavail_int_xuuc : std_ulogic_vector(0 to threads-1); +signal ex3_n_fu_vec_unavail_int_axu : std_ulogic_vector(0 to threads-1); +signal ex3_n_xu_vec_unavail_int_xuuc : std_ulogic_vector(0 to threads-1); +signal ex3_n_deratmiss_dtlb_int : std_ulogic_vector(0 to threads-1); +signal ex3_n_tlbmiss_dtlb_int : std_ulogic_vector(0 to threads-1); +signal ex3_n_dacr_dbg_cint_xu : std_ulogic_vector(0 to threads-1); +signal ex3_n_dacw_dbg_cint_xu : std_ulogic_vector(0 to threads-1); +signal msr_guest_priv : std_ulogic_vector(0 to threads-1); +signal ex3_n_spr_hpriv_int_xuuc : std_ulogic_vector(0 to threads-1); +signal ex3_n_instr_hpriv_int_xuuc : std_ulogic_vector(0 to threads-1); +signal ex3_n_ehpriv_hpriv_int : std_ulogic_vector(0 to threads-1); +signal ex3_np1_dbg_cint_en : std_ulogic_vector(0 to threads-1); +signal ex3_np1_instr_flush : std_ulogic_vector(0 to threads-1); +signal ex3_np1_init_flush : std_ulogic_vector(0 to threads-1); +signal ex3_n_ram_flush : std_ulogic_vector(0 to threads-1); +signal ex3_n_mmuhold_flush : std_ulogic_vector(0 to threads-1); +signal ex3_n_ici_flush : std_ulogic_vector(0 to threads-1); +signal ex3_n_dci_flush : std_ulogic_vector(0 to threads-1); +signal ex3_n_mmu_flush : std_ulogic_vector(0 to threads-1); +signal ex3_n_multcoll_flush : std_ulogic_vector(0 to threads-1); +signal ex3_n_lsu_dcpe_flush : std_ulogic_vector(0 to threads-1); +signal ex3_n_fu_rfpe_flush, ex3_n_fu_rfpe_det : std_ulogic_vector(0 to threads-1); +signal ex3_n_xu_rfpe_flush : std_ulogic_vector(0 to threads-1); +signal ex3_n_sprg_ue_flush : std_ulogic_vector(0 to threads-1); +signal ex3_np1_sprg_ce_flush : std_ulogic_vector(0 to threads-1); +signal ex3_n_fu_dep_flush : std_ulogic_vector(0 to threads-1); +signal ex3_n_lsualign_2ucode_flush : std_ulogic_vector(0 to threads-1); +signal ex3_n_fu_2ucode_flush : std_ulogic_vector(0 to threads-1); +signal ex3_n_derat_dep_flush : std_ulogic_vector(0 to threads-1); +signal ex3_n_lsu_dep_flush : std_ulogic_vector(0 to threads-1); +signal ex3_n_lsu_ddpe_flush : std_ulogic_vector(0 to threads-1); +signal ex4_n_ldq_full_flush : std_ulogic_vector(0 to threads-1); +signal ex4_n_ieratre_par_mcint : std_ulogic_vector(0 to threads-1); +signal ex4_n_deratre_par_mcint : std_ulogic_vector(0 to threads-1); +signal ex4_n_tlbwemiss_dlrat_int : std_ulogic_vector(0 to threads-1); +signal ex4_n_tlbwe_pil_prog_int : std_ulogic_vector(0 to threads-1); +signal ex4_n_tlbmh_mchk_mcint : std_ulogic_vector(0 to threads-1); +signal ex4_n_tlbpar_mchk_mcint : std_ulogic_vector(0 to threads-1); +signal ex4_n_mmu_hpriv_int : std_ulogic_vector(0 to threads-1); +signal ex4_ena_prog_int : std_ulogic_vector(0 to threads-1); +signal ex4_barrier_flush : std_ulogic_vector(0 to threads-1); +signal ex4_lsu_barr_flush : std_ulogic_vector(0 to threads-1); +signal ex4_div_barr_flush : std_ulogic_vector(0 to threads-1); +signal ex3_hold_block : std_ulogic_vector(0 to threads-1); +signal ex5_csi : std_ulogic_vector(0 to threads-1); +signal exx_thread_stop_mcflush : std_ulogic_vector(0 to threads-1); +signal exx_lateflush_mcflush : std_ulogic_vector(0 to threads-1); +signal exx_csi_mcflush : std_ulogic_vector(0 to threads-1); +signal exx_hold0_mcflush : std_ulogic_vector(0 to threads-1); +signal exx_hold1_mcflush : std_ulogic_vector(0 to threads-1); +signal exx_barr_mcflush : std_ulogic_vector(0 to threads-1); +signal ex4_late_flush : std_ulogic_vector(0 to threads-1); +signal ex4_n_ddmh_mchk_mcint : std_ulogic_vector(0 to threads-1); +signal ex3_n_ierat_flush : std_ulogic_vector(0 to threads-1); +signal ex3_async_int_block_cond : std_ulogic_vector(0 to threads-1); +signal ex3_base_int_block_cond : std_ulogic_vector(0 to threads-1); +signal ex3_mchk_int_block_cond : std_ulogic_vector(0 to threads-1); +signal ex5_cm_hold_cond : std_ulogic_vector(0 to threads-1); +signal exx_cm_hold : std_ulogic_vector(0 to threads-1); +signal ex5_cia_p1 : IFAR; +signal ex5_msr_cm : std_ulogic; +signal ex2_msr_updater : std_ulogic; +signal ex4_async_block : std_ulogic_vector(0 to threads-1); +signal any_ext_perf_ints : std_ulogic_vector(0 to threads-1); +signal any_ext_perf_int : std_ulogic; +signal ext_int_asserted, crit_int_asserted : std_ulogic_vector(0 to threads-1); +signal perf_int_asserted : std_ulogic_vector(0 to threads-1); +signal rf1_is_dci : std_ulogic; +signal rf1_is_ici : std_ulogic; +signal rf1_th_fld_val : std_ulogic; +signal rf1_opcode_is_31 : boolean; +signal rf1_opcode_is_0 : boolean; +signal rf1_opcode_is_19 : boolean; +signal ex3_dlk_dstor_cond0, ex3_dlk_dstor_cond1 : std_ulogic_vector(0 to threads-1); +signal ex3_dlk_dstor_cond2, ex3_dlk_dstor_cond : std_ulogic_vector(0 to threads-1); +signal ex4_n_fu_rfpe_flush : std_ulogic_vector(0 to threads-1); +signal ex4_n_xu_rfpe_flush : std_ulogic_vector(0 to threads-1); +signal ex4_n_flush_pri_ehpriv : std_ulogic_vector(0 to threads-1); +signal ici_hold_present : std_ulogic; +signal ex4_n_fu_rfpe_set, ex4_n_xu_rfpe_set : std_ulogic; +signal pc_err_mcsr, pc_err_mcsr_rpt : std_ulogic_vector(0 to 11*threads-1); +signal dbg_group0, dbg_group1, dbg_group2, dbg_group3, + dbg_group4, dbg_group5, dbg_group6, dbg_group7, + dbg_group8, dbg_group9, dbg_group10,dbg_group11, + dbg_group12,dbg_group13,dbg_group14,dbg_group15, + dbg_group16,dbg_group17,dbg_group18,dbg_group19, + dbg_group20,dbg_group21,dbg_group22,dbg_group23, + dbg_group24,dbg_group25,dbg_group26,dbg_group27, + dbg_group28,dbg_group29,dbg_group30,dbg_group31: std_ulogic_vector(0 to 87); +signal trg_group0 ,trg_group1 ,trg_group2 ,trg_group3 : std_ulogic_vector(0 to 11); +signal cpl_debug_data_in_int : std_ulogic_vector(0 to 87); +signal dbg_match : ARY3; +signal dbg_misc : ARY4; +signal dbg_valids, dbg_valids_opc, dbg_msr, dbg_int_types : ARY5; +signal dbg_async_block : ARY7; +signal dbg_iuflush : ARY9; +signal ex5_flush_pri_enc_dbg,dbg_hold : ARY6; +signal ex4_cia_out : ARY_IFAR; +signal ex5_axu_ucode_val_opc : std_ulogic_vector(0 to threads-1); +signal ex5_axu_val_dbg_opc, ex5_xu_val_dbg_opc : std_ulogic_vector(0 to threads-1); +signal br_debug : std_ulogic_vector(0 to 11); +signal ex4_xu_siar_val, ex4_axu_siar_val : std_ulogic; +signal ex4_siar_cpl : std_ulogic_vector(0 to threads-1); +signal ex4_siar_sel_act : std_ulogic; +signal ex4_siar_axu_sel : std_ulogic; +signal ex4_siar_tid, ex4_siar_sel, siar_cm : std_ulogic_vector(0 to 3); +signal ex5_xu_ppc_cpl, ex5_axu_ppc_cpl : std_ulogic_vector(0 to threads-1); +signal ex5_xu_trace_val, ex5_axu_trace_val : std_ulogic; +signal exx_act : std_ulogic_vector(0 to 4); +signal ex1_ifar_act, ex2_ifar_act, ex3_ifar_act : std_ulogic_vector(0 to threads-1); +signal ex4_nia_act : std_ulogic_vector(0 to threads-1); +signal ex2_axu_act : std_ulogic; +signal ex4_dbsr_act, ex4_mcsr_act, ex4_esr_act : std_ulogic_vector(0 to threads-1); +signal ex5_mcsr_act : std_ulogic; +signal ex3_uc_cia_act : std_ulogic_vector(0 to threads-1); +signal exx_flush_inf_act, ex4_flush_inf_act : std_ulogic; +signal spr_bit_w_int_act : std_ulogic; +signal exx_np1_icmp_dbg_cint : std_ulogic_vector(0 to threads-1); +signal exx_np1_icmp_dbg_event : std_ulogic_vector(0 to threads-1); +signal ex4_np1_icmp_dbg_en : std_ulogic_vector(0 to threads-1); +signal ex4_n_flush_pri_icmp : std_ulogic_vector(0 to threads-1); +signal ex4_n_flush_pri_irpt : std_ulogic_vector(0 to threads-1); +signal ex4_np1_icmp_dbg_event : std_ulogic_vector(0 to threads-1); +signal ex4_np1_icmp_dbg_cint : std_ulogic_vector(0 to threads-1); +signal ex4_icmp_async_block : std_ulogic_vector(0 to threads-1); +signal exx_np1_irpt_dbg_cint : std_ulogic_vector(0 to threads-1); +signal exx_np1_irpt_dbg_event : std_ulogic_vector(0 to threads-1); +signal ex4_n_flush_pri_dacr_async : std_ulogic_vector(0 to threads-1); +signal ex4_ram_cpl : std_ulogic_vector(0 to threads-1); +signal ex4_siar_cm_mask : IFAR; +signal ex3_n_tlb_mchk_flush_en : std_ulogic_vector(0 to threads-1); +signal ex3_n_tlbmh_mchk_flush : std_ulogic_vector(0 to threads-1); +signal ex3_n_tlbpe_mchk_flush : std_ulogic_vector(0 to threads-1); +signal ex3_n_dexx_mchk_flush_en : std_ulogic_vector(0 to threads-1); +signal ex3_n_demh_mchk_flush : std_ulogic_vector(0 to threads-1); +signal ex3_n_depe_mchk_flush : std_ulogic_vector(0 to threads-1); +signal ex3_n_mmu_mchk_flush_only : std_ulogic; +signal ex3_is_any_ldst : std_ulogic; +signal ex5_ram_issue_gated : std_ulogic_vector(0 to threads-1); +signal rfpe_quiesced : std_ulogic; +signal rfpe_quiesce_cond_b, rfpe_quiesced_ctr_zero_b : std_ulogic; +signal ex4_axu_trap_pie : std_ulogic_vector(0 to threads-1); +signal rf1_is_tlbre : std_ulogic; +signal rf1_is_tlbsx, rf1_is_tlbsrx : std_ulogic; +signal tlbsx_async_block_set : std_ulogic_vector(0 to threads-1); +signal tlbsx_async_block_clr : std_ulogic_vector(0 to threads-1); + +begin + + +tiup <= '1'; +tidn <= '0'; + +exx_act_d <= (clk_override_q or clkg_ctl_q or dec_cpl_rf0_act) & exx_act(0 to 3); + +exx_act(0) <= exx_act_q(0); +exx_act(1) <= exx_act_q(1); +exx_act(2) <= exx_act_q(2); +exx_act(3) <= exx_act_q(3) or or_reduce(ex3_axu_val_q); +exx_act(4) <= exx_act_q(4); + +ex2_axu_act <= or_reduce(ex2_axu_act_q) or clk_override_q; + +ex1_ifar_act <= ex1_xu_val_q or ex1_xu_issued_q or ex1_ucode_val_q or ex1_axu_act_q or (0 to threads-1=>clk_override_q); +ex2_ifar_act <= ex2_xu_val_q or ex2_xu_issued_q or ex2_ucode_val_q or ex2_axu_act_q or (0 to threads-1=>clk_override_q); +ex3_ifar_act <= ex3_xu_val_q or ex3_xu_issued_q or ex3_ucode_val_q or ex3_axu_val_q or (0 to threads-1=>clk_override_q) or ex3_axu_issued_q; + +spr_bit_w_int_act <= spr_bit_act_q or clkg_ctl_q; + +rf1_opcode_is_31 <= dec_cpl_rf1_instr(0 to 5) = "011111"; +rf1_opcode_is_0 <= dec_cpl_rf1_instr(0 to 5) = "000000"; +rf1_opcode_is_19 <= dec_cpl_rf1_instr(0 to 5) = "010011"; +rf1_is_tlbsx <= '1' when rf1_opcode_is_31 and dec_cpl_rf1_instr(21 to 30) = "1110010010" else '0'; +rf1_is_tlbsrx <= '1' when rf1_opcode_is_31 and dec_cpl_rf1_instr(21 to 30) = "1101010010" else '0'; +rf1_is_tlbre <= '1' when rf1_opcode_is_31 and dec_cpl_rf1_instr(21 to 30) = "1110110010" else '0'; +rf1_is_tlbwe <= '1' when rf1_opcode_is_31 and dec_cpl_rf1_instr(21 to 30) = "1111010010" else '0'; +rf1_is_eratre <= '1' when rf1_opcode_is_31 and dec_cpl_rf1_instr(21 to 30) = "0010110011" else '0'; +rf1_is_wait <= '1' when rf1_opcode_is_31 and dec_cpl_rf1_instr(21 to 30) = "0000111110" else '0'; +rf1_is_icblc <= '1' when rf1_opcode_is_31 and dec_cpl_rf1_instr(21 to 30) = "0011100110" else '0'; +rf1_is_icbtls <= '1' when rf1_opcode_is_31 and dec_cpl_rf1_instr(21 to 30) = "0111100110" else '0'; +rf1_is_dcblc <= '1' when rf1_opcode_is_31 and dec_cpl_rf1_instr(21 to 30) = "0110000110" else '0'; +rf1_is_dcbtls <= '1' when rf1_opcode_is_31 and dec_cpl_rf1_instr(21 to 30) = "0010100110" else '0'; +rf1_is_dcbtstls <= '1' when rf1_opcode_is_31 and dec_cpl_rf1_instr(21 to 30) = "0010000110" else '0'; +rf1_is_rfi <= '1' when rf1_opcode_is_19 and dec_cpl_rf1_instr(21 to 30) = "0000110010" else '0'; +rf1_is_rfci <= '1' when rf1_opcode_is_19 and dec_cpl_rf1_instr(21 to 30) = "0000110011" else '0'; +rf1_is_rfgi <= '1' when rf1_opcode_is_19 and dec_cpl_rf1_instr(21 to 30) = "0001100110" else '0'; +rf1_is_rfmci <= '1' when rf1_opcode_is_19 and dec_cpl_rf1_instr(21 to 30) = "0000100110" else '0'; +rf1_is_mfspr <= '1' when rf1_opcode_is_31 and dec_cpl_rf1_instr(21 to 30) = "0101010011" else '0'; +rf1_is_mtspr <= '1' when rf1_opcode_is_31 and dec_cpl_rf1_instr(21 to 30) = "0111010011" else '0'; +rf1_is_mtmsr <= '1' when rf1_opcode_is_31 and dec_cpl_rf1_instr(21 to 30) = "0010010010" else '0'; +rf1_is_wrtee <= '1' when rf1_opcode_is_31 and dec_cpl_rf1_instr(21 to 30) = "0010000011" else '0'; +rf1_is_wrteei <= '1' when rf1_opcode_is_31 and dec_cpl_rf1_instr(21 to 30) = "0010100011" else '0'; +rf1_is_erativax <= '1' when rf1_opcode_is_31 and dec_cpl_rf1_instr(21 to 30) = "1100110011" else '0'; +rf1_is_isync <= '1' when rf1_opcode_is_19 and dec_cpl_rf1_instr(21 to 30) = "0010010110" else '0'; +rf1_is_sc <= '1' when dec_cpl_rf1_instr( 0 to 5) = "010001" else '0'; +rf1_is_dci <= '1' when rf1_opcode_is_31 and dec_cpl_rf1_instr(21 to 30) = "0111000110" else '0'; +rf1_is_ici <= '1' when rf1_opcode_is_31 and dec_cpl_rf1_instr(21 to 30) = "1111000110" else '0'; +rf1_is_tlbivax <= '1' when rf1_opcode_is_31 and dec_cpl_rf1_instr(21 to 30) = "1100010010" else '0'; +rf1_is_ehpriv <= '1' when rf1_opcode_is_31 and dec_cpl_rf1_instr(21 to 30) = "0100001110" else '0'; +rf1_is_attn <= '1' when rf1_opcode_is_0 and dec_cpl_rf1_instr(21 to 30) = "0100000000" else '0'; +rf1_is_icswx <= '1' when rf1_opcode_is_31 and (dec_cpl_rf1_instr(21 to 30) = "0110010110" or + dec_cpl_rf1_instr(21 to 30) = "1110110110") else '0'; +rf1_is_any_ldstmw <= '1' when dec_cpl_rf1_instr(0 to 4) = "10111" else '0'; +rf1_sc_lev <= dec_cpl_rf1_instr(26); + +rf1_is_ldbrx <= '1' when rf1_opcode_is_31 and dec_cpl_rf1_instr(21 to 30) = "1000010100" else '0'; +rf1_is_lwbrx <= '1' when rf1_opcode_is_31 and dec_cpl_rf1_instr(21 to 30) = "1000010110" else '0'; +rf1_is_lhbrx <= '1' when rf1_opcode_is_31 and dec_cpl_rf1_instr(21 to 30) = "1100010110" else '0'; +rf1_is_stdbrx <= '1' when rf1_opcode_is_31 and dec_cpl_rf1_instr(21 to 30) = "1010010100" else '0'; +rf1_is_stwbrx <= '1' when rf1_opcode_is_31 and dec_cpl_rf1_instr(21 to 30) = "1010010110" else '0'; +rf1_is_sthbrx <= '1' when rf1_opcode_is_31 and dec_cpl_rf1_instr(21 to 30) = "1110010110" else '0'; + +rf1_byte_rev <= rf1_is_lhbrx or rf1_is_lwbrx or rf1_is_ldbrx or rf1_is_sthbrx or rf1_is_stwbrx or rf1_is_stdbrx; +rf1_is_dlock <= rf1_is_dcblc or rf1_is_dcbtls or rf1_is_dcbtstls; +rf1_is_ilock <= rf1_is_icblc or rf1_is_icbtls; + +rf1_is_mtxucr0 <= rf1_is_mtspr and (dec_cpl_rf1_instr(11 to 20) = "1011011111"); + +rf1_th_fld_val <= (dec_cpl_rf1_instr(7 to 10) = "0000") or (dec_cpl_rf1_instr(7 to 10) = "0010"); +ex1_is_dci_d <= rf1_is_dci and rf1_th_fld_val; +ex1_is_ici_d <= rf1_is_ici and rf1_th_fld_val; + +ex3_np1_instr_flush_d <= (ex2_is_mtmsr_q or + ex2_is_isync_q or + ex2_is_tlbivax_q or + ex2_is_erativax_q or + ex2_is_attn_q or + ex2_is_dci_q or + ex2_is_ici_q); + + +spare_4_d(0) <= not (rf1_is_tlbsx or rf1_is_tlbsrx); +spare_4_d(1 to 3) <= not spare_4_q(0 to 2); + +spare_4_d(4 to 7) <= not (tlbsx_async_block_set or (spare_4_q(4 to 7) and not tlbsx_async_block_clr)); + +tlbsx_async_block_set <= gate(ex4_instr_cpl_q,spare_4_q(3)); +tlbsx_async_block_clr <= ex4_anyuc_val_q or ex5_is_any_int or ex4_thread_stop_q; + + +xuq_cpl_slice : for t in 0 to threads-1 generate + + signal ex4_cia_b_q, ex4_cia_b_d : IFAR; + signal ex4_uc_cia_q, ex4_uc_cia_d : IFAR_UC; + signal ex4_axu_instr_type_q, ex4_axu_instr_type_d : std_ulogic_vector(0 to 2); + signal ex5_mem_attr_q : std_ulogic_vector(lsu_xu_ex3_attr'range); + signal ex5_ivo_sel_q, ex4_ivo_sel : std_ulogic_vector(0 to ivos-1); + signal ex5_flush_pri_dbg_q : std_ulogic_vector(0 to Fnp1); + signal ex4_cia_flush, flush_ifar : IFAR; + signal ex4_axu_instr_type : std_ulogic_vector(0 to 2); + signal ex3_ifar, ex4_ifar, ex3_spr_lr : IFAR; + signal ex5_flush_ifar : IFAR; + signal ex4_n_flush_cond, ex4_n_flush_pri : std_ulogic_vector(0 to Fn); + signal ex4_np1_flush_cond, ex4_np1_flush_pri : std_ulogic_vector(Fn+1 to Fnp1); + signal ex4_np1_flush_pri_nongated : std_ulogic_vector(Fn+1 to Fnp1); + signal ex4_np1_flush_pri_instr : std_ulogic_vector(0 to RFI); + signal ex4_flush_pri : std_ulogic_vector(0 to Fnp1); + signal ex4_n_flush_pri_unavail : std_ulogic_vector(0 to VEC); + signal ex4_n_flush_pri_ena : std_ulogic_vector(0 to 1); + signal ex5_ivo_mask_guest : std_ulogic_vector(0 to ivos-1); + signal ex5_ivo_guest_sel, ex5_ivo_hypv_sel : std_ulogic_vector(0 to ivos-1); + signal ex5_ivo : std_ulogic_vector(52 to 59); + signal ex4_nia : IFAR; + signal ex4_nia_instr, ex4_nia_cpl : IFAR; + signal ex4_cia : IFAR; + signal ex4_cia_p1 : IFAR; + signal ex4_cia_sel, ex4_nia_sel : IFAR; + signal ex4_uc_nia : IFAR_UC; + signal ex4_esr_mask : std_ulogic_vector(0 to cpl_spr_ex5_esr'length/threads-1); + signal ex4_cm_mask : IFAR; + signal ex4_dbsr_cond : std_ulogic_vector(0 to 1); + signal ex4_dbsr_en_cond : std_ulogic_vector(0 to 1); + signal ex4_esr_cond, ex4_esr_pri : std_ulogic_vector(0 to UCT); + + begin + + + + ex3_np1_crit_cint(t) <= spr_cpl_crit_interrupt(t) and not ex3_async_int_block(t); + + ex3_mchk_int_en(t) <= (msr_me_q(t) or msr_gs_q(t)) and not ex3_mchk_int_block(t); + + ex3_n_tlbmh_mchk_flush(t) <= ex3_n_tlb_mchk_flush_en(t) and ex3_tlb_multihit_err_q(t); + ex3_n_tlbpe_mchk_flush(t) <= ex3_n_tlb_mchk_flush_en(t) and ex3_tlb_par_err_q(t); + + ex3_n_tlb_mchk_flush(t) <= ex3_n_tlbmh_mchk_flush(t) or + ex3_n_tlbpe_mchk_flush(t); + + ex3_n_tlb_mchk_flush_en(t) <= ex3_n_mmu_mchk_flush_only and mmu_eratmiss_done_q(t); + ex3_n_ieratsx_par_mchk_mcint(t) <= ex3_xu_val(t) and iu_xu_ierat_ex3_par_err(t); + + ex3_n_iemh_mchk_mcint_xuuc(t) <= ex3_iu_error_q(6); + ex3_n_iepe_mchk_mcint_xuuc(t) <= ex3_iu_error_q(5); + ex3_n_il2ecc_mchk_mcint_xuuc(t) <= ex3_iu_error_q(2); + ex3_n_tlbmh_mchk_mcint(t) <= not ex3_n_tlb_mchk_flush_en(t) and ex3_tlb_multihit_err_q(t); + ex3_n_tlbpe_mchk_mcint(t) <= not ex3_n_tlb_mchk_flush_en(t) and ex3_tlb_par_err_q(t); + ex3_n_tlblru_mchk_mcint(t) <= ex3_tlb_lru_par_err_q(t); + ex3_n_tlbsrej_mchk_mcint(t) <= ex3_tlb_local_snoop_reject_q(t); + ex3_n_ieratre_par_mchk_mcint(t) <= ex5_xu_val_q(t) and ex5_ieratre_par_err_q(t); + + spare_5_d(t) <= not(ex3_n_tlbpe_mchk_mcint(t) or ex3_n_tlblru_mchk_mcint(t)); + + ex3_n_imchk_mcint(t) <=(ex3_xuuc_val(t) and (ex3_n_iemh_mchk_mcint_xuuc(t) or + ex3_n_iepe_mchk_mcint_xuuc(t) or + ex3_n_il2ecc_mchk_mcint_xuuc(t))) + or + ex3_n_tlbmh_mchk_mcint(t) or + ex3_n_tlbpe_mchk_mcint(t) or + ex3_n_tlblru_mchk_mcint(t) or + ex3_n_tlbsrej_mchk_mcint(t) or + ex3_n_ieratre_par_mchk_mcint(t); + + ex3_n_dexx_mchk_flush_en(t) <= ex3_n_mmu_mchk_flush_only and ex3_is_any_ldst; + + ex3_n_demh_mchk_mcint_xu(t) <= not ex3_n_dexx_mchk_flush_en(t) and lsu_xu_ex3_derat_multihit_err(t); + ex3_n_depe_mchk_mcint_xu(t) <= not ex3_n_dexx_mchk_flush_en(t) and lsu_xu_ex3_derat_par_err(t); + ex3_n_dl2ecc_mchk_mcint(t) <= lsu_xu_ex3_l2_uc_ecc_err(t); + ex3_n_ddpe_mchk_mcint_xu(t) <= lsu_xu_ex3_ddir_par_err and spr_xucr0_mddp; + ex3_n_deratre_par_mchk_mcint(t) <= ex5_xu_val_q(t) and ex5_deratre_par_err_q(t); + + ex3_n_dpovr_mchk_mcint(t) <= ex4_xu_val(t) and ex4_mtdp_nr_q and not lsu_xu_ex4_mtdp_cr_status; + ex3_n_dcpe_mchk_mcint(t) <= ex6_xu_val_q(t) and lsu_xu_ex6_datc_par_err and spr_xucr0_mdcp; + + + ex3_n_dmchk_mcint(t) <=(ex3_xu_val(t) and (ex3_n_demh_mchk_mcint_xu(t) or + ex3_n_depe_mchk_mcint_xu(t) or + ex3_n_ddpe_mchk_mcint_xu(t))) + or + ex3_n_dl2ecc_mchk_mcint(t) or + ex3_n_dpovr_mchk_mcint(t) or + ex3_n_dcpe_mchk_mcint(t) or + ex3_n_deratre_par_mchk_mcint(t); + + ex4_n_ddmh_mchk_en_d(t) <= ex3_xu_val(t) and dec_cpl_ex3_ddmh_en and spr_xucr4_mddmh; + ex4_n_ddmh_mchk_mcint(t) <= ex4_n_ddmh_mchk_en_q(t) and lsu_xu_ex4_n_lsu_ddmh_flush(t); + + ex3_np1_ext_mchk_mcint(t) <= external_mchk_q(t) and not ex3_async_int_block(t); + + ex3_ct(t) <=(spr_cpl_ex3_ct_le(t) and lsu_xu_ex3_attr(8)) or + (spr_cpl_ex3_ct_be(t) and not lsu_xu_ex3_attr(8)); + + ex3_dlk_dstor_cond0(t) <= msrp_uclep_q(t) and msr_gs_q(t); + ex3_dlk_dstor_cond1(t) <= not msr_ucle_q(t) and not msrp_uclep_q(t); + ex3_dlk_dstor_cond2(t) <= not msr_ucle_q(t) and not msr_gs_q(t); + + ex3_dlk_dstor_cond(t) <= ex3_dlk_dstor_cond0(t) or + ex3_dlk_dstor_cond1(t) or + ex3_dlk_dstor_cond2(t); + ex3_n_rwaccess_dstor_int(t) <= ex3_xuuc_val(t) and derat_xu_ex3_dsi(t); + ex3_n_i1w1lock_dstor_int(t) <= ex3_xu_val(t) and lsu_xu_ex3_dsi(t); + ex3_n_uct_dstor_int(t) <= ex3_xu_val(t) and ex3_is_icswx_q and not ex3_ct(t); + ex3_n_dlk0_dstor_int(t) <= ex3_xu_val(t) and msr_pr_q(t) and ex3_dlk_dstor_cond(t) and ex3_is_dlock_q; + ex3_n_dlk1_dstor_int(t) <= ex3_xu_val(t) and msr_pr_q(t) and ex3_dlk_dstor_cond(t) and ex3_is_ilock_q; + ex3_n_tlbi_dstor_int(t) <= ex3_tlb_inelig_q(t) and ex3_mmu_esr_data_q(t); + ex3_n_pt_dstor_int(t) <= ex3_tlb_pt_fault_q(t) and ex3_mmu_esr_data_q(t); + ex3_n_vf_dstor_int(t) <= ex3_xuuc_val(t) and lsu_xu_ex3_derat_vf and ex3_is_any_ldst; + ex3_n_dstor_int(t) <= ex3_n_rwaccess_dstor_int(t) or + ex3_n_i1w1lock_dstor_int(t) or + ex3_n_uct_dstor_int(t) or + ex3_n_dlk0_dstor_int(t) or + ex3_n_dlk1_dstor_int(t) or + ex3_n_tlbi_dstor_int(t) or + ex3_n_pt_dstor_int(t) or + ex3_n_vf_dstor_int(t); + + ex3_n_exaccess_istor_int(t) <= ex3_xuuc_val(t) and ex3_iu_error_q(4); + ex3_n_tlbi_istor_int(t) <= ex3_tlb_inelig_q(t) and not ex3_mmu_esr_data_q(t); + ex3_n_pt_istor_int(t) <= ex3_tlb_pt_fault_q(t) and not ex3_mmu_esr_data_q(t); + ex3_n_istor_int(t) <= ex3_n_exaccess_istor_int(t) or + ex3_n_tlbi_istor_int(t) or + ex3_n_pt_istor_int(t); + + ex3_np1_ext_int(t) <= spr_cpl_ext_interrupt(t) and not ex3_async_int_block(t); + + ex3_n_ldstmw_align_int(t) <= ex3_ucode_val(t) and ex3_n_align_int_q; + ex3_n_ldst_align_int(t) <= ex3_xu_val(t) and lsu_xu_ex3_align(t); + ex3_n_align_int(t) <= ex3_n_ldstmw_align_int(t) or + ex3_n_ldst_align_int(t); + + ex3_n_sprpil_prog_int_xu(t) <= spr_cpl_ex3_spr_illeg and not (spr_cpl_ex3_spr_priv and msr_pr_q(t)); + ex3_n_tlbpil_prog_int_xu(t) <= dec_cpl_ex3_tlb_illeg; + ex3_n_mmupil_prog_int_xu(t) <= mm_xu_illeg_instr(t) and not ex7_is_tlbwe_q(t); + ex3_n_xupil_prog_int_xuuc(t) <= ex3_illegal_op_q; + ex3_n_iupil_prog_int_xuuc(t) <= ex3_iu_error_q(1); + ex3_n_pil_prog_int(t) <=(ex3_xuuc_val(t) and (ex3_n_iupil_prog_int_xuuc(t) or + ex3_n_xupil_prog_int_xuuc(t))) + or + (ex3_xu_val(t) and (ex3_n_sprpil_prog_int_xu(t) or + ex3_n_tlbpil_prog_int_xu(t) or + ex3_n_mmupil_prog_int_xu(t))); + + ex3_n_tlbwe_pil_prog_int(t) <= ex3_tlb_illeg_q(t) and ex8_is_tlbwe_q(t); + + ex3_n_ppr_prog_int_en(t) <= msr_pr_q(t) and not (ex3_n_dlk0_dstor_int(t) or + ex3_n_dlk1_dstor_int(t)); + ex3_n_sprppr_prog_int_xuuc(t) <= spr_cpl_ex3_spr_priv; + ex3_n_instrppr_prog_int_xuuc(t) <= dec_cpl_ex3_instr_priv and not ex3_is_ehpriv_q; + ex3_n_ppr_prog_int(t) <= ex3_n_ppr_prog_int_en(t) and + ex3_xuuc_val(t) and (ex3_n_sprppr_prog_int_xuuc(t) or + ex3_n_instrppr_prog_int_xuuc(t)); + + ex3_n_puo_prog_int(t) <= (ex3_ucode_val(t) or ex3_n_2ucode_flush(t)) and spr_ccr2_ucode_dis; + + ex3_np1_ptr_prog_int(t) <= ex3_xu_val(t) and alu_cpl_ex3_trap_val and not (spr_dbcr0_trap(t) and msr_de_q(t) and dbcr0_idm_q(t) and debug_event_en_q(t)); + + ex3_n_fpena_prog_int(t) <= fu_xu_ex3_trap(t) and spr_cpl_fp_precise(t) and not ex3_async_int_block_noaxu(t); + ex3_n_apena_prog_int(t) <= ex3_any_val(t) and fu_xu_ex3_ap_int_req(t); + ex3_n_ena_prog_int(t) <= + ex3_n_fpena_prog_int(t) or + ex3_n_apena_prog_int(t); + + ex3_n_fu_fp_unavail_int_axu(t) <= ex3_axu_instr_type_q(2+3*t) and not msr_fp_q(t); + ex3_n_xu_fp_unavail_int_xuuc(t) <= dec_cpl_ex3_axu_instr_type(2) and not msr_fp_q(t); + ex3_n_fu_ap_unavail_int_axu(t) <= ex3_axu_instr_type_q(3*t) and not ccr2_ap_q(t); + ex3_n_xu_ap_unavail_int_xuuc(t) <= dec_cpl_ex3_axu_instr_type(0) and not ccr2_ap_q(t); + ex3_n_fu_vec_unavail_int_axu(t) <= ex3_axu_instr_type_q(1+3*t) and not msr_spv_q(t); + ex3_n_xu_vec_unavail_int_xuuc(t) <= dec_cpl_ex3_axu_instr_type(1) and not msr_spv_q(t); + ex3_n_fp_unavail_int(t) <=(ex3_axu_val(t) and ex3_n_fu_fp_unavail_int_axu(t)) or + (ex3_xuuc_val(t) and ex3_n_xu_fp_unavail_int_xuuc(t)); + + ex3_n_ap_unavail_int(t) <=(ex3_axu_val(t) and ex3_n_fu_ap_unavail_int_axu(t)) or + (ex3_xuuc_val(t) and ex3_n_xu_ap_unavail_int_xuuc(t)); + + ex3_n_vec_unavail_int(t) <=(ex3_axu_val(t) and ex3_n_fu_vec_unavail_int_axu(t)) or + (ex3_xuuc_val(t) and ex3_n_xu_vec_unavail_int_xuuc(t)); + + ex3_n_any_unavail_int(t) <=(ex3_axu_val(t) and (ex3_n_fu_fp_unavail_int_axu(t) or + ex3_n_fu_ap_unavail_int_axu(t) or + ex3_n_fu_vec_unavail_int_axu(t))) + or + (ex3_xuuc_val(t) and (ex3_n_xu_fp_unavail_int_xuuc(t) or + ex3_n_xu_ap_unavail_int_xuuc(t) or + ex3_n_xu_vec_unavail_int_xuuc(t))); + + ex3_np1_sc_int(t) <= ex3_xu_val(t) and ex3_is_sc_q; + ex3_np1_rfi(t) <= ex3_xu_val(t) and (ex3_is_rfmci_q or ex3_is_rfci_q or ex3_is_rfi_q or ex3_is_rfgi_q); + ex3_np1_instr_int(t) <= ex3_np1_ptr_prog_int(t) or + ex3_np1_sc_int(t) or + ex3_np1_rfi(t); + + ex3_np1_dec_int(t) <= spr_cpl_dec_interrupt(t) and not ex3_async_int_block(t); + + ex3_np1_fit_int(t) <= spr_cpl_fit_interrupt(t) and not ex3_async_int_block(t); + + ex3_np1_wdog_cint(t) <= spr_cpl_wdog_interrupt(t) and not ex3_async_int_block(t); + + ex3_n_deratmiss_dtlb_int(t) <= ex3_xuuc_val(t) and derat_xu_ex3_miss(t) and spr_ccr2_notlb; + ex3_n_tlbmiss_dtlb_int(t) <= ex3_tlb_miss_q(t) and ex3_mmu_esr_data_q(t) and not spr_ccr2_notlb; + ex3_n_dtlb_int(t) <= ex3_n_deratmiss_dtlb_int(t) or + ex3_n_tlbmiss_dtlb_int(t); + ex3_n_ieratmiss_itlb_int(t) <= ex3_xuuc_val(t) and ex3_iu_error_q(7) and spr_ccr2_notlb; + ex3_n_tlbmiss_itlb_int(t) <= ex3_tlb_miss_q(t) and not ex3_mmu_esr_data_q(t) and not spr_ccr2_notlb; + ex3_n_itlb_int(t) <= ex3_n_ieratmiss_itlb_int(t) or + ex3_n_tlbmiss_itlb_int(t); + + debug_event_en_d(t) <= not (spr_epcr_duvd(t) and not spr_msr_gs(t) and not spr_msr_pr(t)); + + ex3_n_brt_dbg_cint(t) <= ex3_xu_val(t) and ex3_br_update_q and spr_dbcr0_brt(t) and msr_de_q(t) and debug_event_en_q(t); + ex3_n_trap_dbg_cint(t) <= ex3_xu_val(t) and alu_cpl_ex3_trap_val and spr_dbcr0_trap(t) and debug_event_en_q(t); + ex3_n_ret_dbg_cint(t) <= ex3_xu_val(t) and (ex3_is_rfi_q or ex3_is_rfgi_q) and spr_dbcr0_ret(t) and debug_event_en_q(t); + + ex3_n_iac_dbg_cint(t) <= not ram_mode_q(t) and not ex5_in_ucode_q(t) and + ((ex3_xuuc_val(t) and not ex3_xu_is_ucode_q) or + (ex3_axu_val(t) and not ex3_axu_is_ucode_q(t))) and + (ex3_iac1_cmpr(t) or + ex3_iac2_cmpr(t) or + ex3_iac3_cmpr(t) or + ex3_iac4_cmpr(t)) and debug_event_en_q(t); + + ex3_n_async_dacr_dbg_cint(t) <= not ex3_async_int_block(t) and + (fxu_cpl_ex3_dac1r_cmpr_async(t) or + fxu_cpl_ex3_dac2r_cmpr_async(t)); + + ex3_n_dacr_dbg_cint_xu(t) <= fxu_cpl_ex3_dac1r_cmpr(t) or + fxu_cpl_ex3_dac2r_cmpr(t) or + fxu_cpl_ex3_dac3r_cmpr(t) or + fxu_cpl_ex3_dac4r_cmpr(t); + + ex3_n_dacw_dbg_cint_xu(t) <= fxu_cpl_ex3_dac1w_cmpr(t) or + fxu_cpl_ex3_dac2w_cmpr(t) or + fxu_cpl_ex3_dac3w_cmpr(t) or + fxu_cpl_ex3_dac4w_cmpr(t); + + ex3_n_dac_dbg_cint(t) <=(ex3_xu_val(t) and ( ex3_n_dacr_dbg_cint_xu(t) or + ex3_n_dacw_dbg_cint_xu(t))) and debug_event_en_q(t); + + + ex3_n_ivc_dbg_match(t) <= not ex5_in_ucode_q(t) and ( + (ex3_xuuc_val(t) and ex3_xu_instr_match_q and not ex3_xu_is_ucode_q) or + (ex3_axu_val(t) and ex3_axu_instr_match_q(t) and not ex3_axu_is_ucode_q(t))); + + ex3_n_ivc_dbg_cint(t) <= spr_dbcr3_ivc(t) and ex3_n_ivc_dbg_match(t) and debug_event_en_q(t); + + ex3_n_instr_dbg_cint(t) <= ex4_debug_flush_en_d(t) and (ex3_n_ivc_dbg_cint(t) or ex3_n_iac_dbg_cint(t)); + + ex3_np1_dbg_cint_en(t) <= not ex3_async_int_block(t); + ex3_np1_ide_dbg_cint(t) <= ex3_np1_dbg_cint_en(t) and debug_event_en_q(t) and + spr_cpl_dbsr_ide(t) and dbcr0_idm_q(t) and msr_de_q(t); + ex3_np1_ude_dbg_cint(t) <= ex3_np1_dbg_cint_en(t) and + force_ude_q(t) and debug_event_en_q(t); + + ex3_np1_ude_dbg_event(t) <= force_ude_q(t) and debug_event_en_q(t); + + + ex3_np1_dbell_int(t) <= spr_cpl_dbell_interrupt(t) and not ex3_async_int_block(t); + + ex3_np1_cdbell_cint(t) <= spr_cpl_cdbell_interrupt(t) and not ex3_async_int_block(t); + + ex3_np1_gdbell_int(t) <= spr_cpl_gdbell_interrupt(t) and not ex3_async_int_block(t); + + ex3_np1_gcdbell_cint(t) <= spr_cpl_gcdbell_interrupt(t) and not ex3_async_int_block(t); + + ex3_np1_gmcdbell_cint(t) <= spr_cpl_gmcdbell_interrupt(t) and not ex3_async_int_block(t); + + + msr_guest_priv(t) <= not msr_pr_q(t) and msr_gs_q(t); + ex3_n_spr_hpriv_int_xuuc(t) <= msr_guest_priv(t) and spr_cpl_ex3_spr_hypv; + ex3_n_instr_hpriv_int_xuuc(t) <= msr_guest_priv(t) and dec_cpl_ex3_instr_hypv; + ex3_n_ehpriv_hpriv_int(t) <= ex3_xu_val(t) and ex3_is_ehpriv_q; + ex3_n_mmu_hpriv_int(t) <= msr_guest_priv(t) and ex3_mmu_hv_priv_q(t); + ex4_n_any_hpriv_int_d(t) <=(ex3_xuuc_val(t) and (ex3_n_spr_hpriv_int_xuuc(t) or + ex3_n_instr_hpriv_int_xuuc(t))) + or + ex3_n_ehpriv_hpriv_int(t) or + ex3_n_mmu_hpriv_int(t); + + + ex3_n_ilrat_int(t) <= ex3_lrat_miss_q(t) and ex3_mmu_esr_pt_q(t) and not ex3_mmu_esr_data_q(t); + + ex3_n_ptemiss_dlrat_int(t) <= ex3_lrat_miss_q(t) and ex3_mmu_esr_pt_q(t) and ex3_mmu_esr_data_q(t); + ex3_n_tlbwemiss_dlrat_int(t) <= ex3_lrat_miss_q(t) and not ex3_mmu_esr_pt_q(t); + ex3_n_dlrat_int(t) <= ex3_n_ptemiss_dlrat_int(t) or + ex3_n_tlbwemiss_dlrat_int(t); + + + ex3_np1_udec_int(t) <= spr_cpl_udec_interrupt(t) and not ex3_async_int_block(t); + + ex3_np1_perf_int(t) <= spr_cpl_perf_interrupt(t) and not ex3_async_int_block(t); + + + ex3_np1_instr_flush(t) <= ex3_xu_val(t) and ex3_np1_instr_flush_q; + + ex3_np1_sprg_ce_flush(t) <= or_reduce(ex3_xu_val) and spr_cpl_ex3_sprg_ce; + + ex3_np1_fu_flush(t) <= not ex3_flush(t) and + not fu_xu_ex3_flush2ucode(t) and + fu_xu_ex3_np1_flush(t); + + ex3_np1_run_ctl_flush(t) <= or_reduce(ex3_xu_val) and ex3_np1_run_ctl_flush_q(t); + + ex3_non_uc_val(t) <=(ex3_xu_val(t) and not ex3_xu_is_ucode_q) or + (ex3_axu_val(t) and not ex3_axu_is_ucode_q(t)); + + ex3_np1_step_flush(t) <= ex4_step_q(t) and ex3_non_uc_val(t); + + ex3_np1_init_flush(t) <= pc_init_reset_q; + + ex3_np1_mtxucr0_flush(t) <= or_reduce(ex3_xu_val) and ex3_is_mtxucr0_q; + + ex3_np1_flush(t) <= ex3_np1_instr_flush(t) or + ex3_np1_mtiar_flush(t) or + ex3_np1_run_ctl_flush(t) or + ex3_np1_step_flush(t) or + ex3_np1_init_flush(t) or + ex3_np1_sprg_ce_flush(t) or + ex3_np1_mtxucr0_flush(t) or + slowspr_flush_q(t); + + ex3_n_imiss_flush(t) <= ex3_xuuc_val(t) and ex3_iu_error_q(7) and not spr_ccr2_notlb; + ex4_n_imiss_flush(t) <= ex4_n_flush_pri(IMISSn); + + ex3_n_dmiss_flush(t) <= ex3_xuuc_val(t) and derat_xu_ex3_miss(t) and not spr_ccr2_notlb; + ex4_n_dmiss_flush(t) <= ex4_n_flush_pri(DMISSn); + + + ex3_n_derat_dep_flush(t) <= ex3_xuuc_val(t) and derat_xu_ex3_n_flush_req(t); + ex3_n_lsu_dep_flush(t) <= (ex3_xuuc_val(t) or ex3_dep_val(t)) and lsu_xu_ex3_dep_flush; + ex3_n_fu_dep_flush(t) <= not ex3_flush(t) and + not fu_xu_ex3_flush2ucode(t) and + fu_xu_ex3_n_flush(t); + + ex3_n_dep_flush(t) <= ex3_n_lsu_dep_flush(t) or + ex3_n_derat_dep_flush(t) or + ex3_n_fu_dep_flush(t); + + ex3_n_ldq_hit_flush(t) <= lsu_xu_ex3_ldq_hit_flush; + + ex4_n_ldq_full_flush(t) <= ex4_xu_val_q(t) and lsu_xu_ex4_ldq_full_flush; + + + + + ex3_n_ram_flush(t) <= ram_flush_q(t); + ex3_n_mmuhold_flush(t) <= ex3_mmu_hold_val(t); + ex3_n_ici_flush(t) <= or_reduce(ex3_xu_val) and not ex3_xu_val(t) and ex3_is_ici_q; + ex3_n_dci_flush(t) <= or_reduce(ex3_xu_val) and not ex3_xu_val(t) and ex3_is_dci_q; + ex3_n_mmu_flush(t) <= mm_xu_ex3_flush_req(t); + ex3_n_thrctl_stop_flush(t) <= (pc_dbg_stop_q(t) and not pc_dbg_stop_2_q(t)) and not (ex5_in_ucode_q(t) or ex4_ucode_val(t)); + ex3_n_multcoll_flush(t) <= ex3_xu_val(t) and dec_cpl_ex3_mult_coll; + ex3_n_ierat_flush(t) <= ex3_anyuc_val(t) and ex3_ierat_flush_req_q(t); + + ex3_n_flush(t) <= ex3_n_ram_flush(t) or + ex3_n_mmuhold_flush(t) or + ex3_n_ici_flush(t) or + ex3_n_dci_flush(t) or + ex3_n_mmu_flush(t) or + ex3_n_ierat_flush(t) or + ex5_n_ext_dbg_stopc_flush_q or + ex3_n_thrctl_stop_flush(t) or + ex3_n_multcoll_flush(t); + + ex4_n_lsu_ddmh_flush_en_d(t) <= (or_reduce(ex3_xu_val) and dec_cpl_ex3_ddmh_en) or dec_cpl_ex3_back_inv; + ex4_n_lsu_ddmh_flush(t) <= ex4_n_lsu_ddmh_flush_en_q(t) and lsu_xu_ex4_n_lsu_ddmh_flush(t); + + ex3_n_lsu_flush(t) <= lsu_xu_ex3_n_flush_req; + ex4_n_lsu_flush(t) <= ex4_xu_val_q(t) and ex4_n_lsu_flush_q(t); + + ex3_n_demh_mchk_flush(t) <= ex3_n_dexx_mchk_flush_en(t) and ex3_xu_val(t) and lsu_xu_ex3_derat_multihit_err(t); + ex3_n_depe_mchk_flush(t) <= ex3_n_dexx_mchk_flush_en(t) and ex3_xu_val(t) and lsu_xu_ex3_derat_par_err(t); + ex3_n_lsu_dcpe_flush(t) <= or_reduce(ex6_xu_val_q) and lsu_xu_ex6_datc_par_err; + ex3_n_lsu_ddpe_flush(t) <= or_reduce(ex3_xu_val) and lsu_xu_ex3_ddir_par_err; + ex3_n_fu_rfpe_flush(t) <= or_reduce(ex3_n_fu_rfpe_det); + ex3_n_xu_rfpe_flush(t) <= or_reduce(ex3_xuuc_val or ex3_dep_val) and gpr_cpl_ex3_regfile_err_det; + ex3_n_sprg_ue_flush(t) <= ex3_xu_val(t) and spr_cpl_ex3_sprg_ue; + + ex3_n_pe_flush(t) <= ex3_n_l2_ecc_err_flush_q(t) or + ex3_n_dcpe_flush_q(t) or + ex3_n_lsu_dcpe_flush(t) or + ex3_n_lsu_ddpe_flush(t) or + ex3_n_fu_rfpe_flush(t) or + ex3_n_xu_rfpe_flush(t) or + ex3_n_sprg_ue_flush(t) or + ex3_n_demh_mchk_flush(t) or + ex3_n_depe_mchk_flush(t); + + ex3_n_lsualign_2ucode_flush(t) <= ex3_xu_val(t) and lsu_xu_ex3_inval_align_2ucode; + ex3_n_fu_2ucode_flush(t) <= not ex3_flush(t) and + fu_xu_ex3_flush2ucode(t) and + fu_xu_ex3_n_flush(t); + ex3_n_2ucode_flush(t) <= ex3_n_lsualign_2ucode_flush(t) or + ex3_n_fu_2ucode_flush(t); + + ex3_div_coll_d(t) <= fxa_cpl_ex2_div_coll(t) and not any_flush(t); + ex3_div_coll(t) <= ex3_div_coll_q(t) and not any_flush(t); + + ex3_n_barr_flush(t) <= ex3_xu_val(t) and or_reduce(ex3_div_coll); + + + ex5_step_done(t) <= ex4_step_q(t) and (ex5_instr_cpl_q(t) or ex5_is_any_int(t) or ex5_n_ext_dbg_stopc_flush_q or ex5_n_ext_dbg_stopt_flush_q(t)); + ex4_np1_run_ctl_flush(t) <= or_reduce(ex4_xu_val) and ex4_np1_run_ctl_flush_q(t); + ex4_attn_flush(t) <= ex4_xu_val(t) and ex4_is_attn_q; + + ex3_thread_stop(t) <= ex5_step_done(t) or + ex5_np1_run_ctl_flush_q(t) or + ex4_n_thrctl_stop_flush_q(t) or + ex5_attn_flush_q(t); + + ex5_csi(t) <=(ex5_xu_val_q(t) and (ex5_is_mtmsr_q or ex5_is_isync_q)) or + ex5_is_any_int(t) or + ex5_is_any_rfi_q(t); + + ex4_flush_act(t) <= ex4_n_flush(t) or ex4_np1_flush(t); + + hold_state_0(t) <= mmu_hold_present_q(t) or + derat_hold_present_q(t) or + ierat_hold_present_q(t) or + ex5_np1_irpt_dbg_cint_q(t); + + mmu_hold_request_d(t) <= mm_xu_hold_req(t) or (mmu_hold_request_q(t) and or_reduce(ex3_hold_block)); + ex3_mmu_hold_val(t) <= mmu_hold_request_q(t) and not or_reduce(ex3_hold_block); + xu_mm_hold_ack(t) <= ex6_mmu_hold_val_q(t); + + mmu_hold_present_d(t) <= ex3_mmu_hold_val(t) or (mmu_hold_present_q(t) and not mm_xu_hold_done(t)); + ierat_hold_present_d(t) <= ex4_n_imiss_flush(t) or (ierat_hold_present_q(t) and not mmu_eratmiss_done_q(t)); + derat_hold_present_d(t) <= ex4_n_dmiss_flush(t) or (derat_hold_present_q(t) and not mmu_eratmiss_done_q(t)); + + ext_dbg_stop_n_d(t) <=((pc_dbg_action_q(3*t to 3*t+2) = "010") or + (pc_dbg_action_q(3*t to 3*t+2) = "110")); + ext_dbg_stop_core_d(t) <=((pc_dbg_action_q(3*t to 3*t+2) = "011") or + (pc_dbg_action_q(3*t to 3*t+2) = "111")); + ext_dbg_act_err_d(t) <= pc_dbg_action_q(3*t to 3*t+2) = "100"; + ext_dbg_act_ext_d(t) <=((pc_dbg_action_q(3*t to 3*t+2) = "101") or + (pc_dbg_action_q(3*t to 3*t+2) = "110") or + (pc_dbg_action_q(3*t to 3*t+2) = "111")); + + cpl_spr_dbcr0_edm(t) <= or_reduce(pc_dbg_action_q(3*t to 3*t+2)); + + pc_dbg_stop_d(t) <= pc_xu_stop(t) and not ex5_in_ucode_q(t); + + ex5_ext_dbg_err_d(t) <= ext_dbg_act_err_q(t) and ex4_dbsr_update(t); + ex5_ext_dbg_ext_d(t) <= ext_dbg_act_ext_q(t) and ex4_dbsr_update(t); + + ex4_step_d(t) <= pc_xu_step(t); + + ex3_ifar <= ex3_ifar_q(eff_ifar*t to eff_ifar*(t+1)-1); + ex4_ifar <= ex4_ifar_q(eff_ifar*t to eff_ifar*(t+1)-1); + + ex3_spr_lr <= spr_lr(regsize*t to regsize*(t+1)-3); + + ex3_lr_cmprl(t) <= '1' when ex3_ifar(32 to 61) = ex3_spr_lr(32 to 61) else '0'; + ex3_cia_cmprl(t) <= '1' when ex3_ifar(32 to 61) = ex4_cia(32 to 61) else '0'; + ex4_cia_cmprl(t) <= '1' when ex4_ifar(32 to 61) = ex4_cia(32 to 61) else '0'; + xuq_cpl_cmprh_gen0 : if IFAR'left < 32 generate + ex3_lr_cmprh(t) <= '1' when ex3_ifar(IFAR'left to 31) = ex3_spr_lr(IFAR'left to 31) else '0'; + ex3_cia_cmprh(t) <= '1' when ex3_ifar(IFAR'left to 31) = ex4_cia(IFAR'left to 31) else '0'; + ex4_cia_cmprh(t) <= '1' when ex4_ifar(IFAR'left to 31) = ex4_cia(IFAR'left to 31) else '0'; + end generate; + xuq_cpl_cmprh_gen1 : if IFAR'left >= 32 generate + ex3_lr_cmprh(t) <= '1'; + ex3_cia_cmprh(t) <= '1'; + ex4_cia_cmprh(t) <= '1'; + end generate; + + ex3_lr_cmpr(t) <= ex3_anyuc_val_q(t) and ex3_lr_cmprl(t) and (ex3_lr_cmprh(t) or not msr_cm_q(t)); + ex3_cia_cmpr(t) <= ex3_anyuc_val_q(t) and ex3_cia_cmprl(t) and (ex3_cia_cmprh(t) or not msr_cm_q(t)); + ex4_cia_cmpr(t) <= ex4_anyuc_val_q(t) and ex4_cia_cmprl(t) and (ex4_cia_cmprh(t) or not msr_cm_q(t)); + + ex4_clear_bclr_chk(t) <= (ex4_anyuc_val_q(t) and not ram_mode_q(t)) or ex5_late_flush_q(0)(t); + + ex4_taken_bclr(t) <= (ex4_taken_bclr_q and ex4_xu_val(t)); + ex5_check_bclr_d(t) <= (ex5_check_bclr_q(t) and not ex4_clear_bclr_chk(t)) or + ex4_taken_bclr(t); + + ex5_check_bclr(t) <= ex5_check_bclr_q(t) and not ex4_clear_bclr_chk(t); + + ex3_bclr_cmpr_b(t) <= (not ex3_lr_cmpr(t) and ex4_taken_bclr(t)) or + (not ex3_cia_cmpr(t) and ex5_check_bclr(t)); + + ex3_n_bclr_ta_miscmpr_flush(t) <= not ram_mode_q(t) and ex3_anyuc_val(t) and ex3_bclr_cmpr_b(t); + + ex4_check_cia(t) <=((ex4_xu_val_q(t) or ex4_axu_val_q(t)) and not ex5_in_ucode_q(t)) or + ex4_ucode_val_q(t); + + ex5_err_nia_miscmpr_d(t) <= ex4_instr_cpl(t) and ex4_check_cia(t) and not ex4_cia_cmpr(t) and not (ex4_taken_bclr(t) or ex5_check_bclr_q(t)); + + ex4_mem_attr_act(t) <= ex4_ucode_val(t); + + ex4_mem_attr_val(t) <=(ex4_ucode_val(t) and (ex4_is_any_store_dac_q or ex4_is_any_load_dac_q)) or + (ex5_mem_attr_val_q(t) and ex5_in_ucode_q(t)); + + ex3_mem_attr_cmpr(t) <= '1' when lsu_xu_ex3_attr = ex5_mem_attr_q else '0'; + + ex3_mem_attr_chk(t) <= ex5_in_ucode_q(t) and ex5_mem_attr_val_q(t) and + (ex3_xu_val(t) and (ex3_is_any_store_dac_q or + ex3_is_any_load_dac_q)); + + ex3_n_memattr_miscmpr_flush(t) <= ex3_mem_attr_chk(t) and not ex3_mem_attr_cmpr(t); + + ex5_mem_attr_le_d(t) <= ex4_mem_attr_q(8) xor ex4_byte_rev_q; + + ex4_ucode_end(t) <= ex5_in_ucode_q(t) and ((ex4_xu_val_q(t) and not ex4_xu_is_ucode_q) or + (ex4_axu_val_q(t) and not ex4_axu_is_ucode_q(t)) or + ex5_is_any_int(t)); + + ex5_in_ucode_d(t) <= ex4_ucode_val(t) or (ex5_in_ucode_q(t) and not (((ex4_np1_flush(t) or ex4_n_flush(t)) and ex4_ucode_restart(t)) or ex5_is_any_int(t))); + + ssprwr_ip_d(t) <=(ex4_xu_val(t) and ex4_is_slowspr_wr_q) or + (ssprwr_ip_q(t) and not mux_cpl_slowspr_done(t)); + + exx_instr_async_block_d(t)(1) <= rf1_xu_val(t) and (rf1_is_wait or rf1_is_eratre or rf1_is_tlbwe or rf1_is_tlbre or rf1_is_tlbsx or rf1_is_tlbsrx); + exx_instr_async_block_d(t)(2 to 7) <= exx_instr_async_block_q(t)(1 to 6); + + + ex3_async_int_block_cond(t) <= (ex2_xu_val_q(t) and (ex2_msr_updater or ex2_mtiar or ex2_is_slowspr_wr_q)) or + or_reduce(exx_instr_async_block_q(t)) or + ex4_n_flush_cond(IMISSn) or ex4_n_flush_cond(DMISSn); + + ex3_base_int_block_cond(t) <= ex4_is_mchk_int(t) or ex4_is_crit_int(t) or ex4_is_base_int(t); + ex3_mchk_int_block_cond(t) <= ex4_is_mchk_int(t); + + ex3_hold_block(t) <= ssprwr_ip_q(t) or + ex5_in_ucode_q(t); + + ex3_async_int_block_noaxu(t) <= + ssprwr_ip_q(t) or + ram_mode_q(t) or + ex5_in_ucode_q(t) or + ex3_async_int_block_q(t) or + exx_hold0_mcflush(t) or + exx_hold1_mcflush(t) or + ex4_async_block(t) or + ex4_base_int_block_q(t) or + spare_4_q(4+t); + + + ex3_async_int_block(t) <= ex3_async_int_block_noaxu(t) or ex3_axu_async_block_q(t) or ex4_icmp_async_block(t); + + + + ex3_debug_int_en(t) <= msr_de_q(t) and dbcr0_idm_q(t) and not (ex4_is_crit_int(t) or ex4_is_mchk_int(t) or ext_dbg_stop_n_q(t) or ext_dbg_stop_core_q(t)); + + ex4_debug_flush_en_d(t) <= ex3_debug_int_en(t) or ext_dbg_stop_n_q(t) or ext_dbg_stop_core_q(t); + + ex3_esr_bit_act(t) <= not (ex3_flush(t) and not ex4_n_flush_pri(F2Un)) and + (ex3_ucode_val_q(t) or + (ex3_xu_val_q(t) and not (ex5_in_ucode_q(t) or ex3_xu_is_ucode_q )) or + (ex3_axu_val_q(t) and not (ex5_in_ucode_q(t) or ex3_axu_is_ucode_q(t)))); + + ex5_sel_rt_d(t) <= ex4_np1_mtiar_flush(t) or ex4_is_any_rfi(t); + + with s3'(ex5_is_any_hint(t) & ex5_is_any_gint(t) & ex5_sel_rt_q(t)) select + ex5_flush_ifar <= spr_ivpr(62-eff_ifar to 51) & ex5_ivo & "00" when "100", + spr_givpr(62-eff_ifar to 51) & ex5_ivo & "00" when "010", + ex5_rt_q(62-eff_ifar to 61) when others; + + + flush_ifar_repwr : for r in 1 to ifar_repwr-1 generate + with (ex5_late_flush_q(r)(t)) select + flush_ifar(64-8*(r+1) to 63-8*r) <= not ex4_cia_b_q(64-8*(r+1) to 63-8*r) when '1', + ex2_br_flush_ifar(64-8*(r+1) to 63-8*r) when others; + end generate; + with (ex5_late_flush_q(0)(t)) select + flush_ifar(56 to 61) <= not ex4_cia_b_q(56 to 61) when '1', + ex2_br_flush_ifar(56 to 61) when others; + + ex4_instr_cpl_d(t) <=((ex3_xu_val(t) and not ex3_xu_is_ucode_q) or + (ex3_axu_val(t) and not ex3_axu_is_ucode_q(t))); + + ex4_instr_cpl(t) <= not ram_mode_q(t) and ex4_instr_cpl_q(t) and not ex4_flush(t); + ex4_ram_cpl(t) <= ex4_instr_cpl_q(t) and not ex4_flush(t); + + ex5_flush_update(t) <= ex5_is_any_int(t) or ex5_is_any_rfi_q(t) or ex5_sel_rt_q(t); + + with (ex4_xu_val_q(t) and ex4_br_update_q) select + ex4_nia_instr <= ex4_br_flush_ifar_q when '1', + ex4_cia_p1 when others; + + with ex5_flush_update(t) select + ex4_cia_flush <= ex5_flush_ifar when '1', + ex4_cia when others; + + with (ex4_instr_cpl(t)) select + ex4_nia_cpl <= (ex4_nia_instr and ex4_cm_mask) when '1', + (ex4_cia_flush and ex4_cm_mask) when others; + + ex4_nia <= ex4_nia_cpl; + ex4_cia <= not ex4_cia_b_q; + ex4_cia_b_d <= not ex4_nia; + + ex4_cia_p1 <= std_ulogic_vector(unsigned(ex4_cia) + 1); + + ex5_cm_hold_cond(t) <= (ex5_xu_val_q(t) and ex5_is_mtmsr_q) or ex5_is_any_int(t) or ex5_is_any_rfi_q(t); + + ex4_cm(t) <= msr_cm_q(t) or exx_cm_hold(t); + + ex4_cm_mask(32 to 61) <= (others=>'1'); + xuq_cpl_cm_mask_gen : if IFAR'left < 32 generate + ex4_cm_mask(IFAR'left to 31) <= (others=>ex4_cm(t)); + end generate; + + ex3_cia_act(t) <= ex4_instr_cpl_q(t) or ex5_flush_update(t) or exx_cm_hold(t) or exx_cm_hold_q(t) or spr_xucr0_clkg_ctl(2); + + ex4_nia_act(t) <= ex4_cia_act_q(t) or ex3_cia_act(t) or ex4_n_flush(t) or ex4_np1_flush(t); + + ex5_uc_cia_val_d(t) <= ex5_in_ucode_q(t) and ex4_uc_cia_val(t); + ex4_uc_cia_val(t) <= ex5_in_ucode_q(t) and (ex5_uc_cia_val_q(t) or ex4_any_val(t)); + + ex3_uc_cia_act(t) <= clkg_ctl_q or (ex5_in_ucode_q(t) and (ex4_xu_val_q(t) or ex4_axu_val_q(t))); + + with (ex4_xu_val_q(t) or ex4_axu_val_q(t)) select + ex4_uc_nia <= ex4_ifar(IFAR_UC'range) when '1', + ex4_uc_cia_q when others; + + with ex4_n_flush(t) select + ex4_uc_cia_d <= ex4_uc_cia_q when '1', + ex4_uc_nia when others; + + xu_iu_uc_flush_ifar(uc_ifar*t to uc_ifar*(t+1)-1) <= ex4_uc_cia_q; + + ex4_dbsr_cond(0) <= ex4_n_ivc_dbg_cint_q(t) or + ex4_n_iac_dbg_cint_q(t); + + ex4_dbsr_cond(1) <= ex4_n_dac_dbg_cint_q(t) or + ex4_n_ret_dbg_cint_q(t) or + ex4_n_brt_dbg_cint_q(t) or + ex4_n_trap_dbg_cint_q(t); + + ex4_dbsr_en_cond(0) <= ex4_anyuc_val(t) or ex4_n_flush_pri(DBG0n); + ex4_dbsr_en_cond(1) <= ex4_anyuc_val(t) or ex4_n_flush_pri(DBG1n); + + ex4_n_flush_cond(PREVn) <= exx_np1_irpt_dbg_cint(t) or exx_np1_icmp_dbg_cint(t) or (ex4_debug_flush_en_q(t) and ex4_n_async_dacr_dbg_cint_q(t)); + ex4_n_flush_cond(BTAn) <= ex4_n_bclr_ta_miscmpr_flush_q(t); + ex4_n_flush_cond(DEPn) <= ex4_n_dep_flush_q(t) or ex4_n_tlb_mchk_flush_q(t); + ex4_n_flush_cond(IMISSn) <= ex4_n_imiss_flush_q(t); + ex4_n_flush_cond(IMCHKn) <= ex4_n_imchk_mcint_q(t) or ex4_n_ieratsx_par_mchk_mcint_q(t); + ex4_n_flush_cond(DBG0n) <= ex4_n_instr_dbg_cint_q(t); + ex4_n_flush_cond(ITLBn) <= ex4_n_itlb_int_q(t); + ex4_n_flush_cond(ISTORn) <= ex4_n_istor_int_q(t); + ex4_n_flush_cond(ILRATn) <= ex4_n_ilrat_int_q(t); + ex4_n_flush_cond(FPEn) <= ex4_n_pe_flush_q(t) or ex4_n_lsu_ddmh_flush(t); + ex4_n_flush_cond(PROG0n) <= ex4_n_pil_prog_int_q(t); + ex4_n_flush_cond(UNAVAILn) <= ex4_n_any_unavail_int_q(t); + ex4_n_flush_cond(PROG1n) <= ex4_n_ppr_prog_int_q(t); + ex4_n_flush_cond(PROG2n) <= ex4_n_puo_prog_int_q(t); + ex4_n_flush_cond(PROG3n) <= ex4_n_ena_prog_int_q(t); + ex4_n_flush_cond(HPRIVn) <= ex4_n_any_hpriv_int_q(t); + ex4_n_flush_cond(PROG0An) <= ex4_n_tlbwe_pil_prog_int_q(t); + ex4_n_flush_cond(DMCHKn) <= ex4_n_dmchk_mcint_q(t) or ex4_n_ddmh_mchk_mcint(t); + ex4_n_flush_cond(DTLBn) <= ex4_n_dtlb_int_q(t); + ex4_n_flush_cond(DMISSn) <= ex4_n_dmiss_flush_q(t); + ex4_n_flush_cond(DSTORn) <= ex4_n_dstor_int_q(t); + ex4_n_flush_cond(ALIGNn) <= ex4_n_align_int_q(t) or ex4_n_memattr_miscmpr_flush_q(t); + ex4_n_flush_cond(DLRATn) <= ex4_n_dlrat_int_q(t); + ex4_n_flush_cond(DBG1n) <= ex4_debug_flush_en_q(t) and ex4_dbsr_cond(1); + ex4_n_flush_cond(F2Un) <= ex4_n_2ucode_flush_q(t); + ex4_n_flush_cond(FwBSn) <= ex4_n_barr_flush_q(t) or (ex4_xu_val_q(t) and ex4_n_ldq_hit_flush_q(t)); + ex4_n_flush_cond(Fn) <= ex4_n_flush_q(t) or ex4_n_ldq_full_flush(t) or ex4_n_lsu_flush(t) or ex4_thread_stop_q(t); + + ex4_np1_flush_cond(INSTRnp1) <= ex4_np1_instr_int_q(t); + ex4_np1_flush_cond(MCHKnp1) <= ex4_np1_ext_mchk_mcint_q(t); + ex4_np1_flush_cond(GDBMCHKnp1) <= ex4_np1_gmcdbell_cint_q(t); + ex4_np1_flush_cond(DBG3np1) <= ex4_debug_flush_en_q(t) and (ex4_np1_ide_dbg_cint_q(t) or ex4_np1_ude_dbg_cint_q(t)); + ex4_np1_flush_cond(CRITnp1) <= ex4_np1_crit_cint_q(t); + ex4_np1_flush_cond(WDOGnp1) <= ex4_np1_wdog_cint_q(t); + ex4_np1_flush_cond(CDBELLnp1) <= ex4_np1_cdbell_cint_q(t); + ex4_np1_flush_cond(GCDBELLnp1) <= ex4_np1_gcdbell_cint_q(t); + ex4_np1_flush_cond(EXTnp1) <= ex4_np1_ext_int_q(t); + ex4_np1_flush_cond(FITnp1) <= ex4_np1_fit_int_q(t); + ex4_np1_flush_cond(DECnp1) <= ex4_np1_dec_int_q(t); + ex4_np1_flush_cond(DBELLnp1) <= ex4_np1_dbell_int_q(t); + ex4_np1_flush_cond(GDBELLnp1) <= ex4_np1_gdbell_int_q(t); + ex4_np1_flush_cond(UDECnp1) <= ex4_np1_udec_int_q(t); + ex4_np1_flush_cond(PERFnp1) <= ex4_np1_perf_int_q(t); + ex4_np1_flush_cond(Fnp1) <= ex4_np1_flush_q(t) or ex4_ucode_end(t) or ex4_np1_fu_flush_q(t); + + xu_cpl_n_pri : entity work.xuq_cpl_pri(xuq_cpl_pri) + generic map (size => ex4_n_flush_cond'length) + port map( + cond => ex4_n_flush_cond, + pri => ex4_n_flush_pri, + or_cond => ex4_n_flush(t)); + + xu_cpl_np1_pri : entity work.xuq_cpl_pri(xuq_cpl_pri) + generic map (size => ex4_np1_flush_cond'length) + port map( + cond => ex4_np1_flush_cond, + pri => ex4_np1_flush_pri_nongated, + or_cond => ex4_np1_flush(t)); + + ex4_np1_flush_pri <= gate(ex4_np1_flush_pri_nongated,(not ex4_n_flush(t))); + + ex4_flush_pri <= ex4_n_flush_pri & ex4_np1_flush_pri; + + ex4_async_block(t) <= ex4_n_flush(t) or ex4_np1_flush(t); + + xu_lsu_ex4_val(t) <= ex4_xu_val_q(t); + + xu_lsu_ex4_flush_local(t) <= or_reduce(ex4_n_flush_cond(PREVn to ISTORn)) or + ex4_n_flush_cond(PROG0n) or + ex4_n_flush_cond(PROG1n) or + ex4_n_flush_cond(UNAVAILn) or + ex4_n_flush_cond(PROG3n) or + ex4_n_dmchk_mcint_q(t) or + or_reduce(ex4_n_flush_cond(DTLBn to ALIGNn)) or + (ex4_debug_flush_en_q(t) and ex4_n_dac_dbg_cint_q(t)) or + ex4_n_flush_cond(F2Un) or + ex4_n_flush_cond(FPEn) or + (ex4_xu_val_q(t) and ex4_n_ldq_hit_flush_q(t)) or + ex4_n_flush_q(t) or ex4_n_lsu_flush(t) or + ex4_thread_stop_q(t) or + ex4_flush_q(t); + + ex5_flush_pri_enc_dbg(t) <= gate("000001",ex5_flush_pri_dbg_q(0)) or + gate("000010",ex5_flush_pri_dbg_q(1)) or + gate("000011",ex5_flush_pri_dbg_q(2)) or + gate("000100",ex5_flush_pri_dbg_q(3)) or + gate("000101",ex5_flush_pri_dbg_q(4)) or + gate("000110",ex5_flush_pri_dbg_q(5)) or + gate("000111",ex5_flush_pri_dbg_q(6)) or + gate("001000",ex5_flush_pri_dbg_q(7)) or + gate("001001",ex5_flush_pri_dbg_q(8)) or + gate("001010",ex5_flush_pri_dbg_q(9)) or + gate("001011",ex5_flush_pri_dbg_q(10)) or + gate("001100",ex5_flush_pri_dbg_q(11)) or + gate("001101",ex5_flush_pri_dbg_q(12)) or + gate("001110",ex5_flush_pri_dbg_q(13)) or + gate("001111",ex5_flush_pri_dbg_q(14)) or + gate("010000",ex5_flush_pri_dbg_q(15)) or + gate("010001",ex5_flush_pri_dbg_q(16)) or + gate("010010",ex5_flush_pri_dbg_q(17)) or + gate("010011",ex5_flush_pri_dbg_q(18)) or + gate("010100",ex5_flush_pri_dbg_q(19)) or + gate("010101",ex5_flush_pri_dbg_q(20)) or + gate("010110",ex5_flush_pri_dbg_q(21)) or + gate("010111",ex5_flush_pri_dbg_q(22)) or + gate("011000",ex5_flush_pri_dbg_q(23)) or + gate("011001",ex5_flush_pri_dbg_q(24)) or + gate("011010",ex5_flush_pri_dbg_q(25)) or + gate("011011",ex5_flush_pri_dbg_q(26)) or + gate("011100",ex5_flush_pri_dbg_q(27)) or + gate("011101",ex5_flush_pri_dbg_q(28)) or + gate("011110",ex5_flush_pri_dbg_q(29)) or + gate("011111",ex5_flush_pri_dbg_q(30)) or + gate("100000",ex5_flush_pri_dbg_q(31)) or + gate("100001",ex5_flush_pri_dbg_q(32)) or + gate("100010",ex5_flush_pri_dbg_q(33)) or + gate("100011",ex5_flush_pri_dbg_q(34)) or + gate("100100",ex5_flush_pri_dbg_q(35)) or + gate("100101",ex5_flush_pri_dbg_q(36)) or + gate("100110",ex5_flush_pri_dbg_q(37)) or + gate("100111",ex5_flush_pri_dbg_q(38)) or + gate("101000",ex5_flush_pri_dbg_q(39)) or + gate("101001",ex5_flush_pri_dbg_q(40)) or + gate("101010",ex5_flush_pri_dbg_q(41)) or + gate("101011",ex5_flush_pri_dbg_q(42)); + + + ex4_n_flush_pri_dacr_async(t) <= ex4_n_flush_cond(PREVn) and ex4_n_async_dacr_dbg_cint_q(t); + + ex4_np1_flush_pri_instr(TRAP) <= not ex4_n_flush(t) and ex4_np1_ptr_prog_int_q(t); + ex4_np1_flush_pri_instr(SC) <= not ex4_n_flush(t) and ex4_np1_sc_int_q(t); + ex4_np1_flush_pri_instr(RFI) <= not ex4_n_flush(t) and ex4_np1_rfi_q(t); + + ex4_n_flush_pri_unavail(FP) <= ex4_n_flush_pri(UNAVAILn) and ex4_n_fp_unavail_int_q(t); + ex4_n_flush_pri_unavail(AP) <= ex4_n_flush_pri(UNAVAILn) and ex4_n_ap_unavail_int_q(t); + ex4_n_flush_pri_unavail(VEC) <= ex4_n_flush_pri(UNAVAILn) and ex4_n_vec_unavail_int_q(t); + + ex4_n_flush_pri_ena(APENA) <= ex4_n_flush_pri(PROG3n) and ex4_apena_prog_int_q(t); + ex4_n_flush_pri_ena(FPENA) <= ex4_n_flush_pri(PROG3n) and ex4_fpena_prog_int_q(t); + + ex4_n_flush_pri_ehpriv(t) <= ex4_n_flush_pri(HPRIVn) and ex4_is_ehpriv_q; + + ex4_n_flush_sprg_ue_flush(t) <= ex4_n_flush_pri(FPEn) and ex4_n_sprg_ue_flush_q(t); + + + ex4_icmp_event_on_int_ok(t) <= ex4_n_flush_pri_ehpriv(t) or ex4_np1_flush_pri_instr(SC) or ex4_np1_flush_pri_instr(TRAP); + + ex4_np1_icmp_dbg_en(t) <= spr_dbcr0_icmp(t) and msr_de_q(t) and debug_event_en_q(t); + ex4_np1_icmp_dbg_event(t) <= ex4_np1_icmp_dbg_en(t) and (ex4_instr_cpl(t) or ex4_icmp_event_on_int_ok(t)); + ex4_np1_icmp_dbg_cint(t) <= ex4_np1_icmp_dbg_en(t) and ex4_instr_cpl(t) and ex4_debug_flush_en_q(t); + + ex4_icmp_async_block(t) <=(ex4_np1_icmp_dbg_en(t) and (ex3_anyuc_val_q(t) or ex4_instr_cpl_q(t))) or ex5_np1_icmp_dbg_cint_q(t); + + ex5_np1_icmp_dbg_event_d(t) <=(ex4_np1_icmp_dbg_event(t) and not ((ex5_is_any_int(t) and not ex5_icmp_event_on_int_ok_q(t)) or ex4_thread_stop_q(t))) or + (ex5_np1_icmp_dbg_event_q(t) and not (ex4_anyuc_val_q(t) or (ex5_is_any_int(t) or ex4_thread_stop_q(t)))); + + ex5_np1_icmp_dbg_cint_d(t) <=(ex4_np1_icmp_dbg_cint(t) and not (ex5_is_any_int(t) or ex4_thread_stop_q(t))) or + (ex5_np1_icmp_dbg_cint_q(t) and not (ex4_anyuc_val_q(t) or ex5_is_any_int(t) or ex4_thread_stop_q(t))); + + exx_np1_icmp_dbg_cint(t) <= ex5_np1_icmp_dbg_cint_q(t) and (ex4_anyuc_val_q(t) or ex4_thread_stop_q(t)); + exx_np1_icmp_dbg_event(t) <= ex5_np1_icmp_dbg_event_q(t) and (ex4_anyuc_val_q(t) or ex4_thread_stop_q(t) or (ex5_is_any_int(t) and ex5_icmp_event_on_int_ok_q(t))); + + ex4_n_flush_pri_icmp(t) <= ex4_n_flush_pri(PREVn) and exx_np1_icmp_dbg_cint(t); + + + ex4_np1_irpt_dbg_cint(t) <= ex4_is_base_int(t) and debug_event_en_q(t) and spr_dbcr0_irpt(t) and ex4_debug_flush_en_q(t); + ex4_np1_irpt_dbg_event(t) <= ex4_is_base_int(t) and debug_event_en_q(t) and spr_dbcr0_irpt(t); + + ex6_np1_irpt_dbg_cint_d(t) <= ex5_np1_irpt_dbg_cint_q(t) or + (ex6_np1_irpt_dbg_cint_q(t) and ex4_base_int_block_q(t)); + exx_np1_irpt_dbg_cint(t) <= ex6_np1_irpt_dbg_cint_q(t) and not ex4_base_int_block_q(t); + + ex6_np1_irpt_dbg_event_d(t) <= ex5_np1_irpt_dbg_event_q(t) or + (ex6_np1_irpt_dbg_event_q(t) and ex4_base_int_block_q(t)); + exx_np1_irpt_dbg_event(t) <= ex6_np1_irpt_dbg_event_q(t) and not ex4_base_int_block_q(t); + + ex4_n_flush_pri_irpt(t) <= ex4_n_flush_pri(PREVn) and exx_np1_irpt_dbg_cint(t); + + + ex4_ivo_sel(0) <= ex4_np1_flush_pri(CRITnp1); + ex4_ivo_sel(1) <= ex4_mchk_int_en_q(t) and (ex4_n_flush_pri(IMCHKn) or ex4_n_flush_pri(DMCHKn) or ex4_np1_flush_pri(MCHKnp1)); + ex4_ivo_sel(2) <= ex4_n_flush_pri(DSTORn); + ex4_ivo_sel(3) <= ex4_n_flush_pri(ISTORn); + ex4_ivo_sel(4) <= ex4_np1_flush_pri(EXTnp1); + ex4_ivo_sel(5) <= ex4_n_flush_pri(ALIGNn); + ex4_ivo_sel(6) <= ex4_n_flush_pri(PROG0n) or ex4_n_flush_pri(PROG0An) or ex4_n_flush_pri(PROG1n) or ex4_n_flush_pri(PROG2n) or ex4_n_flush_pri(PROG3n) or ex4_np1_flush_pri_instr(TRAP); + ex4_ivo_sel(7) <= ex4_n_flush_pri_unavail(FP); + ex4_ivo_sel(8) <= ex4_np1_flush_pri_instr(SC) and not ex4_sc_lev_q; + ex4_ivo_sel(9) <= ex4_n_flush_pri_unavail(AP); + ex4_ivo_sel(10) <= ex4_np1_flush_pri(DECnp1); + ex4_ivo_sel(11) <= ex4_np1_flush_pri(FITnp1); + ex4_ivo_sel(12) <= ex4_np1_flush_pri(WDOGnp1); + ex4_ivo_sel(13) <= ex4_n_flush_pri(DTLBn); + ex4_ivo_sel(14) <= ex4_n_flush_pri(ITLBn); + ex4_ivo_sel(15) <= (ex4_debug_int_en_q(t) and (ex4_n_flush_pri(DBG0n) or ex4_n_flush_pri(DBG1n) or ex4_np1_flush_pri(DBG3np1) or ex4_n_flush_pri_dacr_async(t) or ex4_n_flush_pri_icmp(t) or ex4_n_flush_pri_irpt(t))); + ex4_ivo_sel(16) <= ex4_n_flush_pri_unavail(VEC); + ex4_ivo_sel(17) <= ex4_np1_flush_pri(DBELLnp1); + ex4_ivo_sel(18) <= ex4_np1_flush_pri(CDBELLnp1); + ex4_ivo_sel(19) <= ex4_np1_flush_pri(GDBELLnp1); + ex4_ivo_sel(20) <= ex4_np1_flush_pri(GCDBELLnp1) or ex4_np1_flush_pri(GDBMCHKnp1); + ex4_ivo_sel(21) <= ex4_np1_flush_pri_instr(SC) and ex4_sc_lev_q; + ex4_ivo_sel(22) <= ex4_n_flush_pri(HPRIVn); + ex4_ivo_sel(23) <= ex4_n_flush_pri(ILRATn) or ex4_n_flush_pri(DLRATn); + ex4_ivo_sel(24) <= ex4_np1_flush_pri(UDECnp1); + ex4_ivo_sel(25) <= ex4_np1_flush_pri(PERFnp1); + + + ex5_dsigs_d(t) <= msr_gs_q(t) and spr_epcr_dsigs(t) and not ex4_esr_pri(VF); + ex5_isigs_d(t) <= msr_gs_q(t) and spr_epcr_isigs(t); + ex5_extgs_d(t) <= msr_gs_q(t) and spr_epcr_extgs(t); + ex5_dtlbgs_d(t) <= msr_gs_q(t) and spr_epcr_dtlbgs(t); + ex5_itlbgs_d(t) <= msr_gs_q(t) and spr_epcr_itlbgs(t); + + ex5_ivo_mask_guest(0) <= '0'; + ex5_ivo_mask_guest(1) <= '0'; + ex5_ivo_mask_guest(2) <= ex5_dsigs_q(t) and not ex5_tlb_inelig_q(t); + ex5_ivo_mask_guest(3) <= ex5_isigs_q(t) and not ex5_tlb_inelig_q(t); + ex5_ivo_mask_guest(4) <= ex5_extgs_q(t); + ex5_ivo_mask_guest(5) <= '0'; + ex5_ivo_mask_guest(6) <= '0'; + ex5_ivo_mask_guest(7) <= '0'; + ex5_ivo_mask_guest(8) <= msr_gs_q(t); + ex5_ivo_mask_guest(9) <= '0'; + ex5_ivo_mask_guest(10) <= '0'; + ex5_ivo_mask_guest(11) <= '0'; + ex5_ivo_mask_guest(12) <= '0'; + ex5_ivo_mask_guest(13) <= ex5_dtlbgs_q(t); + ex5_ivo_mask_guest(14) <= ex5_itlbgs_q(t); + ex5_ivo_mask_guest(15) <= '0'; + ex5_ivo_mask_guest(16) <= '0'; + ex5_ivo_mask_guest(17) <= '0'; + ex5_ivo_mask_guest(18) <= '0'; + ex5_ivo_mask_guest(19) <= '0'; + ex5_ivo_mask_guest(20) <= '0'; + ex5_ivo_mask_guest(21) <= '0'; + ex5_ivo_mask_guest(22) <= '0'; + ex5_ivo_mask_guest(23) <= '0'; + ex5_ivo_mask_guest(24) <= '0'; + ex5_ivo_mask_guest(25) <= '0'; + + ex5_ivo_guest_sel <= ex5_ivo_sel_q and ex5_ivo_mask_guest; + ex5_ivo_hypv_sel <= ex5_ivo_sel_q and not ex5_ivo_mask_guest; + + ex5_is_any_gint(t) <= or_reduce(ex5_ivo_guest_sel); + ex5_is_any_hint(t) <= or_reduce(ex5_ivo_hypv_sel); + + ex5_is_any_int(t) <= or_reduce(ex5_ivo_sel_q); + ex4_is_any_rfi(t) <= ex4_np1_flush_pri_instr(RFI); + + ex5_is_base_hint(t) <= or_reduce(ex5_ivo_hypv_sel(2 to 11)) or or_reduce(ex5_ivo_hypv_sel(13 to 14)) or or_reduce(ex5_ivo_hypv_sel(16 to 17)) or ex5_ivo_hypv_sel(19) or or_reduce(ex5_ivo_hypv_sel(21 to 25)); + ex5_is_base_gint(t) <= or_reduce(ex5_ivo_guest_sel(2 to 11)) or or_reduce(ex5_ivo_guest_sel(13 to 14)) or or_reduce(ex5_ivo_guest_sel(16 to 17)) or ex5_ivo_guest_sel(19) or or_reduce(ex5_ivo_guest_sel(21 to 25)); + ex4_is_base_int(t) <= or_reduce(ex4_ivo_sel(2 to 11)) or or_reduce(ex4_ivo_sel(13 to 14)) or or_reduce(ex4_ivo_sel(16 to 17)) or ex4_ivo_sel(19) or or_reduce(ex4_ivo_sel(21 to 25)); + + ex4_is_crit_int(t) <= ex4_ivo_sel(0) or ex4_ivo_sel(12) or ex4_ivo_sel(15) or ex4_ivo_sel(18) or ex4_ivo_sel(20); + ex4_is_mchk_int(t) <= ex4_ivo_sel(1); + + ex5_ivo <= gate(x"02",ex5_ivo_sel_q( 0)) or + gate(x"00",ex5_ivo_sel_q( 1)) or + gate(x"06",ex5_ivo_sel_q( 2)) or + gate(x"08",ex5_ivo_sel_q( 3)) or + gate(x"0A",ex5_ivo_sel_q( 4)) or + gate(x"0C",ex5_ivo_sel_q( 5)) or + gate(x"0E",ex5_ivo_sel_q( 6)) or + gate(x"10",ex5_ivo_sel_q( 7)) or + gate(x"12",ex5_ivo_sel_q( 8)) or + gate(x"14",ex5_ivo_sel_q( 9)) or + gate(x"16",ex5_ivo_sel_q(10)) or + gate(x"18",ex5_ivo_sel_q(11)) or + gate(x"1A",ex5_ivo_sel_q(12)) or + gate(x"1C",ex5_ivo_sel_q(13)) or + gate(x"1E",ex5_ivo_sel_q(14)) or + gate(x"04",ex5_ivo_sel_q(15)) or + gate(x"20",ex5_ivo_sel_q(16)) or + gate(x"28",ex5_ivo_sel_q(17)) or + gate(x"2A",ex5_ivo_sel_q(18)) or + gate(x"2C",ex5_ivo_sel_q(19)) or + gate(x"2E",ex5_ivo_sel_q(20)) or + gate(x"30",ex5_ivo_sel_q(21)) or + gate(x"32",ex5_ivo_sel_q(22)) or + gate(x"34",ex5_ivo_sel_q(23)) or + gate(x"80",ex5_ivo_sel_q(24)) or + gate(x"82",ex5_ivo_sel_q(25)); + + ex5_force_gsrr_d(t) <= ex4_np1_flush_pri(GDBELLnp1); + + + ex4_ena_prog_int(t) <= ex4_n_flush_pri_ena(FPENA) and not ex5_axu_trap_pie_q(t); + ex4_n_ieratre_par_mcint(t) <= ex4_n_flush_pri(IMCHKn) and ex4_n_ieratre_par_mchk_mcint_q(t); + ex4_n_deratre_par_mcint(t) <= ex4_n_flush_pri(DMCHKn) and ex4_n_deratre_par_mchk_mcint_q(t); + ex4_n_mmu_hpriv_int(t) <= ex4_n_flush_pri(HPRIVn) and ex4_n_mmu_hpriv_int_q(t); + ex4_n_tlbwemiss_dlrat_int(t) <= ex4_n_flush_pri(DLRATn) and ex4_n_tlbwemiss_dlrat_int_q(t); + ex4_n_tlbwe_pil_prog_int(t) <= ex4_n_flush_pri(PROG0An); + ex4_n_tlbmh_mchk_mcint(t) <= ex4_n_flush_pri(IMCHKn) and ex4_n_tlbmh_mchk_mcint_q(t) and not mmu_eratmiss_done_q(t); + ex4_n_tlbpar_mchk_mcint(t) <= ex4_n_flush_pri(IMCHKn) and spare_5_q(t) and not mmu_eratmiss_done_q(t); + + + + ex5_srr0_dec_d(t) <= ex4_ena_prog_int(t) or + ex4_n_ieratre_par_mcint(t) or ex4_n_deratre_par_mcint(t) or + ex4_n_mmu_hpriv_int(t) or + ex4_n_tlbwemiss_dlrat_int(t) or + ex4_n_tlbwe_pil_prog_int(t) or + ex4_n_tlbmh_mchk_mcint(t) or + ex4_n_tlbpar_mchk_mcint(t); + + + ex4_axu_trap_pie(t) <= not(spare_1_d(t)) or spare_1_q(t) or spare_1_q(4+t) or spare_1_q(8+t); + + ex5_axu_trap_pie_d(t) <= ex4_axu_trap_q(t) and (ex4_axu_trap_pie(t) or ex5_axu_trap_pie_q(t)); + + + ex5_dear_update_saved_d(t) <= derat_hold_present_q(t); + cpl_spr_ex5_dear_update_saved(t) <= ex5_dear_update_saved_q(t); + cpl_spr_ex5_dear_save(t) <= ex5_n_dmiss_flush_q(t); + + cpl_spr_ex5_dear_update(t) <= ex5_ivo_sel_q(2) or ex5_ivo_sel_q(5) or ex5_ivo_sel_q(13) or (ex5_ivo_sel_q(23) and ex5_n_ptemiss_dlrat_int_q(t)); + cpl_spr_ex5_esr_update(t) <= ex5_ivo_sel_q(2) or ex5_ivo_sel_q(5) or ex5_ivo_sel_q(13) or ex5_ivo_sel_q(6) or ex5_ivo_sel_q(3) or ex5_ivo_sel_q(16) or ex5_ivo_sel_q(23); + + ex4_dbsr_update(t) <= or_reduce(ex4_dbsr_cond and ex4_dbsr_en_cond) or exx_np1_icmp_dbg_event(t) or exx_np1_irpt_dbg_event(t) or ex4_n_flush_pri_dacr_async(t) or ex4_np1_ude_dbg_event_q(t); + ex4_dbsr_act(t) <= clkg_ctl_q or or_reduce(ex4_dbsr_cond) or exx_np1_icmp_dbg_event(t) or exx_np1_irpt_dbg_event(t) or ex4_n_flush_pri_dacr_async(t) or ex4_np1_ude_dbg_event_q(t); + + ex4_esr_act(t) <= clkg_ctl_q or ex4_n_flush_pri(PROG0n) or ex4_n_flush_pri(PROG1n) or ex4_n_flush_pri(PROG2n) or ex4_n_flush_pri(PROG3n) or ex4_n_flush_pri(PROG0An) or + ex4_n_flush_pri(ALIGNn) or ex4_n_flush_pri(UNAVAILn) or ex4_np1_ptr_prog_int_q(t) or + ex4_n_flush_pri(DSTORn) or ex4_n_flush_pri(DLRATn) or ex4_n_flush_pri(DTLBn) or + ex4_n_flush_pri(ISTORn) or ex4_n_flush_pri(ILRATn); + ex4_mcsr_act(t) <= clkg_ctl_q or ex4_n_flush_cond(IMCHKn) or ex4_n_flush_cond(DMCHKn) or ex4_np1_flush_cond(MCHKnp1); + + ex4_mcsr_d(0+14*t) <= ex3_n_dpovr_mchk_mcint(t); + ex4_mcsr_d(1+14*t) <= ex3_n_tlbsrej_mchk_mcint(t); + ex4_mcsr_d(2+14*t) <= ex3_n_tlblru_mchk_mcint(t); + ex4_mcsr_d(3+14*t) <= ex3_xuuc_val_q(t) and ex3_n_il2ecc_mchk_mcint_xuuc(t); + ex4_mcsr_d(4+14*t) <= ex3_n_dl2ecc_mchk_mcint(t); + ex4_mcsr_d(5+14*t) <= ex3_xu_val_q(t) and ex3_n_ddpe_mchk_mcint_xu(t); + ex4_mcsr_d(6+14*t) <= ex3_np1_ext_mchk_mcint(t); + ex4_mcsr_d(7+14*t) <= ex3_n_dcpe_mchk_mcint(t); + ex4_mcsr_d(8+14*t) <= ex3_xuuc_val_q(t) and ex3_n_iemh_mchk_mcint_xuuc(t); + ex4_mcsr_d(9+14*t) <= ex3_xu_val_q(t) and lsu_xu_ex3_derat_multihit_err(t); + ex4_mcsr_d(10+14*t) <= ex3_tlb_multihit_err_q(t); + ex4_mcsr_d(11+14*t) <=(ex3_xuuc_val_q(t) and ex3_n_iepe_mchk_mcint_xuuc(t)) or + ex3_n_ieratre_par_mchk_mcint(t); + ex4_mcsr_d(12+14*t) <=(ex3_xu_val_q(t) and lsu_xu_ex3_derat_par_err(t)) or + ( ex3_n_deratre_par_mchk_mcint(t)); + ex4_mcsr_d(13+14*t) <= ex3_tlb_par_err_q(t); + + + ex5_mcsr_d(0+15*t) <= ex4_n_flush_pri(DMCHKn) and ex4_mcsr_q(0+14*t); + ex5_mcsr_d(1+15*t) <= ex4_n_flush_pri(DMCHKn) and ex4_n_ddmh_mchk_mcint(t); + ex5_mcsr_d(2+15*t) <= ex4_n_flush_pri(IMCHKn) and ex4_mcsr_q(1+14*t); + ex5_mcsr_d(3+15*t) <= ex4_n_flush_pri(IMCHKn) and ex4_mcsr_q(2+14*t); + ex5_mcsr_d(4+15*t) <= ex4_n_flush_pri(IMCHKn) and ex4_mcsr_q(3+14*t); + ex5_mcsr_d(5+15*t) <= ex4_n_flush_pri(DMCHKn) and ex4_mcsr_q(4+14*t); + ex5_mcsr_d(6+15*t) <= ex4_n_flush_pri(DMCHKn) and ex4_mcsr_q(5+14*t); + ex5_mcsr_d(7+15*t) <= ex4_np1_flush_pri(MCHKnp1) and ex4_mcsr_q(6+14*t); + ex5_mcsr_d(8+15*t) <= ex4_n_flush_pri(DMCHKn) and ex4_mcsr_q(7+14*t); + ex5_mcsr_d(9+15*t) <= ex4_n_flush_pri(IMCHKn) and ex4_mcsr_q(8+14*t); + ex5_mcsr_d(10+15*t) <= ex4_n_flush_pri(DMCHKn) and ex4_mcsr_q(9+14*t); + ex5_mcsr_d(11+15*t) <= ex4_n_flush_pri(IMCHKn) and ex4_mcsr_q(10+14*t); + ex5_mcsr_d(12+15*t) <= ex4_n_flush_pri(IMCHKn) and(ex4_mcsr_q(11+14*t) or + ex4_n_ieratsx_par_mchk_mcint_q(t)); + ex5_mcsr_d(13+15*t) <= ex4_n_flush_pri(DMCHKn) and ex4_mcsr_q(12+14*t); + ex5_mcsr_d(14+15*t) <= ex4_n_flush_pri(IMCHKn) and ex4_mcsr_q(13+14*t); + + pc_err_mcsr(0+11*t) <= ex5_mcsr_act_q(t) and ex5_mcsr_q(0+15*t); + pc_err_mcsr(1+11*t) <= ex5_mcsr_act_q(t) and ex5_mcsr_q(2+15*t); + pc_err_mcsr(2+11*t) <= ex5_mcsr_act_q(t) and ex5_mcsr_q(3+15*t); + pc_err_mcsr(3+11*t) <= ex5_mcsr_act_q(t) and ex5_mcsr_q(7+15*t); + pc_err_mcsr(4+11*t) <= ex5_mcsr_act_q(t) and ex5_mcsr_q(9+15*t); + pc_err_mcsr(5+11*t) <= ex5_mcsr_act_q(t) and ex5_mcsr_q(10+15*t); + pc_err_mcsr(6+11*t) <= ex5_mcsr_act_q(t) and ex5_mcsr_q(11+15*t); + pc_err_mcsr(7+11*t) <= ex5_mcsr_act_q(t) and ex5_mcsr_q(12+15*t); + pc_err_mcsr(8+11*t) <= ex5_mcsr_act_q(t) and ex5_mcsr_q(13+15*t); + pc_err_mcsr(9+11*t) <= ex5_mcsr_act_q(t) and ex5_mcsr_q(14+15*t); + pc_err_mcsr(10+11*t) <= not ex5_mchk_int_en_q(t) and or_reduce(pc_err_mcsr(11*t to 11*t+9)); + pc_err_mcsr_summary_d(t) <= or_reduce(pc_err_mcsr_rpt(11*t to 11*t+9)); + + ex4_esr_mask(0) <= ex4_n_flush_pri(PROG0n) or ex4_n_flush_pri(PROG0An); + ex4_esr_mask(1) <= ex4_n_flush_pri(PROG1n); + ex4_esr_mask(2) <= ex4_np1_flush_pri_instr(TRAP); + ex4_esr_mask(3) <= ex4_n_flush_pri(ALIGNn) or ex4_n_flush_pri(DSTORn) or ex4_n_flush_pri(DTLBn) or ex4_n_flush_pri(DLRATn) or + ex4_n_flush_pri(PROG0n) or ex4_n_flush_pri(PROG1n) or ex4_n_flush_pri(PROG2n) or ex4_n_flush_pri(PROG3n); + ex4_esr_mask(4) <= ex4_n_flush_pri(ALIGNn) or ex4_n_flush_pri(DSTORn) or ex4_n_flush_pri(DTLBn) or ex4_n_flush_pri(DLRATn); + ex4_esr_mask(5) <= ex4_n_flush_pri(DSTORn); + ex4_esr_mask(6) <= ex4_n_flush_pri(DSTORn); + ex4_esr_mask(7) <= ex4_esr_mask(3); + ex4_esr_mask(8) <= ex4_n_flush_pri(PROG2n); + ex4_esr_mask(9) <= '0'; + ex4_esr_mask(10) <= ex4_n_flush_pri_ena(FPENA); + ex4_esr_mask(11) <= ex4_n_flush_pri(DSTORn); + ex4_esr_mask(12) <= ex4_n_flush_pri(DLRATn); + ex4_esr_mask(13) <= ex4_n_flush_pri(ISTORn) or ex4_n_flush_pri(DSTORn); + ex4_esr_mask(14) <= ex4_n_flush_pri(ISTORn) or ex4_n_flush_pri(DSTORn) or ex4_n_flush_pri(ILRATn) or ex4_n_flush_pri(DLRATn); + ex4_esr_mask(15) <= ex4_esr_mask(3) or ex4_n_flush_pri_unavail(VEC); + ex4_esr_mask(16) <= ex4_esr_mask(4); + + ex4_mmu_esr_val_d(t) <= ex3_tlb_inelig_q(t) or ex3_tlb_pt_fault_q(t) or ex3_tlb_miss_q(t); + + with ex4_n_flush_pri_ena select + ex4_axu_instr_type <= "001" when "01", + "100" when "10", + ex4_axu_instr_type_q when others; + + with ex4_mmu_esr_val_q(t) select + ex4_is_any_store(t) <= ex4_mmu_esr_st_q(t) when '1', + ex4_is_any_store_q(t) when others; + + + with ex4_mmu_esr_val_q(t) select + ex4_epid_instr(t) <= ex4_mmu_esr_epid_q(t) when '1', + ex4_epid_instr_q(t) when others; + + + ex4_esr_cond(DLK) <= ex4_n_flush_pri(DSTORn) and (ex4_n_dlk0_dstor_int_q(t) or ex4_n_dlk1_dstor_int_q(t)); + ex4_esr_cond(PT) <= ex4_mmu_esr_pt_q(t); + ex4_esr_cond(VF) <= ex4_n_flush_pri(DSTORn) and ex4_n_vf_dstor_int_q(t); + ex4_esr_cond(TLBI) <= ex4_tlb_inelig_q(t); + ex4_esr_cond(RW) <=(ex4_n_flush_pri(DSTORn) and ex4_n_rwaccess_dstor_int_q(t)) or + (ex4_n_flush_pri(ISTORn) and ex4_n_exaccess_istor_int_q(t)); + ex4_esr_cond(UCT) <= ex4_n_flush_pri(DSTORn) and ex4_n_uct_dstor_int_q(t); + + xu_cpl_esr_pri : entity work.xuq_cpl_pri(xuq_cpl_pri) + generic map (size => ex4_esr_cond'length) + port map( + cond => ex4_esr_cond, + pri => ex4_esr_pri); + + + ex5_esr_d(0+17*t) <= ex4_esr_mask(0); + ex5_esr_d(1+17*t) <= ex4_esr_mask(1); + ex5_esr_d(2+17*t) <= ex4_esr_mask(2) and ex4_np1_ptr_prog_int_q(t); + ex5_esr_d(3+17*t) <= ex4_esr_mask(3) and ex4_axu_instr_type(2); + ex5_esr_d(4+17*t) <= ex4_esr_mask(4) and ex4_is_any_store(t) and not ex4_esr_pri(UCT); + ex5_esr_d(5+17*t) <= ex4_esr_mask(5) and ex4_esr_pri(DLK) and ex4_n_dlk0_dstor_int_q(t); + ex5_esr_d(6+17*t) <= ex4_esr_mask(6) and ex4_esr_pri(DLK) and ex4_n_dlk1_dstor_int_q(t); + ex5_esr_d(7+17*t) <= ex4_esr_mask(7) and ex4_axu_instr_type(0); + ex5_esr_d(8+17*t) <= ex4_esr_mask(8); + ex5_esr_d(9+17*t) <= ex4_esr_mask(9); + ex5_esr_d(10+17*t) <= ex4_esr_mask(10) and ex5_axu_trap_pie_q(t); + ex5_esr_d(11+17*t) <= ex4_esr_mask(11) and ex4_esr_pri(UCT); + ex5_esr_d(12+17*t) <= ex4_esr_mask(12) and ex4_mmu_esr_data_q(t); + ex5_esr_d(13+17*t) <= ex4_esr_mask(13) and ex4_esr_pri(TLBI); + ex5_esr_d(14+17*t) <= ex4_esr_mask(14) and ex4_esr_pri(PT); + ex5_esr_d(15+17*t) <= ex4_esr_mask(15) and ex4_axu_instr_type(1); + ex5_esr_d(16+17*t) <= ex4_esr_mask(16) and ex4_epid_instr(t); + + ex5_dbsr_d(0+19*t) <= ex4_np1_ude_dbg_event_q(t); + ex5_dbsr_d(1+19*t) <= exx_np1_icmp_dbg_event(t); + ex5_dbsr_d(2+19*t) <= ex4_dbsr_en_cond(1) and ex4_n_brt_dbg_cint_q(t); + ex5_dbsr_d(3+19*t) <= exx_np1_irpt_dbg_event(t); + ex5_dbsr_d(4+19*t) <= ex4_dbsr_en_cond(1) and ex4_n_trap_dbg_cint_q(t); + ex5_dbsr_d(5+19*t) <= ex4_dbsr_en_cond(0) and ex4_iac1_cmpr_q(t) and ex4_anyuc_val_q(t); + ex5_dbsr_d(6+19*t) <= ex4_dbsr_en_cond(0) and ex4_iac2_cmpr_q(t) and ex4_anyuc_val_q(t); + ex5_dbsr_d(7+19*t) <= ex4_dbsr_en_cond(0) and ex4_iac3_cmpr_q(t) and ex4_anyuc_val_q(t); + ex5_dbsr_d(8+19*t) <= ex4_dbsr_en_cond(0) and ex4_iac4_cmpr_q(t) and ex4_anyuc_val_q(t); + ex5_dbsr_d(9+19*t) <=(ex4_dbsr_en_cond(1) and ex4_dacr_cmpr_q(1)(t) and ex4_anyuc_val_q(t)) or + ex4_dac1r_cmpr_async_q(t); + ex5_dbsr_d(10+19*t) <= ex4_dbsr_en_cond(1) and ex4_dacw_cmpr_q(1)(t) and ex4_anyuc_val_q(t); + ex5_dbsr_d(11+19*t) <=(ex4_dbsr_en_cond(1) and ex4_dacr_cmpr_q(2)(t) and ex4_anyuc_val_q(t)) or + ex4_dac2r_cmpr_async_q(t); + ex5_dbsr_d(12+19*t) <= ex4_dbsr_en_cond(1) and ex4_dacw_cmpr_q(2)(t) and ex4_anyuc_val_q(t); + ex5_dbsr_d(13+19*t) <= ex4_dbsr_en_cond(1) and ex4_n_ret_dbg_cint_q(t); + ex5_dbsr_d(14+19*t) <= ex4_dbsr_en_cond(1) and ex4_dacr_cmpr_q(3)(t) and ex4_anyuc_val_q(t); + ex5_dbsr_d(15+19*t) <= ex4_dbsr_en_cond(1) and ex4_dacw_cmpr_q(3)(t) and ex4_anyuc_val_q(t); + ex5_dbsr_d(16+19*t) <= ex4_dbsr_en_cond(1) and ex4_dacr_cmpr_q(4)(t) and ex4_anyuc_val_q(t); + ex5_dbsr_d(17+19*t) <= ex4_dbsr_en_cond(1) and ex4_dacw_cmpr_q(4)(t) and ex4_anyuc_val_q(t); + ex5_dbsr_d(18+19*t) <= ex4_dbsr_en_cond(0) and ex4_n_ivc_dbg_cint_q(t); + + ex5_dbsr_ide_d(t) <=(ex4_dac1r_cmpr_async_q(t) or ex4_dac2r_cmpr_async_q(t)) and not ex5_in_ucode_q(t); + cpl_spr_ex5_dbsr_ide(t) <= ex5_dbsr_ide_q(t); + + + ex4_ucode_restart(t) <= not ex4_uc_cia_val(t) or + (ex4_np1_flush_pri(Fnp1) and ex4_ucode_end(t)) or + ex4_n_flush_pri(F2Un) or + ex5_is_any_int(t); + with ex4_flush_act(t) select + ex5_ucode_restart_d(t) <= ex4_ucode_restart(t) when '1', + (ex5_ucode_restart_q(t) or ex5_is_any_int(t)) when others; + + ex5_flush_2ucode_d(t) <= ex4_n_flush_pri(F2Un); + + ex5_ram_interrupt(t) <= ram_ip_q(t) and ex5_is_any_int(t); + ex5_ram_issue_d(t) <= ram_ip_q(t) and ex5_late_flush_q(0)(t); + + with s2'((ex3_xu_val_q(t) or ex3_ucode_val_q(t)) & ex3_axu_val_q(t)) select + ex4_axu_instr_type_d <= dec_cpl_ex3_axu_instr_type when "10", + ex3_axu_instr_type_q(3*t to 3*t+2) when "01", + "000" when others; + + + + ex4_cia_sel <= fanout((not ex4_n_flush(t) and ex4_np1_ptr_prog_int_q(t)),eff_ifar); + ex4_nia_sel <= fanout(( ex4_n_flush(t) or not ex4_np1_ptr_prog_int_q(t)),eff_ifar); + + ex5_dbell_taken_d(t) <= ex4_np1_flush_pri(DBELLnp1); + ex5_cdbell_taken_d(t) <= ex4_np1_flush_pri(CDBELLnp1); + ex5_gdbell_taken_d(t) <= ex4_np1_flush_pri(GDBELLnp1); + ex5_gcdbell_taken_d(t) <= ex4_np1_flush_pri(GCDBELLnp1); + ex5_gmcdbell_taken_d(t) <= ex4_np1_flush_pri(GDBMCHKnp1); + + xu_iu_iu0_flush_ifar(eff_ifar*t to eff_ifar*(t+1)-1) <= flush_ifar; + ex4_cia_p1_out(eff_ifar*t to eff_ifar*(t+1)-1) <= ex4_cia_p1; + cpl_spr_ex5_nia(eff_ifar*t to eff_ifar*(t+1)-1) <= not ex5_nia_b_q(eff_ifar*t to eff_ifar*(t+1)-1); + spr_iar(eff_ifar*t to eff_ifar*(t+1)-1) <= ex4_cia when ram_mode_q(t)='1' else ex4_cia_p1; + + + ex3_n_fu_rfpe_det(t) <= not (ex3_flush_q(t) or ex3_flush(t)) and fu_xu_ex3_regfile_err_det(t); + + ex4_n_fu_rfpe_flush_d(t) <= ex3_n_fu_rfpe_det(t); + ex4_n_xu_rfpe_flush_d(t) <= (ex3_xuuc_val(t) or ex3_dep_val(t)) and gpr_cpl_ex3_regfile_err_det; + + ex4_n_fu_rfpe_flush(t) <= ex4_n_flush_pri(FPEn) and ex4_n_fu_rfpe_flush_q(t); + ex4_n_xu_rfpe_flush(t) <= ex4_n_flush_pri(FPEn) and ex4_n_xu_rfpe_flush_q(t); + + ex4_barrier_flush(t) <= ex4_n_flush_pri(FwBSn); + + cia_out_gen_32 : if eff_ifar /= 62 generate + ex4_cia_out(t) <= (0 to 62-eff_ifar=>'0') & ex4_cia; + end generate; + cia_out_gen_64 : if eff_ifar = 62 generate + ex4_cia_out(t) <= ex4_cia; + end generate; + + ex4_cia_b_latch : tri_rlmreg_p + generic map(width => ex4_cia_b_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, + vd => vdd, + gd => gnd, + act => ex3_cia_act(t), + forcee => bcfg_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => bcfg_sl_thold_0_b, + sg => sg_0, + scin => siv_bcfg(ex4_cia_b_offset_bcfg + ex4_cia_b_q'length*t to ex4_cia_b_offset_bcfg + ex4_cia_b_q'length*(t+1)-1), + scout => sov_bcfg(ex4_cia_b_offset_bcfg + ex4_cia_b_q'length*t to ex4_cia_b_offset_bcfg + ex4_cia_b_q'length*(t+1)-1), + din => ex4_cia_b_d, + dout => ex4_cia_b_q); + ex4_uc_cia_latch : tri_rlmreg_p + generic map (width => ex4_uc_cia_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => ex3_uc_cia_act(t), + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_uc_cia_offset + ex4_uc_cia_q'length*t to ex4_uc_cia_offset + ex4_uc_cia_q'length*(t+1)-1), + scout => sov(ex4_uc_cia_offset + ex4_uc_cia_q'length*t to ex4_uc_cia_offset + ex4_uc_cia_q'length*(t+1)-1), + din => ex4_uc_cia_d, + dout => ex4_uc_cia_q); + ex4_axu_instr_type_latch : tri_rlmreg_p + generic map (width => ex4_axu_instr_type_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex3_esr_bit_act(t), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_axu_instr_type_offset + ex4_axu_instr_type_q'length*t to ex4_axu_instr_type_offset + ex4_axu_instr_type_q'length*(t+1)-1), + scout => sov(ex4_axu_instr_type_offset + ex4_axu_instr_type_q'length*t to ex4_axu_instr_type_offset + ex4_axu_instr_type_q'length*(t+1)-1), + din => ex4_axu_instr_type_d, + dout => ex4_axu_instr_type_q); + ex4_is_any_store_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex3_esr_bit_act(t), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_is_any_store_offset+t), + scout => sov(ex4_is_any_store_offset+t), + din => dec_cpl_ex3_is_any_store, + dout => ex4_is_any_store_q(t)); + ex4_epid_instr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex3_esr_bit_act(t), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_epid_instr_offset+t), + scout => sov(ex4_epid_instr_offset+t), + din => ex3_epid_instr_q, + dout => ex4_epid_instr_q(t)); + ex5_mem_attr_latch : tri_rlmreg_p + generic map (width => ex5_mem_attr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => ex4_mem_attr_act(t), + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_mem_attr_offset + ex5_mem_attr_q'length*t to ex5_mem_attr_offset + ex5_mem_attr_q'length*(t+1)-1), + scout => sov(ex5_mem_attr_offset + ex5_mem_attr_q'length*t to ex5_mem_attr_offset + ex5_mem_attr_q'length*(t+1)-1), + din => ex4_mem_attr_q, + dout => ex5_mem_attr_q); + ex5_flush_2ucode_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_flush_act(t), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_flush_2ucode_offset+t), + scout => sov(ex5_flush_2ucode_offset+t), + din => ex5_flush_2ucode_d(t), + dout => ex5_flush_2ucode_q(t)); + ex5_ucode_restart_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_ucode_restart_offset+t), + scout => sov(ex5_ucode_restart_offset+t), + din => ex5_ucode_restart_d(t), + dout => ex5_ucode_restart_q(t)); + ex5_mem_attr_le_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_flush_act(t), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_mem_attr_le_offset+t), + scout => sov(ex5_mem_attr_le_offset+t), + din => ex5_mem_attr_le_d(t), + dout => ex5_mem_attr_le_q(t)); + ex5_ivo_sel_latch : tri_rlmreg_p + generic map (width => ex5_ivo_sel_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_flush_inf_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_ivo_sel_offset + ex5_ivo_sel_q'length*t to ex5_ivo_sel_offset + ex5_ivo_sel_q'length*(t+1)-1), + scout => sov(ex5_ivo_sel_offset + ex5_ivo_sel_q'length*t to ex5_ivo_sel_offset + ex5_ivo_sel_q'length*(t+1)-1), + din => ex4_ivo_sel, + dout => ex5_ivo_sel_q); + ex5_nia_b_latch : entity tri.tri_aoi22_nlats_wlcb(tri_aoi22_nlats_wlcb) + generic map (width => eff_ifar, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_nia_act(t), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_nia_b_offset + eff_ifar*t to ex5_nia_b_offset + eff_ifar*(t+1)-1), + scout => sov(ex5_nia_b_offset + eff_ifar*t to ex5_nia_b_offset + eff_ifar*(t+1)-1), + A1 => ex4_cia, + A2 => ex4_cia_sel, + B1 => ex4_nia, + B2 => ex4_nia_sel, + QB => ex5_nia_b_q(eff_ifar*t to eff_ifar*(t+1)-1)); + ex5_flush_pri_dbg_latch : tri_regk + generic map (width => ex5_flush_pri_dbg_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex4_flush_pri, + dout => ex5_flush_pri_dbg_q); + exx_instr_async_block_latch : tri_rlmreg_p + generic map (width => exx_instr_async_block_q(t)'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(exx_instr_async_block_offset+exx_instr_async_block_q(t)'length*t to exx_instr_async_block_offset + exx_instr_async_block_q(t)'length*(t+1)-1), + scout => sov(exx_instr_async_block_offset+exx_instr_async_block_q(t)'length*t to exx_instr_async_block_offset + exx_instr_async_block_q(t)'length*(t+1)-1), + din => exx_instr_async_block_d(t), + dout => exx_instr_async_block_q(t)); + ex5_esr_latch : tri_rlmreg_p + generic map (width => ex5_esr_q'length/threads, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_esr_act(t), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_esr_offset+(ex5_esr_q'length*t)/threads to ex5_esr_offset+((ex5_esr_q'length*(t+1))/threads)-1), + scout => sov(ex5_esr_offset+(ex5_esr_q'length*t)/threads to ex5_esr_offset+((ex5_esr_q'length*(t+1))/threads)-1), + din => ex5_esr_d((ex5_esr_q'length*t)/threads to ((ex5_esr_q'length*(t+1))/threads)-1), + dout => ex5_esr_q((ex5_esr_q'length*t)/threads to ((ex5_esr_q'length*(t+1))/threads)-1)); + ex5_dbsr_latch : tri_rlmreg_p + generic map (width => ex5_dbsr_q'length/threads, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_dbsr_act(t), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_dbsr_offset+(ex5_dbsr_q'length*t)/threads to ex5_dbsr_offset+((ex5_dbsr_q'length*(t+1))/threads)-1), + scout => sov(ex5_dbsr_offset+(ex5_dbsr_q'length*t)/threads to ex5_dbsr_offset+((ex5_dbsr_q'length*(t+1))/threads)-1), + din => ex5_dbsr_d((ex5_dbsr_q'length*t)/threads to ((ex5_dbsr_q'length*(t+1))/threads)-1), + dout => ex5_dbsr_q((ex5_dbsr_q'length*t)/threads to ((ex5_dbsr_q'length*(t+1))/threads)-1)); + ex5_mcsr_latch : tri_rlmreg_p + generic map (width => ex5_mcsr_q'length/threads, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_mcsr_act(t), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_mcsr_offset+(ex5_mcsr_q'length*t)/threads to ex5_mcsr_offset+((ex5_mcsr_q'length*(t+1))/threads)-1), + scout => sov(ex5_mcsr_offset+(ex5_mcsr_q'length*t)/threads to ex5_mcsr_offset+((ex5_mcsr_q'length*(t+1))/threads)-1), + din => ex5_mcsr_d((ex5_mcsr_q'length*t)/threads to ((ex5_mcsr_q'length*(t+1))/threads)-1), + dout => ex5_mcsr_q((ex5_mcsr_q'length*t)/threads to ((ex5_mcsr_q'length*(t+1))/threads)-1)); + dbg_flushcond_latch : tri_regk + generic map (width => dbg_flushcond_q(t)'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => dbg_flushcond_d(t), + dout => dbg_flushcond_q(t)); + ex5_np1_icmp_dbg_cint_latch : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_np1_icmp_dbg_cint_offset+t to ex5_np1_icmp_dbg_cint_offset+t), + scout => sov(ex5_np1_icmp_dbg_cint_offset+t to ex5_np1_icmp_dbg_cint_offset+t), + din(0) => ex5_np1_icmp_dbg_cint_d(t), + dout(0) => ex5_np1_icmp_dbg_cint_q(t)); + ex5_np1_icmp_dbg_event_latch : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_np1_icmp_dbg_event_offset+t to ex5_np1_icmp_dbg_event_offset+t), + scout => sov(ex5_np1_icmp_dbg_event_offset+t to ex5_np1_icmp_dbg_event_offset+t), + din(0) => ex5_np1_icmp_dbg_event_d(t), + dout(0) => ex5_np1_icmp_dbg_event_q(t)); + + ex5_perf_itlb_d(t) <= ex4_n_flush_pri(ITLBn); + ex5_perf_dtlb_d(t) <= ex4_n_flush_pri(DTLBn); + + xu_mm_ex5_perf_itlb(t) <= ex5_perf_itlb_q(t); + xu_mm_ex5_perf_dtlb(t) <= ex5_perf_dtlb_q(t); + + ex5_perf_event_d(00+14*t) <= ex4_instr_cpl(t); + ex5_perf_event_d(01+14*t) <= ex4_xuuc_val(t); + ex5_perf_event_d(02+14*t) <= ex4_np1_flush_pri(Fnp1) and ex4_ucode_end(t); + ex5_perf_event_d(03+14*t) <= ex2_br_flush(t) or ex4_n_flush(t) or ex4_np1_flush(t); + ex5_perf_event_d(04+14*t) <= ex4_xu_val(t) and ex4_perf_event_q(0); + ex5_perf_event_d(05+14*t) <= ex4_anyuc_val(t) and ex4_perf_event_q(1); + ex5_perf_event_d(06+14*t) <= ex4_anyuc_val(t) and ex4_perf_event_q(2); + ex5_perf_event_d(07+14*t) <= ex4_n_flush_pri(BTAn); + ex5_perf_event_d(08+14*t) <= ex4_anyuc_val(t) and ex4_perf_event_q(3); + ex5_perf_event_d(09+14*t) <= (ext_int_asserted(t) or ex5_perf_event_q(09+14*t)) and not ex5_ivo_sel_q(4); + ex5_perf_event_d(10+14*t) <= (crit_int_asserted(t) or ex5_perf_event_q(10+14*t)) and not ex5_ivo_sel_q(0); + ex5_perf_event_d(11+14*t) <= (perf_int_asserted(t) or ex5_perf_event_q(11+14*t)) and not ex5_ivo_sel_q(25); + ex5_perf_event_d(12+14*t) <= ex4_anyuc_val(t) and ex4_n_ivc_dbg_match_q(t); + ex5_perf_event_d(13+14*t) <= ex4_instr_cpl(t) and not or_reduce(spr_ccr0_we); + + cpl_perf_tx_events(00+19*t)<= ex5_perf_event_q(00+14*t); + cpl_perf_tx_events(01+19*t)<= ex5_perf_event_q(01+14*t); + cpl_perf_tx_events(02+19*t)<= ex5_perf_event_q(02+14*t); + cpl_perf_tx_events(03+19*t)<= ex5_perf_event_q(03+14*t); + cpl_perf_tx_events(04+19*t)<= ex5_perf_event_q(04+14*t); + cpl_perf_tx_events(05+19*t)<= ex5_perf_event_q(05+14*t); + cpl_perf_tx_events(06+19*t)<= ex5_perf_event_q(06+14*t); + cpl_perf_tx_events(07+19*t)<= ex5_perf_event_q(07+14*t); + cpl_perf_tx_events(08+19*t)<= ex5_perf_event_q(08+14*t); + cpl_perf_tx_events(09+19*t)<= ex5_perf_event_q(09+14*t); + cpl_perf_tx_events(10+19*t)<= ex5_perf_event_q(10+14*t); + cpl_perf_tx_events(11+19*t)<= ex5_perf_event_q(11+14*t); + cpl_perf_tx_events(12+19*t)<= ex5_perf_event_q(12+14*t); + cpl_perf_tx_events(13+19*t)<= ex5_perf_event_q(13+14*t); + cpl_perf_tx_events(14+19*t)<= any_ext_perf_int; + cpl_perf_tx_events(15+19*t)<= ex5_ivo_sel_q(4); + cpl_perf_tx_events(16+19*t)<= ex5_ivo_sel_q(0); + cpl_perf_tx_events(17+19*t)<= ex5_ivo_sel_q(25); + cpl_perf_tx_events(18+19*t)<= ex5_ivo_sel_q(17) or ex5_ivo_sel_q(18); + + any_ext_perf_ints(t) <= ex5_ivo_sel_q(4) or ex5_ivo_sel_q(0) or ex5_ivo_sel_q(25); + + ext_int_asserted(t) <= spr_cpl_async_int(0+3*t) and not spr_cpl_async_int_q(0+3*t); + crit_int_asserted(t) <= spr_cpl_async_int(1+3*t) and not spr_cpl_async_int_q(1+3*t); + perf_int_asserted(t) <= spr_cpl_async_int(2+3*t) and not spr_cpl_async_int_q(2+3*t); + + mark_unused(ex4_esr_pri(VF)); + mark_unused(ex4_esr_pri(RW)); + + ex5_axu_ucode_val_opc(t) <= ex5_ucode_end_dbg_q(t) and ex4_axu_instr_type_q(2) and not ex5_mem_attr_val_q(t); + + ex5_axu_val_dbg_opc(t) <= ex5_axu_val_dbg_q(t) or ex5_axu_ucode_val_opc(t); + ex5_xu_val_dbg_opc(t) <= ex5_xu_val_q(t) and not ex5_axu_ucode_val_opc(t); + + +end generate; + + + +any_ext_perf_int <= or_reduce(any_ext_perf_ints); + +xu_cpl_br : entity work.xuq_cpl_br(xuq_cpl_br) +generic map( + expand_type => expand_type, + threads => threads, + eff_ifar => eff_ifar, + uc_ifar => uc_ifar, + regsize => regsize) +port map( + nclk => nclk, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc, + mpw1_dc_b => mpw1_dc_b, + mpw2_dc_b => mpw2_dc_b, + func_sl_thold_0_b => func_sl_thold_0_b, + func_sl_force => func_sl_force, + sg_0 => sg_0, + scan_in => siv_3(0), + scan_out => sov_3(0), + rf1_act => exx_act(0), + ex1_act => exx_act(1), + rf1_tid => rf1_tid_q, + ex1_tid => ex1_xu_val_q, + ex1_xu_val => ex1_xu_val, + dec_cpl_rf1_ifar => dec_cpl_rf1_ifar, + ex1_xu_ifar => ex1_xu_ifar, + dec_cpl_rf1_pred_taken_cnt => dec_cpl_rf1_pred_taken_cnt, + dec_cpl_rf1_instr => dec_cpl_rf1_instr, + byp_cpl_ex1_cr_bit => byp_cpl_ex1_cr_bit, + spr_lr => spr_lr, + spr_ctr => spr_ctr, + ex2_br_flush => ex2_br_flush, + ex2_br_flush_ifar => ex2_br_flush_ifar, + ex1_branch => ex1_branch, + ex1_br_mispred => ex1_br_mispred, + ex1_br_taken => ex1_br_taken, + ex1_br_update => ex1_br_update, + ex1_is_bcctr => open, + ex1_is_bclr => ex1_is_bclr, + ex1_lr_update => ex1_lr_update, + ex1_ctr_dec_update => ex1_ctr_dec_update, + ex1_instr => ex1_instr, + spr_msr_cm => msr_cm_q, + br_debug => br_debug, + vdd => vdd, + gnd => gnd +); + +xu_cpl_spr : entity work.xuq_cpl_spr(xuq_cpl_spr) +generic map( + hvmode => hvmode, + a2mode => a2mode, + expand_type => expand_type, + threads => threads, + regsize => regsize, + eff_ifar => eff_ifar) +port map( + nclk => nclk, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc, + mpw1_dc_b => mpw1_dc_b, + mpw2_dc_b => mpw2_dc_b, + dcfg_sl_force => dcfg_sl_force, + dcfg_sl_thold_0_b => dcfg_sl_thold_0_b, + func_sl_force => func_sl_force, + func_sl_thold_0_b => func_sl_thold_0_b, + func_nsl_force => func_nsl_force, + func_nsl_thold_0_b => func_nsl_thold_0_b, + sg_0 => sg_0, + scan_in => siv_3(1), + scan_out => sov_3(1), + dcfg_scan_in => siv_dcfg(0), + dcfg_scan_out => sov_dcfg(0), + spr_bit_act => spr_bit_act_q, + exx_act => exx_act(1 to 4), + ex1_instr => ex1_instr(11 to 20), + ex2_tid => ex2_xu_val_q, + ex2_ifar => ex2_ifar, + ex1_is_mfspr => ex1_is_mfspr_q, + ex1_is_mtspr => ex1_is_mtspr_q, + ex4_lr_update => ex4_lr_update_q, + ex4_ctr_dec_update => ex4_ctr_dec_update_q, + ex5_val => ex5_xu_val_q, + ex5_spr_wd => ex5_rt_q, + ex5_cia_p1 => ex5_cia_p1, + ex2_mtiar => ex2_mtiar, + cpl_byp_ex3_spr_rt => cpl_byp_ex3_spr_rt, + ex3_iac1_cmpr => ex3_iac1_cmpr, + ex3_iac2_cmpr => ex3_iac2_cmpr, + ex3_iac3_cmpr => ex3_iac3_cmpr, + ex3_iac4_cmpr => ex3_iac4_cmpr, + spr_cpl_iac1_en => spr_cpl_iac1_en, + spr_cpl_iac2_en => spr_cpl_iac2_en, + spr_cpl_iac3_en => spr_cpl_iac3_en, + spr_cpl_iac4_en => spr_cpl_iac4_en, + spr_dbcr1_iac12m => spr_dbcr1_iac12m, + spr_dbcr1_iac34m => spr_dbcr1_iac34m, + spr_iar => spr_iar, + spr_msr_cm => msr_cm_q, + spr_givpr => spr_givpr, + spr_ivpr => spr_ivpr, + spr_ctr => spr_ctr, + spr_lr => spr_lr, + spr_xucr3_cm_hold_dly => spr_xucr3_cm_hold_dly, + spr_xucr3_stop_dly => spr_xucr3_stop_dly, + spr_xucr3_hold0_dly => spr_xucr3_hold0_dly, + spr_xucr3_hold1_dly => spr_xucr3_hold1_dly, + spr_xucr3_csi_dly => spr_xucr3_csi_dly, + spr_xucr3_int_dly => spr_xucr3_int_dly, + spr_xucr3_asyncblk_dly => spr_xucr3_asyncblk_dly, + spr_xucr3_flush_dly => spr_xucr3_flush_dly, + spr_xucr4_div_bar_dis => spr_xucr4_div_bar_dis, + spr_xucr4_lsu_bar_dis => spr_xucr4_lsu_bar_dis, + spr_xucr4_barr_dly => spr_xucr4_barr_dly, + spr_xucr4_div_barr_thres => spr_xucr4_div_barr_thres, + spr_xucr4_mddmh => spr_xucr4_mddmh, + spr_xucr4_mmu_mchk => spr_xucr4_mmu_mchk_int, + vdd => vdd, + gnd => gnd +); + +xu_cpl_sprg_ue_err_rpt : entity tri.tri_direct_err_rpt(tri_direct_err_rpt) +generic map(width => threads, expand_type => expand_type) +port map ( vd => vdd, gd => gnd, + err_in => ex5_n_flush_sprg_ue_flush_q, + err_out => xu_pc_err_sprg_ue); + +xu_cpl_err_debug_rpt : entity tri.tri_direct_err_rpt(tri_direct_err_rpt) +generic map (width => threads, expand_type => expand_type) +port map (vd => vdd, gd => gnd, + err_in => ex5_ext_dbg_err_q, + err_out => xu_pc_err_debug_event); + +xu_cpl_err_attn_rpt : entity tri.tri_direct_err_rpt(tri_direct_err_rpt) +generic map (width => threads, expand_type => expand_type) +port map (vd => vdd, gd => gnd, + err_in => ex5_is_attn_q, + err_out => xu_pc_err_attention_instr); + +xu_cpl_err_nia_rpt : entity tri.tri_direct_err_rpt(tri_direct_err_rpt) +generic map (width => threads, expand_type => expand_type) +port map (vd => vdd, gd => gnd, + err_in => ex5_err_nia_miscmpr_q, + err_out => xu_pc_err_nia_miscmpr); + + +ex6_mcsr_act_d <= or_reduce(ex5_mcsr_act_q); +ex5_mcsr_act <= ex6_mcsr_act_d or ex6_mcsr_act_q; + +bcfg_lcbnd: entity tri.tri_lcbnd +generic map (expand_type => expand_type ) +port map(act => ex5_mcsr_act, + vd => vdd, + gd => gnd, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + nclk => nclk, + forcee => bcfg_slp_sl_force, + sg => sg_0, + thold_b => bcfg_slp_sl_thold_0_b, + d1clk => mcsr_bcfg_slp_sl_d1clk, + d2clk => mcsr_bcfg_slp_sl_d2clk, + lclk => mcsr_bcfg_slp_sl_lclk); + +bcfg_lcbs: tri_lcbs +generic map (expand_type => expand_type ) +port map(vd => vdd, + gd => gnd, + delay_lclkr => delay_lclkr_dc, + nclk => nclk, + forcee => so_force, + thold_b => bcfg_so_thold_0_b, + dclk => bcfg_so_d2clk, + lclk => bcfg_so_lclk); + +xu_cpl_err_mcsr_rpt : entity tri.tri_err_rpt +generic map (width => pc_err_mcsr'length, mask_reset_value => (pc_err_mcsr'range=>'0'), inline => false, expand_type => expand_type) +port map (vd => vdd, gd => gnd, + err_d1clk => mcsr_bcfg_slp_sl_d1clk, + err_d2clk => mcsr_bcfg_slp_sl_d2clk, + err_lclk => mcsr_bcfg_slp_sl_lclk, + err_scan_in => siv_bcfg(mcsr_rpt_offset_bcfg to mcsr_rpt_offset_bcfg + pc_err_mcsr'length-1), + err_scan_out => sov_bcfg(mcsr_rpt_offset_bcfg to mcsr_rpt_offset_bcfg + pc_err_mcsr'length-1), + mode_dclk => bcfg_so_d2clk, + mode_lclk => bcfg_so_lclk, + mode_scan_in => siv_bcfg(mcsr_rpt2_offset_bcfg to mcsr_rpt2_offset_bcfg + pc_err_mcsr'length-1), + mode_scan_out => sov_bcfg(mcsr_rpt2_offset_bcfg to mcsr_rpt2_offset_bcfg + pc_err_mcsr'length-1), + err_in => pc_err_mcsr, + err_out => pc_err_mcsr_rpt); + + pc_err_mcsr_rpt_d <= or_reduce_t(pc_err_mcsr_rpt,threads); + + xu_pc_err_mcsr_summary <= pc_err_mcsr_summary_q; + xu_pc_err_ditc_overrun <= pc_err_mcsr_rpt_q(0); + xu_pc_err_local_snoop_reject <= pc_err_mcsr_rpt_q(1); + xu_pc_err_tlb_lru_parity <= pc_err_mcsr_rpt_q(2); + xu_pc_err_ext_mchk <= pc_err_mcsr_rpt_q(3); + xu_pc_err_ierat_multihit <= pc_err_mcsr_rpt_q(4); + xu_pc_err_derat_multihit <= pc_err_mcsr_rpt_q(5); + xu_pc_err_tlb_multihit <= pc_err_mcsr_rpt_q(6); + xu_pc_err_ierat_parity <= pc_err_mcsr_rpt_q(7); + xu_pc_err_derat_parity <= pc_err_mcsr_rpt_q(8); + xu_pc_err_tlb_parity <= pc_err_mcsr_rpt_q(9); + xu_pc_err_mchk_disabled <= pc_err_mcsr_rpt_q(10); + + +ex5_cm_fctr : entity work.xuq_cpl_fctr(xuq_cpl_fctr) +generic map (threads => threads, expand_type => expand_type, passthru => 1, clockgate => 0) +port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_cm_hold_cond_offset), + scout => sov(ex5_cm_hold_cond_offset), + delay => spr_xucr3_cm_hold_dly, + din => ex5_cm_hold_cond, + dout => exx_cm_hold); + +ex3_async_int_block_fctr : entity work.xuq_cpl_fctr(xuq_cpl_fctr) +generic map (threads => threads, expand_type => expand_type, passthru => 1) +port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_async_int_block_cond_offset), + scout => sov(ex3_async_int_block_cond_offset), + delay => spr_xucr3_asyncblk_dly, + din => ex3_async_int_block_cond, + dout => ex3_async_int_block_d); + +ex3_base_int_block_fctr : entity work.xuq_cpl_fctr(xuq_cpl_fctr) +generic map (threads => threads, expand_type => expand_type, passthru => 1, clockgate => 0) +port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_base_int_block_offset), + scout => sov(ex3_base_int_block_offset), + delay => spr_xucr3_int_dly, + din => ex3_base_int_block_cond, + dout => ex3_base_int_block); + +ex3_mchk_int_block_fctr : entity work.xuq_cpl_fctr(xuq_cpl_fctr) +generic map (threads => threads, expand_type => expand_type, passthru => 1, clockgate => 0) +port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_mchk_int_block_offset), + scout => sov(ex3_mchk_int_block_offset), + delay => spr_xucr3_int_dly, + din => ex3_mchk_int_block_cond, + dout => ex3_mchk_int_block); + +exx_thread_stop_mcflush_fctr : entity work.xuq_cpl_fctr(xuq_cpl_fctr) +generic map (threads => threads, expand_type => expand_type, passthru => 1) +port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(exx_thread_stop_mcflush_offset), + scout => sov(exx_thread_stop_mcflush_offset), + delay => spr_xucr3_stop_dly, + din => ex4_thread_stop_q, + dout => exx_thread_stop_mcflush); + +exx_csi_mcflush_fctr : entity work.xuq_cpl_fctr(xuq_cpl_fctr) +generic map (threads => threads, expand_type => expand_type, passthru => 1) +port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(exx_csi_mcflush_offset), + scout => sov(exx_csi_mcflush_offset), + delay => spr_xucr3_csi_dly, + din => ex5_csi, + dout => exx_csi_mcflush); + +exx_lateflush_mcflush_fctr : entity work.xuq_cpl_fctr(xuq_cpl_fctr) +generic map (threads => threads, expand_type => expand_type, passthru => 0) +port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(exx_lateflush_mcflush_offset), + scout => sov(exx_lateflush_mcflush_offset), + delay => spr_xucr3_flush_dly, + din => ex4_late_flush, + dout => exx_lateflush_mcflush); + +exx_hold0_mcflush_fctr : entity work.xuq_cpl_fctr(xuq_cpl_fctr) +generic map (threads => threads, expand_type => expand_type, passthru => 1) +port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(exx_hold0_mcflush_offset), + scout => sov(exx_hold0_mcflush_offset), + delay => spr_xucr3_hold0_dly, + din => hold_state_0, + dout => exx_hold0_mcflush); + +exx_hold1_mcflush_fctr : entity work.xuq_cpl_fctr(xuq_cpl_fctr) +generic map (threads => threads, expand_type => expand_type, passthru => 1) +port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(exx_hold1_mcflush_offset), + scout => sov(exx_hold1_mcflush_offset), + delay => spr_xucr3_hold1_dly, + din => hold_state_1, + dout => exx_hold1_mcflush); + +exx_barr_mcflush_fctr : entity work.xuq_cpl_fctr(xuq_cpl_fctr) +generic map (threads => threads, expand_type => expand_type, passthru => 0) +port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(exx_barr_mcflush_offset), + scout => sov(exx_barr_mcflush_offset), + delay => spr_xucr4_barr_dly, + din => ex4_barrier_flush, + dout => exx_barr_mcflush); + + +exx_multi_flush_d <= exx_thread_stop_mcflush or + exx_hold0_mcflush or + exx_hold1_mcflush or + exx_barr_mcflush or + exx_csi_mcflush; + +exx_multi_flush <= exx_lateflush_mcflush or + exx_multi_flush_q; + + +xu_iu_ex5_ppc_cpl <= ex5_instr_cpl_q; + +iu_flush <= ex2_br_flush or ex5_late_flush_q(0); +xu_iu_flush <= iu_flush; + +ex4_late_flush <= ex4_np1_flush or ex4_n_flush; + +ex5_late_flush_repwr : for r in 0 to ifar_repwr-1 generate + ex5_late_flush_d(r) <= ex4_np1_flush or ex4_n_flush or exx_multi_flush or hold_state_1; +end generate; + +exx_flush_inf_act <= clkg_ctl_q or or_reduce(any_flush or is2_flush_q); +ex4_flush_inf_act <= clkg_ctl_q or or_reduce(ex4_flush or ex5_flush_q); + +any_flush <= ex2_br_flush or ex4_np1_flush or ex4_n_flush or exx_multi_flush or hold_state_1; +is2_flush <= ex2_br_flush or ex4_np1_flush or ex4_n_flush or exx_multi_flush or hold_state_1; +rf0_flush <= ex2_br_flush or ex4_np1_flush or ex4_n_flush or exx_multi_flush or hold_state_1; +rf1_flush <= ex2_br_flush or ex4_np1_flush or ex4_n_flush or exx_multi_flush or hold_state_1; +ex1_flush <= ex2_br_flush or ex4_np1_flush or ex4_n_flush or exx_multi_flush or hold_state_1; +ex2_flush <= ex4_np1_flush or ex4_n_flush or exx_multi_flush or hold_state_1; +ex3_flush <= ex4_np1_flush or ex4_n_flush or exx_multi_flush or hold_state_1; +ex4_flush <= ex4_n_flush or exx_multi_flush_q or hold_state_1; + +xu_rf0_flush <= rf0_flush_q; +xu_rf1_flush <= rf1_flush_q; +xu_ex1_flush <= ex1_flush_q; +xu_ex2_flush <= ex2_flush_q; +xu_ex3_flush <= ex3_flush_q; +xu_ex4_flush <= ex4_flush_q; +xu_ex5_flush <= ex5_flush_q; + +xu_n_is2_flush <= xu_is2_n_flush_q; +xu_n_rf0_flush <= xu_rf0_n_flush_q; +xu_n_rf1_flush <= xu_rf1_n_flush_q; +xu_n_ex1_flush <= xu_ex1_n_flush_q; +xu_n_ex2_flush <= xu_ex2_n_flush_q; +xu_n_ex3_flush <= xu_ex3_n_flush_q; +xu_n_ex4_flush <= xu_ex4_n_flush_q; +xu_n_ex5_flush <= xu_ex5_n_flush_q; + +xu_s_rf1_flush <= xu_rf1_s_flush_q; +xu_s_ex1_flush <= xu_ex1_s_flush_q; +xu_s_ex2_flush <= xu_ex2_s_flush_q; +xu_s_ex3_flush <= xu_ex3_s_flush_q; +xu_s_ex4_flush <= xu_ex4_s_flush_q; +xu_s_ex5_flush <= xu_ex5_s_flush_q; + +xu_w_rf1_flush <= xu_rf1_w_flush_q; +xu_w_ex1_flush <= xu_ex1_w_flush_q; +xu_w_ex2_flush <= xu_ex2_w_flush_q; +xu_w_ex3_flush <= xu_ex3_w_flush_q; +xu_w_ex4_flush <= xu_ex4_w_flush_q; +xu_w_ex5_flush <= xu_ex5_w_flush_q; + +xu_mm_ex4_flush <= ex4_flush_q; +xu_mm_ex5_flush <= ex5_flush_q and not ex5_n_dmiss_flush_q; +xu_mm_ierat_flush <= is2_flush_q and not ierat_hold_present_q; +xu_mm_ierat_miss <= ex5_n_imiss_flush_q; + +rf1_xu_val <= dec_cpl_rf1_val and not rf1_flush_q; +ex1_xu_val <= ex1_xu_val_q and not ex1_flush_q and not ex1_flush; +ex2_xu_val <= ex2_xu_val_q and not ex2_flush; +ex3_xu_val <= ex3_xu_val_q and not ex3_flush; +ex4_xu_val <= ex4_xu_val_q and not ex4_flush; + +ex2_axu_val <= fu_xu_ex2_ifar_val and not ex2_flush_q and not ex2_flush; +ex3_axu_val <= ex3_axu_val_q and not ex3_flush; +ex4_axu_val <= ex4_axu_val_q and not ex4_flush; + +rf1_ucode_val <= dec_cpl_rf1_ucode_val and not rf1_flush_q and not rf1_flush; +ex1_ucode_val <= ex1_ucode_val_q and not ex1_flush; +ex2_ucode_val <= ex2_ucode_val_q and not ex2_flush; +ex3_ucode_val <= ex3_ucode_val_q and not ex3_flush; +ex4_ucode_val <= ex4_ucode_val_q and not ex4_flush; + +ex3_any_val <= (ex3_xu_val_q or ex3_axu_val_q) and not ex3_flush; +ex4_any_val <= (ex4_xu_val_q or ex4_axu_val_q) and not ex4_flush; + + +ex3_anyuc_val <= ex3_anyuc_val_q and not ex3_flush; +ex4_anyuc_val <= ex4_anyuc_val_q and not ex4_flush; + +ex3_anyuc_val_q<= (ex3_xu_val_q or ex3_axu_val_q or + ex3_ucode_val_q); + +ex4_anyuc_val_q<= (ex4_xu_val_q or ex4_axu_val_q or + ex4_ucode_val_q); + +ex3_xuuc_val_q <= (ex3_xu_val_q or ex3_ucode_val_q); +ex4_xuuc_val_q <= (ex4_xu_val_q or ex4_ucode_val_q); + +ex3_xuuc_val <= ex3_xuuc_val_q and not ex3_flush; +ex4_xuuc_val <= ex4_xuuc_val_q and not ex4_flush; + +ex3_dep_val <= dec_cpl_ex3_mc_dep_chk_val and not ex3_flush; + +ex3_n_mmu_mchk_flush_only <= not spr_ccr2_notlb and not spr_xucr4_mmu_mchk_int; + +ex3_is_any_ldst <= ex3_is_any_load_dac_q or ex3_is_any_store_dac_q or ex3_is_icswx_q; + + +ex2_msr_updater <= ex2_is_mtmsr_q or ex2_any_wrtee_q or + ex2_is_rfi_q or ex2_is_rfgi_q or + ex2_is_rfci_q or ex2_is_rfmci_q; + +ex5_cia_p1_d <= mux_t(ex4_cia_p1_out,ex4_xu_val_q); + +ex5_msr_cm <= or_reduce(ex5_xu_val_q and msr_cm_q); + +ex5_cia_p1(32 to 61) <= ex5_cia_p1_q(32 to 61); +ex5_cia_p1_gen : if IFAR'left < 32 generate + ex5_cia_p1(IFAR'left to 31) <= gate(ex5_cia_p1_q(IFAR'left to 31),ex5_msr_cm); +end generate; + +ex2_n_align_int_d <= ex1_is_any_ldstmw_q and or_reduce(alu_cpl_ex1_eff_addr(62 to 63)); + +ex1_taken_bclr <= ex1_is_bclr and ex1_br_taken; + +ex5_n_ext_dbg_stopc_flush_d <= or_reduce(ex4_dbsr_update and ext_dbg_stop_core_q); + +ex5_n_ext_dbg_stopt_flush_d <= ex4_dbsr_update and ext_dbg_stop_n_q; + +ex3_n_dcpe_flush_d <= (0 to threads-1=>lsu_xu_datc_perr_recovery); + +ex2_ifar <= not ex2_ifar_b_q; + +ex3_np1_mtiar_flush <= gate(ex3_xu_val,ex3_mtiar_q); +ex4_np1_mtiar_flush <= gate(ex4_xu_val,ex4_mtiar_q); + +ex2_any_wrtee_d <= ex1_is_wrtee_q or ex1_is_wrteei_q; + +ex7_is_tlbwe_d <= gate(ex6_xu_val_q,ex6_is_tlbwe_q); + +with s3'(pc_xu_ram_mode & pc_xu_ram_thread) select + ram_mode_d <= "1000" when "100", + "0100" when "101", + "0010" when "110", + "0001" when "111", + "0000" when others; + +with s3'(pc_xu_ram_execute & pc_xu_ram_thread) select + ram_execute_d <= "1000" when "100", + "0100" when "101", + "0010" when "110", + "0001" when "111", + "0000" when others; + +with s3'(pc_xu_ram_flush_thread & pc_xu_ram_thread) select + ram_flush_d <= "1000" when "100", + "0100" when "101", + "0010" when "110", + "0001" when "111", + "0000" when others; + + +ram_ip_d <= ram_mode_q and (ram_execute_q or + (ram_ip_q and not (ex4_ram_cpl or ex5_is_any_int))); + +ex5_ram_issue_gated <= ex5_ram_issue_q and not (ex7_ram_issue_q or ex8_ram_issue_q); + +ex5_ram_done_d <= or_reduce(ram_ip_q and ram_mode_q and gate(ex4_xu_val,not(ex4_xu_is_ucode_q))); +ex6_ram_issue_d <= ram_mode_q and (ram_execute_q or ex5_ram_issue_gated) and not ex5_ram_interrupt; +ex6_ram_interrupt_d <= or_reduce(ex5_ram_interrupt); +xu_iu_ram_issue <= ex6_ram_issue_q; +xu_pc_ram_interrupt <= ex6_ram_interrupt_q; +xu_pc_ram_done <= ex6_ram_done_q; +xu_pc_step_done <= ex6_step_done_q; + +with dec_cpl_ex2_error select + ex3_iu_error_d <= "1000000" when "001", + "0100000" when "010", + "0010000" when "011", + "0001000" when "100", + "0000100" when "101", + "0000010" when "110", + "0000001" when "111", + "0000000" when others; + +ex4_dac1r_cmpr_async_d <= fxu_cpl_ex3_dac1r_cmpr_async; +ex4_dac2r_cmpr_async_d <= fxu_cpl_ex3_dac2r_cmpr_async; + +ex4_dacr_cmpr_d(1) <= fxu_cpl_ex3_dac1r_cmpr; +ex4_dacr_cmpr_d(2) <= fxu_cpl_ex3_dac2r_cmpr; +ex4_dacr_cmpr_d(3) <= fxu_cpl_ex3_dac3r_cmpr; +ex4_dacr_cmpr_d(4) <= fxu_cpl_ex3_dac4r_cmpr; + +ex4_dacw_cmpr_d(1) <= fxu_cpl_ex3_dac1w_cmpr; +ex4_dacw_cmpr_d(2) <= fxu_cpl_ex3_dac2w_cmpr; +ex4_dacw_cmpr_d(3) <= fxu_cpl_ex3_dac3w_cmpr; +ex4_dacw_cmpr_d(4) <= fxu_cpl_ex3_dac4w_cmpr; + +ex5_is_attn_d <= gate(ex4_xu_val,ex4_is_attn_q); + +ex5_xu_ifar_d <= mux_t(ex4_ifar_q,ex4_xu_val_q); + +ex4_lsu_barr_flush <= ex4_barrier_flush and ex4_n_ldq_hit_flush_q; +ex4_div_barr_flush <= ex4_barrier_flush and ex4_n_barr_flush_q; + +ex5_lsu_set_barr_d <= gate(ex4_lsu_barr_flush,not(spr_xucr4_lsu_bar_dis)); +ex5_div_set_barr_d <= gate(ex4_div_barr_flush,not(spr_xucr4_div_bar_dis)); + +xu_lsu_ex5_set_barr <= ex5_lsu_set_barr_q; +cpl_fxa_ex5_set_barr <= ex5_div_set_barr_q; + +ex6_set_barr_d <= ex5_lsu_set_barr_q; + +cpl_iu_set_barr_tid <= ex6_set_barr_q; + +cpl_quiesced_d <= not( + ssprwr_ip_q or + ex5_in_ucode_q or + ex3_async_int_block_q or + hold_state_0 or + hold_state_1); + +cpl_spr_quiesce <= cpl_quiesced_q; + +quiesced_d <= and_reduce(spr_cpl_quiesce); + +hold_state_1 <=(others=> + (ici_hold_present or + fu_rfpe_hold_present_q or + xu_rfpe_hold_present_q)); + +dci_val_d <= or_reduce(ex4_xu_val) and ex4_is_dci_q; +ici_val_d <= or_reduce(ex4_xu_val) and ex4_is_ici_q; + +ici_hold_present_d(0 to 2) <= ici_val_d & ici_hold_present_q(0 to 1); +ici_hold_present <= or_reduce(ici_hold_present_q); + +ex4_n_fu_rfpe_set <= or_reduce(ex4_n_fu_rfpe_flush); +ex4_n_xu_rfpe_set <= or_reduce(ex4_n_xu_rfpe_flush); + +rfpe_quiesce_cond_b <= ex4_n_fu_rfpe_set or ex4_n_xu_rfpe_set or not quiesced_q; + +rfpe_quiesced <= not rfpe_quiesce_cond_b and not rfpe_quiesced_ctr_zero_b; + +rfpe_quiesce_fctr : entity work.xuq_cpl_fctr(xuq_cpl_fctr) +generic map (threads => 1, expand_type => expand_type, passthru => 0, clockgate => 0, delay_width => 8) +port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rfpe_quiesce_offset), + scout => sov(rfpe_quiesce_offset), + delay => "11000000", + din(0) => rfpe_quiesce_cond_b, + dout(0) => rfpe_quiesced_ctr_zero_b); + +fu_rfpe_hold_present_d <= (ex4_n_fu_rfpe_set or fu_rfpe_hold_present_q) and not (rfpe_quiesced and fu_rf_seq_end_q); +xu_rfpe_hold_present_d <= (ex4_n_xu_rfpe_set or xu_rfpe_hold_present_q) and not (rfpe_quiesced and xu_rf_seq_end_q); + +fu_rfpe_ack_d(0) <= fu_rfpe_hold_present_q and rfpe_quiesced; +fu_rfpe_ack_d(1) <= fu_rfpe_ack_d(0) and not fu_rfpe_ack_q(0); +xu_fu_regfile_seq_beg <= fu_rfpe_ack_q(1); + +xu_rfpe_ack_d(0) <= xu_rfpe_hold_present_q and rfpe_quiesced; +xu_rfpe_ack_d(1) <= xu_rfpe_ack_d(0) and not xu_rfpe_ack_q(0); +cpl_gpr_regfile_seq_beg <= xu_rfpe_ack_q(1); + +pc_dbg_stop <= pc_dbg_stop_q and not (ex5_in_ucode_q or ex4_ucode_val); +cpl_spr_stop <= pc_dbg_stop_2_q; +xu_lsu_dci <= dci_val_q; +xu_lsu_ici <= ici_val_q; +xu_pc_stop_dbg_event <= (0 to threads-1=>ex5_n_ext_dbg_stopc_flush_q) or ex5_n_ext_dbg_stopt_flush_q; +ac_tc_debug_trigger <= ex5_ext_dbg_ext_q; +xu_iu_ex5_ifar <= ex5_xu_ifar_q; +xu_iu_ex5_br_taken <= or_reduce(ex5_xu_val_q) and ex5_br_taken_q; +cpl_spr_ex5_instr_cpl <= ex5_any_val_q; +spr_xucr4_mmu_mchk <= spr_xucr4_mmu_mchk_int; + +xu_iu_flush_2ucode <= ex5_flush_2ucode_q; +xu_iu_ucode_restart <= ex5_ucode_restart_q; +xu_iu_flush_2ucode_type <= ex5_mem_attr_le_q; + +cpl_spr_ex5_act <= ex5_late_flush_q(0) or ex6_late_flush_q; +cpl_spr_ex5_int <= ex5_is_base_hint; +cpl_spr_ex5_gint <= ex5_is_base_gint; +cpl_spr_ex5_cint <= ex5_is_crit_int_q; +cpl_spr_ex5_mcint <= ex5_is_mchk_int_q; +cpl_spr_ex5_srr0_dec <= ex5_srr0_dec_q; +cpl_spr_ex5_force_gsrr <= ex5_force_gsrr_q; +cpl_spr_ex5_dbsr_update <= ex5_dbsr_update_q; +cpl_spr_ex5_esr <= ex5_esr_q; +cpl_spr_ex5_mcsr <= ex5_mcsr_q; +cpl_spr_ex5_dbsr <= ex5_dbsr_q; +cpl_spr_ex5_dbell_taken <= ex5_dbell_taken_q; +cpl_spr_ex5_cdbell_taken <= ex5_cdbell_taken_q; +cpl_spr_ex5_gdbell_taken <= ex5_gdbell_taken_q; +cpl_spr_ex5_gcdbell_taken <= ex5_gcdbell_taken_q; +cpl_spr_ex5_gmcdbell_taken <= ex5_gmcdbell_taken_q; + +cpl_dec_in_ucode <= ex5_in_ucode_q; + +cpl_msr_gs <= msr_gs_q; +cpl_msr_pr <= msr_pr_q; +cpl_msr_fp <= msr_fp_q; +cpl_msr_spv <= msr_spv_q; +cpl_ccr2_ap <= ccr2_ap_q; + +ex2_perf_event_d(0) <= ex1_branch; +ex2_perf_event_d(1) <= ex1_br_mispred; +ex2_perf_event_d(2) <= ex1_br_taken; + +ex4_perf_event_d(0) <= ex3_perf_event_q(0); +ex4_perf_event_d(1) <= ex3_perf_event_q(1); +ex4_perf_event_d(2) <= ex3_perf_event_q(2); +ex4_perf_event_d(3) <= or_reduce(ex3_n_multcoll_flush); + +ex4_xu_siar_val <= or_reduce(ex4_xuuc_val and not ex5_in_ucode_q); +ex4_axu_siar_val <= or_reduce(ex4_axu_val and not ex5_in_ucode_q); +ex4_siar_cpl <= (ex4_instr_cpl and not ex5_in_ucode_q) or ex4_ucode_val; + +ex3_xu_issued <= gate(ex3_xu_issued_q,not(or_reduce(ex3_iu_error_q))); + +ex4_siar_sel_act <= ex4_xu_siar_val and ex4_axu_siar_val and trace_bus_enable_q; +ex4_siar_sel_d(0 to 1) <= ex4_siar_sel_q(1) & ex4_siar_sel_q(0); + +with ex4_siar_sel_act select + ex4_siar_axu_sel <= ex4_siar_sel_q(1) when '1', + ex4_axu_siar_val when others; + +with (ex4_siar_axu_sel and not ex4_instr_trace_val_q) select + ex4_siar_tid <= ex4_axu_issued_q when '1', + ex4_xu_issued_q when others; + +with (ex4_siar_axu_sel and not ex4_instr_trace_val_q) select + ex4_siar_sel <= (ex4_axu_val_q and not ex5_in_ucode_q) when '1', + (ex4_xuuc_val_q and not ex5_in_ucode_q) when others; + + +ex4_siar_cm_mask(32 to 61) <= (others=>'1'); +xuq_cpl_siar_cm_mask_gen : if IFAR'left < 32 generate + ex4_siar_cm_mask(IFAR'left to 31) <= (others=>or_reduce(msr_cm_q and ex4_siar_sel)); +end generate; +ex5_siar_d <= ex4_siar_cm_mask and mux_t(ex4_ifar_q,ex4_siar_sel); +ex5_siar_gs_d <= or_reduce(msr_gs_q and ex4_siar_sel); +ex5_siar_pr_d <= or_reduce(msr_pr_q and ex4_siar_sel); +ex5_siar_cpl_d <= or_reduce(ex4_siar_cpl and ex4_siar_sel); +ex5_siar_issued_d <= or_reduce(ex4_siar_tid); +with s4'(ex4_siar_cpl and ex4_siar_sel) select + ex5_siar_tid_d <= "00" when "1000", + "01" when "0100", + "10" when "0010", + "11" when others; + +mark_unused(ex5_siar_issued_q); + + + +dbg_subgroup_gen : for t in 0 to threads-1 generate +dbg_valids_opc(t)(0 to 4) <= ex5_xu_val_dbg_opc(t) & ex5_axu_val_dbg_opc(t) & ex5_instr_cpl_dbg_q(t) & ex5_ucode_val_dbg_q(t) & ex5_ucode_end_dbg_q(t); +dbg_valids(t)(0 to 4) <= ex5_xu_val_q(t) & ex5_axu_val_dbg_q(t) & ex5_instr_cpl_dbg_q(t) & ex5_ucode_val_dbg_q(t) & ex5_ucode_end_dbg_q(t); +dbg_iuflush(t)(0 to 8) <= ex2_br_flush(t) & iu_flush(t) & ex5_is_any_hint(t) & ex5_is_any_gint(t) & ex5_ucode_restart_q(t) & ex5_flush_2ucode_q(t) & ex5_mem_attr_le_q(t) & hold_state_0(t) & hold_state_1(t); +dbg_msr(t)(0 to 4) <= msr_de_q(t) & msr_cm_q(t) & msr_gs_q(t) & msr_me_q(t) & msr_pr_q(t); +dbg_match(t)(0) <= ex5_dbsr_q(18+19*t); +dbg_match(t)(1) <= ex5_dbsr_q(5+19*t) or ex5_dbsr_q(6+19*t) or ex5_dbsr_q(7+19*t) or ex5_dbsr_q(8+19*t); +dbg_match(t)(2) <= ex5_dbsr_q(9+19*t) or ex5_dbsr_q(10+19*t) or ex5_dbsr_q(11+19*t) or ex5_dbsr_q(12+19*t) or + ex5_dbsr_q(14+19*t) or ex5_dbsr_q(15+19*t) or ex5_dbsr_q(16+19*t) or ex5_dbsr_q(17+19*t); +dbg_flushcond_d(t)(00) <= ex3_n_lsu_ddpe_flush(t); + +dbg_flushcond_d(t)(01) <= ex3_n_barr_flush(t); + +dbg_flushcond_d(t)(02) <= ex3_n_l2_ecc_err_flush_q(t); +dbg_flushcond_d(t)(03) <= ex3_n_dcpe_flush_q(t); +dbg_flushcond_d(t)(04) <= ex3_n_dlk0_dstor_int(t); +dbg_flushcond_d(t)(05) <= ex3_n_dlk1_dstor_int(t); +dbg_flushcond_d(t)(06) <= ex3_n_ieratre_par_mchk_mcint(t); +dbg_flushcond_d(t)(07) <= ex3_np1_sprg_ce_flush(t); +dbg_flushcond_d(t)(08) <= ex3_n_2ucode_flush(t); +dbg_flushcond_d(t)(09) <= ex3_n_lsualign_2ucode_flush(t); +dbg_flushcond_d(t)(10) <= ex3_n_fu_2ucode_flush(t); +dbg_flushcond_d(t)(11) <= ex3_n_mmuhold_flush(t); +dbg_flushcond_d(t)(12) <= ex3_n_lsu_dcpe_flush(t); +dbg_flushcond_d(t)(13) <= ex5_n_ext_dbg_stopc_flush_q; +dbg_flushcond_d(t)(14) <= ex5_n_ext_dbg_stopt_flush_q(t); +dbg_flushcond_d(t)(15) <= ex3_n_dci_flush(t); +dbg_flushcond_d(t)(16) <= ex3_n_ici_flush(t); +dbg_flushcond_d(t)(17) <= ex3_n_multcoll_flush(t); +dbg_flushcond_d(t)(18) <= ex3_n_ram_flush(t); +dbg_flushcond_d(t)(19) <= ex3_n_derat_dep_flush(t); +dbg_flushcond_d(t)(20) <= ex3_n_lsu_dep_flush(t); +dbg_flushcond_d(t)(21) <= ex3_n_dep_flush(t); +dbg_flushcond_d(t)(22) <= ex3_n_thrctl_stop_flush(t); +dbg_flushcond_d(t)(23) <= ex3_n_bclr_ta_miscmpr_flush(t); +dbg_flushcond_d(t)(24) <= ex3_n_memattr_miscmpr_flush(t); +dbg_flushcond_d(t)(25) <= ex3_np1_instr_flush(t); +dbg_flushcond_d(t)(26) <= ex3_n_ldq_hit_flush(t); +dbg_flushcond_d(t)(27) <= ex3_np1_fu_flush(t); +dbg_flushcond_d(t)(28) <= ex3_n_fu_dep_flush(t); +dbg_flushcond_d(t)(29) <= ex3_n_mmu_flush(t); +dbg_flushcond_d(t)(30) <= ex3_n_tlbmiss_dtlb_int(t); +dbg_flushcond_d(t)(31) <= ex3_n_deratmiss_dtlb_int(t); +dbg_flushcond_d(t)(32) <= ex3_n_tlbmiss_itlb_int(t); +dbg_flushcond_d(t)(33) <= ex3_n_ieratmiss_itlb_int(t); +dbg_flushcond_d(t)(34) <= ex3_n_apena_prog_int(t); +dbg_flushcond_d(t)(35) <= ex3_n_fpena_prog_int(t); +dbg_flushcond_d(t)(36) <= ex3_n_tlbpil_prog_int_xu(t) and ex3_xu_val(t); +dbg_flushcond_d(t)(37) <= ex3_n_sprpil_prog_int_xu(t) and ex3_xu_val(t); +dbg_flushcond_d(t)(38) <= ex3_n_iupil_prog_int_xuuc(t) and ex3_xuuc_val(t); +dbg_flushcond_d(t)(39) <= ex3_n_mmupil_prog_int_xu(t) and ex3_xu_val(t); +dbg_flushcond_d(t)(40) <= ex3_n_xupil_prog_int_xuuc(t) and ex3_xuuc_val(t); +dbg_flushcond_d(t)(41) <= ex3_n_puo_prog_int(t); +dbg_flushcond_d(t)(42) <= ex3_n_sprppr_prog_int_xuuc(t) and ex3_xuuc_val(t); +dbg_flushcond_d(t)(43) <= ex3_n_instrppr_prog_int_xuuc(t) and ex3_xuuc_val(t); +dbg_flushcond_d(t)(44) <= ex3_np1_ptr_prog_int(t); +dbg_flushcond_d(t)(45) <= ex3_n_any_unavail_int(t); +dbg_flushcond_d(t)(46) <= ex3_n_ldst_align_int(t); +dbg_flushcond_d(t)(47) <= ex3_n_ldstmw_align_int(t); +dbg_flushcond_d(t)(48) <= ex3_n_vf_dstor_int(t); +dbg_flushcond_d(t)(49) <= ex3_n_tlbi_dstor_int(t); +dbg_flushcond_d(t)(50) <= ex3_n_i1w1lock_dstor_int(t); +dbg_flushcond_d(t)(51) <= ex3_n_rwaccess_dstor_int(t); +dbg_flushcond_d(t)(52) <= ex3_n_uct_dstor_int(t); +dbg_flushcond_d(t)(53) <= ex3_n_pt_dstor_int(t); +dbg_flushcond_d(t)(54) <= ex3_n_tlbi_istor_int(t); +dbg_flushcond_d(t)(55) <= ex3_n_exaccess_istor_int(t); +dbg_flushcond_d(t)(56) <= ex3_n_pt_istor_int(t); +dbg_flushcond_d(t)(57) <= ex3_np1_instr_int(t); +dbg_flushcond_d(t)(58) <= ex3_n_ptemiss_dlrat_int(t); +dbg_flushcond_d(t)(59) <= ex3_n_tlbwemiss_dlrat_int(t); +dbg_flushcond_d(t)(60) <= ex3_n_spr_hpriv_int_xuuc(t) and ex3_xuuc_val(t); +dbg_flushcond_d(t)(61) <= ex3_n_instr_hpriv_int_xuuc(t) and ex3_xuuc_val(t); +dbg_flushcond_d(t)(62) <= ex3_n_mmu_hpriv_int(t); +dbg_flushcond_d(t)(63) <= ex3_n_ehpriv_hpriv_int(t); + + +dbg_hold(t)(0 to 5) <= mmu_hold_present_q(t) & derat_hold_present_q(t) & ierat_hold_present_q(t) & ici_hold_present & fu_rfpe_hold_present_q & xu_rfpe_hold_present_q; +dbg_async_block(t)(0 to 6) <= ssprwr_ip_q(t) & ex5_in_ucode_q(t) & ram_mode_q(t) & ex3_async_int_block_q(t) & ex4_icmp_async_block(t) & exx_hold0_mcflush(t) & exx_hold1_mcflush(t); +dbg_int_types(t)(0 to 4) <= ex4_is_mchk_int(t) & ex4_is_crit_int(t) & ex5_is_any_hint(t) & ex5_is_any_gint(t) & ex5_is_any_rfi_q(t); +dbg_misc(t)(0 to 3) <= ex5_tlb_inelig_q(t) & ex5_dear_update_saved_q(t) & exx_cm_hold(t) & ex3_esr_bit_act(t); + + +end generate; + +ex5_xu_ppc_cpl <= (ex5_xu_val_q and not (ex5_in_ucode_q or ex5_ucode_end_dbg_q)) or ex5_ucode_val_dbg_q; +ex5_axu_ppc_cpl <= (ex5_axu_val_dbg_q and not (ex5_in_ucode_q or ex5_ucode_end_dbg_q)); + +ex5_axu_trace_val <= instr_trace_mode_q and or_reduce(ex5_axu_ppc_cpl); +ex5_xu_trace_val <= ex5_instr_trace_val_q and or_reduce(ex5_xu_ppc_cpl); + +siar_cm(0) <= msr_cm_q(0) and not ex5_instr_trace_val_q; +siar_cm(1 to 2) <= msr_cm_q(1 to 2); +siar_cm(3) <=(msr_cm_q(3) and not ex5_instr_trace_val_q) or ex5_xu_trace_val; + +dbg_group0 <= dbg_valids(0) & ex5_in_ucode_q(0) & ex5_flush_pri_enc_dbg(0) & ex4_cia_out(0) & dbg_iuflush(0) & dbg_msr(0); +dbg_group1 <= dbg_valids(1) & ex5_in_ucode_q(1) & ex5_flush_pri_enc_dbg(1) & ex4_cia_out(1) & dbg_iuflush(1) & dbg_msr(1); +dbg_group2 <= dbg_valids(2) & ex5_in_ucode_q(2) & ex5_flush_pri_enc_dbg(2) & ex4_cia_out(2) & dbg_iuflush(2) & dbg_msr(2); +dbg_group3 <= dbg_valids(3) & ex5_in_ucode_q(3) & ex5_flush_pri_enc_dbg(3) & ex4_cia_out(3) & dbg_iuflush(3) & dbg_msr(3); +dbg_group4 <= dbg_valids_opc(0) & dbg_valids_opc(1) & dbg_valids_opc(2) & dbg_valids_opc(3) & ex5_in_ucode_q & ex1_instr(0 to 6) & ex1_instr(21 to 31) & ex1_instr(7 to 20) & ex4_cia_out(0)(54 to 61) & ex4_cia_out(1)(54 to 61) & ex4_cia_out(2)(54 to 61) & ex4_cia_out(3)(54 to 61); +dbg_group5 <= dbg_valids(0) & ex5_in_ucode_q(0) & ex5_flush_pri_enc_dbg(0) & dbg_flushcond_q(0)(0 to 63) & dbg_iuflush(0)(0 to 6) & dbg_msr(0); +dbg_group6 <= dbg_valids(1) & ex5_in_ucode_q(1) & ex5_flush_pri_enc_dbg(1) & dbg_flushcond_q(1)(0 to 63) & dbg_iuflush(1)(0 to 6) & dbg_msr(1); +dbg_group7 <= dbg_valids(2) & ex5_in_ucode_q(2) & ex5_flush_pri_enc_dbg(2) & dbg_flushcond_q(2)(0 to 63) & dbg_iuflush(2)(0 to 6) & dbg_msr(2); +dbg_group8 <= dbg_valids(3) & ex5_in_ucode_q(3) & ex5_flush_pri_enc_dbg(3) & dbg_flushcond_q(3)(0 to 63) & dbg_iuflush(3)(0 to 6) & dbg_msr(3); +dbg_group9 <= dbg_valids(0) & ex5_in_ucode_q(0) & ex5_flush_pri_enc_dbg(0) & dbg_iuflush(0) & ex1_instr(0 to 31) & + dbg_hold(0)(0 to 5) & dbg_async_block(0)(0 to 6) & dbg_int_types(0)(0 to 4) & dbg_misc(0)(0 to 3) & + br_debug & '0'; + +dbg_group10 <= dbg_valids(1) & ex5_in_ucode_q(1) & ex5_flush_pri_enc_dbg(1) & dbg_iuflush(1) & ex1_instr(0 to 31) & + dbg_hold(1)(0 to 5) & dbg_async_block(1)(0 to 6) & dbg_int_types(1)(0 to 4) & dbg_misc(1)(0 to 3) & + br_debug & '0'; + +dbg_group11 <= dbg_valids(2) & ex5_in_ucode_q(2) & ex5_flush_pri_enc_dbg(2) & dbg_iuflush(2) & ex1_instr(0 to 31) & + dbg_hold(2)(0 to 5) & dbg_async_block(2)(0 to 6) & dbg_int_types(2)(0 to 4) & dbg_misc(2)(0 to 3) & + br_debug & '0'; + +dbg_group12 <= dbg_valids(3) & ex5_in_ucode_q(3) & ex5_flush_pri_enc_dbg(3) & dbg_iuflush(3) & ex1_instr(0 to 31) & + dbg_hold(3)(0 to 5) & dbg_async_block(3)(0 to 6) & dbg_int_types(3)(0 to 4) & dbg_misc(3)(0 to 3) & + br_debug & '0'; + +dbg_group13 <= ex5_siar_q & ex5_siar_gs_q & ex5_siar_pr_q & siar_cm & ex5_siar_cpl_q & ex5_siar_cpl_q & ex5_siar_tid_q & ex4_xu_issued_q & ex4_axu_issued_q & ex5_instr_cpl_q & ex5_ucode_val_dbg_q; +dbg_group14 <= ex2_instr_dbg_q & x"0ABCDE" & '1' & ex2_instr_trace_type_q & (59 to 63=>'0') & '1' & ex2_instr_trace_type_q & '1' & (68 to 87=>'0'); +dbg_group15 <= ex1_instr(0 to 31) & dbg_valids(0) & ex5_in_ucode_q(0) & ex5_flush_pri_enc_dbg(0) & iu_flush(0) & ex5_ucode_restart_q(0) & + dbg_valids(1) & ex5_in_ucode_q(1) & ex5_flush_pri_enc_dbg(1) & iu_flush(1) & ex5_ucode_restart_q(1) & + dbg_valids(2) & ex5_in_ucode_q(2) & ex5_flush_pri_enc_dbg(2) & iu_flush(2) & ex5_ucode_restart_q(2) & + dbg_valids(3) & ex5_in_ucode_q(3) & ex5_flush_pri_enc_dbg(3) & iu_flush(3) & ex5_ucode_restart_q(3); +dbg_group16 <= (others=>'0'); +dbg_group17 <= (others=>'0'); +dbg_group18 <= (others=>'0'); +dbg_group19 <= (others=>'0'); +dbg_group20 <= (others=>'0'); +dbg_group21 <= (others=>'0'); +dbg_group22 <= (others=>'0'); +dbg_group23 <= (others=>'0'); +dbg_group24 <= (others=>'0'); +dbg_group25 <= (others=>'0'); +dbg_group26 <= (others=>'0'); +dbg_group27 <= (others=>'0'); +dbg_group28 <= fxa_cpl_debug(0 to 87); +dbg_group29 <= fxa_cpl_debug(88 to 175); +dbg_group30 <= fxa_cpl_debug(207 to 272) & fxa_cpl_debug(176 to 197); +dbg_group31 <= fxa_cpl_debug(198 to 272) & ex5_xu_ifar_q(49 to 61); +trg_group0 <= dbg_valids(0)(0 to 4) & dbg_iuflush(0)(0 to 3) & dbg_match(0)(0 to 2); +trg_group1 <= dbg_valids(1)(0 to 4) & dbg_iuflush(1)(0 to 3) & dbg_match(1)(0 to 2); +trg_group2 <= dbg_valids(2)(0 to 4) & dbg_iuflush(2)(0 to 3) & dbg_match(2)(0 to 2); +trg_group3 <= dbg_valids(3)(0 to 4) & dbg_iuflush(3)(0 to 3) & dbg_match(3)(0 to 2); + + + +with s2'(ex1_instr_trace_val_q & ex4_instr_trace_val_q) select + debug_mux_ctrls_int <= x"71E0" when "10", + x"69E0" when "01", + debug_mux_ctrls_q when others; + + +cpl_debug_data_in_int(0 to 55) <= cpl_debug_data_in(0 to 55); +cpl_debug_data_in_int(56) <= cpl_debug_data_in(56) or ex5_axu_trace_val; +cpl_debug_data_in_int(57 to 63) <= cpl_debug_data_in(57 to 63); +cpl_debug_data_in_int(64) <= cpl_debug_data_in(64) or ex5_axu_trace_val; +cpl_debug_data_in_int(65 to 66) <= cpl_debug_data_in(65 to 66); +cpl_debug_data_in_int(67) <= cpl_debug_data_in(67) or ex5_axu_trace_val; +cpl_debug_data_in_int(68 to 87) <= cpl_debug_data_in(68 to 87); + +xu_debug_mux : entity clib.c_debug_mux32(c_debug_mux32) +port map( + vd => vdd, + gd => gnd, + select_bits => debug_mux_ctrls_int_q, + trace_data_in => cpl_debug_data_in_int, + trigger_data_in => cpl_trigger_data_in, + dbg_group0 => dbg_group0, + dbg_group1 => dbg_group1, + dbg_group2 => dbg_group2, + dbg_group3 => dbg_group3, + dbg_group4 => dbg_group4, + dbg_group5 => dbg_group5, + dbg_group6 => dbg_group6, + dbg_group7 => dbg_group7, + dbg_group8 => dbg_group8, + dbg_group9 => dbg_group9, + dbg_group10 => dbg_group10, + dbg_group11 => dbg_group11, + dbg_group12 => dbg_group12, + dbg_group13 => dbg_group13, + dbg_group14 => dbg_group14, + dbg_group15 => dbg_group15, + dbg_group16 => dbg_group16, + dbg_group17 => dbg_group17, + dbg_group18 => dbg_group18, + dbg_group19 => dbg_group19, + dbg_group20 => dbg_group20, + dbg_group21 => dbg_group21, + dbg_group22 => dbg_group22, + dbg_group23 => dbg_group23, + dbg_group24 => dbg_group24, + dbg_group25 => dbg_group25, + dbg_group26 => dbg_group26, + dbg_group27 => dbg_group27, + dbg_group28 => dbg_group28, + dbg_group29 => dbg_group29, + dbg_group30 => dbg_group30, + dbg_group31 => dbg_group31, + trg_group0 => trg_group0, + trg_group1 => trg_group1, + trg_group2 => trg_group2, + trg_group3 => trg_group3, + trigger_data_out => trigger_data_out_d, + trace_data_out => debug_data_out_d); + +cpl_trigger_data_out <= trigger_data_out_q; +cpl_debug_data_out <= debug_data_out_q; + + +mark_unused(ex3_iu_error_q(3)); +mark_unused(spare_0_q); +mark_unused(spare_1_q); +mark_unused(spare_2_q); +mark_unused(spare_3_q); +mark_unused(spare_4_q); + + +is2_flush_latch : tri_rlmreg_p + generic map (width => is2_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(is2_flush_offset to is2_flush_offset + is2_flush_q'length-1), + scout => sov(is2_flush_offset to is2_flush_offset + is2_flush_q'length-1), + din => any_flush , + dout => is2_flush_q); +rf0_flush_latch : tri_rlmreg_p + generic map (width => rf0_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_flush_inf_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_flush_offset to rf0_flush_offset + rf0_flush_q'length-1), + scout => sov(rf0_flush_offset to rf0_flush_offset + rf0_flush_q'length-1), + din => is2_flush , + dout => rf0_flush_q); +rf1_flush_latch : tri_rlmreg_p + generic map (width => rf1_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_flush_inf_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf1_flush_offset to rf1_flush_offset + rf1_flush_q'length-1), + scout => sov(rf1_flush_offset to rf1_flush_offset + rf1_flush_q'length-1), + din => rf0_flush , + dout => rf1_flush_q); +rf1_tid_latch : tri_rlmreg_p + generic map (width => rf1_tid_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf1_tid_offset to rf1_tid_offset + rf1_tid_q'length-1), + scout => sov(rf1_tid_offset to rf1_tid_offset + rf1_tid_q'length-1), + din => dec_cpl_rf0_tid , + dout => rf1_tid_q); +ex1_axu_act_latch : tri_rlmreg_p + generic map (width => ex1_axu_act_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_axu_act_offset to ex1_axu_act_offset + ex1_axu_act_q'length-1), + scout => sov(ex1_axu_act_offset to ex1_axu_act_offset + ex1_axu_act_q'length-1), + din => fu_xu_rf1_act , + dout => ex1_axu_act_q); +ex1_byte_rev_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_byte_rev_offset), + scout => sov(ex1_byte_rev_offset), + din => rf1_byte_rev, + dout => ex1_byte_rev_q); +ex1_flush_latch : tri_rlmreg_p + generic map (width => ex1_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_flush_inf_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_flush_offset to ex1_flush_offset + ex1_flush_q'length-1), + scout => sov(ex1_flush_offset to ex1_flush_offset + ex1_flush_q'length-1), + din => rf1_flush , + dout => ex1_flush_q); +ex1_is_any_ldstmw_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_any_ldstmw_offset), + scout => sov(ex1_is_any_ldstmw_offset), + din => rf1_is_any_ldstmw, + dout => ex1_is_any_ldstmw_q); +ex1_is_attn_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_attn_offset), + scout => sov(ex1_is_attn_offset), + din => rf1_is_attn, + dout => ex1_is_attn_q); +ex1_is_dci_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_dci_offset), + scout => sov(ex1_is_dci_offset), + din => ex1_is_dci_d, + dout => ex1_is_dci_q); +ex1_is_dlock_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_dlock_offset), + scout => sov(ex1_is_dlock_offset), + din => rf1_is_dlock, + dout => ex1_is_dlock_q); +ex1_is_ehpriv_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_ehpriv_offset), + scout => sov(ex1_is_ehpriv_offset), + din => rf1_is_ehpriv, + dout => ex1_is_ehpriv_q); +ex1_is_erativax_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_erativax_offset), + scout => sov(ex1_is_erativax_offset), + din => rf1_is_erativax, + dout => ex1_is_erativax_q); +ex1_is_ici_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_ici_offset), + scout => sov(ex1_is_ici_offset), + din => ex1_is_ici_d, + dout => ex1_is_ici_q); +ex1_is_icswx_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_icswx_offset), + scout => sov(ex1_is_icswx_offset), + din => rf1_is_icswx, + dout => ex1_is_icswx_q); +ex1_is_ilock_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_ilock_offset), + scout => sov(ex1_is_ilock_offset), + din => rf1_is_ilock, + dout => ex1_is_ilock_q); +ex1_is_isync_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_isync_offset), + scout => sov(ex1_is_isync_offset), + din => rf1_is_isync, + dout => ex1_is_isync_q); +ex1_is_mfspr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_mfspr_offset), + scout => sov(ex1_is_mfspr_offset), + din => rf1_is_mfspr, + dout => ex1_is_mfspr_q); +ex1_is_mtmsr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_mtmsr_offset), + scout => sov(ex1_is_mtmsr_offset), + din => rf1_is_mtmsr, + dout => ex1_is_mtmsr_q); +ex1_is_mtspr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_mtspr_offset), + scout => sov(ex1_is_mtspr_offset), + din => rf1_is_mtspr, + dout => ex1_is_mtspr_q); +ex1_is_rfci_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_rfci_offset), + scout => sov(ex1_is_rfci_offset), + din => rf1_is_rfci, + dout => ex1_is_rfci_q); +ex1_is_rfgi_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_rfgi_offset), + scout => sov(ex1_is_rfgi_offset), + din => rf1_is_rfgi, + dout => ex1_is_rfgi_q); +ex1_is_rfi_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_rfi_offset), + scout => sov(ex1_is_rfi_offset), + din => rf1_is_rfi, + dout => ex1_is_rfi_q); +ex1_is_rfmci_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_rfmci_offset), + scout => sov(ex1_is_rfmci_offset), + din => rf1_is_rfmci, + dout => ex1_is_rfmci_q); +ex1_is_sc_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_sc_offset), + scout => sov(ex1_is_sc_offset), + din => rf1_is_sc, + dout => ex1_is_sc_q); +ex1_is_tlbivax_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_tlbivax_offset), + scout => sov(ex1_is_tlbivax_offset), + din => rf1_is_tlbivax, + dout => ex1_is_tlbivax_q); +ex1_is_wrtee_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_wrtee_offset), + scout => sov(ex1_is_wrtee_offset), + din => rf1_is_wrtee, + dout => ex1_is_wrtee_q); +ex1_is_wrteei_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_wrteei_offset), + scout => sov(ex1_is_wrteei_offset), + din => rf1_is_wrteei, + dout => ex1_is_wrteei_q); +ex1_is_mtxucr0_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_mtxucr0_offset), + scout => sov(ex1_is_mtxucr0_offset), + din => rf1_is_mtxucr0, + dout => ex1_is_mtxucr0_q); +ex1_is_tlbwe_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_tlbwe_offset), + scout => sov(ex1_is_tlbwe_offset), + din => rf1_is_tlbwe, + dout => ex1_is_tlbwe_q); +ex1_sc_lev_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_sc_lev_offset), + scout => sov(ex1_sc_lev_offset), + din => rf1_sc_lev, + dout => ex1_sc_lev_q); +ex1_ucode_val_latch : tri_rlmreg_p + generic map (width => ex1_ucode_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_ucode_val_offset to ex1_ucode_val_offset + ex1_ucode_val_q'length-1), + scout => sov(ex1_ucode_val_offset to ex1_ucode_val_offset + ex1_ucode_val_q'length-1), + din => rf1_ucode_val , + dout => ex1_ucode_val_q); +ex1_xu_val_latch : tri_rlmreg_p + generic map (width => ex1_xu_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_xu_val_offset to ex1_xu_val_offset + ex1_xu_val_q'length-1), + scout => sov(ex1_xu_val_offset to ex1_xu_val_offset + ex1_xu_val_q'length-1), + din => rf1_xu_val , + dout => ex1_xu_val_q); +ex2_axu_act_latch : tri_regk + generic map (width => ex2_axu_act_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex1_axu_act_q , + dout => ex2_axu_act_q); +ex2_any_wrtee_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_any_wrtee_d, + dout(0) => ex2_any_wrtee_q); +ex2_br_taken_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_br_taken , + dout(0) => ex2_br_taken_q); +ex2_br_update_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_br_update , + dout(0) => ex2_br_update_q); +ex2_byte_rev_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_byte_rev_q , + dout(0) => ex2_byte_rev_q); +ex2_ctr_dec_update_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_ctr_dec_update , + dout(0) => ex2_ctr_dec_update_q); +ex2_epid_instr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => dec_cpl_ex1_epid_instr , + dout(0) => ex2_epid_instr_q); +ex2_flush_latch : tri_rlmreg_p + generic map (width => ex2_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_flush_inf_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_flush_offset to ex2_flush_offset + ex2_flush_q'length-1), + scout => sov(ex2_flush_offset to ex2_flush_offset + ex2_flush_q'length-1), + din => ex1_flush , + dout => ex2_flush_q); +ex2_is_attn_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_attn_q , + dout(0) => ex2_is_attn_q); +ex2_is_dci_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_dci_q , + dout(0) => ex2_is_dci_q); +ex2_is_dlock_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_dlock_q , + dout(0) => ex2_is_dlock_q); +ex2_is_ehpriv_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_ehpriv_q , + dout(0) => ex2_is_ehpriv_q); +ex2_is_erativax_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_erativax_q , + dout(0) => ex2_is_erativax_q); +ex2_is_ici_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_ici_q , + dout(0) => ex2_is_ici_q); +ex2_is_icswx_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_icswx_q , + dout(0) => ex2_is_icswx_q); +ex2_is_ilock_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_ilock_q , + dout(0) => ex2_is_ilock_q); +ex2_is_isync_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_isync_q , + dout(0) => ex2_is_isync_q); +ex2_is_mtmsr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_mtmsr_q , + dout(0) => ex2_is_mtmsr_q); +ex2_is_rfci_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_rfci_q , + dout(0) => ex2_is_rfci_q); +ex2_is_rfgi_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_rfgi_q , + dout(0) => ex2_is_rfgi_q); +ex2_is_rfi_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_rfi_q , + dout(0) => ex2_is_rfi_q); +ex2_is_rfmci_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_rfmci_q , + dout(0) => ex2_is_rfmci_q); +ex2_is_sc_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_sc_q , + dout(0) => ex2_is_sc_q); +ex2_is_slowspr_wr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => dec_cpl_ex1_is_slowspr_wr , + dout(0) => ex2_is_slowspr_wr_q); +ex2_is_tlbivax_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_tlbivax_q , + dout(0) => ex2_is_tlbivax_q); +ex2_is_tlbwe_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_tlbwe_q , + dout(0) => ex2_is_tlbwe_q); +ex2_lr_update_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_lr_update , + dout(0) => ex2_lr_update_q); +ex2_n_align_int_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_n_align_int_d, + dout(0) => ex2_n_align_int_q); +ex2_sc_lev_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_sc_lev_q , + dout(0) => ex2_sc_lev_q); +ex2_taken_bclr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_taken_bclr , + dout(0) => ex2_taken_bclr_q); +ex2_ucode_val_latch : tri_rlmreg_p + generic map (width => ex2_ucode_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_ucode_val_offset to ex2_ucode_val_offset + ex2_ucode_val_q'length-1), + scout => sov(ex2_ucode_val_offset to ex2_ucode_val_offset + ex2_ucode_val_q'length-1), + din => ex1_ucode_val , + dout => ex2_ucode_val_q); +ex2_xu_val_latch : tri_rlmreg_p + generic map (width => ex2_xu_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_xu_val_offset to ex2_xu_val_offset + ex2_xu_val_q'length-1), + scout => sov(ex2_xu_val_offset to ex2_xu_val_offset + ex2_xu_val_q'length-1), + din => ex1_xu_val , + dout => ex2_xu_val_q); +ex2_is_mtxucr0_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_mtxucr0_q , + dout(0) => ex2_is_mtxucr0_q); +ex3_async_int_block_latch : tri_rlmreg_p + generic map (width => ex3_async_int_block_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_async_int_block_offset to ex3_async_int_block_offset + ex3_async_int_block_q'length-1), + scout => sov(ex3_async_int_block_offset to ex3_async_int_block_offset + ex3_async_int_block_q'length-1), + din => ex3_async_int_block_d, + dout => ex3_async_int_block_q); +ex3_axu_instr_match_latch : tri_rlmreg_p + generic map (width => ex3_axu_instr_match_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_axu_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_axu_instr_match_offset to ex3_axu_instr_match_offset + ex3_axu_instr_match_q'length-1), + scout => sov(ex3_axu_instr_match_offset to ex3_axu_instr_match_offset + ex3_axu_instr_match_q'length-1), + din => fu_xu_ex2_instr_match , + dout => ex3_axu_instr_match_q); +ex3_axu_instr_type_latch : tri_rlmreg_p + generic map (width => ex3_axu_instr_type_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_axu_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_axu_instr_type_offset to ex3_axu_instr_type_offset + ex3_axu_instr_type_q'length-1), + scout => sov(ex3_axu_instr_type_offset to ex3_axu_instr_type_offset + ex3_axu_instr_type_q'length-1), + din => fu_xu_ex2_instr_type , + dout => ex3_axu_instr_type_q); +ex3_axu_is_ucode_latch : tri_rlmreg_p + generic map (width => ex3_axu_is_ucode_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_axu_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_axu_is_ucode_offset to ex3_axu_is_ucode_offset + ex3_axu_is_ucode_q'length-1), + scout => sov(ex3_axu_is_ucode_offset to ex3_axu_is_ucode_offset + ex3_axu_is_ucode_q'length-1), + din => fu_xu_ex2_is_ucode , + dout => ex3_axu_is_ucode_q); +ex3_axu_val_latch : tri_rlmreg_p + generic map (width => ex3_axu_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_axu_val_offset to ex3_axu_val_offset + ex3_axu_val_q'length-1), + scout => sov(ex3_axu_val_offset to ex3_axu_val_offset + ex3_axu_val_q'length-1), + din => ex2_axu_val , + dout => ex3_axu_val_q); +ex3_br_flush_ifar_latch : tri_rlmreg_p + generic map (width => ex3_br_flush_ifar_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_br_flush_ifar_offset to ex3_br_flush_ifar_offset + ex3_br_flush_ifar_q'length-1), + scout => sov(ex3_br_flush_ifar_offset to ex3_br_flush_ifar_offset + ex3_br_flush_ifar_q'length-1), + din => ex2_br_flush_ifar , + dout => ex3_br_flush_ifar_q); +ex3_br_taken_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_br_taken_offset), + scout => sov(ex3_br_taken_offset), + din => ex2_br_taken_q , + dout => ex3_br_taken_q); +ex3_br_update_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_br_update_offset), + scout => sov(ex3_br_update_offset), + din => ex2_br_update_q , + dout => ex3_br_update_q); +ex3_byte_rev_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_byte_rev_offset), + scout => sov(ex3_byte_rev_offset), + din => ex2_byte_rev_q , + dout => ex3_byte_rev_q); +ex3_ctr_dec_update_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_ctr_dec_update_offset), + scout => sov(ex3_ctr_dec_update_offset), + din => ex2_ctr_dec_update_q , + dout => ex3_ctr_dec_update_q); +ex3_div_coll_latch : tri_rlmreg_p + generic map (width => ex3_div_coll_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_div_coll_offset to ex3_div_coll_offset + ex3_div_coll_q'length-1), + scout => sov(ex3_div_coll_offset to ex3_div_coll_offset + ex3_div_coll_q'length-1), + din => ex3_div_coll_d, + dout => ex3_div_coll_q); +ex3_epid_instr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_epid_instr_offset), + scout => sov(ex3_epid_instr_offset), + din => ex2_epid_instr_q , + dout => ex3_epid_instr_q); +ex3_flush_latch : tri_rlmreg_p + generic map (width => ex3_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_flush_inf_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_flush_offset to ex3_flush_offset + ex3_flush_q'length-1), + scout => sov(ex3_flush_offset to ex3_flush_offset + ex3_flush_q'length-1), + din => ex2_flush , + dout => ex3_flush_q); +ex3_ierat_flush_req_latch : tri_rlmreg_p + generic map (width => ex3_ierat_flush_req_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_ierat_flush_req_offset to ex3_ierat_flush_req_offset + ex3_ierat_flush_req_q'length-1), + scout => sov(ex3_ierat_flush_req_offset to ex3_ierat_flush_req_offset + ex3_ierat_flush_req_q'length-1), + din => iu_xu_ierat_ex2_flush_req , + dout => ex3_ierat_flush_req_q); +ex3_illegal_op_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_illegal_op_offset), + scout => sov(ex3_illegal_op_offset), + din => dec_cpl_ex2_illegal_op , + dout => ex3_illegal_op_q); +ex3_is_any_load_dac_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_any_load_dac_offset), + scout => sov(ex3_is_any_load_dac_offset), + din => dec_cpl_ex2_is_any_load_dac, + dout => ex3_is_any_load_dac_q); +ex3_is_any_store_dac_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_any_store_dac_offset), + scout => sov(ex3_is_any_store_dac_offset), + din => dec_cpl_ex2_is_any_store_dac, + dout => ex3_is_any_store_dac_q); +ex3_is_attn_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_attn_offset), + scout => sov(ex3_is_attn_offset), + din => ex2_is_attn_q , + dout => ex3_is_attn_q); +ex3_is_dci_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_dci_offset), + scout => sov(ex3_is_dci_offset), + din => ex2_is_dci_q , + dout => ex3_is_dci_q); +ex3_is_dlock_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_dlock_offset), + scout => sov(ex3_is_dlock_offset), + din => ex2_is_dlock_q , + dout => ex3_is_dlock_q); +ex3_is_ehpriv_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_ehpriv_offset), + scout => sov(ex3_is_ehpriv_offset), + din => ex2_is_ehpriv_q , + dout => ex3_is_ehpriv_q); +ex3_is_ici_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_ici_offset), + scout => sov(ex3_is_ici_offset), + din => ex2_is_ici_q , + dout => ex3_is_ici_q); +ex3_is_icswx_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_icswx_offset), + scout => sov(ex3_is_icswx_offset), + din => ex2_is_icswx_q , + dout => ex3_is_icswx_q); +ex3_is_ilock_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_ilock_offset), + scout => sov(ex3_is_ilock_offset), + din => ex2_is_ilock_q , + dout => ex3_is_ilock_q); +ex3_is_isync_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_isync_offset), + scout => sov(ex3_is_isync_offset), + din => ex2_is_isync_q , + dout => ex3_is_isync_q); +ex3_is_mtmsr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_mtmsr_offset), + scout => sov(ex3_is_mtmsr_offset), + din => ex2_is_mtmsr_q , + dout => ex3_is_mtmsr_q); +ex3_is_rfci_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_rfci_offset), + scout => sov(ex3_is_rfci_offset), + din => ex2_is_rfci_q , + dout => ex3_is_rfci_q); +ex3_is_rfgi_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_rfgi_offset), + scout => sov(ex3_is_rfgi_offset), + din => ex2_is_rfgi_q , + dout => ex3_is_rfgi_q); +ex3_is_rfi_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_rfi_offset), + scout => sov(ex3_is_rfi_offset), + din => ex2_is_rfi_q , + dout => ex3_is_rfi_q); +ex3_is_rfmci_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_rfmci_offset), + scout => sov(ex3_is_rfmci_offset), + din => ex2_is_rfmci_q , + dout => ex3_is_rfmci_q); +ex3_is_sc_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_sc_offset), + scout => sov(ex3_is_sc_offset), + din => ex2_is_sc_q , + dout => ex3_is_sc_q); +ex3_is_tlbwe_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_tlbwe_offset), + scout => sov(ex3_is_tlbwe_offset), + din => ex2_is_tlbwe_q , + dout => ex3_is_tlbwe_q); +ex3_is_slowspr_wr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_slowspr_wr_offset), + scout => sov(ex3_is_slowspr_wr_offset), + din => ex2_is_slowspr_wr_q , + dout => ex3_is_slowspr_wr_q); +ex3_iu_error_latch : tri_rlmreg_p + generic map (width => ex3_iu_error_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_iu_error_offset to ex3_iu_error_offset + ex3_iu_error_q'length-1), + scout => sov(ex3_iu_error_offset to ex3_iu_error_offset + ex3_iu_error_q'length-1), + din => ex3_iu_error_d, + dout => ex3_iu_error_q); +ex3_lr_update_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_lr_update_offset), + scout => sov(ex3_lr_update_offset), + din => ex2_lr_update_q , + dout => ex3_lr_update_q); +ex3_lrat_miss_latch : tri_rlmreg_p + generic map (width => ex3_lrat_miss_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_lrat_miss_offset to ex3_lrat_miss_offset + ex3_lrat_miss_q'length-1), + scout => sov(ex3_lrat_miss_offset to ex3_lrat_miss_offset + ex3_lrat_miss_q'length-1), + din => mm_xu_lrat_miss , + dout => ex3_lrat_miss_q); +ex3_mmu_esr_data_latch : tri_rlmreg_p + generic map (width => ex3_mmu_esr_data_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_mmu_esr_data_offset to ex3_mmu_esr_data_offset + ex3_mmu_esr_data_q'length-1), + scout => sov(ex3_mmu_esr_data_offset to ex3_mmu_esr_data_offset + ex3_mmu_esr_data_q'length-1), + din => mm_xu_esr_data , + dout => ex3_mmu_esr_data_q); +ex3_mmu_esr_epid_latch : tri_rlmreg_p + generic map (width => ex3_mmu_esr_epid_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_mmu_esr_epid_offset to ex3_mmu_esr_epid_offset + ex3_mmu_esr_epid_q'length-1), + scout => sov(ex3_mmu_esr_epid_offset to ex3_mmu_esr_epid_offset + ex3_mmu_esr_epid_q'length-1), + din => mm_xu_esr_epid , + dout => ex3_mmu_esr_epid_q); +ex3_mmu_esr_pt_latch : tri_rlmreg_p + generic map (width => ex3_mmu_esr_pt_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_mmu_esr_pt_offset to ex3_mmu_esr_pt_offset + ex3_mmu_esr_pt_q'length-1), + scout => sov(ex3_mmu_esr_pt_offset to ex3_mmu_esr_pt_offset + ex3_mmu_esr_pt_q'length-1), + din => mm_xu_esr_pt , + dout => ex3_mmu_esr_pt_q); +ex3_mmu_esr_st_latch : tri_rlmreg_p + generic map (width => ex3_mmu_esr_st_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_mmu_esr_st_offset to ex3_mmu_esr_st_offset + ex3_mmu_esr_st_q'length-1), + scout => sov(ex3_mmu_esr_st_offset to ex3_mmu_esr_st_offset + ex3_mmu_esr_st_q'length-1), + din => mm_xu_esr_st , + dout => ex3_mmu_esr_st_q); +ex3_mmu_hv_priv_latch : tri_rlmreg_p + generic map (width => ex3_mmu_hv_priv_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_mmu_hv_priv_offset to ex3_mmu_hv_priv_offset + ex3_mmu_hv_priv_q'length-1), + scout => sov(ex3_mmu_hv_priv_offset to ex3_mmu_hv_priv_offset + ex3_mmu_hv_priv_q'length-1), + din => mm_xu_hv_priv , + dout => ex3_mmu_hv_priv_q); +ex3_mtiar_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_mtiar_offset), + scout => sov(ex3_mtiar_offset), + din => ex2_mtiar, + dout => ex3_mtiar_q); +ex3_n_align_int_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_n_align_int_offset), + scout => sov(ex3_n_align_int_offset), + din => ex2_n_align_int_q , + dout => ex3_n_align_int_q); +ex3_n_dcpe_flush_latch : tri_rlmreg_p + generic map (width => ex3_n_dcpe_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_n_dcpe_flush_offset to ex3_n_dcpe_flush_offset + ex3_n_dcpe_flush_q'length-1), + scout => sov(ex3_n_dcpe_flush_offset to ex3_n_dcpe_flush_offset + ex3_n_dcpe_flush_q'length-1), + din => ex3_n_dcpe_flush_d, + dout => ex3_n_dcpe_flush_q); +ex3_n_l2_ecc_err_flush_latch : tri_rlmreg_p + generic map (width => ex3_n_l2_ecc_err_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_n_l2_ecc_err_flush_offset to ex3_n_l2_ecc_err_flush_offset + ex3_n_l2_ecc_err_flush_q'length-1), + scout => sov(ex3_n_l2_ecc_err_flush_offset to ex3_n_l2_ecc_err_flush_offset + ex3_n_l2_ecc_err_flush_q'length-1), + din => lsu_xu_l2_ecc_err_flush , + dout => ex3_n_l2_ecc_err_flush_q); +ex3_np1_run_ctl_flush_latch : tri_rlmreg_p + generic map (width => ex3_np1_run_ctl_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_np1_run_ctl_flush_offset to ex3_np1_run_ctl_flush_offset + ex3_np1_run_ctl_flush_q'length-1), + scout => sov(ex3_np1_run_ctl_flush_offset to ex3_np1_run_ctl_flush_offset + ex3_np1_run_ctl_flush_q'length-1), + din => spr_cpl_ex2_run_ctl_flush , + dout => ex3_np1_run_ctl_flush_q); +ex3_sc_lev_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_sc_lev_offset), + scout => sov(ex3_sc_lev_offset), + din => ex2_sc_lev_q , + dout => ex3_sc_lev_q); +ex3_taken_bclr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_taken_bclr_offset), + scout => sov(ex3_taken_bclr_offset), + din => ex2_taken_bclr_q , + dout => ex3_taken_bclr_q); +ex3_tlb_inelig_latch : tri_rlmreg_p + generic map (width => ex3_tlb_inelig_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_tlb_inelig_offset to ex3_tlb_inelig_offset + ex3_tlb_inelig_q'length-1), + scout => sov(ex3_tlb_inelig_offset to ex3_tlb_inelig_offset + ex3_tlb_inelig_q'length-1), + din => mm_xu_tlb_inelig , + dout => ex3_tlb_inelig_q); +ex3_tlb_local_snoop_reject_latch : tri_rlmreg_p + generic map (width => ex3_tlb_local_snoop_reject_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_tlb_local_snoop_reject_offset to ex3_tlb_local_snoop_reject_offset + ex3_tlb_local_snoop_reject_q'length-1), + scout => sov(ex3_tlb_local_snoop_reject_offset to ex3_tlb_local_snoop_reject_offset + ex3_tlb_local_snoop_reject_q'length-1), + din => mm_xu_local_snoop_reject , + dout => ex3_tlb_local_snoop_reject_q); +ex3_tlb_lru_par_err_latch : tri_rlmreg_p + generic map (width => ex3_tlb_lru_par_err_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_tlb_lru_par_err_offset to ex3_tlb_lru_par_err_offset + ex3_tlb_lru_par_err_q'length-1), + scout => sov(ex3_tlb_lru_par_err_offset to ex3_tlb_lru_par_err_offset + ex3_tlb_lru_par_err_q'length-1), + din => mm_xu_lru_par_err , + dout => ex3_tlb_lru_par_err_q); +ex3_tlb_illeg_latch : tri_rlmreg_p + generic map (width => ex3_tlb_illeg_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_tlb_illeg_offset to ex3_tlb_illeg_offset + ex3_tlb_illeg_q'length-1), + scout => sov(ex3_tlb_illeg_offset to ex3_tlb_illeg_offset + ex3_tlb_illeg_q'length-1), + din => mm_xu_illeg_instr , + dout => ex3_tlb_illeg_q); +ex3_tlb_miss_latch : tri_rlmreg_p + generic map (width => ex3_tlb_miss_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_tlb_miss_offset to ex3_tlb_miss_offset + ex3_tlb_miss_q'length-1), + scout => sov(ex3_tlb_miss_offset to ex3_tlb_miss_offset + ex3_tlb_miss_q'length-1), + din => mm_xu_tlb_miss , + dout => ex3_tlb_miss_q); +ex3_tlb_multihit_err_latch : tri_rlmreg_p + generic map (width => ex3_tlb_multihit_err_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_tlb_multihit_err_offset to ex3_tlb_multihit_err_offset + ex3_tlb_multihit_err_q'length-1), + scout => sov(ex3_tlb_multihit_err_offset to ex3_tlb_multihit_err_offset + ex3_tlb_multihit_err_q'length-1), + din => mm_xu_tlb_multihit_err , + dout => ex3_tlb_multihit_err_q); +ex3_tlb_par_err_latch : tri_rlmreg_p + generic map (width => ex3_tlb_par_err_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_tlb_par_err_offset to ex3_tlb_par_err_offset + ex3_tlb_par_err_q'length-1), + scout => sov(ex3_tlb_par_err_offset to ex3_tlb_par_err_offset + ex3_tlb_par_err_q'length-1), + din => mm_xu_tlb_par_err , + dout => ex3_tlb_par_err_q); +ex3_tlb_pt_fault_latch : tri_rlmreg_p + generic map (width => ex3_tlb_pt_fault_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_tlb_pt_fault_offset to ex3_tlb_pt_fault_offset + ex3_tlb_pt_fault_q'length-1), + scout => sov(ex3_tlb_pt_fault_offset to ex3_tlb_pt_fault_offset + ex3_tlb_pt_fault_q'length-1), + din => mm_xu_pt_fault , + dout => ex3_tlb_pt_fault_q); +ex3_ucode_val_latch : tri_rlmreg_p + generic map (width => ex3_ucode_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_ucode_val_offset to ex3_ucode_val_offset + ex3_ucode_val_q'length-1), + scout => sov(ex3_ucode_val_offset to ex3_ucode_val_offset + ex3_ucode_val_q'length-1), + din => ex2_ucode_val , + dout => ex3_ucode_val_q); +ex3_xu_instr_match_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_xu_instr_match_offset), + scout => sov(ex3_xu_instr_match_offset), + din => dec_cpl_ex2_match , + dout => ex3_xu_instr_match_q); +ex3_xu_is_ucode_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_xu_is_ucode_offset), + scout => sov(ex3_xu_is_ucode_offset), + din => dec_cpl_ex2_is_ucode , + dout => ex3_xu_is_ucode_q); +ex3_xu_val_latch : tri_rlmreg_p + generic map (width => ex3_xu_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_xu_val_offset to ex3_xu_val_offset + ex3_xu_val_q'length-1), + scout => sov(ex3_xu_val_offset to ex3_xu_val_offset + ex3_xu_val_q'length-1), + din => ex2_xu_val , + dout => ex3_xu_val_q); +ex3_axu_async_block_latch : tri_rlmreg_p + generic map (width => ex3_axu_async_block_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_axu_async_block_offset to ex3_axu_async_block_offset + ex3_axu_async_block_q'length-1), + scout => sov(ex3_axu_async_block_offset to ex3_axu_async_block_offset + ex3_axu_async_block_q'length-1), + din => fu_xu_ex2_async_block , + dout => ex3_axu_async_block_q); +ex3_is_mtxucr0_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_mtxucr0_offset), + scout => sov(ex3_is_mtxucr0_offset), + din => ex2_is_mtxucr0_q , + dout => ex3_is_mtxucr0_q); +ex3_np1_instr_flush_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_np1_instr_flush_offset), + scout => sov(ex3_np1_instr_flush_offset), + din => ex3_np1_instr_flush_d, + dout => ex3_np1_instr_flush_q); +ex4_apena_prog_int_latch : tri_rlmreg_p + generic map (width => ex4_apena_prog_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_apena_prog_int_offset to ex4_apena_prog_int_offset + ex4_apena_prog_int_q'length-1), + scout => sov(ex4_apena_prog_int_offset to ex4_apena_prog_int_offset + ex4_apena_prog_int_q'length-1), + din => ex3_n_apena_prog_int, + dout => ex4_apena_prog_int_q); +ex4_axu_is_ucode_latch : tri_rlmreg_p + generic map (width => ex4_axu_is_ucode_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_axu_is_ucode_offset to ex4_axu_is_ucode_offset + ex4_axu_is_ucode_q'length-1), + scout => sov(ex4_axu_is_ucode_offset to ex4_axu_is_ucode_offset + ex4_axu_is_ucode_q'length-1), + din => ex3_axu_is_ucode_q , + dout => ex4_axu_is_ucode_q); +ex4_axu_trap_latch : tri_rlmreg_p + generic map (width => ex4_axu_trap_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_axu_trap_offset to ex4_axu_trap_offset + ex4_axu_trap_q'length-1), + scout => sov(ex4_axu_trap_offset to ex4_axu_trap_offset + ex4_axu_trap_q'length-1), + din => fu_xu_ex3_trap , + dout => ex4_axu_trap_q); +ex4_axu_val_latch : tri_rlmreg_p + generic map (width => ex4_axu_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_axu_val_offset to ex4_axu_val_offset + ex4_axu_val_q'length-1), + scout => sov(ex4_axu_val_offset to ex4_axu_val_offset + ex4_axu_val_q'length-1), + din => ex3_axu_val , + dout => ex4_axu_val_q); +ex4_base_int_block_latch : tri_rlmreg_p + generic map (width => ex4_base_int_block_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_base_int_block_offset to ex4_base_int_block_offset + ex4_base_int_block_q'length-1), + scout => sov(ex4_base_int_block_offset to ex4_base_int_block_offset + ex4_base_int_block_q'length-1), + din => ex3_base_int_block , + dout => ex4_base_int_block_q); +ex4_br_flush_ifar_latch : tri_rlmreg_p + generic map (width => ex4_br_flush_ifar_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_br_flush_ifar_offset to ex4_br_flush_ifar_offset + ex4_br_flush_ifar_q'length-1), + scout => sov(ex4_br_flush_ifar_offset to ex4_br_flush_ifar_offset + ex4_br_flush_ifar_q'length-1), + din => ex3_br_flush_ifar_q , + dout => ex4_br_flush_ifar_q); +ex4_br_taken_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_br_taken_offset), + scout => sov(ex4_br_taken_offset), + din => ex3_br_taken_q , + dout => ex4_br_taken_q); +ex4_br_update_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_br_update_offset), + scout => sov(ex4_br_update_offset), + din => ex3_br_update_q , + dout => ex4_br_update_q); +ex4_byte_rev_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_byte_rev_offset), + scout => sov(ex4_byte_rev_offset), + din => ex3_byte_rev_q , + dout => ex4_byte_rev_q); +ex4_ctr_dec_update_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_ctr_dec_update_offset), + scout => sov(ex4_ctr_dec_update_offset), + din => ex3_ctr_dec_update_q , + dout => ex4_ctr_dec_update_q); +ex4_debug_flush_en_latch : tri_rlmreg_p + generic map (width => ex4_debug_flush_en_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_debug_flush_en_offset to ex4_debug_flush_en_offset + ex4_debug_flush_en_q'length-1), + scout => sov(ex4_debug_flush_en_offset to ex4_debug_flush_en_offset + ex4_debug_flush_en_q'length-1), + din => ex4_debug_flush_en_d, + dout => ex4_debug_flush_en_q); +ex4_debug_int_en_latch : tri_rlmreg_p + generic map (width => ex4_debug_int_en_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_debug_int_en_offset to ex4_debug_int_en_offset + ex4_debug_int_en_q'length-1), + scout => sov(ex4_debug_int_en_offset to ex4_debug_int_en_offset + ex4_debug_int_en_q'length-1), + din => ex3_debug_int_en, + dout => ex4_debug_int_en_q); +ex4_flush_latch : tri_rlmreg_p + generic map (width => ex4_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_flush_inf_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_flush_offset to ex4_flush_offset + ex4_flush_q'length-1), + scout => sov(ex4_flush_offset to ex4_flush_offset + ex4_flush_q'length-1), + din => ex3_flush , + dout => ex4_flush_q); +ex4_fpena_prog_int_latch : tri_rlmreg_p + generic map (width => ex4_fpena_prog_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_fpena_prog_int_offset to ex4_fpena_prog_int_offset + ex4_fpena_prog_int_q'length-1), + scout => sov(ex4_fpena_prog_int_offset to ex4_fpena_prog_int_offset + ex4_fpena_prog_int_q'length-1), + din => ex3_n_fpena_prog_int, + dout => ex4_fpena_prog_int_q); +ex4_iac1_cmpr_latch : tri_rlmreg_p + generic map (width => ex4_iac1_cmpr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_iac1_cmpr_offset to ex4_iac1_cmpr_offset + ex4_iac1_cmpr_q'length-1), + scout => sov(ex4_iac1_cmpr_offset to ex4_iac1_cmpr_offset + ex4_iac1_cmpr_q'length-1), + din => ex3_iac1_cmpr, + dout => ex4_iac1_cmpr_q); +ex4_iac2_cmpr_latch : tri_rlmreg_p + generic map (width => ex4_iac2_cmpr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_iac2_cmpr_offset to ex4_iac2_cmpr_offset + ex4_iac2_cmpr_q'length-1), + scout => sov(ex4_iac2_cmpr_offset to ex4_iac2_cmpr_offset + ex4_iac2_cmpr_q'length-1), + din => ex3_iac2_cmpr, + dout => ex4_iac2_cmpr_q); +ex4_iac3_cmpr_latch : tri_rlmreg_p + generic map (width => ex4_iac3_cmpr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_iac3_cmpr_offset to ex4_iac3_cmpr_offset + ex4_iac3_cmpr_q'length-1), + scout => sov(ex4_iac3_cmpr_offset to ex4_iac3_cmpr_offset + ex4_iac3_cmpr_q'length-1), + din => ex3_iac3_cmpr, + dout => ex4_iac3_cmpr_q); +ex4_iac4_cmpr_latch : tri_rlmreg_p + generic map (width => ex4_iac4_cmpr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_iac4_cmpr_offset to ex4_iac4_cmpr_offset + ex4_iac4_cmpr_q'length-1), + scout => sov(ex4_iac4_cmpr_offset to ex4_iac4_cmpr_offset + ex4_iac4_cmpr_q'length-1), + din => ex3_iac4_cmpr, + dout => ex4_iac4_cmpr_q); +ex4_instr_cpl_latch : tri_rlmreg_p + generic map (width => ex4_instr_cpl_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_instr_cpl_offset to ex4_instr_cpl_offset + ex4_instr_cpl_q'length-1), + scout => sov(ex4_instr_cpl_offset to ex4_instr_cpl_offset + ex4_instr_cpl_q'length-1), + din => ex4_instr_cpl_d, + dout => ex4_instr_cpl_q); +ex4_is_any_load_dac_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_is_any_load_dac_offset), + scout => sov(ex4_is_any_load_dac_offset), + din => ex3_is_any_load_dac_q , + dout => ex4_is_any_load_dac_q); +ex4_is_any_store_dac_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_is_any_store_dac_offset), + scout => sov(ex4_is_any_store_dac_offset), + din => ex3_is_any_store_dac_q , + dout => ex4_is_any_store_dac_q); +ex4_is_attn_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_is_attn_offset), + scout => sov(ex4_is_attn_offset), + din => ex3_is_attn_q , + dout => ex4_is_attn_q); +ex4_is_dci_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_is_dci_offset), + scout => sov(ex4_is_dci_offset), + din => ex3_is_dci_q , + dout => ex4_is_dci_q); +ex4_is_ehpriv_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_is_ehpriv_offset), + scout => sov(ex4_is_ehpriv_offset), + din => ex3_is_ehpriv_q , + dout => ex4_is_ehpriv_q); +ex4_is_ici_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_is_ici_offset), + scout => sov(ex4_is_ici_offset), + din => ex3_is_ici_q , + dout => ex4_is_ici_q); +ex4_is_isync_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_is_isync_offset), + scout => sov(ex4_is_isync_offset), + din => ex3_is_isync_q , + dout => ex4_is_isync_q); +ex4_is_mtmsr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_is_mtmsr_offset), + scout => sov(ex4_is_mtmsr_offset), + din => ex3_is_mtmsr_q , + dout => ex4_is_mtmsr_q); +ex4_is_tlbwe_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_is_tlbwe_offset), + scout => sov(ex4_is_tlbwe_offset), + din => ex3_is_tlbwe_q , + dout => ex4_is_tlbwe_q); +ex4_is_slowspr_wr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_is_slowspr_wr_offset), + scout => sov(ex4_is_slowspr_wr_offset), + din => ex3_is_slowspr_wr_q , + dout => ex4_is_slowspr_wr_q); +ex4_lr_update_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_lr_update_offset), + scout => sov(ex4_lr_update_offset), + din => ex3_lr_update_q , + dout => ex4_lr_update_q); +ex4_mcsr_latch : tri_rlmreg_p + generic map (width => ex4_mcsr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_mcsr_offset to ex4_mcsr_offset + ex4_mcsr_q'length-1), + scout => sov(ex4_mcsr_offset to ex4_mcsr_offset + ex4_mcsr_q'length-1), + din => ex4_mcsr_d, + dout => ex4_mcsr_q); +ex4_mem_attr_latch : tri_rlmreg_p + generic map (width => ex4_mem_attr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_mem_attr_offset to ex4_mem_attr_offset + ex4_mem_attr_q'length-1), + scout => sov(ex4_mem_attr_offset to ex4_mem_attr_offset + ex4_mem_attr_q'length-1), + din => lsu_xu_ex3_attr , + dout => ex4_mem_attr_q); +ex4_mmu_esr_data_latch : tri_rlmreg_p + generic map (width => ex4_mmu_esr_data_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_mmu_esr_data_offset to ex4_mmu_esr_data_offset + ex4_mmu_esr_data_q'length-1), + scout => sov(ex4_mmu_esr_data_offset to ex4_mmu_esr_data_offset + ex4_mmu_esr_data_q'length-1), + din => ex3_mmu_esr_data_q , + dout => ex4_mmu_esr_data_q); +ex4_mmu_esr_epid_latch : tri_rlmreg_p + generic map (width => ex4_mmu_esr_epid_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_mmu_esr_epid_offset to ex4_mmu_esr_epid_offset + ex4_mmu_esr_epid_q'length-1), + scout => sov(ex4_mmu_esr_epid_offset to ex4_mmu_esr_epid_offset + ex4_mmu_esr_epid_q'length-1), + din => ex3_mmu_esr_epid_q , + dout => ex4_mmu_esr_epid_q); +ex4_mmu_esr_pt_latch : tri_rlmreg_p + generic map (width => ex4_mmu_esr_pt_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_mmu_esr_pt_offset to ex4_mmu_esr_pt_offset + ex4_mmu_esr_pt_q'length-1), + scout => sov(ex4_mmu_esr_pt_offset to ex4_mmu_esr_pt_offset + ex4_mmu_esr_pt_q'length-1), + din => ex3_mmu_esr_pt_q , + dout => ex4_mmu_esr_pt_q); +ex4_mmu_esr_st_latch : tri_rlmreg_p + generic map (width => ex4_mmu_esr_st_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_mmu_esr_st_offset to ex4_mmu_esr_st_offset + ex4_mmu_esr_st_q'length-1), + scout => sov(ex4_mmu_esr_st_offset to ex4_mmu_esr_st_offset + ex4_mmu_esr_st_q'length-1), + din => ex3_mmu_esr_st_q , + dout => ex4_mmu_esr_st_q); +ex4_mmu_esr_val_latch : tri_rlmreg_p + generic map (width => ex4_mmu_esr_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_mmu_esr_val_offset to ex4_mmu_esr_val_offset + ex4_mmu_esr_val_q'length-1), + scout => sov(ex4_mmu_esr_val_offset to ex4_mmu_esr_val_offset + ex4_mmu_esr_val_q'length-1), + din => ex4_mmu_esr_val_d, + dout => ex4_mmu_esr_val_q); +ex4_mmu_hold_val_latch : tri_rlmreg_p + generic map (width => ex4_mmu_hold_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_mmu_hold_val_offset to ex4_mmu_hold_val_offset + ex4_mmu_hold_val_q'length-1), + scout => sov(ex4_mmu_hold_val_offset to ex4_mmu_hold_val_offset + ex4_mmu_hold_val_q'length-1), + din => ex3_mmu_hold_val, + dout => ex4_mmu_hold_val_q); +ex4_mtdp_nr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_mtdp_nr_offset), + scout => sov(ex4_mtdp_nr_offset), + din => dec_cpl_ex3_mtdp_nr , + dout => ex4_mtdp_nr_q); +ex4_mtiar_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_mtiar_offset), + scout => sov(ex4_mtiar_offset), + din => ex3_mtiar_q , + dout => ex4_mtiar_q); +ex4_n_2ucode_flush_latch : tri_rlmreg_p + generic map (width => ex4_n_2ucode_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_2ucode_flush_offset to ex4_n_2ucode_flush_offset + ex4_n_2ucode_flush_q'length-1), + scout => sov(ex4_n_2ucode_flush_offset to ex4_n_2ucode_flush_offset + ex4_n_2ucode_flush_q'length-1), + din => ex3_n_2ucode_flush, + dout => ex4_n_2ucode_flush_q); +ex4_n_align_int_latch : tri_rlmreg_p + generic map (width => ex4_n_align_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_align_int_offset to ex4_n_align_int_offset + ex4_n_align_int_q'length-1), + scout => sov(ex4_n_align_int_offset to ex4_n_align_int_offset + ex4_n_align_int_q'length-1), + din => ex3_n_align_int, + dout => ex4_n_align_int_q); +ex4_n_any_hpriv_int_latch : tri_rlmreg_p + generic map (width => ex4_n_any_hpriv_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_any_hpriv_int_offset to ex4_n_any_hpriv_int_offset + ex4_n_any_hpriv_int_q'length-1), + scout => sov(ex4_n_any_hpriv_int_offset to ex4_n_any_hpriv_int_offset + ex4_n_any_hpriv_int_q'length-1), + din => ex4_n_any_hpriv_int_d, + dout => ex4_n_any_hpriv_int_q); +ex4_n_any_unavail_int_latch : tri_rlmreg_p + generic map (width => ex4_n_any_unavail_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_any_unavail_int_offset to ex4_n_any_unavail_int_offset + ex4_n_any_unavail_int_q'length-1), + scout => sov(ex4_n_any_unavail_int_offset to ex4_n_any_unavail_int_offset + ex4_n_any_unavail_int_q'length-1), + din => ex3_n_any_unavail_int, + dout => ex4_n_any_unavail_int_q); +ex4_n_ap_unavail_int_latch : tri_rlmreg_p + generic map (width => ex4_n_ap_unavail_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_ap_unavail_int_offset to ex4_n_ap_unavail_int_offset + ex4_n_ap_unavail_int_q'length-1), + scout => sov(ex4_n_ap_unavail_int_offset to ex4_n_ap_unavail_int_offset + ex4_n_ap_unavail_int_q'length-1), + din => ex3_n_ap_unavail_int, + dout => ex4_n_ap_unavail_int_q); +ex4_n_barr_flush_latch : tri_rlmreg_p + generic map (width => ex4_n_barr_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_barr_flush_offset to ex4_n_barr_flush_offset + ex4_n_barr_flush_q'length-1), + scout => sov(ex4_n_barr_flush_offset to ex4_n_barr_flush_offset + ex4_n_barr_flush_q'length-1), + din => ex3_n_barr_flush, + dout => ex4_n_barr_flush_q); +ex4_n_bclr_ta_miscmpr_flush_latch : tri_rlmreg_p + generic map (width => ex4_n_bclr_ta_miscmpr_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_bclr_ta_miscmpr_flush_offset to ex4_n_bclr_ta_miscmpr_flush_offset + ex4_n_bclr_ta_miscmpr_flush_q'length-1), + scout => sov(ex4_n_bclr_ta_miscmpr_flush_offset to ex4_n_bclr_ta_miscmpr_flush_offset + ex4_n_bclr_ta_miscmpr_flush_q'length-1), + din => ex3_n_bclr_ta_miscmpr_flush, + dout => ex4_n_bclr_ta_miscmpr_flush_q); +ex4_n_brt_dbg_cint_latch : tri_rlmreg_p + generic map (width => ex4_n_brt_dbg_cint_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_brt_dbg_cint_offset to ex4_n_brt_dbg_cint_offset + ex4_n_brt_dbg_cint_q'length-1), + scout => sov(ex4_n_brt_dbg_cint_offset to ex4_n_brt_dbg_cint_offset + ex4_n_brt_dbg_cint_q'length-1), + din => ex3_n_brt_dbg_cint, + dout => ex4_n_brt_dbg_cint_q); +ex4_n_dac_dbg_cint_latch : tri_rlmreg_p + generic map (width => ex4_n_dac_dbg_cint_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_dac_dbg_cint_offset to ex4_n_dac_dbg_cint_offset + ex4_n_dac_dbg_cint_q'length-1), + scout => sov(ex4_n_dac_dbg_cint_offset to ex4_n_dac_dbg_cint_offset + ex4_n_dac_dbg_cint_q'length-1), + din => ex3_n_dac_dbg_cint, + dout => ex4_n_dac_dbg_cint_q); +ex4_n_ddmh_mchk_en_latch : tri_rlmreg_p + generic map (width => ex4_n_ddmh_mchk_en_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_ddmh_mchk_en_offset to ex4_n_ddmh_mchk_en_offset + ex4_n_ddmh_mchk_en_q'length-1), + scout => sov(ex4_n_ddmh_mchk_en_offset to ex4_n_ddmh_mchk_en_offset + ex4_n_ddmh_mchk_en_q'length-1), + din => ex4_n_ddmh_mchk_en_d, + dout => ex4_n_ddmh_mchk_en_q); +ex4_n_dep_flush_latch : tri_rlmreg_p + generic map (width => ex4_n_dep_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_dep_flush_offset to ex4_n_dep_flush_offset + ex4_n_dep_flush_q'length-1), + scout => sov(ex4_n_dep_flush_offset to ex4_n_dep_flush_offset + ex4_n_dep_flush_q'length-1), + din => ex3_n_dep_flush, + dout => ex4_n_dep_flush_q); +ex4_n_deratre_par_mchk_mcint_latch : tri_rlmreg_p + generic map (width => ex4_n_deratre_par_mchk_mcint_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_deratre_par_mchk_mcint_offset to ex4_n_deratre_par_mchk_mcint_offset + ex4_n_deratre_par_mchk_mcint_q'length-1), + scout => sov(ex4_n_deratre_par_mchk_mcint_offset to ex4_n_deratre_par_mchk_mcint_offset + ex4_n_deratre_par_mchk_mcint_q'length-1), + din => ex3_n_deratre_par_mchk_mcint, + dout => ex4_n_deratre_par_mchk_mcint_q); +ex4_n_dlk0_dstor_int_latch : tri_rlmreg_p + generic map (width => ex4_n_dlk0_dstor_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_dlk0_dstor_int_offset to ex4_n_dlk0_dstor_int_offset + ex4_n_dlk0_dstor_int_q'length-1), + scout => sov(ex4_n_dlk0_dstor_int_offset to ex4_n_dlk0_dstor_int_offset + ex4_n_dlk0_dstor_int_q'length-1), + din => ex3_n_dlk0_dstor_int, + dout => ex4_n_dlk0_dstor_int_q); +ex4_n_dlk1_dstor_int_latch : tri_rlmreg_p + generic map (width => ex4_n_dlk1_dstor_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_dlk1_dstor_int_offset to ex4_n_dlk1_dstor_int_offset + ex4_n_dlk1_dstor_int_q'length-1), + scout => sov(ex4_n_dlk1_dstor_int_offset to ex4_n_dlk1_dstor_int_offset + ex4_n_dlk1_dstor_int_q'length-1), + din => ex3_n_dlk1_dstor_int, + dout => ex4_n_dlk1_dstor_int_q); +ex4_n_dlrat_int_latch : tri_rlmreg_p + generic map (width => ex4_n_dlrat_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_dlrat_int_offset to ex4_n_dlrat_int_offset + ex4_n_dlrat_int_q'length-1), + scout => sov(ex4_n_dlrat_int_offset to ex4_n_dlrat_int_offset + ex4_n_dlrat_int_q'length-1), + din => ex3_n_dlrat_int, + dout => ex4_n_dlrat_int_q); +ex4_n_dmchk_mcint_latch : tri_rlmreg_p + generic map (width => ex4_n_dmchk_mcint_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_dmchk_mcint_offset to ex4_n_dmchk_mcint_offset + ex4_n_dmchk_mcint_q'length-1), + scout => sov(ex4_n_dmchk_mcint_offset to ex4_n_dmchk_mcint_offset + ex4_n_dmchk_mcint_q'length-1), + din => ex3_n_dmchk_mcint, + dout => ex4_n_dmchk_mcint_q); +ex4_n_dmiss_flush_latch : tri_rlmreg_p + generic map (width => ex4_n_dmiss_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_dmiss_flush_offset to ex4_n_dmiss_flush_offset + ex4_n_dmiss_flush_q'length-1), + scout => sov(ex4_n_dmiss_flush_offset to ex4_n_dmiss_flush_offset + ex4_n_dmiss_flush_q'length-1), + din => ex3_n_dmiss_flush, + dout => ex4_n_dmiss_flush_q); +ex4_n_dstor_int_latch : tri_rlmreg_p + generic map (width => ex4_n_dstor_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_dstor_int_offset to ex4_n_dstor_int_offset + ex4_n_dstor_int_q'length-1), + scout => sov(ex4_n_dstor_int_offset to ex4_n_dstor_int_offset + ex4_n_dstor_int_q'length-1), + din => ex3_n_dstor_int, + dout => ex4_n_dstor_int_q); +ex4_n_dtlb_int_latch : tri_rlmreg_p + generic map (width => ex4_n_dtlb_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_dtlb_int_offset to ex4_n_dtlb_int_offset + ex4_n_dtlb_int_q'length-1), + scout => sov(ex4_n_dtlb_int_offset to ex4_n_dtlb_int_offset + ex4_n_dtlb_int_q'length-1), + din => ex3_n_dtlb_int, + dout => ex4_n_dtlb_int_q); +ex4_n_ena_prog_int_latch : tri_rlmreg_p + generic map (width => ex4_n_ena_prog_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_ena_prog_int_offset to ex4_n_ena_prog_int_offset + ex4_n_ena_prog_int_q'length-1), + scout => sov(ex4_n_ena_prog_int_offset to ex4_n_ena_prog_int_offset + ex4_n_ena_prog_int_q'length-1), + din => ex3_n_ena_prog_int, + dout => ex4_n_ena_prog_int_q); +ex4_n_flush_latch : tri_rlmreg_p + generic map (width => ex4_n_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_flush_offset to ex4_n_flush_offset + ex4_n_flush_q'length-1), + scout => sov(ex4_n_flush_offset to ex4_n_flush_offset + ex4_n_flush_q'length-1), + din => ex3_n_flush, + dout => ex4_n_flush_q); +ex4_n_pe_flush_latch : tri_rlmreg_p + generic map (width => ex4_n_pe_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_pe_flush_offset to ex4_n_pe_flush_offset + ex4_n_pe_flush_q'length-1), + scout => sov(ex4_n_pe_flush_offset to ex4_n_pe_flush_offset + ex4_n_pe_flush_q'length-1), + din => ex3_n_pe_flush, + dout => ex4_n_pe_flush_q); +ex4_n_tlb_mchk_flush_latch : tri_rlmreg_p + generic map (width => ex4_n_tlb_mchk_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_tlb_mchk_flush_offset to ex4_n_tlb_mchk_flush_offset + ex4_n_tlb_mchk_flush_q'length-1), + scout => sov(ex4_n_tlb_mchk_flush_offset to ex4_n_tlb_mchk_flush_offset + ex4_n_tlb_mchk_flush_q'length-1), + din => ex3_n_tlb_mchk_flush, + dout => ex4_n_tlb_mchk_flush_q); +ex4_n_fp_unavail_int_latch : tri_rlmreg_p + generic map (width => ex4_n_fp_unavail_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_fp_unavail_int_offset to ex4_n_fp_unavail_int_offset + ex4_n_fp_unavail_int_q'length-1), + scout => sov(ex4_n_fp_unavail_int_offset to ex4_n_fp_unavail_int_offset + ex4_n_fp_unavail_int_q'length-1), + din => ex3_n_fp_unavail_int, + dout => ex4_n_fp_unavail_int_q); +ex4_n_fu_rfpe_flush_latch : tri_rlmreg_p + generic map (width => ex4_n_fu_rfpe_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_fu_rfpe_flush_offset to ex4_n_fu_rfpe_flush_offset + ex4_n_fu_rfpe_flush_q'length-1), + scout => sov(ex4_n_fu_rfpe_flush_offset to ex4_n_fu_rfpe_flush_offset + ex4_n_fu_rfpe_flush_q'length-1), + din => ex4_n_fu_rfpe_flush_d, + dout => ex4_n_fu_rfpe_flush_q); +ex4_n_iac_dbg_cint_latch : tri_rlmreg_p + generic map (width => ex4_n_iac_dbg_cint_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_iac_dbg_cint_offset to ex4_n_iac_dbg_cint_offset + ex4_n_iac_dbg_cint_q'length-1), + scout => sov(ex4_n_iac_dbg_cint_offset to ex4_n_iac_dbg_cint_offset + ex4_n_iac_dbg_cint_q'length-1), + din => ex3_n_iac_dbg_cint, + dout => ex4_n_iac_dbg_cint_q); +ex4_n_ieratre_par_mchk_mcint_latch : tri_rlmreg_p + generic map (width => ex4_n_ieratre_par_mchk_mcint_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_ieratre_par_mchk_mcint_offset to ex4_n_ieratre_par_mchk_mcint_offset + ex4_n_ieratre_par_mchk_mcint_q'length-1), + scout => sov(ex4_n_ieratre_par_mchk_mcint_offset to ex4_n_ieratre_par_mchk_mcint_offset + ex4_n_ieratre_par_mchk_mcint_q'length-1), + din => ex3_n_ieratre_par_mchk_mcint, + dout => ex4_n_ieratre_par_mchk_mcint_q); +ex4_n_ilrat_int_latch : tri_rlmreg_p + generic map (width => ex4_n_ilrat_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_ilrat_int_offset to ex4_n_ilrat_int_offset + ex4_n_ilrat_int_q'length-1), + scout => sov(ex4_n_ilrat_int_offset to ex4_n_ilrat_int_offset + ex4_n_ilrat_int_q'length-1), + din => ex3_n_ilrat_int, + dout => ex4_n_ilrat_int_q); +ex4_n_imchk_mcint_latch : tri_rlmreg_p + generic map (width => ex4_n_imchk_mcint_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_imchk_mcint_offset to ex4_n_imchk_mcint_offset + ex4_n_imchk_mcint_q'length-1), + scout => sov(ex4_n_imchk_mcint_offset to ex4_n_imchk_mcint_offset + ex4_n_imchk_mcint_q'length-1), + din => ex3_n_imchk_mcint, + dout => ex4_n_imchk_mcint_q); +ex4_n_imiss_flush_latch : tri_rlmreg_p + generic map (width => ex4_n_imiss_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_imiss_flush_offset to ex4_n_imiss_flush_offset + ex4_n_imiss_flush_q'length-1), + scout => sov(ex4_n_imiss_flush_offset to ex4_n_imiss_flush_offset + ex4_n_imiss_flush_q'length-1), + din => ex3_n_imiss_flush, + dout => ex4_n_imiss_flush_q); +ex4_n_instr_dbg_cint_latch : tri_rlmreg_p + generic map (width => ex4_n_instr_dbg_cint_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_instr_dbg_cint_offset to ex4_n_instr_dbg_cint_offset + ex4_n_instr_dbg_cint_q'length-1), + scout => sov(ex4_n_instr_dbg_cint_offset to ex4_n_instr_dbg_cint_offset + ex4_n_instr_dbg_cint_q'length-1), + din => ex3_n_instr_dbg_cint, + dout => ex4_n_instr_dbg_cint_q); +ex4_n_istor_int_latch : tri_rlmreg_p + generic map (width => ex4_n_istor_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_istor_int_offset to ex4_n_istor_int_offset + ex4_n_istor_int_q'length-1), + scout => sov(ex4_n_istor_int_offset to ex4_n_istor_int_offset + ex4_n_istor_int_q'length-1), + din => ex3_n_istor_int, + dout => ex4_n_istor_int_q); +ex4_n_itlb_int_latch : tri_rlmreg_p + generic map (width => ex4_n_itlb_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_itlb_int_offset to ex4_n_itlb_int_offset + ex4_n_itlb_int_q'length-1), + scout => sov(ex4_n_itlb_int_offset to ex4_n_itlb_int_offset + ex4_n_itlb_int_q'length-1), + din => ex3_n_itlb_int, + dout => ex4_n_itlb_int_q); +ex4_n_ivc_dbg_cint_latch : tri_rlmreg_p + generic map (width => ex4_n_ivc_dbg_cint_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_ivc_dbg_cint_offset to ex4_n_ivc_dbg_cint_offset + ex4_n_ivc_dbg_cint_q'length-1), + scout => sov(ex4_n_ivc_dbg_cint_offset to ex4_n_ivc_dbg_cint_offset + ex4_n_ivc_dbg_cint_q'length-1), + din => ex3_n_ivc_dbg_cint, + dout => ex4_n_ivc_dbg_cint_q); +ex4_n_ivc_dbg_match_latch : tri_rlmreg_p + generic map (width => ex4_n_ivc_dbg_match_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_ivc_dbg_match_offset to ex4_n_ivc_dbg_match_offset + ex4_n_ivc_dbg_match_q'length-1), + scout => sov(ex4_n_ivc_dbg_match_offset to ex4_n_ivc_dbg_match_offset + ex4_n_ivc_dbg_match_q'length-1), + din => ex3_n_ivc_dbg_match, + dout => ex4_n_ivc_dbg_match_q); +ex4_n_ldq_hit_flush_latch : tri_rlmreg_p + generic map (width => ex4_n_ldq_hit_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_ldq_hit_flush_offset to ex4_n_ldq_hit_flush_offset + ex4_n_ldq_hit_flush_q'length-1), + scout => sov(ex4_n_ldq_hit_flush_offset to ex4_n_ldq_hit_flush_offset + ex4_n_ldq_hit_flush_q'length-1), + din => ex3_n_ldq_hit_flush, + dout => ex4_n_ldq_hit_flush_q); +ex4_n_lsu_ddmh_flush_en_latch : tri_rlmreg_p + generic map (width => ex4_n_lsu_ddmh_flush_en_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_lsu_ddmh_flush_en_offset to ex4_n_lsu_ddmh_flush_en_offset + ex4_n_lsu_ddmh_flush_en_q'length-1), + scout => sov(ex4_n_lsu_ddmh_flush_en_offset to ex4_n_lsu_ddmh_flush_en_offset + ex4_n_lsu_ddmh_flush_en_q'length-1), + din => ex4_n_lsu_ddmh_flush_en_d, + dout => ex4_n_lsu_ddmh_flush_en_q); +ex4_n_lsu_flush_latch : tri_rlmreg_p + generic map (width => ex4_n_lsu_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_lsu_flush_offset to ex4_n_lsu_flush_offset + ex4_n_lsu_flush_q'length-1), + scout => sov(ex4_n_lsu_flush_offset to ex4_n_lsu_flush_offset + ex4_n_lsu_flush_q'length-1), + din => ex3_n_lsu_flush, + dout => ex4_n_lsu_flush_q); +ex4_n_memattr_miscmpr_flush_latch : tri_rlmreg_p + generic map (width => ex4_n_memattr_miscmpr_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_memattr_miscmpr_flush_offset to ex4_n_memattr_miscmpr_flush_offset + ex4_n_memattr_miscmpr_flush_q'length-1), + scout => sov(ex4_n_memattr_miscmpr_flush_offset to ex4_n_memattr_miscmpr_flush_offset + ex4_n_memattr_miscmpr_flush_q'length-1), + din => ex3_n_memattr_miscmpr_flush, + dout => ex4_n_memattr_miscmpr_flush_q); +ex4_n_mmu_hpriv_int_latch : tri_rlmreg_p + generic map (width => ex4_n_mmu_hpriv_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_mmu_hpriv_int_offset to ex4_n_mmu_hpriv_int_offset + ex4_n_mmu_hpriv_int_q'length-1), + scout => sov(ex4_n_mmu_hpriv_int_offset to ex4_n_mmu_hpriv_int_offset + ex4_n_mmu_hpriv_int_q'length-1), + din => ex3_n_mmu_hpriv_int, + dout => ex4_n_mmu_hpriv_int_q); +ex4_n_pil_prog_int_latch : tri_rlmreg_p + generic map (width => ex4_n_pil_prog_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_pil_prog_int_offset to ex4_n_pil_prog_int_offset + ex4_n_pil_prog_int_q'length-1), + scout => sov(ex4_n_pil_prog_int_offset to ex4_n_pil_prog_int_offset + ex4_n_pil_prog_int_q'length-1), + din => ex3_n_pil_prog_int, + dout => ex4_n_pil_prog_int_q); +ex4_n_ppr_prog_int_latch : tri_rlmreg_p + generic map (width => ex4_n_ppr_prog_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_ppr_prog_int_offset to ex4_n_ppr_prog_int_offset + ex4_n_ppr_prog_int_q'length-1), + scout => sov(ex4_n_ppr_prog_int_offset to ex4_n_ppr_prog_int_offset + ex4_n_ppr_prog_int_q'length-1), + din => ex3_n_ppr_prog_int, + dout => ex4_n_ppr_prog_int_q); +ex4_n_ptemiss_dlrat_int_latch : tri_rlmreg_p + generic map (width => ex4_n_ptemiss_dlrat_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_ptemiss_dlrat_int_offset to ex4_n_ptemiss_dlrat_int_offset + ex4_n_ptemiss_dlrat_int_q'length-1), + scout => sov(ex4_n_ptemiss_dlrat_int_offset to ex4_n_ptemiss_dlrat_int_offset + ex4_n_ptemiss_dlrat_int_q'length-1), + din => ex3_n_ptemiss_dlrat_int, + dout => ex4_n_ptemiss_dlrat_int_q); +ex4_n_puo_prog_int_latch : tri_rlmreg_p + generic map (width => ex4_n_puo_prog_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_puo_prog_int_offset to ex4_n_puo_prog_int_offset + ex4_n_puo_prog_int_q'length-1), + scout => sov(ex4_n_puo_prog_int_offset to ex4_n_puo_prog_int_offset + ex4_n_puo_prog_int_q'length-1), + din => ex3_n_puo_prog_int, + dout => ex4_n_puo_prog_int_q); +ex4_n_ret_dbg_cint_latch : tri_rlmreg_p + generic map (width => ex4_n_ret_dbg_cint_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_ret_dbg_cint_offset to ex4_n_ret_dbg_cint_offset + ex4_n_ret_dbg_cint_q'length-1), + scout => sov(ex4_n_ret_dbg_cint_offset to ex4_n_ret_dbg_cint_offset + ex4_n_ret_dbg_cint_q'length-1), + din => ex3_n_ret_dbg_cint, + dout => ex4_n_ret_dbg_cint_q); +ex4_n_thrctl_stop_flush_latch : tri_rlmreg_p + generic map (width => ex4_n_thrctl_stop_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_thrctl_stop_flush_offset to ex4_n_thrctl_stop_flush_offset + ex4_n_thrctl_stop_flush_q'length-1), + scout => sov(ex4_n_thrctl_stop_flush_offset to ex4_n_thrctl_stop_flush_offset + ex4_n_thrctl_stop_flush_q'length-1), + din => ex3_n_thrctl_stop_flush, + dout => ex4_n_thrctl_stop_flush_q); +ex4_n_tlbwemiss_dlrat_int_latch : tri_rlmreg_p + generic map (width => ex4_n_tlbwemiss_dlrat_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_tlbwemiss_dlrat_int_offset to ex4_n_tlbwemiss_dlrat_int_offset + ex4_n_tlbwemiss_dlrat_int_q'length-1), + scout => sov(ex4_n_tlbwemiss_dlrat_int_offset to ex4_n_tlbwemiss_dlrat_int_offset + ex4_n_tlbwemiss_dlrat_int_q'length-1), + din => ex3_n_tlbwemiss_dlrat_int, + dout => ex4_n_tlbwemiss_dlrat_int_q); +ex4_n_tlbwe_pil_prog_int_latch : tri_rlmreg_p + generic map (width => ex4_n_tlbwe_pil_prog_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_tlbwe_pil_prog_int_offset to ex4_n_tlbwe_pil_prog_int_offset + ex4_n_tlbwe_pil_prog_int_q'length-1), + scout => sov(ex4_n_tlbwe_pil_prog_int_offset to ex4_n_tlbwe_pil_prog_int_offset + ex4_n_tlbwe_pil_prog_int_q'length-1), + din => ex3_n_tlbwe_pil_prog_int, + dout => ex4_n_tlbwe_pil_prog_int_q); +ex4_n_trap_dbg_cint_latch : tri_rlmreg_p + generic map (width => ex4_n_trap_dbg_cint_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_trap_dbg_cint_offset to ex4_n_trap_dbg_cint_offset + ex4_n_trap_dbg_cint_q'length-1), + scout => sov(ex4_n_trap_dbg_cint_offset to ex4_n_trap_dbg_cint_offset + ex4_n_trap_dbg_cint_q'length-1), + din => ex3_n_trap_dbg_cint, + dout => ex4_n_trap_dbg_cint_q); +ex4_n_uct_dstor_int_latch : tri_rlmreg_p + generic map (width => ex4_n_uct_dstor_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_uct_dstor_int_offset to ex4_n_uct_dstor_int_offset + ex4_n_uct_dstor_int_q'length-1), + scout => sov(ex4_n_uct_dstor_int_offset to ex4_n_uct_dstor_int_offset + ex4_n_uct_dstor_int_q'length-1), + din => ex3_n_uct_dstor_int, + dout => ex4_n_uct_dstor_int_q); +ex4_n_vec_unavail_int_latch : tri_rlmreg_p + generic map (width => ex4_n_vec_unavail_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_vec_unavail_int_offset to ex4_n_vec_unavail_int_offset + ex4_n_vec_unavail_int_q'length-1), + scout => sov(ex4_n_vec_unavail_int_offset to ex4_n_vec_unavail_int_offset + ex4_n_vec_unavail_int_q'length-1), + din => ex3_n_vec_unavail_int, + dout => ex4_n_vec_unavail_int_q); +ex4_n_vf_dstor_int_latch : tri_rlmreg_p + generic map (width => ex4_n_vf_dstor_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_vf_dstor_int_offset to ex4_n_vf_dstor_int_offset + ex4_n_vf_dstor_int_q'length-1), + scout => sov(ex4_n_vf_dstor_int_offset to ex4_n_vf_dstor_int_offset + ex4_n_vf_dstor_int_q'length-1), + din => ex3_n_vf_dstor_int, + dout => ex4_n_vf_dstor_int_q); +ex4_n_xu_rfpe_flush_latch : tri_rlmreg_p + generic map (width => ex4_n_xu_rfpe_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_xu_rfpe_flush_offset to ex4_n_xu_rfpe_flush_offset + ex4_n_xu_rfpe_flush_q'length-1), + scout => sov(ex4_n_xu_rfpe_flush_offset to ex4_n_xu_rfpe_flush_offset + ex4_n_xu_rfpe_flush_q'length-1), + din => ex4_n_xu_rfpe_flush_d, + dout => ex4_n_xu_rfpe_flush_q); +ex4_np1_cdbell_cint_latch : tri_rlmreg_p + generic map (width => ex4_np1_cdbell_cint_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_np1_cdbell_cint_offset to ex4_np1_cdbell_cint_offset + ex4_np1_cdbell_cint_q'length-1), + scout => sov(ex4_np1_cdbell_cint_offset to ex4_np1_cdbell_cint_offset + ex4_np1_cdbell_cint_q'length-1), + din => ex3_np1_cdbell_cint, + dout => ex4_np1_cdbell_cint_q); +ex4_np1_crit_cint_latch : tri_rlmreg_p + generic map (width => ex4_np1_crit_cint_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_np1_crit_cint_offset to ex4_np1_crit_cint_offset + ex4_np1_crit_cint_q'length-1), + scout => sov(ex4_np1_crit_cint_offset to ex4_np1_crit_cint_offset + ex4_np1_crit_cint_q'length-1), + din => ex3_np1_crit_cint, + dout => ex4_np1_crit_cint_q); +ex4_np1_dbell_int_latch : tri_rlmreg_p + generic map (width => ex4_np1_dbell_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_np1_dbell_int_offset to ex4_np1_dbell_int_offset + ex4_np1_dbell_int_q'length-1), + scout => sov(ex4_np1_dbell_int_offset to ex4_np1_dbell_int_offset + ex4_np1_dbell_int_q'length-1), + din => ex3_np1_dbell_int, + dout => ex4_np1_dbell_int_q); +ex4_np1_dec_int_latch : tri_rlmreg_p + generic map (width => ex4_np1_dec_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_np1_dec_int_offset to ex4_np1_dec_int_offset + ex4_np1_dec_int_q'length-1), + scout => sov(ex4_np1_dec_int_offset to ex4_np1_dec_int_offset + ex4_np1_dec_int_q'length-1), + din => ex3_np1_dec_int, + dout => ex4_np1_dec_int_q); +ex4_np1_ext_int_latch : tri_rlmreg_p + generic map (width => ex4_np1_ext_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_np1_ext_int_offset to ex4_np1_ext_int_offset + ex4_np1_ext_int_q'length-1), + scout => sov(ex4_np1_ext_int_offset to ex4_np1_ext_int_offset + ex4_np1_ext_int_q'length-1), + din => ex3_np1_ext_int, + dout => ex4_np1_ext_int_q); +ex4_np1_ext_mchk_mcint_latch : tri_rlmreg_p + generic map (width => ex4_np1_ext_mchk_mcint_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_np1_ext_mchk_mcint_offset to ex4_np1_ext_mchk_mcint_offset + ex4_np1_ext_mchk_mcint_q'length-1), + scout => sov(ex4_np1_ext_mchk_mcint_offset to ex4_np1_ext_mchk_mcint_offset + ex4_np1_ext_mchk_mcint_q'length-1), + din => ex3_np1_ext_mchk_mcint, + dout => ex4_np1_ext_mchk_mcint_q); +ex4_np1_fit_int_latch : tri_rlmreg_p + generic map (width => ex4_np1_fit_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_np1_fit_int_offset to ex4_np1_fit_int_offset + ex4_np1_fit_int_q'length-1), + scout => sov(ex4_np1_fit_int_offset to ex4_np1_fit_int_offset + ex4_np1_fit_int_q'length-1), + din => ex3_np1_fit_int, + dout => ex4_np1_fit_int_q); +ex4_np1_flush_latch : tri_rlmreg_p + generic map (width => ex4_np1_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_np1_flush_offset to ex4_np1_flush_offset + ex4_np1_flush_q'length-1), + scout => sov(ex4_np1_flush_offset to ex4_np1_flush_offset + ex4_np1_flush_q'length-1), + din => ex3_np1_flush, + dout => ex4_np1_flush_q); +ex4_np1_gcdbell_cint_latch : tri_rlmreg_p + generic map (width => ex4_np1_gcdbell_cint_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_np1_gcdbell_cint_offset to ex4_np1_gcdbell_cint_offset + ex4_np1_gcdbell_cint_q'length-1), + scout => sov(ex4_np1_gcdbell_cint_offset to ex4_np1_gcdbell_cint_offset + ex4_np1_gcdbell_cint_q'length-1), + din => ex3_np1_gcdbell_cint, + dout => ex4_np1_gcdbell_cint_q); +ex4_np1_gdbell_int_latch : tri_rlmreg_p + generic map (width => ex4_np1_gdbell_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_np1_gdbell_int_offset to ex4_np1_gdbell_int_offset + ex4_np1_gdbell_int_q'length-1), + scout => sov(ex4_np1_gdbell_int_offset to ex4_np1_gdbell_int_offset + ex4_np1_gdbell_int_q'length-1), + din => ex3_np1_gdbell_int, + dout => ex4_np1_gdbell_int_q); +ex4_np1_gmcdbell_cint_latch : tri_rlmreg_p + generic map (width => ex4_np1_gmcdbell_cint_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_np1_gmcdbell_cint_offset to ex4_np1_gmcdbell_cint_offset + ex4_np1_gmcdbell_cint_q'length-1), + scout => sov(ex4_np1_gmcdbell_cint_offset to ex4_np1_gmcdbell_cint_offset + ex4_np1_gmcdbell_cint_q'length-1), + din => ex3_np1_gmcdbell_cint, + dout => ex4_np1_gmcdbell_cint_q); +ex4_np1_ide_dbg_cint_latch : tri_rlmreg_p + generic map (width => ex4_np1_ide_dbg_cint_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_np1_ide_dbg_cint_offset to ex4_np1_ide_dbg_cint_offset + ex4_np1_ide_dbg_cint_q'length-1), + scout => sov(ex4_np1_ide_dbg_cint_offset to ex4_np1_ide_dbg_cint_offset + ex4_np1_ide_dbg_cint_q'length-1), + din => ex3_np1_ide_dbg_cint, + dout => ex4_np1_ide_dbg_cint_q); +ex4_np1_instr_int_latch : tri_rlmreg_p + generic map (width => ex4_np1_instr_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_np1_instr_int_offset to ex4_np1_instr_int_offset + ex4_np1_instr_int_q'length-1), + scout => sov(ex4_np1_instr_int_offset to ex4_np1_instr_int_offset + ex4_np1_instr_int_q'length-1), + din => ex3_np1_instr_int, + dout => ex4_np1_instr_int_q); +ex4_np1_perf_int_latch : tri_rlmreg_p + generic map (width => ex4_np1_perf_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_np1_perf_int_offset to ex4_np1_perf_int_offset + ex4_np1_perf_int_q'length-1), + scout => sov(ex4_np1_perf_int_offset to ex4_np1_perf_int_offset + ex4_np1_perf_int_q'length-1), + din => ex3_np1_perf_int, + dout => ex4_np1_perf_int_q); +ex4_np1_ptr_prog_int_latch : tri_rlmreg_p + generic map (width => ex4_np1_ptr_prog_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_np1_ptr_prog_int_offset to ex4_np1_ptr_prog_int_offset + ex4_np1_ptr_prog_int_q'length-1), + scout => sov(ex4_np1_ptr_prog_int_offset to ex4_np1_ptr_prog_int_offset + ex4_np1_ptr_prog_int_q'length-1), + din => ex3_np1_ptr_prog_int, + dout => ex4_np1_ptr_prog_int_q); +ex4_np1_rfi_latch : tri_rlmreg_p + generic map (width => ex4_np1_rfi_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_np1_rfi_offset to ex4_np1_rfi_offset + ex4_np1_rfi_q'length-1), + scout => sov(ex4_np1_rfi_offset to ex4_np1_rfi_offset + ex4_np1_rfi_q'length-1), + din => ex3_np1_rfi, + dout => ex4_np1_rfi_q); +ex4_np1_run_ctl_flush_latch : tri_rlmreg_p + generic map (width => ex4_np1_run_ctl_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_np1_run_ctl_flush_offset to ex4_np1_run_ctl_flush_offset + ex4_np1_run_ctl_flush_q'length-1), + scout => sov(ex4_np1_run_ctl_flush_offset to ex4_np1_run_ctl_flush_offset + ex4_np1_run_ctl_flush_q'length-1), + din => ex3_np1_run_ctl_flush, + dout => ex4_np1_run_ctl_flush_q); +ex4_np1_sc_int_latch : tri_rlmreg_p + generic map (width => ex4_np1_sc_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_np1_sc_int_offset to ex4_np1_sc_int_offset + ex4_np1_sc_int_q'length-1), + scout => sov(ex4_np1_sc_int_offset to ex4_np1_sc_int_offset + ex4_np1_sc_int_q'length-1), + din => ex3_np1_sc_int, + dout => ex4_np1_sc_int_q); +ex4_np1_ude_dbg_cint_latch : tri_rlmreg_p + generic map (width => ex4_np1_ude_dbg_cint_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_np1_ude_dbg_cint_offset to ex4_np1_ude_dbg_cint_offset + ex4_np1_ude_dbg_cint_q'length-1), + scout => sov(ex4_np1_ude_dbg_cint_offset to ex4_np1_ude_dbg_cint_offset + ex4_np1_ude_dbg_cint_q'length-1), + din => ex3_np1_ude_dbg_cint, + dout => ex4_np1_ude_dbg_cint_q); +ex4_np1_ude_dbg_event_latch : tri_rlmreg_p + generic map (width => ex4_np1_ude_dbg_event_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_np1_ude_dbg_event_offset to ex4_np1_ude_dbg_event_offset + ex4_np1_ude_dbg_event_q'length-1), + scout => sov(ex4_np1_ude_dbg_event_offset to ex4_np1_ude_dbg_event_offset + ex4_np1_ude_dbg_event_q'length-1), + din => ex3_np1_ude_dbg_event, + dout => ex4_np1_ude_dbg_event_q); +ex4_np1_udec_int_latch : tri_rlmreg_p + generic map (width => ex4_np1_udec_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_np1_udec_int_offset to ex4_np1_udec_int_offset + ex4_np1_udec_int_q'length-1), + scout => sov(ex4_np1_udec_int_offset to ex4_np1_udec_int_offset + ex4_np1_udec_int_q'length-1), + din => ex3_np1_udec_int, + dout => ex4_np1_udec_int_q); +ex4_np1_wdog_cint_latch : tri_rlmreg_p + generic map (width => ex4_np1_wdog_cint_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_np1_wdog_cint_offset to ex4_np1_wdog_cint_offset + ex4_np1_wdog_cint_q'length-1), + scout => sov(ex4_np1_wdog_cint_offset to ex4_np1_wdog_cint_offset + ex4_np1_wdog_cint_q'length-1), + din => ex3_np1_wdog_cint, + dout => ex4_np1_wdog_cint_q); +ex4_np1_fu_flush_latch : tri_rlmreg_p + generic map (width => ex4_np1_fu_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1 ) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_np1_fu_flush_offset to ex4_np1_fu_flush_offset + ex4_np1_fu_flush_q'length-1), + scout => sov(ex4_np1_fu_flush_offset to ex4_np1_fu_flush_offset + ex4_np1_fu_flush_q'length-1), + din => ex3_np1_fu_flush, + dout => ex4_np1_fu_flush_q); +ex4_n_ieratsx_par_mchk_mcint_latch : tri_rlmreg_p + generic map (width => ex4_n_ieratsx_par_mchk_mcint_q'length, init => 0, expand_type => expand_type, needs_sreset => 1 ) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_ieratsx_par_mchk_mcint_offset to ex4_n_ieratsx_par_mchk_mcint_offset + ex4_n_ieratsx_par_mchk_mcint_q'length-1), + scout => sov(ex4_n_ieratsx_par_mchk_mcint_offset to ex4_n_ieratsx_par_mchk_mcint_offset + ex4_n_ieratsx_par_mchk_mcint_q'length-1), + din => ex3_n_ieratsx_par_mchk_mcint, + dout => ex4_n_ieratsx_par_mchk_mcint_q); +ex4_n_tlbmh_mchk_mcint_latch : tri_rlmreg_p + generic map (width => ex4_n_tlbmh_mchk_mcint_q'length, init => 0, expand_type => expand_type, needs_sreset => 1 ) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_tlbmh_mchk_mcint_offset to ex4_n_tlbmh_mchk_mcint_offset + ex4_n_tlbmh_mchk_mcint_q'length-1), + scout => sov(ex4_n_tlbmh_mchk_mcint_offset to ex4_n_tlbmh_mchk_mcint_offset + ex4_n_tlbmh_mchk_mcint_q'length-1), + din => ex3_n_tlbmh_mchk_mcint , + dout => ex4_n_tlbmh_mchk_mcint_q); +ex4_n_sprg_ue_flush_latch : tri_rlmreg_p + generic map (width => ex4_n_sprg_ue_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_sprg_ue_flush_offset to ex4_n_sprg_ue_flush_offset + ex4_n_sprg_ue_flush_q'length-1), + scout => sov(ex4_n_sprg_ue_flush_offset to ex4_n_sprg_ue_flush_offset + ex4_n_sprg_ue_flush_q'length-1), + din => ex3_n_sprg_ue_flush , + dout => ex4_n_sprg_ue_flush_q); +ex4_n_rwaccess_dstor_int_latch : tri_rlmreg_p + generic map (width => ex4_n_rwaccess_dstor_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_rwaccess_dstor_int_offset to ex4_n_rwaccess_dstor_int_offset + ex4_n_rwaccess_dstor_int_q'length-1), + scout => sov(ex4_n_rwaccess_dstor_int_offset to ex4_n_rwaccess_dstor_int_offset + ex4_n_rwaccess_dstor_int_q'length-1), + din => ex3_n_rwaccess_dstor_int, + dout => ex4_n_rwaccess_dstor_int_q); +ex4_n_exaccess_istor_int_latch : tri_rlmreg_p + generic map (width => ex4_n_exaccess_istor_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_exaccess_istor_int_offset to ex4_n_exaccess_istor_int_offset + ex4_n_exaccess_istor_int_q'length-1), + scout => sov(ex4_n_exaccess_istor_int_offset to ex4_n_exaccess_istor_int_offset + ex4_n_exaccess_istor_int_q'length-1), + din => ex3_n_exaccess_istor_int, + dout => ex4_n_exaccess_istor_int_q); +ex4_sc_lev_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_sc_lev_offset), + scout => sov(ex4_sc_lev_offset), + din => ex3_sc_lev_q , + dout => ex4_sc_lev_q); +ex4_siar_sel_latch : tri_rlmreg_p + generic map (width => ex4_siar_sel_q'length, init => 1, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_siar_sel_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_siar_sel_offset to ex4_siar_sel_offset + ex4_siar_sel_q'length-1), + scout => sov(ex4_siar_sel_offset to ex4_siar_sel_offset + ex4_siar_sel_q'length-1), + din => ex4_siar_sel_d, + dout => ex4_siar_sel_q); +ex4_step_latch : tri_rlmreg_p + generic map (width => ex4_step_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_step_offset to ex4_step_offset + ex4_step_q'length-1), + scout => sov(ex4_step_offset to ex4_step_offset + ex4_step_q'length-1), + din => ex4_step_d, + dout => ex4_step_q); +ex4_taken_bclr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_taken_bclr_offset), + scout => sov(ex4_taken_bclr_offset), + din => ex3_taken_bclr_q , + dout => ex4_taken_bclr_q); +ex4_tlb_inelig_latch : tri_rlmreg_p + generic map (width => ex4_tlb_inelig_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_tlb_inelig_offset to ex4_tlb_inelig_offset + ex4_tlb_inelig_q'length-1), + scout => sov(ex4_tlb_inelig_offset to ex4_tlb_inelig_offset + ex4_tlb_inelig_q'length-1), + din => ex3_tlb_inelig_q , + dout => ex4_tlb_inelig_q); +ex4_ucode_val_latch : tri_rlmreg_p + generic map (width => ex4_ucode_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_ucode_val_offset to ex4_ucode_val_offset + ex4_ucode_val_q'length-1), + scout => sov(ex4_ucode_val_offset to ex4_ucode_val_offset + ex4_ucode_val_q'length-1), + din => ex3_ucode_val , + dout => ex4_ucode_val_q); +ex4_xu_is_ucode_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_xu_is_ucode_offset), + scout => sov(ex4_xu_is_ucode_offset), + din => ex3_xu_is_ucode_q , + dout => ex4_xu_is_ucode_q); +ex4_xu_val_latch : tri_rlmreg_p + generic map (width => ex4_xu_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_xu_val_offset to ex4_xu_val_offset + ex4_xu_val_q'length-1), + scout => sov(ex4_xu_val_offset to ex4_xu_val_offset + ex4_xu_val_q'length-1), + din => ex3_xu_val , + dout => ex4_xu_val_q); +ex4_cia_act_latch : tri_rlmreg_p + generic map (width => ex4_cia_act_q'length, init => 0, expand_type => expand_type, needs_sreset => 1 ) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_cia_act_offset to ex4_cia_act_offset + ex4_cia_act_q'length-1), + scout => sov(ex4_cia_act_offset to ex4_cia_act_offset + ex4_cia_act_q'length-1), + din => ex3_cia_act, + dout => ex4_cia_act_q); +ex4_n_async_dacr_dbg_cint_latch : tri_rlmreg_p + generic map (width => ex4_n_async_dacr_dbg_cint_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_async_dacr_dbg_cint_offset to ex4_n_async_dacr_dbg_cint_offset + ex4_n_async_dacr_dbg_cint_q'length-1), + scout => sov(ex4_n_async_dacr_dbg_cint_offset to ex4_n_async_dacr_dbg_cint_offset + ex4_n_async_dacr_dbg_cint_q'length-1), + din => ex3_n_async_dacr_dbg_cint, + dout => ex4_n_async_dacr_dbg_cint_q); +ex4_dac1r_cmpr_async_latch : tri_rlmreg_p + generic map (width => ex4_dac1r_cmpr_async_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_dac1r_cmpr_async_offset to ex4_dac1r_cmpr_async_offset + ex4_dac1r_cmpr_async_q'length-1), + scout => sov(ex4_dac1r_cmpr_async_offset to ex4_dac1r_cmpr_async_offset + ex4_dac1r_cmpr_async_q'length-1), + din => ex4_dac1r_cmpr_async_d, + dout => ex4_dac1r_cmpr_async_q); +ex4_dac2r_cmpr_async_latch : tri_rlmreg_p + generic map (width => ex4_dac2r_cmpr_async_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_dac2r_cmpr_async_offset to ex4_dac2r_cmpr_async_offset + ex4_dac2r_cmpr_async_q'length-1), + scout => sov(ex4_dac2r_cmpr_async_offset to ex4_dac2r_cmpr_async_offset + ex4_dac2r_cmpr_async_q'length-1), + din => ex4_dac2r_cmpr_async_d, + dout => ex4_dac2r_cmpr_async_q); +ex4_thread_stop_latch : tri_rlmreg_p + generic map (width => ex4_thread_stop_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_thread_stop_offset to ex4_thread_stop_offset + ex4_thread_stop_q'length-1), + scout => sov(ex4_thread_stop_offset to ex4_thread_stop_offset + ex4_thread_stop_q'length-1), + din => ex3_thread_stop, + dout => ex4_thread_stop_q); +ex5_icmp_event_on_int_ok_latch : tri_rlmreg_p + generic map (width => ex5_icmp_event_on_int_ok_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_icmp_event_on_int_ok_offset to ex5_icmp_event_on_int_ok_offset + ex5_icmp_event_on_int_ok_q'length-1), + scout => sov(ex5_icmp_event_on_int_ok_offset to ex5_icmp_event_on_int_ok_offset + ex5_icmp_event_on_int_ok_q'length-1), + din => ex4_icmp_event_on_int_ok, + dout => ex5_icmp_event_on_int_ok_q); +ex5_any_val_latch : tri_rlmreg_p + generic map (width => ex5_any_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_any_val_offset to ex5_any_val_offset + ex5_any_val_q'length-1), + scout => sov(ex5_any_val_offset to ex5_any_val_offset + ex5_any_val_q'length-1), + din => ex4_any_val , + dout => ex5_any_val_q); +ex5_attn_flush_latch : tri_rlmreg_p + generic map (width => ex5_attn_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_attn_flush_offset to ex5_attn_flush_offset + ex5_attn_flush_q'length-1), + scout => sov(ex5_attn_flush_offset to ex5_attn_flush_offset + ex5_attn_flush_q'length-1), + din => ex4_attn_flush, + dout => ex5_attn_flush_q); +ex5_axu_trap_pie_latch : tri_rlmreg_p + generic map (width => ex5_axu_trap_pie_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_axu_trap_pie_offset to ex5_axu_trap_pie_offset + ex5_axu_trap_pie_q'length-1), + scout => sov(ex5_axu_trap_pie_offset to ex5_axu_trap_pie_offset + ex5_axu_trap_pie_q'length-1), + din => ex5_axu_trap_pie_d, + dout => ex5_axu_trap_pie_q); +ex5_br_taken_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_br_taken_offset), + scout => sov(ex5_br_taken_offset), + din => ex4_br_taken_q , + dout => ex5_br_taken_q); +ex5_cdbell_taken_latch : tri_rlmreg_p + generic map (width => ex5_cdbell_taken_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_cdbell_taken_offset to ex5_cdbell_taken_offset + ex5_cdbell_taken_q'length-1), + scout => sov(ex5_cdbell_taken_offset to ex5_cdbell_taken_offset + ex5_cdbell_taken_q'length-1), + din => ex5_cdbell_taken_d, + dout => ex5_cdbell_taken_q); +ex5_check_bclr_latch : tri_rlmreg_p + generic map (width => ex5_check_bclr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_check_bclr_offset to ex5_check_bclr_offset + ex5_check_bclr_q'length-1), + scout => sov(ex5_check_bclr_offset to ex5_check_bclr_offset + ex5_check_bclr_q'length-1), + din => ex5_check_bclr_d, + dout => ex5_check_bclr_q); +ex5_cia_p1_latch : tri_rlmreg_p + generic map (width => ex5_cia_p1_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_cia_p1_offset to ex5_cia_p1_offset + ex5_cia_p1_q'length-1), + scout => sov(ex5_cia_p1_offset to ex5_cia_p1_offset + ex5_cia_p1_q'length-1), + din => ex5_cia_p1_d, + dout => ex5_cia_p1_q); +ex5_dbell_taken_latch : tri_rlmreg_p + generic map (width => ex5_dbell_taken_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_dbell_taken_offset to ex5_dbell_taken_offset + ex5_dbell_taken_q'length-1), + scout => sov(ex5_dbell_taken_offset to ex5_dbell_taken_offset + ex5_dbell_taken_q'length-1), + din => ex5_dbell_taken_d, + dout => ex5_dbell_taken_q); +ex5_dbsr_update_latch : tri_rlmreg_p + generic map (width => ex5_dbsr_update_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_dbsr_update_offset to ex5_dbsr_update_offset + ex5_dbsr_update_q'length-1), + scout => sov(ex5_dbsr_update_offset to ex5_dbsr_update_offset + ex5_dbsr_update_q'length-1), + din => ex4_dbsr_update, + dout => ex5_dbsr_update_q); +ex5_dear_update_saved_latch : tri_rlmreg_p + generic map (width => ex5_dear_update_saved_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_dear_update_saved_offset to ex5_dear_update_saved_offset + ex5_dear_update_saved_q'length-1), + scout => sov(ex5_dear_update_saved_offset to ex5_dear_update_saved_offset + ex5_dear_update_saved_q'length-1), + din => ex5_dear_update_saved_d, + dout => ex5_dear_update_saved_q); +ex5_deratre_par_err_latch : tri_rlmreg_p + generic map (width => ex5_deratre_par_err_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_deratre_par_err_offset to ex5_deratre_par_err_offset + ex5_deratre_par_err_q'length-1), + scout => sov(ex5_deratre_par_err_offset to ex5_deratre_par_err_offset + ex5_deratre_par_err_q'length-1), + din => lsu_xu_ex4_derat_par_err , + dout => ex5_deratre_par_err_q); +ex5_div_set_barr_latch : tri_rlmreg_p + generic map (width => ex5_div_set_barr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_div_set_barr_offset to ex5_div_set_barr_offset + ex5_div_set_barr_q'length-1), + scout => sov(ex5_div_set_barr_offset to ex5_div_set_barr_offset + ex5_div_set_barr_q'length-1), + din => ex5_div_set_barr_d, + dout => ex5_div_set_barr_q); +ex5_dsigs_latch : tri_rlmreg_p + generic map (width => ex5_dsigs_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_dsigs_offset to ex5_dsigs_offset + ex5_dsigs_q'length-1), + scout => sov(ex5_dsigs_offset to ex5_dsigs_offset + ex5_dsigs_q'length-1), + din => ex5_dsigs_d, + dout => ex5_dsigs_q); +ex5_dtlbgs_latch : tri_rlmreg_p + generic map (width => ex5_dtlbgs_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_dtlbgs_offset to ex5_dtlbgs_offset + ex5_dtlbgs_q'length-1), + scout => sov(ex5_dtlbgs_offset to ex5_dtlbgs_offset + ex5_dtlbgs_q'length-1), + din => ex5_dtlbgs_d, + dout => ex5_dtlbgs_q); +ex5_err_nia_miscmpr_latch : tri_rlmreg_p + generic map (width => ex5_err_nia_miscmpr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_err_nia_miscmpr_offset to ex5_err_nia_miscmpr_offset + ex5_err_nia_miscmpr_q'length-1), + scout => sov(ex5_err_nia_miscmpr_offset to ex5_err_nia_miscmpr_offset + ex5_err_nia_miscmpr_q'length-1), + din => ex5_err_nia_miscmpr_d, + dout => ex5_err_nia_miscmpr_q); +ex5_ext_dbg_err_latch : tri_rlmreg_p + generic map (width => ex5_ext_dbg_err_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_ext_dbg_err_offset to ex5_ext_dbg_err_offset + ex5_ext_dbg_err_q'length-1), + scout => sov(ex5_ext_dbg_err_offset to ex5_ext_dbg_err_offset + ex5_ext_dbg_err_q'length-1), + din => ex5_ext_dbg_err_d, + dout => ex5_ext_dbg_err_q); +ex5_ext_dbg_ext_latch : tri_rlmreg_p + generic map (width => ex5_ext_dbg_ext_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_ext_dbg_ext_offset to ex5_ext_dbg_ext_offset + ex5_ext_dbg_ext_q'length-1), + scout => sov(ex5_ext_dbg_ext_offset to ex5_ext_dbg_ext_offset + ex5_ext_dbg_ext_q'length-1), + din => ex5_ext_dbg_ext_d, + dout => ex5_ext_dbg_ext_q); +ex5_extgs_latch : tri_rlmreg_p + generic map (width => ex5_extgs_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_extgs_offset to ex5_extgs_offset + ex5_extgs_q'length-1), + scout => sov(ex5_extgs_offset to ex5_extgs_offset + ex5_extgs_q'length-1), + din => ex5_extgs_d, + dout => ex5_extgs_q); +ex5_flush_latch : tri_rlmreg_p + generic map (width => ex5_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_flush_offset to ex5_flush_offset + ex5_flush_q'length-1), + scout => sov(ex5_flush_offset to ex5_flush_offset + ex5_flush_q'length-1), + din => ex4_flush , + dout => ex5_flush_q); +ex5_force_gsrr_latch : tri_rlmreg_p + generic map (width => ex5_force_gsrr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_force_gsrr_offset to ex5_force_gsrr_offset + ex5_force_gsrr_q'length-1), + scout => sov(ex5_force_gsrr_offset to ex5_force_gsrr_offset + ex5_force_gsrr_q'length-1), + din => ex5_force_gsrr_d, + dout => ex5_force_gsrr_q); +ex5_gcdbell_taken_latch : tri_rlmreg_p + generic map (width => ex5_gcdbell_taken_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_gcdbell_taken_offset to ex5_gcdbell_taken_offset + ex5_gcdbell_taken_q'length-1), + scout => sov(ex5_gcdbell_taken_offset to ex5_gcdbell_taken_offset + ex5_gcdbell_taken_q'length-1), + din => ex5_gcdbell_taken_d, + dout => ex5_gcdbell_taken_q); +ex5_gdbell_taken_latch : tri_rlmreg_p + generic map (width => ex5_gdbell_taken_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_gdbell_taken_offset to ex5_gdbell_taken_offset + ex5_gdbell_taken_q'length-1), + scout => sov(ex5_gdbell_taken_offset to ex5_gdbell_taken_offset + ex5_gdbell_taken_q'length-1), + din => ex5_gdbell_taken_d, + dout => ex5_gdbell_taken_q); +ex5_gmcdbell_taken_latch : tri_rlmreg_p + generic map (width => ex5_gmcdbell_taken_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_gmcdbell_taken_offset to ex5_gmcdbell_taken_offset + ex5_gmcdbell_taken_q'length-1), + scout => sov(ex5_gmcdbell_taken_offset to ex5_gmcdbell_taken_offset + ex5_gmcdbell_taken_q'length-1), + din => ex5_gmcdbell_taken_d, + dout => ex5_gmcdbell_taken_q); +ex5_ieratre_par_err_latch : tri_rlmreg_p + generic map (width => ex5_ieratre_par_err_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_ieratre_par_err_offset to ex5_ieratre_par_err_offset + ex5_ieratre_par_err_q'length-1), + scout => sov(ex5_ieratre_par_err_offset to ex5_ieratre_par_err_offset + ex5_ieratre_par_err_q'length-1), + din => iu_xu_ierat_ex4_par_err , + dout => ex5_ieratre_par_err_q); +ex5_in_ucode_latch : tri_rlmreg_p + generic map (width => ex5_in_ucode_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_in_ucode_offset to ex5_in_ucode_offset + ex5_in_ucode_q'length-1), + scout => sov(ex5_in_ucode_offset to ex5_in_ucode_offset + ex5_in_ucode_q'length-1), + din => ex5_in_ucode_d, + dout => ex5_in_ucode_q); +ex5_instr_cpl_latch : tri_rlmreg_p + generic map (width => ex5_instr_cpl_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_instr_cpl_offset to ex5_instr_cpl_offset + ex5_instr_cpl_q'length-1), + scout => sov(ex5_instr_cpl_offset to ex5_instr_cpl_offset + ex5_instr_cpl_q'length-1), + din => ex4_instr_cpl, + dout => ex5_instr_cpl_q); +ex5_is_any_rfi_latch : tri_rlmreg_p + generic map (width => ex5_is_any_rfi_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_is_any_rfi_offset to ex5_is_any_rfi_offset + ex5_is_any_rfi_q'length-1), + scout => sov(ex5_is_any_rfi_offset to ex5_is_any_rfi_offset + ex5_is_any_rfi_q'length-1), + din => ex4_is_any_rfi, + dout => ex5_is_any_rfi_q); +ex5_is_attn_latch : tri_rlmreg_p + generic map (width => ex5_is_attn_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_is_attn_offset to ex5_is_attn_offset + ex5_is_attn_q'length-1), + scout => sov(ex5_is_attn_offset to ex5_is_attn_offset + ex5_is_attn_q'length-1), + din => ex5_is_attn_d, + dout => ex5_is_attn_q); +ex5_is_crit_int_latch : tri_rlmreg_p + generic map (width => ex5_is_crit_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_is_crit_int_offset to ex5_is_crit_int_offset + ex5_is_crit_int_q'length-1), + scout => sov(ex5_is_crit_int_offset to ex5_is_crit_int_offset + ex5_is_crit_int_q'length-1), + din => ex4_is_crit_int , + dout => ex5_is_crit_int_q); +ex5_is_mchk_int_latch : tri_rlmreg_p + generic map (width => ex5_is_mchk_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_is_mchk_int_offset to ex5_is_mchk_int_offset + ex5_is_mchk_int_q'length-1), + scout => sov(ex5_is_mchk_int_offset to ex5_is_mchk_int_offset + ex5_is_mchk_int_q'length-1), + din => ex4_is_mchk_int , + dout => ex5_is_mchk_int_q); +ex5_is_mtmsr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_is_mtmsr_offset), + scout => sov(ex5_is_mtmsr_offset), + din => ex4_is_mtmsr_q , + dout => ex5_is_mtmsr_q); +ex5_is_isync_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_is_isync_offset), + scout => sov(ex5_is_isync_offset), + din => ex4_is_isync_q , + dout => ex5_is_isync_q); +ex5_is_tlbwe_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_is_tlbwe_offset), + scout => sov(ex5_is_tlbwe_offset), + din => ex4_is_tlbwe_q , + dout => ex5_is_tlbwe_q); +ex5_isigs_latch : tri_rlmreg_p + generic map (width => ex5_isigs_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_isigs_offset to ex5_isigs_offset + ex5_isigs_q'length-1), + scout => sov(ex5_isigs_offset to ex5_isigs_offset + ex5_isigs_q'length-1), + din => ex5_isigs_d, + dout => ex5_isigs_q); +ex5_itlbgs_latch : tri_rlmreg_p + generic map (width => ex5_itlbgs_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_itlbgs_offset to ex5_itlbgs_offset + ex5_itlbgs_q'length-1), + scout => sov(ex5_itlbgs_offset to ex5_itlbgs_offset + ex5_itlbgs_q'length-1), + din => ex5_itlbgs_d, + dout => ex5_itlbgs_q); +ex5_lsu_set_barr_latch : tri_rlmreg_p + generic map (width => ex5_lsu_set_barr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_lsu_set_barr_offset to ex5_lsu_set_barr_offset + ex5_lsu_set_barr_q'length-1), + scout => sov(ex5_lsu_set_barr_offset to ex5_lsu_set_barr_offset + ex5_lsu_set_barr_q'length-1), + din => ex5_lsu_set_barr_d, + dout => ex5_lsu_set_barr_q); +ex5_mem_attr_val_latch : tri_rlmreg_p + generic map (width => ex5_mem_attr_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_mem_attr_val_offset to ex5_mem_attr_val_offset + ex5_mem_attr_val_q'length-1), + scout => sov(ex5_mem_attr_val_offset to ex5_mem_attr_val_offset + ex5_mem_attr_val_q'length-1), + din => ex4_mem_attr_val, + dout => ex5_mem_attr_val_q); +ex5_mmu_hold_val_latch : tri_rlmreg_p + generic map (width => ex5_mmu_hold_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_mmu_hold_val_offset to ex5_mmu_hold_val_offset + ex5_mmu_hold_val_q'length-1), + scout => sov(ex5_mmu_hold_val_offset to ex5_mmu_hold_val_offset + ex5_mmu_hold_val_q'length-1), + din => ex4_mmu_hold_val_q, + dout => ex5_mmu_hold_val_q); +ex5_n_dmiss_flush_latch : tri_rlmreg_p + generic map (width => ex5_n_dmiss_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_n_dmiss_flush_offset to ex5_n_dmiss_flush_offset + ex5_n_dmiss_flush_q'length-1), + scout => sov(ex5_n_dmiss_flush_offset to ex5_n_dmiss_flush_offset + ex5_n_dmiss_flush_q'length-1), + din => ex4_n_dmiss_flush, + dout => ex5_n_dmiss_flush_q); +ex5_n_ext_dbg_stopc_flush_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_n_ext_dbg_stopc_flush_offset), + scout => sov(ex5_n_ext_dbg_stopc_flush_offset), + din => ex5_n_ext_dbg_stopc_flush_d, + dout => ex5_n_ext_dbg_stopc_flush_q); +ex5_n_ext_dbg_stopt_flush_latch : tri_rlmreg_p + generic map (width => ex5_n_ext_dbg_stopt_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_n_ext_dbg_stopt_flush_offset to ex5_n_ext_dbg_stopt_flush_offset + ex5_n_ext_dbg_stopt_flush_q'length-1), + scout => sov(ex5_n_ext_dbg_stopt_flush_offset to ex5_n_ext_dbg_stopt_flush_offset + ex5_n_ext_dbg_stopt_flush_q'length-1), + din => ex5_n_ext_dbg_stopt_flush_d, + dout => ex5_n_ext_dbg_stopt_flush_q); +ex5_n_imiss_flush_latch : tri_rlmreg_p + generic map (width => ex5_n_imiss_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_n_imiss_flush_offset to ex5_n_imiss_flush_offset + ex5_n_imiss_flush_q'length-1), + scout => sov(ex5_n_imiss_flush_offset to ex5_n_imiss_flush_offset + ex5_n_imiss_flush_q'length-1), + din => ex4_n_imiss_flush, + dout => ex5_n_imiss_flush_q); +ex5_n_ptemiss_dlrat_int_latch : tri_rlmreg_p + generic map (width => ex5_n_ptemiss_dlrat_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_n_ptemiss_dlrat_int_offset to ex5_n_ptemiss_dlrat_int_offset + ex5_n_ptemiss_dlrat_int_q'length-1), + scout => sov(ex5_n_ptemiss_dlrat_int_offset to ex5_n_ptemiss_dlrat_int_offset + ex5_n_ptemiss_dlrat_int_q'length-1), + din => ex4_n_ptemiss_dlrat_int_q , + dout => ex5_n_ptemiss_dlrat_int_q); +ex5_np1_run_ctl_flush_latch : tri_rlmreg_p + generic map (width => ex5_np1_run_ctl_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_np1_run_ctl_flush_offset to ex5_np1_run_ctl_flush_offset + ex5_np1_run_ctl_flush_q'length-1), + scout => sov(ex5_np1_run_ctl_flush_offset to ex5_np1_run_ctl_flush_offset + ex5_np1_run_ctl_flush_q'length-1), + din => ex4_np1_run_ctl_flush, + dout => ex5_np1_run_ctl_flush_q); +ex5_dbsr_ide_latch : tri_rlmreg_p + generic map (width => ex5_dbsr_ide_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_dbsr_ide_offset to ex5_dbsr_ide_offset + ex5_dbsr_ide_q'length-1), + scout => sov(ex5_dbsr_ide_offset to ex5_dbsr_ide_offset + ex5_dbsr_ide_q'length-1), + din => ex5_dbsr_ide_d, + dout => ex5_dbsr_ide_q); +ex5_perf_dtlb_latch : tri_rlmreg_p + generic map (width => ex5_perf_dtlb_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_perf_dtlb_offset to ex5_perf_dtlb_offset + ex5_perf_dtlb_q'length-1), + scout => sov(ex5_perf_dtlb_offset to ex5_perf_dtlb_offset + ex5_perf_dtlb_q'length-1), + din => ex5_perf_dtlb_d, + dout => ex5_perf_dtlb_q); +ex5_perf_itlb_latch : tri_rlmreg_p + generic map (width => ex5_perf_itlb_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_perf_itlb_offset to ex5_perf_itlb_offset + ex5_perf_itlb_q'length-1), + scout => sov(ex5_perf_itlb_offset to ex5_perf_itlb_offset + ex5_perf_itlb_q'length-1), + din => ex5_perf_itlb_d, + dout => ex5_perf_itlb_q); +ex5_ram_done_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_ram_done_offset), + scout => sov(ex5_ram_done_offset), + din => ex5_ram_done_d, + dout => ex5_ram_done_q); +ex5_ram_issue_latch : tri_rlmreg_p + generic map (width => ex5_ram_issue_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_ram_issue_offset to ex5_ram_issue_offset + ex5_ram_issue_q'length-1), + scout => sov(ex5_ram_issue_offset to ex5_ram_issue_offset + ex5_ram_issue_q'length-1), + din => ex5_ram_issue_d, + dout => ex5_ram_issue_q); +ex5_rt_latch : tri_rlmreg_p + generic map (width => ex5_rt_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_rt_offset to ex5_rt_offset + ex5_rt_q'length-1), + scout => sov(ex5_rt_offset to ex5_rt_offset + ex5_rt_q'length-1), + din => mux_cpl_ex4_rt , + dout => ex5_rt_q); +ex5_sel_rt_latch : tri_rlmreg_p + generic map (width => ex5_sel_rt_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_sel_rt_offset to ex5_sel_rt_offset + ex5_sel_rt_q'length-1), + scout => sov(ex5_sel_rt_offset to ex5_sel_rt_offset + ex5_sel_rt_q'length-1), + din => ex5_sel_rt_d, + dout => ex5_sel_rt_q); +ex5_srr0_dec_latch : tri_rlmreg_p + generic map (width => ex5_srr0_dec_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_srr0_dec_offset to ex5_srr0_dec_offset + ex5_srr0_dec_q'length-1), + scout => sov(ex5_srr0_dec_offset to ex5_srr0_dec_offset + ex5_srr0_dec_q'length-1), + din => ex5_srr0_dec_d, + dout => ex5_srr0_dec_q); +ex5_tlb_inelig_latch : tri_rlmreg_p + generic map (width => ex5_tlb_inelig_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_tlb_inelig_offset to ex5_tlb_inelig_offset + ex5_tlb_inelig_q'length-1), + scout => sov(ex5_tlb_inelig_offset to ex5_tlb_inelig_offset + ex5_tlb_inelig_q'length-1), + din => ex4_tlb_inelig_q , + dout => ex5_tlb_inelig_q); +ex5_uc_cia_val_latch : tri_rlmreg_p + generic map (width => ex5_uc_cia_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_uc_cia_val_offset to ex5_uc_cia_val_offset + ex5_uc_cia_val_q'length-1), + scout => sov(ex5_uc_cia_val_offset to ex5_uc_cia_val_offset + ex5_uc_cia_val_q'length-1), + din => ex5_uc_cia_val_d, + dout => ex5_uc_cia_val_q); +ex5_xu_ifar_latch : tri_rlmreg_p + generic map (width => ex5_xu_ifar_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_xu_ifar_offset to ex5_xu_ifar_offset + ex5_xu_ifar_q'length-1), + scout => sov(ex5_xu_ifar_offset to ex5_xu_ifar_offset + ex5_xu_ifar_q'length-1), + din => ex5_xu_ifar_d, + dout => ex5_xu_ifar_q); +ex5_xu_val_latch : tri_rlmreg_p + generic map (width => ex5_xu_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_xu_val_offset to ex5_xu_val_offset + ex5_xu_val_q'length-1), + scout => sov(ex5_xu_val_offset to ex5_xu_val_offset + ex5_xu_val_q'length-1), + din => ex4_xu_val , + dout => ex5_xu_val_q); +ex5_n_flush_sprg_ue_flush_latch : tri_rlmreg_p + generic map (width => ex5_n_flush_sprg_ue_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_n_flush_sprg_ue_flush_offset to ex5_n_flush_sprg_ue_flush_offset + ex5_n_flush_sprg_ue_flush_q'length-1), + scout => sov(ex5_n_flush_sprg_ue_flush_offset to ex5_n_flush_sprg_ue_flush_offset + ex5_n_flush_sprg_ue_flush_q'length-1), + din => ex4_n_flush_sprg_ue_flush, + dout => ex5_n_flush_sprg_ue_flush_q); +ex5_mcsr_act_latch : tri_rlmreg_p + generic map (width => ex5_mcsr_act_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_mcsr_act_offset to ex5_mcsr_act_offset + ex5_mcsr_act_q'length-1), + scout => sov(ex5_mcsr_act_offset to ex5_mcsr_act_offset + ex5_mcsr_act_q'length-1), + din => ex4_mcsr_act , + dout => ex5_mcsr_act_q); +ex6_mcsr_act_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_mcsr_act_offset), + scout => sov(ex6_mcsr_act_offset), + din => ex6_mcsr_act_d , + dout => ex6_mcsr_act_q); +ex6_late_flush_latch : tri_regk + generic map (width => ex6_late_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex5_late_flush_q(0), + dout => ex6_late_flush_q); +ex6_mmu_hold_val_latch : tri_regk + generic map (width => ex6_mmu_hold_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex5_mmu_hold_val_q, + dout => ex6_mmu_hold_val_q); +ex6_ram_done_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_ram_done_offset), + scout => sov(ex6_ram_done_offset), + din => ex5_ram_done_q , + dout => ex6_ram_done_q); +ex6_ram_interrupt_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_ram_interrupt_offset), + scout => sov(ex6_ram_interrupt_offset), + din => ex6_ram_interrupt_d, + dout => ex6_ram_interrupt_q); +ex6_ram_issue_latch : tri_rlmreg_p + generic map (width => ex6_ram_issue_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_ram_issue_offset to ex6_ram_issue_offset + ex6_ram_issue_q'length-1), + scout => sov(ex6_ram_issue_offset to ex6_ram_issue_offset + ex6_ram_issue_q'length-1), + din => ex6_ram_issue_d, + dout => ex6_ram_issue_q); +ex7_ram_issue_latch : tri_rlmreg_p + generic map (width => ex7_ram_issue_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex7_ram_issue_offset to ex7_ram_issue_offset + ex7_ram_issue_q'length-1), + scout => sov(ex7_ram_issue_offset to ex7_ram_issue_offset + ex7_ram_issue_q'length-1), + din => ex6_ram_issue_q, + dout => ex7_ram_issue_q); +ex8_ram_issue_latch : tri_rlmreg_p + generic map (width => ex8_ram_issue_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex8_ram_issue_offset to ex8_ram_issue_offset + ex8_ram_issue_q'length-1), + scout => sov(ex8_ram_issue_offset to ex8_ram_issue_offset + ex8_ram_issue_q'length-1), + din => ex7_ram_issue_q, + dout => ex8_ram_issue_q); +ex6_set_barr_latch : tri_regk + generic map (width => ex6_set_barr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex6_set_barr_d, + dout => ex6_set_barr_q); +ex6_step_done_latch : tri_rlmreg_p + generic map (width => ex6_step_done_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_step_done_offset to ex6_step_done_offset + ex6_step_done_q'length-1), + scout => sov(ex6_step_done_offset to ex6_step_done_offset + ex6_step_done_q'length-1), + din => ex5_step_done, + dout => ex6_step_done_q); +ex6_xu_val_latch : tri_rlmreg_p + generic map (width => ex6_xu_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_xu_val_offset to ex6_xu_val_offset + ex6_xu_val_q'length-1), + scout => sov(ex6_xu_val_offset to ex6_xu_val_offset + ex6_xu_val_q'length-1), + din => ex5_xu_val_q , + dout => ex6_xu_val_q); +ex6_is_tlbwe_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex5_is_tlbwe_q , + dout(0) => ex6_is_tlbwe_q); +ex7_is_tlbwe_latch : tri_rlmreg_p + generic map (width => ex7_is_tlbwe_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex7_is_tlbwe_offset to ex7_is_tlbwe_offset + ex7_is_tlbwe_q'length-1), + scout => sov(ex7_is_tlbwe_offset to ex7_is_tlbwe_offset + ex7_is_tlbwe_q'length-1), + din => ex7_is_tlbwe_d, + dout => ex7_is_tlbwe_q); +ex8_is_tlbwe_latch : tri_rlmreg_p + generic map (width => ex8_is_tlbwe_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex8_is_tlbwe_offset to ex8_is_tlbwe_offset + ex8_is_tlbwe_q'length-1), + scout => sov(ex8_is_tlbwe_offset to ex8_is_tlbwe_offset + ex8_is_tlbwe_q'length-1), + din => ex7_is_tlbwe_q , + dout => ex8_is_tlbwe_q); +ccr2_ap_latch : tri_rlmreg_p + generic map (width => ccr2_ap_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ccr2_ap_offset to ccr2_ap_offset + ccr2_ap_q'length-1), + scout => sov(ccr2_ap_offset to ccr2_ap_offset + ccr2_ap_q'length-1), + din => spr_ccr2_ap , + dout => ccr2_ap_q); +cpl_quiesced_latch : tri_rlmreg_p + generic map (width => cpl_quiesced_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(cpl_quiesced_offset to cpl_quiesced_offset + cpl_quiesced_q'length-1), + scout => sov(cpl_quiesced_offset to cpl_quiesced_offset + cpl_quiesced_q'length-1), + din => cpl_quiesced_d, + dout => cpl_quiesced_q); +dbcr0_idm_latch : tri_rlmreg_p + generic map (width => dbcr0_idm_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dbcr0_idm_offset to dbcr0_idm_offset + dbcr0_idm_q'length-1), + scout => sov(dbcr0_idm_offset to dbcr0_idm_offset + dbcr0_idm_q'length-1), + din => spr_dbcr0_idm , + dout => dbcr0_idm_q); +dci_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dci_val_offset), + scout => sov(dci_val_offset), + din => dci_val_d, + dout => dci_val_q); +debug_event_en_latch : tri_rlmreg_p + generic map (width => debug_event_en_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(debug_event_en_offset to debug_event_en_offset + debug_event_en_q'length-1), + scout => sov(debug_event_en_offset to debug_event_en_offset + debug_event_en_q'length-1), + din => debug_event_en_d, + dout => debug_event_en_q); +derat_hold_present_latch : tri_rlmreg_p + generic map (width => derat_hold_present_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(derat_hold_present_offset to derat_hold_present_offset + derat_hold_present_q'length-1), + scout => sov(derat_hold_present_offset to derat_hold_present_offset + derat_hold_present_q'length-1), + din => derat_hold_present_d, + dout => derat_hold_present_q); +ext_dbg_act_err_latch : tri_rlmreg_p + generic map (width => ext_dbg_act_err_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ext_dbg_act_err_offset to ext_dbg_act_err_offset + ext_dbg_act_err_q'length-1), + scout => sov(ext_dbg_act_err_offset to ext_dbg_act_err_offset + ext_dbg_act_err_q'length-1), + din => ext_dbg_act_err_d, + dout => ext_dbg_act_err_q); +ext_dbg_act_ext_latch : tri_rlmreg_p + generic map (width => ext_dbg_act_ext_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ext_dbg_act_ext_offset to ext_dbg_act_ext_offset + ext_dbg_act_ext_q'length-1), + scout => sov(ext_dbg_act_ext_offset to ext_dbg_act_ext_offset + ext_dbg_act_ext_q'length-1), + din => ext_dbg_act_ext_d, + dout => ext_dbg_act_ext_q); +ext_dbg_stop_core_latch : tri_rlmreg_p + generic map (width => ext_dbg_stop_core_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ext_dbg_stop_core_offset to ext_dbg_stop_core_offset + ext_dbg_stop_core_q'length-1), + scout => sov(ext_dbg_stop_core_offset to ext_dbg_stop_core_offset + ext_dbg_stop_core_q'length-1), + din => ext_dbg_stop_core_d, + dout => ext_dbg_stop_core_q); +ext_dbg_stop_n_latch : tri_rlmreg_p + generic map (width => ext_dbg_stop_n_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ext_dbg_stop_n_offset to ext_dbg_stop_n_offset + ext_dbg_stop_n_q'length-1), + scout => sov(ext_dbg_stop_n_offset to ext_dbg_stop_n_offset + ext_dbg_stop_n_q'length-1), + din => ext_dbg_stop_n_d, + dout => ext_dbg_stop_n_q); +external_mchk_latch : tri_rlmreg_p + generic map (width => external_mchk_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(external_mchk_offset to external_mchk_offset + external_mchk_q'length-1), + scout => sov(external_mchk_offset to external_mchk_offset + external_mchk_q'length-1), + din => spr_cpl_external_mchk , + dout => external_mchk_q); +exx_multi_flush_latch : tri_rlmreg_p + generic map (width => exx_multi_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(exx_multi_flush_offset to exx_multi_flush_offset + exx_multi_flush_q'length-1), + scout => sov(exx_multi_flush_offset to exx_multi_flush_offset + exx_multi_flush_q'length-1), + din => exx_multi_flush_d, + dout => exx_multi_flush_q); +force_ude_latch : tri_rlmreg_p + generic map (width => force_ude_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(force_ude_offset to force_ude_offset + force_ude_q'length-1), + scout => sov(force_ude_offset to force_ude_offset + force_ude_q'length-1), + din => pc_xu_force_ude , + dout => force_ude_q); +fu_rf_seq_end_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(fu_rf_seq_end_offset), + scout => sov(fu_rf_seq_end_offset), + din => fu_xu_regfile_seq_end , + dout => fu_rf_seq_end_q); +fu_rfpe_ack_latch : tri_rlmreg_p + generic map (width => fu_rfpe_ack_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(fu_rfpe_ack_offset to fu_rfpe_ack_offset + fu_rfpe_ack_q'length-1), + scout => sov(fu_rfpe_ack_offset to fu_rfpe_ack_offset + fu_rfpe_ack_q'length-1), + din => fu_rfpe_ack_d, + dout => fu_rfpe_ack_q); +fu_rfpe_hold_present_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(fu_rfpe_hold_present_offset), + scout => sov(fu_rfpe_hold_present_offset), + din => fu_rfpe_hold_present_d, + dout => fu_rfpe_hold_present_q); +ici_hold_present_latch : tri_rlmreg_p + generic map (width => ici_hold_present_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ici_hold_present_offset to ici_hold_present_offset + ici_hold_present_q'length-1), + scout => sov(ici_hold_present_offset to ici_hold_present_offset + ici_hold_present_q'length-1), + din => ici_hold_present_d, + dout => ici_hold_present_q); +ici_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ici_val_offset), + scout => sov(ici_val_offset), + din => ici_val_d, + dout => ici_val_q); +ierat_hold_present_latch : tri_rlmreg_p + generic map (width => ierat_hold_present_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ierat_hold_present_offset to ierat_hold_present_offset + ierat_hold_present_q'length-1), + scout => sov(ierat_hold_present_offset to ierat_hold_present_offset + ierat_hold_present_q'length-1), + din => ierat_hold_present_d, + dout => ierat_hold_present_q); +mmu_eratmiss_done_latch : tri_rlmreg_p + generic map (width => mmu_eratmiss_done_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(mmu_eratmiss_done_offset to mmu_eratmiss_done_offset + mmu_eratmiss_done_q'length-1), + scout => sov(mmu_eratmiss_done_offset to mmu_eratmiss_done_offset + mmu_eratmiss_done_q'length-1), + din => mm_xu_eratmiss_done , + dout => mmu_eratmiss_done_q); +mmu_hold_present_latch : tri_rlmreg_p + generic map (width => mmu_hold_present_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(mmu_hold_present_offset to mmu_hold_present_offset + mmu_hold_present_q'length-1), + scout => sov(mmu_hold_present_offset to mmu_hold_present_offset + mmu_hold_present_q'length-1), + din => mmu_hold_present_d, + dout => mmu_hold_present_q); +mmu_hold_request_latch : tri_rlmreg_p + generic map (width => mmu_hold_request_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(mmu_hold_request_offset to mmu_hold_request_offset + mmu_hold_request_q'length-1), + scout => sov(mmu_hold_request_offset to mmu_hold_request_offset + mmu_hold_request_q'length-1), + din => mmu_hold_request_d, + dout => mmu_hold_request_q); +msr_cm_latch : tri_rlmreg_p + generic map (width => msr_cm_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_w_int_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(msr_cm_offset to msr_cm_offset + msr_cm_q'length-1), + scout => sov(msr_cm_offset to msr_cm_offset + msr_cm_q'length-1), + din => spr_msr_cm , + dout => msr_cm_q); +msr_de_latch : tri_rlmreg_p + generic map (width => msr_de_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_w_int_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(msr_de_offset to msr_de_offset + msr_de_q'length-1), + scout => sov(msr_de_offset to msr_de_offset + msr_de_q'length-1), + din => spr_msr_de , + dout => msr_de_q); +msr_fp_latch : tri_rlmreg_p + generic map (width => msr_fp_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_w_int_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(msr_fp_offset to msr_fp_offset + msr_fp_q'length-1), + scout => sov(msr_fp_offset to msr_fp_offset + msr_fp_q'length-1), + din => spr_msr_fp , + dout => msr_fp_q); +msr_gs_latch : tri_rlmreg_p + generic map (width => msr_gs_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_w_int_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(msr_gs_offset to msr_gs_offset + msr_gs_q'length-1), + scout => sov(msr_gs_offset to msr_gs_offset + msr_gs_q'length-1), + din => spr_msr_gs , + dout => msr_gs_q); +msr_me_latch : tri_rlmreg_p + generic map (width => msr_me_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_w_int_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(msr_me_offset to msr_me_offset + msr_me_q'length-1), + scout => sov(msr_me_offset to msr_me_offset + msr_me_q'length-1), + din => spr_msr_me , + dout => msr_me_q); +msr_pr_latch : tri_rlmreg_p + generic map (width => msr_pr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_w_int_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(msr_pr_offset to msr_pr_offset + msr_pr_q'length-1), + scout => sov(msr_pr_offset to msr_pr_offset + msr_pr_q'length-1), + din => spr_msr_pr , + dout => msr_pr_q); +msr_spv_latch : tri_rlmreg_p + generic map (width => msr_spv_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_w_int_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(msr_spv_offset to msr_spv_offset + msr_spv_q'length-1), + scout => sov(msr_spv_offset to msr_spv_offset + msr_spv_q'length-1), + din => spr_msr_spv , + dout => msr_spv_q); +msr_ucle_latch : tri_rlmreg_p + generic map (width => msr_ucle_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_w_int_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(msr_ucle_offset to msr_ucle_offset + msr_ucle_q'length-1), + scout => sov(msr_ucle_offset to msr_ucle_offset + msr_ucle_q'length-1), + din => spr_msr_ucle , + dout => msr_ucle_q); +msrp_uclep_latch : tri_rlmreg_p + generic map (width => msrp_uclep_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(msrp_uclep_offset to msrp_uclep_offset + msrp_uclep_q'length-1), + scout => sov(msrp_uclep_offset to msrp_uclep_offset + msrp_uclep_q'length-1), + din => spr_msrp_uclep , + dout => msrp_uclep_q); +pc_dbg_action_latch : tri_rlmreg_p + generic map (width => pc_dbg_action_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(pc_dbg_action_offset to pc_dbg_action_offset + pc_dbg_action_q'length-1), + scout => sov(pc_dbg_action_offset to pc_dbg_action_offset + pc_dbg_action_q'length-1), + din => pc_xu_dbg_action , + dout => pc_dbg_action_q); +pc_dbg_stop_latch : tri_rlmreg_p + generic map (width => pc_dbg_stop_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(pc_dbg_stop_offset to pc_dbg_stop_offset + pc_dbg_stop_q'length-1), + scout => sov(pc_dbg_stop_offset to pc_dbg_stop_offset + pc_dbg_stop_q'length-1), + din => pc_dbg_stop_d, + dout => pc_dbg_stop_q); +pc_dbg_stop_2_latch : tri_rlmreg_p + generic map (width => pc_dbg_stop_2_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(pc_dbg_stop_2_offset to pc_dbg_stop_2_offset + pc_dbg_stop_2_q'length-1), + scout => sov(pc_dbg_stop_2_offset to pc_dbg_stop_2_offset + pc_dbg_stop_2_q'length-1), + din => pc_dbg_stop, + dout => pc_dbg_stop_2_q); +pc_err_mcsr_rpt_latch : tri_rlmreg_p + generic map (width => pc_err_mcsr_rpt_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(pc_err_mcsr_rpt_offset to pc_err_mcsr_rpt_offset + pc_err_mcsr_rpt_q'length-1), + scout => sov(pc_err_mcsr_rpt_offset to pc_err_mcsr_rpt_offset + pc_err_mcsr_rpt_q'length-1), + din => pc_err_mcsr_rpt_d, + dout => pc_err_mcsr_rpt_q); +pc_err_mcsr_summary_latch : tri_rlmreg_p + generic map (width => pc_err_mcsr_summary_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(pc_err_mcsr_summary_offset to pc_err_mcsr_summary_offset + pc_err_mcsr_summary_q'length-1), + scout => sov(pc_err_mcsr_summary_offset to pc_err_mcsr_summary_offset + pc_err_mcsr_summary_q'length-1), + din => pc_err_mcsr_summary_d, + dout => pc_err_mcsr_summary_q); +pc_init_reset_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(pc_init_reset_offset), + scout => sov(pc_init_reset_offset), + din => pc_xu_init_reset , + dout => pc_init_reset_q); +quiesced_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(quiesced_offset), + scout => sov(quiesced_offset), + din => quiesced_d, + dout => quiesced_q); +ram_flush_latch : tri_rlmreg_p + generic map (width => ram_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ram_flush_offset to ram_flush_offset + ram_flush_q'length-1), + scout => sov(ram_flush_offset to ram_flush_offset + ram_flush_q'length-1), + din => ram_flush_d, + dout => ram_flush_q); +ram_ip_latch : tri_rlmreg_p + generic map (width => ram_ip_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ram_ip_offset to ram_ip_offset + ram_ip_q'length-1), + scout => sov(ram_ip_offset to ram_ip_offset + ram_ip_q'length-1), + din => ram_ip_d, + dout => ram_ip_q); +ram_mode_latch : tri_rlmreg_p + generic map (width => ram_mode_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ram_mode_offset to ram_mode_offset + ram_mode_q'length-1), + scout => sov(ram_mode_offset to ram_mode_offset + ram_mode_q'length-1), + din => ram_mode_d, + dout => ram_mode_q); +slowspr_flush_latch : tri_rlmreg_p + generic map (width => slowspr_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(slowspr_flush_offset to slowspr_flush_offset + slowspr_flush_q'length-1), + scout => sov(slowspr_flush_offset to slowspr_flush_offset + slowspr_flush_q'length-1), + din => mux_cpl_slowspr_flush , + dout => slowspr_flush_q); +spr_cpl_async_int_latch : tri_rlmreg_p + generic map (width => spr_cpl_async_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(spr_cpl_async_int_offset to spr_cpl_async_int_offset + spr_cpl_async_int_q'length-1), + scout => sov(spr_cpl_async_int_offset to spr_cpl_async_int_offset + spr_cpl_async_int_q'length-1), + din => spr_cpl_async_int , + dout => spr_cpl_async_int_q); +ram_execute_latch : tri_rlmreg_p + generic map (width => ram_execute_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ram_execute_offset to ram_execute_offset + ram_execute_q'length-1), + scout => sov(ram_execute_offset to ram_execute_offset + ram_execute_q'length-1), + din => ram_execute_d, + dout => ram_execute_q); +ssprwr_ip_latch : tri_rlmreg_p + generic map (width => ssprwr_ip_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ssprwr_ip_offset to ssprwr_ip_offset + ssprwr_ip_q'length-1), + scout => sov(ssprwr_ip_offset to ssprwr_ip_offset + ssprwr_ip_q'length-1), + din => ssprwr_ip_d, + dout => ssprwr_ip_q); +exx_cm_hold_latch : tri_rlmreg_p + generic map (width => exx_cm_hold_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(exx_cm_hold_offset to exx_cm_hold_offset + exx_cm_hold_q'length-1), + scout => sov(exx_cm_hold_offset to exx_cm_hold_offset + exx_cm_hold_q'length-1), + din => exx_cm_hold , + dout => exx_cm_hold_q); +xu_ex1_n_flush_latch : tri_rlmreg_p + generic map (width => xu_ex1_n_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_flush_inf_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xu_ex1_n_flush_offset to xu_ex1_n_flush_offset + xu_ex1_n_flush_q'length-1), + scout => sov(xu_ex1_n_flush_offset to xu_ex1_n_flush_offset + xu_ex1_n_flush_q'length-1), + din => rf1_flush , + dout => xu_ex1_n_flush_q); +xu_ex1_s_flush_latch : tri_rlmreg_p + generic map (width => xu_ex1_s_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_flush_inf_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xu_ex1_s_flush_offset to xu_ex1_s_flush_offset + xu_ex1_s_flush_q'length-1), + scout => sov(xu_ex1_s_flush_offset to xu_ex1_s_flush_offset + xu_ex1_s_flush_q'length-1), + din => rf1_flush , + dout => xu_ex1_s_flush_q); +xu_ex1_w_flush_latch : tri_rlmreg_p + generic map (width => xu_ex1_w_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_flush_inf_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xu_ex1_w_flush_offset to xu_ex1_w_flush_offset + xu_ex1_w_flush_q'length-1), + scout => sov(xu_ex1_w_flush_offset to xu_ex1_w_flush_offset + xu_ex1_w_flush_q'length-1), + din => rf1_flush , + dout => xu_ex1_w_flush_q); +xu_ex2_n_flush_latch : tri_rlmreg_p + generic map (width => xu_ex2_n_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_flush_inf_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xu_ex2_n_flush_offset to xu_ex2_n_flush_offset + xu_ex2_n_flush_q'length-1), + scout => sov(xu_ex2_n_flush_offset to xu_ex2_n_flush_offset + xu_ex2_n_flush_q'length-1), + din => ex1_flush , + dout => xu_ex2_n_flush_q); +xu_ex2_s_flush_latch : tri_rlmreg_p + generic map (width => xu_ex2_s_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_flush_inf_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xu_ex2_s_flush_offset to xu_ex2_s_flush_offset + xu_ex2_s_flush_q'length-1), + scout => sov(xu_ex2_s_flush_offset to xu_ex2_s_flush_offset + xu_ex2_s_flush_q'length-1), + din => ex1_flush , + dout => xu_ex2_s_flush_q); +xu_ex2_w_flush_latch : tri_rlmreg_p + generic map (width => xu_ex2_w_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_flush_inf_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xu_ex2_w_flush_offset to xu_ex2_w_flush_offset + xu_ex2_w_flush_q'length-1), + scout => sov(xu_ex2_w_flush_offset to xu_ex2_w_flush_offset + xu_ex2_w_flush_q'length-1), + din => ex1_flush , + dout => xu_ex2_w_flush_q); +xu_ex3_n_flush_latch : tri_rlmreg_p + generic map (width => xu_ex3_n_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_flush_inf_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xu_ex3_n_flush_offset to xu_ex3_n_flush_offset + xu_ex3_n_flush_q'length-1), + scout => sov(xu_ex3_n_flush_offset to xu_ex3_n_flush_offset + xu_ex3_n_flush_q'length-1), + din => ex2_flush , + dout => xu_ex3_n_flush_q); +xu_ex3_s_flush_latch : tri_rlmreg_p + generic map (width => xu_ex3_s_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_flush_inf_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xu_ex3_s_flush_offset to xu_ex3_s_flush_offset + xu_ex3_s_flush_q'length-1), + scout => sov(xu_ex3_s_flush_offset to xu_ex3_s_flush_offset + xu_ex3_s_flush_q'length-1), + din => ex2_flush , + dout => xu_ex3_s_flush_q); +xu_ex3_w_flush_latch : tri_rlmreg_p + generic map (width => xu_ex3_w_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_flush_inf_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xu_ex3_w_flush_offset to xu_ex3_w_flush_offset + xu_ex3_w_flush_q'length-1), + scout => sov(xu_ex3_w_flush_offset to xu_ex3_w_flush_offset + xu_ex3_w_flush_q'length-1), + din => ex2_flush , + dout => xu_ex3_w_flush_q); +xu_ex4_n_flush_latch : tri_rlmreg_p + generic map (width => xu_ex4_n_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_flush_inf_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xu_ex4_n_flush_offset to xu_ex4_n_flush_offset + xu_ex4_n_flush_q'length-1), + scout => sov(xu_ex4_n_flush_offset to xu_ex4_n_flush_offset + xu_ex4_n_flush_q'length-1), + din => ex3_flush , + dout => xu_ex4_n_flush_q); +xu_ex4_s_flush_latch : tri_rlmreg_p + generic map (width => xu_ex4_s_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_flush_inf_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xu_ex4_s_flush_offset to xu_ex4_s_flush_offset + xu_ex4_s_flush_q'length-1), + scout => sov(xu_ex4_s_flush_offset to xu_ex4_s_flush_offset + xu_ex4_s_flush_q'length-1), + din => ex3_flush , + dout => xu_ex4_s_flush_q); +xu_ex4_w_flush_latch : tri_rlmreg_p + generic map (width => xu_ex4_w_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_flush_inf_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xu_ex4_w_flush_offset to xu_ex4_w_flush_offset + xu_ex4_w_flush_q'length-1), + scout => sov(xu_ex4_w_flush_offset to xu_ex4_w_flush_offset + xu_ex4_w_flush_q'length-1), + din => ex3_flush , + dout => xu_ex4_w_flush_q); +xu_ex5_n_flush_latch : tri_rlmreg_p + generic map (width => xu_ex5_n_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_flush_inf_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xu_ex5_n_flush_offset to xu_ex5_n_flush_offset + xu_ex5_n_flush_q'length-1), + scout => sov(xu_ex5_n_flush_offset to xu_ex5_n_flush_offset + xu_ex5_n_flush_q'length-1), + din => ex4_flush , + dout => xu_ex5_n_flush_q); +xu_ex5_s_flush_latch : tri_rlmreg_p + generic map (width => xu_ex5_s_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_flush_inf_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xu_ex5_s_flush_offset to xu_ex5_s_flush_offset + xu_ex5_s_flush_q'length-1), + scout => sov(xu_ex5_s_flush_offset to xu_ex5_s_flush_offset + xu_ex5_s_flush_q'length-1), + din => ex4_flush , + dout => xu_ex5_s_flush_q); +xu_ex5_w_flush_latch : tri_rlmreg_p + generic map (width => xu_ex5_w_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_flush_inf_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xu_ex5_w_flush_offset to xu_ex5_w_flush_offset + xu_ex5_w_flush_q'length-1), + scout => sov(xu_ex5_w_flush_offset to xu_ex5_w_flush_offset + xu_ex5_w_flush_q'length-1), + din => ex4_flush , + dout => xu_ex5_w_flush_q); +xu_is2_n_flush_latch : tri_rlmreg_p + generic map (width => xu_is2_n_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_flush_inf_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xu_is2_n_flush_offset to xu_is2_n_flush_offset + xu_is2_n_flush_q'length-1), + scout => sov(xu_is2_n_flush_offset to xu_is2_n_flush_offset + xu_is2_n_flush_q'length-1), + din => any_flush , + dout => xu_is2_n_flush_q); +xu_rf0_n_flush_latch : tri_rlmreg_p + generic map (width => xu_rf0_n_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_flush_inf_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xu_rf0_n_flush_offset to xu_rf0_n_flush_offset + xu_rf0_n_flush_q'length-1), + scout => sov(xu_rf0_n_flush_offset to xu_rf0_n_flush_offset + xu_rf0_n_flush_q'length-1), + din => is2_flush , + dout => xu_rf0_n_flush_q); +xu_rf1_n_flush_latch : tri_rlmreg_p + generic map (width => xu_rf1_n_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_flush_inf_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xu_rf1_n_flush_offset to xu_rf1_n_flush_offset + xu_rf1_n_flush_q'length-1), + scout => sov(xu_rf1_n_flush_offset to xu_rf1_n_flush_offset + xu_rf1_n_flush_q'length-1), + din => rf0_flush , + dout => xu_rf1_n_flush_q); +xu_rf1_s_flush_latch : tri_rlmreg_p + generic map (width => xu_rf1_s_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_flush_inf_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xu_rf1_s_flush_offset to xu_rf1_s_flush_offset + xu_rf1_s_flush_q'length-1), + scout => sov(xu_rf1_s_flush_offset to xu_rf1_s_flush_offset + xu_rf1_s_flush_q'length-1), + din => rf0_flush , + dout => xu_rf1_s_flush_q); +xu_rf1_w_flush_latch : tri_rlmreg_p + generic map (width => xu_rf1_w_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_flush_inf_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xu_rf1_w_flush_offset to xu_rf1_w_flush_offset + xu_rf1_w_flush_q'length-1), + scout => sov(xu_rf1_w_flush_offset to xu_rf1_w_flush_offset + xu_rf1_w_flush_q'length-1), + din => rf0_flush , + dout => xu_rf1_w_flush_q); +ex5_np1_irpt_dbg_cint_latch : tri_rlmreg_p + generic map (width => ex5_np1_irpt_dbg_cint_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_np1_irpt_dbg_cint_offset to ex5_np1_irpt_dbg_cint_offset + ex5_np1_irpt_dbg_cint_q'length-1), + scout => sov(ex5_np1_irpt_dbg_cint_offset to ex5_np1_irpt_dbg_cint_offset + ex5_np1_irpt_dbg_cint_q'length-1), + din => ex4_np1_irpt_dbg_cint, + dout => ex5_np1_irpt_dbg_cint_q); +ex6_np1_irpt_dbg_cint_latch : tri_rlmreg_p + generic map (width => ex6_np1_irpt_dbg_cint_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_np1_irpt_dbg_cint_offset to ex6_np1_irpt_dbg_cint_offset + ex6_np1_irpt_dbg_cint_q'length-1), + scout => sov(ex6_np1_irpt_dbg_cint_offset to ex6_np1_irpt_dbg_cint_offset + ex6_np1_irpt_dbg_cint_q'length-1), + din => ex6_np1_irpt_dbg_cint_d, + dout => ex6_np1_irpt_dbg_cint_q); +ex5_np1_irpt_dbg_event_latch : tri_rlmreg_p + generic map (width => ex5_np1_irpt_dbg_event_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_np1_irpt_dbg_event_offset to ex5_np1_irpt_dbg_event_offset + ex5_np1_irpt_dbg_event_q'length-1), + scout => sov(ex5_np1_irpt_dbg_event_offset to ex5_np1_irpt_dbg_event_offset + ex5_np1_irpt_dbg_event_q'length-1), + din => ex4_np1_irpt_dbg_event, + dout => ex5_np1_irpt_dbg_event_q); +ex6_np1_irpt_dbg_event_latch : tri_rlmreg_p + generic map (width => ex6_np1_irpt_dbg_event_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_np1_irpt_dbg_event_offset to ex6_np1_irpt_dbg_event_offset + ex6_np1_irpt_dbg_event_q'length-1), + scout => sov(ex6_np1_irpt_dbg_event_offset to ex6_np1_irpt_dbg_event_offset + ex6_np1_irpt_dbg_event_q'length-1), + din => ex6_np1_irpt_dbg_event_d, + dout => ex6_np1_irpt_dbg_event_q); +clkg_ctl_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(clkg_ctl_offset), + scout => sov(clkg_ctl_offset), + din => spr_xucr0_clkg_ctl(2) , + dout => clkg_ctl_q); +xu_rf_seq_end_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xu_rf_seq_end_offset), + scout => sov(xu_rf_seq_end_offset), + din => gpr_cpl_regfile_seq_end , + dout => xu_rf_seq_end_q); +xu_rfpe_ack_latch : tri_rlmreg_p + generic map (width => xu_rfpe_ack_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xu_rfpe_ack_offset to xu_rfpe_ack_offset + xu_rfpe_ack_q'length-1), + scout => sov(xu_rfpe_ack_offset to xu_rfpe_ack_offset + xu_rfpe_ack_q'length-1), + din => xu_rfpe_ack_d, + dout => xu_rfpe_ack_q); +xu_rfpe_hold_present_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xu_rfpe_hold_present_offset), + scout => sov(xu_rfpe_hold_present_offset), + din => xu_rfpe_hold_present_d, + dout => xu_rfpe_hold_present_q); +exx_act_latch : tri_rlmreg_p + generic map (width => exx_act_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(exx_act_offset to exx_act_offset + exx_act_q'length-1), + scout => sov(exx_act_offset to exx_act_offset + exx_act_q'length-1), + din => exx_act_d, + dout => exx_act_q); +ex4_mchk_int_en_latch : tri_rlmreg_p + generic map (width => ex4_mchk_int_en_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_mchk_int_en_offset to ex4_mchk_int_en_offset + ex4_mchk_int_en_q'length-1), + scout => sov(ex4_mchk_int_en_offset to ex4_mchk_int_en_offset + ex4_mchk_int_en_q'length-1), + din => ex3_mchk_int_en, + dout => ex4_mchk_int_en_q); +ex5_mchk_int_en_latch : tri_rlmreg_p + generic map (width => ex5_mchk_int_en_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_mchk_int_en_offset to ex5_mchk_int_en_offset + ex5_mchk_int_en_q'length-1), + scout => sov(ex5_mchk_int_en_offset to ex5_mchk_int_en_offset + ex5_mchk_int_en_q'length-1), + din => ex4_mchk_int_en_q, + dout => ex5_mchk_int_en_q); +trace_bus_enable_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(trace_bus_enable_offset), + scout => sov(trace_bus_enable_offset), + din => pc_xu_trace_bus_enable , + dout => trace_bus_enable_q); +ex1_instr_trace_type_latch : tri_rlmreg_p + generic map (width => ex1_instr_trace_type_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_instr_trace_type_offset to ex1_instr_trace_type_offset + ex1_instr_trace_type_q'length-1), + scout => sov(ex1_instr_trace_type_offset to ex1_instr_trace_type_offset + ex1_instr_trace_type_q'length-1), + din => dec_cpl_rf1_instr_trace_type, + dout => ex1_instr_trace_type_q); +ex1_instr_trace_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_instr_trace_val_offset), + scout => sov(ex1_instr_trace_val_offset), + din => dec_cpl_rf1_instr_trace_val, + dout => ex1_instr_trace_val_q); +ex1_xu_issued_latch : tri_rlmreg_p + generic map (width => ex1_xu_issued_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_xu_issued_offset to ex1_xu_issued_offset + ex1_xu_issued_q'length-1), + scout => sov(ex1_xu_issued_offset to ex1_xu_issued_offset + ex1_xu_issued_q'length-1), + din => dec_cpl_rf1_issued , + dout => ex1_xu_issued_q); +ex2_xu_issued_latch : tri_rlmreg_p + generic map (width => ex2_xu_issued_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_xu_issued_offset to ex2_xu_issued_offset + ex2_xu_issued_q'length-1), + scout => sov(ex2_xu_issued_offset to ex2_xu_issued_offset + ex2_xu_issued_q'length-1), + din => ex1_xu_issued_q , + dout => ex2_xu_issued_q); +ex3_xu_issued_latch : tri_rlmreg_p + generic map (width => ex3_xu_issued_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_xu_issued_offset to ex3_xu_issued_offset + ex3_xu_issued_q'length-1), + scout => sov(ex3_xu_issued_offset to ex3_xu_issued_offset + ex3_xu_issued_q'length-1), + din => ex2_xu_issued_q , + dout => ex3_xu_issued_q); +ex4_xu_issued_latch : tri_rlmreg_p + generic map (width => ex4_xu_issued_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_xu_issued_offset to ex4_xu_issued_offset + ex4_xu_issued_q'length-1), + scout => sov(ex4_xu_issued_offset to ex4_xu_issued_offset + ex4_xu_issued_q'length-1), + din => ex3_xu_issued , + dout => ex4_xu_issued_q); +ex3_axu_issued_latch : tri_rlmreg_p + generic map (width => ex3_axu_issued_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_axu_issued_offset to ex3_axu_issued_offset + ex3_axu_issued_q'length-1), + scout => sov(ex3_axu_issued_offset to ex3_axu_issued_offset + ex3_axu_issued_q'length-1), + din => fu_xu_ex2_ifar_issued , + dout => ex3_axu_issued_q); +ex4_axu_issued_latch : tri_rlmreg_p + generic map (width => ex4_axu_issued_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_axu_issued_offset to ex4_axu_issued_offset + ex4_axu_issued_q'length-1), + scout => sov(ex4_axu_issued_offset to ex4_axu_issued_offset + ex4_axu_issued_q'length-1), + din => ex3_axu_issued_q , + dout => ex4_axu_issued_q); +ex2_instr_dbg_latch : tri_rlmreg_p + generic map (width => ex2_instr_dbg_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_instr_dbg_offset to ex2_instr_dbg_offset + ex2_instr_dbg_q'length-1), + scout => sov(ex2_instr_dbg_offset to ex2_instr_dbg_offset + ex2_instr_dbg_q'length-1), + din => ex1_instr , + dout => ex2_instr_dbg_q); +ex2_instr_trace_type_latch : tri_rlmreg_p + generic map (width => ex2_instr_trace_type_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_instr_trace_type_offset to ex2_instr_trace_type_offset + ex2_instr_trace_type_q'length-1), + scout => sov(ex2_instr_trace_type_offset to ex2_instr_trace_type_offset + ex2_instr_trace_type_q'length-1), + din => ex1_instr_trace_type_q , + dout => ex2_instr_trace_type_q); +ex4_instr_trace_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_instr_trace_val_offset), + scout => sov(ex4_instr_trace_val_offset), + din => dec_cpl_ex3_instr_trace_val, + dout => ex4_instr_trace_val_q); +ex5_axu_val_dbg_latch : tri_regk + generic map (width => ex5_axu_val_dbg_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex4_axu_val , + dout => ex5_axu_val_dbg_q); +ex5_instr_cpl_dbg_latch : tri_regk + generic map (width => ex5_instr_cpl_dbg_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex4_instr_cpl , + dout => ex5_instr_cpl_dbg_q); +ex5_instr_trace_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_instr_trace_val_offset), + scout => sov(ex5_instr_trace_val_offset), + din => ex4_instr_trace_val_q , + dout => ex5_instr_trace_val_q); +ex5_siar_latch : tri_rlmreg_p + generic map (width => ex5_siar_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_siar_offset to ex5_siar_offset + ex5_siar_q'length-1), + scout => sov(ex5_siar_offset to ex5_siar_offset + ex5_siar_q'length-1), + din => ex5_siar_d, + dout => ex5_siar_q); +ex5_siar_cpl_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_siar_cpl_offset), + scout => sov(ex5_siar_cpl_offset), + din => ex5_siar_cpl_d, + dout => ex5_siar_cpl_q); +ex5_siar_gs_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_siar_gs_offset), + scout => sov(ex5_siar_gs_offset), + din => ex5_siar_gs_d, + dout => ex5_siar_gs_q); +ex5_siar_issued_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_siar_issued_offset), + scout => sov(ex5_siar_issued_offset), + din => ex5_siar_issued_d, + dout => ex5_siar_issued_q); +ex5_siar_pr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_siar_pr_offset), + scout => sov(ex5_siar_pr_offset), + din => ex5_siar_pr_d, + dout => ex5_siar_pr_q); +ex5_siar_tid_latch : tri_rlmreg_p + generic map (width => ex5_siar_tid_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_siar_tid_offset to ex5_siar_tid_offset + ex5_siar_tid_q'length-1), + scout => sov(ex5_siar_tid_offset to ex5_siar_tid_offset + ex5_siar_tid_q'length-1), + din => ex5_siar_tid_d, + dout => ex5_siar_tid_q); +ex5_ucode_end_dbg_latch : tri_rlmreg_p + generic map (width => ex5_ucode_end_dbg_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_ucode_end_dbg_offset to ex5_ucode_end_dbg_offset + ex5_ucode_end_dbg_q'length-1), + scout => sov(ex5_ucode_end_dbg_offset to ex5_ucode_end_dbg_offset + ex5_ucode_end_dbg_q'length-1), + din => ex4_ucode_end , + dout => ex5_ucode_end_dbg_q); +ex5_ucode_val_dbg_latch : tri_rlmreg_p + generic map (width => ex5_ucode_val_dbg_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_ucode_val_dbg_offset to ex5_ucode_val_dbg_offset + ex5_ucode_val_dbg_q'length-1), + scout => sov(ex5_ucode_val_dbg_offset to ex5_ucode_val_dbg_offset + ex5_ucode_val_dbg_q'length-1), + din => ex4_ucode_val , + dout => ex5_ucode_val_dbg_q); +instr_trace_mode_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(instr_trace_mode_offset), + scout => sov(instr_trace_mode_offset), + din => pc_xu_instr_trace_mode , + dout => instr_trace_mode_q); +debug_data_out_latch : tri_rlmreg_p + generic map (width => debug_data_out_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(debug_data_out_offset to debug_data_out_offset + debug_data_out_q'length-1), + scout => sov(debug_data_out_offset to debug_data_out_offset + debug_data_out_q'length-1), + din => debug_data_out_d, + dout => debug_data_out_q); +debug_mux_ctrls_latch : tri_rlmreg_p + generic map (width => debug_mux_ctrls_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(debug_mux_ctrls_offset to debug_mux_ctrls_offset + debug_mux_ctrls_q'length-1), + scout => sov(debug_mux_ctrls_offset to debug_mux_ctrls_offset + debug_mux_ctrls_q'length-1), + din => cpl_debug_mux_ctrls , + dout => debug_mux_ctrls_q); +debug_mux_ctrls_int_latch : tri_rlmreg_p + generic map (width => debug_mux_ctrls_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(debug_mux_ctrls_int_offset to debug_mux_ctrls_int_offset + debug_mux_ctrls_int_q'length-1), + scout => sov(debug_mux_ctrls_int_offset to debug_mux_ctrls_int_offset + debug_mux_ctrls_int_q'length-1), + din => debug_mux_ctrls_int, + dout => debug_mux_ctrls_int_q); +trigger_data_out_latch : tri_rlmreg_p + generic map (width => trigger_data_out_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(trigger_data_out_offset to trigger_data_out_offset + trigger_data_out_q'length-1), + scout => sov(trigger_data_out_offset to trigger_data_out_offset + trigger_data_out_q'length-1), + din => trigger_data_out_d, + dout => trigger_data_out_q); +event_bus_enable_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(event_bus_enable_offset), + scout => sov(event_bus_enable_offset), + din => pc_xu_event_bus_enable , + dout => event_bus_enable_q); +ex2_perf_event_latch : tri_regk + generic map (width => ex2_perf_event_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => event_bus_enable_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex2_perf_event_d, + dout => ex2_perf_event_q); +ex3_perf_event_latch : tri_rlmreg_p + generic map (width => ex3_perf_event_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => event_bus_enable_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_perf_event_offset to ex3_perf_event_offset + ex3_perf_event_q'length-1), + scout => sov(ex3_perf_event_offset to ex3_perf_event_offset + ex3_perf_event_q'length-1), + din => ex2_perf_event_q , + dout => ex3_perf_event_q); +ex4_perf_event_latch : tri_regk + generic map (width => ex4_perf_event_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => event_bus_enable_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex4_perf_event_d, + dout => ex4_perf_event_q); +ex5_perf_event_latch : tri_rlmreg_p + generic map (width => ex5_perf_event_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => event_bus_enable_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_perf_event_offset to ex5_perf_event_offset + ex5_perf_event_q'length-1), + scout => sov(ex5_perf_event_offset to ex5_perf_event_offset + ex5_perf_event_q'length-1), + din => ex5_perf_event_d, + dout => ex5_perf_event_q); +spr_bit_act_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(spr_bit_act_offset), + scout => sov(spr_bit_act_offset), + din => spr_bit_act, + dout => spr_bit_act_q); + + +dd1_clk_override_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc, + thold_b => ccfg_so_thold_0_b, + scin => siv_ccfg(dd1_clk_override_offset_ccfg to dd1_clk_override_offset_ccfg), + scout => sov_ccfg(dd1_clk_override_offset_ccfg to dd1_clk_override_offset_ccfg), + dout(0) => clk_override_q); + + +spare_0_lcb: entity tri.tri_lcbnd(tri_lcbnd) + port map(vd => vdd, + gd => gnd, + act => tidn, + nclk => nclk, + forcee => func_sl_force, + thold_b => func_sl_thold_0_b, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + sg => sg_0, + lclk => spare_0_lclk, + d1clk => spare_0_d1clk, + d2clk => spare_0_d2clk); +spare_0_latch : entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width => spare_0_q'length, expand_type => expand_type, btr => "NLI0001_X2_A12TH", init=>(spare_0_q'range=>'0')) + port map (vd => vdd, gd => gnd, + LCLK => spare_0_lclk, + D1CLK => spare_0_d1clk, + D2CLK => spare_0_d2clk, + SCANIN => siv(spare_0_offset to spare_0_offset + spare_0_q'length-1), + SCANOUT => sov(spare_0_offset to spare_0_offset + spare_0_q'length-1), + D => spare_0_d, + QB => spare_0_q); +spare_0_d <= not spare_0_q; + +spare_1_lcb: entity tri.tri_lcbnd(tri_lcbnd) + port map(vd => vdd, + gd => gnd, + act => tiup, + nclk => nclk, + forcee => func_sl_force, + thold_b => func_sl_thold_0_b, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + sg => sg_0, + lclk => spare_1_lclk, + d1clk => spare_1_d1clk, + d2clk => spare_1_d2clk); +spare_1_latch : entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width => spare_1_q'length, expand_type => expand_type, btr => "NLI0001_X2_A12TH", init=>(spare_1_q'range=>'0')) + port map (vd => vdd, gd => gnd, + LCLK => spare_1_lclk, + D1CLK => spare_1_d1clk, + D2CLK => spare_1_d2clk, + SCANIN => siv(spare_1_offset to spare_1_offset + spare_1_q'length-1), + SCANOUT => sov(spare_1_offset to spare_1_offset + spare_1_q'length-1), + D => spare_1_d, + QB => spare_1_q); +spare_1_d(0 to 3) <= not (ex4_instr_cpl and not ex5_in_ucode_q); +spare_1_d(4 to 7) <= not spare_1_q(0 to 3); +spare_1_d(8 to 11) <= not spare_1_q(4 to 7); +spare_1_d(12 to 15) <= not spare_1_q(12 to 15); + + +spare_2_lcb: entity tri.tri_lcbnd(tri_lcbnd) + port map(vd => vdd, + gd => gnd, + act => tidn, + nclk => nclk, + forcee => func_sl_force, + thold_b => func_sl_thold_0_b, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + sg => sg_0, + lclk => spare_2_lclk, + d1clk => spare_2_d1clk, + d2clk => spare_2_d2clk); +spare_2_latch : entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width => spare_2_q'length, expand_type => expand_type, btr => "NLI0001_X2_A12TH", init=>(spare_2_q'range=>'0')) + port map (vd => vdd, gd => gnd, + LCLK => spare_2_lclk, + D1CLK => spare_2_d1clk, + D2CLK => spare_2_d2clk, + SCANIN => siv(spare_2_offset to spare_2_offset + spare_2_q'length-1), + SCANOUT => sov(spare_2_offset to spare_2_offset + spare_2_q'length-1), + D => spare_2_d, + QB => spare_2_q); +spare_2_d <= not spare_2_q; + +spare_3_lcb: entity tri.tri_lcbnd(tri_lcbnd) + port map(vd => vdd, + gd => gnd, + act => tidn, + nclk => nclk, + forcee => func_sl_force, + thold_b => func_sl_thold_0_b, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + sg => sg_0, + lclk => spare_3_lclk, + d1clk => spare_3_d1clk, + d2clk => spare_3_d2clk); +spare_3_latch : entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width => spare_3_q'length, expand_type => expand_type, btr => "NLI0001_X2_A12TH", init=>(spare_3_q'range=>'0')) + port map (vd => vdd, gd => gnd, + LCLK => spare_3_lclk, + D1CLK => spare_3_d1clk, + D2CLK => spare_3_d2clk, + SCANIN => siv(spare_3_offset to spare_3_offset + spare_3_q'length-1), + SCANOUT => sov(spare_3_offset to spare_3_offset + spare_3_q'length-1), + D => spare_3_d, + QB => spare_3_q); +spare_3_d <= not spare_3_q; + +spare_4_lcb: entity tri.tri_lcbnd(tri_lcbnd) + port map(vd => vdd, + gd => gnd, + act => tiup, + nclk => nclk, + forcee => func_sl_force, + thold_b => func_sl_thold_0_b, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + sg => sg_0, + lclk => spare_4_lclk, + d1clk => spare_4_d1clk, + d2clk => spare_4_d2clk); +spare_4_latch : entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width => spare_4_q'length, expand_type => expand_type, btr => "NLI0001_X2_A12TH", init=>(spare_4_q'range=>'0')) + port map (vd => vdd, gd => gnd, + LCLK => spare_4_lclk, + D1CLK => spare_4_d1clk, + D2CLK => spare_4_d2clk, + SCANIN => siv(spare_4_offset to spare_4_offset + spare_4_q'length-1), + SCANOUT => sov(spare_4_offset to spare_4_offset + spare_4_q'length-1), + D => spare_4_d, + QB => spare_4_q); + +spare_5_lcb: entity tri.tri_lcbnd(tri_lcbnd) + port map(vd => vdd, + gd => gnd, + act => tiup, + nclk => nclk, + forcee => func_sl_force, + thold_b => func_sl_thold_0_b, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + sg => sg_0, + lclk => spare_5_lclk, + d1clk => spare_5_d1clk, + d2clk => spare_5_d2clk); +spare_5_latch : entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width => spare_5_q'length, expand_type => expand_type, btr => "NLI0001_X2_A12TH", init=>(spare_5_q'range=>'0')) + port map (vd => vdd, gd => gnd, + LCLK => spare_5_lclk, + D1CLK => spare_5_d1clk, + D2CLK => spare_5_d2clk, + SCANIN => siv(spare_5_offset to spare_5_offset + spare_5_q'length-1), + SCANOUT => sov(spare_5_offset to spare_5_offset + spare_5_q'length-1), + D => spare_5_d, + QB => spare_5_q); + + + + + + + + +ex4_dac_cmpr_gem : for t in 1 to 4 generate + ex4_dacr_cmpr_latch : tri_regk + generic map (width => ex4_dacr_cmpr_q(t)'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex4_dacr_cmpr_d(t), + dout => ex4_dacr_cmpr_q(t)); + ex4_dacw_cmpr_latch : tri_regk + generic map (width => ex4_dacw_cmpr_q(t)'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex4_dacw_cmpr_d(t), + dout => ex4_dacw_cmpr_q(t)); +end generate; + +ex5_late_flush_gen : for t in 0 to ifar_repwr-1 generate + ex5_late_flush_latch : tri_rlmreg_p + generic map (width => ex5_late_flush_q(t)'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_flush_inf_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_late_flush_offset+ex5_late_flush_q(t)'length*t to ex5_late_flush_offset + ex5_late_flush_q(t)'length*(t+1)-1), + scout => sov(ex5_late_flush_offset+ex5_late_flush_q(t)'length*t to ex5_late_flush_offset + ex5_late_flush_q(t)'length*(t+1)-1), + din => ex5_late_flush_d(t), + dout => ex5_late_flush_q(t)); +end generate; +ex2_ifar_b_latch_gen : for t in 0 to threads-1 generate + ex2_ifar_b_latch : entity tri.tri_aoi22_nlats_wlcb(tri_aoi22_nlats_wlcb) + generic map (width => eff_ifar, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_ifar_act(t), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_ifar_b_offset+eff_ifar*t to ex2_ifar_b_offset+eff_ifar*(t+1)-1), + scout => sov(ex2_ifar_b_offset+eff_ifar*t to ex2_ifar_b_offset+eff_ifar*(t+1)-1), + A1 => fu_xu_ex1_ifar(eff_ifar*t to eff_ifar*(t+1)-1), + A2 => ex1_ifar_sel_b(eff_ifar*t to eff_ifar*(t+1)-1), + B1 => ex1_xu_ifar, + B2 => ex1_ifar_sel(eff_ifar*t to eff_ifar*(t+1)-1), + QB => ex2_ifar_b_q(eff_ifar*t to eff_ifar*(t+1)-1)); + ex1_ifar_sel(eff_ifar*t to eff_ifar*(t+1)-1) <= (others=> (ex1_xu_val_q(t) or ex1_ucode_val_q(t))); + ex1_ifar_sel_b(eff_ifar*t to eff_ifar*(t+1)-1) <= (others=>not(ex1_xu_val_q(t) or ex1_ucode_val_q(t))); + + ex3_ifar_latch : tri_rlmreg_p + generic map (width => eff_ifar, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_ifar_act(t), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_ifar_offset+eff_ifar*t to ex3_ifar_offset+eff_ifar*(t+1)-1), + scout => sov(ex3_ifar_offset+eff_ifar*t to ex3_ifar_offset+eff_ifar*(t+1)-1), + din => ex2_ifar(eff_ifar*t to eff_ifar*(t+1)-1), + dout => ex3_ifar_q(eff_ifar*t to eff_ifar*(t+1)-1)); + ex4_ifar_latch : tri_rlmreg_p + generic map (width => eff_ifar, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex3_ifar_act(t), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_ifar_offset+eff_ifar*t to ex4_ifar_offset+eff_ifar*(t+1)-1), + scout => sov(ex4_ifar_offset+eff_ifar*t to ex4_ifar_offset+eff_ifar*(t+1)-1), + din => ex3_ifar_q(eff_ifar*t to eff_ifar*(t+1)-1), + dout => ex4_ifar_q(eff_ifar*t to eff_ifar*(t+1)-1)); +end generate; + +perv_2to1_reg: tri_plat + generic map (width => 8, expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_xu_ccflush_dc, + din(0) => func_slp_sl_thold_2, + din(1) => func_slp_nsl_thold_2, + din(2) => func_sl_thold_2, + din(3) => func_nsl_thold_2, + din(4) => cfg_sl_thold_2, + din(5) => cfg_slp_sl_thold_2, + din(6) => sg_2, + din(7) => fce_2, + q(0) => func_slp_sl_thold_1, + q(1) => func_slp_nsl_thold_1, + q(2) => func_sl_thold_1, + q(3) => func_nsl_thold_1, + q(4) => cfg_sl_thold_1, + q(5) => cfg_slp_sl_thold_1, + q(6) => sg_1, + q(7) => fce_1); + +perv_1to0_reg: tri_plat + generic map (width => 8, expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_xu_ccflush_dc, + din(0) => func_slp_sl_thold_1, + din(1) => func_slp_nsl_thold_1, + din(2) => func_sl_thold_1, + din(3) => func_nsl_thold_1, + din(4) => cfg_sl_thold_1, + din(5) => cfg_slp_sl_thold_1, + din(6) => sg_1, + din(7) => fce_1, + q(0) => func_slp_sl_thold_0, + q(1) => func_slp_nsl_thold_0, + q(2) => func_sl_thold_0, + q(3) => func_nsl_thold_0, + q(4) => cfg_sl_thold_0, + q(5) => cfg_slp_sl_thold_0, + q(6) => sg_0, + q(7) => fce_0); + +perv_lcbor_cfg_sl: tri_lcbor + generic map (expand_type => expand_type) +port map (clkoff_b => clkoff_dc_b, + thold => cfg_sl_thold_0, + sg => sg_0, + act_dis => tidn, + forcee => cfg_sl_force, + thold_b => cfg_sl_thold_0_b); + +bcfg_sl_force <= cfg_sl_force; +bcfg_sl_thold_0_b <= cfg_sl_thold_0_b; +dcfg_sl_force <= cfg_sl_force; +dcfg_sl_thold_0_b <= cfg_sl_thold_0_b; + +perv_lcbor_cfg_slp: tri_lcbor + generic map (expand_type => expand_type) +port map (clkoff_b => clkoff_dc_b, + thold => cfg_slp_sl_thold_0, + sg => sg_0, + act_dis => tidn, + forcee => cfg_slp_sl_force, + thold_b => cfg_slp_sl_thold_0_b); + +bcfg_slp_sl_force <= cfg_slp_sl_force; +bcfg_slp_sl_thold_0_b <= cfg_slp_sl_thold_0_b; + +so_force <= sg_0; +ccfg_so_thold_0_b <= not cfg_sl_thold_0; +bcfg_so_thold_0_b <= not cfg_sl_thold_0; +dcfg_so_thold_0_b <= not cfg_sl_thold_0; +func_so_thold_0_b <= not func_sl_thold_0; + +perv_lcbor_func_sl: tri_lcbor + generic map (expand_type => expand_type) +port map (clkoff_b => clkoff_dc_b, + thold => func_sl_thold_0, + sg => sg_0, + act_dis => tidn, + forcee => func_sl_force, + thold_b => func_sl_thold_0_b); + +perv_lcbor_func_slp_sl: tri_lcbor + generic map (expand_type => expand_type) +port map (clkoff_b => clkoff_dc_b, + thold => func_slp_sl_thold_0, + sg => sg_0, + act_dis => tidn, + forcee => func_slp_sl_force, + thold_b => func_slp_sl_thold_0_b); + +perv_lcbor_func_slp_nsl: tri_lcbor + generic map (expand_type => expand_type) +port map (clkoff_b => clkoff_dc_b, + thold => func_slp_nsl_thold_0, + sg => fce_0, + act_dis => tidn, + forcee => func_slp_nsl_force, + thold_b => func_slp_nsl_thold_0_b); + +perv_lcbor_func_nsl: tri_lcbor + generic map (expand_type => expand_type) +port map (clkoff_b => clkoff_dc_b, + thold => func_nsl_thold_0, + sg => fce_0, + act_dis => tidn, + forcee => func_nsl_force, + thold_b => func_nsl_thold_0_b); + +siv( 0 to MSL-1) <= sov( 1 to MSL-1) & func_scan_rpwr_in(0); +func_scan_rpwr_out(0) <= sov( 0); + +siv(MSL to 2*MSL-1) <= sov(MSL+1 to 2*MSL-1) & func_scan_rpwr_in(1); +func_scan_rpwr_out(1) <= sov(MSL); + +siv(2*MSL to siv'right) <= sov(2*MSL+1 to siv'right) & func_scan_rpwr_in(2); +func_scan_rpwr_out(2) <= sov(2*MSL); + +siv_3(0 to siv_3'right) <= sov_3(1 to siv_3'right) & func_scan_rpwr_in(3); +func_scan_rpwr_out(3) <= sov_3(0); + +siv_ccfg(0 to scan_right_ccfg-1) <= sov_ccfg(1 to scan_right_ccfg-1) & ccfg_scan_rpwr_in(0); +ccfg_scan_rpwr_out <= sov_ccfg(0 to 0); + +siv_bcfg(0 to scan_right_bcfg-1) <= sov_bcfg(1 to scan_right_bcfg-1) & bcfg_scan_rpwr_in(0); +bcfg_scan_rpwr_out <= sov_bcfg(0 to 0); + +siv_dcfg(0 to scan_right_dcfg-1) <= sov_dcfg(1 to scan_right_dcfg-1) & dcfg_scan_rpwr_in(0); +dcfg_scan_rpwr_out <= sov_dcfg(0 to 0); + +ccfg_scan_rpwr_0i_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc, + thold_b => ccfg_so_thold_0_b, + scin(0) => ccfg_scan_in, + scout => ccfg_scan_rpwr_in(0 to 0), + dout => open); +ccfg_scan_rpwr_0o_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc, + thold_b => ccfg_so_thold_0_b, + scin => ccfg_scan_rpwr_out(0 to 0), + scout => ccfg_scan_out_gate(0 to 0), + dout => open); +bcfg_scan_rpwr_0i_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc, + thold_b => bcfg_so_thold_0_b, + scin(0) => bcfg_scan_in, + scout => bcfg_scan_rpwr_in(0 to 0), + dout => open); +bcfg_scan_rpwr_0o_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc, + thold_b => bcfg_so_thold_0_b, + scin => bcfg_scan_rpwr_out(0 to 0), + scout => bcfg_scan_out_gate(0 to 0), + dout => open); +dcfg_scan_rpwr_0i_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc, + thold_b => dcfg_so_thold_0_b, + scin(0) => dcfg_scan_in, + scout => dcfg_scan_rpwr_in(0 to 0), + dout => open); +dcfg_scan_rpwr_0o_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc, + thold_b => dcfg_so_thold_0_b, + scin => dcfg_scan_rpwr_out(0 to 0), + scout => dcfg_scan_out_gate(0 to 0), + dout => open); +func_scan_rpwr_50i_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc, + thold_b => func_so_thold_0_b, + scin => func_scan_in(50 to 50), + scout => func_scan_rpwr_in(0 to 0), + dout => open); +func_scan_rpwr_50o_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc, + thold_b => func_so_thold_0_b, + scin => func_scan_rpwr_out(0 to 0), + scout => func_scan_out_gate(50 to 50), + dout => open); +func_scan_rpwr_51i_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc, + thold_b => func_so_thold_0_b, + scin => func_scan_in(51 to 51), + scout => func_scan_rpwr_in(1 to 1), + dout => open); +func_scan_rpwr_51o_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc, + thold_b => func_so_thold_0_b, + scin => func_scan_rpwr_out(1 to 1), + scout => func_scan_out_gate(51 to 51), + dout => open); +func_scan_rpwr_52i_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc, + thold_b => func_so_thold_0_b, + scin => func_scan_in(52 to 52), + scout => func_scan_rpwr_in(2 to 2), + dout => open); +func_scan_rpwr_52o_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc, + thold_b => func_so_thold_0_b, + scin => func_scan_rpwr_out(2 to 2), + scout => func_scan_out_gate(52 to 52), + dout => open); +func_scan_rpwr_53i_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc, + thold_b => func_so_thold_0_b, + scin => func_scan_in(53 to 53), + scout => func_scan_rpwr2_in(3 to 3), + dout => open); +func_scan_rpwr_53i_2_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc, + thold_b => func_so_thold_0_b, + scin => func_scan_rpwr2_in(3 to 3), + scout => func_scan_rpwr_in(3 to 3), + dout => open); +func_scan_rpwr_53o_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc, + thold_b => func_so_thold_0_b, + scin => func_scan_rpwr_out(3 to 3), + scout => func_scan_out_gate(53 to 53), + dout => open); + +func_scan_out <= gate(func_scan_out_gate,an_ac_scan_dis_dc_b); +ccfg_scan_out <= ccfg_scan_out_gate(0) and an_ac_scan_dis_dc_b; +bcfg_scan_out <= bcfg_scan_out_gate(0) and an_ac_scan_dis_dc_b; +dcfg_scan_out <= dcfg_scan_out_gate(0) and an_ac_scan_dis_dc_b; + + +end architecture xuq_cpl; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_cpl_br.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_cpl_br.vhdl new file mode 100644 index 0000000..41d2fb6 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_cpl_br.vhdl @@ -0,0 +1,358 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee,ibm,support,work,tri; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use support.power_logic_pkg.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use tri.tri_latches_pkg.all; +use work.xuq_pkg.all; + +entity xuq_cpl_br is +generic( + expand_type : integer := 2; + threads : integer := 4; + eff_ifar : integer := 62; + uc_ifar : integer := 21; + regsize : integer := 64); +port( + nclk : in clk_logic; + + d_mode_dc : in std_ulogic; + delay_lclkr_dc : in std_ulogic; + mpw1_dc_b : in std_ulogic; + mpw2_dc_b : in std_ulogic; + func_sl_thold_0_b : in std_ulogic; + func_sl_force : in std_ulogic; + sg_0 : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + rf1_act : in std_ulogic; + ex1_act : in std_ulogic; + + rf1_tid : in std_ulogic_vector(0 to threads-1); + ex1_tid : in std_ulogic_vector(0 to threads-1); + ex1_xu_val : in std_ulogic_vector(0 to threads-1); + + dec_cpl_rf1_ifar : in std_ulogic_vector(62-eff_ifar to 61); + ex1_xu_ifar : out std_ulogic_vector(62-eff_ifar to 61); + + dec_cpl_rf1_pred_taken_cnt : in std_ulogic; + dec_cpl_rf1_instr : in std_ulogic_vector(0 to 31); + + byp_cpl_ex1_cr_bit : in std_ulogic; + spr_lr : in std_ulogic_vector(0 to regsize*threads-1); + spr_ctr : in std_ulogic_vector(0 to regsize*threads-1); + + ex2_br_flush : out std_ulogic_vector(0 to threads-1); + ex2_br_flush_ifar : out std_ulogic_vector(62-eff_ifar to 61); + + ex1_branch : out std_ulogic; + ex1_br_mispred : out std_ulogic; + ex1_br_taken : out std_ulogic; + ex1_br_update : out std_ulogic; + ex1_is_bcctr : out std_ulogic; + ex1_is_bclr : out std_ulogic; + ex1_lr_update : out std_ulogic; + ex1_ctr_dec_update : out std_ulogic; + ex1_instr : out std_ulogic_vector(0 to 31); + + spr_msr_cm : in std_ulogic_vector(0 to threads-1); + + br_debug : out std_ulogic_vector(0 to 11); + + vdd : inout power_logic; + gnd : inout power_logic +); + + +end xuq_cpl_br; +architecture xuq_cpl_br of xuq_cpl_br is + +signal ex1_instr_q : std_ulogic_vector(0 to 31); +signal ex1_is_b_q : std_ulogic; +signal ex1_is_bcctr_q : std_ulogic; +signal ex1_is_bclr_q : std_ulogic; +signal ex1_ctr_ok_q, ex1_ctr_ok_d : std_ulogic; +signal ex1_pred_taken_cnt_q : std_ulogic; +signal ex1_is_branch_cond_q, ex1_is_branch_cond_d : std_ulogic; +signal ex1_xu_ifar_q : std_ulogic_vector(62-eff_ifar to 61); +signal ex2_br_flush_q, ex2_br_flush_d : std_ulogic_vector(0 to threads-1); +signal ex2_br_flush_ifar_q, ex2_br_flush_ifar_d : std_ulogic_vector(62-eff_ifar to 61); +constant ex1_instr_offset : integer := 0; +constant ex1_is_b_offset : integer := ex1_instr_offset + ex1_instr_q'length; +constant ex1_is_bcctr_offset : integer := ex1_is_b_offset + 1; +constant ex1_is_bclr_offset : integer := ex1_is_bcctr_offset + 1; +constant ex1_ctr_ok_offset : integer := ex1_is_bclr_offset + 1; +constant ex1_pred_taken_cnt_offset : integer := ex1_ctr_ok_offset + 1; +constant ex1_is_branch_cond_offset : integer := ex1_pred_taken_cnt_offset + 1; +constant ex1_ifar_offset : integer := ex1_is_branch_cond_offset + 1; +constant ex2_br_flush_offset : integer := ex1_ifar_offset + ex1_xu_ifar_q'length; +constant ex2_br_flush_ifar_offset : integer := ex2_br_flush_offset + ex2_br_flush_q'length; +constant scan_right : integer := ex2_br_flush_ifar_offset + ex2_br_flush_ifar_q'length; +signal siv : std_ulogic_vector(0 to scan_right-1); +signal sov : std_ulogic_vector(0 to scan_right-1); +signal tiup : std_ulogic; +signal rf1_ctr : std_ulogic_vector(64-regsize to 63); +signal rf1_instr : std_ulogic_vector(0 to 31); +signal rf1_msr_cm : std_ulogic; +signal rf1_opcode_is_19 : boolean; +signal rf1_is_b,rf1_is_bc,rf1_is_bcctr,rf1_is_bclr : std_ulogic; +signal rf1_ctr_low_zero, rf1_ctr_hi_zero : std_ulogic; +signal rf1_ctr_zero, rf1_ctr_one, rf1_ctr_one_b : std_ulogic; +signal ex1_br_mispred_int,ex1_bcctr_flush : std_ulogic; +signal ex1_imm,ex1_cia : std_ulogic_vector(62-eff_ifar to 61); +signal ex1_br_t_trgt,ex1_br_nt_trgt,ex1_br_imm_trgt: std_ulogic_vector(62-eff_ifar to 61); +signal ex1_br_flush_ifar : std_ulogic_vector(62-eff_ifar to 61); +signal ex1_lr,ex1_ctr : std_ulogic_vector(64-regsize to 63); +signal ex1_taken : std_ulogic; + +begin + + + +tiup <= '1'; + +rf1_instr <= dec_cpl_rf1_instr; + + +rf1_opcode_is_19 <= rf1_instr( 0 to 5) = "010011"; +rf1_is_b <= '1' when rf1_instr( 0 to 5) = "010010" else '0'; +rf1_is_bc <= '1' when rf1_instr( 0 to 5) = "010000" else '0'; +rf1_is_bcctr <= '1' when rf1_opcode_is_19 and rf1_instr(21 to 30) = "1000010000" else '0'; +rf1_is_bclr <= '1' when rf1_opcode_is_19 and rf1_instr(21 to 30) = "0000010000" else '0'; + +rf1_msr_cm <= or_reduce(spr_msr_cm and rf1_tid); +rf1_ctr <= mux_t(spr_ctr,rf1_tid); +rf1_ctr_low_zero <= not or_reduce(rf1_ctr(32 to 62)); +xuq_cpl_ctr_cmp_0 : if regsize > 32 generate + rf1_ctr_hi_zero <= not or_reduce(rf1_ctr(64-regsize to 31)); +end generate; +xuq_cpl_ctr_cmp_1 : if regsize <= 32 generate + rf1_ctr_hi_zero <= '1'; +end generate; +rf1_ctr_zero <= rf1_ctr_low_zero and (rf1_ctr_hi_zero or not rf1_msr_cm); +rf1_ctr_one <= rf1_ctr_zero and rf1_ctr(63); +rf1_ctr_one_b <= not rf1_ctr_one; + +ex1_ctr_ok_d <= rf1_instr(8) or (rf1_ctr_one_b xor rf1_instr(9)); +ex1_taken <= (ex1_instr_q(6) or (byp_cpl_ex1_cr_bit xnor ex1_instr_q(7))) and ex1_ctr_ok_q; + +ex1_is_branch_cond_d <= rf1_is_bc or rf1_is_bclr or rf1_is_bcctr; + +ex1_cia <= ex1_xu_ifar_q and not (62-eff_ifar to 61=>ex1_instr_q(30)); + +ex1_imm(62-eff_ifar to 37) <= (others=>ex1_imm(38)); + +with ex1_is_b_q select + ex1_imm(38 to 47) <= ex1_instr_q( 6 to 15) when '1', + (38 to 47=>ex1_imm(48)) when others; + +ex1_imm(48 to 61) <= ex1_instr_q(16 to 29); + +ex1_br_nt_trgt <= std_ulogic_vector(unsigned(ex1_xu_ifar_q) + 1); + +ex1_br_imm_trgt <= std_ulogic_vector(unsigned(ex1_cia) + unsigned(ex1_imm)); + +ex1_lr <= mux_t(spr_lr,ex1_tid); +ex1_ctr <= mux_t(spr_ctr,ex1_tid); + +with s2'(ex1_is_bcctr_q & ex1_is_bclr_q) select + ex1_br_t_trgt <= ex1_ctr(64-regsize to 61) when "10", + ex1_lr(64-regsize to 61) when "01", + ex1_br_imm_trgt when others; + +with (ex1_is_b_q or ex1_taken) select + ex1_br_flush_ifar <= ex1_br_t_trgt when '1', + ex1_br_nt_trgt when others; + +ex2_br_flush_ifar_d <= ex1_br_flush_ifar; + +ex1_br_mispred_int <= ex1_is_branch_cond_q and (ex1_taken xor ex1_pred_taken_cnt_q); +ex1_bcctr_flush <= ex1_is_bcctr_q and ex1_taken; + +ex2_br_flush_d <= ex1_xu_val and (0 to threads-1=>(ex1_br_mispred_int or ex1_bcctr_flush)); + +ex2_br_flush_ifar <= ex2_br_flush_ifar_q; +ex2_br_flush <= ex2_br_flush_q; + +ex1_xu_ifar <= ex1_xu_ifar_q; +ex1_branch <= ex1_is_branch_cond_q or ex1_is_b_q; +ex1_br_mispred <= ex1_br_mispred_int; +ex1_br_taken <= (ex1_taken and ex1_is_branch_cond_q) or ex1_is_b_q; +ex1_br_update <= ex1_is_b_q or (ex1_is_branch_cond_q and ex1_taken); +ex1_is_bcctr <= ex1_is_bcctr_q; +ex1_is_bclr <= ex1_is_bclr_q; +ex1_ctr_dec_update <= ex1_is_branch_cond_q and not ex1_instr_q(8); +ex1_lr_update <= (ex1_is_branch_cond_q or ex1_is_b_q) and ex1_instr_q(31); +ex1_instr <= ex1_instr_q; + +mark_unused(ex1_lr(62 to 63)); +mark_unused(ex1_ctr(62 to 63)); + +br_debug <= rf1_msr_cm & rf1_ctr_low_zero & rf1_ctr_hi_zero & rf1_ctr_one & ex1_ctr_ok_q & ex1_taken & ex1_pred_taken_cnt_q & byp_cpl_ex1_cr_bit & ex2_br_flush_q; + +ex1_instr_latch : tri_rlmreg_p + generic map (width => ex1_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_instr_offset to ex1_instr_offset + ex1_instr_q'length-1), + scout => sov(ex1_instr_offset to ex1_instr_offset + ex1_instr_q'length-1), + din => rf1_instr, + dout => ex1_instr_q); +ex1_is_b_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_b_offset), + scout => sov(ex1_is_b_offset), + din => rf1_is_b, + dout => ex1_is_b_q); +ex1_is_bcctr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_bcctr_offset), + scout => sov(ex1_is_bcctr_offset), + din => rf1_is_bcctr, + dout => ex1_is_bcctr_q); +ex1_is_bclr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_bclr_offset), + scout => sov(ex1_is_bclr_offset), + din => rf1_is_bclr, + dout => ex1_is_bclr_q); +ex1_ctr_ok_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_ctr_ok_offset), + scout => sov(ex1_ctr_ok_offset), + din => ex1_ctr_ok_d, + dout => ex1_ctr_ok_q); +ex1_pred_taken_cnt_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_pred_taken_cnt_offset), + scout => sov(ex1_pred_taken_cnt_offset), + din => dec_cpl_rf1_pred_taken_cnt, + dout => ex1_pred_taken_cnt_q); +ex1_is_branch_cond_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_branch_cond_offset), + scout => sov(ex1_is_branch_cond_offset), + din => ex1_is_branch_cond_d, + dout => ex1_is_branch_cond_q); +ex1_ifar_latch : tri_rlmreg_p + generic map (width => ex1_xu_ifar_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_ifar_offset to ex1_ifar_offset + ex1_xu_ifar_q'length-1), + scout => sov(ex1_ifar_offset to ex1_ifar_offset + ex1_xu_ifar_q'length-1), + din => dec_cpl_rf1_ifar, + dout => ex1_xu_ifar_q); +ex2_br_flush_latch : tri_rlmreg_p + generic map (width => ex2_br_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_br_flush_offset to ex2_br_flush_offset + ex2_br_flush_q'length-1), + scout => sov(ex2_br_flush_offset to ex2_br_flush_offset + ex2_br_flush_q'length-1), + din => ex2_br_flush_d, + dout => ex2_br_flush_q); +ex2_br_flush_ifar_latch : tri_rlmreg_p + generic map (width => ex2_br_flush_ifar_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_br_flush_ifar_offset to ex2_br_flush_ifar_offset + ex2_br_flush_ifar_q'length-1), + scout => sov(ex2_br_flush_ifar_offset to ex2_br_flush_ifar_offset + ex2_br_flush_ifar_q'length-1), + din => ex2_br_flush_ifar_d, + dout => ex2_br_flush_ifar_q); + +siv(0 to scan_right-1) <= sov(1 to scan_right-1) & scan_in; +scan_out <= sov(0); + + +end architecture xuq_cpl_br; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_cpl_fctr.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_cpl_fctr.vhdl new file mode 100644 index 0000000..94d890b --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_cpl_fctr.vhdl @@ -0,0 +1,134 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee,ibm,support,tri; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ibm.std_ulogic_function_support.all; +use support.power_logic_pkg.all; +use tri.tri_latches_pkg.all; + +entity xuq_cpl_fctr is +generic( + expand_type : integer := 2; + threads : integer := 4; + clockgate : integer range 0 to 1 := 1; + passthru : integer range 0 to 1 := 1; + delay_width : integer := 4); +port( + nclk : in clk_logic; + + forcee : in std_ulogic; + thold_b : in std_ulogic; + sg : in std_ulogic; + d_mode : in std_ulogic; + delay_lclkr : in std_ulogic; + mpw1_b : in std_ulogic; + mpw2_b : in std_ulogic; + + scin : in std_ulogic; + scout : out std_ulogic; + + din : in std_ulogic_vector(0 to threads-1); + dout : out std_ulogic_vector(0 to threads-1); + delay : in std_ulogic_vector(0 to delay_width-1); + + vd : inout power_logic; + gd : inout power_logic + +); + +-- synopsys translate_off +-- synopsys translate_on + +end xuq_cpl_fctr; +architecture xuq_cpl_fctr of xuq_cpl_fctr is + +type DELAY_ARR is array (0 to threads-1) of std_ulogic_vector(0 to delay_width-1); +subtype s2 is std_ulogic_vector(0 to 1); +signal delay_q, delay_d : DELAY_ARR; +constant delay_offset : integer := 0; +constant scan_right : integer := delay_offset + delay_q(0)'length*threads; +signal siv : std_ulogic_vector(0 to scan_right-1); +signal sov : std_ulogic_vector(0 to scan_right-1); +signal set,zero_b,act : std_ulogic_vector(0 to threads-1); + +begin + +threads_gen : for t in 0 to threads-1 generate +signal delay_m1 : std_ulogic_vector(0 to delay_width-1); +begin + + set(t) <= din(t); + zero_b(t) <= or_reduce(delay_q(t)); + delay_m1 <= std_ulogic_vector(unsigned(delay_q(t)) - 1); + + clockgate_0 : if clockgate = 0 generate + act(t) <= '1'; + + with s2'(set(t) & zero_b(t)) select + delay_d(t) <= delay when "11", + delay when "10", + delay_m1 when "01", + delay_q(t) when others; + end generate; + clockgate_1 : if clockgate = 1 generate + act(t) <= set(t) or zero_b(t); + + with set(t) select + delay_d(t) <= delay when '1', + delay_m1 when others; + end generate; + + passthru_gen_1 : if passthru = 1 generate + dout(t) <= zero_b(t) or din(t); + end generate; + passthru_gen_0 : if passthru = 0 generate + dout(t) <= zero_b(t); + end generate; + + delay_latch : tri_rlmreg_p + generic map (width => delay_q(0)'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vd, gd => gd, + act => act(t), + forcee => forcee, + d_mode => d_mode, delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, mpw2_b => mpw2_b, + thold_b => thold_b, + sg => sg, + scin => siv(delay_offset+delay_q(0)'length*t to delay_offset+delay_q(0)'length*(t+1)-1), + scout => sov(delay_offset+delay_q(0)'length*t to delay_offset+delay_q(0)'length*(t+1)-1), + din => delay_d(t), + dout => delay_q(t)); + +end generate; + +siv(0 to scan_right-1) <= sov(1 to scan_right-1) & scin; +scout <= sov(0); + +end architecture xuq_cpl_fctr; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_cpl_fxub.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_cpl_fxub.vhdl new file mode 100644 index 0000000..1906a6a --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_cpl_fxub.vhdl @@ -0,0 +1,1547 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee,ibm,support,work,tri,clib; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use support.power_logic_pkg.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use tri.tri_latches_pkg.all; +use work.xuq_pkg.all; + +entity xuq_cpl_fxub is +generic( + expand_type : integer := 2; + threads : integer := 4; + eff_ifar : integer := 62; + uc_ifar : integer := 21; + regsize : integer := 64; + hvmode : integer := 1; + regmode : integer := 6; + dc_size : natural := 14; + cl_size : natural := 6; + real_data_add : integer := 42; + fxu_synth : integer := 0; + a2mode : integer := 1); +port( + + nclk : in clk_logic; + vdd : inout power_logic; + gnd : inout power_logic; + vcs : inout power_logic; + + func_scan_in : in std_ulogic_vector(50 to 58); + func_scan_out : out std_ulogic_vector(50 to 58); + an_ac_scan_dis_dc_b : in std_ulogic; + pc_xu_ccflush_dc : in std_ulogic; + clkoff_dc_b : out std_ulogic; + d_mode_dc : out std_ulogic; + delay_lclkr_dc : out std_ulogic_vector(0 to 4); + mpw1_dc_b : out std_ulogic_vector(0 to 4); + mpw2_dc_b : out std_ulogic; + g6t_clkoff_dc_b : out std_ulogic; + g6t_d_mode_dc : out std_ulogic; + g6t_delay_lclkr_dc : out std_ulogic_vector(0 to 4); + g6t_mpw1_dc_b : out std_ulogic_vector(0 to 4); + g6t_mpw2_dc_b : out std_ulogic; + g8t_clkoff_dc_b : out std_ulogic; + g8t_d_mode_dc : out std_ulogic; + g8t_delay_lclkr_dc : out std_ulogic_vector(0 to 4); + g8t_mpw1_dc_b : out std_ulogic_vector(0 to 4); + g8t_mpw2_dc_b : out std_ulogic; + cam_clkoff_dc_b : out std_ulogic; + cam_d_mode_dc : out std_ulogic; + cam_delay_lclkr_dc : out std_ulogic_vector(0 to 4); + cam_act_dis_dc : out std_ulogic; + cam_mpw1_dc_b : out std_ulogic_vector(0 to 4); + cam_mpw2_dc_b : out std_ulogic; + pc_xu_sg_3 : in std_ulogic_vector(0 to 4); + pc_xu_func_sl_thold_3 : in std_ulogic_vector(0 to 4); + pc_xu_func_slp_sl_thold_3 : in std_ulogic_vector(0 to 4); + pc_xu_func_nsl_thold_3 : in std_ulogic; + pc_xu_func_slp_nsl_thold_3 : in std_ulogic; + pc_xu_gptr_sl_thold_3 : in std_ulogic; + pc_xu_abst_sl_thold_3 : in std_ulogic; + pc_xu_abst_slp_sl_thold_3 : in std_ulogic; + pc_xu_regf_sl_thold_3 : in std_ulogic; + pc_xu_regf_slp_sl_thold_3 : in std_ulogic; + pc_xu_time_sl_thold_3 : in std_ulogic; + pc_xu_cfg_sl_thold_3 : in std_ulogic; + pc_xu_cfg_slp_sl_thold_3 : in std_ulogic; + pc_xu_ary_nsl_thold_3 : in std_ulogic; + pc_xu_ary_slp_nsl_thold_3 : in std_ulogic; + pc_xu_repr_sl_thold_3 : in std_ulogic; + pc_xu_bolt_sl_thold_3 : in std_ulogic; + pc_xu_bo_enable_3 : in std_ulogic; + pc_xu_fce_3 : in std_ulogic_vector(0 to 1); + an_ac_scan_diag_dc : in std_ulogic; + sg_2 : out std_ulogic_vector(0 to 3); + fce_2 : out std_ulogic_vector(0 to 1); + func_sl_thold_2 : out std_ulogic_vector(0 to 3); + func_slp_sl_thold_2 : out std_ulogic_vector(0 to 1); + func_nsl_thold_2 : out std_ulogic; + func_slp_nsl_thold_2 : out std_ulogic; + abst_sl_thold_2 : out std_ulogic; + abst_slp_sl_thold_2 : out std_ulogic; + time_sl_thold_2 : out std_ulogic; + gptr_sl_thold_2 : out std_ulogic; + ary_nsl_thold_2 : out std_ulogic; + ary_slp_nsl_thold_2 : out std_ulogic; + repr_sl_thold_2 : out std_ulogic; + cfg_sl_thold_2 : out std_ulogic; + cfg_slp_sl_thold_2 : out std_ulogic; + regf_slp_sl_thold_2 : out std_ulogic; + bolt_sl_thold_2 : out std_ulogic; + bo_enable_2 : out std_ulogic; + gptr_scan_in : in std_ulogic; + gptr_scan_out : out std_ulogic; + + fxa_fxb_rf0_val : in std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_issued : in std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_ucode_val : in std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_act : in std_ulogic; + fxa_fxb_ex1_hold_ctr_flush : in std_ulogic; + fxa_fxb_rf0_instr : in std_ulogic_vector(0 to 31); + fxa_fxb_rf0_tid : in std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_ta_vld : in std_ulogic; + fxa_fxb_rf0_ta : in std_ulogic_vector(0 to 7); + fxa_fxb_rf0_error : in std_ulogic_vector(0 to 2); + fxa_fxb_rf0_match : in std_ulogic; + fxa_fxb_rf0_is_ucode : in std_ulogic; + fxa_fxb_rf0_gshare : in std_ulogic_vector(0 to 3); + fxa_fxb_rf0_ifar : in std_ulogic_vector(62-eff_ifar to 61); + fxa_fxb_rf0_s1_vld : in std_ulogic; + fxa_fxb_rf0_s1 : in std_ulogic_vector(0 to 7); + fxa_fxb_rf0_s2_vld : in std_ulogic; + fxa_fxb_rf0_s2 : in std_ulogic_vector(0 to 7); + fxa_fxb_rf0_s3_vld : in std_ulogic; + fxa_fxb_rf0_s3 : in std_ulogic_vector(0 to 7); + fxa_fxb_rf0_axu_instr_type : in std_ulogic_vector(0 to 2); + fxa_fxb_rf0_axu_ld_or_st : in std_ulogic; + fxa_fxb_rf0_axu_store : in std_ulogic; + fxa_fxb_rf0_axu_ldst_forcealign : in std_ulogic; + fxa_fxb_rf0_axu_ldst_forceexcept : in std_ulogic; + fxa_fxb_rf0_axu_ldst_indexed : in std_ulogic; + fxa_fxb_rf0_axu_ldst_tag : in std_ulogic_vector(0 to 8); + fxa_fxb_rf0_axu_mftgpr : in std_ulogic; + fxa_fxb_rf0_axu_mffgpr : in std_ulogic; + fxa_fxb_rf0_axu_movedp : in std_ulogic; + fxa_fxb_rf0_axu_ldst_size : in std_ulogic_vector(0 to 5); + fxa_fxb_rf0_axu_ldst_update : in std_ulogic; + fxa_fxb_rf0_pred_update : in std_ulogic; + fxa_fxb_rf0_pred_taken_cnt : in std_ulogic_vector(0 to 1); + fxa_fxb_rf0_mc_dep_chk_val : in std_ulogic_vector(0 to threads-1); + fxa_fxb_rf1_mul_val : in std_ulogic; + fxa_fxb_rf1_div_val : in std_ulogic; + fxa_fxb_rf1_div_ctr : in std_ulogic_vector(0 to 7); + fxa_fxb_rf0_xu_epid_instr : in std_ulogic; + fxa_fxb_rf0_axu_is_extload : in std_ulogic; + fxa_fxb_rf0_axu_is_extstore : in std_ulogic; + fxa_fxb_rf0_is_mfocrf : in std_ulogic; + fxa_fxb_rf0_3src_instr : in std_ulogic; + fxa_fxb_rf0_gpr0_zero : in std_ulogic; + fxa_fxb_rf0_use_imm : in std_ulogic; + fxa_fxb_rf1_muldiv_coll : in std_ulogic; + fxa_cpl_ex2_div_coll : in std_ulogic_vector(0 to threads-1); + fxb_fxa_ex7_we0 : out std_ulogic; + fxb_fxa_ex7_wa0 : out std_ulogic_vector(0 to 7); + fxb_fxa_ex7_wd0 : out std_ulogic_vector(64-regsize to 63); + fxa_fxb_rf1_do0 : in std_ulogic_vector(64-regsize to 63); + fxa_fxb_rf1_do1 : in std_ulogic_vector(64-regsize to 63); + fxa_fxb_rf1_do2 : in std_ulogic_vector(64-regsize to 63); + + xu_lsu_rf0_act : out std_ulogic; + xu_lsu_rf1_cache_acc : out std_ulogic; + xu_lsu_rf1_thrd_id : out std_ulogic_vector(0 to threads-1); + xu_lsu_rf1_optype1 : out std_ulogic; + xu_lsu_rf1_optype2 : out std_ulogic; + xu_lsu_rf1_optype4 : out std_ulogic; + xu_lsu_rf1_optype8 : out std_ulogic; + xu_lsu_rf1_optype16 : out std_ulogic; + xu_lsu_rf1_optype32 : out std_ulogic; + xu_lsu_rf1_target_gpr : out std_ulogic_vector(0 to 8); + xu_lsu_rf1_load_instr : out std_ulogic; + xu_lsu_rf1_store_instr : out std_ulogic; + xu_lsu_rf1_dcbf_instr : out std_ulogic; + xu_lsu_rf1_sync_instr : out std_ulogic; + xu_lsu_rf1_mbar_instr : out std_ulogic; + xu_lsu_rf1_l_fld : out std_ulogic_vector(0 to 1); + xu_lsu_rf1_dcbi_instr : out std_ulogic; + xu_lsu_rf1_dcbz_instr : out std_ulogic; + xu_lsu_rf1_dcbt_instr : out std_ulogic; + xu_lsu_rf1_dcbtst_instr : out std_ulogic; + xu_lsu_rf1_th_fld : out std_ulogic_vector(0 to 4); + xu_lsu_rf1_dcbtls_instr : out std_ulogic; + xu_lsu_rf1_dcbtstls_instr : out std_ulogic; + xu_lsu_rf1_dcblc_instr : out std_ulogic; + xu_lsu_rf1_dcbst_instr : out std_ulogic; + xu_lsu_rf1_icbi_instr : out std_ulogic; + xu_lsu_rf1_icblc_instr : out std_ulogic; + xu_lsu_rf1_icbt_instr : out std_ulogic; + xu_lsu_rf1_icbtls_instr : out std_ulogic; + xu_lsu_rf1_tlbsync_instr : out std_ulogic; + xu_lsu_rf1_lock_instr : out std_ulogic; + xu_lsu_rf1_mutex_hint : out std_ulogic; + xu_lsu_rf1_axu_op_val : out std_ulogic; + xu_lsu_rf1_axu_ldst_falign : out std_ulogic; + xu_lsu_rf1_axu_ldst_fexcpt : out std_ulogic; + xu_lsu_ex1_store_data : out std_ulogic_vector(64-(2**regmode) to 63); + xu_lsu_rf1_algebraic : out std_ulogic; + xu_lsu_rf1_byte_rev : out std_ulogic; + xu_lsu_rf1_src_gpr : out std_ulogic; + xu_lsu_rf1_src_axu : out std_ulogic; + xu_lsu_rf1_src_dp : out std_ulogic; + xu_lsu_rf1_targ_gpr : out std_ulogic; + xu_lsu_rf1_targ_axu : out std_ulogic; + xu_lsu_rf1_targ_dp : out std_ulogic; + xu_lsu_ex4_val : out std_ulogic_vector(0 to threads-1); + xu_lsu_ex1_rotsel_ovrd : out std_ulogic_vector(0 to 4); + xu_lsu_rf1_derat_act : out std_ulogic; + xu_lsu_rf1_derat_is_load : out std_ulogic; + xu_lsu_rf1_derat_is_store : out std_ulogic; + xu_lsu_rf1_src0_vld : out std_ulogic; + xu_lsu_rf1_src0_reg : out std_ulogic_vector(0 to 7); + xu_lsu_rf1_src1_vld : out std_ulogic; + xu_lsu_rf1_src1_reg : out std_ulogic_vector(0 to 7); + xu_lsu_rf1_targ_vld : out std_ulogic; + xu_lsu_rf1_targ_reg : out std_ulogic_vector(0 to 7); + xu_bx_ex1_mtdp_val : out std_ulogic; + xu_bx_ex1_mfdp_val : out std_ulogic; + xu_bx_ex1_ipc_thrd : out std_ulogic_vector(0 to 1); + xu_bx_ex2_ipc_ba : out std_ulogic_vector(0 to 4); + xu_bx_ex2_ipc_sz : out std_ulogic_vector(0 to 1); + xu_lsu_rf1_is_touch : out std_ulogic; + xu_lsu_rf1_is_msgsnd : out std_ulogic; + xu_lsu_rf1_dci_instr : out std_ulogic; + xu_lsu_rf1_ici_instr : out std_ulogic; + xu_lsu_rf1_icswx_instr : out std_ulogic; + xu_lsu_rf1_icswx_dot_instr : out std_ulogic; + xu_lsu_rf1_icswx_epid : out std_ulogic; + xu_lsu_rf1_ldawx_instr : out std_ulogic; + xu_lsu_rf1_wclr_instr : out std_ulogic; + xu_lsu_rf1_wchk_instr : out std_ulogic; + xu_lsu_rf1_derat_ra_eq_ea : out std_ulogic; + xu_lsu_rf1_cmd_act : out std_ulogic; + xu_lsu_rf1_data_act : out std_ulogic; + xu_lsu_rf1_mtspr_trace : out std_ulogic; + lsu_xu_ex5_wren : in std_ulogic; + lsu_xu_rel_wren : in std_ulogic; + lsu_xu_rel_ta_gpr : in std_ulogic_vector(0 to 7); + lsu_xu_need_hole : in std_ulogic; + lsu_xu_rot_ex6_data_b : in std_ulogic_vector(64-(2**regmode) to 63); + lsu_xu_rot_rel_data : in std_ulogic_vector(64-(2**regmode) to 63); + xu_lsu_ex4_dvc1_en : out std_ulogic; + xu_lsu_ex4_dvc2_en : out std_ulogic; + lsu_xu_ex2_dvc1_st_cmp : in std_ulogic_vector(8-(2**regmode)/8 to 7); + lsu_xu_ex2_dvc2_st_cmp : in std_ulogic_vector(8-(2**regmode)/8 to 7); + lsu_xu_ex8_dvc1_ld_cmp : in std_ulogic_vector(8-(2**regmode)/8 to 7); + lsu_xu_ex8_dvc2_ld_cmp : in std_ulogic_vector(8-(2**regmode)/8 to 7); + lsu_xu_rel_dvc1_en : in std_ulogic; + lsu_xu_rel_dvc2_en : in std_ulogic; + lsu_xu_rel_dvc_thrd_id : in std_ulogic_vector(0 to 3); + lsu_xu_rel_dvc1_cmp : in std_ulogic_vector(8-(2**regmode)/8 to 7); + lsu_xu_rel_dvc2_cmp : in std_ulogic_vector(8-(2**regmode)/8 to 7); + xu_lsu_ex1_add_src0 : out std_ulogic_vector(64-regsize to 63); + xu_lsu_ex1_add_src1 : out std_ulogic_vector(64-regsize to 63); + + xu_ex1_eff_addr_int : out std_ulogic_vector(64-(dc_size-3) to 63); + + xu_lsu_ex5_set_barr : out std_ulogic_vector(0 to threads-1); + cpl_fxa_ex5_set_barr : out std_ulogic_vector(0 to threads-1); + cpl_iu_set_barr_tid : out std_ulogic_vector(0 to threads-1); + + xu_iu_rf1_val : out std_ulogic_vector(0 to threads-1); + xu_rf1_val : out std_ulogic_vector(0 to threads-1); + xu_rf1_is_tlbre : out std_ulogic; + xu_rf1_is_tlbwe : out std_ulogic; + xu_rf1_is_tlbsx : out std_ulogic; + xu_rf1_is_tlbsrx : out std_ulogic; + xu_rf1_is_tlbilx : out std_ulogic; + xu_rf1_is_tlbivax : out std_ulogic; + xu_rf1_is_eratre : out std_ulogic; + xu_rf1_is_eratwe : out std_ulogic; + xu_rf1_is_eratsx : out std_ulogic; + xu_rf1_is_eratsrx : out std_ulogic; + xu_rf1_is_eratilx : out std_ulogic; + xu_rf1_is_erativax : out std_ulogic; + xu_ex1_is_isync : out std_ulogic; + xu_ex1_is_csync : out std_ulogic; + xu_rf1_ws : out std_ulogic_vector(0 to 1); + xu_rf1_t : out std_ulogic_vector(0 to 2); + xu_ex1_rs_is : out std_ulogic_vector(0 to 8); + xu_ex1_ra_entry : out std_ulogic_vector(7 to 11); + xu_ex1_rb : out std_ulogic_vector(64-(2**regmode) to 51); + xu_ex2_eff_addr : out std_ulogic_vector(64-(2**regmode) to 63); + xu_ex4_rs_data : out std_ulogic_vector(64-(2**regmode) to 63); + lsu_xu_ex4_tlb_data : in std_ulogic_vector(64-(2**regmode) to 63); + iu_xu_ex4_tlb_data : in std_ulogic_vector(64-(2**regmode) to 63); + + xu_mm_derat_epn : out std_ulogic_vector(62-eff_ifar to 51); + + lsu_xu_is2_back_inv : in std_ulogic; + lsu_xu_is2_back_inv_addr : in std_ulogic_vector(64-real_data_add to 63-cl_size); + + mm_xu_mmucr0_0_tlbsel : in std_ulogic_vector(4 to 5); + mm_xu_mmucr0_1_tlbsel : in std_ulogic_vector(4 to 5); + mm_xu_mmucr0_2_tlbsel : in std_ulogic_vector(4 to 5); + mm_xu_mmucr0_3_tlbsel : in std_ulogic_vector(4 to 5); + + xu_mm_rf1_is_tlbsxr : out std_ulogic; + mm_xu_cr0_eq_valid : in std_ulogic_vector(0 to threads-1); + mm_xu_cr0_eq : in std_ulogic_vector(0 to threads-1); + + fu_xu_ex4_cr_val : in std_ulogic_vector(0 to threads-1); + fu_xu_ex4_cr_noflush : in std_ulogic_vector(0 to threads-1); + fu_xu_ex4_cr0 : in std_ulogic_vector(0 to 3); + fu_xu_ex4_cr0_bf : in std_ulogic_vector(0 to 2); + fu_xu_ex4_cr1 : in std_ulogic_vector(0 to 3); + fu_xu_ex4_cr1_bf : in std_ulogic_vector(0 to 2); + fu_xu_ex4_cr2 : in std_ulogic_vector(0 to 3); + fu_xu_ex4_cr2_bf : in std_ulogic_vector(0 to 2); + fu_xu_ex4_cr3 : in std_ulogic_vector(0 to 3); + fu_xu_ex4_cr3_bf : in std_ulogic_vector(0 to 2); + + xu_pc_ram_data : out std_ulogic_vector(64-(2**regmode) to 63); + + xu_iu_ex5_val : out std_ulogic; + xu_iu_ex5_tid : out std_ulogic_vector(0 to threads-1); + xu_iu_ex5_br_update : out std_ulogic; + xu_iu_ex5_br_hist : out std_ulogic_vector(0 to 1); + xu_iu_ex5_bclr : out std_ulogic; + xu_iu_ex5_lk : out std_ulogic; + xu_iu_ex5_bh : out std_ulogic_vector(0 to 1); + xu_iu_ex6_pri : out std_ulogic_vector(0 to 2); + xu_iu_ex6_pri_val : out std_ulogic_vector(0 to 3); + xu_iu_spr_xer : out std_ulogic_vector(0 to 7*threads-1); + xu_iu_slowspr_done : out std_ulogic_vector(0 to threads-1); + xu_iu_need_hole : out std_ulogic; + fxb_fxa_ex6_clear_barrier : out std_ulogic_vector(0 to threads-1); + xu_iu_ex5_gshare : out std_ulogic_vector(0 to 3); + xu_iu_ex5_getNIA : out std_ulogic; + + an_ac_stcx_complete : in std_ulogic_vector(0 to threads-1); + an_ac_stcx_pass : in std_ulogic_vector(0 to threads-1); + + an_ac_back_inv : in std_ulogic; + an_ac_back_inv_addr : in std_ulogic_vector(58 to 63); + an_ac_back_inv_target_bit3 : in std_ulogic; + + slowspr_val_in : in std_ulogic; + slowspr_rw_in : in std_ulogic; + slowspr_etid_in : in std_ulogic_vector(0 to 1); + slowspr_addr_in : in std_ulogic_vector(0 to 9); + slowspr_data_in : in std_ulogic_vector(64-(2**regmode) to 63); + slowspr_done_in : in std_ulogic; + + an_ac_dcr_act : in std_ulogic; + an_ac_dcr_val : in std_ulogic; + an_ac_dcr_read : in std_ulogic; + an_ac_dcr_etid : in std_ulogic_vector(0 to 1); + an_ac_dcr_data : in std_ulogic_vector(64-(2**regmode) to 63); + an_ac_dcr_done : in std_ulogic; + + lsu_xu_ex4_mtdp_cr_status : in std_ulogic; + lsu_xu_ex4_mfdp_cr_status : in std_ulogic; + dec_cpl_ex3_mc_dep_chk_val : in std_ulogic_vector(0 to threads-1); + + lsu_xu_ex4_cr_upd : in std_ulogic; + lsu_xu_ex5_cr_rslt : in std_ulogic; + + dec_spr_ex4_val : out std_ulogic_vector(0 to threads-1); + dec_spr_ex1_epid_instr : out std_ulogic; + mux_spr_ex2_rt : out std_ulogic_vector(64-(2**regmode) to 63); + fxu_spr_ex1_rs0 : out std_ulogic_vector(52 to 63); + fxu_spr_ex1_rs1 : out std_ulogic_vector(54 to 63); + spr_msr_cm : in std_ulogic_vector(0 to threads-1); + spr_dec_spr_xucr0_ssdly : in std_ulogic_vector(0 to 4); + spr_ccr2_en_attn : in std_ulogic; + spr_ccr2_en_ditc : in std_ulogic; + spr_ccr2_en_pc : in std_ulogic; + spr_ccr2_en_icswx : in std_ulogic; + spr_ccr2_en_dcr : in std_ulogic; + spr_dec_rf1_epcr_dgtmi : in std_ulogic_vector(0 to threads-1); + spr_dec_rf1_msr_ucle : in std_ulogic_vector(0 to threads-1); + spr_dec_rf1_msrp_uclep : in std_ulogic_vector(0 to threads-1); + spr_byp_ex4_is_mfxer : in std_ulogic_vector(0 to threads-1); + spr_byp_ex3_spr_rt : in std_ulogic_vector(64-(2**regmode) to 63); + spr_byp_ex4_is_mtxer : in std_ulogic_vector(0 to threads-1); + spr_ccr2_notlb : in std_ulogic; + dec_spr_rf1_val : out std_ulogic_vector(0 to threads-1); + fxu_spr_ex1_rs2 : out std_ulogic_vector(42 to 55); + + fxa_perf_muldiv_in_use : in std_ulogic; + spr_perf_tx_events : in std_ulogic_vector(0 to 8*threads-1); + xu_pc_event_data : out std_ulogic_vector(0 to 7); + + pc_xu_event_bus_enable : in std_ulogic; + pc_xu_event_count_mode : in std_ulogic_vector(0 to 2); + pc_xu_event_mux_ctrls : in std_ulogic_vector(0 to 47); + + pc_xu_trace_bus_enable : in std_ulogic; + pc_xu_instr_trace_mode : in std_ulogic; + pc_xu_instr_trace_tid : in std_ulogic_vector(0 to 1); + xu_lsu_ex2_instr_trace_val : out std_ulogic; + fxu_debug_mux_ctrls : in std_ulogic_vector(0 to 15); + fxu_trigger_data_in : in std_ulogic_vector(0 to 11); + fxu_debug_data_in : in std_ulogic_vector(0 to 87); + fxu_trigger_data_out : out std_ulogic_vector(0 to 11); + fxu_debug_data_out : out std_ulogic_vector(0 to 87); + lsu_xu_data_debug0 : in std_ulogic_vector(0 to 87); + lsu_xu_data_debug1 : in std_ulogic_vector(0 to 87); + lsu_xu_data_debug2 : in std_ulogic_vector(0 to 87); + + spr_msr_gs : in std_ulogic_vector(0 to threads-1); + spr_msr_ds : in std_ulogic_vector(0 to threads-1); + spr_msr_pr : in std_ulogic_vector(0 to threads-1); + spr_dbcr0_dac1 : in std_ulogic_vector(0 to 2*threads-1); + spr_dbcr0_dac2 : in std_ulogic_vector(0 to 2*threads-1); + spr_dbcr0_dac3 : in std_ulogic_vector(0 to 2*threads-1); + spr_dbcr0_dac4 : in std_ulogic_vector(0 to 2*threads-1); + spr_xucr0_clkg_ctl : in std_ulogic_vector(2 to 2); + + ac_tc_debug_trigger : out std_ulogic_vector(0 to threads-1); + + ccfg_scan_in : in std_ulogic; + ccfg_scan_out : out std_ulogic; + bcfg_scan_in : in std_ulogic; + bcfg_scan_out : out std_ulogic; + dcfg_scan_in : in std_ulogic; + dcfg_scan_out : out std_ulogic; + + dec_cpl_rf0_act : in std_ulogic; + dec_cpl_rf0_tid : in std_ulogic_vector(0 to threads-1); + + + fu_xu_rf1_act : in std_ulogic_vector(0 to threads-1); + fu_xu_ex1_ifar : in std_ulogic_vector(0 to eff_ifar*threads-1); + fu_xu_ex2_ifar_val : in std_ulogic_vector(0 to threads-1); + fu_xu_ex2_ifar_issued : in std_ulogic_vector(0 to threads-1); + fu_xu_ex2_instr_type : in std_ulogic_vector(0 to 3*threads-1); + fu_xu_ex2_instr_match : in std_ulogic_vector(0 to threads-1); + fu_xu_ex2_is_ucode : in std_ulogic_vector(0 to threads-1); + + pc_xu_step : in std_ulogic_vector(0 to threads-1); + pc_xu_stop : in std_ulogic_vector(0 to threads-1); + pc_xu_dbg_action : in std_ulogic_vector(0 to 3*threads-1); + pc_xu_force_ude : in std_ulogic_vector(0 to threads-1); + xu_pc_step_done : out std_ulogic_vector(0 to threads-1); + pc_xu_init_reset : in std_ulogic; + + spr_cpl_ext_interrupt : in std_ulogic_vector(0 to threads-1); + spr_cpl_udec_interrupt : in std_ulogic_vector(0 to threads-1); + spr_cpl_perf_interrupt : in std_ulogic_vector(0 to threads-1); + spr_cpl_dec_interrupt : in std_ulogic_vector(0 to threads-1); + spr_cpl_fit_interrupt : in std_ulogic_vector(0 to threads-1); + spr_cpl_crit_interrupt : in std_ulogic_vector(0 to threads-1); + spr_cpl_wdog_interrupt : in std_ulogic_vector(0 to threads-1); + spr_cpl_dbell_interrupt : in std_ulogic_vector(0 to threads-1); + spr_cpl_cdbell_interrupt : in std_ulogic_vector(0 to threads-1); + spr_cpl_gdbell_interrupt : in std_ulogic_vector(0 to threads-1); + spr_cpl_gcdbell_interrupt : in std_ulogic_vector(0 to threads-1); + spr_cpl_gmcdbell_interrupt : in std_ulogic_vector(0 to threads-1); + + cpl_spr_ex5_dbell_taken : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_cdbell_taken : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_gdbell_taken : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_gcdbell_taken : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_gmcdbell_taken : out std_ulogic_vector(0 to threads-1); + + cpl_spr_ex5_act : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_int : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_gint : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_cint : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_mcint : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_nia : out std_ulogic_vector(0 to eff_ifar*threads-1); + cpl_spr_ex5_esr : out std_ulogic_vector(0 to 17*threads-1); + cpl_spr_ex5_mcsr : out std_ulogic_vector(0 to 15*threads-1); + cpl_spr_ex5_dbsr : out std_ulogic_vector(0 to 19*threads-1); + cpl_spr_ex5_dear_save : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_dear_update_saved : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_dear_update : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_dbsr_update : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_esr_update : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_srr0_dec : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_force_gsrr : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_dbsr_ide : out std_ulogic_vector(0 to threads-1); + + spr_cpl_dbsr_ide : in std_ulogic_vector(0 to threads-1); + + mm_xu_local_snoop_reject : in std_ulogic_vector(0 to threads-1); + mm_xu_lru_par_err : in std_ulogic_vector(0 to threads-1); + mm_xu_tlb_par_err : in std_ulogic_vector(0 to threads-1); + mm_xu_tlb_multihit_err : in std_ulogic_vector(0 to threads-1); + lsu_xu_ex3_derat_par_err : in std_ulogic_vector(0 to threads-1); + lsu_xu_ex4_derat_par_err : in std_ulogic_vector(0 to threads-1); + lsu_xu_ex3_derat_multihit_err : in std_ulogic_vector(0 to threads-1); + lsu_xu_ex3_l2_uc_ecc_err : in std_ulogic_vector(0 to threads-1); + lsu_xu_ex3_ddir_par_err : in std_ulogic; + lsu_xu_ex4_n_lsu_ddmh_flush : in std_ulogic_vector(0 to 3); + lsu_xu_ex6_datc_par_err : in std_ulogic; + spr_cpl_external_mchk : in std_ulogic_vector(0 to threads-1); + + xu_pc_err_attention_instr : out std_ulogic_vector(0 to threads-1); + xu_pc_err_nia_miscmpr : out std_ulogic_vector(0 to threads-1); + xu_pc_err_debug_event : out std_ulogic_vector(0 to threads-1); + + lsu_xu_ex3_dsi : in std_ulogic_vector(0 to threads-1); + derat_xu_ex3_dsi : in std_ulogic_vector(0 to threads-1); + spr_cpl_ex3_ct_le : in std_ulogic_vector(0 to threads-1); + spr_cpl_ex3_ct_be : in std_ulogic_vector(0 to threads-1); + + lsu_xu_ex3_align : in std_ulogic_vector(0 to threads-1); + + spr_cpl_ex3_spr_illeg : in std_ulogic; + spr_cpl_ex3_spr_priv : in std_ulogic; + + spr_cpl_ex3_spr_hypv : in std_logic; + + derat_xu_ex3_miss : in std_ulogic_vector(0 to threads-1); + + pc_xu_ram_mode : in std_ulogic; + pc_xu_ram_thread : in std_ulogic_vector(0 to 1); + pc_xu_ram_execute : in std_ulogic; + xu_iu_ram_issue : out std_ulogic_vector(0 to threads-1); + xu_pc_ram_interrupt : out std_ulogic; + xu_pc_ram_done : out std_ulogic; + pc_xu_ram_flush_thread : in std_ulogic; + + cpl_spr_stop : out std_ulogic_vector(0 to threads-1); + xu_pc_stop_dbg_event : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_instr_cpl : out std_ulogic_vector(0 to threads-1); + spr_cpl_quiesce : in std_ulogic_vector(0 to threads-1); + cpl_spr_quiesce : out std_ulogic_vector(0 to threads-1); + spr_cpl_ex2_run_ctl_flush : in std_ulogic_vector(0 to threads-1); + + mm_xu_illeg_instr : in std_ulogic_vector(0 to threads-1); + mm_xu_tlb_miss : in std_ulogic_vector(0 to threads-1); + mm_xu_pt_fault : in std_ulogic_vector(0 to threads-1); + mm_xu_tlb_inelig : in std_ulogic_vector(0 to threads-1); + mm_xu_lrat_miss : in std_ulogic_vector(0 to threads-1); + mm_xu_hv_priv : in std_ulogic_vector(0 to threads-1); + mm_xu_esr_pt : in std_ulogic_vector(0 to threads-1); + mm_xu_esr_data : in std_ulogic_vector(0 to threads-1); + mm_xu_esr_epid : in std_ulogic_vector(0 to threads-1); + mm_xu_esr_st : in std_ulogic_vector(0 to threads-1); + mm_xu_hold_req : in std_ulogic_vector(0 to threads-1); + mm_xu_hold_done : in std_ulogic_vector(0 to threads-1); + xu_mm_hold_ack : out std_ulogic_vector(0 to threads-1); + mm_xu_eratmiss_done : in std_ulogic_vector(0 to threads-1); + mm_xu_ex3_flush_req : in std_ulogic_vector(0 to threads-1); + + lsu_xu_l2_ecc_err_flush : in std_ulogic_vector(0 to threads-1); + lsu_xu_datc_perr_recovery : in std_ulogic; + lsu_xu_ex3_dep_flush : in std_ulogic; + lsu_xu_ex3_n_flush_req : in std_ulogic; + lsu_xu_ex3_ldq_hit_flush : in std_ulogic; + lsu_xu_ex4_ldq_full_flush : in std_ulogic; + derat_xu_ex3_n_flush_req : in std_ulogic_vector(0 to threads-1); + lsu_xu_ex3_inval_align_2ucode : in std_ulogic; + lsu_xu_ex3_attr : in std_ulogic_vector(0 to 8); + lsu_xu_ex3_derat_vf : in std_ulogic; + + fu_xu_ex3_ap_int_req : in std_ulogic_vector(0 to threads-1); + fu_xu_ex3_trap : in std_ulogic_vector(0 to threads-1); + fu_xu_ex3_n_flush : in std_ulogic_vector(0 to threads-1); + fu_xu_ex3_np1_flush : in std_ulogic_vector(0 to threads-1); + fu_xu_ex3_flush2ucode : in std_ulogic_vector(0 to threads-1); + fu_xu_ex2_async_block : in std_ulogic_vector(0 to threads-1); + + xu_iu_ex5_br_taken : out std_ulogic; + xu_iu_ex5_ifar : out std_ulogic_vector(62-eff_ifar to 61); + xu_iu_flush : out std_ulogic_vector(0 to threads-1); + xu_iu_iu0_flush_ifar : out std_ulogic_vector(0 to eff_ifar*threads-1); + xu_iu_uc_flush_ifar : out std_ulogic_vector(0 to uc_ifar*threads-1); + xu_iu_flush_2ucode : out std_ulogic_vector(0 to threads-1); + xu_iu_flush_2ucode_type : out std_ulogic_vector(0 to threads-1); + xu_iu_ucode_restart : out std_ulogic_vector(0 to threads-1); + xu_iu_ex5_ppc_cpl : out std_ulogic_vector(0 to threads-1); + + xu_rf0_flush : out std_ulogic_vector(0 to threads-1); + xu_rf1_flush : out std_ulogic_vector(0 to threads-1); + xu_ex1_flush : out std_ulogic_vector(0 to threads-1); + xu_ex2_flush : out std_ulogic_vector(0 to threads-1); + xu_ex3_flush : out std_ulogic_vector(0 to threads-1); + xu_ex4_flush : out std_ulogic_vector(0 to threads-1); + xu_n_is2_flush : out std_ulogic_vector(0 to threads-1); + xu_n_rf0_flush : out std_ulogic_vector(0 to threads-1); + xu_n_rf1_flush : out std_ulogic_vector(0 to threads-1); + xu_n_ex1_flush : out std_ulogic_vector(0 to threads-1); + xu_n_ex2_flush : out std_ulogic_vector(0 to threads-1); + xu_n_ex3_flush : out std_ulogic_vector(0 to threads-1); + xu_n_ex4_flush : out std_ulogic_vector(0 to threads-1); + xu_n_ex5_flush : out std_ulogic_vector(0 to threads-1); + xu_s_rf1_flush : out std_ulogic_vector(0 to threads-1); + xu_s_ex1_flush : out std_ulogic_vector(0 to threads-1); + xu_s_ex2_flush : out std_ulogic_vector(0 to threads-1); + xu_s_ex3_flush : out std_ulogic_vector(0 to threads-1); + xu_s_ex4_flush : out std_ulogic_vector(0 to threads-1); + xu_s_ex5_flush : out std_ulogic_vector(0 to threads-1); + xu_w_rf1_flush : out std_ulogic_vector(0 to threads-1); + xu_w_ex1_flush : out std_ulogic_vector(0 to threads-1); + xu_w_ex2_flush : out std_ulogic_vector(0 to threads-1); + xu_w_ex3_flush : out std_ulogic_vector(0 to threads-1); + xu_w_ex4_flush : out std_ulogic_vector(0 to threads-1); + xu_w_ex5_flush : out std_ulogic_vector(0 to threads-1); + xu_lsu_ex4_flush_local : out std_ulogic_vector(0 to threads-1); + xu_mm_ex4_flush : out std_ulogic_vector(0 to threads-1); + xu_mm_ex5_flush : out std_ulogic_vector(0 to threads-1); + xu_mm_ierat_flush : out std_ulogic_vector(0 to threads-1); + xu_mm_ierat_miss : out std_ulogic_vector(0 to threads-1); + xu_mm_ex5_perf_itlb : out std_ulogic_vector(0 to threads-1); + xu_mm_ex5_perf_dtlb : out std_ulogic_vector(0 to threads-1); + + + spr_bit_act : in std_ulogic; + spr_cpl_iac1_en : in std_ulogic_vector(0 to threads-1); + spr_cpl_iac2_en : in std_ulogic_vector(0 to threads-1); + spr_cpl_iac3_en : in std_ulogic_vector(0 to threads-1); + spr_cpl_iac4_en : in std_ulogic_vector(0 to threads-1); + spr_dbcr1_iac12m : in std_ulogic_vector(0 to threads-1); + spr_dbcr1_iac34m : in std_ulogic_vector(0 to threads-1); + spr_cpl_fp_precise : in std_ulogic_vector(0 to threads-1); + spr_xucr0_mddp : in std_ulogic; + spr_xucr0_mdcp : in std_ulogic; + spr_msr_de : in std_ulogic_vector(0 to threads-1); + spr_msr_spv : in std_ulogic_vector(0 to threads-1); + spr_msr_fp : in std_ulogic_vector(0 to threads-1); + spr_msr_me : in std_ulogic_vector(0 to threads-1); + spr_msr_ucle : in std_ulogic_vector(0 to threads-1); + spr_msrp_uclep : in std_ulogic_vector(0 to threads-1); + spr_ccr2_ucode_dis : in std_ulogic; + spr_ccr2_ap : in std_ulogic_vector(0 to threads-1); + spr_dbcr0_idm : in std_ulogic_vector(0 to threads-1); + cpl_spr_dbcr0_edm : out std_ulogic_vector(0 to threads-1); + spr_dbcr0_icmp : in std_ulogic_vector(0 to threads-1); + spr_dbcr0_brt : in std_ulogic_vector(0 to threads-1); + spr_dbcr0_trap : in std_ulogic_vector(0 to threads-1); + spr_dbcr0_ret : in std_ulogic_vector(0 to threads-1); + spr_dbcr0_irpt : in std_ulogic_vector(0 to threads-1); + spr_epcr_dsigs : in std_ulogic_vector(0 to threads-1); + spr_epcr_isigs : in std_ulogic_vector(0 to threads-1); + spr_epcr_extgs : in std_ulogic_vector(0 to threads-1); + spr_epcr_dtlbgs : in std_ulogic_vector(0 to threads-1); + spr_epcr_itlbgs : in std_ulogic_vector(0 to threads-1); + spr_xucr4_div_barr_thres : out std_ulogic_vector(0 to 7); + spr_ccr0_we : in std_ulogic_vector(0 to threads-1); + spr_epcr_duvd : in std_ulogic_vector(0 to threads-1); + cpl_msr_gs : out std_ulogic_vector(0 to threads-1); + cpl_msr_pr : out std_ulogic_vector(0 to threads-1); + cpl_msr_fp : out std_ulogic_vector(0 to threads-1); + cpl_msr_spv : out std_ulogic_vector(0 to threads-1); + cpl_ccr2_ap : out std_ulogic_vector(0 to threads-1); + spr_xucr4_mmu_mchk : out std_ulogic; + + xu_lsu_ici : out std_ulogic; + xu_lsu_dci : out std_ulogic; + + spr_cpl_ex3_sprg_ce : in std_ulogic; + spr_cpl_ex3_sprg_ue : in std_ulogic; + iu_xu_ierat_ex2_flush_req : in std_ulogic_vector(0 to threads-1); + iu_xu_ierat_ex3_par_err : in std_ulogic_vector(0 to threads-1); + iu_xu_ierat_ex4_par_err : in std_ulogic_vector(0 to threads-1); + + fu_xu_ex3_regfile_err_det : in std_ulogic_vector(0 to threads-1); + xu_fu_regfile_seq_beg : out std_ulogic; + fu_xu_regfile_seq_end : in std_ulogic; + gpr_cpl_ex3_regfile_err_det : in std_ulogic; + cpl_gpr_regfile_seq_beg : out std_ulogic; + gpr_cpl_regfile_seq_end : in std_ulogic; + xu_pc_err_mcsr_summary : out std_ulogic_vector(0 to threads-1); + xu_pc_err_ditc_overrun : out std_ulogic; + xu_pc_err_local_snoop_reject : out std_ulogic; + xu_pc_err_tlb_lru_parity : out std_ulogic; + xu_pc_err_ext_mchk : out std_ulogic; + xu_pc_err_ierat_multihit : out std_ulogic; + xu_pc_err_derat_multihit : out std_ulogic; + xu_pc_err_tlb_multihit : out std_ulogic; + xu_pc_err_ierat_parity : out std_ulogic; + xu_pc_err_derat_parity : out std_ulogic; + xu_pc_err_tlb_parity : out std_ulogic; + xu_pc_err_mchk_disabled : out std_ulogic; + xu_pc_err_sprg_ue : out std_ulogic_vector(0 to threads-1); + + cpl_debug_mux_ctrls : in std_ulogic_vector(0 to 15); + cpl_debug_data_in : in std_ulogic_vector(0 to 87); + cpl_debug_data_out : out std_ulogic_vector(0 to 87); + cpl_trigger_data_in : in std_ulogic_vector(0 to 11); + cpl_trigger_data_out : out std_ulogic_vector(0 to 11); + fxa_cpl_debug : in std_ulogic_vector(0 to 272) +); + +-- synopsys translate_off + +-- synopsys translate_on +end xuq_cpl_fxub; +architecture xuq_cpl_fxub of xuq_cpl_fxub is + +signal clkoff_dc_b_b : std_ulogic; +signal d_mode_dc_b : std_ulogic; +signal delay_lclkr_dc_b : std_ulogic_vector(0 to 4); +signal mpw1_dc_b_b : std_ulogic_vector(0 to 4); +signal mpw2_dc_b_b : std_ulogic; +signal sg_2_b : std_ulogic_vector(0 to 3); +signal fce_2_b : std_ulogic_vector(0 to 1); +signal func_sl_thold_2_b : std_ulogic_vector(0 to 3); +signal func_slp_sl_thold_2_b : std_ulogic_vector(0 to 1); +signal func_nsl_thold_2_b : std_ulogic; +signal func_slp_nsl_thold_2_b : std_ulogic; +signal cfg_sl_thold_2_b : std_ulogic; +signal cfg_slp_sl_thold_2_b : std_ulogic; + +signal dec_cpl_ex3_mult_coll :std_ulogic; +signal dec_cpl_ex3_axu_instr_type :std_ulogic_vector(0 to 2); +signal dec_cpl_ex3_instr_hypv :std_ulogic; +signal dec_cpl_rf1_ucode_val :std_ulogic_vector(0 to threads-1); +signal dec_cpl_ex2_error :std_ulogic_vector(0 to 2); +signal dec_cpl_ex2_match :std_ulogic; +signal dec_cpl_ex2_is_ucode :std_ulogic; +signal dec_cpl_rf1_ifar :std_ulogic_vector(62-eff_ifar to 61); +signal dec_cpl_ex3_is_any_store :std_ulogic; +signal dec_cpl_ex2_is_any_load_dac :std_ulogic; +signal dec_cpl_ex3_instr_priv :std_ulogic; +signal dec_ex1_epid_instr :std_ulogic; +signal dec_cpl_ex2_illegal_op :std_ulogic; +signal alu_cpl_ex3_trap_val :std_ulogic; +signal mux_cpl_ex4_rt :std_ulogic_vector(64-(2**regmode) to 63); +signal dec_cpl_ex2_is_any_store_dac :std_ulogic; +signal dec_cpl_ex3_tlb_illeg :std_ulogic; +signal dec_cpl_ex3_mtdp_nr :std_ulogic; +signal mux_cpl_slowspr_done :std_ulogic_vector(0 to threads-1); +signal mux_cpl_slowspr_flush :std_ulogic_vector(0 to threads-1); +signal dec_cpl_rf1_val :std_ulogic_vector(0 to threads-1); +signal dec_cpl_rf1_issued :std_ulogic_vector(0 to threads-1); +signal dec_cpl_rf1_instr :std_ulogic_vector(0 to 31); +signal cpl_byp_ex3_spr_rt :std_ulogic_vector(64-(2**regmode) to 63); +signal byp_cpl_ex1_cr_bit :std_ulogic; +signal dec_cpl_rf1_pred_taken_cnt :std_ulogic; +signal dec_cpl_ex1_is_slowspr_wr :std_ulogic; +signal dec_cpl_ex3_ddmh_en :std_ulogic; +signal dec_cpl_ex3_back_inv :std_ulogic; +signal fxu_cpl_ex3_dac1r_cmpr_async :std_ulogic_vector(0 to threads-1); +signal fxu_cpl_ex3_dac2r_cmpr_async :std_ulogic_vector(0 to threads-1); +signal fxu_cpl_ex3_dac1r_cmpr :std_ulogic_vector(0 to threads-1); +signal fxu_cpl_ex3_dac2r_cmpr :std_ulogic_vector(0 to threads-1); +signal fxu_cpl_ex3_dac3r_cmpr :std_ulogic_vector(0 to threads-1); +signal fxu_cpl_ex3_dac4r_cmpr :std_ulogic_vector(0 to threads-1); +signal fxu_cpl_ex3_dac1w_cmpr :std_ulogic_vector(0 to threads-1); +signal fxu_cpl_ex3_dac2w_cmpr :std_ulogic_vector(0 to threads-1); +signal fxu_cpl_ex3_dac3w_cmpr :std_ulogic_vector(0 to threads-1); +signal fxu_cpl_ex3_dac4w_cmpr :std_ulogic_vector(0 to threads-1); +signal xu_ex1_eff_addr :std_ulogic_vector(64-(dc_size-3) to 63); +signal xu_rf0_flush_int :std_ulogic_vector(0 to threads-1); +signal xu_rf1_flush_int :std_ulogic_vector(0 to threads-1); +signal xu_ex1_flush_int :std_ulogic_vector(0 to threads-1); +signal xu_ex2_flush_int :std_ulogic_vector(0 to threads-1); +signal xu_ex3_flush_int :std_ulogic_vector(0 to threads-1); +signal xu_ex4_flush_int :std_ulogic_vector(0 to threads-1); +signal xu_ex5_flush_int :std_ulogic_vector(0 to threads-1); +signal cpl_perf_tx_events :std_ulogic_vector(0 to 75); +signal spr_cpl_async_int :std_ulogic_vector(0 to 3*threads-1); +signal spr_dbcr3_ivc_int :std_ulogic_vector(0 to threads-1); +signal dec_cpl_rf1_instr_trace_val :std_ulogic; +signal dec_cpl_rf1_instr_trace_type :std_ulogic_vector(0 to 1); +signal dec_cpl_ex3_instr_trace_val :std_ulogic; +signal cpl_dec_in_ucode :std_ulogic_vector(0 to threads-1); + + + +begin + +perf_count : for t in 0 to threads-1 generate +spr_cpl_async_int(0+3*t) <= spr_perf_tx_events(5+8*t); +spr_cpl_async_int(1+3*t) <= spr_perf_tx_events(6+8*t); +spr_cpl_async_int(2+3*t) <= spr_perf_tx_events(7+8*t); +end generate; + +clkoff_dc_b <= clkoff_dc_b_b; +d_mode_dc <= d_mode_dc_b; +delay_lclkr_dc <= delay_lclkr_dc_b; +mpw1_dc_b <= mpw1_dc_b_b; +mpw2_dc_b <= mpw2_dc_b_b; +sg_2 <= sg_2_b; +fce_2 <= fce_2_b; +func_sl_thold_2 <= func_sl_thold_2_b; +func_slp_sl_thold_2 <= func_slp_sl_thold_2_b; +func_nsl_thold_2 <= func_nsl_thold_2_b; +func_slp_nsl_thold_2 <= func_slp_nsl_thold_2_b; +cfg_sl_thold_2 <= cfg_sl_thold_2_b; +cfg_slp_sl_thold_2 <= cfg_slp_sl_thold_2_b; + + xuq_fxu_b : entity work.xuq_fxu_b(xuq_fxu_b) + generic map( + expand_type => expand_type, + threads => threads, + eff_ifar => eff_ifar, + regmode => regmode, + regsize => regsize, + a2mode => a2mode, + hvmode => hvmode, + dc_size => dc_size, + cl_size => cl_size, + real_data_add => real_data_add, + fxu_synth => fxu_synth) + port map( + nclk => nclk, + vdd => vdd, + gnd => gnd, + vcs => vcs, + func_scan_in => func_scan_in(54 to 58), + func_scan_out => func_scan_out(54 to 58), + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b, + pc_xu_ccflush_dc => pc_xu_ccflush_dc, + clkoff_dc_b => clkoff_dc_b_b, + d_mode_dc => d_mode_dc_b, + delay_lclkr_dc => delay_lclkr_dc_b, + mpw1_dc_b => mpw1_dc_b_b, + mpw2_dc_b => mpw2_dc_b_b, + g6t_clkoff_dc_b => g6t_clkoff_dc_b, + g6t_d_mode_dc => g6t_d_mode_dc, + g6t_delay_lclkr_dc => g6t_delay_lclkr_dc, + g6t_mpw1_dc_b => g6t_mpw1_dc_b, + g6t_mpw2_dc_b => g6t_mpw2_dc_b, + g8t_clkoff_dc_b => g8t_clkoff_dc_b, + g8t_d_mode_dc => g8t_d_mode_dc, + g8t_delay_lclkr_dc => g8t_delay_lclkr_dc, + g8t_mpw1_dc_b => g8t_mpw1_dc_b, + g8t_mpw2_dc_b => g8t_mpw2_dc_b, + cam_clkoff_dc_b => cam_clkoff_dc_b, + cam_d_mode_dc => cam_d_mode_dc, + cam_delay_lclkr_dc => cam_delay_lclkr_dc, + cam_act_dis_dc => cam_act_dis_dc, + cam_mpw1_dc_b => cam_mpw1_dc_b, + cam_mpw2_dc_b => cam_mpw2_dc_b, + pc_xu_sg_3 => pc_xu_sg_3, + pc_xu_func_sl_thold_3 => pc_xu_func_sl_thold_3, + pc_xu_func_slp_sl_thold_3 => pc_xu_func_slp_sl_thold_3, + pc_xu_func_nsl_thold_3 => pc_xu_func_nsl_thold_3, + pc_xu_func_slp_nsl_thold_3 => pc_xu_func_slp_nsl_thold_3, + pc_xu_gptr_sl_thold_3 => pc_xu_gptr_sl_thold_3, + pc_xu_abst_sl_thold_3 => pc_xu_abst_sl_thold_3, + pc_xu_abst_slp_sl_thold_3 => pc_xu_abst_slp_sl_thold_3, + pc_xu_regf_sl_thold_3 => pc_xu_regf_sl_thold_3, + pc_xu_regf_slp_sl_thold_3 => pc_xu_regf_slp_sl_thold_3, + pc_xu_time_sl_thold_3 => pc_xu_time_sl_thold_3, + pc_xu_cfg_sl_thold_3 => pc_xu_cfg_sl_thold_3, + pc_xu_cfg_slp_sl_thold_3 => pc_xu_cfg_slp_sl_thold_3, + pc_xu_ary_nsl_thold_3 => pc_xu_ary_nsl_thold_3, + pc_xu_ary_slp_nsl_thold_3 => pc_xu_ary_slp_nsl_thold_3, + pc_xu_repr_sl_thold_3 => pc_xu_repr_sl_thold_3, + pc_xu_bolt_sl_thold_3 => pc_xu_bolt_sl_thold_3, + pc_xu_bo_enable_3 => pc_xu_bo_enable_3, + pc_xu_fce_3 => pc_xu_fce_3, + an_ac_scan_diag_dc => an_ac_scan_diag_dc, + sg_2 => sg_2_b, + fce_2 => fce_2_b, + func_sl_thold_2 => func_sl_thold_2_b, + func_slp_sl_thold_2 => func_slp_sl_thold_2_b, + func_nsl_thold_2 => func_nsl_thold_2_b, + func_slp_nsl_thold_2 => func_slp_nsl_thold_2_b, + abst_sl_thold_2 => abst_sl_thold_2, + abst_slp_sl_thold_2 => abst_slp_sl_thold_2, + time_sl_thold_2 => time_sl_thold_2, + gptr_sl_thold_2 => gptr_sl_thold_2, + ary_nsl_thold_2 => ary_nsl_thold_2, + ary_slp_nsl_thold_2 => ary_slp_nsl_thold_2, + repr_sl_thold_2 => repr_sl_thold_2, + cfg_sl_thold_2 => cfg_sl_thold_2_b, + cfg_slp_sl_thold_2 => cfg_slp_sl_thold_2_b, + regf_slp_sl_thold_2 => regf_slp_sl_thold_2, + bolt_sl_thold_2 => bolt_sl_thold_2, + bo_enable_2 => bo_enable_2, + gptr_scan_in => gptr_scan_in, + gptr_scan_out => gptr_scan_out, + fxa_fxb_rf0_val => fxa_fxb_rf0_val, + fxa_fxb_rf0_issued => fxa_fxb_rf0_issued, + fxa_fxb_rf0_ucode_val => fxa_fxb_rf0_ucode_val, + fxa_fxb_rf0_act => fxa_fxb_rf0_act, + fxa_fxb_ex1_hold_ctr_flush => fxa_fxb_ex1_hold_ctr_flush, + fxa_fxb_rf0_instr => fxa_fxb_rf0_instr, + fxa_fxb_rf0_tid => fxa_fxb_rf0_tid, + fxa_fxb_rf0_ta_vld => fxa_fxb_rf0_ta_vld, + fxa_fxb_rf0_ta => fxa_fxb_rf0_ta, + fxa_fxb_rf0_error => fxa_fxb_rf0_error, + fxa_fxb_rf0_match => fxa_fxb_rf0_match, + fxa_fxb_rf0_is_ucode => fxa_fxb_rf0_is_ucode, + fxa_fxb_rf0_gshare => fxa_fxb_rf0_gshare, + fxa_fxb_rf0_ifar => fxa_fxb_rf0_ifar, + fxa_fxb_rf0_s1_vld => fxa_fxb_rf0_s1_vld, + fxa_fxb_rf0_s1 => fxa_fxb_rf0_s1, + fxa_fxb_rf0_s2_vld => fxa_fxb_rf0_s2_vld, + fxa_fxb_rf0_s2 => fxa_fxb_rf0_s2, + fxa_fxb_rf0_s3_vld => fxa_fxb_rf0_s3_vld, + fxa_fxb_rf0_s3 => fxa_fxb_rf0_s3, + fxa_fxb_rf0_axu_instr_type => fxa_fxb_rf0_axu_instr_type, + fxa_fxb_rf0_axu_ld_or_st => fxa_fxb_rf0_axu_ld_or_st, + fxa_fxb_rf0_axu_store => fxa_fxb_rf0_axu_store, + fxa_fxb_rf0_axu_ldst_forcealign => fxa_fxb_rf0_axu_ldst_forcealign, + fxa_fxb_rf0_axu_ldst_forceexcept => fxa_fxb_rf0_axu_ldst_forceexcept, + fxa_fxb_rf0_axu_ldst_indexed => fxa_fxb_rf0_axu_ldst_indexed, + fxa_fxb_rf0_axu_ldst_tag => fxa_fxb_rf0_axu_ldst_tag, + fxa_fxb_rf0_axu_mftgpr => fxa_fxb_rf0_axu_mftgpr, + fxa_fxb_rf0_axu_mffgpr => fxa_fxb_rf0_axu_mffgpr, + fxa_fxb_rf0_axu_movedp => fxa_fxb_rf0_axu_movedp, + fxa_fxb_rf0_axu_ldst_size => fxa_fxb_rf0_axu_ldst_size, + fxa_fxb_rf0_axu_ldst_update => fxa_fxb_rf0_axu_ldst_update, + fxa_fxb_rf0_pred_update => fxa_fxb_rf0_pred_update, + fxa_fxb_rf0_pred_taken_cnt => fxa_fxb_rf0_pred_taken_cnt, + fxa_fxb_rf0_mc_dep_chk_val => fxa_fxb_rf0_mc_dep_chk_val, + fxa_fxb_rf1_mul_val => fxa_fxb_rf1_mul_val, + fxa_fxb_rf1_muldiv_coll => fxa_fxb_rf1_muldiv_coll, + fxa_fxb_rf1_div_val => fxa_fxb_rf1_div_val, + fxa_fxb_rf1_div_ctr => fxa_fxb_rf1_div_ctr, + fxa_fxb_rf0_xu_epid_instr => fxa_fxb_rf0_xu_epid_instr, + fxa_fxb_rf0_axu_is_extload => fxa_fxb_rf0_axu_is_extload, + fxa_fxb_rf0_axu_is_extstore => fxa_fxb_rf0_axu_is_extstore, + fxa_fxb_rf0_is_mfocrf => fxa_fxb_rf0_is_mfocrf, + fxa_fxb_rf0_3src_instr => fxa_fxb_rf0_3src_instr, + fxa_fxb_rf0_gpr0_zero => fxa_fxb_rf0_gpr0_zero, + fxa_fxb_rf0_use_imm => fxa_fxb_rf0_use_imm, + fxb_fxa_ex7_we0 => fxb_fxa_ex7_we0, + fxb_fxa_ex7_wa0 => fxb_fxa_ex7_wa0, + fxb_fxa_ex7_wd0 => fxb_fxa_ex7_wd0, + fxa_fxb_rf1_do0 => fxa_fxb_rf1_do0, + fxa_fxb_rf1_do1 => fxa_fxb_rf1_do1, + fxa_fxb_rf1_do2 => fxa_fxb_rf1_do2, + xu_lsu_rf0_act => xu_lsu_rf0_act, + xu_lsu_rf1_cache_acc => xu_lsu_rf1_cache_acc, + xu_lsu_rf1_thrd_id => xu_lsu_rf1_thrd_id, + xu_lsu_rf1_optype1 => xu_lsu_rf1_optype1, + xu_lsu_rf1_optype2 => xu_lsu_rf1_optype2, + xu_lsu_rf1_optype4 => xu_lsu_rf1_optype4, + xu_lsu_rf1_optype8 => xu_lsu_rf1_optype8, + xu_lsu_rf1_optype16 => xu_lsu_rf1_optype16, + xu_lsu_rf1_optype32 => xu_lsu_rf1_optype32, + xu_lsu_rf1_target_gpr => xu_lsu_rf1_target_gpr, + xu_lsu_rf1_load_instr => xu_lsu_rf1_load_instr, + xu_lsu_rf1_store_instr => xu_lsu_rf1_store_instr, + xu_lsu_rf1_dcbf_instr => xu_lsu_rf1_dcbf_instr, + xu_lsu_rf1_sync_instr => xu_lsu_rf1_sync_instr, + xu_lsu_rf1_mbar_instr => xu_lsu_rf1_mbar_instr, + xu_lsu_rf1_l_fld => xu_lsu_rf1_l_fld, + xu_lsu_rf1_dcbi_instr => xu_lsu_rf1_dcbi_instr, + xu_lsu_rf1_dcbz_instr => xu_lsu_rf1_dcbz_instr, + xu_lsu_rf1_dcbt_instr => xu_lsu_rf1_dcbt_instr, + xu_lsu_rf1_dcbtst_instr => xu_lsu_rf1_dcbtst_instr, + xu_lsu_rf1_th_fld => xu_lsu_rf1_th_fld, + xu_lsu_rf1_dcbtls_instr => xu_lsu_rf1_dcbtls_instr, + xu_lsu_rf1_dcbtstls_instr => xu_lsu_rf1_dcbtstls_instr, + xu_lsu_rf1_dcblc_instr => xu_lsu_rf1_dcblc_instr, + xu_lsu_rf1_dcbst_instr => xu_lsu_rf1_dcbst_instr, + xu_lsu_rf1_icbi_instr => xu_lsu_rf1_icbi_instr, + xu_lsu_rf1_icblc_instr => xu_lsu_rf1_icblc_instr, + xu_lsu_rf1_icbt_instr => xu_lsu_rf1_icbt_instr, + xu_lsu_rf1_icbtls_instr => xu_lsu_rf1_icbtls_instr, + xu_lsu_rf1_tlbsync_instr => xu_lsu_rf1_tlbsync_instr, + xu_lsu_rf1_lock_instr => xu_lsu_rf1_lock_instr, + xu_lsu_rf1_mutex_hint => xu_lsu_rf1_mutex_hint, + xu_lsu_rf1_axu_op_val => xu_lsu_rf1_axu_op_val, + xu_lsu_rf1_axu_ldst_falign => xu_lsu_rf1_axu_ldst_falign, + xu_lsu_rf1_axu_ldst_fexcpt => xu_lsu_rf1_axu_ldst_fexcpt, + xu_lsu_ex1_store_data => xu_lsu_ex1_store_data, + xu_lsu_rf1_algebraic => xu_lsu_rf1_algebraic, + xu_lsu_rf1_byte_rev => xu_lsu_rf1_byte_rev, + xu_lsu_rf1_src_gpr => xu_lsu_rf1_src_gpr, + xu_lsu_rf1_src_axu => xu_lsu_rf1_src_axu, + xu_lsu_rf1_src_dp => xu_lsu_rf1_src_dp, + xu_lsu_rf1_targ_gpr => xu_lsu_rf1_targ_gpr, + xu_lsu_rf1_targ_axu => xu_lsu_rf1_targ_axu, + xu_lsu_rf1_targ_dp => xu_lsu_rf1_targ_dp, + xu_lsu_ex1_rotsel_ovrd => xu_lsu_ex1_rotsel_ovrd, + xu_lsu_rf1_derat_act => xu_lsu_rf1_derat_act, + xu_lsu_rf1_derat_is_load => xu_lsu_rf1_derat_is_load, + xu_lsu_rf1_derat_is_store => xu_lsu_rf1_derat_is_store, + xu_lsu_rf1_src0_vld => xu_lsu_rf1_src0_vld, + xu_lsu_rf1_src0_reg => xu_lsu_rf1_src0_reg, + xu_lsu_rf1_src1_vld => xu_lsu_rf1_src1_vld, + xu_lsu_rf1_src1_reg => xu_lsu_rf1_src1_reg, + xu_lsu_rf1_targ_vld => xu_lsu_rf1_targ_vld, + xu_lsu_rf1_targ_reg => xu_lsu_rf1_targ_reg, + xu_bx_ex1_mtdp_val => xu_bx_ex1_mtdp_val, + xu_bx_ex1_mfdp_val => xu_bx_ex1_mfdp_val, + xu_bx_ex1_ipc_thrd => xu_bx_ex1_ipc_thrd, + xu_bx_ex2_ipc_ba => xu_bx_ex2_ipc_ba, + xu_bx_ex2_ipc_sz => xu_bx_ex2_ipc_sz, + xu_lsu_rf1_is_touch => xu_lsu_rf1_is_touch, + xu_lsu_rf1_is_msgsnd => xu_lsu_rf1_is_msgsnd, + xu_lsu_rf1_dci_instr => xu_lsu_rf1_dci_instr, + xu_lsu_rf1_ici_instr => xu_lsu_rf1_ici_instr, + xu_lsu_rf1_icswx_instr => xu_lsu_rf1_icswx_instr, + xu_lsu_rf1_icswx_dot_instr => xu_lsu_rf1_icswx_dot_instr, + xu_lsu_rf1_icswx_epid => xu_lsu_rf1_icswx_epid, + xu_lsu_rf1_ldawx_instr => xu_lsu_rf1_ldawx_instr, + xu_lsu_rf1_wclr_instr => xu_lsu_rf1_wclr_instr, + xu_lsu_rf1_wchk_instr => xu_lsu_rf1_wchk_instr, + xu_lsu_rf1_derat_ra_eq_ea => xu_lsu_rf1_derat_ra_eq_ea, + xu_lsu_rf1_cmd_act => xu_lsu_rf1_cmd_act, + xu_lsu_rf1_data_act => xu_lsu_rf1_data_act, + xu_lsu_rf1_mtspr_trace => xu_lsu_rf1_mtspr_trace, + lsu_xu_ex5_wren => lsu_xu_ex5_wren, + lsu_xu_rel_wren => lsu_xu_rel_wren, + lsu_xu_rel_ta_gpr => lsu_xu_rel_ta_gpr, + lsu_xu_need_hole => lsu_xu_need_hole, + lsu_xu_rot_ex6_data_b => lsu_xu_rot_ex6_data_b, + lsu_xu_rot_rel_data => lsu_xu_rot_rel_data(64-(2**regmode) to 63), + xu_lsu_ex4_dvc1_en => xu_lsu_ex4_dvc1_en, + xu_lsu_ex4_dvc2_en => xu_lsu_ex4_dvc2_en, + lsu_xu_ex2_dvc1_st_cmp => lsu_xu_ex2_dvc1_st_cmp, + lsu_xu_ex2_dvc2_st_cmp => lsu_xu_ex2_dvc2_st_cmp, + lsu_xu_ex8_dvc1_ld_cmp => lsu_xu_ex8_dvc1_ld_cmp, + lsu_xu_ex8_dvc2_ld_cmp => lsu_xu_ex8_dvc2_ld_cmp, + lsu_xu_rel_dvc1_en => lsu_xu_rel_dvc1_en, + lsu_xu_rel_dvc2_en => lsu_xu_rel_dvc2_en, + lsu_xu_rel_dvc_thrd_id => lsu_xu_rel_dvc_thrd_id, + lsu_xu_rel_dvc1_cmp => lsu_xu_rel_dvc1_cmp, + lsu_xu_rel_dvc2_cmp => lsu_xu_rel_dvc2_cmp, + xu_lsu_ex1_add_src0 => xu_lsu_ex1_add_src0, + xu_lsu_ex1_add_src1 => xu_lsu_ex1_add_src1, + xu_ex1_eff_addr_int => xu_ex1_eff_addr, + xu_iu_rf1_val => xu_iu_rf1_val, + xu_rf1_val => xu_rf1_val, + xu_rf1_is_tlbre => xu_rf1_is_tlbre, + xu_rf1_is_tlbwe => xu_rf1_is_tlbwe, + xu_rf1_is_tlbsx => xu_rf1_is_tlbsx, + xu_rf1_is_tlbsrx => xu_rf1_is_tlbsrx, + xu_rf1_is_tlbilx => xu_rf1_is_tlbilx, + xu_rf1_is_tlbivax => xu_rf1_is_tlbivax, + xu_rf1_is_eratre => xu_rf1_is_eratre, + xu_rf1_is_eratwe => xu_rf1_is_eratwe, + xu_rf1_is_eratsx => xu_rf1_is_eratsx, + xu_rf1_is_eratsrx => xu_rf1_is_eratsrx, + xu_rf1_is_eratilx => xu_rf1_is_eratilx, + xu_rf1_is_erativax => xu_rf1_is_erativax, + xu_ex1_is_isync => xu_ex1_is_isync, + xu_ex1_is_csync => xu_ex1_is_csync, + xu_rf1_ws => xu_rf1_ws, + xu_rf1_t => xu_rf1_t, + xu_ex1_rs_is => xu_ex1_rs_is, + xu_ex1_ra_entry => xu_ex1_ra_entry, + xu_ex1_rb => xu_ex1_rb, + xu_ex2_eff_addr => xu_ex2_eff_addr, + xu_ex4_rs_data => xu_ex4_rs_data, + lsu_xu_ex4_tlb_data => lsu_xu_ex4_tlb_data, + iu_xu_ex4_tlb_data => iu_xu_ex4_tlb_data, + xu_mm_derat_epn => xu_mm_derat_epn, + lsu_xu_is2_back_inv => lsu_xu_is2_back_inv, + lsu_xu_is2_back_inv_addr => lsu_xu_is2_back_inv_addr, + mm_xu_mmucr0_0_tlbsel => mm_xu_mmucr0_0_tlbsel, + mm_xu_mmucr0_1_tlbsel => mm_xu_mmucr0_1_tlbsel, + mm_xu_mmucr0_2_tlbsel => mm_xu_mmucr0_2_tlbsel, + mm_xu_mmucr0_3_tlbsel => mm_xu_mmucr0_3_tlbsel, + xu_mm_rf1_is_tlbsxr => xu_mm_rf1_is_tlbsxr, + mm_xu_cr0_eq_valid => mm_xu_cr0_eq_valid, + mm_xu_cr0_eq => mm_xu_cr0_eq, + fu_xu_ex4_cr_val => fu_xu_ex4_cr_val, + fu_xu_ex4_cr_noflush => fu_xu_ex4_cr_noflush, + fu_xu_ex4_cr0 => fu_xu_ex4_cr0, + fu_xu_ex4_cr0_bf => fu_xu_ex4_cr0_bf, + fu_xu_ex4_cr1 => fu_xu_ex4_cr1, + fu_xu_ex4_cr1_bf => fu_xu_ex4_cr1_bf, + fu_xu_ex4_cr2 => fu_xu_ex4_cr2, + fu_xu_ex4_cr2_bf => fu_xu_ex4_cr2_bf, + fu_xu_ex4_cr3 => fu_xu_ex4_cr3, + fu_xu_ex4_cr3_bf => fu_xu_ex4_cr3_bf, + xu_pc_ram_data => xu_pc_ram_data, + xu_iu_ex5_val => xu_iu_ex5_val, + xu_iu_ex5_tid => xu_iu_ex5_tid, + xu_iu_ex5_br_update => xu_iu_ex5_br_update, + xu_iu_ex5_br_hist => xu_iu_ex5_br_hist, + xu_iu_ex5_bclr => xu_iu_ex5_bclr, + xu_iu_ex5_lk => xu_iu_ex5_lk, + xu_iu_ex5_bh => xu_iu_ex5_bh, + xu_iu_ex6_pri => xu_iu_ex6_pri, + xu_iu_ex6_pri_val => xu_iu_ex6_pri_val, + xu_iu_spr_xer => xu_iu_spr_xer, + xu_iu_slowspr_done => xu_iu_slowspr_done, + xu_iu_need_hole => xu_iu_need_hole, + fxb_fxa_ex6_clear_barrier => fxb_fxa_ex6_clear_barrier, + xu_iu_ex5_gshare => xu_iu_ex5_gshare, + xu_iu_ex5_getNIA => xu_iu_ex5_getNIA, + an_ac_stcx_complete => an_ac_stcx_complete, + an_ac_stcx_pass => an_ac_stcx_pass, + an_ac_back_inv => an_ac_back_inv, + an_ac_back_inv_addr => an_ac_back_inv_addr, + an_ac_back_inv_target_bit3 => an_ac_back_inv_target_bit3, + slowspr_val_in => slowspr_val_in, + slowspr_rw_in => slowspr_rw_in, + slowspr_etid_in => slowspr_etid_in, + slowspr_addr_in => slowspr_addr_in, + slowspr_data_in => slowspr_data_in, + slowspr_done_in => slowspr_done_in, + an_ac_dcr_act => an_ac_dcr_act, + an_ac_dcr_val => an_ac_dcr_val, + an_ac_dcr_read => an_ac_dcr_read, + an_ac_dcr_etid => an_ac_dcr_etid, + an_ac_dcr_data => an_ac_dcr_data, + an_ac_dcr_done => an_ac_dcr_done, + lsu_xu_ex4_mtdp_cr_status => lsu_xu_ex4_mtdp_cr_status, + lsu_xu_ex4_mfdp_cr_status => lsu_xu_ex4_mfdp_cr_status, + lsu_xu_ex4_cr_upd => lsu_xu_ex4_cr_upd, + lsu_xu_ex5_cr_rslt => lsu_xu_ex5_cr_rslt, + dec_cpl_ex3_mult_coll => dec_cpl_ex3_mult_coll, + dec_cpl_ex3_axu_instr_type => dec_cpl_ex3_axu_instr_type, + dec_cpl_ex3_instr_hypv => dec_cpl_ex3_instr_hypv, + dec_cpl_rf1_ucode_val => dec_cpl_rf1_ucode_val, + dec_cpl_ex2_error => dec_cpl_ex2_error, + dec_cpl_ex2_match => dec_cpl_ex2_match, + dec_cpl_ex2_is_ucode => dec_cpl_ex2_is_ucode, + dec_cpl_rf1_ifar => dec_cpl_rf1_ifar, + dec_cpl_ex3_is_any_store => dec_cpl_ex3_is_any_store, + dec_cpl_ex2_is_any_load_dac => dec_cpl_ex2_is_any_load_dac, + dec_cpl_ex3_instr_priv => dec_cpl_ex3_instr_priv, + dec_cpl_ex1_epid_instr => dec_ex1_epid_instr, + dec_cpl_ex2_illegal_op => dec_cpl_ex2_illegal_op, + alu_cpl_ex3_trap_val => alu_cpl_ex3_trap_val, + mux_cpl_ex4_rt => mux_cpl_ex4_rt, + dec_cpl_ex2_is_any_store_dac => dec_cpl_ex2_is_any_store_dac, + dec_cpl_ex3_tlb_illeg => dec_cpl_ex3_tlb_illeg, + dec_cpl_ex3_mtdp_nr => dec_cpl_ex3_mtdp_nr, + mux_cpl_slowspr_done => mux_cpl_slowspr_done, + mux_cpl_slowspr_flush => mux_cpl_slowspr_flush, + dec_cpl_rf1_val => dec_cpl_rf1_val, + dec_cpl_rf1_issued => dec_cpl_rf1_issued, + dec_cpl_rf1_instr => dec_cpl_rf1_instr, + cpl_byp_ex3_spr_rt => cpl_byp_ex3_spr_rt, + byp_cpl_ex1_cr_bit => byp_cpl_ex1_cr_bit, + dec_cpl_rf1_pred_taken_cnt => dec_cpl_rf1_pred_taken_cnt, + dec_cpl_ex1_is_slowspr_wr => dec_cpl_ex1_is_slowspr_wr, + dec_cpl_ex3_ddmh_en => dec_cpl_ex3_ddmh_en, + dec_cpl_ex3_back_inv => dec_cpl_ex3_back_inv, + xu_rf1_flush => xu_rf1_flush_int, + xu_ex1_flush => xu_ex1_flush_int, + xu_ex2_flush => xu_ex2_flush_int, + xu_ex3_flush => xu_ex3_flush_int, + xu_ex4_flush => xu_ex4_flush_int, + xu_ex5_flush => xu_ex5_flush_int, + dec_spr_ex4_val => dec_spr_ex4_val, + mux_spr_ex2_rt => mux_spr_ex2_rt, + fxu_spr_ex1_rs0 => fxu_spr_ex1_rs0, + fxu_spr_ex1_rs1 => fxu_spr_ex1_rs1, + spr_bit_act => spr_bit_act, + spr_msr_cm => spr_msr_cm, + spr_dec_spr_xucr0_ssdly => spr_dec_spr_xucr0_ssdly, + spr_ccr2_en_attn => spr_ccr2_en_attn, + spr_ccr2_en_ditc => spr_ccr2_en_ditc, + spr_ccr2_en_pc => spr_ccr2_en_pc, + spr_ccr2_en_icswx => spr_ccr2_en_icswx, + spr_ccr2_en_dcr => spr_ccr2_en_dcr, + spr_dec_rf1_epcr_dgtmi => spr_dec_rf1_epcr_dgtmi, + spr_dec_rf1_msrp_uclep => spr_dec_rf1_msrp_uclep, + spr_dec_rf1_msr_ucle => spr_dec_rf1_msr_ucle, + spr_byp_ex4_is_mfxer => spr_byp_ex4_is_mfxer, + spr_byp_ex3_spr_rt => spr_byp_ex3_spr_rt, + spr_byp_ex4_is_mtxer => spr_byp_ex4_is_mtxer, + spr_ccr2_notlb => spr_ccr2_notlb, + dec_spr_rf1_val => dec_spr_rf1_val, + fxu_spr_ex1_rs2 => fxu_spr_ex1_rs2, + fxa_perf_muldiv_in_use => fxa_perf_muldiv_in_use, + cpl_perf_tx_events => cpl_perf_tx_events, + spr_perf_tx_events => spr_perf_tx_events, + xu_pc_event_data => xu_pc_event_data, + pc_xu_event_bus_enable => pc_xu_event_bus_enable, + pc_xu_event_count_mode => pc_xu_event_count_mode, + pc_xu_event_mux_ctrls => pc_xu_event_mux_ctrls, + pc_xu_trace_bus_enable => pc_xu_trace_bus_enable, + pc_xu_instr_trace_mode => pc_xu_instr_trace_mode, + pc_xu_instr_trace_tid => pc_xu_instr_trace_tid, + xu_lsu_ex2_instr_trace_val => xu_lsu_ex2_instr_trace_val, + dec_cpl_rf1_instr_trace_val => dec_cpl_rf1_instr_trace_val, + dec_cpl_rf1_instr_trace_type => dec_cpl_rf1_instr_trace_type, + dec_cpl_ex3_instr_trace_val => dec_cpl_ex3_instr_trace_val, + cpl_dec_in_ucode => cpl_dec_in_ucode, + lsu_xu_data_debug0 => lsu_xu_data_debug0, + lsu_xu_data_debug1 => lsu_xu_data_debug1, + lsu_xu_data_debug2 => lsu_xu_data_debug2, + fxu_debug_mux_ctrls => fxu_debug_mux_ctrls, + fxu_debug_data_in => fxu_debug_data_in, + fxu_trigger_data_in => fxu_trigger_data_in, + fxu_debug_data_out => fxu_debug_data_out, + fxu_trigger_data_out => fxu_trigger_data_out, + fxu_cpl_ex3_dac1r_cmpr_async => fxu_cpl_ex3_dac1r_cmpr_async, + fxu_cpl_ex3_dac2r_cmpr_async => fxu_cpl_ex3_dac2r_cmpr_async, + fxu_cpl_ex3_dac1r_cmpr => fxu_cpl_ex3_dac1r_cmpr, + fxu_cpl_ex3_dac2r_cmpr => fxu_cpl_ex3_dac2r_cmpr, + fxu_cpl_ex3_dac3r_cmpr => fxu_cpl_ex3_dac3r_cmpr, + fxu_cpl_ex3_dac4r_cmpr => fxu_cpl_ex3_dac4r_cmpr, + fxu_cpl_ex3_dac1w_cmpr => fxu_cpl_ex3_dac1w_cmpr, + fxu_cpl_ex3_dac2w_cmpr => fxu_cpl_ex3_dac2w_cmpr, + fxu_cpl_ex3_dac3w_cmpr => fxu_cpl_ex3_dac3w_cmpr, + fxu_cpl_ex3_dac4w_cmpr => fxu_cpl_ex3_dac4w_cmpr, + spr_msr_gs => spr_msr_gs, + spr_msr_ds => spr_msr_ds, + spr_msr_pr => spr_msr_pr, + spr_dbcr0_dac1 => spr_dbcr0_dac1, + spr_dbcr0_dac2 => spr_dbcr0_dac2, + spr_dbcr0_dac3 => spr_dbcr0_dac3, + spr_dbcr0_dac4 => spr_dbcr0_dac4, + spr_dbcr3_ivc => spr_dbcr3_ivc_int, + spr_xucr0_clkg_ctl => spr_xucr0_clkg_ctl(2 to 2) + ); + + xu_cpl : entity work.xuq_cpl(xuq_cpl) + generic map( + expand_type => expand_type, + threads => threads, + regsize => regsize, + eff_ifar => eff_ifar) + port map( + nclk => nclk, + ac_tc_debug_trigger => ac_tc_debug_trigger, + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b, + pc_xu_ccflush_dc => pc_xu_ccflush_dc, + clkoff_dc_b => clkoff_dc_b_b, + d_mode_dc => d_mode_dc_b, + delay_lclkr_dc => delay_lclkr_dc_b(3), + mpw1_dc_b => mpw1_dc_b_b(3), + mpw2_dc_b => mpw2_dc_b_b, + func_slp_sl_thold_2 => func_slp_sl_thold_2_b(0), + func_slp_nsl_thold_2 => func_slp_nsl_thold_2_b, + func_sl_thold_2 => func_sl_thold_2_b(0), + func_nsl_thold_2 => func_nsl_thold_2_b, + cfg_sl_thold_2 => cfg_sl_thold_2_b, + cfg_slp_sl_thold_2 => cfg_slp_sl_thold_2_b, + sg_2 => sg_2_b(0), + fce_2 => fce_2_b(0), + func_scan_in => func_scan_in(50 to 53), + func_scan_out => func_scan_out(50 to 53), + bcfg_scan_in => bcfg_scan_in, + bcfg_scan_out => bcfg_scan_out, + ccfg_scan_in => ccfg_scan_in, + ccfg_scan_out => ccfg_scan_out, + dcfg_scan_in => dcfg_scan_in, + dcfg_scan_out => dcfg_scan_out, + + dec_cpl_rf0_act => dec_cpl_rf0_act, + dec_cpl_rf0_tid => dec_cpl_rf0_tid, + dec_cpl_rf1_val => dec_cpl_rf1_val, + dec_cpl_rf1_issued => dec_cpl_rf1_issued, + fu_xu_rf1_act => fu_xu_rf1_act, + fu_xu_ex2_ifar_val => fu_xu_ex2_ifar_val, + fu_xu_ex2_ifar_issued => fu_xu_ex2_ifar_issued, + fu_xu_ex1_ifar => fu_xu_ex1_ifar, + fu_xu_ex2_instr_type => fu_xu_ex2_instr_type, + fu_xu_ex2_instr_match => fu_xu_ex2_instr_match, + fu_xu_ex2_is_ucode => fu_xu_ex2_is_ucode, + fu_xu_ex3_trap => fu_xu_ex3_trap, + fu_xu_ex3_ap_int_req => fu_xu_ex3_ap_int_req, + pc_xu_step => pc_xu_step, + pc_xu_stop => pc_xu_stop, + pc_xu_dbg_action => pc_xu_dbg_action, + pc_xu_force_ude => pc_xu_force_ude, + xu_pc_step_done => xu_pc_step_done, + byp_cpl_ex1_cr_bit => byp_cpl_ex1_cr_bit, + dec_cpl_rf1_pred_taken_cnt => dec_cpl_rf1_pred_taken_cnt, + dec_cpl_rf1_instr => dec_cpl_rf1_instr, + dec_cpl_ex2_error => dec_cpl_ex2_error, + dec_cpl_ex2_match => dec_cpl_ex2_match, + dec_cpl_ex2_is_ucode => dec_cpl_ex2_is_ucode, + dec_cpl_ex3_is_any_store => dec_cpl_ex3_is_any_store, + dec_cpl_ex2_is_any_store_dac => dec_cpl_ex2_is_any_store_dac, + dec_cpl_ex2_is_any_load_dac => dec_cpl_ex2_is_any_load_dac, + dec_cpl_ex3_instr_priv => dec_cpl_ex3_instr_priv, + dec_cpl_ex1_epid_instr => dec_ex1_epid_instr, + dec_cpl_ex2_illegal_op => dec_cpl_ex2_illegal_op, + dec_cpl_ex3_mult_coll => dec_cpl_ex3_mult_coll, + dec_cpl_ex3_tlb_illeg => dec_cpl_ex3_tlb_illeg, + dec_cpl_ex3_axu_instr_type => dec_cpl_ex3_axu_instr_type, + dec_cpl_ex3_mc_dep_chk_val => dec_cpl_ex3_mc_dep_chk_val, + dec_cpl_rf1_ucode_val => dec_cpl_rf1_ucode_val, + dec_cpl_ex3_mtdp_nr => dec_cpl_ex3_mtdp_nr, + lsu_xu_ex4_mtdp_cr_status => lsu_xu_ex4_mtdp_cr_status, + dec_cpl_ex3_instr_hypv => dec_cpl_ex3_instr_hypv, + fxa_cpl_ex2_div_coll => fxa_cpl_ex2_div_coll, + spr_cpl_ext_interrupt => spr_cpl_ext_interrupt, + spr_cpl_dec_interrupt => spr_cpl_dec_interrupt, + spr_cpl_udec_interrupt => spr_cpl_udec_interrupt, + spr_cpl_perf_interrupt => spr_cpl_perf_interrupt, + spr_cpl_fit_interrupt => spr_cpl_fit_interrupt, + spr_cpl_crit_interrupt => spr_cpl_crit_interrupt, + spr_cpl_wdog_interrupt => spr_cpl_wdog_interrupt, + spr_cpl_dbell_interrupt => spr_cpl_dbell_interrupt, + spr_cpl_cdbell_interrupt => spr_cpl_cdbell_interrupt, + spr_cpl_gdbell_interrupt => spr_cpl_gdbell_interrupt, + spr_cpl_gcdbell_interrupt => spr_cpl_gcdbell_interrupt, + spr_cpl_gmcdbell_interrupt => spr_cpl_gmcdbell_interrupt, + cpl_spr_ex5_dbell_taken => cpl_spr_ex5_dbell_taken, + cpl_spr_ex5_cdbell_taken => cpl_spr_ex5_cdbell_taken, + cpl_spr_ex5_gdbell_taken => cpl_spr_ex5_gdbell_taken, + cpl_spr_ex5_gcdbell_taken => cpl_spr_ex5_gcdbell_taken, + cpl_spr_ex5_gmcdbell_taken => cpl_spr_ex5_gmcdbell_taken, + dec_cpl_rf1_ifar => dec_cpl_rf1_ifar, + fxu_cpl_ex3_dac1r_cmpr_async => fxu_cpl_ex3_dac1r_cmpr_async, + fxu_cpl_ex3_dac2r_cmpr_async => fxu_cpl_ex3_dac2r_cmpr_async, + fxu_cpl_ex3_dac1r_cmpr => fxu_cpl_ex3_dac1r_cmpr, + fxu_cpl_ex3_dac2r_cmpr => fxu_cpl_ex3_dac2r_cmpr, + fxu_cpl_ex3_dac3r_cmpr => fxu_cpl_ex3_dac3r_cmpr, + fxu_cpl_ex3_dac4r_cmpr => fxu_cpl_ex3_dac4r_cmpr, + fxu_cpl_ex3_dac1w_cmpr => fxu_cpl_ex3_dac1w_cmpr, + fxu_cpl_ex3_dac2w_cmpr => fxu_cpl_ex3_dac2w_cmpr, + fxu_cpl_ex3_dac3w_cmpr => fxu_cpl_ex3_dac3w_cmpr, + fxu_cpl_ex3_dac4w_cmpr => fxu_cpl_ex3_dac4w_cmpr, + cpl_spr_ex5_act => cpl_spr_ex5_act, + cpl_spr_ex5_int => cpl_spr_ex5_int, + cpl_spr_ex5_gint => cpl_spr_ex5_gint, + cpl_spr_ex5_cint => cpl_spr_ex5_cint, + cpl_spr_ex5_mcint => cpl_spr_ex5_mcint, + cpl_spr_ex5_nia => cpl_spr_ex5_nia, + cpl_spr_ex5_esr => cpl_spr_ex5_esr, + cpl_spr_ex5_mcsr => cpl_spr_ex5_mcsr, + cpl_spr_ex5_dbsr => cpl_spr_ex5_dbsr, + cpl_spr_ex5_dear_save => cpl_spr_ex5_dear_save, + cpl_spr_ex5_dear_update_saved => cpl_spr_ex5_dear_update_saved, + cpl_spr_ex5_dear_update => cpl_spr_ex5_dear_update, + cpl_spr_ex5_dbsr_update => cpl_spr_ex5_dbsr_update, + cpl_spr_ex5_esr_update => cpl_spr_ex5_esr_update, + cpl_spr_ex5_srr0_dec => cpl_spr_ex5_srr0_dec, + cpl_spr_ex5_force_gsrr => cpl_spr_ex5_force_gsrr, + cpl_spr_ex5_dbsr_ide => cpl_spr_ex5_dbsr_ide, + spr_cpl_dbsr_ide => spr_cpl_dbsr_ide, + alu_cpl_ex1_eff_addr => xu_ex1_eff_addr(62 to 63), + mm_xu_local_snoop_reject => mm_xu_local_snoop_reject, + mm_xu_lru_par_err => mm_xu_lru_par_err, + mm_xu_tlb_par_err => mm_xu_tlb_par_err, + mm_xu_tlb_multihit_err => mm_xu_tlb_multihit_err, + lsu_xu_ex3_derat_par_err => lsu_xu_ex3_derat_par_err, + lsu_xu_ex4_derat_par_err => lsu_xu_ex4_derat_par_err, + lsu_xu_ex3_derat_multihit_err => lsu_xu_ex3_derat_multihit_err, + lsu_xu_ex3_l2_uc_ecc_err => lsu_xu_ex3_l2_uc_ecc_err, + lsu_xu_ex3_ddir_par_err => lsu_xu_ex3_ddir_par_err, + lsu_xu_ex4_n_lsu_ddmh_flush => lsu_xu_ex4_n_lsu_ddmh_flush, + lsu_xu_ex6_datc_par_err => lsu_xu_ex6_datc_par_err, + spr_cpl_external_mchk => spr_cpl_external_mchk, + xu_pc_err_attention_instr => xu_pc_err_attention_instr, + xu_pc_err_nia_miscmpr => xu_pc_err_nia_miscmpr, + xu_pc_err_debug_event => xu_pc_err_debug_event, + derat_xu_ex3_dsi => derat_xu_ex3_dsi, + lsu_xu_ex3_dsi => lsu_xu_ex3_dsi, + spr_cpl_ex3_ct_le => spr_cpl_ex3_ct_le, + spr_cpl_ex3_ct_be => spr_cpl_ex3_ct_be, + lsu_xu_ex3_align => lsu_xu_ex3_align, + spr_cpl_ex3_spr_illeg => spr_cpl_ex3_spr_illeg, + spr_cpl_ex3_spr_priv => spr_cpl_ex3_spr_priv, + alu_cpl_ex3_trap_val => alu_cpl_ex3_trap_val, + spr_cpl_ex3_spr_hypv => spr_cpl_ex3_spr_hypv, + derat_xu_ex3_miss => derat_xu_ex3_miss, + mm_xu_illeg_instr => mm_xu_illeg_instr, + mm_xu_tlb_miss => mm_xu_tlb_miss, + pc_xu_ram_mode => pc_xu_ram_mode, + pc_xu_ram_thread => pc_xu_ram_thread, + pc_xu_ram_execute => pc_xu_ram_execute, + pc_xu_ram_flush_thread => pc_xu_ram_flush_thread, + xu_iu_ram_issue => xu_iu_ram_issue, + xu_pc_ram_interrupt => xu_pc_ram_interrupt, + xu_pc_ram_done => xu_pc_ram_done, + pc_xu_init_reset => pc_xu_init_reset, + cpl_spr_stop => cpl_spr_stop, + cpl_spr_ex5_instr_cpl => cpl_spr_ex5_instr_cpl, + xu_pc_stop_dbg_event => xu_pc_stop_dbg_event, + spr_cpl_quiesce => spr_cpl_quiesce, + cpl_spr_quiesce => cpl_spr_quiesce, + spr_cpl_ex2_run_ctl_flush => spr_cpl_ex2_run_ctl_flush, + mm_xu_pt_fault => mm_xu_pt_fault, + mm_xu_tlb_inelig => mm_xu_tlb_inelig, + mm_xu_lrat_miss => mm_xu_lrat_miss, + mm_xu_hv_priv => mm_xu_hv_priv, + mm_xu_esr_pt => mm_xu_esr_pt, + mm_xu_esr_data => mm_xu_esr_data, + mm_xu_esr_epid => mm_xu_esr_epid, + mm_xu_esr_st => mm_xu_esr_st, + mm_xu_hold_req => mm_xu_hold_req, + mm_xu_hold_done => mm_xu_hold_done, + xu_mm_hold_ack => xu_mm_hold_ack, + mm_xu_eratmiss_done => mm_xu_eratmiss_done, + mm_xu_ex3_flush_req => mm_xu_ex3_flush_req, + lsu_xu_l2_ecc_err_flush => lsu_xu_l2_ecc_err_flush, + lsu_xu_datc_perr_recovery => lsu_xu_datc_perr_recovery, + lsu_xu_ex3_dep_flush => lsu_xu_ex3_dep_flush, + lsu_xu_ex3_n_flush_req => lsu_xu_ex3_n_flush_req, + lsu_xu_ex3_ldq_hit_flush => lsu_xu_ex3_ldq_hit_flush, + lsu_xu_ex4_ldq_full_flush => lsu_xu_ex4_ldq_full_flush, + derat_xu_ex3_n_flush_req => derat_xu_ex3_n_flush_req, + lsu_xu_ex3_inval_align_2ucode => lsu_xu_ex3_inval_align_2ucode, + lsu_xu_ex3_attr => lsu_xu_ex3_attr, + lsu_xu_ex3_derat_vf => lsu_xu_ex3_derat_vf, + fu_xu_ex3_n_flush => fu_xu_ex3_n_flush, + fu_xu_ex3_np1_flush => fu_xu_ex3_np1_flush, + fu_xu_ex3_flush2ucode => fu_xu_ex3_flush2ucode, + fu_xu_ex2_async_block => fu_xu_ex2_async_block, + xu_iu_ex5_br_taken => xu_iu_ex5_br_taken, + xu_iu_ex5_ifar => xu_iu_ex5_ifar, + xu_iu_flush => xu_iu_flush, + xu_iu_iu0_flush_ifar => xu_iu_iu0_flush_ifar, + xu_iu_uc_flush_ifar => xu_iu_uc_flush_ifar, + xu_iu_flush_2ucode => xu_iu_flush_2ucode, + xu_iu_flush_2ucode_type => xu_iu_flush_2ucode_type, + xu_iu_ucode_restart => xu_iu_ucode_restart, + xu_iu_ex5_ppc_cpl => xu_iu_ex5_ppc_cpl, + xu_n_is2_flush => xu_n_is2_flush, + xu_n_rf0_flush => xu_n_rf0_flush, + xu_n_rf1_flush => xu_n_rf1_flush, + xu_n_ex1_flush => xu_n_ex1_flush, + xu_n_ex2_flush => xu_n_ex2_flush, + xu_n_ex3_flush => xu_n_ex3_flush, + xu_n_ex4_flush => xu_n_ex4_flush, + xu_n_ex5_flush => xu_n_ex5_flush, + xu_s_rf1_flush => xu_s_rf1_flush, + xu_s_ex1_flush => xu_s_ex1_flush, + xu_s_ex2_flush => xu_s_ex2_flush, + xu_s_ex3_flush => xu_s_ex3_flush, + xu_s_ex4_flush => xu_s_ex4_flush, + xu_s_ex5_flush => xu_s_ex5_flush, + xu_w_rf1_flush => xu_w_rf1_flush, + xu_w_ex1_flush => xu_w_ex1_flush, + xu_w_ex2_flush => xu_w_ex2_flush, + xu_w_ex3_flush => xu_w_ex3_flush, + xu_w_ex4_flush => xu_w_ex4_flush, + xu_w_ex5_flush => xu_w_ex5_flush, + xu_rf0_flush => xu_rf0_flush_int, + xu_rf1_flush => xu_rf1_flush_int, + xu_ex1_flush => xu_ex1_flush_int, + xu_ex2_flush => xu_ex2_flush_int, + xu_ex3_flush => xu_ex3_flush_int, + xu_ex4_flush => xu_ex4_flush_int, + xu_ex5_flush => xu_ex5_flush_int, + xu_mm_ex4_flush => xu_mm_ex4_flush, + xu_mm_ex5_flush => xu_mm_ex5_flush, + xu_mm_ierat_flush => xu_mm_ierat_flush, + xu_mm_ierat_miss => xu_mm_ierat_miss, + xu_mm_ex5_perf_itlb => xu_mm_ex5_perf_itlb, + xu_mm_ex5_perf_dtlb => xu_mm_ex5_perf_dtlb, + xu_lsu_ex4_flush_local => xu_lsu_ex4_flush_local, + xu_lsu_dci => xu_lsu_dci, + xu_lsu_ici => xu_lsu_ici, + xu_lsu_ex4_val => xu_lsu_ex4_val, + spr_cpl_ex3_sprg_ue => spr_cpl_ex3_sprg_ue, + spr_cpl_ex3_sprg_ce => spr_cpl_ex3_sprg_ce, + iu_xu_ierat_ex2_flush_req => iu_xu_ierat_ex2_flush_req, + iu_xu_ierat_ex3_par_err => iu_xu_ierat_ex3_par_err, + iu_xu_ierat_ex4_par_err => iu_xu_ierat_ex4_par_err, + fu_xu_ex3_regfile_err_det => fu_xu_ex3_regfile_err_det, + xu_fu_regfile_seq_beg => xu_fu_regfile_seq_beg, + fu_xu_regfile_seq_end => fu_xu_regfile_seq_end, + gpr_cpl_ex3_regfile_err_det => gpr_cpl_ex3_regfile_err_det, + cpl_gpr_regfile_seq_beg => cpl_gpr_regfile_seq_beg, + gpr_cpl_regfile_seq_end => gpr_cpl_regfile_seq_end, + xu_pc_err_mcsr_summary => xu_pc_err_mcsr_summary, + xu_pc_err_ditc_overrun => xu_pc_err_ditc_overrun, + xu_pc_err_local_snoop_reject => xu_pc_err_local_snoop_reject, + xu_pc_err_tlb_lru_parity => xu_pc_err_tlb_lru_parity, + xu_pc_err_ext_mchk => xu_pc_err_ext_mchk, + xu_pc_err_ierat_multihit => xu_pc_err_ierat_multihit, + xu_pc_err_derat_multihit => xu_pc_err_derat_multihit, + xu_pc_err_tlb_multihit => xu_pc_err_tlb_multihit, + xu_pc_err_ierat_parity => xu_pc_err_ierat_parity, + xu_pc_err_derat_parity => xu_pc_err_derat_parity, + xu_pc_err_mchk_disabled => xu_pc_err_mchk_disabled, + xu_pc_err_tlb_parity => xu_pc_err_tlb_parity, + xu_pc_err_sprg_ue => xu_pc_err_sprg_ue, + cpl_perf_tx_events => cpl_perf_tx_events, + spr_cpl_async_int => spr_cpl_async_int, + xu_lsu_ex5_set_barr => xu_lsu_ex5_set_barr, + cpl_fxa_ex5_set_barr => cpl_fxa_ex5_set_barr, + cpl_iu_set_barr_tid => cpl_iu_set_barr_tid, + cpl_byp_ex3_spr_rt => cpl_byp_ex3_spr_rt, + mux_cpl_ex4_rt => mux_cpl_ex4_rt, + spr_bit_act => spr_bit_act, + spr_cpl_iac1_en => spr_cpl_iac1_en, + spr_cpl_iac2_en => spr_cpl_iac2_en, + spr_cpl_iac3_en => spr_cpl_iac3_en, + spr_cpl_iac4_en => spr_cpl_iac4_en, + spr_dbcr1_iac12m => spr_dbcr1_iac12m, + spr_dbcr1_iac34m => spr_dbcr1_iac34m, + spr_cpl_fp_precise => spr_cpl_fp_precise, + spr_xucr0_mddp => spr_xucr0_mddp, + spr_xucr0_mdcp => spr_xucr0_mdcp, + spr_msr_de => spr_msr_de, + spr_msr_spv => spr_msr_spv, + spr_msr_fp => spr_msr_fp, + spr_msr_pr => spr_msr_pr, + spr_msr_gs => spr_msr_gs, + spr_msr_me => spr_msr_me, + spr_msr_cm => spr_msr_cm, + spr_msr_ucle => spr_msr_ucle, + spr_msrp_uclep => spr_msrp_uclep, + spr_ccr2_notlb => spr_ccr2_notlb, + spr_ccr2_ucode_dis => spr_ccr2_ucode_dis, + spr_ccr2_ap => spr_ccr2_ap, + spr_dbcr0_idm => spr_dbcr0_idm, + cpl_spr_dbcr0_edm => cpl_spr_dbcr0_edm, + spr_dbcr0_icmp => spr_dbcr0_icmp, + spr_dbcr0_brt => spr_dbcr0_brt, + spr_dbcr0_trap => spr_dbcr0_trap, + spr_dbcr0_ret => spr_dbcr0_ret, + spr_dbcr0_irpt => spr_dbcr0_irpt, + spr_dbcr3_ivc => spr_dbcr3_ivc_int, + spr_epcr_dsigs => spr_epcr_dsigs, + spr_epcr_isigs => spr_epcr_isigs, + spr_epcr_extgs => spr_epcr_extgs, + spr_epcr_dtlbgs => spr_epcr_dtlbgs, + spr_epcr_itlbgs => spr_epcr_itlbgs, + spr_xucr4_div_barr_thres => spr_xucr4_div_barr_thres, + spr_xucr4_mmu_mchk => spr_xucr4_mmu_mchk, + spr_ccr0_we => spr_ccr0_we, + spr_epcr_duvd => spr_epcr_duvd, + cpl_msr_gs => cpl_msr_gs, + cpl_msr_pr => cpl_msr_pr, + cpl_msr_fp => cpl_msr_fp, + cpl_msr_spv => cpl_msr_spv, + cpl_ccr2_ap => cpl_ccr2_ap, + spr_xucr0_clkg_ctl => spr_xucr0_clkg_ctl(2 to 2), + mux_cpl_slowspr_flush => mux_cpl_slowspr_flush, + mux_cpl_slowspr_done => mux_cpl_slowspr_done, + dec_cpl_ex1_is_slowspr_wr => dec_cpl_ex1_is_slowspr_wr, + dec_cpl_ex3_ddmh_en => dec_cpl_ex3_ddmh_en, + dec_cpl_ex3_back_inv => dec_cpl_ex3_back_inv, + pc_xu_event_bus_enable => pc_xu_event_bus_enable, + pc_xu_trace_bus_enable => pc_xu_trace_bus_enable, + pc_xu_instr_trace_mode => pc_xu_instr_trace_mode, + dec_cpl_rf1_instr_trace_val => dec_cpl_rf1_instr_trace_val, + dec_cpl_rf1_instr_trace_type => dec_cpl_rf1_instr_trace_type, + dec_cpl_ex3_instr_trace_val => dec_cpl_ex3_instr_trace_val, + cpl_dec_in_ucode => cpl_dec_in_ucode, + cpl_debug_mux_ctrls => cpl_debug_mux_ctrls, + cpl_debug_data_in => cpl_debug_data_in, + cpl_debug_data_out => cpl_debug_data_out, + cpl_trigger_data_in => cpl_trigger_data_in, + cpl_trigger_data_out => cpl_trigger_data_out, + fxa_cpl_debug => fxa_cpl_debug, + vdd => vdd, + gnd => gnd + ); + +xu_ex1_eff_addr_int <= xu_ex1_eff_addr; +xu_rf0_flush <= xu_rf0_flush_int; +xu_rf1_flush <= xu_rf1_flush_int; +xu_ex1_flush <= xu_ex1_flush_int; +xu_ex2_flush <= xu_ex2_flush_int; +xu_ex3_flush <= xu_ex3_flush_int; +xu_ex4_flush <= xu_ex4_flush_int; +dec_spr_ex1_epid_instr <= dec_ex1_epid_instr; + +end xuq_cpl_fxub; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_cpl_pri.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_cpl_pri.vhdl new file mode 100644 index 0000000..05c171a --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_cpl_pri.vhdl @@ -0,0 +1,113 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee,ibm,support; +use ieee.std_logic_1164.all; +use ibm.std_ulogic_function_support.reverse; + +entity xuq_cpl_pri is +generic( + size : integer range 3 to 32 := 32; + rev : integer range 0 to 1 := 0; + cmp_zero : integer range 0 to 1 := 0); +port( + cond : in std_ulogic_vector(0 to size-1); + pri : out std_ulogic_vector(0 to size-1+cmp_zero); + or_cond : out std_ulogic +); + +-- synopsys translate_off +-- synopsys translate_on + +end xuq_cpl_pri; +architecture xuq_cpl_pri of xuq_cpl_pri is + +constant s : integer := size-1; +signal l0 : std_ulogic_vector(0 to s); +signal or_l1,or_l2,or_l3,or_l4,or_l5: std_ulogic_vector(0 to s); + + +begin + +rev_gen0 : if rev = 0 generate + l0(0 to s) <= cond(0 to s); +end generate; +rev_gen1 : if rev = 1 generate + l0(0 to s) <= reverse(cond(0 to s)); +end generate; + + +l1_not: or_l1(0) <= not l0(0); +l1_nor: or_l1(1 to s) <= l0(0 to s-1) nor l0(1 to s); + + +or_l2_gen0 : if s >= 2 generate + or_l2(0 to 1) <= not or_l1(0 to 1); + or_l2(2 to s) <= or_l1(2 to s) nand or_l1(0 to s-2); +end generate; +or_l2_gen1 : if s < 2 generate + or_l2 <= not or_l1; +end generate; + +or_l3_gen0 : if s >= 4 generate + or_l3(0 to 3) <= not or_l2(0 to 3); + or_l3(4 to s) <= or_l2(4 to s) nor or_l2(0 to s-4); +end generate; +or_l3_gen1 : if s < 4 generate + or_l3 <= not or_l2; +end generate; + +or_l4_gen0 : if s >= 8 generate + or_l4(0 to 7) <= not or_l3(0 to 7); + or_l4(8 to s) <= or_l3(8 to s) nand or_l3(0 to s-8); +end generate; +or_l4_gen1 : if s < 8 generate + or_l4 <= not or_l3; +end generate; + +or_l5_gen0 : if s >= 16 generate + or_l5(0 to 15) <= not or_l4(0 to 15); + or_l5(16 to s) <= or_l4(16 to s) nor or_l4(0 to s-16); +end generate; +or_l5_gen1 : if s < 16 generate + or_l5 <= not or_l4; +end generate; + + +pri(0) <= cond(0); +pri(1 to s) <= cond(1 to s) and or_l5(0 to s-1); + +cmp_zero_gen : if cmp_zero = 1 generate +pri(s+1) <= or_l5(s); +end generate; + +or_cond <= not or_l5(s); + + + +end architecture xuq_cpl_pri; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_cpl_spr.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_cpl_spr.vhdl new file mode 100644 index 0000000..cf2b11f --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_cpl_spr.vhdl @@ -0,0 +1,246 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee,ibm,support,work,tri; +use ieee.std_logic_1164.all; +use support.power_logic_pkg.all; +use ibm.std_ulogic_function_support.all; +use tri.tri_latches_pkg.all; + +entity xuq_cpl_spr is +generic( + hvmode : integer := 1; + a2mode : integer := 1; + expand_type : integer := 2; + threads : integer := 4; + regsize : integer := 64; + eff_ifar : integer := 62); +port( + nclk : in clk_logic; + + d_mode_dc : in std_ulogic; + delay_lclkr_dc : in std_ulogic; + mpw1_dc_b : in std_ulogic; + mpw2_dc_b : in std_ulogic; + + dcfg_sl_force : in std_ulogic; + dcfg_sl_thold_0_b : in std_ulogic; + func_sl_force : in std_ulogic; + func_sl_thold_0_b : in std_ulogic; + func_nsl_force : in std_ulogic; + func_nsl_thold_0_b : in std_ulogic; + sg_0 : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + dcfg_scan_in : in std_ulogic; + dcfg_scan_out : out std_ulogic; + + spr_bit_act : in std_ulogic; + exx_act : in std_ulogic_vector(1 to 4); + ex1_instr : in std_ulogic_vector(11 to 20); + ex2_tid : in std_ulogic_vector(0 to threads-1); + ex1_is_mfspr : in std_ulogic; + ex1_is_mtspr : in std_ulogic; + ex4_lr_update : in std_ulogic; + ex4_ctr_dec_update : in std_ulogic; + + ex2_ifar : in std_ulogic_vector(0 to eff_ifar*threads-1); + + ex5_val : in std_ulogic_vector(0 to threads-1); + ex5_spr_wd : in std_ulogic_vector(64-regsize to 63); + ex5_cia_p1 : in std_ulogic_vector(62-eff_ifar to 61); + + ex2_mtiar : out std_ulogic; + + cpl_byp_ex3_spr_rt : out std_ulogic_vector(64-regsize to 63); + + + ex3_iac1_cmpr : out std_ulogic_vector(0 to threads-1); + ex3_iac2_cmpr : out std_ulogic_vector(0 to threads-1); + ex3_iac3_cmpr : out std_ulogic_vector(0 to threads-1); + ex3_iac4_cmpr : out std_ulogic_vector(0 to threads-1); + + spr_cpl_iac1_en : in std_ulogic_vector(0 to threads-1); + spr_cpl_iac2_en : in std_ulogic_vector(0 to threads-1); + spr_cpl_iac3_en : in std_ulogic_vector(0 to threads-1); + spr_cpl_iac4_en : in std_ulogic_vector(0 to threads-1); + spr_dbcr1_iac12m : in std_ulogic_vector(0 to threads-1); + spr_dbcr1_iac34m : in std_ulogic_vector(0 to threads-1); + spr_iar : in std_ulogic_vector(0 to eff_ifar*threads-1); + spr_msr_cm : in std_ulogic_vector(0 to threads-1); + spr_givpr : out std_ulogic_vector(0 to eff_ifar-10-1); + spr_ivpr : out std_ulogic_vector(0 to eff_ifar-10-1); + spr_xucr3_hold1_dly : out std_ulogic_vector(0 to 3); + spr_xucr3_cm_hold_dly : out std_ulogic_vector(0 to 3); + spr_xucr3_stop_dly : out std_ulogic_vector(0 to 3); + spr_xucr3_hold0_dly : out std_ulogic_vector(0 to 3); + spr_xucr3_csi_dly : out std_ulogic_vector(0 to 3); + spr_xucr3_int_dly : out std_ulogic_vector(0 to 3); + spr_xucr3_asyncblk_dly : out std_ulogic_vector(0 to 3); + spr_xucr3_flush_dly : out std_ulogic_vector(0 to 3); + spr_xucr4_mmu_mchk : out std_ulogic; + spr_xucr4_mddmh : out std_ulogic; + spr_xucr4_div_barr_thres : out std_ulogic_vector(0 to 7); + spr_xucr4_div_bar_dis : out std_ulogic; + spr_xucr4_lsu_bar_dis : out std_ulogic; + spr_xucr4_barr_dly : out std_ulogic_vector(0 to 3); + spr_ctr : out std_ulogic_vector(0 to (regsize)*threads-1); + spr_lr : out std_ulogic_vector(0 to (regsize)*threads-1); + + vdd : inout power_logic; + gnd : inout power_logic +); + +-- synopsys translate_off + +-- synopsys translate_on +end xuq_cpl_spr; +architecture xuq_cpl_spr of xuq_cpl_spr is + + +signal siv : std_ulogic_vector(0 to threads); +signal sov : std_ulogic_vector(0 to threads); +signal cspr_tspr_ex5_is_mtspr : std_ulogic; +signal cspr_tspr_ex5_instr : std_ulogic_vector(11 to 20); +signal cspr_tspr_ex2_instr : std_ulogic_vector(11 to 20); +signal tspr_cspr_ex2_tspr_rt : std_ulogic_vector(0 to regsize*threads-1); + +begin + +xu_cpl_spr_cspr : entity work.xuq_cpl_spr_cspr(xuq_cpl_spr_cspr) +generic map( + hvmode => hvmode, + a2mode => a2mode, + expand_type => expand_type, + threads => threads, + regsize => regsize, + eff_ifar => eff_ifar) +port map( + nclk => nclk, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc, + mpw1_dc_b => mpw1_dc_b, + mpw2_dc_b => mpw2_dc_b, + dcfg_sl_force => dcfg_sl_force, + dcfg_sl_thold_0_b => dcfg_sl_thold_0_b, + func_sl_force => func_sl_force, + func_sl_thold_0_b => func_sl_thold_0_b, + func_nsl_force => func_nsl_force, + func_nsl_thold_0_b => func_nsl_thold_0_b, + sg_0 => sg_0, + scan_in => siv(threads), + scan_out => sov(threads), + dcfg_scan_in => dcfg_scan_in, + dcfg_scan_out => dcfg_scan_out, + spr_bit_act => spr_bit_act, + exx_act => exx_act, + ex1_instr => ex1_instr, + ex2_tid => ex2_tid, + ex1_is_mfspr => ex1_is_mfspr, + ex1_is_mtspr => ex1_is_mtspr, + ex2_ifar => ex2_ifar, + ex5_valid => ex5_val, + ex5_spr_wd => ex5_spr_wd, + ex2_mtiar => ex2_mtiar, + cspr_tspr_ex5_is_mtspr => cspr_tspr_ex5_is_mtspr, + cspr_tspr_ex5_instr => cspr_tspr_ex5_instr, + cspr_tspr_ex2_instr => cspr_tspr_ex2_instr, + tspr_cspr_ex2_tspr_rt => tspr_cspr_ex2_tspr_rt, + cpl_byp_ex3_spr_rt => cpl_byp_ex3_spr_rt, + ex3_iac1_cmpr => ex3_iac1_cmpr, + ex3_iac2_cmpr => ex3_iac2_cmpr, + ex3_iac3_cmpr => ex3_iac3_cmpr, + ex3_iac4_cmpr => ex3_iac4_cmpr, + spr_cpl_iac1_en => spr_cpl_iac1_en, + spr_cpl_iac2_en => spr_cpl_iac2_en, + spr_cpl_iac3_en => spr_cpl_iac3_en, + spr_cpl_iac4_en => spr_cpl_iac4_en, + spr_dbcr1_iac12m => spr_dbcr1_iac12m, + spr_dbcr1_iac34m => spr_dbcr1_iac34m, + spr_msr_cm => spr_msr_cm, + spr_givpr => spr_givpr, + spr_ivpr => spr_ivpr, + spr_xucr3_hold1_dly => spr_xucr3_hold1_dly, + spr_xucr3_cm_hold_dly => spr_xucr3_cm_hold_dly, + spr_xucr3_stop_dly => spr_xucr3_stop_dly, + spr_xucr3_hold0_dly => spr_xucr3_hold0_dly, + spr_xucr3_csi_dly => spr_xucr3_csi_dly, + spr_xucr3_int_dly => spr_xucr3_int_dly, + spr_xucr3_asyncblk_dly => spr_xucr3_asyncblk_dly, + spr_xucr3_flush_dly => spr_xucr3_flush_dly, + spr_xucr4_mmu_mchk => spr_xucr4_mmu_mchk, + spr_xucr4_mddmh => spr_xucr4_mddmh, + spr_xucr4_div_barr_thres => spr_xucr4_div_barr_thres, + spr_xucr4_div_bar_dis => spr_xucr4_div_bar_dis, + spr_xucr4_lsu_bar_dis => spr_xucr4_lsu_bar_dis, + spr_xucr4_barr_dly => spr_xucr4_barr_dly, + vdd => vdd, + gnd => gnd +); + +thread : for t in 0 to threads-1 generate +xu_cpl_spr_tspr : entity work.xuq_cpl_spr_tspr(xuq_cpl_spr_tspr) +generic map( + hvmode => hvmode, + a2mode => a2mode, + expand_type => expand_type, + regsize => regsize, + eff_ifar => eff_ifar) +port map( + nclk => nclk, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc, + mpw1_dc_b => mpw1_dc_b, + mpw2_dc_b => mpw2_dc_b, + func_sl_force => func_sl_force, + func_sl_thold_0_b => func_sl_thold_0_b, + sg_0 => sg_0, + scan_in => siv(t), + scan_out => sov(t), + cspr_tspr_ex2_instr => cspr_tspr_ex2_instr, + tspr_cspr_ex2_tspr_rt => tspr_cspr_ex2_tspr_rt(regsize*t to regsize*(t+1)-1), + ex5_val => ex5_val(t), + cspr_tspr_ex5_is_mtspr => cspr_tspr_ex5_is_mtspr, + cspr_tspr_ex5_instr => cspr_tspr_ex5_instr, + ex5_spr_wd => ex5_spr_wd, + ex5_cia_p1 => ex5_cia_p1, + ex4_lr_update => ex4_lr_update, + ex4_ctr_dec_update => ex4_ctr_dec_update, + spr_iar => spr_iar(eff_ifar*t to eff_ifar*(t+1)-1), + spr_ctr => spr_ctr((regsize)*t to (regsize)*(t+1)-1), + spr_lr => spr_lr((regsize)*t to (regsize)*(t+1)-1), + vdd => vdd, + gnd => gnd +); +end generate; + +siv(0 to threads) <= sov(1 to threads) & scan_in; +scan_out <= sov(0); + + +end architecture xuq_cpl_spr; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_cpl_spr_cspr.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_cpl_spr_cspr.vhdl new file mode 100644 index 0000000..9580218 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_cpl_spr_cspr.vhdl @@ -0,0 +1,951 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee,ibm,support,work,tri; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use support.power_logic_pkg.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use tri.tri_latches_pkg.all; +use work.xuq_pkg.all; + +entity xuq_cpl_spr_cspr is +generic( + hvmode : integer := 1; + a2mode : integer := 1; + expand_type : integer := 2; + threads : integer := 4; + regsize : integer := 64; + eff_ifar : integer := 62); +port( + nclk : in clk_logic; + + d_mode_dc : in std_ulogic; + delay_lclkr_dc : in std_ulogic; + mpw1_dc_b : in std_ulogic; + mpw2_dc_b : in std_ulogic; + + dcfg_sl_force : in std_ulogic; + dcfg_sl_thold_0_b : in std_ulogic; + func_sl_force : in std_ulogic; + func_sl_thold_0_b : in std_ulogic; + func_nsl_force : in std_ulogic; + func_nsl_thold_0_b : in std_ulogic; + sg_0 : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + dcfg_scan_in : in std_ulogic; + dcfg_scan_out : out std_ulogic; + + spr_bit_act : in std_ulogic; + exx_act : in std_ulogic_vector(1 to 4); + ex1_instr : in std_ulogic_vector(11 to 20); + ex2_tid : in std_ulogic_vector(0 to threads-1); + ex1_is_mfspr : in std_ulogic; + ex1_is_mtspr : in std_ulogic; + + ex2_ifar : in std_ulogic_vector(0 to eff_ifar*threads-1); + + ex5_valid : in std_ulogic_vector(0 to threads-1); + ex5_spr_wd : in std_ulogic_vector(64-regsize to 63); + + ex2_mtiar : out std_ulogic; + + cspr_tspr_ex5_is_mtspr : out std_ulogic; + cspr_tspr_ex5_instr : out std_ulogic_vector(11 to 20); + cspr_tspr_ex2_instr : out std_ulogic_vector(11 to 20); + + tspr_cspr_ex2_tspr_rt : in std_ulogic_vector(0 to regsize*threads-1); + cpl_byp_ex3_spr_rt : out std_ulogic_vector(64-regsize to 63); + + + ex3_iac1_cmpr : out std_ulogic_vector(0 to threads-1); + ex3_iac2_cmpr : out std_ulogic_vector(0 to threads-1); + ex3_iac3_cmpr : out std_ulogic_vector(0 to threads-1); + ex3_iac4_cmpr : out std_ulogic_vector(0 to threads-1); + + spr_cpl_iac1_en : in std_ulogic_vector(0 to threads-1); + spr_cpl_iac2_en : in std_ulogic_vector(0 to threads-1); + spr_cpl_iac3_en : in std_ulogic_vector(0 to threads-1); + spr_cpl_iac4_en : in std_ulogic_vector(0 to threads-1); + spr_dbcr1_iac12m : in std_ulogic_vector(0 to threads-1); + spr_dbcr1_iac34m : in std_ulogic_vector(0 to threads-1); + spr_msr_cm : in std_ulogic_vector(0 to threads-1); + spr_givpr : out std_ulogic_vector(0 to eff_ifar-10-1); + spr_ivpr : out std_ulogic_vector(0 to eff_ifar-10-1); + spr_xucr3_hold1_dly : out std_ulogic_vector(0 to 3); + spr_xucr3_cm_hold_dly : out std_ulogic_vector(0 to 3); + spr_xucr3_stop_dly : out std_ulogic_vector(0 to 3); + spr_xucr3_hold0_dly : out std_ulogic_vector(0 to 3); + spr_xucr3_csi_dly : out std_ulogic_vector(0 to 3); + spr_xucr3_int_dly : out std_ulogic_vector(0 to 3); + spr_xucr3_asyncblk_dly : out std_ulogic_vector(0 to 3); + spr_xucr3_flush_dly : out std_ulogic_vector(0 to 3); + spr_xucr4_mmu_mchk : out std_ulogic; + spr_xucr4_mddmh : out std_ulogic; + spr_xucr4_div_barr_thres : out std_ulogic_vector(0 to 7); + spr_xucr4_div_bar_dis : out std_ulogic; + spr_xucr4_lsu_bar_dis : out std_ulogic; + spr_xucr4_barr_dly : out std_ulogic_vector(0 to 3); + + vdd : inout power_logic; + gnd : inout power_logic +); + +-- synopsys translate_off + +-- synopsys translate_on +end xuq_cpl_spr_cspr; +architecture xuq_cpl_spr_cspr of xuq_cpl_spr_cspr is + +constant ui : integer := 62-eff_ifar; +subtype DO is std_ulogic_vector(65-regsize to 64); +type IFAR_ARR is array (0 to threads-1) of std_ulogic_vector(62-eff_ifar to 61); +type IACM_ARR is array (0 to threads-1) of std_ulogic_vector(0 to regsize/8-1); +signal givpr_d , givpr_q : std_ulogic_vector(64-(eff_ifar-10) to 63); +signal iac1_d , iac1_q : std_ulogic_vector(64-(eff_ifar) to 63); +signal iac2_d , iac2_q : std_ulogic_vector(64-(eff_ifar) to 63); +signal iac3_d , iac3_q : std_ulogic_vector(64-(eff_ifar) to 63); +signal iac4_d , iac4_q : std_ulogic_vector(64-(eff_ifar) to 63); +signal ivpr_d , ivpr_q : std_ulogic_vector(64-(eff_ifar-10) to 63); +signal xucr3_d , xucr3_q : std_ulogic_vector(32 to 63); +signal xucr4_d , xucr4_q : std_ulogic_vector(48 to 63); +constant givpr_offset : natural := 0; +constant iac1_offset : natural := givpr_offset + givpr_q'length*hvmode; +constant iac2_offset : natural := iac1_offset + iac1_q'length; +constant iac3_offset : natural := iac2_offset + iac2_q'length; +constant iac4_offset : natural := iac3_offset + iac3_q'length*a2mode; +constant ivpr_offset : natural := iac4_offset + iac4_q'length*a2mode; +constant last_reg_offset : natural := ivpr_offset + ivpr_q'length; +constant last_reg_offset_bcfg : natural := 1; +constant last_reg_offset_ccfg : natural := 1; +constant xucr3_offset_dcfg : natural := 0; +constant xucr4_offset_dcfg : natural := xucr3_offset_dcfg + xucr3_q'length; +constant last_reg_offset_dcfg : natural := xucr4_offset_dcfg + xucr4_q'length; +signal ex2_is_mfspr_q : std_ulogic; +signal ex2_is_mtspr_q : std_ulogic; +signal ex2_instr_q : std_ulogic_vector(11 to 20); +signal ex3_is_mtspr_q : std_ulogic; +signal ex3_instr_q : std_ulogic_vector(11 to 20); +signal ex3_spr_rt_q, ex3_spr_rt_d : std_ulogic_vector(64-regsize to 63); +signal ex3_iac1_cmpr_q, ex3_iac1_cmpr_d: std_ulogic_vector(0 to threads-1); +signal ex3_iac2_cmpr_q, ex3_iac2_cmpr_d: std_ulogic_vector(0 to threads-1); +signal ex3_iac3_cmpr_q, ex3_iac3_cmpr_d: std_ulogic_vector(0 to threads-1); +signal ex3_iac4_cmpr_q, ex3_iac4_cmpr_d: std_ulogic_vector(0 to threads-1); +signal ex4_is_mtspr_q : std_ulogic; +signal ex4_instr_q : std_ulogic_vector(11 to 20); +signal ex5_is_mtspr_q : std_ulogic; +signal ex5_instr_q : std_ulogic_vector(11 to 20); +signal dbcr1_iac12m_2_q, dbcr1_iac12m_2_d : IACM_ARR; +signal dbcr1_iac34m_2_q, dbcr1_iac34m_2_d : IACM_ARR; +signal iac1_en_q : std_ulogic_vector(0 to threads-1); +signal iac2_en_q : std_ulogic_vector(0 to threads-1); +signal iac3_en_q : std_ulogic_vector(0 to threads-1); +signal iac4_en_q : std_ulogic_vector(0 to threads-1); +signal dbcr1_iac12m_q : std_ulogic_vector(0 to threads-1); +signal dbcr1_iac34m_q : std_ulogic_vector(0 to threads-1); +constant ex2_is_mfspr_offset : integer := last_reg_offset; +constant ex2_is_mtspr_offset : integer := ex2_is_mfspr_offset + 1; +constant ex2_instr_offset : integer := ex2_is_mtspr_offset + 1; +constant ex3_is_mtspr_offset : integer := ex2_instr_offset + ex2_instr_q'length; +constant ex3_instr_offset : integer := ex3_is_mtspr_offset + 1; +constant ex3_spr_rt_offset : integer := ex3_instr_offset + ex3_instr_q'length; +constant ex3_iac1_cmpr_offset : integer := ex3_spr_rt_offset + ex3_spr_rt_q'length; +constant ex3_iac2_cmpr_offset : integer := ex3_iac1_cmpr_offset + ex3_iac1_cmpr_q'length; +constant ex3_iac3_cmpr_offset : integer := ex3_iac2_cmpr_offset + ex3_iac2_cmpr_q'length; +constant ex3_iac4_cmpr_offset : integer := ex3_iac3_cmpr_offset + ex3_iac3_cmpr_q'length; +constant ex4_is_mtspr_offset : integer := ex3_iac4_cmpr_offset + ex3_iac4_cmpr_q'length; +constant ex4_instr_offset : integer := ex4_is_mtspr_offset + 1; +constant ex5_is_mtspr_offset : integer := ex4_instr_offset + ex4_instr_q'length; +constant ex5_instr_offset : integer := ex5_is_mtspr_offset + 1; +constant iac1_en_offset : integer := ex5_instr_offset + ex5_instr_q'length; +constant iac2_en_offset : integer := iac1_en_offset + iac1_en_q'length; +constant iac3_en_offset : integer := iac2_en_offset + iac2_en_q'length; +constant iac4_en_offset : integer := iac3_en_offset + iac3_en_q'length; +constant dbcr1_iac12m_offset : integer := iac4_en_offset + iac4_en_q'length; +constant dbcr1_iac34m_offset : integer := dbcr1_iac12m_offset + dbcr1_iac12m_q'length; +constant scan_right : integer := dbcr1_iac34m_offset + dbcr1_iac34m_q'length; +signal siv : std_ulogic_vector(0 to scan_right-1); +signal sov : std_ulogic_vector(0 to scan_right-1); +constant scan_right_dcfg : integer := last_reg_offset_dcfg; +signal siv_dcfg : std_ulogic_vector(0 to scan_right_dcfg-1); +signal sov_dcfg : std_ulogic_vector(0 to scan_right_dcfg-1); +signal tiup : std_ulogic; +signal tidn : std_ulogic_vector(00 to 63); +signal ex2_iac1_cmprh : std_ulogic_vector(0 to threads-1); +signal ex2_iac2_cmprh : std_ulogic_vector(0 to threads-1); +signal ex2_iac3_cmprh : std_ulogic_vector(0 to threads-1); +signal ex2_iac4_cmprh : std_ulogic_vector(0 to threads-1); +signal ex2_iac1_cmprl : std_ulogic_vector(0 to threads-1); +signal ex2_iac2_cmprl : std_ulogic_vector(0 to threads-1); +signal ex2_iac3_cmprl : std_ulogic_vector(0 to threads-1); +signal ex2_iac4_cmprl : std_ulogic_vector(0 to threads-1); +signal ex2_iac1_cmpr : std_ulogic_vector(0 to threads-1); +signal ex2_iac2_cmpr : std_ulogic_vector(0 to threads-1); +signal ex2_iac3_cmpr : std_ulogic_vector(0 to threads-1); +signal ex2_iac4_cmpr : std_ulogic_vector(0 to threads-1); +signal ex2_iac1_cmpr_sel : std_ulogic_vector(0 to threads-1); +signal ex2_iac2_cmpr_sel : std_ulogic_vector(0 to threads-1); +signal ex2_iac3_cmpr_sel : std_ulogic_vector(0 to threads-1); +signal ex2_iac4_cmpr_sel : std_ulogic_vector(0 to threads-1); +signal ex2_instr : std_ulogic_vector(11 to 20); +signal ex5_is_mtspr : std_ulogic; +signal ex5_instr : std_ulogic_vector(11 to 20); +signal ex2_cspr_rt,ex2_tspr_rt : std_ulogic_vector(64-regsize to 63); +signal ex5_val : std_ulogic; + +signal ex5_givpr_di : std_ulogic_vector(givpr_q'range); +signal ex5_iac1_di : std_ulogic_vector(iac1_q'range); +signal ex5_iac2_di : std_ulogic_vector(iac2_q'range); +signal ex5_iac3_di : std_ulogic_vector(iac3_q'range); +signal ex5_iac4_di : std_ulogic_vector(iac4_q'range); +signal ex5_ivpr_di : std_ulogic_vector(ivpr_q'range); +signal ex5_xucr3_di : std_ulogic_vector(xucr3_q'range); +signal ex5_xucr4_di : std_ulogic_vector(xucr4_q'range); +signal + ex2_givpr_rdec , ex2_iac1_rdec , ex2_iac2_rdec , ex2_iac3_rdec + , ex2_iac4_rdec , ex2_ivpr_rdec , ex2_xucr3_rdec , ex2_xucr4_rdec + : std_ulogic; +signal + ex2_givpr_re , ex2_iac1_re , ex2_iac2_re , ex2_iac3_re + , ex2_iac4_re , ex2_ivpr_re , ex2_xucr3_re , ex2_xucr4_re + : std_ulogic; +signal + ex5_givpr_wdec , ex5_iac1_wdec , ex5_iac2_wdec , ex5_iac3_wdec + , ex5_iac4_wdec , ex5_ivpr_wdec , ex5_xucr3_wdec , ex5_xucr4_wdec + : std_ulogic; +signal + ex5_givpr_we , ex5_iac1_we , ex5_iac2_we , ex5_iac3_we + , ex5_iac4_we , ex5_ivpr_we , ex5_xucr3_we , ex5_xucr4_we + : std_ulogic; +signal + givpr_act , iac1_act , iac2_act , iac3_act + , iac4_act , ivpr_act , xucr3_act , xucr4_act + : std_ulogic; +signal + givpr_do , iac1_do , iac2_do , iac3_do + , iac4_do , ivpr_do , xucr3_do , xucr4_do + : std_ulogic_vector(0 to 64); + +begin + + +tiup <= '1'; +tidn <= (others=>'0'); + +ex2_instr <= ex2_instr_q; +ex5_is_mtspr <= ex5_is_mtspr_q; +ex5_instr <= ex5_instr_q; +ex5_val <= or_reduce(ex5_valid); + +ex2_mtiar <= ex2_is_mtspr_q and (ex2_instr_q(11 to 20) = "1001011011"); + +cspr_tspr_ex5_is_mtspr <= ex5_is_mtspr_q; +cspr_tspr_ex5_instr <= ex5_instr_q; +cspr_tspr_ex2_instr <= ex2_instr_q; + + +iac1_act <= ex5_iac1_we; +iac1_d <= ex5_iac1_di; + +iac2_act <= ex5_iac2_we; +iac2_d <= ex5_iac2_di; + +iac3_act <= ex5_iac3_we; +iac3_d <= ex5_iac3_di; + +iac4_act <= ex5_iac4_we; +iac4_d <= ex5_iac4_di; + +ivpr_act <= ex5_ivpr_we; +ivpr_d <= ex5_ivpr_di; + +givpr_act <= ex5_givpr_we; +givpr_d <= ex5_givpr_di; + +xucr3_act <= ex5_xucr3_we; +xucr3_d <= ex5_xucr3_di; + +xucr4_act <= ex5_xucr4_we; +xucr4_d <= ex5_xucr4_di; + + + +ex3_iac1_cmpr <= ex3_iac1_cmpr_q; +ex3_iac2_cmpr <= ex3_iac2_cmpr_q; +ex3_iac3_cmpr <= ex3_iac3_cmpr_q; +ex3_iac4_cmpr <= ex3_iac4_cmpr_q; + +ifar_cmp : for t in 0 to threads-1 generate +signal ex2_ifar_int : std_ulogic_vector(62-eff_ifar to 61); +signal ex2_iac2_mask : std_ulogic_vector(62-eff_ifar to 61); +signal ex2_iac4_mask : std_ulogic_vector(62-eff_ifar to 61); +begin + + ex2_ifar_int <= ex2_ifar(eff_ifar*t to eff_ifar*(t+1)-1); + + ex2_iac2_mask <= iac2_q or not fanout(dbcr1_iac12m_2_q(t),eff_ifar); + ex2_iac4_mask <= iac4_q or not fanout(dbcr1_iac34m_2_q(t),eff_ifar); + + xuq_spr_iac_cmprh_gen0 : if eff_ifar > 32 generate + ex2_iac1_cmprh(t) <= and_reduce((ex2_ifar_int(ui to 31) xnor iac1_q(ui+2 to 33)) or not ex2_iac2_mask(ui to 31)); + ex2_iac2_cmprh(t) <= and_reduce((ex2_ifar_int(ui to 31) xnor iac2_q(ui+2 to 33)) ); + ex2_iac3_cmprh(t) <= and_reduce((ex2_ifar_int(ui to 31) xnor iac3_q(ui+2 to 33)) or not ex2_iac4_mask(ui to 31)); + ex2_iac4_cmprh(t) <= and_reduce((ex2_ifar_int(ui to 31) xnor iac4_q(ui+2 to 33)) ); + + ex2_iac1_cmprl(t) <= and_reduce((ex2_ifar_int(32 to 61) xnor iac1_q(32+2 to 63)) or not ex2_iac2_mask(32 to 61)); + ex2_iac2_cmprl(t) <= and_reduce((ex2_ifar_int(32 to 61) xnor iac2_q(32+2 to 63)) ); + ex2_iac3_cmprl(t) <= and_reduce((ex2_ifar_int(32 to 61) xnor iac3_q(32+2 to 63)) or not ex2_iac4_mask(32 to 61)); + ex2_iac4_cmprl(t) <= and_reduce((ex2_ifar_int(32 to 61) xnor iac4_q(32+2 to 63)) ); + + ex2_iac1_cmpr(t) <= ex2_iac1_cmprl(t) and (ex2_iac1_cmprh(t) or not spr_msr_cm(t)); + ex2_iac2_cmpr(t) <= ex2_iac2_cmprl(t) and (ex2_iac2_cmprh(t) or not spr_msr_cm(t)); + ex2_iac3_cmpr(t) <= ex2_iac3_cmprl(t) and (ex2_iac3_cmprh(t) or not spr_msr_cm(t)); + ex2_iac4_cmpr(t) <= ex2_iac4_cmprl(t) and (ex2_iac4_cmprh(t) or not spr_msr_cm(t)); + end generate; + + xuq_spr_iac_cmprh_gen1 : if eff_ifar <= 32 generate + ex2_iac1_cmprh(t) <= '1'; + ex2_iac2_cmprh(t) <= '1'; + ex2_iac3_cmprh(t) <= '1'; + ex2_iac4_cmprh(t) <= '1'; + + ex2_iac1_cmprl(t) <= and_reduce((ex2_ifar(ui to 61) xnor iac1_q(ui+2 to 63)) or not ex2_iac2_mask(ui to 61)); + ex2_iac2_cmprl(t) <= and_reduce((ex2_ifar(ui to 61) xnor iac2_q(ui+2 to 63)) ); + ex2_iac3_cmprl(t) <= and_reduce((ex2_ifar(ui to 61) xnor iac3_q(ui+2 to 63)) or not ex2_iac4_mask(ui to 61)); + ex2_iac4_cmprl(t) <= and_reduce((ex2_ifar(ui to 61) xnor iac4_q(ui+2 to 63)) ); + + ex2_iac1_cmpr(t) <= ex2_iac1_cmprl(t); + ex2_iac2_cmpr(t) <= ex2_iac2_cmprl(t); + ex2_iac3_cmpr(t) <= ex2_iac3_cmprl(t); + ex2_iac4_cmpr(t) <= ex2_iac4_cmprl(t); + end generate; + + ex2_iac1_cmpr_sel(t) <= ex2_iac1_cmpr(t); + ex2_iac2_cmpr_sel(t) <= ex2_iac2_cmpr(t) when dbcr1_iac12m_2_q(t)(0)='0' else ex2_iac1_cmpr(t); + ex2_iac3_cmpr_sel(t) <= ex2_iac3_cmpr(t); + ex2_iac4_cmpr_sel(t) <= ex2_iac4_cmpr(t) when dbcr1_iac34m_2_q(t)(0)='0' else ex2_iac3_cmpr(t); + + ex3_iac1_cmpr_d(t) <= ex2_iac1_cmpr_sel(t) and iac1_en_q(t); + ex3_iac2_cmpr_d(t) <= ex2_iac2_cmpr_sel(t) and iac2_en_q(t); + ex3_iac3_cmpr_d(t) <= ex2_iac3_cmpr_sel(t) and iac3_en_q(t); + ex3_iac4_cmpr_d(t) <= ex2_iac4_cmpr_sel(t) and iac4_en_q(t); +end generate; + + + + +readmux_00 : if a2mode = 0 and hvmode = 0 generate +ex2_cspr_rt <= + (iac1_do(DO'range) and (DO'range => ex2_iac1_re )) or + (iac2_do(DO'range) and (DO'range => ex2_iac2_re )) or + (ivpr_do(DO'range) and (DO'range => ex2_ivpr_re )) or + (xucr3_do(DO'range) and (DO'range => ex2_xucr3_re )) or + (xucr4_do(DO'range) and (DO'range => ex2_xucr4_re )); +end generate; +readmux_01 : if a2mode = 0 and hvmode = 1 generate +ex2_cspr_rt <= + (givpr_do(DO'range) and (DO'range => ex2_givpr_re )) or + (iac1_do(DO'range) and (DO'range => ex2_iac1_re )) or + (iac2_do(DO'range) and (DO'range => ex2_iac2_re )) or + (ivpr_do(DO'range) and (DO'range => ex2_ivpr_re )) or + (xucr3_do(DO'range) and (DO'range => ex2_xucr3_re )) or + (xucr4_do(DO'range) and (DO'range => ex2_xucr4_re )); +end generate; +readmux_10 : if a2mode = 1 and hvmode = 0 generate +ex2_cspr_rt <= + (iac1_do(DO'range) and (DO'range => ex2_iac1_re )) or + (iac2_do(DO'range) and (DO'range => ex2_iac2_re )) or + (iac3_do(DO'range) and (DO'range => ex2_iac3_re )) or + (iac4_do(DO'range) and (DO'range => ex2_iac4_re )) or + (ivpr_do(DO'range) and (DO'range => ex2_ivpr_re )) or + (xucr3_do(DO'range) and (DO'range => ex2_xucr3_re )) or + (xucr4_do(DO'range) and (DO'range => ex2_xucr4_re )); +end generate; +readmux_11 : if a2mode = 1 and hvmode = 1 generate +ex2_cspr_rt <= + (givpr_do(DO'range) and (DO'range => ex2_givpr_re )) or + (iac1_do(DO'range) and (DO'range => ex2_iac1_re )) or + (iac2_do(DO'range) and (DO'range => ex2_iac2_re )) or + (iac3_do(DO'range) and (DO'range => ex2_iac3_re )) or + (iac4_do(DO'range) and (DO'range => ex2_iac4_re )) or + (ivpr_do(DO'range) and (DO'range => ex2_ivpr_re )) or + (xucr3_do(DO'range) and (DO'range => ex2_xucr3_re )) or + (xucr4_do(DO'range) and (DO'range => ex2_xucr4_re )); +end generate; + +ex2_tspr_rt <= mux_t(tspr_cspr_ex2_tspr_rt,ex2_tid); +ex3_spr_rt_d <= gate((ex2_tspr_rt or ex2_cspr_rt),ex2_is_mfspr_q); +cpl_byp_ex3_spr_rt <= ex3_spr_rt_q; + + +ex2_givpr_rdec <= (ex2_instr(11 to 20) = "1111101101"); +ex2_iac1_rdec <= (ex2_instr(11 to 20) = "1100001001"); +ex2_iac2_rdec <= (ex2_instr(11 to 20) = "1100101001"); +ex2_iac3_rdec <= (ex2_instr(11 to 20) = "1101001001"); +ex2_iac4_rdec <= (ex2_instr(11 to 20) = "1101101001"); +ex2_ivpr_rdec <= (ex2_instr(11 to 20) = "1111100001"); +ex2_xucr3_rdec <= (ex2_instr(11 to 20) = "1010011010"); +ex2_xucr4_rdec <= (ex2_instr(11 to 20) = "1010111010"); +ex2_givpr_re <= ex2_givpr_rdec; +ex2_iac1_re <= ex2_iac1_rdec; +ex2_iac2_re <= ex2_iac2_rdec; +ex2_iac3_re <= ex2_iac3_rdec; +ex2_iac4_re <= ex2_iac4_rdec; +ex2_ivpr_re <= ex2_ivpr_rdec; +ex2_xucr3_re <= ex2_xucr3_rdec; +ex2_xucr4_re <= ex2_xucr4_rdec; + +ex5_givpr_wdec <= (ex5_instr(11 to 20) = "1111101101"); +ex5_iac1_wdec <= (ex5_instr(11 to 20) = "1100001001"); +ex5_iac2_wdec <= (ex5_instr(11 to 20) = "1100101001"); +ex5_iac3_wdec <= (ex5_instr(11 to 20) = "1101001001"); +ex5_iac4_wdec <= (ex5_instr(11 to 20) = "1101101001"); +ex5_ivpr_wdec <= (ex5_instr(11 to 20) = "1111100001"); +ex5_xucr3_wdec <= (ex5_instr(11 to 20) = "1010011010"); +ex5_xucr4_wdec <= (ex5_instr(11 to 20) = "1010111010"); +ex5_givpr_we <= ex5_val and ex5_is_mtspr and ex5_givpr_wdec; +ex5_iac1_we <= ex5_val and ex5_is_mtspr and ex5_iac1_wdec; +ex5_iac2_we <= ex5_val and ex5_is_mtspr and ex5_iac2_wdec; +ex5_iac3_we <= ex5_val and ex5_is_mtspr and ex5_iac3_wdec; +ex5_iac4_we <= ex5_val and ex5_is_mtspr and ex5_iac4_wdec; +ex5_ivpr_we <= ex5_val and ex5_is_mtspr and ex5_ivpr_wdec; +ex5_xucr3_we <= ex5_val and ex5_is_mtspr and ex5_xucr3_wdec; +ex5_xucr4_we <= ex5_val and ex5_is_mtspr and ex5_xucr4_wdec; + +spr_givpr <= givpr_q(64-(eff_ifar-10) to 63); +spr_ivpr <= ivpr_q(64-(eff_ifar-10) to 63); +spr_xucr3_hold1_dly <= xucr3_q(32 to 35); +spr_xucr3_cm_hold_dly <= xucr3_q(36 to 39); +spr_xucr3_stop_dly <= xucr3_q(40 to 43); +spr_xucr3_hold0_dly <= xucr3_q(44 to 47); +spr_xucr3_csi_dly <= xucr3_q(48 to 51); +spr_xucr3_int_dly <= xucr3_q(52 to 55); +spr_xucr3_asyncblk_dly <= xucr3_q(56 to 59); +spr_xucr3_flush_dly <= xucr3_q(60 to 63); +spr_xucr4_mmu_mchk <= xucr4_q(48); +spr_xucr4_mddmh <= xucr4_q(49); +spr_xucr4_div_barr_thres <= xucr4_q(50 to 57); +spr_xucr4_div_bar_dis <= xucr4_q(58); +spr_xucr4_lsu_bar_dis <= xucr4_q(59); +spr_xucr4_barr_dly <= xucr4_q(60 to 63); + +ex5_givpr_di <= ex5_spr_wd(52-(eff_ifar-10) to 51); +givpr_do <= tidn(0 to 52-(eff_ifar-10)) & + givpr_q(64-(eff_ifar-10) to 63) & + tidn(52 to 63) ; +ex5_iac1_di <= ex5_spr_wd(62-(eff_ifar) to 61) ; +iac1_do <= tidn(0 to 62-(eff_ifar)) & + iac1_q(64-(eff_ifar) to 63) & + tidn(62 to 63) ; +ex5_iac2_di <= ex5_spr_wd(62-(eff_ifar) to 61) ; +iac2_do <= tidn(0 to 62-(eff_ifar)) & + iac2_q(64-(eff_ifar) to 63) & + tidn(62 to 63) ; +ex5_iac3_di <= ex5_spr_wd(62-(eff_ifar) to 61) ; +iac3_do <= tidn(0 to 62-(eff_ifar)) & + iac3_q(64-(eff_ifar) to 63) & + tidn(62 to 63) ; +ex5_iac4_di <= ex5_spr_wd(62-(eff_ifar) to 61) ; +iac4_do <= tidn(0 to 62-(eff_ifar)) & + iac4_q(64-(eff_ifar) to 63) & + tidn(62 to 63) ; +ex5_ivpr_di <= ex5_spr_wd(52-(eff_ifar-10) to 51); +ivpr_do <= tidn(0 to 52-(eff_ifar-10)) & + ivpr_q(64-(eff_ifar-10) to 63) & + tidn(52 to 63) ; +ex5_xucr3_di <= ex5_spr_wd(32 to 35) & + ex5_spr_wd(36 to 39) & + ex5_spr_wd(40 to 43) & + ex5_spr_wd(44 to 47) & + ex5_spr_wd(48 to 51) & + ex5_spr_wd(52 to 55) & + ex5_spr_wd(56 to 59) & + ex5_spr_wd(60 to 63) ; +xucr3_do <= tidn(0 to 0) & + tidn(0 to 31) & + xucr3_q(32 to 35) & + xucr3_q(36 to 39) & + xucr3_q(40 to 43) & + xucr3_q(44 to 47) & + xucr3_q(48 to 51) & + xucr3_q(52 to 55) & + xucr3_q(56 to 59) & + xucr3_q(60 to 63) ; +ex5_xucr4_di <= ex5_spr_wd(46 to 46) & + ex5_spr_wd(47 to 47) & + ex5_spr_wd(48 to 55) & + ex5_spr_wd(58 to 58) & + ex5_spr_wd(59 to 59) & + ex5_spr_wd(60 to 63) ; +xucr4_do <= tidn(0 to 0) & + tidn(0 to 31) & + tidn(32 to 45) & + xucr4_q(48 to 48) & + xucr4_q(49 to 49) & + xucr4_q(50 to 57) & + tidn(56 to 57) & + xucr4_q(58 to 58) & + xucr4_q(59 to 59) & + xucr4_q(60 to 63) ; + +mark_unused(givpr_do(0 to 64-regsize)); +mark_unused(iac1_do(0 to 64-regsize)); +mark_unused(iac2_do(0 to 64-regsize)); +mark_unused(iac3_do(0 to 64-regsize)); +mark_unused(iac4_do(0 to 64-regsize)); +mark_unused(ivpr_do(0 to 64-regsize)); +mark_unused(xucr3_do(0 to 64-regsize)); +mark_unused(xucr4_do(0 to 64-regsize)); + +givpr_latch_gen : if hvmode = 1 generate +givpr_latch : tri_ser_rlmreg_p +generic map(width => givpr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => givpr_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(givpr_offset to givpr_offset + givpr_q'length-1), + scout => sov(givpr_offset to givpr_offset + givpr_q'length-1), + din => givpr_d, + dout => givpr_q); +end generate; +givpr_latch_tie : if hvmode = 0 generate + givpr_q <= (others=>'0'); +end generate; +iac1_latch : tri_ser_rlmreg_p +generic map(width => iac1_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => iac1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(iac1_offset to iac1_offset + iac1_q'length-1), + scout => sov(iac1_offset to iac1_offset + iac1_q'length-1), + din => iac1_d, + dout => iac1_q); +iac2_latch : tri_ser_rlmreg_p +generic map(width => iac2_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => iac2_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(iac2_offset to iac2_offset + iac2_q'length-1), + scout => sov(iac2_offset to iac2_offset + iac2_q'length-1), + din => iac2_d, + dout => iac2_q); +iac3_latch_gen : if a2mode = 1 generate +iac3_latch : tri_ser_rlmreg_p +generic map(width => iac3_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => iac3_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(iac3_offset to iac3_offset + iac3_q'length-1), + scout => sov(iac3_offset to iac3_offset + iac3_q'length-1), + din => iac3_d, + dout => iac3_q); +end generate; +iac3_latch_tie : if a2mode = 0 generate + iac3_q <= (others=>'0'); +end generate; +iac4_latch_gen : if a2mode = 1 generate +iac4_latch : tri_ser_rlmreg_p +generic map(width => iac4_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => iac4_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(iac4_offset to iac4_offset + iac4_q'length-1), + scout => sov(iac4_offset to iac4_offset + iac4_q'length-1), + din => iac4_d, + dout => iac4_q); +end generate; +iac4_latch_tie : if a2mode = 0 generate + iac4_q <= (others=>'0'); +end generate; +ivpr_latch : tri_ser_rlmreg_p +generic map(width => ivpr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => ivpr_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ivpr_offset to ivpr_offset + ivpr_q'length-1), + scout => sov(ivpr_offset to ivpr_offset + ivpr_q'length-1), + din => ivpr_d, + dout => ivpr_q); +xucr3_latch : tri_ser_rlmreg_p +generic map(width => xucr3_q'length, init => 37753921, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => xucr3_act, + forcee => dcfg_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => dcfg_sl_thold_0_b, + sg => sg_0, + scin => siv_dcfg(xucr3_offset_dcfg to xucr3_offset_dcfg + xucr3_q'length-1), + scout => sov_dcfg(xucr3_offset_dcfg to xucr3_offset_dcfg + xucr3_q'length-1), + din => xucr3_d, + dout => xucr3_q); +xucr4_latch : tri_ser_rlmreg_p +generic map(width => xucr4_q'length, init => 320, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => xucr4_act, + forcee => dcfg_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => dcfg_sl_thold_0_b, + sg => sg_0, + scin => siv_dcfg(xucr4_offset_dcfg to xucr4_offset_dcfg + xucr4_q'length-1), + scout => sov_dcfg(xucr4_offset_dcfg to xucr4_offset_dcfg + xucr4_q'length-1), + din => xucr4_d, + dout => xucr4_q); + + +mark_unused(tidn(46 to 51)); + +ex2_is_mfspr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_is_mfspr_offset), + scout => sov(ex2_is_mfspr_offset), + din => ex1_is_mfspr, + dout => ex2_is_mfspr_q); +ex2_is_mtspr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_is_mtspr_offset), + scout => sov(ex2_is_mtspr_offset), + din => ex1_is_mtspr, + dout => ex2_is_mtspr_q); +ex2_instr_latch : tri_rlmreg_p + generic map (width => ex2_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_instr_offset to ex2_instr_offset + ex2_instr_q'length-1), + scout => sov(ex2_instr_offset to ex2_instr_offset + ex2_instr_q'length-1), + din => ex1_instr, + dout => ex2_instr_q); +ex3_is_mtspr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_mtspr_offset), + scout => sov(ex3_is_mtspr_offset), + din => ex2_is_mtspr_q, + dout => ex3_is_mtspr_q); +ex3_instr_latch : tri_rlmreg_p + generic map (width => ex3_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_instr_offset to ex3_instr_offset + ex3_instr_q'length-1), + scout => sov(ex3_instr_offset to ex3_instr_offset + ex3_instr_q'length-1), + din => ex2_instr_q, + dout => ex3_instr_q); +ex3_spr_rt_latch : tri_rlmreg_p + generic map (width => ex3_spr_rt_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_spr_rt_offset to ex3_spr_rt_offset + ex3_spr_rt_q'length-1), + scout => sov(ex3_spr_rt_offset to ex3_spr_rt_offset + ex3_spr_rt_q'length-1), + din => ex3_spr_rt_d, + dout => ex3_spr_rt_q); +ex3_iac1_cmpr_latch : tri_rlmreg_p + generic map (width => ex3_iac1_cmpr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_iac1_cmpr_offset to ex3_iac1_cmpr_offset + ex3_iac1_cmpr_q'length-1), + scout => sov(ex3_iac1_cmpr_offset to ex3_iac1_cmpr_offset + ex3_iac1_cmpr_q'length-1), + din => ex3_iac1_cmpr_d, + dout => ex3_iac1_cmpr_q); +ex3_iac2_cmpr_latch : tri_rlmreg_p + generic map (width => ex3_iac2_cmpr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_iac2_cmpr_offset to ex3_iac2_cmpr_offset + ex3_iac2_cmpr_q'length-1), + scout => sov(ex3_iac2_cmpr_offset to ex3_iac2_cmpr_offset + ex3_iac2_cmpr_q'length-1), + din => ex3_iac2_cmpr_d, + dout => ex3_iac2_cmpr_q); +ex3_iac3_cmpr_latch : tri_rlmreg_p + generic map (width => ex3_iac3_cmpr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_iac3_cmpr_offset to ex3_iac3_cmpr_offset + ex3_iac3_cmpr_q'length-1), + scout => sov(ex3_iac3_cmpr_offset to ex3_iac3_cmpr_offset + ex3_iac3_cmpr_q'length-1), + din => ex3_iac3_cmpr_d, + dout => ex3_iac3_cmpr_q); +ex3_iac4_cmpr_latch : tri_rlmreg_p + generic map (width => ex3_iac4_cmpr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_iac4_cmpr_offset to ex3_iac4_cmpr_offset + ex3_iac4_cmpr_q'length-1), + scout => sov(ex3_iac4_cmpr_offset to ex3_iac4_cmpr_offset + ex3_iac4_cmpr_q'length-1), + din => ex3_iac4_cmpr_d, + dout => ex3_iac4_cmpr_q); +ex4_is_mtspr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_is_mtspr_offset), + scout => sov(ex4_is_mtspr_offset), + din => ex3_is_mtspr_q, + dout => ex4_is_mtspr_q); +ex4_instr_latch : tri_rlmreg_p + generic map (width => ex4_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_instr_offset to ex4_instr_offset + ex4_instr_q'length-1), + scout => sov(ex4_instr_offset to ex4_instr_offset + ex4_instr_q'length-1), + din => ex3_instr_q, + dout => ex4_instr_q); +ex5_is_mtspr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_is_mtspr_offset), + scout => sov(ex5_is_mtspr_offset), + din => ex4_is_mtspr_q, + dout => ex5_is_mtspr_q); +ex5_instr_latch : tri_rlmreg_p + generic map (width => ex5_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_instr_offset to ex5_instr_offset + ex5_instr_q'length-1), + scout => sov(ex5_instr_offset to ex5_instr_offset + ex5_instr_q'length-1), + din => ex4_instr_q, + dout => ex5_instr_q); + +dbcr1_iacm_gen : for t in 0 to threads-1 generate +dbcr1_iac12m_2_latch : tri_regk + generic map (width => dbcr1_iac12m_2_q(t)'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => dbcr1_iac12m_2_d(t), + dout => dbcr1_iac12m_2_q(t)); +dbcr1_iac34m_2_latch : tri_regk + generic map (width => dbcr1_iac34m_2_q(t)'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => dbcr1_iac34m_2_d(t), + dout => dbcr1_iac34m_2_q(t)); +dbcr1_iac12m_2_d(t) <= (others=>dbcr1_iac12m_q(t)); +dbcr1_iac34m_2_d(t) <= (others=>dbcr1_iac34m_q(t)); +end generate; + +iac1_en_latch : tri_rlmreg_p + generic map (width => iac1_en_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(iac1_en_offset to iac1_en_offset + iac1_en_q'length-1), + scout => sov(iac1_en_offset to iac1_en_offset + iac1_en_q'length-1), + din => spr_cpl_iac1_en , + dout => iac1_en_q); +iac2_en_latch : tri_rlmreg_p + generic map (width => iac2_en_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(iac2_en_offset to iac2_en_offset + iac2_en_q'length-1), + scout => sov(iac2_en_offset to iac2_en_offset + iac2_en_q'length-1), + din => spr_cpl_iac2_en , + dout => iac2_en_q); +iac3_en_latch : tri_rlmreg_p + generic map (width => iac3_en_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(iac3_en_offset to iac3_en_offset + iac3_en_q'length-1), + scout => sov(iac3_en_offset to iac3_en_offset + iac3_en_q'length-1), + din => spr_cpl_iac3_en , + dout => iac3_en_q); +iac4_en_latch : tri_rlmreg_p + generic map (width => iac4_en_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(iac4_en_offset to iac4_en_offset + iac4_en_q'length-1), + scout => sov(iac4_en_offset to iac4_en_offset + iac4_en_q'length-1), + din => spr_cpl_iac4_en , + dout => iac4_en_q); +dbcr1_iac12m_latch : tri_rlmreg_p + generic map (width => dbcr1_iac12m_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dbcr1_iac12m_offset to dbcr1_iac12m_offset + dbcr1_iac12m_q'length-1), + scout => sov(dbcr1_iac12m_offset to dbcr1_iac12m_offset + dbcr1_iac12m_q'length-1), + din => spr_dbcr1_iac12m, + dout => dbcr1_iac12m_q); +dbcr1_iac34m_latch : tri_rlmreg_p + generic map (width => dbcr1_iac34m_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dbcr1_iac34m_offset to dbcr1_iac34m_offset + dbcr1_iac34m_q'length-1), + scout => sov(dbcr1_iac34m_offset to dbcr1_iac34m_offset + dbcr1_iac34m_q'length-1), + din => spr_dbcr1_iac34m, + dout => dbcr1_iac34m_q); + +siv(0 to scan_right-1) <= sov(1 to scan_right-1) & scan_in; +scan_out <= sov(0); + + +dcfg_l : if sov_dcfg'length > 1 generate +siv_dcfg(0 to scan_right_dcfg-1) <= sov_dcfg(1 to scan_right_dcfg-1) & dcfg_scan_in; +dcfg_scan_out <= sov_dcfg(0); +end generate; +dcfg_s : if sov_dcfg'length <= 1 generate +dcfg_scan_out <= dcfg_scan_in; +sov_dcfg <= (others=>'0'); +siv_dcfg <= (others=>'0'); +end generate; + +end architecture xuq_cpl_spr_cspr; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_cpl_spr_tspr.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_cpl_spr_tspr.vhdl new file mode 100644 index 0000000..7b65ce6 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_cpl_spr_tspr.vhdl @@ -0,0 +1,281 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee,ibm,support,work,tri; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use support.power_logic_pkg.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use tri.tri_latches_pkg.all; +use work.xuq_pkg.all; + +entity xuq_cpl_spr_tspr is +generic( + hvmode : integer := 1; + a2mode : integer := 1; + expand_type : integer := 2; + regsize : integer := 64; + eff_ifar : integer := 62); +port( + nclk : in clk_logic; + d_mode_dc : in std_ulogic; + delay_lclkr_dc : in std_ulogic; + mpw1_dc_b : in std_ulogic; + mpw2_dc_b : in std_ulogic; + func_sl_force : in std_ulogic; + func_sl_thold_0_b : in std_ulogic; + sg_0 : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + cspr_tspr_ex2_instr : in std_ulogic_vector(11 to 20); + tspr_cspr_ex2_tspr_rt : out std_ulogic_vector(64-regsize to 63); + + ex5_val : in std_ulogic; + cspr_tspr_ex5_is_mtspr : in std_ulogic; + cspr_tspr_ex5_instr : in std_ulogic_vector(11 to 20); + ex5_spr_wd : in std_ulogic_vector(64-regsize to 63); + ex5_cia_p1 : in std_ulogic_vector(62-eff_ifar to 61); + + ex4_lr_update : in std_ulogic; + ex4_ctr_dec_update : in std_ulogic; + + + spr_iar : in std_ulogic_vector(62-eff_ifar to 61); + spr_ctr : out std_ulogic_vector(0 to regsize-1); + spr_lr : out std_ulogic_vector(0 to regsize-1); + + vdd : inout power_logic; + gnd : inout power_logic +); + +-- synopsys translate_off + +-- synopsys translate_on +end xuq_cpl_spr_tspr; +architecture xuq_cpl_spr_tspr of xuq_cpl_spr_tspr is + +subtype DO is std_ulogic_vector(65-regsize to 64); +signal ctr_d , ctr_q : std_ulogic_vector(64-(regsize) to 63); +signal lr_d , lr_q : std_ulogic_vector(64-(regsize) to 63); +constant ctr_offset : natural := 0; +constant lr_offset : natural := ctr_offset + ctr_q'length; +constant last_reg_offset : natural := lr_offset + lr_q'length; +constant last_reg_offset_bcfg : natural := 1; +constant last_reg_offset_ccfg : natural := 1; +constant last_reg_offset_dcfg : natural := 1; +signal ex5_lr_update_q : std_ulogic; +signal ex5_ctr_dec_update_q : std_ulogic; +constant ex5_lr_update_offset : integer := last_reg_offset; +constant ex5_ctr_dec_update_offset : integer := ex5_lr_update_offset + 1; +constant scan_right : integer := ex5_ctr_dec_update_offset + 1; +signal siv : std_ulogic_vector(0 to scan_right-1); +signal sov : std_ulogic_vector(0 to scan_right-1); +signal tiup : std_ulogic; +signal tidn : std_ulogic_vector(00 to 63); +signal ex2_instr : std_ulogic_vector(11 to 20); +signal ex5_is_mtspr : std_ulogic; +signal ex5_instr : std_ulogic_vector(11 to 20); +signal ex5_lr_update : std_ulogic; +signal ex5_ctr_dec_update : std_ulogic; +signal spr_iar_int : std_ulogic_vector(0 to 62); + +signal ex5_ctr_di : std_ulogic_vector(ctr_q'range); +signal ex5_lr_di : std_ulogic_vector(lr_q'range); +signal + ex2_ctr_rdec , ex2_iar_rdec , ex2_lr_rdec + : std_ulogic; +signal + ex2_ctr_re , ex2_iar_re , ex2_lr_re + : std_ulogic; +signal + ex5_ctr_wdec , ex5_iar_wdec , ex5_lr_wdec + : std_ulogic; +signal + ex5_ctr_we , ex5_iar_we , ex5_lr_we + : std_ulogic; +signal + ctr_act , iar_act , lr_act + : std_ulogic; +signal + ctr_do , iar_do , lr_do + : std_ulogic_vector(0 to 64); + +begin + + +tiup <= '1'; +tidn <= (others=>'0'); +ex2_instr <= cspr_tspr_ex2_instr; +ex5_is_mtspr <= cspr_tspr_ex5_is_mtspr; +ex5_instr <= cspr_tspr_ex5_instr; + +ex5_lr_update <= ex5_val and ex5_lr_update_q; +ex5_ctr_dec_update <= ex5_val and ex5_ctr_dec_update_q; + +spr_iar_int <= tidn(0 to 62-eff_ifar) & spr_iar; + +ctr_act <= ex5_ctr_we or ex5_ctr_dec_update; + +with ex5_ctr_dec_update_q select + ctr_d <= std_ulogic_vector(unsigned(ctr_q) - 1) when '1', + ex5_ctr_di when others; + +iar_act <= tiup; + +lr_act <= ex5_lr_we or ex5_lr_update; + +with ex5_lr_update select + lr_d <= ex5_cia_p1 & "00" when '1', + ex5_lr_di when others; + + + + +readmux_00 : if a2mode = 0 and hvmode = 0 generate +tspr_cspr_ex2_tspr_rt <= + (ctr_do(DO'range) and (DO'range => ex2_ctr_re )) or + (iar_do(DO'range) and (DO'range => ex2_iar_re )) or + (lr_do(DO'range) and (DO'range => ex2_lr_re )); +end generate; +readmux_01 : if a2mode = 0 and hvmode = 1 generate +tspr_cspr_ex2_tspr_rt <= + (ctr_do(DO'range) and (DO'range => ex2_ctr_re )) or + (iar_do(DO'range) and (DO'range => ex2_iar_re )) or + (lr_do(DO'range) and (DO'range => ex2_lr_re )); +end generate; +readmux_10 : if a2mode = 1 and hvmode = 0 generate +tspr_cspr_ex2_tspr_rt <= + (ctr_do(DO'range) and (DO'range => ex2_ctr_re )) or + (iar_do(DO'range) and (DO'range => ex2_iar_re )) or + (lr_do(DO'range) and (DO'range => ex2_lr_re )); +end generate; +readmux_11 : if a2mode = 1 and hvmode = 1 generate +tspr_cspr_ex2_tspr_rt <= + (ctr_do(DO'range) and (DO'range => ex2_ctr_re )) or + (iar_do(DO'range) and (DO'range => ex2_iar_re )) or + (lr_do(DO'range) and (DO'range => ex2_lr_re )); +end generate; + +ex2_ctr_rdec <= (ex2_instr(11 to 20) = "0100100000"); +ex2_iar_rdec <= (ex2_instr(11 to 20) = "1001011011"); +ex2_lr_rdec <= (ex2_instr(11 to 20) = "0100000000"); +ex2_ctr_re <= ex2_ctr_rdec; +ex2_iar_re <= ex2_iar_rdec; +ex2_lr_re <= ex2_lr_rdec; + +ex5_ctr_wdec <= (ex5_instr(11 to 20) = "0100100000"); +ex5_iar_wdec <= (ex5_instr(11 to 20) = "1001011011"); +ex5_lr_wdec <= (ex5_instr(11 to 20) = "0100000000"); +ex5_ctr_we <= ex5_val and ex5_is_mtspr and ex5_ctr_wdec; +ex5_iar_we <= ex5_val and ex5_is_mtspr and ex5_iar_wdec; +ex5_lr_we <= ex5_val and ex5_is_mtspr and ex5_lr_wdec; + +spr_ctr <= ctr_q(64-(regsize) to 63); +spr_lr <= lr_q(64-(regsize) to 63); + +ex5_ctr_di <= ex5_spr_wd(64-(regsize) to 63) ; +ctr_do <= tidn(0 to 64-(regsize)) & + ctr_q(64-(regsize) to 63) ; +iar_do <= tidn(0 to 0) & + spr_iar_int(1 to 62) & + tidn(62 to 63) ; +ex5_lr_di <= ex5_spr_wd(64-(regsize) to 63) ; +lr_do <= tidn(0 to 64-(regsize)) & + lr_q(64-(regsize) to 63) ; + +mark_unused(ctr_do(0 to 64-regsize)); +mark_unused(iar_do(0 to 64-regsize)); +mark_unused(lr_do(0 to 64-regsize)); + +ctr_latch : tri_ser_rlmreg_p +generic map(width => ctr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => ctr_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ctr_offset to ctr_offset + ctr_q'length-1), + scout => sov(ctr_offset to ctr_offset + ctr_q'length-1), + din => ctr_d, + dout => ctr_q); +lr_latch : tri_ser_rlmreg_p +generic map(width => lr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => lr_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(lr_offset to lr_offset + lr_q'length-1), + scout => sov(lr_offset to lr_offset + lr_q'length-1), + din => lr_d, + dout => lr_q); + + +mark_unused(tidn(1 to 61)); +mark_unused(spr_iar_int(0)); +mark_unused(iar_act); +mark_unused(ex5_iar_we); + +ex5_lr_update_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_lr_update_offset), + scout => sov(ex5_lr_update_offset), + din => ex4_lr_update, + dout => ex5_lr_update_q); +ex5_ctr_dec_update_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_ctr_dec_update_offset), + scout => sov(ex5_ctr_dec_update_offset), + din => ex4_ctr_dec_update, + dout => ex5_ctr_dec_update_q); + +siv(0 to scan_right-1) <= sov(1 to scan_right-1) & scan_in; +scan_out <= sov(0); + + +end architecture xuq_cpl_spr_tspr; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_ctrl.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_ctrl.vhdl new file mode 100644 index 0000000..fac40db --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_ctrl.vhdl @@ -0,0 +1,2206 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee,ibm,support,work,tri,clib; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use support.power_logic_pkg.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use tri.tri_latches_pkg.all; +use work.xuq_pkg.all; + +entity xuq_ctrl is +generic( + expand_type : integer := 2; + threads : integer := 4; + eff_ifar : integer := 62; + uc_ifar : integer := 21; + regsize : integer := 64; + hvmode : integer := 1; + regmode : integer := 6; + dc_size : natural := 14; + cl_size : natural := 6; + real_data_add : integer := 42; + fxu_synth : integer := 0; + a2mode : integer := 1; + lmq_entries : integer := 8; + l_endian_m : integer := 1; + load_credits : integer := 4; + store_credits : integer := 20; + st_data_32B_mode : integer := 1; + bcfg_epn_0to15 : integer := 0; + bcfg_epn_16to31 : integer := 0; + bcfg_epn_32to47 : integer := (2**16)-1; + bcfg_epn_48to51 : integer := (2**4)-1; + bcfg_rpn_22to31 : integer := (2**10)-1; + bcfg_rpn_32to47 : integer := (2**16)-1; + bcfg_rpn_48to51 : integer := (2**4)-1); +port( + + func_scan_in :in std_ulogic_vector(41 to 58); + func_scan_out :out std_ulogic_vector(41 to 58); + an_ac_grffence_en_dc :in std_ulogic; + an_ac_scan_dis_dc_b :in std_ulogic; + an_ac_lbist_en_dc :in std_ulogic; + pc_xu_abist_raddr_0 :in std_ulogic_vector(5 to 9); + pc_xu_abist_ena_dc :in std_ulogic; + pc_xu_abist_waddr_0 :in std_ulogic_vector(5 to 9); + pc_xu_abist_di_0 :in std_ulogic_vector(0 to 3); + pc_xu_abist_raw_dc_b :in std_ulogic; + pc_xu_ccflush_dc :in std_ulogic; + clkoff_dc_b :out std_ulogic; + d_mode_dc :out std_ulogic; + delay_lclkr_dc :out std_ulogic_vector(0 to 4); + mpw1_dc_b :out std_ulogic_vector(0 to 4); + mpw2_dc_b :out std_ulogic; + g6t_clkoff_dc_b :out std_ulogic; + g6t_d_mode_dc :out std_ulogic; + g6t_delay_lclkr_dc :out std_ulogic_vector(0 to 4); + g6t_mpw1_dc_b :out std_ulogic_vector(0 to 4); + g6t_mpw2_dc_b :out std_ulogic; + pc_xu_sg_3 :in std_ulogic_vector(0 to 4); + pc_xu_func_sl_thold_3 :in std_ulogic_vector(0 to 4); + pc_xu_func_slp_sl_thold_3 :in std_ulogic_vector(0 to 4); + pc_xu_func_nsl_thold_3 :in std_ulogic; + pc_xu_func_slp_nsl_thold_3 :in std_ulogic; + pc_xu_gptr_sl_thold_3 :in std_ulogic; + pc_xu_abst_sl_thold_3 :in std_ulogic; + pc_xu_abst_slp_sl_thold_3 :in std_ulogic; + pc_xu_regf_sl_thold_3 :in std_ulogic; + pc_xu_regf_slp_sl_thold_3 :in std_ulogic; + pc_xu_time_sl_thold_3 :in std_ulogic; + pc_xu_cfg_sl_thold_3 :in std_ulogic; + pc_xu_cfg_slp_sl_thold_3 :in std_ulogic; + pc_xu_ary_nsl_thold_3 :in std_ulogic; + pc_xu_ary_slp_nsl_thold_3 :in std_ulogic; + pc_xu_repr_sl_thold_3 :in std_ulogic; + pc_xu_fce_3 :in std_ulogic_vector(0 to 1); + an_ac_scan_diag_dc :in std_ulogic; + sg_2 :out std_ulogic_vector(0 to 3); + fce_2 :out std_ulogic_vector(0 to 1); + func_sl_thold_2 :out std_ulogic_vector(0 to 3); + func_slp_sl_thold_2 :out std_ulogic_vector(0 to 1); + func_nsl_thold_2 :out std_ulogic; + func_slp_nsl_thold_2 :out std_ulogic; + abst_sl_thold_2 :out std_ulogic; + time_sl_thold_2 :out std_ulogic; + gptr_sl_thold_2 :out std_ulogic; + ary_nsl_thold_2 :out std_ulogic; + repr_sl_thold_2 :out std_ulogic; + cfg_sl_thold_2 :out std_ulogic; + cfg_slp_sl_thold_2 :out std_ulogic; + regf_slp_sl_thold_2 :out std_ulogic; + gptr_scan_in :in std_ulogic; + gptr_scan_out :out std_ulogic; + time_scan_in :in std_ulogic; + time_scan_out :out std_ulogic; + pc_xu_bolt_sl_thold_3 :in std_ulogic; + pc_xu_bo_enable_3 :in std_ulogic; + bolt_sl_thold_2 :out std_ulogic; + bo_enable_2 :out std_ulogic; + pc_xu_bo_unload :in std_ulogic; + pc_xu_bo_repair :in std_ulogic; + pc_xu_bo_reset :in std_ulogic; + pc_xu_bo_shdata :in std_ulogic; + pc_xu_bo_select :in std_ulogic_vector(1 to 4); + xu_pc_bo_fail :out std_ulogic_vector(1 to 4); + xu_pc_bo_diagout :out std_ulogic_vector(1 to 4); + + fxa_fxb_rf0_val :in std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_issued :in std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_ucode_val :in std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_act :in std_ulogic; + fxa_fxb_ex1_hold_ctr_flush :in std_ulogic; + fxa_fxb_rf0_instr :in std_ulogic_vector(0 to 31); + fxa_fxb_rf0_tid :in std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_ta_vld :in std_ulogic; + fxa_fxb_rf0_ta :in std_ulogic_vector(0 to 7); + fxa_fxb_rf0_error :in std_ulogic_vector(0 to 2); + fxa_fxb_rf0_match :in std_ulogic; + fxa_fxb_rf0_is_ucode :in std_ulogic; + fxa_fxb_rf0_gshare :in std_ulogic_vector(0 to 3); + fxa_fxb_rf0_ifar :in std_ulogic_vector(62-eff_ifar to 61); + fxa_fxb_rf0_s1_vld :in std_ulogic; + fxa_fxb_rf0_s1 :in std_ulogic_vector(0 to 7); + fxa_fxb_rf0_s2_vld :in std_ulogic; + fxa_fxb_rf0_s2 :in std_ulogic_vector(0 to 7); + fxa_fxb_rf0_s3_vld :in std_ulogic; + fxa_fxb_rf0_s3 :in std_ulogic_vector(0 to 7); + fxa_fxb_rf0_axu_instr_type :in std_ulogic_vector(0 to 2); + fxa_fxb_rf0_axu_ld_or_st :in std_ulogic; + fxa_fxb_rf0_axu_store :in std_ulogic; + fxa_fxb_rf0_axu_ldst_forcealign :in std_ulogic; + fxa_fxb_rf0_axu_ldst_forceexcept :in std_ulogic; + fxa_fxb_rf0_axu_ldst_indexed :in std_ulogic; + fxa_fxb_rf0_axu_ldst_tag :in std_ulogic_vector(0 to 8); + fxa_fxb_rf0_axu_mftgpr :in std_ulogic; + fxa_fxb_rf0_axu_mffgpr :in std_ulogic; + fxa_fxb_rf0_axu_movedp :in std_ulogic; + fxa_fxb_rf0_axu_ldst_size :in std_ulogic_vector(0 to 5); + fxa_fxb_rf0_axu_ldst_update :in std_ulogic; + fxa_fxb_rf0_pred_update :in std_ulogic; + fxa_fxb_rf0_pred_taken_cnt :in std_ulogic_vector(0 to 1); + fxa_fxb_rf0_mc_dep_chk_val :in std_ulogic_vector(0 to threads-1); + fxa_fxb_rf1_mul_val :in std_ulogic; + fxa_fxb_rf1_div_val :in std_ulogic; + fxa_fxb_rf1_div_ctr :in std_ulogic_vector(0 to 7); + fxa_fxb_rf0_xu_epid_instr :in std_ulogic; + fxa_fxb_rf0_axu_is_extload :in std_ulogic; + fxa_fxb_rf0_axu_is_extstore :in std_ulogic; + fxa_fxb_rf0_is_mfocrf :in std_ulogic; + fxa_fxb_rf0_3src_instr :in std_ulogic; + fxa_fxb_rf0_gpr0_zero :in std_ulogic; + fxa_fxb_rf0_use_imm :in std_ulogic; + fxa_fxb_rf1_muldiv_coll :in std_ulogic; + fxa_cpl_ex2_div_coll :in std_ulogic_vector(0 to threads-1); + fxb_fxa_ex7_we0 :out std_ulogic; + fxb_fxa_ex7_wa0 :out std_ulogic_vector(0 to 7); + fxb_fxa_ex7_wd0 :out std_ulogic_vector(64-regsize to 63); + fxa_fxb_rf1_do0 :in std_ulogic_vector(64-regsize to 63); + fxa_fxb_rf1_do1 :in std_ulogic_vector(64-regsize to 63); + fxa_fxb_rf1_do2 :in std_ulogic_vector(64-regsize to 63); + xu_bx_ex1_mtdp_val :out std_ulogic; + xu_bx_ex1_mfdp_val :out std_ulogic; + xu_bx_ex1_ipc_thrd :out std_ulogic_vector(0 to 1); + xu_bx_ex2_ipc_ba :out std_ulogic_vector(0 to 4); + xu_bx_ex2_ipc_sz :out std_ulogic_vector(0 to 1); + + xu_mm_derat_epn :out std_ulogic_vector(62-eff_ifar to 51); + + xu_mm_rf1_is_tlbsxr :out std_ulogic; + mm_xu_cr0_eq_valid :in std_ulogic_vector(0 to threads-1); + mm_xu_cr0_eq :in std_ulogic_vector(0 to threads-1); + + fu_xu_ex4_cr_val :in std_ulogic_vector(0 to threads-1); + fu_xu_ex4_cr_noflush :in std_ulogic_vector(0 to threads-1); + fu_xu_ex4_cr0 :in std_ulogic_vector(0 to 3); + fu_xu_ex4_cr0_bf :in std_ulogic_vector(0 to 2); + fu_xu_ex4_cr1 :in std_ulogic_vector(0 to 3); + fu_xu_ex4_cr1_bf :in std_ulogic_vector(0 to 2); + fu_xu_ex4_cr2 :in std_ulogic_vector(0 to 3); + fu_xu_ex4_cr2_bf :in std_ulogic_vector(0 to 2); + fu_xu_ex4_cr3 :in std_ulogic_vector(0 to 3); + fu_xu_ex4_cr3_bf :in std_ulogic_vector(0 to 2); + + pc_xu_ram_mode :in std_ulogic; + pc_xu_ram_thread :in std_ulogic_vector(0 to 1); + pc_xu_ram_execute :in std_ulogic; + pc_xu_ram_flush_thread :in std_ulogic; + xu_iu_ram_issue :out std_ulogic_vector(0 to threads-1); + xu_pc_ram_interrupt :out std_ulogic; + xu_pc_ram_done :out std_ulogic; + xu_pc_ram_data :out std_ulogic_vector(64-(2**regmode) to 63); + + xu_iu_ex5_val :out std_ulogic; + xu_iu_ex5_tid :out std_ulogic_vector(0 to threads-1); + xu_iu_ex5_br_update :out std_ulogic; + xu_iu_ex5_br_hist :out std_ulogic_vector(0 to 1); + xu_iu_ex5_bclr :out std_ulogic; + xu_iu_ex5_lk :out std_ulogic; + xu_iu_ex5_bh :out std_ulogic_vector(0 to 1); + xu_iu_ex6_pri :out std_ulogic_vector(0 to 2); + xu_iu_ex6_pri_val :out std_ulogic_vector(0 to 3); + xu_iu_spr_xer :out std_ulogic_vector(0 to 7*threads-1); + xu_iu_slowspr_done :out std_ulogic_vector(0 to threads-1); + xu_iu_need_hole :out std_ulogic; + fxb_fxa_ex6_clear_barrier :out std_ulogic_vector(0 to threads-1); + xu_iu_ex5_gshare :out std_ulogic_vector(0 to 3); + xu_iu_ex5_getNIA :out std_ulogic; + + an_ac_stcx_complete :in std_ulogic_vector(0 to threads-1); + an_ac_stcx_pass :in std_ulogic_vector(0 to threads-1); + + slowspr_val_in :in std_ulogic; + slowspr_rw_in :in std_ulogic; + slowspr_etid_in :in std_ulogic_vector(0 to 1); + slowspr_addr_in :in std_ulogic_vector(0 to 9); + slowspr_data_in :in std_ulogic_vector(64-(2**regmode) to 63); + slowspr_done_in :in std_ulogic; + + an_ac_dcr_act :in std_ulogic; + an_ac_dcr_val :in std_ulogic; + an_ac_dcr_read :in std_ulogic; + an_ac_dcr_etid :in std_ulogic_vector(0 to 1); + an_ac_dcr_data :in std_ulogic_vector(64-(2**regmode) to 63); + an_ac_dcr_done :in std_ulogic; + + lsu_xu_ex4_mtdp_cr_status :in std_ulogic; + lsu_xu_ex4_mfdp_cr_status :in std_ulogic; + dec_cpl_ex3_mc_dep_chk_val :in std_ulogic_vector(0 to threads-1); + + dec_spr_ex4_val :out std_ulogic_vector(0 to threads-1); + dec_spr_ex1_epid_instr :out std_ulogic; + mux_spr_ex2_rt :out std_ulogic_vector(64-(2**regmode) to 63); + fxu_spr_ex1_rs0 :out std_ulogic_vector(52 to 63); + fxu_spr_ex1_rs1 :out std_ulogic_vector(54 to 63); + spr_msr_cm :in std_ulogic_vector(0 to threads-1); + spr_dec_spr_xucr0_ssdly :in std_ulogic_vector(0 to 4); + spr_ccr2_en_attn :in std_ulogic; + spr_ccr2_en_ditc :in std_ulogic; + spr_ccr2_en_pc :in std_ulogic; + spr_ccr2_en_icswx :in std_ulogic; + spr_ccr2_en_dcr :in std_ulogic; + spr_dec_rf1_epcr_dgtmi :in std_ulogic_vector(0 to threads-1); + spr_byp_ex4_is_mfxer :in std_ulogic_vector(0 to threads-1); + spr_byp_ex3_spr_rt :in std_ulogic_vector(64-(2**regmode) to 63); + spr_byp_ex4_is_mtxer :in std_ulogic_vector(0 to threads-1); + spr_ccr2_notlb :in std_ulogic; + dec_spr_rf1_val :out std_ulogic_vector(0 to threads-1); + fxu_spr_ex1_rs2 :out std_ulogic_vector(42 to 55); + + fxa_perf_muldiv_in_use :in std_ulogic; + spr_perf_tx_events :in std_ulogic_vector(0 to 8*threads-1); + xu_pc_event_data :out std_ulogic_vector(0 to 7); + + pc_xu_event_count_mode :in std_ulogic_vector(0 to 2); + pc_xu_event_mux_ctrls :in std_ulogic_vector(0 to 47); + + fxu_debug_mux_ctrls :in std_ulogic_vector(0 to 15); + cpl_debug_mux_ctrls :in std_ulogic_vector(0 to 15); + lsu_debug_mux_ctrls :in std_ulogic_vector(0 to 15); + ctrl_trigger_data_in :in std_ulogic_vector(0 to 11); + ctrl_trigger_data_out :out std_ulogic_vector(0 to 11); + ctrl_debug_data_in :in std_ulogic_vector(0 to 87); + ctrl_debug_data_out :out std_ulogic_vector(0 to 87); + lsu_xu_data_debug0 :in std_ulogic_vector(0 to 87); + lsu_xu_data_debug1 :in std_ulogic_vector(0 to 87); + lsu_xu_data_debug2 :in std_ulogic_vector(0 to 87); + fxa_cpl_debug :in std_ulogic_vector(0 to 272); + + spr_msr_gs :in std_ulogic_vector(0 to threads-1); + spr_msr_ds :in std_ulogic_vector(0 to threads-1); + spr_msr_pr :in std_ulogic_vector(0 to threads-1); + spr_dbcr0_dac1 :in std_ulogic_vector(0 to 2*threads-1); + spr_dbcr0_dac2 :in std_ulogic_vector(0 to 2*threads-1); + spr_dbcr0_dac3 :in std_ulogic_vector(0 to 2*threads-1); + spr_dbcr0_dac4 :in std_ulogic_vector(0 to 2*threads-1); + + ac_tc_debug_trigger :out std_ulogic_vector(0 to threads-1); + + bcfg_scan_in :in std_ulogic; + bcfg_scan_out :out std_ulogic; + dcfg_scan_in :in std_ulogic; + dcfg_scan_out :out std_ulogic; + + dec_cpl_rf0_act :in std_ulogic; + dec_cpl_rf0_tid :in std_ulogic_vector(0 to threads-1); + + fu_xu_rf1_act :in std_ulogic_vector(0 to threads-1); + fu_xu_ex1_ifar :in std_ulogic_vector(0 to eff_ifar*threads-1); + fu_xu_ex2_ifar_val :in std_ulogic_vector(0 to threads-1); + fu_xu_ex2_ifar_issued :in std_ulogic_vector(0 to threads-1); + fu_xu_ex2_instr_type :in std_ulogic_vector(0 to 3*threads-1); + fu_xu_ex2_instr_match :in std_ulogic_vector(0 to threads-1); + fu_xu_ex2_is_ucode :in std_ulogic_vector(0 to threads-1); + + pc_xu_step :in std_ulogic_vector(0 to threads-1); + pc_xu_stop :in std_ulogic_vector(0 to threads-1); + pc_xu_dbg_action :in std_ulogic_vector(0 to 3*threads-1); + pc_xu_force_ude :in std_ulogic_vector(0 to threads-1); + xu_pc_step_done :out std_ulogic_vector(0 to threads-1); + pc_xu_init_reset :in std_ulogic; + + spr_cpl_ext_interrupt :in std_ulogic_vector(0 to threads-1); + spr_cpl_udec_interrupt :in std_ulogic_vector(0 to threads-1); + spr_cpl_perf_interrupt :in std_ulogic_vector(0 to threads-1); + spr_cpl_dec_interrupt :in std_ulogic_vector(0 to threads-1); + spr_cpl_fit_interrupt :in std_ulogic_vector(0 to threads-1); + spr_cpl_crit_interrupt :in std_ulogic_vector(0 to threads-1); + spr_cpl_wdog_interrupt :in std_ulogic_vector(0 to threads-1); + spr_cpl_dbell_interrupt :in std_ulogic_vector(0 to threads-1); + spr_cpl_cdbell_interrupt :in std_ulogic_vector(0 to threads-1); + spr_cpl_gdbell_interrupt :in std_ulogic_vector(0 to threads-1); + spr_cpl_gcdbell_interrupt :in std_ulogic_vector(0 to threads-1); + spr_cpl_gmcdbell_interrupt :in std_ulogic_vector(0 to threads-1); + + cpl_spr_ex5_dbell_taken :out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_cdbell_taken :out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_gdbell_taken :out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_gcdbell_taken :out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_gmcdbell_taken :out std_ulogic_vector(0 to threads-1); + + cpl_spr_ex5_act :out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_int :out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_gint :out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_cint :out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_mcint :out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_nia :out std_ulogic_vector(0 to eff_ifar*threads-1); + cpl_spr_ex5_esr :out std_ulogic_vector(0 to 17*threads-1); + cpl_spr_ex5_mcsr :out std_ulogic_vector(0 to 15*threads-1); + cpl_spr_ex5_dbsr :out std_ulogic_vector(0 to 19*threads-1); + cpl_spr_ex5_dear_save :out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_dear_update_saved :out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_dear_update :out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_dbsr_update :out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_esr_update :out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_srr0_dec :out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_force_gsrr :out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_dbsr_ide :out std_ulogic_vector(0 to threads-1); + + spr_cpl_dbsr_ide :in std_ulogic_vector(0 to threads-1); + + mm_xu_local_snoop_reject :in std_ulogic_vector(0 to threads-1); + mm_xu_lru_par_err :in std_ulogic_vector(0 to threads-1); + mm_xu_tlb_par_err :in std_ulogic_vector(0 to threads-1); + mm_xu_tlb_multihit_err :in std_ulogic_vector(0 to threads-1); + spr_cpl_external_mchk :in std_ulogic_vector(0 to threads-1); + + xu_pc_err_attention_instr :out std_ulogic_vector(0 to threads-1); + xu_pc_err_nia_miscmpr :out std_ulogic_vector(0 to threads-1); + xu_pc_err_debug_event :out std_ulogic_vector(0 to threads-1); + + spr_cpl_ex3_ct_le :in std_ulogic_vector(0 to threads-1); + spr_cpl_ex3_ct_be :in std_ulogic_vector(0 to threads-1); + + spr_cpl_ex3_spr_illeg :in std_ulogic; + spr_cpl_ex3_spr_priv :in std_ulogic; + + spr_cpl_ex3_spr_hypv :in std_logic; + + cpl_spr_stop :out std_ulogic_vector(0 to threads-1); + xu_pc_stop_dbg_event :out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_instr_cpl :out std_ulogic_vector(0 to threads-1); + spr_cpl_quiesce :in std_ulogic_vector(0 to threads-1); + cpl_spr_quiesce :out std_ulogic_vector(0 to threads-1); + spr_cpl_ex2_run_ctl_flush :in std_ulogic_vector(0 to threads-1); + + mm_xu_illeg_instr :in std_ulogic_vector(0 to threads-1); + mm_xu_tlb_miss :in std_ulogic_vector(0 to threads-1); + mm_xu_pt_fault :in std_ulogic_vector(0 to threads-1); + mm_xu_tlb_inelig :in std_ulogic_vector(0 to threads-1); + mm_xu_lrat_miss :in std_ulogic_vector(0 to threads-1); + mm_xu_hv_priv :in std_ulogic_vector(0 to threads-1); + mm_xu_esr_pt :in std_ulogic_vector(0 to threads-1); + mm_xu_esr_data :in std_ulogic_vector(0 to threads-1); + mm_xu_esr_epid :in std_ulogic_vector(0 to threads-1); + mm_xu_esr_st :in std_ulogic_vector(0 to threads-1); + mm_xu_hold_req :in std_ulogic_vector(0 to threads-1); + mm_xu_hold_done :in std_ulogic_vector(0 to threads-1); + xu_mm_hold_ack :out std_ulogic_vector(0 to threads-1); + mm_xu_eratmiss_done :in std_ulogic_vector(0 to threads-1); + mm_xu_ex3_flush_req :in std_ulogic_vector(0 to threads-1); + + fu_xu_ex3_ap_int_req :in std_ulogic_vector(0 to threads-1); + fu_xu_ex3_trap :in std_ulogic_vector(0 to threads-1); + fu_xu_ex3_n_flush :in std_ulogic_vector(0 to threads-1); + fu_xu_ex3_np1_flush :in std_ulogic_vector(0 to threads-1); + fu_xu_ex3_flush2ucode :in std_ulogic_vector(0 to threads-1); + fu_xu_ex2_async_block :in std_ulogic_vector(0 to threads-1); + + xu_iu_ex5_br_taken :out std_ulogic; + xu_iu_ex5_ifar :out std_ulogic_vector(62-eff_ifar to 61); + xu_iu_flush :out std_ulogic_vector(0 to threads-1); + xu_iu_iu0_flush_ifar :out std_ulogic_vector(0 to eff_ifar*threads-1); + xu_iu_uc_flush_ifar :out std_ulogic_vector(0 to uc_ifar*threads-1); + xu_iu_flush_2ucode :out std_ulogic_vector(0 to threads-1); + xu_iu_flush_2ucode_type :out std_ulogic_vector(0 to threads-1); + xu_iu_ucode_restart :out std_ulogic_vector(0 to threads-1); + xu_iu_ex5_ppc_cpl :out std_ulogic_vector(0 to threads-1); + + xu_n_is2_flush : out std_ulogic_vector(0 to threads-1); + xu_n_rf0_flush : out std_ulogic_vector(0 to threads-1); + xu_n_rf1_flush : out std_ulogic_vector(0 to threads-1); + xu_n_ex1_flush : out std_ulogic_vector(0 to threads-1); + xu_n_ex2_flush : out std_ulogic_vector(0 to threads-1); + xu_n_ex3_flush : out std_ulogic_vector(0 to threads-1); + xu_n_ex4_flush : out std_ulogic_vector(0 to threads-1); + xu_n_ex5_flush : out std_ulogic_vector(0 to threads-1); + + xu_s_rf1_flush : out std_ulogic_vector(0 to threads-1); + xu_s_ex1_flush : out std_ulogic_vector(0 to threads-1); + xu_s_ex2_flush : out std_ulogic_vector(0 to threads-1); + xu_s_ex3_flush : out std_ulogic_vector(0 to threads-1); + xu_s_ex4_flush : out std_ulogic_vector(0 to threads-1); + xu_s_ex5_flush : out std_ulogic_vector(0 to threads-1); + + xu_w_rf1_flush : out std_ulogic_vector(0 to threads-1); + xu_w_ex1_flush : out std_ulogic_vector(0 to threads-1); + xu_w_ex2_flush : out std_ulogic_vector(0 to threads-1); + xu_w_ex3_flush : out std_ulogic_vector(0 to threads-1); + xu_w_ex4_flush : out std_ulogic_vector(0 to threads-1); + xu_w_ex5_flush : out std_ulogic_vector(0 to threads-1); + + xu_lsu_ex4_flush_local :out std_ulogic_vector(0 to threads-1); + xu_mm_ex4_flush :out std_ulogic_vector(0 to threads-1); + xu_mm_ex5_flush :out std_ulogic_vector(0 to threads-1); + xu_mm_ierat_flush :out std_ulogic_vector(0 to threads-1); + xu_mm_ierat_miss :out std_ulogic_vector(0 to threads-1); + xu_mm_ex5_perf_itlb :out std_ulogic_vector(0 to threads-1); + xu_mm_ex5_perf_dtlb :out std_ulogic_vector(0 to threads-1); + + spr_bit_act :in std_ulogic; + spr_epcr_duvd :in std_ulogic_vector(0 to threads-1); + spr_cpl_iac1_en :in std_ulogic_vector(0 to threads-1); + spr_cpl_iac2_en :in std_ulogic_vector(0 to threads-1); + spr_cpl_iac3_en :in std_ulogic_vector(0 to threads-1); + spr_cpl_iac4_en :in std_ulogic_vector(0 to threads-1); + spr_dbcr1_iac12m :in std_ulogic_vector(0 to threads-1); + spr_dbcr1_iac34m :in std_ulogic_vector(0 to threads-1); + spr_cpl_fp_precise :in std_ulogic_vector(0 to threads-1); + spr_xucr0_mddp :in std_ulogic; + spr_xucr0_mdcp :in std_ulogic; + spr_msr_de :in std_ulogic_vector(0 to threads-1); + spr_msr_spv :in std_ulogic_vector(0 to threads-1); + spr_msr_fp :in std_ulogic_vector(0 to threads-1); + spr_msr_me :in std_ulogic_vector(0 to threads-1); + spr_msr_ucle :in std_ulogic_vector(0 to threads-1); + spr_msrp_uclep :in std_ulogic_vector(0 to threads-1); + spr_ccr2_ucode_dis :in std_ulogic; + spr_ccr2_ap :in std_ulogic_vector(0 to threads-1); + spr_dbcr0_idm :in std_ulogic_vector(0 to threads-1); + cpl_spr_dbcr0_edm :out std_ulogic_vector(0 to threads-1); + spr_dbcr0_icmp :in std_ulogic_vector(0 to threads-1); + spr_dbcr0_brt :in std_ulogic_vector(0 to threads-1); + spr_dbcr0_trap :in std_ulogic_vector(0 to threads-1); + spr_dbcr0_ret :in std_ulogic_vector(0 to threads-1); + spr_dbcr0_irpt :in std_ulogic_vector(0 to threads-1); + spr_epcr_dsigs :in std_ulogic_vector(0 to threads-1); + spr_epcr_isigs :in std_ulogic_vector(0 to threads-1); + spr_epcr_extgs :in std_ulogic_vector(0 to threads-1); + spr_epcr_dtlbgs :in std_ulogic_vector(0 to threads-1); + spr_epcr_itlbgs :in std_ulogic_vector(0 to threads-1); + spr_xucr4_div_barr_thres :out std_ulogic_vector(0 to 7); + spr_ccr0_we :in std_ulogic_vector(0 to threads-1); + cpl_msr_gs :out std_ulogic_vector(0 to threads-1); + cpl_msr_pr :out std_ulogic_vector(0 to threads-1); + cpl_msr_fp :out std_ulogic_vector(0 to threads-1); + cpl_msr_spv :out std_ulogic_vector(0 to threads-1); + cpl_ccr2_ap :out std_ulogic_vector(0 to threads-1); + spr_xucr0_clkg_ctl :in std_ulogic_vector(1 to 3); + spr_xucr4_mmu_mchk :out std_ulogic; + + spr_cpl_ex3_sprg_ce :in std_ulogic; + spr_cpl_ex3_sprg_ue :in std_ulogic; + iu_xu_ierat_ex2_flush_req :in std_ulogic_vector(0 to threads-1); + iu_xu_ierat_ex3_par_err :in std_ulogic_vector(0 to threads-1); + iu_xu_ierat_ex4_par_err :in std_ulogic_vector(0 to threads-1); + + fu_xu_ex3_regfile_err_det :in std_ulogic_vector(0 to threads-1); + xu_fu_regfile_seq_beg :out std_ulogic; + fu_xu_regfile_seq_end :in std_ulogic; + gpr_cpl_ex3_regfile_err_det :in std_ulogic; + cpl_gpr_regfile_seq_beg :out std_ulogic; + gpr_cpl_regfile_seq_end :in std_ulogic; + xu_pc_err_mcsr_summary :out std_ulogic_vector(0 to threads-1); + xu_pc_err_ditc_overrun :out std_ulogic; + xu_pc_err_local_snoop_reject :out std_ulogic; + xu_pc_err_tlb_lru_parity :out std_ulogic; + xu_pc_err_ext_mchk :out std_ulogic; + xu_pc_err_ierat_multihit :out std_ulogic; + xu_pc_err_derat_multihit :out std_ulogic; + xu_pc_err_tlb_multihit :out std_ulogic; + xu_pc_err_ierat_parity :out std_ulogic; + xu_pc_err_derat_parity :out std_ulogic; + xu_pc_err_tlb_parity :out std_ulogic; + xu_pc_err_mchk_disabled :out std_ulogic; + xu_pc_err_sprg_ue :out std_ulogic_vector(0 to threads-1); + + xu_iu_rf1_val :out std_ulogic_vector(0 to threads-1); + xu_rf1_val :out std_ulogic_vector(0 to threads-1); + xu_rf1_is_tlbre :out std_ulogic; + xu_rf1_is_tlbwe :out std_ulogic; + xu_rf1_is_tlbsx :out std_ulogic; + xu_rf1_is_tlbsrx :out std_ulogic; + xu_rf1_is_tlbilx :out std_ulogic; + xu_rf1_is_tlbivax :out std_ulogic; + xu_rf1_is_eratre :out std_ulogic; + xu_rf1_is_eratwe :out std_ulogic; + xu_rf1_is_eratsx :out std_ulogic; + xu_rf1_is_eratsrx :out std_ulogic; + xu_rf1_is_eratilx :out std_ulogic; + xu_rf1_is_erativax :out std_ulogic; + xu_ex1_is_isync :out std_ulogic; + xu_ex1_is_csync :out std_ulogic; + xu_rf1_ws :out std_ulogic_vector(0 to 1); + xu_rf1_t :out std_ulogic_vector(0 to 2); + xu_ex1_rs_is :out std_ulogic_vector(0 to 8); + xu_ex1_ra_entry :out std_ulogic_vector(8 to 11); + xu_ex4_rs_data :out std_ulogic_vector(64-(2**regmode) to 63); + + xu_lsu_rf1_data_act :out std_ulogic; + xu_lsu_rf1_axu_ldst_falign :out std_ulogic; + xu_lsu_ex1_store_data :out std_ulogic_vector(64-(2**regmode) to 63); + xu_lsu_ex1_rotsel_ovrd :out std_ulogic_vector(0 to 4); + xu_lsu_ex1_eff_addr :out std_ulogic_vector(64-(dc_size-3) to 63); + + cpl_fxa_ex5_set_barr :out std_ulogic_vector(0 to threads-1); + cpl_iu_set_barr_tid :out std_ulogic_vector(0 to threads-1); + + lsu_xu_ex6_datc_par_err :in std_ulogic; + + lsu_xu_ex2_dvc1_st_cmp :in std_ulogic_vector(8-(2**regmode)/8 to 7); + lsu_xu_ex2_dvc2_st_cmp :in std_ulogic_vector(8-(2**regmode)/8 to 7); + lsu_xu_ex8_dvc1_ld_cmp :in std_ulogic_vector(8-(2**regmode)/8 to 7); + lsu_xu_ex8_dvc2_ld_cmp :in std_ulogic_vector(8-(2**regmode)/8 to 7); + lsu_xu_rel_dvc1_en :in std_ulogic; + lsu_xu_rel_dvc2_en :in std_ulogic; + lsu_xu_rel_dvc_thrd_id :in std_ulogic_vector(0 to 3); + lsu_xu_rel_dvc1_cmp :in std_ulogic_vector(8-(2**regmode)/8 to 7); + lsu_xu_rel_dvc2_cmp :in std_ulogic_vector(8-(2**regmode)/8 to 7); + + lsu_xu_rot_ex6_data_b :in std_ulogic_vector(64-(2**regmode) to 63); + lsu_xu_rot_rel_data :in std_ulogic_vector(64-(2**regmode) to 63); + pc_xu_trace_bus_enable :in std_ulogic; + pc_xu_instr_trace_mode :in std_ulogic; + pc_xu_instr_trace_tid :in std_ulogic_vector(0 to 1); + iu_xu_ex4_tlb_data :in std_ulogic_vector(64-(2**regmode) to 63); + + pc_xu_inj_dcachedir_parity :in std_ulogic; + pc_xu_inj_dcachedir_multihit :in std_ulogic; + + ex4_256st_data :in std_ulogic_vector(0 to 255); + + xu_lsu_mtspr_trace_en :in std_ulogic_vector(0 to 3); + xu_lsu_spr_xucr0_aflsta :in std_ulogic; + xu_lsu_spr_xucr0_flsta :in std_ulogic; + xu_lsu_spr_xucr0_l2siw :in std_ulogic; + xu_lsu_spr_xucr0_dcdis :in std_ulogic; + xu_lsu_spr_xucr0_wlk :in std_ulogic; + xu_lsu_spr_xucr0_clfc :in std_ulogic; + xu_lsu_spr_xucr0_flh2l2 :in std_ulogic; + xu_lsu_spr_xucr0_cred :in std_ulogic; + xu_lsu_spr_xucr0_rel :in std_ulogic; + xu_lsu_spr_xucr0_mbar_ack :in std_ulogic; + xu_lsu_spr_xucr0_tlbsync :in std_ulogic; + xu_lsu_spr_xucr0_cls :in std_ulogic; + xu_lsu_spr_ccr2_dfrat :in std_ulogic; + xu_lsu_spr_ccr2_dfratsc :in std_ulogic_vector(0 to 8); + + an_ac_flh2l2_gate :in std_ulogic; + + xu_lsu_rf0_derat_val :in std_ulogic_vector(0 to 3); + xu_lsu_rf0_derat_is_extload :in std_ulogic; + xu_lsu_rf0_derat_is_extstore :in std_ulogic; + xu_lsu_hid_mmu_mode :in std_ulogic; + ex6_ld_par_err :in std_ulogic; + + xu_mm_derat_req :out std_ulogic; + xu_mm_derat_thdid :out std_ulogic_vector(0 to 3); + xu_mm_derat_state :out std_ulogic_vector(0 to 3); + xu_mm_derat_tid :out std_ulogic_vector(0 to 13); + xu_mm_derat_lpid :out std_ulogic_vector(0 to 7); + xu_mm_derat_ttype :out std_ulogic_vector(0 to 1); + mm_xu_derat_rel_val :in std_ulogic_vector(0 to 4); + mm_xu_derat_rel_data :in std_ulogic_vector(0 to 131); + mm_xu_derat_pid0 :in std_ulogic_vector(0 to 13); + mm_xu_derat_pid1 :in std_ulogic_vector(0 to 13); + mm_xu_derat_pid2 :in std_ulogic_vector(0 to 13); + mm_xu_derat_pid3 :in std_ulogic_vector(0 to 13); + mm_xu_derat_mmucr0_0 :in std_ulogic_vector(0 to 19); + mm_xu_derat_mmucr0_1 :in std_ulogic_vector(0 to 19); + mm_xu_derat_mmucr0_2 :in std_ulogic_vector(0 to 19); + mm_xu_derat_mmucr0_3 :in std_ulogic_vector(0 to 19); + xu_mm_derat_mmucr0 :out std_ulogic_vector(0 to 17); + xu_mm_derat_mmucr0_we :out std_ulogic_vector(0 to 3); + mm_xu_derat_mmucr1 :in std_ulogic_vector(0 to 9); + xu_mm_derat_mmucr1 :out std_ulogic_vector(0 to 4); + xu_mm_derat_mmucr1_we :out std_ulogic; + mm_xu_derat_snoop_coming :in std_ulogic; + mm_xu_derat_snoop_val :in std_ulogic; + mm_xu_derat_snoop_attr :in std_ulogic_vector(0 to 25); + mm_xu_derat_snoop_vpn :in std_ulogic_vector(64-(2**REGMODE) to 51); + xu_mm_derat_snoop_ack :out std_ulogic; + + xu_lsu_slowspr_val :in std_ulogic; + xu_lsu_slowspr_rw :in std_ulogic; + xu_lsu_slowspr_etid :in std_ulogic_vector(0 to 1); + xu_lsu_slowspr_addr :in std_ulogic_vector(0 to 9); + xu_lsu_slowspr_data :in std_ulogic_vector(64-(2**REGMODE) to 63); + xu_lsu_slowspr_done :in std_ulogic; + slowspr_val_out :out std_ulogic; + slowspr_rw_out :out std_ulogic; + slowspr_etid_out :out std_ulogic_vector(0 to 1); + slowspr_addr_out :out std_ulogic_vector(0 to 9); + slowspr_data_out :out std_ulogic_vector(64-(2**REGMODE) to 63); + slowspr_done_out :out std_ulogic; + + ex1_optype1 :out std_ulogic; + ex1_optype2 :out std_ulogic; + ex1_optype4 :out std_ulogic; + ex1_optype8 :out std_ulogic; + ex1_optype16 :out std_ulogic; + ex1_optype32 :out std_ulogic; + ex1_saxu_instr :out std_ulogic; + ex1_sdp_instr :out std_ulogic; + ex1_stgpr_instr :out std_ulogic; + ex1_store_instr :out std_ulogic; + ex1_axu_op_val :out std_ulogic; + ex3_algebraic :out std_ulogic; + ex3_data_swap :out std_ulogic; + ex3_thrd_id :out std_ulogic_vector(0 to 3); + xu_fu_ex3_eff_addr :out std_ulogic_vector(59 to 63); + xu_lsu_ici :out std_ulogic; + + rel_upd_dcarr_val :out std_ulogic; + + xu_fu_ex5_reload_val :out std_ulogic; + xu_fu_ex5_load_val :out std_ulogic_vector(0 to 3); + xu_fu_ex5_load_tag :out std_ulogic_vector(0 to 8); + + dcarr_up_way_addr :out std_ulogic_vector(0 to 2); + + lsu_xu_spr_xucr0_cslc_xuop :out std_ulogic; + lsu_xu_spr_xucr0_cslc_binv :out std_ulogic; + lsu_xu_spr_xucr0_clo :out std_ulogic; + lsu_xu_spr_xucr0_cul :out std_ulogic; + lsu_xu_spr_epsc_epr :out std_ulogic_vector(0 to 3); + lsu_xu_spr_epsc_egs :out std_ulogic_vector(0 to 3); + + ex4_load_op_hit :out std_ulogic; + ex4_store_hit :out std_ulogic; + ex4_axu_op_val :out std_ulogic; + spr_dvc1_act :out std_ulogic; + spr_dvc2_act :out std_ulogic; + spr_dvc1_dbg :out std_ulogic_vector(64-(2**regmode) to 63); + spr_dvc2_dbg :out std_ulogic_vector(64-(2**regmode) to 63); + + an_ac_req_ld_pop :in std_ulogic; + an_ac_req_st_pop :in std_ulogic; + an_ac_req_st_gather :in std_ulogic; + an_ac_req_st_pop_thrd :in std_ulogic_vector(0 to 2); + + an_ac_reld_data_vld :in std_ulogic; + an_ac_reld_core_tag :in std_ulogic_vector(0 to 4); + an_ac_reld_qw :in std_ulogic_vector(57 to 59); + an_ac_reld_data :in std_ulogic_vector(0 to 127); + an_ac_reld_data_coming :in std_ulogic; + an_ac_reld_ditc :in std_ulogic; + an_ac_reld_crit_qw :in std_ulogic; + an_ac_reld_l1_dump :in std_ulogic; + + an_ac_reld_ecc_err :in std_ulogic; + an_ac_reld_ecc_err_ue :in std_ulogic; + + an_ac_back_inv :in std_ulogic; + an_ac_back_inv_addr :in std_ulogic_vector(64-real_data_add to 63); + an_ac_back_inv_target_bit1 :in std_ulogic; + an_ac_back_inv_target_bit3 :in std_ulogic; + an_ac_back_inv_target_bit4 :in std_ulogic; + an_ac_req_spare_ctrl_a1 :in std_ulogic_vector(0 to 3); + + xu_iu_stcx_complete : out std_ulogic_vector(0 to 3); + xu_iu_reld_core_tag_clone :out std_ulogic_vector(1 to 4); + xu_iu_reld_data_coming_clone :out std_ulogic; + xu_iu_reld_data_vld_clone :out std_ulogic; + xu_iu_reld_ditc_clone :out std_ulogic; + + + lsu_reld_data_vld :out std_ulogic; + lsu_reld_core_tag :out std_ulogic_vector(3 to 4); + lsu_reld_qw :out std_ulogic_vector(58 to 59); + lsu_reld_ditc :out std_ulogic; + lsu_reld_ecc_err :out std_ulogic; + lsu_reld_data :out std_ulogic_vector(0 to 127); + + lsu_req_st_pop :out std_ulogic; + lsu_req_st_pop_thrd :out std_ulogic_vector(0 to 2); + + ac_an_reld_ditc_pop_int : in std_ulogic_vector(0 to 3); + ac_an_reld_ditc_pop_q : out std_ulogic_vector(0 to 3); + bx_ib_empty_int : in std_ulogic_vector(0 to 3); + bx_ib_empty_q : out std_ulogic_vector(0 to 3); + + iu_xu_ra :in std_ulogic_vector(64-real_data_add to 59); + iu_xu_request :in std_ulogic; + iu_xu_wimge :in std_ulogic_vector(0 to 4); + iu_xu_thread :in std_ulogic_vector(0 to 3); + iu_xu_userdef :in std_ulogic_vector(0 to 3); + + mm_xu_lsu_req :in std_ulogic_vector(0 to 3); + mm_xu_lsu_ttype :in std_ulogic_vector(0 to 1); + mm_xu_lsu_wimge :in std_ulogic_vector(0 to 4); + mm_xu_lsu_u :in std_ulogic_vector(0 to 3); + mm_xu_lsu_addr :in std_ulogic_vector(64-real_data_add to 63); + mm_xu_lsu_lpid :in std_ulogic_vector(0 to 7); + mm_xu_lsu_lpidr :in std_ulogic_vector(0 to 7); + mm_xu_lsu_gs :in std_ulogic; + mm_xu_lsu_ind :in std_ulogic; + mm_xu_lsu_lbit :in std_ulogic; + xu_mm_lsu_token :out std_ulogic; + + bx_lsu_ob_pwr_tok :in std_ulogic; + bx_lsu_ob_req_val :in std_ulogic; + bx_lsu_ob_ditc_val :in std_ulogic; + bx_lsu_ob_thrd :in std_ulogic_vector(0 to 1); + bx_lsu_ob_qw :in std_ulogic_vector(58 to 59); + bx_lsu_ob_dest :in std_ulogic_vector(0 to 14); + bx_lsu_ob_data :in std_ulogic_vector(0 to 127); + bx_lsu_ob_addr :in std_ulogic_vector(64-real_data_add to 57); + lsu_bx_cmd_avail :out std_ulogic; + lsu_bx_cmd_sent :out std_ulogic; + lsu_bx_cmd_stall :out std_ulogic; + + lsu_xu_ldq_barr_done :out std_ulogic_vector(0 to 3); + lsu_xu_barr_done :out std_ulogic_vector(0 to 3); + + ldq_rel_data_val_early :out std_ulogic; + ldq_rel_op_size :out std_ulogic_vector(0 to 5); + ldq_rel_addr :out std_ulogic_vector(64-(dc_size-3) to 58); + ldq_rel_data_val :out std_ulogic; + ldq_rel_rot_sel :out std_ulogic_vector(0 to 4); + ldq_rel_axu_val :out std_ulogic; + ldq_rel_ci :out std_ulogic; + ldq_rel_thrd_id :out std_ulogic_vector(0 to 3); + ldq_rel_le_mode :out std_ulogic; + ldq_rel_algebraic :out std_ulogic; + ldq_rel_256_data :out std_ulogic_vector(0 to 255); + + ldq_rel_dvc1_en :out std_ulogic; + ldq_rel_dvc2_en :out std_ulogic; + ldq_rel_beat_crit_qw :out std_ulogic; + ldq_rel_beat_crit_qw_block :out std_ulogic; + lsu_xu_rel_wren :out std_ulogic; + lsu_xu_rel_ta_gpr :out std_ulogic_vector(0 to 7); + + xu_iu_ex4_loadmiss_qentry :out std_ulogic_vector(0 to lmq_entries-1); + xu_iu_ex4_loadmiss_target :out std_ulogic_vector(0 to 8); + xu_iu_ex4_loadmiss_target_type :out std_ulogic_vector(0 to 1); + xu_iu_ex4_loadmiss_tid :out std_ulogic_vector(0 to 3); + xu_iu_ex5_loadmiss_qentry :out std_ulogic_vector(0 to lmq_entries-1); + xu_iu_ex5_loadmiss_target :out std_ulogic_vector(0 to 8); + xu_iu_ex5_loadmiss_target_type :out std_ulogic_vector(0 to 1); + xu_iu_ex5_loadmiss_tid :out std_ulogic_vector(0 to 3); + xu_iu_complete_qentry :out std_ulogic_vector(0 to lmq_entries-1); + xu_iu_complete_tid :out std_ulogic_vector(0 to 3); + xu_iu_complete_target_type :out std_ulogic_vector(0 to 1); + + xu_iu_ex6_icbi_val :out std_ulogic_vector(0 to 3); + xu_iu_ex6_icbi_addr :out std_ulogic_vector(64-real_data_add to 57); + + xu_iu_larx_done_tid :out std_ulogic_vector(0 to 3); + xu_mm_lmq_stq_empty :out std_ulogic; + lsu_xu_quiesce :out std_ulogic_vector(0 to 3); + lsu_xu_dbell_val :out std_ulogic; + lsu_xu_dbell_type :out std_ulogic_vector(0 to 4); + lsu_xu_dbell_brdcast :out std_ulogic; + lsu_xu_dbell_lpid_match :out std_ulogic; + lsu_xu_dbell_pirtag :out std_ulogic_vector(50 to 63); + + xu_ex1_rb :out std_ulogic_vector(64-(2**regmode) to 51); + xu_ex2_eff_addr :out std_ulogic_vector(64-(2**regmode) to 63); + + ac_an_req_pwr_token :out std_ulogic; + ac_an_req :out std_ulogic; + ac_an_req_ra :out std_ulogic_vector(64-real_data_add to 63); + ac_an_req_ttype :out std_ulogic_vector(0 to 5); + ac_an_req_thread :out std_ulogic_vector(0 to 2); + ac_an_req_wimg_w :out std_ulogic; + ac_an_req_wimg_i :out std_ulogic; + ac_an_req_wimg_m :out std_ulogic; + ac_an_req_wimg_g :out std_ulogic; + ac_an_req_endian :out std_ulogic; + ac_an_req_user_defined :out std_ulogic_vector(0 to 3); + ac_an_req_spare_ctrl_a0 :out std_ulogic_vector(0 to 3); + ac_an_req_ld_core_tag :out std_ulogic_vector(0 to 4); + ac_an_req_ld_xfr_len :out std_ulogic_vector(0 to 2); + ac_an_st_byte_enbl :out std_ulogic_vector(0 to 15+(st_data_32B_mode*16)); + ac_an_st_data :out std_ulogic_vector(0 to 127+(st_data_32B_mode*128)); + ac_an_st_data_pwr_token :out std_ulogic; + + xu_pc_err_dcachedir_parity :out std_ulogic; + xu_pc_err_dcachedir_multihit :out std_ulogic; + xu_pc_err_l2intrf_ecc :out std_ulogic; + xu_pc_err_l2intrf_ue :out std_ulogic; + xu_pc_err_invld_reld :out std_ulogic; + xu_pc_err_l2credit_overrun :out std_ulogic; + + pc_xu_event_bus_enable :in std_ulogic; + pc_xu_lsu_event_mux_ctrls :in std_ulogic_vector(0 to 47); + pc_xu_cache_par_err_event :in std_ulogic; + xu_pc_lsu_event_data :out std_ulogic_vector(0 to 7); + + lsu_xu_cmd_debug :out std_ulogic_vector(0 to 175); + + an_ac_lbist_ary_wrt_thru_dc :in std_ulogic; + pc_xu_abist_g8t_wenb :in std_ulogic; + pc_xu_abist_g8t1p_renb_0 :in std_ulogic; + pc_xu_abist_g8t_bw_1 :in std_ulogic; + pc_xu_abist_g8t_bw_0 :in std_ulogic; + pc_xu_abist_wl32_comp_ena :in std_ulogic; + pc_xu_abist_g8t_dcomp :in std_ulogic_vector(0 to 3); + + vcs :inout power_logic; + vdd :inout power_logic; + gnd :inout power_logic; + nclk :in clk_logic; + an_ac_coreid :in std_ulogic_vector(6 to 7); + an_ac_atpg_en_dc :in std_ulogic; + + ccfg_scan_in :in std_ulogic; + ccfg_scan_out :out std_ulogic; + regf_scan_in :in std_ulogic_vector(0 to 6); + regf_scan_out :out std_ulogic_vector(0 to 6); + abst_scan_in :in std_ulogic; + abst_scan_out :out std_ulogic; + repr_scan_in :in std_ulogic; + repr_scan_out :out std_ulogic +); + +-- synopsys translate_off + + +-- synopsys translate_on +end xuq_ctrl; +architecture xuq_ctrl of xuq_ctrl is + +signal clkoff_dc_b_b :std_ulogic; +signal d_mode_dc_b :std_ulogic; +signal delay_lclkr_dc_b :std_ulogic_vector(0 to 4); +signal mpw1_dc_b_b :std_ulogic_vector(0 to 4); +signal mpw2_dc_b_b :std_ulogic; +signal sg_2_b :std_ulogic_vector(0 to 3); +signal fce_2_b :std_ulogic_vector(0 to 1); +signal func_sl_thold_2_b :std_ulogic_vector(0 to 3); +signal func_slp_sl_thold_2_b :std_ulogic_vector(0 to 1); +signal func_nsl_thold_2_b :std_ulogic; +signal func_slp_nsl_thold_2_b :std_ulogic; +signal time_sl_thold_2_b :std_ulogic; +signal repr_sl_thold_2_b :std_ulogic; +signal cfg_slp_sl_thold_2_b :std_ulogic; +signal regf_slp_sl_thold_2_b :std_ulogic; +signal bolt_sl_thold_2_b : std_ulogic; +signal bo_enable_2_b : std_ulogic; + +signal cam_clkoff_dc_b :std_ulogic; +signal cam_d_mode_dc :std_ulogic; +signal cam_act_dis_dc :std_ulogic; +signal cam_delay_lclkr_dc :std_ulogic_vector(0 to 4); +signal cam_mpw1_dc_b :std_ulogic_vector(0 to 4); +signal cam_mpw2_dc_b :std_ulogic; +signal xu_lsu_rf0_act :std_ulogic; +signal xu_lsu_rf1_cache_acc :std_ulogic; +signal xu_lsu_rf1_thrd_id :std_ulogic_vector(0 to threads-1); +signal xu_lsu_rf1_optype1 :std_ulogic; +signal xu_lsu_rf1_optype2 :std_ulogic; +signal xu_lsu_rf1_optype4 :std_ulogic; +signal xu_lsu_rf1_optype8 :std_ulogic; +signal xu_lsu_rf1_optype16 :std_ulogic; +signal xu_lsu_rf1_optype32 :std_ulogic; +signal xu_lsu_rf1_target_gpr :std_ulogic_vector(0 to 8); +signal xu_lsu_rf1_load_instr :std_ulogic; +signal xu_lsu_rf1_store_instr :std_ulogic; +signal xu_lsu_rf1_dcbf_instr :std_ulogic; +signal xu_lsu_rf1_sync_instr :std_ulogic; +signal xu_lsu_rf1_mbar_instr :std_ulogic; +signal xu_lsu_rf1_l_fld :std_ulogic_vector(0 to 1); +signal xu_lsu_rf1_dcbi_instr :std_ulogic; +signal xu_lsu_rf1_dcbz_instr :std_ulogic; +signal xu_lsu_rf1_dcbt_instr :std_ulogic; +signal xu_lsu_rf1_dcbtst_instr :std_ulogic; +signal xu_lsu_rf1_th_fld :std_ulogic_vector(0 to 4); +signal xu_lsu_rf1_dcbtls_instr :std_ulogic; +signal xu_lsu_rf1_dcbtstls_instr :std_ulogic; +signal xu_lsu_rf1_dcblc_instr :std_ulogic; +signal xu_lsu_rf1_dcbst_instr :std_ulogic; +signal xu_lsu_rf1_icbi_instr :std_ulogic; +signal xu_lsu_rf1_icblc_instr :std_ulogic; +signal xu_lsu_rf1_icbt_instr :std_ulogic; +signal xu_lsu_rf1_icbtls_instr :std_ulogic; +signal xu_lsu_rf1_tlbsync_instr :std_ulogic; +signal xu_lsu_rf1_lock_instr :std_ulogic; +signal xu_lsu_rf1_mutex_hint :std_ulogic; +signal xu_lsu_rf1_axu_op_val :std_ulogic; +signal xu_lsu_rf1_axu_ldst_falign_int :std_ulogic; +signal xu_lsu_rf1_axu_ldst_fexcpt :std_ulogic; +signal xu_lsu_rf1_algebraic :std_ulogic; +signal xu_lsu_rf1_byte_rev :std_ulogic; +signal xu_lsu_rf1_src_gpr :std_ulogic; +signal xu_lsu_rf1_src_axu :std_ulogic; +signal xu_lsu_rf1_src_dp :std_ulogic; +signal xu_lsu_rf1_targ_gpr :std_ulogic; +signal xu_lsu_rf1_targ_axu :std_ulogic; +signal xu_lsu_rf1_targ_dp :std_ulogic; +signal xu_lsu_ex4_val :std_ulogic_vector(0 to 3); +signal xu_lsu_rf1_derat_act :std_ulogic; +signal xu_lsu_rf1_derat_is_load :std_ulogic; +signal xu_lsu_rf1_derat_is_store :std_ulogic; +signal xu_lsu_rf1_src0_vld :std_ulogic; +signal xu_lsu_rf1_src0_reg :std_ulogic_vector(0 to 7); +signal xu_lsu_rf1_src1_vld :std_ulogic; +signal xu_lsu_rf1_src1_reg :std_ulogic_vector(0 to 7); +signal xu_lsu_rf1_targ_vld :std_ulogic; +signal xu_lsu_rf1_targ_reg :std_ulogic_vector(0 to 7); +signal xu_lsu_rf1_is_touch :std_ulogic; +signal xu_lsu_rf1_is_msgsnd :std_ulogic; +signal xu_lsu_rf1_dci_instr :std_ulogic; +signal xu_lsu_rf1_ici_instr :std_ulogic; +signal xu_lsu_rf1_icswx_instr :std_ulogic; +signal xu_lsu_rf1_icswx_dot_instr :std_ulogic; +signal xu_lsu_rf1_icswx_epid :std_ulogic; +signal xu_lsu_rf1_ldawx_instr :std_ulogic; +signal xu_lsu_rf1_wclr_instr :std_ulogic; +signal xu_lsu_rf1_wchk_instr :std_ulogic; +signal xu_lsu_rf1_derat_ra_eq_ea :std_ulogic; +signal xu_lsu_rf1_cmd_act :std_ulogic; +signal xu_lsu_rf1_mtspr_trace :std_ulogic; +signal lsu_xu_ex5_wren :std_ulogic; +signal lsu_xu_rel_wren_int :std_ulogic; +signal lsu_xu_rel_ta_gpr_int :std_ulogic_vector(0 to 7); +signal xu_lsu_ex4_dvc1_en :std_ulogic; +signal xu_lsu_ex4_dvc2_en :std_ulogic; +signal xu_lsu_ex1_add_src0 :std_ulogic_vector(64-regsize to 63); +signal xu_lsu_ex1_add_src1 :std_ulogic_vector(64-regsize to 63); +signal xu_rf1_is_eratre_int :std_ulogic; +signal xu_rf1_is_eratwe_int :std_ulogic; +signal xu_rf1_is_eratsx_int :std_ulogic; +signal xu_rf1_is_eratsrx_int :std_ulogic; +signal xu_rf1_is_eratilx_int :std_ulogic; +signal xu_rf1_is_erativax_int :std_ulogic; +signal xu_ex1_is_isync_int :std_ulogic; +signal xu_ex1_is_csync_int :std_ulogic; +signal xu_rf1_ws_int :std_ulogic_vector(0 to 1); +signal xu_rf1_t_int :std_ulogic_vector(0 to 2); +signal xu_ex1_rs_is_int :std_ulogic_vector(0 to 8); +signal xu_ex1_ra_entry_int :std_ulogic_vector(7 to 11); +signal lsu_xu_ex4_tlb_data :std_ulogic_vector(64-(2**regmode) to 63); +signal lsu_xu_is2_back_inv :std_ulogic; +signal lsu_xu_is2_back_inv_addr :std_ulogic_vector(64-real_data_add to 63-cl_size); +signal lsu_xu_ex4_cr_upd :std_ulogic; +signal lsu_xu_ex5_cr_rslt :std_ulogic; +signal lsu_xu_ex3_derat_par_err :std_ulogic_vector(0 to threads-1); +signal lsu_xu_ex3_derat_multihit_err :std_ulogic_vector(0 to threads-1); +signal lsu_xu_ex3_l2_uc_ecc_err :std_ulogic_vector(0 to 3); +signal lsu_xu_ex3_ddir_par_err :std_ulogic; +signal lsu_xu_ex4_n_lsu_ddmh_flush :std_ulogic_vector(0 to threads-1); +signal lsu_xu_ex3_dsi :std_ulogic_vector(0 to threads-1); +signal derat_xu_ex3_dsi :std_ulogic_vector(0 to threads-1); +signal lsu_xu_ex3_align :std_ulogic_vector(0 to threads-1); +signal derat_xu_ex3_miss :std_ulogic_vector(0 to threads-1); +signal lsu_xu_l2_ecc_err_flush :std_ulogic_vector(0 to threads-1); +signal lsu_xu_datc_perr_recovery :std_ulogic; +signal lsu_xu_ex3_dep_flush :std_ulogic; +signal lsu_xu_ex3_n_flush_req :std_ulogic; +signal lsu_xu_ex3_ldq_hit_flush :std_ulogic; +signal lsu_xu_ex4_ldq_full_flush :std_ulogic; +signal derat_xu_ex3_n_flush_req :std_ulogic_vector(0 to threads-1); +signal lsu_xu_ex3_inval_align_2ucode :std_ulogic; +signal lsu_xu_ex3_attr :std_ulogic_vector(0 to 8); +signal lsu_xu_ex3_derat_vf :std_ulogic; +signal xu_lsu_ex4_flush_local_int :std_ulogic_vector(0 to 3); +signal xu_lsu_dci :std_ulogic; +signal xu_rf0_flush :std_ulogic_vector(0 to threads-1); +signal xu_rf1_flush :std_ulogic_vector(0 to threads-1); +signal xu_ex1_flush :std_ulogic_vector(0 to threads-1); +signal xu_ex2_flush :std_ulogic_vector(0 to threads-1); +signal xu_ex3_flush :std_ulogic_vector(0 to threads-1); +signal xu_ex4_flush :std_ulogic_vector(0 to threads-1); +signal bcfg_scan_out_int :std_ulogic; +signal ccfg_scan_out_int :std_ulogic; +signal dcfg_scan_out_int :std_ulogic; +signal xu_ex4_rs_data_int :std_ulogic_vector(64-(2**regmode) to 63); +signal xu_lsu_ex5_set_barr :std_ulogic_vector(0 to threads-1); +signal xu_ex1_eff_addr_int :std_ulogic_vector(64-(dc_size-3) to 63); +signal lsu_xu_ex4_derat_par_err :std_ulogic_vector(0 to 3); +signal fxu_trigger_data_in :std_ulogic_vector(0 to 11); +signal fxu_debug_data_in :std_ulogic_vector(0 to 87); +signal fxu_trigger_data_out :std_ulogic_vector(0 to 11); +signal fxu_debug_data_out :std_ulogic_vector(0 to 87); +signal cpl_debug_data_in :std_ulogic_vector(0 to 87); +signal cpl_debug_data_out :std_ulogic_vector(0 to 87); +signal cpl_trigger_data_in :std_ulogic_vector(0 to 11); +signal cpl_trigger_data_out :std_ulogic_vector(0 to 11); +signal lsu_trigger_data_in :std_ulogic_vector(0 to 11); +signal lsu_debug_data_in :std_ulogic_vector(0 to 87); +signal lsu_trigger_data_out :std_ulogic_vector(0 to 11); +signal lsu_debug_data_out :std_ulogic_vector(0 to 87); +signal ary_slp_nsl_thold_2 :std_ulogic; +signal abst_slp_sl_thold_2 :std_ulogic; +signal xu_n_ex5_flush_int :std_ulogic_vector(0 to threads-1); +signal lsu_xu_need_hole :std_ulogic; +signal xu_lsu_ex2_instr_trace_val :std_ulogic; +signal g8t_clkoff_dc_b :std_ulogic; +signal g8t_d_mode_dc :std_ulogic; +signal g8t_delay_lclkr_dc :std_ulogic_vector(0 to 4); +signal g8t_mpw1_dc_b :std_ulogic_vector(0 to 4); +signal g8t_mpw2_dc_b :std_ulogic; +signal spr_xucr4_mmu_mchk_int :std_ulogic; + + +begin + +xu_n_ex5_flush <= xu_n_ex5_flush_int; +spr_xucr4_mmu_mchk <= spr_xucr4_mmu_mchk_int; + +fxu_trigger_data_in <= ctrl_trigger_data_in; +fxu_debug_data_in <= ctrl_debug_data_in; +cpl_debug_data_in <= fxu_debug_data_out; +cpl_trigger_data_in <= fxu_trigger_data_out; +lsu_debug_data_in <= cpl_debug_data_out; +lsu_trigger_data_in <= cpl_trigger_data_out; +ctrl_debug_data_out <= lsu_debug_data_out; +ctrl_trigger_data_out<= lsu_trigger_data_out; + +clkoff_dc_b <= clkoff_dc_b_b; +d_mode_dc <= d_mode_dc_b; +delay_lclkr_dc <= delay_lclkr_dc_b; +mpw1_dc_b <= mpw1_dc_b_b; +mpw2_dc_b <= mpw2_dc_b_b; +sg_2 <= sg_2_b; +fce_2 <= fce_2_b; +func_sl_thold_2 <= func_sl_thold_2_b; +func_slp_sl_thold_2 <= func_slp_sl_thold_2_b; +func_nsl_thold_2 <= func_nsl_thold_2_b; +func_slp_nsl_thold_2 <= func_slp_nsl_thold_2_b; +time_sl_thold_2 <= time_sl_thold_2_b; +repr_sl_thold_2 <= repr_sl_thold_2_b; +cfg_slp_sl_thold_2 <= cfg_slp_sl_thold_2_b; +regf_slp_sl_thold_2 <= regf_slp_sl_thold_2_b; +bolt_sl_thold_2 <= bolt_sl_thold_2_b; +bo_enable_2 <= bo_enable_2_b; + + xuq_cpl_fxub : entity work.xuq_cpl_fxub(xuq_cpl_fxub) + generic map( + expand_type => expand_type, + threads => threads, + eff_ifar => eff_ifar, + regmode => regmode, + regsize => regsize, + hvmode => hvmode, + dc_size => dc_size, + cl_size => cl_size, + real_data_add => real_data_add, + uc_ifar => uc_ifar, + fxu_synth => fxu_synth, + a2mode => a2mode) + port map( + nclk => nclk, + vdd => vdd, + gnd => gnd, + vcs => vcs, + + func_scan_in => func_scan_in(50 to 58), + func_scan_out => func_scan_out(50 to 58), + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b, + pc_xu_ccflush_dc => pc_xu_ccflush_dc, + clkoff_dc_b => clkoff_dc_b_b, + d_mode_dc => d_mode_dc_b, + delay_lclkr_dc => delay_lclkr_dc_b, + mpw1_dc_b => mpw1_dc_b_b, + mpw2_dc_b => mpw2_dc_b_b, + g6t_clkoff_dc_b => g6t_clkoff_dc_b, + g6t_d_mode_dc => g6t_d_mode_dc, + g6t_delay_lclkr_dc => g6t_delay_lclkr_dc, + g6t_mpw1_dc_b => g6t_mpw1_dc_b, + g6t_mpw2_dc_b => g6t_mpw2_dc_b, + g8t_clkoff_dc_b => g8t_clkoff_dc_b, + g8t_d_mode_dc => g8t_d_mode_dc, + g8t_delay_lclkr_dc => g8t_delay_lclkr_dc, + g8t_mpw1_dc_b => g8t_mpw1_dc_b, + g8t_mpw2_dc_b => g8t_mpw2_dc_b, + cam_clkoff_dc_b => cam_clkoff_dc_b, + cam_d_mode_dc => cam_d_mode_dc, + cam_delay_lclkr_dc => cam_delay_lclkr_dc, + cam_act_dis_dc => cam_act_dis_dc, + cam_mpw1_dc_b => cam_mpw1_dc_b, + cam_mpw2_dc_b => cam_mpw2_dc_b, + pc_xu_sg_3 => pc_xu_sg_3, + pc_xu_func_sl_thold_3 => pc_xu_func_sl_thold_3, + pc_xu_func_slp_sl_thold_3 => pc_xu_func_slp_sl_thold_3, + pc_xu_func_nsl_thold_3 => pc_xu_func_nsl_thold_3, + pc_xu_func_slp_nsl_thold_3 => pc_xu_func_slp_nsl_thold_3, + pc_xu_gptr_sl_thold_3 => pc_xu_gptr_sl_thold_3, + pc_xu_abst_sl_thold_3 => pc_xu_abst_sl_thold_3, + pc_xu_abst_slp_sl_thold_3 => pc_xu_abst_slp_sl_thold_3, + pc_xu_regf_sl_thold_3 => pc_xu_regf_sl_thold_3, + pc_xu_regf_slp_sl_thold_3 => pc_xu_regf_slp_sl_thold_3, + pc_xu_time_sl_thold_3 => pc_xu_time_sl_thold_3, + pc_xu_cfg_sl_thold_3 => pc_xu_cfg_sl_thold_3, + pc_xu_cfg_slp_sl_thold_3 => pc_xu_cfg_slp_sl_thold_3, + pc_xu_ary_nsl_thold_3 => pc_xu_ary_nsl_thold_3, + pc_xu_ary_slp_nsl_thold_3 => pc_xu_ary_slp_nsl_thold_3, + pc_xu_repr_sl_thold_3 => pc_xu_repr_sl_thold_3, + pc_xu_fce_3 => pc_xu_fce_3, + pc_xu_bolt_sl_thold_3 => pc_xu_bolt_sl_thold_3, + pc_xu_bo_enable_3 => pc_xu_bo_enable_3, + bolt_sl_thold_2 => bolt_sl_thold_2_b, + bo_enable_2 => bo_enable_2_b, + an_ac_scan_diag_dc => an_ac_scan_diag_dc, + sg_2 => sg_2_b, + fce_2 => fce_2_b, + func_sl_thold_2 => func_sl_thold_2_b, + func_slp_sl_thold_2 => func_slp_sl_thold_2_b, + func_nsl_thold_2 => func_nsl_thold_2_b, + func_slp_nsl_thold_2 => func_slp_nsl_thold_2_b, + abst_sl_thold_2 => abst_sl_thold_2, + abst_slp_sl_thold_2 => abst_slp_sl_thold_2, + time_sl_thold_2 => time_sl_thold_2_b, + gptr_sl_thold_2 => gptr_sl_thold_2, + ary_nsl_thold_2 => ary_nsl_thold_2, + ary_slp_nsl_thold_2 => ary_slp_nsl_thold_2, + repr_sl_thold_2 => repr_sl_thold_2_b, + cfg_sl_thold_2 => cfg_sl_thold_2, + cfg_slp_sl_thold_2 => cfg_slp_sl_thold_2_b, + regf_slp_sl_thold_2 => regf_slp_sl_thold_2_b, + gptr_scan_in => gptr_scan_in, + gptr_scan_out => gptr_scan_out, + fxa_fxb_rf0_val => fxa_fxb_rf0_val, + fxa_fxb_rf0_issued => fxa_fxb_rf0_issued, + fxa_fxb_rf0_ucode_val => fxa_fxb_rf0_ucode_val, + fxa_fxb_rf0_act => fxa_fxb_rf0_act, + fxa_fxb_ex1_hold_ctr_flush => fxa_fxb_ex1_hold_ctr_flush, + fxa_fxb_rf0_instr => fxa_fxb_rf0_instr, + fxa_fxb_rf0_tid => fxa_fxb_rf0_tid, + fxa_fxb_rf0_ta_vld => fxa_fxb_rf0_ta_vld, + fxa_fxb_rf0_ta => fxa_fxb_rf0_ta, + fxa_fxb_rf0_error => fxa_fxb_rf0_error, + fxa_fxb_rf0_match => fxa_fxb_rf0_match, + fxa_fxb_rf0_is_ucode => fxa_fxb_rf0_is_ucode, + fxa_fxb_rf0_gshare => fxa_fxb_rf0_gshare, + fxa_fxb_rf0_ifar => fxa_fxb_rf0_ifar, + fxa_fxb_rf0_s1_vld => fxa_fxb_rf0_s1_vld, + fxa_fxb_rf0_s1 => fxa_fxb_rf0_s1, + fxa_fxb_rf0_s2_vld => fxa_fxb_rf0_s2_vld, + fxa_fxb_rf0_s2 => fxa_fxb_rf0_s2, + fxa_fxb_rf0_s3_vld => fxa_fxb_rf0_s3_vld, + fxa_fxb_rf0_s3 => fxa_fxb_rf0_s3, + fxa_fxb_rf0_axu_instr_type => fxa_fxb_rf0_axu_instr_type, + fxa_fxb_rf0_axu_ld_or_st => fxa_fxb_rf0_axu_ld_or_st, + fxa_fxb_rf0_axu_store => fxa_fxb_rf0_axu_store, + fxa_fxb_rf0_axu_ldst_forcealign => fxa_fxb_rf0_axu_ldst_forcealign, + fxa_fxb_rf0_axu_ldst_forceexcept => fxa_fxb_rf0_axu_ldst_forceexcept, + fxa_fxb_rf0_axu_ldst_indexed => fxa_fxb_rf0_axu_ldst_indexed, + fxa_fxb_rf0_axu_ldst_tag => fxa_fxb_rf0_axu_ldst_tag, + fxa_fxb_rf0_axu_mftgpr => fxa_fxb_rf0_axu_mftgpr, + fxa_fxb_rf0_axu_mffgpr => fxa_fxb_rf0_axu_mffgpr, + fxa_fxb_rf0_axu_movedp => fxa_fxb_rf0_axu_movedp, + fxa_fxb_rf0_axu_ldst_size => fxa_fxb_rf0_axu_ldst_size, + fxa_fxb_rf0_axu_ldst_update => fxa_fxb_rf0_axu_ldst_update, + fxa_fxb_rf0_pred_update => fxa_fxb_rf0_pred_update, + fxa_fxb_rf0_pred_taken_cnt => fxa_fxb_rf0_pred_taken_cnt, + fxa_fxb_rf0_mc_dep_chk_val => fxa_fxb_rf0_mc_dep_chk_val, + fxa_fxb_rf1_mul_val => fxa_fxb_rf1_mul_val, + fxa_fxb_rf1_div_val => fxa_fxb_rf1_div_val, + fxa_fxb_rf1_div_ctr => fxa_fxb_rf1_div_ctr, + fxa_fxb_rf0_xu_epid_instr => fxa_fxb_rf0_xu_epid_instr, + fxa_fxb_rf0_axu_is_extload => fxa_fxb_rf0_axu_is_extload, + fxa_fxb_rf0_axu_is_extstore => fxa_fxb_rf0_axu_is_extstore, + fxa_fxb_rf0_is_mfocrf => fxa_fxb_rf0_is_mfocrf, + fxa_fxb_rf0_3src_instr => fxa_fxb_rf0_3src_instr, + fxa_fxb_rf0_gpr0_zero => fxa_fxb_rf0_gpr0_zero, + fxa_fxb_rf0_use_imm => fxa_fxb_rf0_use_imm, + fxa_fxb_rf1_muldiv_coll => fxa_fxb_rf1_muldiv_coll, + fxa_cpl_ex2_div_coll => fxa_cpl_ex2_div_coll, + fxb_fxa_ex7_we0 => fxb_fxa_ex7_we0, + fxb_fxa_ex7_wa0 => fxb_fxa_ex7_wa0, + fxb_fxa_ex7_wd0 => fxb_fxa_ex7_wd0, + fxa_fxb_rf1_do0 => fxa_fxb_rf1_do0, + fxa_fxb_rf1_do1 => fxa_fxb_rf1_do1, + fxa_fxb_rf1_do2 => fxa_fxb_rf1_do2, + xu_lsu_rf0_act => xu_lsu_rf0_act, + xu_lsu_rf1_cache_acc => xu_lsu_rf1_cache_acc, + xu_lsu_rf1_thrd_id => xu_lsu_rf1_thrd_id, + xu_lsu_rf1_optype1 => xu_lsu_rf1_optype1, + xu_lsu_rf1_optype2 => xu_lsu_rf1_optype2, + xu_lsu_rf1_optype4 => xu_lsu_rf1_optype4, + xu_lsu_rf1_optype8 => xu_lsu_rf1_optype8, + xu_lsu_rf1_optype16 => xu_lsu_rf1_optype16, + xu_lsu_rf1_optype32 => xu_lsu_rf1_optype32, + xu_lsu_rf1_target_gpr => xu_lsu_rf1_target_gpr, + xu_lsu_rf1_load_instr => xu_lsu_rf1_load_instr, + xu_lsu_rf1_store_instr => xu_lsu_rf1_store_instr, + xu_lsu_rf1_dcbf_instr => xu_lsu_rf1_dcbf_instr, + xu_lsu_rf1_sync_instr => xu_lsu_rf1_sync_instr, + xu_lsu_rf1_mbar_instr => xu_lsu_rf1_mbar_instr, + xu_lsu_rf1_l_fld => xu_lsu_rf1_l_fld, + xu_lsu_rf1_dcbi_instr => xu_lsu_rf1_dcbi_instr, + xu_lsu_rf1_dcbz_instr => xu_lsu_rf1_dcbz_instr, + xu_lsu_rf1_dcbt_instr => xu_lsu_rf1_dcbt_instr, + xu_lsu_rf1_dcbtst_instr => xu_lsu_rf1_dcbtst_instr, + xu_lsu_rf1_th_fld => xu_lsu_rf1_th_fld, + xu_lsu_rf1_dcbtls_instr => xu_lsu_rf1_dcbtls_instr, + xu_lsu_rf1_dcbtstls_instr => xu_lsu_rf1_dcbtstls_instr, + xu_lsu_rf1_dcblc_instr => xu_lsu_rf1_dcblc_instr, + xu_lsu_rf1_dcbst_instr => xu_lsu_rf1_dcbst_instr, + xu_lsu_rf1_icbi_instr => xu_lsu_rf1_icbi_instr, + xu_lsu_rf1_icblc_instr => xu_lsu_rf1_icblc_instr, + xu_lsu_rf1_icbt_instr => xu_lsu_rf1_icbt_instr, + xu_lsu_rf1_icbtls_instr => xu_lsu_rf1_icbtls_instr, + xu_lsu_rf1_tlbsync_instr => xu_lsu_rf1_tlbsync_instr, + xu_lsu_rf1_lock_instr => xu_lsu_rf1_lock_instr, + xu_lsu_rf1_mutex_hint => xu_lsu_rf1_mutex_hint, + xu_lsu_rf1_axu_op_val => xu_lsu_rf1_axu_op_val, + xu_lsu_rf1_axu_ldst_falign => xu_lsu_rf1_axu_ldst_falign_int, + xu_lsu_rf1_axu_ldst_fexcpt => xu_lsu_rf1_axu_ldst_fexcpt, + xu_lsu_ex1_store_data => xu_lsu_ex1_store_data, + xu_lsu_rf1_algebraic => xu_lsu_rf1_algebraic, + xu_lsu_rf1_byte_rev => xu_lsu_rf1_byte_rev, + xu_lsu_rf1_src_gpr => xu_lsu_rf1_src_gpr, + xu_lsu_rf1_src_axu => xu_lsu_rf1_src_axu, + xu_lsu_rf1_src_dp => xu_lsu_rf1_src_dp, + xu_lsu_rf1_targ_gpr => xu_lsu_rf1_targ_gpr, + xu_lsu_rf1_targ_axu => xu_lsu_rf1_targ_axu, + xu_lsu_rf1_targ_dp => xu_lsu_rf1_targ_dp, + xu_lsu_ex4_val => xu_lsu_ex4_val, + xu_lsu_ex1_rotsel_ovrd => xu_lsu_ex1_rotsel_ovrd, + xu_lsu_rf1_derat_act => xu_lsu_rf1_derat_act, + xu_lsu_rf1_derat_is_load => xu_lsu_rf1_derat_is_load, + xu_lsu_rf1_derat_is_store => xu_lsu_rf1_derat_is_store, + xu_lsu_rf1_src0_vld => xu_lsu_rf1_src0_vld, + xu_lsu_rf1_src0_reg => xu_lsu_rf1_src0_reg, + xu_lsu_rf1_src1_vld => xu_lsu_rf1_src1_vld, + xu_lsu_rf1_src1_reg => xu_lsu_rf1_src1_reg, + xu_lsu_rf1_targ_vld => xu_lsu_rf1_targ_vld, + xu_lsu_rf1_targ_reg => xu_lsu_rf1_targ_reg, + xu_bx_ex1_mtdp_val => xu_bx_ex1_mtdp_val, + xu_bx_ex1_mfdp_val => xu_bx_ex1_mfdp_val, + xu_bx_ex1_ipc_thrd => xu_bx_ex1_ipc_thrd, + xu_bx_ex2_ipc_ba => xu_bx_ex2_ipc_ba, + xu_bx_ex2_ipc_sz => xu_bx_ex2_ipc_sz, + xu_lsu_rf1_is_touch => xu_lsu_rf1_is_touch, + xu_lsu_rf1_is_msgsnd => xu_lsu_rf1_is_msgsnd, + xu_lsu_rf1_dci_instr => xu_lsu_rf1_dci_instr, + xu_lsu_rf1_ici_instr => xu_lsu_rf1_ici_instr, + xu_lsu_rf1_icswx_instr => xu_lsu_rf1_icswx_instr, + xu_lsu_rf1_icswx_dot_instr => xu_lsu_rf1_icswx_dot_instr, + xu_lsu_rf1_icswx_epid => xu_lsu_rf1_icswx_epid, + xu_lsu_rf1_ldawx_instr => xu_lsu_rf1_ldawx_instr, + xu_lsu_rf1_wclr_instr => xu_lsu_rf1_wclr_instr, + xu_lsu_rf1_wchk_instr => xu_lsu_rf1_wchk_instr, + xu_lsu_rf1_derat_ra_eq_ea => xu_lsu_rf1_derat_ra_eq_ea, + xu_lsu_rf1_cmd_act => xu_lsu_rf1_cmd_act, + xu_lsu_rf1_data_act => xu_lsu_rf1_data_act, + xu_lsu_rf1_mtspr_trace => xu_lsu_rf1_mtspr_trace, + lsu_xu_ex5_wren => lsu_xu_ex5_wren, + lsu_xu_rel_wren => lsu_xu_rel_wren_int, + lsu_xu_rel_ta_gpr => lsu_xu_rel_ta_gpr_int, + lsu_xu_need_hole => lsu_xu_need_hole, + lsu_xu_rot_ex6_data_b => lsu_xu_rot_ex6_data_b, + lsu_xu_rot_rel_data => lsu_xu_rot_rel_data, + xu_lsu_ex4_dvc1_en => xu_lsu_ex4_dvc1_en, + xu_lsu_ex4_dvc2_en => xu_lsu_ex4_dvc2_en, + lsu_xu_ex2_dvc1_st_cmp => lsu_xu_ex2_dvc1_st_cmp, + lsu_xu_ex2_dvc2_st_cmp => lsu_xu_ex2_dvc2_st_cmp, + lsu_xu_ex8_dvc1_ld_cmp => lsu_xu_ex8_dvc1_ld_cmp, + lsu_xu_ex8_dvc2_ld_cmp => lsu_xu_ex8_dvc2_ld_cmp, + lsu_xu_rel_dvc1_en => lsu_xu_rel_dvc1_en, + lsu_xu_rel_dvc2_en => lsu_xu_rel_dvc2_en, + lsu_xu_rel_dvc_thrd_id => lsu_xu_rel_dvc_thrd_id, + lsu_xu_rel_dvc1_cmp => lsu_xu_rel_dvc1_cmp, + lsu_xu_rel_dvc2_cmp => lsu_xu_rel_dvc2_cmp, + xu_lsu_ex1_add_src0 => xu_lsu_ex1_add_src0, + xu_lsu_ex1_add_src1 => xu_lsu_ex1_add_src1, + xu_ex1_eff_addr_int => xu_ex1_eff_addr_int, + xu_lsu_ex5_set_barr => xu_lsu_ex5_set_barr, + cpl_fxa_ex5_set_barr => cpl_fxa_ex5_set_barr, + cpl_iu_set_barr_tid => cpl_iu_set_barr_tid, + xu_iu_rf1_val => xu_iu_rf1_val, + xu_rf1_val => xu_rf1_val, + xu_rf1_is_tlbre => xu_rf1_is_tlbre, + xu_rf1_is_tlbwe => xu_rf1_is_tlbwe, + xu_rf1_is_tlbsx => xu_rf1_is_tlbsx, + xu_rf1_is_tlbsrx => xu_rf1_is_tlbsrx, + xu_rf1_is_tlbilx => xu_rf1_is_tlbilx, + xu_rf1_is_tlbivax => xu_rf1_is_tlbivax, + xu_rf1_is_eratre => xu_rf1_is_eratre_int, + xu_rf1_is_eratwe => xu_rf1_is_eratwe_int, + xu_rf1_is_eratsx => xu_rf1_is_eratsx_int, + xu_rf1_is_eratsrx => xu_rf1_is_eratsrx_int, + xu_rf1_is_eratilx => xu_rf1_is_eratilx_int, + xu_rf1_is_erativax => xu_rf1_is_erativax_int, + xu_ex1_is_isync => xu_ex1_is_isync_int, + xu_ex1_is_csync => xu_ex1_is_csync_int, + xu_rf1_ws => xu_rf1_ws_int, + xu_rf1_t => xu_rf1_t_int, + xu_ex1_rs_is => xu_ex1_rs_is_int, + xu_ex1_ra_entry => xu_ex1_ra_entry_int, + xu_ex1_rb => xu_ex1_rb, + xu_ex2_eff_addr => xu_ex2_eff_addr, + xu_ex4_rs_data => xu_ex4_rs_data_int, + lsu_xu_ex4_tlb_data => lsu_xu_ex4_tlb_data, + iu_xu_ex4_tlb_data => iu_xu_ex4_tlb_data, + xu_mm_derat_epn => xu_mm_derat_epn, + lsu_xu_is2_back_inv => lsu_xu_is2_back_inv, + lsu_xu_is2_back_inv_addr => lsu_xu_is2_back_inv_addr, + mm_xu_mmucr0_0_tlbsel => mm_xu_derat_mmucr0_0(4 to 5), + mm_xu_mmucr0_1_tlbsel => mm_xu_derat_mmucr0_1(4 to 5), + mm_xu_mmucr0_2_tlbsel => mm_xu_derat_mmucr0_2(4 to 5), + mm_xu_mmucr0_3_tlbsel => mm_xu_derat_mmucr0_3(4 to 5), + xu_mm_rf1_is_tlbsxr => xu_mm_rf1_is_tlbsxr, + mm_xu_cr0_eq_valid => mm_xu_cr0_eq_valid, + mm_xu_cr0_eq => mm_xu_cr0_eq, + fu_xu_ex4_cr_val => fu_xu_ex4_cr_val, + fu_xu_ex4_cr_noflush => fu_xu_ex4_cr_noflush, + fu_xu_ex4_cr0 => fu_xu_ex4_cr0, + fu_xu_ex4_cr0_bf => fu_xu_ex4_cr0_bf, + fu_xu_ex4_cr1 => fu_xu_ex4_cr1, + fu_xu_ex4_cr1_bf => fu_xu_ex4_cr1_bf, + fu_xu_ex4_cr2 => fu_xu_ex4_cr2, + fu_xu_ex4_cr2_bf => fu_xu_ex4_cr2_bf, + fu_xu_ex4_cr3 => fu_xu_ex4_cr3, + fu_xu_ex4_cr3_bf => fu_xu_ex4_cr3_bf, + xu_pc_ram_data => xu_pc_ram_data, + xu_iu_ex5_val => xu_iu_ex5_val, + xu_iu_ex5_tid => xu_iu_ex5_tid, + xu_iu_ex5_br_update => xu_iu_ex5_br_update, + xu_iu_ex5_br_hist => xu_iu_ex5_br_hist, + xu_iu_ex5_bclr => xu_iu_ex5_bclr, + xu_iu_ex5_lk => xu_iu_ex5_lk, + xu_iu_ex5_bh => xu_iu_ex5_bh, + xu_iu_ex6_pri => xu_iu_ex6_pri, + xu_iu_ex6_pri_val => xu_iu_ex6_pri_val, + xu_iu_spr_xer => xu_iu_spr_xer, + xu_iu_slowspr_done => xu_iu_slowspr_done, + xu_iu_need_hole => xu_iu_need_hole, + fxb_fxa_ex6_clear_barrier => fxb_fxa_ex6_clear_barrier, + xu_iu_ex5_gshare => xu_iu_ex5_gshare, + xu_iu_ex5_getNIA => xu_iu_ex5_getNIA, + an_ac_stcx_complete => an_ac_stcx_complete, + an_ac_stcx_pass => an_ac_stcx_pass, + + an_ac_back_inv => an_ac_back_inv, + an_ac_back_inv_addr => an_ac_back_inv_addr(58 to 63), + an_ac_back_inv_target_bit3 => an_ac_back_inv_target_bit3, + slowspr_val_in => slowspr_val_in, + slowspr_rw_in => slowspr_rw_in, + slowspr_etid_in => slowspr_etid_in, + slowspr_addr_in => slowspr_addr_in, + slowspr_data_in => slowspr_data_in, + slowspr_done_in => slowspr_done_in, + an_ac_dcr_act => an_ac_dcr_act, + an_ac_dcr_val => an_ac_dcr_val, + an_ac_dcr_read => an_ac_dcr_read, + an_ac_dcr_etid => an_ac_dcr_etid, + an_ac_dcr_data => an_ac_dcr_data, + an_ac_dcr_done => an_ac_dcr_done, + lsu_xu_ex4_mtdp_cr_status => lsu_xu_ex4_mtdp_cr_status, + lsu_xu_ex4_mfdp_cr_status => lsu_xu_ex4_mfdp_cr_status, + dec_cpl_ex3_mc_dep_chk_val => dec_cpl_ex3_mc_dep_chk_val, + lsu_xu_ex4_cr_upd => lsu_xu_ex4_cr_upd, + lsu_xu_ex5_cr_rslt => lsu_xu_ex5_cr_rslt, + dec_spr_ex4_val => dec_spr_ex4_val, + dec_spr_ex1_epid_instr => dec_spr_ex1_epid_instr, + mux_spr_ex2_rt => mux_spr_ex2_rt, + fxu_spr_ex1_rs0 => fxu_spr_ex1_rs0, + fxu_spr_ex1_rs1 => fxu_spr_ex1_rs1, + spr_msr_cm => spr_msr_cm, + spr_dec_spr_xucr0_ssdly => spr_dec_spr_xucr0_ssdly, + spr_ccr2_en_attn => spr_ccr2_en_attn, + spr_ccr2_en_ditc => spr_ccr2_en_ditc, + spr_ccr2_en_pc => spr_ccr2_en_pc, + spr_ccr2_en_icswx => spr_ccr2_en_icswx, + spr_ccr2_en_dcr => spr_ccr2_en_dcr, + spr_dec_rf1_epcr_dgtmi => spr_dec_rf1_epcr_dgtmi, + spr_dec_rf1_msr_ucle => spr_msr_ucle, + spr_dec_rf1_msrp_uclep => spr_msrp_uclep, + spr_byp_ex4_is_mfxer => spr_byp_ex4_is_mfxer, + spr_byp_ex3_spr_rt => spr_byp_ex3_spr_rt, + spr_byp_ex4_is_mtxer => spr_byp_ex4_is_mtxer, + spr_ccr2_notlb => spr_ccr2_notlb, + dec_spr_rf1_val => dec_spr_rf1_val, + fxu_spr_ex1_rs2 => fxu_spr_ex1_rs2, + fxa_perf_muldiv_in_use => fxa_perf_muldiv_in_use, + spr_perf_tx_events => spr_perf_tx_events, + xu_pc_event_data => xu_pc_event_data, + pc_xu_event_bus_enable => pc_xu_event_bus_enable, + pc_xu_event_count_mode => pc_xu_event_count_mode, + pc_xu_event_mux_ctrls => pc_xu_event_mux_ctrls, + pc_xu_trace_bus_enable => pc_xu_trace_bus_enable, + pc_xu_instr_trace_mode => pc_xu_instr_trace_mode, + pc_xu_instr_trace_tid => pc_xu_instr_trace_tid, + xu_lsu_ex2_instr_trace_val => xu_lsu_ex2_instr_trace_val, + fxu_debug_mux_ctrls => fxu_debug_mux_ctrls, + fxu_trigger_data_in => fxu_trigger_data_in, + fxu_debug_data_in => fxu_debug_data_in, + fxu_trigger_data_out => fxu_trigger_data_out, + fxu_debug_data_out => fxu_debug_data_out, + lsu_xu_data_debug0 => lsu_xu_data_debug0, + lsu_xu_data_debug1 => lsu_xu_data_debug1, + lsu_xu_data_debug2 => lsu_xu_data_debug2, + spr_msr_gs => spr_msr_gs, + spr_msr_ds => spr_msr_ds, + spr_msr_pr => spr_msr_pr, + spr_dbcr0_dac1 => spr_dbcr0_dac1, + spr_dbcr0_dac2 => spr_dbcr0_dac2, + spr_dbcr0_dac3 => spr_dbcr0_dac3, + spr_dbcr0_dac4 => spr_dbcr0_dac4, + spr_xucr4_mmu_mchk => spr_xucr4_mmu_mchk_int, + ac_tc_debug_trigger => ac_tc_debug_trigger, + bcfg_scan_in => bcfg_scan_in, + bcfg_scan_out => bcfg_scan_out_int, + ccfg_scan_in => ccfg_scan_in, + ccfg_scan_out => ccfg_scan_out_int, + dcfg_scan_in => dcfg_scan_in, + dcfg_scan_out => dcfg_scan_out_int, + dec_cpl_rf0_act => dec_cpl_rf0_act, + dec_cpl_rf0_tid => dec_cpl_rf0_tid, + fu_xu_rf1_act => fu_xu_rf1_act, + fu_xu_ex1_ifar => fu_xu_ex1_ifar, + fu_xu_ex2_ifar_val => fu_xu_ex2_ifar_val, + fu_xu_ex2_ifar_issued => fu_xu_ex2_ifar_issued, + fu_xu_ex2_instr_type => fu_xu_ex2_instr_type, + fu_xu_ex2_instr_match => fu_xu_ex2_instr_match, + fu_xu_ex2_is_ucode => fu_xu_ex2_is_ucode, + pc_xu_step => pc_xu_step, + pc_xu_stop => pc_xu_stop, + pc_xu_dbg_action => pc_xu_dbg_action, + pc_xu_force_ude => pc_xu_force_ude, + xu_pc_step_done => xu_pc_step_done, + pc_xu_init_reset => pc_xu_init_reset, + spr_cpl_ext_interrupt => spr_cpl_ext_interrupt, + spr_cpl_udec_interrupt => spr_cpl_udec_interrupt, + spr_cpl_perf_interrupt => spr_cpl_perf_interrupt, + spr_cpl_dec_interrupt => spr_cpl_dec_interrupt, + spr_cpl_fit_interrupt => spr_cpl_fit_interrupt, + spr_cpl_crit_interrupt => spr_cpl_crit_interrupt, + spr_cpl_wdog_interrupt => spr_cpl_wdog_interrupt, + spr_cpl_dbell_interrupt => spr_cpl_dbell_interrupt, + spr_cpl_cdbell_interrupt => spr_cpl_cdbell_interrupt, + spr_cpl_gdbell_interrupt => spr_cpl_gdbell_interrupt, + spr_cpl_gcdbell_interrupt => spr_cpl_gcdbell_interrupt, + spr_cpl_gmcdbell_interrupt => spr_cpl_gmcdbell_interrupt, + cpl_spr_ex5_dbell_taken => cpl_spr_ex5_dbell_taken, + cpl_spr_ex5_cdbell_taken => cpl_spr_ex5_cdbell_taken, + cpl_spr_ex5_gdbell_taken => cpl_spr_ex5_gdbell_taken, + cpl_spr_ex5_gcdbell_taken => cpl_spr_ex5_gcdbell_taken, + cpl_spr_ex5_gmcdbell_taken => cpl_spr_ex5_gmcdbell_taken, + cpl_spr_ex5_act => cpl_spr_ex5_act, + cpl_spr_ex5_int => cpl_spr_ex5_int, + cpl_spr_ex5_gint => cpl_spr_ex5_gint, + cpl_spr_ex5_cint => cpl_spr_ex5_cint, + cpl_spr_ex5_mcint => cpl_spr_ex5_mcint, + cpl_spr_ex5_nia => cpl_spr_ex5_nia, + cpl_spr_ex5_esr => cpl_spr_ex5_esr, + cpl_spr_ex5_mcsr => cpl_spr_ex5_mcsr, + cpl_spr_ex5_dbsr => cpl_spr_ex5_dbsr, + cpl_spr_ex5_dear_save => cpl_spr_ex5_dear_save, + cpl_spr_ex5_dear_update_saved => cpl_spr_ex5_dear_update_saved, + cpl_spr_ex5_dear_update => cpl_spr_ex5_dear_update, + cpl_spr_ex5_dbsr_update => cpl_spr_ex5_dbsr_update, + cpl_spr_ex5_esr_update => cpl_spr_ex5_esr_update, + cpl_spr_ex5_srr0_dec => cpl_spr_ex5_srr0_dec, + cpl_spr_ex5_force_gsrr => cpl_spr_ex5_force_gsrr, + cpl_spr_ex5_dbsr_ide => cpl_spr_ex5_dbsr_ide, + spr_cpl_dbsr_ide => spr_cpl_dbsr_ide, + mm_xu_local_snoop_reject => mm_xu_local_snoop_reject, + mm_xu_lru_par_err => mm_xu_lru_par_err, + mm_xu_tlb_par_err => mm_xu_tlb_par_err, + mm_xu_tlb_multihit_err => mm_xu_tlb_multihit_err, + lsu_xu_ex3_derat_par_err => lsu_xu_ex3_derat_par_err, + lsu_xu_ex4_derat_par_err => lsu_xu_ex4_derat_par_err, + lsu_xu_ex3_derat_multihit_err => lsu_xu_ex3_derat_multihit_err, + lsu_xu_ex3_l2_uc_ecc_err => lsu_xu_ex3_l2_uc_ecc_err, + lsu_xu_ex3_ddir_par_err => lsu_xu_ex3_ddir_par_err, + lsu_xu_ex4_n_lsu_ddmh_flush => lsu_xu_ex4_n_lsu_ddmh_flush, + lsu_xu_ex6_datc_par_err => lsu_xu_ex6_datc_par_err, + spr_cpl_external_mchk => spr_cpl_external_mchk, + xu_pc_err_attention_instr => xu_pc_err_attention_instr, + xu_pc_err_nia_miscmpr => xu_pc_err_nia_miscmpr, + xu_pc_err_debug_event => xu_pc_err_debug_event, + lsu_xu_ex3_dsi => lsu_xu_ex3_dsi, + derat_xu_ex3_dsi => derat_xu_ex3_dsi, + spr_cpl_ex3_ct_le => spr_cpl_ex3_ct_le, + spr_cpl_ex3_ct_be => spr_cpl_ex3_ct_be, + lsu_xu_ex3_align => lsu_xu_ex3_align, + spr_cpl_ex3_spr_illeg => spr_cpl_ex3_spr_illeg, + spr_cpl_ex3_spr_priv => spr_cpl_ex3_spr_priv, + spr_cpl_ex3_spr_hypv => spr_cpl_ex3_spr_hypv, + derat_xu_ex3_miss => derat_xu_ex3_miss, + pc_xu_ram_mode => pc_xu_ram_mode, + pc_xu_ram_thread => pc_xu_ram_thread, + pc_xu_ram_execute => pc_xu_ram_execute, + xu_iu_ram_issue => xu_iu_ram_issue, + xu_pc_ram_interrupt => xu_pc_ram_interrupt, + xu_pc_ram_done => xu_pc_ram_done, + pc_xu_ram_flush_thread => pc_xu_ram_flush_thread, + cpl_spr_stop => cpl_spr_stop, + xu_pc_stop_dbg_event => xu_pc_stop_dbg_event, + cpl_spr_ex5_instr_cpl => cpl_spr_ex5_instr_cpl, + spr_cpl_quiesce => spr_cpl_quiesce, + cpl_spr_quiesce => cpl_spr_quiesce, + spr_cpl_ex2_run_ctl_flush => spr_cpl_ex2_run_ctl_flush, + mm_xu_illeg_instr => mm_xu_illeg_instr, + mm_xu_tlb_miss => mm_xu_tlb_miss, + mm_xu_pt_fault => mm_xu_pt_fault, + mm_xu_tlb_inelig => mm_xu_tlb_inelig, + mm_xu_lrat_miss => mm_xu_lrat_miss, + mm_xu_hv_priv => mm_xu_hv_priv, + mm_xu_esr_pt => mm_xu_esr_pt, + mm_xu_esr_data => mm_xu_esr_data, + mm_xu_esr_epid => mm_xu_esr_epid, + mm_xu_esr_st => mm_xu_esr_st, + mm_xu_hold_req => mm_xu_hold_req, + mm_xu_hold_done => mm_xu_hold_done, + xu_mm_hold_ack => xu_mm_hold_ack, + mm_xu_eratmiss_done => mm_xu_eratmiss_done, + mm_xu_ex3_flush_req => mm_xu_ex3_flush_req, + lsu_xu_l2_ecc_err_flush => lsu_xu_l2_ecc_err_flush, + lsu_xu_datc_perr_recovery => lsu_xu_datc_perr_recovery, + lsu_xu_ex3_dep_flush => lsu_xu_ex3_dep_flush, + lsu_xu_ex3_n_flush_req => lsu_xu_ex3_n_flush_req, + lsu_xu_ex3_ldq_hit_flush => lsu_xu_ex3_ldq_hit_flush, + lsu_xu_ex4_ldq_full_flush => lsu_xu_ex4_ldq_full_flush, + derat_xu_ex3_n_flush_req => derat_xu_ex3_n_flush_req, + lsu_xu_ex3_inval_align_2ucode => lsu_xu_ex3_inval_align_2ucode, + lsu_xu_ex3_attr => lsu_xu_ex3_attr, + lsu_xu_ex3_derat_vf => lsu_xu_ex3_derat_vf, + fu_xu_ex3_ap_int_req => fu_xu_ex3_ap_int_req, + fu_xu_ex3_trap => fu_xu_ex3_trap, + fu_xu_ex3_n_flush => fu_xu_ex3_n_flush, + fu_xu_ex3_np1_flush => fu_xu_ex3_np1_flush, + fu_xu_ex3_flush2ucode => fu_xu_ex3_flush2ucode, + fu_xu_ex2_async_block => fu_xu_ex2_async_block, + xu_iu_ex5_br_taken => xu_iu_ex5_br_taken, + xu_iu_ex5_ifar => xu_iu_ex5_ifar, + xu_iu_flush => xu_iu_flush, + xu_iu_iu0_flush_ifar => xu_iu_iu0_flush_ifar, + xu_iu_uc_flush_ifar => xu_iu_uc_flush_ifar, + xu_iu_flush_2ucode => xu_iu_flush_2ucode, + xu_iu_flush_2ucode_type => xu_iu_flush_2ucode_type, + xu_iu_ucode_restart => xu_iu_ucode_restart, + xu_iu_ex5_ppc_cpl => xu_iu_ex5_ppc_cpl, + xu_rf0_flush => xu_rf0_flush, + xu_rf1_flush => xu_rf1_flush, + xu_ex1_flush => xu_ex1_flush, + xu_ex2_flush => xu_ex2_flush, + xu_ex3_flush => xu_ex3_flush, + xu_ex4_flush => xu_ex4_flush, + xu_n_is2_flush => xu_n_is2_flush, + xu_n_rf0_flush => xu_n_rf0_flush, + xu_n_rf1_flush => xu_n_rf1_flush, + xu_n_ex1_flush => xu_n_ex1_flush, + xu_n_ex2_flush => xu_n_ex2_flush, + xu_n_ex3_flush => xu_n_ex3_flush, + xu_n_ex4_flush => xu_n_ex4_flush, + xu_n_ex5_flush => xu_n_ex5_flush_int, + xu_s_rf1_flush => xu_s_rf1_flush, + xu_s_ex1_flush => xu_s_ex1_flush, + xu_s_ex2_flush => xu_s_ex2_flush, + xu_s_ex3_flush => xu_s_ex3_flush, + xu_s_ex4_flush => xu_s_ex4_flush, + xu_s_ex5_flush => xu_s_ex5_flush, + xu_w_rf1_flush => xu_w_rf1_flush, + xu_w_ex1_flush => xu_w_ex1_flush, + xu_w_ex2_flush => xu_w_ex2_flush, + xu_w_ex3_flush => xu_w_ex3_flush, + xu_w_ex4_flush => xu_w_ex4_flush, + xu_w_ex5_flush => xu_w_ex5_flush, + xu_lsu_ex4_flush_local => xu_lsu_ex4_flush_local_int, + xu_mm_ex4_flush => xu_mm_ex4_flush, + xu_mm_ex5_flush => xu_mm_ex5_flush, + xu_mm_ierat_flush => xu_mm_ierat_flush, + xu_mm_ierat_miss => xu_mm_ierat_miss, + xu_mm_ex5_perf_itlb => xu_mm_ex5_perf_itlb, + xu_mm_ex5_perf_dtlb => xu_mm_ex5_perf_dtlb, + spr_cpl_iac1_en => spr_cpl_iac1_en, + spr_cpl_iac2_en => spr_cpl_iac2_en, + spr_cpl_iac3_en => spr_cpl_iac3_en, + spr_cpl_iac4_en => spr_cpl_iac4_en, + spr_bit_act => spr_bit_act, + spr_epcr_duvd => spr_epcr_duvd, + spr_dbcr1_iac12m => spr_dbcr1_iac12m, + spr_dbcr1_iac34m => spr_dbcr1_iac34m, + spr_cpl_fp_precise => spr_cpl_fp_precise, + spr_xucr0_mddp => spr_xucr0_mddp, + spr_xucr0_mdcp => spr_xucr0_mdcp, + spr_msr_de => spr_msr_de, + spr_msr_spv => spr_msr_spv, + spr_msr_fp => spr_msr_fp, + spr_msr_me => spr_msr_me, + spr_msr_ucle => spr_msr_ucle, + spr_msrp_uclep => spr_msrp_uclep, + spr_ccr2_ucode_dis => spr_ccr2_ucode_dis, + spr_ccr2_ap => spr_ccr2_ap, + spr_dbcr0_idm => spr_dbcr0_idm, + cpl_spr_dbcr0_edm => cpl_spr_dbcr0_edm, + spr_dbcr0_icmp => spr_dbcr0_icmp, + spr_dbcr0_brt => spr_dbcr0_brt, + spr_dbcr0_trap => spr_dbcr0_trap, + spr_dbcr0_ret => spr_dbcr0_ret, + spr_dbcr0_irpt => spr_dbcr0_irpt, + spr_epcr_dsigs => spr_epcr_dsigs, + spr_epcr_isigs => spr_epcr_isigs, + spr_epcr_extgs => spr_epcr_extgs, + spr_epcr_dtlbgs => spr_epcr_dtlbgs, + spr_epcr_itlbgs => spr_epcr_itlbgs, + spr_xucr4_div_barr_thres => spr_xucr4_div_barr_thres, + spr_ccr0_we => spr_ccr0_we, + cpl_msr_gs => cpl_msr_gs, + cpl_msr_pr => cpl_msr_pr, + cpl_msr_fp => cpl_msr_fp, + cpl_msr_spv => cpl_msr_spv, + cpl_ccr2_ap => cpl_ccr2_ap, + xu_lsu_ici => xu_lsu_ici, + xu_lsu_dci => xu_lsu_dci, + spr_xucr0_clkg_ctl => spr_xucr0_clkg_ctl(2 to 2), + spr_cpl_ex3_sprg_ce => spr_cpl_ex3_sprg_ce, + spr_cpl_ex3_sprg_ue => spr_cpl_ex3_sprg_ue, + iu_xu_ierat_ex2_flush_req => iu_xu_ierat_ex2_flush_req, + iu_xu_ierat_ex3_par_err => iu_xu_ierat_ex3_par_err, + iu_xu_ierat_ex4_par_err => iu_xu_ierat_ex4_par_err, + fu_xu_ex3_regfile_err_det => fu_xu_ex3_regfile_err_det, + xu_fu_regfile_seq_beg => xu_fu_regfile_seq_beg, + fu_xu_regfile_seq_end => fu_xu_regfile_seq_end, + gpr_cpl_ex3_regfile_err_det => gpr_cpl_ex3_regfile_err_det, + cpl_gpr_regfile_seq_beg => cpl_gpr_regfile_seq_beg, + gpr_cpl_regfile_seq_end => gpr_cpl_regfile_seq_end, + xu_pc_err_mcsr_summary => xu_pc_err_mcsr_summary, + xu_pc_err_ditc_overrun => xu_pc_err_ditc_overrun, + xu_pc_err_local_snoop_reject => xu_pc_err_local_snoop_reject, + xu_pc_err_tlb_lru_parity => xu_pc_err_tlb_lru_parity, + xu_pc_err_ext_mchk => xu_pc_err_ext_mchk, + xu_pc_err_ierat_multihit => xu_pc_err_ierat_multihit, + xu_pc_err_derat_multihit => xu_pc_err_derat_multihit, + xu_pc_err_tlb_multihit => xu_pc_err_tlb_multihit, + xu_pc_err_ierat_parity => xu_pc_err_ierat_parity, + xu_pc_err_derat_parity => xu_pc_err_derat_parity, + xu_pc_err_tlb_parity => xu_pc_err_tlb_parity, + xu_pc_err_mchk_disabled => xu_pc_err_mchk_disabled, + xu_pc_err_sprg_ue => xu_pc_err_sprg_ue, + cpl_debug_mux_ctrls => cpl_debug_mux_ctrls, + cpl_debug_data_in => cpl_debug_data_in, + cpl_debug_data_out => cpl_debug_data_out, + cpl_trigger_data_in => cpl_trigger_data_in, + cpl_trigger_data_out => cpl_trigger_data_out, + fxa_cpl_debug => fxa_cpl_debug + ); + +lsucmd : entity work.xuq_lsu_cmd(xuq_lsu_cmd) +generic map(expand_type => expand_type, + lmq_entries => lmq_entries, + l_endian_m => l_endian_m, + regmode => regmode, + dc_size => dc_size, + cl_size => cl_size, + real_data_add => real_data_add, + a2mode => a2mode, + load_credits => load_credits, + store_credits => store_credits, + bcfg_epn_0to15 => bcfg_epn_0to15, + bcfg_epn_16to31 => bcfg_epn_16to31, + bcfg_epn_32to47 => bcfg_epn_32to47, + bcfg_epn_48to51 => bcfg_epn_48to51, + bcfg_rpn_22to31 => bcfg_rpn_22to31, + bcfg_rpn_32to47 => bcfg_rpn_32to47, + bcfg_rpn_48to51 => bcfg_rpn_48to51, + st_data_32B_mode => st_data_32B_mode) +port map( + xu_lsu_rf0_act => xu_lsu_rf0_act, + xu_lsu_rf1_cmd_act => xu_lsu_rf1_cmd_act, + xu_lsu_rf1_axu_op_val => xu_lsu_rf1_axu_op_val, + xu_lsu_rf1_axu_ldst_falign => xu_lsu_rf1_axu_ldst_falign_int, + xu_lsu_rf1_axu_ldst_fexcpt => xu_lsu_rf1_axu_ldst_fexcpt, + xu_lsu_rf1_cache_acc => xu_lsu_rf1_cache_acc, + xu_lsu_rf1_thrd_id => xu_lsu_rf1_thrd_id, + xu_lsu_rf1_optype1 => xu_lsu_rf1_optype1, + xu_lsu_rf1_optype2 => xu_lsu_rf1_optype2, + xu_lsu_rf1_optype4 => xu_lsu_rf1_optype4, + xu_lsu_rf1_optype8 => xu_lsu_rf1_optype8, + xu_lsu_rf1_optype16 => xu_lsu_rf1_optype16, + xu_lsu_rf1_optype32 => xu_lsu_rf1_optype32, + xu_lsu_rf1_target_gpr => xu_lsu_rf1_target_gpr, + xu_lsu_rf1_mtspr_trace => xu_lsu_rf1_mtspr_trace, + xu_lsu_rf1_load_instr => xu_lsu_rf1_load_instr, + xu_lsu_rf1_store_instr => xu_lsu_rf1_store_instr, + xu_lsu_rf1_dcbf_instr => xu_lsu_rf1_dcbf_instr, + xu_lsu_rf1_sync_instr => xu_lsu_rf1_sync_instr, + xu_lsu_rf1_l_fld => xu_lsu_rf1_l_fld, + xu_lsu_rf1_dcbi_instr => xu_lsu_rf1_dcbi_instr, + xu_lsu_rf1_dcbz_instr => xu_lsu_rf1_dcbz_instr, + xu_lsu_rf1_dcbt_instr => xu_lsu_rf1_dcbt_instr, + xu_lsu_rf1_dcbtst_instr => xu_lsu_rf1_dcbtst_instr, + xu_lsu_rf1_th_fld => xu_lsu_rf1_th_fld, + xu_lsu_rf1_dcbtls_instr => xu_lsu_rf1_dcbtls_instr, + xu_lsu_rf1_dcbtstls_instr => xu_lsu_rf1_dcbtstls_instr, + xu_lsu_rf1_dcblc_instr => xu_lsu_rf1_dcblc_instr, + xu_lsu_rf1_dcbst_instr => xu_lsu_rf1_dcbst_instr, + xu_lsu_rf1_icbi_instr => xu_lsu_rf1_icbi_instr, + xu_lsu_rf1_icblc_instr => xu_lsu_rf1_icblc_instr, + xu_lsu_rf1_icbt_instr => xu_lsu_rf1_icbt_instr, + xu_lsu_rf1_icbtls_instr => xu_lsu_rf1_icbtls_instr, + xu_lsu_rf1_icswx_instr => xu_lsu_rf1_icswx_instr, + xu_lsu_rf1_icswx_dot_instr => xu_lsu_rf1_icswx_dot_instr, + xu_lsu_rf1_icswx_epid => xu_lsu_rf1_icswx_epid, + xu_lsu_rf1_tlbsync_instr => xu_lsu_rf1_tlbsync_instr, + xu_lsu_rf1_ldawx_instr => xu_lsu_rf1_ldawx_instr, + xu_lsu_rf1_wclr_instr => xu_lsu_rf1_wclr_instr, + xu_lsu_rf1_wchk_instr => xu_lsu_rf1_wchk_instr, + xu_lsu_rf1_lock_instr => xu_lsu_rf1_lock_instr, + xu_lsu_rf1_mutex_hint => xu_lsu_rf1_mutex_hint, + xu_lsu_rf1_mbar_instr => xu_lsu_rf1_mbar_instr, + xu_lsu_rf1_is_msgsnd => xu_lsu_rf1_is_msgsnd, + xu_lsu_rf1_dci_instr => xu_lsu_rf1_dci_instr, + xu_lsu_rf1_ici_instr => xu_lsu_rf1_ici_instr, + xu_lsu_rf1_algebraic => xu_lsu_rf1_algebraic, + xu_lsu_rf1_byte_rev => xu_lsu_rf1_byte_rev, + xu_lsu_rf1_src_gpr => xu_lsu_rf1_src_gpr, + xu_lsu_rf1_src_axu => xu_lsu_rf1_src_axu, + xu_lsu_rf1_src_dp => xu_lsu_rf1_src_dp, + xu_lsu_rf1_targ_gpr => xu_lsu_rf1_targ_gpr, + xu_lsu_rf1_targ_axu => xu_lsu_rf1_targ_axu, + xu_lsu_rf1_targ_dp => xu_lsu_rf1_targ_dp, + xu_lsu_ex4_val => xu_lsu_ex4_val, + xu_lsu_ex1_add_src0 => xu_lsu_ex1_add_src0, + xu_lsu_ex1_add_src1 => xu_lsu_ex1_add_src1, + xu_lsu_ex2_instr_trace_val => xu_lsu_ex2_instr_trace_val, + + xu_lsu_rf1_src0_vld => xu_lsu_rf1_src0_vld, + xu_lsu_rf1_src0_reg => xu_lsu_rf1_src0_reg, + xu_lsu_rf1_src1_vld => xu_lsu_rf1_src1_vld, + xu_lsu_rf1_src1_reg => xu_lsu_rf1_src1_reg, + xu_lsu_rf1_targ_vld => xu_lsu_rf1_targ_vld, + xu_lsu_rf1_targ_reg => xu_lsu_rf1_targ_reg, + + pc_xu_inj_dcachedir_parity => pc_xu_inj_dcachedir_parity, + pc_xu_inj_dcachedir_multihit => pc_xu_inj_dcachedir_multihit, + + derat_xu_ex3_n_flush_req => derat_xu_ex3_n_flush_req, + derat_xu_ex3_miss => derat_xu_ex3_miss, + derat_xu_ex3_dsi => derat_xu_ex3_dsi, + lsu_xu_ex3_derat_multihit_err => lsu_xu_ex3_derat_multihit_err, + lsu_xu_ex3_derat_par_err => lsu_xu_ex3_derat_par_err, + lsu_xu_ex4_derat_par_err => lsu_xu_ex4_derat_par_err, + + ex4_256st_data => ex4_256st_data, + xu_lsu_ex4_dvc1_en => xu_lsu_ex4_dvc1_en, + xu_lsu_ex4_dvc2_en => xu_lsu_ex4_dvc2_en, + + xu_lsu_mtspr_trace_en => xu_lsu_mtspr_trace_en, + spr_xucr0_clkg_ctl_b1 => spr_xucr0_clkg_ctl(1), + spr_xucr0_clkg_ctl_b3 => spr_xucr0_clkg_ctl(3), + spr_xucr4_mmu_mchk => spr_xucr4_mmu_mchk_int, + xu_lsu_spr_xucr0_aflsta => xu_lsu_spr_xucr0_aflsta, + xu_lsu_spr_xucr0_flsta => xu_lsu_spr_xucr0_flsta, + xu_lsu_spr_xucr0_l2siw => xu_lsu_spr_xucr0_l2siw, + xu_lsu_spr_xucr0_dcdis => xu_lsu_spr_xucr0_dcdis, + xu_lsu_spr_xucr0_wlk => xu_lsu_spr_xucr0_wlk, + xu_lsu_spr_xucr0_flh2l2 => xu_lsu_spr_xucr0_flh2l2, + xu_lsu_spr_xucr0_clfc => xu_lsu_spr_xucr0_clfc, + xu_lsu_spr_xucr0_cred => xu_lsu_spr_xucr0_cred, + xu_lsu_spr_xucr0_rel => xu_lsu_spr_xucr0_rel, + xu_lsu_spr_xucr0_mbar_ack => xu_lsu_spr_xucr0_mbar_ack, + xu_lsu_spr_xucr0_tlbsync => xu_lsu_spr_xucr0_tlbsync, + xu_lsu_spr_xucr0_cls => xu_lsu_spr_xucr0_cls, + xu_lsu_spr_ccr2_dfrat => xu_lsu_spr_ccr2_dfrat, + xu_lsu_spr_ccr2_dfratsc => xu_lsu_spr_ccr2_dfratsc, + xu_lsu_ex5_set_barr => xu_lsu_ex5_set_barr, + + an_ac_flh2l2_gate => an_ac_flh2l2_gate, + + xu_lsu_dci => xu_lsu_dci, + + xu_lsu_rf0_derat_val => xu_lsu_rf0_derat_val, + xu_lsu_rf1_derat_act => xu_lsu_rf1_derat_act, + xu_lsu_rf1_derat_ra_eq_ea => xu_lsu_rf1_derat_ra_eq_ea, + xu_lsu_rf1_derat_is_load => xu_lsu_rf1_derat_is_load, + xu_lsu_rf1_derat_is_store => xu_lsu_rf1_derat_is_store, + xu_lsu_rf0_derat_is_extload => xu_lsu_rf0_derat_is_extload, + xu_lsu_rf0_derat_is_extstore => xu_lsu_rf0_derat_is_extstore, + xu_lsu_rf1_is_eratre => xu_rf1_is_eratre_int, + xu_lsu_rf1_is_eratwe => xu_rf1_is_eratwe_int, + xu_lsu_rf1_is_eratsx => xu_rf1_is_eratsx_int, + xu_lsu_rf1_is_eratilx => xu_rf1_is_eratilx_int, + xu_lsu_ex1_is_isync => xu_ex1_is_isync_int, + xu_lsu_ex1_is_csync => xu_ex1_is_csync_int, + xu_lsu_rf1_is_touch => xu_lsu_rf1_is_touch, + xu_lsu_rf1_ws => xu_rf1_ws_int, + xu_lsu_rf1_t => xu_rf1_t_int, + xu_lsu_ex1_rs_is => xu_ex1_rs_is_int, + xu_lsu_ex1_ra_entry => xu_ex1_ra_entry_int(7 to 11), + xu_lsu_ex4_rs_data => xu_ex4_rs_data_int, + xu_lsu_msr_gs => spr_msr_gs, + xu_lsu_msr_pr => spr_msr_pr, + xu_lsu_msr_ds => spr_msr_ds, + xu_lsu_msr_cm => spr_msr_cm, + xu_lsu_hid_mmu_mode => xu_lsu_hid_mmu_mode, + ex6_ld_par_err => ex6_ld_par_err, + + xu_lsu_rf0_flush => xu_rf0_flush, + xu_lsu_rf1_flush => xu_rf1_flush, + xu_lsu_ex1_flush => xu_ex1_flush, + xu_lsu_ex2_flush => xu_ex2_flush, + xu_lsu_ex3_flush => xu_ex3_flush, + xu_lsu_ex4_flush => xu_ex4_flush, + xu_lsu_ex5_flush => xu_n_ex5_flush_int, + + lsu_xu_ex4_tlb_data => lsu_xu_ex4_tlb_data, + xu_mm_derat_req => xu_mm_derat_req, + xu_mm_derat_thdid => xu_mm_derat_thdid, + xu_mm_derat_state => xu_mm_derat_state, + xu_mm_derat_tid => xu_mm_derat_tid, + xu_mm_derat_lpid => xu_mm_derat_lpid, + xu_mm_derat_ttype => xu_mm_derat_ttype, + mm_xu_derat_rel_val => mm_xu_derat_rel_val, + mm_xu_derat_rel_data => mm_xu_derat_rel_data, + mm_xu_derat_pid0 => mm_xu_derat_pid0, + mm_xu_derat_pid1 => mm_xu_derat_pid1, + mm_xu_derat_pid2 => mm_xu_derat_pid2, + mm_xu_derat_pid3 => mm_xu_derat_pid3, + mm_xu_derat_mmucr0_0 => mm_xu_derat_mmucr0_0, + mm_xu_derat_mmucr0_1 => mm_xu_derat_mmucr0_1, + mm_xu_derat_mmucr0_2 => mm_xu_derat_mmucr0_2, + mm_xu_derat_mmucr0_3 => mm_xu_derat_mmucr0_3, + xu_mm_derat_mmucr0 => xu_mm_derat_mmucr0, + xu_mm_derat_mmucr0_we => xu_mm_derat_mmucr0_we, + mm_xu_derat_mmucr1 => mm_xu_derat_mmucr1, + xu_mm_derat_mmucr1 => xu_mm_derat_mmucr1, + xu_mm_derat_mmucr1_we => xu_mm_derat_mmucr1_we, + mm_xu_derat_snoop_coming => mm_xu_derat_snoop_coming, + mm_xu_derat_snoop_val => mm_xu_derat_snoop_val, + mm_xu_derat_snoop_attr => mm_xu_derat_snoop_attr, + mm_xu_derat_snoop_vpn => mm_xu_derat_snoop_vpn , + xu_mm_derat_snoop_ack => xu_mm_derat_snoop_ack , + + xu_lsu_slowspr_val => xu_lsu_slowspr_val, + xu_lsu_slowspr_rw => xu_lsu_slowspr_rw, + xu_lsu_slowspr_etid => xu_lsu_slowspr_etid, + xu_lsu_slowspr_addr => xu_lsu_slowspr_addr, + xu_lsu_slowspr_data => xu_lsu_slowspr_data, + xu_lsu_slowspr_done => xu_lsu_slowspr_done, + slowspr_val_out => slowspr_val_out, + slowspr_rw_out => slowspr_rw_out, + slowspr_etid_out => slowspr_etid_out, + slowspr_addr_out => slowspr_addr_out, + slowspr_data_out => slowspr_data_out, + slowspr_done_out => slowspr_done_out, + + ex1_optype1 => ex1_optype1, + ex1_optype2 => ex1_optype2, + ex1_optype4 => ex1_optype4, + ex1_optype8 => ex1_optype8, + ex1_optype16 => ex1_optype16, + ex1_optype32 => ex1_optype32, + ex1_saxu_instr => ex1_saxu_instr, + ex1_sdp_instr => ex1_sdp_instr, + ex1_stgpr_instr => ex1_stgpr_instr, + ex1_store_instr => ex1_store_instr, + ex1_axu_op_val => ex1_axu_op_val, + + lsu_xu_ex3_align => lsu_xu_ex3_align, + lsu_xu_ex3_dsi => lsu_xu_ex3_dsi, + lsu_xu_ex3_inval_align_2ucode => lsu_xu_ex3_inval_align_2ucode, + lsu_xu_ex3_attr => lsu_xu_ex3_attr, + lsu_xu_ex3_derat_vf => lsu_xu_ex3_derat_vf, + + lsu_xu_ex3_n_flush_req => lsu_xu_ex3_n_flush_req, + lsu_xu_ex4_ldq_full_flush => lsu_xu_ex4_ldq_full_flush, + lsu_xu_ex3_ldq_hit_flush => lsu_xu_ex3_ldq_hit_flush, + lsu_xu_ex3_dep_flush => lsu_xu_ex3_dep_flush, + lsu_xu_datc_perr_recovery => lsu_xu_datc_perr_recovery, + lsu_xu_l2_ecc_err_flush => lsu_xu_l2_ecc_err_flush, + + ex3_algebraic => ex3_algebraic, + ex3_data_swap => ex3_data_swap, + ex3_thrd_id => ex3_thrd_id, + xu_fu_ex3_eff_addr => xu_fu_ex3_eff_addr, + + lsu_xu_ex3_ddir_par_err => lsu_xu_ex3_ddir_par_err, + lsu_xu_ex4_n_lsu_ddmh_flush => lsu_xu_ex4_n_lsu_ddmh_flush, + + lsu_xu_is2_back_inv => lsu_xu_is2_back_inv, + lsu_xu_is2_back_inv_addr => lsu_xu_is2_back_inv_addr, + lsu_xu_ex4_cr_upd => lsu_xu_ex4_cr_upd, + lsu_xu_ex5_cr_rslt => lsu_xu_ex5_cr_rslt, + + rel_upd_dcarr_val => rel_upd_dcarr_val, + + lsu_xu_ex5_wren => lsu_xu_ex5_wren, + lsu_xu_rel_wren => lsu_xu_rel_wren_int, + lsu_xu_rel_ta_gpr => lsu_xu_rel_ta_gpr_int, + lsu_xu_need_hole => lsu_xu_need_hole, + xu_fu_ex5_reload_val => xu_fu_ex5_reload_val, + xu_fu_ex5_load_val => xu_fu_ex5_load_val, + xu_fu_ex5_load_tag => xu_fu_ex5_load_tag, + + dcarr_up_way_addr => dcarr_up_way_addr, + + lsu_xu_spr_xucr0_cslc_xuop => lsu_xu_spr_xucr0_cslc_xuop, + lsu_xu_spr_xucr0_cslc_binv => lsu_xu_spr_xucr0_cslc_binv, + lsu_xu_spr_xucr0_clo => lsu_xu_spr_xucr0_clo, + lsu_xu_spr_xucr0_cul => lsu_xu_spr_xucr0_cul, + lsu_xu_spr_epsc_epr => lsu_xu_spr_epsc_epr, + lsu_xu_spr_epsc_egs => lsu_xu_spr_epsc_egs, + + ex4_load_op_hit => ex4_load_op_hit, + ex4_store_hit => ex4_store_hit, + ex4_axu_op_val => ex4_axu_op_val, + spr_dvc1_act => spr_dvc1_act, + spr_dvc2_act => spr_dvc2_act, + spr_dvc1_dbg => spr_dvc1_dbg, + spr_dvc2_dbg => spr_dvc2_dbg, + + an_ac_req_ld_pop => an_ac_req_ld_pop, + an_ac_req_st_pop => an_ac_req_st_pop, + an_ac_req_st_gather => an_ac_req_st_gather, + an_ac_req_st_pop_thrd => an_ac_req_st_pop_thrd, + an_ac_reld_data_val => an_ac_reld_data_vld, + an_ac_reld_core_tag => an_ac_reld_core_tag, + an_ac_reld_qw => an_ac_reld_qw, + an_ac_reld_data => an_ac_reld_data, + an_ac_reld_ecc_err => an_ac_reld_ecc_err, + an_ac_reld_ecc_err_ue => an_ac_reld_ecc_err_ue, + an_ac_reld_data_coming => an_ac_reld_data_coming, + an_ac_reld_ditc => an_ac_reld_ditc, + an_ac_reld_crit_qw => an_ac_reld_crit_qw, + an_ac_reld_l1_dump => an_ac_reld_l1_dump, + + an_ac_back_inv => an_ac_back_inv, + an_ac_back_inv_addr => an_ac_back_inv_addr, + an_ac_back_inv_target_bit1 => an_ac_back_inv_target_bit1, + an_ac_back_inv_target_bit4 => an_ac_back_inv_target_bit4, + + an_ac_req_spare_ctrl_a1 => an_ac_req_spare_ctrl_a1, + + an_ac_stcx_complete => an_ac_stcx_complete, + xu_iu_stcx_complete => xu_iu_stcx_complete, + xu_iu_reld_core_tag_clone => xu_iu_reld_core_tag_clone, + xu_iu_reld_data_coming_clone => xu_iu_reld_data_coming_clone, + xu_iu_reld_data_vld_clone => xu_iu_reld_data_vld_clone, + xu_iu_reld_ditc_clone => xu_iu_reld_ditc_clone, + + lsu_reld_data_vld => lsu_reld_data_vld, + lsu_reld_core_tag => lsu_reld_core_tag, + lsu_reld_qw => lsu_reld_qw, + lsu_reld_ditc => lsu_reld_ditc, + lsu_reld_ecc_err => lsu_reld_ecc_err, + lsu_reld_data => lsu_reld_data, + lsu_req_st_pop => lsu_req_st_pop, + lsu_req_st_pop_thrd => lsu_req_st_pop_thrd, + + ac_an_reld_ditc_pop_int => ac_an_reld_ditc_pop_int, + ac_an_reld_ditc_pop_q => ac_an_reld_ditc_pop_q , + bx_ib_empty_int => bx_ib_empty_int , + bx_ib_empty_q => bx_ib_empty_q , + + + i_x_ra => iu_xu_ra, + i_x_request => iu_xu_request, + i_x_wimge => iu_xu_wimge, + i_x_thread => iu_xu_thread, + i_x_userdef => iu_xu_userdef, + + mm_xu_lsu_req => mm_xu_lsu_req, + mm_xu_lsu_ttype => mm_xu_lsu_ttype, + mm_xu_lsu_wimge => mm_xu_lsu_wimge, + mm_xu_lsu_u => mm_xu_lsu_u, + mm_xu_lsu_addr => mm_xu_lsu_addr, + mm_xu_lsu_lpid => mm_xu_lsu_lpid, + mm_xu_lsu_lpidr => mm_xu_lsu_lpidr, + mm_xu_lsu_gs => mm_xu_lsu_gs , + mm_xu_lsu_ind => mm_xu_lsu_ind , + mm_xu_lsu_lbit => mm_xu_lsu_lbit, + xu_mm_lsu_token => xu_mm_lsu_token, + + bx_lsu_ob_pwr_tok => bx_lsu_ob_pwr_tok, + bx_lsu_ob_req_val => bx_lsu_ob_req_val, + bx_lsu_ob_ditc_val => bx_lsu_ob_ditc_val, + bx_lsu_ob_thrd => bx_lsu_ob_thrd, + bx_lsu_ob_qw => bx_lsu_ob_qw, + bx_lsu_ob_dest => bx_lsu_ob_dest, + bx_lsu_ob_data => bx_lsu_ob_data, + bx_lsu_ob_addr => bx_lsu_ob_addr, + + lsu_bx_cmd_avail => lsu_bx_cmd_avail, + lsu_bx_cmd_sent => lsu_bx_cmd_sent, + lsu_bx_cmd_stall => lsu_bx_cmd_stall, + + lsu_xu_ldq_barr_done => lsu_xu_ldq_barr_done, + lsu_xu_barr_done => lsu_xu_barr_done, + + ldq_rel_data_val_early => ldq_rel_data_val_early, + ldq_rel_op_size => ldq_rel_op_size, + ldq_rel_addr => ldq_rel_addr, + ldq_rel_data_val => ldq_rel_data_val, + ldq_rel_rot_sel => ldq_rel_rot_sel, + ldq_rel_axu_val => ldq_rel_axu_val, + ldq_rel_ci => ldq_rel_ci, + ldq_rel_thrd_id => ldq_rel_thrd_id, + ldq_rel_le_mode => ldq_rel_le_mode, + ldq_rel_algebraic => ldq_rel_algebraic, + ldq_rel_256_data => ldq_rel_256_data, + ldq_rel_dvc1_en => ldq_rel_dvc1_en, + ldq_rel_dvc2_en => ldq_rel_dvc2_en, + ldq_rel_beat_crit_qw => ldq_rel_beat_crit_qw, + ldq_rel_beat_crit_qw_block => ldq_rel_beat_crit_qw_block, + + xu_iu_ex4_loadmiss_qentry => xu_iu_ex4_loadmiss_qentry, + xu_iu_ex4_loadmiss_target => xu_iu_ex4_loadmiss_target, + xu_iu_ex4_loadmiss_target_type => xu_iu_ex4_loadmiss_target_type, + xu_iu_ex4_loadmiss_tid => xu_iu_ex4_loadmiss_tid, + xu_iu_ex5_loadmiss_qentry => xu_iu_ex5_loadmiss_qentry, + xu_iu_ex5_loadmiss_target => xu_iu_ex5_loadmiss_target, + xu_iu_ex5_loadmiss_target_type => xu_iu_ex5_loadmiss_target_type, + xu_iu_ex5_loadmiss_tid => xu_iu_ex5_loadmiss_tid, + xu_iu_complete_qentry => xu_iu_complete_qentry, + xu_iu_complete_tid => xu_iu_complete_tid, + xu_iu_complete_target_type => xu_iu_complete_target_type, + + xu_iu_ex6_icbi_val => xu_iu_ex6_icbi_val, + xu_iu_ex6_icbi_addr => xu_iu_ex6_icbi_addr, + + xu_iu_larx_done_tid => xu_iu_larx_done_tid, + xu_mm_lmq_stq_empty => xu_mm_lmq_stq_empty, + lsu_xu_quiesce => lsu_xu_quiesce, + lsu_xu_dbell_val => lsu_xu_dbell_val, + lsu_xu_dbell_type => lsu_xu_dbell_type, + lsu_xu_dbell_brdcast => lsu_xu_dbell_brdcast, + lsu_xu_dbell_lpid_match => lsu_xu_dbell_lpid_match, + lsu_xu_dbell_pirtag => lsu_xu_dbell_pirtag, + + ac_an_req_pwr_token => ac_an_req_pwr_token, + ac_an_req => ac_an_req, + ac_an_req_ra => ac_an_req_ra, + ac_an_req_ttype => ac_an_req_ttype, + ac_an_req_thread => ac_an_req_thread, + ac_an_req_wimg_w => ac_an_req_wimg_w, + ac_an_req_wimg_i => ac_an_req_wimg_i, + ac_an_req_wimg_m => ac_an_req_wimg_m, + ac_an_req_wimg_g => ac_an_req_wimg_g, + ac_an_req_endian => ac_an_req_endian, + ac_an_req_user_defined => ac_an_req_user_defined, + ac_an_req_spare_ctrl_a0 => ac_an_req_spare_ctrl_a0, + ac_an_req_ld_core_tag => ac_an_req_ld_core_tag, + ac_an_req_ld_xfr_len => ac_an_req_ld_xfr_len, + ac_an_st_byte_enbl => ac_an_st_byte_enbl, + ac_an_st_data => ac_an_st_data, + ac_an_st_data_pwr_token => ac_an_st_data_pwr_token, + + lsu_xu_ex3_l2_uc_ecc_err => lsu_xu_ex3_l2_uc_ecc_err, + xu_pc_err_dcachedir_parity => xu_pc_err_dcachedir_parity, + xu_pc_err_dcachedir_multihit => xu_pc_err_dcachedir_multihit, + xu_pc_err_l2intrf_ecc => xu_pc_err_l2intrf_ecc, + xu_pc_err_l2intrf_ue => xu_pc_err_l2intrf_ue, + xu_pc_err_invld_reld => xu_pc_err_invld_reld, + xu_pc_err_l2credit_overrun => xu_pc_err_l2credit_overrun, + pc_xu_event_bus_enable => pc_xu_event_bus_enable, + pc_xu_event_count_mode => pc_xu_event_count_mode, + pc_xu_lsu_event_mux_ctrls => pc_xu_lsu_event_mux_ctrls, + pc_xu_cache_par_err_event => pc_xu_cache_par_err_event, + xu_pc_lsu_event_data => xu_pc_lsu_event_data, + + pc_xu_trace_bus_enable => pc_xu_trace_bus_enable, + lsu_debug_mux_ctrls => lsu_debug_mux_ctrls, + trigger_data_in => lsu_trigger_data_in, + debug_data_in => lsu_debug_data_in, + trigger_data_out => lsu_trigger_data_out, + debug_data_out => lsu_debug_data_out, + lsu_xu_cmd_debug => lsu_xu_cmd_debug, + + vcs => vcs, + vdd => vdd, + gnd => gnd, + nclk => nclk, + + pc_xu_abist_g8t_wenb => pc_xu_abist_g8t_wenb, + pc_xu_abist_g8t1p_renb_0 => pc_xu_abist_g8t1p_renb_0, + pc_xu_abist_di_0 => pc_xu_abist_di_0, + pc_xu_abist_g8t_bw_1 => pc_xu_abist_g8t_bw_1, + pc_xu_abist_g8t_bw_0 => pc_xu_abist_g8t_bw_0, + pc_xu_abist_waddr_0 => pc_xu_abist_waddr_0(5 to 9), + pc_xu_abist_raddr_0 => pc_xu_abist_raddr_0(5 to 9), + an_ac_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc, + pc_xu_abist_ena_dc => pc_xu_abist_ena_dc, + pc_xu_abist_wl32_comp_ena => pc_xu_abist_wl32_comp_ena, + pc_xu_abist_raw_dc_b => pc_xu_abist_raw_dc_b, + pc_xu_abist_g8t_dcomp => pc_xu_abist_g8t_dcomp, + pc_xu_bo_unload => pc_xu_bo_unload, + pc_xu_bo_repair => pc_xu_bo_repair, + pc_xu_bo_reset => pc_xu_bo_reset, + pc_xu_bo_shdata => pc_xu_bo_shdata, + pc_xu_bo_select => pc_xu_bo_select, + xu_pc_bo_fail => xu_pc_bo_fail, + xu_pc_bo_diagout => xu_pc_bo_diagout, + + an_ac_grffence_en_dc => an_ac_grffence_en_dc, + an_ac_coreid => an_ac_coreid, + pc_xu_init_reset => pc_xu_init_reset, + pc_xu_ccflush_dc => pc_xu_ccflush_dc, + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b, + an_ac_atpg_en_dc => an_ac_atpg_en_dc, + an_ac_scan_diag_dc => an_ac_scan_diag_dc, + an_ac_lbist_en_dc => an_ac_lbist_en_dc, + clkoff_dc_b => clkoff_dc_b_b, + sg_2 => sg_2_b(2 to 3), + fce_2 => fce_2_b(1), + func_sl_thold_2 => func_sl_thold_2_b(2 to 3), + func_nsl_thold_2 => func_nsl_thold_2_b, + func_slp_sl_thold_2 => func_slp_sl_thold_2_b(1), + func_slp_nsl_thold_2 => func_slp_nsl_thold_2_b, + cfg_slp_sl_thold_2 => cfg_slp_sl_thold_2_b, + ary_slp_nsl_thold_2 => ary_slp_nsl_thold_2, + regf_slp_sl_thold_2 => regf_slp_sl_thold_2_b, + abst_slp_sl_thold_2 => abst_slp_sl_thold_2, + time_sl_thold_2 => time_sl_thold_2_b, + repr_sl_thold_2 => repr_sl_thold_2_b, + bolt_sl_thold_2 => bolt_sl_thold_2_b, + bo_enable_2 => bo_enable_2_b, + d_mode_dc => d_mode_dc_b, + delay_lclkr_dc => delay_lclkr_dc_b, + mpw1_dc_b => mpw1_dc_b_b, + mpw2_dc_b => mpw2_dc_b_b, + g8t_clkoff_dc_b => g8t_clkoff_dc_b, + g8t_d_mode_dc => g8t_d_mode_dc, + g8t_delay_lclkr_dc => g8t_delay_lclkr_dc, + g8t_mpw1_dc_b => g8t_mpw1_dc_b, + g8t_mpw2_dc_b => g8t_mpw2_dc_b, + cam_clkoff_dc_b => cam_clkoff_dc_b, + cam_d_mode_dc => cam_d_mode_dc, + cam_delay_lclkr_dc => cam_delay_lclkr_dc, + cam_act_dis_dc => cam_act_dis_dc, + cam_mpw1_dc_b => cam_mpw1_dc_b, + cam_mpw2_dc_b => cam_mpw2_dc_b, + bcfg_scan_in => bcfg_scan_out_int, + bcfg_scan_out => bcfg_scan_out, + ccfg_scan_in => ccfg_scan_out_int, + ccfg_scan_out => ccfg_scan_out, + dcfg_scan_in => dcfg_scan_out_int, + dcfg_scan_out => dcfg_scan_out, + regf_scan_in => regf_scan_in, + regf_scan_out => regf_scan_out, + abst_scan_in => abst_scan_in, + time_scan_in => time_scan_in, + repr_scan_in => repr_scan_in, + abst_scan_out => abst_scan_out, + time_scan_out => time_scan_out, + repr_scan_out => repr_scan_out, + func_scan_in => func_scan_in(41 to 49), + func_scan_out => func_scan_out(41 to 49) +); + +xu_lsu_ex4_flush_local <= xu_lsu_ex4_flush_local_int; + +xu_rf1_is_eratre <= xu_rf1_is_eratre_int; +xu_rf1_is_eratwe <= xu_rf1_is_eratwe_int; +xu_rf1_is_eratsx <= xu_rf1_is_eratsx_int; +xu_rf1_is_eratsrx <= xu_rf1_is_eratsrx_int; +xu_rf1_is_eratilx <= xu_rf1_is_eratilx_int; +xu_rf1_is_erativax <= xu_rf1_is_erativax_int; +xu_ex1_is_isync <= xu_ex1_is_isync_int; +xu_ex1_is_csync <= xu_ex1_is_csync_int; +xu_rf1_ws <= xu_rf1_ws_int; +xu_rf1_t <= xu_rf1_t_int; +xu_ex1_rs_is <= xu_ex1_rs_is_int; +xu_ex1_ra_entry <= xu_ex1_ra_entry_int(8 to 11); +xu_ex4_rs_data <= xu_ex4_rs_data_int; +xu_lsu_ex1_eff_addr <= xu_ex1_eff_addr_int; +lsu_xu_rel_wren <= lsu_xu_rel_wren_int; +lsu_xu_rel_ta_gpr <= lsu_xu_rel_ta_gpr_int; +xu_lsu_rf1_axu_ldst_falign <= xu_lsu_rf1_axu_ldst_falign_int; + +end xuq_ctrl; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_ctrl_spr.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_ctrl_spr.vhdl new file mode 100644 index 0000000..bd43f53 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_ctrl_spr.vhdl @@ -0,0 +1,2210 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee,ibm,support,work,tri,clib; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use support.power_logic_pkg.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use tri.tri_latches_pkg.all; +use work.xuq_pkg.all; + +entity xuq_ctrl_spr is +generic( + expand_type : integer := 2; + threads : integer := 4; + eff_ifar : integer := 62; + spr_xucr0_init_mod : integer := 0; + uc_ifar : integer := 21; + regsize : integer := 64; + hvmode : integer := 1; + regmode : integer := 6; + dc_size : natural := 14; + cl_size : natural := 6; + real_data_add : integer := 42; + fxu_synth : integer := 0; + a2mode : integer := 1; + lmq_entries : integer := 8; + l_endian_m : integer := 1; + load_credits : integer := 4; + store_credits : integer := 20; + st_data_32B_mode : integer := 1; + bcfg_epn_0to15 : integer := 0; + bcfg_epn_16to31 : integer := 0; + bcfg_epn_32to47 : integer := (2**16)-1; + bcfg_epn_48to51 : integer := (2**4)-1; + bcfg_rpn_22to31 : integer := (2**10)-1; + bcfg_rpn_32to47 : integer := (2**16)-1; + bcfg_rpn_48to51 : integer := (2**4)-1); +port( + + fxa_fxb_rf0_val :in std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_issued :in std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_ucode_val :in std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_act :in std_ulogic; + fxa_fxb_ex1_hold_ctr_flush :in std_ulogic; + fxa_fxb_rf0_instr :in std_ulogic_vector(0 to 31); + fxa_fxb_rf0_tid :in std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_ta_vld :in std_ulogic; + fxa_fxb_rf0_ta :in std_ulogic_vector(0 to 7); + fxa_fxb_rf0_error :in std_ulogic_vector(0 to 2); + fxa_fxb_rf0_match :in std_ulogic; + fxa_fxb_rf0_is_ucode :in std_ulogic; + fxa_fxb_rf0_gshare :in std_ulogic_vector(0 to 3); + fxa_fxb_rf0_ifar :in std_ulogic_vector(62-eff_ifar to 61); + fxa_fxb_rf0_s1_vld :in std_ulogic; + fxa_fxb_rf0_s1 :in std_ulogic_vector(0 to 7); + fxa_fxb_rf0_s2_vld :in std_ulogic; + fxa_fxb_rf0_s2 :in std_ulogic_vector(0 to 7); + fxa_fxb_rf0_s3_vld :in std_ulogic; + fxa_fxb_rf0_s3 :in std_ulogic_vector(0 to 7); + fxa_fxb_rf0_axu_instr_type :in std_ulogic_vector(0 to 2); + fxa_fxb_rf0_axu_ld_or_st :in std_ulogic; + fxa_fxb_rf0_axu_store :in std_ulogic; + fxa_fxb_rf0_axu_ldst_forcealign :in std_ulogic; + fxa_fxb_rf0_axu_ldst_forceexcept :in std_ulogic; + fxa_fxb_rf0_axu_ldst_indexed :in std_ulogic; + fxa_fxb_rf0_axu_ldst_tag :in std_ulogic_vector(0 to 8); + fxa_fxb_rf0_axu_mftgpr :in std_ulogic; + fxa_fxb_rf0_axu_mffgpr :in std_ulogic; + fxa_fxb_rf0_axu_movedp :in std_ulogic; + fxa_fxb_rf0_axu_ldst_size :in std_ulogic_vector(0 to 5); + fxa_fxb_rf0_axu_ldst_update :in std_ulogic; + fxa_fxb_rf0_pred_update :in std_ulogic; + fxa_fxb_rf0_pred_taken_cnt :in std_ulogic_vector(0 to 1); + fxa_fxb_rf0_mc_dep_chk_val :in std_ulogic_vector(0 to threads-1); + fxa_fxb_rf1_mul_val :in std_ulogic; + fxa_fxb_rf1_div_val :in std_ulogic; + fxa_fxb_rf1_div_ctr :in std_ulogic_vector(0 to 7); + fxa_fxb_rf0_xu_epid_instr :in std_ulogic; + fxa_fxb_rf0_axu_is_extload :in std_ulogic; + fxa_fxb_rf0_axu_is_extstore :in std_ulogic; + fxa_fxb_rf0_is_mfocrf :in std_ulogic; + fxa_fxb_rf0_3src_instr :in std_ulogic; + fxa_fxb_rf0_gpr0_zero :in std_ulogic; + fxa_fxb_rf0_use_imm :in std_ulogic; + fxa_fxb_rf1_muldiv_coll :in std_ulogic; + fxa_cpl_ex2_div_coll :in std_ulogic_vector(0 to threads-1); + fxb_fxa_ex7_we0 :out std_ulogic; + fxb_fxa_ex7_wa0 :out std_ulogic_vector(0 to 7); + fxb_fxa_ex7_wd0 :out std_ulogic_vector(64-regsize to 63); + fxb_fxa_ex6_clear_barrier :out std_ulogic_vector(0 to threads-1); + fxa_fxb_rf1_do0 :in std_ulogic_vector(64-regsize to 63); + fxa_fxb_rf1_do1 :in std_ulogic_vector(64-regsize to 63); + fxa_fxb_rf1_do2 :in std_ulogic_vector(64-regsize to 63); + + xu_bx_ex1_mtdp_val :out std_ulogic; + xu_bx_ex1_mfdp_val :out std_ulogic; + xu_bx_ex1_ipc_thrd :out std_ulogic_vector(0 to 1); + xu_bx_ex2_ipc_ba :out std_ulogic_vector(0 to 4); + xu_bx_ex2_ipc_sz :out std_ulogic_vector(0 to 1); + + xu_mm_derat_epn :out std_ulogic_vector(62-eff_ifar to 51); + + xu_mm_rf1_is_tlbsxr :out std_ulogic; + mm_xu_cr0_eq_valid :in std_ulogic_vector(0 to threads-1); + mm_xu_cr0_eq :in std_ulogic_vector(0 to threads-1); + + fu_xu_ex4_cr_val :in std_ulogic_vector(0 to threads-1); + fu_xu_ex4_cr_noflush :in std_ulogic_vector(0 to threads-1); + fu_xu_ex4_cr0 :in std_ulogic_vector(0 to 3); + fu_xu_ex4_cr0_bf :in std_ulogic_vector(0 to 2); + fu_xu_ex4_cr1 :in std_ulogic_vector(0 to 3); + fu_xu_ex4_cr1_bf :in std_ulogic_vector(0 to 2); + fu_xu_ex4_cr2 :in std_ulogic_vector(0 to 3); + fu_xu_ex4_cr2_bf :in std_ulogic_vector(0 to 2); + fu_xu_ex4_cr3 :in std_ulogic_vector(0 to 3); + fu_xu_ex4_cr3_bf :in std_ulogic_vector(0 to 2); + + pc_xu_ram_mode :in std_ulogic; + pc_xu_ram_thread :in std_ulogic_vector(0 to 1); + pc_xu_ram_execute :in std_ulogic; + pc_xu_ram_flush_thread :in std_ulogic; + xu_iu_ram_issue :out std_ulogic_vector(0 to threads-1); + xu_pc_ram_interrupt :out std_ulogic; + xu_pc_ram_done :out std_ulogic; + xu_pc_ram_data :out std_ulogic_vector(64-(2**regmode) to 63); + pc_xu_msrovride_enab :in std_ulogic; + pc_xu_msrovride_gs :in std_ulogic; + pc_xu_msrovride_de :in std_ulogic; + + + xu_iu_ex5_val :out std_ulogic; + xu_iu_ex5_tid :out std_ulogic_vector(0 to threads-1); + xu_iu_ex5_br_update :out std_ulogic; + xu_iu_ex5_br_hist :out std_ulogic_vector(0 to 1); + xu_iu_ex5_bclr :out std_ulogic; + xu_iu_ex5_lk :out std_ulogic; + xu_iu_ex5_bh :out std_ulogic_vector(0 to 1); + xu_iu_ex6_pri :out std_ulogic_vector(0 to 2); + xu_iu_ex6_pri_val :out std_ulogic_vector(0 to 3); + xu_iu_spr_xer :out std_ulogic_vector(0 to 7*threads-1); + xu_iu_slowspr_done :out std_ulogic_vector(0 to threads-1); + xu_iu_need_hole :out std_ulogic; + xu_iu_ex5_gshare :out std_ulogic_vector(0 to 3); + xu_iu_ex5_getNIA :out std_ulogic; + + an_ac_stcx_complete :in std_ulogic_vector(0 to threads-1); + an_ac_stcx_pass :in std_ulogic_vector(0 to threads-1); + xu_iu_stcx_complete : out std_ulogic_vector(0 to 3); + xu_iu_reld_core_tag_clone :out std_ulogic_vector(1 to 4); + xu_iu_reld_data_coming_clone :out std_ulogic; + xu_iu_reld_data_vld_clone :out std_ulogic; + xu_iu_reld_ditc_clone :out std_ulogic; + + slowspr_val_in :in std_ulogic; + slowspr_rw_in :in std_ulogic; + slowspr_etid_in :in std_ulogic_vector(0 to 1); + slowspr_addr_in :in std_ulogic_vector(0 to 9); + slowspr_data_in :in std_ulogic_vector(64-(2**regmode) to 63); + slowspr_done_in :in std_ulogic; + slowspr_val_out :out std_ulogic; + slowspr_rw_out :out std_ulogic; + slowspr_etid_out :out std_ulogic_vector(0 to 1); + slowspr_addr_out :out std_ulogic_vector(0 to 9); + slowspr_data_out :out std_ulogic_vector(64-(2**REGMODE) to 63); + slowspr_done_out :out std_ulogic; + + an_ac_dcr_act :in std_ulogic; + an_ac_dcr_val :in std_ulogic; + an_ac_dcr_read :in std_ulogic; + an_ac_dcr_etid :in std_ulogic_vector(0 to 1); + an_ac_dcr_data :in std_ulogic_vector(64-(2**regmode) to 63); + an_ac_dcr_done :in std_ulogic; + + lsu_xu_ex4_mtdp_cr_status :in std_ulogic; + lsu_xu_ex4_mfdp_cr_status :in std_ulogic; + dec_cpl_ex3_mc_dep_chk_val :in std_ulogic_vector(0 to threads-1); + + xu_pc_event_data :out std_ulogic_vector(0 to 7); + + pc_xu_event_count_mode :in std_ulogic_vector(0 to 2); + pc_xu_event_mux_ctrls :in std_ulogic_vector(0 to 47); + + fxu_debug_mux_ctrls :in std_ulogic_vector(0 to 15); + cpl_debug_mux_ctrls :in std_ulogic_vector(0 to 15); + lsu_debug_mux_ctrls :in std_ulogic_vector(0 to 15); + spr_debug_mux_ctrls :in std_ulogic_vector(0 to 15); + trigger_data_in :in std_ulogic_vector(0 to 11); + trigger_data_out :out std_ulogic_vector(0 to 11); + debug_data_in :in std_ulogic_vector(0 to 87); + debug_data_out :out std_ulogic_vector(0 to 87); + lsu_xu_data_debug0 :in std_ulogic_vector(0 to 87); + lsu_xu_data_debug1 :in std_ulogic_vector(0 to 87); + lsu_xu_data_debug2 :in std_ulogic_vector(0 to 87); + fxa_cpl_debug :in std_ulogic_vector(0 to 272); + + + ac_tc_debug_trigger :out std_ulogic_vector(0 to threads-1); + + dec_cpl_rf0_act :in std_ulogic; + dec_cpl_rf0_tid :in std_ulogic_vector(0 to threads-1); + + fu_xu_rf1_act :in std_ulogic_vector(0 to threads-1); + fu_xu_ex1_ifar :in std_ulogic_vector(0 to eff_ifar*threads-1); + fu_xu_ex2_ifar_val :in std_ulogic_vector(0 to threads-1); + fu_xu_ex2_ifar_issued :in std_ulogic_vector(0 to threads-1); + fu_xu_ex2_instr_type :in std_ulogic_vector(0 to 3*threads-1); + fu_xu_ex2_instr_match :in std_ulogic_vector(0 to threads-1); + fu_xu_ex2_is_ucode :in std_ulogic_vector(0 to threads-1); + + pc_xu_step :in std_ulogic_vector(0 to threads-1); + pc_xu_stop :in std_ulogic_vector(0 to threads-1); + pc_xu_dbg_action :in std_ulogic_vector(0 to 3*threads-1); + pc_xu_force_ude :in std_ulogic_vector(0 to threads-1); + xu_pc_step_done :out std_ulogic_vector(0 to threads-1); + pc_xu_init_reset :in std_ulogic; + + mm_xu_local_snoop_reject :in std_ulogic_vector(0 to threads-1); + mm_xu_lru_par_err :in std_ulogic_vector(0 to threads-1); + mm_xu_tlb_par_err :in std_ulogic_vector(0 to threads-1); + mm_xu_tlb_multihit_err :in std_ulogic_vector(0 to threads-1); + an_ac_external_mchk :in std_ulogic_vector(0 to threads-1); + + xu_pc_err_attention_instr :out std_ulogic_vector(0 to threads-1); + xu_pc_err_nia_miscmpr :out std_ulogic_vector(0 to threads-1); + xu_pc_err_debug_event :out std_ulogic_vector(0 to threads-1); + + xu_pc_stop_dbg_event :out std_ulogic_vector(0 to threads-1); + + mm_xu_illeg_instr :in std_ulogic_vector(0 to threads-1); + mm_xu_tlb_miss :in std_ulogic_vector(0 to threads-1); + mm_xu_pt_fault :in std_ulogic_vector(0 to threads-1); + mm_xu_tlb_inelig :in std_ulogic_vector(0 to threads-1); + mm_xu_lrat_miss :in std_ulogic_vector(0 to threads-1); + mm_xu_hv_priv :in std_ulogic_vector(0 to threads-1); + mm_xu_esr_pt :in std_ulogic_vector(0 to threads-1); + mm_xu_esr_data :in std_ulogic_vector(0 to threads-1); + mm_xu_esr_epid :in std_ulogic_vector(0 to threads-1); + mm_xu_esr_st :in std_ulogic_vector(0 to threads-1); + mm_xu_hold_req :in std_ulogic_vector(0 to threads-1); + mm_xu_hold_done :in std_ulogic_vector(0 to threads-1); + xu_mm_hold_ack :out std_ulogic_vector(0 to threads-1); + mm_xu_eratmiss_done :in std_ulogic_vector(0 to threads-1); + mm_xu_ex3_flush_req :in std_ulogic_vector(0 to threads-1); + + fu_xu_ex3_ap_int_req :in std_ulogic_vector(0 to threads-1); + fu_xu_ex3_trap :in std_ulogic_vector(0 to threads-1); + fu_xu_ex3_n_flush :in std_ulogic_vector(0 to threads-1); + fu_xu_ex3_np1_flush :in std_ulogic_vector(0 to threads-1); + fu_xu_ex3_flush2ucode :in std_ulogic_vector(0 to threads-1); + fu_xu_ex2_async_block :in std_ulogic_vector(0 to threads-1); + + xu_iu_ex5_br_taken :out std_ulogic; + xu_iu_ex5_ifar :out std_ulogic_vector(62-eff_ifar to 61); + xu_iu_flush :out std_ulogic_vector(0 to threads-1); + xu_iu_iu0_flush_ifar :out std_ulogic_vector(0 to eff_ifar*threads-1); + xu_iu_uc_flush_ifar :out std_ulogic_vector(0 to uc_ifar*threads-1); + xu_iu_flush_2ucode :out std_ulogic_vector(0 to threads-1); + xu_iu_flush_2ucode_type :out std_ulogic_vector(0 to threads-1); + xu_iu_ucode_restart :out std_ulogic_vector(0 to threads-1); + xu_iu_ex5_ppc_cpl :out std_ulogic_vector(0 to threads-1); + + xu_n_is2_flush :out std_ulogic_vector(0 to threads-1); + xu_n_rf0_flush :out std_ulogic_vector(0 to threads-1); + xu_n_rf1_flush :out std_ulogic_vector(0 to threads-1); + xu_n_ex1_flush :out std_ulogic_vector(0 to threads-1); + xu_n_ex2_flush :out std_ulogic_vector(0 to threads-1); + xu_n_ex3_flush :out std_ulogic_vector(0 to threads-1); + xu_n_ex4_flush :out std_ulogic_vector(0 to threads-1); + xu_n_ex5_flush :out std_ulogic_vector(0 to threads-1); + + xu_s_rf1_flush :out std_ulogic_vector(0 to threads-1); + xu_s_ex1_flush :out std_ulogic_vector(0 to threads-1); + xu_s_ex2_flush :out std_ulogic_vector(0 to threads-1); + xu_s_ex3_flush :out std_ulogic_vector(0 to threads-1); + xu_s_ex4_flush :out std_ulogic_vector(0 to threads-1); + xu_s_ex5_flush :out std_ulogic_vector(0 to threads-1); + + xu_w_rf1_flush :out std_ulogic_vector(0 to threads-1); + xu_w_ex1_flush :out std_ulogic_vector(0 to threads-1); + xu_w_ex2_flush :out std_ulogic_vector(0 to threads-1); + xu_w_ex3_flush :out std_ulogic_vector(0 to threads-1); + xu_w_ex4_flush :out std_ulogic_vector(0 to threads-1); + xu_w_ex5_flush :out std_ulogic_vector(0 to threads-1); + + xu_lsu_ex4_flush_local :out std_ulogic_vector(0 to threads-1); + xu_mm_ex4_flush :out std_ulogic_vector(0 to threads-1); + xu_mm_ex5_flush :out std_ulogic_vector(0 to threads-1); + xu_mm_ierat_flush :out std_ulogic_vector(0 to threads-1); + xu_mm_ierat_miss :out std_ulogic_vector(0 to threads-1); + xu_mm_ex5_perf_itlb :out std_ulogic_vector(0 to threads-1); + xu_mm_ex5_perf_dtlb :out std_ulogic_vector(0 to threads-1); + + spr_xucr4_div_barr_thres :out std_ulogic_vector(0 to 7); + + iu_xu_ierat_ex2_flush_req :in std_ulogic_vector(0 to threads-1); + iu_xu_ierat_ex3_par_err :in std_ulogic_vector(0 to threads-1); + iu_xu_ierat_ex4_par_err :in std_ulogic_vector(0 to threads-1); + + fu_xu_ex3_regfile_err_det :in std_ulogic_vector(0 to threads-1); + xu_fu_regfile_seq_beg :out std_ulogic; + fu_xu_regfile_seq_end :in std_ulogic; + gpr_cpl_ex3_regfile_err_det :in std_ulogic; + cpl_gpr_regfile_seq_beg :out std_ulogic; + gpr_cpl_regfile_seq_end :in std_ulogic; + xu_pc_err_mcsr_summary :out std_ulogic_vector(0 to threads-1); + xu_pc_err_ditc_overrun :out std_ulogic; + xu_pc_err_local_snoop_reject :out std_ulogic; + xu_pc_err_tlb_lru_parity :out std_ulogic; + xu_pc_err_ext_mchk :out std_ulogic; + xu_pc_err_ierat_multihit :out std_ulogic; + xu_pc_err_derat_multihit :out std_ulogic; + xu_pc_err_tlb_multihit :out std_ulogic; + xu_pc_err_ierat_parity :out std_ulogic; + xu_pc_err_derat_parity :out std_ulogic; + xu_pc_err_tlb_parity :out std_ulogic; + xu_pc_err_mchk_disabled :out std_ulogic; + + xu_iu_rf1_val :out std_ulogic_vector(0 to threads-1); + xu_rf1_val :out std_ulogic_vector(0 to threads-1); + xu_rf1_is_tlbre :out std_ulogic; + xu_rf1_is_tlbwe :out std_ulogic; + xu_rf1_is_tlbsx :out std_ulogic; + xu_rf1_is_tlbsrx :out std_ulogic; + xu_rf1_is_tlbilx :out std_ulogic; + xu_rf1_is_tlbivax :out std_ulogic; + xu_rf1_is_eratre :out std_ulogic; + xu_rf1_is_eratwe :out std_ulogic; + xu_rf1_is_eratsx :out std_ulogic; + xu_rf1_is_eratilx :out std_ulogic; + xu_rf1_is_erativax :out std_ulogic; + xu_ex1_is_isync :out std_ulogic; + xu_ex1_is_csync :out std_ulogic; + xu_rf1_ws :out std_ulogic_vector(0 to 1); + xu_rf1_t :out std_ulogic_vector(0 to 2); + xu_ex1_rs_is :out std_ulogic_vector(0 to 8); + xu_ex1_ra_entry :out std_ulogic_vector(8 to 11); + xu_ex4_rs_data :out std_ulogic_vector(64-(2**regmode) to 63); + + xu_lsu_rf1_data_act :out std_ulogic; + xu_lsu_rf1_axu_ldst_falign :out std_ulogic; + xu_lsu_ex1_store_data :out std_ulogic_vector(64-(2**regmode) to 63); + xu_lsu_ex1_rotsel_ovrd :out std_ulogic_vector(0 to 4); + xu_lsu_ex1_eff_addr :out std_ulogic_vector(64-(dc_size-3) to 63); + + cpl_fxa_ex5_set_barr :out std_ulogic_vector(0 to threads-1); + cpl_iu_set_barr_tid :out std_ulogic_vector(0 to threads-1); + + lsu_xu_ex6_datc_par_err :in std_ulogic; + + lsu_xu_ex2_dvc1_st_cmp :in std_ulogic_vector(8-(2**regmode)/8 to 7); + lsu_xu_ex2_dvc2_st_cmp :in std_ulogic_vector(8-(2**regmode)/8 to 7); + lsu_xu_ex8_dvc1_ld_cmp :in std_ulogic_vector(8-(2**regmode)/8 to 7); + lsu_xu_ex8_dvc2_ld_cmp :in std_ulogic_vector(8-(2**regmode)/8 to 7); + lsu_xu_rel_dvc1_en :in std_ulogic; + lsu_xu_rel_dvc2_en :in std_ulogic; + lsu_xu_rel_dvc_thrd_id :in std_ulogic_vector(0 to 3); + lsu_xu_rel_dvc1_cmp :in std_ulogic_vector(8-(2**regmode)/8 to 7); + lsu_xu_rel_dvc2_cmp :in std_ulogic_vector(8-(2**regmode)/8 to 7); + + lsu_xu_rot_ex6_data_b :in std_ulogic_vector(64-(2**regmode) to 63); + lsu_xu_rot_rel_data :in std_ulogic_vector(64-(2**regmode) to 63); + pc_xu_trace_bus_enable :in std_ulogic; + pc_xu_instr_trace_mode :in std_ulogic; + pc_xu_instr_trace_tid :in std_ulogic_vector(0 to 1); + iu_xu_ex4_tlb_data :in std_ulogic_vector(64-(2**regmode) to 63); + + pc_xu_inj_dcachedir_parity :in std_ulogic; + pc_xu_inj_dcachedir_multihit :in std_ulogic; + + ex4_256st_data :in std_ulogic_vector(0 to 255); + + an_ac_flh2l2_gate :in std_ulogic; + + xu_lsu_rf0_derat_val :in std_ulogic_vector(0 to 3); + xu_lsu_rf0_derat_is_extload :in std_ulogic; + xu_lsu_rf0_derat_is_extstore :in std_ulogic; + xu_lsu_hid_mmu_mode :in std_ulogic; + ex6_ld_par_err :in std_ulogic; + + xu_mm_derat_req :out std_ulogic; + xu_mm_derat_thdid :out std_ulogic_vector(0 to 3); + xu_mm_derat_state :out std_ulogic_vector(0 to 3); + xu_mm_derat_tid :out std_ulogic_vector(0 to 13); + xu_mm_derat_lpid :out std_ulogic_vector(0 to 7); + xu_mm_derat_ttype :out std_ulogic_vector(0 to 1); + mm_xu_derat_rel_val :in std_ulogic_vector(0 to 4); + mm_xu_derat_rel_data :in std_ulogic_vector(0 to 131); + mm_xu_derat_pid0 :in std_ulogic_vector(0 to 13); + mm_xu_derat_pid1 :in std_ulogic_vector(0 to 13); + mm_xu_derat_pid2 :in std_ulogic_vector(0 to 13); + mm_xu_derat_pid3 :in std_ulogic_vector(0 to 13); + mm_xu_derat_mmucr0_0 :in std_ulogic_vector(0 to 19); + mm_xu_derat_mmucr0_1 :in std_ulogic_vector(0 to 19); + mm_xu_derat_mmucr0_2 :in std_ulogic_vector(0 to 19); + mm_xu_derat_mmucr0_3 :in std_ulogic_vector(0 to 19); + xu_mm_derat_mmucr0 :out std_ulogic_vector(0 to 17); + xu_mm_derat_mmucr0_we :out std_ulogic_vector(0 to 3); + mm_xu_derat_mmucr1 :in std_ulogic_vector(0 to 9); + xu_mm_derat_mmucr1 :out std_ulogic_vector(0 to 4); + xu_mm_derat_mmucr1_we :out std_ulogic; + mm_xu_derat_snoop_coming :in std_ulogic; + mm_xu_derat_snoop_val :in std_ulogic; + mm_xu_derat_snoop_attr :in std_ulogic_vector(0 to 25); + mm_xu_derat_snoop_vpn :in std_ulogic_vector(64-(2**REGMODE) to 51); + xu_mm_derat_snoop_ack :out std_ulogic; + + ex1_optype1 :out std_ulogic; + ex1_optype2 :out std_ulogic; + ex1_optype4 :out std_ulogic; + ex1_optype8 :out std_ulogic; + ex1_optype16 :out std_ulogic; + ex1_optype32 :out std_ulogic; + ex1_saxu_instr :out std_ulogic; + ex1_sdp_instr :out std_ulogic; + ex1_stgpr_instr :out std_ulogic; + ex1_store_instr :out std_ulogic; + ex1_axu_op_val :out std_ulogic; + + ex3_algebraic :out std_ulogic; + ex3_data_swap :out std_ulogic; + ex3_thrd_id :out std_ulogic_vector(0 to 3); + xu_fu_ex3_eff_addr :out std_ulogic_vector(59 to 63); + xu_lsu_ici :out std_ulogic; + + rel_upd_dcarr_val :out std_ulogic; + + xu_fu_ex5_reload_val :out std_ulogic; + xu_fu_ex5_load_val :out std_ulogic_vector(0 to 3); + xu_fu_ex5_load_tag :out std_ulogic_vector(0 to 8); + + dcarr_up_way_addr :out std_ulogic_vector(0 to 2); + + ex4_load_op_hit :out std_ulogic; + ex4_store_hit :out std_ulogic; + ex4_axu_op_val :out std_ulogic; + spr_dvc1_act :out std_ulogic; + spr_dvc2_act :out std_ulogic; + spr_dvc1_dbg :out std_ulogic_vector(64-(2**regmode) to 63); + spr_dvc2_dbg :out std_ulogic_vector(64-(2**regmode) to 63); + + an_ac_req_ld_pop :in std_ulogic; + an_ac_req_st_pop :in std_ulogic; + an_ac_req_st_gather :in std_ulogic; + an_ac_req_st_pop_thrd :in std_ulogic_vector(0 to 2); + + an_ac_reld_data_vld :in std_ulogic; + an_ac_reld_core_tag :in std_ulogic_vector(0 to 4); + an_ac_reld_qw :in std_ulogic_vector(57 to 59); + an_ac_reld_data :in std_ulogic_vector(0 to 127); + an_ac_reld_data_coming :in std_ulogic; + an_ac_reld_ditc :in std_ulogic; + an_ac_reld_crit_qw :in std_ulogic; + an_ac_reld_l1_dump :in std_ulogic; + + an_ac_reld_ecc_err :in std_ulogic; + an_ac_reld_ecc_err_ue :in std_ulogic; + + an_ac_back_inv :in std_ulogic; + an_ac_back_inv_addr :in std_ulogic_vector(64-real_data_add to 63); + an_ac_back_inv_target_bit1 :in std_ulogic; + an_ac_back_inv_target_bit3 :in std_ulogic; + an_ac_back_inv_target_bit4 :in std_ulogic; + an_ac_req_spare_ctrl_a1 :in std_ulogic_vector(0 to 3); + + + lsu_reld_data_vld :out std_ulogic; + lsu_reld_core_tag :out std_ulogic_vector(3 to 4); + lsu_reld_qw :out std_ulogic_vector(58 to 59); + lsu_reld_ditc :out std_ulogic; + lsu_reld_ecc_err :out std_ulogic; + lsu_reld_data :out std_ulogic_vector(0 to 127); + + lsu_req_st_pop :out std_ulogic; + lsu_req_st_pop_thrd :out std_ulogic_vector(0 to 2); + + ac_an_reld_ditc_pop_int : in std_ulogic_vector(0 to 3); + ac_an_reld_ditc_pop_q : out std_ulogic_vector(0 to 3); + bx_ib_empty_int : in std_ulogic_vector(0 to 3); + bx_ib_empty_q : out std_ulogic_vector(0 to 3); + + iu_xu_ra :in std_ulogic_vector(64-real_data_add to 59); + iu_xu_request :in std_ulogic; + iu_xu_wimge :in std_ulogic_vector(0 to 4); + iu_xu_thread :in std_ulogic_vector(0 to 3); + iu_xu_userdef :in std_ulogic_vector(0 to 3); + + mm_xu_lsu_req :in std_ulogic_vector(0 to 3); + mm_xu_lsu_ttype :in std_ulogic_vector(0 to 1); + mm_xu_lsu_wimge :in std_ulogic_vector(0 to 4); + mm_xu_lsu_u :in std_ulogic_vector(0 to 3); + mm_xu_lsu_addr :in std_ulogic_vector(64-real_data_add to 63); + mm_xu_lsu_lpid :in std_ulogic_vector(0 to 7); + mm_xu_lsu_lpidr :in std_ulogic_vector(0 to 7); + mm_xu_lsu_gs :in std_ulogic; + mm_xu_lsu_ind :in std_ulogic; + mm_xu_lsu_lbit :in std_ulogic; + xu_mm_lsu_token :out std_ulogic; + + bx_lsu_ob_pwr_tok :in std_ulogic; + bx_lsu_ob_req_val :in std_ulogic; + bx_lsu_ob_ditc_val :in std_ulogic; + bx_lsu_ob_thrd :in std_ulogic_vector(0 to 1); + bx_lsu_ob_qw :in std_ulogic_vector(58 to 59); + bx_lsu_ob_dest :in std_ulogic_vector(0 to 14); + bx_lsu_ob_data :in std_ulogic_vector(0 to 127); + bx_lsu_ob_addr :in std_ulogic_vector(64-real_data_add to 57); + lsu_bx_cmd_avail :out std_ulogic; + lsu_bx_cmd_sent :out std_ulogic; + lsu_bx_cmd_stall :out std_ulogic; + + lsu_xu_ldq_barr_done :out std_ulogic_vector(0 to 3); + lsu_xu_barr_done :out std_ulogic_vector(0 to 3); + + ldq_rel_data_val_early :out std_ulogic; + ldq_rel_op_size :out std_ulogic_vector(0 to 5); + ldq_rel_addr :out std_ulogic_vector(64-(dc_size-3) to 58); + ldq_rel_data_val :out std_ulogic; + ldq_rel_rot_sel :out std_ulogic_vector(0 to 4); + ldq_rel_axu_val :out std_ulogic; + ldq_rel_ci :out std_ulogic; + ldq_rel_thrd_id :out std_ulogic_vector(0 to 3); + ldq_rel_le_mode :out std_ulogic; + ldq_rel_algebraic :out std_ulogic; + ldq_rel_256_data :out std_ulogic_vector(0 to 255); + + ldq_rel_dvc1_en :out std_ulogic; + ldq_rel_dvc2_en :out std_ulogic; + ldq_rel_beat_crit_qw :out std_ulogic; + ldq_rel_beat_crit_qw_block :out std_ulogic; + lsu_xu_rel_wren :out std_ulogic; + lsu_xu_rel_ta_gpr :out std_ulogic_vector(0 to 7); + + xu_iu_ex4_loadmiss_qentry :out std_ulogic_vector(0 to lmq_entries-1); + xu_iu_ex4_loadmiss_target :out std_ulogic_vector(0 to 8); + xu_iu_ex4_loadmiss_target_type :out std_ulogic_vector(0 to 1); + xu_iu_ex4_loadmiss_tid :out std_ulogic_vector(0 to 3); + xu_iu_ex5_loadmiss_qentry :out std_ulogic_vector(0 to lmq_entries-1); + xu_iu_ex5_loadmiss_target :out std_ulogic_vector(0 to 8); + xu_iu_ex5_loadmiss_target_type :out std_ulogic_vector(0 to 1); + xu_iu_ex5_loadmiss_tid :out std_ulogic_vector(0 to 3); + xu_iu_complete_qentry :out std_ulogic_vector(0 to lmq_entries-1); + xu_iu_complete_tid :out std_ulogic_vector(0 to 3); + xu_iu_complete_target_type :out std_ulogic_vector(0 to 1); + + xu_iu_ex6_icbi_val :out std_ulogic_vector(0 to 3); + xu_iu_ex6_icbi_addr :out std_ulogic_vector(64-real_data_add to 57); + + xu_iu_larx_done_tid :out std_ulogic_vector(0 to 3); + xu_mm_lmq_stq_empty :out std_ulogic; + xu_ex1_rb :out std_ulogic_vector(64-(2**regmode) to 51); + xu_ex2_eff_addr :out std_ulogic_vector(64-(2**regmode) to 63); + + ac_an_req_pwr_token :out std_ulogic; + ac_an_req :out std_ulogic; + ac_an_req_ra :out std_ulogic_vector(64-real_data_add to 63); + ac_an_req_ttype :out std_ulogic_vector(0 to 5); + ac_an_req_thread :out std_ulogic_vector(0 to 2); + ac_an_req_wimg_w :out std_ulogic; + ac_an_req_wimg_i :out std_ulogic; + ac_an_req_wimg_m :out std_ulogic; + ac_an_req_wimg_g :out std_ulogic; + ac_an_req_endian :out std_ulogic; + ac_an_req_user_defined :out std_ulogic_vector(0 to 3); + ac_an_req_spare_ctrl_a0 :out std_ulogic_vector(0 to 3); + ac_an_req_ld_core_tag :out std_ulogic_vector(0 to 4); + ac_an_req_ld_xfr_len :out std_ulogic_vector(0 to 2); + ac_an_st_byte_enbl :out std_ulogic_vector(0 to 15+(st_data_32B_mode*16)); + ac_an_st_data :out std_ulogic_vector(0 to 127+(st_data_32B_mode*128)); + ac_an_st_data_pwr_token :out std_ulogic; + + xu_pc_err_dcachedir_parity :out std_ulogic; + xu_pc_err_dcachedir_multihit :out std_ulogic; + xu_pc_err_l2intrf_ecc :out std_ulogic; + xu_pc_err_l2intrf_ue :out std_ulogic; + xu_pc_err_invld_reld :out std_ulogic; + xu_pc_err_l2credit_overrun :out std_ulogic; + + pc_xu_event_bus_enable :in std_ulogic; + pc_xu_lsu_event_mux_ctrls :in std_ulogic_vector(0 to 47); + pc_xu_cache_par_err_event :in std_ulogic; + xu_pc_lsu_event_data :out std_ulogic_vector(0 to 7); + fxa_perf_muldiv_in_use :in std_ulogic; + + dec_spr_rf0_tid :in std_ulogic_vector(0 to threads-1); + dec_spr_rf0_instr :in std_ulogic_vector(0 to 31); + + ac_an_dcr_act :out std_ulogic; + ac_an_dcr_val :out std_ulogic; + ac_an_dcr_read :out std_ulogic; + ac_an_dcr_user :out std_ulogic; + ac_an_dcr_etid :out std_ulogic_vector(0 to 1); + ac_an_dcr_addr :out std_ulogic_vector(11 to 20); + ac_an_dcr_data :out std_ulogic_vector(64-regsize to 63); + + xu_pc_running :out std_ulogic_vector(0 to threads-1); + xu_iu_run_thread :out std_ulogic_vector(0 to threads-1); + xu_iu_single_instr_mode :out std_ulogic_vector(0 to threads-1); + xu_iu_raise_iss_pri :out std_ulogic_vector(0 to threads-1); + xu_pc_spr_ccr0_we :out std_ulogic_vector(0 to threads-1); + + iu_xu_quiesce :in std_ulogic_vector(0 to threads-1); + mm_xu_quiesce :in std_ulogic_vector(0 to threads-1); + bx_xu_quiesce :in std_ulogic_vector(0 to threads-1); + + pc_xu_extirpts_dis_on_stop :in std_ulogic; + pc_xu_timebase_dis_on_stop :in std_ulogic; + pc_xu_decrem_dis_on_stop :in std_ulogic; + + pc_xu_msrovride_pr :in std_ulogic; + + xu_pc_err_llbust_attempt :out std_ulogic_vector(0 to threads-1); + xu_pc_err_llbust_failed :out std_ulogic_vector(0 to threads-1); + + pc_xu_reset_wd_complete :in std_ulogic; + pc_xu_reset_1_complete :in std_ulogic; + pc_xu_reset_2_complete :in std_ulogic; + pc_xu_reset_3_complete :in std_ulogic; + ac_tc_reset_1_request :out std_ulogic; + ac_tc_reset_2_request :out std_ulogic; + ac_tc_reset_3_request :out std_ulogic; + ac_tc_reset_wd_request :out std_ulogic; + + pc_xu_inj_llbust_attempt :in std_ulogic_vector(0 to threads-1); + pc_xu_inj_llbust_failed :in std_ulogic_vector(0 to threads-1); + pc_xu_inj_wdt_reset :in std_ulogic_vector(0 to threads-1); + xu_pc_err_wdt_reset :out std_ulogic_vector(0 to threads-1); + + pc_xu_inj_sprg_ecc :in std_ulogic_vector(0 to threads-1); + xu_pc_err_sprg_ecc :out std_ulogic_vector(0 to threads-1); + xu_pc_err_sprg_ue :out std_ulogic_vector(0 to threads-1); + + spr_msr_is :out std_ulogic_vector(0 to threads-1); + spr_msr_gs :out std_ulogic_vector(0 to threads-1); + spr_msr_pr :out std_ulogic_vector(0 to threads-1); + spr_msr_ds :out std_ulogic_vector(0 to threads-1); + spr_msr_cm :out std_ulogic_vector(0 to threads-1); + spr_msr_fp :out std_ulogic_vector(0 to threads-1); + spr_msr_spv :out std_ulogic_vector(0 to threads-1); + spr_ccr2_ap :out std_ulogic_vector(0 to threads-1); + spr_ccr2_en_dcr :out std_ulogic; + spr_ccr2_notlb :out std_ulogic; + spr_ccr2_en_ditc :out std_ulogic; + xu_lsu_spr_xucr0_dcdis :out std_ulogic; + xu_lsu_spr_xucr0_rel :out std_ulogic; + xu_pc_spr_ccr0_pme :out std_ulogic_vector(0 to 1); + xu_iu_spr_ccr2_ifratsc :out std_ulogic_vector(0 to 8); + xu_iu_spr_ccr2_ifrat :out std_ulogic; + spr_xucr0_clkg_ctl_b0 :out std_ulogic; + xu_mm_spr_epcr_dmiuh :out std_ulogic_vector(0 to threads-1); + xu_mm_spr_epcr_dgtmi :out std_ulogic_vector(0 to threads-1); + cpl_msr_gs :out std_ulogic_vector(0 to threads-1); + cpl_msr_pr :out std_ulogic_vector(0 to threads-1); + cpl_msr_fp :out std_ulogic_vector(0 to threads-1); + cpl_msr_spv :out std_ulogic_vector(0 to threads-1); + cpl_ccr2_ap :out std_ulogic_vector(0 to threads-1); + spr_xucr4_mmu_mchk :out std_ulogic; + + pc_xu_bolt_sl_thold_3 :in std_ulogic; + pc_xu_bo_enable_3 :in std_ulogic; + bolt_sl_thold_2 :out std_ulogic; + bo_enable_2 :out std_ulogic; + pc_xu_bo_unload :in std_ulogic; + pc_xu_bo_repair :in std_ulogic; + pc_xu_bo_reset :in std_ulogic; + pc_xu_bo_shdata :in std_ulogic; + pc_xu_bo_select :in std_ulogic_vector(0 to 4); + xu_pc_bo_fail :out std_ulogic_vector(0 to 4); + xu_pc_bo_diagout :out std_ulogic_vector(0 to 4); + an_ac_coreid :in std_ulogic_vector(54 to 61); + spr_pvr_version_dc :in std_ulogic_vector(8 to 15); + spr_pvr_revision_dc :in std_ulogic_vector(12 to 15); + an_ac_atpg_en_dc :in std_ulogic; + an_ac_ext_interrupt :in std_ulogic_vector(0 to threads-1); + an_ac_crit_interrupt :in std_ulogic_vector(0 to threads-1); + an_ac_perf_interrupt :in std_ulogic_vector(0 to threads-1); + an_ac_reservation_vld :in std_ulogic_vector(0 to threads-1); + an_ac_grffence_en_dc :in std_ulogic; + an_ac_tb_update_pulse :in std_ulogic; + an_ac_tb_update_enable :in std_ulogic; + an_ac_sleep_en :in std_ulogic_vector(0 to threads-1); + an_ac_hang_pulse :in std_ulogic_vector(0 to threads-1); + an_ac_scan_dis_dc_b :in std_ulogic; + an_ac_lbist_en_dc :in std_ulogic; + an_ac_lbist_ary_wrt_thru_dc :in std_ulogic; + ac_tc_machine_check :out std_ulogic_vector(0 to threads-1); + pc_xu_abist_raddr_0 :in std_ulogic_vector(4 to 9); + pc_xu_abist_ena_dc :in std_ulogic; + pc_xu_abist_waddr_0 :in std_ulogic_vector(4 to 9); + pc_xu_abist_di_0 :in std_ulogic_vector(0 to 3); + pc_xu_abist_raw_dc_b :in std_ulogic; + pc_xu_ccflush_dc :in std_ulogic; + pc_xu_abist_g8t_wenb :in std_ulogic; + pc_xu_abist_g8t1p_renb_0 :in std_ulogic; + pc_xu_abist_g8t_bw_1 :in std_ulogic; + pc_xu_abist_g8t_bw_0 :in std_ulogic; + pc_xu_abist_wl32_comp_ena :in std_ulogic; + pc_xu_abist_g8t_dcomp :in std_ulogic_vector(0 to 3); + clkoff_dc_b :out std_ulogic; + d_mode_dc :out std_ulogic; + delay_lclkr_dc :out std_ulogic_vector(0 to 4); + mpw1_dc_b :out std_ulogic_vector(0 to 4); + mpw2_dc_b :out std_ulogic; + g6t_clkoff_dc_b :out std_ulogic; + g6t_d_mode_dc :out std_ulogic; + g6t_delay_lclkr_dc :out std_ulogic_vector(0 to 4); + g6t_mpw1_dc_b :out std_ulogic_vector(0 to 4); + g6t_mpw2_dc_b :out std_ulogic; + pc_xu_sg_3 :in std_ulogic_vector(0 to 4); + pc_xu_func_sl_thold_3 :in std_ulogic_vector(0 to 4); + pc_xu_func_slp_sl_thold_3 :in std_ulogic_vector(0 to 4); + pc_xu_func_nsl_thold_3 :in std_ulogic; + pc_xu_func_slp_nsl_thold_3 :in std_ulogic; + pc_xu_gptr_sl_thold_3 :in std_ulogic; + pc_xu_abst_sl_thold_3 :in std_ulogic; + pc_xu_abst_slp_sl_thold_3 :in std_ulogic; + pc_xu_regf_sl_thold_3 :in std_ulogic; + pc_xu_regf_slp_sl_thold_3 :in std_ulogic; + pc_xu_time_sl_thold_3 :in std_ulogic; + pc_xu_cfg_sl_thold_3 :in std_ulogic; + pc_xu_cfg_slp_sl_thold_3 :in std_ulogic; + pc_xu_ary_nsl_thold_3 :in std_ulogic; + pc_xu_ary_slp_nsl_thold_3 :in std_ulogic; + pc_xu_repr_sl_thold_3 :in std_ulogic; + pc_xu_fce_3 :in std_ulogic_vector(0 to 1); + an_ac_scan_diag_dc :in std_ulogic; + sg_2 :out std_ulogic_vector(0 to 3); + fce_2 :out std_ulogic_vector(0 to 1); + func_sl_thold_2 :out std_ulogic_vector(0 to 3); + func_slp_sl_thold_2 :out std_ulogic_vector(0 to 1); + func_slp_nsl_thold_2 :out std_ulogic; + func_nsl_thold_2 :out std_ulogic; + abst_sl_thold_2 :out std_ulogic; + time_sl_thold_2 :out std_ulogic; + gptr_sl_thold_2 :out std_ulogic; + ary_nsl_thold_2 :out std_ulogic; + repr_sl_thold_2 :out std_ulogic; + cfg_sl_thold_2 :out std_ulogic; + cfg_slp_sl_thold_2 :out std_ulogic; + regf_slp_sl_thold_2 :out std_ulogic; + gptr_scan_in :in std_ulogic; + gptr_scan_out :out std_ulogic; + time_scan_in :in std_ulogic; + time_scan_out :out std_ulogic; + ccfg_scan_in :in std_ulogic; + ccfg_scan_out :out std_ulogic; + regf_scan_in :in std_ulogic_vector(0 to 6); + regf_scan_out :out std_ulogic_vector(0 to 6); + abst_scan_in :in std_ulogic_vector(0 to 1); + abst_scan_out :out std_ulogic_vector(0 to 1); + repr_scan_in :in std_ulogic; + repr_scan_out :out std_ulogic; + func_scan_in :in std_ulogic_vector(35 to 58); + func_scan_out :out std_ulogic_vector(35 to 58); + bcfg_scan_in :in std_ulogic; + bcfg_scan_out :out std_ulogic; + dcfg_scan_in :in std_ulogic; + dcfg_scan_out :out std_ulogic; + + vcs :inout power_logic; + vdd :inout power_logic; + gnd :inout power_logic; + nclk :in clk_logic +); + +-- synopsys translate_off + + +-- synopsys translate_on +end xuq_ctrl_spr; +architecture xuq_ctrl_spr of xuq_ctrl_spr is + +signal bolt_sl_thold_2_b : std_ulogic; +signal bo_enable_2_b : std_ulogic; +signal clkoff_dc_b_b : std_ulogic; +signal d_mode_dc_b : std_ulogic; +signal delay_lclkr_dc_b : std_ulogic_vector(0 to 4); +signal mpw1_dc_b_b : std_ulogic_vector(0 to 4); +signal mpw2_dc_b_b : std_ulogic; +signal sg_2_b : std_ulogic_vector(0 to 3); +signal fce_2_b : std_ulogic_vector(0 to 1); +signal func_sl_thold_2_b : std_ulogic_vector(0 to 3); +signal func_slp_sl_thold_2_b : std_ulogic_vector(0 to 1); +signal func_slp_nsl_thold_2_b : std_ulogic; +signal func_nsl_thold_2_b : std_ulogic; +signal abst_sl_thold_2_b : std_ulogic; +signal time_sl_thold_2_b : std_ulogic; +signal gptr_sl_thold_2_b : std_ulogic; +signal ary_nsl_thold_2_b : std_ulogic; +signal repr_sl_thold_2_b : std_ulogic; +signal cfg_sl_thold_2_b : std_ulogic; +signal cfg_slp_sl_thold_2_b : std_ulogic; + +signal dec_spr_ex4_val :std_ulogic_vector(0 to threads-1); +signal dec_spr_ex1_epid_instr :std_ulogic; +signal mux_spr_ex2_rt :std_ulogic_vector(64-(2**regmode) to 63); +signal fxu_spr_ex1_rs0 :std_ulogic_vector(52 to 63); +signal fxu_spr_ex1_rs1 :std_ulogic_vector(54 to 63); +signal spr_msr_cm_int :std_ulogic_vector(0 to threads-1); +signal spr_dec_spr_xucr0_ssdly :std_ulogic_vector(0 to 4); +signal spr_ccr2_en_attn :std_ulogic; +signal spr_ccr2_en_ditc_int :std_ulogic; +signal spr_ccr2_en_pc :std_ulogic; +signal spr_ccr2_en_icswx :std_ulogic; +signal spr_ccr2_en_dcr_int :std_ulogic; +signal spr_dec_rf1_epcr_dgtmi :std_ulogic_vector(0 to threads-1); +signal spr_byp_ex4_is_mfxer :std_ulogic_vector(0 to threads-1); +signal spr_byp_ex3_spr_rt :std_ulogic_vector(64-(2**regmode) to 63); +signal spr_byp_ex4_is_mtxer :std_ulogic_vector(0 to threads-1); +signal spr_ccr2_notlb_int :std_ulogic; +signal dec_spr_rf1_val :std_ulogic_vector(0 to threads-1); +signal fxu_spr_ex1_rs2 :std_ulogic_vector(42 to 55); +signal spr_perf_tx_events :std_ulogic_vector(0 to 8*threads-1); +signal spr_msr_gs_int :std_ulogic_vector(0 to threads-1); +signal spr_msr_ds_int :std_ulogic_vector(0 to threads-1); +signal spr_msr_pr_int :std_ulogic_vector(0 to threads-1); +signal spr_dbcr0_dac1 :std_ulogic_vector(0 to 2*threads-1); +signal spr_dbcr0_dac2 :std_ulogic_vector(0 to 2*threads-1); +signal spr_dbcr0_dac3 :std_ulogic_vector(0 to 2*threads-1); +signal spr_dbcr0_dac4 :std_ulogic_vector(0 to 2*threads-1); +signal spr_cpl_external_mchk :std_ulogic_vector(0 to threads-1); +signal spr_cpl_ext_interrupt :std_ulogic_vector(0 to threads-1); +signal spr_cpl_dec_interrupt :std_ulogic_vector(0 to threads-1); +signal spr_cpl_udec_interrupt :std_ulogic_vector(0 to threads-1); +signal spr_cpl_perf_interrupt :std_ulogic_vector(0 to threads-1); +signal spr_cpl_fit_interrupt :std_ulogic_vector(0 to threads-1); +signal spr_cpl_crit_interrupt :std_ulogic_vector(0 to threads-1); +signal spr_cpl_wdog_interrupt :std_ulogic_vector(0 to threads-1); +signal spr_cpl_dbell_interrupt :std_ulogic_vector(0 to threads-1); +signal spr_cpl_cdbell_interrupt :std_ulogic_vector(0 to threads-1); +signal spr_cpl_gdbell_interrupt :std_ulogic_vector(0 to threads-1); +signal spr_cpl_gcdbell_interrupt :std_ulogic_vector(0 to threads-1); +signal spr_cpl_gmcdbell_interrupt :std_ulogic_vector(0 to threads-1); +signal cpl_spr_ex5_dbell_taken :std_ulogic_vector(0 to threads-1); +signal cpl_spr_ex5_cdbell_taken :std_ulogic_vector(0 to threads-1); +signal cpl_spr_ex5_gdbell_taken :std_ulogic_vector(0 to threads-1); +signal cpl_spr_ex5_gcdbell_taken :std_ulogic_vector(0 to threads-1); +signal cpl_spr_ex5_gmcdbell_taken :std_ulogic_vector(0 to threads-1); +signal spr_bit_act :std_ulogic; +signal cpl_spr_ex5_act :std_ulogic_vector(0 to threads-1); +signal cpl_spr_ex5_int :std_ulogic_vector(0 to threads-1); +signal cpl_spr_ex5_gint :std_ulogic_vector(0 to threads-1); +signal cpl_spr_ex5_cint :std_ulogic_vector(0 to threads-1); +signal cpl_spr_ex5_mcint :std_ulogic_vector(0 to threads-1); +signal cpl_spr_ex5_nia :std_ulogic_vector(0 to eff_ifar*threads-1); +signal cpl_spr_ex5_esr :std_ulogic_vector(0 to 17*threads-1); +signal cpl_spr_ex5_mcsr :std_ulogic_vector(0 to 15*threads-1); +signal cpl_spr_ex5_dbsr :std_ulogic_vector(0 to 19*threads-1); +signal cpl_spr_ex5_dear_update :std_ulogic_vector(0 to threads-1); +signal cpl_spr_ex5_dear_update_saved :std_ulogic_vector(0 to threads-1); +signal cpl_spr_ex5_dear_save :std_ulogic_vector(0 to threads-1); +signal cpl_spr_ex5_dbsr_update :std_ulogic_vector(0 to threads-1); +signal cpl_spr_ex5_esr_update :std_ulogic_vector(0 to threads-1); +signal cpl_spr_ex5_srr0_dec :std_ulogic_vector(0 to threads-1); +signal cpl_spr_ex5_force_gsrr :std_ulogic_vector(0 to threads-1); +signal cpl_spr_ex5_dbsr_ide :std_ulogic_vector(0 to threads-1); +signal spr_cpl_dbsr_ide :std_ulogic_vector(0 to threads-1); +signal spr_cpl_ex3_ct_le :std_ulogic_vector(0 to threads-1); +signal spr_cpl_ex3_ct_be :std_ulogic_vector(0 to threads-1); +signal spr_cpl_ex3_spr_hypv :std_ulogic; +signal spr_cpl_ex3_spr_illeg :std_ulogic; +signal spr_cpl_ex3_spr_priv :std_ulogic; +signal cpl_spr_stop :std_ulogic_vector(0 to threads-1); +signal cpl_spr_ex5_instr_cpl :std_ulogic_vector(0 to threads-1); +signal cpl_spr_quiesce :std_ulogic_vector(0 to threads-1); +signal spr_cpl_quiesce :std_ulogic_vector(0 to threads-1); +signal spr_cpl_ex2_run_ctl_flush :std_ulogic_vector(0 to threads-1); +signal spr_cpl_fp_precise :std_ulogic_vector(0 to threads-1); +signal spr_cpl_iac1_en :std_ulogic_vector(0 to threads-1); +signal spr_cpl_iac2_en :std_ulogic_vector(0 to threads-1); +signal spr_cpl_iac3_en :std_ulogic_vector(0 to threads-1); +signal spr_cpl_iac4_en :std_ulogic_vector(0 to threads-1); +signal spr_dbcr1_iac12m :std_ulogic_vector(0 to threads-1); +signal spr_dbcr1_iac34m :std_ulogic_vector(0 to threads-1); +signal spr_epcr_duvd :std_ulogic_vector(0 to threads-1); +signal spr_xucr0_mddp :std_ulogic; +signal spr_xucr0_mdcp :std_ulogic; +signal spr_msr_de :std_ulogic_vector(0 to threads-1); +signal spr_msr_spv_int :std_ulogic_vector(0 to threads-1); +signal spr_msr_fp_int :std_ulogic_vector(0 to threads-1); +signal spr_msr_me :std_ulogic_vector(0 to threads-1); +signal spr_msr_ucle :std_ulogic_vector(0 to threads-1); +signal spr_msrp_uclep :std_ulogic_vector(0 to threads-1); +signal spr_ccr2_ucode_dis :std_ulogic; +signal spr_ccr2_ap_int :std_ulogic_vector(0 to 3); +signal cpl_spr_dbcr0_edm :std_ulogic_vector(0 to threads-1); +signal spr_dbcr0_idm :std_ulogic_vector(0 to threads-1); +signal spr_dbcr0_icmp :std_ulogic_vector(0 to threads-1); +signal spr_dbcr0_brt :std_ulogic_vector(0 to threads-1); +signal spr_dbcr0_trap :std_ulogic_vector(0 to threads-1); +signal spr_dbcr0_ret :std_ulogic_vector(0 to threads-1); +signal spr_dbcr0_irpt :std_ulogic_vector(0 to threads-1); +signal spr_epcr_dsigs :std_ulogic_vector(0 to threads-1); +signal spr_epcr_isigs :std_ulogic_vector(0 to threads-1); +signal spr_epcr_extgs :std_ulogic_vector(0 to threads-1); +signal spr_epcr_dtlbgs :std_ulogic_vector(0 to threads-1); +signal spr_epcr_itlbgs :std_ulogic_vector(0 to threads-1); +signal spr_cpl_ex3_sprg_ce :std_ulogic; +signal spr_cpl_ex3_sprg_ue :std_ulogic; +signal xu_lsu_slowspr_val :std_ulogic; +signal xu_lsu_slowspr_rw :std_ulogic; +signal xu_lsu_slowspr_etid :std_ulogic_vector(0 to 1); +signal xu_lsu_slowspr_addr :std_ulogic_vector(0 to 9); +signal xu_lsu_slowspr_data :std_ulogic_vector(64-(2**REGMODE) to 63); +signal xu_lsu_slowspr_done :std_ulogic; +signal lsu_xu_dbell_val :std_ulogic; +signal lsu_xu_dbell_type :std_ulogic_vector(0 to 4); +signal lsu_xu_dbell_brdcast :std_ulogic; +signal lsu_xu_dbell_lpid_match :std_ulogic; +signal lsu_xu_dbell_pirtag :std_ulogic_vector(50 to 63); +signal lsu_xu_quiesce :std_ulogic_vector(0 to threads-1); +signal xu_lsu_mtspr_trace_en :std_ulogic_vector(0 to threads-1); +signal lsu_xu_spr_xucr0_cslc_xuop :std_ulogic; +signal lsu_xu_spr_xucr0_cslc_binv :std_ulogic; +signal lsu_xu_spr_xucr0_clo :std_ulogic; +signal lsu_xu_spr_xucr0_cul :std_ulogic; +signal lsu_xu_spr_epsc_epr :std_ulogic_vector(0 to 3); +signal lsu_xu_spr_epsc_egs :std_ulogic_vector(0 to 3); +signal xu_lsu_spr_xucr0_aflsta :std_ulogic; +signal xu_lsu_spr_xucr0_flsta :std_ulogic; +signal xu_lsu_spr_xucr0_l2siw :std_ulogic; +signal xu_lsu_spr_xucr0_dcdis_int :std_ulogic; +signal xu_lsu_spr_xucr0_wlk :std_ulogic; +signal xu_lsu_spr_xucr0_clfc :std_ulogic; +signal xu_lsu_spr_xucr0_flh2l2 :std_ulogic; +signal xu_lsu_spr_xucr0_cred :std_ulogic; +signal xu_lsu_spr_xucr0_rel_int :std_ulogic; +signal xu_lsu_spr_xucr0_mbar_ack :std_ulogic; +signal xu_lsu_spr_xucr0_tlbsync :std_ulogic; +signal xu_lsu_spr_xucr0_cls :std_ulogic; +signal xu_lsu_spr_ccr2_dfrat :std_ulogic; +signal xu_lsu_spr_ccr2_dfratsc :std_ulogic_vector(0 to 8); +signal ctrl_bcfg_scan_in :std_ulogic; +signal ctrl_ccfg_scan_in :std_ulogic; +signal ctrl_dcfg_scan_in :std_ulogic; +signal ctrl_time_scan_in :std_ulogic; +signal ctrl_repr_scan_in :std_ulogic; +signal ctrl_gptr_scan_in :std_ulogic; +signal ctrl_bcfg_scan_out :std_ulogic; +signal ctrl_ccfg_scan_out :std_ulogic; +signal ctrl_dcfg_scan_out :std_ulogic; +signal ctrl_time_scan_out :std_ulogic; +signal ctrl_repr_scan_out :std_ulogic; +signal ctrl_gptr_scan_out :std_ulogic; +signal spr_bcfg_scan_in :std_ulogic; +signal spr_ccfg_scan_in :std_ulogic; +signal spr_dcfg_scan_in :std_ulogic; +signal spr_time_scan_in :std_ulogic; +signal spr_repr_scan_in :std_ulogic; +signal spr_gptr_scan_in :std_ulogic; +signal spr_bcfg_scan_out :std_ulogic; +signal spr_ccfg_scan_out :std_ulogic; +signal spr_dcfg_scan_out :std_ulogic; +signal spr_time_scan_out :std_ulogic; +signal spr_repr_scan_out :std_ulogic; +signal spr_gptr_scan_out :std_ulogic; +signal xu_s_rf1_flush_int :std_ulogic_vector(0 to threads-1); +signal xu_s_ex1_flush_int :std_ulogic_vector(0 to threads-1); +signal xu_s_ex2_flush_int :std_ulogic_vector(0 to threads-1); +signal xu_s_ex3_flush_int :std_ulogic_vector(0 to threads-1); +signal xu_s_ex4_flush_int :std_ulogic_vector(0 to threads-1); +signal xu_s_ex5_flush_int :std_ulogic_vector(0 to threads-1); +signal spr_ccr0_we :std_ulogic_vector(0 to threads-1); +signal spr_xucr0_clkg_ctl :std_ulogic_vector(0 to 3); +signal spr_debug_data_in :std_ulogic_vector(0 to 87); +signal spr_debug_data_out :std_ulogic_vector(0 to 87); +signal spr_trigger_data_in :std_ulogic_vector(0 to 11); +signal spr_trigger_data_out :std_ulogic_vector(0 to 11); +signal ctrl_debug_data_in :std_ulogic_vector(0 to 87); +signal ctrl_debug_data_out :std_ulogic_vector(0 to 87); +signal ctrl_trigger_data_in :std_ulogic_vector(0 to 11); +signal ctrl_trigger_data_out :std_ulogic_vector(0 to 11); +signal lsu_xu_cmd_debug :std_ulogic_vector(0 to 175); + +begin + +ctrl_trigger_data_in <= trigger_data_in; +ctrl_debug_data_in <= debug_data_in; +spr_debug_data_in <= ctrl_debug_data_out; +spr_trigger_data_in <= ctrl_trigger_data_out; +debug_data_out <= spr_debug_data_out; +trigger_data_out <= spr_trigger_data_out; + +ctrl_bcfg_scan_in <= bcfg_scan_in; +ctrl_ccfg_scan_in <= ccfg_scan_in; +ctrl_dcfg_scan_in <= dcfg_scan_in; +ctrl_time_scan_in <= time_scan_in; +ctrl_repr_scan_in <= repr_scan_in; +ctrl_gptr_scan_in <= gptr_scan_in; + +spr_bcfg_scan_in <= ctrl_bcfg_scan_out; +spr_ccfg_scan_in <= ctrl_ccfg_scan_out; +spr_dcfg_scan_in <= ctrl_dcfg_scan_out; +spr_time_scan_in <= ctrl_time_scan_out; +spr_repr_scan_in <= ctrl_repr_scan_out; +spr_gptr_scan_in <= ctrl_gptr_scan_out; + +bcfg_scan_out <= spr_bcfg_scan_out; +ccfg_scan_out <= spr_ccfg_scan_out; +dcfg_scan_out <= spr_dcfg_scan_out; +time_scan_out <= spr_time_scan_out; +repr_scan_out <= spr_repr_scan_out; +gptr_scan_out <= spr_gptr_scan_out; + + +xu_lsu_slowspr_done <= '0'; + +xu_s_rf1_flush <= xu_s_rf1_flush_int; +xu_s_ex1_flush <= xu_s_ex1_flush_int; +xu_s_ex2_flush <= xu_s_ex2_flush_int; +xu_s_ex3_flush <= xu_s_ex3_flush_int; +xu_s_ex4_flush <= xu_s_ex4_flush_int; +xu_s_ex5_flush <= xu_s_ex5_flush_int; + +xu_mm_spr_epcr_dgtmi <= spr_dec_rf1_epcr_dgtmi; + +xu_pc_spr_ccr0_we <= spr_ccr0_we; + +bolt_sl_thold_2 <= bolt_sl_thold_2_b; +bo_enable_2 <= bo_enable_2_b; +clkoff_dc_b <= clkoff_dc_b_b; +d_mode_dc <= d_mode_dc_b; +delay_lclkr_dc <= delay_lclkr_dc_b; +mpw1_dc_b <= mpw1_dc_b_b; +mpw2_dc_b <= mpw2_dc_b_b; +sg_2 <= sg_2_b; +fce_2 <= fce_2_b; +func_sl_thold_2 <= func_sl_thold_2_b; +func_slp_sl_thold_2 <= func_slp_sl_thold_2_b; +func_slp_nsl_thold_2 <= func_slp_nsl_thold_2_b; +func_nsl_thold_2 <= func_nsl_thold_2_b; +abst_sl_thold_2 <= abst_sl_thold_2_b; +time_sl_thold_2 <= time_sl_thold_2_b; +gptr_sl_thold_2 <= gptr_sl_thold_2_b; +ary_nsl_thold_2 <= ary_nsl_thold_2_b; +repr_sl_thold_2 <= repr_sl_thold_2_b; +cfg_sl_thold_2 <= cfg_sl_thold_2_b; +cfg_slp_sl_thold_2 <= cfg_slp_sl_thold_2_b; + + +ctrl : entity work.xuq_ctrl(xuq_ctrl) +generic map( + expand_type => expand_type, + threads => threads, + eff_ifar => eff_ifar, + uc_ifar => uc_ifar, + regsize => regsize, + hvmode => hvmode, + regmode => regmode, + dc_size => dc_size, + cl_size => cl_size, + real_data_add => real_data_add, + fxu_synth => fxu_synth, + a2mode => a2mode, + lmq_entries => lmq_entries, + l_endian_m => l_endian_m, + load_credits => load_credits, + store_credits => store_credits, + st_data_32B_mode => st_data_32B_mode, + bcfg_epn_0to15 => bcfg_epn_0to15, + bcfg_epn_16to31 => bcfg_epn_16to31, + bcfg_epn_32to47 => bcfg_epn_32to47, + bcfg_epn_48to51 => bcfg_epn_48to51, + bcfg_rpn_22to31 => bcfg_rpn_22to31, + bcfg_rpn_32to47 => bcfg_rpn_32to47, + bcfg_rpn_48to51 => bcfg_rpn_48to51) +port map( + + an_ac_grffence_en_dc => an_ac_grffence_en_dc, + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b, + an_ac_lbist_en_dc => an_ac_lbist_en_dc, + pc_xu_abist_raddr_0 => pc_xu_abist_raddr_0(5 to 9), + pc_xu_abist_ena_dc => pc_xu_abist_ena_dc, + pc_xu_abist_waddr_0 => pc_xu_abist_waddr_0(5 to 9), + pc_xu_abist_di_0 => pc_xu_abist_di_0, + pc_xu_abist_raw_dc_b => pc_xu_abist_raw_dc_b, + pc_xu_ccflush_dc => pc_xu_ccflush_dc, + clkoff_dc_b => clkoff_dc_b_b, + d_mode_dc => d_mode_dc_b, + delay_lclkr_dc => delay_lclkr_dc_b, + mpw1_dc_b => mpw1_dc_b_b, + mpw2_dc_b => mpw2_dc_b_b, + g6t_clkoff_dc_b => g6t_clkoff_dc_b, + g6t_d_mode_dc => g6t_d_mode_dc, + g6t_delay_lclkr_dc => g6t_delay_lclkr_dc, + g6t_mpw1_dc_b => g6t_mpw1_dc_b, + g6t_mpw2_dc_b => g6t_mpw2_dc_b, + pc_xu_sg_3 => pc_xu_sg_3, + pc_xu_func_sl_thold_3 => pc_xu_func_sl_thold_3, + pc_xu_func_slp_sl_thold_3 => pc_xu_func_slp_sl_thold_3, + pc_xu_func_nsl_thold_3 => pc_xu_func_nsl_thold_3, + pc_xu_func_slp_nsl_thold_3 => pc_xu_func_slp_nsl_thold_3, + pc_xu_gptr_sl_thold_3 => pc_xu_gptr_sl_thold_3, + pc_xu_abst_sl_thold_3 => pc_xu_abst_sl_thold_3, + pc_xu_abst_slp_sl_thold_3 => pc_xu_abst_slp_sl_thold_3, + pc_xu_regf_sl_thold_3 => pc_xu_regf_sl_thold_3, + pc_xu_regf_slp_sl_thold_3 => pc_xu_regf_slp_sl_thold_3, + pc_xu_time_sl_thold_3 => pc_xu_time_sl_thold_3, + pc_xu_cfg_sl_thold_3 => pc_xu_cfg_sl_thold_3, + pc_xu_cfg_slp_sl_thold_3 => pc_xu_cfg_slp_sl_thold_3, + pc_xu_ary_nsl_thold_3 => pc_xu_ary_nsl_thold_3, + pc_xu_ary_slp_nsl_thold_3 => pc_xu_ary_slp_nsl_thold_3, + pc_xu_repr_sl_thold_3 => pc_xu_repr_sl_thold_3, + pc_xu_fce_3 => pc_xu_fce_3, + an_ac_scan_diag_dc => an_ac_scan_diag_dc, + sg_2 => sg_2_b, + fce_2 => fce_2_b, + func_sl_thold_2 => func_sl_thold_2_b, + func_slp_sl_thold_2 => func_slp_sl_thold_2_b, + func_slp_nsl_thold_2 => func_slp_nsl_thold_2_b, + func_nsl_thold_2 => func_nsl_thold_2_b, + abst_sl_thold_2 => abst_sl_thold_2_b, + time_sl_thold_2 => time_sl_thold_2_b, + gptr_sl_thold_2 => gptr_sl_thold_2_b, + ary_nsl_thold_2 => ary_nsl_thold_2_b, + repr_sl_thold_2 => repr_sl_thold_2_b, + bolt_sl_thold_2 => bolt_sl_thold_2_b, + bo_enable_2 => bo_enable_2_b, + cfg_sl_thold_2 => cfg_sl_thold_2_b, + cfg_slp_sl_thold_2 => cfg_slp_sl_thold_2_b, + regf_slp_sl_thold_2 => regf_slp_sl_thold_2, + pc_xu_bolt_sl_thold_3 => pc_xu_bolt_sl_thold_3, + pc_xu_bo_enable_3 => pc_xu_bo_enable_3, + + fxa_fxb_rf0_val => fxa_fxb_rf0_val, + fxa_fxb_rf0_issued => fxa_fxb_rf0_issued, + fxa_fxb_rf0_ucode_val => fxa_fxb_rf0_ucode_val, + fxa_fxb_rf0_act => fxa_fxb_rf0_act, + fxa_fxb_ex1_hold_ctr_flush => fxa_fxb_ex1_hold_ctr_flush, + fxa_fxb_rf0_instr => fxa_fxb_rf0_instr, + fxa_fxb_rf0_tid => fxa_fxb_rf0_tid, + fxa_fxb_rf0_ta_vld => fxa_fxb_rf0_ta_vld, + fxa_fxb_rf0_ta => fxa_fxb_rf0_ta, + fxa_fxb_rf0_error => fxa_fxb_rf0_error, + fxa_fxb_rf0_match => fxa_fxb_rf0_match, + fxa_fxb_rf0_is_ucode => fxa_fxb_rf0_is_ucode, + fxa_fxb_rf0_gshare => fxa_fxb_rf0_gshare, + fxa_fxb_rf0_ifar => fxa_fxb_rf0_ifar, + fxa_fxb_rf0_s1_vld => fxa_fxb_rf0_s1_vld, + fxa_fxb_rf0_s1 => fxa_fxb_rf0_s1, + fxa_fxb_rf0_s2_vld => fxa_fxb_rf0_s2_vld, + fxa_fxb_rf0_s2 => fxa_fxb_rf0_s2, + fxa_fxb_rf0_s3_vld => fxa_fxb_rf0_s3_vld, + fxa_fxb_rf0_s3 => fxa_fxb_rf0_s3, + fxa_fxb_rf0_axu_instr_type => fxa_fxb_rf0_axu_instr_type, + fxa_fxb_rf0_axu_ld_or_st => fxa_fxb_rf0_axu_ld_or_st, + fxa_fxb_rf0_axu_store => fxa_fxb_rf0_axu_store, + fxa_fxb_rf0_axu_ldst_forcealign => fxa_fxb_rf0_axu_ldst_forcealign, + fxa_fxb_rf0_axu_ldst_forceexcept => fxa_fxb_rf0_axu_ldst_forceexcept, + fxa_fxb_rf0_axu_ldst_indexed => fxa_fxb_rf0_axu_ldst_indexed, + fxa_fxb_rf0_axu_ldst_tag => fxa_fxb_rf0_axu_ldst_tag, + fxa_fxb_rf0_axu_mftgpr => fxa_fxb_rf0_axu_mftgpr, + fxa_fxb_rf0_axu_mffgpr => fxa_fxb_rf0_axu_mffgpr, + fxa_fxb_rf0_axu_movedp => fxa_fxb_rf0_axu_movedp, + fxa_fxb_rf0_axu_ldst_size => fxa_fxb_rf0_axu_ldst_size, + fxa_fxb_rf0_axu_ldst_update => fxa_fxb_rf0_axu_ldst_update, + fxa_fxb_rf0_pred_update => fxa_fxb_rf0_pred_update, + fxa_fxb_rf0_pred_taken_cnt => fxa_fxb_rf0_pred_taken_cnt, + fxa_fxb_rf0_mc_dep_chk_val => fxa_fxb_rf0_mc_dep_chk_val, + fxa_fxb_rf1_mul_val => fxa_fxb_rf1_mul_val, + fxa_fxb_rf1_div_val => fxa_fxb_rf1_div_val, + fxa_fxb_rf1_div_ctr => fxa_fxb_rf1_div_ctr, + fxa_fxb_rf0_xu_epid_instr => fxa_fxb_rf0_xu_epid_instr, + fxa_fxb_rf0_axu_is_extload => fxa_fxb_rf0_axu_is_extload, + fxa_fxb_rf0_axu_is_extstore => fxa_fxb_rf0_axu_is_extstore, + fxa_fxb_rf0_is_mfocrf => fxa_fxb_rf0_is_mfocrf, + fxa_fxb_rf0_3src_instr => fxa_fxb_rf0_3src_instr, + fxa_fxb_rf0_gpr0_zero => fxa_fxb_rf0_gpr0_zero, + fxa_fxb_rf0_use_imm => fxa_fxb_rf0_use_imm, + fxa_fxb_rf1_muldiv_coll => fxa_fxb_rf1_muldiv_coll, + fxa_cpl_ex2_div_coll => fxa_cpl_ex2_div_coll, + fxb_fxa_ex7_we0 => fxb_fxa_ex7_we0, + fxb_fxa_ex7_wa0 => fxb_fxa_ex7_wa0, + fxb_fxa_ex7_wd0 => fxb_fxa_ex7_wd0, + fxa_fxb_rf1_do0 => fxa_fxb_rf1_do0, + fxa_fxb_rf1_do1 => fxa_fxb_rf1_do1, + fxa_fxb_rf1_do2 => fxa_fxb_rf1_do2, + + xu_bx_ex1_mtdp_val => xu_bx_ex1_mtdp_val, + xu_bx_ex1_mfdp_val => xu_bx_ex1_mfdp_val, + xu_bx_ex1_ipc_thrd => xu_bx_ex1_ipc_thrd, + xu_bx_ex2_ipc_ba => xu_bx_ex2_ipc_ba, + xu_bx_ex2_ipc_sz => xu_bx_ex2_ipc_sz, + + xu_mm_derat_epn => xu_mm_derat_epn, + + xu_mm_rf1_is_tlbsxr => xu_mm_rf1_is_tlbsxr, + mm_xu_cr0_eq_valid => mm_xu_cr0_eq_valid, + mm_xu_cr0_eq => mm_xu_cr0_eq, + + fu_xu_ex4_cr_val => fu_xu_ex4_cr_val, + fu_xu_ex4_cr_noflush => fu_xu_ex4_cr_noflush, + fu_xu_ex4_cr0 => fu_xu_ex4_cr0, + fu_xu_ex4_cr0_bf => fu_xu_ex4_cr0_bf, + fu_xu_ex4_cr1 => fu_xu_ex4_cr1, + fu_xu_ex4_cr1_bf => fu_xu_ex4_cr1_bf, + fu_xu_ex4_cr2 => fu_xu_ex4_cr2, + fu_xu_ex4_cr2_bf => fu_xu_ex4_cr2_bf, + fu_xu_ex4_cr3 => fu_xu_ex4_cr3, + fu_xu_ex4_cr3_bf => fu_xu_ex4_cr3_bf, + + pc_xu_ram_mode => pc_xu_ram_mode, + pc_xu_ram_thread => pc_xu_ram_thread, + pc_xu_ram_execute => pc_xu_ram_execute, + pc_xu_ram_flush_thread => pc_xu_ram_flush_thread, + xu_iu_ram_issue => xu_iu_ram_issue, + xu_pc_ram_interrupt => xu_pc_ram_interrupt, + xu_pc_ram_done => xu_pc_ram_done, + xu_pc_ram_data => xu_pc_ram_data, + + xu_iu_ex5_val => xu_iu_ex5_val, + xu_iu_ex5_tid => xu_iu_ex5_tid, + xu_iu_ex5_br_update => xu_iu_ex5_br_update, + xu_iu_ex5_br_hist => xu_iu_ex5_br_hist, + xu_iu_ex5_bclr => xu_iu_ex5_bclr, + xu_iu_ex5_lk => xu_iu_ex5_lk, + xu_iu_ex5_bh => xu_iu_ex5_bh, + xu_iu_ex6_pri => xu_iu_ex6_pri, + xu_iu_ex6_pri_val => xu_iu_ex6_pri_val, + xu_iu_spr_xer => xu_iu_spr_xer, + xu_iu_slowspr_done => xu_iu_slowspr_done, + xu_iu_need_hole => xu_iu_need_hole, + fxb_fxa_ex6_clear_barrier => fxb_fxa_ex6_clear_barrier, + xu_iu_ex5_gshare => xu_iu_ex5_gshare, + xu_iu_ex5_getNIA => xu_iu_ex5_getNIA, + + an_ac_stcx_complete => an_ac_stcx_complete, + an_ac_stcx_pass => an_ac_stcx_pass, + xu_iu_stcx_complete => xu_iu_stcx_complete, + xu_iu_reld_core_tag_clone => xu_iu_reld_core_tag_clone, + xu_iu_reld_data_coming_clone => xu_iu_reld_data_coming_clone, + xu_iu_reld_data_vld_clone => xu_iu_reld_data_vld_clone, + xu_iu_reld_ditc_clone => xu_iu_reld_ditc_clone, + + slowspr_val_in => slowspr_val_in, + slowspr_rw_in => slowspr_rw_in, + slowspr_etid_in => slowspr_etid_in, + slowspr_addr_in => slowspr_addr_in, + slowspr_data_in => slowspr_data_in, + slowspr_done_in => slowspr_done_in, + + an_ac_dcr_act => an_ac_dcr_act, + an_ac_dcr_val => an_ac_dcr_val, + an_ac_dcr_read => an_ac_dcr_read, + an_ac_dcr_etid => an_ac_dcr_etid, + an_ac_dcr_data => an_ac_dcr_data, + an_ac_dcr_done => an_ac_dcr_done, + + lsu_xu_ex4_mtdp_cr_status => lsu_xu_ex4_mtdp_cr_status, + lsu_xu_ex4_mfdp_cr_status => lsu_xu_ex4_mfdp_cr_status, + dec_cpl_ex3_mc_dep_chk_val => dec_cpl_ex3_mc_dep_chk_val, + + dec_spr_ex4_val => dec_spr_ex4_val, + dec_spr_ex1_epid_instr => dec_spr_ex1_epid_instr, + mux_spr_ex2_rt => mux_spr_ex2_rt, + fxu_spr_ex1_rs0 => fxu_spr_ex1_rs0, + fxu_spr_ex1_rs1 => fxu_spr_ex1_rs1, + spr_msr_cm => spr_msr_cm_int, + spr_dec_spr_xucr0_ssdly => spr_dec_spr_xucr0_ssdly, + spr_ccr2_en_attn => spr_ccr2_en_attn, + spr_ccr2_en_ditc => spr_ccr2_en_ditc_int, + spr_ccr2_en_pc => spr_ccr2_en_pc, + spr_ccr2_en_icswx => spr_ccr2_en_icswx, + spr_ccr2_en_dcr => spr_ccr2_en_dcr_int, + spr_dec_rf1_epcr_dgtmi => spr_dec_rf1_epcr_dgtmi, + spr_byp_ex4_is_mfxer => spr_byp_ex4_is_mfxer, + spr_byp_ex3_spr_rt => spr_byp_ex3_spr_rt, + spr_byp_ex4_is_mtxer => spr_byp_ex4_is_mtxer, + spr_ccr2_notlb => spr_ccr2_notlb_int, + dec_spr_rf1_val => dec_spr_rf1_val, + fxu_spr_ex1_rs2 => fxu_spr_ex1_rs2, + + fxa_perf_muldiv_in_use => fxa_perf_muldiv_in_use, + spr_perf_tx_events => spr_perf_tx_events, + xu_pc_event_data => xu_pc_event_data, + + pc_xu_event_count_mode => pc_xu_event_count_mode, + pc_xu_event_mux_ctrls => pc_xu_event_mux_ctrls, + + fxu_debug_mux_ctrls => fxu_debug_mux_ctrls, + cpl_debug_mux_ctrls => cpl_debug_mux_ctrls, + lsu_debug_mux_ctrls => lsu_debug_mux_ctrls, + ctrl_trigger_data_in => ctrl_trigger_data_in, + ctrl_trigger_data_out => ctrl_trigger_data_out, + ctrl_debug_data_in => ctrl_debug_data_in, + ctrl_debug_data_out => ctrl_debug_data_out, + lsu_xu_data_debug0 => lsu_xu_data_debug0, + lsu_xu_data_debug1 => lsu_xu_data_debug1, + lsu_xu_data_debug2 => lsu_xu_data_debug2, + fxa_cpl_debug => fxa_cpl_debug, + + spr_msr_gs => spr_msr_gs_int, + spr_msr_ds => spr_msr_ds_int, + spr_msr_pr => spr_msr_pr_int, + spr_dbcr0_dac1 => spr_dbcr0_dac1, + spr_dbcr0_dac2 => spr_dbcr0_dac2, + spr_dbcr0_dac3 => spr_dbcr0_dac3, + spr_dbcr0_dac4 => spr_dbcr0_dac4, + + ac_tc_debug_trigger => ac_tc_debug_trigger, + + dec_cpl_rf0_act => dec_cpl_rf0_act, + dec_cpl_rf0_tid => dec_cpl_rf0_tid, + + fu_xu_rf1_act => fu_xu_rf1_act, + fu_xu_ex1_ifar => fu_xu_ex1_ifar, + fu_xu_ex2_ifar_val => fu_xu_ex2_ifar_val, + fu_xu_ex2_ifar_issued => fu_xu_ex2_ifar_issued, + fu_xu_ex2_instr_type => fu_xu_ex2_instr_type, + fu_xu_ex2_instr_match => fu_xu_ex2_instr_match, + fu_xu_ex2_is_ucode => fu_xu_ex2_is_ucode, + + pc_xu_stop => pc_xu_stop, + pc_xu_step => pc_xu_step, + pc_xu_dbg_action => pc_xu_dbg_action, + pc_xu_force_ude => pc_xu_force_ude, + xu_pc_step_done => xu_pc_step_done, + pc_xu_init_reset => pc_xu_init_reset, + + spr_cpl_external_mchk => spr_cpl_external_mchk, + spr_cpl_ext_interrupt => spr_cpl_ext_interrupt, + spr_cpl_udec_interrupt => spr_cpl_udec_interrupt, + spr_cpl_perf_interrupt => spr_cpl_perf_interrupt, + spr_cpl_dec_interrupt => spr_cpl_dec_interrupt, + spr_cpl_fit_interrupt => spr_cpl_fit_interrupt, + spr_cpl_crit_interrupt => spr_cpl_crit_interrupt, + spr_cpl_wdog_interrupt => spr_cpl_wdog_interrupt, + spr_cpl_dbell_interrupt => spr_cpl_dbell_interrupt, + spr_cpl_cdbell_interrupt => spr_cpl_cdbell_interrupt, + spr_cpl_gdbell_interrupt => spr_cpl_gdbell_interrupt, + spr_cpl_gcdbell_interrupt => spr_cpl_gcdbell_interrupt, + spr_cpl_gmcdbell_interrupt => spr_cpl_gmcdbell_interrupt, + cpl_spr_ex5_dbell_taken => cpl_spr_ex5_dbell_taken, + cpl_spr_ex5_cdbell_taken => cpl_spr_ex5_cdbell_taken, + cpl_spr_ex5_gdbell_taken => cpl_spr_ex5_gdbell_taken, + cpl_spr_ex5_gcdbell_taken => cpl_spr_ex5_gcdbell_taken, + cpl_spr_ex5_gmcdbell_taken => cpl_spr_ex5_gmcdbell_taken, + + cpl_spr_ex5_act => cpl_spr_ex5_act, + cpl_spr_ex5_int => cpl_spr_ex5_int, + cpl_spr_ex5_gint => cpl_spr_ex5_gint, + cpl_spr_ex5_cint => cpl_spr_ex5_cint, + cpl_spr_ex5_mcint => cpl_spr_ex5_mcint, + cpl_spr_ex5_nia => cpl_spr_ex5_nia, + cpl_spr_ex5_esr => cpl_spr_ex5_esr, + cpl_spr_ex5_mcsr => cpl_spr_ex5_mcsr, + cpl_spr_ex5_dbsr => cpl_spr_ex5_dbsr, + cpl_spr_ex5_dear_save => cpl_spr_ex5_dear_save, + cpl_spr_ex5_dear_update_saved => cpl_spr_ex5_dear_update_saved, + cpl_spr_ex5_dear_update => cpl_spr_ex5_dear_update, + cpl_spr_ex5_dbsr_update => cpl_spr_ex5_dbsr_update, + cpl_spr_ex5_esr_update => cpl_spr_ex5_esr_update, + cpl_spr_ex5_srr0_dec => cpl_spr_ex5_srr0_dec, + cpl_spr_ex5_force_gsrr => cpl_spr_ex5_force_gsrr, + cpl_spr_ex5_dbsr_ide => cpl_spr_ex5_dbsr_ide, + spr_cpl_dbsr_ide => spr_cpl_dbsr_ide, + + mm_xu_local_snoop_reject => mm_xu_local_snoop_reject, + mm_xu_lru_par_err => mm_xu_lru_par_err, + mm_xu_tlb_par_err => mm_xu_tlb_par_err, + mm_xu_tlb_multihit_err => mm_xu_tlb_multihit_err, + + xu_pc_err_attention_instr => xu_pc_err_attention_instr, + xu_pc_err_nia_miscmpr => xu_pc_err_nia_miscmpr, + xu_pc_err_debug_event => xu_pc_err_debug_event, + + spr_cpl_ex3_ct_le => spr_cpl_ex3_ct_le, + spr_cpl_ex3_ct_be => spr_cpl_ex3_ct_be, + + spr_cpl_ex3_spr_illeg => spr_cpl_ex3_spr_illeg, + spr_cpl_ex3_spr_priv => spr_cpl_ex3_spr_priv, + + spr_cpl_ex3_spr_hypv => spr_cpl_ex3_spr_hypv, + + cpl_spr_stop => cpl_spr_stop, + cpl_spr_ex5_instr_cpl => cpl_spr_ex5_instr_cpl, + spr_cpl_quiesce => spr_cpl_quiesce, + cpl_spr_quiesce => cpl_spr_quiesce, + spr_cpl_ex2_run_ctl_flush => spr_cpl_ex2_run_ctl_flush, + xu_pc_stop_dbg_event => xu_pc_stop_dbg_event, + + mm_xu_illeg_instr => mm_xu_illeg_instr, + mm_xu_tlb_miss => mm_xu_tlb_miss, + mm_xu_pt_fault => mm_xu_pt_fault, + mm_xu_tlb_inelig => mm_xu_tlb_inelig, + mm_xu_lrat_miss => mm_xu_lrat_miss, + mm_xu_hv_priv => mm_xu_hv_priv, + mm_xu_esr_pt => mm_xu_esr_pt, + mm_xu_esr_data => mm_xu_esr_data, + mm_xu_esr_epid => mm_xu_esr_epid, + mm_xu_esr_st => mm_xu_esr_st, + mm_xu_hold_req => mm_xu_hold_req, + mm_xu_hold_done => mm_xu_hold_done, + xu_mm_hold_ack => xu_mm_hold_ack, + mm_xu_eratmiss_done => mm_xu_eratmiss_done, + mm_xu_ex3_flush_req => mm_xu_ex3_flush_req, + + fu_xu_ex3_ap_int_req => fu_xu_ex3_ap_int_req, + fu_xu_ex3_trap => fu_xu_ex3_trap, + fu_xu_ex3_n_flush => fu_xu_ex3_n_flush, + fu_xu_ex3_np1_flush => fu_xu_ex3_np1_flush, + fu_xu_ex3_flush2ucode => fu_xu_ex3_flush2ucode, + fu_xu_ex2_async_block => fu_xu_ex2_async_block, + + xu_iu_ex5_br_taken => xu_iu_ex5_br_taken, + xu_iu_ex5_ifar => xu_iu_ex5_ifar, + xu_iu_flush => xu_iu_flush, + xu_iu_iu0_flush_ifar => xu_iu_iu0_flush_ifar, + xu_iu_uc_flush_ifar => xu_iu_uc_flush_ifar, + xu_iu_flush_2ucode => xu_iu_flush_2ucode, + xu_iu_flush_2ucode_type => xu_iu_flush_2ucode_type, + xu_iu_ucode_restart => xu_iu_ucode_restart, + xu_iu_ex5_ppc_cpl => xu_iu_ex5_ppc_cpl, + + xu_n_is2_flush => xu_n_is2_flush, + xu_n_rf0_flush => xu_n_rf0_flush, + xu_n_rf1_flush => xu_n_rf1_flush, + xu_n_ex1_flush => xu_n_ex1_flush, + xu_n_ex2_flush => xu_n_ex2_flush, + xu_n_ex3_flush => xu_n_ex3_flush, + xu_n_ex4_flush => xu_n_ex4_flush, + xu_n_ex5_flush => xu_n_ex5_flush, + xu_s_rf1_flush => xu_s_rf1_flush_int, + xu_s_ex1_flush => xu_s_ex1_flush_int, + xu_s_ex2_flush => xu_s_ex2_flush_int, + xu_s_ex3_flush => xu_s_ex3_flush_int, + xu_s_ex4_flush => xu_s_ex4_flush_int, + xu_s_ex5_flush => xu_s_ex5_flush_int, + xu_w_rf1_flush => xu_w_rf1_flush, + xu_w_ex1_flush => xu_w_ex1_flush, + xu_w_ex2_flush => xu_w_ex2_flush, + xu_w_ex3_flush => xu_w_ex3_flush, + xu_w_ex4_flush => xu_w_ex4_flush, + xu_w_ex5_flush => xu_w_ex5_flush, + xu_lsu_ex4_flush_local => xu_lsu_ex4_flush_local, + xu_mm_ex4_flush => xu_mm_ex4_flush, + xu_mm_ex5_flush => xu_mm_ex5_flush, + xu_mm_ierat_flush => xu_mm_ierat_flush, + xu_mm_ierat_miss => xu_mm_ierat_miss, + xu_mm_ex5_perf_itlb => xu_mm_ex5_perf_itlb, + xu_mm_ex5_perf_dtlb => xu_mm_ex5_perf_dtlb, + + spr_bit_act => spr_bit_act, + spr_cpl_iac1_en => spr_cpl_iac1_en, + spr_cpl_iac2_en => spr_cpl_iac2_en, + spr_cpl_iac3_en => spr_cpl_iac3_en, + spr_cpl_iac4_en => spr_cpl_iac4_en, + spr_dbcr1_iac12m => spr_dbcr1_iac12m, + spr_dbcr1_iac34m => spr_dbcr1_iac34m, + spr_epcr_duvd => spr_epcr_duvd, + spr_cpl_fp_precise => spr_cpl_fp_precise, + spr_xucr0_mddp => spr_xucr0_mddp, + spr_xucr0_mdcp => spr_xucr0_mdcp, + spr_msr_de => spr_msr_de, + spr_msr_spv => spr_msr_spv_int, + spr_msr_fp => spr_msr_fp_int, + spr_msr_me => spr_msr_me, + spr_msr_ucle => spr_msr_ucle, + spr_msrp_uclep => spr_msrp_uclep, + spr_ccr2_ucode_dis => spr_ccr2_ucode_dis, + spr_ccr2_ap => spr_ccr2_ap_int, + spr_dbcr0_idm => spr_dbcr0_idm, + cpl_spr_dbcr0_edm => cpl_spr_dbcr0_edm, + spr_dbcr0_icmp => spr_dbcr0_icmp, + spr_dbcr0_brt => spr_dbcr0_brt, + spr_dbcr0_trap => spr_dbcr0_trap, + spr_dbcr0_ret => spr_dbcr0_ret, + spr_dbcr0_irpt => spr_dbcr0_irpt, + spr_epcr_dsigs => spr_epcr_dsigs, + spr_epcr_isigs => spr_epcr_isigs, + spr_epcr_extgs => spr_epcr_extgs, + spr_epcr_dtlbgs => spr_epcr_dtlbgs, + spr_epcr_itlbgs => spr_epcr_itlbgs, + spr_xucr4_div_barr_thres => spr_xucr4_div_barr_thres, + spr_ccr0_we => spr_ccr0_we, + cpl_msr_gs => cpl_msr_gs, + cpl_msr_pr => cpl_msr_pr, + cpl_msr_fp => cpl_msr_fp, + cpl_msr_spv => cpl_msr_spv, + cpl_ccr2_ap => cpl_ccr2_ap, + spr_xucr0_clkg_ctl => spr_xucr0_clkg_ctl(1 to 3), + spr_xucr4_mmu_mchk => spr_xucr4_mmu_mchk, + + spr_cpl_ex3_sprg_ce => spr_cpl_ex3_sprg_ce, + spr_cpl_ex3_sprg_ue => spr_cpl_ex3_sprg_ue, + iu_xu_ierat_ex2_flush_req => iu_xu_ierat_ex2_flush_req, + iu_xu_ierat_ex3_par_err => iu_xu_ierat_ex3_par_err, + iu_xu_ierat_ex4_par_err => iu_xu_ierat_ex4_par_err, + + fu_xu_ex3_regfile_err_det => fu_xu_ex3_regfile_err_det, + xu_fu_regfile_seq_beg => xu_fu_regfile_seq_beg, + fu_xu_regfile_seq_end => fu_xu_regfile_seq_end, + gpr_cpl_ex3_regfile_err_det => gpr_cpl_ex3_regfile_err_det, + cpl_gpr_regfile_seq_beg => cpl_gpr_regfile_seq_beg, + gpr_cpl_regfile_seq_end => gpr_cpl_regfile_seq_end, + xu_pc_err_mcsr_summary => xu_pc_err_mcsr_summary, + xu_pc_err_ditc_overrun => xu_pc_err_ditc_overrun, + xu_pc_err_local_snoop_reject => xu_pc_err_local_snoop_reject, + xu_pc_err_tlb_lru_parity => xu_pc_err_tlb_lru_parity, + xu_pc_err_ext_mchk => xu_pc_err_ext_mchk, + xu_pc_err_ierat_multihit => xu_pc_err_ierat_multihit, + xu_pc_err_derat_multihit => xu_pc_err_derat_multihit, + xu_pc_err_tlb_multihit => xu_pc_err_tlb_multihit, + xu_pc_err_ierat_parity => xu_pc_err_ierat_parity, + xu_pc_err_derat_parity => xu_pc_err_derat_parity, + xu_pc_err_tlb_parity => xu_pc_err_tlb_parity, + xu_pc_err_mchk_disabled => xu_pc_err_mchk_disabled, + xu_pc_err_sprg_ue => xu_pc_err_sprg_ue, + + xu_iu_rf1_val => xu_iu_rf1_val, + xu_rf1_val => xu_rf1_val, + xu_rf1_is_tlbre => xu_rf1_is_tlbre, + xu_rf1_is_tlbwe => xu_rf1_is_tlbwe, + xu_rf1_is_tlbsx => xu_rf1_is_tlbsx, + xu_rf1_is_tlbsrx => xu_rf1_is_tlbsrx, + xu_rf1_is_tlbilx => xu_rf1_is_tlbilx, + xu_rf1_is_tlbivax => xu_rf1_is_tlbivax, + xu_rf1_is_eratre => xu_rf1_is_eratre, + xu_rf1_is_eratwe => xu_rf1_is_eratwe, + xu_rf1_is_eratsx => xu_rf1_is_eratsx, + xu_rf1_is_eratilx => xu_rf1_is_eratilx, + xu_rf1_is_erativax => xu_rf1_is_erativax, + xu_ex1_is_isync => xu_ex1_is_isync, + xu_ex1_is_csync => xu_ex1_is_csync, + xu_rf1_ws => xu_rf1_ws, + xu_rf1_t => xu_rf1_t, + xu_ex1_rs_is => xu_ex1_rs_is, + xu_ex1_ra_entry => xu_ex1_ra_entry, + xu_ex4_rs_data => xu_ex4_rs_data, + + xu_lsu_rf1_data_act => xu_lsu_rf1_data_act, + xu_lsu_rf1_axu_ldst_falign => xu_lsu_rf1_axu_ldst_falign, + xu_lsu_ex1_store_data => xu_lsu_ex1_store_data, + xu_lsu_ex1_rotsel_ovrd => xu_lsu_ex1_rotsel_ovrd, + xu_lsu_ex1_eff_addr => xu_lsu_ex1_eff_addr, + + cpl_fxa_ex5_set_barr => cpl_fxa_ex5_set_barr, + cpl_iu_set_barr_tid => cpl_iu_set_barr_tid, + + lsu_xu_ex6_datc_par_err => lsu_xu_ex6_datc_par_err, + + lsu_xu_ex2_dvc1_st_cmp => lsu_xu_ex2_dvc1_st_cmp, + lsu_xu_ex2_dvc2_st_cmp => lsu_xu_ex2_dvc2_st_cmp, + lsu_xu_ex8_dvc1_ld_cmp => lsu_xu_ex8_dvc1_ld_cmp, + lsu_xu_ex8_dvc2_ld_cmp => lsu_xu_ex8_dvc2_ld_cmp, + lsu_xu_rel_dvc1_en => lsu_xu_rel_dvc1_en, + lsu_xu_rel_dvc2_en => lsu_xu_rel_dvc2_en, + lsu_xu_rel_dvc_thrd_id => lsu_xu_rel_dvc_thrd_id, + lsu_xu_rel_dvc1_cmp => lsu_xu_rel_dvc1_cmp, + lsu_xu_rel_dvc2_cmp => lsu_xu_rel_dvc2_cmp, + + lsu_xu_rot_ex6_data_b => lsu_xu_rot_ex6_data_b, + lsu_xu_rot_rel_data => lsu_xu_rot_rel_data, + pc_xu_trace_bus_enable => pc_xu_trace_bus_enable, + pc_xu_instr_trace_mode => pc_xu_instr_trace_mode, + pc_xu_instr_trace_tid => pc_xu_instr_trace_tid, + iu_xu_ex4_tlb_data => iu_xu_ex4_tlb_data, + + pc_xu_inj_dcachedir_parity => pc_xu_inj_dcachedir_parity, + pc_xu_inj_dcachedir_multihit => pc_xu_inj_dcachedir_multihit, + + ex4_256st_data => ex4_256st_data, + + xu_lsu_mtspr_trace_en => xu_lsu_mtspr_trace_en, + xu_lsu_spr_xucr0_aflsta => xu_lsu_spr_xucr0_aflsta, + xu_lsu_spr_xucr0_flsta => xu_lsu_spr_xucr0_flsta, + xu_lsu_spr_xucr0_l2siw => xu_lsu_spr_xucr0_l2siw, + xu_lsu_spr_xucr0_dcdis => xu_lsu_spr_xucr0_dcdis_int, + xu_lsu_spr_xucr0_wlk => xu_lsu_spr_xucr0_wlk, + xu_lsu_spr_xucr0_clfc => xu_lsu_spr_xucr0_clfc, + xu_lsu_spr_xucr0_flh2l2 => xu_lsu_spr_xucr0_flh2l2, + xu_lsu_spr_xucr0_cred => xu_lsu_spr_xucr0_cred, + xu_lsu_spr_xucr0_rel => xu_lsu_spr_xucr0_rel_int, + xu_lsu_spr_xucr0_mbar_ack => xu_lsu_spr_xucr0_mbar_ack, + xu_lsu_spr_xucr0_tlbsync => xu_lsu_spr_xucr0_tlbsync, + xu_lsu_spr_xucr0_cls => xu_lsu_spr_xucr0_cls, + xu_lsu_spr_ccr2_dfrat => xu_lsu_spr_ccr2_dfrat, + xu_lsu_spr_ccr2_dfratsc => xu_lsu_spr_ccr2_dfratsc, + + an_ac_flh2l2_gate => an_ac_flh2l2_gate, + + xu_lsu_rf0_derat_val => xu_lsu_rf0_derat_val, + xu_lsu_rf0_derat_is_extload => xu_lsu_rf0_derat_is_extload, + xu_lsu_rf0_derat_is_extstore => xu_lsu_rf0_derat_is_extstore, + + + xu_lsu_hid_mmu_mode => xu_lsu_hid_mmu_mode, + ex6_ld_par_err => ex6_ld_par_err, + + xu_mm_derat_req => xu_mm_derat_req, + xu_mm_derat_thdid => xu_mm_derat_thdid, + xu_mm_derat_state => xu_mm_derat_state, + xu_mm_derat_tid => xu_mm_derat_tid, + xu_mm_derat_lpid => xu_mm_derat_lpid, + xu_mm_derat_ttype => xu_mm_derat_ttype, + mm_xu_derat_rel_val => mm_xu_derat_rel_val, + mm_xu_derat_rel_data => mm_xu_derat_rel_data, + mm_xu_derat_pid0 => mm_xu_derat_pid0, + mm_xu_derat_pid1 => mm_xu_derat_pid1, + mm_xu_derat_pid2 => mm_xu_derat_pid2, + mm_xu_derat_pid3 => mm_xu_derat_pid3, + mm_xu_derat_mmucr0_0 => mm_xu_derat_mmucr0_0, + mm_xu_derat_mmucr0_1 => mm_xu_derat_mmucr0_1, + mm_xu_derat_mmucr0_2 => mm_xu_derat_mmucr0_2, + mm_xu_derat_mmucr0_3 => mm_xu_derat_mmucr0_3, + xu_mm_derat_mmucr0 => xu_mm_derat_mmucr0, + xu_mm_derat_mmucr0_we => xu_mm_derat_mmucr0_we, + mm_xu_derat_mmucr1 => mm_xu_derat_mmucr1, + xu_mm_derat_mmucr1 => xu_mm_derat_mmucr1, + xu_mm_derat_mmucr1_we => xu_mm_derat_mmucr1_we, + mm_xu_derat_snoop_coming => mm_xu_derat_snoop_coming, + mm_xu_derat_snoop_val => mm_xu_derat_snoop_val, + mm_xu_derat_snoop_attr => mm_xu_derat_snoop_attr, + mm_xu_derat_snoop_vpn => mm_xu_derat_snoop_vpn, + xu_mm_derat_snoop_ack => xu_mm_derat_snoop_ack, + + xu_lsu_slowspr_val => xu_lsu_slowspr_val, + xu_lsu_slowspr_rw => xu_lsu_slowspr_rw, + xu_lsu_slowspr_etid => xu_lsu_slowspr_etid, + xu_lsu_slowspr_addr => xu_lsu_slowspr_addr, + xu_lsu_slowspr_data => xu_lsu_slowspr_data, + xu_lsu_slowspr_done => xu_lsu_slowspr_done, + slowspr_val_out => slowspr_val_out, + slowspr_rw_out => slowspr_rw_out, + slowspr_etid_out => slowspr_etid_out, + slowspr_addr_out => slowspr_addr_out, + slowspr_data_out => slowspr_data_out, + slowspr_done_out => slowspr_done_out, + + ex1_optype1 => ex1_optype1, + ex1_optype2 => ex1_optype2, + ex1_optype4 => ex1_optype4, + ex1_optype8 => ex1_optype8, + ex1_optype16 => ex1_optype16, + ex1_optype32 => ex1_optype32, + ex1_saxu_instr => ex1_saxu_instr, + ex1_sdp_instr => ex1_sdp_instr, + ex1_stgpr_instr => ex1_stgpr_instr, + ex1_store_instr => ex1_store_instr, + ex1_axu_op_val => ex1_axu_op_val, + + ex3_algebraic => ex3_algebraic, + ex3_data_swap => ex3_data_swap, + ex3_thrd_id => ex3_thrd_id, + xu_fu_ex3_eff_addr => xu_fu_ex3_eff_addr, + xu_lsu_ici => xu_lsu_ici, + + rel_upd_dcarr_val => rel_upd_dcarr_val, + + xu_fu_ex5_reload_val => xu_fu_ex5_reload_val, + xu_fu_ex5_load_val => xu_fu_ex5_load_val, + xu_fu_ex5_load_tag => xu_fu_ex5_load_tag, + + dcarr_up_way_addr => dcarr_up_way_addr, + + lsu_xu_spr_xucr0_cslc_xuop => lsu_xu_spr_xucr0_cslc_xuop, + lsu_xu_spr_xucr0_cslc_binv => lsu_xu_spr_xucr0_cslc_binv, + lsu_xu_spr_xucr0_clo => lsu_xu_spr_xucr0_clo, + lsu_xu_spr_xucr0_cul => lsu_xu_spr_xucr0_cul, + lsu_xu_spr_epsc_epr => lsu_xu_spr_epsc_epr, + lsu_xu_spr_epsc_egs => lsu_xu_spr_epsc_egs, + + ex4_load_op_hit => ex4_load_op_hit, + ex4_store_hit => ex4_store_hit, + ex4_axu_op_val => ex4_axu_op_val, + spr_dvc1_act => spr_dvc1_act, + spr_dvc2_act => spr_dvc2_act, + spr_dvc1_dbg => spr_dvc1_dbg, + spr_dvc2_dbg => spr_dvc2_dbg, + + an_ac_req_ld_pop => an_ac_req_ld_pop, + an_ac_req_st_pop => an_ac_req_st_pop, + an_ac_req_st_gather => an_ac_req_st_gather, + an_ac_req_st_pop_thrd => an_ac_req_st_pop_thrd, + an_ac_reld_data_vld => an_ac_reld_data_vld, + an_ac_reld_core_tag => an_ac_reld_core_tag, + an_ac_reld_qw => an_ac_reld_qw, + an_ac_reld_data => an_ac_reld_data, + an_ac_reld_data_coming => an_ac_reld_data_coming, + an_ac_reld_ditc => an_ac_reld_ditc, + an_ac_reld_crit_qw => an_ac_reld_crit_qw, + an_ac_reld_l1_dump => an_ac_reld_l1_dump, + an_ac_reld_ecc_err => an_ac_reld_ecc_err, + an_ac_reld_ecc_err_ue => an_ac_reld_ecc_err_ue, + an_ac_back_inv => an_ac_back_inv, + an_ac_back_inv_addr => an_ac_back_inv_addr, + an_ac_back_inv_target_bit1 => an_ac_back_inv_target_bit1, + an_ac_back_inv_target_bit3 => an_ac_back_inv_target_bit3, + an_ac_back_inv_target_bit4 => an_ac_back_inv_target_bit4, + an_ac_req_spare_ctrl_a1 => an_ac_req_spare_ctrl_a1, + + lsu_reld_data_vld => lsu_reld_data_vld, + lsu_reld_core_tag => lsu_reld_core_tag, + lsu_reld_qw => lsu_reld_qw, + lsu_reld_ditc => lsu_reld_ditc, + lsu_reld_ecc_err => lsu_reld_ecc_err, + lsu_reld_data => lsu_reld_data, + + lsu_req_st_pop => lsu_req_st_pop, + lsu_req_st_pop_thrd => lsu_req_st_pop_thrd, + + ac_an_reld_ditc_pop_int => ac_an_reld_ditc_pop_int, + ac_an_reld_ditc_pop_q => ac_an_reld_ditc_pop_q , + bx_ib_empty_int => bx_ib_empty_int , + bx_ib_empty_q => bx_ib_empty_q , + + iu_xu_ra => iu_xu_ra, + iu_xu_request => iu_xu_request, + iu_xu_wimge => iu_xu_wimge, + iu_xu_thread => iu_xu_thread, + iu_xu_userdef => iu_xu_userdef, + + mm_xu_lsu_req => mm_xu_lsu_req, + mm_xu_lsu_ttype => mm_xu_lsu_ttype, + mm_xu_lsu_wimge => mm_xu_lsu_wimge, + mm_xu_lsu_u => mm_xu_lsu_u, + mm_xu_lsu_addr => mm_xu_lsu_addr, + mm_xu_lsu_lpid => mm_xu_lsu_lpid, + mm_xu_lsu_lpidr => mm_xu_lsu_lpidr, + mm_xu_lsu_gs => mm_xu_lsu_gs, + mm_xu_lsu_ind => mm_xu_lsu_ind, + mm_xu_lsu_lbit => mm_xu_lsu_lbit, + xu_mm_lsu_token => xu_mm_lsu_token, + + bx_lsu_ob_pwr_tok => bx_lsu_ob_pwr_tok, + bx_lsu_ob_req_val => bx_lsu_ob_req_val, + bx_lsu_ob_ditc_val => bx_lsu_ob_ditc_val, + bx_lsu_ob_thrd => bx_lsu_ob_thrd, + bx_lsu_ob_qw => bx_lsu_ob_qw, + bx_lsu_ob_dest => bx_lsu_ob_dest, + bx_lsu_ob_data => bx_lsu_ob_data, + bx_lsu_ob_addr => bx_lsu_ob_addr, + lsu_bx_cmd_avail => lsu_bx_cmd_avail, + lsu_bx_cmd_sent => lsu_bx_cmd_sent, + lsu_bx_cmd_stall => lsu_bx_cmd_stall, + + lsu_xu_ldq_barr_done => lsu_xu_ldq_barr_done, + lsu_xu_barr_done => lsu_xu_barr_done, + + ldq_rel_data_val_early => ldq_rel_data_val_early, + ldq_rel_op_size => ldq_rel_op_size, + ldq_rel_addr => ldq_rel_addr, + ldq_rel_data_val => ldq_rel_data_val, + ldq_rel_rot_sel => ldq_rel_rot_sel, + ldq_rel_axu_val => ldq_rel_axu_val, + ldq_rel_ci => ldq_rel_ci, + ldq_rel_thrd_id => ldq_rel_thrd_id, + ldq_rel_le_mode => ldq_rel_le_mode, + ldq_rel_algebraic => ldq_rel_algebraic, + ldq_rel_256_data => ldq_rel_256_data, + ldq_rel_dvc1_en => ldq_rel_dvc1_en, + ldq_rel_dvc2_en => ldq_rel_dvc2_en, + ldq_rel_beat_crit_qw => ldq_rel_beat_crit_qw, + ldq_rel_beat_crit_qw_block => ldq_rel_beat_crit_qw_block, + lsu_xu_rel_wren => lsu_xu_rel_wren, + lsu_xu_rel_ta_gpr => lsu_xu_rel_ta_gpr, + + xu_iu_ex4_loadmiss_qentry => xu_iu_ex4_loadmiss_qentry, + xu_iu_ex4_loadmiss_target => xu_iu_ex4_loadmiss_target, + xu_iu_ex4_loadmiss_target_type => xu_iu_ex4_loadmiss_target_type, + xu_iu_ex4_loadmiss_tid => xu_iu_ex4_loadmiss_tid, + xu_iu_ex5_loadmiss_qentry => xu_iu_ex5_loadmiss_qentry, + xu_iu_ex5_loadmiss_target => xu_iu_ex5_loadmiss_target, + xu_iu_ex5_loadmiss_target_type => xu_iu_ex5_loadmiss_target_type, + xu_iu_ex5_loadmiss_tid => xu_iu_ex5_loadmiss_tid, + xu_iu_complete_qentry => xu_iu_complete_qentry, + xu_iu_complete_tid => xu_iu_complete_tid, + xu_iu_complete_target_type => xu_iu_complete_target_type, + + xu_iu_ex6_icbi_val => xu_iu_ex6_icbi_val, + xu_iu_ex6_icbi_addr => xu_iu_ex6_icbi_addr, + + xu_iu_larx_done_tid => xu_iu_larx_done_tid, + xu_mm_lmq_stq_empty => xu_mm_lmq_stq_empty, + lsu_xu_quiesce => lsu_xu_quiesce, + lsu_xu_dbell_val => lsu_xu_dbell_val, + lsu_xu_dbell_type => lsu_xu_dbell_type, + lsu_xu_dbell_brdcast => lsu_xu_dbell_brdcast, + lsu_xu_dbell_lpid_match => lsu_xu_dbell_lpid_match, + lsu_xu_dbell_pirtag => lsu_xu_dbell_pirtag, + + xu_ex1_rb => xu_ex1_rb, + xu_ex2_eff_addr => xu_ex2_eff_addr, + + ac_an_req_pwr_token => ac_an_req_pwr_token, + ac_an_req => ac_an_req, + ac_an_req_ra => ac_an_req_ra, + ac_an_req_ttype => ac_an_req_ttype, + ac_an_req_thread => ac_an_req_thread, + ac_an_req_wimg_w => ac_an_req_wimg_w, + ac_an_req_wimg_i => ac_an_req_wimg_i, + ac_an_req_wimg_m => ac_an_req_wimg_m, + ac_an_req_wimg_g => ac_an_req_wimg_g, + ac_an_req_endian => ac_an_req_endian, + ac_an_req_user_defined => ac_an_req_user_defined, + ac_an_req_spare_ctrl_a0 => ac_an_req_spare_ctrl_a0, + ac_an_req_ld_core_tag => ac_an_req_ld_core_tag, + ac_an_req_ld_xfr_len => ac_an_req_ld_xfr_len, + ac_an_st_byte_enbl => ac_an_st_byte_enbl, + ac_an_st_data => ac_an_st_data, + ac_an_st_data_pwr_token => ac_an_st_data_pwr_token, + + xu_pc_err_dcachedir_parity => xu_pc_err_dcachedir_parity, + xu_pc_err_dcachedir_multihit => xu_pc_err_dcachedir_multihit, + xu_pc_err_l2intrf_ecc => xu_pc_err_l2intrf_ecc, + xu_pc_err_l2intrf_ue => xu_pc_err_l2intrf_ue, + xu_pc_err_invld_reld => xu_pc_err_invld_reld, + xu_pc_err_l2credit_overrun => xu_pc_err_l2credit_overrun, + + pc_xu_event_bus_enable => pc_xu_event_bus_enable, + pc_xu_lsu_event_mux_ctrls => pc_xu_lsu_event_mux_ctrls, + pc_xu_cache_par_err_event => pc_xu_cache_par_err_event, + xu_pc_lsu_event_data => xu_pc_lsu_event_data, + + lsu_xu_cmd_debug => lsu_xu_cmd_debug, + + an_ac_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc, + pc_xu_abist_g8t_wenb => pc_xu_abist_g8t_wenb, + pc_xu_abist_g8t1p_renb_0 => pc_xu_abist_g8t1p_renb_0, + pc_xu_abist_g8t_bw_1 => pc_xu_abist_g8t_bw_1, + pc_xu_abist_g8t_bw_0 => pc_xu_abist_g8t_bw_0, + pc_xu_abist_wl32_comp_ena => pc_xu_abist_wl32_comp_ena, + pc_xu_abist_g8t_dcomp => pc_xu_abist_g8t_dcomp, + pc_xu_bo_unload => pc_xu_bo_unload, + pc_xu_bo_repair => pc_xu_bo_repair, + pc_xu_bo_reset => pc_xu_bo_reset, + pc_xu_bo_shdata => pc_xu_bo_shdata, + pc_xu_bo_select => pc_xu_bo_select(1 to 4), + xu_pc_bo_fail => xu_pc_bo_fail(1 to 4), + xu_pc_bo_diagout => xu_pc_bo_diagout(1 to 4), + + vcs => vcs, + vdd => vdd, + gnd => gnd, + nclk => nclk, + an_ac_coreid => an_ac_coreid(60 to 61), + an_ac_atpg_en_dc => an_ac_atpg_en_dc, + + bcfg_scan_in => ctrl_bcfg_scan_in, + bcfg_scan_out => ctrl_bcfg_scan_out, + dcfg_scan_in => ctrl_dcfg_scan_in, + dcfg_scan_out => ctrl_dcfg_scan_out, + gptr_scan_in => ctrl_gptr_scan_in, + gptr_scan_out => ctrl_gptr_scan_out, + time_scan_in => ctrl_time_scan_in, + time_scan_out => ctrl_time_scan_out, + func_scan_in => func_scan_in(41 to 58), + func_scan_out => func_scan_out(41 to 58), + ccfg_scan_in => ctrl_ccfg_scan_in, + ccfg_scan_out => ctrl_ccfg_scan_out, + regf_scan_in => regf_scan_in, + regf_scan_out => regf_scan_out, + abst_scan_in => abst_scan_in(0), + abst_scan_out => abst_scan_out(0), + repr_scan_in => ctrl_repr_scan_in, + repr_scan_out => ctrl_repr_scan_out +); + +xu_spr : entity work.xuq_spr(xuq_spr) +generic map( + hvmode => hvmode, + a2mode => a2mode, + expand_type => expand_type, + threads => threads, + regsize => regsize, + eff_ifar => eff_ifar, + spr_xucr0_init_mod => spr_xucr0_init_mod) +port map( + nclk => nclk, + + an_ac_coreid => an_ac_coreid, + spr_pvr_version_dc => spr_pvr_version_dc, + spr_pvr_revision_dc => spr_pvr_revision_dc, + an_ac_ext_interrupt => an_ac_ext_interrupt, + an_ac_crit_interrupt => an_ac_crit_interrupt, + an_ac_perf_interrupt => an_ac_perf_interrupt, + an_ac_reservation_vld => an_ac_reservation_vld, + an_ac_tb_update_pulse => an_ac_tb_update_pulse, + an_ac_tb_update_enable => an_ac_tb_update_enable, + an_ac_sleep_en => an_ac_sleep_en, + an_ac_hang_pulse => an_ac_hang_pulse, + ac_tc_machine_check => ac_tc_machine_check, + an_ac_external_mchk => an_ac_external_mchk, + pc_xu_instr_trace_mode => pc_xu_instr_trace_mode, + pc_xu_instr_trace_tid => pc_xu_instr_trace_tid, + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b, + an_ac_scan_diag_dc => an_ac_scan_diag_dc, + pc_xu_ccflush_dc => pc_xu_ccflush_dc, + clkoff_dc_b => clkoff_dc_b_b, + d_mode_dc => d_mode_dc_b, + delay_lclkr_dc => delay_lclkr_dc_b(2), + mpw1_dc_b => mpw1_dc_b_b(2), + mpw2_dc_b => mpw2_dc_b_b, + func_sl_thold_2 => func_sl_thold_2_b(1), + func_slp_sl_thold_2 => func_slp_sl_thold_2_b(0), + func_nsl_thold_2 => func_nsl_thold_2_b, + func_slp_nsl_thold_2 => func_slp_nsl_thold_2_b, + cfg_sl_thold_2 => cfg_sl_thold_2_b, + cfg_slp_sl_thold_2 => cfg_slp_sl_thold_2_b, + ary_nsl_thold_2 => ary_nsl_thold_2_b, + time_sl_thold_2 => time_sl_thold_2_b, + gptr_sl_thold_2 => gptr_sl_thold_2_b, + abst_sl_thold_2 => abst_sl_thold_2_b, + repr_sl_thold_2 => repr_sl_thold_2_b, + sg_2 => sg_2_b(1), + fce_2 => fce_2_b(0), + func_scan_in => func_scan_in(35 to 40), + func_scan_out => func_scan_out(35 to 40), + bcfg_scan_in => spr_bcfg_scan_in, + bcfg_scan_out => spr_bcfg_scan_out, + ccfg_scan_in => spr_ccfg_scan_in, + ccfg_scan_out => spr_ccfg_scan_out, + dcfg_scan_in => spr_dcfg_scan_in, + dcfg_scan_out => spr_dcfg_scan_out, + time_scan_in => spr_time_scan_in, + time_scan_out => spr_time_scan_out, + abst_scan_in => abst_scan_in(1), + abst_scan_out => abst_scan_out(1), + repr_scan_in => spr_repr_scan_in, + repr_scan_out => spr_repr_scan_out, + gptr_scan_in => spr_gptr_scan_in, + gptr_scan_out => spr_gptr_scan_out, + + dec_spr_rf0_tid => dec_spr_rf0_tid, + dec_spr_rf0_instr => dec_spr_rf0_instr, + dec_spr_rf1_val => dec_spr_rf1_val, + dec_spr_ex1_epid_instr => dec_spr_ex1_epid_instr, + dec_spr_ex4_val => dec_spr_ex4_val, + + spr_byp_ex3_spr_rt => spr_byp_ex3_spr_rt, + + fxu_spr_ex1_rs2 => fxu_spr_ex1_rs2, + + fxu_spr_ex1_rs0 => fxu_spr_ex1_rs0, + fxu_spr_ex1_rs1 => fxu_spr_ex1_rs1, + mux_spr_ex2_rt => mux_spr_ex2_rt, + + cpl_spr_ex5_act => cpl_spr_ex5_act, + cpl_spr_ex5_int => cpl_spr_ex5_int, + cpl_spr_ex5_gint => cpl_spr_ex5_gint, + cpl_spr_ex5_cint => cpl_spr_ex5_cint, + cpl_spr_ex5_mcint => cpl_spr_ex5_mcint, + cpl_spr_ex5_nia => cpl_spr_ex5_nia, + cpl_spr_ex5_esr => cpl_spr_ex5_esr, + cpl_spr_ex5_mcsr => cpl_spr_ex5_mcsr, + cpl_spr_ex5_dbsr => cpl_spr_ex5_dbsr, + cpl_spr_ex5_dear_save => cpl_spr_ex5_dear_save, + cpl_spr_ex5_dear_update_saved => cpl_spr_ex5_dear_update_saved, + cpl_spr_ex5_dear_update => cpl_spr_ex5_dear_update, + cpl_spr_ex5_dbsr_update => cpl_spr_ex5_dbsr_update, + cpl_spr_ex5_esr_update => cpl_spr_ex5_esr_update, + cpl_spr_ex5_srr0_dec => cpl_spr_ex5_srr0_dec, + cpl_spr_ex5_force_gsrr => cpl_spr_ex5_force_gsrr, + cpl_spr_ex5_dbsr_ide => cpl_spr_ex5_dbsr_ide, + spr_cpl_dbsr_ide => spr_cpl_dbsr_ide, + + spr_cpl_external_mchk => spr_cpl_external_mchk, + spr_cpl_ext_interrupt => spr_cpl_ext_interrupt, + spr_cpl_udec_interrupt => spr_cpl_udec_interrupt, + spr_cpl_perf_interrupt => spr_cpl_perf_interrupt, + spr_cpl_dec_interrupt => spr_cpl_dec_interrupt, + spr_cpl_fit_interrupt => spr_cpl_fit_interrupt, + spr_cpl_crit_interrupt => spr_cpl_crit_interrupt, + spr_cpl_wdog_interrupt => spr_cpl_wdog_interrupt, + spr_cpl_dbell_interrupt => spr_cpl_dbell_interrupt, + spr_cpl_cdbell_interrupt => spr_cpl_cdbell_interrupt, + spr_cpl_gdbell_interrupt => spr_cpl_gdbell_interrupt, + spr_cpl_gcdbell_interrupt => spr_cpl_gcdbell_interrupt, + spr_cpl_gmcdbell_interrupt => spr_cpl_gmcdbell_interrupt, + cpl_spr_ex5_dbell_taken => cpl_spr_ex5_dbell_taken, + cpl_spr_ex5_cdbell_taken => cpl_spr_ex5_cdbell_taken, + cpl_spr_ex5_gdbell_taken => cpl_spr_ex5_gdbell_taken, + cpl_spr_ex5_gcdbell_taken => cpl_spr_ex5_gcdbell_taken, + cpl_spr_ex5_gmcdbell_taken => cpl_spr_ex5_gmcdbell_taken, + + lsu_xu_dbell_val => lsu_xu_dbell_val, + lsu_xu_dbell_type => lsu_xu_dbell_type, + lsu_xu_dbell_brdcast => lsu_xu_dbell_brdcast, + lsu_xu_dbell_lpid_match => lsu_xu_dbell_lpid_match, + lsu_xu_dbell_pirtag => lsu_xu_dbell_pirtag, + + xu_lsu_slowspr_val => xu_lsu_slowspr_val, + xu_lsu_slowspr_rw => xu_lsu_slowspr_rw, + xu_lsu_slowspr_etid => xu_lsu_slowspr_etid, + xu_lsu_slowspr_addr => xu_lsu_slowspr_addr, + xu_lsu_slowspr_data => xu_lsu_slowspr_data, + + ac_an_dcr_act => ac_an_dcr_act, + ac_an_dcr_val => ac_an_dcr_val, + ac_an_dcr_read => ac_an_dcr_read, + ac_an_dcr_user => ac_an_dcr_user, + ac_an_dcr_etid => ac_an_dcr_etid, + ac_an_dcr_addr => ac_an_dcr_addr, + ac_an_dcr_data => ac_an_dcr_data, + + xu_ex4_flush => xu_s_ex4_flush_int, + xu_ex5_flush => xu_s_ex5_flush_int, + + spr_cpl_fp_precise => spr_cpl_fp_precise, + spr_cpl_ex3_spr_hypv => spr_cpl_ex3_spr_hypv, + spr_cpl_ex3_spr_illeg => spr_cpl_ex3_spr_illeg, + spr_cpl_ex3_spr_priv => spr_cpl_ex3_spr_priv, + spr_cpl_ex3_ct_le => spr_cpl_ex3_ct_le, + spr_cpl_ex3_ct_be => spr_cpl_ex3_ct_be, + + cpl_spr_stop => cpl_spr_stop, + xu_pc_running => xu_pc_running, + xu_iu_run_thread => xu_iu_run_thread, + xu_iu_single_instr_mode => xu_iu_single_instr_mode, + xu_iu_raise_iss_pri => xu_iu_raise_iss_pri, + spr_cpl_ex2_run_ctl_flush => spr_cpl_ex2_run_ctl_flush, + xu_pc_spr_ccr0_we => spr_ccr0_we, + + iu_xu_quiesce => iu_xu_quiesce, + lsu_xu_quiesce => lsu_xu_quiesce, + mm_xu_quiesce => mm_xu_quiesce, + bx_xu_quiesce => bx_xu_quiesce, + spr_cpl_quiesce => spr_cpl_quiesce, + cpl_spr_quiesce => cpl_spr_quiesce, + + pc_xu_extirpts_dis_on_stop => pc_xu_extirpts_dis_on_stop, + pc_xu_timebase_dis_on_stop => pc_xu_timebase_dis_on_stop, + pc_xu_decrem_dis_on_stop => pc_xu_decrem_dis_on_stop, + + pc_xu_ram_mode => pc_xu_ram_mode, + pc_xu_ram_thread => pc_xu_ram_thread, + pc_xu_msrovride_enab => pc_xu_msrovride_enab, + pc_xu_msrovride_pr => pc_xu_msrovride_pr, + pc_xu_msrovride_gs => pc_xu_msrovride_gs, + pc_xu_msrovride_de => pc_xu_msrovride_de, + + cpl_spr_ex5_instr_cpl => cpl_spr_ex5_instr_cpl, + xu_pc_err_llbust_attempt => xu_pc_err_llbust_attempt, + xu_pc_err_llbust_failed => xu_pc_err_llbust_failed, + + spr_byp_ex4_is_mtxer => spr_byp_ex4_is_mtxer, + spr_byp_ex4_is_mfxer => spr_byp_ex4_is_mfxer, + + pc_xu_reset_wd_complete => pc_xu_reset_wd_complete, + pc_xu_reset_1_complete => pc_xu_reset_1_complete, + pc_xu_reset_2_complete => pc_xu_reset_2_complete, + pc_xu_reset_3_complete => pc_xu_reset_3_complete, + ac_tc_reset_1_request => ac_tc_reset_1_request, + ac_tc_reset_2_request => ac_tc_reset_2_request, + ac_tc_reset_3_request => ac_tc_reset_3_request, + ac_tc_reset_wd_request => ac_tc_reset_wd_request, + + pc_xu_inj_llbust_attempt => pc_xu_inj_llbust_attempt, + pc_xu_inj_llbust_failed => pc_xu_inj_llbust_failed, + pc_xu_inj_wdt_reset => pc_xu_inj_wdt_reset, + xu_pc_err_wdt_reset => xu_pc_err_wdt_reset, + + spr_cpl_ex3_sprg_ce => spr_cpl_ex3_sprg_ce, + spr_cpl_ex3_sprg_ue => spr_cpl_ex3_sprg_ue, + pc_xu_inj_sprg_ecc => pc_xu_inj_sprg_ecc, + xu_pc_err_sprg_ecc => xu_pc_err_sprg_ecc, + + spr_perf_tx_events => spr_perf_tx_events, + xu_lsu_mtspr_trace_en => xu_lsu_mtspr_trace_en, + + spr_bit_act => spr_bit_act, + spr_cpl_iac1_en => spr_cpl_iac1_en, + spr_cpl_iac2_en => spr_cpl_iac2_en, + spr_cpl_iac3_en => spr_cpl_iac3_en, + spr_cpl_iac4_en => spr_cpl_iac4_en, + spr_dbcr1_iac12m => spr_dbcr1_iac12m, + spr_dbcr1_iac34m => spr_dbcr1_iac34m, + spr_epcr_duvd => spr_epcr_duvd, + lsu_xu_spr_xucr0_cslc_xuop => lsu_xu_spr_xucr0_cslc_xuop, + lsu_xu_spr_xucr0_cslc_binv => lsu_xu_spr_xucr0_cslc_binv, + lsu_xu_spr_xucr0_clo => lsu_xu_spr_xucr0_clo, + lsu_xu_spr_xucr0_cul => lsu_xu_spr_xucr0_cul, + lsu_xu_spr_epsc_epr => lsu_xu_spr_epsc_epr, + lsu_xu_spr_epsc_egs => lsu_xu_spr_epsc_egs, + spr_epcr_extgs => spr_epcr_extgs, + spr_msr_pr => spr_msr_pr_int, + spr_msr_is => spr_msr_is, + spr_msr_cm => spr_msr_cm_int, + spr_msr_gs => spr_msr_gs_int, + spr_msr_me => spr_msr_me, + xu_lsu_spr_xucr0_clfc => xu_lsu_spr_xucr0_clfc, + xu_pc_spr_ccr0_pme => xu_pc_spr_ccr0_pme, + spr_ccr2_en_dcr => spr_ccr2_en_dcr_int, + spr_ccr2_en_pc => spr_ccr2_en_pc, + xu_iu_spr_ccr2_ifratsc => xu_iu_spr_ccr2_ifratsc, + xu_iu_spr_ccr2_ifrat => xu_iu_spr_ccr2_ifrat, + xu_lsu_spr_ccr2_dfratsc => xu_lsu_spr_ccr2_dfratsc, + xu_lsu_spr_ccr2_dfrat => xu_lsu_spr_ccr2_dfrat, + spr_ccr2_ucode_dis => spr_ccr2_ucode_dis, + spr_ccr2_ap => spr_ccr2_ap_int, + spr_ccr2_en_attn => spr_ccr2_en_attn, + spr_ccr2_en_ditc => spr_ccr2_en_ditc_int, + spr_ccr2_en_icswx => spr_ccr2_en_icswx, + spr_ccr2_notlb => spr_ccr2_notlb_int, + xu_lsu_spr_xucr0_mbar_ack => xu_lsu_spr_xucr0_mbar_ack, + xu_lsu_spr_xucr0_tlbsync => xu_lsu_spr_xucr0_tlbsync, + spr_dec_spr_xucr0_ssdly => spr_dec_spr_xucr0_ssdly, + spr_xucr0_cls => xu_lsu_spr_xucr0_cls, + xu_lsu_spr_xucr0_aflsta => xu_lsu_spr_xucr0_aflsta, + spr_xucr0_mddp => spr_xucr0_mddp, + xu_lsu_spr_xucr0_cred => xu_lsu_spr_xucr0_cred, + xu_lsu_spr_xucr0_rel => xu_lsu_spr_xucr0_rel_int, + spr_xucr0_mdcp => spr_xucr0_mdcp, + xu_lsu_spr_xucr0_flsta => xu_lsu_spr_xucr0_flsta, + xu_lsu_spr_xucr0_l2siw => xu_lsu_spr_xucr0_l2siw, + xu_lsu_spr_xucr0_flh2l2 => xu_lsu_spr_xucr0_flh2l2, + xu_lsu_spr_xucr0_dcdis => xu_lsu_spr_xucr0_dcdis_int, + xu_lsu_spr_xucr0_wlk => xu_lsu_spr_xucr0_wlk, + cpl_spr_dbcr0_edm => cpl_spr_dbcr0_edm, + spr_dbcr0_idm => spr_dbcr0_idm, + spr_dbcr0_icmp => spr_dbcr0_icmp, + spr_dbcr0_brt => spr_dbcr0_brt, + spr_dbcr0_irpt => spr_dbcr0_irpt, + spr_dbcr0_trap => spr_dbcr0_trap, + spr_dbcr0_dac1 => spr_dbcr0_dac1, + spr_dbcr0_dac2 => spr_dbcr0_dac2, + spr_dbcr0_ret => spr_dbcr0_ret, + spr_dbcr0_dac3 => spr_dbcr0_dac3, + spr_dbcr0_dac4 => spr_dbcr0_dac4, + spr_epcr_dtlbgs => spr_epcr_dtlbgs, + spr_epcr_itlbgs => spr_epcr_itlbgs, + spr_epcr_dsigs => spr_epcr_dsigs, + spr_epcr_isigs => spr_epcr_isigs, + spr_epcr_dgtmi => spr_dec_rf1_epcr_dgtmi, + xu_mm_spr_epcr_dmiuh => xu_mm_spr_epcr_dmiuh, + spr_msr_ucle => spr_msr_ucle, + spr_msr_spv => spr_msr_spv_int, + spr_msr_fp => spr_msr_fp_int, + spr_msr_de => spr_msr_de, + spr_msr_ds => spr_msr_ds_int, + spr_msrp_uclep => spr_msrp_uclep, + spr_xucr0_clkg_ctl => spr_xucr0_clkg_ctl, + + an_ac_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc, + pc_xu_abist_ena_dc => pc_xu_abist_ena_dc, + pc_xu_abist_g8t_wenb => pc_xu_abist_g8t_wenb, + pc_xu_abist_waddr_0 => pc_xu_abist_waddr_0(4 to 9), + pc_xu_abist_di_0 => pc_xu_abist_di_0, + pc_xu_abist_g8t1p_renb_0 => pc_xu_abist_g8t1p_renb_0, + pc_xu_abist_raddr_0 => pc_xu_abist_raddr_0(4 to 9), + pc_xu_abist_wl32_comp_ena => pc_xu_abist_wl32_comp_ena, + pc_xu_abist_raw_dc_b => pc_xu_abist_raw_dc_b, + pc_xu_abist_g8t_dcomp => pc_xu_abist_g8t_dcomp, + pc_xu_abist_g8t_bw_1 => pc_xu_abist_g8t_bw_1, + pc_xu_abist_g8t_bw_0 => pc_xu_abist_g8t_bw_0, + bolt_sl_thold_2 => bolt_sl_thold_2_b, + bo_enable_2 => bo_enable_2_b, + pc_xu_bo_unload => pc_xu_bo_unload, + pc_xu_bo_repair => pc_xu_bo_repair, + pc_xu_bo_reset => pc_xu_bo_reset, + pc_xu_bo_shdata => pc_xu_bo_shdata, + pc_xu_bo_select => pc_xu_bo_select(0), + xu_pc_bo_fail => xu_pc_bo_fail(0), + xu_pc_bo_diagout => xu_pc_bo_diagout(0), + + lsu_xu_cmd_debug => lsu_xu_cmd_debug, + pc_xu_trace_bus_enable => pc_xu_trace_bus_enable, + spr_debug_mux_ctrls => spr_debug_mux_ctrls, + spr_debug_data_in => spr_debug_data_in, + spr_debug_data_out => spr_debug_data_out, + spr_trigger_data_in => spr_trigger_data_in, + spr_trigger_data_out => spr_trigger_data_out, + + vcs => vcs, + vdd => vdd, + gnd => gnd +); + +spr_msr_gs <= spr_msr_gs_int; +spr_msr_pr <= spr_msr_pr_int; +spr_msr_ds <= spr_msr_ds_int; +spr_msr_cm <= spr_msr_cm_int; +spr_msr_fp <= spr_msr_fp_int; +spr_msr_spv <= spr_msr_spv_int; +spr_ccr2_ap <= spr_ccr2_ap_int; +spr_ccr2_en_dcr <= spr_ccr2_en_dcr_int; +spr_ccr2_notlb <= spr_ccr2_notlb_int; +spr_ccr2_en_ditc <= spr_ccr2_en_ditc_int; +xu_lsu_spr_xucr0_dcdis <= xu_lsu_spr_xucr0_dcdis_int; +xu_lsu_spr_xucr0_rel <= xu_lsu_spr_xucr0_rel_int; +spr_xucr0_clkg_ctl_b0 <= spr_xucr0_clkg_ctl(0); + +end xuq_ctrl_spr; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_debug.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_debug.vhdl new file mode 100644 index 0000000..dea9923 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_debug.vhdl @@ -0,0 +1,231 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee,ibm,support,work,tri,clib; +use ieee.std_logic_1164.all; +use support.power_logic_pkg.all; +use tri.tri_latches_pkg.all; + +entity xuq_debug is +generic( + expand_type : integer := 2); +port( + nclk : in clk_logic; + + d_mode_dc : in std_ulogic; + delay_lclkr_dc : in std_ulogic; + mpw1_dc_b : in std_ulogic; + mpw2_dc_b : in std_ulogic; + sg_0 : in std_ulogic; + func_slp_sl_thold_0_b : in std_ulogic; + func_slp_sl_force : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + dec_byp_ex3_instr_trace_val : in std_ulogic; + + pc_xu_trace_bus_enable : in std_ulogic; + debug_mux_ctrls : in std_ulogic_vector(0 to 15); + trigger_data_in : in std_ulogic_vector(0 to 11); + debug_data_in : in std_ulogic_vector(0 to 87); + trigger_data_out : out std_ulogic_vector(0 to 11); + debug_data_out : out std_ulogic_vector(0 to 87); + + dbg_group0 : in std_ulogic_vector(0 to 87) := (others=>'0'); + dbg_group1 : in std_ulogic_vector(0 to 87) := (others=>'0'); + dbg_group2 : in std_ulogic_vector(0 to 87) := (others=>'0'); + dbg_group3 : in std_ulogic_vector(0 to 87) := (others=>'0'); + dbg_group4 : in std_ulogic_vector(0 to 87) := (others=>'0'); + dbg_group5 : in std_ulogic_vector(0 to 87) := (others=>'0'); + dbg_group6 : in std_ulogic_vector(0 to 87) := (others=>'0'); + dbg_group7 : in std_ulogic_vector(0 to 87) := (others=>'0'); + dbg_group8 : in std_ulogic_vector(0 to 87) := (others=>'0'); + dbg_group9 : in std_ulogic_vector(0 to 87) := (others=>'0'); + dbg_group10 : in std_ulogic_vector(0 to 87) := (others=>'0'); + dbg_group11 : in std_ulogic_vector(0 to 87) := (others=>'0'); + dbg_group12 : in std_ulogic_vector(0 to 87) := (others=>'0'); + dbg_group13 : in std_ulogic_vector(0 to 87) := (others=>'0'); + dbg_group14 : in std_ulogic_vector(0 to 87) := (others=>'0'); + dbg_group15 : in std_ulogic_vector(0 to 87) := (others=>'0'); + + trg_group0 : in std_ulogic_vector(0 to 11) := (others=>'0'); + trg_group1 : in std_ulogic_vector(0 to 11) := (others=>'0'); + trg_group2 : in std_ulogic_vector(0 to 11) := (others=>'0'); + trg_group3 : in std_ulogic_vector(0 to 11) := (others=>'0'); + + vdd : inout power_logic; + gnd : inout power_logic +); + +-- synopsys translate_off + +-- synopsys translate_on +end xuq_debug; +architecture xuq_debug of xuq_debug is + +signal tiup : std_ulogic; +signal trace_bus_enable_q : std_ulogic; +signal debug_mux_ctrls_q : std_ulogic_vector(0 to 15); +signal debug_mux_ctrls_int_q, debug_mux_ctrls_int : std_ulogic_vector(0 to 15); +signal trigger_data_out_q, trigger_data_out_d : std_ulogic_vector(0 to 11); +signal debug_data_out_q, debug_data_out_d : std_ulogic_vector(0 to 87); +signal ex4_instr_trace_val_q : std_ulogic; +constant trace_bus_enable_offset : integer := 0; +constant debug_mux_ctrls_offset : integer := trace_bus_enable_offset + 1; +constant debug_mux_ctrls_int_offset : integer := debug_mux_ctrls_offset + debug_mux_ctrls_q'length; +constant trigger_data_out_offset : integer := debug_mux_ctrls_int_offset + debug_mux_ctrls_int_q'length; +constant debug_data_out_offset : integer := trigger_data_out_offset + trigger_data_out_q'length; +constant ex4_instr_trace_val_offset : integer := debug_data_out_offset + debug_data_out_q'length; +constant scan_right : integer := ex4_instr_trace_val_offset + 1; +signal siv : std_ulogic_vector(0 to scan_right-1); +signal sov : std_ulogic_vector(0 to scan_right-1); + +begin + +tiup <= '1'; +trigger_data_out <= trigger_data_out_q; +debug_data_out <= debug_data_out_q; + +with ex4_instr_trace_val_q select + debug_mux_ctrls_int <= x"11E0" when '1', + debug_mux_ctrls_q when others; + +xu_debug_mux : entity clib.c_debug_mux16(c_debug_mux16) +port map( + vd => vdd, + gd => gnd, + select_bits => debug_mux_ctrls_int_q, + trace_data_in => debug_data_in, + trigger_data_in => trigger_data_in, + dbg_group0 => dbg_group0, + dbg_group1 => dbg_group1, + dbg_group2 => dbg_group2, + dbg_group3 => dbg_group3, + dbg_group4 => dbg_group4, + dbg_group5 => dbg_group5, + dbg_group6 => dbg_group6, + dbg_group7 => dbg_group7, + dbg_group8 => dbg_group8, + dbg_group9 => dbg_group9, + dbg_group10 => dbg_group10, + dbg_group11 => dbg_group11, + dbg_group12 => dbg_group12, + dbg_group13 => dbg_group13, + dbg_group14 => dbg_group14, + dbg_group15 => dbg_group15, + trg_group0 => trg_group0, + trg_group1 => trg_group1, + trg_group2 => trg_group2, + trg_group3 => trg_group3, + trigger_data_out => trigger_data_out_d, + trace_data_out => debug_data_out_d); + +trace_bus_enable_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(trace_bus_enable_offset), + scout => sov(trace_bus_enable_offset), + din => pc_xu_trace_bus_enable, + dout => trace_bus_enable_q); +debug_mux_ctrls_latch : tri_rlmreg_p + generic map (width => debug_mux_ctrls_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(debug_mux_ctrls_offset to debug_mux_ctrls_offset + debug_mux_ctrls_q'length-1), + scout => sov(debug_mux_ctrls_offset to debug_mux_ctrls_offset + debug_mux_ctrls_q'length-1), + din => debug_mux_ctrls, + dout => debug_mux_ctrls_q); +debug_mux_ctrls_int_latch : tri_rlmreg_p + generic map (width => debug_mux_ctrls_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(debug_mux_ctrls_int_offset to debug_mux_ctrls_int_offset + debug_mux_ctrls_int_q'length-1), + scout => sov(debug_mux_ctrls_int_offset to debug_mux_ctrls_int_offset + debug_mux_ctrls_int_q'length-1), + din => debug_mux_ctrls_int, + dout => debug_mux_ctrls_int_q); +trigger_data_out_latch : tri_rlmreg_p + generic map (width => trigger_data_out_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(trigger_data_out_offset to trigger_data_out_offset + trigger_data_out_q'length-1), + scout => sov(trigger_data_out_offset to trigger_data_out_offset + trigger_data_out_q'length-1), + din => trigger_data_out_d, + dout => trigger_data_out_q); +debug_data_out_latch : tri_rlmreg_p + generic map (width => debug_data_out_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(debug_data_out_offset to debug_data_out_offset + debug_data_out_q'length-1), + scout => sov(debug_data_out_offset to debug_data_out_offset + debug_data_out_q'length-1), + din => debug_data_out_d, + dout => debug_data_out_q); +ex4_instr_trace_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_instr_trace_val_offset), + scout => sov(ex4_instr_trace_val_offset), + din => dec_byp_ex3_instr_trace_val, + dout => ex4_instr_trace_val_q); + +siv(0 to scan_right-1) <= sov(1 to scan_right-1) & scan_in; +scan_out <= sov(0); + + +end architecture xuq_debug; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_debug_mux32.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_debug_mux32.vhdl new file mode 100644 index 0000000..2612c5b --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_debug_mux32.vhdl @@ -0,0 +1,338 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee,ibm,support,work,tri,clib,work; +use ieee.std_logic_1164.all; +use support.power_logic_pkg.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; +use tri.tri_latches_pkg.all; +use work.xuq_pkg.all; + +entity xuq_debug_mux32 is +generic(expand_type :integer := 2); +port( + + trace_bus_enable :in std_ulogic; + trace_unit_sel :in std_ulogic_vector(0 to 15); + + debug_data_in :in std_ulogic_vector(0 to 87); + trigger_data_in :in std_ulogic_vector(0 to 11); + + dbg_group0 :in std_ulogic_vector(0 to 87); + dbg_group1 :in std_ulogic_vector(0 to 87); + dbg_group2 :in std_ulogic_vector(0 to 87); + dbg_group3 :in std_ulogic_vector(0 to 87); + dbg_group4 :in std_ulogic_vector(0 to 87); + dbg_group5 :in std_ulogic_vector(0 to 87); + dbg_group6 :in std_ulogic_vector(0 to 87); + dbg_group7 :in std_ulogic_vector(0 to 87); + dbg_group8 :in std_ulogic_vector(0 to 87); + dbg_group9 :in std_ulogic_vector(0 to 87); + dbg_group10 :in std_ulogic_vector(0 to 87); + dbg_group11 :in std_ulogic_vector(0 to 87); + dbg_group12 :in std_ulogic_vector(0 to 87); + dbg_group13 :in std_ulogic_vector(0 to 87); + dbg_group14 :in std_ulogic_vector(0 to 87); + dbg_group15 :in std_ulogic_vector(0 to 87); + dbg_group16 :in std_ulogic_vector(0 to 87); + dbg_group17 :in std_ulogic_vector(0 to 87); + dbg_group18 :in std_ulogic_vector(0 to 87); + dbg_group19 :in std_ulogic_vector(0 to 87); + dbg_group20 :in std_ulogic_vector(0 to 87); + dbg_group21 :in std_ulogic_vector(0 to 87); + dbg_group22 :in std_ulogic_vector(0 to 87); + dbg_group23 :in std_ulogic_vector(0 to 87); + dbg_group24 :in std_ulogic_vector(0 to 87); + dbg_group25 :in std_ulogic_vector(0 to 87); + dbg_group26 :in std_ulogic_vector(0 to 87); + dbg_group27 :in std_ulogic_vector(0 to 87); + dbg_group28 :in std_ulogic_vector(0 to 87); + dbg_group29 :in std_ulogic_vector(0 to 87); + dbg_group30 :in std_ulogic_vector(0 to 87); + dbg_group31 :in std_ulogic_vector(0 to 87); + + trg_group0 :in std_ulogic_vector(0 to 11); + trg_group1 :in std_ulogic_vector(0 to 11); + trg_group2 :in std_ulogic_vector(0 to 11); + trg_group3 :in std_ulogic_vector(0 to 11); + + trigger_data_out :out std_ulogic_vector(0 to 11); + debug_data_out :out std_ulogic_vector(0 to 87); + + vdd :inout power_logic; + gnd :inout power_logic; + nclk :in clk_logic; + sg_0 :in std_ulogic; + func_slp_sl_thold_0_b :in std_ulogic; + func_slp_sl_force :in std_ulogic; + d_mode_dc :in std_ulogic; + delay_lclkr_dc :in std_ulogic; + mpw1_dc_b :in std_ulogic; + mpw2_dc_b :in std_ulogic; + scan_in :in std_ulogic; + scan_out :out std_ulogic +); + +-- synopsys translate_off + +-- synopsys translate_on +end xuq_debug_mux32; +architecture xuq_debug_mux32 of xuq_debug_mux32 is + +type ARY_32 is array (0 to 31) of std_ulogic_vector(0 to 3); + +signal dbg_group_int_data :std_ulogic_vector(0 to 87); +signal dbg_group_rotate0 :std_ulogic_vector(0 to 87); +signal dbg_group_rotate1 :std_ulogic_vector(0 to 87); +signal dbg_group_rotate2 :std_ulogic_vector(0 to 87); +signal dbg_group_rotate3 :std_ulogic_vector(0 to 87); +signal dbg_group_rotate :std_ulogic_vector(0 to 87); +signal dbg_group_pthru_data0 :std_ulogic_vector(0 to 21); +signal dbg_group_pthru_data1 :std_ulogic_vector(0 to 21); +signal dbg_group_pthru_data2 :std_ulogic_vector(0 to 21); +signal dbg_group_pthru_data3 :std_ulogic_vector(0 to 21); +signal dbg_group_pthru_data :std_ulogic_vector(0 to 87); +signal debug_data_out_d :std_ulogic_vector(0 to 87); +signal debug_data_out_q :std_ulogic_vector(0 to 87); +signal dbg_group_int_trig :std_ulogic_vector(0 to 11); +signal dbg_group_rot_trig0 :std_ulogic_vector(0 to 11); +signal dbg_group_rot_trig1 :std_ulogic_vector(0 to 11); +signal dbg_group_rot_trig :std_ulogic_vector(0 to 11); +signal dbg_group_pthru_trig0 :std_ulogic_vector(0 to 5); +signal dbg_group_pthru_trig1 :std_ulogic_vector(0 to 5); +signal dbg_group_pthru_trig :std_ulogic_vector(0 to 11); +signal trigger_data_out_d :std_ulogic_vector(0 to 11); +signal trigger_data_out_q :std_ulogic_vector(0 to 11); +signal trace_unit_sel10 :std_ulogic_vector(0 to 31); +signal trace_unit_selC840 :std_ulogic_vector(0 to 31); +signal trace_unit_sel3210 :std_ulogic_vector(0 to 31); +signal dbg_data_unit_sel_d :ARY_32; +signal dbg_data_unit_sel_q :ARY_32; +signal dbg_trace_unit_sel_d :std_ulogic_vector(32 to 46); +signal dbg_trace_unit_sel_q :std_ulogic_vector(32 to 46); +signal dbg_rot_grp_sel :std_ulogic_vector(0 to 3); +signal dbg_data_pthru_sel :std_ulogic_vector(0 to 3); +signal dbg_trig_grp_sel :std_ulogic_vector(0 to 3); +signal dbg_rot_trig_sel :std_ulogic; +signal dbg_trig_pthru_sel :std_ulogic_vector(0 to 1); + +constant dbg_data_unit_sel_offset :natural := 0; +constant dbg_trace_unit_sel_offset :natural := dbg_data_unit_sel_offset + dbg_data_unit_sel_q(0)'length*32; +constant trigger_data_out_offset :natural := dbg_trace_unit_sel_offset + 15; +constant debug_data_out_offset :natural := trigger_data_out_offset + 12; +constant scan_right :natural := debug_data_out_offset + 88 - 1; +signal siv :std_ulogic_vector(0 to scan_right); +signal sov :std_ulogic_vector(0 to scan_right); + +begin + + +with trace_unit_sel(0) select + trace_unit_sel10 <= x"80000000" when '0', + x"00008000" when others; + +with trace_unit_sel(1 to 2) select + trace_unit_selC840 <= trace_unit_sel10(0 to 31) when "00", + x"0" & trace_unit_sel10(0 to 27) when "01", + x"00" & trace_unit_sel10(0 to 23) when "10", + x"000" & trace_unit_sel10(0 to 19) when others; + +with trace_unit_sel(3 to 4) select + trace_unit_sel3210 <= trace_unit_selC840(0 to 31) when "00", + '0' & trace_unit_selC840(0 to 30) when "01", + "00" & trace_unit_selC840(0 to 29) when "10", + "000" & trace_unit_selC840(0 to 28) when others; + +with trace_unit_sel(5 to 6) select + dbg_trace_unit_sel_d(32 to 35) <= "1000" when "00", + "0100" when "01", + "0010" when "10", + "0001" when others; + +dbg_trace_unit_sel_d(36 to 39) <= trace_unit_sel(7 to 10); + +with trace_unit_sel(11 to 12) select + dbg_trace_unit_sel_d(40 to 43) <= "1000" when "00", + "0100" when "01", + "0010" when "10", + "0001" when others; + +dbg_trace_unit_sel_d(44) <= trace_unit_sel(13); + +dbg_trace_unit_sel_d(45 to 46) <= trace_unit_sel(14 to 15); + +dbg_rot_grp_sel <= dbg_trace_unit_sel_q(32 to 35); +dbg_data_pthru_sel <= dbg_trace_unit_sel_q(36 to 39); +dbg_trig_grp_sel <= dbg_trace_unit_sel_q(40 to 43); +dbg_rot_trig_sel <= dbg_trace_unit_sel_q(44); +dbg_trig_pthru_sel <= dbg_trace_unit_sel_q(45 to 46); + + +dbg_group_int_data <= (dbg_group0 and fanout(dbg_data_unit_sel_q(00),88)) or + (dbg_group1 and fanout(dbg_data_unit_sel_q(01),88)) or + (dbg_group2 and fanout(dbg_data_unit_sel_q(02),88)) or + (dbg_group3 and fanout(dbg_data_unit_sel_q(03),88)) or + (dbg_group4 and fanout(dbg_data_unit_sel_q(04),88)) or + (dbg_group5 and fanout(dbg_data_unit_sel_q(05),88)) or + (dbg_group6 and fanout(dbg_data_unit_sel_q(06),88)) or + (dbg_group7 and fanout(dbg_data_unit_sel_q(07),88)) or + (dbg_group8 and fanout(dbg_data_unit_sel_q(08),88)) or + (dbg_group9 and fanout(dbg_data_unit_sel_q(09),88)) or + (dbg_group10 and fanout(dbg_data_unit_sel_q(10),88)) or + (dbg_group11 and fanout(dbg_data_unit_sel_q(11),88)) or + (dbg_group12 and fanout(dbg_data_unit_sel_q(12),88)) or + (dbg_group13 and fanout(dbg_data_unit_sel_q(13),88)) or + (dbg_group14 and fanout(dbg_data_unit_sel_q(14),88)) or + (dbg_group15 and fanout(dbg_data_unit_sel_q(15),88)) or + (dbg_group16 and fanout(dbg_data_unit_sel_q(16),88)) or + (dbg_group17 and fanout(dbg_data_unit_sel_q(17),88)) or + (dbg_group18 and fanout(dbg_data_unit_sel_q(18),88)) or + (dbg_group19 and fanout(dbg_data_unit_sel_q(19),88)) or + (dbg_group20 and fanout(dbg_data_unit_sel_q(20),88)) or + (dbg_group21 and fanout(dbg_data_unit_sel_q(21),88)) or + (dbg_group22 and fanout(dbg_data_unit_sel_q(22),88)) or + (dbg_group23 and fanout(dbg_data_unit_sel_q(23),88)) or + (dbg_group24 and fanout(dbg_data_unit_sel_q(24),88)) or + (dbg_group25 and fanout(dbg_data_unit_sel_q(25),88)) or + (dbg_group26 and fanout(dbg_data_unit_sel_q(26),88)) or + (dbg_group27 and fanout(dbg_data_unit_sel_q(27),88)) or + (dbg_group28 and fanout(dbg_data_unit_sel_q(28),88)) or + (dbg_group29 and fanout(dbg_data_unit_sel_q(29),88)) or + (dbg_group30 and fanout(dbg_data_unit_sel_q(30),88)) or + (dbg_group31 and fanout(dbg_data_unit_sel_q(31),88)); + +dbg_group_rotate0 <= dbg_group_int_data(0 to 87); +dbg_group_rotate1 <= dbg_group_int_data(66 to 87) & dbg_group_int_data(0 to 65); +dbg_group_rotate2 <= dbg_group_int_data(44 to 87) & dbg_group_int_data(0 to 43); +dbg_group_rotate3 <= dbg_group_int_data(22 to 87) & dbg_group_int_data(0 to 21); +dbg_group_rotate <= gate(dbg_group_rotate0, dbg_rot_grp_sel(0)) or gate(dbg_group_rotate1, dbg_rot_grp_sel(1)) or + gate(dbg_group_rotate2, dbg_rot_grp_sel(2)) or gate(dbg_group_rotate3, dbg_rot_grp_sel(3)); + +dbg_group_pthru_data0 <= gate(dbg_group_rotate(0 to 21), dbg_data_pthru_sel(0)) or gate(debug_data_in(0 to 21), not dbg_data_pthru_sel(0)); +dbg_group_pthru_data1 <= gate(dbg_group_rotate(22 to 43), dbg_data_pthru_sel(1)) or gate(debug_data_in(22 to 43), not dbg_data_pthru_sel(1)); +dbg_group_pthru_data2 <= gate(dbg_group_rotate(44 to 65), dbg_data_pthru_sel(2)) or gate(debug_data_in(44 to 65), not dbg_data_pthru_sel(2)); +dbg_group_pthru_data3 <= gate(dbg_group_rotate(66 to 87), dbg_data_pthru_sel(3)) or gate(debug_data_in(66 to 87), not dbg_data_pthru_sel(3)); +dbg_group_pthru_data <= dbg_group_pthru_data0 & dbg_group_pthru_data1 & dbg_group_pthru_data2 & dbg_group_pthru_data3; + +debug_data_out_d <= dbg_group_pthru_data; + +dbg_group_int_trig <= gate(trg_group0, dbg_trig_grp_sel(0)) or gate(trg_group1, dbg_trig_grp_sel(1)) or gate(trg_group2, dbg_trig_grp_sel(2)) or gate(trg_group3, dbg_trig_grp_sel(3)); + +dbg_group_rot_trig0 <= dbg_group_int_trig(0 to 11); +dbg_group_rot_trig1 <= dbg_group_int_trig(6 to 11) & dbg_group_int_trig(0 to 5); +dbg_group_rot_trig <= gate(dbg_group_rot_trig0, not dbg_rot_trig_sel) or gate(dbg_group_rot_trig1, dbg_rot_trig_sel); + +dbg_group_pthru_trig0 <= gate(dbg_group_rot_trig(0 to 5), dbg_trig_pthru_sel(0)) or gate(trigger_data_in(0 to 5), not dbg_trig_pthru_sel(0)); +dbg_group_pthru_trig1 <= gate(dbg_group_rot_trig(6 to 11), dbg_trig_pthru_sel(1)) or gate(trigger_data_in(6 to 11), not dbg_trig_pthru_sel(1)); +dbg_group_pthru_trig <= dbg_group_pthru_trig0 & dbg_group_pthru_trig1; + +trigger_data_out_d <= dbg_group_pthru_trig; + +debug_data_out <= debug_data_out_q; +trigger_data_out <= trigger_data_out_q; + +dbg_data_unit_sel_gen : for g in 0 to 31 generate + dbg_data_unit_sel_latch : tri_rlmreg_p + generic map (width => dbg_data_unit_sel_q(g)'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => trace_bus_enable, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(dbg_data_unit_sel_offset+dbg_data_unit_sel_q(g)'length*g to dbg_data_unit_sel_offset + dbg_data_unit_sel_q(g)'length*(g+1)-1), + scout => sov(dbg_data_unit_sel_offset+dbg_data_unit_sel_q(g)'length*g to dbg_data_unit_sel_offset + dbg_data_unit_sel_q(g)'length*(g+1)-1), + din => dbg_data_unit_sel_d(g), + dout => dbg_data_unit_sel_q(g)); + + dbg_data_unit_sel_d(g) <= (others=>trace_unit_sel3210(g)); + +end generate; +dbg_trace_unit_sel_latch : tri_rlmreg_p +generic map (width => dbg_trace_unit_sel_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => trace_bus_enable, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(dbg_trace_unit_sel_offset to dbg_trace_unit_sel_offset + dbg_trace_unit_sel_q'length-1), + scout => sov(dbg_trace_unit_sel_offset to dbg_trace_unit_sel_offset + dbg_trace_unit_sel_q'length-1), + din => dbg_trace_unit_sel_d, + dout => dbg_trace_unit_sel_q); +trigger_data_out_latch : tri_rlmreg_p +generic map (width => trigger_data_out_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => trace_bus_enable, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(trigger_data_out_offset to trigger_data_out_offset + trigger_data_out_q'length-1), + scout => sov(trigger_data_out_offset to trigger_data_out_offset + trigger_data_out_q'length-1), + din => trigger_data_out_d, + dout => trigger_data_out_q); +debug_data_out_latch : tri_rlmreg_p +generic map (width => debug_data_out_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => trace_bus_enable, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(debug_data_out_offset to debug_data_out_offset + debug_data_out_q'length-1), + scout => sov(debug_data_out_offset to debug_data_out_offset + debug_data_out_q'length-1), + din => debug_data_out_d, + dout => debug_data_out_q); + +siv(0 to scan_right) <= sov(1 to scan_right) & scan_in; +scan_out <= sov(0); + +end architecture xuq_debug_mux32; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_dec_a.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_dec_a.vhdl new file mode 100644 index 0000000..8ed2445 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_dec_a.vhdl @@ -0,0 +1,2568 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.numeric_std.all; +LIBRARY ibm; +USE ibm.std_ulogic_support.all; +USE ibm.std_ulogic_function_support.all; +LIBRARY support; +USE support.power_logic_pkg.all; +LIBRARY tri; +USE tri.tri_latches_pkg.all; +LIBRARY work; +USE work.xuq_pkg.all; + +entity xuq_dec_a is + generic( + expand_type : integer := 2; + threads : integer := 4; + regmode : integer := 6; + regsize : integer := 63; + real_data_add : integer := 42; + eff_ifar : integer := 62); + port( + nclk : in clk_logic; + + vdd : inout power_logic; + gnd : inout power_logic; + + d_mode_dc : in std_ulogic; + delay_lclkr_dc : in std_ulogic; + mpw1_dc_b : in std_ulogic; + mpw2_dc_b : in std_ulogic; + func_sl_force : in std_ulogic; + func_sl_thold_0_b : in std_ulogic; + sg_0 : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + iu_xu_is2_vld : in std_ulogic; + iu_xu_is2_ifar : in std_ulogic_vector(62-eff_ifar to 61); + iu_xu_is2_tid : in std_ulogic_vector(0 to threads-1); + iu_xu_is2_instr : in std_ulogic_vector(0 to 31); + iu_xu_is2_ta_vld : in std_ulogic; + iu_xu_is2_ta : in std_ulogic_vector(0 to 5); + iu_xu_is2_s1_vld : in std_ulogic; + iu_xu_is2_s1 : in std_ulogic_vector(0 to 5); + iu_xu_is2_s2_vld : in std_ulogic; + iu_xu_is2_s2 : in std_ulogic_vector(0 to 5); + iu_xu_is2_s3_vld : in std_ulogic; + iu_xu_is2_s3 : in std_ulogic_vector(0 to 5); + iu_xu_is2_axu_ld_or_st : in std_ulogic; + iu_xu_is2_axu_store : in std_ulogic; + iu_xu_is2_axu_ldst_size : in std_ulogic_vector(0 to 5); + iu_xu_is2_axu_ldst_update : in std_ulogic; + iu_xu_is2_axu_ldst_forcealign : in std_ulogic; + iu_xu_is2_axu_ldst_forceexcept : in std_ulogic; + iu_xu_is2_axu_ldst_extpid : in std_ulogic; + iu_xu_is2_axu_ldst_indexed : in std_ulogic; + iu_xu_is2_axu_ldst_tag : in std_ulogic_vector(0 to 8); + iu_xu_is2_axu_mftgpr : in std_ulogic; + iu_xu_is2_axu_mffgpr : in std_ulogic; + iu_xu_is2_axu_movedp : in std_ulogic; + iu_xu_is2_axu_instr_type : in std_ulogic_vector(0 to 2); + iu_xu_is2_pred_update : in std_ulogic; + iu_xu_is2_pred_taken_cnt : in std_ulogic_vector(0 to 1); + iu_xu_is2_error : in std_ulogic_vector(0 to 2); + iu_xu_is2_match : in std_ulogic; + iu_xu_is2_is_ucode : in std_ulogic; + iu_xu_is2_ucode_vld : in std_ulogic; + iu_xu_is2_gshare : in std_ulogic_vector(0 to 3); + xu_div_barr_done : out std_ulogic_vector(0 to threads-1); + xu_div_coll_barr_done : out std_ulogic_vector(0 to threads-1); + + dec_gpr_rf0_re0 : out std_ulogic; + dec_gpr_rf0_re1 : out std_ulogic; + dec_gpr_rf0_re2 : out std_ulogic; + dec_gpr_rf0_ra0 : out std_ulogic_vector(0 to 7); + dec_gpr_rf0_ra1 : out std_ulogic_vector(0 to 7); + dec_gpr_rf0_ra2 : out std_ulogic_vector(0 to 7); + dec_gpr_rel_ta_gpr : out std_ulogic_vector(0 to 7); + dec_gpr_rel_wren : out std_ulogic; + + fxa_fxb_rf0_val : out std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_issued : out std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_ucode_val : out std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_act : out std_ulogic; + fxa_fxb_ex1_hold_ctr_flush : out std_ulogic; + fxa_fxb_rf0_instr : out std_ulogic_vector(0 to 31); + fxa_fxb_rf0_tid : out std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_ta_vld : out std_ulogic; + fxa_fxb_rf0_ta : out std_ulogic_vector(0 to 7); + fxa_fxb_rf0_error : out std_ulogic_vector(0 to 2); + fxa_fxb_rf0_match : out std_ulogic; + fxa_fxb_rf0_is_ucode : out std_ulogic; + fxa_fxb_rf0_gshare : out std_ulogic_vector(0 to 3); + fxa_fxb_rf0_ifar : out std_ulogic_vector(62-eff_ifar to 61); + fxa_fxb_rf0_s1_vld : out std_ulogic; + fxa_fxb_rf0_s1 : out std_ulogic_vector(0 to 7); + fxa_fxb_rf0_s2_vld : out std_ulogic; + fxa_fxb_rf0_s2 : out std_ulogic_vector(0 to 7); + fxa_fxb_rf0_s3_vld : out std_ulogic; + fxa_fxb_rf0_s3 : out std_ulogic_vector(0 to 7); + fxa_fxb_rf0_axu_instr_type : out std_ulogic_vector(0 to 2); + fxa_fxb_rf0_axu_ld_or_st : out std_ulogic; + fxa_fxb_rf0_axu_store : out std_ulogic; + fxa_fxb_rf0_axu_ldst_forcealign : out std_ulogic; + fxa_fxb_rf0_axu_ldst_forceexcept : out std_ulogic; + fxa_fxb_rf0_axu_ldst_indexed : out std_ulogic; + fxa_fxb_rf0_axu_ldst_tag : out std_ulogic_vector(0 to 8); + fxa_fxb_rf0_axu_mftgpr : out std_ulogic; + fxa_fxb_rf0_axu_mffgpr : out std_ulogic; + fxa_fxb_rf0_axu_movedp : out std_ulogic; + fxa_fxb_rf0_axu_ldst_size : out std_ulogic_vector(0 to 5); + fxa_fxb_rf0_axu_ldst_update : out std_ulogic; + fxa_fxb_rf0_pred_update : out std_ulogic; + fxa_fxb_rf0_pred_taken_cnt : out std_ulogic_vector(0 to 1); + fxa_fxb_rf0_mc_dep_chk_val : out std_ulogic_vector(0 to threads-1); + fxa_fxb_rf1_mul_val : out std_ulogic; + fxa_fxb_rf1_muldiv_coll : out std_ulogic; + fxa_fxb_rf1_div_val : out std_ulogic; + fxa_fxb_rf1_div_ctr : out std_ulogic_vector(0 to 7); + fxa_fxb_rf0_xu_epid_instr : out std_ulogic; + fxa_fxb_rf0_axu_is_extload : out std_ulogic; + fxa_fxb_rf0_axu_is_extstore : out std_ulogic; + fxa_fxb_rf0_spr_tid : out std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_cpl_tid : out std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_cpl_act : out std_ulogic; + fxa_fxb_rf0_is_mfocrf : out std_ulogic; + fxa_fxb_rf0_3src_instr : out std_ulogic; + fxa_fxb_rf0_gpr0_zero : out std_ulogic; + fxa_fxb_rf0_use_imm : out std_ulogic; + dec_cpl_ex3_mc_dep_chk_val : out std_ulogic_vector(0 to threads-1); + fxa_cpl_ex2_div_coll : out std_ulogic_vector(0 to threads-1); + cpl_fxa_ex5_set_barr : in std_ulogic_vector(0 to threads-1); + fxa_iu_set_barr_tid : out std_ulogic_vector(0 to threads-1); + spr_xucr4_div_barr_thres : in std_ulogic_vector(0 to 7); + fxa_perf_muldiv_in_use : out std_ulogic; + + xu_is2_flush : in std_ulogic_vector(0 to threads-1); + xu_rf0_flush : in std_ulogic_vector(0 to threads-1); + xu_rf1_flush : in std_ulogic_vector(0 to threads-1); + xu_ex1_flush : in std_ulogic_vector(0 to threads-1); + xu_ex2_flush : in std_ulogic_vector(0 to threads-1); + xu_ex3_flush : in std_ulogic_vector(0 to threads-1); + xu_ex4_flush : in std_ulogic_vector(0 to threads-1); + xu_ex5_flush : in std_ulogic_vector(0 to threads-1); + + an_ac_back_inv : in std_ulogic; + an_ac_back_inv_addr : in std_ulogic_vector(62 to 63); + an_ac_back_inv_target_bit3 : in std_ulogic; + + dec_spr_rf0_instr : out std_ulogic_vector(0 to 31); + spr_xucr0_clkg_ctl_b0 : in std_ulogic; + + xu_lsu_rf0_derat_is_extload : out std_ulogic; + xu_lsu_rf0_derat_is_extstore : out std_ulogic; + xu_lsu_rf0_derat_val : out std_ulogic_vector(0 to threads-1); + lsu_xu_rel_wren : in std_ulogic; + lsu_xu_rel_ta_gpr : in std_ulogic_vector(0 to 7); + + dec_debug : out std_ulogic_vector(0 to 175) + ); +end xuq_dec_a; +ARCHITECTURE XUQ_DEC_A + OF XUQ_DEC_A + IS +SIGNAL TBL_3SRC_DEC_PT : STD_ULOGIC_VECTOR(1 TO 15) := +(OTHERS=> 'U'); +SIGNAL TBL_GPR0_ZERO_PT : STD_ULOGIC_VECTOR(1 TO 33) := +(OTHERS=> 'U'); +SIGNAL TBL_RF0_DEC_PT : STD_ULOGIC_VECTOR(1 TO 11) := +(OTHERS=> 'U'); +SIGNAL TBL_RF0_EPID_DEC_PT : STD_ULOGIC_VECTOR(1 TO 9) := +(OTHERS=> 'U'); +SIGNAL TBL_USE_IMM_PT : STD_ULOGIC_VECTOR(1 TO 15) := +(OTHERS=> 'U'); +subtype s2 is std_ulogic_vector(0 to 1); +subtype s3 is std_ulogic_vector(0 to 2); +constant tiup : std_ulogic := '1'; +constant tidn : std_ulogic := '0'; +signal rf0_axu_instr_type_q : std_ulogic_vector(0 to 2); +signal rf0_axu_ld_or_st_q : std_ulogic; +signal rf0_axu_ldst_extpid_q : std_ulogic; +signal rf0_axu_ldst_forcealign_q : std_ulogic; +signal rf0_axu_ldst_forceexcept_q : std_ulogic; +signal rf0_axu_ldst_indexed_q : std_ulogic; +signal rf0_axu_ldst_size_q : std_ulogic_vector(0 to 5); +signal rf0_axu_ldst_tag_q : std_ulogic_vector(0 to 8); +signal rf0_axu_ldst_update_q : std_ulogic; +signal rf0_axu_mffgpr_q : std_ulogic; +signal rf0_axu_mftgpr_q : std_ulogic; +signal rf0_axu_movedp_q : std_ulogic; +signal rf0_axu_store_q : std_ulogic; +signal rf0_error_q : std_ulogic_vector(0 to 2); +signal rf0_gshare_q : std_ulogic_vector(0 to 3); +signal rf0_ifar_q : std_ulogic_vector(62-eff_ifar to 61); +signal rf0_instr_q : std_ulogic_vector(0 to 31); +signal rf0_is_ucode_q : std_ulogic; +signal rf0_match_q : std_ulogic; +signal rf0_pred_taken_cnt_q : std_ulogic_vector(0 to 1); +signal rf0_pred_update_q : std_ulogic; +signal rf0_s1_q : std_ulogic_vector(0 to 5); +signal rf0_s1_vld_q, rf0_s1_vld_d : std_ulogic; +signal rf0_s2_q : std_ulogic_vector(0 to 5); +signal rf0_s2_vld_q, rf0_s2_vld_d : std_ulogic; +signal rf0_s3_q : std_ulogic_vector(0 to 5); +signal rf0_s3_vld_q, rf0_s3_vld_d : std_ulogic; +signal rf0_ta_q : std_ulogic_vector(0 to 5); +signal rf0_ta_vld_q, rf0_ta_vld_d : std_ulogic; +signal rf0_tid_q : std_ulogic_vector(0 to threads-1); +signal rf0_ucode_val_q, rf0_ucode_val_d : std_ulogic_vector(0 to threads-1); +signal rf0_val_q, rf0_val_d : std_ulogic_vector(0 to threads-1); +signal rf1_barrier_done_q, rf0_barrier_done : std_ulogic; +signal rf1_div_coll_q, rf1_div_coll_d : std_ulogic; +signal rf1_div_val_q, rf0_div_val : std_ulogic_vector(0 to threads-1); +signal rf1_mul_valid_q, rf0_mul_valid : std_ulogic; +signal rf1_muldiv_coll_q, rf0_muldiv_coll : std_ulogic; +signal rf1_multdiv_val_q, rf0_multdiv_val : std_ulogic_vector(0 to threads-1); +signal rf1_recirc_ctr_q, rf1_recirc_ctr_d : std_ulogic_vector(0 to 7); +signal rf1_recirc_ctr_flush_q, rf0_recirc_ctr_flush : std_ulogic; +signal ex1_div_coll_q, ex1_div_coll_d : std_ulogic; +signal ex1_div_val_q, ex1_div_val_d : std_ulogic_vector(0 to threads-1); +signal ex1_muldiv_in_use_q : std_ulogic; +signal ex1_multdiv_val_q, ex1_multdiv_val_d : std_ulogic_vector(0 to threads-1); +signal ex1_recirc_ctr_flush_q : std_ulogic; +signal ex2_div_coll_q, ex2_div_coll_d : std_ulogic; +signal ex2_div_val_q, ex2_div_val_d : std_ulogic_vector(0 to threads-1); +signal ex2_multdiv_val_q, ex2_multdiv_val_d : std_ulogic_vector(0 to threads-1); +signal ex3_div_val_q, ex3_div_val_d : std_ulogic_vector(0 to threads-1); +signal ex3_multdiv_val_q, ex3_multdiv_val_d : std_ulogic_vector(0 to threads-1); +signal ex4_div_val_q, ex4_div_val_d : std_ulogic_vector(0 to threads-1); +signal ex5_div_val_q, ex5_div_val_d : std_ulogic_vector(0 to threads-1); +signal ex6_div_barr_val_q : std_ulogic; +signal ex6_set_barr_q, ex5_set_barr : std_ulogic_vector(0 to threads-1); +signal an_ac_back_inv_q : std_ulogic; +signal an_ac_back_inv_addr_q : std_ulogic_vector(62 to 63); +signal an_ac_back_inv_target_bit3_q : std_ulogic; +signal back_inv_val_q, back_inv_val_d : std_ulogic; +signal coll_tid_q, coll_tid_d : std_ulogic_vector(0 to threads-1); +signal div_barr_done_q, div_barr_done_d : std_ulogic_vector(0 to threads-1); +signal div_barr_thres_q : std_ulogic_vector(0 to 7); +signal div_coll_barr_done_q, div_coll_barr_done_d : std_ulogic_vector(0 to threads-1); +signal hold_divide_q : std_ulogic; +signal hold_error_q, hold_error_d : std_ulogic_vector(0 to 2); +signal hold_ifar_q, hold_ifar_d : std_ulogic_vector(62-eff_ifar to 61); +signal hold_instr_q, hold_instr_d : std_ulogic_vector(0 to 31); +signal hold_is_ucode_q, hold_is_ucode_d : std_ulogic; +signal hold_match_q, hold_match_d : std_ulogic; +signal hold_s1_q, hold_s1_d : std_ulogic_vector(0 to 7); +signal hold_s1_vld_q, hold_s1_vld_d : std_ulogic; +signal hold_s2_q, hold_s2_d : std_ulogic_vector(0 to 7); +signal hold_s2_vld_q, hold_s2_vld_d : std_ulogic; +signal hold_s3_q, hold_s3_d : std_ulogic_vector(0 to 7); +signal hold_s3_vld_q, hold_s3_vld_d : std_ulogic; +signal hold_ta_q, hold_ta_d : std_ulogic_vector(0 to 7); +signal hold_ta_vld_q, hold_ta_vld_d : std_ulogic; +signal hold_tid_q, hold_tid_d : std_ulogic_vector(0 to threads-1); +signal hold_use_imm_q, hold_use_imm_d : std_ulogic; +signal lsu_xu_rel_ta_gpr_q : std_ulogic_vector(0 to 7); +signal lsu_xu_rel_wren_q : std_ulogic; +signal spare_0_q, spare_0_d : std_ulogic_vector(0 to 15); +signal spare_1_q, spare_1_d : std_ulogic_vector(0 to 15); +constant rf0_axu_instr_type_offset : integer := 0; +constant rf0_axu_ld_or_st_offset : integer := rf0_axu_instr_type_offset + rf0_axu_instr_type_q'length; +constant rf0_axu_ldst_extpid_offset : integer := rf0_axu_ld_or_st_offset + 1; +constant rf0_axu_ldst_forcealign_offset : integer := rf0_axu_ldst_extpid_offset + 1; +constant rf0_axu_ldst_forceexcept_offset : integer := rf0_axu_ldst_forcealign_offset + 1; +constant rf0_axu_ldst_indexed_offset : integer := rf0_axu_ldst_forceexcept_offset + 1; +constant rf0_axu_ldst_size_offset : integer := rf0_axu_ldst_indexed_offset + 1; +constant rf0_axu_ldst_tag_offset : integer := rf0_axu_ldst_size_offset + rf0_axu_ldst_size_q'length; +constant rf0_axu_ldst_update_offset : integer := rf0_axu_ldst_tag_offset + rf0_axu_ldst_tag_q'length; +constant rf0_axu_mffgpr_offset : integer := rf0_axu_ldst_update_offset + 1; +constant rf0_axu_mftgpr_offset : integer := rf0_axu_mffgpr_offset + 1; +constant rf0_axu_movedp_offset : integer := rf0_axu_mftgpr_offset + 1; +constant rf0_axu_store_offset : integer := rf0_axu_movedp_offset + 1; +constant rf0_error_offset : integer := rf0_axu_store_offset + 1; +constant rf0_gshare_offset : integer := rf0_error_offset + rf0_error_q'length; +constant rf0_ifar_offset : integer := rf0_gshare_offset + rf0_gshare_q'length; +constant rf0_instr_offset : integer := rf0_ifar_offset + rf0_ifar_q'length; +constant rf0_is_ucode_offset : integer := rf0_instr_offset + rf0_instr_q'length; +constant rf0_match_offset : integer := rf0_is_ucode_offset + 1; +constant rf0_pred_taken_cnt_offset : integer := rf0_match_offset + 1; +constant rf0_pred_update_offset : integer := rf0_pred_taken_cnt_offset + rf0_pred_taken_cnt_q'length; +constant rf0_s1_offset : integer := rf0_pred_update_offset + 1; +constant rf0_s1_vld_offset : integer := rf0_s1_offset + rf0_s1_q'length; +constant rf0_s2_offset : integer := rf0_s1_vld_offset + 1; +constant rf0_s2_vld_offset : integer := rf0_s2_offset + rf0_s2_q'length; +constant rf0_s3_offset : integer := rf0_s2_vld_offset + 1; +constant rf0_s3_vld_offset : integer := rf0_s3_offset + rf0_s3_q'length; +constant rf0_ta_offset : integer := rf0_s3_vld_offset + 1; +constant rf0_ta_vld_offset : integer := rf0_ta_offset + rf0_ta_q'length; +constant rf0_tid_offset : integer := rf0_ta_vld_offset + 1; +constant rf0_ucode_val_offset : integer := rf0_tid_offset + rf0_tid_q'length; +constant rf0_val_offset : integer := rf0_ucode_val_offset + rf0_ucode_val_q'length; +constant rf1_barrier_done_offset : integer := rf0_val_offset + rf0_val_q'length; +constant rf1_div_coll_offset : integer := rf1_barrier_done_offset + 1; +constant rf1_div_val_offset : integer := rf1_div_coll_offset + 1; +constant rf1_mul_valid_offset : integer := rf1_div_val_offset + rf1_div_val_q'length; +constant rf1_muldiv_coll_offset : integer := rf1_mul_valid_offset + 1; +constant rf1_multdiv_val_offset : integer := rf1_muldiv_coll_offset + 1; +constant rf1_recirc_ctr_offset : integer := rf1_multdiv_val_offset + rf1_multdiv_val_q'length; +constant rf1_recirc_ctr_flush_offset : integer := rf1_recirc_ctr_offset + rf1_recirc_ctr_q'length; +constant ex1_div_coll_offset : integer := rf1_recirc_ctr_flush_offset + 1; +constant ex1_div_val_offset : integer := ex1_div_coll_offset + 1; +constant ex1_muldiv_in_use_offset : integer := ex1_div_val_offset + ex1_div_val_q'length; +constant ex1_multdiv_val_offset : integer := ex1_muldiv_in_use_offset + 1; +constant ex1_recirc_ctr_flush_offset : integer := ex1_multdiv_val_offset + ex1_multdiv_val_q'length; +constant ex2_div_coll_offset : integer := ex1_recirc_ctr_flush_offset + 1; +constant ex2_div_val_offset : integer := ex2_div_coll_offset + 1; +constant ex2_multdiv_val_offset : integer := ex2_div_val_offset + ex2_div_val_q'length; +constant ex3_div_val_offset : integer := ex2_multdiv_val_offset + ex2_multdiv_val_q'length; +constant ex3_multdiv_val_offset : integer := ex3_div_val_offset + ex3_div_val_q'length; +constant ex4_div_val_offset : integer := ex3_multdiv_val_offset + ex3_multdiv_val_q'length; +constant ex5_div_val_offset : integer := ex4_div_val_offset + ex4_div_val_q'length; +constant ex6_div_barr_val_offset : integer := ex5_div_val_offset + ex5_div_val_q'length; +constant ex6_set_barr_offset : integer := ex6_div_barr_val_offset + 1; +constant an_ac_back_inv_offset : integer := ex6_set_barr_offset + ex6_set_barr_q'length; +constant an_ac_back_inv_addr_offset : integer := an_ac_back_inv_offset + 1; +constant an_ac_back_inv_target_bit3_offset : integer := an_ac_back_inv_addr_offset + an_ac_back_inv_addr_q'length; +constant back_inv_val_offset : integer := an_ac_back_inv_target_bit3_offset + 1; +constant coll_tid_offset : integer := back_inv_val_offset + 1; +constant div_barr_done_offset : integer := coll_tid_offset + coll_tid_q'length; +constant div_barr_thres_offset : integer := div_barr_done_offset + div_barr_done_q'length; +constant div_coll_barr_done_offset : integer := div_barr_thres_offset + div_barr_thres_q'length; +constant hold_divide_offset : integer := div_coll_barr_done_offset + div_coll_barr_done_q'length; +constant hold_error_offset : integer := hold_divide_offset + 1; +constant hold_ifar_offset : integer := hold_error_offset + hold_error_q'length; +constant hold_instr_offset : integer := hold_ifar_offset + hold_ifar_q'length; +constant hold_is_ucode_offset : integer := hold_instr_offset + hold_instr_q'length; +constant hold_match_offset : integer := hold_is_ucode_offset + 1; +constant hold_s1_offset : integer := hold_match_offset + 1; +constant hold_s1_vld_offset : integer := hold_s1_offset + hold_s1_q'length; +constant hold_s2_offset : integer := hold_s1_vld_offset + 1; +constant hold_s2_vld_offset : integer := hold_s2_offset + hold_s2_q'length; +constant hold_s3_offset : integer := hold_s2_vld_offset + 1; +constant hold_s3_vld_offset : integer := hold_s3_offset + hold_s3_q'length; +constant hold_ta_offset : integer := hold_s3_vld_offset + 1; +constant hold_ta_vld_offset : integer := hold_ta_offset + hold_ta_q'length; +constant hold_tid_offset : integer := hold_ta_vld_offset + 1; +constant hold_use_imm_offset : integer := hold_tid_offset + hold_tid_q'length; +constant lsu_xu_rel_ta_gpr_offset : integer := hold_use_imm_offset + 1; +constant lsu_xu_rel_wren_offset : integer := lsu_xu_rel_ta_gpr_offset + lsu_xu_rel_ta_gpr_q'length; +constant spare_0_offset : integer := lsu_xu_rel_wren_offset + 1; +constant spare_1_offset : integer := spare_0_offset + spare_0_q'length; +constant scan_right : integer := spare_1_offset + spare_1_q'length; +signal siv : std_ulogic_vector(0 to scan_right-1); +signal sov : std_ulogic_vector(0 to scan_right-1); +signal spare_0_lclk : clk_logic; +signal spare_1_lclk : clk_logic; +signal spare_0_d1clk, spare_0_d2clk : std_ulogic; +signal spare_1_d1clk, spare_1_d2clk : std_ulogic; +signal rf0_is_mfocrf : std_ulogic; +signal rf0_valid : std_ulogic; +signal rf0_hold_latch_act : std_ulogic; +signal rf0_multicyc_op : std_ulogic; +signal rf0_singlcyc_op : std_ulogic; +signal rf0_recirc_ctr_init : std_ulogic_vector(0 to 7); +signal rf0_recirc_ctr_done : std_ulogic; +signal rf0_recirc_ctr_start : std_ulogic; +signal rf0_divide, rf0_multiply : std_ulogic; +signal rf0_muldiv_in_use, rf1_muldiv_in_use : std_ulogic; +signal rf0_div_coll : std_ulogic; +signal rf0_derat_is_extload, rf0_derat_is_extstore : std_ulogic; +signal rf0_axu_is_extload, rf0_axu_is_extstore : std_ulogic; +signal rf0_thread_num : std_ulogic_vector(0 to 1); +signal icswx_val : std_ulogic_vector(0 to threads-1); +signal icswx_thrd_dec : std_ulogic_vector(0 to threads-1); +signal rf0_3source_instr : std_ulogic; +signal rf0_gpr0_zero : std_ulogic; +signal rf0_axu_gpr0_zero : std_ulogic; +signal ex5_div_barr_val : std_ulogic; +signal rf0_recirc_ctr_dec : std_ulogic_vector(0 to 7); +signal rf0_recirc_ctr_clear : std_ulogic; +signal rf1_barrier_en : std_ulogic; +signal rf1_barrier_done : std_ulogic_vector(0 to threads-1); +signal rf0_div_valid : std_ulogic; +signal ex5_div_val : std_ulogic_vector(0 to threads-1); +signal rf1_hold_tid_flush : std_ulogic; +signal rf0_tid : std_ulogic_vector(0 to threads-1); +signal rf0_use_imm : std_ulogic; +signal is2_act : std_ulogic; +signal rf0_instr : std_ulogic_vector(0 to 31); + BEGIN + +fxa_fxb_rf0_spr_tid <= rf0_tid or rf0_ucode_val_q; +fxa_fxb_rf0_cpl_act <= or_reduce(rf0_tid or rf0_ucode_val_q); +fxa_fxb_rf0_cpl_tid <= rf0_tid_q; +fxa_fxb_rf0_is_mfocrf <= rf0_is_mfocrf; +fxa_fxb_rf0_3src_instr <= rf0_3source_instr and not rf0_recirc_ctr_done; +fxa_fxb_rf0_gpr0_zero <= (rf0_gpr0_zero or rf0_axu_gpr0_zero) and not rf0_recirc_ctr_done; +rf0_axu_gpr0_zero <= rf0_axu_ld_or_st_q and not or_reduce(rf0_s1_q); +dec_spr_rf0_instr <= rf0_instr; +fxa_fxb_rf0_instr <= rf0_instr; +mark_unused(spr_xucr0_clkg_ctl_b0); +is2_act <= '1'; +rf0_ucode_val_d <= iu_xu_is2_tid and (0 to threads-1=>iu_xu_is2_ucode_vld) and not xu_is2_flush; +rf0_val_d <= iu_xu_is2_tid and (0 to threads-1=>iu_xu_is2_vld) and not xu_is2_flush; +rf0_ta_vld_d <= iu_xu_is2_ta_vld and or_reduce(iu_xu_is2_tid and (0 to threads-1=> iu_xu_is2_vld) and not xu_is2_flush); +rf0_s1_vld_d <= iu_xu_is2_s1_vld and or_reduce(iu_xu_is2_tid and (0 to threads-1=>(iu_xu_is2_vld or iu_xu_is2_ucode_vld)) and not xu_is2_flush); +rf0_s2_vld_d <= iu_xu_is2_s2_vld and or_reduce(iu_xu_is2_tid and (0 to threads-1=>(iu_xu_is2_vld or iu_xu_is2_ucode_vld)) and not xu_is2_flush); +rf0_s3_vld_d <= iu_xu_is2_s3_vld and or_reduce(iu_xu_is2_tid and (0 to threads-1=>(iu_xu_is2_vld or iu_xu_is2_ucode_vld)) and not xu_is2_flush); + WITH s2'(rf0_recirc_ctr_start & rf0_recirc_ctr_done) SELECT fxa_fxb_rf0_val <= "0000" when "10", + hold_tid_q and not xu_rf0_flush when "01", + rf0_val_q and not xu_rf0_flush when others; + WITH s2'(rf0_recirc_ctr_start & (rf0_recirc_ctr_done or rf0_recirc_ctr_flush)) SELECT fxa_fxb_rf0_issued <= "0000" when "10", + hold_tid_q when "01", + (rf0_val_q or rf0_ucode_val_q) when others; + WITH s2'(rf0_recirc_ctr_start & rf0_recirc_ctr_done) SELECT fxa_fxb_rf0_ta_vld <= '0' when "10", + hold_ta_vld_q when "01", + rf0_ta_vld_q when others; +fxa_fxb_rf0_ucode_val <= rf0_ucode_val_q and not xu_rf0_flush; +fxa_fxb_rf0_act <= or_reduce(rf0_val_q) or or_reduce(rf0_ucode_val_q) or rf0_recirc_ctr_done; + WITH rf0_tid_q(0 to 3) SELECT rf0_thread_num <= "11" when "0001", + "10" when "0010", + "01" when "0100", + "00" when others; +rf0_valid <= or_reduce(rf0_val_q and not xu_rf0_flush); +rf1_muldiv_in_use <= or_reduce(rf1_recirc_ctr_q); +rf0_muldiv_in_use <= rf1_muldiv_in_use or rf0_recirc_ctr_start; +fxa_perf_muldiv_in_use <= ex1_muldiv_in_use_q; +rf1_hold_tid_flush <= or_reduce(hold_tid_q and xu_rf1_flush); +rf0_recirc_ctr_flush <= rf1_muldiv_in_use and rf1_hold_tid_flush; +rf0_recirc_ctr_clear <= rf0_recirc_ctr_flush or not (rf0_muldiv_in_use); +rf0_recirc_ctr_start <= rf0_valid and not rf1_muldiv_in_use and rf0_multicyc_op; +rf0_muldiv_coll <= rf0_valid and rf1_muldiv_in_use and (rf0_multicyc_op or rf0_singlcyc_op); +rf0_div_coll <= rf0_muldiv_coll and rf0_divide; +with rf0_recirc_ctr_start select + rf0_recirc_ctr_dec <= rf0_recirc_ctr_init when '1', + std_ulogic_vector(unsigned(rf1_recirc_ctr_q) - 1) when others; +with rf0_recirc_ctr_clear select + rf1_recirc_ctr_d <= (others=>'0') when '1', + rf0_recirc_ctr_dec when others; +rf0_recirc_ctr_done <= '1' when (rf1_recirc_ctr_q = "00000001") else '0'; +rf0_barrier_done <= hold_divide_q and (rf0_recirc_ctr_done or (rf0_recirc_ctr_flush and ex5_div_barr_val)); +rf1_barrier_done <= (others=>rf1_barrier_done_q); +fxa_iu_set_barr_tid <= ex6_set_barr_q; +ex5_set_barr <= gate(cpl_fxa_ex5_set_barr,rf1_muldiv_in_use); +coll_tid_d <= (coll_tid_q or ex5_set_barr) and not rf1_barrier_done; +div_coll_barr_done_d <= (coll_tid_q or ex5_set_barr) and not (0 to threads-1=>rf1_muldiv_in_use); +div_barr_done_d <= (hold_tid_q and rf1_barrier_done) or + icswx_val; +xu_div_coll_barr_done <= div_coll_barr_done_q; +xu_div_barr_done <= div_barr_done_q; +rf0_hold_latch_act <= rf0_recirc_ctr_start; +rf0_mul_valid <= rf0_valid and rf0_multiply and not rf1_muldiv_in_use; +rf0_div_valid <= rf0_valid and rf0_divide and not rf1_muldiv_in_use; +fxa_fxb_rf1_div_val <= or_reduce(rf1_div_val_q); +fxa_fxb_rf1_mul_val <= rf1_mul_valid_q; +fxa_fxb_rf1_div_ctr <= rf1_recirc_ctr_q; +fxa_fxb_ex1_hold_ctr_flush <= ex1_recirc_ctr_flush_q; +rf1_barrier_en <= '1' when (rf1_recirc_ctr_q > div_barr_thres_q) else '0'; +rf1_div_coll_d <= rf0_div_coll and or_reduce(rf0_tid_q and not coll_tid_q) and not rf1_hold_tid_flush; +ex1_div_coll_d <= rf1_div_coll_q and rf1_barrier_en and hold_divide_q and not rf1_hold_tid_flush; +ex2_div_coll_d <= ex1_div_coll_q and not rf1_hold_tid_flush; +fxa_cpl_ex2_div_coll <= gate(hold_tid_q,ex2_div_coll_q); +fxa_fxb_rf1_muldiv_coll <= rf1_muldiv_coll_q; +rf0_div_val <= gate(rf0_val_q,rf0_div_valid); +ex1_div_val_d <= rf1_div_val_q and not xu_rf1_flush; +ex2_div_val_d <= ex1_div_val_q and not xu_ex1_flush; +ex3_div_val_d <= ex2_div_val_q and not xu_ex2_flush; +ex4_div_val_d <= ex3_div_val_q and not xu_ex3_flush; +ex5_div_val_d <= ex4_div_val_q and not xu_ex4_flush; +ex5_div_val <= ex5_div_val_q and not xu_ex5_flush; +ex5_div_barr_val <= (or_reduce(ex5_div_val)) or + (ex6_div_barr_val_q and rf1_muldiv_in_use); +rf0_multdiv_val <= gate(rf0_val_q,rf0_recirc_ctr_start); +ex1_multdiv_val_d <= rf1_multdiv_val_q and not xu_rf1_flush; +ex2_multdiv_val_d <= ex1_multdiv_val_q and not xu_ex1_flush; +ex3_multdiv_val_d <= ex2_multdiv_val_q and not xu_ex2_flush; +fxa_fxb_rf0_mc_dep_chk_val <= rf0_multdiv_val; +dec_cpl_ex3_mc_dep_chk_val <= ex3_multdiv_val_q; +hold_tid_d <= rf0_tid_q; +hold_instr_d <= rf0_instr_q; +hold_ta_vld_d <= rf0_ta_vld_q; +hold_ta_d <= rf0_ta_q & rf0_thread_num; +hold_error_d <= rf0_error_q; +hold_match_d <= rf0_match_q; +hold_is_ucode_d <= rf0_is_ucode_q; +hold_ifar_d <= rf0_ifar_q; +hold_s1_d <= rf0_s1_q & rf0_thread_num; +hold_s2_d <= rf0_s2_q & rf0_thread_num; +hold_s3_d <= rf0_s3_q & rf0_thread_num; +hold_s1_vld_d <= rf0_s1_vld_q; +hold_s2_vld_d <= rf0_s2_vld_q; +hold_s3_vld_d <= rf0_s3_vld_q; +hold_use_imm_d <= rf0_use_imm; +with rf0_recirc_ctr_done select + fxa_fxb_rf0_tid <= (rf0_val_q or rf0_ucode_val_q) when '0', + hold_tid_q when others; +with rf0_recirc_ctr_done select + rf0_instr <= rf0_instr_q when '0', + hold_instr_q when others; +with rf0_recirc_ctr_done select + rf0_tid <= rf0_tid_q when '0', + hold_tid_q when others; +with rf0_recirc_ctr_done select + fxa_fxb_rf0_ta <= rf0_ta_q & rf0_thread_num when '0', + hold_ta_q when others; +with rf0_recirc_ctr_done select + fxa_fxb_rf0_error <= rf0_error_q when '0', + hold_error_q when others; +with rf0_recirc_ctr_done select + fxa_fxb_rf0_match <= rf0_match_q when '0', + hold_match_q when others; +with rf0_recirc_ctr_done select + fxa_fxb_rf0_is_ucode <= rf0_is_ucode_q when '0', + hold_is_ucode_q when others; +with rf0_recirc_ctr_done select + fxa_fxb_rf0_ifar <= rf0_ifar_q when '0', + hold_ifar_q when others; +with rf0_recirc_ctr_done select + fxa_fxb_rf0_s1 <= rf0_s1_q & rf0_thread_num when '0', + hold_s1_q when others; +with rf0_recirc_ctr_done select + fxa_fxb_rf0_s2 <= rf0_s2_q & rf0_thread_num when '0', + hold_s2_q when others; +with rf0_recirc_ctr_done select + fxa_fxb_rf0_s3 <= rf0_s3_q & rf0_thread_num when '0', + hold_s3_q when others; +with rf0_recirc_ctr_done select + fxa_fxb_rf0_s1_vld <= rf0_s1_vld_q when '0', + hold_s1_vld_q when others; +with rf0_recirc_ctr_done select + fxa_fxb_rf0_s2_vld <= rf0_s2_vld_q when '0', + hold_s2_vld_q when others; +with rf0_recirc_ctr_done select + fxa_fxb_rf0_s3_vld <= rf0_s3_vld_q when '0', + hold_s3_vld_q when others; +with rf0_recirc_ctr_done select + fxa_fxb_rf0_use_imm <= rf0_use_imm when '0', + hold_use_imm_q when others; +fxa_fxb_rf0_axu_ld_or_st <= rf0_axu_ld_or_st_q and not rf0_recirc_ctr_done; +fxa_fxb_rf0_axu_store <= rf0_axu_store_q and not rf0_recirc_ctr_done; +fxa_fxb_rf0_axu_mftgpr <= rf0_axu_mftgpr_q and not rf0_recirc_ctr_done; +fxa_fxb_rf0_axu_mffgpr <= rf0_axu_mffgpr_q and not rf0_recirc_ctr_done; +fxa_fxb_rf0_axu_movedp <= rf0_axu_movedp_q and not rf0_recirc_ctr_done; +fxa_fxb_rf0_pred_update <= rf0_pred_update_q and not rf0_recirc_ctr_done; +fxa_fxb_rf0_gshare <= rf0_gshare_q; +fxa_fxb_rf0_axu_instr_type <= rf0_axu_instr_type_q; +fxa_fxb_rf0_axu_ldst_forcealign <= rf0_axu_ldst_forcealign_q; +fxa_fxb_rf0_axu_ldst_forceexcept <= rf0_axu_ldst_forceexcept_q; +fxa_fxb_rf0_axu_ldst_indexed <= rf0_axu_ldst_indexed_q; +fxa_fxb_rf0_axu_ldst_tag <= rf0_axu_ldst_tag_q; +fxa_fxb_rf0_axu_ldst_size <= rf0_axu_ldst_size_q; +fxa_fxb_rf0_axu_ldst_update <= rf0_axu_ldst_update_q; +fxa_fxb_rf0_pred_taken_cnt <= rf0_pred_taken_cnt_q; + WITH an_ac_back_inv_addr_q(62 to 63) SELECT icswx_thrd_dec <= "1000" when "00", + "0100" when "01", + "0010" when "10", + "0001" when others; +back_inv_val_d <= an_ac_back_inv_q and an_ac_back_inv_target_bit3_q; +icswx_val <= gate(icswx_thrd_dec, back_inv_val_q); +dec_gpr_rf0_re0 <= rf0_s1_vld_q; +dec_gpr_rf0_re1 <= rf0_s2_vld_q; +dec_gpr_rf0_re2 <= rf0_s3_vld_q; +dec_gpr_rf0_ra0 <= rf0_s1_q & rf0_thread_num; +dec_gpr_rf0_ra1 <= rf0_s2_q & rf0_thread_num; +dec_gpr_rf0_ra2 <= rf0_s3_q & rf0_thread_num; +dec_gpr_rel_wren <= lsu_xu_rel_wren_q; +dec_gpr_rel_ta_gpr <= lsu_xu_rel_ta_gpr_q; +rf0_axu_is_extload <= rf0_axu_ldst_extpid_q and ((rf0_axu_ld_or_st_q and not (rf0_axu_mftgpr_q or rf0_axu_mffgpr_q)) and not rf0_axu_store_q); +rf0_axu_is_extstore <= rf0_axu_ldst_extpid_q and ((rf0_axu_ld_or_st_q and not (rf0_axu_mftgpr_q or rf0_axu_mffgpr_q)) and rf0_axu_store_q); +xu_lsu_rf0_derat_is_extload <= rf0_derat_is_extload or rf0_axu_is_extload; +xu_lsu_rf0_derat_is_extstore <= rf0_derat_is_extstore or rf0_axu_is_extstore; +fxa_fxb_rf0_xu_epid_instr <= not rf0_recirc_ctr_done and (rf0_derat_is_extload or rf0_derat_is_extstore); +fxa_fxb_rf0_axu_is_extload <= not rf0_recirc_ctr_done and rf0_axu_is_extload; +fxa_fxb_rf0_axu_is_extstore <= not rf0_recirc_ctr_done and rf0_axu_is_extstore; +xu_lsu_rf0_derat_val <= rf0_val_q or rf0_ucode_val_q; +dec_debug(0 TO 87) <= rf0_val_q & + rf0_instr_q(0 to 5) & + rf0_instr_q(21 to 30) & + hold_instr_q(0 to 5) & + hold_instr_q(21 to 30) & + rf0_ta_vld_q & + rf0_s1_vld_q & + rf0_s2_vld_q & + rf0_s3_vld_q & + xu_rf0_flush & + hold_ta_vld_q & + ex1_recirc_ctr_flush_q & + rf0_recirc_ctr_start & + rf0_recirc_ctr_done & + rf1_recirc_ctr_q & + hold_tid_q & + rf0_divide & + rf0_multiply & + rf1_barrier_done_q & + ex6_set_barr_q & + coll_tid_q & + div_coll_barr_done_q & + div_barr_done_q & + rf1_muldiv_coll_q & + rf1_div_coll_q & + ex1_div_coll_q & + cpl_fxa_ex5_set_barr & + ex5_div_barr_val & + back_inv_val_q; +dec_debug(88 TO 175) <= rf0_val_q & + rf0_instr_q & + rf0_ta_q & + rf0_error_q & + rf0_match_q & + rf0_is_ucode_q & + rf0_s1_vld_q & + rf0_s2_vld_q & + rf0_s3_vld_q & + rf0_axu_ld_or_st_q & + rf0_axu_store_q & + rf0_axu_mftgpr_q & + rf0_axu_mffgpr_q & + rf0_axu_movedp_q & + rf0_pred_update_q & + rf0_gshare_q & + rf0_axu_instr_type_q & + rf0_axu_ldst_forcealign_q & + rf0_axu_ldst_forceexcept_q & + rf0_axu_ldst_indexed_q & + rf0_axu_ldst_tag_q & + rf0_axu_ldst_size_q & + rf0_axu_ldst_update_q & + rf0_pred_taken_cnt_q & + rf0_recirc_ctr_done & + rf0_recirc_ctr_start & + rf1_muldiv_coll_q & + back_inv_val_q; +MQQ1:TBL_RF0_DEC_PT(1) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(11) & RF0_INSTR_Q(21) & + RF0_INSTR_Q(22) & RF0_INSTR_Q(23) & + RF0_INSTR_Q(24) & RF0_INSTR_Q(25) & + RF0_INSTR_Q(26) & RF0_INSTR_Q(27) & + RF0_INSTR_Q(28) & RF0_INSTR_Q(29) & + RF0_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("01111110000010011")); +MQQ2:TBL_RF0_DEC_PT(2) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(21) & RF0_INSTR_Q(23) & + RF0_INSTR_Q(24) & RF0_INSTR_Q(25) & + RF0_INSTR_Q(26) & RF0_INSTR_Q(27) & + RF0_INSTR_Q(28) & RF0_INSTR_Q(29) & + RF0_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111111101001")); +MQQ3:TBL_RF0_DEC_PT(3) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(22) & RF0_INSTR_Q(23) & + RF0_INSTR_Q(24) & RF0_INSTR_Q(25) & + RF0_INSTR_Q(26) & RF0_INSTR_Q(27) & + RF0_INSTR_Q(28) & RF0_INSTR_Q(29) & + RF0_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111011101011")); +MQQ4:TBL_RF0_DEC_PT(4) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(22) & RF0_INSTR_Q(23) & + RF0_INSTR_Q(25) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111100001011")); +MQQ5:TBL_RF0_DEC_PT(5) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(22) & RF0_INSTR_Q(23) & + RF0_INSTR_Q(24) & RF0_INSTR_Q(25) & + RF0_INSTR_Q(26) & RF0_INSTR_Q(27) & + RF0_INSTR_Q(28) & RF0_INSTR_Q(29) & + RF0_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111011101001")); +MQQ6:TBL_RF0_DEC_PT(6) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(22) & RF0_INSTR_Q(23) & + RF0_INSTR_Q(24) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111111001001")); +MQQ7:TBL_RF0_DEC_PT(7) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(22) & RF0_INSTR_Q(23) & + RF0_INSTR_Q(25) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111100001001")); +MQQ8:TBL_RF0_DEC_PT(8) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(22) & RF0_INSTR_Q(23) & + RF0_INSTR_Q(24) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111111001011")); +MQQ9:TBL_RF0_DEC_PT(9) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(22) & RF0_INSTR_Q(23) & + RF0_INSTR_Q(24) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111111101011")); +MQQ10:TBL_RF0_DEC_PT(10) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(22) & RF0_INSTR_Q(23) & + RF0_INSTR_Q(24) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111111101001")); +MQQ11:TBL_RF0_DEC_PT(11) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) + ) , STD_ULOGIC_VECTOR'("000111")); +MQQ12:RF0_RECIRC_CTR_INIT(0) <= + (TBL_RF0_DEC_PT(6)); +MQQ13:RF0_RECIRC_CTR_INIT(1) <= + (TBL_RF0_DEC_PT(8) OR TBL_RF0_DEC_PT(10) + ); +MQQ14:RF0_RECIRC_CTR_INIT(2) <= + (TBL_RF0_DEC_PT(9)); +MQQ15:RF0_RECIRC_CTR_INIT(3) <= + ('0'); +MQQ16:RF0_RECIRC_CTR_INIT(4) <= + ('0'); +MQQ17:RF0_RECIRC_CTR_INIT(5) <= + ('0'); +MQQ18:RF0_RECIRC_CTR_INIT(6) <= + (TBL_RF0_DEC_PT(5) OR TBL_RF0_DEC_PT(7) + ); +MQQ19:RF0_RECIRC_CTR_INIT(7) <= + (TBL_RF0_DEC_PT(2) OR TBL_RF0_DEC_PT(6) + OR TBL_RF0_DEC_PT(7) OR TBL_RF0_DEC_PT(8) + OR TBL_RF0_DEC_PT(9) OR TBL_RF0_DEC_PT(10) + OR TBL_RF0_DEC_PT(11)); +MQQ20:RF0_SINGLCYC_OP <= + (TBL_RF0_DEC_PT(3) OR TBL_RF0_DEC_PT(4) + ); +MQQ21:RF0_MULTICYC_OP <= + (TBL_RF0_DEC_PT(5) OR TBL_RF0_DEC_PT(6) + OR TBL_RF0_DEC_PT(7) OR TBL_RF0_DEC_PT(8) + OR TBL_RF0_DEC_PT(9) OR TBL_RF0_DEC_PT(10) + OR TBL_RF0_DEC_PT(11)); +MQQ22:RF0_DIVIDE <= + (TBL_RF0_DEC_PT(6) OR TBL_RF0_DEC_PT(8) + OR TBL_RF0_DEC_PT(9) OR TBL_RF0_DEC_PT(10) + ); +MQQ23:RF0_MULTIPLY <= + (TBL_RF0_DEC_PT(3) OR TBL_RF0_DEC_PT(4) + OR TBL_RF0_DEC_PT(5) OR TBL_RF0_DEC_PT(7) + OR TBL_RF0_DEC_PT(11)); +MQQ24:RF0_IS_MFOCRF <= + (TBL_RF0_DEC_PT(1)); + +MQQ25:TBL_RF0_EPID_DEC_PT(1) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(21) & RF0_INSTR_Q(22) & + RF0_INSTR_Q(23) & RF0_INSTR_Q(24) & + RF0_INSTR_Q(25) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111111110110110")); +MQQ26:TBL_RF0_EPID_DEC_PT(2) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(21) & RF0_INSTR_Q(22) & + RF0_INSTR_Q(23) & RF0_INSTR_Q(24) & + RF0_INSTR_Q(25) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111111111111111")); +MQQ27:TBL_RF0_EPID_DEC_PT(3) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(21) & RF0_INSTR_Q(22) & + RF0_INSTR_Q(23) & RF0_INSTR_Q(24) & + RF0_INSTR_Q(25) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111111111011111")); +MQQ28:TBL_RF0_EPID_DEC_PT(4) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(21) & RF0_INSTR_Q(22) & + RF0_INSTR_Q(23) & RF0_INSTR_Q(24) & + RF0_INSTR_Q(25) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111000001111")); +MQQ29:TBL_RF0_EPID_DEC_PT(5) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(21) & RF0_INSTR_Q(22) & + RF0_INSTR_Q(23) & RF0_INSTR_Q(24) & + RF0_INSTR_Q(25) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111001001111")); +MQQ30:TBL_RF0_EPID_DEC_PT(6) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(21) & RF0_INSTR_Q(23) & + RF0_INSTR_Q(24) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111100011111")); +MQQ31:TBL_RF0_EPID_DEC_PT(7) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(21) & RF0_INSTR_Q(22) & + RF0_INSTR_Q(23) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111100011111")); +MQQ32:TBL_RF0_EPID_DEC_PT(8) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(21) & RF0_INSTR_Q(22) & + RF0_INSTR_Q(23) & RF0_INSTR_Q(24) & + RF0_INSTR_Q(26) & RF0_INSTR_Q(27) & + RF0_INSTR_Q(28) & RF0_INSTR_Q(29) & + RF0_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111001111111")); +MQQ33:TBL_RF0_EPID_DEC_PT(9) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(21) & RF0_INSTR_Q(23) & + RF0_INSTR_Q(24) & RF0_INSTR_Q(25) & + RF0_INSTR_Q(26) & RF0_INSTR_Q(27) & + RF0_INSTR_Q(28) & RF0_INSTR_Q(29) & + RF0_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111010011111")); +MQQ34:RF0_DERAT_IS_EXTLOAD <= + (TBL_RF0_EPID_DEC_PT(3) OR TBL_RF0_EPID_DEC_PT(4) + OR TBL_RF0_EPID_DEC_PT(6) OR TBL_RF0_EPID_DEC_PT(7) + ); +MQQ35:RF0_DERAT_IS_EXTSTORE <= + (TBL_RF0_EPID_DEC_PT(1) OR TBL_RF0_EPID_DEC_PT(2) + OR TBL_RF0_EPID_DEC_PT(5) OR TBL_RF0_EPID_DEC_PT(8) + OR TBL_RF0_EPID_DEC_PT(9)); + +MQQ36:TBL_3SRC_DEC_PT(1) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(21) & RF0_INSTR_Q(23) & + RF0_INSTR_Q(24) & RF0_INSTR_Q(25) & + RF0_INSTR_Q(26) & RF0_INSTR_Q(27) & + RF0_INSTR_Q(28) & RF0_INSTR_Q(29) + ) , STD_ULOGIC_VECTOR'("01111101001011")); +MQQ37:TBL_3SRC_DEC_PT(2) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(21) & RF0_INSTR_Q(22) & + RF0_INSTR_Q(23) & RF0_INSTR_Q(24) & + RF0_INSTR_Q(25) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111111111010010")); +MQQ38:TBL_3SRC_DEC_PT(3) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(21) & RF0_INSTR_Q(22) & + RF0_INSTR_Q(23) & RF0_INSTR_Q(24) & + RF0_INSTR_Q(26) & RF0_INSTR_Q(27) & + RF0_INSTR_Q(28) & RF0_INSTR_Q(29) & + RF0_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111111010110")); +MQQ39:TBL_3SRC_DEC_PT(4) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(21) & RF0_INSTR_Q(22) & + RF0_INSTR_Q(23) & RF0_INSTR_Q(24) & + RF0_INSTR_Q(25) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111101001010")); +MQQ40:TBL_3SRC_DEC_PT(5) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(21) & RF0_INSTR_Q(22) & + RF0_INSTR_Q(23) & RF0_INSTR_Q(24) & + RF0_INSTR_Q(25) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(28) & RF0_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111100100111")); +MQQ41:TBL_3SRC_DEC_PT(6) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(21) & RF0_INSTR_Q(22) & + RF0_INSTR_Q(23) & RF0_INSTR_Q(24) & + RF0_INSTR_Q(26) & RF0_INSTR_Q(27) & + RF0_INSTR_Q(28) & RF0_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111100101011")); +MQQ42:TBL_3SRC_DEC_PT(7) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(21) & RF0_INSTR_Q(22) & + RF0_INSTR_Q(23) & RF0_INSTR_Q(25) & + RF0_INSTR_Q(26) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111100101111")); +MQQ43:TBL_3SRC_DEC_PT(8) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(21) & RF0_INSTR_Q(22) & + RF0_INSTR_Q(23) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111100110111")); +MQQ44:TBL_3SRC_DEC_PT(9) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(21) & RF0_INSTR_Q(23) & + RF0_INSTR_Q(24) & RF0_INSTR_Q(25) & + RF0_INSTR_Q(26) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111101001111")); +MQQ45:TBL_3SRC_DEC_PT(10) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(21) & RF0_INSTR_Q(23) & + RF0_INSTR_Q(24) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111101010111")); +MQQ46:TBL_3SRC_DEC_PT(11) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(21) & RF0_INSTR_Q(22) & + RF0_INSTR_Q(23) & RF0_INSTR_Q(25) & + RF0_INSTR_Q(26) & RF0_INSTR_Q(27) & + RF0_INSTR_Q(28) & RF0_INSTR_Q(29) + ) , STD_ULOGIC_VECTOR'("01111100101011")); +MQQ47:TBL_3SRC_DEC_PT(12) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) + ) , STD_ULOGIC_VECTOR'("1010")); +MQQ48:TBL_3SRC_DEC_PT(13) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("1111100")); +MQQ49:TBL_3SRC_DEC_PT(14) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) + ) , STD_ULOGIC_VECTOR'("1001")); +MQQ50:TBL_3SRC_DEC_PT(15) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(05) + ) , STD_ULOGIC_VECTOR'("1011")); +MQQ51:RF0_3SOURCE_INSTR <= + (TBL_3SRC_DEC_PT(1) OR TBL_3SRC_DEC_PT(2) + OR TBL_3SRC_DEC_PT(3) OR TBL_3SRC_DEC_PT(4) + OR TBL_3SRC_DEC_PT(5) OR TBL_3SRC_DEC_PT(6) + OR TBL_3SRC_DEC_PT(7) OR TBL_3SRC_DEC_PT(8) + OR TBL_3SRC_DEC_PT(9) OR TBL_3SRC_DEC_PT(10) + OR TBL_3SRC_DEC_PT(11) OR TBL_3SRC_DEC_PT(12) + OR TBL_3SRC_DEC_PT(13) OR TBL_3SRC_DEC_PT(14) + OR TBL_3SRC_DEC_PT(15)); + +MQQ52:TBL_GPR0_ZERO_PT(1) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) & + RF0_INSTR_Q(05) & RF0_INSTR_Q(21) & + RF0_INSTR_Q(22) & RF0_INSTR_Q(23) & + RF0_INSTR_Q(24) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) & + RF0_S1_Q(00) & RF0_S1_Q(01) & + RF0_S1_Q(02) & RF0_S1_Q(03) & + RF0_S1_Q(04) & RF0_S1_Q(05) + ) , STD_ULOGIC_VECTOR'("01111001000110000000")); +MQQ53:TBL_GPR0_ZERO_PT(2) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) & + RF0_INSTR_Q(05) & RF0_INSTR_Q(21) & + RF0_INSTR_Q(22) & RF0_INSTR_Q(23) & + RF0_INSTR_Q(24) & RF0_INSTR_Q(25) & + RF0_INSTR_Q(26) & RF0_INSTR_Q(27) & + RF0_INSTR_Q(28) & RF0_S1_Q(00) & + RF0_S1_Q(01) & RF0_S1_Q(02) & + RF0_S1_Q(03) & RF0_S1_Q(04) & + RF0_S1_Q(05) ) , STD_ULOGIC_VECTOR'("0111100000101000000")); +MQQ54:TBL_GPR0_ZERO_PT(3) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) & + RF0_INSTR_Q(05) & RF0_INSTR_Q(21) & + RF0_INSTR_Q(24) & RF0_INSTR_Q(25) & + RF0_INSTR_Q(26) & RF0_INSTR_Q(27) & + RF0_INSTR_Q(28) & RF0_INSTR_Q(29) & + RF0_S1_Q(00) & RF0_S1_Q(01) & + RF0_S1_Q(02) & RF0_S1_Q(03) & + RF0_S1_Q(04) & RF0_S1_Q(05) + ) , STD_ULOGIC_VECTOR'("011110001011000000")); +MQQ55:TBL_GPR0_ZERO_PT(4) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) & + RF0_INSTR_Q(05) & RF0_INSTR_Q(21) & + RF0_INSTR_Q(22) & RF0_INSTR_Q(23) & + RF0_INSTR_Q(24) & RF0_INSTR_Q(25) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) & + RF0_S1_Q(00) & RF0_S1_Q(01) & + RF0_S1_Q(02) & RF0_S1_Q(03) & + RF0_S1_Q(04) & RF0_S1_Q(05) + ) , STD_ULOGIC_VECTOR'("01111001110110000000")); +MQQ56:TBL_GPR0_ZERO_PT(5) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) & + RF0_INSTR_Q(05) & RF0_INSTR_Q(21) & + RF0_INSTR_Q(23) & RF0_INSTR_Q(24) & + RF0_INSTR_Q(25) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) & + RF0_S1_Q(00) & RF0_S1_Q(01) & + RF0_S1_Q(02) & RF0_S1_Q(03) & + RF0_S1_Q(04) & RF0_S1_Q(05) + ) , STD_ULOGIC_VECTOR'("01111111110110000000")); +MQQ57:TBL_GPR0_ZERO_PT(6) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) & + RF0_INSTR_Q(05) & RF0_INSTR_Q(21) & + RF0_INSTR_Q(22) & RF0_INSTR_Q(25) & + RF0_INSTR_Q(26) & RF0_INSTR_Q(27) & + RF0_INSTR_Q(28) & RF0_INSTR_Q(29) & + RF0_S1_Q(00) & RF0_S1_Q(01) & + RF0_S1_Q(02) & RF0_S1_Q(03) & + RF0_S1_Q(04) & RF0_S1_Q(05) + ) , STD_ULOGIC_VECTOR'("011110001011000000")); +MQQ58:TBL_GPR0_ZERO_PT(7) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) & + RF0_INSTR_Q(05) & RF0_INSTR_Q(21) & + RF0_INSTR_Q(24) & RF0_INSTR_Q(25) & + RF0_INSTR_Q(26) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) & + RF0_S1_Q(00) & RF0_S1_Q(01) & + RF0_S1_Q(02) & RF0_S1_Q(03) & + RF0_S1_Q(04) & RF0_S1_Q(05) + ) , STD_ULOGIC_VECTOR'("011110001111000000")); +MQQ59:TBL_GPR0_ZERO_PT(8) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) & + RF0_INSTR_Q(05) & RF0_INSTR_Q(22) & + RF0_INSTR_Q(23) & RF0_INSTR_Q(25) & + RF0_INSTR_Q(26) & RF0_INSTR_Q(27) & + RF0_INSTR_Q(28) & RF0_INSTR_Q(29) & + RF0_INSTR_Q(30) & RF0_S1_Q(00) & + RF0_S1_Q(01) & RF0_S1_Q(02) & + RF0_S1_Q(03) & RF0_S1_Q(04) & + RF0_S1_Q(05) ) , STD_ULOGIC_VECTOR'("0111111010110000000")); +MQQ60:TBL_GPR0_ZERO_PT(9) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) & + RF0_INSTR_Q(05) & RF0_INSTR_Q(21) & + RF0_INSTR_Q(22) & RF0_INSTR_Q(24) & + RF0_INSTR_Q(25) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(30) & RF0_S1_Q(00) & + RF0_S1_Q(01) & RF0_S1_Q(02) & + RF0_S1_Q(03) & RF0_S1_Q(04) & + RF0_S1_Q(05) ) , STD_ULOGIC_VECTOR'("0111110001010000000")); +MQQ61:TBL_GPR0_ZERO_PT(10) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) & + RF0_INSTR_Q(05) & RF0_INSTR_Q(21) & + RF0_INSTR_Q(22) & RF0_INSTR_Q(23) & + RF0_INSTR_Q(25) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) & + RF0_S1_Q(00) & RF0_S1_Q(01) & + RF0_S1_Q(02) & RF0_S1_Q(03) & + RF0_S1_Q(04) & RF0_S1_Q(05) + ) , STD_ULOGIC_VECTOR'("01111110110011000000")); +MQQ62:TBL_GPR0_ZERO_PT(11) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) & + RF0_INSTR_Q(05) & RF0_INSTR_Q(21) & + RF0_INSTR_Q(22) & RF0_INSTR_Q(23) & + RF0_INSTR_Q(24) & RF0_INSTR_Q(25) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) & + RF0_S1_Q(00) & RF0_S1_Q(01) & + RF0_S1_Q(02) & RF0_S1_Q(03) & + RF0_S1_Q(04) & RF0_S1_Q(05) + ) , STD_ULOGIC_VECTOR'("01111111010110000000")); +MQQ63:TBL_GPR0_ZERO_PT(12) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) & + RF0_INSTR_Q(05) & RF0_INSTR_Q(21) & + RF0_INSTR_Q(22) & RF0_INSTR_Q(23) & + RF0_INSTR_Q(24) & RF0_INSTR_Q(27) & + RF0_INSTR_Q(28) & RF0_INSTR_Q(29) & + RF0_INSTR_Q(30) & RF0_S1_Q(00) & + RF0_S1_Q(01) & RF0_S1_Q(02) & + RF0_S1_Q(03) & RF0_S1_Q(04) & + RF0_S1_Q(05) ) , STD_ULOGIC_VECTOR'("0111111111111000000")); +MQQ64:TBL_GPR0_ZERO_PT(13) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) & + RF0_INSTR_Q(05) & RF0_INSTR_Q(21) & + RF0_INSTR_Q(22) & RF0_INSTR_Q(23) & + RF0_INSTR_Q(25) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) & + RF0_S1_Q(00) & RF0_S1_Q(01) & + RF0_S1_Q(02) & RF0_S1_Q(03) & + RF0_S1_Q(04) & RF0_S1_Q(05) + ) , STD_ULOGIC_VECTOR'("01111110010010000000")); +MQQ65:TBL_GPR0_ZERO_PT(14) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(21) & RF0_INSTR_Q(22) & + RF0_INSTR_Q(23) & RF0_INSTR_Q(24) & + RF0_INSTR_Q(25) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111110010100011")); +MQQ66:TBL_GPR0_ZERO_PT(15) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) & + RF0_INSTR_Q(05) & RF0_INSTR_Q(21) & + RF0_INSTR_Q(23) & RF0_INSTR_Q(24) & + RF0_INSTR_Q(25) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) & + RF0_S1_Q(00) & RF0_S1_Q(01) & + RF0_S1_Q(02) & RF0_S1_Q(03) & + RF0_S1_Q(04) & RF0_S1_Q(05) + ) , STD_ULOGIC_VECTOR'("01111011100110000000")); +MQQ67:TBL_GPR0_ZERO_PT(16) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(21) & RF0_INSTR_Q(22) & + RF0_INSTR_Q(23) & RF0_INSTR_Q(24) & + RF0_INSTR_Q(26) & RF0_INSTR_Q(27) & + RF0_INSTR_Q(28) & RF0_INSTR_Q(29) & + RF0_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111001101110")); +MQQ68:TBL_GPR0_ZERO_PT(17) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) & + RF0_INSTR_Q(05) & RF0_INSTR_Q(21) & + RF0_INSTR_Q(22) & RF0_INSTR_Q(24) & + RF0_INSTR_Q(25) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(29) & + RF0_INSTR_Q(30) & RF0_S1_Q(00) & + RF0_S1_Q(01) & RF0_S1_Q(02) & + RF0_S1_Q(03) & RF0_S1_Q(04) & + RF0_S1_Q(05) ) , STD_ULOGIC_VECTOR'("0111111001010000000")); +MQQ69:TBL_GPR0_ZERO_PT(18) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) & + RF0_INSTR_Q(05) & RF0_INSTR_Q(21) & + RF0_INSTR_Q(23) & RF0_INSTR_Q(24) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) & + RF0_S1_Q(00) & RF0_S1_Q(01) & + RF0_S1_Q(02) & RF0_S1_Q(03) & + RF0_S1_Q(04) & RF0_S1_Q(05) + ) , STD_ULOGIC_VECTOR'("011110001111000000")); +MQQ70:TBL_GPR0_ZERO_PT(19) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) & + RF0_INSTR_Q(05) & RF0_INSTR_Q(21) & + RF0_INSTR_Q(22) & RF0_INSTR_Q(23) & + RF0_INSTR_Q(24) & RF0_INSTR_Q(25) & + RF0_INSTR_Q(26) & RF0_INSTR_Q(27) & + RF0_INSTR_Q(28) & RF0_INSTR_Q(29) & + RF0_INSTR_Q(30) & RF0_S1_Q(00) & + RF0_S1_Q(01) & RF0_S1_Q(02) & + RF0_S1_Q(03) & RF0_S1_Q(04) & + RF0_S1_Q(05) ) , STD_ULOGIC_VECTOR'("011110000110011000000")); +MQQ71:TBL_GPR0_ZERO_PT(20) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) & + RF0_INSTR_Q(05) & RF0_INSTR_Q(21) & + RF0_INSTR_Q(22) & RF0_INSTR_Q(25) & + RF0_INSTR_Q(26) & RF0_INSTR_Q(27) & + RF0_INSTR_Q(28) & RF0_INSTR_Q(29) & + RF0_INSTR_Q(30) & RF0_S1_Q(00) & + RF0_S1_Q(01) & RF0_S1_Q(02) & + RF0_S1_Q(03) & RF0_S1_Q(04) & + RF0_S1_Q(05) ) , STD_ULOGIC_VECTOR'("0111110010101000000")); +MQQ72:TBL_GPR0_ZERO_PT(21) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) & + RF0_INSTR_Q(05) & RF0_INSTR_Q(21) & + RF0_INSTR_Q(22) & RF0_INSTR_Q(24) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) & + RF0_S1_Q(00) & RF0_S1_Q(01) & + RF0_S1_Q(02) & RF0_S1_Q(03) & + RF0_S1_Q(04) & RF0_S1_Q(05) + ) , STD_ULOGIC_VECTOR'("011110011111000000")); +MQQ73:TBL_GPR0_ZERO_PT(22) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) & + RF0_INSTR_Q(05) & RF0_INSTR_Q(21) & + RF0_INSTR_Q(22) & RF0_INSTR_Q(24) & + RF0_INSTR_Q(25) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(28) & RF0_INSTR_Q(30) & + RF0_S1_Q(00) & RF0_S1_Q(01) & + RF0_S1_Q(02) & RF0_S1_Q(03) & + RF0_S1_Q(04) & RF0_S1_Q(05) + ) , STD_ULOGIC_VECTOR'("011110000111000000")); +MQQ74:TBL_GPR0_ZERO_PT(23) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) & + RF0_INSTR_Q(05) & RF0_INSTR_Q(21) & + RF0_INSTR_Q(22) & RF0_INSTR_Q(23) & + RF0_INSTR_Q(24) & RF0_INSTR_Q(25) & + RF0_INSTR_Q(26) & RF0_INSTR_Q(27) & + RF0_INSTR_Q(28) & RF0_INSTR_Q(30) & + RF0_S1_Q(00) & RF0_S1_Q(01) & + RF0_S1_Q(02) & RF0_S1_Q(03) & + RF0_S1_Q(04) & RF0_S1_Q(05) + ) , STD_ULOGIC_VECTOR'("01111010101011000000")); +MQQ75:TBL_GPR0_ZERO_PT(24) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) & + RF0_INSTR_Q(05) & RF0_INSTR_Q(21) & + RF0_INSTR_Q(23) & RF0_INSTR_Q(24) & + RF0_INSTR_Q(25) & RF0_INSTR_Q(27) & + RF0_INSTR_Q(28) & RF0_INSTR_Q(29) & + RF0_INSTR_Q(30) & RF0_S1_Q(00) & + RF0_S1_Q(01) & RF0_S1_Q(02) & + RF0_S1_Q(03) & RF0_S1_Q(04) & + RF0_S1_Q(05) ) , STD_ULOGIC_VECTOR'("0111101000110000000")); +MQQ76:TBL_GPR0_ZERO_PT(25) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) & + RF0_INSTR_Q(05) & RF0_INSTR_Q(21) & + RF0_INSTR_Q(22) & RF0_INSTR_Q(24) & + RF0_INSTR_Q(25) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(30) & RF0_S1_Q(00) & + RF0_S1_Q(01) & RF0_S1_Q(02) & + RF0_S1_Q(03) & RF0_S1_Q(04) & + RF0_S1_Q(05) ) , STD_ULOGIC_VECTOR'("0111100101010000000")); +MQQ77:TBL_GPR0_ZERO_PT(26) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) & + RF0_INSTR_Q(05) & RF0_INSTR_Q(21) & + RF0_INSTR_Q(22) & RF0_INSTR_Q(23) & + RF0_INSTR_Q(24) & RF0_INSTR_Q(25) & + RF0_INSTR_Q(26) & RF0_INSTR_Q(27) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) & + RF0_S1_Q(00) & RF0_S1_Q(01) & + RF0_S1_Q(02) & RF0_S1_Q(03) & + RF0_S1_Q(04) & RF0_S1_Q(05) + ) , STD_ULOGIC_VECTOR'("01111000001010000000")); +MQQ78:TBL_GPR0_ZERO_PT(27) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) & + RF0_INSTR_Q(05) & RF0_INSTR_Q(21) & + RF0_INSTR_Q(22) & RF0_INSTR_Q(23) & + RF0_INSTR_Q(24) & RF0_INSTR_Q(25) & + RF0_INSTR_Q(26) & RF0_INSTR_Q(27) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) & + RF0_S1_Q(00) & RF0_S1_Q(01) & + RF0_S1_Q(02) & RF0_S1_Q(03) & + RF0_S1_Q(04) & RF0_S1_Q(05) + ) , STD_ULOGIC_VECTOR'("01111001001011000000")); +MQQ79:TBL_GPR0_ZERO_PT(28) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(05) & RF0_S1_Q(00) & + RF0_S1_Q(01) & RF0_S1_Q(02) & + RF0_S1_Q(03) & RF0_S1_Q(04) & + RF0_S1_Q(05) ) , STD_ULOGIC_VECTOR'("100000000")); +MQQ80:TBL_GPR0_ZERO_PT(29) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) & + RF0_INSTR_Q(05) & RF0_INSTR_Q(21) & + RF0_INSTR_Q(22) & RF0_INSTR_Q(23) & + RF0_INSTR_Q(24) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) & + RF0_S1_Q(00) & RF0_S1_Q(01) & + RF0_S1_Q(02) & RF0_S1_Q(03) & + RF0_S1_Q(04) & RF0_S1_Q(05) + ) , STD_ULOGIC_VECTOR'("01111000010110000000")); +MQQ81:TBL_GPR0_ZERO_PT(30) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) & + RF0_INSTR_Q(05) & RF0_INSTR_Q(31) & + RF0_S1_Q(00) & RF0_S1_Q(01) & + RF0_S1_Q(02) & RF0_S1_Q(03) & + RF0_S1_Q(04) & RF0_S1_Q(05) + ) , STD_ULOGIC_VECTOR'("110100000000")); +MQQ82:TBL_GPR0_ZERO_PT(31) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(30) & RF0_INSTR_Q(31) & + RF0_S1_Q(00) & RF0_S1_Q(01) & + RF0_S1_Q(02) & RF0_S1_Q(03) & + RF0_S1_Q(04) & RF0_S1_Q(05) + ) , STD_ULOGIC_VECTOR'("111000000000")); +MQQ83:TBL_GPR0_ZERO_PT(32) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) & + RF0_INSTR_Q(05) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) & + RF0_S1_Q(00) & RF0_S1_Q(01) & + RF0_S1_Q(02) & RF0_S1_Q(03) & + RF0_S1_Q(04) & RF0_S1_Q(05) + ) , STD_ULOGIC_VECTOR'("0111101111000000")); +MQQ84:TBL_GPR0_ZERO_PT(33) <= + Eq(( RF0_INSTR_Q(01) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) & + RF0_S1_Q(00) & RF0_S1_Q(01) & + RF0_S1_Q(02) & RF0_S1_Q(03) & + RF0_S1_Q(04) & RF0_S1_Q(05) + ) , STD_ULOGIC_VECTOR'("0111000000")); +MQQ85:RF0_GPR0_ZERO <= + (TBL_GPR0_ZERO_PT(1) OR TBL_GPR0_ZERO_PT(2) + OR TBL_GPR0_ZERO_PT(3) OR TBL_GPR0_ZERO_PT(4) + OR TBL_GPR0_ZERO_PT(5) OR TBL_GPR0_ZERO_PT(6) + OR TBL_GPR0_ZERO_PT(7) OR TBL_GPR0_ZERO_PT(8) + OR TBL_GPR0_ZERO_PT(9) OR TBL_GPR0_ZERO_PT(10) + OR TBL_GPR0_ZERO_PT(11) OR TBL_GPR0_ZERO_PT(12) + OR TBL_GPR0_ZERO_PT(13) OR TBL_GPR0_ZERO_PT(14) + OR TBL_GPR0_ZERO_PT(15) OR TBL_GPR0_ZERO_PT(16) + OR TBL_GPR0_ZERO_PT(17) OR TBL_GPR0_ZERO_PT(18) + OR TBL_GPR0_ZERO_PT(19) OR TBL_GPR0_ZERO_PT(20) + OR TBL_GPR0_ZERO_PT(21) OR TBL_GPR0_ZERO_PT(22) + OR TBL_GPR0_ZERO_PT(23) OR TBL_GPR0_ZERO_PT(24) + OR TBL_GPR0_ZERO_PT(25) OR TBL_GPR0_ZERO_PT(26) + OR TBL_GPR0_ZERO_PT(27) OR TBL_GPR0_ZERO_PT(28) + OR TBL_GPR0_ZERO_PT(29) OR TBL_GPR0_ZERO_PT(30) + OR TBL_GPR0_ZERO_PT(31) OR TBL_GPR0_ZERO_PT(32) + OR TBL_GPR0_ZERO_PT(33)); + +MQQ86:TBL_USE_IMM_PT(1) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(22) & RF0_INSTR_Q(24) & + RF0_INSTR_Q(25) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("011101101000")); +MQQ87:TBL_USE_IMM_PT(2) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(21) & RF0_INSTR_Q(22) & + RF0_INSTR_Q(24) & RF0_INSTR_Q(25) & + RF0_INSTR_Q(26) & RF0_INSTR_Q(27) & + RF0_INSTR_Q(28) & RF0_INSTR_Q(29) & + RF0_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("0111101010101")); +MQQ88:TBL_USE_IMM_PT(3) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(21) & RF0_INSTR_Q(22) & + RF0_INSTR_Q(23) & RF0_INSTR_Q(24) & + RF0_INSTR_Q(26) & RF0_INSTR_Q(27) & + RF0_INSTR_Q(28) & RF0_INSTR_Q(29) & + RF0_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("0111001000011")); +MQQ89:TBL_USE_IMM_PT(4) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(21) & RF0_INSTR_Q(23) & + RF0_INSTR_Q(24) & RF0_INSTR_Q(25) & + RF0_INSTR_Q(26) & RF0_INSTR_Q(27) & + RF0_INSTR_Q(28) & RF0_INSTR_Q(29) & + RF0_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("0111011010011")); +MQQ90:TBL_USE_IMM_PT(5) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(21) & RF0_INSTR_Q(22) & + RF0_INSTR_Q(23) & RF0_INSTR_Q(24) & + RF0_INSTR_Q(25) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("0111001001000")); +MQQ91:TBL_USE_IMM_PT(6) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(22) & RF0_INSTR_Q(23) & + RF0_INSTR_Q(24) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("01110110100")); +MQQ92:TBL_USE_IMM_PT(7) <= + Eq(( RF0_INSTR_Q(01) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) ) , STD_ULOGIC_VECTOR'("001")); +MQQ93:TBL_USE_IMM_PT(8) <= + Eq(( RF0_INSTR_Q(01) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(05) ) , STD_ULOGIC_VECTOR'("010")); +MQQ94:TBL_USE_IMM_PT(9) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) + ) , STD_ULOGIC_VECTOR'("0110")); +MQQ95:TBL_USE_IMM_PT(10) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) + ) , STD_ULOGIC_VECTOR'("0110")); +MQQ96:TBL_USE_IMM_PT(11) <= + Eq(( RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(31) ) , STD_ULOGIC_VECTOR'("10100")); +MQQ97:TBL_USE_IMM_PT(12) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("11100")); +MQQ98:TBL_USE_IMM_PT(13) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) + ) , STD_ULOGIC_VECTOR'("10")); +MQQ99:TBL_USE_IMM_PT(14) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(05) + ) , STD_ULOGIC_VECTOR'("0100")); +MQQ100:TBL_USE_IMM_PT(15) <= + Eq(( RF0_INSTR_Q(01) & RF0_INSTR_Q(04) & + RF0_INSTR_Q(05) ) , STD_ULOGIC_VECTOR'("011")); +MQQ101:RF0_USE_IMM <= + (TBL_USE_IMM_PT(1) OR TBL_USE_IMM_PT(2) + OR TBL_USE_IMM_PT(3) OR TBL_USE_IMM_PT(4) + OR TBL_USE_IMM_PT(5) OR TBL_USE_IMM_PT(6) + OR TBL_USE_IMM_PT(7) OR TBL_USE_IMM_PT(8) + OR TBL_USE_IMM_PT(9) OR TBL_USE_IMM_PT(10) + OR TBL_USE_IMM_PT(11) OR TBL_USE_IMM_PT(12) + OR TBL_USE_IMM_PT(13) OR TBL_USE_IMM_PT(14) + OR TBL_USE_IMM_PT(15)); + +rf0_axu_instr_type_latch : tri_rlmreg_p + generic map (width => rf0_axu_instr_type_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => is2_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_axu_instr_type_offset to rf0_axu_instr_type_offset + rf0_axu_instr_type_q'length-1), + scout => sov(rf0_axu_instr_type_offset to rf0_axu_instr_type_offset + rf0_axu_instr_type_q'length-1), + din => iu_xu_is2_axu_instr_type , + dout => rf0_axu_instr_type_q); +rf0_axu_ld_or_st_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_axu_ld_or_st_offset), + scout => sov(rf0_axu_ld_or_st_offset), + din => iu_xu_is2_axu_ld_or_st , + dout => rf0_axu_ld_or_st_q); +rf0_axu_ldst_extpid_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => is2_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_axu_ldst_extpid_offset), + scout => sov(rf0_axu_ldst_extpid_offset), + din => iu_xu_is2_axu_ldst_extpid , + dout => rf0_axu_ldst_extpid_q); +rf0_axu_ldst_forcealign_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => is2_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_axu_ldst_forcealign_offset), + scout => sov(rf0_axu_ldst_forcealign_offset), + din => iu_xu_is2_axu_ldst_forcealign, + dout => rf0_axu_ldst_forcealign_q); +rf0_axu_ldst_forceexcept_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => is2_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_axu_ldst_forceexcept_offset), + scout => sov(rf0_axu_ldst_forceexcept_offset), + din => iu_xu_is2_axu_ldst_forceexcept, + dout => rf0_axu_ldst_forceexcept_q); +rf0_axu_ldst_indexed_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => is2_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_axu_ldst_indexed_offset), + scout => sov(rf0_axu_ldst_indexed_offset), + din => iu_xu_is2_axu_ldst_indexed , + dout => rf0_axu_ldst_indexed_q); +rf0_axu_ldst_size_latch : tri_rlmreg_p + generic map (width => rf0_axu_ldst_size_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => is2_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_axu_ldst_size_offset to rf0_axu_ldst_size_offset + rf0_axu_ldst_size_q'length-1), + scout => sov(rf0_axu_ldst_size_offset to rf0_axu_ldst_size_offset + rf0_axu_ldst_size_q'length-1), + din => iu_xu_is2_axu_ldst_size , + dout => rf0_axu_ldst_size_q); +rf0_axu_ldst_tag_latch : tri_rlmreg_p + generic map (width => rf0_axu_ldst_tag_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => is2_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_axu_ldst_tag_offset to rf0_axu_ldst_tag_offset + rf0_axu_ldst_tag_q'length-1), + scout => sov(rf0_axu_ldst_tag_offset to rf0_axu_ldst_tag_offset + rf0_axu_ldst_tag_q'length-1), + din => iu_xu_is2_axu_ldst_tag , + dout => rf0_axu_ldst_tag_q); +rf0_axu_ldst_update_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => is2_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_axu_ldst_update_offset), + scout => sov(rf0_axu_ldst_update_offset), + din => iu_xu_is2_axu_ldst_update , + dout => rf0_axu_ldst_update_q); +rf0_axu_mffgpr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => is2_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_axu_mffgpr_offset), + scout => sov(rf0_axu_mffgpr_offset), + din => iu_xu_is2_axu_mffgpr , + dout => rf0_axu_mffgpr_q); +rf0_axu_mftgpr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => is2_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_axu_mftgpr_offset), + scout => sov(rf0_axu_mftgpr_offset), + din => iu_xu_is2_axu_mftgpr , + dout => rf0_axu_mftgpr_q); +rf0_axu_movedp_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => is2_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_axu_movedp_offset), + scout => sov(rf0_axu_movedp_offset), + din => iu_xu_is2_axu_movedp , + dout => rf0_axu_movedp_q); +rf0_axu_store_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => is2_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_axu_store_offset), + scout => sov(rf0_axu_store_offset), + din => iu_xu_is2_axu_store , + dout => rf0_axu_store_q); +rf0_error_latch : tri_rlmreg_p + generic map (width => rf0_error_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => is2_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_error_offset to rf0_error_offset + rf0_error_q'length-1), + scout => sov(rf0_error_offset to rf0_error_offset + rf0_error_q'length-1), + din => iu_xu_is2_error , + dout => rf0_error_q); +rf0_gshare_latch : tri_rlmreg_p + generic map (width => rf0_gshare_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => is2_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_gshare_offset to rf0_gshare_offset + rf0_gshare_q'length-1), + scout => sov(rf0_gshare_offset to rf0_gshare_offset + rf0_gshare_q'length-1), + din => iu_xu_is2_gshare , + dout => rf0_gshare_q); +rf0_ifar_latch : tri_rlmreg_p + generic map (width => rf0_ifar_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => is2_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_ifar_offset to rf0_ifar_offset + rf0_ifar_q'length-1), + scout => sov(rf0_ifar_offset to rf0_ifar_offset + rf0_ifar_q'length-1), + din => iu_xu_is2_ifar , + dout => rf0_ifar_q); +rf0_instr_latch : tri_rlmreg_p + generic map (width => rf0_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => is2_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_instr_offset to rf0_instr_offset + rf0_instr_q'length-1), + scout => sov(rf0_instr_offset to rf0_instr_offset + rf0_instr_q'length-1), + din => iu_xu_is2_instr , + dout => rf0_instr_q); +rf0_is_ucode_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => is2_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_is_ucode_offset), + scout => sov(rf0_is_ucode_offset), + din => iu_xu_is2_is_ucode , + dout => rf0_is_ucode_q); +rf0_match_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => is2_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_match_offset), + scout => sov(rf0_match_offset), + din => iu_xu_is2_match , + dout => rf0_match_q); +rf0_pred_taken_cnt_latch : tri_rlmreg_p + generic map (width => rf0_pred_taken_cnt_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => is2_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_pred_taken_cnt_offset to rf0_pred_taken_cnt_offset + rf0_pred_taken_cnt_q'length-1), + scout => sov(rf0_pred_taken_cnt_offset to rf0_pred_taken_cnt_offset + rf0_pred_taken_cnt_q'length-1), + din => iu_xu_is2_pred_taken_cnt , + dout => rf0_pred_taken_cnt_q); +rf0_pred_update_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => is2_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_pred_update_offset), + scout => sov(rf0_pred_update_offset), + din => iu_xu_is2_pred_update , + dout => rf0_pred_update_q); +rf0_s1_latch : tri_rlmreg_p + generic map (width => rf0_s1_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => is2_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_s1_offset to rf0_s1_offset + rf0_s1_q'length-1), + scout => sov(rf0_s1_offset to rf0_s1_offset + rf0_s1_q'length-1), + din => iu_xu_is2_s1 , + dout => rf0_s1_q); +rf0_s1_vld_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => is2_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_s1_vld_offset), + scout => sov(rf0_s1_vld_offset), + din => rf0_s1_vld_d, + dout => rf0_s1_vld_q); +rf0_s2_latch : tri_rlmreg_p + generic map (width => rf0_s2_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => is2_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_s2_offset to rf0_s2_offset + rf0_s2_q'length-1), + scout => sov(rf0_s2_offset to rf0_s2_offset + rf0_s2_q'length-1), + din => iu_xu_is2_s2 , + dout => rf0_s2_q); +rf0_s2_vld_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => is2_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_s2_vld_offset), + scout => sov(rf0_s2_vld_offset), + din => rf0_s2_vld_d, + dout => rf0_s2_vld_q); +rf0_s3_latch : tri_rlmreg_p + generic map (width => rf0_s3_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => is2_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_s3_offset to rf0_s3_offset + rf0_s3_q'length-1), + scout => sov(rf0_s3_offset to rf0_s3_offset + rf0_s3_q'length-1), + din => iu_xu_is2_s3 , + dout => rf0_s3_q); +rf0_s3_vld_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => is2_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_s3_vld_offset), + scout => sov(rf0_s3_vld_offset), + din => rf0_s3_vld_d, + dout => rf0_s3_vld_q); +rf0_ta_latch : tri_rlmreg_p + generic map (width => rf0_ta_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => is2_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_ta_offset to rf0_ta_offset + rf0_ta_q'length-1), + scout => sov(rf0_ta_offset to rf0_ta_offset + rf0_ta_q'length-1), + din => iu_xu_is2_ta , + dout => rf0_ta_q); +rf0_ta_vld_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => is2_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_ta_vld_offset), + scout => sov(rf0_ta_vld_offset), + din => rf0_ta_vld_d, + dout => rf0_ta_vld_q); +rf0_tid_latch : tri_rlmreg_p + generic map (width => rf0_tid_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => is2_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_tid_offset to rf0_tid_offset + rf0_tid_q'length-1), + scout => sov(rf0_tid_offset to rf0_tid_offset + rf0_tid_q'length-1), + din => iu_xu_is2_tid , + dout => rf0_tid_q); +rf0_ucode_val_latch : tri_rlmreg_p + generic map (width => rf0_ucode_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_ucode_val_offset to rf0_ucode_val_offset + rf0_ucode_val_q'length-1), + scout => sov(rf0_ucode_val_offset to rf0_ucode_val_offset + rf0_ucode_val_q'length-1), + din => rf0_ucode_val_d, + dout => rf0_ucode_val_q); +rf0_val_latch : tri_rlmreg_p + generic map (width => rf0_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_val_offset to rf0_val_offset + rf0_val_q'length-1), + scout => sov(rf0_val_offset to rf0_val_offset + rf0_val_q'length-1), + din => rf0_val_d, + dout => rf0_val_q); +rf1_barrier_done_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf1_barrier_done_offset), + scout => sov(rf1_barrier_done_offset), + din => rf0_barrier_done, + dout => rf1_barrier_done_q); +rf1_div_coll_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf1_div_coll_offset), + scout => sov(rf1_div_coll_offset), + din => rf1_div_coll_d, + dout => rf1_div_coll_q); +rf1_div_val_latch : tri_rlmreg_p + generic map (width => rf1_div_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf1_div_val_offset to rf1_div_val_offset + rf1_div_val_q'length-1), + scout => sov(rf1_div_val_offset to rf1_div_val_offset + rf1_div_val_q'length-1), + din => rf0_div_val, + dout => rf1_div_val_q); +rf1_mul_valid_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf1_mul_valid_offset), + scout => sov(rf1_mul_valid_offset), + din => rf0_mul_valid, + dout => rf1_mul_valid_q); +rf1_muldiv_coll_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf1_muldiv_coll_offset), + scout => sov(rf1_muldiv_coll_offset), + din => rf0_muldiv_coll, + dout => rf1_muldiv_coll_q); +rf1_multdiv_val_latch : tri_rlmreg_p + generic map (width => rf1_multdiv_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf1_multdiv_val_offset to rf1_multdiv_val_offset + rf1_multdiv_val_q'length-1), + scout => sov(rf1_multdiv_val_offset to rf1_multdiv_val_offset + rf1_multdiv_val_q'length-1), + din => rf0_multdiv_val, + dout => rf1_multdiv_val_q); +rf1_recirc_ctr_latch : tri_rlmreg_p + generic map (width => rf1_recirc_ctr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf1_recirc_ctr_offset to rf1_recirc_ctr_offset + rf1_recirc_ctr_q'length-1), + scout => sov(rf1_recirc_ctr_offset to rf1_recirc_ctr_offset + rf1_recirc_ctr_q'length-1), + din => rf1_recirc_ctr_d, + dout => rf1_recirc_ctr_q); +rf1_recirc_ctr_flush_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf1_recirc_ctr_flush_offset), + scout => sov(rf1_recirc_ctr_flush_offset), + din => rf0_recirc_ctr_flush, + dout => rf1_recirc_ctr_flush_q); +ex1_div_coll_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_div_coll_offset), + scout => sov(ex1_div_coll_offset), + din => ex1_div_coll_d, + dout => ex1_div_coll_q); +ex1_div_val_latch : tri_rlmreg_p + generic map (width => ex1_div_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_div_val_offset to ex1_div_val_offset + ex1_div_val_q'length-1), + scout => sov(ex1_div_val_offset to ex1_div_val_offset + ex1_div_val_q'length-1), + din => ex1_div_val_d, + dout => ex1_div_val_q); +ex1_muldiv_in_use_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_muldiv_in_use_offset), + scout => sov(ex1_muldiv_in_use_offset), + din => rf1_muldiv_in_use , + dout => ex1_muldiv_in_use_q); +ex1_multdiv_val_latch : tri_rlmreg_p + generic map (width => ex1_multdiv_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_multdiv_val_offset to ex1_multdiv_val_offset + ex1_multdiv_val_q'length-1), + scout => sov(ex1_multdiv_val_offset to ex1_multdiv_val_offset + ex1_multdiv_val_q'length-1), + din => ex1_multdiv_val_d, + dout => ex1_multdiv_val_q); +ex1_recirc_ctr_flush_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_recirc_ctr_flush_offset), + scout => sov(ex1_recirc_ctr_flush_offset), + din => rf1_recirc_ctr_flush_q , + dout => ex1_recirc_ctr_flush_q); +ex2_div_coll_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_div_coll_offset), + scout => sov(ex2_div_coll_offset), + din => ex2_div_coll_d, + dout => ex2_div_coll_q); +ex2_div_val_latch : tri_rlmreg_p + generic map (width => ex2_div_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_div_val_offset to ex2_div_val_offset + ex2_div_val_q'length-1), + scout => sov(ex2_div_val_offset to ex2_div_val_offset + ex2_div_val_q'length-1), + din => ex2_div_val_d, + dout => ex2_div_val_q); +ex2_multdiv_val_latch : tri_rlmreg_p + generic map (width => ex2_multdiv_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_multdiv_val_offset to ex2_multdiv_val_offset + ex2_multdiv_val_q'length-1), + scout => sov(ex2_multdiv_val_offset to ex2_multdiv_val_offset + ex2_multdiv_val_q'length-1), + din => ex2_multdiv_val_d, + dout => ex2_multdiv_val_q); +ex3_div_val_latch : tri_rlmreg_p + generic map (width => ex3_div_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_div_val_offset to ex3_div_val_offset + ex3_div_val_q'length-1), + scout => sov(ex3_div_val_offset to ex3_div_val_offset + ex3_div_val_q'length-1), + din => ex3_div_val_d, + dout => ex3_div_val_q); +ex3_multdiv_val_latch : tri_rlmreg_p + generic map (width => ex3_multdiv_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_multdiv_val_offset to ex3_multdiv_val_offset + ex3_multdiv_val_q'length-1), + scout => sov(ex3_multdiv_val_offset to ex3_multdiv_val_offset + ex3_multdiv_val_q'length-1), + din => ex3_multdiv_val_d, + dout => ex3_multdiv_val_q); +ex4_div_val_latch : tri_rlmreg_p + generic map (width => ex4_div_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_div_val_offset to ex4_div_val_offset + ex4_div_val_q'length-1), + scout => sov(ex4_div_val_offset to ex4_div_val_offset + ex4_div_val_q'length-1), + din => ex4_div_val_d, + dout => ex4_div_val_q); +ex5_div_val_latch : tri_rlmreg_p + generic map (width => ex5_div_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_div_val_offset to ex5_div_val_offset + ex5_div_val_q'length-1), + scout => sov(ex5_div_val_offset to ex5_div_val_offset + ex5_div_val_q'length-1), + din => ex5_div_val_d, + dout => ex5_div_val_q); +ex6_div_barr_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_div_barr_val_offset), + scout => sov(ex6_div_barr_val_offset), + din => ex5_div_barr_val , + dout => ex6_div_barr_val_q); +ex6_set_barr_latch : tri_rlmreg_p + generic map (width => ex6_set_barr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_set_barr_offset to ex6_set_barr_offset + ex6_set_barr_q'length-1), + scout => sov(ex6_set_barr_offset to ex6_set_barr_offset + ex6_set_barr_q'length-1), + din => ex5_set_barr, + dout => ex6_set_barr_q); +an_ac_back_inv_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(an_ac_back_inv_offset), + scout => sov(an_ac_back_inv_offset), + din => an_ac_back_inv , + dout => an_ac_back_inv_q); +an_ac_back_inv_addr_latch : tri_rlmreg_p + generic map (width => an_ac_back_inv_addr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => an_ac_back_inv_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(an_ac_back_inv_addr_offset to an_ac_back_inv_addr_offset + an_ac_back_inv_addr_q'length-1), + scout => sov(an_ac_back_inv_addr_offset to an_ac_back_inv_addr_offset + an_ac_back_inv_addr_q'length-1), + din => an_ac_back_inv_addr , + dout => an_ac_back_inv_addr_q); +an_ac_back_inv_target_bit3_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => an_ac_back_inv , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(an_ac_back_inv_target_bit3_offset), + scout => sov(an_ac_back_inv_target_bit3_offset), + din => an_ac_back_inv_target_bit3 , + dout => an_ac_back_inv_target_bit3_q); +back_inv_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(back_inv_val_offset), + scout => sov(back_inv_val_offset), + din => back_inv_val_d, + dout => back_inv_val_q); +coll_tid_latch : tri_rlmreg_p + generic map (width => coll_tid_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(coll_tid_offset to coll_tid_offset + coll_tid_q'length-1), + scout => sov(coll_tid_offset to coll_tid_offset + coll_tid_q'length-1), + din => coll_tid_d, + dout => coll_tid_q); +div_barr_done_latch : tri_rlmreg_p + generic map (width => div_barr_done_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(div_barr_done_offset to div_barr_done_offset + div_barr_done_q'length-1), + scout => sov(div_barr_done_offset to div_barr_done_offset + div_barr_done_q'length-1), + din => div_barr_done_d, + dout => div_barr_done_q); +div_barr_thres_latch : tri_rlmreg_p + generic map (width => div_barr_thres_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(div_barr_thres_offset to div_barr_thres_offset + div_barr_thres_q'length-1), + scout => sov(div_barr_thres_offset to div_barr_thres_offset + div_barr_thres_q'length-1), + din => spr_xucr4_div_barr_thres , + dout => div_barr_thres_q); +div_coll_barr_done_latch : tri_rlmreg_p + generic map (width => div_coll_barr_done_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(div_coll_barr_done_offset to div_coll_barr_done_offset + div_coll_barr_done_q'length-1), + scout => sov(div_coll_barr_done_offset to div_coll_barr_done_offset + div_coll_barr_done_q'length-1), + din => div_coll_barr_done_d, + dout => div_coll_barr_done_q); +hold_divide_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_hold_latch_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(hold_divide_offset), + scout => sov(hold_divide_offset), + din => rf0_divide , + dout => hold_divide_q); +hold_error_latch : tri_rlmreg_p + generic map (width => hold_error_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_hold_latch_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(hold_error_offset to hold_error_offset + hold_error_q'length-1), + scout => sov(hold_error_offset to hold_error_offset + hold_error_q'length-1), + din => hold_error_d, + dout => hold_error_q); +hold_ifar_latch : tri_rlmreg_p + generic map (width => hold_ifar_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_hold_latch_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(hold_ifar_offset to hold_ifar_offset + hold_ifar_q'length-1), + scout => sov(hold_ifar_offset to hold_ifar_offset + hold_ifar_q'length-1), + din => hold_ifar_d, + dout => hold_ifar_q); +hold_instr_latch : tri_rlmreg_p + generic map (width => hold_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_hold_latch_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(hold_instr_offset to hold_instr_offset + hold_instr_q'length-1), + scout => sov(hold_instr_offset to hold_instr_offset + hold_instr_q'length-1), + din => hold_instr_d, + dout => hold_instr_q); +hold_is_ucode_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_hold_latch_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(hold_is_ucode_offset), + scout => sov(hold_is_ucode_offset), + din => hold_is_ucode_d, + dout => hold_is_ucode_q); +hold_match_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_hold_latch_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(hold_match_offset), + scout => sov(hold_match_offset), + din => hold_match_d, + dout => hold_match_q); +hold_s1_latch : tri_rlmreg_p + generic map (width => hold_s1_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_hold_latch_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(hold_s1_offset to hold_s1_offset + hold_s1_q'length-1), + scout => sov(hold_s1_offset to hold_s1_offset + hold_s1_q'length-1), + din => hold_s1_d, + dout => hold_s1_q); +hold_s1_vld_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_hold_latch_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(hold_s1_vld_offset), + scout => sov(hold_s1_vld_offset), + din => hold_s1_vld_d, + dout => hold_s1_vld_q); +hold_s2_latch : tri_rlmreg_p + generic map (width => hold_s2_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_hold_latch_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(hold_s2_offset to hold_s2_offset + hold_s2_q'length-1), + scout => sov(hold_s2_offset to hold_s2_offset + hold_s2_q'length-1), + din => hold_s2_d, + dout => hold_s2_q); +hold_s2_vld_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_hold_latch_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(hold_s2_vld_offset), + scout => sov(hold_s2_vld_offset), + din => hold_s2_vld_d, + dout => hold_s2_vld_q); +hold_s3_latch : tri_rlmreg_p + generic map (width => hold_s3_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_hold_latch_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(hold_s3_offset to hold_s3_offset + hold_s3_q'length-1), + scout => sov(hold_s3_offset to hold_s3_offset + hold_s3_q'length-1), + din => hold_s3_d, + dout => hold_s3_q); +hold_s3_vld_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_hold_latch_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(hold_s3_vld_offset), + scout => sov(hold_s3_vld_offset), + din => hold_s3_vld_d, + dout => hold_s3_vld_q); +hold_ta_latch : tri_rlmreg_p + generic map (width => hold_ta_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_hold_latch_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(hold_ta_offset to hold_ta_offset + hold_ta_q'length-1), + scout => sov(hold_ta_offset to hold_ta_offset + hold_ta_q'length-1), + din => hold_ta_d, + dout => hold_ta_q); +hold_ta_vld_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_hold_latch_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(hold_ta_vld_offset), + scout => sov(hold_ta_vld_offset), + din => hold_ta_vld_d, + dout => hold_ta_vld_q); +hold_tid_latch : tri_rlmreg_p + generic map (width => hold_tid_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_hold_latch_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(hold_tid_offset to hold_tid_offset + hold_tid_q'length-1), + scout => sov(hold_tid_offset to hold_tid_offset + hold_tid_q'length-1), + din => hold_tid_d, + dout => hold_tid_q); +hold_use_imm_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_hold_latch_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(hold_use_imm_offset), + scout => sov(hold_use_imm_offset), + din => hold_use_imm_d, + dout => hold_use_imm_q); +lsu_xu_rel_ta_gpr_latch : tri_rlmreg_p + generic map (width => lsu_xu_rel_ta_gpr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(lsu_xu_rel_ta_gpr_offset to lsu_xu_rel_ta_gpr_offset + lsu_xu_rel_ta_gpr_q'length-1), + scout => sov(lsu_xu_rel_ta_gpr_offset to lsu_xu_rel_ta_gpr_offset + lsu_xu_rel_ta_gpr_q'length-1), + din => lsu_xu_rel_ta_gpr , + dout => lsu_xu_rel_ta_gpr_q); +lsu_xu_rel_wren_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(lsu_xu_rel_wren_offset), + scout => sov(lsu_xu_rel_wren_offset), + din => lsu_xu_rel_wren , + dout => lsu_xu_rel_wren_q); +spare_0_lcb: entity tri.tri_lcbnd(tri_lcbnd) + port map(vd => vdd, + gd => gnd, + act => tidn, + nclk => nclk, + forcee => func_sl_force, + thold_b => func_sl_thold_0_b, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + sg => sg_0, + lclk => spare_0_lclk, + d1clk => spare_0_d1clk, + d2clk => spare_0_d2clk); +spare_0_latch : entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width => spare_0_q'length, expand_type => expand_type, btr => "NLI0001_X2_A12TH", init=>(spare_0_q'range=>'0')) + port map (vd => vdd, gd => gnd, + LCLK => spare_0_lclk, + D1CLK => spare_0_d1clk, + D2CLK => spare_0_d2clk, + SCANIN => siv(spare_0_offset to spare_0_offset + spare_0_q'length-1), + SCANOUT => sov(spare_0_offset to spare_0_offset + spare_0_q'length-1), + D => spare_0_d, + QB => spare_0_q); +spare_0_d <= not spare_0_q; +mark_unused(spare_0_q); +spare_1_lcb: entity tri.tri_lcbnd(tri_lcbnd) + port map(vd => vdd, + gd => gnd, + act => tidn, + nclk => nclk, + forcee => func_sl_force, + thold_b => func_sl_thold_0_b, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + sg => sg_0, + lclk => spare_1_lclk, + d1clk => spare_1_d1clk, + d2clk => spare_1_d2clk); +spare_1_latch : entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width => spare_1_q'length, expand_type => expand_type, btr => "NLI0001_X2_A12TH", init=>(spare_1_q'range=>'0')) + port map (vd => vdd, gd => gnd, + LCLK => spare_1_lclk, + D1CLK => spare_1_d1clk, + D2CLK => spare_1_d2clk, + SCANIN => siv(spare_1_offset to spare_1_offset + spare_1_q'length-1), + SCANOUT => sov(spare_1_offset to spare_1_offset + spare_1_q'length-1), + D => spare_1_d, + QB => spare_1_q); +spare_1_d <= not spare_1_q; +mark_unused(spare_1_q); +siv(0 TO siv'right) <= sov(1 to siv'right) & scan_in; +scan_out <= sov(0); +END XUQ_DEC_A; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_dec_b.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_dec_b.vhdl new file mode 100644 index 0000000..d6a5644 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_dec_b.vhdl @@ -0,0 +1,8326 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.numeric_std.all; +LIBRARY ibm; +USE ibm.std_ulogic_support.all; +USE ibm.std_ulogic_function_support.all; +LIBRARY support; +USE support.power_logic_pkg.all; +LIBRARY tri; +USE tri.tri_latches_pkg.all; +LIBRARY work; +USE work.xuq_pkg.all; + +entity xuq_dec_b is + generic( + expand_type : integer := 2; + threads : integer := 4; + regmode : integer := 6; + regsize : integer := 64; + cl_size : natural := 6; + real_data_add : integer := 42; + eff_ifar : integer := 62); + port( + nclk : in clk_logic; + + vdd : inout power_logic; + gnd : inout power_logic; + + d_mode_dc : in std_ulogic; + delay_lclkr_dc : in std_ulogic; + mpw1_dc_b : in std_ulogic; + mpw2_dc_b : in std_ulogic; + func_sl_force : in std_ulogic; + func_sl_thold_0_b : in std_ulogic; + func_nsl_force : in std_ulogic; + func_nsl_thold_0_b : in std_ulogic; + func_slp_sl_force : in std_ulogic; + func_slp_sl_thold_0_b : in std_ulogic; + func_slp_nsl_force : in std_ulogic; + func_slp_nsl_thold_0_b : in std_ulogic; + sg_0 : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + slowspr_val_in : in std_ulogic; + slowspr_rw_in : in std_ulogic; + slowspr_etid_in : in std_ulogic_vector(0 to 1); + an_ac_dcr_act : in std_ulogic; + an_ac_dcr_val : in std_ulogic; + an_ac_dcr_read : in std_ulogic; + an_ac_dcr_etid : in std_ulogic_vector(0 to 1); + an_ac_dcr_ack : out std_ulogic; + dec_byp_ex4_dcr_ack : out std_ulogic; + + xu_mm_rf1_is_tlbsxr : out std_ulogic; + mm_xu_mmucr0_0_tlbsel : in std_ulogic_vector(4 to 5); + mm_xu_mmucr0_1_tlbsel : in std_ulogic_vector(4 to 5); + mm_xu_mmucr0_2_tlbsel : in std_ulogic_vector(4 to 5); + mm_xu_mmucr0_3_tlbsel : in std_ulogic_vector(4 to 5); + + fxb_fxa_ex7_we0 : out std_ulogic; + fxb_fxa_ex7_wa0 : out std_ulogic_vector(0 to 7); + + xu_rf1_flush : in std_ulogic_vector(0 to threads-1); + xu_ex1_flush : in std_ulogic_vector(0 to threads-1); + xu_ex2_flush : in std_ulogic_vector(0 to threads-1); + xu_ex3_flush : in std_ulogic_vector(0 to threads-1); + xu_ex4_flush : in std_ulogic_vector(0 to threads-1); + xu_ex5_flush : in std_ulogic_vector(0 to threads-1); + + fxa_fxb_rf0_val : in std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_issued : in std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_ucode_val : in std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_act : in std_ulogic; + fxa_fxb_rf0_instr : in std_ulogic_vector(0 to 31); + fxa_fxb_rf0_tid : in std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_ta_vld : in std_ulogic; + fxa_fxb_rf0_ta : in std_ulogic_vector(0 to 7); + fxa_fxb_rf0_error : in std_ulogic_vector(0 to 2); + fxa_fxb_rf0_match : in std_ulogic; + fxa_fxb_rf0_is_ucode : in std_ulogic; + fxa_fxb_rf0_gshare : in std_ulogic_vector(0 to 3); + fxa_fxb_rf0_ifar : in std_ulogic_vector(62-eff_ifar to 61); + fxa_fxb_rf0_s1_vld : in std_ulogic; + fxa_fxb_rf0_s1 : in std_ulogic_vector(0 to 7); + fxa_fxb_rf0_s2_vld : in std_ulogic; + fxa_fxb_rf0_s2 : in std_ulogic_vector(0 to 7); + fxa_fxb_rf0_s3_vld : in std_ulogic; + fxa_fxb_rf0_s3 : in std_ulogic_vector(0 to 7); + fxa_fxb_rf0_axu_instr_type : in std_ulogic_vector(0 to 2); + fxa_fxb_rf0_axu_ld_or_st : in std_ulogic; + fxa_fxb_rf0_axu_store : in std_ulogic; + fxa_fxb_rf0_axu_ldst_forcealign : in std_ulogic; + fxa_fxb_rf0_axu_ldst_forceexcept : in std_ulogic; + fxa_fxb_rf0_axu_ldst_indexed : in std_ulogic; + fxa_fxb_rf0_axu_ldst_tag : in std_ulogic_vector(0 to 8); + fxa_fxb_rf0_axu_mftgpr : in std_ulogic; + fxa_fxb_rf0_axu_mffgpr : in std_ulogic; + fxa_fxb_rf0_axu_movedp : in std_ulogic; + fxa_fxb_rf0_axu_ldst_size : in std_ulogic_vector(0 to 5); + fxa_fxb_rf0_axu_ldst_update : in std_ulogic; + fxa_fxb_rf0_pred_update : in std_ulogic; + fxa_fxb_rf0_pred_taken_cnt : in std_ulogic_vector(0 to 1); + fxa_fxb_rf0_mc_dep_chk_val : in std_ulogic_vector(0 to threads-1); + fxa_fxb_rf1_muldiv_coll : in std_ulogic; + fxa_fxb_rf0_xu_epid_instr : in std_ulogic; + fxa_fxb_rf0_axu_is_extload : in std_ulogic; + fxa_fxb_rf0_axu_is_extstore : in std_ulogic; + fxa_fxb_rf0_3src_instr : in std_ulogic; + fxa_fxb_rf0_gpr0_zero : in std_ulogic; + fxa_fxb_rf0_use_imm : in std_ulogic; + + alu_dec_ex1_ipb_ba : in std_ulogic_vector(27 to 31); + alu_dec_div_need_hole : in std_ulogic; + + dec_byp_rf1_rs0_sel : out std_ulogic_vector(1 to 9); + dec_byp_rf1_rs1_sel : out std_ulogic_vector(1 to 10); + dec_byp_rf1_rs2_sel : out std_ulogic_vector(1 to 9); + dec_byp_rf1_imm : out std_ulogic_vector(64-regsize to 63); + dec_byp_rf1_instr : out std_ulogic_vector(6 to 25); + dec_byp_rf1_cr_so_update : out std_ulogic_vector(0 to 1); + dec_byp_ex3_val : out std_ulogic_vector(0 to threads-1); + dec_byp_rf1_cr_we : out std_ulogic; + dec_byp_rf1_is_mcrf : out std_ulogic; + dec_byp_rf1_use_crfld0 : out std_ulogic; + dec_byp_rf1_alu_cmp : out std_ulogic; + dec_byp_rf1_is_mtcrf : out std_ulogic; + dec_byp_rf1_is_mtocrf : out std_ulogic; + dec_byp_rf1_byp_val : out std_ulogic_vector(1 to 3); + dec_byp_ex4_is_eratsxr : out std_ulogic; + dec_byp_rf1_ca_used : out std_ulogic; + dec_byp_rf1_ov_used : out std_ulogic; + dec_byp_ex4_dp_instr : out std_ulogic; + dec_byp_ex4_mtdp_val : out std_ulogic; + dec_byp_ex4_mfdp_val : out std_ulogic; + dec_byp_ex4_is_wchkall : out std_ulogic; + dec_byp_ex5_instr : out std_ulogic_vector(12 to 19); + dec_byp_rf0_act : out std_ulogic; + + dec_alu_rf1_act : out std_ulogic; + dec_alu_ex1_act : out std_ulogic; + dec_alu_rf1_sel : out std_ulogic_vector(0 to 3); + dec_alu_rf1_add_rs0_inv : out std_ulogic_vector(64-(2**regmode) to 63); + dec_alu_rf1_add_ci : out std_ulogic; + +dec_alu_rf1_mul_recform : out std_ulogic; +dec_alu_rf1_div_recform : out std_ulogic; +dec_alu_rf1_mul_ret : out std_ulogic; +dec_alu_rf1_mul_sign : out std_ulogic; +dec_alu_rf1_mul_size : out std_ulogic; +dec_alu_rf1_mul_imm : out std_ulogic; +dec_alu_rf1_div_sign : out std_ulogic; +dec_alu_rf1_div_size : out std_ulogic; +dec_alu_rf1_div_extd : out std_ulogic; +dec_alu_rf1_is_cmpl : out std_ulogic; +dec_alu_rf1_tw_cmpsel : out std_ulogic_vector(0 to 5); +dec_alu_ex1_is_cmp : out std_ulogic; +dec_rf1_is_isel : out std_ulogic; +dec_alu_rf1_xer_ov_update : out std_ulogic; +dec_alu_rf1_xer_ca_update : out std_ulogic; +dec_alu_rf1_sh_right : out std_ulogic; +dec_alu_rf1_sh_word : out std_ulogic; +dec_alu_rf1_sgnxtd_byte : out std_ulogic; +dec_alu_rf1_sgnxtd_half : out std_ulogic; +dec_alu_rf1_sgnxtd_wd : out std_ulogic; +dec_alu_rf1_sra_dw : out std_ulogic; +dec_alu_rf1_sra_wd : out std_ulogic; +dec_alu_rf1_chk_shov_dw : out std_ulogic; +dec_alu_rf1_chk_shov_wd : out std_ulogic; +dec_alu_rf1_use_me_ins_hi : out std_ulogic; +dec_alu_rf1_use_me_ins_lo : out std_ulogic; +dec_alu_rf1_use_mb_ins_hi : out std_ulogic; +dec_alu_rf1_use_mb_ins_lo : out std_ulogic; +dec_alu_rf1_use_me_rb_hi : out std_ulogic; +dec_alu_rf1_use_me_rb_lo : out std_ulogic; +dec_alu_rf1_use_mb_rb_hi : out std_ulogic; +dec_alu_rf1_use_mb_rb_lo : out std_ulogic; +dec_alu_rf1_use_rb_amt_hi : out std_ulogic; +dec_alu_rf1_use_rb_amt_lo : out std_ulogic; +dec_alu_rf1_zm_ins : out std_ulogic; +dec_alu_rf1_cr_logical : out std_ulogic; +dec_alu_rf1_cr_log_fcn : out std_ulogic_vector(0 to 3); +dec_alu_rf1_log_fcn : out std_ulogic_vector(0 to 3); +dec_alu_rf1_me_ins_b : out std_ulogic_vector(0 to 5); +dec_alu_rf1_mb_ins : out std_ulogic_vector(0 to 5); +dec_alu_rf1_sh_amt : out std_ulogic_vector(0 to 5); +dec_alu_rf1_mb_gt_me : out std_ulogic; +dec_alu_rf1_select_64bmode : out std_ulogic; +alu_ex3_mul_done : in std_ulogic; +alu_ex2_div_done : in std_ulogic; +dec_rf1_tid : out std_ulogic_vector(0 to threads-1); +dec_ex1_tid : out std_ulogic_vector(0 to threads-1); +dec_ex2_tid : out std_ulogic_vector(0 to threads-1); +dec_ex3_tid : out std_ulogic_vector(0 to threads-1); +dec_ex4_tid : out std_ulogic_vector(0 to threads-1); +dec_ex5_tid : out std_ulogic_vector(0 to threads-1); +dec_byp_ex1_spr_sel : out std_ulogic; +dec_byp_ex4_is_mfcr : out std_ulogic; +dec_byp_ex3_tlb_sel : out std_ulogic_vector(0 to 1); +dec_spr_ex1_is_mtspr : out std_ulogic; +dec_spr_ex1_is_mfspr : out std_ulogic; +dec_cpl_rf1_val : out std_ulogic_vector(0 to threads-1); +dec_cpl_rf1_issued : out std_ulogic_vector(0 to threads-1); +dec_spr_rf1_val : out std_ulogic_vector(0 to threads-1); +dec_spr_ex4_val : out std_ulogic_vector(0 to threads-1); +dec_cpl_rf1_instr : out std_ulogic_vector(0 to 31); +dec_fspr_ex1_instr : out std_ulogic_vector(11 to 20); +dec_fspr_ex6_val : out std_ulogic_vector(0 to threads-1); +dec_cpl_rf1_ifar : out std_ulogic_vector(62-eff_ifar to 61); +dec_cpl_rf1_pred_taken_cnt : out std_ulogic; +dec_cpl_rf1_ucode_val : out std_ulogic_vector(0 to threads-1); +dec_cpl_ex2_error : out std_ulogic_vector(0 to 2); +dec_cpl_ex2_match : out std_ulogic; +dec_cpl_ex2_is_ucode : out std_ulogic; +dec_cpl_ex3_is_any_store : out std_ulogic; +ex2_is_any_load_dac : out std_ulogic; +ex2_is_any_store_dac : out std_ulogic; +dec_cpl_ex3_mtdp_nr : out std_ulogic; +dec_cpl_ex3_instr_priv : out std_ulogic; +dec_cpl_ex3_mult_coll : out std_ulogic; +dec_cpl_ex3_tlb_illeg : out std_ulogic; +dec_cpl_ex3_axu_instr_type : out std_ulogic_vector(0 to 2); +dec_cpl_ex3_instr_hypv : out std_ulogic; +dec_cpl_ex1_epid_instr : out std_ulogic; +dec_cpl_ex2_illegal_op : out std_ulogic; +dec_cpl_ex1_is_slowspr_wr : out std_ulogic; +dec_cpl_ex3_ddmh_en : out std_ulogic; +dec_cpl_ex3_back_inv : out std_ulogic; +xu_lsu_rf0_act : out std_ulogic; +xu_lsu_rf1_cache_acc : out std_ulogic; +xu_lsu_rf1_axu_op_val : out std_ulogic; +xu_lsu_rf1_axu_ldst_falign : out std_ulogic; +xu_lsu_rf1_axu_ldst_fexcpt : out std_ulogic; +xu_lsu_rf1_thrd_id : out std_ulogic_vector(0 to 3); +xu_lsu_rf1_optype1 : out std_ulogic; +xu_lsu_rf1_optype2 : out std_ulogic; +xu_lsu_rf1_optype4 : out std_ulogic; +xu_lsu_rf1_optype8 : out std_ulogic; +xu_lsu_rf1_optype16 : out std_ulogic; +xu_lsu_rf1_optype32 : out std_ulogic; +xu_lsu_rf1_target_gpr : out std_ulogic_vector(0 to 8); +xu_lsu_rf1_load_instr : out std_ulogic; +xu_lsu_rf1_store_instr : out std_ulogic; +xu_lsu_rf1_dcbf_instr : out std_ulogic; +xu_lsu_rf1_sync_instr : out std_ulogic; +xu_lsu_rf1_mbar_instr : out std_ulogic; +xu_lsu_rf1_l_fld : out std_ulogic_vector(0 to 1); +xu_lsu_rf1_dcbi_instr : out std_ulogic; +xu_lsu_rf1_dcbz_instr : out std_ulogic; +xu_lsu_rf1_dcbt_instr : out std_ulogic; +xu_lsu_rf1_dcbtst_instr : out std_ulogic; +xu_lsu_rf1_th_fld : out std_ulogic_vector(0 to 4); +xu_lsu_rf1_dcbtls_instr : out std_ulogic; +xu_lsu_rf1_dcbtstls_instr : out std_ulogic; +xu_lsu_rf1_dcblc_instr : out std_ulogic; +xu_lsu_rf1_dcbst_instr : out std_ulogic; +xu_lsu_rf1_icbi_instr : out std_ulogic; +xu_lsu_rf1_icblc_instr : out std_ulogic; +xu_lsu_rf1_icbt_instr : out std_ulogic; +xu_lsu_rf1_icbtls_instr : out std_ulogic; +xu_lsu_rf1_tlbsync_instr : out std_ulogic; +xu_lsu_rf1_lock_instr : out std_ulogic; +xu_lsu_rf1_mutex_hint : out std_ulogic; +xu_lsu_rf1_algebraic : out std_ulogic; +xu_lsu_rf1_byte_rev : out std_ulogic; +xu_lsu_rf1_src_gpr : out std_ulogic; +xu_lsu_rf1_src_axu : out std_ulogic; +xu_lsu_rf1_src_dp : out std_ulogic; +xu_lsu_rf1_targ_gpr : out std_ulogic; +xu_lsu_rf1_targ_axu : out std_ulogic; +xu_lsu_rf1_targ_dp : out std_ulogic; +xu_lsu_ex1_rotsel_ovrd : out std_ulogic_vector(0 to 4); +lsu_xu_ex5_wren : in std_ulogic; +lsu_xu_rel_wren : in std_ulogic; +lsu_xu_rel_ta_gpr : in std_ulogic_vector(0 to 7); +lsu_xu_need_hole : in std_ulogic; +xu_lsu_rf1_src0_vld : out std_ulogic; +xu_lsu_rf1_src0_reg : out std_ulogic_vector(0 to 7); +xu_lsu_rf1_src1_vld : out std_ulogic; +xu_lsu_rf1_src1_reg : out std_ulogic_vector(0 to 7); +xu_lsu_rf1_targ_vld : out std_ulogic; +xu_lsu_rf1_targ_reg : out std_ulogic_vector(0 to 7); +xu_bx_ex1_mtdp_val : out std_ulogic; +xu_bx_ex1_mfdp_val : out std_ulogic; +xu_bx_ex1_ipc_thrd : out std_ulogic_vector(0 to 1); +xu_bx_ex2_ipc_ba : out std_ulogic_vector(0 to 4); +xu_bx_ex2_ipc_sz : out std_ulogic_vector(0 to 1); +xu_lsu_rf1_is_touch : out std_ulogic; +xu_lsu_rf1_is_msgsnd : out std_ulogic; +xu_lsu_rf1_dci_instr : out std_ulogic; +xu_lsu_rf1_ici_instr : out std_ulogic; +xu_lsu_rf1_icswx_instr : out std_ulogic; +xu_lsu_rf1_icswx_dot_instr : out std_ulogic; +xu_lsu_rf1_icswx_epid : out std_ulogic; +xu_lsu_rf1_ldawx_instr : out std_ulogic; +xu_lsu_rf1_wclr_instr : out std_ulogic; +xu_lsu_rf1_wchk_instr : out std_ulogic; +xu_lsu_rf1_derat_ra_eq_ea : out std_ulogic; +xu_lsu_rf1_cmd_act : out std_ulogic; +xu_lsu_rf1_data_act : out std_ulogic; +xu_lsu_rf1_mtspr_trace : out std_ulogic; +xu_iu_rf1_val : out std_ulogic_vector(0 to threads-1); +xu_rf1_val : out std_ulogic_vector(0 to threads-1); +xu_rf1_is_tlbre : out std_ulogic; +xu_rf1_is_tlbwe : out std_ulogic; +xu_rf1_is_tlbsx : out std_ulogic; +xu_rf1_is_tlbsrx : out std_ulogic; +xu_rf1_is_tlbivax : out std_ulogic; +xu_rf1_is_tlbilx : out std_ulogic; +xu_rf1_is_eratre : out std_ulogic; +xu_rf1_is_eratwe : out std_ulogic; +xu_rf1_is_eratsx : out std_ulogic; +xu_rf1_is_eratsrx : out std_ulogic; +xu_rf1_is_erativax : out std_ulogic; +xu_rf1_is_eratilx : out std_ulogic; +xu_ex1_is_isync : out std_ulogic; +xu_ex1_is_csync : out std_ulogic; +xu_lsu_rf1_derat_act : out std_ulogic; +xu_lsu_rf1_derat_is_load : out std_ulogic; +xu_lsu_rf1_derat_is_store : out std_ulogic; +xu_rf1_ws : out std_ulogic_vector(0 to 1); +xu_rf1_t : out std_ulogic_vector(0 to 2); +lsu_xu_is2_back_inv : in std_ulogic; +lsu_xu_is2_back_inv_addr : in std_ulogic_vector(64-real_data_add to 63-cl_size); +byp_dec_rf1_xer_ca : in std_ulogic; +spr_dec_rf1_msr_ucle : in std_ulogic_vector(0 to threads-1); +spr_dec_rf1_msrp_uclep : in std_ulogic_vector(0 to threads-1); +spr_dec_rf1_epcr_dgtmi : in std_ulogic_vector(0 to threads-1); +spr_dec_spr_xucr0_ssdly : in std_ulogic_vector(0 to 4); +byp_xer_si : in std_ulogic_vector(0 to 7*threads-1); +xu_iu_ex6_pri : out std_ulogic_vector(0 to 2); +xu_iu_ex6_pri_val : out std_ulogic_vector(0 to 3); +xu_iu_need_hole : out std_ulogic; +fxb_fxa_ex6_clear_barrier : out std_ulogic_vector(0 to threads-1); +xu_iu_ex5_gshare : out std_ulogic_vector(0 to 3); +xu_iu_ex5_getNIA : out std_ulogic; +xu_iu_ex5_val : out std_ulogic; +xu_iu_ex5_tid : out std_ulogic_vector(0 to threads-1); +xu_iu_ex5_br_update : out std_ulogic; +xu_iu_ex5_br_hist : out std_ulogic_vector(0 to 1); +xu_iu_ex5_bclr : out std_ulogic; +xu_iu_ex5_lk : out std_ulogic; +xu_iu_ex5_bh : out std_ulogic_vector(0 to 1); +pc_xu_trace_bus_enable : in std_ulogic; +pc_xu_instr_trace_mode : in std_ulogic; +pc_xu_instr_trace_tid : in std_ulogic_vector(0 to 1); +dec_byp_ex3_instr_trace_val : out std_ulogic; +dec_byp_ex3_instr_trace_gate : out std_ulogic; +dec_cpl_rf1_instr_trace_val : out std_ulogic; +dec_cpl_rf1_instr_trace_type : out std_ulogic_vector(0 to 1); +dec_cpl_ex3_instr_trace_val : out std_ulogic; +xu_lsu_ex2_instr_trace_val : out std_ulogic; +cpl_dec_in_ucode : in std_ulogic_vector(0 to threads-1); +spr_bit_act : in std_ulogic; +spr_msr_cm : in std_ulogic_vector(0 to threads-1); +spr_ccr2_notlb : in std_ulogic; +spr_ccr2_en_attn : in std_ulogic; +spr_ccr2_en_ditc : in std_ulogic; +spr_ccr2_en_pc : in std_ulogic; +spr_ccr2_en_icswx : in std_ulogic; +spr_ccr2_en_dcr : in std_ulogic; +spr_xucr0_clkg_ctl : in std_ulogic_vector(2 to 2); +byp_grp3_debug : out std_ulogic_vector(0 to 14); +byp_grp4_debug : out std_ulogic_vector(0 to 13); +byp_grp5_debug : out std_ulogic_vector(0 to 14); +dec_grp0_debug : out std_ulogic_vector(0 to 87); +dec_grp1_debug : out std_ulogic_vector(0 to 87) + ); +end xuq_dec_b; +ARCHITECTURE XUQ_DEC_B + OF XUQ_DEC_B + IS +SIGNAL TBL_LD_ST_DEC_PT : STD_ULOGIC_VECTOR(1 TO 77) := +(OTHERS=> 'U'); +SIGNAL TBL_MASTER_DEC_PT : STD_ULOGIC_VECTOR(1 TO 97) := +(OTHERS=> 'U'); +SIGNAL TBL_PRI_CHANGE_PT : STD_ULOGIC_VECTOR(1 TO 7) := +(OTHERS=> 'U'); +SIGNAL TBL_RECFORM_DEC_PT : STD_ULOGIC_VECTOR(1 TO 29) := +(OTHERS=> 'U'); +SIGNAL TBL_VAL_STG_GATE_PT : STD_ULOGIC_VECTOR(1 TO 47) := +(OTHERS=> 'U'); +SIGNAL TBL_XER_DEC_PT : STD_ULOGIC_VECTOR(1 TO 37) := +(OTHERS=> 'U'); +subtype s2 is std_ulogic_vector(0 to 1); +subtype s3 is std_ulogic_vector(0 to 2); +signal is1_need_hole_q, is1_need_hole_d : std_ulogic; +signal is2_need_hole_q, is2_need_hole_d : std_ulogic; +signal rf0_back_inv_q : std_ulogic; +signal rf0_back_inv_addr_q : std_ulogic_vector(64-real_data_add to 63-cl_size); +signal rf0_need_hole_q : std_ulogic; +signal rf1_3src_instr_q : std_ulogic; +signal rf1_act_q, rf0_act : std_ulogic; +signal rf1_axu_instr_type_q : std_ulogic_vector(0 to 2); +signal rf1_axu_is_extload_q : std_ulogic; +signal rf1_axu_is_extstore_q : std_ulogic; +signal rf1_axu_ld_or_st_q : std_ulogic; +signal rf1_axu_ldst_forcealign_q : std_ulogic; +signal rf1_axu_ldst_forceexcept_q : std_ulogic; +signal rf1_axu_ldst_indexed_q : std_ulogic; +signal rf1_axu_ldst_size_q : std_ulogic_vector(0 to 5); +signal rf1_axu_ldst_tag_q : std_ulogic_vector(0 to 8); +signal rf1_axu_ldst_update_q : std_ulogic; +signal rf1_axu_mffgpr_q : std_ulogic; +signal rf1_axu_mftgpr_q : std_ulogic; +signal rf1_axu_movedp_q : std_ulogic; +signal rf1_axu_store_q : std_ulogic; +signal rf1_back_inv_q : std_ulogic; +signal rf1_back_inv_addr_q : std_ulogic_vector(64-real_data_add to 63-cl_size); +signal rf1_error_q : std_ulogic_vector(0 to 2); +signal rf1_gpr0_zero_q : std_ulogic; +signal rf1_gshare_q : std_ulogic_vector(0 to 3); +signal rf1_ifar_q : std_ulogic_vector(62-eff_ifar to 61); +signal rf1_instr_q : std_ulogic_vector(0 to 31); +signal rf1_instr_21to30_00_q, rf1_instr_21to30_00_d : std_ulogic_vector(21 to 30); +signal rf1_instr_21to30_01_q, rf1_instr_21to30_01_d : std_ulogic_vector(21 to 30); +signal rf1_instr_21to30_02_q, rf1_instr_21to30_02_d : std_ulogic_vector(21 to 30); +signal rf1_instr_21to30_03_q, rf1_instr_21to30_03_d : std_ulogic_vector(21 to 30); +signal rf1_instr_21to30_04_q, rf1_instr_21to30_04_d : std_ulogic_vector(21 to 30); +signal rf1_instr_21to30_05_q, rf1_instr_21to30_05_d : std_ulogic_vector(21 to 30); +signal rf1_instr_21to30_06_q, rf1_instr_21to30_06_d : std_ulogic_vector(21 to 30); +signal rf1_instr_21to30_07_q, rf1_instr_21to30_07_d : std_ulogic_vector(21 to 30); +signal rf1_instr_21to30_08_q, rf1_instr_21to30_08_d : std_ulogic_vector(21 to 30); +signal rf1_instr_21to30_09_q, rf1_instr_21to30_09_d : std_ulogic_vector(21 to 30); +signal rf1_instr_21to30_10_q, rf1_instr_21to30_10_d : std_ulogic_vector(21 to 30); +signal rf1_is_isel_q, rf1_is_isel_d : std_ulogic; +signal rf1_is_ucode_q : std_ulogic; +signal rf1_issued_q : std_ulogic_vector(0 to threads-1); +signal rf1_match_q : std_ulogic; +signal rf1_mc_dep_chk_val_q, rf1_mc_dep_chk_val_d : std_ulogic_vector(0 to threads-1); +signal rf1_need_hole_q : std_ulogic; +signal rf1_opcode_is_31_q, rf1_opcode_is_31_d : std_ulogic_vector(0 to 9); +signal rf1_pred_taken_cnt_q : std_ulogic_vector(0 to 1); +signal rf1_pred_update_q : std_ulogic; +signal rf1_s1_q : std_ulogic_vector(0 to 7); +signal rf1_s1_vld_q : std_ulogic; +signal rf1_s2_q : std_ulogic_vector(0 to 7); +signal rf1_s2_vld_q : std_ulogic; +signal rf1_s3_q : std_ulogic_vector(0 to 7); +signal rf1_s3_vld_q : std_ulogic; +signal rf1_ta_q : std_ulogic_vector(0 to 7); +signal rf1_ta_vld_q : std_ulogic; +signal rf1_tid_q : std_ulogic_vector(0 to threads-1); +signal rf1_tid_2_q : std_ulogic_vector(0 to threads-1); +signal rf1_ucode_val_q : std_ulogic_vector(0 to threads-1); +signal rf1_use_imm_q : std_ulogic; +signal rf1_val_q : std_ulogic_vector(0 to threads-1); +signal rf1_val_iu_q : std_ulogic_vector(0 to threads-1); +signal rf1_xu_epid_instr_q : std_ulogic; +signal ex1_act_q, ex1_act_d : std_ulogic; +signal ex1_axu_instr_type_q, ex1_axu_instr_type_d : std_ulogic_vector(0 to 2); +signal ex1_axu_movedp_q : std_ulogic; +signal ex1_back_inv_q : std_ulogic; +signal ex1_bh_q : std_ulogic_vector(0 to 1); +signal ex1_clear_barrier_q : std_ulogic; +signal ex1_ddmh_en_q, ex1_ddmh_en_d : std_ulogic; +signal ex1_ditc_illeg_q, ex1_ditc_illeg_d : std_ulogic; +signal ex1_dp_indexed_q, ex1_dp_indexed_d : std_ulogic; +signal ex1_epid_instr_q, ex1_epid_instr_d : std_ulogic; +signal ex1_error_q : std_ulogic_vector(0 to 2); +signal ex1_getNIA_q : std_ulogic; +signal ex1_gpr_we_q, ex1_gpr_we_d : std_ulogic; +signal ex1_gshare_q : std_ulogic_vector(0 to 3); +signal ex1_instr_q : std_ulogic_vector(11 to 25); +signal ex1_instr_hypv_q : std_ulogic; +signal ex1_instr_priv_q : std_ulogic; +signal ex1_is_any_load_dac_q : std_ulogic; +signal ex1_is_any_store_q : std_ulogic; +signal ex1_is_any_store_dac_q : std_ulogic; +signal ex1_is_attn_q : std_ulogic; +signal ex1_is_bclr_q : std_ulogic; +signal ex1_is_cmp_q : std_ulogic; +signal ex1_is_csync_q, rf1_is_csync : std_ulogic; +signal ex1_is_eratsxr_q : std_ulogic; +signal ex1_is_icswx_q, ex1_is_icswx_d : std_ulogic; +signal ex1_is_isync_q : std_ulogic; +signal ex1_is_ld_w_update_q : std_ulogic; +signal ex1_is_lmw_q : std_ulogic; +signal ex1_is_lswi_q : std_ulogic; +signal ex1_is_lswx_q : std_ulogic; +signal ex1_is_mfcr_q : std_ulogic; +signal ex1_is_mfspr_q : std_ulogic; +signal ex1_is_msgclr_q : std_ulogic; +signal ex1_is_msgsnd_q : std_ulogic; +signal ex1_is_mtspr_q : std_ulogic; +signal ex1_is_sc_q : std_ulogic; +signal ex1_is_st_w_update_q : std_ulogic; +signal ex1_is_ucode_q : std_ulogic; +signal ex1_is_wchkall_q : std_ulogic; +signal ex1_lk_q : std_ulogic; +signal ex1_match_q : std_ulogic; +signal ex1_mfdcr_instr_q, rf1_mfdcr_instr : std_ulogic; +signal ex1_mfdp_val_q, ex1_mfdp_val_d : std_ulogic; +signal ex1_mtdcr_instr_q, rf1_mtdcr_instr : std_ulogic; +signal ex1_mtdp_nr_q, ex1_mtdp_nr_d : std_ulogic; +signal ex1_mtdp_val_q, ex1_mtdp_val_d : std_ulogic; +signal ex1_muldiv_coll_q : std_ulogic; +signal ex1_need_hole_q : std_ulogic; +signal ex1_num_regs_q, ex1_num_regs_d : std_ulogic_vector(0 to 5); +signal ex1_ovr_rotsel_q, ex1_ovr_rotsel_d : std_ulogic; +signal ex1_pred_taken_cnt_q : std_ulogic_vector(0 to 1); +signal ex1_pred_update_q : std_ulogic; +signal ex1_pri_q : std_ulogic_vector(0 to 2); +signal ex1_rotsel_ovrd_q, ex1_rotsel_ovrd_d : std_ulogic_vector(0 to 4); +signal ex1_s1_q : std_ulogic_vector(0 to 7); +signal ex1_s2_q : std_ulogic_vector(0 to 7); +signal ex1_s3_q : std_ulogic_vector(0 to 7); +signal ex1_spr_sel_q : std_ulogic; +signal ex1_ta_q : std_ulogic_vector(0 to 7); +signal ex1_tid_q : std_ulogic_vector(0 to threads-1); +signal ex1_tlb_data_val_q, ex1_tlb_data_val_d : std_ulogic; +signal ex1_tlb_illeg_q, ex1_tlb_illeg_d : std_ulogic; +signal ex1_trace_type_q, rf1_trace_type : std_ulogic_vector(0 to 1); +signal ex1_trace_val_q, rf1_trace_val : std_ulogic; +signal ex1_val_q, ex1_val_d : std_ulogic_vector(0 to threads-1); +signal ex1_axu_ld_or_st_q : std_ulogic; +signal ex2_act_q, ex2_act_d : std_ulogic; +signal ex2_axu_instr_type_q : std_ulogic_vector(0 to 2); +signal ex2_back_inv_q : std_ulogic; +signal ex2_bh_q : std_ulogic_vector(0 to 1); +signal ex2_clear_barrier_q : std_ulogic; +signal ex2_ddmh_en_q : std_ulogic; +signal ex2_ditc_illeg_q, ex2_ditc_illeg_d : std_ulogic; +signal ex2_error_q : std_ulogic_vector(0 to 2); +signal ex2_getNIA_q : std_ulogic; +signal ex2_gpr_we_q, ex2_gpr_we_d : std_ulogic; +signal ex2_gshare_q : std_ulogic_vector(0 to 3); +signal ex2_instr_q : std_ulogic_vector(12 to 25); +signal ex2_instr_hypv_q : std_ulogic; +signal ex2_instr_priv_q : std_ulogic; +signal ex2_ipb_ba_q, ex2_ipb_ba_d : std_ulogic_vector(0 to 4); +signal ex2_ipb_sz_q, ex2_ipb_sz_d : std_ulogic_vector(0 to 1); +signal ex2_is_any_load_dac_q : std_ulogic; +signal ex2_is_any_store_q : std_ulogic; +signal ex2_is_any_store_dac_q : std_ulogic; +signal ex2_is_attn_q : std_ulogic; +signal ex2_is_bclr_q : std_ulogic; +signal ex2_is_eratsxr_q : std_ulogic; +signal ex2_is_icswx_q : std_ulogic; +signal ex2_is_ld_w_update_q : std_ulogic; +signal ex2_is_lmw_q : std_ulogic; +signal ex2_is_lswi_q : std_ulogic; +signal ex2_is_lswx_q : std_ulogic; +signal ex2_is_mfcr_q : std_ulogic; +signal ex2_is_msgclr_q : std_ulogic; +signal ex2_is_msgsnd_q : std_ulogic; +signal ex2_is_sc_q : std_ulogic; +signal ex2_is_st_w_update_q : std_ulogic; +signal ex2_is_ucode_q : std_ulogic; +signal ex2_is_wchkall_q : std_ulogic; +signal ex2_lk_q : std_ulogic; +signal ex2_match_q : std_ulogic; +signal ex2_mfdp_val_q : std_ulogic; +signal ex2_mtdp_nr_q : std_ulogic; +signal ex2_mtdp_val_q : std_ulogic; +signal ex2_muldiv_coll_q : std_ulogic; +signal ex2_need_hole_q : std_ulogic; +signal ex2_pred_taken_cnt_q : std_ulogic_vector(0 to 1); +signal ex2_pred_update_q : std_ulogic; +signal ex2_pri_q : std_ulogic_vector(0 to 2); +signal ex2_ra_eq_rt_q, ex2_ra_eq_rt_d : std_ulogic; +signal ex2_ra_eq_zero_q, ex2_ra_eq_zero_d : std_ulogic; +signal ex2_ra_in_rng_lmw_q, ex2_ra_in_rng_lmw_d : std_ulogic; +signal ex2_ra_in_rng_nowrap_q, ex2_ra_in_rng_nowrap_d : std_ulogic; +signal ex2_ra_in_rng_wrap_q, ex2_ra_in_rng_wrap_d : std_ulogic; +signal ex2_range_wrap_q, ex2_range_wrap_d : std_ulogic; +signal ex2_rb_eq_rt_q, ex2_rb_eq_rt_d : std_ulogic; +signal ex2_rb_in_rng_nowrap_q, ex2_rb_in_rng_nowrap_d : std_ulogic; +signal ex2_rb_in_rng_wrap_q, ex2_rb_in_rng_wrap_d : std_ulogic; +signal ex2_slowspr_dcr_rd_q, ex1_slowspr_dcr_rd : std_ulogic; +signal ex2_ta_q : std_ulogic_vector(0 to 7); +signal ex2_tid_q : std_ulogic_vector(0 to threads-1); +signal ex2_tlb_data_val_q : std_ulogic; +signal ex2_tlb_illeg_q : std_ulogic; +signal ex2_trace_type_q : std_ulogic_vector(0 to 1); +signal ex2_trace_val_q : std_ulogic; +signal ex2_val_q, ex2_val_d : std_ulogic_vector(0 to threads-1); +signal ex3_act_q, ex3_act_d : std_ulogic; +signal ex3_axu_instr_type_q : std_ulogic_vector(0 to 2); +signal ex3_back_inv_q : std_ulogic; +signal ex3_bh_q : std_ulogic_vector(0 to 1); +signal ex3_clear_barrier_q : std_ulogic; +signal ex3_ddmh_en_q : std_ulogic; +signal ex3_div_done_q : std_ulogic; +signal ex3_getNIA_q : std_ulogic; +signal ex3_gpr_we_q : std_ulogic; +signal ex3_gshare_q : std_ulogic_vector(0 to 3); +signal ex3_instr_q : std_ulogic_vector(12 to 19); +signal ex3_instr_hypv_q : std_ulogic; +signal ex3_instr_priv_q : std_ulogic; +signal ex3_is_any_store_q : std_ulogic; +signal ex3_is_bclr_q : std_ulogic; +signal ex3_is_eratsxr_q : std_ulogic; +signal ex3_is_mfcr_q : std_ulogic; +signal ex3_is_wchkall_q : std_ulogic; +signal ex3_lk_q : std_ulogic; +signal ex3_mfdp_val_q : std_ulogic; +signal ex3_mtdp_nr_q : std_ulogic; +signal ex3_mtdp_val_q : std_ulogic; +signal ex3_muldiv_coll_q : std_ulogic; +signal ex3_need_hole_q : std_ulogic; +signal ex3_pred_taken_cnt_q : std_ulogic_vector(0 to 1); +signal ex3_pred_update_q : std_ulogic; +signal ex3_pri_q : std_ulogic_vector(0 to 2); +signal ex3_slowspr_dcr_rd_q : std_ulogic; +signal ex3_ta_q : std_ulogic_vector(0 to 7); +signal ex3_tid_q : std_ulogic_vector(0 to threads-1); +signal ex3_tlb_data_val_q : std_ulogic; +signal ex3_tlb_illeg_q : std_ulogic; +signal ex3_trace_type_q : std_ulogic_vector(0 to 1); +signal ex3_trace_val_q : std_ulogic; +signal ex3_val_q, ex3_val_d : std_ulogic_vector(0 to threads-1); +signal ex4_act_q, ex4_act_d : std_ulogic; +signal ex4_bh_q : std_ulogic_vector(0 to 1); +signal ex4_clear_barrier_q : std_ulogic; +signal ex4_dp_instr_q, ex4_dp_instr_d : std_ulogic; +signal ex4_getNIA_q : std_ulogic; +signal ex4_gpr_we_q, ex4_gpr_we_d : std_ulogic; +signal ex4_gshare_q : std_ulogic_vector(0 to 3); +signal ex4_instr_q : std_ulogic_vector(12 to 19); +signal ex4_is_bclr_q : std_ulogic; +signal ex4_is_eratsxr_q : std_ulogic; +signal ex4_is_mfcr_q : std_ulogic; +signal ex4_is_wchkall_q : std_ulogic; +signal ex4_lk_q : std_ulogic; +signal ex4_mfdp_val_q : std_ulogic; +signal ex4_mtdp_val_q : std_ulogic; +signal ex4_pred_taken_cnt_q : std_ulogic_vector(0 to 1); +signal ex4_pred_update_q : std_ulogic; +signal ex4_pri_q : std_ulogic_vector(0 to 2); +signal ex4_slowspr_dcr_rd_q : std_ulogic; +signal ex4_ta_q : std_ulogic_vector(0 to 7); +signal ex4_tid_q : std_ulogic_vector(0 to threads-1); +signal ex4_val_q, ex4_val_d : std_ulogic_vector(0 to threads-1); +signal ex5_act_q, ex5_act_d : std_ulogic; +signal ex5_bh_q : std_ulogic_vector(0 to 1); +signal ex5_clear_barrier_q : std_ulogic; +signal ex5_getNIA_q : std_ulogic; +signal ex5_gpr_we_q, ex5_gpr_we_d : std_ulogic; +signal ex5_gshare_q : std_ulogic_vector(0 to 3); +signal ex5_instr_q : std_ulogic_vector(12 to 19); +signal ex5_is_bclr_q : std_ulogic; +signal ex5_lk_q : std_ulogic; +signal ex5_pred_taken_cnt_q : std_ulogic_vector(0 to 1); +signal ex5_pred_update_q : std_ulogic; +signal ex5_pri_q : std_ulogic_vector(0 to 2); +signal ex5_slowspr_dcr_rd_q, ex5_slowspr_dcr_rd_d : std_ulogic_vector(0 to threads-1); +signal ex5_ta_q : std_ulogic_vector(0 to 7); +signal ex5_tid_q : std_ulogic_vector(0 to threads-1); +signal ex5_val_q, ex5_val_d : std_ulogic_vector(0 to threads-1); +signal ex6_clear_barrier_q, ex6_clear_barrier_d : std_ulogic_vector(0 to threads-1); +signal ex6_gpr_we_q, ex6_gpr_we_d : std_ulogic; +signal ex6_pri_q : std_ulogic_vector(0 to 2); +signal ex6_ta_q, ex6_ta_d : std_ulogic_vector(0 to 7); +signal ex6_val_q, ex6_val_d : std_ulogic_vector(0 to threads-1); +signal ex7_gpr_we_q : std_ulogic; +signal ex7_ta_q : std_ulogic_vector(0 to 7); +signal ex7_val_q : std_ulogic_vector(0 to threads-1); +signal an_ac_dcr_val_q : std_ulogic; +signal dcr_ack_q, dcr_ack : std_ulogic; +signal dcr_act_q : std_ulogic; +signal dcr_etid_q : std_ulogic_vector(0 to 1); +signal dcr_read_q : std_ulogic; +signal dcr_val_q, dcr_val_d : std_ulogic; +signal instr_trace_mode_q : std_ulogic; +signal instr_trace_tid_q : std_ulogic_vector(0 to 1); +signal lsu_xu_need_hole_q, lsu_xu_need_hole_d : std_ulogic; +signal lsu_xu_rel_ta_gpr_q : std_ulogic_vector(0 to 7); +signal lsu_xu_rel_wren_q : std_ulogic; +signal mmucr0_0_tlbsel_q : std_ulogic_vector(4 to 5); +signal mmucr0_1_tlbsel_q : std_ulogic_vector(4 to 5); +signal mmucr0_2_tlbsel_q : std_ulogic_vector(4 to 5); +signal mmucr0_3_tlbsel_q : std_ulogic_vector(4 to 5); +signal slowspr_etid_q : std_ulogic_vector(0 to 1); +signal slowspr_rw_q : std_ulogic; +signal slowspr_val_q : std_ulogic; +signal spr_ccr2_en_attn_q : std_ulogic; +signal spr_ccr2_en_dcr_q : std_ulogic; +signal spr_ccr2_en_ditc_q : std_ulogic; +signal spr_ccr2_en_icswx_q : std_ulogic; +signal spr_ccr2_en_pc_q : std_ulogic; +signal spr_ccr2_notlb_q : std_ulogic; +signal spr_msr_cm_q : std_ulogic_vector(0 to threads-1); +signal t0_hold_ta_q : std_ulogic_vector(0 to 5); +signal t1_hold_ta_q : std_ulogic_vector(0 to 5); +signal t2_hold_ta_q : std_ulogic_vector(0 to 5); +signal t3_hold_ta_q : std_ulogic_vector(0 to 5); +signal trace_bus_enable_q : std_ulogic; +signal clkg_ctl_q : std_ulogic; +signal spr_bit_act_q : std_ulogic; +signal spare_0_q, spare_0_d : std_ulogic_vector(0 to 15); +signal spare_1_q, spare_1_d : std_ulogic_vector(0 to 15); +constant is1_need_hole_offset : integer := 0; +constant is2_need_hole_offset : integer := is1_need_hole_offset + 1; +constant rf0_back_inv_offset : integer := is2_need_hole_offset + 1; +constant rf0_back_inv_addr_offset : integer := rf0_back_inv_offset + 1; +constant rf0_need_hole_offset : integer := rf0_back_inv_addr_offset + rf0_back_inv_addr_q'length; +constant rf1_act_offset : integer := rf0_need_hole_offset + 1; +constant rf1_axu_ld_or_st_offset : integer := rf1_act_offset + 1; +constant rf1_back_inv_offset : integer := rf1_axu_ld_or_st_offset + 1; +constant rf1_need_hole_offset : integer := rf1_back_inv_offset + 1; +constant rf1_ta_vld_offset : integer := rf1_need_hole_offset + 1; +constant rf1_ucode_val_offset : integer := rf1_ta_vld_offset + 1; +constant rf1_val_offset : integer := rf1_ucode_val_offset + rf1_ucode_val_q'length; +constant rf1_val_iu_offset : integer := rf1_val_offset + rf1_val_q'length; +constant ex1_act_offset : integer := rf1_val_iu_offset + rf1_val_iu_q'length; +constant ex1_axu_instr_type_offset : integer := ex1_act_offset + 1; +constant ex1_axu_movedp_offset : integer := ex1_axu_instr_type_offset + ex1_axu_instr_type_q'length; +constant ex1_back_inv_offset : integer := ex1_axu_movedp_offset + 1; +constant ex1_bh_offset : integer := ex1_back_inv_offset + 1; +constant ex1_clear_barrier_offset : integer := ex1_bh_offset + ex1_bh_q'length; +constant ex1_ddmh_en_offset : integer := ex1_clear_barrier_offset + 1; +constant ex1_ditc_illeg_offset : integer := ex1_ddmh_en_offset + 1; +constant ex1_dp_indexed_offset : integer := ex1_ditc_illeg_offset + 1; +constant ex1_epid_instr_offset : integer := ex1_dp_indexed_offset + 1; +constant ex1_error_offset : integer := ex1_epid_instr_offset + 1; +constant ex1_getNIA_offset : integer := ex1_error_offset + ex1_error_q'length; +constant ex1_gpr_we_offset : integer := ex1_getNIA_offset + 1; +constant ex1_gshare_offset : integer := ex1_gpr_we_offset + 1; +constant ex1_instr_offset : integer := ex1_gshare_offset + ex1_gshare_q'length; +constant ex1_instr_hypv_offset : integer := ex1_instr_offset + ex1_instr_q'length; +constant ex1_instr_priv_offset : integer := ex1_instr_hypv_offset + 1; +constant ex1_is_any_load_dac_offset : integer := ex1_instr_priv_offset + 1; +constant ex1_is_any_store_offset : integer := ex1_is_any_load_dac_offset + 1; +constant ex1_is_any_store_dac_offset : integer := ex1_is_any_store_offset + 1; +constant ex1_is_attn_offset : integer := ex1_is_any_store_dac_offset + 1; +constant ex1_is_bclr_offset : integer := ex1_is_attn_offset + 1; +constant ex1_is_cmp_offset : integer := ex1_is_bclr_offset + 1; +constant ex1_is_csync_offset : integer := ex1_is_cmp_offset + 1; +constant ex1_is_eratsxr_offset : integer := ex1_is_csync_offset + 1; +constant ex1_is_icswx_offset : integer := ex1_is_eratsxr_offset + 1; +constant ex1_is_isync_offset : integer := ex1_is_icswx_offset + 1; +constant ex1_is_ld_w_update_offset : integer := ex1_is_isync_offset + 1; +constant ex1_is_lmw_offset : integer := ex1_is_ld_w_update_offset + 1; +constant ex1_is_lswi_offset : integer := ex1_is_lmw_offset + 1; +constant ex1_is_lswx_offset : integer := ex1_is_lswi_offset + 1; +constant ex1_is_mfcr_offset : integer := ex1_is_lswx_offset + 1; +constant ex1_is_mfspr_offset : integer := ex1_is_mfcr_offset + 1; +constant ex1_is_msgclr_offset : integer := ex1_is_mfspr_offset + 1; +constant ex1_is_msgsnd_offset : integer := ex1_is_msgclr_offset + 1; +constant ex1_is_mtspr_offset : integer := ex1_is_msgsnd_offset + 1; +constant ex1_is_sc_offset : integer := ex1_is_mtspr_offset + 1; +constant ex1_is_st_w_update_offset : integer := ex1_is_sc_offset + 1; +constant ex1_is_ucode_offset : integer := ex1_is_st_w_update_offset + 1; +constant ex1_is_wchkall_offset : integer := ex1_is_ucode_offset + 1; +constant ex1_lk_offset : integer := ex1_is_wchkall_offset + 1; +constant ex1_match_offset : integer := ex1_lk_offset + 1; +constant ex1_mfdcr_instr_offset : integer := ex1_match_offset + 1; +constant ex1_mfdp_val_offset : integer := ex1_mfdcr_instr_offset + 1; +constant ex1_mtdcr_instr_offset : integer := ex1_mfdp_val_offset + 1; +constant ex1_mtdp_nr_offset : integer := ex1_mtdcr_instr_offset + 1; +constant ex1_mtdp_val_offset : integer := ex1_mtdp_nr_offset + 1; +constant ex1_muldiv_coll_offset : integer := ex1_mtdp_val_offset + 1; +constant ex1_need_hole_offset : integer := ex1_muldiv_coll_offset + 1; +constant ex1_num_regs_offset : integer := ex1_need_hole_offset + 1; +constant ex1_ovr_rotsel_offset : integer := ex1_num_regs_offset + ex1_num_regs_q'length; +constant ex1_pred_taken_cnt_offset : integer := ex1_ovr_rotsel_offset + 1; +constant ex1_pred_update_offset : integer := ex1_pred_taken_cnt_offset + ex1_pred_taken_cnt_q'length; +constant ex1_pri_offset : integer := ex1_pred_update_offset + 1; +constant ex1_rotsel_ovrd_offset : integer := ex1_pri_offset + ex1_pri_q'length; +constant ex1_s1_offset : integer := ex1_rotsel_ovrd_offset + ex1_rotsel_ovrd_q'length; +constant ex1_s2_offset : integer := ex1_s1_offset + ex1_s1_q'length; +constant ex1_s3_offset : integer := ex1_s2_offset + ex1_s2_q'length; +constant ex1_spr_sel_offset : integer := ex1_s3_offset + ex1_s3_q'length; +constant ex1_ta_offset : integer := ex1_spr_sel_offset + 1; +constant ex1_tid_offset : integer := ex1_ta_offset + ex1_ta_q'length; +constant ex1_tlb_data_val_offset : integer := ex1_tid_offset + ex1_tid_q'length; +constant ex1_tlb_illeg_offset : integer := ex1_tlb_data_val_offset + 1; +constant ex1_trace_type_offset : integer := ex1_tlb_illeg_offset + 1; +constant ex1_trace_val_offset : integer := ex1_trace_type_offset + ex1_trace_type_q'length; +constant ex1_val_offset : integer := ex1_trace_val_offset + 1; +constant ex1_axu_ld_or_st_offset : integer := ex1_val_offset + ex1_val_q'length; +constant ex2_act_offset : integer := ex1_axu_ld_or_st_offset + 1; +constant ex2_back_inv_offset : integer := ex2_act_offset + 1; +constant ex2_clear_barrier_offset : integer := ex2_back_inv_offset + 1; +constant ex2_ipb_ba_offset : integer := ex2_clear_barrier_offset + 1; +constant ex2_ipb_sz_offset : integer := ex2_ipb_ba_offset + ex2_ipb_ba_q'length; +constant ex2_gpr_we_offset : integer := ex2_ipb_sz_offset + ex2_ipb_sz_q'length; +constant ex2_is_ucode_offset : integer := ex2_gpr_we_offset + 1; +constant ex2_muldiv_coll_offset : integer := ex2_is_ucode_offset + 1; +constant ex2_need_hole_offset : integer := ex2_muldiv_coll_offset + 1; +constant ex2_val_offset : integer := ex2_need_hole_offset + 1; +constant ex3_act_offset : integer := ex2_val_offset + ex2_val_q'length; +constant ex3_axu_instr_type_offset : integer := ex3_act_offset + 1; +constant ex3_back_inv_offset : integer := ex3_axu_instr_type_offset + ex3_axu_instr_type_q'length; +constant ex3_bh_offset : integer := ex3_back_inv_offset + 1; +constant ex3_clear_barrier_offset : integer := ex3_bh_offset + ex3_bh_q'length; +constant ex3_ddmh_en_offset : integer := ex3_clear_barrier_offset + 1; +constant ex3_div_done_offset : integer := ex3_ddmh_en_offset + 1; +constant ex3_getNIA_offset : integer := ex3_div_done_offset + 1; +constant ex3_gpr_we_offset : integer := ex3_getNIA_offset + 1; +constant ex3_gshare_offset : integer := ex3_gpr_we_offset + 1; +constant ex3_instr_offset : integer := ex3_gshare_offset + ex3_gshare_q'length; +constant ex3_instr_hypv_offset : integer := ex3_instr_offset + ex3_instr_q'length; +constant ex3_instr_priv_offset : integer := ex3_instr_hypv_offset + 1; +constant ex3_is_any_store_offset : integer := ex3_instr_priv_offset + 1; +constant ex3_is_bclr_offset : integer := ex3_is_any_store_offset + 1; +constant ex3_is_eratsxr_offset : integer := ex3_is_bclr_offset + 1; +constant ex3_is_mfcr_offset : integer := ex3_is_eratsxr_offset + 1; +constant ex3_is_wchkall_offset : integer := ex3_is_mfcr_offset + 1; +constant ex3_lk_offset : integer := ex3_is_wchkall_offset + 1; +constant ex3_mfdp_val_offset : integer := ex3_lk_offset + 1; +constant ex3_mtdp_nr_offset : integer := ex3_mfdp_val_offset + 1; +constant ex3_mtdp_val_offset : integer := ex3_mtdp_nr_offset + 1; +constant ex3_muldiv_coll_offset : integer := ex3_mtdp_val_offset + 1; +constant ex3_need_hole_offset : integer := ex3_muldiv_coll_offset + 1; +constant ex3_pred_taken_cnt_offset : integer := ex3_need_hole_offset + 1; +constant ex3_pred_update_offset : integer := ex3_pred_taken_cnt_offset + ex3_pred_taken_cnt_q'length; +constant ex3_pri_offset : integer := ex3_pred_update_offset + 1; +constant ex3_slowspr_dcr_rd_offset : integer := ex3_pri_offset + ex3_pri_q'length; +constant ex3_ta_offset : integer := ex3_slowspr_dcr_rd_offset + 1; +constant ex3_tid_offset : integer := ex3_ta_offset + ex3_ta_q'length; +constant ex3_tlb_data_val_offset : integer := ex3_tid_offset + ex3_tid_q'length; +constant ex3_tlb_illeg_offset : integer := ex3_tlb_data_val_offset + 1; +constant ex3_trace_type_offset : integer := ex3_tlb_illeg_offset + 1; +constant ex3_trace_val_offset : integer := ex3_trace_type_offset + ex3_trace_type_q'length; +constant ex3_val_offset : integer := ex3_trace_val_offset + 1; +constant ex4_act_offset : integer := ex3_val_offset + ex3_val_q'length; +constant ex4_clear_barrier_offset : integer := ex4_act_offset + 1; +constant ex4_gpr_we_offset : integer := ex4_clear_barrier_offset + 1; +constant ex4_val_offset : integer := ex4_gpr_we_offset + 1; +constant ex5_act_offset : integer := ex4_val_offset + ex4_val_q'length; +constant ex5_bh_offset : integer := ex5_act_offset + 1; +constant ex5_clear_barrier_offset : integer := ex5_bh_offset + ex5_bh_q'length; +constant ex5_getNIA_offset : integer := ex5_clear_barrier_offset + 1; +constant ex5_gpr_we_offset : integer := ex5_getNIA_offset + 1; +constant ex5_gshare_offset : integer := ex5_gpr_we_offset + 1; +constant ex5_instr_offset : integer := ex5_gshare_offset + ex5_gshare_q'length; +constant ex5_is_bclr_offset : integer := ex5_instr_offset + ex5_instr_q'length; +constant ex5_lk_offset : integer := ex5_is_bclr_offset + 1; +constant ex5_pred_taken_cnt_offset : integer := ex5_lk_offset + 1; +constant ex5_pred_update_offset : integer := ex5_pred_taken_cnt_offset + ex5_pred_taken_cnt_q'length; +constant ex5_pri_offset : integer := ex5_pred_update_offset + 1; +constant ex5_slowspr_dcr_rd_offset : integer := ex5_pri_offset + ex5_pri_q'length; +constant ex5_ta_offset : integer := ex5_slowspr_dcr_rd_offset + ex5_slowspr_dcr_rd_q'length; +constant ex5_tid_offset : integer := ex5_ta_offset + ex5_ta_q'length; +constant ex5_val_offset : integer := ex5_tid_offset + ex5_tid_q'length; +constant ex6_clear_barrier_offset : integer := ex5_val_offset + ex5_val_q'length; +constant ex6_gpr_we_offset : integer := ex6_clear_barrier_offset + ex6_clear_barrier_q'length; +constant ex6_pri_offset : integer := ex6_gpr_we_offset + 1; +constant ex6_ta_offset : integer := ex6_pri_offset + ex6_pri_q'length; +constant ex6_val_offset : integer := ex6_ta_offset + ex6_ta_q'length; +constant ex7_gpr_we_offset : integer := ex6_val_offset + ex6_val_q'length; +constant ex7_ta_offset : integer := ex7_gpr_we_offset + 1; +constant ex7_val_offset : integer := ex7_ta_offset + ex7_ta_q'length; +constant an_ac_dcr_val_offset : integer := ex7_val_offset + ex7_val_q'length; +constant dcr_ack_offset : integer := an_ac_dcr_val_offset + 1; +constant dcr_act_offset : integer := dcr_ack_offset + 1; +constant dcr_etid_offset : integer := dcr_act_offset + 1; +constant dcr_read_offset : integer := dcr_etid_offset + dcr_etid_q'length; +constant dcr_val_offset : integer := dcr_read_offset + 1; +constant instr_trace_mode_offset : integer := dcr_val_offset + 1; +constant instr_trace_tid_offset : integer := instr_trace_mode_offset + 1; +constant lsu_xu_need_hole_offset : integer := instr_trace_tid_offset + instr_trace_tid_q'length; +constant lsu_xu_rel_ta_gpr_offset : integer := lsu_xu_need_hole_offset + 1; +constant lsu_xu_rel_wren_offset : integer := lsu_xu_rel_ta_gpr_offset + lsu_xu_rel_ta_gpr_q'length; +constant mmucr0_0_tlbsel_offset : integer := lsu_xu_rel_wren_offset + 1; +constant mmucr0_1_tlbsel_offset : integer := mmucr0_0_tlbsel_offset + mmucr0_0_tlbsel_q'length; +constant mmucr0_2_tlbsel_offset : integer := mmucr0_1_tlbsel_offset + mmucr0_1_tlbsel_q'length; +constant mmucr0_3_tlbsel_offset : integer := mmucr0_2_tlbsel_offset + mmucr0_2_tlbsel_q'length; +constant slowspr_etid_offset : integer := mmucr0_3_tlbsel_offset + mmucr0_3_tlbsel_q'length; +constant slowspr_rw_offset : integer := slowspr_etid_offset + slowspr_etid_q'length; +constant slowspr_val_offset : integer := slowspr_rw_offset + 1; +constant spr_ccr2_en_attn_offset : integer := slowspr_val_offset + 1; +constant spr_ccr2_en_dcr_offset : integer := spr_ccr2_en_attn_offset + 1; +constant spr_ccr2_en_ditc_offset : integer := spr_ccr2_en_dcr_offset + 1; +constant spr_ccr2_en_icswx_offset : integer := spr_ccr2_en_ditc_offset + 1; +constant spr_ccr2_en_pc_offset : integer := spr_ccr2_en_icswx_offset + 1; +constant spr_ccr2_notlb_offset : integer := spr_ccr2_en_pc_offset + 1; +constant spr_msr_cm_offset : integer := spr_ccr2_notlb_offset + 1; +constant t0_hold_ta_offset : integer := spr_msr_cm_offset + spr_msr_cm_q'length; +constant t1_hold_ta_offset : integer := t0_hold_ta_offset + t0_hold_ta_q'length; +constant t2_hold_ta_offset : integer := t1_hold_ta_offset + t1_hold_ta_q'length; +constant t3_hold_ta_offset : integer := t2_hold_ta_offset + t2_hold_ta_q'length; +constant trace_bus_enable_offset : integer := t3_hold_ta_offset + t3_hold_ta_q'length; +constant clkg_ctl_offset : integer := trace_bus_enable_offset + 1; +constant spr_bit_act_offset : integer := clkg_ctl_offset + 1; +constant spare_0_offset : integer := spr_bit_act_offset + 1; +constant spare_1_offset : integer := spare_0_offset + spare_0_q'length; +constant xu_dec_sspr_offset : integer := spare_1_offset + spare_1_q'length; +constant scan_right : integer := xu_dec_sspr_offset + 1; +signal siv : std_ulogic_vector(0 to scan_right-1); +signal sov : std_ulogic_vector(0 to scan_right-1); +signal spare_0_lclk : clk_logic; +signal spare_1_lclk : clk_logic; +signal spare_0_d1clk, spare_0_d2clk : std_ulogic; +signal spare_1_d1clk, spare_1_d2clk : std_ulogic; +signal rf0_opcode_is_31 : std_ulogic; +signal rf1_opcode_is_31, rf1_opcode_is_0, + rf1_opcode_is_19, rf1_opcode_is_62, rf1_opcode_is_58 : boolean; +signal + rf1_is_attn , rf1_is_bc , rf1_is_bclr , rf1_is_dcbf , rf1_is_dcbi , + rf1_is_dcbst , rf1_is_dcblc , rf1_is_dcbt , rf1_is_dcbtls , rf1_is_dcbtst , + rf1_is_dcbtstls , rf1_is_dcbz , rf1_is_dci , rf1_is_eratilx , rf1_is_erativax , + rf1_is_eratre , rf1_is_eratsx , rf1_is_eratsrx , rf1_is_eratwe , rf1_is_ici , + rf1_is_icbi , rf1_is_icblc , rf1_is_icbt , rf1_is_icbtls , rf1_is_isync , + rf1_is_ld , rf1_is_ldarx , rf1_is_ldbrx , rf1_is_ldu , rf1_is_lhbrx , + rf1_is_lmw , rf1_is_lswi , rf1_is_lswx , rf1_is_lwa , rf1_is_lwarx , + rf1_is_lwbrx , rf1_is_mfcr , rf1_is_mfdp , rf1_is_mfdpx , rf1_is_mtdp , + rf1_is_mtdpx , rf1_is_mfspr , rf1_is_mtcrf , rf1_is_mtmsr , rf1_is_mtspr , + rf1_is_neg , rf1_is_rfci , rf1_is_rfi , rf1_is_rfmci , rf1_is_sc , + rf1_is_std , rf1_is_stdbrx , rf1_is_stdcxr , rf1_is_stdu , rf1_is_sthbrx , + rf1_is_stwcxr , rf1_is_stwbrx , rf1_is_subf , rf1_is_subfc , rf1_is_subfe , + rf1_is_subfic , rf1_is_subfme , rf1_is_subfze , rf1_is_td , rf1_is_tdi , + rf1_is_tlbilx , rf1_is_tlbivax , rf1_is_tlbre , rf1_is_tlbsx , rf1_is_tlbsrx , + rf1_is_tlbwe , rf1_is_tlbwec , rf1_is_tw , rf1_is_twi , + rf1_is_wrtee , rf1_is_dcbstep , rf1_is_dcbtep , rf1_is_dcbfep , rf1_is_dcbtstep , + rf1_is_icbiep , rf1_is_dcbzep , rf1_is_rfgi , rf1_is_ehpriv , rf1_is_msgclr , + rf1_is_msgsnd , rf1_is_icswx , rf1_is_icswepx , rf1_is_wchkall , rf1_is_wclr , + rf1_is_mfdcr , rf1_is_mfdcrux , rf1_is_mfdcrx , rf1_is_mtdcr , rf1_is_mtdcrux , + rf1_is_mtdcrx , rf1_is_mulhd , rf1_is_mulhdu , rf1_is_mulhw , rf1_is_mulhwu , + rf1_is_mulld , rf1_is_mulli , rf1_is_mullw , rf1_is_divd , rf1_is_divdu , + rf1_is_divw , rf1_is_divwu , rf1_is_divwe , rf1_is_divweu , rf1_is_divde , + rf1_is_divdeu , rf1_is_eratsxr , rf1_is_tlbsxr : std_ulogic; +signal tiup : std_ulogic; +signal tidn : std_ulogic; +signal rf1_add_ext : std_ulogic; +signal rf1_sub : std_ulogic; +signal rf1_is_any_store : std_ulogic; +signal rf1_is_any_load_axu : std_ulogic; +signal rf1_is_any_store_axu : std_ulogic; +signal rf1_is_any_load_dac : std_ulogic; +signal rf1_is_any_store_dac : std_ulogic; +signal rf1_imm_size : std_ulogic; +signal rf1_imm_signext : std_ulogic; +signal rf1_16b_imm : std_ulogic_vector(0 to 15); +signal rf1_64b_imm : std_ulogic_vector(0 to 63); +signal rf1_imm_sign_ext : std_ulogic_vector(0 to 63); +signal rf1_imm_shifted : std_ulogic_vector(0 to 63); +signal rf1_shift_imm : std_ulogic; +signal rf1_zero_imm : std_ulogic; +signal rf1_ones_imm : std_ulogic; +signal rf1_gpr0_zero : std_ulogic; +signal rf1_cache_acc : std_ulogic; +signal rf1_touch_drop : std_ulogic; +signal rf1_wclr_all : std_ulogic; +signal rf1_xer_ca : std_ulogic; +signal rf1_xer_ca_update : std_ulogic; +signal rf1_xer_ov_update : std_ulogic; +signal rf1_lk : std_ulogic; +signal rf1_bh : std_ulogic_vector(0 to 1); +signal rf1_cmp : std_ulogic; +signal rf1_cmp_lfld : std_ulogic; +signal rf1_is_st_w_update : std_ulogic; +signal rf1_is_ld_w_update : std_ulogic; +signal rf1_rs0_byp_cmp, rf1_rs1_byp_cmp, rf1_rs2_byp_cmp : std_ulogic_vector(1 to 8); +signal rf1_rs0_byp_stageval, rf1_rs1_byp_stageval, rf1_rs2_byp_stageval : std_ulogic_vector(1 to 7); +signal rf1_rs0_byp_val : std_ulogic_vector(0 to 8); +signal rf1_rs1_byp_val : std_ulogic_vector(1 to 8); +signal rf1_rs2_byp_val : std_ulogic_vector(1 to 8); +signal rf1_rs0_sel : std_ulogic_vector(1 to 9); +signal rf1_rs1_sel : std_ulogic_vector(1 to 9); +signal rf1_rs2_sel : std_ulogic_vector(1 to 9); +signal rf1_cmp_uext : std_ulogic; +signal rf1_val_stg : std_ulogic; +signal rf1_val_w_ldstm : std_ulogic; +signal rf1_instr_priv : std_ulogic; +signal rf1_instr_hypv : std_ulogic; +signal rf1_use_crfld0 : std_ulogic; +signal rf1_use_crfld0_nmult : std_ulogic; +signal rf1_rs1_use_imm : std_ulogic; +signal ex3_tlbsel : std_ulogic_vector(12 to 13); +signal ex1_ipc_ln : std_ulogic_vector(0 to 1); +signal ex1_dp_rot_addr : std_ulogic_vector(0 to 5); +signal ex1_dp_rot_op_size : std_ulogic_vector(0 to 5); +signal ex1_dp_rot_r_amt : std_ulogic_vector(0 to 5); +signal ex1_dp_rot_l_amt : std_ulogic_vector(0 to 5); +signal ex1_dp_rot_dir : std_ulogic_vector(0 to 1); +signal ex1_dp_rot_amt : std_ulogic_vector(0 to 5); +signal rf1_mfdp : std_ulogic; +signal rf1_mtdp : std_ulogic; +signal rf1_derat_is_load : std_ulogic; +signal rf1_derat_is_store : std_ulogic; +signal rf1_tlbsel : std_ulogic_vector(12 to 12); +signal rf1_tlb_illeg_ws : std_ulogic; +signal rf1_tlb_illeg_ws2 : std_ulogic; +signal rf1_tlb_illeg_ws3 : std_ulogic; +signal rf1_tlb_illeg_sel : std_ulogic; +signal rf1_tlb_illeg_t : std_ulogic; +signal rf1_clear_barrier : std_ulogic; +signal rf1_th_fld_b0 : std_ulogic; +signal rf1_th_fld_c : std_ulogic; +signal rf1_th_fld_l2 : std_ulogic; +signal rf1_num_bytes : std_ulogic_vector(0 to 7); +signal rf1_num_bytes_plus3 : std_ulogic_vector(0 to 7); +signal ex1_lower_bnd : std_ulogic_vector(0 to 5); +signal ex1_upper_bnd : std_ulogic_vector(0 to 5); +signal ex1_upper_bnd_wrap : std_ulogic_vector(0 to 5); +signal ex2_ra_in_rng : std_ulogic; +signal ex2_rb_in_rng : std_ulogic; +signal slowspr_need_hole : std_ulogic; +signal rf1_src0_vld : std_ulogic; +signal rf1_src0_reg : std_ulogic_vector(0 to 7); +signal rf1_src1_vld : std_ulogic; +signal rf1_src1_reg : std_ulogic_vector(0 to 7); +signal rf1_targ_vld : std_ulogic; +signal rf1_targ_reg : std_ulogic_vector(0 to 7); +signal rf1_spr_msr_cm : std_ulogic; +signal rf1_spr_sel : std_ulogic; +signal rf1_is_trap : std_ulogic; +signal rf1_cr_so_update : std_ulogic_vector(0 to 1); +signal rf1_cr_we : std_ulogic; +signal rf1_alu_cmp : std_ulogic; +signal rf1_pri : std_ulogic_vector(0 to 2); +signal rf1_instr_hypv_other : std_ulogic; +signal rf1_instr_hypv_tbl : std_ulogic; +signal rf1_instr_priv_other : std_ulogic; +signal rf1_instr_priv_tbl : std_ulogic; +signal rf1_sel : std_ulogic_vector(0 to 3); +signal rf1_imm_size_tbl : std_ulogic; +signal rf1_imm_signext_tbl : std_ulogic; +signal rf1_getNIA : std_ulogic; +signal rf1_mtspr_trace : std_ulogic; +signal rf1_ldst_trgt_gate : std_ulogic; +signal rf1_axu_instr_type : std_ulogic_vector(0 to 2); +signal rf1_axu_ldst_forcealign : std_ulogic; +signal rf1_axu_ldst_forceexcept : std_ulogic; +signal rf1_axu_ldst_indexed_b : std_ulogic; +signal rf1_axu_mftgpr : std_ulogic; +signal rf1_axu_mffgpr : std_ulogic; +signal rf1_axu_movedp : std_ulogic; +signal rf1_axu_ldst_size : std_ulogic_vector(1 to 5); +signal rf1_axu_ldst_update : std_ulogic; +signal rf1_axu_instr_priv : std_ulogic; +signal ex1_is_slowspr_rd : std_ulogic; +signal ex1_is_slowspr_wr : std_ulogic; +signal ex5_slow_op_done : std_ulogic; +signal ex5_ta_etid : std_ulogic_vector(0 to 1); +signal ex5_hold_ta : std_ulogic_vector(t0_hold_ta_q'range); +signal dcr_val : std_ulogic; +signal rf1_xer_si_zero_b : std_ulogic; +signal rf1_spr_xer_si : std_ulogic_vector(0 to 6); +signal rf1_force_64b_cmp, rf1_force_32b_cmp : std_ulogic; +signal rf1_trace_mtspr, rf1_trace_ldst : std_ulogic; +signal instr_trace_tid : std_ulogic_vector(0 to threads-1); +signal rf1_is_touch, rf1_derat_ra_eq_ea : std_ulogic; +signal rf1_target_gpr : std_ulogic_vector(0 to 8); +signal rf1_cmd_act, rf1_derat_act : std_ulogic; +signal rf1_zero_imm_binv, rf1_ones_imm_binv : std_ulogic; + BEGIN + +tiup <= '1'; +tidn <= '0'; +ex1_val_d <= rf1_val_q and not xu_rf1_flush; +ex2_val_d <= ex1_val_q and not xu_ex1_flush; +ex3_val_d <= ex2_val_q and not xu_ex2_flush; +ex4_val_d <= ex3_val_q and not xu_ex3_flush; +ex5_val_d <= ex4_val_q and not xu_ex4_flush; +ex6_val_d <= ex5_val_q and not xu_ex5_flush; +rf1_val_stg <= or_reduce(rf1_val_q); +rf0_act <= fxa_fxb_rf0_act or rf0_back_inv_q or clkg_ctl_q; +dec_byp_rf0_act <= rf0_act; +ex1_act_d <= rf1_act_q; +ex2_act_d <= ex1_act_q; +ex3_act_d <= ex2_act_q; +ex4_act_d <= ex3_act_q; +ex5_act_d <= ex4_act_q; +dec_alu_rf1_act <= rf1_act_q; +dec_alu_ex1_act <= ex1_act_q; +rf1_spr_msr_cm <= or_reduce(spr_msr_cm_q and rf1_tid_q); +rf1_cmp_lfld <= rf1_instr_q(10); +rf1_force_64b_cmp <= rf1_is_tdi or rf1_is_td or (rf1_alu_cmp and rf1_cmp_lfld) or rf1_back_inv_q; +rf1_force_32b_cmp <= rf1_is_twi or rf1_is_tw or (rf1_alu_cmp and not rf1_cmp_lfld); +dec_alu_rf1_select_64bmode <= (rf1_spr_msr_cm and not rf1_force_32b_cmp) or rf1_force_64b_cmp; +rf1_axu_ldst_forcealign <= rf1_axu_ldst_forcealign_q and rf1_axu_ld_or_st_q; +rf1_axu_ldst_forceexcept <= rf1_axu_ldst_forceexcept_q and rf1_axu_ld_or_st_q; +rf1_axu_ldst_indexed_b <= not(rf1_axu_ldst_indexed_q) and rf1_axu_ld_or_st_q; +rf1_axu_mftgpr <= rf1_axu_mftgpr_q and rf1_axu_ld_or_st_q; +rf1_axu_mffgpr <= rf1_axu_mffgpr_q and rf1_axu_ld_or_st_q; +rf1_axu_movedp <= rf1_axu_movedp_q and rf1_axu_ld_or_st_q; +rf1_axu_ldst_size <= gate(rf1_axu_ldst_size_q(1 to 5), rf1_axu_ld_or_st_q); +rf1_axu_ldst_update <= rf1_axu_ldst_update_q and rf1_axu_ld_or_st_q; +rf1_axu_instr_type <= gate(rf1_axu_instr_type_q, (rf1_axu_ld_or_st_q or or_reduce(rf1_ucode_val_q))); +rf1_ldst_trgt_gate <= not(rf1_cache_acc) or rf1_is_st_w_update or rf1_axu_ldst_update; +ex1_gpr_we_d <= rf1_ta_vld_q and rf1_ldst_trgt_gate; +ex2_gpr_we_d <= ex1_gpr_we_q and not ex1_slowspr_dcr_rd; +ex4_gpr_we_d <= ex3_gpr_we_q; +ex5_gpr_we_d <= ex4_gpr_we_q; +ex6_gpr_we_d <= (or_reduce(ex6_val_d) and (lsu_xu_ex5_wren or ex5_gpr_we_q)) or ex5_slow_op_done; +fxb_fxa_ex7_we0 <= ex7_gpr_we_q; +fxb_fxa_ex7_wa0 <= ex7_ta_q; +with instr_trace_tid_q select + instr_trace_tid <= "1000" when "00", + "0100" when "01", + "0010" when "10", + "0001" when others; +rf1_trace_val <= instr_trace_mode_q and not rf1_is_ucode_q and + or_reduce((rf1_val_q or rf1_ucode_val_q) and instr_trace_tid and not cpl_dec_in_ucode); +rf1_trace_mtspr <= rf1_is_mtspr or rf1_is_mtmsr or rf1_is_mtcrf or rf1_is_wrtee; +rf1_trace_ldst <= rf1_is_any_load_dac or rf1_is_any_store_dac or rf1_is_icswx or rf1_is_icswepx; + WITH s2'(rf1_trace_mtspr & rf1_trace_ldst) SELECT rf1_trace_type <= "10" when "10", + "11" when "01", + "01" when others; +dec_cpl_rf1_instr_trace_val <= rf1_trace_val; +dec_byp_ex3_instr_trace_val <= ex3_trace_val_q and ex3_trace_type_q(0); +dec_cpl_ex3_instr_trace_val <= ex3_trace_val_q; +xu_lsu_ex2_instr_trace_val <= ex2_trace_val_q and and_reduce(ex2_trace_type_q); +dec_byp_ex3_instr_trace_gate <= ex3_trace_val_q and ex3_trace_type_q(0) and ex3_trace_type_q(1) and not or_reduce(spr_msr_cm_q and instr_trace_tid); +dec_cpl_rf1_instr_trace_type <= rf1_trace_type; +dcr_val <= an_ac_dcr_val and spr_ccr2_en_dcr_q; +dcr_val_d <= dcr_val or (dcr_val_q and or_reduce(ex4_val_q)); +dcr_ack <= (dcr_val_q and not or_reduce(ex4_val_q)); +dec_byp_ex4_dcr_ack <= dcr_ack; +an_ac_dcr_ack <= dcr_ack_q; +ex5_slow_op_done <= (slowspr_val_q and slowspr_rw_q ) or + ( dcr_ack and dcr_read_q); +dec_cpl_ex1_is_slowspr_wr <= ex1_is_slowspr_wr or (ex1_mtdcr_instr_q and spr_ccr2_en_dcr_q); +ex1_slowspr_dcr_rd <= ex1_is_slowspr_rd or ex1_mfdcr_instr_q; +ex5_slowspr_dcr_rd_d <= gate(ex4_val_q,ex4_slowspr_dcr_rd_q); +ex5_ta_etid <= gate(slowspr_etid_q,slowspr_val_q) or + gate( dcr_etid_q, dcr_val_q); +with ex5_ta_etid select + ex5_hold_ta <= t0_hold_ta_q when "00", + t1_hold_ta_q when "01", + t2_hold_ta_q when "10", + t3_hold_ta_q when others; +with ex5_slow_op_done select + ex6_ta_d <= ex5_ta_q when '0', + ex5_hold_ta & ex5_ta_etid when others; +xu_iu_ex6_pri <= ex6_pri_q; +xu_iu_ex6_pri_val <= gate(ex6_val_q,or_reduce(ex6_pri_q)); +xu_dec_sspr : entity work.xuq_dec_sspr(xuq_dec_sspr) + generic map( + expand_type => expand_type, + threads => threads, + ctr_size => spr_dec_spr_xucr0_ssdly'length) + port map( + nclk => nclk, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc, + mpw1_dc_b => mpw1_dc_b, + mpw2_dc_b => mpw2_dc_b, + func_sl_force => func_sl_force, + func_sl_thold_0_b => func_sl_thold_0_b, + sg_0 => sg_0, + scan_in => siv(xu_dec_sspr_offset), + scan_out => sov(xu_dec_sspr_offset), + rf1_act => rf1_act_q, + rf1_val => rf1_val_q, + rf1_instr => rf1_instr_q, + slowspr_need_hole => slowspr_need_hole, + spr_dec_spr_xucr0_ssdly => spr_dec_spr_xucr0_ssdly, + ex1_is_slowspr_rd => ex1_is_slowspr_rd, + ex1_is_slowspr_wr => ex1_is_slowspr_wr, + vdd => vdd, + gnd => gnd); +lsu_xu_need_hole_d <= lsu_xu_need_hole; +is1_need_hole_d <= slowspr_need_hole; +is2_need_hole_d <= is1_need_hole_q or an_ac_dcr_val_q; +xu_iu_need_hole <= slowspr_need_hole or an_ac_dcr_val_q or alu_dec_div_need_hole or lsu_xu_need_hole_q; +dec_spr_ex1_is_mtspr <= ex1_is_mtspr_q; +dec_spr_ex1_is_mfspr <= ex1_is_mfspr_q; +dec_spr_ex4_val <= ex4_val_q; +dec_cpl_rf1_ucode_val <= rf1_ucode_val_q; +ex2_is_any_load_dac <= ex2_is_any_load_dac_q; +ex2_is_any_store_dac <= ex2_is_any_store_dac_q; +dec_cpl_ex3_is_any_store <= ex3_is_any_store_q; +dec_cpl_ex3_instr_priv <= ex3_instr_priv_q; +dec_cpl_ex3_mtdp_nr <= ex3_mtdp_nr_q; +dec_cpl_ex3_instr_hypv <= ex3_instr_hypv_q; +ex1_axu_instr_type_d <= rf1_axu_instr_type; +dec_cpl_ex3_axu_instr_type <= ex3_axu_instr_type_q; +dec_cpl_rf1_issued <= rf1_issued_q; +dec_cpl_rf1_val <= rf1_val_q; +dec_spr_rf1_val <= rf1_val_q or rf1_ucode_val_q; +dec_cpl_rf1_instr <= rf1_instr_q; +dec_cpl_ex2_error <= ex2_error_q; +dec_cpl_ex2_match <= ex2_match_q; +dec_cpl_ex2_is_ucode <= ex2_is_ucode_q; +dec_fspr_ex1_instr <= ex1_instr_q(11 to 20); +dec_fspr_ex6_val <= ex6_val_q; +xu_iu_ex5_val <= or_reduce(ex5_val_q and not xu_ex5_flush); +xu_iu_ex5_tid <= ex5_tid_q; +xu_iu_ex5_br_update <= ex5_pred_update_q; +xu_iu_ex5_br_hist <= ex5_pred_taken_cnt_q; +xu_iu_ex5_bclr <= ex5_is_bclr_q; +xu_iu_ex5_lk <= ex5_lk_q; +xu_iu_ex5_bh <= ex5_bh_q; +xu_iu_ex5_gshare <= ex5_gshare_q; +rf1_getNIA <= rf1_is_bc and + (rf1_instr_q(6 to 10) = "10100") and + (rf1_instr_q(11 to 15) = "11111") and + (rf1_instr_q(16 to 29) = "00000000000001") and + not rf1_instr_q(30) and + rf1_instr_q(31); +xu_iu_ex5_getNIA <= ex5_getNIA_q; +dec_byp_ex5_instr <= ex5_instr_q(12 to 19); +dec_byp_rf1_instr <= rf1_instr_q(6 to 25); +dec_byp_rf1_cr_so_update <= rf1_cr_so_update(0) & (rf1_cr_so_update(1) or rf1_use_crfld0); +dec_byp_ex3_val <= ex3_val_q; +dec_byp_rf1_cr_we <= rf1_cr_we or rf1_use_crfld0_nmult; +dec_byp_rf1_use_crfld0 <= rf1_use_crfld0; +dec_byp_rf1_alu_cmp <= rf1_alu_cmp or rf1_use_crfld0; +dec_byp_rf1_is_mtocrf <= tidn; +dec_byp_rf1_byp_val(1) <= or_reduce(rf1_tid_q and ex1_val_q); +dec_byp_rf1_byp_val(2) <= or_reduce(rf1_tid_q and ex2_val_q); +dec_byp_rf1_byp_val(3) <= or_reduce(rf1_tid_q and ex3_val_q); +dec_byp_ex4_is_eratsxr <= ex4_is_eratsxr_q; +dec_cpl_rf1_ifar <= rf1_ifar_q; +dec_cpl_rf1_pred_taken_cnt <= rf1_pred_taken_cnt_q(0); +dcdmrg : entity work.xuq_dec_dcdmrg(xuq_dec_dcdmrg) + port map ( + i => rf1_instr_q, + dec_alu_rf1_sel_rot_log => open, + dec_alu_rf1_sh_right => dec_alu_rf1_sh_right, + dec_alu_rf1_sh_word => dec_alu_rf1_sh_word, + dec_alu_rf1_sgnxtd_byte => dec_alu_rf1_sgnxtd_byte, + dec_alu_rf1_sgnxtd_half => dec_alu_rf1_sgnxtd_half, + dec_alu_rf1_sgnxtd_wd => dec_alu_rf1_sgnxtd_wd, + dec_alu_rf1_sra_dw => dec_alu_rf1_sra_dw, + dec_alu_rf1_sra_wd => dec_alu_rf1_sra_wd, + dec_alu_rf1_chk_shov_dw => dec_alu_rf1_chk_shov_dw, + dec_alu_rf1_chk_shov_wd => dec_alu_rf1_chk_shov_wd, + dec_alu_rf1_use_me_ins_hi => dec_alu_rf1_use_me_ins_hi, + dec_alu_rf1_use_me_ins_lo => dec_alu_rf1_use_me_ins_lo, + dec_alu_rf1_use_mb_ins_hi => dec_alu_rf1_use_mb_ins_hi, + dec_alu_rf1_use_mb_ins_lo => dec_alu_rf1_use_mb_ins_lo, + dec_alu_rf1_use_me_rb_hi => dec_alu_rf1_use_me_rb_hi, + dec_alu_rf1_use_me_rb_lo => dec_alu_rf1_use_me_rb_lo, + dec_alu_rf1_use_mb_rb_hi => dec_alu_rf1_use_mb_rb_hi, + dec_alu_rf1_use_mb_rb_lo => dec_alu_rf1_use_mb_rb_lo, + dec_alu_rf1_use_rb_amt_hi => dec_alu_rf1_use_rb_amt_hi, + dec_alu_rf1_use_rb_amt_lo => dec_alu_rf1_use_rb_amt_lo, + dec_alu_rf1_zm_ins => dec_alu_rf1_zm_ins, + dec_alu_rf1_cr_logical => dec_alu_rf1_cr_logical, + dec_alu_rf1_cr_log_fcn => dec_alu_rf1_cr_log_fcn, + dec_alu_rf1_log_fcn => dec_alu_rf1_log_fcn, + dec_alu_rf1_me_ins_b => dec_alu_rf1_me_ins_b, + dec_alu_rf1_mb_ins => dec_alu_rf1_mb_ins, + dec_alu_rf1_sh_amt => dec_alu_rf1_sh_amt, + dec_alu_rf1_mb_gt_me => dec_alu_rf1_mb_gt_me); +rf1_is_isel_d <= '1' when fxa_fxb_rf0_instr(0 to 5) = "011111" and + fxa_fxb_rf0_instr(26 to 30) = "01111" else '0'; +dec_rf1_is_isel <= rf1_is_isel_q; +dec_alu_rf1_xer_ov_update <= rf1_xer_ov_update; +dec_alu_rf1_xer_ca_update <= rf1_xer_ca_update; +dec_rf1_tid <= rf1_tid_2_q; +dec_ex1_tid <= ex1_tid_q; +dec_ex2_tid <= ex2_tid_q; +dec_ex3_tid <= ex3_tid_q; +dec_ex4_tid <= ex4_tid_q; +dec_ex5_tid <= ex5_tid_q; +dec_byp_ex4_is_mfcr <= ex4_is_mfcr_q; +rf1_xer_si_zero_b <= or_reduce(rf1_spr_xer_si); +rf1_spr_xer_si <= (byp_xer_si(0 to 6) and (0 to 6 => rf1_tid_q(0))) or + (byp_xer_si(7 to 13) and (7 to 13 => rf1_tid_q(1))) or + (byp_xer_si(14 to 20) and (14 to 20 => rf1_tid_q(2))) or + (byp_xer_si(21 to 27) and (21 to 27 => rf1_tid_q(3))); +rf1_lk <= rf1_instr_q(31); +rf1_bh <= rf1_instr_q(19 to 20); +rf1_instr_hypv_other <= ((rf1_is_tlbwe or rf1_is_tlbsrx or rf1_is_tlbwec or rf1_is_tlbilx ) and or_reduce(spr_dec_rf1_epcr_dgtmi and rf1_val_q)) or + ((rf1_is_dcblc or rf1_is_dcbtls or rf1_is_dcbtstls or rf1_is_icblc or rf1_is_icbtls) and or_reduce(spr_dec_rf1_msrp_uclep and rf1_val_q)); +rf1_instr_hypv <= rf1_instr_hypv_tbl or rf1_instr_hypv_other; +rf1_axu_instr_priv <= rf1_axu_is_extstore_q or rf1_axu_is_extload_q or rf1_axu_movedp_q; +rf1_instr_priv_other <= (rf1_is_dcblc or rf1_is_dcbtls or rf1_is_dcbtstls or rf1_is_icblc or rf1_is_icbtls) + and not or_reduce(spr_dec_rf1_msr_ucle and rf1_val_q); +rf1_instr_priv <= rf1_instr_priv_tbl or rf1_instr_priv_other or (rf1_axu_ld_or_st_q and rf1_axu_instr_priv); +rf1_mfdcr_instr <= rf1_is_mfdcr or rf1_is_mfdcrux or rf1_is_mfdcrx; +rf1_mtdcr_instr <= rf1_is_mtdcr or rf1_is_mtdcrux or rf1_is_mtdcrx; + WITH s2'(rf1_is_lswi & rf1_is_lswx) SELECT rf1_num_bytes <= "00" & not or_reduce(rf1_instr_q(16 to 20)) & rf1_instr_q(16 to 20) when "10", + '0' & rf1_spr_xer_si when "01", + (others=>tidn) when others; +rf1_num_bytes_plus3 <= std_ulogic_vector(unsigned(rf1_num_bytes) + 3); +ex1_num_regs_d <= rf1_num_bytes_plus3(0 to 5); +ex1_lower_bnd <= ex1_ta_q(0 to 5); +ex1_upper_bnd <= std_ulogic_vector(unsigned(ex1_lower_bnd) + unsigned(ex1_num_regs_q)); +ex1_upper_bnd_wrap <= '0' & ex1_upper_bnd(1 to 5); +ex2_range_wrap_d <= ex1_upper_bnd(0); +ex2_ra_in_rng_lmw_d <= '1' when ex1_s1_q(0 to 5) >= ex1_lower_bnd else '0'; +ex2_ra_in_rng_nowrap_d <= '1' when (ex1_s1_q(0 to 5) >= ex1_lower_bnd) and + (ex1_s1_q(0 to 5) < ex1_upper_bnd) else '0'; +ex2_ra_in_rng_wrap_d <= '1' when (ex1_s1_q(0 to 5) < ex1_upper_bnd_wrap)else '0'; +ex2_ra_in_rng <= (ex2_ra_in_rng_nowrap_q ) or + (ex2_ra_in_rng_wrap_q and ex2_range_wrap_q); +ex2_rb_in_rng_nowrap_d <= '1' when (ex1_s2_q(0 to 5) >= ex1_lower_bnd) and + (ex1_s2_q(0 to 5) < ex1_upper_bnd) else '0'; +ex2_rb_in_rng_wrap_d <= '1' when (ex1_s2_q(0 to 5) < ex1_upper_bnd_wrap)else '0'; +ex2_rb_in_rng <= (ex2_rb_in_rng_nowrap_q ) or + (ex2_rb_in_rng_wrap_q and ex2_range_wrap_q); +ex2_ra_eq_zero_d <= '1' when ex1_s1_q(0 to 5) = "000000" else '0'; +ex2_ra_eq_rt_d <= (ex1_s1_q(0 to 5) = ex1_ta_q(0 to 5)) and not ex1_axu_ld_or_st_q; +ex2_rb_eq_rt_d <= '1' when ex1_s2_q(0 to 5) = ex1_ta_q(0 to 5) else '0'; +ex1_ditc_illeg_d <= (rf1_is_mfdp or rf1_is_mfdpx or rf1_is_mtdp or rf1_is_mtdpx) and + not rf1_instr_q(20) and rf1_instr_q(16); +ex2_ditc_illeg_d <= (ex1_axu_ld_or_st_q and ex1_axu_movedp_q and not ex1_ovr_rotsel_q) or + ex1_ditc_illeg_q; +dec_cpl_ex2_illegal_op <= ex2_ditc_illeg_q + or (ex2_is_icswx_q and not spr_ccr2_en_icswx_q) + or (ex2_is_attn_q and not spr_ccr2_en_attn_q) + or ((ex2_mtdp_val_q or ex2_mfdp_val_q) and not spr_ccr2_en_ditc_q) + or ((ex2_is_msgsnd_q or ex2_is_msgclr_q) and not spr_ccr2_en_pc_q) + or (ex2_is_st_w_update_q and ex2_ra_eq_zero_q) + or (ex2_is_ld_w_update_q and (ex2_ra_eq_zero_q or + ex2_ra_eq_rt_q)) + or (ex2_is_lmw_q and ex2_ra_in_rng_lmw_q) + or (ex2_is_lswi_q and ex2_ra_in_rng) + or (ex2_is_lswx_q and (ex2_ra_eq_rt_q or + ex2_rb_eq_rt_q or + ex2_ra_in_rng or + ex2_rb_in_rng)) + or (ex2_is_sc_q and or_reduce(ex2_instr_q(20 to 25))); +rf1_rs1_use_imm <= rf1_use_imm_q or + rf1_axu_ldst_indexed_b or + rf1_back_inv_q; +rf1_gpr0_zero <= rf1_gpr0_zero_q or rf1_back_inv_q; +rf1_rs0_byp_cmp(1) <= '1' when rf1_s1_q = ex1_ta_q else '0'; +rf1_rs0_byp_cmp(2) <= '1' when rf1_s1_q = ex2_ta_q else '0'; +rf1_rs0_byp_cmp(3) <= '1' when rf1_s1_q = ex3_ta_q else '0'; +rf1_rs0_byp_cmp(4) <= '1' when rf1_s1_q = ex4_ta_q else '0'; +rf1_rs0_byp_cmp(5) <= '1' when rf1_s1_q = ex5_ta_q else '0'; +rf1_rs0_byp_cmp(6) <= '1' when rf1_s1_q = ex6_ta_q else '0'; +rf1_rs0_byp_cmp(7) <= '1' when rf1_s1_q = ex7_ta_q else '0'; +rf1_rs0_byp_cmp(8) <= '1' when rf1_s1_q = lsu_xu_rel_ta_gpr_q else '0'; +rf1_rs0_byp_stageval(1) <= or_reduce(ex1_val_q) and ex1_gpr_we_q; +rf1_rs0_byp_stageval(2) <= or_reduce(ex2_val_q) and ex2_gpr_we_q; +rf1_rs0_byp_stageval(3) <= or_reduce(ex3_val_q) and ex3_gpr_we_q; +rf1_rs0_byp_stageval(4) <= or_reduce(ex4_val_q) and ex4_gpr_we_q; +rf1_rs0_byp_stageval(5) <= or_reduce(ex5_val_q) and ex5_gpr_we_q; +rf1_rs0_byp_stageval(6) <= or_reduce(ex6_val_q) and ex6_gpr_we_q; +rf1_rs0_byp_stageval(7) <= or_reduce(ex7_val_q) and ex7_gpr_we_q; +rf1_rs0_byp_val(0) <= rf1_gpr0_zero; +rf1_rs0_byp_val(1) <= rf1_rs0_byp_stageval(1) and rf1_s1_vld_q and rf1_rs0_byp_cmp(1); +rf1_rs0_byp_val(2) <= rf1_rs0_byp_stageval(2) and rf1_s1_vld_q and rf1_rs0_byp_cmp(2); +rf1_rs0_byp_val(3) <= rf1_rs0_byp_stageval(3) and rf1_s1_vld_q and rf1_rs0_byp_cmp(3); +rf1_rs0_byp_val(4) <= rf1_rs0_byp_stageval(4) and rf1_s1_vld_q and rf1_rs0_byp_cmp(4); +rf1_rs0_byp_val(5) <= rf1_rs0_byp_stageval(5) and rf1_s1_vld_q and rf1_rs0_byp_cmp(5); +rf1_rs0_byp_val(6) <= rf1_rs0_byp_stageval(6) and rf1_s1_vld_q and rf1_rs0_byp_cmp(6); +rf1_rs0_byp_val(7) <= rf1_rs0_byp_stageval(7) and rf1_s1_vld_q and rf1_rs0_byp_cmp(7); +rf1_rs0_byp_val(8) <= lsu_xu_rel_wren_q and rf1_s1_vld_q and rf1_rs0_byp_cmp(8); +rf1_rs0_sel(1) <= rf1_rs0_byp_val(1) and not rf1_rs0_byp_val(0); +rf1_rs0_sel(2) <= rf1_rs0_byp_val(2) and not or_reduce(rf1_rs0_byp_val(0 to 1)); +rf1_rs0_sel(3) <= rf1_rs0_byp_val(3) and not or_reduce(rf1_rs0_byp_val(0 to 2)); +rf1_rs0_sel(4) <= rf1_rs0_byp_val(4) and not or_reduce(rf1_rs0_byp_val(0 to 3)); +rf1_rs0_sel(5) <= rf1_rs0_byp_val(5) and not or_reduce(rf1_rs0_byp_val(0 to 4)); +rf1_rs0_sel(6) <= rf1_rs0_byp_val(6) and not or_reduce(rf1_rs0_byp_val(0 to 5)); +rf1_rs0_sel(7) <= rf1_rs0_byp_val(7) and not or_reduce(rf1_rs0_byp_val(0 to 6)); +rf1_rs0_sel(8) <= rf1_rs0_byp_val(8) and not or_reduce(rf1_rs0_byp_val(0 to 7)); +rf1_rs0_sel(9) <= not or_reduce(rf1_rs0_byp_val(0 to 8)); +dec_byp_rf1_rs0_sel <= rf1_rs0_sel(1 to 9); +rf1_rs1_byp_cmp(1) <= '1' when rf1_s2_q = ex1_ta_q else '0'; +rf1_rs1_byp_cmp(2) <= '1' when rf1_s2_q = ex2_ta_q else '0'; +rf1_rs1_byp_cmp(3) <= '1' when rf1_s2_q = ex3_ta_q else '0'; +rf1_rs1_byp_cmp(4) <= '1' when rf1_s2_q = ex4_ta_q else '0'; +rf1_rs1_byp_cmp(5) <= '1' when rf1_s2_q = ex5_ta_q else '0'; +rf1_rs1_byp_cmp(6) <= '1' when rf1_s2_q = ex6_ta_q else '0'; +rf1_rs1_byp_cmp(7) <= '1' when rf1_s2_q = ex7_ta_q else '0'; +rf1_rs1_byp_cmp(8) <= '1' when rf1_s2_q = lsu_xu_rel_ta_gpr_q else '0'; +rf1_rs1_byp_stageval(1) <= or_reduce(ex1_val_q) and ex1_gpr_we_q; +rf1_rs1_byp_stageval(2) <= or_reduce(ex2_val_q) and ex2_gpr_we_q; +rf1_rs1_byp_stageval(3) <= or_reduce(ex3_val_q) and ex3_gpr_we_q; +rf1_rs1_byp_stageval(4) <= or_reduce(ex4_val_q) and ex4_gpr_we_q; +rf1_rs1_byp_stageval(5) <= or_reduce(ex5_val_q) and ex5_gpr_we_q; +rf1_rs1_byp_stageval(6) <= or_reduce(ex6_val_q) and ex6_gpr_we_q; +rf1_rs1_byp_stageval(7) <= or_reduce(ex7_val_q) and ex7_gpr_we_q; +rf1_rs1_byp_val(1) <= rf1_rs1_byp_stageval(1) and rf1_s2_vld_q and rf1_rs1_byp_cmp(1); +rf1_rs1_byp_val(2) <= rf1_rs1_byp_stageval(2) and rf1_s2_vld_q and rf1_rs1_byp_cmp(2); +rf1_rs1_byp_val(3) <= rf1_rs1_byp_stageval(3) and rf1_s2_vld_q and rf1_rs1_byp_cmp(3); +rf1_rs1_byp_val(4) <= rf1_rs1_byp_stageval(4) and rf1_s2_vld_q and rf1_rs1_byp_cmp(4); +rf1_rs1_byp_val(5) <= rf1_rs1_byp_stageval(5) and rf1_s2_vld_q and rf1_rs1_byp_cmp(5); +rf1_rs1_byp_val(6) <= rf1_rs1_byp_stageval(6) and rf1_s2_vld_q and rf1_rs1_byp_cmp(6); +rf1_rs1_byp_val(7) <= rf1_rs1_byp_stageval(7) and rf1_s2_vld_q and rf1_rs1_byp_cmp(7); +rf1_rs1_byp_val(8) <= lsu_xu_rel_wren_q and rf1_s2_vld_q and rf1_rs1_byp_cmp(8); +rf1_rs1_sel(1) <= rf1_rs1_byp_val(1); +rf1_rs1_sel(2) <= rf1_rs1_byp_val(2) and not rf1_rs1_byp_val(1); +rf1_rs1_sel(3) <= rf1_rs1_byp_val(3) and not or_reduce(rf1_rs1_byp_val(1 to 2)); +rf1_rs1_sel(4) <= rf1_rs1_byp_val(4) and not or_reduce(rf1_rs1_byp_val(1 to 3)); +rf1_rs1_sel(5) <= rf1_rs1_byp_val(5) and not or_reduce(rf1_rs1_byp_val(1 to 4)); +rf1_rs1_sel(6) <= rf1_rs1_byp_val(6) and not or_reduce(rf1_rs1_byp_val(1 to 5)); +rf1_rs1_sel(7) <= rf1_rs1_byp_val(7) and not or_reduce(rf1_rs1_byp_val(1 to 6)); +rf1_rs1_sel(8) <= rf1_rs1_byp_val(8) and not or_reduce(rf1_rs1_byp_val(1 to 7)); +rf1_rs1_sel(9) <= not or_reduce(rf1_rs1_byp_val(1 to 8)); +dec_byp_rf1_rs1_sel <= rf1_rs1_sel(1 to 9) & rf1_rs1_use_imm; +rf1_rs2_byp_cmp(1) <= '1' when rf1_s3_q = ex1_ta_q else '0'; +rf1_rs2_byp_cmp(2) <= '1' when rf1_s3_q = ex2_ta_q else '0'; +rf1_rs2_byp_cmp(3) <= '1' when rf1_s3_q = ex3_ta_q else '0'; +rf1_rs2_byp_cmp(4) <= '1' when rf1_s3_q = ex4_ta_q else '0'; +rf1_rs2_byp_cmp(5) <= '1' when rf1_s3_q = ex5_ta_q else '0'; +rf1_rs2_byp_cmp(6) <= '1' when rf1_s3_q = ex6_ta_q else '0'; +rf1_rs2_byp_cmp(7) <= '1' when rf1_s3_q = ex7_ta_q else '0'; +rf1_rs2_byp_cmp(8) <= '1' when rf1_s3_q = lsu_xu_rel_ta_gpr_q else '0'; +rf1_rs2_byp_stageval(1) <= or_reduce(ex1_val_q) and ex1_gpr_we_q; +rf1_rs2_byp_stageval(2) <= or_reduce(ex2_val_q) and ex2_gpr_we_q; +rf1_rs2_byp_stageval(3) <= or_reduce(ex3_val_q) and ex3_gpr_we_q; +rf1_rs2_byp_stageval(4) <= or_reduce(ex4_val_q) and ex4_gpr_we_q; +rf1_rs2_byp_stageval(5) <= or_reduce(ex5_val_q) and ex5_gpr_we_q; +rf1_rs2_byp_stageval(6) <= or_reduce(ex6_val_q) and ex6_gpr_we_q; +rf1_rs2_byp_stageval(7) <= or_reduce(ex7_val_q) and ex7_gpr_we_q; +rf1_rs2_byp_val(1) <= rf1_rs2_byp_stageval(1) and rf1_s3_vld_q and rf1_rs2_byp_cmp(1); +rf1_rs2_byp_val(2) <= rf1_rs2_byp_stageval(2) and rf1_s3_vld_q and rf1_rs2_byp_cmp(2); +rf1_rs2_byp_val(3) <= rf1_rs2_byp_stageval(3) and rf1_s3_vld_q and rf1_rs2_byp_cmp(3); +rf1_rs2_byp_val(4) <= rf1_rs2_byp_stageval(4) and rf1_s3_vld_q and rf1_rs2_byp_cmp(4); +rf1_rs2_byp_val(5) <= rf1_rs2_byp_stageval(5) and rf1_s3_vld_q and rf1_rs2_byp_cmp(5); +rf1_rs2_byp_val(6) <= rf1_rs2_byp_stageval(6) and rf1_s3_vld_q and rf1_rs2_byp_cmp(6); +rf1_rs2_byp_val(7) <= rf1_rs2_byp_stageval(7) and rf1_s3_vld_q and rf1_rs2_byp_cmp(7); +rf1_rs2_byp_val(8) <= lsu_xu_rel_wren_q and rf1_s3_vld_q and rf1_rs2_byp_cmp(8); +rf1_rs2_sel(1) <= rf1_rs2_byp_val(1); +rf1_rs2_sel(2) <= rf1_rs2_byp_val(2) and not rf1_rs2_byp_val(1); +rf1_rs2_sel(3) <= rf1_rs2_byp_val(3) and not or_reduce(rf1_rs2_byp_val(1 to 2)); +rf1_rs2_sel(4) <= rf1_rs2_byp_val(4) and not or_reduce(rf1_rs2_byp_val(1 to 3)); +rf1_rs2_sel(5) <= rf1_rs2_byp_val(5) and not or_reduce(rf1_rs2_byp_val(1 to 4)); +rf1_rs2_sel(6) <= rf1_rs2_byp_val(6) and not or_reduce(rf1_rs2_byp_val(1 to 5)); +rf1_rs2_sel(7) <= rf1_rs2_byp_val(7) and not or_reduce(rf1_rs2_byp_val(1 to 6)); +rf1_rs2_sel(8) <= rf1_rs2_byp_val(8) and not or_reduce(rf1_rs2_byp_val(1 to 7)); +rf1_rs2_sel(9) <= not or_reduce(rf1_rs2_byp_val(1 to 8)); +dec_byp_rf1_rs2_sel <= rf1_rs2_sel(1 to 9); +dec_alu_rf1_sel(0) <= rf1_sel(0) or rf1_axu_ld_or_st_q or rf1_back_inv_q; +dec_alu_rf1_sel(1 TO 3) <= rf1_sel(1 to 3); +dec_alu_ex1_is_cmp <= ex1_is_cmp_q; +rf1_xer_ca <= byp_dec_rf1_xer_ca; + WITH s2'(rf1_add_ext & rf1_sub) SELECT dec_alu_rf1_add_ci <= rf1_xer_ca when "10", + '1' when "01", + '0' when others; +dec_alu_rf1_add_rs0_inv <= (others=> + (rf1_is_subf or rf1_is_subfc or rf1_is_subfe or + rf1_is_subfic or rf1_is_subfme or rf1_is_subfze or + rf1_is_neg or rf1_cmp)); +rf1_is_tlbsxr <= rf1_is_tlbsx and rf1_instr_q(31); +rf1_is_eratsxr <= rf1_is_eratsx and rf1_instr_q(31); +xu_mm_rf1_is_tlbsxr <= rf1_is_tlbsxr; +dec_alu_rf1_is_cmpl <= rf1_cmp_uext; +dec_alu_rf1_tw_cmpsel <= rf1_is_trap & rf1_instr_q(6 to 10); +dec_byp_ex1_spr_sel <= ex1_spr_sel_q; +xu_lsu_rf1_mtspr_trace <= rf1_mtspr_trace; +dec_alu_rf1_mul_ret <= rf1_is_mulhw or rf1_is_mulhwu or rf1_is_mulhd or rf1_is_mulhdu; +dec_alu_rf1_mul_size <= rf1_is_mulld or rf1_is_mulhd or rf1_is_mulhdu or rf1_is_mulli; +dec_alu_rf1_mul_imm <= rf1_is_mulli; +dec_alu_rf1_mul_sign <= not (rf1_is_mulhdu or rf1_is_mulhwu); +dec_alu_rf1_mul_recform <= rf1_instr_q(31) and + (rf1_is_mulhd or rf1_is_mulhdu or rf1_is_mulhw or + rf1_is_mulhwu or rf1_is_mulld or rf1_is_mullw); +dec_alu_rf1_div_size <= rf1_is_divd or rf1_is_divdu or + rf1_is_divde or rf1_is_divdeu; +dec_alu_rf1_div_extd <= rf1_is_divde or rf1_is_divdeu or + rf1_is_divwe or rf1_is_divweu; +dec_alu_rf1_div_sign <= rf1_is_divw or rf1_is_divd or + rf1_is_divwe or rf1_is_divde; +dec_alu_rf1_div_recform <= rf1_instr_q(31) and + (rf1_is_divd or rf1_is_divdu or + rf1_is_divw or rf1_is_divwu or + rf1_is_divde or rf1_is_divdeu or + rf1_is_divwe or rf1_is_divweu); +dec_cpl_ex3_mult_coll <= ex3_muldiv_coll_q or + ((ex3_div_done_q or alu_ex3_mul_done) and ex3_need_hole_q); +rf1_imm_size <= rf1_imm_size_tbl or rf1_axu_ldst_indexed_b; +rf1_imm_signext <= rf1_imm_signext_tbl or rf1_axu_ldst_indexed_b; + WITH (rf1_is_std or rf1_is_stdu or rf1_is_lwa or rf1_is_ld or rf1_is_ldu) SELECT rf1_16b_imm <= rf1_instr_q(16 to 31) when '0', + rf1_instr_q(16 to 29) & (30 to 31 => tidn) when others; +with rf1_back_inv_q select + rf1_64b_imm <= (0 to (63-real_data_add) => '0') & rf1_back_inv_addr_q & ((64-cl_size) to 63 => '0') when '1', + (0 to 37 => '0') & rf1_instr_q(6 to 31) when others; + WITH s2'((rf1_imm_size and not rf1_back_inv_q) & rf1_imm_signext) SELECT rf1_imm_sign_ext <= (0 to 47 => rf1_16b_imm(0)) & rf1_16b_imm when "11", + (0 to 47 => '0') & rf1_16b_imm when "10", + rf1_64b_imm when others; + WITH (rf1_shift_imm and not rf1_back_inv_q) SELECT rf1_imm_shifted <= rf1_imm_sign_ext when '0', + rf1_imm_sign_ext(16 to 63) & (48 to 63 => '0') when others; +rf1_zero_imm_binv <= rf1_zero_imm and not rf1_back_inv_q; +rf1_ones_imm_binv <= rf1_ones_imm and not rf1_back_inv_q; +dec_byp_rf1_imm <= (rf1_imm_shifted(64-regsize to 63) and (not (64-regsize to 63 => rf1_zero_imm_binv))) or (64-regsize to 63 => rf1_ones_imm_binv); +dec_byp_ex4_is_wchkall <= ex4_is_wchkall_q; +rf1_mfdp <= rf1_is_mfdp or rf1_is_mfdpx or (rf1_axu_mffgpr and rf1_axu_movedp); +rf1_mtdp <= rf1_is_mtdp or rf1_is_mtdpx or (rf1_axu_mftgpr and rf1_axu_movedp); +ex1_mtdp_nr_d <= (rf1_is_mtdp or rf1_is_mtdpx) and not rf1_instr_q(31); +ex1_mtdp_val_d <= rf1_mtdp; +ex1_mfdp_val_d <= rf1_mfdp; +ex4_dp_instr_d <= ex3_mtdp_val_q or ex3_mfdp_val_q; +dec_byp_ex4_dp_instr <= ex4_dp_instr_q and spr_ccr2_en_ditc_q; +dec_byp_ex4_mtdp_val <= ex4_mtdp_val_q and spr_ccr2_en_ditc_q and or_reduce(ex4_val_q); +dec_byp_ex4_mfdp_val <= ex4_mfdp_val_q and spr_ccr2_en_ditc_q and or_reduce(ex4_val_q); +xu_bx_ex1_mtdp_val <= ex1_mtdp_val_q and or_reduce(ex2_val_d); +xu_bx_ex1_mfdp_val <= ex1_mfdp_val_q and or_reduce(ex2_val_d); +xu_bx_ex1_ipc_thrd <= "00" when ex1_tid_q = "1000" else + "01" when ex1_tid_q = "0100" else + "10" when ex1_tid_q = "0010" else + "11" when ex1_tid_q = "0001" else + "00"; +ex1_dp_indexed_d <= rf1_is_mtdpx or rf1_is_mfdpx or + ((rf1_axu_mffgpr or rf1_axu_mftgpr) and rf1_axu_movedp and not rf1_axu_ldst_indexed_b); +with ex1_dp_indexed_q select + ex2_ipb_ba_d <= ex1_instr_q(11 to 15) when '0', + alu_dec_ex1_ipb_ba(27 to 31) when others; +xu_bx_ex2_ipc_ba <= ex2_ipb_ba_q; +ex2_ipb_sz_d <= ex1_instr_q(16 to 17); +xu_bx_ex2_ipc_sz <= ex2_ipb_sz_q; +ex1_ipc_ln <= ex1_instr_q(18 to 19); +ex1_dp_rot_addr <= "01" & ex2_ipb_ba_d(3 to 4) & "00"; +with ex2_ipb_sz_d select + ex1_dp_rot_op_size <= "010000" when "10", + "001000" when "01", + "000100" when "00", + "000000" when others; +ex1_dp_rot_r_amt <= std_ulogic_vector(unsigned(ex1_dp_rot_addr) + unsigned(ex1_dp_rot_op_size)); +ex1_dp_rot_l_amt <= std_ulogic_vector(32 - unsigned(ex1_dp_rot_r_amt)); +ex1_dp_rot_dir <= "10" when (ex2_ipb_ba_d(3 to 4) < ex1_ipc_ln) or (ex1_axu_movedp_q = '0') else + "00" when ex2_ipb_ba_d(3 to 4) = ex1_ipc_ln else + "01" when ex2_ipb_ba_d(3 to 4) > ex1_ipc_ln else + "11"; +with ex1_dp_rot_dir select + ex1_dp_rot_amt <= "000000" when "00", + ex1_dp_rot_r_amt when "01", + ex1_dp_rot_l_amt when "10", + "000000" when others; +ex1_ovr_rotsel_d <= rf1_axu_mffgpr or rf1_axu_mftgpr; +ex1_epid_instr_d <= rf1_xu_epid_instr_q or rf1_axu_is_extload_q or rf1_axu_is_extstore_q; +dec_cpl_ex1_epid_instr <= ex1_epid_instr_q; +xu_lsu_rf1_is_touch <= rf1_is_touch; +rf1_is_touch <= rf1_is_dcbt or rf1_is_dcbtep or rf1_is_dcbtst or rf1_is_dcbtstep or rf1_is_icbt or + ((rf1_is_dcbtls or rf1_is_dcbtstls or rf1_is_dcblc) and not (rf1_th_fld_c or rf1_th_fld_l2)) or + ((rf1_is_icbtls or rf1_is_icblc) and not (rf1_th_fld_c or rf1_th_fld_l2)); +rf1_th_fld_b0 <= rf1_instr_q(6) and (rf1_is_dcbt or rf1_is_dcbtep or rf1_is_dcbtst or rf1_is_dcbtstep); +rf1_th_fld_c <= '1' when (rf1_th_fld_b0='0' and (rf1_instr_q(7 to 10) = "0000")) else '0'; +rf1_th_fld_l2 <= '1' when (rf1_th_fld_b0='0' and (rf1_instr_q(7 to 10) = "0010")) else '0'; +xu_lsu_rf1_target_gpr <= rf1_target_gpr; +with rf1_axu_ld_or_st_q select + rf1_target_gpr <= '0' & rf1_ta_q(0 to 7) when '0', + rf1_axu_ldst_tag_q when others; +ex1_rotsel_ovrd_d <= rf1_axu_ldst_size(1 to 5); +xu_lsu_rf1_derat_ra_eq_ea <= rf1_derat_ra_eq_ea; +rf1_derat_ra_eq_ea <= rf1_back_inv_q or (rf1_val_stg and rf1_is_msgsnd) or rf1_mtspr_trace; +xu_lsu_rf1_thrd_id <= rf1_tid_q; +xu_lsu_rf1_axu_op_val <= rf1_axu_ld_or_st_q; +xu_lsu_rf1_axu_ldst_falign <= rf1_axu_ldst_forcealign and rf1_val_stg; +xu_lsu_rf1_axu_ldst_fexcpt <= rf1_axu_ldst_forceexcept and rf1_val_stg; +with ex1_ovr_rotsel_q select + xu_lsu_ex1_rotsel_ovrd <= ex1_rotsel_ovrd_q when '1', + ex1_dp_rot_amt(1 to 5) when others; +xu_lsu_rf0_act <= rf0_act; +xu_lsu_rf1_cache_acc <= rf1_cache_acc; +rf1_touch_drop <= (rf1_is_dcbt or rf1_is_dcbtep or rf1_is_dcbtst or rf1_is_dcbtstep or rf1_is_icbt or + rf1_is_dcbtls or rf1_is_dcbtstls or rf1_is_dcblc or rf1_is_icbtls or rf1_is_icblc) and not (rf1_th_fld_l2 or rf1_th_fld_c); +rf1_wclr_all <= rf1_is_wclr and not rf1_instr_q(9); +ex1_ddmh_en_d <= rf1_cache_acc and not (rf1_touch_drop or rf1_wclr_all); +dec_cpl_ex3_ddmh_en <= ex3_ddmh_en_q; +dec_cpl_ex3_back_inv <= ex3_back_inv_q; +xu_lsu_rf1_load_instr <= rf1_is_any_load_axu; +xu_lsu_rf1_store_instr <= rf1_is_any_store_axu; +xu_lsu_rf1_l_fld <= rf1_instr_q(9 to 10); +xu_lsu_rf1_th_fld <= rf1_instr_q(6 to 10); +xu_lsu_rf1_mutex_hint <= rf1_instr_q(31); +xu_lsu_rf1_byte_rev <= not or_reduce(rf1_ucode_val_q) and (rf1_is_lhbrx or rf1_is_lwbrx or rf1_is_ldbrx or rf1_is_sthbrx or rf1_is_stwbrx or rf1_is_stdbrx); +xu_lsu_rf1_dcbf_instr <= rf1_is_dcbf or rf1_is_dcbfep; +xu_lsu_rf1_dcbi_instr <= rf1_is_dcbi; +xu_lsu_rf1_dcbz_instr <= rf1_is_dcbz or rf1_is_dcbzep; +xu_lsu_rf1_dcbt_instr <= rf1_is_dcbt or rf1_is_dcbtep; +xu_lsu_rf1_dcbtst_instr <= rf1_is_dcbtst or rf1_is_dcbtstep; +xu_lsu_rf1_dcbtls_instr <= rf1_is_dcbtls; +xu_lsu_rf1_dcbtstls_instr <= rf1_is_dcbtstls; +xu_lsu_rf1_dcblc_instr <= rf1_is_dcblc; +xu_lsu_rf1_dcbst_instr <= rf1_is_dcbst or rf1_is_dcbstep; +xu_lsu_rf1_icbi_instr <= rf1_is_icbi or rf1_is_icbiep; +xu_lsu_rf1_icblc_instr <= rf1_is_icblc; +xu_lsu_rf1_icbt_instr <= rf1_is_icbt; +xu_lsu_rf1_icbtls_instr <= rf1_is_icbtls; +xu_lsu_rf1_lock_instr <= rf1_is_ldarx or rf1_is_lwarx or rf1_is_stdcxr or rf1_is_stwcxr; +xu_lsu_rf1_dci_instr <= rf1_is_dci and rf1_val_stg; +xu_lsu_rf1_ici_instr <= rf1_is_ici and rf1_val_stg; +xu_iu_rf1_val <= rf1_val_iu_q; +xu_rf1_val <= rf1_val_q; +xu_rf1_is_tlbre <= rf1_is_tlbre; +xu_rf1_is_tlbwe <= rf1_is_tlbwe; +xu_rf1_is_tlbsx <= rf1_is_tlbsx; +xu_rf1_is_tlbsrx <= rf1_is_tlbsrx; +xu_rf1_is_tlbilx <= rf1_is_tlbilx; +xu_rf1_is_tlbivax <= rf1_is_tlbivax; +xu_rf1_is_eratre <= rf1_is_eratre; +xu_rf1_is_eratwe <= rf1_is_eratwe; +xu_rf1_is_eratsx <= rf1_is_eratsx; +xu_rf1_is_eratsrx <= rf1_is_eratsrx; +xu_rf1_is_eratilx <= rf1_is_eratilx; +xu_rf1_is_erativax <= rf1_is_erativax; +xu_lsu_rf1_cmd_act <= rf1_cmd_act or or_reduce(rf1_ucode_val_q); +xu_lsu_rf1_derat_act <= rf1_derat_act or or_reduce(rf1_ucode_val_q) or (rf1_val_stg and (rf1_is_isync or rf1_is_csync or rf1_is_eratre or rf1_is_eratwe or + rf1_is_eratsx or rf1_is_eratilx or (rf1_is_wclr and rf1_instr_q(9)))); +xu_lsu_rf1_derat_is_load <= rf1_derat_is_load or (rf1_is_wclr and rf1_instr_q(9)); +xu_lsu_rf1_derat_is_store <= rf1_derat_is_store; +xu_rf1_ws <= rf1_instr_q(19 to 20); +xu_rf1_t <= rf1_instr_q(8 to 10); +xu_ex1_is_isync <= ex1_is_isync_q; +xu_ex1_is_csync <= ex1_is_csync_q; +rf1_is_csync <= rf1_is_sc or rf1_is_mtmsr or rf1_is_ehpriv or + rf1_is_rfi or rf1_is_rfci or rf1_is_rfmci or rf1_is_rfgi or + (rf1_is_mtspr and ((rf1_instr_q(11 to 20) = "1000000001") or + (rf1_instr_q(11 to 20) = "1001001010"))); +rf1_mc_dep_chk_val_d <= fxa_fxb_rf0_mc_dep_chk_val; +rf1_val_w_ldstm <= rf1_val_stg or + or_reduce(rf1_mc_dep_chk_val_q) or + or_reduce(rf1_ucode_val_q); +rf1_targ_vld <= rf1_ta_vld_q when rf1_3src_instr_q = '0' else rf1_s3_vld_q; +rf1_targ_reg <= rf1_ta_q when rf1_3src_instr_q = '0' else rf1_s3_q; +rf1_src0_vld <= rf1_s1_vld_q when rf1_3src_instr_q = '0' else rf1_s1_vld_q; +rf1_src0_reg <= rf1_s1_q when rf1_3src_instr_q = '0' else rf1_s1_q; +rf1_src1_vld <= rf1_s2_vld_q when rf1_3src_instr_q = '0' else rf1_s2_vld_q; +rf1_src1_reg <= rf1_s2_q when rf1_3src_instr_q = '0' else rf1_s2_q; +xu_lsu_rf1_targ_vld <= rf1_targ_vld and rf1_val_w_ldstm; +xu_lsu_rf1_targ_reg <= rf1_targ_reg; +xu_lsu_rf1_src0_vld <= rf1_src0_vld and rf1_val_w_ldstm and not rf1_gpr0_zero_q; +xu_lsu_rf1_src0_reg <= rf1_src0_reg; +xu_lsu_rf1_src1_vld <= rf1_src1_vld and rf1_val_w_ldstm; +xu_lsu_rf1_src1_reg <= rf1_src1_reg; +ex3_tlbsel <= mmucr0_0_tlbsel_q when ex3_tid_q = "1000" else + mmucr0_1_tlbsel_q when ex3_tid_q = "0100" else + mmucr0_2_tlbsel_q when ex3_tid_q = "0010" else + mmucr0_3_tlbsel_q when ex3_tid_q = "0001" else + "00"; + WITH s3'(ex3_tlb_data_val_q & ex3_tlbsel) SELECT dec_byp_ex3_tlb_sel <= "10" when "111", + "01" when "110", + "00" when others; +ex1_tlb_data_val_d <= rf1_is_eratre or rf1_is_eratsx; +rf1_tlbsel(12) <= mmucr0_0_tlbsel_q(4) when rf1_tid_q = "1000" else + mmucr0_1_tlbsel_q(4) when rf1_tid_q = "0100" else + mmucr0_2_tlbsel_q(4) when rf1_tid_q = "0010" else + mmucr0_3_tlbsel_q(4) when rf1_tid_q = "0001" else + '0'; +rf1_tlb_illeg_ws <= (rf1_is_eratwe or rf1_is_eratre) and rf1_instr_q(16 to 18)/="000"; +rf1_tlb_illeg_ws2 <= (rf1_is_eratwe or rf1_is_eratre) and rf1_instr_q(19 to 20)="10" and rf1_spr_msr_cm; +rf1_tlb_illeg_ws3 <= rf1_is_eratwe and rf1_instr_q(19 to 20)="11" and rf1_tlbsel(12)='0'; +rf1_tlb_illeg_t <= rf1_is_tlbilx and rf1_instr_q(8 to 10) = "010"; +rf1_tlb_illeg_sel <= ((rf1_is_tlbwe or rf1_is_tlbre or rf1_is_tlbsx or rf1_is_tlbsrx or rf1_is_tlbilx or rf1_is_tlbivax) and spr_ccr2_notlb_q) + or ((rf1_is_eratwe or rf1_is_eratre or rf1_is_eratsx) and not rf1_tlbsel(12)) + or ((rf1_is_erativax) and not spr_ccr2_notlb_q); +ex1_tlb_illeg_d <= rf1_tlb_illeg_ws or rf1_tlb_illeg_ws2 or rf1_tlb_illeg_ws3 or rf1_tlb_illeg_sel or rf1_tlb_illeg_t; +dec_cpl_ex3_tlb_illeg <= ex3_tlb_illeg_q; +rf1_clear_barrier <= rf1_is_mtmsr or rf1_is_rfci or rf1_is_rfi or rf1_is_rfmci or rf1_is_sc or rf1_is_rfgi or rf1_is_isync; +ex6_clear_barrier_d <= (0 to threads-1 => ex5_clear_barrier_q) and ex6_val_d; +fxb_fxa_ex6_clear_barrier <= ex6_clear_barrier_q; +byp_grp3_debug <= ex1_s1_q & ex1_ta_q(0 to 5) & ex1_gpr_we_q; +byp_grp4_debug <= ex1_s2_q & ex1_ta_q(0 to 5); +byp_grp5_debug <= ex1_s3_q & ex1_ta_q(0 to 5) & ex1_gpr_we_q; +dec_grp0_debug <= rf1_ucode_val_q & + rf1_val_q & + rf1_instr_q & + rf1_cache_acc & + rf1_axu_ld_or_st_q & + rf1_is_any_load_axu & + rf1_is_any_store_axu & + rf1_derat_is_load & + rf1_derat_is_store & + rf1_derat_ra_eq_ea & + rf1_axu_ldst_forcealign & + rf1_axu_ldst_forceexcept & + rf1_is_any_load_dac & + rf1_is_any_store_dac & + rf1_is_touch & + rf1_target_gpr & + rf1_targ_vld & + rf1_targ_reg & + rf1_src0_vld & + rf1_src0_reg & + rf1_src1_vld & + rf1_src1_reg; +dec_grp1_debug <= rf1_ucode_val_q & + rf1_val_q & + rf1_instr_q & + rf1_cache_acc & + rf1_axu_ld_or_st_q & + rf1_is_any_load_axu & + rf1_is_any_store_axu & + rf1_derat_is_load & + rf1_derat_is_store & + rf1_derat_ra_eq_ea & + rf1_axu_ldst_forcealign & + rf1_axu_ldst_forceexcept & + rf1_is_any_load_dac & + rf1_is_any_store_dac & + rf1_back_inv_q & + rf1_back_inv_addr_q; +rf1_is_attn <= '1' when rf1_opcode_is_0 and rf1_instr_21to30_00_q(21 to 30) = "0100000000" else '0'; +rf1_is_bc <= '1' when rf1_instr_q( 0 to 5) = "010000" else '0'; +rf1_is_bclr <= '1' when rf1_opcode_is_19 and rf1_instr_21to30_00_q(21 to 30) = "0000010000" else '0'; +rf1_is_dcbf <= '1' when rf1_opcode_is_31_q(0) = '1' and rf1_instr_21to30_00_q(21 to 30) = "0001010110" else '0'; +rf1_is_dcbi <= '1' when rf1_opcode_is_31_q(0) = '1' and rf1_instr_21to30_00_q(21 to 30) = "0111010110" else '0'; +rf1_is_dcbst <= '1' when rf1_opcode_is_31_q(0) = '1' and rf1_instr_21to30_00_q(21 to 30) = "0000110110" else '0'; +rf1_is_dcblc <= '1' when rf1_opcode_is_31_q(0) = '1' and rf1_instr_21to30_00_q(21 to 30) = "0110000110" else '0'; +rf1_is_dcbt <= '1' when rf1_opcode_is_31_q(0) = '1' and rf1_instr_21to30_00_q(21 to 30) = "0100010110" else '0'; +rf1_is_dcbtls <= '1' when rf1_opcode_is_31_q(0) = '1' and rf1_instr_21to30_00_q(21 to 30) = "0010100110" else '0'; +rf1_is_dcbtst <= '1' when rf1_opcode_is_31_q(0) = '1' and rf1_instr_21to30_01_q(21 to 30) = "0011110110" else '0'; +rf1_is_dcbtstls <= '1' when rf1_opcode_is_31_q(0) = '1' and rf1_instr_21to30_01_q(21 to 30) = "0010000110" else '0'; +rf1_is_dcbz <= '1' when rf1_opcode_is_31_q(1) = '1' and rf1_instr_21to30_01_q(21 to 30) = "1111110110" else '0'; +rf1_is_dci <= '1' when rf1_opcode_is_31_q(1) = '1' and rf1_instr_21to30_01_q(21 to 30) = "0111000110" else '0'; +rf1_is_eratilx <= '1' when rf1_opcode_is_31_q(1) = '1' and rf1_instr_21to30_01_q(21 to 30) = "0000110011" else '0'; +rf1_is_erativax <= '1' when rf1_opcode_is_31_q(1) = '1' and rf1_instr_21to30_01_q(21 to 30) = "1100110011" else '0'; +rf1_is_eratre <= '1' when rf1_opcode_is_31_q(1) = '1' and rf1_instr_21to30_01_q(21 to 30) = "0010110011" else '0'; +rf1_is_eratsx <= '1' when rf1_opcode_is_31_q(1) = '1' and rf1_instr_21to30_01_q(21 to 30) = "0010010011" else '0'; +rf1_is_eratsrx <= '1' when rf1_opcode_is_31_q(1) = '1' and rf1_instr_21to30_02_q(21 to 30) = "1101110011" else '0'; +rf1_is_eratwe <= '1' when rf1_opcode_is_31_q(1) = '1' and rf1_instr_21to30_02_q(21 to 30) = "0011010011" else '0'; +rf1_is_ici <= '1' when rf1_opcode_is_31_q(2) = '1' and rf1_instr_21to30_02_q(21 to 30) = "1111000110" else '0'; +rf1_is_icbi <= '1' when rf1_opcode_is_31_q(2) = '1' and rf1_instr_21to30_02_q(21 to 30) = "1111010110" else '0'; +rf1_is_icblc <= '1' when rf1_opcode_is_31_q(2) = '1' and rf1_instr_21to30_02_q(21 to 30) = "0011100110" else '0'; +rf1_is_icbt <= '1' when rf1_opcode_is_31_q(2) = '1' and rf1_instr_21to30_02_q(21 to 30) = "0000010110" else '0'; +rf1_is_icbtls <= '1' when rf1_opcode_is_31_q(2) = '1' and rf1_instr_21to30_02_q(21 to 30) = "0111100110" else '0'; +rf1_is_isync <= '1' when rf1_opcode_is_19 and rf1_instr_21to30_02_q(21 to 30) = "0010010110" else '0'; +rf1_is_ld <= '1' when rf1_opcode_is_58 and rf1_instr_q(30 to 31) = "00" else '0'; +rf1_is_ldarx <= '1' when rf1_opcode_is_31_q(2) = '1' and rf1_instr_21to30_03_q(21 to 30) = "0001010100" else '0'; +rf1_is_ldbrx <= '1' when rf1_opcode_is_31_q(2) = '1' and rf1_instr_21to30_03_q(21 to 30) = "1000010100" else '0'; +rf1_is_ldu <= '1' when rf1_opcode_is_58 and rf1_instr_q(30 to 31) = "01" else '0'; +rf1_is_lhbrx <= '1' when rf1_opcode_is_31_q(2) = '1' and rf1_instr_21to30_03_q(21 to 30) = "1100010110" else '0'; +rf1_is_lmw <= '1' when rf1_instr_q( 0 to 5) = "101110" else '0'; +rf1_is_lswi <= '1' when rf1_opcode_is_31_q(3) = '1' and rf1_instr_21to30_03_q(21 to 30) = "1001010101" else '0'; +rf1_is_lswx <= '1' when rf1_opcode_is_31_q(3) = '1' and rf1_instr_21to30_03_q(21 to 30) = "1000010101" else '0'; +rf1_is_lwa <= '1' when rf1_opcode_is_58 and rf1_instr_q(30 to 31) = "10" else '0'; +rf1_is_lwarx <= '1' when rf1_opcode_is_31_q(3) = '1' and rf1_instr_21to30_03_q(21 to 30) = "0000010100" else '0'; +rf1_is_lwbrx <= '1' when rf1_opcode_is_31_q(3) = '1' and rf1_instr_21to30_03_q(21 to 30) = "1000010110" else '0'; +rf1_is_mfcr <= '1' when rf1_opcode_is_31_q(3) = '1' and (rf1_instr_21to30_03_q(21 to 30) & rf1_instr_q(11) = "00000100110") else '0'; +rf1_is_mfdp <= '1' when rf1_opcode_is_31_q(3) = '1' and rf1_instr_21to30_04_q(21 to 30) = "0000100011" else '0'; +rf1_is_mfdpx <= '1' when rf1_opcode_is_31_q(3) = '1' and rf1_instr_21to30_04_q(21 to 30) = "0000000011" else '0'; +rf1_is_mtdp <= '1' when rf1_opcode_is_31_q(3) = '1' and rf1_instr_21to30_04_q(21 to 30) = "0001100011" else '0'; +rf1_is_mtdpx <= '1' when rf1_opcode_is_31_q(4) = '1' and rf1_instr_21to30_04_q(21 to 30) = "0001000011" else '0'; +rf1_is_mfspr <= '1' when rf1_opcode_is_31_q(4) = '1' and rf1_instr_21to30_04_q(21 to 30) = "0101010011" else '0'; +rf1_is_mtcrf <= '1' when rf1_opcode_is_31_q(4) = '1' and rf1_instr_21to30_04_q(21 to 30) = "0010010000" else '0'; +rf1_is_mtmsr <= '1' when rf1_opcode_is_31_q(4) = '1' and rf1_instr_21to30_04_q(21 to 30) = "0010010010" else '0'; +rf1_is_mtspr <= '1' when rf1_opcode_is_31_q(4) = '1' and rf1_instr_21to30_04_q(21 to 30) = "0111010011" else '0'; +rf1_is_neg <= '1' when rf1_opcode_is_31_q(4) = '1' and rf1_instr_21to30_05_q(22 to 30) = "001101000" else '0'; +rf1_is_rfci <= '1' when rf1_opcode_is_19 and rf1_instr_21to30_05_q(21 to 30) = "0000110011" else '0'; +rf1_is_rfi <= '1' when rf1_opcode_is_19 and rf1_instr_21to30_05_q(21 to 30) = "0000110010" else '0'; +rf1_is_rfmci <= '1' when rf1_opcode_is_19 and rf1_instr_21to30_05_q(21 to 30) = "0000100110" else '0'; +rf1_is_sc <= '1' when rf1_instr_q( 0 to 5) = "010001" else '0'; +rf1_is_std <= '1' when rf1_opcode_is_62 and rf1_instr_q(30 to 31) = "00" else '0'; +rf1_is_stdbrx <= '1' when rf1_opcode_is_31_q(4) = '1' and rf1_instr_21to30_05_q(21 to 30) = "1010010100" else '0'; +rf1_is_stdcxr <= '1' when rf1_opcode_is_31_q(4) = '1' and rf1_instr_21to30_05_q(21 to 30) = "0011010110" else '0'; +rf1_is_stdu <= '1' when rf1_opcode_is_62 and rf1_instr_q(30 to 31) = "01" else '0'; +rf1_is_sthbrx <= '1' when rf1_opcode_is_31_q(5) = '1' and rf1_instr_21to30_05_q(21 to 30) = "1110010110" else '0'; +rf1_is_stwcxr <= '1' when rf1_opcode_is_31_q(5) = '1' and rf1_instr_21to30_05_q(21 to 30) = "0010010110" else '0'; +rf1_is_stwbrx <= '1' when rf1_opcode_is_31_q(5) = '1' and rf1_instr_21to30_06_q(21 to 30) = "1010010110" else '0'; +rf1_is_subf <= '1' when rf1_opcode_is_31_q(5) = '1' and rf1_instr_21to30_06_q(22 to 30) = "000101000" else '0'; +rf1_is_subfc <= '1' when rf1_opcode_is_31_q(5) = '1' and rf1_instr_21to30_06_q(22 to 30) = "000001000" else '0'; +rf1_is_subfe <= '1' when rf1_opcode_is_31_q(5) = '1' and rf1_instr_21to30_06_q(22 to 30) = "010001000" else '0'; +rf1_is_subfic <= '1' when rf1_instr_q( 0 to 5) = "001000" else '0'; +rf1_is_subfme <= '1' when rf1_opcode_is_31_q(5) = '1' and rf1_instr_21to30_06_q(22 to 30) = "011101000" else '0'; +rf1_is_subfze <= '1' when rf1_opcode_is_31_q(5) = '1' and rf1_instr_21to30_06_q(22 to 30) = "011001000" else '0'; +rf1_is_td <= '1' when rf1_opcode_is_31_q(6) = '1' and rf1_instr_21to30_06_q(21 to 30) = "0001000100" else '0'; +rf1_is_tdi <= '1' when rf1_instr_q( 0 to 5) = "000010" else '0'; +rf1_is_tlbilx <= '1' when rf1_opcode_is_31_q(6) = '1' and rf1_instr_21to30_06_q(21 to 30) = "0000010010" else '0'; +rf1_is_tlbivax <= '1' when rf1_opcode_is_31_q(6) = '1' and rf1_instr_21to30_07_q(21 to 30) = "1100010010" else '0'; +rf1_is_tlbre <= '1' when rf1_opcode_is_31_q(6) = '1' and rf1_instr_21to30_07_q(21 to 30) = "1110110010" else '0'; +rf1_is_tlbsx <= '1' when rf1_opcode_is_31_q(6) = '1' and rf1_instr_21to30_07_q(21 to 30) = "1110010010" else '0'; +rf1_is_tlbsrx <= '1' when rf1_opcode_is_31_q(6) = '1' and rf1_instr_21to30_07_q(21 to 30) = "1101010010" else '0'; +rf1_is_tlbwe <= '1' when rf1_opcode_is_31_q(6) = '1' and rf1_instr_21to30_07_q(21 to 30) = "1111010010" else '0'; +rf1_is_tlbwec <= '0'; +rf1_is_tw <= '1' when rf1_opcode_is_31_q(6) = '1' and rf1_instr_21to30_07_q(21 to 30) = "0000000100" else '0'; +rf1_is_twi <= '1' when rf1_instr_q( 0 to 5) = "000011" else '0'; +rf1_is_wrtee <= '1' when rf1_opcode_is_31_q(7) = '1' and rf1_instr_21to30_07_q(21 to 30) = "0010000011" else '0'; +rf1_is_dcbstep <= '1' when rf1_opcode_is_31_q(7) = '1' and rf1_instr_21to30_07_q(21 to 30) = "0000111111" else '0'; +rf1_is_dcbtep <= '1' when rf1_opcode_is_31_q(7) = '1' and rf1_instr_21to30_08_q(21 to 30) = "0100111111" else '0'; +rf1_is_dcbfep <= '1' when rf1_opcode_is_31_q(7) = '1' and rf1_instr_21to30_08_q(21 to 30) = "0001111111" else '0'; +rf1_is_dcbtstep <= '1' when rf1_opcode_is_31_q(7) = '1' and rf1_instr_21to30_08_q(21 to 30) = "0011111111" else '0'; +rf1_is_icbiep <= '1' when rf1_opcode_is_31_q(7) = '1' and rf1_instr_21to30_08_q(21 to 30) = "1111011111" else '0'; +rf1_is_dcbzep <= '1' when rf1_opcode_is_31_q(7) = '1' and rf1_instr_21to30_08_q(21 to 30) = "1111111111" else '0'; +rf1_is_rfgi <= '1' when rf1_opcode_is_19 and rf1_instr_21to30_08_q(21 to 30) = "0001100110" else '0'; +rf1_is_ehpriv <= '1' when rf1_opcode_is_31_q(7) = '1' and rf1_instr_21to30_08_q(21 to 30) = "0100001110" else '0'; +rf1_is_msgclr <= '1' when rf1_opcode_is_31_q(8) = '1' and rf1_instr_21to30_08_q(21 to 30) = "0011101110" else '0'; +rf1_is_msgsnd <= '1' when rf1_opcode_is_31_q(8) = '1' and rf1_instr_21to30_09_q(21 to 30) = "0011001110" else '0'; +rf1_is_icswx <= '1' when rf1_opcode_is_31_q(8) = '1' and rf1_instr_21to30_09_q(21 to 30) = "0110010110" else '0'; +rf1_is_icswepx <= '1' when rf1_opcode_is_31_q(8) = '1' and rf1_instr_21to30_09_q(21 to 30) = "1110110110" else '0'; +rf1_is_wchkall <= '1' when rf1_opcode_is_31_q(8) = '1' and rf1_instr_21to30_09_q(21 to 30) = "1110000110" else '0'; +rf1_is_wclr <= '1' when rf1_opcode_is_31_q(8) = '1' and rf1_instr_21to30_09_q(21 to 30) = "1110100110" else '0'; +rf1_is_mfdcr <= '1' when rf1_opcode_is_31_q(8) = '1' and rf1_instr_21to30_09_q(21 to 30) = "0101000011" else '0'; +rf1_is_mfdcrux <= '1' when rf1_opcode_is_31_q(8) = '1' and rf1_instr_21to30_09_q(21 to 30) = "0100100011" else '0'; +rf1_is_mfdcrx <= '1' when rf1_opcode_is_31_q(9) = '1' and rf1_instr_21to30_09_q(21 to 30) = "0100000011" else '0'; +rf1_is_mtdcr <= '1' when rf1_opcode_is_31_q(9) = '1' and rf1_instr_21to30_10_q(21 to 30) = "0111000011" else '0'; +rf1_is_mtdcrux <= '1' when rf1_opcode_is_31_q(9) = '1' and rf1_instr_21to30_10_q(21 to 30) = "0110100011" else '0'; +rf1_is_mtdcrx <= '1' when rf1_opcode_is_31_q(9) = '1' and rf1_instr_21to30_10_q(21 to 30) = "0110000011" else '0'; +rf1_is_mulhd <= '1' when rf1_opcode_is_31 and rf1_instr_q(22 to 30) = "001001001" else '0'; +rf1_is_mulhdu <= '1' when rf1_opcode_is_31 and rf1_instr_q(22 to 30) = "000001001" else '0'; +rf1_is_mulhw <= '1' when rf1_opcode_is_31 and rf1_instr_q(22 to 30) = "001001011" else '0'; +rf1_is_mulhwu <= '1' when rf1_opcode_is_31 and rf1_instr_q(22 to 30) = "000001011" else '0'; +rf1_is_mulld <= '1' when rf1_opcode_is_31 and rf1_instr_q(22 to 30) = "011101001" else '0'; +rf1_is_mulli <= '1' when rf1_instr_q( 0 to 5) = "000111" else '0'; +rf1_is_mullw <= '1' when rf1_opcode_is_31 and rf1_instr_q(22 to 30) = "011101011" else '0'; +rf1_is_divd <= '1' when rf1_opcode_is_31 and rf1_instr_q(22 to 30) = "111101001" else '0'; +rf1_is_divdu <= '1' when rf1_opcode_is_31 and rf1_instr_q(22 to 30) = "111001001" else '0'; +rf1_is_divw <= '1' when rf1_opcode_is_31 and rf1_instr_q(22 to 30) = "111101011" else '0'; +rf1_is_divwu <= '1' when rf1_opcode_is_31 and rf1_instr_q(22 to 30) = "111001011" else '0'; +rf1_is_divwe <= '1' when rf1_opcode_is_31 and rf1_instr_q(22 to 30) = "110101011" else '0'; +rf1_is_divweu <= '1' when rf1_opcode_is_31 and rf1_instr_q(22 to 30) = "110001011" else '0'; +rf1_is_divde <= '1' when rf1_opcode_is_31 and rf1_instr_q(22 to 30) = "110101001" else '0'; +rf1_is_divdeu <= '1' when rf1_opcode_is_31 and rf1_instr_q(22 to 30) = "110001001" else '0'; +opcode_31_gen : for i in 0 to 9 generate +rf1_opcode_is_31_d(i) <= rf0_opcode_is_31; +end generate; +rf1_instr_21to30_00_d <= fxa_fxb_rf0_instr(21 to 30); +rf1_instr_21to30_01_d <= fxa_fxb_rf0_instr(21 to 30); +rf1_instr_21to30_02_d <= fxa_fxb_rf0_instr(21 to 30); +rf1_instr_21to30_03_d <= fxa_fxb_rf0_instr(21 to 30); +rf1_instr_21to30_04_d <= fxa_fxb_rf0_instr(21 to 30); +rf1_instr_21to30_05_d <= fxa_fxb_rf0_instr(21 to 30); +rf1_instr_21to30_06_d <= fxa_fxb_rf0_instr(21 to 30); +rf1_instr_21to30_07_d <= fxa_fxb_rf0_instr(21 to 30); +rf1_instr_21to30_08_d <= fxa_fxb_rf0_instr(21 to 30); +rf1_instr_21to30_09_d <= fxa_fxb_rf0_instr(21 to 30); +rf1_instr_21to30_10_d <= fxa_fxb_rf0_instr(21 to 30); +rf0_opcode_is_31 <= '1' when fxa_fxb_rf0_instr(0 to 5) = "011111" else '0'; +rf1_opcode_is_31 <= rf1_instr_q(0 to 5) = "011111"; +rf1_opcode_is_0 <= rf1_instr_q(0 to 5) = "000000"; +rf1_opcode_is_19 <= rf1_instr_q(0 to 5) = "010011"; +rf1_opcode_is_62 <= rf1_instr_q(0 to 5) = "111110"; +rf1_opcode_is_58 <= rf1_instr_q(0 to 5) = "111010"; +MQQ1:TBL_MASTER_DEC_PT(1) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0100111000010000")); +MQQ2:TBL_MASTER_DEC_PT(2) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0100110000000000")); +MQQ3:TBL_MASTER_DEC_PT(3) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0100110000100110")); +MQQ4:TBL_MASTER_DEC_PT(4) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0100110000110011")); +MQQ5:TBL_MASTER_DEC_PT(5) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("010011011000001")); +MQQ6:TBL_MASTER_DEC_PT(6) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111110111111100")); +MQQ7:TBL_MASTER_DEC_PT(7) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("010011010100001")); +MQQ8:TBL_MASTER_DEC_PT(8) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("010011001100001")); +MQQ9:TBL_MASTER_DEC_PT(9) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("010011000100001")); +MQQ10:TBL_MASTER_DEC_PT(10) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("010011010000001")); +MQQ11:TBL_MASTER_DEC_PT(11) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("010011001000001")); +MQQ12:TBL_MASTER_DEC_PT(12) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111110101001110")); +MQQ13:TBL_MASTER_DEC_PT(13) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("010011000100110")); +MQQ14:TBL_MASTER_DEC_PT(14) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111110000100000")); +MQQ15:TBL_MASTER_DEC_PT(15) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111110100001110")); +MQQ16:TBL_MASTER_DEC_PT(16) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) ) , STD_ULOGIC_VECTOR'("010011000011001")); +MQQ17:TBL_MASTER_DEC_PT(17) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111110010010000")); +MQQ18:TBL_MASTER_DEC_PT(18) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111111000110110")); +MQQ19:TBL_MASTER_DEC_PT(19) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111110001010011")); +MQQ20:TBL_MASTER_DEC_PT(20) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111111000110")); +MQQ21:TBL_MASTER_DEC_PT(21) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(21) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) + ) , STD_ULOGIC_VECTOR'("01111110011101")); +MQQ22:TBL_MASTER_DEC_PT(22) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111111100110011")); +MQQ23:TBL_MASTER_DEC_PT(23) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111001101000")); +MQQ24:TBL_MASTER_DEC_PT(24) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(21) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111111011010")); +MQQ25:TBL_MASTER_DEC_PT(25) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111111111111")); +MQQ26:TBL_MASTER_DEC_PT(26) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111111011010")); +MQQ27:TBL_MASTER_DEC_PT(27) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111110111010110")); +MQQ28:TBL_MASTER_DEC_PT(28) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111010110011")); +MQQ29:TBL_MASTER_DEC_PT(29) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111111010010")); +MQQ30:TBL_MASTER_DEC_PT(30) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111000011000")); +MQQ31:TBL_MASTER_DEC_PT(31) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111110010100011")); +MQQ32:TBL_MASTER_DEC_PT(32) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("0111011011100")); +MQQ33:TBL_MASTER_DEC_PT(33) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111101100100")); +MQQ34:TBL_MASTER_DEC_PT(34) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111101010101")); +MQQ35:TBL_MASTER_DEC_PT(35) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111110010000011")); +MQQ36:TBL_MASTER_DEC_PT(36) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("0111000111100")); +MQQ37:TBL_MASTER_DEC_PT(37) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111000011011")); +MQQ38:TBL_MASTER_DEC_PT(38) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(02) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(21) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111111010110")); +MQQ39:TBL_MASTER_DEC_PT(39) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111001001000")); +MQQ40:TBL_MASTER_DEC_PT(40) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111101110100")); +MQQ41:TBL_MASTER_DEC_PT(41) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111001101110")); +MQQ42:TBL_MASTER_DEC_PT(42) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(02) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(21) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111011100110")); +MQQ43:TBL_MASTER_DEC_PT(43) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111011010011")); +MQQ44:TBL_MASTER_DEC_PT(44) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111001010011")); +MQQ45:TBL_MASTER_DEC_PT(45) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111000000100")); +MQQ46:TBL_MASTER_DEC_PT(46) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111000110011")); +MQQ47:TBL_MASTER_DEC_PT(47) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111110010010")); +MQQ48:TBL_MASTER_DEC_PT(48) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(21) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("0111111001100")); +MQQ49:TBL_MASTER_DEC_PT(49) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(02) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(21) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111110010010")); +MQQ50:TBL_MASTER_DEC_PT(50) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(21) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("0111111011010")); +MQQ51:TBL_MASTER_DEC_PT(51) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111111010010")); +MQQ52:TBL_MASTER_DEC_PT(52) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111000000000")); +MQQ53:TBL_MASTER_DEC_PT(53) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111100001000")); +MQQ54:TBL_MASTER_DEC_PT(54) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(02) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(21) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111000011011")); +MQQ55:TBL_MASTER_DEC_PT(55) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111100000011")); +MQQ56:TBL_MASTER_DEC_PT(56) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(02) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(21) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111001000110")); +MQQ57:TBL_MASTER_DEC_PT(57) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("011101011100")); +MQQ58:TBL_MASTER_DEC_PT(58) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("011100011100")); +MQQ59:TBL_MASTER_DEC_PT(59) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111100111111")); +MQQ60:TBL_MASTER_DEC_PT(60) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(02) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(21) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("0111111110110")); +MQQ61:TBL_MASTER_DEC_PT(61) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(02) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(21) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("0111101011011")); +MQQ62:TBL_MASTER_DEC_PT(62) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(02) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("0111100001010")); +MQQ63:TBL_MASTER_DEC_PT(63) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(02) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(21) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) ) , STD_ULOGIC_VECTOR'("0111110001010")); +MQQ64:TBL_MASTER_DEC_PT(64) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111000010010")); +MQQ65:TBL_MASTER_DEC_PT(65) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111100001111")); +MQQ66:TBL_MASTER_DEC_PT(66) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111100011111")); +MQQ67:TBL_MASTER_DEC_PT(67) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111100011111")); +MQQ68:TBL_MASTER_DEC_PT(68) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("0111110100100")); +MQQ69:TBL_MASTER_DEC_PT(69) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(02) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(21) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) ) , STD_ULOGIC_VECTOR'("0111100111011")); +MQQ70:TBL_MASTER_DEC_PT(70) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(02) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(21) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("0111100101010")); +MQQ71:TBL_MASTER_DEC_PT(71) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(02) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(21) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("0111101000110")); +MQQ72:TBL_MASTER_DEC_PT(72) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(02) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(21) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) ) , STD_ULOGIC_VECTOR'("0111100000101")); +MQQ73:TBL_MASTER_DEC_PT(73) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(02) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(21) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) ) , STD_ULOGIC_VECTOR'("0111100001011")); +MQQ74:TBL_MASTER_DEC_PT(74) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(02) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(21) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("011110001111")); +MQQ75:TBL_MASTER_DEC_PT(75) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(02) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(21) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("011110001011")); +MQQ76:TBL_MASTER_DEC_PT(76) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(02) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("011110010110")); +MQQ77:TBL_MASTER_DEC_PT(77) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(02) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(21) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("011110010111")); +MQQ78:TBL_MASTER_DEC_PT(78) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011101111")); +MQQ79:TBL_MASTER_DEC_PT(79) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) + ) , STD_ULOGIC_VECTOR'("010000")); +MQQ80:TBL_MASTER_DEC_PT(80) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(02) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("110100")); +MQQ81:TBL_MASTER_DEC_PT(81) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) + ) , STD_ULOGIC_VECTOR'("01111000")); +MQQ82:TBL_MASTER_DEC_PT(82) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) + ) , STD_ULOGIC_VECTOR'("001000")); +MQQ83:TBL_MASTER_DEC_PT(83) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) + ) , STD_ULOGIC_VECTOR'("001010")); +MQQ84:TBL_MASTER_DEC_PT(84) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(02) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("11100")); +MQQ85:TBL_MASTER_DEC_PT(85) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(27) ) , STD_ULOGIC_VECTOR'("0111100")); +MQQ86:TBL_MASTER_DEC_PT(86) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) ) , STD_ULOGIC_VECTOR'("01010")); +MQQ87:TBL_MASTER_DEC_PT(87) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) ) , STD_ULOGIC_VECTOR'("00001")); +MQQ88:TBL_MASTER_DEC_PT(88) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) + ) , STD_ULOGIC_VECTOR'("001111")); +MQQ89:TBL_MASTER_DEC_PT(89) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) ) , STD_ULOGIC_VECTOR'("01101")); +MQQ90:TBL_MASTER_DEC_PT(90) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(05) ) , STD_ULOGIC_VECTOR'("01011")); +MQQ91:TBL_MASTER_DEC_PT(91) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(05) ) , STD_ULOGIC_VECTOR'("01101")); +MQQ92:TBL_MASTER_DEC_PT(92) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) ) , STD_ULOGIC_VECTOR'("00101")); +MQQ93:TBL_MASTER_DEC_PT(93) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(04) + ) , STD_ULOGIC_VECTOR'("0110")); +MQQ94:TBL_MASTER_DEC_PT(94) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) + ) , STD_ULOGIC_VECTOR'("10")); +MQQ95:TBL_MASTER_DEC_PT(95) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) + ) , STD_ULOGIC_VECTOR'("0110")); +MQQ96:TBL_MASTER_DEC_PT(96) <= + Eq(( RF1_INSTR_Q(01) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) ) , STD_ULOGIC_VECTOR'("011")); +MQQ97:TBL_MASTER_DEC_PT(97) <= + Eq(( RF1_INSTR_Q(01) & RF1_INSTR_Q(02) & + RF1_INSTR_Q(03) ) , STD_ULOGIC_VECTOR'("011")); +MQQ98:DEC_BYP_RF1_IS_MCRF <= + (TBL_MASTER_DEC_PT(2)); +MQQ99:DEC_BYP_RF1_IS_MTCRF <= + (TBL_MASTER_DEC_PT(17)); +MQQ100:RF1_ADD_EXT <= + (TBL_MASTER_DEC_PT(40) OR TBL_MASTER_DEC_PT(68) + ); +MQQ101:RF1_ALU_CMP <= + (TBL_MASTER_DEC_PT(52) OR TBL_MASTER_DEC_PT(92) + ); +MQQ102:RF1_CMP <= + (TBL_MASTER_DEC_PT(45) OR TBL_MASTER_DEC_PT(52) + OR TBL_MASTER_DEC_PT(87) OR TBL_MASTER_DEC_PT(92) + ); +MQQ103:RF1_CMP_UEXT <= + (TBL_MASTER_DEC_PT(14) OR TBL_MASTER_DEC_PT(83) + ); +MQQ104:RF1_CR_SO_UPDATE(00) <= + (TBL_MASTER_DEC_PT(5) OR TBL_MASTER_DEC_PT(7) + OR TBL_MASTER_DEC_PT(8) OR TBL_MASTER_DEC_PT(9) + OR TBL_MASTER_DEC_PT(10) OR TBL_MASTER_DEC_PT(11) + OR TBL_MASTER_DEC_PT(17)); +MQQ105:RF1_CR_SO_UPDATE(01) <= + (TBL_MASTER_DEC_PT(52) OR TBL_MASTER_DEC_PT(92) + ); +MQQ106:RF1_CR_WE <= + (TBL_MASTER_DEC_PT(2) OR TBL_MASTER_DEC_PT(5) + OR TBL_MASTER_DEC_PT(7) OR TBL_MASTER_DEC_PT(8) + OR TBL_MASTER_DEC_PT(9) OR TBL_MASTER_DEC_PT(10) + OR TBL_MASTER_DEC_PT(11) OR TBL_MASTER_DEC_PT(52) + OR TBL_MASTER_DEC_PT(92)); +MQQ107:RF1_IMM_SIGNEXT_TBL <= + (TBL_MASTER_DEC_PT(79) OR TBL_MASTER_DEC_PT(80) + OR TBL_MASTER_DEC_PT(82) OR TBL_MASTER_DEC_PT(84) + OR TBL_MASTER_DEC_PT(87) OR TBL_MASTER_DEC_PT(94) + OR TBL_MASTER_DEC_PT(96) OR TBL_MASTER_DEC_PT(97) + ); +MQQ108:RF1_IMM_SIZE_TBL <= + (TBL_MASTER_DEC_PT(31) OR TBL_MASTER_DEC_PT(34) + OR TBL_MASTER_DEC_PT(79) OR TBL_MASTER_DEC_PT(80) + OR TBL_MASTER_DEC_PT(82) OR TBL_MASTER_DEC_PT(83) + OR TBL_MASTER_DEC_PT(84) OR TBL_MASTER_DEC_PT(87) + OR TBL_MASTER_DEC_PT(93) OR TBL_MASTER_DEC_PT(94) + OR TBL_MASTER_DEC_PT(95) OR TBL_MASTER_DEC_PT(96) + OR TBL_MASTER_DEC_PT(97)); +MQQ109:RF1_INSTR_HYPV_TBL <= + (TBL_MASTER_DEC_PT(3) OR TBL_MASTER_DEC_PT(4) + OR TBL_MASTER_DEC_PT(18) OR TBL_MASTER_DEC_PT(22) + OR TBL_MASTER_DEC_PT(29) OR TBL_MASTER_DEC_PT(41) + OR TBL_MASTER_DEC_PT(44) OR TBL_MASTER_DEC_PT(46) + OR TBL_MASTER_DEC_PT(47)); +MQQ110:RF1_INSTR_PRIV_TBL <= + (TBL_MASTER_DEC_PT(13) OR TBL_MASTER_DEC_PT(15) + OR TBL_MASTER_DEC_PT(16) OR TBL_MASTER_DEC_PT(18) + OR TBL_MASTER_DEC_PT(19) OR TBL_MASTER_DEC_PT(20) + OR TBL_MASTER_DEC_PT(22) OR TBL_MASTER_DEC_PT(25) + OR TBL_MASTER_DEC_PT(26) OR TBL_MASTER_DEC_PT(27) + OR TBL_MASTER_DEC_PT(31) OR TBL_MASTER_DEC_PT(35) + OR TBL_MASTER_DEC_PT(41) OR TBL_MASTER_DEC_PT(44) + OR TBL_MASTER_DEC_PT(46) OR TBL_MASTER_DEC_PT(51) + OR TBL_MASTER_DEC_PT(55) OR TBL_MASTER_DEC_PT(59) + OR TBL_MASTER_DEC_PT(64) OR TBL_MASTER_DEC_PT(65) + OR TBL_MASTER_DEC_PT(66) OR TBL_MASTER_DEC_PT(67) + ); +MQQ111:RF1_IS_TRAP <= + (TBL_MASTER_DEC_PT(45) OR TBL_MASTER_DEC_PT(87) + ); +MQQ112:RF1_ONES_IMM <= + (TBL_MASTER_DEC_PT(40)); +MQQ113:RF1_SEL(00) <= + (TBL_MASTER_DEC_PT(22) OR TBL_MASTER_DEC_PT(23) + OR TBL_MASTER_DEC_PT(25) OR TBL_MASTER_DEC_PT(27) + OR TBL_MASTER_DEC_PT(31) OR TBL_MASTER_DEC_PT(34) + OR TBL_MASTER_DEC_PT(35) OR TBL_MASTER_DEC_PT(38) + OR TBL_MASTER_DEC_PT(40) OR TBL_MASTER_DEC_PT(41) + OR TBL_MASTER_DEC_PT(42) OR TBL_MASTER_DEC_PT(43) + OR TBL_MASTER_DEC_PT(45) OR TBL_MASTER_DEC_PT(47) + OR TBL_MASTER_DEC_PT(49) OR TBL_MASTER_DEC_PT(52) + OR TBL_MASTER_DEC_PT(53) OR TBL_MASTER_DEC_PT(54) + OR TBL_MASTER_DEC_PT(56) OR TBL_MASTER_DEC_PT(59) + OR TBL_MASTER_DEC_PT(60) OR TBL_MASTER_DEC_PT(61) + OR TBL_MASTER_DEC_PT(62) OR TBL_MASTER_DEC_PT(63) + OR TBL_MASTER_DEC_PT(64) OR TBL_MASTER_DEC_PT(65) + OR TBL_MASTER_DEC_PT(66) OR TBL_MASTER_DEC_PT(67) + OR TBL_MASTER_DEC_PT(68) OR TBL_MASTER_DEC_PT(69) + OR TBL_MASTER_DEC_PT(70) OR TBL_MASTER_DEC_PT(71) + OR TBL_MASTER_DEC_PT(72) OR TBL_MASTER_DEC_PT(73) + OR TBL_MASTER_DEC_PT(74) OR TBL_MASTER_DEC_PT(75) + OR TBL_MASTER_DEC_PT(76) OR TBL_MASTER_DEC_PT(77) + OR TBL_MASTER_DEC_PT(80) OR TBL_MASTER_DEC_PT(82) + OR TBL_MASTER_DEC_PT(84) OR TBL_MASTER_DEC_PT(87) + OR TBL_MASTER_DEC_PT(92) OR TBL_MASTER_DEC_PT(94) + OR TBL_MASTER_DEC_PT(97)); +MQQ114:RF1_SEL(01) <= + (TBL_MASTER_DEC_PT(21) OR TBL_MASTER_DEC_PT(24) + OR TBL_MASTER_DEC_PT(30) OR TBL_MASTER_DEC_PT(37) + OR TBL_MASTER_DEC_PT(48) OR TBL_MASTER_DEC_PT(50) + OR TBL_MASTER_DEC_PT(81) OR TBL_MASTER_DEC_PT(85) + OR TBL_MASTER_DEC_PT(86) OR TBL_MASTER_DEC_PT(90) + ); +MQQ115:RF1_SEL(02) <= + (TBL_MASTER_DEC_PT(32) OR TBL_MASTER_DEC_PT(36) + OR TBL_MASTER_DEC_PT(57) OR TBL_MASTER_DEC_PT(58) + OR TBL_MASTER_DEC_PT(78) OR TBL_MASTER_DEC_PT(93) + OR TBL_MASTER_DEC_PT(95)); +MQQ116:RF1_SEL(03) <= + (TBL_MASTER_DEC_PT(6)); +MQQ117:RF1_SHIFT_IMM <= + (TBL_MASTER_DEC_PT(88) OR TBL_MASTER_DEC_PT(89) + OR TBL_MASTER_DEC_PT(91)); +MQQ118:RF1_SPR_SEL <= + (TBL_MASTER_DEC_PT(1) OR TBL_MASTER_DEC_PT(12) + OR TBL_MASTER_DEC_PT(13) OR TBL_MASTER_DEC_PT(16) + OR TBL_MASTER_DEC_PT(19) OR TBL_MASTER_DEC_PT(28) + ); +MQQ119:RF1_SUB <= + (TBL_MASTER_DEC_PT(23) OR TBL_MASTER_DEC_PT(45) + OR TBL_MASTER_DEC_PT(52) OR TBL_MASTER_DEC_PT(53) + OR TBL_MASTER_DEC_PT(82) OR TBL_MASTER_DEC_PT(87) + OR TBL_MASTER_DEC_PT(92)); +MQQ120:RF1_ZERO_IMM <= + (TBL_MASTER_DEC_PT(23) OR TBL_MASTER_DEC_PT(33) + OR TBL_MASTER_DEC_PT(34) OR TBL_MASTER_DEC_PT(35) + OR TBL_MASTER_DEC_PT(39) OR TBL_MASTER_DEC_PT(43) + ); + +MQQ121:TBL_LD_ST_DEC_PT(1) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(09) & RF1_INSTR_Q(21) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("01111111110100110")); +MQQ122:TBL_LD_ST_DEC_PT(2) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111110011010100")); +MQQ123:TBL_LD_ST_DEC_PT(3) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111111111111111")); +MQQ124:TBL_LD_ST_DEC_PT(4) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111111111011111")); +MQQ125:TBL_LD_ST_DEC_PT(5) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111110011110111")); +MQQ126:TBL_LD_ST_DEC_PT(6) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111111001010101")); +MQQ127:TBL_LD_ST_DEC_PT(7) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111110110000110")); +MQQ128:TBL_LD_ST_DEC_PT(8) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111111110110110")); +MQQ129:TBL_LD_ST_DEC_PT(9) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_XER_SI_ZERO_B + ) , STD_ULOGIC_VECTOR'("0111111010010101")); +MQQ130:TBL_LD_ST_DEC_PT(10) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111111111110110")); +MQQ131:TBL_LD_ST_DEC_PT(11) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111110011010110")); +MQQ132:TBL_LD_ST_DEC_PT(12) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111111111010110")); +MQQ133:TBL_LD_ST_DEC_PT(13) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111111011010101")); +MQQ134:TBL_LD_ST_DEC_PT(14) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111110000110110")); +MQQ135:TBL_LD_ST_DEC_PT(15) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111111000010100")); +MQQ136:TBL_LD_ST_DEC_PT(16) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111110001010110")); +MQQ137:TBL_LD_ST_DEC_PT(17) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111010001111")); +MQQ138:TBL_LD_ST_DEC_PT(18) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111011100110")); +MQQ139:TBL_LD_ST_DEC_PT(19) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111111100010110")); +MQQ140:TBL_LD_ST_DEC_PT(20) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111110101010101")); +MQQ141:TBL_LD_ST_DEC_PT(21) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111000111111")); +MQQ142:TBL_LD_ST_DEC_PT(22) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111001101111")); +MQQ143:TBL_LD_ST_DEC_PT(23) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_XER_SI_ZERO_B ) , STD_ULOGIC_VECTOR'("011111000010101")); +MQQ144:TBL_LD_ST_DEC_PT(24) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111001100110")); +MQQ145:TBL_LD_ST_DEC_PT(25) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111111010010100")); +MQQ146:TBL_LD_ST_DEC_PT(26) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111110000010100")); +MQQ147:TBL_LD_ST_DEC_PT(27) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111111000010110")); +MQQ148:TBL_LD_ST_DEC_PT(28) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111111110010110")); +MQQ149:TBL_LD_ST_DEC_PT(29) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111110101010111")); +MQQ150:TBL_LD_ST_DEC_PT(30) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111010111011")); +MQQ151:TBL_LD_ST_DEC_PT(31) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111110010110101")); +MQQ152:TBL_LD_ST_DEC_PT(32) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111110110110111")); +MQQ153:TBL_LD_ST_DEC_PT(33) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111000011011")); +MQQ154:TBL_LD_ST_DEC_PT(34) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111110010110111")); +MQQ155:TBL_LD_ST_DEC_PT(35) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111000001101")); +MQQ156:TBL_LD_ST_DEC_PT(36) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111001000110")); +MQQ157:TBL_LD_ST_DEC_PT(37) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111010010110")); +MQQ158:TBL_LD_ST_DEC_PT(38) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111001010100")); +MQQ159:TBL_LD_ST_DEC_PT(39) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111000101111")); +MQQ160:TBL_LD_ST_DEC_PT(40) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111011010110")); +MQQ161:TBL_LD_ST_DEC_PT(41) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111001001101")); +MQQ162:TBL_LD_ST_DEC_PT(42) <= + Eq(( RF1_AXU_LD_OR_ST_Q & RF1_AXU_MFTGPR_Q & + RF1_AXU_MFFGPR_Q & RF1_AXU_MOVEDP_Q & + RF1_AXU_STORE_Q & RF1_AXU_LDST_UPDATE_Q + ) , STD_ULOGIC_VECTOR'("100001")); +MQQ163:TBL_LD_ST_DEC_PT(43) <= + Eq(( RF1_AXU_LD_OR_ST_Q & RF1_AXU_MFTGPR_Q & + RF1_AXU_MFFGPR_Q & RF1_AXU_MOVEDP_Q & + RF1_AXU_STORE_Q & RF1_AXU_LDST_UPDATE_Q + ) , STD_ULOGIC_VECTOR'("100011")); +MQQ164:TBL_LD_ST_DEC_PT(44) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111000001111")); +MQQ165:TBL_LD_ST_DEC_PT(45) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111011001111")); +MQQ166:TBL_LD_ST_DEC_PT(46) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111101001111")); +MQQ167:TBL_LD_ST_DEC_PT(47) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111100110111")); +MQQ168:TBL_LD_ST_DEC_PT(48) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111001001111")); +MQQ169:TBL_LD_ST_DEC_PT(49) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111010010110")); +MQQ170:TBL_LD_ST_DEC_PT(50) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111100111111")); +MQQ171:TBL_LD_ST_DEC_PT(51) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) + ) , STD_ULOGIC_VECTOR'("01111100001011")); +MQQ172:TBL_LD_ST_DEC_PT(52) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) + ) , STD_ULOGIC_VECTOR'("01111100111011")); +MQQ173:TBL_LD_ST_DEC_PT(53) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(30) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("11111001")); +MQQ174:TBL_LD_ST_DEC_PT(54) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(30) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("11101001")); +MQQ175:TBL_LD_ST_DEC_PT(55) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) + ) , STD_ULOGIC_VECTOR'("100000")); +MQQ176:TBL_LD_ST_DEC_PT(56) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(30) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("11101000")); +MQQ177:TBL_LD_ST_DEC_PT(57) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(30) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("11101010")); +MQQ178:TBL_LD_ST_DEC_PT(58) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) + ) , STD_ULOGIC_VECTOR'("101010")); +MQQ179:TBL_LD_ST_DEC_PT(59) <= + Eq(( RF1_AXU_LD_OR_ST_Q & RF1_AXU_MFTGPR_Q & + RF1_AXU_MFFGPR_Q & RF1_AXU_MOVEDP_Q & + RF1_AXU_STORE_Q ) , STD_ULOGIC_VECTOR'("10000")); +MQQ180:TBL_LD_ST_DEC_PT(60) <= + Eq(( RF1_AXU_LD_OR_ST_Q & RF1_AXU_MFTGPR_Q & + RF1_AXU_MFFGPR_Q & RF1_AXU_MOVEDP_Q & + RF1_AXU_STORE_Q ) , STD_ULOGIC_VECTOR'("10001")); +MQQ181:TBL_LD_ST_DEC_PT(61) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) + ) , STD_ULOGIC_VECTOR'("100010")); +MQQ182:TBL_LD_ST_DEC_PT(62) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(05) ) , STD_ULOGIC_VECTOR'("10011")); +MQQ183:TBL_LD_ST_DEC_PT(63) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) ) , STD_ULOGIC_VECTOR'("10101")); +MQQ184:TBL_LD_ST_DEC_PT(64) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(05) ) , STD_ULOGIC_VECTOR'("10100")); +MQQ185:TBL_LD_ST_DEC_PT(65) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) ) , STD_ULOGIC_VECTOR'("10010")); +MQQ186:TBL_LD_ST_DEC_PT(66) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("1111100")); +MQQ187:TBL_LD_ST_DEC_PT(67) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) ) , STD_ULOGIC_VECTOR'("10110")); +MQQ188:TBL_LD_ST_DEC_PT(68) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(05) + ) , STD_ULOGIC_VECTOR'("1001")); +MQQ189:TBL_LD_ST_DEC_PT(69) <= + Eq(( RF1_AXU_LD_OR_ST_Q & RF1_AXU_LDST_SIZE_Q(01) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ190:TBL_LD_ST_DEC_PT(70) <= + Eq(( RF1_AXU_LD_OR_ST_Q & RF1_AXU_LDST_SIZE_Q(00) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ191:TBL_LD_ST_DEC_PT(71) <= + Eq(( RF1_AXU_LD_OR_ST_Q & RF1_AXU_LDST_SIZE_Q(05) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ192:TBL_LD_ST_DEC_PT(72) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) ) , STD_ULOGIC_VECTOR'("10011")); +MQQ193:TBL_LD_ST_DEC_PT(73) <= + Eq(( RF1_AXU_LD_OR_ST_Q & RF1_AXU_LDST_SIZE_Q(04) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ194:TBL_LD_ST_DEC_PT(74) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) ) , STD_ULOGIC_VECTOR'("10110")); +MQQ195:TBL_LD_ST_DEC_PT(75) <= + Eq(( RF1_AXU_LD_OR_ST_Q & RF1_AXU_LDST_SIZE_Q(02) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ196:TBL_LD_ST_DEC_PT(76) <= + Eq(( RF1_AXU_LD_OR_ST_Q & RF1_AXU_LDST_SIZE_Q(03) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ197:TBL_LD_ST_DEC_PT(77) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(05) + ) , STD_ULOGIC_VECTOR'("1011")); +MQQ198:RF1_DERAT_IS_LOAD <= + (TBL_LD_ST_DEC_PT(1) OR TBL_LD_ST_DEC_PT(4) + OR TBL_LD_ST_DEC_PT(6) OR TBL_LD_ST_DEC_PT(7) + OR TBL_LD_ST_DEC_PT(12) OR TBL_LD_ST_DEC_PT(14) + OR TBL_LD_ST_DEC_PT(15) OR TBL_LD_ST_DEC_PT(16) + OR TBL_LD_ST_DEC_PT(18) OR TBL_LD_ST_DEC_PT(19) + OR TBL_LD_ST_DEC_PT(20) OR TBL_LD_ST_DEC_PT(21) + OR TBL_LD_ST_DEC_PT(23) OR TBL_LD_ST_DEC_PT(24) + OR TBL_LD_ST_DEC_PT(26) OR TBL_LD_ST_DEC_PT(27) + OR TBL_LD_ST_DEC_PT(29) OR TBL_LD_ST_DEC_PT(30) + OR TBL_LD_ST_DEC_PT(33) OR TBL_LD_ST_DEC_PT(35) + OR TBL_LD_ST_DEC_PT(38) OR TBL_LD_ST_DEC_PT(39) + OR TBL_LD_ST_DEC_PT(44) OR TBL_LD_ST_DEC_PT(46) + OR TBL_LD_ST_DEC_PT(47) OR TBL_LD_ST_DEC_PT(51) + OR TBL_LD_ST_DEC_PT(54) OR TBL_LD_ST_DEC_PT(55) + OR TBL_LD_ST_DEC_PT(56) OR TBL_LD_ST_DEC_PT(57) + OR TBL_LD_ST_DEC_PT(59) OR TBL_LD_ST_DEC_PT(61) + OR TBL_LD_ST_DEC_PT(64) OR TBL_LD_ST_DEC_PT(67) + OR TBL_LD_ST_DEC_PT(68)); +MQQ199:RF1_DERAT_IS_STORE <= + (TBL_LD_ST_DEC_PT(3) OR TBL_LD_ST_DEC_PT(8) + OR TBL_LD_ST_DEC_PT(9) OR TBL_LD_ST_DEC_PT(10) + OR TBL_LD_ST_DEC_PT(13) OR TBL_LD_ST_DEC_PT(25) + OR TBL_LD_ST_DEC_PT(28) OR TBL_LD_ST_DEC_PT(31) + OR TBL_LD_ST_DEC_PT(32) OR TBL_LD_ST_DEC_PT(34) + OR TBL_LD_ST_DEC_PT(36) OR TBL_LD_ST_DEC_PT(37) + OR TBL_LD_ST_DEC_PT(40) OR TBL_LD_ST_DEC_PT(41) + OR TBL_LD_ST_DEC_PT(45) OR TBL_LD_ST_DEC_PT(48) + OR TBL_LD_ST_DEC_PT(49) OR TBL_LD_ST_DEC_PT(50) + OR TBL_LD_ST_DEC_PT(52) OR TBL_LD_ST_DEC_PT(60) + OR TBL_LD_ST_DEC_PT(65) OR TBL_LD_ST_DEC_PT(66) + OR TBL_LD_ST_DEC_PT(72) OR TBL_LD_ST_DEC_PT(74) + OR TBL_LD_ST_DEC_PT(77)); +MQQ200:RF1_IS_ANY_LOAD_AXU <= + (TBL_LD_ST_DEC_PT(15) OR TBL_LD_ST_DEC_PT(17) + OR TBL_LD_ST_DEC_PT(19) OR TBL_LD_ST_DEC_PT(20) + OR TBL_LD_ST_DEC_PT(26) OR TBL_LD_ST_DEC_PT(27) + OR TBL_LD_ST_DEC_PT(29) OR TBL_LD_ST_DEC_PT(35) + OR TBL_LD_ST_DEC_PT(38) OR TBL_LD_ST_DEC_PT(39) + OR TBL_LD_ST_DEC_PT(44) OR TBL_LD_ST_DEC_PT(55) + OR TBL_LD_ST_DEC_PT(56) OR TBL_LD_ST_DEC_PT(57) + OR TBL_LD_ST_DEC_PT(59) OR TBL_LD_ST_DEC_PT(61) + OR TBL_LD_ST_DEC_PT(64)); +MQQ201:RF1_IS_ANY_LOAD_DAC <= + (TBL_LD_ST_DEC_PT(1) OR TBL_LD_ST_DEC_PT(4) + OR TBL_LD_ST_DEC_PT(6) OR TBL_LD_ST_DEC_PT(7) + OR TBL_LD_ST_DEC_PT(12) OR TBL_LD_ST_DEC_PT(15) + OR TBL_LD_ST_DEC_PT(18) OR TBL_LD_ST_DEC_PT(19) + OR TBL_LD_ST_DEC_PT(20) OR TBL_LD_ST_DEC_PT(23) + OR TBL_LD_ST_DEC_PT(24) OR TBL_LD_ST_DEC_PT(26) + OR TBL_LD_ST_DEC_PT(27) OR TBL_LD_ST_DEC_PT(29) + OR TBL_LD_ST_DEC_PT(30) OR TBL_LD_ST_DEC_PT(33) + OR TBL_LD_ST_DEC_PT(35) OR TBL_LD_ST_DEC_PT(38) + OR TBL_LD_ST_DEC_PT(39) OR TBL_LD_ST_DEC_PT(44) + OR TBL_LD_ST_DEC_PT(46) OR TBL_LD_ST_DEC_PT(47) + OR TBL_LD_ST_DEC_PT(51) OR TBL_LD_ST_DEC_PT(54) + OR TBL_LD_ST_DEC_PT(55) OR TBL_LD_ST_DEC_PT(56) + OR TBL_LD_ST_DEC_PT(57) OR TBL_LD_ST_DEC_PT(59) + OR TBL_LD_ST_DEC_PT(61) OR TBL_LD_ST_DEC_PT(64) + OR TBL_LD_ST_DEC_PT(67) OR TBL_LD_ST_DEC_PT(68) + ); +MQQ202:RF1_IS_ANY_STORE <= + (TBL_LD_ST_DEC_PT(3) OR TBL_LD_ST_DEC_PT(8) + OR TBL_LD_ST_DEC_PT(9) OR TBL_LD_ST_DEC_PT(10) + OR TBL_LD_ST_DEC_PT(13) OR TBL_LD_ST_DEC_PT(25) + OR TBL_LD_ST_DEC_PT(28) OR TBL_LD_ST_DEC_PT(31) + OR TBL_LD_ST_DEC_PT(32) OR TBL_LD_ST_DEC_PT(34) + OR TBL_LD_ST_DEC_PT(36) OR TBL_LD_ST_DEC_PT(37) + OR TBL_LD_ST_DEC_PT(40) OR TBL_LD_ST_DEC_PT(41) + OR TBL_LD_ST_DEC_PT(45) OR TBL_LD_ST_DEC_PT(48) + OR TBL_LD_ST_DEC_PT(49) OR TBL_LD_ST_DEC_PT(50) + OR TBL_LD_ST_DEC_PT(52) OR TBL_LD_ST_DEC_PT(60) + OR TBL_LD_ST_DEC_PT(65) OR TBL_LD_ST_DEC_PT(66) + OR TBL_LD_ST_DEC_PT(72) OR TBL_LD_ST_DEC_PT(74) + OR TBL_LD_ST_DEC_PT(77)); +MQQ203:RF1_IS_ANY_STORE_AXU <= + (TBL_LD_ST_DEC_PT(5) OR TBL_LD_ST_DEC_PT(11) + OR TBL_LD_ST_DEC_PT(22) OR TBL_LD_ST_DEC_PT(25) + OR TBL_LD_ST_DEC_PT(28) OR TBL_LD_ST_DEC_PT(31) + OR TBL_LD_ST_DEC_PT(32) OR TBL_LD_ST_DEC_PT(34) + OR TBL_LD_ST_DEC_PT(41) OR TBL_LD_ST_DEC_PT(45) + OR TBL_LD_ST_DEC_PT(48) OR TBL_LD_ST_DEC_PT(49) + OR TBL_LD_ST_DEC_PT(60) OR TBL_LD_ST_DEC_PT(65) + OR TBL_LD_ST_DEC_PT(66) OR TBL_LD_ST_DEC_PT(72) + OR TBL_LD_ST_DEC_PT(74)); +MQQ204:RF1_IS_ANY_STORE_DAC <= + (TBL_LD_ST_DEC_PT(3) OR TBL_LD_ST_DEC_PT(9) + OR TBL_LD_ST_DEC_PT(10) OR TBL_LD_ST_DEC_PT(13) + OR TBL_LD_ST_DEC_PT(14) OR TBL_LD_ST_DEC_PT(16) + OR TBL_LD_ST_DEC_PT(21) OR TBL_LD_ST_DEC_PT(25) + OR TBL_LD_ST_DEC_PT(28) OR TBL_LD_ST_DEC_PT(31) + OR TBL_LD_ST_DEC_PT(32) OR TBL_LD_ST_DEC_PT(34) + OR TBL_LD_ST_DEC_PT(36) OR TBL_LD_ST_DEC_PT(40) + OR TBL_LD_ST_DEC_PT(41) OR TBL_LD_ST_DEC_PT(45) + OR TBL_LD_ST_DEC_PT(48) OR TBL_LD_ST_DEC_PT(49) + OR TBL_LD_ST_DEC_PT(50) OR TBL_LD_ST_DEC_PT(52) + OR TBL_LD_ST_DEC_PT(60) OR TBL_LD_ST_DEC_PT(65) + OR TBL_LD_ST_DEC_PT(66) OR TBL_LD_ST_DEC_PT(72) + OR TBL_LD_ST_DEC_PT(74) OR TBL_LD_ST_DEC_PT(77) + ); +MQQ205:RF1_IS_LD_W_UPDATE <= + (TBL_LD_ST_DEC_PT(30) OR TBL_LD_ST_DEC_PT(33) + OR TBL_LD_ST_DEC_PT(42) OR TBL_LD_ST_DEC_PT(47) + OR TBL_LD_ST_DEC_PT(54) OR TBL_LD_ST_DEC_PT(68) + ); +MQQ206:RF1_IS_ST_W_UPDATE <= + (TBL_LD_ST_DEC_PT(5) OR TBL_LD_ST_DEC_PT(31) + OR TBL_LD_ST_DEC_PT(32) OR TBL_LD_ST_DEC_PT(34) + OR TBL_LD_ST_DEC_PT(43) OR TBL_LD_ST_DEC_PT(53) + OR TBL_LD_ST_DEC_PT(62) OR TBL_LD_ST_DEC_PT(63) + ); +MQQ207:XU_LSU_RF1_ALGEBRAIC <= + (TBL_LD_ST_DEC_PT(20) OR TBL_LD_ST_DEC_PT(29) + OR TBL_LD_ST_DEC_PT(57) OR TBL_LD_ST_DEC_PT(58) + ); +MQQ208:XU_LSU_RF1_LDAWX_INSTR <= + (TBL_LD_ST_DEC_PT(2)); +MQQ209:XU_LSU_RF1_OPTYPE1 <= + (TBL_LD_ST_DEC_PT(5) OR TBL_LD_ST_DEC_PT(22) + OR TBL_LD_ST_DEC_PT(39) OR TBL_LD_ST_DEC_PT(61) + OR TBL_LD_ST_DEC_PT(71) OR TBL_LD_ST_DEC_PT(72) + ); +MQQ210:XU_LSU_RF1_OPTYPE16 <= + (TBL_LD_ST_DEC_PT(69)); +MQQ211:XU_LSU_RF1_OPTYPE2 <= + (TBL_LD_ST_DEC_PT(17) OR TBL_LD_ST_DEC_PT(19) + OR TBL_LD_ST_DEC_PT(28) OR TBL_LD_ST_DEC_PT(29) + OR TBL_LD_ST_DEC_PT(32) OR TBL_LD_ST_DEC_PT(45) + OR TBL_LD_ST_DEC_PT(64) OR TBL_LD_ST_DEC_PT(73) + OR TBL_LD_ST_DEC_PT(74)); +MQQ212:XU_LSU_RF1_OPTYPE32 <= + (TBL_LD_ST_DEC_PT(70)); +MQQ213:XU_LSU_RF1_OPTYPE4 <= + (TBL_LD_ST_DEC_PT(8) OR TBL_LD_ST_DEC_PT(20) + OR TBL_LD_ST_DEC_PT(26) OR TBL_LD_ST_DEC_PT(27) + OR TBL_LD_ST_DEC_PT(34) OR TBL_LD_ST_DEC_PT(37) + OR TBL_LD_ST_DEC_PT(44) OR TBL_LD_ST_DEC_PT(48) + OR TBL_LD_ST_DEC_PT(49) OR TBL_LD_ST_DEC_PT(55) + OR TBL_LD_ST_DEC_PT(57) OR TBL_LD_ST_DEC_PT(65) + OR TBL_LD_ST_DEC_PT(76)); +MQQ214:XU_LSU_RF1_OPTYPE8 <= + (TBL_LD_ST_DEC_PT(11) OR TBL_LD_ST_DEC_PT(15) + OR TBL_LD_ST_DEC_PT(25) OR TBL_LD_ST_DEC_PT(31) + OR TBL_LD_ST_DEC_PT(35) OR TBL_LD_ST_DEC_PT(38) + OR TBL_LD_ST_DEC_PT(41) OR TBL_LD_ST_DEC_PT(56) + OR TBL_LD_ST_DEC_PT(66) OR TBL_LD_ST_DEC_PT(75) + ); + +MQQ215:TBL_RECFORM_DEC_PT(1) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_INSTR_Q(31) ) , STD_ULOGIC_VECTOR'("01111111101101100")); +MQQ216:TBL_RECFORM_DEC_PT(2) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_INSTR_Q(31) ) , STD_ULOGIC_VECTOR'("01111101100101100")); +MQQ217:TBL_RECFORM_DEC_PT(3) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_INSTR_Q(31) ) , STD_ULOGIC_VECTOR'("01111111101101101")); +MQQ218:TBL_RECFORM_DEC_PT(4) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_INSTR_Q(31) ) , STD_ULOGIC_VECTOR'("01111101100101101")); +MQQ219:TBL_RECFORM_DEC_PT(5) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_INSTR_Q(31) ) , STD_ULOGIC_VECTOR'("0111000000111")); +MQQ220:TBL_RECFORM_DEC_PT(6) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("01110001111001")); +MQQ221:TBL_RECFORM_DEC_PT(7) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("01110110111001")); +MQQ222:TBL_RECFORM_DEC_PT(8) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("01110000110111")); +MQQ223:TBL_RECFORM_DEC_PT(9) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("01111100111011")); +MQQ224:TBL_RECFORM_DEC_PT(10) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("011101110101")); +MQQ225:TBL_RECFORM_DEC_PT(11) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(30) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("011100001011")); +MQQ226:TBL_RECFORM_DEC_PT(12) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("01111110110101")); +MQQ227:TBL_RECFORM_DEC_PT(13) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_INSTR_Q(31) ) , STD_ULOGIC_VECTOR'("0111001010001")); +MQQ228:TBL_RECFORM_DEC_PT(14) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(30) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("011101101001")); +MQQ229:TBL_RECFORM_DEC_PT(15) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_INSTR_Q(31) ) , STD_ULOGIC_VECTOR'("0111000010001")); +MQQ230:TBL_RECFORM_DEC_PT(16) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_INSTR_Q(31) ) , STD_ULOGIC_VECTOR'("0111000111001")); +MQQ231:TBL_RECFORM_DEC_PT(17) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_INSTR_Q(31) ) , STD_ULOGIC_VECTOR'("0111010111001")); +MQQ232:TBL_RECFORM_DEC_PT(18) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_INSTR_Q(31) ) , STD_ULOGIC_VECTOR'("0111000010101")); +MQQ233:TBL_RECFORM_DEC_PT(19) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_INSTR_Q(31) ) , STD_ULOGIC_VECTOR'("0111110110101")); +MQQ234:TBL_RECFORM_DEC_PT(20) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(30) & + RF1_INSTR_Q(31) ) , STD_ULOGIC_VECTOR'("0111110011001")); +MQQ235:TBL_RECFORM_DEC_PT(21) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(30) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("011101001001")); +MQQ236:TBL_RECFORM_DEC_PT(22) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("01110001")); +MQQ237:TBL_RECFORM_DEC_PT(23) <= + Eq(( RF1_INSTR_Q(31) & RF1_AXU_MFFGPR & + RF1_AXU_MOVEDP & RF1_VAL_STG + ) , STD_ULOGIC_VECTOR'("1111")); +MQQ238:TBL_RECFORM_DEC_PT(24) <= + Eq(( RF1_INSTR_Q(31) & RF1_AXU_MFTGPR & + RF1_AXU_MOVEDP & RF1_VAL_STG + ) , STD_ULOGIC_VECTOR'("1111")); +MQQ239:TBL_RECFORM_DEC_PT(25) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(31) ) , STD_ULOGIC_VECTOR'("0111001")); +MQQ240:TBL_RECFORM_DEC_PT(26) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(02) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) ) , STD_ULOGIC_VECTOR'("01101")); +MQQ241:TBL_RECFORM_DEC_PT(27) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) ) , STD_ULOGIC_VECTOR'("01110")); +MQQ242:TBL_RECFORM_DEC_PT(28) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("010111")); +MQQ243:TBL_RECFORM_DEC_PT(29) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(31) ) , STD_ULOGIC_VECTOR'("01101")); +MQQ244:RF1_USE_CRFLD0 <= + (TBL_RECFORM_DEC_PT(5) OR TBL_RECFORM_DEC_PT(6) + OR TBL_RECFORM_DEC_PT(7) OR TBL_RECFORM_DEC_PT(8) + OR TBL_RECFORM_DEC_PT(9) OR TBL_RECFORM_DEC_PT(10) + OR TBL_RECFORM_DEC_PT(11) OR TBL_RECFORM_DEC_PT(12) + OR TBL_RECFORM_DEC_PT(13) OR TBL_RECFORM_DEC_PT(15) + OR TBL_RECFORM_DEC_PT(16) OR TBL_RECFORM_DEC_PT(17) + OR TBL_RECFORM_DEC_PT(18) OR TBL_RECFORM_DEC_PT(19) + OR TBL_RECFORM_DEC_PT(20) OR TBL_RECFORM_DEC_PT(21) + OR TBL_RECFORM_DEC_PT(22) OR TBL_RECFORM_DEC_PT(23) + OR TBL_RECFORM_DEC_PT(24) OR TBL_RECFORM_DEC_PT(25) + OR TBL_RECFORM_DEC_PT(26) OR TBL_RECFORM_DEC_PT(27) + OR TBL_RECFORM_DEC_PT(28) OR TBL_RECFORM_DEC_PT(29) + ); +MQQ245:RF1_USE_CRFLD0_NMULT <= + (TBL_RECFORM_DEC_PT(5) OR TBL_RECFORM_DEC_PT(6) + OR TBL_RECFORM_DEC_PT(7) OR TBL_RECFORM_DEC_PT(8) + OR TBL_RECFORM_DEC_PT(9) OR TBL_RECFORM_DEC_PT(12) + OR TBL_RECFORM_DEC_PT(13) OR TBL_RECFORM_DEC_PT(14) + OR TBL_RECFORM_DEC_PT(15) OR TBL_RECFORM_DEC_PT(16) + OR TBL_RECFORM_DEC_PT(17) OR TBL_RECFORM_DEC_PT(18) + OR TBL_RECFORM_DEC_PT(19) OR TBL_RECFORM_DEC_PT(20) + OR TBL_RECFORM_DEC_PT(21) OR TBL_RECFORM_DEC_PT(22) + OR TBL_RECFORM_DEC_PT(23) OR TBL_RECFORM_DEC_PT(24) + OR TBL_RECFORM_DEC_PT(25) OR TBL_RECFORM_DEC_PT(26) + OR TBL_RECFORM_DEC_PT(27) OR TBL_RECFORM_DEC_PT(28) + OR TBL_RECFORM_DEC_PT(29)); +MQQ246:XU_LSU_RF1_ICSWX_INSTR <= + (TBL_RECFORM_DEC_PT(1) OR TBL_RECFORM_DEC_PT(2) + ); +MQQ247:XU_LSU_RF1_ICSWX_DOT_INSTR <= + (TBL_RECFORM_DEC_PT(3) OR TBL_RECFORM_DEC_PT(4) + ); +MQQ248:XU_LSU_RF1_ICSWX_EPID <= + (TBL_RECFORM_DEC_PT(1) OR TBL_RECFORM_DEC_PT(3) + ); +MQQ249:EX1_IS_ICSWX_D <= + (TBL_RECFORM_DEC_PT(1) OR TBL_RECFORM_DEC_PT(2) + OR TBL_RECFORM_DEC_PT(3) OR TBL_RECFORM_DEC_PT(4) + ); + +MQQ250:TBL_XER_DEC_PT(1) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(11) & RF1_INSTR_Q(12) & + RF1_INSTR_Q(13) & RF1_INSTR_Q(14) & + RF1_INSTR_Q(15) & RF1_INSTR_Q(16) & + RF1_INSTR_Q(17) & RF1_INSTR_Q(18) & + RF1_INSTR_Q(19) & RF1_INSTR_Q(20) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111100001000000101010011")); +MQQ251:TBL_XER_DEC_PT(2) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) ) , STD_ULOGIC_VECTOR'("011111110011101")); +MQQ252:TBL_XER_DEC_PT(3) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("01111100111011")); +MQQ253:TBL_XER_DEC_PT(4) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(21) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111001010110")); +MQQ254:TBL_XER_DEC_PT(5) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111100101000")); +MQQ255:TBL_XER_DEC_PT(6) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("01110110111001")); +MQQ256:TBL_XER_DEC_PT(7) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111100001010")); +MQQ257:TBL_XER_DEC_PT(8) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("01110001111001")); +MQQ258:TBL_XER_DEC_PT(9) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) + ) , STD_ULOGIC_VECTOR'("01111110111010")); +MQQ259:TBL_XER_DEC_PT(10) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(21) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111000000000")); +MQQ260:TBL_XER_DEC_PT(11) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111110110100")); +MQQ261:TBL_XER_DEC_PT(12) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("01111110110101")); +MQQ262:TBL_XER_DEC_PT(13) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111111001100")); +MQQ263:TBL_XER_DEC_PT(14) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(30) & + RF1_INSTR_Q(31) ) , STD_ULOGIC_VECTOR'("0111110011001")); +MQQ264:TBL_XER_DEC_PT(15) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_INSTR_Q(31) ) , STD_ULOGIC_VECTOR'("0111010111001")); +MQQ265:TBL_XER_DEC_PT(16) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("0111111110101")); +MQQ266:TBL_XER_DEC_PT(17) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111110000100")); +MQQ267:TBL_XER_DEC_PT(18) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_INSTR_Q(31) ) , STD_ULOGIC_VECTOR'("0111000111001")); +MQQ268:TBL_XER_DEC_PT(19) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_INSTR_Q(31) ) , STD_ULOGIC_VECTOR'("0111000010111")); +MQQ269:TBL_XER_DEC_PT(20) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("0111110110100")); +MQQ270:TBL_XER_DEC_PT(21) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("0111110100100")); +MQQ271:TBL_XER_DEC_PT(22) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_INSTR_Q(31) ) , STD_ULOGIC_VECTOR'("0111110110101")); +MQQ272:TBL_XER_DEC_PT(23) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_INSTR_Q(31) ) , STD_ULOGIC_VECTOR'("0111001010001")); +MQQ273:TBL_XER_DEC_PT(24) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(30) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("011101001001")); +MQQ274:TBL_XER_DEC_PT(25) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("0111110000100")); +MQQ275:TBL_XER_DEC_PT(26) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_INSTR_Q(31) ) , STD_ULOGIC_VECTOR'("0111000010001")); +MQQ276:TBL_XER_DEC_PT(27) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_INSTR_Q(31) ) , STD_ULOGIC_VECTOR'("0111000010101")); +MQQ277:TBL_XER_DEC_PT(28) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("011101110101")); +MQQ278:TBL_XER_DEC_PT(29) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(30) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("011100001011")); +MQQ279:TBL_XER_DEC_PT(30) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) ) , STD_ULOGIC_VECTOR'("00100")); +MQQ280:TBL_XER_DEC_PT(31) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("01110001")); +MQQ281:TBL_XER_DEC_PT(32) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) ) , STD_ULOGIC_VECTOR'("00101")); +MQQ282:TBL_XER_DEC_PT(33) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(31) ) , STD_ULOGIC_VECTOR'("0111001")); +MQQ283:TBL_XER_DEC_PT(34) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) + ) , STD_ULOGIC_VECTOR'("001101")); +MQQ284:TBL_XER_DEC_PT(35) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("010111")); +MQQ285:TBL_XER_DEC_PT(36) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(31) ) , STD_ULOGIC_VECTOR'("01101")); +MQQ286:TBL_XER_DEC_PT(37) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) ) , STD_ULOGIC_VECTOR'("01110")); +MQQ287:DEC_BYP_RF1_CA_USED <= + (TBL_XER_DEC_PT(1) OR TBL_XER_DEC_PT(20) + OR TBL_XER_DEC_PT(21)); +MQQ288:DEC_BYP_RF1_OV_USED <= + (TBL_XER_DEC_PT(1) OR TBL_XER_DEC_PT(3) + OR TBL_XER_DEC_PT(4) OR TBL_XER_DEC_PT(6) + OR TBL_XER_DEC_PT(8) OR TBL_XER_DEC_PT(10) + OR TBL_XER_DEC_PT(12) OR TBL_XER_DEC_PT(14) + OR TBL_XER_DEC_PT(15) OR TBL_XER_DEC_PT(18) + OR TBL_XER_DEC_PT(19) OR TBL_XER_DEC_PT(22) + OR TBL_XER_DEC_PT(23) OR TBL_XER_DEC_PT(24) + OR TBL_XER_DEC_PT(26) OR TBL_XER_DEC_PT(27) + OR TBL_XER_DEC_PT(28) OR TBL_XER_DEC_PT(29) + OR TBL_XER_DEC_PT(31) OR TBL_XER_DEC_PT(32) + OR TBL_XER_DEC_PT(33) OR TBL_XER_DEC_PT(34) + OR TBL_XER_DEC_PT(35) OR TBL_XER_DEC_PT(36) + OR TBL_XER_DEC_PT(37)); +MQQ289:RF1_XER_CA_UPDATE <= + (TBL_XER_DEC_PT(2) OR TBL_XER_DEC_PT(13) + OR TBL_XER_DEC_PT(20) OR TBL_XER_DEC_PT(25) + OR TBL_XER_DEC_PT(30) OR TBL_XER_DEC_PT(34) + ); +MQQ290:RF1_XER_OV_UPDATE <= + (TBL_XER_DEC_PT(5) OR TBL_XER_DEC_PT(7) + OR TBL_XER_DEC_PT(9) OR TBL_XER_DEC_PT(11) + OR TBL_XER_DEC_PT(16) OR TBL_XER_DEC_PT(17) + ); + +MQQ291:TBL_PRI_CHANGE_PT(1) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(06) & RF1_INSTR_Q(07) & + RF1_INSTR_Q(08) & RF1_INSTR_Q(09) & + RF1_INSTR_Q(10) & RF1_INSTR_Q(11) & + RF1_INSTR_Q(12) & RF1_INSTR_Q(13) & + RF1_INSTR_Q(14) & RF1_INSTR_Q(15) & + RF1_INSTR_Q(16) & RF1_INSTR_Q(17) & + RF1_INSTR_Q(18) & RF1_INSTR_Q(19) & + RF1_INSTR_Q(20) & RF1_INSTR_Q(21) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("01111111111111111111101101111000")); +MQQ292:TBL_PRI_CHANGE_PT(2) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(06) & RF1_INSTR_Q(07) & + RF1_INSTR_Q(08) & RF1_INSTR_Q(09) & + RF1_INSTR_Q(10) & RF1_INSTR_Q(11) & + RF1_INSTR_Q(12) & RF1_INSTR_Q(13) & + RF1_INSTR_Q(14) & RF1_INSTR_Q(15) & + RF1_INSTR_Q(16) & RF1_INSTR_Q(17) & + RF1_INSTR_Q(18) & RF1_INSTR_Q(19) & + RF1_INSTR_Q(20) & RF1_INSTR_Q(21) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("01111100010000100001001101111000")); +MQQ293:TBL_PRI_CHANGE_PT(3) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(06) & RF1_INSTR_Q(07) & + RF1_INSTR_Q(08) & RF1_INSTR_Q(09) & + RF1_INSTR_Q(10) & RF1_INSTR_Q(11) & + RF1_INSTR_Q(12) & RF1_INSTR_Q(13) & + RF1_INSTR_Q(14) & RF1_INSTR_Q(15) & + RF1_INSTR_Q(16) & RF1_INSTR_Q(17) & + RF1_INSTR_Q(18) & RF1_INSTR_Q(19) & + RF1_INSTR_Q(20) & RF1_INSTR_Q(21) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("01111100001000010000101101111000")); +MQQ294:TBL_PRI_CHANGE_PT(4) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(06) & RF1_INSTR_Q(07) & + RF1_INSTR_Q(08) & RF1_INSTR_Q(09) & + RF1_INSTR_Q(10) & RF1_INSTR_Q(11) & + RF1_INSTR_Q(12) & RF1_INSTR_Q(13) & + RF1_INSTR_Q(14) & RF1_INSTR_Q(15) & + RF1_INSTR_Q(16) & RF1_INSTR_Q(17) & + RF1_INSTR_Q(18) & RF1_INSTR_Q(19) & + RF1_INSTR_Q(20) & RF1_INSTR_Q(21) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("01111100101001010010101101111000")); +MQQ295:TBL_PRI_CHANGE_PT(5) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(06) & RF1_INSTR_Q(07) & + RF1_INSTR_Q(08) & RF1_INSTR_Q(09) & + RF1_INSTR_Q(10) & RF1_INSTR_Q(11) & + RF1_INSTR_Q(12) & RF1_INSTR_Q(13) & + RF1_INSTR_Q(14) & RF1_INSTR_Q(15) & + RF1_INSTR_Q(16) & RF1_INSTR_Q(17) & + RF1_INSTR_Q(18) & RF1_INSTR_Q(19) & + RF1_INSTR_Q(20) & RF1_INSTR_Q(21) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("01111100110001100011001101111000")); +MQQ296:TBL_PRI_CHANGE_PT(6) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(06) & RF1_INSTR_Q(07) & + RF1_INSTR_Q(08) & RF1_INSTR_Q(09) & + RF1_INSTR_Q(10) & RF1_INSTR_Q(11) & + RF1_INSTR_Q(12) & RF1_INSTR_Q(13) & + RF1_INSTR_Q(14) & RF1_INSTR_Q(15) & + RF1_INSTR_Q(16) & RF1_INSTR_Q(17) & + RF1_INSTR_Q(18) & RF1_INSTR_Q(19) & + RF1_INSTR_Q(20) & RF1_INSTR_Q(21) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("01111100011000110001101101111000")); +MQQ297:TBL_PRI_CHANGE_PT(7) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(06) & RF1_INSTR_Q(07) & + RF1_INSTR_Q(08) & RF1_INSTR_Q(09) & + RF1_INSTR_Q(10) & RF1_INSTR_Q(11) & + RF1_INSTR_Q(12) & RF1_INSTR_Q(13) & + RF1_INSTR_Q(14) & RF1_INSTR_Q(15) & + RF1_INSTR_Q(16) & RF1_INSTR_Q(17) & + RF1_INSTR_Q(18) & RF1_INSTR_Q(19) & + RF1_INSTR_Q(20) & RF1_INSTR_Q(21) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("01111100111001110011101101111000")); +MQQ298:RF1_PRI(00) <= + (TBL_PRI_CHANGE_PT(2) OR TBL_PRI_CHANGE_PT(4) + OR TBL_PRI_CHANGE_PT(6) OR TBL_PRI_CHANGE_PT(7) + ); +MQQ299:RF1_PRI(01) <= + (TBL_PRI_CHANGE_PT(3) OR TBL_PRI_CHANGE_PT(5) + OR TBL_PRI_CHANGE_PT(6) OR TBL_PRI_CHANGE_PT(7) + ); +MQQ300:RF1_PRI(02) <= + (TBL_PRI_CHANGE_PT(1) OR TBL_PRI_CHANGE_PT(4) + OR TBL_PRI_CHANGE_PT(5) OR TBL_PRI_CHANGE_PT(7) + ); + +MQQ301:TBL_VAL_STG_GATE_PT(1) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(11) & RF1_INSTR_Q(12) & + RF1_INSTR_Q(13) & RF1_INSTR_Q(14) & + RF1_INSTR_Q(15) & RF1_INSTR_Q(16) & + RF1_INSTR_Q(17) & RF1_INSTR_Q(18) & + RF1_INSTR_Q(19) & RF1_INSTR_Q(20) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_VAL_STG ) , STD_ULOGIC_VECTOR'("011111011101111101110100111")); +MQQ302:TBL_VAL_STG_GATE_PT(2) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) & RF1_AXU_MOVEDP & + RF1_VAL_STG ) , STD_ULOGIC_VECTOR'("01111100000001101")); +MQQ303:TBL_VAL_STG_GATE_PT(3) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_VAL_STG ) , STD_ULOGIC_VECTOR'("01111111100001101")); +MQQ304:TBL_VAL_STG_GATE_PT(4) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_VAL_STG ) , STD_ULOGIC_VECTOR'("01111100110011101")); +MQQ305:TBL_VAL_STG_GATE_PT(5) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_VAL_STG ) , STD_ULOGIC_VECTOR'("01111111010101101")); +MQQ306:TBL_VAL_STG_GATE_PT(6) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_VAL_STG ) , STD_ULOGIC_VECTOR'("01111110001101101")); +MQQ307:TBL_VAL_STG_GATE_PT(7) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_VAL_STG ) , STD_ULOGIC_VECTOR'("01111111101001101")); +MQQ308:TBL_VAL_STG_GATE_PT(8) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_VAL_STG ) , STD_ULOGIC_VECTOR'("01111110010101101")); +MQQ309:TBL_VAL_STG_GATE_PT(9) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) & RF1_VAL_STG + ) , STD_ULOGIC_VECTOR'("0111111110101101")); +MQQ310:TBL_VAL_STG_GATE_PT(10) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) & RF1_VAL_STG + ) , STD_ULOGIC_VECTOR'("0111110001000111")); +MQQ311:TBL_VAL_STG_GATE_PT(11) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) & RF1_VAL_STG + ) , STD_ULOGIC_VECTOR'("0111110000000111")); +MQQ312:TBL_VAL_STG_GATE_PT(12) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) & RF1_VAL_STG + ) , STD_ULOGIC_VECTOR'("0111111111111111")); +MQQ313:TBL_VAL_STG_GATE_PT(13) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) & RF1_VAL_STG + ) , STD_ULOGIC_VECTOR'("0111110111001101")); +MQQ314:TBL_VAL_STG_GATE_PT(14) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_VAL_STG ) , STD_ULOGIC_VECTOR'("011111001101111")); +MQQ315:TBL_VAL_STG_GATE_PT(15) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_VAL_STG ) , STD_ULOGIC_VECTOR'("011111010010111")); +MQQ316:TBL_VAL_STG_GATE_PT(16) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_VAL_STG ) , STD_ULOGIC_VECTOR'("011111001010111")); +MQQ317:TBL_VAL_STG_GATE_PT(17) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) & RF1_VAL_STG + ) , STD_ULOGIC_VECTOR'("01111111001101")); +MQQ318:TBL_VAL_STG_GATE_PT(18) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) & RF1_VAL_STG + ) , STD_ULOGIC_VECTOR'("01111100011111")); +MQQ319:TBL_VAL_STG_GATE_PT(19) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) & RF1_VAL_STG + ) , STD_ULOGIC_VECTOR'("0111110010001101")); +MQQ320:TBL_VAL_STG_GATE_PT(20) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_VAL_STG ) , STD_ULOGIC_VECTOR'("011111010001101")); +MQQ321:TBL_VAL_STG_GATE_PT(21) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(30) & RF1_VAL_STG + ) , STD_ULOGIC_VECTOR'("0111110101010111")); +MQQ322:TBL_VAL_STG_GATE_PT(22) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_VAL_STG ) , STD_ULOGIC_VECTOR'("011111010101101")); +MQQ323:TBL_VAL_STG_GATE_PT(23) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_VAL_STG ) , STD_ULOGIC_VECTOR'("011111000111111")); +MQQ324:TBL_VAL_STG_GATE_PT(24) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) & RF1_VAL_STG + ) , STD_ULOGIC_VECTOR'("0111110010101001")); +MQQ325:TBL_VAL_STG_GATE_PT(25) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) & RF1_VAL_STG + ) , STD_ULOGIC_VECTOR'("0111110000101101")); +MQQ326:TBL_VAL_STG_GATE_PT(26) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_VAL_STG ) , STD_ULOGIC_VECTOR'("011111001111111")); +MQQ327:TBL_VAL_STG_GATE_PT(27) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_VAL_STG + ) , STD_ULOGIC_VECTOR'("0111110000010101")); +MQQ328:TBL_VAL_STG_GATE_PT(28) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_VAL_STG ) , STD_ULOGIC_VECTOR'("011111111101101")); +MQQ329:TBL_VAL_STG_GATE_PT(29) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_VAL_STG ) , STD_ULOGIC_VECTOR'("011111001110111")); +MQQ330:TBL_VAL_STG_GATE_PT(30) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(30) & + RF1_VAL_STG ) , STD_ULOGIC_VECTOR'("011111100010101")); +MQQ331:TBL_VAL_STG_GATE_PT(31) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(30) & + RF1_VAL_STG ) , STD_ULOGIC_VECTOR'("011111001010111")); +MQQ332:TBL_VAL_STG_GATE_PT(32) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_VAL_STG ) , STD_ULOGIC_VECTOR'("011111100101101")); +MQQ333:TBL_VAL_STG_GATE_PT(33) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_VAL_STG ) , STD_ULOGIC_VECTOR'("011111010101111")); +MQQ334:TBL_VAL_STG_GATE_PT(34) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(30) & RF1_VAL_STG + ) , STD_ULOGIC_VECTOR'("01111100001111")); +MQQ335:TBL_VAL_STG_GATE_PT(35) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_VAL_STG + ) , STD_ULOGIC_VECTOR'("01111100010111")); +MQQ336:TBL_VAL_STG_GATE_PT(36) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_VAL_STG + ) , STD_ULOGIC_VECTOR'("01111100010111")); +MQQ337:TBL_VAL_STG_GATE_PT(37) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) & RF1_VAL_STG + ) , STD_ULOGIC_VECTOR'("01111100011111")); +MQQ338:TBL_VAL_STG_GATE_PT(38) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(02) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(31) & + RF1_VAL_STG ) , STD_ULOGIC_VECTOR'("1101001")); +MQQ339:TBL_VAL_STG_GATE_PT(39) <= + Eq(( RF1_AXU_LD_OR_ST_Q & RF1_AXU_MFTGPR & + RF1_AXU_MFFGPR & RF1_AXU_MOVEDP & + RF1_VAL_STG ) , STD_ULOGIC_VECTOR'("10001")); +MQQ340:TBL_VAL_STG_GATE_PT(40) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(05) & + RF1_VAL_STG ) , STD_ULOGIC_VECTOR'("10001")); +MQQ341:TBL_VAL_STG_GATE_PT(41) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(30) & RF1_VAL_STG + ) , STD_ULOGIC_VECTOR'("11111001")); +MQQ342:TBL_VAL_STG_GATE_PT(42) <= + Eq(( RF1_AXU_MFFGPR & RF1_AXU_MOVEDP & + RF1_VAL_STG ) , STD_ULOGIC_VECTOR'("111")); +MQQ343:TBL_VAL_STG_GATE_PT(43) <= + Eq(( RF1_AXU_MFTGPR & RF1_AXU_MOVEDP & + RF1_VAL_STG ) , STD_ULOGIC_VECTOR'("111")); +MQQ344:TBL_VAL_STG_GATE_PT(44) <= + Eq(( RF1_AXU_MFTGPR & RF1_AXU_MOVEDP & + RF1_VAL_STG ) , STD_ULOGIC_VECTOR'("101")); +MQQ345:TBL_VAL_STG_GATE_PT(45) <= + Eq(( RF1_AXU_MFFGPR & RF1_AXU_MOVEDP & + RF1_VAL_STG ) , STD_ULOGIC_VECTOR'("101")); +MQQ346:TBL_VAL_STG_GATE_PT(46) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(04) & + RF1_VAL_STG ) , STD_ULOGIC_VECTOR'("10101")); +MQQ347:TBL_VAL_STG_GATE_PT(47) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_VAL_STG ) , STD_ULOGIC_VECTOR'("10011")); +MQQ348:RF1_CACHE_ACC <= + (TBL_VAL_STG_GATE_PT(7) OR TBL_VAL_STG_GATE_PT(12) + OR TBL_VAL_STG_GATE_PT(13) OR TBL_VAL_STG_GATE_PT(19) + OR TBL_VAL_STG_GATE_PT(20) OR TBL_VAL_STG_GATE_PT(21) + OR TBL_VAL_STG_GATE_PT(22) OR TBL_VAL_STG_GATE_PT(23) + OR TBL_VAL_STG_GATE_PT(24) OR TBL_VAL_STG_GATE_PT(25) + OR TBL_VAL_STG_GATE_PT(26) OR TBL_VAL_STG_GATE_PT(27) + OR TBL_VAL_STG_GATE_PT(28) OR TBL_VAL_STG_GATE_PT(29) + OR TBL_VAL_STG_GATE_PT(30) OR TBL_VAL_STG_GATE_PT(31) + OR TBL_VAL_STG_GATE_PT(32) OR TBL_VAL_STG_GATE_PT(33) + OR TBL_VAL_STG_GATE_PT(34) OR TBL_VAL_STG_GATE_PT(35) + OR TBL_VAL_STG_GATE_PT(36) OR TBL_VAL_STG_GATE_PT(37) + OR TBL_VAL_STG_GATE_PT(38) OR TBL_VAL_STG_GATE_PT(39) + OR TBL_VAL_STG_GATE_PT(40) OR TBL_VAL_STG_GATE_PT(41) + OR TBL_VAL_STG_GATE_PT(46) OR TBL_VAL_STG_GATE_PT(47) + ); +MQQ349:XU_LSU_RF1_IS_MSGSND <= + (TBL_VAL_STG_GATE_PT(4)); +MQQ350:XU_LSU_RF1_MBAR_INSTR <= + (TBL_VAL_STG_GATE_PT(5)); +MQQ351:XU_LSU_RF1_SYNC_INSTR <= + (TBL_VAL_STG_GATE_PT(8)); +MQQ352:XU_LSU_RF1_TLBSYNC_INSTR <= + (TBL_VAL_STG_GATE_PT(6)); +MQQ353:XU_LSU_RF1_WCLR_INSTR <= + (TBL_VAL_STG_GATE_PT(7)); +MQQ354:XU_LSU_RF1_WCHK_INSTR <= + (TBL_VAL_STG_GATE_PT(3)); +MQQ355:XU_LSU_RF1_SRC_GPR <= + (TBL_VAL_STG_GATE_PT(10) OR TBL_VAL_STG_GATE_PT(45) + ); +MQQ356:XU_LSU_RF1_SRC_AXU <= + (TBL_VAL_STG_GATE_PT(43) OR TBL_VAL_STG_GATE_PT(44) + ); +MQQ357:XU_LSU_RF1_SRC_DP <= + (TBL_VAL_STG_GATE_PT(11) OR TBL_VAL_STG_GATE_PT(42) + ); +MQQ358:XU_LSU_RF1_TARG_GPR <= + (TBL_VAL_STG_GATE_PT(2) OR TBL_VAL_STG_GATE_PT(44) + ); +MQQ359:XU_LSU_RF1_TARG_AXU <= + (TBL_VAL_STG_GATE_PT(42) OR TBL_VAL_STG_GATE_PT(45) + ); +MQQ360:XU_LSU_RF1_TARG_DP <= + (TBL_VAL_STG_GATE_PT(10) OR TBL_VAL_STG_GATE_PT(43) + ); +MQQ361:RF1_CMD_ACT <= + (TBL_VAL_STG_GATE_PT(1) OR TBL_VAL_STG_GATE_PT(4) + OR TBL_VAL_STG_GATE_PT(5) OR TBL_VAL_STG_GATE_PT(6) + OR TBL_VAL_STG_GATE_PT(7) OR TBL_VAL_STG_GATE_PT(8) + OR TBL_VAL_STG_GATE_PT(10) OR TBL_VAL_STG_GATE_PT(11) + OR TBL_VAL_STG_GATE_PT(12) OR TBL_VAL_STG_GATE_PT(13) + OR TBL_VAL_STG_GATE_PT(17) OR TBL_VAL_STG_GATE_PT(19) + OR TBL_VAL_STG_GATE_PT(21) OR TBL_VAL_STG_GATE_PT(23) + OR TBL_VAL_STG_GATE_PT(24) OR TBL_VAL_STG_GATE_PT(25) + OR TBL_VAL_STG_GATE_PT(26) OR TBL_VAL_STG_GATE_PT(27) + OR TBL_VAL_STG_GATE_PT(28) OR TBL_VAL_STG_GATE_PT(29) + OR TBL_VAL_STG_GATE_PT(30) OR TBL_VAL_STG_GATE_PT(31) + OR TBL_VAL_STG_GATE_PT(32) OR TBL_VAL_STG_GATE_PT(33) + OR TBL_VAL_STG_GATE_PT(34) OR TBL_VAL_STG_GATE_PT(35) + OR TBL_VAL_STG_GATE_PT(36) OR TBL_VAL_STG_GATE_PT(37) + OR TBL_VAL_STG_GATE_PT(38) OR TBL_VAL_STG_GATE_PT(39) + OR TBL_VAL_STG_GATE_PT(40) OR TBL_VAL_STG_GATE_PT(41) + OR TBL_VAL_STG_GATE_PT(42) OR TBL_VAL_STG_GATE_PT(43) + OR TBL_VAL_STG_GATE_PT(44) OR TBL_VAL_STG_GATE_PT(45) + OR TBL_VAL_STG_GATE_PT(46) OR TBL_VAL_STG_GATE_PT(47) + ); +MQQ362:XU_LSU_RF1_DATA_ACT <= + (TBL_VAL_STG_GATE_PT(9) OR TBL_VAL_STG_GATE_PT(10) + OR TBL_VAL_STG_GATE_PT(11) OR TBL_VAL_STG_GATE_PT(14) + OR TBL_VAL_STG_GATE_PT(15) OR TBL_VAL_STG_GATE_PT(16) + OR TBL_VAL_STG_GATE_PT(18) OR TBL_VAL_STG_GATE_PT(21) + OR TBL_VAL_STG_GATE_PT(24) OR TBL_VAL_STG_GATE_PT(27) + OR TBL_VAL_STG_GATE_PT(30) OR TBL_VAL_STG_GATE_PT(31) + OR TBL_VAL_STG_GATE_PT(32) OR TBL_VAL_STG_GATE_PT(33) + OR TBL_VAL_STG_GATE_PT(34) OR TBL_VAL_STG_GATE_PT(37) + OR TBL_VAL_STG_GATE_PT(38) OR TBL_VAL_STG_GATE_PT(39) + OR TBL_VAL_STG_GATE_PT(40) OR TBL_VAL_STG_GATE_PT(41) + OR TBL_VAL_STG_GATE_PT(42) OR TBL_VAL_STG_GATE_PT(43) + OR TBL_VAL_STG_GATE_PT(44) OR TBL_VAL_STG_GATE_PT(45) + OR TBL_VAL_STG_GATE_PT(46) OR TBL_VAL_STG_GATE_PT(47) + ); +MQQ363:RF1_MTSPR_TRACE <= + (TBL_VAL_STG_GATE_PT(1)); +MQQ364:RF1_DERAT_ACT <= + (TBL_VAL_STG_GATE_PT(12) OR TBL_VAL_STG_GATE_PT(13) + OR TBL_VAL_STG_GATE_PT(19) OR TBL_VAL_STG_GATE_PT(20) + OR TBL_VAL_STG_GATE_PT(21) OR TBL_VAL_STG_GATE_PT(22) + OR TBL_VAL_STG_GATE_PT(23) OR TBL_VAL_STG_GATE_PT(24) + OR TBL_VAL_STG_GATE_PT(25) OR TBL_VAL_STG_GATE_PT(26) + OR TBL_VAL_STG_GATE_PT(27) OR TBL_VAL_STG_GATE_PT(28) + OR TBL_VAL_STG_GATE_PT(29) OR TBL_VAL_STG_GATE_PT(30) + OR TBL_VAL_STG_GATE_PT(31) OR TBL_VAL_STG_GATE_PT(32) + OR TBL_VAL_STG_GATE_PT(33) OR TBL_VAL_STG_GATE_PT(34) + OR TBL_VAL_STG_GATE_PT(35) OR TBL_VAL_STG_GATE_PT(36) + OR TBL_VAL_STG_GATE_PT(37) OR TBL_VAL_STG_GATE_PT(38) + OR TBL_VAL_STG_GATE_PT(39) OR TBL_VAL_STG_GATE_PT(40) + OR TBL_VAL_STG_GATE_PT(41) OR TBL_VAL_STG_GATE_PT(46) + OR TBL_VAL_STG_GATE_PT(47)); + +mark_unused(rf1_num_bytes_plus3(6 to 7)); +mark_unused(ex1_dp_rot_amt(0)); +is1_need_hole_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(is1_need_hole_offset), + scout => sov(is1_need_hole_offset), + din => is1_need_hole_d, + dout => is1_need_hole_q); +is2_need_hole_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(is2_need_hole_offset), + scout => sov(is2_need_hole_offset), + din => is2_need_hole_d, + dout => is2_need_hole_q); +rf0_back_inv_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_back_inv_offset), + scout => sov(rf0_back_inv_offset), + din => lsu_xu_is2_back_inv , + dout => rf0_back_inv_q); +rf0_back_inv_addr_latch : tri_rlmreg_p + generic map (width => rf0_back_inv_addr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => lsu_xu_is2_back_inv , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_back_inv_addr_offset to rf0_back_inv_addr_offset + rf0_back_inv_addr_q'length-1), + scout => sov(rf0_back_inv_addr_offset to rf0_back_inv_addr_offset + rf0_back_inv_addr_q'length-1), + din => lsu_xu_is2_back_inv_addr , + dout => rf0_back_inv_addr_q); +rf0_need_hole_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_need_hole_offset), + scout => sov(rf0_need_hole_offset), + din => is2_need_hole_q , + dout => rf0_need_hole_q); +rf1_3src_instr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => fxa_fxb_rf0_3src_instr , + dout(0) => rf1_3src_instr_q); +rf1_act_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf1_act_offset), + scout => sov(rf1_act_offset), + din => rf0_act, + dout => rf1_act_q); +rf1_axu_instr_type_latch : tri_regk + generic map (width => rf1_axu_instr_type_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => fxa_fxb_rf0_axu_instr_type , + dout => rf1_axu_instr_type_q); +rf1_axu_is_extload_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => fxa_fxb_rf0_axu_is_extload , + dout(0) => rf1_axu_is_extload_q); +rf1_axu_is_extstore_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => fxa_fxb_rf0_axu_is_extstore , + dout(0) => rf1_axu_is_extstore_q); +rf1_axu_ld_or_st_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf1_axu_ld_or_st_offset), + scout => sov(rf1_axu_ld_or_st_offset), + din => fxa_fxb_rf0_axu_ld_or_st , + dout => rf1_axu_ld_or_st_q); +rf1_axu_ldst_forcealign_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => fxa_fxb_rf0_axu_ldst_forcealign , + dout(0) => rf1_axu_ldst_forcealign_q); +rf1_axu_ldst_forceexcept_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => fxa_fxb_rf0_axu_ldst_forceexcept , + dout(0) => rf1_axu_ldst_forceexcept_q); +rf1_axu_ldst_indexed_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => fxa_fxb_rf0_axu_ldst_indexed , + dout(0) => rf1_axu_ldst_indexed_q); +rf1_axu_ldst_size_latch : tri_regk + generic map (width => rf1_axu_ldst_size_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => fxa_fxb_rf0_axu_ldst_size , + dout => rf1_axu_ldst_size_q); +rf1_axu_ldst_tag_latch : tri_regk + generic map (width => rf1_axu_ldst_tag_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => fxa_fxb_rf0_axu_ldst_tag , + dout => rf1_axu_ldst_tag_q); +rf1_axu_ldst_update_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => fxa_fxb_rf0_axu_ldst_update , + dout(0) => rf1_axu_ldst_update_q); +rf1_axu_mffgpr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => fxa_fxb_rf0_axu_mffgpr , + dout(0) => rf1_axu_mffgpr_q); +rf1_axu_mftgpr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => fxa_fxb_rf0_axu_mftgpr , + dout(0) => rf1_axu_mftgpr_q); +rf1_axu_movedp_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => fxa_fxb_rf0_axu_movedp , + dout(0) => rf1_axu_movedp_q); +rf1_axu_store_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => fxa_fxb_rf0_axu_store , + dout(0) => rf1_axu_store_q); +rf1_back_inv_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(rf1_back_inv_offset), + scout => sov(rf1_back_inv_offset), + din => rf0_back_inv_q , + dout => rf1_back_inv_q); +rf1_back_inv_addr_latch : tri_regk + generic map (width => rf1_back_inv_addr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_back_inv_q , + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => rf0_back_inv_addr_q , + dout => rf1_back_inv_addr_q); +rf1_error_latch : tri_regk + generic map (width => rf1_error_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => fxa_fxb_rf0_error , + dout => rf1_error_q); +rf1_gpr0_zero_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => fxa_fxb_rf0_gpr0_zero , + dout(0) => rf1_gpr0_zero_q); +rf1_gshare_latch : tri_regk + generic map (width => rf1_gshare_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => fxa_fxb_rf0_gshare , + dout => rf1_gshare_q); +rf1_ifar_latch : tri_regk + generic map (width => rf1_ifar_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => fxa_fxb_rf0_ifar , + dout => rf1_ifar_q); +rf1_instr_latch : tri_regk + generic map (width => rf1_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => fxa_fxb_rf0_instr , + dout => rf1_instr_q); +rf1_instr_21to30_00_latch : tri_regk + generic map (width => rf1_instr_21to30_00_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rf1_instr_21to30_00_d, + dout => rf1_instr_21to30_00_q); +rf1_instr_21to30_01_latch : tri_regk + generic map (width => rf1_instr_21to30_01_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rf1_instr_21to30_01_d, + dout => rf1_instr_21to30_01_q); +rf1_instr_21to30_02_latch : tri_regk + generic map (width => rf1_instr_21to30_02_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rf1_instr_21to30_02_d, + dout => rf1_instr_21to30_02_q); +rf1_instr_21to30_03_latch : tri_regk + generic map (width => rf1_instr_21to30_03_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rf1_instr_21to30_03_d, + dout => rf1_instr_21to30_03_q); +rf1_instr_21to30_04_latch : tri_regk + generic map (width => rf1_instr_21to30_04_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rf1_instr_21to30_04_d, + dout => rf1_instr_21to30_04_q); +rf1_instr_21to30_05_latch : tri_regk + generic map (width => rf1_instr_21to30_05_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rf1_instr_21to30_05_d, + dout => rf1_instr_21to30_05_q); +rf1_instr_21to30_06_latch : tri_regk + generic map (width => rf1_instr_21to30_06_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rf1_instr_21to30_06_d, + dout => rf1_instr_21to30_06_q); +rf1_instr_21to30_07_latch : tri_regk + generic map (width => rf1_instr_21to30_07_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rf1_instr_21to30_07_d, + dout => rf1_instr_21to30_07_q); +rf1_instr_21to30_08_latch : tri_regk + generic map (width => rf1_instr_21to30_08_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rf1_instr_21to30_08_d, + dout => rf1_instr_21to30_08_q); +rf1_instr_21to30_09_latch : tri_regk + generic map (width => rf1_instr_21to30_09_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rf1_instr_21to30_09_d, + dout => rf1_instr_21to30_09_q); +rf1_instr_21to30_10_latch : tri_regk + generic map (width => rf1_instr_21to30_10_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rf1_instr_21to30_10_d, + dout => rf1_instr_21to30_10_q); +rf1_is_isel_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rf1_is_isel_d, + dout(0) => rf1_is_isel_q); +rf1_is_ucode_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => fxa_fxb_rf0_is_ucode , + dout(0) => rf1_is_ucode_q); +rf1_issued_latch : tri_regk + generic map (width => rf1_issued_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => fxa_fxb_rf0_issued , + dout => rf1_issued_q); +rf1_match_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => fxa_fxb_rf0_match , + dout(0) => rf1_match_q); +rf1_mc_dep_chk_val_latch : tri_regk + generic map (width => rf1_mc_dep_chk_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rf1_mc_dep_chk_val_d, + dout => rf1_mc_dep_chk_val_q); +rf1_need_hole_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf1_need_hole_offset), + scout => sov(rf1_need_hole_offset), + din => rf0_need_hole_q , + dout => rf1_need_hole_q); +rf1_opcode_is_31_latch : tri_regk + generic map (width => rf1_opcode_is_31_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rf1_opcode_is_31_d, + dout => rf1_opcode_is_31_q); +rf1_pred_taken_cnt_latch : tri_regk + generic map (width => rf1_pred_taken_cnt_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => fxa_fxb_rf0_pred_taken_cnt , + dout => rf1_pred_taken_cnt_q); +rf1_pred_update_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => fxa_fxb_rf0_pred_update , + dout(0) => rf1_pred_update_q); +rf1_s1_latch : tri_regk + generic map (width => rf1_s1_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => fxa_fxb_rf0_s1 , + dout => rf1_s1_q); +rf1_s1_vld_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => fxa_fxb_rf0_s1_vld , + dout(0) => rf1_s1_vld_q); +rf1_s2_latch : tri_regk + generic map (width => rf1_s2_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => fxa_fxb_rf0_s2 , + dout => rf1_s2_q); +rf1_s2_vld_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => fxa_fxb_rf0_s2_vld , + dout(0) => rf1_s2_vld_q); +rf1_s3_latch : tri_regk + generic map (width => rf1_s3_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => fxa_fxb_rf0_s3 , + dout => rf1_s3_q); +rf1_s3_vld_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => fxa_fxb_rf0_s3_vld , + dout(0) => rf1_s3_vld_q); +rf1_ta_latch : tri_regk + generic map (width => rf1_ta_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => fxa_fxb_rf0_ta , + dout => rf1_ta_q); +rf1_ta_vld_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf1_ta_vld_offset), + scout => sov(rf1_ta_vld_offset), + din => fxa_fxb_rf0_ta_vld , + dout => rf1_ta_vld_q); +rf1_tid_latch : tri_regk + generic map (width => rf1_tid_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => fxa_fxb_rf0_tid , + dout => rf1_tid_q); +rf1_tid_2_latch : tri_regk + generic map (width => rf1_tid_2_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => fxa_fxb_rf0_tid , + dout => rf1_tid_2_q); +rf1_ucode_val_latch : tri_rlmreg_p + generic map (width => rf1_ucode_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf1_ucode_val_offset to rf1_ucode_val_offset + rf1_ucode_val_q'length-1), + scout => sov(rf1_ucode_val_offset to rf1_ucode_val_offset + rf1_ucode_val_q'length-1), + din => fxa_fxb_rf0_ucode_val , + dout => rf1_ucode_val_q); +rf1_use_imm_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => fxa_fxb_rf0_use_imm , + dout(0) => rf1_use_imm_q); +rf1_val_latch : tri_rlmreg_p + generic map (width => rf1_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf1_val_offset to rf1_val_offset + rf1_val_q'length-1), + scout => sov(rf1_val_offset to rf1_val_offset + rf1_val_q'length-1), + din => fxa_fxb_rf0_val , + dout => rf1_val_q); +rf1_val_iu_latch : tri_rlmreg_p + generic map (width => rf1_val_iu_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf1_val_iu_offset to rf1_val_iu_offset + rf1_val_iu_q'length-1), + scout => sov(rf1_val_iu_offset to rf1_val_iu_offset + rf1_val_iu_q'length-1), + din => fxa_fxb_rf0_val , + dout => rf1_val_iu_q); +rf1_xu_epid_instr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => fxa_fxb_rf0_xu_epid_instr , + dout(0) => rf1_xu_epid_instr_q); +ex1_act_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_act_offset), + scout => sov(ex1_act_offset), + din => ex1_act_d, + dout => ex1_act_q); +ex1_axu_instr_type_latch : tri_rlmreg_p + generic map (width => ex1_axu_instr_type_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_axu_instr_type_offset to ex1_axu_instr_type_offset + ex1_axu_instr_type_q'length-1), + scout => sov(ex1_axu_instr_type_offset to ex1_axu_instr_type_offset + ex1_axu_instr_type_q'length-1), + din => ex1_axu_instr_type_d, + dout => ex1_axu_instr_type_q); +ex1_axu_movedp_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_axu_movedp_offset), + scout => sov(ex1_axu_movedp_offset), + din => rf1_axu_movedp_q , + dout => ex1_axu_movedp_q); +ex1_back_inv_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_back_inv_offset), + scout => sov(ex1_back_inv_offset), + din => rf1_back_inv_q , + dout => ex1_back_inv_q); +ex1_bh_latch : tri_rlmreg_p + generic map (width => ex1_bh_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_bh_offset to ex1_bh_offset + ex1_bh_q'length-1), + scout => sov(ex1_bh_offset to ex1_bh_offset + ex1_bh_q'length-1), + din => rf1_bh , + dout => ex1_bh_q); +ex1_clear_barrier_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_clear_barrier_offset), + scout => sov(ex1_clear_barrier_offset), + din => rf1_clear_barrier , + dout => ex1_clear_barrier_q); +ex1_ddmh_en_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_ddmh_en_offset), + scout => sov(ex1_ddmh_en_offset), + din => ex1_ddmh_en_d, + dout => ex1_ddmh_en_q); +ex1_ditc_illeg_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_ditc_illeg_offset), + scout => sov(ex1_ditc_illeg_offset), + din => ex1_ditc_illeg_d, + dout => ex1_ditc_illeg_q); +ex1_dp_indexed_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_dp_indexed_offset), + scout => sov(ex1_dp_indexed_offset), + din => ex1_dp_indexed_d, + dout => ex1_dp_indexed_q); +ex1_epid_instr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_epid_instr_offset), + scout => sov(ex1_epid_instr_offset), + din => ex1_epid_instr_d, + dout => ex1_epid_instr_q); +ex1_error_latch : tri_rlmreg_p + generic map (width => ex1_error_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_error_offset to ex1_error_offset + ex1_error_q'length-1), + scout => sov(ex1_error_offset to ex1_error_offset + ex1_error_q'length-1), + din => rf1_error_q , + dout => ex1_error_q); +ex1_getNIA_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_getNIA_offset), + scout => sov(ex1_getNIA_offset), + din => rf1_getNIA , + dout => ex1_getNIA_q); +ex1_gpr_we_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_gpr_we_offset), + scout => sov(ex1_gpr_we_offset), + din => ex1_gpr_we_d, + dout => ex1_gpr_we_q); +ex1_gshare_latch : tri_rlmreg_p + generic map (width => ex1_gshare_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_gshare_offset to ex1_gshare_offset + ex1_gshare_q'length-1), + scout => sov(ex1_gshare_offset to ex1_gshare_offset + ex1_gshare_q'length-1), + din => rf1_gshare_q , + dout => ex1_gshare_q); +ex1_instr_latch : tri_rlmreg_p + generic map (width => ex1_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_instr_offset to ex1_instr_offset + ex1_instr_q'length-1), + scout => sov(ex1_instr_offset to ex1_instr_offset + ex1_instr_q'length-1), + din => rf1_instr_q(11 to 25), + dout => ex1_instr_q); +ex1_instr_hypv_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_instr_hypv_offset), + scout => sov(ex1_instr_hypv_offset), + din => rf1_instr_hypv , + dout => ex1_instr_hypv_q); +ex1_instr_priv_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_instr_priv_offset), + scout => sov(ex1_instr_priv_offset), + din => rf1_instr_priv , + dout => ex1_instr_priv_q); +ex1_is_any_load_dac_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_any_load_dac_offset), + scout => sov(ex1_is_any_load_dac_offset), + din => rf1_is_any_load_dac , + dout => ex1_is_any_load_dac_q); +ex1_is_any_store_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_any_store_offset), + scout => sov(ex1_is_any_store_offset), + din => rf1_is_any_store , + dout => ex1_is_any_store_q); +ex1_is_any_store_dac_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_any_store_dac_offset), + scout => sov(ex1_is_any_store_dac_offset), + din => rf1_is_any_store_dac , + dout => ex1_is_any_store_dac_q); +ex1_is_attn_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_attn_offset), + scout => sov(ex1_is_attn_offset), + din => rf1_is_attn , + dout => ex1_is_attn_q); +ex1_is_bclr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_bclr_offset), + scout => sov(ex1_is_bclr_offset), + din => rf1_is_bclr , + dout => ex1_is_bclr_q); +ex1_is_cmp_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_cmp_offset), + scout => sov(ex1_is_cmp_offset), + din => rf1_cmp , + dout => ex1_is_cmp_q); +ex1_is_csync_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_csync_offset), + scout => sov(ex1_is_csync_offset), + din => rf1_is_csync, + dout => ex1_is_csync_q); +ex1_is_eratsxr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_eratsxr_offset), + scout => sov(ex1_is_eratsxr_offset), + din => rf1_is_eratsxr , + dout => ex1_is_eratsxr_q); +ex1_is_icswx_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_icswx_offset), + scout => sov(ex1_is_icswx_offset), + din => ex1_is_icswx_d, + dout => ex1_is_icswx_q); +ex1_is_isync_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_isync_offset), + scout => sov(ex1_is_isync_offset), + din => rf1_is_isync , + dout => ex1_is_isync_q); +ex1_is_ld_w_update_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_ld_w_update_offset), + scout => sov(ex1_is_ld_w_update_offset), + din => rf1_is_ld_w_update , + dout => ex1_is_ld_w_update_q); +ex1_is_lmw_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_lmw_offset), + scout => sov(ex1_is_lmw_offset), + din => rf1_is_lmw , + dout => ex1_is_lmw_q); +ex1_is_lswi_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_lswi_offset), + scout => sov(ex1_is_lswi_offset), + din => rf1_is_lswi , + dout => ex1_is_lswi_q); +ex1_is_lswx_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_lswx_offset), + scout => sov(ex1_is_lswx_offset), + din => rf1_is_lswx , + dout => ex1_is_lswx_q); +ex1_is_mfcr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_mfcr_offset), + scout => sov(ex1_is_mfcr_offset), + din => rf1_is_mfcr , + dout => ex1_is_mfcr_q); +ex1_is_mfspr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_mfspr_offset), + scout => sov(ex1_is_mfspr_offset), + din => rf1_is_mfspr , + dout => ex1_is_mfspr_q); +ex1_is_msgclr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_msgclr_offset), + scout => sov(ex1_is_msgclr_offset), + din => rf1_is_msgclr , + dout => ex1_is_msgclr_q); +ex1_is_msgsnd_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_msgsnd_offset), + scout => sov(ex1_is_msgsnd_offset), + din => rf1_is_msgsnd , + dout => ex1_is_msgsnd_q); +ex1_is_mtspr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_mtspr_offset), + scout => sov(ex1_is_mtspr_offset), + din => rf1_is_mtspr , + dout => ex1_is_mtspr_q); +ex1_is_sc_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_sc_offset), + scout => sov(ex1_is_sc_offset), + din => rf1_is_sc , + dout => ex1_is_sc_q); +ex1_is_st_w_update_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_st_w_update_offset), + scout => sov(ex1_is_st_w_update_offset), + din => rf1_is_st_w_update , + dout => ex1_is_st_w_update_q); +ex1_is_ucode_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_ucode_offset), + scout => sov(ex1_is_ucode_offset), + din => rf1_is_ucode_q , + dout => ex1_is_ucode_q); +ex1_is_wchkall_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_wchkall_offset), + scout => sov(ex1_is_wchkall_offset), + din => rf1_is_wchkall , + dout => ex1_is_wchkall_q); +ex1_lk_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_lk_offset), + scout => sov(ex1_lk_offset), + din => rf1_lk , + dout => ex1_lk_q); +ex1_match_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_match_offset), + scout => sov(ex1_match_offset), + din => rf1_match_q , + dout => ex1_match_q); +ex1_mfdcr_instr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_mfdcr_instr_offset), + scout => sov(ex1_mfdcr_instr_offset), + din => rf1_mfdcr_instr, + dout => ex1_mfdcr_instr_q); +ex1_mfdp_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_mfdp_val_offset), + scout => sov(ex1_mfdp_val_offset), + din => ex1_mfdp_val_d, + dout => ex1_mfdp_val_q); +ex1_mtdcr_instr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_mtdcr_instr_offset), + scout => sov(ex1_mtdcr_instr_offset), + din => rf1_mtdcr_instr, + dout => ex1_mtdcr_instr_q); +ex1_mtdp_nr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_mtdp_nr_offset), + scout => sov(ex1_mtdp_nr_offset), + din => ex1_mtdp_nr_d, + dout => ex1_mtdp_nr_q); +ex1_mtdp_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_mtdp_val_offset), + scout => sov(ex1_mtdp_val_offset), + din => ex1_mtdp_val_d, + dout => ex1_mtdp_val_q); +ex1_muldiv_coll_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_muldiv_coll_offset), + scout => sov(ex1_muldiv_coll_offset), + din => fxa_fxb_rf1_muldiv_coll , + dout => ex1_muldiv_coll_q); +ex1_need_hole_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_need_hole_offset), + scout => sov(ex1_need_hole_offset), + din => rf1_need_hole_q , + dout => ex1_need_hole_q); +ex1_num_regs_latch : tri_rlmreg_p + generic map (width => ex1_num_regs_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_num_regs_offset to ex1_num_regs_offset + ex1_num_regs_q'length-1), + scout => sov(ex1_num_regs_offset to ex1_num_regs_offset + ex1_num_regs_q'length-1), + din => ex1_num_regs_d, + dout => ex1_num_regs_q); +ex1_ovr_rotsel_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_ovr_rotsel_offset), + scout => sov(ex1_ovr_rotsel_offset), + din => ex1_ovr_rotsel_d, + dout => ex1_ovr_rotsel_q); +ex1_pred_taken_cnt_latch : tri_rlmreg_p + generic map (width => ex1_pred_taken_cnt_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_pred_taken_cnt_offset to ex1_pred_taken_cnt_offset + ex1_pred_taken_cnt_q'length-1), + scout => sov(ex1_pred_taken_cnt_offset to ex1_pred_taken_cnt_offset + ex1_pred_taken_cnt_q'length-1), + din => rf1_pred_taken_cnt_q , + dout => ex1_pred_taken_cnt_q); +ex1_pred_update_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_pred_update_offset), + scout => sov(ex1_pred_update_offset), + din => rf1_pred_update_q , + dout => ex1_pred_update_q); +ex1_pri_latch : tri_rlmreg_p + generic map (width => ex1_pri_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_pri_offset to ex1_pri_offset + ex1_pri_q'length-1), + scout => sov(ex1_pri_offset to ex1_pri_offset + ex1_pri_q'length-1), + din => rf1_pri , + dout => ex1_pri_q); +ex1_rotsel_ovrd_latch : tri_rlmreg_p + generic map (width => ex1_rotsel_ovrd_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_rotsel_ovrd_offset to ex1_rotsel_ovrd_offset + ex1_rotsel_ovrd_q'length-1), + scout => sov(ex1_rotsel_ovrd_offset to ex1_rotsel_ovrd_offset + ex1_rotsel_ovrd_q'length-1), + din => ex1_rotsel_ovrd_d, + dout => ex1_rotsel_ovrd_q); +ex1_s1_latch : tri_rlmreg_p + generic map (width => ex1_s1_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_s1_offset to ex1_s1_offset + ex1_s1_q'length-1), + scout => sov(ex1_s1_offset to ex1_s1_offset + ex1_s1_q'length-1), + din => rf1_s1_q , + dout => ex1_s1_q); +ex1_s2_latch : tri_rlmreg_p + generic map (width => ex1_s2_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_s2_offset to ex1_s2_offset + ex1_s2_q'length-1), + scout => sov(ex1_s2_offset to ex1_s2_offset + ex1_s2_q'length-1), + din => rf1_s2_q , + dout => ex1_s2_q); +ex1_s3_latch : tri_rlmreg_p + generic map (width => ex1_s3_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_s3_offset to ex1_s3_offset + ex1_s3_q'length-1), + scout => sov(ex1_s3_offset to ex1_s3_offset + ex1_s3_q'length-1), + din => rf1_s3_q , + dout => ex1_s3_q); +ex1_spr_sel_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_spr_sel_offset), + scout => sov(ex1_spr_sel_offset), + din => rf1_spr_sel , + dout => ex1_spr_sel_q); +ex1_ta_latch : tri_rlmreg_p + generic map (width => ex1_ta_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_ta_offset to ex1_ta_offset + ex1_ta_q'length-1), + scout => sov(ex1_ta_offset to ex1_ta_offset + ex1_ta_q'length-1), + din => rf1_ta_q , + dout => ex1_ta_q); +ex1_tid_latch : tri_rlmreg_p + generic map (width => ex1_tid_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_tid_offset to ex1_tid_offset + ex1_tid_q'length-1), + scout => sov(ex1_tid_offset to ex1_tid_offset + ex1_tid_q'length-1), + din => rf1_tid_q , + dout => ex1_tid_q); +ex1_tlb_data_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_tlb_data_val_offset), + scout => sov(ex1_tlb_data_val_offset), + din => ex1_tlb_data_val_d, + dout => ex1_tlb_data_val_q); +ex1_tlb_illeg_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_tlb_illeg_offset), + scout => sov(ex1_tlb_illeg_offset), + din => ex1_tlb_illeg_d, + dout => ex1_tlb_illeg_q); +ex1_trace_type_latch : tri_rlmreg_p + generic map (width => ex1_trace_type_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_trace_type_offset to ex1_trace_type_offset + ex1_trace_type_q'length-1), + scout => sov(ex1_trace_type_offset to ex1_trace_type_offset + ex1_trace_type_q'length-1), + din => rf1_trace_type, + dout => ex1_trace_type_q); +ex1_trace_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_trace_val_offset), + scout => sov(ex1_trace_val_offset), + din => rf1_trace_val, + dout => ex1_trace_val_q); +ex1_val_latch : tri_rlmreg_p + generic map (width => ex1_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_val_offset to ex1_val_offset + ex1_val_q'length-1), + scout => sov(ex1_val_offset to ex1_val_offset + ex1_val_q'length-1), + din => ex1_val_d, + dout => ex1_val_q); +ex1_axu_ld_or_st_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_axu_ld_or_st_offset), + scout => sov(ex1_axu_ld_or_st_offset), + din => rf1_axu_ld_or_st_q, + dout => ex1_axu_ld_or_st_q); +ex2_act_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_act_offset), + scout => sov(ex2_act_offset), + din => ex2_act_d, + dout => ex2_act_q); +ex2_axu_instr_type_latch : tri_regk + generic map (width => ex2_axu_instr_type_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex1_axu_instr_type_q , + dout => ex2_axu_instr_type_q); +ex2_back_inv_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_back_inv_offset), + scout => sov(ex2_back_inv_offset), + din => ex1_back_inv_q , + dout => ex2_back_inv_q); +ex2_bh_latch : tri_regk + generic map (width => ex2_bh_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex1_bh_q , + dout => ex2_bh_q); +ex2_clear_barrier_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_clear_barrier_offset), + scout => sov(ex2_clear_barrier_offset), + din => ex1_clear_barrier_q , + dout => ex2_clear_barrier_q); +ex2_ddmh_en_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_ddmh_en_q , + dout(0) => ex2_ddmh_en_q); +ex2_ditc_illeg_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_ditc_illeg_d, + dout(0) => ex2_ditc_illeg_q); +ex2_error_latch : tri_regk + generic map (width => ex2_error_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex1_error_q , + dout => ex2_error_q); +ex2_getNIA_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_getNIA_q , + dout(0) => ex2_getNIA_q); +ex2_gpr_we_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_gpr_we_offset), + scout => sov(ex2_gpr_we_offset), + din => ex2_gpr_we_d, + dout => ex2_gpr_we_q); +ex2_gshare_latch : tri_regk + generic map (width => ex2_gshare_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex1_gshare_q , + dout => ex2_gshare_q); +ex2_instr_latch : tri_regk + generic map (width => ex2_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex1_instr_q(12 to 25), + dout => ex2_instr_q); +ex2_instr_hypv_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_instr_hypv_q , + dout(0) => ex2_instr_hypv_q); +ex2_instr_priv_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_instr_priv_q , + dout(0) => ex2_instr_priv_q); +ex2_ipb_ba_latch : tri_rlmreg_p + generic map (width => ex2_ipb_ba_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_ipb_ba_offset to ex2_ipb_ba_offset + ex2_ipb_ba_q'length-1), + scout => sov(ex2_ipb_ba_offset to ex2_ipb_ba_offset + ex2_ipb_ba_q'length-1), + din => ex2_ipb_ba_d, + dout => ex2_ipb_ba_q); +ex2_ipb_sz_latch : tri_rlmreg_p + generic map (width => ex2_ipb_sz_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_ipb_sz_offset to ex2_ipb_sz_offset + ex2_ipb_sz_q'length-1), + scout => sov(ex2_ipb_sz_offset to ex2_ipb_sz_offset + ex2_ipb_sz_q'length-1), + din => ex2_ipb_sz_d, + dout => ex2_ipb_sz_q); +ex2_is_any_load_dac_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_any_load_dac_q , + dout(0) => ex2_is_any_load_dac_q); +ex2_is_any_store_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_any_store_q , + dout(0) => ex2_is_any_store_q); +ex2_is_any_store_dac_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_any_store_dac_q , + dout(0) => ex2_is_any_store_dac_q); +ex2_is_attn_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_attn_q , + dout(0) => ex2_is_attn_q); +ex2_is_bclr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_bclr_q , + dout(0) => ex2_is_bclr_q); +ex2_is_eratsxr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_eratsxr_q , + dout(0) => ex2_is_eratsxr_q); +ex2_is_icswx_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_icswx_q , + dout(0) => ex2_is_icswx_q); +ex2_is_ld_w_update_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_ld_w_update_q , + dout(0) => ex2_is_ld_w_update_q); +ex2_is_lmw_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_lmw_q , + dout(0) => ex2_is_lmw_q); +ex2_is_lswi_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_lswi_q , + dout(0) => ex2_is_lswi_q); +ex2_is_lswx_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_lswx_q , + dout(0) => ex2_is_lswx_q); +ex2_is_mfcr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_mfcr_q , + dout(0) => ex2_is_mfcr_q); +ex2_is_msgclr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_msgclr_q , + dout(0) => ex2_is_msgclr_q); +ex2_is_msgsnd_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_msgsnd_q , + dout(0) => ex2_is_msgsnd_q); +ex2_is_sc_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_sc_q , + dout(0) => ex2_is_sc_q); +ex2_is_st_w_update_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_st_w_update_q , + dout(0) => ex2_is_st_w_update_q); +ex2_is_ucode_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_is_ucode_offset), + scout => sov(ex2_is_ucode_offset), + din => ex1_is_ucode_q , + dout => ex2_is_ucode_q); +ex2_is_wchkall_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_wchkall_q , + dout(0) => ex2_is_wchkall_q); +ex2_lk_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_lk_q , + dout(0) => ex2_lk_q); +ex2_match_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_match_q , + dout(0) => ex2_match_q); +ex2_mfdp_val_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_mfdp_val_q , + dout(0) => ex2_mfdp_val_q); +ex2_mtdp_nr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_mtdp_nr_q , + dout(0) => ex2_mtdp_nr_q); +ex2_mtdp_val_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_mtdp_val_q , + dout(0) => ex2_mtdp_val_q); +ex2_muldiv_coll_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_muldiv_coll_offset), + scout => sov(ex2_muldiv_coll_offset), + din => ex1_muldiv_coll_q , + dout => ex2_muldiv_coll_q); +ex2_need_hole_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_need_hole_offset), + scout => sov(ex2_need_hole_offset), + din => ex1_need_hole_q , + dout => ex2_need_hole_q); +ex2_pred_taken_cnt_latch : tri_regk + generic map (width => ex2_pred_taken_cnt_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex1_pred_taken_cnt_q , + dout => ex2_pred_taken_cnt_q); +ex2_pred_update_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_pred_update_q , + dout(0) => ex2_pred_update_q); +ex2_pri_latch : tri_regk + generic map (width => ex2_pri_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex1_pri_q , + dout => ex2_pri_q); +ex2_ra_eq_rt_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_ra_eq_rt_d, + dout(0) => ex2_ra_eq_rt_q); +ex2_ra_eq_zero_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_ra_eq_zero_d, + dout(0) => ex2_ra_eq_zero_q); +ex2_ra_in_rng_lmw_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_ra_in_rng_lmw_d, + dout(0) => ex2_ra_in_rng_lmw_q); +ex2_ra_in_rng_nowrap_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_ra_in_rng_nowrap_d, + dout(0) => ex2_ra_in_rng_nowrap_q); +ex2_ra_in_rng_wrap_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_ra_in_rng_wrap_d, + dout(0) => ex2_ra_in_rng_wrap_q); +ex2_range_wrap_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_range_wrap_d, + dout(0) => ex2_range_wrap_q); +ex2_rb_eq_rt_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_rb_eq_rt_d, + dout(0) => ex2_rb_eq_rt_q); +ex2_rb_in_rng_nowrap_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_rb_in_rng_nowrap_d, + dout(0) => ex2_rb_in_rng_nowrap_q); +ex2_rb_in_rng_wrap_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_rb_in_rng_wrap_d, + dout(0) => ex2_rb_in_rng_wrap_q); +ex2_slowspr_dcr_rd_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_slowspr_dcr_rd, + dout(0) => ex2_slowspr_dcr_rd_q); +ex2_ta_latch : tri_regk + generic map (width => ex2_ta_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex1_ta_q , + dout => ex2_ta_q); +ex2_tid_latch : tri_regk + generic map (width => ex2_tid_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex1_tid_q , + dout => ex2_tid_q); +ex2_tlb_data_val_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_tlb_data_val_q , + dout(0) => ex2_tlb_data_val_q); +ex2_tlb_illeg_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_tlb_illeg_q , + dout(0) => ex2_tlb_illeg_q); +ex2_trace_type_latch : tri_regk + generic map (width => ex2_trace_type_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex1_trace_type_q , + dout => ex2_trace_type_q); +ex2_trace_val_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_trace_val_q , + dout(0) => ex2_trace_val_q); +ex2_val_latch : tri_rlmreg_p + generic map (width => ex2_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_val_offset to ex2_val_offset + ex2_val_q'length-1), + scout => sov(ex2_val_offset to ex2_val_offset + ex2_val_q'length-1), + din => ex2_val_d, + dout => ex2_val_q); +ex3_act_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_act_offset), + scout => sov(ex3_act_offset), + din => ex3_act_d, + dout => ex3_act_q); +ex3_axu_instr_type_latch : tri_rlmreg_p + generic map (width => ex3_axu_instr_type_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_axu_instr_type_offset to ex3_axu_instr_type_offset + ex3_axu_instr_type_q'length-1), + scout => sov(ex3_axu_instr_type_offset to ex3_axu_instr_type_offset + ex3_axu_instr_type_q'length-1), + din => ex2_axu_instr_type_q , + dout => ex3_axu_instr_type_q); +ex3_back_inv_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_back_inv_offset), + scout => sov(ex3_back_inv_offset), + din => ex2_back_inv_q , + dout => ex3_back_inv_q); +ex3_bh_latch : tri_rlmreg_p + generic map (width => ex3_bh_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_bh_offset to ex3_bh_offset + ex3_bh_q'length-1), + scout => sov(ex3_bh_offset to ex3_bh_offset + ex3_bh_q'length-1), + din => ex2_bh_q , + dout => ex3_bh_q); +ex3_clear_barrier_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_clear_barrier_offset), + scout => sov(ex3_clear_barrier_offset), + din => ex2_clear_barrier_q , + dout => ex3_clear_barrier_q); +ex3_ddmh_en_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_ddmh_en_offset), + scout => sov(ex3_ddmh_en_offset), + din => ex2_ddmh_en_q , + dout => ex3_ddmh_en_q); +ex3_div_done_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_div_done_offset), + scout => sov(ex3_div_done_offset), + din => alu_ex2_div_done , + dout => ex3_div_done_q); +ex3_getNIA_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_getNIA_offset), + scout => sov(ex3_getNIA_offset), + din => ex2_getNIA_q , + dout => ex3_getNIA_q); +ex3_gpr_we_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_gpr_we_offset), + scout => sov(ex3_gpr_we_offset), + din => ex2_gpr_we_q , + dout => ex3_gpr_we_q); +ex3_gshare_latch : tri_rlmreg_p + generic map (width => ex3_gshare_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_gshare_offset to ex3_gshare_offset + ex3_gshare_q'length-1), + scout => sov(ex3_gshare_offset to ex3_gshare_offset + ex3_gshare_q'length-1), + din => ex2_gshare_q , + dout => ex3_gshare_q); +ex3_instr_latch : tri_rlmreg_p + generic map (width => ex3_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_instr_offset to ex3_instr_offset + ex3_instr_q'length-1), + scout => sov(ex3_instr_offset to ex3_instr_offset + ex3_instr_q'length-1), + din => ex2_instr_q(12 to 19), + dout => ex3_instr_q); +ex3_instr_hypv_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_instr_hypv_offset), + scout => sov(ex3_instr_hypv_offset), + din => ex2_instr_hypv_q , + dout => ex3_instr_hypv_q); +ex3_instr_priv_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_instr_priv_offset), + scout => sov(ex3_instr_priv_offset), + din => ex2_instr_priv_q , + dout => ex3_instr_priv_q); +ex3_is_any_store_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_any_store_offset), + scout => sov(ex3_is_any_store_offset), + din => ex2_is_any_store_q , + dout => ex3_is_any_store_q); +ex3_is_bclr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_bclr_offset), + scout => sov(ex3_is_bclr_offset), + din => ex2_is_bclr_q , + dout => ex3_is_bclr_q); +ex3_is_eratsxr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_eratsxr_offset), + scout => sov(ex3_is_eratsxr_offset), + din => ex2_is_eratsxr_q , + dout => ex3_is_eratsxr_q); +ex3_is_mfcr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_mfcr_offset), + scout => sov(ex3_is_mfcr_offset), + din => ex2_is_mfcr_q , + dout => ex3_is_mfcr_q); +ex3_is_wchkall_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_wchkall_offset), + scout => sov(ex3_is_wchkall_offset), + din => ex2_is_wchkall_q , + dout => ex3_is_wchkall_q); +ex3_lk_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_lk_offset), + scout => sov(ex3_lk_offset), + din => ex2_lk_q , + dout => ex3_lk_q); +ex3_mfdp_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_mfdp_val_offset), + scout => sov(ex3_mfdp_val_offset), + din => ex2_mfdp_val_q , + dout => ex3_mfdp_val_q); +ex3_mtdp_nr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_mtdp_nr_offset), + scout => sov(ex3_mtdp_nr_offset), + din => ex2_mtdp_nr_q , + dout => ex3_mtdp_nr_q); +ex3_mtdp_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_mtdp_val_offset), + scout => sov(ex3_mtdp_val_offset), + din => ex2_mtdp_val_q , + dout => ex3_mtdp_val_q); +ex3_muldiv_coll_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_muldiv_coll_offset), + scout => sov(ex3_muldiv_coll_offset), + din => ex2_muldiv_coll_q , + dout => ex3_muldiv_coll_q); +ex3_need_hole_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_need_hole_offset), + scout => sov(ex3_need_hole_offset), + din => ex2_need_hole_q , + dout => ex3_need_hole_q); +ex3_pred_taken_cnt_latch : tri_rlmreg_p + generic map (width => ex3_pred_taken_cnt_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_pred_taken_cnt_offset to ex3_pred_taken_cnt_offset + ex3_pred_taken_cnt_q'length-1), + scout => sov(ex3_pred_taken_cnt_offset to ex3_pred_taken_cnt_offset + ex3_pred_taken_cnt_q'length-1), + din => ex2_pred_taken_cnt_q , + dout => ex3_pred_taken_cnt_q); +ex3_pred_update_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_pred_update_offset), + scout => sov(ex3_pred_update_offset), + din => ex2_pred_update_q , + dout => ex3_pred_update_q); +ex3_pri_latch : tri_rlmreg_p + generic map (width => ex3_pri_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_pri_offset to ex3_pri_offset + ex3_pri_q'length-1), + scout => sov(ex3_pri_offset to ex3_pri_offset + ex3_pri_q'length-1), + din => ex2_pri_q , + dout => ex3_pri_q); +ex3_slowspr_dcr_rd_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_slowspr_dcr_rd_offset), + scout => sov(ex3_slowspr_dcr_rd_offset), + din => ex2_slowspr_dcr_rd_q , + dout => ex3_slowspr_dcr_rd_q); +ex3_ta_latch : tri_rlmreg_p + generic map (width => ex3_ta_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_ta_offset to ex3_ta_offset + ex3_ta_q'length-1), + scout => sov(ex3_ta_offset to ex3_ta_offset + ex3_ta_q'length-1), + din => ex2_ta_q , + dout => ex3_ta_q); +ex3_tid_latch : tri_rlmreg_p + generic map (width => ex3_tid_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_tid_offset to ex3_tid_offset + ex3_tid_q'length-1), + scout => sov(ex3_tid_offset to ex3_tid_offset + ex3_tid_q'length-1), + din => ex2_tid_q , + dout => ex3_tid_q); +ex3_tlb_data_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_tlb_data_val_offset), + scout => sov(ex3_tlb_data_val_offset), + din => ex2_tlb_data_val_q , + dout => ex3_tlb_data_val_q); +ex3_tlb_illeg_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_tlb_illeg_offset), + scout => sov(ex3_tlb_illeg_offset), + din => ex2_tlb_illeg_q , + dout => ex3_tlb_illeg_q); +ex3_trace_type_latch : tri_rlmreg_p + generic map (width => ex3_trace_type_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_trace_type_offset to ex3_trace_type_offset + ex3_trace_type_q'length-1), + scout => sov(ex3_trace_type_offset to ex3_trace_type_offset + ex3_trace_type_q'length-1), + din => ex2_trace_type_q, + dout => ex3_trace_type_q); +ex3_trace_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_trace_val_offset), + scout => sov(ex3_trace_val_offset), + din => ex2_trace_val_q , + dout => ex3_trace_val_q); +ex3_val_latch : tri_rlmreg_p + generic map (width => ex3_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_val_offset to ex3_val_offset + ex3_val_q'length-1), + scout => sov(ex3_val_offset to ex3_val_offset + ex3_val_q'length-1), + din => ex3_val_d, + dout => ex3_val_q); +ex4_act_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_act_offset), + scout => sov(ex4_act_offset), + din => ex4_act_d, + dout => ex4_act_q); +ex4_bh_latch : tri_regk + generic map (width => ex4_bh_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex3_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex3_bh_q , + dout => ex4_bh_q); +ex4_clear_barrier_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_clear_barrier_offset), + scout => sov(ex4_clear_barrier_offset), + din => ex3_clear_barrier_q , + dout => ex4_clear_barrier_q); +ex4_dp_instr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex3_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex4_dp_instr_d, + dout(0) => ex4_dp_instr_q); +ex4_getNIA_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex3_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_getNIA_q , + dout(0) => ex4_getNIA_q); +ex4_gpr_we_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_gpr_we_offset), + scout => sov(ex4_gpr_we_offset), + din => ex4_gpr_we_d, + dout => ex4_gpr_we_q); +ex4_gshare_latch : tri_regk + generic map (width => ex4_gshare_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex3_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex3_gshare_q , + dout => ex4_gshare_q); +ex4_instr_latch : tri_regk + generic map (width => ex4_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex3_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex3_instr_q , + dout => ex4_instr_q); +ex4_is_bclr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex3_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_is_bclr_q , + dout(0) => ex4_is_bclr_q); +ex4_is_eratsxr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex3_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_is_eratsxr_q , + dout(0) => ex4_is_eratsxr_q); +ex4_is_mfcr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex3_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_is_mfcr_q , + dout(0) => ex4_is_mfcr_q); +ex4_is_wchkall_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex3_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_is_wchkall_q , + dout(0) => ex4_is_wchkall_q); +ex4_lk_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex3_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_lk_q , + dout(0) => ex4_lk_q); +ex4_mfdp_val_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex3_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_mfdp_val_q , + dout(0) => ex4_mfdp_val_q); +ex4_mtdp_val_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex3_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_mtdp_val_q , + dout(0) => ex4_mtdp_val_q); +ex4_pred_taken_cnt_latch : tri_regk + generic map (width => ex4_pred_taken_cnt_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex3_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex3_pred_taken_cnt_q , + dout => ex4_pred_taken_cnt_q); +ex4_pred_update_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex3_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_pred_update_q , + dout(0) => ex4_pred_update_q); +ex4_pri_latch : tri_regk + generic map (width => ex4_pri_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex3_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex3_pri_q , + dout => ex4_pri_q); +ex4_slowspr_dcr_rd_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex3_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_slowspr_dcr_rd_q , + dout(0) => ex4_slowspr_dcr_rd_q); +ex4_ta_latch : tri_regk + generic map (width => ex4_ta_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex3_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex3_ta_q , + dout => ex4_ta_q); +ex4_tid_latch : tri_regk + generic map (width => ex4_tid_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex3_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex3_tid_q , + dout => ex4_tid_q); +ex4_val_latch : tri_rlmreg_p + generic map (width => ex4_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_val_offset to ex4_val_offset + ex4_val_q'length-1), + scout => sov(ex4_val_offset to ex4_val_offset + ex4_val_q'length-1), + din => ex4_val_d, + dout => ex4_val_q); +ex5_act_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_act_offset), + scout => sov(ex5_act_offset), + din => ex5_act_d, + dout => ex5_act_q); +ex5_bh_latch : tri_rlmreg_p + generic map (width => ex5_bh_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_bh_offset to ex5_bh_offset + ex5_bh_q'length-1), + scout => sov(ex5_bh_offset to ex5_bh_offset + ex5_bh_q'length-1), + din => ex4_bh_q , + dout => ex5_bh_q); +ex5_clear_barrier_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_clear_barrier_offset), + scout => sov(ex5_clear_barrier_offset), + din => ex4_clear_barrier_q , + dout => ex5_clear_barrier_q); +ex5_getNIA_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_getNIA_offset), + scout => sov(ex5_getNIA_offset), + din => ex4_getNIA_q , + dout => ex5_getNIA_q); +ex5_gpr_we_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_gpr_we_offset), + scout => sov(ex5_gpr_we_offset), + din => ex5_gpr_we_d, + dout => ex5_gpr_we_q); +ex5_gshare_latch : tri_rlmreg_p + generic map (width => ex5_gshare_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_gshare_offset to ex5_gshare_offset + ex5_gshare_q'length-1), + scout => sov(ex5_gshare_offset to ex5_gshare_offset + ex5_gshare_q'length-1), + din => ex4_gshare_q , + dout => ex5_gshare_q); +ex5_instr_latch : tri_rlmreg_p + generic map (width => ex5_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_instr_offset to ex5_instr_offset + ex5_instr_q'length-1), + scout => sov(ex5_instr_offset to ex5_instr_offset + ex5_instr_q'length-1), + din => ex4_instr_q , + dout => ex5_instr_q); +ex5_is_bclr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_is_bclr_offset), + scout => sov(ex5_is_bclr_offset), + din => ex4_is_bclr_q , + dout => ex5_is_bclr_q); +ex5_lk_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_lk_offset), + scout => sov(ex5_lk_offset), + din => ex4_lk_q , + dout => ex5_lk_q); +ex5_pred_taken_cnt_latch : tri_rlmreg_p + generic map (width => ex5_pred_taken_cnt_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_pred_taken_cnt_offset to ex5_pred_taken_cnt_offset + ex5_pred_taken_cnt_q'length-1), + scout => sov(ex5_pred_taken_cnt_offset to ex5_pred_taken_cnt_offset + ex5_pred_taken_cnt_q'length-1), + din => ex4_pred_taken_cnt_q , + dout => ex5_pred_taken_cnt_q); +ex5_pred_update_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_pred_update_offset), + scout => sov(ex5_pred_update_offset), + din => ex4_pred_update_q , + dout => ex5_pred_update_q); +ex5_pri_latch : tri_rlmreg_p + generic map (width => ex5_pri_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_pri_offset to ex5_pri_offset + ex5_pri_q'length-1), + scout => sov(ex5_pri_offset to ex5_pri_offset + ex5_pri_q'length-1), + din => ex4_pri_q , + dout => ex5_pri_q); +ex5_slowspr_dcr_rd_latch : tri_rlmreg_p + generic map (width => ex5_slowspr_dcr_rd_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_slowspr_dcr_rd_offset to ex5_slowspr_dcr_rd_offset + ex5_slowspr_dcr_rd_q'length-1), + scout => sov(ex5_slowspr_dcr_rd_offset to ex5_slowspr_dcr_rd_offset + ex5_slowspr_dcr_rd_q'length-1), + din => ex5_slowspr_dcr_rd_d, + dout => ex5_slowspr_dcr_rd_q); +ex5_ta_latch : tri_rlmreg_p + generic map (width => ex5_ta_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_ta_offset to ex5_ta_offset + ex5_ta_q'length-1), + scout => sov(ex5_ta_offset to ex5_ta_offset + ex5_ta_q'length-1), + din => ex4_ta_q , + dout => ex5_ta_q); +ex5_tid_latch : tri_rlmreg_p + generic map (width => ex5_tid_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_tid_offset to ex5_tid_offset + ex5_tid_q'length-1), + scout => sov(ex5_tid_offset to ex5_tid_offset + ex5_tid_q'length-1), + din => ex4_tid_q , + dout => ex5_tid_q); +ex5_val_latch : tri_rlmreg_p + generic map (width => ex5_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_val_offset to ex5_val_offset + ex5_val_q'length-1), + scout => sov(ex5_val_offset to ex5_val_offset + ex5_val_q'length-1), + din => ex5_val_d, + dout => ex5_val_q); +ex6_clear_barrier_latch : tri_rlmreg_p + generic map (width => ex6_clear_barrier_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_clear_barrier_offset to ex6_clear_barrier_offset + ex6_clear_barrier_q'length-1), + scout => sov(ex6_clear_barrier_offset to ex6_clear_barrier_offset + ex6_clear_barrier_q'length-1), + din => ex6_clear_barrier_d, + dout => ex6_clear_barrier_q); +ex6_gpr_we_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_gpr_we_offset), + scout => sov(ex6_gpr_we_offset), + din => ex6_gpr_we_d, + dout => ex6_gpr_we_q); +ex6_pri_latch : tri_rlmreg_p + generic map (width => ex6_pri_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex5_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_pri_offset to ex6_pri_offset + ex6_pri_q'length-1), + scout => sov(ex6_pri_offset to ex6_pri_offset + ex6_pri_q'length-1), + din => ex5_pri_q , + dout => ex6_pri_q); +ex6_ta_latch : tri_rlmreg_p + generic map (width => ex6_ta_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_ta_offset to ex6_ta_offset + ex6_ta_q'length-1), + scout => sov(ex6_ta_offset to ex6_ta_offset + ex6_ta_q'length-1), + din => ex6_ta_d, + dout => ex6_ta_q); +ex6_val_latch : tri_rlmreg_p + generic map (width => ex6_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_val_offset to ex6_val_offset + ex6_val_q'length-1), + scout => sov(ex6_val_offset to ex6_val_offset + ex6_val_q'length-1), + din => ex6_val_d, + dout => ex6_val_q); +ex7_gpr_we_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex7_gpr_we_offset), + scout => sov(ex7_gpr_we_offset), + din => ex6_gpr_we_q , + dout => ex7_gpr_we_q); +ex7_ta_latch : tri_rlmreg_p + generic map (width => ex7_ta_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex7_ta_offset to ex7_ta_offset + ex7_ta_q'length-1), + scout => sov(ex7_ta_offset to ex7_ta_offset + ex7_ta_q'length-1), + din => ex6_ta_q , + dout => ex7_ta_q); +ex7_val_latch : tri_rlmreg_p + generic map (width => ex7_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex7_val_offset to ex7_val_offset + ex7_val_q'length-1), + scout => sov(ex7_val_offset to ex7_val_offset + ex7_val_q'length-1), + din => ex6_val_q , + dout => ex7_val_q); +an_ac_dcr_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(an_ac_dcr_val_offset), + scout => sov(an_ac_dcr_val_offset), + din => an_ac_dcr_val , + dout => an_ac_dcr_val_q); +dcr_ack_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dcr_ack_offset), + scout => sov(dcr_ack_offset), + din => dcr_ack, + dout => dcr_ack_q); +dcr_act_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dcr_act_offset), + scout => sov(dcr_act_offset), + din => an_ac_dcr_act , + dout => dcr_act_q); +dcr_etid_latch : tri_rlmreg_p + generic map (width => dcr_etid_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => dcr_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dcr_etid_offset to dcr_etid_offset + dcr_etid_q'length-1), + scout => sov(dcr_etid_offset to dcr_etid_offset + dcr_etid_q'length-1), + din => an_ac_dcr_etid , + dout => dcr_etid_q); +dcr_read_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => dcr_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dcr_read_offset), + scout => sov(dcr_read_offset), + din => an_ac_dcr_read , + dout => dcr_read_q); +dcr_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dcr_val_offset), + scout => sov(dcr_val_offset), + din => dcr_val_d, + dout => dcr_val_q); +instr_trace_mode_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(instr_trace_mode_offset), + scout => sov(instr_trace_mode_offset), + din => pc_xu_instr_trace_mode , + dout => instr_trace_mode_q); +instr_trace_tid_latch : tri_rlmreg_p + generic map (width => instr_trace_tid_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(instr_trace_tid_offset to instr_trace_tid_offset + instr_trace_tid_q'length-1), + scout => sov(instr_trace_tid_offset to instr_trace_tid_offset + instr_trace_tid_q'length-1), + din => pc_xu_instr_trace_tid , + dout => instr_trace_tid_q); +lsu_xu_need_hole_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(lsu_xu_need_hole_offset), + scout => sov(lsu_xu_need_hole_offset), + din => lsu_xu_need_hole_d, + dout => lsu_xu_need_hole_q); +lsu_xu_rel_ta_gpr_latch : tri_rlmreg_p + generic map (width => lsu_xu_rel_ta_gpr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(lsu_xu_rel_ta_gpr_offset to lsu_xu_rel_ta_gpr_offset + lsu_xu_rel_ta_gpr_q'length-1), + scout => sov(lsu_xu_rel_ta_gpr_offset to lsu_xu_rel_ta_gpr_offset + lsu_xu_rel_ta_gpr_q'length-1), + din => lsu_xu_rel_ta_gpr , + dout => lsu_xu_rel_ta_gpr_q); +lsu_xu_rel_wren_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(lsu_xu_rel_wren_offset), + scout => sov(lsu_xu_rel_wren_offset), + din => lsu_xu_rel_wren , + dout => lsu_xu_rel_wren_q); +mmucr0_0_tlbsel_latch : tri_rlmreg_p + generic map (width => mmucr0_0_tlbsel_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(mmucr0_0_tlbsel_offset to mmucr0_0_tlbsel_offset + mmucr0_0_tlbsel_q'length-1), + scout => sov(mmucr0_0_tlbsel_offset to mmucr0_0_tlbsel_offset + mmucr0_0_tlbsel_q'length-1), + din => mm_xu_mmucr0_0_tlbsel , + dout => mmucr0_0_tlbsel_q); +mmucr0_1_tlbsel_latch : tri_rlmreg_p + generic map (width => mmucr0_1_tlbsel_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(mmucr0_1_tlbsel_offset to mmucr0_1_tlbsel_offset + mmucr0_1_tlbsel_q'length-1), + scout => sov(mmucr0_1_tlbsel_offset to mmucr0_1_tlbsel_offset + mmucr0_1_tlbsel_q'length-1), + din => mm_xu_mmucr0_1_tlbsel , + dout => mmucr0_1_tlbsel_q); +mmucr0_2_tlbsel_latch : tri_rlmreg_p + generic map (width => mmucr0_2_tlbsel_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(mmucr0_2_tlbsel_offset to mmucr0_2_tlbsel_offset + mmucr0_2_tlbsel_q'length-1), + scout => sov(mmucr0_2_tlbsel_offset to mmucr0_2_tlbsel_offset + mmucr0_2_tlbsel_q'length-1), + din => mm_xu_mmucr0_2_tlbsel , + dout => mmucr0_2_tlbsel_q); +mmucr0_3_tlbsel_latch : tri_rlmreg_p + generic map (width => mmucr0_3_tlbsel_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(mmucr0_3_tlbsel_offset to mmucr0_3_tlbsel_offset + mmucr0_3_tlbsel_q'length-1), + scout => sov(mmucr0_3_tlbsel_offset to mmucr0_3_tlbsel_offset + mmucr0_3_tlbsel_q'length-1), + din => mm_xu_mmucr0_3_tlbsel , + dout => mmucr0_3_tlbsel_q); +slowspr_etid_latch : tri_rlmreg_p + generic map (width => slowspr_etid_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => slowspr_val_in , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(slowspr_etid_offset to slowspr_etid_offset + slowspr_etid_q'length-1), + scout => sov(slowspr_etid_offset to slowspr_etid_offset + slowspr_etid_q'length-1), + din => slowspr_etid_in , + dout => slowspr_etid_q); +slowspr_rw_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => slowspr_val_in , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(slowspr_rw_offset), + scout => sov(slowspr_rw_offset), + din => slowspr_rw_in , + dout => slowspr_rw_q); +slowspr_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(slowspr_val_offset), + scout => sov(slowspr_val_offset), + din => slowspr_val_in , + dout => slowspr_val_q); +spr_ccr2_en_attn_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(spr_ccr2_en_attn_offset), + scout => sov(spr_ccr2_en_attn_offset), + din => spr_ccr2_en_attn , + dout => spr_ccr2_en_attn_q); +spr_ccr2_en_dcr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(spr_ccr2_en_dcr_offset), + scout => sov(spr_ccr2_en_dcr_offset), + din => spr_ccr2_en_dcr , + dout => spr_ccr2_en_dcr_q); +spr_ccr2_en_ditc_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(spr_ccr2_en_ditc_offset), + scout => sov(spr_ccr2_en_ditc_offset), + din => spr_ccr2_en_ditc , + dout => spr_ccr2_en_ditc_q); +spr_ccr2_en_icswx_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(spr_ccr2_en_icswx_offset), + scout => sov(spr_ccr2_en_icswx_offset), + din => spr_ccr2_en_icswx , + dout => spr_ccr2_en_icswx_q); +spr_ccr2_en_pc_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(spr_ccr2_en_pc_offset), + scout => sov(spr_ccr2_en_pc_offset), + din => spr_ccr2_en_pc , + dout => spr_ccr2_en_pc_q); +spr_ccr2_notlb_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(spr_ccr2_notlb_offset), + scout => sov(spr_ccr2_notlb_offset), + din => spr_ccr2_notlb , + dout => spr_ccr2_notlb_q); +spr_msr_cm_latch : tri_rlmreg_p + generic map (width => spr_msr_cm_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(spr_msr_cm_offset to spr_msr_cm_offset + spr_msr_cm_q'length-1), + scout => sov(spr_msr_cm_offset to spr_msr_cm_offset + spr_msr_cm_q'length-1), + din => spr_msr_cm , + dout => spr_msr_cm_q); +t0_hold_ta_latch : tri_rlmreg_p + generic map (width => t0_hold_ta_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex5_slowspr_dcr_rd_q(0), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(t0_hold_ta_offset to t0_hold_ta_offset + t0_hold_ta_q'length-1), + scout => sov(t0_hold_ta_offset to t0_hold_ta_offset + t0_hold_ta_q'length-1), + din => ex5_ta_q(0 to 5) , + dout => t0_hold_ta_q); +t1_hold_ta_latch : tri_rlmreg_p + generic map (width => t1_hold_ta_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex5_slowspr_dcr_rd_q(1), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(t1_hold_ta_offset to t1_hold_ta_offset + t1_hold_ta_q'length-1), + scout => sov(t1_hold_ta_offset to t1_hold_ta_offset + t1_hold_ta_q'length-1), + din => ex5_ta_q(0 to 5) , + dout => t1_hold_ta_q); +t2_hold_ta_latch : tri_rlmreg_p + generic map (width => t2_hold_ta_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex5_slowspr_dcr_rd_q(2), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(t2_hold_ta_offset to t2_hold_ta_offset + t2_hold_ta_q'length-1), + scout => sov(t2_hold_ta_offset to t2_hold_ta_offset + t2_hold_ta_q'length-1), + din => ex5_ta_q(0 to 5) , + dout => t2_hold_ta_q); +t3_hold_ta_latch : tri_rlmreg_p + generic map (width => t3_hold_ta_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex5_slowspr_dcr_rd_q(3), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(t3_hold_ta_offset to t3_hold_ta_offset + t3_hold_ta_q'length-1), + scout => sov(t3_hold_ta_offset to t3_hold_ta_offset + t3_hold_ta_q'length-1), + din => ex5_ta_q(0 to 5) , + dout => t3_hold_ta_q); +trace_bus_enable_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(trace_bus_enable_offset), + scout => sov(trace_bus_enable_offset), + din => pc_xu_trace_bus_enable , + dout => trace_bus_enable_q); +clkg_ctl_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(clkg_ctl_offset), + scout => sov(clkg_ctl_offset), + din => spr_xucr0_clkg_ctl(2), + dout => clkg_ctl_q); +spr_bit_act_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(spr_bit_act_offset), + scout => sov(spr_bit_act_offset), + din => spr_bit_act, + dout => spr_bit_act_q); +spare_0_lcb: entity tri.tri_lcbnd(tri_lcbnd) + port map(vd => vdd, + gd => gnd, + act => tidn, + nclk => nclk, + forcee => func_sl_force, + thold_b => func_sl_thold_0_b, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + sg => sg_0, + lclk => spare_0_lclk, + d1clk => spare_0_d1clk, + d2clk => spare_0_d2clk); +spare_0_latch : entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width => spare_0_q'length, expand_type => expand_type, btr => "NLI0001_X2_A12TH", init=>(spare_0_q'range=>'0')) + port map (vd => vdd, gd => gnd, + LCLK => spare_0_lclk, + D1CLK => spare_0_d1clk, + D2CLK => spare_0_d2clk, + SCANIN => siv(spare_0_offset to spare_0_offset + spare_0_q'length-1), + SCANOUT => sov(spare_0_offset to spare_0_offset + spare_0_q'length-1), + D => spare_0_d, + QB => spare_0_q); +spare_0_d <= not spare_0_q; +mark_unused(spare_0_q); +spare_1_lcb: entity tri.tri_lcbnd(tri_lcbnd) + port map(vd => vdd, + gd => gnd, + act => tidn, + nclk => nclk, + forcee => func_sl_force, + thold_b => func_sl_thold_0_b, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + sg => sg_0, + lclk => spare_1_lclk, + d1clk => spare_1_d1clk, + d2clk => spare_1_d2clk); +spare_1_latch : entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width => spare_1_q'length, expand_type => expand_type, btr => "NLI0001_X2_A12TH", init=>(spare_1_q'range=>'0')) + port map (vd => vdd, gd => gnd, + LCLK => spare_1_lclk, + D1CLK => spare_1_d1clk, + D2CLK => spare_1_d2clk, + SCANIN => siv(spare_1_offset to spare_1_offset + spare_1_q'length-1), + SCANOUT => sov(spare_1_offset to spare_1_offset + spare_1_q'length-1), + D => spare_1_d, + QB => spare_1_q); +spare_1_d <= not spare_1_q; +mark_unused(spare_1_q); +siv(0 TO siv'right) <= sov(1 to siv'right) & scan_in; +scan_out <= sov(0); +END XUQ_DEC_B; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_dec_dcdmrg.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_dec_dcdmrg.vhdl new file mode 100644 index 0000000..7c2033e --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_dec_dcdmrg.vhdl @@ -0,0 +1,469 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +LIBRARY work ; +LIBRARY ieee; USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY ibm; + USE ibm.std_ulogic_support.all; + USE ibm.std_ulogic_unsigned.all; + USE ibm.std_ulogic_function_support.all; +LIBRARY support; + USE support.power_logic_pkg.all; +LIBRARY tri; USE tri.tri_latches_pkg.all; +LIBRARY clib ; +LIBRARY work; USE work.xuq_pkg.all; + +entity xuq_dec_dcdmrg is + port ( + i : in std_ulogic_vector(0 to 31); + dec_alu_rf1_sel_rot_log : out std_ulogic; + dec_alu_rf1_sh_right : out std_ulogic; + dec_alu_rf1_sh_word : out std_ulogic; + dec_alu_rf1_sgnxtd_byte : out std_ulogic; + dec_alu_rf1_sgnxtd_half : out std_ulogic; + dec_alu_rf1_sgnxtd_wd : out std_ulogic; + dec_alu_rf1_sra_dw : out std_ulogic; + dec_alu_rf1_sra_wd : out std_ulogic; + dec_alu_rf1_chk_shov_dw : out std_ulogic; + dec_alu_rf1_chk_shov_wd : out std_ulogic; + + dec_alu_rf1_use_me_ins_hi : out std_ulogic; + dec_alu_rf1_use_me_ins_lo : out std_ulogic; + dec_alu_rf1_use_mb_ins_hi : out std_ulogic; + dec_alu_rf1_use_mb_ins_lo : out std_ulogic; + + dec_alu_rf1_use_me_rb_hi : out std_ulogic; + dec_alu_rf1_use_me_rb_lo : out std_ulogic; + dec_alu_rf1_use_mb_rb_hi : out std_ulogic; + dec_alu_rf1_use_mb_rb_lo : out std_ulogic; + + dec_alu_rf1_use_rb_amt_hi : out std_ulogic; + dec_alu_rf1_use_rb_amt_lo : out std_ulogic; + dec_alu_rf1_zm_ins : out std_ulogic; + dec_alu_rf1_cr_logical : out std_ulogic; + dec_alu_rf1_cr_log_fcn : out std_ulogic_vector(0 to 3); + dec_alu_rf1_log_fcn : out std_ulogic_vector(0 to 3); + dec_alu_rf1_me_ins_b : out std_ulogic_vector(0 to 5); + dec_alu_rf1_mb_ins : out std_ulogic_vector(0 to 5); + dec_alu_rf1_sh_amt : out std_ulogic_vector(0 to 5); + dec_alu_rf1_mb_gt_me : out std_ulogic + ); +-- synopsys translate_off +-- synopsys translate_on + +end xuq_dec_dcdmrg; + +architecture xuq_dec_dcdmrg of xuq_dec_dcdmrg is + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal cmp_byt : std_ulogic; + signal cr_log : std_ulogic; + signal rotlw : std_ulogic; + signal imm_log : std_ulogic; + signal rotld : std_ulogic; + signal x31 : std_ulogic; + signal f0_xxxx00 : std_ulogic; + signal f0_xxx0xx : std_ulogic; + signal f0_xxxx0x : std_ulogic; + signal f1_1xxxx : std_ulogic; + signal f1_111xx : std_ulogic; + signal f1_110xx : std_ulogic; + signal f1_x1x1x : std_ulogic; + signal f1_x1xx0 : std_ulogic; + signal f1_x1xx1 : std_ulogic; + signal f1_xxx00 : std_ulogic; + signal f1_xxx11 : std_ulogic; + signal f1_xx10x : std_ulogic; + signal f2_11xxx : std_ulogic; + signal f2_xxx0x : std_ulogic; + signal f2_111xx : std_ulogic; + signal f1_xxx01 : std_ulogic; + signal f1_xxx10 : std_ulogic; + signal f2_xx01x : std_ulogic; + signal f2_xx00x : std_ulogic; + signal rotlw_nm : std_ulogic; + signal rotlw_pass : std_ulogic; + signal rotld_pass : std_ulogic; + signal sh_lft_rb : std_ulogic; + signal sh_lft_rb_dw : std_ulogic; + signal sh_rgt : std_ulogic; + signal sh_rgt_rb : std_ulogic; + signal sh_rgt_rb_dw : std_ulogic; + signal shift_imm : std_ulogic; + signal sh_rb : std_ulogic; + signal sh_rb_dw : std_ulogic; + signal sh_rb_wd : std_ulogic; + signal x31_sh_log_sgn : std_ulogic; + signal op_sgn_xtd : std_ulogic; + signal op_sra : std_ulogic; + signal wd_if_sh : std_ulogic; + signal xtd_log : std_ulogic; + signal sh_word_int : std_ulogic; + signal imm_xor_or : std_ulogic; + signal imm_and_or : std_ulogic; + signal xtd_nor : std_ulogic; + signal xtd_eqv_orc_nand : std_ulogic; + signal xtd_nand : std_ulogic; + signal xtd_andc_xor_or : std_ulogic; + signal xtd_and_eqv_orc : std_ulogic; + signal xtd_or_orc : std_ulogic; + signal xtd_xor_or : std_ulogic; + signal sel_ins_amt_hi : std_ulogic; + signal sel_ins_me_lo_wd : std_ulogic; + signal sel_ins_me_lo_dw : std_ulogic; + signal sel_ins_amt_lo : std_ulogic; + signal sel_ins_me_hi : std_ulogic; + signal rot_imm_mb : std_ulogic; + signal gt5_g_45 : std_ulogic; + signal gt5_g_23 : std_ulogic; + signal gt5_g_1 : std_ulogic; + signal gt5_t_23 : std_ulogic; + signal gt5_t_1 : std_ulogic; + signal mb_gt_me_cmp_wd0_b : std_ulogic; + signal mb_gt_me_cmp_wd1_b : std_ulogic; + signal mb_gt_me_cmp_wd2_b : std_ulogic; + signal mb_gt_me_cmp_wd : std_ulogic; + signal gt6_g_45 : std_ulogic; + signal gt6_g_23 : std_ulogic; + signal gt6_g_01 : std_ulogic; + signal gt6_t_23 : std_ulogic; + signal gt6_t_01 : std_ulogic; + signal mb_gt_me_cmp_dw0_b : std_ulogic; + signal mb_gt_me_cmp_dw1_b : std_ulogic; + signal mb_gt_me_cmp_dw2_b : std_ulogic; + signal mb_gt_me_cmp_dw : std_ulogic; + signal me_ins : std_ulogic_vector(0 to 5); + signal gt5_in0 : std_ulogic_vector(1 to 5); + signal gt5_in1 : std_ulogic_vector(1 to 5); + signal gt6_in0 : std_ulogic_vector(0 to 5); + signal gt6_in1 : std_ulogic_vector(0 to 5); + signal gt5_g_b : std_ulogic_vector(1 to 5); + signal gt5_t_b : std_ulogic_vector(1 to 4); + signal gt6_g_b : std_ulogic_vector(0 to 5); + signal gt6_t_b : std_ulogic_vector(0 to 4); + signal f0_xxxx11 : std_ulogic; + signal f1_0xxxx : std_ulogic; + signal f1_1xxx0 : std_ulogic; + signal f1_xxxx0 : std_ulogic; + signal f1_xxxx1 : std_ulogic; + signal f2_xxx1x : std_ulogic; + signal f1_xx1xx : std_ulogic; + signal xtd_nand_or_orc : std_ulogic; + signal rld_cr : std_ulogic; + signal rld_cl : std_ulogic; + signal rld_icr : std_ulogic; + signal rld_icl : std_ulogic; + signal rld_ic : std_ulogic; + signal rld_imi : std_ulogic; + signal sh_lft_imm_dw : std_ulogic; + signal sh_lft_imm : std_ulogic; + signal sh_rgt_imm_dw : std_ulogic; + signal sh_rgt_imm : std_ulogic; + signal rotld_en_mbgtme : std_ulogic; + signal rf1_log_fcn : std_ulogic_vector(0 to 3); + signal isel : std_ulogic; + +begin + + isel <= '1' when x31='1' and i(26 to 30) = "01111" else '0'; + + cmp_byt <= '1' when x31='1' and i(21 to 30) = "0111111100" else '0'; + + cr_log <= not i(0) and i(1) and not i(2) and not i(3) and i(4) and i(5) ; + rotlw <= not i(0) and i(1) and not i(2) and i(3) ; + imm_log <= not i(0) and i(1) and i(2) and (not i(3) or not i(4) ); + rotld <= not i(0) and i(1) and i(2) and i(3) and i(4) and not i(5) ; + x31 <= not i(0) and i(1) and i(2) and i(3) and i(4) and i(5) ; + + f0_xxxx00 <= not i(4) and not i(5) ; + f0_xxx0xx <= not i(3) ; + f0_xxxx0x <= not i(4) ; + f0_xxxx11 <= i(4) and i(5) ; + + + + f1_0xxxx <= not i(21) ; + f1_110xx <= i(21) and i(22) and not i(23) ; + f1_111xx <= i(21) and i(22) and i(23) ; + f1_1xxx0 <= i(21) and not i(25) ; + f1_1xxxx <= i(21) ; + f1_x1x1x <= i(22) and i(24) ; + f1_xx1xx <= i(23) ; + f1_x1xx0 <= i(22) and not i(25) ; + f1_x1xx1 <= i(22) and i(25) ; + f1_xx10x <= i(23) and not i(24) ; + f1_xxx01 <= not i(24) and i(25) ; + f1_xxx11 <= i(24) and i(25) ; + f1_xxxx0 <= not i(25) ; + f1_xxxx1 <= i(25) ; + f1_xxx00 <= not i(24) and not i(25) ; + f1_xxx10 <= i(24) and not i(25) ; + + + f2_11xxx <= i(26) and i(27) ; + f2_xxx0x <= not i(29) ; + f2_111xx <= i(26) and i(27) and i(28) ; + f2_xx01x <= not i(28) and i(29) ; + f2_xx00x <= not i(28) and not i(29) ; + f2_xxx1x <= i(29) ; + + + rotlw_nm <= rotlw and f0_xxxx11 ; + rotlw_pass <= rotlw and f0_xxxx00 ; + + rotld_pass <= rld_imi ; + + sh_lft_rb <= x31 and f1_0xxxx ; + sh_lft_rb_dw <= x31 and f1_0xxxx and f2_xxx1x ; + sh_rgt <= x31 and f1_1xxxx ; + sh_rgt_rb <= x31 and f1_1xxx0 ; + sh_rgt_rb_dw <= x31 and f1_1xxx0 and f2_xxx1x ; + shift_imm <= x31 and f1_xxxx1 ; + sh_rb <= x31 and f1_xxxx0 ; + sh_rb_dw <= x31 and f1_xxxx0 and f2_xxx1x ; + sh_rb_wd <= x31 and f1_xxxx0 and f2_xxx0x ; + x31_sh_log_sgn <= x31 and f2_11xxx ; + op_sgn_xtd <= x31 and f1_111xx ; + op_sra <= x31 and f1_110xx ; + wd_if_sh <= x31 and f2_xxx0x ; + xtd_log <= x31 and f2_111xx ; + + sh_lft_imm_dw <= tidn; + sh_lft_imm <= tidn; + sh_rgt_imm_dw <= x31 and i(21) and i(25) and i(29) ; + sh_rgt_imm <= x31 and i(21) and i(25) ; + + + dec_alu_rf1_sel_rot_log <= (cmp_byt ) or + (cr_log ) or + (rotlw ) or + (imm_log ) or + (rotld ) or + (x31_sh_log_sgn ); + + dec_alu_rf1_zm_ins <= (isel ) or + (cmp_byt ) or + (cr_log ) or + (xtd_log ) or + (imm_log ) or + (op_sgn_xtd ); + + dec_alu_rf1_sh_right <= sh_rgt; + + sh_word_int <=(rotlw ) or + (wd_if_sh ); + + dec_alu_rf1_sh_word <= sh_word_int ; + dec_alu_rf1_cr_logical <= cr_log ; + + dec_alu_rf1_sgnxtd_byte <= op_sgn_xtd and f1_xxx01 and not isel; + dec_alu_rf1_sgnxtd_half <= op_sgn_xtd and f1_xxx00 and not isel; + dec_alu_rf1_sgnxtd_wd <= op_sgn_xtd and f1_xxx10 and not isel; + dec_alu_rf1_sra_dw <= op_sra and f2_xx01x and not isel; + dec_alu_rf1_sra_wd <= op_sra and f2_xx00x and not isel; + + dec_alu_rf1_cr_log_fcn(0) <= i(25) ; + dec_alu_rf1_cr_log_fcn(1) <= i(24) ; + dec_alu_rf1_cr_log_fcn(2) <= i(23) ; + dec_alu_rf1_cr_log_fcn(3) <= i(22) ; + + imm_xor_or <= f0_xxx0xx ; + imm_and_or <= f0_xxxx0x ; + xtd_nor <= f1_xxx11 ; + xtd_eqv_orc_nand <= f1_x1xx0 ; + xtd_nand <= f1_x1x1x ; + xtd_nand_or_orc <= f1_xx1xx ; + xtd_andc_xor_or <= f1_xxx01 ; + xtd_and_eqv_orc <= f1_xxx00 ; + xtd_or_orc <= f1_xx10x ; + xtd_xor_or <= f1_x1xx1 ; + + + with cmp_byt select + dec_alu_rf1_log_fcn <= "1001" when '1', + rf1_log_fcn when others; + + + rf1_log_fcn(0) <= (xtd_log and xtd_nor ) or + (xtd_log and xtd_eqv_orc_nand ) or + (cmp_byt ) ; + + rf1_log_fcn(1) <= (xtd_log and xtd_xor_or ) or + (xtd_log and xtd_nand ) or + (imm_log and imm_xor_or ) or + (rotlw_pass ) or + (rotld_pass ) ; + + rf1_log_fcn(2) <= (xtd_log and xtd_andc_xor_or ) or + (xtd_log and xtd_nand_or_orc ) or + (imm_log and imm_xor_or ) ; + + + rf1_log_fcn(3) <= (cmp_byt ) or + (xtd_log and xtd_and_eqv_orc ) or + (xtd_log and xtd_or_orc ) or + (imm_log and imm_and_or ) or + (rotlw_pass ) or + (rotld_pass ) ; + + + dec_alu_rf1_chk_shov_dw <= (sh_rb_dw ); + dec_alu_rf1_chk_shov_wd <= (sh_rb_wd ); + + + + dec_alu_rf1_me_ins_b(0 to 5) <= not me_ins(0 to 5) ; + + me_ins(0) <= ( rotlw ) or + ( i(26) and sel_ins_me_hi ) or + ( not i(30) and sel_ins_amt_hi ) ; + + me_ins(1 to 5) <= ( i(26 to 30) and (1 to 5=> sel_ins_me_lo_wd) ) or + ( i(21 to 25) and (1 to 5=> sel_ins_me_lo_dw) ) or + ( not i(16 to 20) and (1 to 5=> sel_ins_amt_lo ) ) ; + + sel_ins_me_lo_wd <= rotlw ; + sel_ins_me_lo_dw <= rld_cr or rld_icr ; + + sel_ins_amt_lo <= rld_ic or rld_imi or sh_lft_rb ; + sel_ins_amt_hi <= rld_ic or rld_imi or sh_lft_rb_dw ; + sel_ins_me_hi <= rld_cr or rld_icr ; + + + dec_alu_rf1_use_me_rb_hi <= ( sh_lft_rb_dw ); + dec_alu_rf1_use_me_rb_lo <= ( sh_lft_rb ); + + dec_alu_rf1_use_me_ins_hi <= rld_cr or rld_icr or rld_imi or rld_ic or rotlw or sh_lft_imm_dw ; + dec_alu_rf1_use_me_ins_lo <= rld_cr or rld_icr or rld_imi or rld_ic or rotlw or sh_lft_imm ; + + rld_icl <= rotld and not i(27) and not i(28) and not i(29) ; + rld_icr <= rotld and not i(27) and not i(28) and i(29) ; + rld_ic <= rotld and not i(27) and i(28) and not i(29) ; + rld_imi <= rotld and not i(27) and i(28) and i(29) ; + rld_cl <= rotld and i(27) and not i(30); + rld_cr <= rotld and i(27) and i(30); + + + + dec_alu_rf1_mb_ins(0) <= ( i(26) and rot_imm_mb ) or + ( i(30) and shift_imm ) or + ( rotlw ) or + ( wd_if_sh ) ; + + + dec_alu_rf1_mb_ins(1 to 5) <= ( i(21 to 25) and (1 to 5=> rot_imm_mb ) ) or + ( i(16 to 20) and (1 to 5=> shift_imm ) ) ; + + + rot_imm_mb <= ( rotlw ) or + ( rld_cl or rld_icl or rld_ic or rld_imi ) ; + + + dec_alu_rf1_use_mb_rb_lo <= sh_rgt_rb ; + dec_alu_rf1_use_mb_rb_hi <= sh_rgt_rb_dw ; + dec_alu_rf1_use_mb_ins_hi <= rld_cl or rld_icl or rld_imi or rld_ic or rotlw or sh_rgt_imm_dw or wd_if_sh; + dec_alu_rf1_use_mb_ins_lo <= rld_cl or rld_icl or rld_imi or rld_ic or rotlw or sh_rgt_imm ; + + + + dec_alu_rf1_use_rb_amt_hi <= ( rld_cr ) or + ( rld_cl ) or + ( sh_rb_dw ) ; + + + + dec_alu_rf1_use_rb_amt_lo <= ( rld_cr ) or + ( rld_cl ) or + ( rotlw_nm ) or + ( sh_rb ) ; + + + + dec_alu_rf1_sh_amt(0) <= i(30) and not sh_word_int ; + dec_alu_rf1_sh_amt(1 to 5) <= i(16 to 20) ; + + + + rotld_en_mbgtme <= rld_imi or rld_ic ; + + dec_alu_rf1_mb_gt_me <= (mb_gt_me_cmp_wd and rotlw ) or + (mb_gt_me_cmp_dw and rotld_en_mbgtme ) ; + + + + + gt5_in1(1 to 5) <= i(21 to 25) ; + gt5_in0(1 to 5) <= not i(26 to 30) ; + + gt6_in1(0 to 5) <= i(26) & i(21 to 25) ; + gt6_in0(0 to 5) <= i(30) & i(16 to 20) ; + + + gt5_g_b(1 to 5) <= not( gt5_in0(1 to 5) and gt5_in1(1 to 5) ); + gt5_t_b(1 to 4) <= not( gt5_in0(1 to 4) or gt5_in1(1 to 4) ); + + gt5_g_45 <= not( gt5_g_b(4) and (gt5_t_b(4) or gt5_g_b(5) ) ); + gt5_g_23 <= not( gt5_g_b(2) and (gt5_t_b(2) or gt5_g_b(3) ) ); + gt5_g_1 <= not( gt5_g_b(1) ); + + gt5_t_23 <= not( gt5_t_b(2) or gt5_t_b(3) ); + gt5_t_1 <= not( gt5_t_b(1) ); + + mb_gt_me_cmp_wd0_b <= not( gt5_g_1 ); + mb_gt_me_cmp_wd1_b <= not( gt5_g_23 and gt5_t_1 ); + mb_gt_me_cmp_wd2_b <= not( gt5_g_45 and gt5_t_1 and gt5_t_23 ); + + mb_gt_me_cmp_wd <= not( mb_gt_me_cmp_wd0_b and mb_gt_me_cmp_wd1_b and mb_gt_me_cmp_wd2_b ); + + + gt6_g_b(0 to 5) <= not( gt6_in0(0 to 5) and gt6_in1(0 to 5) ); + gt6_t_b(0 to 4) <= not( gt6_in0(0 to 4) or gt6_in1(0 to 4) ); + + gt6_g_45 <= not( gt6_g_b(4) and (gt6_t_b(4) or gt6_g_b(5) ) ); + gt6_g_23 <= not( gt6_g_b(2) and (gt6_t_b(2) or gt6_g_b(3) ) ); + gt6_g_01 <= not( gt6_g_b(0) and (gt6_t_b(0) or gt6_g_b(1) ) ); + + gt6_t_23 <= not( gt6_t_b(2) or gt6_t_b(3) ); + gt6_t_01 <= not( gt6_t_b(0) or gt6_t_b(1) ); + + mb_gt_me_cmp_dw0_b <= not( gt6_g_01 ); + mb_gt_me_cmp_dw1_b <= not( gt6_g_23 and gt6_t_01 ); + mb_gt_me_cmp_dw2_b <= not( gt6_g_45 and gt6_t_01 and gt6_t_23 ); + + mb_gt_me_cmp_dw <= not( mb_gt_me_cmp_dw0_b and mb_gt_me_cmp_dw1_b and mb_gt_me_cmp_dw2_b ); + + + mark_unused(i(6 to 15)); + mark_unused(i(31)); + + +end architecture xuq_dec_dcdmrg; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_dec_sspr.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_dec_sspr.vhdl new file mode 100644 index 0000000..441d8fd --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_dec_sspr.vhdl @@ -0,0 +1,470 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee,ibm,support,work,tri; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use support.power_logic_pkg.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use tri.tri_latches_pkg.all; +use work.xuq_pkg.all; + +entity xuq_dec_sspr is +generic( + expand_type : integer := 2; + threads : integer := 4; + ctr_size : integer := 5); +port( + nclk : in clk_logic; + + d_mode_dc : in std_ulogic; + delay_lclkr_dc : in std_ulogic; + mpw1_dc_b : in std_ulogic; + mpw2_dc_b : in std_ulogic; + + func_sl_force : in std_ulogic; + func_sl_thold_0_b : in std_ulogic; + sg_0 : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + rf1_act : in std_ulogic; + rf1_val : in std_ulogic_vector(0 to threads-1); + rf1_instr : in std_ulogic_vector(0 to 31); + + spr_dec_spr_xucr0_ssdly : in std_ulogic_vector(0 to ctr_size-1); + + slowspr_need_hole : out std_ulogic; + ex1_is_slowspr_rd : out std_ulogic; + ex1_is_slowspr_wr : out std_ulogic; + + vdd : inout power_logic; + gnd : inout power_logic +); + +-- synopsys translate_off + +-- synopsys translate_on +end xuq_dec_sspr; +architecture xuq_dec_sspr of xuq_dec_sspr is + +subtype s2 is std_ulogic_vector(0 to 1); +type T_ctr is array (0 to threads-1) of std_ulogic_vector(0 to ctr_size-1); +signal slowspr_ctr_q, slowspr_ctr_d : T_ctr; +signal spr_xucr0_ssdly_q : std_ulogic_vector(0 to ctr_size-1); +signal ex1_is_slowspr_wr_q, rf1_is_slowspr_wr : std_ulogic; +signal ex1_is_slowspr_rd_q, rf1_is_slowspr_rd : std_ulogic; +signal slowspr_hole_q, slowspr_hole_d : std_ulogic; +constant slowspr_ctr_offset : integer := 0; +constant spr_xucr0_ssdly_offset : integer := slowspr_ctr_offset + slowspr_ctr_q(0)'length*threads; +constant ex1_is_slowspr_wr_offset : integer := spr_xucr0_ssdly_offset + spr_xucr0_ssdly_q'length; +constant ex1_is_slowspr_rd_offset : integer := ex1_is_slowspr_wr_offset + 1; +constant slowspr_hole_offset : integer := ex1_is_slowspr_rd_offset + 1; +constant scan_right : integer := slowspr_hole_offset + 1; +signal siv : std_ulogic_vector(0 to scan_right-1); +signal sov : std_ulogic_vector(0 to scan_right-1); +signal tiup : std_ulogic; +signal rf1_opcode_is_31 : std_ulogic; +signal rf1_is_mfspr, rf1_is_mtspr : std_ulogic; +signal rf1_slowspr_range : std_ulogic; +signal rf1_sspr_ctr_init, rf1_sspr_ctr_act : std_ulogic_vector(0 to threads-1); +signal slowspr_ctr_zero, slowspr_ctr_one : std_ulogic_vector(0 to threads-1); +signal slowspr_hole : std_ulogic_vector(0 to threads-1); +signal slowspr_ctr_m1 : T_ctr; +signal + rf1_dvc1_re , rf1_dvc2_re , rf1_eplc_re , rf1_epsc_re + , rf1_eptcfg_re , rf1_immr_re , rf1_imr_re , rf1_iucr0_re + , rf1_iucr1_re , rf1_iucr2_re , rf1_iudbg0_re , rf1_iudbg1_re + , rf1_iudbg2_re , rf1_iulfsr_re , rf1_iullcr_re , rf1_lper_re + , rf1_lperu_re , rf1_lpidr_re , rf1_lratcfg_re , rf1_lratps_re + , rf1_mas0_re , rf1_mas0_mas1_re, rf1_mas1_re , rf1_mas2_re + , rf1_mas2u_re , rf1_mas3_re , rf1_mas4_re , rf1_mas5_re + , rf1_mas5_mas6_re, rf1_mas6_re , rf1_mas7_re , rf1_mas7_mas3_re + , rf1_mas8_re , rf1_mas8_mas1_re, rf1_mmucfg_re , rf1_mmucr0_re + , rf1_mmucr1_re , rf1_mmucr2_re , rf1_mmucr3_re , rf1_mmucsr0_re + , rf1_pid_re , rf1_ppr32_re , rf1_tlb0cfg_re , rf1_tlb0ps_re + , rf1_xucr2_re , rf1_xudbg0_re , rf1_xudbg1_re , rf1_xudbg2_re + : std_ulogic; +signal + rf1_dvc1_we , rf1_dvc2_we , rf1_eplc_we , rf1_epsc_we + , rf1_immr_we , rf1_imr_we , rf1_iucr0_we , rf1_iucr1_we + , rf1_iucr2_we , rf1_iudbg0_we , rf1_iulfsr_we , rf1_iullcr_we + , rf1_lper_we , rf1_lperu_we , rf1_lpidr_we , rf1_mas0_we + , rf1_mas0_mas1_we, rf1_mas1_we , rf1_mas2_we , rf1_mas2u_we + , rf1_mas3_we , rf1_mas4_we , rf1_mas5_we , rf1_mas5_mas6_we + , rf1_mas6_we , rf1_mas7_we , rf1_mas7_mas3_we, rf1_mas8_we + , rf1_mas8_mas1_we, rf1_mmucr0_we , rf1_mmucr1_we , rf1_mmucr2_we + , rf1_mmucr3_we , rf1_mmucsr0_we , rf1_pid_we , rf1_ppr32_we + , rf1_xucr2_we , rf1_xudbg0_we + : std_ulogic; +signal + rf1_dvc1_rdec , rf1_dvc2_rdec , rf1_eplc_rdec , rf1_epsc_rdec + , rf1_eptcfg_rdec, rf1_immr_rdec , rf1_imr_rdec , rf1_iucr0_rdec + , rf1_iucr1_rdec , rf1_iucr2_rdec , rf1_iudbg0_rdec, rf1_iudbg1_rdec + , rf1_iudbg2_rdec, rf1_iulfsr_rdec, rf1_iullcr_rdec, rf1_lper_rdec + , rf1_lperu_rdec , rf1_lpidr_rdec , rf1_lratcfg_rdec, rf1_lratps_rdec + , rf1_mas0_rdec , rf1_mas0_mas1_rdec, rf1_mas1_rdec , rf1_mas2_rdec + , rf1_mas2u_rdec , rf1_mas3_rdec , rf1_mas4_rdec , rf1_mas5_rdec + , rf1_mas5_mas6_rdec, rf1_mas6_rdec , rf1_mas7_rdec , rf1_mas7_mas3_rdec + , rf1_mas8_rdec , rf1_mas8_mas1_rdec, rf1_mmucfg_rdec, rf1_mmucr0_rdec + , rf1_mmucr1_rdec, rf1_mmucr2_rdec, rf1_mmucr3_rdec, rf1_mmucsr0_rdec + , rf1_pid_rdec , rf1_ppr32_rdec , rf1_tlb0cfg_rdec, rf1_tlb0ps_rdec + , rf1_xucr2_rdec , rf1_xudbg0_rdec, rf1_xudbg1_rdec, rf1_xudbg2_rdec + : std_ulogic; +signal + rf1_dvc1_wdec , rf1_dvc2_wdec , rf1_eplc_wdec , rf1_epsc_wdec + , rf1_immr_wdec , rf1_imr_wdec , rf1_iucr0_wdec , rf1_iucr1_wdec + , rf1_iucr2_wdec , rf1_iudbg0_wdec, rf1_iulfsr_wdec, rf1_iullcr_wdec + , rf1_lper_wdec , rf1_lperu_wdec , rf1_lpidr_wdec , rf1_mas0_wdec + , rf1_mas0_mas1_wdec, rf1_mas1_wdec , rf1_mas2_wdec , rf1_mas2u_wdec + , rf1_mas3_wdec , rf1_mas4_wdec , rf1_mas5_wdec , rf1_mas5_mas6_wdec + , rf1_mas6_wdec , rf1_mas7_wdec , rf1_mas7_mas3_wdec, rf1_mas8_wdec + , rf1_mas8_mas1_wdec, rf1_mmucr0_wdec, rf1_mmucr1_wdec, rf1_mmucr2_wdec + , rf1_mmucr3_wdec, rf1_mmucsr0_wdec, rf1_pid_wdec , rf1_ppr32_wdec + , rf1_xucr2_wdec , rf1_xudbg0_wdec + : std_ulogic; + +begin + +tiup <= '1'; + +slowspr_hole_gen : for t in 0 to threads-1 generate + + rf1_sspr_ctr_act(t) <= rf1_val(t) or not slowspr_ctr_zero(t); + + rf1_sspr_ctr_init(t) <= rf1_val(t) and rf1_is_mfspr and rf1_is_slowspr_rd; + + slowspr_ctr_m1(t) <= std_ulogic_vector(unsigned(slowspr_ctr_q(t)) - 1); + + with s2'(rf1_sspr_ctr_init(t) & slowspr_ctr_zero(t)) select + slowspr_ctr_d(t) <= slowspr_ctr_m1(t) when "00", + (others=>'0') when "01", + spr_xucr0_ssdly_q when others; + + slowspr_ctr_zero(t) <= not or_reduce(slowspr_ctr_q(t)); + + slowspr_ctr_one(t) <= not or_reduce(slowspr_ctr_q(t)(0 to ctr_size-2)) and slowspr_ctr_q(t)(ctr_size-1); + + with (not or_reduce(spr_xucr0_ssdly_q)) select + slowspr_hole(t) <= rf1_sspr_ctr_init(t) when '1', + slowspr_ctr_one(t) when others; + +end generate; + +slowspr_hole_d <= or_reduce(slowspr_hole); +slowspr_need_hole <= slowspr_hole_q; +ex1_is_slowspr_wr <= ex1_is_slowspr_wr_q; +ex1_is_slowspr_rd <= ex1_is_slowspr_rd_q; + +rf1_opcode_is_31 <= rf1_instr(0 to 5) = "011111"; +rf1_is_mfspr <= '1' when rf1_opcode_is_31='1' and rf1_instr(21 to 30) = "0101010011" else '0'; +rf1_is_mtspr <= '1' when rf1_opcode_is_31='1' and rf1_instr(21 to 30) = "0111010011" else '0'; +rf1_slowspr_range <=((rf1_instr(16 to 20) = "11110") or + (rf1_instr(16 to 20) = "11100")) + and rf1_instr(11); +rf1_dvc1_rdec <= (rf1_instr(11 to 20) = "1111001001"); +rf1_dvc2_rdec <= (rf1_instr(11 to 20) = "1111101001"); +rf1_eplc_rdec <= (rf1_instr(11 to 20) = "1001111101"); +rf1_epsc_rdec <= (rf1_instr(11 to 20) = "1010011101"); +rf1_eptcfg_rdec <= (rf1_instr(11 to 20) = "1111001010"); +rf1_immr_rdec <= (rf1_instr(11 to 20) = "1000111011"); +rf1_imr_rdec <= (rf1_instr(11 to 20) = "1000011011"); +rf1_iucr0_rdec <= (rf1_instr(11 to 20) = "1001111111"); +rf1_iucr1_rdec <= (rf1_instr(11 to 20) = "1001111011"); +rf1_iucr2_rdec <= (rf1_instr(11 to 20) = "1010011011"); +rf1_iudbg0_rdec <= (rf1_instr(11 to 20) = "1100011011"); +rf1_iudbg1_rdec <= (rf1_instr(11 to 20) = "1100111011"); +rf1_iudbg2_rdec <= (rf1_instr(11 to 20) = "1101011011"); +rf1_iulfsr_rdec <= (rf1_instr(11 to 20) = "1101111011"); +rf1_iullcr_rdec <= (rf1_instr(11 to 20) = "1110011011"); +rf1_lper_rdec <= (rf1_instr(11 to 20) = "1100000001"); +rf1_lperu_rdec <= (rf1_instr(11 to 20) = "1100100001"); +rf1_lpidr_rdec <= (rf1_instr(11 to 20) = "1001001010"); +rf1_lratcfg_rdec <= (rf1_instr(11 to 20) = "1011001010"); +rf1_lratps_rdec <= (rf1_instr(11 to 20) = "1011101010"); +rf1_mas0_rdec <= (rf1_instr(11 to 20) = "1000010011"); +rf1_mas0_mas1_rdec<= (rf1_instr(11 to 20) = "1010101011"); +rf1_mas1_rdec <= (rf1_instr(11 to 20) = "1000110011"); +rf1_mas2_rdec <= (rf1_instr(11 to 20) = "1001010011"); +rf1_mas2u_rdec <= (rf1_instr(11 to 20) = "1011110011"); +rf1_mas3_rdec <= (rf1_instr(11 to 20) = "1001110011"); +rf1_mas4_rdec <= (rf1_instr(11 to 20) = "1010010011"); +rf1_mas5_rdec <= (rf1_instr(11 to 20) = "1001101010"); +rf1_mas5_mas6_rdec<= (rf1_instr(11 to 20) = "1110001010"); +rf1_mas6_rdec <= (rf1_instr(11 to 20) = "1011010011"); +rf1_mas7_rdec <= (rf1_instr(11 to 20) = "1000011101"); +rf1_mas7_mas3_rdec<= (rf1_instr(11 to 20) = "1010001011"); +rf1_mas8_rdec <= (rf1_instr(11 to 20) = "1010101010"); +rf1_mas8_mas1_rdec<= (rf1_instr(11 to 20) = "1110101010"); +rf1_mmucfg_rdec <= (rf1_instr(11 to 20) = "1011111111"); +rf1_mmucr0_rdec <= (rf1_instr(11 to 20) = "1110011111"); +rf1_mmucr1_rdec <= (rf1_instr(11 to 20) = "1110111111"); +rf1_mmucr2_rdec <= (rf1_instr(11 to 20) = "1111011111"); +rf1_mmucr3_rdec <= (rf1_instr(11 to 20) = "1111111111"); +rf1_mmucsr0_rdec <= (rf1_instr(11 to 20) = "1010011111"); +rf1_pid_rdec <= (rf1_instr(11 to 20) = "1000000001"); +rf1_ppr32_rdec <= (rf1_instr(11 to 20) = "0001011100"); +rf1_tlb0cfg_rdec <= (rf1_instr(11 to 20) = "1000010101"); +rf1_tlb0ps_rdec <= (rf1_instr(11 to 20) = "1100001010"); +rf1_xucr2_rdec <= (rf1_instr(11 to 20) = "1100011111"); +rf1_xudbg0_rdec <= (rf1_instr(11 to 20) = "1010111011"); +rf1_xudbg1_rdec <= (rf1_instr(11 to 20) = "1011011011"); +rf1_xudbg2_rdec <= (rf1_instr(11 to 20) = "1011111011"); +rf1_dvc1_re <= rf1_dvc1_rdec; +rf1_dvc2_re <= rf1_dvc2_rdec; +rf1_eplc_re <= rf1_eplc_rdec; +rf1_epsc_re <= rf1_epsc_rdec; +rf1_eptcfg_re <= rf1_eptcfg_rdec; +rf1_immr_re <= rf1_immr_rdec; +rf1_imr_re <= rf1_imr_rdec; +rf1_iucr0_re <= rf1_iucr0_rdec; +rf1_iucr1_re <= rf1_iucr1_rdec; +rf1_iucr2_re <= rf1_iucr2_rdec; +rf1_iudbg0_re <= rf1_iudbg0_rdec; +rf1_iudbg1_re <= rf1_iudbg1_rdec; +rf1_iudbg2_re <= rf1_iudbg2_rdec; +rf1_iulfsr_re <= rf1_iulfsr_rdec; +rf1_iullcr_re <= rf1_iullcr_rdec; +rf1_lper_re <= rf1_lper_rdec; +rf1_lperu_re <= rf1_lperu_rdec; +rf1_lpidr_re <= rf1_lpidr_rdec; +rf1_lratcfg_re <= rf1_lratcfg_rdec; +rf1_lratps_re <= rf1_lratps_rdec; +rf1_mas0_re <= rf1_mas0_rdec; +rf1_mas0_mas1_re <= rf1_mas0_mas1_rdec; +rf1_mas1_re <= rf1_mas1_rdec; +rf1_mas2_re <= rf1_mas2_rdec; +rf1_mas2u_re <= rf1_mas2u_rdec; +rf1_mas3_re <= rf1_mas3_rdec; +rf1_mas4_re <= rf1_mas4_rdec; +rf1_mas5_re <= rf1_mas5_rdec; +rf1_mas5_mas6_re <= rf1_mas5_mas6_rdec; +rf1_mas6_re <= rf1_mas6_rdec; +rf1_mas7_re <= rf1_mas7_rdec; +rf1_mas7_mas3_re <= rf1_mas7_mas3_rdec; +rf1_mas8_re <= rf1_mas8_rdec; +rf1_mas8_mas1_re <= rf1_mas8_mas1_rdec; +rf1_mmucfg_re <= rf1_mmucfg_rdec; +rf1_mmucr0_re <= rf1_mmucr0_rdec; +rf1_mmucr1_re <= rf1_mmucr1_rdec; +rf1_mmucr2_re <= rf1_mmucr2_rdec; +rf1_mmucr3_re <= rf1_mmucr3_rdec; +rf1_mmucsr0_re <= rf1_mmucsr0_rdec; +rf1_pid_re <= rf1_pid_rdec; +rf1_ppr32_re <= rf1_ppr32_rdec; +rf1_tlb0cfg_re <= rf1_tlb0cfg_rdec; +rf1_tlb0ps_re <= rf1_tlb0ps_rdec; +rf1_xucr2_re <= rf1_xucr2_rdec; +rf1_xudbg0_re <= rf1_xudbg0_rdec; +rf1_xudbg1_re <= rf1_xudbg1_rdec; +rf1_xudbg2_re <= rf1_xudbg2_rdec; +rf1_dvc1_wdec <= rf1_dvc1_rdec; +rf1_dvc2_wdec <= rf1_dvc2_rdec; +rf1_eplc_wdec <= rf1_eplc_rdec; +rf1_epsc_wdec <= rf1_epsc_rdec; +rf1_immr_wdec <= rf1_immr_rdec; +rf1_imr_wdec <= rf1_imr_rdec; +rf1_iucr0_wdec <= rf1_iucr0_rdec; +rf1_iucr1_wdec <= rf1_iucr1_rdec; +rf1_iucr2_wdec <= rf1_iucr2_rdec; +rf1_iudbg0_wdec <= rf1_iudbg0_rdec; +rf1_iulfsr_wdec <= rf1_iulfsr_rdec; +rf1_iullcr_wdec <= rf1_iullcr_rdec; +rf1_lper_wdec <= rf1_lper_rdec; +rf1_lperu_wdec <= rf1_lperu_rdec; +rf1_lpidr_wdec <= rf1_lpidr_rdec; +rf1_mas0_wdec <= rf1_mas0_rdec; +rf1_mas0_mas1_wdec<= rf1_mas0_mas1_rdec; +rf1_mas1_wdec <= rf1_mas1_rdec; +rf1_mas2_wdec <= rf1_mas2_rdec; +rf1_mas2u_wdec <= rf1_mas2u_rdec; +rf1_mas3_wdec <= rf1_mas3_rdec; +rf1_mas4_wdec <= rf1_mas4_rdec; +rf1_mas5_wdec <= rf1_mas5_rdec; +rf1_mas5_mas6_wdec<= rf1_mas5_mas6_rdec; +rf1_mas6_wdec <= rf1_mas6_rdec; +rf1_mas7_wdec <= rf1_mas7_rdec; +rf1_mas7_mas3_wdec<= rf1_mas7_mas3_rdec; +rf1_mas8_wdec <= rf1_mas8_rdec; +rf1_mas8_mas1_wdec<= rf1_mas8_mas1_rdec; +rf1_mmucr0_wdec <= rf1_mmucr0_rdec; +rf1_mmucr1_wdec <= rf1_mmucr1_rdec; +rf1_mmucr2_wdec <= rf1_mmucr2_rdec; +rf1_mmucr3_wdec <= rf1_mmucr3_rdec; +rf1_mmucsr0_wdec <= rf1_mmucsr0_rdec; +rf1_pid_wdec <= rf1_pid_rdec; +rf1_ppr32_wdec <= rf1_ppr32_rdec; +rf1_xucr2_wdec <= rf1_xucr2_rdec; +rf1_xudbg0_wdec <= rf1_xudbg0_rdec; +rf1_dvc1_we <= rf1_dvc1_wdec; +rf1_dvc2_we <= rf1_dvc2_wdec; +rf1_eplc_we <= rf1_eplc_wdec; +rf1_epsc_we <= rf1_epsc_wdec; +rf1_immr_we <= rf1_immr_wdec; +rf1_imr_we <= rf1_imr_wdec; +rf1_iucr0_we <= rf1_iucr0_wdec; +rf1_iucr1_we <= rf1_iucr1_wdec; +rf1_iucr2_we <= rf1_iucr2_wdec; +rf1_iudbg0_we <= rf1_iudbg0_wdec; +rf1_iulfsr_we <= rf1_iulfsr_wdec; +rf1_iullcr_we <= rf1_iullcr_wdec; +rf1_lper_we <= rf1_lper_wdec; +rf1_lperu_we <= rf1_lperu_wdec; +rf1_lpidr_we <= rf1_lpidr_wdec; +rf1_mas0_we <= rf1_mas0_wdec; +rf1_mas0_mas1_we <= rf1_mas0_mas1_wdec; +rf1_mas1_we <= rf1_mas1_wdec; +rf1_mas2_we <= rf1_mas2_wdec; +rf1_mas2u_we <= rf1_mas2u_wdec; +rf1_mas3_we <= rf1_mas3_wdec; +rf1_mas4_we <= rf1_mas4_wdec; +rf1_mas5_we <= rf1_mas5_wdec; +rf1_mas5_mas6_we <= rf1_mas5_mas6_wdec; +rf1_mas6_we <= rf1_mas6_wdec; +rf1_mas7_we <= rf1_mas7_wdec; +rf1_mas7_mas3_we <= rf1_mas7_mas3_wdec; +rf1_mas8_we <= rf1_mas8_wdec; +rf1_mas8_mas1_we <= rf1_mas8_mas1_wdec; +rf1_mmucr0_we <= rf1_mmucr0_wdec; +rf1_mmucr1_we <= rf1_mmucr1_wdec; +rf1_mmucr2_we <= rf1_mmucr2_wdec; +rf1_mmucr3_we <= rf1_mmucr3_wdec; +rf1_mmucsr0_we <= rf1_mmucsr0_wdec; +rf1_pid_we <= rf1_pid_wdec; +rf1_ppr32_we <= rf1_ppr32_wdec; +rf1_xucr2_we <= rf1_xucr2_wdec; +rf1_xudbg0_we <= rf1_xudbg0_wdec; + +rf1_is_slowspr_wr <=(rf1_is_mtspr and (rf1_slowspr_range or + rf1_dvc1_we or rf1_dvc2_we or rf1_eplc_we + or rf1_epsc_we or rf1_immr_we or rf1_imr_we + or rf1_iucr0_we or rf1_iucr1_we or rf1_iucr2_we + or rf1_iudbg0_we or rf1_iulfsr_we or rf1_iullcr_we + or rf1_lper_we or rf1_lperu_we or rf1_lpidr_we + or rf1_mas0_we or rf1_mas0_mas1_we or rf1_mas1_we + or rf1_mas2_we or rf1_mas2u_we or rf1_mas3_we + or rf1_mas4_we or rf1_mas5_we or rf1_mas5_mas6_we + or rf1_mas6_we or rf1_mas7_we or rf1_mas7_mas3_we + or rf1_mas8_we or rf1_mas8_mas1_we or rf1_mmucr0_we + or rf1_mmucr1_we or rf1_mmucr2_we or rf1_mmucr3_we + or rf1_mmucsr0_we or rf1_pid_we or rf1_ppr32_we + or rf1_xucr2_we or rf1_xudbg0_we )); +rf1_is_slowspr_rd <= (rf1_is_mfspr and (rf1_slowspr_range or + rf1_dvc1_re or rf1_dvc2_re or rf1_eplc_re + or rf1_epsc_re or rf1_eptcfg_re or rf1_immr_re + or rf1_imr_re or rf1_iucr0_re or rf1_iucr1_re + or rf1_iucr2_re or rf1_iudbg0_re or rf1_iudbg1_re + or rf1_iudbg2_re or rf1_iulfsr_re or rf1_iullcr_re + or rf1_lper_re or rf1_lperu_re or rf1_lpidr_re + or rf1_lratcfg_re or rf1_lratps_re or rf1_mas0_re + or rf1_mas0_mas1_re or rf1_mas1_re or rf1_mas2_re + or rf1_mas2u_re or rf1_mas3_re or rf1_mas4_re + or rf1_mas5_re or rf1_mas5_mas6_re or rf1_mas6_re + or rf1_mas7_re or rf1_mas7_mas3_re or rf1_mas8_re + or rf1_mas8_mas1_re or rf1_mmucfg_re or rf1_mmucr0_re + or rf1_mmucr1_re or rf1_mmucr2_re or rf1_mmucr3_re + or rf1_mmucsr0_re or rf1_pid_re or rf1_ppr32_re + or rf1_tlb0cfg_re or rf1_tlb0ps_re or rf1_xucr2_re + or rf1_xudbg0_re or rf1_xudbg1_re or rf1_xudbg2_re )); + +mark_unused(rf1_instr(6 to 10)); +mark_unused(rf1_instr(31)); + +slowspr_ctr_gen : for t in 0 to threads-1 generate +slowspr_ctr_latch : tri_rlmreg_p + generic map (width => slowspr_ctr_q(t)'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_sspr_ctr_act(t), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(slowspr_ctr_offset+slowspr_ctr_q(t)'length*t to slowspr_ctr_offset+slowspr_ctr_q(t)'length*(t+1)-1), + scout => sov(slowspr_ctr_offset+slowspr_ctr_q(t)'length*t to slowspr_ctr_offset+slowspr_ctr_q(t)'length*(t+1)-1), + din => slowspr_ctr_d(t), + dout => slowspr_ctr_q(t)); +end generate; +spr_xucr0_ssdly_latch : tri_rlmreg_p + generic map (width => spr_xucr0_ssdly_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(spr_xucr0_ssdly_offset to spr_xucr0_ssdly_offset + spr_xucr0_ssdly_q'length-1), + scout => sov(spr_xucr0_ssdly_offset to spr_xucr0_ssdly_offset + spr_xucr0_ssdly_q'length-1), + din => spr_dec_spr_xucr0_ssdly, + dout => spr_xucr0_ssdly_q); +ex1_is_slowspr_wr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_slowspr_wr_offset), + scout => sov(ex1_is_slowspr_wr_offset), + din => rf1_is_slowspr_wr, + dout => ex1_is_slowspr_wr_q); +ex1_is_slowspr_rd_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_slowspr_rd_offset), + scout => sov(ex1_is_slowspr_rd_offset), + din => rf1_is_slowspr_rd, + dout => ex1_is_slowspr_rd_q); +slowspr_hole_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(slowspr_hole_offset), + scout => sov(slowspr_hole_offset), + din => slowspr_hole_d, + dout => slowspr_hole_q); + +siv(0 to siv'right) <= sov(1 to siv'right) & scan_in; +scan_out <= sov(0); + +end architecture xuq_dec_sspr; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_eccchk.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_eccchk.vhdl new file mode 100644 index 0000000..42ddeab --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_eccchk.vhdl @@ -0,0 +1,255 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee,ibm,support; +use ieee.std_logic_1164.all; +use ibm.std_ulogic_function_support.all; +use work.xuq_pkg.all; + +entity xuq_eccchk is +generic( + regsize : integer := 32); +port( + din : in std_ulogic_vector(0 to regsize-1); + EnCorr : in std_ulogic; + NSyn : in std_ulogic_vector(0 to 8-(64/regsize)); + Corrd : out std_ulogic_vector(0 to regsize-1); + SBE : out std_ulogic; + UE : out std_ulogic + ); + +-- synopsys translate_off +-- synopsys translate_on + +end xuq_eccchk; +architecture xuq_eccchk of xuq_eccchk is +begin +ecc64 : if regsize = 64 generate + + signal Syn : std_ulogic_vector(0 to 7); + signal DcdD : std_ulogic_vector(0 to 71); + signal Synzero : std_ulogic; + signal SBE_int : std_ulogic; + signal A0to1 : std_ulogic_vector(0 to 3); + signal A2to3 : std_ulogic_vector(0 to 3); + signal A4to5 : std_ulogic_vector(0 to 3); + signal A6to7 : std_ulogic_vector(0 to 2); + + begin + + + Syn <= not NSyn(0 to 7); + + A0to1(0) <= not (NSyn(0) and NSyn(1) and EnCorr); + A0to1(1) <= not (NSyn(0) and Syn(1) and EnCorr); + A0to1(2) <= not ( Syn(0) and NSyn(1) and EnCorr); + A0to1(3) <= not ( Syn(0) and Syn(1) and EnCorr); + + A2to3(0) <= not (NSyn(2) and NSyn(3)); + A2to3(1) <= not (NSyn(2) and Syn(3)); + A2to3(2) <= not ( Syn(2) and NSyn(3)); + A2to3(3) <= not ( Syn(2) and Syn(3)); + + A4to5(0) <= not (NSyn(4) and NSyn(5)); + A4to5(1) <= not (NSyn(4) and Syn(5)); + A4to5(2) <= not ( Syn(4) and NSyn(5)); + A4to5(3) <= not ( Syn(4) and Syn(5)); + + A6to7(0) <= not (NSyn(6) and NSyn(7)); + A6to7(1) <= not (NSyn(6) and Syn(7)); + A6to7(2) <= not ( Syn(6) and NSyn(7)); + + DcdD( 0) <= not (A0to1(3) or A2to3(2) or A4to5(0) or A6to7(0)); + DcdD( 1) <= not (A0to1(3) or A2to3(1) or A4to5(0) or A6to7(0)); + DcdD( 2) <= not (A0to1(2) or A2to3(3) or A4to5(0) or A6to7(0)); + DcdD( 3) <= not (A0to1(1) or A2to3(3) or A4to5(0) or A6to7(0)); + DcdD( 4) <= not (A0to1(3) or A2to3(0) or A4to5(2) or A6to7(0)); + DcdD( 5) <= not (A0to1(2) or A2to3(2) or A4to5(2) or A6to7(0)); + DcdD( 6) <= not (A0to1(1) or A2to3(2) or A4to5(2) or A6to7(0)); + DcdD( 7) <= not (A0to1(2) or A2to3(1) or A4to5(2) or A6to7(0)); + DcdD( 8) <= not (A0to1(1) or A2to3(1) or A4to5(2) or A6to7(0)); + DcdD( 9) <= not (A0to1(0) or A2to3(3) or A4to5(2) or A6to7(0)); + DcdD(10) <= not (A0to1(3) or A2to3(3) or A4to5(2) or A6to7(0)); + DcdD(11) <= not (A0to1(3) or A2to3(0) or A4to5(1) or A6to7(0)); + DcdD(12) <= not (A0to1(2) or A2to3(2) or A4to5(1) or A6to7(0)); + DcdD(13) <= not (A0to1(1) or A2to3(2) or A4to5(1) or A6to7(0)); + DcdD(14) <= not (A0to1(2) or A2to3(1) or A4to5(1) or A6to7(0)); + DcdD(15) <= not (A0to1(1) or A2to3(1) or A4to5(1) or A6to7(0)); + DcdD(16) <= not (A0to1(0) or A2to3(3) or A4to5(1) or A6to7(0)); + DcdD(17) <= not (A0to1(3) or A2to3(3) or A4to5(1) or A6to7(0)); + DcdD(18) <= not (A0to1(2) or A2to3(0) or A4to5(3) or A6to7(0)); + DcdD(19) <= not (A0to1(1) or A2to3(0) or A4to5(3) or A6to7(0)); + DcdD(20) <= not (A0to1(0) or A2to3(2) or A4to5(3) or A6to7(0)); + DcdD(21) <= not (A0to1(3) or A2to3(2) or A4to5(3) or A6to7(0)); + DcdD(22) <= not (A0to1(0) or A2to3(1) or A4to5(3) or A6to7(0)); + DcdD(23) <= not (A0to1(3) or A2to3(1) or A4to5(3) or A6to7(0)); + DcdD(24) <= not (A0to1(2) or A2to3(3) or A4to5(3) or A6to7(0)); + DcdD(25) <= not (A0to1(1) or A2to3(3) or A4to5(3) or A6to7(0)); + DcdD(26) <= not (A0to1(3) or A2to3(0) or A4to5(0) or A6to7(2)); + DcdD(27) <= not (A0to1(2) or A2to3(2) or A4to5(0) or A6to7(2)); + DcdD(28) <= not (A0to1(1) or A2to3(2) or A4to5(0) or A6to7(2)); + DcdD(29) <= not (A0to1(2) or A2to3(1) or A4to5(0) or A6to7(2)); + DcdD(30) <= not (A0to1(1) or A2to3(1) or A4to5(0) or A6to7(2)); + DcdD(31) <= not (A0to1(0) or A2to3(3) or A4to5(0) or A6to7(2)); + DcdD(32) <= not (A0to1(3) or A2to3(3) or A4to5(0) or A6to7(2)); + DcdD(33) <= not (A0to1(2) or A2to3(0) or A4to5(2) or A6to7(2)); + DcdD(34) <= not (A0to1(1) or A2to3(0) or A4to5(2) or A6to7(2)); + DcdD(35) <= not (A0to1(0) or A2to3(2) or A4to5(2) or A6to7(2)); + DcdD(36) <= not (A0to1(3) or A2to3(2) or A4to5(2) or A6to7(2)); + DcdD(37) <= not (A0to1(0) or A2to3(1) or A4to5(2) or A6to7(2)); + DcdD(38) <= not (A0to1(3) or A2to3(1) or A4to5(2) or A6to7(2)); + DcdD(39) <= not (A0to1(2) or A2to3(3) or A4to5(2) or A6to7(2)); + DcdD(40) <= not (A0to1(1) or A2to3(3) or A4to5(2) or A6to7(2)); + DcdD(41) <= not (A0to1(2) or A2to3(0) or A4to5(1) or A6to7(2)); + DcdD(42) <= not (A0to1(1) or A2to3(0) or A4to5(1) or A6to7(2)); + DcdD(43) <= not (A0to1(0) or A2to3(2) or A4to5(1) or A6to7(2)); + DcdD(44) <= not (A0to1(3) or A2to3(2) or A4to5(1) or A6to7(2)); + DcdD(45) <= not (A0to1(0) or A2to3(1) or A4to5(1) or A6to7(2)); + DcdD(46) <= not (A0to1(3) or A2to3(1) or A4to5(1) or A6to7(2)); + DcdD(47) <= not (A0to1(2) or A2to3(3) or A4to5(1) or A6to7(2)); + DcdD(48) <= not (A0to1(1) or A2to3(3) or A4to5(1) or A6to7(2)); + DcdD(49) <= not (A0to1(0) or A2to3(0) or A4to5(3) or A6to7(2)); + DcdD(50) <= not (A0to1(3) or A2to3(0) or A4to5(3) or A6to7(2)); + DcdD(51) <= not (A0to1(2) or A2to3(2) or A4to5(3) or A6to7(2)); + DcdD(52) <= not (A0to1(1) or A2to3(2) or A4to5(3) or A6to7(2)); + DcdD(53) <= not (A0to1(2) or A2to3(1) or A4to5(3) or A6to7(2)); + DcdD(54) <= not (A0to1(1) or A2to3(1) or A4to5(3) or A6to7(2)); + DcdD(55) <= not (A0to1(0) or A2to3(3) or A4to5(3) or A6to7(2)); + DcdD(56) <= not (A0to1(3) or A2to3(3) or A4to5(3) or A6to7(2)); + DcdD(57) <= not (A0to1(3) or A2to3(0) or A4to5(0) or A6to7(1)); + DcdD(58) <= not (A0to1(2) or A2to3(2) or A4to5(0) or A6to7(1)); + DcdD(59) <= not (A0to1(1) or A2to3(2) or A4to5(0) or A6to7(1)); + DcdD(60) <= not (A0to1(2) or A2to3(1) or A4to5(0) or A6to7(1)); + DcdD(61) <= not (A0to1(1) or A2to3(1) or A4to5(0) or A6to7(1)); + DcdD(62) <= not (A0to1(0) or A2to3(3) or A4to5(0) or A6to7(1)); + DcdD(63) <= not (A0to1(3) or A2to3(3) or A4to5(0) or A6to7(1)); + DcdD(64) <= not (A0to1(2) or A2to3(0) or A4to5(0) or A6to7(0)); + DcdD(65) <= not (A0to1(1) or A2to3(0) or A4to5(0) or A6to7(0)); + DcdD(66) <= not (A0to1(0) or A2to3(2) or A4to5(0) or A6to7(0)); + DcdD(67) <= not (A0to1(0) or A2to3(1) or A4to5(0) or A6to7(0)); + DcdD(68) <= not (A0to1(0) or A2to3(0) or A4to5(2) or A6to7(0)); + DcdD(69) <= not (A0to1(0) or A2to3(0) or A4to5(1) or A6to7(0)); + DcdD(70) <= not (A0to1(0) or A2to3(0) or A4to5(0) or A6to7(2)); + DcdD(71) <= not (A0to1(0) or A2to3(0) or A4to5(0) or A6to7(1)); + Synzero <= not (A0to1(0) or A2to3(0) or A4to5(0) or A6to7(0)); + + CorrD(0 to 63) <= Din(0 to 63) xor DcdD(0 to 63); + + SBE_int <= '1' when DcdD(0 to 71) /= (0 to 71=>'0') else '0'; + SBE <= SBE_int; + UE <= (not SBE_int) and ((not Synzero)) and EnCorr; + +end generate; +ecc32 : if regsize = 32 generate + + signal Syn : std_ulogic_vector(0 to 6); + signal DcdD : std_ulogic_vector(0 to 38); + signal Synzero : std_ulogic; + signal SBE_int : std_ulogic; + signal A0to1 : std_ulogic_vector(0 to 3); + signal A2to3 : std_ulogic_vector(0 to 3); + signal A4to6 : std_ulogic_vector(0 to 7); + + begin + + + Syn <= not NSyn(0 to 6); + + A0to1(0) <= not (NSyn(0) and NSyn(1) and EnCorr); + A0to1(1) <= not (NSyn(0) and Syn(1) and EnCorr); + A0to1(2) <= not ( Syn(0) and NSyn(1) and EnCorr); + A0to1(3) <= not ( Syn(0) and Syn(1) and EnCorr); + + A2to3(0) <= not (NSyn(2) and NSyn(3)); + A2to3(1) <= not (NSyn(2) and Syn(3)); + A2to3(2) <= not ( Syn(2) and NSyn(3)); + A2to3(3) <= not ( Syn(2) and Syn(3)); + + A4to6(0) <= not (NSyn(4) and NSyn(5) and NSyn(6)); + A4to6(1) <= not (NSyn(4) and NSyn(5) and Syn(6)); + A4to6(2) <= not (NSyn(4) and Syn(5) and NSyn(6)); + A4to6(3) <= not (NSyn(4) and Syn(5) and Syn(6)); + A4to6(4) <= not ( Syn(4) and NSyn(5) and NSyn(6)); + A4to6(5) <= not ( Syn(4) and NSyn(5) and Syn(6)); + A4to6(6) <= not ( Syn(4) and Syn(5) and NSyn(6)); + A4to6(7) <= not ( Syn(4) and Syn(5) and Syn(6)); + + DcdD( 0) <= not (A0to1(3) or A2to3(2) or A4to6(0)); + DcdD( 1) <= not (A0to1(3) or A2to3(1) or A4to6(0)); + DcdD( 2) <= not (A0to1(2) or A2to3(3) or A4to6(0)); + DcdD( 3) <= not (A0to1(1) or A2to3(3) or A4to6(0)); + DcdD( 4) <= not (A0to1(3) or A2to3(0) or A4to6(4)); + DcdD( 5) <= not (A0to1(2) or A2to3(2) or A4to6(4)); + DcdD( 6) <= not (A0to1(1) or A2to3(2) or A4to6(4)); + DcdD( 7) <= not (A0to1(2) or A2to3(1) or A4to6(4)); + DcdD( 8) <= not (A0to1(1) or A2to3(1) or A4to6(4)); + DcdD( 9) <= not (A0to1(0) or A2to3(3) or A4to6(4)); + DcdD(10) <= not (A0to1(3) or A2to3(3) or A4to6(4)); + DcdD(11) <= not (A0to1(3) or A2to3(0) or A4to6(2)); + DcdD(12) <= not (A0to1(2) or A2to3(2) or A4to6(2)); + DcdD(13) <= not (A0to1(1) or A2to3(2) or A4to6(2)); + DcdD(14) <= not (A0to1(2) or A2to3(1) or A4to6(2)); + DcdD(15) <= not (A0to1(1) or A2to3(1) or A4to6(2)); + DcdD(16) <= not (A0to1(0) or A2to3(3) or A4to6(2)); + DcdD(17) <= not (A0to1(3) or A2to3(3) or A4to6(2)); + DcdD(18) <= not (A0to1(2) or A2to3(0) or A4to6(6)); + DcdD(19) <= not (A0to1(1) or A2to3(0) or A4to6(6)); + DcdD(20) <= not (A0to1(0) or A2to3(2) or A4to6(6)); + DcdD(21) <= not (A0to1(3) or A2to3(2) or A4to6(6)); + DcdD(22) <= not (A0to1(0) or A2to3(1) or A4to6(6)); + DcdD(23) <= not (A0to1(3) or A2to3(1) or A4to6(6)); + DcdD(24) <= not (A0to1(2) or A2to3(3) or A4to6(6)); + DcdD(25) <= not (A0to1(1) or A2to3(3) or A4to6(6)); + DcdD(26) <= not (A0to1(3) or A2to3(0) or A4to6(1)); + DcdD(27) <= not (A0to1(2) or A2to3(2) or A4to6(1)); + DcdD(28) <= not (A0to1(1) or A2to3(2) or A4to6(1)); + DcdD(29) <= not (A0to1(2) or A2to3(1) or A4to6(1)); + DcdD(30) <= not (A0to1(1) or A2to3(1) or A4to6(1)); + DcdD(31) <= not (A0to1(0) or A2to3(3) or A4to6(1)); + DcdD(32) <= not (A0to1(2) or A2to3(0) or A4to6(0)); + DcdD(33) <= not (A0to1(1) or A2to3(0) or A4to6(0)); + DcdD(34) <= not (A0to1(0) or A2to3(2) or A4to6(0)); + DcdD(35) <= not (A0to1(0) or A2to3(1) or A4to6(0)); + DcdD(36) <= not (A0to1(0) or A2to3(0) or A4to6(4)); + DcdD(37) <= not (A0to1(0) or A2to3(0) or A4to6(2)); + DcdD(38) <= not (A0to1(0) or A2to3(0) or A4to6(1)); + Synzero <= not (A0to1(0) or A2to3(0) or A4to6(0)); + + CorrD(0 to 31) <= Din(0 to 31) xor DcdD(0 to 31); + + SBE_int <= '1' when DcdD(0 to 38) /= (0 to 38=>'0') else '0'; + SBE <= SBE_int; + UE <= (not SBE_int) and ((not Synzero)) and EnCorr; + + mark_unused(A4to6(3)); + mark_unused(A4to6(5)); + mark_unused(A4to6(7)); + +end generate; + +end xuq_eccchk; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_eccgen.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_eccgen.vhdl new file mode 100644 index 0000000..8ee07d1 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_eccgen.vhdl @@ -0,0 +1,124 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee,ibm,support; +use ieee.std_logic_1164.all; +use ibm.std_ulogic_function_support.all; + +entity xuq_eccgen is +generic( + regsize : integer := 64); +port( + din : in std_ulogic_vector(0 to regsize+8-(64/regsize)); + Syn : out std_ulogic_vector(0 to 8-(64/regsize)) + ); + +-- synopsys translate_off +-- synopsys translate_on + +end xuq_eccgen; +architecture xuq_eccgen of xuq_eccgen is +begin +ecc64 : if regsize = 64 generate + + signal e : std_ulogic_vector(0 to 71); + signal l1term : std_ulogic_vector(0 to 22); + + begin + + + e(0 to 71) <= din(0 to 71); + + l1term(0) <= parity_map(e(0)&e(10)&e(17)&e(21)&e(32)&e(36)&e(44)&e(56)); + l1term(1) <= parity_map(e(22)&e(23)&e(24)&e(25)&e(53)&e(54)&e(55)&e(56)); + l1term(2) <= parity_map(e(1)&e(4)&e(11)&e(23)&e(26)&e(38)&e(46)&e(50)); + l1term(3) <= parity_map(e(2)&e(5)&e(12)&e(24)&e(27)&e(39)&e(47)&e(51)); + l1term(4) <= parity_map(e(3)&e(6)&e(13)&e(25)&e(28)&e(40)&e(48)&e(52)); + l1term(5) <= parity_map(e(7)&e(8)&e(9)&e(10)&e(37)&e(38)&e(39)&e(40)); + l1term(6) <= parity_map(e(14)&e(15)&e(16)&e(17)&e(45)&e(46)&e(47)&e(48)); + l1term(7) <= parity_map(e(18)&e(19)&e(20)&e(21)&e(49)&e(50)&e(51)&e(52)); + l1term(8) <= parity_map(e(7)&e(14)&e(18)&e(29)&e(33)&e(41)&e(53)&e(57)); + l1term(9) <= parity_map(e(58)&e(60)&e(63)&e(64)); + l1term(10) <= parity_map(e(8)&e(15)&e(19)&e(30)&e(34)&e(42)&e(54)&e(57)); + l1term(11) <= parity_map(e(59)&e(61)&e(63)&e(65)); + l1term(12) <= parity_map(e(9)&e(16)&e(20)&e(31)&e(35)&e(43)&e(55)&e(58)); + l1term(13) <= parity_map(e(59)&e(62)&e(63)&e(66)); + l1term(14) <= parity_map(e(1)&e(2)&e(3)&e(29)&e(30)&e(31)&e(32)&e(60)); + l1term(15) <= parity_map(e(61)&e(62)&e(63)&e(67)); + l1term(16) <= parity_map(e(4)&e(5)&e(6)&e(33)&e(34)&e(35)&e(36)&e(68)); + l1term(17) <= parity_map(e(11)&e(12)&e(13)&e(41)&e(42)&e(43)&e(44)&e(69)); + l1term(18) <= parity_map(e(26)&e(27)&e(28)&e(29)&e(30)&e(31)&e(32)&e(33)); + l1term(19) <= parity_map(e(34)&e(35)&e(36)&e(37)&e(38)&e(39)&e(40)&e(41)); + l1term(20) <= parity_map(e(42)&e(43)&e(44)&e(45)&e(46)&e(47)&e(48)&e(49)); + l1term(21) <= parity_map(e(50)&e(51)&e(52)&e(53)&e(54)&e(55)&e(56)&e(70)); + l1term(22) <= parity_map(e(57)&e(58)&e(59)&e(60)&e(61)&e(62)&e(63)&e(71)); + Syn(0) <= parity_map(l1term(0)&l1term(2)&l1term(3)&l1term(8)&l1term(9)); + Syn(1) <= parity_map(l1term(0)&l1term(2)&l1term(4)&l1term(10)&l1term(11)); + Syn(2) <= parity_map(l1term(0)&l1term(3)&l1term(4)&l1term(12)&l1term(13)); + Syn(3) <= parity_map(l1term(1)&l1term(5)&l1term(6)&l1term(14)&l1term(15)); + Syn(4) <= parity_map(l1term(1)&l1term(5)&l1term(7)&l1term(16)); + Syn(5) <= parity_map(l1term(1)&l1term(6)&l1term(7)&l1term(17)); + Syn(6) <= parity_map(l1term(18)&l1term(19)&l1term(20)&l1term(21)); + Syn(7) <= l1term(22); + +end generate; +ecc32 : if regsize = 32 generate + + signal e : std_ulogic_vector(0 to 38); + signal l1term : std_ulogic_vector(0 to 13); + + begin + + + e(0 to 38) <= din(0 to 38); + + l1term(0) <= parity_map(e(0)&e(1)&e(4)&e(10)&e(11)&e(17)&e(21)&e(23)); + l1term(1) <= parity_map(e(2)&e(3)&e(9)&e(10)&e(16)&e(17)&e(24)&e(25)); + l1term(2) <= parity_map(e(18)&e(19)&e(20)&e(21)&e(22)&e(23)&e(24)&e(25)); + l1term(3) <= parity_map(e(2)&e(5)&e(7)&e(12)&e(14)&e(18)&e(24)&e(26)); + l1term(4) <= parity_map(e(27)&e(29)&e(32)); + l1term(5) <= parity_map(e(3)&e(6)&e(8)&e(13)&e(15)&e(19)&e(25)&e(26)); + l1term(6) <= parity_map(e(28)&e(30)&e(33)); + l1term(7) <= parity_map(e(0)&e(5)&e(6)&e(12)&e(13)&e(20)&e(21)&e(27)); + l1term(8) <= parity_map(e(28)&e(31)&e(34)); + l1term(9) <= parity_map(e(1)&e(7)&e(8)&e(14)&e(15)&e(22)&e(23)&e(29)); + l1term(10) <= parity_map(e(30)&e(31)&e(35)); + l1term(11) <= parity_map(e(4)&e(5)&e(6)&e(7)&e(8)&e(9)&e(10)&e(36)); + l1term(12) <= parity_map(e(11)&e(12)&e(13)&e(14)&e(15)&e(16)&e(17)&e(37)); + l1term(13) <= parity_map(e(26)&e(27)&e(28)&e(29)&e(30)&e(31)&e(38)); + Syn(0) <= parity_map(l1term(0)&l1term(3)&l1term(4)); + Syn(1) <= parity_map(l1term(0)&l1term(5)&l1term(6)); + Syn(2) <= parity_map(l1term(1)&l1term(7)&l1term(8)); + Syn(3) <= parity_map(l1term(1)&l1term(9)&l1term(10)); + Syn(4) <= parity_map(l1term(2)&l1term(11)); + Syn(5) <= parity_map(l1term(2)&l1term(12)); + Syn(6) <= l1term(13); + +end generate; + +end xuq_eccgen; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_fxu_a.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_fxu_a.vhdl new file mode 100644 index 0000000..2646b60 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_fxu_a.vhdl @@ -0,0 +1,757 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +LIBRARY ieee; USE ieee.std_logic_1164.all; +LIBRARY support; + USE support.power_logic_pkg.all; +LIBRARY tri; USE tri.tri_latches_pkg.all; +LIBRARY work; USE work.xuq_pkg.mark_unused; + +entity xuq_fxu_a is + generic( + expand_type : integer := 2; + threads : integer := 4; + eff_ifar : integer := 62; + regmode : integer := 6; + regsize : integer := 64; + a2mode : integer := 1; + hvmode : integer := 1; + real_data_add : integer := 42); + port( + nclk : in clk_logic; + vdd : inout power_logic; + gnd : inout power_logic; + vcs : inout power_logic; + + an_ac_scan_dis_dc_b : in std_ulogic; + func_scan_in : in std_ulogic_vector(14 to 14); + func_scan_out : out std_ulogic_vector(14 to 14); + abst_scan_in : in std_ulogic; + abst_scan_out : out std_ulogic; + pc_xu_abist_raddr_0 : in std_ulogic_vector(2 to 9); + pc_xu_abist_raddr_1 : in std_ulogic_vector(2 to 9); + pc_xu_abist_grf_renb_0 : in std_ulogic; + pc_xu_abist_grf_renb_1 : in std_ulogic; + pc_xu_abist_ena_dc : in std_ulogic; + pc_xu_abist_waddr_0 : in std_ulogic_vector(2 to 9); + pc_xu_abist_waddr_1 : in std_ulogic_vector(2 to 9); + pc_xu_abist_grf_wenb_0 : in std_ulogic; + pc_xu_abist_grf_wenb_1 : in std_ulogic; + pc_xu_abist_di_0 : in std_ulogic_vector(0 to 3); + pc_xu_abist_di_1 : in std_ulogic_vector(0 to 3); + pc_xu_abist_wl144_comp_ena : in std_ulogic; + pc_xu_abist_raw_dc_b : in std_ulogic; + pc_xu_ccflush_dc : in std_ulogic; + bo_enable_2 : in std_ulogic; + pc_xu_bo_reset : in std_ulogic; + pc_xu_bo_unload : in std_ulogic; + pc_xu_bo_load : in std_ulogic; + pc_xu_bo_shdata : in std_ulogic; + pc_xu_bo_select : in std_ulogic_vector(0 to 1); + xu_pc_bo_fail : out std_ulogic_vector(0 to 1); + xu_pc_bo_diagout : out std_ulogic_vector(0 to 1); + clkoff_dc_b : in std_ulogic; + d_mode_dc : in std_ulogic; + delay_lclkr_dc : in std_ulogic_vector(4 to 4); + mpw1_dc_b : in std_ulogic_vector(4 to 4); + mpw2_dc_b : in std_ulogic; + an_ac_scan_diag_dc : in std_ulogic; + an_ac_lbist_ary_wrt_thru_dc : in std_ulogic; + scan_dis_dc_b : in std_ulogic; + sg_2 : in std_ulogic_vector(0 to 0); + fce_2 : in std_ulogic_vector(0 to 0); + func_sl_thold_2 : in std_ulogic_vector(0 to 0); + func_nsl_thold_2 : in std_ulogic; + abst_sl_thold_2 : in std_ulogic; + time_sl_thold_2 : in std_ulogic; + gptr_sl_thold_2 : in std_ulogic; + bolt_sl_thold_2 : in std_ulogic; + ary_nsl_thold_2 : in std_ulogic; + time_scan_in : in std_ulogic; + time_scan_out : out std_ulogic; + gptr_scan_in : in std_ulogic; + gptr_scan_out : out std_ulogic; + + iu_xu_is2_vld : in std_ulogic; + iu_xu_is2_ifar : in std_ulogic_vector(62-eff_ifar to 61); + iu_xu_is2_tid : in std_ulogic_vector(0 to threads-1); + iu_xu_is2_instr : in std_ulogic_vector(0 to 31); + iu_xu_is2_ta_vld : in std_ulogic; + iu_xu_is2_ta : in std_ulogic_vector(0 to 5); + iu_xu_is2_s1_vld : in std_ulogic; + iu_xu_is2_s1 : in std_ulogic_vector(0 to 5); + iu_xu_is2_s2_vld : in std_ulogic; + iu_xu_is2_s2 : in std_ulogic_vector(0 to 5); + iu_xu_is2_s3_vld : in std_ulogic; + iu_xu_is2_s3 : in std_ulogic_vector(0 to 5); + iu_xu_is2_axu_ld_or_st : in std_ulogic; + iu_xu_is2_axu_store : in std_ulogic; + iu_xu_is2_axu_ldst_size : in std_ulogic_vector(0 to 5); + iu_xu_is2_axu_ldst_update : in std_ulogic; + iu_xu_is2_axu_ldst_forcealign : in std_ulogic; + iu_xu_is2_axu_ldst_forceexcept : in std_ulogic; + iu_xu_is2_axu_ldst_extpid : in std_ulogic; + iu_xu_is2_axu_ldst_indexed : in std_ulogic; + iu_xu_is2_axu_ldst_tag : in std_ulogic_vector(0 to 8); + iu_xu_is2_axu_mftgpr : in std_ulogic; + iu_xu_is2_axu_mffgpr : in std_ulogic; + iu_xu_is2_axu_movedp : in std_ulogic; + iu_xu_is2_axu_instr_type : in std_ulogic_vector(0 to 2); + iu_xu_is2_pred_update : in std_ulogic; + iu_xu_is2_pred_taken_cnt : in std_ulogic_vector(0 to 1); + iu_xu_is2_error : in std_ulogic_vector(0 to 2); + iu_xu_is2_match : in std_ulogic; + iu_xu_is2_is_ucode : in std_ulogic; + iu_xu_is2_ucode_vld : in std_ulogic; + iu_xu_is2_gshare : in std_ulogic_vector(0 to 3); + xu_iu_multdiv_done : out std_ulogic_vector(0 to threads-1); + xu_iu_membar_tid : out std_ulogic_vector(0 to threads-1); + + lsu_xu_ldq_barr_done : in std_ulogic_vector(0 to threads-1); + lsu_xu_barr_done : in std_ulogic_vector(0 to threads-1); + + fxa_fxb_rf0_val : out std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_issued : out std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_ucode_val : out std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_act : out std_ulogic; + fxa_fxb_ex1_hold_ctr_flush : out std_ulogic; + fxa_fxb_rf0_instr : out std_ulogic_vector(0 to 31); + fxa_fxb_rf0_tid : out std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_ta_vld : out std_ulogic; + fxa_fxb_rf0_ta : out std_ulogic_vector(0 to 7); + fxa_fxb_rf0_error : out std_ulogic_vector(0 to 2); + fxa_fxb_rf0_match : out std_ulogic; + fxa_fxb_rf0_is_ucode : out std_ulogic; + fxa_fxb_rf0_gshare : out std_ulogic_vector(0 to 3); + fxa_fxb_rf0_ifar : out std_ulogic_vector(62-eff_ifar to 61); + fxa_fxb_rf0_s1_vld : out std_ulogic; + fxa_fxb_rf0_s1 : out std_ulogic_vector(0 to 7); + fxa_fxb_rf0_s2_vld : out std_ulogic; + fxa_fxb_rf0_s2 : out std_ulogic_vector(0 to 7); + fxa_fxb_rf0_s3_vld : out std_ulogic; + fxa_fxb_rf0_s3 : out std_ulogic_vector(0 to 7); + fxa_fxb_rf0_axu_instr_type : out std_ulogic_vector(0 to 2); + fxa_fxb_rf0_axu_ld_or_st : out std_ulogic; + fxa_fxb_rf0_axu_store : out std_ulogic; + fxa_fxb_rf0_axu_mftgpr : out std_ulogic; + fxa_fxb_rf0_axu_mffgpr : out std_ulogic; + fxa_fxb_rf0_axu_movedp : out std_ulogic; + fxa_fxb_rf0_axu_ldst_size : out std_ulogic_vector(0 to 5); + fxa_fxb_rf0_axu_ldst_update : out std_ulogic; + fxa_fxb_rf0_axu_ldst_forcealign : out std_ulogic; + fxa_fxb_rf0_axu_ldst_forceexcept : out std_ulogic; + fxa_fxb_rf0_axu_ldst_indexed : out std_ulogic; + fxa_fxb_rf0_axu_ldst_tag : out std_ulogic_vector(0 to 8); + fxa_fxb_rf0_pred_update : out std_ulogic; + fxa_fxb_rf0_pred_taken_cnt : out std_ulogic_vector(0 to 1); + fxa_fxb_rf0_mc_dep_chk_val : out std_ulogic_vector(0 to threads-1); + fxa_fxb_rf1_mul_val : out std_ulogic; + fxa_fxb_rf1_muldiv_coll : out std_ulogic; + fxa_fxb_rf1_div_val : out std_ulogic; + fxa_fxb_rf1_div_ctr : out std_ulogic_vector(0 to 7); + fxa_fxb_rf0_xu_epid_instr : out std_ulogic; + fxa_fxb_rf0_axu_is_extload : out std_ulogic; + fxa_fxb_rf0_axu_is_extstore : out std_ulogic; + fxa_fxb_rf0_spr_tid : out std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_cpl_tid : out std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_cpl_act : out std_ulogic; + fxa_fxb_rf0_is_mfocrf : out std_ulogic; + fxa_fxb_rf0_3src_instr : out std_ulogic; + fxa_fxb_rf0_gpr0_zero : out std_ulogic; + fxa_fxb_rf0_use_imm : out std_ulogic; + dec_cpl_ex3_mc_dep_chk_val : out std_ulogic_vector(0 to threads-1); + fxb_fxa_ex7_we0 : in std_ulogic; + fxb_fxa_ex7_wa0 : in std_ulogic_vector(0 to 7); + fxb_fxa_ex7_wd0 : in std_ulogic_vector(64-regsize to 63); + fxa_fxb_rf1_do0 : out std_ulogic_vector(64-regsize to 63); + fxa_fxb_rf1_do1 : out std_ulogic_vector(64-regsize to 63); + fxa_fxb_rf1_do2 : out std_ulogic_vector(64-regsize to 63); + fxb_fxa_ex6_clear_barrier : in std_ulogic_vector(0 to threads-1); + fxa_perf_muldiv_in_use : out std_ulogic; + + xu_is2_flush : in std_ulogic_vector(0 to threads-1); + xu_rf0_flush : in std_ulogic_vector(0 to threads-1); + xu_rf1_flush : in std_ulogic_vector(0 to threads-1); + xu_ex1_flush : in std_ulogic_vector(0 to threads-1); + xu_ex2_flush : in std_ulogic_vector(0 to threads-1); + xu_ex3_flush : in std_ulogic_vector(0 to threads-1); + xu_ex4_flush : in std_ulogic_vector(0 to threads-1); + xu_ex5_flush : in std_ulogic_vector(0 to threads-1); + fxa_cpl_ex2_div_coll : out std_ulogic_vector(0 to threads-1); + cpl_fxa_ex5_set_barr : in std_ulogic_vector(0 to threads-1); + fxa_iu_set_barr_tid : out std_ulogic_vector(0 to threads-1); + spr_xucr4_div_barr_thres : in std_ulogic_vector(0 to 7); + + an_ac_back_inv : in std_ulogic; + an_ac_back_inv_addr : in std_ulogic_vector(62 to 63); + an_ac_back_inv_target_bit3 : in std_ulogic; + + dec_spr_rf0_instr : out std_ulogic_vector(0 to 31); + + pc_xu_inj_regfile_parity : in std_ulogic_vector(0 to 3); + xu_pc_err_regfile_parity : out std_ulogic_vector(0 to threads-1); + xu_pc_err_regfile_ue : out std_ulogic_vector(0 to 3); + gpr_cpl_ex3_regfile_err_det : out std_ulogic; + cpl_gpr_regfile_seq_beg : in std_ulogic; + gpr_cpl_regfile_seq_end : out std_ulogic; + + xu_lsu_rf0_derat_is_extload : out std_ulogic; + xu_lsu_rf0_derat_is_extstore : out std_ulogic; + xu_lsu_rf0_derat_val : out std_ulogic_vector(0 to threads-1); + lsu_xu_rel_wren : in std_ulogic; + lsu_xu_rel_ta_gpr : in std_ulogic_vector(0 to 7); + lsu_xu_rot_rel_data : in std_ulogic_vector(64-(2**regmode) to 63+(2**regmode)/8); + + spr_xucr0_clkg_ctl_b0 : in std_ulogic; + fxa_cpl_debug : out std_ulogic_vector(0 to 272) + ); + -- synopsys translate_off + + -- synopsys translate_on +end xuq_fxu_a; + +architecture xuq_fxu_a of xuq_fxu_a is + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal func_sl_thold_1 : std_ulogic; + signal func_nsl_thold_1 : std_ulogic; + signal time_sl_thold_1 : std_ulogic; + signal gptr_sl_thold_1 : std_ulogic; + signal bolt_sl_thold_1 : std_ulogic; + signal sg_1 : std_ulogic; + signal fce_1 : std_ulogic_vector(0 to 1); + signal abst_sl_thold_1 : std_ulogic; + signal ary_nsl_thold_1 : std_ulogic; + signal func_sl_thold_0 : std_ulogic; + signal func_nsl_thold_0 : std_ulogic; + signal time_sl_thold_0 : std_ulogic; + signal gptr_sl_thold_0 : std_ulogic; + signal bolt_sl_thold_0 : std_ulogic; + signal sg_0 : std_ulogic; + signal fce_0 : std_ulogic_vector(0 to 1); + signal abst_sl_thold_0 : std_ulogic; + signal ary_nsl_thold_0 : std_ulogic; + signal func_sl_force : std_ulogic; + signal func_nsl_force : std_ulogic; + signal func_sl_thold_0_b : std_ulogic; + signal func_nsl_thold_0_b : std_ulogic; + signal func_scan_rpwr_in : std_ulogic_vector(14 to 14); + signal func_scan_rpwr_out : std_ulogic_vector(14 to 14); + signal func_scan_out_gate : std_ulogic_vector(14 to 14); + signal func_so_thold_0_b, so_force : std_ulogic; + + signal abst_sl_thold_0_b : std_ulogic; + signal abst_sl_force : std_ulogic; + signal pc_xu_abist_raddr_0_q : std_ulogic_vector(2 to 9); + signal pc_xu_abist_raddr_1_q : std_ulogic_vector(2 to 9); + signal pc_xu_abist_grf_renb_0_q : std_ulogic; + signal pc_xu_abist_grf_renb_1_q : std_ulogic; + signal pc_xu_abist_waddr_0_q : std_ulogic_vector(2 to 9); + signal pc_xu_abist_waddr_1_q : std_ulogic_vector(2 to 9); + signal pc_xu_abist_grf_wenb_0_q : std_ulogic; + signal pc_xu_abist_grf_wenb_1_q : std_ulogic; + signal pc_xu_abist_di_0_q : std_ulogic_vector(0 to 3); + signal pc_xu_abist_di_1_q : std_ulogic_vector(0 to 3); + signal pc_xu_abist_wl144_comp_ena_q : std_ulogic; + signal slat_force : std_ulogic; + signal abst_slat_thold_b : std_ulogic; + signal abst_slat_d2clk : std_ulogic; + signal abst_slat_lclk : clk_logic; + signal abist_siv : std_ulogic_vector(0 to 45); + signal abist_sov : std_ulogic_vector(0 to 45); + signal abst_scan_in_q : std_ulogic; + signal abst_scan_out_int : std_ulogic; + signal abst_scan_out_q : std_ulogic; + signal abst_scan_in_2_q : std_ulogic; + signal abst_scan_out_2_q : std_ulogic; + + signal siv_14 : std_ulogic_vector(0 to 1); + signal sov_14 : std_ulogic_vector(0 to 1); + + signal dec_gpr_rf0_re0 : std_ulogic; + signal dec_gpr_rf0_re1 : std_ulogic; + signal dec_gpr_rf0_re2 : std_ulogic; + signal dec_gpr_rf0_ra0 : std_ulogic_vector(0 to 7); + signal dec_gpr_rf0_ra1 : std_ulogic_vector(0 to 7); + signal dec_gpr_rf0_ra2 : std_ulogic_vector(0 to 7); + signal dec_gpr_rel_ta_gpr : std_ulogic_vector(0 to 7); + signal dec_gpr_rel_wren : std_ulogic; + signal gpr_rel_data : std_ulogic_vector(64-regsize to 69+regsize/8); + signal gpr_data_out_0 : std_ulogic_vector(64-regsize to 69+regsize/8); + signal gpr_data_out_1 : std_ulogic_vector(64-regsize to 69+regsize/8); + signal gpr_data_out_2 : std_ulogic_vector(64-regsize to 69+regsize/8); + signal xu_div_coll_barr_done : std_ulogic_vector(0 to threads-1); + signal xu_div_barr_done : std_ulogic_vector(0 to threads-1); + signal gpr_debug : std_ulogic_vector(0 to 21); + signal dec_debug : std_ulogic_vector(0 to 175); + signal gpr_we1_debug : std_ulogic_vector(0 to 74); + +begin + + fxa_cpl_debug <= dec_debug & gpr_debug & (0 to 74=>'0'); + + gpr_we1_debug(0 to 65) <= gpr_rel_data(0 to 63) & dec_gpr_rel_wren & dec_gpr_rel_ta_gpr(0); + gpr_we1_debug(66 to 74) <= dec_gpr_rel_wren & dec_gpr_rel_ta_gpr; + + mark_unused(gpr_we1_debug); + + xu_iu_membar_tid <= lsu_xu_ldq_barr_done or xu_div_coll_barr_done; + + xu_iu_multdiv_done <= xu_div_barr_done or fxb_fxa_ex6_clear_barrier or lsu_xu_barr_done; + + abist_reg: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 45, needs_sreset => 0) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => pc_xu_abist_ena_dc, + thold_b => abst_sl_thold_0_b, + sg => sg_0, + forcee => abst_sl_force, + delay_lclkr => delay_lclkr_dc(4), + mpw1_b => mpw1_dc_b(4), + mpw2_b => mpw2_dc_b, + d_mode => d_mode_dc, + scin => abist_siv(1 to 45), + scout => abist_sov(1 to 45), + din(0 to 7) => pc_xu_abist_raddr_0, + din(8 to 15) => pc_xu_abist_raddr_1, + din(16) => pc_xu_abist_grf_renb_0, + din(17) => pc_xu_abist_grf_renb_1, + din(18 to 25) => pc_xu_abist_waddr_0, + din(26 to 33) => pc_xu_abist_waddr_1, + din(34) => pc_xu_abist_grf_wenb_0, + din(35) => pc_xu_abist_grf_wenb_1, + din(36 to 39) => pc_xu_abist_di_0, + din(40 to 43) => pc_xu_abist_di_1, + din(44) => pc_xu_abist_wl144_comp_ena, + dout(0 to 7) => pc_xu_abist_raddr_0_q, + dout(8 to 15) => pc_xu_abist_raddr_1_q, + dout(16) => pc_xu_abist_grf_renb_0_q, + dout(17) => pc_xu_abist_grf_renb_1_q, + dout(18 to 25) => pc_xu_abist_waddr_0_q, + dout(26 to 33) => pc_xu_abist_waddr_1_q, + dout(34) => pc_xu_abist_grf_wenb_0_q, + dout(35) => pc_xu_abist_grf_wenb_1_q, + dout(36 to 39) => pc_xu_abist_di_0_q, + dout(40 to 43) => pc_xu_abist_di_1_q, + dout(44) => pc_xu_abist_wl144_comp_ena_q); + + slat_force <= sg_0; + abst_slat_thold_b <= NOT abst_sl_thold_0; + + perv_lcbs_abst: tri_lcbs + generic map (expand_type => expand_type ) + port map (vd => vdd, + gd => gnd, + delay_lclkr => delay_lclkr_dc(4), + nclk => nclk, + forcee => slat_force, + thold_b => abst_slat_thold_b, + dclk => abst_slat_d2clk, + lclk => abst_slat_lclk ); + + perv_abst_stg: tri_slat_scan + generic map (width => 4, init => (1 to 4=>'0'), expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + dclk => abst_slat_d2clk, + lclk => abst_slat_lclk, + scan_in(0) => abst_scan_in, + scan_in(1) => abst_scan_out_int, + scan_in(2) => abst_scan_in_q, + scan_in(3) => abst_scan_out_q, + scan_out(0) => abst_scan_in_q, + scan_out(1) => abst_scan_out_q, + scan_out(2) => abst_scan_in_2_q, + scan_out(3) => abst_scan_out_2_q); + + + abist_siv <= abist_sov(1 to abist_sov'right) & abst_scan_in_2_q; + abst_scan_out_int <= abist_sov(0); + abst_scan_out <= abst_scan_out_2_q and scan_dis_dc_b; + + + + perv_2to1_reg: tri_plat + generic map (width => 10, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_xu_ccflush_dc, + din(0) => abst_sl_thold_2, + din(1) => func_sl_thold_2(0), + din(2) => sg_2(0), + din(3) => fce_2(0), + din(4) => fce_2(0), + din(5) => ary_nsl_thold_2, + din(6) => time_sl_thold_2, + din(7) => gptr_sl_thold_2, + din(8) => bolt_sl_thold_2, + din(9) => func_nsl_thold_2, + q(0) => abst_sl_thold_1, + q(1) => func_sl_thold_1, + q(2) => sg_1, + q(3) => fce_1(0), + q(4) => fce_1(1), + q(5) => ary_nsl_thold_1, + q(6) => time_sl_thold_1, + q(7) => gptr_sl_thold_1, + q(8) => bolt_sl_thold_1, + q(9) => func_nsl_thold_1); + + perv_1to0_reg: tri_plat + generic map (width => 10, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_xu_ccflush_dc, + din(0) => abst_sl_thold_1, + din(1) => func_sl_thold_1, + din(2) => sg_1, + din(3) => fce_1(0), + din(4) => fce_1(1), + din(5) => ary_nsl_thold_1, + din(6) => time_sl_thold_1, + din(7) => gptr_sl_thold_1, + din(8) => bolt_sl_thold_1, + din(9) => func_nsl_thold_1, + q(0) => abst_sl_thold_0, + q(1) => func_sl_thold_0, + q(2) => sg_0, + q(3) => fce_0(0), + q(4) => fce_0(1), + q(5) => ary_nsl_thold_0, + q(6) => time_sl_thold_0, + q(7) => gptr_sl_thold_0, + q(8) => bolt_sl_thold_0, + q(9) => func_nsl_thold_0); + + perv_lcbor_func_nsl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_dc_b, + thold => func_nsl_thold_0, + sg => fce_0(0), + act_dis => tidn, + forcee => func_nsl_force, + thold_b => func_nsl_thold_0_b); + + perv_lcbor_func_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_dc_b, + thold => func_sl_thold_0, + sg => sg_0, + act_dis => tidn, + forcee => func_sl_force, + thold_b => func_sl_thold_0_b); + + perv_lcbor_abst_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_dc_b, + thold => abst_sl_thold_0, + sg => sg_0, + act_dis => tidn, + forcee => abst_sl_force, + thold_b => abst_sl_thold_0_b); + + so_force <= sg_0; + func_so_thold_0_b <= not func_sl_thold_0; + + + xu_dec_a : entity work.xuq_dec_a(xuq_dec_a) + generic map( + expand_type => expand_type, + threads => threads, + regmode => regmode, + regsize => regsize, + real_data_add => real_data_add, + eff_ifar => eff_ifar) + port map( + nclk => nclk, + vdd => vdd, + gnd => gnd, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc(4), + mpw1_dc_b => mpw1_dc_b(4), + mpw2_dc_b => mpw2_dc_b, + func_sl_force => func_sl_force, + func_sl_thold_0_b => func_sl_thold_0_b, + sg_0 => sg_0, + scan_in => siv_14(0), + scan_out => sov_14(0), + iu_xu_is2_vld => iu_xu_is2_vld, + iu_xu_is2_ifar => iu_xu_is2_ifar, + iu_xu_is2_tid => iu_xu_is2_tid, + iu_xu_is2_instr => iu_xu_is2_instr, + iu_xu_is2_ta_vld => iu_xu_is2_ta_vld, + iu_xu_is2_ta => iu_xu_is2_ta, + iu_xu_is2_s1_vld => iu_xu_is2_s1_vld, + iu_xu_is2_s1 => iu_xu_is2_s1, + iu_xu_is2_s2_vld => iu_xu_is2_s2_vld, + iu_xu_is2_s2 => iu_xu_is2_s2, + iu_xu_is2_s3_vld => iu_xu_is2_s3_vld, + iu_xu_is2_s3 => iu_xu_is2_s3, + iu_xu_is2_axu_ld_or_st => iu_xu_is2_axu_ld_or_st, + iu_xu_is2_axu_store => iu_xu_is2_axu_store, + iu_xu_is2_axu_ldst_size => iu_xu_is2_axu_ldst_size, + iu_xu_is2_axu_ldst_update => iu_xu_is2_axu_ldst_update, + iu_xu_is2_axu_ldst_forcealign => iu_xu_is2_axu_ldst_forcealign, + iu_xu_is2_axu_ldst_forceexcept => iu_xu_is2_axu_ldst_forceexcept, + iu_xu_is2_axu_ldst_extpid => iu_xu_is2_axu_ldst_extpid, + iu_xu_is2_axu_ldst_indexed => iu_xu_is2_axu_ldst_indexed, + iu_xu_is2_axu_ldst_tag => iu_xu_is2_axu_ldst_tag, + iu_xu_is2_axu_mftgpr => iu_xu_is2_axu_mftgpr, + iu_xu_is2_axu_mffgpr => iu_xu_is2_axu_mffgpr, + iu_xu_is2_axu_movedp => iu_xu_is2_axu_movedp, + iu_xu_is2_axu_instr_type => iu_xu_is2_axu_instr_type, + iu_xu_is2_pred_update => iu_xu_is2_pred_update, + iu_xu_is2_pred_taken_cnt => iu_xu_is2_pred_taken_cnt, + iu_xu_is2_error => iu_xu_is2_error, + iu_xu_is2_match => iu_xu_is2_match, + iu_xu_is2_is_ucode => iu_xu_is2_is_ucode, + iu_xu_is2_ucode_vld => iu_xu_is2_ucode_vld, + iu_xu_is2_gshare => iu_xu_is2_gshare, + xu_div_coll_barr_done => xu_div_coll_barr_done, + xu_div_barr_done => xu_div_barr_done, + dec_gpr_rf0_re0 => dec_gpr_rf0_re0, + dec_gpr_rf0_re1 => dec_gpr_rf0_re1, + dec_gpr_rf0_re2 => dec_gpr_rf0_re2, + dec_gpr_rf0_ra0 => dec_gpr_rf0_ra0, + dec_gpr_rf0_ra1 => dec_gpr_rf0_ra1, + dec_gpr_rf0_ra2 => dec_gpr_rf0_ra2, + dec_gpr_rel_ta_gpr => dec_gpr_rel_ta_gpr, + dec_gpr_rel_wren => dec_gpr_rel_wren, + fxa_fxb_rf0_val => fxa_fxb_rf0_val, + fxa_fxb_rf0_issued => fxa_fxb_rf0_issued, + fxa_fxb_rf0_ucode_val => fxa_fxb_rf0_ucode_val, + fxa_fxb_rf0_act => fxa_fxb_rf0_act, + fxa_fxb_ex1_hold_ctr_flush => fxa_fxb_ex1_hold_ctr_flush, + fxa_fxb_rf0_instr => fxa_fxb_rf0_instr, + fxa_fxb_rf0_tid => fxa_fxb_rf0_tid, + fxa_fxb_rf0_ta_vld => fxa_fxb_rf0_ta_vld, + fxa_fxb_rf0_ta => fxa_fxb_rf0_ta, + fxa_fxb_rf0_error => fxa_fxb_rf0_error, + fxa_fxb_rf0_match => fxa_fxb_rf0_match, + fxa_fxb_rf0_is_ucode => fxa_fxb_rf0_is_ucode, + fxa_fxb_rf0_gshare => fxa_fxb_rf0_gshare, + fxa_fxb_rf0_ifar => fxa_fxb_rf0_ifar, + fxa_fxb_rf0_s1_vld => fxa_fxb_rf0_s1_vld, + fxa_fxb_rf0_s1 => fxa_fxb_rf0_s1, + fxa_fxb_rf0_s2_vld => fxa_fxb_rf0_s2_vld, + fxa_fxb_rf0_s2 => fxa_fxb_rf0_s2, + fxa_fxb_rf0_s3_vld => fxa_fxb_rf0_s3_vld, + fxa_fxb_rf0_s3 => fxa_fxb_rf0_s3, + fxa_fxb_rf0_axu_instr_type => fxa_fxb_rf0_axu_instr_type, + fxa_fxb_rf0_axu_ld_or_st => fxa_fxb_rf0_axu_ld_or_st, + fxa_fxb_rf0_axu_store => fxa_fxb_rf0_axu_store, + fxa_fxb_rf0_axu_mftgpr => fxa_fxb_rf0_axu_mftgpr, + fxa_fxb_rf0_axu_mffgpr => fxa_fxb_rf0_axu_mffgpr, + fxa_fxb_rf0_axu_movedp => fxa_fxb_rf0_axu_movedp, + fxa_fxb_rf0_axu_ldst_size => fxa_fxb_rf0_axu_ldst_size, + fxa_fxb_rf0_axu_ldst_update => fxa_fxb_rf0_axu_ldst_update, + fxa_fxb_rf0_axu_ldst_forcealign => fxa_fxb_rf0_axu_ldst_forcealign, + fxa_fxb_rf0_axu_ldst_forceexcept => fxa_fxb_rf0_axu_ldst_forceexcept, + fxa_fxb_rf0_axu_ldst_indexed => fxa_fxb_rf0_axu_ldst_indexed, + fxa_fxb_rf0_axu_ldst_tag => fxa_fxb_rf0_axu_ldst_tag, + fxa_fxb_rf0_pred_update => fxa_fxb_rf0_pred_update, + fxa_fxb_rf0_pred_taken_cnt => fxa_fxb_rf0_pred_taken_cnt, + fxa_fxb_rf0_mc_dep_chk_val => fxa_fxb_rf0_mc_dep_chk_val, + fxa_fxb_rf1_mul_val => fxa_fxb_rf1_mul_val, + fxa_fxb_rf1_muldiv_coll => fxa_fxb_rf1_muldiv_coll, + fxa_fxb_rf1_div_val => fxa_fxb_rf1_div_val, + fxa_fxb_rf1_div_ctr => fxa_fxb_rf1_div_ctr, + fxa_fxb_rf0_xu_epid_instr => fxa_fxb_rf0_xu_epid_instr, + fxa_fxb_rf0_axu_is_extload => fxa_fxb_rf0_axu_is_extload, + fxa_fxb_rf0_axu_is_extstore => fxa_fxb_rf0_axu_is_extstore, + fxa_fxb_rf0_spr_tid => fxa_fxb_rf0_spr_tid, + fxa_fxb_rf0_cpl_tid => fxa_fxb_rf0_cpl_tid, + fxa_fxb_rf0_cpl_act => fxa_fxb_rf0_cpl_act, + fxa_fxb_rf0_is_mfocrf => fxa_fxb_rf0_is_mfocrf, + fxa_fxb_rf0_3src_instr => fxa_fxb_rf0_3src_instr, + fxa_fxb_rf0_gpr0_zero => fxa_fxb_rf0_gpr0_zero, + fxa_fxb_rf0_use_imm => fxa_fxb_rf0_use_imm, + dec_cpl_ex3_mc_dep_chk_val => dec_cpl_ex3_mc_dep_chk_val, + fxa_perf_muldiv_in_use => fxa_perf_muldiv_in_use, + xu_is2_flush => xu_is2_flush, + xu_rf0_flush => xu_rf0_flush, + xu_rf1_flush => xu_rf1_flush, + xu_ex1_flush => xu_ex1_flush, + xu_ex2_flush => xu_ex2_flush, + xu_ex3_flush => xu_ex3_flush, + xu_ex4_flush => xu_ex4_flush, + xu_ex5_flush => xu_ex5_flush, + fxa_cpl_ex2_div_coll => fxa_cpl_ex2_div_coll, + cpl_fxa_ex5_set_barr => cpl_fxa_ex5_set_barr, + fxa_iu_set_barr_tid => fxa_iu_set_barr_tid, + spr_xucr4_div_barr_thres => spr_xucr4_div_barr_thres, + an_ac_back_inv => an_ac_back_inv, + an_ac_back_inv_addr => an_ac_back_inv_addr, + an_ac_back_inv_target_bit3 => an_ac_back_inv_target_bit3, + dec_spr_rf0_instr => dec_spr_rf0_instr, + xu_lsu_rf0_derat_is_extload => xu_lsu_rf0_derat_is_extload, + xu_lsu_rf0_derat_is_extstore => xu_lsu_rf0_derat_is_extstore, + xu_lsu_rf0_derat_val => xu_lsu_rf0_derat_val, + lsu_xu_rel_wren => lsu_xu_rel_wren, + lsu_xu_rel_ta_gpr => lsu_xu_rel_ta_gpr, + spr_xucr0_clkg_ctl_b0 => spr_xucr0_clkg_ctl_b0, + dec_debug => dec_debug); + + gpr_rel_data <= lsu_xu_rot_rel_data & "000000"; + + xuq_fxu_gpr : entity work.xuq_fxu_gpr(xuq_fxu_gpr) + generic map( + expand_type => expand_type, + regsize => regsize, + threads => threads) + port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc(4), + clkoff_dc_b => clkoff_dc_b, + mpw1_dc_b => mpw1_dc_b(4), + mpw2_dc_b => mpw2_dc_b, + func_sl_force => func_sl_force, + func_sl_thold_0_b => func_sl_thold_0_b, + func_nsl_force => func_nsl_force, + func_nsl_thold_0_b => func_nsl_thold_0_b, + sg_0 => sg_0, + scan_in => siv_14(1), + scan_out => sov_14(1), + an_ac_scan_diag_dc => an_ac_scan_diag_dc, + + r0e_addr_abist => pc_xu_abist_raddr_0_q(2 to 9), + r1e_addr_abist => pc_xu_abist_raddr_1_q(2 to 9), + r0e_en_abist => pc_xu_abist_grf_renb_0_q, + r1e_en_abist => pc_xu_abist_grf_renb_1_q, + r0e_sel_lbist => an_ac_lbist_ary_wrt_thru_dc, + r1e_sel_lbist => an_ac_lbist_ary_wrt_thru_dc, + abist_en => pc_xu_abist_ena_dc, + lbist_en => an_ac_lbist_ary_wrt_thru_dc, + w0e_addr_abist => pc_xu_abist_waddr_0_q(2 to 9), + w0l_addr_abist => pc_xu_abist_waddr_1_q(2 to 9), + w0e_en_abist => pc_xu_abist_grf_wenb_0_q, + w0l_en_abist => pc_xu_abist_grf_wenb_1_q, + w0e_data_abist => pc_xu_abist_di_0_q, + w0l_data_abist => pc_xu_abist_di_1_q, + r0e_abist_comp_en => pc_xu_abist_wl144_comp_ena_q, + r1e_abist_comp_en => pc_xu_abist_wl144_comp_ena_q, + abist_raw_dc_b => pc_xu_abist_raw_dc_b, + + bo_enable_2 => bo_enable_2, + pc_xu_bo_reset => pc_xu_bo_reset, + pc_xu_bo_unload => pc_xu_bo_unload, + pc_xu_bo_load => pc_xu_bo_load, + pc_xu_bo_shdata => pc_xu_bo_shdata, + pc_xu_bo_select => pc_xu_bo_select, + xu_pc_bo_fail => xu_pc_bo_fail, + xu_pc_bo_diagout => xu_pc_bo_diagout, + + lcb_fce_0 => fce_0(1), + lcb_scan_diag_dc => an_ac_scan_diag_dc, + lcb_scan_dis_dc_b => scan_dis_dc_b, + lcb_sg_0 => sg_0, + lcb_abst_sl_thold_0 => abst_sl_thold_0, + lcb_ary_nsl_thold_0 => ary_nsl_thold_0, + lcb_time_sl_thold_0 => time_sl_thold_0, + lcb_gptr_sl_thold_0 => gptr_sl_thold_0, + lcb_bolt_sl_thold_0 => bolt_sl_thold_0, + + gpr_abst_scan_in => abist_siv(0), + gpr_abst_scan_out => abist_sov(0), + gpr_time_scan_in => time_scan_in, + gpr_time_scan_out => time_scan_out, + gpr_gptr_scan_in => gptr_scan_in, + gpr_gptr_scan_out => gptr_scan_out, + + pc_xu_inj_regfile_parity => pc_xu_inj_regfile_parity, + xu_pc_err_regfile_parity => xu_pc_err_regfile_parity, + xu_pc_err_regfile_ue => xu_pc_err_regfile_ue, + gpr_cpl_ex3_regfile_err_det => gpr_cpl_ex3_regfile_err_det, + cpl_gpr_regfile_seq_beg => cpl_gpr_regfile_seq_beg, + gpr_cpl_regfile_seq_end => gpr_cpl_regfile_seq_end, + + r0_en => dec_gpr_rf0_re0, + r0_addr_func => dec_gpr_rf0_ra0, + r0_data_out => gpr_data_out_0, + + r1_en => dec_gpr_rf0_re1, + r1_addr_func => dec_gpr_rf0_ra1, + r1_data_out => gpr_data_out_1, + + r2_en => dec_gpr_rf0_re2, + r2_addr_func => dec_gpr_rf0_ra2, + r2_data_out => gpr_data_out_2, + + w_e_act => fxb_fxa_ex7_we0, + w_e_addr_func => fxb_fxa_ex7_wa0, + w_e_data_func => fxb_fxa_ex7_wd0, + + w_l_act => dec_gpr_rel_wren, + w_l_addr_func => dec_gpr_rel_ta_gpr, + w_l_data_func => gpr_rel_data, + + gpr_debug => gpr_debug); + + fxa_fxb_rf1_do0 <= gpr_data_out_0(64-regsize to 63); + fxa_fxb_rf1_do1 <= gpr_data_out_1(64-regsize to 63); + fxa_fxb_rf1_do2 <= gpr_data_out_2(64-regsize to 63); + +siv_14(0 to sov_14'right) <= sov_14(1 to sov_14'right) & func_scan_rpwr_in(14); +func_scan_rpwr_out(14) <= sov_14(0); +func_scan_out(14) <= func_scan_out_gate(14) and an_ac_scan_dis_dc_b; + +func_scan_rpwr_i_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc(4), + thold_b => func_so_thold_0_b, + scin => func_scan_in(14 to 14), + scout => func_scan_rpwr_in(14 to 14), + dout => open); +func_scan_rpwr_o_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc(4), + thold_b => func_so_thold_0_b, + scin => func_scan_rpwr_out(14 to 14), + scout => func_scan_out_gate(14 to 14), + dout => open); + + +mark_unused(gpr_data_out_0(64 to 77)); +mark_unused(gpr_data_out_1(64 to 77)); +mark_unused(gpr_data_out_2(64 to 77)); + + +end architecture xuq_fxu_a; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_fxu_b.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_fxu_b.vhdl new file mode 100644 index 0000000..2e6208e --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_fxu_b.vhdl @@ -0,0 +1,1730 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +LIBRARY ieee; USE ieee.std_logic_1164.all; +LIBRARY support; + USE support.power_logic_pkg.all; +LIBRARY tri; USE tri.tri_latches_pkg.all; +LIBRARY work; USE work.xuq_pkg.all; + +entity xuq_fxu_b is + generic( + expand_type : integer := 2; + threads : integer := 4; + eff_ifar : integer := 62; + regmode : integer := 6; + regsize : integer := 64; + a2mode : integer := 1; + hvmode : integer := 1; + dc_size : natural := 14; + cl_size : natural := 6; + real_data_add : integer := 42; + fxu_synth : integer := 0); + port( + nclk : in clk_logic; + vdd : inout power_logic; + gnd : inout power_logic; + vcs : inout power_logic; + + func_scan_in : in std_ulogic_vector(54 to 58); + func_scan_out : out std_ulogic_vector(54 to 58); + an_ac_scan_dis_dc_b : in std_ulogic; + pc_xu_ccflush_dc : in std_ulogic; + clkoff_dc_b : out std_ulogic; + d_mode_dc : out std_ulogic; + delay_lclkr_dc : out std_ulogic_vector(0 to 4); + mpw1_dc_b : out std_ulogic_vector(0 to 4); + mpw2_dc_b : out std_ulogic; + g6t_clkoff_dc_b : out std_ulogic; + g6t_d_mode_dc : out std_ulogic; + g6t_delay_lclkr_dc : out std_ulogic_vector(0 to 4); + g6t_mpw1_dc_b : out std_ulogic_vector(0 to 4); + g6t_mpw2_dc_b : out std_ulogic; + g8t_clkoff_dc_b : out std_ulogic; + g8t_d_mode_dc : out std_ulogic; + g8t_delay_lclkr_dc : out std_ulogic_vector(0 to 4); + g8t_mpw1_dc_b : out std_ulogic_vector(0 to 4); + g8t_mpw2_dc_b : out std_ulogic; + cam_clkoff_dc_b : out std_ulogic; + cam_d_mode_dc : out std_ulogic; + cam_delay_lclkr_dc : out std_ulogic_vector(0 to 4); + cam_act_dis_dc : out std_ulogic; + cam_mpw1_dc_b : out std_ulogic_vector(0 to 4); + cam_mpw2_dc_b : out std_ulogic; + pc_xu_sg_3 : in std_ulogic_vector(0 to 4); + pc_xu_func_sl_thold_3 : in std_ulogic_vector(0 to 4); + pc_xu_func_slp_sl_thold_3 : in std_ulogic_vector(0 to 4); + pc_xu_func_nsl_thold_3 : in std_ulogic; + pc_xu_func_slp_nsl_thold_3 : in std_ulogic; + pc_xu_gptr_sl_thold_3 : in std_ulogic; + pc_xu_abst_sl_thold_3 : in std_ulogic; + pc_xu_abst_slp_sl_thold_3 : in std_ulogic; + pc_xu_regf_sl_thold_3 : in std_ulogic; + pc_xu_regf_slp_sl_thold_3 : in std_ulogic; + pc_xu_time_sl_thold_3 : in std_ulogic; + pc_xu_cfg_sl_thold_3 : in std_ulogic; + pc_xu_cfg_slp_sl_thold_3 : in std_ulogic; + pc_xu_ary_nsl_thold_3 : in std_ulogic; + pc_xu_ary_slp_nsl_thold_3 : in std_ulogic; + pc_xu_repr_sl_thold_3 : in std_ulogic; + pc_xu_bolt_sl_thold_3 : in std_ulogic; + pc_xu_bo_enable_3 : in std_ulogic; + pc_xu_fce_3 : in std_ulogic_vector(0 to 1); + an_ac_scan_diag_dc : in std_ulogic; + sg_2 : out std_ulogic_vector(0 to 3); + fce_2 : out std_ulogic_vector(0 to 1); + func_sl_thold_2 : out std_ulogic_vector(0 to 3); + func_slp_sl_thold_2 : out std_ulogic_vector(0 to 1); + func_nsl_thold_2 : out std_ulogic; + func_slp_nsl_thold_2 : out std_ulogic; + abst_sl_thold_2 : out std_ulogic; + abst_slp_sl_thold_2 : out std_ulogic; + time_sl_thold_2 : out std_ulogic; + gptr_sl_thold_2 : out std_ulogic; + ary_nsl_thold_2 : out std_ulogic; + ary_slp_nsl_thold_2 : out std_ulogic; + repr_sl_thold_2 : out std_ulogic; + cfg_sl_thold_2 : out std_ulogic; + cfg_slp_sl_thold_2 : out std_ulogic; + regf_slp_sl_thold_2 : out std_ulogic; + bolt_sl_thold_2 : out std_ulogic; + bo_enable_2 : out std_ulogic; + gptr_scan_in : in std_ulogic; + gptr_scan_out : out std_ulogic; + + fxa_fxb_rf0_val : in std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_issued : in std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_ucode_val : in std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_act : in std_ulogic; + fxa_fxb_ex1_hold_ctr_flush : in std_ulogic; + fxa_fxb_rf0_instr : in std_ulogic_vector(0 to 31); + fxa_fxb_rf0_tid : in std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_ta_vld : in std_ulogic; + fxa_fxb_rf0_ta : in std_ulogic_vector(0 to 7); + fxa_fxb_rf0_error : in std_ulogic_vector(0 to 2); + fxa_fxb_rf0_match : in std_ulogic; + fxa_fxb_rf0_is_ucode : in std_ulogic; + fxa_fxb_rf0_gshare : in std_ulogic_vector(0 to 3); + fxa_fxb_rf0_ifar : in std_ulogic_vector(62-eff_ifar to 61); + fxa_fxb_rf0_s1_vld : in std_ulogic; + fxa_fxb_rf0_s1 : in std_ulogic_vector(0 to 7); + fxa_fxb_rf0_s2_vld : in std_ulogic; + fxa_fxb_rf0_s2 : in std_ulogic_vector(0 to 7); + fxa_fxb_rf0_s3_vld : in std_ulogic; + fxa_fxb_rf0_s3 : in std_ulogic_vector(0 to 7); + fxa_fxb_rf0_axu_instr_type : in std_ulogic_vector(0 to 2); + fxa_fxb_rf0_axu_ld_or_st : in std_ulogic; + fxa_fxb_rf0_axu_store : in std_ulogic; + fxa_fxb_rf0_axu_ldst_forcealign : in std_ulogic; + fxa_fxb_rf0_axu_ldst_forceexcept : in std_ulogic; + fxa_fxb_rf0_axu_ldst_indexed : in std_ulogic; + fxa_fxb_rf0_axu_ldst_tag : in std_ulogic_vector(0 to 8); + fxa_fxb_rf0_axu_mftgpr : in std_ulogic; + fxa_fxb_rf0_axu_mffgpr : in std_ulogic; + fxa_fxb_rf0_axu_movedp : in std_ulogic; + fxa_fxb_rf0_axu_ldst_size : in std_ulogic_vector(0 to 5); + fxa_fxb_rf0_axu_ldst_update : in std_ulogic; + fxa_fxb_rf0_pred_update : in std_ulogic; + fxa_fxb_rf0_pred_taken_cnt : in std_ulogic_vector(0 to 1); + fxa_fxb_rf0_mc_dep_chk_val : in std_ulogic_vector(0 to threads-1); + fxa_fxb_rf1_mul_val : in std_ulogic; + fxa_fxb_rf1_div_val : in std_ulogic; + fxa_fxb_rf1_div_ctr : in std_ulogic_vector(0 to 7); + fxa_fxb_rf0_xu_epid_instr : in std_ulogic; + fxa_fxb_rf0_axu_is_extload : in std_ulogic; + fxa_fxb_rf0_axu_is_extstore : in std_ulogic; + fxa_fxb_rf0_is_mfocrf : in std_ulogic; + fxa_fxb_rf0_3src_instr : in std_ulogic; + fxa_fxb_rf0_gpr0_zero : in std_ulogic; + fxa_fxb_rf0_use_imm : in std_ulogic; + fxa_fxb_rf1_muldiv_coll : in std_ulogic; + fxb_fxa_ex7_we0 : out std_ulogic; + fxb_fxa_ex7_wa0 : out std_ulogic_vector(0 to 7); + fxb_fxa_ex7_wd0 : out std_ulogic_vector(64-regsize to 63); + fxa_fxb_rf1_do0 : in std_ulogic_vector(64-regsize to 63); + fxa_fxb_rf1_do1 : in std_ulogic_vector(64-regsize to 63); + fxa_fxb_rf1_do2 : in std_ulogic_vector(64-regsize to 63); + + xu_lsu_rf0_act : out std_ulogic; + xu_lsu_rf1_cache_acc : out std_ulogic; + xu_lsu_rf1_thrd_id : out std_ulogic_vector(0 to threads-1); + xu_lsu_rf1_optype1 : out std_ulogic; + xu_lsu_rf1_optype2 : out std_ulogic; + xu_lsu_rf1_optype4 : out std_ulogic; + xu_lsu_rf1_optype8 : out std_ulogic; + xu_lsu_rf1_optype16 : out std_ulogic; + xu_lsu_rf1_optype32 : out std_ulogic; + xu_lsu_rf1_target_gpr : out std_ulogic_vector(0 to 8); + xu_lsu_rf1_load_instr : out std_ulogic; + xu_lsu_rf1_store_instr : out std_ulogic; + xu_lsu_rf1_dcbf_instr : out std_ulogic; + xu_lsu_rf1_sync_instr : out std_ulogic; + xu_lsu_rf1_mbar_instr : out std_ulogic; + xu_lsu_rf1_l_fld : out std_ulogic_vector(0 to 1); + xu_lsu_rf1_dcbi_instr : out std_ulogic; + xu_lsu_rf1_dcbz_instr : out std_ulogic; + xu_lsu_rf1_dcbt_instr : out std_ulogic; + xu_lsu_rf1_dcbtst_instr : out std_ulogic; + xu_lsu_rf1_th_fld : out std_ulogic_vector(0 to 4); + xu_lsu_rf1_dcbtls_instr : out std_ulogic; + xu_lsu_rf1_dcbtstls_instr : out std_ulogic; + xu_lsu_rf1_dcblc_instr : out std_ulogic; + xu_lsu_rf1_dcbst_instr : out std_ulogic; + xu_lsu_rf1_icbi_instr : out std_ulogic; + xu_lsu_rf1_icblc_instr : out std_ulogic; + xu_lsu_rf1_icbt_instr : out std_ulogic; + xu_lsu_rf1_icbtls_instr : out std_ulogic; + xu_lsu_rf1_tlbsync_instr : out std_ulogic; + xu_lsu_rf1_lock_instr : out std_ulogic; + xu_lsu_rf1_mutex_hint : out std_ulogic; + xu_lsu_rf1_axu_op_val : out std_ulogic; + xu_lsu_rf1_axu_ldst_falign : out std_ulogic; + xu_lsu_rf1_axu_ldst_fexcpt : out std_ulogic; + xu_lsu_ex1_store_data : out std_ulogic_vector(64-(2**regmode) to 63); + xu_lsu_rf1_algebraic : out std_ulogic; + xu_lsu_rf1_byte_rev : out std_ulogic; + xu_lsu_rf1_src_gpr : out std_ulogic; + xu_lsu_rf1_src_axu : out std_ulogic; + xu_lsu_rf1_src_dp : out std_ulogic; + xu_lsu_rf1_targ_gpr : out std_ulogic; + xu_lsu_rf1_targ_axu : out std_ulogic; + xu_lsu_rf1_targ_dp : out std_ulogic; + xu_lsu_ex1_rotsel_ovrd : out std_ulogic_vector(0 to 4); + xu_lsu_rf1_derat_act : out std_ulogic; + xu_lsu_rf1_derat_is_load : out std_ulogic; + xu_lsu_rf1_derat_is_store : out std_ulogic; + xu_lsu_rf1_src0_vld : out std_ulogic; + xu_lsu_rf1_src0_reg : out std_ulogic_vector(0 to 7); + xu_lsu_rf1_src1_vld : out std_ulogic; + xu_lsu_rf1_src1_reg : out std_ulogic_vector(0 to 7); + xu_lsu_rf1_targ_vld : out std_ulogic; + xu_lsu_rf1_targ_reg : out std_ulogic_vector(0 to 7); + xu_bx_ex1_mtdp_val : out std_ulogic; + xu_bx_ex1_mfdp_val : out std_ulogic; + xu_bx_ex1_ipc_thrd : out std_ulogic_vector(0 to 1); + xu_bx_ex2_ipc_ba : out std_ulogic_vector(0 to 4); + xu_bx_ex2_ipc_sz : out std_ulogic_vector(0 to 1); + xu_lsu_rf1_is_touch : out std_ulogic; + xu_lsu_rf1_is_msgsnd : out std_ulogic; + xu_lsu_rf1_dci_instr : out std_ulogic; + xu_lsu_rf1_ici_instr : out std_ulogic; + xu_lsu_rf1_icswx_instr : out std_ulogic; + xu_lsu_rf1_icswx_dot_instr : out std_ulogic; + xu_lsu_rf1_icswx_epid : out std_ulogic; + xu_lsu_rf1_ldawx_instr : out std_ulogic; + xu_lsu_rf1_wclr_instr : out std_ulogic; + xu_lsu_rf1_wchk_instr : out std_ulogic; + xu_lsu_rf1_derat_ra_eq_ea : out std_ulogic; + xu_lsu_rf1_cmd_act : out std_ulogic; + xu_lsu_rf1_data_act : out std_ulogic; + xu_lsu_rf1_mtspr_trace : out std_ulogic; + lsu_xu_ex5_wren : in std_ulogic; + lsu_xu_rel_wren : in std_ulogic; + lsu_xu_rel_ta_gpr : in std_ulogic_vector(0 to 7); + lsu_xu_need_hole : in std_ulogic; + lsu_xu_rot_ex6_data_b : in std_ulogic_vector(64-(2**regmode) to 63); + lsu_xu_rot_rel_data : in std_ulogic_vector(64-(2**regmode) to 63); + xu_lsu_ex4_dvc1_en : out std_ulogic; + xu_lsu_ex4_dvc2_en : out std_ulogic; + lsu_xu_ex2_dvc1_st_cmp : in std_ulogic_vector(8-(2**regmode)/8 to 7); + lsu_xu_ex2_dvc2_st_cmp : in std_ulogic_vector(8-(2**regmode)/8 to 7); + lsu_xu_ex8_dvc1_ld_cmp : in std_ulogic_vector(8-(2**regmode)/8 to 7); + lsu_xu_ex8_dvc2_ld_cmp : in std_ulogic_vector(8-(2**regmode)/8 to 7); + lsu_xu_rel_dvc1_en : in std_ulogic; + lsu_xu_rel_dvc2_en : in std_ulogic; + lsu_xu_rel_dvc_thrd_id : in std_ulogic_vector(0 to 3); + lsu_xu_rel_dvc1_cmp : in std_ulogic_vector(8-(2**regmode)/8 to 7); + lsu_xu_rel_dvc2_cmp : in std_ulogic_vector(8-(2**regmode)/8 to 7); + xu_lsu_ex1_add_src0 : out std_ulogic_vector(64-regsize to 63); + xu_lsu_ex1_add_src1 : out std_ulogic_vector(64-regsize to 63); + + xu_ex1_eff_addr_int : out std_ulogic_vector(64-(dc_size-3) to 63); + + xu_iu_rf1_val : out std_ulogic_vector(0 to threads-1); + xu_rf1_val : out std_ulogic_vector(0 to threads-1); + xu_rf1_is_tlbre : out std_ulogic; + xu_rf1_is_tlbwe : out std_ulogic; + xu_rf1_is_tlbsx : out std_ulogic; + xu_rf1_is_tlbsrx : out std_ulogic; + xu_rf1_is_tlbilx : out std_ulogic; + xu_rf1_is_tlbivax : out std_ulogic; + xu_rf1_is_eratre : out std_ulogic; + xu_rf1_is_eratwe : out std_ulogic; + xu_rf1_is_eratsx : out std_ulogic; + xu_rf1_is_eratsrx : out std_ulogic; + xu_rf1_is_eratilx : out std_ulogic; + xu_rf1_is_erativax : out std_ulogic; + xu_ex1_is_isync : out std_ulogic; + xu_ex1_is_csync : out std_ulogic; + xu_rf1_ws : out std_ulogic_vector(0 to 1); + xu_rf1_t : out std_ulogic_vector(0 to 2); + xu_ex1_rs_is : out std_ulogic_vector(0 to 8); + xu_ex1_ra_entry : out std_ulogic_vector(7 to 11); + xu_ex1_rb : out std_ulogic_vector(64-(2**regmode) to 51); + xu_ex2_eff_addr : out std_ulogic_vector(64-(2**regmode) to 63); + xu_ex4_rs_data : out std_ulogic_vector(64-(2**regmode) to 63); + lsu_xu_ex4_tlb_data : in std_ulogic_vector(64-(2**regmode) to 63); + iu_xu_ex4_tlb_data : in std_ulogic_vector(64-(2**regmode) to 63); + + xu_mm_derat_epn : out std_ulogic_vector(62-eff_ifar to 51); + + lsu_xu_is2_back_inv : in std_ulogic; + lsu_xu_is2_back_inv_addr : in std_ulogic_vector(64-real_data_add to 63-cl_size); + + mm_xu_mmucr0_0_tlbsel : in std_ulogic_vector(4 to 5); + mm_xu_mmucr0_1_tlbsel : in std_ulogic_vector(4 to 5); + mm_xu_mmucr0_2_tlbsel : in std_ulogic_vector(4 to 5); + mm_xu_mmucr0_3_tlbsel : in std_ulogic_vector(4 to 5); + + xu_mm_rf1_is_tlbsxr : out std_ulogic; + mm_xu_cr0_eq_valid : in std_ulogic_vector(0 to threads-1); + mm_xu_cr0_eq : in std_ulogic_vector(0 to threads-1); + + fu_xu_ex4_cr_val : in std_ulogic_vector(0 to threads-1); + fu_xu_ex4_cr_noflush : in std_ulogic_vector(0 to threads-1); + fu_xu_ex4_cr0 : in std_ulogic_vector(0 to 3); + fu_xu_ex4_cr0_bf : in std_ulogic_vector(0 to 2); + fu_xu_ex4_cr1 : in std_ulogic_vector(0 to 3); + fu_xu_ex4_cr1_bf : in std_ulogic_vector(0 to 2); + fu_xu_ex4_cr2 : in std_ulogic_vector(0 to 3); + fu_xu_ex4_cr2_bf : in std_ulogic_vector(0 to 2); + fu_xu_ex4_cr3 : in std_ulogic_vector(0 to 3); + fu_xu_ex4_cr3_bf : in std_ulogic_vector(0 to 2); + + xu_pc_ram_data : out std_ulogic_vector(64-(2**regmode) to 63); + + xu_iu_ex5_val : out std_ulogic; + xu_iu_ex5_tid : out std_ulogic_vector(0 to threads-1); + xu_iu_ex5_br_update : out std_ulogic; + xu_iu_ex5_br_hist : out std_ulogic_vector(0 to 1); + xu_iu_ex5_bclr : out std_ulogic; + xu_iu_ex5_lk : out std_ulogic; + xu_iu_ex5_bh : out std_ulogic_vector(0 to 1); + xu_iu_ex6_pri : out std_ulogic_vector(0 to 2); + xu_iu_ex6_pri_val : out std_ulogic_vector(0 to 3); + xu_iu_spr_xer : out std_ulogic_vector(0 to 7*threads-1); + xu_iu_slowspr_done : out std_ulogic_vector(0 to threads-1); + xu_iu_need_hole : out std_ulogic; + fxb_fxa_ex6_clear_barrier : out std_ulogic_vector(0 to threads-1); + xu_iu_ex5_gshare : out std_ulogic_vector(0 to 3); + xu_iu_ex5_getNIA : out std_ulogic; + + an_ac_stcx_complete : in std_ulogic_vector(0 to threads-1); + an_ac_stcx_pass : in std_ulogic_vector(0 to threads-1); + + an_ac_back_inv : in std_ulogic; + an_ac_back_inv_addr : in std_ulogic_vector(58 to 63); + an_ac_back_inv_target_bit3 : in std_ulogic; + + slowspr_val_in : in std_ulogic; + slowspr_rw_in : in std_ulogic; + slowspr_etid_in : in std_ulogic_vector(0 to 1); + slowspr_addr_in : in std_ulogic_vector(0 to 9); + slowspr_data_in : in std_ulogic_vector(64-(2**regmode) to 63); + slowspr_done_in : in std_ulogic; + + an_ac_dcr_act : in std_ulogic; + an_ac_dcr_val : in std_ulogic; + an_ac_dcr_read : in std_ulogic; + an_ac_dcr_etid : in std_ulogic_vector(0 to 1); + an_ac_dcr_data : in std_ulogic_vector(64-(2**regmode) to 63); + an_ac_dcr_done : in std_ulogic; + an_ac_dcr_ack : out std_ulogic; + + lsu_xu_ex4_mtdp_cr_status : in std_ulogic; + lsu_xu_ex4_mfdp_cr_status : in std_ulogic; + + lsu_xu_ex4_cr_upd : in std_ulogic; + lsu_xu_ex5_cr_rslt : in std_ulogic; + + dec_cpl_ex3_mult_coll : out std_ulogic; + dec_cpl_ex3_axu_instr_type : out std_ulogic_vector(0 to 2); + dec_cpl_ex3_instr_hypv : out std_ulogic; + dec_cpl_rf1_ucode_val : out std_ulogic_vector(0 to threads-1); + dec_cpl_ex2_error : out std_ulogic_vector(0 to 2); + dec_cpl_ex2_match : out std_ulogic; + dec_cpl_ex2_is_ucode : out std_ulogic; + dec_cpl_rf1_ifar : out std_ulogic_vector(62-eff_ifar to 61); + dec_cpl_ex3_is_any_store : out std_ulogic; + dec_cpl_ex2_is_any_load_dac : out std_ulogic; + dec_cpl_ex3_instr_priv : out std_ulogic; + dec_cpl_ex1_epid_instr : out std_ulogic; + dec_cpl_ex2_illegal_op : out std_ulogic; + alu_cpl_ex3_trap_val : out std_ulogic; + mux_cpl_ex4_rt : out std_ulogic_vector(64-(2**regmode) to 63); + dec_cpl_ex2_is_any_store_dac : out std_ulogic; + dec_cpl_ex3_tlb_illeg : out std_ulogic; + dec_cpl_ex3_mtdp_nr : out std_ulogic; + mux_cpl_slowspr_done : out std_ulogic_vector(0 to threads-1); + mux_cpl_slowspr_flush : out std_ulogic_vector(0 to threads-1); + dec_cpl_rf1_val : out std_ulogic_vector(0 to threads-1); + dec_cpl_rf1_issued : out std_ulogic_vector(0 to threads-1); + dec_cpl_rf1_instr : out std_ulogic_vector(0 to 31); + cpl_byp_ex3_spr_rt : in std_ulogic_vector(64-(2**regmode) to 63); + byp_cpl_ex1_cr_bit : out std_ulogic; + dec_cpl_rf1_pred_taken_cnt : out std_ulogic; + dec_cpl_ex1_is_slowspr_wr : out std_ulogic; + dec_cpl_ex3_ddmh_en : out std_ulogic; + dec_cpl_ex3_back_inv : out std_ulogic; + + xu_rf1_flush : in std_ulogic_vector(0 to threads-1); + xu_ex1_flush : in std_ulogic_vector(0 to threads-1); + xu_ex2_flush : in std_ulogic_vector(0 to threads-1); + xu_ex3_flush : in std_ulogic_vector(0 to threads-1); + xu_ex4_flush : in std_ulogic_vector(0 to threads-1); + xu_ex5_flush : in std_ulogic_vector(0 to threads-1); + + dec_spr_ex4_val : out std_ulogic_vector(0 to threads-1); + mux_spr_ex2_rt : out std_ulogic_vector(64-(2**regmode) to 63); + fxu_spr_ex1_rs0 : out std_ulogic_vector(52 to 63); + fxu_spr_ex1_rs1 : out std_ulogic_vector(54 to 63); + spr_msr_cm : in std_ulogic_vector(0 to threads-1); + spr_dec_spr_xucr0_ssdly : in std_ulogic_vector(0 to 4); + spr_ccr2_en_attn : in std_ulogic; + spr_ccr2_en_ditc : in std_ulogic; + spr_ccr2_en_pc : in std_ulogic; + spr_ccr2_en_icswx : in std_ulogic; + spr_ccr2_en_dcr : in std_ulogic; + spr_dec_rf1_epcr_dgtmi : in std_ulogic_vector(0 to threads-1); + spr_dec_rf1_msr_ucle : in std_ulogic_vector(0 to threads-1); + spr_dec_rf1_msrp_uclep : in std_ulogic_vector(0 to threads-1); + spr_byp_ex4_is_mfxer : in std_ulogic_vector(0 to threads-1); + spr_byp_ex3_spr_rt : in std_ulogic_vector(64-(2**regmode) to 63); + spr_byp_ex4_is_mtxer : in std_ulogic_vector(0 to threads-1); + spr_ccr2_notlb : in std_ulogic; + dec_spr_rf1_val : out std_ulogic_vector(0 to threads-1); + fxu_spr_ex1_rs2 : out std_ulogic_vector(42 to 55); + + cpl_perf_tx_events : in std_ulogic_vector(0 to 75); + spr_perf_tx_events : in std_ulogic_vector(0 to 8*threads-1); + fxa_perf_muldiv_in_use : in std_ulogic; + xu_pc_event_data : out std_ulogic_vector(0 to 7); + + pc_xu_event_bus_enable : in std_ulogic; + pc_xu_event_count_mode : in std_ulogic_vector(0 to 2); + pc_xu_event_mux_ctrls : in std_ulogic_vector(0 to 47); + + pc_xu_trace_bus_enable : in std_ulogic; + pc_xu_instr_trace_mode : in std_ulogic; + pc_xu_instr_trace_tid : in std_ulogic_vector(0 to 1); + dec_cpl_rf1_instr_trace_val : out std_ulogic; + dec_cpl_rf1_instr_trace_type : out std_ulogic_vector(0 to 1); + dec_cpl_ex3_instr_trace_val : out std_ulogic; + xu_lsu_ex2_instr_trace_val : out std_ulogic; + cpl_dec_in_ucode : in std_ulogic_vector(0 to threads-1); + fxu_debug_mux_ctrls : in std_ulogic_vector(0 to 15); + fxu_trigger_data_in : in std_ulogic_vector(0 to 11); + fxu_debug_data_in : in std_ulogic_vector(0 to 87); + fxu_trigger_data_out : out std_ulogic_vector(0 to 11); + fxu_debug_data_out : out std_ulogic_vector(0 to 87); + lsu_xu_data_debug0 : in std_ulogic_vector(0 to 87); + lsu_xu_data_debug1 : in std_ulogic_vector(0 to 87); + lsu_xu_data_debug2 : in std_ulogic_vector(0 to 87); + + fxu_cpl_ex3_dac1r_cmpr_async : out std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac2r_cmpr_async : out std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac1r_cmpr : out std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac2r_cmpr : out std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac3r_cmpr : out std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac4r_cmpr : out std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac1w_cmpr : out std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac2w_cmpr : out std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac3w_cmpr : out std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac4w_cmpr : out std_ulogic_vector(0 to threads-1); + + spr_bit_act : in std_ulogic; + spr_msr_gs : in std_ulogic_vector(0 to threads-1); + spr_msr_ds : in std_ulogic_vector(0 to threads-1); + spr_msr_pr : in std_ulogic_vector(0 to threads-1); + spr_dbcr0_dac1 : in std_ulogic_vector(0 to 2*threads-1); + spr_dbcr0_dac2 : in std_ulogic_vector(0 to 2*threads-1); + spr_dbcr0_dac3 : in std_ulogic_vector(0 to 2*threads-1); + spr_dbcr0_dac4 : in std_ulogic_vector(0 to 2*threads-1); + spr_dbcr3_ivc : out std_ulogic_vector(0 to threads-1); + spr_xucr0_clkg_ctl : in std_ulogic_vector(2 to 2) + ); + -- synopsys translate_off + + + -- synopsys translate_on +end xuq_fxu_b; + +architecture xuq_fxu_b of xuq_fxu_b is + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal sg_2_b : std_ulogic_vector(0 to 3); + signal fce_2_b : std_ulogic_vector(0 to 1); + signal func_sl_thold_2_b : std_ulogic_vector(0 to 3); + signal func_slp_sl_thold_2_b : std_ulogic_vector(0 to 1); + signal func_slp_nsl_thold_2_b : std_ulogic; + signal func_nsl_thold_2_b : std_ulogic; + signal clkoff_dc_b_b : std_ulogic; + signal d_mode_dc_b : std_ulogic; + signal delay_lclkr_dc_b : std_ulogic_vector(0 to 4); + signal mpw1_dc_b_b : std_ulogic_vector(0 to 4); + signal mpw2_dc_b_b : std_ulogic; + + signal func_slp_sl_thold_1 : std_ulogic; + signal func_slp_nsl_thold_1 : std_ulogic; + signal func_sl_thold_1 : std_ulogic; + signal func_nsl_thold_1 : std_ulogic; + signal sg_1 : std_ulogic; + signal fce_1 : std_ulogic; + signal func_slp_sl_thold_0 : std_ulogic; + signal func_slp_nsl_thold_0 : std_ulogic; + signal func_sl_thold_0 : std_ulogic; + signal func_nsl_thold_0 : std_ulogic; + signal sg_0 : std_ulogic; + signal fce_0 : std_ulogic; + signal func_sl_force : std_ulogic; + signal func_nsl_force : std_ulogic; + signal func_sl_thold_0_b : std_ulogic; + signal func_nsl_thold_0_b : std_ulogic; + signal func_slp_sl_force : std_ulogic; + signal func_slp_sl_thold_0_b : std_ulogic; + signal func_slp_nsl_force : std_ulogic; + signal func_slp_nsl_thold_0_b : std_ulogic; + signal so_force : std_ulogic; + signal func_so_thold_0_b : std_ulogic; + + signal dec_spr_ex1_is_mfspr : std_ulogic; + signal dec_spr_ex1_is_mtspr : std_ulogic; + + signal byp_alu_ex1_rs0 : std_ulogic_vector(64-regsize to 63); + signal byp_alu_ex1_rs1 : std_ulogic_vector(64-regsize to 63); + signal alu_byp_ex2_rt : std_ulogic_vector(64-regsize to 63); + signal alu_byp_ex2_rt_b : std_ulogic_vector(64-regsize to 63); + signal alu_byp_ex1_log_rt : std_ulogic_vector(64-regsize to 63); + signal byp_spr_ex6_rt : std_ulogic_vector(64-regsize to 63); + signal byp_alu_ex1_mulsrc_0 : std_ulogic_vector(64-regsize to 63); + signal byp_alu_ex1_mulsrc_1 : std_ulogic_vector(64-regsize to 63); + signal byp_alu_ex1_divsrc_0 : std_ulogic_vector(64-regsize to 63); + signal byp_alu_ex1_divsrc_1 : std_ulogic_vector(64-regsize to 63); + signal alu_ex2_div_done : std_ulogic; + signal alu_ex3_mul_done : std_ulogic; + signal alu_ex4_mul_done : std_ulogic; + signal alu_byp_ex3_cr_div : std_ulogic_vector(0 to 4); + signal alu_byp_ex3_xer_div : std_ulogic_vector(0 to 3); + signal dec_byp_rf1_rs0_sel : std_ulogic_vector(1 to 9); + signal dec_byp_rf1_rs1_sel : std_ulogic_vector(1 to 10); + signal dec_byp_rf1_rs2_sel : std_ulogic_vector(1 to 9); + signal dec_byp_rf1_instr : std_ulogic_vector(6 to 25); + signal dec_byp_rf1_cr_so_update : std_ulogic_vector(0 to 1); + signal dec_byp_ex3_val : std_ulogic_vector(0 to threads-1); + signal dec_byp_rf1_cr_we : std_ulogic; + signal dec_byp_rf1_is_mcrf : std_ulogic; + signal dec_byp_rf1_use_crfld0 : std_ulogic; + signal dec_byp_rf1_alu_cmp : std_ulogic; + signal dec_byp_rf1_is_mtcrf : std_ulogic; + signal dec_byp_rf1_is_mtocrf : std_ulogic; + signal dec_byp_rf1_byp_val : std_ulogic_vector(1 to 3); + signal dec_byp_ex4_is_eratsxr : std_ulogic; + signal dec_byp_ex3_tlb_sel : std_ulogic_vector(0 to 1); + signal dec_alu_rf1_div_val : std_ulogic; + signal dec_alu_rf1_div_sign : std_ulogic; + signal dec_alu_rf1_div_size : std_ulogic; + signal dec_alu_rf1_div_extd : std_ulogic; + signal dec_alu_rf1_div_recform : std_ulogic; + signal dec_alu_rf1_sel : std_ulogic_vector(0 to 3); + signal dec_alu_rf1_add_rs0_inv : std_ulogic_vector(64-regsize to 63); + signal dec_alu_rf1_add_ci : std_ulogic; + signal dec_alu_rf1_is_cmpl : std_ulogic; + signal dec_alu_rf1_tw_cmpsel : std_ulogic_vector(0 to 5); + signal dec_rf1_is_isel : std_ulogic; + signal dec_alu_rf1_xer_ov_update : std_ulogic; + signal dec_alu_rf1_xer_ca_update : std_ulogic; + signal dec_alu_rf1_sh_right : std_ulogic; + signal dec_alu_rf1_sh_word : std_ulogic; + signal dec_alu_rf1_sgnxtd_byte : std_ulogic; + signal dec_alu_rf1_sgnxtd_half : std_ulogic; + signal dec_alu_rf1_sgnxtd_wd : std_ulogic; + signal dec_alu_rf1_sra_dw : std_ulogic; + signal dec_alu_rf1_sra_wd : std_ulogic; + signal dec_alu_rf1_chk_shov_dw : std_ulogic; + signal dec_alu_rf1_chk_shov_wd : std_ulogic; + signal dec_alu_rf1_use_me_ins_hi : std_ulogic; + signal dec_alu_rf1_use_me_ins_lo : std_ulogic; + signal dec_alu_rf1_use_mb_ins_hi : std_ulogic; + signal dec_alu_rf1_use_mb_ins_lo : std_ulogic; + signal dec_alu_rf1_use_me_rb_hi : std_ulogic; + signal dec_alu_rf1_use_me_rb_lo : std_ulogic; + signal dec_alu_rf1_use_mb_rb_hi : std_ulogic; + signal dec_alu_rf1_use_mb_rb_lo : std_ulogic; + signal dec_alu_rf1_use_rb_amt_hi : std_ulogic; + signal dec_alu_rf1_use_rb_amt_lo : std_ulogic; + signal dec_alu_rf1_zm_ins : std_ulogic; + signal dec_alu_rf1_log_fcn : std_ulogic_vector(0 to 3); + signal dec_alu_rf1_me_ins_b : std_ulogic_vector(0 to 5); + signal dec_alu_rf1_mb_ins : std_ulogic_vector(0 to 5); + signal dec_alu_rf1_sh_amt : std_ulogic_vector(0 to 5); + signal dec_alu_rf1_mb_gt_me : std_ulogic; + signal dec_alu_rf1_mul_recform : std_ulogic; + signal dec_alu_rf1_mul_val : std_ulogic; + signal dec_alu_rf1_mul_ret : std_ulogic; + signal dec_alu_rf1_mul_sign : std_ulogic; + signal dec_alu_rf1_mul_size : std_ulogic; + signal dec_alu_rf1_mul_imm : std_ulogic; + signal dec_alu_ex1_is_cmp : std_ulogic; + signal dec_alu_rf1_select_64bmode : std_ulogic; + signal dec_byp_rf1_imm : std_ulogic_vector(64-regsize to 63); + signal dec_rf1_tid : std_ulogic_vector(0 to threads-1); + signal dec_ex1_tid : std_ulogic_vector(0 to threads-1); + signal dec_ex2_tid : std_ulogic_vector(0 to threads-1); + signal dec_ex3_tid : std_ulogic_vector(0 to threads-1); + signal dec_ex4_tid : std_ulogic_vector(0 to threads-1); + signal dec_ex5_tid : std_ulogic_vector(0 to threads-1); + signal dec_byp_rf1_ca_used : std_ulogic; + signal dec_byp_rf1_ov_used : std_ulogic; + signal dec_byp_ex4_dp_instr : std_ulogic; + signal dec_byp_ex4_mtdp_val : std_ulogic; + signal dec_byp_ex4_mfdp_val : std_ulogic; + signal dec_byp_ex4_is_wchkall : std_ulogic; + signal dec_byp_ex1_spr_sel : std_ulogic; + signal dec_byp_ex4_is_mfcr : std_ulogic; + signal alu_byp_ex5_mul_rt : std_ulogic_vector(64-regsize to 63); + signal alu_byp_ex3_div_rt : std_ulogic_vector(64-regsize to 63); + signal alu_dec_ex1_ipb_ba : std_ulogic_vector(27 to 31); + signal alu_dec_div_need_hole : std_ulogic; + signal byp_dec_rf1_xer_ca : std_ulogic; + signal alu_byp_ex2_cr_recform : std_ulogic_vector(0 to 3); + signal alu_byp_ex5_cr_mul : std_ulogic_vector(0 to 4); + signal alu_byp_ex2_xer : std_ulogic_vector(0 to 3); + signal alu_byp_ex5_xer_mul : std_ulogic_vector(0 to 3); + signal dec_byp_ex5_instr : std_ulogic_vector(12 to 19); + signal dec_byp_rf0_act : std_ulogic; + signal ex2_is_any_store_dac : std_ulogic; + signal ex2_is_any_load_dac : std_ulogic; + signal fspr_byp_ex3_spr_rt : std_ulogic_vector(64-regsize to 63); + signal dec_fspr_ex1_instr : std_ulogic_vector(11 to 20); + signal dec_fspr_ex6_val : std_ulogic_vector(0 to threads-1); + signal byp_alu_rf1_isel_fcn : std_ulogic_vector(0 to 3); + signal dec_byp_ex4_dcr_ack : std_ulogic; + signal byp_perf_tx_events : std_ulogic_vector(0 to 3*threads-1); + signal dec_byp_ex3_instr_trace_val : std_ulogic; + signal dec_byp_ex3_instr_trace_gate : std_ulogic; + signal ex7_we0 : std_ulogic; + signal ex7_wa0 : std_ulogic_vector(0 to 7); + signal ex7_wd0 : std_ulogic_vector(64-regsize to 63); + signal dec_alu_rf1_act : std_ulogic; + signal dec_alu_ex1_act : std_ulogic; + + signal siv_54, sov_54 : std_ulogic_vector(0 to 2); + signal siv_55, sov_55 : std_ulogic_vector(0 to 2); + signal siv_56, sov_56 : std_ulogic_vector(0 to 4); + signal siv_57, sov_57 : std_ulogic_vector(0 to 3); + signal siv_58, sov_58 : std_ulogic_vector(0 to 2); + signal byp_xer_si : std_ulogic_vector(0 to 7*threads-1); + signal gpr_we0_debug : std_ulogic_vector(0 to 87); + signal byp_grp0_debug : std_ulogic_vector(0 to 87); + signal byp_grp1_debug : std_ulogic_vector(0 to 87); + signal byp_grp2_debug : std_ulogic_vector(0 to 87); + signal byp_grp3_debug : std_ulogic_vector(0 to 87); + signal byp_grp4_debug : std_ulogic_vector(0 to 87); + signal byp_grp5_debug : std_ulogic_vector(0 to 87); + signal byp_grp6_debug : std_ulogic_vector(0 to 87); + signal byp_grp7_debug : std_ulogic_vector(0 to 87); + signal byp_grp8_debug : std_ulogic_vector(22 to 87); + signal dec_grp0_debug : std_ulogic_vector(0 to 87); + signal dec_grp1_debug : std_ulogic_vector(0 to 87); + signal dbg_group0, dbg_group1, dbg_group2, dbg_group3, + dbg_group4, dbg_group5, dbg_group6, dbg_group7, + dbg_group8, dbg_group9, dbg_group10,dbg_group11, + dbg_group12,dbg_group13,dbg_group14,dbg_group15: std_ulogic_vector(0 to 87); + signal trg_group0 ,trg_group1 ,trg_group2 ,trg_group3 : std_ulogic_vector(0 to 11); + +begin + + sg_2 <= sg_2_b; + fce_2 <= fce_2_b; + func_sl_thold_2 <= func_sl_thold_2_b; + func_slp_sl_thold_2 <= func_slp_sl_thold_2_b; + func_slp_nsl_thold_2 <= func_slp_nsl_thold_2_b; + func_nsl_thold_2 <= func_nsl_thold_2_b; + clkoff_dc_b <= clkoff_dc_b_b; + d_mode_dc <= d_mode_dc_b; + delay_lclkr_dc <= delay_lclkr_dc_b; + mpw1_dc_b <= mpw1_dc_b_b; + mpw2_dc_b <= mpw2_dc_b_b; + + perv_2to1_reg: tri_plat + generic map (width => 6, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_xu_ccflush_dc, + din(0) => func_slp_sl_thold_2_b(0), + din(1) => func_slp_nsl_thold_2_b, + din(2) => func_sl_thold_2_b(0), + din(3) => func_nsl_thold_2_b, + din(4) => fce_2_b(0), + din(5) => sg_2_b(0), + q(0) => func_slp_sl_thold_1, + q(1) => func_slp_nsl_thold_1, + q(2) => func_sl_thold_1, + q(3) => func_nsl_thold_1, + q(4) => fce_1, + q(5) => sg_1 + ); + + perv_1to0_reg: tri_plat + generic map (width => 6, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_xu_ccflush_dc, + din(0) => func_slp_sl_thold_1, + din(1) => func_slp_nsl_thold_1, + din(2) => func_sl_thold_1, + din(3) => func_nsl_thold_1, + din(4) => fce_1, + din(5) => sg_1, + q(0) => func_slp_sl_thold_0, + q(1) => func_slp_nsl_thold_0, + q(2) => func_sl_thold_0, + q(3) => func_nsl_thold_0, + q(4) => fce_0, + q(5) => sg_0 + ); + + perv_lcbor_func_nsl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_dc_b_b, + thold => func_nsl_thold_0, + sg => fce_0, + act_dis => tidn, + forcee => func_nsl_force, + thold_b => func_nsl_thold_0_b); + + perv_lcbor_func_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_dc_b_b, + thold => func_sl_thold_0, + sg => sg_0, + act_dis => tidn, + forcee => func_sl_force, + thold_b => func_sl_thold_0_b); + + perv_lcbor_func_slp_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_dc_b_b, + thold => func_slp_sl_thold_0, + sg => sg_0, + act_dis => tidn, + forcee => func_slp_sl_force, + thold_b => func_slp_sl_thold_0_b); + + perv_lcbor_func_slp_nsl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_dc_b_b, + thold => func_slp_nsl_thold_0, + sg => fce_0, + act_dis => tidn, + forcee => func_slp_nsl_force, + thold_b => func_slp_nsl_thold_0_b); + + so_force <= sg_0; + func_so_thold_0_b <= not func_sl_thold_0; + dec_alu_rf1_mul_val <= fxa_fxb_rf1_mul_val; + dec_alu_rf1_div_val <= fxa_fxb_rf1_div_val; + + xu_iu_spr_xer <= byp_xer_si; + dec_cpl_ex2_is_any_store_dac <= ex2_is_any_store_dac; + dec_cpl_ex2_is_any_load_dac <= ex2_is_any_load_dac; + + xu_byp : entity work.xuq_byp(xuq_byp) + generic map( + threads => threads, + expand_type => expand_type, + regsize => regsize, + eff_ifar => eff_ifar) + port map( + nclk => nclk, + vdd => vdd, + gnd => gnd, + d_mode_dc => d_mode_dc_b, + delay_lclkr_dc => delay_lclkr_dc_b(4), + mpw1_dc_b => mpw1_dc_b_b(4), + mpw2_dc_b => mpw2_dc_b_b, + func_sl_force => func_sl_force, + func_sl_thold_0_b => func_sl_thold_0_b, + func_nsl_force => func_nsl_force, + func_nsl_thold_0_b => func_nsl_thold_0_b, + func_slp_sl_force => func_slp_sl_force, + func_slp_sl_thold_0_b => func_slp_sl_thold_0_b, + sg_0 => sg_0, + scan_in(0) => siv_55(1), + scan_in(1) => siv_56(1), + scan_out(0) => sov_55(1), + scan_out(1) => sov_56(1), + pc_xu_trace_bus_enable => pc_xu_trace_bus_enable, + dec_byp_ex3_instr_trace_val => dec_byp_ex3_instr_trace_val, + dec_byp_ex3_instr_trace_gate => dec_byp_ex3_instr_trace_gate, + fu_xu_ex4_cr_val => fu_xu_ex4_cr_val, + fu_xu_ex4_cr_noflush => fu_xu_ex4_cr_noflush, + fu_xu_ex4_cr0 => fu_xu_ex4_cr0, + fu_xu_ex4_cr0_bf => fu_xu_ex4_cr0_bf, + fu_xu_ex4_cr1 => fu_xu_ex4_cr1, + fu_xu_ex4_cr1_bf => fu_xu_ex4_cr1_bf, + fu_xu_ex4_cr2 => fu_xu_ex4_cr2, + fu_xu_ex4_cr2_bf => fu_xu_ex4_cr2_bf, + fu_xu_ex4_cr3 => fu_xu_ex4_cr3, + fu_xu_ex4_cr3_bf => fu_xu_ex4_cr3_bf, + mm_xu_cr0_eq_valid => mm_xu_cr0_eq_valid, + mm_xu_cr0_eq => mm_xu_cr0_eq, + an_ac_stcx_complete => an_ac_stcx_complete, + an_ac_stcx_pass => an_ac_stcx_pass, + an_ac_back_inv => an_ac_back_inv, + an_ac_back_inv_addr => an_ac_back_inv_addr, + an_ac_back_inv_target_bit3 => an_ac_back_inv_target_bit3, + xu_ex3_flush => xu_ex3_flush, + xu_ex4_flush => xu_ex4_flush, + xu_ex5_flush => xu_ex5_flush, + fxa_fxb_rf0_is_mfocrf => fxa_fxb_rf0_is_mfocrf, + dec_alu_rf1_sel => dec_alu_rf1_sel(2 to 2), + dec_byp_rf1_rs0_sel => dec_byp_rf1_rs0_sel, + dec_byp_rf1_rs1_sel => dec_byp_rf1_rs1_sel, + dec_byp_rf1_rs2_sel => dec_byp_rf1_rs2_sel, + dec_byp_rf1_imm => dec_byp_rf1_imm, + dec_byp_rf1_instr => dec_byp_rf1_instr, + dec_byp_rf1_cr_so_update => dec_byp_rf1_cr_so_update, + dec_byp_ex3_val => dec_byp_ex3_val, + dec_byp_rf1_cr_we => dec_byp_rf1_cr_we, + dec_byp_rf1_is_mcrf => dec_byp_rf1_is_mcrf, + dec_byp_rf1_use_crfld0 => dec_byp_rf1_use_crfld0, + dec_byp_rf1_alu_cmp => dec_byp_rf1_alu_cmp, + dec_byp_rf1_is_mtcrf => dec_byp_rf1_is_mtcrf, + dec_byp_rf1_is_mtocrf => dec_byp_rf1_is_mtocrf, + dec_byp_rf1_is_isel => dec_rf1_is_isel, + dec_byp_rf1_byp_val => dec_byp_rf1_byp_val, + dec_byp_ex4_is_eratsxr => dec_byp_ex4_is_eratsxr, + dec_rf1_tid => dec_rf1_tid, + dec_ex1_tid => dec_ex1_tid, + dec_ex2_tid => dec_ex2_tid, + dec_ex3_tid => dec_ex3_tid, + dec_ex5_tid => dec_ex5_tid, + dec_byp_rf1_ca_used => dec_byp_rf1_ca_used, + dec_byp_rf1_ov_used => dec_byp_rf1_ov_used, + dec_byp_ex4_dp_instr => dec_byp_ex4_dp_instr, + dec_byp_ex4_mtdp_val => dec_byp_ex4_mtdp_val, + dec_byp_ex4_mfdp_val => dec_byp_ex4_mfdp_val, + lsu_xu_ex4_mtdp_cr_status => lsu_xu_ex4_mtdp_cr_status, + lsu_xu_ex4_mfdp_cr_status => lsu_xu_ex4_mfdp_cr_status, + dec_byp_ex4_is_wchkall => dec_byp_ex4_is_wchkall, + lsu_xu_ex4_cr_upd => lsu_xu_ex4_cr_upd, + lsu_xu_ex5_cr_rslt => lsu_xu_ex5_cr_rslt, + fxa_fxb_rf1_do0 => fxa_fxb_rf1_do0, + fxa_fxb_rf1_do1 => fxa_fxb_rf1_do1, + fxa_fxb_rf1_do2 => fxa_fxb_rf1_do2, + spr_byp_ex4_is_mtxer => spr_byp_ex4_is_mtxer, + lsu_xu_rot_rel_data => lsu_xu_rot_rel_data, + alu_byp_ex2_cr_recform => alu_byp_ex2_cr_recform, + alu_byp_ex5_cr_mul => alu_byp_ex5_cr_mul, + alu_byp_ex3_cr_div => alu_byp_ex3_cr_div, + alu_byp_ex2_xer => alu_byp_ex2_xer, + alu_byp_ex5_xer_mul => alu_byp_ex5_xer_mul, + alu_byp_ex3_xer_div => alu_byp_ex3_xer_div, + alu_ex4_mul_done => alu_ex4_mul_done, + alu_ex2_div_done => alu_ex2_div_done, + mux_cpl_ex4_rt => mux_cpl_ex4_rt, + byp_spr_ex6_rt => byp_spr_ex6_rt, + fxb_fxa_ex7_wd0 => ex7_wd0, + xu_ex1_rs_is => xu_ex1_rs_is, + xu_ex1_ra_entry => xu_ex1_ra_entry, + xu_ex1_rb => xu_ex1_rb, + xu_lsu_ex1_store_data => xu_lsu_ex1_store_data, + fxu_spr_ex1_rs2 => fxu_spr_ex1_rs2, + fxu_spr_ex1_rs1 => fxu_spr_ex1_rs1, + fxu_spr_ex1_rs0 => fxu_spr_ex1_rs0, + byp_xer_si => byp_xer_si, + byp_dec_rf1_xer_ca => byp_dec_rf1_xer_ca, + byp_alu_ex1_rs0 => byp_alu_ex1_rs0, + byp_alu_ex1_rs1 => byp_alu_ex1_rs1, + byp_alu_ex1_mulsrc_0 => byp_alu_ex1_mulsrc_0, + byp_alu_ex1_mulsrc_1 => byp_alu_ex1_mulsrc_1, + byp_alu_ex1_divsrc_0 => byp_alu_ex1_divsrc_0, + byp_alu_ex1_divsrc_1 => byp_alu_ex1_divsrc_1, + byp_cpl_ex1_cr_bit => byp_cpl_ex1_cr_bit, + dec_byp_ex5_instr => dec_byp_ex5_instr, + dec_byp_rf0_act => dec_byp_rf0_act, + xu_lsu_ex1_add_src0 => xu_lsu_ex1_add_src0, + xu_lsu_ex1_add_src1 => xu_lsu_ex1_add_src1, + byp_alu_rf1_isel_fcn => byp_alu_rf1_isel_fcn, + spr_msr_cm => spr_msr_cm, + xu_ex4_rs_data => xu_ex4_rs_data, + dec_byp_ex1_spr_sel => dec_byp_ex1_spr_sel, + slowspr_val_in => slowspr_val_in, + slowspr_rw_in => slowspr_rw_in, + slowspr_etid_in => slowspr_etid_in, + slowspr_addr_in => slowspr_addr_in, + slowspr_data_in => slowspr_data_in, + slowspr_done_in => slowspr_done_in, + dec_byp_ex4_dcr_ack => dec_byp_ex4_dcr_ack, + an_ac_dcr_act => an_ac_dcr_act, + an_ac_dcr_read => an_ac_dcr_read, + an_ac_dcr_etid => an_ac_dcr_etid, + an_ac_dcr_data => an_ac_dcr_data, + an_ac_dcr_done => an_ac_dcr_done, + xu_iu_slowspr_done => xu_iu_slowspr_done, + mux_cpl_slowspr_done => mux_cpl_slowspr_done, + mux_cpl_slowspr_flush => mux_cpl_slowspr_flush, + lsu_xu_ex5_wren => lsu_xu_ex5_wren, + dec_byp_ex4_is_mfcr => dec_byp_ex4_is_mfcr, + spr_byp_ex4_is_mfxer => spr_byp_ex4_is_mfxer, + dec_byp_ex3_tlb_sel => dec_byp_ex3_tlb_sel, + alu_byp_ex1_log_rt => alu_byp_ex1_log_rt, + alu_byp_ex2_rt => alu_byp_ex2_rt, + cpl_byp_ex3_spr_rt => cpl_byp_ex3_spr_rt, + spr_byp_ex3_spr_rt => spr_byp_ex3_spr_rt, + fspr_byp_ex3_spr_rt => fspr_byp_ex3_spr_rt, + alu_byp_ex5_mul_rt => alu_byp_ex5_mul_rt, + alu_byp_ex3_div_rt => alu_byp_ex3_div_rt, + lsu_xu_ex4_tlb_data => lsu_xu_ex4_tlb_data, + iu_xu_ex4_tlb_data => iu_xu_ex4_tlb_data, + lsu_xu_rot_ex6_data_b => lsu_xu_rot_ex6_data_b, + xu_mm_derat_epn => xu_mm_derat_epn, + xu_pc_ram_data => xu_pc_ram_data, + byp_perf_tx_events => byp_perf_tx_events, + byp_grp0_debug => byp_grp0_debug, + byp_grp1_debug => byp_grp1_debug, + byp_grp2_debug => byp_grp2_debug, + byp_grp3_debug => byp_grp3_debug(15 to 87), + byp_grp4_debug => byp_grp4_debug(14 to 87), + byp_grp5_debug => byp_grp5_debug(15 to 87), + byp_grp6_debug => byp_grp6_debug, + byp_grp7_debug => byp_grp7_debug, + byp_grp8_debug => byp_grp8_debug + ); + + xu_dec_b : entity work.xuq_dec_b(xuq_dec_b) + generic map( + expand_type => expand_type, + threads => threads, + regmode => regmode, + regsize => regsize, + cl_size => cl_size, + real_data_add => real_data_add, + eff_ifar => eff_ifar) + port map( + nclk => nclk, + vdd => vdd, + gnd => gnd, + d_mode_dc => d_mode_dc_b, + delay_lclkr_dc => delay_lclkr_dc_b(4), + mpw1_dc_b => mpw1_dc_b_b(4), + mpw2_dc_b => mpw2_dc_b_b, + func_nsl_force => func_nsl_force, + func_nsl_thold_0_b => func_nsl_thold_0_b, + func_sl_force => func_sl_force, + func_sl_thold_0_b => func_sl_thold_0_b, + func_slp_sl_force => func_slp_sl_force, + func_slp_sl_thold_0_b => func_slp_sl_thold_0_b, + func_slp_nsl_force => func_slp_nsl_force, + func_slp_nsl_thold_0_b => func_slp_nsl_thold_0_b, + sg_0 => sg_0, + scan_in => siv_54(1), + scan_out => sov_54(1), + pc_xu_trace_bus_enable => pc_xu_trace_bus_enable, + pc_xu_instr_trace_mode => pc_xu_instr_trace_mode, + pc_xu_instr_trace_tid => pc_xu_instr_trace_tid, + dec_byp_ex3_instr_trace_val => dec_byp_ex3_instr_trace_val, + dec_byp_ex3_instr_trace_gate => dec_byp_ex3_instr_trace_gate, + dec_cpl_rf1_instr_trace_val => dec_cpl_rf1_instr_trace_val, + dec_cpl_rf1_instr_trace_type => dec_cpl_rf1_instr_trace_type, + dec_cpl_ex3_instr_trace_val => dec_cpl_ex3_instr_trace_val, + xu_lsu_ex2_instr_trace_val => xu_lsu_ex2_instr_trace_val, + cpl_dec_in_ucode => cpl_dec_in_ucode, + slowspr_val_in => slowspr_val_in, + slowspr_rw_in => slowspr_rw_in, + slowspr_etid_in => slowspr_etid_in, + dec_byp_ex4_dcr_ack => dec_byp_ex4_dcr_ack, + an_ac_dcr_act => an_ac_dcr_act, + an_ac_dcr_val => an_ac_dcr_val, + an_ac_dcr_read => an_ac_dcr_read, + an_ac_dcr_etid => an_ac_dcr_etid, + an_ac_dcr_ack => an_ac_dcr_ack, + mm_xu_mmucr0_0_tlbsel => mm_xu_mmucr0_0_tlbsel, + mm_xu_mmucr0_1_tlbsel => mm_xu_mmucr0_1_tlbsel, + mm_xu_mmucr0_2_tlbsel => mm_xu_mmucr0_2_tlbsel, + mm_xu_mmucr0_3_tlbsel => mm_xu_mmucr0_3_tlbsel, + xu_mm_rf1_is_tlbsxr => xu_mm_rf1_is_tlbsxr, + fxb_fxa_ex7_we0 => ex7_we0, + fxb_fxa_ex7_wa0 => ex7_wa0, + dec_byp_ex4_is_mfcr => dec_byp_ex4_is_mfcr, + dec_byp_ex3_tlb_sel => dec_byp_ex3_tlb_sel, + xu_rf1_flush => xu_rf1_flush, + xu_ex1_flush => xu_ex1_flush, + xu_ex2_flush => xu_ex2_flush, + xu_ex3_flush => xu_ex3_flush, + xu_ex4_flush => xu_ex4_flush, + xu_ex5_flush => xu_ex5_flush, + fxa_fxb_rf0_val => fxa_fxb_rf0_val, + fxa_fxb_rf0_issued => fxa_fxb_rf0_issued, + fxa_fxb_rf0_ucode_val => fxa_fxb_rf0_ucode_val, + fxa_fxb_rf0_act => fxa_fxb_rf0_act, + fxa_fxb_rf0_instr => fxa_fxb_rf0_instr, + fxa_fxb_rf0_tid => fxa_fxb_rf0_tid, + fxa_fxb_rf0_ta_vld => fxa_fxb_rf0_ta_vld, + fxa_fxb_rf0_ta => fxa_fxb_rf0_ta, + fxa_fxb_rf0_error => fxa_fxb_rf0_error, + fxa_fxb_rf0_match => fxa_fxb_rf0_match, + fxa_fxb_rf0_is_ucode => fxa_fxb_rf0_is_ucode, + fxa_fxb_rf0_gshare => fxa_fxb_rf0_gshare, + fxa_fxb_rf0_ifar => fxa_fxb_rf0_ifar, + fxa_fxb_rf0_s1_vld => fxa_fxb_rf0_s1_vld, + fxa_fxb_rf0_s1 => fxa_fxb_rf0_s1, + fxa_fxb_rf0_s2_vld => fxa_fxb_rf0_s2_vld, + fxa_fxb_rf0_s2 => fxa_fxb_rf0_s2, + fxa_fxb_rf0_s3_vld => fxa_fxb_rf0_s3_vld, + fxa_fxb_rf0_s3 => fxa_fxb_rf0_s3, + fxa_fxb_rf0_axu_instr_type => fxa_fxb_rf0_axu_instr_type, + fxa_fxb_rf0_axu_ld_or_st => fxa_fxb_rf0_axu_ld_or_st, + fxa_fxb_rf0_axu_store => fxa_fxb_rf0_axu_store, + fxa_fxb_rf0_axu_ldst_forcealign => fxa_fxb_rf0_axu_ldst_forcealign, + fxa_fxb_rf0_axu_ldst_forceexcept => fxa_fxb_rf0_axu_ldst_forceexcept, + fxa_fxb_rf0_axu_ldst_indexed => fxa_fxb_rf0_axu_ldst_indexed, + fxa_fxb_rf0_axu_ldst_tag => fxa_fxb_rf0_axu_ldst_tag, + fxa_fxb_rf0_axu_mftgpr => fxa_fxb_rf0_axu_mftgpr, + fxa_fxb_rf0_axu_mffgpr => fxa_fxb_rf0_axu_mffgpr, + fxa_fxb_rf0_axu_movedp => fxa_fxb_rf0_axu_movedp, + fxa_fxb_rf0_axu_ldst_size => fxa_fxb_rf0_axu_ldst_size, + fxa_fxb_rf0_axu_ldst_update => fxa_fxb_rf0_axu_ldst_update, + fxa_fxb_rf0_pred_update => fxa_fxb_rf0_pred_update, + fxa_fxb_rf0_pred_taken_cnt => fxa_fxb_rf0_pred_taken_cnt, + fxa_fxb_rf0_mc_dep_chk_val => fxa_fxb_rf0_mc_dep_chk_val, + fxa_fxb_rf0_xu_epid_instr => fxa_fxb_rf0_xu_epid_instr, + fxa_fxb_rf0_axu_is_extload => fxa_fxb_rf0_axu_is_extload, + fxa_fxb_rf0_axu_is_extstore => fxa_fxb_rf0_axu_is_extstore, + fxa_fxb_rf0_3src_instr => fxa_fxb_rf0_3src_instr, + fxa_fxb_rf0_gpr0_zero => fxa_fxb_rf0_gpr0_zero, + fxa_fxb_rf0_use_imm => fxa_fxb_rf0_use_imm, + fxa_fxb_rf1_muldiv_coll => fxa_fxb_rf1_muldiv_coll, + alu_dec_ex1_ipb_ba => alu_dec_ex1_ipb_ba, + alu_dec_div_need_hole => alu_dec_div_need_hole, + dec_byp_rf1_rs0_sel => dec_byp_rf1_rs0_sel, + dec_byp_rf1_rs1_sel => dec_byp_rf1_rs1_sel, + dec_byp_rf1_rs2_sel => dec_byp_rf1_rs2_sel, + dec_byp_rf1_instr => dec_byp_rf1_instr, + dec_byp_rf1_cr_so_update => dec_byp_rf1_cr_so_update, + dec_byp_ex3_val => dec_byp_ex3_val, + dec_byp_rf1_cr_we => dec_byp_rf1_cr_we, + dec_byp_rf1_is_mcrf => dec_byp_rf1_is_mcrf, + dec_byp_rf1_use_crfld0 => dec_byp_rf1_use_crfld0, + dec_byp_rf1_alu_cmp => dec_byp_rf1_alu_cmp, + dec_byp_rf1_is_mtcrf => dec_byp_rf1_is_mtcrf, + dec_byp_rf1_is_mtocrf => dec_byp_rf1_is_mtocrf, + dec_byp_rf1_byp_val => dec_byp_rf1_byp_val, + dec_byp_ex4_is_eratsxr => dec_byp_ex4_is_eratsxr, + dec_byp_rf1_ca_used => dec_byp_rf1_ca_used, + dec_byp_rf1_ov_used => dec_byp_rf1_ov_used, + dec_byp_ex4_dp_instr => dec_byp_ex4_dp_instr, + dec_byp_ex4_mtdp_val => dec_byp_ex4_mtdp_val, + dec_byp_ex4_mfdp_val => dec_byp_ex4_mfdp_val, + dec_byp_ex4_is_wchkall => dec_byp_ex4_is_wchkall, + dec_alu_rf1_act => dec_alu_rf1_act, + dec_alu_ex1_act => dec_alu_ex1_act, + dec_alu_rf1_sel => dec_alu_rf1_sel, + dec_alu_rf1_add_rs0_inv => dec_alu_rf1_add_rs0_inv, + dec_alu_rf1_add_ci => dec_alu_rf1_add_ci, + dec_alu_rf1_is_cmpl => dec_alu_rf1_is_cmpl, + dec_alu_rf1_tw_cmpsel => dec_alu_rf1_tw_cmpsel, + dec_rf1_is_isel => dec_rf1_is_isel, + dec_alu_rf1_xer_ov_update => dec_alu_rf1_xer_ov_update, + dec_alu_rf1_xer_ca_update => dec_alu_rf1_xer_ca_update, + dec_alu_rf1_sh_right => dec_alu_rf1_sh_right, + dec_alu_rf1_sh_word => dec_alu_rf1_sh_word, + dec_alu_rf1_sgnxtd_byte => dec_alu_rf1_sgnxtd_byte, + dec_alu_rf1_sgnxtd_half => dec_alu_rf1_sgnxtd_half, + dec_alu_rf1_sgnxtd_wd => dec_alu_rf1_sgnxtd_wd, + dec_alu_rf1_sra_dw => dec_alu_rf1_sra_dw, + dec_alu_rf1_sra_wd => dec_alu_rf1_sra_wd, + dec_alu_rf1_chk_shov_dw => dec_alu_rf1_chk_shov_dw, + dec_alu_rf1_chk_shov_wd => dec_alu_rf1_chk_shov_wd, + dec_alu_rf1_use_me_ins_hi => dec_alu_rf1_use_me_ins_hi, + dec_alu_rf1_use_me_ins_lo => dec_alu_rf1_use_me_ins_lo, + dec_alu_rf1_use_mb_ins_hi => dec_alu_rf1_use_mb_ins_hi, + dec_alu_rf1_use_mb_ins_lo => dec_alu_rf1_use_mb_ins_lo, + dec_alu_rf1_use_me_rb_hi => dec_alu_rf1_use_me_rb_hi, + dec_alu_rf1_use_me_rb_lo => dec_alu_rf1_use_me_rb_lo, + dec_alu_rf1_use_mb_rb_hi => dec_alu_rf1_use_mb_rb_hi, + dec_alu_rf1_use_mb_rb_lo => dec_alu_rf1_use_mb_rb_lo, + dec_alu_rf1_use_rb_amt_hi => dec_alu_rf1_use_rb_amt_hi, + dec_alu_rf1_use_rb_amt_lo => dec_alu_rf1_use_rb_amt_lo, + dec_alu_rf1_zm_ins => dec_alu_rf1_zm_ins, + dec_alu_rf1_log_fcn => dec_alu_rf1_log_fcn, + dec_alu_rf1_me_ins_b => dec_alu_rf1_me_ins_b, + dec_alu_rf1_mb_ins => dec_alu_rf1_mb_ins, + dec_alu_rf1_sh_amt => dec_alu_rf1_sh_amt, + dec_alu_rf1_mb_gt_me => dec_alu_rf1_mb_gt_me, + alu_ex3_mul_done => alu_ex3_mul_done, + alu_ex2_div_done => alu_ex2_div_done, + dec_alu_rf1_mul_recform => dec_alu_rf1_mul_recform, + dec_alu_rf1_div_recform => dec_alu_rf1_div_recform, + dec_alu_rf1_mul_ret => dec_alu_rf1_mul_ret, + dec_alu_rf1_mul_sign => dec_alu_rf1_mul_sign, + dec_alu_rf1_mul_size => dec_alu_rf1_mul_size, + dec_alu_rf1_mul_imm => dec_alu_rf1_mul_imm, + dec_alu_rf1_div_sign => dec_alu_rf1_div_sign, + dec_alu_rf1_div_size => dec_alu_rf1_div_size, + dec_alu_rf1_div_extd => dec_alu_rf1_div_extd, + dec_alu_ex1_is_cmp => dec_alu_ex1_is_cmp, + dec_alu_rf1_select_64bmode => dec_alu_rf1_select_64bmode, + dec_cpl_rf1_ifar => dec_cpl_rf1_ifar, + dec_byp_rf1_imm => dec_byp_rf1_imm, + dec_rf1_tid => dec_rf1_tid, + dec_ex1_tid => dec_ex1_tid, + dec_ex2_tid => dec_ex2_tid, + dec_ex3_tid => dec_ex3_tid, + dec_ex4_tid => dec_ex4_tid, + dec_ex5_tid => dec_ex5_tid, + dec_byp_ex1_spr_sel => dec_byp_ex1_spr_sel, + dec_spr_ex1_is_mtspr => dec_spr_ex1_is_mtspr, + dec_spr_ex1_is_mfspr => dec_spr_ex1_is_mfspr, + dec_cpl_rf1_val => dec_cpl_rf1_val, + dec_cpl_rf1_issued => dec_cpl_rf1_issued, + dec_spr_rf1_val => dec_spr_rf1_val, + dec_spr_ex4_val => dec_spr_ex4_val, + dec_fspr_ex1_instr => dec_fspr_ex1_instr, + dec_fspr_ex6_val => dec_fspr_ex6_val, + dec_cpl_rf1_instr => dec_cpl_rf1_instr, + dec_cpl_rf1_pred_taken_cnt => dec_cpl_rf1_pred_taken_cnt, + dec_cpl_ex1_is_slowspr_wr => dec_cpl_ex1_is_slowspr_wr, + dec_cpl_ex3_ddmh_en => dec_cpl_ex3_ddmh_en, + dec_cpl_ex3_back_inv => dec_cpl_ex3_back_inv, + dec_cpl_ex2_error => dec_cpl_ex2_error, + dec_cpl_ex2_match => dec_cpl_ex2_match, + dec_cpl_ex2_is_ucode => dec_cpl_ex2_is_ucode, + dec_cpl_ex3_is_any_store => dec_cpl_ex3_is_any_store, + ex2_is_any_store_dac => ex2_is_any_store_dac, + ex2_is_any_load_dac => ex2_is_any_load_dac, + dec_cpl_ex3_instr_priv => dec_cpl_ex3_instr_priv, + dec_cpl_ex1_epid_instr => dec_cpl_ex1_epid_instr, + dec_cpl_ex2_illegal_op => dec_cpl_ex2_illegal_op, + dec_cpl_ex3_mtdp_nr => dec_cpl_ex3_mtdp_nr, + dec_cpl_ex3_mult_coll => dec_cpl_ex3_mult_coll, + dec_cpl_ex3_tlb_illeg => dec_cpl_ex3_tlb_illeg, + dec_cpl_ex3_axu_instr_type => dec_cpl_ex3_axu_instr_type, + dec_cpl_ex3_instr_hypv => dec_cpl_ex3_instr_hypv, + dec_cpl_rf1_ucode_val => dec_cpl_rf1_ucode_val, + byp_dec_rf1_xer_ca => byp_dec_rf1_xer_ca, + spr_dec_rf1_epcr_dgtmi => spr_dec_rf1_epcr_dgtmi, + spr_dec_rf1_msr_ucle => spr_dec_rf1_msr_ucle, + spr_dec_rf1_msrp_uclep => spr_dec_rf1_msrp_uclep, + xu_lsu_rf0_act => xu_lsu_rf0_act, + xu_lsu_rf1_cache_acc => xu_lsu_rf1_cache_acc, + xu_lsu_rf1_axu_op_val => xu_lsu_rf1_axu_op_val, + xu_lsu_rf1_axu_ldst_falign => xu_lsu_rf1_axu_ldst_falign, + xu_lsu_rf1_axu_ldst_fexcpt => xu_lsu_rf1_axu_ldst_fexcpt, + xu_lsu_rf1_thrd_id => xu_lsu_rf1_thrd_id, + xu_lsu_rf1_optype1 => xu_lsu_rf1_optype1, + xu_lsu_rf1_optype2 => xu_lsu_rf1_optype2, + xu_lsu_rf1_optype4 => xu_lsu_rf1_optype4, + xu_lsu_rf1_optype8 => xu_lsu_rf1_optype8, + xu_lsu_rf1_optype16 => xu_lsu_rf1_optype16, + xu_lsu_rf1_optype32 => xu_lsu_rf1_optype32, + xu_lsu_rf1_target_gpr => xu_lsu_rf1_target_gpr, + xu_lsu_rf1_load_instr => xu_lsu_rf1_load_instr, + xu_lsu_rf1_store_instr => xu_lsu_rf1_store_instr, + xu_lsu_rf1_dcbf_instr => xu_lsu_rf1_dcbf_instr, + xu_lsu_rf1_sync_instr => xu_lsu_rf1_sync_instr, + xu_lsu_rf1_mbar_instr => xu_lsu_rf1_mbar_instr, + xu_lsu_rf1_l_fld => xu_lsu_rf1_l_fld, + xu_lsu_rf1_dcbi_instr => xu_lsu_rf1_dcbi_instr, + xu_lsu_rf1_dcbz_instr => xu_lsu_rf1_dcbz_instr, + xu_lsu_rf1_dcbt_instr => xu_lsu_rf1_dcbt_instr, + xu_lsu_rf1_dcbtst_instr => xu_lsu_rf1_dcbtst_instr, + xu_lsu_rf1_th_fld => xu_lsu_rf1_th_fld, + xu_lsu_rf1_dcbtls_instr => xu_lsu_rf1_dcbtls_instr, + xu_lsu_rf1_dcbtstls_instr => xu_lsu_rf1_dcbtstls_instr, + xu_lsu_rf1_dcblc_instr => xu_lsu_rf1_dcblc_instr, + xu_lsu_rf1_dcbst_instr => xu_lsu_rf1_dcbst_instr, + xu_lsu_rf1_icbi_instr => xu_lsu_rf1_icbi_instr, + xu_lsu_rf1_icblc_instr => xu_lsu_rf1_icblc_instr, + xu_lsu_rf1_icbt_instr => xu_lsu_rf1_icbt_instr, + xu_lsu_rf1_icbtls_instr => xu_lsu_rf1_icbtls_instr, + xu_lsu_rf1_tlbsync_instr => xu_lsu_rf1_tlbsync_instr, + xu_lsu_rf1_lock_instr => xu_lsu_rf1_lock_instr, + xu_lsu_rf1_mutex_hint => xu_lsu_rf1_mutex_hint, + xu_lsu_rf1_algebraic => xu_lsu_rf1_algebraic, + xu_lsu_rf1_byte_rev => xu_lsu_rf1_byte_rev, + xu_lsu_rf1_src_gpr => xu_lsu_rf1_src_gpr, + xu_lsu_rf1_src_axu => xu_lsu_rf1_src_axu, + xu_lsu_rf1_src_dp => xu_lsu_rf1_src_dp, + xu_lsu_rf1_targ_gpr => xu_lsu_rf1_targ_gpr, + xu_lsu_rf1_targ_axu => xu_lsu_rf1_targ_axu, + xu_lsu_rf1_targ_dp => xu_lsu_rf1_targ_dp, + xu_lsu_ex1_rotsel_ovrd => xu_lsu_ex1_rotsel_ovrd, + lsu_xu_ex5_wren => lsu_xu_ex5_wren, + lsu_xu_rel_wren => lsu_xu_rel_wren, + lsu_xu_rel_ta_gpr => lsu_xu_rel_ta_gpr, + lsu_xu_need_hole => lsu_xu_need_hole, + xu_lsu_rf1_src0_vld => xu_lsu_rf1_src0_vld, + xu_lsu_rf1_src0_reg => xu_lsu_rf1_src0_reg, + xu_lsu_rf1_src1_vld => xu_lsu_rf1_src1_vld, + xu_lsu_rf1_src1_reg => xu_lsu_rf1_src1_reg, + xu_lsu_rf1_targ_vld => xu_lsu_rf1_targ_vld, + xu_lsu_rf1_targ_reg => xu_lsu_rf1_targ_reg, + xu_bx_ex1_mtdp_val => xu_bx_ex1_mtdp_val, + xu_bx_ex1_mfdp_val => xu_bx_ex1_mfdp_val, + xu_bx_ex1_ipc_thrd => xu_bx_ex1_ipc_thrd, + xu_bx_ex2_ipc_ba => xu_bx_ex2_ipc_ba, + xu_bx_ex2_ipc_sz => xu_bx_ex2_ipc_sz, + xu_lsu_rf1_is_touch => xu_lsu_rf1_is_touch, + xu_lsu_rf1_is_msgsnd => xu_lsu_rf1_is_msgsnd, + xu_lsu_rf1_dci_instr => xu_lsu_rf1_dci_instr, + xu_lsu_rf1_ici_instr => xu_lsu_rf1_ici_instr, + xu_lsu_rf1_icswx_instr => xu_lsu_rf1_icswx_instr, + xu_lsu_rf1_icswx_dot_instr => xu_lsu_rf1_icswx_dot_instr, + xu_lsu_rf1_icswx_epid => xu_lsu_rf1_icswx_epid, + xu_lsu_rf1_ldawx_instr => xu_lsu_rf1_ldawx_instr, + xu_lsu_rf1_wclr_instr => xu_lsu_rf1_wclr_instr, + xu_lsu_rf1_wchk_instr => xu_lsu_rf1_wchk_instr, + xu_lsu_rf1_derat_ra_eq_ea => xu_lsu_rf1_derat_ra_eq_ea, + xu_lsu_rf1_cmd_act => xu_lsu_rf1_cmd_act, + xu_lsu_rf1_data_act => xu_lsu_rf1_data_act, + xu_lsu_rf1_mtspr_trace => xu_lsu_rf1_mtspr_trace, + xu_iu_rf1_val => xu_iu_rf1_val, + xu_rf1_val => xu_rf1_val, + xu_rf1_is_tlbre => xu_rf1_is_tlbre, + xu_rf1_is_tlbwe => xu_rf1_is_tlbwe, + xu_rf1_is_tlbsx => xu_rf1_is_tlbsx, + xu_rf1_is_tlbsrx => xu_rf1_is_tlbsrx, + xu_rf1_is_tlbivax => xu_rf1_is_tlbivax, + xu_rf1_is_tlbilx => xu_rf1_is_tlbilx, + xu_rf1_is_eratre => xu_rf1_is_eratre, + xu_rf1_is_eratwe => xu_rf1_is_eratwe, + xu_rf1_is_eratsx => xu_rf1_is_eratsx, + xu_rf1_is_eratsrx => xu_rf1_is_eratsrx, + xu_rf1_is_erativax => xu_rf1_is_erativax, + xu_rf1_is_eratilx => xu_rf1_is_eratilx, + xu_ex1_is_isync => xu_ex1_is_isync, + xu_ex1_is_csync => xu_ex1_is_csync, + xu_lsu_rf1_derat_act => xu_lsu_rf1_derat_act, + xu_lsu_rf1_derat_is_load => xu_lsu_rf1_derat_is_load, + xu_lsu_rf1_derat_is_store => xu_lsu_rf1_derat_is_store, + xu_rf1_ws => xu_rf1_ws, + xu_rf1_t => xu_rf1_t, + lsu_xu_is2_back_inv => lsu_xu_is2_back_inv, + lsu_xu_is2_back_inv_addr => lsu_xu_is2_back_inv_addr, + xu_iu_ex6_pri => xu_iu_ex6_pri, + xu_iu_ex6_pri_val => xu_iu_ex6_pri_val, + fxb_fxa_ex6_clear_barrier => fxb_fxa_ex6_clear_barrier, + xu_iu_ex5_gshare => xu_iu_ex5_gshare, + xu_iu_ex5_getNIA => xu_iu_ex5_getNIA, + xu_iu_need_hole => xu_iu_need_hole, + byp_xer_si => byp_xer_si, + xu_iu_ex5_val => xu_iu_ex5_val, + xu_iu_ex5_tid => xu_iu_ex5_tid, + xu_iu_ex5_br_update => xu_iu_ex5_br_update, + xu_iu_ex5_br_hist => xu_iu_ex5_br_hist, + xu_iu_ex5_bclr => xu_iu_ex5_bclr, + xu_iu_ex5_lk => xu_iu_ex5_lk, + xu_iu_ex5_bh => xu_iu_ex5_bh, + dec_byp_ex5_instr => dec_byp_ex5_instr, + dec_byp_rf0_act => dec_byp_rf0_act, + spr_msr_cm => spr_msr_cm, + spr_ccr2_notlb => spr_ccr2_notlb, + spr_dec_spr_xucr0_ssdly => spr_dec_spr_xucr0_ssdly, + spr_ccr2_en_attn => spr_ccr2_en_attn, + spr_ccr2_en_pc => spr_ccr2_en_pc, + spr_ccr2_en_ditc => spr_ccr2_en_ditc, + spr_ccr2_en_icswx => spr_ccr2_en_icswx, + spr_ccr2_en_dcr => spr_ccr2_en_dcr, + spr_xucr0_clkg_ctl => spr_xucr0_clkg_ctl, + spr_bit_act => spr_bit_act, + byp_grp3_debug => byp_grp3_debug(0 to 14), + byp_grp4_debug => byp_grp4_debug(0 to 13), + byp_grp5_debug => byp_grp5_debug(0 to 14), + dec_grp0_debug => dec_grp0_debug, + dec_grp1_debug => dec_grp1_debug + ); + + xu_alu : entity work.xuq_alu(xuq_alu) + generic map( + expand_type => expand_type, + regmode => regmode, + a2mode => a2mode, + threads => threads, + dc_size => dc_size, + fxu_synth => fxu_synth) + port map( + nclk => nclk, + vdd => vdd, + gnd => gnd, + d_mode_dc => d_mode_dc_b, + delay_lclkr_dc => delay_lclkr_dc_b(4), + mpw1_dc_b => mpw1_dc_b_b(4), + mpw2_dc_b => mpw2_dc_b_b, + func_sl_force => func_sl_force, + func_sl_thold_0_b => func_sl_thold_0_b, + sg_0 => sg_0, + scan_in(0) => siv_57(1), + scan_in(1) => siv_58(1), + scan_out(0) => sov_57(1), + scan_out(1) => sov_58(1), + spr_msr_cm => spr_msr_cm, + dec_alu_rf1_act => dec_alu_rf1_act, + dec_alu_ex1_act => dec_alu_ex1_act, + dec_alu_rf1_sel => dec_alu_rf1_sel, + dec_alu_rf1_add_rs0_inv => dec_alu_rf1_add_rs0_inv, + dec_alu_rf1_add_ci => dec_alu_rf1_add_ci, + dec_alu_rf1_is_cmpl => dec_alu_rf1_is_cmpl, + dec_alu_rf1_tw_cmpsel => dec_alu_rf1_tw_cmpsel, + dec_alu_rf1_xer_ov_update => dec_alu_rf1_xer_ov_update, + dec_alu_rf1_xer_ca_update => dec_alu_rf1_xer_ca_update, + dec_alu_rf1_sh_right => dec_alu_rf1_sh_right, + dec_alu_rf1_sh_word => dec_alu_rf1_sh_word, + dec_alu_rf1_sgnxtd_byte => dec_alu_rf1_sgnxtd_byte, + dec_alu_rf1_sgnxtd_half => dec_alu_rf1_sgnxtd_half, + dec_alu_rf1_sgnxtd_wd => dec_alu_rf1_sgnxtd_wd, + dec_alu_rf1_sra_dw => dec_alu_rf1_sra_dw, + dec_alu_rf1_sra_wd => dec_alu_rf1_sra_wd, + dec_alu_rf1_chk_shov_dw => dec_alu_rf1_chk_shov_dw, + dec_alu_rf1_chk_shov_wd => dec_alu_rf1_chk_shov_wd, + dec_alu_rf1_use_me_ins_hi => dec_alu_rf1_use_me_ins_hi, + dec_alu_rf1_use_me_ins_lo => dec_alu_rf1_use_me_ins_lo, + dec_alu_rf1_use_mb_ins_hi => dec_alu_rf1_use_mb_ins_hi, + dec_alu_rf1_use_mb_ins_lo => dec_alu_rf1_use_mb_ins_lo, + dec_alu_rf1_use_me_rb_hi => dec_alu_rf1_use_me_rb_hi, + dec_alu_rf1_use_me_rb_lo => dec_alu_rf1_use_me_rb_lo, + dec_alu_rf1_use_mb_rb_hi => dec_alu_rf1_use_mb_rb_hi, + dec_alu_rf1_use_mb_rb_lo => dec_alu_rf1_use_mb_rb_lo, + dec_alu_rf1_use_rb_amt_hi => dec_alu_rf1_use_rb_amt_hi, + dec_alu_rf1_use_rb_amt_lo => dec_alu_rf1_use_rb_amt_lo, + dec_alu_rf1_zm_ins => dec_alu_rf1_zm_ins, + dec_alu_rf1_log_fcn => dec_alu_rf1_log_fcn, + dec_alu_rf1_me_ins_b => dec_alu_rf1_me_ins_b, + dec_alu_rf1_mb_ins => dec_alu_rf1_mb_ins, + dec_alu_rf1_sh_amt => dec_alu_rf1_sh_amt, + dec_alu_rf1_mb_gt_me => dec_alu_rf1_mb_gt_me, + byp_alu_rf1_isel_fcn => byp_alu_rf1_isel_fcn, + fxa_fxb_ex1_hold_ctr_flush => fxa_fxb_ex1_hold_ctr_flush, + dec_ex2_tid => dec_ex2_tid, + dec_ex4_tid => dec_ex4_tid, + dec_alu_rf1_mul_recform => dec_alu_rf1_mul_recform, + dec_alu_rf1_div_recform => dec_alu_rf1_div_recform, + dec_alu_rf1_mul_val => dec_alu_rf1_mul_val, + dec_alu_rf1_mul_ret => dec_alu_rf1_mul_ret, + dec_alu_rf1_mul_sign => dec_alu_rf1_mul_sign, + dec_alu_rf1_mul_size => dec_alu_rf1_mul_size, + dec_alu_rf1_mul_imm => dec_alu_rf1_mul_imm, + dec_alu_rf1_div_val => dec_alu_rf1_div_val, + dec_alu_rf1_div_sign => dec_alu_rf1_div_sign, + dec_alu_rf1_div_size => dec_alu_rf1_div_size, + dec_alu_rf1_div_extd => dec_alu_rf1_div_extd, + fxa_fxb_rf1_div_ctr => fxa_fxb_rf1_div_ctr, + dec_alu_ex1_is_cmp => dec_alu_ex1_is_cmp, + dec_alu_rf1_select_64bmode => dec_alu_rf1_select_64bmode, + alu_cpl_ex3_trap_val => alu_cpl_ex3_trap_val, + byp_alu_ex1_rs0 => byp_alu_ex1_rs0, + byp_alu_ex1_rs1 => byp_alu_ex1_rs1, + byp_alu_ex1_mulsrc_0 => byp_alu_ex1_mulsrc_0, + byp_alu_ex1_mulsrc_1 => byp_alu_ex1_mulsrc_1, + byp_alu_ex1_divsrc_0 => byp_alu_ex1_divsrc_0, + byp_alu_ex1_divsrc_1 => byp_alu_ex1_divsrc_1, + xu_ex1_eff_addr_int => xu_ex1_eff_addr_int, + xu_ex2_eff_addr => xu_ex2_eff_addr, + alu_byp_ex5_mul_rt => alu_byp_ex5_mul_rt, + alu_byp_ex3_div_rt => alu_byp_ex3_div_rt, + alu_ex2_div_done => alu_ex2_div_done, + alu_dec_ex1_ipb_ba => alu_dec_ex1_ipb_ba, + alu_dec_div_need_hole => alu_dec_div_need_hole, + alu_ex3_mul_done => alu_ex3_mul_done, + alu_ex4_mul_done => alu_ex4_mul_done, + alu_byp_ex2_cr_recform => alu_byp_ex2_cr_recform, + alu_byp_ex5_cr_mul => alu_byp_ex5_cr_mul, + alu_byp_ex3_cr_div => alu_byp_ex3_cr_div, + alu_byp_ex2_xer => alu_byp_ex2_xer, + alu_byp_ex5_xer_mul => alu_byp_ex5_xer_mul, + alu_byp_ex3_xer_div => alu_byp_ex3_xer_div, + alu_byp_ex1_log_rt => alu_byp_ex1_log_rt, + alu_byp_ex2_rt => alu_byp_ex2_rt); + + mux_spr_ex2_rt <= alu_byp_ex2_rt; + alu_byp_ex2_rt_b <= alu_byp_ex2_rt; + + xu_perv : entity work.xuq_perv(xuq_perv) + generic map( + expand_type => expand_type) + port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_xu_sg_3 => pc_xu_sg_3, + pc_xu_func_sl_thold_3 => pc_xu_func_sl_thold_3, + pc_xu_func_slp_sl_thold_3 => pc_xu_func_slp_sl_thold_3, + pc_xu_gptr_sl_thold_3 => pc_xu_gptr_sl_thold_3, + pc_xu_func_nsl_thold_3 => pc_xu_func_nsl_thold_3, + pc_xu_func_slp_nsl_thold_3 => pc_xu_func_slp_nsl_thold_3, + pc_xu_abst_sl_thold_3 => pc_xu_abst_sl_thold_3, + pc_xu_abst_slp_sl_thold_3 => pc_xu_abst_slp_sl_thold_3, + pc_xu_regf_sl_thold_3 => pc_xu_regf_sl_thold_3, + pc_xu_regf_slp_sl_thold_3 => pc_xu_regf_slp_sl_thold_3, + pc_xu_time_sl_thold_3 => pc_xu_time_sl_thold_3, + pc_xu_ary_nsl_thold_3 => pc_xu_ary_nsl_thold_3, + pc_xu_ary_slp_nsl_thold_3 => pc_xu_ary_slp_nsl_thold_3, + pc_xu_repr_sl_thold_3 => pc_xu_repr_sl_thold_3, + pc_xu_cfg_sl_thold_3 => pc_xu_cfg_sl_thold_3, + pc_xu_cfg_slp_sl_thold_3 => pc_xu_cfg_slp_sl_thold_3, + pc_xu_bolt_sl_thold_3 => pc_xu_bolt_sl_thold_3, + pc_xu_bo_enable_3 => pc_xu_bo_enable_3, + pc_xu_fce_3 => pc_xu_fce_3, + pc_xu_ccflush_dc => pc_xu_ccflush_dc, + an_ac_scan_diag_dc => an_ac_scan_diag_dc, + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b, + sg_2 => sg_2_b, + func_sl_thold_2 => func_sl_thold_2_b, + func_slp_sl_thold_2 => func_slp_sl_thold_2_b, + func_nsl_thold_2 => func_nsl_thold_2_b, + func_slp_nsl_thold_2 => func_slp_nsl_thold_2_b, + ary_nsl_thold_2 => ary_nsl_thold_2, + ary_slp_nsl_thold_2 => ary_slp_nsl_thold_2, + time_sl_thold_2 => time_sl_thold_2, + gptr_sl_thold_2 => gptr_sl_thold_2, + abst_sl_thold_2 => abst_sl_thold_2, + abst_slp_sl_thold_2 => abst_slp_sl_thold_2, + regf_sl_thold_2 => open, + repr_sl_thold_2 => repr_sl_thold_2, + cfg_sl_thold_2 => cfg_sl_thold_2, + cfg_slp_sl_thold_2 => cfg_slp_sl_thold_2, + regf_slp_sl_thold_2 => regf_slp_sl_thold_2, + bolt_sl_thold_2 => bolt_sl_thold_2, + bo_enable_2 => bo_enable_2, + sg_0 => open, + sg_1 => open, + ary_nsl_thold_0 => open, + abst_sl_thold_0 => open, + time_sl_thold_0 => open, + repr_sl_thold_0 => open, + fce_2 => fce_2_b, + clkoff_dc_b => clkoff_dc_b_b, + d_mode_dc => d_mode_dc_b, + delay_lclkr_dc => delay_lclkr_dc_b, + mpw1_dc_b => mpw1_dc_b_b, + mpw2_dc_b => mpw2_dc_b_b, + g6t_clkoff_dc_b => g6t_clkoff_dc_b, + g6t_d_mode_dc => g6t_d_mode_dc, + g6t_delay_lclkr_dc => g6t_delay_lclkr_dc, + g6t_mpw1_dc_b => g6t_mpw1_dc_b, + g6t_mpw2_dc_b => g6t_mpw2_dc_b, + g8t_clkoff_dc_b => g8t_clkoff_dc_b, + g8t_d_mode_dc => g8t_d_mode_dc, + g8t_delay_lclkr_dc => g8t_delay_lclkr_dc, + g8t_mpw1_dc_b => g8t_mpw1_dc_b, + g8t_mpw2_dc_b => g8t_mpw2_dc_b, + cam_clkoff_dc_b => cam_clkoff_dc_b, + cam_d_mode_dc => cam_d_mode_dc, + cam_delay_lclkr_dc => cam_delay_lclkr_dc, + cam_act_dis_dc => cam_act_dis_dc, + cam_mpw1_dc_b => cam_mpw1_dc_b, + cam_mpw2_dc_b => cam_mpw2_dc_b, + gptr_scan_in => gptr_scan_in, + gptr_scan_out => gptr_scan_out + ); + + xu_perf : entity work.xuq_perf(xuq_perf) + generic map( + expand_type => expand_type) + port map( + nclk => nclk, + func_sl_thold_2 => func_sl_thold_2_b(1), + sg_2 => sg_2_b(1), + d_mode_dc => d_mode_dc_b, + delay_lclkr_dc => delay_lclkr_dc_b(4), + mpw1_dc_b => mpw1_dc_b_b(4), + mpw2_dc_b => mpw2_dc_b_b, + clkoff_dc_b => clkoff_dc_b_b, + pc_xu_ccflush_dc => pc_xu_ccflush_dc, + scan_in => siv_56(2), + scan_out => sov_56(2), + cpl_perf_tx_events => cpl_perf_tx_events, + spr_perf_tx_events => spr_perf_tx_events, + byp_perf_tx_events => byp_perf_tx_events, + fxa_perf_muldiv_in_use => fxa_perf_muldiv_in_use, + pc_xu_event_bus_enable => pc_xu_event_bus_enable, + pc_xu_event_count_mode => pc_xu_event_count_mode, + pc_xu_event_mux_ctrls => pc_xu_event_mux_ctrls, + xu_pc_event_data => xu_pc_event_data, + spr_msr_gs => spr_msr_gs, + spr_msr_pr => spr_msr_pr, + vdd => vdd, + gnd => gnd); + + + xu_fxu_debug : entity work.xuq_debug(xuq_debug) + generic map( + expand_type => expand_type) + port map( + nclk => nclk, + d_mode_dc => d_mode_dc_b, + delay_lclkr_dc => delay_lclkr_dc_b(4), + mpw1_dc_b => mpw1_dc_b_b(4), + mpw2_dc_b => mpw2_dc_b_b, + func_slp_sl_thold_0_b => func_slp_sl_thold_0_b, + func_slp_sl_force => func_slp_sl_force, + sg_0 => sg_0, + scan_in => siv_56(3), + scan_out => sov_56(3), + dec_byp_ex3_instr_trace_val => dec_byp_ex3_instr_trace_val, + pc_xu_trace_bus_enable => pc_xu_trace_bus_enable, + debug_mux_ctrls => fxu_debug_mux_ctrls, + trigger_data_in => fxu_trigger_data_in, + debug_data_in => fxu_debug_data_in, + trigger_data_out => fxu_trigger_data_out, + debug_data_out => fxu_debug_data_out, + dbg_group0 => dbg_group0, + dbg_group1 => dbg_group1, + dbg_group2 => dbg_group2, + dbg_group3 => dbg_group3, + dbg_group4 => dbg_group4, + dbg_group5 => dbg_group5, + dbg_group6 => dbg_group6, + dbg_group7 => dbg_group7, + dbg_group8 => dbg_group8, + dbg_group9 => dbg_group9, + dbg_group10 => dbg_group10, + dbg_group11 => dbg_group11, + dbg_group12 => dbg_group12, + dbg_group13 => dbg_group13, + dbg_group14 => dbg_group14, + dbg_group15 => dbg_group15, + trg_group0 => trg_group0, + trg_group1 => trg_group1, + trg_group2 => trg_group2, + trg_group3 => trg_group3, + vdd => vdd, + gnd => gnd + ); + + fxb_fxa_ex7_we0 <= ex7_we0; + fxb_fxa_ex7_wa0 <= ex7_wa0; + fxb_fxa_ex7_wd0 <= ex7_wd0; + + gpr_we0_debug(0 to 65) <= ex7_wd0(0 to 63) & ex7_we0 & ex7_wa0(0); + gpr_we0_debug(66 to 87) <= ex7_we0 & ex7_wa0 & (9 to 21=>'0'); + + dbg_group0 <= (others=>'0'); + dbg_group1 <= byp_grp1_debug; + dbg_group2 <= (others=>'0'); + dbg_group3 <= (others=>'0'); + dbg_group4 <= (others=>'0'); + dbg_group5 <= (others=>'0'); + dbg_group6 <= byp_grp6_debug; + dbg_group7 <= byp_grp7_debug; + dbg_group8 <= (0 to 21=>'0') & byp_grp8_debug; + dbg_group9 <= (others=>'0'); + dbg_group10 <= (others=>'0'); + dbg_group11 <= dec_grp1_debug; + dbg_group12 <= lsu_xu_data_debug0; + dbg_group13 <= lsu_xu_data_debug1; + dbg_group14 <= lsu_xu_data_debug2; + dbg_group15 <= (others=>'0'); + trg_group0 <= (others=>'0'); + trg_group1 <= (others=>'0'); + trg_group2 <= (others=>'0'); + trg_group3 <= (others=>'0'); + + mark_unused(byp_grp0_debug); + mark_unused(byp_grp2_debug); + mark_unused(byp_grp3_debug); + mark_unused(byp_grp4_debug); + mark_unused(byp_grp5_debug); + mark_unused(gpr_we0_debug); + mark_unused(dec_grp0_debug); + + xu_fxu_spr : entity work.xuq_fxu_spr(xuq_fxu_spr) + generic map ( + hvmode => hvmode, + a2mode => a2mode, + expand_type => expand_type, + threads => threads, + regsize => regsize, + eff_ifar => eff_ifar) + port map( + nclk => nclk, + d_mode_dc => d_mode_dc_b, + delay_lclkr_dc => delay_lclkr_dc_b(4), + mpw1_dc_b => mpw1_dc_b_b(4), + mpw2_dc_b => mpw2_dc_b_b, + func_sl_force => func_sl_force, + func_sl_thold_0_b => func_sl_thold_0_b, + func_nsl_force => func_nsl_force, + func_nsl_thold_0_b => func_nsl_thold_0_b, + sg_0 => sg_0, + scan_in => siv_57(2), + scan_out => sov_57(2), + ex1_tid => dec_ex1_tid, + ex1_instr => dec_fspr_ex1_instr, + dec_spr_ex1_is_mfspr => dec_spr_ex1_is_mfspr, + dec_spr_ex1_is_mtspr => dec_spr_ex1_is_mtspr, + ex6_val => dec_fspr_ex6_val, + ex6_spr_wd => byp_spr_ex6_rt, + fspr_byp_ex3_spr_rt => fspr_byp_ex3_spr_rt, + mux_spr_ex2_rt => alu_byp_ex2_rt_b, + ex2_is_any_load_dac => ex2_is_any_load_dac, + ex2_is_any_store_dac => ex2_is_any_store_dac, + xu_lsu_ex4_dvc1_en => xu_lsu_ex4_dvc1_en, + xu_lsu_ex4_dvc2_en => xu_lsu_ex4_dvc2_en, + lsu_xu_ex2_dvc1_st_cmp => lsu_xu_ex2_dvc1_st_cmp, + lsu_xu_ex2_dvc2_st_cmp => lsu_xu_ex2_dvc2_st_cmp, + lsu_xu_ex8_dvc1_ld_cmp => lsu_xu_ex8_dvc1_ld_cmp, + lsu_xu_ex8_dvc2_ld_cmp => lsu_xu_ex8_dvc2_ld_cmp, + lsu_xu_rel_dvc1_en => lsu_xu_rel_dvc1_en, + lsu_xu_rel_dvc2_en => lsu_xu_rel_dvc2_en, + lsu_xu_rel_dvc_thrd_id => lsu_xu_rel_dvc_thrd_id, + lsu_xu_rel_dvc1_cmp => lsu_xu_rel_dvc1_cmp, + lsu_xu_rel_dvc2_cmp => lsu_xu_rel_dvc2_cmp, + fxu_cpl_ex3_dac1r_cmpr_async => fxu_cpl_ex3_dac1r_cmpr_async, + fxu_cpl_ex3_dac2r_cmpr_async => fxu_cpl_ex3_dac2r_cmpr_async, + fxu_cpl_ex3_dac1r_cmpr => fxu_cpl_ex3_dac1r_cmpr, + fxu_cpl_ex3_dac2r_cmpr => fxu_cpl_ex3_dac2r_cmpr, + fxu_cpl_ex3_dac3r_cmpr => fxu_cpl_ex3_dac3r_cmpr, + fxu_cpl_ex3_dac4r_cmpr => fxu_cpl_ex3_dac4r_cmpr, + fxu_cpl_ex3_dac1w_cmpr => fxu_cpl_ex3_dac1w_cmpr, + fxu_cpl_ex3_dac2w_cmpr => fxu_cpl_ex3_dac2w_cmpr, + fxu_cpl_ex3_dac3w_cmpr => fxu_cpl_ex3_dac3w_cmpr, + fxu_cpl_ex3_dac4w_cmpr => fxu_cpl_ex3_dac4w_cmpr, + spr_bit_act => spr_bit_act, + spr_msr_pr => spr_msr_pr, + spr_msr_ds => spr_msr_ds, + spr_dbcr0_dac1 => spr_dbcr0_dac1, + spr_dbcr0_dac2 => spr_dbcr0_dac2, + spr_dbcr0_dac3 => spr_dbcr0_dac3, + spr_dbcr0_dac4 => spr_dbcr0_dac4, + spr_dbcr3_ivc => spr_dbcr3_ivc, + vdd => vdd, + gnd => gnd + ); + +func_scan_rpwr_54i_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc_b(4), + thold_b => func_so_thold_0_b, + scin => siv_54(siv_54'left to siv_54'left), + scout => sov_54(sov_54'left to sov_54'left), + dout => open); +func_scan_rpwr_54o_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc_b(4), + thold_b => func_so_thold_0_b, + scin => siv_54(siv_54'right to siv_54'right), + scout => sov_54(sov_54'right to sov_54'right), + dout => open); +func_scan_rpwr_55i_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc_b(4), + thold_b => func_so_thold_0_b, + scin => siv_55(siv_55'left to siv_55'left), + scout => sov_55(sov_55'left to sov_55'left), + dout => open); +func_scan_rpwr_55o_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc_b(4), + thold_b => func_so_thold_0_b, + scin => siv_55(siv_55'right to siv_55'right), + scout => sov_55(sov_55'right to sov_55'right), + dout => open); +func_scan_rpwr_56i_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc_b(4), + thold_b => func_so_thold_0_b, + scin => siv_56(siv_56'left to siv_56'left), + scout => sov_56(sov_56'left to sov_56'left), + dout => open); +func_scan_rpwr_56o_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc_b(4), + thold_b => func_so_thold_0_b, + scin => siv_56(siv_56'right to siv_56'right), + scout => sov_56(sov_56'right to sov_56'right), + dout => open); +func_scan_rpwr_57i_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc_b(4), + thold_b => func_so_thold_0_b, + scin => siv_57(siv_57'left to siv_57'left), + scout => sov_57(sov_57'left to sov_57'left), + dout => open); +func_scan_rpwr_57o_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc_b(4), + thold_b => func_so_thold_0_b, + scin => siv_57(siv_57'right to siv_57'right), + scout => sov_57(sov_57'right to sov_57'right), + dout => open); +func_scan_rpwr_58i_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc_b(4), + thold_b => func_so_thold_0_b, + scin => siv_58(siv_58'left to siv_58'left), + scout => sov_58(sov_58'left to sov_58'left), + dout => open); +func_scan_rpwr_58o_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc_b(4), + thold_b => func_so_thold_0_b, + scin => siv_58(siv_58'right to siv_58'right), + scout => sov_58(sov_58'right to sov_58'right), + dout => open); + + +siv_54(0 to sov_54'right) <= sov_54(1 to sov_54'right) & func_scan_in(54); +func_scan_out(54) <= sov_54(0) and an_ac_scan_dis_dc_b; +siv_55(0 to sov_55'right) <= sov_55(1 to sov_55'right) & func_scan_in(55); +func_scan_out(55) <= sov_55(0) and an_ac_scan_dis_dc_b; +siv_56(0 to sov_56'right) <= sov_56(1 to sov_56'right) & func_scan_in(56); +func_scan_out(56) <= sov_56(0) and an_ac_scan_dis_dc_b; +siv_57(0 to sov_57'right) <= sov_57(1 to sov_57'right) & func_scan_in(57); +func_scan_out(57) <= sov_57(0) and an_ac_scan_dis_dc_b; +siv_58(0 to sov_58'right) <= sov_58(1 to sov_58'right) & func_scan_in(58); +func_scan_out(58) <= sov_58(0) and an_ac_scan_dis_dc_b; + + + + +end architecture xuq_fxu_b; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_fxu_gpr.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_fxu_gpr.vhdl new file mode 100644 index 0000000..9ece0c8 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_fxu_gpr.vhdl @@ -0,0 +1,1218 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +LIBRARY ieee; USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY ibm; + USE ibm.std_ulogic_support.all; + USE ibm.std_ulogic_unsigned.all; + USE ibm.std_ulogic_function_support.all; +LIBRARY support; + USE support.power_logic_pkg.all; +LIBRARY tri; USE tri.tri_latches_pkg.all; + +entity xuq_fxu_gpr is + generic( + expand_type : integer := 2; + regsize : integer := 64; + threads : integer := 4); + port ( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + + d_mode_dc : in std_ulogic; + delay_lclkr_dc : in std_ulogic; + clkoff_dc_b : in std_ulogic; + mpw1_dc_b : in std_ulogic; + mpw2_dc_b : in std_ulogic; + func_sl_force : in std_ulogic; + func_sl_thold_0_b : in std_ulogic; + func_nsl_force : in std_ulogic; + func_nsl_thold_0_b : in std_ulogic; + sg_0 : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + an_ac_scan_diag_dc : in std_ulogic; + + lbist_en : in std_ulogic; + abist_en : in std_ulogic; + abist_raw_dc_b : in std_ulogic; + r0e_sel_lbist : in std_ulogic; + r1e_sel_lbist : in std_ulogic; + r0e_abist_comp_en : in std_ulogic; + r1e_abist_comp_en : in std_ulogic; + r0e_addr_abist : in std_ulogic_vector(2 to 9); + r1e_addr_abist : in std_ulogic_vector(2 to 9); + r0e_en_abist : in std_ulogic; + r1e_en_abist : in std_ulogic; + w0e_addr_abist : in std_ulogic_vector(2 to 9); + w0l_addr_abist : in std_ulogic_vector(2 to 9); + w0e_en_abist : in std_ulogic; + w0l_en_abist : in std_ulogic; + w0e_data_abist : in std_ulogic_vector(0 to 3); + w0l_data_abist : in std_ulogic_vector(0 to 3); + + bo_enable_2 : in std_ulogic; + pc_xu_bo_reset : in std_ulogic; + pc_xu_bo_unload : in std_ulogic; + pc_xu_bo_load : in std_ulogic; + pc_xu_bo_shdata : in std_ulogic; + pc_xu_bo_select : in std_ulogic_vector(0 to 1); + xu_pc_bo_fail : out std_ulogic_vector(0 to 1); + xu_pc_bo_diagout : out std_ulogic_vector(0 to 1); + + lcb_fce_0 : in std_ulogic; + lcb_scan_diag_dc : in std_ulogic; + lcb_scan_dis_dc_b : in std_ulogic; + lcb_sg_0 : in std_ulogic; + lcb_abst_sl_thold_0 : in std_ulogic; + lcb_ary_nsl_thold_0 : in std_ulogic; + lcb_time_sl_thold_0 : in std_ulogic; + lcb_gptr_sl_thold_0 : in std_ulogic; + lcb_bolt_sl_thold_0 : in std_ulogic; + + gpr_gptr_scan_in : in std_ulogic; + gpr_gptr_scan_out : out std_ulogic; + gpr_time_scan_in : in std_ulogic; + gpr_time_scan_out : out std_ulogic; + gpr_abst_scan_in : in std_ulogic; + gpr_abst_scan_out : out std_ulogic; + + pc_xu_inj_regfile_parity : in std_ulogic_vector(0 to 3); + xu_pc_err_regfile_parity : out std_ulogic_vector(0 to threads-1); + xu_pc_err_regfile_ue : out std_ulogic_vector(0 to 3); + gpr_cpl_ex3_regfile_err_det : out std_ulogic; + cpl_gpr_regfile_seq_beg : in std_ulogic; + gpr_cpl_regfile_seq_end : out std_ulogic; + + r0_en : in std_ulogic; + r0_addr_func : in std_ulogic_vector(0 to 7); + r0_data_out : out std_ulogic_vector(64-regsize to 69+regsize/8); + + r1_en : in std_ulogic; + r1_addr_func : in std_ulogic_vector(0 to 7); + r1_data_out : out std_ulogic_vector(64-regsize to 69+regsize/8); + + r2_en : in std_ulogic; + r2_addr_func : in std_ulogic_vector(0 to 7); + r2_data_out : out std_ulogic_vector(64-regsize to 69+regsize/8); + + r3_en : in std_ulogic := '0'; + r3_addr_func : in std_ulogic_vector(0 to 7) := "00000000"; + r3_data_out : out std_ulogic_vector(64-regsize to 69+regsize/8) := (others=>'0'); + + w_e_act : in std_ulogic; + w_e_addr_func : in std_ulogic_vector(0 to 7); + w_e_data_func : in std_ulogic_vector(64-regsize to 63); + + w_l_act : in std_ulogic; + w_l_addr_func : in std_ulogic_vector(0 to 7); + w_l_data_func : in std_ulogic_vector(64-regsize to 69+regsize/8); + + gpr_debug : out std_ulogic_vector(0 to 21) + + ); + + -- synopsys translate_off + -- synopsys translate_on +end xuq_fxu_gpr; + +architecture xuq_fxu_gpr of xuq_fxu_gpr is + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + subtype s3 is std_ulogic_vector(0 to 2); + + signal siv_abst, sov_abst : std_ulogic_vector(0 to 7); + signal siv_time, sov_time : std_ulogic_vector(0 to 1); + + signal lcb_clkoff_dc_b : std_ulogic_vector(0 to 1); + signal lcb_delay_lclkr_dc : std_ulogic_vector(0 to 4); + signal lcb_act_dis_dc : std_ulogic; + signal lcb_d_mode_dc : std_ulogic; + signal lcb_mpw1_dc_b : std_ulogic_vector(0 to 4); + signal lcb_mpw2_dc_b : std_ulogic; + signal arr_delay_lclkr_dc : std_ulogic_vector(0 to 9); + signal arr_mpw1_dc_b : std_ulogic_vector(1 to 9); + signal r0_array_data : std_ulogic_vector(64-regsize to 69+regsize/8); + signal r1_array_data : std_ulogic_vector(64-regsize to 69+regsize/8); + signal r2_array_data : std_ulogic_vector(64-regsize to 69+regsize/8); + signal r3_array_data : std_ulogic_vector(64-regsize to 69+regsize/8); + signal gpr_do0_par : std_ulogic_vector(8-regsize/8 to 7); + signal gpr_do0_par_err : std_ulogic; + signal gpr_do1_par : std_ulogic_vector(8-regsize/8 to 7); + signal gpr_do1_par_err : std_ulogic; + signal gpr_do2_par : std_ulogic_vector(8-regsize/8 to 7); + signal gpr_do2_par_err : std_ulogic; + signal gpr_do3_par : std_ulogic_vector(8-regsize/8 to 7); + signal gpr_do3_par_err : std_ulogic; + signal r0_read_enable : std_ulogic; + signal r1_read_enable : std_ulogic; + signal r2_read_enable : std_ulogic; + signal r3_read_enable : std_ulogic; + signal r0_read_addr : std_ulogic_vector(0 to 7); + signal r1_read_addr : std_ulogic_vector(0 to 7); + signal r2_read_addr : std_ulogic_vector(0 to 7); + signal r3_read_addr : std_ulogic_vector(0 to 7); + signal w_e_data, w0e_data, w1e_data : std_ulogic_vector(64-regsize to 69+regsize/8); + signal w_l_data : std_ulogic_vector(64-regsize to 69+regsize/8); + signal w_e_enable : std_ulogic; + signal w_l_enable : std_ulogic; + signal w_e_addr : std_ulogic_vector(0 to 7); + signal w_l_addr : std_ulogic_vector(0 to 7); + signal w_e_data_func_par : std_ulogic_vector(64-regsize to 69+regsize/8); + signal w_e_parity : std_ulogic_vector(8-regsize/8 to 7); + signal perr_sm_next : std_ulogic_vector(0 to 4); + signal perr_write_data_sel : std_ulogic_vector(0 to 1); + signal tri_err_in : std_ulogic_vector(0 to 7); + signal tri_err_out : std_ulogic_vector(0 to 7); + signal r0_byp_r : std_ulogic; + signal r1_byp_r : std_ulogic; + signal r2_byp_r : std_ulogic; + signal r3_byp_r : std_ulogic; + signal perr_tid : std_ulogic_vector(0 to threads-1); + signal perr_ue, perr_ce : std_ulogic; + signal w_e_tid : std_ulogic_vector(0 to threads-1); + signal perr_inj : std_ulogic; + + signal ex3_regfile_err_det_q, ex2_regfile_err_det : std_ulogic; + signal gpr_do0_par_err_q : std_ulogic; + signal gpr_do1_par_err_q : std_ulogic; + signal gpr_do2_par_err_q : std_ulogic; + signal gpr_do3_par_err_q : std_ulogic; + signal r0_array_data_q : std_ulogic_vector(0 to 63+regsize/8); + signal r0_read_addr_q : std_ulogic_vector(0 to 7); + signal r0_read_addr_1_q : std_ulogic_vector(0 to 7); + signal r0_read_addr_2_q : std_ulogic_vector(0 to 7); + signal r0_read_enable_q : std_ulogic; + signal r0_read_val_q : std_ulogic; + signal r1_array_data_q : std_ulogic_vector(0 to 63+regsize/8); + signal r1_read_addr_q : std_ulogic_vector(0 to 7); + signal r1_read_addr_1_q : std_ulogic_vector(0 to 7); + signal r1_read_addr_2_q : std_ulogic_vector(0 to 7); + signal r1_read_enable_q : std_ulogic; + signal r1_read_val_q : std_ulogic; + signal r2_array_data_q : std_ulogic_vector(0 to 63+regsize/8); + signal r2_read_addr_q : std_ulogic_vector(0 to 7); + signal r2_read_addr_1_q : std_ulogic_vector(0 to 7); + signal r2_read_addr_2_q : std_ulogic_vector(0 to 7); + signal r2_read_enable_q : std_ulogic; + signal r2_read_val_q : std_ulogic; + signal r3_array_data_q : std_ulogic_vector(0 to 63+regsize/8); + signal r3_read_enable_q : std_ulogic; + signal r3_read_val_q : std_ulogic; + signal perr_addr_q, perr_addr_d : std_ulogic_vector(0 to 7); + signal perr_direction_q, perr_direction_d : std_ulogic_vector(0 to 1); + signal perr_inj_q : std_ulogic_vector(0 to 3); + signal perr_sm_q, perr_sm_d : std_ulogic_vector(0 to 4); + signal perr_write_data_q, perr_write_data_d : std_ulogic_vector(64-regsize to 69+regsize/8); + signal err_regfile_parity_q, err_regfile_parity_d : std_ulogic_vector(0 to threads-1); + signal err_regfile_ue_q, err_regfile_ue_d : std_ulogic_vector(0 to threads-1); + signal err_seq_0_q : std_ulogic; + signal wthru_r0_w_e_q, wthru_r0_w_e_d : std_ulogic; + signal wthru_r0_w_l_q, wthru_r0_w_l_d : std_ulogic; + signal wthru_r1_w_e_q, wthru_r1_w_e_d : std_ulogic; + signal wthru_r1_w_l_q, wthru_r1_w_l_d : std_ulogic; + signal wthru_r2_w_e_q, wthru_r2_w_e_d : std_ulogic; + signal wthru_r2_w_l_q, wthru_r2_w_l_d : std_ulogic; + signal wthru_r3_w_e_q, wthru_r3_w_e_d : std_ulogic; + signal wthru_r3_w_l_q, wthru_r3_w_l_d : std_ulogic; + constant ex3_regfile_err_det_offset : integer := 0; + constant gpr_do0_par_err_offset : integer := ex3_regfile_err_det_offset + 1; + constant gpr_do1_par_err_offset : integer := gpr_do0_par_err_offset + 1; + constant gpr_do2_par_err_offset : integer := gpr_do1_par_err_offset + 1; + constant gpr_do3_par_err_offset : integer := gpr_do2_par_err_offset + 1; + constant r0_array_data_offset : integer := gpr_do3_par_err_offset + 1; + constant r0_read_addr_1_offset : integer := r0_array_data_offset + r0_array_data_q'length; + constant r0_read_val_offset : integer := r0_read_addr_1_offset + r0_read_addr_1_q'length; + constant r1_array_data_offset : integer := r0_read_val_offset + 1; + constant r1_read_addr_1_offset : integer := r1_array_data_offset + r1_array_data_q'length; + constant r1_read_val_offset : integer := r1_read_addr_1_offset + r1_read_addr_1_q'length; + constant r2_array_data_offset : integer := r1_read_val_offset + 1; + constant r2_read_addr_1_offset : integer := r2_array_data_offset + r2_array_data_q'length; + constant r2_read_val_offset : integer := r2_read_addr_1_offset + r2_read_addr_1_q'length; + constant r3_array_data_offset : integer := r2_read_val_offset + 1; + constant r3_read_val_offset : integer := r3_array_data_offset + r3_array_data_q'length; + constant perr_addr_offset : integer := r3_read_val_offset + 1; + constant perr_direction_offset : integer := perr_addr_offset + perr_addr_q'length; + constant perr_inj_offset : integer := perr_direction_offset + perr_direction_q'length; + constant perr_sm_offset : integer := perr_inj_offset + perr_inj_q'length; + constant perr_write_data_offset : integer := perr_sm_offset + perr_sm_q'length; + constant err_regfile_parity_offset : integer := perr_write_data_offset + perr_write_data_q'length; + constant err_regfile_ue_offset : integer := err_regfile_parity_offset + err_regfile_parity_q'length; + constant err_seq_0_offset : integer := err_regfile_ue_offset + err_regfile_ue_q'length; + constant wthru_r0_w_e_offset : integer := err_seq_0_offset + 1; + constant wthru_r0_w_l_offset : integer := wthru_r0_w_e_offset + 1; + constant wthru_r1_w_e_offset : integer := wthru_r0_w_l_offset + 1; + constant wthru_r1_w_l_offset : integer := wthru_r1_w_e_offset + 1; + constant wthru_r2_w_e_offset : integer := wthru_r1_w_l_offset + 1; + constant wthru_r2_w_l_offset : integer := wthru_r2_w_e_offset + 1; + constant wthru_r3_w_e_offset : integer := wthru_r2_w_l_offset + 1; + constant wthru_r3_w_l_offset : integer := wthru_r3_w_e_offset + 1; + constant scan_right : integer := wthru_r3_w_l_offset + 1; + signal siv : std_ulogic_vector(0 to scan_right-1); + signal sov : std_ulogic_vector(0 to scan_right-1); + +begin + + + tri_err_in <= err_regfile_parity_q & err_regfile_ue_q; + + xu_gpr_err_rpt : entity tri.tri_direct_err_rpt(tri_direct_err_rpt) + generic map( + width => 8, + expand_type => expand_type) + port map( + vd => vdd, + gd => gnd, + err_in => tri_err_in, + err_out => tri_err_out); + + xu_pc_err_regfile_parity <= tri_err_out(0 to 3); + xu_pc_err_regfile_ue <= tri_err_out(4 to 7); + + +gpr_64b_par_gen : if regsize = 64 generate + w_e_parity(0) <= xor_reduce(w_e_data_func(0 to 7 )); + w_e_parity(1) <= xor_reduce(w_e_data_func(8 to 15)); + w_e_parity(2) <= xor_reduce(w_e_data_func(16 to 23)); + w_e_parity(3) <= xor_reduce(w_e_data_func(24 to 31)); + w_e_parity(4) <= xor_reduce(w_e_data_func(32 to 39)); + w_e_parity(5) <= xor_reduce(w_e_data_func(40 to 47)); + w_e_parity(6) <= xor_reduce(w_e_data_func(48 to 55)); + w_e_parity(7) <= xor_reduce(w_e_data_func(56 to 63)); +end generate; + +gpr_32b_par_gen : if regsize = 32 generate + w_e_parity(4) <= xor_reduce(w_e_data_func(32 to 39)); + w_e_parity(5) <= xor_reduce(w_e_data_func(40 to 47)); + w_e_parity(6) <= xor_reduce(w_e_data_func(48 to 55)); + w_e_parity(7) <= xor_reduce(w_e_data_func(56 to 63)); +end generate; + + r0_data_out <= r0_array_data(64-regsize to 69+regsize/8); + r1_data_out <= r1_array_data(64-regsize to 69+regsize/8); + r2_data_out <= r2_array_data(64-regsize to 69+regsize/8); + r3_data_out <= r3_array_data(64-regsize to 69+regsize/8); + +gpr_64b_data_out : if regsize = 64 generate + w_e_data_func_par <= w_e_data_func & w_e_parity & "000000"; + + with perr_sm_q(3) select + w_e_data <= w_e_data_func_par when '0', + perr_write_data_q when others; + + w_l_data <= w_l_data_func; +end generate; +gpr_32b_data_out : if regsize = 32 generate + w_e_data_func_par <= w_e_data_func & w_e_parity & "0000000000"; + + with perr_sm_q(3) select + w_e_data <= (0 to 31 => tidn) & w_e_data_func_par when '0', + (0 to 31 => tidn) & perr_write_data_q when others; + + w_l_data <= (0 to 31 => tidn) & w_l_data_func; +end generate; + + with w_e_addr_func(6 to 7) select + w_e_tid <= "0100" when "01", + "0010" when "10", + "0001" when "11", + "1000" when others; + + perr_inj <= or_reduce(w_e_tid and perr_inj_q) and perr_sm_q(0); + + w0e_data(64-regsize) <= w_e_data(64-regsize) xor perr_inj; + w0e_data(65-regsize to 69+regsize/8) <= w_e_data(65-regsize to 69+regsize/8); + + w1e_data(64-regsize) <= w_e_data(64-regsize); + w1e_data(65-regsize to 69+regsize/8) <= w_e_data(65-regsize to 69+regsize/8); + + r0_read_enable <= r0_en or lbist_en; + with perr_sm_q(1) select + r1_read_enable <=(r1_en or lbist_en) when '0', + '1' when others; + r2_read_enable <=(r2_en or lbist_en); + with perr_sm_q(1) select + r3_read_enable <=(r3_en or lbist_en) when '0', + '1' when others; + + r0_read_addr <= r0_addr_func; + with perr_sm_q(1) select + r1_read_addr <= r1_addr_func when '0', + perr_addr_q when others; + r2_read_addr <= r2_addr_func; + with perr_sm_q(1) select + r3_read_addr <= (others=>tidn) when '0', + perr_addr_q when others; + + with perr_sm_q(3) select + w_e_enable <= w_e_act when '0', + '1' when others; + w_l_enable <= w_l_act; + + with perr_sm_q(3) select + w_e_addr <= w_e_addr_func when '0', + perr_addr_q when others; + w_l_addr <= w_l_addr_func; + + + +gpr_parity_chk : for i in (8-regsize/8) to 7 generate + gpr_do0_par(i) <= xor_reduce(r0_array_data_q(8*i to 8*i+7)); + gpr_do1_par(i) <= xor_reduce(r1_array_data_q(8*i to 8*i+7)); + gpr_do2_par(i) <= xor_reduce(r2_array_data_q(8*i to 8*i+7)); + gpr_do3_par(i) <= xor_reduce(r3_array_data_q(8*i to 8*i+7)); +end generate; + + gpr_do0_par_err <= r0_read_val_q and (r0_array_data_q(64 to 63+regsize/8) /= gpr_do0_par); + gpr_do1_par_err <= r1_read_val_q and (r1_array_data_q(64 to 63+regsize/8) /= gpr_do1_par); + gpr_do2_par_err <= r2_read_val_q and (r2_array_data_q(64 to 63+regsize/8) /= gpr_do2_par); + gpr_do3_par_err <= r3_read_val_q and (r3_array_data_q(64 to 63+regsize/8) /= gpr_do3_par); + + ex2_regfile_err_det <= perr_sm_q(0) and (gpr_do0_par_err_q or gpr_do1_par_err_q or gpr_do2_par_err_q); + gpr_cpl_ex3_regfile_err_det <= ex3_regfile_err_det_q; + + + perr_addr_d <= r0_read_addr_2_q when (gpr_do0_par_err_q and perr_sm_q(0)) = '1' else + r1_read_addr_2_q when (gpr_do1_par_err_q and perr_sm_q(0)) = '1' else + r2_read_addr_2_q when (gpr_do2_par_err_q and perr_sm_q(0)) = '1' else + perr_addr_q; + perr_direction_d <= "10" when ((gpr_do0_par_err_q or gpr_do1_par_err_q) and perr_sm_q(0)) = '1' else + "01" when ( gpr_do2_par_err_q and perr_sm_q(0)) = '1' else + perr_direction_q; + + perr_write_data_sel <= perr_direction_q and (0 to 1 => perr_sm_q(2)); + with perr_write_data_sel select + perr_write_data_d <= r1_array_data when "01", + r3_array_data when "10", + (others=>tidn) when others; + + + perr_sm_d <= ("10000" and (0 to 4 => perr_sm_next(0))) or + ("01000" and (0 to 4 => perr_sm_next(1))) or + ("00100" and (0 to 4 => perr_sm_next(2))) or + ("00010" and (0 to 4 => perr_sm_next(3))) or + ("00001" and (0 to 4 => perr_sm_next(4))) or + (perr_sm_q and (0 to 4 => not (or_reduce(perr_sm_next)))); + + perr_sm_next(0) <= perr_sm_q(4); + gpr_cpl_regfile_seq_end <= perr_sm_q(3); + + perr_sm_next(1) <= perr_sm_q(0) and err_seq_0_q; + + perr_sm_next(2) <= perr_sm_q(1); + + perr_sm_next(3) <= perr_sm_q(2); + perr_sm_next(4) <= perr_sm_q(3); + + with perr_addr_q(6 to 7) select + perr_tid <= "1000" when "00", + "0100" when "01", + "0010" when "10", + "0001" when others; + + perr_ue <= perr_sm_q(4) and + ((perr_direction_q(0) and gpr_do3_par_err_q) or + (perr_direction_q(1) and gpr_do1_par_err_q)); + + perr_ce <= perr_sm_q(4) and not perr_ue; + + err_regfile_parity_d <= gate(perr_tid,perr_ce); + err_regfile_ue_d <= gate(perr_tid,perr_ue); + + wthru_r0_w_e_d <= (r0_addr_func = w_e_addr_func) and w_e_act; + wthru_r1_w_e_d <= (r1_addr_func = w_e_addr_func) and w_e_act; + wthru_r2_w_e_d <= (r2_addr_func = w_e_addr_func) and w_e_act; + wthru_r3_w_e_d <= (r3_addr_func = w_e_addr_func) and w_e_act; + + wthru_r0_w_l_d <= (r0_addr_func = w_l_addr_func) and w_l_act; + wthru_r1_w_l_d <= (r1_addr_func = w_l_addr_func) and w_l_act; + wthru_r2_w_l_d <= (r2_addr_func = w_l_addr_func) and w_l_act; + wthru_r3_w_l_d <= (r3_addr_func = w_l_addr_func) and w_l_act; + + r0_byp_r <= not (wthru_r0_w_e_q or wthru_r0_w_l_q); + r1_byp_r <= not (wthru_r1_w_e_q or wthru_r1_w_l_q); + r2_byp_r <= not (wthru_r2_w_e_q or wthru_r2_w_l_q); + r3_byp_r <= not (wthru_r3_w_e_q or wthru_r3_w_l_q); + + + gpr_debug <= perr_sm_q(0 to 3) & perr_direction_q & perr_addr_q(0 to 7) & + wthru_r0_w_e_q & wthru_r0_w_l_q & + wthru_r1_w_e_q & wthru_r1_w_l_q & + wthru_r2_w_e_q & wthru_r2_w_l_q & + wthru_r3_w_e_q & wthru_r3_w_l_q; + + xu_gpr_a : entity tri.tri_144x78_2r2w_eco(tri_144x78_2r2w_eco) + generic map( + expand_type => expand_type) + port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + abist_en => abist_en, + lbist_en => lbist_en, + abist_raw_dc_b => abist_raw_dc_b, + r0e_abist_comp_en => r0e_abist_comp_en, + r1e_abist_comp_en => r1e_abist_comp_en, + lcb_act_dis_dc => lcb_act_dis_dc, + lcb_clkoff_dc_b => lcb_clkoff_dc_b, + lcb_d_mode_dc => lcb_d_mode_dc, + lcb_delay_lclkr_dc => arr_delay_lclkr_dc, + lcb_fce_0 => lcb_fce_0, + lcb_mpw1_dc_b => arr_mpw1_dc_b, + lcb_mpw2_dc_b => lcb_mpw2_dc_b, + lcb_scan_diag_dc => lcb_scan_diag_dc, + lcb_scan_dis_dc_b => lcb_scan_dis_dc_b, + lcb_sg_0 => lcb_sg_0, + lcb_abst_sl_thold_0 => lcb_abst_sl_thold_0, + lcb_ary_nsl_thold_0 => lcb_ary_nsl_thold_0, + lcb_time_sl_thold_0 => lcb_time_sl_thold_0, + lcb_obs0_sg_0 => lcb_sg_0, + lcb_obs0_sl_thold_0 => lcb_abst_sl_thold_0, + lcb_time_sg_0 => lcb_sg_0, + obs0_scan_in => siv_abst(0), + obs0_scan_out => sov_abst(0), + lcb_obs1_sg_0 => lcb_sg_0, + lcb_obs1_sl_thold_0 => lcb_abst_sl_thold_0, + obs1_scan_in => siv_abst(1), + obs1_scan_out => sov_abst(1), + time_scan_in => siv_time(0), + time_scan_out => sov_time(0), + r_scan_in => siv_abst(2), + r_scan_out => sov_abst(2), + w_scan_in => siv_abst(3), + w_scan_out => sov_abst(3), + lcb_bolt_sl_thold_0 => lcb_bolt_sl_thold_0, + pc_bo_enable_2 => bo_enable_2, + pc_bo_reset => pc_xu_bo_reset, + pc_bo_unload => pc_xu_bo_unload, + pc_bo_load => pc_xu_bo_load, + pc_bo_shdata => pc_xu_bo_shdata, + pc_bo_select => pc_xu_bo_select(0), + bo_pc_failout => xu_pc_bo_fail(0), + bo_pc_diagloop => xu_pc_bo_diagout(0), + tri_lcb_mpw1_dc_b => mpw1_dc_b, + tri_lcb_mpw2_dc_b => mpw2_dc_b, + tri_lcb_delay_lclkr_dc => delay_lclkr_dc, + tri_lcb_clkoff_dc_b => clkoff_dc_b, + tri_lcb_act_dis_dc => tidn, + r0e_act => r0_read_enable, + r0e_en_func => r0_read_enable, + r0e_en_abist => r0e_en_abist, + r0e_sel_lbist => r0e_sel_lbist, + r0e_addr_func => r0_read_addr, + r0e_addr_abist => r0e_addr_abist, + r0e_data_out => r0_array_data, + r0e_byp_e => wthru_r0_w_e_q, + r0e_byp_l => wthru_r0_w_l_q, + r0e_byp_r => r0_byp_r, + r1e_act => r1_read_enable, + r1e_en_func => r1_read_enable, + r1e_en_abist => r1e_en_abist, + r1e_sel_lbist => r1e_sel_lbist, + r1e_addr_func => r1_read_addr, + r1e_addr_abist => r1e_addr_abist, + r1e_data_out => r1_array_data, + r1e_byp_e => wthru_r1_w_e_q, + r1e_byp_l => wthru_r1_w_l_q, + r1e_byp_r => r1_byp_r, + w0e_act => w_e_enable, + w0e_en_func => w_e_enable, + w0e_en_abist => w0e_en_abist, + w0e_addr_func => w_e_addr, + w0e_addr_abist => w0e_addr_abist, + w0e_data_func => w0e_data, + w0e_data_abist => w0e_data_abist, + w0l_act => w_l_enable, + w0l_en_func => w_l_enable, + w0l_en_abist => w0l_en_abist, + w0l_addr_func => w_l_addr, + w0l_addr_abist => w0l_addr_abist, + w0l_data_func => w_l_data, + w0l_data_abist => w0l_data_abist); + + xu_gpr_b : entity tri.tri_144x78_2r2w_eco(tri_144x78_2r2w_eco) + generic map( + expand_type => expand_type) + port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + abist_en => abist_en, + lbist_en => lbist_en, + abist_raw_dc_b => abist_raw_dc_b, + r0e_abist_comp_en => r0e_abist_comp_en, + r1e_abist_comp_en => r1e_abist_comp_en, + lcb_act_dis_dc => lcb_act_dis_dc, + lcb_clkoff_dc_b => lcb_clkoff_dc_b, + lcb_d_mode_dc => lcb_d_mode_dc, + lcb_delay_lclkr_dc => arr_delay_lclkr_dc, + lcb_fce_0 => lcb_fce_0, + lcb_mpw1_dc_b => arr_mpw1_dc_b, + lcb_mpw2_dc_b => lcb_mpw2_dc_b, + lcb_scan_diag_dc => lcb_scan_diag_dc, + lcb_scan_dis_dc_b => lcb_scan_dis_dc_b, + lcb_sg_0 => lcb_sg_0, + lcb_abst_sl_thold_0 => lcb_abst_sl_thold_0, + lcb_ary_nsl_thold_0 => lcb_ary_nsl_thold_0, + lcb_time_sg_0 => lcb_sg_0, + lcb_time_sl_thold_0 => lcb_time_sl_thold_0, + lcb_obs0_sg_0 => lcb_sg_0, + lcb_obs0_sl_thold_0 => lcb_abst_sl_thold_0, + obs0_scan_in => siv_abst(4), + obs0_scan_out => sov_abst(4), + lcb_obs1_sg_0 => lcb_sg_0, + lcb_obs1_sl_thold_0 => lcb_abst_sl_thold_0, + obs1_scan_in => siv_abst(5), + obs1_scan_out => sov_abst(5), + time_scan_in => siv_time(1), + time_scan_out => sov_time(1), + r_scan_in => siv_abst(6), + r_scan_out => sov_abst(6), + w_scan_in => siv_abst(7), + w_scan_out => sov_abst(7), + lcb_bolt_sl_thold_0 => lcb_bolt_sl_thold_0, + pc_bo_enable_2 => bo_enable_2, + pc_bo_reset => pc_xu_bo_reset, + pc_bo_unload => pc_xu_bo_unload, + pc_bo_load => pc_xu_bo_load, + pc_bo_shdata => pc_xu_bo_shdata, + pc_bo_select => pc_xu_bo_select(1), + bo_pc_failout => xu_pc_bo_fail(1), + bo_pc_diagloop => xu_pc_bo_diagout(1), + tri_lcb_mpw1_dc_b => mpw1_dc_b, + tri_lcb_mpw2_dc_b => mpw2_dc_b, + tri_lcb_delay_lclkr_dc => delay_lclkr_dc, + tri_lcb_clkoff_dc_b => clkoff_dc_b, + tri_lcb_act_dis_dc => tidn, + r0e_act => r2_read_enable, + r0e_en_func => r2_read_enable, + r0e_en_abist => r0e_en_abist, + r0e_sel_lbist => r0e_sel_lbist, + r0e_addr_func => r2_read_addr, + r0e_addr_abist => r0e_addr_abist, + r0e_data_out => r2_array_data, + r0e_byp_e => wthru_r2_w_e_q, + r0e_byp_l => wthru_r2_w_l_q, + r0e_byp_r => r2_byp_r, + r1e_act => r3_read_enable, + r1e_en_func => r3_read_enable, + r1e_en_abist => r1e_en_abist, + r1e_sel_lbist => r1e_sel_lbist, + r1e_addr_func => r3_read_addr, + r1e_addr_abist => r1e_addr_abist, + r1e_data_out => r3_array_data, + r1e_byp_e => wthru_r3_w_e_q, + r1e_byp_l => wthru_r3_w_l_q, + r1e_byp_r => r3_byp_r, + w0e_act => w_e_enable, + w0e_en_func => w_e_enable, + w0e_en_abist => w0e_en_abist, + w0e_addr_func => w_e_addr, + w0e_addr_abist => w0e_addr_abist, + w0e_data_func => w1e_data, + w0e_data_abist => w0e_data_abist, + w0l_act => w_l_enable, + w0l_en_func => w_l_enable, + w0l_en_abist => w0l_en_abist, + w0l_addr_func => w_l_addr, + w0l_addr_abist => w0l_addr_abist, + w0l_data_func => w_l_data, + w0l_data_abist => w0l_data_abist); + +perv_lcbctrl_regf_0: tri_lcbcntl_array_mac +generic map (expand_type => expand_type) +port map ( + vdd => vdd, + gnd => gnd, + sg => lcb_sg_0, + nclk => nclk, + scan_in => gpr_gptr_scan_in, + scan_diag_dc => an_ac_scan_diag_dc, + thold => lcb_gptr_sl_thold_0, + clkoff_dc_b => lcb_clkoff_dc_b(0), + delay_lclkr_dc => lcb_delay_lclkr_dc, + act_dis_dc => lcb_act_dis_dc, + d_mode_dc => lcb_d_mode_dc, + mpw1_dc_b => lcb_mpw1_dc_b, + mpw2_dc_b => lcb_mpw2_dc_b, + scan_out => gpr_gptr_scan_out); + + lcb_clkoff_dc_b(1) <= lcb_clkoff_dc_b(0); + + arr_delay_lclkr_dc(0) <= lcb_delay_lclkr_dc(0); + arr_delay_lclkr_dc(1) <= lcb_delay_lclkr_dc(1); + arr_delay_lclkr_dc(2) <= lcb_delay_lclkr_dc(0); + arr_delay_lclkr_dc(3) <= lcb_delay_lclkr_dc(1); + arr_delay_lclkr_dc(4) <= lcb_delay_lclkr_dc(2); + arr_delay_lclkr_dc(5) <= lcb_delay_lclkr_dc(3); + arr_delay_lclkr_dc(6) <= lcb_delay_lclkr_dc(4); + arr_delay_lclkr_dc(7) <= lcb_delay_lclkr_dc(4); + arr_delay_lclkr_dc(8) <= lcb_delay_lclkr_dc(3); + arr_delay_lclkr_dc(9) <= lcb_delay_lclkr_dc(3); + + arr_mpw1_dc_b(1) <= lcb_mpw1_dc_b(0); + arr_mpw1_dc_b(2) <= lcb_mpw1_dc_b(0); + arr_mpw1_dc_b(3) <= lcb_mpw1_dc_b(0); + arr_mpw1_dc_b(4) <= lcb_mpw1_dc_b(1); + arr_mpw1_dc_b(5) <= lcb_mpw1_dc_b(2); + arr_mpw1_dc_b(6) <= lcb_mpw1_dc_b(3); + arr_mpw1_dc_b(7) <= lcb_mpw1_dc_b(4); + arr_mpw1_dc_b(8) <= lcb_mpw1_dc_b(2); + arr_mpw1_dc_b(9) <= lcb_mpw1_dc_b(2); + + ex3_regfile_err_det_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_regfile_err_det_offset), + scout => sov(ex3_regfile_err_det_offset), + din => ex2_regfile_err_det, + dout => ex3_regfile_err_det_q); + gpr_do0_par_err_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(gpr_do0_par_err_offset), + scout => sov(gpr_do0_par_err_offset), + din => gpr_do0_par_err , + dout => gpr_do0_par_err_q); + gpr_do1_par_err_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(gpr_do1_par_err_offset), + scout => sov(gpr_do1_par_err_offset), + din => gpr_do1_par_err , + dout => gpr_do1_par_err_q); + gpr_do2_par_err_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(gpr_do2_par_err_offset), + scout => sov(gpr_do2_par_err_offset), + din => gpr_do2_par_err , + dout => gpr_do2_par_err_q); + gpr_do3_par_err_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(gpr_do3_par_err_offset), + scout => sov(gpr_do3_par_err_offset), + din => gpr_do3_par_err , + dout => gpr_do3_par_err_q); + r0_array_data_latch : tri_rlmreg_p + generic map (width => r0_array_data_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => r0_read_enable_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(r0_array_data_offset to r0_array_data_offset + r0_array_data_q'length-1), + scout => sov(r0_array_data_offset to r0_array_data_offset + r0_array_data_q'length-1), + din => r0_array_data(0 to 63+regsize/8), + dout => r0_array_data_q); + r0_read_addr_latch : tri_regk + generic map (width => r0_read_addr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => r0_read_enable , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => r0_read_addr , + dout => r0_read_addr_q); + r0_read_addr_1_latch : tri_rlmreg_p + generic map (width => r0_read_addr_1_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => r0_read_enable_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(r0_read_addr_1_offset to r0_read_addr_1_offset + r0_read_addr_1_q'length-1), + scout => sov(r0_read_addr_1_offset to r0_read_addr_1_offset + r0_read_addr_1_q'length-1), + din => r0_read_addr_q , + dout => r0_read_addr_1_q); + r0_read_addr_2_latch : tri_regk + generic map (width => r0_read_addr_2_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => r0_read_val_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => r0_read_addr_1_q , + dout => r0_read_addr_2_q); + r0_read_enable_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => r0_read_enable , + dout(0) => r0_read_enable_q); + r0_read_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(r0_read_val_offset), + scout => sov(r0_read_val_offset), + din => r0_read_enable_q , + dout => r0_read_val_q); + r1_array_data_latch : tri_rlmreg_p + generic map (width => r1_array_data_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => r1_read_enable_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(r1_array_data_offset to r1_array_data_offset + r1_array_data_q'length-1), + scout => sov(r1_array_data_offset to r1_array_data_offset + r1_array_data_q'length-1), + din => r1_array_data(0 to 63+regsize/8), + dout => r1_array_data_q); + r1_read_addr_latch : tri_regk + generic map (width => r1_read_addr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => r1_read_enable , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => r1_read_addr , + dout => r1_read_addr_q); + r1_read_addr_1_latch : tri_rlmreg_p + generic map (width => r1_read_addr_1_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => r1_read_enable_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(r1_read_addr_1_offset to r1_read_addr_1_offset + r1_read_addr_1_q'length-1), + scout => sov(r1_read_addr_1_offset to r1_read_addr_1_offset + r1_read_addr_1_q'length-1), + din => r1_read_addr_q , + dout => r1_read_addr_1_q); + r1_read_addr_2_latch : tri_regk + generic map (width => r1_read_addr_2_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => r1_read_val_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => r1_read_addr_1_q , + dout => r1_read_addr_2_q); + r1_read_enable_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => r1_read_enable , + dout(0) => r1_read_enable_q); + r1_read_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(r1_read_val_offset), + scout => sov(r1_read_val_offset), + din => r1_read_enable_q , + dout => r1_read_val_q); + r2_array_data_latch : tri_rlmreg_p + generic map (width => r2_array_data_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => r2_read_enable_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(r2_array_data_offset to r2_array_data_offset + r2_array_data_q'length-1), + scout => sov(r2_array_data_offset to r2_array_data_offset + r2_array_data_q'length-1), + din => r2_array_data(0 to 63+regsize/8), + dout => r2_array_data_q); + r2_read_addr_latch : tri_regk + generic map (width => r2_read_addr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => r2_read_enable , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => r2_read_addr , + dout => r2_read_addr_q); + r2_read_addr_1_latch : tri_rlmreg_p + generic map (width => r2_read_addr_1_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => r2_read_enable_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(r2_read_addr_1_offset to r2_read_addr_1_offset + r2_read_addr_1_q'length-1), + scout => sov(r2_read_addr_1_offset to r2_read_addr_1_offset + r2_read_addr_1_q'length-1), + din => r2_read_addr_q , + dout => r2_read_addr_1_q); + r2_read_addr_2_latch : tri_regk + generic map (width => r2_read_addr_2_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => r2_read_val_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => r2_read_addr_1_q , + dout => r2_read_addr_2_q); + r2_read_enable_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => r2_read_enable , + dout(0) => r2_read_enable_q); + r2_read_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(r2_read_val_offset), + scout => sov(r2_read_val_offset), + din => r2_read_enable_q , + dout => r2_read_val_q); + r3_array_data_latch : tri_rlmreg_p + generic map (width => r3_array_data_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => r3_read_enable_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(r3_array_data_offset to r3_array_data_offset + r3_array_data_q'length-1), + scout => sov(r3_array_data_offset to r3_array_data_offset + r3_array_data_q'length-1), + din => r3_array_data(0 to 63+regsize/8), + dout => r3_array_data_q); + r3_read_enable_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => r3_read_enable , + dout(0) => r3_read_enable_q); + r3_read_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(r3_read_val_offset), + scout => sov(r3_read_val_offset), + din => r3_read_enable_q , + dout => r3_read_val_q); + perr_addr_latch : tri_rlmreg_p + generic map (width => perr_addr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(perr_addr_offset to perr_addr_offset + perr_addr_q'length-1), + scout => sov(perr_addr_offset to perr_addr_offset + perr_addr_q'length-1), + din => perr_addr_d, + dout => perr_addr_q); + perr_direction_latch : tri_rlmreg_p + generic map (width => perr_direction_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(perr_direction_offset to perr_direction_offset + perr_direction_q'length-1), + scout => sov(perr_direction_offset to perr_direction_offset + perr_direction_q'length-1), + din => perr_direction_d, + dout => perr_direction_q); + perr_inj_latch : tri_rlmreg_p + generic map (width => perr_inj_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(perr_inj_offset to perr_inj_offset + perr_inj_q'length-1), + scout => sov(perr_inj_offset to perr_inj_offset + perr_inj_q'length-1), + din => pc_xu_inj_regfile_parity , + dout => perr_inj_q); + perr_sm_latch : tri_rlmreg_p + generic map (width => perr_sm_q'length, init => 2**(perr_sm_q'length-1), expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(perr_sm_offset to perr_sm_offset + perr_sm_q'length-1), + scout => sov(perr_sm_offset to perr_sm_offset + perr_sm_q'length-1), + din => perr_sm_d, + dout => perr_sm_q); + perr_write_data_latch : tri_rlmreg_p + generic map (width => perr_write_data_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => perr_sm_q(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(perr_write_data_offset to perr_write_data_offset + perr_write_data_q'length-1), + scout => sov(perr_write_data_offset to perr_write_data_offset + perr_write_data_q'length-1), + din => perr_write_data_d, + dout => perr_write_data_q); + err_regfile_parity_latch : tri_rlmreg_p + generic map (width => err_regfile_parity_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(err_regfile_parity_offset to err_regfile_parity_offset + err_regfile_parity_q'length-1), + scout => sov(err_regfile_parity_offset to err_regfile_parity_offset + err_regfile_parity_q'length-1), + din => err_regfile_parity_d, + dout => err_regfile_parity_q); + err_regfile_ue_latch : tri_rlmreg_p + generic map (width => err_regfile_ue_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(err_regfile_ue_offset to err_regfile_ue_offset + err_regfile_ue_q'length-1), + scout => sov(err_regfile_ue_offset to err_regfile_ue_offset + err_regfile_ue_q'length-1), + din => err_regfile_ue_d, + dout => err_regfile_ue_q); + err_seq_0_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(err_seq_0_offset), + scout => sov(err_seq_0_offset), + din => cpl_gpr_regfile_seq_beg , + dout => err_seq_0_q); + wthru_r0_w_e_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(wthru_r0_w_e_offset), + scout => sov(wthru_r0_w_e_offset), + din => wthru_r0_w_e_d, + dout => wthru_r0_w_e_q); + wthru_r0_w_l_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(wthru_r0_w_l_offset), + scout => sov(wthru_r0_w_l_offset), + din => wthru_r0_w_l_d, + dout => wthru_r0_w_l_q); + wthru_r1_w_e_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(wthru_r1_w_e_offset), + scout => sov(wthru_r1_w_e_offset), + din => wthru_r1_w_e_d, + dout => wthru_r1_w_e_q); + wthru_r1_w_l_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(wthru_r1_w_l_offset), + scout => sov(wthru_r1_w_l_offset), + din => wthru_r1_w_l_d, + dout => wthru_r1_w_l_q); + wthru_r2_w_e_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(wthru_r2_w_e_offset), + scout => sov(wthru_r2_w_e_offset), + din => wthru_r2_w_e_d, + dout => wthru_r2_w_e_q); + wthru_r2_w_l_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(wthru_r2_w_l_offset), + scout => sov(wthru_r2_w_l_offset), + din => wthru_r2_w_l_d, + dout => wthru_r2_w_l_q); + wthru_r3_w_e_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(wthru_r3_w_e_offset), + scout => sov(wthru_r3_w_e_offset), + din => wthru_r3_w_e_d, + dout => wthru_r3_w_e_q); + wthru_r3_w_l_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(wthru_r3_w_l_offset), + scout => sov(wthru_r3_w_l_offset), + din => wthru_r3_w_l_d, + dout => wthru_r3_w_l_q); + + siv(0 to siv'right) <= sov(1 to siv'right) & scan_in; + scan_out <= sov(0); + + siv_abst(0 to siv_abst'right) <= sov_abst(1 to siv_abst'right) & gpr_abst_scan_in; + gpr_abst_scan_out <= sov_abst(0); + + siv_time(0 to siv_time'right) <= sov_time(1 to siv_time'right) & gpr_time_scan_in; + gpr_time_scan_out <= sov_time(0); + + +end architecture xuq_fxu_gpr; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_fxu_spr.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_fxu_spr.vhdl new file mode 100644 index 0000000..67928ae --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_fxu_spr.vhdl @@ -0,0 +1,271 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee,ibm,support,work,tri; +use ieee.std_logic_1164.all; +use support.power_logic_pkg.all; +use ibm.std_ulogic_function_support.all; +use tri.tri_latches_pkg.all; + +entity xuq_fxu_spr is +generic( + hvmode : integer := 1; + a2mode : integer := 1; + expand_type : integer := 2; + threads : integer := 4; + regsize : integer := 64; + eff_ifar : integer := 62); +port( + nclk : in clk_logic; + + d_mode_dc : in std_ulogic; + delay_lclkr_dc : in std_ulogic; + mpw1_dc_b : in std_ulogic; + mpw2_dc_b : in std_ulogic; + + func_sl_force : in std_ulogic; + func_sl_thold_0_b : in std_ulogic; + func_nsl_force : in std_ulogic; + func_nsl_thold_0_b : in std_ulogic; + sg_0 : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + ex1_tid : in std_ulogic_vector(0 to threads-1); + ex1_instr : in std_ulogic_vector(11 to 20); + dec_spr_ex1_is_mfspr : in std_ulogic; + dec_spr_ex1_is_mtspr : in std_ulogic; + + ex6_val : in std_ulogic_vector(0 to threads-1); + ex6_spr_wd : in std_ulogic_vector(64-regsize to 63); + + fspr_byp_ex3_spr_rt : out std_ulogic_vector(64-regsize to 63); + mux_spr_ex2_rt : in std_ulogic_vector(64-regsize to 63); + + ex2_is_any_load_dac : in std_ulogic; + ex2_is_any_store_dac : in std_ulogic; + + xu_lsu_ex4_dvc1_en : out std_ulogic; + xu_lsu_ex4_dvc2_en : out std_ulogic; + lsu_xu_ex2_dvc1_st_cmp : in std_ulogic_vector(8-regsize/8 to 7); + lsu_xu_ex2_dvc2_st_cmp : in std_ulogic_vector(8-regsize/8 to 7); + lsu_xu_ex8_dvc1_ld_cmp : in std_ulogic_vector(8-regsize/8 to 7); + lsu_xu_ex8_dvc2_ld_cmp : in std_ulogic_vector(8-regsize/8 to 7); + lsu_xu_rel_dvc1_en : in std_ulogic; + lsu_xu_rel_dvc2_en : in std_ulogic; + lsu_xu_rel_dvc_thrd_id : in std_ulogic_vector(0 to 3); + lsu_xu_rel_dvc1_cmp : in std_ulogic_vector(8-regsize/8 to 7); + lsu_xu_rel_dvc2_cmp : in std_ulogic_vector(8-regsize/8 to 7); + + fxu_cpl_ex3_dac1r_cmpr_async : out std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac2r_cmpr_async : out std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac1r_cmpr : out std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac2r_cmpr : out std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac3r_cmpr : out std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac4r_cmpr : out std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac1w_cmpr : out std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac2w_cmpr : out std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac3w_cmpr : out std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac4w_cmpr : out std_ulogic_vector(0 to threads-1); + + spr_bit_act : in std_ulogic; + spr_msr_pr : in std_ulogic_vector(0 to threads-1); + spr_msr_ds : in std_ulogic_vector(0 to threads-1); + spr_dbcr0_dac1 : in std_ulogic_vector(0 to 2*threads-1); + spr_dbcr0_dac2 : in std_ulogic_vector(0 to 2*threads-1); + spr_dbcr0_dac3 : in std_ulogic_vector(0 to 2*threads-1); + spr_dbcr0_dac4 : in std_ulogic_vector(0 to 2*threads-1); + + spr_dbcr3_ivc : out std_ulogic_vector(0 to threads-1); + + vdd : inout power_logic; + gnd : inout power_logic +); + +-- synopsys translate_off + +-- synopsys translate_on +end xuq_fxu_spr; +architecture xuq_fxu_spr of xuq_fxu_spr is + + +signal siv : std_ulogic_vector(0 to threads); +signal sov : std_ulogic_vector(0 to threads); +signal cspr_tspr_ex6_is_mtspr : std_ulogic; +signal cspr_tspr_ex6_instr : std_ulogic_vector(11 to 20); +signal cspr_tspr_ex2_instr : std_ulogic_vector(11 to 20); +signal tspr_cspr_ex2_tspr_rt : std_ulogic_vector(0 to regsize*threads-1); +signal tspr_cspr_dbcr2_dac1us : std_ulogic_vector(0 to 2*threads-1); +signal tspr_cspr_dbcr2_dac1er : std_ulogic_vector(0 to 2*threads-1); +signal tspr_cspr_dbcr2_dac2us : std_ulogic_vector(0 to 2*threads-1); +signal tspr_cspr_dbcr2_dac2er : std_ulogic_vector(0 to 2*threads-1); +signal tspr_cspr_dbcr3_dac3us : std_ulogic_vector(0 to 2*threads-1); +signal tspr_cspr_dbcr3_dac3er : std_ulogic_vector(0 to 2*threads-1); +signal tspr_cspr_dbcr3_dac4us : std_ulogic_vector(0 to 2*threads-1); +signal tspr_cspr_dbcr3_dac4er : std_ulogic_vector(0 to 2*threads-1); +signal tspr_cspr_dbcr2_dac12m : std_ulogic_vector(0 to threads-1); +signal tspr_cspr_dbcr3_dac34m : std_ulogic_vector(0 to threads-1); +signal tspr_cspr_dbcr2_dvc1m : std_ulogic_vector(0 to 2*threads-1); +signal tspr_cspr_dbcr2_dvc2m : std_ulogic_vector(0 to 2*threads-1); +signal tspr_cspr_dbcr2_dvc1be : std_ulogic_vector(0 to 8*threads-1); +signal tspr_cspr_dbcr2_dvc2be : std_ulogic_vector(0 to 8*threads-1); + +begin + + +xu_fxu_spr_cspr : entity work.xuq_fxu_spr_cspr(xuq_fxu_spr_cspr) +generic map( + hvmode => hvmode, + a2mode => a2mode, + expand_type => expand_type, + threads => threads, + regsize => regsize, + eff_ifar => eff_ifar) +port map( + nclk => nclk, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc, + mpw1_dc_b => mpw1_dc_b, + mpw2_dc_b => mpw2_dc_b, + func_sl_force => func_sl_force, + func_sl_thold_0_b => func_sl_thold_0_b, + func_nsl_force => func_nsl_force, + func_nsl_thold_0_b => func_nsl_thold_0_b, + sg_0 => sg_0, + scan_in => siv(threads), + scan_out => sov(threads), + ex1_instr => ex1_instr, + ex1_tid => ex1_tid, + dec_spr_ex1_is_mfspr => dec_spr_ex1_is_mfspr, + dec_spr_ex1_is_mtspr => dec_spr_ex1_is_mtspr, + ex6_valid => ex6_val, + ex6_spr_wd => ex6_spr_wd, + cspr_tspr_ex6_is_mtspr => cspr_tspr_ex6_is_mtspr, + cspr_tspr_ex6_instr => cspr_tspr_ex6_instr, + cspr_tspr_ex2_instr => cspr_tspr_ex2_instr, + tspr_cspr_ex2_tspr_rt => tspr_cspr_ex2_tspr_rt, + fspr_byp_ex3_spr_rt => fspr_byp_ex3_spr_rt, + mux_spr_ex2_rt => mux_spr_ex2_rt, + ex2_is_any_load_dac => ex2_is_any_load_dac, + ex2_is_any_store_dac => ex2_is_any_store_dac, + xu_lsu_ex4_dvc1_en => xu_lsu_ex4_dvc1_en, + xu_lsu_ex4_dvc2_en => xu_lsu_ex4_dvc2_en, + lsu_xu_ex2_dvc1_st_cmp => lsu_xu_ex2_dvc1_st_cmp, + lsu_xu_ex2_dvc2_st_cmp => lsu_xu_ex2_dvc2_st_cmp, + lsu_xu_ex8_dvc1_ld_cmp => lsu_xu_ex8_dvc1_ld_cmp, + lsu_xu_ex8_dvc2_ld_cmp => lsu_xu_ex8_dvc2_ld_cmp, + lsu_xu_rel_dvc1_en => lsu_xu_rel_dvc1_en, + lsu_xu_rel_dvc2_en => lsu_xu_rel_dvc2_en, + lsu_xu_rel_dvc_thrd_id => lsu_xu_rel_dvc_thrd_id, + lsu_xu_rel_dvc1_cmp => lsu_xu_rel_dvc1_cmp, + lsu_xu_rel_dvc2_cmp => lsu_xu_rel_dvc2_cmp, + fxu_cpl_ex3_dac1r_cmpr_async => fxu_cpl_ex3_dac1r_cmpr_async, + fxu_cpl_ex3_dac2r_cmpr_async => fxu_cpl_ex3_dac2r_cmpr_async, + fxu_cpl_ex3_dac1r_cmpr => fxu_cpl_ex3_dac1r_cmpr, + fxu_cpl_ex3_dac2r_cmpr => fxu_cpl_ex3_dac2r_cmpr, + fxu_cpl_ex3_dac3r_cmpr => fxu_cpl_ex3_dac3r_cmpr, + fxu_cpl_ex3_dac4r_cmpr => fxu_cpl_ex3_dac4r_cmpr, + fxu_cpl_ex3_dac1w_cmpr => fxu_cpl_ex3_dac1w_cmpr, + fxu_cpl_ex3_dac2w_cmpr => fxu_cpl_ex3_dac2w_cmpr, + fxu_cpl_ex3_dac3w_cmpr => fxu_cpl_ex3_dac3w_cmpr, + fxu_cpl_ex3_dac4w_cmpr => fxu_cpl_ex3_dac4w_cmpr, + spr_bit_act => spr_bit_act, + spr_msr_pr => spr_msr_pr, + spr_msr_ds => spr_msr_ds, + spr_dbcr0_dac1 => spr_dbcr0_dac1, + spr_dbcr0_dac2 => spr_dbcr0_dac2, + spr_dbcr0_dac3 => spr_dbcr0_dac3, + spr_dbcr0_dac4 => spr_dbcr0_dac4, + tspr_cspr_dbcr2_dac1us => tspr_cspr_dbcr2_dac1us, + tspr_cspr_dbcr2_dac1er => tspr_cspr_dbcr2_dac1er, + tspr_cspr_dbcr2_dac2us => tspr_cspr_dbcr2_dac2us, + tspr_cspr_dbcr2_dac2er => tspr_cspr_dbcr2_dac2er, + tspr_cspr_dbcr3_dac3us => tspr_cspr_dbcr3_dac3us, + tspr_cspr_dbcr3_dac3er => tspr_cspr_dbcr3_dac3er, + tspr_cspr_dbcr3_dac4us => tspr_cspr_dbcr3_dac4us, + tspr_cspr_dbcr3_dac4er => tspr_cspr_dbcr3_dac4er, + tspr_cspr_dbcr2_dac12m => tspr_cspr_dbcr2_dac12m, + tspr_cspr_dbcr3_dac34m => tspr_cspr_dbcr3_dac34m, + tspr_cspr_dbcr2_dvc1m => tspr_cspr_dbcr2_dvc1m, + tspr_cspr_dbcr2_dvc2m => tspr_cspr_dbcr2_dvc2m, + tspr_cspr_dbcr2_dvc1be => tspr_cspr_dbcr2_dvc1be, + tspr_cspr_dbcr2_dvc2be => tspr_cspr_dbcr2_dvc2be, + + vdd => vdd, + gnd => gnd +); + +thread : for t in 0 to threads-1 generate +xu_fxu_spr_tspr : entity work.xuq_fxu_spr_tspr(xuq_fxu_spr_tspr) +generic map( + hvmode => hvmode, + a2mode => a2mode, + expand_type => expand_type, + regsize => regsize, + eff_ifar => eff_ifar) +port map( + nclk => nclk, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc, + mpw1_dc_b => mpw1_dc_b, + mpw2_dc_b => mpw2_dc_b, + func_sl_force => func_sl_force, + func_sl_thold_0_b => func_sl_thold_0_b, + sg_0 => sg_0, + scan_in => siv(t), + scan_out => sov(t), + cspr_tspr_ex2_instr => cspr_tspr_ex2_instr, + tspr_cspr_ex2_tspr_rt => tspr_cspr_ex2_tspr_rt(regsize*t to regsize*(t+1)-1), + ex6_val => ex6_val(t), + cspr_tspr_ex6_is_mtspr => cspr_tspr_ex6_is_mtspr, + cspr_tspr_ex6_instr => cspr_tspr_ex6_instr, + ex6_spr_wd => ex6_spr_wd, + tspr_cspr_dbcr2_dac1us => tspr_cspr_dbcr2_dac1us(2*t to 2*(t+1)-1), + tspr_cspr_dbcr2_dac1er => tspr_cspr_dbcr2_dac1er(2*t to 2*(t+1)-1), + tspr_cspr_dbcr2_dac2us => tspr_cspr_dbcr2_dac2us(2*t to 2*(t+1)-1), + tspr_cspr_dbcr2_dac2er => tspr_cspr_dbcr2_dac2er(2*t to 2*(t+1)-1), + tspr_cspr_dbcr3_dac3us => tspr_cspr_dbcr3_dac3us(2*t to 2*(t+1)-1), + tspr_cspr_dbcr3_dac3er => tspr_cspr_dbcr3_dac3er(2*t to 2*(t+1)-1), + tspr_cspr_dbcr3_dac4us => tspr_cspr_dbcr3_dac4us(2*t to 2*(t+1)-1), + tspr_cspr_dbcr3_dac4er => tspr_cspr_dbcr3_dac4er(2*t to 2*(t+1)-1), + tspr_cspr_dbcr2_dac12m => tspr_cspr_dbcr2_dac12m(t), + tspr_cspr_dbcr3_dac34m => tspr_cspr_dbcr3_dac34m(t), + tspr_cspr_dbcr2_dvc1m => tspr_cspr_dbcr2_dvc1m(2*t to 2*(t+1)-1), + tspr_cspr_dbcr2_dvc2m => tspr_cspr_dbcr2_dvc2m(2*t to 2*(t+1)-1), + tspr_cspr_dbcr2_dvc1be => tspr_cspr_dbcr2_dvc1be(8*t to 8*(t+1)-1), + tspr_cspr_dbcr2_dvc2be => tspr_cspr_dbcr2_dvc2be(8*t to 8*(t+1)-1), + spr_dbcr3_ivc => spr_dbcr3_ivc(t), + vdd => vdd, + gnd => gnd +); +end generate; + +siv(0 to threads) <= sov(1 to threads) & scan_in; +scan_out <= sov(0); + +end architecture xuq_fxu_spr; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_fxu_spr_cspr.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_fxu_spr_cspr.vhdl new file mode 100644 index 0000000..fe242ca --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_fxu_spr_cspr.vhdl @@ -0,0 +1,1237 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee,ibm,support,work,tri; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use support.power_logic_pkg.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use tri.tri_latches_pkg.all; +use work.xuq_pkg.all; + +entity xuq_fxu_spr_cspr is +generic( + hvmode : integer := 1; + a2mode : integer := 1; + expand_type : integer := 2; + threads : integer := 4; + regsize : integer := 64; + eff_ifar : integer := 62); +port( + nclk : in clk_logic; + + d_mode_dc : in std_ulogic; + delay_lclkr_dc : in std_ulogic; + mpw1_dc_b : in std_ulogic; + mpw2_dc_b : in std_ulogic; + + func_sl_force : in std_ulogic; + func_sl_thold_0_b : in std_ulogic; + func_nsl_force : in std_ulogic; + func_nsl_thold_0_b : in std_ulogic; + sg_0 : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + ex1_instr : in std_ulogic_vector(11 to 20); + ex1_tid : in std_ulogic_vector(0 to threads-1); + dec_spr_ex1_is_mfspr : in std_ulogic; + dec_spr_ex1_is_mtspr : in std_ulogic; + + ex6_valid : in std_ulogic_vector(0 to threads-1); + ex6_spr_wd : in std_ulogic_vector(64-regsize to 63); + + cspr_tspr_ex6_is_mtspr : out std_ulogic; + cspr_tspr_ex6_instr : out std_ulogic_vector(11 to 20); + cspr_tspr_ex2_is_mfspr : out std_ulogic; + cspr_tspr_ex2_instr : out std_ulogic_vector(11 to 20); + + tspr_cspr_ex2_tspr_rt : in std_ulogic_vector(0 to regsize*threads-1); + fspr_byp_ex3_spr_rt : out std_ulogic_vector(64-regsize to 63); + mux_spr_ex2_rt : in std_ulogic_vector(64-regsize to 63); + + ex2_is_any_load_dac : in std_ulogic; + ex2_is_any_store_dac : in std_ulogic; + + xu_lsu_ex4_dvc1_en : out std_ulogic; + xu_lsu_ex4_dvc2_en : out std_ulogic; + lsu_xu_ex2_dvc1_st_cmp : in std_ulogic_vector(8-regsize/8 to 7); + lsu_xu_ex2_dvc2_st_cmp : in std_ulogic_vector(8-regsize/8 to 7); + lsu_xu_ex8_dvc1_ld_cmp : in std_ulogic_vector(8-regsize/8 to 7); + lsu_xu_ex8_dvc2_ld_cmp : in std_ulogic_vector(8-regsize/8 to 7); + lsu_xu_rel_dvc1_en : in std_ulogic; + lsu_xu_rel_dvc2_en : in std_ulogic; + lsu_xu_rel_dvc_thrd_id : in std_ulogic_vector(0 to 3); + lsu_xu_rel_dvc1_cmp : in std_ulogic_vector(8-regsize/8 to 7); + lsu_xu_rel_dvc2_cmp : in std_ulogic_vector(8-regsize/8 to 7); + + fxu_cpl_ex3_dac1r_cmpr_async : out std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac2r_cmpr_async : out std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac1r_cmpr : out std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac2r_cmpr : out std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac3r_cmpr : out std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac4r_cmpr : out std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac1w_cmpr : out std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac2w_cmpr : out std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac3w_cmpr : out std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac4w_cmpr : out std_ulogic_vector(0 to threads-1); + + spr_bit_act : in std_ulogic; + spr_msr_pr : in std_ulogic_vector(0 to threads-1); + spr_msr_ds : in std_ulogic_vector(0 to threads-1); + + spr_dbcr0_dac1 : in std_ulogic_vector(0 to 2*threads-1); + spr_dbcr0_dac2 : in std_ulogic_vector(0 to 2*threads-1); + spr_dbcr0_dac3 : in std_ulogic_vector(0 to 2*threads-1); + spr_dbcr0_dac4 : in std_ulogic_vector(0 to 2*threads-1); + + tspr_cspr_dbcr2_dac1us : in std_ulogic_vector(0 to 2*threads-1); + tspr_cspr_dbcr2_dac1er : in std_ulogic_vector(0 to 2*threads-1); + tspr_cspr_dbcr2_dac2us : in std_ulogic_vector(0 to 2*threads-1); + tspr_cspr_dbcr2_dac2er : in std_ulogic_vector(0 to 2*threads-1); + tspr_cspr_dbcr3_dac3us : in std_ulogic_vector(0 to 2*threads-1); + tspr_cspr_dbcr3_dac3er : in std_ulogic_vector(0 to 2*threads-1); + tspr_cspr_dbcr3_dac4us : in std_ulogic_vector(0 to 2*threads-1); + tspr_cspr_dbcr3_dac4er : in std_ulogic_vector(0 to 2*threads-1); + + tspr_cspr_dbcr2_dac12m : in std_ulogic_vector(0 to threads-1); + tspr_cspr_dbcr3_dac34m : in std_ulogic_vector(0 to threads-1); + tspr_cspr_dbcr2_dvc1m : in std_ulogic_vector(0 to 2*threads-1); + tspr_cspr_dbcr2_dvc2m : in std_ulogic_vector(0 to 2*threads-1); + tspr_cspr_dbcr2_dvc1be : in std_ulogic_vector(0 to 8*threads-1); + tspr_cspr_dbcr2_dvc2be : in std_ulogic_vector(0 to 8*threads-1); + + + vdd : inout power_logic; + gnd : inout power_logic +); + +-- synopsys translate_off + +-- synopsys translate_on +end xuq_fxu_spr_cspr; +architecture xuq_fxu_spr_cspr of xuq_fxu_spr_cspr is + +subtype DO is std_ulogic_vector(65-regsize to 64); +signal dac1_d , dac1_q : std_ulogic_vector(64-(regsize) to 63); +signal dac2_d , dac2_q : std_ulogic_vector(64-(regsize) to 63); +signal dac3_d , dac3_q : std_ulogic_vector(64-(regsize) to 63); +signal dac4_d , dac4_q : std_ulogic_vector(64-(regsize) to 63); +constant dac1_offset : natural := 0; +constant dac2_offset : natural := dac1_offset + dac1_q'length*a2mode; +constant dac3_offset : natural := dac2_offset + dac2_q'length*a2mode; +constant dac4_offset : natural := dac3_offset + dac3_q'length; +constant last_reg_offset : natural := dac4_offset + dac4_q'length; +signal exx_act_q, exx_act_d : std_ulogic_vector(2 to 5); +signal ex2_dac12m_q, ex2_dac12m_d : std_ulogic_vector(0 to 7); +signal ex2_dac34m_q, ex2_dac34m_d : std_ulogic_vector(0 to 7); +signal ex2_instr_q : std_ulogic_vector(11 to 20); +signal ex2_is_mfspr_q : std_ulogic; +signal ex2_is_mtspr_q : std_ulogic; +signal ex2_tid_q : std_ulogic_vector(0 to threads-1); +signal ex3_dac1r_cmpr_q, ex2_dac1r_cmpr : std_ulogic_vector(0 to threads-1); +signal ex3_dac1w_cmpr_q, ex2_dac1w_cmpr : std_ulogic_vector(0 to threads-1); +signal ex3_dac2r_cmpr_q, ex2_dac2r_cmpr : std_ulogic_vector(0 to threads-1); +signal ex3_dac2w_cmpr_q, ex2_dac2w_cmpr : std_ulogic_vector(0 to threads-1); +signal ex3_dac3r_cmpr_q, ex2_dac3r_cmpr : std_ulogic_vector(0 to threads-1); +signal ex3_dac3w_cmpr_q, ex2_dac3w_cmpr : std_ulogic_vector(0 to threads-1); +signal ex3_dac4r_cmpr_q, ex2_dac4r_cmpr : std_ulogic_vector(0 to threads-1); +signal ex3_dac4w_cmpr_q, ex2_dac4w_cmpr : std_ulogic_vector(0 to threads-1); +signal ex3_dvc1w_cmpr_q, ex2_dvc1w_cmpr : std_ulogic_vector(0 to threads-1); +signal ex3_dvc2w_cmpr_q, ex2_dvc2w_cmpr : std_ulogic_vector(0 to threads-1); +signal ex3_instr_q : std_ulogic_vector(11 to 20); +signal ex3_is_mtspr_q : std_ulogic; +signal ex3_spr_rt_q, ex3_spr_rt_d : std_ulogic_vector(64-regsize to 63); +signal ex4_dvc1_en_q, ex3_dvc1_en : std_ulogic; +signal ex4_dvc2_en_q, ex3_dvc2_en : std_ulogic; +signal ex4_instr_q : std_ulogic_vector(11 to 20); +signal ex4_is_mtspr_q : std_ulogic; +signal ex5_dvc1_en_q : std_ulogic; +signal ex5_dvc2_en_q : std_ulogic; +signal ex5_instr_q : std_ulogic_vector(11 to 20); +signal ex5_is_mtspr_q : std_ulogic; +signal ex6_dvc1_en_q : std_ulogic; +signal ex6_dvc2_en_q : std_ulogic; +signal ex6_instr_q : std_ulogic_vector(11 to 20); +signal ex6_is_mtspr_q : std_ulogic; +signal ex7_dvc1_en_q : std_ulogic; +signal ex7_dvc2_en_q : std_ulogic; +signal ex7_val_q : std_ulogic_vector(0 to threads-1); +signal ex8_dvc1_en_q : std_ulogic; +signal ex8_dvc2_en_q : std_ulogic; +signal ex8_val_q : std_ulogic_vector(0 to threads-1); +signal dbcr0_dac1_q : std_ulogic_vector(0 to 2*threads-1); +signal dbcr0_dac2_q : std_ulogic_vector(0 to 2*threads-1); +signal dbcr0_dac3_q : std_ulogic_vector(0 to 2*threads-1); +signal dbcr0_dac4_q : std_ulogic_vector(0 to 2*threads-1); +signal dbcr2_dvc1m_on_q, dbcr2_dvc1m_on_d : std_ulogic_vector(0 to threads-1); +signal dbcr2_dvc2m_on_q, dbcr2_dvc2m_on_d : std_ulogic_vector(0 to threads-1); +signal dvc1r_cmpr_q, dvc1r_cmpr_d : std_ulogic_vector(0 to threads-1); +signal dvc2r_cmpr_q, dvc2r_cmpr_d : std_ulogic_vector(0 to threads-1); +signal msr_ds_q : std_ulogic_vector(0 to threads-1); +signal msr_pr_q : std_ulogic_vector(0 to threads-1); +signal spr_bit_act_q : std_ulogic; +constant exx_act_offset : integer := last_reg_offset; +constant ex3_dac1r_cmpr_offset : integer := exx_act_offset + exx_act_q'length; +constant ex3_dac1w_cmpr_offset : integer := ex3_dac1r_cmpr_offset + ex3_dac1r_cmpr_q'length; +constant ex3_dac2r_cmpr_offset : integer := ex3_dac1w_cmpr_offset + ex3_dac1w_cmpr_q'length; +constant ex3_dac2w_cmpr_offset : integer := ex3_dac2r_cmpr_offset + ex3_dac2r_cmpr_q'length; +constant ex3_dac3r_cmpr_offset : integer := ex3_dac2w_cmpr_offset + ex3_dac2w_cmpr_q'length; +constant ex3_dac3w_cmpr_offset : integer := ex3_dac3r_cmpr_offset + ex3_dac3r_cmpr_q'length; +constant ex3_dac4r_cmpr_offset : integer := ex3_dac3w_cmpr_offset + ex3_dac3w_cmpr_q'length; +constant ex3_dac4w_cmpr_offset : integer := ex3_dac4r_cmpr_offset + ex3_dac4r_cmpr_q'length; +constant ex3_dvc1w_cmpr_offset : integer := ex3_dac4w_cmpr_offset + ex3_dac4w_cmpr_q'length; +constant ex3_dvc2w_cmpr_offset : integer := ex3_dvc1w_cmpr_offset + ex3_dvc1w_cmpr_q'length; +constant ex3_instr_offset : integer := ex3_dvc2w_cmpr_offset + ex3_dvc2w_cmpr_q'length; +constant ex3_is_mtspr_offset : integer := ex3_instr_offset + ex3_instr_q'length; +constant ex3_spr_rt_offset : integer := ex3_is_mtspr_offset + 1; +constant ex5_dvc1_en_offset : integer := ex3_spr_rt_offset + ex3_spr_rt_q'length; +constant ex5_dvc2_en_offset : integer := ex5_dvc1_en_offset + 1; +constant ex5_instr_offset : integer := ex5_dvc2_en_offset + 1; +constant ex5_is_mtspr_offset : integer := ex5_instr_offset + ex5_instr_q'length; +constant ex7_dvc1_en_offset : integer := ex5_is_mtspr_offset + 1; +constant ex7_dvc2_en_offset : integer := ex7_dvc1_en_offset + 1; +constant ex7_val_offset : integer := ex7_dvc2_en_offset + 1; +constant ex8_val_offset : integer := ex7_val_offset + ex7_val_q'length; +constant dbcr0_dac1_offset : integer := ex8_val_offset + ex8_val_q'length; +constant dbcr0_dac2_offset : integer := dbcr0_dac1_offset + dbcr0_dac1_q'length; +constant dbcr0_dac3_offset : integer := dbcr0_dac2_offset + dbcr0_dac2_q'length; +constant dbcr0_dac4_offset : integer := dbcr0_dac3_offset + dbcr0_dac3_q'length; +constant dbcr2_dvc1m_on_offset : integer := dbcr0_dac4_offset + dbcr0_dac4_q'length; +constant dbcr2_dvc2m_on_offset : integer := dbcr2_dvc1m_on_offset + dbcr2_dvc1m_on_q'length; +constant dvc1r_cmpr_offset : integer := dbcr2_dvc2m_on_offset + dbcr2_dvc2m_on_q'length; +constant dvc2r_cmpr_offset : integer := dvc1r_cmpr_offset + dvc1r_cmpr_q'length; +constant msr_ds_offset : integer := dvc2r_cmpr_offset + dvc2r_cmpr_q'length; +constant msr_pr_offset : integer := msr_ds_offset + msr_ds_q'length; +constant spr_bit_act_offset : integer := msr_pr_offset + msr_pr_q'length; +constant scan_right : integer := spr_bit_act_offset + 1; +signal siv : std_ulogic_vector(0 to scan_right-1); +signal sov : std_ulogic_vector(0 to scan_right-1); +signal tiup : std_ulogic; +signal tidn : std_ulogic_vector(00 to 63); +signal ex2_instr : std_ulogic_vector(11 to 20); +signal ex6_is_mtspr : std_ulogic; +signal ex6_instr : std_ulogic_vector(11 to 20); +signal ex6_val : std_ulogic; +signal ex2_cspr_rt,ex2_tspr_rt : std_ulogic_vector(64-regsize to 63); +signal ex2_dac2_mask : std_ulogic_vector(64-regsize to 63); +signal ex2_dac4_mask : std_ulogic_vector(64-regsize to 63); +signal ex2_dac1_cmpr, ex2_dac1_cmpr_sel : std_ulogic; +signal ex2_dac2_cmpr, ex2_dac2_cmpr_sel : std_ulogic; +signal ex2_dac3_cmpr, ex2_dac3_cmpr_sel : std_ulogic; +signal ex2_dac4_cmpr, ex2_dac4_cmpr_sel : std_ulogic; +signal ex2_dac1r_en, ex2_dac1w_en : std_ulogic_vector(0 to threads-1); +signal ex2_dac2r_en, ex2_dac2w_en : std_ulogic_vector(0 to threads-1); +signal ex2_dac3r_en, ex2_dac3w_en : std_ulogic_vector(0 to threads-1); +signal ex2_dac4r_en, ex2_dac4w_en : std_ulogic_vector(0 to threads-1); +signal ex8_dvc1r_cmpr,rel_dvc1r_cmpr : std_ulogic_vector(0 to threads-1); +signal ex8_dvc2r_cmpr,rel_dvc2r_cmpr : std_ulogic_vector(0 to threads-1); +signal ex8_dvc1_en, ex8_dvc2_en : std_ulogic_vector(0 to threads-1); +signal rel_dvc1_en, rel_dvc2_en : std_ulogic_vector(0 to threads-1); +signal exx_act : std_ulogic_vector(1 to 5); + + +signal ex6_dac1_di : std_ulogic_vector(dac1_q'range); +signal ex6_dac2_di : std_ulogic_vector(dac2_q'range); +signal ex6_dac3_di : std_ulogic_vector(dac3_q'range); +signal ex6_dac4_di : std_ulogic_vector(dac4_q'range); +signal + ex2_dac1_rdec , ex2_dac2_rdec , ex2_dac3_rdec , ex2_dac4_rdec + : std_ulogic; +signal + ex2_dac1_re , ex2_dac2_re , ex2_dac3_re , ex2_dac4_re + : std_ulogic; +signal + ex6_dac1_wdec , ex6_dac2_wdec , ex6_dac3_wdec , ex6_dac4_wdec + : std_ulogic; +signal + ex6_dac1_we , ex6_dac2_we , ex6_dac3_we , ex6_dac4_we + : std_ulogic; +signal + dac1_act , dac2_act , dac3_act , dac4_act + : std_ulogic; +signal + dac1_do , dac2_do , dac3_do , dac4_do + : std_ulogic_vector(0 to 64); + +begin + + +tiup <= '1'; +tidn <= (others=>'0'); + + +exx_act_d <= exx_act(1 to 4); + +exx_act(1) <= or_reduce(ex1_tid); +exx_act(2) <= exx_act_q(2); +exx_act(3) <= exx_act_q(3); +exx_act(4) <= exx_act_q(4); +exx_act(5) <= exx_act_q(5); + +ex2_instr <= ex2_instr_q; +ex6_is_mtspr <= ex6_is_mtspr_q; +ex6_instr <= ex6_instr_q; +ex6_val <= or_reduce(ex6_valid); + +cspr_tspr_ex6_is_mtspr <= ex6_is_mtspr_q; +cspr_tspr_ex6_instr <= ex6_instr_q; +cspr_tspr_ex2_is_mfspr <= ex2_is_mfspr_q; +cspr_tspr_ex2_instr <= ex2_instr_q; + +dac1_act <= ex6_dac1_we; +dac1_d <= ex6_dac1_di; + +dac2_act <= ex6_dac2_we; +dac2_d <= ex6_dac2_di; + +dac3_act <= ex6_dac3_we; +dac3_d <= ex6_dac3_di; + +dac4_act <= ex6_dac4_we; +dac4_d <= ex6_dac4_di; + + +ex2_dac12m_d <= fanout(or_reduce(tspr_cspr_dbcr2_dac12m and ex1_tid),ex2_dac12m_d'length); +ex2_dac34m_d <= fanout(or_reduce(tspr_cspr_dbcr3_dac34m and ex1_tid),ex2_dac34m_d'length); + +ex2_dac2_mask <= dac2_q or not fanout(ex2_dac12m_q,regsize); +ex2_dac4_mask <= dac4_q or not fanout(ex2_dac34m_q,regsize); + +ex2_dac1_cmpr <= and_reduce((mux_spr_ex2_rt xnor dac1_q) or not ex2_dac2_mask); +ex2_dac2_cmpr <= and_reduce((mux_spr_ex2_rt xnor dac2_q) ); +ex2_dac3_cmpr <= and_reduce((mux_spr_ex2_rt xnor dac3_q) or not ex2_dac4_mask); +ex2_dac4_cmpr <= and_reduce((mux_spr_ex2_rt xnor dac4_q) ); + +ex2_dac1_cmpr_sel <= ex2_dac1_cmpr; +ex2_dac2_cmpr_sel <= ex2_dac2_cmpr when ex2_dac12m_q(0)='0' else ex2_dac1_cmpr; +ex2_dac3_cmpr_sel <= ex2_dac3_cmpr; +ex2_dac4_cmpr_sel <= ex2_dac4_cmpr when ex2_dac34m_q(0)='0' else ex2_dac3_cmpr; + +xuq_fxu_spr_dac1en : entity work.xuq_spr_dacen(xuq_spr_dacen) +generic map( + threads => threads) +port map( + spr_msr_pr => msr_pr_q, + spr_msr_ds => msr_ds_q, + spr_dbcr0_dac => dbcr0_dac1_q, + spr_dbcr_dac_us => tspr_cspr_dbcr2_dac1us, + spr_dbcr_dac_er => tspr_cspr_dbcr2_dac1er, + val => ex2_tid_q, + load => ex2_is_any_load_dac, + store => ex2_is_any_store_dac, + dacr_en => ex2_dac1r_en, + dacw_en => ex2_dac1w_en); + +xuq_fxu_spr_dac2en : entity work.xuq_spr_dacen(xuq_spr_dacen) +generic map( + threads => threads) +port map( + spr_msr_pr => msr_pr_q, + spr_msr_ds => msr_ds_q, + spr_dbcr0_dac => dbcr0_dac2_q, + spr_dbcr_dac_us => tspr_cspr_dbcr2_dac2us, + spr_dbcr_dac_er => tspr_cspr_dbcr2_dac2er, + val => ex2_tid_q, + load => ex2_is_any_load_dac, + store => ex2_is_any_store_dac, + dacr_en => ex2_dac2r_en, + dacw_en => ex2_dac2w_en); + + +xuq_fxu_spr_dac3en : entity work.xuq_spr_dacen(xuq_spr_dacen) +generic map( + threads => threads) +port map( + spr_msr_pr => msr_pr_q, + spr_msr_ds => msr_ds_q, + spr_dbcr0_dac => dbcr0_dac3_q, + spr_dbcr_dac_us => tspr_cspr_dbcr3_dac3us, + spr_dbcr_dac_er => tspr_cspr_dbcr3_dac3er, + val => ex2_tid_q, + load => ex2_is_any_load_dac, + store => ex2_is_any_store_dac, + dacr_en => ex2_dac3r_en, + dacw_en => ex2_dac3w_en); + + +xuq_fxu_spr_dac4en : entity work.xuq_spr_dacen(xuq_spr_dacen) +generic map( + threads => threads) +port map( + spr_msr_pr => msr_pr_q, + spr_msr_ds => msr_ds_q, + spr_dbcr0_dac => dbcr0_dac4_q, + spr_dbcr_dac_us => tspr_cspr_dbcr3_dac4us, + spr_dbcr_dac_er => tspr_cspr_dbcr3_dac4er, + val => ex2_tid_q, + load => ex2_is_any_load_dac, + store => ex2_is_any_store_dac, + dacr_en => ex2_dac4r_en, + dacw_en => ex2_dac4w_en); + + +ex8_dvc1_en <= gate(ex8_val_q,ex8_dvc1_en_q); +ex8_dvc2_en <= gate(ex8_val_q,ex8_dvc2_en_q); + +rel_dvc1_en <= gate(lsu_xu_rel_dvc_thrd_id,lsu_xu_rel_dvc1_en); +rel_dvc2_en <= gate(lsu_xu_rel_dvc_thrd_id,lsu_xu_rel_dvc2_en); + +xuq_fxu_spr_dvc_cmp : for t in 0 to threads-1 generate +begin + + dbcr2_dvc1m_on_d(t) <= or_reduce(tspr_cspr_dbcr2_dvc1m(2*t to 2*t+1)) and or_reduce(tspr_cspr_dbcr2_dvc1be(t*8+8-lsu_xu_ex2_dvc1_st_cmp'length to t*8+7)); + dbcr2_dvc2m_on_d(t) <= or_reduce(tspr_cspr_dbcr2_dvc2m(2*t to 2*t+1)) and or_reduce(tspr_cspr_dbcr2_dvc2be(t*8+8-lsu_xu_ex2_dvc2_st_cmp'length to t*8+7)); + + dvc1_st : entity work.xuq_spr_dvccmp(xuq_spr_dvccmp) + generic map(regsize => regsize) + port map( + en => '1', + cmp => lsu_xu_ex2_dvc1_st_cmp, + dvcm => tspr_cspr_dbcr2_dvc1m(2*t to 2*t+1), + dvcbe => tspr_cspr_dbcr2_dvc1be(t*8+8-lsu_xu_ex2_dvc1_st_cmp'length to t*8+7), + dvc_cmpr => ex2_dvc1w_cmpr(t) + ); + + dvc2_st : entity work.xuq_spr_dvccmp(xuq_spr_dvccmp) + generic map(regsize => regsize) + port map( + en => '1', + cmp => lsu_xu_ex2_dvc2_st_cmp, + dvcm => tspr_cspr_dbcr2_dvc2m(2*t to 2*t+1), + dvcbe => tspr_cspr_dbcr2_dvc2be(t*8+8-lsu_xu_ex2_dvc2_st_cmp'length to t*8+7), + dvc_cmpr => ex2_dvc2w_cmpr(t) + ); + + dvc1_ld : entity work.xuq_spr_dvccmp(xuq_spr_dvccmp) + generic map(regsize => regsize) + port map( + en => ex8_dvc1_en(t), + en00 => '0', + cmp => lsu_xu_ex8_dvc1_ld_cmp, + dvcm => tspr_cspr_dbcr2_dvc1m(2*t to 2*t+1), + dvcbe => tspr_cspr_dbcr2_dvc1be(t*8+8-lsu_xu_ex8_dvc1_ld_cmp'length to t*8+7), + dvc_cmpr => ex8_dvc1r_cmpr(t) + ); + + dvc2_ld : entity work.xuq_spr_dvccmp(xuq_spr_dvccmp) + generic map(regsize => regsize) + port map( + en => ex8_dvc2_en(t), + en00 => '0', + cmp => lsu_xu_ex8_dvc2_ld_cmp, + dvcm => tspr_cspr_dbcr2_dvc2m(2*t to 2*t+1), + dvcbe => tspr_cspr_dbcr2_dvc2be(t*8+8-lsu_xu_ex8_dvc2_ld_cmp'length to t*8+7), + dvc_cmpr => ex8_dvc2r_cmpr(t) + ); + + dvc1_rel : entity work.xuq_spr_dvccmp(xuq_spr_dvccmp) + generic map(regsize => regsize) + port map( + en => rel_dvc1_en(t), + en00 => '0', + cmp => lsu_xu_rel_dvc1_cmp, + dvcm => tspr_cspr_dbcr2_dvc1m(2*t to 2*t+1), + dvcbe => tspr_cspr_dbcr2_dvc1be(t*8+8-lsu_xu_rel_dvc1_cmp'length to t*8+7), + dvc_cmpr => rel_dvc1r_cmpr(t) + ); + + dvc2_rel : entity work.xuq_spr_dvccmp(xuq_spr_dvccmp) + generic map(regsize => regsize) + port map( + en => rel_dvc2_en(t), + en00 => '0', + cmp => lsu_xu_rel_dvc2_cmp, + dvcm => tspr_cspr_dbcr2_dvc2m(2*t to 2*t+1), + dvcbe => tspr_cspr_dbcr2_dvc2be(t*8+8-lsu_xu_rel_dvc2_cmp'length to t*8+7), + dvc_cmpr => rel_dvc2r_cmpr(t) + ); + +end generate; + +ex2_dac1r_cmpr <= gate(ex2_dac1r_en,ex2_dac1_cmpr_sel); +ex2_dac2r_cmpr <= gate(ex2_dac2r_en,ex2_dac2_cmpr_sel); +ex2_dac3r_cmpr <= gate(ex2_dac3r_en,ex2_dac3_cmpr_sel); +ex2_dac4r_cmpr <= gate(ex2_dac4r_en,ex2_dac4_cmpr_sel); + +ex2_dac1w_cmpr <= gate(ex2_dac1w_en,ex2_dac1_cmpr_sel); +ex2_dac2w_cmpr <= gate(ex2_dac2w_en,ex2_dac2_cmpr_sel); +ex2_dac3w_cmpr <= gate(ex2_dac3w_en,ex2_dac3_cmpr_sel); +ex2_dac4w_cmpr <= gate(ex2_dac4w_en,ex2_dac4_cmpr_sel); + +dvc1r_cmpr_d <= ex8_dvc1r_cmpr or rel_dvc1r_cmpr; +dvc2r_cmpr_d <= ex8_dvc2r_cmpr or rel_dvc2r_cmpr; + +ex3_dvc1_en <= or_reduce(ex3_dac1r_cmpr_q and dbcr2_dvc1m_on_q); +ex3_dvc2_en <= or_reduce(ex3_dac2r_cmpr_q and dbcr2_dvc2m_on_q); + +fxu_cpl_ex3_dac1r_cmpr_async <= dvc1r_cmpr_q; +fxu_cpl_ex3_dac2r_cmpr_async <= dvc2r_cmpr_q; +fxu_cpl_ex3_dac1r_cmpr <=(ex3_dac1r_cmpr_q and not dbcr2_dvc1m_on_q); +fxu_cpl_ex3_dac2r_cmpr <=(ex3_dac2r_cmpr_q and not dbcr2_dvc2m_on_q); +fxu_cpl_ex3_dac3r_cmpr <= ex3_dac3r_cmpr_q; +fxu_cpl_ex3_dac4r_cmpr <= ex3_dac4r_cmpr_q; + +fxu_cpl_ex3_dac1w_cmpr <= ex3_dac1w_cmpr_q and (ex3_dvc1w_cmpr_q or not dbcr2_dvc1m_on_q); +fxu_cpl_ex3_dac2w_cmpr <= ex3_dac2w_cmpr_q and (ex3_dvc2w_cmpr_q or not dbcr2_dvc2m_on_q); +fxu_cpl_ex3_dac3w_cmpr <= ex3_dac3w_cmpr_q; +fxu_cpl_ex3_dac4w_cmpr <= ex3_dac4w_cmpr_q; + +xu_lsu_ex4_dvc1_en <= ex4_dvc1_en_q; +xu_lsu_ex4_dvc2_en <= ex4_dvc2_en_q; + + +readmux_00 : if a2mode = 0 and hvmode = 0 generate +ex2_cspr_rt <= + (dac3_do(DO'range) and (DO'range => ex2_dac3_re )) or + (dac4_do(DO'range) and (DO'range => ex2_dac4_re )); +end generate; +readmux_01 : if a2mode = 0 and hvmode = 1 generate +ex2_cspr_rt <= + (dac3_do(DO'range) and (DO'range => ex2_dac3_re )) or + (dac4_do(DO'range) and (DO'range => ex2_dac4_re )); +end generate; +readmux_10 : if a2mode = 1 and hvmode = 0 generate +ex2_cspr_rt <= + (dac1_do(DO'range) and (DO'range => ex2_dac1_re )) or + (dac2_do(DO'range) and (DO'range => ex2_dac2_re )) or + (dac3_do(DO'range) and (DO'range => ex2_dac3_re )) or + (dac4_do(DO'range) and (DO'range => ex2_dac4_re )); +end generate; +readmux_11 : if a2mode = 1 and hvmode = 1 generate +ex2_cspr_rt <= + (dac1_do(DO'range) and (DO'range => ex2_dac1_re )) or + (dac2_do(DO'range) and (DO'range => ex2_dac2_re )) or + (dac3_do(DO'range) and (DO'range => ex2_dac3_re )) or + (dac4_do(DO'range) and (DO'range => ex2_dac4_re )); +end generate; + +ex2_tspr_rt <= mux_t(tspr_cspr_ex2_tspr_rt,ex2_tid_q); +ex3_spr_rt_d <= gate((ex2_tspr_rt or ex2_cspr_rt),ex2_is_mfspr_q); +fspr_byp_ex3_spr_rt <= ex3_spr_rt_q; + +mark_unused(tidn); + + +ex2_dac1_rdec <= (ex2_instr(11 to 20) = "1110001001"); +ex2_dac2_rdec <= (ex2_instr(11 to 20) = "1110101001"); +ex2_dac3_rdec <= (ex2_instr(11 to 20) = "1000111010"); +ex2_dac4_rdec <= (ex2_instr(11 to 20) = "1001011010"); +ex2_dac1_re <= ex2_dac1_rdec; +ex2_dac2_re <= ex2_dac2_rdec; +ex2_dac3_re <= ex2_dac3_rdec; +ex2_dac4_re <= ex2_dac4_rdec; + +ex6_dac1_wdec <= (ex6_instr(11 to 20) = "1110001001"); +ex6_dac2_wdec <= (ex6_instr(11 to 20) = "1110101001"); +ex6_dac3_wdec <= (ex6_instr(11 to 20) = "1000111010"); +ex6_dac4_wdec <= (ex6_instr(11 to 20) = "1001011010"); +ex6_dac1_we <= ex6_val and ex6_is_mtspr and ex6_dac1_wdec; +ex6_dac2_we <= ex6_val and ex6_is_mtspr and ex6_dac2_wdec; +ex6_dac3_we <= ex6_val and ex6_is_mtspr and ex6_dac3_wdec; +ex6_dac4_we <= ex6_val and ex6_is_mtspr and ex6_dac4_wdec; + + + +ex6_dac1_di <= ex6_spr_wd(64-(regsize) to 63) ; +dac1_do <= tidn(0 to 64-(regsize)) & + dac1_q(64-(regsize) to 63) ; +ex6_dac2_di <= ex6_spr_wd(64-(regsize) to 63) ; +dac2_do <= tidn(0 to 64-(regsize)) & + dac2_q(64-(regsize) to 63) ; +ex6_dac3_di <= ex6_spr_wd(64-(regsize) to 63) ; +dac3_do <= tidn(0 to 64-(regsize)) & + dac3_q(64-(regsize) to 63) ; +ex6_dac4_di <= ex6_spr_wd(64-(regsize) to 63) ; +dac4_do <= tidn(0 to 64-(regsize)) & + dac4_q(64-(regsize) to 63) ; + +mark_unused(dac1_do(0 to 64-regsize)); +mark_unused(dac2_do(0 to 64-regsize)); +mark_unused(dac3_do(0 to 64-regsize)); +mark_unused(dac4_do(0 to 64-regsize)); + +dac1_latch_gen : if a2mode = 1 generate +dac1_latch : tri_ser_rlmreg_p +generic map(width => dac1_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => dac1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dac1_offset to dac1_offset + dac1_q'length-1), + scout => sov(dac1_offset to dac1_offset + dac1_q'length-1), + din => dac1_d, + dout => dac1_q); +end generate; +dac1_latch_tie : if a2mode = 0 generate + dac1_q <= (others=>'0'); +end generate; +dac2_latch_gen : if a2mode = 1 generate +dac2_latch : tri_ser_rlmreg_p +generic map(width => dac2_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => dac2_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dac2_offset to dac2_offset + dac2_q'length-1), + scout => sov(dac2_offset to dac2_offset + dac2_q'length-1), + din => dac2_d, + dout => dac2_q); +end generate; +dac2_latch_tie : if a2mode = 0 generate + dac2_q <= (others=>'0'); +end generate; +dac3_latch : tri_ser_rlmreg_p +generic map(width => dac3_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => dac3_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dac3_offset to dac3_offset + dac3_q'length-1), + scout => sov(dac3_offset to dac3_offset + dac3_q'length-1), + din => dac3_d, + dout => dac3_q); +dac4_latch : tri_ser_rlmreg_p +generic map(width => dac4_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => dac4_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dac4_offset to dac4_offset + dac4_q'length-1), + scout => sov(dac4_offset to dac4_offset + dac4_q'length-1), + din => dac4_d, + dout => dac4_q); + + +exx_act_latch : tri_rlmreg_p + generic map (width => exx_act_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(exx_act_offset to exx_act_offset + exx_act_q'length-1), + scout => sov(exx_act_offset to exx_act_offset + exx_act_q'length-1), + din => exx_act_d, + dout => exx_act_q); +ex2_dac12m_latch : tri_regk + generic map (width => ex2_dac12m_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex2_dac12m_d, + dout => ex2_dac12m_q); +ex2_dac34m_latch : tri_regk + generic map (width => ex2_dac34m_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex2_dac34m_d, + dout => ex2_dac34m_q); +ex2_instr_latch : tri_regk + generic map (width => ex2_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex1_instr , + dout => ex2_instr_q); +ex2_is_mfspr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => dec_spr_ex1_is_mfspr , + dout(0) => ex2_is_mfspr_q); +ex2_is_mtspr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => dec_spr_ex1_is_mtspr , + dout(0) => ex2_is_mtspr_q); +ex2_tid_latch : tri_regk + generic map (width => ex2_tid_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex1_tid , + dout => ex2_tid_q); +ex3_dac1r_cmpr_latch : tri_rlmreg_p + generic map (width => ex3_dac1r_cmpr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_dac1r_cmpr_offset to ex3_dac1r_cmpr_offset + ex3_dac1r_cmpr_q'length-1), + scout => sov(ex3_dac1r_cmpr_offset to ex3_dac1r_cmpr_offset + ex3_dac1r_cmpr_q'length-1), + din => ex2_dac1r_cmpr, + dout => ex3_dac1r_cmpr_q); +ex3_dac1w_cmpr_latch : tri_rlmreg_p + generic map (width => ex3_dac1w_cmpr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_dac1w_cmpr_offset to ex3_dac1w_cmpr_offset + ex3_dac1w_cmpr_q'length-1), + scout => sov(ex3_dac1w_cmpr_offset to ex3_dac1w_cmpr_offset + ex3_dac1w_cmpr_q'length-1), + din => ex2_dac1w_cmpr, + dout => ex3_dac1w_cmpr_q); +ex3_dac2r_cmpr_latch : tri_rlmreg_p + generic map (width => ex3_dac2r_cmpr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_dac2r_cmpr_offset to ex3_dac2r_cmpr_offset + ex3_dac2r_cmpr_q'length-1), + scout => sov(ex3_dac2r_cmpr_offset to ex3_dac2r_cmpr_offset + ex3_dac2r_cmpr_q'length-1), + din => ex2_dac2r_cmpr, + dout => ex3_dac2r_cmpr_q); +ex3_dac2w_cmpr_latch : tri_rlmreg_p + generic map (width => ex3_dac2w_cmpr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_dac2w_cmpr_offset to ex3_dac2w_cmpr_offset + ex3_dac2w_cmpr_q'length-1), + scout => sov(ex3_dac2w_cmpr_offset to ex3_dac2w_cmpr_offset + ex3_dac2w_cmpr_q'length-1), + din => ex2_dac2w_cmpr, + dout => ex3_dac2w_cmpr_q); +ex3_dac3r_cmpr_latch : tri_rlmreg_p + generic map (width => ex3_dac3r_cmpr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_dac3r_cmpr_offset to ex3_dac3r_cmpr_offset + ex3_dac3r_cmpr_q'length-1), + scout => sov(ex3_dac3r_cmpr_offset to ex3_dac3r_cmpr_offset + ex3_dac3r_cmpr_q'length-1), + din => ex2_dac3r_cmpr, + dout => ex3_dac3r_cmpr_q); +ex3_dac3w_cmpr_latch : tri_rlmreg_p + generic map (width => ex3_dac3w_cmpr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_dac3w_cmpr_offset to ex3_dac3w_cmpr_offset + ex3_dac3w_cmpr_q'length-1), + scout => sov(ex3_dac3w_cmpr_offset to ex3_dac3w_cmpr_offset + ex3_dac3w_cmpr_q'length-1), + din => ex2_dac3w_cmpr, + dout => ex3_dac3w_cmpr_q); +ex3_dac4r_cmpr_latch : tri_rlmreg_p + generic map (width => ex3_dac4r_cmpr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_dac4r_cmpr_offset to ex3_dac4r_cmpr_offset + ex3_dac4r_cmpr_q'length-1), + scout => sov(ex3_dac4r_cmpr_offset to ex3_dac4r_cmpr_offset + ex3_dac4r_cmpr_q'length-1), + din => ex2_dac4r_cmpr, + dout => ex3_dac4r_cmpr_q); +ex3_dac4w_cmpr_latch : tri_rlmreg_p + generic map (width => ex3_dac4w_cmpr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_dac4w_cmpr_offset to ex3_dac4w_cmpr_offset + ex3_dac4w_cmpr_q'length-1), + scout => sov(ex3_dac4w_cmpr_offset to ex3_dac4w_cmpr_offset + ex3_dac4w_cmpr_q'length-1), + din => ex2_dac4w_cmpr, + dout => ex3_dac4w_cmpr_q); +ex3_dvc1w_cmpr_latch : tri_rlmreg_p + generic map (width => ex3_dvc1w_cmpr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_dvc1w_cmpr_offset to ex3_dvc1w_cmpr_offset + ex3_dvc1w_cmpr_q'length-1), + scout => sov(ex3_dvc1w_cmpr_offset to ex3_dvc1w_cmpr_offset + ex3_dvc1w_cmpr_q'length-1), + din => ex2_dvc1w_cmpr, + dout => ex3_dvc1w_cmpr_q); +ex3_dvc2w_cmpr_latch : tri_rlmreg_p + generic map (width => ex3_dvc2w_cmpr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_dvc2w_cmpr_offset to ex3_dvc2w_cmpr_offset + ex3_dvc2w_cmpr_q'length-1), + scout => sov(ex3_dvc2w_cmpr_offset to ex3_dvc2w_cmpr_offset + ex3_dvc2w_cmpr_q'length-1), + din => ex2_dvc2w_cmpr, + dout => ex3_dvc2w_cmpr_q); +ex3_instr_latch : tri_rlmreg_p + generic map (width => ex3_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_instr_offset to ex3_instr_offset + ex3_instr_q'length-1), + scout => sov(ex3_instr_offset to ex3_instr_offset + ex3_instr_q'length-1), + din => ex2_instr_q , + dout => ex3_instr_q); +ex3_is_mtspr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_mtspr_offset), + scout => sov(ex3_is_mtspr_offset), + din => ex2_is_mtspr_q , + dout => ex3_is_mtspr_q); +ex3_spr_rt_latch : tri_rlmreg_p + generic map (width => ex3_spr_rt_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_spr_rt_offset to ex3_spr_rt_offset + ex3_spr_rt_q'length-1), + scout => sov(ex3_spr_rt_offset to ex3_spr_rt_offset + ex3_spr_rt_q'length-1), + din => ex3_spr_rt_d, + dout => ex3_spr_rt_q); +ex4_dvc1_en_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_dvc1_en, + dout(0) => ex4_dvc1_en_q); +ex4_dvc2_en_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_dvc2_en, + dout(0) => ex4_dvc2_en_q); +ex4_instr_latch : tri_regk + generic map (width => ex4_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex3_instr_q , + dout => ex4_instr_q); +ex4_is_mtspr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_is_mtspr_q , + dout(0) => ex4_is_mtspr_q); +ex5_dvc1_en_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_dvc1_en_offset), + scout => sov(ex5_dvc1_en_offset), + din => ex4_dvc1_en_q , + dout => ex5_dvc1_en_q); +ex5_dvc2_en_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_dvc2_en_offset), + scout => sov(ex5_dvc2_en_offset), + din => ex4_dvc2_en_q , + dout => ex5_dvc2_en_q); +ex5_instr_latch : tri_rlmreg_p + generic map (width => ex5_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_instr_offset to ex5_instr_offset + ex5_instr_q'length-1), + scout => sov(ex5_instr_offset to ex5_instr_offset + ex5_instr_q'length-1), + din => ex4_instr_q , + dout => ex5_instr_q); +ex5_is_mtspr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_is_mtspr_offset), + scout => sov(ex5_is_mtspr_offset), + din => ex4_is_mtspr_q , + dout => ex5_is_mtspr_q); +ex6_dvc1_en_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(5) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex5_dvc1_en_q , + dout(0) => ex6_dvc1_en_q); +ex6_dvc2_en_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(5) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex5_dvc2_en_q , + dout(0) => ex6_dvc2_en_q); +ex6_instr_latch : tri_regk + generic map (width => ex6_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(5) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex5_instr_q , + dout => ex6_instr_q); +ex6_is_mtspr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(5) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex5_is_mtspr_q , + dout(0) => ex6_is_mtspr_q); +ex7_dvc1_en_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex7_dvc1_en_offset), + scout => sov(ex7_dvc1_en_offset), + din => ex6_dvc1_en_q , + dout => ex7_dvc1_en_q); +ex7_dvc2_en_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex7_dvc2_en_offset), + scout => sov(ex7_dvc2_en_offset), + din => ex6_dvc2_en_q , + dout => ex7_dvc2_en_q); +ex7_val_latch : tri_rlmreg_p + generic map (width => ex7_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex7_val_offset to ex7_val_offset + ex7_val_q'length-1), + scout => sov(ex7_val_offset to ex7_val_offset + ex7_val_q'length-1), + din => ex6_valid , + dout => ex7_val_q); +ex8_dvc1_en_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex7_dvc1_en_q , + dout(0) => ex8_dvc1_en_q); +ex8_dvc2_en_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex7_dvc2_en_q , + dout(0) => ex8_dvc2_en_q); +ex8_val_latch : tri_rlmreg_p + generic map (width => ex8_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex8_val_offset to ex8_val_offset + ex8_val_q'length-1), + scout => sov(ex8_val_offset to ex8_val_offset + ex8_val_q'length-1), + din => ex7_val_q , + dout => ex8_val_q); +dbcr0_dac1_latch : tri_rlmreg_p + generic map (width => dbcr0_dac1_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dbcr0_dac1_offset to dbcr0_dac1_offset + dbcr0_dac1_q'length-1), + scout => sov(dbcr0_dac1_offset to dbcr0_dac1_offset + dbcr0_dac1_q'length-1), + din => spr_dbcr0_dac1 , + dout => dbcr0_dac1_q); +dbcr0_dac2_latch : tri_rlmreg_p + generic map (width => dbcr0_dac2_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dbcr0_dac2_offset to dbcr0_dac2_offset + dbcr0_dac2_q'length-1), + scout => sov(dbcr0_dac2_offset to dbcr0_dac2_offset + dbcr0_dac2_q'length-1), + din => spr_dbcr0_dac2 , + dout => dbcr0_dac2_q); +dbcr0_dac3_latch : tri_rlmreg_p + generic map (width => dbcr0_dac3_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dbcr0_dac3_offset to dbcr0_dac3_offset + dbcr0_dac3_q'length-1), + scout => sov(dbcr0_dac3_offset to dbcr0_dac3_offset + dbcr0_dac3_q'length-1), + din => spr_dbcr0_dac3 , + dout => dbcr0_dac3_q); +dbcr0_dac4_latch : tri_rlmreg_p + generic map (width => dbcr0_dac4_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dbcr0_dac4_offset to dbcr0_dac4_offset + dbcr0_dac4_q'length-1), + scout => sov(dbcr0_dac4_offset to dbcr0_dac4_offset + dbcr0_dac4_q'length-1), + din => spr_dbcr0_dac4 , + dout => dbcr0_dac4_q); +dbcr2_dvc1m_on_latch : tri_rlmreg_p + generic map (width => dbcr2_dvc1m_on_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dbcr2_dvc1m_on_offset to dbcr2_dvc1m_on_offset + dbcr2_dvc1m_on_q'length-1), + scout => sov(dbcr2_dvc1m_on_offset to dbcr2_dvc1m_on_offset + dbcr2_dvc1m_on_q'length-1), + din => dbcr2_dvc1m_on_d, + dout => dbcr2_dvc1m_on_q); +dbcr2_dvc2m_on_latch : tri_rlmreg_p + generic map (width => dbcr2_dvc2m_on_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dbcr2_dvc2m_on_offset to dbcr2_dvc2m_on_offset + dbcr2_dvc2m_on_q'length-1), + scout => sov(dbcr2_dvc2m_on_offset to dbcr2_dvc2m_on_offset + dbcr2_dvc2m_on_q'length-1), + din => dbcr2_dvc2m_on_d, + dout => dbcr2_dvc2m_on_q); +dvc1r_cmpr_latch : tri_rlmreg_p + generic map (width => dvc1r_cmpr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dvc1r_cmpr_offset to dvc1r_cmpr_offset + dvc1r_cmpr_q'length-1), + scout => sov(dvc1r_cmpr_offset to dvc1r_cmpr_offset + dvc1r_cmpr_q'length-1), + din => dvc1r_cmpr_d, + dout => dvc1r_cmpr_q); +dvc2r_cmpr_latch : tri_rlmreg_p + generic map (width => dvc2r_cmpr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dvc2r_cmpr_offset to dvc2r_cmpr_offset + dvc2r_cmpr_q'length-1), + scout => sov(dvc2r_cmpr_offset to dvc2r_cmpr_offset + dvc2r_cmpr_q'length-1), + din => dvc2r_cmpr_d, + dout => dvc2r_cmpr_q); +msr_ds_latch : tri_rlmreg_p + generic map (width => msr_ds_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(msr_ds_offset to msr_ds_offset + msr_ds_q'length-1), + scout => sov(msr_ds_offset to msr_ds_offset + msr_ds_q'length-1), + din => spr_msr_ds , + dout => msr_ds_q); +msr_pr_latch : tri_rlmreg_p + generic map (width => msr_pr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(msr_pr_offset to msr_pr_offset + msr_pr_q'length-1), + scout => sov(msr_pr_offset to msr_pr_offset + msr_pr_q'length-1), + din => spr_msr_pr , + dout => msr_pr_q); +spr_bit_act_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(spr_bit_act_offset), + scout => sov(spr_bit_act_offset), + din => spr_bit_act, + dout => spr_bit_act_q); + +siv(0 to scan_right-1) <= sov(1 to scan_right-1) & scan_in; +scan_out <= sov(0); + +end architecture xuq_fxu_spr_cspr; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_fxu_spr_tspr.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_fxu_spr_tspr.vhdl new file mode 100644 index 0000000..ad3a0c2 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_fxu_spr_tspr.vhdl @@ -0,0 +1,297 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee,ibm,support,work,tri; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use support.power_logic_pkg.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use tri.tri_latches_pkg.all; +use work.xuq_pkg.all; + +entity xuq_fxu_spr_tspr is +generic( + hvmode : integer := 1; + a2mode : integer := 1; + expand_type : integer := 2; + regsize : integer := 64; + eff_ifar : integer := 62); +port( + nclk : in clk_logic; + d_mode_dc : in std_ulogic; + delay_lclkr_dc : in std_ulogic; + mpw1_dc_b : in std_ulogic; + mpw2_dc_b : in std_ulogic; + func_sl_force : in std_ulogic; + func_sl_thold_0_b : in std_ulogic; + sg_0 : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + cspr_tspr_ex2_instr : in std_ulogic_vector(11 to 20); + tspr_cspr_ex2_tspr_rt : out std_ulogic_vector(64-regsize to 63); + + ex6_val : in std_ulogic; + cspr_tspr_ex6_is_mtspr : in std_ulogic; + cspr_tspr_ex6_instr : in std_ulogic_vector(11 to 20); + ex6_spr_wd : in std_ulogic_vector(64-regsize to 63); + + tspr_cspr_dbcr2_dac1us : out std_ulogic_vector(0 to 1); + tspr_cspr_dbcr2_dac1er : out std_ulogic_vector(0 to 1); + tspr_cspr_dbcr2_dac2us : out std_ulogic_vector(0 to 1); + tspr_cspr_dbcr2_dac2er : out std_ulogic_vector(0 to 1); + tspr_cspr_dbcr3_dac3us : out std_ulogic_vector(0 to 1); + tspr_cspr_dbcr3_dac3er : out std_ulogic_vector(0 to 1); + tspr_cspr_dbcr3_dac4us : out std_ulogic_vector(0 to 1); + tspr_cspr_dbcr3_dac4er : out std_ulogic_vector(0 to 1); + tspr_cspr_dbcr2_dac12m : out std_ulogic; + tspr_cspr_dbcr3_dac34m : out std_ulogic; + tspr_cspr_dbcr2_dvc1m : out std_ulogic_vector(0 to 1); + tspr_cspr_dbcr2_dvc2m : out std_ulogic_vector(0 to 1); + tspr_cspr_dbcr2_dvc1be : out std_ulogic_vector(0 to 7); + tspr_cspr_dbcr2_dvc2be : out std_ulogic_vector(0 to 7); + spr_dbcr3_ivc : out std_ulogic; + + vdd : inout power_logic; + gnd : inout power_logic +); + +-- synopsys translate_off + +-- synopsys translate_on +end xuq_fxu_spr_tspr; +architecture xuq_fxu_spr_tspr of xuq_fxu_spr_tspr is + +subtype DO is std_ulogic_vector(65-regsize to 64); +signal dbcr2_d , dbcr2_q : std_ulogic_vector(35 to 63); +signal dbcr3_d , dbcr3_q : std_ulogic_vector(54 to 63); +constant dbcr2_offset : natural := 0; +constant dbcr3_offset : natural := dbcr2_offset + dbcr2_q'length*a2mode; +constant last_reg_offset : natural := dbcr3_offset + dbcr3_q'length; +constant scan_right : integer := last_reg_offset; +signal siv : std_ulogic_vector(0 to scan_right-1); +signal sov : std_ulogic_vector(0 to scan_right-1); +signal tiup : std_ulogic; +signal tidn : std_ulogic_vector(00 to 63); +signal ex2_instr : std_ulogic_vector(11 to 20); +signal ex6_is_mtspr : std_ulogic; +signal ex6_instr : std_ulogic_vector(11 to 20); +signal spr_dbcr2_dac1us : std_ulogic_vector(0 to 1); +signal spr_dbcr2_dac1er : std_ulogic_vector(0 to 1); +signal spr_dbcr2_dac2us : std_ulogic_vector(0 to 1); +signal spr_dbcr2_dac2er : std_ulogic_vector(0 to 1); +signal spr_dbcr2_dac12m : std_ulogic; +signal spr_dbcr2_dvc1m : std_ulogic_vector(0 to 1); +signal spr_dbcr2_dvc2m : std_ulogic_vector(0 to 1); +signal spr_dbcr2_dvc1be : std_ulogic_vector(0 to 7); +signal spr_dbcr2_dvc2be : std_ulogic_vector(0 to 7); +signal spr_dbcr3_dac3us : std_ulogic_vector(0 to 1); +signal spr_dbcr3_dac3er : std_ulogic_vector(0 to 1); +signal spr_dbcr3_dac4us : std_ulogic_vector(0 to 1); +signal spr_dbcr3_dac4er : std_ulogic_vector(0 to 1); +signal spr_dbcr3_dac34m : std_ulogic; +signal ex6_dbcr2_di : std_ulogic_vector(dbcr2_q'range); +signal ex6_dbcr3_di : std_ulogic_vector(dbcr3_q'range); +signal + ex2_dbcr2_rdec , ex2_dbcr3_rdec + : std_ulogic; +signal + ex2_dbcr2_re , ex2_dbcr3_re + : std_ulogic; +signal + ex6_dbcr2_wdec , ex6_dbcr3_wdec + : std_ulogic; +signal + ex6_dbcr2_we , ex6_dbcr3_we + : std_ulogic; +signal + dbcr2_act , dbcr3_act + : std_ulogic; +signal + dbcr2_do , dbcr3_do + : std_ulogic_vector(0 to 64); + +begin + + +tiup <= '1'; +tidn <= (others=>'0'); +ex2_instr <= cspr_tspr_ex2_instr; +ex6_is_mtspr <= cspr_tspr_ex6_is_mtspr; +ex6_instr <= cspr_tspr_ex6_instr; + +dbcr2_act <= ex6_dbcr2_we; +dbcr2_d <= ex6_dbcr2_di; + +dbcr3_act <= ex6_dbcr3_we; +dbcr3_d <= ex6_dbcr3_di; + +readmux_00 : if a2mode = 0 and hvmode = 0 generate +tspr_cspr_ex2_tspr_rt <= + (dbcr3_do(DO'range) and (DO'range => ex2_dbcr3_re )); +end generate; +readmux_01 : if a2mode = 0 and hvmode = 1 generate +tspr_cspr_ex2_tspr_rt <= + (dbcr3_do(DO'range) and (DO'range => ex2_dbcr3_re )); +end generate; +readmux_10 : if a2mode = 1 and hvmode = 0 generate +tspr_cspr_ex2_tspr_rt <= + (dbcr2_do(DO'range) and (DO'range => ex2_dbcr2_re )) or + (dbcr3_do(DO'range) and (DO'range => ex2_dbcr3_re )); +end generate; +readmux_11 : if a2mode = 1 and hvmode = 1 generate +tspr_cspr_ex2_tspr_rt <= + (dbcr2_do(DO'range) and (DO'range => ex2_dbcr2_re )) or + (dbcr3_do(DO'range) and (DO'range => ex2_dbcr3_re )); +end generate; + +ex2_dbcr2_rdec <= (ex2_instr(11 to 20) = "1011001001"); +ex2_dbcr3_rdec <= (ex2_instr(11 to 20) = "1000011010"); +ex2_dbcr2_re <= ex2_dbcr2_rdec; +ex2_dbcr3_re <= ex2_dbcr3_rdec; + +ex6_dbcr2_wdec <= (ex6_instr(11 to 20) = "1011001001"); +ex6_dbcr3_wdec <= (ex6_instr(11 to 20) = "1000011010"); +ex6_dbcr2_we <= ex6_val and ex6_is_mtspr and ex6_dbcr2_wdec; +ex6_dbcr3_we <= ex6_val and ex6_is_mtspr and ex6_dbcr3_wdec; + +spr_dbcr2_dac1us <= dbcr2_q(35 to 36); +spr_dbcr2_dac1er <= dbcr2_q(37 to 38); +spr_dbcr2_dac2us <= dbcr2_q(39 to 40); +spr_dbcr2_dac2er <= dbcr2_q(41 to 42); +spr_dbcr2_dac12m <= dbcr2_q(43); +spr_dbcr2_dvc1m <= dbcr2_q(44 to 45); +spr_dbcr2_dvc2m <= dbcr2_q(46 to 47); +spr_dbcr2_dvc1be <= dbcr2_q(48 to 55); +spr_dbcr2_dvc2be <= dbcr2_q(56 to 63); +spr_dbcr3_dac3us <= dbcr3_q(54 to 55); +spr_dbcr3_dac3er <= dbcr3_q(56 to 57); +spr_dbcr3_dac4us <= dbcr3_q(58 to 59); +spr_dbcr3_dac4er <= dbcr3_q(60 to 61); +spr_dbcr3_dac34m <= dbcr3_q(62); +spr_dbcr3_ivc <= dbcr3_q(63); +tspr_cspr_dbcr2_dac1us <= spr_dbcr2_dac1us; +tspr_cspr_dbcr2_dac1er <= spr_dbcr2_dac1er; +tspr_cspr_dbcr2_dac2us <= spr_dbcr2_dac2us; +tspr_cspr_dbcr2_dac2er <= spr_dbcr2_dac2er; +tspr_cspr_dbcr3_dac3us <= spr_dbcr3_dac3us; +tspr_cspr_dbcr3_dac3er <= spr_dbcr3_dac3er; +tspr_cspr_dbcr3_dac4us <= spr_dbcr3_dac4us; +tspr_cspr_dbcr3_dac4er <= spr_dbcr3_dac4er; +tspr_cspr_dbcr2_dac12m <= spr_dbcr2_dac12m; +tspr_cspr_dbcr3_dac34m <= spr_dbcr3_dac34m; +tspr_cspr_dbcr2_dvc1m <= spr_dbcr2_dvc1m; +tspr_cspr_dbcr2_dvc2m <= spr_dbcr2_dvc2m; +tspr_cspr_dbcr2_dvc1be <= spr_dbcr2_dvc1be; +tspr_cspr_dbcr2_dvc2be <= spr_dbcr2_dvc2be; + +mark_unused(tiup); +mark_unused(tidn); +mark_unused(ex6_spr_wd); + + +ex6_dbcr2_di <= ex6_spr_wd(32 to 33) & + ex6_spr_wd(34 to 35) & + ex6_spr_wd(36 to 37) & + ex6_spr_wd(38 to 39) & + ex6_spr_wd(41 to 41) & + ex6_spr_wd(44 to 45) & + ex6_spr_wd(46 to 47) & + ex6_spr_wd(48 to 55) & + ex6_spr_wd(56 to 63) ; +dbcr2_do <= tidn(0 to 0) & + tidn(0 to 31) & + dbcr2_q(35 to 36) & + dbcr2_q(37 to 38) & + dbcr2_q(39 to 40) & + dbcr2_q(41 to 42) & + tidn(40 to 40) & + dbcr2_q(43 to 43) & + tidn(42 to 43) & + dbcr2_q(44 to 45) & + dbcr2_q(46 to 47) & + dbcr2_q(48 to 55) & + dbcr2_q(56 to 63) ; +ex6_dbcr3_di <= ex6_spr_wd(32 to 33) & + ex6_spr_wd(34 to 35) & + ex6_spr_wd(36 to 37) & + ex6_spr_wd(38 to 39) & + ex6_spr_wd(41 to 41) & + ex6_spr_wd(63 to 63) ; +dbcr3_do <= tidn(0 to 0) & + tidn(0 to 31) & + dbcr3_q(54 to 55) & + dbcr3_q(56 to 57) & + dbcr3_q(58 to 59) & + dbcr3_q(60 to 61) & + tidn(40 to 40) & + dbcr3_q(62 to 62) & + tidn(42 to 62) & + dbcr3_q(63 to 63) ; + +mark_unused(dbcr2_do(0 to 64-regsize)); +mark_unused(dbcr3_do(0 to 64-regsize)); + +dbcr2_latch_gen : if a2mode = 1 generate +dbcr2_latch : tri_ser_rlmreg_p +generic map(width => dbcr2_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => dbcr2_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dbcr2_offset to dbcr2_offset + dbcr2_q'length-1), + scout => sov(dbcr2_offset to dbcr2_offset + dbcr2_q'length-1), + din => dbcr2_d, + dout => dbcr2_q); +end generate; +dbcr2_latch_tie : if a2mode = 0 generate + dbcr2_q <= (others=>'0'); +end generate; +dbcr3_latch : tri_ser_rlmreg_p +generic map(width => dbcr3_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => dbcr3_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dbcr3_offset to dbcr3_offset + dbcr3_q'length-1), + scout => sov(dbcr3_offset to dbcr3_offset + dbcr3_q'length-1), + din => dbcr3_d, + dout => dbcr3_q); + + +siv(0 to scan_right-1) <= sov(1 to scan_right-1) & scan_in; +scan_out <= sov(0); + +end architecture xuq_fxu_spr_tspr; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_fxua_data.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_fxua_data.vhdl new file mode 100644 index 0000000..5df9462 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_fxua_data.vhdl @@ -0,0 +1,699 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee,ibm,support,work,tri,clib; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use support.power_logic_pkg.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use tri.tri_latches_pkg.all; +use work.xuq_pkg.all; + +entity xuq_fxua_data is +generic(expand_type : integer := 2; + regmode : integer := 6; + dc_size : natural := 14; + cl_size : natural := 6; + l_endian_m : integer := 1; + threads : integer := 4; + eff_ifar : integer := 62; + regsize : integer := 64; + a2mode : integer := 1; + hvmode : integer := 1; + real_data_add : integer := 42); +port( + + pc_xu_abist_raddr_0 : in std_ulogic_vector(1 to 9); + pc_xu_abist_raddr_1 : in std_ulogic_vector(2 to 9); + pc_xu_abist_grf_renb_0 : in std_ulogic; + pc_xu_abist_grf_renb_1 : in std_ulogic; + pc_xu_abist_ena_dc : in std_ulogic; + pc_xu_abist_waddr_0 : in std_ulogic_vector(2 to 9); + pc_xu_abist_waddr_1 : in std_ulogic_vector(2 to 9); + pc_xu_abist_grf_wenb_0 : in std_ulogic; + pc_xu_abist_grf_wenb_1 : in std_ulogic; + pc_xu_abist_di_0 : in std_ulogic_vector(0 to 3); + pc_xu_abist_di_1 : in std_ulogic_vector(0 to 3); + pc_xu_abist_wl144_comp_ena : in std_ulogic; + pc_xu_abist_raw_dc_b : in std_ulogic; + pc_xu_ccflush_dc : in std_ulogic; + clkoff_dc_b : in std_ulogic; + d_mode_dc : in std_ulogic; + delay_lclkr_dc : in std_ulogic_vector(4 to 4); + mpw1_dc_b : in std_ulogic_vector(4 to 4); + mpw2_dc_b : in std_ulogic; + g6t_clkoff_dc_b : in std_ulogic; + g6t_d_mode_dc : in std_ulogic; + g6t_delay_lclkr_dc : in std_ulogic_vector(0 to 4); + g6t_mpw1_dc_b : in std_ulogic_vector(0 to 4); + g6t_mpw2_dc_b : in std_ulogic; + an_ac_scan_diag_dc : in std_ulogic; + an_ac_lbist_ary_wrt_thru_dc : in std_ulogic; + sg_2 : in std_ulogic_vector(0 to 2); + fce_2 : in std_ulogic_vector(0 to 0); + func_sl_thold_2 : in std_ulogic_vector(0 to 3); + func_nsl_thold_2 : in std_ulogic; + abst_sl_thold_2 : in std_ulogic; + time_sl_thold_2 : in std_ulogic; + ary_nsl_thold_2 : in std_ulogic; + repr_sl_thold_2 : in std_ulogic; + gptr_sl_thold_2 : in std_ulogic; + bolt_sl_thold_2 : in std_ulogic; + bo_enable_2 : in std_ulogic; + pc_xu_bo_unload : in std_ulogic; + pc_xu_bo_load : in std_ulogic; + pc_xu_bo_repair : in std_ulogic; + pc_xu_bo_reset : in std_ulogic; + pc_xu_bo_shdata : in std_ulogic; + pc_xu_bo_select : in std_ulogic_vector(5 to 8); + xu_pc_bo_fail : out std_ulogic_vector(5 to 8); + xu_pc_bo_diagout : out std_ulogic_vector(5 to 8); + + iu_xu_is2_vld : in std_ulogic; + iu_xu_is2_ifar : in std_ulogic_vector(62-eff_ifar to 61); + iu_xu_is2_tid : in std_ulogic_vector(0 to threads-1); + iu_xu_is2_instr : in std_ulogic_vector(0 to 31); + iu_xu_is2_ta_vld : in std_ulogic; + iu_xu_is2_ta : in std_ulogic_vector(0 to 5); + iu_xu_is2_s1_vld : in std_ulogic; + iu_xu_is2_s1 : in std_ulogic_vector(0 to 5); + iu_xu_is2_s2_vld : in std_ulogic; + iu_xu_is2_s2 : in std_ulogic_vector(0 to 5); + iu_xu_is2_s3_vld : in std_ulogic; + iu_xu_is2_s3 : in std_ulogic_vector(0 to 5); + iu_xu_is2_axu_ld_or_st : in std_ulogic; + iu_xu_is2_axu_store : in std_ulogic; + iu_xu_is2_axu_ldst_size : in std_ulogic_vector(0 to 5); + iu_xu_is2_axu_ldst_update : in std_ulogic; + iu_xu_is2_axu_ldst_forcealign : in std_ulogic; + iu_xu_is2_axu_ldst_forceexcept : in std_ulogic; + iu_xu_is2_axu_ldst_extpid : in std_ulogic; + iu_xu_is2_axu_ldst_indexed : in std_ulogic; + iu_xu_is2_axu_ldst_tag : in std_ulogic_vector(0 to 8); + iu_xu_is2_axu_mftgpr : in std_ulogic; + iu_xu_is2_axu_mffgpr : in std_ulogic; + iu_xu_is2_axu_movedp : in std_ulogic; + iu_xu_is2_axu_instr_type : in std_ulogic_vector(0 to 2); + iu_xu_is2_pred_update : in std_ulogic; + iu_xu_is2_pred_taken_cnt : in std_ulogic_vector(0 to 1); + iu_xu_is2_error : in std_ulogic_vector(0 to 2); + iu_xu_is2_match : in std_ulogic; + iu_xu_is2_is_ucode : in std_ulogic; + iu_xu_is2_ucode_vld : in std_ulogic; + iu_xu_is2_gshare : in std_ulogic_vector(0 to 3); + xu_iu_multdiv_done : out std_ulogic_vector(0 to threads-1); + xu_iu_membar_tid : out std_ulogic_vector(0 to threads-1); + + lsu_xu_ldq_barr_done : in std_ulogic_vector(0 to threads-1); + lsu_xu_barr_done : in std_ulogic_vector(0 to threads-1); + + fxa_fxb_rf0_val : out std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_issued : out std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_ucode_val : out std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_act : out std_ulogic; + fxa_fxb_ex1_hold_ctr_flush : out std_ulogic; + fxa_fxb_rf0_instr : out std_ulogic_vector(0 to 31); + fxa_fxb_rf0_tid : out std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_ta_vld : out std_ulogic; + fxa_fxb_rf0_ta : out std_ulogic_vector(0 to 7); + fxa_fxb_rf0_error : out std_ulogic_vector(0 to 2); + fxa_fxb_rf0_match : out std_ulogic; + fxa_fxb_rf0_is_ucode : out std_ulogic; + fxa_fxb_rf0_gshare : out std_ulogic_vector(0 to 3); + fxa_fxb_rf0_ifar : out std_ulogic_vector(62-eff_ifar to 61); + fxa_fxb_rf0_s1_vld : out std_ulogic; + fxa_fxb_rf0_s1 : out std_ulogic_vector(0 to 7); + fxa_fxb_rf0_s2_vld : out std_ulogic; + fxa_fxb_rf0_s2 : out std_ulogic_vector(0 to 7); + fxa_fxb_rf0_s3_vld : out std_ulogic; + fxa_fxb_rf0_s3 : out std_ulogic_vector(0 to 7); + fxa_fxb_rf0_axu_instr_type : out std_ulogic_vector(0 to 2); + fxa_fxb_rf0_axu_ld_or_st : out std_ulogic; + fxa_fxb_rf0_axu_store : out std_ulogic; + fxa_fxb_rf0_axu_mftgpr : out std_ulogic; + fxa_fxb_rf0_axu_mffgpr : out std_ulogic; + fxa_fxb_rf0_axu_movedp : out std_ulogic; + fxa_fxb_rf0_axu_ldst_size : out std_ulogic_vector(0 to 5); + fxa_fxb_rf0_axu_ldst_update : out std_ulogic; + fxa_fxb_rf0_axu_ldst_forcealign : out std_ulogic; + fxa_fxb_rf0_axu_ldst_forceexcept : out std_ulogic; + fxa_fxb_rf0_axu_ldst_indexed : out std_ulogic; + fxa_fxb_rf0_axu_ldst_tag : out std_ulogic_vector(0 to 8); + fxa_fxb_rf0_pred_update : out std_ulogic; + fxa_fxb_rf0_pred_taken_cnt : out std_ulogic_vector(0 to 1); + fxa_fxb_rf0_mc_dep_chk_val : out std_ulogic_vector(0 to threads-1); + fxa_fxb_rf1_mul_val : out std_ulogic; + fxa_fxb_rf1_muldiv_coll : out std_ulogic; + fxa_fxb_rf1_div_val : out std_ulogic; + fxa_fxb_rf1_div_ctr : out std_ulogic_vector(0 to 7); + fxa_fxb_rf0_xu_epid_instr : out std_ulogic; + fxa_fxb_rf0_axu_is_extload : out std_ulogic; + fxa_fxb_rf0_axu_is_extstore : out std_ulogic; + fxa_fxb_rf0_spr_tid : out std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_cpl_tid : out std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_cpl_act : out std_ulogic; + fxa_fxb_rf0_is_mfocrf : out std_ulogic; + fxa_fxb_rf0_3src_instr : out std_ulogic; + fxa_fxb_rf0_gpr0_zero : out std_ulogic; + fxa_fxb_rf0_use_imm : out std_ulogic; + dec_cpl_ex3_mc_dep_chk_val : out std_ulogic_vector(0 to threads-1); + fxb_fxa_ex7_we0 : in std_ulogic; + fxb_fxa_ex7_wa0 : in std_ulogic_vector(0 to 7); + fxb_fxa_ex7_wd0 : in std_ulogic_vector(64-regsize to 63); + fxa_fxb_rf1_do0 : out std_ulogic_vector(64-regsize to 63); + fxa_fxb_rf1_do1 : out std_ulogic_vector(64-regsize to 63); + fxa_fxb_rf1_do2 : out std_ulogic_vector(64-regsize to 63); + fxb_fxa_ex6_clear_barrier : in std_ulogic_vector(0 to threads-1); + fxa_perf_muldiv_in_use : out std_ulogic; + + xu_is2_flush : in std_ulogic_vector(0 to threads-1); + xu_rf0_flush : in std_ulogic_vector(0 to threads-1); + xu_rf1_flush : in std_ulogic_vector(0 to threads-1); + xu_ex1_flush : in std_ulogic_vector(0 to threads-1); + xu_ex2_flush : in std_ulogic_vector(0 to threads-1); + xu_ex3_flush : in std_ulogic_vector(0 to threads-1); + xu_ex4_flush : in std_ulogic_vector(0 to threads-1); + xu_ex5_flush : in std_ulogic_vector(0 to threads-1); + fxa_cpl_ex2_div_coll : out std_ulogic_vector(0 to threads-1); + cpl_fxa_ex5_set_barr : in std_ulogic_vector(0 to threads-1); + fxa_iu_set_barr_tid : out std_ulogic_vector(0 to threads-1); + spr_xucr4_div_barr_thres : in std_ulogic_vector(0 to 7); + + an_ac_back_inv : in std_ulogic; + an_ac_back_inv_addr : in std_ulogic_vector(62 to 63); + an_ac_back_inv_target_bit3 : in std_ulogic; + + dec_spr_rf0_instr : out std_ulogic_vector(0 to 31); + + pc_xu_inj_regfile_parity : in std_ulogic_vector(0 to 3); + xu_pc_err_regfile_parity : out std_ulogic_vector(0 to threads-1); + xu_pc_err_regfile_ue : out std_ulogic_vector(0 to 3); + gpr_cpl_ex3_regfile_err_det : out std_ulogic; + cpl_gpr_regfile_seq_beg : in std_ulogic; + gpr_cpl_regfile_seq_end : out std_ulogic; + + xu_lsu_rf0_derat_is_extload : out std_ulogic; + xu_lsu_rf0_derat_is_extstore : out std_ulogic; + xu_lsu_rf0_derat_val : out std_ulogic_vector(0 to threads-1); + lsu_xu_rel_wren : in std_ulogic; + lsu_xu_rel_ta_gpr : in std_ulogic_vector(0 to 7); + fxa_cpl_debug : out std_ulogic_vector(0 to 272); + + xu_lsu_rf1_data_act :in std_ulogic; + xu_lsu_rf1_axu_ldst_falign :in std_ulogic; + xu_lsu_ex1_store_data :in std_ulogic_vector(64-(2**REGMODE) to 63); + xu_lsu_ex1_eff_addr :in std_ulogic_vector(64-(dc_size-3) to 63); + xu_lsu_ex1_rotsel_ovrd :in std_ulogic_vector(0 to 4); + ex1_optype32 :in std_ulogic; + ex1_optype16 :in std_ulogic; + ex1_optype8 :in std_ulogic; + ex1_optype4 :in std_ulogic; + ex1_optype2 :in std_ulogic; + ex1_optype1 :in std_ulogic; + ex1_store_instr :in std_ulogic; + ex1_axu_op_val :in std_ulogic; + ex1_saxu_instr :in std_ulogic; + ex1_sdp_instr :in std_ulogic; + ex1_stgpr_instr :in std_ulogic; + + fu_xu_ex2_store_data_val :in std_ulogic; + fu_xu_ex2_store_data :in std_ulogic_vector(0 to 255); + + ex3_algebraic :in std_ulogic; + ex3_data_swap :in std_ulogic; + ex3_thrd_id :in std_ulogic_vector(0 to 3); + bx_xu_ex5_dp_data :in std_ulogic_vector(0 to 127); + + ex4_load_op_hit :in std_ulogic; + ex4_store_hit :in std_ulogic; + ex4_axu_op_val :in std_ulogic; + spr_dvc1_act :in std_ulogic; + spr_dvc2_act :in std_ulogic; + spr_dvc1_dbg :in std_ulogic_vector(64-(2**regmode) to 63); + spr_dvc2_dbg :in std_ulogic_vector(64-(2**regmode) to 63); + + rel_upd_dcarr_val :in std_ulogic; + + xu_lsu_ex4_flush_local :in std_ulogic_vector(0 to 3); + + xu_pc_err_dcache_parity :out std_ulogic; + pc_xu_inj_dcache_parity :in std_ulogic; + + xu_lsu_spr_xucr0_dcdis :in std_ulogic; + spr_xucr0_clkg_ctl_b0 :in std_ulogic; + + ldq_rel_data_val_early :in std_ulogic; + ldq_rel_algebraic :in std_ulogic; + ldq_rel_data_val :in std_ulogic; + ldq_rel_ci :in std_ulogic; + ldq_rel_thrd_id :in std_ulogic_vector(0 to 3); + ldq_rel_axu_val :in std_ulogic; + ldq_rel_256_data :in std_ulogic_vector(0 to 255); + ldq_rel_rot_sel :in std_ulogic_vector(0 to 4); + ldq_rel_op_size :in std_ulogic_vector(0 to 5); + ldq_rel_le_mode :in std_ulogic; + ldq_rel_dvc1_en :in std_ulogic; + ldq_rel_dvc2_en :in std_ulogic; + ldq_rel_beat_crit_qw :in std_ulogic; + ldq_rel_beat_crit_qw_block :in std_ulogic; + ldq_rel_addr :in std_ulogic_vector(64-(dc_size-3) to 58); + + dcarr_up_way_addr :in std_ulogic_vector(0 to 2); + + ex4_256st_data :out std_ulogic_vector(0 to 255); + ex6_ld_par_err :out std_ulogic; + lsu_xu_ex6_datc_par_err :out std_ulogic; + + ex6_xu_ld_data_b :out std_ulogic_vector(64-(2**regmode) to 63); + rel_xu_ld_data :out std_ulogic_vector(64-(2**regmode) to 63); + xu_fu_ex6_load_data :out std_ulogic_vector(0 to 255); + xu_fu_ex5_load_le :out std_ulogic; + + lsu_xu_rel_dvc_thrd_id :out std_ulogic_vector(0 to 3); + lsu_xu_ex2_dvc1_st_cmp :out std_ulogic_vector(0 to ((2**regmode)/8)-1); + lsu_xu_ex8_dvc1_ld_cmp :out std_ulogic_vector(0 to ((2**regmode)/8)-1); + lsu_xu_rel_dvc1_en :out std_ulogic; + lsu_xu_rel_dvc1_cmp :out std_ulogic_vector(0 to ((2**regmode)/8)-1); + lsu_xu_ex2_dvc2_st_cmp :out std_ulogic_vector(0 to ((2**regmode)/8)-1); + lsu_xu_ex8_dvc2_ld_cmp :out std_ulogic_vector(0 to ((2**regmode)/8)-1); + lsu_xu_rel_dvc2_en :out std_ulogic; + lsu_xu_rel_dvc2_cmp :out std_ulogic_vector(0 to ((2**regmode)/8)-1); + + pc_xu_trace_bus_enable :in std_ulogic; + lsudat_debug_mux_ctrls :in std_ulogic_vector(0 to 1); + lsu_xu_data_debug0 :out std_ulogic_vector(0 to 87); + lsu_xu_data_debug1 :out std_ulogic_vector(0 to 87); + lsu_xu_data_debug2 :out std_ulogic_vector(0 to 87); + + vdd :inout power_logic; + gnd :inout power_logic; + vcs :inout power_logic; + nclk :in clk_logic; + an_ac_scan_dis_dc_b :in std_ulogic; + + pc_xu_abist_g6t_bw :in std_ulogic_vector(0 to 1); + pc_xu_abist_di_g6t_2r :in std_ulogic_vector(0 to 3); + pc_xu_abist_wl512_comp_ena :in std_ulogic; + pc_xu_abist_dcomp_g6t_2r :in std_ulogic_vector(0 to 3); + pc_xu_abist_g6t_r_wb :in std_ulogic; + + abst_scan_in :in std_ulogic_vector(0 to 1); + repr_scan_in :in std_ulogic; + gptr_scan_in :in std_ulogic; + time_scan_in :in std_ulogic; + func_scan_in :in std_ulogic_vector(0 to 3); + abst_scan_out :out std_ulogic_vector(0 to 1); + repr_scan_out :out std_ulogic; + time_scan_out :out std_ulogic; + gptr_scan_out :out std_ulogic; + func_scan_out :out std_ulogic_vector(0 to 3) +); + +-- synopsys translate_off + + +-- synopsys translate_on +end xuq_fxua_data; +architecture xuq_fxua_data of xuq_fxua_data is + +signal rel_xu_ld_data_int :std_ulogic_vector(64-(2**regmode) to 64+((2**regmode)/8)-1); +signal dat_abst_scan_in :std_ulogic; +signal dat_time_scan_in :std_ulogic; + +begin + + xuq_fxu_a : entity work.xuq_fxu_a(xuq_fxu_a) + generic map( + expand_type => expand_type, + threads => threads, + eff_ifar => eff_ifar, + regmode => regmode, + regsize => regsize, + a2mode => a2mode, + hvmode => hvmode, + real_data_add => real_data_add) + port map( + nclk => nclk, + vdd => vdd, + gnd => gnd, + vcs => vcs, + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b, + func_scan_in => func_scan_in(0 to 0), + func_scan_out => func_scan_out(0 to 0), + abst_scan_in => abst_scan_in(0), + abst_scan_out => abst_scan_out(0), + an_ac_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc, + pc_xu_abist_raddr_0 => pc_xu_abist_raddr_0(2 to 9), + pc_xu_abist_raddr_1 => pc_xu_abist_raddr_1(2 to 9), + pc_xu_abist_grf_renb_0 => pc_xu_abist_grf_renb_0, + pc_xu_abist_grf_renb_1 => pc_xu_abist_grf_renb_1, + pc_xu_abist_ena_dc => pc_xu_abist_ena_dc, + pc_xu_abist_waddr_0 => pc_xu_abist_waddr_0(2 to 9), + pc_xu_abist_waddr_1 => pc_xu_abist_waddr_1(2 to 9), + pc_xu_abist_grf_wenb_0 => pc_xu_abist_grf_wenb_0, + pc_xu_abist_grf_wenb_1 => pc_xu_abist_grf_wenb_1, + pc_xu_abist_di_0 => pc_xu_abist_di_0, + pc_xu_abist_di_1 => pc_xu_abist_di_1, + pc_xu_abist_wl144_comp_ena => pc_xu_abist_wl144_comp_ena, + pc_xu_abist_raw_dc_b => pc_xu_abist_raw_dc_b, + pc_xu_ccflush_dc => pc_xu_ccflush_dc, + clkoff_dc_b => clkoff_dc_b, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc(4 to 4), + mpw1_dc_b => mpw1_dc_b(4 to 4), + mpw2_dc_b => mpw2_dc_b, + bolt_sl_thold_2 => bolt_sl_thold_2, + bo_enable_2 => bo_enable_2, + pc_xu_bo_unload => pc_xu_bo_unload, + pc_xu_bo_load => pc_xu_bo_load, + pc_xu_bo_reset => pc_xu_bo_reset, + pc_xu_bo_shdata => pc_xu_bo_shdata, + pc_xu_bo_select => pc_xu_bo_select(7 to 8), + xu_pc_bo_fail => xu_pc_bo_fail(7 to 8), + xu_pc_bo_diagout => xu_pc_bo_diagout(7 to 8), + an_ac_scan_diag_dc => an_ac_scan_diag_dc, + scan_dis_dc_b => an_ac_scan_dis_dc_b, + sg_2 => sg_2(0 to 0), + fce_2 => fce_2(0 to 0), + func_sl_thold_2 => func_sl_thold_2(0 to 0), + func_nsl_thold_2 => func_nsl_thold_2, + abst_sl_thold_2 => abst_sl_thold_2, + time_sl_thold_2 => time_sl_thold_2, + ary_nsl_thold_2 => ary_nsl_thold_2, + gptr_sl_thold_2 => gptr_sl_thold_2, + time_scan_in => time_scan_in, + time_scan_out => dat_time_scan_in, + gptr_scan_in => gptr_scan_in, + gptr_scan_out => gptr_scan_out, + iu_xu_is2_vld => iu_xu_is2_vld, + iu_xu_is2_ifar => iu_xu_is2_ifar, + iu_xu_is2_tid => iu_xu_is2_tid, + iu_xu_is2_instr => iu_xu_is2_instr, + iu_xu_is2_ta_vld => iu_xu_is2_ta_vld, + iu_xu_is2_ta => iu_xu_is2_ta, + iu_xu_is2_s1_vld => iu_xu_is2_s1_vld, + iu_xu_is2_s1 => iu_xu_is2_s1, + iu_xu_is2_s2_vld => iu_xu_is2_s2_vld, + iu_xu_is2_s2 => iu_xu_is2_s2, + iu_xu_is2_s3_vld => iu_xu_is2_s3_vld, + iu_xu_is2_s3 => iu_xu_is2_s3, + iu_xu_is2_axu_ld_or_st => iu_xu_is2_axu_ld_or_st, + iu_xu_is2_axu_store => iu_xu_is2_axu_store, + iu_xu_is2_axu_ldst_size => iu_xu_is2_axu_ldst_size, + iu_xu_is2_axu_ldst_update => iu_xu_is2_axu_ldst_update, + iu_xu_is2_axu_ldst_forcealign => iu_xu_is2_axu_ldst_forcealign, + iu_xu_is2_axu_ldst_forceexcept => iu_xu_is2_axu_ldst_forceexcept, + iu_xu_is2_axu_ldst_extpid => iu_xu_is2_axu_ldst_extpid, + iu_xu_is2_axu_ldst_indexed => iu_xu_is2_axu_ldst_indexed, + iu_xu_is2_axu_ldst_tag => iu_xu_is2_axu_ldst_tag, + iu_xu_is2_axu_mftgpr => iu_xu_is2_axu_mftgpr, + iu_xu_is2_axu_mffgpr => iu_xu_is2_axu_mffgpr, + iu_xu_is2_axu_movedp => iu_xu_is2_axu_movedp, + iu_xu_is2_axu_instr_type => iu_xu_is2_axu_instr_type, + iu_xu_is2_pred_update => iu_xu_is2_pred_update, + iu_xu_is2_pred_taken_cnt => iu_xu_is2_pred_taken_cnt, + iu_xu_is2_error => iu_xu_is2_error, + iu_xu_is2_match => iu_xu_is2_match, + iu_xu_is2_is_ucode => iu_xu_is2_is_ucode, + iu_xu_is2_ucode_vld => iu_xu_is2_ucode_vld, + iu_xu_is2_gshare => iu_xu_is2_gshare, + xu_iu_multdiv_done => xu_iu_multdiv_done, + xu_iu_membar_tid => xu_iu_membar_tid, + lsu_xu_ldq_barr_done => lsu_xu_ldq_barr_done, + lsu_xu_barr_done => lsu_xu_barr_done, + fxa_fxb_rf0_val => fxa_fxb_rf0_val, + fxa_fxb_rf0_issued => fxa_fxb_rf0_issued, + fxa_fxb_rf0_ucode_val => fxa_fxb_rf0_ucode_val, + fxa_fxb_rf0_act => fxa_fxb_rf0_act, + fxa_fxb_ex1_hold_ctr_flush => fxa_fxb_ex1_hold_ctr_flush, + fxa_fxb_rf0_instr => fxa_fxb_rf0_instr, + fxa_fxb_rf0_tid => fxa_fxb_rf0_tid, + fxa_fxb_rf0_ta_vld => fxa_fxb_rf0_ta_vld, + fxa_fxb_rf0_ta => fxa_fxb_rf0_ta, + fxa_fxb_rf0_error => fxa_fxb_rf0_error, + fxa_fxb_rf0_match => fxa_fxb_rf0_match, + fxa_fxb_rf0_is_ucode => fxa_fxb_rf0_is_ucode, + fxa_fxb_rf0_gshare => fxa_fxb_rf0_gshare, + fxa_fxb_rf0_ifar => fxa_fxb_rf0_ifar, + fxa_fxb_rf0_s1_vld => fxa_fxb_rf0_s1_vld, + fxa_fxb_rf0_s1 => fxa_fxb_rf0_s1, + fxa_fxb_rf0_s2_vld => fxa_fxb_rf0_s2_vld, + fxa_fxb_rf0_s2 => fxa_fxb_rf0_s2, + fxa_fxb_rf0_s3_vld => fxa_fxb_rf0_s3_vld, + fxa_fxb_rf0_s3 => fxa_fxb_rf0_s3, + fxa_fxb_rf0_axu_instr_type => fxa_fxb_rf0_axu_instr_type, + fxa_fxb_rf0_axu_ld_or_st => fxa_fxb_rf0_axu_ld_or_st, + fxa_fxb_rf0_axu_store => fxa_fxb_rf0_axu_store, + fxa_fxb_rf0_axu_mftgpr => fxa_fxb_rf0_axu_mftgpr, + fxa_fxb_rf0_axu_mffgpr => fxa_fxb_rf0_axu_mffgpr, + fxa_fxb_rf0_axu_movedp => fxa_fxb_rf0_axu_movedp, + fxa_fxb_rf0_axu_ldst_size => fxa_fxb_rf0_axu_ldst_size, + fxa_fxb_rf0_axu_ldst_update => fxa_fxb_rf0_axu_ldst_update, + fxa_fxb_rf0_axu_ldst_forcealign => fxa_fxb_rf0_axu_ldst_forcealign, + fxa_fxb_rf0_axu_ldst_forceexcept => fxa_fxb_rf0_axu_ldst_forceexcept, + fxa_fxb_rf0_axu_ldst_indexed => fxa_fxb_rf0_axu_ldst_indexed, + fxa_fxb_rf0_axu_ldst_tag => fxa_fxb_rf0_axu_ldst_tag, + fxa_fxb_rf0_pred_update => fxa_fxb_rf0_pred_update, + fxa_fxb_rf0_pred_taken_cnt => fxa_fxb_rf0_pred_taken_cnt, + fxa_fxb_rf0_mc_dep_chk_val => fxa_fxb_rf0_mc_dep_chk_val, + fxa_fxb_rf1_mul_val => fxa_fxb_rf1_mul_val, + fxa_fxb_rf1_muldiv_coll => fxa_fxb_rf1_muldiv_coll, + fxa_fxb_rf1_div_val => fxa_fxb_rf1_div_val, + fxa_fxb_rf1_div_ctr => fxa_fxb_rf1_div_ctr, + fxa_fxb_rf0_xu_epid_instr => fxa_fxb_rf0_xu_epid_instr, + fxa_fxb_rf0_axu_is_extload => fxa_fxb_rf0_axu_is_extload, + fxa_fxb_rf0_axu_is_extstore => fxa_fxb_rf0_axu_is_extstore, + fxa_fxb_rf0_is_mfocrf => fxa_fxb_rf0_is_mfocrf, + fxa_fxb_rf0_3src_instr => fxa_fxb_rf0_3src_instr, + fxa_fxb_rf0_gpr0_zero => fxa_fxb_rf0_gpr0_zero, + fxa_fxb_rf0_use_imm => fxa_fxb_rf0_use_imm, + fxb_fxa_ex7_we0 => fxb_fxa_ex7_we0, + fxb_fxa_ex7_wa0 => fxb_fxa_ex7_wa0, + fxb_fxa_ex7_wd0 => fxb_fxa_ex7_wd0, + fxa_fxb_rf1_do0 => fxa_fxb_rf1_do0, + fxa_fxb_rf1_do1 => fxa_fxb_rf1_do1, + fxa_fxb_rf1_do2 => fxa_fxb_rf1_do2, + fxb_fxa_ex6_clear_barrier => fxb_fxa_ex6_clear_barrier, + fxa_perf_muldiv_in_use => fxa_perf_muldiv_in_use, + dec_cpl_ex3_mc_dep_chk_val => dec_cpl_ex3_mc_dep_chk_val, + xu_is2_flush => xu_is2_flush, + xu_rf0_flush => xu_rf0_flush, + xu_rf1_flush => xu_rf1_flush, + xu_ex1_flush => xu_ex1_flush, + xu_ex2_flush => xu_ex2_flush, + xu_ex3_flush => xu_ex3_flush, + xu_ex4_flush => xu_ex4_flush, + xu_ex5_flush => xu_ex5_flush, + fxa_cpl_ex2_div_coll => fxa_cpl_ex2_div_coll, + cpl_fxa_ex5_set_barr => cpl_fxa_ex5_set_barr, + fxa_iu_set_barr_tid => fxa_iu_set_barr_tid, + spr_xucr4_div_barr_thres => spr_xucr4_div_barr_thres, + an_ac_back_inv => an_ac_back_inv, + an_ac_back_inv_addr => an_ac_back_inv_addr(62 to 63), + an_ac_back_inv_target_bit3 => an_ac_back_inv_target_bit3, + dec_spr_rf0_instr => dec_spr_rf0_instr, + pc_xu_inj_regfile_parity => pc_xu_inj_regfile_parity, + xu_pc_err_regfile_parity => xu_pc_err_regfile_parity, + xu_pc_err_regfile_ue => xu_pc_err_regfile_ue, + gpr_cpl_ex3_regfile_err_det => gpr_cpl_ex3_regfile_err_det, + cpl_gpr_regfile_seq_beg => cpl_gpr_regfile_seq_beg, + gpr_cpl_regfile_seq_end => gpr_cpl_regfile_seq_end, + xu_lsu_rf0_derat_is_extload => xu_lsu_rf0_derat_is_extload, + xu_lsu_rf0_derat_is_extstore => xu_lsu_rf0_derat_is_extstore, + xu_lsu_rf0_derat_val => xu_lsu_rf0_derat_val, + lsu_xu_rel_wren => lsu_xu_rel_wren, + lsu_xu_rel_ta_gpr => lsu_xu_rel_ta_gpr, + lsu_xu_rot_rel_data => rel_xu_ld_data_int, + fxa_fxb_rf0_spr_tid => fxa_fxb_rf0_spr_tid, + fxa_fxb_rf0_cpl_tid => fxa_fxb_rf0_cpl_tid, + fxa_fxb_rf0_cpl_act => fxa_fxb_rf0_cpl_act, + fxa_cpl_debug => fxa_cpl_debug, + spr_xucr0_clkg_ctl_b0 => spr_xucr0_clkg_ctl_b0 + ); + + +lsudata : entity work.xuq_lsu_data(xuq_lsu_data) +generic map(expand_type => expand_type, + regmode => regmode, + dc_size => dc_size, + l_endian_m => l_endian_m) +port map( + + xu_lsu_rf1_data_act => xu_lsu_rf1_data_act, + xu_lsu_rf1_axu_ldst_falign => xu_lsu_rf1_axu_ldst_falign, + xu_lsu_ex1_store_data => xu_lsu_ex1_store_data, + xu_lsu_ex1_eff_addr => xu_lsu_ex1_eff_addr, + xu_lsu_ex1_rotsel_ovrd => xu_lsu_ex1_rotsel_ovrd, + ex1_optype32 => ex1_optype32, + ex1_optype16 => ex1_optype16, + ex1_optype8 => ex1_optype8, + ex1_optype4 => ex1_optype4, + ex1_optype2 => ex1_optype2, + ex1_optype1 => ex1_optype1, + ex1_store_instr => ex1_store_instr, + ex1_axu_op_val => ex1_axu_op_val, + ex1_saxu_instr => ex1_saxu_instr, + ex1_sdp_instr => ex1_sdp_instr, + ex1_stgpr_instr => ex1_stgpr_instr, + fu_xu_ex2_store_data_val => fu_xu_ex2_store_data_val, + fu_xu_ex2_store_data => fu_xu_ex2_store_data, + + ex3_algebraic => ex3_algebraic, + ex3_data_swap => ex3_data_swap, + ex3_thrd_id => ex3_thrd_id, + ex5_dp_data => bx_xu_ex5_dp_data, + + ex4_load_op_hit => ex4_load_op_hit, + ex4_store_hit => ex4_store_hit, + ex4_axu_op_val => ex4_axu_op_val, + spr_dvc1_act => spr_dvc1_act, + spr_dvc2_act => spr_dvc2_act, + spr_dvc1_dbg => spr_dvc1_dbg, + spr_dvc2_dbg => spr_dvc2_dbg, + + rel_upd_dcarr_val => rel_upd_dcarr_val, + + xu_lsu_ex4_flush => xu_ex4_flush, + xu_lsu_ex4_flush_local => xu_lsu_ex4_flush_local, + xu_lsu_ex5_flush => xu_ex5_flush, + + xu_pc_err_dcache_parity => xu_pc_err_dcache_parity, + pc_xu_inj_dcache_parity => pc_xu_inj_dcache_parity, + + xu_lsu_spr_xucr0_dcdis => xu_lsu_spr_xucr0_dcdis, + spr_xucr0_clkg_ctl_b0 => spr_xucr0_clkg_ctl_b0, + + ldq_rel_data_val_early => ldq_rel_data_val_early, + ldq_rel_algebraic => ldq_rel_algebraic, + ldq_rel_data_val => ldq_rel_data_val, + ldq_rel_ci => ldq_rel_ci, + ldq_rel_thrd_id => ldq_rel_thrd_id, + ldq_rel_axu_val => ldq_rel_axu_val, + ldq_rel_data => ldq_rel_256_data, + ldq_rel_rot_sel => ldq_rel_rot_sel, + ldq_rel_op_size => ldq_rel_op_size, + ldq_rel_le_mode => ldq_rel_le_mode, + ldq_rel_dvc1_en => ldq_rel_dvc1_en, + ldq_rel_dvc2_en => ldq_rel_dvc2_en, + ldq_rel_beat_crit_qw => ldq_rel_beat_crit_qw, + ldq_rel_beat_crit_qw_block => ldq_rel_beat_crit_qw_block, + ldq_rel_addr => ldq_rel_addr, + + dcarr_up_way_addr => dcarr_up_way_addr, + + ex4_256st_data => ex4_256st_data, + ex6_ld_par_err => ex6_ld_par_err, + lsu_xu_ex6_datc_par_err => lsu_xu_ex6_datc_par_err, + + ex6_xu_ld_data_b => ex6_xu_ld_data_b, + rel_xu_ld_data => rel_xu_ld_data_int, + xu_fu_ex6_load_data => xu_fu_ex6_load_data, + xu_fu_ex5_load_le => xu_fu_ex5_load_le, + + lsu_xu_rel_dvc_thrd_id => lsu_xu_rel_dvc_thrd_id, + lsu_xu_ex2_dvc1_st_cmp => lsu_xu_ex2_dvc1_st_cmp, + lsu_xu_ex8_dvc1_ld_cmp => lsu_xu_ex8_dvc1_ld_cmp, + lsu_xu_rel_dvc1_en => lsu_xu_rel_dvc1_en, + lsu_xu_rel_dvc1_cmp => lsu_xu_rel_dvc1_cmp, + lsu_xu_ex2_dvc2_st_cmp => lsu_xu_ex2_dvc2_st_cmp, + lsu_xu_ex8_dvc2_ld_cmp => lsu_xu_ex8_dvc2_ld_cmp, + lsu_xu_rel_dvc2_en => lsu_xu_rel_dvc2_en, + lsu_xu_rel_dvc2_cmp => lsu_xu_rel_dvc2_cmp, + + pc_xu_trace_bus_enable => pc_xu_trace_bus_enable, + lsudat_debug_mux_ctrls => lsudat_debug_mux_ctrls, + lsu_xu_data_debug0 => lsu_xu_data_debug0, + lsu_xu_data_debug1 => lsu_xu_data_debug1, + lsu_xu_data_debug2 => lsu_xu_data_debug2, + + vdd => vdd, + gnd => gnd, + vcs => vcs, + nclk => nclk, + pc_xu_ccflush_dc => pc_xu_ccflush_dc, + clkoff_dc_b => clkoff_dc_b, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc(4 to 4), + mpw1_dc_b => mpw1_dc_b(4 to 4), + mpw2_dc_b => mpw2_dc_b, + g6t_clkoff_dc_b => g6t_clkoff_dc_b, + g6t_d_mode_dc => g6t_d_mode_dc, + g6t_delay_lclkr_dc => g6t_delay_lclkr_dc, + g6t_mpw1_dc_b => g6t_mpw1_dc_b, + g6t_mpw2_dc_b => g6t_mpw2_dc_b, + sg_2 => sg_2(2), + fce_2 => fce_2(0), + func_sl_thold_2 => func_sl_thold_2(3), + func_nsl_thold_2 => func_nsl_thold_2, + abst_sl_thold_2 => abst_sl_thold_2, + time_sl_thold_2 => time_sl_thold_2, + ary_nsl_thold_2 => ary_nsl_thold_2, + repr_sl_thold_2 => repr_sl_thold_2, + bolt_sl_thold_2 => bolt_sl_thold_2, + bo_enable_2 => bo_enable_2, + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b, + an_ac_scan_diag_dc => an_ac_scan_diag_dc, + + an_ac_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc, + pc_xu_abist_ena_dc => pc_xu_abist_ena_dc, + pc_xu_abist_g6t_bw => pc_xu_abist_g6t_bw, + pc_xu_abist_di_g6t_2r => pc_xu_abist_di_g6t_2r, + pc_xu_abist_wl512_comp_ena => pc_xu_abist_wl512_comp_ena, + pc_xu_abist_raw_dc_b => pc_xu_abist_raw_dc_b, + pc_xu_abist_dcomp_g6t_2r => pc_xu_abist_dcomp_g6t_2r, + pc_xu_abist_raddr_0 => pc_xu_abist_raddr_0(1 to 9), + pc_xu_abist_g6t_r_wb => pc_xu_abist_g6t_r_wb, + pc_xu_bo_unload => pc_xu_bo_unload, + pc_xu_bo_repair => pc_xu_bo_repair, + pc_xu_bo_reset => pc_xu_bo_reset, + pc_xu_bo_shdata => pc_xu_bo_shdata, + pc_xu_bo_select => pc_xu_bo_select(5 to 6), + xu_pc_bo_fail => xu_pc_bo_fail(5 to 6), + xu_pc_bo_diagout => xu_pc_bo_diagout(5 to 6), + + abst_scan_in(0) => abst_scan_in(1), + abst_scan_in(1) => dat_abst_scan_in, + abst_scan_out(0) => dat_abst_scan_in, + abst_scan_out(1) => abst_scan_out(1), + + time_scan_in => dat_time_scan_in, + repr_scan_in => repr_scan_in, + time_scan_out => time_scan_out, + repr_scan_out => repr_scan_out, + func_scan_in => func_scan_in(1 to 3), + func_scan_out => func_scan_out(1 to 3) +); + +rel_xu_ld_data <= rel_xu_ld_data_int(64-(2**regmode) to 63); + +mark_unused(sg_2(1)); +mark_unused(func_sl_thold_2(1 to 2)); + +end xuq_fxua_data; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_cmd.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_cmd.vhdl new file mode 100644 index 0000000..a68208c --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_cmd.vhdl @@ -0,0 +1,2608 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ibm, ieee, work, tri, support; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use tri.tri_latches_pkg.all; +use support.power_logic_pkg.all; +use work.xuq_pkg.mark_unused; + +entity xuq_lsu_cmd is +generic(expand_type : integer := 2; + lmq_entries : integer := 8; + l_endian_m : integer := 1; + regmode : integer := 6; + dc_size : natural := 14; + cl_size : natural := 6; + real_data_add : integer := 42; + a2mode : integer := 1; + load_credits : integer := 4; + store_credits : integer := 20; + st_data_32B_mode : integer := 1; + bcfg_epn_0to15 : integer := 0; + bcfg_epn_16to31 : integer := 0; + bcfg_epn_32to47 : integer := (2**16)-1; + bcfg_epn_48to51 : integer := (2**4)-1; + bcfg_rpn_22to31 : integer := (2**10)-1; + bcfg_rpn_32to47 : integer := (2**16)-1; + bcfg_rpn_48to51 : integer := (2**4)-1); +port( + xu_lsu_rf0_act :in std_ulogic; + xu_lsu_rf1_cmd_act :in std_ulogic; + xu_lsu_rf1_axu_op_val :in std_ulogic; + xu_lsu_rf1_axu_ldst_falign :in std_ulogic; + xu_lsu_rf1_axu_ldst_fexcpt :in std_ulogic; + xu_lsu_rf1_cache_acc :in std_ulogic; + xu_lsu_rf1_thrd_id :in std_ulogic_vector(0 to 3); + xu_lsu_rf1_optype1 :in std_ulogic; + xu_lsu_rf1_optype2 :in std_ulogic; + xu_lsu_rf1_optype4 :in std_ulogic; + xu_lsu_rf1_optype8 :in std_ulogic; + xu_lsu_rf1_optype16 :in std_ulogic; + xu_lsu_rf1_optype32 :in std_ulogic; + xu_lsu_rf1_target_gpr :in std_ulogic_vector(0 to 8); + xu_lsu_rf1_mtspr_trace :in std_ulogic; + xu_lsu_rf1_load_instr :in std_ulogic; + xu_lsu_rf1_store_instr :in std_ulogic; + xu_lsu_rf1_dcbf_instr :in std_ulogic; + xu_lsu_rf1_sync_instr :in std_ulogic; + xu_lsu_rf1_l_fld :in std_ulogic_vector(0 to 1); + xu_lsu_rf1_dcbi_instr :in std_ulogic; + xu_lsu_rf1_dcbz_instr :in std_ulogic; + xu_lsu_rf1_dcbt_instr :in std_ulogic; + xu_lsu_rf1_dcbtst_instr :in std_ulogic; + xu_lsu_rf1_th_fld :in std_ulogic_vector(0 to 4); + xu_lsu_rf1_dcbtls_instr :in std_ulogic; + xu_lsu_rf1_dcbtstls_instr :in std_ulogic; + xu_lsu_rf1_dcblc_instr :in std_ulogic; + xu_lsu_rf1_dcbst_instr :in std_ulogic; + xu_lsu_rf1_icbi_instr :in std_ulogic; + xu_lsu_rf1_icblc_instr :in std_ulogic; + xu_lsu_rf1_icbt_instr :in std_ulogic; + xu_lsu_rf1_icbtls_instr :in std_ulogic; + xu_lsu_rf1_icswx_instr :in std_ulogic; + xu_lsu_rf1_icswx_dot_instr :in std_ulogic; + xu_lsu_rf1_icswx_epid :in std_ulogic; + xu_lsu_rf1_tlbsync_instr :in std_ulogic; + xu_lsu_rf1_ldawx_instr :in std_ulogic; + xu_lsu_rf1_wclr_instr :in std_ulogic; + xu_lsu_rf1_wchk_instr :in std_ulogic; + xu_lsu_rf1_lock_instr :in std_ulogic; + xu_lsu_rf1_mutex_hint :in std_ulogic; + xu_lsu_rf1_mbar_instr :in std_ulogic; + xu_lsu_rf1_is_msgsnd :in std_ulogic; + xu_lsu_rf1_dci_instr :in std_ulogic; + xu_lsu_rf1_ici_instr :in std_ulogic; + xu_lsu_rf1_algebraic :in std_ulogic; + xu_lsu_rf1_byte_rev :in std_ulogic; + xu_lsu_rf1_src_gpr :in std_ulogic; + xu_lsu_rf1_src_axu :in std_ulogic; + xu_lsu_rf1_src_dp :in std_ulogic; + xu_lsu_rf1_targ_gpr :in std_ulogic; + xu_lsu_rf1_targ_axu :in std_ulogic; + xu_lsu_rf1_targ_dp :in std_ulogic; + xu_lsu_ex4_val :in std_ulogic_vector(0 to 3); + xu_lsu_ex1_add_src0 :in std_ulogic_vector(64-(2**REGMODE) to 63); + xu_lsu_ex1_add_src1 :in std_ulogic_vector(64-(2**REGMODE) to 63); + xu_lsu_ex2_instr_trace_val :in std_ulogic; + + xu_lsu_rf1_src0_vld :in std_ulogic; + xu_lsu_rf1_src0_reg :in std_ulogic_vector(0 to 7); + xu_lsu_rf1_src1_vld :in std_ulogic; + xu_lsu_rf1_src1_reg :in std_ulogic_vector(0 to 7); + xu_lsu_rf1_targ_vld :in std_ulogic; + xu_lsu_rf1_targ_reg :in std_ulogic_vector(0 to 7); + + pc_xu_inj_dcachedir_parity :in std_ulogic; + pc_xu_inj_dcachedir_multihit :in std_ulogic; + + ex4_256st_data :in std_ulogic_vector(0 to 255); + xu_lsu_ex4_dvc1_en :in std_ulogic; + xu_lsu_ex4_dvc2_en :in std_ulogic; + + xu_lsu_mtspr_trace_en :in std_ulogic_vector(0 to 3); + spr_xucr0_clkg_ctl_b1 :in std_ulogic; + spr_xucr0_clkg_ctl_b3 :in std_ulogic; + spr_xucr4_mmu_mchk :in std_ulogic; + xu_lsu_spr_xucr0_aflsta :in std_ulogic; + xu_lsu_spr_xucr0_flsta :in std_ulogic; + xu_lsu_spr_xucr0_l2siw :in std_ulogic; + xu_lsu_spr_xucr0_dcdis :in std_ulogic; + xu_lsu_spr_xucr0_wlk :in std_ulogic; + xu_lsu_spr_xucr0_clfc :in std_ulogic; + xu_lsu_spr_xucr0_flh2l2 :in std_ulogic; + xu_lsu_spr_xucr0_cred :in std_ulogic; + xu_lsu_spr_xucr0_rel :in std_ulogic; + xu_lsu_spr_xucr0_mbar_ack :in std_ulogic; + xu_lsu_spr_xucr0_tlbsync :in std_ulogic; + xu_lsu_spr_xucr0_cls :in std_ulogic; + xu_lsu_spr_ccr2_dfrat :in std_ulogic; + xu_lsu_spr_ccr2_dfratsc :in std_ulogic_vector(0 to 8); + + an_ac_flh2l2_gate :in std_ulogic; + + xu_lsu_dci :in std_ulogic; + + xu_lsu_rf0_derat_val :in std_ulogic_vector(0 to 3); + xu_lsu_rf1_derat_act :in std_ulogic; + xu_lsu_rf1_derat_ra_eq_ea :in std_ulogic; + xu_lsu_rf1_derat_is_load :in std_ulogic; + xu_lsu_rf1_derat_is_store :in std_ulogic; + xu_lsu_rf0_derat_is_extload :in std_ulogic; + xu_lsu_rf0_derat_is_extstore :in std_ulogic; + xu_lsu_rf1_is_eratre :in std_ulogic; + xu_lsu_rf1_is_eratwe :in std_ulogic; + xu_lsu_rf1_is_eratsx :in std_ulogic; + xu_lsu_rf1_is_eratilx :in std_ulogic; + xu_lsu_ex1_is_isync :in std_ulogic; + xu_lsu_ex1_is_csync :in std_ulogic; + xu_lsu_rf1_is_touch :in std_ulogic; + xu_lsu_rf1_ws :in std_ulogic_vector(0 to 1); + xu_lsu_rf1_t :in std_ulogic_vector(0 to 2); + xu_lsu_ex1_rs_is :in std_ulogic_vector(0 to 8); + xu_lsu_ex1_ra_entry :in std_ulogic_vector(0 to 4); + xu_lsu_ex4_rs_data :in std_ulogic_vector(64-(2**REGMODE) to 63); + xu_lsu_msr_gs :in std_ulogic_vector(0 to 3); + xu_lsu_msr_pr :in std_ulogic_vector(0 to 3); + xu_lsu_msr_ds :in std_ulogic_vector(0 to 3); + xu_lsu_msr_cm :in std_ulogic_vector(0 to 3); + xu_lsu_hid_mmu_mode :in std_ulogic; + ex6_ld_par_err :in std_ulogic; + + xu_lsu_rf0_flush :in std_ulogic_vector(0 to 3); + xu_lsu_rf1_flush :in std_ulogic_vector(0 to 3); + xu_lsu_ex1_flush :in std_ulogic_vector(0 to 3); + xu_lsu_ex2_flush :in std_ulogic_vector(0 to 3); + xu_lsu_ex3_flush :in std_ulogic_vector(0 to 3); + xu_lsu_ex4_flush :in std_ulogic_vector(0 to 3); + xu_lsu_ex5_flush :in std_ulogic_vector(0 to 3); + + lsu_xu_ex4_tlb_data :out std_ulogic_vector(64-(2**REGMODE) to 63); + xu_mm_derat_req :out std_ulogic; + xu_mm_derat_thdid :out std_ulogic_vector(0 to 3); + xu_mm_derat_state :out std_ulogic_vector(0 to 3); + xu_mm_derat_tid :out std_ulogic_vector(0 to 13); + xu_mm_derat_lpid :out std_ulogic_vector(0 to 7); + xu_mm_derat_ttype :out std_ulogic_vector(0 to 1); + mm_xu_derat_rel_val :in std_ulogic_vector(0 to 4); + mm_xu_derat_rel_data :in std_ulogic_vector(0 to 131); + mm_xu_derat_pid0 :in std_ulogic_vector(0 to 13); + mm_xu_derat_pid1 :in std_ulogic_vector(0 to 13); + mm_xu_derat_pid2 :in std_ulogic_vector(0 to 13); + mm_xu_derat_pid3 :in std_ulogic_vector(0 to 13); + mm_xu_derat_mmucr0_0 :in std_ulogic_vector(0 to 19); + mm_xu_derat_mmucr0_1 :in std_ulogic_vector(0 to 19); + mm_xu_derat_mmucr0_2 :in std_ulogic_vector(0 to 19); + mm_xu_derat_mmucr0_3 :in std_ulogic_vector(0 to 19); + xu_mm_derat_mmucr0 :out std_ulogic_vector(0 to 17); + xu_mm_derat_mmucr0_we :out std_ulogic_vector(0 to 3); + mm_xu_derat_mmucr1 :in std_ulogic_vector(0 to 9); + xu_mm_derat_mmucr1 :out std_ulogic_vector(0 to 4); + xu_mm_derat_mmucr1_we :out std_ulogic; + mm_xu_derat_snoop_coming :in std_ulogic; + mm_xu_derat_snoop_val :in std_ulogic; + mm_xu_derat_snoop_attr :in std_ulogic_vector(0 to 25); + mm_xu_derat_snoop_vpn :in std_ulogic_vector(64-(2**REGMODE) to 51); + xu_mm_derat_snoop_ack :out std_ulogic; + + xu_lsu_slowspr_val :in std_ulogic; + xu_lsu_slowspr_rw :in std_ulogic; + xu_lsu_slowspr_etid :in std_ulogic_vector(0 to 1); + xu_lsu_slowspr_addr :in std_ulogic_vector(0 to 9); + xu_lsu_slowspr_data :in std_ulogic_vector(64-(2**REGMODE) to 63); + xu_lsu_slowspr_done :in std_ulogic; + slowspr_val_out :out std_ulogic; + slowspr_rw_out :out std_ulogic; + slowspr_etid_out :out std_ulogic_vector(0 to 1); + slowspr_addr_out :out std_ulogic_vector(0 to 9); + slowspr_data_out :out std_ulogic_vector(64-(2**REGMODE) to 63); + slowspr_done_out :out std_ulogic; + + ex1_optype1 :out std_ulogic; + ex1_optype2 :out std_ulogic; + ex1_optype4 :out std_ulogic; + ex1_optype8 :out std_ulogic; + ex1_optype16 :out std_ulogic; + ex1_optype32 :out std_ulogic; + ex1_saxu_instr :out std_ulogic; + ex1_sdp_instr :out std_ulogic; + ex1_stgpr_instr :out std_ulogic; + ex1_store_instr :out std_ulogic; + ex1_axu_op_val :out std_ulogic; + + lsu_xu_ex3_align :out std_ulogic_vector(0 to 3); + lsu_xu_ex3_dsi :out std_ulogic_vector(0 to 3); + lsu_xu_ex3_inval_align_2ucode :out std_ulogic; + lsu_xu_ex3_attr :out std_ulogic_vector(0 to 8); + lsu_xu_ex3_derat_vf :out std_ulogic; + + lsu_xu_ex3_n_flush_req :out std_ulogic; + lsu_xu_datc_perr_recovery :out std_ulogic; + lsu_xu_l2_ecc_err_flush :out std_ulogic_vector(0 to 3); + lsu_xu_ex4_ldq_full_flush :out std_ulogic; + lsu_xu_ex3_ldq_hit_flush :out std_ulogic; + lsu_xu_ex3_dep_flush :out std_ulogic; + lsu_xu_ex3_l2_uc_ecc_err :out std_ulogic_vector(0 to 3); + lsu_xu_ex3_derat_par_err :out std_ulogic_vector(0 to 3); + lsu_xu_ex3_derat_multihit_err :out std_ulogic_vector(0 to 3); + lsu_xu_ex4_derat_par_err :out std_ulogic_vector(0 to 3); + derat_xu_ex3_miss :out std_ulogic_vector(0 to 3); + derat_xu_ex3_dsi :out std_ulogic_vector(0 to 3); + derat_xu_ex3_n_flush_req :out std_ulogic_vector(0 to 3); + + ex3_algebraic :out std_ulogic; + ex3_data_swap :out std_ulogic; + ex3_thrd_id :out std_ulogic_vector(0 to 3); + xu_fu_ex3_eff_addr :out std_ulogic_vector(59 to 63); + + lsu_xu_ex3_ddir_par_err :out std_ulogic; + lsu_xu_ex4_n_lsu_ddmh_flush :out std_ulogic_vector(0 to 3); + + lsu_xu_is2_back_inv :out std_ulogic; + lsu_xu_is2_back_inv_addr :out std_ulogic_vector(64-real_data_add to 63-cl_size); + + rel_upd_dcarr_val :out std_ulogic; + + lsu_xu_ex4_cr_upd :out std_ulogic; + lsu_xu_ex5_cr_rslt :out std_ulogic; + lsu_xu_ex5_wren :out std_ulogic; + lsu_xu_rel_wren :out std_ulogic; + lsu_xu_rel_ta_gpr :out std_ulogic_vector(0 to 7); + lsu_xu_need_hole :out std_ulogic; + xu_fu_ex5_reload_val :out std_ulogic; + xu_fu_ex5_load_val :out std_ulogic_vector(0 to 3); + xu_fu_ex5_load_tag :out std_ulogic_vector(0 to 8); + + dcarr_up_way_addr :out std_ulogic_vector(0 to 2); + + lsu_xu_spr_xucr0_cslc_xuop :out std_ulogic; + lsu_xu_spr_xucr0_cslc_binv :out std_ulogic; + lsu_xu_spr_xucr0_clo :out std_ulogic; + lsu_xu_spr_xucr0_cul :out std_ulogic; + lsu_xu_spr_epsc_epr :out std_ulogic_vector(0 to 3); + lsu_xu_spr_epsc_egs :out std_ulogic_vector(0 to 3); + + ex4_load_op_hit :out std_ulogic; + ex4_store_hit :out std_ulogic; + ex4_axu_op_val :out std_ulogic; + spr_dvc1_act :out std_ulogic; + spr_dvc2_act :out std_ulogic; + spr_dvc1_dbg :out std_ulogic_vector(64-(2**regmode) to 63); + spr_dvc2_dbg :out std_ulogic_vector(64-(2**regmode) to 63); + + an_ac_req_ld_pop :in std_ulogic; + an_ac_req_st_pop :in std_ulogic; + an_ac_req_st_gather :in std_ulogic; + an_ac_req_st_pop_thrd :in std_ulogic_vector(0 to 2); + + an_ac_reld_data_val :in std_ulogic; + an_ac_reld_core_tag :in std_ulogic_vector(0 to 4); + an_ac_reld_qw :in std_ulogic_vector(57 to 59); + an_ac_reld_data :in std_ulogic_vector(0 to 127); + an_ac_reld_data_coming :in std_ulogic; + an_ac_reld_ditc :in std_ulogic; + an_ac_reld_crit_qw :in std_ulogic; + an_ac_reld_l1_dump :in std_ulogic; + + an_ac_reld_ecc_err :in std_ulogic; + an_ac_reld_ecc_err_ue :in std_ulogic; + + an_ac_back_inv :in std_ulogic; + an_ac_back_inv_addr :in std_ulogic_vector(64-real_data_add to 63); + an_ac_back_inv_target_bit1 :in std_ulogic; + an_ac_back_inv_target_bit4 :in std_ulogic; + an_ac_req_spare_ctrl_a1 :in std_ulogic_vector(0 to 3); + + an_ac_stcx_complete :in std_ulogic_vector(0 to 3); + xu_iu_stcx_complete : out std_ulogic_vector(0 to 3); + xu_iu_reld_core_tag_clone :out std_ulogic_vector(1 to 4); + xu_iu_reld_data_coming_clone :out std_ulogic; + xu_iu_reld_data_vld_clone :out std_ulogic; + xu_iu_reld_ditc_clone :out std_ulogic; + + lsu_reld_data_vld :out std_ulogic; + lsu_reld_core_tag :out std_ulogic_vector(3 to 4); + lsu_reld_qw :out std_ulogic_vector(58 to 59); + lsu_reld_ecc_err :out std_ulogic; + lsu_reld_ditc :out std_ulogic; + lsu_reld_data :out std_ulogic_vector(0 to 127); + + lsu_req_st_pop :out std_ulogic; + lsu_req_st_pop_thrd :out std_ulogic_vector(0 to 2); + + i_x_ra :in std_ulogic_vector(64-real_data_add to 59); + i_x_request :in std_ulogic; + i_x_wimge :in std_ulogic_vector(0 to 4); + i_x_thread :in std_ulogic_vector(0 to 3); + i_x_userdef :in std_ulogic_vector(0 to 3); + + mm_xu_lsu_req :in std_ulogic_vector(0 to 3); + mm_xu_lsu_ttype :in std_ulogic_vector(0 to 1); + mm_xu_lsu_wimge :in std_ulogic_vector(0 to 4); + mm_xu_lsu_u :in std_ulogic_vector(0 to 3); + mm_xu_lsu_addr :in std_ulogic_vector(64-real_data_add to 63); + mm_xu_lsu_lpid :in std_ulogic_vector(0 to 7); + mm_xu_lsu_lpidr :in std_ulogic_vector(0 to 7); + mm_xu_lsu_gs :in std_ulogic; + mm_xu_lsu_ind :in std_ulogic; + mm_xu_lsu_lbit :in std_ulogic; + xu_mm_lsu_token :out std_ulogic; + lsu_xu_ldq_barr_done :out std_ulogic_vector(0 to 3); + lsu_xu_barr_done :out std_ulogic_vector(0 to 3); + + bx_lsu_ob_pwr_tok :in std_ulogic; + bx_lsu_ob_req_val :in std_ulogic; + bx_lsu_ob_ditc_val :in std_ulogic; + bx_lsu_ob_thrd :in std_ulogic_vector(0 to 1); + bx_lsu_ob_qw :in std_ulogic_vector(58 to 59); + bx_lsu_ob_dest :in std_ulogic_vector(0 to 14); + bx_lsu_ob_data :in std_ulogic_vector(0 to 127); + bx_lsu_ob_addr :in std_ulogic_vector(64-real_data_add to 57); + lsu_bx_cmd_avail :out std_ulogic; + lsu_bx_cmd_sent :out std_ulogic; + lsu_bx_cmd_stall :out std_ulogic; + + ldq_rel_data_val_early :out std_ulogic; + ldq_rel_op_size :out std_ulogic_vector(0 to 5); + ldq_rel_addr :out std_ulogic_vector(64-(dc_size-3) to 58); + ldq_rel_data_val :out std_ulogic; + ldq_rel_rot_sel :out std_ulogic_vector(0 to 4); + ldq_rel_axu_val :out std_ulogic; + ldq_rel_ci :out std_ulogic; + ldq_rel_thrd_id :out std_ulogic_vector(0 to 3); + ldq_rel_le_mode :out std_ulogic; + ldq_rel_algebraic :out std_ulogic; + ldq_rel_256_data :out std_ulogic_vector(0 to 255); + + ldq_rel_dvc1_en :out std_ulogic; + ldq_rel_dvc2_en :out std_ulogic; + ldq_rel_beat_crit_qw :out std_ulogic; + ldq_rel_beat_crit_qw_block :out std_ulogic; + + xu_iu_ex4_loadmiss_qentry :out std_ulogic_vector(0 to lmq_entries-1); + xu_iu_ex4_loadmiss_target :out std_ulogic_vector(0 to 8); + xu_iu_ex4_loadmiss_target_type :out std_ulogic_vector(0 to 1); + xu_iu_ex4_loadmiss_tid :out std_ulogic_vector(0 to 3); + xu_iu_ex5_loadmiss_qentry :out std_ulogic_vector(0 to lmq_entries-1); + xu_iu_ex5_loadmiss_target :out std_ulogic_vector(0 to 8); + xu_iu_ex5_loadmiss_target_type :out std_ulogic_vector(0 to 1); + xu_iu_ex5_loadmiss_tid :out std_ulogic_vector(0 to 3); + xu_iu_complete_qentry :out std_ulogic_vector(0 to lmq_entries-1); + xu_iu_complete_tid :out std_ulogic_vector(0 to 3); + xu_iu_complete_target_type :out std_ulogic_vector(0 to 1); + + xu_iu_ex6_icbi_val :out std_ulogic_vector(0 to 3); + xu_iu_ex6_icbi_addr :out std_ulogic_vector(64-real_data_add to 57); + + xu_lsu_ex5_set_barr :in std_ulogic_vector(0 to 3); + xu_iu_larx_done_tid :out std_ulogic_vector(0 to 3); + xu_mm_lmq_stq_empty :out std_ulogic; + lsu_xu_quiesce :out std_ulogic_vector(0 to 3); + lsu_xu_dbell_val :out std_ulogic; + lsu_xu_dbell_type :out std_ulogic_vector(0 to 4); + lsu_xu_dbell_brdcast :out std_ulogic; + lsu_xu_dbell_lpid_match :out std_ulogic; + lsu_xu_dbell_pirtag :out std_ulogic_vector(50 to 63); + + ac_an_req_pwr_token :out std_ulogic; + ac_an_req :out std_ulogic; + ac_an_req_ra :out std_ulogic_vector(64-real_data_add to 63); + ac_an_req_ttype :out std_ulogic_vector(0 to 5); + ac_an_req_thread :out std_ulogic_vector(0 to 2); + ac_an_req_wimg_w :out std_ulogic; + ac_an_req_wimg_i :out std_ulogic; + ac_an_req_wimg_m :out std_ulogic; + ac_an_req_wimg_g :out std_ulogic; + ac_an_req_endian :out std_ulogic; + ac_an_req_user_defined :out std_ulogic_vector(0 to 3); + ac_an_req_spare_ctrl_a0 :out std_ulogic_vector(0 to 3); + ac_an_req_ld_core_tag :out std_ulogic_vector(0 to 4); + ac_an_req_ld_xfr_len :out std_ulogic_vector(0 to 2); + ac_an_st_byte_enbl :out std_ulogic_vector(0 to 15+(st_data_32B_mode*16)); + ac_an_st_data :out std_ulogic_vector(0 to 127+(st_data_32B_mode*128)); + ac_an_st_data_pwr_token :out std_ulogic; + + ac_an_reld_ditc_pop_int : in std_ulogic_vector(0 to 3); + ac_an_reld_ditc_pop_q : out std_ulogic_vector(0 to 3); + bx_ib_empty_int : in std_ulogic_vector(0 to 3); + bx_ib_empty_q : out std_ulogic_vector(0 to 3); + + xu_pc_err_dcachedir_parity :out std_ulogic; + xu_pc_err_dcachedir_multihit :out std_ulogic; + xu_pc_err_l2intrf_ecc :out std_ulogic; + xu_pc_err_l2intrf_ue :out std_ulogic; + xu_pc_err_invld_reld :out std_ulogic; + xu_pc_err_l2credit_overrun :out std_ulogic; + pc_xu_init_reset :in std_ulogic; + + pc_xu_event_bus_enable :in std_ulogic; + pc_xu_event_count_mode :in std_ulogic_vector(0 to 2); + pc_xu_lsu_event_mux_ctrls :in std_ulogic_vector(0 to 47); + pc_xu_cache_par_err_event :in std_ulogic; + xu_pc_lsu_event_data :out std_ulogic_vector(0 to 7); + + pc_xu_trace_bus_enable :in std_ulogic; + lsu_debug_mux_ctrls :in std_ulogic_vector(0 to 15); + trigger_data_in :in std_ulogic_vector(0 to 11); + debug_data_in :in std_ulogic_vector(0 to 87); + trigger_data_out :out std_ulogic_vector(0 to 11); + debug_data_out :out std_ulogic_vector(0 to 87); + lsu_xu_cmd_debug :out std_ulogic_vector(0 to 175); + + an_ac_lbist_ary_wrt_thru_dc :in std_ulogic; + pc_xu_abist_g8t_wenb :in std_ulogic; + pc_xu_abist_g8t1p_renb_0 :in std_ulogic; + pc_xu_abist_di_0 :in std_ulogic_vector(0 to 3); + pc_xu_abist_g8t_bw_1 :in std_ulogic; + pc_xu_abist_g8t_bw_0 :in std_ulogic; + pc_xu_abist_waddr_0 :in std_ulogic_vector(5 to 9); + pc_xu_abist_raddr_0 :in std_ulogic_vector(5 to 9); + pc_xu_abist_ena_dc :in std_ulogic; + pc_xu_abist_wl32_comp_ena :in std_ulogic; + pc_xu_abist_raw_dc_b :in std_ulogic; + pc_xu_abist_g8t_dcomp :in std_ulogic_vector(0 to 3); + pc_xu_bo_unload :in std_ulogic; + pc_xu_bo_repair :in std_ulogic; + pc_xu_bo_reset :in std_ulogic; + pc_xu_bo_shdata :in std_ulogic; + pc_xu_bo_select :in std_ulogic_vector(1 to 4); + xu_pc_bo_fail :out std_ulogic_vector(1 to 4); + xu_pc_bo_diagout :out std_ulogic_vector(1 to 4); + + vcs :inout power_logic; + vdd :inout power_logic; + gnd :inout power_logic; + nclk :in clk_logic; + an_ac_grffence_en_dc :in std_ulogic; + an_ac_coreid :in std_ulogic_vector(6 to 7); + pc_xu_ccflush_dc :in std_ulogic; + an_ac_scan_dis_dc_b :in std_ulogic; + an_ac_atpg_en_dc :in std_ulogic; + an_ac_scan_diag_dc :in std_ulogic; + an_ac_lbist_en_dc :in std_ulogic; + clkoff_dc_b :in std_ulogic; + sg_2 :in std_ulogic_vector(2 to 3); + fce_2 :in std_ulogic; + func_sl_thold_2 :in std_ulogic_vector(2 to 3); + func_nsl_thold_2 :in std_ulogic; + func_slp_sl_thold_2 :in std_ulogic; + func_slp_nsl_thold_2 :in std_ulogic; + cfg_slp_sl_thold_2 :in std_ulogic; + regf_slp_sl_thold_2 :in std_ulogic; + abst_slp_sl_thold_2 :in std_ulogic; + time_sl_thold_2 :in std_ulogic; + ary_slp_nsl_thold_2 :in std_ulogic; + repr_sl_thold_2 :in std_ulogic; + bolt_sl_thold_2 :in std_ulogic; + bo_enable_2 :in std_ulogic; + d_mode_dc :in std_ulogic; + delay_lclkr_dc :in std_ulogic_vector(5 to 9); + mpw1_dc_b :in std_ulogic_vector(5 to 9); + mpw2_dc_b :in std_ulogic; + g8t_clkoff_dc_b :in std_ulogic; + g8t_d_mode_dc :in std_ulogic; + g8t_delay_lclkr_dc :in std_ulogic_vector(0 to 4); + g8t_mpw1_dc_b :in std_ulogic_vector(0 to 4); + g8t_mpw2_dc_b :in std_ulogic; + cam_clkoff_dc_b :in std_ulogic; + cam_d_mode_dc :in std_ulogic; + cam_act_dis_dc :in std_ulogic; + cam_delay_lclkr_dc :in std_ulogic_vector(0 to 4); + cam_mpw1_dc_b :in std_ulogic_vector(0 to 4); + cam_mpw2_dc_b :in std_ulogic; + bcfg_scan_in :in std_ulogic; + bcfg_scan_out :out std_ulogic; + ccfg_scan_in :in std_ulogic; + ccfg_scan_out :out std_ulogic; + dcfg_scan_in :in std_ulogic; + dcfg_scan_out :out std_ulogic; + regf_scan_in :in std_ulogic_vector(0 to 6); + regf_scan_out :out std_ulogic_vector(0 to 6); + abst_scan_in :in std_ulogic; + abst_scan_out :out std_ulogic; + time_scan_in :in std_ulogic; + time_scan_out :out std_ulogic; + repr_scan_in :in std_ulogic; + repr_scan_out :out std_ulogic; + func_scan_in :in std_ulogic_vector(41 to 49); + func_scan_out :out std_ulogic_vector(41 to 49) +); +-- synopsys translate_off +-- synopsys translate_on +end xuq_lsu_cmd; +architecture xuq_lsu_cmd of xuq_lsu_cmd is + +constant uprTagBit :natural := 64-real_data_add; +constant lwrTagBit :natural := 63-(dc_size-3); +constant tagSize :natural := lwrTagBit-uprTagBit+1; +constant parExtCalc :natural := 8 - (tagSize mod 8); +constant parBits :natural := (tagSize+parExtCalc) / 8; +constant wayDataSize :natural := tagSize+parBits; + +signal ex3_req_thrd_id :std_ulogic_vector(0 to 3); +signal ex3_l_s_q_val :std_ulogic; +signal ex3_drop_ld_req :std_ulogic; +signal ex3_drop_touch :std_ulogic; +signal ex3_cache_inh :std_ulogic; +signal ex3_load_instr :std_ulogic; +signal ex3_store_instr :std_ulogic; +signal ex3_cache_acc :std_ulogic; +signal ex2_p_addr_lwr :std_ulogic_vector(52 to 57); +signal ex3_p_addr_lwr :std_ulogic_vector(58 to 63); +signal ex3_opsize :std_ulogic_vector(0 to 5); +signal ex3_target_gpr :std_ulogic_vector(0 to 8); +signal ex3_axu_op_val :std_ulogic; +signal ex3_larx_instr :std_ulogic; +signal ex3_mutex_hint :std_ulogic; +signal ex3_stx_instr :std_ulogic; +signal ex3_dcbt_instr :std_ulogic; +signal ex3_dcbf_instr :std_ulogic; +signal ex3_dcbtst_instr :std_ulogic; +signal ex3_dcbst_instr :std_ulogic; +signal ex3_dcbz_instr :std_ulogic; +signal ex3_dcbi_instr :std_ulogic; +signal ex3_icbi_instr :std_ulogic; +signal ex3_icswx_instr :std_ulogic; +signal ex3_icswx_dot :std_ulogic; +signal ex3_icswx_epid :std_ulogic; +signal ex3_sync_instr :std_ulogic; +signal ex3_mtspr_trace :std_ulogic; +signal ex3_byte_en :std_ulogic_vector(0 to 31); +signal ex3_l_fld :std_ulogic_vector(0 to 1); +signal ex3_mbar_instr :std_ulogic; +signal ex3_msgsnd_instr :std_ulogic; +signal ex3_dci_instr :std_ulogic; +signal ex3_ici_instr :std_ulogic; +signal ex3_flush_stg :std_ulogic; +signal ex4_flush_stg :std_ulogic; +signal ex3_algebraic_op :std_ulogic; +signal ex3_dcbtls_instr :std_ulogic; +signal ex3_dcbtstls_instr :std_ulogic; +signal ex3_dcblc_instr :std_ulogic; +signal ex3_icblc_instr :std_ulogic; +signal ex3_icbt_instr :std_ulogic; +signal ex3_icbtls_instr :std_ulogic; +signal ex3_tlbsync_instr :std_ulogic; +signal ex3_local_dcbf :std_ulogic; +signal ex4_drop_rel :std_ulogic; +signal ex3_load_l1hit :std_ulogic; +signal ex3_rotate_sel :std_ulogic_vector(0 to 4); +signal ex3_lock_en :std_ulogic; +signal ex3_th_fld_l2 :std_ulogic; +signal cmp_flush :std_ulogic; +signal cmp_ldq_fnd_b :std_ulogic; +signal cmp_ldq_fnd :std_ulogic; +signal ex1_src0_vld :std_ulogic; +signal ex1_src0_reg :std_ulogic_vector(0 to 7); +signal ex1_src1_vld :std_ulogic; +signal ex1_src1_reg :std_ulogic_vector(0 to 7); +signal ex1_targ_vld :std_ulogic; +signal ex1_targ_reg :std_ulogic_vector(0 to 7); +signal ex1_check_watch :std_ulogic_vector(0 to 3); +signal ex2_lm_dep_hit :std_ulogic; +signal ldq_rel1_val :std_ulogic; +signal ldq_rel1_early_v :std_ulogic; +signal ldq_rel_mid_val :std_ulogic; +signal ldq_rel_retry_val :std_ulogic; +signal ldq_rel3_val :std_ulogic; +signal ldq_rel3_early_v :std_ulogic; +signal ldq_rel_tag :std_ulogic_vector(1 to 3); +signal ldq_rel_tag_early :std_ulogic_vector(1 to 3); +signal ldq_rel_set_val :std_ulogic; +signal ldq_rel_ecc_err :std_ulogic; +signal ldq_rel_classid :std_ulogic_vector(0 to 1); +signal ldq_rel_lock_en :std_ulogic; +signal ldq_rel_watch_en :std_ulogic; +signal rel_ldq_thrd_id :std_ulogic_vector(0 to 3); +signal ldq_rel_ta_gpr :std_ulogic_vector(0 to 8); +signal ldq_rel_addr_early :std_ulogic_vector(64-real_data_add to 63-cl_size); +signal ldq_rel_back_invalidated :std_ulogic; +signal ldq_recirc_rel_val :std_ulogic; +signal ldq_rel_l1dump_cslc :std_ulogic; +signal ldq_rel3_l1dump_val :std_ulogic; +signal rel_ldq_ci :std_ulogic; +signal rel_ldq_upd_gpr :std_ulogic; +signal rel_ldq_addr :std_ulogic_vector(64-real_data_add to 58); +signal rel_ldq_axu_val :std_ulogic; +signal is2_l2_inv_val :std_ulogic; +signal is2_l2_inv_p_addr :std_ulogic_vector(64-real_data_add to 63-cl_size); +signal l2_data_ecc_err_ue :std_ulogic_vector(0 to 3); +signal gpr_ecc_err_flush_tid :std_ulogic_vector(0 to 3); +signal dcpar_err_flush :std_ulogic; +signal ex4_dir_perr_det :std_ulogic_vector(0 to 0); +signal ex4_dir_multihit_det :std_ulogic_vector(0 to 0); +signal ex4_n_lsu_ddmh_flush :std_ulogic_vector(0 to 3); +signal dcachedir_parity :std_ulogic_vector(0 to 0); +signal dcachedir_multihit :std_ulogic_vector(0 to 0); +signal ex3_watch_en :std_ulogic; +signal ex3_ld_queue_full :std_ulogic; +signal ex3_stq_flush :std_ulogic; +signal ex3_ig_flush :std_ulogic; +signal ex3_cClass_collision :std_ulogic; +signal ex3_cClass_collision_b :std_ulogic; +signal derat_xu_ex2_vf :std_ulogic; +signal derat_xu_ex2_miss :std_ulogic_vector(0 to 3); +signal derat_xu_ex2_attr :std_ulogic_vector(0 to 5); +signal derat_xu_ex4_data :std_ulogic_vector(64-(2**REGMODE) to 63); +signal derat_iu_barrier_done :std_ulogic_vector(0 to 3); +signal derat_fir_par_err :std_ulogic_vector(0 to 3); +signal derat_fir_multihit :std_ulogic_vector(0 to 3); +signal xu_derat_epsc_wr :std_ulogic_vector(0 to 3); +signal xu_derat_eplc_wr :std_ulogic_vector(0 to 3); +signal xu_derat_eplc0_epr :std_ulogic; +signal xu_derat_eplc0_eas :std_ulogic; +signal xu_derat_eplc0_egs :std_ulogic; +signal xu_derat_eplc0_elpid :std_ulogic_vector(40 to 47); +signal xu_derat_eplc0_epid :std_ulogic_vector(50 to 63); +signal xu_derat_eplc1_epr :std_ulogic; +signal xu_derat_eplc1_eas :std_ulogic; +signal xu_derat_eplc1_egs :std_ulogic; +signal xu_derat_eplc1_elpid :std_ulogic_vector(40 to 47); +signal xu_derat_eplc1_epid :std_ulogic_vector(50 to 63); +signal xu_derat_eplc2_epr :std_ulogic; +signal xu_derat_eplc2_eas :std_ulogic; +signal xu_derat_eplc2_egs :std_ulogic; +signal xu_derat_eplc2_elpid :std_ulogic_vector(40 to 47); +signal xu_derat_eplc2_epid :std_ulogic_vector(50 to 63); +signal xu_derat_eplc3_epr :std_ulogic; +signal xu_derat_eplc3_eas :std_ulogic; +signal xu_derat_eplc3_egs :std_ulogic; +signal xu_derat_eplc3_elpid :std_ulogic_vector(40 to 47); +signal xu_derat_eplc3_epid :std_ulogic_vector(50 to 63); +signal xu_derat_epsc0_epr :std_ulogic; +signal xu_derat_epsc0_eas :std_ulogic; +signal xu_derat_epsc0_egs :std_ulogic; +signal xu_derat_epsc0_elpid :std_ulogic_vector(40 to 47); +signal xu_derat_epsc0_epid :std_ulogic_vector(50 to 63); +signal xu_derat_epsc1_epr :std_ulogic; +signal xu_derat_epsc1_eas :std_ulogic; +signal xu_derat_epsc1_egs :std_ulogic; +signal xu_derat_epsc1_elpid :std_ulogic_vector(40 to 47); +signal xu_derat_epsc1_epid :std_ulogic_vector(50 to 63); +signal xu_derat_epsc2_epr :std_ulogic; +signal xu_derat_epsc2_eas :std_ulogic; +signal xu_derat_epsc2_egs :std_ulogic; +signal xu_derat_epsc2_elpid :std_ulogic_vector(40 to 47); +signal xu_derat_epsc2_epid :std_ulogic_vector(50 to 63); +signal xu_derat_epsc3_epr :std_ulogic; +signal xu_derat_epsc3_eas :std_ulogic; +signal xu_derat_epsc3_egs :std_ulogic; +signal xu_derat_epsc3_elpid :std_ulogic_vector(40 to 47); +signal xu_derat_epsc3_epid :std_ulogic_vector(50 to 63); +signal derat_xu_ex2_rpn :std_ulogic_vector(22 to 51); +signal derat_xu_ex2_wimge :std_ulogic_vector(0 to 4); +signal derat_xu_ex2_u :std_ulogic_vector(0 to 3); +signal derat_xu_ex2_wlc :std_ulogic_vector(0 to 1); +signal xu_derat_ex1_epn_arr :std_ulogic_vector(64-(2**regmode) to 51); +signal xu_derat_ex1_epn_nonarr :std_ulogic_vector(64-(2**regmode) to 51); +signal snoop_addr :std_ulogic_vector(64-(2**regmode) to 51); +signal snoop_addr_sel :std_ulogic; +signal lsu_perf_events :std_ulogic_vector(0 to 46); +signal ex1_stg_act :std_ulogic; +signal ex2_stg_act :std_ulogic; +signal ex3_stg_act :std_ulogic; +signal ex4_stg_act :std_ulogic; +signal binv1_stg_act :std_ulogic; +signal binv2_stg_act :std_ulogic; +signal binv2_ex2_stg_act :std_ulogic; +signal lsu_xu_sync_barr_done :std_ulogic_vector(0 to 3); +signal bcfg_scan_out_int :std_ulogic; +signal ccfg_scan_out_int :std_ulogic; +signal dcfg_scan_out_int :std_ulogic; +signal abist_siv :std_ulogic_vector(0 to 23); +signal abist_sov :std_ulogic_vector(0 to 23); +signal rel_data_val :std_ulogic; +signal rel_data_val_early :std_ulogic; +signal dir_arr_rd_addr_01 :std_ulogic_vector(64-(dc_size-3) to 63-cl_size); +signal dir_arr_rd_addr_23 :std_ulogic_vector(64-(dc_size-3) to 63-cl_size); +signal dir_arr_rd_addr_45 :std_ulogic_vector(64-(dc_size-3) to 63-cl_size); +signal dir_arr_rd_addr_67 :std_ulogic_vector(64-(dc_size-3) to 63-cl_size); +signal dir_arr_rd_data :std_ulogic_vector(0 to 8*wayDataSize-1); +signal dir_wr_enable :std_ulogic_vector(0 to 3); +signal dir_wr_way :std_ulogic_vector(0 to 7); +signal dir_arr_wr_addr :std_ulogic_vector(64-(dc_size-3) to 63-cl_size); +signal dir_arr_wr_data :std_ulogic_vector(64-real_data_add to 64-real_data_add+wayDataSize-1); +signal abst_slp_sl_thold_1 :std_ulogic; +signal time_sl_thold_1 :std_ulogic; +signal ary_slp_nsl_thold_1 :std_ulogic; +signal repr_sl_thold_1 :std_ulogic; +signal regf_slp_sl_thold_1 :std_ulogic; +signal func_slp_nsl_thold_1 :std_ulogic; +signal abst_slp_sl_thold_0 :std_ulogic; +signal time_sl_thold_0 :std_ulogic; +signal ary_slp_nsl_thold_0 :std_ulogic; +signal repr_sl_thold_0 :std_ulogic; +signal regf_slp_sl_thold_0 :std_ulogic; +signal func_slp_nsl_thold_0 :std_ulogic; +signal abst_slp_sl_thold_0_b :std_ulogic; +signal abst_slp_sl_force :std_ulogic; +signal abst_scan_in_q :std_ulogic; +signal abst_scan_out_int :std_ulogic; +signal abst_scan_out_q :std_ulogic; +signal time_scan_in_q :std_ulogic; +signal time_scan_out_int :std_ulogic_vector(0 to 1); +signal time_scan_out_q :std_ulogic; +signal repr_scan_in_q :std_ulogic; +signal repr_scan_out_int :std_ulogic; +signal repr_scan_out_q :std_ulogic; +signal func_scan_in_q :std_ulogic_vector(41 to 49); +signal func_scan_out_int :std_ulogic_vector(41 to 49); +signal func_scan_out_q :std_ulogic_vector(41 to 49); +signal regf_scan_in_q :std_ulogic_vector(0 to 6); +signal regf_scan_out_int :std_ulogic_vector(0 to 6); +signal regf_scan_out_q :std_ulogic_vector(0 to 6); +signal derat_scan_out :std_ulogic_vector(0 to 1); +signal dir_scan_out :std_ulogic_vector(0 to 1); +signal cmp_scan_out :std_ulogic; +signal l2cmdq_scan_out :std_ulogic; +signal tidn :std_ulogic; +signal func_slp_sl_thold_1 :std_ulogic; +signal func_sl_thold_1 :std_ulogic; +signal func_nsl_thold_1 :std_ulogic; +signal cfg_slp_sl_thold_1 :std_ulogic; +signal sg_1 :std_ulogic; +signal fce_1 :std_ulogic; +signal bolt_sl_thold_1 :std_ulogic; +signal func_slp_sl_thold_0 :std_ulogic; +signal func_sl_thold_0 :std_ulogic; +signal func_nsl_thold_0 :std_ulogic; +signal cfg_slp_sl_thold_0 :std_ulogic; +signal sg_0 :std_ulogic; +signal fce_0 :std_ulogic; +signal bolt_sl_thold_0 :std_ulogic; +signal func_sl_force :std_ulogic; +signal func_sl_thold_0_b :std_ulogic; +signal func_nsl_force :std_ulogic; +signal func_nsl_thold_0_b :std_ulogic; +signal cfg_slp_sl_force :std_ulogic; +signal cfg_slp_sl_thold_0_b :std_ulogic; +signal func_slp_sl_force :std_ulogic; +signal func_slp_sl_thold_0_b :std_ulogic; +signal func_slp_nsl_force :std_ulogic; +signal func_slp_nsl_thold_0_b :std_ulogic; +signal pc_xu_abist_g8t_wenb_q :std_ulogic; +signal pc_xu_abist_g8t1p_renb_0_q :std_ulogic; +signal pc_xu_abist_di_0_q :std_ulogic_vector(0 to 3); +signal pc_xu_abist_g8t_bw_1_q :std_ulogic; +signal pc_xu_abist_g8t_bw_0_q :std_ulogic; +signal pc_xu_abist_waddr_0_q :std_ulogic_vector(0 to 4); +signal pc_xu_abist_raddr_0_q :std_ulogic_vector(0 to 4); +signal pc_xu_abist_wl32_comp_ena_q :std_ulogic; +signal pc_xu_abist_g8t_dcomp_q :std_ulogic_vector(0 to 3); +signal slat_force :std_ulogic; +signal abst_slat_thold_b :std_ulogic; +signal abst_slat_d2clk :std_ulogic; +signal abst_slat_lclk :clk_logic; +signal time_slat_thold_b :std_ulogic; +signal time_slat_d2clk :std_ulogic; +signal time_slat_lclk :clk_logic; +signal repr_slat_thold_b :std_ulogic; +signal repr_slat_d2clk :std_ulogic; +signal repr_slat_lclk :clk_logic; +signal func_slat_thold_b :std_ulogic; +signal func_slat_d2clk :std_ulogic; +signal func_slat_lclk :clk_logic; +signal regf_slat_thold_b :std_ulogic; +signal regf_slat_d2clk :std_ulogic; +signal regf_slat_lclk :clk_logic; +signal lmq_pe_recov_state :std_ulogic; +signal lmq_dbg_dcache_pe :std_ulogic_vector(1 to 60); +signal lmq_dbg_l2req :std_ulogic_vector(0 to 212); +signal lmq_dbg_rel :std_ulogic_vector(0 to 140); +signal lmq_dbg_binv :std_ulogic_vector(0 to 44); +signal lmq_dbg_pops :std_ulogic_vector(0 to 5); +signal lmq_dbg_grp0 :std_ulogic_vector(0 to 81); +signal lmq_dbg_grp1 :std_ulogic_vector(0 to 81); +signal lmq_dbg_grp2 :std_ulogic_vector(0 to 87); +signal lmq_dbg_grp3 :std_ulogic_vector(0 to 87); +signal lmq_dbg_grp4 :std_ulogic_vector(0 to 87); +signal lmq_dbg_grp5 :std_ulogic_vector(0 to 87); +signal lmq_dbg_grp6 :std_ulogic_vector(0 to 87); + +signal spr_xucr0_cls :std_ulogic; +signal ex3_data_swap_int :std_ulogic; +signal ex3_blkable_touch :std_ulogic; +signal ex7_targ_match :std_ulogic; +signal ex8_targ_match :std_ulogic; +signal ex4_ld_entry :std_ulogic_vector(0 to 67); +signal ex2_wayA_tag :std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); +signal ex2_wayB_tag :std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); +signal ex2_wayC_tag :std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); +signal ex2_wayD_tag :std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); +signal ex2_wayE_tag :std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); +signal ex2_wayF_tag :std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); +signal ex2_wayG_tag :std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); +signal ex2_wayH_tag :std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); +signal ex3_cClass_upd_way_a :std_ulogic; +signal ex3_cClass_upd_way_b :std_ulogic; +signal ex3_cClass_upd_way_c :std_ulogic; +signal ex3_cClass_upd_way_d :std_ulogic; +signal ex3_cClass_upd_way_e :std_ulogic; +signal ex3_cClass_upd_way_f :std_ulogic; +signal ex3_cClass_upd_way_g :std_ulogic; +signal ex3_cClass_upd_way_h :std_ulogic; +signal ex3_way_cmp_a :std_ulogic; +signal ex3_way_cmp_b :std_ulogic; +signal ex3_way_cmp_c :std_ulogic; +signal ex3_way_cmp_d :std_ulogic; +signal ex3_way_cmp_e :std_ulogic; +signal ex3_way_cmp_f :std_ulogic; +signal ex3_way_cmp_g :std_ulogic; +signal ex3_way_cmp_h :std_ulogic; +signal cmp_lmq_entry_act :std_ulogic; +signal cmp_ldq_comp_val :std_ulogic_vector(0 to 7); +signal cmp_ldq_match :std_ulogic_vector(0 to 7); +signal cmp_l_q_wrt_en :std_ulogic_vector(0 to 7); +signal cmp_ld_ex7_recov :std_ulogic; +signal cmp_ex3_p_addr_o :std_ulogic_vector(22 to 57); +signal cmp_ex7_ld_recov_addr :std_ulogic_vector(64-real_data_add to 57); +signal cmp_ex4_loadmiss_qentry :std_ulogic_vector(0 to 7); +signal cmp_ex4_ld_addr :std_ulogic_vector(64-real_data_add to 57); +signal cmp_l_q_rd_en :std_ulogic_vector(0 to 7); +signal cmp_l_miss_entry_addr :std_ulogic_vector(64-real_data_add to 57); +signal cmp_rel_tag_1hot :std_ulogic_vector(0 to 7); +signal cmp_rel_addr :std_ulogic_vector(64-real_data_add to 57); +signal cmp_back_inv_addr :std_ulogic_vector(64-real_data_add to 57); +signal cmp_back_inv_cmp_val :std_ulogic_vector(0 to 7); +signal cmp_back_inv_addr_hit :std_ulogic_vector(0 to 7); +signal cmp_s_m_queue0_addr :std_ulogic_vector(64-real_data_add to 57); +signal cmp_st_entry0_val :std_ulogic ; +signal cmp_ex3addr_hit_stq :std_ulogic ; +signal cmp_ex4_st_entry_addr :std_ulogic_vector(64-real_data_add to 57); +signal cmp_ex4_st_val :std_ulogic ; +signal cmp_ex3addr_hit_ex4st :std_ulogic ; +signal dir_rd_stg_act :std_ulogic; +signal xu_derat_rf1_binv_val :std_ulogic; +signal derat_xu_ex3_rpn :std_ulogic_vector(64-real_data_add to 51); +signal derat_xu_ex3_wimge :std_ulogic_vector(0 to 4); +signal derat_xu_ex3_u :std_ulogic_vector(0 to 3); +signal derat_xu_ex3_wlc :std_ulogic_vector(0 to 1); +signal derat_xu_ex3_attr :std_ulogic_vector(0 to 5); +signal derat_xu_ex3_vf :std_ulogic; +signal derat_xu_ex3_noop_touch :std_ulogic_vector(0 to 3); +signal dir_arr_rd_is2_val :std_ulogic; +signal dir_arr_rd_congr_cl :std_ulogic_vector(0 to 4); +signal is2_back_inv_addr :std_ulogic_vector(64-real_data_add to 63-cl_size); +signal ex3_wayA_tag :std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); +signal ex3_wayB_tag :std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); +signal ex3_wayC_tag :std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); +signal ex3_wayD_tag :std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); +signal ex3_wayE_tag :std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); +signal ex3_wayF_tag :std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); +signal ex3_wayG_tag :std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); +signal ex3_wayH_tag :std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); +signal dc_fgen_dbg_data :std_ulogic_vector(0 to 1); +signal dc_cntrl_dbg_data :std_ulogic_vector(0 to 66); +signal dc_val_dbg_data :std_ulogic_vector(0 to 293); +signal dc_lru_dbg_data :std_ulogic_vector(0 to 81); +signal dc_dir_dbg_data :std_ulogic_vector(0 to 35); +signal dir_arr_dbg_data :std_ulogic_vector(0 to 60); +signal pe_recov_begin :std_ulogic; +signal derat_xu_debug_group0 :std_ulogic_vector(0 to 87); +signal derat_xu_debug_group1 :std_ulogic_vector(0 to 87); + +begin + +tidn <= '0'; + +lsuderat : entity work.xuq_lsu_derat(xuq_lsu_derat) +generic map( expand_type => expand_type, + rs_data_width => (2**regmode), + data_out_width => (2**regmode), + epn_width => (2**regmode)-12, + bcfg_epn_0to15 => bcfg_epn_0to15, + bcfg_epn_16to31 => bcfg_epn_16to31, + bcfg_epn_32to47 => bcfg_epn_32to47, + bcfg_epn_48to51 => bcfg_epn_48to51, + bcfg_rpn_22to31 => bcfg_rpn_22to31, + bcfg_rpn_32to47 => bcfg_rpn_32to47, + bcfg_rpn_48to51 => bcfg_rpn_48to51) +port map( + vdd => vdd, + gnd => gnd, + vcs => vcs, + nclk => nclk, + pc_xu_init_reset => pc_xu_init_reset, + pc_xu_ccflush_dc => pc_xu_ccflush_dc, + tc_scan_dis_dc_b => an_ac_scan_dis_dc_b, + tc_scan_diag_dc => an_ac_scan_diag_dc, + tc_lbist_en_dc => an_ac_lbist_en_dc, + an_ac_atpg_en_dc => an_ac_atpg_en_dc, + an_ac_grffence_en_dc => an_ac_grffence_en_dc, + + lcb_d_mode_dc => d_mode_dc, + lcb_clkoff_dc_b => clkoff_dc_b, + lcb_act_dis_dc => tidn, + lcb_mpw1_dc_b => mpw1_dc_b, + lcb_mpw2_dc_b => mpw2_dc_b, + lcb_delay_lclkr_dc => delay_lclkr_dc, + + pc_func_sl_thold_2 => func_sl_thold_2(2), + pc_func_slp_sl_thold_2 => func_slp_sl_thold_2, + pc_func_slp_nsl_thold_2 => func_slp_nsl_thold_2, + pc_cfg_slp_sl_thold_2 => cfg_slp_sl_thold_2, + pc_regf_slp_sl_thold_2 => regf_slp_sl_thold_2, + pc_time_sl_thold_2 => time_sl_thold_2, + pc_sg_2 => sg_2(2), + pc_fce_2 => fce_2, + + cam_clkoff_dc_b => cam_clkoff_dc_b, + cam_act_dis_dc => cam_act_dis_dc, + cam_d_mode_dc => cam_d_mode_dc, + cam_delay_lclkr_dc => cam_delay_lclkr_dc, + cam_mpw1_dc_b => cam_mpw1_dc_b, + cam_mpw2_dc_b => cam_mpw2_dc_b, + + + ac_func_scan_in => func_scan_in_q(41 to 42), + ac_func_scan_out => derat_scan_out, + ac_ccfg_scan_in => ccfg_scan_in, + ac_ccfg_scan_out => ccfg_scan_out_int, + time_scan_in => time_scan_out_int(0), + time_scan_out => time_scan_out_int(1), + + regf_scan_in => regf_scan_in_q, + regf_scan_out => regf_scan_out_int, + + spr_xucr4_mmu_mchk => spr_xucr4_mmu_mchk, + spr_xucr0_clkg_ctl_b1 => spr_xucr0_clkg_ctl_b1, + xu_derat_rf0_val => xu_lsu_rf0_derat_val, + xu_derat_rf1_act => xu_lsu_rf1_derat_act, + xu_derat_rf1_ra_eq_ea => xu_lsu_rf1_derat_ra_eq_ea, + xu_derat_rf1_is_load => xu_lsu_rf1_derat_is_load, + xu_derat_rf1_is_store => xu_lsu_rf1_derat_is_store, + xu_derat_rf1_is_eratre => xu_lsu_rf1_is_eratre, + xu_derat_rf1_is_eratwe => xu_lsu_rf1_is_eratwe, + xu_derat_rf1_is_eratsx => xu_lsu_rf1_is_eratsx, + xu_derat_rf1_is_eratilx => xu_lsu_rf1_is_eratilx, + xu_derat_ex1_is_isync => xu_lsu_ex1_is_isync, + xu_derat_ex1_is_csync => xu_lsu_ex1_is_csync, + xu_derat_rf1_is_touch => xu_lsu_rf1_is_touch, + xu_derat_rf1_icbtls_instr => xu_lsu_rf1_icbtls_instr, + xu_derat_rf1_icblc_instr => xu_lsu_rf1_icblc_instr, + xu_derat_rf0_is_extload => xu_lsu_rf0_derat_is_extload, + xu_derat_rf0_is_extstore => xu_lsu_rf0_derat_is_extstore, + xu_derat_rf1_ws => xu_lsu_rf1_ws, + xu_derat_rf1_t => xu_lsu_rf1_t, + xu_derat_rf1_binv_val => xu_derat_rf1_binv_val, + xu_derat_ex1_rs_is => xu_lsu_ex1_rs_is, + xu_derat_ex1_ra_entry => xu_lsu_ex1_ra_entry, + xu_derat_ex1_epn_arr => xu_derat_ex1_epn_arr, + xu_derat_ex1_epn_nonarr => xu_derat_ex1_epn_nonarr, + snoop_addr => snoop_addr, + snoop_addr_sel => snoop_addr_sel, + xu_derat_rf0_n_flush => xu_lsu_rf0_flush, + xu_derat_rf1_n_flush => xu_lsu_rf1_flush, + xu_derat_ex1_n_flush => xu_lsu_ex1_flush, + xu_derat_ex2_n_flush => xu_lsu_ex2_flush, + xu_derat_ex3_n_flush => xu_lsu_ex3_flush, + xu_derat_ex4_n_flush => xu_lsu_ex4_flush, + xu_derat_ex5_n_flush => xu_lsu_ex5_flush, + xu_derat_ex4_rs_data => xu_lsu_ex4_rs_data, + xu_derat_msr_hv => xu_lsu_msr_gs, + xu_derat_msr_pr => xu_lsu_msr_pr, + xu_derat_msr_ds => xu_lsu_msr_ds, + xu_derat_msr_cm => xu_lsu_msr_cm, + xu_derat_hid_mmu_mode => xu_lsu_hid_mmu_mode, + xu_derat_spr_ccr2_dfrat => xu_lsu_spr_ccr2_dfrat, + xu_derat_spr_ccr2_dfratsc => xu_lsu_spr_ccr2_dfratsc, + + derat_xu_ex2_miss => derat_xu_ex2_miss, + derat_xu_ex2_rpn => derat_xu_ex2_rpn, + derat_xu_ex2_wimge => derat_xu_ex2_wimge, + derat_xu_ex2_u => derat_xu_ex2_u, + derat_xu_ex2_wlc => derat_xu_ex2_wlc, + derat_xu_ex2_attr => derat_xu_ex2_attr, + derat_xu_ex2_vf => derat_xu_ex2_vf, + + derat_xu_ex3_rpn => derat_xu_ex3_rpn, + derat_xu_ex3_wimge => derat_xu_ex3_wimge, + derat_xu_ex3_u => derat_xu_ex3_u, + derat_xu_ex3_wlc => derat_xu_ex3_wlc, + derat_xu_ex3_attr => derat_xu_ex3_attr, + derat_xu_ex3_vf => derat_xu_ex3_vf, + derat_xu_ex3_miss => derat_xu_ex3_miss, + derat_xu_ex3_dsi => derat_xu_ex3_dsi, + derat_xu_ex3_multihit_err => lsu_xu_ex3_derat_multihit_err, + derat_xu_ex3_noop_touch => derat_xu_ex3_noop_touch, + derat_xu_ex3_par_err => lsu_xu_ex3_derat_par_err, + + derat_xu_ex3_n_flush_req => derat_xu_ex3_n_flush_req, + derat_xu_ex4_data => derat_xu_ex4_data, + derat_xu_ex4_par_err => lsu_xu_ex4_derat_par_err, + derat_iu_barrier_done => derat_iu_barrier_done, + derat_fir_par_err => derat_fir_par_err, + derat_fir_multihit => derat_fir_multihit, + + xu_derat_epsc_wr => xu_derat_epsc_wr, + xu_derat_eplc_wr => xu_derat_eplc_wr, + xu_derat_eplc0_epr => xu_derat_eplc0_epr, + xu_derat_eplc0_eas => xu_derat_eplc0_eas, + xu_derat_eplc0_egs => xu_derat_eplc0_egs, + xu_derat_eplc0_elpid => xu_derat_eplc0_elpid, + xu_derat_eplc0_epid => xu_derat_eplc0_epid, + xu_derat_eplc1_epr => xu_derat_eplc1_epr, + xu_derat_eplc1_eas => xu_derat_eplc1_eas, + xu_derat_eplc1_egs => xu_derat_eplc1_egs, + xu_derat_eplc1_elpid => xu_derat_eplc1_elpid, + xu_derat_eplc1_epid => xu_derat_eplc1_epid, + xu_derat_eplc2_epr => xu_derat_eplc2_epr, + xu_derat_eplc2_eas => xu_derat_eplc2_eas, + xu_derat_eplc2_egs => xu_derat_eplc2_egs, + xu_derat_eplc2_elpid => xu_derat_eplc2_elpid, + xu_derat_eplc2_epid => xu_derat_eplc2_epid, + xu_derat_eplc3_epr => xu_derat_eplc3_epr, + xu_derat_eplc3_eas => xu_derat_eplc3_eas, + xu_derat_eplc3_egs => xu_derat_eplc3_egs, + xu_derat_eplc3_elpid => xu_derat_eplc3_elpid, + xu_derat_eplc3_epid => xu_derat_eplc3_epid, + xu_derat_epsc0_epr => xu_derat_epsc0_epr, + xu_derat_epsc0_eas => xu_derat_epsc0_eas, + xu_derat_epsc0_egs => xu_derat_epsc0_egs, + xu_derat_epsc0_elpid => xu_derat_epsc0_elpid, + xu_derat_epsc0_epid => xu_derat_epsc0_epid, + xu_derat_epsc1_epr => xu_derat_epsc1_epr, + xu_derat_epsc1_eas => xu_derat_epsc1_eas, + xu_derat_epsc1_egs => xu_derat_epsc1_egs, + xu_derat_epsc1_elpid => xu_derat_epsc1_elpid, + xu_derat_epsc1_epid => xu_derat_epsc1_epid, + xu_derat_epsc2_epr => xu_derat_epsc2_epr, + xu_derat_epsc2_eas => xu_derat_epsc2_eas, + xu_derat_epsc2_egs => xu_derat_epsc2_egs, + xu_derat_epsc2_elpid => xu_derat_epsc2_elpid, + xu_derat_epsc2_epid => xu_derat_epsc2_epid, + xu_derat_epsc3_epr => xu_derat_epsc3_epr, + xu_derat_epsc3_eas => xu_derat_epsc3_eas, + xu_derat_epsc3_egs => xu_derat_epsc3_egs, + xu_derat_epsc3_elpid => xu_derat_epsc3_elpid, + xu_derat_epsc3_epid => xu_derat_epsc3_epid, + + xu_mm_derat_req => xu_mm_derat_req, + xu_mm_derat_thdid => xu_mm_derat_thdid, + xu_mm_derat_state => xu_mm_derat_state, + xu_mm_derat_tid => xu_mm_derat_tid, + xu_mm_derat_ttype => xu_mm_derat_ttype, + xu_mm_derat_lpid => xu_mm_derat_lpid, + + mm_xu_derat_rel_val => mm_xu_derat_rel_val, + mm_xu_derat_rel_data => mm_xu_derat_rel_data, + + mm_xu_derat_pid0 => mm_xu_derat_pid0, + mm_xu_derat_pid1 => mm_xu_derat_pid1, + mm_xu_derat_pid2 => mm_xu_derat_pid2, + mm_xu_derat_pid3 => mm_xu_derat_pid3, + + mm_xu_derat_mmucr0_0 => mm_xu_derat_mmucr0_0, + mm_xu_derat_mmucr0_1 => mm_xu_derat_mmucr0_1, + mm_xu_derat_mmucr0_2 => mm_xu_derat_mmucr0_2, + mm_xu_derat_mmucr0_3 => mm_xu_derat_mmucr0_3, + xu_mm_derat_mmucr0 => xu_mm_derat_mmucr0, + xu_mm_derat_mmucr0_we => xu_mm_derat_mmucr0_we, + mm_xu_derat_mmucr1 => mm_xu_derat_mmucr1, + xu_mm_derat_mmucr1 => xu_mm_derat_mmucr1, + xu_mm_derat_mmucr1_we => xu_mm_derat_mmucr1_we, + + mm_xu_derat_snoop_coming => mm_xu_derat_snoop_coming, + mm_xu_derat_snoop_val => mm_xu_derat_snoop_val, + mm_xu_derat_snoop_attr => mm_xu_derat_snoop_attr, + mm_xu_derat_snoop_vpn => mm_xu_derat_snoop_vpn, + xu_mm_derat_snoop_ack => xu_mm_derat_snoop_ack, + + pc_xu_trace_bus_enable => pc_xu_trace_bus_enable, + derat_xu_debug_group0 => derat_xu_debug_group0, + derat_xu_debug_group1 => derat_xu_debug_group1, + derat_xu_debug_group2 => lsu_xu_cmd_debug(0 to 87), + derat_xu_debug_group3 => lsu_xu_cmd_debug(88 to 175) +); + +lsu_xu_ex4_tlb_data <= derat_xu_ex4_data(64-(2**REGMODE) to 63); + +lsudir : entity work.xuq_lsu_dir(xuq_lsu_dir) +generic map(expand_type => expand_type, + l_endian_m => l_endian_m, + regmode => regmode, + lmq_entries => lmq_entries, + dc_size => dc_size, + cl_size => cl_size, + wayDataSize => wayDataSize, + real_data_add => real_data_add) +port map( + + xu_lsu_rf0_act => xu_lsu_rf0_act, + xu_lsu_rf1_cmd_act => xu_lsu_rf1_cmd_act, + xu_lsu_rf1_axu_op_val => xu_lsu_rf1_axu_op_val, + xu_lsu_rf1_axu_ldst_falign => xu_lsu_rf1_axu_ldst_falign, + xu_lsu_rf1_axu_ldst_fexcpt => xu_lsu_rf1_axu_ldst_fexcpt, + xu_lsu_rf1_cache_acc => xu_lsu_rf1_cache_acc, + xu_lsu_rf1_thrd_id => xu_lsu_rf1_thrd_id, + xu_lsu_rf1_optype1 => xu_lsu_rf1_optype1, + xu_lsu_rf1_optype2 => xu_lsu_rf1_optype2, + xu_lsu_rf1_optype4 => xu_lsu_rf1_optype4, + xu_lsu_rf1_optype8 => xu_lsu_rf1_optype8, + xu_lsu_rf1_optype16 => xu_lsu_rf1_optype16, + xu_lsu_rf1_optype32 => xu_lsu_rf1_optype32, + xu_lsu_rf1_target_gpr => xu_lsu_rf1_target_gpr, + xu_lsu_rf1_mtspr_trace => xu_lsu_rf1_mtspr_trace, + xu_lsu_rf1_load_instr => xu_lsu_rf1_load_instr, + xu_lsu_rf1_store_instr => xu_lsu_rf1_store_instr, + xu_lsu_rf1_dcbf_instr => xu_lsu_rf1_dcbf_instr, + xu_lsu_rf1_sync_instr => xu_lsu_rf1_sync_instr, + xu_lsu_rf1_l_fld => xu_lsu_rf1_l_fld, + xu_lsu_rf1_dcbi_instr => xu_lsu_rf1_dcbi_instr, + xu_lsu_rf1_dcbz_instr => xu_lsu_rf1_dcbz_instr, + xu_lsu_rf1_dcbt_instr => xu_lsu_rf1_dcbt_instr, + xu_lsu_rf1_dcbtst_instr => xu_lsu_rf1_dcbtst_instr, + xu_lsu_rf1_th_fld => xu_lsu_rf1_th_fld, + xu_lsu_rf1_dcbtls_instr => xu_lsu_rf1_dcbtls_instr, + xu_lsu_rf1_dcbtstls_instr => xu_lsu_rf1_dcbtstls_instr, + xu_lsu_rf1_dcblc_instr => xu_lsu_rf1_dcblc_instr, + xu_lsu_rf1_dcbst_instr => xu_lsu_rf1_dcbst_instr, + xu_lsu_rf1_icbi_instr => xu_lsu_rf1_icbi_instr, + xu_lsu_rf1_icblc_instr => xu_lsu_rf1_icblc_instr, + xu_lsu_rf1_icbt_instr => xu_lsu_rf1_icbt_instr, + xu_lsu_rf1_icbtls_instr => xu_lsu_rf1_icbtls_instr, + xu_lsu_rf1_icswx_instr => xu_lsu_rf1_icswx_instr, + xu_lsu_rf1_icswx_dot_instr => xu_lsu_rf1_icswx_dot_instr, + xu_lsu_rf1_icswx_epid => xu_lsu_rf1_icswx_epid, + xu_lsu_rf1_tlbsync_instr => xu_lsu_rf1_tlbsync_instr, + xu_lsu_rf1_ldawx_instr => xu_lsu_rf1_ldawx_instr, + xu_lsu_rf1_wclr_instr => xu_lsu_rf1_wclr_instr, + xu_lsu_rf1_wchk_instr => xu_lsu_rf1_wchk_instr, + xu_lsu_rf1_lock_instr => xu_lsu_rf1_lock_instr, + xu_lsu_rf1_mutex_hint => xu_lsu_rf1_mutex_hint, + xu_lsu_rf1_mbar_instr => xu_lsu_rf1_mbar_instr, + xu_lsu_rf1_is_msgsnd => xu_lsu_rf1_is_msgsnd, + xu_lsu_rf1_dci_instr => xu_lsu_rf1_dci_instr, + xu_lsu_rf1_ici_instr => xu_lsu_rf1_ici_instr, + xu_lsu_rf1_algebraic => xu_lsu_rf1_algebraic, + xu_lsu_rf1_byte_rev => xu_lsu_rf1_byte_rev, + xu_lsu_rf1_src_gpr => xu_lsu_rf1_src_gpr, + xu_lsu_rf1_src_axu => xu_lsu_rf1_src_axu, + xu_lsu_rf1_src_dp => xu_lsu_rf1_src_dp, + xu_lsu_rf1_targ_gpr => xu_lsu_rf1_targ_gpr, + xu_lsu_rf1_targ_axu => xu_lsu_rf1_targ_axu, + xu_lsu_rf1_targ_dp => xu_lsu_rf1_targ_dp, + xu_lsu_ex4_val => xu_lsu_ex4_val, + xu_lsu_ex1_add_src0 => xu_lsu_ex1_add_src0, + xu_lsu_ex1_add_src1 => xu_lsu_ex1_add_src1, + + xu_lsu_rf1_src0_vld => xu_lsu_rf1_src0_vld, + xu_lsu_rf1_src0_reg => xu_lsu_rf1_src0_reg, + xu_lsu_rf1_src1_vld => xu_lsu_rf1_src1_vld, + xu_lsu_rf1_src1_reg => xu_lsu_rf1_src1_reg, + xu_lsu_rf1_targ_vld => xu_lsu_rf1_targ_vld, + xu_lsu_rf1_targ_reg => xu_lsu_rf1_targ_reg, + + pc_xu_inj_dcachedir_parity => pc_xu_inj_dcachedir_parity, + pc_xu_inj_dcachedir_multihit => pc_xu_inj_dcachedir_multihit, + + ex3_wimge_w_bit => derat_xu_ex3_wimge(0), + ex3_wimge_i_bit => derat_xu_ex3_wimge(1), + ex3_wimge_e_bit => derat_xu_ex3_wimge(4), + ex3_p_addr => cmp_ex3_p_addr_o(64-real_data_add to 51), + derat_xu_ex3_noop_touch => derat_xu_ex3_noop_touch, + ex3_ld_queue_full => ex3_ld_queue_full, + ex3_stq_flush => ex3_stq_flush, + ex3_ig_flush => ex3_ig_flush, + + ex2_lm_dep_hit => ex2_lm_dep_hit, + + ex3_way_cmp_a => ex3_way_cmp_a, + ex3_way_cmp_b => ex3_way_cmp_b, + ex3_way_cmp_c => ex3_way_cmp_c, + ex3_way_cmp_d => ex3_way_cmp_d, + ex3_way_cmp_e => ex3_way_cmp_e, + ex3_way_cmp_f => ex3_way_cmp_f, + ex3_way_cmp_g => ex3_way_cmp_g, + ex3_way_cmp_h => ex3_way_cmp_h, + + ex3_wayA_tag => ex3_wayA_tag, + ex3_wayB_tag => ex3_wayB_tag, + ex3_wayC_tag => ex3_wayC_tag, + ex3_wayD_tag => ex3_wayD_tag, + ex3_wayE_tag => ex3_wayE_tag, + ex3_wayF_tag => ex3_wayF_tag, + ex3_wayG_tag => ex3_wayG_tag, + ex3_wayH_tag => ex3_wayH_tag, + + xu_lsu_mtspr_trace_en => xu_lsu_mtspr_trace_en, + spr_xucr0_clkg_ctl_b1 => spr_xucr0_clkg_ctl_b1, + xu_lsu_spr_xucr0_aflsta => xu_lsu_spr_xucr0_aflsta, + xu_lsu_spr_xucr0_flsta => xu_lsu_spr_xucr0_flsta, + xu_lsu_spr_xucr0_l2siw => xu_lsu_spr_xucr0_l2siw, + xu_lsu_spr_xucr0_dcdis => xu_lsu_spr_xucr0_dcdis, + xu_lsu_spr_xucr0_wlk => xu_lsu_spr_xucr0_wlk, + xu_lsu_spr_ccr2_dfrat => xu_lsu_spr_ccr2_dfrat, + xu_lsu_spr_xucr0_clfc => xu_lsu_spr_xucr0_clfc, + xu_lsu_spr_xucr0_flh2l2 => xu_lsu_spr_xucr0_flh2l2, + xu_lsu_spr_xucr0_cls => xu_lsu_spr_xucr0_cls, + xu_lsu_spr_msr_cm => xu_lsu_msr_cm, + xu_lsu_msr_gs => xu_lsu_msr_gs, + xu_lsu_msr_pr => xu_lsu_msr_pr, + + an_ac_flh2l2_gate => an_ac_flh2l2_gate, + + ldq_rel1_early_v => ldq_rel1_early_v, + ldq_rel1_val => ldq_rel1_val, + ldq_rel_mid_val => ldq_rel_mid_val, + ldq_rel_retry_val => ldq_rel_retry_val, + ldq_rel3_early_v => ldq_rel3_early_v, + ldq_rel3_val => ldq_rel3_val, + ldq_rel_back_invalidated => ldq_rel_back_invalidated, + ldq_rel_data_val_early => rel_data_val_early, + rel_data_val => rel_data_val, + ldq_rel_tag => ldq_rel_tag, + ldq_rel_tag_early => ldq_rel_tag_early, + ldq_rel_set_val => ldq_rel_set_val, + ldq_rel_ecc_err => ldq_rel_ecc_err, + ldq_rel_classid => ldq_rel_classid, + ldq_rel_lock_en => ldq_rel_lock_en, + ldq_rel_l1dump_cslc => ldq_rel_l1dump_cslc, + ldq_rel3_l1dump_val => ldq_rel3_l1dump_val, + ldq_rel_watch_en => ldq_rel_watch_en, + ldq_rel_addr => rel_ldq_addr(64-real_data_add to 52), + ldq_rel_addr_early => ldq_rel_addr_early, + ldq_rel_axu_val => rel_ldq_axu_val, + ldq_rel_thrd_id => rel_ldq_thrd_id, + ldq_rel_ta_gpr => ldq_rel_ta_gpr, + ldq_rel_upd_gpr => rel_ldq_upd_gpr, + ldq_rel_ci => rel_ldq_ci, + ldq_recirc_rel_val => ldq_recirc_rel_val, + + xu_lsu_dci => xu_lsu_dci, + + is2_l2_inv_val => is2_l2_inv_val, + + ex6_ld_par_err => ex6_ld_par_err, + + xu_lsu_rf1_flush => xu_lsu_rf1_flush, + xu_lsu_ex1_flush => xu_lsu_ex1_flush, + xu_lsu_ex2_flush => xu_lsu_ex2_flush, + xu_lsu_ex3_flush => xu_lsu_ex3_flush, + xu_lsu_ex4_flush => xu_lsu_ex4_flush, + xu_lsu_ex5_flush => xu_lsu_ex5_flush, + + xu_lsu_slowspr_val => xu_lsu_slowspr_val, + xu_lsu_slowspr_rw => xu_lsu_slowspr_rw, + xu_lsu_slowspr_etid => xu_lsu_slowspr_etid, + xu_lsu_slowspr_addr => xu_lsu_slowspr_addr, + xu_lsu_slowspr_data => xu_lsu_slowspr_data, + xu_lsu_slowspr_done => xu_lsu_slowspr_done, + slowspr_val_out => slowspr_val_out, + slowspr_rw_out => slowspr_rw_out, + slowspr_etid_out => slowspr_etid_out, + slowspr_addr_out => slowspr_addr_out, + slowspr_data_out => slowspr_data_out, + slowspr_done_out => slowspr_done_out, + + dir_arr_rd_addr_01 => dir_arr_rd_addr_01, + dir_arr_rd_addr_23 => dir_arr_rd_addr_23, + dir_arr_rd_addr_45 => dir_arr_rd_addr_45, + dir_arr_rd_addr_67 => dir_arr_rd_addr_67, + dir_arr_rd_data => dir_arr_rd_data, + + dir_wr_enable => dir_wr_enable, + dir_wr_way => dir_wr_way, + dir_arr_wr_addr => dir_arr_wr_addr, + dir_arr_wr_data => dir_arr_wr_data, + + ex1_src0_vld => ex1_src0_vld, + ex1_src0_reg => ex1_src0_reg, + ex1_src1_vld => ex1_src1_vld, + ex1_src1_reg => ex1_src1_reg, + ex1_targ_vld => ex1_targ_vld, + ex1_targ_reg => ex1_targ_reg, + ex1_check_watch => ex1_check_watch, + + xu_derat_ex1_epn_arr => xu_derat_ex1_epn_arr, + xu_derat_ex1_epn_nonarr => xu_derat_ex1_epn_nonarr, + snoop_addr => snoop_addr, + snoop_addr_sel => snoop_addr_sel, + xu_derat_rf1_binv_val => xu_derat_rf1_binv_val, + ex3_cache_acc => ex3_cache_acc, + ex1_optype1 => ex1_optype1, + ex1_optype2 => ex1_optype2, + ex1_optype4 => ex1_optype4, + ex1_optype8 => ex1_optype8, + ex1_optype16 => ex1_optype16, + ex1_optype32 => ex1_optype32, + ex1_saxu_instr => ex1_saxu_instr, + ex1_sdp_instr => ex1_sdp_instr, + ex1_stgpr_instr => ex1_stgpr_instr, + ex1_store_instr => ex1_store_instr, + ex1_axu_op_val => ex1_axu_op_val, + + lsu_xu_ex3_align => lsu_xu_ex3_align, + lsu_xu_ex3_dsi => lsu_xu_ex3_dsi, + lsu_xu_ex3_inval_align_2ucode => lsu_xu_ex3_inval_align_2ucode, + + ex3_stg_flush => ex3_flush_stg, + ex4_stg_flush => ex4_flush_stg, + lsu_xu_ex3_n_flush_req => lsu_xu_ex3_n_flush_req, + lsu_xu_ex4_ldq_full_flush => lsu_xu_ex4_ldq_full_flush, + lsu_xu_ex3_dep_flush => lsu_xu_ex3_dep_flush, + + ex2_p_addr_lwr => ex2_p_addr_lwr, + ex3_p_addr_lwr => ex3_p_addr_lwr, + ex3_req_thrd_id => ex3_req_thrd_id, + ex3_target_gpr => ex3_target_gpr, + ex3_dcbt_instr => ex3_dcbt_instr, + ex3_dcbtst_instr => ex3_dcbtst_instr, + ex3_th_fld_l2 => ex3_th_fld_l2, + ex3_dcbst_instr => ex3_dcbst_instr, + ex3_dcbf_instr => ex3_dcbf_instr, + ex3_sync_instr => ex3_sync_instr, + ex3_mtspr_trace => ex3_mtspr_trace, + ex3_byte_en => ex3_byte_en, + ex3_l_fld => ex3_l_fld, + ex3_dcbi_instr => ex3_dcbi_instr, + ex3_dcbz_instr => ex3_dcbz_instr, + ex3_icbi_instr => ex3_icbi_instr, + ex3_icswx_instr => ex3_icswx_instr, + ex3_icswx_dot => ex3_icswx_dot, + ex3_icswx_epid => ex3_icswx_epid, + ex3_mbar_instr => ex3_mbar_instr, + ex3_msgsnd_instr => ex3_msgsnd_instr, + ex3_dci_instr => ex3_dci_instr, + ex3_ici_instr => ex3_ici_instr, + ex3_load_instr => ex3_load_instr, + ex3_store_instr => ex3_store_instr, + ex3_axu_op_val => ex3_axu_op_val, + ex3_algebraic => ex3_algebraic_op, + ex3_dcbtls_instr => ex3_dcbtls_instr, + ex3_dcbtstls_instr => ex3_dcbtstls_instr, + ex3_dcblc_instr => ex3_dcblc_instr, + ex3_icblc_instr => ex3_icblc_instr, + ex3_icbt_instr => ex3_icbt_instr, + ex3_icbtls_instr => ex3_icbtls_instr, + ex3_tlbsync_instr => ex3_tlbsync_instr, + ex3_local_dcbf => ex3_local_dcbf, + ex3_lock_en => ex3_lock_en, + ex4_drop_rel => ex4_drop_rel, + ex3_load_l1hit => ex3_load_l1hit, + ex3_rotate_sel => ex3_rotate_sel, + ex3_watch_en => ex3_watch_en, + ex3_data_swap => ex3_data_swap_int, + ex3_blkable_touch => ex3_blkable_touch, + ex7_targ_match => ex7_targ_match, + ex8_targ_match => ex8_targ_match, + ex4_ld_entry => ex4_ld_entry, + + ex3_cache_inh => ex3_cache_inh, + ex3_l_s_q_val => ex3_l_s_q_val, + ex3_drop_ld_req => ex3_drop_ld_req, + ex3_drop_touch => ex3_drop_touch, + ex3_stx_instr => ex3_stx_instr, + ex3_larx_instr => ex3_larx_instr, + ex3_mutex_hint => ex3_mutex_hint, + ex3_opsize => ex3_opsize, + ex4_dir_perr_det => ex4_dir_perr_det(0), + ex4_dir_multihit_det => ex4_dir_multihit_det(0), + ex4_n_lsu_ddmh_flush => ex4_n_lsu_ddmh_flush, + + dcpar_err_flush => dcpar_err_flush, + pe_recov_begin => pe_recov_begin, + + lsu_xu_ex3_ddir_par_err => lsu_xu_ex3_ddir_par_err, + ex3_cClass_collision => ex3_cClass_collision, + + ex3_cClass_upd_way_a => ex3_cClass_upd_way_a, + ex3_cClass_upd_way_b => ex3_cClass_upd_way_b, + ex3_cClass_upd_way_c => ex3_cClass_upd_way_c, + ex3_cClass_upd_way_d => ex3_cClass_upd_way_d, + ex3_cClass_upd_way_e => ex3_cClass_upd_way_e, + ex3_cClass_upd_way_f => ex3_cClass_upd_way_f, + ex3_cClass_upd_way_g => ex3_cClass_upd_way_g, + ex3_cClass_upd_way_h => ex3_cClass_upd_way_h, + + ex2_wayA_tag => ex2_wayA_tag, + ex2_wayB_tag => ex2_wayB_tag, + ex2_wayC_tag => ex2_wayC_tag, + ex2_wayD_tag => ex2_wayD_tag, + ex2_wayE_tag => ex2_wayE_tag, + ex2_wayF_tag => ex2_wayF_tag, + ex2_wayG_tag => ex2_wayG_tag, + ex2_wayH_tag => ex2_wayH_tag, + + rel_upd_dcarr_val => rel_upd_dcarr_val, + + lsu_xu_ex4_cr_upd => lsu_xu_ex4_cr_upd, + lsu_xu_ex5_cr_rslt => lsu_xu_ex5_cr_rslt, + lsu_xu_ex5_wren => lsu_xu_ex5_wren, + lsu_xu_rel_wren => lsu_xu_rel_wren, + lsu_xu_rel_ta_gpr => lsu_xu_rel_ta_gpr, + lsu_xu_perf_events => lsu_perf_events(0 to 37), + lsu_xu_need_hole => lsu_xu_need_hole, + xu_fu_ex5_reload_val => xu_fu_ex5_reload_val, + xu_fu_ex5_load_val => xu_fu_ex5_load_val, + xu_fu_ex5_load_tag => xu_fu_ex5_load_tag, + + xu_iu_ex6_icbi_val => xu_iu_ex6_icbi_val, + xu_iu_ex6_icbi_addr => xu_iu_ex6_icbi_addr, + + dcarr_up_way_addr => dcarr_up_way_addr, + + xu_derat_epsc_wr => xu_derat_epsc_wr, + xu_derat_eplc_wr => xu_derat_eplc_wr, + xu_derat_eplc0_epr => xu_derat_eplc0_epr, + xu_derat_eplc0_eas => xu_derat_eplc0_eas, + xu_derat_eplc0_egs => xu_derat_eplc0_egs, + xu_derat_eplc0_elpid => xu_derat_eplc0_elpid, + xu_derat_eplc0_epid => xu_derat_eplc0_epid, + xu_derat_eplc1_epr => xu_derat_eplc1_epr, + xu_derat_eplc1_eas => xu_derat_eplc1_eas, + xu_derat_eplc1_egs => xu_derat_eplc1_egs, + xu_derat_eplc1_elpid => xu_derat_eplc1_elpid, + xu_derat_eplc1_epid => xu_derat_eplc1_epid, + xu_derat_eplc2_epr => xu_derat_eplc2_epr, + xu_derat_eplc2_eas => xu_derat_eplc2_eas, + xu_derat_eplc2_egs => xu_derat_eplc2_egs, + xu_derat_eplc2_elpid => xu_derat_eplc2_elpid, + xu_derat_eplc2_epid => xu_derat_eplc2_epid, + xu_derat_eplc3_epr => xu_derat_eplc3_epr, + xu_derat_eplc3_eas => xu_derat_eplc3_eas, + xu_derat_eplc3_egs => xu_derat_eplc3_egs, + xu_derat_eplc3_elpid => xu_derat_eplc3_elpid, + xu_derat_eplc3_epid => xu_derat_eplc3_epid, + xu_derat_epsc0_epr => xu_derat_epsc0_epr, + xu_derat_epsc0_eas => xu_derat_epsc0_eas, + xu_derat_epsc0_egs => xu_derat_epsc0_egs, + xu_derat_epsc0_elpid => xu_derat_epsc0_elpid, + xu_derat_epsc0_epid => xu_derat_epsc0_epid, + xu_derat_epsc1_epr => xu_derat_epsc1_epr, + xu_derat_epsc1_eas => xu_derat_epsc1_eas, + xu_derat_epsc1_egs => xu_derat_epsc1_egs, + xu_derat_epsc1_elpid => xu_derat_epsc1_elpid, + xu_derat_epsc1_epid => xu_derat_epsc1_epid, + xu_derat_epsc2_epr => xu_derat_epsc2_epr, + xu_derat_epsc2_eas => xu_derat_epsc2_eas, + xu_derat_epsc2_egs => xu_derat_epsc2_egs, + xu_derat_epsc2_elpid => xu_derat_epsc2_elpid, + xu_derat_epsc2_epid => xu_derat_epsc2_epid, + xu_derat_epsc3_epr => xu_derat_epsc3_epr, + xu_derat_epsc3_eas => xu_derat_epsc3_eas, + xu_derat_epsc3_egs => xu_derat_epsc3_egs, + xu_derat_epsc3_elpid => xu_derat_epsc3_elpid, + xu_derat_epsc3_epid => xu_derat_epsc3_epid, + + ex1_stg_act => ex1_stg_act, + ex2_stg_act => ex2_stg_act, + ex3_stg_act => ex3_stg_act, + ex4_stg_act => ex4_stg_act, + binv1_stg_act => binv1_stg_act, + binv2_stg_act => binv2_stg_act, + + lsu_xu_spr_xucr0_cslc_xuop => lsu_xu_spr_xucr0_cslc_xuop, + lsu_xu_spr_xucr0_cslc_binv => lsu_xu_spr_xucr0_cslc_binv, + lsu_xu_spr_xucr0_clo => lsu_xu_spr_xucr0_clo, + lsu_xu_spr_xucr0_cul => lsu_xu_spr_xucr0_cul, + spr_xucr0_cls => spr_xucr0_cls, + + dir_arr_rd_is2_val => dir_arr_rd_is2_val, + dir_arr_rd_congr_cl => dir_arr_rd_congr_cl, + + ex4_load_op_hit => ex4_load_op_hit, + ex4_store_hit => ex4_store_hit, + ex4_axu_op_val => ex4_axu_op_val, + spr_dvc1_act => spr_dvc1_act, + spr_dvc2_act => spr_dvc2_act, + spr_dvc1_dbg => spr_dvc1_dbg, + spr_dvc2_dbg => spr_dvc2_dbg, + + pc_xu_trace_bus_enable => pc_xu_trace_bus_enable, + dc_fgen_dbg_data => dc_fgen_dbg_data, + dc_cntrl_dbg_data => dc_cntrl_dbg_data, + dc_val_dbg_data => dc_val_dbg_data, + dc_lru_dbg_data => dc_lru_dbg_data, + dc_dir_dbg_data => dc_dir_dbg_data, + dir_arr_dbg_data => dir_arr_dbg_data, + + vdd => vdd, + gnd => gnd, + nclk => nclk, + sg_0 => sg_0, + func_sl_thold_0_b => func_sl_thold_0_b, + func_sl_force => func_sl_force, + func_slp_sl_thold_0_b => func_slp_sl_thold_0_b, + func_slp_sl_force => func_slp_sl_force, + func_nsl_thold_0_b => func_nsl_thold_0_b, + func_nsl_force => func_nsl_force, + func_slp_nsl_thold_0_b => func_slp_nsl_thold_0_b, + func_slp_nsl_force => func_slp_nsl_force, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc(5), + mpw1_dc_b => mpw1_dc_b(5), + mpw2_dc_b => mpw2_dc_b, + scan_in => func_scan_in_q(43 to 46), + scan_out(0 to 1) => func_scan_out_int(43 to 44), + scan_out(2 to 3) => dir_scan_out +); + + +binv2_ex2_stg_act <= binv2_stg_act or ex2_stg_act; + + lsucmp: entity work.xuq_lsu_cmp(xuq_lsu_cmp) +generic map(expand_type => expand_type) + port map( + vdd => vdd , + gnd => gnd , + nclk => nclk , + delay_lclkr (0) => delay_lclkr_dc(5) , + delay_lclkr (1) => delay_lclkr_dc(5) , + delay_lclkr (2) => delay_lclkr_dc(5) , + mpw1_b (0) => mpw1_dc_b(5) , + mpw1_b (1) => mpw1_dc_b(5) , + mpw1_b (2) => mpw1_dc_b(5) , + mpw2_b (0) => mpw2_dc_b , + mpw2_b (1) => mpw2_dc_b , + mpw2_b (2) => mpw2_dc_b , + forcee (0) => func_slp_sl_force , + forcee (1) => func_slp_sl_force , + forcee (2) => func_sl_force , + sg_0 (0) => sg_0 , + sg_0 (1) => sg_0 , + sg_0 (2) => sg_0 , + thold_0_b (0) => func_slp_sl_thold_0_b , + thold_0_b (1) => func_slp_sl_thold_0_b , + thold_0_b (2) => func_sl_thold_0_b , + scan_in (0) => derat_scan_out(0) , + scan_in (1) => dir_scan_out(1) , + scan_in (2) => l2cmdq_scan_out , + scan_out (0) => func_scan_out_int(41) , + scan_out (1) => cmp_scan_out , + scan_out (2) => func_scan_out_int(47) , + enable_lsb_lmq_b => spr_xucr0_cls, + enable_lsb_oth_b => spr_xucr0_cls, + enable_lsb_bi_b => spr_xucr0_cls, + ex2_erat_act => binv2_ex2_stg_act , + binv2_ex2_stg_act => binv2_ex2_stg_act , + lmq_entry_act => cmp_lmq_entry_act , + ex3_p_addr => derat_xu_ex3_rpn , + ex2_p_addr_lwr => ex2_p_addr_lwr(52 to 57) , + ex3_p_addr_o => cmp_ex3_p_addr_o(22 to 57) , + ex2_wayA_tag(22 to 52) => ex2_wayA_tag(22 to 52) , + ex2_wayB_tag(22 to 52) => ex2_wayB_tag(22 to 52) , + ex2_wayC_tag(22 to 52) => ex2_wayC_tag(22 to 52) , + ex2_wayD_tag(22 to 52) => ex2_wayD_tag(22 to 52) , + ex2_wayE_tag(22 to 52) => ex2_wayE_tag(22 to 52) , + ex2_wayF_tag(22 to 52) => ex2_wayF_tag(22 to 52) , + ex2_wayG_tag(22 to 52) => ex2_wayG_tag(22 to 52) , + ex2_wayH_tag(22 to 52) => ex2_wayH_tag(22 to 52) , + ex3_cClass_upd_way_a => ex3_cClass_upd_way_a , + ex3_cClass_upd_way_b => ex3_cClass_upd_way_b , + ex3_cClass_upd_way_c => ex3_cClass_upd_way_c , + ex3_cClass_upd_way_d => ex3_cClass_upd_way_d , + ex3_cClass_upd_way_e => ex3_cClass_upd_way_e , + ex3_cClass_upd_way_f => ex3_cClass_upd_way_f , + ex3_cClass_upd_way_g => ex3_cClass_upd_way_g , + ex3_cClass_upd_way_h => ex3_cClass_upd_way_h , + ex3_way_cmp_a => ex3_way_cmp_a , + ex3_way_cmp_b => ex3_way_cmp_b , + ex3_way_cmp_c => ex3_way_cmp_c , + ex3_way_cmp_d => ex3_way_cmp_d , + ex3_way_cmp_e => ex3_way_cmp_e , + ex3_way_cmp_f => ex3_way_cmp_f , + ex3_way_cmp_g => ex3_way_cmp_g , + ex3_way_cmp_h => ex3_way_cmp_h , + ex3_wayA_tag => ex3_wayA_tag, + ex3_wayB_tag => ex3_wayB_tag, + ex3_wayC_tag => ex3_wayC_tag, + ex3_wayD_tag => ex3_wayD_tag, + ex3_wayE_tag => ex3_wayE_tag, + ex3_wayF_tag => ex3_wayF_tag, + ex3_wayG_tag => ex3_wayG_tag, + ex3_wayH_tag => ex3_wayH_tag, + + ldq_comp_val(0 to 7) => cmp_ldq_comp_val(0 to 7) , + ldq_match(0 to 7) => cmp_ldq_match(0 to 7) , + ldq_fnd_b => cmp_ldq_fnd_b , + cmp_flush => cmp_flush , + dir_eq_v_or_b => ex3_cClass_collision_b , + l_q_wrt_en(0 to 7) => cmp_l_q_wrt_en(0 to 7) , + ld_ex7_recov => cmp_ld_ex7_recov , + ex7_ld_recov_addr => cmp_ex7_ld_recov_addr , + ex4_loadmiss_qentry(0 to 7) => cmp_ex4_loadmiss_qentry(0 to 7) , + ex4_ld_addr(22 to 57) => cmp_ex4_ld_addr(22 to 57) , + l_q_rd_en(0 to 7) => cmp_l_q_rd_en(0 to 7) , + l_miss_entry_addr(22 to 57) => cmp_l_miss_entry_addr(22 to 57) , + rel_tag_1hot(0 to 7) => cmp_rel_tag_1hot(0 to 7) , + rel_addr => cmp_rel_addr , + back_inv_addr => cmp_back_inv_addr , + back_inv_cmp_val(0 to 7) => cmp_back_inv_cmp_val(0 to 7) , + back_inv_addr_hit(0 to 7) => cmp_back_inv_addr_hit(0 to 7) , + s_m_queue0_addr(22 to 57) => cmp_s_m_queue0_addr(22 to 57) , + st_entry0_val => cmp_st_entry0_val , + ex3addr_hit_stq => cmp_ex3addr_hit_stq , + ex4_st_entry_addr(22 to 57) => cmp_ex4_st_entry_addr(22 to 57) , + ex4_st_val => cmp_ex4_st_val , + ex3addr_hit_ex4st => cmp_ex3addr_hit_ex4st +); + +cmp_ldq_fnd <= not cmp_ldq_fnd_b; +ex3_cClass_collision <= not ex3_cClass_collision_b; + + +dir_rd_stg_act <= ex1_stg_act or binv1_stg_act; + +dc16Kdir64B : if (2**dc_size) = 16384 and (2**cl_size) = 64 generate begin + tridirarr: entity tri.tri_32x35_8w_1r1w(tri_32x35_8w_1r1w) + GENERIC MAP (addressable_ports => 32, + addressbus_width => 5, + port_bitwidth => wayDataSize, + ways => 8, + expand_type => expand_type) + PORT MAP( + vcs => vcs, + vdd => vdd, + gnd => gnd, + + nclk => nclk, + rd0_act => dir_rd_stg_act, + sg_0 => sg_0, + ary_slp_nsl_thold_0 => ary_slp_nsl_thold_0, + abst_slp_sl_thold_0 => abst_slp_sl_thold_0, + time_sl_thold_0 => time_sl_thold_0, + repr_sl_thold_0 => repr_sl_thold_0, + clkoff_dc_b => g8t_clkoff_dc_b, + ccflush_dc => pc_xu_ccflush_dc, + scan_dis_dc_b => an_ac_scan_dis_dc_b, + scan_diag_dc => an_ac_scan_diag_dc, + d_mode_dc => g8t_d_mode_dc, + mpw1_dc_b => g8t_mpw1_dc_b, + mpw2_dc_b => g8t_mpw2_dc_b, + delay_lclkr_dc => g8t_delay_lclkr_dc, + + wr_abst_act => pc_xu_abist_g8t_wenb_q, + rd0_abst_act => pc_xu_abist_g8t1p_renb_0_q, + abist_di => pc_xu_abist_di_0_q, + abist_bw_odd => pc_xu_abist_g8t_bw_1_q, + abist_bw_even => pc_xu_abist_g8t_bw_0_q, + abist_wr_adr => pc_xu_abist_waddr_0_q, + abist_rd0_adr => pc_xu_abist_raddr_0_q, + tc_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc, + abist_ena_1 => pc_xu_abist_ena_dc, + abist_g8t_rd0_comp_ena => pc_xu_abist_wl32_comp_ena_q, + abist_raw_dc_b => pc_xu_abist_raw_dc_b, + obs0_abist_cmp => pc_xu_abist_g8t_dcomp_q, + + abst_scan_in => abist_siv(0), + time_scan_in => time_scan_in_q, + repr_scan_in => repr_scan_in_q, + abst_scan_out => abist_sov(0), + time_scan_out => time_scan_out_int(0), + repr_scan_out => repr_scan_out_int, + + lcb_bolt_sl_thold_0 => bolt_sl_thold_0, + pc_bo_enable_2 => bo_enable_2, + pc_bo_reset => pc_xu_bo_reset, + pc_bo_unload => pc_xu_bo_unload, + pc_bo_repair => pc_xu_bo_repair, + pc_bo_shdata => pc_xu_bo_shdata, + pc_bo_select => pc_xu_bo_select, + bo_pc_failout => xu_pc_bo_fail, + bo_pc_diagloop => xu_pc_bo_diagout, + tri_lcb_mpw1_dc_b => mpw1_dc_b(5), + tri_lcb_mpw2_dc_b => mpw2_dc_b, + tri_lcb_delay_lclkr_dc => delay_lclkr_dc(5), + tri_lcb_clkoff_dc_b => clkoff_dc_b, + tri_lcb_act_dis_dc => tidn, + + write_enable => dir_wr_enable, + way => dir_wr_way, + addr_wr => dir_arr_wr_addr, + data_in => dir_arr_wr_data, + addr_rd_01 => dir_arr_rd_addr_01, + addr_rd_23 => dir_arr_rd_addr_23, + addr_rd_45 => dir_arr_rd_addr_45, + addr_rd_67 => dir_arr_rd_addr_67, + data_out => dir_arr_rd_data + ); +end generate dc16Kdir64B; + +dc32Kdir64B : if (2**dc_size) = 32768 and (2**cl_size) = 64 generate begin + tridirarr: entity tri.tri_32x35_8w_1r1w(tri_32x35_8w_1r1w) + GENERIC MAP (addressable_ports => 64, + addressbus_width => 6, + port_bitwidth => wayDataSize, + ways => 8, + expand_type => expand_type) + PORT MAP( + vcs => vcs, + vdd => vdd, + gnd => gnd, + + nclk => nclk, + rd0_act => dir_rd_stg_act, + sg_0 => sg_0, + ary_slp_nsl_thold_0 => ary_slp_nsl_thold_0, + abst_slp_sl_thold_0 => abst_slp_sl_thold_0, + time_sl_thold_0 => time_sl_thold_0, + repr_sl_thold_0 => repr_sl_thold_0, + clkoff_dc_b => g8t_clkoff_dc_b, + ccflush_dc => pc_xu_ccflush_dc, + scan_dis_dc_b => an_ac_scan_dis_dc_b, + scan_diag_dc => an_ac_scan_diag_dc, + d_mode_dc => g8t_d_mode_dc, + mpw1_dc_b => g8t_mpw1_dc_b, + mpw2_dc_b => g8t_mpw2_dc_b, + delay_lclkr_dc => g8t_delay_lclkr_dc, + + wr_abst_act => pc_xu_abist_g8t_wenb_q, + rd0_abst_act => pc_xu_abist_g8t1p_renb_0_q, + abist_di => pc_xu_abist_di_0_q, + abist_bw_odd => pc_xu_abist_g8t_bw_1_q, + abist_bw_even => pc_xu_abist_g8t_bw_0_q, + abist_wr_adr => pc_xu_abist_waddr_0_q, + abist_rd0_adr => pc_xu_abist_raddr_0_q, + tc_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc, + abist_ena_1 => pc_xu_abist_ena_dc, + abist_g8t_rd0_comp_ena => pc_xu_abist_wl32_comp_ena_q, + abist_raw_dc_b => pc_xu_abist_raw_dc_b, + obs0_abist_cmp => pc_xu_abist_g8t_dcomp_q, + + abst_scan_in => abist_siv(0), + time_scan_in => time_scan_in_q, + repr_scan_in => repr_scan_in_q, + abst_scan_out => abist_sov(0), + time_scan_out => time_scan_out_int(0), + repr_scan_out => repr_scan_out_int, + + lcb_bolt_sl_thold_0 => bolt_sl_thold_0, + pc_bo_enable_2 => bo_enable_2, + pc_bo_reset => pc_xu_bo_reset, + pc_bo_unload => pc_xu_bo_unload, + pc_bo_repair => pc_xu_bo_repair, + pc_bo_shdata => pc_xu_bo_shdata, + pc_bo_select => pc_xu_bo_select, + bo_pc_failout => xu_pc_bo_fail, + bo_pc_diagloop => xu_pc_bo_diagout, + tri_lcb_mpw1_dc_b => mpw1_dc_b(5), + tri_lcb_mpw2_dc_b => mpw2_dc_b, + tri_lcb_delay_lclkr_dc => delay_lclkr_dc(5), + tri_lcb_clkoff_dc_b => clkoff_dc_b, + tri_lcb_act_dis_dc => tidn, + + write_enable => dir_wr_enable, + way => dir_wr_way, + addr_wr => dir_arr_wr_addr, + data_in => dir_arr_wr_data, + addr_rd_01 => dir_arr_rd_addr_01, + addr_rd_23 => dir_arr_rd_addr_23, + addr_rd_45 => dir_arr_rd_addr_45, + addr_rd_67 => dir_arr_rd_addr_67, + data_out => dir_arr_rd_data + ); +end generate dc32Kdir64B; + + + + + + + + + + + + + + + + + +l2cmdq : entity work.xuq_lsu_l2cmdq(xuq_lsu_l2cmdq) +generic map(expand_type => expand_type, + lmq_entries => lmq_entries, + dc_size => dc_size, + cl_size => cl_size, + real_data_add => real_data_add, + a2mode => a2mode, + load_credits => load_credits, + store_credits => store_credits, + st_data_32B_mode => st_data_32B_mode) +PORT map( + ex3_thrd_id => ex3_req_thrd_id, + ex3_l_s_q_val => ex3_l_s_q_val, + ex3_drop_ld_req => ex3_drop_ld_req, + ex3_drop_touch => ex3_drop_touch, + ex3_cache_inh => ex3_cache_inh, + ex3_load_instr => ex3_load_instr, + ex3_store_instr => ex3_store_instr, + ex3_cache_acc => ex3_cache_acc, + ex3_p_addr_lwr => ex3_p_addr_lwr(58 to 63), + ex3_opsize => ex3_opsize, + ex3_rot_sel => ex3_rotate_sel, + ex3_byte_en => ex3_byte_en, + ex4_256st_data => ex4_256st_data, + ex3_target_gpr => ex3_target_gpr, + ex3_axu_op_val => ex3_axu_op_val, + ex3_le_mode => ex3_data_swap_int, + ex3_larx_instr => ex3_larx_instr, + ex3_mutex_hint => ex3_mutex_hint, + ex3_stx_instr => ex3_stx_instr, + ex3_dcbt_instr => ex3_dcbt_instr, + ex3_dcbf_instr => ex3_dcbf_instr, + ex3_dcbtst_instr => ex3_dcbtst_instr, + ex3_dcbst_instr => ex3_dcbst_instr, + ex3_dcbz_instr => ex3_dcbz_instr, + ex3_dcbi_instr => ex3_dcbi_instr, + ex3_icbi_instr => ex3_icbi_instr, + ex3_sync_instr => ex3_sync_instr, + ex3_mtspr_trace => ex3_mtspr_trace, + ex3_l_fld => ex3_l_fld, + ex3_mbar_instr => ex3_mbar_instr, + ex3_wimge_bits => derat_xu_ex3_wimge, + ex3_usr_bits => derat_xu_ex3_u, + ex3_stg_flush => ex3_flush_stg, + ex4_stg_flush => ex4_flush_stg, + xu_lsu_ex5_flush => xu_lsu_ex5_flush, + ex3_byp_l1 => '0', + ex3_algebraic => ex3_algebraic_op, + xu_lsu_ex4_dvc1_en => xu_lsu_ex4_dvc1_en, + xu_lsu_ex4_dvc2_en => xu_lsu_ex4_dvc2_en, + ex3_dcbtls_instr => ex3_dcbtls_instr, + ex3_dcbtstls_instr => ex3_dcbtstls_instr, + ex3_dcblc_instr => ex3_dcblc_instr, + ex3_dci_instr => ex3_dci_instr, + ex3_ici_instr => ex3_ici_instr, + ex3_icblc_instr => ex3_icblc_instr, + ex3_icbt_instr => ex3_icbt_instr, + ex3_icbtls_instr => ex3_icbtls_instr, + ex3_tlbsync_instr => ex3_tlbsync_instr, + ex3_local_dcbf => ex3_local_dcbf, + ex3_icswx_instr => ex3_icswx_instr, + ex3_icswx_dot => ex3_icswx_dot, + ex3_icswx_epid => ex3_icswx_epid, + ex3_classid => derat_xu_ex3_wlc, + ex3_lock_en => ex3_lock_en, + ex3_th_fld_l2 => ex3_th_fld_l2, + ex4_drop_rel => ex4_drop_rel, + ex3_load_l1hit => ex3_load_l1hit, + ex3_msgsnd_instr => ex3_msgsnd_instr, + ex3_watch_en => ex3_watch_en, + ex3_stg_act => ex3_stg_act, + ex4_stg_act => ex4_stg_act, + ex7_targ_match => ex7_targ_match, + ex8_targ_match => ex8_targ_match, + ex4_ld_entry => ex4_ld_entry, + + xu_lsu_ex5_set_barr => xu_lsu_ex5_set_barr, + + ex1_src0_vld => ex1_src0_vld, + ex1_src0_reg => ex1_src0_reg, + ex1_src1_vld => ex1_src1_vld, + ex1_src1_reg => ex1_src1_reg, + ex1_targ_vld => ex1_targ_vld, + ex1_targ_reg => ex1_targ_reg, + ex1_check_watch => ex1_check_watch, + ex2_lm_dep_hit => ex2_lm_dep_hit, + + ex6_ld_par_err => ex6_ld_par_err, + pe_recov_begin => pe_recov_begin, + + an_ac_req_ld_pop => an_ac_req_ld_pop, + an_ac_req_st_pop => an_ac_req_st_pop, + an_ac_req_st_gather => an_ac_req_st_gather, + an_ac_req_st_pop_thrd => an_ac_req_st_pop_thrd, + + an_ac_reld_data_val => an_ac_reld_data_val, + an_ac_reld_core_tag => an_ac_reld_core_tag, + an_ac_reld_qw => an_ac_reld_qw, + an_ac_reld_data => an_ac_reld_data, + an_ac_reld_ecc_err => an_ac_reld_ecc_err, + an_ac_reld_ecc_err_ue => an_ac_reld_ecc_err_ue, + an_ac_reld_data_coming => an_ac_reld_data_coming, + an_ac_reld_ditc => an_ac_reld_ditc, + an_ac_reld_crit_qw => an_ac_reld_crit_qw, + an_ac_reld_l1_dump => an_ac_reld_l1_dump, + + an_ac_back_inv => an_ac_back_inv, + an_ac_back_inv_addr => an_ac_back_inv_addr, + an_ac_back_inv_target_bit1 => an_ac_back_inv_target_bit1, + an_ac_back_inv_target_bit4 => an_ac_back_inv_target_bit4, + an_ac_req_spare_ctrl_a1 => an_ac_req_spare_ctrl_a1, + + an_ac_stcx_complete => an_ac_stcx_complete, + xu_iu_stcx_complete => xu_iu_stcx_complete, + xu_iu_reld_core_tag_clone => xu_iu_reld_core_tag_clone, + xu_iu_reld_data_coming_clone => xu_iu_reld_data_coming_clone, + xu_iu_reld_data_vld_clone => xu_iu_reld_data_vld_clone, + xu_iu_reld_ditc_clone => xu_iu_reld_ditc_clone, + + lsu_reld_data_vld => lsu_reld_data_vld, + lsu_reld_core_tag => lsu_reld_core_tag, + lsu_reld_qw => lsu_reld_qw , + lsu_reld_ecc_err => lsu_reld_ecc_err, + lsu_reld_ditc => lsu_reld_ditc, + lsu_reld_data => lsu_reld_data, + lsu_req_st_pop => lsu_req_st_pop, + lsu_req_st_pop_thrd => lsu_req_st_pop_thrd, + + i_x_ra => i_x_ra, + i_x_request => i_x_request, + i_x_wimge => i_x_wimge, + i_x_thread => i_x_thread, + i_x_userdef => i_x_userdef, + + mm_xu_lsu_req => mm_xu_lsu_req, + mm_xu_lsu_ttype => mm_xu_lsu_ttype, + mm_xu_lsu_wimge => mm_xu_lsu_wimge, + mm_xu_lsu_u => mm_xu_lsu_u, + mm_xu_lsu_addr => mm_xu_lsu_addr, + mm_xu_lsu_lpid => mm_xu_lsu_lpid, + mm_xu_lsu_lpidr => mm_xu_lsu_lpidr, + mm_xu_lsu_gs => mm_xu_lsu_gs , + mm_xu_lsu_ind => mm_xu_lsu_ind , + mm_xu_lsu_lbit => mm_xu_lsu_lbit, + + spr_xucr0_clkg_ctl_b3 => spr_xucr0_clkg_ctl_b3, + xu_lsu_spr_xucr0_rel => xu_lsu_spr_xucr0_rel, + xu_lsu_spr_xucr0_l2siw => xu_lsu_spr_xucr0_l2siw, + xu_lsu_spr_xucr0_cred => xu_lsu_spr_xucr0_cred, + xu_lsu_spr_xucr0_mbar_ack => xu_lsu_spr_xucr0_mbar_ack, + xu_lsu_spr_xucr0_tlbsync => xu_lsu_spr_xucr0_tlbsync, + xu_lsu_spr_xucr0_cls => xu_lsu_spr_xucr0_cls, + xu_mm_lsu_token => xu_mm_lsu_token, + lsu_xu_ldq_barr_done => lsu_xu_ldq_barr_done, + lsu_xu_sync_barr_done => lsu_xu_sync_barr_done, + + mm_xu_derat_pid0 => mm_xu_derat_pid0, + mm_xu_derat_pid1 => mm_xu_derat_pid1, + mm_xu_derat_pid2 => mm_xu_derat_pid2, + mm_xu_derat_pid3 => mm_xu_derat_pid3, + xu_lsu_msr_gs => xu_lsu_msr_gs, + xu_lsu_msr_pr => xu_lsu_msr_pr, + xu_lsu_msr_ds => xu_lsu_msr_ds, + xu_derat_epsc0_epr => xu_derat_epsc0_epr, + xu_derat_epsc0_eas => xu_derat_epsc0_eas, + xu_derat_epsc0_egs => xu_derat_epsc0_egs, + xu_derat_epsc0_elpid => xu_derat_epsc0_elpid, + xu_derat_epsc0_epid => xu_derat_epsc0_epid, + xu_derat_epsc1_epr => xu_derat_epsc1_epr, + xu_derat_epsc1_eas => xu_derat_epsc1_eas, + xu_derat_epsc1_egs => xu_derat_epsc1_egs, + xu_derat_epsc1_elpid => xu_derat_epsc1_elpid, + xu_derat_epsc1_epid => xu_derat_epsc1_epid, + xu_derat_epsc2_epr => xu_derat_epsc2_epr, + xu_derat_epsc2_eas => xu_derat_epsc2_eas, + xu_derat_epsc2_egs => xu_derat_epsc2_egs, + xu_derat_epsc2_elpid => xu_derat_epsc2_elpid, + xu_derat_epsc2_epid => xu_derat_epsc2_epid, + xu_derat_epsc3_epr => xu_derat_epsc3_epr, + xu_derat_epsc3_eas => xu_derat_epsc3_eas, + xu_derat_epsc3_egs => xu_derat_epsc3_egs, + xu_derat_epsc3_elpid => xu_derat_epsc3_elpid, + xu_derat_epsc3_epid => xu_derat_epsc3_epid, + + bx_lsu_ob_pwr_tok => bx_lsu_ob_pwr_tok , + bx_lsu_ob_req_val => bx_lsu_ob_req_val , + bx_lsu_ob_ditc_val => bx_lsu_ob_ditc_val , + bx_lsu_ob_thrd => bx_lsu_ob_thrd , + bx_lsu_ob_qw => bx_lsu_ob_qw , + bx_lsu_ob_dest => bx_lsu_ob_dest , + bx_lsu_ob_data => bx_lsu_ob_data , + bx_lsu_ob_addr => bx_lsu_ob_addr , + lsu_bx_cmd_avail => lsu_bx_cmd_avail , + lsu_bx_cmd_sent => lsu_bx_cmd_sent , + lsu_bx_cmd_stall => lsu_bx_cmd_stall , + + ldq_rel_op_size => ldq_rel_op_size, + ldq_rel_thrd_id => rel_ldq_thrd_id, + ldq_rel_addr => rel_ldq_addr, + ldq_rel_addr_early => ldq_rel_addr_early, + ldq_rel_data_val => rel_data_val, + ldq_rel_data_val_early => rel_data_val_early, + ldq_rel_tag => ldq_rel_tag, + ldq_rel_tag_early => ldq_rel_tag_early, + ldq_rel1_val => ldq_rel1_val, + ldq_rel1_early_v => ldq_rel1_early_v, + ldq_rel_mid_val => ldq_rel_mid_val, + ldq_rel_retry_val => ldq_rel_retry_val, + ldq_rel3_val => ldq_rel3_val, + ldq_rel3_early_v => ldq_rel3_early_v, + ldq_rel_ta_gpr => ldq_rel_ta_gpr, + ldq_rel_rot_sel => ldq_rel_rot_sel, + ldq_rel_axu_val => rel_ldq_axu_val, + ldq_rel_upd_gpr => rel_ldq_upd_gpr, + ldq_rel_le_mode => ldq_rel_le_mode, + ldq_rel_algebraic => ldq_rel_algebraic, + ldq_rel_set_val => ldq_rel_set_val, + ldq_rel_ecc_err => ldq_rel_ecc_err, + ldq_rel_256_data => ldq_rel_256_data, + ldq_rel_classid => ldq_rel_classid, + ldq_rel_lock_en => ldq_rel_lock_en, + ldq_rel_ci => rel_ldq_ci, + ldq_rel_dvc1_en => ldq_rel_dvc1_en, + ldq_rel_dvc2_en => ldq_rel_dvc2_en, + ldq_rel_watch_en => ldq_rel_watch_en, + ldq_rel_back_invalidated => ldq_rel_back_invalidated, + ldq_recirc_rel_val => ldq_recirc_rel_val, + ldq_rel_beat_crit_qw => ldq_rel_beat_crit_qw, + ldq_rel_beat_crit_qw_block => ldq_rel_beat_crit_qw_block, + + l1dump_cslc => ldq_rel_l1dump_cslc, + ldq_rel3_l1dump_val => ldq_rel3_l1dump_val, + + is2_l2_inv_val => is2_l2_inv_val, + is2_l2_inv_p_addr => is2_l2_inv_p_addr, + + ex3_ld_queue_full => ex3_ld_queue_full, + ex3_stq_flush => ex3_stq_flush, + ex3_ig_flush => ex3_ig_flush, + gpr_ecc_err_flush_tid => gpr_ecc_err_flush_tid, + + xu_iu_ex4_loadmiss_qentry => xu_iu_ex4_loadmiss_qentry, + xu_iu_ex4_loadmiss_target => xu_iu_ex4_loadmiss_target, + xu_iu_ex4_loadmiss_target_type => xu_iu_ex4_loadmiss_target_type, + xu_iu_ex4_loadmiss_tid => xu_iu_ex4_loadmiss_tid, + xu_iu_ex5_loadmiss_qentry => xu_iu_ex5_loadmiss_qentry, + xu_iu_ex5_loadmiss_target => xu_iu_ex5_loadmiss_target, + xu_iu_ex5_loadmiss_target_type => xu_iu_ex5_loadmiss_target_type, + xu_iu_ex5_loadmiss_tid => xu_iu_ex5_loadmiss_tid, + xu_iu_complete_qentry => xu_iu_complete_qentry, + xu_iu_complete_tid => xu_iu_complete_tid, + xu_iu_complete_target_type => xu_iu_complete_target_type, + + xu_iu_larx_done_tid => xu_iu_larx_done_tid, + xu_mm_lmq_stq_empty => xu_mm_lmq_stq_empty, + lsu_xu_quiesce => lsu_xu_quiesce, + lsu_xu_dbell_val => lsu_xu_dbell_val, + lsu_xu_dbell_type => lsu_xu_dbell_type, + lsu_xu_dbell_brdcast => lsu_xu_dbell_brdcast, + lsu_xu_dbell_lpid_match => lsu_xu_dbell_lpid_match, + lsu_xu_dbell_pirtag => lsu_xu_dbell_pirtag, + + ac_an_req_pwr_token => ac_an_req_pwr_token, + ac_an_req => ac_an_req, + ac_an_req_ra => ac_an_req_ra, + ac_an_req_ttype => ac_an_req_ttype, + ac_an_req_thread => ac_an_req_thread, + ac_an_req_wimg_w => ac_an_req_wimg_w, + ac_an_req_wimg_i => ac_an_req_wimg_i, + ac_an_req_wimg_m => ac_an_req_wimg_m, + ac_an_req_wimg_g => ac_an_req_wimg_g, + ac_an_req_endian => ac_an_req_endian, + ac_an_req_user_defined => ac_an_req_user_defined, + ac_an_req_spare_ctrl_a0 => ac_an_req_spare_ctrl_a0, + ac_an_req_ld_core_tag => ac_an_req_ld_core_tag, + ac_an_req_ld_xfr_len => ac_an_req_ld_xfr_len, + ac_an_st_byte_enbl => ac_an_st_byte_enbl, + ac_an_st_data => ac_an_st_data, + ac_an_st_data_pwr_token => ac_an_st_data_pwr_token, + + cmp_lmq_entry_act => cmp_lmq_entry_act , + cmp_ex3_p_addr_o => cmp_ex3_p_addr_o , + cmp_ldq_comp_val => cmp_ldq_comp_val , + cmp_ldq_match => cmp_ldq_match , + cmp_ldq_fnd => cmp_ldq_fnd , + cmp_l_q_wrt_en => cmp_l_q_wrt_en , + cmp_ld_ex7_recov => cmp_ld_ex7_recov , + cmp_ex7_ld_recov_addr => cmp_ex7_ld_recov_addr , + cmp_ex4_loadmiss_qentry => cmp_ex4_loadmiss_qentry, + cmp_ex4_ld_addr => cmp_ex4_ld_addr , + cmp_l_q_rd_en => cmp_l_q_rd_en , + cmp_l_miss_entry_addr => cmp_l_miss_entry_addr , + cmp_rel_tag_1hot => cmp_rel_tag_1hot , + cmp_rel_addr => cmp_rel_addr , + cmp_back_inv_addr => cmp_back_inv_addr , + cmp_back_inv_cmp_val => cmp_back_inv_cmp_val , + cmp_back_inv_addr_hit => cmp_back_inv_addr_hit , + cmp_s_m_queue0_addr => cmp_s_m_queue0_addr , + cmp_st_entry0_val => cmp_st_entry0_val , + cmp_ex3addr_hit_stq => cmp_ex3addr_hit_stq , + cmp_ex4_st_entry_addr => cmp_ex4_st_entry_addr , + cmp_ex4_st_val => cmp_ex4_st_val , + cmp_ex3addr_hit_ex4st => cmp_ex3addr_hit_ex4st , + + l2_data_ecc_err_ue => l2_data_ecc_err_ue, + xu_pc_err_l2intrf_ecc => xu_pc_err_l2intrf_ecc, + xu_pc_err_l2intrf_ue => xu_pc_err_l2intrf_ue, + xu_pc_err_invld_reld => xu_pc_err_invld_reld, + xu_pc_err_l2credit_overrun => xu_pc_err_l2credit_overrun, + an_ac_coreid => an_ac_coreid, + lsu_xu_perf_events => lsu_perf_events(38 to 46), + + ac_an_reld_ditc_pop_int => ac_an_reld_ditc_pop_int, + ac_an_reld_ditc_pop_q => ac_an_reld_ditc_pop_q , + bx_ib_empty_int => bx_ib_empty_int , + bx_ib_empty_q => bx_ib_empty_q , + + lmq_pe_recov_state => lmq_pe_recov_state, + lmq_dbg_dcache_pe => lmq_dbg_dcache_pe, + lmq_dbg_l2req => lmq_dbg_l2req, + lmq_dbg_rel => lmq_dbg_rel , + lmq_dbg_binv => lmq_dbg_binv, + lmq_dbg_pops => lmq_dbg_pops, + lmq_dbg_grp0 => lmq_dbg_grp0, + lmq_dbg_grp1 => lmq_dbg_grp1, + lmq_dbg_grp2 => lmq_dbg_grp2, + lmq_dbg_grp3 => lmq_dbg_grp3, + lmq_dbg_grp4 => lmq_dbg_grp4, + lmq_dbg_grp5 => lmq_dbg_grp5, + lmq_dbg_grp6 => lmq_dbg_grp6, + + vdd => vdd, + gnd => gnd, + nclk => nclk, + sg_0 => sg_0, + func_sl_thold_0_b => func_sl_thold_0_b, + func_sl_force => func_sl_force, + func_slp_sl_thold_0_b => func_slp_sl_thold_0_b, + func_slp_sl_force => func_slp_sl_force, + cfg_slp_sl_thold_0_b => cfg_slp_sl_thold_0_b, + cfg_slp_sl_force => cfg_slp_sl_force, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc(5), + mpw1_dc_b => mpw1_dc_b(5), + mpw2_dc_b => mpw2_dc_b, + scan_dis_dc_b => an_ac_scan_dis_dc_b, + bcfg_scan_in => bcfg_scan_in, + bcfg_scan_out => bcfg_scan_out_int, + scan_in => func_scan_in_q(47 to 49), + scan_out(0) => l2cmdq_scan_out, + scan_out(1 to 2) => func_scan_out_int(48 to 49) +); + +is2_back_inv_addr(64-real_data_add to 52) <= is2_l2_inv_p_addr(64-real_data_add to 52); + +with is2_l2_inv_val select + is2_back_inv_addr(53 to 63-cl_size) <= is2_l2_inv_p_addr(53 to 63-cl_size) when '1', + dir_arr_rd_congr_cl when others; + +lsuperf : entity work.xuq_lsu_perf(xuq_lsu_perf) +generic map(expand_type => expand_type) +PORT map( + + lsu_perf_events => lsu_perf_events, + + pc_xu_event_bus_enable => pc_xu_event_bus_enable, + pc_xu_event_count_mode => pc_xu_event_count_mode, + pc_xu_lsu_event_mux_ctrls => pc_xu_lsu_event_mux_ctrls, + pc_xu_cache_par_err_event => pc_xu_cache_par_err_event, + + xu_pc_lsu_event_data => xu_pc_lsu_event_data, + + spr_msr_gs => xu_lsu_msr_gs, + spr_msr_pr => xu_lsu_msr_pr, + + vdd => vdd, + gnd => gnd, + nclk => nclk, + sg_0 => sg_0, + func_slp_sl_thold_0_b => func_slp_sl_thold_0_b, + func_slp_sl_force => func_slp_sl_force, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc(5), + mpw1_dc_b => mpw1_dc_b(5), + mpw2_dc_b => mpw2_dc_b, + scan_in => cmp_scan_out, + scan_out => func_scan_out_int(46) +); + + +lsudbg : entity work.xuq_lsu_debug(xuq_lsu_debug) +generic map(expand_type => expand_type) +PORT map( + + pc_xu_trace_bus_enable => pc_xu_trace_bus_enable, + lsu_debug_mux_ctrls => lsu_debug_mux_ctrls, + xu_lsu_ex2_instr_trace_val => xu_lsu_ex2_instr_trace_val, + + trigger_data_in => trigger_data_in, + debug_data_in => debug_data_in, + + dc_fgen_dbg_data => dc_fgen_dbg_data, + dc_cntrl_dbg_data => dc_cntrl_dbg_data, + dc_val_dbg_data => dc_val_dbg_data, + dc_lru_dbg_data => dc_lru_dbg_data, + dc_dir_dbg_data => dc_dir_dbg_data, + dir_arr_dbg_data => dir_arr_dbg_data, + lmq_dbg_dcache_pe => lmq_dbg_dcache_pe, + lmq_dbg_l2req => lmq_dbg_l2req, + lmq_dbg_rel => lmq_dbg_rel , + lmq_dbg_binv => lmq_dbg_binv, + lmq_dbg_pops => lmq_dbg_pops, + lmq_dbg_grp0 => lmq_dbg_grp0, + lmq_dbg_grp1 => lmq_dbg_grp1, + lmq_dbg_grp2 => lmq_dbg_grp2, + lmq_dbg_grp3 => lmq_dbg_grp3, + lmq_dbg_grp4 => lmq_dbg_grp4, + lmq_dbg_grp5 => lmq_dbg_grp5, + lmq_dbg_grp6 => lmq_dbg_grp6, + pe_recov_begin => pe_recov_begin, + derat_xu_debug_group0 => derat_xu_debug_group0, + derat_xu_debug_group1 => derat_xu_debug_group1, + + trigger_data_out => trigger_data_out, + debug_data_out => debug_data_out, + + vdd => vdd, + gnd => gnd, + nclk => nclk, + sg_0 => sg_0, + func_slp_sl_thold_0_b => func_slp_sl_thold_0_b, + func_slp_sl_force => func_slp_sl_force, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc(5), + mpw1_dc_b => mpw1_dc_b(5), + mpw2_dc_b => mpw2_dc_b, + scan_in => dir_scan_out(0), + scan_out => func_scan_out_int(45) +); + + +DDPerr: tri_direct_err_rpt +generic map(width => 1, expand_type => expand_type) +port map( + vd => vdd, + gd => gnd, + err_in => ex4_dir_perr_det(0 to 0), + err_out => dcachedir_parity(0 to 0) +); + +DDMulti: tri_direct_err_rpt +generic map(width => 1, expand_type => expand_type) +port map( + vd => vdd, + gd => gnd, + err_in => ex4_dir_multihit_det(0 to 0), + err_out => dcachedir_multihit(0 to 0) +); + +ex3_data_swap <= ex3_data_swap_int; +xu_pc_err_dcachedir_parity <= dcachedir_parity(0); +xu_pc_err_dcachedir_multihit <= dcachedir_multihit(0); +lsu_xu_ex3_derat_vf <= derat_xu_ex3_vf and not ex3_blkable_touch; +ldq_rel_addr <= rel_ldq_addr(64-(dc_size-3) to 58); +ldq_rel_axu_val <= rel_ldq_axu_val; +ldq_rel_ci <= rel_ldq_ci; +ldq_rel_thrd_id <= rel_ldq_thrd_id; +xu_fu_ex3_eff_addr <= ex3_p_addr_lwr(59 to 63); +ex3_algebraic <= ex3_algebraic_op; +ex3_thrd_id <= ex3_req_thrd_id; +lsu_xu_ex3_attr <= derat_xu_ex3_u & derat_xu_ex3_wimge; +lsu_xu_ex3_l2_uc_ecc_err <= l2_data_ecc_err_ue; +lsu_xu_datc_perr_recovery <= lmq_pe_recov_state or dcpar_err_flush; +lsu_xu_l2_ecc_err_flush <= gpr_ecc_err_flush_tid; +lsu_xu_ex3_ldq_hit_flush <= cmp_flush; +lsu_xu_ex4_n_lsu_ddmh_flush <= ex4_n_lsu_ddmh_flush; +lsu_xu_is2_back_inv <= is2_l2_inv_val or dir_arr_rd_is2_val; +lsu_xu_is2_back_inv_addr <= is2_back_inv_addr; +lsu_xu_spr_epsc_epr <= xu_derat_epsc0_epr & xu_derat_epsc1_epr & xu_derat_epsc2_epr & xu_derat_epsc3_epr; +lsu_xu_spr_epsc_egs <= xu_derat_epsc0_egs & xu_derat_epsc1_egs & xu_derat_epsc2_egs & xu_derat_epsc3_egs; +bcfg_scan_out <= bcfg_scan_out_int and an_ac_scan_dis_dc_b; +ccfg_scan_out <= ccfg_scan_out_int and an_ac_scan_dis_dc_b; +abst_scan_out <= abst_scan_out_q and an_ac_scan_dis_dc_b; +time_scan_out <= time_scan_out_q and an_ac_scan_dis_dc_b; +repr_scan_out <= repr_scan_out_q and an_ac_scan_dis_dc_b; +func_scan_out <= gate(func_scan_out_q, an_ac_scan_dis_dc_b); +regf_scan_out <= gate(regf_scan_out_q, an_ac_scan_dis_dc_b); +dcfg_scan_out_int <= dcfg_scan_in; +dcfg_scan_out <= dcfg_scan_out_int and an_ac_scan_dis_dc_b; + +lsu_xu_barr_done <= derat_iu_barrier_done or lsu_xu_sync_barr_done; +ldq_rel_data_val <= rel_data_val; +ldq_rel_data_val_early <= rel_data_val_early; + +abist_reg: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 23, needs_sreset => 0) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => pc_xu_abist_ena_dc, + thold_b => abst_slp_sl_thold_0_b, + sg => sg_0, + forcee => abst_slp_sl_force, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + d_mode => d_mode_dc, + scin => abist_siv(1 to 23), + scout => abist_sov(1 to 23), + din (0) => pc_xu_abist_g8t_wenb, + din (1) => pc_xu_abist_g8t1p_renb_0, + din (2 to 5) => pc_xu_abist_di_0, + din (6) => pc_xu_abist_g8t_bw_1, + din (7) => pc_xu_abist_g8t_bw_0, + din (8 to 12) => pc_xu_abist_waddr_0, + din (13 to 17) => pc_xu_abist_raddr_0, + din (18) => pc_xu_abist_wl32_comp_ena, + din (19 to 22) => pc_xu_abist_g8t_dcomp, + dout(0) => pc_xu_abist_g8t_wenb_q, + dout(1) => pc_xu_abist_g8t1p_renb_0_q, + dout(2 to 5) => pc_xu_abist_di_0_q, + dout(6) => pc_xu_abist_g8t_bw_1_q, + dout(7) => pc_xu_abist_g8t_bw_0_q, + dout(8 to 12) => pc_xu_abist_waddr_0_q, + dout(13 to 17) => pc_xu_abist_raddr_0_q, + dout(18) => pc_xu_abist_wl32_comp_ena_q, + dout(19 to 22) => pc_xu_abist_g8t_dcomp_q); + +perv_2to1_reg: tri_plat + generic map (width => 13, expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_xu_ccflush_dc, + din(0) => func_slp_sl_thold_2, + din(1) => func_sl_thold_2(3), + din(2) => func_nsl_thold_2, + din(3) => sg_2(3), + din(4) => cfg_slp_sl_thold_2, + din(5) => ary_slp_nsl_thold_2, + din(6) => abst_slp_sl_thold_2, + din(7) => time_sl_thold_2, + din(8) => repr_sl_thold_2, + din(9) => regf_slp_sl_thold_2, + din(10) => func_slp_nsl_thold_2, + din(11) => fce_2, + din(12) => bolt_sl_thold_2, + q(0) => func_slp_sl_thold_1, + q(1) => func_sl_thold_1, + q(2) => func_nsl_thold_1, + q(3) => sg_1, + q(4) => cfg_slp_sl_thold_1, + q(5) => ary_slp_nsl_thold_1, + q(6) => abst_slp_sl_thold_1, + q(7) => time_sl_thold_1, + q(8) => repr_sl_thold_1, + q(9) => regf_slp_sl_thold_1, + q(10) => func_slp_nsl_thold_1, + q(11) => fce_1, + q(12) => bolt_sl_thold_1); + +perv_1to0_reg: tri_plat + generic map (width => 13, expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_xu_ccflush_dc, + din(0) => func_slp_sl_thold_1, + din(1) => func_sl_thold_1, + din(2) => func_nsl_thold_1, + din(3) => sg_1, + din(4) => cfg_slp_sl_thold_1, + din(5) => ary_slp_nsl_thold_1, + din(6) => abst_slp_sl_thold_1, + din(7) => time_sl_thold_1, + din(8) => repr_sl_thold_1, + din(9) => regf_slp_sl_thold_1, + din(10) => func_slp_nsl_thold_1, + din(11) => fce_1, + din(12) => bolt_sl_thold_1, + q(0) => func_slp_sl_thold_0, + q(1) => func_sl_thold_0, + q(2) => func_nsl_thold_0, + q(3) => sg_0, + q(4) => cfg_slp_sl_thold_0, + q(5) => ary_slp_nsl_thold_0, + q(6) => abst_slp_sl_thold_0, + q(7) => time_sl_thold_0, + q(8) => repr_sl_thold_0, + q(9) => regf_slp_sl_thold_0, + q(10) => func_slp_nsl_thold_0, + q(11) => fce_0, + q(12) => bolt_sl_thold_0); + +perv_lcbor_func_sl: tri_lcbor + generic map (expand_type => expand_type) +port map (clkoff_b => clkoff_dc_b, + thold => func_sl_thold_0, + sg => sg_0, + act_dis => tidn, + forcee => func_sl_force, + thold_b => func_sl_thold_0_b); + +perv_lcbor_func_nsl: tri_lcbor + generic map (expand_type => expand_type) +port map (clkoff_b => clkoff_dc_b, + thold => func_nsl_thold_0, + sg => fce_0, + act_dis => tidn, + forcee => func_nsl_force, + thold_b => func_nsl_thold_0_b); + +perv_lcbor_func_slp_sl: tri_lcbor + generic map (expand_type => expand_type) +port map (clkoff_b => clkoff_dc_b, + thold => func_slp_sl_thold_0, + sg => sg_0, + act_dis => tidn, + forcee => func_slp_sl_force, + thold_b => func_slp_sl_thold_0_b); + +perv_lcbor_cfg_slp_sl: tri_lcbor + generic map (expand_type => expand_type) +port map (clkoff_b => clkoff_dc_b, + thold => cfg_slp_sl_thold_0, + sg => sg_0, + act_dis => tidn, + forcee => cfg_slp_sl_force, + thold_b => cfg_slp_sl_thold_0_b); + +perv_lcbor_abst_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_dc_b, + thold => abst_slp_sl_thold_0, + sg => sg_0, + act_dis => tidn, + forcee => abst_slp_sl_force, + thold_b => abst_slp_sl_thold_0_b); + +perv_lcbor_func_slp_nsl: tri_lcbor + generic map (expand_type => expand_type) +port map (clkoff_b => clkoff_dc_b, + thold => func_slp_nsl_thold_0, + sg => fce_0, + act_dis => tidn, + forcee => func_slp_nsl_force, + thold_b => func_slp_nsl_thold_0_b); + +slat_force <= sg_0; +abst_slat_thold_b <= NOT abst_slp_sl_thold_0; +time_slat_thold_b <= NOT time_sl_thold_0; +repr_slat_thold_b <= NOT repr_sl_thold_0; +func_slat_thold_b <= NOT func_sl_thold_0; +regf_slat_thold_b <= NOT regf_slp_sl_thold_0; + +perv_lcbs_abst: tri_lcbs + generic map (expand_type => expand_type ) + port map ( + vd => vdd, + gd => gnd, + delay_lclkr => delay_lclkr_dc(5), + nclk => nclk, + forcee => slat_force, + thold_b => abst_slat_thold_b, + dclk => abst_slat_d2clk, + lclk => abst_slat_lclk ); + +perv_abst_stg: tri_slat_scan + generic map (width => 2, init => "00", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => abst_slat_d2clk, + lclk => abst_slat_lclk, + scan_in(0) => abst_scan_in, + scan_in(1) => abst_scan_out_int, + scan_out(0) => abst_scan_in_q, + scan_out(1) => abst_scan_out_q ); + +perv_lcbs_time: tri_lcbs + generic map (expand_type => expand_type ) + port map ( + vd => vdd, + gd => gnd, + delay_lclkr => delay_lclkr_dc(5), + nclk => nclk, + forcee => slat_force, + thold_b => time_slat_thold_b, + dclk => time_slat_d2clk, + lclk => time_slat_lclk ); + +perv_time_stg: tri_slat_scan + generic map (width => 2, init => "00", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => time_slat_d2clk, + lclk => time_slat_lclk, + scan_in(0) => time_scan_in, + scan_in(1) => time_scan_out_int(1), + scan_out(0) => time_scan_in_q, + scan_out(1) => time_scan_out_q ); + +perv_lcbs_repr: tri_lcbs + generic map (expand_type => expand_type ) + port map ( + vd => vdd, + gd => gnd, + delay_lclkr => delay_lclkr_dc(5), + nclk => nclk, + forcee => slat_force, + thold_b => repr_slat_thold_b, + dclk => repr_slat_d2clk, + lclk => repr_slat_lclk ); + +perv_repr_stg: tri_slat_scan + generic map (width => 2, init => "00", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => repr_slat_d2clk, + lclk => repr_slat_lclk, + scan_in(0) => repr_scan_in, + scan_in(1) => repr_scan_out_int, + scan_out(0) => repr_scan_in_q, + scan_out(1) => repr_scan_out_q ); + +perv_lcbs_func: tri_lcbs + generic map (expand_type => expand_type ) + port map ( + vd => vdd, + gd => gnd, + delay_lclkr => delay_lclkr_dc(5), + nclk => nclk, + forcee => slat_force, + thold_b => func_slat_thold_b, + dclk => func_slat_d2clk, + lclk => func_slat_lclk ); + +func_scan_out_int(42) <= derat_scan_out(1); + +perv_func_stg: tri_slat_scan + generic map (width => 18, init => "0000000000", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => func_slat_d2clk, + lclk => func_slat_lclk, + scan_in(0 to 8) => func_scan_in, + scan_in(9 to 17) => func_scan_out_int, + scan_out(0 to 8) => func_scan_in_q, + scan_out(9 to 17) => func_scan_out_q ); + +perv_lcbs_regf: tri_lcbs + generic map (expand_type => expand_type ) + port map ( + vd => vdd, + gd => gnd, + delay_lclkr => delay_lclkr_dc(5), + nclk => nclk, + forcee => slat_force, + thold_b => regf_slat_thold_b, + dclk => regf_slat_d2clk, + lclk => regf_slat_lclk ); + +perv_regf_stg: tri_slat_scan + generic map (width => 14, init => "00000000000000", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => regf_slat_d2clk, + lclk => regf_slat_lclk, + scan_in(0 to 6) => regf_scan_in, + scan_in(7 to 13) => regf_scan_out_int, + scan_out(0 to 6) => regf_scan_in_q, + scan_out(7 to 13) => regf_scan_out_q ); + +abist_siv <= abist_sov(1 to abist_sov'right) & abst_scan_in_q; +abst_scan_out_int <= abist_sov(0); + +mark_unused(derat_xu_ex2_miss); +mark_unused(derat_xu_ex2_rpn); +mark_unused(derat_xu_ex2_wimge); +mark_unused(derat_xu_ex2_u); +mark_unused(derat_xu_ex2_wlc); +mark_unused(derat_xu_ex2_attr); +mark_unused(derat_xu_ex2_vf); +mark_unused(derat_xu_ex3_attr); +mark_unused(derat_fir_par_err); +mark_unused(derat_fir_multihit); + +end xuq_lsu_cmd; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_cmp.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_cmp.vhdl new file mode 100644 index 0000000..e732403 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_cmp.vhdl @@ -0,0 +1,1011 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + +entity xuq_lsu_cmp is +generic( expand_type: integer := 2 ); +port( + vdd :inout power_logic; + gnd :inout power_logic; + nclk :in clk_logic; + delay_lclkr :in std_ulogic_vector(0 to 2); + mpw1_b :in std_ulogic_vector(0 to 2); + mpw2_b :in std_ulogic_vector(0 to 2); + forcee :in std_ulogic_vector(0 to 2); + sg_0 :in std_ulogic_vector(0 to 2); + thold_0_b :in std_ulogic_vector(0 to 2); + scan_in :in std_ulogic_vector(0 to 2); + scan_out :out std_ulogic_vector(0 to 2); + + enable_lsb_lmq_b :in std_ulogic ; + enable_lsb_oth_b :in std_ulogic ; + enable_lsb_bi_b :in std_ulogic ; + + ex2_erat_act :in std_ulogic; + binv2_ex2_stg_act :in std_ulogic; + lmq_entry_act :in std_ulogic; + + ex3_p_addr :in std_ulogic_vector(22 to 51); + ex2_p_addr_lwr :in std_ulogic_vector(52 to 57); + ex3_p_addr_o :out std_ulogic_vector(22 to 57); + + ex2_wayA_tag :in std_ulogic_vector(22 to 52); + ex2_wayB_tag :in std_ulogic_vector(22 to 52); + ex2_wayC_tag :in std_ulogic_vector(22 to 52); + ex2_wayD_tag :in std_ulogic_vector(22 to 52); + ex2_wayE_tag :in std_ulogic_vector(22 to 52); + ex2_wayF_tag :in std_ulogic_vector(22 to 52); + ex2_wayG_tag :in std_ulogic_vector(22 to 52); + ex2_wayH_tag :in std_ulogic_vector(22 to 52); + + ex3_cClass_upd_way_a :in std_ulogic; + ex3_cClass_upd_way_b :in std_ulogic; + ex3_cClass_upd_way_c :in std_ulogic; + ex3_cClass_upd_way_d :in std_ulogic; + ex3_cClass_upd_way_e :in std_ulogic; + ex3_cClass_upd_way_f :in std_ulogic; + ex3_cClass_upd_way_g :in std_ulogic; + ex3_cClass_upd_way_h :in std_ulogic; + + ex3_way_cmp_a :out std_ulogic; + ex3_way_cmp_b :out std_ulogic; + ex3_way_cmp_c :out std_ulogic; + ex3_way_cmp_d :out std_ulogic; + ex3_way_cmp_e :out std_ulogic; + ex3_way_cmp_f :out std_ulogic; + ex3_way_cmp_g :out std_ulogic; + ex3_way_cmp_h :out std_ulogic; + + ex3_wayA_tag :out std_ulogic_vector(0 to 30); + ex3_wayB_tag :out std_ulogic_vector(0 to 30); + ex3_wayC_tag :out std_ulogic_vector(0 to 30); + ex3_wayD_tag :out std_ulogic_vector(0 to 30); + ex3_wayE_tag :out std_ulogic_vector(0 to 30); + ex3_wayF_tag :out std_ulogic_vector(0 to 30); + ex3_wayG_tag :out std_ulogic_vector(0 to 30); + ex3_wayH_tag :out std_ulogic_vector(0 to 30); + + ldq_comp_val :in std_ulogic_vector(0 to 7); + ldq_match :out std_ulogic_vector(0 to 7); + + ldq_fnd_b :out std_ulogic; + cmp_flush :out std_ulogic; + + dir_eq_v_or_b :out std_ulogic; + + l_q_wrt_en :in std_ulogic_vector(0 to 7); + ld_ex7_recov :in std_ulogic ; + ex7_ld_recov_addr :in std_ulogic_vector(22 to 57) ; + + ex4_loadmiss_qentry :in std_ulogic_vector(0 to 7); + ex4_ld_addr :out std_ulogic_vector(22 to 57); + + l_q_rd_en :in std_ulogic_vector(0 to 7); + l_miss_entry_addr :out std_ulogic_vector(22 to 57); + + rel_tag_1hot :in std_ulogic_vector(0 to 7); + rel_addr :out std_ulogic_vector(22 to 57); + + back_inv_addr :in std_ulogic_vector(22 to 57); + back_inv_cmp_val :in std_ulogic_vector(0 to 7); + back_inv_addr_hit :out std_ulogic_vector(0 to 7); + + s_m_queue0_addr :in std_ulogic_vector(22 to 57); + st_entry0_val :in std_ulogic ; + ex3addr_hit_stq :out std_ulogic ; + + ex4_st_entry_addr :in std_ulogic_vector(22 to 57); + ex4_st_val :in std_ulogic ; + ex3addr_hit_ex4st :out std_ulogic + +); + + + +end xuq_lsu_cmp; + +architecture xuq_lsu_cmp of xuq_lsu_cmp is + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal ex3_erat_lclk, dir_lclk , lmq_lclk :clk_logic; + signal ex3_erat_d1clk, dir_d1clk , lmq_d1clk :std_ulogic; + signal ex3_erat_d2clk, dir_d2clk , lmq_d2clk :std_ulogic; + + signal ex3_erat_q :std_ulogic_vector(0 to 35); + signal ex3_erat_q_b :std_ulogic_vector(30 to 35); + signal ex3_erat_si, ex3_erat_so :std_ulogic_vector(0 to 5); + signal dir0_si, dir0_so, dir0_q_b, dir0_q :std_ulogic_vector(0 to 30); + signal dir1_si, dir1_so, dir1_q_b, dir1_q :std_ulogic_vector(0 to 30); + signal dir2_si, dir2_so, dir2_q_b, dir2_q :std_ulogic_vector(0 to 30); + signal dir3_si, dir3_so, dir3_q_b, dir3_q :std_ulogic_vector(0 to 30); + signal dir4_si, dir4_so, dir4_q_b, dir4_q :std_ulogic_vector(0 to 30); + signal dir5_si, dir5_so, dir5_q_b, dir5_q :std_ulogic_vector(0 to 30); + signal dir6_si, dir6_so, dir6_q_b, dir6_q :std_ulogic_vector(0 to 30); + signal dir7_si, dir7_so, dir7_q_b, dir7_q :std_ulogic_vector(0 to 30); + signal lmq0_si, lmq0_so, lmq0_q_b, lmq0_q , lmq0_din , lmq0_new_b , lmq0_fbk_b :std_ulogic_vector(0 to 35); + signal lmq1_si, lmq1_so, lmq1_q_b, lmq1_q , lmq1_din , lmq1_new_b , lmq1_fbk_b :std_ulogic_vector(0 to 35); + signal lmq2_si, lmq2_so, lmq2_q_b, lmq2_q , lmq2_din , lmq2_new_b , lmq2_fbk_b :std_ulogic_vector(0 to 35); + signal lmq3_si, lmq3_so, lmq3_q_b, lmq3_q , lmq3_din , lmq3_new_b , lmq3_fbk_b :std_ulogic_vector(0 to 35); + signal lmq4_si, lmq4_so, lmq4_q_b, lmq4_q , lmq4_din , lmq4_new_b , lmq4_fbk_b :std_ulogic_vector(0 to 35); + signal lmq5_si, lmq5_so, lmq5_q_b, lmq5_q , lmq5_din , lmq5_new_b , lmq5_fbk_b :std_ulogic_vector(0 to 35); + signal lmq6_si, lmq6_so, lmq6_q_b, lmq6_q , lmq6_din , lmq6_new_b , lmq6_fbk_b :std_ulogic_vector(0 to 35); + signal lmq7_si, lmq7_so, lmq7_q_b, lmq7_q , lmq7_din , lmq7_new_b , lmq7_fbk_b :std_ulogic_vector(0 to 35); + + signal l_q_wrt_en_b :std_ulogic_vector(0 to 7); + + + signal ex3_erat_i1_b :std_ulogic_vector(0 to 35); + signal ex3_erat_i2 :std_ulogic_vector(0 to 35); + signal ex3_erat_i3_b :std_ulogic_vector(0 to 35); + signal ex3_erat_i4 :std_ulogic_vector(0 to 35); + signal ex3_erat_i5_b :std_ulogic_vector(0 to 35); + signal ex3_erat_i6 :std_ulogic_vector(0 to 35); + signal ex3_erat_din :std_ulogic_vector(0 to 35); + signal ld_ex7_recov_b :std_ulogic ; + signal ex3_lmq_wd0_b, ex3_lmq_wd1_b, ex3_lmq_wd, ex3_lmq_wd_b :std_ulogic_vector(0 to 35); + + + + + + + + signal dir4_q1_b, dir4_q0 :std_ulogic_vector(0 to 30); + signal dir5_q1_b, dir5_q0 :std_ulogic_vector(0 to 30); + signal dir6_q1_b, dir6_q0 :std_ulogic_vector(0 to 30); + signal dir7_q1_b, dir7_q0 :std_ulogic_vector(0 to 30); + + + + + + signal lmq_eq, lmq_eq_b :std_ulogic_vector(0 to 7); + signal dir_eq :std_ulogic_vector(0 to 7); + + + + signal lmq0_i0_b , lmq0_ix , lmq0_ix1_b, lmq0_ix2, lmq0_iy :std_ulogic_vector(0 to 35); + signal lmq1_i0_b , lmq1_ix , lmq1_ix1_b, lmq1_ix2, lmq1_iy :std_ulogic_vector(0 to 35); + signal lmq2_i0_b , lmq2_ix , lmq2_ix1_b, lmq2_ix2, lmq2_iy :std_ulogic_vector(0 to 35); + signal lmq3_i0_b , lmq3_ix , lmq3_ix1_b, lmq3_ix2, lmq3_iy :std_ulogic_vector(0 to 35); + signal lmq4_i0_b , lmq4_ix , lmq4_ix1_b, lmq4_ix2, lmq4_iy :std_ulogic_vector(0 to 35); + signal lmq5_i0_b , lmq5_ix , lmq5_ix1_b, lmq5_ix2, lmq5_iy :std_ulogic_vector(0 to 35); + signal lmq6_i0_b , lmq6_ix , lmq6_ix1_b, lmq6_ix2, lmq6_iy :std_ulogic_vector(0 to 35); + signal lmq7_i0_b , lmq7_ix , lmq7_ix1_b, lmq7_ix2, lmq7_iy :std_ulogic_vector(0 to 35); + + + + + + + + + + + + + + + signal smq_addr_b, sto_addr_b :std_ulogic_vector(0 to 35); + signal smq_eq, smq_eqv_b, sto_eq, sto_eqv_b :std_ulogic; + + signal binv_addr_b, binv_addr :std_ulogic_vector(0 to 35); + signal binv_eq, binv_eqv_b :std_ulogic_vector(0 to 7); + + + signal mux1_lv1_01_b, mux1_lv1_23_b, mux1_lv1_45_b, mux1_lv1_67_b :std_ulogic_vector(0 to 35); + signal mux1_lv2_03, mux1_lv2_47, mux1_lv3_07_b :std_ulogic_vector(0 to 35); + + signal mux2_lv1_01_b, mux2_lv1_23_b, mux2_lv1_45_b, mux2_lv1_67_b :std_ulogic_vector(0 to 35); + signal mux2_lv2_03, mux2_lv2_47, mux2_lv3_07_b :std_ulogic_vector(0 to 35); + + signal mux3_lv1_01_b, mux3_lv1_23_b, mux3_lv1_45_b, mux3_lv1_67_b :std_ulogic_vector(0 to 35); + signal mux3_lv2_03, mux3_lv2_47, mux3_lv3_07_b :std_ulogic_vector(0 to 35); + + + signal cmpe_36_b :std_ulogic_vector(0 to 7); + signal o2_36 :std_ulogic_vector(0 to 3); + signal o4_36_b :std_ulogic_vector(0 to 1); + signal o8_36 :std_ulogic; + + signal cmpe_30_b :std_ulogic_vector(0 to 7); + signal o2_30 :std_ulogic_vector(0 to 3); + signal o4_30_b :std_ulogic_vector(0 to 1); + signal o8_30 :std_ulogic; + signal hit_b, hit, hit_1_b, hit_2, hit_3_b :std_ulogic ; + + + + + + signal dir_comp_val :std_ulogic_vector(0 to 7); + + + signal enable_lsb_lmq, enable_lsb_oth, enable_lsb_bi :std_ulogic ; + + + +begin + + + + ex3_erat_q(0 to 29) <= ex3_p_addr; + u_ex3_erat_q : ex3_erat_q (30 to 35) <= not( ex3_erat_q_b (30 to 35)); + u_ex3_erat_i1 : ex3_erat_i1_b (0 to 35) <= not( ex3_erat_q (0 to 35) ); + u_ex3_erat_i2 : ex3_erat_i2 (0 to 35) <= not( ex3_erat_i1_b (0 to 35) ); + u_ex3_erat_i3 : ex3_erat_i3_b (0 to 35) <= not( ex3_erat_i2 (0 to 35) ); + u_ex3_erat_i4 : ex3_erat_i4 (0 to 35) <= not( ex3_erat_i3_b (0 to 35) ); + u_ex3_erat_i5 : ex3_erat_i5_b (0 to 35) <= not( ex3_erat_i4 (0 to 35) ); + u_ex3_erat_i6 : ex3_erat_i6 (0 to 35) <= not( ex3_erat_i5_b (0 to 35) ); + ex3_p_addr_o(22 to 57) <= ex3_erat_i6 (0 to 35) ; + + ld_ex7_recov_b <= not( ld_ex7_recov ); + + u_ex3_lmq_wd0 : ex3_lmq_wd0_b(0 to 35) <= not( ex3_erat_i4 (0 to 35) and (0 to 35=> ld_ex7_recov_b) ) ; + u_ex3_lmq_wd1 : ex3_lmq_wd1_b(0 to 35) <= not( ex7_ld_recov_addr(22 to 57) and (0 to 35=> ld_ex7_recov ) ) ; + u_ex3_lmq_wd : ex3_lmq_wd (0 to 35) <= not( ex3_lmq_wd0_b(0 to 35) and ex3_lmq_wd1_b(0 to 35) ) ; + u_ex3_lmq_wdi : ex3_lmq_wd_b (0 to 35) <= not( ex3_lmq_wd(0 to 35) ) ; + u_ex3_erat_din : ex3_erat_din (0 to 35) <= not( ex3_lmq_wd_b(0 to 35) ); + + + + + + u_dir0_q: dir0_q (0 to 30) <= not( dir0_q_b (0 to 30) ); + u_dir1_q: dir1_q (0 to 30) <= not( dir1_q_b (0 to 30) ); + u_dir2_q: dir2_q (0 to 30) <= not( dir2_q_b (0 to 30) ); + u_dir3_q: dir3_q (0 to 30) <= not( dir3_q_b (0 to 30) ); + + u_dir4_q0: dir4_q0 (0 to 30) <= not( dir4_q_b (0 to 30) ); + u_dir5_q0: dir5_q0 (0 to 30) <= not( dir5_q_b (0 to 30) ); + u_dir6_q0: dir6_q0 (0 to 30) <= not( dir6_q_b (0 to 30) ); + u_dir7_q0: dir7_q0 (0 to 30) <= not( dir7_q_b (0 to 30) ); + + u_dir4_q1: dir4_q1_b (0 to 30) <= not( dir4_q0 (0 to 30) ); + u_dir5_q1: dir5_q1_b (0 to 30) <= not( dir5_q0 (0 to 30) ); + u_dir6_q1: dir6_q1_b (0 to 30) <= not( dir6_q0 (0 to 30) ); + u_dir7_q1: dir7_q1_b (0 to 30) <= not( dir7_q0 (0 to 30) ); + + u_dir4_q: dir4_q (0 to 30) <= not( dir4_q1_b (0 to 30) ); + u_dir5_q: dir5_q (0 to 30) <= not( dir5_q1_b (0 to 30) ); + u_dir6_q: dir6_q (0 to 30) <= not( dir6_q1_b (0 to 30) ); + u_dir7_q: dir7_q (0 to 30) <= not( dir7_q1_b (0 to 30) ); + + + + dir0cmp: entity work.xuq_lsu_cmp_cmp31(xuq_lsu_cmp_cmp31) port map( + d0(0 to 30) => ex3_erat_i2(0 to 30) , + d1(0 to 30) => dir0_q (0 to 30) , + eq => dir_eq(0) ); + + dir1cmp: entity work.xuq_lsu_cmp_cmp31(xuq_lsu_cmp_cmp31) port map( + d0(0 to 30) => ex3_erat_i2(0 to 30) , + d1(0 to 30) => dir1_q (0 to 30) , + eq => dir_eq(1) ); + + dir2cmp: entity work.xuq_lsu_cmp_cmp31(xuq_lsu_cmp_cmp31) port map( + d0(0 to 30) => ex3_erat_i2(0 to 30) , + d1(0 to 30) => dir2_q (0 to 30) , + eq => dir_eq(2) ); + + dir3cmp: entity work.xuq_lsu_cmp_cmp31(xuq_lsu_cmp_cmp31) port map( + d0(0 to 30) => ex3_erat_i2(0 to 30) , + d1(0 to 30) => dir3_q (0 to 30) , + eq => dir_eq(3) ); + + dir4cmp: entity work.xuq_lsu_cmp_cmp31(xuq_lsu_cmp_cmp31) port map( + d0(0 to 30) => ex3_erat_i2(0 to 30) , + d1(0 to 30) => dir4_q (0 to 30) , + eq => dir_eq(4) ); + + dir5cmp: entity work.xuq_lsu_cmp_cmp31(xuq_lsu_cmp_cmp31) port map( + d0(0 to 30) => ex3_erat_i2(0 to 30) , + d1(0 to 30) => dir5_q (0 to 30) , + eq => dir_eq(5) ); + + dir6cmp: entity work.xuq_lsu_cmp_cmp31(xuq_lsu_cmp_cmp31) port map( + d0(0 to 30) => ex3_erat_i2(0 to 30) , + d1(0 to 30) => dir6_q (0 to 30) , + eq => dir_eq(6) ); + + dir7cmp: entity work.xuq_lsu_cmp_cmp31(xuq_lsu_cmp_cmp31) port map( + d0(0 to 30) => ex3_erat_i2(0 to 30) , + d1(0 to 30) => dir7_q (0 to 30) , + eq => dir_eq(7) ); + + + +ex3_way_cmp_a <= dir_eq(0); +ex3_way_cmp_b <= dir_eq(1); +ex3_way_cmp_c <= dir_eq(2); +ex3_way_cmp_d <= dir_eq(3); +ex3_way_cmp_e <= dir_eq(4); +ex3_way_cmp_f <= dir_eq(5); +ex3_way_cmp_g <= dir_eq(6); +ex3_way_cmp_h <= dir_eq(7); + +ex3_wayA_tag <= not dir0_q_b; +ex3_wayB_tag <= not dir1_q_b; +ex3_wayC_tag <= not dir2_q_b; +ex3_wayD_tag <= not dir3_q_b; +ex3_wayE_tag <= not dir4_q_b; +ex3_wayF_tag <= not dir5_q_b; +ex3_wayG_tag <= not dir6_q_b; +ex3_wayH_tag <= not dir7_q_b; + + + lmq0cmp: entity work.xuq_lsu_cmp_cmp36e(xuq_lsu_cmp_cmp36e) port map( + enable_lsb => enable_lsb_lmq , + d0(0 to 35) => ex3_erat_i2(0 to 35) , + d1(0 to 35) => lmq0_iy (0 to 35) , + eq => lmq_eq(0) ); + + lmq1cmp: entity work.xuq_lsu_cmp_cmp36e(xuq_lsu_cmp_cmp36e) port map( + enable_lsb => enable_lsb_lmq , + d0(0 to 35) => ex3_erat_i2(0 to 35) , + d1(0 to 35) => lmq1_iy (0 to 35) , + eq => lmq_eq(1) ); + + lmq2cmp: entity work.xuq_lsu_cmp_cmp36e(xuq_lsu_cmp_cmp36e) port map( + enable_lsb => enable_lsb_lmq , + d0(0 to 35) => ex3_erat_i2(0 to 35) , + d1(0 to 35) => lmq2_iy (0 to 35) , + eq => lmq_eq(2) ); + + lmq3cmp: entity work.xuq_lsu_cmp_cmp36e(xuq_lsu_cmp_cmp36e) port map( + enable_lsb => enable_lsb_lmq , + d0(0 to 35) => ex3_erat_i2(0 to 35) , + d1(0 to 35) => lmq3_iy (0 to 35) , + eq => lmq_eq(3) ); + + lmq4cmp: entity work.xuq_lsu_cmp_cmp36e(xuq_lsu_cmp_cmp36e) port map( + enable_lsb => enable_lsb_lmq , + d0(0 to 35) => ex3_erat_i2(0 to 35) , + d1(0 to 35) => lmq4_iy (0 to 35) , + eq => lmq_eq(4) ); + + lmq5cmp: entity work.xuq_lsu_cmp_cmp36e(xuq_lsu_cmp_cmp36e) port map( + enable_lsb => enable_lsb_lmq , + d0(0 to 35) => ex3_erat_i2(0 to 35) , + d1(0 to 35) => lmq5_iy (0 to 35) , + eq => lmq_eq(5) ); + + lmq6cmp: entity work.xuq_lsu_cmp_cmp36e(xuq_lsu_cmp_cmp36e) port map( + enable_lsb => enable_lsb_lmq , + d0(0 to 35) => ex3_erat_i2(0 to 35) , + d1(0 to 35) => lmq6_iy (0 to 35) , + eq => lmq_eq(6) ); + + lmq7cmp: entity work.xuq_lsu_cmp_cmp36e(xuq_lsu_cmp_cmp36e) port map( + enable_lsb => enable_lsb_lmq , + d0(0 to 35) => ex3_erat_i2(0 to 35) , + d1(0 to 35) => lmq7_iy (0 to 35) , + eq => lmq_eq(7) ); + + u_lmq_cmp_cp: lmq_eq_b(0 to 7) <= not( lmq_eq (0 to 7) ); + ldq_match(0 to 7) <= not( lmq_eq_b(0 to 7) ); + + + + dir_comp_val(0) <= ex3_cClass_upd_way_a ; + dir_comp_val(1) <= ex3_cClass_upd_way_b ; + dir_comp_val(2) <= ex3_cClass_upd_way_c ; + dir_comp_val(3) <= ex3_cClass_upd_way_d ; + dir_comp_val(4) <= ex3_cClass_upd_way_e ; + dir_comp_val(5) <= ex3_cClass_upd_way_f ; + dir_comp_val(6) <= ex3_cClass_upd_way_g ; + dir_comp_val(7) <= ex3_cClass_upd_way_h ; + + + u_cmpe_36: cmpe_36_b(0 to 7) <= not( lmq_eq(0 to 7) and ldq_comp_val(0 to 7) ) ; + + u_o2_36_0: o2_36(0) <= not( cmpe_36_b(0) and cmpe_36_b(1) ); + u_o2_36_1: o2_36(1) <= not( cmpe_36_b(2) and cmpe_36_b(3) ); + u_o2_36_2: o2_36(2) <= not( cmpe_36_b(4) and cmpe_36_b(5) ); + u_o2_36_3: o2_36(3) <= not( cmpe_36_b(6) and cmpe_36_b(7) ); + + u_o4_36_0: o4_36_b(0) <= not( o2_36(0) or o2_36(1) ); + u_o4_36_1: o4_36_b(1) <= not( o2_36(2) or o2_36(3) ); + + u_o8_36: o8_36 <= not( o4_36_b(0) and o4_36_b(1) ); + + + u_cmpe_30: cmpe_30_b(0 to 7) <= not( dir_eq(0 to 7) and dir_comp_val(0 to 7) ) ; + + u_o2_30_0: o2_30(0) <= not( cmpe_30_b(0) and cmpe_30_b(1) ); + u_o2_30_1: o2_30(1) <= not( cmpe_30_b(2) and cmpe_30_b(3) ); + u_o2_30_2: o2_30(2) <= not( cmpe_30_b(4) and cmpe_30_b(5) ); + u_o2_30_3: o2_30(3) <= not( cmpe_30_b(6) and cmpe_30_b(7) ); + + u_o4_30_0: o4_30_b(0) <= not( o2_30(0) or o2_30(1) ); + u_o4_30_1: o4_30_b(1) <= not( o2_30(2) or o2_30(3) ); + + u_o8_30: o8_30 <= not( o4_30_b(0) and o4_30_b(1) ); + + + u_o16i: hit_b <= not( o8_36 ); + u_o16: hit <= not( hit_b ); + u_hit_1: hit_1_b <= not( hit ); + u_hit_2: hit_2 <= not( hit_1_b ); + u_hit_3: hit_3_b <= not( hit_2 ); + u_hit_4: cmp_flush <= not( hit_3_b ); + + + u_o8_dir: dir_eq_v_or_b <= not( o8_30 ); + u_o8_ldq: ldq_fnd_b <= not( o8_36 ); + + + + + + smq_addr_b(0 to 35) <= not( s_m_queue0_addr (22 to 57) ); + sto_addr_b(0 to 35) <= not( ex4_st_entry_addr(22 to 57) ); + + smq_cmp: entity work.xuq_lsu_cmp_cmp36e(xuq_lsu_cmp_cmp36e) port map( + enable_lsb => enable_lsb_oth , + d0(0 to 35) => ex3_erat_i5_b(0 to 35) , + d1(0 to 35) => smq_addr_b (0 to 35) , + eq => smq_eq ); + + sto_cmp: entity work.xuq_lsu_cmp_cmp36e(xuq_lsu_cmp_cmp36e) port map( + enable_lsb => enable_lsb_oth , + d0(0 to 35) => ex3_erat_i5_b(0 to 35) , + d1(0 to 35) => sto_addr_b (0 to 35) , + eq => sto_eq ); + + + u_smq_eqv: smq_eqv_b <= not( smq_eq and st_entry0_val ); + u_sto_eqv: sto_eqv_b <= not( sto_eq and ex4_st_val ); + + ex3addr_hit_stq <= not( smq_eqv_b ); + ex3addr_hit_ex4st <= not( sto_eqv_b ); + + + + + + l_q_wrt_en_b(0 to 7) <= not l_q_wrt_en(0 to 7); + + u_lmq0_q: lmq0_q (0 to 35) <= not( lmq0_q_b(0 to 35) ); + u_lmq1_q: lmq1_q (0 to 35) <= not( lmq1_q_b(0 to 35) ); + u_lmq2_q: lmq2_q (0 to 35) <= not( lmq2_q_b(0 to 35) ); + u_lmq3_q: lmq3_q (0 to 35) <= not( lmq3_q_b(0 to 35) ); + u_lmq4_q: lmq4_q (0 to 35) <= not( lmq4_q_b(0 to 35) ); + u_lmq5_q: lmq5_q (0 to 35) <= not( lmq5_q_b(0 to 35) ); + u_lmq6_q: lmq6_q (0 to 35) <= not( lmq6_q_b(0 to 35) ); + u_lmq7_q: lmq7_q (0 to 35) <= not( lmq7_q_b(0 to 35) ); + + u_lmq0_i0: lmq0_i0_b(0 to 35) <= not( lmq0_q (0 to 35) ); + u_lmq1_i0: lmq1_i0_b(0 to 35) <= not( lmq1_q (0 to 35) ); + u_lmq2_i0: lmq2_i0_b(0 to 35) <= not( lmq2_q (0 to 35) ); + u_lmq3_i0: lmq3_i0_b(0 to 35) <= not( lmq3_q (0 to 35) ); + u_lmq4_i0: lmq4_i0_b(0 to 35) <= not( lmq4_q (0 to 35) ); + u_lmq5_i0: lmq5_i0_b(0 to 35) <= not( lmq5_q (0 to 35) ); + u_lmq6_i0: lmq6_i0_b(0 to 35) <= not( lmq6_q (0 to 35) ); + u_lmq7_i0: lmq7_i0_b(0 to 35) <= not( lmq7_q (0 to 35) ); + + u_lmq0_iy: lmq0_iy (0 to 35) <= not( lmq0_i0_b(0 to 35) ); + u_lmq1_iy: lmq1_iy (0 to 35) <= not( lmq1_i0_b(0 to 35) ); + u_lmq2_iy: lmq2_iy (0 to 35) <= not( lmq2_i0_b(0 to 35) ); + u_lmq3_iy: lmq3_iy (0 to 35) <= not( lmq3_i0_b(0 to 35) ); + u_lmq4_iy: lmq4_iy (0 to 35) <= not( lmq4_i0_b(0 to 35) ); + u_lmq5_iy: lmq5_iy (0 to 35) <= not( lmq5_i0_b(0 to 35) ); + u_lmq6_iy: lmq6_iy (0 to 35) <= not( lmq6_i0_b(0 to 35) ); + u_lmq7_iy: lmq7_iy (0 to 35) <= not( lmq7_i0_b(0 to 35) ); + + u_lmq0_ix: lmq0_ix (0 to 35) <= not( lmq0_i0_b(0 to 35) ); + u_lmq1_ix: lmq1_ix (0 to 35) <= not( lmq1_i0_b(0 to 35) ); + u_lmq2_ix: lmq2_ix (0 to 35) <= not( lmq2_i0_b(0 to 35) ); + u_lmq3_ix: lmq3_ix (0 to 35) <= not( lmq3_i0_b(0 to 35) ); + u_lmq4_ix: lmq4_ix (0 to 35) <= not( lmq4_i0_b(0 to 35) ); + u_lmq5_ix: lmq5_ix (0 to 35) <= not( lmq5_i0_b(0 to 35) ); + u_lmq6_ix: lmq6_ix (0 to 35) <= not( lmq6_i0_b(0 to 35) ); + u_lmq7_ix: lmq7_ix (0 to 35) <= not( lmq7_i0_b(0 to 35) ); + + u_lmq0_ix1: lmq0_ix1_b(0 to 35) <= not( lmq0_ix (0 to 35) ); + u_lmq1_ix1: lmq1_ix1_b(0 to 35) <= not( lmq1_ix (0 to 35) ); + u_lmq2_ix1: lmq2_ix1_b(0 to 35) <= not( lmq2_ix (0 to 35) ); + u_lmq3_ix1: lmq3_ix1_b(0 to 35) <= not( lmq3_ix (0 to 35) ); + u_lmq4_ix1: lmq4_ix1_b(0 to 35) <= not( lmq4_ix (0 to 35) ); + u_lmq5_ix1: lmq5_ix1_b(0 to 35) <= not( lmq5_ix (0 to 35) ); + u_lmq6_ix1: lmq6_ix1_b(0 to 35) <= not( lmq6_ix (0 to 35) ); + u_lmq7_ix1: lmq7_ix1_b(0 to 35) <= not( lmq7_ix (0 to 35) ); + + u_lmq0_ix2: lmq0_ix2 (0 to 35) <= not( lmq0_ix1_b(0 to 35) ); + u_lmq1_ix2: lmq1_ix2 (0 to 35) <= not( lmq1_ix1_b(0 to 35) ); + u_lmq2_ix2: lmq2_ix2 (0 to 35) <= not( lmq2_ix1_b(0 to 35) ); + u_lmq3_ix2: lmq3_ix2 (0 to 35) <= not( lmq3_ix1_b(0 to 35) ); + u_lmq4_ix2: lmq4_ix2 (0 to 35) <= not( lmq4_ix1_b(0 to 35) ); + u_lmq5_ix2: lmq5_ix2 (0 to 35) <= not( lmq5_ix1_b(0 to 35) ); + u_lmq6_ix2: lmq6_ix2 (0 to 35) <= not( lmq6_ix1_b(0 to 35) ); + u_lmq7_ix2: lmq7_ix2 (0 to 35) <= not( lmq7_ix1_b(0 to 35) ); + + + u_lmq0_new: lmq0_new_b(0 to 35) <= not( ex3_erat_din(0 to 35) and (0 to 35=> l_q_wrt_en (0) ) ); + u_lmq1_new: lmq1_new_b(0 to 35) <= not( ex3_erat_din(0 to 35) and (0 to 35=> l_q_wrt_en (1) ) ); + u_lmq2_new: lmq2_new_b(0 to 35) <= not( ex3_erat_din(0 to 35) and (0 to 35=> l_q_wrt_en (2) ) ); + u_lmq3_new: lmq3_new_b(0 to 35) <= not( ex3_erat_din(0 to 35) and (0 to 35=> l_q_wrt_en (3) ) ); + u_lmq4_new: lmq4_new_b(0 to 35) <= not( ex3_erat_din(0 to 35) and (0 to 35=> l_q_wrt_en (4) ) ); + u_lmq5_new: lmq5_new_b(0 to 35) <= not( ex3_erat_din(0 to 35) and (0 to 35=> l_q_wrt_en (5) ) ); + u_lmq6_new: lmq6_new_b(0 to 35) <= not( ex3_erat_din(0 to 35) and (0 to 35=> l_q_wrt_en (6) ) ); + u_lmq7_new: lmq7_new_b(0 to 35) <= not( ex3_erat_din(0 to 35) and (0 to 35=> l_q_wrt_en (7) ) ); + + u_lmq0_fbk: lmq0_fbk_b(0 to 35) <= not( lmq0_ix (0 to 35) and (0 to 35=> l_q_wrt_en_b(0) ) ); + u_lmq1_fbk: lmq1_fbk_b(0 to 35) <= not( lmq1_ix (0 to 35) and (0 to 35=> l_q_wrt_en_b(1) ) ); + u_lmq2_fbk: lmq2_fbk_b(0 to 35) <= not( lmq2_ix (0 to 35) and (0 to 35=> l_q_wrt_en_b(2) ) ); + u_lmq3_fbk: lmq3_fbk_b(0 to 35) <= not( lmq3_ix (0 to 35) and (0 to 35=> l_q_wrt_en_b(3) ) ); + u_lmq4_fbk: lmq4_fbk_b(0 to 35) <= not( lmq4_ix (0 to 35) and (0 to 35=> l_q_wrt_en_b(4) ) ); + u_lmq5_fbk: lmq5_fbk_b(0 to 35) <= not( lmq5_ix (0 to 35) and (0 to 35=> l_q_wrt_en_b(5) ) ); + u_lmq6_fbk: lmq6_fbk_b(0 to 35) <= not( lmq6_ix (0 to 35) and (0 to 35=> l_q_wrt_en_b(6) ) ); + u_lmq7_fbk: lmq7_fbk_b(0 to 35) <= not( lmq7_ix (0 to 35) and (0 to 35=> l_q_wrt_en_b(7) ) ); + + u_lmq0_din: lmq0_din (0 to 35) <= not( lmq0_new_b (0 to 35) and lmq0_fbk_b(0 to 35) ); + u_lmq1_din: lmq1_din (0 to 35) <= not( lmq1_new_b (0 to 35) and lmq1_fbk_b(0 to 35) ); + u_lmq2_din: lmq2_din (0 to 35) <= not( lmq2_new_b (0 to 35) and lmq2_fbk_b(0 to 35) ); + u_lmq3_din: lmq3_din (0 to 35) <= not( lmq3_new_b (0 to 35) and lmq3_fbk_b(0 to 35) ); + u_lmq4_din: lmq4_din (0 to 35) <= not( lmq4_new_b (0 to 35) and lmq4_fbk_b(0 to 35) ); + u_lmq5_din: lmq5_din (0 to 35) <= not( lmq5_new_b (0 to 35) and lmq5_fbk_b(0 to 35) ); + u_lmq6_din: lmq6_din (0 to 35) <= not( lmq6_new_b (0 to 35) and lmq6_fbk_b(0 to 35) ); + u_lmq7_din: lmq7_din (0 to 35) <= not( lmq7_new_b (0 to 35) and lmq7_fbk_b(0 to 35) ); + + + + + + + binv_addr_b(0 to 35) <= not( back_inv_addr(22 to 57) ); + u_binv_addr: binv_addr (0 to 35) <= not( binv_addr_b(0 to 35) ); + + binv0cmp: entity work.xuq_lsu_cmp_cmp36e(xuq_lsu_cmp_cmp36e) port map( + enable_lsb => enable_lsb_bi , + d0(0 to 35) => binv_addr (0 to 35) , + d1(0 to 35) => lmq0_ix (0 to 35) , + eq => binv_eq(0) ); + + binv1cmp: entity work.xuq_lsu_cmp_cmp36e(xuq_lsu_cmp_cmp36e) port map( + enable_lsb => enable_lsb_bi , + d0(0 to 35) => binv_addr (0 to 35) , + d1(0 to 35) => lmq1_ix (0 to 35) , + eq => binv_eq(1) ); + + binv2cmp: entity work.xuq_lsu_cmp_cmp36e(xuq_lsu_cmp_cmp36e) port map( + enable_lsb => enable_lsb_bi , + d0(0 to 35) => binv_addr (0 to 35) , + d1(0 to 35) => lmq2_ix (0 to 35) , + eq => binv_eq(2) ); + + binv3cmp: entity work.xuq_lsu_cmp_cmp36e(xuq_lsu_cmp_cmp36e) port map( + enable_lsb => enable_lsb_bi , + d0(0 to 35) => binv_addr (0 to 35) , + d1(0 to 35) => lmq3_ix (0 to 35) , + eq => binv_eq(3) ); + + binv4cmp: entity work.xuq_lsu_cmp_cmp36e(xuq_lsu_cmp_cmp36e) port map( + enable_lsb => enable_lsb_bi , + d0(0 to 35) => binv_addr (0 to 35) , + d1(0 to 35) => lmq4_ix (0 to 35) , + eq => binv_eq(4) ); + + binv5cmp: entity work.xuq_lsu_cmp_cmp36e(xuq_lsu_cmp_cmp36e) port map( + enable_lsb => enable_lsb_bi , + d0(0 to 35) => binv_addr (0 to 35) , + d1(0 to 35) => lmq5_ix (0 to 35) , + eq => binv_eq(5) ); + + binv6cmp: entity work.xuq_lsu_cmp_cmp36e(xuq_lsu_cmp_cmp36e) port map( + enable_lsb => enable_lsb_bi , + d0(0 to 35) => binv_addr (0 to 35) , + d1(0 to 35) => lmq6_ix (0 to 35) , + eq => binv_eq(6) ); + + binv7cmp: entity work.xuq_lsu_cmp_cmp36e(xuq_lsu_cmp_cmp36e) port map( + enable_lsb => enable_lsb_bi , + d0(0 to 35) => binv_addr (0 to 35) , + d1(0 to 35) => lmq7_ix (0 to 35) , + eq => binv_eq(7) ); + + + u_binv_eqv: binv_eqv_b (0 to 7) <= not( binv_eq(0 to 7) and back_inv_cmp_val(0 to 7) ); + back_inv_addr_hit(0 to 7) <= not( binv_eqv_b(0 to 7) ); + + + + + u_mux1_lv1_01: mux1_lv1_01_b(0 to 35) <= not( ( lmq0_ix2(0 to 35) and (0 to 35 => rel_tag_1hot(0) ) ) or + ( lmq1_ix2(0 to 35) and (0 to 35 => rel_tag_1hot(1) ) ) ); + u_mux1_lv1_23: mux1_lv1_23_b(0 to 35) <= not( ( lmq2_ix2(0 to 35) and (0 to 35 => rel_tag_1hot(2) ) ) or + ( lmq3_ix2(0 to 35) and (0 to 35 => rel_tag_1hot(3) ) ) ); + u_mux1_lv1_45: mux1_lv1_45_b(0 to 35) <= not( ( lmq4_ix2(0 to 35) and (0 to 35 => rel_tag_1hot(4) ) ) or + ( lmq5_ix2(0 to 35) and (0 to 35 => rel_tag_1hot(5) ) ) ); + u_mux1_lv1_67: mux1_lv1_67_b(0 to 35) <= not( ( lmq6_ix2(0 to 35) and (0 to 35 => rel_tag_1hot(6) ) ) or + ( lmq7_ix2(0 to 35) and (0 to 35 => rel_tag_1hot(7) ) ) ); + + u_mux1_lv2_03: mux1_lv2_03(0 to 35) <= not( mux1_lv1_01_b(0 to 35) and mux1_lv1_23_b(0 to 35) ); + u_mux1_lv2_47: mux1_lv2_47(0 to 35) <= not( mux1_lv1_45_b(0 to 35) and mux1_lv1_67_b(0 to 35) ); + + u_mux1_lv3_07: mux1_lv3_07_b(0 to 35) <= not( mux1_lv2_03(0 to 35) or mux1_lv2_47(0 to 35) ); + + rel_addr(22 to 57) <= not mux1_lv3_07_b(0 to 35) ; + + + + u_mux2_lv1_01: mux2_lv1_01_b(0 to 35) <= not( ( lmq0_ix2(0 to 35) and (0 to 35 => l_q_rd_en(0) ) ) or + ( lmq1_ix2(0 to 35) and (0 to 35 => l_q_rd_en(1) ) ) ); + u_mux2_lv1_23: mux2_lv1_23_b(0 to 35) <= not( ( lmq2_ix2(0 to 35) and (0 to 35 => l_q_rd_en(2) ) ) or + ( lmq3_ix2(0 to 35) and (0 to 35 => l_q_rd_en(3) ) ) ); + u_mux2_lv1_45: mux2_lv1_45_b(0 to 35) <= not( ( lmq4_ix2(0 to 35) and (0 to 35 => l_q_rd_en(4) ) ) or + ( lmq5_ix2(0 to 35) and (0 to 35 => l_q_rd_en(5) ) ) ); + u_mux2_lv1_67: mux2_lv1_67_b(0 to 35) <= not( ( lmq6_ix2(0 to 35) and (0 to 35 => l_q_rd_en(6) ) ) or + ( lmq7_ix2(0 to 35) and (0 to 35 => l_q_rd_en(7) ) ) ); + + + u_mux2_lv2_03: mux2_lv2_03(0 to 35) <= not( mux2_lv1_01_b(0 to 35) and mux2_lv1_23_b(0 to 35) ); + u_mux2_lv2_47: mux2_lv2_47(0 to 35) <= not( mux2_lv1_45_b(0 to 35) and mux2_lv1_67_b(0 to 35) ); + + u_mux2_lv3_07: mux2_lv3_07_b(0 to 35) <= not( mux2_lv2_03(0 to 35) or mux2_lv2_47(0 to 35) ); + + l_miss_entry_addr(22 to 57) <= not mux2_lv3_07_b(0 to 35) ; + + + + + u_mux3_lv1_01: mux3_lv1_01_b(0 to 35) <= not( ( lmq0_ix2(0 to 35) and (0 to 35 => ex4_loadmiss_qentry(0) ) ) or + ( lmq1_ix2(0 to 35) and (0 to 35 => ex4_loadmiss_qentry(1) ) ) ); + u_mux3_lv1_23: mux3_lv1_23_b(0 to 35) <= not( ( lmq2_ix2(0 to 35) and (0 to 35 => ex4_loadmiss_qentry(2) ) ) or + ( lmq3_ix2(0 to 35) and (0 to 35 => ex4_loadmiss_qentry(3) ) ) ); + u_mux3_lv1_45: mux3_lv1_45_b(0 to 35) <= not( ( lmq4_ix2(0 to 35) and (0 to 35 => ex4_loadmiss_qentry(4) ) ) or + ( lmq5_ix2(0 to 35) and (0 to 35 => ex4_loadmiss_qentry(5) ) ) ); + u_mux3_lv1_67: mux3_lv1_67_b(0 to 35) <= not( ( lmq6_ix2(0 to 35) and (0 to 35 => ex4_loadmiss_qentry(6) ) ) or + ( lmq7_ix2(0 to 35) and (0 to 35 => ex4_loadmiss_qentry(7) ) ) ); + + + u_mux3_lv2_03: mux3_lv2_03(0 to 35) <= not( mux3_lv1_01_b(0 to 35) and mux3_lv1_23_b(0 to 35) ); + u_mux3_lv2_47: mux3_lv2_47(0 to 35) <= not( mux3_lv1_45_b(0 to 35) and mux3_lv1_67_b(0 to 35) ); + + u_mux3_lv3_07: mux3_lv3_07_b(0 to 35) <= not( mux3_lv2_03(0 to 35) or mux3_lv2_47(0 to 35) ); + + ex4_ld_addr(22 to 57) <= not mux3_lv3_07_b(0 to 35) ; + + + u_en_lsb_lmq: enable_lsb_lmq <= not( enable_lsb_lmq_b ); + u_en_lsb_oth: enable_lsb_oth <= not( enable_lsb_oth_b ); + u_en_lsb_bi: enable_lsb_bi <= not( enable_lsb_bi_b ); + + + + + lmq0_lat: entity tri.tri_inv_nlats generic map (width => 36, init=> (1 to 36=>'0'), btr=> "NLI0001_X1_A12TH", expand_type => expand_type) port map ( + VD => vdd , + GD => gnd , + LCLK => lmq_lclk , + D1CLK => lmq_d1clk , + D2CLK => lmq_d2clk , + SCANIN => lmq0_si , + SCANOUT => lmq0_so , + D => lmq0_din(0 to 35) , + QB => lmq0_q_b(0 to 35) ); + + lmq1_lat: entity tri.tri_inv_nlats generic map (width => 36, init=> (1 to 36=>'0'), btr=> "NLI0001_X1_A12TH", expand_type => expand_type) port map ( + VD => vdd , + GD => gnd , + LCLK => lmq_lclk , + D1CLK => lmq_d1clk , + D2CLK => lmq_d2clk , + SCANIN => lmq1_si , + SCANOUT => lmq1_so , + D => lmq1_din(0 to 35) , + QB => lmq1_q_b(0 to 35) ); + + lmq2_lat: entity tri.tri_inv_nlats generic map (width => 36, init=> (1 to 36=>'0'), btr=> "NLI0001_X1_A12TH", expand_type => expand_type) port map ( + VD => vdd , + GD => gnd , + LCLK => lmq_lclk , + D1CLK => lmq_d1clk , + D2CLK => lmq_d2clk , + SCANIN => lmq2_si , + SCANOUT => lmq2_so , + D => lmq2_din(0 to 35) , + QB => lmq2_q_b(0 to 35) ); + + lmq3_lat: entity tri.tri_inv_nlats generic map (width => 36, init=> (1 to 36=>'0'), btr=> "NLI0001_X1_A12TH", expand_type => expand_type) port map ( + VD => vdd , + GD => gnd , + LCLK => lmq_lclk , + D1CLK => lmq_d1clk , + D2CLK => lmq_d2clk , + SCANIN => lmq3_si , + SCANOUT => lmq3_so , + D => lmq3_din(0 to 35) , + QB => lmq3_q_b(0 to 35) ); + + lmq4_lat: entity tri.tri_inv_nlats generic map (width => 36, init=> (1 to 36=>'0'), btr=> "NLI0001_X1_A12TH", expand_type => expand_type) port map ( + VD => vdd , + GD => gnd , + LCLK => lmq_lclk , + D1CLK => lmq_d1clk , + D2CLK => lmq_d2clk , + SCANIN => lmq4_si , + SCANOUT => lmq4_so , + D => lmq4_din(0 to 35) , + QB => lmq4_q_b(0 to 35) ); + + lmq5_lat: entity tri.tri_inv_nlats generic map (width => 36, init=> (1 to 36=>'0'), btr=> "NLI0001_X1_A12TH", expand_type => expand_type) port map ( + VD => vdd , + GD => gnd , + LCLK => lmq_lclk , + D1CLK => lmq_d1clk , + D2CLK => lmq_d2clk , + SCANIN => lmq5_si , + SCANOUT => lmq5_so , + D => lmq5_din(0 to 35) , + QB => lmq5_q_b(0 to 35) ); + + lmq6_lat: entity tri.tri_inv_nlats generic map (width => 36, init=> (1 to 36=>'0'), btr=> "NLI0001_X1_A12TH", expand_type => expand_type) port map ( + VD => vdd , + GD => gnd , + LCLK => lmq_lclk , + D1CLK => lmq_d1clk , + D2CLK => lmq_d2clk , + SCANIN => lmq6_si , + SCANOUT => lmq6_so , + D => lmq6_din(0 to 35) , + QB => lmq6_q_b(0 to 35) ); + + lmq7_lat: entity tri.tri_inv_nlats generic map (width => 36, init=> (1 to 36=>'0'), btr=> "NLI0001_X1_A12TH", expand_type => expand_type) port map ( + VD => vdd , + GD => gnd , + LCLK => lmq_lclk , + D1CLK => lmq_d1clk , + D2CLK => lmq_d2clk , + SCANIN => lmq7_si , + SCANOUT => lmq7_so , + D => lmq7_din(0 to 35) , + QB => lmq7_q_b(0 to 35) ); + + ex3_erat_lat: entity tri.tri_inv_nlats generic map (width => 6, init=> (1 to 6=>'0'), btr=> "NLI0001_X4_A12TH", expand_type => expand_type) port map ( + VD => vdd , + GD => gnd , + LCLK => ex3_erat_lclk , + D1CLK => ex3_erat_d1clk , + D2CLK => ex3_erat_d2clk , + SCANIN => ex3_erat_si , + SCANOUT => ex3_erat_so , + D => ex2_p_addr_lwr(52 to 57) , + QB => ex3_erat_q_b(30 to 35) ); + + dir0_lat: entity tri.tri_inv_nlats generic map (width => 31, init=> (1 to 31=>'0'), btr=> "NLI0001_X2_A12TH", expand_type => expand_type) port map ( + VD => vdd , + GD => gnd , + LCLK => dir_lclk , + D1CLK => dir_d1clk , + D2CLK => dir_d2clk , + SCANIN => dir0_si , + SCANOUT => dir0_so , + D => ex2_wayA_tag(22 to 52) , + QB => dir0_q_b(0 to 30) ); + + dir1_lat: entity tri.tri_inv_nlats generic map (width => 31, init=> (1 to 31=>'0'), btr=> "NLI0001_X2_A12TH", expand_type => expand_type) port map ( + VD => vdd , + GD => gnd , + LCLK => dir_lclk , + D1CLK => dir_d1clk , + D2CLK => dir_d2clk , + SCANIN => dir1_si , + SCANOUT => dir1_so , + D => ex2_wayB_tag(22 to 52) , + QB => dir1_q_b(0 to 30) ); + + dir2_lat: entity tri.tri_inv_nlats generic map (width => 31, init=> (1 to 31=>'0'), btr=> "NLI0001_X2_A12TH", expand_type => expand_type) port map ( + VD => vdd , + GD => gnd , + LCLK => dir_lclk , + D1CLK => dir_d1clk , + D2CLK => dir_d2clk , + SCANIN => dir2_si , + SCANOUT => dir2_so , + D => ex2_wayC_tag(22 to 52) , + QB => dir2_q_b(0 to 30) ); + + dir3_lat: entity tri.tri_inv_nlats generic map (width => 31, init=> (1 to 31=>'0'), btr=> "NLI0001_X2_A12TH", expand_type => expand_type) port map ( + VD => vdd , + GD => gnd , + LCLK => dir_lclk , + D1CLK => dir_d1clk , + D2CLK => dir_d2clk , + SCANIN => dir3_si , + SCANOUT => dir3_so , + D => ex2_wayD_tag(22 to 52) , + QB => dir3_q_b(0 to 30) ); + + dir4_lat: entity tri.tri_inv_nlats generic map (width => 31, init=> (1 to 31=>'0'), btr=> "NLI0001_X2_A12TH", expand_type => expand_type) port map ( + VD => vdd , + GD => gnd , + LCLK => dir_lclk , + D1CLK => dir_d1clk , + D2CLK => dir_d2clk , + SCANIN => dir4_si , + SCANOUT => dir4_so , + D => ex2_wayE_tag(22 to 52) , + QB => dir4_q_b(0 to 30) ); + + dir5_lat: entity tri.tri_inv_nlats generic map (width => 31, init=> (1 to 31=>'0'), btr=> "NLI0001_X2_A12TH", expand_type => expand_type) port map ( + VD => vdd , + GD => gnd , + LCLK => dir_lclk , + D1CLK => dir_d1clk , + D2CLK => dir_d2clk , + SCANIN => dir5_si , + SCANOUT => dir5_so , + D => ex2_wayF_tag(22 to 52) , + QB => dir5_q_b(0 to 30) ); + + dir6_lat: entity tri.tri_inv_nlats generic map (width => 31, init=> (1 to 31=>'0'), btr=> "NLI0001_X2_A12TH", expand_type => expand_type) port map ( + VD => vdd , + GD => gnd , + LCLK => dir_lclk , + D1CLK => dir_d1clk , + D2CLK => dir_d2clk , + SCANIN => dir6_si , + SCANOUT => dir6_so , + D => ex2_wayG_tag(22 to 52) , + QB => dir6_q_b(0 to 30) ); + + dir7_lat: entity tri.tri_inv_nlats generic map (width => 31, init=> (1 to 31=>'0'), btr=> "NLI0001_X2_A12TH", expand_type => expand_type) port map ( + VD => vdd , + GD => gnd , + LCLK => dir_lclk , + D1CLK => dir_d1clk , + D2CLK => dir_d2clk , + SCANIN => dir7_si , + SCANOUT => dir7_so , + D => ex2_wayH_tag(22 to 52) , + QB => dir7_q_b(0 to 30) ); + + + + + + ex3_erat_lcb : tri_lcbnd generic map (expand_type => expand_type) port map( + nclk => nclk , + vd => vdd , + gd => gnd , + act => ex2_erat_act , + delay_lclkr => delay_lclkr (0) , + mpw1_b => mpw1_b (0) , + mpw2_b => mpw2_b (0) , + forcee => forcee (0) , + sg => sg_0 (0) , + thold_b => thold_0_b (0) , + d1clk => ex3_erat_d1clk , + d2clk => ex3_erat_d2clk , + lclk => ex3_erat_lclk ); + + dir_lcb : tri_lcbnd generic map (expand_type => expand_type) port map( + nclk => nclk , + vd => vdd , + gd => gnd , + act => binv2_ex2_stg_act , + delay_lclkr => delay_lclkr (1) , + mpw1_b => mpw1_b (1) , + mpw2_b => mpw2_b (1) , + forcee => forcee (1) , + sg => sg_0 (1) , + thold_b => thold_0_b (1) , + d1clk => dir_d1clk , + d2clk => dir_d2clk , + lclk => dir_lclk ); + + lmq_lcb : tri_lcbnd generic map (expand_type => expand_type) port map( + nclk => nclk , + vd => vdd , + gd => gnd , + act => lmq_entry_act , + delay_lclkr => delay_lclkr (2) , + mpw1_b => mpw1_b (2) , + mpw2_b => mpw2_b (2) , + forcee => forcee (2) , + sg => sg_0 (2) , + thold_b => thold_0_b (2) , + d1clk => lmq_d1clk , + d2clk => lmq_d2clk , + lclk => lmq_lclk ); + + + + + + ex3_erat_si(5) <= scan_in(0); + ex3_erat_si(0 to 4) <= ex3_erat_so(1 to 5); + scan_out(0) <= ex3_erat_so(0); + + dir0_si(0) <= scan_in(1); + dir0_si(1 to 30) <= dir0_so(0 to 29); + dir1_si(30) <= dir0_so(30) ; + dir1_si(0 to 29) <= dir1_so(1 to 30); + dir2_si(0) <= dir1_so(0) ; + dir2_si(1 to 30) <= dir2_so(0 to 29); + dir3_si(30) <= dir2_so(30) ; + dir3_si(0 to 29) <= dir3_so(1 to 30); + dir4_si(0) <= dir3_so(0) ; + dir4_si(1 to 30) <= dir4_so(0 to 29); + dir5_si(30) <= dir4_so(30) ; + dir5_si(0 to 29) <= dir5_so(1 to 30); + dir6_si(0) <= dir5_so(0) ; + dir6_si(1 to 30) <= dir6_so(0 to 29); + dir7_si(30) <= dir6_so(30) ; + dir7_si(0 to 29) <= dir7_so(1 to 30); + scan_out(1) <= dir7_so(0) ; + + lmq0_si(0) <= scan_in(2); + lmq0_si(1 to 35) <= lmq0_so(0 to 34); + lmq1_si(35) <= lmq0_so(35) ; + lmq1_si(0 to 34) <= lmq1_so(1 to 35); + lmq2_si(0) <= lmq1_so(0) ; + lmq2_si(1 to 35) <= lmq2_so(0 to 34); + lmq3_si(35) <= lmq2_so(35) ; + lmq3_si(0 to 34) <= lmq3_so(1 to 35); + lmq4_si(0) <= lmq3_so(0) ; + lmq4_si(1 to 35) <= lmq4_so(0 to 34); + lmq5_si(35) <= lmq4_so(35) ; + lmq5_si(0 to 34) <= lmq5_so(1 to 35); + lmq6_si(0) <= lmq5_so(0) ; + lmq6_si(1 to 35) <= lmq6_so(0 to 34); + lmq7_si(35) <= lmq6_so(35) ; + lmq7_si(0 to 34) <= lmq7_so(1 to 35); + scan_out(2) <= lmq7_so(0) ; + + +end; + + + + + + + + + + + + + + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_cmp_cmp31.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_cmp_cmp31.vhdl new file mode 100644 index 0000000..6412273 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_cmp_cmp31.vhdl @@ -0,0 +1,112 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + + + +LIBRARY ieee; USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY ibm; + USE ibm.std_ulogic_support.all; + USE ibm.std_ulogic_unsigned.all; + USE ibm.std_ulogic_function_support.all; +LIBRARY support; + USE support.power_logic_pkg.all; +LIBRARY tri; USE tri.tri_latches_pkg.all; +LIBRARY clib ; +-- pragma translate_off +LIBRARY latches ; +LIBRARY macros ; +-- pragma translate_on + + +entity xuq_lsu_cmp_cmp31 is +generic( expand_type: integer := 2 ); +port( + d0 :in std_ulogic_vector(0 to 30); + d1 :in std_ulogic_vector(0 to 30); + eq :out std_ulogic +); + + + + + +end xuq_lsu_cmp_cmp31; + +architecture xuq_lsu_cmp_cmp31 of xuq_lsu_cmp_cmp31 is + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal eq01 :std_ulogic_vector(0 to 30) ; + signal eq03_b : std_ulogic_vector(0 to 11); + signal eq06 : std_ulogic_vector(0 to 5); + signal eq18_b : std_ulogic_vector(0 to 1); + + + + + + + + +begin + + + u_eq01: eq01(0 to 30) <= not( d0(0 to 30) xor d1(0 to 30) ); + + u_eq03_00: eq03_b( 0) <= not( eq01( 0) and eq01( 1) and eq01( 2) ); + u_eq03_01: eq03_b( 1) <= not( eq01( 3) and eq01( 4) and eq01( 5) ); + u_eq03_02: eq03_b( 2) <= not( eq01( 6) and eq01( 7) and eq01( 8) ); + u_eq03_03: eq03_b( 3) <= not( eq01( 9) and eq01(10) and eq01(11) ); + u_eq03_04: eq03_b( 4) <= not( eq01(12) and eq01(13) and eq01(14) ); + u_eq03_05: eq03_b( 5) <= not( eq01(15) and eq01(16) and eq01(17) ); + u_eq03_06: eq03_b( 6) <= not( eq01(18) and eq01(19) and eq01(20) ); + u_eq03_07: eq03_b( 7) <= not( eq01(21) and eq01(22) ); + u_eq03_08: eq03_b( 8) <= not( eq01(23) and eq01(24) ); + u_eq03_09: eq03_b( 9) <= not( eq01(25) and eq01(26) ); + u_eq03_10: eq03_b(10) <= not( eq01(27) and eq01(28) ); + u_eq03_11: eq03_b(11) <= not( eq01(29) and eq01(30) ); + + u_eq06_00: eq06( 0) <= not( eq03_b( 0) or eq03_b( 1) ); + u_eq06_01: eq06( 1) <= not( eq03_b( 2) or eq03_b( 3) ); + u_eq06_02: eq06( 2) <= not( eq03_b( 4) or eq03_b( 5) ); + u_eq06_03: eq06( 3) <= not( eq03_b( 6) or eq03_b( 7) ); + u_eq06_04: eq06( 4) <= not( eq03_b( 8) or eq03_b( 9) ); + u_eq06_05: eq06( 5) <= not( eq03_b(10) or eq03_b(11) ); + + u_eq18_00: eq18_b( 0) <= not( eq06(0) and eq06(1) and eq06(2) ); + u_eq18_01: eq18_b( 1) <= not( eq06(3) and eq06(4) and eq06(5) ); + + u_eq36_00: eq <= not( eq18_b( 0) or eq18_b( 1) ); + + + +end; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_cmp_cmp36e.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_cmp_cmp36e.vhdl new file mode 100644 index 0000000..80fc701 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_cmp_cmp36e.vhdl @@ -0,0 +1,136 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + + + +LIBRARY ieee; USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY ibm; + USE ibm.std_ulogic_support.all; + USE ibm.std_ulogic_unsigned.all; + USE ibm.std_ulogic_function_support.all; +LIBRARY support; + USE support.power_logic_pkg.all; +LIBRARY tri; USE tri.tri_latches_pkg.all; +LIBRARY clib ; +-- pragma translate_off +LIBRARY latches ; +LIBRARY macros ; +-- pragma translate_on + + +entity xuq_lsu_cmp_cmp36e is +generic( expand_type: integer := 2 ); +port( + enable_lsb :in std_ulogic; + d0 :in std_ulogic_vector(0 to 35); + d1 :in std_ulogic_vector(0 to 35); + eq :out std_ulogic +); + + + + + +end xuq_lsu_cmp_cmp36e; + +architecture xuq_lsu_cmp_cmp36e of xuq_lsu_cmp_cmp36e is + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal eq01_b :std_ulogic_vector(0 to 35) ; + signal eq02 :std_ulogic_vector(0 to 18) ; + signal eq04_b :std_ulogic_vector(0 to 9); + signal eq08 :std_ulogic_vector(0 to 4); + signal eq24_b :std_ulogic_vector(0 to 1); + + + + + + + + + +begin + + + u_eq01: eq01_b(0 to 35) <= ( d0(0 to 35) xor d1(0 to 35) ); + + u_eq_00: eq02 ( 0) <= not( eq01_b( 0) or eq01_b( 1) ); + u_eq_02: eq02 ( 1) <= not( eq01_b( 2) or eq01_b( 3) ); + u_eq_04: eq02 ( 2) <= not( eq01_b( 4) or eq01_b( 5) ); + u_eq_06: eq02 ( 3) <= not( eq01_b( 6) or eq01_b( 7) ); + u_eq_08: eq02 ( 4) <= not( eq01_b( 8) or eq01_b( 9) ); + u_eq_10: eq02 ( 5) <= not( eq01_b(10) or eq01_b(11) ); + u_eq_12: eq02 ( 6) <= not( eq01_b(12) or eq01_b(13) ); + u_eq_14: eq02 ( 7) <= not( eq01_b(14) or eq01_b(15) ); + u_eq_16: eq02 ( 8) <= not( eq01_b(16) or eq01_b(17) ); + u_eq_18: eq02 ( 9) <= not( eq01_b(18) or eq01_b(19) ); + u_eq_20: eq02 (10) <= not( eq01_b(20) or eq01_b(21) ); + u_eq_22: eq02 (11) <= not( eq01_b(22) or eq01_b(23) ); + u_eq_24: eq02 (12) <= not( eq01_b(24) or eq01_b(25) ); + u_eq_26: eq02 (13) <= not( eq01_b(26) or eq01_b(27) ); + u_eq_28: eq02 (14) <= not( eq01_b(28) or eq01_b(29) ); + u_eq_30: eq02 (15) <= not( eq01_b(30) or eq01_b(31) ); + u_eq_31: eq02 (16) <= not( eq01_b(32) or eq01_b(33) ); + u_eq_33: eq02 (17) <= not( eq01_b(34) ); + u_eq_35: eq02 (18) <= not( eq01_b(35) and enable_lsb ); + + u_eq_01: eq04_b( 0) <= not( eq02 ( 0) and eq02 ( 1) ); + u_eq_05: eq04_b( 1) <= not( eq02 ( 2) and eq02 ( 3) ); + u_eq_09: eq04_b( 2) <= not( eq02 ( 4) and eq02 ( 5) ); + u_eq_13: eq04_b( 3) <= not( eq02 ( 6) and eq02 ( 7) ); + u_eq_17: eq04_b( 4) <= not( eq02 ( 8) and eq02 ( 9) ); + u_eq_21: eq04_b( 5) <= not( eq02 (10) and eq02 (11) ); + u_eq_25: eq04_b( 6) <= not( eq02 (12) and eq02 (13) ); + u_eq_29: eq04_b( 7) <= not( eq02 (14) and eq02 (15) ); + u_eq_32: eq04_b( 8) <= not( eq02 (16) and eq02 (17) ); + u_eq_36: eq04_b( 9) <= not( eq02 (18) ); + + u_eq_03: eq08 ( 0) <= not( eq04_b( 0) or eq04_b( 1) ); + u_eq_11: eq08 ( 1) <= not( eq04_b( 2) or eq04_b( 3) ); + u_eq_19: eq08 ( 2) <= not( eq04_b( 4) or eq04_b( 5) ); + u_eq_27: eq08 ( 3) <= not( eq04_b( 6) or eq04_b( 7) ); + u_eq_34: eq08 ( 4) <= not( eq04_b( 8) or eq04_b( 9) ); + + u_eq_07: eq24_b( 0) <= not( eq08 ( 0) and eq08 ( 1) and eq08 ( 2) ); + u_eq_23: eq24_b( 1) <= not( eq08 ( 3) and eq08 ( 4) ); + + u_eq_15: eq <= not( eq24_b( 0) or eq24_b( 1) ); + + + + + +end; + + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_data.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_data.vhdl new file mode 100644 index 0000000..dc0fe54 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_data.vhdl @@ -0,0 +1,4205 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ibm, ieee, work, tri, support; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use tri.tri_latches_pkg.all; +use support.power_logic_pkg.all; + +entity xuq_lsu_data is +generic(expand_type : integer := 2; + regmode : integer := 6; + dc_size : natural := 14; + cl_size : natural := 6; + l_endian_m : integer := 1); +port( + + xu_lsu_rf1_data_act :in std_ulogic; + xu_lsu_rf1_axu_ldst_falign :in std_ulogic; + xu_lsu_ex1_store_data :in std_ulogic_vector(64-(2**REGMODE) to 63); + xu_lsu_ex1_eff_addr :in std_ulogic_vector(64-(dc_size-3) to 63); + xu_lsu_ex1_rotsel_ovrd :in std_ulogic_vector(0 to 4); + ex1_optype32 :in std_ulogic; + ex1_optype16 :in std_ulogic; + ex1_optype8 :in std_ulogic; + ex1_optype4 :in std_ulogic; + ex1_optype2 :in std_ulogic; + ex1_optype1 :in std_ulogic; + ex1_store_instr :in std_ulogic; + ex1_axu_op_val :in std_ulogic; + ex1_saxu_instr :in std_ulogic; + ex1_sdp_instr :in std_ulogic; + ex1_stgpr_instr :in std_ulogic; + + fu_xu_ex2_store_data_val :in std_ulogic; + fu_xu_ex2_store_data :in std_ulogic_vector(0 to 255); + + ex3_algebraic :in std_ulogic; + ex3_data_swap :in std_ulogic; + ex3_thrd_id :in std_ulogic_vector(0 to 3); + ex5_dp_data :in std_ulogic_vector(0 to 127); + + ex4_load_op_hit :in std_ulogic; + ex4_store_hit :in std_ulogic; + ex4_axu_op_val :in std_ulogic; + spr_dvc1_act :in std_ulogic; + spr_dvc2_act :in std_ulogic; + spr_dvc1_dbg :in std_ulogic_vector(64-(2**regmode) to 63); + spr_dvc2_dbg :in std_ulogic_vector(64-(2**regmode) to 63); + + rel_upd_dcarr_val :in std_ulogic; + + xu_lsu_ex4_flush :in std_ulogic_vector(0 to 3); + xu_lsu_ex4_flush_local :in std_ulogic_vector(0 to 3); + xu_lsu_ex5_flush :in std_ulogic_vector(0 to 3); + + xu_pc_err_dcache_parity :out std_ulogic; + pc_xu_inj_dcache_parity :in std_ulogic; + + xu_lsu_spr_xucr0_dcdis :in std_ulogic; + spr_xucr0_clkg_ctl_b0 :in std_ulogic; + + ldq_rel_data_val_early :in std_ulogic; + ldq_rel_algebraic :in std_ulogic; + ldq_rel_data_val :in std_ulogic; + ldq_rel_ci :in std_ulogic; + ldq_rel_thrd_id :in std_ulogic_vector(0 to 3); + ldq_rel_axu_val :in std_ulogic; + ldq_rel_data :in std_ulogic_vector(0 to 255); + ldq_rel_rot_sel :in std_ulogic_vector(0 to 4); + ldq_rel_op_size :in std_ulogic_vector(0 to 5); + ldq_rel_le_mode :in std_ulogic; + ldq_rel_dvc1_en :in std_ulogic; + ldq_rel_dvc2_en :in std_ulogic; + ldq_rel_beat_crit_qw :in std_ulogic; + ldq_rel_beat_crit_qw_block :in std_ulogic; + ldq_rel_addr :in std_ulogic_vector(64-(dc_size-3) to 58); + + dcarr_up_way_addr :in std_ulogic_vector(0 to 2); + + ex4_256st_data :out std_ulogic_vector(0 to 255); + ex6_ld_par_err :out std_ulogic; + lsu_xu_ex6_datc_par_err :out std_ulogic; + + ex6_xu_ld_data_b :out std_ulogic_vector(64-(2**regmode) to 63); + rel_xu_ld_data :out std_ulogic_vector(64-(2**regmode) to 64+((2**regmode)/8)-1); + xu_fu_ex6_load_data :out std_ulogic_vector(0 to 255); + xu_fu_ex5_load_le :out std_ulogic; + + lsu_xu_rel_dvc_thrd_id :out std_ulogic_vector(0 to 3); + lsu_xu_ex2_dvc1_st_cmp :out std_ulogic_vector(0 to ((2**regmode)/8)-1); + lsu_xu_ex8_dvc1_ld_cmp :out std_ulogic_vector(0 to ((2**regmode)/8)-1); + lsu_xu_rel_dvc1_en :out std_ulogic; + lsu_xu_rel_dvc1_cmp :out std_ulogic_vector(0 to ((2**regmode)/8)-1); + lsu_xu_ex2_dvc2_st_cmp :out std_ulogic_vector(0 to ((2**regmode)/8)-1); + lsu_xu_ex8_dvc2_ld_cmp :out std_ulogic_vector(0 to ((2**regmode)/8)-1); + lsu_xu_rel_dvc2_en :out std_ulogic; + lsu_xu_rel_dvc2_cmp :out std_ulogic_vector(0 to ((2**regmode)/8)-1); + + pc_xu_trace_bus_enable :in std_ulogic; + lsudat_debug_mux_ctrls :in std_ulogic_vector(0 to 1); + lsu_xu_data_debug0 :out std_ulogic_vector(0 to 87); + lsu_xu_data_debug1 :out std_ulogic_vector(0 to 87); + lsu_xu_data_debug2 :out std_ulogic_vector(0 to 87); + + vdd :inout power_logic; + gnd :inout power_logic; + vcs :inout power_logic; + nclk :in clk_logic; + pc_xu_ccflush_dc :in std_ulogic; + sg_2 :in std_ulogic; + fce_2 :in std_ulogic; + func_sl_thold_2 :in std_ulogic; + func_nsl_thold_2 :in std_ulogic; + clkoff_dc_b :in std_ulogic; + d_mode_dc :in std_ulogic; + delay_lclkr_dc :in std_ulogic_vector(5 to 5); + mpw1_dc_b :in std_ulogic_vector(5 to 5); + mpw2_dc_b :in std_ulogic; + g6t_clkoff_dc_b :in std_ulogic; + g6t_d_mode_dc :in std_ulogic; + g6t_delay_lclkr_dc :in std_ulogic_vector(0 to 4); + g6t_mpw1_dc_b :in std_ulogic_vector(0 to 4); + g6t_mpw2_dc_b :in std_ulogic; + abst_sl_thold_2 :in std_ulogic; + time_sl_thold_2 :in std_ulogic; + ary_nsl_thold_2 :in std_ulogic; + repr_sl_thold_2 :in std_ulogic; + bolt_sl_thold_2 :in std_ulogic; + bo_enable_2 :in std_ulogic; + an_ac_scan_dis_dc_b :in std_ulogic; + an_ac_scan_diag_dc :in std_ulogic; + + an_ac_lbist_ary_wrt_thru_dc :in std_ulogic; + pc_xu_abist_ena_dc :in std_ulogic; + pc_xu_abist_g6t_bw :in std_ulogic_vector(0 to 1); + pc_xu_abist_di_g6t_2r :in std_ulogic_vector(0 to 3); + pc_xu_abist_wl512_comp_ena :in std_ulogic; + pc_xu_abist_raw_dc_b :in std_ulogic; + pc_xu_abist_dcomp_g6t_2r :in std_ulogic_vector(0 to 3); + pc_xu_abist_raddr_0 :in std_ulogic_vector(1 to 9); + pc_xu_abist_g6t_r_wb :in std_ulogic; + pc_xu_bo_unload :in std_ulogic; + pc_xu_bo_repair :in std_ulogic; + pc_xu_bo_reset :in std_ulogic; + pc_xu_bo_shdata :in std_ulogic; + pc_xu_bo_select :in std_ulogic_vector(5 to 6); + xu_pc_bo_fail :out std_ulogic_vector(5 to 6); + xu_pc_bo_diagout :out std_ulogic_vector(5 to 6); + + abst_scan_in :in std_ulogic_vector(0 to 1); + time_scan_in :in std_ulogic; + repr_scan_in :in std_ulogic; + abst_scan_out :out std_ulogic_vector(0 to 1); + time_scan_out :out std_ulogic; + repr_scan_out :out std_ulogic; + func_scan_in :in std_ulogic_vector(0 to 2); + func_scan_out :out std_ulogic_vector(0 to 2) +); +-- synopsys translate_off + + +-- synopsys translate_on + +end xuq_lsu_data; +architecture xuq_lsu_data of xuq_lsu_data is + + +constant rot_max_size :std_ulogic_vector(0 to 5) := "100000"; +constant byte16_size :std_ulogic_vector(0 to 5) := "010000"; +constant uprCClassBit :natural := 64-(dc_size-3); +constant lwrCClassBit :natural := 63-cl_size; + +constant ex3_opsize_offset :natural := 0; +constant ex3_ovrd_rot_offset :natural := ex3_opsize_offset + 6; +constant ex4_le_mode_sel_offset :natural := ex3_ovrd_rot_offset + 1; +constant ex4_be_mode_sel_offset :natural := ex4_le_mode_sel_offset + 16; +constant ex5_load_hit_offset :natural := ex4_be_mode_sel_offset + 16; +constant ex7_load_hit_offset :natural := ex5_load_hit_offset + 1; +constant ex2_st_data_offset :natural := ex7_load_hit_offset + 1; +constant axu_rel_upd_offset :natural := ex2_st_data_offset + (2**regmode); +constant rel_data_val_offset :natural := axu_rel_upd_offset + 16; +constant rel_addr_stg_offset :natural := rel_data_val_offset + 16; +constant rel_addr_offset :natural := rel_addr_stg_offset + 58-uprCClassBit+1; +constant ex5_axu_data_sel_offset :natural := rel_addr_offset + 58-uprCClassBit+1; +constant ex3_stgpr_instr_offset :natural := ex5_axu_data_sel_offset + 3; +constant ex4_stgpr_instr_offset :natural := ex3_stgpr_instr_offset + 1; +constant ex3_sdp_instr_offset :natural := ex4_stgpr_instr_offset + 1; +constant ex4_sdp_instr_offset :natural := ex3_sdp_instr_offset + 1; +constant ex5_sdp_instr_offset :natural := ex4_sdp_instr_offset + 1; +constant rot_addr_offset :natural := ex5_sdp_instr_offset + 1; +constant rot_sel_non_le_offset :natural := rot_addr_offset + 5; +constant ex5_dvc1_en_offset :natural := rot_sel_non_le_offset + 5; +constant ex6_dvc1_en_offset :natural := ex5_dvc1_en_offset + 1; +constant ex7_dvc1_en_offset :natural := ex6_dvc1_en_offset + 1; +constant rel_dvc1_val_offset :natural := ex7_dvc1_en_offset + ((2**regmode)/8); +constant ex8_ld_dvc1_cmp_offset :natural := rel_dvc1_val_offset + 1; +constant rel_dvc1_val_stg_offset :natural := ex8_ld_dvc1_cmp_offset + ((2**regmode)/8); +constant rel_dvc1_val_stg2_offset :natural := rel_dvc1_val_stg_offset + 1; +constant rel_dvc2_val_stg_offset :natural := rel_dvc1_val_stg2_offset + 1; +constant rel_dvc2_val_stg2_offset :natural := rel_dvc2_val_stg_offset + 1; +constant ex5_dvc2_en_offset :natural := rel_dvc2_val_stg2_offset + 1; +constant ex6_dvc2_en_offset :natural := ex5_dvc2_en_offset + 1; +constant ex7_dvc2_en_offset :natural := ex6_dvc2_en_offset + 1; +constant rel_dvc2_val_offset :natural := ex7_dvc2_en_offset + ((2**regmode)/8); +constant ex8_ld_dvc2_cmp_offset :natural := rel_dvc2_val_offset + 1; +constant ex2_optype32_offset :natural := ex8_ld_dvc2_cmp_offset + ((2**regmode)/8); +constant ex2_optype16_offset :natural := ex2_optype32_offset + 1; +constant ex2_optype8_offset :natural := ex2_optype16_offset + 1; +constant ex2_optype4_offset :natural := ex2_optype8_offset + 1; +constant ex2_optype2_offset :natural := ex2_optype4_offset + 1; +constant ex2_optype1_offset :natural := ex2_optype2_offset + 1; +constant ex2_p_addr_offset :natural := ex2_optype1_offset + 1; +constant frc_p_addr_offset :natural := ex2_p_addr_offset + 64-uprCClassBit; +constant ex2_store_instr_offset :natural := frc_p_addr_offset + 6; +constant ex2_axu_op_val_offset :natural := ex2_store_instr_offset + 1; +constant ex4_axu_op_val_offset :natural := ex2_axu_op_val_offset + 1; +constant ex2_xu_cmp_val_offset :natural := ex4_axu_op_val_offset + 1; +constant ex2_saxu_instr_offset :natural := ex2_xu_cmp_val_offset + (2**regmode)/8; +constant ex2_sdp_instr_offset :natural := ex2_saxu_instr_offset + 1; +constant ex2_stgpr_instr_offset :natural := ex2_sdp_instr_offset + 1; +constant ex4_saxu_instr_offset :natural := ex2_stgpr_instr_offset + 1; +constant ex4_algebraic_offset :natural := ex4_saxu_instr_offset + 1; +constant ex2_ovrd_rot_sel_offset :natural := ex4_algebraic_offset + 1; +constant ex4_p_addr_offset :natural := ex2_ovrd_rot_sel_offset + 5; +constant spr_xucr0_dcdis_offset :natural := ex4_p_addr_offset + 64-uprCClassBit; +constant clkg_ctl_override_offset :natural := spr_xucr0_dcdis_offset + 1; +constant rel_dvc_tid_stg_offset :natural := clkg_ctl_override_offset + 1; +constant inj_dcache_parity_offset :natural := rel_dvc_tid_stg_offset + 4; +constant ex5_stgpr_dp_instr_offset :natural := inj_dcache_parity_offset + 1; +constant ex6_stgpr_dp_instr_offset :natural := ex5_stgpr_dp_instr_offset + 1; +constant ex6_stgpr_dp_data_offset :natural := ex6_stgpr_dp_instr_offset + 1; +constant ex5_rel_le_mode_offset :natural := ex6_stgpr_dp_data_offset + 128; +constant ex1_ldst_falign_offset :natural := ex5_rel_le_mode_offset + 1; +constant ex5_thrd_id_offset :natural := ex1_ldst_falign_offset + 1; +constant axu_rel_val_stg1_offset :natural := ex5_thrd_id_offset + 4; +constant axu_rel_val_stg2_offset :natural := axu_rel_val_stg1_offset + 1; +constant axu_rel_val_stg3_offset :natural := axu_rel_val_stg2_offset + 1; +constant rel_256ld_data_stg2_offset :natural := axu_rel_val_stg3_offset + 1; +constant rel_axu_le_val_offset :natural := rel_256ld_data_stg2_offset + 256; +constant rel_axu_le_val_stg1_offset :natural := rel_axu_le_val_offset + 1; +constant dcarr_wren_offset :natural := rel_axu_le_val_stg1_offset + 1; +constant dat_dbg_arr_offset :natural := dcarr_wren_offset + 1; +constant ld_alg_le_sel_offset :natural := dat_dbg_arr_offset + 13; +constant ex1_stg_act_offset :natural := ld_alg_le_sel_offset + 5; +constant ex2_stg_act_offset :natural := ex1_stg_act_offset + 1; +constant ex3_stg_act_offset :natural := ex2_stg_act_offset + 1; +constant ex4_stg_act_offset :natural := ex3_stg_act_offset + 1; +constant ex5_stg_act_offset :natural := ex4_stg_act_offset + 1; +constant ex6_stg_act_offset :natural := ex5_stg_act_offset + 1; +constant rel1_stg_act_offset :natural := ex6_stg_act_offset + 1; +constant rel2_stg_act_offset :natural := rel1_stg_act_offset + 1; +constant rel3_stg_act_offset :natural := rel2_stg_act_offset + 1; +constant rel4_stg_act_offset :natural := rel3_stg_act_offset + 1; +constant rel5_stg_act_offset :natural := rel4_stg_act_offset + 1; +constant rel2_ex2_stg_act_offset :natural := rel5_stg_act_offset + 1; +constant rel3_ex3_stg_act_offset :natural := rel2_ex2_stg_act_offset + 1; +constant rel4_ex4_stg_act_offset :natural := rel3_ex3_stg_act_offset + 1; +constant ex8_ld_par_err_offset :natural := rel4_ex4_stg_act_offset + 1; +constant my_spare_latches_offset :natural := ex8_ld_par_err_offset + 1; +constant scan_right0 :natural := my_spare_latches_offset + 8 - 1; +constant l1dcar_offset :natural := 0; +constant l1dcld_offset :natural := l1dcar_offset + 1; +constant rel_data_offset :natural := l1dcld_offset + 1; +constant rel_algebraic_offset :natural := rel_data_offset + 256; +constant rel_rot_sel_offset :natural := rel_algebraic_offset + 1; +constant rel_op_size_offset :natural := rel_rot_sel_offset + 5; +constant rel_le_mode_offset :natural := rel_op_size_offset + 6; +constant rel_dvc1_en_offset :natural := rel_le_mode_offset + 1; +constant rel_dvc2_en_offset :natural := rel_dvc1_en_offset + 1; +constant rel_upd_gpr_offset :natural := rel_dvc2_en_offset + 1; +constant rel_axu_val_offset :natural := rel_upd_gpr_offset + 1; +constant rel_ci_offset :natural := rel_axu_val_offset + 1; +constant rel_thrd_id_offset :natural := rel_ci_offset + 1; +constant rel_data_val_stg_offset :natural := rel_thrd_id_offset + 4; +constant spr_dvc1_dbg_offset :natural := rel_data_val_stg_offset + 1; +constant spr_dvc2_dbg_offset :natural := spr_dvc1_dbg_offset + (2**regmode); +constant trace_bus_enable_offset :natural := spr_dvc2_dbg_offset + (2**regmode); +constant dat_debug_mux_ctrls_offset :natural := trace_bus_enable_offset + 1; +constant dat_dbg_st_dat_offset :natural := dat_debug_mux_ctrls_offset + 2; +constant scan_right1 :natural := dat_dbg_st_dat_offset + 64 - 1; + +signal op_size :std_ulogic_vector(0 to 5); +signal ex3_opsize_d :std_ulogic_vector(0 to 5); +signal ex3_opsize_q :std_ulogic_vector(0 to 5); +signal rot_addr :std_ulogic_vector(0 to 5); +signal rot_addr_le :std_ulogic_vector(0 to 5); +signal rot_size :std_ulogic_vector(0 to 5); +signal rot_size_le :std_ulogic_vector(0 to 5); +signal ex3_le_mode :std_ulogic; +signal ex3_be_mode :std_ulogic; +signal ex4_le_mode_d :std_ulogic; +signal ex4_le_mode_q :std_ulogic; +signal ex4_le_mode_sel_d :std_ulogic_vector(0 to 15); +signal ex4_le_mode_sel_q :std_ulogic_vector(0 to 15); +signal ex4_be_mode_sel_d :std_ulogic_vector(0 to 15); +signal ex4_be_mode_sel_q :std_ulogic_vector(0 to 15); +signal st_256data :std_ulogic_vector(0 to 255); +signal ex3_byte_en :std_ulogic_vector(0 to 31); +signal ex5_ld_data :std_ulogic_vector(0 to 255); +signal ex5_ld_data_par :std_ulogic_vector(0 to 31); +signal ex6_par_chk_val :std_ulogic; +signal ex2_st_data_fixup :std_ulogic_vector(0 to 127); +signal ex2_st_data_d :std_ulogic_vector(64-(2**regmode) to 63); +signal ex2_st_data_q :std_ulogic_vector(64-(2**regmode) to 63); +signal fu_ex2_store_data_val :std_ulogic; +signal fu_ex2_store_data :std_ulogic_vector(0 to 255); +signal rel_256ld_data :std_ulogic_vector(0 to 255); +signal rel_64ld_data :std_ulogic_vector(64-(2**regmode) to 63); +signal axu_rel_upd_d :std_ulogic_vector(0 to 15); +signal axu_rel_upd_q :std_ulogic_vector(0 to 15); +signal ex6_rot_sel :std_ulogic_vector(0 to 31); +signal rot_sel_non_le :std_ulogic_vector(0 to 5); +signal be_st_rot_sel :std_ulogic_vector(1 to 5); +signal le_st_rot_sel :std_ulogic_vector(0 to 3); +signal ex4_ld_rot_sel :std_ulogic_vector(1 to 5); +signal st_ovrd_rot_sel :std_ulogic_vector(0 to 4); +signal ex3_st_rot_sel_d :std_ulogic_vector(0 to 4); +signal ex3_st_rot_sel_q :std_ulogic_vector(0 to 4); +signal rel_algebraic :std_ulogic; +signal rel_data :std_ulogic_vector(0 to 255); +signal rel_data_val :std_ulogic_vector(0 to 15); +signal rel_upd_gpr_d :std_ulogic; +signal rel_upd_gpr_q :std_ulogic; +signal rel_rot_sel :std_ulogic_vector(0 to 4); +signal rel_op_size :std_ulogic_vector(0 to 5); +signal rel_le_mode :std_ulogic; +signal rel_algebraic_d :std_ulogic; +signal rel_data_val_d :std_ulogic_vector(0 to 15); +signal rel_data_d :std_ulogic_vector(0 to 255); +signal rel_rot_sel_d :std_ulogic_vector(0 to 4); +signal rel_op_size_d :std_ulogic_vector(0 to 5); +signal rel_le_mode_d :std_ulogic; +signal rel_addr_d :std_ulogic_vector(uprCClassBit to 58); +signal rel_algebraic_q :std_ulogic; +signal rel_data_val_q :std_ulogic_vector(0 to 15); +signal rel_data_q :std_ulogic_vector(0 to 255); +signal rel_rot_sel_q :std_ulogic_vector(0 to 4); +signal rel_op_size_q :std_ulogic_vector(0 to 5); +signal rel_le_mode_q :std_ulogic; +signal rel_addr_q :std_ulogic_vector(uprCClassBit to 58); +signal rel_xu_ld_par :std_ulogic_vector(0 to 7); +signal rel_ex2_data :std_ulogic_vector(0 to 255); +signal rel_ex3_data_d :std_ulogic_vector(0 to 255); +signal rel_ex3_data_q :std_ulogic_vector(0 to 255); +signal rel_addr_stg_d :std_ulogic_vector(uprCClassBit to 58); +signal rel_addr_stg_q :std_ulogic_vector(uprCClassBit to 58); +signal rel_data_val_stg_d :std_ulogic; +signal rel_data_val_stg_q :std_ulogic; +signal rel_data_val_stg_dly_d :std_ulogic; +signal rel_data_val_stg_dly_q :std_ulogic; +signal ex4_parity_gen :std_ulogic_vector(0 to 31); +signal non_le_byte_bit0 :std_ulogic_vector(0 to 31); +signal le_byte_bit0 :std_ulogic_vector(0 to 31); +signal alg_bit_sel :std_ulogic_vector(0 to 4); +signal alg_byte :std_ulogic_vector(0 to 31); +signal algebraic_bit :std_ulogic; +signal rel_alg_bit_d :std_ulogic; +signal rel_alg_bit_q :std_ulogic; +signal ex2_ovrd_rot :std_ulogic; +signal ex3_ovrd_rot_d :std_ulogic; +signal ex3_ovrd_rot_q :std_ulogic; +signal ex3_sdp_instr_d :std_ulogic; +signal ex3_sdp_instr_q :std_ulogic; +signal ex4_sdp_instr_d :std_ulogic; +signal ex4_sdp_instr_q :std_ulogic; +signal ex5_sdp_instr_d :std_ulogic; +signal ex5_sdp_instr_q :std_ulogic; +signal ex3_stgpr_instr_d :std_ulogic; +signal ex3_stgpr_instr_q :std_ulogic; +signal ex4_stgpr_instr_d :std_ulogic; +signal ex4_stgpr_instr_q :std_ulogic; +signal ex5_stgpr_dp_instr_d :std_ulogic; +signal ex5_stgpr_dp_instr_q :std_ulogic; +signal ex6_stgpr_dp_instr_d :std_ulogic; +signal ex6_stgpr_dp_instr_q :std_ulogic; +signal ex6_stgpr_dp_instr_q_b :std_ulogic; +signal ex4_stgpr_data :std_ulogic_vector(64-(2**regmode) to 63); +signal ex5_stgpr_data_d :std_ulogic_vector(64-(2**regmode) to 63); +signal ex5_stgpr_data_q :std_ulogic_vector(64-(2**regmode) to 63); +signal ex6_stgpr_dp_data_d :std_ulogic_vector(0 to 127); +signal ex6_stgpr_dp_data_q :std_ulogic_vector(0 to 127); +signal rel_axu_le_mode :std_ulogic; +signal rot_addr_d :std_ulogic_vector(1 to 5); +signal rot_addr_q :std_ulogic_vector(1 to 5); +signal ex4_rot_addr_d :std_ulogic_vector(1 to 5); +signal ex4_rot_addr_q :std_ulogic_vector(1 to 5); +signal rot_sel_non_le_d :std_ulogic_vector(1 to 5); +signal rot_sel_non_le_q :std_ulogic_vector(1 to 5); +signal ex4_rot_sel_non_le_d :std_ulogic_vector(1 to 5); +signal ex4_rot_sel_non_le_q :std_ulogic_vector(1 to 5); +signal rel_axu_val_d :std_ulogic; +signal rel_axu_val_q :std_ulogic; +signal rel_ci_d :std_ulogic; +signal rel_ci_q :std_ulogic; +signal rel_ci_dly_d :std_ulogic; +signal rel_ci_dly_q :std_ulogic; +signal ex2_st_dvc1_cmp_d :std_ulogic_vector((64-(2**regmode))/8 to 7); +signal ex2_st_dvc1_cmp_q :std_ulogic_vector((64-(2**regmode))/8 to 7); +signal ex2_st_dvc2_cmp_d :std_ulogic_vector((64-(2**regmode))/8 to 7); +signal ex2_st_dvc2_cmp_q :std_ulogic_vector((64-(2**regmode))/8 to 7); +signal ex8_ld_dvc1_cmp_d :std_ulogic_vector((64-(2**regmode))/8 to 7); +signal ex8_ld_dvc1_cmp_q :std_ulogic_vector((64-(2**regmode))/8 to 7); +signal ex8_ld_dvc2_cmp_d :std_ulogic_vector((64-(2**regmode))/8 to 7); +signal ex8_ld_dvc2_cmp_q :std_ulogic_vector((64-(2**regmode))/8 to 7); +signal rel_dvc1_cmp_d :std_ulogic_vector((64-(2**regmode))/8 to 7); +signal rel_dvc1_cmp_q :std_ulogic_vector((64-(2**regmode))/8 to 7); +signal rel_dvc2_cmp_d :std_ulogic_vector((64-(2**regmode))/8 to 7); +signal rel_dvc2_cmp_q :std_ulogic_vector((64-(2**regmode))/8 to 7); +signal rel_dvc1_val_stg_d :std_ulogic; +signal rel_dvc1_val_stg_q :std_ulogic; +signal rel_dvc1_val_stg2_d :std_ulogic; +signal rel_dvc1_val_stg2_q :std_ulogic; +signal rel_dvc2_val_stg_d :std_ulogic; +signal rel_dvc2_val_stg_q :std_ulogic; +signal rel_dvc2_val_stg2_d :std_ulogic; +signal rel_dvc2_val_stg2_q :std_ulogic; +signal ex5_dvc1_en_d :std_ulogic; +signal ex5_dvc1_en_q :std_ulogic; +signal ex6_dvc1_en_d :std_ulogic; +signal ex6_dvc1_en_q :std_ulogic; +signal ex7_dvc1_en_d :std_ulogic_vector((64-(2**regmode))/8 to 7); +signal ex7_dvc1_en_q :std_ulogic_vector((64-(2**regmode))/8 to 7); +signal ex5_dvc2_en_d :std_ulogic; +signal ex5_dvc2_en_q :std_ulogic; +signal ex6_dvc2_en_d :std_ulogic; +signal ex6_dvc2_en_q :std_ulogic; +signal ex7_dvc2_en_d :std_ulogic_vector((64-(2**regmode))/8 to 7); +signal ex7_dvc2_en_q :std_ulogic_vector((64-(2**regmode))/8 to 7); +signal rel_dvc1_en_d :std_ulogic; +signal rel_dvc1_en_q :std_ulogic; +signal rel_dvc2_en_d :std_ulogic; +signal rel_dvc2_en_q :std_ulogic; +signal rel_dvc1_val_d :std_ulogic; +signal rel_dvc1_val_q :std_ulogic; +signal rel_dvc2_val_d :std_ulogic; +signal rel_dvc2_val_q :std_ulogic; +signal ex1_op_size :std_ulogic_vector(2 to 5); +signal ex1_st_byte_mask :std_ulogic_vector(0 to 7); +signal ex2_optype32_d :std_ulogic; +signal ex2_optype32_q :std_ulogic; +signal ex2_optype16_d :std_ulogic; +signal ex2_optype16_q :std_ulogic; +signal ex2_optype8_d :std_ulogic; +signal ex2_optype8_q :std_ulogic; +signal ex2_optype4_d :std_ulogic; +signal ex2_optype4_q :std_ulogic; +signal ex2_optype2_d :std_ulogic; +signal ex2_optype2_q :std_ulogic; +signal ex2_optype1_d :std_ulogic; +signal ex2_optype1_q :std_ulogic; +signal ex2_p_addr_d :std_ulogic_vector(uprCClassBit to 63); +signal ex2_p_addr_q :std_ulogic_vector(uprCClassBit to 63); +signal ex3_fu_st_val_d :std_ulogic; +signal ex3_fu_st_val_q :std_ulogic; +signal frc_p_addr_d :std_ulogic_vector(58 to 63); +signal frc_p_addr_q :std_ulogic_vector(58 to 63); +signal ex2_store_instr_d :std_ulogic; +signal ex2_store_instr_q :std_ulogic; +signal ex3_store_instr_d :std_ulogic; +signal ex3_store_instr_q :std_ulogic; +signal ex2_axu_op_val_d :std_ulogic; +signal ex2_axu_op_val_q :std_ulogic; +signal ex3_axu_op_val_d :std_ulogic; +signal ex3_axu_op_val_q :std_ulogic; +signal ex4_axu_op_val_d :std_ulogic; +signal ex4_axu_op_val_q :std_ulogic; +signal ex2_xu_cmp_val_d :std_ulogic_vector((64-(2**regmode))/8 to 7); +signal ex2_xu_cmp_val_q :std_ulogic_vector((64-(2**regmode))/8 to 7); +signal ex2_saxu_instr_d :std_ulogic; +signal ex2_saxu_instr_q :std_ulogic; +signal ex2_sdp_instr_d :std_ulogic; +signal ex2_sdp_instr_q :std_ulogic; +signal ex2_stgpr_instr_d :std_ulogic; +signal ex2_stgpr_instr_q :std_ulogic; +signal ex3_saxu_instr_d :std_ulogic; +signal ex3_saxu_instr_q :std_ulogic; +signal ex4_saxu_instr_d :std_ulogic; +signal ex4_saxu_instr_q :std_ulogic; +signal ex4_algebraic_d :std_ulogic; +signal ex4_algebraic_q :std_ulogic; +signal ex2_ovrd_rot_sel_d :std_ulogic_vector(0 to 4); +signal ex2_ovrd_rot_sel_q :std_ulogic_vector(0 to 4); +signal ex3_p_addr_d :std_ulogic_vector(uprCClassBit to 63); +signal ex3_p_addr_q :std_ulogic_vector(uprCClassBit to 63); +signal ex4_p_addr_d :std_ulogic_vector(uprCClassBit to 63); +signal ex4_p_addr_q :std_ulogic_vector(uprCClassBit to 63); +signal rel_ex2_par_gen :std_ulogic_vector(0 to 31); +signal rel_ex3_par_gen_d :std_ulogic_vector(0 to 31); +signal rel_ex3_par_gen_q :std_ulogic_vector(0 to 31); +signal ex2_fu_data_val :std_ulogic; +signal rel_xu_data :std_ulogic_vector(0 to 255); +signal spr_xucr0_dcdis_d :std_ulogic; +signal spr_xucr0_dcdis_q :std_ulogic; +signal clkg_ctl_override_d :std_ulogic; +signal clkg_ctl_override_q :std_ulogic; +signal rel_data_val_wren :std_ulogic; +signal rel_thrd_id_d :std_ulogic_vector(0 to 3); +signal rel_thrd_id_q :std_ulogic_vector(0 to 3); +signal rel_dvc_thrd_id_d :std_ulogic_vector(0 to 3); +signal rel_dvc_thrd_id_q :std_ulogic_vector(0 to 3); +signal rel_dvc_tid_stg_d :std_ulogic_vector(0 to 3); +signal rel_dvc_tid_stg_q :std_ulogic_vector(0 to 3); +signal rel_dvc_tid_stg2_d :std_ulogic_vector(0 to 3); +signal rel_dvc_tid_stg2_q :std_ulogic_vector(0 to 3); +signal dont_do_this :std_ulogic_vector(0 to 63); +signal ex6_xld_data :std_ulogic_vector(0 to 63); +signal ex6_xld_data_b :std_ulogic_vector(0 to 63); +signal ex6_ld_alg_bit :std_ulogic_vector(0 to 5); +signal ex6_ld_dvc_byte_mask :std_ulogic_vector((64-(2**regmode))/8 to 7); +signal ld_swzl_data :std_ulogic_vector(0 to 255); +signal axu_data_sel :std_ulogic_vector(0 to 1); +signal ex5_axu_data_sel_d :std_ulogic_vector(0 to 2); +signal ex5_axu_data_sel_q :std_ulogic_vector(0 to 2); +signal ex6_axu_data_sel_d :std_ulogic_vector(0 to 47); +signal ex6_axu_data_sel_q :std_ulogic_vector(0 to 47); +signal inj_dcache_parity_d :std_ulogic; +signal inj_dcache_parity_q :std_ulogic; +signal ex5_rel_le_mode_d :std_ulogic; +signal ex5_rel_le_mode_q :std_ulogic; +signal ex1_ldst_falign_d :std_ulogic; +signal ex1_ldst_falign_q :std_ulogic; +signal ex1_frc_align32 :std_ulogic; +signal ex1_frc_align16 :std_ulogic; +signal ex1_frc_align8 :std_ulogic; +signal ex1_frc_align4 :std_ulogic; +signal ex1_frc_align2 :std_ulogic; +signal ex4_stg_flush :std_ulogic; +signal ex5_stg_flush :std_ulogic; +signal ex4_load_hit :std_ulogic; +signal ex5_load_hit_d :std_ulogic; +signal ex5_load_hit_q :std_ulogic; +signal ex6_load_hit_d :std_ulogic; +signal ex6_load_hit_q :std_ulogic; +signal ex7_load_hit_d :std_ulogic; +signal ex7_load_hit_q :std_ulogic; +signal ex4_thrd_id_d :std_ulogic_vector(0 to 3); +signal ex4_thrd_id_q :std_ulogic_vector(0 to 3); +signal ex5_thrd_id_d :std_ulogic_vector(0 to 3); +signal ex5_thrd_id_q :std_ulogic_vector(0 to 3); +signal axu_rel_val_stg1_d :std_ulogic; +signal axu_rel_val_stg1_q :std_ulogic; +signal axu_rel_val_stg2_d :std_ulogic; +signal axu_rel_val_stg2_q :std_ulogic; +signal axu_rel_val_stg3_d :std_ulogic; +signal axu_rel_val_stg3_q :std_ulogic; +signal rel_data_rot_sel :std_ulogic; +signal rel_256ld_data_stg1_d :std_ulogic_vector(0 to 255); +signal rel_256ld_data_stg1_q :std_ulogic_vector(0 to 255); +signal rel_256ld_data_stg2_d :std_ulogic_vector(0 to 255); +signal rel_256ld_data_stg2_q :std_ulogic_vector(0 to 255); +signal rel_axu_le_val_d :std_ulogic; +signal rel_axu_le_val_q :std_ulogic; +signal rel_axu_le_val_stg1_d :std_ulogic; +signal rel_axu_le_val_stg1_q :std_ulogic; +signal dcarr_rd_data :std_ulogic_vector(0 to 287); +signal dcarr_bw :std_ulogic_vector(0 to 287); +signal dcarr_addr :std_ulogic_vector(uprCClassBit to 58); +signal dcarr_wr_data :std_ulogic_vector(0 to 287); +signal dcarr_bw_dly :std_ulogic_vector(0 to 31); +signal dcarr_wren_b :std_ulogic; +signal dcarr_wren :std_ulogic; +signal dcarr_wren_d :std_ulogic; +signal dcarr_wren_q :std_ulogic; +signal ex4_store_hit_early_gate :std_ulogic; +signal rel_ex4_store_hit :std_ulogic; +signal ex4_thrd_id_mask :std_ulogic_vector(0 to 3); +signal dat_dbg_arr_d :std_ulogic_vector(0 to 12); +signal dat_dbg_arr_q :std_ulogic_vector(0 to 12); +signal ex4_256st_dataFixUp :std_ulogic_vector(0 to 255); +signal alg_bit_le_sel :std_ulogic_vector(0 to 5); +signal ex4_ld_alg_sel :std_ulogic_vector(1 to 5); +signal ld_alg_le_sel_d :std_ulogic_vector(1 to 5); +signal ld_alg_le_sel_q :std_ulogic_vector(1 to 5); +signal ex4_ld_alg_le_sel_d :std_ulogic_vector(1 to 5); +signal ex4_ld_alg_le_sel_q :std_ulogic_vector(1 to 5); +signal ex6_axu_rel_gpr_data_sel :std_ulogic_vector(0 to 15); +signal ex6_axu_rel_gpr_data :std_ulogic_vector(0 to 127); +signal ex7_ld_par_err :std_ulogic_vector(0 to 1); +signal ex8_ld_par_err_d :std_ulogic; +signal ex8_ld_par_err_q :std_ulogic; +signal dcache_parity :std_ulogic_vector(0 to 0); +signal ex6_ld_par_err_int :std_ulogic; +signal spr_dvc1_dbg_d :std_ulogic_vector(64-(2**regmode) to 63); +signal spr_dvc1_dbg_q :std_ulogic_vector(64-(2**regmode) to 63); +signal spr_dvc2_dbg_d :std_ulogic_vector(64-(2**regmode) to 63); +signal spr_dvc2_dbg_q :std_ulogic_vector(64-(2**regmode) to 63); +signal ex7_xld_data_d :std_ulogic_vector(64-(2**regmode) to 63); +signal ex7_xld_data_q :std_ulogic_vector(64-(2**regmode) to 63); +signal ex4_stg_flush_lcl_b :std_ulogic_vector(0 to 3); +signal ex4_flush_t01_b :std_ulogic; +signal ex4_flush_t23_b :std_ulogic; +signal rel_ex4_upd_en :std_ulogic; +signal ex1_stg_act_d :std_ulogic; +signal ex1_stg_act_q :std_ulogic; +signal ex2_stg_act_d :std_ulogic; +signal ex2_stg_act_q :std_ulogic; +signal ex3_stg_act_d :std_ulogic; +signal ex3_stg_act_q :std_ulogic; +signal ex4_stg_act_d :std_ulogic; +signal ex4_stg_act_q :std_ulogic; +signal ex5_stg_act_d :std_ulogic; +signal ex5_stg_act_q :std_ulogic; +signal ex6_stg_act_d :std_ulogic; +signal ex6_stg_act_q :std_ulogic; +signal rel1_stg_act_d :std_ulogic; +signal rel1_stg_act_q :std_ulogic; +signal rel2_stg_act_d :std_ulogic; +signal rel2_stg_act_q :std_ulogic; +signal rel3_stg_act_d :std_ulogic; +signal rel3_stg_act_q :std_ulogic; +signal rel4_stg_act_d :std_ulogic; +signal rel4_stg_act_q :std_ulogic; +signal rel5_stg_act_d :std_ulogic; +signal rel5_stg_act_q :std_ulogic; +signal rel2_ex2_stg_act :std_ulogic; +signal rel2_ex2_stg_act_d :std_ulogic; +signal rel2_ex2_stg_act_q :std_ulogic; +signal rel3_ex3_stg_act :std_ulogic; +signal rel3_ex3_stg_act_d :std_ulogic; +signal rel3_ex3_stg_act_q :std_ulogic; +signal rel4_ex4_stg_act :std_ulogic; +signal rel4_ex4_stg_act_d :std_ulogic; +signal rel4_ex4_stg_act_q :std_ulogic; +signal rel_dvc_byte_mask :std_ulogic_vector((64-(2**regmode))/8 to 7); +signal trace_bus_enable_q :std_ulogic; +signal dat_debug_mux_ctrls_q :std_ulogic_vector(0 to 1); +signal rel_ex3_store_data0 :std_ulogic_vector(0 to 63); +signal rel_ex3_store_data1 :std_ulogic_vector(0 to 63); +signal rel_ex3_store_data2 :std_ulogic_vector(0 to 63); +signal rel_ex3_store_data3 :std_ulogic_vector(0 to 63); +signal dat_dbg_st_dat_d :std_ulogic_vector(0 to 63); +signal dat_dbg_st_dat_q :std_ulogic_vector(0 to 63); +signal dat_dbg_ld_dat :std_ulogic_vector(0 to 63); +signal abst_scan_in_q :std_ulogic_vector(0 to 1); +signal abst_scan_out_int :std_ulogic_vector(0 to 1); +signal abst_scan_out_q :std_ulogic_vector(0 to 1); +signal time_scan_in_q :std_ulogic; +signal time_scan_out_int :std_ulogic; +signal time_scan_out_q :std_ulogic; +signal repr_scan_in_q :std_ulogic; +signal repr_scan_out_int :std_ulogic; +signal repr_scan_out_q :std_ulogic; +signal func_scan_in_q :std_ulogic_vector(0 to 2); +signal func_scan_in_2_q :std_ulogic_vector(0 to 2); +signal func_scan_out_int :std_ulogic_vector(0 to 2); +signal func_scan_out_q :std_ulogic_vector(0 to 2); +signal func_scan_out_2_q :std_ulogic_vector(0 to 2); +signal tiup :std_ulogic; +signal tidn :std_ulogic; +signal func_nsl_thold_1 :std_ulogic; +signal func_sl_thold_1 :std_ulogic; +signal sg_1 :std_ulogic; +signal fce_1 :std_ulogic; +signal func_nsl_thold_0 :std_ulogic; +signal func_sl_thold_0 :std_ulogic; +signal sg_0 :std_ulogic; +signal fce_0 :std_ulogic; +signal func_sl_force :std_ulogic; +signal func_sl_thold_0_b :std_ulogic; +signal func_nsl_force :std_ulogic; +signal func_nsl_thold_0_b :std_ulogic; +signal siv0 :std_ulogic_vector(0 to scan_right0); +signal sov0 :std_ulogic_vector(0 to scan_right0); +signal siv1 :std_ulogic_vector(0 to scan_right1); +signal sov1 :std_ulogic_vector(0 to scan_right1); +signal abist_siv :std_ulogic_vector(0 to 21); +signal abist_sov :std_ulogic_vector(0 to 21); +signal abst_sl_thold_1 :std_ulogic; +signal time_sl_thold_1 :std_ulogic; +signal ary_nsl_thold_1 :std_ulogic; +signal repr_sl_thold_1 :std_ulogic; +signal bolt_sl_thold_1 :std_ulogic; +signal abst_sl_thold_0 :std_ulogic; +signal time_sl_thold_0 :std_ulogic; +signal ary_nsl_thold_0 :std_ulogic; +signal repr_sl_thold_0 :std_ulogic; +signal bolt_sl_thold_0 :std_ulogic; +signal abst_sl_thold_0_b :std_ulogic; +signal abst_sl_force :std_ulogic; +signal pc_xu_abist_g6t_bw_q :std_ulogic_vector(0 to 1); +signal pc_xu_abist_di_g6t_2r_q :std_ulogic_vector(0 to 3); +signal pc_xu_abist_wl512_comp_ena_q :std_ulogic; +signal pc_xu_abist_dcomp_g6t_2r_q :std_ulogic_vector(0 to 3); +signal pc_xu_abist_raddr_0_q :std_ulogic_vector(0 to 8); +signal pc_xu_abist_g6t_r_wb_q :std_ulogic; +signal slat_force :std_ulogic; +signal abst_slat_thold_b :std_ulogic; +signal abst_slat_d2clk :std_ulogic; +signal abst_slat_lclk :clk_logic; +signal time_slat_thold_b :std_ulogic; +signal time_slat_d2clk :std_ulogic; +signal time_slat_lclk :clk_logic; +signal repr_slat_thold_b :std_ulogic; +signal repr_slat_d2clk :std_ulogic; +signal repr_slat_lclk :clk_logic; +signal func_slat_thold_b :std_ulogic; +signal func_slat_d2clk :std_ulogic; +signal func_slat_lclk :clk_logic; +signal my_spare_latches_d :std_ulogic_vector(0 to 7); +signal my_spare_latches_q :std_ulogic_vector(0 to 7); +signal my_spare0_lclk :clk_logic; +signal my_spare0_d1clk :std_ulogic; +signal my_spare0_d2clk :std_ulogic; + +signal ex6_frot_b, ex6_fdat, ex6_rot_sel_bus, ex6_axu_oth_b :std_ulogic_vector(0 to 255); +signal ex6_rot_d_b, ex6_rot_d, ex6_xld_rot_b, ex6_xld_oth_b :std_ulogic_vector(0 to 63); +signal ex6_xld_sgnx_b , ex6_xld_sgn_b, ex6_xld_sgn :std_ulogic_vector(0 to 5); + + + + + + + +begin + +tiup <= '1'; +tidn <= '0'; + + +ex1_stg_act_d <= xu_lsu_rf1_data_act or clkg_ctl_override_q; +ex2_stg_act_d <= ex1_stg_act_q; +ex3_stg_act_d <= ex2_stg_act_q; +ex4_stg_act_d <= ex3_stg_act_q; +ex5_stg_act_d <= ex4_stg_act_q; +ex6_stg_act_d <= ex5_stg_act_q; +rel1_stg_act_d <= ldq_rel_data_val_early or clkg_ctl_override_q; +rel2_stg_act_d <= ldq_rel_ci or ldq_rel_data_val or clkg_ctl_override_q; +rel3_stg_act_d <= rel2_stg_act_q; +rel4_stg_act_d <= rel3_stg_act_q; +rel5_stg_act_d <= rel4_stg_act_q; +rel2_ex2_stg_act_d <= rel2_stg_act_d or ex2_stg_act_d; +rel3_ex3_stg_act_d <= rel3_stg_act_d or ex3_stg_act_d; +rel4_ex4_stg_act_d <= rel4_stg_act_d or ex4_stg_act_d; + +rel2_ex2_stg_act <= rel2_ex2_stg_act_q; +rel3_ex3_stg_act <= rel3_ex3_stg_act_q; +rel4_ex4_stg_act <= rel4_ex4_stg_act_q; + + +rel_algebraic_d <= ldq_rel_algebraic; +rel_data_d <= ldq_rel_data; +rel_rot_sel_d <= ldq_rel_rot_sel; +rel_op_size_d <= ldq_rel_op_size; +rel_le_mode_d <= ldq_rel_le_mode; +rel_dvc1_en_d <= ldq_rel_dvc1_en; +rel_dvc2_en_d <= ldq_rel_dvc2_en; +rel_upd_gpr_d <= ldq_rel_beat_crit_qw; +rel_axu_val_d <= ldq_rel_axu_val; +rel_ci_d <= ldq_rel_ci; +rel_ci_dly_d <= rel_ci_q; +rel_thrd_id_d <= ldq_rel_thrd_id; +rel_data_val_stg_d <= ldq_rel_data_val; +rel_data_val_stg_dly_d <= rel_data_val_stg_q; + +rel_algebraic <= rel_algebraic_q; +rel_data <= rel_data_q; +rel_rot_sel <= rel_rot_sel_q; +rel_op_size <= rel_op_size_q; +rel_le_mode <= rel_le_mode_q; + +inj_dcache_parity_d <= pc_xu_inj_dcache_parity; + +rel_data_rot_sel <= rel_ci_q or rel_data_val_stg_q; +rel_data_val_wren <= rel_data_val_stg_q and not spr_xucr0_dcdis_q; +rel_data_val_d(0 to 7) <= (others=>rel_data_val_wren); +rel_data_val_d(8 to 15) <= (others=>(not rel_data_val_wren)); +rel_data_val <= rel_data_val_q; +rel_addr_stg_d <= ldq_rel_addr; +rel_addr_d <= rel_addr_stg_q; + +spr_xucr0_dcdis_d <= xu_lsu_spr_xucr0_dcdis; +clkg_ctl_override_d <= spr_xucr0_clkg_ctl_b0; +ex1_ldst_falign_d <= xu_lsu_rf1_axu_ldst_falign; +ex1_frc_align32 <= ex1_ldst_falign_q and ex1_optype32; +ex1_frc_align16 <= ex1_ldst_falign_q and ex1_optype16; +ex1_frc_align8 <= ex1_ldst_falign_q and ex1_optype8; +ex1_frc_align4 <= ex1_ldst_falign_q and ex1_optype4; +ex1_frc_align2 <= ex1_ldst_falign_q and ex1_optype2; +ex2_p_addr_d <= xu_lsu_ex1_eff_addr(uprCClassBit to 63); +ex3_fu_st_val_d <= fu_xu_ex2_store_data_val; +ex2_optype32_d <= ex1_optype32; +ex2_optype16_d <= ex1_optype16; +ex2_optype8_d <= ex1_optype8; +ex2_optype4_d <= ex1_optype4; +ex2_optype2_d <= ex1_optype2; +ex2_optype1_d <= ex1_optype1; +ex2_store_instr_d <= ex1_store_instr; +ex3_store_instr_d <= ex2_store_instr_q and ex2_stg_act_q; +ex2_axu_op_val_d <= ex1_axu_op_val; +ex3_axu_op_val_d <= ex2_axu_op_val_q; +ex4_axu_op_val_d <= ex3_axu_op_val_q; +ex2_saxu_instr_d <= ex1_saxu_instr; +ex2_sdp_instr_d <= ex1_sdp_instr; +ex2_stgpr_instr_d <= ex1_stgpr_instr; +ex3_saxu_instr_d <= ex2_saxu_instr_q; +ex4_saxu_instr_d <= ex3_saxu_instr_q; +ex4_algebraic_d <= ex3_algebraic; +ex2_ovrd_rot_sel_d <= xu_lsu_ex1_rotsel_ovrd; +ex3_p_addr_d <= ex2_p_addr_q; +ex4_p_addr_d <= ex3_p_addr_q; +ex4_thrd_id_d <= ex3_thrd_id; +ex5_thrd_id_d <= ex4_thrd_id_q; +ex4_load_hit <= ex4_load_op_hit and not ex4_stg_flush; +ex5_load_hit_d <= ex4_load_hit; +ex6_load_hit_d <= ex5_load_hit_q; +ex7_load_hit_d <= ex6_load_hit_q; +spr_dvc1_dbg_d <= spr_dvc1_dbg; +spr_dvc2_dbg_d <= spr_dvc2_dbg; + +ex1_op_size <= ex1_optype8 & ex1_optype4 & ex1_optype2 & ex1_optype1; + +with ex1_op_size(2 to 5) select + ex1_st_byte_mask <= x"01" when "0001", + x"03" when "0010", + x"0F" when "0100", + x"FF" when others; + +ex2_xu_cmp_val_d <= gate(ex1_st_byte_mask((64-(2**regmode))/8 to 7), (not ex1_axu_op_val and ex1_store_instr)); + +frc_p_addr_d(58) <= xu_lsu_ex1_eff_addr(58); +frc_p_addr_d(59) <= xu_lsu_ex1_eff_addr(59) and not ex1_frc_align32; +frc_p_addr_d(60) <= xu_lsu_ex1_eff_addr(60) and not (ex1_frc_align32 or ex1_frc_align16); +frc_p_addr_d(61) <= xu_lsu_ex1_eff_addr(61) and not (ex1_frc_align32 or ex1_frc_align16 or ex1_frc_align8); +frc_p_addr_d(62) <= xu_lsu_ex1_eff_addr(62) and not (ex1_frc_align32 or ex1_frc_align16 or ex1_frc_align8 or ex1_frc_align4); +frc_p_addr_d(63) <= xu_lsu_ex1_eff_addr(63) and not (ex1_frc_align32 or ex1_frc_align16 or ex1_frc_align8 or ex1_frc_align4 or ex1_frc_align2); + +axu_rel_val_stg1_d <= rel_axu_val_q; +axu_rel_val_stg2_d <= axu_rel_val_stg1_q and rel_upd_gpr_q; +axu_rel_val_stg3_d <= axu_rel_val_stg2_q; +axu_rel_upd_d <= (others=>axu_rel_val_stg3_q); + +op_size <= ex2_optype32_q & ex2_optype16_q & ex2_optype8_q & ex2_optype4_q & ex2_optype2_q & ex2_optype1_q; +rot_addr <= frc_p_addr_q(58 to 63); +ex3_le_mode <= ex3_data_swap and not (ex3_ovrd_rot_q or rel_data_val(0)); +ex3_be_mode <= ex3_ovrd_rot_q or rel_data_val(0) or (not ex3_data_swap); +ex4_le_mode_sel_d(0 to 15) <= (others=>ex3_le_mode); +ex4_be_mode_sel_d(0 to 15) <= (others=>ex3_be_mode); +ex4_le_mode_d <= ex3_le_mode; + +rot_size <= std_ulogic_vector(unsigned(rot_addr) + unsigned(op_size)); +rot_sel_non_le <= std_ulogic_vector(unsigned(rot_max_size) - unsigned(rot_size)); + + +rot_addr_le <= std_ulogic_vector(unsigned(rot_addr) + unsigned(byte16_size)); +rot_size_le <= std_ulogic_vector(unsigned(rot_max_size) - unsigned(rot_addr_le)); + +with op_size(0) select + le_st_rot_sel <= (others=>'0') when '1', + rot_size_le(2 to 5) when others; + +be_st_rot_sel <= rot_sel_non_le(1 to 5); + +with ex2_ovrd_rot select + st_ovrd_rot_sel <= ex2_ovrd_rot_sel_q when '1', + be_st_rot_sel when others; + +ex3_st_rot_sel_d <= st_ovrd_rot_sel; + + +rot_addr_d <= rot_addr(1 to 5); +ex4_rot_addr_d <= rot_addr_q; +rot_sel_non_le_d <= rot_sel_non_le(1 to 5); +ex4_rot_sel_non_le_d <= rot_sel_non_le_q; + +with ex4_le_mode_q select + ex4_ld_rot_sel <= ex4_rot_addr_q(1 to 5) when '1', + ex4_rot_sel_non_le_q(1 to 5) when others; + +alg_bit_le_sel <= std_ulogic_vector(unsigned(rot_size) - "000001"); +ld_alg_le_sel_d(1 to 5) <= alg_bit_le_sel(1 to 5); +ex4_ld_alg_le_sel_d <= ld_alg_le_sel_q; + +with ex4_le_mode_q select + ex4_ld_alg_sel <= ex4_rot_addr_q when '0', + ex4_ld_alg_le_sel_q when others; + +fu_ex2_store_data_val <= (ex2_axu_op_val_q and ex2_store_instr_q) or ex2_saxu_instr_q; +fu_ex2_store_data <= fu_xu_ex2_store_data; + +ex2_st_data_d <= xu_lsu_ex1_store_data; +ex2_st_data_fixup(0 to 127-(2**regmode)) <= (others=>'0'); +ex2_st_data_fixup(128-(2**regmode) to 127) <= ex2_st_data_q; + +with rel_data_rot_sel select + rel_xu_data <= rel_data when '1', + ex2_st_data_fixup & ex2_st_data_fixup when others; + +ex2_fu_data_val <= fu_ex2_store_data_val and not rel_data_rot_sel; + +with ex2_fu_data_val select + rel_ex2_data <= fu_ex2_store_data when '1', + rel_xu_data when others; + +stDataFrmtBit : for bit in 0 to 7 generate begin + stDataFrmtByte : for byte in 0 to 31 generate begin + rel_ex3_data_d((bit*32)+byte) <= rel_ex2_data((byte*8)+bit); + end generate stDataFrmtByte; +end generate stDataFrmtBit; + + + + +ex4_store_hit_early_gate <= ex4_store_hit and not ex7_ld_par_err(0); +rel_ex4_store_hit <= ex4_store_hit_early_gate or rel_upd_dcarr_val; +ex4_thrd_id_mask <= gate(ex4_thrd_id_q, not rel_upd_dcarr_val); + +ex4Flushb0: ex4_stg_flush_lcl_b(0) <= not (xu_lsu_ex4_flush_local(0) and ex4_thrd_id_mask(0)); +ex4Flushb1: ex4_stg_flush_lcl_b(1) <= not (xu_lsu_ex4_flush_local(1) and ex4_thrd_id_mask(1)); +ex4Flushb2: ex4_stg_flush_lcl_b(2) <= not (xu_lsu_ex4_flush_local(2) and ex4_thrd_id_mask(2)); +ex4Flushb3: ex4_stg_flush_lcl_b(3) <= not (xu_lsu_ex4_flush_local(3) and ex4_thrd_id_mask(3)); + +ex4Flush01b: ex4_flush_t01_b <= not (ex4_stg_flush_lcl_b(0) and ex4_stg_flush_lcl_b(1)); +ex4Flush23b: ex4_flush_t23_b <= not (ex4_stg_flush_lcl_b(2) and ex4_stg_flush_lcl_b(3)); +relex4UpdEn: rel_ex4_upd_en <= not (ex4_flush_t01_b or ex4_flush_t23_b); + +ex4_stg_flush <= (xu_lsu_ex4_flush(0) and ex4_thrd_id_q(0)) or + (xu_lsu_ex4_flush(1) and ex4_thrd_id_q(1)) or + (xu_lsu_ex4_flush(2) and ex4_thrd_id_q(2)) or + (xu_lsu_ex4_flush(3) and ex4_thrd_id_q(3)); + +ex5_stg_flush <= (xu_lsu_ex5_flush(0) and ex5_thrd_id_q(0)) or + (xu_lsu_ex5_flush(1) and ex5_thrd_id_q(1)) or + (xu_lsu_ex5_flush(2) and ex5_thrd_id_q(2)) or + (xu_lsu_ex5_flush(3) and ex5_thrd_id_q(3)); + + +ex2_ovrd_rot <= ex2_saxu_instr_q or ex2_stgpr_instr_q; +ex3_ovrd_rot_d <= ex2_ovrd_rot; +ex3_stgpr_instr_d <= ex2_stgpr_instr_q; +ex4_stgpr_instr_d <= ex3_stgpr_instr_q; + +stDataFixUp : for byte in 0 to 31 generate + ex4_256st_dataFixUp(byte*8 to (byte*8)+7) <= st_256data(byte) & st_256data(byte+32) & st_256data(byte+64) & st_256data(byte+96) & + st_256data(byte+128) & st_256data(byte+160) & st_256data(byte+192) & st_256data(byte+224); +end generate stDataFixUp; + +ex4_stgpr_data <= ex4_256st_dataFixUp(256-(2**regmode) to 255); +ex5_stgpr_data_d <= ex4_stgpr_data; +ex3_sdp_instr_d <= ex2_sdp_instr_q; +ex4_sdp_instr_d <= ex3_sdp_instr_q; +ex5_sdp_instr_d <= ex4_sdp_instr_q; + + +pargen : for t in 0 to 31 generate begin + rel_ex2_par_gen(t) <= xor_reduce(rel_ex2_data(t*8 to (t*8)+7)); +end generate pargen; + +rel_ex3_par_gen_d <= rel_ex2_par_gen; + + + +non_le_byte_bit0 <= rel_data(0) & rel_data(8) & rel_data(16) & rel_data(24) & rel_data(32) & rel_data(40) & rel_data(48) & rel_data(56) & + rel_data(64) & rel_data(72) & rel_data(80) & rel_data(88) & rel_data(96) & rel_data(104) & rel_data(112) & rel_data(120) & + rel_data(128) & rel_data(136) & rel_data(144) & rel_data(152) & rel_data(160) & rel_data(168) & rel_data(176) & rel_data(184) & + rel_data(192) & rel_data(200) & rel_data(208) & rel_data(216) & rel_data(224) & rel_data(232) & rel_data(240) & rel_data(248); + +le_byte_bit0 <= rel_data(248) & rel_data(240) & rel_data(232) & rel_data(224) & rel_data(216) & rel_data(208) & rel_data(200) & rel_data(192) & + rel_data(184) & rel_data(176) & rel_data(168) & rel_data(160) & rel_data(152) & rel_data(144) & rel_data(136) & rel_data(128) & + rel_data(120) & rel_data(112) & rel_data(104) & rel_data(96) & rel_data(88) & rel_data(80) & rel_data(72) & rel_data(64) & + rel_data(56) & rel_data(48) & rel_data(40) & rel_data(32) & rel_data(24) & rel_data(16) & rel_data(8) & rel_data(0); + +with rel_le_mode select + alg_byte <= le_byte_bit0 when '1', + non_le_byte_bit0 when others; + +alg_bit_sel <= std_ulogic_vector(unsigned(rel_rot_sel) - unsigned(rel_op_size(1 to 5))); + +with alg_bit_sel select + algebraic_bit <= alg_byte(0) when "00000", + alg_byte(1) when "00001", + alg_byte(2) when "00010", + alg_byte(3) when "00011", + alg_byte(4) when "00100", + alg_byte(5) when "00101", + alg_byte(6) when "00110", + alg_byte(7) when "00111", + alg_byte(8) when "01000", + alg_byte(9) when "01001", + alg_byte(10) when "01010", + alg_byte(11) when "01011", + alg_byte(12) when "01100", + alg_byte(13) when "01101", + alg_byte(14) when "01110", + alg_byte(15) when "01111", + alg_byte(16) when "10000", + alg_byte(17) when "10001", + alg_byte(18) when "10010", + alg_byte(19) when "10011", + alg_byte(20) when "10100", + alg_byte(21) when "10101", + alg_byte(22) when "10110", + alg_byte(23) when "10111", + alg_byte(24) when "11000", + alg_byte(25) when "11001", + alg_byte(26) when "11010", + alg_byte(27) when "11011", + alg_byte(28) when "11100", + alg_byte(29) when "11101", + alg_byte(30) when "11110", + alg_byte(31) when others; + +rel_alg_bit_d <= algebraic_bit; + + +l1dcst: entity work.xuq_lsu_data_st(xuq_lsu_data_st) +GENERIC MAP(expand_type => expand_type, + regmode => regmode, + l_endian_m => l_endian_m) +PORT MAP( + + ex2_stg_act => ex2_stg_act_q, + ex3_stg_act => ex3_stg_act_q, + rel2_stg_act => rel2_stg_act_q, + rel3_stg_act => rel3_stg_act_q, + rel2_ex2_stg_act => rel2_ex2_stg_act, + rel3_ex3_stg_act => rel3_ex3_stg_act, + + rel_data_rot_sel => rel_data_rot_sel, + ldq_rel_rot_sel => rel_rot_sel, + ldq_rel_op_size => rel_op_size, + ldq_rel_le_mode => rel_le_mode, + ldq_rel_algebraic => rel_algebraic, + ldq_rel_data_val => rel_data_val, + rel_alg_bit => rel_alg_bit_q, + + ex2_opsize => op_size, + ex2_rot_sel => st_ovrd_rot_sel, + ex2_rot_sel_le => le_st_rot_sel, + ex2_rot_addr => rot_addr(1 to 5), + ex4_le_mode_sel => ex4_le_mode_sel_q, + ex4_be_mode_sel => ex4_be_mode_sel_q, + + rel_ex3_data => rel_ex3_data_q, + rel_ex3_par_gen => rel_ex3_par_gen_q, + + rel_256ld_data => rel_256ld_data, + rel_64ld_data => rel_64ld_data, + rel_xu_ld_par => rel_xu_ld_par, + ex4_256st_data => st_256data, + ex3_byte_en => ex3_byte_en, + ex4_parity_gen => ex4_parity_gen, + rel_axu_le_mode => rel_axu_le_mode, + rel_dvc_byte_mask => rel_dvc_byte_mask, + + vdd => vdd, + gnd => gnd, + nclk => nclk, + sg_0 => sg_0, + func_sl_thold_0_b => func_sl_thold_0_b, + func_sl_force => func_sl_force, + func_nsl_thold_0_b => func_nsl_thold_0_b, + func_nsl_force => func_nsl_force, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc(5), + mpw1_dc_b => mpw1_dc_b(5), + mpw2_dc_b => mpw2_dc_b, + scan_in => func_scan_in_2_q(2), + scan_out => func_scan_out_int(2) +); + + +l1dcarr : entity work.xuq_lsu_dc_arr(xuq_lsu_dc_arr) +generic map(expand_type => expand_type, + dc_size => dc_size) +port map( + + ex3_stg_act => ex3_stg_act_q, + ex4_stg_act => ex4_stg_act_q, + rel3_stg_act => rel3_stg_act_q, + rel4_stg_act => rel4_stg_act_q, + + ex3_p_addr => ex3_p_addr_q(uprCClassBit to 58), + ex3_byte_en => ex3_byte_en, + ex4_256st_data => st_256data, + ex4_parity_gen => ex4_parity_gen, + ex4_load_hit => ex4_load_hit, + ex5_stg_flush => ex5_stg_flush, + + inj_dcache_parity => inj_dcache_parity_q, + + ldq_rel_data_val => rel_data_val(0), + ldq_rel_addr => rel_addr_q, + + dcarr_rd_data => dcarr_rd_data, + dcarr_bw => dcarr_bw, + dcarr_addr => dcarr_addr, + dcarr_wr_data => dcarr_wr_data, + dcarr_bw_dly => dcarr_bw_dly, + + ex5_ld_data => ex5_ld_data, + ex5_ld_data_par => ex5_ld_data_par, + ex6_par_chk_val => ex6_par_chk_val, + + vdd => vdd, + gnd => gnd, + nclk => nclk, + sg_0 => sg_0, + func_sl_thold_0_b => func_sl_thold_0_b, + func_sl_force => func_sl_force, + func_nsl_thold_0_b => func_nsl_thold_0_b, + func_nsl_force => func_nsl_force, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc(5), + mpw1_dc_b => mpw1_dc_b(5), + mpw2_dc_b => mpw2_dc_b, + scan_in => siv1(l1dcar_offset), + scan_out => sov1(l1dcar_offset) +); + + +dcArrWenb: dcarr_wren_b <= not (rel_ex4_store_hit and rel_ex4_upd_en); +dcArrWen: dcarr_wren <= not (dcarr_wren_b); + +dcarr_wren_d <= dcarr_wren; +dat_dbg_arr_d <= ex4_store_hit & (not rel_ex4_upd_en) & rel_upd_dcarr_val & rel4_ex4_stg_act & + dcarr_up_way_addr & dcarr_addr; + +dc16K: if (2**dc_size) = 16384 generate + tridcarr: entity tri.tri_512x288_9(tri_512x288_9) + GENERIC Map(addressable_ports => 512, + addressbus_width => 6, + port_bitwidth => 288, + bit_write_type => 9, + ways => 1, + expand_type => expand_type) + PORT Map( + vcs => vcs, + vdd => vdd, + gnd => gnd, + + nclk => nclk, + act => rel4_ex4_stg_act, + sg_0 => sg_0, + sg_1 => sg_1, + ary_nsl_thold_0 => ary_nsl_thold_0, + abst_sl_thold_0 => abst_sl_thold_0, + time_sl_thold_0 => time_sl_thold_0, + repr_sl_thold_0 => repr_sl_thold_0, + clkoff_dc_b => g6t_clkoff_dc_b, + ccflush_dc => pc_xu_ccflush_dc, + scan_dis_dc_b => an_ac_scan_dis_dc_b, + scan_diag_dc => an_ac_scan_diag_dc, + d_mode_dc => g6t_d_mode_dc, + act_dis_dc => tidn, + lcb_delay_lclkr_np_dc => g6t_delay_lclkr_dc(0), + lcb_mpw1_pp_dc_b => g6t_mpw1_dc_b(0), + lcb_mpw1_2_pp_dc_b => g6t_mpw1_dc_b(4), + ctrl_lcb_delay_lclkr_np_dc => g6t_delay_lclkr_dc(1), + ctrl_lcb_mpw1_np_dc_b => g6t_mpw1_dc_b(1), + dibw_lcb_delay_lclkr_np_dc => g6t_delay_lclkr_dc(2), + dibw_lcb_mpw1_np_dc_b => g6t_mpw1_dc_b(2), + aodo_lcb_delay_lclkr_dc => g6t_delay_lclkr_dc(3), + aodo_lcb_mpw1_dc_b => g6t_mpw1_dc_b(3), + aodo_lcb_mpw2_dc_b => g6t_mpw2_dc_b, + + bitw_abist => pc_xu_abist_g6t_bw_q, + tc_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc, + abist_en_1 => pc_xu_abist_ena_dc, + din_abist => pc_xu_abist_di_g6t_2r_q, + abist_cmp_en => pc_xu_abist_wl512_comp_ena_q, + abist_raw_b_dc => pc_xu_abist_raw_dc_b, + data_cmp_abist => pc_xu_abist_dcomp_g6t_2r_q, + addr_abist => pc_xu_abist_raddr_0_q, + r_wb_abist => pc_xu_abist_g6t_r_wb_q, + + abst_scan_in(0) => abist_siv(0), + abst_scan_in(1) => abst_scan_in_q(1), + time_scan_in => time_scan_in_q, + repr_scan_in => repr_scan_in_q, + abst_scan_out(0) => abist_sov(0), + abst_scan_out(1) => abst_scan_out_int(1), + time_scan_out => time_scan_out_int, + repr_scan_out => repr_scan_out_int, + + lcb_bolt_sl_thold_0 => bolt_sl_thold_0, + pc_bo_enable_2 => bo_enable_2, + pc_bo_reset => pc_xu_bo_reset, + pc_bo_unload => pc_xu_bo_unload, + pc_bo_repair => pc_xu_bo_repair, + pc_bo_shdata => pc_xu_bo_shdata, + pc_bo_select => pc_xu_bo_select, + bo_pc_failout => xu_pc_bo_fail, + bo_pc_diagloop => xu_pc_bo_diagout, + tri_lcb_mpw1_dc_b => mpw1_dc_b(5), + tri_lcb_mpw2_dc_b => mpw2_dc_b, + tri_lcb_delay_lclkr_dc => delay_lclkr_dc(5), + tri_lcb_clkoff_dc_b => clkoff_dc_b, + tri_lcb_act_dis_dc => tidn, + + + write_enable => dcarr_wren, + bw => dcarr_bw, + arr_up_addr => dcarr_up_way_addr, + addr => dcarr_addr, + data_in => dcarr_wr_data, + data_out => dcarr_rd_data + ); +end generate dc16K; + +dc32K: if (2**dc_size) = 32768 generate + tridcarr: entity tri.tri_512x288_9(tri_512x288_9) + GENERIC Map(addressable_ports => 1024, + addressbus_width => 7, + port_bitwidth => 288, + bit_write_type => 9, + ways => 1, + expand_type => expand_type) + PORT Map( + vcs => vcs, + vdd => vdd, + gnd => gnd, + + nclk => nclk, + act => rel4_ex4_stg_act, + sg_0 => sg_0, + sg_1 => sg_1, + ary_nsl_thold_0 => ary_nsl_thold_0, + abst_sl_thold_0 => abst_sl_thold_0, + time_sl_thold_0 => time_sl_thold_0, + repr_sl_thold_0 => repr_sl_thold_0, + clkoff_dc_b => g6t_clkoff_dc_b, + ccflush_dc => pc_xu_ccflush_dc, + scan_dis_dc_b => an_ac_scan_dis_dc_b, + scan_diag_dc => an_ac_scan_diag_dc, + d_mode_dc => g6t_d_mode_dc, + act_dis_dc => tidn, + lcb_delay_lclkr_np_dc => g6t_delay_lclkr_dc(0), + lcb_mpw1_pp_dc_b => g6t_mpw1_dc_b(0), + lcb_mpw1_2_pp_dc_b => g6t_mpw1_dc_b(4), + ctrl_lcb_delay_lclkr_np_dc => g6t_delay_lclkr_dc(1), + ctrl_lcb_mpw1_np_dc_b => g6t_mpw1_dc_b(1), + dibw_lcb_delay_lclkr_np_dc => g6t_delay_lclkr_dc(2), + dibw_lcb_mpw1_np_dc_b => g6t_mpw1_dc_b(2), + aodo_lcb_delay_lclkr_dc => g6t_delay_lclkr_dc(3), + aodo_lcb_mpw1_dc_b => g6t_mpw1_dc_b(3), + aodo_lcb_mpw2_dc_b => g6t_mpw2_dc_b, + + bitw_abist => pc_xu_abist_g6t_bw_q, + tc_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc, + abist_en_1 => pc_xu_abist_ena_dc, + din_abist => pc_xu_abist_di_g6t_2r_q, + abist_cmp_en => pc_xu_abist_wl512_comp_ena_q, + abist_raw_b_dc => pc_xu_abist_raw_dc_b, + data_cmp_abist => pc_xu_abist_dcomp_g6t_2r_q, + addr_abist => pc_xu_abist_raddr_0_q, + r_wb_abist => pc_xu_abist_g6t_r_wb_q, + + abst_scan_in(0) => abist_siv(0), + abst_scan_in(1) => abst_scan_in_q(1), + time_scan_in => time_scan_in_q, + repr_scan_in => repr_scan_in_q, + abst_scan_out(0) => abist_sov(0), + abst_scan_out(1) => abst_scan_out_int(1), + time_scan_out => time_scan_out_int, + repr_scan_out => repr_scan_out_int, + + lcb_bolt_sl_thold_0 => bolt_sl_thold_0, + pc_bo_enable_2 => bo_enable_2, + pc_bo_reset => pc_xu_bo_reset, + pc_bo_unload => pc_xu_bo_unload, + pc_bo_repair => pc_xu_bo_repair, + pc_bo_shdata => pc_xu_bo_shdata, + pc_bo_select => pc_xu_bo_select, + bo_pc_failout => xu_pc_bo_fail, + bo_pc_diagloop => xu_pc_bo_diagout, + tri_lcb_mpw1_dc_b => mpw1_dc_b(5), + tri_lcb_mpw2_dc_b => mpw2_dc_b, + tri_lcb_delay_lclkr_dc => delay_lclkr_dc(5), + tri_lcb_clkoff_dc_b => clkoff_dc_b, + tri_lcb_act_dis_dc => tidn, + + write_enable => dcarr_wren, + bw => dcarr_bw, + arr_up_addr => dcarr_up_way_addr, + addr => dcarr_addr, + data_in => dcarr_wr_data, + data_out => dcarr_rd_data + ); +end generate dc32K; + +ex3_opsize_d <= op_size; + +rel_axu_le_val_d <= rel_axu_le_mode and rel_upd_gpr_q; +rel_axu_le_val_stg1_d <= rel_axu_le_val_q; +ex5_rel_le_mode_d <= (ex4_le_mode_q and not rel_axu_le_val_stg1_q) or rel_axu_le_val_stg1_q; + +l1dcld: entity work.xuq_lsu_data_ld(xuq_lsu_data_ld) +GENERIC MAP(expand_type => expand_type, + regmode => regmode, + l_endian_m => l_endian_m) +PORT MAP( + + ex3_stg_act => ex3_stg_act_q, + ex4_stg_act => ex4_stg_act_q, + ex5_stg_act => ex5_stg_act_q, + + ex3_opsize => ex3_opsize_q, + ex3_algebraic => ex3_algebraic, + ex4_ld_rot_sel => ex4_ld_rot_sel, + ex4_ld_alg_sel => ex4_ld_alg_sel, + ex4_le_mode => ex4_le_mode_q, + ex5_ld_data => ex5_ld_data, + ex5_ld_data_par => ex5_ld_data_par, + ex6_par_chk_val => ex6_par_chk_val, + + trace_bus_enable => trace_bus_enable_q, + dat_debug_mux_ctrls => dat_debug_mux_ctrls_q, + dat_dbg_ld_dat => dat_dbg_ld_dat, + + ld_swzl_data (0 to 255) => ld_swzl_data(0 to 255) , + ex6_ld_alg_bit(0 to 5) => ex6_ld_alg_bit(0 to 5) , + ex6_ld_dvc_byte_mask => ex6_ld_dvc_byte_mask, + + + ex6_ld_par_err => ex6_ld_par_err_int, + ex7_ld_par_err => ex7_ld_par_err, + + vdd => vdd, + gnd => gnd, + nclk => nclk, + sg_0 => sg_0, + func_sl_thold_0_b => func_sl_thold_0_b, + func_sl_force => func_sl_force, + func_nsl_thold_0_b => func_nsl_thold_0_b, + func_nsl_force => func_nsl_force, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc(5), + mpw1_dc_b => mpw1_dc_b(5), + mpw2_dc_b => mpw2_dc_b, + scan_in => siv1(l1dcld_offset), + scan_out => sov1(l1dcld_offset) +); + + +stDbgData : for byte in 0 to 7 generate begin + rel_ex3_store_data0(byte*8 to (byte*8)+7) <= rel_ex3_data_q(byte+0) & rel_ex3_data_q(byte+32) & rel_ex3_data_q(byte+64) & rel_ex3_data_q(byte+96) & + rel_ex3_data_q(byte+128) & rel_ex3_data_q(byte+160) & rel_ex3_data_q(byte+192) & rel_ex3_data_q(byte+224); + rel_ex3_store_data1(byte*8 to (byte*8)+7) <= rel_ex3_data_q(8+byte+0) & rel_ex3_data_q(8+byte+32) & rel_ex3_data_q(8+byte+64) & rel_ex3_data_q(8+byte+96) & + rel_ex3_data_q(8+byte+128) & rel_ex3_data_q(8+byte+160) & rel_ex3_data_q(8+byte+192) & rel_ex3_data_q(8+byte+224); + rel_ex3_store_data2(byte*8 to (byte*8)+7) <= rel_ex3_data_q(16+byte+0) & rel_ex3_data_q(16+byte+32) & rel_ex3_data_q(16+byte+64) & rel_ex3_data_q(16+byte+96) & + rel_ex3_data_q(16+byte+128) & rel_ex3_data_q(16+byte+160) & rel_ex3_data_q(16+byte+192) & rel_ex3_data_q(16+byte+224); + rel_ex3_store_data3(byte*8 to (byte*8)+7) <= rel_ex3_data_q(24+byte+0) & rel_ex3_data_q(24+byte+32) & rel_ex3_data_q(24+byte+64) & rel_ex3_data_q(24+byte+96) & + rel_ex3_data_q(24+byte+128) & rel_ex3_data_q(24+byte+160) & rel_ex3_data_q(24+byte+192) & rel_ex3_data_q(24+byte+224); +end generate stDbgData; + +with dat_debug_mux_ctrls_q select + dat_dbg_st_dat_d <= rel_ex3_store_data0 when "00", + rel_ex3_store_data1 when "01", + rel_ex3_store_data2 when "10", + rel_ex3_store_data3 when others; + + + + + + +lsu_xu_data_debug0(0 to 21) <= ex4_saxu_instr_q & ex4_sdp_instr_q & ex4_stgpr_instr_q & ex4_axu_op_val_q & + ex4_algebraic_q & ex4_le_mode_q & ex4_ld_rot_sel & ex4_p_addr_q; +lsu_xu_data_debug0(22 to 43) <= ex7_load_hit_q & ex7_ld_par_err(1) & dat_dbg_ld_dat(0 to 19); +lsu_xu_data_debug0(44 to 65) <= dat_dbg_ld_dat(20 to 41); +lsu_xu_data_debug0(66 to 87) <= dat_dbg_ld_dat(42 to 63); + + + + + +lsu_xu_data_debug1(0 to 21) <= dcarr_wren_q & rel_ci_dly_q & ex4_saxu_instr_q & ex4_stgpr_instr_q & + ex3_fu_st_val_q & ex4_le_mode_q & ex3_st_rot_sel_q & ex4_p_addr_q; +lsu_xu_data_debug1(22 to 43) <= ex3_store_instr_q & rel_data_val_stg_dly_q & dat_dbg_st_dat_q(0 to 19); +lsu_xu_data_debug1(44 to 65) <= dat_dbg_st_dat_q(20 to 41); +lsu_xu_data_debug1(66 to 87) <= dat_dbg_st_dat_q(42 to 63); + + + + + +lsu_xu_data_debug2(0 to 21) <= dat_dbg_arr_q(0 to 2) & dat_dbg_arr_q(4 to 12) & dcarr_bw_dly(0 to 9); +lsu_xu_data_debug2(22 to 43) <= dcarr_bw_dly(10 to 31); +lsu_xu_data_debug2(44 to 65) <= dat_dbg_arr_q(3) & dat_dbg_st_dat_q(21 to 41); +lsu_xu_data_debug2(66 to 87) <= dat_dbg_st_dat_q(42 to 63); + + +dvcCmpSt : for t in (64-(2**regmode))/8 to 7 generate begin + ex2_st_dvc1_cmp_d(t) <= (xu_lsu_ex1_store_data(t*8 to (t*8)+7) = + spr_dvc1_dbg_q(t*8 to (t*8)+7)); + ex2_st_dvc2_cmp_d(t) <= (xu_lsu_ex1_store_data(t*8 to (t*8)+7) = + spr_dvc2_dbg_q(t*8 to (t*8)+7)); +end generate dvcCmpSt; + +ex5_dvc1_en_d <= ex4_load_hit and not ex4_axu_op_val; +ex5_dvc2_en_d <= ex4_load_hit and not ex4_axu_op_val; +ex6_dvc1_en_d <= ex5_dvc1_en_q; +ex6_dvc2_en_d <= ex5_dvc2_en_q; +ex7_dvc1_en_d <= gate(ex6_ld_dvc_byte_mask, ex6_dvc1_en_q); +ex7_dvc2_en_d <= gate(ex6_ld_dvc_byte_mask, ex6_dvc2_en_q); + +dvcCmpLd : for t in (64-(2**regmode))/8 to 7 generate begin + ex8_ld_dvc1_cmp_d(t) <= ex7_dvc1_en_q(t) and (ex7_xld_data_q(t*8 to (t*8)+7) = + spr_dvc1_dbg_q(t*8 to (t*8)+7)); + ex8_ld_dvc2_cmp_d(t) <= ex7_dvc2_en_q(t) and (ex7_xld_data_q(t*8 to (t*8)+7) = + spr_dvc2_dbg_q(t*8 to (t*8)+7)); +end generate dvcCmpLd; + +rel_dvc1_val_d <= rel_dvc1_en_q and not rel_axu_val_q; +rel_dvc1_val_stg_d <= rel_upd_gpr_q and rel_dvc1_val_q and not ldq_rel_beat_crit_qw_block; +rel_dvc1_val_stg2_d <= rel_dvc1_val_stg_q; +rel_dvc2_val_d <= rel_dvc2_en_q and not rel_axu_val_q; +rel_dvc2_val_stg_d <= rel_upd_gpr_q and rel_dvc2_val_q and not ldq_rel_beat_crit_qw_block; +rel_dvc2_val_stg2_d <= rel_dvc2_val_stg_q; +rel_dvc_thrd_id_d <= rel_thrd_id_q; +rel_dvc_tid_stg_d <= rel_dvc_thrd_id_q; +rel_dvc_tid_stg2_d <= rel_dvc_tid_stg_q; + +dvcCmpRl : for t in (64-(2**regmode))/8 to 7 generate begin + rel_dvc1_cmp_d(t) <= (rel_64ld_data(t*8 to (t*8)+7) = + spr_dvc1_dbg_q(t*8 to (t*8)+7)) and rel_dvc_byte_mask(t); + rel_dvc2_cmp_d(t) <= (rel_64ld_data(t*8 to (t*8)+7) = + spr_dvc2_dbg_q(t*8 to (t*8)+7)) and rel_dvc_byte_mask(t); +end generate dvcCmpRl; + + +ex6_stgpr_dp_data_d(0 to 127-(2**regmode)) <= ex5_dp_data(0 to 127-(2**regmode)); +ex6_stgpr_dp_data_d(128-(2**regmode) to 127) <= gate(ex5_dp_data(128-(2**regmode) to 127), ex5_sdp_instr_q) or + gate(ex5_stgpr_data_q(64-(2**regmode) to 63), not ex5_sdp_instr_q); + +axu_data_sel <= (ex4_sdp_instr_q or ex4_stgpr_instr_q) & axu_rel_val_stg2_q; + +with axu_data_sel select + ex5_axu_data_sel_d <= "001" when "00", + "100" when "10", + "010" when others; + +selGen : for sel in 0 to 15 generate begin + ex6_axu_data_sel_d(3*sel to (3*sel)+2) <= ex5_axu_data_sel_q; +end generate selGen; + +ex5_stgpr_dp_instr_d <= ex4_sdp_instr_q or ex4_stgpr_instr_q; +ex6_stgpr_dp_instr_d <= ex5_stgpr_dp_instr_q; + + +rel_256ld_data_stg1_d <= rel_256ld_data; +rel_256ld_data_stg2_d <= rel_256ld_data_stg1_q; + + + ex6_rot_sel(0 to 15) <= not axu_rel_upd_q(0 to 15) ; + + axuldreldata : for t in 0 to 15 generate begin + + ex6_axu_oth_b(t*8 to (t*8)+7) <= not( gate(rel_256ld_data_stg2_q(t*8 to (t*8)+7), axu_rel_upd_q(t)) ); + + end generate axuldreldata; + +axuRelGpr : for byte in 0 to 15 generate + ex6_axu_rel_gpr_data(8*byte to (8*byte)+7) <= gate(ex6_stgpr_dp_data_q(8*byte to (8*byte)+7), ex6_axu_data_sel_q((byte*3))) or + gate(rel_256ld_data_stg2_q(128+(8*byte) to 128+(8*byte)+7), ex6_axu_data_sel_q((byte*3)+1)); + + ex6_axu_rel_gpr_data_sel(byte) <= not ex6_axu_data_sel_q((byte*3)+2); + ex6_rot_sel(16 + byte) <= ex6_axu_data_sel_q((byte*3)+2); + + ex6_axu_oth_b(128+(8*byte) to 128+(8*byte)+7) <= not( gate(ex6_axu_rel_gpr_data(8*byte to (8*byte)+7), ex6_axu_rel_gpr_data_sel(byte) ) ); + +end generate axuRelGpr; + + + ex6_rot_sel_bus(0 to 255) <= ( 0 to 7 => ex6_rot_sel( 0) ) & + ( 0 to 7 => ex6_rot_sel( 1) ) & + ( 0 to 7 => ex6_rot_sel( 2) ) & + ( 0 to 7 => ex6_rot_sel( 3) ) & + ( 0 to 7 => ex6_rot_sel( 4) ) & + ( 0 to 7 => ex6_rot_sel( 5) ) & + ( 0 to 7 => ex6_rot_sel( 6) ) & + ( 0 to 7 => ex6_rot_sel( 7) ) & + ( 0 to 7 => ex6_rot_sel( 8) ) & + ( 0 to 7 => ex6_rot_sel( 9) ) & + ( 0 to 7 => ex6_rot_sel(10) ) & + ( 0 to 7 => ex6_rot_sel(11) ) & + ( 0 to 7 => ex6_rot_sel(12) ) & + ( 0 to 7 => ex6_rot_sel(13) ) & + ( 0 to 7 => ex6_rot_sel(14) ) & + ( 0 to 7 => ex6_rot_sel(15) ) & + ( 0 to 7 => ex6_rot_sel(16) ) & + ( 0 to 7 => ex6_rot_sel(17) ) & + ( 0 to 7 => ex6_rot_sel(18) ) & + ( 0 to 7 => ex6_rot_sel(19) ) & + ( 0 to 7 => ex6_rot_sel(20) ) & + ( 0 to 7 => ex6_rot_sel(21) ) & + ( 0 to 7 => ex6_rot_sel(22) ) & + ( 0 to 7 => ex6_rot_sel(23) ) & + ( 0 to 7 => ex6_rot_sel(24) ) & + ( 0 to 7 => ex6_rot_sel(25) ) & + ( 0 to 7 => ex6_rot_sel(26) ) & + ( 0 to 7 => ex6_rot_sel(27) ) & + ( 0 to 7 => ex6_rot_sel(28) ) & + ( 0 to 7 => ex6_rot_sel(29) ) & + ( 0 to 7 => ex6_rot_sel(30) ) & + ( 0 to 7 => ex6_rot_sel(31) ) ; + + + u_axu_rot: ex6_frot_b (0 to 255) <= not( ld_swzl_data (0 to 255) and ex6_rot_sel_bus(0 to 255) ); + u_axu_dat: ex6_fdat (0 to 255) <= not( ex6_frot_b (0 to 255) and ex6_axu_oth_b (0 to 255) ); + + u_axu_dati: xu_fu_ex6_load_data (0 to 255) <= ex6_fdat(0 to 255); + + + ex6_stgpr_dp_instr_q_b <= not ex6_stgpr_dp_instr_q ; + + + u_xrot_i: ex6_rot_d_b(0 to 63) <= not( ld_swzl_data(192 to 255) ); + u_xrot_ii: ex6_rot_d (0 to 63) <= not( ex6_rot_d_b(0 to 63) ); + + u_xld_sgn: ex6_xld_sgnx_b(0 to 5) <= not( ex6_ld_alg_bit(0 to 5) and (0 to 5=> ex6_stgpr_dp_instr_q_b) ); + u_xld_sgni: ex6_xld_sgn (0 to 5) <= not( ex6_xld_sgnx_b(0 to 5) ); + u_xld_sgnii: ex6_xld_sgn_b (0 to 5) <= not( ex6_xld_sgn (0 to 5) ); + + u_xld_rot: ex6_xld_rot_b(0 to 63) <= not( ex6_rot_d(0 to 63) and (0 to 63=> ex6_stgpr_dp_instr_q_b) ); + u_xld_oth: ex6_xld_oth_b(0 to 63) <= not( ex6_stgpr_dp_data_q(64 to 127) and (0 to 63=> ex6_stgpr_dp_instr_q ) ); + + u_xld_or_00: ex6_xld_data( 0) <= not( ex6_xld_rot_b( 0) and ex6_xld_sgn_b( 0) and ex6_xld_oth_b( 0) ); + u_xld_or_01: ex6_xld_data( 1) <= not( ex6_xld_rot_b( 1) and ex6_xld_sgn_b( 0) and ex6_xld_oth_b( 1) ); + u_xld_or_02: ex6_xld_data( 2) <= not( ex6_xld_rot_b( 2) and ex6_xld_sgn_b( 1) and ex6_xld_oth_b( 2) ); + u_xld_or_03: ex6_xld_data( 3) <= not( ex6_xld_rot_b( 3) and ex6_xld_sgn_b( 1) and ex6_xld_oth_b( 3) ); + u_xld_or_04: ex6_xld_data( 4) <= not( ex6_xld_rot_b( 4) and ex6_xld_sgn_b( 2) and ex6_xld_oth_b( 4) ); + u_xld_or_05: ex6_xld_data( 5) <= not( ex6_xld_rot_b( 5) and ex6_xld_sgn_b( 2) and ex6_xld_oth_b( 5) ); + u_xld_or_06: ex6_xld_data( 6) <= not( ex6_xld_rot_b( 6) and ex6_xld_sgn_b( 3) and ex6_xld_oth_b( 6) ); + u_xld_or_07: ex6_xld_data( 7) <= not( ex6_xld_rot_b( 7) and ex6_xld_sgn_b( 3) and ex6_xld_oth_b( 7) ); + + u_xld_or_08: ex6_xld_data( 8) <= not( ex6_xld_rot_b( 8) and ex6_xld_sgn_b( 0) and ex6_xld_oth_b( 8) ); + u_xld_or_09: ex6_xld_data( 9) <= not( ex6_xld_rot_b( 9) and ex6_xld_sgn_b( 0) and ex6_xld_oth_b( 9) ); + u_xld_or_10: ex6_xld_data(10) <= not( ex6_xld_rot_b(10) and ex6_xld_sgn_b( 1) and ex6_xld_oth_b(10) ); + u_xld_or_11: ex6_xld_data(11) <= not( ex6_xld_rot_b(11) and ex6_xld_sgn_b( 1) and ex6_xld_oth_b(11) ); + u_xld_or_12: ex6_xld_data(12) <= not( ex6_xld_rot_b(12) and ex6_xld_sgn_b( 2) and ex6_xld_oth_b(12) ); + u_xld_or_13: ex6_xld_data(13) <= not( ex6_xld_rot_b(13) and ex6_xld_sgn_b( 2) and ex6_xld_oth_b(13) ); + u_xld_or_14: ex6_xld_data(14) <= not( ex6_xld_rot_b(14) and ex6_xld_sgn_b( 3) and ex6_xld_oth_b(14) ); + u_xld_or_15: ex6_xld_data(15) <= not( ex6_xld_rot_b(15) and ex6_xld_sgn_b( 3) and ex6_xld_oth_b(15) ); + + u_xld_or_16: ex6_xld_data(16) <= not( ex6_xld_rot_b(16) and ex6_xld_sgn_b( 0) and ex6_xld_oth_b(16) ); + u_xld_or_17: ex6_xld_data(17) <= not( ex6_xld_rot_b(17) and ex6_xld_sgn_b( 0) and ex6_xld_oth_b(17) ); + u_xld_or_18: ex6_xld_data(18) <= not( ex6_xld_rot_b(18) and ex6_xld_sgn_b( 1) and ex6_xld_oth_b(18) ); + u_xld_or_19: ex6_xld_data(19) <= not( ex6_xld_rot_b(19) and ex6_xld_sgn_b( 1) and ex6_xld_oth_b(19) ); + u_xld_or_20: ex6_xld_data(20) <= not( ex6_xld_rot_b(20) and ex6_xld_sgn_b( 2) and ex6_xld_oth_b(20) ); + u_xld_or_21: ex6_xld_data(21) <= not( ex6_xld_rot_b(21) and ex6_xld_sgn_b( 2) and ex6_xld_oth_b(21) ); + u_xld_or_22: ex6_xld_data(22) <= not( ex6_xld_rot_b(22) and ex6_xld_sgn_b( 3) and ex6_xld_oth_b(22) ); + u_xld_or_23: ex6_xld_data(23) <= not( ex6_xld_rot_b(23) and ex6_xld_sgn_b( 3) and ex6_xld_oth_b(23) ); + + u_xld_or_24: ex6_xld_data(24) <= not( ex6_xld_rot_b(24) and ex6_xld_sgn_b( 0) and ex6_xld_oth_b(24) ); + u_xld_or_25: ex6_xld_data(25) <= not( ex6_xld_rot_b(25) and ex6_xld_sgn_b( 0) and ex6_xld_oth_b(25) ); + u_xld_or_26: ex6_xld_data(26) <= not( ex6_xld_rot_b(26) and ex6_xld_sgn_b( 1) and ex6_xld_oth_b(26) ); + u_xld_or_27: ex6_xld_data(27) <= not( ex6_xld_rot_b(27) and ex6_xld_sgn_b( 1) and ex6_xld_oth_b(27) ); + u_xld_or_28: ex6_xld_data(28) <= not( ex6_xld_rot_b(28) and ex6_xld_sgn_b( 2) and ex6_xld_oth_b(28) ); + u_xld_or_29: ex6_xld_data(29) <= not( ex6_xld_rot_b(29) and ex6_xld_sgn_b( 2) and ex6_xld_oth_b(29) ); + u_xld_or_30: ex6_xld_data(30) <= not( ex6_xld_rot_b(30) and ex6_xld_sgn_b( 3) and ex6_xld_oth_b(30) ); + u_xld_or_31: ex6_xld_data(31) <= not( ex6_xld_rot_b(31) and ex6_xld_sgn_b( 3) and ex6_xld_oth_b(31) ); + + u_xld_or_32: ex6_xld_data(32) <= not( ex6_xld_rot_b(32) and ex6_xld_sgn_b( 4) and ex6_xld_oth_b(32) ); + u_xld_or_33: ex6_xld_data(33) <= not( ex6_xld_rot_b(33) and ex6_xld_sgn_b( 4) and ex6_xld_oth_b(33) ); + u_xld_or_34: ex6_xld_data(34) <= not( ex6_xld_rot_b(34) and ex6_xld_sgn_b( 4) and ex6_xld_oth_b(34) ); + u_xld_or_35: ex6_xld_data(35) <= not( ex6_xld_rot_b(35) and ex6_xld_sgn_b( 4) and ex6_xld_oth_b(35) ); + u_xld_or_36: ex6_xld_data(36) <= not( ex6_xld_rot_b(36) and ex6_xld_sgn_b( 5) and ex6_xld_oth_b(36) ); + u_xld_or_37: ex6_xld_data(37) <= not( ex6_xld_rot_b(37) and ex6_xld_sgn_b( 5) and ex6_xld_oth_b(37) ); + u_xld_or_38: ex6_xld_data(38) <= not( ex6_xld_rot_b(38) and ex6_xld_sgn_b( 5) and ex6_xld_oth_b(38) ); + u_xld_or_39: ex6_xld_data(39) <= not( ex6_xld_rot_b(39) and ex6_xld_sgn_b( 5) and ex6_xld_oth_b(39) ); + + u_xld_or_40: ex6_xld_data(40) <= not( ex6_xld_rot_b(40) and ex6_xld_sgn_b( 4) and ex6_xld_oth_b(40) ); + u_xld_or_41: ex6_xld_data(41) <= not( ex6_xld_rot_b(41) and ex6_xld_sgn_b( 4) and ex6_xld_oth_b(41) ); + u_xld_or_42: ex6_xld_data(42) <= not( ex6_xld_rot_b(42) and ex6_xld_sgn_b( 4) and ex6_xld_oth_b(42) ); + u_xld_or_43: ex6_xld_data(43) <= not( ex6_xld_rot_b(43) and ex6_xld_sgn_b( 4) and ex6_xld_oth_b(43) ); + u_xld_or_44: ex6_xld_data(44) <= not( ex6_xld_rot_b(44) and ex6_xld_sgn_b( 5) and ex6_xld_oth_b(44) ); + u_xld_or_45: ex6_xld_data(45) <= not( ex6_xld_rot_b(45) and ex6_xld_sgn_b( 5) and ex6_xld_oth_b(45) ); + u_xld_or_46: ex6_xld_data(46) <= not( ex6_xld_rot_b(46) and ex6_xld_sgn_b( 5) and ex6_xld_oth_b(46) ); + u_xld_or_47: ex6_xld_data(47) <= not( ex6_xld_rot_b(47) and ex6_xld_sgn_b( 5) and ex6_xld_oth_b(47) ); + + u_xld_or_48: ex6_xld_data(48) <= not( ex6_xld_rot_b(48) and ex6_xld_oth_b(48) ); + u_xld_or_49: ex6_xld_data(49) <= not( ex6_xld_rot_b(49) and ex6_xld_oth_b(49) ); + u_xld_or_50: ex6_xld_data(50) <= not( ex6_xld_rot_b(50) and ex6_xld_oth_b(50) ); + u_xld_or_51: ex6_xld_data(51) <= not( ex6_xld_rot_b(51) and ex6_xld_oth_b(51) ); + u_xld_or_52: ex6_xld_data(52) <= not( ex6_xld_rot_b(52) and ex6_xld_oth_b(52) ); + u_xld_or_53: ex6_xld_data(53) <= not( ex6_xld_rot_b(53) and ex6_xld_oth_b(53) ); + u_xld_or_54: ex6_xld_data(54) <= not( ex6_xld_rot_b(54) and ex6_xld_oth_b(54) ); + u_xld_or_55: ex6_xld_data(55) <= not( ex6_xld_rot_b(55) and ex6_xld_oth_b(55) ); + u_xld_or_56: ex6_xld_data(56) <= not( ex6_xld_rot_b(56) and ex6_xld_oth_b(56) ); + u_xld_or_57: ex6_xld_data(57) <= not( ex6_xld_rot_b(57) and ex6_xld_oth_b(57) ); + u_xld_or_58: ex6_xld_data(58) <= not( ex6_xld_rot_b(58) and ex6_xld_oth_b(58) ); + u_xld_or_59: ex6_xld_data(59) <= not( ex6_xld_rot_b(59) and ex6_xld_oth_b(59) ); + u_xld_or_60: ex6_xld_data(60) <= not( ex6_xld_rot_b(60) and ex6_xld_oth_b(60) ); + u_xld_or_61: ex6_xld_data(61) <= not( ex6_xld_rot_b(61) and ex6_xld_oth_b(61) ); + u_xld_or_62: ex6_xld_data(62) <= not( ex6_xld_rot_b(62) and ex6_xld_oth_b(62) ); + u_xld_or_63: ex6_xld_data(63) <= not( ex6_xld_rot_b(63) and ex6_xld_oth_b(63) ); + + + u_xld_oi: ex6_xld_data_b(0 to 63) <= not( ex6_xld_data (0 to 63) ); + u_dont_do_this: dont_do_this <= not( ex6_xld_data_b(0 to 63) ); + +ex7_xld_data_d <= dont_do_this(64-(2**regmode) to 63); + +ex6_xu_ld_data_b(0 to 63) <= ex6_xld_data_b(0 to 63); + + +DCPerr: tri_direct_err_rpt +generic map(width => 1, expand_type => expand_type) +port map( + vd => vdd, + gd => gnd, + err_in => ex7_ld_par_err(0 to 0), + err_out => dcache_parity(0 to 0) +); + +ex8_ld_par_err_d <= ex7_ld_par_err(0); + +my_spare_latches_d <= not my_spare_latches_q; + + +xu_pc_err_dcache_parity <= dcache_parity(0); + +lsu_xu_ex2_dvc1_st_cmp <= ex2_st_dvc1_cmp_q and ex2_xu_cmp_val_q; +lsu_xu_ex2_dvc2_st_cmp <= ex2_st_dvc2_cmp_q and ex2_xu_cmp_val_q; +lsu_xu_ex8_dvc1_ld_cmp <= gate(ex8_ld_dvc1_cmp_q, not ex8_ld_par_err_q); +lsu_xu_ex8_dvc2_ld_cmp <= gate(ex8_ld_dvc2_cmp_q, not ex8_ld_par_err_q); +lsu_xu_rel_dvc1_en <= rel_dvc1_val_stg2_q; +lsu_xu_rel_dvc1_cmp <= rel_dvc1_cmp_q; +lsu_xu_rel_dvc2_en <= rel_dvc2_val_stg2_q; +lsu_xu_rel_dvc2_cmp <= rel_dvc2_cmp_q; +lsu_xu_rel_dvc_thrd_id <= rel_dvc_tid_stg2_q; + +ex4_256st_data <= ex4_256st_dataFixUp; + +rel_xu_ld_data <= rel_64ld_data(64-(2**regmode) to 63) & rel_xu_ld_par(0 to ((2**regmode)/8)-1); +lsu_xu_ex6_datc_par_err <= ex6_ld_par_err_int; +ex6_ld_par_err <= ex6_ld_par_err_int; + +xu_fu_ex5_load_le <= ex5_rel_le_mode_q; + +abst_scan_out <= gate(abst_scan_out_q, an_ac_scan_dis_dc_b); +time_scan_out <= time_scan_out_q and an_ac_scan_dis_dc_b; +repr_scan_out <= repr_scan_out_q and an_ac_scan_dis_dc_b; +func_scan_out(0) <= func_scan_out_2_q(0) and an_ac_scan_dis_dc_b; +func_scan_out(1) <= func_scan_out_2_q(1) and an_ac_scan_dis_dc_b; +func_scan_out(2) <= func_scan_out_2_q(2) and an_ac_scan_dis_dc_b; + +ex3_opsize_reg: tri_rlmreg_p + generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex3_opsize_offset to ex3_opsize_offset + ex3_opsize_d'length-1), + scout => sov0(ex3_opsize_offset to ex3_opsize_offset + ex3_opsize_d'length-1), + din => ex3_opsize_d, + dout => ex3_opsize_q); + +ex3_ovrd_rot_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex3_ovrd_rot_offset), + scout => sov0(ex3_ovrd_rot_offset), + din => ex3_ovrd_rot_d, + dout => ex3_ovrd_rot_q); + +ex4_le_mode_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_ex3_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex4_le_mode_d, + dout(0) => ex4_le_mode_q); + +ex4_le_mode_sel_reg: tri_rlmreg_p +generic map (width => 16, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_ex3_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex4_le_mode_sel_offset to ex4_le_mode_sel_offset + ex4_le_mode_sel_d'length-1), + scout => sov0(ex4_le_mode_sel_offset to ex4_le_mode_sel_offset + ex4_le_mode_sel_d'length-1), + din => ex4_le_mode_sel_d, + dout => ex4_le_mode_sel_q); + +ex4_be_mode_sel_reg: tri_rlmreg_p +generic map (width => 16, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_ex3_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex4_be_mode_sel_offset to ex4_be_mode_sel_offset + ex4_be_mode_sel_d'length-1), + scout => sov0(ex4_be_mode_sel_offset to ex4_be_mode_sel_offset + ex4_be_mode_sel_d'length-1), + din => ex4_be_mode_sel_d, + dout => ex4_be_mode_sel_q); + +ex5_load_hit_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex5_load_hit_offset), + scout => sov0(ex5_load_hit_offset), + din => ex5_load_hit_d, + dout => ex5_load_hit_q); + +ex6_load_hit_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex5_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex6_load_hit_d, + dout(0) => ex6_load_hit_q); + +ex7_load_hit_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex6_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex7_load_hit_offset), + scout => sov0(ex7_load_hit_offset), + din => ex7_load_hit_d, + dout => ex7_load_hit_q); + +ex2_st_data_reg: tri_rlmreg_p +generic map (width => (2**regmode), init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex2_st_data_offset to ex2_st_data_offset + ex2_st_data_d'length-1), + scout => sov0(ex2_st_data_offset to ex2_st_data_offset + ex2_st_data_d'length-1), + din => ex2_st_data_d, + dout => ex2_st_data_q); + +axu_rel_upd_reg: tri_rlmreg_p +generic map (width => 16, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(axu_rel_upd_offset to axu_rel_upd_offset + axu_rel_upd_d'length-1), + scout => sov0(axu_rel_upd_offset to axu_rel_upd_offset + axu_rel_upd_d'length-1), + din => axu_rel_upd_d, + dout => axu_rel_upd_q); + +rel_data_val_reg: tri_rlmreg_p +generic map (width => 16, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(rel_data_val_offset to rel_data_val_offset + rel_data_val_d'length-1), + scout => sov0(rel_data_val_offset to rel_data_val_offset + rel_data_val_d'length-1), + din => rel_data_val_d, + dout => rel_data_val_q); + +rel_addr_stg_reg: tri_rlmreg_p +generic map (width => 58-uprCClassBit+1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(rel_addr_stg_offset to rel_addr_stg_offset + rel_addr_stg_d'length-1), + scout => sov0(rel_addr_stg_offset to rel_addr_stg_offset + rel_addr_stg_d'length-1), + din => rel_addr_stg_d, + dout => rel_addr_stg_q); + +rel_addr_reg: tri_rlmreg_p +generic map (width => 58-uprCClassBit+1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(rel_addr_offset to rel_addr_offset + rel_addr_d'length-1), + scout => sov0(rel_addr_offset to rel_addr_offset + rel_addr_d'length-1), + din => rel_addr_d, + dout => rel_addr_q); + +ex5_axu_data_sel_reg: tri_rlmreg_p +generic map (width => 3, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex5_axu_data_sel_offset to ex5_axu_data_sel_offset + ex5_axu_data_sel_d'length-1), + scout => sov0(ex5_axu_data_sel_offset to ex5_axu_data_sel_offset + ex5_axu_data_sel_d'length-1), + din => ex5_axu_data_sel_d, + dout => ex5_axu_data_sel_q); + +rel_ex3_data_reg: tri_regk + generic map (width => 256, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_ex2_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_ex3_data_d, + dout => rel_ex3_data_q); + +rel_alg_bit_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel_alg_bit_d, + dout(0) => rel_alg_bit_q); + +ex5_stgpr_data_reg: tri_regk + generic map (width => (2**regmode), init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex5_stgpr_data_d, + dout => ex5_stgpr_data_q); + +ex6_axu_data_sel_0reg: tri_regk + generic map (width => 24, init => 2396745, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex6_axu_data_sel_d(0 to 23), + dout => ex6_axu_data_sel_q(0 to 23)); + +ex6_axu_data_sel_1reg: tri_regk + generic map (width => 24, init => 2396745, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex6_axu_data_sel_d(24 to 47), + dout => ex6_axu_data_sel_q(24 to 47)); + +ex3_stgpr_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex3_stgpr_instr_offset), + scout => sov0(ex3_stgpr_instr_offset), + din => ex3_stgpr_instr_d, + dout => ex3_stgpr_instr_q); + +ex4_stgpr_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex4_stgpr_instr_offset), + scout => sov0(ex4_stgpr_instr_offset), + din => ex4_stgpr_instr_d, + dout => ex4_stgpr_instr_q); + +ex3_sdp_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex3_sdp_instr_offset), + scout => sov0(ex3_sdp_instr_offset), + din => ex3_sdp_instr_d, + dout => ex3_sdp_instr_q); + +ex4_sdp_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex4_sdp_instr_offset), + scout => sov0(ex4_sdp_instr_offset), + din => ex4_sdp_instr_d, + dout => ex4_sdp_instr_q); + +ex5_sdp_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex5_sdp_instr_offset), + scout => sov0(ex5_sdp_instr_offset), + din => ex5_sdp_instr_d, + dout => ex5_sdp_instr_q); + +rot_addr_reg: tri_rlmreg_p + generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(rot_addr_offset to rot_addr_offset + rot_addr_d'length-1), + scout => sov0(rot_addr_offset to rot_addr_offset + rot_addr_d'length-1), + din => rot_addr_d, + dout => rot_addr_q); + +ex4_rot_addr_reg: tri_regk + generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex4_rot_addr_d, + dout => ex4_rot_addr_q); + +rot_sel_non_le_reg: tri_rlmreg_p + generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(rot_sel_non_le_offset to rot_sel_non_le_offset + rot_sel_non_le_d'length-1), + scout => sov0(rot_sel_non_le_offset to rot_sel_non_le_offset + rot_sel_non_le_d'length-1), + din => rot_sel_non_le_d, + dout => rot_sel_non_le_q); + +ex4_rot_sel_non_le_reg: tri_regk + generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex4_rot_sel_non_le_d, + dout => ex4_rot_sel_non_le_q); + +ex2_st_dvc1_cmp_reg: tri_regk + generic map (width => ((2**regmode)/8), init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex2_st_dvc1_cmp_d, + dout => ex2_st_dvc1_cmp_q); + +ex5_dvc1_en_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex5_dvc1_en_offset), + scout => sov0(ex5_dvc1_en_offset), + din => ex5_dvc1_en_d, + dout => ex5_dvc1_en_q); + +ex6_dvc1_en_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex6_dvc1_en_offset), + scout => sov0(ex6_dvc1_en_offset), + din => ex6_dvc1_en_d, + dout => ex6_dvc1_en_q); + +ex7_dvc1_en_reg: tri_rlmreg_p +generic map (width => ((2**regmode)/8), init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex7_dvc1_en_offset to ex7_dvc1_en_offset + ex7_dvc1_en_d'length-1), + scout => sov0(ex7_dvc1_en_offset to ex7_dvc1_en_offset + ex7_dvc1_en_d'length-1), + din => ex7_dvc1_en_d, + dout => ex7_dvc1_en_q); + +rel_dvc1_val_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(rel_dvc1_val_offset), + scout => sov0(rel_dvc1_val_offset), + din => rel_dvc1_val_d, + dout => rel_dvc1_val_q); + +ex8_ld_dvc1_cmp_reg: tri_rlmreg_p + generic map (width => ((2**regmode)/8), init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex8_ld_dvc1_cmp_offset to ex8_ld_dvc1_cmp_offset + ex8_ld_dvc1_cmp_d'length-1), + scout => sov0(ex8_ld_dvc1_cmp_offset to ex8_ld_dvc1_cmp_offset + ex8_ld_dvc1_cmp_d'length-1), + din => ex8_ld_dvc1_cmp_d, + dout => ex8_ld_dvc1_cmp_q); + +rel_dvc1_val_stg_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(rel_dvc1_val_stg_offset), + scout => sov0(rel_dvc1_val_stg_offset), + din => rel_dvc1_val_stg_d, + dout => rel_dvc1_val_stg_q); + +rel_dvc1_val_stg2_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(rel_dvc1_val_stg2_offset), + scout => sov0(rel_dvc1_val_stg2_offset), + din => rel_dvc1_val_stg2_d, + dout => rel_dvc1_val_stg2_q); + +rel_dvc1_cmp_reg: tri_regk + generic map (width => ((2**regmode)/8), init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel4_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_dvc1_cmp_d, + dout => rel_dvc1_cmp_q); + +rel_dvc2_val_stg_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(rel_dvc2_val_stg_offset), + scout => sov0(rel_dvc2_val_stg_offset), + din => rel_dvc2_val_stg_d, + dout => rel_dvc2_val_stg_q); + +rel_dvc2_val_stg2_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(rel_dvc2_val_stg2_offset), + scout => sov0(rel_dvc2_val_stg2_offset), + din => rel_dvc2_val_stg2_d, + dout => rel_dvc2_val_stg2_q); + +rel_dvc2_cmp_reg: tri_regk + generic map (width => ((2**regmode)/8), init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel4_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_dvc2_cmp_d, + dout => rel_dvc2_cmp_q); + +ex2_st_dvc2_cmp_reg: tri_regk + generic map (width => ((2**regmode)/8), init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex2_st_dvc2_cmp_d, + dout => ex2_st_dvc2_cmp_q); + +ex5_dvc2_en_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex5_dvc2_en_offset), + scout => sov0(ex5_dvc2_en_offset), + din => ex5_dvc2_en_d, + dout => ex5_dvc2_en_q); + +ex6_dvc2_en_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex6_dvc2_en_offset), + scout => sov0(ex6_dvc2_en_offset), + din => ex6_dvc2_en_d, + dout => ex6_dvc2_en_q); + +ex7_dvc2_en_reg: tri_rlmreg_p +generic map (width => ((2**regmode)/8), init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex7_dvc2_en_offset to ex7_dvc2_en_offset + ex7_dvc2_en_d'length-1), + scout => sov0(ex7_dvc2_en_offset to ex7_dvc2_en_offset + ex7_dvc2_en_d'length-1), + din => ex7_dvc2_en_d, + dout => ex7_dvc2_en_q); + +rel_dvc2_val_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(rel_dvc2_val_offset), + scout => sov0(rel_dvc2_val_offset), + din => rel_dvc2_val_d, + dout => rel_dvc2_val_q); + +ex8_ld_dvc2_cmp_reg: tri_rlmreg_p + generic map (width => ((2**regmode)/8), init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex8_ld_dvc2_cmp_offset to ex8_ld_dvc2_cmp_offset + ex8_ld_dvc2_cmp_d'length-1), + scout => sov0(ex8_ld_dvc2_cmp_offset to ex8_ld_dvc2_cmp_offset + ex8_ld_dvc2_cmp_d'length-1), + din => ex8_ld_dvc2_cmp_d, + dout => ex8_ld_dvc2_cmp_q); + +ex2_optype32_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex2_optype32_offset), + scout => sov0(ex2_optype32_offset), + din => ex2_optype32_d, + dout => ex2_optype32_q); + +ex2_optype16_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex2_optype16_offset), + scout => sov0(ex2_optype16_offset), + din => ex2_optype16_d, + dout => ex2_optype16_q); + +ex2_optype8_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex2_optype8_offset), + scout => sov0(ex2_optype8_offset), + din => ex2_optype8_d, + dout => ex2_optype8_q); + +ex2_optype4_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex2_optype4_offset), + scout => sov0(ex2_optype4_offset), + din => ex2_optype4_d, + dout => ex2_optype4_q); + +ex2_optype2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex2_optype2_offset), + scout => sov0(ex2_optype2_offset), + din => ex2_optype2_d, + dout => ex2_optype2_q); + +ex2_optype1_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex2_optype1_offset), + scout => sov0(ex2_optype1_offset), + din => ex2_optype1_d, + dout => ex2_optype1_q); + +ex2_p_addr_reg: tri_rlmreg_p + generic map (width => 64-uprCClassBit, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex2_p_addr_offset to ex2_p_addr_offset + ex2_p_addr_d'length-1), + scout => sov0(ex2_p_addr_offset to ex2_p_addr_offset + ex2_p_addr_d'length-1), + din => ex2_p_addr_d, + dout => ex2_p_addr_q); + +ex3_fu_st_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_fu_st_val_d, + dout(0) => ex3_fu_st_val_q); + +frc_p_addr_reg: tri_rlmreg_p + generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(frc_p_addr_offset to frc_p_addr_offset + frc_p_addr_d'length-1), + scout => sov0(frc_p_addr_offset to frc_p_addr_offset + frc_p_addr_d'length-1), + din => frc_p_addr_d, + dout => frc_p_addr_q); + +ex2_store_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex2_store_instr_offset), + scout => sov0(ex2_store_instr_offset), + din => ex2_store_instr_d, + dout => ex2_store_instr_q); + +ex3_store_instr_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_store_instr_d, + dout(0) => ex3_store_instr_q); + +ex3_st_rot_sel_reg: tri_regk +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex3_st_rot_sel_d, + dout => ex3_st_rot_sel_q); + +ex2_axu_op_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex2_axu_op_val_offset), + scout => sov0(ex2_axu_op_val_offset), + din => ex2_axu_op_val_d, + dout => ex2_axu_op_val_q); + +ex3_axu_op_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_axu_op_val_d, + dout(0) => ex3_axu_op_val_q); + +ex4_axu_op_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex4_axu_op_val_offset), + scout => sov0(ex4_axu_op_val_offset), + din => ex4_axu_op_val_d, + dout => ex4_axu_op_val_q); + +ex2_xu_cmp_val_reg: tri_rlmreg_p + generic map (width => (2**regmode)/8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex2_xu_cmp_val_offset to ex2_xu_cmp_val_offset + ex2_xu_cmp_val_d'length-1), + scout => sov0(ex2_xu_cmp_val_offset to ex2_xu_cmp_val_offset + ex2_xu_cmp_val_d'length-1), + din => ex2_xu_cmp_val_d, + dout => ex2_xu_cmp_val_q); + +ex2_saxu_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex2_saxu_instr_offset), + scout => sov0(ex2_saxu_instr_offset), + din => ex2_saxu_instr_d, + dout => ex2_saxu_instr_q); + +ex2_sdp_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex2_sdp_instr_offset), + scout => sov0(ex2_sdp_instr_offset), + din => ex2_sdp_instr_d, + dout => ex2_sdp_instr_q); + +ex2_stgpr_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex2_stgpr_instr_offset), + scout => sov0(ex2_stgpr_instr_offset), + din => ex2_stgpr_instr_d, + dout => ex2_stgpr_instr_q); + +ex3_saxu_instr_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_saxu_instr_d, + dout(0) => ex3_saxu_instr_q); + +ex4_saxu_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex4_saxu_instr_offset), + scout => sov0(ex4_saxu_instr_offset), + din => ex4_saxu_instr_d, + dout => ex4_saxu_instr_q); + +ex4_algebraic_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex4_algebraic_offset), + scout => sov0(ex4_algebraic_offset), + din => ex4_algebraic_d, + dout => ex4_algebraic_q); + +ex2_ovrd_rot_sel_reg: tri_rlmreg_p + generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex2_ovrd_rot_sel_offset to ex2_ovrd_rot_sel_offset + ex2_ovrd_rot_sel_d'length-1), + scout => sov0(ex2_ovrd_rot_sel_offset to ex2_ovrd_rot_sel_offset + ex2_ovrd_rot_sel_d'length-1), + din => ex2_ovrd_rot_sel_d, + dout => ex2_ovrd_rot_sel_q); + +ex3_p_addr_reg: tri_regk + generic map (width => 64-uprCClassBit, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex3_p_addr_d, + dout => ex3_p_addr_q); + +ex4_p_addr_reg: tri_rlmreg_p + generic map (width => 64-uprCClassBit, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex4_p_addr_offset to ex4_p_addr_offset + ex4_p_addr_d'length-1), + scout => sov0(ex4_p_addr_offset to ex4_p_addr_offset + ex4_p_addr_d'length-1), + din => ex4_p_addr_d, + dout => ex4_p_addr_q); + +rel_ex3_par_gen_reg: tri_regk + generic map (width => 32, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_ex2_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_ex3_par_gen_d, + dout => rel_ex3_par_gen_q); + +spr_xucr0_dcdis_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(spr_xucr0_dcdis_offset), + scout => sov0(spr_xucr0_dcdis_offset), + din => spr_xucr0_dcdis_d, + dout => spr_xucr0_dcdis_q); + +clkg_ctl_override_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(clkg_ctl_override_offset), + scout => sov0(clkg_ctl_override_offset), + din => clkg_ctl_override_d, + dout => clkg_ctl_override_q); + +rel_dvc_thrd_id_reg: tri_regk + generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_dvc_thrd_id_d, + dout => rel_dvc_thrd_id_q); + +rel_dvc_tid_stg_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(rel_dvc_tid_stg_offset to rel_dvc_tid_stg_offset + rel_dvc_tid_stg_d'length-1), + scout => sov0(rel_dvc_tid_stg_offset to rel_dvc_tid_stg_offset + rel_dvc_tid_stg_d'length-1), + din => rel_dvc_tid_stg_d, + dout => rel_dvc_tid_stg_q); + +rel_dvc_tid_stg2_reg: tri_regk + generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_dvc_tid_stg2_d, + dout => rel_dvc_tid_stg2_q); + +inj_dcache_parity_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(inj_dcache_parity_offset), + scout => sov0(inj_dcache_parity_offset), + din => inj_dcache_parity_d, + dout => inj_dcache_parity_q); + +ex5_stgpr_dp_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex5_stgpr_dp_instr_offset), + scout => sov0(ex5_stgpr_dp_instr_offset), + din => ex5_stgpr_dp_instr_d, + dout => ex5_stgpr_dp_instr_q); + +ex6_stgpr_dp_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex6_stgpr_dp_instr_offset), + scout => sov0(ex6_stgpr_dp_instr_offset), + din => ex6_stgpr_dp_instr_d, + dout => ex6_stgpr_dp_instr_q); + +ex6_stgpr_dp_data_reg: tri_rlmreg_p + generic map (width => 128, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex5_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex6_stgpr_dp_data_offset to ex6_stgpr_dp_data_offset + ex6_stgpr_dp_data_d'length-1), + scout => sov0(ex6_stgpr_dp_data_offset to ex6_stgpr_dp_data_offset + ex6_stgpr_dp_data_d'length-1), + din => ex6_stgpr_dp_data_d, + dout => ex6_stgpr_dp_data_q); + +ex5_rel_le_mode_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex5_rel_le_mode_offset), + scout => sov0(ex5_rel_le_mode_offset), + din => ex5_rel_le_mode_d, + dout => ex5_rel_le_mode_q); + +ex1_ldst_falign_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex1_ldst_falign_offset), + scout => sov0(ex1_ldst_falign_offset), + din => ex1_ldst_falign_d, + dout => ex1_ldst_falign_q); + +ex4_thrd_id_reg: tri_regk + generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex4_thrd_id_d, + dout => ex4_thrd_id_q); + +ex5_thrd_id_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex5_thrd_id_offset to ex5_thrd_id_offset + ex5_thrd_id_d'length-1), + scout => sov0(ex5_thrd_id_offset to ex5_thrd_id_offset + ex5_thrd_id_d'length-1), + din => ex5_thrd_id_d, + dout => ex5_thrd_id_q); + +axu_rel_val_stg1_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(axu_rel_val_stg1_offset), + scout => sov0(axu_rel_val_stg1_offset), + din => axu_rel_val_stg1_d, + dout => axu_rel_val_stg1_q); + +axu_rel_val_stg2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(axu_rel_val_stg2_offset), + scout => sov0(axu_rel_val_stg2_offset), + din => axu_rel_val_stg2_d, + dout => axu_rel_val_stg2_q); + +axu_rel_val_stg3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(axu_rel_val_stg3_offset), + scout => sov0(axu_rel_val_stg3_offset), + din => axu_rel_val_stg3_d, + dout => axu_rel_val_stg3_q); + +rel_256ld_data_stg1_reg: tri_regk +generic map (width => 256, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel4_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_256ld_data_stg1_d, + dout => rel_256ld_data_stg1_q); + +rel_256ld_data_stg2_reg: tri_rlmreg_p +generic map (width => 256, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel5_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(rel_256ld_data_stg2_offset to rel_256ld_data_stg2_offset + rel_256ld_data_stg2_d'length-1), + scout => sov0(rel_256ld_data_stg2_offset to rel_256ld_data_stg2_offset + rel_256ld_data_stg2_d'length-1), + din => rel_256ld_data_stg2_d, + dout => rel_256ld_data_stg2_q); + +rel_axu_le_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(rel_axu_le_val_offset), + scout => sov0(rel_axu_le_val_offset), + din => rel_axu_le_val_d, + dout => rel_axu_le_val_q); + +rel_axu_le_val_stg1_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(rel_axu_le_val_stg1_offset), + scout => sov0(rel_axu_le_val_stg1_offset), + din => rel_axu_le_val_stg1_d, + dout => rel_axu_le_val_stg1_q); + +dcarr_wren_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel4_ex4_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(dcarr_wren_offset), + scout => sov0(dcarr_wren_offset), + din => dcarr_wren_d, + dout => dcarr_wren_q); + +dat_dbg_arr_reg: tri_rlmreg_p +generic map (width => 13, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => trace_bus_enable_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(dat_dbg_arr_offset to dat_dbg_arr_offset + dat_dbg_arr_d'length-1), + scout => sov0(dat_dbg_arr_offset to dat_dbg_arr_offset + dat_dbg_arr_d'length-1), + din => dat_dbg_arr_d, + dout => dat_dbg_arr_q); + +ld_alg_le_sel_reg: tri_rlmreg_p +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ld_alg_le_sel_offset to ld_alg_le_sel_offset + ld_alg_le_sel_d'length-1), + scout => sov0(ld_alg_le_sel_offset to ld_alg_le_sel_offset + ld_alg_le_sel_d'length-1), + din => ld_alg_le_sel_d, + dout => ld_alg_le_sel_q); + +ex4_ld_alg_le_sel_reg: tri_regk +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex4_ld_alg_le_sel_d, + dout => ex4_ld_alg_le_sel_q); + +ex1_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex1_stg_act_offset), + scout => sov0(ex1_stg_act_offset), + din => ex1_stg_act_d, + dout => ex1_stg_act_q); + +ex2_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex2_stg_act_offset), + scout => sov0(ex2_stg_act_offset), + din => ex2_stg_act_d, + dout => ex2_stg_act_q); + +ex3_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex3_stg_act_offset), + scout => sov0(ex3_stg_act_offset), + din => ex3_stg_act_d, + dout => ex3_stg_act_q); + +ex4_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex4_stg_act_offset), + scout => sov0(ex4_stg_act_offset), + din => ex4_stg_act_d, + dout => ex4_stg_act_q); + +ex5_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex5_stg_act_offset), + scout => sov0(ex5_stg_act_offset), + din => ex5_stg_act_d, + dout => ex5_stg_act_q); + +ex6_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex6_stg_act_offset), + scout => sov0(ex6_stg_act_offset), + din => ex6_stg_act_d, + dout => ex6_stg_act_q); + +rel1_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(rel1_stg_act_offset), + scout => sov0(rel1_stg_act_offset), + din => rel1_stg_act_d, + dout => rel1_stg_act_q); + +rel2_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(rel2_stg_act_offset), + scout => sov0(rel2_stg_act_offset), + din => rel2_stg_act_d, + dout => rel2_stg_act_q); + +rel3_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(rel3_stg_act_offset), + scout => sov0(rel3_stg_act_offset), + din => rel3_stg_act_d, + dout => rel3_stg_act_q); + +rel4_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(rel4_stg_act_offset), + scout => sov0(rel4_stg_act_offset), + din => rel4_stg_act_d, + dout => rel4_stg_act_q); + +rel5_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(rel5_stg_act_offset), + scout => sov0(rel5_stg_act_offset), + din => rel5_stg_act_d, + dout => rel5_stg_act_q); + +rel2_ex2_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(rel2_ex2_stg_act_offset), + scout => sov0(rel2_ex2_stg_act_offset), + din => rel2_ex2_stg_act_d, + dout => rel2_ex2_stg_act_q); + +rel3_ex3_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(rel3_ex3_stg_act_offset), + scout => sov0(rel3_ex3_stg_act_offset), + din => rel3_ex3_stg_act_d, + dout => rel3_ex3_stg_act_q); + +rel4_ex4_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(rel4_ex4_stg_act_offset), + scout => sov0(rel4_ex4_stg_act_offset), + din => rel4_ex4_stg_act_d, + dout => rel4_ex4_stg_act_q); + +ex8_ld_par_err_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex8_ld_par_err_offset), + scout => sov0(ex8_ld_par_err_offset), + din => ex8_ld_par_err_d, + dout => ex8_ld_par_err_q); + +my_spare0_lcb : entity tri.tri_lcbnd(tri_lcbnd) +generic map (expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + d1clk => my_spare0_d1clk, + d2clk => my_spare0_d2clk, + lclk => my_spare0_lclk); +my_spare_latches_reg: entity tri.tri_inv_nlats(tri_inv_nlats) +generic map (width => 8, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + lclk => my_spare0_lclk, + d1clk => my_spare0_d1clk, + d2clk => my_spare0_d2clk, + scanin => siv0(my_spare_latches_offset to my_spare_latches_offset + my_spare_latches_d'length-1), + scanout => sov0(my_spare_latches_offset to my_spare_latches_offset + my_spare_latches_d'length-1), + d => my_spare_latches_d, + qb => my_spare_latches_q); + +rel_data_reg: tri_rlmreg_p +generic map (width => 256, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv1(rel_data_offset to rel_data_offset + rel_data_d'length-1), + scout => sov1(rel_data_offset to rel_data_offset + rel_data_d'length-1), + din => rel_data_d, + dout => rel_data_q); + +rel_algebraic_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv1(rel_algebraic_offset), + scout => sov1(rel_algebraic_offset), + din => rel_algebraic_d, + dout => rel_algebraic_q); + +rel_rot_sel_reg: tri_rlmreg_p +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv1(rel_rot_sel_offset to rel_rot_sel_offset + rel_rot_sel_d'length-1), + scout => sov1(rel_rot_sel_offset to rel_rot_sel_offset + rel_rot_sel_d'length-1), + din => rel_rot_sel_d, + dout => rel_rot_sel_q); + +rel_op_size_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv1(rel_op_size_offset to rel_op_size_offset + rel_op_size_d'length-1), + scout => sov1(rel_op_size_offset to rel_op_size_offset + rel_op_size_d'length-1), + din => rel_op_size_d, + dout => rel_op_size_q); + +rel_le_mode_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv1(rel_le_mode_offset), + scout => sov1(rel_le_mode_offset), + din => rel_le_mode_d, + dout => rel_le_mode_q); + +rel_dvc1_en_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv1(rel_dvc1_en_offset), + scout => sov1(rel_dvc1_en_offset), + din => rel_dvc1_en_d, + dout => rel_dvc1_en_q); + +rel_dvc2_en_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv1(rel_dvc2_en_offset), + scout => sov1(rel_dvc2_en_offset), + din => rel_dvc2_en_d, + dout => rel_dvc2_en_q); + +rel_upd_gpr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv1(rel_upd_gpr_offset), + scout => sov1(rel_upd_gpr_offset), + din => rel_upd_gpr_d, + dout => rel_upd_gpr_q); + +rel_axu_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv1(rel_axu_val_offset), + scout => sov1(rel_axu_val_offset), + din => rel_axu_val_d, + dout => rel_axu_val_q); + +rel_ci_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv1(rel_ci_offset), + scout => sov1(rel_ci_offset), + din => rel_ci_d, + dout => rel_ci_q); + +rel_ci_dly_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel_ci_dly_d, + dout(0) => rel_ci_dly_q); + +rel_thrd_id_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv1(rel_thrd_id_offset to rel_thrd_id_offset + rel_thrd_id_d'length-1), + scout => sov1(rel_thrd_id_offset to rel_thrd_id_offset + rel_thrd_id_d'length-1), + din => rel_thrd_id_d, + dout => rel_thrd_id_q); + +rel_data_val_stg_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv1(rel_data_val_stg_offset), + scout => sov1(rel_data_val_stg_offset), + din => rel_data_val_stg_d, + dout => rel_data_val_stg_q); + +rel_data_val_stg_dly_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel_data_val_stg_dly_d, + dout(0) => rel_data_val_stg_dly_q); + +spr_dvc1_dbg_reg: tri_ser_rlmreg_p +generic map (width => (2**regmode), init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_dvc1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv1(spr_dvc1_dbg_offset to spr_dvc1_dbg_offset + spr_dvc1_dbg_d'length-1), + scout => sov1(spr_dvc1_dbg_offset to spr_dvc1_dbg_offset + spr_dvc1_dbg_d'length-1), + din => spr_dvc1_dbg_d, + dout => spr_dvc1_dbg_q); + +spr_dvc2_dbg_reg: tri_ser_rlmreg_p +generic map (width => (2**regmode), init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_dvc2_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv1(spr_dvc2_dbg_offset to spr_dvc2_dbg_offset + spr_dvc2_dbg_d'length-1), + scout => sov1(spr_dvc2_dbg_offset to spr_dvc2_dbg_offset + spr_dvc2_dbg_d'length-1), + din => spr_dvc2_dbg_d, + dout => spr_dvc2_dbg_q); + +ex7_xld_data_reg: tri_regk +generic map (width => (2**regmode), init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex6_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex7_xld_data_d, + dout => ex7_xld_data_q); + +trace_bus_enable_latch : tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 0) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv1(trace_bus_enable_offset), + scout => sov1(trace_bus_enable_offset), + din => pc_xu_trace_bus_enable, + dout => trace_bus_enable_q); + +dat_debug_mux_ctrls_reg: tri_rlmreg_p + generic map (width => 2, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv1(dat_debug_mux_ctrls_offset to dat_debug_mux_ctrls_offset + dat_debug_mux_ctrls_q'length-1), + scout => sov1(dat_debug_mux_ctrls_offset to dat_debug_mux_ctrls_offset + dat_debug_mux_ctrls_q'length-1), + din => lsudat_debug_mux_ctrls, + dout => dat_debug_mux_ctrls_q); + +dat_dbg_st_dat_reg: tri_rlmreg_p + generic map (width => 64, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => trace_bus_enable_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv1(dat_dbg_st_dat_offset to dat_dbg_st_dat_offset + dat_dbg_st_dat_d'length-1), + scout => sov1(dat_dbg_st_dat_offset to dat_dbg_st_dat_offset + dat_dbg_st_dat_d'length-1), + din => dat_dbg_st_dat_d, + dout => dat_dbg_st_dat_q); + +abist_reg: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 21, needs_sreset => 0) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => pc_xu_abist_ena_dc, + thold_b => abst_sl_thold_0_b, + sg => sg_0, + forcee => abst_sl_force, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + d_mode => d_mode_dc, + scin => abist_siv(1 to 21), + scout => abist_sov(1 to 21), + din(0 to 1) => pc_xu_abist_g6t_bw, + din(2 to 5) => pc_xu_abist_di_g6t_2r, + din(6) => pc_xu_abist_wl512_comp_ena, + din(7 to 10) => pc_xu_abist_dcomp_g6t_2r, + din(11 to 19) => pc_xu_abist_raddr_0, + din(20) => pc_xu_abist_g6t_r_wb, + dout(0 to 1) => pc_xu_abist_g6t_bw_q, + dout(2 to 5) => pc_xu_abist_di_g6t_2r_q, + dout(6) => pc_xu_abist_wl512_comp_ena_q, + dout(7 to 10) => pc_xu_abist_dcomp_g6t_2r_q, + dout(11 to 19) => pc_xu_abist_raddr_0_q, + dout(20) => pc_xu_abist_g6t_r_wb_q); + +perv_2to1_reg: tri_plat + generic map (width => 9, expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_xu_ccflush_dc, + din(0) => func_nsl_thold_2, + din(1) => func_sl_thold_2, + din(2) => ary_nsl_thold_2, + din(3) => abst_sl_thold_2, + din(4) => time_sl_thold_2, + din(5) => repr_sl_thold_2, + din(6) => bolt_sl_thold_2, + din(7) => sg_2, + din(8) => fce_2, + q(0) => func_nsl_thold_1, + q(1) => func_sl_thold_1, + q(2) => ary_nsl_thold_1, + q(3) => abst_sl_thold_1, + q(4) => time_sl_thold_1, + q(5) => repr_sl_thold_1, + q(6) => bolt_sl_thold_1, + q(7) => sg_1, + q(8) => fce_1); + +perv_1to0_reg: tri_plat + generic map (width => 9, expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_xu_ccflush_dc, + din(0) => func_nsl_thold_1, + din(1) => func_sl_thold_1, + din(2) => ary_nsl_thold_1, + din(3) => abst_sl_thold_1, + din(4) => time_sl_thold_1, + din(5) => repr_sl_thold_1, + din(6) => bolt_sl_thold_1, + din(7) => sg_1, + din(8) => fce_1, + q(0) => func_nsl_thold_0, + q(1) => func_sl_thold_0, + q(2) => ary_nsl_thold_0, + q(3) => abst_sl_thold_0, + q(4) => time_sl_thold_0, + q(5) => repr_sl_thold_0, + q(6) => bolt_sl_thold_0, + q(7) => sg_0, + q(8) => fce_0); + +perv_lcbor_func_sl: tri_lcbor + generic map (expand_type => expand_type) +port map (clkoff_b => clkoff_dc_b, + thold => func_sl_thold_0, + sg => sg_0, + act_dis => tidn, + forcee => func_sl_force, + thold_b => func_sl_thold_0_b); + +perv_lcbor_func_nsl: tri_lcbor + generic map (expand_type => expand_type) +port map (clkoff_b => clkoff_dc_b, + thold => func_nsl_thold_0, + sg => fce_0, + act_dis => tidn, + forcee => func_nsl_force, + thold_b => func_nsl_thold_0_b); + +perv_lcbor_abst_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_dc_b, + thold => abst_sl_thold_0, + sg => sg_0, + act_dis => tidn, + forcee => abst_sl_force, + thold_b => abst_sl_thold_0_b); + +slat_force <= sg_0; +abst_slat_thold_b <= NOT abst_sl_thold_0; +time_slat_thold_b <= NOT time_sl_thold_0; +repr_slat_thold_b <= NOT repr_sl_thold_0; +func_slat_thold_b <= NOT func_sl_thold_0; + +perv_lcbs_abst: tri_lcbs + generic map (expand_type => expand_type ) + port map ( + vd => vdd, + gd => gnd, + delay_lclkr => delay_lclkr_dc(5), + nclk => nclk, + forcee => slat_force, + thold_b => abst_slat_thold_b, + dclk => abst_slat_d2clk, + lclk => abst_slat_lclk ); + +perv_abst_stg: tri_slat_scan + generic map (width => 4, init => "0000", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => abst_slat_d2clk, + lclk => abst_slat_lclk, + scan_in(0 to 1) => abst_scan_in, + scan_in(2 to 3) => abst_scan_out_int, + scan_out(0 to 1) => abst_scan_in_q, + scan_out(2 to 3) => abst_scan_out_q ); + +perv_lcbs_time: tri_lcbs + generic map (expand_type => expand_type ) + port map ( + vd => vdd, + gd => gnd, + delay_lclkr => delay_lclkr_dc(5), + nclk => nclk, + forcee => slat_force, + thold_b => time_slat_thold_b, + dclk => time_slat_d2clk, + lclk => time_slat_lclk ); + +perv_time_stg: tri_slat_scan + generic map (width => 2, init => "00", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => time_slat_d2clk, + lclk => time_slat_lclk, + scan_in(0) => time_scan_in, + scan_in(1) => time_scan_out_int, + scan_out(0) => time_scan_in_q, + scan_out(1) => time_scan_out_q ); + +perv_lcbs_repr: tri_lcbs + generic map (expand_type => expand_type ) + port map ( + vd => vdd, + gd => gnd, + delay_lclkr => delay_lclkr_dc(5), + nclk => nclk, + forcee => slat_force, + thold_b => repr_slat_thold_b, + dclk => repr_slat_d2clk, + lclk => repr_slat_lclk ); + +perv_repr_stg: tri_slat_scan + generic map (width => 2, init => "00", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => repr_slat_d2clk, + lclk => repr_slat_lclk, + scan_in(0) => repr_scan_in, + scan_in(1) => repr_scan_out_int, + scan_out(0) => repr_scan_in_q, + scan_out(1) => repr_scan_out_q ); + +perv_lcbs_func: tri_lcbs + generic map (expand_type => expand_type ) + port map ( + vd => vdd, + gd => gnd, + delay_lclkr => delay_lclkr_dc(5), + nclk => nclk, + forcee => slat_force, + thold_b => func_slat_thold_b, + dclk => func_slat_d2clk, + lclk => func_slat_lclk ); + +perv_func_stg: tri_slat_scan + generic map (width => 12, init => (1 to 12=>'0'), expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => func_slat_d2clk, + lclk => func_slat_lclk, + scan_in(0) => func_scan_in(0), + scan_in(1) => func_scan_in(1), + scan_in(2) => func_scan_in(2), + scan_in(3) => func_scan_out_int(0), + scan_in(4) => func_scan_out_int(1), + scan_in(5) => func_scan_out_int(2), + scan_in(6) => func_scan_in_q(0), + scan_in(7) => func_scan_in_q(1), + scan_in(8) => func_scan_in_q(2), + scan_in(9) => func_scan_out_q(0), + scan_in(10) => func_scan_out_q(1), + scan_in(11) => func_scan_out_q(2), + scan_out(0) => func_scan_in_q(0), + scan_out(1) => func_scan_in_q(1), + scan_out(2) => func_scan_in_q(2), + scan_out(3) => func_scan_out_q(0), + scan_out(4) => func_scan_out_q(1), + scan_out(5) => func_scan_out_q(2), + scan_out(6) => func_scan_in_2_q(0), + scan_out(7) => func_scan_in_2_q(1), + scan_out(8) => func_scan_in_2_q(2), + scan_out(9) => func_scan_out_2_q(0), + scan_out(10)=> func_scan_out_2_q(1), + scan_out(11)=> func_scan_out_2_q(2) + ); + +siv0 <= sov0(1 to scan_right0) & func_scan_in_2_q(0); +func_scan_out_int(0) <= sov0(0); + +siv1 <= sov1(1 to scan_right1) & func_scan_in_2_q(1); +func_scan_out_int(1) <= sov1(0); + +abist_siv <= abist_sov(1 to abist_sov'right) & abst_scan_in_q(0); +abst_scan_out_int(0) <= abist_sov(0); + +end xuq_lsu_data; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_data_ld.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_data_ld.vhdl new file mode 100644 index 0000000..5841a39 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_data_ld.vhdl @@ -0,0 +1,507 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ibm, ieee, work, tri, support; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use tri.tri_latches_pkg.all; +use support.power_logic_pkg.all; + + + +entity xuq_lsu_data_ld is +generic(expand_type : integer := 2; + regmode : integer := 6; + l_endian_m : integer := 1); +port( + + ex3_stg_act :in std_ulogic; + ex4_stg_act :in std_ulogic; + ex5_stg_act :in std_ulogic; + + ex3_opsize :in std_ulogic_vector(0 to 5); + ex3_algebraic :in std_ulogic; + ex4_ld_rot_sel :in std_ulogic_vector(0 to 4); + ex4_ld_alg_sel :in std_ulogic_vector(0 to 4); + ex4_le_mode :in std_ulogic; + ex5_ld_data :in std_ulogic_vector(0 to 255); + ex5_ld_data_par :in std_ulogic_vector(0 to 31); + ex6_par_chk_val :in std_ulogic; + + trace_bus_enable :in std_ulogic; + dat_debug_mux_ctrls :in std_ulogic_vector(2 to 3); + dat_dbg_ld_dat :out std_ulogic_vector(0 to 63); + + ld_swzl_data :out std_ulogic_vector(0 to 255); + ex6_ld_alg_bit :out std_ulogic_vector(0 to 5); + ex6_ld_dvc_byte_mask :out std_ulogic_vector((64-(2**regmode))/8 to 7); + + ex6_ld_par_err :out std_ulogic; + ex7_ld_par_err :out std_ulogic_vector(0 to 1); + + vdd :inout power_logic; + gnd :inout power_logic; + nclk :in clk_logic; + sg_0 :in std_ulogic; + func_sl_thold_0_b :in std_ulogic; + func_sl_force :in std_ulogic; + func_nsl_thold_0_b :in std_ulogic; + func_nsl_force :in std_ulogic; + d_mode_dc :in std_ulogic; + delay_lclkr_dc :in std_ulogic; + mpw1_dc_b :in std_ulogic; + mpw2_dc_b :in std_ulogic; + scan_in :in std_ulogic; + scan_out :out std_ulogic +); +-- synopsys translate_off +-- synopsys translate_on +end xuq_lsu_data_ld; +architecture xuq_lsu_data_ld of xuq_lsu_data_ld is + + +constant ex5_opsize_offset :natural := 0; +constant ex5_algebraic_offset :natural := ex5_opsize_offset + 6; +constant rotate_select_offset :natural := ex5_algebraic_offset + 1; +constant le_mode_select_offset :natural := rotate_select_offset + 5; +constant ex6_ld_data_par_offset :natural := le_mode_select_offset + 1; +constant ex5_ld_alg_sel_offset :natural := ex6_ld_data_par_offset + 32; +constant ex7_ld_par_err_offset :natural := ex5_ld_alg_sel_offset + 5; +constant my_spare_latches_offset :natural := ex7_ld_par_err_offset + 2; +constant scan_right :natural := my_spare_latches_offset + 14 - 1; + + +signal le_mode_select_d :std_ulogic; +signal le_mode_select_q :std_ulogic; +signal ex4_opsize_d :std_ulogic_vector(0 to 5); +signal ex4_opsize_q :std_ulogic_vector(0 to 5); +signal ex5_opsize_d :std_ulogic_vector(0 to 5); +signal ex5_opsize_q :std_ulogic_vector(0 to 5); +signal ex6_opsize_d :std_ulogic_vector(2 to 5); +signal ex6_opsize_q :std_ulogic_vector(2 to 5); +signal ex4_algebraic_d :std_ulogic; +signal ex4_algebraic_q :std_ulogic; +signal ex5_algebraic_d :std_ulogic; +signal ex5_algebraic_q :std_ulogic; +signal ex6_ld_data :std_ulogic_vector(0 to 255); +signal ex6_ld_data_rot :std_ulogic_vector(0 to 255); +signal rotate_select_d :std_ulogic_vector(0 to 4); +signal rotate_select_q :std_ulogic_vector(0 to 4); +signal ex6_ld_data_par_d :std_ulogic_vector(0 to 31); +signal ex6_ld_data_par_q :std_ulogic_vector(0 to 31); +signal par_err_byte :std_ulogic_vector(0 to 31); +signal par_err_det :std_ulogic; +signal ex5_ld_alg_sel_d :std_ulogic_vector(0 to 4); +signal ex5_ld_alg_sel_q :std_ulogic_vector(0 to 4); +signal ex7_ld_par_err_d :std_ulogic_vector(0 to 1); +signal ex7_ld_par_err_q :std_ulogic_vector(0 to 1); +signal ex6_par_err_det1_b :std_ulogic; +signal ex6_par_err_det1 :std_ulogic; +signal ex6_par_err_det2_b :std_ulogic; +signal ex6_par_err_det2 :std_ulogic; +signal ld_byte_mask :std_ulogic_vector(0 to 7); +signal my_spare0_lclk :clk_logic; +signal my_spare0_d1clk :std_ulogic; +signal my_spare0_d2clk :std_ulogic; +signal my_spare_latches_d :std_ulogic_vector(0 to 13); +signal my_spare_latches_q :std_ulogic_vector(0 to 13); +signal ex6_load_data0 :std_ulogic_vector(0 to 63); +signal ex6_load_data1 :std_ulogic_vector(0 to 63); +signal ex6_load_data2 :std_ulogic_vector(0 to 63); +signal ex6_load_data3 :std_ulogic_vector(0 to 63); +signal dat_dbg_ld_dat_d :std_ulogic_vector(0 to 63); +signal dat_dbg_ld_dat_q :std_ulogic_vector(0 to 63); + +signal tiup :std_ulogic; +signal siv :std_ulogic_vector(0 to scan_right); +signal sov :std_ulogic_vector(0 to scan_right); +signal rot_scan_in :std_ulogic_vector(0 to 7); +signal rot_scan_out :std_ulogic_vector(0 to 7); + + + +begin + + +tiup <= '1'; + +ex4_opsize_d <= ex3_opsize; +ex5_opsize_d <= ex4_opsize_q; +ex6_opsize_d <= ex5_opsize_q(2 to 5); +ex4_algebraic_d <= ex3_algebraic; +ex5_algebraic_d <= ex4_algebraic_q; +rotate_select_d <= ex4_ld_rot_sel; +ex5_ld_alg_sel_d <= ex4_ld_alg_sel; +le_mode_select_d <= ex4_le_mode; +ex6_ld_data_par_d <= ex5_ld_data_par; + + +ldDbgData : for byte in 0 to 7 generate begin + ex6_load_data0(byte*8 to (byte*8)+7) <= ex6_ld_data(byte+0) & ex6_ld_data(byte+32) & ex6_ld_data(byte+64) & ex6_ld_data(byte+96) & + ex6_ld_data(byte+128) & ex6_ld_data(byte+160) & ex6_ld_data(byte+192) & ex6_ld_data(byte+224); + ex6_load_data1(byte*8 to (byte*8)+7) <= ex6_ld_data(8+byte+0) & ex6_ld_data(8+byte+32) & ex6_ld_data(8+byte+64) & ex6_ld_data(8+byte+96) & + ex6_ld_data(8+byte+128) & ex6_ld_data(8+byte+160) & ex6_ld_data(8+byte+192) & ex6_ld_data(8+byte+224); + ex6_load_data2(byte*8 to (byte*8)+7) <= ex6_ld_data(16+byte+0) & ex6_ld_data(16+byte+32) & ex6_ld_data(16+byte+64) & ex6_ld_data(16+byte+96) & + ex6_ld_data(16+byte+128) & ex6_ld_data(16+byte+160) & ex6_ld_data(16+byte+192) & ex6_ld_data(16+byte+224); + ex6_load_data3(byte*8 to (byte*8)+7) <= ex6_ld_data(24+byte+0) & ex6_ld_data(24+byte+32) & ex6_ld_data(24+byte+64) & ex6_ld_data(24+byte+96) & + ex6_ld_data(24+byte+128) & ex6_ld_data(24+byte+160) & ex6_ld_data(24+byte+192) & ex6_ld_data(24+byte+224); +end generate ldDbgData; + +with dat_debug_mux_ctrls(2 to 3) select + dat_dbg_ld_dat_d <= ex6_load_data0 when "00", + ex6_load_data1 when "01", + ex6_load_data2 when "10", + ex6_load_data3 when others; + + +par_Bdet : for t in 0 to 31 generate begin + par_err_byte(t) <= ex6_ld_data(t+0) xor ex6_ld_data(t+32) xor ex6_ld_data(t+64) xor ex6_ld_data(t+96) xor + ex6_ld_data(t+128) xor ex6_ld_data(t+160) xor ex6_ld_data(t+192) xor ex6_ld_data(t+224) xor + ex6_ld_data_par_q(t); +end generate par_Bdet; + +par_err_det <= or_reduce(par_err_byte); + +ex6par_err1_nand2 : ex6_par_err_det1_b <= not (par_err_det and ex6_par_chk_val); +ex6par_err1_inv : ex6_par_err_det1 <= not (ex6_par_err_det1_b); + +ex7_ld_par_err_d <= (others=>ex6_par_err_det1); + + +l1dcrotr : for bit in 0 to 7 generate begin + sgrp : if (bit = 0) generate + begin + bits : entity work.xuq_lsu_data_rot32s_ru(xuq_lsu_data_rot32s_ru) + generic map(expand_type => expand_type) + port map ( + opsize => ex5_opsize_q, + le => le_mode_select_q, + rotate_sel => rotate_select_q, + algebraic => ex5_algebraic_q, + algebraic_sel => ex5_ld_alg_sel_q, + + data => ex5_ld_data(bit*32 to (bit*32)+31), + data_latched => ex6_ld_data(bit*32 to (bit*32)+31), + data_rot => ex6_ld_data_rot(bit*32 to (bit*32)+31), + algebraic_bit => ex6_ld_alg_bit, + + vdd => vdd, + gnd => gnd, + nclk => nclk, + act => ex5_stg_act, + func_sl_force => func_sl_force, + delay_lclkr_dc => delay_lclkr_dc, + mpw1_dc_b => mpw1_dc_b, + mpw2_dc_b => mpw2_dc_b, + func_sl_thold_0_b => func_sl_thold_0_b, + sg_0 => sg_0, + scan_in => rot_scan_in(bit), + scan_out => rot_scan_out(bit) + ); + end generate sgrp; + grp : if (bit /= 0) generate + begin + bits : entity work.xuq_lsu_data_rot32_ru(xuq_lsu_data_rot32_ru) + generic map(expand_type => expand_type) + port map ( + opsize => ex5_opsize_q, + le => le_mode_select_q, + rotate_sel => rotate_select_q, + + data => ex5_ld_data(bit*32 to (bit*32)+31), + data_latched => ex6_ld_data(bit*32 to (bit*32)+31), + data_rot => ex6_ld_data_rot(bit*32 to (bit*32)+31), + + vdd => vdd, + gnd => gnd, + nclk => nclk, + act => ex5_stg_act, + func_sl_force => func_sl_force, + delay_lclkr_dc => delay_lclkr_dc, + mpw1_dc_b => mpw1_dc_b, + mpw2_dc_b => mpw2_dc_b, + func_sl_thold_0_b => func_sl_thold_0_b, + sg_0 => sg_0, + scan_in => rot_scan_in(bit), + scan_out => rot_scan_out(bit) + ); + end generate grp; +end generate l1dcrotr; + + + + +with ex6_opsize_q select + ld_byte_mask <= x"01" when "0001", + x"03" when "0010", + x"0F" when "0100", + x"FF" when others; + +ex6_ld_dvc_byte_mask <= ld_byte_mask((64-(2**regmode))/8 to 7); + +ld256data : for t in 0 to 31 generate begin + ld_swzl_data(t*8 to (t*8)+7) <= ex6_ld_data_rot(t) & ex6_ld_data_rot(t+32) & ex6_ld_data_rot(t+64) & ex6_ld_data_rot(t+96) & + ex6_ld_data_rot(t+128) & ex6_ld_data_rot(t+160) & ex6_ld_data_rot(t+192) & ex6_ld_data_rot(t+224); +end generate ld256data; + + +my_spare_latches_d <= not my_spare_latches_q; + + + +ex6par_err2_nand2 : ex6_par_err_det2_b <= not (par_err_det and ex6_par_chk_val); +ex6par_err2_inv : ex6_par_err_det2 <= not (ex6_par_err_det2_b); + +ex6_ld_par_err <= ex6_par_err_det2; +ex7_ld_par_err <= ex7_ld_par_err_q; + +dat_dbg_ld_dat <= dat_dbg_ld_dat_q; + +ex4_opsize_reg: tri_regk + generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex4_opsize_d, + dout => ex4_opsize_q); + +ex5_opsize_reg: tri_rlmreg_p + generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_opsize_offset to ex5_opsize_offset + ex5_opsize_d'length-1), + scout => sov(ex5_opsize_offset to ex5_opsize_offset + ex5_opsize_d'length-1), + din => ex5_opsize_d, + dout => ex5_opsize_q); + +ex6_opsize_reg: tri_regk + generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex5_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex6_opsize_d, + dout => ex6_opsize_q); + +ex4_algebraic_reg: tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex4_algebraic_d, + dout(0) => ex4_algebraic_q); + +ex5_algebraic_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_algebraic_offset), + scout => sov(ex5_algebraic_offset), + din => ex5_algebraic_d, + dout => ex5_algebraic_q); + +rotate_select_reg: tri_rlmreg_p + generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rotate_select_offset to rotate_select_offset + rotate_select_d'length-1), + scout => sov(rotate_select_offset to rotate_select_offset + rotate_select_d'length-1), + din => rotate_select_d, + dout => rotate_select_q); + +le_mode_select_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(le_mode_select_offset), + scout => sov(le_mode_select_offset), + din => le_mode_select_d, + dout => le_mode_select_q); + +ex6_ld_data_par_reg: tri_rlmreg_p +generic map (width => 32, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex5_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_ld_data_par_offset to ex6_ld_data_par_offset + ex6_ld_data_par_d'length-1), + scout => sov(ex6_ld_data_par_offset to ex6_ld_data_par_offset + ex6_ld_data_par_d'length-1), + din => ex6_ld_data_par_d, + dout => ex6_ld_data_par_q); + +ex5_ld_alg_sel_reg: tri_rlmreg_p +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_ld_alg_sel_offset to ex5_ld_alg_sel_offset + ex5_ld_alg_sel_d'length-1), + scout => sov(ex5_ld_alg_sel_offset to ex5_ld_alg_sel_offset + ex5_ld_alg_sel_d'length-1), + din => ex5_ld_alg_sel_d, + dout => ex5_ld_alg_sel_q); + +ex7_ld_par_err_reg: tri_rlmreg_p + generic map (width => 2, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex7_ld_par_err_offset to ex7_ld_par_err_offset + ex7_ld_par_err_d'length-1), + scout => sov(ex7_ld_par_err_offset to ex7_ld_par_err_offset + ex7_ld_par_err_d'length-1), + din => ex7_ld_par_err_d, + dout => ex7_ld_par_err_q); + +my_spare0_lcb : entity tri.tri_lcbnd(tri_lcbnd) +generic map (expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + d1clk => my_spare0_d1clk, + d2clk => my_spare0_d2clk, + lclk => my_spare0_lclk); +my_spare_latches_reg: entity tri.tri_inv_nlats(tri_inv_nlats) +generic map (width => 14, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + lclk => my_spare0_lclk, + d1clk => my_spare0_d1clk, + d2clk => my_spare0_d2clk, + scanin => siv(my_spare_latches_offset to my_spare_latches_offset + my_spare_latches_d'length-1), + scanout => sov(my_spare_latches_offset to my_spare_latches_offset + my_spare_latches_d'length-1), + d => my_spare_latches_d, + qb => my_spare_latches_q); + +dat_dbg_ld_dat_reg: tri_regk + generic map (width => 64, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => trace_bus_enable, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => dat_dbg_ld_dat_d, + dout => dat_dbg_ld_dat_q); + +siv(0 to scan_right) <= sov(1 to scan_right) & scan_in; +rot_scan_in(0 to 7) <= rot_scan_out(1 to 7) & sov(0); +scan_out <= rot_scan_out(0); + +end xuq_lsu_data_ld; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_data_rot32_lu.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_data_rot32_lu.vhdl new file mode 100644 index 0000000..9b6f0bc --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_data_rot32_lu.vhdl @@ -0,0 +1,233 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ibm, ieee, work, tri, support; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use tri.tri_latches_pkg.all; +use support.power_logic_pkg.all; + + +entity xuq_lsu_data_rot32_lu is +generic(l_endian_m : integer := 1); +port( + + vdd :inout power_logic; + gnd :inout power_logic; + + rot_sel1 :in std_ulogic_vector(0 to 31); + rot_sel2 :in std_ulogic_vector(0 to 31); + rot_sel3 :in std_ulogic_vector(0 to 31); + rot_sel2_le :in std_ulogic_vector(0 to 31); + rot_sel3_le :in std_ulogic_vector(0 to 31); + rot_data :in std_ulogic_vector(0 to 127); + + data256_rot_le :out std_ulogic_vector(0 to 127); + data256_rot :out std_ulogic_vector(0 to 127) +); +-- synopsys translate_off +-- synopsys translate_on +end xuq_lsu_data_rot32_lu; +architecture xuq_lsu_data_rot32_lu of xuq_lsu_data_rot32_lu is + + + + +signal rot3210 :std_ulogic_vector(0 to 127); +signal rotC840 :std_ulogic_vector(0 to 127); +signal rot10 :std_ulogic_vector(0 to 127); +signal le_rot_data :std_ulogic_vector(0 to 127); +signal le_rotC840 :std_ulogic_vector(0 to 127); +signal le_rot3210 :std_ulogic_vector(0 to 127); + +begin + + + +le_mode_on : if l_endian_m = 1 generate begin + + lvl1rot: for byte in 0 to 31 generate begin + bit: for b in 0 to 3 generate + signal muxIn :std_ulogic_vector(0 to 3); + signal muxSel :std_ulogic_vector(0 to 3); + begin + muxIn <= rot_data(byte+(b*32)) & rot_data((((16+byte) mod 32))+(b*32)) & + rot_data(((31 - byte))+(b*32)) & rot_data(((31 - ((16+byte) mod 32)))+(b*32)); + muxSel <= rot_sel1(4*(byte/4) to (4*(byte/4))+3); + + mux4sel: entity work.xuq_lsu_mux41(xuq_lsu_mux41) + port map ( vdd => vdd, + gnd => gnd, + d0 => muxIn(0), + d1 => muxIn(1), + d2 => muxIn(2), + d3 => muxIn(3), + s0 => muxSel(0), + s1 => muxSel(1), + s2 => muxSel(2), + s3 => muxSel(3), + y => rot10(byte+(b*32))); + end generate; + end generate lvl1rot; + + bitSwap : for bit in 0 to 3 generate begin + byteSwap : for byte in 0 to 31 generate begin + le_rot_data(byte+(bit*32)) <= rot_data((31-byte)+(bit*32)); + end generate byteSwap; + end generate bitSwap; + + lvl2rot: for byte in 0 to 31 generate begin + bit: for b in 0 to 3 generate + signal muxIn :std_ulogic_vector(0 to 3); + signal muxSel :std_ulogic_vector(0 to 3); + begin + muxIn <= le_rot_data(byte+(b*32)) & le_rot_data(((4+byte) mod 32)+(b*32)) & + le_rot_data(((8+byte) mod 32)+(b*32)) & le_rot_data(((12+byte) mod 32)+(b*32)); + muxSel <= rot_sel2_le(4*(byte/4) to (4*(byte/4))+3); + + mux4sel: entity work.xuq_lsu_mux41(xuq_lsu_mux41) + port map ( vdd => vdd, + gnd => gnd, + d0 => muxIn(0), + d1 => muxIn(1), + d2 => muxIn(2), + d3 => muxIn(3), + s0 => muxSel(0), + s1 => muxSel(1), + s2 => muxSel(2), + s3 => muxSel(3), + y => le_rotC840(byte+(b*32))); + end generate; + end generate lvl2rot; + + lvl3rot: for byte in 0 to 31 generate begin + bit: for b in 0 to 3 generate + signal muxIn :std_ulogic_vector(0 to 3); + signal muxSel :std_ulogic_vector(0 to 3); + begin + muxIn <= le_rotC840(byte+(b*32)) & le_rotC840(((1+byte) mod 32)+(b*32)) & + le_rotC840(((2+byte) mod 32)+(b*32)) & le_rotC840(((3+byte) mod 32)+(b*32)); + muxSel <= rot_sel3_le(4*(byte/4) to (4*(byte/4))+3); + + mux4sel: entity work.xuq_lsu_mux41(xuq_lsu_mux41) + port map ( vdd => vdd, + gnd => gnd, + d0 => muxIn(0), + d1 => muxIn(1), + d2 => muxIn(2), + d3 => muxIn(3), + s0 => muxSel(0), + s1 => muxSel(1), + s2 => muxSel(2), + s3 => muxSel(3), + y => le_rot3210(byte+(b*32))); + end generate; + end generate lvl3rot; + data256_rot_le <= le_rot3210; +end generate le_mode_on; + +le_mode_off : if l_endian_m = 0 generate begin + + lvl1rot: for byte in 0 to 31 generate begin + bit: for b in 0 to 3 generate + signal muxIn :std_ulogic_vector(0 to 3); + signal muxSel :std_ulogic_vector(0 to 3); + begin + muxIn <= rot_data(byte+(b*32)) & rot_data(((16+byte) mod 32)+(b*32)) & + rot_data((31 - byte)+(b*32)) & rot_data((31 - ((16+byte) mod 32))+(b*32)); + muxSel <= rot_sel1(4*(byte/4) to (4*(byte/4))+3); + + rot10(byte+(b*32)) <= (rot_data(byte+(b*32)) and rot_sel1(b*4*(byte/16))) or + (rot_data(((16+byte) mod 32)+(b*32)) and rot_sel1((b*4*(byte/16))+1)); + end generate; + end generate lvl1rot; + + le_rot_data <= (others=>'0'); + le_rotC840 <= (others=>'0'); + le_rot3210 <= (others=>'0'); + data256_rot_le <= (others=>'0'); +end generate le_mode_off; + +lvl2rot: for byte in 0 to 31 generate begin + bit: for b in 0 to 3 generate + signal muxIn :std_ulogic_vector(0 to 3); + signal muxSel :std_ulogic_vector(0 to 3); + begin + muxIn <= rot10(byte+(b*32)) & rot10(((4+byte) mod 32)+(b*32)) & + rot10(((8+byte) mod 32)+(b*32)) & rot10(((12+byte) mod 32)+(b*32)); + muxSel <= rot_sel2(4*(byte/4) to (4*(byte/4))+3); + + mux4sel: entity work.xuq_lsu_mux41(xuq_lsu_mux41) + port map ( vdd => vdd, + gnd => gnd, + d0 => muxIn(0), + d1 => muxIn(1), + d2 => muxIn(2), + d3 => muxIn(3), + s0 => muxSel(0), + s1 => muxSel(1), + s2 => muxSel(2), + s3 => muxSel(3), + y => rotC840(byte+(b*32))); + end generate; +end generate lvl2rot; + +lvl3rot: for byte in 0 to 31 generate begin + bit: for b in 0 to 3 generate + signal muxIn :std_ulogic_vector(0 to 3); + signal muxSel :std_ulogic_vector(0 to 3); + begin + muxIn <= rotC840(byte+(b*32)) & rotC840(((1+byte) mod 32)+(b*32)) & + rotC840(((2+byte) mod 32)+(b*32)) & rotC840(((3+byte) mod 32)+(b*32)); + muxSel <= rot_sel3(4*(byte/4) to (4*(byte/4))+3); + + mux4sel: entity work.xuq_lsu_mux41(xuq_lsu_mux41) + port map ( vdd => vdd, + gnd => gnd, + d0 => muxIn(0), + d1 => muxIn(1), + d2 => muxIn(2), + d3 => muxIn(3), + s0 => muxSel(0), + s1 => muxSel(1), + s2 => muxSel(2), + s3 => muxSel(3), + y => rot3210(byte+(b*32))); + end generate; +end generate lvl3rot; + + + +data256_rot <= rot3210; + +end xuq_lsu_data_rot32_lu; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_data_rot32_ru.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_data_rot32_ru.vhdl new file mode 100644 index 0000000..580bce6 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_data_rot32_ru.vhdl @@ -0,0 +1,454 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +LIBRARY ieee; USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY ibm; + USE ibm.std_ulogic_support.all; + USE ibm.std_ulogic_unsigned.all; + USE ibm.std_ulogic_function_support.all; +LIBRARY support; + USE support.power_logic_pkg.all; +LIBRARY tri; USE tri.tri_latches_pkg.all; +LIBRARY clib ; + + +entity xuq_lsu_data_rot32_ru is + generic (expand_type : integer := 2 ); + port ( + + opsize :in std_ulogic_vector(0 to 5); + le :in std_ulogic; + rotate_sel :in std_ulogic_vector(0 to 4); + + data :in std_ulogic_vector(0 to 31); + data_latched :out std_ulogic_vector(0 to 31); + data_rot :out std_ulogic_vector(0 to 31); + + nclk :in clk_logic; + vdd :inout power_logic; + gnd :inout power_logic; + delay_lclkr_dc :in std_ulogic; + mpw1_dc_b :in std_ulogic; + mpw2_dc_b :in std_ulogic; + func_sl_force :in std_ulogic; + func_sl_thold_0_b :in std_ulogic; + sg_0 :in std_ulogic; + act :in std_ulogic; + scan_in :in std_ulogic; + scan_out :out std_ulogic + ); + + +end xuq_lsu_data_rot32_ru; + +architecture xuq_lsu_data_rot32_ru of xuq_lsu_data_rot32_ru is + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal my_d1clk, my_d2clk :std_ulogic ; + signal my_lclk :clk_logic ; + + signal di_lat_si, di_lat_so, di_q_b, di_q, di_din :std_ulogic_vector(0 to 31); + signal shx16_gp0_lat_si, shx16_gp0_lat_so, shx16_gp0_q_b, shx16_gp0_q, shx16_gp0_din :std_ulogic_vector(0 to 3); + signal shx16_gp1_lat_si, shx16_gp1_lat_so, shx16_gp1_q_b, shx16_gp1_q, shx16_gp1_din :std_ulogic_vector(0 to 3); + signal shx04_gp0_lat_si, shx04_gp0_lat_so, shx04_gp0_q_b, shx04_gp0_q, shx04_gp0_din :std_ulogic_vector(0 to 3); + signal shx04_gp1_lat_si, shx04_gp1_lat_so, shx04_gp1_q_b, shx04_gp1_q, shx04_gp1_din :std_ulogic_vector(0 to 3); + signal shx01_gp0_lat_si, shx01_gp0_lat_so, shx01_gp0_q_b, shx01_gp0_q, shx01_gp0_din :std_ulogic_vector(0 to 3); + signal shx01_gp1_lat_si, shx01_gp1_lat_so, shx01_gp1_q_b, shx01_gp1_q, shx01_gp1_din :std_ulogic_vector(0 to 3); + signal mask_lat_si, mask_lat_so, mask_q_b, mask_q, mask_din :std_ulogic_vector(0 to 5); + + signal mx1_0_b, mx1_1_b, mx1 :std_ulogic_vector(0 to 31); + signal mx2_0_b, mx2_1_b, mx2 :std_ulogic_vector(0 to 31); + signal mx3_0_b, mx3_1_b, mx3 :std_ulogic_vector(0 to 31); + signal do_b :std_ulogic_vector(0 to 31) ; + + signal mx1_d0, mx1_d1, mx1_d2, mx1_d3 :std_ulogic_vector(0 to 31) ; + signal mx2_d0, mx2_d1, mx2_d2, mx2_d3 :std_ulogic_vector(0 to 31) ; + signal mx3_d0, mx3_d1, mx3_d2, mx3_d3 :std_ulogic_vector(0 to 31) ; + + signal mx1_s0, mx1_s1, mx1_s2, mx1_s3 :std_ulogic_vector(0 to 31) ; + signal mx2_s0, mx2_s1, mx2_s2, mx2_s3 :std_ulogic_vector(0 to 31) ; + signal mx3_s0, mx3_s1, mx3_s2, mx3_s3 :std_ulogic_vector(0 to 31) ; + + signal mask_en :std_ulogic_vector(0 to 31); + signal shx16_sel , shx04_sel , shx01_sel :std_ulogic_vector(0 to 3); + + + + + + + + + + +begin + + + + + shx16_sel(0) <= not le and not rotate_sel(0); + shx16_sel(1) <= not le and rotate_sel(0); + shx16_sel(2) <= le and not rotate_sel(0); + shx16_sel(3) <= le and rotate_sel(0); + + shx04_sel(0) <= not rotate_sel(1) and not rotate_sel(2); + shx04_sel(1) <= not rotate_sel(1) and rotate_sel(2); + shx04_sel(2) <= rotate_sel(1) and not rotate_sel(2); + shx04_sel(3) <= rotate_sel(1) and rotate_sel(2); + + shx01_sel(0) <= not rotate_sel(3) and not rotate_sel(4); + shx01_sel(1) <= not rotate_sel(3) and rotate_sel(4); + shx01_sel(2) <= rotate_sel(3) and not rotate_sel(4); + shx01_sel(3) <= rotate_sel(3) and rotate_sel(4); + + mask_din(0) <= opsize(0) ; + mask_din(1) <= opsize(1) or mask_din(0) ; + mask_din(2) <= opsize(2) or mask_din(1) ; + mask_din(3) <= opsize(3) or mask_din(2) ; + mask_din(4) <= opsize(4) or mask_din(3) ; + mask_din(5) <= opsize(5) or mask_din(4) ; + + di_din(0 to 31) <= data(0 to 31); + shx16_gp0_din(0 to 3) <= shx16_sel(0 to 3); + shx16_gp1_din(0 to 3) <= shx16_sel(0 to 3); + shx04_gp0_din(0 to 3) <= shx04_sel(0 to 3); + shx04_gp1_din(0 to 3) <= shx04_sel(0 to 3); + shx01_gp0_din(0 to 3) <= shx01_sel(0 to 3); + shx01_gp1_din(0 to 3) <= shx01_sel(0 to 3); + + + + u_di_q: di_q(0 to 31) <= not di_q_b(0 to 31) ; + u_shx16_gp0_q: shx16_gp0_q(0 to 3) <= not shx16_gp0_q_b(0 to 3) ; + u_shx16_gp1_q: shx16_gp1_q(0 to 3) <= not shx16_gp1_q_b(0 to 3) ; + u_shx04_gp0_q: shx04_gp0_q(0 to 3) <= not shx04_gp0_q_b(0 to 3) ; + u_shx04_gp1_q: shx04_gp1_q(0 to 3) <= not shx04_gp1_q_b(0 to 3) ; + u_shx01_gp0_q: shx01_gp0_q(0 to 3) <= not shx01_gp0_q_b(0 to 3) ; + u_shx01_gp1_q: shx01_gp1_q(0 to 3) <= not shx01_gp1_q_b(0 to 3) ; + mask_q(0 to 5) <= not mask_q_b(0 to 5) ; + + + mx1_s0( 0 to 15) <= ( 0 to 15=> shx16_gp0_q(0) ) ; + mx1_s1( 0 to 15) <= ( 0 to 15=> shx16_gp0_q(1) ) ; + mx1_s2( 0 to 15) <= ( 0 to 15=> shx16_gp0_q(2) ) ; + mx1_s3( 0 to 15) <= ( 0 to 15=> shx16_gp0_q(3) ) ; + mx1_s0(16 to 31) <= (16 to 31=> shx16_gp1_q(0) ) ; + mx1_s1(16 to 31) <= (16 to 31=> shx16_gp1_q(1) ) ; + mx1_s2(16 to 31) <= (16 to 31=> shx16_gp1_q(2) ) ; + mx1_s3(16 to 31) <= (16 to 31=> shx16_gp1_q(3) ) ; + + mx1_d0(0) <= di_q(0) ; mx1_d1(0) <= di_q(16) ; mx1_d2(0) <= di_q(31) ; mx1_d3(0) <= di_q(15) ; + mx1_d0(1) <= di_q(1) ; mx1_d1(1) <= di_q(17) ; mx1_d2(1) <= di_q(30) ; mx1_d3(1) <= di_q(14) ; + mx1_d0(2) <= di_q(2) ; mx1_d1(2) <= di_q(18) ; mx1_d2(2) <= di_q(29) ; mx1_d3(2) <= di_q(13) ; + mx1_d0(3) <= di_q(3) ; mx1_d1(3) <= di_q(19) ; mx1_d2(3) <= di_q(28) ; mx1_d3(3) <= di_q(12) ; + mx1_d0(4) <= di_q(4) ; mx1_d1(4) <= di_q(20) ; mx1_d2(4) <= di_q(27) ; mx1_d3(4) <= di_q(11) ; + mx1_d0(5) <= di_q(5) ; mx1_d1(5) <= di_q(21) ; mx1_d2(5) <= di_q(26) ; mx1_d3(5) <= di_q(10) ; + mx1_d0(6) <= di_q(6) ; mx1_d1(6) <= di_q(22) ; mx1_d2(6) <= di_q(25) ; mx1_d3(6) <= di_q(9) ; + mx1_d0(7) <= di_q(7) ; mx1_d1(7) <= di_q(23) ; mx1_d2(7) <= di_q(24) ; mx1_d3(7) <= di_q(8) ; + mx1_d0(8) <= di_q(8) ; mx1_d1(8) <= di_q(24) ; mx1_d2(8) <= di_q(23) ; mx1_d3(8) <= di_q(7) ; + mx1_d0(9) <= di_q(9) ; mx1_d1(9) <= di_q(25) ; mx1_d2(9) <= di_q(22) ; mx1_d3(9) <= di_q(6) ; + mx1_d0(10) <= di_q(10) ; mx1_d1(10) <= di_q(26) ; mx1_d2(10) <= di_q(21) ; mx1_d3(10) <= di_q(5) ; + mx1_d0(11) <= di_q(11) ; mx1_d1(11) <= di_q(27) ; mx1_d2(11) <= di_q(20) ; mx1_d3(11) <= di_q(4) ; + mx1_d0(12) <= di_q(12) ; mx1_d1(12) <= di_q(28) ; mx1_d2(12) <= di_q(19) ; mx1_d3(12) <= di_q(3) ; + mx1_d0(13) <= di_q(13) ; mx1_d1(13) <= di_q(29) ; mx1_d2(13) <= di_q(18) ; mx1_d3(13) <= di_q(2) ; + mx1_d0(14) <= di_q(14) ; mx1_d1(14) <= di_q(30) ; mx1_d2(14) <= di_q(17) ; mx1_d3(14) <= di_q(1) ; + mx1_d0(15) <= di_q(15) ; mx1_d1(15) <= di_q(31) ; mx1_d2(15) <= di_q(16) ; mx1_d3(15) <= di_q(0) ; + mx1_d0(16) <= di_q(16) ; mx1_d1(16) <= di_q(0) ; mx1_d2(16) <= di_q(15) ; mx1_d3(16) <= di_q(31) ; + mx1_d0(17) <= di_q(17) ; mx1_d1(17) <= di_q(1) ; mx1_d2(17) <= di_q(14) ; mx1_d3(17) <= di_q(30) ; + mx1_d0(18) <= di_q(18) ; mx1_d1(18) <= di_q(2) ; mx1_d2(18) <= di_q(13) ; mx1_d3(18) <= di_q(29) ; + mx1_d0(19) <= di_q(19) ; mx1_d1(19) <= di_q(3) ; mx1_d2(19) <= di_q(12) ; mx1_d3(19) <= di_q(28) ; + mx1_d0(20) <= di_q(20) ; mx1_d1(20) <= di_q(4) ; mx1_d2(20) <= di_q(11) ; mx1_d3(20) <= di_q(27) ; + mx1_d0(21) <= di_q(21) ; mx1_d1(21) <= di_q(5) ; mx1_d2(21) <= di_q(10) ; mx1_d3(21) <= di_q(26) ; + mx1_d0(22) <= di_q(22) ; mx1_d1(22) <= di_q(6) ; mx1_d2(22) <= di_q(9) ; mx1_d3(22) <= di_q(25) ; + mx1_d0(23) <= di_q(23) ; mx1_d1(23) <= di_q(7) ; mx1_d2(23) <= di_q(8) ; mx1_d3(23) <= di_q(24) ; + mx1_d0(24) <= di_q(24) ; mx1_d1(24) <= di_q(8) ; mx1_d2(24) <= di_q(7) ; mx1_d3(24) <= di_q(23) ; + mx1_d0(25) <= di_q(25) ; mx1_d1(25) <= di_q(9) ; mx1_d2(25) <= di_q(6) ; mx1_d3(25) <= di_q(22) ; + mx1_d0(26) <= di_q(26) ; mx1_d1(26) <= di_q(10) ; mx1_d2(26) <= di_q(5) ; mx1_d3(26) <= di_q(21) ; + mx1_d0(27) <= di_q(27) ; mx1_d1(27) <= di_q(11) ; mx1_d2(27) <= di_q(4) ; mx1_d3(27) <= di_q(20) ; + mx1_d0(28) <= di_q(28) ; mx1_d1(28) <= di_q(12) ; mx1_d2(28) <= di_q(3) ; mx1_d3(28) <= di_q(19) ; + mx1_d0(29) <= di_q(29) ; mx1_d1(29) <= di_q(13) ; mx1_d2(29) <= di_q(2) ; mx1_d3(29) <= di_q(18) ; + mx1_d0(30) <= di_q(30) ; mx1_d1(30) <= di_q(14) ; mx1_d2(30) <= di_q(1) ; mx1_d3(30) <= di_q(17) ; + mx1_d0(31) <= di_q(31) ; mx1_d1(31) <= di_q(15) ; mx1_d2(31) <= di_q(0) ; mx1_d3(31) <= di_q(16) ; + + + u_mx1_0: mx1_0_b(0 to 31) <= not( (mx1_s0(0 to 31) and mx1_d0(0 to 31) ) or + (mx1_s1(0 to 31) and mx1_d1(0 to 31) ) ); + + u_mx1_1: mx1_1_b(0 to 31) <= not( (mx1_s2(0 to 31) and mx1_d2(0 to 31) ) or + (mx1_s3(0 to 31) and mx1_d3(0 to 31) ) ); + + u_mx1: mx1(0 to 31) <= not( mx1_0_b(0 to 31) and mx1_1_b(0 to 31) ); + + + mx2_s0( 0 to 15) <= ( 0 to 15=> shx04_gp0_q(0) ) ; + mx2_s1( 0 to 15) <= ( 0 to 15=> shx04_gp0_q(1) ) ; + mx2_s2( 0 to 15) <= ( 0 to 15=> shx04_gp0_q(2) ) ; + mx2_s3( 0 to 15) <= ( 0 to 15=> shx04_gp0_q(3) ) ; + mx2_s0(16 to 31) <= (16 to 31=> shx04_gp1_q(0) ) ; + mx2_s1(16 to 31) <= (16 to 31=> shx04_gp1_q(1) ) ; + mx2_s2(16 to 31) <= (16 to 31=> shx04_gp1_q(2) ) ; + mx2_s3(16 to 31) <= (16 to 31=> shx04_gp1_q(3) ) ; + + mx2_d0(0) <= mx1(0) ; mx2_d1(0) <= mx1(28) ; mx2_d2(0) <= mx1(24) ; mx2_d3(0) <= mx1(20) ; + mx2_d0(1) <= mx1(1) ; mx2_d1(1) <= mx1(29) ; mx2_d2(1) <= mx1(25) ; mx2_d3(1) <= mx1(21) ; + mx2_d0(2) <= mx1(2) ; mx2_d1(2) <= mx1(30) ; mx2_d2(2) <= mx1(26) ; mx2_d3(2) <= mx1(22) ; + mx2_d0(3) <= mx1(3) ; mx2_d1(3) <= mx1(31) ; mx2_d2(3) <= mx1(27) ; mx2_d3(3) <= mx1(23) ; + mx2_d0(4) <= mx1(4) ; mx2_d1(4) <= mx1(0) ; mx2_d2(4) <= mx1(28) ; mx2_d3(4) <= mx1(24) ; + mx2_d0(5) <= mx1(5) ; mx2_d1(5) <= mx1(1) ; mx2_d2(5) <= mx1(29) ; mx2_d3(5) <= mx1(25) ; + mx2_d0(6) <= mx1(6) ; mx2_d1(6) <= mx1(2) ; mx2_d2(6) <= mx1(30) ; mx2_d3(6) <= mx1(26) ; + mx2_d0(7) <= mx1(7) ; mx2_d1(7) <= mx1(3) ; mx2_d2(7) <= mx1(31) ; mx2_d3(7) <= mx1(27) ; + mx2_d0(8) <= mx1(8) ; mx2_d1(8) <= mx1(4) ; mx2_d2(8) <= mx1(0) ; mx2_d3(8) <= mx1(28) ; + mx2_d0(9) <= mx1(9) ; mx2_d1(9) <= mx1(5) ; mx2_d2(9) <= mx1(1) ; mx2_d3(9) <= mx1(29) ; + mx2_d0(10) <= mx1(10) ; mx2_d1(10) <= mx1(6) ; mx2_d2(10) <= mx1(2) ; mx2_d3(10) <= mx1(30) ; + mx2_d0(11) <= mx1(11) ; mx2_d1(11) <= mx1(7) ; mx2_d2(11) <= mx1(3) ; mx2_d3(11) <= mx1(31) ; + mx2_d0(12) <= mx1(12) ; mx2_d1(12) <= mx1(8) ; mx2_d2(12) <= mx1(4) ; mx2_d3(12) <= mx1(0) ; + mx2_d0(13) <= mx1(13) ; mx2_d1(13) <= mx1(9) ; mx2_d2(13) <= mx1(5) ; mx2_d3(13) <= mx1(1) ; + mx2_d0(14) <= mx1(14) ; mx2_d1(14) <= mx1(10) ; mx2_d2(14) <= mx1(6) ; mx2_d3(14) <= mx1(2) ; + mx2_d0(15) <= mx1(15) ; mx2_d1(15) <= mx1(11) ; mx2_d2(15) <= mx1(7) ; mx2_d3(15) <= mx1(3) ; + mx2_d0(16) <= mx1(16) ; mx2_d1(16) <= mx1(12) ; mx2_d2(16) <= mx1(8) ; mx2_d3(16) <= mx1(4) ; + mx2_d0(17) <= mx1(17) ; mx2_d1(17) <= mx1(13) ; mx2_d2(17) <= mx1(9) ; mx2_d3(17) <= mx1(5) ; + mx2_d0(18) <= mx1(18) ; mx2_d1(18) <= mx1(14) ; mx2_d2(18) <= mx1(10) ; mx2_d3(18) <= mx1(6) ; + mx2_d0(19) <= mx1(19) ; mx2_d1(19) <= mx1(15) ; mx2_d2(19) <= mx1(11) ; mx2_d3(19) <= mx1(7) ; + mx2_d0(20) <= mx1(20) ; mx2_d1(20) <= mx1(16) ; mx2_d2(20) <= mx1(12) ; mx2_d3(20) <= mx1(8) ; + mx2_d0(21) <= mx1(21) ; mx2_d1(21) <= mx1(17) ; mx2_d2(21) <= mx1(13) ; mx2_d3(21) <= mx1(9) ; + mx2_d0(22) <= mx1(22) ; mx2_d1(22) <= mx1(18) ; mx2_d2(22) <= mx1(14) ; mx2_d3(22) <= mx1(10) ; + mx2_d0(23) <= mx1(23) ; mx2_d1(23) <= mx1(19) ; mx2_d2(23) <= mx1(15) ; mx2_d3(23) <= mx1(11) ; + mx2_d0(24) <= mx1(24) ; mx2_d1(24) <= mx1(20) ; mx2_d2(24) <= mx1(16) ; mx2_d3(24) <= mx1(12) ; + mx2_d0(25) <= mx1(25) ; mx2_d1(25) <= mx1(21) ; mx2_d2(25) <= mx1(17) ; mx2_d3(25) <= mx1(13) ; + mx2_d0(26) <= mx1(26) ; mx2_d1(26) <= mx1(22) ; mx2_d2(26) <= mx1(18) ; mx2_d3(26) <= mx1(14) ; + mx2_d0(27) <= mx1(27) ; mx2_d1(27) <= mx1(23) ; mx2_d2(27) <= mx1(19) ; mx2_d3(27) <= mx1(15) ; + mx2_d0(28) <= mx1(28) ; mx2_d1(28) <= mx1(24) ; mx2_d2(28) <= mx1(20) ; mx2_d3(28) <= mx1(16) ; + mx2_d0(29) <= mx1(29) ; mx2_d1(29) <= mx1(25) ; mx2_d2(29) <= mx1(21) ; mx2_d3(29) <= mx1(17) ; + mx2_d0(30) <= mx1(30) ; mx2_d1(30) <= mx1(26) ; mx2_d2(30) <= mx1(22) ; mx2_d3(30) <= mx1(18) ; + mx2_d0(31) <= mx1(31) ; mx2_d1(31) <= mx1(27) ; mx2_d2(31) <= mx1(23) ; mx2_d3(31) <= mx1(19) ; + + + u_mx2_0: mx2_0_b(0 to 31) <= not( (mx2_s0(0 to 31) and mx2_d0(0 to 31) ) or + (mx2_s1(0 to 31) and mx2_d1(0 to 31) ) ); + + u_mx2_1: mx2_1_b(0 to 31) <= not( (mx2_s2(0 to 31) and mx2_d2(0 to 31) ) or + (mx2_s3(0 to 31) and mx2_d3(0 to 31) ) ); + + u_mx2: mx2(0 to 31) <= not( mx2_0_b(0 to 31) and mx2_1_b(0 to 31) ); + + + + mask_en( 0 to 15) <= ( 0 to 15=> mask_q(0) ); + mask_en(16 to 23) <= (16 to 23=> mask_q(1) ); + mask_en(24 to 27) <= (24 to 27=> mask_q(2) ); + mask_en(28 to 29) <= (28 to 29=> mask_q(3) ); + mask_en(30) <= ( mask_q(4) ); + mask_en(31) <= ( mask_q(5) ); + + mx3_s0( 0 to 15) <= ( 0 to 15=> shx01_gp0_q(0) ) and mask_en( 0 to 15); + mx3_s1( 0 to 15) <= ( 0 to 15=> shx01_gp0_q(1) ) and mask_en( 0 to 15); + mx3_s2( 0 to 15) <= ( 0 to 15=> shx01_gp0_q(2) ) and mask_en( 0 to 15); + mx3_s3( 0 to 15) <= ( 0 to 15=> shx01_gp0_q(3) ) and mask_en( 0 to 15); + mx3_s0(16 to 31) <= (16 to 31=> shx01_gp1_q(0) ) and mask_en(16 to 31); + mx3_s1(16 to 31) <= (16 to 31=> shx01_gp1_q(1) ) and mask_en(16 to 31); + mx3_s2(16 to 31) <= (16 to 31=> shx01_gp1_q(2) ) and mask_en(16 to 31); + mx3_s3(16 to 31) <= (16 to 31=> shx01_gp1_q(3) ) and mask_en(16 to 31); + + mx3_d0(0) <= mx2(0) ; mx3_d1(0) <= mx2(31) ; mx3_d2(0) <= mx2(30) ; mx3_d3(0) <= mx2(29) ; + mx3_d0(1) <= mx2(1) ; mx3_d1(1) <= mx2(0) ; mx3_d2(1) <= mx2(31) ; mx3_d3(1) <= mx2(30) ; + mx3_d0(2) <= mx2(2) ; mx3_d1(2) <= mx2(1) ; mx3_d2(2) <= mx2(0) ; mx3_d3(2) <= mx2(31) ; + mx3_d0(3) <= mx2(3) ; mx3_d1(3) <= mx2(2) ; mx3_d2(3) <= mx2(1) ; mx3_d3(3) <= mx2(0) ; + mx3_d0(4) <= mx2(4) ; mx3_d1(4) <= mx2(3) ; mx3_d2(4) <= mx2(2) ; mx3_d3(4) <= mx2(1) ; + mx3_d0(5) <= mx2(5) ; mx3_d1(5) <= mx2(4) ; mx3_d2(5) <= mx2(3) ; mx3_d3(5) <= mx2(2) ; + mx3_d0(6) <= mx2(6) ; mx3_d1(6) <= mx2(5) ; mx3_d2(6) <= mx2(4) ; mx3_d3(6) <= mx2(3) ; + mx3_d0(7) <= mx2(7) ; mx3_d1(7) <= mx2(6) ; mx3_d2(7) <= mx2(5) ; mx3_d3(7) <= mx2(4) ; + mx3_d0(8) <= mx2(8) ; mx3_d1(8) <= mx2(7) ; mx3_d2(8) <= mx2(6) ; mx3_d3(8) <= mx2(5) ; + mx3_d0(9) <= mx2(9) ; mx3_d1(9) <= mx2(8) ; mx3_d2(9) <= mx2(7) ; mx3_d3(9) <= mx2(6) ; + mx3_d0(10) <= mx2(10) ; mx3_d1(10) <= mx2(9) ; mx3_d2(10) <= mx2(8) ; mx3_d3(10) <= mx2(7) ; + mx3_d0(11) <= mx2(11) ; mx3_d1(11) <= mx2(10) ; mx3_d2(11) <= mx2(9) ; mx3_d3(11) <= mx2(8) ; + mx3_d0(12) <= mx2(12) ; mx3_d1(12) <= mx2(11) ; mx3_d2(12) <= mx2(10) ; mx3_d3(12) <= mx2(9) ; + mx3_d0(13) <= mx2(13) ; mx3_d1(13) <= mx2(12) ; mx3_d2(13) <= mx2(11) ; mx3_d3(13) <= mx2(10) ; + mx3_d0(14) <= mx2(14) ; mx3_d1(14) <= mx2(13) ; mx3_d2(14) <= mx2(12) ; mx3_d3(14) <= mx2(11) ; + mx3_d0(15) <= mx2(15) ; mx3_d1(15) <= mx2(14) ; mx3_d2(15) <= mx2(13) ; mx3_d3(15) <= mx2(12) ; + mx3_d0(16) <= mx2(16) ; mx3_d1(16) <= mx2(15) ; mx3_d2(16) <= mx2(14) ; mx3_d3(16) <= mx2(13) ; + mx3_d0(17) <= mx2(17) ; mx3_d1(17) <= mx2(16) ; mx3_d2(17) <= mx2(15) ; mx3_d3(17) <= mx2(14) ; + mx3_d0(18) <= mx2(18) ; mx3_d1(18) <= mx2(17) ; mx3_d2(18) <= mx2(16) ; mx3_d3(18) <= mx2(15) ; + mx3_d0(19) <= mx2(19) ; mx3_d1(19) <= mx2(18) ; mx3_d2(19) <= mx2(17) ; mx3_d3(19) <= mx2(16) ; + mx3_d0(20) <= mx2(20) ; mx3_d1(20) <= mx2(19) ; mx3_d2(20) <= mx2(18) ; mx3_d3(20) <= mx2(17) ; + mx3_d0(21) <= mx2(21) ; mx3_d1(21) <= mx2(20) ; mx3_d2(21) <= mx2(19) ; mx3_d3(21) <= mx2(18) ; + mx3_d0(22) <= mx2(22) ; mx3_d1(22) <= mx2(21) ; mx3_d2(22) <= mx2(20) ; mx3_d3(22) <= mx2(19) ; + mx3_d0(23) <= mx2(23) ; mx3_d1(23) <= mx2(22) ; mx3_d2(23) <= mx2(21) ; mx3_d3(23) <= mx2(20) ; + mx3_d0(24) <= mx2(24) ; mx3_d1(24) <= mx2(23) ; mx3_d2(24) <= mx2(22) ; mx3_d3(24) <= mx2(21) ; + mx3_d0(25) <= mx2(25) ; mx3_d1(25) <= mx2(24) ; mx3_d2(25) <= mx2(23) ; mx3_d3(25) <= mx2(22) ; + mx3_d0(26) <= mx2(26) ; mx3_d1(26) <= mx2(25) ; mx3_d2(26) <= mx2(24) ; mx3_d3(26) <= mx2(23) ; + mx3_d0(27) <= mx2(27) ; mx3_d1(27) <= mx2(26) ; mx3_d2(27) <= mx2(25) ; mx3_d3(27) <= mx2(24) ; + mx3_d0(28) <= mx2(28) ; mx3_d1(28) <= mx2(27) ; mx3_d2(28) <= mx2(26) ; mx3_d3(28) <= mx2(25) ; + mx3_d0(29) <= mx2(29) ; mx3_d1(29) <= mx2(28) ; mx3_d2(29) <= mx2(27) ; mx3_d3(29) <= mx2(26) ; + mx3_d0(30) <= mx2(30) ; mx3_d1(30) <= mx2(29) ; mx3_d2(30) <= mx2(28) ; mx3_d3(30) <= mx2(27) ; + mx3_d0(31) <= mx2(31) ; mx3_d1(31) <= mx2(30) ; mx3_d2(31) <= mx2(29) ; mx3_d3(31) <= mx2(28) ; + + u_mx3_0: mx3_0_b(0 to 31) <= not( (mx3_s0(0 to 31) and mx3_d0(0 to 31) ) or + (mx3_s1(0 to 31) and mx3_d1(0 to 31) ) ); + + u_mx3_1: mx3_1_b(0 to 31) <= not( (mx3_s2(0 to 31) and mx3_d2(0 to 31) ) or + (mx3_s3(0 to 31) and mx3_d3(0 to 31) ) ); + + u_mx3: mx3(0 to 31) <= not( mx3_0_b(0 to 31) and mx3_1_b(0 to 31) ); + + + u_oi1: do_b(0 to 31) <= not( mx3(0 to 31) ) ; + u_oi2: data_rot(0 to 31) <= not( do_b(0 to 31) ) ; + + u_oth_i: data_latched <= not di_q_b; + + + + di_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 32, init=>(1 to 32=>'0'), btr => "NLI0001_X4_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + VD => vdd , + GD => gnd , + LCLK => my_lclk , + D1CLK => my_d1clk , + D2CLK => my_d2clk , + SCANIN => di_lat_si , + SCANOUT => di_lat_so , + D => di_din(0 to 31) , + QB => di_q_b(0 to 31) ); + + shx16_gp0_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 4, init=>(1 to 4=>'0'),btr => "NLI0001_X4_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + VD => vdd , + GD => gnd , + LCLK => my_lclk , + D1CLK => my_d1clk , + D2CLK => my_d2clk , + SCANIN => shx16_gp0_lat_si , + SCANOUT => shx16_gp0_lat_so , + D => shx16_gp0_din , + QB => shx16_gp0_q_b(0 to 3) ); + + shx16_gp1_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 4, init=>(1 to 4=>'0'),btr => "NLI0001_X4_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + VD => vdd , + GD => gnd , + LCLK => my_lclk , + D1CLK => my_d1clk , + D2CLK => my_d2clk , + SCANIN => shx16_gp1_lat_si , + SCANOUT => shx16_gp1_lat_so , + D => shx16_gp1_din , + QB => shx16_gp1_q_b(0 to 3) ); + + shx04_gp0_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 4, init=>(1 to 4=>'0'),btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + VD => vdd , + GD => gnd , + LCLK => my_lclk , + D1CLK => my_d1clk , + D2CLK => my_d2clk , + SCANIN => shx04_gp0_lat_si , + SCANOUT => shx04_gp0_lat_so , + D => shx04_gp0_din , + QB => shx04_gp0_q_b(0 to 3) ); + + shx04_gp1_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 4, init=>(1 to 4=>'0'),btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + VD => vdd , + GD => gnd , + LCLK => my_lclk , + D1CLK => my_d1clk , + D2CLK => my_d2clk , + SCANIN => shx04_gp1_lat_si , + SCANOUT => shx04_gp1_lat_so , + D => shx04_gp1_din , + QB => shx04_gp1_q_b(0 to 3) ); + + shx01_gp0_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 4, init=>(1 to 4=>'0'),btr => "NLI0001_X1_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + VD => vdd , + GD => gnd , + LCLK => my_lclk , + D1CLK => my_d1clk , + D2CLK => my_d2clk , + SCANIN => shx01_gp0_lat_si , + SCANOUT => shx01_gp0_lat_so , + D => shx01_gp0_din , + QB => shx01_gp0_q_b(0 to 3) ); + + shx01_gp1_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 4, init=>(1 to 4=>'0'),btr => "NLI0001_X1_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + VD => vdd , + GD => gnd , + LCLK => my_lclk , + D1CLK => my_d1clk , + D2CLK => my_d2clk , + SCANIN => shx01_gp1_lat_si , + SCANOUT => shx01_gp1_lat_so , + D => shx01_gp1_din , + QB => shx01_gp1_q_b(0 to 3) ); + + mask_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 6, init=>(1 to 6=>'0'),btr => "NLI0001_X1_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + VD => vdd , + GD => gnd , + LCLK => my_lclk , + D1CLK => my_d1clk , + D2CLK => my_d2clk , + SCANIN => mask_lat_si , + SCANOUT => mask_lat_so , + D => mask_din , + QB => mask_q_b(0 to 5) ); + + + di_lat_si(0) <= scan_in; + di_lat_si(1 to 31) <= di_lat_so(0 to 30); + shx16_gp0_lat_si(0) <= di_lat_so(31); + shx16_gp0_lat_si(1 to 3) <= shx16_gp0_lat_so(0 to 2); + shx16_gp1_lat_si(0) <= shx16_gp0_lat_so(3); + shx16_gp1_lat_si(1 to 3) <= shx16_gp1_lat_so(0 to 2); + shx04_gp0_lat_si(0) <= shx16_gp1_lat_so(3); + shx04_gp0_lat_si(1 to 3) <= shx04_gp0_lat_so(0 to 2); + shx04_gp1_lat_si(0) <= shx04_gp0_lat_so(3); + shx04_gp1_lat_si(1 to 3) <= shx04_gp1_lat_so(0 to 2); + shx01_gp0_lat_si(0) <= shx04_gp1_lat_so(3); + shx01_gp0_lat_si(1 to 3) <= shx01_gp0_lat_so(0 to 2); + shx01_gp1_lat_si(0) <= shx01_gp0_lat_so(3); + shx01_gp1_lat_si(1 to 3) <= shx01_gp1_lat_so(0 to 2); + mask_lat_si(0) <= shx01_gp1_lat_so(3); + mask_lat_si(1 to 5) <= mask_lat_so(0 to 4); + scan_out <= mask_lat_so(5); + + + + my_lcb: tri_lcbnd generic map (expand_type => expand_type) port map ( + delay_lclkr => delay_lclkr_dc , + mpw1_b => mpw1_dc_b , + mpw2_b => mpw2_dc_b , + forcee => func_sl_force , + nclk => nclk , + vd => vdd , + gd => gnd , + act => act , + sg => sg_0 , + thold_b => func_sl_thold_0_b , + d1clk => my_d1clk , + d2clk => my_d2clk , + lclk => my_lclk ); + +end architecture xuq_lsu_data_rot32_ru; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_data_rot32s_ru.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_data_rot32s_ru.vhdl new file mode 100644 index 0000000..bbf02a8 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_data_rot32s_ru.vhdl @@ -0,0 +1,607 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +LIBRARY ieee; USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY ibm; + USE ibm.std_ulogic_support.all; + USE ibm.std_ulogic_unsigned.all; + USE ibm.std_ulogic_function_support.all; +LIBRARY support; + USE support.power_logic_pkg.all; +LIBRARY tri; USE tri.tri_latches_pkg.all; +LIBRARY clib ; + + +entity xuq_lsu_data_rot32s_ru is + generic (expand_type : integer := 2 ); + port ( + + opsize :in std_ulogic_vector(0 to 5); + le :in std_ulogic; + rotate_sel :in std_ulogic_vector(0 to 4); + algebraic :in std_ulogic; + algebraic_sel :in std_ulogic_vector(0 to 4); + + data :in std_ulogic_vector(0 to 31); + data_latched :out std_ulogic_vector(0 to 31); + data_rot :out std_ulogic_vector(0 to 31); + algebraic_bit :out std_ulogic_vector(0 to 5); + + nclk :in clk_logic; + vdd :inout power_logic; + gnd :inout power_logic; + delay_lclkr_dc :in std_ulogic; + mpw1_dc_b :in std_ulogic; + mpw2_dc_b :in std_ulogic; + func_sl_force :in std_ulogic; + func_sl_thold_0_b :in std_ulogic; + sg_0 :in std_ulogic; + act :in std_ulogic; + scan_in :in std_ulogic; + scan_out :out std_ulogic + ); + + +end xuq_lsu_data_rot32s_ru; + +architecture xuq_lsu_data_rot32s_ru of xuq_lsu_data_rot32s_ru is + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal my_d1clk, my_d2clk :std_ulogic ; + signal my_lclk :clk_logic ; + + signal di_lat_si, di_lat_so, di_q_b, di_q, di_din :std_ulogic_vector(0 to 31); + signal shx16_gp0_lat_si, shx16_gp0_lat_so, shx16_gp0_q_b, shx16_gp0_q, shx16_gp0_din :std_ulogic_vector(0 to 3); + signal shx16_gp1_lat_si, shx16_gp1_lat_so, shx16_gp1_q_b, shx16_gp1_q, shx16_gp1_din :std_ulogic_vector(0 to 3); + signal shx04_gp0_lat_si, shx04_gp0_lat_so, shx04_gp0_q_b, shx04_gp0_q, shx04_gp0_din :std_ulogic_vector(0 to 3); + signal shx04_gp1_lat_si, shx04_gp1_lat_so, shx04_gp1_q_b, shx04_gp1_q, shx04_gp1_din :std_ulogic_vector(0 to 3); + signal shx01_gp0_lat_si, shx01_gp0_lat_so, shx01_gp0_q_b, shx01_gp0_q, shx01_gp0_din :std_ulogic_vector(0 to 3); + signal shx01_gp1_lat_si, shx01_gp1_lat_so, shx01_gp1_q_b, shx01_gp1_q, shx01_gp1_din :std_ulogic_vector(0 to 3); + signal mask_lat_si, mask_lat_so, mask_q_b, mask_q, mask_din :std_ulogic_vector(0 to 5); + signal shx16_sgn0_lat_si, shx16_sgn0_lat_so, shx16_sgn0_q_b, shx16_sgn0_q, shx16_sgn0_din :std_ulogic_vector(0 to 1); + signal shx04_sgn0_lat_si, shx04_sgn0_lat_so, shx04_sgn0_q_b, shx04_sgn0_q, shx04_sgn0_din :std_ulogic_vector(0 to 3); + signal shx01_sgn0_lat_si, shx01_sgn0_lat_so, shx01_sgn0_q_b, shx01_sgn0_q, shx01_sgn0_din :std_ulogic_vector(0 to 3); + + + signal mx1_0_b, mx1_1_b, mx1 :std_ulogic_vector(0 to 31); + signal sx1_0_b, sx1_1_b, sx1 :std_ulogic_vector(0 to 15); + signal mx2_0_b, mx2_1_b, mx2 :std_ulogic_vector(0 to 31); + signal sx2_0_b, sx2_1_b, sx2 :std_ulogic_vector(0 to 7); + signal mx3_0_b, mx3_1_b, mx3 :std_ulogic_vector(0 to 31); + signal sx3_0_b, sx3_1_b, sx3 :std_ulogic_vector(0 to 5); + signal do_b :std_ulogic_vector(0 to 31) ; + signal sign_copy_b :std_ulogic_vector(0 to 5) ; + + signal mx1_d0, mx1_d1, mx1_d2, mx1_d3 :std_ulogic_vector(0 to 31) ; + signal mx2_d0, mx2_d1, mx2_d2, mx2_d3 :std_ulogic_vector(0 to 31) ; + signal sx2_d0, sx2_d1, sx2_d2, sx2_d3 :std_ulogic_vector(0 to 7) ; + signal mx3_d0, mx3_d1, mx3_d2, mx3_d3 :std_ulogic_vector(0 to 31) ; + signal sx3_d0, sx3_d1, sx3_d2, sx3_d3 :std_ulogic_vector(0 to 5) ; + + signal mx1_s0, mx1_s1, mx1_s2, mx1_s3 :std_ulogic_vector(0 to 31) ; + signal sx1_s0, sx1_s1 :std_ulogic_vector(0 to 15) ; + signal mx2_s0, mx2_s1, mx2_s2, mx2_s3 :std_ulogic_vector(0 to 31) ; + signal sx2_s0, sx2_s1, sx2_s2, sx2_s3 :std_ulogic_vector(0 to 7) ; + signal mx3_s0, mx3_s1, mx3_s2, mx3_s3 :std_ulogic_vector(0 to 31) ; + signal sx3_s0, sx3_s1, sx3_s2, sx3_s3 :std_ulogic_vector(0 to 5) ; + + signal mask_en :std_ulogic_vector(0 to 31); + signal shx16_sel , shx04_sel , shx01_sel :std_ulogic_vector(0 to 3); + signal sgn_amt :std_ulogic_vector(0 to 4); + signal shx04_sgn, shx01_sgn :std_ulogic_vector(0 to 3); + signal shx16_sgn :std_ulogic_vector(0 to 1); + + + + + + + + + +begin + + + + + shx16_sel(0) <= not le and not rotate_sel(0); + shx16_sel(1) <= not le and rotate_sel(0); + shx16_sel(2) <= le and not rotate_sel(0); + shx16_sel(3) <= le and rotate_sel(0); + + shx04_sel(0) <= not rotate_sel(1) and not rotate_sel(2); + shx04_sel(1) <= not rotate_sel(1) and rotate_sel(2); + shx04_sel(2) <= rotate_sel(1) and not rotate_sel(2); + shx04_sel(3) <= rotate_sel(1) and rotate_sel(2); + + shx01_sel(0) <= not rotate_sel(3) and not rotate_sel(4); + shx01_sel(1) <= not rotate_sel(3) and rotate_sel(4); + shx01_sel(2) <= rotate_sel(3) and not rotate_sel(4); + shx01_sel(3) <= rotate_sel(3) and rotate_sel(4); + + + + + sgn_amt(0) <= algebraic_sel(0); + sgn_amt(1) <= algebraic_sel(1); + sgn_amt(2) <= algebraic_sel(2); + sgn_amt(3) <= algebraic_sel(3); + sgn_amt(4) <= algebraic_sel(4); + + shx16_sgn(0) <= not sgn_amt(0); + shx16_sgn(1) <= sgn_amt(0); + + shx04_sgn(0) <= not sgn_amt(1) and not sgn_amt(2); + shx04_sgn(1) <= not sgn_amt(1) and sgn_amt(2); + shx04_sgn(2) <= sgn_amt(1) and not sgn_amt(2); + shx04_sgn(3) <= sgn_amt(1) and sgn_amt(2); + + shx01_sgn(0) <= not sgn_amt(3) and not sgn_amt(4) and algebraic ; + shx01_sgn(1) <= not sgn_amt(3) and sgn_amt(4) and algebraic ; + shx01_sgn(2) <= sgn_amt(3) and not sgn_amt(4) and algebraic ; + shx01_sgn(3) <= sgn_amt(3) and sgn_amt(4) and algebraic ; + + mask_din(0) <= opsize(0) ; + mask_din(1) <= opsize(1) or mask_din(0) ; + mask_din(2) <= opsize(2) or mask_din(1) ; + mask_din(3) <= opsize(3) or mask_din(2) ; + mask_din(4) <= opsize(4) or mask_din(3) ; + mask_din(5) <= opsize(5) or mask_din(4) ; + + di_din(0 to 31) <= data(0 to 31); + shx16_gp0_din(0 to 3) <= shx16_sel(0 to 3); + shx16_gp1_din(0 to 3) <= shx16_sel(0 to 3); + shx04_gp0_din(0 to 3) <= shx04_sel(0 to 3); + shx04_gp1_din(0 to 3) <= shx04_sel(0 to 3); + shx01_gp0_din(0 to 3) <= shx01_sel(0 to 3); + shx01_gp1_din(0 to 3) <= shx01_sel(0 to 3); + shx16_sgn0_din(0 to 1) <= shx16_sgn(0 to 1); + shx04_sgn0_din(0 to 3) <= shx04_sgn(0 to 3); + shx01_sgn0_din(0 to 3) <= shx01_sgn(0 to 3); + + + + u_di_q: di_q(0 to 31) <= not di_q_b(0 to 31) ; + u_shx16_gp0_q: shx16_gp0_q(0 to 3) <= not shx16_gp0_q_b(0 to 3) ; + u_shx16_gp1_q: shx16_gp1_q(0 to 3) <= not shx16_gp1_q_b(0 to 3) ; + u_shx04_gp0_q: shx04_gp0_q(0 to 3) <= not shx04_gp0_q_b(0 to 3) ; + u_shx04_gp1_q: shx04_gp1_q(0 to 3) <= not shx04_gp1_q_b(0 to 3) ; + u_shx01_gp0_q: shx01_gp0_q(0 to 3) <= not shx01_gp0_q_b(0 to 3) ; + u_shx01_gp1_q: shx01_gp1_q(0 to 3) <= not shx01_gp1_q_b(0 to 3) ; + u_shx16_sgn0_q: shx16_sgn0_q(0 to 1) <= not shx16_sgn0_q_b(0 to 1) ; + u_shx04_sgn0_q: shx04_sgn0_q(0 to 3) <= not shx04_sgn0_q_b(0 to 3) ; + u_shx01_sgn0_q: shx01_sgn0_q(0 to 3) <= not shx01_sgn0_q_b(0 to 3) ; + mask_q(0 to 5) <= not mask_q_b(0 to 5) ; + + + mx1_s0( 0 to 15) <= ( 0 to 15=> shx16_gp0_q(0) ) ; + mx1_s1( 0 to 15) <= ( 0 to 15=> shx16_gp0_q(1) ) ; + mx1_s2( 0 to 15) <= ( 0 to 15=> shx16_gp0_q(2) ) ; + mx1_s3( 0 to 15) <= ( 0 to 15=> shx16_gp0_q(3) ) ; + mx1_s0(16 to 31) <= (16 to 31=> shx16_gp1_q(0) ) ; + mx1_s1(16 to 31) <= (16 to 31=> shx16_gp1_q(1) ) ; + mx1_s2(16 to 31) <= (16 to 31=> shx16_gp1_q(2) ) ; + mx1_s3(16 to 31) <= (16 to 31=> shx16_gp1_q(3) ) ; + + sx1_s0( 0 to 15) <= ( 0 to 15=> shx16_sgn0_q(0) ) ; + sx1_s1( 0 to 15) <= ( 0 to 15=> shx16_sgn0_q(1) ) ; + + mx1_d0(0) <= di_q(0) ; mx1_d1(0) <= di_q(16) ; mx1_d2(0) <= di_q(31) ; mx1_d3(0) <= di_q(15) ; + mx1_d0(1) <= di_q(1) ; mx1_d1(1) <= di_q(17) ; mx1_d2(1) <= di_q(30) ; mx1_d3(1) <= di_q(14) ; + mx1_d0(2) <= di_q(2) ; mx1_d1(2) <= di_q(18) ; mx1_d2(2) <= di_q(29) ; mx1_d3(2) <= di_q(13) ; + mx1_d0(3) <= di_q(3) ; mx1_d1(3) <= di_q(19) ; mx1_d2(3) <= di_q(28) ; mx1_d3(3) <= di_q(12) ; + mx1_d0(4) <= di_q(4) ; mx1_d1(4) <= di_q(20) ; mx1_d2(4) <= di_q(27) ; mx1_d3(4) <= di_q(11) ; + mx1_d0(5) <= di_q(5) ; mx1_d1(5) <= di_q(21) ; mx1_d2(5) <= di_q(26) ; mx1_d3(5) <= di_q(10) ; + mx1_d0(6) <= di_q(6) ; mx1_d1(6) <= di_q(22) ; mx1_d2(6) <= di_q(25) ; mx1_d3(6) <= di_q(9) ; + mx1_d0(7) <= di_q(7) ; mx1_d1(7) <= di_q(23) ; mx1_d2(7) <= di_q(24) ; mx1_d3(7) <= di_q(8) ; + mx1_d0(8) <= di_q(8) ; mx1_d1(8) <= di_q(24) ; mx1_d2(8) <= di_q(23) ; mx1_d3(8) <= di_q(7) ; + mx1_d0(9) <= di_q(9) ; mx1_d1(9) <= di_q(25) ; mx1_d2(9) <= di_q(22) ; mx1_d3(9) <= di_q(6) ; + mx1_d0(10) <= di_q(10) ; mx1_d1(10) <= di_q(26) ; mx1_d2(10) <= di_q(21) ; mx1_d3(10) <= di_q(5) ; + mx1_d0(11) <= di_q(11) ; mx1_d1(11) <= di_q(27) ; mx1_d2(11) <= di_q(20) ; mx1_d3(11) <= di_q(4) ; + mx1_d0(12) <= di_q(12) ; mx1_d1(12) <= di_q(28) ; mx1_d2(12) <= di_q(19) ; mx1_d3(12) <= di_q(3) ; + mx1_d0(13) <= di_q(13) ; mx1_d1(13) <= di_q(29) ; mx1_d2(13) <= di_q(18) ; mx1_d3(13) <= di_q(2) ; + mx1_d0(14) <= di_q(14) ; mx1_d1(14) <= di_q(30) ; mx1_d2(14) <= di_q(17) ; mx1_d3(14) <= di_q(1) ; + mx1_d0(15) <= di_q(15) ; mx1_d1(15) <= di_q(31) ; mx1_d2(15) <= di_q(16) ; mx1_d3(15) <= di_q(0) ; + mx1_d0(16) <= di_q(16) ; mx1_d1(16) <= di_q(0) ; mx1_d2(16) <= di_q(15) ; mx1_d3(16) <= di_q(31) ; + mx1_d0(17) <= di_q(17) ; mx1_d1(17) <= di_q(1) ; mx1_d2(17) <= di_q(14) ; mx1_d3(17) <= di_q(30) ; + mx1_d0(18) <= di_q(18) ; mx1_d1(18) <= di_q(2) ; mx1_d2(18) <= di_q(13) ; mx1_d3(18) <= di_q(29) ; + mx1_d0(19) <= di_q(19) ; mx1_d1(19) <= di_q(3) ; mx1_d2(19) <= di_q(12) ; mx1_d3(19) <= di_q(28) ; + mx1_d0(20) <= di_q(20) ; mx1_d1(20) <= di_q(4) ; mx1_d2(20) <= di_q(11) ; mx1_d3(20) <= di_q(27) ; + mx1_d0(21) <= di_q(21) ; mx1_d1(21) <= di_q(5) ; mx1_d2(21) <= di_q(10) ; mx1_d3(21) <= di_q(26) ; + mx1_d0(22) <= di_q(22) ; mx1_d1(22) <= di_q(6) ; mx1_d2(22) <= di_q(9) ; mx1_d3(22) <= di_q(25) ; + mx1_d0(23) <= di_q(23) ; mx1_d1(23) <= di_q(7) ; mx1_d2(23) <= di_q(8) ; mx1_d3(23) <= di_q(24) ; + mx1_d0(24) <= di_q(24) ; mx1_d1(24) <= di_q(8) ; mx1_d2(24) <= di_q(7) ; mx1_d3(24) <= di_q(23) ; + mx1_d0(25) <= di_q(25) ; mx1_d1(25) <= di_q(9) ; mx1_d2(25) <= di_q(6) ; mx1_d3(25) <= di_q(22) ; + mx1_d0(26) <= di_q(26) ; mx1_d1(26) <= di_q(10) ; mx1_d2(26) <= di_q(5) ; mx1_d3(26) <= di_q(21) ; + mx1_d0(27) <= di_q(27) ; mx1_d1(27) <= di_q(11) ; mx1_d2(27) <= di_q(4) ; mx1_d3(27) <= di_q(20) ; + mx1_d0(28) <= di_q(28) ; mx1_d1(28) <= di_q(12) ; mx1_d2(28) <= di_q(3) ; mx1_d3(28) <= di_q(19) ; + mx1_d0(29) <= di_q(29) ; mx1_d1(29) <= di_q(13) ; mx1_d2(29) <= di_q(2) ; mx1_d3(29) <= di_q(18) ; + mx1_d0(30) <= di_q(30) ; mx1_d1(30) <= di_q(14) ; mx1_d2(30) <= di_q(1) ; mx1_d3(30) <= di_q(17) ; + mx1_d0(31) <= di_q(31) ; mx1_d1(31) <= di_q(15) ; mx1_d2(31) <= di_q(0) ; mx1_d3(31) <= di_q(16) ; + + + u_mx1_0: mx1_0_b(0 to 31) <= not( (mx1_s0(0 to 31) and mx1_d0(0 to 31) ) or + (mx1_s1(0 to 31) and mx1_d1(0 to 31) ) ); + + u_mx1_1: mx1_1_b(0 to 31) <= not( (mx1_s2(0 to 31) and mx1_d2(0 to 31) ) or + (mx1_s3(0 to 31) and mx1_d3(0 to 31) ) ); + + u_mx1: mx1(0 to 31) <= not( mx1_0_b(0 to 31) and mx1_1_b(0 to 31) ); + + + + + u_sx1_0: sx1_0_b(0 to 15) <= not( sx1_s0(0 to 15) and mx1_d0(0 to 15) ) ; + u_sx1_1: sx1_1_b(0 to 15) <= not( sx1_s1(0 to 15) and mx1_d1(0 to 15) ) ; + u_sx1: sx1(0 to 15) <= not( sx1_0_b(0 to 15) and sx1_1_b(0 to 15) ); + + + mx2_s0( 0 to 15) <= ( 0 to 15=> shx04_gp0_q(0) ) ; + mx2_s1( 0 to 15) <= ( 0 to 15=> shx04_gp0_q(1) ) ; + mx2_s2( 0 to 15) <= ( 0 to 15=> shx04_gp0_q(2) ) ; + mx2_s3( 0 to 15) <= ( 0 to 15=> shx04_gp0_q(3) ) ; + mx2_s0(16 to 31) <= (16 to 31=> shx04_gp1_q(0) ) ; + mx2_s1(16 to 31) <= (16 to 31=> shx04_gp1_q(1) ) ; + mx2_s2(16 to 31) <= (16 to 31=> shx04_gp1_q(2) ) ; + mx2_s3(16 to 31) <= (16 to 31=> shx04_gp1_q(3) ) ; + + + mx2_d0(0) <= mx1(0) ; mx2_d1(0) <= mx1(28) ; mx2_d2(0) <= mx1(24) ; mx2_d3(0) <= mx1(20) ; + mx2_d0(1) <= mx1(1) ; mx2_d1(1) <= mx1(29) ; mx2_d2(1) <= mx1(25) ; mx2_d3(1) <= mx1(21) ; + mx2_d0(2) <= mx1(2) ; mx2_d1(2) <= mx1(30) ; mx2_d2(2) <= mx1(26) ; mx2_d3(2) <= mx1(22) ; + mx2_d0(3) <= mx1(3) ; mx2_d1(3) <= mx1(31) ; mx2_d2(3) <= mx1(27) ; mx2_d3(3) <= mx1(23) ; + mx2_d0(4) <= mx1(4) ; mx2_d1(4) <= mx1(0) ; mx2_d2(4) <= mx1(28) ; mx2_d3(4) <= mx1(24) ; + mx2_d0(5) <= mx1(5) ; mx2_d1(5) <= mx1(1) ; mx2_d2(5) <= mx1(29) ; mx2_d3(5) <= mx1(25) ; + mx2_d0(6) <= mx1(6) ; mx2_d1(6) <= mx1(2) ; mx2_d2(6) <= mx1(30) ; mx2_d3(6) <= mx1(26) ; + mx2_d0(7) <= mx1(7) ; mx2_d1(7) <= mx1(3) ; mx2_d2(7) <= mx1(31) ; mx2_d3(7) <= mx1(27) ; + mx2_d0(8) <= mx1(8) ; mx2_d1(8) <= mx1(4) ; mx2_d2(8) <= mx1(0) ; mx2_d3(8) <= mx1(28) ; + mx2_d0(9) <= mx1(9) ; mx2_d1(9) <= mx1(5) ; mx2_d2(9) <= mx1(1) ; mx2_d3(9) <= mx1(29) ; + mx2_d0(10) <= mx1(10) ; mx2_d1(10) <= mx1(6) ; mx2_d2(10) <= mx1(2) ; mx2_d3(10) <= mx1(30) ; + mx2_d0(11) <= mx1(11) ; mx2_d1(11) <= mx1(7) ; mx2_d2(11) <= mx1(3) ; mx2_d3(11) <= mx1(31) ; + mx2_d0(12) <= mx1(12) ; mx2_d1(12) <= mx1(8) ; mx2_d2(12) <= mx1(4) ; mx2_d3(12) <= mx1(0) ; + mx2_d0(13) <= mx1(13) ; mx2_d1(13) <= mx1(9) ; mx2_d2(13) <= mx1(5) ; mx2_d3(13) <= mx1(1) ; + mx2_d0(14) <= mx1(14) ; mx2_d1(14) <= mx1(10) ; mx2_d2(14) <= mx1(6) ; mx2_d3(14) <= mx1(2) ; + mx2_d0(15) <= mx1(15) ; mx2_d1(15) <= mx1(11) ; mx2_d2(15) <= mx1(7) ; mx2_d3(15) <= mx1(3) ; + mx2_d0(16) <= mx1(16) ; mx2_d1(16) <= mx1(12) ; mx2_d2(16) <= mx1(8) ; mx2_d3(16) <= mx1(4) ; + mx2_d0(17) <= mx1(17) ; mx2_d1(17) <= mx1(13) ; mx2_d2(17) <= mx1(9) ; mx2_d3(17) <= mx1(5) ; + mx2_d0(18) <= mx1(18) ; mx2_d1(18) <= mx1(14) ; mx2_d2(18) <= mx1(10) ; mx2_d3(18) <= mx1(6) ; + mx2_d0(19) <= mx1(19) ; mx2_d1(19) <= mx1(15) ; mx2_d2(19) <= mx1(11) ; mx2_d3(19) <= mx1(7) ; + mx2_d0(20) <= mx1(20) ; mx2_d1(20) <= mx1(16) ; mx2_d2(20) <= mx1(12) ; mx2_d3(20) <= mx1(8) ; + mx2_d0(21) <= mx1(21) ; mx2_d1(21) <= mx1(17) ; mx2_d2(21) <= mx1(13) ; mx2_d3(21) <= mx1(9) ; + mx2_d0(22) <= mx1(22) ; mx2_d1(22) <= mx1(18) ; mx2_d2(22) <= mx1(14) ; mx2_d3(22) <= mx1(10) ; + mx2_d0(23) <= mx1(23) ; mx2_d1(23) <= mx1(19) ; mx2_d2(23) <= mx1(15) ; mx2_d3(23) <= mx1(11) ; + mx2_d0(24) <= mx1(24) ; mx2_d1(24) <= mx1(20) ; mx2_d2(24) <= mx1(16) ; mx2_d3(24) <= mx1(12) ; + mx2_d0(25) <= mx1(25) ; mx2_d1(25) <= mx1(21) ; mx2_d2(25) <= mx1(17) ; mx2_d3(25) <= mx1(13) ; + mx2_d0(26) <= mx1(26) ; mx2_d1(26) <= mx1(22) ; mx2_d2(26) <= mx1(18) ; mx2_d3(26) <= mx1(14) ; + mx2_d0(27) <= mx1(27) ; mx2_d1(27) <= mx1(23) ; mx2_d2(27) <= mx1(19) ; mx2_d3(27) <= mx1(15) ; + mx2_d0(28) <= mx1(28) ; mx2_d1(28) <= mx1(24) ; mx2_d2(28) <= mx1(20) ; mx2_d3(28) <= mx1(16) ; + mx2_d0(29) <= mx1(29) ; mx2_d1(29) <= mx1(25) ; mx2_d2(29) <= mx1(21) ; mx2_d3(29) <= mx1(17) ; + mx2_d0(30) <= mx1(30) ; mx2_d1(30) <= mx1(26) ; mx2_d2(30) <= mx1(22) ; mx2_d3(30) <= mx1(18) ; + mx2_d0(31) <= mx1(31) ; mx2_d1(31) <= mx1(27) ; mx2_d2(31) <= mx1(23) ; mx2_d3(31) <= mx1(19) ; + + + u_mx2_0: mx2_0_b(0 to 31) <= not( (mx2_s0(0 to 31) and mx2_d0(0 to 31) ) or + (mx2_s1(0 to 31) and mx2_d1(0 to 31) ) ); + + u_mx2_1: mx2_1_b(0 to 31) <= not( (mx2_s2(0 to 31) and mx2_d2(0 to 31) ) or + (mx2_s3(0 to 31) and mx2_d3(0 to 31) ) ); + + u_mx2: mx2(0 to 31) <= not( mx2_0_b(0 to 31) and mx2_1_b(0 to 31) ); + + + sx2_s0( 0 to 7) <= ( 0 to 7=> shx04_sgn0_q(0) ) ; + sx2_s1( 0 to 7) <= ( 0 to 7=> shx04_sgn0_q(1) ) ; + sx2_s2( 0 to 7) <= ( 0 to 7=> shx04_sgn0_q(2) ) ; + sx2_s3( 0 to 7) <= ( 0 to 7=> shx04_sgn0_q(3) ) ; + + sx2_d0(0) <= sx1(0) ; sx2_d1(0) <= sx1(4) ; sx2_d2(0) <= sx1(8) ; sx2_d3(0) <= sx1(12) ; + sx2_d0(1) <= sx1(1) ; sx2_d1(1) <= sx1(5) ; sx2_d2(1) <= sx1(9) ; sx2_d3(1) <= sx1(13) ; + sx2_d0(2) <= sx1(2) ; sx2_d1(2) <= sx1(6) ; sx2_d2(2) <= sx1(10) ; sx2_d3(2) <= sx1(14) ; + sx2_d0(3) <= sx1(3) ; sx2_d1(3) <= sx1(7) ; sx2_d2(3) <= sx1(11) ; sx2_d3(3) <= sx1(15) ; + sx2_d0(4) <= sx1(0) ; sx2_d1(4) <= sx1(4) ; sx2_d2(4) <= sx1(8) ; sx2_d3(4) <= sx1(12) ; + sx2_d0(5) <= sx1(1) ; sx2_d1(5) <= sx1(5) ; sx2_d2(5) <= sx1(9) ; sx2_d3(5) <= sx1(13) ; + sx2_d0(6) <= sx1(2) ; sx2_d1(6) <= sx1(6) ; sx2_d2(6) <= sx1(10) ; sx2_d3(6) <= sx1(14) ; + sx2_d0(7) <= sx1(3) ; sx2_d1(7) <= sx1(7) ; sx2_d2(7) <= sx1(11) ; sx2_d3(7) <= sx1(15) ; + + + + + u_sx2_0: sx2_0_b(0 to 7) <= not( (sx2_s0(0 to 7) and sx2_d0(0 to 7) ) or + (sx2_s1(0 to 7) and sx2_d1(0 to 7) ) ); + + u_sx2_1: sx2_1_b(0 to 7) <= not( (sx2_s2(0 to 7) and sx2_d2(0 to 7) ) or + (sx2_s3(0 to 7) and sx2_d3(0 to 7) ) ); + + u_sx2: sx2(0 to 7) <= not( sx2_0_b(0 to 7) and sx2_1_b(0 to 7) ); + + + mask_en( 0 to 15) <= ( 0 to 15=> mask_q(0) ); + mask_en(16 to 23) <= (16 to 23=> mask_q(1) ); + mask_en(24 to 27) <= (24 to 27=> mask_q(2) ); + mask_en(28 to 29) <= (28 to 29=> mask_q(3) ); + mask_en(30) <= ( mask_q(4) ); + mask_en(31) <= ( mask_q(5) ); + + mx3_s0( 0 to 15) <= ( 0 to 15=> shx01_gp0_q(0) ) and mask_en( 0 to 15); + mx3_s1( 0 to 15) <= ( 0 to 15=> shx01_gp0_q(1) ) and mask_en( 0 to 15); + mx3_s2( 0 to 15) <= ( 0 to 15=> shx01_gp0_q(2) ) and mask_en( 0 to 15); + mx3_s3( 0 to 15) <= ( 0 to 15=> shx01_gp0_q(3) ) and mask_en( 0 to 15); + mx3_s0(16 to 31) <= (16 to 31=> shx01_gp1_q(0) ) and mask_en(16 to 31); + mx3_s1(16 to 31) <= (16 to 31=> shx01_gp1_q(1) ) and mask_en(16 to 31); + mx3_s2(16 to 31) <= (16 to 31=> shx01_gp1_q(2) ) and mask_en(16 to 31); + mx3_s3(16 to 31) <= (16 to 31=> shx01_gp1_q(3) ) and mask_en(16 to 31); + + + mx3_d0(0) <= mx2(0) ; mx3_d1(0) <= mx2(31) ; mx3_d2(0) <= mx2(30) ; mx3_d3(0) <= mx2(29) ; + mx3_d0(1) <= mx2(1) ; mx3_d1(1) <= mx2(0) ; mx3_d2(1) <= mx2(31) ; mx3_d3(1) <= mx2(30) ; + mx3_d0(2) <= mx2(2) ; mx3_d1(2) <= mx2(1) ; mx3_d2(2) <= mx2(0) ; mx3_d3(2) <= mx2(31) ; + mx3_d0(3) <= mx2(3) ; mx3_d1(3) <= mx2(2) ; mx3_d2(3) <= mx2(1) ; mx3_d3(3) <= mx2(0) ; + mx3_d0(4) <= mx2(4) ; mx3_d1(4) <= mx2(3) ; mx3_d2(4) <= mx2(2) ; mx3_d3(4) <= mx2(1) ; + mx3_d0(5) <= mx2(5) ; mx3_d1(5) <= mx2(4) ; mx3_d2(5) <= mx2(3) ; mx3_d3(5) <= mx2(2) ; + mx3_d0(6) <= mx2(6) ; mx3_d1(6) <= mx2(5) ; mx3_d2(6) <= mx2(4) ; mx3_d3(6) <= mx2(3) ; + mx3_d0(7) <= mx2(7) ; mx3_d1(7) <= mx2(6) ; mx3_d2(7) <= mx2(5) ; mx3_d3(7) <= mx2(4) ; + mx3_d0(8) <= mx2(8) ; mx3_d1(8) <= mx2(7) ; mx3_d2(8) <= mx2(6) ; mx3_d3(8) <= mx2(5) ; + mx3_d0(9) <= mx2(9) ; mx3_d1(9) <= mx2(8) ; mx3_d2(9) <= mx2(7) ; mx3_d3(9) <= mx2(6) ; + mx3_d0(10) <= mx2(10) ; mx3_d1(10) <= mx2(9) ; mx3_d2(10) <= mx2(8) ; mx3_d3(10) <= mx2(7) ; + mx3_d0(11) <= mx2(11) ; mx3_d1(11) <= mx2(10) ; mx3_d2(11) <= mx2(9) ; mx3_d3(11) <= mx2(8) ; + mx3_d0(12) <= mx2(12) ; mx3_d1(12) <= mx2(11) ; mx3_d2(12) <= mx2(10) ; mx3_d3(12) <= mx2(9) ; + mx3_d0(13) <= mx2(13) ; mx3_d1(13) <= mx2(12) ; mx3_d2(13) <= mx2(11) ; mx3_d3(13) <= mx2(10) ; + mx3_d0(14) <= mx2(14) ; mx3_d1(14) <= mx2(13) ; mx3_d2(14) <= mx2(12) ; mx3_d3(14) <= mx2(11) ; + mx3_d0(15) <= mx2(15) ; mx3_d1(15) <= mx2(14) ; mx3_d2(15) <= mx2(13) ; mx3_d3(15) <= mx2(12) ; + mx3_d0(16) <= mx2(16) ; mx3_d1(16) <= mx2(15) ; mx3_d2(16) <= mx2(14) ; mx3_d3(16) <= mx2(13) ; + mx3_d0(17) <= mx2(17) ; mx3_d1(17) <= mx2(16) ; mx3_d2(17) <= mx2(15) ; mx3_d3(17) <= mx2(14) ; + mx3_d0(18) <= mx2(18) ; mx3_d1(18) <= mx2(17) ; mx3_d2(18) <= mx2(16) ; mx3_d3(18) <= mx2(15) ; + mx3_d0(19) <= mx2(19) ; mx3_d1(19) <= mx2(18) ; mx3_d2(19) <= mx2(17) ; mx3_d3(19) <= mx2(16) ; + mx3_d0(20) <= mx2(20) ; mx3_d1(20) <= mx2(19) ; mx3_d2(20) <= mx2(18) ; mx3_d3(20) <= mx2(17) ; + mx3_d0(21) <= mx2(21) ; mx3_d1(21) <= mx2(20) ; mx3_d2(21) <= mx2(19) ; mx3_d3(21) <= mx2(18) ; + mx3_d0(22) <= mx2(22) ; mx3_d1(22) <= mx2(21) ; mx3_d2(22) <= mx2(20) ; mx3_d3(22) <= mx2(19) ; + mx3_d0(23) <= mx2(23) ; mx3_d1(23) <= mx2(22) ; mx3_d2(23) <= mx2(21) ; mx3_d3(23) <= mx2(20) ; + mx3_d0(24) <= mx2(24) ; mx3_d1(24) <= mx2(23) ; mx3_d2(24) <= mx2(22) ; mx3_d3(24) <= mx2(21) ; + mx3_d0(25) <= mx2(25) ; mx3_d1(25) <= mx2(24) ; mx3_d2(25) <= mx2(23) ; mx3_d3(25) <= mx2(22) ; + mx3_d0(26) <= mx2(26) ; mx3_d1(26) <= mx2(25) ; mx3_d2(26) <= mx2(24) ; mx3_d3(26) <= mx2(23) ; + mx3_d0(27) <= mx2(27) ; mx3_d1(27) <= mx2(26) ; mx3_d2(27) <= mx2(25) ; mx3_d3(27) <= mx2(24) ; + mx3_d0(28) <= mx2(28) ; mx3_d1(28) <= mx2(27) ; mx3_d2(28) <= mx2(26) ; mx3_d3(28) <= mx2(25) ; + mx3_d0(29) <= mx2(29) ; mx3_d1(29) <= mx2(28) ; mx3_d2(29) <= mx2(27) ; mx3_d3(29) <= mx2(26) ; + mx3_d0(30) <= mx2(30) ; mx3_d1(30) <= mx2(29) ; mx3_d2(30) <= mx2(28) ; mx3_d3(30) <= mx2(27) ; + mx3_d0(31) <= mx2(31) ; mx3_d1(31) <= mx2(30) ; mx3_d2(31) <= mx2(29) ; mx3_d3(31) <= mx2(28) ; + + u_mx3_0: mx3_0_b(0 to 31) <= not( (mx3_s0(0 to 31) and mx3_d0(0 to 31) ) or + (mx3_s1(0 to 31) and mx3_d1(0 to 31) ) ); + + u_mx3_1: mx3_1_b(0 to 31) <= not( (mx3_s2(0 to 31) and mx3_d2(0 to 31) ) or + (mx3_s3(0 to 31) and mx3_d3(0 to 31) ) ); + + u_mx3: mx3(0 to 31) <= not( mx3_0_b(0 to 31) and mx3_1_b(0 to 31) ); + + u_oi1: do_b(0 to 31) <= not( mx3(0 to 31) ) ; + u_oi2: data_rot(0 to 31) <= not( do_b(0 to 31) ) ; + + u_oth_i: data_latched <= not di_q_b; + + sx3_s0( 0 to 3) <= ( 0 to 3=> shx01_sgn0_q(0) ) ; + sx3_s1( 0 to 3) <= ( 0 to 3=> shx01_sgn0_q(1) ) ; + sx3_s2( 0 to 3) <= ( 0 to 3=> shx01_sgn0_q(2) ) ; + sx3_s3( 0 to 3) <= ( 0 to 3=> shx01_sgn0_q(3) ) ; + + sx3_s0( 4 to 5) <= ( 4 to 5=> shx01_sgn0_q(0) ) and (4 to 5=> not mask_q(3) ); + sx3_s1( 4 to 5) <= ( 4 to 5=> shx01_sgn0_q(1) ) and (4 to 5=> not mask_q(3) ); + sx3_s2( 4 to 5) <= ( 4 to 5=> shx01_sgn0_q(2) ) and (4 to 5=> not mask_q(3) ); + sx3_s3( 4 to 5) <= ( 4 to 5=> shx01_sgn0_q(3) ) and (4 to 5=> not mask_q(3) ); + + sx3_d0(0) <= sx2(0) ; sx3_d1(0) <= sx2(1) ; sx3_d2(0) <= sx2(2) ; sx3_d3(0) <= sx2(3) ; + sx3_d0(1) <= sx2(0) ; sx3_d1(1) <= sx2(1) ; sx3_d2(1) <= sx2(2) ; sx3_d3(1) <= sx2(3) ; + sx3_d0(2) <= sx2(0) ; sx3_d1(2) <= sx2(1) ; sx3_d2(2) <= sx2(2) ; sx3_d3(2) <= sx2(3) ; + sx3_d0(3) <= sx2(4) ; sx3_d1(3) <= sx2(5) ; sx3_d2(3) <= sx2(6) ; sx3_d3(3) <= sx2(7) ; + sx3_d0(4) <= sx2(4) ; sx3_d1(4) <= sx2(5) ; sx3_d2(4) <= sx2(6) ; sx3_d3(4) <= sx2(7) ; + sx3_d0(5) <= sx2(4) ; sx3_d1(5) <= sx2(5) ; sx3_d2(5) <= sx2(6) ; sx3_d3(5) <= sx2(7) ; + + + u_sx3_0: sx3_0_b(0 to 5) <= not( (sx3_s0(0 to 5) and sx3_d0(0 to 5) ) or + (sx3_s1(0 to 5) and sx3_d1(0 to 5) ) ); + + u_sx3_1: sx3_1_b(0 to 5) <= not( (sx3_s2(0 to 5) and sx3_d2(0 to 5) ) or + (sx3_s3(0 to 5) and sx3_d3(0 to 5) ) ); + + u_sx3: sx3(0 to 5) <= not( sx3_0_b(0 to 5) and sx3_1_b(0 to 5) ); + + u_oi1s: sign_copy_b(0 to 5) <= not( sx3(0 to 5) ) ; + u_oi2s: algebraic_bit(0 to 5) <= not( sign_copy_b(0 to 5) ) ; + + + + di_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 32, init=>(1 to 32=>'0'), btr => "NLI0001_X4_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + VD => vdd , + GD => gnd , + LCLK => my_lclk , + D1CLK => my_d1clk , + D2CLK => my_d2clk , + SCANIN => di_lat_si , + SCANOUT => di_lat_so , + D => di_din(0 to 31) , + QB => di_q_b(0 to 31) ); + + shx16_gp0_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 4, init=>(1 to 4=>'0'), btr => "NLI0001_X4_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + VD => vdd , + GD => gnd , + LCLK => my_lclk , + D1CLK => my_d1clk , + D2CLK => my_d2clk , + SCANIN => shx16_gp0_lat_si , + SCANOUT => shx16_gp0_lat_so , + D => shx16_gp0_din , + QB => shx16_gp0_q_b(0 to 3) ); + + shx16_gp1_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 4, init=>(1 to 4=>'0'), btr => "NLI0001_X4_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + VD => vdd , + GD => gnd , + LCLK => my_lclk , + D1CLK => my_d1clk , + D2CLK => my_d2clk , + SCANIN => shx16_gp1_lat_si , + SCANOUT => shx16_gp1_lat_so , + D => shx16_gp1_din , + QB => shx16_gp1_q_b(0 to 3) ); + + shx04_gp0_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 4, init=>(1 to 4=>'0'), btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + VD => vdd , + GD => gnd , + LCLK => my_lclk , + D1CLK => my_d1clk , + D2CLK => my_d2clk , + SCANIN => shx04_gp0_lat_si , + SCANOUT => shx04_gp0_lat_so , + D => shx04_gp0_din , + QB => shx04_gp0_q_b(0 to 3) ); + + shx04_gp1_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 4, init=>(1 to 4=>'0'), btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + VD => vdd , + GD => gnd , + LCLK => my_lclk , + D1CLK => my_d1clk , + D2CLK => my_d2clk , + SCANIN => shx04_gp1_lat_si , + SCANOUT => shx04_gp1_lat_so , + D => shx04_gp1_din , + QB => shx04_gp1_q_b(0 to 3) ); + + shx01_gp0_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 4, init=>(1 to 4=>'0'), btr => "NLI0001_X1_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + VD => vdd , + GD => gnd , + LCLK => my_lclk , + D1CLK => my_d1clk , + D2CLK => my_d2clk , + SCANIN => shx01_gp0_lat_si , + SCANOUT => shx01_gp0_lat_so , + D => shx01_gp0_din , + QB => shx01_gp0_q_b(0 to 3) ); + + shx01_gp1_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 4, init=>(1 to 4=>'0'), btr => "NLI0001_X1_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + VD => vdd , + GD => gnd , + LCLK => my_lclk , + D1CLK => my_d1clk , + D2CLK => my_d2clk , + SCANIN => shx01_gp1_lat_si , + SCANOUT => shx01_gp1_lat_so , + D => shx01_gp1_din , + QB => shx01_gp1_q_b(0 to 3) ); + + mask_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 6, init=>(1 to 6=>'0'), btr => "NLI0001_X1_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + VD => vdd , + GD => gnd , + LCLK => my_lclk , + D1CLK => my_d1clk , + D2CLK => my_d2clk , + SCANIN => mask_lat_si , + SCANOUT => mask_lat_so , + D => mask_din , + QB => mask_q_b(0 to 5) ); + + + + shx16_sgn0_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 2, init=>(1 to 2=>'0'),btr => "NLI0001_X4_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + VD => vdd , + GD => gnd , + LCLK => my_lclk , + D1CLK => my_d1clk , + D2CLK => my_d2clk , + SCANIN => shx16_sgn0_lat_si , + SCANOUT => shx16_sgn0_lat_so , + D => shx16_sgn0_din , + QB => shx16_sgn0_q_b(0 to 1) ); + + + shx04_sgn0_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 4, init=>(1 to 4=>'0'),btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + VD => vdd , + GD => gnd , + LCLK => my_lclk , + D1CLK => my_d1clk , + D2CLK => my_d2clk , + SCANIN => shx04_sgn0_lat_si , + SCANOUT => shx04_sgn0_lat_so , + D => shx04_sgn0_din , + QB => shx04_sgn0_q_b(0 to 3) ); + + shx01_sgn0_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 4, init=>(1 to 4=>'0'),btr => "NLI0001_X1_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + VD => vdd , + GD => gnd , + LCLK => my_lclk , + D1CLK => my_d1clk , + D2CLK => my_d2clk , + SCANIN => shx01_sgn0_lat_si , + SCANOUT => shx01_sgn0_lat_so , + D => shx01_sgn0_din , + QB => shx01_sgn0_q_b(0 to 3) ); + + + di_lat_si(0) <= scan_in; + di_lat_si(1 to 31) <= di_lat_so(0 to 30); + shx16_gp0_lat_si(0) <= di_lat_so(31); + shx16_gp0_lat_si(1 to 3) <= shx16_gp0_lat_so(0 to 2); + shx16_gp1_lat_si(0) <= shx16_gp0_lat_so(3); + shx16_gp1_lat_si(1 to 3) <= shx16_gp1_lat_so(0 to 2); + shx04_gp0_lat_si(0) <= shx16_gp1_lat_so(3); + shx04_gp0_lat_si(1 to 3) <= shx04_gp0_lat_so(0 to 2); + shx04_gp1_lat_si(0) <= shx04_gp0_lat_so(3); + shx04_gp1_lat_si(1 to 3) <= shx04_gp1_lat_so(0 to 2); + shx01_gp0_lat_si(0) <= shx04_gp1_lat_so(3); + shx01_gp0_lat_si(1 to 3) <= shx01_gp0_lat_so(0 to 2); + shx01_gp1_lat_si(0) <= shx01_gp0_lat_so(3); + shx01_gp1_lat_si(1 to 3) <= shx01_gp1_lat_so(0 to 2); + mask_lat_si(0) <= shx01_gp1_lat_so(3); + mask_lat_si(1 to 5) <= mask_lat_so(0 to 4); + shx16_sgn0_lat_si(0) <= mask_lat_so(5); + shx16_sgn0_lat_si(1) <= shx16_sgn0_lat_so(0); + shx04_sgn0_lat_si(0) <= shx16_sgn0_lat_so(1); + shx04_sgn0_lat_si(1 to 3) <= shx04_sgn0_lat_so(0 to 2); + shx01_sgn0_lat_si(0) <= shx04_sgn0_lat_so(3); + shx01_sgn0_lat_si(1 to 3) <= shx01_sgn0_lat_so(0 to 2); + scan_out <= shx01_sgn0_lat_so(3); + + + my_lcb: tri_lcbnd generic map (expand_type => expand_type) port map ( + delay_lclkr => delay_lclkr_dc , + mpw1_b => mpw1_dc_b , + mpw2_b => mpw2_dc_b , + forcee => func_sl_force , + nclk => nclk , + vd => vdd , + gd => gnd , + act => act , + sg => sg_0 , + thold_b => func_sl_thold_0_b , + d1clk => my_d1clk , + d2clk => my_d2clk , + lclk => my_lclk ); + +end architecture xuq_lsu_data_rot32s_ru; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_data_st.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_data_st.vhdl new file mode 100644 index 0000000..1320855 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_data_st.vhdl @@ -0,0 +1,937 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ibm, ieee, work, tri, support; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use tri.tri_latches_pkg.all; +use support.power_logic_pkg.all; + +entity xuq_lsu_data_st is +generic(expand_type : integer := 2; + regmode : integer := 6; + l_endian_m : integer := 1); +port( + + ex2_stg_act :in std_ulogic; + ex3_stg_act :in std_ulogic; + rel2_stg_act :in std_ulogic; + rel3_stg_act :in std_ulogic; + rel2_ex2_stg_act :in std_ulogic; + rel3_ex3_stg_act :in std_ulogic; + + rel_data_rot_sel :in std_ulogic; + ldq_rel_rot_sel :in std_ulogic_vector(0 to 4); + ldq_rel_op_size :in std_ulogic_vector(0 to 5); + ldq_rel_le_mode :in std_ulogic; + ldq_rel_algebraic :in std_ulogic; + ldq_rel_data_val :in std_ulogic_vector(0 to 15); + rel_alg_bit :in std_ulogic; + + ex2_opsize :in std_ulogic_vector(0 to 5); + ex2_rot_sel :in std_ulogic_vector(0 to 4); + ex2_rot_sel_le :in std_ulogic_vector(0 to 3); + ex2_rot_addr :in std_ulogic_vector(1 to 5); + ex4_le_mode_sel :in std_ulogic_vector(0 to 15); + ex4_be_mode_sel :in std_ulogic_vector(0 to 15); + + rel_ex3_data :in std_ulogic_vector(0 to 255); + rel_ex3_par_gen :in std_ulogic_vector(0 to 31); + + rel_256ld_data :out std_ulogic_vector(0 to 255); + rel_64ld_data :out std_ulogic_vector(64-(2**regmode) to 63); + rel_xu_ld_par :out std_ulogic_vector(0 to 7); + ex4_256st_data :out std_ulogic_vector(0 to 255); + ex3_byte_en :out std_ulogic_vector(0 to 31); + ex4_parity_gen :out std_ulogic_vector(0 to 31); + rel_axu_le_mode :out std_ulogic; + rel_dvc_byte_mask :out std_ulogic_vector((64-(2**regmode))/8 to 7); + + vdd :inout power_logic; + gnd :inout power_logic; + nclk :in clk_logic; + sg_0 :in std_ulogic; + func_sl_thold_0_b :in std_ulogic; + func_sl_force :in std_ulogic; + func_nsl_thold_0_b :in std_ulogic; + func_nsl_force :in std_ulogic; + d_mode_dc :in std_ulogic; + delay_lclkr_dc :in std_ulogic; + mpw1_dc_b :in std_ulogic; + mpw2_dc_b :in std_ulogic; + scan_in :in std_ulogic; + scan_out :out std_ulogic + ); +-- synopsys translate_off +-- synopsys translate_on +end xuq_lsu_data_st; +architecture xuq_lsu_data_st of xuq_lsu_data_st is + + +constant ex3_byte_en_offset :natural := 0; +constant rel_opsize_offset :natural := ex3_byte_en_offset + 32; +constant rel_xu_le_mode_offset :natural := rel_opsize_offset + 6; +constant rel_algebraic_offset :natural := rel_xu_le_mode_offset + 1; +constant ex4_wrt_data_offset :natural := rel_algebraic_offset + 1; +constant ex4_wrt_data_le_offset :natural := ex4_wrt_data_offset + 256; +constant rel_256ld_data_offset :natural := ex4_wrt_data_le_offset + 256; +constant rel_dvc_byte_mask_offset :natural := rel_256ld_data_offset + 256; +constant ex4_parity_gen_offset :natural := rel_dvc_byte_mask_offset + (2**regmode)/8; +constant ex4_parity_gen_le_offset :natural := ex4_parity_gen_offset + 32; +constant my_spare_latches_offset :natural := ex4_parity_gen_le_offset + 32; +constant scan_right :natural := my_spare_latches_offset + 12 - 1; + +signal op_size :std_ulogic_vector(0 to 5); +signal op_sel :std_ulogic_vector(0 to 15); +signal be10_en :std_ulogic_vector(0 to 31); +signal beC840_en :std_ulogic_vector(0 to 31); +signal be3210_en :std_ulogic_vector(0 to 31); +signal byte_en :std_ulogic_vector(0 to 31); +signal ex3_byte_en_d :std_ulogic_vector(0 to 31); +signal ex3_byte_en_q :std_ulogic_vector(0 to 31); +signal rot_addr :std_ulogic_vector(1 to 5); +signal data256_rot :std_ulogic_vector(0 to 255); +signal data256_rot_le :std_ulogic_vector(0 to 255); +signal rot_sel :std_ulogic_vector(0 to 4); +signal rot_sel_le :std_ulogic_vector(0 to 3); +signal rel_upd_gpr :std_ulogic; +signal rel_rot_sel :std_ulogic_vector(0 to 4); +signal rel_le_mode :std_ulogic; +signal rel_opsize_d :std_ulogic_vector(0 to 5); +signal rel_opsize_q :std_ulogic_vector(0 to 5); +signal rel_xu_le_mode_d :std_ulogic; +signal rel_xu_le_mode_q :std_ulogic; +signal rel_xu_opsize :std_ulogic_vector(0 to 5); +signal rel_xu_algebraic :std_ulogic; +signal optype_mask :std_ulogic_vector(0 to 255); +signal bittype_mask :std_ulogic_vector(0 to 31); +signal rel_msk_data :std_ulogic_vector(0 to 255); +signal rel_algebraic_d :std_ulogic; +signal rel_algebraic_q :std_ulogic; +signal lh_algebraic :std_ulogic; +signal lw_algebraic :std_ulogic; +signal lh_algebraic_msk :std_ulogic_vector(0 to 47); +signal lw_algebraic_msk :std_ulogic_vector(0 to 47); +signal algebraic_msk :std_ulogic_vector(0 to 47); +signal algebraic_msk_data :std_ulogic_vector(0 to 255); +signal rel_parity_gen :std_ulogic_vector(0 to 7); +signal rel_xu_data :std_ulogic_vector(0 to 255); +signal rotate_select :std_ulogic_vector(0 to 4); +signal rotate_sel1 :std_ulogic_vector(0 to 3); +signal rotate_sel2 :std_ulogic_vector(0 to 3); +signal rotate_sel3 :std_ulogic_vector(0 to 3); +signal le_rotate_sel2 :std_ulogic_vector(0 to 3); +signal le_rotate_sel3 :std_ulogic_vector(0 to 3); +signal rel_xu_rot_sel1 :std_ulogic_vector(0 to 63); +signal rel_xu_rot_sel1_d :std_ulogic_vector(0 to 63); +signal rel_xu_rot_sel1_q :std_ulogic_vector(0 to 63); +signal rel_xu_rot_sel2 :std_ulogic_vector(0 to 63); +signal rel_xu_rot_sel2_d :std_ulogic_vector(0 to 63); +signal rel_xu_rot_sel2_q :std_ulogic_vector(0 to 63); +signal rel_xu_rot_sel3 :std_ulogic_vector(0 to 63); +signal rel_xu_rot_sel3_d :std_ulogic_vector(0 to 63); +signal rel_xu_rot_sel3_q :std_ulogic_vector(0 to 63); +signal le_xu_rot_sel2 :std_ulogic_vector(0 to 63); +signal le_xu_rot_sel2_d :std_ulogic_vector(0 to 63); +signal le_xu_rot_sel2_q :std_ulogic_vector(0 to 63); +signal le_xu_rot_sel3 :std_ulogic_vector(0 to 63); +signal le_xu_rot_sel3_d :std_ulogic_vector(0 to 63); +signal le_xu_rot_sel3_q :std_ulogic_vector(0 to 63); +signal le_mode_select :std_ulogic; +signal reload_algbit :std_ulogic; +signal lvl1_sel :std_ulogic_vector(0 to 1); +signal lvl2_sel :std_ulogic_vector(0 to 1); +signal lvl3_sel :std_ulogic_vector(0 to 1); +signal le_lvl2_sel :std_ulogic_vector(0 to 1); +signal le_lvl3_sel :std_ulogic_vector(0 to 1); +signal rel_xu_par_gen :std_ulogic_vector(0 to 31); +signal pgrot3210 :std_ulogic_vector(0 to 31); +signal pgrotC840 :std_ulogic_vector(0 to 31); +signal pgrot10 :std_ulogic_vector(0 to 31); +signal ex3_par_rot :std_ulogic_vector(0 to 31); +signal rel_swzl_data :std_ulogic_vector(0 to 255); +signal rel_val_data :std_ulogic_vector(0 to 15); +signal ex3_parity_gen :std_ulogic_vector(0 to 31); +signal ex4_parity_gen_d :std_ulogic_vector(0 to 31); +signal ex4_parity_gen_q :std_ulogic_vector(0 to 31); +signal ex4_parity_gen_le_d :std_ulogic_vector(0 to 31); +signal ex4_parity_gen_le_q :std_ulogic_vector(0 to 31); +signal rel_256ld_data_d :std_ulogic_vector(0 to 255); +signal rel_256ld_data_q :std_ulogic_vector(0 to 255); +signal ex3_wrt_data :std_ulogic_vector(0 to 255); +signal ex4_wrt_data_d :std_ulogic_vector(0 to 255); +signal ex4_wrt_data_q :std_ulogic_vector(0 to 255); +signal ex4_wrt_data_le_d :std_ulogic_vector(0 to 255); +signal ex4_wrt_data_le_q :std_ulogic_vector(0 to 255); +signal le_xu_par_gen :std_ulogic_vector(0 to 31); +signal le_pgrotC840 :std_ulogic_vector(0 to 31); +signal le_pgrot3210 :std_ulogic_vector(0 to 31); +signal ex3_par_rot_le :std_ulogic_vector(0 to 31); +signal rel_byte_mask :std_ulogic_vector(0 to 7); +signal rel_dvc_byte_mask_d :std_ulogic_vector((64-(2**regmode))/8 to 7); +signal rel_dvc_byte_mask_q :std_ulogic_vector((64-(2**regmode))/8 to 7); +signal my_spare0_lclk :clk_logic; +signal my_spare0_d1clk :std_ulogic; +signal my_spare0_d2clk :std_ulogic; +signal my_spare_latches_d :std_ulogic_vector(0 to 11); +signal my_spare_latches_q :std_ulogic_vector(0 to 11); + +signal tiup :std_ulogic; +signal siv :std_ulogic_vector(0 to scan_right); +signal sov :std_ulogic_vector(0 to scan_right); + +begin + +tiup <= '1'; + +rel_upd_gpr <= rel_data_rot_sel; + +rel_opsize_d <= ldq_rel_op_size; +rel_algebraic_d <= ldq_rel_algebraic; + +rel_rot_sel <= ldq_rel_rot_sel; +rel_le_mode <= ldq_rel_le_mode; + +op_size <= ex2_opsize; +rot_sel <= ex2_rot_sel; +rot_sel_le <= ex2_rot_sel_le; +rot_addr <= ex2_rot_addr; + +rel_xu_data <= rel_ex3_data; +rel_xu_par_gen <= rel_ex3_par_gen; +reload_algbit <= rel_alg_bit; + +rel_val_data <= ldq_rel_data_val; + +with rel_upd_gpr select + rotate_select <= rot_sel when '0', + rel_rot_sel when others; + +with rel_upd_gpr select + le_mode_select <= '0' when '0', + rel_le_mode when others; + +lvl1_sel <= le_mode_select & rotate_select(0); +lvl2_sel <= rotate_select(1 to 2); +lvl3_sel <= rotate_select(3 to 4); + +with lvl1_sel select + rotate_sel1 <= "1000" when "00", + "0100" when "01", + "0010" when "10", + "0001" when others; + +with lvl2_sel select + rotate_sel2 <= "1000" when "00", + "0100" when "01", + "0010" when "10", + "0001" when others; + +with lvl3_sel select + rotate_sel3 <= "1000" when "00", + "0100" when "01", + "0010" when "10", + "0001" when others; + +rel_xu_le_mode_d <= le_mode_select; + +selGen : for sel in 0 to 15 generate begin + rel_xu_rot_sel1_d(4*sel to (4*sel)+3) <= rotate_sel1; + rel_xu_rot_sel2_d(4*sel to (4*sel)+3) <= rotate_sel2; + rel_xu_rot_sel3_d(4*sel to (4*sel)+3) <= rotate_sel3; +end generate selGen; + +rel_xu_rot_sel1 <= rel_xu_rot_sel1_q; +rel_xu_rot_sel2 <= rel_xu_rot_sel2_q; +rel_xu_rot_sel3 <= rel_xu_rot_sel3_q; +rel_xu_opsize <= rel_opsize_q; +rel_xu_algebraic <= rel_algebraic_q; + +le_lvl2_sel <= rot_sel_le(0 to 1); +le_lvl3_sel <= rot_sel_le(2 to 3); + +with le_lvl2_sel select + le_rotate_sel2 <= "1000" when "00", + "0100" when "01", + "0010" when "10", + "0001" when others; + +with le_lvl3_sel select + le_rotate_sel3 <= "1000" when "00", + "0100" when "01", + "0010" when "10", + "0001" when others; + +leSelGen : for sel in 0 to 15 generate begin + le_xu_rot_sel2_d(4*sel to (4*sel)+3) <= le_rotate_sel2; + le_xu_rot_sel3_d(4*sel to (4*sel)+3) <= le_rotate_sel3; +end generate leSelGen; + +le_xu_rot_sel2 <= le_xu_rot_sel2_q; +le_xu_rot_sel3 <= le_xu_rot_sel3_q; + + +pglvl1rot: for byte in 0 to 31 generate +signal muxIn :std_ulogic_vector(0 to 3); +signal muxSel :std_ulogic_vector(0 to 3); +begin + muxIn <= rel_xu_par_gen(byte) & rel_xu_par_gen((16+byte) mod 32) & + rel_xu_par_gen(31 - byte) & rel_xu_par_gen(31 - ((16+byte) mod 32)); + muxSel <= rel_xu_rot_sel1(4*(byte/16) to (4*(byte/16))+3); + + mux4sel: entity work.xuq_lsu_mux41(xuq_lsu_mux41) + port map ( vdd => vdd, + gnd => gnd, + d0 => muxIn(0), + d1 => muxIn(1), + d2 => muxIn(2), + d3 => muxIn(3), + s0 => muxSel(0), + s1 => muxSel(1), + s2 => muxSel(2), + s3 => muxSel(3), + y => pgrot10(byte)); +end generate pglvl1rot; + +pglvl2rot: for byte in 0 to 31 generate +signal muxIn :std_ulogic_vector(0 to 3); +signal muxSel :std_ulogic_vector(0 to 3); +begin + muxIn <= pgrot10(byte) & pgrot10((4+byte) mod 32) & + pgrot10((8+byte) mod 32) & pgrot10((12+byte) mod 32); + muxSel <= rel_xu_rot_sel2(4*(byte/16) to (4*(byte/16))+3); + + mux4sel: entity work.xuq_lsu_mux41(xuq_lsu_mux41) + port map (vdd => vdd, + gnd => gnd, + d0 => muxIn(0), + d1 => muxIn(1), + d2 => muxIn(2), + d3 => muxIn(3), + s0 => muxSel(0), + s1 => muxSel(1), + s2 => muxSel(2), + s3 => muxSel(3), + y => pgrotC840(byte)); +end generate pglvl2rot; + +pglvl3rot: for byte in 0 to 31 generate +signal muxIn :std_ulogic_vector(0 to 3); +signal muxSel :std_ulogic_vector(0 to 3); +begin + muxIn <= pgrotC840(byte) & pgrotC840((1+byte) mod 32) & + pgrotC840((2+byte) mod 32) & pgrotC840((3+byte) mod 32); + muxSel <= rel_xu_rot_sel3(4*(byte/16) to (4*(byte/16))+3); + + mux4sel: entity work.xuq_lsu_mux41(xuq_lsu_mux41) + port map ( vdd => vdd, + gnd => gnd, + d0 => muxIn(0), + d1 => muxIn(1), + d2 => muxIn(2), + d3 => muxIn(3), + s0 => muxSel(0), + s1 => muxSel(1), + s2 => muxSel(2), + s3 => muxSel(3), + y => pgrot3210(byte)); +end generate pglvl3rot; + +ex3_par_rot <= pgrot3210; + + +ParSwap : for bit in 0 to 31 generate begin + le_xu_par_gen(bit) <= rel_xu_par_gen(31-bit); +end generate ParSwap; + +lePglvl2rot: for byte in 0 to 31 generate +signal muxIn :std_ulogic_vector(0 to 3); +signal muxSel :std_ulogic_vector(0 to 3); +begin + muxIn <= le_xu_par_gen(byte) & le_xu_par_gen((4+byte) mod 32) & + le_xu_par_gen((8+byte) mod 32) & le_xu_par_gen((12+byte) mod 32); + muxSel <= le_xu_rot_sel2(4*(byte/16) to (4*(byte/16))+3); + + mux4sel: entity work.xuq_lsu_mux41(xuq_lsu_mux41) + port map (vdd => vdd, + gnd => gnd, + d0 => muxIn(0), + d1 => muxIn(1), + d2 => muxIn(2), + d3 => muxIn(3), + s0 => muxSel(0), + s1 => muxSel(1), + s2 => muxSel(2), + s3 => muxSel(3), + y => le_pgrotC840(byte)); +end generate lePglvl2rot; + +lePglvl3rot: for byte in 0 to 31 generate +signal muxIn :std_ulogic_vector(0 to 3); +signal muxSel :std_ulogic_vector(0 to 3); +begin + muxIn <= le_pgrotC840(byte) & le_pgrotC840((1+byte) mod 32) & + le_pgrotC840((2+byte) mod 32) & le_pgrotC840((3+byte) mod 32); + muxSel <= le_xu_rot_sel3(4*(byte/16) to (4*(byte/16))+3); + + mux4sel: entity work.xuq_lsu_mux41(xuq_lsu_mux41) + port map ( vdd => vdd, + gnd => gnd, + d0 => muxIn(0), + d1 => muxIn(1), + d2 => muxIn(2), + d3 => muxIn(3), + s0 => muxSel(0), + s1 => muxSel(1), + s2 => muxSel(2), + s3 => muxSel(3), + y => le_pgrot3210(byte)); +end generate lePglvl3rot; + +ex3_par_rot_le <= le_pgrot3210; + + +op_sel(0) <= op_size(1) or op_size(2) or op_size(3) or op_size(4) or op_size(5); +op_sel(1) <= op_size(1) or op_size(2) or op_size(3) or op_size(4); +op_sel(2) <= op_size(1) or op_size(2) or op_size(3); +op_sel(3) <= op_size(1) or op_size(2) or op_size(3); +op_sel(4) <= op_size(1) or op_size(2); +op_sel(5) <= op_size(1) or op_size(2); +op_sel(6) <= op_size(1) or op_size(2); +op_sel(7) <= op_size(1) or op_size(2); +op_sel(8) <= op_size(1); +op_sel(9) <= op_size(1); +op_sel(10) <= op_size(1); +op_sel(11) <= op_size(1); +op_sel(12) <= op_size(1); +op_sel(13) <= op_size(1); +op_sel(14) <= op_size(1); +op_sel(15) <= op_size(1); + +with rot_addr(1) select + be10_en <= op_sel(0 to 15) & x"0000" when '0', + x"0000" & op_sel(0 to 15) when others; + +with rot_addr(2 to 3) select + beC840_en <= be10_en(0 to 31) when "00", + x"0" & be10_en(0 to 27) when "01", + x"00" & be10_en(0 to 23) when "10", + x"000" & be10_en(0 to 19) when others; + +with rot_addr(4 to 5) select + be3210_en <= beC840_en(0 to 31) when "00", + '0' & beC840_en(0 to 30) when "01", + "00" & beC840_en(0 to 29) when "10", + "000" & beC840_en(0 to 28) when others; + +ben_gen : for t in 0 to 31 generate begin + byte_en(t) <= op_size(0) or be3210_en(t); +end generate ben_gen; + +ex3_byte_en_d <= byte_en; + + +l1dcrotl0 : entity work.xuq_lsu_data_rot32_lu(xuq_lsu_data_rot32_lu) +generic map(l_endian_m => l_endian_m) +port map ( + + vdd => vdd, + gnd => gnd, + + rot_sel1 => rel_xu_rot_sel1(0 to 31), + rot_sel2 => rel_xu_rot_sel2(0 to 31), + rot_sel3 => rel_xu_rot_sel3(0 to 31), + rot_sel2_le => le_xu_rot_sel2(0 to 31), + rot_sel3_le => le_xu_rot_sel3(0 to 31), + rot_data => rel_xu_data(0 to 127), + + data256_rot_le => data256_rot_le(0 to 127), + data256_rot => data256_rot(0 to 127) +); + +l1dcrotl1 : entity work.xuq_lsu_data_rot32_lu(xuq_lsu_data_rot32_lu) +generic map(l_endian_m => l_endian_m) +port map ( + + vdd => vdd, + gnd => gnd, + + rot_sel1 => rel_xu_rot_sel1(32 to 63), + rot_sel2 => rel_xu_rot_sel2(32 to 63), + rot_sel3 => rel_xu_rot_sel3(32 to 63), + rot_sel2_le => le_xu_rot_sel2(32 to 63), + rot_sel3_le => le_xu_rot_sel3(32 to 63), + rot_data => rel_xu_data(128 to 255), + + data256_rot_le => data256_rot_le(128 to 255), + data256_rot => data256_rot(128 to 255) +); + + + +with rel_xu_opsize(2 to 5) select + rel_byte_mask <= x"01" when "0001", + x"03" when "0010", + x"0F" when "0100", + x"FF" when others; + +rel_dvc_byte_mask_d <= rel_byte_mask((64-(2**regmode))/8 to 7); + +with rel_xu_opsize select + bittype_mask <= x"00000001" when "000001", + x"00000003" when "000010", + x"0000000F" when "000100", + x"000000FF" when "001000", + x"0000FFFF" when "010000", + x"FFFFFFFF" when others; + +maskGen : for bit in 0 to 7 generate begin + optype_mask(bit*32 to (bit*32)+31) <= bittype_mask; +end generate maskGen; + +rel_msk_data <= data256_rot and optype_mask; + +lh_algebraic <= rel_xu_opsize(4) and rel_xu_algebraic; +lw_algebraic <= rel_xu_opsize(3) and rel_xu_algebraic; +lh_algebraic_msk <= (0 to 47 => reload_algbit); +lw_algebraic_msk <= (0 to 31 => reload_algbit) & x"0000"; +algebraic_msk <= gate(lh_algebraic_msk,lh_algebraic) or gate(lw_algebraic_msk,lw_algebraic); + +rel256data : for t in 0 to 31 generate begin + rel_swzl_data(t*8 to (t*8)+7) <= rel_msk_data(t) & rel_msk_data(t+32) & rel_msk_data(t+64) & rel_msk_data(t+96) & + rel_msk_data(t+128) & rel_msk_data(t+160) & rel_msk_data(t+192) & rel_msk_data(t+224); +end generate rel256data; + +algebraic_msk_data <= rel_swzl_data(0 to 191) & (rel_swzl_data(192 to 239) or algebraic_msk) & rel_swzl_data(240 to 255); +rel_256ld_data_d <= algebraic_msk_data; + + +ex4_wrt_data_le_d <= data256_rot_le; +ex4_parity_gen_le_d <= ex3_par_rot_le; + +ex3_wrt_data <= data256_rot; +ex3_parity_gen <= ex3_par_rot; + +wrtData : for t in 0 to 7 generate begin + ex4_wrt_data_d(t*32 to (t*32)+31) <= gate(rel_xu_data(t*32 to (t*32)+31),rel_val_data(t)) or gate(ex3_wrt_data(t*32 to (t*32)+31),rel_val_data(t+8)); +end generate wrtData; + +wrtPar : for t in 0 to 31 generate begin + ex4_parity_gen_d(t) <= (rel_xu_par_gen(t) and rel_val_data(t mod 8)) or (ex3_parity_gen(t) and rel_val_data((t mod 8)+8)); +end generate wrtPar; + +leSel : for t in 0 to 15 generate begin + ex4_256st_data(t*16 to (t*16)+15) <= gate(ex4_wrt_data_le_q(t*16 to (t*16)+15), ex4_le_mode_sel(t)) or gate(ex4_wrt_data_q(t*16 to (t*16)+15), ex4_be_mode_sel(t)); + ex4_parity_gen(t*2 to (t*2)+1) <= gate(ex4_parity_gen_le_q(t*2 to (t*2)+1), ex4_le_mode_sel(t)) or gate(ex4_parity_gen_q(t*2 to (t*2)+1), ex4_be_mode_sel(t)); +end generate leSel; + +relpar_gen : for t in 0 to 7 generate begin + R0 : if (t < (2**regmode)/8) generate begin + rel_parity_gen(t) <= xor_reduce(rel_256ld_data_q((t*8)+256-(2**regmode) to (t*8)+256-(2**regmode)+7)); + end generate; + R1 : if( t >= (2**regmode)/8) generate begin rel_parity_gen(t) <= '0'; end generate; +end generate relpar_gen; + +my_spare_latches_d <= not my_spare_latches_q; + +ex3_byte_en <= ex3_byte_en_q; +rel_256ld_data <= rel_256ld_data_q; +rel_64ld_data <= rel_256ld_data_q(256-(2**regmode) to 255); +rel_xu_ld_par <= rel_parity_gen; +rel_axu_le_mode <= rel_xu_le_mode_q; +rel_dvc_byte_mask <= rel_dvc_byte_mask_q; + + + +ex3_byte_en_reg: tri_rlmreg_p + generic map (width => 32, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_byte_en_offset to ex3_byte_en_offset + ex3_byte_en_d'length-1), + scout => sov(ex3_byte_en_offset to ex3_byte_en_offset + ex3_byte_en_d'length-1), + din => ex3_byte_en_d, + dout => ex3_byte_en_q); + +rel_opsize_reg: tri_rlmreg_p + generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_opsize_offset to rel_opsize_offset + rel_opsize_d'length-1), + scout => sov(rel_opsize_offset to rel_opsize_offset + rel_opsize_d'length-1), + din => rel_opsize_d, + dout => rel_opsize_q); + +rel_xu_le_mode_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_ex2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_xu_le_mode_offset), + scout => sov(rel_xu_le_mode_offset), + din => rel_xu_le_mode_d, + dout => rel_xu_le_mode_q); + +rel_algebraic_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_algebraic_offset), + scout => sov(rel_algebraic_offset), + din => rel_algebraic_d, + dout => rel_algebraic_q); + +ex4_wrt_data_reg: tri_rlmreg_p + generic map (width => 256, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_ex3_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_wrt_data_offset to ex4_wrt_data_offset + ex4_wrt_data_d'length-1), + scout => sov(ex4_wrt_data_offset to ex4_wrt_data_offset + ex4_wrt_data_d'length-1), + din => ex4_wrt_data_d, + dout => ex4_wrt_data_q); + +ex4_wrt_data_le_reg: tri_rlmreg_p + generic map (width => 256, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_wrt_data_le_offset to ex4_wrt_data_le_offset + ex4_wrt_data_le_d'length-1), + scout => sov(ex4_wrt_data_le_offset to ex4_wrt_data_le_offset + ex4_wrt_data_le_d'length-1), + din => ex4_wrt_data_le_d, + dout => ex4_wrt_data_le_q); + +rel_256ld_data_reg: tri_rlmreg_p + generic map (width => 256, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_256ld_data_offset to rel_256ld_data_offset + rel_256ld_data_d'length-1), + scout => sov(rel_256ld_data_offset to rel_256ld_data_offset + rel_256ld_data_d'length-1), + din => rel_256ld_data_d, + dout => rel_256ld_data_q); + +rel_dvc_byte_mask_reg: tri_rlmreg_p + generic map (width => (2**regmode)/8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_dvc_byte_mask_offset to rel_dvc_byte_mask_offset + rel_dvc_byte_mask_d'length-1), + scout => sov(rel_dvc_byte_mask_offset to rel_dvc_byte_mask_offset + rel_dvc_byte_mask_d'length-1), + din => rel_dvc_byte_mask_d, + dout => rel_dvc_byte_mask_q); + +ex4_parity_gen_reg: tri_rlmreg_p + generic map (width => 32, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_ex3_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_parity_gen_offset to ex4_parity_gen_offset + ex4_parity_gen_d'length-1), + scout => sov(ex4_parity_gen_offset to ex4_parity_gen_offset + ex4_parity_gen_d'length-1), + din => ex4_parity_gen_d, + dout => ex4_parity_gen_q); + +ex4_parity_gen_le_reg: tri_rlmreg_p + generic map (width => 32, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_parity_gen_le_offset to ex4_parity_gen_le_offset + ex4_parity_gen_le_d'length-1), + scout => sov(ex4_parity_gen_le_offset to ex4_parity_gen_le_offset + ex4_parity_gen_le_d'length-1), + din => ex4_parity_gen_le_d, + dout => ex4_parity_gen_le_q); + +my_spare0_lcb : entity tri.tri_lcbnd(tri_lcbnd) +generic map (expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + d1clk => my_spare0_d1clk, + d2clk => my_spare0_d2clk, + lclk => my_spare0_lclk); +my_spare_latches_reg: entity tri.tri_inv_nlats(tri_inv_nlats) +generic map (width => 12, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + lclk => my_spare0_lclk, + d1clk => my_spare0_d1clk, + d2clk => my_spare0_d2clk, + scanin => siv(my_spare_latches_offset to my_spare_latches_offset + my_spare_latches_d'length-1), + scanout => sov(my_spare_latches_offset to my_spare_latches_offset + my_spare_latches_d'length-1), + d => my_spare_latches_d, + qb => my_spare_latches_q); + + +rel_xu_rot_sel1_0reg: tri_regk + generic map (width => 32, init => 286331153, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_ex2_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_xu_rot_sel1_d(0 to 31), + dout => rel_xu_rot_sel1_q(0 to 31)); + +rel_xu_rot_sel1_1reg: tri_regk + generic map (width => 32, init => 286331153, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_ex2_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_xu_rot_sel1_d(32 to 63), + dout => rel_xu_rot_sel1_q(32 to 63)); + +rel_xu_rot_sel2_0reg: tri_regk + generic map (width => 32, init => 286331153, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_ex2_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_xu_rot_sel2_d(0 to 31), + dout => rel_xu_rot_sel2_q(0 to 31)); + +rel_xu_rot_sel2_1reg: tri_regk + generic map (width => 32, init => 286331153, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_ex2_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_xu_rot_sel2_d(32 to 63), + dout => rel_xu_rot_sel2_q(32 to 63)); + +rel_xu_rot_sel3_0reg: tri_regk + generic map (width => 32, init => 286331153, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_ex2_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_xu_rot_sel3_d(0 to 31), + dout => rel_xu_rot_sel3_q(0 to 31)); + +rel_xu_rot_sel3_1reg: tri_regk + generic map (width => 32, init => 286331153, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_ex2_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_xu_rot_sel3_d(32 to 63), + dout => rel_xu_rot_sel3_q(32 to 63)); + +le_xu_rot_sel2_0reg: tri_regk + generic map (width => 32, init => 286331153, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => le_xu_rot_sel2_d(0 to 31), + dout => le_xu_rot_sel2_q(0 to 31)); + +le_xu_rot_sel2_1reg: tri_regk + generic map (width => 32, init => 286331153, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => le_xu_rot_sel2_d(32 to 63), + dout => le_xu_rot_sel2_q(32 to 63)); + +le_xu_rot_sel3_0reg: tri_regk + generic map (width => 32, init => 286331153, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => le_xu_rot_sel3_d(0 to 31), + dout => le_xu_rot_sel3_q(0 to 31)); + +le_xu_rot_sel3_1reg: tri_regk + generic map (width => 32, init => 286331153, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => le_xu_rot_sel3_d(32 to 63), + dout => le_xu_rot_sel3_q(32 to 63)); + +siv(0 to scan_right) <= sov(1 to scan_right) & scan_in; +scan_out <= sov(0); + +end xuq_lsu_data_st; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_dc.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_dc.vhdl new file mode 100644 index 0000000..429f983 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_dc.vhdl @@ -0,0 +1,956 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ibm, ieee, work, tri, support; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use tri.tri_latches_pkg.all; +use support.power_logic_pkg.all; + + +entity xuq_lsu_dc is +generic(expand_type : integer := 2; + l_endian_m : integer := 1; + regmode : integer := 6; + dc_size : natural := 14; + parBits : natural := 4; + real_data_add : integer := 42); +port( + + xu_lsu_rf0_act :in std_ulogic; + xu_lsu_rf1_cmd_act :in std_ulogic; + xu_lsu_rf1_axu_op_val :in std_ulogic; + xu_lsu_rf1_axu_ldst_falign :in std_ulogic; + xu_lsu_rf1_axu_ldst_fexcpt :in std_ulogic; + xu_lsu_rf1_cache_acc :in std_ulogic; + xu_lsu_rf1_thrd_id :in std_ulogic_vector(0 to 3); + xu_lsu_rf1_optype1 :in std_ulogic; + xu_lsu_rf1_optype2 :in std_ulogic; + xu_lsu_rf1_optype4 :in std_ulogic; + xu_lsu_rf1_optype8 :in std_ulogic; + xu_lsu_rf1_optype16 :in std_ulogic; + xu_lsu_rf1_optype32 :in std_ulogic; + xu_lsu_rf1_target_gpr :in std_ulogic_vector(0 to 8); + xu_lsu_rf1_mtspr_trace :in std_ulogic; + xu_lsu_rf1_load_instr :in std_ulogic; + xu_lsu_rf1_store_instr :in std_ulogic; + xu_lsu_rf1_dcbf_instr :in std_ulogic; + xu_lsu_rf1_sync_instr :in std_ulogic; + xu_lsu_rf1_l_fld :in std_ulogic_vector(0 to 1); + xu_lsu_rf1_dcbi_instr :in std_ulogic; + xu_lsu_rf1_dcbz_instr :in std_ulogic; + xu_lsu_rf1_dcbt_instr :in std_ulogic; + xu_lsu_rf1_dcbtst_instr :in std_ulogic; + xu_lsu_rf1_th_fld :in std_ulogic_vector(0 to 4); + xu_lsu_rf1_dcbtls_instr :in std_ulogic; + xu_lsu_rf1_dcbtstls_instr :in std_ulogic; + xu_lsu_rf1_dcblc_instr :in std_ulogic; + xu_lsu_rf1_dcbst_instr :in std_ulogic; + xu_lsu_rf1_icbi_instr :in std_ulogic; + xu_lsu_rf1_icblc_instr :in std_ulogic; + xu_lsu_rf1_icbt_instr :in std_ulogic; + xu_lsu_rf1_icbtls_instr :in std_ulogic; + xu_lsu_rf1_icswx_instr :in std_ulogic; + xu_lsu_rf1_icswx_dot_instr :in std_ulogic; + xu_lsu_rf1_icswx_epid :in std_ulogic; + xu_lsu_rf1_tlbsync_instr :in std_ulogic; + xu_lsu_rf1_ldawx_instr :in std_ulogic; + xu_lsu_rf1_wclr_instr :in std_ulogic; + xu_lsu_rf1_wchk_instr :in std_ulogic; + xu_lsu_rf1_lock_instr :in std_ulogic; + xu_lsu_rf1_mutex_hint :in std_ulogic; + xu_lsu_rf1_mbar_instr :in std_ulogic; + xu_lsu_rf1_is_msgsnd :in std_ulogic; + xu_lsu_rf1_dci_instr :in std_ulogic; + xu_lsu_rf1_ici_instr :in std_ulogic; + xu_lsu_rf1_algebraic :in std_ulogic; + xu_lsu_rf1_byte_rev :in std_ulogic; + xu_lsu_rf1_src_gpr :in std_ulogic; + xu_lsu_rf1_src_axu :in std_ulogic; + xu_lsu_rf1_src_dp :in std_ulogic; + xu_lsu_rf1_targ_gpr :in std_ulogic; + xu_lsu_rf1_targ_axu :in std_ulogic; + xu_lsu_rf1_targ_dp :in std_ulogic; + xu_lsu_ex4_val :in std_ulogic_vector(0 to 3); + + xu_lsu_rf1_src0_vld :in std_ulogic; + xu_lsu_rf1_src0_reg :in std_ulogic_vector(0 to 7); + xu_lsu_rf1_src1_vld :in std_ulogic; + xu_lsu_rf1_src1_reg :in std_ulogic_vector(0 to 7); + xu_lsu_rf1_targ_vld :in std_ulogic; + xu_lsu_rf1_targ_reg :in std_ulogic_vector(0 to 7); + + ex2_p_addr_lwr :in std_ulogic_vector(52 to 63); + ex2_lm_dep_hit :in std_ulogic; + + ex3_wimge_w_bit :in std_ulogic; + ex3_wimge_i_bit :in std_ulogic; + ex3_wimge_e_bit :in std_ulogic; + ex3_p_addr :in std_ulogic_vector(64-real_data_add to 51); + ex3_ld_queue_full :in std_ulogic; + ex3_stq_flush :in std_ulogic; + ex3_ig_flush :in std_ulogic; + ex3_hit :in std_ulogic; + ex4_miss :in std_ulogic; + ex4_snd_ld_l2 :in std_ulogic; + derat_xu_ex3_noop_touch :in std_ulogic_vector(0 to 3); + ex3_cClass_collision :in std_ulogic; + ex2_lockwatchSet_rel_coll :in std_ulogic; + ex3_wclr_all_flush :in std_ulogic; + rel_dcarr_val_upd :in std_ulogic; + + xu_lsu_mtspr_trace_en :in std_ulogic_vector(0 to 3); + spr_xucr0_clkg_ctl_b1 :in std_ulogic; + xu_lsu_spr_xucr0_aflsta :in std_ulogic; + xu_lsu_spr_xucr0_flsta :in std_ulogic; + xu_lsu_spr_xucr0_l2siw :in std_ulogic; + xu_lsu_spr_xucr0_dcdis :in std_ulogic; + xu_lsu_spr_xucr0_wlk :in std_ulogic; + xu_lsu_spr_ccr2_dfrat :in std_ulogic; + xu_lsu_spr_xucr0_flh2l2 :in std_ulogic; + xu_lsu_spr_xucr0_cls :in std_ulogic; + xu_lsu_spr_msr_cm :in std_ulogic_vector(0 to 3); + + xu_lsu_msr_gs :in std_ulogic_vector(0 to 3); + xu_lsu_msr_pr :in std_ulogic_vector(0 to 3); + + an_ac_flh2l2_gate :in std_ulogic; + + xu_lsu_rf1_flush :in std_ulogic_vector(0 to 3); + xu_lsu_ex1_flush :in std_ulogic_vector(0 to 3); + xu_lsu_ex2_flush :in std_ulogic_vector(0 to 3); + xu_lsu_ex3_flush :in std_ulogic_vector(0 to 3); + xu_lsu_ex4_flush :in std_ulogic_vector(0 to 3); + xu_lsu_ex5_flush :in std_ulogic_vector(0 to 3); + + xu_lsu_slowspr_val :in std_ulogic; + xu_lsu_slowspr_rw :in std_ulogic; + xu_lsu_slowspr_etid :in std_ulogic_vector(0 to 1); + xu_lsu_slowspr_addr :in std_ulogic_vector(0 to 9); + xu_lsu_slowspr_data :in std_ulogic_vector(64-(2**REGMODE) to 63); + xu_lsu_slowspr_done :in std_ulogic; + slowspr_val_out :out std_ulogic; + slowspr_rw_out :out std_ulogic; + slowspr_etid_out :out std_ulogic_vector(0 to 1); + slowspr_addr_out :out std_ulogic_vector(0 to 9); + slowspr_data_out :out std_ulogic_vector(64-(2**REGMODE) to 63); + slowspr_done_out :out std_ulogic; + + ldq_rel_data_val_early :in std_ulogic; + ldq_rel_stg24_val :in std_ulogic; + ldq_rel_axu_val :in std_ulogic; + ldq_rel_thrd_id :in std_ulogic_vector(0 to 3); + ldq_rel_ta_gpr :in std_ulogic_vector(0 to 8); + ldq_rel_upd_gpr :in std_ulogic; + ldq_rel_ci :in std_ulogic; + is2_l2_inv_val :in std_ulogic; + + ex3_wayA_tag :in std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex3_wayB_tag :in std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex3_wayC_tag :in std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex3_wayD_tag :in std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex3_wayE_tag :in std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex3_wayF_tag :in std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex3_wayG_tag :in std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex3_wayH_tag :in std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex3_way_tag_par_a :in std_ulogic_vector(0 to parBits-1); + ex3_way_tag_par_b :in std_ulogic_vector(0 to parBits-1); + ex3_way_tag_par_c :in std_ulogic_vector(0 to parBits-1); + ex3_way_tag_par_d :in std_ulogic_vector(0 to parBits-1); + ex3_way_tag_par_e :in std_ulogic_vector(0 to parBits-1); + ex3_way_tag_par_f :in std_ulogic_vector(0 to parBits-1); + ex3_way_tag_par_g :in std_ulogic_vector(0 to parBits-1); + ex3_way_tag_par_h :in std_ulogic_vector(0 to parBits-1); + ex4_way_a_dir :in std_ulogic_vector(0 to 5); + ex4_way_b_dir :in std_ulogic_vector(0 to 5); + ex4_way_c_dir :in std_ulogic_vector(0 to 5); + ex4_way_d_dir :in std_ulogic_vector(0 to 5); + ex4_way_e_dir :in std_ulogic_vector(0 to 5); + ex4_way_f_dir :in std_ulogic_vector(0 to 5); + ex4_way_g_dir :in std_ulogic_vector(0 to 5); + ex4_way_h_dir :in std_ulogic_vector(0 to 5); + ex4_dir_lru :in std_ulogic_vector(0 to 6); + + ex1_src0_vld :out std_ulogic; + ex1_src0_reg :out std_ulogic_vector(0 to 7); + ex1_src1_vld :out std_ulogic; + ex1_src1_reg :out std_ulogic_vector(0 to 7); + ex1_targ_vld :out std_ulogic; + ex1_targ_reg :out std_ulogic_vector(0 to 7); + ex1_check_watch :out std_ulogic_vector(0 to 3); + + ex1_lsu_64bit_agen :out std_ulogic; + ex1_frc_align2 :out std_ulogic; + ex1_frc_align4 :out std_ulogic; + ex1_frc_align8 :out std_ulogic; + ex1_frc_align16 :out std_ulogic; + ex1_frc_align32 :out std_ulogic; + ex1_dir_acc_val :out std_ulogic; + ex3_cache_acc :out std_ulogic; + ex1_optype1 :out std_ulogic; + ex1_optype2 :out std_ulogic; + ex1_optype4 :out std_ulogic; + ex1_optype8 :out std_ulogic; + ex1_optype16 :out std_ulogic; + ex1_optype32 :out std_ulogic; + ex1_saxu_instr :out std_ulogic; + ex1_sdp_instr :out std_ulogic; + ex1_stgpr_instr :out std_ulogic; + ex1_store_instr :out std_ulogic; + ex1_axu_op_val :out std_ulogic; + ex2_no_lru_upd :out std_ulogic; + ex2_is_inval_op :out std_ulogic; + ex2_lock_set :out std_ulogic; + ex2_lock_clr :out std_ulogic; + ex2_ddir_acc_instr :out std_ulogic; + + ex3_p_addr_lwr :out std_ulogic_vector(58 to 63); + ex3_req_thrd_id :out std_ulogic_vector(0 to 3); + ex3_target_gpr :out std_ulogic_vector(0 to 8); + ex3_dcbt_instr :out std_ulogic; + ex3_dcbtst_instr :out std_ulogic; + ex3_th_fld_l2 :out std_ulogic; + ex3_dcbst_instr :out std_ulogic; + ex3_dcbf_instr :out std_ulogic; + ex3_sync_instr :out std_ulogic; + ex3_mtspr_trace :out std_ulogic; + ex3_byte_en :out std_ulogic_vector(0 to 31); + ex2_l_fld :out std_ulogic_vector(0 to 1); + ex3_l_fld :out std_ulogic_vector(0 to 1); + ex3_dcbi_instr :out std_ulogic; + ex3_dcbz_instr :out std_ulogic; + ex3_icbi_instr :out std_ulogic; + ex3_icswx_instr :out std_ulogic; + ex3_icswx_dot :out std_ulogic; + ex3_icswx_epid :out std_ulogic; + ex3_mbar_instr :out std_ulogic; + ex3_msgsnd_instr :out std_ulogic; + ex3_dci_instr :out std_ulogic; + ex3_ici_instr :out std_ulogic; + ex3_load_instr :out std_ulogic; + ex2_store_instr :out std_ulogic; + ex3_store_instr :out std_ulogic; + ex3_axu_op_val :out std_ulogic; + ex3_algebraic :out std_ulogic; + ex3_dcbtls_instr :out std_ulogic; + ex3_dcbtstls_instr :out std_ulogic; + ex3_dcblc_instr :out std_ulogic; + ex3_icblc_instr :out std_ulogic; + ex3_icbt_instr :out std_ulogic; + ex3_icbtls_instr :out std_ulogic; + ex3_tlbsync_instr :out std_ulogic; + ex3_local_dcbf :out std_ulogic; + ex4_drop_rel :out std_ulogic; + ex3_load_l1hit :out std_ulogic; + ex3_rotate_sel :out std_ulogic_vector(0 to 4); + ex1_thrd_id :out std_ulogic_vector(0 to 3); + ex2_ldawx_instr :out std_ulogic; + ex2_wclr_instr :out std_ulogic; + ex2_wchk_val :out std_ulogic; + ex3_watch_en :out std_ulogic; + ex3_data_swap :out std_ulogic; + ex3_load_val :out std_ulogic; + ex3_blkable_touch :out std_ulogic; + ex3_l2_request :out std_ulogic; + ex3_ldq_potential_flush :out std_ulogic; + ex7_targ_match :out std_ulogic; + ex8_targ_match :out std_ulogic; + ex4_ld_entry :out std_ulogic_vector(0 to 67); + + ex3_lock_en :out std_ulogic; + ex3_cache_en :out std_ulogic; + ex3_cache_inh :out std_ulogic; + ex3_l_s_q_val :out std_ulogic; + ex3_drop_ld_req :out std_ulogic; + ex3_drop_touch :out std_ulogic; + ex3_stx_instr :out std_ulogic; + ex3_larx_instr :out std_ulogic; + ex3_mutex_hint :out std_ulogic; + ex3_opsize :out std_ulogic_vector(0 to 5); + ex4_store_hit :out std_ulogic; + ex4_load_op_hit :out std_ulogic; + ex5_load_op_hit :out std_ulogic; + ex4_axu_op_val :out std_ulogic; + + spr_xucr2_rmt :out std_ulogic_vector(0 to 31); + spr_xucr0_wlck :out std_ulogic; + spr_dvc1_act :out std_ulogic; + spr_dvc2_act :out std_ulogic; + spr_dvc1_dbg :out std_ulogic_vector(64-(2**regmode) to 63); + spr_dvc2_dbg :out std_ulogic_vector(64-(2**regmode) to 63); + + lsu_xu_spr_xucr0_cul :out std_ulogic; + spr_xucr0_cls :out std_ulogic; + agen_xucr0_cls :out std_ulogic; + + dir_arr_rd_is2_val :out std_ulogic; + dir_arr_rd_congr_cl :out std_ulogic_vector(0 to 4); + + lsu_xu_ex3_align :out std_ulogic_vector(0 to 3); + lsu_xu_ex3_dsi :out std_ulogic_vector(0 to 3); + lsu_xu_ex3_inval_align_2ucode :out std_ulogic; + + ex2_stg_flush :out std_ulogic; + ex3_stg_flush :out std_ulogic; + ex4_stg_flush :out std_ulogic; + ex5_stg_flush :out std_ulogic; + lsu_xu_ex3_n_flush_req :out std_ulogic; + lsu_xu_ex3_dep_flush :out std_ulogic; + + rf1_l2_inv_val :out std_ulogic; + ex1_agen_binv_val :out std_ulogic; + ex1_l2_inv_val :out std_ulogic; + + rel_upd_dcarr_val :out std_ulogic; + + lsu_xu_ex4_cr_upd :out std_ulogic; + lsu_xu_ex5_wren :out std_ulogic; + lsu_xu_rel_wren :out std_ulogic; + lsu_xu_rel_ta_gpr :out std_ulogic_vector(0 to 7); + + lsu_xu_perf_events :out std_ulogic_vector(0 to 20); + lsu_xu_need_hole :out std_ulogic; + + xu_fu_ex5_reload_val :out std_ulogic; + xu_fu_ex5_load_val :out std_ulogic_vector(0 to 3); + xu_fu_ex5_load_tag :out std_ulogic_vector(0 to 8); + + xu_iu_ex6_icbi_val :out std_ulogic_vector(0 to 3); + xu_iu_ex6_icbi_addr :out std_ulogic_vector(64-real_data_add to 57); + + xu_derat_epsc_wr :out std_ulogic_vector(0 to 3); + xu_derat_eplc_wr :out std_ulogic_vector(0 to 3); + xu_derat_eplc0_epr :out std_ulogic; + xu_derat_eplc0_eas :out std_ulogic; + xu_derat_eplc0_egs :out std_ulogic; + xu_derat_eplc0_elpid :out std_ulogic_vector(40 to 47); + xu_derat_eplc0_epid :out std_ulogic_vector(50 to 63); + xu_derat_eplc1_epr :out std_ulogic; + xu_derat_eplc1_eas :out std_ulogic; + xu_derat_eplc1_egs :out std_ulogic; + xu_derat_eplc1_elpid :out std_ulogic_vector(40 to 47); + xu_derat_eplc1_epid :out std_ulogic_vector(50 to 63); + xu_derat_eplc2_epr :out std_ulogic; + xu_derat_eplc2_eas :out std_ulogic; + xu_derat_eplc2_egs :out std_ulogic; + xu_derat_eplc2_elpid :out std_ulogic_vector(40 to 47); + xu_derat_eplc2_epid :out std_ulogic_vector(50 to 63); + xu_derat_eplc3_epr :out std_ulogic; + xu_derat_eplc3_eas :out std_ulogic; + xu_derat_eplc3_egs :out std_ulogic; + xu_derat_eplc3_elpid :out std_ulogic_vector(40 to 47); + xu_derat_eplc3_epid :out std_ulogic_vector(50 to 63); + xu_derat_epsc0_epr :out std_ulogic; + xu_derat_epsc0_eas :out std_ulogic; + xu_derat_epsc0_egs :out std_ulogic; + xu_derat_epsc0_elpid :out std_ulogic_vector(40 to 47); + xu_derat_epsc0_epid :out std_ulogic_vector(50 to 63); + xu_derat_epsc1_epr :out std_ulogic; + xu_derat_epsc1_eas :out std_ulogic; + xu_derat_epsc1_egs :out std_ulogic; + xu_derat_epsc1_elpid :out std_ulogic_vector(40 to 47); + xu_derat_epsc1_epid :out std_ulogic_vector(50 to 63); + xu_derat_epsc2_epr :out std_ulogic; + xu_derat_epsc2_eas :out std_ulogic; + xu_derat_epsc2_egs :out std_ulogic; + xu_derat_epsc2_elpid :out std_ulogic_vector(40 to 47); + xu_derat_epsc2_epid :out std_ulogic_vector(50 to 63); + xu_derat_epsc3_epr :out std_ulogic; + xu_derat_epsc3_eas :out std_ulogic; + xu_derat_epsc3_egs :out std_ulogic; + xu_derat_epsc3_elpid :out std_ulogic_vector(40 to 47); + xu_derat_epsc3_epid :out std_ulogic_vector(50 to 63); + + dc_fgen_dbg_data :out std_ulogic_vector(0 to 1); + dc_cntrl_dbg_data :out std_ulogic_vector(0 to 66); + + ex1_stg_act :out std_ulogic; + ex2_stg_act :out std_ulogic; + ex3_stg_act :out std_ulogic; + ex4_stg_act :out std_ulogic; + ex5_stg_act :out std_ulogic; + binv1_stg_act :out std_ulogic; + binv2_stg_act :out std_ulogic; + binv3_stg_act :out std_ulogic; + binv4_stg_act :out std_ulogic; + binv5_stg_act :out std_ulogic; + rel1_stg_act :out std_ulogic; + rel2_stg_act :out std_ulogic; + rel3_stg_act :out std_ulogic; + + vdd :inout power_logic; + gnd :inout power_logic; + nclk :in clk_logic; + sg_0 :in std_ulogic; + func_sl_thold_0_b :in std_ulogic; + func_sl_force :in std_ulogic; + func_slp_sl_thold_0_b :in std_ulogic; + func_slp_sl_force :in std_ulogic; + func_nsl_thold_0_b :in std_ulogic; + func_nsl_force :in std_ulogic; + func_slp_nsl_thold_0_b :in std_ulogic; + func_slp_nsl_force :in std_ulogic; + d_mode_dc :in std_ulogic; + delay_lclkr_dc :in std_ulogic; + mpw1_dc_b :in std_ulogic; + mpw2_dc_b :in std_ulogic; + scan_in :in std_ulogic; + scan_out :out std_ulogic +); +-- synopsys translate_off +-- synopsys translate_on +end xuq_lsu_dc; +architecture xuq_lsu_dc of xuq_lsu_dc is + + +constant dccntrl_offset :natural := 0; +constant dcfgen_offset :natural := dccntrl_offset + 1; +constant scan_right :natural := dcfgen_offset + 1 - 1; + +signal stg_flush_rf1 :std_ulogic; +signal stg_flush_ex1 :std_ulogic; +signal stg_flush_ex2 :std_ulogic; +signal stg_flush_ex3 :std_ulogic; +signal stg_flush_ex4 :std_ulogic; +signal stg_flush_ex5 :std_ulogic; +signal ex1_thrd_id_int :std_ulogic_vector(0 to 3); +signal ex2_thrd_id :std_ulogic_vector(0 to 3); +signal ex3_thrd_id :std_ulogic_vector(0 to 3); +signal ex4_thrd_id :std_ulogic_vector(0 to 3); +signal ex5_thrd_id :std_ulogic_vector(0 to 3); +signal ex2_cache_acc :std_ulogic; +signal ex2_icswx_type :std_ulogic; +signal ex2_store_instr_int :std_ulogic; +signal ex2_load_instr :std_ulogic; +signal ex2_dcbz_instr :std_ulogic; +signal ex2_lock_instr :std_ulogic; +signal ex2_ldawx_instr_int :std_ulogic; +signal ex3_targ_match_b1 :std_ulogic; +signal ex2_targ_match_b2 :std_ulogic; +signal ex2_mv_reg_op :std_ulogic; +signal ex2_axu_op :std_ulogic; +signal ex3_excp_det :std_ulogic; +signal ex2_optype2 :std_ulogic; +signal ex2_optype4 :std_ulogic; +signal ex2_optype8 :std_ulogic; +signal ex2_optype16 :std_ulogic; +signal ex2_optype32 :std_ulogic; +signal ex2_ldst_fexcpt :std_ulogic; +signal ex3_lsq_flush :std_ulogic; + +signal siv :std_ulogic_vector(0 to scan_right); +signal sov :std_ulogic_vector(0 to scan_right); + +begin + + +l1dccntrl : entity work.xuq_lsu_dc_cntrl(xuq_lsu_dc_cntrl) +generic map(expand_type => expand_type, + regmode => regmode, + dc_size => dc_size, + parBits => parBits, + real_data_add => real_data_add) +port map( + + xu_lsu_rf0_act => xu_lsu_rf0_act, + xu_lsu_rf1_cmd_act => xu_lsu_rf1_cmd_act, + xu_lsu_rf1_axu_op_val => xu_lsu_rf1_axu_op_val, + xu_lsu_rf1_axu_ldst_falign => xu_lsu_rf1_axu_ldst_falign, + xu_lsu_rf1_axu_ldst_fexcpt => xu_lsu_rf1_axu_ldst_fexcpt, + xu_lsu_rf1_cache_acc => xu_lsu_rf1_cache_acc, + xu_lsu_rf1_thrd_id => xu_lsu_rf1_thrd_id, + xu_lsu_rf1_optype1 => xu_lsu_rf1_optype1, + xu_lsu_rf1_optype2 => xu_lsu_rf1_optype2, + xu_lsu_rf1_optype4 => xu_lsu_rf1_optype4, + xu_lsu_rf1_optype8 => xu_lsu_rf1_optype8, + xu_lsu_rf1_optype16 => xu_lsu_rf1_optype16, + xu_lsu_rf1_optype32 => xu_lsu_rf1_optype32, + xu_lsu_rf1_target_gpr => xu_lsu_rf1_target_gpr, + xu_lsu_rf1_mtspr_trace => xu_lsu_rf1_mtspr_trace, + xu_lsu_rf1_load_instr => xu_lsu_rf1_load_instr, + xu_lsu_rf1_store_instr => xu_lsu_rf1_store_instr, + xu_lsu_rf1_dcbf_instr => xu_lsu_rf1_dcbf_instr, + xu_lsu_rf1_sync_instr => xu_lsu_rf1_sync_instr, + xu_lsu_rf1_l_fld => xu_lsu_rf1_l_fld, + xu_lsu_rf1_dcbi_instr => xu_lsu_rf1_dcbi_instr, + xu_lsu_rf1_dcbz_instr => xu_lsu_rf1_dcbz_instr, + xu_lsu_rf1_dcbt_instr => xu_lsu_rf1_dcbt_instr, + xu_lsu_rf1_dcbtst_instr => xu_lsu_rf1_dcbtst_instr, + xu_lsu_rf1_th_fld => xu_lsu_rf1_th_fld, + xu_lsu_rf1_dcbtls_instr => xu_lsu_rf1_dcbtls_instr, + xu_lsu_rf1_dcbtstls_instr => xu_lsu_rf1_dcbtstls_instr, + xu_lsu_rf1_dcblc_instr => xu_lsu_rf1_dcblc_instr, + xu_lsu_rf1_dcbst_instr => xu_lsu_rf1_dcbst_instr, + xu_lsu_rf1_icbi_instr => xu_lsu_rf1_icbi_instr, + xu_lsu_rf1_icblc_instr => xu_lsu_rf1_icblc_instr, + xu_lsu_rf1_icbt_instr => xu_lsu_rf1_icbt_instr, + xu_lsu_rf1_icbtls_instr => xu_lsu_rf1_icbtls_instr, + xu_lsu_rf1_icswx_instr => xu_lsu_rf1_icswx_instr, + xu_lsu_rf1_icswx_dot_instr => xu_lsu_rf1_icswx_dot_instr, + xu_lsu_rf1_icswx_epid => xu_lsu_rf1_icswx_epid, + xu_lsu_rf1_tlbsync_instr => xu_lsu_rf1_tlbsync_instr, + xu_lsu_rf1_ldawx_instr => xu_lsu_rf1_ldawx_instr, + xu_lsu_rf1_wclr_instr => xu_lsu_rf1_wclr_instr, + xu_lsu_rf1_wchk_instr => xu_lsu_rf1_wchk_instr, + xu_lsu_rf1_lock_instr => xu_lsu_rf1_lock_instr, + xu_lsu_rf1_mutex_hint => xu_lsu_rf1_mutex_hint, + xu_lsu_rf1_mbar_instr => xu_lsu_rf1_mbar_instr, + xu_lsu_rf1_is_msgsnd => xu_lsu_rf1_is_msgsnd, + xu_lsu_rf1_dci_instr => xu_lsu_rf1_dci_instr, + xu_lsu_rf1_ici_instr => xu_lsu_rf1_ici_instr, + xu_lsu_rf1_algebraic => xu_lsu_rf1_algebraic, + xu_lsu_rf1_byte_rev => xu_lsu_rf1_byte_rev, + xu_lsu_rf1_src_gpr => xu_lsu_rf1_src_gpr, + xu_lsu_rf1_src_axu => xu_lsu_rf1_src_axu, + xu_lsu_rf1_src_dp => xu_lsu_rf1_src_dp, + xu_lsu_rf1_targ_gpr => xu_lsu_rf1_targ_gpr, + xu_lsu_rf1_targ_axu => xu_lsu_rf1_targ_axu, + xu_lsu_rf1_targ_dp => xu_lsu_rf1_targ_dp, + xu_lsu_ex4_val => xu_lsu_ex4_val, + + xu_lsu_rf1_src0_vld => xu_lsu_rf1_src0_vld, + xu_lsu_rf1_src0_reg => xu_lsu_rf1_src0_reg, + xu_lsu_rf1_src1_vld => xu_lsu_rf1_src1_vld, + xu_lsu_rf1_src1_reg => xu_lsu_rf1_src1_reg, + xu_lsu_rf1_targ_vld => xu_lsu_rf1_targ_vld, + xu_lsu_rf1_targ_reg => xu_lsu_rf1_targ_reg, + + is2_l2_inv_val => is2_l2_inv_val, + + ex3_wayA_tag => ex3_wayA_tag, + ex3_wayB_tag => ex3_wayB_tag, + ex3_wayC_tag => ex3_wayC_tag, + ex3_wayD_tag => ex3_wayD_tag, + ex3_wayE_tag => ex3_wayE_tag, + ex3_wayF_tag => ex3_wayF_tag, + ex3_wayG_tag => ex3_wayG_tag, + ex3_wayH_tag => ex3_wayH_tag, + ex3_way_tag_par_a => ex3_way_tag_par_a, + ex3_way_tag_par_b => ex3_way_tag_par_b, + ex3_way_tag_par_c => ex3_way_tag_par_c, + ex3_way_tag_par_d => ex3_way_tag_par_d, + ex3_way_tag_par_e => ex3_way_tag_par_e, + ex3_way_tag_par_f => ex3_way_tag_par_f, + ex3_way_tag_par_g => ex3_way_tag_par_g, + ex3_way_tag_par_h => ex3_way_tag_par_h, + ex4_way_a_dir => ex4_way_a_dir, + ex4_way_b_dir => ex4_way_b_dir, + ex4_way_c_dir => ex4_way_c_dir, + ex4_way_d_dir => ex4_way_d_dir, + ex4_way_e_dir => ex4_way_e_dir, + ex4_way_f_dir => ex4_way_f_dir, + ex4_way_g_dir => ex4_way_g_dir, + ex4_way_h_dir => ex4_way_h_dir, + ex4_dir_lru => ex4_dir_lru, + + ex2_p_addr_lwr => ex2_p_addr_lwr, + ex3_wimge_i_bit => ex3_wimge_i_bit, + ex3_wimge_e_bit => ex3_wimge_e_bit, + + ex3_p_addr => ex3_p_addr, + ex3_ld_queue_full => ex3_ld_queue_full, + ex3_stq_flush => ex3_stq_flush, + ex3_ig_flush => ex3_ig_flush, + ex3_hit => ex3_hit, + ex4_miss => ex4_miss, + ex4_snd_ld_l2 => ex4_snd_ld_l2, + ex3_excp_det => ex3_excp_det, + + rf1_stg_flush => stg_flush_rf1, + ex1_stg_flush => stg_flush_ex1, + ex2_stg_flush => stg_flush_ex2, + ex3_stg_flush => stg_flush_ex3, + ex4_stg_flush => stg_flush_ex4, + ex5_stg_flush => stg_flush_ex5, + + xu_lsu_mtspr_trace_en => xu_lsu_mtspr_trace_en, + spr_xucr0_clkg_ctl_b1 => spr_xucr0_clkg_ctl_b1, + xu_lsu_spr_xucr0_wlk => xu_lsu_spr_xucr0_wlk, + xu_lsu_spr_ccr2_dfrat => xu_lsu_spr_ccr2_dfrat, + xu_lsu_spr_xucr0_dcdis => xu_lsu_spr_xucr0_dcdis, + xu_lsu_spr_xucr0_flh2l2 => xu_lsu_spr_xucr0_flh2l2, + xu_lsu_spr_xucr0_cls => xu_lsu_spr_xucr0_cls, + xu_lsu_spr_msr_cm => xu_lsu_spr_msr_cm, + + xu_lsu_msr_gs => xu_lsu_msr_gs, + xu_lsu_msr_pr => xu_lsu_msr_pr, + + an_ac_flh2l2_gate => an_ac_flh2l2_gate, + + xu_lsu_slowspr_val => xu_lsu_slowspr_val, + xu_lsu_slowspr_rw => xu_lsu_slowspr_rw, + xu_lsu_slowspr_etid => xu_lsu_slowspr_etid, + xu_lsu_slowspr_addr => xu_lsu_slowspr_addr, + xu_lsu_slowspr_data => xu_lsu_slowspr_data, + xu_lsu_slowspr_done => xu_lsu_slowspr_done, + slowspr_val_out => slowspr_val_out, + slowspr_rw_out => slowspr_rw_out, + slowspr_etid_out => slowspr_etid_out, + slowspr_addr_out => slowspr_addr_out, + slowspr_data_out => slowspr_data_out, + slowspr_done_out => slowspr_done_out, + + ldq_rel_data_val_early => ldq_rel_data_val_early, + ldq_rel_stg24_val => ldq_rel_stg24_val, + ldq_rel_axu_val => ldq_rel_axu_val, + ldq_rel_thrd_id => ldq_rel_thrd_id, + ldq_rel_ta_gpr => ldq_rel_ta_gpr, + ldq_rel_upd_gpr => ldq_rel_upd_gpr, + + ex1_src0_vld => ex1_src0_vld, + ex1_src0_reg => ex1_src0_reg, + ex1_src1_vld => ex1_src1_vld, + ex1_src1_reg => ex1_src1_reg, + ex1_targ_vld => ex1_targ_vld, + ex1_targ_reg => ex1_targ_reg, + ex1_check_watch => ex1_check_watch, + + ex1_lsu_64bit_agen => ex1_lsu_64bit_agen, + ex1_frc_align2 => ex1_frc_align2, + ex1_frc_align4 => ex1_frc_align4, + ex1_frc_align8 => ex1_frc_align8, + ex1_frc_align16 => ex1_frc_align16, + ex1_frc_align32 => ex1_frc_align32, + ex1_optype1 => ex1_optype1, + ex1_optype2 => ex1_optype2, + ex1_optype4 => ex1_optype4, + ex1_optype8 => ex1_optype8, + ex1_optype16 => ex1_optype16, + ex1_optype32 => ex1_optype32, + ex1_saxu_instr => ex1_saxu_instr, + ex1_sdp_instr => ex1_sdp_instr, + ex1_stgpr_instr => ex1_stgpr_instr, + ex1_store_instr => ex1_store_instr, + ex1_axu_op_val => ex1_axu_op_val, + ex2_optype2 => ex2_optype2, + ex2_optype4 => ex2_optype4, + ex2_optype8 => ex2_optype8, + ex2_optype16 => ex2_optype16, + ex2_optype32 => ex2_optype32, + ex2_icswx_type => ex2_icswx_type, + ex2_store_instr => ex2_store_instr_int, + ex1_dir_acc_val => ex1_dir_acc_val, + ex2_cache_acc => ex2_cache_acc, + ex3_cache_acc => ex3_cache_acc, + ex2_ldst_fexcpt => ex2_ldst_fexcpt, + ex2_axu_op => ex2_axu_op, + ex2_mv_reg_op => ex2_mv_reg_op, + ex1_thrd_id => ex1_thrd_id_int, + ex2_thrd_id => ex2_thrd_id, + ex3_thrd_id => ex3_thrd_id, + ex4_thrd_id => ex4_thrd_id, + ex5_thrd_id => ex5_thrd_id, + ex3_req_thrd_id => ex3_req_thrd_id, + ex3_targ_match_b1 => ex3_targ_match_b1, + ex2_targ_match_b2 => ex2_targ_match_b2, + ex3_target_gpr => ex3_target_gpr, + ex2_load_instr => ex2_load_instr, + ex3_dcbt_instr => ex3_dcbt_instr, + ex3_dcbtst_instr => ex3_dcbtst_instr, + ex3_th_fld_l2 => ex3_th_fld_l2, + ex3_dcbst_instr => ex3_dcbst_instr, + ex3_dcbf_instr => ex3_dcbf_instr, + ex3_sync_instr => ex3_sync_instr, + ex3_mtspr_trace => ex3_mtspr_trace, + ex3_byte_en => ex3_byte_en, + ex2_l_fld => ex2_l_fld, + ex3_l_fld => ex3_l_fld, + ex3_dcbi_instr => ex3_dcbi_instr, + ex2_dcbz_instr => ex2_dcbz_instr, + ex3_dcbz_instr => ex3_dcbz_instr, + ex3_icbi_instr => ex3_icbi_instr, + ex3_icswx_instr => ex3_icswx_instr, + ex3_icswx_dot => ex3_icswx_dot, + ex3_icswx_epid => ex3_icswx_epid, + ex3_mbar_instr => ex3_mbar_instr, + ex3_msgsnd_instr => ex3_msgsnd_instr, + ex3_dci_instr => ex3_dci_instr, + ex3_ici_instr => ex3_ici_instr, + ex2_lock_instr => ex2_lock_instr, + ex3_load_instr => ex3_load_instr, + ex3_store_instr => ex3_store_instr, + ex3_axu_op_val => ex3_axu_op_val, + ex4_drop_rel => ex4_drop_rel, + ex3_load_l1hit => ex3_load_l1hit, + ex3_rotate_sel => ex3_rotate_sel, + ex2_ldawx_instr => ex2_ldawx_instr_int, + ex2_wclr_instr => ex2_wclr_instr, + ex2_wchk_val => ex2_wchk_val, + ex3_watch_en => ex3_watch_en, + ex3_data_swap => ex3_data_swap, + ex3_load_val => ex3_load_val, + ex3_blkable_touch => ex3_blkable_touch, + ex3_l2_request => ex3_l2_request, + ex3_ldq_potential_flush => ex3_ldq_potential_flush, + ex7_targ_match => ex7_targ_match, + ex8_targ_match => ex8_targ_match, + ex4_ld_entry => ex4_ld_entry, + ex3_algebraic => ex3_algebraic, + ex3_dcbtls_instr => ex3_dcbtls_instr, + ex3_dcbtstls_instr => ex3_dcbtstls_instr, + ex3_dcblc_instr => ex3_dcblc_instr, + ex3_icblc_instr => ex3_icblc_instr, + ex3_icbt_instr => ex3_icbt_instr, + ex3_icbtls_instr => ex3_icbtls_instr, + ex3_tlbsync_instr => ex3_tlbsync_instr, + ex3_local_dcbf => ex3_local_dcbf, + rel_dcarr_val_upd => rel_dcarr_val_upd, + + ex2_no_lru_upd => ex2_no_lru_upd, + ex2_is_inval_op => ex2_is_inval_op, + ex2_lock_set => ex2_lock_set, + ex2_lock_clr => ex2_lock_clr, + ex2_ddir_acc_instr => ex2_ddir_acc_instr, + + ex3_lsq_flush => ex3_lsq_flush, + ex3_p_addr_lwr => ex3_p_addr_lwr, + ex3_lock_en => ex3_lock_en, + ex3_cache_en => ex3_cache_en, + ex3_cache_inh => ex3_cache_inh, + ex3_l_s_q_val => ex3_l_s_q_val, + ex3_drop_ld_req => ex3_drop_ld_req, + ex3_drop_touch => ex3_drop_touch, + ex3_stx_instr => ex3_stx_instr, + ex3_larx_instr => ex3_larx_instr, + ex3_mutex_hint => ex3_mutex_hint, + ex3_opsize => ex3_opsize, + ex4_store_hit => ex4_store_hit, + ex4_load_op_hit => ex4_load_op_hit, + ex5_load_op_hit => ex5_load_op_hit, + ex4_axu_op_val => ex4_axu_op_val, + + spr_xucr2_rmt => spr_xucr2_rmt, + spr_xucr0_wlck => spr_xucr0_wlck, + spr_dvc1_act => spr_dvc1_act, + spr_dvc2_act => spr_dvc2_act, + spr_dvc1_dbg => spr_dvc1_dbg, + spr_dvc2_dbg => spr_dvc2_dbg, + + lsu_xu_spr_xucr0_cul => lsu_xu_spr_xucr0_cul, + spr_xucr0_cls => spr_xucr0_cls, + agen_xucr0_cls => agen_xucr0_cls, + + dir_arr_rd_is2_val => dir_arr_rd_is2_val, + dir_arr_rd_congr_cl => dir_arr_rd_congr_cl, + + rf1_l2_inv_val => rf1_l2_inv_val, + ex1_agen_binv_val => ex1_agen_binv_val, + ex1_l2_inv_val => ex1_l2_inv_val, + + rel_upd_dcarr_val => rel_upd_dcarr_val, + + lsu_xu_ex4_cr_upd => lsu_xu_ex4_cr_upd, + lsu_xu_ex5_wren => lsu_xu_ex5_wren, + lsu_xu_rel_wren => lsu_xu_rel_wren, + lsu_xu_rel_ta_gpr => lsu_xu_rel_ta_gpr, + lsu_xu_perf_events => lsu_xu_perf_events(0 to 16), + lsu_xu_need_hole => lsu_xu_need_hole, + + xu_fu_ex5_reload_val => xu_fu_ex5_reload_val, + xu_fu_ex5_load_val => xu_fu_ex5_load_val, + xu_fu_ex5_load_tag => xu_fu_ex5_load_tag, + + xu_iu_ex6_icbi_val => xu_iu_ex6_icbi_val, + xu_iu_ex6_icbi_addr => xu_iu_ex6_icbi_addr, + + xu_derat_epsc_wr => xu_derat_epsc_wr, + xu_derat_eplc_wr => xu_derat_eplc_wr, + xu_derat_eplc0_epr => xu_derat_eplc0_epr, + xu_derat_eplc0_eas => xu_derat_eplc0_eas, + xu_derat_eplc0_egs => xu_derat_eplc0_egs, + xu_derat_eplc0_elpid => xu_derat_eplc0_elpid, + xu_derat_eplc0_epid => xu_derat_eplc0_epid, + xu_derat_eplc1_epr => xu_derat_eplc1_epr, + xu_derat_eplc1_eas => xu_derat_eplc1_eas, + xu_derat_eplc1_egs => xu_derat_eplc1_egs, + xu_derat_eplc1_elpid => xu_derat_eplc1_elpid, + xu_derat_eplc1_epid => xu_derat_eplc1_epid, + xu_derat_eplc2_epr => xu_derat_eplc2_epr, + xu_derat_eplc2_eas => xu_derat_eplc2_eas, + xu_derat_eplc2_egs => xu_derat_eplc2_egs, + xu_derat_eplc2_elpid => xu_derat_eplc2_elpid, + xu_derat_eplc2_epid => xu_derat_eplc2_epid, + xu_derat_eplc3_epr => xu_derat_eplc3_epr, + xu_derat_eplc3_eas => xu_derat_eplc3_eas, + xu_derat_eplc3_egs => xu_derat_eplc3_egs, + xu_derat_eplc3_elpid => xu_derat_eplc3_elpid, + xu_derat_eplc3_epid => xu_derat_eplc3_epid, + xu_derat_epsc0_epr => xu_derat_epsc0_epr, + xu_derat_epsc0_eas => xu_derat_epsc0_eas, + xu_derat_epsc0_egs => xu_derat_epsc0_egs, + xu_derat_epsc0_elpid => xu_derat_epsc0_elpid, + xu_derat_epsc0_epid => xu_derat_epsc0_epid, + xu_derat_epsc1_epr => xu_derat_epsc1_epr, + xu_derat_epsc1_eas => xu_derat_epsc1_eas, + xu_derat_epsc1_egs => xu_derat_epsc1_egs, + xu_derat_epsc1_elpid => xu_derat_epsc1_elpid, + xu_derat_epsc1_epid => xu_derat_epsc1_epid, + xu_derat_epsc2_epr => xu_derat_epsc2_epr, + xu_derat_epsc2_eas => xu_derat_epsc2_eas, + xu_derat_epsc2_egs => xu_derat_epsc2_egs, + xu_derat_epsc2_elpid => xu_derat_epsc2_elpid, + xu_derat_epsc2_epid => xu_derat_epsc2_epid, + xu_derat_epsc3_epr => xu_derat_epsc3_epr, + xu_derat_epsc3_eas => xu_derat_epsc3_eas, + xu_derat_epsc3_egs => xu_derat_epsc3_egs, + xu_derat_epsc3_elpid => xu_derat_epsc3_elpid, + xu_derat_epsc3_epid => xu_derat_epsc3_epid, + + dc_cntrl_dbg_data => dc_cntrl_dbg_data, + + ex1_stg_act => ex1_stg_act, + ex2_stg_act => ex2_stg_act, + ex3_stg_act => ex3_stg_act, + ex4_stg_act => ex4_stg_act, + ex5_stg_act => ex5_stg_act, + binv1_stg_act => binv1_stg_act, + binv2_stg_act => binv2_stg_act, + binv3_stg_act => binv3_stg_act, + binv4_stg_act => binv4_stg_act, + binv5_stg_act => binv5_stg_act, + rel1_stg_act => rel1_stg_act, + rel2_stg_act => rel2_stg_act, + rel3_stg_act => rel3_stg_act, + + vdd => vdd, + gnd => gnd, + nclk => nclk, + sg_0 => sg_0, + func_sl_thold_0_b => func_sl_thold_0_b, + func_sl_force => func_sl_force, + func_slp_sl_thold_0_b => func_slp_sl_thold_0_b, + func_slp_sl_force => func_slp_sl_force, + func_nsl_thold_0_b => func_nsl_thold_0_b, + func_nsl_force => func_nsl_force, + func_slp_nsl_thold_0_b => func_slp_nsl_thold_0_b, + func_slp_nsl_force => func_slp_nsl_force, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc, + mpw1_dc_b => mpw1_dc_b, + mpw2_dc_b => mpw2_dc_b, + scan_in => siv(dccntrl_offset), + scan_out => sov(dccntrl_offset) +); + + + +lsufgen : entity work.xuq_lsu_fgen(xuq_lsu_fgen) +generic map(expand_type => expand_type, + real_data_add => real_data_add) +port map( + ex2_cache_acc => ex2_cache_acc, + ex2_ldst_fexcpt => ex2_ldst_fexcpt, + ex2_mv_reg_op => ex2_mv_reg_op, + ex2_axu_op => ex2_axu_op, + rf1_thrd_id => xu_lsu_rf1_thrd_id, + ex1_thrd_id => ex1_thrd_id_int, + ex2_thrd_id => ex2_thrd_id, + ex3_thrd_id => ex3_thrd_id, + ex4_thrd_id => ex4_thrd_id, + ex5_thrd_id => ex5_thrd_id, + ex2_optype2 => ex2_optype2, + ex2_optype4 => ex2_optype4, + ex2_optype8 => ex2_optype8, + ex2_optype16 => ex2_optype16, + ex2_optype32 => ex2_optype32, + ex2_p_addr_lwr => ex2_p_addr_lwr(57 to 63), + ex2_icswx_type => ex2_icswx_type, + ex2_store_instr => ex2_store_instr_int, + ex2_load_instr => ex2_load_instr, + ex2_dcbz_instr => ex2_dcbz_instr, + ex2_lock_instr => ex2_lock_instr, + ex2_ldawx_instr => ex2_ldawx_instr_int, + ex2_lm_dep_hit => ex2_lm_dep_hit, + ex3_lsq_flush => ex3_lsq_flush, + derat_xu_ex3_noop_touch => derat_xu_ex3_noop_touch, + ex3_cClass_collision => ex3_cClass_collision, + ex2_lockwatchSet_rel_coll => ex2_lockwatchSet_rel_coll, + ex3_wclr_all_flush => ex3_wclr_all_flush, + ex3_wimge_w_bit => ex3_wimge_w_bit, + ex3_wimge_i_bit => ex3_wimge_i_bit, + ex3_targ_match_b1 => ex3_targ_match_b1, + ex2_targ_match_b2 => ex2_targ_match_b2, + xu_lsu_spr_xucr0_aflsta => xu_lsu_spr_xucr0_aflsta, + xu_lsu_spr_xucr0_flsta => xu_lsu_spr_xucr0_flsta, + xu_lsu_spr_xucr0_l2siw => xu_lsu_spr_xucr0_l2siw, + ldq_rel_ci => ldq_rel_ci, + ldq_rel_axu_val => ldq_rel_axu_val, + xu_lsu_rf1_flush => xu_lsu_rf1_flush, + xu_lsu_ex1_flush => xu_lsu_ex1_flush, + xu_lsu_ex2_flush => xu_lsu_ex2_flush, + xu_lsu_ex3_flush => xu_lsu_ex3_flush, + xu_lsu_ex4_flush => xu_lsu_ex4_flush, + xu_lsu_ex5_flush => xu_lsu_ex5_flush, + rf1_stg_flush => stg_flush_rf1, + ex1_stg_flush => stg_flush_ex1, + ex2_stg_flush => stg_flush_ex2, + ex3_stg_flush => stg_flush_ex3, + ex4_stg_flush => stg_flush_ex4, + ex5_stg_flush => stg_flush_ex5, + lsu_xu_ex3_n_flush_req => lsu_xu_ex3_n_flush_req, + lsu_xu_ex3_dep_flush => lsu_xu_ex3_dep_flush, + ex3_excp_det => ex3_excp_det, + lsu_xu_perf_events => lsu_xu_perf_events(17 to 20), + lsu_xu_ex3_align => lsu_xu_ex3_align, + lsu_xu_ex3_dsi => lsu_xu_ex3_dsi, + lsu_xu_ex3_inval_align_2ucode => lsu_xu_ex3_inval_align_2ucode, + dc_fgen_dbg_data => dc_fgen_dbg_data, + vdd => vdd, + gnd => gnd, + nclk => nclk, + sg_0 => sg_0, + func_sl_thold_0_b => func_sl_thold_0_b, + func_sl_force => func_sl_force, + func_nsl_thold_0_b => func_nsl_thold_0_b, + func_nsl_force => func_nsl_force, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc, + mpw1_dc_b => mpw1_dc_b, + mpw2_dc_b => mpw2_dc_b, + scan_in => siv(dcfgen_offset), + scan_out => sov(dcfgen_offset) +); + +ex2_stg_flush <= stg_flush_ex2; +ex3_stg_flush <= stg_flush_ex3; +ex4_stg_flush <= stg_flush_ex4; +ex5_stg_flush <= stg_flush_ex5; + +ex2_store_instr <= ex2_store_instr_int; +ex2_ldawx_instr <= ex2_ldawx_instr_int; +ex1_thrd_id <= ex1_thrd_id_int; + +siv(0 to scan_right) <= sov(1 to scan_right) & scan_in; +scan_out <= sov(0); + +end xuq_lsu_dc; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_dc_arr.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_dc_arr.vhdl new file mode 100644 index 0000000..6d58b2c --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_dc_arr.vhdl @@ -0,0 +1,288 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ibm, ieee, work, tri, support; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use tri.tri_latches_pkg.all; +use support.power_logic_pkg.all; + + +entity xuq_lsu_dc_arr is +generic(expand_type : integer := 2; + dc_size : natural := 14); +port( + + ex3_stg_act :in std_ulogic; + ex4_stg_act :in std_ulogic; + rel3_stg_act :in std_ulogic; + rel4_stg_act :in std_ulogic; + + ex3_p_addr :in std_ulogic_vector(64-(dc_size-3) to 58); + ex3_byte_en :in std_ulogic_vector(0 to 31); + ex4_256st_data :in std_ulogic_vector(0 to 255); + ex4_parity_gen :in std_ulogic_vector(0 to 31); + ex4_load_hit :in std_ulogic; + ex5_stg_flush :in std_ulogic; + + inj_dcache_parity :in std_ulogic; + + ldq_rel_data_val :in std_ulogic; + ldq_rel_addr :in std_ulogic_vector(64-(dc_size-3) to 58); + + dcarr_rd_data :in std_ulogic_vector(0 to 287); + + dcarr_bw :out std_ulogic_vector(0 to 287); + dcarr_addr :out std_ulogic_vector(64-(dc_size-3) to 58); + dcarr_wr_data :out std_ulogic_vector(0 to 287); + dcarr_bw_dly :out std_ulogic_vector(0 to 31); + + ex5_ld_data :out std_ulogic_vector(0 to 255); + ex5_ld_data_par :out std_ulogic_vector(0 to 31); + ex6_par_chk_val :out std_ulogic; + + vdd :inout power_logic; + gnd :inout power_logic; + nclk :in clk_logic; + sg_0 :in std_ulogic; + func_sl_thold_0_b :in std_ulogic; + func_sl_force :in std_ulogic; + func_nsl_thold_0_b :in std_ulogic; + func_nsl_force :in std_ulogic; + d_mode_dc :in std_ulogic; + delay_lclkr_dc :in std_ulogic; + mpw1_dc_b :in std_ulogic; + mpw2_dc_b :in std_ulogic; + scan_in :in std_ulogic; + scan_out :out std_ulogic +); +-- synopsys translate_off +-- synopsys translate_on +end xuq_lsu_dc_arr; +architecture xuq_lsu_dc_arr of xuq_lsu_dc_arr is + + +constant ex6_par_err_val_offset :natural := 0; +constant ex5_load_op_hit_offset :natural := ex6_par_err_val_offset + 1; +constant arr_addr_offset :natural := ex5_load_op_hit_offset + 1; +constant arr_bw_offset :natural := arr_addr_offset + 58-(64-(dc_size-3))+1; +constant scan_right :natural := arr_bw_offset + 32 - 1; + + +signal xuop_addr :std_ulogic_vector(64-(dc_size-3) to 58); +signal st_byte_en :std_ulogic_vector(0 to 31); +signal rel_addr :std_ulogic_vector(64-(dc_size-3) to 58); +signal arr_addr_d :std_ulogic_vector(64-(dc_size-3) to 58); +signal arr_addr_q :std_ulogic_vector(64-(dc_size-3) to 58); +signal arr_st_data :std_ulogic_vector(0 to 255); +signal arr_parity :std_ulogic_vector(0 to 31); +signal arr_wr_data :std_ulogic_vector(0 to 287); +signal arr_bw_d :std_ulogic_vector(0 to 31); +signal arr_bw_q :std_ulogic_vector(0 to 31); +signal arr_bw_dly_d :std_ulogic_vector(0 to 31); +signal arr_bw_dly_q :std_ulogic_vector(0 to 31); +signal arr_rd_data :std_ulogic_vector(0 to 287); +signal arr_ld_data :std_ulogic_vector(0 to 255); +signal ld_arr_parity :std_ulogic_vector(0 to 31); +signal rel_val_data :std_ulogic; +signal ex5_load_op_hit_d :std_ulogic; +signal ex5_load_op_hit_q :std_ulogic; +signal ex6_par_err_val_d :std_ulogic; +signal ex6_par_err_val_q :std_ulogic; +signal rel3_ex3_stg_act :std_ulogic; +signal rel4_ex4_stg_act :std_ulogic; +signal inj_dcache_parity_b :std_ulogic; +signal arr_rd_data64_b :std_ulogic; +signal stickBit64 :std_ulogic; + +signal tiup :std_ulogic; +signal siv :std_ulogic_vector(0 to scan_right); +signal sov :std_ulogic_vector(0 to scan_right); +begin + + +rel3_ex3_stg_act <= rel3_stg_act or ex3_stg_act; +rel4_ex4_stg_act <= rel4_stg_act or ex4_stg_act; + +tiup <= '1'; + +xuop_addr <= ex3_p_addr; +st_byte_en <= ex3_byte_en; +arr_parity <= ex4_parity_gen; +rel_val_data <= ldq_rel_data_val; +rel_addr <= ldq_rel_addr; + +arr_rd_data <= dcarr_rd_data; +arr_st_data <= ex4_256st_data; +ex5_load_op_hit_d <= ex4_load_hit; +inj_dcache_parity_b <= not inj_dcache_parity; + + +with rel_val_data select + arr_addr_d <= xuop_addr when '0', + rel_addr when others; + +with rel_val_data select + arr_bw_d <= st_byte_en when '0', + x"FFFFFFFF" when others; + +arr_bw_dly_d <= arr_bw_q; + + +arr_wr_data <= arr_st_data(0 to 127) & arr_parity(0 to 15) & + arr_st_data(128 to 255) & arr_parity(16 to 31); + + +arr_rd_data64_b <= not arr_rd_data(64); +stickBit64 <= not (arr_rd_data64_b and inj_dcache_parity_b); + + +arr_ld_data <= arr_rd_data(0 to 63) & stickBit64 & arr_rd_data(65 to 127) & arr_rd_data(144 to 271); + +ld_arr_parity <= arr_rd_data(128 to 143) & arr_rd_data(272 to 287); + +ex6_par_err_val_d <= ex5_load_op_hit_q and not ex5_stg_flush; + + + +bw_gen : for bi in 0 to 31 generate begin + dcarr_bw(bi+0) <= arr_bw_q(bi); + dcarr_bw(bi+32) <= arr_bw_q(bi); + dcarr_bw(bi+64) <= arr_bw_q(bi); + dcarr_bw(bi+96) <= arr_bw_q(bi); + dcarr_bw(bi+144) <= arr_bw_q(bi); + dcarr_bw(bi+176) <= arr_bw_q(bi); + dcarr_bw(bi+208) <= arr_bw_q(bi); + dcarr_bw(bi+240) <= arr_bw_q(bi); + dcarr_bw(bi+128+(128*(bi/16))) <= arr_bw_q(bi); +end generate bw_gen; + +dcarr_addr <= arr_addr_q; +dcarr_wr_data <= arr_wr_data; +dcarr_bw_dly <= arr_bw_dly_q; + +ex5_ld_data <= arr_ld_data; +ex5_ld_data_par <= ld_arr_parity; +ex6_par_chk_val <= ex6_par_err_val_q; + +ex6_par_err_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_par_err_val_offset), + scout => sov(ex6_par_err_val_offset), + din => ex6_par_err_val_d, + dout => ex6_par_err_val_q); + +ex5_load_op_hit_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_load_op_hit_offset), + scout => sov(ex5_load_op_hit_offset), + din => ex5_load_op_hit_d, + dout => ex5_load_op_hit_q); + +arr_addr_reg: tri_rlmreg_p + generic map (width => 58-(64-(dc_size-3))+1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_ex3_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(arr_addr_offset to arr_addr_offset + arr_addr_d'length-1), + scout => sov(arr_addr_offset to arr_addr_offset + arr_addr_d'length-1), + din => arr_addr_d, + dout => arr_addr_q); + +arr_bw_reg: tri_rlmreg_p + generic map (width => 32, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_ex3_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(arr_bw_offset to arr_bw_offset + arr_bw_d'length-1), + scout => sov(arr_bw_offset to arr_bw_offset + arr_bw_d'length-1), + din => arr_bw_d, + dout => arr_bw_q); + +arr_bw_dly_reg: tri_regk + generic map (width => 32, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel4_ex4_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => arr_bw_dly_d, + dout => arr_bw_dly_q); + +siv(0 to scan_right) <= sov(1 to scan_right) & scan_in; +scan_out <= sov(0); + +end xuq_lsu_dc_arr; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_dc_cntrl.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_dc_cntrl.vhdl new file mode 100644 index 0000000..0f3a6b4 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_dc_cntrl.vhdl @@ -0,0 +1,8451 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ibm, ieee, work, tri, support; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use tri.tri_latches_pkg.all; +use support.power_logic_pkg.all; + + +entity xuq_lsu_dc_cntrl is +generic(expand_type : integer := 2; + regmode : integer := 6; + dc_size : natural := 14; + parBits : natural := 4; + real_data_add : integer := 42); +port( + + xu_lsu_rf0_act :in std_ulogic; + xu_lsu_rf1_cmd_act :in std_ulogic; + xu_lsu_rf1_axu_op_val :in std_ulogic; + xu_lsu_rf1_axu_ldst_falign :in std_ulogic; + xu_lsu_rf1_axu_ldst_fexcpt :in std_ulogic; + xu_lsu_rf1_cache_acc :in std_ulogic; + xu_lsu_rf1_thrd_id :in std_ulogic_vector(0 to 3); + xu_lsu_rf1_optype1 :in std_ulogic; + xu_lsu_rf1_optype2 :in std_ulogic; + xu_lsu_rf1_optype4 :in std_ulogic; + xu_lsu_rf1_optype8 :in std_ulogic; + xu_lsu_rf1_optype16 :in std_ulogic; + xu_lsu_rf1_optype32 :in std_ulogic; + xu_lsu_rf1_target_gpr :in std_ulogic_vector(0 to 8); + xu_lsu_rf1_mtspr_trace :in std_ulogic; + xu_lsu_rf1_load_instr :in std_ulogic; + xu_lsu_rf1_store_instr :in std_ulogic; + xu_lsu_rf1_dcbf_instr :in std_ulogic; + xu_lsu_rf1_sync_instr :in std_ulogic; + xu_lsu_rf1_l_fld :in std_ulogic_vector(0 to 1); + xu_lsu_rf1_dcbi_instr :in std_ulogic; + xu_lsu_rf1_dcbz_instr :in std_ulogic; + xu_lsu_rf1_dcbt_instr :in std_ulogic; + xu_lsu_rf1_dcbtst_instr :in std_ulogic; + xu_lsu_rf1_th_fld :in std_ulogic_vector(0 to 4); + xu_lsu_rf1_dcbtls_instr :in std_ulogic; + xu_lsu_rf1_dcbtstls_instr :in std_ulogic; + xu_lsu_rf1_dcblc_instr :in std_ulogic; + xu_lsu_rf1_dcbst_instr :in std_ulogic; + xu_lsu_rf1_icbi_instr :in std_ulogic; + xu_lsu_rf1_icblc_instr :in std_ulogic; + xu_lsu_rf1_icbt_instr :in std_ulogic; + xu_lsu_rf1_icbtls_instr :in std_ulogic; + xu_lsu_rf1_icswx_instr :in std_ulogic; + xu_lsu_rf1_icswx_dot_instr :in std_ulogic; + xu_lsu_rf1_icswx_epid :in std_ulogic; + xu_lsu_rf1_tlbsync_instr :in std_ulogic; + xu_lsu_rf1_ldawx_instr :in std_ulogic; + xu_lsu_rf1_wclr_instr :in std_ulogic; + xu_lsu_rf1_wchk_instr :in std_ulogic; + xu_lsu_rf1_lock_instr :in std_ulogic; + xu_lsu_rf1_mutex_hint :in std_ulogic; + xu_lsu_rf1_mbar_instr :in std_ulogic; + xu_lsu_rf1_is_msgsnd :in std_ulogic; + xu_lsu_rf1_dci_instr :in std_ulogic; + xu_lsu_rf1_ici_instr :in std_ulogic; + xu_lsu_rf1_algebraic :in std_ulogic; + xu_lsu_rf1_byte_rev :in std_ulogic; + xu_lsu_rf1_src_gpr :in std_ulogic; + xu_lsu_rf1_src_axu :in std_ulogic; + xu_lsu_rf1_src_dp :in std_ulogic; + xu_lsu_rf1_targ_gpr :in std_ulogic; + xu_lsu_rf1_targ_axu :in std_ulogic; + xu_lsu_rf1_targ_dp :in std_ulogic; + xu_lsu_ex4_val :in std_ulogic_vector(0 to 3); + + xu_lsu_rf1_src0_vld :in std_ulogic; + xu_lsu_rf1_src0_reg :in std_ulogic_vector(0 to 7); + xu_lsu_rf1_src1_vld :in std_ulogic; + xu_lsu_rf1_src1_reg :in std_ulogic_vector(0 to 7); + xu_lsu_rf1_targ_vld :in std_ulogic; + xu_lsu_rf1_targ_reg :in std_ulogic_vector(0 to 7); + + is2_l2_inv_val :in std_ulogic; + + ex3_wayA_tag :in std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex3_wayB_tag :in std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex3_wayC_tag :in std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex3_wayD_tag :in std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex3_wayE_tag :in std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex3_wayF_tag :in std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex3_wayG_tag :in std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex3_wayH_tag :in std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex3_way_tag_par_a :in std_ulogic_vector(0 to parBits-1); + ex3_way_tag_par_b :in std_ulogic_vector(0 to parBits-1); + ex3_way_tag_par_c :in std_ulogic_vector(0 to parBits-1); + ex3_way_tag_par_d :in std_ulogic_vector(0 to parBits-1); + ex3_way_tag_par_e :in std_ulogic_vector(0 to parBits-1); + ex3_way_tag_par_f :in std_ulogic_vector(0 to parBits-1); + ex3_way_tag_par_g :in std_ulogic_vector(0 to parBits-1); + ex3_way_tag_par_h :in std_ulogic_vector(0 to parBits-1); + ex4_way_a_dir :in std_ulogic_vector(0 to 5); + ex4_way_b_dir :in std_ulogic_vector(0 to 5); + ex4_way_c_dir :in std_ulogic_vector(0 to 5); + ex4_way_d_dir :in std_ulogic_vector(0 to 5); + ex4_way_e_dir :in std_ulogic_vector(0 to 5); + ex4_way_f_dir :in std_ulogic_vector(0 to 5); + ex4_way_g_dir :in std_ulogic_vector(0 to 5); + ex4_way_h_dir :in std_ulogic_vector(0 to 5); + ex4_dir_lru :in std_ulogic_vector(0 to 6); + + ex2_p_addr_lwr :in std_ulogic_vector(52 to 63); + ex3_wimge_i_bit :in std_ulogic; + ex3_wimge_e_bit :in std_ulogic; + + ex3_p_addr :in std_ulogic_vector(64-real_data_add to 51); + ex3_ld_queue_full :in std_ulogic; + ex3_stq_flush :in std_ulogic; + ex3_ig_flush :in std_ulogic; + ex3_hit :in std_ulogic; + ex4_miss :in std_ulogic; + ex4_snd_ld_l2 :in std_ulogic; + ex3_excp_det :in std_ulogic; + + rf1_stg_flush :in std_ulogic; + ex1_stg_flush :in std_ulogic; + ex2_stg_flush :in std_ulogic; + ex3_stg_flush :in std_ulogic; + ex4_stg_flush :in std_ulogic; + ex5_stg_flush :in std_ulogic; + + rel_dcarr_val_upd :in std_ulogic; + + xu_lsu_mtspr_trace_en :in std_ulogic_vector(0 to 3); + spr_xucr0_clkg_ctl_b1 :in std_ulogic; + xu_lsu_spr_xucr0_wlk :in std_ulogic; + xu_lsu_spr_ccr2_dfrat :in std_ulogic; + xu_lsu_spr_xucr0_flh2l2 :in std_ulogic; + xu_lsu_spr_xucr0_cls :in std_ulogic; + xu_lsu_spr_xucr0_dcdis :in std_ulogic; + xu_lsu_spr_msr_cm :in std_ulogic_vector(0 to 3); + + xu_lsu_msr_gs :in std_ulogic_vector(0 to 3); + xu_lsu_msr_pr :in std_ulogic_vector(0 to 3); + + an_ac_flh2l2_gate :in std_ulogic; + + xu_lsu_slowspr_val :in std_ulogic; + xu_lsu_slowspr_rw :in std_ulogic; + xu_lsu_slowspr_etid :in std_ulogic_vector(0 to 1); + xu_lsu_slowspr_addr :in std_ulogic_vector(0 to 9); + xu_lsu_slowspr_data :in std_ulogic_vector(64-(2**REGMODE) to 63); + xu_lsu_slowspr_done :in std_ulogic; + slowspr_val_out :out std_ulogic; + slowspr_rw_out :out std_ulogic; + slowspr_etid_out :out std_ulogic_vector(0 to 1); + slowspr_addr_out :out std_ulogic_vector(0 to 9); + slowspr_data_out :out std_ulogic_vector(64-(2**REGMODE) to 63); + slowspr_done_out :out std_ulogic; + + ldq_rel_data_val_early :in std_ulogic; + ldq_rel_stg24_val :in std_ulogic; + ldq_rel_axu_val :in std_ulogic; + ldq_rel_thrd_id :in std_ulogic_vector(0 to 3); + ldq_rel_ta_gpr :in std_ulogic_vector(0 to 8); + ldq_rel_upd_gpr :in std_ulogic; + + ex1_src0_vld :out std_ulogic; + ex1_src0_reg :out std_ulogic_vector(0 to 7); + ex1_src1_vld :out std_ulogic; + ex1_src1_reg :out std_ulogic_vector(0 to 7); + ex1_targ_vld :out std_ulogic; + ex1_targ_reg :out std_ulogic_vector(0 to 7); + ex1_check_watch :out std_ulogic_vector(0 to 3); + + ex1_lsu_64bit_agen :out std_ulogic; + ex1_frc_align2 :out std_ulogic; + ex1_frc_align4 :out std_ulogic; + ex1_frc_align8 :out std_ulogic; + ex1_frc_align16 :out std_ulogic; + ex1_frc_align32 :out std_ulogic; + ex1_optype1 :out std_ulogic; + ex1_optype2 :out std_ulogic; + ex1_optype4 :out std_ulogic; + ex1_optype8 :out std_ulogic; + ex1_optype16 :out std_ulogic; + ex1_optype32 :out std_ulogic; + ex1_saxu_instr :out std_ulogic; + ex1_sdp_instr :out std_ulogic; + ex1_stgpr_instr :out std_ulogic; + ex1_store_instr :out std_ulogic; + ex1_axu_op_val :out std_ulogic; + + ex2_optype2 :out std_ulogic; + ex2_optype4 :out std_ulogic; + ex2_optype8 :out std_ulogic; + ex2_optype16 :out std_ulogic; + ex2_optype32 :out std_ulogic; + ex2_icswx_type :out std_ulogic; + ex2_store_instr :out std_ulogic; + ex1_dir_acc_val :out std_ulogic; + ex2_cache_acc :out std_ulogic; + ex3_cache_acc :out std_ulogic; + ex2_ldst_fexcpt :out std_ulogic; + ex2_axu_op :out std_ulogic; + ex2_mv_reg_op :out std_ulogic; + ex1_thrd_id :out std_ulogic_vector(0 to 3); + ex2_thrd_id :out std_ulogic_vector(0 to 3); + ex3_thrd_id :out std_ulogic_vector(0 to 3); + ex4_thrd_id :out std_ulogic_vector(0 to 3); + ex5_thrd_id :out std_ulogic_vector(0 to 3); + ex3_req_thrd_id :out std_ulogic_vector(0 to 3); + ex3_targ_match_b1 :out std_ulogic; + ex2_targ_match_b2 :out std_ulogic; + ex3_target_gpr :out std_ulogic_vector(0 to 8); + ex2_load_instr :out std_ulogic; + ex3_dcbt_instr :out std_ulogic; + ex3_dcbtst_instr :out std_ulogic; + ex3_th_fld_l2 :out std_ulogic; + ex3_dcbst_instr :out std_ulogic; + ex3_dcbf_instr :out std_ulogic; + ex3_sync_instr :out std_ulogic; + ex3_mtspr_trace :out std_ulogic; + ex3_byte_en :out std_ulogic_vector(0 to 31); + ex2_l_fld :out std_ulogic_vector(0 to 1); + ex3_l_fld :out std_ulogic_vector(0 to 1); + ex3_dcbi_instr :out std_ulogic; + ex2_dcbz_instr :out std_ulogic; + ex3_dcbz_instr :out std_ulogic; + ex3_icbi_instr :out std_ulogic; + ex3_icswx_instr :out std_ulogic; + ex3_icswx_dot :out std_ulogic; + ex3_icswx_epid :out std_ulogic; + ex3_mbar_instr :out std_ulogic; + ex3_msgsnd_instr :out std_ulogic; + ex3_dci_instr :out std_ulogic; + ex3_ici_instr :out std_ulogic; + ex2_lock_instr :out std_ulogic; + ex3_load_instr :out std_ulogic; + ex3_store_instr :out std_ulogic; + ex3_axu_op_val :out std_ulogic; + ex3_algebraic :out std_ulogic; + ex3_dcbtls_instr :out std_ulogic; + ex3_dcbtstls_instr :out std_ulogic; + ex3_dcblc_instr :out std_ulogic; + ex3_icblc_instr :out std_ulogic; + ex3_icbt_instr :out std_ulogic; + ex3_icbtls_instr :out std_ulogic; + ex3_tlbsync_instr :out std_ulogic; + ex3_local_dcbf :out std_ulogic; + ex4_drop_rel :out std_ulogic; + ex3_load_l1hit :out std_ulogic; + ex3_rotate_sel :out std_ulogic_vector(0 to 4); + ex2_ldawx_instr :out std_ulogic; + ex2_wclr_instr :out std_ulogic; + ex2_wchk_val :out std_ulogic; + ex3_watch_en :out std_ulogic; + ex3_data_swap :out std_ulogic; + ex3_load_val :out std_ulogic; + ex3_blkable_touch :out std_ulogic; + ex3_l2_request :out std_ulogic; + ex3_ldq_potential_flush :out std_ulogic; + ex7_targ_match :out std_ulogic; + ex8_targ_match :out std_ulogic; + ex4_ld_entry :out std_ulogic_vector(0 to 67); + + ex2_no_lru_upd :out std_ulogic; + ex2_is_inval_op :out std_ulogic; + ex2_lock_set :out std_ulogic; + ex2_lock_clr :out std_ulogic; + ex2_ddir_acc_instr :out std_ulogic; + + ex3_lsq_flush :out std_ulogic; + ex3_p_addr_lwr :out std_ulogic_vector(58 to 63); + ex3_lock_en :out std_ulogic; + ex3_cache_en :out std_ulogic; + ex3_cache_inh :out std_ulogic; + ex3_l_s_q_val :out std_ulogic; + ex3_drop_ld_req :out std_ulogic; + ex3_drop_touch :out std_ulogic; + ex3_stx_instr :out std_ulogic; + ex3_larx_instr :out std_ulogic; + ex3_mutex_hint :out std_ulogic; + ex3_opsize :out std_ulogic_vector(0 to 5); + ex4_store_hit :out std_ulogic; + ex4_load_op_hit :out std_ulogic; + ex5_load_op_hit :out std_ulogic; + ex4_axu_op_val :out std_ulogic; + + spr_xucr2_rmt :out std_ulogic_vector(0 to 31); + spr_xucr0_wlck :out std_ulogic; + spr_dvc1_act :out std_ulogic; + spr_dvc2_act :out std_ulogic; + spr_dvc1_dbg :out std_ulogic_vector(64-(2**regmode) to 63); + spr_dvc2_dbg :out std_ulogic_vector(64-(2**regmode) to 63); + + lsu_xu_spr_xucr0_cul :out std_ulogic; + spr_xucr0_cls :out std_ulogic; + agen_xucr0_cls :out std_ulogic; + + dir_arr_rd_is2_val :out std_ulogic; + dir_arr_rd_congr_cl :out std_ulogic_vector(0 to 4); + + rf1_l2_inv_val :out std_ulogic; + ex1_agen_binv_val :out std_ulogic; + ex1_l2_inv_val :out std_ulogic; + + rel_upd_dcarr_val :out std_ulogic; + + lsu_xu_ex4_cr_upd :out std_ulogic; + lsu_xu_ex5_wren :out std_ulogic; + lsu_xu_rel_wren :out std_ulogic; + lsu_xu_rel_ta_gpr :out std_ulogic_vector(0 to 7); + lsu_xu_perf_events :out std_ulogic_vector(0 to 16); + lsu_xu_need_hole :out std_ulogic; + + xu_fu_ex5_reload_val :out std_ulogic; + xu_fu_ex5_load_val :out std_ulogic_vector(0 to 3); + xu_fu_ex5_load_tag :out std_ulogic_vector(0 to 8); + + xu_iu_ex6_icbi_val :out std_ulogic_vector(0 to 3); + xu_iu_ex6_icbi_addr :out std_ulogic_vector(64-real_data_add to 57); + + xu_derat_epsc_wr :out std_ulogic_vector(0 to 3); + xu_derat_eplc_wr :out std_ulogic_vector(0 to 3); + xu_derat_eplc0_epr :out std_ulogic; + xu_derat_eplc0_eas :out std_ulogic; + xu_derat_eplc0_egs :out std_ulogic; + xu_derat_eplc0_elpid :out std_ulogic_vector(40 to 47); + xu_derat_eplc0_epid :out std_ulogic_vector(50 to 63); + xu_derat_eplc1_epr :out std_ulogic; + xu_derat_eplc1_eas :out std_ulogic; + xu_derat_eplc1_egs :out std_ulogic; + xu_derat_eplc1_elpid :out std_ulogic_vector(40 to 47); + xu_derat_eplc1_epid :out std_ulogic_vector(50 to 63); + xu_derat_eplc2_epr :out std_ulogic; + xu_derat_eplc2_eas :out std_ulogic; + xu_derat_eplc2_egs :out std_ulogic; + xu_derat_eplc2_elpid :out std_ulogic_vector(40 to 47); + xu_derat_eplc2_epid :out std_ulogic_vector(50 to 63); + xu_derat_eplc3_epr :out std_ulogic; + xu_derat_eplc3_eas :out std_ulogic; + xu_derat_eplc3_egs :out std_ulogic; + xu_derat_eplc3_elpid :out std_ulogic_vector(40 to 47); + xu_derat_eplc3_epid :out std_ulogic_vector(50 to 63); + xu_derat_epsc0_epr :out std_ulogic; + xu_derat_epsc0_eas :out std_ulogic; + xu_derat_epsc0_egs :out std_ulogic; + xu_derat_epsc0_elpid :out std_ulogic_vector(40 to 47); + xu_derat_epsc0_epid :out std_ulogic_vector(50 to 63); + xu_derat_epsc1_epr :out std_ulogic; + xu_derat_epsc1_eas :out std_ulogic; + xu_derat_epsc1_egs :out std_ulogic; + xu_derat_epsc1_elpid :out std_ulogic_vector(40 to 47); + xu_derat_epsc1_epid :out std_ulogic_vector(50 to 63); + xu_derat_epsc2_epr :out std_ulogic; + xu_derat_epsc2_eas :out std_ulogic; + xu_derat_epsc2_egs :out std_ulogic; + xu_derat_epsc2_elpid :out std_ulogic_vector(40 to 47); + xu_derat_epsc2_epid :out std_ulogic_vector(50 to 63); + xu_derat_epsc3_epr :out std_ulogic; + xu_derat_epsc3_eas :out std_ulogic; + xu_derat_epsc3_egs :out std_ulogic; + xu_derat_epsc3_elpid :out std_ulogic_vector(40 to 47); + xu_derat_epsc3_epid :out std_ulogic_vector(50 to 63); + + dc_cntrl_dbg_data :out std_ulogic_vector(0 to 66); + + ex1_stg_act :out std_ulogic; + ex2_stg_act :out std_ulogic; + ex3_stg_act :out std_ulogic; + ex4_stg_act :out std_ulogic; + ex5_stg_act :out std_ulogic; + binv1_stg_act :out std_ulogic; + binv2_stg_act :out std_ulogic; + binv3_stg_act :out std_ulogic; + binv4_stg_act :out std_ulogic; + binv5_stg_act :out std_ulogic; + rel1_stg_act :out std_ulogic; + rel2_stg_act :out std_ulogic; + rel3_stg_act :out std_ulogic; + + vdd :inout power_logic; + gnd :inout power_logic; + nclk :in clk_logic; + sg_0 :in std_ulogic; + func_sl_thold_0_b :in std_ulogic; + func_sl_force :in std_ulogic; + func_slp_sl_thold_0_b :in std_ulogic; + func_slp_sl_force :in std_ulogic; + func_nsl_thold_0_b :in std_ulogic; + func_nsl_force :in std_ulogic; + func_slp_nsl_thold_0_b :in std_ulogic; + func_slp_nsl_force :in std_ulogic; + d_mode_dc :in std_ulogic; + delay_lclkr_dc :in std_ulogic; + mpw1_dc_b :in std_ulogic; + mpw2_dc_b :in std_ulogic; + scan_in :in std_ulogic; + scan_out :out std_ulogic +); +-- synopsys translate_off +-- synopsys translate_on +end xuq_lsu_dc_cntrl; +architecture xuq_lsu_dc_cntrl of xuq_lsu_dc_cntrl is + + +constant tagSize :natural := (63-(dc_size-3))-(64-real_data_add)+1; +constant rot_max_size :std_ulogic_vector(0 to 5) := "100000"; + +constant ex1_optype1_offset :natural := 0; +constant ex1_optype2_offset :natural := ex1_optype1_offset + 1; +constant ex1_optype4_offset :natural := ex1_optype2_offset + 1; +constant ex1_optype8_offset :natural := ex1_optype4_offset + 1; +constant ex1_optype16_offset :natural := ex1_optype8_offset + 1; +constant ex1_optype32_offset :natural := ex1_optype16_offset + 1; +constant ex1_dir_acc_val_offset :natural := ex1_optype32_offset + 1; +constant cache_acc_ex1_offset :natural := ex1_dir_acc_val_offset + 1; +constant cache_acc_ex2_offset :natural := cache_acc_ex1_offset + 1; +constant cache_acc_ex3_offset :natural := cache_acc_ex2_offset + 1; +constant cache_acc_ex4_offset :natural := cache_acc_ex3_offset + 1; +constant cache_acc_ex5_offset :natural := cache_acc_ex4_offset + 1; +constant ex2_cacc_offset :natural := cache_acc_ex5_offset + 1; +constant ex3_cacc_offset :natural := ex2_cacc_offset + 1; +constant ex1_thrd_id_offset :natural := ex3_cacc_offset + 1; +constant ex3_thrd_id_offset :natural := ex1_thrd_id_offset + 4; +constant ex5_thrd_id_offset :natural := ex3_thrd_id_offset + 4; +constant ex1_target_gpr_offset :natural := ex5_thrd_id_offset + 4; +constant ex3_target_gpr_offset :natural := ex1_target_gpr_offset + 9; +constant ex1_dcbt_instr_offset :natural := ex3_target_gpr_offset + 9; +constant ex3_dcbt_instr_offset :natural := ex1_dcbt_instr_offset + 1; +constant ex1_dcbtst_instr_offset :natural := ex3_dcbt_instr_offset + 1; +constant ex3_dcbtst_instr_offset :natural := ex1_dcbtst_instr_offset + 1; +constant ex1_dcbst_instr_offset :natural := ex3_dcbtst_instr_offset + 1; +constant ex3_dcbst_instr_offset :natural := ex1_dcbst_instr_offset + 1; +constant ex1_dcbf_instr_offset :natural := ex3_dcbst_instr_offset + 1; +constant ex3_dcbf_instr_offset :natural := ex1_dcbf_instr_offset + 1; +constant ex1_sync_instr_offset :natural := ex3_dcbf_instr_offset + 1; +constant ex2_sync_instr_offset :natural := ex1_sync_instr_offset + 1; +constant ex3_sync_instr_offset :natural := ex2_sync_instr_offset + 1; +constant ex1_l_fld_offset :natural := ex3_sync_instr_offset + 1; +constant ex3_l_fld_offset :natural := ex1_l_fld_offset + 2; +constant ex1_dcbi_instr_offset :natural := ex3_l_fld_offset + 2; +constant ex3_dcbi_instr_offset :natural := ex1_dcbi_instr_offset + 1; +constant ex1_dcbz_instr_offset :natural := ex3_dcbi_instr_offset + 1; +constant ex3_dcbz_instr_offset :natural := ex1_dcbz_instr_offset + 1; +constant ex1_icbi_instr_offset :natural := ex3_dcbz_instr_offset + 1; +constant ex3_icbi_instr_offset :natural := ex1_icbi_instr_offset + 1; +constant ex5_icbi_instr_offset :natural := ex3_icbi_instr_offset + 1; +constant ex1_mbar_instr_offset :natural := ex5_icbi_instr_offset + 1; +constant ex2_mbar_instr_offset :natural := ex1_mbar_instr_offset + 1; +constant ex3_mbar_instr_offset :natural := ex2_mbar_instr_offset + 1; +constant ex1_algebraic_offset :natural := ex3_mbar_instr_offset + 1; +constant ex3_algebraic_offset :natural := ex1_algebraic_offset + 1; +constant ex1_byte_rev_offset :natural := ex3_algebraic_offset + 1; +constant ex3_byte_rev_offset :natural := ex1_byte_rev_offset + 1; +constant ex1_lock_instr_offset :natural := ex3_byte_rev_offset + 1; +constant ex3_lock_instr_offset :natural := ex1_lock_instr_offset + 1; +constant ex5_lock_instr_offset :natural := ex3_lock_instr_offset + 1; +constant ex1_mutex_hint_offset :natural := ex5_lock_instr_offset + 1; +constant ex3_mutex_hint_offset :natural := ex1_mutex_hint_offset + 1; +constant ex1_load_instr_offset :natural := ex3_mutex_hint_offset + 1; +constant ex3_load_instr_offset :natural := ex1_load_instr_offset + 1; +constant ex5_load_instr_offset :natural := ex3_load_instr_offset + 1; +constant ex1_store_instr_offset :natural := ex5_load_instr_offset + 1; +constant ex3_store_instr_offset :natural := ex1_store_instr_offset + 1; +constant ex3_l2_op_offset :natural := ex3_store_instr_offset + 1; +constant ex5_cache_inh_offset :natural := ex3_l2_op_offset + 1; +constant ex3_opsize_offset :natural := ex5_cache_inh_offset + 1; +constant ex1_axu_op_val_offset :natural := ex3_opsize_offset + 6; +constant ex3_axu_op_val_offset :natural := ex1_axu_op_val_offset + 1; +constant ex5_axu_op_val_offset :natural := ex3_axu_op_val_offset + 1; +constant rel_upd_gpr_offset :natural := ex5_axu_op_val_offset + 1; +constant rel_axu_op_val_offset :natural := rel_upd_gpr_offset + 1; +constant rel_thrd_id_offset :natural := rel_axu_op_val_offset + 1; +constant rel_ta_gpr_offset :natural := rel_thrd_id_offset + 4; +constant ex4_load_commit_offset :natural := rel_ta_gpr_offset + 9; +constant ex5_load_hit_offset :natural := ex4_load_commit_offset + 1; +constant ex5_axu_rel_val_stg1_offset :natural := ex5_load_hit_offset + 1; +constant ex5_axu_rel_val_stg2_offset :natural := ex5_axu_rel_val_stg1_offset + 1; +constant ex5_axu_wren_offset :natural := ex5_axu_rel_val_stg2_offset + 1; +constant ex5_axu_ta_gpr_offset :natural := ex5_axu_wren_offset + 4; +constant rel_xu_ta_gpr_offset :natural := ex5_axu_ta_gpr_offset + 9; +constant lsu_slowspr_val_offset :natural := rel_xu_ta_gpr_offset + 8; +constant lsu_slowspr_rw_offset :natural := lsu_slowspr_val_offset + 1; +constant lsu_slowspr_etid_offset :natural := lsu_slowspr_rw_offset + 1; +constant lsu_slowspr_addr_offset :natural := lsu_slowspr_etid_offset + 2; +constant lsu_slowspr_data_offset :natural := lsu_slowspr_addr_offset + 10; +constant lsu_slowspr_done_offset :natural := lsu_slowspr_data_offset + 2**REGMODE; +constant mm_slowspr_val_offset :natural := lsu_slowspr_done_offset + 1; +constant mm_slowspr_rw_offset :natural := mm_slowspr_val_offset + 1; +constant mm_slowspr_etid_offset :natural := mm_slowspr_rw_offset + 1; +constant mm_slowspr_addr_offset :natural := mm_slowspr_etid_offset + 2; +constant mm_slowspr_data_offset :natural := mm_slowspr_addr_offset + 10; +constant mm_slowspr_done_offset :natural := mm_slowspr_data_offset + 2**REGMODE; +constant ex1_th_fld_c_offset :natural := mm_slowspr_done_offset + 1; +constant ex3_th_fld_c_offset :natural := ex1_th_fld_c_offset + 1; +constant ex1_th_fld_l2_offset :natural := ex3_th_fld_c_offset + 1; +constant ex3_th_fld_l2_offset :natural := ex1_th_fld_l2_offset + 1; +constant ex1_dcbtls_instr_offset :natural := ex3_th_fld_l2_offset + 1; +constant ex3_dcbtls_instr_offset :natural := ex1_dcbtls_instr_offset + 1; +constant ex3_l2_request_offset :natural := ex3_dcbtls_instr_offset + 1; +constant ex1_dcbtstls_instr_offset :natural := ex3_l2_request_offset + 1; +constant ex3_dcbtstls_instr_offset :natural := ex1_dcbtstls_instr_offset + 1; +constant ex1_dcblc_instr_offset :natural := ex3_dcbtstls_instr_offset + 1; +constant ex3_dcblc_instr_offset :natural := ex1_dcblc_instr_offset + 1; +constant ex1_icblc_l2_instr_offset :natural := ex3_dcblc_instr_offset + 1; +constant ex3_icblc_l2_instr_offset :natural := ex1_icblc_l2_instr_offset + 1; +constant ex1_icbt_l2_instr_offset :natural := ex3_icblc_l2_instr_offset + 1; +constant ex3_icbt_l2_instr_offset :natural := ex1_icbt_l2_instr_offset + 1; +constant ex1_icbtls_l2_instr_offset :natural := ex3_icbt_l2_instr_offset + 1; +constant ex3_icbtls_l2_instr_offset :natural := ex1_icbtls_l2_instr_offset + 1; +constant ex1_tlbsync_instr_offset :natural := ex3_icbtls_l2_instr_offset + 1; +constant ex2_tlbsync_instr_offset :natural := ex1_tlbsync_instr_offset + 1; +constant ex3_tlbsync_instr_offset :natural := ex2_tlbsync_instr_offset + 1; +constant ex1_src0_vld_offset :natural := ex3_tlbsync_instr_offset + 1; +constant ex1_src0_reg_offset :natural := ex1_src0_vld_offset + 1; +constant ex1_src1_vld_offset :natural := ex1_src0_reg_offset + 8; +constant ex1_src1_reg_offset :natural := ex1_src1_vld_offset + 1; +constant ex1_targ_vld_offset :natural := ex1_src1_reg_offset + 8; +constant ex1_targ_reg_offset :natural := ex1_targ_vld_offset + 1; +constant ex5_instr_val_offset :natural := ex1_targ_reg_offset + 8; +constant ex2_targ_match_b1_offset :natural := ex5_instr_val_offset + 1; +constant ex3_targ_match_b1_offset :natural := ex2_targ_match_b1_offset + 1; +constant ex4_targ_match_b1_offset :natural := ex3_targ_match_b1_offset + 1; +constant ex5_targ_match_b1_offset :natural := ex4_targ_match_b1_offset + 1; +constant ex6_targ_match_b1_offset :natural := ex5_targ_match_b1_offset + 1; +constant ex2_targ_match_b2_offset :natural := ex6_targ_match_b1_offset + 1; +constant ex3_targ_match_b2_offset :natural := ex2_targ_match_b2_offset + 1; +constant ex4_targ_match_b2_offset :natural := ex3_targ_match_b2_offset + 1; +constant ex5_targ_match_b2_offset :natural := ex4_targ_match_b2_offset + 1; +constant ex7_targ_match_offset :natural := ex5_targ_match_b2_offset + 1; +constant ex8_targ_match_offset :natural := ex7_targ_match_offset + 1; +constant ex1_ldst_falign_offset :natural := ex8_targ_match_offset + 1; +constant ex1_ldst_fexcpt_offset :natural := ex1_ldst_falign_offset + 1; +constant ex5_load_miss_offset :natural := ex1_ldst_fexcpt_offset + 1; +constant xucr2_reg_a_offset :natural := ex5_load_miss_offset + 1; +constant xucr2_reg_b_offset :natural := xucr2_reg_a_offset + 16; +constant dvc1_act_offset :natural := xucr2_reg_b_offset + 16; +constant dvc2_act_offset :natural := dvc1_act_offset + 1; +constant dvc1_reg_offset :natural := dvc2_act_offset + 1; +constant dvc2_reg_offset :natural := dvc1_reg_offset + 2**REGMODE; +constant xudbg0_reg_offset :natural := dvc2_reg_offset + 2**REGMODE; +constant xudbg0_done_reg_offset :natural := xudbg0_reg_offset + 8; +constant xudbg1_dir_reg_offset :natural := xudbg0_done_reg_offset + 1; +constant xudbg1_parity_reg_offset :natural := xudbg1_dir_reg_offset + 13; +constant xudbg2_reg_offset :natural := xudbg1_parity_reg_offset + parBits; +constant ex4_store_commit_offset :natural := xudbg2_reg_offset + 31; +constant ex1_sgpr_instr_offset :natural := ex4_store_commit_offset + 1; +constant ex1_saxu_instr_offset :natural := ex1_sgpr_instr_offset + 1; +constant ex1_sdp_instr_offset :natural := ex1_saxu_instr_offset + 1; +constant ex1_tgpr_instr_offset :natural := ex1_sdp_instr_offset + 1; +constant ex1_taxu_instr_offset :natural := ex1_tgpr_instr_offset + 1; +constant ex1_tdp_instr_offset :natural := ex1_taxu_instr_offset + 1; +constant ex2_tgpr_instr_offset :natural := ex1_tdp_instr_offset + 1; +constant ex2_taxu_instr_offset :natural := ex2_tgpr_instr_offset + 1; +constant ex2_tdp_instr_offset :natural := ex2_taxu_instr_offset + 1; +constant ex3_tgpr_instr_offset :natural := ex2_tdp_instr_offset + 1; +constant ex3_taxu_instr_offset :natural := ex3_tgpr_instr_offset + 1; +constant ex4_tgpr_instr_offset :natural := ex3_taxu_instr_offset + 1; +constant ex4_taxu_instr_offset :natural := ex4_tgpr_instr_offset + 1; +constant ex3_blkable_touch_offset :natural := ex4_taxu_instr_offset + 1; +constant ex3_p_addr_lwr_offset :natural := ex3_blkable_touch_offset + 1; +constant ex5_p_addr_offset :natural := ex3_p_addr_lwr_offset + 12; +constant eplc_wr_offset :natural := ex5_p_addr_offset + real_data_add-6; +constant epsc_wr_offset :natural := eplc_wr_offset + 4; +constant eplc_t0_reg_a_offset :natural := epsc_wr_offset + 4; +constant eplc_t0_reg_b_offset :natural := eplc_t0_reg_a_offset + 2; +constant eplc_t0_reg_c_offset :natural := eplc_t0_reg_b_offset + 9; +constant eplc_t1_reg_a_offset :natural := eplc_t0_reg_c_offset + 14; +constant eplc_t1_reg_b_offset :natural := eplc_t1_reg_a_offset + 2; +constant eplc_t1_reg_c_offset :natural := eplc_t1_reg_b_offset + 9; +constant eplc_t2_reg_a_offset :natural := eplc_t1_reg_c_offset + 14; +constant eplc_t2_reg_b_offset :natural := eplc_t2_reg_a_offset + 2; +constant eplc_t2_reg_c_offset :natural := eplc_t2_reg_b_offset + 9; +constant eplc_t3_reg_a_offset :natural := eplc_t2_reg_c_offset + 14; +constant eplc_t3_reg_b_offset :natural := eplc_t3_reg_a_offset + 2; +constant eplc_t3_reg_c_offset :natural := eplc_t3_reg_b_offset + 9; +constant epsc_t0_reg_a_offset :natural := eplc_t3_reg_c_offset + 14; +constant epsc_t0_reg_b_offset :natural := epsc_t0_reg_a_offset + 2; +constant epsc_t0_reg_c_offset :natural := epsc_t0_reg_b_offset + 9; +constant epsc_t1_reg_a_offset :natural := epsc_t0_reg_c_offset + 14; +constant epsc_t1_reg_b_offset :natural := epsc_t1_reg_a_offset + 2; +constant epsc_t1_reg_c_offset :natural := epsc_t1_reg_b_offset + 9; +constant epsc_t2_reg_a_offset :natural := epsc_t1_reg_c_offset + 14; +constant epsc_t2_reg_b_offset :natural := epsc_t2_reg_a_offset + 2; +constant epsc_t2_reg_c_offset :natural := epsc_t2_reg_b_offset + 9; +constant epsc_t3_reg_a_offset :natural := epsc_t2_reg_c_offset + 14; +constant epsc_t3_reg_b_offset :natural := epsc_t3_reg_a_offset + 2; +constant epsc_t3_reg_c_offset :natural := epsc_t3_reg_b_offset + 9; +constant ex2_undef_lockset_offset :natural := epsc_t3_reg_c_offset + 14; +constant ex3_undef_lockset_offset :natural := ex2_undef_lockset_offset + 1; +constant ex4_unable_2lock_offset :natural := ex3_undef_lockset_offset + 1; +constant ex5_unable_2lock_offset :natural := ex4_unable_2lock_offset + 1; +constant ex3_ldstq_instr_offset :natural := ex5_unable_2lock_offset + 1; +constant ex5_store_instr_offset :natural := ex3_ldstq_instr_offset + 1; +constant ex5_store_miss_offset :natural := ex5_store_instr_offset + 1; +constant ex5_perf_dcbt_offset :natural := ex5_store_miss_offset + 1; +constant perf_lsu_events_offset :natural := ex5_perf_dcbt_offset + 1; +constant clkg_ctl_override_offset :natural := perf_lsu_events_offset + 17; +constant spr_xucr0_wlck_offset :natural := clkg_ctl_override_offset + 1; +constant spr_xucr0_wlck_cpy_offset :natural := spr_xucr0_wlck_offset + 1; +constant spr_xucr0_flh2l2_offset :natural := spr_xucr0_wlck_cpy_offset + 1; +constant ex3_spr_xucr0_flh2l2_offset :natural := spr_xucr0_flh2l2_offset + 1; +constant spr_xucr0_dcdis_offset :natural := ex3_spr_xucr0_flh2l2_offset + 1; +constant spr_xucr0_cls_offset :natural := spr_xucr0_dcdis_offset + 1; +constant agen_xucr0_cls_dly_offset :natural := spr_xucr0_cls_offset + 1; +constant agen_xucr0_cls_offset :natural := agen_xucr0_cls_dly_offset + 1; +constant mtspr_trace_en_offset :natural := agen_xucr0_cls_offset + 1; +constant ex3_local_dcbf_offset :natural := mtspr_trace_en_offset + 4; +constant ex1_msgsnd_instr_offset :natural := ex3_local_dcbf_offset + 1; +constant ex2_msgsnd_instr_offset :natural := ex1_msgsnd_instr_offset + 1; +constant ex3_msgsnd_instr_offset :natural := ex2_msgsnd_instr_offset + 1; +constant ex1_dci_instr_offset :natural := ex3_msgsnd_instr_offset + 1; +constant ex2_dci_instr_offset :natural := ex1_dci_instr_offset + 1; +constant ex3_dci_instr_offset :natural := ex2_dci_instr_offset + 1; +constant ex1_ici_instr_offset :natural := ex3_dci_instr_offset + 1; +constant ex2_ici_instr_offset :natural := ex1_ici_instr_offset + 1; +constant ex3_ici_instr_offset :natural := ex2_ici_instr_offset + 1; +constant ex3_load_type_offset :natural := ex3_ici_instr_offset + 1; +constant ex3_l2load_type_offset :natural := ex3_load_type_offset + 1; +constant flh2l2_gate_offset :natural := ex3_l2load_type_offset + 1; +constant rel_upd_dcarr_offset :natural := flh2l2_gate_offset + 1; +constant ex5_xu_wren_offset :natural := rel_upd_dcarr_offset + 1; +constant ex1_ldawx_instr_offset :natural := ex5_xu_wren_offset + 1; +constant ex3_watch_en_offset :natural := ex1_ldawx_instr_offset + 1; +constant ex5_watch_en_offset :natural := ex3_watch_en_offset + 1; +constant ex1_wclr_instr_offset :natural := ex5_watch_en_offset + 1; +constant ex3_wclr_instr_offset :natural := ex1_wclr_instr_offset + 1; +constant ex5_wclr_instr_offset :natural := ex3_wclr_instr_offset + 1; +constant ex5_wclr_set_offset :natural := ex5_wclr_instr_offset + 1; +constant ex1_wchk_instr_offset :natural := ex5_wclr_set_offset + 1; +constant ex4_cacheable_linelock_offset :natural := ex1_wchk_instr_offset + 1; +constant ex1_icswx_instr_offset :natural := ex4_cacheable_linelock_offset + 1; +constant ex3_icswx_instr_offset :natural := ex1_icswx_instr_offset + 1; +constant ex1_icswx_dot_instr_offset :natural := ex3_icswx_instr_offset + 1; +constant ex3_icswx_dot_instr_offset :natural := ex1_icswx_dot_instr_offset + 1; +constant ex1_icswx_epid_offset :natural := ex3_icswx_dot_instr_offset + 1; +constant ex3_icswx_epid_offset :natural := ex1_icswx_epid_offset + 1; +constant ex3_c_inh_drop_op_offset :natural := ex3_icswx_epid_offset + 1; +constant axu_rel_wren_offset :natural := ex3_c_inh_drop_op_offset + 1; +constant axu_rel_wren_stg1_offset :natural := axu_rel_wren_offset + 1; +constant rel_axu_tid_offset :natural := axu_rel_wren_stg1_offset + 1; +constant rel_axu_tid_stg1_offset :natural := rel_axu_tid_offset + 4; +constant rel_axu_ta_gpr_offset :natural := rel_axu_tid_stg1_offset + 4; +constant rel_axu_ta_gpr_stg1_offset :natural := rel_axu_ta_gpr_offset + 9; +constant rf0_l2_inv_val_offset :natural := rel_axu_ta_gpr_stg1_offset + 9; +constant rf1_l2_inv_val_offset :natural := rf0_l2_inv_val_offset + 1; +constant ex1_agen_binv_val_offset :natural := rf1_l2_inv_val_offset + 1; +constant ex1_l2_inv_val_offset :natural := ex1_agen_binv_val_offset + 1; +constant lsu_msr_gs_offset :natural := ex1_l2_inv_val_offset + 1; +constant lsu_msr_pr_offset :natural := lsu_msr_gs_offset + 4; +constant lsu_msr_cm_offset :natural := lsu_msr_pr_offset + 4; +constant ex1_lsu_64bit_agen_offset :natural := lsu_msr_cm_offset + 4; +constant ex6_icbi_val_offset :natural := ex1_lsu_64bit_agen_offset + 1; +constant ex1_mtspr_trace_offset :natural := ex6_icbi_val_offset + 4; +constant ex2_mtspr_trace_offset :natural := ex1_mtspr_trace_offset + 1; +constant ex3_mtspr_trace_offset :natural := ex2_mtspr_trace_offset + 1; +constant ex3_byte_en_offset :natural := ex3_mtspr_trace_offset + 1; +constant ex3_rot_sel_le_offset :natural := ex3_byte_en_offset + 32; +constant ex3_rot_sel_be_offset :natural := ex3_rot_sel_le_offset + 5; +constant dir_arr_rd_val_offset :natural := ex3_rot_sel_be_offset + 5; +constant dir_arr_rd_is0_val_offset :natural := dir_arr_rd_val_offset + 1; +constant dir_arr_rd_is1_val_offset :natural := dir_arr_rd_is0_val_offset + 1; +constant dir_arr_rd_is2_val_offset :natural := dir_arr_rd_is1_val_offset + 1; +constant dir_arr_rd_rf0_val_offset :natural := dir_arr_rd_is2_val_offset + 1; +constant dir_arr_rd_rf1_val_offset :natural := dir_arr_rd_rf0_val_offset + 1; +constant dir_arr_rd_rf0_done_offset :natural := dir_arr_rd_rf1_val_offset + 1; +constant dir_arr_rd_rf1_done_offset :natural := dir_arr_rd_rf0_done_offset + 1; +constant dir_arr_rd_ex1_done_offset :natural := dir_arr_rd_rf1_done_offset + 1; +constant dir_arr_rd_ex2_done_offset :natural := dir_arr_rd_ex1_done_offset + 1; +constant dir_arr_rd_ex3_done_offset :natural := dir_arr_rd_ex2_done_offset + 1; +constant dir_arr_rd_ex4_done_offset :natural := dir_arr_rd_ex3_done_offset + 1; +constant my_spare0_latches_offset :natural := dir_arr_rd_ex4_done_offset + 1; +constant my_spare1_latches_offset :natural := my_spare0_latches_offset + 3; +constant rf1_stg_act_offset :natural := my_spare1_latches_offset + 20; +constant ex1_stg_act_offset :natural := rf1_stg_act_offset + 1; +constant ex3_stg_act_offset :natural := ex1_stg_act_offset + 1; +constant ex5_stg_act_offset :natural := ex3_stg_act_offset + 1; +constant binv1_stg_act_offset :natural := ex5_stg_act_offset + 1; +constant binv3_stg_act_offset :natural := binv1_stg_act_offset + 1; +constant binv5_stg_act_offset :natural := binv3_stg_act_offset + 1; +constant rel1_stg_act_offset :natural := binv5_stg_act_offset + 1; +constant rel3_stg_act_offset :natural := rel1_stg_act_offset + 1; +constant scan_right :natural := rel3_stg_act_offset + 1 - 1; + +constant XUCR2_ADDR :std_ulogic_vector(0 to 9) := "11" & x"F8"; +constant XUDBG0_ADDR :std_ulogic_vector(0 to 9) := "11" & x"75"; +constant XUDBG1_ADDR :std_ulogic_vector(0 to 9) := "11" & x"76"; +constant XUDBG2_ADDR :std_ulogic_vector(0 to 9) := "11" & x"77"; +constant DVC1_ADDR :std_ulogic_vector(0 to 9) := "01" & x"3E"; +constant DVC2_ADDR :std_ulogic_vector(0 to 9) := "01" & x"3F"; +constant EPLC_ADDR :std_ulogic_vector(0 to 9) := "11" & x"B3"; +constant EPSC_ADDR :std_ulogic_vector(0 to 9) := "11" & x"B4"; + +signal ex1_optype1_d :std_ulogic; +signal ex2_optype1_d :std_ulogic; +signal ex1_optype2_d :std_ulogic; +signal ex2_optype2_d :std_ulogic; +signal ex1_optype4_d :std_ulogic; +signal ex2_optype4_d :std_ulogic; +signal ex1_optype8_d :std_ulogic; +signal ex2_optype8_d :std_ulogic; +signal ex1_optype16_d :std_ulogic; +signal ex2_optype16_d :std_ulogic; +signal ex1_optype32_d :std_ulogic; +signal ex2_optype32_d :std_ulogic; +signal ex1_dir_acc_val_d :std_ulogic; +signal ex1_dir_acc_val_q :std_ulogic; +signal cache_acc_ex1_d :std_ulogic; +signal cache_acc_ex2_d :std_ulogic; +signal cache_acc_ex3_d :std_ulogic; +signal cache_acc_ex4_d :std_ulogic; +signal cache_acc_ex5_d :std_ulogic; +signal ex2_cacc_d :std_ulogic; +signal ex2_cacc_q :std_ulogic; +signal ex3_cacc_d :std_ulogic; +signal ex3_cacc_q :std_ulogic; +signal ex1_thrd_id_d :std_ulogic_vector(0 to 3); +signal ex2_thrd_id_d :std_ulogic_vector(0 to 3); +signal ex3_thrd_id_d :std_ulogic_vector(0 to 3); +signal ex4_thrd_id_d :std_ulogic_vector(0 to 3); +signal ex5_thrd_id_d :std_ulogic_vector(0 to 3); +signal ex1_target_gpr_d :std_ulogic_vector(0 to 8); +signal ex2_target_gpr_d :std_ulogic_vector(0 to 8); +signal ex3_target_gpr_d :std_ulogic_vector(0 to 8); +signal ex4_target_gpr_d :std_ulogic_vector(0 to 8); +signal ex1_dcbt_instr_d :std_ulogic; +signal ex2_dcbt_instr_d :std_ulogic; +signal ex3_dcbt_instr_d :std_ulogic; +signal ex1_dcbtst_instr_d :std_ulogic; +signal ex2_dcbtst_instr_d :std_ulogic; +signal ex3_dcbtst_instr_d :std_ulogic; +signal ex1_dcbst_instr_d :std_ulogic; +signal ex2_dcbst_instr_d :std_ulogic; +signal ex3_dcbst_instr_d :std_ulogic; +signal ex1_dcbf_instr_d :std_ulogic; +signal ex2_dcbf_instr_d :std_ulogic; +signal ex3_dcbf_instr_d :std_ulogic; +signal ex1_sync_instr_d :std_ulogic; +signal ex2_sync_instr_d :std_ulogic; +signal ex3_sync_instr_d :std_ulogic; +signal ex1_l_fld_d :std_ulogic_vector(0 to 1); +signal ex2_l_fld_d :std_ulogic_vector(0 to 1); +signal ex3_l_fld_d :std_ulogic_vector(0 to 1); +signal ex1_dcbi_instr_d :std_ulogic; +signal ex2_dcbi_instr_d :std_ulogic; +signal ex3_dcbi_instr_d :std_ulogic; +signal ex1_dcbz_instr_d :std_ulogic; +signal ex2_dcbz_instr_d :std_ulogic; +signal ex3_dcbz_instr_d :std_ulogic; +signal ex1_icbi_instr_d :std_ulogic; +signal ex2_icbi_instr_d :std_ulogic; +signal ex3_icbi_instr_d :std_ulogic; +signal ex4_icbi_instr_d :std_ulogic; +signal ex5_icbi_instr_d :std_ulogic; +signal ex1_mbar_instr_d :std_ulogic; +signal ex2_mbar_instr_d :std_ulogic; +signal ex3_mbar_instr_d :std_ulogic; +signal ex1_lock_instr_d :std_ulogic; +signal ex2_lock_instr_d :std_ulogic; +signal ex3_lock_instr_d :std_ulogic; +signal ex4_lock_instr_d :std_ulogic; +signal ex5_lock_instr_d :std_ulogic; +signal ex1_load_instr_d :std_ulogic; +signal ex2_load_instr_d :std_ulogic; +signal ex3_load_instr_d :std_ulogic; +signal ex4_load_instr_d :std_ulogic; +signal ex5_load_instr_d :std_ulogic; +signal ex3_load_type_d :std_ulogic; +signal ex3_load_type_q :std_ulogic; +signal ex4_load_type_d :std_ulogic; +signal ex4_load_type_q :std_ulogic; +signal ex1_store_instr_d :std_ulogic; +signal ex2_store_instr_d :std_ulogic; +signal ex3_store_instr_d :std_ulogic; +signal ex1_optype1_q :std_ulogic; +signal ex2_optype1_q :std_ulogic; +signal ex1_optype2_q :std_ulogic; +signal ex2_optype2_q :std_ulogic; +signal ex1_optype4_q :std_ulogic; +signal ex2_optype4_q :std_ulogic; +signal ex1_optype8_q :std_ulogic; +signal ex2_optype8_q :std_ulogic; +signal ex1_optype16_q :std_ulogic; +signal ex2_optype16_q :std_ulogic; +signal ex1_optype32_q :std_ulogic; +signal ex2_optype32_q :std_ulogic; +signal cache_acc_ex1_q :std_ulogic; +signal cache_acc_ex2_q :std_ulogic; +signal cache_acc_ex3_q :std_ulogic; +signal cache_acc_ex4_q :std_ulogic; +signal cache_acc_ex5_q :std_ulogic; +signal ex1_thrd_id_q :std_ulogic_vector(0 to 3); +signal ex2_thrd_id_q :std_ulogic_vector(0 to 3); +signal ex3_thrd_id_q :std_ulogic_vector(0 to 3); +signal ex4_thrd_id_q :std_ulogic_vector(0 to 3); +signal ex5_thrd_id_q :std_ulogic_vector(0 to 3); +signal ex1_target_gpr_q :std_ulogic_vector(0 to 8); +signal ex2_target_gpr_q :std_ulogic_vector(0 to 8); +signal ex3_target_gpr_q :std_ulogic_vector(0 to 8); +signal ex4_target_gpr_q :std_ulogic_vector(0 to 8); +signal ex1_dcbt_instr_q :std_ulogic; +signal ex2_dcbt_instr_q :std_ulogic; +signal ex3_dcbt_instr_q :std_ulogic; +signal ex1_dcbtst_instr_q :std_ulogic; +signal ex2_dcbtst_instr_q :std_ulogic; +signal ex3_dcbtst_instr_q :std_ulogic; +signal ex1_dcbst_instr_q :std_ulogic; +signal ex2_dcbst_instr_q :std_ulogic; +signal ex3_dcbst_instr_q :std_ulogic; +signal ex1_dcbf_instr_q :std_ulogic; +signal ex2_dcbf_instr_q :std_ulogic; +signal ex3_dcbf_instr_q :std_ulogic; +signal ex1_sync_instr_q :std_ulogic; +signal ex2_sync_instr_q :std_ulogic; +signal ex3_sync_instr_q :std_ulogic; +signal ex1_l_fld_q :std_ulogic_vector(0 to 1); +signal ex2_l_fld_q :std_ulogic_vector(0 to 1); +signal ex3_l_fld_q :std_ulogic_vector(0 to 1); +signal ex1_dcbi_instr_q :std_ulogic; +signal ex2_dcbi_instr_q :std_ulogic; +signal ex3_dcbi_instr_q :std_ulogic; +signal ex1_dcbz_instr_q :std_ulogic; +signal ex2_dcbz_instr_q :std_ulogic; +signal ex3_dcbz_instr_q :std_ulogic; +signal ex1_icbi_instr_q :std_ulogic; +signal ex2_icbi_instr_q :std_ulogic; +signal ex3_icbi_instr_q :std_ulogic; +signal ex4_icbi_instr_q :std_ulogic; +signal ex5_icbi_instr_q :std_ulogic; +signal ex5_icbi_instr :std_ulogic; +signal ex1_mbar_instr_q :std_ulogic; +signal ex2_mbar_instr_q :std_ulogic; +signal ex3_mbar_instr_q :std_ulogic; +signal ex1_lock_instr_q :std_ulogic; +signal ex2_lock_instr_q :std_ulogic; +signal ex3_lock_instr_q :std_ulogic; +signal ex4_lock_instr_q :std_ulogic; +signal ex5_lock_instr_q :std_ulogic; +signal ex1_load_instr_q :std_ulogic; +signal ex2_load_instr_q :std_ulogic; +signal ex3_load_instr_q :std_ulogic; +signal ex4_load_instr_q :std_ulogic; +signal ex5_load_instr_q :std_ulogic; +signal ex1_store_instr_q :std_ulogic; +signal ex2_store_instr_q :std_ulogic; +signal ex3_store_instr_q :std_ulogic; +signal ex4_cache_inh_d :std_ulogic; +signal ex4_cache_inh_q :std_ulogic; +signal ex5_cache_inh_d :std_ulogic; +signal ex5_cache_inh_q :std_ulogic; +signal l_s_q_val :std_ulogic; +signal stx_instr :std_ulogic; +signal larx_instr :std_ulogic; +signal is_mem_bar_op :std_ulogic; +signal is_inval_op :std_ulogic; +signal is_lock_set :std_ulogic; +signal ex3_l2_lock_set :std_ulogic; +signal ex3_c_dcbtls :std_ulogic; +signal ex3_c_dcbtstls :std_ulogic; +signal ex3_c_icbtls :std_ulogic; +signal ex3_l2_dcbtls :std_ulogic; +signal ex3_l2_dcbtstls :std_ulogic; +signal ex3_l2_icbtls :std_ulogic; +signal is_lock_clr :std_ulogic; +signal no_lru_upd :std_ulogic; +signal l2_ctype :std_ulogic; +signal reg_upd_thrd_id :std_ulogic_vector(0 to 3); +signal reg_upd_ta_gpr :std_ulogic_vector(0 to 8); +signal xu_wren :std_ulogic; +signal ex5_xu_wren_d :std_ulogic; +signal ex5_xu_wren_q :std_ulogic; +signal axu_wren :std_ulogic; +signal axu_rel_wren_d :std_ulogic; +signal axu_rel_wren_q :std_ulogic; +signal axu_rel_wren_stg1_d :std_ulogic; +signal axu_rel_wren_stg1_q :std_ulogic; +signal rel_thrd_id_d :std_ulogic_vector(0 to 3); +signal rel_thrd_id_q :std_ulogic_vector(0 to 3); +signal rel_ta_gpr_d :std_ulogic_vector(0 to 8); +signal rel_ta_gpr_q :std_ulogic_vector(0 to 8); +signal rel_upd_gpr_d :std_ulogic; +signal rel_upd_gpr_q :std_ulogic; +signal rel_axu_op_val_d :std_ulogic; +signal rel_axu_op_val_q :std_ulogic; +signal ex4_load_miss :std_ulogic; +signal ex5_load_miss_d :std_ulogic; +signal ex5_load_miss_q :std_ulogic; +signal ex3_l2_op_d :std_ulogic; +signal ex3_l2_op_q :std_ulogic; +signal ex4_load_hit :std_ulogic; +signal ex4_load_commit_d :std_ulogic; +signal ex4_load_commit_q :std_ulogic; +signal ex5_load_hit_d :std_ulogic; +signal ex5_load_hit_q :std_ulogic; +signal ex1_axu_op_val_d :std_ulogic; +signal ex1_axu_op_val_q :std_ulogic; +signal ex2_axu_op_val_d :std_ulogic; +signal ex2_axu_op_val_q :std_ulogic; +signal ex3_axu_op_val_d :std_ulogic; +signal ex3_axu_op_val_q :std_ulogic; +signal ex4_axu_op_val_d :std_ulogic; +signal ex4_axu_op_val_q :std_ulogic; +signal ex5_axu_op_val_d :std_ulogic; +signal ex5_axu_op_val_q :std_ulogic; +signal ex2_op_sel :std_ulogic_vector(0 to 15); +signal ex2_opsize :std_ulogic_vector(0 to 5); +signal ex3_opsize_d :std_ulogic_vector(0 to 5); +signal ex3_opsize_q :std_ulogic_vector(0 to 5); +signal ex5_axu_wren_d :std_ulogic_vector(0 to 3); +signal ex5_axu_wren_q :std_ulogic_vector(0 to 3); +signal ex5_axu_wren_val :std_ulogic; +signal ex5_axu_ta_gpr_d :std_ulogic_vector(0 to 8); +signal ex5_axu_ta_gpr_q :std_ulogic_vector(0 to 8); +signal rel_xu_ta_gpr_d :std_ulogic_vector(0 to 7); +signal rel_xu_ta_gpr_q :std_ulogic_vector(0 to 7); +signal ex1_algebraic_d :std_ulogic; +signal ex1_algebraic_q :std_ulogic; +signal ex2_algebraic_d :std_ulogic; +signal ex2_algebraic_q :std_ulogic; +signal ex3_algebraic_d :std_ulogic; +signal ex3_algebraic_q :std_ulogic; +signal ex1_byte_rev_d :std_ulogic; +signal ex1_byte_rev_q :std_ulogic; +signal ex2_byte_rev_d :std_ulogic; +signal ex2_byte_rev_q :std_ulogic; +signal ex3_byte_rev_d :std_ulogic; +signal ex3_byte_rev_q :std_ulogic; +signal lsu_slowspr_val_d :std_ulogic; +signal lsu_slowspr_rw_d :std_ulogic; +signal lsu_slowspr_etid_d :std_ulogic_vector(0 to 1); +signal lsu_slowspr_addr_d :std_ulogic_vector(0 to 9); +signal lsu_slowspr_data_d :std_ulogic_vector(64-(2**REGMODE) to 63); +signal lsu_slowspr_done_d :std_ulogic; +signal lsu_slowspr_val_q :std_ulogic; +signal lsu_slowspr_rw_q :std_ulogic; +signal lsu_slowspr_etid_q :std_ulogic_vector(0 to 1); +signal lsu_slowspr_addr_q :std_ulogic_vector(0 to 9); +signal lsu_slowspr_data_q :std_ulogic_vector(64-(2**REGMODE) to 63); +signal lsu_slowspr_done_q :std_ulogic; +signal mm_slowspr_val_d :std_ulogic; +signal mm_slowspr_rw_d :std_ulogic; +signal mm_slowspr_etid_d :std_ulogic_vector(0 to 1); +signal mm_slowspr_addr_d :std_ulogic_vector(0 to 9); +signal mm_slowspr_data_d :std_ulogic_vector(64-(2**REGMODE) to 63); +signal mm_slowspr_done_d :std_ulogic; +signal mm_slowspr_val_q :std_ulogic; +signal mm_slowspr_rw_q :std_ulogic; +signal mm_slowspr_etid_q :std_ulogic_vector(0 to 1); +signal mm_slowspr_addr_q :std_ulogic_vector(0 to 9); +signal mm_slowspr_data_q :std_ulogic_vector(64-(2**REGMODE) to 63); +signal mm_slowspr_done_q :std_ulogic; +signal ex3_nogpr_upd :std_ulogic; +signal rf1_th_b0 :std_ulogic; +signal ex1_th_fld_c_d :std_ulogic; +signal ex1_th_fld_c_q :std_ulogic; +signal ex2_th_fld_c_d :std_ulogic; +signal ex2_th_fld_c_q :std_ulogic; +signal ex3_th_fld_c_d :std_ulogic; +signal ex3_th_fld_c_q :std_ulogic; +signal ex1_th_fld_l2_d :std_ulogic; +signal ex1_th_fld_l2_q :std_ulogic; +signal ex2_th_fld_l2_d :std_ulogic; +signal ex2_th_fld_l2_q :std_ulogic; +signal ex3_th_fld_l2_d :std_ulogic; +signal ex3_th_fld_l2_q :std_ulogic; +signal ex1_undef_touch :std_ulogic; +signal ex1_dcbtls_instr_d :std_ulogic; +signal ex1_dcbtls_instr_q :std_ulogic; +signal ex2_dcbtls_instr_d :std_ulogic; +signal ex2_dcbtls_instr_q :std_ulogic; +signal ex3_dcbtls_instr_d :std_ulogic; +signal ex3_dcbtls_instr_q :std_ulogic; +signal ex1_dcbtstls_instr_d :std_ulogic; +signal ex1_dcbtstls_instr_q :std_ulogic; +signal ex2_dcbtstls_instr_d :std_ulogic; +signal ex2_dcbtstls_instr_q :std_ulogic; +signal ex3_dcbtstls_instr_d :std_ulogic; +signal ex3_dcbtstls_instr_q :std_ulogic; +signal ex1_dcblc_instr_d :std_ulogic; +signal ex1_dcblc_instr_q :std_ulogic; +signal ex2_dcblc_instr_d :std_ulogic; +signal ex2_dcblc_instr_q :std_ulogic; +signal ex3_dcblc_instr_d :std_ulogic; +signal ex3_dcblc_instr_q :std_ulogic; +signal ex1_icblc_l2_instr_d :std_ulogic; +signal ex1_icblc_l2_instr_q :std_ulogic; +signal ex2_icblc_l2_instr_d :std_ulogic; +signal ex2_icblc_l2_instr_q :std_ulogic; +signal ex3_icblc_l2_instr_d :std_ulogic; +signal ex3_icblc_l2_instr_q :std_ulogic; +signal ex1_icbt_l2_instr_d :std_ulogic; +signal ex1_icbt_l2_instr_q :std_ulogic; +signal ex2_icbt_l2_instr_d :std_ulogic; +signal ex2_icbt_l2_instr_q :std_ulogic; +signal ex3_icbt_l2_instr_d :std_ulogic; +signal ex3_icbt_l2_instr_q :std_ulogic; +signal ex1_icbtls_l2_instr_d :std_ulogic; +signal ex1_icbtls_l2_instr_q :std_ulogic; +signal ex2_icbtls_l2_instr_d :std_ulogic; +signal ex2_icbtls_l2_instr_q :std_ulogic; +signal ex3_icbtls_l2_instr_d :std_ulogic; +signal ex3_icbtls_l2_instr_q :std_ulogic; +signal ex1_tlbsync_instr_d :std_ulogic; +signal ex1_tlbsync_instr_q :std_ulogic; +signal ex2_tlbsync_instr_d :std_ulogic; +signal ex2_tlbsync_instr_q :std_ulogic; +signal ex3_tlbsync_instr_d :std_ulogic; +signal ex3_tlbsync_instr_q :std_ulogic; +signal ex1_src0_vld_d :std_ulogic; +signal ex1_src0_vld_q :std_ulogic; +signal ex1_src0_reg_d :std_ulogic_vector(0 to 7); +signal ex1_src0_reg_q :std_ulogic_vector(0 to 7); +signal ex1_src1_vld_d :std_ulogic; +signal ex1_src1_vld_q :std_ulogic; +signal ex1_src1_reg_d :std_ulogic_vector(0 to 7); +signal ex1_src1_reg_q :std_ulogic_vector(0 to 7); +signal ex1_targ_vld_d :std_ulogic; +signal ex1_targ_vld_q :std_ulogic; +signal ex1_targ_reg_d :std_ulogic_vector(0 to 7); +signal ex1_targ_reg_q :std_ulogic_vector(0 to 7); +signal ex5_instr_val_d :std_ulogic; +signal ex5_instr_val_q :std_ulogic; +signal ex2_targ_match_b1_d :std_ulogic; +signal ex2_targ_match_b1_q :std_ulogic; +signal ex3_targ_match_b1_d :std_ulogic; +signal ex3_targ_match_b1_q :std_ulogic; +signal ex4_targ_match_b1_d :std_ulogic; +signal ex4_targ_match_b1_q :std_ulogic; +signal ex5_targ_match_b1_d :std_ulogic; +signal ex5_targ_match_b1_q :std_ulogic; +signal ex6_targ_match_b1_d :std_ulogic; +signal ex6_targ_match_b1_q :std_ulogic; +signal ex2_targ_match_b2_d :std_ulogic; +signal ex2_targ_match_b2_q :std_ulogic; +signal ex3_targ_match_b2_d :std_ulogic; +signal ex3_targ_match_b2_q :std_ulogic; +signal ex4_targ_match_b2_d :std_ulogic; +signal ex4_targ_match_b2_q :std_ulogic; +signal ex5_targ_match_b2_d :std_ulogic; +signal ex5_targ_match_b2_q :std_ulogic; +signal ex7_targ_match_d :std_ulogic; +signal ex7_targ_match_q :std_ulogic; +signal ex8_targ_match_d :std_ulogic; +signal ex8_targ_match_q :std_ulogic; +signal ex3_l2_request_d :std_ulogic; +signal ex3_l2_request_q :std_ulogic; +signal ex1_ldst_falign_d :std_ulogic; +signal ex1_ldst_falign_q :std_ulogic; +signal ex1_ldst_fexcpt_d :std_ulogic; +signal ex1_ldst_fexcpt_q :std_ulogic; +signal ex2_ldst_fexcpt_d :std_ulogic; +signal ex2_ldst_fexcpt_q :std_ulogic; +signal xucr2_sel :std_ulogic; +signal dvc1_sel :std_ulogic; +signal dvc2_sel :std_ulogic; +signal eplc_sel :std_ulogic; +signal epsc_sel :std_ulogic; +signal xudbg0_sel :std_ulogic; +signal xudbg1_sel :std_ulogic; +signal xudbg2_sel :std_ulogic; +signal xucr2_wen :std_ulogic; +signal dvc1_wen :std_ulogic; +signal dvc1_act_d :std_ulogic; +signal dvc1_act_q :std_ulogic; +signal dvc2_wen :std_ulogic; +signal dvc2_act_d :std_ulogic; +signal dvc2_act_q :std_ulogic; +signal xudbg0_wen :std_ulogic; +signal eplc_t0_wen :std_ulogic; +signal eplc_t0_hyp_wen :std_ulogic; +signal eplc_t1_wen :std_ulogic; +signal eplc_t1_hyp_wen :std_ulogic; +signal eplc_t2_wen :std_ulogic; +signal eplc_t2_hyp_wen :std_ulogic; +signal eplc_t3_wen :std_ulogic; +signal eplc_t3_hyp_wen :std_ulogic; +signal epsc_t0_wen :std_ulogic; +signal epsc_t0_hyp_wen :std_ulogic; +signal epsc_t1_wen :std_ulogic; +signal epsc_t1_hyp_wen :std_ulogic; +signal epsc_t2_wen :std_ulogic; +signal epsc_t2_hyp_wen :std_ulogic; +signal epsc_t3_wen :std_ulogic; +signal epsc_t3_hyp_wen :std_ulogic; +signal xucr2_reg :std_ulogic_vector((64-(2**REGMODE)) to 63); +signal xucr2_reg_d :std_ulogic_vector(0 to 31); +signal xucr2_reg_q :std_ulogic_vector(0 to 31); +signal dvc1_reg :std_ulogic_vector((64-(2**REGMODE)) to 63); +signal dvc1_reg_d :std_ulogic_vector((64-(2**REGMODE)) to 63); +signal dvc1_reg_q :std_ulogic_vector((64-(2**REGMODE)) to 63); +signal dvc2_reg :std_ulogic_vector((64-(2**REGMODE)) to 63); +signal dvc2_reg_d :std_ulogic_vector((64-(2**REGMODE)) to 63); +signal dvc2_reg_q :std_ulogic_vector((64-(2**REGMODE)) to 63); +signal xudbg0_reg :std_ulogic_vector((64-(2**REGMODE)) to 63); +signal xudbg0_reg_d :std_ulogic_vector(0 to 7); +signal xudbg0_reg_q :std_ulogic_vector(0 to 7); +signal xudbg0_done_reg_d :std_ulogic; +signal xudbg0_done_reg_q :std_ulogic; +signal xudbg1_reg :std_ulogic_vector((64-(2**REGMODE)) to 63); +signal xudbg1_dir_reg_d :std_ulogic_vector(0 to 12); +signal xudbg1_dir_reg_q :std_ulogic_vector(0 to 12); +signal xudbg1_parity_reg_d :std_ulogic_vector(0 to parBits-1); +signal xudbg1_parity_reg_q :std_ulogic_vector(0 to parBits-1); +signal xudbg2_reg :std_ulogic_vector((64-(2**REGMODE)) to 63); +signal xudbg2_reg_d :std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); +signal xudbg2_reg_q :std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); +signal eplc_t0_reg :std_ulogic_vector(0 to 24); +signal eplc_t0_reg_d :std_ulogic_vector(0 to 24); +signal eplc_t0_reg_q :std_ulogic_vector(0 to 24); +signal eplc_t1_reg :std_ulogic_vector(0 to 24); +signal eplc_t1_reg_d :std_ulogic_vector(0 to 24); +signal eplc_t1_reg_q :std_ulogic_vector(0 to 24); +signal eplc_t2_reg :std_ulogic_vector(0 to 24); +signal eplc_t2_reg_d :std_ulogic_vector(0 to 24); +signal eplc_t2_reg_q :std_ulogic_vector(0 to 24); +signal eplc_t3_reg :std_ulogic_vector(0 to 24); +signal eplc_t3_reg_d :std_ulogic_vector(0 to 24); +signal eplc_t3_reg_q :std_ulogic_vector(0 to 24); +signal epsc_t0_reg :std_ulogic_vector(0 to 24); +signal epsc_t0_reg_d :std_ulogic_vector(0 to 24); +signal epsc_t0_reg_q :std_ulogic_vector(0 to 24); +signal epsc_t1_reg :std_ulogic_vector(0 to 24); +signal epsc_t1_reg_d :std_ulogic_vector(0 to 24); +signal epsc_t1_reg_q :std_ulogic_vector(0 to 24); +signal epsc_t2_reg :std_ulogic_vector(0 to 24); +signal epsc_t2_reg_d :std_ulogic_vector(0 to 24); +signal epsc_t2_reg_q :std_ulogic_vector(0 to 24); +signal epsc_t3_reg :std_ulogic_vector(0 to 24); +signal epsc_t3_reg_d :std_ulogic_vector(0 to 24); +signal epsc_t3_reg_q :std_ulogic_vector(0 to 24); +signal eplc_thrd_reg :std_ulogic_vector(0 to 24); +signal epsc_thrd_reg :std_ulogic_vector(0 to 24); +signal eplc_reg :std_ulogic_vector((64-(2**REGMODE)) to 63); +signal epsc_reg :std_ulogic_vector((64-(2**REGMODE)) to 63); +signal eplc_wrt_data :std_ulogic_vector(0 to 24); +signal epsc_wrt_data :std_ulogic_vector(0 to 24); +signal spr_l1dc_rd_val :std_ulogic; +signal spr_l1dc_reg :std_ulogic_vector((64-(2**REGMODE)) to 63); +signal way_lck_rmt :std_ulogic_vector(0 to 31); +signal clkg_ctl_override_d :std_ulogic; +signal clkg_ctl_override_q :std_ulogic; +signal spr_xucr0_wlck_d :std_ulogic; +signal spr_xucr0_wlck_q :std_ulogic; +signal spr_xucr0_wlck_cpy_d :std_ulogic; +signal spr_xucr0_wlck_cpy_q :std_ulogic; +signal spr_xucr0_flh2l2_d :std_ulogic; +signal spr_xucr0_flh2l2_q :std_ulogic; +signal ex2_spr_xucr0_flh2l2 :std_ulogic; +signal ex3_spr_xucr0_flh2l2_d :std_ulogic; +signal ex3_spr_xucr0_flh2l2_q :std_ulogic; +signal spr_xucr0_dcdis_d :std_ulogic; +signal spr_xucr0_dcdis_q :std_ulogic; +signal spr_xucr0_cls_d :std_ulogic; +signal spr_xucr0_cls_q :std_ulogic; +signal agen_xucr0_cls_d :std_ulogic; +signal agen_xucr0_cls_q :std_ulogic; +signal agen_xucr0_cls_dly_d :std_ulogic; +signal agen_xucr0_cls_dly_q :std_ulogic; +signal ex4_store_commit_d :std_ulogic; +signal ex4_store_commit_q :std_ulogic; +signal ex1_sgpr_instr_d :std_ulogic; +signal ex1_sgpr_instr_q :std_ulogic; +signal ex1_saxu_instr_d :std_ulogic; +signal ex1_saxu_instr_q :std_ulogic; +signal ex1_sdp_instr_d :std_ulogic; +signal ex1_sdp_instr_q :std_ulogic; +signal ex1_tgpr_instr_d :std_ulogic; +signal ex1_tgpr_instr_q :std_ulogic; +signal ex1_taxu_instr_d :std_ulogic; +signal ex1_taxu_instr_q :std_ulogic; +signal ex1_tdp_instr_d :std_ulogic; +signal ex1_tdp_instr_q :std_ulogic; +signal ex2_tgpr_instr_d :std_ulogic; +signal ex2_tgpr_instr_q :std_ulogic; +signal ex2_taxu_instr_d :std_ulogic; +signal ex2_taxu_instr_q :std_ulogic; +signal ex2_tdp_instr_d :std_ulogic; +signal ex2_tdp_instr_q :std_ulogic; +signal ex3_tgpr_instr_d :std_ulogic; +signal ex3_tgpr_instr_q :std_ulogic; +signal ex3_taxu_instr_d :std_ulogic; +signal ex3_taxu_instr_q :std_ulogic; +signal ex4_tgpr_instr_d :std_ulogic; +signal ex4_tgpr_instr_q :std_ulogic; +signal ex4_taxu_instr_d :std_ulogic; +signal ex4_taxu_instr_q :std_ulogic; +signal ex4_tgpr_instr :std_ulogic; +signal ex4_taxu_instr :std_ulogic; +signal ex2_dcblc_l1 :std_ulogic; +signal data_touch_op :std_ulogic; +signal inst_touch_op :std_ulogic; +signal all_touch_op :std_ulogic; +signal ddir_acc_instr :std_ulogic; +signal ex2_blkable_touch_d :std_ulogic; +signal ex2_blkable_touch_q :std_ulogic; +signal ex3_blkable_touch_d :std_ulogic; +signal ex3_blkable_touch_q :std_ulogic; +signal ex3_blk_touch :std_ulogic; +signal ex2_l2_dcbf :std_ulogic; +signal ex2_local_dcbf :std_ulogic; +signal ex1_mutex_hint_d :std_ulogic; +signal ex1_mutex_hint_q :std_ulogic; +signal ex2_mutex_hint_d :std_ulogic; +signal ex2_mutex_hint_q :std_ulogic; +signal ex3_mutex_hint_d :std_ulogic; +signal ex3_mutex_hint_q :std_ulogic; +signal ex3_p_addr_lwr_d :std_ulogic_vector(52 to 63); +signal ex3_p_addr_lwr_q :std_ulogic_vector(52 to 63); +signal ex4_p_addr_d :std_ulogic_vector(64-real_data_add to 63); +signal ex4_p_addr_q :std_ulogic_vector(64-real_data_add to 63); +signal ex5_p_addr_d :std_ulogic_vector(64-real_data_add to 57); +signal ex5_p_addr_q :std_ulogic_vector(64-real_data_add to 57); +signal ex6_p_addr_d :std_ulogic_vector(64-real_data_add to 57); +signal ex6_p_addr_q :std_ulogic_vector(64-real_data_add to 57); +signal eplc_wr_d :std_ulogic_vector(0 to 3); +signal eplc_wr_q :std_ulogic_vector(0 to 3); +signal epsc_wr_d :std_ulogic_vector(0 to 3); +signal epsc_wr_q :std_ulogic_vector(0 to 3); +signal ex1_lockset_instr :std_ulogic; +signal ex2_undef_lockset_d :std_ulogic; +signal ex2_undef_lockset_q :std_ulogic; +signal ex3_undef_lockset_d :std_ulogic; +signal ex3_undef_lockset_q :std_ulogic; +signal ex3_cinh_lockset :std_ulogic; +signal ex3_l1dcdis_lockset :std_ulogic; +signal ex4_unable_2lock_d :std_ulogic; +signal ex4_unable_2lock_q :std_ulogic; +signal ex5_unable_2lock_d :std_ulogic; +signal ex5_unable_2lock_q :std_ulogic; +signal ex3_ldstq_instr_d :std_ulogic; +signal ex3_ldstq_instr_q :std_ulogic; +signal ex4_store_instr_d :std_ulogic; +signal ex4_store_instr_q :std_ulogic; +signal ex5_store_instr_d :std_ulogic; +signal ex5_store_instr_q :std_ulogic; +signal ex4_store_miss :std_ulogic; +signal ex5_store_miss_d :std_ulogic; +signal ex5_store_miss_q :std_ulogic; +signal ex4_perf_dcbt_d :std_ulogic; +signal ex4_perf_dcbt_q :std_ulogic; +signal ex5_perf_dcbt_d :std_ulogic; +signal ex5_perf_dcbt_q :std_ulogic; +signal perf_com_stores :std_ulogic; +signal perf_com_store_miss :std_ulogic; +signal perf_com_stcx_exec :std_ulogic; +signal perf_com_loadmiss :std_ulogic; +signal perf_com_cinh_loads :std_ulogic; +signal perf_com_loads :std_ulogic; +signal perf_com_dcbt_sent :std_ulogic; +signal perf_com_dcbt_hit :std_ulogic; +signal perf_com_axu_load :std_ulogic; +signal perf_com_axu_store :std_ulogic; +signal perf_com_watch_clr :std_ulogic; +signal perf_com_wclr_lfld :std_ulogic; +signal perf_com_watch_set :std_ulogic; +signal perf_lsu_events_d :std_ulogic_vector(0 to 16); +signal perf_lsu_events_q :std_ulogic_vector(0 to 16); +signal ex3_local_dcbf_d :std_ulogic; +signal ex3_local_dcbf_q :std_ulogic; +signal ex1_msgsnd_instr_d :std_ulogic; +signal ex1_msgsnd_instr_q :std_ulogic; +signal ex2_msgsnd_instr_d :std_ulogic; +signal ex2_msgsnd_instr_q :std_ulogic; +signal ex3_msgsnd_instr_d :std_ulogic; +signal ex3_msgsnd_instr_q :std_ulogic; +signal ex1_dci_instr_d :std_ulogic; +signal ex1_dci_instr_q :std_ulogic; +signal ex2_dci_instr_d :std_ulogic; +signal ex2_dci_instr_q :std_ulogic; +signal ex3_dci_instr_d :std_ulogic; +signal ex3_dci_instr_q :std_ulogic; +signal ex1_ici_instr_d :std_ulogic; +signal ex1_ici_instr_q :std_ulogic; +signal ex2_ici_instr_d :std_ulogic; +signal ex2_ici_instr_q :std_ulogic; +signal ex3_ici_instr_d :std_ulogic; +signal ex3_ici_instr_q :std_ulogic; +signal ex3_l2load_type_d :std_ulogic; +signal ex3_l2load_type_q :std_ulogic; +signal flh2l2_gate_d :std_ulogic; +signal flh2l2_gate_q :std_ulogic; +signal rel_upd_dcarr_d :std_ulogic; +signal rel_upd_dcarr_q :std_ulogic; +signal ex1_ldawx_instr_d :std_ulogic; +signal ex1_ldawx_instr_q :std_ulogic; +signal ex2_ldawx_instr_d :std_ulogic; +signal ex2_ldawx_instr_q :std_ulogic; +signal ex3_watch_en_d :std_ulogic; +signal ex3_watch_en_q :std_ulogic; +signal ex4_watch_en_d :std_ulogic; +signal ex4_watch_en_q :std_ulogic; +signal ex5_watch_en_d :std_ulogic; +signal ex5_watch_en_q :std_ulogic; +signal ex1_wclr_instr_d :std_ulogic; +signal ex1_wclr_instr_q :std_ulogic; +signal ex2_wclr_instr_d :std_ulogic; +signal ex2_wclr_instr_q :std_ulogic; +signal ex3_wclr_instr_d :std_ulogic; +signal ex3_wclr_instr_q :std_ulogic; +signal ex4_wclr_instr_d :std_ulogic; +signal ex4_wclr_instr_q :std_ulogic; +signal ex5_wclr_instr_d :std_ulogic; +signal ex5_wclr_instr_q :std_ulogic; +signal ex4_wclr_set_d :std_ulogic; +signal ex4_wclr_set_q :std_ulogic; +signal ex5_wclr_set_d :std_ulogic; +signal ex5_wclr_set_q :std_ulogic; +signal ex1_wchk_instr_d :std_ulogic; +signal ex1_wchk_instr_q :std_ulogic; +signal ex2_wchk_instr_d :std_ulogic; +signal ex2_wchk_instr_q :std_ulogic; +signal ex3_stq_full_flush :std_ulogic; +signal ex3_lsq_ig_flush :std_ulogic; +signal ex4_cacheable_linelock_d :std_ulogic; +signal ex4_cacheable_linelock_q :std_ulogic; +signal ex1_icswx_instr_d :std_ulogic; +signal ex1_icswx_instr_q :std_ulogic; +signal ex2_icswx_instr_d :std_ulogic; +signal ex2_icswx_instr_q :std_ulogic; +signal ex3_icswx_instr_d :std_ulogic; +signal ex3_icswx_instr_q :std_ulogic; +signal ex1_icswx_dot_instr_d :std_ulogic; +signal ex1_icswx_dot_instr_q :std_ulogic; +signal ex2_icswx_dot_instr_d :std_ulogic; +signal ex2_icswx_dot_instr_q :std_ulogic; +signal ex3_icswx_dot_instr_d :std_ulogic; +signal ex3_icswx_dot_instr_q :std_ulogic; +signal ex1_icswx_epid_d :std_ulogic; +signal ex1_icswx_epid_q :std_ulogic; +signal ex2_icswx_epid_d :std_ulogic; +signal ex2_icswx_epid_q :std_ulogic; +signal ex3_icswx_epid_d :std_ulogic; +signal ex3_icswx_epid_q :std_ulogic; +signal ex3_c_inh_drop_op_d :std_ulogic; +signal ex3_c_inh_drop_op_q :std_ulogic; +signal ex3_drop_ld_req_b :std_ulogic; +signal ex3_drop_touch_int :std_ulogic; +signal ex3_drop_ld :std_ulogic; +signal ex3_drop_cacheable :std_ulogic; +signal ex3_drop_cacheable_b :std_ulogic; +signal ex3_cache_enabled :std_ulogic; +signal ex3_cache_inhibited :std_ulogic; +signal ex5_axu_rel_val_stg1_d :std_ulogic; +signal ex5_axu_rel_val_stg1_q :std_ulogic; +signal ex5_axu_rel_val_stg2_d :std_ulogic; +signal ex5_axu_rel_val_stg2_q :std_ulogic; +signal rel_axu_tid_d :std_ulogic_vector(0 to 3); +signal rel_axu_tid_q :std_ulogic_vector(0 to 3); +signal rel_axu_tid_stg1_d :std_ulogic_vector(0 to 3); +signal rel_axu_tid_stg1_q :std_ulogic_vector(0 to 3); +signal rel_axu_ta_gpr_d :std_ulogic_vector(0 to 8); +signal rel_axu_ta_gpr_q :std_ulogic_vector(0 to 8); +signal rel_axu_ta_gpr_stg1_d :std_ulogic_vector(0 to 8); +signal rel_axu_ta_gpr_stg1_q :std_ulogic_vector(0 to 8); +signal rf0_l2_inv_val_d :std_ulogic; +signal rf0_l2_inv_val_q :std_ulogic; +signal rf1_l2_inv_val_d :std_ulogic; +signal rf1_l2_inv_val_q :std_ulogic; +signal ex1_agen_binv_val_d :std_ulogic; +signal ex1_agen_binv_val_q :std_ulogic; +signal ex1_l2_inv_val_d :std_ulogic; +signal ex1_l2_inv_val_q :std_ulogic; +signal lsu_msr_gs_d :std_ulogic_vector(0 to 3); +signal lsu_msr_gs_q :std_ulogic_vector(0 to 3); +signal lsu_msr_pr_d :std_ulogic_vector(0 to 3); +signal lsu_msr_pr_q :std_ulogic_vector(0 to 3); +signal hypervisor_state :std_ulogic_vector(0 to 3); +signal lsu_msr_cm_d :std_ulogic_vector(0 to 3); +signal lsu_msr_cm_q :std_ulogic_vector(0 to 3); +signal rf1_lsu_64bit_mode :std_ulogic; +signal ex1_lsu_64bit_agen_d :std_ulogic; +signal ex1_lsu_64bit_agen_q :std_ulogic; +signal ex6_icbi_val_d :std_ulogic_vector(0 to 3); +signal ex6_icbi_val_q :std_ulogic_vector(0 to 3); +signal ex1_mtspr_trace_d :std_ulogic; +signal ex1_mtspr_trace_q :std_ulogic; +signal ex2_mtspr_trace_d :std_ulogic; +signal ex2_mtspr_trace_q :std_ulogic; +signal ex3_mtspr_trace_d :std_ulogic; +signal ex3_mtspr_trace_q :std_ulogic; +signal rf1_stg_act_d :std_ulogic; +signal rf1_stg_act_q :std_ulogic; +signal ex1_stg_act_d :std_ulogic; +signal ex1_stg_act_q :std_ulogic; +signal ex2_stg_act_d :std_ulogic; +signal ex2_stg_act_q :std_ulogic; +signal ex3_stg_act_d :std_ulogic; +signal ex3_stg_act_q :std_ulogic; +signal ex4_stg_act_d :std_ulogic; +signal ex4_stg_act_q :std_ulogic; +signal ex5_stg_act_d :std_ulogic; +signal ex5_stg_act_q :std_ulogic; +signal binv1_stg_act_d :std_ulogic; +signal binv1_stg_act_q :std_ulogic; +signal binv2_stg_act_d :std_ulogic; +signal binv2_stg_act_q :std_ulogic; +signal binv3_stg_act_d :std_ulogic; +signal binv3_stg_act_q :std_ulogic; +signal binv4_stg_act_d :std_ulogic; +signal binv4_stg_act_q :std_ulogic; +signal binv5_stg_act_d :std_ulogic; +signal binv5_stg_act_q :std_ulogic; +signal rel1_stg_act_d :std_ulogic; +signal rel1_stg_act_q :std_ulogic; +signal rel3_stg_act_d :std_ulogic; +signal rel3_stg_act_q :std_ulogic; +signal rel4_stg_act_d :std_ulogic; +signal rel4_stg_act_q :std_ulogic; +signal rel4_ex4_stg_act :std_ulogic; +signal binv2_ex2_stg_act :std_ulogic; +signal mtspr_trace_en_d :std_ulogic_vector(0 to 3); +signal mtspr_trace_en_q :std_ulogic_vector(0 to 3); +signal ex2_be10_en :std_ulogic_vector(0 to 31); +signal ex2_beC840_en :std_ulogic_vector(0 to 31); +signal ex2_be3210_en :std_ulogic_vector(0 to 31); +signal ex2_byte_en :std_ulogic_vector(0 to 31); +signal ex3_byte_en_d :std_ulogic_vector(0 to 31); +signal ex3_byte_en_q :std_ulogic_vector(0 to 31); +signal ex3_data_swap_val :std_ulogic; +signal ex2_rot_sel_be :std_ulogic_vector(0 to 5); +signal ex2_rot_sel_le :std_ulogic_vector(0 to 5); +signal ex3_rot_sel_le_d :std_ulogic_vector(1 to 5); +signal ex3_rot_sel_le_q :std_ulogic_vector(1 to 5); +signal ex3_rot_sel_be_d :std_ulogic_vector(1 to 5); +signal ex3_rot_sel_be_q :std_ulogic_vector(1 to 5); +signal ex3_rot_sel :std_ulogic_vector(0 to 4); +signal ex1_watch_clr_all :std_ulogic; +signal ex2_watch_clr_entry :std_ulogic; +signal dir_arr_rd_done :std_ulogic; +signal dir_arr_rd_cntrl :std_ulogic_vector(0 to 1); +signal dir_arr_rd_val_d :std_ulogic; +signal dir_arr_rd_val_q :std_ulogic; +signal dir_arr_rd_is0_val_d :std_ulogic; +signal dir_arr_rd_is0_val_q :std_ulogic; +signal dir_arr_rd_is1_val_d :std_ulogic; +signal dir_arr_rd_is1_val_q :std_ulogic; +signal dir_arr_rd_is2_val_d :std_ulogic; +signal dir_arr_rd_is2_val_q :std_ulogic; +signal dir_arr_rd_rf0_val_d :std_ulogic; +signal dir_arr_rd_rf0_val_q :std_ulogic; +signal dir_arr_rd_rf1_val_d :std_ulogic; +signal dir_arr_rd_rf1_val_q :std_ulogic; +signal dir_arr_rd_rf0_done_d :std_ulogic; +signal dir_arr_rd_rf0_done_q :std_ulogic; +signal dir_arr_rd_rf1_done_d :std_ulogic; +signal dir_arr_rd_rf1_done_q :std_ulogic; +signal dir_arr_rd_ex1_done_d :std_ulogic; +signal dir_arr_rd_ex1_done_q :std_ulogic; +signal dir_arr_rd_ex2_done_d :std_ulogic; +signal dir_arr_rd_ex2_done_q :std_ulogic; +signal dir_arr_rd_ex3_done_d :std_ulogic; +signal dir_arr_rd_ex3_done_q :std_ulogic; +signal dir_arr_rd_ex4_done_d :std_ulogic; +signal dir_arr_rd_ex4_done_q :std_ulogic; +signal dir_arr_rd_tag :std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); +signal dir_arr_rd_directory :std_ulogic_vector(0 to 5); +signal dir_arr_rd_parity :std_ulogic_vector(0 to parBits-1); +signal dir_arr_rd_lru :std_ulogic_vector(0 to 6); +signal ex2_flh2l2_load :std_ulogic; +signal ex2_l2_lock_clr :std_ulogic; +signal ex4_thrd_enc :std_ulogic_vector(0 to 1); +signal my_spare0_lclk :clk_logic; +signal my_spare0_d1clk :std_ulogic; +signal my_spare0_d2clk :std_ulogic; +signal my_spare0_latches_d :std_ulogic_vector(0 to 2); +signal my_spare0_latches_q :std_ulogic_vector(0 to 2); +signal my_spare1_lclk :clk_logic; +signal my_spare1_d1clk :std_ulogic; +signal my_spare1_d2clk :std_ulogic; +signal my_spare1_latches_d :std_ulogic_vector(0 to 19); +signal my_spare1_latches_q :std_ulogic_vector(0 to 19); +signal ex4_c_inh_d :std_ulogic; +signal ex4_c_inh_q :std_ulogic; +signal ex4_opsize_d :std_ulogic_vector(0 to 5); +signal ex4_opsize_q :std_ulogic_vector(0 to 5); +signal ex4_rot_sel_d :std_ulogic_vector(0 to 4); +signal ex4_rot_sel_q :std_ulogic_vector(0 to 4); +signal ex4_data_swap_val_d :std_ulogic; +signal ex4_data_swap_val_q :std_ulogic; +signal ex4_algebraic_d :std_ulogic; +signal ex4_algebraic_q :std_ulogic; +signal ex4_lock_en_d :std_ulogic; +signal ex4_lock_en_q :std_ulogic; + +signal tiup :std_ulogic; +signal siv :std_ulogic_vector(0 to scan_right); +signal sov :std_ulogic_vector(0 to scan_right); + + + +begin + +tiup <= '1'; + + +rf1_stg_act_d <= xu_lsu_rf0_act or clkg_ctl_override_q; +ex1_stg_act_d <= xu_lsu_rf1_cmd_act or dir_arr_rd_rf1_val_q or clkg_ctl_override_q; +ex2_stg_act_d <= ex1_stg_act_q; +ex3_stg_act_d <= ex2_stg_act_q; +ex4_stg_act_d <= ex3_stg_act_q; +ex5_stg_act_d <= ex4_stg_act_q; + +binv1_stg_act_d <= rf1_l2_inv_val_q or clkg_ctl_override_q; +binv2_stg_act_d <= binv1_stg_act_q; +binv3_stg_act_d <= binv2_stg_act_q; +binv4_stg_act_d <= binv3_stg_act_q; +binv5_stg_act_d <= binv4_stg_act_q; + +rel1_stg_act_d <= ldq_rel_data_val_early or clkg_ctl_override_q; +rel3_stg_act_d <= ldq_rel_stg24_val or clkg_ctl_override_q; +rel4_stg_act_d <= rel3_stg_act_q; + +rel4_ex4_stg_act <= ex4_stg_act_q or rel4_stg_act_q; +binv2_ex2_stg_act <= binv2_stg_act_q or ex2_stg_act_q; + + +flh2l2_gate_d <= an_ac_flh2l2_gate; + +clkg_ctl_override_d <= spr_xucr0_clkg_ctl_b1; + +spr_xucr0_wlck_d <= xu_lsu_spr_xucr0_wlk and not xu_lsu_spr_ccr2_dfrat; +spr_xucr0_wlck_cpy_d <= spr_xucr0_wlck_q; + +spr_xucr0_flh2l2_d <= xu_lsu_spr_xucr0_flh2l2 and flh2l2_gate_q; +ex2_spr_xucr0_flh2l2 <= spr_xucr0_flh2l2_q; +ex3_spr_xucr0_flh2l2_d <= ex2_spr_xucr0_flh2l2; + +spr_xucr0_dcdis_d <= xu_lsu_spr_xucr0_dcdis; + +spr_xucr0_cls_d <= xu_lsu_spr_xucr0_cls; +agen_xucr0_cls_dly_d <= spr_xucr0_cls_q; +agen_xucr0_cls_d <= agen_xucr0_cls_dly_q; + +mtspr_trace_en_d <= xu_lsu_mtspr_trace_en; + +lsu_msr_gs_d <= xu_lsu_msr_gs; +lsu_msr_pr_d <= xu_lsu_msr_pr; +hypervisor_state <= lsu_msr_gs_q nor lsu_msr_pr_q; + +lsu_msr_cm_d <= xu_lsu_spr_msr_cm; +rf1_lsu_64bit_mode <= (xu_lsu_rf1_thrd_id(0) and lsu_msr_cm_q(0)) or (xu_lsu_rf1_thrd_id(1) and lsu_msr_cm_q(1)) or + (xu_lsu_rf1_thrd_id(2) and lsu_msr_cm_q(2)) or (xu_lsu_rf1_thrd_id(3) and lsu_msr_cm_q(3)); +ex1_lsu_64bit_agen_d <= rf1_lsu_64bit_mode or rf1_l2_inv_val_q; + + +rf0_l2_inv_val_d <= is2_l2_inv_val; +rf1_l2_inv_val_d <= rf0_l2_inv_val_q; +ex1_agen_binv_val_d <= rf1_l2_inv_val_q; +ex1_l2_inv_val_d <= rf1_l2_inv_val_q; + +ex1_optype1_d <= xu_lsu_rf1_optype1; +ex2_optype1_d <= ex1_optype1_q; + +ex1_optype2_d <= xu_lsu_rf1_optype2; +ex2_optype2_d <= ex1_optype2_q; + +ex1_optype4_d <= xu_lsu_rf1_optype4; +ex2_optype4_d <= ex1_optype4_q; + +ex1_optype8_d <= xu_lsu_rf1_optype8; +ex2_optype8_d <= ex1_optype8_q; + +ex1_optype16_d <= xu_lsu_rf1_optype16; +ex2_optype16_d <= ex1_optype16_q; + +ex1_optype32_d <= xu_lsu_rf1_optype32; +ex2_optype32_d <= ex1_optype32_q; + +ex3_p_addr_lwr_d <= ex2_p_addr_lwr; +ex4_p_addr_d <= ex3_p_addr & ex3_p_addr_lwr_q(52 to 63); +ex5_p_addr_d <= ex4_p_addr_q(64-real_data_add to 57); +ex6_p_addr_d <= ex5_p_addr_q; + +ex1_dir_acc_val_d <= dir_arr_rd_rf1_done_q or (xu_lsu_rf1_cache_acc and not rf1_stg_flush); + +cache_acc_ex1_d <= xu_lsu_rf1_cache_acc and not rf1_stg_flush; +cache_acc_ex2_d <= cache_acc_ex1_q and not (ex1_undef_touch or ex1_stg_flush); +cache_acc_ex3_d <= cache_acc_ex2_q and not ex2_stg_flush; +cache_acc_ex4_d <= cache_acc_ex3_q and not ex3_stg_flush; +cache_acc_ex5_d <= cache_acc_ex4_q and not ex4_stg_flush; +ex2_cacc_d <= cache_acc_ex1_q; +ex3_cacc_d <= ex2_cacc_q; + +ex1_thrd_id_d <= xu_lsu_rf1_thrd_id; +ex2_thrd_id_d <= ex1_thrd_id_q; +ex3_thrd_id_d <= ex2_thrd_id_q; +ex4_thrd_id_d <= ex3_thrd_id_q; +ex5_thrd_id_d <= ex4_thrd_id_q; + +with ex4_thrd_id_q select + ex4_thrd_enc <= "01" when "0100", + "10" when "0010", + "11" when "0001", + "00" when others; + +ex1_target_gpr_d <= xu_lsu_rf1_target_gpr; +ex2_target_gpr_d <= ex1_target_gpr_q; +ex3_target_gpr_d <= ex2_target_gpr_q; +ex4_target_gpr_d <= ex3_target_gpr_q; + +ex1_dcbt_instr_d <= xu_lsu_rf1_dcbt_instr; +ex2_dcbt_instr_d <= ex1_dcbt_instr_q and (ex1_th_fld_c_q or ex1_th_fld_l2_q); +ex3_dcbt_instr_d <= ex2_dcbt_instr_q; + +ex1_dcbtst_instr_d <= xu_lsu_rf1_dcbtst_instr; +ex2_dcbtst_instr_d <= ex1_dcbtst_instr_q and (ex1_th_fld_c_q or ex1_th_fld_l2_q); +ex3_dcbtst_instr_d <= ex2_dcbtst_instr_q; + +ex4_perf_dcbt_d <= (ex3_th_fld_l2_q or ex3_th_fld_c_q) and (ex3_dcbtst_instr_q or ex3_dcbt_instr_q or ex3_dcbtstls_instr_q or ex3_dcbtls_instr_q) and not ex3_blk_touch; +ex5_perf_dcbt_d <= ex4_perf_dcbt_q; + +rf1_th_b0 <= xu_lsu_rf1_th_fld(0) and (xu_lsu_rf1_dcbt_instr or xu_lsu_rf1_dcbtst_instr); +ex1_th_fld_c_d <= not rf1_th_b0 and (xu_lsu_rf1_th_fld(1 to 4) = "0000"); +ex2_th_fld_c_d <= ex1_th_fld_c_q; +ex3_th_fld_c_d <= ex2_th_fld_c_q; + +ex1_th_fld_l2_d <= not rf1_th_b0 and (xu_lsu_rf1_th_fld(1 to 4) = "0010"); +ex2_th_fld_l2_d <= ex1_th_fld_l2_q; +ex3_th_fld_l2_d <= ex2_th_fld_l2_q; + +ex1_dcbtls_instr_d <= xu_lsu_rf1_dcbtls_instr; +ex2_dcbtls_instr_d <= ex1_dcbtls_instr_q and (ex1_th_fld_c_q or ex1_th_fld_l2_q); +ex3_dcbtls_instr_d <= ex2_dcbtls_instr_q; + +ex1_dcbtstls_instr_d <= xu_lsu_rf1_dcbtstls_instr; +ex2_dcbtstls_instr_d <= ex1_dcbtstls_instr_q and (ex1_th_fld_c_q or ex1_th_fld_l2_q); +ex3_dcbtstls_instr_d <= ex2_dcbtstls_instr_q; + +ex1_dcblc_instr_d <= xu_lsu_rf1_dcblc_instr; +ex2_dcblc_instr_d <= ex1_dcblc_instr_q and (ex1_th_fld_c_q or ex1_th_fld_l2_q); +ex3_dcblc_instr_d <= ex2_dcblc_instr_q; + +ex1_icblc_l2_instr_d <= xu_lsu_rf1_icblc_instr; +ex2_icblc_l2_instr_d <= ex1_icblc_l2_instr_q and (ex1_th_fld_c_q or ex1_th_fld_l2_q); +ex3_icblc_l2_instr_d <= ex2_icblc_l2_instr_q; + +ex1_icbt_l2_instr_d <= xu_lsu_rf1_icbt_instr; +ex2_icbt_l2_instr_d <= ex1_icbt_l2_instr_q and (ex1_th_fld_c_q or ex1_th_fld_l2_q); +ex3_icbt_l2_instr_d <= ex2_icbt_l2_instr_q; + +ex1_icbtls_l2_instr_d <= xu_lsu_rf1_icbtls_instr; +ex2_icbtls_l2_instr_d <= ex1_icbtls_l2_instr_q and (ex1_th_fld_c_q or ex1_th_fld_l2_q); +ex3_icbtls_l2_instr_d <= ex2_icbtls_l2_instr_q; + +ex1_tlbsync_instr_d <= xu_lsu_rf1_tlbsync_instr and not rf1_stg_flush; +ex2_tlbsync_instr_d <= ex1_tlbsync_instr_q and not ex1_stg_flush; +ex3_tlbsync_instr_d <= ex2_tlbsync_instr_q and not ex2_stg_flush; + +ex1_ldawx_instr_d <= xu_lsu_rf1_ldawx_instr; +ex2_ldawx_instr_d <= ex1_ldawx_instr_q; +ex3_watch_en_d <= ex2_ldawx_instr_q; +ex4_watch_en_d <= ex3_watch_en_q; +ex5_watch_en_d <= ex4_watch_en_q; + +ex1_icswx_instr_d <= xu_lsu_rf1_icswx_instr; +ex2_icswx_instr_d <= ex1_icswx_instr_q; +ex3_icswx_instr_d <= ex2_icswx_instr_q; + +ex1_icswx_dot_instr_d <= xu_lsu_rf1_icswx_dot_instr; +ex2_icswx_dot_instr_d <= ex1_icswx_dot_instr_q; +ex3_icswx_dot_instr_d <= ex2_icswx_dot_instr_q; + +ex1_icswx_epid_d <= xu_lsu_rf1_icswx_epid; +ex2_icswx_epid_d <= ex1_icswx_epid_q; +ex3_icswx_epid_d <= ex2_icswx_epid_q; + +ex1_wclr_instr_d <= xu_lsu_rf1_wclr_instr; +ex2_wclr_instr_d <= ex1_wclr_instr_q; +ex3_wclr_instr_d <= ex2_wclr_instr_q; +ex4_wclr_instr_d <= ex3_wclr_instr_q; +ex5_wclr_instr_d <= ex4_wclr_instr_q; +ex4_wclr_set_d <= ex3_l_fld_q = "01"; +ex5_wclr_set_d <= ex4_wclr_set_q; + +ex1_watch_clr_all <= ex1_wclr_instr_q and not ex1_l_fld_q(0); + +ex1_wchk_instr_d <= xu_lsu_rf1_wchk_instr and not rf1_stg_flush; +ex2_wchk_instr_d <= ex1_wchk_instr_q and not ex1_stg_flush; + +ex1_dcbst_instr_d <= xu_lsu_rf1_dcbst_instr; +ex2_dcbst_instr_d <= ex1_dcbst_instr_q; +ex3_dcbst_instr_d <= ex2_dcbst_instr_q; + +ex1_dcbf_instr_d <= xu_lsu_rf1_dcbf_instr; +ex2_dcbf_instr_d <= ex1_dcbf_instr_q; +ex2_l2_dcbf <= ex2_dcbf_instr_q and not (ex2_l_fld_q = "11"); +ex2_local_dcbf <= ex2_dcbf_instr_q and (ex2_l_fld_q = "11"); +ex3_dcbf_instr_d <= ex2_dcbf_instr_q; + +ex1_mtspr_trace_d <= xu_lsu_rf1_mtspr_trace and not rf1_stg_flush; +ex2_mtspr_trace_d <= ex1_mtspr_trace_q and (or_reduce(mtspr_trace_en_q and ex1_thrd_id_q)) and not ex1_stg_flush; +ex3_mtspr_trace_d <= ex2_mtspr_trace_q and not ex2_stg_flush; + +ex1_sync_instr_d <= xu_lsu_rf1_sync_instr and not rf1_stg_flush; +ex2_sync_instr_d <= ex1_sync_instr_q and not ex1_stg_flush; +ex3_sync_instr_d <= ex2_sync_instr_q and not ex2_stg_flush; + +ex1_l_fld_d <= xu_lsu_rf1_l_fld; +ex2_l_fld_d <= ex1_l_fld_q; +ex3_l_fld_d <= ex2_l_fld_q; + +ex1_dcbi_instr_d <= xu_lsu_rf1_dcbi_instr; +ex2_dcbi_instr_d <= ex1_dcbi_instr_q; +ex3_dcbi_instr_d <= ex2_dcbi_instr_q; + +ex1_dcbz_instr_d <= xu_lsu_rf1_dcbz_instr; +ex2_dcbz_instr_d <= ex1_dcbz_instr_q; +ex3_dcbz_instr_d <= ex2_dcbz_instr_q; + +ex1_icbi_instr_d <= xu_lsu_rf1_icbi_instr; +ex2_icbi_instr_d <= ex1_icbi_instr_q; +ex3_icbi_instr_d <= ex2_icbi_instr_q; +ex4_icbi_instr_d <= ex3_icbi_instr_q; +ex5_icbi_instr_d <= ex4_icbi_instr_q; +ex5_icbi_instr <= ex5_icbi_instr_q and cache_acc_ex5_q and not ex5_stg_flush; +ex6_icbi_val_d <= gate(ex5_thrd_id_q, ex5_icbi_instr); + +ex1_mbar_instr_d <= xu_lsu_rf1_mbar_instr and not rf1_stg_flush; +ex2_mbar_instr_d <= ex1_mbar_instr_q and not ex1_stg_flush; +ex3_mbar_instr_d <= ex2_mbar_instr_q and not ex2_stg_flush; + +ex1_msgsnd_instr_d <= xu_lsu_rf1_is_msgsnd and not rf1_stg_flush; +ex2_msgsnd_instr_d <= ex1_msgsnd_instr_q and not ex1_stg_flush; +ex3_msgsnd_instr_d <= ex2_msgsnd_instr_q and not ex2_stg_flush; + +ex1_dci_instr_d <= xu_lsu_rf1_dci_instr and not rf1_stg_flush; +ex2_dci_instr_d <= ex1_dci_instr_q and ex1_th_fld_l2_q and not ex1_stg_flush; +ex3_dci_instr_d <= ex2_dci_instr_q and not ex2_stg_flush; + +ex1_ici_instr_d <= xu_lsu_rf1_ici_instr and not rf1_stg_flush; +ex2_ici_instr_d <= ex1_ici_instr_q and ex1_th_fld_l2_q and not ex1_stg_flush; +ex3_ici_instr_d <= ex2_ici_instr_q and not ex2_stg_flush; + +ex1_algebraic_d <= xu_lsu_rf1_algebraic; +ex2_algebraic_d <= ex1_algebraic_q; +ex3_algebraic_d <= ex2_algebraic_q; + +ex1_byte_rev_d <= xu_lsu_rf1_byte_rev; +ex2_byte_rev_d <= ex1_byte_rev_q; +ex3_byte_rev_d <= ex2_byte_rev_q; + +ex1_lock_instr_d <= xu_lsu_rf1_lock_instr; +ex2_lock_instr_d <= ex1_lock_instr_q; +ex3_lock_instr_d <= ex2_lock_instr_q; +ex4_lock_instr_d <= ex3_lock_instr_q; +ex5_lock_instr_d <= ex4_lock_instr_q; + +ex1_mutex_hint_d <= xu_lsu_rf1_mutex_hint; +ex2_mutex_hint_d <= ex1_mutex_hint_q; +ex3_mutex_hint_d <= ex2_mutex_hint_q; + +ex1_load_instr_d <= xu_lsu_rf1_load_instr; +ex2_load_instr_d <= ex1_load_instr_q; +ex3_load_instr_d <= ex2_load_instr_q; +ex4_load_instr_d <= ex3_load_instr_q; +ex5_load_instr_d <= ex4_load_instr_q; +ex3_load_type_d <= ex2_load_instr_q or ex2_dcbt_instr_q or ex2_dcbtst_instr_q or ex2_dcbtls_instr_q or ex2_dcbtstls_instr_q; +ex4_load_type_d <= ex3_load_type_q; +ex3_l2load_type_d <= ex3_load_type_d or ex2_icbt_l2_instr_q or ex2_icbtls_l2_instr_q; + +ex1_store_instr_d <= xu_lsu_rf1_store_instr; +ex2_store_instr_d <= ex1_store_instr_q; +ex3_store_instr_d <= ex2_store_instr_q; +ex4_store_instr_d <= ex3_store_instr_q; +ex5_store_instr_d <= ex4_store_instr_q; + +ex1_axu_op_val_d <= xu_lsu_rf1_axu_op_val; +ex2_axu_op_val_d <= ex1_axu_op_val_q; +ex3_axu_op_val_d <= ex2_axu_op_val_q; +ex4_axu_op_val_d <= ex3_axu_op_val_q; +ex5_axu_op_val_d <= ex4_axu_op_val_q; + +ex1_src0_vld_d <= xu_lsu_rf1_src0_vld and not rf1_stg_flush; +ex1_src0_reg_d <= xu_lsu_rf1_src0_reg; +ex1_src1_vld_d <= xu_lsu_rf1_src1_vld and not rf1_stg_flush; +ex1_src1_reg_d <= xu_lsu_rf1_src1_reg; +ex1_targ_vld_d <= xu_lsu_rf1_targ_vld and not rf1_stg_flush; +ex1_targ_reg_d <= xu_lsu_rf1_targ_reg; + +ex1_sgpr_instr_d <= xu_lsu_rf1_src_gpr and not rf1_stg_flush; +ex1_saxu_instr_d <= xu_lsu_rf1_src_axu and not rf1_stg_flush; +ex1_sdp_instr_d <= xu_lsu_rf1_src_dp and not rf1_stg_flush; +ex1_tgpr_instr_d <= xu_lsu_rf1_targ_gpr and not rf1_stg_flush; +ex1_taxu_instr_d <= xu_lsu_rf1_targ_axu and not rf1_stg_flush; +ex1_tdp_instr_d <= xu_lsu_rf1_targ_dp and not rf1_stg_flush; + +ex2_tgpr_instr_d <= ex1_tgpr_instr_q and not ex1_stg_flush; +ex2_taxu_instr_d <= ex1_taxu_instr_q and not ex1_stg_flush; +ex2_tdp_instr_d <= ex1_tdp_instr_q and not ex1_stg_flush; + +ex3_tgpr_instr_d <= ex2_tgpr_instr_q and not ex2_stg_flush; +ex3_taxu_instr_d <= ex2_taxu_instr_q and not ex2_stg_flush; + +ex4_tgpr_instr_d <= ex3_tgpr_instr_q and not ex3_stg_flush; +ex4_taxu_instr_d <= ex3_taxu_instr_q and not ex3_stg_flush; +ex4_tgpr_instr <= ex4_tgpr_instr_q and not ex4_stg_flush; +ex4_taxu_instr <= ex4_taxu_instr_q and not ex4_stg_flush; + +ex1_ldst_falign_d <= xu_lsu_rf1_axu_ldst_falign; +ex1_ldst_fexcpt_d <= xu_lsu_rf1_axu_ldst_fexcpt; +ex2_ldst_fexcpt_d <= ex1_ldst_fexcpt_q; + +rel_upd_dcarr_d <= rel_dcarr_val_upd; + + +ex2_opsize <= ex2_optype32_q & ex2_optype16_q & ex2_optype8_q & ex2_optype4_q & ex2_optype2_q & ex2_optype1_q; +ex3_opsize_d <= ex2_opsize; + +ex2_op_sel(0) <= ex2_opsize(1) or ex2_opsize(2) or ex2_opsize(3) or ex2_opsize(4) or ex2_opsize(5); +ex2_op_sel(1) <= ex2_opsize(1) or ex2_opsize(2) or ex2_opsize(3) or ex2_opsize(4); +ex2_op_sel(2) <= ex2_opsize(1) or ex2_opsize(2) or ex2_opsize(3); +ex2_op_sel(3) <= ex2_opsize(1) or ex2_opsize(2) or ex2_opsize(3); +ex2_op_sel(4) <= ex2_opsize(1) or ex2_opsize(2); +ex2_op_sel(5) <= ex2_opsize(1) or ex2_opsize(2); +ex2_op_sel(6) <= ex2_opsize(1) or ex2_opsize(2); +ex2_op_sel(7) <= ex2_opsize(1) or ex2_opsize(2); +ex2_op_sel(8) <= ex2_opsize(1); +ex2_op_sel(9) <= ex2_opsize(1); +ex2_op_sel(10) <= ex2_opsize(1); +ex2_op_sel(11) <= ex2_opsize(1); +ex2_op_sel(12) <= ex2_opsize(1); +ex2_op_sel(13) <= ex2_opsize(1); +ex2_op_sel(14) <= ex2_opsize(1); +ex2_op_sel(15) <= ex2_opsize(1); + +with ex2_p_addr_lwr(59) select + ex2_be10_en <= ex2_op_sel(0 to 15) & x"0000" when '0', + x"0000" & ex2_op_sel(0 to 15) when others; + +with ex2_p_addr_lwr(60 to 61) select + ex2_beC840_en <= ex2_be10_en(0 to 31) when "00", + x"0" & ex2_be10_en(0 to 27) when "01", + x"00" & ex2_be10_en(0 to 23) when "10", + x"000" & ex2_be10_en(0 to 19) when others; + +with ex2_p_addr_lwr(62 to 63) select + ex2_be3210_en <= ex2_beC840_en(0 to 31) when "00", + '0' & ex2_beC840_en(0 to 30) when "01", + "00" & ex2_beC840_en(0 to 29) when "10", + "000" & ex2_beC840_en(0 to 28) when others; + +ben_gen : for t in 0 to 31 generate begin + ex2_byte_en(t) <= ex2_opsize(0) or ex2_be3210_en(t); +end generate ben_gen; + +ex3_byte_en_d <= ex2_byte_en; + + +ex2_rot_sel_be <= std_ulogic_vector(unsigned(ex2_p_addr_lwr(58 to 63)) + unsigned(ex2_opsize)); +ex2_rot_sel_le <= std_ulogic_vector(unsigned(rot_max_size) - unsigned(ex2_p_addr_lwr(58 to 63))); +ex3_rot_sel_le_d <= ex2_rot_sel_le(1 to 5); +ex3_rot_sel_be_d <= ex2_rot_sel_be(1 to 5); + +with ex3_data_swap_val select + ex3_rot_sel <= ex3_rot_sel_le_q when '1', + ex3_rot_sel_be_q when others; + + +ex1_undef_touch <= (ex1_dcbt_instr_q or ex1_dcblc_instr_q or ex1_dcbtls_instr_q or ex1_dcbtstls_instr_q or ex1_dcbtst_instr_q or + ex1_icbt_l2_instr_q or ex1_icblc_l2_instr_q or ex1_icbtls_l2_instr_q) and not (ex1_th_fld_c_q or ex1_th_fld_l2_q); + +ex1_lockset_instr <= ex1_dcbtls_instr_q or ex1_dcbtstls_instr_q or ex1_dcblc_instr_q or ex1_icbtls_l2_instr_q or ex1_icblc_l2_instr_q; +ex2_undef_lockset_d <= (ex1_lockset_instr and cache_acc_ex1_q and not (ex1_th_fld_c_q or ex1_th_fld_l2_q)) and not ex1_stg_flush; +ex3_undef_lockset_d <= ex2_undef_lockset_q and not ex2_stg_flush; +ex3_cinh_lockset <= (ex3_dcbtls_instr_q or ex3_dcbtstls_instr_q or ex3_dcblc_instr_q or ex3_icbtls_l2_instr_q or ex3_icblc_l2_instr_q) and ex3_cache_inhibited; +ex3_l1dcdis_lockset <= (ex3_dcbtls_instr_q or ex3_dcbtstls_instr_q or ex3_dcblc_instr_q) and ex3_th_fld_c_q and spr_xucr0_dcdis_q and ex3_cache_enabled; +ex4_unable_2lock_d <= (ex3_undef_lockset_q or ex3_cinh_lockset or ex3_l1dcdis_lockset) and not ex3_stg_flush; +ex5_unable_2lock_d <= ex4_unable_2lock_q and not ex4_stg_flush; + +ex4_store_commit_d <= ex3_store_instr_q and ex3_cache_enabled and not (ex3_stg_flush or ex3_lock_instr_q or ex3_spr_xucr0_flh2l2_q or spr_xucr0_dcdis_q); +ex4_load_commit_d <= ex3_load_type_q and ex3_cache_enabled and not (ex3_stg_flush or ex3_nogpr_upd or spr_xucr0_dcdis_q); +ex4_load_hit <= ex4_load_commit_q and not ex4_miss and cache_acc_ex4_q and not ex4_stg_flush; +ex5_load_hit_d <= ex4_load_type_q and not ex4_miss and cache_acc_ex4_q and not ex4_cache_inh_q and not ex4_stg_flush; + +ex4_store_miss <= ex4_store_instr_q and ex4_miss and cache_acc_ex4_q and not ex4_cache_inh_q; +ex5_store_miss_d <= ex4_store_miss; +ex4_load_miss <= ex4_load_type_q and ex4_miss and cache_acc_ex4_q and not ex4_cache_inh_q; +ex5_load_miss_d <= ex4_load_miss; + +ex4_cacheable_linelock_d <= (ex3_dcbtls_instr_q or ex3_dcbtstls_instr_q) and ex3_cache_enabled; +ex4_cache_inh_d <= ex3_wimge_i_bit; +ex5_cache_inh_d <= ex4_cache_inh_q; + +ex3_cache_enabled <= cache_acc_ex3_q and not ex3_wimge_i_bit; +ex3_cache_inhibited <= cache_acc_ex3_q and ex3_wimge_i_bit; + +ex3_data_swap_val <= ex3_wimge_e_bit xor ex3_byte_rev_q; + +ex2_dcblc_l1 <= ex2_dcblc_instr_q and ex2_th_fld_c_q; +ddir_acc_instr <= ex2_load_instr_q or ex2_store_instr_q or data_touch_op or ex2_dcblc_l1 or is_inval_op; + + +ex2_targ_match_b1_d <= (ex2_target_gpr_q(1 to 8) = ex1_targ_reg_q) and ex1_targ_vld_q and cache_acc_ex2_q and ex2_load_instr_q and not (ex1_stg_flush or ex2_axu_op_val_q); +ex3_targ_match_b1_d <= ex2_targ_match_b1_q and not ex2_stg_flush; +ex2_targ_match_b2_d <= (ex3_target_gpr_q(1 to 8) = ex1_targ_reg_q) and ex1_targ_vld_q and cache_acc_ex3_q and ex3_load_instr_q and not (ex1_stg_flush or ex3_axu_op_val_q); + +ex5_instr_val_d <= or_reduce(xu_lsu_ex4_val) and not ex4_stg_flush; +ex4_targ_match_b1_d <= ex3_targ_match_b1_q and not ex3_stg_flush; +ex5_targ_match_b1_d <= ex4_targ_match_b1_q and not ex4_stg_flush; +ex6_targ_match_b1_d <= ex5_targ_match_b1_q and ex5_instr_val_q and not ex5_stg_flush; +ex3_targ_match_b2_d <= ex2_targ_match_b2_q and not ex2_stg_flush; +ex4_targ_match_b2_d <= ex3_targ_match_b2_q and not ex3_stg_flush; +ex5_targ_match_b2_d <= ex4_targ_match_b2_q and not ex4_stg_flush; + +ex7_targ_match_d <= ex5_targ_match_b1_q and ex5_instr_val_q and not ex5_stg_flush; +ex8_targ_match_d <= ex6_targ_match_b1_q or (ex5_targ_match_b2_q and ex5_instr_val_q and not ex5_stg_flush); + +data_touch_op <= ex2_dcbt_instr_q or ex2_dcbtst_instr_q or ex2_dcbtls_instr_q or ex2_dcbtstls_instr_q; +inst_touch_op <= ex2_icbt_l2_instr_q or ex2_icbtls_l2_instr_q; +no_lru_upd <= all_touch_op or is_inval_op or ex2_icbi_instr_q or ex2_dcbst_instr_q or ex2_wclr_instr_q or ex2_icblc_l2_instr_q or ex2_dcblc_instr_q; + +ex3_l2_request_d <= ((ex2_dcbtls_instr_q or ex2_dcbtstls_instr_q) and ex2_th_fld_l2_q) or ex2_icbt_l2_instr_q or ex2_icbtls_l2_instr_q or ex2_lock_instr_q; +ex3_l2_request <= ex3_l2_request_q or ex3_cache_inhibited; + +all_touch_op <= data_touch_op or inst_touch_op; +ex2_l2_lock_clr <= (ex2_icblc_l2_instr_q or ex2_dcblc_instr_q) and ex2_th_fld_l2_q; + +is_mem_bar_op <= ex2_sync_instr_q or ex2_mbar_instr_q or ex2_tlbsync_instr_q; + +is_inval_op <= ex2_dcbf_instr_q or ex2_dcbi_instr_q or ex2_lock_instr_q or ex2_dcbz_instr_q or (ex2_spr_xucr0_flh2l2 and ex2_store_instr_q) or ex2_icswx_dot_instr_q or ex2_icswx_instr_q or + ex2_icswx_epid_q; + +is_lock_set <= (ex2_dcbtstls_instr_q or ex2_dcbtls_instr_q) and ex2_th_fld_c_q; +ex3_l2_lock_set <= (ex3_dcbtstls_instr_q or ex3_dcbtls_instr_q) and ex3_th_fld_l2_q; +ex3_c_dcbtls <= ex3_dcbtls_instr_q and ex3_th_fld_c_q; +ex3_c_dcbtstls <= ex3_dcbtstls_instr_q and ex3_th_fld_c_q; +ex3_c_icbtls <= ex3_icbtls_l2_instr_q and ex3_th_fld_c_q; +ex3_l2_dcbtls <= ex3_dcbtls_instr_q and ex3_th_fld_l2_q; +ex3_l2_dcbtstls <= ex3_dcbtstls_instr_q and ex3_th_fld_l2_q; +ex3_l2_icbtls <= ex3_icbtls_l2_instr_q and ex3_th_fld_l2_q; + +is_lock_clr <= (ex2_dcblc_instr_q and ex2_th_fld_c_q) or is_inval_op; + +l2_ctype <= (ex2_store_instr_q or ex2_l2_dcbf or ex2_dcbi_instr_q or ex2_dcbz_instr_q or ex2_dcbst_instr_q or ex2_icbi_instr_q or ex2_icswx_instr_q or + ex2_icswx_dot_instr_q or ex2_icswx_epid_q or ex2_lock_instr_q or all_touch_op or ex2_l2_lock_clr or ex2_load_instr_q) and cache_acc_ex2_q; +ex3_c_inh_drop_op_d <= (all_touch_op or ex2_l2_lock_clr or ex2_local_dcbf) and cache_acc_ex2_q and not ex2_stg_flush; + +ex3_l2_op_d <= (l2_ctype or is_mem_bar_op or ex2_msgsnd_instr_q or ex2_mtspr_trace_q or ex2_dci_instr_q or ex2_ici_instr_q) and not ex2_stg_flush; + +ex2_watch_clr_entry <= ex2_wclr_instr_q and ex2_l_fld_q(0); + +ex3_local_dcbf_d <= (ex2_local_dcbf or ex2_watch_clr_entry) and cache_acc_ex2_q and not ex2_stg_flush; + + +ex2_flh2l2_load <= ex2_load_instr_q and ex2_spr_xucr0_flh2l2; + +ex3_ldstq_instr_d <= (((ex2_store_instr_q or ex2_l2_dcbf or ex2_dcbi_instr_q or ex2_dcbz_instr_q or ex2_dcbst_instr_q or ex2_icbi_instr_q or ex2_icswx_instr_q or ex2_icswx_dot_instr_q or + ex2_icswx_epid_q or ex2_l2_lock_clr or ex2_flh2l2_load) and cache_acc_ex2_q) or + is_mem_bar_op or ex2_msgsnd_instr_q or ex2_mtspr_trace_q or ex2_dci_instr_q or ex2_ici_instr_q) and not ex2_stg_flush; + +ex3_nogpr_upd <= ex3_dcbt_instr_q or ex3_dcbtst_instr_q or ex3_lock_instr_q or ex3_dcbtls_instr_q or ex3_dcbtstls_instr_q; + +ex2_blkable_touch_d <= ex1_dcbt_instr_q or ex1_dcbtst_instr_q or ex1_icbt_l2_instr_q or ex1_undef_touch; +ex3_blkable_touch_d <= ex2_blkable_touch_q; +ex3_blk_touch <= ex3_blkable_touch_q and ex3_excp_det; + +l_s_q_val <= ex3_l2_op_q; +stx_instr <= ex3_store_instr_q and ex3_lock_instr_q; +larx_instr <= ex3_load_instr_q and ex3_lock_instr_q; +ex3_drop_ld <= ex3_load_type_q and not (ex3_l2_lock_set or ex3_lock_instr_q or spr_xucr0_dcdis_q); +ex3_drop_touch_int <= ex3_l2_op_q and (ex3_blk_touch or (ex3_cache_inhibited and ex3_c_inh_drop_op_q)); + +ex3DropCacheB : ex3_drop_cacheable_b <= not (ex3_drop_ld and ex3_cache_enabled); +ex3DropCache : ex3_drop_cacheable <= not ex3_drop_cacheable_b; +ex3DropLd : ex3_drop_ld_req_b <= not ((ex3_hit and ex3_drop_cacheable) or ex3_drop_touch_int); + +ex3_ldq_potential_flush <= ex3_ld_queue_full and ex3_l2load_type_q and cache_acc_ex3_q; +ex3_stq_full_flush <= ex3_stq_flush and ex3_ldstq_instr_q; +ex3_lsq_ig_flush <= ex3_ig_flush and cache_acc_ex3_q; +ex3_lsq_flush <= ex3_stq_full_flush or ex3_lsq_ig_flush; + +with spr_xucr0_wlck_q select + way_lck_rmt <= x"FFFFFFFF" when '0', + xucr2_reg_q when others; + + +ex4_c_inh_d <= ex3_cache_inhibited; +ex4_opsize_d <= ex3_opsize_q(0 to 5); +ex4_rot_sel_d <= ex3_rot_sel(0 to 4); +ex4_data_swap_val_d <= ex3_data_swap_val; +ex4_algebraic_d <= ex3_algebraic_q; +ex4_lock_en_d <= ex3_dcbtls_instr_q or ex3_dcbtstls_instr_q; + +ex4_ld_entry <= ex4_c_inh_q & ex4_opsize_q & ex4_rot_sel_q & ex4_target_gpr_q & ex4_axu_op_val_q & ex4_data_swap_val_q & ex4_algebraic_q & ex4_lock_en_q & ex4_watch_en_q & ex4_p_addr_q; + + +dir_arr_rd_cntrl <= xudbg0_wen & dir_arr_rd_done; + +with dir_arr_rd_cntrl select + dir_arr_rd_val_d <= lsu_slowspr_data_q(62) when "10", + '0' when "01", + dir_arr_rd_val_q when others; + +dir_arr_rd_is0_val_d <= dir_arr_rd_val_q; +dir_arr_rd_is1_val_d <= dir_arr_rd_is0_val_q; +dir_arr_rd_is2_val_d <= dir_arr_rd_is1_val_q; +dir_arr_rd_rf0_val_d <= dir_arr_rd_is2_val_q; +dir_arr_rd_rf1_val_d <= dir_arr_rd_rf0_val_q; + +dir_arr_rd_done <= dir_arr_rd_is2_val_q and not (is2_l2_inv_val or dir_arr_rd_rf0_done_q or dir_arr_rd_rf1_done_q or + dir_arr_rd_ex1_done_q or dir_arr_rd_ex2_done_q); + +dir_arr_rd_rf0_done_d <= dir_arr_rd_done; +dir_arr_rd_rf1_done_d <= dir_arr_rd_rf0_done_q; +dir_arr_rd_ex1_done_d <= dir_arr_rd_rf1_done_q; +dir_arr_rd_ex2_done_d <= dir_arr_rd_ex1_done_q; +dir_arr_rd_ex3_done_d <= dir_arr_rd_ex2_done_q; +dir_arr_rd_ex4_done_d <= dir_arr_rd_ex3_done_q; + +with dir_arr_rd_cntrl select + xudbg0_done_reg_d <= lsu_slowspr_data_q(63) when "10", + '1' when "01", + xudbg0_done_reg_q when others; + +with xudbg0_reg_q(0 to 2) select + dir_arr_rd_tag <= ex3_wayA_tag when "000", + ex3_wayB_tag when "001", + ex3_wayC_tag when "010", + ex3_wayD_tag when "011", + ex3_wayE_tag when "100", + ex3_wayF_tag when "101", + ex3_wayG_tag when "110", + ex3_wayH_tag when others; + + with xudbg0_reg_q(0 to 2) select + dir_arr_rd_directory <= ex4_way_a_dir when "000", + ex4_way_b_dir when "001", + ex4_way_c_dir when "010", + ex4_way_d_dir when "011", + ex4_way_e_dir when "100", + ex4_way_f_dir when "101", + ex4_way_g_dir when "110", + ex4_way_h_dir when others; + + with xudbg0_reg_q(0 to 2) select + dir_arr_rd_parity <= ex3_way_tag_par_a when "000", + ex3_way_tag_par_b when "001", + ex3_way_tag_par_c when "010", + ex3_way_tag_par_d when "011", + ex3_way_tag_par_e when "100", + ex3_way_tag_par_f when "101", + ex3_way_tag_par_g when "110", + ex3_way_tag_par_h when others; + +dir_arr_rd_lru <= ex4_dir_lru; + + +lsu_slowspr_val_d <= xu_lsu_slowspr_val; +lsu_slowspr_rw_d <= xu_lsu_slowspr_rw; +lsu_slowspr_etid_d <= xu_lsu_slowspr_etid; +lsu_slowspr_addr_d <= xu_lsu_slowspr_addr; +lsu_slowspr_data_d <= xu_lsu_slowspr_data; +lsu_slowspr_done_d <= xu_lsu_slowspr_done; + +mm_slowspr_val_d <= lsu_slowspr_val_q; +mm_slowspr_rw_d <= lsu_slowspr_rw_q; +mm_slowspr_etid_d <= lsu_slowspr_etid_q; +mm_slowspr_addr_d <= lsu_slowspr_addr_q; + +xucr2_sel <= (lsu_slowspr_addr_q = XUCR2_ADDR); +dvc1_sel <= (lsu_slowspr_addr_q = DVC1_ADDR); +dvc2_sel <= (lsu_slowspr_addr_q = DVC2_ADDR); +eplc_sel <= (lsu_slowspr_addr_q = EPLC_ADDR); +epsc_sel <= (lsu_slowspr_addr_q = EPSC_ADDR); +xudbg0_sel <= (lsu_slowspr_addr_q = XUDBG0_ADDR); +xudbg1_sel <= (lsu_slowspr_addr_q = XUDBG1_ADDR); +xudbg2_sel <= (lsu_slowspr_addr_q = XUDBG2_ADDR); + + +xucr2_wen <= lsu_slowspr_val_q and xucr2_sel and not lsu_slowspr_rw_q; +xucr2_reg_d <= lsu_slowspr_data_q(32 to 63); + +xucr2_reg(32 to 63) <= xucr2_reg_q; + +dvc1_wen <= lsu_slowspr_val_q and dvc1_sel and not lsu_slowspr_rw_q; +dvc1_act_d <= dvc1_wen; +dvc1_reg_d <= lsu_slowspr_data_q; + +dvc1_reg <= dvc1_reg_q; + +dvc2_wen <= lsu_slowspr_val_q and dvc2_sel and not lsu_slowspr_rw_q; +dvc2_act_d <= dvc2_wen; +dvc2_reg_d <= lsu_slowspr_data_q; + +dvc2_reg <= dvc2_reg_q; + +xudbg0_wen <= lsu_slowspr_val_q and xudbg0_sel and not (lsu_slowspr_rw_q or dir_arr_rd_val_q); +xudbg0_reg_d <= lsu_slowspr_data_q(49 to 51) & lsu_slowspr_data_q(53 to 57); + +xudbg0_reg(64-(2**regmode) to 48) <= (others=>'0'); +xudbg0_reg(49 to 63) <= xudbg0_reg_q(0 to 2) & '0' & xudbg0_reg_q(3 to 7) & "00000" & xudbg0_done_reg_q; + +xudbg1_dir_reg_d <= dir_arr_rd_directory & dir_arr_rd_lru; +xudbg1_parity_reg_d <= dir_arr_rd_parity; + +xudbg1_reg(64-(2**regmode) to 44) <= (others=>'0'); +xudbg1_reg(45 to 63) <= xudbg1_dir_reg_q(2 to 12) & xudbg1_parity_reg_q & "00" & xudbg1_dir_reg_q(1) & xudbg1_dir_reg_q(0); + +xudbg2_reg_d <= dir_arr_rd_tag; + +xudbg2_reg(32 to 63) <= '0' & xudbg2_reg_q; + +eplc_wrt_data <= lsu_slowspr_data_q(32 to 34) & lsu_slowspr_data_q(40 to 47) & lsu_slowspr_data_q(50 to 63); +epsc_wrt_data <= lsu_slowspr_data_q(32 to 34) & lsu_slowspr_data_q(40 to 47) & lsu_slowspr_data_q(50 to 63); +eplc_t0_wen <= lsu_slowspr_val_q and eplc_sel and not lsu_slowspr_rw_q and (lsu_slowspr_etid_q = "00"); +eplc_t0_hyp_wen <= eplc_t0_wen and hypervisor_state(0); + +eplc_t0_reg_d(0 to 1) <= eplc_wrt_data(0 to 1); +eplc_t0_reg_d(2 to 10) <= eplc_wrt_data(2 to 10); +eplc_t0_reg_d(11 to 24) <= eplc_wrt_data(11 to 24); + +eplc_t0_reg <= eplc_t0_reg_q; + +epsc_t0_wen <= lsu_slowspr_val_q and epsc_sel and not lsu_slowspr_rw_q and (lsu_slowspr_etid_q = "00"); +epsc_t0_hyp_wen <= epsc_t0_wen and hypervisor_state(0); + +epsc_t0_reg_d(0 to 1) <= epsc_wrt_data(0 to 1); +epsc_t0_reg_d(2 to 10) <= epsc_wrt_data(2 to 10); +epsc_t0_reg_d(11 to 24) <= epsc_wrt_data(11 to 24); + +epsc_t0_reg <= epsc_t0_reg_q; + +eplc_t1_wen <= lsu_slowspr_val_q and eplc_sel and not lsu_slowspr_rw_q and (lsu_slowspr_etid_q = "01"); +eplc_t1_hyp_wen <= eplc_t1_wen and hypervisor_state(1); + +eplc_t1_reg_d(0 to 1) <= eplc_wrt_data(0 to 1); +eplc_t1_reg_d(2 to 10) <= eplc_wrt_data(2 to 10); +eplc_t1_reg_d(11 to 24) <= eplc_wrt_data(11 to 24); + +eplc_t1_reg <= eplc_t1_reg_q; + +epsc_t1_wen <= lsu_slowspr_val_q and epsc_sel and not lsu_slowspr_rw_q and (lsu_slowspr_etid_q = "01"); +epsc_t1_hyp_wen <= epsc_t1_wen and hypervisor_state(1); + +epsc_t1_reg_d(0 to 1) <= epsc_wrt_data(0 to 1); +epsc_t1_reg_d(2 to 10) <= epsc_wrt_data(2 to 10); +epsc_t1_reg_d(11 to 24) <= epsc_wrt_data(11 to 24); + +epsc_t1_reg <= epsc_t1_reg_q; + +eplc_t2_wen <= lsu_slowspr_val_q and eplc_sel and not lsu_slowspr_rw_q and (lsu_slowspr_etid_q = "10"); +eplc_t2_hyp_wen <= eplc_t2_wen and hypervisor_state(2); + +eplc_t2_reg_d(0 to 1) <= eplc_wrt_data(0 to 1); +eplc_t2_reg_d(2 to 10) <= eplc_wrt_data(2 to 10); +eplc_t2_reg_d(11 to 24) <= eplc_wrt_data(11 to 24); + +eplc_t2_reg <= eplc_t2_reg_q; + +epsc_t2_wen <= lsu_slowspr_val_q and epsc_sel and not lsu_slowspr_rw_q and (lsu_slowspr_etid_q = "10"); +epsc_t2_hyp_wen <= epsc_t2_wen and hypervisor_state(2); + +epsc_t2_reg_d(0 to 1) <= epsc_wrt_data(0 to 1); +epsc_t2_reg_d(2 to 10) <= epsc_wrt_data(2 to 10); +epsc_t2_reg_d(11 to 24) <= epsc_wrt_data(11 to 24); + +epsc_t2_reg <= epsc_t2_reg_q; + +eplc_t3_wen <= lsu_slowspr_val_q and eplc_sel and not lsu_slowspr_rw_q and (lsu_slowspr_etid_q = "11"); +eplc_t3_hyp_wen <= eplc_t3_wen and hypervisor_state(3); + +eplc_t3_reg_d(0 to 1) <= eplc_wrt_data(0 to 1); +eplc_t3_reg_d(2 to 10) <= eplc_wrt_data(2 to 10); +eplc_t3_reg_d(11 to 24) <= eplc_wrt_data(11 to 24); + +eplc_t3_reg <= eplc_t3_reg_q; + +epsc_t3_wen <= lsu_slowspr_val_q and epsc_sel and not lsu_slowspr_rw_q and (lsu_slowspr_etid_q = "11"); +epsc_t3_hyp_wen <= epsc_t3_wen and hypervisor_state(3); + +epsc_t3_reg_d(0 to 1) <= epsc_wrt_data(0 to 1); +epsc_t3_reg_d(2 to 10) <= epsc_wrt_data(2 to 10); +epsc_t3_reg_d(11 to 24) <= epsc_wrt_data(11 to 24); + +epsc_t3_reg <= epsc_t3_reg_q; + +eplc_wr_d(0 to 3) <= eplc_t0_wen & eplc_t1_wen & eplc_t2_wen & eplc_t3_wen; +epsc_wr_d(0 to 3) <= epsc_t0_wen & epsc_t1_wen & epsc_t2_wen & epsc_t3_wen; + +with lsu_slowspr_etid_q select + eplc_thrd_reg <= eplc_t0_reg when "00", + eplc_t1_reg when "01", + eplc_t2_reg when "10", + eplc_t3_reg when others; + +eplc_reg(32 to 63) <= eplc_thrd_reg(0 to 2) & "00000" & eplc_thrd_reg(3 to 10) & "00" & eplc_thrd_reg(11 to 24); + +with lsu_slowspr_etid_q select + epsc_thrd_reg <= epsc_t0_reg when "00", + epsc_t1_reg when "01", + epsc_t2_reg when "10", + epsc_t3_reg when others; + +epsc_reg(32 to 63) <= epsc_thrd_reg(0 to 2) & "00000" & epsc_thrd_reg(3 to 10) & "00" & epsc_thrd_reg(11 to 24); + +gen64mode : if (2**regmode = 64) generate begin + xudbg2_reg(64-(2**REGMODE) to 31) <= (others=>'0'); + eplc_reg(64-(2**REGMODE) to 31) <= (others=>'0'); + epsc_reg(64-(2**REGMODE) to 31) <= (others=>'0'); + xucr2_reg(64-(2**REGMODE) to 31) <= (others=>'0'); +end generate gen64mode; + +spr_l1dc_rd_val <= (xucr2_sel or dvc1_sel or dvc2_sel or eplc_sel or epsc_sel or xudbg0_sel or xudbg1_sel or xudbg2_sel) and lsu_slowspr_val_q and lsu_slowspr_rw_q; +spr_l1dc_reg <= gate(xucr2_reg, xucr2_sel) or gate(dvc1_reg, dvc1_sel) or gate(dvc2_reg, dvc2_sel) or + gate(eplc_reg, eplc_sel) or gate(epsc_reg, epsc_sel) or gate(xudbg0_reg, xudbg0_sel) or + gate(xudbg1_reg, xudbg1_sel) or gate(xudbg2_reg, xudbg2_sel); + +with spr_l1dc_rd_val select + mm_slowspr_data_d <= spr_l1dc_reg when '1', + lsu_slowspr_data_q when others; + +mm_slowspr_done_d <= xucr2_wen or dvc1_wen or dvc2_wen or xudbg0_wen or spr_l1dc_rd_val or lsu_slowspr_done_q; + + +rel_upd_gpr_d <= ldq_rel_upd_gpr; +rel_axu_op_val_d <= ldq_rel_axu_val; +rel_thrd_id_d <= ldq_rel_thrd_id; +rel_ta_gpr_d <= ldq_rel_ta_gpr; + +axu_rel_wren_d <= rel_axu_op_val_q; +axu_rel_wren_stg1_d <= axu_rel_wren_q and rel_upd_gpr_q; +rel_axu_tid_d <= rel_thrd_id_q; +rel_axu_tid_stg1_d <= rel_axu_tid_q; +rel_axu_ta_gpr_d <= rel_ta_gpr_q; +rel_axu_ta_gpr_stg1_d <= rel_axu_ta_gpr_q; + +with axu_rel_wren_stg1_q select + reg_upd_thrd_id <= rel_axu_tid_stg1_q when '1', + ex4_thrd_id_q when others; + +with axu_rel_wren_stg1_q select + reg_upd_ta_gpr <= rel_axu_ta_gpr_stg1_q when '1', + ex4_target_gpr_q when others; + +xu_wren <= (ex4_load_hit and not ex4_axu_op_val_q) or ex4_tgpr_instr; +axu_wren <= axu_rel_wren_stg1_q or (ex4_load_hit and ex4_axu_op_val_q) or ex4_taxu_instr; + +ex5_xu_wren_d <= xu_wren; +rel_xu_ta_gpr_d <= rel_ta_gpr_q(1 to 8); + +ex5_axu_rel_val_stg1_d <= axu_rel_wren_q and rel_upd_gpr_q; +ex5_axu_rel_val_stg2_d <= ex5_axu_rel_val_stg1_q; +ex5_axu_wren_d <= gate(reg_upd_thrd_id,axu_wren); +ex5_axu_wren_val <= or_reduce(ex5_axu_wren_q); +ex5_axu_ta_gpr_d <= reg_upd_ta_gpr; + + +perf_com_loadmiss <= cache_acc_ex5_q and ex5_load_instr_q and ex5_load_miss_q and not ex5_stg_flush; +perf_com_loads <= cache_acc_ex5_q and ex5_load_instr_q and not ex5_cache_inh_q and not ex5_stg_flush; +perf_com_cinh_loads <= cache_acc_ex5_q and ex5_load_instr_q and ex5_cache_inh_q and not ex5_stg_flush; +perf_com_dcbt_hit <= cache_acc_ex5_q and ex5_perf_dcbt_q and ex5_load_hit_q and not ex5_stg_flush; +perf_com_dcbt_sent <= cache_acc_ex5_q and ex5_perf_dcbt_q and ex5_load_miss_q and not ex5_stg_flush; +perf_com_axu_load <= cache_acc_ex5_q and ex5_axu_op_val_q and ex5_load_instr_q and not ex5_stg_flush; +perf_com_stores <= cache_acc_ex5_q and ex5_store_instr_q and not ex5_stg_flush; +perf_com_store_miss <= cache_acc_ex5_q and ex5_store_miss_q and not ex5_stg_flush; +perf_com_stcx_exec <= cache_acc_ex5_q and ex5_store_instr_q and ex5_lock_instr_q and not ex5_stg_flush; +perf_com_axu_store <= cache_acc_ex5_q and ex5_axu_op_val_q and ex5_store_instr_q and not ex5_stg_flush; +perf_com_watch_clr <= cache_acc_ex5_q and ex5_wclr_instr_q and not ex5_stg_flush; +perf_com_wclr_lfld <= cache_acc_ex5_q and ex5_wclr_instr_q and ex5_wclr_set_q and not ex5_stg_flush; +perf_com_watch_set <= cache_acc_ex5_q and ex5_watch_en_q and not ex5_stg_flush; + +perf_lsu_events_d <= ex5_thrd_id_q & perf_com_stores & perf_com_store_miss & perf_com_loadmiss & perf_com_cinh_loads & + perf_com_loads & perf_com_dcbt_sent & perf_com_dcbt_hit & perf_com_axu_load & + perf_com_axu_store & perf_com_stcx_exec & perf_com_watch_clr & perf_com_wclr_lfld & + perf_com_watch_set; + +my_spare0_latches_d <= not my_spare0_latches_q; +my_spare1_latches_d <= not my_spare1_latches_q; + + +ex1_src0_vld <= ex1_src0_vld_q and not ex1_stg_flush; +ex1_src0_reg <= ex1_src0_reg_q; +ex1_src1_vld <= ex1_src1_vld_q and not ex1_stg_flush; +ex1_src1_reg <= ex1_src1_reg_q; +ex1_targ_vld <= ex1_targ_vld_q and not ex1_stg_flush; +ex1_targ_reg <= ex1_targ_reg_q; +ex1_check_watch <= gate((ex1_thrd_id_q), (ex1_watch_clr_all or ex1_wchk_instr_q)); + +ex1_lsu_64bit_agen <= ex1_lsu_64bit_agen_q; +ex1_frc_align32 <= ex1_ldst_falign_q and ex1_optype32_q; +ex1_frc_align16 <= ex1_ldst_falign_q and ex1_optype16_q; +ex1_frc_align8 <= ex1_ldst_falign_q and ex1_optype8_q; +ex1_frc_align4 <= ex1_ldst_falign_q and ex1_optype4_q; +ex1_frc_align2 <= ex1_ldst_falign_q and ex1_optype2_q; +ex1_optype1 <= ex1_optype1_q; +ex1_optype2 <= ex1_optype2_q; +ex1_optype4 <= ex1_optype4_q; +ex1_optype8 <= ex1_optype8_q; +ex1_optype16 <= ex1_optype16_q; +ex1_optype32 <= ex1_optype32_q; +ex1_saxu_instr <= ex1_saxu_instr_q; +ex1_sdp_instr <= ex1_sdp_instr_q; +ex1_stgpr_instr <= ex1_sgpr_instr_q or ex1_tgpr_instr_q; +ex1_store_instr <= ex1_store_instr_q; +ex1_axu_op_val <= ex1_axu_op_val_q; +ex2_optype2 <= ex2_optype2_q; +ex2_optype4 <= ex2_optype4_q; +ex2_optype8 <= ex2_optype8_q; +ex2_optype16 <= ex2_optype16_q; +ex2_optype32 <= ex2_optype32_q; +ex2_icswx_type <= ex2_icswx_instr_q or ex2_icswx_dot_instr_q or ex2_icswx_epid_q; +ex2_store_instr <= ex2_store_instr_q and cache_acc_ex2_q; +ex1_dir_acc_val <= ex1_dir_acc_val_q; +ex2_cache_acc <= cache_acc_ex2_q; +ex3_cache_acc <= cache_acc_ex3_q; +ex2_ldst_fexcpt <= ex2_ldst_fexcpt_q; +ex2_axu_op <= ex2_axu_op_val_q; +ex2_mv_reg_op <= ex2_tgpr_instr_q or ex2_taxu_instr_q or ex2_tdp_instr_q; +ex1_thrd_id <= ex1_thrd_id_q; +ex2_thrd_id <= ex2_thrd_id_q; +ex3_thrd_id <= ex3_thrd_id_q; +ex4_thrd_id <= ex4_thrd_id_q; +ex5_thrd_id <= ex5_thrd_id_q; +ex3_targ_match_b1 <= (ex3_targ_match_b1_q and ex4_snd_ld_l2); +ex2_targ_match_b2 <= (ex2_targ_match_b2_q and ex4_snd_ld_l2); +ex2_load_instr <= ex2_load_instr_q; +ex3_dcbt_instr <= ex3_dcbt_instr_q or ex3_c_dcbtls; +ex3_dcbtst_instr <= ex3_dcbtst_instr_q or ex3_c_dcbtstls; +ex3_th_fld_l2 <= ex3_th_fld_l2_q; +ex3_dcbst_instr <= ex3_dcbst_instr_q; +ex3_dcbf_instr <= ex3_dcbf_instr_q; +ex3_sync_instr <= ex3_sync_instr_q; +ex3_mtspr_trace <= ex3_mtspr_trace_q; +ex3_byte_en <= ex3_byte_en_q; +ex2_l_fld <= ex2_l_fld_q; +ex3_l_fld <= ex3_l_fld_q; +ex3_dcbi_instr <= ex3_dcbi_instr_q; +ex2_dcbz_instr <= ex2_dcbz_instr_q; +ex3_dcbz_instr <= ex3_dcbz_instr_q; +ex3_icbi_instr <= ex3_icbi_instr_q; +ex3_icswx_instr <= ex3_icswx_instr_q; +ex3_icswx_dot <= ex3_icswx_dot_instr_q; +ex3_icswx_epid <= ex3_icswx_epid_q; +ex3_mbar_instr <= ex3_mbar_instr_q; +ex3_msgsnd_instr <= ex3_msgsnd_instr_q; +ex3_dci_instr <= ex3_dci_instr_q; +ex3_ici_instr <= ex3_ici_instr_q; +ex2_lock_instr <= ex2_lock_instr_q and cache_acc_ex2_q; +ex3_load_instr <= ex3_l2load_type_q; +ex3_store_instr <= ex3_store_instr_q; +ex3_dcbtls_instr <= ex3_l2_dcbtls; +ex3_dcbtstls_instr <= ex3_l2_dcbtstls; +ex3_dcblc_instr <= ex3_dcblc_instr_q; +ex3_icblc_instr <= ex3_icblc_l2_instr_q; +ex3_icbt_instr <= ex3_icbt_l2_instr_q or ex3_c_icbtls; +ex3_icbtls_instr <= ex3_l2_icbtls; +ex3_tlbsync_instr <= ex3_tlbsync_instr_q; +ex3_local_dcbf <= ex3_local_dcbf_q; +ex2_no_lru_upd <= no_lru_upd; +ex2_is_inval_op <= is_inval_op and cache_acc_ex2_q; +ex2_lock_set <= is_lock_set and cache_acc_ex2_q; +ex2_lock_clr <= is_lock_clr and cache_acc_ex2_q; +ex2_ddir_acc_instr <= ddir_acc_instr and cache_acc_ex2_q and not ex2_stg_flush; +ex3_cache_inh <= ex3_cache_inhibited; +ex3_cache_en <= ex3_cache_enabled; +ex4_store_hit <= ex4_store_commit_q and not ex4_miss; +ex4_load_op_hit <= ex4_load_commit_q and not ex4_miss; +ex5_load_op_hit <= ex5_load_hit_q; +ex4_axu_op_val <= ex4_axu_op_val_q; +ex4_drop_rel <= ex4_cacheable_linelock_q and not ex4_miss; +ex3_load_l1hit <= ex3_load_instr_q and ex3_spr_xucr0_flh2l2_q and ex3_cache_enabled; +ex3_lock_en <= ex3_dcbtls_instr_q or ex3_dcbtstls_instr_q; +ex3_req_thrd_id <= ex3_thrd_id_q; +ex3_target_gpr <= ex3_target_gpr_q; +ex3_axu_op_val <= ex3_axu_op_val_q; +ex3_algebraic <= ex3_algebraic_q; +ex3_p_addr_lwr <= ex3_p_addr_lwr_q(58 to 63); +ex3_opsize <= ex3_opsize_q; +ex3_rotate_sel <= ex3_rot_sel; +ex2_ldawx_instr <= ex2_ldawx_instr_q and cache_acc_ex2_q; +ex2_wclr_instr <= ex2_wclr_instr_q and cache_acc_ex2_q; +ex2_wchk_val <= ex2_wchk_instr_q; +ex3_watch_en <= ex3_watch_en_q; +ex3_data_swap <= ex3_data_swap_val; +ex3_load_val <= ex3_load_instr_q and cache_acc_ex3_q; +ex3_blkable_touch <= ex3_blkable_touch_q and ex3_cacc_q; +ex7_targ_match <= ex7_targ_match_q; +ex8_targ_match <= ex8_targ_match_q; + +rel_upd_dcarr_val <= rel_upd_dcarr_q; + +lsu_xu_need_hole <= dir_arr_rd_val_q; + +spr_dvc1_act <= dvc1_act_q; +spr_dvc2_act <= dvc2_act_q; +spr_dvc1_dbg <= dvc1_reg_q; +spr_dvc2_dbg <= dvc2_reg_q; +spr_xucr2_rmt <= way_lck_rmt; +spr_xucr0_wlck <= spr_xucr0_wlck_cpy_q; + +ex3_l_s_q_val <= l_s_q_val; +ex3_drop_ld_req <= not ex3_drop_ld_req_b; +ex3_drop_touch <= ex3_drop_touch_int; +ex3_stx_instr <= stx_instr; +ex3_larx_instr <= larx_instr; +ex3_mutex_hint <= ex3_mutex_hint_q; + +lsu_xu_ex4_cr_upd <= cache_acc_ex4_q and ex4_watch_en_q; +lsu_xu_ex5_wren <= ex5_xu_wren_q; +lsu_xu_rel_wren <= rel_upd_gpr_q and not axu_rel_wren_q; +lsu_xu_rel_ta_gpr <= rel_xu_ta_gpr_q; +lsu_xu_perf_events <= perf_lsu_events_q; + +slowspr_val_out <= mm_slowspr_val_q; +slowspr_rw_out <= mm_slowspr_rw_q; +slowspr_etid_out <= mm_slowspr_etid_q; +slowspr_addr_out <= mm_slowspr_addr_q; +slowspr_data_out <= mm_slowspr_data_q; +slowspr_done_out <= mm_slowspr_done_q; + +rf1_l2_inv_val <= rf1_l2_inv_val_q or dir_arr_rd_rf1_val_q; +ex1_agen_binv_val <= ex1_agen_binv_val_q; +ex1_l2_inv_val <= ex1_l2_inv_val_q; + +xu_derat_epsc_wr <= epsc_wr_q; +xu_derat_eplc_wr <= eplc_wr_q; +xu_derat_eplc0_epr <= eplc_t0_reg_q(0); +xu_derat_eplc0_eas <= eplc_t0_reg_q(1); +xu_derat_eplc0_egs <= eplc_t0_reg_q(2); +xu_derat_eplc0_elpid <= eplc_t0_reg_q(3 to 10); +xu_derat_eplc0_epid <= eplc_t0_reg_q(11 to 24); +xu_derat_eplc1_epr <= eplc_t1_reg_q(0); +xu_derat_eplc1_eas <= eplc_t1_reg_q(1); +xu_derat_eplc1_egs <= eplc_t1_reg_q(2); +xu_derat_eplc1_elpid <= eplc_t1_reg_q(3 to 10); +xu_derat_eplc1_epid <= eplc_t1_reg_q(11 to 24); +xu_derat_eplc2_epr <= eplc_t2_reg_q(0); +xu_derat_eplc2_eas <= eplc_t2_reg_q(1); +xu_derat_eplc2_egs <= eplc_t2_reg_q(2); +xu_derat_eplc2_elpid <= eplc_t2_reg_q(3 to 10); +xu_derat_eplc2_epid <= eplc_t2_reg_q(11 to 24); +xu_derat_eplc3_epr <= eplc_t3_reg_q(0); +xu_derat_eplc3_eas <= eplc_t3_reg_q(1); +xu_derat_eplc3_egs <= eplc_t3_reg_q(2); +xu_derat_eplc3_elpid <= eplc_t3_reg_q(3 to 10); +xu_derat_eplc3_epid <= eplc_t3_reg_q(11 to 24); +xu_derat_epsc0_epr <= epsc_t0_reg_q(0); +xu_derat_epsc0_eas <= epsc_t0_reg_q(1); +xu_derat_epsc0_egs <= epsc_t0_reg_q(2); +xu_derat_epsc0_elpid <= epsc_t0_reg_q(3 to 10); +xu_derat_epsc0_epid <= epsc_t0_reg_q(11 to 24); +xu_derat_epsc1_epr <= epsc_t1_reg_q(0); +xu_derat_epsc1_eas <= epsc_t1_reg_q(1); +xu_derat_epsc1_egs <= epsc_t1_reg_q(2); +xu_derat_epsc1_elpid <= epsc_t1_reg_q(3 to 10); +xu_derat_epsc1_epid <= epsc_t1_reg_q(11 to 24); +xu_derat_epsc2_epr <= epsc_t2_reg_q(0); +xu_derat_epsc2_eas <= epsc_t2_reg_q(1); +xu_derat_epsc2_egs <= epsc_t2_reg_q(2); +xu_derat_epsc2_elpid <= epsc_t2_reg_q(3 to 10); +xu_derat_epsc2_epid <= epsc_t2_reg_q(11 to 24); +xu_derat_epsc3_epr <= epsc_t3_reg_q(0); +xu_derat_epsc3_eas <= epsc_t3_reg_q(1); +xu_derat_epsc3_egs <= epsc_t3_reg_q(2); +xu_derat_epsc3_elpid <= epsc_t3_reg_q(3 to 10); +xu_derat_epsc3_epid <= epsc_t3_reg_q(11 to 24); + +dc_cntrl_dbg_data <= rel_upd_gpr_q & rel_ta_gpr_q & rel_axu_op_val_q & spr_xucr0_dcdis_q & + ex4_miss & ex5_axu_ta_gpr_q & is_mem_bar_op & ex3_l2_op_q & + ex1_ldst_falign_q & ex1_ldst_fexcpt_q & ex5_cache_inh_q & ex3_data_swap_val & + ex5_xu_wren_q & ex5_axu_wren_val & ex4_p_addr_q(64-real_data_add to 52) & + ex4_p_addr_q(58 to 61) & ex4_thrd_enc; + +ex1_stg_act <= ex1_stg_act_q; +ex2_stg_act <= ex2_stg_act_q; +ex3_stg_act <= ex3_stg_act_q; +ex4_stg_act <= ex4_stg_act_q; +ex5_stg_act <= ex5_stg_act_q; +binv1_stg_act <= binv1_stg_act_q; +binv2_stg_act <= binv2_stg_act_q; +binv3_stg_act <= binv3_stg_act_q; +binv4_stg_act <= binv4_stg_act_q; +binv5_stg_act <= binv5_stg_act_q; +rel1_stg_act <= rel1_stg_act_q; +rel2_stg_act <= ldq_rel_stg24_val; +rel3_stg_act <= rel3_stg_act_q; + +lsu_xu_spr_xucr0_cul <= ex5_unable_2lock_q; +spr_xucr0_cls <= spr_xucr0_cls_q; +agen_xucr0_cls <= agen_xucr0_cls_q; +dir_arr_rd_is2_val <= dir_arr_rd_is2_val_q; +dir_arr_rd_congr_cl <= xudbg0_reg_q(3 to 7); + +xu_fu_ex5_reload_val <= ex5_axu_rel_val_stg2_q; +xu_fu_ex5_load_val <= ex5_axu_wren_q; +xu_fu_ex5_load_tag <= ex5_axu_ta_gpr_q; + +xu_iu_ex6_icbi_val <= ex6_icbi_val_q; +xu_iu_ex6_icbi_addr <= ex6_p_addr_q; + +ex1_optype1_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_optype1_offset), + scout => sov(ex1_optype1_offset), + din => ex1_optype1_d, + dout => ex1_optype1_q); + +ex1_optype2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_optype2_offset), + scout => sov(ex1_optype2_offset), + din => ex1_optype2_d, + dout => ex1_optype2_q); + +ex1_optype4_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_optype4_offset), + scout => sov(ex1_optype4_offset), + din => ex1_optype4_d, + dout => ex1_optype4_q); + +ex1_optype8_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_optype8_offset), + scout => sov(ex1_optype8_offset), + din => ex1_optype8_d, + dout => ex1_optype8_q); + +ex1_optype16_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_optype16_offset), + scout => sov(ex1_optype16_offset), + din => ex1_optype16_d, + dout => ex1_optype16_q); + +ex1_optype32_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_optype32_offset), + scout => sov(ex1_optype32_offset), + din => ex1_optype32_d, + dout => ex1_optype32_q); + +ex2_optype1_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_optype1_d, + dout(0) => ex2_optype1_q); + +ex2_optype2_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_optype2_d, + dout(0) => ex2_optype2_q); + +ex2_optype4_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_optype4_d, + dout(0) => ex2_optype4_q); + +ex2_optype8_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_optype8_d, + dout(0) => ex2_optype8_q); + +ex2_optype16_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_optype16_d, + dout(0) => ex2_optype16_q); + +ex2_optype32_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_optype32_d, + dout(0) => ex2_optype32_q); + +ex1_dir_acc_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_dir_acc_val_offset), + scout => sov(ex1_dir_acc_val_offset), + din => ex1_dir_acc_val_d, + dout => ex1_dir_acc_val_q); + +cache_acc_ex1_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(cache_acc_ex1_offset), + scout => sov(cache_acc_ex1_offset), + din => cache_acc_ex1_d, + dout => cache_acc_ex1_q); + +cache_acc_ex2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(cache_acc_ex2_offset), + scout => sov(cache_acc_ex2_offset), + din => cache_acc_ex2_d, + dout => cache_acc_ex2_q); + +cache_acc_ex3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(cache_acc_ex3_offset), + scout => sov(cache_acc_ex3_offset), + din => cache_acc_ex3_d, + dout => cache_acc_ex3_q); + +cache_acc_ex4_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(cache_acc_ex4_offset), + scout => sov(cache_acc_ex4_offset), + din => cache_acc_ex4_d, + dout => cache_acc_ex4_q); + +cache_acc_ex5_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(cache_acc_ex5_offset), + scout => sov(cache_acc_ex5_offset), + din => cache_acc_ex5_d, + dout => cache_acc_ex5_q); + +ex2_cacc_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_cacc_offset), + scout => sov(ex2_cacc_offset), + din => ex2_cacc_d, + dout => ex2_cacc_q); + +ex3_cacc_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_cacc_offset), + scout => sov(ex3_cacc_offset), + din => ex3_cacc_d, + dout => ex3_cacc_q); + +ex1_thrd_id_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_thrd_id_offset to ex1_thrd_id_offset + ex1_thrd_id_d'length-1), + scout => sov(ex1_thrd_id_offset to ex1_thrd_id_offset + ex1_thrd_id_d'length-1), + din => ex1_thrd_id_d, + dout => ex1_thrd_id_q); + +ex2_thrd_id_reg: tri_regk +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex2_thrd_id_d, + dout => ex2_thrd_id_q); + +ex3_thrd_id_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_thrd_id_offset to ex3_thrd_id_offset + ex3_thrd_id_d'length-1), + scout => sov(ex3_thrd_id_offset to ex3_thrd_id_offset + ex3_thrd_id_d'length-1), + din => ex3_thrd_id_d, + dout => ex3_thrd_id_q); + +ex4_thrd_id_reg: tri_regk +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex4_thrd_id_d, + dout => ex4_thrd_id_q); + +ex5_thrd_id_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_thrd_id_offset to ex5_thrd_id_offset + ex5_thrd_id_d'length-1), + scout => sov(ex5_thrd_id_offset to ex5_thrd_id_offset + ex5_thrd_id_d'length-1), + din => ex5_thrd_id_d, + dout => ex5_thrd_id_q); + +ex1_target_gpr_reg: tri_rlmreg_p +generic map (width => 9, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_target_gpr_offset to ex1_target_gpr_offset + ex1_target_gpr_d'length-1), + scout => sov(ex1_target_gpr_offset to ex1_target_gpr_offset + ex1_target_gpr_d'length-1), + din => ex1_target_gpr_d, + dout => ex1_target_gpr_q); + +ex2_target_gpr_reg: tri_regk +generic map (width => 9, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex2_target_gpr_d, + dout => ex2_target_gpr_q); + +ex3_target_gpr_reg: tri_rlmreg_p +generic map (width => 9, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_target_gpr_offset to ex3_target_gpr_offset + ex3_target_gpr_d'length-1), + scout => sov(ex3_target_gpr_offset to ex3_target_gpr_offset + ex3_target_gpr_d'length-1), + din => ex3_target_gpr_d, + dout => ex3_target_gpr_q); + +ex4_target_gpr_reg: tri_regk +generic map (width => 9, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex4_target_gpr_d, + dout => ex4_target_gpr_q); + +ex1_dcbt_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_dcbt_instr_offset), + scout => sov(ex1_dcbt_instr_offset), + din => ex1_dcbt_instr_d, + dout => ex1_dcbt_instr_q); + +ex2_dcbt_instr_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_dcbt_instr_d, + dout(0) => ex2_dcbt_instr_q); + +ex3_dcbt_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_dcbt_instr_offset), + scout => sov(ex3_dcbt_instr_offset), + din => ex3_dcbt_instr_d, + dout => ex3_dcbt_instr_q); + +ex1_dcbtst_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_dcbtst_instr_offset), + scout => sov(ex1_dcbtst_instr_offset), + din => ex1_dcbtst_instr_d, + dout => ex1_dcbtst_instr_q); + +ex2_dcbtst_instr_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_dcbtst_instr_d, + dout(0) => ex2_dcbtst_instr_q); + +ex3_dcbtst_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_dcbtst_instr_offset), + scout => sov(ex3_dcbtst_instr_offset), + din => ex3_dcbtst_instr_d, + dout => ex3_dcbtst_instr_q); + +ex1_dcbst_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_dcbst_instr_offset), + scout => sov(ex1_dcbst_instr_offset), + din => ex1_dcbst_instr_d, + dout => ex1_dcbst_instr_q); + +ex2_dcbst_instr_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_dcbst_instr_d, + dout(0) => ex2_dcbst_instr_q); + +ex3_dcbst_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_dcbst_instr_offset), + scout => sov(ex3_dcbst_instr_offset), + din => ex3_dcbst_instr_d, + dout => ex3_dcbst_instr_q); + +ex1_dcbf_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_dcbf_instr_offset), + scout => sov(ex1_dcbf_instr_offset), + din => ex1_dcbf_instr_d, + dout => ex1_dcbf_instr_q); + +ex2_dcbf_instr_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_dcbf_instr_d, + dout(0) => ex2_dcbf_instr_q); + +ex3_dcbf_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_dcbf_instr_offset), + scout => sov(ex3_dcbf_instr_offset), + din => ex3_dcbf_instr_d, + dout => ex3_dcbf_instr_q); + +ex1_sync_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_sync_instr_offset), + scout => sov(ex1_sync_instr_offset), + din => ex1_sync_instr_d, + dout => ex1_sync_instr_q); + +ex2_sync_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_sync_instr_offset), + scout => sov(ex2_sync_instr_offset), + din => ex2_sync_instr_d, + dout => ex2_sync_instr_q); + +ex3_sync_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_sync_instr_offset), + scout => sov(ex3_sync_instr_offset), + din => ex3_sync_instr_d, + dout => ex3_sync_instr_q); + +ex1_l_fld_reg: tri_rlmreg_p +generic map (width => 2, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_l_fld_offset to ex1_l_fld_offset + ex1_l_fld_d'length-1), + scout => sov(ex1_l_fld_offset to ex1_l_fld_offset + ex1_l_fld_d'length-1), + din => ex1_l_fld_d, + dout => ex1_l_fld_q); + +ex2_l_fld_reg: tri_regk +generic map (width => 2, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex2_l_fld_d, + dout => ex2_l_fld_q); + +ex3_l_fld_reg: tri_rlmreg_p +generic map (width => 2, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_l_fld_offset to ex3_l_fld_offset + ex3_l_fld_d'length-1), + scout => sov(ex3_l_fld_offset to ex3_l_fld_offset + ex3_l_fld_d'length-1), + din => ex3_l_fld_d, + dout => ex3_l_fld_q); + +ex1_dcbi_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_dcbi_instr_offset), + scout => sov(ex1_dcbi_instr_offset), + din => ex1_dcbi_instr_d, + dout => ex1_dcbi_instr_q); + +ex2_dcbi_instr_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_dcbi_instr_d, + dout(0) => ex2_dcbi_instr_q); + +ex3_dcbi_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_dcbi_instr_offset), + scout => sov(ex3_dcbi_instr_offset), + din => ex3_dcbi_instr_d, + dout => ex3_dcbi_instr_q); + +ex1_dcbz_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_dcbz_instr_offset), + scout => sov(ex1_dcbz_instr_offset), + din => ex1_dcbz_instr_d, + dout => ex1_dcbz_instr_q); + +ex2_dcbz_instr_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_dcbz_instr_d, + dout(0) => ex2_dcbz_instr_q); + +ex3_dcbz_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_dcbz_instr_offset), + scout => sov(ex3_dcbz_instr_offset), + din => ex3_dcbz_instr_d, + dout => ex3_dcbz_instr_q); + +ex1_icbi_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_icbi_instr_offset), + scout => sov(ex1_icbi_instr_offset), + din => ex1_icbi_instr_d, + dout => ex1_icbi_instr_q); + +ex2_icbi_instr_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_icbi_instr_d, + dout(0) => ex2_icbi_instr_q); + +ex3_icbi_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_icbi_instr_offset), + scout => sov(ex3_icbi_instr_offset), + din => ex3_icbi_instr_d, + dout => ex3_icbi_instr_q); + +ex4_icbi_instr_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex4_icbi_instr_d, + dout(0) => ex4_icbi_instr_q); + +ex5_icbi_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_icbi_instr_offset), + scout => sov(ex5_icbi_instr_offset), + din => ex5_icbi_instr_d, + dout => ex5_icbi_instr_q); + +ex1_mbar_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_mbar_instr_offset), + scout => sov(ex1_mbar_instr_offset), + din => ex1_mbar_instr_d, + dout => ex1_mbar_instr_q); + +ex2_mbar_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_mbar_instr_offset), + scout => sov(ex2_mbar_instr_offset), + din => ex2_mbar_instr_d, + dout => ex2_mbar_instr_q); + +ex3_mbar_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_mbar_instr_offset), + scout => sov(ex3_mbar_instr_offset), + din => ex3_mbar_instr_d, + dout => ex3_mbar_instr_q); + +ex1_algebraic_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_algebraic_offset), + scout => sov(ex1_algebraic_offset), + din => ex1_algebraic_d, + dout => ex1_algebraic_q); + +ex2_algebraic_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_algebraic_d, + dout(0) => ex2_algebraic_q); + +ex3_algebraic_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_algebraic_offset), + scout => sov(ex3_algebraic_offset), + din => ex3_algebraic_d, + dout => ex3_algebraic_q); + +ex1_byte_rev_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_byte_rev_offset), + scout => sov(ex1_byte_rev_offset), + din => ex1_byte_rev_d, + dout => ex1_byte_rev_q); + +ex2_byte_rev_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_byte_rev_d, + dout(0) => ex2_byte_rev_q); + +ex3_byte_rev_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_byte_rev_offset), + scout => sov(ex3_byte_rev_offset), + din => ex3_byte_rev_d, + dout => ex3_byte_rev_q); + +ex1_lock_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_lock_instr_offset), + scout => sov(ex1_lock_instr_offset), + din => ex1_lock_instr_d, + dout => ex1_lock_instr_q); + +ex2_lock_instr_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_lock_instr_d, + dout(0) => ex2_lock_instr_q); + +ex3_lock_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_lock_instr_offset), + scout => sov(ex3_lock_instr_offset), + din => ex3_lock_instr_d, + dout => ex3_lock_instr_q); + +ex4_lock_instr_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex4_lock_instr_d, + dout(0) => ex4_lock_instr_q); + +ex5_lock_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_lock_instr_offset), + scout => sov(ex5_lock_instr_offset), + din => ex5_lock_instr_d, + dout => ex5_lock_instr_q); + +ex1_mutex_hint_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_mutex_hint_offset), + scout => sov(ex1_mutex_hint_offset), + din => ex1_mutex_hint_d, + dout => ex1_mutex_hint_q); + +ex2_mutex_hint_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_mutex_hint_d, + dout(0) => ex2_mutex_hint_q); + +ex3_mutex_hint_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_mutex_hint_offset), + scout => sov(ex3_mutex_hint_offset), + din => ex3_mutex_hint_d, + dout => ex3_mutex_hint_q); + +ex1_load_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_load_instr_offset), + scout => sov(ex1_load_instr_offset), + din => ex1_load_instr_d, + dout => ex1_load_instr_q); + +ex2_load_instr_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_load_instr_d, + dout(0) => ex2_load_instr_q); + +ex3_load_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_load_instr_offset), + scout => sov(ex3_load_instr_offset), + din => ex3_load_instr_d, + dout => ex3_load_instr_q); + +ex4_load_instr_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex4_load_instr_d, + dout(0) => ex4_load_instr_q); + +ex5_load_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_load_instr_offset), + scout => sov(ex5_load_instr_offset), + din => ex5_load_instr_d, + dout => ex5_load_instr_q); + +ex1_store_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_store_instr_offset), + scout => sov(ex1_store_instr_offset), + din => ex1_store_instr_d, + dout => ex1_store_instr_q); + +ex2_store_instr_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_store_instr_d, + dout(0) => ex2_store_instr_q); + +ex3_store_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_store_instr_offset), + scout => sov(ex3_store_instr_offset), + din => ex3_store_instr_d, + dout => ex3_store_instr_q); + +ex3_l2_op_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_l2_op_offset), + scout => sov(ex3_l2_op_offset), + din => ex3_l2_op_d, + dout => ex3_l2_op_q); + +ex4_cache_inh_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex4_cache_inh_d, + dout(0) => ex4_cache_inh_q); + +ex5_cache_inh_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_cache_inh_offset), + scout => sov(ex5_cache_inh_offset), + din => ex5_cache_inh_d, + dout => ex5_cache_inh_q); + +ex3_opsize_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_opsize_offset to ex3_opsize_offset + ex3_opsize_d'length-1), + scout => sov(ex3_opsize_offset to ex3_opsize_offset + ex3_opsize_d'length-1), + din => ex3_opsize_d, + dout => ex3_opsize_q); + +ex1_axu_op_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_axu_op_val_offset), + scout => sov(ex1_axu_op_val_offset), + din => ex1_axu_op_val_d, + dout => ex1_axu_op_val_q); + +ex2_axu_op_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_axu_op_val_d, + dout(0) => ex2_axu_op_val_q); + +ex3_axu_op_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_axu_op_val_offset), + scout => sov(ex3_axu_op_val_offset), + din => ex3_axu_op_val_d, + dout => ex3_axu_op_val_q); + +ex4_axu_op_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex4_axu_op_val_d, + dout(0) => ex4_axu_op_val_q); + +ex5_axu_op_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_axu_op_val_offset), + scout => sov(ex5_axu_op_val_offset), + din => ex5_axu_op_val_d, + dout => ex5_axu_op_val_q); + +rel_upd_gpr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_upd_gpr_offset), + scout => sov(rel_upd_gpr_offset), + din => rel_upd_gpr_d, + dout => rel_upd_gpr_q); + +rel_axu_op_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_axu_op_val_offset), + scout => sov(rel_axu_op_val_offset), + din => rel_axu_op_val_d, + dout => rel_axu_op_val_q); + +rel_thrd_id_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_thrd_id_offset to rel_thrd_id_offset + rel_thrd_id_d'length-1), + scout => sov(rel_thrd_id_offset to rel_thrd_id_offset + rel_thrd_id_d'length-1), + din => rel_thrd_id_d, + dout => rel_thrd_id_q); + +rel_ta_gpr_reg: tri_rlmreg_p +generic map (width => 9, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_ta_gpr_offset to rel_ta_gpr_offset + rel_ta_gpr_d'length-1), + scout => sov(rel_ta_gpr_offset to rel_ta_gpr_offset + rel_ta_gpr_d'length-1), + din => rel_ta_gpr_d, + dout => rel_ta_gpr_q); + +ex4_load_commit_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_load_commit_offset), + scout => sov(ex4_load_commit_offset), + din => ex4_load_commit_d, + dout => ex4_load_commit_q); + +ex5_load_hit_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_load_hit_offset), + scout => sov(ex5_load_hit_offset), + din => ex5_load_hit_d, + dout => ex5_load_hit_q); + +ex5_axu_rel_val_stg1_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_axu_rel_val_stg1_offset), + scout => sov(ex5_axu_rel_val_stg1_offset), + din => ex5_axu_rel_val_stg1_d, + dout => ex5_axu_rel_val_stg1_q); + +ex5_axu_rel_val_stg2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_axu_rel_val_stg2_offset), + scout => sov(ex5_axu_rel_val_stg2_offset), + din => ex5_axu_rel_val_stg2_d, + dout => ex5_axu_rel_val_stg2_q); + +ex5_axu_wren_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_axu_wren_offset to ex5_axu_wren_offset + ex5_axu_wren_d'length-1), + scout => sov(ex5_axu_wren_offset to ex5_axu_wren_offset + ex5_axu_wren_d'length-1), + din => ex5_axu_wren_d, + dout => ex5_axu_wren_q); + +ex5_axu_ta_gpr_reg: tri_rlmreg_p +generic map (width => 9, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel4_ex4_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_axu_ta_gpr_offset to ex5_axu_ta_gpr_offset + ex5_axu_ta_gpr_d'length-1), + scout => sov(ex5_axu_ta_gpr_offset to ex5_axu_ta_gpr_offset + ex5_axu_ta_gpr_d'length-1), + din => ex5_axu_ta_gpr_d, + dout => ex5_axu_ta_gpr_q); + +rel_xu_ta_gpr_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ldq_rel_stg24_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_xu_ta_gpr_offset to rel_xu_ta_gpr_offset + rel_xu_ta_gpr_d'length-1), + scout => sov(rel_xu_ta_gpr_offset to rel_xu_ta_gpr_offset + rel_xu_ta_gpr_d'length-1), + din => rel_xu_ta_gpr_d, + dout => rel_xu_ta_gpr_q); + +lsu_slowspr_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(lsu_slowspr_val_offset), + scout => sov(lsu_slowspr_val_offset), + din => lsu_slowspr_val_d, + dout => lsu_slowspr_val_q); + +lsu_slowspr_rw_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_lsu_slowspr_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(lsu_slowspr_rw_offset), + scout => sov(lsu_slowspr_rw_offset), + din => lsu_slowspr_rw_d, + dout => lsu_slowspr_rw_q); + +lsu_slowspr_etid_reg: tri_rlmreg_p +generic map (width => 2, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_lsu_slowspr_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(lsu_slowspr_etid_offset to lsu_slowspr_etid_offset + lsu_slowspr_etid_d'length-1), + scout => sov(lsu_slowspr_etid_offset to lsu_slowspr_etid_offset + lsu_slowspr_etid_d'length-1), + din => lsu_slowspr_etid_d, + dout => lsu_slowspr_etid_q); + +lsu_slowspr_addr_reg: tri_rlmreg_p +generic map (width => 10, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_lsu_slowspr_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(lsu_slowspr_addr_offset to lsu_slowspr_addr_offset + lsu_slowspr_addr_d'length-1), + scout => sov(lsu_slowspr_addr_offset to lsu_slowspr_addr_offset + lsu_slowspr_addr_d'length-1), + din => lsu_slowspr_addr_d, + dout => lsu_slowspr_addr_q); + +lsu_slowspr_data_reg: tri_rlmreg_p +generic map (width => 2**REGMODE, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_lsu_slowspr_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(lsu_slowspr_data_offset to lsu_slowspr_data_offset + lsu_slowspr_data_d'length-1), + scout => sov(lsu_slowspr_data_offset to lsu_slowspr_data_offset + lsu_slowspr_data_d'length-1), + din => lsu_slowspr_data_d, + dout => lsu_slowspr_data_q); + +lsu_slowspr_done_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(lsu_slowspr_done_offset), + scout => sov(lsu_slowspr_done_offset), + din => lsu_slowspr_done_d, + dout => lsu_slowspr_done_q); + +mm_slowspr_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(mm_slowspr_val_offset), + scout => sov(mm_slowspr_val_offset), + din => mm_slowspr_val_d, + dout => mm_slowspr_val_q); + +mm_slowspr_rw_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lsu_slowspr_val_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(mm_slowspr_rw_offset), + scout => sov(mm_slowspr_rw_offset), + din => mm_slowspr_rw_d, + dout => mm_slowspr_rw_q); + +mm_slowspr_etid_reg: tri_rlmreg_p +generic map (width => 2, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lsu_slowspr_val_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(mm_slowspr_etid_offset to mm_slowspr_etid_offset + mm_slowspr_etid_d'length-1), + scout => sov(mm_slowspr_etid_offset to mm_slowspr_etid_offset + mm_slowspr_etid_d'length-1), + din => mm_slowspr_etid_d, + dout => mm_slowspr_etid_q); + +mm_slowspr_addr_reg: tri_rlmreg_p +generic map (width => 10, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lsu_slowspr_val_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(mm_slowspr_addr_offset to mm_slowspr_addr_offset + mm_slowspr_addr_d'length-1), + scout => sov(mm_slowspr_addr_offset to mm_slowspr_addr_offset + mm_slowspr_addr_d'length-1), + din => mm_slowspr_addr_d, + dout => mm_slowspr_addr_q); + +mm_slowspr_data_reg: tri_rlmreg_p +generic map (width => 2**REGMODE, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lsu_slowspr_val_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(mm_slowspr_data_offset to mm_slowspr_data_offset + mm_slowspr_data_d'length-1), + scout => sov(mm_slowspr_data_offset to mm_slowspr_data_offset + mm_slowspr_data_d'length-1), + din => mm_slowspr_data_d, + dout => mm_slowspr_data_q); + +mm_slowspr_done_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(mm_slowspr_done_offset), + scout => sov(mm_slowspr_done_offset), + din => mm_slowspr_done_d, + dout => mm_slowspr_done_q); + +ex1_th_fld_c_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_th_fld_c_offset), + scout => sov(ex1_th_fld_c_offset), + din => ex1_th_fld_c_d, + dout => ex1_th_fld_c_q); + +ex2_th_fld_c_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_th_fld_c_d, + dout(0) => ex2_th_fld_c_q); + +ex3_th_fld_c_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_th_fld_c_offset), + scout => sov(ex3_th_fld_c_offset), + din => ex3_th_fld_c_d, + dout => ex3_th_fld_c_q); + +ex1_th_fld_l2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_th_fld_l2_offset), + scout => sov(ex1_th_fld_l2_offset), + din => ex1_th_fld_l2_d, + dout => ex1_th_fld_l2_q); + +ex2_th_fld_l2_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_th_fld_l2_d, + dout(0) => ex2_th_fld_l2_q); + +ex3_th_fld_l2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_th_fld_l2_offset), + scout => sov(ex3_th_fld_l2_offset), + din => ex3_th_fld_l2_d, + dout => ex3_th_fld_l2_q); + +ex1_dcbtls_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_dcbtls_instr_offset), + scout => sov(ex1_dcbtls_instr_offset), + din => ex1_dcbtls_instr_d, + dout => ex1_dcbtls_instr_q); + +ex2_dcbtls_instr_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_dcbtls_instr_d, + dout(0) => ex2_dcbtls_instr_q); + +ex3_dcbtls_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_dcbtls_instr_offset), + scout => sov(ex3_dcbtls_instr_offset), + din => ex3_dcbtls_instr_d, + dout => ex3_dcbtls_instr_q); + +ex3_l2_request_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_l2_request_offset), + scout => sov(ex3_l2_request_offset), + din => ex3_l2_request_d, + dout => ex3_l2_request_q); + +ex1_dcbtstls_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_dcbtstls_instr_offset), + scout => sov(ex1_dcbtstls_instr_offset), + din => ex1_dcbtstls_instr_d, + dout => ex1_dcbtstls_instr_q); + +ex2_dcbtstls_instr_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_dcbtstls_instr_d, + dout(0) => ex2_dcbtstls_instr_q); + +ex3_dcbtstls_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_dcbtstls_instr_offset), + scout => sov(ex3_dcbtstls_instr_offset), + din => ex3_dcbtstls_instr_d, + dout => ex3_dcbtstls_instr_q); + +ex1_dcblc_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_dcblc_instr_offset), + scout => sov(ex1_dcblc_instr_offset), + din => ex1_dcblc_instr_d, + dout => ex1_dcblc_instr_q); + +ex2_dcblc_instr_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_dcblc_instr_d, + dout(0) => ex2_dcblc_instr_q); + +ex3_dcblc_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_dcblc_instr_offset), + scout => sov(ex3_dcblc_instr_offset), + din => ex3_dcblc_instr_d, + dout => ex3_dcblc_instr_q); + +ex1_icblc_l2_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_icblc_l2_instr_offset), + scout => sov(ex1_icblc_l2_instr_offset), + din => ex1_icblc_l2_instr_d, + dout => ex1_icblc_l2_instr_q); + +ex2_icblc_l2_instr_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_icblc_l2_instr_d, + dout(0) => ex2_icblc_l2_instr_q); + +ex3_icblc_l2_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_icblc_l2_instr_offset), + scout => sov(ex3_icblc_l2_instr_offset), + din => ex3_icblc_l2_instr_d, + dout => ex3_icblc_l2_instr_q); + +ex1_icbt_l2_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_icbt_l2_instr_offset), + scout => sov(ex1_icbt_l2_instr_offset), + din => ex1_icbt_l2_instr_d, + dout => ex1_icbt_l2_instr_q); + +ex2_icbt_l2_instr_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_icbt_l2_instr_d, + dout(0) => ex2_icbt_l2_instr_q); + +ex3_icbt_l2_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_icbt_l2_instr_offset), + scout => sov(ex3_icbt_l2_instr_offset), + din => ex3_icbt_l2_instr_d, + dout => ex3_icbt_l2_instr_q); + +ex1_icbtls_l2_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_icbtls_l2_instr_offset), + scout => sov(ex1_icbtls_l2_instr_offset), + din => ex1_icbtls_l2_instr_d, + dout => ex1_icbtls_l2_instr_q); + +ex2_icbtls_l2_instr_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_icbtls_l2_instr_d, + dout(0) => ex2_icbtls_l2_instr_q); + +ex3_icbtls_l2_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_icbtls_l2_instr_offset), + scout => sov(ex3_icbtls_l2_instr_offset), + din => ex3_icbtls_l2_instr_d, + dout => ex3_icbtls_l2_instr_q); + +ex1_tlbsync_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_tlbsync_instr_offset), + scout => sov(ex1_tlbsync_instr_offset), + din => ex1_tlbsync_instr_d, + dout => ex1_tlbsync_instr_q); + +ex2_tlbsync_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_tlbsync_instr_offset), + scout => sov(ex2_tlbsync_instr_offset), + din => ex2_tlbsync_instr_d, + dout => ex2_tlbsync_instr_q); + +ex3_tlbsync_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_tlbsync_instr_offset), + scout => sov(ex3_tlbsync_instr_offset), + din => ex3_tlbsync_instr_d, + dout => ex3_tlbsync_instr_q); + +ex1_src0_vld_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_src0_vld_offset), + scout => sov(ex1_src0_vld_offset), + din => ex1_src0_vld_d, + dout => ex1_src0_vld_q); + +ex1_src0_reg_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_src0_reg_offset to ex1_src0_reg_offset + ex1_src0_reg_d'length-1), + scout => sov(ex1_src0_reg_offset to ex1_src0_reg_offset + ex1_src0_reg_d'length-1), + din => ex1_src0_reg_d, + dout => ex1_src0_reg_q); + +ex1_src1_vld_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_src1_vld_offset), + scout => sov(ex1_src1_vld_offset), + din => ex1_src1_vld_d, + dout => ex1_src1_vld_q); + +ex1_src1_reg_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_src1_reg_offset to ex1_src1_reg_offset + ex1_src1_reg_d'length-1), + scout => sov(ex1_src1_reg_offset to ex1_src1_reg_offset + ex1_src1_reg_d'length-1), + din => ex1_src1_reg_d, + dout => ex1_src1_reg_q); + +ex1_targ_vld_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_targ_vld_offset), + scout => sov(ex1_targ_vld_offset), + din => ex1_targ_vld_d, + dout => ex1_targ_vld_q); + +ex1_targ_reg_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_targ_reg_offset to ex1_targ_reg_offset + ex1_targ_reg_d'length-1), + scout => sov(ex1_targ_reg_offset to ex1_targ_reg_offset + ex1_targ_reg_d'length-1), + din => ex1_targ_reg_d, + dout => ex1_targ_reg_q); + +ex5_instr_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_instr_val_offset), + scout => sov(ex5_instr_val_offset), + din => ex5_instr_val_d, + dout => ex5_instr_val_q); + +ex2_targ_match_b1_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_targ_match_b1_offset), + scout => sov(ex2_targ_match_b1_offset), + din => ex2_targ_match_b1_d, + dout => ex2_targ_match_b1_q); + +ex3_targ_match_b1_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_targ_match_b1_offset), + scout => sov(ex3_targ_match_b1_offset), + din => ex3_targ_match_b1_d, + dout => ex3_targ_match_b1_q); + +ex4_targ_match_b1_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_targ_match_b1_offset), + scout => sov(ex4_targ_match_b1_offset), + din => ex4_targ_match_b1_d, + dout => ex4_targ_match_b1_q); + +ex5_targ_match_b1_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_targ_match_b1_offset), + scout => sov(ex5_targ_match_b1_offset), + din => ex5_targ_match_b1_d, + dout => ex5_targ_match_b1_q); + +ex6_targ_match_b1_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_targ_match_b1_offset), + scout => sov(ex6_targ_match_b1_offset), + din => ex6_targ_match_b1_d, + dout => ex6_targ_match_b1_q); + +ex2_targ_match_b2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_targ_match_b2_offset), + scout => sov(ex2_targ_match_b2_offset), + din => ex2_targ_match_b2_d, + dout => ex2_targ_match_b2_q); + +ex3_targ_match_b2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_targ_match_b2_offset), + scout => sov(ex3_targ_match_b2_offset), + din => ex3_targ_match_b2_d, + dout => ex3_targ_match_b2_q); + +ex4_targ_match_b2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_targ_match_b2_offset), + scout => sov(ex4_targ_match_b2_offset), + din => ex4_targ_match_b2_d, + dout => ex4_targ_match_b2_q); + +ex5_targ_match_b2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_targ_match_b2_offset), + scout => sov(ex5_targ_match_b2_offset), + din => ex5_targ_match_b2_d, + dout => ex5_targ_match_b2_q); + +ex7_targ_match_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex7_targ_match_offset), + scout => sov(ex7_targ_match_offset), + din => ex7_targ_match_d, + dout => ex7_targ_match_q); + +ex8_targ_match_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex8_targ_match_offset), + scout => sov(ex8_targ_match_offset), + din => ex8_targ_match_d, + dout => ex8_targ_match_q); + +ex1_ldst_falign_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_ldst_falign_offset), + scout => sov(ex1_ldst_falign_offset), + din => ex1_ldst_falign_d, + dout => ex1_ldst_falign_q); + +ex1_ldst_fexcpt_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_ldst_fexcpt_offset), + scout => sov(ex1_ldst_fexcpt_offset), + din => ex1_ldst_fexcpt_d, + dout => ex1_ldst_fexcpt_q); + +ex2_ldst_fexcpt_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_ldst_fexcpt_d, + dout(0) => ex2_ldst_fexcpt_q); + +ex5_load_miss_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_load_miss_offset), + scout => sov(ex5_load_miss_offset), + din => ex5_load_miss_d, + dout => ex5_load_miss_q); + +xucr2_reg_a_reg : tri_ser_rlmreg_p +generic map (width => 16, init => 65535, expand_type => expand_type, needs_sreset => 1) +port map(vd => vdd, + gd => gnd, + nclk => nclk, + act => xucr2_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xucr2_reg_a_offset to xucr2_reg_a_offset + ((xucr2_reg_d'length)/2)-1), + scout => sov(xucr2_reg_a_offset to xucr2_reg_a_offset + ((xucr2_reg_d'length)/2)-1), + din => xucr2_reg_d(0 to 15), + dout => xucr2_reg_q(0 to 15)); + +xucr2_reg_b_reg: tri_ser_rlmreg_p +generic map (width => 16, init => 65535, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xucr2_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xucr2_reg_b_offset to xucr2_reg_b_offset + ((xucr2_reg_d'length)/2)-1), + scout => sov(xucr2_reg_b_offset to xucr2_reg_b_offset + ((xucr2_reg_d'length)/2)-1), + din => xucr2_reg_d(16 to 31), + dout => xucr2_reg_q(16 to 31)); + +dvc1_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dvc1_act_offset), + scout => sov(dvc1_act_offset), + din => dvc1_act_d, + dout => dvc1_act_q); + +dvc2_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dvc2_act_offset), + scout => sov(dvc2_act_offset), + din => dvc2_act_d, + dout => dvc2_act_q); + +dvc1_reg_reg: tri_ser_rlmreg_p +generic map (width => (2**REGMODE), init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dvc1_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dvc1_reg_offset to dvc1_reg_offset + dvc1_reg_d'length-1), + scout => sov(dvc1_reg_offset to dvc1_reg_offset + dvc1_reg_d'length-1), + din => dvc1_reg_d, + dout => dvc1_reg_q); + +dvc2_reg_reg: tri_ser_rlmreg_p +generic map (width => (2**REGMODE), init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dvc2_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dvc2_reg_offset to dvc2_reg_offset + dvc2_reg_d'length-1), + scout => sov(dvc2_reg_offset to dvc2_reg_offset + dvc2_reg_d'length-1), + din => dvc2_reg_d, + dout => dvc2_reg_q); + +xudbg0_reg_reg: tri_ser_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xudbg0_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xudbg0_reg_offset to xudbg0_reg_offset + xudbg0_reg_d'length-1), + scout => sov(xudbg0_reg_offset to xudbg0_reg_offset + xudbg0_reg_d'length-1), + din => xudbg0_reg_d, + dout => xudbg0_reg_q); + +xudbg0_done_reg_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xudbg0_done_reg_offset), + scout => sov(xudbg0_done_reg_offset), + din => xudbg0_done_reg_d, + dout => xudbg0_done_reg_q); + +xudbg1_dir_reg_reg: tri_ser_rlmreg_p +generic map (width => 13, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_arr_rd_ex4_done_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xudbg1_dir_reg_offset to xudbg1_dir_reg_offset + xudbg1_dir_reg_d'length-1), + scout => sov(xudbg1_dir_reg_offset to xudbg1_dir_reg_offset + xudbg1_dir_reg_d'length-1), + din => xudbg1_dir_reg_d, + dout => xudbg1_dir_reg_q); + +xudbg1_parity_reg_reg: tri_ser_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_arr_rd_ex3_done_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xudbg1_parity_reg_offset to xudbg1_parity_reg_offset + xudbg1_parity_reg_d'length-1), + scout => sov(xudbg1_parity_reg_offset to xudbg1_parity_reg_offset + xudbg1_parity_reg_d'length-1), + din => xudbg1_parity_reg_d, + dout => xudbg1_parity_reg_q); + +xudbg2_reg_reg: tri_ser_rlmreg_p +generic map (width => 31, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_arr_rd_ex3_done_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xudbg2_reg_offset to xudbg2_reg_offset + xudbg2_reg_d'length-1), + scout => sov(xudbg2_reg_offset to xudbg2_reg_offset + xudbg2_reg_d'length-1), + din => xudbg2_reg_d, + dout => xudbg2_reg_q); + +ex4_store_commit_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_store_commit_offset), + scout => sov(ex4_store_commit_offset), + din => ex4_store_commit_d, + dout => ex4_store_commit_q); + +ex1_sgpr_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_sgpr_instr_offset), + scout => sov(ex1_sgpr_instr_offset), + din => ex1_sgpr_instr_d, + dout => ex1_sgpr_instr_q); + +ex1_saxu_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_saxu_instr_offset), + scout => sov(ex1_saxu_instr_offset), + din => ex1_saxu_instr_d, + dout => ex1_saxu_instr_q); + +ex1_sdp_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_sdp_instr_offset), + scout => sov(ex1_sdp_instr_offset), + din => ex1_sdp_instr_d, + dout => ex1_sdp_instr_q); + +ex1_tgpr_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_tgpr_instr_offset), + scout => sov(ex1_tgpr_instr_offset), + din => ex1_tgpr_instr_d, + dout => ex1_tgpr_instr_q); + +ex1_taxu_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_taxu_instr_offset), + scout => sov(ex1_taxu_instr_offset), + din => ex1_taxu_instr_d, + dout => ex1_taxu_instr_q); + +ex1_tdp_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_tdp_instr_offset), + scout => sov(ex1_tdp_instr_offset), + din => ex1_tdp_instr_d, + dout => ex1_tdp_instr_q); + +ex2_tgpr_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_tgpr_instr_offset), + scout => sov(ex2_tgpr_instr_offset), + din => ex2_tgpr_instr_d, + dout => ex2_tgpr_instr_q); + +ex2_taxu_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_taxu_instr_offset), + scout => sov(ex2_taxu_instr_offset), + din => ex2_taxu_instr_d, + dout => ex2_taxu_instr_q); + +ex2_tdp_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_tdp_instr_offset), + scout => sov(ex2_tdp_instr_offset), + din => ex2_tdp_instr_d, + dout => ex2_tdp_instr_q); + +ex3_tgpr_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_tgpr_instr_offset), + scout => sov(ex3_tgpr_instr_offset), + din => ex3_tgpr_instr_d, + dout => ex3_tgpr_instr_q); + +ex3_taxu_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_taxu_instr_offset), + scout => sov(ex3_taxu_instr_offset), + din => ex3_taxu_instr_d, + dout => ex3_taxu_instr_q); + +ex4_tgpr_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_tgpr_instr_offset), + scout => sov(ex4_tgpr_instr_offset), + din => ex4_tgpr_instr_d, + dout => ex4_tgpr_instr_q); + +ex4_taxu_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_taxu_instr_offset), + scout => sov(ex4_taxu_instr_offset), + din => ex4_taxu_instr_d, + dout => ex4_taxu_instr_q); + +ex2_blkable_touch_reg: tri_regk +generic map (width => 1,init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_blkable_touch_d, + dout(0) => ex2_blkable_touch_q); + +ex3_blkable_touch_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_blkable_touch_offset), + scout => sov(ex3_blkable_touch_offset), + din => ex3_blkable_touch_d, + dout => ex3_blkable_touch_q); + +ex3_p_addr_lwr_reg: tri_rlmreg_p +generic map (width => 12, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_p_addr_lwr_offset to ex3_p_addr_lwr_offset + ex3_p_addr_lwr_d'length-1), + scout => sov(ex3_p_addr_lwr_offset to ex3_p_addr_lwr_offset + ex3_p_addr_lwr_d'length-1), + din => ex3_p_addr_lwr_d, + dout => ex3_p_addr_lwr_q); + +ex4_p_addr_reg: tri_regk +generic map (width => real_data_add, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex4_p_addr_d, + dout => ex4_p_addr_q); + +ex5_p_addr_reg: tri_rlmreg_p +generic map (width => real_data_add-6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_p_addr_offset to ex5_p_addr_offset + ex5_p_addr_d'length-1), + scout => sov(ex5_p_addr_offset to ex5_p_addr_offset + ex5_p_addr_d'length-1), + din => ex5_p_addr_d, + dout => ex5_p_addr_q); + +ex6_p_addr_reg: tri_regk +generic map (width => real_data_add-6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex5_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex6_p_addr_d, + dout => ex6_p_addr_q); + +ex4_c_inh_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex4_c_inh_d, + dout(0) => ex4_c_inh_q); + +ex4_opsize_reg: tri_regk +generic map (width => ex4_opsize_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex4_opsize_d, + dout => ex4_opsize_q); + +ex4_rot_sel_reg: tri_regk +generic map (width => ex4_rot_sel_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex4_rot_sel_d, + dout => ex4_rot_sel_q); + +ex4_data_swap_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex4_data_swap_val_d, + dout(0) => ex4_data_swap_val_q); + +ex4_algebraic_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex4_algebraic_d, + dout(0) => ex4_algebraic_q); + +ex4_lock_en_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex4_lock_en_d, + dout(0) => ex4_lock_en_q); + +eplc_wr_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(eplc_wr_offset to eplc_wr_offset + eplc_wr_d'length-1), + scout => sov(eplc_wr_offset to eplc_wr_offset + eplc_wr_d'length-1), + din => eplc_wr_d, + dout => eplc_wr_q); + +epsc_wr_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(epsc_wr_offset to epsc_wr_offset + epsc_wr_d'length-1), + scout => sov(epsc_wr_offset to epsc_wr_offset + epsc_wr_d'length-1), + din => epsc_wr_d, + dout => epsc_wr_q); + +eplc_t0_reg_a_reg: tri_ser_rlmreg_p +generic map (width => 2, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => eplc_t0_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(eplc_t0_reg_a_offset to eplc_t0_reg_a_offset + (eplc_t0_reg_d'length-23)-1), + scout => sov(eplc_t0_reg_a_offset to eplc_t0_reg_a_offset + (eplc_t0_reg_d'length-23)-1), + din => eplc_t0_reg_d(0 to 1), + dout => eplc_t0_reg_q(0 to 1)); + +eplc_t0_reg_b_reg: tri_ser_rlmreg_p +generic map (width => 9, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => eplc_t0_hyp_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(eplc_t0_reg_b_offset to eplc_t0_reg_b_offset + (eplc_t0_reg_d'length-16)-1), + scout => sov(eplc_t0_reg_b_offset to eplc_t0_reg_b_offset + (eplc_t0_reg_d'length-16)-1), + din => eplc_t0_reg_d(2 to 10), + dout => eplc_t0_reg_q(2 to 10)); + +eplc_t0_reg_c_reg: tri_ser_rlmreg_p +generic map (width => 14, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => eplc_t0_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(eplc_t0_reg_c_offset to eplc_t0_reg_c_offset + (eplc_t0_reg_d'length-11)-1), + scout => sov(eplc_t0_reg_c_offset to eplc_t0_reg_c_offset + (eplc_t0_reg_d'length-11)-1), + din => eplc_t0_reg_d(11 to 24), + dout => eplc_t0_reg_q(11 to 24)); + +eplc_t1_reg_a_reg: tri_ser_rlmreg_p +generic map (width => 2, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => eplc_t1_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(eplc_t1_reg_a_offset to eplc_t1_reg_a_offset + (eplc_t1_reg_d'length-23)-1), + scout => sov(eplc_t1_reg_a_offset to eplc_t1_reg_a_offset + (eplc_t1_reg_d'length-23)-1), + din => eplc_t1_reg_d(0 to 1), + dout => eplc_t1_reg_q(0 to 1)); + +eplc_t1_reg_b_reg: tri_ser_rlmreg_p +generic map (width => 9, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => eplc_t1_hyp_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(eplc_t1_reg_b_offset to eplc_t1_reg_b_offset + (eplc_t1_reg_d'length-16)-1), + scout => sov(eplc_t1_reg_b_offset to eplc_t1_reg_b_offset + (eplc_t1_reg_d'length-16)-1), + din => eplc_t1_reg_d(2 to 10), + dout => eplc_t1_reg_q(2 to 10)); + +eplc_t1_reg_c_reg: tri_ser_rlmreg_p +generic map (width => 14, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => eplc_t1_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(eplc_t1_reg_c_offset to eplc_t1_reg_c_offset + (eplc_t1_reg_d'length-11)-1), + scout => sov(eplc_t1_reg_c_offset to eplc_t1_reg_c_offset + (eplc_t1_reg_d'length-11)-1), + din => eplc_t1_reg_d(11 to 24), + dout => eplc_t1_reg_q(11 to 24)); + +eplc_t2_reg_a_reg: tri_ser_rlmreg_p +generic map (width => 2, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => eplc_t2_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(eplc_t2_reg_a_offset to eplc_t2_reg_a_offset + (eplc_t2_reg_d'length-23)-1), + scout => sov(eplc_t2_reg_a_offset to eplc_t2_reg_a_offset + (eplc_t2_reg_d'length-23)-1), + din => eplc_t2_reg_d(0 to 1), + dout => eplc_t2_reg_q(0 to 1)); + +eplc_t2_reg_b_reg: tri_ser_rlmreg_p +generic map (width => 9, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => eplc_t2_hyp_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(eplc_t2_reg_b_offset to eplc_t2_reg_b_offset + (eplc_t2_reg_d'length-16)-1), + scout => sov(eplc_t2_reg_b_offset to eplc_t2_reg_b_offset + (eplc_t2_reg_d'length-16)-1), + din => eplc_t2_reg_d(2 to 10), + dout => eplc_t2_reg_q(2 to 10)); + +eplc_t2_reg_c_reg: tri_ser_rlmreg_p +generic map (width => 14, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => eplc_t2_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(eplc_t2_reg_c_offset to eplc_t2_reg_c_offset + (eplc_t2_reg_d'length-11)-1), + scout => sov(eplc_t2_reg_c_offset to eplc_t2_reg_c_offset + (eplc_t2_reg_d'length-11)-1), + din => eplc_t2_reg_d(11 to 24), + dout => eplc_t2_reg_q(11 to 24)); + +eplc_t3_reg_a_reg: tri_ser_rlmreg_p +generic map (width => 2, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => eplc_t3_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(eplc_t3_reg_a_offset to eplc_t3_reg_a_offset + (eplc_t3_reg_d'length-23)-1), + scout => sov(eplc_t3_reg_a_offset to eplc_t3_reg_a_offset + (eplc_t3_reg_d'length-23)-1), + din => eplc_t3_reg_d(0 to 1), + dout => eplc_t3_reg_q(0 to 1)); + +eplc_t3_reg_b_reg: tri_ser_rlmreg_p +generic map (width => 9, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => eplc_t3_hyp_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(eplc_t3_reg_b_offset to eplc_t3_reg_b_offset + (eplc_t3_reg_d'length-16)-1), + scout => sov(eplc_t3_reg_b_offset to eplc_t3_reg_b_offset + (eplc_t3_reg_d'length-16)-1), + din => eplc_t3_reg_d(2 to 10), + dout => eplc_t3_reg_q(2 to 10)); + +eplc_t3_reg_c_reg: tri_ser_rlmreg_p +generic map (width => 14, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => eplc_t3_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(eplc_t3_reg_c_offset to eplc_t3_reg_c_offset + (eplc_t3_reg_d'length-11)-1), + scout => sov(eplc_t3_reg_c_offset to eplc_t3_reg_c_offset + (eplc_t3_reg_d'length-11)-1), + din => eplc_t3_reg_d(11 to 24), + dout => eplc_t3_reg_q(11 to 24)); + +epsc_t0_reg_a_reg: tri_ser_rlmreg_p +generic map (width => 2, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => epsc_t0_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(epsc_t0_reg_a_offset to epsc_t0_reg_a_offset + (epsc_t0_reg_d'length-23)-1), + scout => sov(epsc_t0_reg_a_offset to epsc_t0_reg_a_offset + (epsc_t0_reg_d'length-23)-1), + din => epsc_t0_reg_d(0 to 1), + dout => epsc_t0_reg_q(0 to 1)); + +epsc_t0_reg_b_reg: tri_ser_rlmreg_p +generic map (width => 9, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => epsc_t0_hyp_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(epsc_t0_reg_b_offset to epsc_t0_reg_b_offset + (epsc_t0_reg_d'length-16)-1), + scout => sov(epsc_t0_reg_b_offset to epsc_t0_reg_b_offset + (epsc_t0_reg_d'length-16)-1), + din => epsc_t0_reg_d(2 to 10), + dout => epsc_t0_reg_q(2 to 10)); + +epsc_t0_reg_c_reg: tri_ser_rlmreg_p +generic map (width => 14, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => epsc_t0_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(epsc_t0_reg_c_offset to epsc_t0_reg_c_offset + (epsc_t0_reg_d'length-11)-1), + scout => sov(epsc_t0_reg_c_offset to epsc_t0_reg_c_offset + (epsc_t0_reg_d'length-11)-1), + din => epsc_t0_reg_d(11 to 24), + dout => epsc_t0_reg_q(11 to 24)); + +epsc_t1_reg_a_reg: tri_ser_rlmreg_p +generic map (width => 2, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => epsc_t1_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(epsc_t1_reg_a_offset to epsc_t1_reg_a_offset + (epsc_t1_reg_d'length-23)-1), + scout => sov(epsc_t1_reg_a_offset to epsc_t1_reg_a_offset + (epsc_t1_reg_d'length-23)-1), + din => epsc_t1_reg_d(0 to 1), + dout => epsc_t1_reg_q(0 to 1)); + +epsc_t1_reg_b_reg: tri_ser_rlmreg_p +generic map (width => 9, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => epsc_t1_hyp_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(epsc_t1_reg_b_offset to epsc_t1_reg_b_offset + (epsc_t1_reg_d'length-16)-1), + scout => sov(epsc_t1_reg_b_offset to epsc_t1_reg_b_offset + (epsc_t1_reg_d'length-16)-1), + din => epsc_t1_reg_d(2 to 10), + dout => epsc_t1_reg_q(2 to 10)); + +epsc_t1_reg_c_reg: tri_ser_rlmreg_p +generic map (width => 14, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => epsc_t1_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(epsc_t1_reg_c_offset to epsc_t1_reg_c_offset + (epsc_t1_reg_d'length-11)-1), + scout => sov(epsc_t1_reg_c_offset to epsc_t1_reg_c_offset + (epsc_t1_reg_d'length-11)-1), + din => epsc_t1_reg_d(11 to 24), + dout => epsc_t1_reg_q(11 to 24)); + +epsc_t2_reg_a_reg: tri_ser_rlmreg_p +generic map (width => 2, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => epsc_t2_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(epsc_t2_reg_a_offset to epsc_t2_reg_a_offset + (epsc_t2_reg_d'length-23)-1), + scout => sov(epsc_t2_reg_a_offset to epsc_t2_reg_a_offset + (epsc_t2_reg_d'length-23)-1), + din => epsc_t2_reg_d(0 to 1), + dout => epsc_t2_reg_q(0 to 1)); + +epsc_t2_reg_b_reg: tri_ser_rlmreg_p +generic map (width => 9, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => epsc_t2_hyp_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(epsc_t2_reg_b_offset to epsc_t2_reg_b_offset + (epsc_t2_reg_d'length-16)-1), + scout => sov(epsc_t2_reg_b_offset to epsc_t2_reg_b_offset + (epsc_t2_reg_d'length-16)-1), + din => epsc_t2_reg_d(2 to 10), + dout => epsc_t2_reg_q(2 to 10)); + +epsc_t2_reg_c_reg: tri_ser_rlmreg_p +generic map (width => 14, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => epsc_t2_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(epsc_t2_reg_c_offset to epsc_t2_reg_c_offset + (epsc_t2_reg_d'length-11)-1), + scout => sov(epsc_t2_reg_c_offset to epsc_t2_reg_c_offset + (epsc_t2_reg_d'length-11)-1), + din => epsc_t2_reg_d(11 to 24), + dout => epsc_t2_reg_q(11 to 24)); + +epsc_t3_reg_a_reg: tri_ser_rlmreg_p +generic map (width => 2, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => epsc_t3_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(epsc_t3_reg_a_offset to epsc_t3_reg_a_offset + (epsc_t3_reg_d'length-23)-1), + scout => sov(epsc_t3_reg_a_offset to epsc_t3_reg_a_offset + (epsc_t3_reg_d'length-23)-1), + din => epsc_t3_reg_d(0 to 1), + dout => epsc_t3_reg_q(0 to 1)); + +epsc_t3_reg_b_reg: tri_ser_rlmreg_p +generic map (width => 9, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => epsc_t3_hyp_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(epsc_t3_reg_b_offset to epsc_t3_reg_b_offset + (epsc_t3_reg_d'length-16)-1), + scout => sov(epsc_t3_reg_b_offset to epsc_t3_reg_b_offset + (epsc_t3_reg_d'length-16)-1), + din => epsc_t3_reg_d(2 to 10), + dout => epsc_t3_reg_q(2 to 10)); + +epsc_t3_reg_c_reg: tri_ser_rlmreg_p +generic map (width => 14, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => epsc_t3_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(epsc_t3_reg_c_offset to epsc_t3_reg_c_offset + (epsc_t3_reg_d'length-11)-1), + scout => sov(epsc_t3_reg_c_offset to epsc_t3_reg_c_offset + (epsc_t3_reg_d'length-11)-1), + din => epsc_t3_reg_d(11 to 24), + dout => epsc_t3_reg_q(11 to 24)); + +ex2_undef_lockset_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_undef_lockset_offset), + scout => sov(ex2_undef_lockset_offset), + din => ex2_undef_lockset_d, + dout => ex2_undef_lockset_q); + +ex3_undef_lockset_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_undef_lockset_offset), + scout => sov(ex3_undef_lockset_offset), + din => ex3_undef_lockset_d, + dout => ex3_undef_lockset_q); + +ex4_unable_2lock_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_unable_2lock_offset), + scout => sov(ex4_unable_2lock_offset), + din => ex4_unable_2lock_d, + dout => ex4_unable_2lock_q); + +ex5_unable_2lock_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_unable_2lock_offset), + scout => sov(ex5_unable_2lock_offset), + din => ex5_unable_2lock_d, + dout => ex5_unable_2lock_q); + +ex3_ldstq_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_ldstq_instr_offset), + scout => sov(ex3_ldstq_instr_offset), + din => ex3_ldstq_instr_d, + dout => ex3_ldstq_instr_q); + +ex4_store_instr_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex4_store_instr_d, + dout(0) => ex4_store_instr_q); + +ex5_store_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_store_instr_offset), + scout => sov(ex5_store_instr_offset), + din => ex5_store_instr_d, + dout => ex5_store_instr_q); + +ex5_store_miss_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_store_miss_offset), + scout => sov(ex5_store_miss_offset), + din => ex5_store_miss_d, + dout => ex5_store_miss_q); + +ex4_perf_dcbt_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex4_perf_dcbt_d, + dout(0) => ex4_perf_dcbt_q); + +ex5_perf_dcbt_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_perf_dcbt_offset), + scout => sov(ex5_perf_dcbt_offset), + din => ex5_perf_dcbt_d, + dout => ex5_perf_dcbt_q); + +perf_lsu_events_reg: tri_rlmreg_p +generic map (width => 17, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(perf_lsu_events_offset to perf_lsu_events_offset + perf_lsu_events_d'length-1), + scout => sov(perf_lsu_events_offset to perf_lsu_events_offset + perf_lsu_events_d'length-1), + din => perf_lsu_events_d, + dout => perf_lsu_events_q); + +clkg_ctl_override_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(clkg_ctl_override_offset), + scout => sov(clkg_ctl_override_offset), + din => clkg_ctl_override_d, + dout => clkg_ctl_override_q); + +spr_xucr0_wlck_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(spr_xucr0_wlck_offset), + scout => sov(spr_xucr0_wlck_offset), + din => spr_xucr0_wlck_d, + dout => spr_xucr0_wlck_q); + +spr_xucr0_wlck_cpy_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(spr_xucr0_wlck_cpy_offset), + scout => sov(spr_xucr0_wlck_cpy_offset), + din => spr_xucr0_wlck_cpy_d, + dout => spr_xucr0_wlck_cpy_q); + +spr_xucr0_flh2l2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(spr_xucr0_flh2l2_offset), + scout => sov(spr_xucr0_flh2l2_offset), + din => spr_xucr0_flh2l2_d, + dout => spr_xucr0_flh2l2_q); + +ex3_spr_xucr0_flh2l2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_spr_xucr0_flh2l2_offset), + scout => sov(ex3_spr_xucr0_flh2l2_offset), + din => ex3_spr_xucr0_flh2l2_d, + dout => ex3_spr_xucr0_flh2l2_q); + +spr_xucr0_dcdis_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(spr_xucr0_dcdis_offset), + scout => sov(spr_xucr0_dcdis_offset), + din => spr_xucr0_dcdis_d, + dout => spr_xucr0_dcdis_q); + +spr_xucr0_cls_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(spr_xucr0_cls_offset), + scout => sov(spr_xucr0_cls_offset), + din => spr_xucr0_cls_d, + dout => spr_xucr0_cls_q); + +agen_xucr0_cls_dly_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(agen_xucr0_cls_dly_offset), + scout => sov(agen_xucr0_cls_dly_offset), + din => agen_xucr0_cls_dly_d, + dout => agen_xucr0_cls_dly_q); + +agen_xucr0_cls_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(agen_xucr0_cls_offset), + scout => sov(agen_xucr0_cls_offset), + din => agen_xucr0_cls_d, + dout => agen_xucr0_cls_q); + +mtspr_trace_en_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(mtspr_trace_en_offset to mtspr_trace_en_offset + mtspr_trace_en_d'length-1), + scout => sov(mtspr_trace_en_offset to mtspr_trace_en_offset + mtspr_trace_en_d'length-1), + din => mtspr_trace_en_d, + dout => mtspr_trace_en_q); + +ex3_local_dcbf_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_local_dcbf_offset), + scout => sov(ex3_local_dcbf_offset), + din => ex3_local_dcbf_d, + dout => ex3_local_dcbf_q); + +ex1_msgsnd_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_msgsnd_instr_offset), + scout => sov(ex1_msgsnd_instr_offset), + din => ex1_msgsnd_instr_d, + dout => ex1_msgsnd_instr_q); + +ex2_msgsnd_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_msgsnd_instr_offset), + scout => sov(ex2_msgsnd_instr_offset), + din => ex2_msgsnd_instr_d, + dout => ex2_msgsnd_instr_q); + +ex3_msgsnd_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_msgsnd_instr_offset), + scout => sov(ex3_msgsnd_instr_offset), + din => ex3_msgsnd_instr_d, + dout => ex3_msgsnd_instr_q); + +ex1_dci_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_dci_instr_offset), + scout => sov(ex1_dci_instr_offset), + din => ex1_dci_instr_d, + dout => ex1_dci_instr_q); + +ex2_dci_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_dci_instr_offset), + scout => sov(ex2_dci_instr_offset), + din => ex2_dci_instr_d, + dout => ex2_dci_instr_q); + +ex3_dci_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_dci_instr_offset), + scout => sov(ex3_dci_instr_offset), + din => ex3_dci_instr_d, + dout => ex3_dci_instr_q); + +ex1_ici_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_ici_instr_offset), + scout => sov(ex1_ici_instr_offset), + din => ex1_ici_instr_d, + dout => ex1_ici_instr_q); + +ex2_ici_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_ici_instr_offset), + scout => sov(ex2_ici_instr_offset), + din => ex2_ici_instr_d, + dout => ex2_ici_instr_q); + +ex3_ici_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_ici_instr_offset), + scout => sov(ex3_ici_instr_offset), + din => ex3_ici_instr_d, + dout => ex3_ici_instr_q); + +ex3_load_type_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_load_type_offset), + scout => sov(ex3_load_type_offset), + din => ex3_load_type_d, + dout => ex3_load_type_q); + +ex4_load_type_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex4_load_type_d, + dout(0) => ex4_load_type_q); + +ex3_l2load_type_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_l2load_type_offset), + scout => sov(ex3_l2load_type_offset), + din => ex3_l2load_type_d, + dout => ex3_l2load_type_q); + +flh2l2_gate_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(flh2l2_gate_offset), + scout => sov(flh2l2_gate_offset), + din => flh2l2_gate_d, + dout => flh2l2_gate_q); + +rel_upd_dcarr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_upd_dcarr_offset), + scout => sov(rel_upd_dcarr_offset), + din => rel_upd_dcarr_d, + dout => rel_upd_dcarr_q); + +ex5_xu_wren_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_xu_wren_offset), + scout => sov(ex5_xu_wren_offset), + din => ex5_xu_wren_d, + dout => ex5_xu_wren_q); + +ex1_ldawx_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_ldawx_instr_offset), + scout => sov(ex1_ldawx_instr_offset), + din => ex1_ldawx_instr_d, + dout => ex1_ldawx_instr_q); + +ex2_ldawx_instr_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_ldawx_instr_d, + dout(0) => ex2_ldawx_instr_q); + +ex3_watch_en_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_watch_en_offset), + scout => sov(ex3_watch_en_offset), + din => ex3_watch_en_d, + dout => ex3_watch_en_q); + +ex4_watch_en_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex4_watch_en_d, + dout(0) => ex4_watch_en_q); + +ex5_watch_en_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_watch_en_offset), + scout => sov(ex5_watch_en_offset), + din => ex5_watch_en_d, + dout => ex5_watch_en_q); + +ex1_wclr_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_wclr_instr_offset), + scout => sov(ex1_wclr_instr_offset), + din => ex1_wclr_instr_d, + dout => ex1_wclr_instr_q); + +ex2_wclr_instr_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_wclr_instr_d, + dout(0) => ex2_wclr_instr_q); + +ex3_wclr_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wclr_instr_offset), + scout => sov(ex3_wclr_instr_offset), + din => ex3_wclr_instr_d, + dout => ex3_wclr_instr_q); + +ex4_wclr_instr_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex4_wclr_instr_d, + dout(0) => ex4_wclr_instr_q); + +ex5_wclr_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_wclr_instr_offset), + scout => sov(ex5_wclr_instr_offset), + din => ex5_wclr_instr_d, + dout => ex5_wclr_instr_q); + +ex4_wclr_set_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex4_wclr_set_d, + dout(0) => ex4_wclr_set_q); + +ex5_wclr_set_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_wclr_set_offset), + scout => sov(ex5_wclr_set_offset), + din => ex5_wclr_set_d, + dout => ex5_wclr_set_q); + +ex1_wchk_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_wchk_instr_offset), + scout => sov(ex1_wchk_instr_offset), + din => ex1_wchk_instr_d, + dout => ex1_wchk_instr_q); + +ex2_wchk_instr_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_wchk_instr_d, + dout(0) => ex2_wchk_instr_q); + +ex4_cacheable_linelock_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_cacheable_linelock_offset), + scout => sov(ex4_cacheable_linelock_offset), + din => ex4_cacheable_linelock_d, + dout => ex4_cacheable_linelock_q); + +ex1_icswx_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_icswx_instr_offset), + scout => sov(ex1_icswx_instr_offset), + din => ex1_icswx_instr_d, + dout => ex1_icswx_instr_q); + +ex2_icswx_instr_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_icswx_instr_d, + dout(0) => ex2_icswx_instr_q); + +ex3_icswx_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_icswx_instr_offset), + scout => sov(ex3_icswx_instr_offset), + din => ex3_icswx_instr_d, + dout => ex3_icswx_instr_q); + +ex1_icswx_dot_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_icswx_dot_instr_offset), + scout => sov(ex1_icswx_dot_instr_offset), + din => ex1_icswx_dot_instr_d, + dout => ex1_icswx_dot_instr_q); + +ex2_icswx_dot_instr_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_icswx_dot_instr_d, + dout(0) => ex2_icswx_dot_instr_q); + +ex3_icswx_dot_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_icswx_dot_instr_offset), + scout => sov(ex3_icswx_dot_instr_offset), + din => ex3_icswx_dot_instr_d, + dout => ex3_icswx_dot_instr_q); + +ex1_icswx_epid_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_icswx_epid_offset), + scout => sov(ex1_icswx_epid_offset), + din => ex1_icswx_epid_d, + dout => ex1_icswx_epid_q); + +ex2_icswx_epid_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_icswx_epid_d, + dout(0) => ex2_icswx_epid_q); + +ex3_icswx_epid_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_icswx_epid_offset), + scout => sov(ex3_icswx_epid_offset), + din => ex3_icswx_epid_d, + dout => ex3_icswx_epid_q); + +ex3_c_inh_drop_op_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_c_inh_drop_op_offset), + scout => sov(ex3_c_inh_drop_op_offset), + din => ex3_c_inh_drop_op_d, + dout => ex3_c_inh_drop_op_q); + +axu_rel_wren_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ldq_rel_stg24_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(axu_rel_wren_offset), + scout => sov(axu_rel_wren_offset), + din => axu_rel_wren_d, + dout => axu_rel_wren_q); + +axu_rel_wren_stg1_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(axu_rel_wren_stg1_offset), + scout => sov(axu_rel_wren_stg1_offset), + din => axu_rel_wren_stg1_d, + dout => axu_rel_wren_stg1_q); + +rel_axu_tid_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ldq_rel_stg24_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_axu_tid_offset to rel_axu_tid_offset + rel_axu_tid_d'length-1), + scout => sov(rel_axu_tid_offset to rel_axu_tid_offset + rel_axu_tid_d'length-1), + din => rel_axu_tid_d, + dout => rel_axu_tid_q); + +rel_axu_tid_stg1_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_axu_tid_stg1_offset to rel_axu_tid_stg1_offset + rel_axu_tid_stg1_d'length-1), + scout => sov(rel_axu_tid_stg1_offset to rel_axu_tid_stg1_offset + rel_axu_tid_stg1_d'length-1), + din => rel_axu_tid_stg1_d, + dout => rel_axu_tid_stg1_q); + +rel_axu_ta_gpr_reg: tri_rlmreg_p +generic map (width => 9, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ldq_rel_stg24_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_axu_ta_gpr_offset to rel_axu_ta_gpr_offset + rel_axu_ta_gpr_d'length-1), + scout => sov(rel_axu_ta_gpr_offset to rel_axu_ta_gpr_offset + rel_axu_ta_gpr_d'length-1), + din => rel_axu_ta_gpr_d, + dout => rel_axu_ta_gpr_q); + +rel_axu_ta_gpr_stg1_reg: tri_rlmreg_p +generic map (width => 9, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_axu_ta_gpr_stg1_offset to rel_axu_ta_gpr_stg1_offset + rel_axu_ta_gpr_stg1_d'length-1), + scout => sov(rel_axu_ta_gpr_stg1_offset to rel_axu_ta_gpr_stg1_offset + rel_axu_ta_gpr_stg1_d'length-1), + din => rel_axu_ta_gpr_stg1_d, + dout => rel_axu_ta_gpr_stg1_q); + +rf0_l2_inv_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_l2_inv_val_offset), + scout => sov(rf0_l2_inv_val_offset), + din => rf0_l2_inv_val_d, + dout => rf0_l2_inv_val_q); + +rf1_l2_inv_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(rf1_l2_inv_val_offset), + scout => sov(rf1_l2_inv_val_offset), + din => rf1_l2_inv_val_d, + dout => rf1_l2_inv_val_q); + +ex1_agen_binv_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_agen_binv_val_offset), + scout => sov(ex1_agen_binv_val_offset), + din => ex1_agen_binv_val_d, + dout => ex1_agen_binv_val_q); + +ex1_l2_inv_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_l2_inv_val_offset), + scout => sov(ex1_l2_inv_val_offset), + din => ex1_l2_inv_val_d, + dout => ex1_l2_inv_val_q); + +lsu_msr_gs_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(lsu_msr_gs_offset to lsu_msr_gs_offset + lsu_msr_gs_d'length-1), + scout => sov(lsu_msr_gs_offset to lsu_msr_gs_offset + lsu_msr_gs_d'length-1), + din => lsu_msr_gs_d, + dout => lsu_msr_gs_q); + +lsu_msr_pr_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(lsu_msr_pr_offset to lsu_msr_pr_offset + lsu_msr_pr_d'length-1), + scout => sov(lsu_msr_pr_offset to lsu_msr_pr_offset + lsu_msr_pr_d'length-1), + din => lsu_msr_pr_d, + dout => lsu_msr_pr_q); + +lsu_msr_cm_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(lsu_msr_cm_offset to lsu_msr_cm_offset + lsu_msr_cm_d'length-1), + scout => sov(lsu_msr_cm_offset to lsu_msr_cm_offset + lsu_msr_cm_d'length-1), + din => lsu_msr_cm_d, + dout => lsu_msr_cm_q); + +ex1_lsu_64bit_agen_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_lsu_64bit_agen_offset), + scout => sov(ex1_lsu_64bit_agen_offset), + din => ex1_lsu_64bit_agen_d, + dout => ex1_lsu_64bit_agen_q); + +ex6_icbi_val_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_icbi_val_offset to ex6_icbi_val_offset + ex6_icbi_val_d'length-1), + scout => sov(ex6_icbi_val_offset to ex6_icbi_val_offset + ex6_icbi_val_d'length-1), + din => ex6_icbi_val_d, + dout => ex6_icbi_val_q); + +ex1_mtspr_trace_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_mtspr_trace_offset), + scout => sov(ex1_mtspr_trace_offset), + din => ex1_mtspr_trace_d, + dout => ex1_mtspr_trace_q); + +ex2_mtspr_trace_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_mtspr_trace_offset), + scout => sov(ex2_mtspr_trace_offset), + din => ex2_mtspr_trace_d, + dout => ex2_mtspr_trace_q); + +ex3_mtspr_trace_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_mtspr_trace_offset), + scout => sov(ex3_mtspr_trace_offset), + din => ex3_mtspr_trace_d, + dout => ex3_mtspr_trace_q); + +ex3_byte_en_reg: tri_rlmreg_p +generic map (width => 32, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_byte_en_offset to ex3_byte_en_offset + ex3_byte_en_d'length-1), + scout => sov(ex3_byte_en_offset to ex3_byte_en_offset + ex3_byte_en_d'length-1), + din => ex3_byte_en_d, + dout => ex3_byte_en_q); + +ex3_rot_sel_le_reg: tri_rlmreg_p +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_rot_sel_le_offset to ex3_rot_sel_le_offset + ex3_rot_sel_le_d'length-1), + scout => sov(ex3_rot_sel_le_offset to ex3_rot_sel_le_offset + ex3_rot_sel_le_d'length-1), + din => ex3_rot_sel_le_d, + dout => ex3_rot_sel_le_q); + +ex3_rot_sel_be_reg: tri_rlmreg_p +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_rot_sel_be_offset to ex3_rot_sel_be_offset + ex3_rot_sel_be_d'length-1), + scout => sov(ex3_rot_sel_be_offset to ex3_rot_sel_be_offset + ex3_rot_sel_be_d'length-1), + din => ex3_rot_sel_be_d, + dout => ex3_rot_sel_be_q); + +dir_arr_rd_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dir_arr_rd_val_offset), + scout => sov(dir_arr_rd_val_offset), + din => dir_arr_rd_val_d, + dout => dir_arr_rd_val_q); + +dir_arr_rd_is0_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dir_arr_rd_is0_val_offset), + scout => sov(dir_arr_rd_is0_val_offset), + din => dir_arr_rd_is0_val_d, + dout => dir_arr_rd_is0_val_q); + +dir_arr_rd_is1_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dir_arr_rd_is1_val_offset), + scout => sov(dir_arr_rd_is1_val_offset), + din => dir_arr_rd_is1_val_d, + dout => dir_arr_rd_is1_val_q); + +dir_arr_rd_is2_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dir_arr_rd_is2_val_offset), + scout => sov(dir_arr_rd_is2_val_offset), + din => dir_arr_rd_is2_val_d, + dout => dir_arr_rd_is2_val_q); + +dir_arr_rd_rf0_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dir_arr_rd_rf0_val_offset), + scout => sov(dir_arr_rd_rf0_val_offset), + din => dir_arr_rd_rf0_val_d, + dout => dir_arr_rd_rf0_val_q); + +dir_arr_rd_rf1_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dir_arr_rd_rf1_val_offset), + scout => sov(dir_arr_rd_rf1_val_offset), + din => dir_arr_rd_rf1_val_d, + dout => dir_arr_rd_rf1_val_q); + +dir_arr_rd_rf0_done_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dir_arr_rd_rf0_done_offset), + scout => sov(dir_arr_rd_rf0_done_offset), + din => dir_arr_rd_rf0_done_d, + dout => dir_arr_rd_rf0_done_q); + +dir_arr_rd_rf1_done_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dir_arr_rd_rf1_done_offset), + scout => sov(dir_arr_rd_rf1_done_offset), + din => dir_arr_rd_rf1_done_d, + dout => dir_arr_rd_rf1_done_q); + +dir_arr_rd_ex1_done_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dir_arr_rd_ex1_done_offset), + scout => sov(dir_arr_rd_ex1_done_offset), + din => dir_arr_rd_ex1_done_d, + dout => dir_arr_rd_ex1_done_q); + +dir_arr_rd_ex2_done_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dir_arr_rd_ex2_done_offset), + scout => sov(dir_arr_rd_ex2_done_offset), + din => dir_arr_rd_ex2_done_d, + dout => dir_arr_rd_ex2_done_q); + +dir_arr_rd_ex3_done_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dir_arr_rd_ex3_done_offset), + scout => sov(dir_arr_rd_ex3_done_offset), + din => dir_arr_rd_ex3_done_d, + dout => dir_arr_rd_ex3_done_q); + +dir_arr_rd_ex4_done_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dir_arr_rd_ex4_done_offset), + scout => sov(dir_arr_rd_ex4_done_offset), + din => dir_arr_rd_ex4_done_d, + dout => dir_arr_rd_ex4_done_q); + +my_spare0_lcb : entity tri.tri_lcbnd(tri_lcbnd) +generic map (expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + d1clk => my_spare0_d1clk, + d2clk => my_spare0_d2clk, + lclk => my_spare0_lclk); +my_spare0_latches_reg: entity tri.tri_inv_nlats(tri_inv_nlats) +generic map (width => 3, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + lclk => my_spare0_lclk, + d1clk => my_spare0_d1clk, + d2clk => my_spare0_d2clk, + scanin => siv(my_spare0_latches_offset to my_spare0_latches_offset + my_spare0_latches_d'length-1), + scanout => sov(my_spare0_latches_offset to my_spare0_latches_offset + my_spare0_latches_d'length-1), + d => my_spare0_latches_d, + qb => my_spare0_latches_q); + +my_spare1_lcb : entity tri.tri_lcbnd(tri_lcbnd) +generic map (expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + d1clk => my_spare1_d1clk, + d2clk => my_spare1_d2clk, + lclk => my_spare1_lclk); +my_spare1_latches_reg: entity tri.tri_inv_nlats(tri_inv_nlats) +generic map (width => 20, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + lclk => my_spare1_lclk, + d1clk => my_spare1_d1clk, + d2clk => my_spare1_d2clk, + scanin => siv(my_spare1_latches_offset to my_spare1_latches_offset + my_spare1_latches_d'length-1), + scanout => sov(my_spare1_latches_offset to my_spare1_latches_offset + my_spare1_latches_d'length-1), + d => my_spare1_latches_d, + qb => my_spare1_latches_q); + +rf1_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf1_stg_act_offset), + scout => sov(rf1_stg_act_offset), + din => rf1_stg_act_d, + dout => rf1_stg_act_q); + +ex1_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_stg_act_offset), + scout => sov(ex1_stg_act_offset), + din => ex1_stg_act_d, + dout => ex1_stg_act_q); + +ex2_stg_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_stg_act_d, + dout(0) => ex2_stg_act_q); + +ex3_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_stg_act_offset), + scout => sov(ex3_stg_act_offset), + din => ex3_stg_act_d, + dout => ex3_stg_act_q); + +ex4_stg_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex4_stg_act_d, + dout(0) => ex4_stg_act_q); + +ex5_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_stg_act_offset), + scout => sov(ex5_stg_act_offset), + din => ex5_stg_act_d, + dout => ex5_stg_act_q); + +binv1_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv1_stg_act_offset), + scout => sov(binv1_stg_act_offset), + din => binv1_stg_act_d, + dout => binv1_stg_act_q); + +binv2_stg_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => binv2_stg_act_d, + dout(0) => binv2_stg_act_q); + +binv3_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv3_stg_act_offset), + scout => sov(binv3_stg_act_offset), + din => binv3_stg_act_d, + dout => binv3_stg_act_q); + +binv4_stg_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => binv4_stg_act_d, + dout(0) => binv4_stg_act_q); + +binv5_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv5_stg_act_offset), + scout => sov(binv5_stg_act_offset), + din => binv5_stg_act_d, + dout => binv5_stg_act_q); + +rel1_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel1_stg_act_offset), + scout => sov(rel1_stg_act_offset), + din => rel1_stg_act_d, + dout => rel1_stg_act_q); + +rel3_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel3_stg_act_offset), + scout => sov(rel3_stg_act_offset), + din => rel3_stg_act_d, + dout => rel3_stg_act_q); + +rel4_stg_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel4_stg_act_d, + dout(0) => rel4_stg_act_q); + +siv(0 to scan_right) <= sov(1 to scan_right) & scan_in; +scan_out <= sov(0); + + +end xuq_lsu_dc_cntrl; + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_debug.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_debug.vhdl new file mode 100644 index 0000000..d62c987 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_debug.vhdl @@ -0,0 +1,752 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee,ibm,support,work,tri,clib; +use ieee.std_logic_1164.all; +use support.power_logic_pkg.all; +use tri.tri_latches_pkg.all; + +entity xuq_lsu_debug is +generic(expand_type :integer := 2); +port( + + pc_xu_trace_bus_enable :in std_ulogic; + lsu_debug_mux_ctrls :in std_ulogic_vector(0 to 15); + xu_lsu_ex2_instr_trace_val :in std_ulogic; + + trigger_data_in :in std_ulogic_vector(0 to 11); + debug_data_in :in std_ulogic_vector(0 to 87); + + dc_fgen_dbg_data :in std_ulogic_vector(0 to 1); + dc_cntrl_dbg_data :in std_ulogic_vector(0 to 66); + dc_val_dbg_data :in std_ulogic_vector(0 to 293); + dc_lru_dbg_data :in std_ulogic_vector(0 to 81); + dc_dir_dbg_data :in std_ulogic_vector(0 to 35); + dir_arr_dbg_data :in std_ulogic_vector(0 to 60); + lmq_dbg_dcache_pe :in std_ulogic_vector(1 to 60); + lmq_dbg_l2req :in std_ulogic_vector(0 to 212); + lmq_dbg_rel :in std_ulogic_vector(0 to 140); + lmq_dbg_binv :in std_ulogic_vector(0 to 44); + lmq_dbg_pops :in std_ulogic_vector(0 to 5); + lmq_dbg_grp0 :in std_ulogic_vector(0 to 81); + lmq_dbg_grp1 :in std_ulogic_vector(0 to 81); + lmq_dbg_grp2 :in std_ulogic_vector(0 to 87); + lmq_dbg_grp3 :in std_ulogic_vector(0 to 87); + lmq_dbg_grp4 :in std_ulogic_vector(0 to 87); + lmq_dbg_grp5 :in std_ulogic_vector(0 to 87); + lmq_dbg_grp6 :in std_ulogic_vector(0 to 87); + pe_recov_begin :in std_ulogic; + derat_xu_debug_group0 :in std_ulogic_vector(0 to 87); + derat_xu_debug_group1 :in std_ulogic_vector(0 to 87); + + trigger_data_out :out std_ulogic_vector(0 to 11); + debug_data_out :out std_ulogic_vector(0 to 87); + + vdd :inout power_logic; + gnd :inout power_logic; + nclk :in clk_logic; + sg_0 :in std_ulogic; + func_slp_sl_thold_0_b :in std_ulogic; + func_slp_sl_force :in std_ulogic; + d_mode_dc :in std_ulogic; + delay_lclkr_dc :in std_ulogic; + mpw1_dc_b :in std_ulogic; + mpw2_dc_b :in std_ulogic; + scan_in :in std_ulogic; + scan_out :out std_ulogic +); + +-- synopsys translate_off + +-- synopsys translate_on +end xuq_lsu_debug; +architecture xuq_lsu_debug of xuq_lsu_debug is + +type dbgSize is array (natural range <>) of std_ulogic_vector(0 to 21); + +signal trace_bus_enable_q :std_ulogic; +signal unit_trace_sel_q :std_ulogic_vector(0 to 15); + +signal lsu_dbg_way_0 :dbgSize(0 to 7); +signal lsu_dbg_way_1 :dbgSize(0 to 7); +signal lsu_dbg_way_2 :dbgSize(0 to 7); +signal lsu_dbg_way_3 :dbgSize(0 to 7); +signal l2cmdq_dbg_data_0 :dbgSize(0 to 3); +signal l2cmdq_dbg_data_1 :dbgSize(0 to 3); +signal l2cmdq_dbg_data_2 :dbgSize(0 to 3); +signal l2cmdq_dbg_data_3 :dbgSize(0 to 3); +signal lsu_dbg_group0_0 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group0_1 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group0_2 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group0_3 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group0 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group1_b64 :std_ulogic; +signal lsu_dbg_group1_b67 :std_ulogic; +signal lsu_dbg_group1_0 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group1_1 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group1_2 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group1_3 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group1 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group2_0 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group2_1 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group2_2 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group2_3 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group2 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group3_0 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group3_1 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group3_2 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group3_3 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group3 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group4_0 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group4_1 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group4_2 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group4_3 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group4 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group5_0 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group5_1 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group5_2 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group5_3 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group5 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group6_0 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group6_1 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group6_2 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group6_3 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group6 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group7_0 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group7_1 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group7_2 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group7_3 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group7 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group8_0 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group8_1 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group8_2 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group8_3 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group8 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group9_0 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group9_1 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group9_2 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group9_3 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group9 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group10_0 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group10_1 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group10_2 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group10_3 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group10 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group11_0 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group11_1 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group11_2 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group11_3 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group11 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group12_0 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group12_1 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group12_2 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group12_3 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group12 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group13_0 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group13_1 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group13_2 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group13_3 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group13 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group14_0 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group14_1 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group14_2 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group14_3 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group14 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group15_0 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group15_1 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group15_2 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group15_3 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group15 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group16_0 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group16_1 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group16_2 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group16_3 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group16 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group17_0 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group17_1 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group17_2 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group17_3 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group17 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group18_0 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group18_1 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group18_2 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group18_3 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group18 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group19_0 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group19_1 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group19_2 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group19_3 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group19 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group20_0 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group20_1 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group20_2 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group20_3 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group20 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group21_0 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group21_1 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group21_2 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group21_3 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group21 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group22 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group23 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group24 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group25 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group26 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group27 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group28 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group29_0 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group29_1 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group29_2 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group29_3 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group29 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group30 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group31 :std_ulogic_vector(0 to 87); +signal lsu_trg_group0 :std_ulogic_vector(0 to 11); +signal lsu_trg_group1 :std_ulogic_vector(0 to 11); +signal lsu_trg_group2 :std_ulogic_vector(0 to 11); +signal lsu_trg_group3 :std_ulogic_vector(0 to 11); +signal lmq_dbg_rel_ctrl :std_ulogic_vector(0 to 5); +signal ex3_instr_trace_val_d :std_ulogic; +signal ex3_instr_trace_val_q :std_ulogic; +signal ex4_instr_trace_val_d :std_ulogic; +signal ex4_instr_trace_val_q :std_ulogic; +signal trace_unit_sel :std_ulogic_vector(0 to 15); + +constant trace_bus_enable_offset :integer := 0; +constant ex3_instr_trace_val_offset :integer := trace_bus_enable_offset + 1; +constant ex4_instr_trace_val_offset :integer := ex3_instr_trace_val_offset + 1; +constant unit_trace_sel_offset :integer := ex4_instr_trace_val_offset + 1; +constant scan_right :integer := unit_trace_sel_offset + unit_trace_sel_q'length; + +signal dbg_scan_out :std_ulogic; +signal siv :std_ulogic_vector(0 to scan_right-1); +signal sov :std_ulogic_vector(0 to scan_right-1); +signal tiup :std_ulogic; + +begin + +tiup <= '1'; + + + +ex3_instr_trace_val_d <= xu_lsu_ex2_instr_trace_val; +ex4_instr_trace_val_d <= ex3_instr_trace_val_q; + +with ex3_instr_trace_val_q select + trace_unit_sel <= unit_trace_sel_q when '0', + x"09E0" when others; + + + + + +lsu_dbg_group0_0 <= dc_val_dbg_data(208 to 215) & dc_val_dbg_data(216 to 220) & dc_val_dbg_data(293) & dc_val_dbg_data(226 to 229) & + dc_cntrl_dbg_data(24) & dc_cntrl_dbg_data(25) & dc_cntrl_dbg_data(26) & dc_cntrl_dbg_data(27); + +lsu_dbg_group0_1 <= dc_val_dbg_data(264 to 267) & dc_val_dbg_data(268 to 271) & dc_cntrl_dbg_data(13 to 21) & dc_cntrl_dbg_data(28) & + dc_cntrl_dbg_data(29) & dc_val_dbg_data(263) & dc_val_dbg_data(262) & dc_val_dbg_data(276); + +lsu_dbg_group0_2 <= dc_cntrl_dbg_data(22) & dc_cntrl_dbg_data(23) & lmq_dbg_grp2(27 to 34) & lmq_dbg_grp3(7) & lmq_dbg_grp2(46) & lmq_dbg_grp3(50) & dc_cntrl_dbg_data(30 to 38); + +lsu_dbg_group0_3 <= dc_cntrl_dbg_data(39 to 60); + +lsu_dbg_group0 <= lsu_dbg_group0_0 & lsu_dbg_group0_1 & lsu_dbg_group0_2 & lsu_dbg_group0_3; + + + + + + +lsu_dbg_group1_b64 <= lmq_dbg_grp2(46) and not ex4_instr_trace_val_q; +lsu_dbg_group1_b67 <= dc_cntrl_dbg_data(23) or ex4_instr_trace_val_q; +lsu_dbg_group1_0 <= dc_val_dbg_data(208 to 215) & dc_val_dbg_data(216 to 220) & dc_val_dbg_data(293) & dc_val_dbg_data(226 to 229) & + dc_cntrl_dbg_data(61 to 64); + +lsu_dbg_group1_1 <= dc_val_dbg_data(274) & dc_fgen_dbg_data(0) & lmq_dbg_grp2(27 to 34) & lmq_dbg_grp3(7) & dc_cntrl_dbg_data(30 to 40); + +lsu_dbg_group1_2 <= dc_cntrl_dbg_data(41 to 60) & lsu_dbg_group1_b64 & lmq_dbg_grp3(50); + +lsu_dbg_group1_3 <= dc_cntrl_dbg_data(22) & lsu_dbg_group1_b67 & dc_fgen_dbg_data(1) & dc_dir_dbg_data(0) & + dc_dir_dbg_data(1) & dc_dir_dbg_data(2) & dc_lru_dbg_data(80) & dc_val_dbg_data(275) & + dc_lru_dbg_data(77 to 79) & dc_dir_dbg_data(4) & dc_cntrl_dbg_data(8 to 9) & dc_val_dbg_data(272) & + dc_lru_dbg_data(75 to 76) & dc_val_dbg_data(221 to 225); + +lsu_dbg_group1 <= lsu_dbg_group1_0 & lsu_dbg_group1_1 & lsu_dbg_group1_2 & lsu_dbg_group1_3; + + + + + +wayDbgGen : for w in 0 to 7 generate begin + + lsu_dbg_way_0(w) <= (others=>'0'); + lsu_dbg_way_1(w) <= (others=>'0'); + lsu_dbg_way_2(w) <= (others=>'0'); + lsu_dbg_way_3(w) <= (others=>'0'); +end generate wayDbgGen; + +lsu_dbg_group2_0 <= lsu_dbg_way_0(0); +lsu_dbg_group2_1 <= lsu_dbg_way_1(0); +lsu_dbg_group2_2 <= lsu_dbg_way_2(0); +lsu_dbg_group2_3 <= lsu_dbg_way_3(0); +lsu_dbg_group2 <= lsu_dbg_group2_0 & lsu_dbg_group2_1 & lsu_dbg_group2_2 & lsu_dbg_group2_3; + + + + + +lsu_dbg_group3_0 <= lsu_dbg_way_0(1); +lsu_dbg_group3_1 <= lsu_dbg_way_1(1); +lsu_dbg_group3_2 <= lsu_dbg_way_2(1); +lsu_dbg_group3_3 <= lsu_dbg_way_3(1); +lsu_dbg_group3 <= lsu_dbg_group3_0 & lsu_dbg_group3_1 & lsu_dbg_group3_2 & lsu_dbg_group3_3; + + + + + +lsu_dbg_group4_0 <= lsu_dbg_way_0(2); +lsu_dbg_group4_1 <= lsu_dbg_way_1(2); +lsu_dbg_group4_2 <= lsu_dbg_way_2(2); +lsu_dbg_group4_3 <= lsu_dbg_way_3(2); +lsu_dbg_group4 <= lsu_dbg_group4_0 & lsu_dbg_group4_1 & lsu_dbg_group4_2 & lsu_dbg_group4_3; + + + + + +lsu_dbg_group5_0 <= lsu_dbg_way_0(3); +lsu_dbg_group5_1 <= lsu_dbg_way_1(3); +lsu_dbg_group5_2 <= lsu_dbg_way_2(3); +lsu_dbg_group5_3 <= lsu_dbg_way_3(3); +lsu_dbg_group5 <= lsu_dbg_group5_0 & lsu_dbg_group5_1 & lsu_dbg_group5_2 & lsu_dbg_group5_3; + + + + + +lsu_dbg_group6_0 <= lsu_dbg_way_0(4); +lsu_dbg_group6_1 <= lsu_dbg_way_1(4); +lsu_dbg_group6_2 <= lsu_dbg_way_2(4); +lsu_dbg_group6_3 <= lsu_dbg_way_3(4); +lsu_dbg_group6 <= lsu_dbg_group6_0 & lsu_dbg_group6_1 & lsu_dbg_group6_2 & lsu_dbg_group6_3; + + + + + +lsu_dbg_group7_0 <= lsu_dbg_way_0(5); +lsu_dbg_group7_1 <= lsu_dbg_way_1(5); +lsu_dbg_group7_2 <= lsu_dbg_way_2(5); +lsu_dbg_group7_3 <= lsu_dbg_way_3(5); +lsu_dbg_group7 <= lsu_dbg_group7_0 & lsu_dbg_group7_1 & lsu_dbg_group7_2 & lsu_dbg_group7_3; + + + + + +lsu_dbg_group8_0 <= lsu_dbg_way_0(6); +lsu_dbg_group8_1 <= lsu_dbg_way_1(6); +lsu_dbg_group8_2 <= lsu_dbg_way_2(6); +lsu_dbg_group8_3 <= lsu_dbg_way_3(6); +lsu_dbg_group8 <= lsu_dbg_group8_0 & lsu_dbg_group8_1 & lsu_dbg_group8_2 & lsu_dbg_group8_3; + + + + + +lsu_dbg_group9_0 <= lsu_dbg_way_0(7); +lsu_dbg_group9_1 <= lsu_dbg_way_1(7); +lsu_dbg_group9_2 <= lsu_dbg_way_2(7); +lsu_dbg_group9_3 <= lsu_dbg_way_3(7); +lsu_dbg_group9 <= lsu_dbg_group9_0 & lsu_dbg_group9_1 & lsu_dbg_group9_2 & lsu_dbg_group9_3; + + + + + +lsu_dbg_group10_0 <= dc_dir_dbg_data(0) & dc_dir_dbg_data(1) & dc_dir_dbg_data(2) & dc_lru_dbg_data(80) & + dc_val_dbg_data(275) & dc_lru_dbg_data(77 to 79) & dc_dir_dbg_data(4) & dc_fgen_dbg_data(0) & + dc_val_dbg_data(274) & dc_cntrl_dbg_data(0) & dc_dir_dbg_data(3) & dc_cntrl_dbg_data(1 to 9); + +lsu_dbg_group10_1 <= dc_val_dbg_data(272) & dc_val_dbg_data(273) & dc_cntrl_dbg_data(10) & dc_lru_dbg_data(75 to 76) & + dc_cntrl_dbg_data(11) & dc_lru_dbg_data(0 to 7) & dc_lru_dbg_data(44) & dc_lru_dbg_data(52 to 58); + +lsu_dbg_group10_2 <= dc_lru_dbg_data(16 to 23) & dc_dir_dbg_data(5 to 18); + +lsu_dbg_group10_3 <= dc_dir_dbg_data(19 to 35) & dc_val_dbg_data(21 to 25); + +lsu_dbg_group10 <= lsu_dbg_group10_0 & lsu_dbg_group10_1 & lsu_dbg_group10_2 & lsu_dbg_group10_3; + + + + + +lsu_dbg_group11_0 <= dc_dir_dbg_data(0) & dc_dir_dbg_data(1) & dc_dir_dbg_data(2) & dc_lru_dbg_data(80) & + dc_val_dbg_data(275) & dc_lru_dbg_data(77 to 79) & dc_dir_dbg_data(4) & dc_fgen_dbg_data(0) & + dc_val_dbg_data(274) & dc_cntrl_dbg_data(8 to 9) & dc_val_dbg_data(272) & dc_lru_dbg_data(75 to 76) & + dc_cntrl_dbg_data(11) & dc_lru_dbg_data(59) & dc_lru_dbg_data(8 to 11); + +lsu_dbg_group11_1 <= dc_lru_dbg_data(12 to 15) & '0' & '0' & dc_lru_dbg_data(16 to 23) & dc_lru_dbg_data(24 to 31); + +lsu_dbg_group11_2 <= dc_lru_dbg_data(0 to 7) & dc_dir_dbg_data(5 to 18); + +lsu_dbg_group11_3 <= dc_dir_dbg_data(19 to 35) & dc_val_dbg_data(21 to 25); + +lsu_dbg_group11 <= lsu_dbg_group11_0 & lsu_dbg_group11_1 & lsu_dbg_group11_2 & lsu_dbg_group11_3; + + + + + +lsu_dbg_group12_0 <= dc_dir_dbg_data(0) & dc_lru_dbg_data(77 to 79) & dc_lru_dbg_data(75 to 76) & dc_lru_dbg_data(42 to 43) & + dc_val_dbg_data(221 to 225) & dc_lru_dbg_data(24 to 31) & dc_lru_dbg_data(44); + +lsu_dbg_group12_1 <= dc_lru_dbg_data(32 to 39) & dc_lru_dbg_data(45 to 51) & dc_lru_dbg_data(52 to 58); + +lsu_dbg_group12_2 <= dc_lru_dbg_data(0 to 7) & dc_lru_dbg_data(59) & dc_val_dbg_data(216 to 220) & dc_lru_dbg_data(60 to 66) & + dc_lru_dbg_data(67); + +lsu_dbg_group12_3 <= dc_lru_dbg_data(68 to 74) & dc_val_dbg_data(208 to 215) & dc_lru_dbg_data(81) & dc_cntrl_dbg_data(11) & + dc_lru_dbg_data(40 to 41) & "000"; + +lsu_dbg_group12 <= lsu_dbg_group12_0 & lsu_dbg_group12_1 & lsu_dbg_group12_2 & lsu_dbg_group12_3; + + + + + +lsu_dbg_group13_0 <= dc_val_dbg_data(277) & dc_val_dbg_data(278) & dc_val_dbg_data(279 to 280) & dc_val_dbg_data(281 to 282) & + dc_val_dbg_data(283) & dc_val_dbg_data(284 to 291) & dc_val_dbg_data(292) & dc_dir_dbg_data(0) & + dc_dir_dbg_data(1) & dc_dir_dbg_data(2) & dc_lru_dbg_data(77 to 79); + +lsu_dbg_group13_1 <= dc_val_dbg_data(221 to 225) & pe_recov_begin & lmq_dbg_dcache_pe(1 to 6) & lmq_dbg_dcache_pe(58 to 60) & + lmq_dbg_dcache_pe(7 to 13); + +lsu_dbg_group13_2 <= lmq_dbg_dcache_pe(14 to 35); + +lsu_dbg_group13_3 <= lmq_dbg_dcache_pe(36 to 57); + +lsu_dbg_group13 <= lsu_dbg_group13_0 & lsu_dbg_group13_1 & lsu_dbg_group13_2 & lsu_dbg_group13_3; + + + + + + +lsu_dbg_group14_0 <= lmq_dbg_l2req(0 to 5) & lmq_dbg_l2req(67 to 77) & lmq_dbg_l2req(82 to 84) & lmq_dbg_l2req(64 to 65); + +lsu_dbg_group14_1 <= lmq_dbg_l2req(66) & lmq_dbg_l2req(78 to 81) & lmq_dbg_rel(0 to 12) & lmq_dbg_pops(0 to 3); + +lsu_dbg_group14_2 <= lmq_dbg_pops(4 to 5) & lmq_dbg_l2req(6 to 25); + +lsu_dbg_group14_3 <= lmq_dbg_l2req(26 to 47); + +lsu_dbg_group14 <= lsu_dbg_group14_0 & lsu_dbg_group14_1 & lsu_dbg_group14_2 & lsu_dbg_group14_3; + + + + + + +dataDbgGen : for w in 0 to 3 generate begin + l2cmdq_dbg_data_0(w) <= lmq_dbg_l2req(0) & lmq_dbg_l2req(67 to 72) & lmq_dbg_l2req(74) & lmq_dbg_l2req(76 to 77) & lmq_dbg_l2req(48+(4*w) to 51+(4*w)) & lmq_dbg_l2req(6 to 13); + l2cmdq_dbg_data_1(w) <= lmq_dbg_l2req(14 to 35); + l2cmdq_dbg_data_2(w) <= lmq_dbg_l2req(36 to 47) & lmq_dbg_l2req(85+(32*w) to 94+(32*w)); + l2cmdq_dbg_data_3(w) <= lmq_dbg_l2req(95+(32*w) to 116+(32*w)); +end generate dataDbgGen; + + +lsu_dbg_group15_0 <= l2cmdq_dbg_data_0(0); +lsu_dbg_group15_1 <= l2cmdq_dbg_data_1(0); +lsu_dbg_group15_2 <= l2cmdq_dbg_data_2(0); +lsu_dbg_group15_3 <= l2cmdq_dbg_data_3(0); +lsu_dbg_group15 <= lsu_dbg_group15_0 & lsu_dbg_group15_1 & lsu_dbg_group15_2 & lsu_dbg_group15_3; + + + + + + +lsu_dbg_group16_0 <= l2cmdq_dbg_data_0(1); +lsu_dbg_group16_1 <= l2cmdq_dbg_data_1(1); +lsu_dbg_group16_2 <= l2cmdq_dbg_data_2(1); +lsu_dbg_group16_3 <= l2cmdq_dbg_data_3(1); +lsu_dbg_group16 <= lsu_dbg_group16_0 & lsu_dbg_group16_1 & lsu_dbg_group16_2 & lsu_dbg_group16_3; + + + + + + +lsu_dbg_group17_0 <= l2cmdq_dbg_data_0(2); +lsu_dbg_group17_1 <= l2cmdq_dbg_data_1(2); +lsu_dbg_group17_2 <= l2cmdq_dbg_data_2(2); +lsu_dbg_group17_3 <= l2cmdq_dbg_data_3(2); +lsu_dbg_group17 <= lsu_dbg_group17_0 & lsu_dbg_group17_1 & lsu_dbg_group17_2 & lsu_dbg_group17_3; + + + + + + +lsu_dbg_group18_0 <= l2cmdq_dbg_data_0(3); +lsu_dbg_group18_1 <= l2cmdq_dbg_data_1(3); +lsu_dbg_group18_2 <= l2cmdq_dbg_data_2(3); +lsu_dbg_group18_3 <= l2cmdq_dbg_data_3(3); +lsu_dbg_group18 <= lsu_dbg_group18_0 & lsu_dbg_group18_1 & lsu_dbg_group18_2 & lsu_dbg_group18_3; + + + + + + +lsu_dbg_group19_0 <= lmq_dbg_l2req(0) & lmq_dbg_l2req(2 to 5) & lmq_dbg_l2req(67 to 72) & lmq_dbg_l2req(74) & lmq_dbg_rel(0 to 3) & lmq_dbg_rel(5 to 10); +lsu_dbg_group19_1 <= lmq_dbg_rel(11 to 12) & lmq_dbg_rel(13 to 32); +lsu_dbg_group19_2 <= lmq_dbg_rel(33 to 54); +lsu_dbg_group19_3 <= lmq_dbg_rel(55 to 76); +lsu_dbg_group19 <= lsu_dbg_group19_0 & lsu_dbg_group19_1 & lsu_dbg_group19_2 & lsu_dbg_group19_3; + + + + + + +lsu_dbg_group20_0 <= lmq_dbg_l2req(0) & lmq_dbg_l2req(2 to 5) & lmq_dbg_l2req(67 to 72) & lmq_dbg_l2req(74) & lmq_dbg_rel(0 to 3) & lmq_dbg_rel(5 to 10); +lsu_dbg_group20_1 <= lmq_dbg_rel(11 to 12) & lmq_dbg_rel(77 to 96); +lsu_dbg_group20_2 <= lmq_dbg_rel(97 to 118); +lsu_dbg_group20_3 <= lmq_dbg_rel(119 to 140); +lsu_dbg_group20 <= lsu_dbg_group20_0 & lsu_dbg_group20_1 & lsu_dbg_group20_2 & lsu_dbg_group20_3; + + + + + + +lsu_dbg_group21_0 <= lmq_dbg_binv(1 to 22); +lsu_dbg_group21_1 <= lmq_dbg_binv(23 to 42) & lmq_dbg_binv(43 to 44); +lsu_dbg_group21_2 <= lmq_dbg_binv(0) & lmq_dbg_grp0(40 to 47) & dc_val_dbg_data(208 to 215) & dc_val_dbg_data(216 to 220); +lsu_dbg_group21_3 <= dc_val_dbg_data(293) & dc_cntrl_dbg_data(40 to 60); +lsu_dbg_group21 <= lsu_dbg_group21_0 & lsu_dbg_group21_1 & lsu_dbg_group21_2 & lsu_dbg_group21_3; + + + +lmq_dbg_rel_ctrl <= dc_dir_dbg_data(3) & dc_dir_dbg_data(0 to 2) & dc_cntrl_dbg_data(0) & dc_dir_dbg_data(4); + +lsu_dbg_group22 <= lmq_dbg_grp0(0 to 71) & lmq_dbg_rel_ctrl & lmq_dbg_grp0(72 to 81); + + + +lsu_dbg_group23 <= lmq_dbg_grp1(0 to 71) & lmq_dbg_rel_ctrl & lmq_dbg_grp1(72 to 81); + + + +lsu_dbg_group24 <= lmq_dbg_grp2; + + + +lsu_dbg_group25 <= lmq_dbg_grp3; + + + +lsu_dbg_group26 <= (others=>'0'); + + + +lsu_dbg_group27 <= lmq_dbg_grp5; + + + +lsu_dbg_group28 <= lmq_dbg_grp6; + + + + + + + + +lsu_dbg_group29_0 <= dir_arr_dbg_data(0 to 16) & dir_arr_dbg_data(55) & dir_arr_dbg_data(48 to 51); +lsu_dbg_group29_1 <= dir_arr_dbg_data(52 to 54) & dir_arr_dbg_data(56 to 60) & dir_arr_dbg_data(17 to 30); +lsu_dbg_group29_2 <= dir_arr_dbg_data(31 to 47) & "00000"; +lsu_dbg_group29_3 <= (others=>'0'); +lsu_dbg_group29 <= lsu_dbg_group29_0 & lsu_dbg_group29_1 & lsu_dbg_group29_2 & lsu_dbg_group29_3; +lsu_dbg_group30 <= derat_xu_debug_group0; +lsu_dbg_group31 <= derat_xu_debug_group1; + + + +lsu_trg_group0 <= dc_val_dbg_data(293) & dc_cntrl_dbg_data(65 to 66) & dc_cntrl_dbg_data(22 to 23) & dc_fgen_dbg_data(1) & + dc_cntrl_dbg_data(12) & dc_cntrl_dbg_data(26) & dc_val_dbg_data(226 to 229); + + + +lsu_trg_group1 <= lmq_dbg_l2req(0) & lmq_dbg_l2req(64 to 65) & lmq_dbg_l2req(67 to 72) & lmq_dbg_l2req(74 to 76); + +lsu_trg_group2 <= (others=>'0'); +lsu_trg_group3 <= (others=>'0'); + + + +dbg : entity work.xuq_debug_mux32(xuq_debug_mux32) +port map( + + trace_bus_enable => trace_bus_enable_q, + trace_unit_sel => trace_unit_sel, + + debug_data_in => debug_data_in, + trigger_data_in => trigger_data_in, + + dbg_group0 => lsu_dbg_group0, + dbg_group1 => lsu_dbg_group1, + dbg_group2 => lsu_dbg_group2, + dbg_group3 => lsu_dbg_group3, + dbg_group4 => lsu_dbg_group4, + dbg_group5 => lsu_dbg_group5, + dbg_group6 => lsu_dbg_group6, + dbg_group7 => lsu_dbg_group7, + dbg_group8 => lsu_dbg_group8, + dbg_group9 => lsu_dbg_group9, + dbg_group10 => lsu_dbg_group10, + dbg_group11 => lsu_dbg_group11, + dbg_group12 => lsu_dbg_group12, + dbg_group13 => lsu_dbg_group13, + dbg_group14 => lsu_dbg_group14, + dbg_group15 => lsu_dbg_group15, + dbg_group16 => lsu_dbg_group16, + dbg_group17 => lsu_dbg_group17, + dbg_group18 => lsu_dbg_group18, + dbg_group19 => lsu_dbg_group19, + dbg_group20 => lsu_dbg_group20, + dbg_group21 => lsu_dbg_group21, + dbg_group22 => lsu_dbg_group22, + dbg_group23 => lsu_dbg_group23, + dbg_group24 => lsu_dbg_group24, + dbg_group25 => lsu_dbg_group25, + dbg_group26 => lsu_dbg_group26, + dbg_group27 => lsu_dbg_group27, + dbg_group28 => lsu_dbg_group28, + dbg_group29 => lsu_dbg_group29, + dbg_group30 => lsu_dbg_group30, + dbg_group31 => lsu_dbg_group31, + + trg_group0 => lsu_trg_group0, + trg_group1 => lsu_trg_group1, + trg_group2 => lsu_trg_group2, + trg_group3 => lsu_trg_group3, + + trigger_data_out => trigger_data_out, + debug_data_out => debug_data_out, + + vdd => vdd, + gnd => gnd, + nclk => nclk, + sg_0 => sg_0, + func_slp_sl_thold_0_b => func_slp_sl_thold_0_b, + func_slp_sl_force => func_slp_sl_force, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc, + mpw1_dc_b => mpw1_dc_b, + mpw2_dc_b => mpw2_dc_b, + scan_in => scan_in, + scan_out => dbg_scan_out +); + +trace_bus_enable_latch : tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 0) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(trace_bus_enable_offset), + scout => sov(trace_bus_enable_offset), + din => pc_xu_trace_bus_enable, + dout => trace_bus_enable_q); +ex3_instr_trace_val_latch : tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 0) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_instr_trace_val_offset), + scout => sov(ex3_instr_trace_val_offset), + din => ex3_instr_trace_val_d, + dout => ex3_instr_trace_val_q); +ex4_instr_trace_val_latch : tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 0) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_instr_trace_val_offset), + scout => sov(ex4_instr_trace_val_offset), + din => ex4_instr_trace_val_d, + dout => ex4_instr_trace_val_q); +unit_trace_sel_latch : tri_rlmreg_p +generic map (width => unit_trace_sel_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => trace_bus_enable_q, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(unit_trace_sel_offset to unit_trace_sel_offset + unit_trace_sel_q'length-1), + scout => sov(unit_trace_sel_offset to unit_trace_sel_offset + unit_trace_sel_q'length-1), + din => lsu_debug_mux_ctrls, + dout => unit_trace_sel_q); + +siv(0 to scan_right-1) <= sov(1 to scan_right-1) & dbg_scan_out; +scan_out <= sov(0); + +end architecture xuq_lsu_debug; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_derat.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_derat.vhdl new file mode 100644 index 0000000..f26cab2 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_derat.vhdl @@ -0,0 +1,9893 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library ibm; +use ibm.std_ulogic_unsigned.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_support.all; +library support; +use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity xuq_lsu_derat is + generic(thdid_width : integer := 4; + ttype_width : integer := 12; + state_width : integer := 4; + lpid_width : integer := 8; + pid_width : integer := 14; + pid_width_erat : integer := 8; + extclass_width : integer := 2; + tlbsel_width : integer := 2; + epn_width : integer := 52; + vpn_width : integer := 61; + rpn_width : integer := 30; + ws_width : integer := 2; + rs_is_width : integer := 9; + ra_entry_width : integer := 5; + rs_data_width : integer := 64; + data_out_width : integer := 64; + error_width : integer := 3; + cam_data_width : natural := 84; + array_data_width : natural := 68; + num_entry : natural := 32; + num_entry_log2 : natural := 5; + por_seq_width : integer := 3; + watermark_width : integer := 5; + eptr_width : integer := 5; + lru_width : integer := 31; + bcfg_width : integer := 123; + ex2_epn_width : integer := 30; + bcfg_epn_0to15 : integer := 0; + bcfg_epn_16to31 : integer := 0; + bcfg_epn_32to47 : integer := (2**16)-1; + bcfg_epn_48to51 : integer := (2**4)-1; + bcfg_rpn_22to31 : integer := (2**10)-1; + bcfg_rpn_32to47 : integer := (2**16)-1; + bcfg_rpn_48to51 : integer := (2**4)-1; + bcfg_rpn2_32to47 : integer := 0; + bcfg_rpn2_48to51 : integer := 0; + bcfg_attr : integer := 0; + check_parity : integer := 1; + expand_type : integer := 2 ); +port( + gnd : inout power_logic; + vdd : inout power_logic; + vcs : inout power_logic; + nclk : in clk_logic; + pc_xu_init_reset : in std_ulogic; + +pc_xu_ccflush_dc : in std_ulogic; +tc_scan_dis_dc_b : in std_ulogic; +tc_scan_diag_dc : in std_ulogic; +tc_lbist_en_dc : in std_ulogic; +an_ac_atpg_en_dc : in std_ulogic; +an_ac_grffence_en_dc : in std_ulogic; +lcb_d_mode_dc : in std_ulogic; +lcb_clkoff_dc_b : in std_ulogic; +lcb_act_dis_dc : in std_ulogic; +lcb_mpw1_dc_b : in std_ulogic_vector(0 to 4); +lcb_mpw2_dc_b : in std_ulogic; +lcb_delay_lclkr_dc : in std_ulogic_vector(0 to 4); +pc_func_sl_thold_2 : in std_ulogic; +pc_func_slp_sl_thold_2 : in std_ulogic; +pc_func_slp_nsl_thold_2 : in std_ulogic; +pc_cfg_slp_sl_thold_2 : in std_ulogic; +pc_regf_slp_sl_thold_2 : in std_ulogic; +pc_time_sl_thold_2 : in std_ulogic; +pc_sg_2 : in std_ulogic; +pc_fce_2 : in std_ulogic; +cam_clkoff_dc_b : in std_ulogic; +cam_act_dis_dc : in std_ulogic; +cam_d_mode_dc : in std_ulogic; +cam_delay_lclkr_dc : in std_ulogic_vector(0 to 4); +cam_mpw1_dc_b : in std_ulogic_vector(0 to 4); +cam_mpw2_dc_b : in std_ulogic; +ac_func_scan_in : in std_ulogic_vector(0 to 1); +ac_func_scan_out : out std_ulogic_vector(0 to 1); +ac_ccfg_scan_in : in std_ulogic; +ac_ccfg_scan_out : out std_ulogic; +time_scan_in : in std_ulogic; +time_scan_out : out std_ulogic; +regf_scan_in : in std_ulogic_vector(0 to 6); +regf_scan_out : out std_ulogic_vector(0 to 6); +spr_xucr0_clkg_ctl_b1 : in std_ulogic; +spr_xucr4_mmu_mchk : in std_ulogic; +xu_derat_rf0_val : in std_ulogic_vector(0 to thdid_width-1); +xu_derat_rf0_is_extload : in std_ulogic; +xu_derat_rf0_is_extstore : in std_ulogic; +xu_derat_rf1_is_load : in std_ulogic; +xu_derat_rf1_is_store : in std_ulogic; +xu_derat_rf1_is_eratre : in std_ulogic; +xu_derat_rf1_is_eratwe : in std_ulogic; +xu_derat_rf1_is_eratsx : in std_ulogic; +xu_derat_rf1_is_eratilx : in std_ulogic; +xu_derat_ex1_is_isync : in std_ulogic; +xu_derat_ex1_is_csync : in std_ulogic; +xu_derat_rf1_is_touch : in std_ulogic; +xu_derat_rf1_icbtls_instr : in std_ulogic; +xu_derat_rf1_icblc_instr : in std_ulogic; +xu_derat_rf1_act : in std_ulogic; +xu_derat_rf1_ra_eq_ea : in std_ulogic; +xu_derat_rf1_ws : in std_ulogic_vector(0 to ws_width-1); +xu_derat_rf1_t : in std_ulogic_vector(0 to 2); +xu_derat_rf1_binv_val : in std_ulogic; +xu_derat_ex1_rs_is : in std_ulogic_vector(0 to rs_is_width-1); +xu_derat_ex1_ra_entry : in std_ulogic_vector(0 to ra_entry_width-1); +xu_derat_ex1_epn_arr : in std_ulogic_vector(64-rs_data_width to 51); +xu_derat_ex1_epn_nonarr : in std_ulogic_vector(64-rs_data_width to 51); +snoop_addr : out std_ulogic_vector(64-rs_data_width to 51); +snoop_addr_sel : out std_ulogic; +xu_derat_rf0_n_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_derat_rf1_n_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_derat_ex1_n_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_derat_ex2_n_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_derat_ex3_n_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_derat_ex4_n_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_derat_ex5_n_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_derat_ex4_rs_data : in std_ulogic_vector(64-rs_data_width to 63); +xu_derat_msr_hv : in std_ulogic_vector(0 to thdid_width-1); +xu_derat_msr_pr : in std_ulogic_vector(0 to thdid_width-1); +xu_derat_msr_ds : in std_ulogic_vector(0 to thdid_width-1); +xu_derat_msr_cm : in std_ulogic_vector(0 to thdid_width-1); +xu_derat_hid_mmu_mode : in std_ulogic; +xu_derat_spr_ccr2_dfrat : in std_ulogic; +xu_derat_spr_ccr2_dfratsc : in std_ulogic_vector(0 to 8); +derat_xu_ex2_miss : out std_ulogic_vector(0 to thdid_width-1); +derat_xu_ex2_rpn : out std_ulogic_vector(22 to 51); +derat_xu_ex2_wimge : out std_ulogic_vector(0 to 4); +derat_xu_ex2_u : out std_ulogic_vector(0 to 3); +derat_xu_ex2_wlc : out std_ulogic_vector(0 to 1); +derat_xu_ex2_attr : out std_ulogic_vector(0 to 5); +derat_xu_ex2_vf : out std_ulogic; +derat_xu_ex3_rpn : out std_ulogic_vector(22 to 51); +derat_xu_ex3_wimge : out std_ulogic_vector(0 to 4); +derat_xu_ex3_u : out std_ulogic_vector(0 to 3); +derat_xu_ex3_wlc : out std_ulogic_vector(0 to 1); +derat_xu_ex3_attr : out std_ulogic_vector(0 to 5); +derat_xu_ex3_vf : out std_ulogic; +derat_xu_ex3_miss : out std_ulogic_vector(0 to thdid_width-1); +derat_xu_ex3_dsi : out std_ulogic_vector(0 to thdid_width-1); +derat_xu_ex3_par_err : out std_ulogic_vector(0 to thdid_width-1); +derat_xu_ex3_multihit_err : out std_ulogic_vector(0 to thdid_width-1); +derat_xu_ex3_noop_touch : out std_ulogic_vector(0 to thdid_width-1); +derat_xu_ex3_n_flush_req : out std_ulogic_vector(0 to thdid_width-1); +derat_xu_ex4_data : out std_ulogic_vector(64-data_out_width to 63); +derat_xu_ex4_par_err : out std_ulogic_vector(0 to thdid_width-1); +derat_iu_barrier_done : out std_ulogic_vector(0 to thdid_width-1); +derat_fir_par_err : out std_ulogic_vector(0 to thdid_width-1); +derat_fir_multihit : out std_ulogic_vector(0 to thdid_width-1); +xu_derat_epsc_wr : in std_ulogic_vector(0 to 3); +xu_derat_eplc_wr : in std_ulogic_vector(0 to 3); +xu_derat_eplc0_epr : in std_ulogic; +xu_derat_eplc0_eas : in std_ulogic; +xu_derat_eplc0_egs : in std_ulogic; +xu_derat_eplc0_elpid : in std_ulogic_vector(40 to 47); +xu_derat_eplc0_epid : in std_ulogic_vector(50 to 63); +xu_derat_eplc1_epr : in std_ulogic; +xu_derat_eplc1_eas : in std_ulogic; +xu_derat_eplc1_egs : in std_ulogic; +xu_derat_eplc1_elpid : in std_ulogic_vector(40 to 47); +xu_derat_eplc1_epid : in std_ulogic_vector(50 to 63); +xu_derat_eplc2_epr : in std_ulogic; +xu_derat_eplc2_eas : in std_ulogic; +xu_derat_eplc2_egs : in std_ulogic; +xu_derat_eplc2_elpid : in std_ulogic_vector(40 to 47); +xu_derat_eplc2_epid : in std_ulogic_vector(50 to 63); +xu_derat_eplc3_epr : in std_ulogic; +xu_derat_eplc3_eas : in std_ulogic; +xu_derat_eplc3_egs : in std_ulogic; +xu_derat_eplc3_elpid : in std_ulogic_vector(40 to 47); +xu_derat_eplc3_epid : in std_ulogic_vector(50 to 63); +xu_derat_epsc0_epr : in std_ulogic; +xu_derat_epsc0_eas : in std_ulogic; +xu_derat_epsc0_egs : in std_ulogic; +xu_derat_epsc0_elpid : in std_ulogic_vector(40 to 47); +xu_derat_epsc0_epid : in std_ulogic_vector(50 to 63); +xu_derat_epsc1_epr : in std_ulogic; +xu_derat_epsc1_eas : in std_ulogic; +xu_derat_epsc1_egs : in std_ulogic; +xu_derat_epsc1_elpid : in std_ulogic_vector(40 to 47); +xu_derat_epsc1_epid : in std_ulogic_vector(50 to 63); +xu_derat_epsc2_epr : in std_ulogic; +xu_derat_epsc2_eas : in std_ulogic; +xu_derat_epsc2_egs : in std_ulogic; +xu_derat_epsc2_elpid : in std_ulogic_vector(40 to 47); +xu_derat_epsc2_epid : in std_ulogic_vector(50 to 63); +xu_derat_epsc3_epr : in std_ulogic; +xu_derat_epsc3_eas : in std_ulogic; +xu_derat_epsc3_egs : in std_ulogic; +xu_derat_epsc3_elpid : in std_ulogic_vector(40 to 47); +xu_derat_epsc3_epid : in std_ulogic_vector(50 to 63); +xu_mm_derat_req : out std_ulogic; +xu_mm_derat_thdid : out std_ulogic_vector(0 to thdid_width-1); +xu_mm_derat_ttype : out std_ulogic_vector(0 to 1); +xu_mm_derat_state : out std_ulogic_vector(0 to state_width-1); +xu_mm_derat_lpid : out std_ulogic_vector(0 to lpid_width-1); +xu_mm_derat_tid : out std_ulogic_vector(0 to pid_width-1); +mm_xu_derat_rel_val : in std_ulogic_vector(0 to 4); +mm_xu_derat_rel_data : in std_ulogic_vector(0 to 131); +mm_xu_derat_pid0 : in std_ulogic_vector(0 to pid_width-1); +mm_xu_derat_pid1 : in std_ulogic_vector(0 to pid_width-1); +mm_xu_derat_pid2 : in std_ulogic_vector(0 to pid_width-1); +mm_xu_derat_pid3 : in std_ulogic_vector(0 to pid_width-1); +mm_xu_derat_mmucr0_0 : in std_ulogic_vector(0 to 19); +mm_xu_derat_mmucr0_1 : in std_ulogic_vector(0 to 19); +mm_xu_derat_mmucr0_2 : in std_ulogic_vector(0 to 19); +mm_xu_derat_mmucr0_3 : in std_ulogic_vector(0 to 19); +xu_mm_derat_mmucr0 : out std_ulogic_vector(0 to 17); +xu_mm_derat_mmucr0_we : out std_ulogic_vector(0 to 3); +mm_xu_derat_mmucr1 : in std_ulogic_vector(0 to 9); +xu_mm_derat_mmucr1 : out std_ulogic_vector(0 to 4); +xu_mm_derat_mmucr1_we : out std_ulogic; +mm_xu_derat_snoop_coming : in std_ulogic; +mm_xu_derat_snoop_val : in std_ulogic; +mm_xu_derat_snoop_attr : in std_ulogic_vector(0 to 25); +mm_xu_derat_snoop_vpn : in std_ulogic_vector(52-epn_width to 51); +xu_mm_derat_snoop_ack : out std_ulogic; +pc_xu_trace_bus_enable : in std_ulogic; +derat_xu_debug_group0 : out std_ulogic_vector(0 to 87); +derat_xu_debug_group1 : out std_ulogic_vector(0 to 87); +derat_xu_debug_group2 : out std_ulogic_vector(0 to 87); +derat_xu_debug_group3 : out std_ulogic_vector(0 to 87) +); +end xuq_lsu_derat; +ARCHITECTURE XUQ_LSU_DERAT + OF XUQ_LSU_DERAT + IS +SIGNAL CAM_MASK_BITS_PT : STD_ULOGIC_VECTOR(1 TO 19) := +(OTHERS=> 'U'); +SIGNAL EX2_FIRST_HIT_ENTRY_PT : STD_ULOGIC_VECTOR(1 TO 31) := +(OTHERS=> 'U'); +SIGNAL EX2_MULTIHIT_B_PT : STD_ULOGIC_VECTOR(1 TO 32) := +(OTHERS=> 'U'); +SIGNAL LRU_RMT_VEC_D_PT : STD_ULOGIC_VECTOR(1 TO 32) := +(OTHERS=> 'U'); +SIGNAL LRU_SET_RESET_VEC_PT : STD_ULOGIC_VECTOR(1 TO 161) := +(OTHERS=> 'U'); +SIGNAL LRU_WAY_ENCODE_PT : STD_ULOGIC_VECTOR(1 TO 31) := +(OTHERS=> 'U'); +component tri_cam_32x143_1r1w1c + generic (expand_type : integer := 2); + port ( + gnd : inout power_logic; + vdd : inout power_logic; + vcs : inout power_logic; + nclk : in clk_logic; + tc_ccflush_dc : in std_ulogic; + tc_scan_dis_dc_b : in std_ulogic; + tc_scan_diag_dc : in std_ulogic; + tc_lbist_en_dc : in std_ulogic; + an_ac_atpg_en_dc : in std_ulogic; + + lcb_d_mode_dc : in std_ulogic; + lcb_clkoff_dc_b : in std_ulogic; + lcb_act_dis_dc : in std_ulogic; + lcb_mpw1_dc_b : in std_ulogic_vector(0 to 3); + lcb_mpw2_dc_b : in std_ulogic; + lcb_delay_lclkr_dc : in std_ulogic_vector(0 to 3); + + pc_sg_2 : in std_ulogic; + pc_func_slp_sl_thold_2 : in std_ulogic; + pc_func_slp_nsl_thold_2 : in std_ulogic; + pc_regf_slp_sl_thold_2 : in std_ulogic; + pc_time_sl_thold_2 : in std_ulogic; + pc_fce_2 : in std_ulogic; + + func_scan_in : in std_ulogic; + func_scan_out : out std_ulogic; + regfile_scan_in : in std_ulogic_vector(0 to 6); + regfile_scan_out : out std_ulogic_vector(0 to 6); + time_scan_in : in std_ulogic; + time_scan_out : out std_ulogic; + + rd_val : in std_ulogic; + rd_val_late : in std_ulogic; + rw_entry : in std_ulogic_vector(0 to 4); + + wr_array_data : in std_ulogic_vector(0 to array_data_width-1); + wr_cam_data : in std_ulogic_vector(0 to cam_data_width-1); + wr_array_val : in std_ulogic_vector(0 to 1); + wr_cam_val : in std_ulogic_vector(0 to 1); + wr_val_early : in std_ulogic; + + comp_request : in std_ulogic; + comp_addr : in std_ulogic_vector(0 to 51); + addr_enable : in std_ulogic_vector(0 to 1); + comp_pgsize : in std_ulogic_vector(0 to 2); + pgsize_enable : in std_ulogic; + comp_class : in std_ulogic_vector(0 to 1); + class_enable : in std_ulogic_vector(0 to 2); + comp_extclass : in std_ulogic_vector(0 to 1); + extclass_enable : in std_ulogic_vector(0 to 1); + comp_state : in std_ulogic_vector(0 to 1); + state_enable : in std_ulogic_vector(0 to 1); + comp_thdid : in std_ulogic_vector(0 to 3); + thdid_enable : in std_ulogic_vector(0 to 1); + comp_pid : in std_ulogic_vector(0 to 7); + pid_enable : in std_ulogic; + comp_invalidate : in std_ulogic; + flash_invalidate : in std_ulogic; + + array_cmp_data : out std_ulogic_vector(0 to array_data_width-1); + rd_array_data : out std_ulogic_vector(0 to array_data_width-1); + + cam_cmp_data : out std_ulogic_vector(0 to cam_data_width-1); + cam_hit : out std_ulogic; + cam_hit_entry : out std_ulogic_vector(0 to 4); + entry_match : out std_ulogic_vector(0 to 31); + entry_valid : out std_ulogic_vector(0 to 31); + rd_cam_data : out std_ulogic_vector(0 to cam_data_width-1); + + bypass_mux_enab_np1 : in std_ulogic; + bypass_attr_np1 : in std_ulogic_vector(0 to 20); + attr_np2 : out std_ulogic_vector(0 to 20); + rpn_np2 : out std_ulogic_vector(22 to 51) + + ); +END component; +component tri_cam_parerr_mac + generic (expand_type : integer := 2); + port ( + gnd :inout power_logic; + vdd :inout power_logic; + nclk :in std_ulogic; + lcb_act_dis_dc :in std_ulogic; + lcb_delay_lclkr_dc :in std_ulogic; + lcb_clkoff_dc_b_0 :in std_ulogic; + lcb_mpw1_dc_b :in std_ulogic; + lcb_mpw2_dc_b :in std_ulogic; + act :in std_ulogic; + lcb_sg_0 :in std_ulogic; + lcb_func_sl_thold_0 :in std_ulogic; + + func_scan_in :in std_ulogic; + func_scan_out :out std_ulogic; + + np1_cam_cmp_data :in std_ulogic_vector(0 to 83); + np1_array_cmp_data :in std_ulogic_vector(0 to 67); + + np2_cam_cmp_data :out std_ulogic_vector(0 to 83); + np2_array_cmp_data :out std_ulogic_vector(0 to 67); + np2_cmp_data_parerr_epn :out std_ulogic; + np2_cmp_data_parerr_rpn :out std_ulogic + ); +END component; +constant MMU_Mode_Value : std_ulogic := '0'; +constant TlbSel_Tlb : std_ulogic_vector(0 to 1) := "00"; +constant TlbSel_IErat : std_ulogic_vector(0 to 1) := "10"; +constant TlbSel_DErat : std_ulogic_vector(0 to 1) := "11"; +constant CAM_PgSize_1GB : std_ulogic_vector(0 to 2) := "110"; +constant CAM_PgSize_16MB : std_ulogic_vector(0 to 2) := "111"; +constant CAM_PgSize_1MB : std_ulogic_vector(0 to 2) := "101"; +constant CAM_PgSize_64KB : std_ulogic_vector(0 to 2) := "011"; +constant CAM_PgSize_4KB : std_ulogic_vector(0 to 2) := "001"; +constant WS0_PgSize_1GB : std_ulogic_vector(0 to 3) := "1010"; +constant WS0_PgSize_16MB : std_ulogic_vector(0 to 3) := "0111"; +constant WS0_PgSize_1MB : std_ulogic_vector(0 to 3) := "0101"; +constant WS0_PgSize_64KB : std_ulogic_vector(0 to 3) := "0011"; +constant WS0_PgSize_4KB : std_ulogic_vector(0 to 3) := "0001"; +constant eratpos_epn : natural := 0; +constant eratpos_x : natural := 52; +constant eratpos_size : natural := 53; +constant eratpos_v : natural := 56; +constant eratpos_thdid : natural := 57; +constant eratpos_class : natural := 61; +constant eratpos_extclass : natural := 63; +constant eratpos_wren : natural := 65; +constant eratpos_rpnrsvd : natural := 66; +constant eratpos_rpn : natural := 70; +constant eratpos_r : natural := 100; +constant eratpos_c : natural := 101; +constant eratpos_relsoon : natural := 102; +constant eratpos_wlc : natural := 103; +constant eratpos_resvattr : natural := 105; +constant eratpos_vf : natural := 106; +constant eratpos_ubits : natural := 107; +constant eratpos_wimge : natural := 111; +constant eratpos_usxwr : natural := 116; +constant eratpos_gs : natural := 122; +constant eratpos_ts : natural := 123; +constant eratpos_tid : natural := 124; +constant PorSeq_Idle : std_ulogic_vector(0 to 2) := "000"; +constant PorSeq_Stg1 : std_ulogic_vector(0 to 2) := "001"; +constant PorSeq_Stg2 : std_ulogic_vector(0 to 2) := "011"; +constant PorSeq_Stg3 : std_ulogic_vector(0 to 2) := "010"; +constant PorSeq_Stg4 : std_ulogic_vector(0 to 2) := "110"; +constant PorSeq_Stg5 : std_ulogic_vector(0 to 2) := "100"; +constant PorSeq_Stg6 : std_ulogic_vector(0 to 2) := "101"; +constant PorSeq_Stg7 : std_ulogic_vector(0 to 2) := "111"; +constant Por_Wr_Entry_Num1 : std_ulogic_vector(0 to num_entry_log2-1) := "11110"; +constant Por_Wr_Entry_Num2 : std_ulogic_vector(0 to num_entry_log2-1) := "11111"; +constant Por_Wr_Cam_Data1 : std_ulogic_vector(0 to 83) := "0000000000000000000000000000000011111111111111111111" & + '0' & "001" & '1' & "1111" & "00" & "00" & "00" & "00000000" & "11110000" & '0'; +constant Por_Wr_Cam_Data2 : std_ulogic_vector(0 to 83) := "0000000000000000000000000000000000000000000000000000" & + '0' & "001" & '1' & "1111" & "00" & "10" & "00" & "00000000" & "11110000" & '0'; +constant Por_Wr_Array_Data1 : std_ulogic_vector(0 to 67) := "111111111111111111111111111111" & + "00" & "0000" & "0000" & "01010" & "01" & "00" & "01" & "0000001000" & "0000000"; +constant Por_Wr_Array_Data2 : std_ulogic_vector(0 to 67) := "000000000000000000000000000000" & + "00" & "0000" & "0000" & "01010" & "01" & "00" & "01" & "0000001010" & "0000000"; +constant rf1_valid_offset : natural := 0; +constant rf1_ttype_offset : natural := rf1_valid_offset + thdid_width; +constant ex1_valid_offset : natural := rf1_ttype_offset + 2; +constant ex1_ttype_offset : natural := ex1_valid_offset + thdid_width; +constant ex1_ws_offset : natural := ex1_ttype_offset + ttype_width; +constant ex1_rs_is_offset : natural := ex1_ws_offset + ws_width; +constant ex1_ra_entry_offset : natural := ex1_rs_is_offset + rs_is_width; +constant ex1_state_offset : natural := ex1_ra_entry_offset + ra_entry_width; +constant ex1_pid_offset : natural := ex1_state_offset + state_width; +constant ex1_extclass_offset : natural := ex1_pid_offset + pid_width; +constant ex1_tlbsel_offset : natural := ex1_extclass_offset + extclass_width; +constant ex2_valid_offset : natural := ex1_tlbsel_offset + tlbsel_width; +constant ex2_ttype_offset : natural := ex2_valid_offset + thdid_width; +constant ex2_ws_offset : natural := ex2_ttype_offset + ttype_width; +constant ex2_rs_is_offset : natural := ex2_ws_offset + ws_width; +constant ex2_ra_entry_offset : natural := ex2_rs_is_offset + rs_is_width; +constant ex2_state_offset : natural := ex2_ra_entry_offset + ra_entry_width; +constant ex2_pid_offset : natural := ex2_state_offset + state_width; +constant ex2_extclass_offset : natural := ex2_pid_offset + pid_width; +constant ex2_tlbsel_offset : natural := ex2_extclass_offset + extclass_width; +constant ex3_valid_offset : natural := ex2_tlbsel_offset + tlbsel_width; +constant ex3_ttype_offset : natural := ex3_valid_offset + thdid_width; +constant ex3_ws_offset : natural := ex3_ttype_offset + ttype_width; +constant ex3_rs_is_offset : natural := ex3_ws_offset + ws_width; +constant ex3_ra_entry_offset : natural := ex3_rs_is_offset + rs_is_width; +constant ex3_state_offset : natural := ex3_ra_entry_offset + ra_entry_width; +constant ex3_pid_offset : natural := ex3_state_offset + state_width; +constant ex3_lpid_offset : natural := ex3_pid_offset + pid_width; +constant ex3_extclass_offset : natural := ex3_lpid_offset + lpid_width; +constant ex3_tlbsel_offset : natural := ex3_extclass_offset + extclass_width; +constant ex4_valid_offset : natural := ex3_tlbsel_offset + tlbsel_width; +constant ex4_ttype_offset : natural := ex4_valid_offset + thdid_width; +constant ex4_ws_offset : natural := ex4_ttype_offset + ttype_width; +constant ex4_rs_is_offset : natural := ex4_ws_offset + ws_width; +constant ex4_ra_entry_offset : natural := ex4_rs_is_offset + rs_is_width; +constant ex4_state_offset : natural := ex4_ra_entry_offset + ra_entry_width; +constant ex4_pid_offset : natural := ex4_state_offset + state_width; +constant ex4_extclass_offset : natural := ex4_pid_offset + pid_width; +constant ex4_tlbsel_offset : natural := ex4_extclass_offset + extclass_width; +constant ex5_valid_offset : natural := ex4_tlbsel_offset + tlbsel_width; +constant ex5_ttype_offset : natural := ex5_valid_offset + thdid_width; +constant ex5_ws_offset : natural := ex5_ttype_offset + ttype_width; +constant ex5_rs_is_offset : natural := ex5_ws_offset + ws_width; +constant ex5_ra_entry_offset : natural := ex5_rs_is_offset + rs_is_width; +constant ex5_state_offset : natural := ex5_ra_entry_offset + ra_entry_width; +constant ex5_pid_offset : natural := ex5_state_offset + state_width; +constant ex5_extclass_offset : natural := ex5_pid_offset + pid_width; +constant ex5_tlbsel_offset : natural := ex5_extclass_offset + extclass_width; +constant ex5_data_in_offset : natural := ex5_tlbsel_offset + tlbsel_width; +constant ex6_valid_offset : natural := ex5_data_in_offset + rs_data_width; +constant ex6_ttype_offset : natural := ex6_valid_offset + thdid_width; +constant ex6_ws_offset : natural := ex6_ttype_offset + ttype_width; +constant ex6_rs_is_offset : natural := ex6_ws_offset + ws_width; +constant ex6_ra_entry_offset : natural := ex6_rs_is_offset + rs_is_width; +constant ex6_state_offset : natural := ex6_ra_entry_offset + ra_entry_width; +constant ex6_pid_offset : natural := ex6_state_offset + state_width; +constant ex6_extclass_offset : natural := ex6_pid_offset + pid_width; +constant ex6_tlbsel_offset : natural := ex6_extclass_offset + extclass_width; +constant ex6_data_in_offset : natural := ex6_tlbsel_offset + tlbsel_width; +constant ex7_valid_offset : natural := ex6_data_in_offset + rs_data_width; +constant ex7_ttype_offset : natural := ex7_valid_offset + thdid_width; +constant ex7_tlbsel_offset : natural := ex7_ttype_offset + ttype_width; +constant ex4_data_out_offset : natural := ex7_tlbsel_offset + tlbsel_width; +constant ex2_n_flush_req_offset : natural := ex4_data_out_offset + data_out_width; +constant ex3_n_flush_req_offset : natural := ex2_n_flush_req_offset + thdid_width; +constant hold_req_reset_offset : natural := ex3_n_flush_req_offset + thdid_width; +constant hold_req_pot_set_offset : natural := hold_req_reset_offset + thdid_width; +constant hold_req_por_offset : natural := hold_req_pot_set_offset + thdid_width; +constant hold_req_offset : natural := hold_req_por_offset + thdid_width; +constant tlb_req_inprogress_offset : natural := hold_req_offset + thdid_width; +constant ex2_dsi_offset : natural := tlb_req_inprogress_offset + thdid_width; +constant ex2_noop_touch_offset : natural := ex2_dsi_offset + 16; +constant ex3_miss_offset : natural := ex2_noop_touch_offset + 16; +constant ex3_dsi_offset : natural := ex3_miss_offset + thdid_width; +constant ex3_noop_touch_offset : natural := ex3_dsi_offset + 16; +constant ex3_multihit_offset : natural := ex3_noop_touch_offset + 16; +constant ex3_multihit_b_pt_offset : natural := ex3_multihit_offset + thdid_width; +constant ex3_first_hit_entry_pt_offset : natural := ex3_multihit_b_pt_offset + num_entry; +constant ex3_parerr_offset : natural := ex3_first_hit_entry_pt_offset + num_entry-1; +constant ex3_attr_offset : natural := ex3_parerr_offset + thdid_width + 2; +constant ex3_tlbreq_offset : natural := ex3_attr_offset + 6; +constant ex3_hit_offset : natural := ex3_tlbreq_offset + 1; +constant ex3_cam_hit_offset : natural := ex3_hit_offset + 1; +constant ex2_debug_offset : natural := ex3_cam_hit_offset + 1; +constant ex3_debug_offset : natural := ex2_debug_offset + 11; +constant spare_a_offset : natural := ex3_debug_offset + 17; +constant scan_right_0 : natural := spare_a_offset + 16 -1; +constant erat_parerr_mac_offset : natural := 0; +constant ex4_rd_cam_data_offset : natural := erat_parerr_mac_offset + 1; +constant ex4_rd_array_data_offset : natural := ex4_rd_cam_data_offset + cam_data_width; +constant ex4_parerr_offset : natural := ex4_rd_array_data_offset + array_data_width; +constant ex4_fir_parerr_offset : natural := ex4_parerr_offset + thdid_width + 2; +constant ex4_fir_multihit_offset : natural := ex4_fir_parerr_offset + thdid_width + 3; +constant ex4_deen_offset : natural := ex4_fir_multihit_offset + thdid_width; +constant ex4_hit_offset : natural := ex4_deen_offset + num_entry_log2 + thdid_width; +constant ex5_deen_offset : natural := ex4_hit_offset + 1; +constant ex5_hit_offset : natural := ex5_deen_offset + num_entry_log2 + thdid_width; +constant ex6_deen_offset : natural := ex5_hit_offset + 1; +constant ex6_hit_offset : natural := ex6_deen_offset + num_entry_log2 + 1; +constant barrier_done_offset : natural := ex6_hit_offset + 1; +constant mmucr1_offset : natural := barrier_done_offset + thdid_width; +constant rpn_holdreg0_offset : natural := mmucr1_offset + 10; +constant rpn_holdreg1_offset : natural := rpn_holdreg0_offset + 64; +constant rpn_holdreg2_offset : natural := rpn_holdreg1_offset + 64; +constant rpn_holdreg3_offset : natural := rpn_holdreg2_offset + 64; +constant entry_valid_offset : natural := rpn_holdreg3_offset + 64; +constant entry_match_offset : natural := entry_valid_offset + 32; +constant watermark_offset : natural := entry_match_offset + 32; +constant mmucr1_b0_cpy_offset : natural := watermark_offset + watermark_width; +constant lru_rmt_vec_offset : natural := mmucr1_b0_cpy_offset + 1; +constant eptr_offset : natural := lru_rmt_vec_offset + lru_width+1; +constant lru_offset : natural := eptr_offset + eptr_width; +constant lru_update_event_offset : natural := lru_offset + lru_width; +constant lru_debug_offset : natural := lru_update_event_offset + 10; +constant snoop_val_offset : natural := lru_debug_offset + 41; +constant snoop_attr_offset : natural := snoop_val_offset + 3; +constant snoop_addr_offset : natural := snoop_attr_offset + 26; +constant ex2_epn_offset : natural := snoop_addr_offset + epn_width; +constant por_seq_offset : natural := ex2_epn_offset + ex2_epn_width; +constant pc_xu_init_reset_offset : natural := por_seq_offset + 3; +constant tlb_rel_val_offset : natural := pc_xu_init_reset_offset + 1; +constant tlb_rel_data_offset : natural := tlb_rel_val_offset + thdid_width + 1; +constant eplc_wr_offset : natural := tlb_rel_data_offset + 132; +constant epsc_wr_offset : natural := eplc_wr_offset + 2*thdid_width + 1; +constant ccr2_frat_paranoia_offset : natural := epsc_wr_offset + 2*thdid_width + 1; +constant ccr2_notlb_offset : natural := ccr2_frat_paranoia_offset + 12; +constant xucr4_mmu_mchk_offset : natural := ccr2_notlb_offset + 1; +constant mchk_flash_inv_offset : natural := xucr4_mmu_mchk_offset + 1; +constant clkg_ctl_override_offset : natural := mchk_flash_inv_offset + 4; +constant rf1_stg_act_offset : natural := clkg_ctl_override_offset + 1; +constant ex1_stg_act_offset : natural := rf1_stg_act_offset + 1; +constant ex2_stg_act_offset : natural := ex1_stg_act_offset + 1; +constant ex3_stg_act_offset : natural := ex2_stg_act_offset + 1; +constant ex4_stg_act_offset : natural := ex3_stg_act_offset + 1; +constant ex5_stg_act_offset : natural := ex4_stg_act_offset + 1; +constant ex6_stg_act_offset : natural := ex5_stg_act_offset + 1; +constant ex7_stg_act_offset : natural := ex6_stg_act_offset + 1; +constant tlb_rel_act_offset : natural := ex7_stg_act_offset + 1; +constant snoop_act_offset : natural := tlb_rel_act_offset + 1; +constant trace_bus_enable_offset : natural := snoop_act_offset + 1; +constant an_ac_grffence_en_dc_offset : natural := trace_bus_enable_offset + 1; +constant spare_b_offset : natural := an_ac_grffence_en_dc_offset + 1; +constant scan_right_1 : natural := spare_b_offset + 16 -1; +constant bcfg_offset : natural := 0; +constant boot_scan_right : natural := bcfg_offset + bcfg_width - 1; +signal rf1_valid_d, rf1_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal rf1_ttype_d, rf1_ttype_q : std_ulogic_vector(10 to 11); +signal ex1_valid_d : std_ulogic_vector(0 to thdid_width-1); +signal ex1_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal ex1_ttype_d : std_ulogic_vector(0 to ttype_width-1); +signal ex1_ttype_q : std_ulogic_vector(0 to ttype_width-1); +signal ex1_ws_d : std_ulogic_vector(0 to ws_width-1); +signal ex1_ws_q : std_ulogic_vector(0 to ws_width-1); +signal ex1_rs_is_d : std_ulogic_vector(0 to rs_is_width-1); +signal ex1_rs_is_q : std_ulogic_vector(0 to rs_is_width-1); +signal ex1_ra_entry_d : std_ulogic_vector(0 to ra_entry_width-1); +signal ex1_ra_entry_q : std_ulogic_vector(0 to ra_entry_width-1); +signal ex1_state_d : std_ulogic_vector(0 to state_width-1); +signal ex1_state_q : std_ulogic_vector(0 to state_width-1); +signal ex1_pid_d : std_ulogic_vector(0 to pid_width-1); +signal ex1_pid_q : std_ulogic_vector(0 to pid_width-1); +signal ex1_extclass_d : std_ulogic_vector(0 to extclass_width-1); +signal ex1_extclass_q : std_ulogic_vector(0 to extclass_width-1); +signal ex1_tlbsel_d : std_ulogic_vector(0 to tlbsel_width-1); +signal ex1_tlbsel_q : std_ulogic_vector(0 to tlbsel_width-1); +signal ex2_valid_d : std_ulogic_vector(0 to thdid_width-1); +signal ex2_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal ex2_ttype_d : std_ulogic_vector(0 to ttype_width-1); +signal ex2_ttype_q : std_ulogic_vector(0 to ttype_width-1); +signal ex2_ws_d : std_ulogic_vector(0 to ws_width-1); +signal ex2_ws_q : std_ulogic_vector(0 to ws_width-1); +signal ex2_rs_is_d : std_ulogic_vector(0 to rs_is_width-1); +signal ex2_rs_is_q : std_ulogic_vector(0 to rs_is_width-1); +signal ex2_ra_entry_d : std_ulogic_vector(0 to ra_entry_width-1); +signal ex2_ra_entry_q : std_ulogic_vector(0 to ra_entry_width-1); +signal ex2_state_d : std_ulogic_vector(0 to state_width-1); +signal ex2_state_q : std_ulogic_vector(0 to state_width-1); +signal ex2_pid_d : std_ulogic_vector(0 to pid_width-1); +signal ex2_pid_q : std_ulogic_vector(0 to pid_width-1); +signal ex2_extclass_d : std_ulogic_vector(0 to extclass_width-1); +signal ex2_extclass_q : std_ulogic_vector(0 to extclass_width-1); +signal ex2_tlbsel_d : std_ulogic_vector(0 to tlbsel_width-1); +signal ex2_tlbsel_q : std_ulogic_vector(0 to tlbsel_width-1); +signal ex3_valid_d : std_ulogic_vector(0 to thdid_width-1); +signal ex3_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal ex3_ttype_d : std_ulogic_vector(0 to ttype_width-1); +signal ex3_ttype_q : std_ulogic_vector(0 to ttype_width-1); +signal ex3_ws_d : std_ulogic_vector(0 to ws_width-1); +signal ex3_ws_q : std_ulogic_vector(0 to ws_width-1); +signal ex3_rs_is_d : std_ulogic_vector(0 to rs_is_width-1); +signal ex3_rs_is_q : std_ulogic_vector(0 to rs_is_width-1); +signal ex3_ra_entry_d : std_ulogic_vector(0 to ra_entry_width-1); +signal ex3_ra_entry_q : std_ulogic_vector(0 to ra_entry_width-1); +signal ex3_state_d : std_ulogic_vector(0 to state_width-1); +signal ex3_state_q : std_ulogic_vector(0 to state_width-1); +signal ex3_pid_d : std_ulogic_vector(0 to pid_width-1); +signal ex3_pid_q : std_ulogic_vector(0 to pid_width-1); +signal ex3_lpid_d : std_ulogic_vector(0 to lpid_width-1); +signal ex3_lpid_q : std_ulogic_vector(0 to lpid_width-1); +signal ex3_extclass_d : std_ulogic_vector(0 to extclass_width-1); +signal ex3_extclass_q : std_ulogic_vector(0 to extclass_width-1); +signal ex3_tlbsel_d : std_ulogic_vector(0 to tlbsel_width-1); +signal ex3_tlbsel_q : std_ulogic_vector(0 to tlbsel_width-1); +signal ex4_valid_d : std_ulogic_vector(0 to thdid_width-1); +signal ex4_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal ex4_ttype_d : std_ulogic_vector(0 to ttype_width-1); +signal ex4_ttype_q : std_ulogic_vector(0 to ttype_width-1); +signal ex4_ws_d : std_ulogic_vector(0 to ws_width-1); +signal ex4_ws_q : std_ulogic_vector(0 to ws_width-1); +signal ex4_rs_is_d : std_ulogic_vector(0 to rs_is_width-1); +signal ex4_rs_is_q : std_ulogic_vector(0 to rs_is_width-1); +signal ex4_ra_entry_d : std_ulogic_vector(0 to ra_entry_width-1); +signal ex4_ra_entry_q : std_ulogic_vector(0 to ra_entry_width-1); +signal ex4_state_d : std_ulogic_vector(0 to state_width-1); +signal ex4_state_q : std_ulogic_vector(0 to state_width-1); +signal ex4_pid_d : std_ulogic_vector(0 to pid_width-1); +signal ex4_pid_q : std_ulogic_vector(0 to pid_width-1); +signal ex4_extclass_d : std_ulogic_vector(0 to extclass_width-1); +signal ex4_extclass_q : std_ulogic_vector(0 to extclass_width-1); +signal ex4_tlbsel_d : std_ulogic_vector(0 to tlbsel_width-1); +signal ex4_tlbsel_q : std_ulogic_vector(0 to tlbsel_width-1); +signal ex5_valid_d, ex5_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal ex5_ttype_d, ex5_ttype_q : std_ulogic_vector(0 to ttype_width-1); +signal ex5_ws_d, ex5_ws_q : std_ulogic_vector(0 to ws_width-1); +signal ex5_rs_is_d, ex5_rs_is_q : std_ulogic_vector(0 to rs_is_width-1); +signal ex5_ra_entry_d, ex5_ra_entry_q : std_ulogic_vector(0 to ra_entry_width-1); +signal ex5_state_d, ex5_state_q : std_ulogic_vector(0 to state_width-1); +signal ex5_pid_d, ex5_pid_q : std_ulogic_vector(0 to pid_width-1); +signal ex5_extclass_d, ex5_extclass_q : std_ulogic_vector(0 to extclass_width-1); +signal ex5_tlbsel_d, ex5_tlbsel_q : std_ulogic_vector(0 to tlbsel_width-1); +signal ex6_valid_d, ex6_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal ex6_ttype_d, ex6_ttype_q : std_ulogic_vector(0 to ttype_width-1); +signal ex6_ws_d, ex6_ws_q : std_ulogic_vector(0 to ws_width-1); +signal ex6_rs_is_d, ex6_rs_is_q : std_ulogic_vector(0 to rs_is_width-1); +signal ex6_ra_entry_d, ex6_ra_entry_q : std_ulogic_vector(0 to ra_entry_width-1); +signal ex6_state_d, ex6_state_q : std_ulogic_vector(0 to state_width-1); +signal ex6_pid_d, ex6_pid_q : std_ulogic_vector(0 to pid_width-1); +signal ex6_extclass_d, ex6_extclass_q : std_ulogic_vector(0 to extclass_width-1); +signal ex6_tlbsel_d, ex6_tlbsel_q : std_ulogic_vector(0 to tlbsel_width-1); +signal ex7_valid_d, ex7_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal ex7_ttype_d, ex7_ttype_q : std_ulogic_vector(0 to ttype_width-1); +signal ex7_tlbsel_d, ex7_tlbsel_q : std_ulogic_vector(0 to tlbsel_width-1); +signal ex5_data_in_d, ex5_data_in_q : std_ulogic_vector(64-rs_data_width to 63); +signal ex6_data_in_d, ex6_data_in_q : std_ulogic_vector(64-rs_data_width to 63); +signal ex4_data_out_d, ex4_data_out_q : std_ulogic_vector(64-data_out_width to 63); +signal ex2_n_flush_req_d, ex2_n_flush_req_q : std_ulogic_vector(0 to thdid_width-1); +signal ex3_n_flush_req_d, ex3_n_flush_req_q : std_ulogic_vector(0 to thdid_width-1); +signal hold_req_d, hold_req_q : std_ulogic_vector(0 to thdid_width-1); +signal hold_req_reset_d, hold_req_reset_q : std_ulogic_vector(0 to thdid_width-1); +signal hold_req_pot_set_d, hold_req_pot_set_q : std_ulogic_vector(0 to thdid_width-1); +signal hold_req_por_d, hold_req_por_q : std_ulogic_vector(0 to thdid_width-1); +signal tlb_req_inprogress_d, tlb_req_inprogress_q : std_ulogic_vector(0 to thdid_width-1); +signal ex1_deratre, ex1_deratwe, ex1_deratsx : std_ulogic; +signal ex2_dsi_d, ex2_dsi_q : std_ulogic_vector(0 to 15); +signal ex2_noop_touch_d, ex2_noop_touch_q : std_ulogic_vector(0 to 15); +signal ex3_miss_d, ex3_miss_q : std_ulogic_vector(0 to thdid_width-1); +signal ex3_dsi_d, ex3_dsi_q : std_ulogic_vector(0 to 15); +signal ex3_noop_touch_d, ex3_noop_touch_q : std_ulogic_vector(0 to 15); +signal ex3_multihit_d, ex3_multihit_q : std_ulogic_vector(0 to thdid_width-1); +signal ex3_multihit_b_pt_d, ex3_multihit_b_pt_q : std_ulogic_vector(1 to num_entry); +signal ex3_first_hit_entry_pt_d, ex3_first_hit_entry_pt_q : std_ulogic_vector(1 to num_entry-1); +signal ex3_parerr_d, ex3_parerr_q : std_ulogic_vector(0 to thdid_width+1); +signal ex3_attr_d, ex3_attr_q : std_ulogic_vector(0 to 5); +signal ex3_tlbreq_d, ex3_tlbreq_q : std_ulogic; +signal ex3_hit_d, ex3_hit_q : std_ulogic; +signal ex3_cam_hit_q : std_ulogic; +signal ex2_debug_d, ex2_debug_q : std_ulogic_vector(0 to 10); +signal ex3_debug_d, ex3_debug_q : std_ulogic_vector(0 to 16); +signal ex3_cam_cmp_data_q : std_ulogic_vector(0 to cam_data_width-1); +signal ex3_array_cmp_data_q : std_ulogic_vector(0 to array_data_width-1); +signal ex4_rd_array_data_d, ex4_rd_array_data_q : std_ulogic_vector(0 to array_data_width-1); +signal ex4_rd_cam_data_d, ex4_rd_cam_data_q : std_ulogic_vector(0 to cam_data_width-1); +signal ex4_parerr_d, ex4_parerr_q : std_ulogic_vector(0 to thdid_width+1); +signal ex4_fir_parerr_d, ex4_fir_parerr_q : std_ulogic_vector(0 to thdid_width+2); +signal ex4_fir_multihit_d, ex4_fir_multihit_q : std_ulogic_vector(0 to thdid_width-1); +signal ex4_deen_d, ex4_deen_q : std_ulogic_vector(0 to thdid_width+num_entry_log2-1); +signal ex4_hit_d, ex4_hit_q : std_ulogic; +signal ex5_deen_d, ex5_deen_q : std_ulogic_vector(0 to thdid_width+num_entry_log2-1); +signal ex5_hit_d, ex5_hit_q : std_ulogic; +signal ex6_deen_d, ex6_deen_q : std_ulogic_vector(0 to num_entry_log2); +signal ex6_hit_d, ex6_hit_q : std_ulogic; +signal ex3_deratwe, ex4_deratwe, ex5_deratwe, ex6_deratwe, ex7_deratwe : std_ulogic; +signal ex6_deratwe_ws3 : std_ulogic; +signal barrier_done_d, barrier_done_q : std_ulogic_vector(0 to thdid_width-1); +signal mmucr1_d, mmucr1_q : std_ulogic_vector(0 to 9); +signal mmucr1_b0_cpy_d, mmucr1_b0_cpy_q : std_ulogic; +signal lru_rmt_vec_d, lru_rmt_vec_q : std_ulogic_vector(0 to lru_width); +signal ex3_dsi : std_ulogic_vector(0 to 7); +signal ex3_noop_touch : std_ulogic_vector(0 to 7); +signal por_seq_d, por_seq_q : std_ulogic_vector(0 to 2); +signal rpn_holdreg0_d, rpn_holdreg0_q : std_ulogic_vector(0 to 63); +signal rpn_holdreg1_d, rpn_holdreg1_q : std_ulogic_vector(0 to 63); +signal rpn_holdreg2_d, rpn_holdreg2_q : std_ulogic_vector(0 to 63); +signal rpn_holdreg3_d, rpn_holdreg3_q : std_ulogic_vector(0 to 63); +signal watermark_d, watermark_q : std_ulogic_vector(0 to watermark_width-1); +signal eptr_d, eptr_q : std_ulogic_vector(0 to eptr_width-1); +signal lru_d, lru_q : std_ulogic_vector(1 to lru_width); +signal lru_update_event_d, lru_update_event_q : std_ulogic_vector(0 to 9); +signal lru_debug_d, lru_debug_q : std_ulogic_vector(0 to 40); +signal snoop_val_d, snoop_val_q : std_ulogic_vector(0 to 2); +signal snoop_attr_d, snoop_attr_q : std_ulogic_vector(0 to 25); +signal snoop_addr_d, snoop_addr_q : std_ulogic_vector(52-epn_width to 51); +signal ex2_epn_d, ex2_epn_q : std_ulogic_vector(52-ex2_epn_width to 51); +signal pc_xu_init_reset_q : std_ulogic; +signal tlb_rel_val_d, tlb_rel_val_q : std_ulogic_vector(0 to 4); +signal tlb_rel_data_d, tlb_rel_data_q : std_ulogic_vector(0 to 131); +signal eplc_wr_d, eplc_wr_q : std_ulogic_vector(0 to 2*thdid_width); +signal epsc_wr_d, epsc_wr_q : std_ulogic_vector(0 to 2*thdid_width); +signal ccr2_frat_paranoia_d, ccr2_frat_paranoia_q : std_ulogic_vector(0 to 11); +signal ccr2_notlb_q, xucr4_mmu_mchk_q : std_ulogic; +signal mchk_flash_inv_d, mchk_flash_inv_q : std_ulogic_vector(0 to 3); +signal mchk_flash_inv_enab : std_ulogic; +signal bcfg_q, bcfg_q_b : std_ulogic_vector(0 to bcfg_width-1); +signal por_wr_cam_val : std_ulogic_vector(0 to 1); +signal por_wr_array_val : std_ulogic_vector(0 to 1); +signal por_wr_cam_data : std_ulogic_vector(0 to cam_data_width-1); +signal por_wr_array_data : std_ulogic_vector(0 to array_data_width-1); +signal por_wr_entry : std_ulogic_vector(0 to num_entry_log2-1); +signal por_hold_req : std_ulogic_vector(0 to thdid_width-1); +signal ex2_multihit_b : std_ulogic; +signal ex2_first_hit_entry : std_ulogic_vector(0 to num_entry_log2-1); +signal ex3_first_hit_entry : std_ulogic_vector(0 to num_entry_log2-1); +signal ex3_dsi_enab : std_ulogic; +signal ex3_noop_touch_enab : std_ulogic; +signal ex3_multihit_enab : std_ulogic; +signal ex3_parerr_enab : std_ulogic; +-- synopsys translate_off +-- synopsys translate_on +signal ex3_eratsx_data : std_ulogic_vector(0 to 2+num_entry_log2-1); +signal hold_req_set : std_ulogic_vector(0 to thdid_width-1); +signal hold_req : std_ulogic_vector(0 to thdid_width-1); +signal lru_way_encode : std_ulogic_vector(0 to num_entry_log2-1); +signal lru_rmt_vec : std_ulogic_vector(0 to lru_width); +signal lru_reset_vec, lru_set_vec : std_ulogic_vector(1 to lru_width); +signal lru_op_vec, lru_vp_vec : std_ulogic_vector(1 to lru_width); +signal lru_eff : std_ulogic_vector(1 to lru_width); +signal lru_watermark_mask : std_ulogic_vector(0 to lru_width); +signal entry_valid_watermarked : std_ulogic_vector(0 to lru_width); +signal eptr_p1 : std_ulogic_vector(0 to eptr_width-1); +signal xu_derat_rf1_is_icbtlslc : std_ulogic; +signal ex3_cmp_data_parerr_epn_mac : std_ulogic; +signal ex3_cmp_data_parerr_rpn_mac : std_ulogic; +signal ex3_cmp_data_parerr_epn : std_ulogic; +signal ex3_cmp_data_parerr_rpn : std_ulogic; +signal ex4_rd_data_calc_par : std_ulogic_vector(50 to 67); +signal ex4_rd_data_parerr_epn : std_ulogic; +signal ex4_rd_data_parerr_rpn : std_ulogic; +-- synopsys translate_off +-- synopsys translate_on +signal ex4_parerr_enab : std_ulogic; +signal ex4_fir_parerr_enab : std_ulogic; +signal rf1_mmucr0_gs, rf1_mmucr0_ts : std_ulogic; +signal rf1_eplc_epr, rf1_epsc_epr, rf1_eplc_egs, rf1_epsc_egs, rf1_eplc_eas, rf1_epsc_eas: std_ulogic; +signal rf1_pid, rf1_mmucr0_pid, rf1_eplc_epid, rf1_epsc_epid : std_ulogic_vector(0 to pid_width-1); +signal tlb_rel_cmpmask : std_ulogic_vector(0 to 3); +signal tlb_rel_xbitmask : std_ulogic_vector(0 to 3); +signal tlb_rel_maskpar : std_ulogic; +signal ex6_data_cmpmask : std_ulogic_vector(0 to 3); +signal ex6_data_xbitmask : std_ulogic_vector(0 to 3); +signal ex6_data_maskpar : std_ulogic; +signal rd_val : std_ulogic; +signal rw_entry : std_ulogic_vector(0 to 4); +signal wr_array_par : std_ulogic_vector(51 to 67); +signal wr_array_data_nopar : std_ulogic_vector(0 to array_data_width-1-10-7); +signal wr_array_data : std_ulogic_vector(0 to array_data_width-1); +signal wr_cam_data : std_ulogic_vector(0 to cam_data_width-1); +signal wr_array_val : std_ulogic_vector(0 to 1); +signal wr_cam_val : std_ulogic_vector(0 to 1); +signal wr_val_early : std_ulogic; +signal comp_request : std_ulogic; +signal comp_addr : std_ulogic_vector(0 to 51); +signal addr_enable : std_ulogic_vector(0 to 1); +signal comp_pgsize : std_ulogic_vector(0 to 2); +signal pgsize_enable : std_ulogic; +signal comp_class : std_ulogic_vector(0 to 1); +signal class_enable : std_ulogic_vector(0 to 2); +signal comp_extclass : std_ulogic_vector(0 to 1); +signal extclass_enable : std_ulogic_vector(0 to 1); +signal comp_state : std_ulogic_vector(0 to 1); +signal state_enable : std_ulogic_vector(0 to 1); +signal comp_thdid : std_ulogic_vector(0 to 3); +signal thdid_enable : std_ulogic_vector(0 to 1); +signal comp_pid : std_ulogic_vector(0 to 7); +signal pid_enable : std_ulogic; +signal comp_invalidate : std_ulogic; +signal flash_invalidate : std_ulogic; +signal array_cmp_data : std_ulogic_vector(0 to array_data_width-1); +signal rd_array_data : std_ulogic_vector(0 to array_data_width-1); +signal cam_cmp_data : std_ulogic_vector(0 to cam_data_width-1); +signal cam_hit : std_ulogic; +signal cam_hit_entry : std_ulogic_vector(0 to 4); +signal entry_match, entry_match_q : std_ulogic_vector(0 to 31); +signal entry_valid, entry_valid_q : std_ulogic_vector(0 to 31); +signal rd_cam_data : std_ulogic_vector(0 to cam_data_width-1); +-- synopsys translate_off +-- synopsys translate_on +signal cam_pgsize : std_ulogic_vector(0 to 2); +signal ws0_pgsize : std_ulogic_vector(0 to 3); +signal bypass_mux_enab_np1 : std_ulogic; +signal bypass_attr_np1 : std_ulogic_vector(0 to 20); +signal attr_np2 : std_ulogic_vector(0 to 20); +signal rpn_np2 : std_ulogic_vector(22 to 51); +signal pc_sg_1 : std_ulogic; +signal pc_sg_0 : std_ulogic; +signal pc_func_sl_thold_1 : std_ulogic; +signal pc_func_sl_thold_0 : std_ulogic; +signal pc_func_sl_thold_0_b : std_ulogic; +signal pc_func_slp_sl_thold_1 : std_ulogic; +signal pc_func_slp_sl_thold_0 : std_ulogic; +signal pc_func_slp_sl_thold_0_b : std_ulogic; +signal pc_func_sl_force : std_ulogic; +signal pc_func_slp_sl_force : std_ulogic; +signal pc_cfg_slp_sl_thold_1 : std_ulogic; +signal pc_cfg_slp_sl_thold_0 : std_ulogic; +signal pc_cfg_slp_sl_thold_0_b : std_ulogic; +signal pc_cfg_slp_sl_force : std_ulogic; +signal lcb_dclk : std_ulogic; +signal lcb_lclk : clk_logic; +signal init_alias : std_ulogic; +signal clkg_ctl_override_d :std_ulogic; +signal clkg_ctl_override_q :std_ulogic; +signal rf1_stg_act_d, rf1_stg_act_q :std_ulogic; +signal ex1_stg_act_d, ex1_stg_act_q :std_ulogic; +signal ex2_stg_act_d, ex2_stg_act_q :std_ulogic; +signal ex3_stg_act_d, ex3_stg_act_q :std_ulogic; +signal ex4_stg_act_d, ex4_stg_act_q :std_ulogic; +signal ex5_stg_act_d, ex5_stg_act_q :std_ulogic; +signal ex6_stg_act_d, ex6_stg_act_q :std_ulogic; +signal ex7_stg_act_d, ex7_stg_act_q :std_ulogic; +signal tlb_rel_act_d, tlb_rel_act_q, tlb_rel_act :std_ulogic; +signal an_ac_grffence_en_dc_q, trace_bus_enable_q :std_ulogic; +signal ex2_cmp_data_act, ex3_grffence_act, ex2_or_ex3_grffence_act, ex3_to_ex6_grffence_act :std_ulogic; +signal ex3_rd_data_act, ex3_data_out_act :std_ulogic; +signal entry_valid_act, entry_match_act :std_ulogic; +signal snoop_act_q, snoop_act :std_ulogic; +signal not_grffence_act, lru_update_act, notlb_grffence_act, debug_grffence_act :std_ulogic; +signal spare_a_q :std_ulogic_vector(0 to 15); +signal spare_b_q :std_ulogic_vector(0 to 15); +signal unused_dc : std_ulogic_vector(0 to 39); +-- synopsys translate_off +-- synopsys translate_on +signal siv_0 : std_ulogic_vector(0 to scan_right_0); +signal sov_0 : std_ulogic_vector(0 to scan_right_0); +signal siv_1 : std_ulogic_vector(0 to scan_right_1); +signal sov_1 : std_ulogic_vector(0 to scan_right_1); +signal bsiv : std_ulogic_vector(0 to boot_scan_right); +signal bsov : std_ulogic_vector(0 to boot_scan_right); +signal func_si_cam_int, func_so_cam_int : std_ulogic; +signal tiup : std_ulogic; + BEGIN + +clkg_ctl_override_d <= spr_xucr0_clkg_ctl_b1; +rf1_stg_act_d <= or_reduce(xu_derat_rf0_val) or clkg_ctl_override_q; +ex1_stg_act_d <= rf1_stg_act_q or xu_derat_rf1_act or xu_derat_rf1_ra_eq_ea; +ex2_stg_act_d <= ex1_stg_act_q; +ex3_stg_act_d <= ex2_stg_act_q; +ex4_stg_act_d <= ex3_stg_act_q; +ex5_stg_act_d <= ex4_stg_act_q; +ex6_stg_act_d <= ex5_stg_act_q; +ex7_stg_act_d <= ex6_stg_act_q; +ex2_cmp_data_act <= ex2_stg_act_q and not(an_ac_grffence_en_dc); +ex3_rd_data_act <= ex3_stg_act_q and not(an_ac_grffence_en_dc); +ex3_data_out_act <= ex3_stg_act_q and not(an_ac_grffence_en_dc); +ex3_grffence_act <= ex3_stg_act_q and not(an_ac_grffence_en_dc); +ex2_or_ex3_grffence_act <= (ex2_stg_act_q or ex3_stg_act_q) and not(an_ac_grffence_en_dc); +ex3_to_ex6_grffence_act <= (ex3_stg_act_q or ex4_stg_act_q or ex5_stg_act_q or ex6_stg_act_q) and not(an_ac_grffence_en_dc); +entry_valid_act <= not an_ac_grffence_en_dc; +entry_match_act <= not an_ac_grffence_en_dc; +not_grffence_act <= not an_ac_grffence_en_dc; +lru_update_act <= ex6_stg_act_q or ex7_stg_act_q or lru_update_event_q(8) or lru_update_event_q(9) or flash_invalidate or ex6_deratwe_ws3; +snoop_act <= snoop_act_q or clkg_ctl_override_q; +notlb_grffence_act <= (not(ccr2_notlb_q) or clkg_ctl_override_q) and not(an_ac_grffence_en_dc); +debug_grffence_act <= trace_bus_enable_q and not(an_ac_grffence_en_dc); +tiup <= '1'; +init_alias <= pc_xu_init_reset_q; +tlb_rel_val_d <= mm_xu_derat_rel_val; +tlb_rel_data_d <= mm_xu_derat_rel_data; +tlb_rel_act_d <= mm_xu_derat_rel_data(eratpos_relsoon); +tlb_rel_act <= (tlb_rel_act_q and not(ccr2_notlb_q)) or clkg_ctl_override_q; +ccr2_frat_paranoia_d(0 TO 8) <= xu_derat_spr_ccr2_dfratsc; +ccr2_frat_paranoia_d(9) <= xu_derat_spr_ccr2_dfrat; +ccr2_frat_paranoia_d(10) <= xu_derat_rf1_ra_eq_ea; +ccr2_frat_paranoia_d(11) <= ccr2_frat_paranoia_q(10); +xu_derat_rf1_is_icbtlslc <= xu_derat_rf1_icbtls_instr or xu_derat_rf1_icblc_instr; +rf1_valid_d <= xu_derat_rf0_val and not(xu_derat_rf0_n_flush); +rf1_ttype_d <= xu_derat_rf0_is_extload & xu_derat_rf0_is_extstore; +rf1_eplc_epr <= (xu_derat_eplc0_epr and rf1_valid_q(0)) or + (xu_derat_eplc1_epr and rf1_valid_q(1)) or + (xu_derat_eplc2_epr and rf1_valid_q(2)) or + (xu_derat_eplc3_epr and rf1_valid_q(3)); +rf1_epsc_epr <= (xu_derat_epsc0_epr and rf1_valid_q(0)) or + (xu_derat_epsc1_epr and rf1_valid_q(1)) or + (xu_derat_epsc2_epr and rf1_valid_q(2)) or + (xu_derat_epsc3_epr and rf1_valid_q(3)); +rf1_eplc_egs <= (xu_derat_eplc0_egs and rf1_valid_q(0)) or + (xu_derat_eplc1_egs and rf1_valid_q(1)) or + (xu_derat_eplc2_egs and rf1_valid_q(2)) or + (xu_derat_eplc3_egs and rf1_valid_q(3)); +rf1_epsc_egs <= (xu_derat_epsc0_egs and rf1_valid_q(0)) or + (xu_derat_epsc1_egs and rf1_valid_q(1)) or + (xu_derat_epsc2_egs and rf1_valid_q(2)) or + (xu_derat_epsc3_egs and rf1_valid_q(3)); +rf1_eplc_eas <= (xu_derat_eplc0_eas and rf1_valid_q(0)) or + (xu_derat_eplc1_eas and rf1_valid_q(1)) or + (xu_derat_eplc2_eas and rf1_valid_q(2)) or + (xu_derat_eplc3_eas and rf1_valid_q(3)); +rf1_epsc_eas <= (xu_derat_epsc0_eas and rf1_valid_q(0)) or + (xu_derat_epsc1_eas and rf1_valid_q(1)) or + (xu_derat_epsc2_eas and rf1_valid_q(2)) or + (xu_derat_epsc3_eas and rf1_valid_q(3)); +rf1_mmucr0_gs <= (mm_xu_derat_mmucr0_0(2) and rf1_valid_q(0)) or + (mm_xu_derat_mmucr0_1(2) and rf1_valid_q(1)) or + (mm_xu_derat_mmucr0_2(2) and rf1_valid_q(2)) or + (mm_xu_derat_mmucr0_3(2) and rf1_valid_q(3)); +rf1_mmucr0_ts <= (mm_xu_derat_mmucr0_0(3) and rf1_valid_q(0)) or + (mm_xu_derat_mmucr0_1(3) and rf1_valid_q(1)) or + (mm_xu_derat_mmucr0_2(3) and rf1_valid_q(2)) or + (mm_xu_derat_mmucr0_3(3) and rf1_valid_q(3)); +rf1_eplc_epid <= (xu_derat_eplc0_epid(50 to 63) and (0 to 13 => rf1_valid_q(0))) or + (xu_derat_eplc1_epid(50 to 63) and (0 to 13 => rf1_valid_q(1))) or + (xu_derat_eplc2_epid(50 to 63) and (0 to 13 => rf1_valid_q(2))) or + (xu_derat_eplc3_epid(50 to 63) and (0 to 13 => rf1_valid_q(3))); +rf1_epsc_epid <= (xu_derat_epsc0_epid(50 to 63) and (0 to 13 => rf1_valid_q(0))) or + (xu_derat_epsc1_epid(50 to 63) and (0 to 13 => rf1_valid_q(1))) or + (xu_derat_epsc2_epid(50 to 63) and (0 to 13 => rf1_valid_q(2))) or + (xu_derat_epsc3_epid(50 to 63) and (0 to 13 => rf1_valid_q(3))); +rf1_mmucr0_pid <= (mm_xu_derat_mmucr0_0(6 to 19) and (0 to 13 => rf1_valid_q(0))) or + (mm_xu_derat_mmucr0_1(6 to 19) and (0 to 13 => rf1_valid_q(1))) or + (mm_xu_derat_mmucr0_2(6 to 19) and (0 to 13 => rf1_valid_q(2))) or + (mm_xu_derat_mmucr0_3(6 to 19) and (0 to 13 => rf1_valid_q(3))); +rf1_pid <= (mm_xu_derat_pid0 and (0 to 13 => rf1_valid_q(0))) or + (mm_xu_derat_pid1 and (0 to 13 => rf1_valid_q(1))) or + (mm_xu_derat_pid2 and (0 to 13 => rf1_valid_q(2))) or + (mm_xu_derat_pid3 and (0 to 13 => rf1_valid_q(3))); +ex1_valid_d <= rf1_valid_q and not(xu_derat_rf1_n_flush); +ex1_ttype_d <= xu_derat_rf1_is_eratre & xu_derat_rf1_is_eratwe & xu_derat_rf1_is_eratsx & xu_derat_rf1_is_eratilx & + xu_derat_rf1_is_load & xu_derat_rf1_is_store & '0' & '0' & + xu_derat_rf1_is_icbtlslc & xu_derat_rf1_is_touch & rf1_ttype_q(10) & rf1_ttype_q(11); +ex1_ws_d <= xu_derat_rf1_ws; +ex1_rs_is_d <= (others => '0'); +ex1_ra_entry_d <= (others => '0'); +ex1_state_d(0) <= rf1_eplc_epr when rf1_ttype_q(10)='1' + else rf1_epsc_epr when rf1_ttype_q(11)='1' + else or_reduce(xu_derat_msr_pr and rf1_valid_q); +ex1_state_d(1) <= rf1_eplc_egs when rf1_ttype_q(10)='1' + else rf1_epsc_egs when rf1_ttype_q(11)='1' + else rf1_mmucr0_gs when xu_derat_rf1_is_eratsx='1' + else or_reduce(xu_derat_msr_hv and rf1_valid_q); +ex1_state_d(2) <= rf1_eplc_eas when rf1_ttype_q(10)='1' + else rf1_epsc_eas when rf1_ttype_q(11)='1' + else rf1_mmucr0_ts when xu_derat_rf1_is_eratsx='1' + else or_reduce(xu_derat_msr_ds and rf1_valid_q); +ex1_state_d(3) <= or_reduce(xu_derat_msr_cm and rf1_valid_q); +ex1_extclass_d <= mm_xu_derat_mmucr0_1(0 to 1) when rf1_valid_q(1)='1' + else mm_xu_derat_mmucr0_2(0 to 1) when rf1_valid_q(2)='1' + else mm_xu_derat_mmucr0_3(0 to 1) when rf1_valid_q(3)='1' + else mm_xu_derat_mmucr0_0(0 to 1); +ex1_tlbsel_d <= mm_xu_derat_mmucr0_1(4 to 5) when rf1_valid_q(1)='1' + else mm_xu_derat_mmucr0_2(4 to 5) when rf1_valid_q(2)='1' + else mm_xu_derat_mmucr0_3(4 to 5) when rf1_valid_q(3)='1' + else mm_xu_derat_mmucr0_0(4 to 5); +ex1_pid_d <= rf1_eplc_epid when rf1_ttype_q(10)='1' + else rf1_epsc_epid when rf1_ttype_q(11)='1' + else rf1_mmucr0_pid when xu_derat_rf1_is_eratsx='1' + else rf1_pid; +ex1_deratre <= or_reduce(ex1_valid_q) and ex1_ttype_q(0) and ex1_tlbsel_q(0) and ex1_tlbsel_q(1); +ex1_deratwe <= or_reduce(ex1_valid_q) and ex1_ttype_q(1) and ex1_tlbsel_q(0) and ex1_tlbsel_q(1); +ex1_deratsx <= or_reduce(ex1_valid_q) and ex1_ttype_q(2) and ex1_tlbsel_q(0) and ex1_tlbsel_q(1); +ex2_valid_d <= ex1_valid_q and not(xu_derat_ex1_n_flush); +ex2_ttype_d(0 TO ttype_width-7) <= ex1_ttype_q(0 to ttype_width-7); +ex2_ttype_d(ttype_width-6 TO ttype_width-5) <= xu_derat_ex1_is_csync & xu_derat_ex1_is_isync; +ex2_ttype_d(ttype_width-4 TO ttype_width-1) <= ex1_ttype_q(ttype_width-4 to ttype_width-1); +ex2_ws_d <= ex1_ws_q; +ex2_rs_is_d <= xu_derat_ex1_rs_is; +ex2_ra_entry_d <= xu_derat_ex1_ra_entry; +ex2_state_d <= ex1_state_q; +ex2_pid_d <= ex1_pid_q; +ex2_extclass_d <= ex1_extclass_q; +ex2_tlbsel_d <= ex1_tlbsel_q; +ex3_valid_d <= ex2_valid_q and not(xu_derat_ex2_n_flush); +ex3_ttype_d <= ex2_ttype_q; +ex3_ws_d <= ex2_ws_q; +ex3_rs_is_d <= ex2_rs_is_q; +ex3_ra_entry_d <= ex2_ra_entry_q; +ex3_tlbsel_d <= ex2_tlbsel_q; +ex3_extclass_d <= ex2_extclass_q; +ex3_state_d <= ex2_state_q; +ex3_pid_d <= ex2_pid_q; +ex3_lpid_d(0 TO lpid_width-1) <= + ( xu_derat_eplc0_elpid(40 to 47) and (40 to 47 => (ex2_valid_q(0) and ex2_ttype_q(10))) ) + or ( xu_derat_eplc1_elpid(40 to 47) and (40 to 47 => (ex2_valid_q(1) and ex2_ttype_q(10))) ) + or ( xu_derat_eplc2_elpid(40 to 47) and (40 to 47 => (ex2_valid_q(2) and ex2_ttype_q(10))) ) + or ( xu_derat_eplc3_elpid(40 to 47) and (40 to 47 => (ex2_valid_q(3) and ex2_ttype_q(10))) ) + or ( xu_derat_epsc0_elpid(40 to 47) and (40 to 47 => (ex2_valid_q(0) and ex2_ttype_q(11))) ) + or ( xu_derat_epsc1_elpid(40 to 47) and (40 to 47 => (ex2_valid_q(1) and ex2_ttype_q(11))) ) + or ( xu_derat_epsc2_elpid(40 to 47) and (40 to 47 => (ex2_valid_q(2) and ex2_ttype_q(11))) ) + or ( xu_derat_epsc3_elpid(40 to 47) and (40 to 47 => (ex2_valid_q(3) and ex2_ttype_q(11))) ); +ex3_deratwe <= or_reduce(ex3_valid_q) and ex3_ttype_q(1) and ex3_tlbsel_q(0) and ex3_tlbsel_q(1); +ex4_valid_d <= ex3_valid_q and not(xu_derat_ex3_n_flush) and not(ex3_n_flush_req_q) and not(ex3_miss_q); +ex4_ttype_d <= ex3_ttype_q; +ex4_ws_d <= ex3_ws_q; +ex4_rs_is_d <= ex3_rs_is_q; +ex4_ra_entry_d <= ex3_first_hit_entry when ex3_ttype_q(2 to 5)/="0000" else ex3_ra_entry_q; +ex4_tlbsel_d <= ex3_tlbsel_q; +ex4_extclass_d <= rd_cam_data(63 to 64) when (ex3_valid_q/="0000" and ex3_ttype_q(0)='1' and ex3_ws_q="00") + else ex3_extclass_q; +ex4_state_d <= ex3_state_q(0) & rd_cam_data(65 to 66) & ex3_state_q(3) when (ex3_valid_q/="0000" and ex3_ttype_q(0)='1' and ex3_ws_q="00") + else ex3_state_q; +ex4_pid_d <= rd_cam_data(61 to 62) & rd_cam_data(57 to 60) & rd_cam_data(67 to 74) + when (ex3_valid_q/="0000" and ex3_ttype_q(0)='1' and ex3_ws_q="00") + else ex3_pid_q; +ex4_deratwe <= or_reduce(ex4_valid_q) and ex4_ttype_q(1) and ex4_tlbsel_q(0) and ex4_tlbsel_q(1); +ex5_valid_d <= ex4_valid_q and not(xu_derat_ex4_n_flush); +ex5_ws_d <= ex4_ws_q; +ex5_rs_is_d <= ex4_rs_is_q; +ex5_ra_entry_d <= ex4_ra_entry_q; +ex5_ttype_d <= ex4_ttype_q; +ex5_extclass_d <= ex4_extclass_q; +ex5_state_d <= ex4_state_q; +ex5_pid_d <= ex4_pid_q; +ex5_tlbsel_d <= ex4_tlbsel_q; +ex5_data_in_d <= xu_derat_ex4_rs_data; +ex5_deratwe <= or_reduce(ex5_valid_q) and ex5_ttype_q(1) and ex5_tlbsel_q(0) and ex5_tlbsel_q(1); +ex6_valid_d <= ex5_valid_q and not(xu_derat_ex5_n_flush); +ex6_ws_d <= ex5_ws_q; +ex6_rs_is_d <= ex5_rs_is_q; +ex6_ra_entry_d <= ex5_ra_entry_q; +ex6_ttype_d(0 TO 5) <= ex5_ttype_q(0 to 5); +ex6_ttype_d(6) <= '1' when (ex5_ttype_q(6)='1' and mmucr1_q(3)='0' and ccr2_notlb_q=MMU_Mode_Value) + else '0'; +ex6_ttype_d(7) <= '1' when (ex5_ttype_q(7)='1' and mmucr1_q(4)='0' and ccr2_notlb_q=MMU_Mode_Value) + else '0'; +ex6_ttype_d(8 TO ttype_width-1) <= ex5_ttype_q(8 to ttype_width-1); +ex6_extclass_d <= mm_xu_derat_mmucr0_0(0 to 1) + when (ex5_valid_q="1000" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else mm_xu_derat_mmucr0_1(0 to 1) + when (ex5_valid_q="0100" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else mm_xu_derat_mmucr0_2(0 to 1) + when (ex5_valid_q="0010" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else mm_xu_derat_mmucr0_3(0 to 1) + when (ex5_valid_q="0001" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else ex5_extclass_q; +ex6_state_d <= xu_derat_msr_pr(0) & mm_xu_derat_mmucr0_0(2 to 3) & xu_derat_msr_cm(0) + when (ex5_valid_q="1000" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else xu_derat_msr_pr(1) & mm_xu_derat_mmucr0_1(2 to 3) & xu_derat_msr_cm(1) + when (ex5_valid_q="0100" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else xu_derat_msr_pr(2) & mm_xu_derat_mmucr0_2(2 to 3) & xu_derat_msr_cm(2) + when (ex5_valid_q="0010" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else xu_derat_msr_pr(3) & mm_xu_derat_mmucr0_3(2 to 3) & xu_derat_msr_cm(3) + when (ex5_valid_q="0001" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else ex5_state_q; +ex6_pid_d <= mm_xu_derat_mmucr0_0(6 to 19) + when (ex5_valid_q="1000" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else mm_xu_derat_mmucr0_1(6 to 19) + when (ex5_valid_q="0100" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else mm_xu_derat_mmucr0_2(6 to 19) + when (ex5_valid_q="0010" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else mm_xu_derat_mmucr0_3(6 to 19) + when (ex5_valid_q="0001" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else ex5_pid_q; +ex6_tlbsel_d <= mm_xu_derat_mmucr0_0(4 to 5) + when (ex5_valid_q="1000" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else mm_xu_derat_mmucr0_1(4 to 5) + when (ex5_valid_q="0100" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else mm_xu_derat_mmucr0_2(4 to 5) + when (ex5_valid_q="0010" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else mm_xu_derat_mmucr0_3(4 to 5) + when (ex5_valid_q="0001" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else ex5_tlbsel_q; +ex6_data_in_d <= ex5_data_in_q; +ex6_deratwe <= or_reduce(ex6_valid_q) and ex6_ttype_q(1) and ex6_tlbsel_q(0) and ex6_tlbsel_q(1); +ex7_valid_d <= ex6_valid_q; +ex7_ttype_d <= ex6_ttype_q; +ex7_tlbsel_d <= ex6_tlbsel_q; +ex7_deratwe <= or_reduce(ex7_valid_q) and ex7_ttype_q(1) and ex7_tlbsel_q(0) and ex7_tlbsel_q(1); +mmucr1_d <= mm_xu_derat_mmucr1; +MQQ1:EX2_MULTIHIT_B_PT(1) <= + Eq(( ENTRY_MATCH(1) & ENTRY_MATCH(2) & + ENTRY_MATCH(3) & ENTRY_MATCH(4) & + ENTRY_MATCH(5) & ENTRY_MATCH(6) & + ENTRY_MATCH(7) & ENTRY_MATCH(8) & + ENTRY_MATCH(9) & ENTRY_MATCH(10) & + ENTRY_MATCH(11) & ENTRY_MATCH(12) & + ENTRY_MATCH(13) & ENTRY_MATCH(14) & + ENTRY_MATCH(15) & ENTRY_MATCH(16) & + ENTRY_MATCH(17) & ENTRY_MATCH(18) & + ENTRY_MATCH(19) & ENTRY_MATCH(20) & + ENTRY_MATCH(21) & ENTRY_MATCH(22) & + ENTRY_MATCH(23) & ENTRY_MATCH(24) & + ENTRY_MATCH(25) & ENTRY_MATCH(26) & + ENTRY_MATCH(27) & ENTRY_MATCH(28) & + ENTRY_MATCH(29) & ENTRY_MATCH(30) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ2:EX2_MULTIHIT_B_PT(2) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(2) & + ENTRY_MATCH(3) & ENTRY_MATCH(4) & + ENTRY_MATCH(5) & ENTRY_MATCH(6) & + ENTRY_MATCH(7) & ENTRY_MATCH(8) & + ENTRY_MATCH(9) & ENTRY_MATCH(10) & + ENTRY_MATCH(11) & ENTRY_MATCH(12) & + ENTRY_MATCH(13) & ENTRY_MATCH(14) & + ENTRY_MATCH(15) & ENTRY_MATCH(16) & + ENTRY_MATCH(17) & ENTRY_MATCH(18) & + ENTRY_MATCH(19) & ENTRY_MATCH(20) & + ENTRY_MATCH(21) & ENTRY_MATCH(22) & + ENTRY_MATCH(23) & ENTRY_MATCH(24) & + ENTRY_MATCH(25) & ENTRY_MATCH(26) & + ENTRY_MATCH(27) & ENTRY_MATCH(28) & + ENTRY_MATCH(29) & ENTRY_MATCH(30) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ3:EX2_MULTIHIT_B_PT(3) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(3) & ENTRY_MATCH(4) & + ENTRY_MATCH(5) & ENTRY_MATCH(6) & + ENTRY_MATCH(7) & ENTRY_MATCH(8) & + ENTRY_MATCH(9) & ENTRY_MATCH(10) & + ENTRY_MATCH(11) & ENTRY_MATCH(12) & + ENTRY_MATCH(13) & ENTRY_MATCH(14) & + ENTRY_MATCH(15) & ENTRY_MATCH(16) & + ENTRY_MATCH(17) & ENTRY_MATCH(18) & + ENTRY_MATCH(19) & ENTRY_MATCH(20) & + ENTRY_MATCH(21) & ENTRY_MATCH(22) & + ENTRY_MATCH(23) & ENTRY_MATCH(24) & + ENTRY_MATCH(25) & ENTRY_MATCH(26) & + ENTRY_MATCH(27) & ENTRY_MATCH(28) & + ENTRY_MATCH(29) & ENTRY_MATCH(30) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ4:EX2_MULTIHIT_B_PT(4) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(4) & + ENTRY_MATCH(5) & ENTRY_MATCH(6) & + ENTRY_MATCH(7) & ENTRY_MATCH(8) & + ENTRY_MATCH(9) & ENTRY_MATCH(10) & + ENTRY_MATCH(11) & ENTRY_MATCH(12) & + ENTRY_MATCH(13) & ENTRY_MATCH(14) & + ENTRY_MATCH(15) & ENTRY_MATCH(16) & + ENTRY_MATCH(17) & ENTRY_MATCH(18) & + ENTRY_MATCH(19) & ENTRY_MATCH(20) & + ENTRY_MATCH(21) & ENTRY_MATCH(22) & + ENTRY_MATCH(23) & ENTRY_MATCH(24) & + ENTRY_MATCH(25) & ENTRY_MATCH(26) & + ENTRY_MATCH(27) & ENTRY_MATCH(28) & + ENTRY_MATCH(29) & ENTRY_MATCH(30) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ5:EX2_MULTIHIT_B_PT(5) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(5) & ENTRY_MATCH(6) & + ENTRY_MATCH(7) & ENTRY_MATCH(8) & + ENTRY_MATCH(9) & ENTRY_MATCH(10) & + ENTRY_MATCH(11) & ENTRY_MATCH(12) & + ENTRY_MATCH(13) & ENTRY_MATCH(14) & + ENTRY_MATCH(15) & ENTRY_MATCH(16) & + ENTRY_MATCH(17) & ENTRY_MATCH(18) & + ENTRY_MATCH(19) & ENTRY_MATCH(20) & + ENTRY_MATCH(21) & ENTRY_MATCH(22) & + ENTRY_MATCH(23) & ENTRY_MATCH(24) & + ENTRY_MATCH(25) & ENTRY_MATCH(26) & + ENTRY_MATCH(27) & ENTRY_MATCH(28) & + ENTRY_MATCH(29) & ENTRY_MATCH(30) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ6:EX2_MULTIHIT_B_PT(6) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(6) & + ENTRY_MATCH(7) & ENTRY_MATCH(8) & + ENTRY_MATCH(9) & ENTRY_MATCH(10) & + ENTRY_MATCH(11) & ENTRY_MATCH(12) & + ENTRY_MATCH(13) & ENTRY_MATCH(14) & + ENTRY_MATCH(15) & ENTRY_MATCH(16) & + ENTRY_MATCH(17) & ENTRY_MATCH(18) & + ENTRY_MATCH(19) & ENTRY_MATCH(20) & + ENTRY_MATCH(21) & ENTRY_MATCH(22) & + ENTRY_MATCH(23) & ENTRY_MATCH(24) & + ENTRY_MATCH(25) & ENTRY_MATCH(26) & + ENTRY_MATCH(27) & ENTRY_MATCH(28) & + ENTRY_MATCH(29) & ENTRY_MATCH(30) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ7:EX2_MULTIHIT_B_PT(7) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(7) & ENTRY_MATCH(8) & + ENTRY_MATCH(9) & ENTRY_MATCH(10) & + ENTRY_MATCH(11) & ENTRY_MATCH(12) & + ENTRY_MATCH(13) & ENTRY_MATCH(14) & + ENTRY_MATCH(15) & ENTRY_MATCH(16) & + ENTRY_MATCH(17) & ENTRY_MATCH(18) & + ENTRY_MATCH(19) & ENTRY_MATCH(20) & + ENTRY_MATCH(21) & ENTRY_MATCH(22) & + ENTRY_MATCH(23) & ENTRY_MATCH(24) & + ENTRY_MATCH(25) & ENTRY_MATCH(26) & + ENTRY_MATCH(27) & ENTRY_MATCH(28) & + ENTRY_MATCH(29) & ENTRY_MATCH(30) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ8:EX2_MULTIHIT_B_PT(8) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(8) & + ENTRY_MATCH(9) & ENTRY_MATCH(10) & + ENTRY_MATCH(11) & ENTRY_MATCH(12) & + ENTRY_MATCH(13) & ENTRY_MATCH(14) & + ENTRY_MATCH(15) & ENTRY_MATCH(16) & + ENTRY_MATCH(17) & ENTRY_MATCH(18) & + ENTRY_MATCH(19) & ENTRY_MATCH(20) & + ENTRY_MATCH(21) & ENTRY_MATCH(22) & + ENTRY_MATCH(23) & ENTRY_MATCH(24) & + ENTRY_MATCH(25) & ENTRY_MATCH(26) & + ENTRY_MATCH(27) & ENTRY_MATCH(28) & + ENTRY_MATCH(29) & ENTRY_MATCH(30) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ9:EX2_MULTIHIT_B_PT(9) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(9) & ENTRY_MATCH(10) & + ENTRY_MATCH(11) & ENTRY_MATCH(12) & + ENTRY_MATCH(13) & ENTRY_MATCH(14) & + ENTRY_MATCH(15) & ENTRY_MATCH(16) & + ENTRY_MATCH(17) & ENTRY_MATCH(18) & + ENTRY_MATCH(19) & ENTRY_MATCH(20) & + ENTRY_MATCH(21) & ENTRY_MATCH(22) & + ENTRY_MATCH(23) & ENTRY_MATCH(24) & + ENTRY_MATCH(25) & ENTRY_MATCH(26) & + ENTRY_MATCH(27) & ENTRY_MATCH(28) & + ENTRY_MATCH(29) & ENTRY_MATCH(30) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ10:EX2_MULTIHIT_B_PT(10) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(10) & + ENTRY_MATCH(11) & ENTRY_MATCH(12) & + ENTRY_MATCH(13) & ENTRY_MATCH(14) & + ENTRY_MATCH(15) & ENTRY_MATCH(16) & + ENTRY_MATCH(17) & ENTRY_MATCH(18) & + ENTRY_MATCH(19) & ENTRY_MATCH(20) & + ENTRY_MATCH(21) & ENTRY_MATCH(22) & + ENTRY_MATCH(23) & ENTRY_MATCH(24) & + ENTRY_MATCH(25) & ENTRY_MATCH(26) & + ENTRY_MATCH(27) & ENTRY_MATCH(28) & + ENTRY_MATCH(29) & ENTRY_MATCH(30) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ11:EX2_MULTIHIT_B_PT(11) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(11) & ENTRY_MATCH(12) & + ENTRY_MATCH(13) & ENTRY_MATCH(14) & + ENTRY_MATCH(15) & ENTRY_MATCH(16) & + ENTRY_MATCH(17) & ENTRY_MATCH(18) & + ENTRY_MATCH(19) & ENTRY_MATCH(20) & + ENTRY_MATCH(21) & ENTRY_MATCH(22) & + ENTRY_MATCH(23) & ENTRY_MATCH(24) & + ENTRY_MATCH(25) & ENTRY_MATCH(26) & + ENTRY_MATCH(27) & ENTRY_MATCH(28) & + ENTRY_MATCH(29) & ENTRY_MATCH(30) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ12:EX2_MULTIHIT_B_PT(12) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(12) & + ENTRY_MATCH(13) & ENTRY_MATCH(14) & + ENTRY_MATCH(15) & ENTRY_MATCH(16) & + ENTRY_MATCH(17) & ENTRY_MATCH(18) & + ENTRY_MATCH(19) & ENTRY_MATCH(20) & + ENTRY_MATCH(21) & ENTRY_MATCH(22) & + ENTRY_MATCH(23) & ENTRY_MATCH(24) & + ENTRY_MATCH(25) & ENTRY_MATCH(26) & + ENTRY_MATCH(27) & ENTRY_MATCH(28) & + ENTRY_MATCH(29) & ENTRY_MATCH(30) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ13:EX2_MULTIHIT_B_PT(13) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(13) & ENTRY_MATCH(14) & + ENTRY_MATCH(15) & ENTRY_MATCH(16) & + ENTRY_MATCH(17) & ENTRY_MATCH(18) & + ENTRY_MATCH(19) & ENTRY_MATCH(20) & + ENTRY_MATCH(21) & ENTRY_MATCH(22) & + ENTRY_MATCH(23) & ENTRY_MATCH(24) & + ENTRY_MATCH(25) & ENTRY_MATCH(26) & + ENTRY_MATCH(27) & ENTRY_MATCH(28) & + ENTRY_MATCH(29) & ENTRY_MATCH(30) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ14:EX2_MULTIHIT_B_PT(14) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(14) & + ENTRY_MATCH(15) & ENTRY_MATCH(16) & + ENTRY_MATCH(17) & ENTRY_MATCH(18) & + ENTRY_MATCH(19) & ENTRY_MATCH(20) & + ENTRY_MATCH(21) & ENTRY_MATCH(22) & + ENTRY_MATCH(23) & ENTRY_MATCH(24) & + ENTRY_MATCH(25) & ENTRY_MATCH(26) & + ENTRY_MATCH(27) & ENTRY_MATCH(28) & + ENTRY_MATCH(29) & ENTRY_MATCH(30) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ15:EX2_MULTIHIT_B_PT(15) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(15) & ENTRY_MATCH(16) & + ENTRY_MATCH(17) & ENTRY_MATCH(18) & + ENTRY_MATCH(19) & ENTRY_MATCH(20) & + ENTRY_MATCH(21) & ENTRY_MATCH(22) & + ENTRY_MATCH(23) & ENTRY_MATCH(24) & + ENTRY_MATCH(25) & ENTRY_MATCH(26) & + ENTRY_MATCH(27) & ENTRY_MATCH(28) & + ENTRY_MATCH(29) & ENTRY_MATCH(30) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ16:EX2_MULTIHIT_B_PT(16) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(16) & + ENTRY_MATCH(17) & ENTRY_MATCH(18) & + ENTRY_MATCH(19) & ENTRY_MATCH(20) & + ENTRY_MATCH(21) & ENTRY_MATCH(22) & + ENTRY_MATCH(23) & ENTRY_MATCH(24) & + ENTRY_MATCH(25) & ENTRY_MATCH(26) & + ENTRY_MATCH(27) & ENTRY_MATCH(28) & + ENTRY_MATCH(29) & ENTRY_MATCH(30) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ17:EX2_MULTIHIT_B_PT(17) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(17) & ENTRY_MATCH(18) & + ENTRY_MATCH(19) & ENTRY_MATCH(20) & + ENTRY_MATCH(21) & ENTRY_MATCH(22) & + ENTRY_MATCH(23) & ENTRY_MATCH(24) & + ENTRY_MATCH(25) & ENTRY_MATCH(26) & + ENTRY_MATCH(27) & ENTRY_MATCH(28) & + ENTRY_MATCH(29) & ENTRY_MATCH(30) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ18:EX2_MULTIHIT_B_PT(18) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) & ENTRY_MATCH(18) & + ENTRY_MATCH(19) & ENTRY_MATCH(20) & + ENTRY_MATCH(21) & ENTRY_MATCH(22) & + ENTRY_MATCH(23) & ENTRY_MATCH(24) & + ENTRY_MATCH(25) & ENTRY_MATCH(26) & + ENTRY_MATCH(27) & ENTRY_MATCH(28) & + ENTRY_MATCH(29) & ENTRY_MATCH(30) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ19:EX2_MULTIHIT_B_PT(19) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) & ENTRY_MATCH(17) & + ENTRY_MATCH(19) & ENTRY_MATCH(20) & + ENTRY_MATCH(21) & ENTRY_MATCH(22) & + ENTRY_MATCH(23) & ENTRY_MATCH(24) & + ENTRY_MATCH(25) & ENTRY_MATCH(26) & + ENTRY_MATCH(27) & ENTRY_MATCH(28) & + ENTRY_MATCH(29) & ENTRY_MATCH(30) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ20:EX2_MULTIHIT_B_PT(20) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) & ENTRY_MATCH(17) & + ENTRY_MATCH(18) & ENTRY_MATCH(20) & + ENTRY_MATCH(21) & ENTRY_MATCH(22) & + ENTRY_MATCH(23) & ENTRY_MATCH(24) & + ENTRY_MATCH(25) & ENTRY_MATCH(26) & + ENTRY_MATCH(27) & ENTRY_MATCH(28) & + ENTRY_MATCH(29) & ENTRY_MATCH(30) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ21:EX2_MULTIHIT_B_PT(21) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) & ENTRY_MATCH(17) & + ENTRY_MATCH(18) & ENTRY_MATCH(19) & + ENTRY_MATCH(21) & ENTRY_MATCH(22) & + ENTRY_MATCH(23) & ENTRY_MATCH(24) & + ENTRY_MATCH(25) & ENTRY_MATCH(26) & + ENTRY_MATCH(27) & ENTRY_MATCH(28) & + ENTRY_MATCH(29) & ENTRY_MATCH(30) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ22:EX2_MULTIHIT_B_PT(22) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) & ENTRY_MATCH(17) & + ENTRY_MATCH(18) & ENTRY_MATCH(19) & + ENTRY_MATCH(20) & ENTRY_MATCH(22) & + ENTRY_MATCH(23) & ENTRY_MATCH(24) & + ENTRY_MATCH(25) & ENTRY_MATCH(26) & + ENTRY_MATCH(27) & ENTRY_MATCH(28) & + ENTRY_MATCH(29) & ENTRY_MATCH(30) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ23:EX2_MULTIHIT_B_PT(23) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) & ENTRY_MATCH(17) & + ENTRY_MATCH(18) & ENTRY_MATCH(19) & + ENTRY_MATCH(20) & ENTRY_MATCH(21) & + ENTRY_MATCH(23) & ENTRY_MATCH(24) & + ENTRY_MATCH(25) & ENTRY_MATCH(26) & + ENTRY_MATCH(27) & ENTRY_MATCH(28) & + ENTRY_MATCH(29) & ENTRY_MATCH(30) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ24:EX2_MULTIHIT_B_PT(24) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) & ENTRY_MATCH(17) & + ENTRY_MATCH(18) & ENTRY_MATCH(19) & + ENTRY_MATCH(20) & ENTRY_MATCH(21) & + ENTRY_MATCH(22) & ENTRY_MATCH(24) & + ENTRY_MATCH(25) & ENTRY_MATCH(26) & + ENTRY_MATCH(27) & ENTRY_MATCH(28) & + ENTRY_MATCH(29) & ENTRY_MATCH(30) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ25:EX2_MULTIHIT_B_PT(25) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) & ENTRY_MATCH(17) & + ENTRY_MATCH(18) & ENTRY_MATCH(19) & + ENTRY_MATCH(20) & ENTRY_MATCH(21) & + ENTRY_MATCH(22) & ENTRY_MATCH(23) & + ENTRY_MATCH(25) & ENTRY_MATCH(26) & + ENTRY_MATCH(27) & ENTRY_MATCH(28) & + ENTRY_MATCH(29) & ENTRY_MATCH(30) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ26:EX2_MULTIHIT_B_PT(26) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) & ENTRY_MATCH(17) & + ENTRY_MATCH(18) & ENTRY_MATCH(19) & + ENTRY_MATCH(20) & ENTRY_MATCH(21) & + ENTRY_MATCH(22) & ENTRY_MATCH(23) & + ENTRY_MATCH(24) & ENTRY_MATCH(26) & + ENTRY_MATCH(27) & ENTRY_MATCH(28) & + ENTRY_MATCH(29) & ENTRY_MATCH(30) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ27:EX2_MULTIHIT_B_PT(27) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) & ENTRY_MATCH(17) & + ENTRY_MATCH(18) & ENTRY_MATCH(19) & + ENTRY_MATCH(20) & ENTRY_MATCH(21) & + ENTRY_MATCH(22) & ENTRY_MATCH(23) & + ENTRY_MATCH(24) & ENTRY_MATCH(25) & + ENTRY_MATCH(27) & ENTRY_MATCH(28) & + ENTRY_MATCH(29) & ENTRY_MATCH(30) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ28:EX2_MULTIHIT_B_PT(28) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) & ENTRY_MATCH(17) & + ENTRY_MATCH(18) & ENTRY_MATCH(19) & + ENTRY_MATCH(20) & ENTRY_MATCH(21) & + ENTRY_MATCH(22) & ENTRY_MATCH(23) & + ENTRY_MATCH(24) & ENTRY_MATCH(25) & + ENTRY_MATCH(26) & ENTRY_MATCH(28) & + ENTRY_MATCH(29) & ENTRY_MATCH(30) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ29:EX2_MULTIHIT_B_PT(29) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) & ENTRY_MATCH(17) & + ENTRY_MATCH(18) & ENTRY_MATCH(19) & + ENTRY_MATCH(20) & ENTRY_MATCH(21) & + ENTRY_MATCH(22) & ENTRY_MATCH(23) & + ENTRY_MATCH(24) & ENTRY_MATCH(25) & + ENTRY_MATCH(26) & ENTRY_MATCH(27) & + ENTRY_MATCH(29) & ENTRY_MATCH(30) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ30:EX2_MULTIHIT_B_PT(30) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) & ENTRY_MATCH(17) & + ENTRY_MATCH(18) & ENTRY_MATCH(19) & + ENTRY_MATCH(20) & ENTRY_MATCH(21) & + ENTRY_MATCH(22) & ENTRY_MATCH(23) & + ENTRY_MATCH(24) & ENTRY_MATCH(25) & + ENTRY_MATCH(26) & ENTRY_MATCH(27) & + ENTRY_MATCH(28) & ENTRY_MATCH(30) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ31:EX2_MULTIHIT_B_PT(31) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) & ENTRY_MATCH(17) & + ENTRY_MATCH(18) & ENTRY_MATCH(19) & + ENTRY_MATCH(20) & ENTRY_MATCH(21) & + ENTRY_MATCH(22) & ENTRY_MATCH(23) & + ENTRY_MATCH(24) & ENTRY_MATCH(25) & + ENTRY_MATCH(26) & ENTRY_MATCH(27) & + ENTRY_MATCH(28) & ENTRY_MATCH(29) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ32:EX2_MULTIHIT_B_PT(32) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) & ENTRY_MATCH(17) & + ENTRY_MATCH(18) & ENTRY_MATCH(19) & + ENTRY_MATCH(20) & ENTRY_MATCH(21) & + ENTRY_MATCH(22) & ENTRY_MATCH(23) & + ENTRY_MATCH(24) & ENTRY_MATCH(25) & + ENTRY_MATCH(26) & ENTRY_MATCH(27) & + ENTRY_MATCH(28) & ENTRY_MATCH(29) & + ENTRY_MATCH(30) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ33:EX2_MULTIHIT_B <= + (EX2_MULTIHIT_B_PT(1) OR EX2_MULTIHIT_B_PT(2) + OR EX2_MULTIHIT_B_PT(3) OR EX2_MULTIHIT_B_PT(4) + OR EX2_MULTIHIT_B_PT(5) OR EX2_MULTIHIT_B_PT(6) + OR EX2_MULTIHIT_B_PT(7) OR EX2_MULTIHIT_B_PT(8) + OR EX2_MULTIHIT_B_PT(9) OR EX2_MULTIHIT_B_PT(10) + OR EX2_MULTIHIT_B_PT(11) OR EX2_MULTIHIT_B_PT(12) + OR EX2_MULTIHIT_B_PT(13) OR EX2_MULTIHIT_B_PT(14) + OR EX2_MULTIHIT_B_PT(15) OR EX2_MULTIHIT_B_PT(16) + OR EX2_MULTIHIT_B_PT(17) OR EX2_MULTIHIT_B_PT(18) + OR EX2_MULTIHIT_B_PT(19) OR EX2_MULTIHIT_B_PT(20) + OR EX2_MULTIHIT_B_PT(21) OR EX2_MULTIHIT_B_PT(22) + OR EX2_MULTIHIT_B_PT(23) OR EX2_MULTIHIT_B_PT(24) + OR EX2_MULTIHIT_B_PT(25) OR EX2_MULTIHIT_B_PT(26) + OR EX2_MULTIHIT_B_PT(27) OR EX2_MULTIHIT_B_PT(28) + OR EX2_MULTIHIT_B_PT(29) OR EX2_MULTIHIT_B_PT(30) + OR EX2_MULTIHIT_B_PT(31) OR EX2_MULTIHIT_B_PT(32) + ); + +ex3_multihit_b_pt_d <= ex2_multihit_b_pt; +ex3_multihit_enab <= not or_reduce(ex3_multihit_b_pt_q); +MQQ34:EX2_FIRST_HIT_ENTRY_PT(1) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) & ENTRY_MATCH(17) & + ENTRY_MATCH(18) & ENTRY_MATCH(19) & + ENTRY_MATCH(20) & ENTRY_MATCH(21) & + ENTRY_MATCH(22) & ENTRY_MATCH(23) & + ENTRY_MATCH(24) & ENTRY_MATCH(25) & + ENTRY_MATCH(26) & ENTRY_MATCH(27) & + ENTRY_MATCH(28) & ENTRY_MATCH(29) & + ENTRY_MATCH(30) & ENTRY_MATCH(31) + ) , STD_ULOGIC_VECTOR'("00000000000000000000000000000001")); +MQQ35:EX2_FIRST_HIT_ENTRY_PT(2) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) & ENTRY_MATCH(17) & + ENTRY_MATCH(18) & ENTRY_MATCH(19) & + ENTRY_MATCH(20) & ENTRY_MATCH(21) & + ENTRY_MATCH(22) & ENTRY_MATCH(23) & + ENTRY_MATCH(24) & ENTRY_MATCH(25) & + ENTRY_MATCH(26) & ENTRY_MATCH(27) & + ENTRY_MATCH(28) & ENTRY_MATCH(29) & + ENTRY_MATCH(30) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000001")); +MQQ36:EX2_FIRST_HIT_ENTRY_PT(3) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) & ENTRY_MATCH(17) & + ENTRY_MATCH(18) & ENTRY_MATCH(19) & + ENTRY_MATCH(20) & ENTRY_MATCH(21) & + ENTRY_MATCH(22) & ENTRY_MATCH(23) & + ENTRY_MATCH(24) & ENTRY_MATCH(25) & + ENTRY_MATCH(26) & ENTRY_MATCH(27) & + ENTRY_MATCH(28) & ENTRY_MATCH(29) + ) , STD_ULOGIC_VECTOR'("000000000000000000000000000001")); +MQQ37:EX2_FIRST_HIT_ENTRY_PT(4) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) & ENTRY_MATCH(17) & + ENTRY_MATCH(18) & ENTRY_MATCH(19) & + ENTRY_MATCH(20) & ENTRY_MATCH(21) & + ENTRY_MATCH(22) & ENTRY_MATCH(23) & + ENTRY_MATCH(24) & ENTRY_MATCH(25) & + ENTRY_MATCH(26) & ENTRY_MATCH(27) & + ENTRY_MATCH(28) ) , STD_ULOGIC_VECTOR'("00000000000000000000000000001")); +MQQ38:EX2_FIRST_HIT_ENTRY_PT(5) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) & ENTRY_MATCH(17) & + ENTRY_MATCH(18) & ENTRY_MATCH(19) & + ENTRY_MATCH(20) & ENTRY_MATCH(21) & + ENTRY_MATCH(22) & ENTRY_MATCH(23) & + ENTRY_MATCH(24) & ENTRY_MATCH(25) & + ENTRY_MATCH(26) & ENTRY_MATCH(27) + ) , STD_ULOGIC_VECTOR'("0000000000000000000000000001")); +MQQ39:EX2_FIRST_HIT_ENTRY_PT(6) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) & ENTRY_MATCH(17) & + ENTRY_MATCH(18) & ENTRY_MATCH(19) & + ENTRY_MATCH(20) & ENTRY_MATCH(21) & + ENTRY_MATCH(22) & ENTRY_MATCH(23) & + ENTRY_MATCH(24) & ENTRY_MATCH(25) & + ENTRY_MATCH(26) ) , STD_ULOGIC_VECTOR'("000000000000000000000000001")); +MQQ40:EX2_FIRST_HIT_ENTRY_PT(7) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) & ENTRY_MATCH(17) & + ENTRY_MATCH(18) & ENTRY_MATCH(19) & + ENTRY_MATCH(20) & ENTRY_MATCH(21) & + ENTRY_MATCH(22) & ENTRY_MATCH(23) & + ENTRY_MATCH(24) & ENTRY_MATCH(25) + ) , STD_ULOGIC_VECTOR'("00000000000000000000000001")); +MQQ41:EX2_FIRST_HIT_ENTRY_PT(8) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) & ENTRY_MATCH(17) & + ENTRY_MATCH(18) & ENTRY_MATCH(19) & + ENTRY_MATCH(20) & ENTRY_MATCH(21) & + ENTRY_MATCH(22) & ENTRY_MATCH(23) & + ENTRY_MATCH(24) ) , STD_ULOGIC_VECTOR'("0000000000000000000000001")); +MQQ42:EX2_FIRST_HIT_ENTRY_PT(9) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) & ENTRY_MATCH(17) & + ENTRY_MATCH(18) & ENTRY_MATCH(19) & + ENTRY_MATCH(20) & ENTRY_MATCH(21) & + ENTRY_MATCH(22) & ENTRY_MATCH(23) + ) , STD_ULOGIC_VECTOR'("000000000000000000000001")); +MQQ43:EX2_FIRST_HIT_ENTRY_PT(10) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) & ENTRY_MATCH(17) & + ENTRY_MATCH(18) & ENTRY_MATCH(19) & + ENTRY_MATCH(20) & ENTRY_MATCH(21) & + ENTRY_MATCH(22) ) , STD_ULOGIC_VECTOR'("00000000000000000000001")); +MQQ44:EX2_FIRST_HIT_ENTRY_PT(11) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) & ENTRY_MATCH(17) & + ENTRY_MATCH(18) & ENTRY_MATCH(19) & + ENTRY_MATCH(20) & ENTRY_MATCH(21) + ) , STD_ULOGIC_VECTOR'("0000000000000000000001")); +MQQ45:EX2_FIRST_HIT_ENTRY_PT(12) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) & ENTRY_MATCH(17) & + ENTRY_MATCH(18) & ENTRY_MATCH(19) & + ENTRY_MATCH(20) ) , STD_ULOGIC_VECTOR'("000000000000000000001")); +MQQ46:EX2_FIRST_HIT_ENTRY_PT(13) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) & ENTRY_MATCH(17) & + ENTRY_MATCH(18) & ENTRY_MATCH(19) + ) , STD_ULOGIC_VECTOR'("00000000000000000001")); +MQQ47:EX2_FIRST_HIT_ENTRY_PT(14) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) & ENTRY_MATCH(17) & + ENTRY_MATCH(18) ) , STD_ULOGIC_VECTOR'("0000000000000000001")); +MQQ48:EX2_FIRST_HIT_ENTRY_PT(15) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) & ENTRY_MATCH(17) + ) , STD_ULOGIC_VECTOR'("000000000000000001")); +MQQ49:EX2_FIRST_HIT_ENTRY_PT(16) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) ) , STD_ULOGIC_VECTOR'("00000000000000001")); +MQQ50:EX2_FIRST_HIT_ENTRY_PT(17) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) + ) , STD_ULOGIC_VECTOR'("0000000000000001")); +MQQ51:EX2_FIRST_HIT_ENTRY_PT(18) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) ) , STD_ULOGIC_VECTOR'("000000000000001")); +MQQ52:EX2_FIRST_HIT_ENTRY_PT(19) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) + ) , STD_ULOGIC_VECTOR'("00000000000001")); +MQQ53:EX2_FIRST_HIT_ENTRY_PT(20) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) ) , STD_ULOGIC_VECTOR'("0000000000001")); +MQQ54:EX2_FIRST_HIT_ENTRY_PT(21) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) + ) , STD_ULOGIC_VECTOR'("000000000001")); +MQQ55:EX2_FIRST_HIT_ENTRY_PT(22) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) ) , STD_ULOGIC_VECTOR'("00000000001")); +MQQ56:EX2_FIRST_HIT_ENTRY_PT(23) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) + ) , STD_ULOGIC_VECTOR'("0000000001")); +MQQ57:EX2_FIRST_HIT_ENTRY_PT(24) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) ) , STD_ULOGIC_VECTOR'("000000001")); +MQQ58:EX2_FIRST_HIT_ENTRY_PT(25) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) + ) , STD_ULOGIC_VECTOR'("00000001")); +MQQ59:EX2_FIRST_HIT_ENTRY_PT(26) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) ) , STD_ULOGIC_VECTOR'("0000001")); +MQQ60:EX2_FIRST_HIT_ENTRY_PT(27) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) + ) , STD_ULOGIC_VECTOR'("000001")); +MQQ61:EX2_FIRST_HIT_ENTRY_PT(28) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) ) , STD_ULOGIC_VECTOR'("00001")); +MQQ62:EX2_FIRST_HIT_ENTRY_PT(29) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) + ) , STD_ULOGIC_VECTOR'("0001")); +MQQ63:EX2_FIRST_HIT_ENTRY_PT(30) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) ) , STD_ULOGIC_VECTOR'("001")); +MQQ64:EX2_FIRST_HIT_ENTRY_PT(31) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) + ) , STD_ULOGIC_VECTOR'("01")); +MQQ65:EX2_FIRST_HIT_ENTRY(0) <= + (EX2_FIRST_HIT_ENTRY_PT(1) OR EX2_FIRST_HIT_ENTRY_PT(2) + OR EX2_FIRST_HIT_ENTRY_PT(3) OR EX2_FIRST_HIT_ENTRY_PT(4) + OR EX2_FIRST_HIT_ENTRY_PT(5) OR EX2_FIRST_HIT_ENTRY_PT(6) + OR EX2_FIRST_HIT_ENTRY_PT(7) OR EX2_FIRST_HIT_ENTRY_PT(8) + OR EX2_FIRST_HIT_ENTRY_PT(9) OR EX2_FIRST_HIT_ENTRY_PT(10) + OR EX2_FIRST_HIT_ENTRY_PT(11) OR EX2_FIRST_HIT_ENTRY_PT(12) + OR EX2_FIRST_HIT_ENTRY_PT(13) OR EX2_FIRST_HIT_ENTRY_PT(14) + OR EX2_FIRST_HIT_ENTRY_PT(15) OR EX2_FIRST_HIT_ENTRY_PT(16) + ); +MQQ66:EX2_FIRST_HIT_ENTRY(1) <= + (EX2_FIRST_HIT_ENTRY_PT(1) OR EX2_FIRST_HIT_ENTRY_PT(2) + OR EX2_FIRST_HIT_ENTRY_PT(3) OR EX2_FIRST_HIT_ENTRY_PT(4) + OR EX2_FIRST_HIT_ENTRY_PT(5) OR EX2_FIRST_HIT_ENTRY_PT(6) + OR EX2_FIRST_HIT_ENTRY_PT(7) OR EX2_FIRST_HIT_ENTRY_PT(8) + OR EX2_FIRST_HIT_ENTRY_PT(17) OR EX2_FIRST_HIT_ENTRY_PT(18) + OR EX2_FIRST_HIT_ENTRY_PT(19) OR EX2_FIRST_HIT_ENTRY_PT(20) + OR EX2_FIRST_HIT_ENTRY_PT(21) OR EX2_FIRST_HIT_ENTRY_PT(22) + OR EX2_FIRST_HIT_ENTRY_PT(23) OR EX2_FIRST_HIT_ENTRY_PT(24) + ); +MQQ67:EX2_FIRST_HIT_ENTRY(2) <= + (EX2_FIRST_HIT_ENTRY_PT(1) OR EX2_FIRST_HIT_ENTRY_PT(2) + OR EX2_FIRST_HIT_ENTRY_PT(3) OR EX2_FIRST_HIT_ENTRY_PT(4) + OR EX2_FIRST_HIT_ENTRY_PT(9) OR EX2_FIRST_HIT_ENTRY_PT(10) + OR EX2_FIRST_HIT_ENTRY_PT(11) OR EX2_FIRST_HIT_ENTRY_PT(12) + OR EX2_FIRST_HIT_ENTRY_PT(17) OR EX2_FIRST_HIT_ENTRY_PT(18) + OR EX2_FIRST_HIT_ENTRY_PT(19) OR EX2_FIRST_HIT_ENTRY_PT(20) + OR EX2_FIRST_HIT_ENTRY_PT(25) OR EX2_FIRST_HIT_ENTRY_PT(26) + OR EX2_FIRST_HIT_ENTRY_PT(27) OR EX2_FIRST_HIT_ENTRY_PT(28) + ); +MQQ68:EX2_FIRST_HIT_ENTRY(3) <= + (EX2_FIRST_HIT_ENTRY_PT(1) OR EX2_FIRST_HIT_ENTRY_PT(2) + OR EX2_FIRST_HIT_ENTRY_PT(5) OR EX2_FIRST_HIT_ENTRY_PT(6) + OR EX2_FIRST_HIT_ENTRY_PT(9) OR EX2_FIRST_HIT_ENTRY_PT(10) + OR EX2_FIRST_HIT_ENTRY_PT(13) OR EX2_FIRST_HIT_ENTRY_PT(14) + OR EX2_FIRST_HIT_ENTRY_PT(17) OR EX2_FIRST_HIT_ENTRY_PT(18) + OR EX2_FIRST_HIT_ENTRY_PT(21) OR EX2_FIRST_HIT_ENTRY_PT(22) + OR EX2_FIRST_HIT_ENTRY_PT(25) OR EX2_FIRST_HIT_ENTRY_PT(26) + OR EX2_FIRST_HIT_ENTRY_PT(29) OR EX2_FIRST_HIT_ENTRY_PT(30) + ); +MQQ69:EX2_FIRST_HIT_ENTRY(4) <= + (EX2_FIRST_HIT_ENTRY_PT(1) OR EX2_FIRST_HIT_ENTRY_PT(3) + OR EX2_FIRST_HIT_ENTRY_PT(5) OR EX2_FIRST_HIT_ENTRY_PT(7) + OR EX2_FIRST_HIT_ENTRY_PT(9) OR EX2_FIRST_HIT_ENTRY_PT(11) + OR EX2_FIRST_HIT_ENTRY_PT(13) OR EX2_FIRST_HIT_ENTRY_PT(15) + OR EX2_FIRST_HIT_ENTRY_PT(17) OR EX2_FIRST_HIT_ENTRY_PT(19) + OR EX2_FIRST_HIT_ENTRY_PT(21) OR EX2_FIRST_HIT_ENTRY_PT(23) + OR EX2_FIRST_HIT_ENTRY_PT(25) OR EX2_FIRST_HIT_ENTRY_PT(27) + OR EX2_FIRST_HIT_ENTRY_PT(29) OR EX2_FIRST_HIT_ENTRY_PT(31) + ); + +ex3_first_hit_entry_pt_d <= ex2_first_hit_entry_pt; +ex3_first_hit_entry(0) <= + (ex3_first_hit_entry_pt_q(1) or ex3_first_hit_entry_pt_q(2) + or ex3_first_hit_entry_pt_q(3) or ex3_first_hit_entry_pt_q(4) + or ex3_first_hit_entry_pt_q(5) or ex3_first_hit_entry_pt_q(6) + or ex3_first_hit_entry_pt_q(7) or ex3_first_hit_entry_pt_q(8) + or ex3_first_hit_entry_pt_q(9) or ex3_first_hit_entry_pt_q(10) + or ex3_first_hit_entry_pt_q(11) or ex3_first_hit_entry_pt_q(12) + or ex3_first_hit_entry_pt_q(13) or ex3_first_hit_entry_pt_q(14) + or ex3_first_hit_entry_pt_q(15) or ex3_first_hit_entry_pt_q(16)); +ex3_first_hit_entry(1) <= + (ex3_first_hit_entry_pt_q(1) or ex3_first_hit_entry_pt_q(2) + or ex3_first_hit_entry_pt_q(3) or ex3_first_hit_entry_pt_q(4) + or ex3_first_hit_entry_pt_q(5) or ex3_first_hit_entry_pt_q(6) + or ex3_first_hit_entry_pt_q(7) or ex3_first_hit_entry_pt_q(8) + or ex3_first_hit_entry_pt_q(17) or ex3_first_hit_entry_pt_q(18) + or ex3_first_hit_entry_pt_q(19) or ex3_first_hit_entry_pt_q(20) + or ex3_first_hit_entry_pt_q(21) or ex3_first_hit_entry_pt_q(22) + or ex3_first_hit_entry_pt_q(23) or ex3_first_hit_entry_pt_q(24)); +ex3_first_hit_entry(2) <= + (ex3_first_hit_entry_pt_q(1) or ex3_first_hit_entry_pt_q(2) + or ex3_first_hit_entry_pt_q(3) or ex3_first_hit_entry_pt_q(4) + or ex3_first_hit_entry_pt_q(9) or ex3_first_hit_entry_pt_q(10) + or ex3_first_hit_entry_pt_q(11) or ex3_first_hit_entry_pt_q(12) + or ex3_first_hit_entry_pt_q(17) or ex3_first_hit_entry_pt_q(18) + or ex3_first_hit_entry_pt_q(19) or ex3_first_hit_entry_pt_q(20) + or ex3_first_hit_entry_pt_q(25) or ex3_first_hit_entry_pt_q(26) + or ex3_first_hit_entry_pt_q(27) or ex3_first_hit_entry_pt_q(28)); +ex3_first_hit_entry(3) <= + (ex3_first_hit_entry_pt_q(1) or ex3_first_hit_entry_pt_q(2) + or ex3_first_hit_entry_pt_q(5) or ex3_first_hit_entry_pt_q(6) + or ex3_first_hit_entry_pt_q(9) or ex3_first_hit_entry_pt_q(10) + or ex3_first_hit_entry_pt_q(13) or ex3_first_hit_entry_pt_q(14) + or ex3_first_hit_entry_pt_q(17) or ex3_first_hit_entry_pt_q(18) + or ex3_first_hit_entry_pt_q(21) or ex3_first_hit_entry_pt_q(22) + or ex3_first_hit_entry_pt_q(25) or ex3_first_hit_entry_pt_q(26) + or ex3_first_hit_entry_pt_q(29) or ex3_first_hit_entry_pt_q(30)); +ex3_first_hit_entry(4) <= + (ex3_first_hit_entry_pt_q(1) or ex3_first_hit_entry_pt_q(3) + or ex3_first_hit_entry_pt_q(5) or ex3_first_hit_entry_pt_q(7) + or ex3_first_hit_entry_pt_q(9) or ex3_first_hit_entry_pt_q(11) + or ex3_first_hit_entry_pt_q(13) or ex3_first_hit_entry_pt_q(15) + or ex3_first_hit_entry_pt_q(17) or ex3_first_hit_entry_pt_q(19) + or ex3_first_hit_entry_pt_q(21) or ex3_first_hit_entry_pt_q(23) + or ex3_first_hit_entry_pt_q(25) or ex3_first_hit_entry_pt_q(27) + or ex3_first_hit_entry_pt_q(29) or ex3_first_hit_entry_pt_q(31) + ); +ex3_miss_d <= (ex2_valid_q and not(xu_derat_ex2_n_flush) and not(ex2_n_flush_req_q)) + when (cam_hit='0' and ex2_ttype_q(4 to 5) /= "00" and ex2_ttype_q(9)='0' and ccr2_frat_paranoia_q(9)='0') + else (others => '0'); +ex3_hit_d <= or_reduce(ex2_valid_q and not(xu_derat_ex2_n_flush) and not(ex2_n_flush_req_q)) + when (cam_hit='1' and ex2_ttype_q(2 to 5) /= "0000") + else '0'; +ex3_eratsx_data <= ex3_multihit_enab & ex3_hit_q & ex3_first_hit_entry; +ex3_tlbreq_d <= '1' when ((ex2_valid_q and not(xu_derat_ex2_n_flush) and not(ex2_n_flush_req_q) and not(hold_req))/="0000" + and ex2_ttype_q(4 to 5) /= "00" and ex2_ttype_q(9)='0' and cam_hit='0' and ccr2_notlb_q=MMU_Mode_Value + and ccr2_frat_paranoia_q(9)='0') + else '0'; +hold_req_reset_d(0) <= ccr2_frat_paranoia_q(9) or xu_derat_ex2_n_flush(0) or xu_derat_ex3_n_flush(0) or xu_derat_ex4_n_flush(0) or + (tlb_rel_val_q(0) and (ccr2_notlb_q=MMU_Mode_Value)); +hold_req_pot_set_d(0) <= ex2_valid_q(0) and not xu_derat_ex2_n_flush(0) and not ex2_n_flush_req_q(0) and + (ex2_ttype_q(4 to 5)/="00") and not ex2_ttype_q(9) and (ccr2_notlb_q=MMU_Mode_Value); +hold_req_por_d(0) <= por_hold_req(0); +hold_req_set(0) <= (hold_req_pot_set_q(0) and not ex3_cam_hit_q); +hold_req(0) <= '1' when hold_req_por_q(0) = '1' else + '0' when hold_req_reset_q(0) = '1' else + '1' when hold_req_set(0) = '1' else + hold_req_q(0); +hold_req_reset_d(1) <= ccr2_frat_paranoia_q(9) or xu_derat_ex2_n_flush(1) or xu_derat_ex3_n_flush(1) or xu_derat_ex4_n_flush(1) or + (tlb_rel_val_q(1) and (ccr2_notlb_q=MMU_Mode_Value)); +hold_req_pot_set_d(1) <= ex2_valid_q(1) and not xu_derat_ex2_n_flush(1) and not ex2_n_flush_req_q(1) and + (ex2_ttype_q(4 to 5)/="00") and not ex2_ttype_q(9) and (ccr2_notlb_q=MMU_Mode_Value); +hold_req_por_d(1) <= por_hold_req(1); +hold_req_set(1) <= (hold_req_pot_set_q(1) and not ex3_cam_hit_q); +hold_req(1) <= '1' when hold_req_por_q(1) = '1' else + '0' when hold_req_reset_q(1) = '1' else + '1' when hold_req_set(1) = '1' else + hold_req_q(1); +hold_req_reset_d(2) <= ccr2_frat_paranoia_q(9) or xu_derat_ex2_n_flush(2) or xu_derat_ex3_n_flush(2) or xu_derat_ex4_n_flush(2) or + (tlb_rel_val_q(2) and (ccr2_notlb_q=MMU_Mode_Value)); +hold_req_pot_set_d(2) <= ex2_valid_q(2) and not xu_derat_ex2_n_flush(2) and not ex2_n_flush_req_q(2) and + (ex2_ttype_q(4 to 5)/="00") and not ex2_ttype_q(9) and (ccr2_notlb_q=MMU_Mode_Value); +hold_req_por_d(2) <= por_hold_req(2); +hold_req_set(2) <= (hold_req_pot_set_q(2) and not ex3_cam_hit_q); +hold_req(2) <= '1' when hold_req_por_q(2) = '1' else + '0' when hold_req_reset_q(2) = '1' else + '1' when hold_req_set(2) = '1' else + hold_req_q(2); +hold_req_reset_d(3) <= ccr2_frat_paranoia_q(9) or xu_derat_ex2_n_flush(3) or xu_derat_ex3_n_flush(3) or xu_derat_ex4_n_flush(3) or + (tlb_rel_val_q(3) and (ccr2_notlb_q=MMU_Mode_Value)); +hold_req_pot_set_d(3) <= ex2_valid_q(3) and not xu_derat_ex2_n_flush(3) and not ex2_n_flush_req_q(3) and + (ex2_ttype_q(4 to 5)/="00") and not ex2_ttype_q(9) and (ccr2_notlb_q=MMU_Mode_Value); +hold_req_por_d(3) <= por_hold_req(3); +hold_req_set(3) <= (hold_req_pot_set_q(3) and not ex3_cam_hit_q); +hold_req(3) <= '1' when hold_req_por_q(3) = '1' else + '0' when hold_req_reset_q(3) = '1' else + '1' when hold_req_set(3) = '1' else + hold_req_q(3); +hold_req_d <= hold_req; +tlb_req_inprogress_d(0) <= '0' when (ccr2_frat_paranoia_q(9)='1' or por_hold_req(0)='1' or ccr2_notlb_q/=MMU_Mode_Value or tlb_rel_val_q(0)='1') + else '0' when (xu_derat_ex3_n_flush(0)='0' and ex3_valid_q(0)='1' and hold_req(0)='0') + else '1' when (ex3_tlbreq_q='1' and ex3_valid_q(0)='1' and ccr2_notlb_q=MMU_Mode_Value) + else tlb_req_inprogress_q(0); +tlb_req_inprogress_d(1) <= '0' when (ccr2_frat_paranoia_q(9)='1' or por_hold_req(1)='1' or ccr2_notlb_q/=MMU_Mode_Value or tlb_rel_val_q(1)='1') + else '0' when (xu_derat_ex3_n_flush(1)='0' and ex3_valid_q(1)='1' and hold_req(1)='0') + else '1' when (ex3_tlbreq_q='1' and ex3_valid_q(1)='1' and ccr2_notlb_q=MMU_Mode_Value) + else tlb_req_inprogress_q(1); +tlb_req_inprogress_d(2) <= '0' when (ccr2_frat_paranoia_q(9)='1' or por_hold_req(2)='1' or ccr2_notlb_q/=MMU_Mode_Value or tlb_rel_val_q(2)='1') + else '0' when (xu_derat_ex3_n_flush(2)='0' and ex3_valid_q(2)='1' and hold_req(2)='0') + else '1' when (ex3_tlbreq_q='1' and ex3_valid_q(2)='1' and ccr2_notlb_q=MMU_Mode_Value) + else tlb_req_inprogress_q(2); +tlb_req_inprogress_d(3) <= '0' when (ccr2_frat_paranoia_q(9)='1' or por_hold_req(3)='1' or ccr2_notlb_q/=MMU_Mode_Value or tlb_rel_val_q(3)='1') + else '0' when (xu_derat_ex3_n_flush(3)='0' and ex3_valid_q(3)='1' and hold_req(3)='0') + else '1' when (ex3_tlbreq_q='1' and ex3_valid_q(3)='1' and ccr2_notlb_q=MMU_Mode_Value) + else tlb_req_inprogress_q(3); +ex3_multihit_d <= (ex2_valid_q and not(xu_derat_ex2_n_flush) and not(ex2_n_flush_req_q)) when + (cam_hit='1' and ex2_ttype_q(4 to 5) /= "00" and ex2_ttype_q(9)='0' and ccr2_frat_paranoia_q(9)='0') + else (others => '0'); +ex3_parerr_d(0 TO thdid_width-1) <= (ex2_valid_q and not(xu_derat_ex2_n_flush) and not(ex2_n_flush_req_q)); +ex3_parerr_d(thdid_width) <= (cam_hit and (ex2_ttype_q(4) or ex2_ttype_q(5)) and not ex2_ttype_q(9) and not ccr2_frat_paranoia_q(9)); +ex3_parerr_d(thdid_width+1) <= (cam_hit and ex2_ttype_q(2) and ex2_tlbsel_q(0) and ex2_tlbsel_q(1) + and not(ex3_deratwe or ex4_deratwe or ex5_deratwe or ex6_deratwe or ex7_deratwe)); +ex3_parerr_enab <= ((ex3_parerr_q(thdid_width) and (ex3_cmp_data_parerr_epn or ex3_cmp_data_parerr_rpn)) or + (ex3_parerr_q(thdid_width+1) and ex3_cmp_data_parerr_epn)) and not ex3_multihit_enab; +ex4_rd_array_data_d <= rd_array_data; +ex4_rd_cam_data_d <= rd_cam_data; +ex4_parerr_d(0 TO thdid_width-1) <= (ex3_valid_q and not(xu_derat_ex3_n_flush) and not(ex3_n_flush_req_q)); +ex4_parerr_d(thdid_width) <= (ex3_ttype_q(0) and not ex3_ws_q(0) and not ex3_ws_q(1) and ex3_tlbsel_q(0) and ex3_tlbsel_q(1) + and not(ex4_deratwe or ex5_deratwe or ex6_deratwe)); +ex4_parerr_d(thdid_width+1) <= (ex3_ttype_q(0) and xor_reduce(ex3_ws_q) and ex3_tlbsel_q(0) and ex3_tlbsel_q(1) + and not(ex4_deratwe or ex5_deratwe or ex6_deratwe)); +ex4_parerr_enab <= (ex4_parerr_q(thdid_width) and ex4_rd_data_parerr_epn) or + (ex4_parerr_q(thdid_width+1) and ex4_rd_data_parerr_rpn); +ex4_fir_parerr_d(0 TO thdid_width-1) <= (ex3_valid_q and not(xu_derat_ex3_n_flush) and not(ex3_n_flush_req_q)); +ex4_fir_parerr_d(thdid_width) <= (ex3_ttype_q(0) and not ex3_ws_q(0) and not ex3_ws_q(1) and ex3_tlbsel_q(0) and ex3_tlbsel_q(1) + and not(ex4_deratwe or ex5_deratwe or ex6_deratwe)); +ex4_fir_parerr_d(thdid_width+1) <= (ex3_ttype_q(0) and xor_reduce(ex3_ws_q) and ex3_tlbsel_q(0) and ex3_tlbsel_q(1) + and not(ex4_deratwe or ex5_deratwe or ex6_deratwe)); +ex4_fir_parerr_d(thdid_width+2) <= ex3_parerr_enab; +ex4_fir_parerr_enab <= (ex4_fir_parerr_q(thdid_width) and ex4_rd_data_parerr_epn) or + (ex4_fir_parerr_q(thdid_width+1) and ex4_rd_data_parerr_rpn) or + ex4_fir_parerr_q(thdid_width+2); +ex4_fir_multihit_d <= (ex3_multihit_q and not(xu_derat_ex3_n_flush) and not(ex3_n_flush_req_q)) when + (ex3_ttype_q(4 to 5) /= "00" and ex3_ttype_q(9)='0' and ex3_multihit_enab='1') + else (others => '0'); +ex4_deen_d(0 TO thdid_width-1) <= (ex3_multihit_q and not(xu_derat_ex3_n_flush) and not(ex3_n_flush_req_q)) + when ((ex3_ttype_q(4)='1' or ex3_ttype_q(5)='1') and ex3_ttype_q(9)='0' and ex3_multihit_enab='1') + else (others => '0'); +ex4_deen_d(thdid_width TO thdid_width+num_entry_log2-1) <= ex3_eratsx_data(2 to 2+num_entry_log2-1) + when ((ex3_ttype_q(2)='1' or ex3_ttype_q(4)='1' or ex3_ttype_q(5)='1') and ex3_ttype_q(9)='0') + else ex3_ra_entry_q + when (ex3_ttype_q(0)='1' and (ex3_ws_q="00" or ex3_ws_q="01" or ex3_ws_q="10") and ex3_tlbsel_q=TlbSel_DErat) + else (others => '0'); +ex4_hit_d <= ex3_hit_q when or_reduce(ex3_valid_q and not(xu_derat_ex3_n_flush))='1' + else '0'; +ex5_deen_d(0 TO thdid_width-1) <= (ex4_deen_q(0 to thdid_width-1) and not(xu_derat_ex4_n_flush)) or + (ex4_fir_parerr_q(0 to thdid_width-1) and not(xu_derat_ex4_n_flush) and (0 to thdid_width-1 => ex4_fir_parerr_enab)); +ex5_deen_d(thdid_width TO thdid_width+num_entry_log2-1) <= ex4_deen_q(thdid_width to thdid_width+num_entry_log2-1); +ex5_hit_d <= ex4_hit_q when or_reduce(ex4_valid_q and not(xu_derat_ex4_n_flush))='1' + else '0'; +ex6_deen_d <= or_reduce(ex5_deen_q(0 to thdid_width-1)) & + ex5_deen_q(thdid_width to thdid_width+num_entry_log2-1); +ex6_hit_d <= ex5_hit_q when or_reduce(ex5_valid_q and not(xu_derat_ex5_n_flush))='1' + else '0'; +barrier_done_d <= ex6_valid_q when (ex6_ttype_q(0)='1') + else (others => '0'); +ex2_dsi_d(0) <= (ex1_ttype_q(5) and not ex1_ttype_q(8) and not ex1_ttype_q(9) and ex1_state_q(0) and not ccr2_frat_paranoia_q(9)); +ex2_dsi_d(1) <= (ex1_ttype_q(4) and not ex1_ttype_q(8) and not ex1_ttype_q(9) and ex1_state_q(0) and not ccr2_frat_paranoia_q(9)); +ex2_dsi_d(2) <= (ex1_ttype_q(4) and ex1_ttype_q(8) and not ex1_ttype_q(9) and ex1_state_q(0) and not ccr2_frat_paranoia_q(9)); +ex2_dsi_d(3) <= (ex1_ttype_q(5) and not ex1_ttype_q(8) and not ex1_ttype_q(9) and not ex1_state_q(0) and not ccr2_frat_paranoia_q(9)); +ex2_dsi_d(4) <= (ex1_ttype_q(4) and not ex1_ttype_q(8) and not ex1_ttype_q(9) and not ex1_state_q(0) and not ccr2_frat_paranoia_q(9)); +ex2_dsi_d(5) <= (ex1_ttype_q(4) and ex1_ttype_q(8) and not ex1_ttype_q(9) and not ex1_state_q(0) and not ccr2_frat_paranoia_q(9)); +ex2_dsi_d(6) <= (ex1_ttype_q(5) and not ex1_ttype_q(9) and mmucr1_q(2) and not ccr2_frat_paranoia_q(9)); +ex2_dsi_d(7) <= (ex1_ttype_q(4) and not ex1_ttype_q(9) and mmucr1_q(1) and not ccr2_frat_paranoia_q(9)); +ex2_dsi_d(8 TO 11) <= (ex1_valid_q and not(xu_derat_ex1_n_flush) and not(ex2_n_flush_req_d)); +ex2_dsi_d(12 TO 15) <= (ex1_valid_q and not(xu_derat_ex1_n_flush) and not(ex2_n_flush_req_d)); +ex3_dsi_d(0 TO 7) <= ex2_dsi_q(0 to 7); +ex3_dsi_d(8 TO 11) <= (ex2_dsi_q(8 to 11) and not(xu_derat_ex2_n_flush) and not(ex2_n_flush_req_q)); +ex3_dsi_d(12 TO 15) <= (ex2_dsi_q(12 to 15) and not(xu_derat_ex2_n_flush) and not(ex2_n_flush_req_q)); +ex3_dsi(0) <= ex3_dsi_q(0) and not ex3_array_cmp_data_q(47); +ex3_dsi(1) <= ex3_dsi_q(1) and not ex3_array_cmp_data_q(49); +ex3_dsi(2) <= ex3_dsi_q(2) and not ex3_array_cmp_data_q(45) and not ex3_array_cmp_data_q(49); +ex3_dsi(3) <= ex3_dsi_q(3) and not ex3_array_cmp_data_q(48); +ex3_dsi(4) <= ex3_dsi_q(4) and not ex3_array_cmp_data_q(50); +ex3_dsi(5) <= ex3_dsi_q(5) and not ex3_array_cmp_data_q(46) and not ex3_array_cmp_data_q(50); +ex3_dsi(6) <= ex3_dsi_q(6) and not ex3_array_cmp_data_q(31); +ex3_dsi(7) <= ex3_dsi_q(7) and not ex3_array_cmp_data_q(30); +ex3_dsi_enab <= or_reduce(ex3_dsi) and not(or_reduce(ex3_miss_q)); +ex2_noop_touch_d(0) <= ((ex1_ttype_q(4) or ex1_ttype_q(5)) and ex1_ttype_q(9)); +ex2_noop_touch_d(1) <= ((ex1_ttype_q(4) or ex1_ttype_q(5)) and ex1_ttype_q(9)); +ex2_noop_touch_d(2) <= ((ex1_ttype_q(4) or ex1_ttype_q(5)) and ex1_ttype_q(9)); +ex2_noop_touch_d(3) <= (ex1_ttype_q(4) and not ex1_ttype_q(8) and ex1_ttype_q(9) and ex1_state_q(0)); +ex2_noop_touch_d(4) <= (ex1_ttype_q(4) and not ex1_ttype_q(8) and ex1_ttype_q(9) and not ex1_state_q(0)); +ex2_noop_touch_d(5) <= (ex1_ttype_q(5) and not ex1_ttype_q(8) and ex1_ttype_q(9) and ex1_state_q(0)); +ex2_noop_touch_d(6) <= (ex1_ttype_q(5) and not ex1_ttype_q(8) and ex1_ttype_q(9) and not ex1_state_q(0)); +ex2_noop_touch_d(7) <= (ex1_ttype_q(4) and ex1_ttype_q(8) and ex1_ttype_q(9)); +ex2_noop_touch_d(8 TO 11) <= (ex1_valid_q and not(xu_derat_ex1_n_flush) and not(ex2_n_flush_req_d)); +ex2_noop_touch_d(12 TO 15) <= (ex1_valid_q and not(xu_derat_ex1_n_flush) and not(ex2_n_flush_req_d)); +ex3_noop_touch_d(0) <= ex2_noop_touch_q(0) and not cam_hit; +ex3_noop_touch_d(1) <= ex2_noop_touch_q(1) and mmucr1_q(1); +ex3_noop_touch_d(2) <= ex2_noop_touch_q(2) and mmucr1_q(2); +ex3_noop_touch_d(3 TO 7) <= ex2_noop_touch_q(3 to 7); +ex3_noop_touch(0) <= ex3_noop_touch_q(0); +ex3_noop_touch(1) <= ex3_noop_touch_q(1) and not ex3_array_cmp_data_q(30); +ex3_noop_touch(2) <= ex3_noop_touch_q(2) and not ex3_array_cmp_data_q(31); +ex3_noop_touch(3) <= ex3_noop_touch_q(3) and not ex3_array_cmp_data_q(49); +ex3_noop_touch(4) <= ex3_noop_touch_q(4) and not ex3_array_cmp_data_q(50); +ex3_noop_touch(5) <= ex3_noop_touch_q(5) and not ex3_array_cmp_data_q(47); +ex3_noop_touch(6) <= ex3_noop_touch_q(6) and not ex3_array_cmp_data_q(48); +ex3_noop_touch(7) <= ex3_noop_touch_q(7); +ex3_noop_touch_d(8 TO 11) <= (ex2_noop_touch_q(8 to 11) and not(xu_derat_ex2_n_flush) and not(ex2_n_flush_req_q)); +ex3_noop_touch_d(12 TO 15) <= (ex2_noop_touch_q(12 to 15) and not(xu_derat_ex2_n_flush) and not(ex2_n_flush_req_q)); +ex3_noop_touch_enab <= or_reduce(ex3_noop_touch(0 to 7)); +ex3_attr_d <= array_cmp_data(45 to 50) or (0 to 5 => ccr2_frat_paranoia_q(9)); +mchk_flash_inv_d(0) <= ex3_parerr_q(thdid_width) and (ex3_cmp_data_parerr_epn or ex3_cmp_data_parerr_rpn); +mchk_flash_inv_d(1) <= ex3_parerr_q(thdid_width) and ex3_multihit_enab; +mchk_flash_inv_d(2) <= (mchk_flash_inv_q(0) or mchk_flash_inv_q(1)) and or_reduce(ex4_parerr_q(0 to thdid_width-1) and not(xu_derat_ex4_n_flush)); +mchk_flash_inv_d(3) <= mchk_flash_inv_enab; +mchk_flash_inv_enab <= mchk_flash_inv_q(2) and not(ccr2_notlb_q) and not(xucr4_mmu_mchk_q); +ex2_n_flush_req_d <= ex1_valid_q and not(xu_derat_ex1_n_flush) + when ( (tlb_rel_val_q(0 to 3)/="0000" and tlb_rel_val_q(4)='1') + or ((epsc_wr_q(8)='1' or eplc_wr_q(8)='1') and mmucr1_q(7)='0') + or snoop_val_q(0 to 1)="11" + or ((ex1_deratre or ex1_deratwe or ex1_deratsx)='1' and tlb_rel_data_q(eratpos_relsoon)='1') ) + else ex1_valid_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_ws_q="00" and ex6_tlbsel_q=TlbSel_DErat) + else ex1_valid_q when ((ex6_valid_q/="0000" and ex6_ttype_q(6 to 7)/="00") or mchk_flash_inv_enab='1' or mchk_flash_inv_q(3)='1') + else (others => '0'); +ex3_n_flush_req_d <= (ex2_valid_q and not(xu_derat_ex2_n_flush)) + when ex2_n_flush_req_q /= "0000" or + (ex3_valid_q /= "0000" and ex3_ttype_q(1)='1' and + ex2_valid_q /= "0000" and ex2_ttype_q(0)='1' and + ex3_tlbsel_q=ex2_tlbsel_q) or + (ex4_valid_q /= "0000" and ex4_ttype_q(1)='1' and + ex2_valid_q /= "0000" and ex2_ttype_q(0)='1' and + ex4_tlbsel_q=ex2_tlbsel_q) or + (ex5_valid_q /= "0000" and ex5_ttype_q(1)='1' and + ex2_valid_q /= "0000" and ex2_ttype_q(0)='1' and + ex5_tlbsel_q=ex2_tlbsel_q) or + (ex6_valid_q /= "0000" and ex6_ttype_q(1)='1' and + ex2_valid_q /= "0000" and ex2_ttype_q(0)='1' and + ex6_tlbsel_q=ex2_tlbsel_q) or + (ex3_valid_q /= "0000" and ex3_ttype_q(1)='1' and + ex2_valid_q /= "0000" and ex2_ttype_q(2)='1' and + ex3_tlbsel_q=ex2_tlbsel_q) or + (ex4_valid_q /= "0000" and ex4_ttype_q(1)='1' and + ex2_valid_q /= "0000" and ex2_ttype_q(2)='1' and + ex4_tlbsel_q=ex2_tlbsel_q) or + (ex5_valid_q /= "0000" and ex5_ttype_q(1)='1' and + ex2_valid_q /= "0000" and ex2_ttype_q(2)='1' and + ex5_tlbsel_q=ex2_tlbsel_q) or + (ex6_valid_q /= "0000" and ex6_ttype_q(1)='1' and + ex2_valid_q /= "0000" and ex2_ttype_q(2)='1' and + ex6_tlbsel_q=ex2_tlbsel_q) or + (ex7_valid_q /= "0000" and ex7_ttype_q(1)='1' and + ex2_valid_q /= "0000" and ex2_ttype_q(2)='1' and + ex7_tlbsel_q=ex2_tlbsel_q) or + (ex3_valid_q /= "0000" and ex3_ttype_q(4 to 5)/="00" and + ex2_valid_q /= "0000" and ex2_ttype_q(0)='1' and + ex2_ws_q="11" and ex2_tlbsel_q=TlbSel_DErat) or + (ex4_valid_q /= "0000" and ex4_ttype_q(4 to 5)/="00" and + ex2_valid_q /= "0000" and ex2_ttype_q(0)='1' and + ex2_ws_q="11" and ex2_tlbsel_q=TlbSel_DErat) or + (ex5_valid_q /= "0000" and ex5_ttype_q(4 to 5)/="00" and + ex2_valid_q /= "0000" and ex2_ttype_q(0)='1' and + ex2_ws_q="11" and ex2_tlbsel_q=TlbSel_DErat) or + (ex6_valid_q /= "0000" and ex6_ttype_q(4 to 5)/="00" and + ex2_valid_q /= "0000" and ex2_ttype_q(0)='1' and + ex2_ws_q="11" and ex2_tlbsel_q=TlbSel_DErat) + else (others => '0'); +snoop_val_d(0) <= mm_xu_derat_snoop_val when snoop_val_q(0)='0' + else '0' when (tlb_rel_val_q(4)='0' and epsc_wr_q(8)='0' and eplc_wr_q(8)='0' and snoop_val_q(1)='1') + else snoop_val_q(0); +snoop_val_d(1) <= not xu_derat_rf1_binv_val; +snoop_val_d(2) <= '0' when (tlb_rel_val_q(4)='1' or epsc_wr_q(8)='1' or eplc_wr_q(8)='1' or snoop_val_q(1)='0') + else snoop_val_q(0); +snoop_attr_d <= mm_xu_derat_snoop_attr when snoop_val_q(0)='0' + else snoop_attr_q; +snoop_addr_d <= mm_xu_derat_snoop_vpn when snoop_val_q(0)='0' + else snoop_addr_q; +xu_mm_derat_snoop_ack <= snoop_val_q(2); +gen64_holdreg: if rs_data_width = 64 generate +rpn_holdreg0_d(0 TO 19) <= ex6_data_in_q(0 to 19) when (ex6_valid_q(0)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='1') + else ex6_data_in_q(32 to 51) when (ex6_valid_q(0)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='0') + else rpn_holdreg0_q(0 to 19); +rpn_holdreg0_d(20 TO 31) <= ex6_data_in_q(20 to 31) when (ex6_valid_q(0)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='1') + else ex6_data_in_q(52 to 63) when (ex6_valid_q(0)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='0') + else rpn_holdreg0_q(20 to 31); +rpn_holdreg0_d(32 TO 51) <= ex6_data_in_q(32 to 51) when (ex6_valid_q(0)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='1') + else ex6_data_in_q(32 to 51) when (ex6_valid_q(0)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='0') + else rpn_holdreg0_q(32 to 51); +rpn_holdreg0_d(52 TO 63) <= ex6_data_in_q(52 to 63) when (ex6_valid_q(0)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='1') + else ex6_data_in_q(52 to 63) when (ex6_valid_q(0)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='0') + else rpn_holdreg0_q(52 to 63); +rpn_holdreg1_d(0 TO 19) <= ex6_data_in_q(0 to 19) when (ex6_valid_q(1)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='1') + else ex6_data_in_q(32 to 51) when (ex6_valid_q(1)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='0') + else rpn_holdreg1_q(0 to 19); +rpn_holdreg1_d(20 TO 31) <= ex6_data_in_q(20 to 31) when (ex6_valid_q(1)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='1') + else ex6_data_in_q(52 to 63) when (ex6_valid_q(1)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='0') + else rpn_holdreg1_q(20 to 31); +rpn_holdreg1_d(32 TO 51) <= ex6_data_in_q(32 to 51) when (ex6_valid_q(1)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='1') + else ex6_data_in_q(32 to 51) when (ex6_valid_q(1)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='0') + else rpn_holdreg1_q(32 to 51); +rpn_holdreg1_d(52 TO 63) <= ex6_data_in_q(52 to 63) when (ex6_valid_q(1)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='1') + else ex6_data_in_q(52 to 63) when (ex6_valid_q(1)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='0') + else rpn_holdreg1_q(52 to 63); +rpn_holdreg2_d(0 TO 19) <= ex6_data_in_q(0 to 19) when (ex6_valid_q(2)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='1') + else ex6_data_in_q(32 to 51) when (ex6_valid_q(2)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='0') + else rpn_holdreg2_q(0 to 19); +rpn_holdreg2_d(20 TO 31) <= ex6_data_in_q(20 to 31) when (ex6_valid_q(2)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='1') + else ex6_data_in_q(52 to 63) when (ex6_valid_q(2)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='0') + else rpn_holdreg2_q(20 to 31); +rpn_holdreg2_d(32 TO 51) <= ex6_data_in_q(32 to 51) when (ex6_valid_q(2)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='1') + else ex6_data_in_q(32 to 51) when (ex6_valid_q(2)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='0') + else rpn_holdreg2_q(32 to 51); +rpn_holdreg2_d(52 TO 63) <= ex6_data_in_q(52 to 63) when (ex6_valid_q(2)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='1') + else ex6_data_in_q(52 to 63) when (ex6_valid_q(2)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='0') + else rpn_holdreg2_q(52 to 63); +rpn_holdreg3_d(0 TO 19) <= ex6_data_in_q(0 to 19) when (ex6_valid_q(3)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='1') + else ex6_data_in_q(32 to 51) when (ex6_valid_q(3)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='0') + else rpn_holdreg3_q(0 to 19); +rpn_holdreg3_d(20 TO 31) <= ex6_data_in_q(20 to 31) when (ex6_valid_q(3)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='1') + else ex6_data_in_q(52 to 63) when (ex6_valid_q(3)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='0') + else rpn_holdreg3_q(20 to 31); +rpn_holdreg3_d(32 TO 51) <= ex6_data_in_q(32 to 51) when (ex6_valid_q(3)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='1') + else ex6_data_in_q(32 to 51) when (ex6_valid_q(3)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='0') + else rpn_holdreg3_q(32 to 51); +rpn_holdreg3_d(52 TO 63) <= ex6_data_in_q(52 to 63) when (ex6_valid_q(3)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='1') + else ex6_data_in_q(52 to 63) when (ex6_valid_q(3)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='0') + else rpn_holdreg3_q(52 to 63); +end generate gen64_holdreg; +gen32_holdreg: if rs_data_width = 32 generate +rpn_holdreg0_d(32 TO 51) <= ex6_data_in_q(32 to 51) when (ex6_valid_q(0)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat) + else rpn_holdreg0_q(32 to 51); +rpn_holdreg0_d(20 TO 31) <= ex6_data_in_q(52 to 63) when (ex6_valid_q(0)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat) + else rpn_holdreg0_q(20 to 31); +rpn_holdreg0_d(52 TO 63) <= ex6_data_in_q(52 to 63) when (ex6_valid_q(0)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_DErat) + else rpn_holdreg0_q(52 to 63); +rpn_holdreg0_d(0 TO 19) <= ex6_data_in_q(32 to 51) when (ex6_valid_q(0)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_DErat) + else rpn_holdreg0_q(0 to 19); +rpn_holdreg1_d(32 TO 51) <= ex6_data_in_q(32 to 51) when (ex6_valid_q(1)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat) + else rpn_holdreg1_q(32 to 51); +rpn_holdreg1_d(20 TO 31) <= ex6_data_in_q(52 to 63) when (ex6_valid_q(1)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat) + else rpn_holdreg1_q(20 to 31); +rpn_holdreg1_d(52 TO 63) <= ex6_data_in_q(52 to 63) when (ex6_valid_q(1)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_DErat) + else rpn_holdreg1_q(52 to 63); +rpn_holdreg1_d(0 TO 19) <= ex6_data_in_q(32 to 51) when (ex6_valid_q(1)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_DErat) + else rpn_holdreg1_q(0 to 19); +rpn_holdreg2_d(32 TO 51) <= ex6_data_in_q(32 to 51) when (ex6_valid_q(2)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat) + else rpn_holdreg2_q(32 to 51); +rpn_holdreg2_d(20 TO 31) <= ex6_data_in_q(52 to 63) when (ex6_valid_q(2)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat) + else rpn_holdreg2_q(20 to 31); +rpn_holdreg2_d(52 TO 63) <= ex6_data_in_q(52 to 63) when (ex6_valid_q(2)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_DErat) + else rpn_holdreg2_q(52 to 63); +rpn_holdreg2_d(0 TO 19) <= ex6_data_in_q(32 to 51) when (ex6_valid_q(2)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_DErat) + else rpn_holdreg2_q(0 to 19); +rpn_holdreg3_d(32 TO 51) <= ex6_data_in_q(32 to 51) when (ex6_valid_q(3)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat) + else rpn_holdreg3_q(32 to 51); +rpn_holdreg3_d(20 TO 31) <= ex6_data_in_q(52 to 63) when (ex6_valid_q(3)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat) + else rpn_holdreg3_q(20 to 31); +rpn_holdreg3_d(52 TO 63) <= ex6_data_in_q(52 to 63) when (ex6_valid_q(3)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_DErat) + else rpn_holdreg3_q(52 to 63); +rpn_holdreg3_d(0 TO 19) <= ex6_data_in_q(32 to 51) when (ex6_valid_q(3)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_DErat) + else rpn_holdreg3_q(0 to 19); +end generate gen32_holdreg; +ex6_deratwe_ws3 <= or_reduce(ex6_valid_q) and ex6_ttype_q(1) and Eq(ex6_ws_q,"11") and Eq(ex6_tlbsel_q,TlbSel_DErat); +watermark_d <= ex6_data_in_q(64-watermark_width to 63) when ex6_deratwe_ws3='1' + else watermark_q; +eptr_d <= (others => '0') when (ex6_deratwe_ws3='1' and mmucr1_q(0)='1') + else (others => '0') when (eptr_q="11111" or eptr_q=watermark_q) and + ( (ex6_valid_q /= "0000" and ex6_ttype_q(1)='1' and + ex6_ws_q="00" and ex6_tlbsel_q=TlbSel_DErat and mmucr1_q(0)='1') or + (tlb_rel_val_q(0 to 3)/="0000" and tlb_rel_val_q(4)='1' and + tlb_rel_data_q(eratpos_wren)='1' and mmucr1_q(0)='1') ) + else eptr_p1 when ( (ex6_valid_q /= "0000" and ex6_ttype_q(1)='1' and + ex6_ws_q="00" and ex6_tlbsel_q=TlbSel_DErat and mmucr1_q(0)='1') or + (tlb_rel_val_q(0 to 3)/="0000" and tlb_rel_val_q(4)='1' and + tlb_rel_data_q(eratpos_wren)='1' and mmucr1_q(0)='1') ) + else eptr_q; +eptr_p1 <= "00001" when eptr_q="00000" + else "00010" when eptr_q="00001" + else "00011" when eptr_q="00010" + else "00100" when eptr_q="00011" + else "00101" when eptr_q="00100" + else "00110" when eptr_q="00101" + else "00111" when eptr_q="00110" + else "01000" when eptr_q="00111" + else "01001" when eptr_q="01000" + else "01010" when eptr_q="01001" + else "01011" when eptr_q="01010" + else "01100" when eptr_q="01011" + else "01101" when eptr_q="01100" + else "01110" when eptr_q="01101" + else "01111" when eptr_q="01110" + else "10000" when eptr_q="01111" + else "10001" when eptr_q="10000" + else "10010" when eptr_q="10001" + else "10011" when eptr_q="10010" + else "10100" when eptr_q="10011" + else "10101" when eptr_q="10100" + else "10110" when eptr_q="10101" + else "10111" when eptr_q="10110" + else "11000" when eptr_q="10111" + else "11001" when eptr_q="11000" + else "11010" when eptr_q="11001" + else "11011" when eptr_q="11010" + else "11100" when eptr_q="11011" + else "11101" when eptr_q="11100" + else "11110" when eptr_q="11101" + else "11111" when eptr_q="11110" + else "00000"; +ex2_epn_d <= xu_derat_ex1_epn_nonarr(52-ex2_epn_width to 51); +lru_update_event_d(0) <= (tlb_rel_data_q(eratpos_wren) and or_reduce(tlb_rel_val_q(0 to 3)) and tlb_rel_val_q(4)); +lru_update_event_d(1) <= (snoop_val_q(0) and snoop_val_q(1)); +lru_update_event_d(2) <= (or_reduce(ex6_valid_q) and or_reduce(ex6_ttype_q(6 to 7))); +lru_update_event_d(3) <= (or_reduce(ex6_valid_q) and ex6_ttype_q(1) + and Eq(ex6_ws_q,"00") and Eq(ex6_tlbsel_q,TlbSel_DErat) and Eq(lru_way_encode,ex6_ra_entry_q)); +lru_update_event_d(4) <= (or_reduce(ex6_valid_q) and or_reduce(ex6_ttype_q(4 to 5)) and ex6_hit_q ); +lru_update_event_d(5) <= lru_update_event_q(0) or lru_update_event_q(3); +lru_update_event_d(6) <= lru_update_event_q(1) or lru_update_event_q(2); +lru_update_event_d(7) <= lru_update_event_q(4); +lru_update_event_d(8) <= (tlb_rel_data_q(eratpos_wren) and or_reduce(tlb_rel_val_q(0 to 3)) and tlb_rel_val_q(4)) + or (snoop_val_q(0) and snoop_val_q(1)) + or (or_reduce(ex6_valid_q) and or_reduce(ex6_ttype_q(6 to 7))) + or (or_reduce(ex6_valid_q) and ex6_ttype_q(1) + and Eq(ex6_ws_q,"00") and Eq(ex6_tlbsel_q,TlbSel_DErat) and Eq(lru_way_encode,ex6_ra_entry_q)) + or (or_reduce(ex6_valid_q) and or_reduce(ex6_ttype_q(4 to 5)) and ex6_hit_q ); +lru_update_event_d(9) <= lru_update_event_q(8); +lru_d(1) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(1)='1' and lru_op_vec(1)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(1)='1' and lru_op_vec(1)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(1); +lru_eff(1) <= (lru_vp_vec(1) and lru_op_vec(1)) or (lru_q(1) and not lru_op_vec(1)); +lru_d(2) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(2)='1' and lru_op_vec(2)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(2)='1' and lru_op_vec(2)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(2); +lru_eff(2) <= (lru_vp_vec(2) and lru_op_vec(2)) or (lru_q(2) and not lru_op_vec(2)); +lru_d(3) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(3)='1' and lru_op_vec(3)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(3)='1' and lru_op_vec(3)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(3); +lru_eff(3) <= (lru_vp_vec(3) and lru_op_vec(3)) or (lru_q(3) and not lru_op_vec(3)); +lru_d(4) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(4)='1' and lru_op_vec(4)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(4)='1' and lru_op_vec(4)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(4); +lru_eff(4) <= (lru_vp_vec(4) and lru_op_vec(4)) or (lru_q(4) and not lru_op_vec(4)); +lru_d(5) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(5)='1' and lru_op_vec(5)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(5)='1' and lru_op_vec(5)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(5); +lru_eff(5) <= (lru_vp_vec(5) and lru_op_vec(5)) or (lru_q(5) and not lru_op_vec(5)); +lru_d(6) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(6)='1' and lru_op_vec(6)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(6)='1' and lru_op_vec(6)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(6); +lru_eff(6) <= (lru_vp_vec(6) and lru_op_vec(6)) or (lru_q(6) and not lru_op_vec(6)); +lru_d(7) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(7)='1' and lru_op_vec(7)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(7)='1' and lru_op_vec(7)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(7); +lru_eff(7) <= (lru_vp_vec(7) and lru_op_vec(7)) or (lru_q(7) and not lru_op_vec(7)); +lru_d(8) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(8)='1' and lru_op_vec(8)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(8)='1' and lru_op_vec(8)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(8); +lru_eff(8) <= (lru_vp_vec(8) and lru_op_vec(8)) or (lru_q(8) and not lru_op_vec(8)); +lru_d(9) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(9)='1' and lru_op_vec(9)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(9)='1' and lru_op_vec(9)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(9); +lru_eff(9) <= (lru_vp_vec(9) and lru_op_vec(9)) or (lru_q(9) and not lru_op_vec(9)); +lru_d(10) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(10)='1' and lru_op_vec(10)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(10)='1' and lru_op_vec(10)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(10); +lru_eff(10) <= (lru_vp_vec(10) and lru_op_vec(10)) or (lru_q(10) and not lru_op_vec(10)); +lru_d(11) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(11)='1' and lru_op_vec(11)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(11)='1' and lru_op_vec(11)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(11); +lru_eff(11) <= (lru_vp_vec(11) and lru_op_vec(11)) or (lru_q(11) and not lru_op_vec(11)); +lru_d(12) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(12)='1' and lru_op_vec(12)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(12)='1' and lru_op_vec(12)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(12); +lru_eff(12) <= (lru_vp_vec(12) and lru_op_vec(12)) or (lru_q(12) and not lru_op_vec(12)); +lru_d(13) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(13)='1' and lru_op_vec(13)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(13)='1' and lru_op_vec(13)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(13); +lru_eff(13) <= (lru_vp_vec(13) and lru_op_vec(13)) or (lru_q(13) and not lru_op_vec(13)); +lru_d(14) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(14)='1' and lru_op_vec(14)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(14)='1' and lru_op_vec(14)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(14); +lru_eff(14) <= (lru_vp_vec(14) and lru_op_vec(14)) or (lru_q(14) and not lru_op_vec(14)); +lru_d(15) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(15)='1' and lru_op_vec(15)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(15)='1' and lru_op_vec(15)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(15); +lru_eff(15) <= (lru_vp_vec(15) and lru_op_vec(15)) or (lru_q(15) and not lru_op_vec(15)); +lru_d(16) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(16)='1' and lru_op_vec(16)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(16)='1' and lru_op_vec(16)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(16); +lru_eff(16) <= (lru_vp_vec(16) and lru_op_vec(16)) or (lru_q(16) and not lru_op_vec(16)); +lru_d(17) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(17)='1' and lru_op_vec(17)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(17)='1' and lru_op_vec(17)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(17); +lru_eff(17) <= (lru_vp_vec(17) and lru_op_vec(17)) or (lru_q(17) and not lru_op_vec(17)); +lru_d(18) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(18)='1' and lru_op_vec(18)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(18)='1' and lru_op_vec(18)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(18); +lru_eff(18) <= (lru_vp_vec(18) and lru_op_vec(18)) or (lru_q(18) and not lru_op_vec(18)); +lru_d(19) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(19)='1' and lru_op_vec(19)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(19)='1' and lru_op_vec(19)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(19); +lru_eff(19) <= (lru_vp_vec(19) and lru_op_vec(19)) or (lru_q(19) and not lru_op_vec(19)); +lru_d(20) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(20)='1' and lru_op_vec(20)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(20)='1' and lru_op_vec(20)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(20); +lru_eff(20) <= (lru_vp_vec(20) and lru_op_vec(20)) or (lru_q(20) and not lru_op_vec(20)); +lru_d(21) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(21)='1' and lru_op_vec(21)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(21)='1' and lru_op_vec(21)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(21); +lru_eff(21) <= (lru_vp_vec(21) and lru_op_vec(21)) or (lru_q(21) and not lru_op_vec(21)); +lru_d(22) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(22)='1' and lru_op_vec(22)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(22)='1' and lru_op_vec(22)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(22); +lru_eff(22) <= (lru_vp_vec(22) and lru_op_vec(22)) or (lru_q(22) and not lru_op_vec(22)); +lru_d(23) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(23)='1' and lru_op_vec(23)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(23)='1' and lru_op_vec(23)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(23); +lru_eff(23) <= (lru_vp_vec(23) and lru_op_vec(23)) or (lru_q(23) and not lru_op_vec(23)); +lru_d(24) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(24)='1' and lru_op_vec(24)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(24)='1' and lru_op_vec(24)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(24); +lru_eff(24) <= (lru_vp_vec(24) and lru_op_vec(24)) or (lru_q(24) and not lru_op_vec(24)); +lru_d(25) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(25)='1' and lru_op_vec(25)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(25)='1' and lru_op_vec(25)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(25); +lru_eff(25) <= (lru_vp_vec(25) and lru_op_vec(25)) or (lru_q(25) and not lru_op_vec(25)); +lru_d(26) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(26)='1' and lru_op_vec(26)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(26)='1' and lru_op_vec(26)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(26); +lru_eff(26) <= (lru_vp_vec(26) and lru_op_vec(26)) or (lru_q(26) and not lru_op_vec(26)); +lru_d(27) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(27)='1' and lru_op_vec(27)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(27)='1' and lru_op_vec(27)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(27); +lru_eff(27) <= (lru_vp_vec(27) and lru_op_vec(27)) or (lru_q(27) and not lru_op_vec(27)); +lru_d(28) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(28)='1' and lru_op_vec(28)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(28)='1' and lru_op_vec(28)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(28); +lru_eff(28) <= (lru_vp_vec(28) and lru_op_vec(28)) or (lru_q(28) and not lru_op_vec(28)); +lru_d(29) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(29)='1' and lru_op_vec(29)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(29)='1' and lru_op_vec(29)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(29); +lru_eff(29) <= (lru_vp_vec(29) and lru_op_vec(29)) or (lru_q(29) and not lru_op_vec(29)); +lru_d(30) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(30)='1' and lru_op_vec(30)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(30)='1' and lru_op_vec(30)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(30); +lru_eff(30) <= (lru_vp_vec(30) and lru_op_vec(30)) or (lru_q(30) and not lru_op_vec(30)); +lru_d(31) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(31)='1' and lru_op_vec(31)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(31)='1' and lru_op_vec(31)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(31); +lru_eff(31) <= (lru_vp_vec(31) and lru_op_vec(31)) or (lru_q(31) and not lru_op_vec(31)); +lru_op_vec(1) <= (lru_rmt_vec(0) or lru_rmt_vec(1) or lru_rmt_vec(2) or lru_rmt_vec(3) or + lru_rmt_vec(4) or lru_rmt_vec(5) or lru_rmt_vec(6) or lru_rmt_vec(7) or + lru_rmt_vec(8) or lru_rmt_vec(9) or lru_rmt_vec(10) or lru_rmt_vec(11) or + lru_rmt_vec(12) or lru_rmt_vec(13) or lru_rmt_vec(14) or lru_rmt_vec(15)) xor + (lru_rmt_vec(16) or lru_rmt_vec(17) or lru_rmt_vec(18) or lru_rmt_vec(19) or + lru_rmt_vec(20) or lru_rmt_vec(21) or lru_rmt_vec(22) or lru_rmt_vec(23) or + lru_rmt_vec(24) or lru_rmt_vec(25) or lru_rmt_vec(26) or lru_rmt_vec(27) or + lru_rmt_vec(28) or lru_rmt_vec(29) or lru_rmt_vec(30) or lru_rmt_vec(31)); +lru_op_vec(2) <= (lru_rmt_vec(0) or lru_rmt_vec(1) or lru_rmt_vec(2) or lru_rmt_vec(3) or + lru_rmt_vec(4) or lru_rmt_vec(5) or lru_rmt_vec(6) or lru_rmt_vec(7)) xor + (lru_rmt_vec(8) or lru_rmt_vec(9) or lru_rmt_vec(10) or lru_rmt_vec(11) or + lru_rmt_vec(12) or lru_rmt_vec(13) or lru_rmt_vec(14) or lru_rmt_vec(15)); +lru_op_vec(3) <= (lru_rmt_vec(16) or lru_rmt_vec(17) or lru_rmt_vec(18) or lru_rmt_vec(19) or + lru_rmt_vec(20) or lru_rmt_vec(21) or lru_rmt_vec(22) or lru_rmt_vec(23)) xor + (lru_rmt_vec(24) or lru_rmt_vec(25) or lru_rmt_vec(26) or lru_rmt_vec(27) or + lru_rmt_vec(28) or lru_rmt_vec(29) or lru_rmt_vec(30) or lru_rmt_vec(31)); +lru_op_vec(4) <= (lru_rmt_vec(0) or lru_rmt_vec(1) or lru_rmt_vec(2) or lru_rmt_vec(3)) xor + (lru_rmt_vec(4) or lru_rmt_vec(5) or lru_rmt_vec(6) or lru_rmt_vec(7)); +lru_op_vec(5) <= (lru_rmt_vec(8) or lru_rmt_vec(9) or lru_rmt_vec(10) or lru_rmt_vec(11)) xor + (lru_rmt_vec(12) or lru_rmt_vec(13) or lru_rmt_vec(14) or lru_rmt_vec(15)); +lru_op_vec(6) <= (lru_rmt_vec(16) or lru_rmt_vec(17) or lru_rmt_vec(18) or lru_rmt_vec(19)) xor + (lru_rmt_vec(20) or lru_rmt_vec(21) or lru_rmt_vec(22) or lru_rmt_vec(23)); +lru_op_vec(7) <= (lru_rmt_vec(24) or lru_rmt_vec(25) or lru_rmt_vec(26) or lru_rmt_vec(27)) xor + (lru_rmt_vec(28) or lru_rmt_vec(29) or lru_rmt_vec(30) or lru_rmt_vec(31)); +lru_op_vec(8) <= (lru_rmt_vec(0) or lru_rmt_vec(1)) xor (lru_rmt_vec(2) or lru_rmt_vec(3)); +lru_op_vec(9) <= (lru_rmt_vec(4) or lru_rmt_vec(5)) xor (lru_rmt_vec(6) or lru_rmt_vec(7)); +lru_op_vec(10) <= (lru_rmt_vec(8) or lru_rmt_vec(9)) xor (lru_rmt_vec(10) or lru_rmt_vec(11)); +lru_op_vec(11) <= (lru_rmt_vec(12) or lru_rmt_vec(13)) xor (lru_rmt_vec(14) or lru_rmt_vec(15)); +lru_op_vec(12) <= (lru_rmt_vec(16) or lru_rmt_vec(17)) xor (lru_rmt_vec(18) or lru_rmt_vec(19)); +lru_op_vec(13) <= (lru_rmt_vec(20) or lru_rmt_vec(21)) xor (lru_rmt_vec(22) or lru_rmt_vec(23)); +lru_op_vec(14) <= (lru_rmt_vec(24) or lru_rmt_vec(25)) xor (lru_rmt_vec(26) or lru_rmt_vec(27)); +lru_op_vec(15) <= (lru_rmt_vec(28) or lru_rmt_vec(29)) xor (lru_rmt_vec(30) or lru_rmt_vec(31)); +lru_op_vec(16) <= lru_rmt_vec(0) xor lru_rmt_vec(1); +lru_op_vec(17) <= lru_rmt_vec(2) xor lru_rmt_vec(3); +lru_op_vec(18) <= lru_rmt_vec(4) xor lru_rmt_vec(5); +lru_op_vec(19) <= lru_rmt_vec(6) xor lru_rmt_vec(7); +lru_op_vec(20) <= lru_rmt_vec(8) xor lru_rmt_vec(9); +lru_op_vec(21) <= lru_rmt_vec(10) xor lru_rmt_vec(11); +lru_op_vec(22) <= lru_rmt_vec(12) xor lru_rmt_vec(13); +lru_op_vec(23) <= lru_rmt_vec(14) xor lru_rmt_vec(15); +lru_op_vec(24) <= lru_rmt_vec(16) xor lru_rmt_vec(17); +lru_op_vec(25) <= lru_rmt_vec(18) xor lru_rmt_vec(19); +lru_op_vec(26) <= lru_rmt_vec(20) xor lru_rmt_vec(21); +lru_op_vec(27) <= lru_rmt_vec(22) xor lru_rmt_vec(23); +lru_op_vec(28) <= lru_rmt_vec(24) xor lru_rmt_vec(25); +lru_op_vec(29) <= lru_rmt_vec(26) xor lru_rmt_vec(27); +lru_op_vec(30) <= lru_rmt_vec(28) xor lru_rmt_vec(29); +lru_op_vec(31) <= lru_rmt_vec(30) xor lru_rmt_vec(31); +lru_vp_vec(1) <= (lru_rmt_vec(16) or lru_rmt_vec(17) or lru_rmt_vec(18) or lru_rmt_vec(19) or + lru_rmt_vec(20) or lru_rmt_vec(21) or lru_rmt_vec(22) or lru_rmt_vec(23) or + lru_rmt_vec(24) or lru_rmt_vec(25) or lru_rmt_vec(26) or lru_rmt_vec(27) or + lru_rmt_vec(28) or lru_rmt_vec(29) or lru_rmt_vec(30) or lru_rmt_vec(31)); +lru_vp_vec(2) <= (lru_rmt_vec(8) or lru_rmt_vec(9) or lru_rmt_vec(10) or lru_rmt_vec(11) or + lru_rmt_vec(12) or lru_rmt_vec(13) or lru_rmt_vec(14) or lru_rmt_vec(15)); +lru_vp_vec(3) <= (lru_rmt_vec(24) or lru_rmt_vec(25) or lru_rmt_vec(26) or lru_rmt_vec(27) or + lru_rmt_vec(28) or lru_rmt_vec(29) or lru_rmt_vec(30) or lru_rmt_vec(31)); +lru_vp_vec(4) <= (lru_rmt_vec(4) or lru_rmt_vec(5) or lru_rmt_vec(6) or lru_rmt_vec(7)); +lru_vp_vec(5) <= (lru_rmt_vec(12) or lru_rmt_vec(13) or lru_rmt_vec(14) or lru_rmt_vec(15)); +lru_vp_vec(6) <= (lru_rmt_vec(20) or lru_rmt_vec(21) or lru_rmt_vec(22) or lru_rmt_vec(23)); +lru_vp_vec(7) <= (lru_rmt_vec(28) or lru_rmt_vec(29) or lru_rmt_vec(30) or lru_rmt_vec(31)); +lru_vp_vec(8) <= (lru_rmt_vec(2) or lru_rmt_vec(3)); +lru_vp_vec(9) <= (lru_rmt_vec(6) or lru_rmt_vec(7)); +lru_vp_vec(10) <= (lru_rmt_vec(10) or lru_rmt_vec(11)); +lru_vp_vec(11) <= (lru_rmt_vec(14) or lru_rmt_vec(15)); +lru_vp_vec(12) <= (lru_rmt_vec(18) or lru_rmt_vec(19)); +lru_vp_vec(13) <= (lru_rmt_vec(22) or lru_rmt_vec(23)); +lru_vp_vec(14) <= (lru_rmt_vec(26) or lru_rmt_vec(27)); +lru_vp_vec(15) <= (lru_rmt_vec(30) or lru_rmt_vec(31)); +lru_vp_vec(16) <= lru_rmt_vec(1); +lru_vp_vec(17) <= lru_rmt_vec(3); +lru_vp_vec(18) <= lru_rmt_vec(5); +lru_vp_vec(19) <= lru_rmt_vec(7); +lru_vp_vec(20) <= lru_rmt_vec(9); +lru_vp_vec(21) <= lru_rmt_vec(11); +lru_vp_vec(22) <= lru_rmt_vec(13); +lru_vp_vec(23) <= lru_rmt_vec(15); +lru_vp_vec(24) <= lru_rmt_vec(17); +lru_vp_vec(25) <= lru_rmt_vec(19); +lru_vp_vec(26) <= lru_rmt_vec(21); +lru_vp_vec(27) <= lru_rmt_vec(23); +lru_vp_vec(28) <= lru_rmt_vec(25); +lru_vp_vec(29) <= lru_rmt_vec(27); +lru_vp_vec(30) <= lru_rmt_vec(29); +lru_vp_vec(31) <= lru_rmt_vec(31); +MQQ70:LRU_RMT_VEC_D_PT(1) <= + Eq(( WATERMARK_D(0) & WATERMARK_D(1) & + WATERMARK_D(2) & WATERMARK_D(3) & + WATERMARK_D(4) ) , STD_ULOGIC_VECTOR'("11111")); +MQQ71:LRU_RMT_VEC_D_PT(2) <= + Eq(( WATERMARK_D(1) & WATERMARK_D(2) & + WATERMARK_D(3) & WATERMARK_D(4) + ) , STD_ULOGIC_VECTOR'("1111")); +MQQ72:LRU_RMT_VEC_D_PT(3) <= + Eq(( WATERMARK_D(0) & WATERMARK_D(2) & + WATERMARK_D(3) & WATERMARK_D(4) + ) , STD_ULOGIC_VECTOR'("1111")); +MQQ73:LRU_RMT_VEC_D_PT(4) <= + Eq(( WATERMARK_D(2) & WATERMARK_D(3) & + WATERMARK_D(4) ) , STD_ULOGIC_VECTOR'("111")); +MQQ74:LRU_RMT_VEC_D_PT(5) <= + Eq(( WATERMARK_D(0) & WATERMARK_D(1) & + WATERMARK_D(3) & WATERMARK_D(4) + ) , STD_ULOGIC_VECTOR'("1111")); +MQQ75:LRU_RMT_VEC_D_PT(6) <= + Eq(( WATERMARK_D(1) & WATERMARK_D(3) & + WATERMARK_D(4) ) , STD_ULOGIC_VECTOR'("111")); +MQQ76:LRU_RMT_VEC_D_PT(7) <= + Eq(( WATERMARK_D(0) & WATERMARK_D(3) & + WATERMARK_D(4) ) , STD_ULOGIC_VECTOR'("111")); +MQQ77:LRU_RMT_VEC_D_PT(8) <= + Eq(( WATERMARK_D(3) & WATERMARK_D(4) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ78:LRU_RMT_VEC_D_PT(9) <= + Eq(( WATERMARK_D(0) & WATERMARK_D(1) & + WATERMARK_D(2) & WATERMARK_D(4) + ) , STD_ULOGIC_VECTOR'("1111")); +MQQ79:LRU_RMT_VEC_D_PT(10) <= + Eq(( WATERMARK_D(1) & WATERMARK_D(2) & + WATERMARK_D(4) ) , STD_ULOGIC_VECTOR'("111")); +MQQ80:LRU_RMT_VEC_D_PT(11) <= + Eq(( WATERMARK_D(0) & WATERMARK_D(2) & + WATERMARK_D(4) ) , STD_ULOGIC_VECTOR'("111")); +MQQ81:LRU_RMT_VEC_D_PT(12) <= + Eq(( WATERMARK_D(2) & WATERMARK_D(4) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ82:LRU_RMT_VEC_D_PT(13) <= + Eq(( WATERMARK_D(0) & WATERMARK_D(1) & + WATERMARK_D(4) ) , STD_ULOGIC_VECTOR'("111")); +MQQ83:LRU_RMT_VEC_D_PT(14) <= + Eq(( WATERMARK_D(1) & WATERMARK_D(4) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ84:LRU_RMT_VEC_D_PT(15) <= + Eq(( WATERMARK_D(0) & WATERMARK_D(4) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ85:LRU_RMT_VEC_D_PT(16) <= + Eq(( WATERMARK_D(4) ) , STD_ULOGIC'('1')); +MQQ86:LRU_RMT_VEC_D_PT(17) <= + Eq(( WATERMARK_D(0) & WATERMARK_D(1) & + WATERMARK_D(2) & WATERMARK_D(3) + ) , STD_ULOGIC_VECTOR'("1111")); +MQQ87:LRU_RMT_VEC_D_PT(18) <= + Eq(( WATERMARK_D(1) & WATERMARK_D(2) & + WATERMARK_D(3) ) , STD_ULOGIC_VECTOR'("111")); +MQQ88:LRU_RMT_VEC_D_PT(19) <= + Eq(( WATERMARK_D(0) & WATERMARK_D(2) & + WATERMARK_D(3) ) , STD_ULOGIC_VECTOR'("111")); +MQQ89:LRU_RMT_VEC_D_PT(20) <= + Eq(( WATERMARK_D(2) & WATERMARK_D(3) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ90:LRU_RMT_VEC_D_PT(21) <= + Eq(( WATERMARK_D(0) & WATERMARK_D(1) & + WATERMARK_D(3) ) , STD_ULOGIC_VECTOR'("111")); +MQQ91:LRU_RMT_VEC_D_PT(22) <= + Eq(( WATERMARK_D(1) & WATERMARK_D(3) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ92:LRU_RMT_VEC_D_PT(23) <= + Eq(( WATERMARK_D(0) & WATERMARK_D(3) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ93:LRU_RMT_VEC_D_PT(24) <= + Eq(( WATERMARK_D(3) ) , STD_ULOGIC'('1')); +MQQ94:LRU_RMT_VEC_D_PT(25) <= + Eq(( WATERMARK_D(0) & WATERMARK_D(1) & + WATERMARK_D(2) ) , STD_ULOGIC_VECTOR'("111")); +MQQ95:LRU_RMT_VEC_D_PT(26) <= + Eq(( WATERMARK_D(1) & WATERMARK_D(2) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ96:LRU_RMT_VEC_D_PT(27) <= + Eq(( WATERMARK_D(0) & WATERMARK_D(2) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ97:LRU_RMT_VEC_D_PT(28) <= + Eq(( WATERMARK_D(2) ) , STD_ULOGIC'('1')); +MQQ98:LRU_RMT_VEC_D_PT(29) <= + Eq(( WATERMARK_D(0) & WATERMARK_D(1) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ99:LRU_RMT_VEC_D_PT(30) <= + Eq(( WATERMARK_D(1) ) , STD_ULOGIC'('1')); +MQQ100:LRU_RMT_VEC_D_PT(31) <= + Eq(( WATERMARK_D(0) ) , STD_ULOGIC'('1')); +MQQ101:LRU_RMT_VEC_D_PT(32) <= + '1'; +MQQ102:LRU_RMT_VEC_D(0) <= + (LRU_RMT_VEC_D_PT(32)); +MQQ103:LRU_RMT_VEC_D(1) <= + (LRU_RMT_VEC_D_PT(16) OR LRU_RMT_VEC_D_PT(24) + OR LRU_RMT_VEC_D_PT(28) OR LRU_RMT_VEC_D_PT(30) + OR LRU_RMT_VEC_D_PT(31)); +MQQ104:LRU_RMT_VEC_D(2) <= + (LRU_RMT_VEC_D_PT(24) OR LRU_RMT_VEC_D_PT(28) + OR LRU_RMT_VEC_D_PT(30) OR LRU_RMT_VEC_D_PT(31) + ); +MQQ105:LRU_RMT_VEC_D(3) <= + (LRU_RMT_VEC_D_PT(8) OR LRU_RMT_VEC_D_PT(28) + OR LRU_RMT_VEC_D_PT(30) OR LRU_RMT_VEC_D_PT(31) + ); +MQQ106:LRU_RMT_VEC_D(4) <= + (LRU_RMT_VEC_D_PT(28) OR LRU_RMT_VEC_D_PT(30) + OR LRU_RMT_VEC_D_PT(31)); +MQQ107:LRU_RMT_VEC_D(5) <= + (LRU_RMT_VEC_D_PT(12) OR LRU_RMT_VEC_D_PT(20) + OR LRU_RMT_VEC_D_PT(30) OR LRU_RMT_VEC_D_PT(31) + ); +MQQ108:LRU_RMT_VEC_D(6) <= + (LRU_RMT_VEC_D_PT(20) OR LRU_RMT_VEC_D_PT(30) + OR LRU_RMT_VEC_D_PT(31)); +MQQ109:LRU_RMT_VEC_D(7) <= + (LRU_RMT_VEC_D_PT(4) OR LRU_RMT_VEC_D_PT(30) + OR LRU_RMT_VEC_D_PT(31)); +MQQ110:LRU_RMT_VEC_D(8) <= + (LRU_RMT_VEC_D_PT(30) OR LRU_RMT_VEC_D_PT(31) + ); +MQQ111:LRU_RMT_VEC_D(9) <= + (LRU_RMT_VEC_D_PT(14) OR LRU_RMT_VEC_D_PT(22) + OR LRU_RMT_VEC_D_PT(26) OR LRU_RMT_VEC_D_PT(31) + ); +MQQ112:LRU_RMT_VEC_D(10) <= + (LRU_RMT_VEC_D_PT(22) OR LRU_RMT_VEC_D_PT(26) + OR LRU_RMT_VEC_D_PT(31)); +MQQ113:LRU_RMT_VEC_D(11) <= + (LRU_RMT_VEC_D_PT(6) OR LRU_RMT_VEC_D_PT(26) + OR LRU_RMT_VEC_D_PT(31)); +MQQ114:LRU_RMT_VEC_D(12) <= + (LRU_RMT_VEC_D_PT(26) OR LRU_RMT_VEC_D_PT(31) + ); +MQQ115:LRU_RMT_VEC_D(13) <= + (LRU_RMT_VEC_D_PT(10) OR LRU_RMT_VEC_D_PT(18) + OR LRU_RMT_VEC_D_PT(31)); +MQQ116:LRU_RMT_VEC_D(14) <= + (LRU_RMT_VEC_D_PT(18) OR LRU_RMT_VEC_D_PT(31) + ); +MQQ117:LRU_RMT_VEC_D(15) <= + (LRU_RMT_VEC_D_PT(2) OR LRU_RMT_VEC_D_PT(31) + ); +MQQ118:LRU_RMT_VEC_D(16) <= + (LRU_RMT_VEC_D_PT(31)); +MQQ119:LRU_RMT_VEC_D(17) <= + (LRU_RMT_VEC_D_PT(15) OR LRU_RMT_VEC_D_PT(23) + OR LRU_RMT_VEC_D_PT(27) OR LRU_RMT_VEC_D_PT(29) + ); +MQQ120:LRU_RMT_VEC_D(18) <= + (LRU_RMT_VEC_D_PT(23) OR LRU_RMT_VEC_D_PT(27) + OR LRU_RMT_VEC_D_PT(29)); +MQQ121:LRU_RMT_VEC_D(19) <= + (LRU_RMT_VEC_D_PT(7) OR LRU_RMT_VEC_D_PT(27) + OR LRU_RMT_VEC_D_PT(29)); +MQQ122:LRU_RMT_VEC_D(20) <= + (LRU_RMT_VEC_D_PT(27) OR LRU_RMT_VEC_D_PT(29) + ); +MQQ123:LRU_RMT_VEC_D(21) <= + (LRU_RMT_VEC_D_PT(11) OR LRU_RMT_VEC_D_PT(19) + OR LRU_RMT_VEC_D_PT(29)); +MQQ124:LRU_RMT_VEC_D(22) <= + (LRU_RMT_VEC_D_PT(19) OR LRU_RMT_VEC_D_PT(29) + ); +MQQ125:LRU_RMT_VEC_D(23) <= + (LRU_RMT_VEC_D_PT(3) OR LRU_RMT_VEC_D_PT(29) + ); +MQQ126:LRU_RMT_VEC_D(24) <= + (LRU_RMT_VEC_D_PT(29)); +MQQ127:LRU_RMT_VEC_D(25) <= + (LRU_RMT_VEC_D_PT(13) OR LRU_RMT_VEC_D_PT(21) + OR LRU_RMT_VEC_D_PT(25)); +MQQ128:LRU_RMT_VEC_D(26) <= + (LRU_RMT_VEC_D_PT(21) OR LRU_RMT_VEC_D_PT(25) + ); +MQQ129:LRU_RMT_VEC_D(27) <= + (LRU_RMT_VEC_D_PT(5) OR LRU_RMT_VEC_D_PT(25) + ); +MQQ130:LRU_RMT_VEC_D(28) <= + (LRU_RMT_VEC_D_PT(25)); +MQQ131:LRU_RMT_VEC_D(29) <= + (LRU_RMT_VEC_D_PT(9) OR LRU_RMT_VEC_D_PT(17) + ); +MQQ132:LRU_RMT_VEC_D(30) <= + (LRU_RMT_VEC_D_PT(17)); +MQQ133:LRU_RMT_VEC_D(31) <= + (LRU_RMT_VEC_D_PT(1)); + +mmucr1_b0_cpy_d <= mmucr1_d(0); +lru_rmt_vec <= lru_rmt_vec_q; +lru_watermark_mask <= not lru_rmt_vec_q; +entry_valid_watermarked <= entry_valid_q or lru_watermark_mask; +MQQ134:LRU_SET_RESET_VEC_PT(1) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) & + ENTRY_MATCH_Q(13) & ENTRY_MATCH_Q(14) & + ENTRY_MATCH_Q(15) & ENTRY_MATCH_Q(16) & + ENTRY_MATCH_Q(17) & ENTRY_MATCH_Q(18) & + ENTRY_MATCH_Q(19) & ENTRY_MATCH_Q(20) & + ENTRY_MATCH_Q(21) & ENTRY_MATCH_Q(22) & + ENTRY_MATCH_Q(23) & ENTRY_MATCH_Q(24) & + ENTRY_MATCH_Q(25) & ENTRY_MATCH_Q(26) & + ENTRY_MATCH_Q(27) & ENTRY_MATCH_Q(28) & + ENTRY_MATCH_Q(29) & ENTRY_MATCH_Q(30) & + ENTRY_MATCH_Q(31) ) , STD_ULOGIC_VECTOR'("0011111111111111111111111111111111100000000000000000000" & +"000000000001")); +MQQ135:LRU_SET_RESET_VEC_PT(2) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) & + ENTRY_MATCH_Q(13) & ENTRY_MATCH_Q(14) & + ENTRY_MATCH_Q(15) & ENTRY_MATCH_Q(16) & + ENTRY_MATCH_Q(17) & ENTRY_MATCH_Q(18) & + ENTRY_MATCH_Q(19) & ENTRY_MATCH_Q(20) & + ENTRY_MATCH_Q(21) & ENTRY_MATCH_Q(22) & + ENTRY_MATCH_Q(23) & ENTRY_MATCH_Q(24) & + ENTRY_MATCH_Q(25) & ENTRY_MATCH_Q(26) & + ENTRY_MATCH_Q(27) & ENTRY_MATCH_Q(28) & + ENTRY_MATCH_Q(29) & ENTRY_MATCH_Q(30) + ) , STD_ULOGIC_VECTOR'("001111111111111111111111111111111110000000000000000000000000000001")); +MQQ136:LRU_SET_RESET_VEC_PT(3) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_MATCH_Q(0) & ENTRY_MATCH_Q(1) & + ENTRY_MATCH_Q(2) & ENTRY_MATCH_Q(3) & + ENTRY_MATCH_Q(4) & ENTRY_MATCH_Q(5) & + ENTRY_MATCH_Q(6) & ENTRY_MATCH_Q(7) & + ENTRY_MATCH_Q(8) & ENTRY_MATCH_Q(9) & + ENTRY_MATCH_Q(10) & ENTRY_MATCH_Q(11) & + ENTRY_MATCH_Q(12) & ENTRY_MATCH_Q(13) & + ENTRY_MATCH_Q(14) & ENTRY_MATCH_Q(15) & + ENTRY_MATCH_Q(16) & ENTRY_MATCH_Q(17) & + ENTRY_MATCH_Q(18) & ENTRY_MATCH_Q(19) & + ENTRY_MATCH_Q(20) & ENTRY_MATCH_Q(21) & + ENTRY_MATCH_Q(22) & ENTRY_MATCH_Q(23) & + ENTRY_MATCH_Q(24) & ENTRY_MATCH_Q(25) & + ENTRY_MATCH_Q(26) & ENTRY_MATCH_Q(27) & + ENTRY_MATCH_Q(28) & ENTRY_MATCH_Q(29) & + ENTRY_MATCH_Q(30) ) , STD_ULOGIC_VECTOR'("0011111111111111111111111111111111000000000000000000000" & +"0000000001")); +MQQ137:LRU_SET_RESET_VEC_PT(4) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) & + ENTRY_MATCH_Q(13) & ENTRY_MATCH_Q(14) & + ENTRY_MATCH_Q(15) & ENTRY_MATCH_Q(16) & + ENTRY_MATCH_Q(17) & ENTRY_MATCH_Q(18) & + ENTRY_MATCH_Q(19) & ENTRY_MATCH_Q(20) & + ENTRY_MATCH_Q(21) & ENTRY_MATCH_Q(22) & + ENTRY_MATCH_Q(23) & ENTRY_MATCH_Q(24) & + ENTRY_MATCH_Q(25) & ENTRY_MATCH_Q(26) & + ENTRY_MATCH_Q(27) & ENTRY_MATCH_Q(28) & + ENTRY_MATCH_Q(29) ) , STD_ULOGIC_VECTOR'("0011111111111111111111111111111111100000000000000000000" & +"0000000001")); +MQQ138:LRU_SET_RESET_VEC_PT(5) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) & + ENTRY_MATCH_Q(13) & ENTRY_MATCH_Q(14) & + ENTRY_MATCH_Q(15) & ENTRY_MATCH_Q(16) & + ENTRY_MATCH_Q(17) & ENTRY_MATCH_Q(18) & + ENTRY_MATCH_Q(19) & ENTRY_MATCH_Q(20) & + ENTRY_MATCH_Q(21) & ENTRY_MATCH_Q(22) & + ENTRY_MATCH_Q(23) & ENTRY_MATCH_Q(24) & + ENTRY_MATCH_Q(25) & ENTRY_MATCH_Q(26) & + ENTRY_MATCH_Q(27) & ENTRY_MATCH_Q(29) + ) , STD_ULOGIC_VECTOR'("00111111111111111111111111111111100000000000000000000000000001")); +MQQ139:LRU_SET_RESET_VEC_PT(6) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) & + ENTRY_MATCH_Q(13) & ENTRY_MATCH_Q(14) & + ENTRY_MATCH_Q(15) & ENTRY_MATCH_Q(16) & + ENTRY_MATCH_Q(17) & ENTRY_MATCH_Q(18) & + ENTRY_MATCH_Q(19) & ENTRY_MATCH_Q(20) & + ENTRY_MATCH_Q(21) & ENTRY_MATCH_Q(22) & + ENTRY_MATCH_Q(23) & ENTRY_MATCH_Q(24) & + ENTRY_MATCH_Q(25) & ENTRY_MATCH_Q(26) & + ENTRY_MATCH_Q(27) & ENTRY_MATCH_Q(28) + ) , STD_ULOGIC_VECTOR'("0011111111111111111111111111111111100000000000000000000000000001")); +MQQ140:LRU_SET_RESET_VEC_PT(7) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) & + ENTRY_MATCH_Q(13) & ENTRY_MATCH_Q(14) & + ENTRY_MATCH_Q(15) & ENTRY_MATCH_Q(16) & + ENTRY_MATCH_Q(17) & ENTRY_MATCH_Q(18) & + ENTRY_MATCH_Q(19) & ENTRY_MATCH_Q(20) & + ENTRY_MATCH_Q(21) & ENTRY_MATCH_Q(22) & + ENTRY_MATCH_Q(23) & ENTRY_MATCH_Q(24) & + ENTRY_MATCH_Q(25) & ENTRY_MATCH_Q(26) & + ENTRY_MATCH_Q(27) ) , STD_ULOGIC_VECTOR'("0011111111111111111111111111111111100000000000000000000" & +"00000001")); +MQQ141:LRU_SET_RESET_VEC_PT(8) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) & + ENTRY_MATCH_Q(13) & ENTRY_MATCH_Q(14) & + ENTRY_MATCH_Q(15) & ENTRY_MATCH_Q(16) & + ENTRY_MATCH_Q(17) & ENTRY_MATCH_Q(18) & + ENTRY_MATCH_Q(19) & ENTRY_MATCH_Q(20) & + ENTRY_MATCH_Q(21) & ENTRY_MATCH_Q(22) & + ENTRY_MATCH_Q(23) & ENTRY_MATCH_Q(27) + ) , STD_ULOGIC_VECTOR'("00111111111111111111111111111110000000000000000000000001")); +MQQ142:LRU_SET_RESET_VEC_PT(9) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) & + ENTRY_MATCH_Q(13) & ENTRY_MATCH_Q(14) & + ENTRY_MATCH_Q(15) & ENTRY_MATCH_Q(16) & + ENTRY_MATCH_Q(17) & ENTRY_MATCH_Q(18) & + ENTRY_MATCH_Q(19) & ENTRY_MATCH_Q(20) & + ENTRY_MATCH_Q(21) & ENTRY_MATCH_Q(22) & + ENTRY_MATCH_Q(23) & ENTRY_MATCH_Q(24) & + ENTRY_MATCH_Q(25) & ENTRY_MATCH_Q(26) + ) , STD_ULOGIC_VECTOR'("00111111111111111111111111111111111000000000000000000000000001")); +MQQ143:LRU_SET_RESET_VEC_PT(10) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) & + ENTRY_MATCH_Q(13) & ENTRY_MATCH_Q(14) & + ENTRY_MATCH_Q(15) & ENTRY_MATCH_Q(16) & + ENTRY_MATCH_Q(17) & ENTRY_MATCH_Q(18) & + ENTRY_MATCH_Q(19) & ENTRY_MATCH_Q(20) & + ENTRY_MATCH_Q(21) & ENTRY_MATCH_Q(22) & + ENTRY_MATCH_Q(23) & ENTRY_MATCH_Q(24) & + ENTRY_MATCH_Q(25) ) , STD_ULOGIC_VECTOR'("0011111111111111111111111111111111100000000000000000000" & +"000001")); +MQQ144:LRU_SET_RESET_VEC_PT(11) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) & + ENTRY_MATCH_Q(13) & ENTRY_MATCH_Q(14) & + ENTRY_MATCH_Q(15) & ENTRY_MATCH_Q(16) & + ENTRY_MATCH_Q(17) & ENTRY_MATCH_Q(18) & + ENTRY_MATCH_Q(19) & ENTRY_MATCH_Q(20) & + ENTRY_MATCH_Q(21) & ENTRY_MATCH_Q(22) & + ENTRY_MATCH_Q(23) & ENTRY_MATCH_Q(25) + ) , STD_ULOGIC_VECTOR'("001111111111111111111111111111111110000000000000000000000001")); +MQQ145:LRU_SET_RESET_VEC_PT(12) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) & + ENTRY_MATCH_Q(13) & ENTRY_MATCH_Q(14) & + ENTRY_MATCH_Q(15) & ENTRY_MATCH_Q(16) & + ENTRY_MATCH_Q(17) & ENTRY_MATCH_Q(18) & + ENTRY_MATCH_Q(19) & ENTRY_MATCH_Q(20) & + ENTRY_MATCH_Q(21) & ENTRY_MATCH_Q(22) & + ENTRY_MATCH_Q(23) & ENTRY_MATCH_Q(24) + ) , STD_ULOGIC_VECTOR'("001111111111111111111111111111111110000000000000000000000001")); +MQQ146:LRU_SET_RESET_VEC_PT(13) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) & + ENTRY_MATCH_Q(13) & ENTRY_MATCH_Q(14) & + ENTRY_MATCH_Q(15) & ENTRY_MATCH_Q(16) & + ENTRY_MATCH_Q(17) & ENTRY_MATCH_Q(18) & + ENTRY_MATCH_Q(19) & ENTRY_MATCH_Q(20) & + ENTRY_MATCH_Q(21) & ENTRY_MATCH_Q(22) & + ENTRY_MATCH_Q(23) ) , STD_ULOGIC_VECTOR'("0011111111111111111111111111111111100000000000000000000" & +"0001")); +MQQ147:LRU_SET_RESET_VEC_PT(14) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) & + ENTRY_MATCH_Q(13) & ENTRY_MATCH_Q(14) & + ENTRY_MATCH_Q(15) & ENTRY_MATCH_Q(23) + ) , STD_ULOGIC_VECTOR'("00111111111111111111111111100000000000000001")); +MQQ148:LRU_SET_RESET_VEC_PT(15) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) & + ENTRY_MATCH_Q(13) & ENTRY_MATCH_Q(14) & + ENTRY_MATCH_Q(15) & ENTRY_MATCH_Q(16) & + ENTRY_MATCH_Q(17) & ENTRY_MATCH_Q(18) & + ENTRY_MATCH_Q(19) & ENTRY_MATCH_Q(20) & + ENTRY_MATCH_Q(21) & ENTRY_MATCH_Q(22) + ) , STD_ULOGIC_VECTOR'("0011111111111111111111111111111111100000000000000000000001")); +MQQ149:LRU_SET_RESET_VEC_PT(16) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) & + ENTRY_MATCH_Q(13) & ENTRY_MATCH_Q(14) & + ENTRY_MATCH_Q(15) & ENTRY_MATCH_Q(16) & + ENTRY_MATCH_Q(17) & ENTRY_MATCH_Q(18) & + ENTRY_MATCH_Q(19) & ENTRY_MATCH_Q(20) & + ENTRY_MATCH_Q(21) ) , STD_ULOGIC_VECTOR'("0011111111111111111111111111111111100000000000000000000" & +"01")); +MQQ150:LRU_SET_RESET_VEC_PT(17) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) & + ENTRY_MATCH_Q(13) & ENTRY_MATCH_Q(14) & + ENTRY_MATCH_Q(15) & ENTRY_MATCH_Q(16) & + ENTRY_MATCH_Q(17) & ENTRY_MATCH_Q(18) & + ENTRY_MATCH_Q(19) & ENTRY_MATCH_Q(21) + ) , STD_ULOGIC_VECTOR'("00111111111111111111111111111111111000000000000000000001")); +MQQ151:LRU_SET_RESET_VEC_PT(18) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) & + ENTRY_MATCH_Q(13) & ENTRY_MATCH_Q(14) & + ENTRY_MATCH_Q(15) & ENTRY_MATCH_Q(16) & + ENTRY_MATCH_Q(17) & ENTRY_MATCH_Q(18) & + ENTRY_MATCH_Q(19) & ENTRY_MATCH_Q(20) + ) , STD_ULOGIC_VECTOR'("00111111111111111111111111111111111000000000000000000001")); +MQQ152:LRU_SET_RESET_VEC_PT(19) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) & + ENTRY_MATCH_Q(13) & ENTRY_MATCH_Q(14) & + ENTRY_MATCH_Q(15) & ENTRY_MATCH_Q(16) & + ENTRY_MATCH_Q(17) & ENTRY_MATCH_Q(18) & + ENTRY_MATCH_Q(19) ) , STD_ULOGIC_VECTOR'("0011111111111111111111111111111111100000000000000000001") +); +MQQ153:LRU_SET_RESET_VEC_PT(20) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) & + ENTRY_MATCH_Q(13) & ENTRY_MATCH_Q(14) & + ENTRY_MATCH_Q(15) & ENTRY_MATCH_Q(19) + ) , STD_ULOGIC_VECTOR'("0011111111111111111111111111111111100000000000000001")); +MQQ154:LRU_SET_RESET_VEC_PT(21) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) & + ENTRY_MATCH_Q(13) & ENTRY_MATCH_Q(14) & + ENTRY_MATCH_Q(15) & ENTRY_MATCH_Q(16) & + ENTRY_MATCH_Q(17) & ENTRY_MATCH_Q(18) + ) , STD_ULOGIC_VECTOR'("001111111111111111111111111111111110000000000000000001")); +MQQ155:LRU_SET_RESET_VEC_PT(22) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) & + ENTRY_MATCH_Q(13) & ENTRY_MATCH_Q(14) & + ENTRY_MATCH_Q(15) & ENTRY_MATCH_Q(16) & + ENTRY_MATCH_Q(17) ) , STD_ULOGIC_VECTOR'("00111111111111111111111111111111111000000000000000001") +); +MQQ156:LRU_SET_RESET_VEC_PT(23) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) & + ENTRY_MATCH_Q(13) & ENTRY_MATCH_Q(14) & + ENTRY_MATCH_Q(15) & ENTRY_MATCH_Q(17) + ) , STD_ULOGIC_VECTOR'("0011111111111111111111111111111111100000000000000001")); +MQQ157:LRU_SET_RESET_VEC_PT(24) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) & + ENTRY_MATCH_Q(13) & ENTRY_MATCH_Q(14) & + ENTRY_MATCH_Q(15) & ENTRY_MATCH_Q(16) + ) , STD_ULOGIC_VECTOR'("0011111111111111111111111111111111100000000000000001")); +MQQ158:LRU_SET_RESET_VEC_PT(25) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) & + ENTRY_MATCH_Q(13) & ENTRY_MATCH_Q(14) & + ENTRY_MATCH_Q(15) & ENTRY_MATCH_Q(16) + ) , STD_ULOGIC_VECTOR'("001111111111111111100000000000000001")); +MQQ159:LRU_SET_RESET_VEC_PT(26) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) & + ENTRY_MATCH_Q(13) & ENTRY_MATCH_Q(14) & + ENTRY_MATCH_Q(15) ) , STD_ULOGIC_VECTOR'("001111111111111111111111111111111110000000000000001")); +MQQ160:LRU_SET_RESET_VEC_PT(27) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_MATCH_Q(15) + ) , STD_ULOGIC_VECTOR'("00111111111111111111")); +MQQ161:LRU_SET_RESET_VEC_PT(28) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) & + ENTRY_MATCH_Q(13) & ENTRY_MATCH_Q(14) + ) , STD_ULOGIC_VECTOR'("00111111111111111111111111111111111000000000000001")); +MQQ162:LRU_SET_RESET_VEC_PT(29) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) & + ENTRY_MATCH_Q(13) ) , STD_ULOGIC_VECTOR'("0011111111111111111111111111111111100000000000001")); +MQQ163:LRU_SET_RESET_VEC_PT(30) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(13) + ) , STD_ULOGIC_VECTOR'("001111111111111111111111111111111110000000000001")); +MQQ164:LRU_SET_RESET_VEC_PT(31) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) + ) , STD_ULOGIC_VECTOR'("001111111111111111111111111111111110000000000001")); +MQQ165:LRU_SET_RESET_VEC_PT(32) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) ) , STD_ULOGIC_VECTOR'("00111111111111111111111111111111111000000000001")); +MQQ166:LRU_SET_RESET_VEC_PT(33) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(11) + ) , STD_ULOGIC_VECTOR'("00111111111111111111111111111111111000000001")); +MQQ167:LRU_SET_RESET_VEC_PT(34) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) + ) , STD_ULOGIC_VECTOR'("0011111111111111111111111111111111100000000001")); +MQQ168:LRU_SET_RESET_VEC_PT(35) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) ) , STD_ULOGIC_VECTOR'("001111111111111111111111111111111110000000001")); +MQQ169:LRU_SET_RESET_VEC_PT(36) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(9) + ) , STD_ULOGIC_VECTOR'("00111111111111111111111111111111111000000001")); +MQQ170:LRU_SET_RESET_VEC_PT(37) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) + ) , STD_ULOGIC_VECTOR'("00111111111111111111111111111111111000000001")); +MQQ171:LRU_SET_RESET_VEC_PT(38) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) + ) , STD_ULOGIC_VECTOR'("001111111111111111111111111000000001")); +MQQ172:LRU_SET_RESET_VEC_PT(39) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) ) , STD_ULOGIC_VECTOR'("0011111111111111111111111111111111100000001")); +MQQ173:LRU_SET_RESET_VEC_PT(40) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(7) + ) , STD_ULOGIC_VECTOR'("001111111111111111111111111111111111")); +MQQ174:LRU_SET_RESET_VEC_PT(41) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) + ) , STD_ULOGIC_VECTOR'("001111111111111111111111111111111110000001")); +MQQ175:LRU_SET_RESET_VEC_PT(42) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) ) , STD_ULOGIC_VECTOR'("00111111111111111111111111111111111000001")); +MQQ176:LRU_SET_RESET_VEC_PT(43) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(5) + ) , STD_ULOGIC_VECTOR'("0011111111111111111111111111111111100001")); +MQQ177:LRU_SET_RESET_VEC_PT(44) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) + ) , STD_ULOGIC_VECTOR'("0011111111111111111111111111111111100001")); +MQQ178:LRU_SET_RESET_VEC_PT(45) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) + ) , STD_ULOGIC_VECTOR'("001111111111111111111111111111100001")); +MQQ179:LRU_SET_RESET_VEC_PT(46) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) ) , STD_ULOGIC_VECTOR'("001111111111111111111111111111111110001")); +MQQ180:LRU_SET_RESET_VEC_PT(47) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(3) + ) , STD_ULOGIC_VECTOR'("001111111111111111111111111111111111")); +MQQ181:LRU_SET_RESET_VEC_PT(48) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) + ) , STD_ULOGIC_VECTOR'("00111111111111111111111111111111111001")); +MQQ182:LRU_SET_RESET_VEC_PT(49) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) + ) , STD_ULOGIC_VECTOR'("001111111111111111111111111111111001")); +MQQ183:LRU_SET_RESET_VEC_PT(50) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + ENTRY_MATCH_Q(0) & ENTRY_MATCH_Q(1) + ) , STD_ULOGIC_VECTOR'("001111111111111111111111111111111101")); +MQQ184:LRU_SET_RESET_VEC_PT(51) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(1) + ) , STD_ULOGIC_VECTOR'("001111111111111111111111111111111111")); +MQQ185:LRU_SET_RESET_VEC_PT(52) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) + ) , STD_ULOGIC_VECTOR'("001111111111111111111111111111111111")); +MQQ186:LRU_SET_RESET_VEC_PT(53) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + LRU_Q(1) & LRU_Q(3) & + LRU_Q(7) & LRU_Q(15) & + LRU_Q(31) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111111110")); +MQQ187:LRU_SET_RESET_VEC_PT(54) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(3) & + LRU_Q(7) & LRU_Q(15) & + LRU_Q(31) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111111111")); +MQQ188:LRU_SET_RESET_VEC_PT(55) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(3) & + LRU_Q(7) & LRU_Q(15) & + LRU_Q(30) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111111100")); +MQQ189:LRU_SET_RESET_VEC_PT(56) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(3) & + LRU_Q(7) & LRU_Q(15) & + LRU_Q(30) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111111101")); +MQQ190:LRU_SET_RESET_VEC_PT(57) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(3) & + LRU_Q(7) & LRU_Q(14) & + LRU_Q(29) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111111010")); +MQQ191:LRU_SET_RESET_VEC_PT(58) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(3) & + LRU_Q(7) & LRU_Q(14) & + LRU_Q(29) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111111011")); +MQQ192:LRU_SET_RESET_VEC_PT(59) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(3) & + LRU_Q(7) & LRU_Q(14) & + LRU_Q(28) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111111000")); +MQQ193:LRU_SET_RESET_VEC_PT(60) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(3) & + LRU_Q(7) & LRU_Q(14) & + LRU_Q(28) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111111001")); +MQQ194:LRU_SET_RESET_VEC_PT(61) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(3) & + LRU_Q(6) & LRU_Q(13) & + LRU_Q(27) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111110110")); +MQQ195:LRU_SET_RESET_VEC_PT(62) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(3) & + LRU_Q(6) & LRU_Q(13) & + LRU_Q(27) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111110111")); +MQQ196:LRU_SET_RESET_VEC_PT(63) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(3) & + LRU_Q(6) & LRU_Q(13) & + LRU_Q(26) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111110100")); +MQQ197:LRU_SET_RESET_VEC_PT(64) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(3) & + LRU_Q(6) & LRU_Q(13) & + LRU_Q(26) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111110101")); +MQQ198:LRU_SET_RESET_VEC_PT(65) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(3) & + LRU_Q(6) & LRU_Q(12) & + LRU_Q(25) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111110010")); +MQQ199:LRU_SET_RESET_VEC_PT(66) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(3) & + LRU_Q(6) & LRU_Q(12) & + LRU_Q(25) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111110011")); +MQQ200:LRU_SET_RESET_VEC_PT(67) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(3) & + LRU_Q(6) & LRU_Q(12) & + LRU_Q(24) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111110000")); +MQQ201:LRU_SET_RESET_VEC_PT(68) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(3) & + LRU_Q(6) & LRU_Q(12) & + LRU_Q(24) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111110001")); +MQQ202:LRU_SET_RESET_VEC_PT(69) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(2) & + LRU_Q(5) & LRU_Q(11) & + LRU_Q(23) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111101110")); +MQQ203:LRU_SET_RESET_VEC_PT(70) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(2) & + LRU_Q(5) & LRU_Q(11) & + LRU_Q(23) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111101111")); +MQQ204:LRU_SET_RESET_VEC_PT(71) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(2) & + LRU_Q(5) & LRU_Q(11) & + LRU_Q(22) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111101100")); +MQQ205:LRU_SET_RESET_VEC_PT(72) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(2) & + LRU_Q(5) & LRU_Q(11) & + LRU_Q(22) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111101101")); +MQQ206:LRU_SET_RESET_VEC_PT(73) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(2) & + LRU_Q(5) & LRU_Q(10) & + LRU_Q(21) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111101010")); +MQQ207:LRU_SET_RESET_VEC_PT(74) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(2) & + LRU_Q(5) & LRU_Q(10) & + LRU_Q(21) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111101011")); +MQQ208:LRU_SET_RESET_VEC_PT(75) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(2) & + LRU_Q(5) & LRU_Q(10) & + LRU_Q(20) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111101000")); +MQQ209:LRU_SET_RESET_VEC_PT(76) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(2) & + LRU_Q(5) & LRU_Q(10) & + LRU_Q(20) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111101001")); +MQQ210:LRU_SET_RESET_VEC_PT(77) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(2) & + LRU_Q(4) & LRU_Q(9) & + LRU_Q(19) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111100110")); +MQQ211:LRU_SET_RESET_VEC_PT(78) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(2) & + LRU_Q(4) & LRU_Q(9) & + LRU_Q(19) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111100111")); +MQQ212:LRU_SET_RESET_VEC_PT(79) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(2) & + LRU_Q(4) & LRU_Q(9) & + LRU_Q(18) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111100100")); +MQQ213:LRU_SET_RESET_VEC_PT(80) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(2) & + LRU_Q(4) & LRU_Q(9) & + LRU_Q(18) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111100101")); +MQQ214:LRU_SET_RESET_VEC_PT(81) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(2) & + LRU_Q(4) & LRU_Q(8) & + LRU_Q(17) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111100010")); +MQQ215:LRU_SET_RESET_VEC_PT(82) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(2) & + LRU_Q(4) & LRU_Q(8) & + LRU_Q(17) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111100011")); +MQQ216:LRU_SET_RESET_VEC_PT(83) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(2) & + LRU_Q(4) & LRU_Q(8) & + LRU_Q(16) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111100000")); +MQQ217:LRU_SET_RESET_VEC_PT(84) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(2) & + LRU_Q(4) & LRU_Q(8) & + LRU_Q(16) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111100001")); +MQQ218:LRU_SET_RESET_VEC_PT(85) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & LRU_Q(1) & + LRU_Q(3) & LRU_Q(7) & + LRU_Q(15) ) , STD_ULOGIC_VECTOR'("11111111111111111111111111111111110")); +MQQ219:LRU_SET_RESET_VEC_PT(86) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & LRU_Q(1) & + LRU_Q(3) & LRU_Q(7) & + LRU_Q(15) ) , STD_ULOGIC_VECTOR'("11111111111111111111111111111111111")); +MQQ220:LRU_SET_RESET_VEC_PT(87) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & LRU_Q(1) & + LRU_Q(3) & LRU_Q(7) & + LRU_Q(14) ) , STD_ULOGIC_VECTOR'("11111111111111111111111111111111100")); +MQQ221:LRU_SET_RESET_VEC_PT(88) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & LRU_Q(1) & + LRU_Q(3) & LRU_Q(7) & + LRU_Q(14) ) , STD_ULOGIC_VECTOR'("11111111111111111111111111111111101")); +MQQ222:LRU_SET_RESET_VEC_PT(89) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & LRU_Q(1) & + LRU_Q(3) & LRU_Q(6) & + LRU_Q(13) ) , STD_ULOGIC_VECTOR'("11111111111111111111111111111111010")); +MQQ223:LRU_SET_RESET_VEC_PT(90) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & LRU_Q(1) & + LRU_Q(3) & LRU_Q(6) & + LRU_Q(13) ) , STD_ULOGIC_VECTOR'("11111111111111111111111111111111011")); +MQQ224:LRU_SET_RESET_VEC_PT(91) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & LRU_Q(1) & + LRU_Q(3) & LRU_Q(6) & + LRU_Q(12) ) , STD_ULOGIC_VECTOR'("11111111111111111111111111111111000")); +MQQ225:LRU_SET_RESET_VEC_PT(92) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & LRU_Q(1) & + LRU_Q(3) & LRU_Q(6) & + LRU_Q(12) ) , STD_ULOGIC_VECTOR'("11111111111111111111111111111111001")); +MQQ226:LRU_SET_RESET_VEC_PT(93) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & LRU_Q(1) & + LRU_Q(2) & LRU_Q(5) & + LRU_Q(11) ) , STD_ULOGIC_VECTOR'("11111111111111111111111111111110110")); +MQQ227:LRU_SET_RESET_VEC_PT(94) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & LRU_Q(1) & + LRU_Q(2) & LRU_Q(5) & + LRU_Q(11) ) , STD_ULOGIC_VECTOR'("11111111111111111111111111111110111")); +MQQ228:LRU_SET_RESET_VEC_PT(95) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & LRU_Q(1) & + LRU_Q(2) & LRU_Q(5) & + LRU_Q(10) ) , STD_ULOGIC_VECTOR'("11111111111111111111111111111110100")); +MQQ229:LRU_SET_RESET_VEC_PT(96) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & LRU_Q(1) & + LRU_Q(2) & LRU_Q(5) & + LRU_Q(10) ) , STD_ULOGIC_VECTOR'("11111111111111111111111111111110101")); +MQQ230:LRU_SET_RESET_VEC_PT(97) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & LRU_Q(1) & + LRU_Q(2) & LRU_Q(4) & + LRU_Q(9) ) , STD_ULOGIC_VECTOR'("11111111111111111111111111111110010")); +MQQ231:LRU_SET_RESET_VEC_PT(98) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & LRU_Q(1) & + LRU_Q(2) & LRU_Q(4) & + LRU_Q(9) ) , STD_ULOGIC_VECTOR'("11111111111111111111111111111110011")); +MQQ232:LRU_SET_RESET_VEC_PT(99) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & LRU_Q(1) & + LRU_Q(2) & LRU_Q(4) & + LRU_Q(8) ) , STD_ULOGIC_VECTOR'("11111111111111111111111111111110000")); +MQQ233:LRU_SET_RESET_VEC_PT(100) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & LRU_Q(1) & + LRU_Q(2) & LRU_Q(4) & + LRU_Q(8) ) , STD_ULOGIC_VECTOR'("11111111111111111111111111111110001")); +MQQ234:LRU_SET_RESET_VEC_PT(101) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & LRU_Q(1) & + LRU_Q(3) & LRU_Q(7) + ) , STD_ULOGIC_VECTOR'("11111111111111111111111111111110")); +MQQ235:LRU_SET_RESET_VEC_PT(102) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & LRU_Q(1) & + LRU_Q(3) & LRU_Q(7) + ) , STD_ULOGIC_VECTOR'("11111111111111111111111111111111")); +MQQ236:LRU_SET_RESET_VEC_PT(103) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & LRU_Q(1) & + LRU_Q(3) & LRU_Q(6) + ) , STD_ULOGIC_VECTOR'("11111111111111111111111111111100")); +MQQ237:LRU_SET_RESET_VEC_PT(104) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & LRU_Q(1) & + LRU_Q(3) & LRU_Q(6) + ) , STD_ULOGIC_VECTOR'("11111111111111111111111111111101")); +MQQ238:LRU_SET_RESET_VEC_PT(105) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & LRU_Q(1) & + LRU_Q(2) & LRU_Q(5) + ) , STD_ULOGIC_VECTOR'("11111111111111111111111111111010")); +MQQ239:LRU_SET_RESET_VEC_PT(106) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & LRU_Q(1) & + LRU_Q(2) & LRU_Q(5) + ) , STD_ULOGIC_VECTOR'("11111111111111111111111111111011")); +MQQ240:LRU_SET_RESET_VEC_PT(107) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & LRU_Q(1) & + LRU_Q(2) & LRU_Q(4) + ) , STD_ULOGIC_VECTOR'("11111111111111111111111111111000")); +MQQ241:LRU_SET_RESET_VEC_PT(108) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & LRU_Q(1) & + LRU_Q(2) & LRU_Q(4) + ) , STD_ULOGIC_VECTOR'("11111111111111111111111111111001")); +MQQ242:LRU_SET_RESET_VEC_PT(109) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & LRU_Q(1) & + LRU_Q(3) ) , STD_ULOGIC_VECTOR'("111111111111111111111111110")); +MQQ243:LRU_SET_RESET_VEC_PT(110) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & LRU_Q(1) & + LRU_Q(3) ) , STD_ULOGIC_VECTOR'("111111111111111111111111111")); +MQQ244:LRU_SET_RESET_VEC_PT(111) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & LRU_Q(1) & + LRU_Q(2) ) , STD_ULOGIC_VECTOR'("111111111111111111111111100")); +MQQ245:LRU_SET_RESET_VEC_PT(112) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & LRU_Q(1) & + LRU_Q(2) ) , STD_ULOGIC_VECTOR'("111111111111111111111111101")); +MQQ246:LRU_SET_RESET_VEC_PT(113) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & LRU_Q(1) + ) , STD_ULOGIC_VECTOR'("111111111111111110")); +MQQ247:LRU_SET_RESET_VEC_PT(114) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & LRU_Q(1) + ) , STD_ULOGIC_VECTOR'("111111111111111111")); +MQQ248:LRU_SET_RESET_VEC_PT(115) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) + ) , STD_ULOGIC_VECTOR'("11111111111111111111111111111110")); +MQQ249:LRU_SET_RESET_VEC_PT(116) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111110")); +MQQ250:LRU_SET_RESET_VEC_PT(117) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) + ) , STD_ULOGIC_VECTOR'("111111111111111111111111111110")); +MQQ251:LRU_SET_RESET_VEC_PT(118) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(29) ) , STD_ULOGIC_VECTOR'("11111111111111111111111111110")); +MQQ252:LRU_SET_RESET_VEC_PT(119) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) ) , STD_ULOGIC_VECTOR'("11111111111111111111111111110")); +MQQ253:LRU_SET_RESET_VEC_PT(120) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) + ) , STD_ULOGIC_VECTOR'("1111111111111111111111111110")); +MQQ254:LRU_SET_RESET_VEC_PT(121) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(27) ) , STD_ULOGIC_VECTOR'("1111111111111111111111110")); +MQQ255:LRU_SET_RESET_VEC_PT(122) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) ) , STD_ULOGIC_VECTOR'("111111111111111111111111110")); +MQQ256:LRU_SET_RESET_VEC_PT(123) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) + ) , STD_ULOGIC_VECTOR'("11111111111111111111111110")); +MQQ257:LRU_SET_RESET_VEC_PT(124) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(25) ) , STD_ULOGIC_VECTOR'("1111111111111111111111110")); +MQQ258:LRU_SET_RESET_VEC_PT(125) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) ) , STD_ULOGIC_VECTOR'("1111111111111111111111110")); +MQQ259:LRU_SET_RESET_VEC_PT(126) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) + ) , STD_ULOGIC_VECTOR'("111111111111111111111110")); +MQQ260:LRU_SET_RESET_VEC_PT(127) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(23) ) , STD_ULOGIC_VECTOR'("11111111111111110")); +MQQ261:LRU_SET_RESET_VEC_PT(128) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) ) , STD_ULOGIC_VECTOR'("11111111111111111111110")); +MQQ262:LRU_SET_RESET_VEC_PT(129) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) + ) , STD_ULOGIC_VECTOR'("1111111111111111111110")); +MQQ263:LRU_SET_RESET_VEC_PT(130) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(21) ) , STD_ULOGIC_VECTOR'("111111111111111111110")); +MQQ264:LRU_SET_RESET_VEC_PT(131) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) ) , STD_ULOGIC_VECTOR'("111111111111111111110")); +MQQ265:LRU_SET_RESET_VEC_PT(132) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) + ) , STD_ULOGIC_VECTOR'("11111111111111111110")); +MQQ266:LRU_SET_RESET_VEC_PT(133) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(19) ) , STD_ULOGIC_VECTOR'("11111111111111110")); +MQQ267:LRU_SET_RESET_VEC_PT(134) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) ) , STD_ULOGIC_VECTOR'("1111111111111111110")); +MQQ268:LRU_SET_RESET_VEC_PT(135) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) + ) , STD_ULOGIC_VECTOR'("111111111111111110")); +MQQ269:LRU_SET_RESET_VEC_PT(136) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(17) ) , STD_ULOGIC_VECTOR'("11111111111111110")); +MQQ270:LRU_SET_RESET_VEC_PT(137) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) ) , STD_ULOGIC_VECTOR'("11111111111111110")); +MQQ271:LRU_SET_RESET_VEC_PT(138) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) + ) , STD_ULOGIC_VECTOR'("1111111111111110")); +MQQ272:LRU_SET_RESET_VEC_PT(139) <= + Eq(( ENTRY_VALID_WATERMARKED(15) ) , STD_ULOGIC'('0')); +MQQ273:LRU_SET_RESET_VEC_PT(140) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) ) , STD_ULOGIC_VECTOR'("111111111111110")); +MQQ274:LRU_SET_RESET_VEC_PT(141) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) + ) , STD_ULOGIC_VECTOR'("11111111111110")); +MQQ275:LRU_SET_RESET_VEC_PT(142) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(13) ) , STD_ULOGIC_VECTOR'("1111111111110")); +MQQ276:LRU_SET_RESET_VEC_PT(143) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) ) , STD_ULOGIC_VECTOR'("1111111111110")); +MQQ277:LRU_SET_RESET_VEC_PT(144) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) + ) , STD_ULOGIC_VECTOR'("111111111110")); +MQQ278:LRU_SET_RESET_VEC_PT(145) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(11) ) , STD_ULOGIC_VECTOR'("111111110")); +MQQ279:LRU_SET_RESET_VEC_PT(146) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) ) , STD_ULOGIC_VECTOR'("11111111110")); +MQQ280:LRU_SET_RESET_VEC_PT(147) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) + ) , STD_ULOGIC_VECTOR'("1111111110")); +MQQ281:LRU_SET_RESET_VEC_PT(148) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(9) ) , STD_ULOGIC_VECTOR'("111111110")); +MQQ282:LRU_SET_RESET_VEC_PT(149) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) ) , STD_ULOGIC_VECTOR'("111111110")); +MQQ283:LRU_SET_RESET_VEC_PT(150) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) + ) , STD_ULOGIC_VECTOR'("11111110")); +MQQ284:LRU_SET_RESET_VEC_PT(151) <= + Eq(( ENTRY_VALID_WATERMARKED(7) ) , STD_ULOGIC'('0')); +MQQ285:LRU_SET_RESET_VEC_PT(152) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) ) , STD_ULOGIC_VECTOR'("1111110")); +MQQ286:LRU_SET_RESET_VEC_PT(153) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) + ) , STD_ULOGIC_VECTOR'("111110")); +MQQ287:LRU_SET_RESET_VEC_PT(154) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(5) ) , STD_ULOGIC_VECTOR'("11110")); +MQQ288:LRU_SET_RESET_VEC_PT(155) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) ) , STD_ULOGIC_VECTOR'("11110")); +MQQ289:LRU_SET_RESET_VEC_PT(156) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) + ) , STD_ULOGIC_VECTOR'("1110")); +MQQ290:LRU_SET_RESET_VEC_PT(157) <= + Eq(( ENTRY_VALID_WATERMARKED(3) ) , STD_ULOGIC'('0')); +MQQ291:LRU_SET_RESET_VEC_PT(158) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) ) , STD_ULOGIC_VECTOR'("110")); +MQQ292:LRU_SET_RESET_VEC_PT(159) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) + ) , STD_ULOGIC_VECTOR'("10")); +MQQ293:LRU_SET_RESET_VEC_PT(160) <= + Eq(( ENTRY_VALID_WATERMARKED(1) ) , STD_ULOGIC'('0')); +MQQ294:LRU_SET_RESET_VEC_PT(161) <= + Eq(( ENTRY_VALID_WATERMARKED(0) ) , STD_ULOGIC'('0')); +MQQ295:LRU_RESET_VEC(1) <= + (LRU_SET_RESET_VEC_PT(1) OR LRU_SET_RESET_VEC_PT(2) + OR LRU_SET_RESET_VEC_PT(4) OR LRU_SET_RESET_VEC_PT(6) + OR LRU_SET_RESET_VEC_PT(7) OR LRU_SET_RESET_VEC_PT(9) + OR LRU_SET_RESET_VEC_PT(10) OR LRU_SET_RESET_VEC_PT(12) + OR LRU_SET_RESET_VEC_PT(13) OR LRU_SET_RESET_VEC_PT(15) + OR LRU_SET_RESET_VEC_PT(16) OR LRU_SET_RESET_VEC_PT(18) + OR LRU_SET_RESET_VEC_PT(19) OR LRU_SET_RESET_VEC_PT(21) + OR LRU_SET_RESET_VEC_PT(22) OR LRU_SET_RESET_VEC_PT(25) + OR LRU_SET_RESET_VEC_PT(114) OR LRU_SET_RESET_VEC_PT(139) + OR LRU_SET_RESET_VEC_PT(140) OR LRU_SET_RESET_VEC_PT(142) + OR LRU_SET_RESET_VEC_PT(143) OR LRU_SET_RESET_VEC_PT(145) + OR LRU_SET_RESET_VEC_PT(146) OR LRU_SET_RESET_VEC_PT(148) + OR LRU_SET_RESET_VEC_PT(149) OR LRU_SET_RESET_VEC_PT(151) + OR LRU_SET_RESET_VEC_PT(152) OR LRU_SET_RESET_VEC_PT(154) + OR LRU_SET_RESET_VEC_PT(155) OR LRU_SET_RESET_VEC_PT(157) + OR LRU_SET_RESET_VEC_PT(158) OR LRU_SET_RESET_VEC_PT(160) + OR LRU_SET_RESET_VEC_PT(161)); +MQQ296:LRU_RESET_VEC(2) <= + (LRU_SET_RESET_VEC_PT(26) OR LRU_SET_RESET_VEC_PT(28) + OR LRU_SET_RESET_VEC_PT(29) OR LRU_SET_RESET_VEC_PT(31) + OR LRU_SET_RESET_VEC_PT(32) OR LRU_SET_RESET_VEC_PT(34) + OR LRU_SET_RESET_VEC_PT(35) OR LRU_SET_RESET_VEC_PT(38) + OR LRU_SET_RESET_VEC_PT(112) OR LRU_SET_RESET_VEC_PT(151) + OR LRU_SET_RESET_VEC_PT(152) OR LRU_SET_RESET_VEC_PT(154) + OR LRU_SET_RESET_VEC_PT(155) OR LRU_SET_RESET_VEC_PT(157) + OR LRU_SET_RESET_VEC_PT(158) OR LRU_SET_RESET_VEC_PT(160) + OR LRU_SET_RESET_VEC_PT(161)); +MQQ297:LRU_RESET_VEC(3) <= + (LRU_SET_RESET_VEC_PT(1) OR LRU_SET_RESET_VEC_PT(2) + OR LRU_SET_RESET_VEC_PT(4) OR LRU_SET_RESET_VEC_PT(6) + OR LRU_SET_RESET_VEC_PT(7) OR LRU_SET_RESET_VEC_PT(9) + OR LRU_SET_RESET_VEC_PT(10) OR LRU_SET_RESET_VEC_PT(12) + OR LRU_SET_RESET_VEC_PT(110) OR LRU_SET_RESET_VEC_PT(127) + OR LRU_SET_RESET_VEC_PT(128) OR LRU_SET_RESET_VEC_PT(130) + OR LRU_SET_RESET_VEC_PT(131) OR LRU_SET_RESET_VEC_PT(133) + OR LRU_SET_RESET_VEC_PT(134) OR LRU_SET_RESET_VEC_PT(136) + OR LRU_SET_RESET_VEC_PT(137)); +MQQ298:LRU_RESET_VEC(4) <= + (LRU_SET_RESET_VEC_PT(39) OR LRU_SET_RESET_VEC_PT(41) + OR LRU_SET_RESET_VEC_PT(42) OR LRU_SET_RESET_VEC_PT(45) + OR LRU_SET_RESET_VEC_PT(108) OR LRU_SET_RESET_VEC_PT(157) + OR LRU_SET_RESET_VEC_PT(158) OR LRU_SET_RESET_VEC_PT(160) + OR LRU_SET_RESET_VEC_PT(161)); +MQQ299:LRU_RESET_VEC(5) <= + (LRU_SET_RESET_VEC_PT(26) OR LRU_SET_RESET_VEC_PT(28) + OR LRU_SET_RESET_VEC_PT(29) OR LRU_SET_RESET_VEC_PT(31) + OR LRU_SET_RESET_VEC_PT(106) OR LRU_SET_RESET_VEC_PT(145) + OR LRU_SET_RESET_VEC_PT(146) OR LRU_SET_RESET_VEC_PT(148) + OR LRU_SET_RESET_VEC_PT(149)); +MQQ300:LRU_RESET_VEC(6) <= + (LRU_SET_RESET_VEC_PT(13) OR LRU_SET_RESET_VEC_PT(15) + OR LRU_SET_RESET_VEC_PT(16) OR LRU_SET_RESET_VEC_PT(18) + OR LRU_SET_RESET_VEC_PT(104) OR LRU_SET_RESET_VEC_PT(133) + OR LRU_SET_RESET_VEC_PT(134) OR LRU_SET_RESET_VEC_PT(136) + OR LRU_SET_RESET_VEC_PT(137)); +MQQ301:LRU_RESET_VEC(7) <= + (LRU_SET_RESET_VEC_PT(1) OR LRU_SET_RESET_VEC_PT(2) + OR LRU_SET_RESET_VEC_PT(4) OR LRU_SET_RESET_VEC_PT(6) + OR LRU_SET_RESET_VEC_PT(102) OR LRU_SET_RESET_VEC_PT(121) + OR LRU_SET_RESET_VEC_PT(122) OR LRU_SET_RESET_VEC_PT(124) + OR LRU_SET_RESET_VEC_PT(125)); +MQQ302:LRU_RESET_VEC(8) <= + (LRU_SET_RESET_VEC_PT(46) OR LRU_SET_RESET_VEC_PT(49) + OR LRU_SET_RESET_VEC_PT(100) OR LRU_SET_RESET_VEC_PT(160) + OR LRU_SET_RESET_VEC_PT(161)); +MQQ303:LRU_RESET_VEC(9) <= + (LRU_SET_RESET_VEC_PT(39) OR LRU_SET_RESET_VEC_PT(41) + OR LRU_SET_RESET_VEC_PT(98) OR LRU_SET_RESET_VEC_PT(154) + OR LRU_SET_RESET_VEC_PT(155)); +MQQ304:LRU_RESET_VEC(10) <= + (LRU_SET_RESET_VEC_PT(32) OR LRU_SET_RESET_VEC_PT(34) + OR LRU_SET_RESET_VEC_PT(96) OR LRU_SET_RESET_VEC_PT(148) + OR LRU_SET_RESET_VEC_PT(149)); +MQQ305:LRU_RESET_VEC(11) <= + (LRU_SET_RESET_VEC_PT(26) OR LRU_SET_RESET_VEC_PT(28) + OR LRU_SET_RESET_VEC_PT(94) OR LRU_SET_RESET_VEC_PT(142) + OR LRU_SET_RESET_VEC_PT(143)); +MQQ306:LRU_RESET_VEC(12) <= + (LRU_SET_RESET_VEC_PT(19) OR LRU_SET_RESET_VEC_PT(21) + OR LRU_SET_RESET_VEC_PT(92) OR LRU_SET_RESET_VEC_PT(136) + OR LRU_SET_RESET_VEC_PT(137)); +MQQ307:LRU_RESET_VEC(13) <= + (LRU_SET_RESET_VEC_PT(13) OR LRU_SET_RESET_VEC_PT(15) + OR LRU_SET_RESET_VEC_PT(90) OR LRU_SET_RESET_VEC_PT(130) + OR LRU_SET_RESET_VEC_PT(131)); +MQQ308:LRU_RESET_VEC(14) <= + (LRU_SET_RESET_VEC_PT(7) OR LRU_SET_RESET_VEC_PT(9) + OR LRU_SET_RESET_VEC_PT(88) OR LRU_SET_RESET_VEC_PT(124) + OR LRU_SET_RESET_VEC_PT(125)); +MQQ309:LRU_RESET_VEC(15) <= + (LRU_SET_RESET_VEC_PT(1) OR LRU_SET_RESET_VEC_PT(2) + OR LRU_SET_RESET_VEC_PT(86) OR LRU_SET_RESET_VEC_PT(118) + OR LRU_SET_RESET_VEC_PT(119)); +MQQ310:LRU_RESET_VEC(16) <= + (LRU_SET_RESET_VEC_PT(50) OR LRU_SET_RESET_VEC_PT(84) + OR LRU_SET_RESET_VEC_PT(161)); +MQQ311:LRU_RESET_VEC(17) <= + (LRU_SET_RESET_VEC_PT(46) OR LRU_SET_RESET_VEC_PT(82) + OR LRU_SET_RESET_VEC_PT(158)); +MQQ312:LRU_RESET_VEC(18) <= + (LRU_SET_RESET_VEC_PT(42) OR LRU_SET_RESET_VEC_PT(80) + OR LRU_SET_RESET_VEC_PT(155)); +MQQ313:LRU_RESET_VEC(19) <= + (LRU_SET_RESET_VEC_PT(39) OR LRU_SET_RESET_VEC_PT(78) + OR LRU_SET_RESET_VEC_PT(152)); +MQQ314:LRU_RESET_VEC(20) <= + (LRU_SET_RESET_VEC_PT(35) OR LRU_SET_RESET_VEC_PT(76) + OR LRU_SET_RESET_VEC_PT(149)); +MQQ315:LRU_RESET_VEC(21) <= + (LRU_SET_RESET_VEC_PT(32) OR LRU_SET_RESET_VEC_PT(74) + OR LRU_SET_RESET_VEC_PT(146)); +MQQ316:LRU_RESET_VEC(22) <= + (LRU_SET_RESET_VEC_PT(29) OR LRU_SET_RESET_VEC_PT(72) + OR LRU_SET_RESET_VEC_PT(143)); +MQQ317:LRU_RESET_VEC(23) <= + (LRU_SET_RESET_VEC_PT(26) OR LRU_SET_RESET_VEC_PT(70) + OR LRU_SET_RESET_VEC_PT(140)); +MQQ318:LRU_RESET_VEC(24) <= + (LRU_SET_RESET_VEC_PT(22) OR LRU_SET_RESET_VEC_PT(68) + OR LRU_SET_RESET_VEC_PT(137)); +MQQ319:LRU_RESET_VEC(25) <= + (LRU_SET_RESET_VEC_PT(19) OR LRU_SET_RESET_VEC_PT(66) + OR LRU_SET_RESET_VEC_PT(134)); +MQQ320:LRU_RESET_VEC(26) <= + (LRU_SET_RESET_VEC_PT(16) OR LRU_SET_RESET_VEC_PT(64) + OR LRU_SET_RESET_VEC_PT(131)); +MQQ321:LRU_RESET_VEC(27) <= + (LRU_SET_RESET_VEC_PT(13) OR LRU_SET_RESET_VEC_PT(62) + OR LRU_SET_RESET_VEC_PT(128)); +MQQ322:LRU_RESET_VEC(28) <= + (LRU_SET_RESET_VEC_PT(10) OR LRU_SET_RESET_VEC_PT(60) + OR LRU_SET_RESET_VEC_PT(125)); +MQQ323:LRU_RESET_VEC(29) <= + (LRU_SET_RESET_VEC_PT(7) OR LRU_SET_RESET_VEC_PT(58) + OR LRU_SET_RESET_VEC_PT(122)); +MQQ324:LRU_RESET_VEC(30) <= + (LRU_SET_RESET_VEC_PT(4) OR LRU_SET_RESET_VEC_PT(56) + OR LRU_SET_RESET_VEC_PT(119)); +MQQ325:LRU_RESET_VEC(31) <= + (LRU_SET_RESET_VEC_PT(1) OR LRU_SET_RESET_VEC_PT(54) + OR LRU_SET_RESET_VEC_PT(116)); +MQQ326:LRU_SET_VEC(1) <= + (LRU_SET_RESET_VEC_PT(27) OR LRU_SET_RESET_VEC_PT(28) + OR LRU_SET_RESET_VEC_PT(30) OR LRU_SET_RESET_VEC_PT(31) + OR LRU_SET_RESET_VEC_PT(33) OR LRU_SET_RESET_VEC_PT(34) + OR LRU_SET_RESET_VEC_PT(36) OR LRU_SET_RESET_VEC_PT(37) + OR LRU_SET_RESET_VEC_PT(40) OR LRU_SET_RESET_VEC_PT(41) + OR LRU_SET_RESET_VEC_PT(43) OR LRU_SET_RESET_VEC_PT(44) + OR LRU_SET_RESET_VEC_PT(47) OR LRU_SET_RESET_VEC_PT(48) + OR LRU_SET_RESET_VEC_PT(51) OR LRU_SET_RESET_VEC_PT(52) + OR LRU_SET_RESET_VEC_PT(113) OR LRU_SET_RESET_VEC_PT(115) + OR LRU_SET_RESET_VEC_PT(116) OR LRU_SET_RESET_VEC_PT(117) + OR LRU_SET_RESET_VEC_PT(119) OR LRU_SET_RESET_VEC_PT(120) + OR LRU_SET_RESET_VEC_PT(122) OR LRU_SET_RESET_VEC_PT(123) + OR LRU_SET_RESET_VEC_PT(125) OR LRU_SET_RESET_VEC_PT(126) + OR LRU_SET_RESET_VEC_PT(128) OR LRU_SET_RESET_VEC_PT(129) + OR LRU_SET_RESET_VEC_PT(131) OR LRU_SET_RESET_VEC_PT(132) + OR LRU_SET_RESET_VEC_PT(134) OR LRU_SET_RESET_VEC_PT(135) + OR LRU_SET_RESET_VEC_PT(137)); +MQQ327:LRU_SET_VEC(2) <= + (LRU_SET_RESET_VEC_PT(40) OR LRU_SET_RESET_VEC_PT(41) + OR LRU_SET_RESET_VEC_PT(43) OR LRU_SET_RESET_VEC_PT(44) + OR LRU_SET_RESET_VEC_PT(47) OR LRU_SET_RESET_VEC_PT(48) + OR LRU_SET_RESET_VEC_PT(51) OR LRU_SET_RESET_VEC_PT(52) + OR LRU_SET_RESET_VEC_PT(111) OR LRU_SET_RESET_VEC_PT(138) + OR LRU_SET_RESET_VEC_PT(140) OR LRU_SET_RESET_VEC_PT(141) + OR LRU_SET_RESET_VEC_PT(143) OR LRU_SET_RESET_VEC_PT(144) + OR LRU_SET_RESET_VEC_PT(146) OR LRU_SET_RESET_VEC_PT(147) + OR LRU_SET_RESET_VEC_PT(149)); +MQQ328:LRU_SET_VEC(3) <= + (LRU_SET_RESET_VEC_PT(14) OR LRU_SET_RESET_VEC_PT(15) + OR LRU_SET_RESET_VEC_PT(17) OR LRU_SET_RESET_VEC_PT(18) + OR LRU_SET_RESET_VEC_PT(20) OR LRU_SET_RESET_VEC_PT(21) + OR LRU_SET_RESET_VEC_PT(23) OR LRU_SET_RESET_VEC_PT(24) + OR LRU_SET_RESET_VEC_PT(109) OR LRU_SET_RESET_VEC_PT(115) + OR LRU_SET_RESET_VEC_PT(116) OR LRU_SET_RESET_VEC_PT(117) + OR LRU_SET_RESET_VEC_PT(119) OR LRU_SET_RESET_VEC_PT(120) + OR LRU_SET_RESET_VEC_PT(122) OR LRU_SET_RESET_VEC_PT(123) + OR LRU_SET_RESET_VEC_PT(125)); +MQQ329:LRU_SET_VEC(4) <= + (LRU_SET_RESET_VEC_PT(47) OR LRU_SET_RESET_VEC_PT(48) + OR LRU_SET_RESET_VEC_PT(51) OR LRU_SET_RESET_VEC_PT(52) + OR LRU_SET_RESET_VEC_PT(107) OR LRU_SET_RESET_VEC_PT(150) + OR LRU_SET_RESET_VEC_PT(152) OR LRU_SET_RESET_VEC_PT(153) + OR LRU_SET_RESET_VEC_PT(155)); +MQQ330:LRU_SET_VEC(5) <= + (LRU_SET_RESET_VEC_PT(33) OR LRU_SET_RESET_VEC_PT(34) + OR LRU_SET_RESET_VEC_PT(36) OR LRU_SET_RESET_VEC_PT(37) + OR LRU_SET_RESET_VEC_PT(105) OR LRU_SET_RESET_VEC_PT(138) + OR LRU_SET_RESET_VEC_PT(140) OR LRU_SET_RESET_VEC_PT(141) + OR LRU_SET_RESET_VEC_PT(143)); +MQQ331:LRU_SET_VEC(6) <= + (LRU_SET_RESET_VEC_PT(20) OR LRU_SET_RESET_VEC_PT(21) + OR LRU_SET_RESET_VEC_PT(23) OR LRU_SET_RESET_VEC_PT(24) + OR LRU_SET_RESET_VEC_PT(103) OR LRU_SET_RESET_VEC_PT(126) + OR LRU_SET_RESET_VEC_PT(128) OR LRU_SET_RESET_VEC_PT(129) + OR LRU_SET_RESET_VEC_PT(131)); +MQQ332:LRU_SET_VEC(7) <= + (LRU_SET_RESET_VEC_PT(8) OR LRU_SET_RESET_VEC_PT(9) + OR LRU_SET_RESET_VEC_PT(11) OR LRU_SET_RESET_VEC_PT(12) + OR LRU_SET_RESET_VEC_PT(101) OR LRU_SET_RESET_VEC_PT(115) + OR LRU_SET_RESET_VEC_PT(116) OR LRU_SET_RESET_VEC_PT(117) + OR LRU_SET_RESET_VEC_PT(119)); +MQQ333:LRU_SET_VEC(8) <= + (LRU_SET_RESET_VEC_PT(51) OR LRU_SET_RESET_VEC_PT(52) + OR LRU_SET_RESET_VEC_PT(99) OR LRU_SET_RESET_VEC_PT(156) + OR LRU_SET_RESET_VEC_PT(158)); +MQQ334:LRU_SET_VEC(9) <= + (LRU_SET_RESET_VEC_PT(43) OR LRU_SET_RESET_VEC_PT(44) + OR LRU_SET_RESET_VEC_PT(97) OR LRU_SET_RESET_VEC_PT(150) + OR LRU_SET_RESET_VEC_PT(152)); +MQQ335:LRU_SET_VEC(10) <= + (LRU_SET_RESET_VEC_PT(36) OR LRU_SET_RESET_VEC_PT(37) + OR LRU_SET_RESET_VEC_PT(95) OR LRU_SET_RESET_VEC_PT(144) + OR LRU_SET_RESET_VEC_PT(146)); +MQQ336:LRU_SET_VEC(11) <= + (LRU_SET_RESET_VEC_PT(30) OR LRU_SET_RESET_VEC_PT(31) + OR LRU_SET_RESET_VEC_PT(93) OR LRU_SET_RESET_VEC_PT(138) + OR LRU_SET_RESET_VEC_PT(140)); +MQQ337:LRU_SET_VEC(12) <= + (LRU_SET_RESET_VEC_PT(23) OR LRU_SET_RESET_VEC_PT(24) + OR LRU_SET_RESET_VEC_PT(91) OR LRU_SET_RESET_VEC_PT(132) + OR LRU_SET_RESET_VEC_PT(134)); +MQQ338:LRU_SET_VEC(13) <= + (LRU_SET_RESET_VEC_PT(17) OR LRU_SET_RESET_VEC_PT(18) + OR LRU_SET_RESET_VEC_PT(89) OR LRU_SET_RESET_VEC_PT(126) + OR LRU_SET_RESET_VEC_PT(128)); +MQQ339:LRU_SET_VEC(14) <= + (LRU_SET_RESET_VEC_PT(11) OR LRU_SET_RESET_VEC_PT(12) + OR LRU_SET_RESET_VEC_PT(87) OR LRU_SET_RESET_VEC_PT(120) + OR LRU_SET_RESET_VEC_PT(122)); +MQQ340:LRU_SET_VEC(15) <= + (LRU_SET_RESET_VEC_PT(5) OR LRU_SET_RESET_VEC_PT(6) + OR LRU_SET_RESET_VEC_PT(85) OR LRU_SET_RESET_VEC_PT(115) + OR LRU_SET_RESET_VEC_PT(116)); +MQQ341:LRU_SET_VEC(16) <= + (LRU_SET_RESET_VEC_PT(52) OR LRU_SET_RESET_VEC_PT(83) + OR LRU_SET_RESET_VEC_PT(159)); +MQQ342:LRU_SET_VEC(17) <= + (LRU_SET_RESET_VEC_PT(48) OR LRU_SET_RESET_VEC_PT(81) + OR LRU_SET_RESET_VEC_PT(156)); +MQQ343:LRU_SET_VEC(18) <= + (LRU_SET_RESET_VEC_PT(44) OR LRU_SET_RESET_VEC_PT(79) + OR LRU_SET_RESET_VEC_PT(153)); +MQQ344:LRU_SET_VEC(19) <= + (LRU_SET_RESET_VEC_PT(41) OR LRU_SET_RESET_VEC_PT(77) + OR LRU_SET_RESET_VEC_PT(150)); +MQQ345:LRU_SET_VEC(20) <= + (LRU_SET_RESET_VEC_PT(37) OR LRU_SET_RESET_VEC_PT(75) + OR LRU_SET_RESET_VEC_PT(147)); +MQQ346:LRU_SET_VEC(21) <= + (LRU_SET_RESET_VEC_PT(34) OR LRU_SET_RESET_VEC_PT(73) + OR LRU_SET_RESET_VEC_PT(144)); +MQQ347:LRU_SET_VEC(22) <= + (LRU_SET_RESET_VEC_PT(31) OR LRU_SET_RESET_VEC_PT(71) + OR LRU_SET_RESET_VEC_PT(141)); +MQQ348:LRU_SET_VEC(23) <= + (LRU_SET_RESET_VEC_PT(28) OR LRU_SET_RESET_VEC_PT(69) + OR LRU_SET_RESET_VEC_PT(138)); +MQQ349:LRU_SET_VEC(24) <= + (LRU_SET_RESET_VEC_PT(24) OR LRU_SET_RESET_VEC_PT(67) + OR LRU_SET_RESET_VEC_PT(135)); +MQQ350:LRU_SET_VEC(25) <= + (LRU_SET_RESET_VEC_PT(21) OR LRU_SET_RESET_VEC_PT(65) + OR LRU_SET_RESET_VEC_PT(132)); +MQQ351:LRU_SET_VEC(26) <= + (LRU_SET_RESET_VEC_PT(18) OR LRU_SET_RESET_VEC_PT(63) + OR LRU_SET_RESET_VEC_PT(129)); +MQQ352:LRU_SET_VEC(27) <= + (LRU_SET_RESET_VEC_PT(15) OR LRU_SET_RESET_VEC_PT(61) + OR LRU_SET_RESET_VEC_PT(126)); +MQQ353:LRU_SET_VEC(28) <= + (LRU_SET_RESET_VEC_PT(12) OR LRU_SET_RESET_VEC_PT(59) + OR LRU_SET_RESET_VEC_PT(123)); +MQQ354:LRU_SET_VEC(29) <= + (LRU_SET_RESET_VEC_PT(9) OR LRU_SET_RESET_VEC_PT(57) + OR LRU_SET_RESET_VEC_PT(120)); +MQQ355:LRU_SET_VEC(30) <= + (LRU_SET_RESET_VEC_PT(6) OR LRU_SET_RESET_VEC_PT(55) + OR LRU_SET_RESET_VEC_PT(117)); +MQQ356:LRU_SET_VEC(31) <= + (LRU_SET_RESET_VEC_PT(3) OR LRU_SET_RESET_VEC_PT(53) + OR LRU_SET_RESET_VEC_PT(115)); + +MQQ357:LRU_WAY_ENCODE_PT(1) <= + Eq(( LRU_EFF(1) & LRU_EFF(3) & + LRU_EFF(7) & LRU_EFF(15) & + LRU_EFF(31) ) , STD_ULOGIC_VECTOR'("11111")); +MQQ358:LRU_WAY_ENCODE_PT(2) <= + Eq(( LRU_EFF(1) & LRU_EFF(3) & + LRU_EFF(7) & LRU_EFF(15) & + LRU_EFF(30) ) , STD_ULOGIC_VECTOR'("11101")); +MQQ359:LRU_WAY_ENCODE_PT(3) <= + Eq(( LRU_EFF(1) & LRU_EFF(3) & + LRU_EFF(7) & LRU_EFF(14) & + LRU_EFF(29) ) , STD_ULOGIC_VECTOR'("11011")); +MQQ360:LRU_WAY_ENCODE_PT(4) <= + Eq(( LRU_EFF(1) & LRU_EFF(3) & + LRU_EFF(7) & LRU_EFF(14) & + LRU_EFF(28) ) , STD_ULOGIC_VECTOR'("11001")); +MQQ361:LRU_WAY_ENCODE_PT(5) <= + Eq(( LRU_EFF(1) & LRU_EFF(3) & + LRU_EFF(6) & LRU_EFF(13) & + LRU_EFF(27) ) , STD_ULOGIC_VECTOR'("10111")); +MQQ362:LRU_WAY_ENCODE_PT(6) <= + Eq(( LRU_EFF(1) & LRU_EFF(3) & + LRU_EFF(6) & LRU_EFF(13) & + LRU_EFF(26) ) , STD_ULOGIC_VECTOR'("10101")); +MQQ363:LRU_WAY_ENCODE_PT(7) <= + Eq(( LRU_EFF(1) & LRU_EFF(3) & + LRU_EFF(6) & LRU_EFF(12) & + LRU_EFF(25) ) , STD_ULOGIC_VECTOR'("10011")); +MQQ364:LRU_WAY_ENCODE_PT(8) <= + Eq(( LRU_EFF(1) & LRU_EFF(3) & + LRU_EFF(6) & LRU_EFF(12) & + LRU_EFF(24) ) , STD_ULOGIC_VECTOR'("10001")); +MQQ365:LRU_WAY_ENCODE_PT(9) <= + Eq(( LRU_EFF(1) & LRU_EFF(2) & + LRU_EFF(5) & LRU_EFF(11) & + LRU_EFF(23) ) , STD_ULOGIC_VECTOR'("01111")); +MQQ366:LRU_WAY_ENCODE_PT(10) <= + Eq(( LRU_EFF(1) & LRU_EFF(2) & + LRU_EFF(5) & LRU_EFF(11) & + LRU_EFF(22) ) , STD_ULOGIC_VECTOR'("01101")); +MQQ367:LRU_WAY_ENCODE_PT(11) <= + Eq(( LRU_EFF(1) & LRU_EFF(2) & + LRU_EFF(5) & LRU_EFF(10) & + LRU_EFF(21) ) , STD_ULOGIC_VECTOR'("01011")); +MQQ368:LRU_WAY_ENCODE_PT(12) <= + Eq(( LRU_EFF(1) & LRU_EFF(2) & + LRU_EFF(5) & LRU_EFF(10) & + LRU_EFF(20) ) , STD_ULOGIC_VECTOR'("01001")); +MQQ369:LRU_WAY_ENCODE_PT(13) <= + Eq(( LRU_EFF(1) & LRU_EFF(2) & + LRU_EFF(4) & LRU_EFF(9) & + LRU_EFF(19) ) , STD_ULOGIC_VECTOR'("00111")); +MQQ370:LRU_WAY_ENCODE_PT(14) <= + Eq(( LRU_EFF(1) & LRU_EFF(2) & + LRU_EFF(4) & LRU_EFF(9) & + LRU_EFF(18) ) , STD_ULOGIC_VECTOR'("00101")); +MQQ371:LRU_WAY_ENCODE_PT(15) <= + Eq(( LRU_EFF(1) & LRU_EFF(2) & + LRU_EFF(4) & LRU_EFF(8) & + LRU_EFF(17) ) , STD_ULOGIC_VECTOR'("00011")); +MQQ372:LRU_WAY_ENCODE_PT(16) <= + Eq(( LRU_EFF(1) & LRU_EFF(2) & + LRU_EFF(4) & LRU_EFF(8) & + LRU_EFF(16) ) , STD_ULOGIC_VECTOR'("00001")); +MQQ373:LRU_WAY_ENCODE_PT(17) <= + Eq(( LRU_EFF(1) & LRU_EFF(3) & + LRU_EFF(7) & LRU_EFF(15) + ) , STD_ULOGIC_VECTOR'("1111")); +MQQ374:LRU_WAY_ENCODE_PT(18) <= + Eq(( LRU_EFF(1) & LRU_EFF(3) & + LRU_EFF(7) & LRU_EFF(14) + ) , STD_ULOGIC_VECTOR'("1101")); +MQQ375:LRU_WAY_ENCODE_PT(19) <= + Eq(( LRU_EFF(1) & LRU_EFF(3) & + LRU_EFF(6) & LRU_EFF(13) + ) , STD_ULOGIC_VECTOR'("1011")); +MQQ376:LRU_WAY_ENCODE_PT(20) <= + Eq(( LRU_EFF(1) & LRU_EFF(3) & + LRU_EFF(6) & LRU_EFF(12) + ) , STD_ULOGIC_VECTOR'("1001")); +MQQ377:LRU_WAY_ENCODE_PT(21) <= + Eq(( LRU_EFF(1) & LRU_EFF(2) & + LRU_EFF(5) & LRU_EFF(11) + ) , STD_ULOGIC_VECTOR'("0111")); +MQQ378:LRU_WAY_ENCODE_PT(22) <= + Eq(( LRU_EFF(1) & LRU_EFF(2) & + LRU_EFF(5) & LRU_EFF(10) + ) , STD_ULOGIC_VECTOR'("0101")); +MQQ379:LRU_WAY_ENCODE_PT(23) <= + Eq(( LRU_EFF(1) & LRU_EFF(2) & + LRU_EFF(4) & LRU_EFF(9) + ) , STD_ULOGIC_VECTOR'("0011")); +MQQ380:LRU_WAY_ENCODE_PT(24) <= + Eq(( LRU_EFF(1) & LRU_EFF(2) & + LRU_EFF(4) & LRU_EFF(8) + ) , STD_ULOGIC_VECTOR'("0001")); +MQQ381:LRU_WAY_ENCODE_PT(25) <= + Eq(( LRU_EFF(1) & LRU_EFF(3) & + LRU_EFF(7) ) , STD_ULOGIC_VECTOR'("111")); +MQQ382:LRU_WAY_ENCODE_PT(26) <= + Eq(( LRU_EFF(1) & LRU_EFF(3) & + LRU_EFF(6) ) , STD_ULOGIC_VECTOR'("101")); +MQQ383:LRU_WAY_ENCODE_PT(27) <= + Eq(( LRU_EFF(1) & LRU_EFF(2) & + LRU_EFF(5) ) , STD_ULOGIC_VECTOR'("011")); +MQQ384:LRU_WAY_ENCODE_PT(28) <= + Eq(( LRU_EFF(1) & LRU_EFF(2) & + LRU_EFF(4) ) , STD_ULOGIC_VECTOR'("001")); +MQQ385:LRU_WAY_ENCODE_PT(29) <= + Eq(( LRU_EFF(1) & LRU_EFF(3) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ386:LRU_WAY_ENCODE_PT(30) <= + Eq(( LRU_EFF(1) & LRU_EFF(2) + ) , STD_ULOGIC_VECTOR'("01")); +MQQ387:LRU_WAY_ENCODE_PT(31) <= + Eq(( LRU_EFF(1) ) , STD_ULOGIC'('1')); +MQQ388:LRU_WAY_ENCODE(0) <= + (LRU_WAY_ENCODE_PT(31)); +MQQ389:LRU_WAY_ENCODE(1) <= + (LRU_WAY_ENCODE_PT(29) OR LRU_WAY_ENCODE_PT(30) + ); +MQQ390:LRU_WAY_ENCODE(2) <= + (LRU_WAY_ENCODE_PT(25) OR LRU_WAY_ENCODE_PT(26) + OR LRU_WAY_ENCODE_PT(27) OR LRU_WAY_ENCODE_PT(28) + ); +MQQ391:LRU_WAY_ENCODE(3) <= + (LRU_WAY_ENCODE_PT(17) OR LRU_WAY_ENCODE_PT(18) + OR LRU_WAY_ENCODE_PT(19) OR LRU_WAY_ENCODE_PT(20) + OR LRU_WAY_ENCODE_PT(21) OR LRU_WAY_ENCODE_PT(22) + OR LRU_WAY_ENCODE_PT(23) OR LRU_WAY_ENCODE_PT(24) + ); +MQQ392:LRU_WAY_ENCODE(4) <= + (LRU_WAY_ENCODE_PT(1) OR LRU_WAY_ENCODE_PT(2) + OR LRU_WAY_ENCODE_PT(3) OR LRU_WAY_ENCODE_PT(4) + OR LRU_WAY_ENCODE_PT(5) OR LRU_WAY_ENCODE_PT(6) + OR LRU_WAY_ENCODE_PT(7) OR LRU_WAY_ENCODE_PT(8) + OR LRU_WAY_ENCODE_PT(9) OR LRU_WAY_ENCODE_PT(10) + OR LRU_WAY_ENCODE_PT(11) OR LRU_WAY_ENCODE_PT(12) + OR LRU_WAY_ENCODE_PT(13) OR LRU_WAY_ENCODE_PT(14) + OR LRU_WAY_ENCODE_PT(15) OR LRU_WAY_ENCODE_PT(16) + ); + +Por_Sequencer: PROCESS (por_seq_q, init_alias, bcfg_q(0 to 106)) +BEGIN +por_wr_cam_val <= (others => '0'); +por_wr_array_val <= (others => '0'); +por_wr_cam_data <= (others => '0'); +por_wr_array_data <= (others => '0'); +por_wr_entry <= (others => '0'); +CASE por_seq_q IS + WHEN PorSeq_Idle => + por_wr_cam_val <= (others => '0'); por_wr_array_val <= (others => '0'); + por_hold_req <= (others => init_alias); + + if init_alias ='1' then + por_seq_d <= PorSeq_Stg1; + else + por_seq_d <= PorSeq_Idle; + end if; + WHEN PorSeq_Stg1 => + por_wr_cam_val <= (others => '0'); por_wr_array_val <= (others => '0'); + por_seq_d <= PorSeq_Stg2; por_hold_req <= (others => '1'); + + WHEN PorSeq_Stg2 => + por_wr_cam_val <= (others => '1'); por_wr_array_val <= (others => '1'); + por_wr_entry <= Por_Wr_Entry_Num1; + por_wr_cam_data <= bcfg_q(0 to 51) & Por_Wr_Cam_Data1(52 to 83); + por_wr_array_data <= bcfg_q(52 to 81) & Por_Wr_Array_Data1(30 to 35) & bcfg_q(82 to 85) & + Por_Wr_Array_Data1(40 to 43) & bcfg_q(86) & Por_Wr_Array_Data1(45 to 67); + por_hold_req <= (others => '1'); + por_seq_d <= PorSeq_Stg3; + + WHEN PorSeq_Stg3 => + por_wr_cam_val <= (others => '0'); por_wr_array_val <= (others => '0'); + por_hold_req <= (others => '1'); + por_seq_d <= PorSeq_Stg4; + + WHEN PorSeq_Stg4 => + por_wr_cam_val <= (others => '1'); por_wr_array_val <= (others => '1'); + por_wr_entry <= Por_Wr_Entry_Num2; + por_wr_cam_data <= Por_Wr_Cam_Data2; + por_wr_array_data <= bcfg_q(52 to 61) & bcfg_q(87 to 106) & Por_Wr_Array_Data2(30 to 35) & bcfg_q(82 to 85) & + Por_Wr_Array_Data2(40 to 43) & bcfg_q(86) & Por_Wr_Array_Data2(45 to 67); + por_hold_req <= (others => '1'); + por_seq_d <= PorSeq_Stg5; + + WHEN PorSeq_Stg5 => + por_wr_cam_val <= (others => '0'); por_wr_array_val <= (others => '0'); + por_hold_req <= (others => '1'); + por_seq_d <= PorSeq_Stg6; + + WHEN PorSeq_Stg6 => + por_wr_cam_val <= (others => '0'); por_wr_array_val <= (others => '0'); + por_hold_req <= (others => '0'); + por_seq_d <= PorSeq_Stg7; + + WHEN PorSeq_Stg7 => + por_wr_cam_val <= (others => '0'); por_wr_array_val <= (others => '0'); + por_hold_req <= (others => '0'); + if init_alias ='0' then + por_seq_d <= PorSeq_Idle; + else + por_seq_d <= PorSeq_Stg7; + end if; + + WHEN OTHERS => + por_seq_d <= PorSeq_Idle; + END CASE; +END PROCESS Por_Sequencer; +cam_pgsize(0 TO 2) <= (CAM_PgSize_1GB and (0 to 2 => Eq(ex6_data_in_q(56 to 59),WS0_PgSize_1GB))) + or (CAM_PgSize_16MB and (0 to 2 => Eq(ex6_data_in_q(56 to 59),WS0_PgSize_16MB))) + or (CAM_PgSize_1MB and (0 to 2 => Eq(ex6_data_in_q(56 to 59),WS0_PgSize_1MB))) + or (CAM_PgSize_64KB and (0 to 2 => Eq(ex6_data_in_q(56 to 59),WS0_PgSize_64KB))) + or (CAM_PgSize_4KB and (0 to 2 => not(Eq(ex6_data_in_q(56 to 59),WS0_PgSize_1GB) or + Eq(ex6_data_in_q(56 to 59),WS0_PgSize_16MB) or + Eq(ex6_data_in_q(56 to 59),WS0_PgSize_1MB) or + Eq(ex6_data_in_q(56 to 59),WS0_PgSize_64KB)))); +ws0_pgsize(0 TO 3) <= (WS0_PgSize_1GB and (0 to 3 => Eq(rd_cam_data(53 to 55),CAM_PgSize_1GB))) + or (WS0_PgSize_16MB and (0 to 3 => Eq(rd_cam_data(53 to 55),CAM_PgSize_16MB))) + or (WS0_PgSize_1MB and (0 to 3 => Eq(rd_cam_data(53 to 55),CAM_PgSize_1MB))) + or (WS0_PgSize_64KB and (0 to 3 => Eq(rd_cam_data(53 to 55),CAM_PgSize_64KB))) + or (WS0_PgSize_4KB and (0 to 3 => Eq(rd_cam_data(53 to 55),CAM_PgSize_4KB))); +rd_val <= or_reduce(ex2_valid_q) and ex2_ttype_q(0) and Eq(ex2_tlbsel_q, TlbSel_DErat); +rw_entry <= ( por_wr_entry and (0 to 4 => or_reduce(por_seq_q)) ) + or ( eptr_q and (0 to 4 => (or_reduce(tlb_rel_val_q(0 to 3)) and tlb_rel_val_q(4) and mmucr1_q(0))) ) + or ( lru_way_encode and (0 to 4 => (or_reduce(tlb_rel_val_q(0 to 3)) and tlb_rel_val_q(4) and not mmucr1_q(0))) ) + or ( eptr_q and (0 to 4 => (or_reduce(ex6_valid_q) and ex6_ttype_q(1) and Eq(ex6_tlbsel_q, TlbSel_DErat) and not tlb_rel_val_q(4) and mmucr1_q(0))) ) + or ( ex6_ra_entry_q and (0 to 4 => (or_reduce(ex6_valid_q) and ex6_ttype_q(1) and Eq(ex6_tlbsel_q, TlbSel_DErat) and not tlb_rel_val_q(4) and not mmucr1_q(0))) ) + or ( ex2_ra_entry_q and (0 to 4 => (or_reduce(ex2_valid_q) and ex2_ttype_q(0) and not(or_reduce(ex6_valid_q) and ex6_ttype_q(1) and Eq(ex6_tlbsel_q, TlbSel_DErat)) and not tlb_rel_val_q(4))) ); +wr_cam_val <= por_wr_cam_val when por_seq_q/=PorSeq_Idle + else (others => '0') when (ex6_valid_q/="0000" and ex6_ttype_q(6 to 7)/="00") + else (others => tlb_rel_data_q(eratpos_wren)) when (tlb_rel_val_q(0 to 3)/="0000" and tlb_rel_val_q(4)='1') + else (others => '1') when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' and ex6_ws_q="00" and ex6_tlbsel_q=TlbSel_DErat) + else (others => '0'); +wr_val_early <= or_reduce(por_seq_q) or + or_reduce(tlb_req_inprogress_q) or + (or_reduce(ex5_valid_q) and ex5_ttype_q(1) and Eq(ex5_ws_q,"00") and Eq(ex5_tlbsel_q,TlbSel_DErat)) or + (or_reduce(ex6_valid_q) and ex6_ttype_q(1) and Eq(ex6_ws_q,"00") and Eq(ex6_tlbsel_q,TlbSel_DErat)); +gen64_wr_cam_data: if rs_data_width = 64 generate +wr_cam_data <= ( por_wr_cam_data and (0 to 83 => (por_seq_q(0) or por_seq_q(1) or por_seq_q(2))) ) + or ( (tlb_rel_data_q(0 to 64) & tlb_rel_data_q(122 to 131) & + tlb_rel_cmpmask(0 to 3) & tlb_rel_xbitmask(0 to 3) & tlb_rel_maskpar) + and (0 to 83 => ((tlb_rel_val_q(0) or tlb_rel_val_q(1) or tlb_rel_val_q(2) or tlb_rel_val_q(3)) and tlb_rel_val_q(4))) ) + or ( ((ex6_data_in_q(0 to 31) and (0 to 31 => ex6_state_q(3))) & ex6_data_in_q(32 to 51) & ex6_data_in_q(55) & + cam_pgsize(0 to 2) & ex6_data_in_q(54) & ex6_data_in_q(60 to 63) & ex6_data_in_q(52 to 53) & + ex6_extclass_q & ex6_state_q(1 to 2) & ex6_pid_q(pid_width-8 to pid_width-1) & + ex6_data_cmpmask(0 to 3) & ex6_data_xbitmask(0 to 3) & ex6_data_maskpar) + and (0 to 83 => ((ex6_valid_q(0) or ex6_valid_q(1) or ex6_valid_q(2) or ex6_valid_q(3)) + and ex6_ttype_q(1) and not ex6_ws_q(0) and not ex6_ws_q(1) and not tlb_rel_val_q(4))) ); +end generate gen64_wr_cam_data; +gen32_wr_cam_data: if rs_data_width = 32 generate +wr_cam_data <= ( por_wr_cam_data and (0 to 83 => (por_seq_q(0) or por_seq_q(1) or por_seq_q(2))) ) + or ( (tlb_rel_data_q(0 to 64) & tlb_rel_data_q(122 to 131) & + tlb_rel_cmpmask(0 to 3) & tlb_rel_xbitmask(0 to 3) & tlb_rel_maskpar) + and (0 to 83 => ((tlb_rel_val_q(0) or tlb_rel_val_q(1) or tlb_rel_val_q(2) or tlb_rel_val_q(3)) and tlb_rel_val_q(4))) ) + or ( ((0 to 31 => '0') & ex6_data_in_q(32 to 51) & ex6_data_in_q(55) & cam_pgsize(0 to 2) & ex6_data_in_q(54) & + ex6_data_in_q(60 to 63) & ex6_data_in_q(52 to 53) & + ex6_extclass_q & ex6_state_q(1 to 2) & ex6_pid_q(pid_width-8 to pid_width-1) & + ex6_data_cmpmask(0 to 3) & ex6_data_xbitmask(0 to 3) & ex6_data_maskpar) + and (0 to 83 => ((ex6_valid_q(0) or ex6_valid_q(1) or ex6_valid_q(2) or ex6_valid_q(3)) + and ex6_ttype_q(1) and not ex6_ws_q(0) and not ex6_ws_q(1) and not tlb_rel_val_q(4))) ); +end generate gen32_wr_cam_data; +MQQ393:CAM_MASK_BITS_PT(1) <= + Eq(( EX6_DATA_IN_Q(55) & EX6_DATA_IN_Q(56) & + EX6_DATA_IN_Q(57) & EX6_DATA_IN_Q(58) & + EX6_DATA_IN_Q(59) ) , STD_ULOGIC_VECTOR'("11010")); +MQQ394:CAM_MASK_BITS_PT(2) <= + Eq(( EX6_DATA_IN_Q(56) & EX6_DATA_IN_Q(59) + ) , STD_ULOGIC_VECTOR'("00")); +MQQ395:CAM_MASK_BITS_PT(3) <= + Eq(( EX6_DATA_IN_Q(55) & EX6_DATA_IN_Q(56) & + EX6_DATA_IN_Q(57) & EX6_DATA_IN_Q(58) & + EX6_DATA_IN_Q(59) ) , STD_ULOGIC_VECTOR'("10101")); +MQQ396:CAM_MASK_BITS_PT(4) <= + Eq(( EX6_DATA_IN_Q(55) & EX6_DATA_IN_Q(56) & + EX6_DATA_IN_Q(57) & EX6_DATA_IN_Q(58) & + EX6_DATA_IN_Q(59) ) , STD_ULOGIC_VECTOR'("10011")); +MQQ397:CAM_MASK_BITS_PT(5) <= + Eq(( EX6_DATA_IN_Q(55) & EX6_DATA_IN_Q(56) & + EX6_DATA_IN_Q(57) & EX6_DATA_IN_Q(58) & + EX6_DATA_IN_Q(59) ) , STD_ULOGIC_VECTOR'("10111")); +MQQ398:CAM_MASK_BITS_PT(6) <= + Eq(( EX6_DATA_IN_Q(55) & EX6_DATA_IN_Q(56) & + EX6_DATA_IN_Q(58) & EX6_DATA_IN_Q(59) + ) , STD_ULOGIC_VECTOR'("0011")); +MQQ399:CAM_MASK_BITS_PT(7) <= + Eq(( EX6_DATA_IN_Q(56) & EX6_DATA_IN_Q(59) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ400:CAM_MASK_BITS_PT(8) <= + Eq(( EX6_DATA_IN_Q(57) & EX6_DATA_IN_Q(58) + ) , STD_ULOGIC_VECTOR'("00")); +MQQ401:CAM_MASK_BITS_PT(9) <= + Eq(( EX6_DATA_IN_Q(58) ) , STD_ULOGIC'('0')); +MQQ402:CAM_MASK_BITS_PT(10) <= + Eq(( EX6_DATA_IN_Q(56) & EX6_DATA_IN_Q(57) + ) , STD_ULOGIC_VECTOR'("00")); +MQQ403:CAM_MASK_BITS_PT(11) <= + Eq(( EX6_DATA_IN_Q(56) & EX6_DATA_IN_Q(57) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ404:CAM_MASK_BITS_PT(12) <= + Eq(( TLB_REL_DATA_Q(52) & TLB_REL_DATA_Q(55) + ) , STD_ULOGIC_VECTOR'("10")); +MQQ405:CAM_MASK_BITS_PT(13) <= + Eq(( TLB_REL_DATA_Q(52) & TLB_REL_DATA_Q(53) & + TLB_REL_DATA_Q(54) & TLB_REL_DATA_Q(55) + ) , STD_ULOGIC_VECTOR'("1111")); +MQQ406:CAM_MASK_BITS_PT(14) <= + Eq(( TLB_REL_DATA_Q(52) & TLB_REL_DATA_Q(54) & + TLB_REL_DATA_Q(55) ) , STD_ULOGIC_VECTOR'("011")); +MQQ407:CAM_MASK_BITS_PT(15) <= + Eq(( TLB_REL_DATA_Q(53) & TLB_REL_DATA_Q(54) + ) , STD_ULOGIC_VECTOR'("00")); +MQQ408:CAM_MASK_BITS_PT(16) <= + Eq(( TLB_REL_DATA_Q(52) & TLB_REL_DATA_Q(53) & + TLB_REL_DATA_Q(54) ) , STD_ULOGIC_VECTOR'("110")); +MQQ409:CAM_MASK_BITS_PT(17) <= + Eq(( TLB_REL_DATA_Q(54) ) , STD_ULOGIC'('0')); +MQQ410:CAM_MASK_BITS_PT(18) <= + Eq(( TLB_REL_DATA_Q(52) & TLB_REL_DATA_Q(53) & + TLB_REL_DATA_Q(54) ) , STD_ULOGIC_VECTOR'("101")); +MQQ411:CAM_MASK_BITS_PT(19) <= + Eq(( TLB_REL_DATA_Q(53) ) , STD_ULOGIC'('0')); +MQQ412:TLB_REL_CMPMASK(0) <= + (CAM_MASK_BITS_PT(13) OR CAM_MASK_BITS_PT(14) + OR CAM_MASK_BITS_PT(17) OR CAM_MASK_BITS_PT(18) + ); +MQQ413:TLB_REL_CMPMASK(1) <= + (CAM_MASK_BITS_PT(17) OR CAM_MASK_BITS_PT(19) + ); +MQQ414:TLB_REL_CMPMASK(2) <= + (CAM_MASK_BITS_PT(19)); +MQQ415:TLB_REL_CMPMASK(3) <= + (CAM_MASK_BITS_PT(15)); +MQQ416:TLB_REL_XBITMASK(0) <= + (CAM_MASK_BITS_PT(12)); +MQQ417:TLB_REL_XBITMASK(1) <= + (CAM_MASK_BITS_PT(13)); +MQQ418:TLB_REL_XBITMASK(2) <= + (CAM_MASK_BITS_PT(16)); +MQQ419:TLB_REL_XBITMASK(3) <= + (CAM_MASK_BITS_PT(18)); +MQQ420:TLB_REL_MASKPAR <= + (CAM_MASK_BITS_PT(12) OR CAM_MASK_BITS_PT(14) + OR CAM_MASK_BITS_PT(16)); +MQQ421:EX6_DATA_CMPMASK(0) <= + (CAM_MASK_BITS_PT(2) OR CAM_MASK_BITS_PT(4) + OR CAM_MASK_BITS_PT(5) OR CAM_MASK_BITS_PT(6) + OR CAM_MASK_BITS_PT(7) OR CAM_MASK_BITS_PT(9) + OR CAM_MASK_BITS_PT(11)); +MQQ422:EX6_DATA_CMPMASK(1) <= + (CAM_MASK_BITS_PT(2) OR CAM_MASK_BITS_PT(7) + OR CAM_MASK_BITS_PT(9) OR CAM_MASK_BITS_PT(10) + OR CAM_MASK_BITS_PT(11)); +MQQ423:EX6_DATA_CMPMASK(2) <= + (CAM_MASK_BITS_PT(2) OR CAM_MASK_BITS_PT(7) + OR CAM_MASK_BITS_PT(8) OR CAM_MASK_BITS_PT(10) + OR CAM_MASK_BITS_PT(11)); +MQQ424:EX6_DATA_CMPMASK(3) <= + (CAM_MASK_BITS_PT(2) OR CAM_MASK_BITS_PT(7) + OR CAM_MASK_BITS_PT(8) OR CAM_MASK_BITS_PT(11) + ); +MQQ425:EX6_DATA_XBITMASK(0) <= + (CAM_MASK_BITS_PT(1)); +MQQ426:EX6_DATA_XBITMASK(1) <= + (CAM_MASK_BITS_PT(5)); +MQQ427:EX6_DATA_XBITMASK(2) <= + (CAM_MASK_BITS_PT(3)); +MQQ428:EX6_DATA_XBITMASK(3) <= + (CAM_MASK_BITS_PT(4)); +MQQ429:EX6_DATA_MASKPAR <= + (CAM_MASK_BITS_PT(1) OR CAM_MASK_BITS_PT(3) + OR CAM_MASK_BITS_PT(6)); + +wr_array_val <= por_wr_array_val when por_seq_q/=PorSeq_Idle + else (others => '0') when (ex6_valid_q/="0000" and ex6_ttype_q(6 to 7)/="00") + else (others => tlb_rel_data_q(eratpos_wren)) + when (tlb_rel_val_q(0 to 3)/="0000" and tlb_rel_val_q(4)='1') + else (others => '1') when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_ws_q="00" and ex6_tlbsel_q=TlbSel_DErat) + else (others => '0'); +wr_array_data_nopar <= ( por_wr_array_data(0 to 50) and (0 to 50 => (por_seq_q(0) or por_seq_q(1) or por_seq_q(2))) ) + or ( (tlb_rel_data_q(70 to 101) & tlb_rel_data_q(103 to 121)) + and (0 to 50 => ((tlb_rel_val_q(0) or tlb_rel_val_q(1) or tlb_rel_val_q(2) or tlb_rel_val_q(3)) and tlb_rel_val_q(4))) ) + or ( (rpn_holdreg0_q(22 to 51) & rpn_holdreg0_q(16 to 17) & rpn_holdreg0_q(8 to 10) & rpn_holdreg0_q(57) & + rpn_holdreg0_q(12 to 15) & rpn_holdreg0_q(52 to 56) & rpn_holdreg0_q(58 to 63)) + and (0 to 50 => (ex6_valid_q(0) and ex6_ttype_q(1) and not ex6_ws_q(0) and not ex6_ws_q(1) and not tlb_rel_val_q(4))) ) + or ( (rpn_holdreg1_q(22 to 51) & rpn_holdreg1_q(16 to 17) & rpn_holdreg1_q(8 to 10) & rpn_holdreg1_q(57) & + rpn_holdreg1_q(12 to 15) & rpn_holdreg1_q(52 to 56) & rpn_holdreg1_q(58 to 63)) + and (0 to 50 => (ex6_valid_q(1) and ex6_ttype_q(1) and not ex6_ws_q(0) and not ex6_ws_q(1) and not tlb_rel_val_q(4))) ) + or ( (rpn_holdreg2_q(22 to 51) & rpn_holdreg2_q(16 to 17) & rpn_holdreg2_q(8 to 10) & rpn_holdreg2_q(57) & + rpn_holdreg2_q(12 to 15) & rpn_holdreg2_q(52 to 56) & rpn_holdreg2_q(58 to 63)) + and (0 to 50 => (ex6_valid_q(2) and ex6_ttype_q(1) and not ex6_ws_q(0) and not ex6_ws_q(1) and not tlb_rel_val_q(4))) ) + or ( (rpn_holdreg3_q(22 to 51) & rpn_holdreg3_q(16 to 17) & rpn_holdreg3_q(8 to 10) & rpn_holdreg3_q(57) & + rpn_holdreg3_q(12 to 15) & rpn_holdreg3_q(52 to 56) & rpn_holdreg3_q(58 to 63)) + and (0 to 50 => (ex6_valid_q(3) and ex6_ttype_q(1) and not ex6_ws_q(0) and not ex6_ws_q(1) and not tlb_rel_val_q(4))) ); +wr_array_par(51) <= xor_reduce(wr_cam_data(0 to 7)); +wr_array_par(52) <= xor_reduce(wr_cam_data(8 to 15)); +wr_array_par(53) <= xor_reduce(wr_cam_data(16 to 23)); +wr_array_par(54) <= xor_reduce(wr_cam_data(24 to 31)); +wr_array_par(55) <= xor_reduce(wr_cam_data(32 to 39)); +wr_array_par(56) <= xor_reduce(wr_cam_data(40 to 47)); +wr_array_par(57) <= xor_reduce(wr_cam_data(48 to 55)); +wr_array_par(58) <= xor_reduce(wr_cam_data(57 to 62)); +wr_array_par(59) <= xor_reduce(wr_cam_data(63 to 66)); +wr_array_par(60) <= xor_reduce(wr_cam_data(67 to 74)); +wr_array_par(61) <= xor_reduce(wr_array_data_nopar(0 to 5)); +wr_array_par(62) <= xor_reduce(wr_array_data_nopar(6 to 13)); +wr_array_par(63) <= xor_reduce(wr_array_data_nopar(14 to 21)); +wr_array_par(64) <= xor_reduce(wr_array_data_nopar(22 to 29)); +wr_array_par(65) <= xor_reduce(wr_array_data_nopar(30 to 37)); +wr_array_par(66) <= xor_reduce(wr_array_data_nopar(38 to 44)); +wr_array_par(67) <= xor_reduce(wr_array_data_nopar(45 to 50)); +wr_array_data(0 TO 50) <= wr_array_data_nopar; +wr_array_data(51 TO 67) <= (wr_array_par(51 to 60) & wr_array_par(61 to 67)) + when ((tlb_rel_val_q(0 to 3)/="0000" and tlb_rel_val_q(4)='1') or + por_seq_q/=PorSeq_Idle) + else ((wr_array_par(51) xor mmucr1_q(5)) & wr_array_par(52 to 60) & + (wr_array_par(61) xor mmucr1_q(6)) & wr_array_par(62 to 67)) + when (ex6_valid_q(0 to 3)/="0000" and ex6_ttype_q(1)='1' and ex6_ws_q="00") + else (others => '0'); +ex4_rd_data_calc_par(50) <= xor_reduce(ex4_rd_cam_data_q(75 to 82)); +ex4_rd_data_calc_par(51) <= xor_reduce(ex4_rd_cam_data_q(0 to 7)); +ex4_rd_data_calc_par(52) <= xor_reduce(ex4_rd_cam_data_q(8 to 15)); +ex4_rd_data_calc_par(53) <= xor_reduce(ex4_rd_cam_data_q(16 to 23)); +ex4_rd_data_calc_par(54) <= xor_reduce(ex4_rd_cam_data_q(24 to 31)); +ex4_rd_data_calc_par(55) <= xor_reduce(ex4_rd_cam_data_q(32 to 39)); +ex4_rd_data_calc_par(56) <= xor_reduce(ex4_rd_cam_data_q(40 to 47)); +ex4_rd_data_calc_par(57) <= xor_reduce(ex4_rd_cam_data_q(48 to 55)); +ex4_rd_data_calc_par(58) <= xor_reduce(ex4_rd_cam_data_q(57 to 62)); +ex4_rd_data_calc_par(59) <= xor_reduce(ex4_rd_cam_data_q(63 to 66)); +ex4_rd_data_calc_par(60) <= xor_reduce(ex4_rd_cam_data_q(67 to 74)); +ex4_rd_data_calc_par(61) <= xor_reduce(ex4_rd_array_data_q(0 to 5)); +ex4_rd_data_calc_par(62) <= xor_reduce(ex4_rd_array_data_q(6 to 13)); +ex4_rd_data_calc_par(63) <= xor_reduce(ex4_rd_array_data_q(14 to 21)); +ex4_rd_data_calc_par(64) <= xor_reduce(ex4_rd_array_data_q(22 to 29)); +ex4_rd_data_calc_par(65) <= xor_reduce(ex4_rd_array_data_q(30 to 37)); +ex4_rd_data_calc_par(66) <= xor_reduce(ex4_rd_array_data_q(38 to 44)); +ex4_rd_data_calc_par(67) <= xor_reduce(ex4_rd_array_data_q(45 to 50)); +parerr_gen0: if check_parity = 0 generate +ex3_cmp_data_parerr_epn <= '0'; +ex3_cmp_data_parerr_rpn <= '0'; +end generate parerr_gen0; +parerr_gen1: if check_parity = 1 generate +ex3_cmp_data_parerr_epn <= ex3_cmp_data_parerr_epn_mac; +ex3_cmp_data_parerr_rpn <= ex3_cmp_data_parerr_rpn_mac; +end generate parerr_gen1; +parerr_gen2: if check_parity = 0 generate +ex4_rd_data_parerr_epn <= '0'; +ex4_rd_data_parerr_rpn <= '0'; +end generate parerr_gen2; +parerr_gen3: if check_parity = 1 generate +ex4_rd_data_parerr_epn <= or_reduce(ex4_rd_data_calc_par(50 to 60) xor (ex4_rd_cam_data_q(83) & ex4_rd_array_data_q(51 to 60))); +ex4_rd_data_parerr_rpn <= or_reduce(ex4_rd_data_calc_par(61 to 67) xor ex4_rd_array_data_q(61 to 67)); +end generate parerr_gen3; +epsc_wr_d(0 TO thdid_width-1) <= xu_derat_epsc_wr and (0 to thdid_width-1 => not bcfg_q(108)); +epsc_wr_d(thdid_width TO 2*thdid_width-1) <= (epsc_wr_q(0 to thdid_width-1) or epsc_wr_q(thdid_width to 2*thdid_width-1)) + when or_reduce(tlb_rel_val_q(0 to 4))='1' + else epsc_wr_q(0 to thdid_width-1); +epsc_wr_d(2*thdid_width) <= (or_reduce(epsc_wr_q(0 to thdid_width-1)) or epsc_wr_q(2*thdid_width)) + when or_reduce(tlb_rel_val_q(0 to 4))='1' + else or_reduce(epsc_wr_q(0 to thdid_width-1)); +eplc_wr_d(0 TO thdid_width-1) <= xu_derat_eplc_wr and (0 to thdid_width-1 => not bcfg_q(109)); +eplc_wr_d(thdid_width TO 2*thdid_width-1) <= (eplc_wr_q(0 to thdid_width-1) or eplc_wr_q(thdid_width to 2*thdid_width-1)) + when (or_reduce(tlb_rel_val_q(0 to 4))='1' or epsc_wr_q(2*thdid_width)='1') + else eplc_wr_q(0 to thdid_width-1); +eplc_wr_d(2*thdid_width) <= (or_reduce(eplc_wr_q(0 to thdid_width-1)) or eplc_wr_q(2*thdid_width)) + when (or_reduce(tlb_rel_val_q(0 to 4))='1' or epsc_wr_q(2*thdid_width)='1') + else or_reduce(eplc_wr_q(0 to thdid_width-1)); +flash_invalidate <= Eq(por_seq_q,PorSeq_Stg1) or mchk_flash_inv_enab; +comp_invalidate <= '1' when (ex6_valid_q/="0000" and ex6_ttype_q(6 to 7)/="00") + else '0' when (tlb_rel_val_q(0 to 3)/="0000" and tlb_rel_val_q(4)='1') + else '1' when ((eplc_wr_q(8)='1' or epsc_wr_q(8)='1') and tlb_rel_val_q(4)='0' and mmucr1_q(7)='0') + else '1' when snoop_val_q(0 to 1)="11" + else '0'; +comp_request <= '1' when (ex6_valid_q/="0000" and ex6_ttype_q(6 to 7)/="00") + else '1' when ((eplc_wr_q(8)='1' or epsc_wr_q(8)='1') and tlb_rel_val_q(4)='0' and mmucr1_q(7)='0') + else '1' when (snoop_val_q(0 to 1)="11" and (tlb_rel_val_q(0 to 3)="0000" or tlb_rel_val_q(4)='0')) + else '1' when (ex1_valid_q/="0000" and ex1_ttype_q(2)='1' and ex1_tlbsel_q=TlbSel_DErat) + else '1' when (ex1_valid_q/="0000" and ex1_ttype_q(4 to 5)/="00" ) + else '0'; +gen64_comp_addr: if rs_data_width = 64 generate +comp_addr <= xu_derat_ex1_epn_arr; +snoop_addr <= snoop_addr_q; +snoop_addr_sel <= snoop_val_q(0) and snoop_val_q(1); +end generate gen64_comp_addr; +gen32_comp_addr: if rs_data_width = 32 generate +comp_addr <= (0 to 31 => '0') & xu_derat_ex1_epn_arr(32 to 51); +snoop_addr <= (0 to 31 => '0') & snoop_addr_q(32 to 51); +snoop_addr_sel <= snoop_val_q(0) and snoop_val_q(1); +end generate gen32_comp_addr; +addr_enable <= "00" when (ex6_valid_q/="0000" and ex6_ttype_q(6 to 7)/="00") + else "00" when (epsc_wr_q(8)='1' or eplc_wr_q(8)='1') + else "00" when (snoop_val_q(0 to 1)="11" and snoop_attr_q(1 to 3)/="011") + else "10" when (snoop_val_q(0 to 1)="11" and snoop_attr_q(0 to 3)="0011") + else "11" when (snoop_val_q(0 to 1)="11" and snoop_attr_q(0 to 3)="1011") + else "11" when (ex1_valid_q/="0000" and ex1_ttype_q(2)='1' and ex1_tlbsel_q=TlbSel_DErat) + else "11" when (ex1_valid_q/="0000" and ex1_ttype_q(4 to 5)/="00" ) + else "00"; +comp_pgsize <= CAM_PgSize_1GB when snoop_attr_q(14 to 17)=WS0_PgSize_1GB + else CAM_PgSize_16MB when snoop_attr_q(14 to 17)=WS0_PgSize_16MB + else CAM_PgSize_1MB when snoop_attr_q(14 to 17)=WS0_PgSize_1MB + else CAM_PgSize_64KB when snoop_attr_q(14 to 17)=WS0_PgSize_64KB + else CAM_PgSize_4KB; +pgsize_enable <= '0' when (ex6_valid_q/="0000" and ex6_ttype_q(6 to 7)/="00") + else '0' when (epsc_wr_q(8)='1' or eplc_wr_q(8)='1') + else '1' when (snoop_val_q(0 to 1)="11" and snoop_attr_q(0 to 3)="0011") + else '0'; +comp_class <= "11" when (epsc_wr_q(8)='1' and mmucr1_q(7)='0') + else "10" when (epsc_wr_q(8)='0' and eplc_wr_q(8)='1' and mmucr1_q(7)='0') + else snoop_attr_q(20 to 21) when (snoop_val_q(0 to 1)="11" and mmucr1_q(7)='1') + else snoop_attr_q(2 to 3) when (snoop_val_q(0 to 1)="11") + else ex1_pid_q(pid_width-14 to pid_width-13) when mmucr1_q(7)='1' + else ((ex1_ttype_q(10) or ex1_ttype_q(11)) & ex1_ttype_q(11)); +class_enable(0) <= '0' when (mmucr1_q(7)='1') + else '0' when (ex6_valid_q/="0000" and ex6_ttype_q(6 to 7)/="00") + else '1' when ((eplc_wr_q(8)='1' or epsc_wr_q(8)='1') and tlb_rel_val_q(4)='0' and mmucr1_q(7)='0') + else '1' when (snoop_val_q(0 to 1)="11" and snoop_attr_q(1)='1') + else '1' when (ex1_valid_q/="0000" and ex1_ttype_q(10 to 11)/="00" and mmucr1_q(9)='0') + else '1' when (ex1_valid_q/="0000" and ex1_ttype_q(4 to 5)/="00" and mmucr1_q(9)='0') + else '0'; +class_enable(1) <= '0' when (mmucr1_q(7)='1') + else '0' when (ex6_valid_q/="0000" and ex6_ttype_q(6 to 7)/="00") + else '1' when ((eplc_wr_q(8)='1' or epsc_wr_q(8)='1') and tlb_rel_val_q(4)='0' and mmucr1_q(7)='0') + else '1' when (snoop_val_q(0 to 1)="11" and snoop_attr_q(1)='1') + else '1' when (ex1_valid_q/="0000" and ex1_ttype_q(10 to 11)/="00" and mmucr1_q(9)='0') + else '0'; +class_enable(2) <= '0' when (mmucr1_q(7)='0') + else pid_enable; +comp_extclass(0) <= '0'; +comp_extclass(1) <= snoop_attr_q(19); +extclass_enable(0) <= ( or_reduce(ex6_valid_q) and or_reduce(ex6_ttype_q(6 to 7)) ) + or ( (eplc_wr_q(8) or epsc_wr_q(8)) and not mmucr1_q(7) ) + or ( snoop_val_q(0) and snoop_attr_q(18) ); +extclass_enable(1) <= ( snoop_val_q(0) and not snoop_attr_q(1) and snoop_attr_q(3) ); +comp_state <= snoop_attr_q(4 to 5) when (snoop_val_q(0 to 1)="11" and snoop_attr_q(1 to 2)="01") + else ex1_state_q(1 to 2); +state_enable <= "00" when (ex6_valid_q/="0000" and ex6_ttype_q(6 to 7)/="00") + else "00" when (epsc_wr_q(8)='1' or eplc_wr_q(8)='1') + else "00" when (snoop_val_q(0 to 1)="11" and snoop_attr_q(1 to 2)/="01") + else "10" when (snoop_val_q(0 to 1)="11" and snoop_attr_q(1 to 3)="010") + else "11" when (snoop_val_q(0 to 1)="11" and snoop_attr_q(1 to 3)="011") + else "11" when (ex1_valid_q/="0000" and ex1_ttype_q(2)='1' and ex1_tlbsel_q=TlbSel_DErat) + else "11" when (ex1_valid_q/="0000" and ex1_ttype_q(4 to 5)/="00" ) + else "00"; +comp_thdid <= snoop_attr_q(22 to 25) when (snoop_val_q(0 to 1)="11" and mmucr1_q(8)='1') + else ex1_pid_q(pid_width-12 to pid_width-9) when (mmucr1_q(8)='1') + else epsc_wr_q(4 to 7) when (epsc_wr_q(8)='1' and mmucr1_q(8)='0') + else eplc_wr_q(4 to 7) when (epsc_wr_q(8)='0' and eplc_wr_q(8)='1' and mmucr1_q(8)='0') + else (others => '1') when (snoop_val_q(0 to 1)="11" and mmucr1_q(8)='0') + else ex1_valid_q; +thdid_enable(0) <= '0' when (mmucr1_q(8)='1') + else '0' when (ex6_valid_q/="0000" and ex6_ttype_q(6 to 7)/="00") + else '1' when (epsc_wr_q(8)='1' and tlb_rel_val_q(4)='0' and mmucr1_q(8)='0') + else '1' when (epsc_wr_q(8)='0' and eplc_wr_q(8)='1' and tlb_rel_val_q(4)='0' and mmucr1_q(8)='0') + else '0' when (snoop_val_q(0 to 1)="11") + else '1' when (ex1_valid_q/="0000" and ((ex1_ttype_q(2)='1' and ex1_tlbsel_q=TlbSel_DErat) or or_reduce(ex1_ttype_q(4 to 5))='1')) + else '0'; +thdid_enable(1) <= '0' when (mmucr1_q(8)='0') + else pid_enable; +comp_pid <= snoop_attr_q(6 to 13) when (snoop_val_q(0 to 1)="11") + else ex1_pid_q(pid_width-8 to pid_width-1); +pid_enable <= '0' when (ex6_valid_q/="0000" and ex6_ttype_q(6 to 7)/="00") + else '0' when (epsc_wr_q(8)='1' or eplc_wr_q(8)='1') + else '0' when (snoop_val_q(0 to 1)="11" and snoop_attr_q(1)='1') + else '0' when (snoop_val_q(0 to 1)="11" and snoop_attr_q(3)='0') + else '1' when (snoop_val_q(0 to 1)="11" and snoop_attr_q(1 to 3)="001") + else '1' when (snoop_val_q(0 to 1)="11" and snoop_attr_q(1 to 3)="011") + else '1' when (ex1_valid_q/="0000" and ex1_ttype_q(2)='1' and ex1_tlbsel_q=TlbSel_DErat) + else '1' when (ex1_valid_q/="0000" and ex1_ttype_q(4 to 5)/="00" ) + else '0'; +gen64_data_out: if data_out_width = 64 generate +ex4_data_out_d <= ( ((0 to 31 => '0') & rd_cam_data(32 to 51) & rd_cam_data(61 to 62) & rd_cam_data(56) & + rd_cam_data(52) & ws0_pgsize(0 to 3) & rd_cam_data(57 to 60)) + and (64-data_out_width to 63 => (or_reduce(ex3_valid_q) and ex3_ttype_q(0) and not ex3_ws_q(0) and not ex3_ws_q(1) and not ex3_state_q(3))) ) + or ( ((0 to 31 => '0') & rd_array_data(10 to 29) & "00" & rd_array_data(0 to 9)) + and (64-data_out_width to 63 => (or_reduce(ex3_valid_q) and ex3_ttype_q(0) and not ex3_ws_q(0) and ex3_ws_q(1) and not ex3_state_q(3))) ) + or ( ((0 to 31 => '0') & "00000000" & rd_array_data(32 to 34) & '0' & rd_array_data(36 to 39) & rd_array_data(30 to 31) & + "00" & rd_array_data(40 to 44) & rd_array_data(35) & rd_array_data(45 to 50)) + and (64-data_out_width to 63 => (or_reduce(ex3_valid_q) and ex3_ttype_q(0) and ex3_ws_q(0) and not ex3_ws_q(1) and not ex3_state_q(3))) ) + or ( (rd_cam_data(0 to 51) & rd_cam_data(61 to 62) & rd_cam_data(56) & + rd_cam_data(52) & ws0_pgsize(0 to 3) & rd_cam_data(57 to 60)) + and (64-data_out_width to 63 => (or_reduce(ex3_valid_q) and ex3_ttype_q(0) and not ex3_ws_q(0) and not ex3_ws_q(1) and ex3_state_q(3))) ) + or ( ("00000000" & rd_array_data(32 to 34) & '0' & rd_array_data(36 to 39) & rd_array_data(30 to 31) & + "0000" & rd_array_data(0 to 29) & rd_array_data(40 to 44) & rd_array_data(35) & rd_array_data(45 to 50)) + and (64-data_out_width to 63 => (or_reduce(ex3_valid_q) and ex3_ttype_q(0) and not ex3_ws_q(0) and ex3_ws_q(1) and ex3_state_q(3))) ) + or ( ((0 to 47-watermark_width => '0') & (watermark_q and (48-watermark_width to 47 => bcfg_q(107))) & (48 to 63-eptr_width => '0') & eptr_q) + and (64-data_out_width to 63 => (or_reduce(ex3_valid_q) and ex3_ttype_q(0) and ex3_ws_q(0) and ex3_ws_q(1) and mmucr1_q(0))) ) + or ( ((0 to 47-watermark_width => '0') & (watermark_q and (48-watermark_width to 47 => bcfg_q(107))) & (48 to 63-num_entry_log2 => '0') & lru_way_encode) + and (64-data_out_width to 63 => (or_reduce(ex3_valid_q) and ex3_ttype_q(0) and ex3_ws_q(0) and ex3_ws_q(1) and not mmucr1_q(0))) ) + or ( ((0 to 49 => '0') & ex3_eratsx_data(0 to 1) & (52 to 58 => '0') & ex3_eratsx_data(2 to 2+num_entry_log2-1)) + and (64-data_out_width to 63 => (or_reduce(ex3_valid_q) and ex3_ttype_q(2))) ); +end generate gen64_data_out; +gen32_data_out: if data_out_width = 32 generate +ex4_data_out_d <= ( (rd_cam_data(32 to 51) & rd_cam_data(61 to 62) & rd_cam_data(56) & + rd_cam_data(52) & ws0_pgsize(0 to 3) & rd_cam_data(57 to 60)) + and (64-data_out_width to 63 => (or_reduce(ex3_valid_q) and ex3_ttype_q(0) and not ex3_ws_q(0) and not ex3_ws_q(1))) ) + or ( (rd_array_data(10 to 29) & "00" & rd_array_data(0 to 9)) + and (64-data_out_width to 63 => (or_reduce(ex3_valid_q) and ex3_ttype_q(0) and not ex3_ws_q(0) and ex3_ws_q(1))) ) + or ( ("00000000" & rd_array_data(32 to 34) & '0' & rd_array_data(36 to 39) & rd_array_data(30 to 31) & + "00" & rd_array_data(40 to 44) & rd_array_data(35) & rd_array_data(45 to 50)) + and (64-data_out_width to 63 => (or_reduce(ex3_valid_q) and ex3_ttype_q(0) and ex3_ws_q(0) and not ex3_ws_q(1))) ) + or ( ((32 to 47-watermark_width => '0') & (watermark_q and (48-watermark_width to 47 => bcfg_q(107))) & (48 to 58 => '0') & eptr_q) + and (64-data_out_width to 63 => (or_reduce(ex3_valid_q) and ex3_ttype_q(0) and ex3_ws_q(0) and ex3_ws_q(1) and mmucr1_q(0))) ) + or ( ((32 to 47-watermark_width => '0') & (watermark_q and (48-watermark_width to 47 => bcfg_q(107))) & (48 to 58 => '0') & lru_way_encode) + and (64-data_out_width to 63 => (or_reduce(ex3_valid_q) and ex3_ttype_q(0) and ex3_ws_q(0) and ex3_ws_q(1) and not mmucr1_q(0))) ) + or ( ((32 to 49 => '0') & ex3_eratsx_data(0 to 1) & (52 to 58 => '0') & ex3_eratsx_data(2 to 2+num_entry_log2-1)) + and (64-data_out_width to 63 => (or_reduce(ex3_valid_q) and ex3_ttype_q(2))) ); +end generate gen32_data_out; +derat_xu_ex2_miss <= ex2_valid_q and (0 to thdid_width-1 => (not cam_hit and or_reduce(ex2_ttype_q(4 to 5)) and not ex2_ttype_q(9) and not ccr2_frat_paranoia_q(9))); +gen_mcompar_breaks_timing_1: if ex2_epn_width = rpn_width generate +derat_xu_ex2_rpn(22 TO 33) <= ( ex2_epn_q(22 to 33) and (22 to 33 => (ccr2_frat_paranoia_q(9) or ccr2_frat_paranoia_q(11))) ) or + ( array_cmp_data(0 to 11) and (0 to 11 => (not ccr2_frat_paranoia_q(9) and not ccr2_frat_paranoia_q(11))) ); +derat_xu_ex2_rpn(34 TO 39) <= ( ex2_epn_q(34 to 39) and (34 to 39 => (not(cam_cmp_data(75)) or ccr2_frat_paranoia_q(9) or ccr2_frat_paranoia_q(11))) ) or + ( array_cmp_data(12 to 17) and (12 to 17 => (cam_cmp_data(75) and not ccr2_frat_paranoia_q(9) and not ccr2_frat_paranoia_q(11))) ); +derat_xu_ex2_rpn(40 TO 43) <= ( ex2_epn_q(40 to 43) and (40 to 43 => (not(cam_cmp_data(76)) or ccr2_frat_paranoia_q(9) or ccr2_frat_paranoia_q(11))) ) or + ( array_cmp_data(18 to 21) and (18 to 21 => (cam_cmp_data(76) and not ccr2_frat_paranoia_q(9) and not ccr2_frat_paranoia_q(11))) ); +derat_xu_ex2_rpn(44 TO 47) <= ( ex2_epn_q(44 to 47) and (44 to 47 => (not(cam_cmp_data(77)) or ccr2_frat_paranoia_q(9) or ccr2_frat_paranoia_q(11))) ) or + ( array_cmp_data(22 to 25) and (22 to 25 => (cam_cmp_data(77) and not ccr2_frat_paranoia_q(9) and not ccr2_frat_paranoia_q(11))) ); +derat_xu_ex2_rpn(48 TO 51) <= ( ex2_epn_q(48 to 51) and (48 to 51 => (not(cam_cmp_data(78)) or ccr2_frat_paranoia_q(9) or ccr2_frat_paranoia_q(11))) ) or + ( array_cmp_data(26 to 29) and (26 to 29 => (cam_cmp_data(78) and not ccr2_frat_paranoia_q(9) and not ccr2_frat_paranoia_q(11))) ); +derat_xu_ex2_u <= ( ccr2_frat_paranoia_q(5 to 8) and (5 to 8 => ccr2_frat_paranoia_q(9)) ) or + ( array_cmp_data(36 to 39) and (36 to 39 => not ccr2_frat_paranoia_q(9)) ); +derat_xu_ex2_wimge <= ( ccr2_frat_paranoia_q(0 to 4) and (0 to 4 => ccr2_frat_paranoia_q(9)) ) or + ( array_cmp_data(40 to 44) and (40 to 44 => not ccr2_frat_paranoia_q(9)) ); +derat_xu_ex2_wlc <= array_cmp_data(32 to 33) and (32 to 33 => not ccr2_frat_paranoia_q(9)); +derat_xu_ex2_vf <= array_cmp_data(35) and not ccr2_frat_paranoia_q(9); +end generate gen_mcompar_breaks_timing_1; +gen_no_frat_1: if ex2_epn_width = 18 generate +derat_xu_ex2_rpn(22 TO 33) <= array_cmp_data(0 to 11); +derat_xu_ex2_rpn(34 TO 39) <= ( ex2_epn_q(34 to 39) and (34 to 39 => (cam_cmp_data(53) and cam_cmp_data(54) and not cam_cmp_data(55))) ) or + ( array_cmp_data(12 to 17) and (12 to 17 => (not(cam_cmp_data(53)) or not(cam_cmp_data(54)) or cam_cmp_data(55))) ); +derat_xu_ex2_rpn(40 TO 43) <= ( ex2_epn_q(40 to 43) and (40 to 43 => (cam_cmp_data(53) and cam_cmp_data(54))) ) or + ( array_cmp_data(18 to 21) and (18 to 21 => (not cam_cmp_data(53) or not cam_cmp_data(54))) ); +derat_xu_ex2_rpn(44 TO 47) <= ( ex2_epn_q(44 to 47) and (44 to 47 => cam_cmp_data(53)) ) or + ( array_cmp_data(22 to 25) and (22 to 25 => not cam_cmp_data(53)) ); +derat_xu_ex2_rpn(48 TO 51) <= ( ex2_epn_q(48 to 51) and (48 to 51 => (cam_cmp_data(53) or cam_cmp_data(54))) ) or + ( array_cmp_data(26 to 29) and (26 to 29 => (not cam_cmp_data(53) and not cam_cmp_data(54))) ); +derat_xu_ex2_u <= array_cmp_data(36 to 39); +derat_xu_ex2_wimge <= array_cmp_data(40 to 44); +derat_xu_ex2_wlc <= array_cmp_data(32 to 33); +derat_xu_ex2_vf <= array_cmp_data(35); +end generate gen_no_frat_1; +bypass_mux_enab_np1 <= (ccr2_frat_paranoia_q(9) or ccr2_frat_paranoia_q(11) or an_ac_grffence_en_dc); +bypass_attr_np1(0 TO 5) <= (others => '0'); +bypass_attr_np1(6 TO 9) <= ccr2_frat_paranoia_q(5 to 8); +bypass_attr_np1(10 TO 14) <= ccr2_frat_paranoia_q(0 to 4); +bypass_attr_np1(15 TO 20) <= "111111"; +derat_xu_ex2_attr <= ex3_attr_d; +derat_xu_ex3_miss <= ex3_miss_q; +derat_xu_ex3_dsi <= ex3_dsi_q(12 to 15) and (0 to 3 => ex3_dsi_enab); +derat_xu_ex3_noop_touch <= ex3_noop_touch_q(12 to 15) and (0 to 3 => ex3_noop_touch_enab); +derat_xu_ex3_multihit_err <= ex3_multihit_q and (0 to 3 => ex3_multihit_enab); +derat_xu_ex3_par_err <= ex3_parerr_q(0 to thdid_width-1) and (0 to thdid_width-1 => ex3_parerr_enab); +derat_xu_ex3_n_flush_req <= ex3_n_flush_req_q; +derat_xu_ex4_data <= ex4_data_out_q; +derat_xu_ex4_par_err <= ex4_parerr_q(0 to thdid_width-1) and (0 to thdid_width-1 => ex4_parerr_enab); +derat_fir_par_err <= ex4_fir_parerr_q(0 to thdid_width-1) and (0 to thdid_width-1 => ex4_fir_parerr_enab); +derat_fir_multihit <= ex4_fir_multihit_q; +derat_iu_barrier_done <= barrier_done_q; +xu_mm_derat_req <= ex3_tlbreq_q; +xu_mm_derat_thdid <= ex3_valid_q; +xu_mm_derat_state <= ex3_state_q; +xu_mm_derat_ttype <= "11" when ex3_ttype_q(11)='1' + else "10" when ex3_ttype_q(10)='1' + else "01" when ex3_ttype_q(5)='1' + else "00"; +xu_mm_derat_tid <= ex3_pid_q; +xu_mm_derat_lpid <= ex3_lpid_q; +xu_mm_derat_mmucr0 <= ex6_extclass_q & ex6_state_q(1 to 2) & ex6_pid_q; +xu_mm_derat_mmucr0_we <= ex6_valid_q when (ex6_ttype_q(0)='1' and ex6_ws_q="00" and ex6_tlbsel_q=TlbSel_DErat) + else (others => '0'); +xu_mm_derat_mmucr1 <= ex6_deen_q(1 to num_entry_log2); +xu_mm_derat_mmucr1_we <= ex6_deen_q(0); +derat_cam: entity tri.tri_cam_32x143_1r1w1c + generic map (expand_type => expand_type) + port map ( + gnd => gnd, + vdd => vdd, + vcs => vcs, + nclk => nclk, + + + tc_ccflush_dc => pc_xu_ccflush_dc, + tc_scan_dis_dc_b => tc_scan_dis_dc_b, + tc_scan_diag_dc => tc_scan_diag_dc, + tc_lbist_en_dc => tc_lbist_en_dc, + an_ac_atpg_en_dc => an_ac_atpg_en_dc, + + lcb_d_mode_dc => cam_d_mode_dc, + lcb_clkoff_dc_b => cam_clkoff_dc_b, + lcb_act_dis_dc => cam_act_dis_dc, + lcb_mpw1_dc_b => cam_mpw1_dc_b(0 to 3), + lcb_mpw2_dc_b => cam_mpw2_dc_b, + lcb_delay_lclkr_dc => cam_delay_lclkr_dc(0 to 3), + + pc_sg_2 => pc_sg_2, + pc_func_slp_sl_thold_2 => pc_func_slp_sl_thold_2, + pc_func_slp_nsl_thold_2 => pc_func_slp_nsl_thold_2, + pc_regf_slp_sl_thold_2 => pc_regf_slp_sl_thold_2, + pc_time_sl_thold_2 => pc_time_sl_thold_2, + pc_fce_2 => pc_fce_2, + + func_scan_in => func_si_cam_int, + func_scan_out => func_so_cam_int, + regfile_scan_in => regf_scan_in, + regfile_scan_out => regf_scan_out, + time_scan_in => time_scan_in, + time_scan_out => time_scan_out, + + + rd_val => rd_val, + rd_val_late => tiup, + rw_entry => rw_entry, + + wr_array_data => wr_array_data, + wr_cam_data => wr_cam_data, + wr_array_val => wr_array_val, + wr_cam_val => wr_cam_val, + wr_val_early => wr_val_early, + + comp_request => comp_request, + comp_addr => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + comp_class => comp_class, + class_enable => class_enable, + comp_extclass => comp_extclass, + extclass_enable => extclass_enable, + comp_state => comp_state, + state_enable => state_enable, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + comp_pid => comp_pid, + pid_enable => pid_enable, + comp_invalidate => comp_invalidate, + flash_invalidate => flash_invalidate, + + array_cmp_data => array_cmp_data, + rd_array_data => rd_array_data, + + cam_cmp_data => cam_cmp_data, + cam_hit => cam_hit, + cam_hit_entry => cam_hit_entry, + entry_match => entry_match, + entry_valid => entry_valid, + rd_cam_data => rd_cam_data, + + +bypass_mux_enab_np1 => bypass_mux_enab_np1, + bypass_attr_np1 => bypass_attr_np1, + attr_np2 => attr_np2, + rpn_np2 => rpn_np2 + + ); +derat_cmp_parerr_mac: entity tri.tri_cam_parerr_mac + port map ( + gnd => gnd, + vdd => vdd, + + nclk => nclk, + lcb_act_dis_dc => cam_act_dis_dc, + lcb_delay_lclkr_dc => cam_delay_lclkr_dc(4), + lcb_clkoff_dc_b_0 => cam_clkoff_dc_b, + lcb_mpw1_dc_b => cam_mpw1_dc_b(4), + lcb_mpw2_dc_b => cam_mpw2_dc_b, + + act => ex2_cmp_data_act, + lcb_sg_0 => pc_sg_0, + lcb_func_sl_thold_0 => pc_func_slp_sl_thold_0, + + func_scan_in => siv_1(erat_parerr_mac_offset), + func_scan_out => sov_1(erat_parerr_mac_offset), + + np1_cam_cmp_data => cam_cmp_data, + np1_array_cmp_data => array_cmp_data, + + np2_cam_cmp_data => ex3_cam_cmp_data_q, + np2_array_cmp_data => ex3_array_cmp_data_q, + np2_cmp_data_parerr_epn => ex3_cmp_data_parerr_epn_mac, + np2_cmp_data_parerr_rpn => ex3_cmp_data_parerr_rpn_mac + + ); +derat_xu_ex3_rpn <= rpn_np2; +derat_xu_ex3_wimge <= attr_np2(10 to 14); +derat_xu_ex3_u <= attr_np2(6 to 9); +derat_xu_ex3_wlc <= attr_np2(2 to 3); +derat_xu_ex3_attr <= attr_np2(15 to 20); +derat_xu_ex3_vf <= attr_np2(5); +ex2_debug_d(0) <= comp_request; +ex2_debug_d(1) <= comp_invalidate; +ex2_debug_d(2) <= ( or_reduce(ex6_valid_q) and or_reduce(ex6_ttype_q(6 to 7)) ); +ex2_debug_d(3) <= ( (eplc_wr_q(8) or epsc_wr_q(8)) and not(tlb_rel_val_q(4)) and not(mmucr1_q(7)) ); +ex2_debug_d(4) <= ( snoop_val_q(0) and snoop_val_q(1) and not(or_reduce(tlb_rel_val_q(0 to 3)) and tlb_rel_val_q(4)) ); +ex2_debug_d(5) <= ( or_reduce(ex1_valid_q) and ex1_ttype_q(2) and Eq(ex1_tlbsel_q,TlbSel_DErat)); +ex2_debug_d(6) <= ( or_reduce(ex1_valid_q) and or_reduce(ex1_ttype_q(4 to 5)) ); +ex2_debug_d(7) <= ( or_reduce(tlb_rel_val_q(0 to 3)) and tlb_rel_val_q(4) ); +ex2_debug_d(8) <= ( or_reduce(tlb_rel_val_q(0 to 3)) ); +ex2_debug_d(9) <= ( snoop_val_q(0) and snoop_val_q(1) ); +ex2_debug_d(10) <= ( eplc_wr_q(8) or epsc_wr_q(8) ); +ex3_debug_d(0 TO 10) <= ex2_debug_q(0 to 10); +ex3_debug_d(11 TO 15) <= ex3_first_hit_entry; +ex3_debug_d(16) <= ex3_multihit_enab; +lru_debug_d(0) <= tlb_rel_data_q(eratpos_wren) when (tlb_rel_val_q(0 to 3)/="0000" and tlb_rel_val_q(4)='1') else '0'; +lru_debug_d(1) <= '1' when snoop_val_q(0 to 1)="11" else '0'; +lru_debug_d(2) <= '1' when (ex6_valid_q/="0000" and ex6_ttype_q(6 to 7)/="00") else '0'; +lru_debug_d(3) <= '1' when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_ws_q="00" and ex6_tlbsel_q=TlbSel_DErat and lru_way_encode=ex6_ra_entry_q) else '0'; +lru_debug_d(4) <= '1' when (ex6_valid_q/="0000" and ex6_ttype_q(4 to 5)/="00" and ex6_hit_q='1' ) else '0'; +lru_debug_d(5 TO 35) <= lru_eff; +lru_debug_d(36 TO 40) <= lru_way_encode; +derat_xu_debug_group0(0 TO 83) <= ex3_cam_cmp_data_q(0 to 83); +derat_xu_debug_group0(84) <= ex3_cam_hit_q; +derat_xu_debug_group0(85) <= ex3_debug_q(0); +derat_xu_debug_group0(86) <= ex3_debug_q(1); +derat_xu_debug_group0(87) <= ex3_debug_q(9); +derat_xu_debug_group1(0 TO 67) <= ex3_array_cmp_data_q(0 to 67); +derat_xu_debug_group1(68) <= ex3_cam_hit_q; +derat_xu_debug_group1(69) <= ex3_debug_q(16); +derat_xu_debug_group1(70 TO 74) <= ex3_debug_q(11 to 15); +derat_xu_debug_group1(75) <= ex3_debug_q(0); +derat_xu_debug_group1(76) <= ex3_debug_q(1); +derat_xu_debug_group1(77) <= ex3_debug_q(2); +derat_xu_debug_group1(78) <= ex3_debug_q(3); +derat_xu_debug_group1(79) <= ex3_debug_q(4); +derat_xu_debug_group1(80) <= ex3_debug_q(5); +derat_xu_debug_group1(81) <= ex3_debug_q(6); +derat_xu_debug_group1(82) <= ex3_debug_q(7); +derat_xu_debug_group1(83) <= ex3_debug_q(8); +derat_xu_debug_group1(84) <= ex3_debug_q(9); +derat_xu_debug_group1(85) <= ex3_debug_q(10); +derat_xu_debug_group1(86) <= ex3_ttype_q(8); +derat_xu_debug_group1(87) <= ex3_ttype_q(9); +derat_xu_debug_group2(0 TO 31) <= entry_valid_q(0 to 31); +derat_xu_debug_group2(32 TO 63) <= entry_match_q(0 to 31); +derat_xu_debug_group2(64 TO 73) <= lru_update_event_q(0 to 9); +derat_xu_debug_group2(74 TO 78) <= lru_debug_q(36 to 40); +derat_xu_debug_group2(79 TO 83) <= watermark_q(0 to 4); +derat_xu_debug_group2(84) <= ex3_cam_hit_q; +derat_xu_debug_group2(85) <= ex3_debug_q(0); +derat_xu_debug_group2(86) <= ex3_debug_q(1); +derat_xu_debug_group2(87) <= ex3_debug_q(9); +derat_xu_debug_group3(0) <= ex3_cam_hit_q; +derat_xu_debug_group3(1) <= ex3_debug_q(0); +derat_xu_debug_group3(2) <= ex3_debug_q(1); +derat_xu_debug_group3(3) <= ex3_debug_q(9); +derat_xu_debug_group3(4 TO 8) <= ex3_debug_q(11 to 15); +derat_xu_debug_group3(9) <= lru_update_event_q(9); +derat_xu_debug_group3(10 TO 14) <= lru_debug_q(0 to 4); +derat_xu_debug_group3(15 TO 19) <= watermark_q(0 to 4); +derat_xu_debug_group3(20) <= '0'; +derat_xu_debug_group3(21 TO 51) <= lru_q(1 to 31); +derat_xu_debug_group3(52 TO 82) <= lru_debug_q(5 to 35); +derat_xu_debug_group3(83 TO 87) <= lru_debug_q(36 to 40); +unused_dc(0) <= or_reduce(LCB_DELAY_LCLKR_DC(1 TO 4)); +unused_dc(1) <= or_reduce(LCB_MPW1_DC_B(1 TO 4)); +unused_dc(2) <= '0'; +unused_dc(3) <= '0'; +unused_dc(4) <= PC_FUNC_SL_FORCE; +unused_dc(5) <= PC_FUNC_SL_THOLD_0_B; +unused_dc(6) <= or_reduce(EX1_TTYPE_Q(6 TO 7)); +unused_dc(7) <= or_reduce(EX1_RS_IS_Q); +unused_dc(8) <= or_reduce(EX1_RA_ENTRY_Q); +unused_dc(9) <= or_reduce(cam_hit_entry); +unused_dc(10) <= or_reduce(ex2_first_hit_entry) or ex2_multihit_b; +unused_dc(11) <= or_reduce(EX3_DSI_Q(8 TO 11)); +unused_dc(12) <= EX3_NOOP_TOUCH_Q(1); +unused_dc(13) <= or_reduce(EX3_NOOP_TOUCH_Q(8 TO 11)); +unused_dc(14) <= or_reduce(EX3_ATTR_Q); +unused_dc(15) <= EX4_RD_CAM_DATA_Q(56); +unused_dc(16) <= or_reduce(EX6_RS_IS_Q); +unused_dc(17) <= EX6_STATE_Q(0); +unused_dc(18) <= EX7_TTYPE_Q(0); +unused_dc(19) <= or_reduce(EX7_TTYPE_Q(2 TO 11)); +unused_dc(20) <= or_reduce(tlb_rel_data_q(eratpos_rpnrsvd TO eratpos_rpnrsvd+3)); +unused_dc(21) <= or_reduce(XU_DERAT_EX1_EPN_NONARR(0 TO 15)); +unused_dc(22) <= or_reduce(XU_DERAT_EX1_EPN_NONARR(16 TO 21)); +unused_dc(23) <= or_reduce(XU_DERAT_RF1_T); +unused_dc(24) <= or_reduce(ATTR_NP2(0 TO 1)); +unused_dc(25) <= ATTR_NP2(4); +unused_dc(26) <= mmucr1_b0_cpy_q; +unused_dc(27) <= or_reduce(BCFG_Q_B(0 to 15)); +unused_dc(28) <= or_reduce(BCFG_Q_B(16 to 31)); +unused_dc(29) <= or_reduce(BCFG_Q_B(32 to 47)); +unused_dc(30) <= or_reduce(BCFG_Q_B(48 to 51)); +unused_dc(31) <= or_reduce(bcfg_q_b(52 to 61)); +unused_dc(32) <= or_reduce(bcfg_q_b(62 to 77)); +unused_dc(33) <= or_reduce(bcfg_q_b(78 to 81)); +unused_dc(34) <= or_reduce(bcfg_q_b(82 to 86)); +unused_dc(35) <= or_reduce(por_wr_array_data(51 to 67)); +unused_dc(36) <= or_reduce(bcfg_q_b(87 to 102)); +unused_dc(37) <= or_reduce(bcfg_q_b(103 to 106)); +unused_dc(38) <= or_reduce(bcfg_q(110 to 122)); +unused_dc(39) <= or_reduce(bcfg_q_b(107 to 122)); +rf1_valid_latch: tri_rlmreg_p + generic map (width => rf1_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(rf1_valid_offset to rf1_valid_offset+rf1_valid_q'length-1), + scout => sov_0(rf1_valid_offset to rf1_valid_offset+rf1_valid_q'length-1), + din => rf1_valid_d(0 to thdid_width-1), + dout => rf1_valid_q(0 to thdid_width-1) ); +rf1_ttype_latch: tri_rlmreg_p + generic map (width => rf1_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(rf1_ttype_offset to rf1_ttype_offset+rf1_ttype_q'length-1), + scout => sov_0(rf1_ttype_offset to rf1_ttype_offset+rf1_ttype_q'length-1), + din => rf1_ttype_d, + dout => rf1_ttype_q ); +ex1_valid_latch: tri_rlmreg_p + generic map (width => ex1_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex1_valid_offset to ex1_valid_offset+ex1_valid_q'length-1), + scout => sov_0(ex1_valid_offset to ex1_valid_offset+ex1_valid_q'length-1), + din => ex1_valid_d(0 to thdid_width-1), + dout => ex1_valid_q(0 to thdid_width-1) ); +ex1_ttype_latch: tri_rlmreg_p + generic map (width => ex1_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex1_ttype_offset to ex1_ttype_offset+ex1_ttype_q'length-1), + scout => sov_0(ex1_ttype_offset to ex1_ttype_offset+ex1_ttype_q'length-1), + din => ex1_ttype_d, + dout => ex1_ttype_q ); +ex1_ws_latch: tri_rlmreg_p + generic map (width => ex1_ws_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex1_ws_offset to ex1_ws_offset+ex1_ws_q'length-1), + scout => sov_0(ex1_ws_offset to ex1_ws_offset+ex1_ws_q'length-1), + din => ex1_ws_d(0 to ws_width-1), + dout => ex1_ws_q(0 to ws_width-1) ); +ex1_rs_is_latch: tri_rlmreg_p + generic map (width => ex1_rs_is_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex1_rs_is_offset to ex1_rs_is_offset+ex1_rs_is_q'length-1), + scout => sov_0(ex1_rs_is_offset to ex1_rs_is_offset+ex1_rs_is_q'length-1), + din => ex1_rs_is_d(0 to rs_is_width-1), + dout => ex1_rs_is_q(0 to rs_is_width-1) ); +ex1_ra_entry_latch: tri_rlmreg_p + generic map (width => ex1_ra_entry_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex1_ra_entry_offset to ex1_ra_entry_offset+ex1_ra_entry_q'length-1), + scout => sov_0(ex1_ra_entry_offset to ex1_ra_entry_offset+ex1_ra_entry_q'length-1), + din => ex1_ra_entry_d(0 to ra_entry_width-1), + dout => ex1_ra_entry_q(0 to ra_entry_width-1) ); +ex1_state_latch: tri_rlmreg_p + generic map (width => ex1_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex1_state_offset to ex1_state_offset+ex1_state_q'length-1), + scout => sov_0(ex1_state_offset to ex1_state_offset+ex1_state_q'length-1), + din => ex1_state_d(0 to state_width-1), + dout => ex1_state_q(0 to state_width-1) ); +ex1_pid_latch: tri_rlmreg_p + generic map (width => ex1_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex1_pid_offset to ex1_pid_offset+ex1_pid_q'length-1), + scout => sov_0(ex1_pid_offset to ex1_pid_offset+ex1_pid_q'length-1), + din => ex1_pid_d, + dout => ex1_pid_q ); +ex1_extclass_latch: tri_rlmreg_p + generic map (width => ex1_extclass_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex1_extclass_offset to ex1_extclass_offset+ex1_extclass_q'length-1), + scout => sov_0(ex1_extclass_offset to ex1_extclass_offset+ex1_extclass_q'length-1), + din => ex1_extclass_d(0 to extclass_width-1), + dout => ex1_extclass_q(0 to extclass_width-1) ); +ex1_tlbsel_latch: tri_rlmreg_p + generic map (width => ex1_tlbsel_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex1_tlbsel_offset to ex1_tlbsel_offset+ex1_tlbsel_q'length-1), + scout => sov_0(ex1_tlbsel_offset to ex1_tlbsel_offset+ex1_tlbsel_q'length-1), + din => ex1_tlbsel_d(0 to tlbsel_width-1), + dout => ex1_tlbsel_q(0 to tlbsel_width-1) ); +ex2_valid_latch: tri_rlmreg_p + generic map (width => ex2_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex2_valid_offset to ex2_valid_offset+ex2_valid_q'length-1), + scout => sov_0(ex2_valid_offset to ex2_valid_offset+ex2_valid_q'length-1), + din => ex2_valid_d(0 to thdid_width-1), + dout => ex2_valid_q(0 to thdid_width-1) ); +ex2_ttype_latch: tri_rlmreg_p + generic map (width => ex2_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex2_ttype_offset to ex2_ttype_offset+ex2_ttype_q'length-1), + scout => sov_0(ex2_ttype_offset to ex2_ttype_offset+ex2_ttype_q'length-1), + din => ex2_ttype_d(0 to ttype_width-1), + dout => ex2_ttype_q(0 to ttype_width-1) ); +ex2_ws_latch: tri_rlmreg_p + generic map (width => ex2_ws_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex2_ws_offset to ex2_ws_offset+ex2_ws_q'length-1), + scout => sov_0(ex2_ws_offset to ex2_ws_offset+ex2_ws_q'length-1), + din => ex2_ws_d(0 to ws_width-1), + dout => ex2_ws_q(0 to ws_width-1) ); +ex2_rs_is_latch: tri_rlmreg_p + generic map (width => ex2_rs_is_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex2_rs_is_offset to ex2_rs_is_offset+ex2_rs_is_q'length-1), + scout => sov_0(ex2_rs_is_offset to ex2_rs_is_offset+ex2_rs_is_q'length-1), + din => ex2_rs_is_d(0 to rs_is_width-1), + dout => ex2_rs_is_q(0 to rs_is_width-1) ); +ex2_ra_entry_latch: tri_rlmreg_p + generic map (width => ex2_ra_entry_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex2_ra_entry_offset to ex2_ra_entry_offset+ex2_ra_entry_q'length-1), + scout => sov_0(ex2_ra_entry_offset to ex2_ra_entry_offset+ex2_ra_entry_q'length-1), + din => ex2_ra_entry_d(0 to ra_entry_width-1), + dout => ex2_ra_entry_q(0 to ra_entry_width-1) ); +ex2_state_latch: tri_rlmreg_p + generic map (width => ex2_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex2_state_offset to ex2_state_offset+ex2_state_q'length-1), + scout => sov_0(ex2_state_offset to ex2_state_offset+ex2_state_q'length-1), + din => ex2_state_d(0 to state_width-1), + dout => ex2_state_q(0 to state_width-1) ); +ex2_pid_latch: tri_rlmreg_p + generic map (width => ex2_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex2_pid_offset to ex2_pid_offset+ex2_pid_q'length-1), + scout => sov_0(ex2_pid_offset to ex2_pid_offset+ex2_pid_q'length-1), + din => ex2_pid_d, + dout => ex2_pid_q ); +ex2_extclass_latch: tri_rlmreg_p + generic map (width => ex2_extclass_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex2_extclass_offset to ex2_extclass_offset+ex2_extclass_q'length-1), + scout => sov_0(ex2_extclass_offset to ex2_extclass_offset+ex2_extclass_q'length-1), + din => ex2_extclass_d(0 to extclass_width-1), + dout => ex2_extclass_q(0 to extclass_width-1) ); +ex2_tlbsel_latch: tri_rlmreg_p + generic map (width => ex2_tlbsel_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex2_tlbsel_offset to ex2_tlbsel_offset+ex2_tlbsel_q'length-1), + scout => sov_0(ex2_tlbsel_offset to ex2_tlbsel_offset+ex2_tlbsel_q'length-1), + din => ex2_tlbsel_d(0 to tlbsel_width-1), + dout => ex2_tlbsel_q(0 to tlbsel_width-1) ); +ex3_valid_latch: tri_rlmreg_p + generic map (width => ex3_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_valid_offset to ex3_valid_offset+ex3_valid_q'length-1), + scout => sov_0(ex3_valid_offset to ex3_valid_offset+ex3_valid_q'length-1), + din => ex3_valid_d(0 to thdid_width-1), + dout => ex3_valid_q(0 to thdid_width-1) ); +ex3_ttype_latch: tri_rlmreg_p + generic map (width => ex3_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_ttype_offset to ex3_ttype_offset+ex3_ttype_q'length-1), + scout => sov_0(ex3_ttype_offset to ex3_ttype_offset+ex3_ttype_q'length-1), + din => ex3_ttype_d(0 to ttype_width-1), + dout => ex3_ttype_q(0 to ttype_width-1) ); +ex3_ws_latch: tri_rlmreg_p + generic map (width => ex3_ws_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_ws_offset to ex3_ws_offset+ex3_ws_q'length-1), + scout => sov_0(ex3_ws_offset to ex3_ws_offset+ex3_ws_q'length-1), + din => ex3_ws_d(0 to ws_width-1), + dout => ex3_ws_q(0 to ws_width-1) ); +ex3_rs_is_latch: tri_rlmreg_p + generic map (width => ex3_rs_is_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_rs_is_offset to ex3_rs_is_offset+ex3_rs_is_q'length-1), + scout => sov_0(ex3_rs_is_offset to ex3_rs_is_offset+ex3_rs_is_q'length-1), + din => ex3_rs_is_d(0 to rs_is_width-1), + dout => ex3_rs_is_q(0 to rs_is_width-1) ); +ex3_ra_entry_latch: tri_rlmreg_p + generic map (width => ex3_ra_entry_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_ra_entry_offset to ex3_ra_entry_offset+ex3_ra_entry_q'length-1), + scout => sov_0(ex3_ra_entry_offset to ex3_ra_entry_offset+ex3_ra_entry_q'length-1), + din => ex3_ra_entry_d(0 to ra_entry_width-1), + dout => ex3_ra_entry_q(0 to ra_entry_width-1) ); +ex3_state_latch: tri_rlmreg_p + generic map (width => ex3_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_state_offset to ex3_state_offset+ex3_state_q'length-1), + scout => sov_0(ex3_state_offset to ex3_state_offset+ex3_state_q'length-1), + din => ex3_state_d(0 to state_width-1), + dout => ex3_state_q(0 to state_width-1) ); +ex3_pid_latch: tri_rlmreg_p + generic map (width => ex3_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_pid_offset to ex3_pid_offset+ex3_pid_q'length-1), + scout => sov_0(ex3_pid_offset to ex3_pid_offset+ex3_pid_q'length-1), + din => ex3_pid_d, + dout => ex3_pid_q ); +ex3_lpid_latch: tri_rlmreg_p + generic map (width => ex3_lpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_lpid_offset to ex3_lpid_offset+ex3_lpid_q'length-1), + scout => sov_0(ex3_lpid_offset to ex3_lpid_offset+ex3_lpid_q'length-1), + din => ex3_lpid_d, + dout => ex3_lpid_q ); +ex3_extclass_latch: tri_rlmreg_p + generic map (width => ex3_extclass_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_extclass_offset to ex3_extclass_offset+ex3_extclass_q'length-1), + scout => sov_0(ex3_extclass_offset to ex3_extclass_offset+ex3_extclass_q'length-1), + din => ex3_extclass_d(0 to extclass_width-1), + dout => ex3_extclass_q(0 to extclass_width-1) ); +ex3_tlbsel_latch: tri_rlmreg_p + generic map (width => ex3_tlbsel_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_tlbsel_offset to ex3_tlbsel_offset+ex3_tlbsel_q'length-1), + scout => sov_0(ex3_tlbsel_offset to ex3_tlbsel_offset+ex3_tlbsel_q'length-1), + din => ex3_tlbsel_d(0 to tlbsel_width-1), + dout => ex3_tlbsel_q(0 to tlbsel_width-1) ); +ex4_valid_latch: tri_rlmreg_p + generic map (width => ex4_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex4_valid_offset to ex4_valid_offset+ex4_valid_q'length-1), + scout => sov_0(ex4_valid_offset to ex4_valid_offset+ex4_valid_q'length-1), + din => ex4_valid_d(0 to thdid_width-1), + dout => ex4_valid_q(0 to thdid_width-1) ); +ex4_ttype_latch: tri_rlmreg_p + generic map (width => ex4_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex4_ttype_offset to ex4_ttype_offset+ex4_ttype_q'length-1), + scout => sov_0(ex4_ttype_offset to ex4_ttype_offset+ex4_ttype_q'length-1), + din => ex4_ttype_d(0 to ttype_width-1), + dout => ex4_ttype_q(0 to ttype_width-1) ); +ex4_ws_latch: tri_rlmreg_p + generic map (width => ex4_ws_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex4_ws_offset to ex4_ws_offset+ex4_ws_q'length-1), + scout => sov_0(ex4_ws_offset to ex4_ws_offset+ex4_ws_q'length-1), + din => ex4_ws_d(0 to ws_width-1), + dout => ex4_ws_q(0 to ws_width-1) ); +ex4_rs_is_latch: tri_rlmreg_p + generic map (width => ex4_rs_is_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex4_rs_is_offset to ex4_rs_is_offset+ex4_rs_is_q'length-1), + scout => sov_0(ex4_rs_is_offset to ex4_rs_is_offset+ex4_rs_is_q'length-1), + din => ex4_rs_is_d(0 to rs_is_width-1), + dout => ex4_rs_is_q(0 to rs_is_width-1) ); +ex4_ra_entry_latch: tri_rlmreg_p + generic map (width => ex4_ra_entry_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex4_ra_entry_offset to ex4_ra_entry_offset+ex4_ra_entry_q'length-1), + scout => sov_0(ex4_ra_entry_offset to ex4_ra_entry_offset+ex4_ra_entry_q'length-1), + din => ex4_ra_entry_d(0 to ra_entry_width-1), + dout => ex4_ra_entry_q(0 to ra_entry_width-1) ); +ex4_state_latch: tri_rlmreg_p + generic map (width => ex4_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex4_state_offset to ex4_state_offset+ex4_state_q'length-1), + scout => sov_0(ex4_state_offset to ex4_state_offset+ex4_state_q'length-1), + din => ex4_state_d(0 to state_width-1), + dout => ex4_state_q(0 to state_width-1) ); +ex4_pid_latch: tri_rlmreg_p + generic map (width => ex4_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex4_pid_offset to ex4_pid_offset+ex4_pid_q'length-1), + scout => sov_0(ex4_pid_offset to ex4_pid_offset+ex4_pid_q'length-1), + din => ex4_pid_d, + dout => ex4_pid_q ); +ex4_extclass_latch: tri_rlmreg_p + generic map (width => ex4_extclass_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex4_extclass_offset to ex4_extclass_offset+ex4_extclass_q'length-1), + scout => sov_0(ex4_extclass_offset to ex4_extclass_offset+ex4_extclass_q'length-1), + din => ex4_extclass_d(0 to extclass_width-1), + dout => ex4_extclass_q(0 to extclass_width-1) ); +ex4_tlbsel_latch: tri_rlmreg_p + generic map (width => ex4_tlbsel_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex4_tlbsel_offset to ex4_tlbsel_offset+ex4_tlbsel_q'length-1), + scout => sov_0(ex4_tlbsel_offset to ex4_tlbsel_offset+ex4_tlbsel_q'length-1), + din => ex4_tlbsel_d(0 to tlbsel_width-1), + dout => ex4_tlbsel_q(0 to tlbsel_width-1) ); +ex5_valid_latch: tri_rlmreg_p + generic map (width => ex5_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex5_valid_offset to ex5_valid_offset+ex5_valid_q'length-1), + scout => sov_0(ex5_valid_offset to ex5_valid_offset+ex5_valid_q'length-1), + din => ex5_valid_d(0 to thdid_width-1), + dout => ex5_valid_q(0 to thdid_width-1) ); +ex5_ttype_latch: tri_rlmreg_p + generic map (width => ex5_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex5_ttype_offset to ex5_ttype_offset+ex5_ttype_q'length-1), + scout => sov_0(ex5_ttype_offset to ex5_ttype_offset+ex5_ttype_q'length-1), + din => ex5_ttype_d(0 to ttype_width-1), + dout => ex5_ttype_q(0 to ttype_width-1) ); +ex5_ws_latch: tri_rlmreg_p + generic map (width => ex5_ws_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex5_ws_offset to ex5_ws_offset+ex5_ws_q'length-1), + scout => sov_0(ex5_ws_offset to ex5_ws_offset+ex5_ws_q'length-1), + din => ex5_ws_d(0 to ws_width-1), + dout => ex5_ws_q(0 to ws_width-1) ); +ex5_rs_is_latch: tri_rlmreg_p + generic map (width => ex5_rs_is_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex5_rs_is_offset to ex5_rs_is_offset+ex5_rs_is_q'length-1), + scout => sov_0(ex5_rs_is_offset to ex5_rs_is_offset+ex5_rs_is_q'length-1), + din => ex5_rs_is_d(0 to rs_is_width-1), + dout => ex5_rs_is_q(0 to rs_is_width-1) ); +ex5_ra_entry_latch: tri_rlmreg_p + generic map (width => ex5_ra_entry_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex5_ra_entry_offset to ex5_ra_entry_offset+ex5_ra_entry_q'length-1), + scout => sov_0(ex5_ra_entry_offset to ex5_ra_entry_offset+ex5_ra_entry_q'length-1), + din => ex5_ra_entry_d(0 to ra_entry_width-1), + dout => ex5_ra_entry_q(0 to ra_entry_width-1) ); +ex5_state_latch: tri_rlmreg_p + generic map (width => ex5_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex5_state_offset to ex5_state_offset+ex5_state_q'length-1), + scout => sov_0(ex5_state_offset to ex5_state_offset+ex5_state_q'length-1), + din => ex5_state_d(0 to state_width-1), + dout => ex5_state_q(0 to state_width-1) ); +ex5_pid_latch: tri_rlmreg_p + generic map (width => ex5_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex5_pid_offset to ex5_pid_offset+ex5_pid_q'length-1), + scout => sov_0(ex5_pid_offset to ex5_pid_offset+ex5_pid_q'length-1), + din => ex5_pid_d, + dout => ex5_pid_q ); +ex5_extclass_latch: tri_rlmreg_p + generic map (width => ex5_extclass_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex5_extclass_offset to ex5_extclass_offset+ex5_extclass_q'length-1), + scout => sov_0(ex5_extclass_offset to ex5_extclass_offset+ex5_extclass_q'length-1), + din => ex5_extclass_d(0 to extclass_width-1), + dout => ex5_extclass_q(0 to extclass_width-1) ); +ex5_tlbsel_latch: tri_rlmreg_p + generic map (width => ex5_tlbsel_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex5_tlbsel_offset to ex5_tlbsel_offset+ex5_tlbsel_q'length-1), + scout => sov_0(ex5_tlbsel_offset to ex5_tlbsel_offset+ex5_tlbsel_q'length-1), + din => ex5_tlbsel_d(0 to tlbsel_width-1), + dout => ex5_tlbsel_q(0 to tlbsel_width-1) ); +ex5_data_in_latch: tri_rlmreg_p + generic map (width => ex5_data_in_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex5_data_in_offset to ex5_data_in_offset+ex5_data_in_q'length-1), + scout => sov_0(ex5_data_in_offset to ex5_data_in_offset+ex5_data_in_q'length-1), + din => ex5_data_in_d(64-rs_data_width to 63), + dout => ex5_data_in_q(64-rs_data_width to 63) ); +ex6_valid_latch: tri_rlmreg_p + generic map (width => ex6_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex6_valid_offset to ex6_valid_offset+ex6_valid_q'length-1), + scout => sov_0(ex6_valid_offset to ex6_valid_offset+ex6_valid_q'length-1), + din => ex6_valid_d(0 to thdid_width-1), + dout => ex6_valid_q(0 to thdid_width-1) ); +ex6_ttype_latch: tri_rlmreg_p + generic map (width => ex6_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex6_ttype_offset to ex6_ttype_offset+ex6_ttype_q'length-1), + scout => sov_0(ex6_ttype_offset to ex6_ttype_offset+ex6_ttype_q'length-1), + din => ex6_ttype_d(0 to ttype_width-1), + dout => ex6_ttype_q(0 to ttype_width-1) ); +ex6_ws_latch: tri_rlmreg_p + generic map (width => ex6_ws_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex5_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex6_ws_offset to ex6_ws_offset+ex6_ws_q'length-1), + scout => sov_0(ex6_ws_offset to ex6_ws_offset+ex6_ws_q'length-1), + din => ex6_ws_d(0 to ws_width-1), + dout => ex6_ws_q(0 to ws_width-1) ); +ex6_rs_is_latch: tri_rlmreg_p + generic map (width => ex6_rs_is_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex5_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex6_rs_is_offset to ex6_rs_is_offset+ex6_rs_is_q'length-1), + scout => sov_0(ex6_rs_is_offset to ex6_rs_is_offset+ex6_rs_is_q'length-1), + din => ex6_rs_is_d(0 to rs_is_width-1), + dout => ex6_rs_is_q(0 to rs_is_width-1) ); +ex6_ra_entry_latch: tri_rlmreg_p + generic map (width => ex6_ra_entry_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex5_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex6_ra_entry_offset to ex6_ra_entry_offset+ex6_ra_entry_q'length-1), + scout => sov_0(ex6_ra_entry_offset to ex6_ra_entry_offset+ex6_ra_entry_q'length-1), + din => ex6_ra_entry_d(0 to ra_entry_width-1), + dout => ex6_ra_entry_q(0 to ra_entry_width-1) ); +ex6_state_latch: tri_rlmreg_p + generic map (width => ex6_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex5_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex6_state_offset to ex6_state_offset+ex6_state_q'length-1), + scout => sov_0(ex6_state_offset to ex6_state_offset+ex6_state_q'length-1), + din => ex6_state_d(0 to state_width-1), + dout => ex6_state_q(0 to state_width-1) ); +ex6_pid_latch: tri_rlmreg_p + generic map (width => ex6_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex5_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex6_pid_offset to ex6_pid_offset+ex6_pid_q'length-1), + scout => sov_0(ex6_pid_offset to ex6_pid_offset+ex6_pid_q'length-1), + din => ex6_pid_d, + dout => ex6_pid_q ); +ex6_extclass_latch: tri_rlmreg_p + generic map (width => ex6_extclass_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex5_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex6_extclass_offset to ex6_extclass_offset+ex6_extclass_q'length-1), + scout => sov_0(ex6_extclass_offset to ex6_extclass_offset+ex6_extclass_q'length-1), + din => ex6_extclass_d(0 to extclass_width-1), + dout => ex6_extclass_q(0 to extclass_width-1) ); +ex6_tlbsel_latch: tri_rlmreg_p + generic map (width => ex6_tlbsel_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex5_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex6_tlbsel_offset to ex6_tlbsel_offset+ex6_tlbsel_q'length-1), + scout => sov_0(ex6_tlbsel_offset to ex6_tlbsel_offset+ex6_tlbsel_q'length-1), + din => ex6_tlbsel_d(0 to tlbsel_width-1), + dout => ex6_tlbsel_q(0 to tlbsel_width-1) ); +ex6_data_in_latch: tri_rlmreg_p + generic map (width => ex6_data_in_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex5_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex6_data_in_offset to ex6_data_in_offset+ex6_data_in_q'length-1), + scout => sov_0(ex6_data_in_offset to ex6_data_in_offset+ex6_data_in_q'length-1), + din => ex6_data_in_d(64-rs_data_width to 63), + dout => ex6_data_in_q(64-rs_data_width to 63) ); +ex7_valid_latch: tri_rlmreg_p + generic map (width => ex7_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex7_valid_offset to ex7_valid_offset+ex7_valid_q'length-1), + scout => sov_0(ex7_valid_offset to ex7_valid_offset+ex7_valid_q'length-1), + din => ex7_valid_d(0 to thdid_width-1), + dout => ex7_valid_q(0 to thdid_width-1) ); +ex7_ttype_latch: tri_rlmreg_p + generic map (width => ex7_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex7_ttype_offset to ex7_ttype_offset+ex7_ttype_q'length-1), + scout => sov_0(ex7_ttype_offset to ex7_ttype_offset+ex7_ttype_q'length-1), + din => ex7_ttype_d(0 to ttype_width-1), + dout => ex7_ttype_q(0 to ttype_width-1) ); +ex7_tlbsel_latch: tri_rlmreg_p + generic map (width => ex7_tlbsel_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex7_tlbsel_offset to ex7_tlbsel_offset+ex7_tlbsel_q'length-1), + scout => sov_0(ex7_tlbsel_offset to ex7_tlbsel_offset+ex7_tlbsel_q'length-1), + din => ex7_tlbsel_d(0 to tlbsel_width-1), + dout => ex7_tlbsel_q(0 to tlbsel_width-1) ); +ex4_data_out_latch: tri_rlmreg_p + generic map (width => ex4_data_out_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_data_out_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex4_data_out_offset to ex4_data_out_offset+ex4_data_out_q'length-1), + scout => sov_0(ex4_data_out_offset to ex4_data_out_offset+ex4_data_out_q'length-1), + din => ex4_data_out_d(64-data_out_width to 63), + dout => ex4_data_out_q(64-data_out_width to 63) ); +ex2_n_flush_req_latch: tri_rlmreg_p + generic map (width => ex2_n_flush_req_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex2_n_flush_req_offset to ex2_n_flush_req_offset+ex2_n_flush_req_q'length-1), + scout => sov_0(ex2_n_flush_req_offset to ex2_n_flush_req_offset+ex2_n_flush_req_q'length-1), + din => ex2_n_flush_req_d(0 to thdid_width-1), + dout => ex2_n_flush_req_q(0 to thdid_width-1) ); +ex3_n_flush_req_latch: tri_rlmreg_p + generic map (width => ex3_n_flush_req_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_n_flush_req_offset to ex3_n_flush_req_offset+ex3_n_flush_req_q'length-1), + scout => sov_0(ex3_n_flush_req_offset to ex3_n_flush_req_offset+ex3_n_flush_req_q'length-1), + din => ex3_n_flush_req_d(0 to thdid_width-1), + dout => ex3_n_flush_req_q(0 to thdid_width-1) ); +hold_req_reset_latch: tri_rlmreg_p + generic map (width => hold_req_reset_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(hold_req_reset_offset to hold_req_reset_offset+hold_req_reset_q'length-1), + scout => sov_0(hold_req_reset_offset to hold_req_reset_offset+hold_req_reset_q'length-1), + din => hold_req_reset_d(0 to thdid_width-1), + dout => hold_req_reset_q(0 to thdid_width-1) ); +hold_req_pot_set_latch: tri_rlmreg_p + generic map (width => hold_req_pot_set_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(hold_req_pot_set_offset to hold_req_pot_set_offset+hold_req_pot_set_q'length-1), + scout => sov_0(hold_req_pot_set_offset to hold_req_pot_set_offset+hold_req_pot_set_q'length-1), + din => hold_req_pot_set_d(0 to thdid_width-1), + dout => hold_req_pot_set_q(0 to thdid_width-1) ); +hold_req_por_latch: tri_rlmreg_p + generic map (width => hold_req_por_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(hold_req_por_offset to hold_req_por_offset+hold_req_por_q'length-1), + scout => sov_0(hold_req_por_offset to hold_req_por_offset+hold_req_por_q'length-1), + din => hold_req_por_d(0 to thdid_width-1), + dout => hold_req_por_q(0 to thdid_width-1) ); +hold_req_latch: tri_rlmreg_p + generic map (width => hold_req_q'length, init => 15, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(hold_req_offset to hold_req_offset+hold_req_q'length-1), + scout => sov_0(hold_req_offset to hold_req_offset+hold_req_q'length-1), + din => hold_req_d(0 to thdid_width-1), + dout => hold_req_q(0 to thdid_width-1) ); +tlb_req_inprogress_latch: tri_rlmreg_p + generic map (width => tlb_req_inprogress_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_req_inprogress_offset to tlb_req_inprogress_offset+tlb_req_inprogress_q'length-1), + scout => sov_0(tlb_req_inprogress_offset to tlb_req_inprogress_offset+tlb_req_inprogress_q'length-1), + din => tlb_req_inprogress_d(0 to thdid_width-1), + dout => tlb_req_inprogress_q(0 to thdid_width-1) ); +ex2_dsi_latch: tri_rlmreg_p + generic map (width => ex2_dsi_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex2_dsi_offset to ex2_dsi_offset+ex2_dsi_q'length-1), + scout => sov_0(ex2_dsi_offset to ex2_dsi_offset+ex2_dsi_q'length-1), + din => ex2_dsi_d, + dout => ex2_dsi_q); +ex2_noop_touch_latch: tri_rlmreg_p + generic map (width => ex2_noop_touch_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex2_noop_touch_offset to ex2_noop_touch_offset+ex2_noop_touch_q'length-1), + scout => sov_0(ex2_noop_touch_offset to ex2_noop_touch_offset+ex2_noop_touch_q'length-1), + din => ex2_noop_touch_d, + dout => ex2_noop_touch_q); +ex3_miss_latch: tri_rlmreg_p + generic map (width => ex3_miss_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_or_ex3_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_miss_offset to ex3_miss_offset+ex3_miss_q'length-1), + scout => sov_0(ex3_miss_offset to ex3_miss_offset+ex3_miss_q'length-1), + din => ex3_miss_d(0 to thdid_width-1), + dout => ex3_miss_q(0 to thdid_width-1)); +ex3_dsi_latch: tri_rlmreg_p + generic map (width => ex3_dsi_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_dsi_offset to ex3_dsi_offset+ex3_dsi_q'length-1), + scout => sov_0(ex3_dsi_offset to ex3_dsi_offset+ex3_dsi_q'length-1), + din => ex3_dsi_d, + dout => ex3_dsi_q); +ex3_noop_touch_latch: tri_rlmreg_p + generic map (width => ex3_noop_touch_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_or_ex3_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_noop_touch_offset to ex3_noop_touch_offset+ex3_noop_touch_q'length-1), + scout => sov_0(ex3_noop_touch_offset to ex3_noop_touch_offset+ex3_noop_touch_q'length-1), + din => ex3_noop_touch_d, + dout => ex3_noop_touch_q); +ex3_multihit_latch: tri_rlmreg_p + generic map (width => ex3_multihit_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_or_ex3_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_multihit_offset to ex3_multihit_offset+ex3_multihit_q'length-1), + scout => sov_0(ex3_multihit_offset to ex3_multihit_offset+ex3_multihit_q'length-1), + din => ex3_multihit_d(0 to thdid_width-1), + dout => ex3_multihit_q(0 to thdid_width-1)); +ex3_multihit_b_pt_latch: tri_rlmreg_p + generic map (width => ex3_multihit_b_pt_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_or_ex3_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_multihit_b_pt_offset to ex3_multihit_b_pt_offset+ex3_multihit_b_pt_q'length-1), + scout => sov_0(ex3_multihit_b_pt_offset to ex3_multihit_b_pt_offset+ex3_multihit_b_pt_q'length-1), + din => ex3_multihit_b_pt_d, + dout => ex3_multihit_b_pt_q); +ex3_first_hit_entry_pt_latch: tri_rlmreg_p + generic map (width => ex3_first_hit_entry_pt_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_or_ex3_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_first_hit_entry_pt_offset to ex3_first_hit_entry_pt_offset+ex3_first_hit_entry_pt_q'length-1), + scout => sov_0(ex3_first_hit_entry_pt_offset to ex3_first_hit_entry_pt_offset+ex3_first_hit_entry_pt_q'length-1), + din => ex3_first_hit_entry_pt_d, + dout => ex3_first_hit_entry_pt_q); +ex3_parerr_latch: tri_rlmreg_p + generic map (width => ex3_parerr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => not_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_parerr_offset to ex3_parerr_offset+ex3_parerr_q'length-1), + scout => sov_0(ex3_parerr_offset to ex3_parerr_offset+ex3_parerr_q'length-1), + din => ex3_parerr_d, + dout => ex3_parerr_q); +ex3_attr_latch: tri_rlmreg_p + generic map (width => ex3_attr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_attr_offset to ex3_attr_offset+ex3_attr_q'length-1), + scout => sov_0(ex3_attr_offset to ex3_attr_offset+ex3_attr_q'length-1), + din => ex3_attr_q(0 to 5), + dout => ex3_attr_q(0 to 5)); +ex3_tlbreq_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => notlb_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_tlbreq_offset), + scout => sov_0(ex3_tlbreq_offset), + din => ex3_tlbreq_d, + dout => ex3_tlbreq_q); +ex3_cam_hit_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_or_ex3_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_cam_hit_offset), + scout => sov_0(ex3_cam_hit_offset), + din => cam_hit, + dout => ex3_cam_hit_q); +ex3_hit_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_or_ex3_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_hit_offset), + scout => sov_0(ex3_hit_offset), + din => ex3_hit_d, + dout => ex3_hit_q); +ex2_debug_latch: tri_rlmreg_p + generic map (width => ex2_debug_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => trace_bus_enable_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex2_debug_offset to ex2_debug_offset+ex2_debug_q'length-1), + scout => sov_0(ex2_debug_offset to ex2_debug_offset+ex2_debug_q'length-1), + din => ex2_debug_d, + dout => ex2_debug_q); +ex3_debug_latch: tri_rlmreg_p + generic map (width => ex3_debug_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => debug_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_debug_offset to ex3_debug_offset+ex3_debug_q'length-1), + scout => sov_0(ex3_debug_offset to ex3_debug_offset+ex3_debug_q'length-1), + din => ex3_debug_d, + dout => ex3_debug_q); +ex4_rd_array_data_latch: tri_rlmreg_p + generic map (width => ex4_rd_array_data_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_rd_data_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ex4_rd_array_data_offset to ex4_rd_array_data_offset+ex4_rd_array_data_q'length-1), + scout => sov_1(ex4_rd_array_data_offset to ex4_rd_array_data_offset+ex4_rd_array_data_q'length-1), + din => ex4_rd_array_data_d(0 to array_data_width-1), + dout => ex4_rd_array_data_q(0 to array_data_width-1)); +ex4_rd_cam_data_latch: tri_rlmreg_p + generic map (width => ex4_rd_cam_data_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_rd_data_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ex4_rd_cam_data_offset to ex4_rd_cam_data_offset+ex4_rd_cam_data_q'length-1), + scout => sov_1(ex4_rd_cam_data_offset to ex4_rd_cam_data_offset+ex4_rd_cam_data_q'length-1), + din => ex4_rd_cam_data_d(0 to cam_data_width-1), + dout => ex4_rd_cam_data_q(0 to cam_data_width-1)); +ex4_parerr_latch: tri_rlmreg_p + generic map (width => ex4_parerr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ex4_parerr_offset to ex4_parerr_offset+ex4_parerr_q'length-1), + scout => sov_1(ex4_parerr_offset to ex4_parerr_offset+ex4_parerr_q'length-1), + din => ex4_parerr_d, + dout => ex4_parerr_q); +ex4_fir_parerr_latch: tri_rlmreg_p + generic map (width => ex4_fir_parerr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ex4_fir_parerr_offset to ex4_fir_parerr_offset+ex4_fir_parerr_q'length-1), + scout => sov_1(ex4_fir_parerr_offset to ex4_fir_parerr_offset+ex4_fir_parerr_q'length-1), + din => ex4_fir_parerr_d, + dout => ex4_fir_parerr_q); +ex4_fir_multihit_latch: tri_rlmreg_p + generic map (width => ex4_fir_multihit_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ex4_fir_multihit_offset to ex4_fir_multihit_offset+ex4_fir_multihit_q'length-1), + scout => sov_1(ex4_fir_multihit_offset to ex4_fir_multihit_offset+ex4_fir_multihit_q'length-1), + din => ex4_fir_multihit_d(0 to thdid_width-1), + dout => ex4_fir_multihit_q(0 to thdid_width-1)); +ex4_deen_latch: tri_rlmreg_p + generic map (width => ex4_deen_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ex4_deen_offset to ex4_deen_offset+ex4_deen_q'length-1), + scout => sov_1(ex4_deen_offset to ex4_deen_offset+ex4_deen_q'length-1), + din => ex4_deen_d(0 to ex4_deen_d'length-1), + dout => ex4_deen_q(0 to ex4_deen_q'length-1)); +ex4_hit_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ex4_hit_offset), + scout => sov_1(ex4_hit_offset), + din => ex4_hit_d, + dout => ex4_hit_q); +ex5_deen_latch: tri_rlmreg_p + generic map (width => ex5_deen_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ex5_deen_offset to ex5_deen_offset+ex5_deen_q'length-1), + scout => sov_1(ex5_deen_offset to ex5_deen_offset+ex5_deen_q'length-1), + din => ex5_deen_d(0 to ex5_deen_d'length-1), + dout => ex5_deen_q(0 to ex5_deen_q'length-1)); +ex5_hit_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ex5_hit_offset), + scout => sov_1(ex5_hit_offset), + din => ex5_hit_d, + dout => ex5_hit_q); +ex6_deen_latch: tri_rlmreg_p + generic map (width => ex6_deen_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ex6_deen_offset to ex6_deen_offset+ex6_deen_q'length-1), + scout => sov_1(ex6_deen_offset to ex6_deen_offset+ex6_deen_q'length-1), + din => ex6_deen_d(0 to ex6_deen_d'length-1), + dout => ex6_deen_q(0 to ex6_deen_q'length-1)); +ex6_hit_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ex6_hit_offset), + scout => sov_1(ex6_hit_offset), + din => ex6_hit_d, + dout => ex6_hit_q); +barrier_done_latch: tri_rlmreg_p + generic map (width => barrier_done_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(barrier_done_offset to barrier_done_offset+barrier_done_q'length-1), + scout => sov_1(barrier_done_offset to barrier_done_offset+barrier_done_q'length-1), + din => barrier_done_d(0 to barrier_done_d'length-1), + dout => barrier_done_q(0 to barrier_done_q'length-1)); +mchk_flash_inv_latch: tri_rlmreg_p + generic map (width => mchk_flash_inv_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_to_ex6_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mchk_flash_inv_offset to mchk_flash_inv_offset+mchk_flash_inv_q'length-1), + scout => sov_1(mchk_flash_inv_offset to mchk_flash_inv_offset+mchk_flash_inv_q'length-1), + din => mchk_flash_inv_d(0 to mchk_flash_inv_d'length-1), + dout => mchk_flash_inv_q(0 to mchk_flash_inv_q'length-1)); +mmucr1_latch: tri_rlmreg_p + generic map (width => mmucr1_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mmucr1_offset to mmucr1_offset+mmucr1_q'length-1), + scout => sov_1(mmucr1_offset to mmucr1_offset+mmucr1_q'length-1), + din => mmucr1_d, + dout => mmucr1_q ); +rpn_holdreg0_latch: tri_rlmreg_p + generic map (width => rpn_holdreg0_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex6_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(rpn_holdreg0_offset to rpn_holdreg0_offset+rpn_holdreg0_q'length-1), + scout => sov_1(rpn_holdreg0_offset to rpn_holdreg0_offset+rpn_holdreg0_q'length-1), + din => rpn_holdreg0_d(0 to 63), + dout => rpn_holdreg0_q(0 to 63) ); +rpn_holdreg1_latch: tri_rlmreg_p + generic map (width => rpn_holdreg1_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex6_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(rpn_holdreg1_offset to rpn_holdreg1_offset+rpn_holdreg1_q'length-1), + scout => sov_1(rpn_holdreg1_offset to rpn_holdreg1_offset+rpn_holdreg1_q'length-1), + din => rpn_holdreg1_d(0 to 63), + dout => rpn_holdreg1_q(0 to 63) ); +rpn_holdreg2_latch: tri_rlmreg_p + generic map (width => rpn_holdreg2_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex6_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(rpn_holdreg2_offset to rpn_holdreg2_offset+rpn_holdreg2_q'length-1), + scout => sov_1(rpn_holdreg2_offset to rpn_holdreg2_offset+rpn_holdreg2_q'length-1), + din => rpn_holdreg2_d(0 to 63), + dout => rpn_holdreg2_q(0 to 63) ); +rpn_holdreg3_latch: tri_rlmreg_p + generic map (width => rpn_holdreg3_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex6_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(rpn_holdreg3_offset to rpn_holdreg3_offset+rpn_holdreg3_q'length-1), + scout => sov_1(rpn_holdreg3_offset to rpn_holdreg3_offset+rpn_holdreg3_q'length-1), + din => rpn_holdreg3_d(0 to 63), + dout => rpn_holdreg3_q(0 to 63) ); +entry_valid_latch: tri_rlmreg_p + generic map (width => entry_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => entry_valid_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(entry_valid_offset to entry_valid_offset+entry_valid_q'length-1), + scout => sov_1(entry_valid_offset to entry_valid_offset+entry_valid_q'length-1), + din => entry_valid, + dout => entry_valid_q ); +entry_match_latch: tri_rlmreg_p + generic map (width => entry_match_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => entry_match_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(entry_match_offset to entry_match_offset+entry_match_q'length-1), + scout => sov_1(entry_match_offset to entry_match_offset+entry_match_q'length-1), + din => entry_match, + dout => entry_match_q ); +watermark_latch: tri_rlmreg_p + generic map (width => watermark_q'length, init => 29, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex6_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(watermark_offset to watermark_offset+watermark_q'length-1), + scout => sov_1(watermark_offset to watermark_offset+watermark_q'length-1), + din => watermark_d(0 to watermark_width-1), + dout => watermark_q(0 to watermark_width-1) ); +mmucr1_b0_cpy_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mmucr1_b0_cpy_offset), + scout => sov_1(mmucr1_b0_cpy_offset), + din => mmucr1_b0_cpy_d, + dout => mmucr1_b0_cpy_q); +lru_rmt_vec_latch: tri_rlmreg_p + generic map (width => lru_rmt_vec_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex6_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(lru_rmt_vec_offset to lru_rmt_vec_offset+lru_rmt_vec_q'length-1), + scout => sov_1(lru_rmt_vec_offset to lru_rmt_vec_offset+lru_rmt_vec_q'length-1), + din => lru_rmt_vec_d, + dout => lru_rmt_vec_q ); +eptr_latch: tri_rlmreg_p + generic map (width => eptr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => mmucr1_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(eptr_offset to eptr_offset+eptr_q'length-1), + scout => sov_1(eptr_offset to eptr_offset+eptr_q'length-1), + din => eptr_d(0 to eptr_width-1), + dout => eptr_q(0 to eptr_width-1) ); +lru_latch: tri_rlmreg_p + generic map (width => lru_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lru_update_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(lru_offset to lru_offset+lru_q'length-1), + scout => sov_1(lru_offset to lru_offset+lru_q'length-1), + din => lru_d(1 to lru_width), + dout => lru_q(1 to lru_width) ); +lru_update_event_latch: tri_rlmreg_p + generic map (width => lru_update_event_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => not_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(lru_update_event_offset to lru_update_event_offset+lru_update_event_q'length-1), + scout => sov_1(lru_update_event_offset to lru_update_event_offset+lru_update_event_q'length-1), + din => lru_update_event_d, + dout => lru_update_event_q ); +lru_debug_latch: tri_rlmreg_p + generic map (width => lru_debug_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => trace_bus_enable_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(lru_debug_offset to lru_debug_offset+lru_debug_q'length-1), + scout => sov_1(lru_debug_offset to lru_debug_offset+lru_debug_q'length-1), + din => lru_debug_d, + dout => lru_debug_q ); +snoop_val_latch: tri_rlmreg_p + generic map (width => snoop_val_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(snoop_val_offset to snoop_val_offset+snoop_val_q'length-1), + scout => sov_1(snoop_val_offset to snoop_val_offset+snoop_val_q'length-1), + din => snoop_val_d, + dout => snoop_val_q ); +snoop_attr_latch: tri_rlmreg_p + generic map (width => snoop_attr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => snoop_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(snoop_attr_offset to snoop_attr_offset+snoop_attr_q'length-1), + scout => sov_1(snoop_attr_offset to snoop_attr_offset+snoop_attr_q'length-1), + din => snoop_attr_d, + dout => snoop_attr_q ); +snoop_addr_latch: tri_rlmreg_p + generic map (width => snoop_addr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => snoop_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(snoop_addr_offset to snoop_addr_offset+snoop_addr_q'length-1), + scout => sov_1(snoop_addr_offset to snoop_addr_offset+snoop_addr_q'length-1), + din => snoop_addr_d(52-epn_width to 51), + dout => snoop_addr_q(52-epn_width to 51) ); +ex2_epn_latch: tri_rlmreg_p + generic map (width => ex2_epn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ex2_epn_offset to ex2_epn_offset+ex2_epn_q'length-1), + scout => sov_1(ex2_epn_offset to ex2_epn_offset+ex2_epn_q'length-1), + din => ex2_epn_d(52-ex2_epn_width to 51), + dout => ex2_epn_q(52-ex2_epn_width to 51) ); +por_seq_latch: tri_rlmreg_p + generic map (width => por_seq_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(por_seq_offset to por_seq_offset+por_seq_q'length-1), + scout => sov_1(por_seq_offset to por_seq_offset+por_seq_q'length-1), + din => por_seq_d(0 to por_seq_width-1), + dout => por_seq_q(0 to por_seq_width-1) ); +pc_xu_init_reset_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(pc_xu_init_reset_offset), + scout => sov_1(pc_xu_init_reset_offset), + din => pc_xu_init_reset, + dout => pc_xu_init_reset_q); +tlb_rel_val_latch: tri_rlmreg_p + generic map (width => tlb_rel_val_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(tlb_rel_val_offset to tlb_rel_val_offset+tlb_rel_val_q'length-1), + scout => sov_1(tlb_rel_val_offset to tlb_rel_val_offset+tlb_rel_val_q'length-1), + din => tlb_rel_val_d, + dout => tlb_rel_val_q ); +tlb_rel_data_latch: tri_rlmreg_p + generic map (width => tlb_rel_data_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_rel_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(tlb_rel_data_offset to tlb_rel_data_offset+tlb_rel_data_q'length-1), + scout => sov_1(tlb_rel_data_offset to tlb_rel_data_offset+tlb_rel_data_q'length-1), + din => tlb_rel_data_d, + dout => tlb_rel_data_q ); +eplc_wr_latch: tri_rlmreg_p + generic map (width => eplc_wr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(eplc_wr_offset to eplc_wr_offset+eplc_wr_q'length-1), + scout => sov_1(eplc_wr_offset to eplc_wr_offset+eplc_wr_q'length-1), + din => eplc_wr_d, + dout => eplc_wr_q ); +epsc_wr_latch: tri_rlmreg_p + generic map (width => epsc_wr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(epsc_wr_offset to epsc_wr_offset+epsc_wr_q'length-1), + scout => sov_1(epsc_wr_offset to epsc_wr_offset+epsc_wr_q'length-1), + din => epsc_wr_d, + dout => epsc_wr_q ); +ccr2_frat_paranoia_latch: tri_rlmreg_p + generic map (width => ccr2_frat_paranoia_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ccr2_frat_paranoia_offset to ccr2_frat_paranoia_offset+ccr2_frat_paranoia_q'length-1), + scout => sov_1(ccr2_frat_paranoia_offset to ccr2_frat_paranoia_offset+ccr2_frat_paranoia_q'length-1), + din => ccr2_frat_paranoia_d, + dout => ccr2_frat_paranoia_q ); +ccr2_notlb_latch: tri_rlmlatch_p + generic map (init => 1, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ccr2_notlb_offset), + scout => sov_1(ccr2_notlb_offset), + din => xu_derat_hid_mmu_mode, + dout => ccr2_notlb_q); +xucr4_mmu_mchk_latch: tri_rlmlatch_p + generic map (init => 1, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(xucr4_mmu_mchk_offset), + scout => sov_1(xucr4_mmu_mchk_offset), + din => spr_xucr4_mmu_mchk, + dout => xucr4_mmu_mchk_q); +clkg_ctl_override_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(clkg_ctl_override_offset), + scout => sov_1(clkg_ctl_override_offset), + din => clkg_ctl_override_d, + dout => clkg_ctl_override_q); +rf1_stg_act_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(rf1_stg_act_offset), + scout => sov_1(rf1_stg_act_offset), + din => rf1_stg_act_d, + dout => rf1_stg_act_q); +ex1_stg_act_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ex1_stg_act_offset), + scout => sov_1(ex1_stg_act_offset), + din => ex1_stg_act_d, + dout => ex1_stg_act_q); +ex2_stg_act_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ex2_stg_act_offset), + scout => sov_1(ex2_stg_act_offset), + din => ex2_stg_act_d, + dout => ex2_stg_act_q); +ex3_stg_act_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ex3_stg_act_offset), + scout => sov_1(ex3_stg_act_offset), + din => ex3_stg_act_d, + dout => ex3_stg_act_q); +ex4_stg_act_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ex4_stg_act_offset), + scout => sov_1(ex4_stg_act_offset), + din => ex4_stg_act_d, + dout => ex4_stg_act_q); +ex5_stg_act_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ex5_stg_act_offset), + scout => sov_1(ex5_stg_act_offset), + din => ex5_stg_act_d, + dout => ex5_stg_act_q); +ex6_stg_act_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ex6_stg_act_offset), + scout => sov_1(ex6_stg_act_offset), + din => ex6_stg_act_d, + dout => ex6_stg_act_q); +ex7_stg_act_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ex7_stg_act_offset), + scout => sov_1(ex7_stg_act_offset), + din => ex7_stg_act_d, + dout => ex7_stg_act_q); +tlb_rel_act_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(tlb_rel_act_offset), + scout => sov_1(tlb_rel_act_offset), + din => tlb_rel_act_d, + dout => tlb_rel_act_q); +snoop_act_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(snoop_act_offset), + scout => sov_1(snoop_act_offset), + din => mm_xu_derat_snoop_coming, + dout => snoop_act_q); +trace_bus_enable_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(trace_bus_enable_offset), + scout => sov_1(trace_bus_enable_offset), + din => pc_xu_trace_bus_enable, + dout => trace_bus_enable_q); +an_ac_grffence_en_dc_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(an_ac_grffence_en_dc_offset), + scout => sov_1(an_ac_grffence_en_dc_offset), + din => an_ac_grffence_en_dc_q, + dout => an_ac_grffence_en_dc_q); +spare_a_latch: tri_rlmreg_p + generic map (width => spare_a_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spare_a_offset to spare_a_offset+spare_a_q'length-1), + scout => sov_0(spare_a_offset to spare_a_offset+spare_a_q'length-1), + din => spare_a_q, + dout => spare_a_q ); +spare_b_latch: tri_rlmreg_p + generic map (width => spare_b_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spare_b_offset to spare_b_offset+spare_b_q'length-1), + scout => sov_1(spare_b_offset to spare_b_offset+spare_b_q'length-1), + din => spare_b_q, + dout => spare_b_q ); +mpg_bcfg_gen: if expand_type /= 1 generate +bcfg_epn_0to15_latch: tri_slat_scan + generic map (width => 16, init => std_ulogic_vector( to_unsigned( bcfg_epn_0to15, 16 ) ), + reset_inverts_scan => true, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + dclk => lcb_dclk, + lclk => lcb_lclk, + scan_in => bsiv(bcfg_offset to bcfg_offset+15), + scan_out => bsov(bcfg_offset to bcfg_offset+15), + q => bcfg_q(0 to 15), + q_b => bcfg_q_b(0 to 15) ); +bcfg_epn_16to31_latch: tri_slat_scan + generic map (width => 16, init => std_ulogic_vector( to_unsigned( bcfg_epn_16to31, 16 ) ), + reset_inverts_scan => true, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + dclk => lcb_dclk, + lclk => lcb_lclk, + scan_in => bsiv(bcfg_offset+16 to bcfg_offset+31), + scan_out => bsov(bcfg_offset+16 to bcfg_offset+31), + q => bcfg_q(16 to 31), + q_b => bcfg_q_b(16 to 31) ); +bcfg_epn_32to47_latch: tri_slat_scan + generic map (width => 16, init => std_ulogic_vector( to_unsigned( bcfg_epn_32to47, 16 ) ), + reset_inverts_scan => true, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + dclk => lcb_dclk, + lclk => lcb_lclk, + scan_in => bsiv(bcfg_offset+32 to bcfg_offset+47), + scan_out => bsov(bcfg_offset+32 to bcfg_offset+47), + q => bcfg_q(32 to 47), + q_b => bcfg_q_b(32 to 47) ); +bcfg_epn_48to51_latch: tri_slat_scan + generic map (width => 4, init => std_ulogic_vector( to_unsigned( bcfg_epn_48to51, 4 ) ), + reset_inverts_scan => true, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + dclk => lcb_dclk, + lclk => lcb_lclk, + scan_in => bsiv(bcfg_offset+48 to bcfg_offset+51), + scan_out => bsov(bcfg_offset+48 to bcfg_offset+51), + q => bcfg_q(48 to 51), + q_b => bcfg_q_b(48 to 51) ); +bcfg_rpn_22to31_latch: tri_slat_scan + generic map (width => 10, init => std_ulogic_vector( to_unsigned( bcfg_rpn_22to31, 10 ) ), + reset_inverts_scan => true, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + dclk => lcb_dclk, + lclk => lcb_lclk, + scan_in => bsiv(bcfg_offset+52 to bcfg_offset+61), + scan_out => bsov(bcfg_offset+52 to bcfg_offset+61), + q => bcfg_q(52 to 61), + q_b => bcfg_q_b(52 to 61) ); +bcfg_rpn_32to47_latch: tri_slat_scan + generic map (width => 16, init => std_ulogic_vector( to_unsigned( bcfg_rpn_32to47, 16 ) ), + reset_inverts_scan => true, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + dclk => lcb_dclk, + lclk => lcb_lclk, + scan_in => bsiv(bcfg_offset+62 to bcfg_offset+77), + scan_out => bsov(bcfg_offset+62 to bcfg_offset+77), + q => bcfg_q(62 to 77), + q_b => bcfg_q_b(62 to 77) ); +bcfg_rpn_48to51_latch: tri_slat_scan + generic map (width => 4, init => std_ulogic_vector( to_unsigned( bcfg_rpn_48to51, 4 ) ), + reset_inverts_scan => true, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + dclk => lcb_dclk, + lclk => lcb_lclk, + scan_in => bsiv(bcfg_offset+78 to bcfg_offset+81), + scan_out => bsov(bcfg_offset+78 to bcfg_offset+81), + q => bcfg_q(78 to 81), + q_b => bcfg_q_b(78 to 81) ); +bcfg_attr_latch: tri_slat_scan + generic map (width => 5, init => std_ulogic_vector( to_unsigned( bcfg_attr, 5 ) ), + reset_inverts_scan => true, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + dclk => lcb_dclk, + lclk => lcb_lclk, + scan_in => bsiv(bcfg_offset+82 to bcfg_offset+86), + scan_out => bsov(bcfg_offset+82 to bcfg_offset+86), + q => bcfg_q(82 to 86), + q_b => bcfg_q_b(82 to 86) ); +bcfg_rpn2_32to47_latch: tri_slat_scan + generic map (width => 16, init => std_ulogic_vector( to_unsigned( bcfg_rpn2_32to47, 16 ) ), + reset_inverts_scan => true, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + dclk => lcb_dclk, + lclk => lcb_lclk, + scan_in => bsiv(bcfg_offset+87 to bcfg_offset+102), + scan_out => bsov(bcfg_offset+87 to bcfg_offset+102), + q => bcfg_q(87 to 102), + q_b => bcfg_q_b(87 to 102) ); +bcfg_rpn2_48to51_latch: tri_slat_scan + generic map (width => 4, init => std_ulogic_vector( to_unsigned( bcfg_rpn2_48to51, 4 ) ), + reset_inverts_scan => true, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + dclk => lcb_dclk, + lclk => lcb_lclk, + scan_in => bsiv(bcfg_offset+103 to bcfg_offset+106), + scan_out => bsov(bcfg_offset+103 to bcfg_offset+106), + q => bcfg_q(103 to 106), + q_b => bcfg_q_b(103 to 106) ); +bcfg_spare_latch: tri_slat_scan + generic map (width => 16, init => std_ulogic_vector( to_unsigned( 0, 16 ) ), + reset_inverts_scan => true, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + dclk => lcb_dclk, + lclk => lcb_lclk, + scan_in => bsiv(bcfg_offset+107 to bcfg_offset+122), + scan_out => bsov(bcfg_offset+107 to bcfg_offset+122), + q => bcfg_q(107 to 122), + q_b => bcfg_q_b(107 to 122) ); +end generate mpg_bcfg_gen; +fpga_bcfg_gen: if expand_type = 1 generate +bcfg_epn_0to15_latch: tri_rlmreg_p + generic map (width => 16, init => bcfg_epn_0to15, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(0 to 15), + scout => bsov(0 to 15), + din => bcfg_q(0 to 15), + dout => bcfg_q(0 to 15) ); +bcfg_epn_16to31_latch: tri_rlmreg_p + generic map (width => 16, init => bcfg_epn_16to31, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(16 to 31), + scout => bsov(16 to 31), + din => bcfg_q(16 to 31), + dout => bcfg_q(16 to 31) ); +bcfg_epn_32to47_latch: tri_rlmreg_p + generic map (width => 16, init => bcfg_epn_32to47, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(32 to 47), + scout => bsov(32 to 47), + din => bcfg_q(32 to 47), + dout => bcfg_q(32 to 47) ); +bcfg_epn_48to51_latch: tri_rlmreg_p + generic map (width => 4, init => bcfg_epn_48to51, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(48 to 51), + scout => bsov(48 to 51), + din => bcfg_q(48 to 51), + dout => bcfg_q(48 to 51) ); +bcfg_rpn_22to31_latch: tri_rlmreg_p + generic map (width => 10, init => bcfg_rpn_22to31, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(52 to 61), + scout => bsov(52 to 61), + din => bcfg_q(52 to 61), + dout => bcfg_q(52 to 61) ); +bcfg_rpn_32to47_latch: tri_rlmreg_p + generic map (width => 16, init => bcfg_rpn_32to47, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(62 to 77), + scout => bsov(62 to 77), + din => bcfg_q(62 to 77), + dout => bcfg_q(62 to 77) ); +bcfg_rpn_48to51_latch: tri_rlmreg_p + generic map (width => 4, init => bcfg_rpn_48to51, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(78 to 81), + scout => bsov(78 to 81), + din => bcfg_q(78 to 81), + dout => bcfg_q(78 to 81) ); +bcfg_attr_latch: tri_rlmreg_p + generic map (width => 5, init => bcfg_attr, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(82 to 86), + scout => bsov(82 to 86), + din => bcfg_q(82 to 86), + dout => bcfg_q(82 to 86) ); +bcfg_rpn2_32to47_latch: tri_rlmreg_p + generic map (width => 16, init => bcfg_rpn2_32to47, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(87 to 102), + scout => bsov(87 to 102), + din => bcfg_q(87 to 102), + dout => bcfg_q(87 to 102) ); +bcfg_rpn2_48to51_latch: tri_rlmreg_p + generic map (width => 4, init => bcfg_rpn2_48to51, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(103 to 106), + scout => bsov(103 to 106), + din => bcfg_q(103 to 106), + dout => bcfg_q(103 to 106) ); +bcfg_spare_latch: tri_rlmreg_p + generic map (width => 16, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(107 to 122), + scout => bsov(107 to 122), + din => bcfg_q(107 to 122), + dout => bcfg_q(107 to 122) ); +end generate fpga_bcfg_gen; +perv_2to1_reg: tri_plat + generic map (width => 4, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_xu_ccflush_dc, + din(0) => pc_func_sl_thold_2, + din(1) => pc_func_slp_sl_thold_2, + din(2) => pc_cfg_slp_sl_thold_2, + din(3) => pc_sg_2, + q(0) => pc_func_sl_thold_1, + q(1) => pc_func_slp_sl_thold_1, + q(2) => pc_cfg_slp_sl_thold_1, + q(3) => pc_sg_1); +perv_1to0_reg: tri_plat + generic map (width => 4, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_xu_ccflush_dc, + din(0) => pc_func_sl_thold_1, + din(1) => pc_func_slp_sl_thold_1, + din(2) => pc_cfg_slp_sl_thold_1, + din(3) => pc_sg_1, + q(0) => pc_func_sl_thold_0, + q(1) => pc_func_slp_sl_thold_0, + q(2) => pc_cfg_slp_sl_thold_0, + q(3) => pc_sg_0); +perv_lcbor_func_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b, + thold => pc_func_sl_thold_0, + sg => pc_sg_0, + act_dis => lcb_act_dis_dc, + forcee => pc_func_sl_force, + thold_b => pc_func_sl_thold_0_b); +perv_lcbor_func_slp_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b, + thold => pc_func_slp_sl_thold_0, + sg => pc_sg_0, + act_dis => lcb_act_dis_dc, + forcee => pc_func_slp_sl_force, + thold_b => pc_func_slp_sl_thold_0_b); +mpg_bcfg_lcb_gen: if expand_type /= 1 generate +bcfg_lcb: tri_lcbs + generic map (expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + delay_lclkr => lcb_delay_lclkr_dc(0), + nclk => nclk, + forcee => pc_cfg_slp_sl_force, + thold_b => pc_cfg_slp_sl_thold_0_b, + dclk => lcb_dclk, + lclk => lcb_lclk ); +pc_cfg_slp_sl_thold_0_b <= NOT pc_cfg_slp_sl_thold_0; +pc_cfg_slp_sl_force <= pc_sg_0; +end generate mpg_bcfg_lcb_gen; +fpga_bcfg_lcb_gen: if expand_type = 1 generate +perv_lcbor_cfg_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b, + thold => pc_cfg_slp_sl_thold_0, + sg => pc_sg_0, + act_dis => lcb_act_dis_dc, + forcee => pc_cfg_slp_sl_force, + thold_b => pc_cfg_slp_sl_thold_0_b); +end generate fpga_bcfg_lcb_gen; +siv_0(0 TO scan_right_0) <= sov_0(1 to scan_right_0) & ac_func_scan_in(0); +func_si_cam_int <= sov_0(0); +ac_func_scan_out(0) <= func_so_cam_int; +siv_1(0 TO scan_right_1) <= sov_1(1 to scan_right_1) & ac_func_scan_in(1); +ac_func_scan_out(1) <= sov_1(0); +bsiv(0 TO boot_scan_right) <= bsov(1 to boot_scan_right) & ac_ccfg_scan_in; +ac_ccfg_scan_out <= bsov(0); +END XUQ_LSU_DERAT; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_dir.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_dir.vhdl new file mode 100644 index 0000000..8f2f168 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_dir.vhdl @@ -0,0 +1,2120 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ibm, ieee, work, tri, support; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use tri.tri_latches_pkg.all; +use support.power_logic_pkg.all; + +entity xuq_lsu_dir is +generic(expand_type : integer := 2; + l_endian_m : integer := 1; + regmode : integer := 6; + lmq_entries : integer := 8; + dc_size : natural := 14; + cl_size : natural := 6; + wayDataSize : natural := 35; + real_data_add : integer := 42); +port( + + xu_lsu_rf0_act :in std_ulogic; + xu_lsu_rf1_cmd_act :in std_ulogic; + xu_lsu_rf1_axu_op_val :in std_ulogic; + xu_lsu_rf1_axu_ldst_falign :in std_ulogic; + xu_lsu_rf1_axu_ldst_fexcpt :in std_ulogic; + xu_lsu_rf1_cache_acc :in std_ulogic; + xu_lsu_rf1_thrd_id :in std_ulogic_vector(0 to 3); + xu_lsu_rf1_optype1 :in std_ulogic; + xu_lsu_rf1_optype2 :in std_ulogic; + xu_lsu_rf1_optype4 :in std_ulogic; + xu_lsu_rf1_optype8 :in std_ulogic; + xu_lsu_rf1_optype16 :in std_ulogic; + xu_lsu_rf1_optype32 :in std_ulogic; + xu_lsu_rf1_target_gpr :in std_ulogic_vector(0 to 8); + xu_lsu_rf1_mtspr_trace :in std_ulogic; + xu_lsu_rf1_load_instr :in std_ulogic; + xu_lsu_rf1_store_instr :in std_ulogic; + xu_lsu_rf1_dcbf_instr :in std_ulogic; + xu_lsu_rf1_sync_instr :in std_ulogic; + xu_lsu_rf1_l_fld :in std_ulogic_vector(0 to 1); + xu_lsu_rf1_dcbi_instr :in std_ulogic; + xu_lsu_rf1_dcbz_instr :in std_ulogic; + xu_lsu_rf1_dcbt_instr :in std_ulogic; + xu_lsu_rf1_dcbtst_instr :in std_ulogic; + xu_lsu_rf1_th_fld :in std_ulogic_vector(0 to 4); + xu_lsu_rf1_dcbtls_instr :in std_ulogic; + xu_lsu_rf1_dcbtstls_instr :in std_ulogic; + xu_lsu_rf1_dcblc_instr :in std_ulogic; + xu_lsu_rf1_dcbst_instr :in std_ulogic; + xu_lsu_rf1_icbi_instr :in std_ulogic; + xu_lsu_rf1_icblc_instr :in std_ulogic; + xu_lsu_rf1_icbt_instr :in std_ulogic; + xu_lsu_rf1_icbtls_instr :in std_ulogic; + xu_lsu_rf1_icswx_instr :in std_ulogic; + xu_lsu_rf1_icswx_dot_instr :in std_ulogic; + xu_lsu_rf1_icswx_epid :in std_ulogic; + xu_lsu_rf1_tlbsync_instr :in std_ulogic; + xu_lsu_rf1_ldawx_instr :in std_ulogic; + xu_lsu_rf1_wclr_instr :in std_ulogic; + xu_lsu_rf1_wchk_instr :in std_ulogic; + xu_lsu_rf1_lock_instr :in std_ulogic; + xu_lsu_rf1_mutex_hint :in std_ulogic; + xu_lsu_rf1_mbar_instr :in std_ulogic; + xu_lsu_rf1_is_msgsnd :in std_ulogic; + xu_lsu_rf1_dci_instr :in std_ulogic; + xu_lsu_rf1_ici_instr :in std_ulogic; + xu_lsu_rf1_algebraic :in std_ulogic; + xu_lsu_rf1_byte_rev :in std_ulogic; + xu_lsu_rf1_src_gpr :in std_ulogic; + xu_lsu_rf1_src_axu :in std_ulogic; + xu_lsu_rf1_src_dp :in std_ulogic; + xu_lsu_rf1_targ_gpr :in std_ulogic; + xu_lsu_rf1_targ_axu :in std_ulogic; + xu_lsu_rf1_targ_dp :in std_ulogic; + xu_lsu_ex4_val :in std_ulogic_vector(0 to 3); + xu_lsu_ex1_add_src0 :in std_ulogic_vector(64-(2**REGMODE) to 63); + xu_lsu_ex1_add_src1 :in std_ulogic_vector(64-(2**REGMODE) to 63); + + xu_lsu_rf1_src0_vld :in std_ulogic; + xu_lsu_rf1_src0_reg :in std_ulogic_vector(0 to 7); + xu_lsu_rf1_src1_vld :in std_ulogic; + xu_lsu_rf1_src1_reg :in std_ulogic_vector(0 to 7); + xu_lsu_rf1_targ_vld :in std_ulogic; + xu_lsu_rf1_targ_reg :in std_ulogic_vector(0 to 7); + + pc_xu_inj_dcachedir_parity :in std_ulogic; + pc_xu_inj_dcachedir_multihit :in std_ulogic; + + ex3_wimge_w_bit :in std_ulogic; + ex3_wimge_i_bit :in std_ulogic; + ex3_wimge_e_bit :in std_ulogic; + ex3_p_addr :in std_ulogic_vector(64-real_data_add to 51); + derat_xu_ex3_noop_touch :in std_ulogic_vector(0 to 3); + ex3_ld_queue_full :in std_ulogic; + ex3_stq_flush :in std_ulogic; + ex3_ig_flush :in std_ulogic; + + ex2_lm_dep_hit :in std_ulogic; + + ex3_way_cmp_a :in std_ulogic; + ex3_way_cmp_b :in std_ulogic; + ex3_way_cmp_c :in std_ulogic; + ex3_way_cmp_d :in std_ulogic; + ex3_way_cmp_e :in std_ulogic; + ex3_way_cmp_f :in std_ulogic; + ex3_way_cmp_g :in std_ulogic; + ex3_way_cmp_h :in std_ulogic; + + ex3_wayA_tag :in std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex3_wayB_tag :in std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex3_wayC_tag :in std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex3_wayD_tag :in std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex3_wayE_tag :in std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex3_wayF_tag :in std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex3_wayG_tag :in std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex3_wayH_tag :in std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + + xu_lsu_mtspr_trace_en :in std_ulogic_vector(0 to 3); + spr_xucr0_clkg_ctl_b1 :in std_ulogic; + xu_lsu_spr_xucr0_aflsta :in std_ulogic; + xu_lsu_spr_xucr0_flsta :in std_ulogic; + xu_lsu_spr_xucr0_l2siw :in std_ulogic; + xu_lsu_spr_xucr0_dcdis :in std_ulogic; + xu_lsu_spr_xucr0_wlk :in std_ulogic; + xu_lsu_spr_ccr2_dfrat :in std_ulogic; + xu_lsu_spr_xucr0_clfc :in std_ulogic; + xu_lsu_spr_xucr0_flh2l2 :in std_ulogic; + xu_lsu_spr_xucr0_cls :in std_ulogic; + xu_lsu_spr_msr_cm :in std_ulogic_vector(0 to 3); + + xu_lsu_msr_gs :in std_ulogic_vector(0 to 3); + xu_lsu_msr_pr :in std_ulogic_vector(0 to 3); + + an_ac_flh2l2_gate :in std_ulogic; + + ldq_rel1_early_v :in std_ulogic; + ldq_rel1_val :in std_ulogic; + ldq_rel_mid_val :in std_ulogic; + ldq_rel_retry_val :in std_ulogic; + ldq_rel3_early_v :in std_ulogic; + ldq_rel3_val :in std_ulogic; + ldq_rel_back_invalidated :in std_ulogic; + ldq_rel_data_val_early :in std_ulogic; + rel_data_val :in std_ulogic; + ldq_rel_tag :in std_ulogic_vector(1 to 3); + ldq_rel_tag_early :in std_ulogic_vector(1 to 3); + ldq_rel_set_val :in std_ulogic; + ldq_rel_ecc_err :in std_ulogic; + ldq_rel_classid :in std_ulogic_vector(0 to 1); + ldq_rel_lock_en :in std_ulogic; + ldq_rel_l1dump_cslc :in std_ulogic; + ldq_rel3_l1dump_val :in std_ulogic; + ldq_rel_watch_en :in std_ulogic; + ldq_rel_addr :in std_ulogic_vector(64-real_data_add to 52); + ldq_rel_addr_early :in std_ulogic_vector(64-real_data_add to 63-cl_size); + ldq_recirc_rel_val :out std_ulogic; + + xu_lsu_dci :in std_ulogic; + + is2_l2_inv_val :in std_ulogic; + + ex6_ld_par_err :in std_ulogic; + + xu_lsu_rf1_flush :in std_ulogic_vector(0 to 3); + xu_lsu_ex1_flush :in std_ulogic_vector(0 to 3); + xu_lsu_ex2_flush :in std_ulogic_vector(0 to 3); + xu_lsu_ex3_flush :in std_ulogic_vector(0 to 3); + xu_lsu_ex4_flush :in std_ulogic_vector(0 to 3); + xu_lsu_ex5_flush :in std_ulogic_vector(0 to 3); + + xu_lsu_slowspr_val :in std_ulogic; + xu_lsu_slowspr_rw :in std_ulogic; + xu_lsu_slowspr_etid :in std_ulogic_vector(0 to 1); + xu_lsu_slowspr_addr :in std_ulogic_vector(0 to 9); + xu_lsu_slowspr_data :in std_ulogic_vector(64-(2**REGMODE) to 63); + xu_lsu_slowspr_done :in std_ulogic; + slowspr_val_out :out std_ulogic; + slowspr_rw_out :out std_ulogic; + slowspr_etid_out :out std_ulogic_vector(0 to 1); + slowspr_addr_out :out std_ulogic_vector(0 to 9); + slowspr_data_out :out std_ulogic_vector(64-(2**REGMODE) to 63); + slowspr_done_out :out std_ulogic; + + ldq_rel_axu_val :in std_ulogic; + ldq_rel_thrd_id :in std_ulogic_vector(0 to 3); + ldq_rel_ta_gpr :in std_ulogic_vector(0 to 8); + ldq_rel_upd_gpr :in std_ulogic; + ldq_rel_ci :in std_ulogic; + + dir_arr_rd_addr_01 :out std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + dir_arr_rd_addr_23 :out std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + dir_arr_rd_addr_45 :out std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + dir_arr_rd_addr_67 :out std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + dir_arr_rd_data :in std_ulogic_vector(0 to 8*wayDataSize-1); + + dir_wr_enable :out std_ulogic_vector(0 to 3); + dir_wr_way :out std_ulogic_vector(0 to 7); + dir_arr_wr_addr :out std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + dir_arr_wr_data :out std_ulogic_vector(64-real_data_add to 64-real_data_add+wayDataSize-1); + + ex1_src0_vld :out std_ulogic; + ex1_src0_reg :out std_ulogic_vector(0 to 7); + ex1_src1_vld :out std_ulogic; + ex1_src1_reg :out std_ulogic_vector(0 to 7); + ex1_targ_vld :out std_ulogic; + ex1_targ_reg :out std_ulogic_vector(0 to 7); + ex1_check_watch :out std_ulogic_vector(0 to 3); + + ex3_cache_acc :out std_ulogic; + ex1_optype1 :out std_ulogic; + ex1_optype2 :out std_ulogic; + ex1_optype4 :out std_ulogic; + ex1_optype8 :out std_ulogic; + ex1_optype16 :out std_ulogic; + ex1_optype32 :out std_ulogic; + ex1_saxu_instr :out std_ulogic; + ex1_sdp_instr :out std_ulogic; + ex1_stgpr_instr :out std_ulogic; + ex1_store_instr :out std_ulogic; + ex1_axu_op_val :out std_ulogic; + + lsu_xu_ex3_align :out std_ulogic_vector(0 to 3); + lsu_xu_ex3_dsi :out std_ulogic_vector(0 to 3); + lsu_xu_ex3_inval_align_2ucode :out std_ulogic; + + ex3_stg_flush :out std_ulogic; + ex4_stg_flush :out std_ulogic; + lsu_xu_ex3_n_flush_req :out std_ulogic; + lsu_xu_ex4_ldq_full_flush :out std_ulogic; + lsu_xu_ex3_dep_flush :out std_ulogic; + + xu_derat_ex1_epn_arr :out std_ulogic_vector(64-(2**regmode) to 51); + xu_derat_ex1_epn_nonarr :out std_ulogic_vector(64-(2**regmode) to 51); + snoop_addr :in std_ulogic_vector(64-(2**regmode) to 51); + snoop_addr_sel :in std_ulogic; + xu_derat_rf1_binv_val :out std_ulogic; + ex3_req_thrd_id :out std_ulogic_vector(0 to 3); + ex3_target_gpr :out std_ulogic_vector(0 to 8); + ex3_dcbt_instr :out std_ulogic; + ex3_dcbtst_instr :out std_ulogic; + ex3_th_fld_l2 :out std_ulogic; + ex3_dcbst_instr :out std_ulogic; + ex3_dcbf_instr :out std_ulogic; + ex3_sync_instr :out std_ulogic; + ex3_mtspr_trace :out std_ulogic; + ex3_byte_en :out std_ulogic_vector(0 to 31); + ex3_l_fld :out std_ulogic_vector(0 to 1); + ex3_dcbi_instr :out std_ulogic; + ex3_dcbz_instr :out std_ulogic; + ex3_icbi_instr :out std_ulogic; + ex3_icswx_instr :out std_ulogic; + ex3_icswx_dot :out std_ulogic; + ex3_icswx_epid :out std_ulogic; + ex3_mbar_instr :out std_ulogic; + ex3_msgsnd_instr :out std_ulogic; + ex3_dci_instr :out std_ulogic; + ex3_ici_instr :out std_ulogic; + ex3_load_instr :out std_ulogic; + ex3_store_instr :out std_ulogic; + ex3_axu_op_val :out std_ulogic; + ex3_algebraic :out std_ulogic; + ex3_dcbtls_instr :out std_ulogic; + ex3_dcbtstls_instr :out std_ulogic; + ex3_dcblc_instr :out std_ulogic; + ex3_icblc_instr :out std_ulogic; + ex3_icbt_instr :out std_ulogic; + ex3_icbtls_instr :out std_ulogic; + ex3_tlbsync_instr :out std_ulogic; + ex3_local_dcbf :out std_ulogic; + ex3_lock_en :out std_ulogic; + ex4_drop_rel :out std_ulogic; + ex3_load_l1hit :out std_ulogic; + ex3_rotate_sel :out std_ulogic_vector(0 to 4); + ex3_watch_en :out std_ulogic; + ex3_data_swap :out std_ulogic; + ex3_blkable_touch :out std_ulogic; + ex7_targ_match :out std_ulogic; + ex8_targ_match :out std_ulogic; + ex4_ld_entry :out std_ulogic_vector(0 to 67); + + ex3_cache_inh :out std_ulogic; + ex3_l_s_q_val :out std_ulogic; + ex3_drop_ld_req :out std_ulogic; + ex3_drop_touch :out std_ulogic; + ex3_stx_instr :out std_ulogic; + ex3_larx_instr :out std_ulogic; + ex3_mutex_hint :out std_ulogic; + ex3_opsize :out std_ulogic_vector(0 to 5); + ex4_dir_perr_det :out std_ulogic; + ex4_dir_multihit_det :out std_ulogic; + ex4_n_lsu_ddmh_flush :out std_ulogic_vector(0 to 3); + + ex2_p_addr_lwr :out std_ulogic_vector(52 to 57); + ex3_p_addr_lwr :out std_ulogic_vector(58 to 63); + dcpar_err_flush :out std_ulogic; + pe_recov_begin :out std_ulogic; + + lsu_xu_ex3_ddir_par_err :out std_ulogic; + ex3_cClass_collision :in std_ulogic; + + ex3_cClass_upd_way_a :out std_ulogic; + ex3_cClass_upd_way_b :out std_ulogic; + ex3_cClass_upd_way_c :out std_ulogic; + ex3_cClass_upd_way_d :out std_ulogic; + ex3_cClass_upd_way_e :out std_ulogic; + ex3_cClass_upd_way_f :out std_ulogic; + ex3_cClass_upd_way_g :out std_ulogic; + ex3_cClass_upd_way_h :out std_ulogic; + + ex2_wayA_tag :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex2_wayB_tag :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex2_wayC_tag :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex2_wayD_tag :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex2_wayE_tag :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex2_wayF_tag :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex2_wayG_tag :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex2_wayH_tag :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + + rel_upd_dcarr_val :out std_ulogic; + + lsu_xu_ex4_cr_upd :out std_ulogic; + lsu_xu_ex5_cr_rslt :out std_ulogic; + lsu_xu_ex5_wren :out std_ulogic; + lsu_xu_rel_wren :out std_ulogic; + lsu_xu_rel_ta_gpr :out std_ulogic_vector(0 to 7); + lsu_xu_perf_events :out std_ulogic_vector(0 to 37); + lsu_xu_need_hole :out std_ulogic; + xu_fu_ex5_reload_val :out std_ulogic; + xu_fu_ex5_load_val :out std_ulogic_vector(0 to 3); + xu_fu_ex5_load_tag :out std_ulogic_vector(0 to 8); + + xu_iu_ex6_icbi_val :out std_ulogic_vector(0 to 3); + xu_iu_ex6_icbi_addr :out std_ulogic_vector(64-real_data_add to 57); + + dcarr_up_way_addr :out std_ulogic_vector(0 to 2); + + xu_derat_epsc_wr :out std_ulogic_vector(0 to 3); + xu_derat_eplc_wr :out std_ulogic_vector(0 to 3); + xu_derat_eplc0_epr :out std_ulogic; + xu_derat_eplc0_eas :out std_ulogic; + xu_derat_eplc0_egs :out std_ulogic; + xu_derat_eplc0_elpid :out std_ulogic_vector(40 to 47); + xu_derat_eplc0_epid :out std_ulogic_vector(50 to 63); + xu_derat_eplc1_epr :out std_ulogic; + xu_derat_eplc1_eas :out std_ulogic; + xu_derat_eplc1_egs :out std_ulogic; + xu_derat_eplc1_elpid :out std_ulogic_vector(40 to 47); + xu_derat_eplc1_epid :out std_ulogic_vector(50 to 63); + xu_derat_eplc2_epr :out std_ulogic; + xu_derat_eplc2_eas :out std_ulogic; + xu_derat_eplc2_egs :out std_ulogic; + xu_derat_eplc2_elpid :out std_ulogic_vector(40 to 47); + xu_derat_eplc2_epid :out std_ulogic_vector(50 to 63); + xu_derat_eplc3_epr :out std_ulogic; + xu_derat_eplc3_eas :out std_ulogic; + xu_derat_eplc3_egs :out std_ulogic; + xu_derat_eplc3_elpid :out std_ulogic_vector(40 to 47); + xu_derat_eplc3_epid :out std_ulogic_vector(50 to 63); + xu_derat_epsc0_epr :out std_ulogic; + xu_derat_epsc0_eas :out std_ulogic; + xu_derat_epsc0_egs :out std_ulogic; + xu_derat_epsc0_elpid :out std_ulogic_vector(40 to 47); + xu_derat_epsc0_epid :out std_ulogic_vector(50 to 63); + xu_derat_epsc1_epr :out std_ulogic; + xu_derat_epsc1_eas :out std_ulogic; + xu_derat_epsc1_egs :out std_ulogic; + xu_derat_epsc1_elpid :out std_ulogic_vector(40 to 47); + xu_derat_epsc1_epid :out std_ulogic_vector(50 to 63); + xu_derat_epsc2_epr :out std_ulogic; + xu_derat_epsc2_eas :out std_ulogic; + xu_derat_epsc2_egs :out std_ulogic; + xu_derat_epsc2_elpid :out std_ulogic_vector(40 to 47); + xu_derat_epsc2_epid :out std_ulogic_vector(50 to 63); + xu_derat_epsc3_epr :out std_ulogic; + xu_derat_epsc3_eas :out std_ulogic; + xu_derat_epsc3_egs :out std_ulogic; + xu_derat_epsc3_elpid :out std_ulogic_vector(40 to 47); + xu_derat_epsc3_epid :out std_ulogic_vector(50 to 63); + + ex1_stg_act :out std_ulogic; + ex2_stg_act :out std_ulogic; + ex3_stg_act :out std_ulogic; + ex4_stg_act :out std_ulogic; + binv1_stg_act :out std_ulogic; + binv2_stg_act :out std_ulogic; + + lsu_xu_spr_xucr0_cslc_xuop :out std_ulogic; + lsu_xu_spr_xucr0_cslc_binv :out std_ulogic; + lsu_xu_spr_xucr0_clo :out std_ulogic; + lsu_xu_spr_xucr0_cul :out std_ulogic; + spr_xucr0_cls :out std_ulogic; + + dir_arr_rd_is2_val :out std_ulogic; + dir_arr_rd_congr_cl :out std_ulogic_vector(0 to 4); + + ex4_load_op_hit :out std_ulogic; + ex4_store_hit :out std_ulogic; + ex4_axu_op_val :out std_ulogic; + spr_dvc1_act :out std_ulogic; + spr_dvc2_act :out std_ulogic; + spr_dvc1_dbg :out std_ulogic_vector(64-(2**regmode) to 63); + spr_dvc2_dbg :out std_ulogic_vector(64-(2**regmode) to 63); + + pc_xu_trace_bus_enable :in std_ulogic; + dc_fgen_dbg_data :out std_ulogic_vector(0 to 1); + dc_cntrl_dbg_data :out std_ulogic_vector(0 to 66); + dc_val_dbg_data :out std_ulogic_vector(0 to 293); + dc_lru_dbg_data :out std_ulogic_vector(0 to 81); + dc_dir_dbg_data :out std_ulogic_vector(0 to 35); + dir_arr_dbg_data :out std_ulogic_vector(0 to 60); + + vdd :inout power_logic; + gnd :inout power_logic; + nclk :in clk_logic; + sg_0 :in std_ulogic; + func_sl_thold_0_b :in std_ulogic; + func_sl_force :in std_ulogic; + func_slp_sl_thold_0_b :in std_ulogic; + func_slp_sl_force :in std_ulogic; + func_nsl_thold_0_b :in std_ulogic; + func_nsl_force :in std_ulogic; + func_slp_nsl_thold_0_b :in std_ulogic; + func_slp_nsl_force :in std_ulogic; + d_mode_dc :in std_ulogic; + delay_lclkr_dc :in std_ulogic; + mpw1_dc_b :in std_ulogic; + mpw2_dc_b :in std_ulogic; + scan_in :in std_ulogic_vector(0 to 3); + scan_out :out std_ulogic_vector(0 to 3) +); +-- synopsys translate_off +-- synopsys translate_on +end xuq_lsu_dir; +architecture xuq_lsu_dir of xuq_lsu_dir is + + +constant uprCClassBit :natural := 64-(dc_size-3); +constant lwrCClassBit :natural := 63-cl_size; +constant uprTagBit :natural := 64-real_data_add; +constant lwrTagBit :natural := 63-(dc_size-3); +constant tagSize :natural := lwrTagBit-uprTagBit+1; +constant parExtCalc :natural := 8 - (tagSize mod 8); +constant parBits :natural := (tagSize+parExtCalc) / 8; + +constant lwr_p_addr_offset :natural := 0; +constant ldq_rel1_val_stg_offset :natural := lwr_p_addr_offset + 12; +constant ldq_rel_mid_stg_offset :natural := ldq_rel1_val_stg_offset + 1; +constant ldq_rel3_val_stg_offset :natural := ldq_rel_mid_stg_offset + 1; +constant spr_xucr0_dcdis_offset :natural := ldq_rel3_val_stg_offset + 1; +constant ex4_dir_perr_det_offset :natural := spr_xucr0_dcdis_offset + 1; +constant recirc_rel_val_offset :natural := ex4_dir_perr_det_offset + 1; +constant trace_bus_enable_offset :natural := recirc_rel_val_offset + 1; +constant scan_right :natural := trace_bus_enable_offset + 1 - 1; + +signal ex1_p_addr :std_ulogic_vector(64-(dc_size-3) to 63-cl_size); +signal lwr_p_addr_d :std_ulogic_vector(52 to 63); +signal lwr_p_addr_q :std_ulogic_vector(52 to 63); +signal rel1_val :std_ulogic; +signal rel_mid_val :std_ulogic; +signal rel3_val :std_ulogic; +signal ldq_rel_stg24_val_d :std_ulogic; +signal ldq_rel_stg24_val_q :std_ulogic; +signal rel_st_tag :std_ulogic_vector(1 to 3); +signal rel_st_tag_early :std_ulogic_vector(1 to 3); +signal rel24_addr_d :std_ulogic_vector(64-real_data_add to 52); +signal rel24_addr_q :std_ulogic_vector(64-real_data_add to 52); +signal rel_way_val_a :std_ulogic; +signal rel_way_val_b :std_ulogic; +signal rel_way_val_c :std_ulogic; +signal rel_way_val_d :std_ulogic; +signal rel_way_val_e :std_ulogic; +signal rel_way_val_f :std_ulogic; +signal rel_way_val_g :std_ulogic; +signal rel_way_val_h :std_ulogic; +signal rel_way_lock_a :std_ulogic; +signal rel_way_lock_b :std_ulogic; +signal rel_way_lock_c :std_ulogic; +signal rel_way_lock_d :std_ulogic; +signal rel_way_lock_e :std_ulogic; +signal rel_way_lock_f :std_ulogic; +signal rel_way_lock_g :std_ulogic; +signal rel_way_lock_h :std_ulogic; +signal ex2_is_inval_op :std_ulogic; +signal ex2_lock_set :std_ulogic; +signal ex2_lock_clr :std_ulogic; +signal rel_wayA_wen :std_ulogic; +signal rel_wayB_wen :std_ulogic; +signal rel_wayC_wen :std_ulogic; +signal rel_wayD_wen :std_ulogic; +signal rel_wayE_wen :std_ulogic; +signal rel_wayF_wen :std_ulogic; +signal rel_wayG_wen :std_ulogic; +signal rel_wayH_wen :std_ulogic; +signal ex3_l1hit :std_ulogic; +signal ex4_l1miss :std_ulogic; +signal ex4_way_a_hit :std_ulogic; +signal ex4_way_b_hit :std_ulogic; +signal ex4_way_c_hit :std_ulogic; +signal ex4_way_d_hit :std_ulogic; +signal ex4_way_e_hit :std_ulogic; +signal ex4_way_f_hit :std_ulogic; +signal ex4_way_g_hit :std_ulogic; +signal ex4_way_h_hit :std_ulogic; +signal ex4_way_a_dir :std_ulogic_vector(0 to 5); +signal ex4_way_b_dir :std_ulogic_vector(0 to 5); +signal ex4_way_c_dir :std_ulogic_vector(0 to 5); +signal ex4_way_d_dir :std_ulogic_vector(0 to 5); +signal ex4_way_e_dir :std_ulogic_vector(0 to 5); +signal ex4_way_f_dir :std_ulogic_vector(0 to 5); +signal ex4_way_g_dir :std_ulogic_vector(0 to 5); +signal ex4_way_h_dir :std_ulogic_vector(0 to 5); +signal rel_way_upd_a :std_ulogic; +signal rel_way_upd_b :std_ulogic; +signal rel_way_upd_c :std_ulogic; +signal rel_way_upd_d :std_ulogic; +signal rel_way_upd_e :std_ulogic; +signal rel_way_upd_f :std_ulogic; +signal rel_way_upd_g :std_ulogic; +signal rel_way_upd_h :std_ulogic; +signal rel_way_clr_a :std_ulogic; +signal rel_way_clr_b :std_ulogic; +signal rel_way_clr_c :std_ulogic; +signal rel_way_clr_d :std_ulogic; +signal rel_way_clr_e :std_ulogic; +signal rel_way_clr_f :std_ulogic; +signal rel_way_clr_g :std_ulogic; +signal rel_way_clr_h :std_ulogic; +signal rel4_set_val :std_ulogic; +signal stg_ex2_flush :std_ulogic; +signal stg_ex3_flush :std_ulogic; +signal stg_ex4_flush :std_ulogic; +signal stg_ex5_flush :std_ulogic; +signal ex2_no_lru_upd :std_ulogic; +signal ex3_tag_way_perr :std_ulogic_vector(0 to 7); +signal ex3_cache_en :std_ulogic; +signal rel_lock_en :std_ulogic; +signal rel_l1dump_cslc :std_ulogic; +signal rel3_l1dump_val :std_ulogic; +signal rel1_classid :std_ulogic_vector(0 to 1); +signal dcbtstls_instr_ex3 :std_ulogic; +signal dcbtls_instr_ex3 :std_ulogic; +signal ex1_frc_align2 :std_ulogic; +signal ex1_frc_align4 :std_ulogic; +signal ex1_frc_align8 :std_ulogic; +signal ex1_frc_align16 :std_ulogic; +signal ex1_frc_align32 :std_ulogic; +signal spr_xucr2_rmt :std_ulogic_vector(0 to 31); +signal spr_xucr0_wlck :std_ulogic; +signal ex5_load_op_hit :std_ulogic; +signal ex2_ddir_acc_instr :std_ulogic; +signal ex3_dir_perr_det :std_ulogic; +signal ex4_ldq_full_flush :std_ulogic; +signal rel_up_way_addr_b :std_ulogic_vector(0 to 2); +signal rel_dcarr_addr_en :std_ulogic; +signal rel_dcarr_val_upd :std_ulogic; +signal spr_xucr0_dcdis_d :std_ulogic; +signal spr_xucr0_dcdis_q :std_ulogic; +signal ex2_p_addr_lwr_int :std_ulogic_vector(52 to 63); +signal ex1_thrd_id :std_ulogic_vector(0 to 3); +signal ex2_ldawx_instr :std_ulogic; +signal ex2_wclr_instr :std_ulogic; +signal ex2_wchk_val :std_ulogic; +signal ex2_l_fld :std_ulogic_vector(0 to 1); +signal store_instr_ex2 :std_ulogic; +signal rel_watch_en :std_ulogic; +signal rel_thrd_id :std_ulogic_vector(0 to 3); +signal ex1_l2_inv_val :std_ulogic; +signal ex1_l2_inv_val_b :std_ulogic; +signal ex2_frc_align_d :std_ulogic_vector(59 to 63); +signal ex2_frc_align_q :std_ulogic_vector(59 to 63); +signal ex1_lsu_64bit_agen :std_ulogic; +signal ex1_agen_addr :std_ulogic_vector(64-(2**regmode) to 51); +signal ex1_dir01_addr :std_ulogic_vector(64-(dc_size-3) to 63-cl_size); +signal ex1_dir23_addr :std_ulogic_vector(64-(dc_size-3) to 63-cl_size); +signal ex1_dir45_addr :std_ulogic_vector(64-(dc_size-3) to 63-cl_size); +signal ex1_dir67_addr :std_ulogic_vector(64-(dc_size-3) to 63-cl_size); +signal ex1_eff_addr :std_ulogic_vector(64-(2**regmode) to 63); +signal ex4_dir_perr_det_d :std_ulogic; +signal ex4_dir_perr_det_q :std_ulogic; +signal recirc_rel_val :std_ulogic; +signal recirc_rel_val_d :std_ulogic; +signal recirc_rel_val_q :std_ulogic; +signal ex1_dir_acc_val :std_ulogic; +signal ex1_dir_acc_val_b :std_ulogic; +signal rf1_l2_inv_val :std_ulogic; +signal ex1_agen_binv_val :std_ulogic; +signal dir_wr_enable_int :std_ulogic_vector(0 to 3); +signal dir_arr_wr_addr_int :std_ulogic_vector(64-(dc_size-3) to 63-cl_size); +signal dir_wr_way_int :std_ulogic_vector(0 to 7); +signal dir_arr_wr_data_int :std_ulogic_vector(64-real_data_add to 64-real_data_add+wayDataSize-1); +signal ex1_stg_act_int :std_ulogic; +signal ex2_stg_act_int :std_ulogic; +signal ex3_stg_act_int :std_ulogic; +signal ex4_stg_act_int :std_ulogic; +signal ex5_stg_act_int :std_ulogic; +signal binv1_stg_act_int :std_ulogic; +signal binv2_stg_act_int :std_ulogic; +signal binv3_stg_act_int :std_ulogic; +signal binv4_stg_act_int :std_ulogic; +signal binv5_stg_act_int :std_ulogic; +signal rel1_stg_act_int :std_ulogic; +signal rel2_stg_act_int :std_ulogic; +signal rel3_stg_act_int :std_ulogic; +signal binv1_ex1_stg_act :std_ulogic; +signal ex2_lockwatchSet_rel_coll :std_ulogic; +signal ex3_wclr_all_flush :std_ulogic; +signal spr_xucr0_cls_int :std_ulogic; +signal agen_xucr0_cls :std_ulogic; +signal agen_xucr0_cls_b :std_ulogic; +signal tag_scan_out :std_ulogic; +signal lru_scan_out :std_ulogic; +signal dir_scan_out :std_ulogic; +signal ex3_way_tag_par_a :std_ulogic_vector(0 to parBits-1); +signal ex3_way_tag_par_b :std_ulogic_vector(0 to parBits-1); +signal ex3_way_tag_par_c :std_ulogic_vector(0 to parBits-1); +signal ex3_way_tag_par_d :std_ulogic_vector(0 to parBits-1); +signal ex3_way_tag_par_e :std_ulogic_vector(0 to parBits-1); +signal ex3_way_tag_par_f :std_ulogic_vector(0 to parBits-1); +signal ex3_way_tag_par_g :std_ulogic_vector(0 to parBits-1); +signal ex3_way_tag_par_h :std_ulogic_vector(0 to parBits-1); +signal ex4_dir_lru :std_ulogic_vector(0 to 6); +signal ex3_load_val :std_ulogic; +signal ex3_l2_request :std_ulogic; +signal ex3_ldq_potential_flush :std_ulogic; +signal ex4_snd_ld_l2 :std_ulogic; +signal ldq_rel1_val_stg_d :std_ulogic; +signal ldq_rel1_val_stg_q :std_ulogic; +signal ldq_rel_mid_stg_d :std_ulogic; +signal ldq_rel_mid_stg_q :std_ulogic; +signal ldq_rel3_val_stg_d :std_ulogic; +signal ldq_rel3_val_stg_q :std_ulogic; +signal ldq_rel_data_stg_d :std_ulogic; +signal ldq_rel_data_stg_q :std_ulogic; +signal ldq_rel_set_stg_d :std_ulogic; +signal ldq_rel_set_stg_q :std_ulogic; +signal trace_bus_enable_q :std_ulogic; +signal dir_arr_dbg_data_d :std_ulogic_vector(0 to 60); +signal dir_arr_dbg_data_q :std_ulogic_vector(0 to 60); +signal ex3_cache_acc_int :std_ulogic; + +signal tiup :std_ulogic; +signal siv :std_ulogic_vector(0 to scan_right); +signal sov :std_ulogic_vector(0 to scan_right); +begin + + +tiup <= '1'; + +ex2_frc_align_d(59) <= not ex1_frc_align32; +ex2_frc_align_d(60) <= not (ex1_frc_align32 or ex1_frc_align16); +ex2_frc_align_d(61) <= not (ex1_frc_align32 or ex1_frc_align16 or ex1_frc_align8); +ex2_frc_align_d(62) <= not (ex1_frc_align32 or ex1_frc_align16 or ex1_frc_align8 or ex1_frc_align4); +ex2_frc_align_d(63) <= not (ex1_frc_align32 or ex1_frc_align16 or ex1_frc_align8 or ex1_frc_align4 or ex1_frc_align2); + +spr_xucr0_dcdis_d <= xu_lsu_spr_xucr0_dcdis; +ldq_rel_stg24_val_d <= ldq_rel1_val or ldq_rel3_val or ldq_rel_ci or rel_data_val or ldq_rel_mid_val; + +ldq_rel1_val_stg_d <= ldq_rel1_val; +ldq_rel_mid_stg_d <= ldq_rel_mid_val; +ldq_rel3_val_stg_d <= ldq_rel3_val; +ldq_rel_data_stg_d <= rel_data_val; +ldq_rel_set_stg_d <= ldq_rel_set_val; +rel1_val <= ldq_rel1_val and not spr_xucr0_dcdis_q; +rel_st_tag <= ldq_rel_tag; +rel_st_tag_early <= ldq_rel_tag_early; +rel24_addr_d <= ldq_rel_addr; +rel4_set_val <= ldq_rel_set_val; +rel_lock_en <= ldq_rel_lock_en; +rel_l1dump_cslc <= ldq_rel_l1dump_cslc and not spr_xucr0_dcdis_q; +rel3_l1dump_val <= ldq_rel3_l1dump_val and not spr_xucr0_dcdis_q; +rel_watch_en <= ldq_rel_watch_en; +rel_thrd_id <= ldq_rel_thrd_id; +rel1_classid <= ldq_rel_classid; +rel3_val <= ldq_rel3_val and not spr_xucr0_dcdis_q; +rel_mid_val <= ldq_rel_mid_val and not spr_xucr0_dcdis_q; +ex2_p_addr_lwr_int <= lwr_p_addr_q(52 to 58) & (lwr_p_addr_q(59 to 63) and ex2_frc_align_q); +binv1_ex1_stg_act <= binv1_stg_act_int or ex1_stg_act_int; + + + +agen_xucr0_cls_b <= not agen_xucr0_cls; +ex1_dir_acc_val_b <= not ex1_dir_acc_val; +ex1_l2_inv_val_b <= not ex1_l2_inv_val; + +Mode32b : if regmode = 5 generate begin + ex1_eff_addr <= std_ulogic_vector(unsigned(xu_lsu_ex1_add_src0) + unsigned(xu_lsu_ex1_add_src1)); + ex1_agen_addr <= ex1_eff_addr(64-(2**regmode) to 51); + lwr_p_addr_d <= ex1_eff_addr(52 to 63); + ex1_p_addr <= ex1_eff_addr(64-(dc_size-3) to 63-cl_size); + ex1_dir01_addr(64-(dc_size-3) to 63-cl_size-1) <= ex1_eff_addr(64-(dc_size-3) to 63-cl_size-1); + ex1_dir01_addr(63-cl_size) <= ex1_eff_addr(63-cl_size) or agen_xucr0_cls; + ex1_dir23_addr(64-(dc_size-3) to 63-cl_size-1) <= ex1_eff_addr(64-(dc_size-3) to 63-cl_size-1); + ex1_dir23_addr(63-cl_size) <= ex1_eff_addr(63-cl_size) or agen_xucr0_cls; + ex1_dir45_addr(64-(dc_size-3) to 63-cl_size-1) <= ex1_eff_addr(64-(dc_size-3) to 63-cl_size-1); + ex1_dir45_addr(63-cl_size) <= ex1_eff_addr(63-cl_size) or agen_xucr0_cls; + ex1_dir67_addr(64-(dc_size-3) to 63-cl_size-1) <= ex1_eff_addr(64-(dc_size-3) to 63-cl_size-1); + ex1_dir67_addr(63-cl_size) <= ex1_eff_addr(63-cl_size) or agen_xucr0_cls; +end generate Mode32b; + +Mode64b : if regmode = 6 generate begin + lsuagen : entity work.xuq_agen(xuq_agen) + port map( + x => xu_lsu_ex1_add_src0, + y => xu_lsu_ex1_add_src1, + mode64 => ex1_lsu_64bit_agen, + dir_ig_57_b => agen_xucr0_cls_b, + snoop_addr => snoop_addr(0 to 51), + snoop_sel => snoop_addr_sel, + binv_val => ex1_agen_binv_val, + sum_non_erat => ex1_eff_addr, + sum => ex1_agen_addr(0 to 51), + sum_arr_dir01 => ex1_dir01_addr, + sum_arr_dir23 => ex1_dir23_addr, + sum_arr_dir45 => ex1_dir45_addr, + sum_arr_dir67 => ex1_dir67_addr, + z => dir_arr_wr_addr_int, + way => dir_wr_way_int, + inv1_val_b => ex1_l2_inv_val_b, + ex1_cache_acc_b => ex1_dir_acc_val_b, + rel3_val => rel3_val, + ary_write_act_01 => dir_wr_enable(0), + ary_write_act_23 => dir_wr_enable(1), + ary_write_act_45 => dir_wr_enable(2), + ary_write_act_67 => dir_wr_enable(3), + ary_write_act => dir_wr_enable_int, + match_oth => recirc_rel_val, + vdd => vdd, + gnd => gnd + ); + + lwr_p_addr_d <= ex1_eff_addr(52 to 63); + ex1_p_addr <= ex1_eff_addr(64-(dc_size-3) to 63-cl_size); +end generate Mode64b; + +recirc_rel_val_d <= recirc_rel_val and rel3_val; + + +lsudc : entity work.xuq_lsu_dc(xuq_lsu_dc) +generic map(expand_type => expand_type, + l_endian_m => l_endian_m, + regmode => regmode, + dc_size => dc_size, + parBits => parBits, + real_data_add => real_data_add) +port map( + + xu_lsu_rf0_act => xu_lsu_rf0_act, + xu_lsu_rf1_cmd_act => xu_lsu_rf1_cmd_act, + xu_lsu_rf1_axu_op_val => xu_lsu_rf1_axu_op_val, + xu_lsu_rf1_axu_ldst_falign => xu_lsu_rf1_axu_ldst_falign, + xu_lsu_rf1_axu_ldst_fexcpt => xu_lsu_rf1_axu_ldst_fexcpt, + xu_lsu_rf1_cache_acc => xu_lsu_rf1_cache_acc, + xu_lsu_rf1_thrd_id => xu_lsu_rf1_thrd_id, + xu_lsu_rf1_optype1 => xu_lsu_rf1_optype1, + xu_lsu_rf1_optype2 => xu_lsu_rf1_optype2, + xu_lsu_rf1_optype4 => xu_lsu_rf1_optype4, + xu_lsu_rf1_optype8 => xu_lsu_rf1_optype8, + xu_lsu_rf1_optype16 => xu_lsu_rf1_optype16, + xu_lsu_rf1_optype32 => xu_lsu_rf1_optype32, + xu_lsu_rf1_target_gpr => xu_lsu_rf1_target_gpr, + xu_lsu_rf1_mtspr_trace => xu_lsu_rf1_mtspr_trace, + xu_lsu_rf1_load_instr => xu_lsu_rf1_load_instr, + xu_lsu_rf1_store_instr => xu_lsu_rf1_store_instr, + xu_lsu_rf1_dcbf_instr => xu_lsu_rf1_dcbf_instr, + xu_lsu_rf1_sync_instr => xu_lsu_rf1_sync_instr, + xu_lsu_rf1_l_fld => xu_lsu_rf1_l_fld, + xu_lsu_rf1_dcbi_instr => xu_lsu_rf1_dcbi_instr, + xu_lsu_rf1_dcbz_instr => xu_lsu_rf1_dcbz_instr, + xu_lsu_rf1_dcbt_instr => xu_lsu_rf1_dcbt_instr, + xu_lsu_rf1_dcbtst_instr => xu_lsu_rf1_dcbtst_instr, + xu_lsu_rf1_th_fld => xu_lsu_rf1_th_fld, + xu_lsu_rf1_dcbtls_instr => xu_lsu_rf1_dcbtls_instr, + xu_lsu_rf1_dcbtstls_instr => xu_lsu_rf1_dcbtstls_instr, + xu_lsu_rf1_dcblc_instr => xu_lsu_rf1_dcblc_instr, + xu_lsu_rf1_dcbst_instr => xu_lsu_rf1_dcbst_instr, + xu_lsu_rf1_icbi_instr => xu_lsu_rf1_icbi_instr, + xu_lsu_rf1_icblc_instr => xu_lsu_rf1_icblc_instr, + xu_lsu_rf1_icbt_instr => xu_lsu_rf1_icbt_instr, + xu_lsu_rf1_icbtls_instr => xu_lsu_rf1_icbtls_instr, + xu_lsu_rf1_icswx_instr => xu_lsu_rf1_icswx_instr, + xu_lsu_rf1_icswx_dot_instr => xu_lsu_rf1_icswx_dot_instr, + xu_lsu_rf1_icswx_epid => xu_lsu_rf1_icswx_epid, + xu_lsu_rf1_tlbsync_instr => xu_lsu_rf1_tlbsync_instr, + xu_lsu_rf1_ldawx_instr => xu_lsu_rf1_ldawx_instr, + xu_lsu_rf1_wclr_instr => xu_lsu_rf1_wclr_instr, + xu_lsu_rf1_wchk_instr => xu_lsu_rf1_wchk_instr, + xu_lsu_rf1_lock_instr => xu_lsu_rf1_lock_instr, + xu_lsu_rf1_mutex_hint => xu_lsu_rf1_mutex_hint, + xu_lsu_rf1_mbar_instr => xu_lsu_rf1_mbar_instr, + xu_lsu_rf1_is_msgsnd => xu_lsu_rf1_is_msgsnd, + xu_lsu_rf1_dci_instr => xu_lsu_rf1_dci_instr, + xu_lsu_rf1_ici_instr => xu_lsu_rf1_ici_instr, + xu_lsu_rf1_algebraic => xu_lsu_rf1_algebraic, + xu_lsu_rf1_byte_rev => xu_lsu_rf1_byte_rev, + xu_lsu_rf1_src_gpr => xu_lsu_rf1_src_gpr, + xu_lsu_rf1_src_axu => xu_lsu_rf1_src_axu, + xu_lsu_rf1_src_dp => xu_lsu_rf1_src_dp, + xu_lsu_rf1_targ_gpr => xu_lsu_rf1_targ_gpr, + xu_lsu_rf1_targ_axu => xu_lsu_rf1_targ_axu, + xu_lsu_rf1_targ_dp => xu_lsu_rf1_targ_dp, + xu_lsu_ex4_val => xu_lsu_ex4_val, + + xu_lsu_rf1_src0_vld => xu_lsu_rf1_src0_vld, + xu_lsu_rf1_src0_reg => xu_lsu_rf1_src0_reg, + xu_lsu_rf1_src1_vld => xu_lsu_rf1_src1_vld, + xu_lsu_rf1_src1_reg => xu_lsu_rf1_src1_reg, + xu_lsu_rf1_targ_vld => xu_lsu_rf1_targ_vld, + xu_lsu_rf1_targ_reg => xu_lsu_rf1_targ_reg, + + ex2_p_addr_lwr => ex2_p_addr_lwr_int, + ex3_wimge_w_bit => ex3_wimge_w_bit, + ex3_wimge_i_bit => ex3_wimge_i_bit, + ex3_wimge_e_bit => ex3_wimge_e_bit, + ex2_lm_dep_hit => ex2_lm_dep_hit, + + ex3_p_addr => ex3_p_addr, + ex3_ld_queue_full => ex3_ld_queue_full, + ex3_stq_flush => ex3_stq_flush, + ex3_ig_flush => ex3_ig_flush, + ex3_hit => ex3_l1hit, + ex4_miss => ex4_l1miss, + ex4_snd_ld_l2 => ex4_snd_ld_l2, + derat_xu_ex3_noop_touch => derat_xu_ex3_noop_touch, + ex3_cClass_collision => ex3_cClass_collision, + ex2_lockwatchSet_rel_coll => ex2_lockwatchSet_rel_coll, + ex3_wclr_all_flush => ex3_wclr_all_flush, + + rel_dcarr_val_upd => rel_dcarr_val_upd, + + xu_lsu_mtspr_trace_en => xu_lsu_mtspr_trace_en, + spr_xucr0_clkg_ctl_b1 => spr_xucr0_clkg_ctl_b1, + xu_lsu_spr_xucr0_aflsta => xu_lsu_spr_xucr0_aflsta, + xu_lsu_spr_xucr0_flsta => xu_lsu_spr_xucr0_flsta, + xu_lsu_spr_xucr0_l2siw => xu_lsu_spr_xucr0_l2siw, + xu_lsu_spr_xucr0_dcdis => xu_lsu_spr_xucr0_dcdis, + xu_lsu_spr_xucr0_wlk => xu_lsu_spr_xucr0_wlk, + xu_lsu_spr_ccr2_dfrat => xu_lsu_spr_ccr2_dfrat, + xu_lsu_spr_xucr0_flh2l2 => xu_lsu_spr_xucr0_flh2l2, + xu_lsu_spr_xucr0_cls => xu_lsu_spr_xucr0_cls, + xu_lsu_spr_msr_cm => xu_lsu_spr_msr_cm, + + xu_lsu_msr_gs => xu_lsu_msr_gs, + xu_lsu_msr_pr => xu_lsu_msr_pr, + + an_ac_flh2l2_gate => an_ac_flh2l2_gate, + + xu_lsu_rf1_flush => xu_lsu_rf1_flush, + xu_lsu_ex1_flush => xu_lsu_ex1_flush, + xu_lsu_ex2_flush => xu_lsu_ex2_flush, + xu_lsu_ex3_flush => xu_lsu_ex3_flush, + xu_lsu_ex4_flush => xu_lsu_ex4_flush, + xu_lsu_ex5_flush => xu_lsu_ex5_flush, + + xu_lsu_slowspr_val => xu_lsu_slowspr_val, + xu_lsu_slowspr_rw => xu_lsu_slowspr_rw, + xu_lsu_slowspr_etid => xu_lsu_slowspr_etid, + xu_lsu_slowspr_addr => xu_lsu_slowspr_addr, + xu_lsu_slowspr_data => xu_lsu_slowspr_data, + xu_lsu_slowspr_done => xu_lsu_slowspr_done, + slowspr_val_out => slowspr_val_out, + slowspr_rw_out => slowspr_rw_out, + slowspr_etid_out => slowspr_etid_out, + slowspr_addr_out => slowspr_addr_out, + slowspr_data_out => slowspr_data_out, + slowspr_done_out => slowspr_done_out, + + ldq_rel_data_val_early => ldq_rel_data_val_early, + ldq_rel_stg24_val => ldq_rel_stg24_val_q, + ldq_rel_axu_val => ldq_rel_axu_val, + ldq_rel_thrd_id => ldq_rel_thrd_id, + ldq_rel_ta_gpr => ldq_rel_ta_gpr, + ldq_rel_upd_gpr => ldq_rel_upd_gpr, + ldq_rel_ci => ldq_rel_ci, + is2_l2_inv_val => is2_l2_inv_val, + + ex3_wayA_tag => ex3_wayA_tag, + ex3_wayB_tag => ex3_wayB_tag, + ex3_wayC_tag => ex3_wayC_tag, + ex3_wayD_tag => ex3_wayD_tag, + ex3_wayE_tag => ex3_wayE_tag, + ex3_wayF_tag => ex3_wayF_tag, + ex3_wayG_tag => ex3_wayG_tag, + ex3_wayH_tag => ex3_wayH_tag, + ex3_way_tag_par_a => ex3_way_tag_par_a, + ex3_way_tag_par_b => ex3_way_tag_par_b, + ex3_way_tag_par_c => ex3_way_tag_par_c, + ex3_way_tag_par_d => ex3_way_tag_par_d, + ex3_way_tag_par_e => ex3_way_tag_par_e, + ex3_way_tag_par_f => ex3_way_tag_par_f, + ex3_way_tag_par_g => ex3_way_tag_par_g, + ex3_way_tag_par_h => ex3_way_tag_par_h, + ex4_way_a_dir => ex4_way_a_dir, + ex4_way_b_dir => ex4_way_b_dir, + ex4_way_c_dir => ex4_way_c_dir, + ex4_way_d_dir => ex4_way_d_dir, + ex4_way_e_dir => ex4_way_e_dir, + ex4_way_f_dir => ex4_way_f_dir, + ex4_way_g_dir => ex4_way_g_dir, + ex4_way_h_dir => ex4_way_h_dir, + ex4_dir_lru => ex4_dir_lru, + + ex1_src0_vld => ex1_src0_vld, + ex1_src0_reg => ex1_src0_reg, + ex1_src1_vld => ex1_src1_vld, + ex1_src1_reg => ex1_src1_reg, + ex1_targ_vld => ex1_targ_vld, + ex1_targ_reg => ex1_targ_reg, + ex1_check_watch => ex1_check_watch, + + ex1_dir_acc_val => ex1_dir_acc_val, + ex3_cache_acc => ex3_cache_acc_int, + ex1_lsu_64bit_agen => ex1_lsu_64bit_agen, + ex1_frc_align2 => ex1_frc_align2, + ex1_frc_align4 => ex1_frc_align4, + ex1_frc_align8 => ex1_frc_align8, + ex1_frc_align16 => ex1_frc_align16, + ex1_frc_align32 => ex1_frc_align32, + ex1_optype1 => ex1_optype1, + ex1_optype2 => ex1_optype2, + ex1_optype4 => ex1_optype4, + ex1_optype8 => ex1_optype8, + ex1_optype16 => ex1_optype16, + ex1_optype32 => ex1_optype32, + ex1_saxu_instr => ex1_saxu_instr, + ex1_sdp_instr => ex1_sdp_instr, + ex1_stgpr_instr => ex1_stgpr_instr, + ex1_store_instr => ex1_store_instr, + ex1_axu_op_val => ex1_axu_op_val, + ex2_no_lru_upd => ex2_no_lru_upd, + ex2_is_inval_op => ex2_is_inval_op, + ex2_lock_set => ex2_lock_set, + ex2_lock_clr => ex2_lock_clr, + ex2_ddir_acc_instr => ex2_ddir_acc_instr, + + ex3_p_addr_lwr => ex3_p_addr_lwr, + ex3_req_thrd_id => ex3_req_thrd_id, + ex3_target_gpr => ex3_target_gpr, + ex3_dcbt_instr => ex3_dcbt_instr, + ex3_dcbtst_instr => ex3_dcbtst_instr, + ex3_th_fld_l2 => ex3_th_fld_l2, + ex3_dcbst_instr => ex3_dcbst_instr, + ex3_dcbf_instr => ex3_dcbf_instr, + ex3_sync_instr => ex3_sync_instr, + ex3_mtspr_trace => ex3_mtspr_trace, + ex3_byte_en => ex3_byte_en, + ex2_l_fld => ex2_l_fld, + ex3_l_fld => ex3_l_fld, + ex3_dcbi_instr => ex3_dcbi_instr, + ex3_dcbz_instr => ex3_dcbz_instr, + ex3_icbi_instr => ex3_icbi_instr, + ex3_icswx_instr => ex3_icswx_instr, + ex3_icswx_dot => ex3_icswx_dot, + ex3_icswx_epid => ex3_icswx_epid, + ex3_mbar_instr => ex3_mbar_instr, + ex3_msgsnd_instr => ex3_msgsnd_instr, + ex3_dci_instr => ex3_dci_instr, + ex3_ici_instr => ex3_ici_instr, + ex3_load_instr => ex3_load_instr, + ex2_store_instr => store_instr_ex2, + ex3_store_instr => ex3_store_instr, + ex3_axu_op_val => ex3_axu_op_val, + ex3_algebraic => ex3_algebraic, + ex3_dcbtls_instr => dcbtls_instr_ex3, + ex3_dcbtstls_instr => dcbtstls_instr_ex3, + ex3_dcblc_instr => ex3_dcblc_instr, + ex3_icblc_instr => ex3_icblc_instr, + ex3_icbt_instr => ex3_icbt_instr, + ex3_icbtls_instr => ex3_icbtls_instr, + ex3_tlbsync_instr => ex3_tlbsync_instr, + ex3_local_dcbf => ex3_local_dcbf, + ex4_drop_rel => ex4_drop_rel, + ex3_load_l1hit => ex3_load_l1hit, + ex3_rotate_sel => ex3_rotate_sel, + ex1_thrd_id => ex1_thrd_id, + ex2_ldawx_instr => ex2_ldawx_instr, + ex2_wclr_instr => ex2_wclr_instr, + ex2_wchk_val => ex2_wchk_val, + ex3_watch_en => ex3_watch_en, + ex3_data_swap => ex3_data_swap, + ex3_load_val => ex3_load_val, + ex3_blkable_touch => ex3_blkable_touch, + ex3_l2_request => ex3_l2_request, + ex3_ldq_potential_flush => ex3_ldq_potential_flush, + ex7_targ_match => ex7_targ_match, + ex8_targ_match => ex8_targ_match, + ex4_ld_entry => ex4_ld_entry, + + ex3_lock_en => ex3_lock_en, + ex3_cache_en => ex3_cache_en, + ex3_cache_inh => ex3_cache_inh, + ex3_l_s_q_val => ex3_l_s_q_val, + ex3_drop_ld_req => ex3_drop_ld_req, + ex3_drop_touch => ex3_drop_touch, + ex3_stx_instr => ex3_stx_instr, + ex3_larx_instr => ex3_larx_instr, + ex3_mutex_hint => ex3_mutex_hint, + ex3_opsize => ex3_opsize, + ex4_store_hit => ex4_store_hit, + + spr_xucr2_rmt => spr_xucr2_rmt, + spr_xucr0_wlck => spr_xucr0_wlck, + ex4_load_op_hit => ex4_load_op_hit, + ex5_load_op_hit => ex5_load_op_hit, + ex4_axu_op_val => ex4_axu_op_val, + spr_dvc1_act => spr_dvc1_act, + spr_dvc2_act => spr_dvc2_act, + spr_dvc1_dbg => spr_dvc1_dbg, + spr_dvc2_dbg => spr_dvc2_dbg, + + lsu_xu_spr_xucr0_cul => lsu_xu_spr_xucr0_cul, + spr_xucr0_cls => spr_xucr0_cls_int, + agen_xucr0_cls => agen_xucr0_cls, + + dir_arr_rd_is2_val => dir_arr_rd_is2_val, + dir_arr_rd_congr_cl => dir_arr_rd_congr_cl, + + lsu_xu_ex3_align => lsu_xu_ex3_align, + lsu_xu_ex3_dsi => lsu_xu_ex3_dsi, + lsu_xu_ex3_inval_align_2ucode => lsu_xu_ex3_inval_align_2ucode, + + ex2_stg_flush => stg_ex2_flush, + ex3_stg_flush => stg_ex3_flush, + ex4_stg_flush => stg_ex4_flush, + ex5_stg_flush => stg_ex5_flush, + lsu_xu_ex3_n_flush_req => lsu_xu_ex3_n_flush_req, + lsu_xu_ex3_dep_flush => lsu_xu_ex3_dep_flush, + + rf1_l2_inv_val => rf1_l2_inv_val, + ex1_agen_binv_val => ex1_agen_binv_val, + ex1_l2_inv_val => ex1_l2_inv_val, + + rel_upd_dcarr_val => rel_upd_dcarr_val, + + lsu_xu_ex4_cr_upd => lsu_xu_ex4_cr_upd, + lsu_xu_ex5_wren => lsu_xu_ex5_wren, + lsu_xu_rel_wren => lsu_xu_rel_wren, + lsu_xu_rel_ta_gpr => lsu_xu_rel_ta_gpr, + lsu_xu_perf_events => lsu_xu_perf_events(0 to 20), + lsu_xu_need_hole => lsu_xu_need_hole, + + xu_fu_ex5_reload_val => xu_fu_ex5_reload_val, + xu_fu_ex5_load_val => xu_fu_ex5_load_val, + xu_fu_ex5_load_tag => xu_fu_ex5_load_tag, + + xu_iu_ex6_icbi_val => xu_iu_ex6_icbi_val, + xu_iu_ex6_icbi_addr => xu_iu_ex6_icbi_addr, + + xu_derat_epsc_wr => xu_derat_epsc_wr, + xu_derat_eplc_wr => xu_derat_eplc_wr, + xu_derat_eplc0_epr => xu_derat_eplc0_epr, + xu_derat_eplc0_eas => xu_derat_eplc0_eas, + xu_derat_eplc0_egs => xu_derat_eplc0_egs, + xu_derat_eplc0_elpid => xu_derat_eplc0_elpid, + xu_derat_eplc0_epid => xu_derat_eplc0_epid, + xu_derat_eplc1_epr => xu_derat_eplc1_epr, + xu_derat_eplc1_eas => xu_derat_eplc1_eas, + xu_derat_eplc1_egs => xu_derat_eplc1_egs, + xu_derat_eplc1_elpid => xu_derat_eplc1_elpid, + xu_derat_eplc1_epid => xu_derat_eplc1_epid, + xu_derat_eplc2_epr => xu_derat_eplc2_epr, + xu_derat_eplc2_eas => xu_derat_eplc2_eas, + xu_derat_eplc2_egs => xu_derat_eplc2_egs, + xu_derat_eplc2_elpid => xu_derat_eplc2_elpid, + xu_derat_eplc2_epid => xu_derat_eplc2_epid, + xu_derat_eplc3_epr => xu_derat_eplc3_epr, + xu_derat_eplc3_eas => xu_derat_eplc3_eas, + xu_derat_eplc3_egs => xu_derat_eplc3_egs, + xu_derat_eplc3_elpid => xu_derat_eplc3_elpid, + xu_derat_eplc3_epid => xu_derat_eplc3_epid, + xu_derat_epsc0_epr => xu_derat_epsc0_epr, + xu_derat_epsc0_eas => xu_derat_epsc0_eas, + xu_derat_epsc0_egs => xu_derat_epsc0_egs, + xu_derat_epsc0_elpid => xu_derat_epsc0_elpid, + xu_derat_epsc0_epid => xu_derat_epsc0_epid, + xu_derat_epsc1_epr => xu_derat_epsc1_epr, + xu_derat_epsc1_eas => xu_derat_epsc1_eas, + xu_derat_epsc1_egs => xu_derat_epsc1_egs, + xu_derat_epsc1_elpid => xu_derat_epsc1_elpid, + xu_derat_epsc1_epid => xu_derat_epsc1_epid, + xu_derat_epsc2_epr => xu_derat_epsc2_epr, + xu_derat_epsc2_eas => xu_derat_epsc2_eas, + xu_derat_epsc2_egs => xu_derat_epsc2_egs, + xu_derat_epsc2_elpid => xu_derat_epsc2_elpid, + xu_derat_epsc2_epid => xu_derat_epsc2_epid, + xu_derat_epsc3_epr => xu_derat_epsc3_epr, + xu_derat_epsc3_eas => xu_derat_epsc3_eas, + xu_derat_epsc3_egs => xu_derat_epsc3_egs, + xu_derat_epsc3_elpid => xu_derat_epsc3_elpid, + xu_derat_epsc3_epid => xu_derat_epsc3_epid, + + dc_fgen_dbg_data => dc_fgen_dbg_data, + dc_cntrl_dbg_data => dc_cntrl_dbg_data, + + ex1_stg_act => ex1_stg_act_int, + ex2_stg_act => ex2_stg_act_int, + ex3_stg_act => ex3_stg_act_int, + ex4_stg_act => ex4_stg_act_int, + ex5_stg_act => ex5_stg_act_int, + binv1_stg_act => binv1_stg_act_int, + binv2_stg_act => binv2_stg_act_int, + binv3_stg_act => binv3_stg_act_int, + binv4_stg_act => binv4_stg_act_int, + binv5_stg_act => binv5_stg_act_int, + rel1_stg_act => rel1_stg_act_int, + rel2_stg_act => rel2_stg_act_int, + rel3_stg_act => rel3_stg_act_int, + + vdd => vdd, + gnd => gnd, + nclk => nclk, + sg_0 => sg_0, + func_sl_thold_0_b => func_sl_thold_0_b, + func_sl_force => func_sl_force, + func_slp_sl_thold_0_b => func_slp_sl_thold_0_b, + func_slp_sl_force => func_slp_sl_force, + func_nsl_thold_0_b => func_nsl_thold_0_b, + func_nsl_force => func_nsl_force, + func_slp_nsl_thold_0_b => func_slp_nsl_thold_0_b, + func_slp_nsl_force => func_slp_nsl_force, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc, + mpw1_dc_b => mpw1_dc_b, + mpw2_dc_b => mpw2_dc_b, + scan_in => scan_in(0), + scan_out => scan_out(0) +); +dir16k : if (2**dc_size) = 16384 generate begin + +l1dcdv: entity work.xuq_lsu_dir_val16(xuq_lsu_dir_val16) +GENERIC MAP(expand_type => expand_type, + dc_size => dc_size, + cl_size => cl_size) +PORT MAP ( + + ex1_stg_act => ex1_stg_act_int, + ex2_stg_act => ex2_stg_act_int, + ex3_stg_act => ex3_stg_act_int, + ex4_stg_act => ex4_stg_act_int, + ex5_stg_act => ex5_stg_act_int, + binv1_stg_act => binv1_stg_act_int, + binv2_stg_act => binv2_stg_act_int, + binv3_stg_act => binv3_stg_act_int, + binv4_stg_act => binv4_stg_act_int, + binv5_stg_act => binv5_stg_act_int, + rel1_stg_act => rel1_stg_act_int, + rel2_stg_act => rel2_stg_act_int, + + ldq_rel1_early_v => ldq_rel1_early_v, + rel1_val => rel1_val, + rel_addr_early => ldq_rel_addr_early(64-(dc_size-3) to 63-cl_size), + rel_lock_en => rel_lock_en, + rel_l1dump_cslc => rel_l1dump_cslc, + rel3_l1dump_val => rel3_l1dump_val, + rel_watch_en => rel_watch_en, + rel_thrd_id => rel_thrd_id, + rel_way_clr_a => rel_way_clr_a, + rel_way_clr_b => rel_way_clr_b, + rel_way_clr_c => rel_way_clr_c, + rel_way_clr_d => rel_way_clr_d, + rel_way_clr_e => rel_way_clr_e, + rel_way_clr_f => rel_way_clr_f, + rel_way_clr_g => rel_way_clr_g, + rel_way_clr_h => rel_way_clr_h, + + ldq_rel3_early_v => ldq_rel3_early_v, + rel3_val => rel3_val, + rel_back_inval => ldq_rel_back_invalidated, + rel4_set_val => rel4_set_val, + rel4_recirc_val => recirc_rel_val_q, + rel4_ecc_err => ldq_rel_ecc_err, + rel_way_wen_a => rel_wayA_wen, + rel_way_wen_b => rel_wayB_wen, + rel_way_wen_c => rel_wayC_wen, + rel_way_wen_d => rel_wayD_wen, + rel_way_wen_e => rel_wayE_wen, + rel_way_wen_f => rel_wayF_wen, + rel_way_wen_g => rel_wayG_wen, + rel_way_wen_h => rel_wayH_wen, + rel_up_way_addr_b => rel_up_way_addr_b, + rel_dcarr_addr_en => rel_dcarr_addr_en, + + xu_lsu_dci => xu_lsu_dci, + xu_lsu_spr_xucr0_clfc => xu_lsu_spr_xucr0_clfc, + spr_xucr0_dcdis => spr_xucr0_dcdis_q, + spr_xucr0_cls => spr_xucr0_cls_int, + + ex1_thrd_id => ex1_thrd_id, + ex1_p_addr => ex1_p_addr, + ex2_is_inval_op => ex2_is_inval_op, + ex2_lock_set => ex2_lock_set, + ex2_lock_clr => ex2_lock_clr, + ex3_cache_en => ex3_cache_en, + ex3_cache_acc => ex3_cache_acc_int, + ex3_tag_way_perr => ex3_tag_way_perr, + ex5_load_op_hit => ex5_load_op_hit, + ex6_ld_par_err => ex6_ld_par_err, + ex2_ldawx_instr => ex2_ldawx_instr, + ex2_wclr_instr => ex2_wclr_instr, + ex2_wchk_val => ex2_wchk_val, + ex2_l_fld => ex2_l_fld, + ex2_store_instr => store_instr_ex2, + ex3_load_val => ex3_load_val, + ex3_wimge_i_bit => ex3_wimge_i_bit, + ex3_l2_request => ex3_l2_request, + ex3_ldq_potential_flush => ex3_ldq_potential_flush, + + inv1_val => ex1_l2_inv_val, + + ex3_way_cmp_a => ex3_way_cmp_a, + ex3_way_cmp_b => ex3_way_cmp_b, + ex3_way_cmp_c => ex3_way_cmp_c, + ex3_way_cmp_d => ex3_way_cmp_d, + ex3_way_cmp_e => ex3_way_cmp_e, + ex3_way_cmp_f => ex3_way_cmp_f, + ex3_way_cmp_g => ex3_way_cmp_g, + ex3_way_cmp_h => ex3_way_cmp_h, + + ex2_stg_flush => stg_ex2_flush, + ex3_stg_flush => stg_ex3_flush, + ex4_stg_flush => stg_ex4_flush, + ex5_stg_flush => stg_ex5_flush, + + pc_xu_inj_dcachedir_multihit => pc_xu_inj_dcachedir_multihit, + + ex4_way_a_dir => ex4_way_a_dir, + ex4_way_b_dir => ex4_way_b_dir, + ex4_way_c_dir => ex4_way_c_dir, + ex4_way_d_dir => ex4_way_d_dir, + ex4_way_e_dir => ex4_way_e_dir, + ex4_way_f_dir => ex4_way_f_dir, + ex4_way_g_dir => ex4_way_g_dir, + ex4_way_h_dir => ex4_way_h_dir, + + ex4_way_a_hit => ex4_way_a_hit, + ex4_way_b_hit => ex4_way_b_hit, + ex4_way_c_hit => ex4_way_c_hit, + ex4_way_d_hit => ex4_way_d_hit, + ex4_way_e_hit => ex4_way_e_hit, + ex4_way_f_hit => ex4_way_f_hit, + ex4_way_g_hit => ex4_way_g_hit, + ex4_way_h_hit => ex4_way_h_hit, + + ex2_lockwatchSet_rel_coll => ex2_lockwatchSet_rel_coll, + ex3_wclr_all_flush => ex3_wclr_all_flush, + + ex3_cClass_upd_way_a => ex3_cClass_upd_way_a, + ex3_cClass_upd_way_b => ex3_cClass_upd_way_b, + ex3_cClass_upd_way_c => ex3_cClass_upd_way_c, + ex3_cClass_upd_way_d => ex3_cClass_upd_way_d, + ex3_cClass_upd_way_e => ex3_cClass_upd_way_e, + ex3_cClass_upd_way_f => ex3_cClass_upd_way_f, + ex3_cClass_upd_way_g => ex3_cClass_upd_way_g, + ex3_cClass_upd_way_h => ex3_cClass_upd_way_h, + + ex3_hit => ex3_l1hit, + ex3_dir_perr_det => ex3_dir_perr_det, + ex4_dir_multihit_det => ex4_dir_multihit_det, + ex4_n_lsu_ddmh_flush => ex4_n_lsu_ddmh_flush, + ex4_ldq_full_flush => ex4_ldq_full_flush, + ex4_miss => ex4_l1miss, + ex4_snd_ld_l2 => ex4_snd_ld_l2, + dcpar_err_flush => dcpar_err_flush, + pe_recov_begin => pe_recov_begin, + + lsu_xu_ex5_cr_rslt => lsu_xu_ex5_cr_rslt, + + rel_way_val_a => rel_way_val_a, + rel_way_val_b => rel_way_val_b, + rel_way_val_c => rel_way_val_c, + rel_way_val_d => rel_way_val_d, + rel_way_val_e => rel_way_val_e, + rel_way_val_f => rel_way_val_f, + rel_way_val_g => rel_way_val_g, + rel_way_val_h => rel_way_val_h, + + rel_way_lock_a => rel_way_lock_a, + rel_way_lock_b => rel_way_lock_b, + rel_way_lock_c => rel_way_lock_c, + rel_way_lock_d => rel_way_lock_d, + rel_way_lock_e => rel_way_lock_e, + rel_way_lock_f => rel_way_lock_f, + rel_way_lock_g => rel_way_lock_g, + rel_way_lock_h => rel_way_lock_h, + + dcarr_up_way_addr => dcarr_up_way_addr, + + lsu_xu_perf_events => lsu_xu_perf_events(21 to 37), + + lsu_xu_spr_xucr0_cslc_xuop => lsu_xu_spr_xucr0_cslc_xuop, + lsu_xu_spr_xucr0_cslc_binv => lsu_xu_spr_xucr0_cslc_binv, + + dc_val_dbg_data => dc_val_dbg_data, + + vdd => vdd, + gnd => gnd, + nclk => nclk, + sg_0 => sg_0, + func_sl_thold_0_b => func_sl_thold_0_b, + func_sl_force => func_sl_force, + func_slp_sl_thold_0_b => func_slp_sl_thold_0_b, + func_slp_sl_force => func_slp_sl_force, + func_nsl_thold_0_b => func_nsl_thold_0_b, + func_nsl_force => func_nsl_force, + func_slp_nsl_thold_0_b => func_slp_nsl_thold_0_b, + func_slp_nsl_force => func_slp_nsl_force, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc, + mpw1_dc_b => mpw1_dc_b, + mpw2_dc_b => mpw2_dc_b, + scan_in => scan_in(1 to 3), + scan_out(0 to 1) => scan_out(1 to 2), + scan_out(2) => dir_scan_out +); + +ex4_dir_perr_det_d <= ex3_dir_perr_det; + +l1dcdl : entity work.xuq_lsu_dir_lru16(xuq_lsu_dir_lru16) +GENERIC MAP(expand_type => expand_type, + dc_size => dc_size, + lmq_entries => lmq_entries, + cl_size => cl_size) +PORT MAP( + + ex1_stg_act => ex1_stg_act_int, + ex2_stg_act => ex2_stg_act_int, + ex3_stg_act => ex3_stg_act_int, + ex4_stg_act => ex4_stg_act_int, + ex5_stg_act => ex5_stg_act_int, + rel1_stg_act => rel1_stg_act_int, + rel2_stg_act => rel2_stg_act_int, + rel3_stg_act => rel3_stg_act_int, + + rel1_val => rel1_val, + rel1_classid => rel1_classid, + rel_mid_val => rel_mid_val, + rel_retry_val => ldq_rel_retry_val, + rel3_val => rel3_val, + rel_st_tag => rel_st_tag, + rel_st_tag_early => rel_st_tag_early, + rel_addr_early => ldq_rel_addr_early(64-(dc_size-3) to 63-cl_size), + rel_lock_en => rel_lock_en, + rel4_recirc_val => recirc_rel_val_q, + rel4_ecc_err => ldq_rel_ecc_err, + + rel_way_val_a => rel_way_val_a, + rel_way_val_b => rel_way_val_b, + rel_way_val_c => rel_way_val_c, + rel_way_val_d => rel_way_val_d, + rel_way_val_e => rel_way_val_e, + rel_way_val_f => rel_way_val_f, + rel_way_val_g => rel_way_val_g, + rel_way_val_h => rel_way_val_h, + + rel_way_lock_a => rel_way_lock_a, + rel_way_lock_b => rel_way_lock_b, + rel_way_lock_c => rel_way_lock_c, + rel_way_lock_d => rel_way_lock_d, + rel_way_lock_e => rel_way_lock_e, + rel_way_lock_f => rel_way_lock_f, + rel_way_lock_g => rel_way_lock_g, + rel_way_lock_h => rel_way_lock_h, + + ex1_p_addr => ex1_p_addr, + ex2_no_lru_upd => ex2_no_lru_upd, + ex3_cache_en => ex3_cache_en, + + ex4_way_a_hit => ex4_way_a_hit, + ex4_way_b_hit => ex4_way_b_hit, + ex4_way_c_hit => ex4_way_c_hit, + ex4_way_d_hit => ex4_way_d_hit, + ex4_way_e_hit => ex4_way_e_hit, + ex4_way_f_hit => ex4_way_f_hit, + ex4_way_g_hit => ex4_way_g_hit, + ex4_way_h_hit => ex4_way_h_hit, + ex3_hit => ex3_l1hit, + + ex3_stg_flush => stg_ex3_flush, + ex4_stg_flush => stg_ex4_flush, + ex5_stg_flush => stg_ex5_flush, + + spr_xucr2_rmt => spr_xucr2_rmt, + spr_xucr0_wlck => spr_xucr0_wlck, + spr_xucr0_dcdis => spr_xucr0_dcdis_q, + spr_xucr0_cls => spr_xucr0_cls_int, + + rel_way_upd_a => rel_way_upd_a, + rel_way_upd_b => rel_way_upd_b, + rel_way_upd_c => rel_way_upd_c, + rel_way_upd_d => rel_way_upd_d, + rel_way_upd_e => rel_way_upd_e, + rel_way_upd_f => rel_way_upd_f, + rel_way_upd_g => rel_way_upd_g, + rel_way_upd_h => rel_way_upd_h, + + rel_way_wen_a => rel_wayA_wen, + rel_way_wen_b => rel_wayB_wen, + rel_way_wen_c => rel_wayC_wen, + rel_way_wen_d => rel_wayD_wen, + rel_way_wen_e => rel_wayE_wen, + rel_way_wen_f => rel_wayF_wen, + rel_way_wen_g => rel_wayG_wen, + rel_way_wen_h => rel_wayH_wen, + + rel_way_clr_a => rel_way_clr_a, + rel_way_clr_b => rel_way_clr_b, + rel_way_clr_c => rel_way_clr_c, + rel_way_clr_d => rel_way_clr_d, + rel_way_clr_e => rel_way_clr_e, + rel_way_clr_f => rel_way_clr_f, + rel_way_clr_g => rel_way_clr_g, + rel_way_clr_h => rel_way_clr_h, + rel_dcarr_val_upd => rel_dcarr_val_upd, + rel_up_way_addr_b => rel_up_way_addr_b, + rel_dcarr_addr_en => rel_dcarr_addr_en, + + lsu_xu_spr_xucr0_clo => lsu_xu_spr_xucr0_clo, + ex4_dir_lru => ex4_dir_lru, + dc_lru_dbg_data => dc_lru_dbg_data, + + vdd => vdd, + gnd => gnd, + nclk => nclk, + sg_0 => sg_0, + func_sl_thold_0_b => func_sl_thold_0_b, + func_sl_force => func_sl_force, + func_nsl_thold_0_b => func_nsl_thold_0_b, + func_nsl_force => func_nsl_force, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc, + mpw1_dc_b => mpw1_dc_b, + mpw2_dc_b => mpw2_dc_b, + scan_in => dir_scan_out, + scan_out => lru_scan_out + ); +end generate dir16k; + +dir32k : if (2**dc_size) = 32768 generate begin + +l1dcdv: entity work.xuq_lsu_dir_val32(xuq_lsu_dir_val32) +GENERIC MAP(expand_type => expand_type, + dc_size => dc_size, + cl_size => cl_size) +PORT MAP ( + + ex1_stg_act => ex1_stg_act_int, + ex2_stg_act => ex2_stg_act_int, + ex3_stg_act => ex3_stg_act_int, + ex4_stg_act => ex4_stg_act_int, + ex5_stg_act => ex5_stg_act_int, + binv1_stg_act => binv1_stg_act_int, + binv2_stg_act => binv2_stg_act_int, + binv3_stg_act => binv3_stg_act_int, + binv4_stg_act => binv4_stg_act_int, + binv5_stg_act => binv5_stg_act_int, + rel1_stg_act => rel1_stg_act_int, + rel2_stg_act => rel2_stg_act_int, + + ldq_rel1_early_v => ldq_rel1_early_v, + rel1_val => rel1_val, + rel_addr_early => ldq_rel_addr_early(64-(dc_size-3) to 63-cl_size), + rel_lock_en => rel_lock_en, + rel_l1dump_cslc => rel_l1dump_cslc, + rel3_l1dump_val => rel3_l1dump_val, + rel_watch_en => rel_watch_en, + rel_thrd_id => rel_thrd_id, + rel_way_clr_a => rel_way_clr_a, + rel_way_clr_b => rel_way_clr_b, + rel_way_clr_c => rel_way_clr_c, + rel_way_clr_d => rel_way_clr_d, + rel_way_clr_e => rel_way_clr_e, + rel_way_clr_f => rel_way_clr_f, + rel_way_clr_g => rel_way_clr_g, + rel_way_clr_h => rel_way_clr_h, + + ldq_rel3_early_v => ldq_rel3_early_v, + rel3_val => rel3_val, + rel_back_inval => ldq_rel_back_invalidated, + rel4_set_val => rel4_set_val, + rel4_recirc_val => recirc_rel_val_q, + rel4_ecc_err => ldq_rel_ecc_err, + rel_way_wen_a => rel_wayA_wen, + rel_way_wen_b => rel_wayB_wen, + rel_way_wen_c => rel_wayC_wen, + rel_way_wen_d => rel_wayD_wen, + rel_way_wen_e => rel_wayE_wen, + rel_way_wen_f => rel_wayF_wen, + rel_way_wen_g => rel_wayG_wen, + rel_way_wen_h => rel_wayH_wen, + rel_up_way_addr_b => rel_up_way_addr_b, + rel_dcarr_addr_en => rel_dcarr_addr_en, + + xu_lsu_dci => xu_lsu_dci, + xu_lsu_spr_xucr0_clfc => xu_lsu_spr_xucr0_clfc, + spr_xucr0_dcdis => spr_xucr0_dcdis_q, + spr_xucr0_cls => spr_xucr0_cls_int, + + ex1_thrd_id => ex1_thrd_id, + ex1_p_addr => ex1_p_addr, + ex2_is_inval_op => ex2_is_inval_op, + ex2_lock_set => ex2_lock_set, + ex2_lock_clr => ex2_lock_clr, + ex3_cache_en => ex3_cache_en, + ex3_cache_acc => ex3_cache_acc_int, + ex3_tag_way_perr => ex3_tag_way_perr, + ex5_load_op_hit => ex5_load_op_hit, + ex6_ld_par_err => ex6_ld_par_err, + ex2_ldawx_instr => ex2_ldawx_instr, + ex2_wclr_instr => ex2_wclr_instr, + ex2_wchk_val => ex2_wchk_val, + ex2_l_fld => ex2_l_fld, + ex2_store_instr => store_instr_ex2, + ex3_load_val => ex3_load_val, + ex3_wimge_i_bit => ex3_wimge_i_bit, + ex3_l2_request => ex3_l2_request, + ex3_ldq_potential_flush => ex3_ldq_potential_flush, + + inv1_val => ex1_l2_inv_val, + + ex3_way_cmp_a => ex3_way_cmp_a, + ex3_way_cmp_b => ex3_way_cmp_b, + ex3_way_cmp_c => ex3_way_cmp_c, + ex3_way_cmp_d => ex3_way_cmp_d, + ex3_way_cmp_e => ex3_way_cmp_e, + ex3_way_cmp_f => ex3_way_cmp_f, + ex3_way_cmp_g => ex3_way_cmp_g, + ex3_way_cmp_h => ex3_way_cmp_h, + + ex2_stg_flush => stg_ex2_flush, + ex3_stg_flush => stg_ex3_flush, + ex4_stg_flush => stg_ex4_flush, + ex5_stg_flush => stg_ex5_flush, + + pc_xu_inj_dcachedir_multihit => pc_xu_inj_dcachedir_multihit, + + ex4_way_a_dir => ex4_way_a_dir, + ex4_way_b_dir => ex4_way_b_dir, + ex4_way_c_dir => ex4_way_c_dir, + ex4_way_d_dir => ex4_way_d_dir, + ex4_way_e_dir => ex4_way_e_dir, + ex4_way_f_dir => ex4_way_f_dir, + ex4_way_g_dir => ex4_way_g_dir, + ex4_way_h_dir => ex4_way_h_dir, + + ex4_way_a_hit => ex4_way_a_hit, + ex4_way_b_hit => ex4_way_b_hit, + ex4_way_c_hit => ex4_way_c_hit, + ex4_way_d_hit => ex4_way_d_hit, + ex4_way_e_hit => ex4_way_e_hit, + ex4_way_f_hit => ex4_way_f_hit, + ex4_way_g_hit => ex4_way_g_hit, + ex4_way_h_hit => ex4_way_h_hit, + + ex2_lockwatchSet_rel_coll => ex2_lockwatchSet_rel_coll, + ex3_wclr_all_flush => ex3_wclr_all_flush, + + ex3_cClass_upd_way_a => ex3_cClass_upd_way_a, + ex3_cClass_upd_way_b => ex3_cClass_upd_way_b, + ex3_cClass_upd_way_c => ex3_cClass_upd_way_c, + ex3_cClass_upd_way_d => ex3_cClass_upd_way_d, + ex3_cClass_upd_way_e => ex3_cClass_upd_way_e, + ex3_cClass_upd_way_f => ex3_cClass_upd_way_f, + ex3_cClass_upd_way_g => ex3_cClass_upd_way_g, + ex3_cClass_upd_way_h => ex3_cClass_upd_way_h, + + ex3_hit => ex3_l1hit, + ex3_dir_perr_det => ex3_dir_perr_det, + ex4_dir_multihit_det => ex4_dir_multihit_det, + ex4_n_lsu_ddmh_flush => ex4_n_lsu_ddmh_flush, + ex4_ldq_full_flush => ex4_ldq_full_flush, + ex4_miss => ex4_l1miss, + ex4_snd_ld_l2 => ex4_snd_ld_l2, + dcpar_err_flush => dcpar_err_flush, + pe_recov_begin => pe_recov_begin, + + lsu_xu_ex5_cr_rslt => lsu_xu_ex5_cr_rslt, + + rel_way_val_a => rel_way_val_a, + rel_way_val_b => rel_way_val_b, + rel_way_val_c => rel_way_val_c, + rel_way_val_d => rel_way_val_d, + rel_way_val_e => rel_way_val_e, + rel_way_val_f => rel_way_val_f, + rel_way_val_g => rel_way_val_g, + rel_way_val_h => rel_way_val_h, + + rel_way_lock_a => rel_way_lock_a, + rel_way_lock_b => rel_way_lock_b, + rel_way_lock_c => rel_way_lock_c, + rel_way_lock_d => rel_way_lock_d, + rel_way_lock_e => rel_way_lock_e, + rel_way_lock_f => rel_way_lock_f, + rel_way_lock_g => rel_way_lock_g, + rel_way_lock_h => rel_way_lock_h, + + dcarr_up_way_addr => dcarr_up_way_addr, + + lsu_xu_perf_events => lsu_xu_perf_events(21 to 37), + + lsu_xu_spr_xucr0_cslc_xuop => lsu_xu_spr_xucr0_cslc_xuop, + lsu_xu_spr_xucr0_cslc_binv => lsu_xu_spr_xucr0_cslc_binv, + + dc_val_dbg_data => dc_val_dbg_data, + + vdd => vdd, + gnd => gnd, + nclk => nclk, + sg_0 => sg_0, + func_sl_thold_0_b => func_sl_thold_0_b, + func_sl_force => func_sl_force, + func_slp_sl_thold_0_b => func_slp_sl_thold_0_b, + func_slp_sl_force => func_slp_sl_force, + func_nsl_thold_0_b => func_nsl_thold_0_b, + func_nsl_force => func_nsl_force, + func_slp_nsl_thold_0_b => func_slp_nsl_thold_0_b, + func_slp_nsl_force => func_slp_nsl_force, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc, + mpw1_dc_b => mpw1_dc_b, + mpw2_dc_b => mpw2_dc_b, + scan_in => scan_in(1 to 3), + scan_out(0 to 1) => scan_out(1 to 2), + scan_out(2) => dir_scan_out +); + +ex4_dir_perr_det_d <= ex3_dir_perr_det; + +l1dcdl : entity work.xuq_lsu_dir_lru32(xuq_lsu_dir_lru32) +GENERIC MAP(expand_type => expand_type, + dc_size => dc_size, + lmq_entries => lmq_entries, + cl_size => cl_size) +PORT MAP( + + ex1_stg_act => ex1_stg_act_int, + ex2_stg_act => ex2_stg_act_int, + ex3_stg_act => ex3_stg_act_int, + ex4_stg_act => ex4_stg_act_int, + ex5_stg_act => ex5_stg_act_int, + rel1_stg_act => rel1_stg_act_int, + rel2_stg_act => rel2_stg_act_int, + rel3_stg_act => rel3_stg_act_int, + + rel1_val => rel1_val, + rel1_classid => rel1_classid, + rel_mid_val => rel_mid_val, + rel_retry_val => ldq_rel_retry_val, + rel3_val => rel3_val, + rel_st_tag => rel_st_tag, + rel_st_tag_early => rel_st_tag_early, + rel_addr_early => ldq_rel_addr_early(64-(dc_size-3) to 63-cl_size), + rel_lock_en => rel_lock_en, + rel4_recirc_val => recirc_rel_val_q, + rel4_ecc_err => ldq_rel_ecc_err, + + rel_way_val_a => rel_way_val_a, + rel_way_val_b => rel_way_val_b, + rel_way_val_c => rel_way_val_c, + rel_way_val_d => rel_way_val_d, + rel_way_val_e => rel_way_val_e, + rel_way_val_f => rel_way_val_f, + rel_way_val_g => rel_way_val_g, + rel_way_val_h => rel_way_val_h, + + rel_way_lock_a => rel_way_lock_a, + rel_way_lock_b => rel_way_lock_b, + rel_way_lock_c => rel_way_lock_c, + rel_way_lock_d => rel_way_lock_d, + rel_way_lock_e => rel_way_lock_e, + rel_way_lock_f => rel_way_lock_f, + rel_way_lock_g => rel_way_lock_g, + rel_way_lock_h => rel_way_lock_h, + + ex1_p_addr => ex1_p_addr, + ex2_no_lru_upd => ex2_no_lru_upd, + ex3_cache_en => ex3_cache_en, + + ex4_way_a_hit => ex4_way_a_hit, + ex4_way_b_hit => ex4_way_b_hit, + ex4_way_c_hit => ex4_way_c_hit, + ex4_way_d_hit => ex4_way_d_hit, + ex4_way_e_hit => ex4_way_e_hit, + ex4_way_f_hit => ex4_way_f_hit, + ex4_way_g_hit => ex4_way_g_hit, + ex4_way_h_hit => ex4_way_h_hit, + ex3_hit => ex3_l1hit, + + ex3_stg_flush => stg_ex3_flush, + ex4_stg_flush => stg_ex4_flush, + ex5_stg_flush => stg_ex5_flush, + + spr_xucr2_rmt => spr_xucr2_rmt, + spr_xucr0_wlck => spr_xucr0_wlck, + spr_xucr0_dcdis => spr_xucr0_dcdis_q, + spr_xucr0_cls => spr_xucr0_cls_int, + + rel_way_upd_a => rel_way_upd_a, + rel_way_upd_b => rel_way_upd_b, + rel_way_upd_c => rel_way_upd_c, + rel_way_upd_d => rel_way_upd_d, + rel_way_upd_e => rel_way_upd_e, + rel_way_upd_f => rel_way_upd_f, + rel_way_upd_g => rel_way_upd_g, + rel_way_upd_h => rel_way_upd_h, + + rel_way_wen_a => rel_wayA_wen, + rel_way_wen_b => rel_wayB_wen, + rel_way_wen_c => rel_wayC_wen, + rel_way_wen_d => rel_wayD_wen, + rel_way_wen_e => rel_wayE_wen, + rel_way_wen_f => rel_wayF_wen, + rel_way_wen_g => rel_wayG_wen, + rel_way_wen_h => rel_wayH_wen, + + rel_way_clr_a => rel_way_clr_a, + rel_way_clr_b => rel_way_clr_b, + rel_way_clr_c => rel_way_clr_c, + rel_way_clr_d => rel_way_clr_d, + rel_way_clr_e => rel_way_clr_e, + rel_way_clr_f => rel_way_clr_f, + rel_way_clr_g => rel_way_clr_g, + rel_way_clr_h => rel_way_clr_h, + rel_dcarr_val_upd => rel_dcarr_val_upd, + rel_up_way_addr_b => rel_up_way_addr_b, + rel_dcarr_addr_en => rel_dcarr_addr_en, + + lsu_xu_spr_xucr0_clo => lsu_xu_spr_xucr0_clo, + ex4_dir_lru => ex4_dir_lru, + dc_lru_dbg_data => dc_lru_dbg_data, + + vdd => vdd, + gnd => gnd, + nclk => nclk, + sg_0 => sg_0, + func_sl_thold_0_b => func_sl_thold_0_b, + func_sl_force => func_sl_force, + func_nsl_thold_0_b => func_nsl_thold_0_b, + func_nsl_force => func_nsl_force, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc, + mpw1_dc_b => mpw1_dc_b, + mpw2_dc_b => mpw2_dc_b, + scan_in => dir_scan_out, + scan_out => lru_scan_out + ); +end generate dir32k; + +l1dcdt : entity work.xuq_lsu_dir_tag(xuq_lsu_dir_tag) +GENERIC MAP(expand_type => expand_type, + dc_size => dc_size, + cl_size => cl_size, + wayDataSize => wayDataSize, + parBits => parBits, + real_data_add => real_data_add) +PORT MAP ( + + ex2_stg_act => ex2_stg_act_int, + binv2_stg_act => binv2_stg_act_int, + + rel_addr_early => ldq_rel_addr_early, + rel_way_upd_a => rel_way_upd_a, + rel_way_upd_b => rel_way_upd_b, + rel_way_upd_c => rel_way_upd_c, + rel_way_upd_d => rel_way_upd_d, + rel_way_upd_e => rel_way_upd_e, + rel_way_upd_f => rel_way_upd_f, + rel_way_upd_g => rel_way_upd_g, + rel_way_upd_h => rel_way_upd_h, + + inv1_val => ex1_l2_inv_val, + + xu_lsu_spr_xucr0_dcdis => xu_lsu_spr_xucr0_dcdis, + + ex1_p_addr_01 => ex1_dir01_addr, + ex1_p_addr_23 => ex1_dir23_addr, + ex1_p_addr_45 => ex1_dir45_addr, + ex1_p_addr_67 => ex1_dir67_addr, + ex2_ddir_acc_instr => ex2_ddir_acc_instr, + + pc_xu_inj_dcachedir_parity => pc_xu_inj_dcachedir_parity, + + dir_arr_rd_addr_01 => dir_arr_rd_addr_01, + dir_arr_rd_addr_23 => dir_arr_rd_addr_23, + dir_arr_rd_addr_45 => dir_arr_rd_addr_45, + dir_arr_rd_addr_67 => dir_arr_rd_addr_67, + dir_arr_rd_data => dir_arr_rd_data, + + dir_wr_way => dir_wr_way_int, + dir_arr_wr_addr => dir_arr_wr_addr_int, + dir_arr_wr_data => dir_arr_wr_data_int, + + ex2_wayA_tag => ex2_wayA_tag, + ex2_wayB_tag => ex2_wayB_tag, + ex2_wayC_tag => ex2_wayC_tag, + ex2_wayD_tag => ex2_wayD_tag, + ex2_wayE_tag => ex2_wayE_tag, + ex2_wayF_tag => ex2_wayF_tag, + ex2_wayG_tag => ex2_wayG_tag, + ex2_wayH_tag => ex2_wayH_tag, + + ex3_way_tag_par_a => ex3_way_tag_par_a, + ex3_way_tag_par_b => ex3_way_tag_par_b, + ex3_way_tag_par_c => ex3_way_tag_par_c, + ex3_way_tag_par_d => ex3_way_tag_par_d, + ex3_way_tag_par_e => ex3_way_tag_par_e, + ex3_way_tag_par_f => ex3_way_tag_par_f, + ex3_way_tag_par_g => ex3_way_tag_par_g, + ex3_way_tag_par_h => ex3_way_tag_par_h, + + ex3_tag_way_perr => ex3_tag_way_perr, + + vdd => vdd, + gnd => gnd, + nclk => nclk, + sg_0 => sg_0, + func_sl_thold_0_b => func_sl_thold_0_b, + func_sl_force => func_sl_force, + func_slp_sl_thold_0_b => func_slp_sl_thold_0_b, + func_slp_sl_force => func_slp_sl_force, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc, + mpw1_dc_b => mpw1_dc_b, + mpw2_dc_b => mpw2_dc_b, + scan_in => lru_scan_out, + scan_out => tag_scan_out + ); + + +dir_arr_dbg_data_d <= dir_wr_enable_int & dir_wr_way_int & dir_arr_wr_addr_int & dir_arr_wr_data_int & + ex1_dir_acc_val & ex1_l2_inv_val & binv1_ex1_stg_act & recirc_rel_val_q & + lwr_p_addr_q(53 to 57); + +dir_arr_dbg_data <= dir_arr_dbg_data_q; + +dc_dir_dbg_data <= ldq_rel1_val_stg_q & ldq_rel_mid_stg_q & ldq_rel3_val_stg_q & ldq_rel_data_stg_q & + ldq_rel_set_stg_q & rel24_addr_q; + +xu_derat_ex1_epn_arr <= ex1_agen_addr(64-(2**regmode) to 51); +xu_derat_ex1_epn_nonarr <= ex1_eff_addr(64-(2**regmode) to 51); +ex3_dcbtls_instr <= dcbtls_instr_ex3; +ex3_dcbtstls_instr <= dcbtstls_instr_ex3; +ex3_stg_flush <= stg_ex3_flush; +ex4_stg_flush <= stg_ex4_flush; +lsu_xu_ex3_ddir_par_err <= ex3_dir_perr_det; +lsu_xu_ex4_ldq_full_flush <= ex4_ldq_full_flush; +ex4_dir_perr_det <= ex4_dir_perr_det_q; +spr_xucr0_cls <= spr_xucr0_cls_int; +ldq_recirc_rel_val <= recirc_rel_val_q; +xu_derat_rf1_binv_val <= rf1_l2_inv_val; +dir_arr_wr_addr <= dir_arr_wr_addr_int; +dir_arr_wr_data <= dir_arr_wr_data_int; +dir_wr_way <= dir_wr_way_int; +ex2_p_addr_lwr <= ex2_p_addr_lwr_int(52 to 57); +ex3_cache_acc <= ex3_cache_acc_int; + +ex1_stg_act <= ex1_stg_act_int; +ex2_stg_act <= ex2_stg_act_int; +ex3_stg_act <= ex3_stg_act_int; +ex4_stg_act <= ex4_stg_act_int; +binv1_stg_act <= binv1_stg_act_int; +binv2_stg_act <= binv2_stg_act_int; + +lwr_p_addr_reg: tri_rlmreg_p +generic map (width => 12, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv1_ex1_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(lwr_p_addr_offset to lwr_p_addr_offset + lwr_p_addr_d'length-1), + scout => sov(lwr_p_addr_offset to lwr_p_addr_offset + lwr_p_addr_d'length-1), + din => lwr_p_addr_d, + dout => lwr_p_addr_q); +ldq_rel1_val_stg_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ldq_rel1_val_stg_offset), + scout => sov(ldq_rel1_val_stg_offset), + din => ldq_rel1_val_stg_d, + dout => ldq_rel1_val_stg_q); +ldq_rel_mid_stg_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ldq_rel_mid_stg_offset), + scout => sov(ldq_rel_mid_stg_offset), + din => ldq_rel_mid_stg_d, + dout => ldq_rel_mid_stg_q); +ldq_rel3_val_stg_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ldq_rel3_val_stg_offset), + scout => sov(ldq_rel3_val_stg_offset), + din => ldq_rel3_val_stg_d, + dout => ldq_rel3_val_stg_q); +ldq_rel_data_stg_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ldq_rel_data_stg_d, + dout(0) => ldq_rel_data_stg_q); +ldq_rel_set_stg_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ldq_rel_set_stg_d, + dout(0) => ldq_rel_set_stg_q); +rel24_addr_reg: tri_regk +generic map (width => real_data_add-11, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act_int, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel24_addr_d, + dout => rel24_addr_q); +spr_xucr0_dcdis_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(spr_xucr0_dcdis_offset), + scout => sov(spr_xucr0_dcdis_offset), + din => spr_xucr0_dcdis_d, + dout => spr_xucr0_dcdis_q); +ex2_frc_align_reg: tri_regk +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_int, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex2_frc_align_d, + dout => ex2_frc_align_q); + +ldq_rel_stg24_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ldq_rel_stg24_val_d, + dout(0) => ldq_rel_stg24_val_q); + +ex4_dir_perr_det_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_dir_perr_det_offset), + scout => sov(ex4_dir_perr_det_offset), + din => ex4_dir_perr_det_d, + dout => ex4_dir_perr_det_q); + +recirc_rel_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(recirc_rel_val_offset), + scout => sov(recirc_rel_val_offset), + din => recirc_rel_val_d, + dout => recirc_rel_val_q); + +trace_bus_enable_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(trace_bus_enable_offset), + scout => sov(trace_bus_enable_offset), + din => pc_xu_trace_bus_enable, + dout => trace_bus_enable_q); + +dir_arr_dbg_data_reg: tri_regk +generic map (width => 61, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => trace_bus_enable_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => dir_arr_dbg_data_d, + dout => dir_arr_dbg_data_q); + +siv(0 to scan_right) <= sov(1 to scan_right) & tag_scan_out; +scan_out(3) <= sov(0); +end xuq_lsu_dir; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_dir_lru16.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_dir_lru16.vhdl new file mode 100644 index 0000000..98bc632 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_dir_lru16.vhdl @@ -0,0 +1,3841 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ibm, ieee, work, tri, support; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use tri.tri_latches_pkg.all; +use support.power_logic_pkg.all; + +entity xuq_lsu_dir_lru16 is +generic(expand_type : integer := 2; + dc_size : natural := 14; + lmq_entries : integer := 8; + cl_size : natural := 6); +port( + + ex1_stg_act :in std_ulogic; + ex2_stg_act :in std_ulogic; + ex3_stg_act :in std_ulogic; + ex4_stg_act :in std_ulogic; + ex5_stg_act :in std_ulogic; + rel1_stg_act :in std_ulogic; + rel2_stg_act :in std_ulogic; + rel3_stg_act :in std_ulogic; + + rel1_val :in std_ulogic; + rel1_classid :in std_ulogic_vector(0 to 1); + rel_mid_val :in std_ulogic; + rel_retry_val :in std_ulogic; + rel3_val :in std_ulogic; + rel4_recirc_val :in std_ulogic; + rel4_ecc_err :in std_ulogic; + rel_st_tag_early :in std_ulogic_vector(1 to 3); + rel_st_tag :in std_ulogic_vector(1 to 3); + rel_addr_early :in std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + rel_lock_en :in std_ulogic; + + rel_way_val_a :in std_ulogic; + rel_way_val_b :in std_ulogic; + rel_way_val_c :in std_ulogic; + rel_way_val_d :in std_ulogic; + rel_way_val_e :in std_ulogic; + rel_way_val_f :in std_ulogic; + rel_way_val_g :in std_ulogic; + rel_way_val_h :in std_ulogic; + + rel_way_lock_a :in std_ulogic; + rel_way_lock_b :in std_ulogic; + rel_way_lock_c :in std_ulogic; + rel_way_lock_d :in std_ulogic; + rel_way_lock_e :in std_ulogic; + rel_way_lock_f :in std_ulogic; + rel_way_lock_g :in std_ulogic; + rel_way_lock_h :in std_ulogic; + + ex1_p_addr :in std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + ex3_cache_en :in std_ulogic; + ex2_no_lru_upd :in std_ulogic; + + ex4_way_a_hit :in std_ulogic; + ex4_way_b_hit :in std_ulogic; + ex4_way_c_hit :in std_ulogic; + ex4_way_d_hit :in std_ulogic; + ex4_way_e_hit :in std_ulogic; + ex4_way_f_hit :in std_ulogic; + ex4_way_g_hit :in std_ulogic; + ex4_way_h_hit :in std_ulogic; + ex3_hit :in std_ulogic; + + spr_xucr2_rmt :in std_ulogic_vector(0 to 31); + spr_xucr0_wlck :in std_ulogic; + spr_xucr0_dcdis :in std_ulogic; + spr_xucr0_cls :in std_ulogic; + + ex3_stg_flush :in std_ulogic; + ex4_stg_flush :in std_ulogic; + ex5_stg_flush :in std_ulogic; + + rel_way_upd_a :out std_ulogic; + rel_way_upd_b :out std_ulogic; + rel_way_upd_c :out std_ulogic; + rel_way_upd_d :out std_ulogic; + rel_way_upd_e :out std_ulogic; + rel_way_upd_f :out std_ulogic; + rel_way_upd_g :out std_ulogic; + rel_way_upd_h :out std_ulogic; + + rel_way_wen_a :out std_ulogic; + rel_way_wen_b :out std_ulogic; + rel_way_wen_c :out std_ulogic; + rel_way_wen_d :out std_ulogic; + rel_way_wen_e :out std_ulogic; + rel_way_wen_f :out std_ulogic; + rel_way_wen_g :out std_ulogic; + rel_way_wen_h :out std_ulogic; + + rel_way_clr_a :out std_ulogic; + rel_way_clr_b :out std_ulogic; + rel_way_clr_c :out std_ulogic; + rel_way_clr_d :out std_ulogic; + rel_way_clr_e :out std_ulogic; + rel_way_clr_f :out std_ulogic; + rel_way_clr_g :out std_ulogic; + rel_way_clr_h :out std_ulogic; + rel_dcarr_val_upd :out std_ulogic; + rel_up_way_addr_b :out std_ulogic_vector(0 to 2); + rel_dcarr_addr_en :out std_ulogic; + + lsu_xu_spr_xucr0_clo :out std_ulogic; + + ex4_dir_lru :out std_ulogic_vector(0 to 6); + + dc_lru_dbg_data :out std_ulogic_vector(0 to 81); + + vdd :inout power_logic; + gnd :inout power_logic; + nclk :in clk_logic; + sg_0 :in std_ulogic; + func_sl_thold_0_b :in std_ulogic; + func_sl_force :in std_ulogic; + func_nsl_thold_0_b :in std_ulogic; + func_nsl_force :in std_ulogic; + d_mode_dc :in std_ulogic; + delay_lclkr_dc :in std_ulogic; + mpw1_dc_b :in std_ulogic; + mpw2_dc_b :in std_ulogic; + scan_in :in std_ulogic; + scan_out :out std_ulogic + ); +-- synopsys translate_off +-- synopsys translate_on +end xuq_lsu_dir_lru16; +ARCHITECTURE XUQ_LSU_DIR_LRU16 + OF XUQ_LSU_DIR_LRU16 + IS +constant congr_cl0_lru_offset :natural := 0; +constant congr_cl1_lru_offset :natural := congr_cl0_lru_offset + 7; +constant congr_cl2_lru_offset :natural := congr_cl1_lru_offset + 7; +constant congr_cl3_lru_offset :natural := congr_cl2_lru_offset + 7; +constant congr_cl4_lru_offset :natural := congr_cl3_lru_offset + 7; +constant congr_cl5_lru_offset :natural := congr_cl4_lru_offset + 7; +constant congr_cl6_lru_offset :natural := congr_cl5_lru_offset + 7; +constant congr_cl7_lru_offset :natural := congr_cl6_lru_offset + 7; +constant congr_cl8_lru_offset :natural := congr_cl7_lru_offset + 7; +constant congr_cl9_lru_offset :natural := congr_cl8_lru_offset + 7; +constant congr_cl10_lru_offset :natural := congr_cl9_lru_offset + 7; +constant congr_cl11_lru_offset :natural := congr_cl10_lru_offset + 7; +constant congr_cl12_lru_offset :natural := congr_cl11_lru_offset + 7; +constant congr_cl13_lru_offset :natural := congr_cl12_lru_offset + 7; +constant congr_cl14_lru_offset :natural := congr_cl13_lru_offset + 7; +constant congr_cl15_lru_offset :natural := congr_cl14_lru_offset + 7; +constant congr_cl16_lru_offset :natural := congr_cl15_lru_offset + 7; +constant congr_cl17_lru_offset :natural := congr_cl16_lru_offset + 7; +constant congr_cl18_lru_offset :natural := congr_cl17_lru_offset + 7; +constant congr_cl19_lru_offset :natural := congr_cl18_lru_offset + 7; +constant congr_cl20_lru_offset :natural := congr_cl19_lru_offset + 7; +constant congr_cl21_lru_offset :natural := congr_cl20_lru_offset + 7; +constant congr_cl22_lru_offset :natural := congr_cl21_lru_offset + 7; +constant congr_cl23_lru_offset :natural := congr_cl22_lru_offset + 7; +constant congr_cl24_lru_offset :natural := congr_cl23_lru_offset + 7; +constant congr_cl25_lru_offset :natural := congr_cl24_lru_offset + 7; +constant congr_cl26_lru_offset :natural := congr_cl25_lru_offset + 7; +constant congr_cl27_lru_offset :natural := congr_cl26_lru_offset + 7; +constant congr_cl28_lru_offset :natural := congr_cl27_lru_offset + 7; +constant congr_cl29_lru_offset :natural := congr_cl28_lru_offset + 7; +constant congr_cl30_lru_offset :natural := congr_cl29_lru_offset + 7; +constant congr_cl31_lru_offset :natural := congr_cl30_lru_offset + 7; +constant congr_cl_lru_b_offset :natural := congr_cl31_lru_offset + 7; +constant rel_congr_cl_lru_b_offset :natural := congr_cl_lru_b_offset + 7; +constant reld_q_sel_offset :natural := rel_congr_cl_lru_b_offset + 7; +constant ex5_congr_cl_offset :natural := reld_q_sel_offset + 8; +constant rel_congr_cl_offset :natural := ex5_congr_cl_offset + 5; +constant relu_congr_cl_offset :natural := rel_congr_cl_offset + 5; +constant ex5_lru_upd_offset :natural := relu_congr_cl_offset + 5; +constant rel2_val_offset :natural := ex5_lru_upd_offset + 7; +constant relu_val_wen_offset :natural := rel2_val_offset + 1; +constant ex4_hit_offset :natural := relu_val_wen_offset + 1; +constant ex4_c_acc_offset :natural := ex4_hit_offset + 1; +constant ex5_c_acc_offset :natural := ex4_c_acc_offset + 1; +constant ex6_c_acc_val_offset :natural := ex5_c_acc_offset + 1; +constant ex3_congr_cl_offset :natural := ex6_c_acc_val_offset + 1; +constant rel_val_wen_offset :natural := ex3_congr_cl_offset + 5; +constant relu_lru_upd_offset :natural := rel_val_wen_offset + 1; +constant rel_way_qsel_offset :natural := relu_lru_upd_offset + 7; +constant rel_val_qsel_offset :natural := rel_way_qsel_offset + 8; +constant rel_way_early_qsel_offset :natural := rel_val_qsel_offset + 1; +constant rel_val_early_qsel_offset :natural := rel_way_early_qsel_offset + 8; +constant rel4_val_offset :natural := rel_val_early_qsel_offset + 1; +constant rel2_mid_val_offset :natural := rel4_val_offset + 1; +constant rel4_retry_val_offset :natural := rel2_mid_val_offset + 1; +constant rel2_wlock_offset :natural := rel4_retry_val_offset + 1; +constant reld_q0_congr_cl_offset :natural := rel2_wlock_offset + 8; +constant reld_q1_congr_cl_offset :natural := reld_q0_congr_cl_offset + 5; +constant reld_q2_congr_cl_offset :natural := reld_q1_congr_cl_offset + 5; +constant reld_q3_congr_cl_offset :natural := reld_q2_congr_cl_offset + 5; +constant reld_q4_congr_cl_offset :natural := reld_q3_congr_cl_offset + 5; +constant reld_q5_congr_cl_offset :natural := reld_q4_congr_cl_offset + 5; +constant reld_q6_congr_cl_offset :natural := reld_q5_congr_cl_offset + 5; +constant reld_q7_congr_cl_offset :natural := reld_q6_congr_cl_offset + 5; +constant reld_q0_way_offset :natural := reld_q7_congr_cl_offset + 5; +constant reld_q1_way_offset :natural := reld_q0_way_offset + 8; +constant reld_q2_way_offset :natural := reld_q1_way_offset + 8; +constant reld_q3_way_offset :natural := reld_q2_way_offset + 8; +constant reld_q4_way_offset :natural := reld_q3_way_offset + 8; +constant reld_q5_way_offset :natural := reld_q4_way_offset + 8; +constant reld_q6_way_offset :natural := reld_q5_way_offset + 8; +constant reld_q7_way_offset :natural := reld_q6_way_offset + 8; +constant reld_q0_val_offset :natural := reld_q7_way_offset + 8; +constant reld_q1_val_offset :natural := reld_q0_val_offset + 1; +constant reld_q2_val_offset :natural := reld_q1_val_offset + 1; +constant reld_q3_val_offset :natural := reld_q2_val_offset + 1; +constant reld_q4_val_offset :natural := reld_q3_val_offset + 1; +constant reld_q5_val_offset :natural := reld_q4_val_offset + 1; +constant reld_q6_val_offset :natural := reld_q5_val_offset + 1; +constant reld_q7_val_offset :natural := reld_q6_val_offset + 1; +constant reld_q0_lock_offset :natural := reld_q7_val_offset + 1; +constant reld_q1_lock_offset :natural := reld_q0_lock_offset + 1; +constant reld_q2_lock_offset :natural := reld_q1_lock_offset + 1; +constant reld_q3_lock_offset :natural := reld_q2_lock_offset + 1; +constant reld_q4_lock_offset :natural := reld_q3_lock_offset + 1; +constant reld_q5_lock_offset :natural := reld_q4_lock_offset + 1; +constant reld_q6_lock_offset :natural := reld_q5_lock_offset + 1; +constant reld_q7_lock_offset :natural := reld_q6_lock_offset + 1; +constant rel_m_q_way_offset :natural := reld_q7_lock_offset + 1; +constant ex3_no_lru_upd_offset :natural := rel_m_q_way_offset + 8; +constant rel2_lock_en_offset :natural := ex3_no_lru_upd_offset + 1; +constant xucr0_clo_offset :natural := rel2_lock_en_offset + 1; +constant rel_up_way_addr_offset :natural := xucr0_clo_offset + 1; +constant rel_dcarr_addr_en_offset :natural := rel_up_way_addr_offset + 3; +constant rel_dcarr_val_upd_offset :natural := rel_dcarr_addr_en_offset + 1; +constant congr_cl_ex3_ex4_cmp_offset :natural := rel_dcarr_val_upd_offset + 1; +constant congr_cl_ex3_ex5_cmp_offset :natural := congr_cl_ex3_ex4_cmp_offset + 1; +constant congr_cl_ex3_ex6_cmp_offset :natural := congr_cl_ex3_ex5_cmp_offset + 1; +constant congr_cl_ex3_rel2_cmp_offset :natural := congr_cl_ex3_ex6_cmp_offset + 1; +constant congr_cl_ex3_rel_upd_cmp_offset :natural := congr_cl_ex3_rel2_cmp_offset + 1; +constant congr_cl_rel1_ex4_cmp_offset :natural := congr_cl_ex3_rel_upd_cmp_offset + 1; +constant congr_cl_rel1_ex5_cmp_offset :natural := congr_cl_rel1_ex4_cmp_offset + 1; +constant congr_cl_rel1_ex6_cmp_offset :natural := congr_cl_rel1_ex5_cmp_offset + 1; +constant congr_cl_rel1_rel2_cmp_offset :natural := congr_cl_rel1_ex6_cmp_offset + 1; +constant congr_cl_rel1_relu_cmp_offset :natural := congr_cl_rel1_rel2_cmp_offset + 1; +constant congr_cl_rel1_rel_upd_cmp_offset :natural := congr_cl_rel1_relu_cmp_offset + 1; +constant congr_cl_act_offset :natural := congr_cl_rel1_rel_upd_cmp_offset + 1; +constant scan_right :natural := congr_cl_act_offset + 1 - 1; +signal congr_cl0_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl0_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl0_lru_wen :std_ulogic; +signal xu_op_cl0_lru_wen :std_ulogic; +signal rel_cl0_lru_wen :std_ulogic; +signal rel_ldst_cl0_lru :std_ulogic_vector(0 to 6); +signal congr_cl1_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl1_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl1_lru_wen :std_ulogic; +signal xu_op_cl1_lru_wen :std_ulogic; +signal rel_cl1_lru_wen :std_ulogic; +signal rel_ldst_cl1_lru :std_ulogic_vector(0 to 6); +signal congr_cl2_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl2_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl2_lru_wen :std_ulogic; +signal xu_op_cl2_lru_wen :std_ulogic; +signal rel_cl2_lru_wen :std_ulogic; +signal rel_ldst_cl2_lru :std_ulogic_vector(0 to 6); +signal congr_cl3_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl3_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl3_lru_wen :std_ulogic; +signal xu_op_cl3_lru_wen :std_ulogic; +signal rel_cl3_lru_wen :std_ulogic; +signal rel_ldst_cl3_lru :std_ulogic_vector(0 to 6); +signal congr_cl4_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl4_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl4_lru_wen :std_ulogic; +signal xu_op_cl4_lru_wen :std_ulogic; +signal rel_cl4_lru_wen :std_ulogic; +signal rel_ldst_cl4_lru :std_ulogic_vector(0 to 6); +signal congr_cl5_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl5_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl5_lru_wen :std_ulogic; +signal xu_op_cl5_lru_wen :std_ulogic; +signal rel_cl5_lru_wen :std_ulogic; +signal rel_ldst_cl5_lru :std_ulogic_vector(0 to 6); +signal congr_cl6_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl6_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl6_lru_wen :std_ulogic; +signal xu_op_cl6_lru_wen :std_ulogic; +signal rel_cl6_lru_wen :std_ulogic; +signal rel_ldst_cl6_lru :std_ulogic_vector(0 to 6); +signal congr_cl7_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl7_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl7_lru_wen :std_ulogic; +signal xu_op_cl7_lru_wen :std_ulogic; +signal rel_cl7_lru_wen :std_ulogic; +signal rel_ldst_cl7_lru :std_ulogic_vector(0 to 6); +signal congr_cl8_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl8_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl8_lru_wen :std_ulogic; +signal xu_op_cl8_lru_wen :std_ulogic; +signal rel_cl8_lru_wen :std_ulogic; +signal rel_ldst_cl8_lru :std_ulogic_vector(0 to 6); +signal congr_cl9_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl9_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl9_lru_wen :std_ulogic; +signal xu_op_cl9_lru_wen :std_ulogic; +signal rel_cl9_lru_wen :std_ulogic; +signal rel_ldst_cl9_lru :std_ulogic_vector(0 to 6); +signal congr_cl10_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl10_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl10_lru_wen :std_ulogic; +signal xu_op_cl10_lru_wen :std_ulogic; +signal rel_cl10_lru_wen :std_ulogic; +signal rel_ldst_cl10_lru :std_ulogic_vector(0 to 6); +signal congr_cl11_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl11_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl11_lru_wen :std_ulogic; +signal xu_op_cl11_lru_wen :std_ulogic; +signal rel_cl11_lru_wen :std_ulogic; +signal rel_ldst_cl11_lru :std_ulogic_vector(0 to 6); +signal congr_cl12_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl12_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl12_lru_wen :std_ulogic; +signal xu_op_cl12_lru_wen :std_ulogic; +signal rel_cl12_lru_wen :std_ulogic; +signal rel_ldst_cl12_lru :std_ulogic_vector(0 to 6); +signal congr_cl13_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl13_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl13_lru_wen :std_ulogic; +signal xu_op_cl13_lru_wen :std_ulogic; +signal rel_cl13_lru_wen :std_ulogic; +signal rel_ldst_cl13_lru :std_ulogic_vector(0 to 6); +signal congr_cl14_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl14_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl14_lru_wen :std_ulogic; +signal xu_op_cl14_lru_wen :std_ulogic; +signal rel_cl14_lru_wen :std_ulogic; +signal rel_ldst_cl14_lru :std_ulogic_vector(0 to 6); +signal congr_cl15_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl15_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl15_lru_wen :std_ulogic; +signal xu_op_cl15_lru_wen :std_ulogic; +signal rel_cl15_lru_wen :std_ulogic; +signal rel_ldst_cl15_lru :std_ulogic_vector(0 to 6); +signal congr_cl16_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl16_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl16_lru_wen :std_ulogic; +signal xu_op_cl16_lru_wen :std_ulogic; +signal rel_cl16_lru_wen :std_ulogic; +signal rel_ldst_cl16_lru :std_ulogic_vector(0 to 6); +signal congr_cl17_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl17_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl17_lru_wen :std_ulogic; +signal xu_op_cl17_lru_wen :std_ulogic; +signal rel_cl17_lru_wen :std_ulogic; +signal rel_ldst_cl17_lru :std_ulogic_vector(0 to 6); +signal congr_cl18_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl18_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl18_lru_wen :std_ulogic; +signal xu_op_cl18_lru_wen :std_ulogic; +signal rel_cl18_lru_wen :std_ulogic; +signal rel_ldst_cl18_lru :std_ulogic_vector(0 to 6); +signal congr_cl19_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl19_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl19_lru_wen :std_ulogic; +signal xu_op_cl19_lru_wen :std_ulogic; +signal rel_cl19_lru_wen :std_ulogic; +signal rel_ldst_cl19_lru :std_ulogic_vector(0 to 6); +signal congr_cl20_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl20_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl20_lru_wen :std_ulogic; +signal xu_op_cl20_lru_wen :std_ulogic; +signal rel_cl20_lru_wen :std_ulogic; +signal rel_ldst_cl20_lru :std_ulogic_vector(0 to 6); +signal congr_cl21_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl21_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl21_lru_wen :std_ulogic; +signal xu_op_cl21_lru_wen :std_ulogic; +signal rel_cl21_lru_wen :std_ulogic; +signal rel_ldst_cl21_lru :std_ulogic_vector(0 to 6); +signal congr_cl22_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl22_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl22_lru_wen :std_ulogic; +signal xu_op_cl22_lru_wen :std_ulogic; +signal rel_cl22_lru_wen :std_ulogic; +signal rel_ldst_cl22_lru :std_ulogic_vector(0 to 6); +signal congr_cl23_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl23_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl23_lru_wen :std_ulogic; +signal xu_op_cl23_lru_wen :std_ulogic; +signal rel_cl23_lru_wen :std_ulogic; +signal rel_ldst_cl23_lru :std_ulogic_vector(0 to 6); +signal congr_cl24_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl24_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl24_lru_wen :std_ulogic; +signal xu_op_cl24_lru_wen :std_ulogic; +signal rel_cl24_lru_wen :std_ulogic; +signal rel_ldst_cl24_lru :std_ulogic_vector(0 to 6); +signal congr_cl25_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl25_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl25_lru_wen :std_ulogic; +signal xu_op_cl25_lru_wen :std_ulogic; +signal rel_cl25_lru_wen :std_ulogic; +signal rel_ldst_cl25_lru :std_ulogic_vector(0 to 6); +signal congr_cl26_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl26_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl26_lru_wen :std_ulogic; +signal xu_op_cl26_lru_wen :std_ulogic; +signal rel_cl26_lru_wen :std_ulogic; +signal rel_ldst_cl26_lru :std_ulogic_vector(0 to 6); +signal congr_cl27_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl27_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl27_lru_wen :std_ulogic; +signal xu_op_cl27_lru_wen :std_ulogic; +signal rel_cl27_lru_wen :std_ulogic; +signal rel_ldst_cl27_lru :std_ulogic_vector(0 to 6); +signal congr_cl28_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl28_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl28_lru_wen :std_ulogic; +signal xu_op_cl28_lru_wen :std_ulogic; +signal rel_cl28_lru_wen :std_ulogic; +signal rel_ldst_cl28_lru :std_ulogic_vector(0 to 6); +signal congr_cl29_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl29_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl29_lru_wen :std_ulogic; +signal xu_op_cl29_lru_wen :std_ulogic; +signal rel_cl29_lru_wen :std_ulogic; +signal rel_ldst_cl29_lru :std_ulogic_vector(0 to 6); +signal congr_cl30_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl30_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl30_lru_wen :std_ulogic; +signal xu_op_cl30_lru_wen :std_ulogic; +signal rel_cl30_lru_wen :std_ulogic; +signal rel_ldst_cl30_lru :std_ulogic_vector(0 to 6); +signal congr_cl31_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl31_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl31_lru_wen :std_ulogic; +signal xu_op_cl31_lru_wen :std_ulogic; +signal rel_cl31_lru_wen :std_ulogic; +signal rel_ldst_cl31_lru :std_ulogic_vector(0 to 6); +signal ex1_congr_cl :std_ulogic_vector(3 to 7); +signal ex2_congr_cl_d :std_ulogic_vector(3 to 7); +signal ex2_congr_cl_q :std_ulogic_vector(3 to 7); +signal ex3_congr_cl_d :std_ulogic_vector(3 to 7); +signal ex3_congr_cl_q :std_ulogic_vector(3 to 7); +signal ex4_congr_cl_d :std_ulogic_vector(3 to 7); +signal ex4_congr_cl_q :std_ulogic_vector(3 to 7); +signal ex5_congr_cl_d :std_ulogic_vector(3 to 7); +signal ex5_congr_cl_q :std_ulogic_vector(3 to 7); +signal ex6_congr_cl_d :std_ulogic_vector(3 to 7); +signal ex6_congr_cl_q :std_ulogic_vector(3 to 7); +signal rel_early_congr_cl :std_ulogic_vector(3 to 7); +signal rel_congr_cl_d :std_ulogic_vector(3 to 7); +signal rel_congr_cl_q :std_ulogic_vector(3 to 7); +signal rel_congr_cl_stg_d :std_ulogic_vector(3 to 7); +signal rel_congr_cl_stg_q :std_ulogic_vector(3 to 7); +signal relu_congr_cl_d :std_ulogic_vector(3 to 7); +signal relu_congr_cl_q :std_ulogic_vector(3 to 7); +signal rel2_val_d :std_ulogic; +signal rel2_val_q :std_ulogic; +signal relu_val_wen_d :std_ulogic; +signal relu_val_wen_q :std_ulogic; +signal rel_val_wen_d :std_ulogic; +signal rel_val_wen_q :std_ulogic; +signal congr_cl_lru_b_q :std_ulogic_vector(0 to 6); +signal rel_wayA_clr :std_ulogic; +signal rel_wayB_clr :std_ulogic; +signal rel_wayC_clr :std_ulogic; +signal rel_wayD_clr :std_ulogic; +signal rel_wayE_clr :std_ulogic; +signal rel_wayF_clr :std_ulogic; +signal rel_wayG_clr :std_ulogic; +signal rel_wayH_clr :std_ulogic; +signal rel_hit_vec :std_ulogic_vector(0 to 7); +signal hit_wayA_upd :std_ulogic_vector(0 to 6); +signal hit_wayB_upd :std_ulogic_vector(0 to 6); +signal hit_wayC_upd :std_ulogic_vector(0 to 6); +signal hit_wayD_upd :std_ulogic_vector(0 to 6); +signal hit_wayE_upd :std_ulogic_vector(0 to 6); +signal hit_wayF_upd :std_ulogic_vector(0 to 6); +signal hit_wayG_upd :std_ulogic_vector(0 to 6); +signal hit_wayh_upd :std_ulogic_vector(0 to 6); +signal rel_hit_wayA_upd :std_ulogic_vector(0 to 6); +signal rel_hit_wayB_upd :std_ulogic_vector(0 to 6); +signal rel_hit_wayC_upd :std_ulogic_vector(0 to 6); +signal rel_hit_wayD_upd :std_ulogic_vector(0 to 6); +signal rel_hit_wayE_upd :std_ulogic_vector(0 to 6); +signal rel_hit_wayF_upd :std_ulogic_vector(0 to 6); +signal rel_hit_wayG_upd :std_ulogic_vector(0 to 6); +signal rel_hit_wayh_upd :std_ulogic_vector(0 to 6); +signal ldst_wayA_hit :std_ulogic; +signal ldst_wayB_hit :std_ulogic; +signal ldst_wayC_hit :std_ulogic; +signal ldst_wayD_hit :std_ulogic; +signal ldst_wayE_hit :std_ulogic; +signal ldst_wayF_hit :std_ulogic; +signal ldst_wayG_hit :std_ulogic; +signal ldst_wayH_hit :std_ulogic; +signal lru_upd :std_ulogic_vector(0 to 6); +signal relu_lru_upd_d :std_ulogic_vector(0 to 6); +signal relu_lru_upd_q :std_ulogic_vector(0 to 6); +signal rel_lru_val_d :std_ulogic_vector(0 to 6); +signal rel_lru_val_q :std_ulogic_vector(0 to 6); +signal ex5_lru_upd_d :std_ulogic_vector(0 to 6); +signal ex5_lru_upd_q :std_ulogic_vector(0 to 6); +signal ex6_lru_upd_d :std_ulogic_vector(0 to 6); +signal ex6_lru_upd_q :std_ulogic_vector(0 to 6); +signal ex4_hit_d :std_ulogic; +signal ex4_hit_q :std_ulogic; +signal ex3_c_acc_val :std_ulogic; +signal ex4_c_acc_val :std_ulogic; +signal ex4_c_acc :std_ulogic; +signal ex4_c_acc_d :std_ulogic; +signal ex4_c_acc_q :std_ulogic; +signal ex5_c_acc_val :std_ulogic; +signal ex5_c_acc_d :std_ulogic; +signal ex5_c_acc_q :std_ulogic; +signal ex6_c_acc_val_d :std_ulogic; +signal ex6_c_acc_val_q :std_ulogic; +signal ex3_flush :std_ulogic; +signal ex4_flush :std_ulogic; +signal ex5_flush :std_ulogic; +signal xu_op_lru :std_ulogic_vector(0 to 6); +signal rel_op_lru :std_ulogic_vector(0 to 6); +signal ldst_hit_vector :std_ulogic_vector(0 to 7); +signal arr_congr_cl_lru :std_ulogic_vector(0 to 6); +signal rel_congr_cl_lru :std_ulogic_vector(0 to 6); +signal p0_arr_lru_rd :std_ulogic_vector(0 to 6); +signal p1_arr_lru_rd :std_ulogic_vector(0 to 6); +signal rel_congr_cl_lru_b_q :std_ulogic_vector(0 to 6); +signal congr_cl_ex3_ex4_m :std_ulogic; +signal congr_cl_ex3_ex5_m :std_ulogic; +signal congr_cl_ex3_p0_m :std_ulogic; +signal congr_cl_ex3_rel2_m :std_ulogic; +signal congr_cl_ex3_p1_m :std_ulogic; +signal congr_cl_ex3_ex4_cmp_d :std_ulogic; +signal congr_cl_ex3_ex4_cmp_q :std_ulogic; +signal congr_cl_ex3_ex5_cmp_d :std_ulogic; +signal congr_cl_ex3_ex5_cmp_q :std_ulogic; +signal congr_cl_ex3_ex6_cmp_d :std_ulogic; +signal congr_cl_ex3_ex6_cmp_q :std_ulogic; +signal congr_cl_ex3_rel2_cmp_d :std_ulogic; +signal congr_cl_ex3_rel2_cmp_q :std_ulogic; +signal congr_cl_ex3_rel_upd_cmp_d :std_ulogic; +signal congr_cl_ex3_rel_upd_cmp_q :std_ulogic; +signal congr_cl_rel1_ex4_cmp_d :std_ulogic; +signal congr_cl_rel1_ex4_cmp_q :std_ulogic; +signal congr_cl_rel1_ex5_cmp_d :std_ulogic; +signal congr_cl_rel1_ex5_cmp_q :std_ulogic; +signal congr_cl_rel1_ex6_cmp_d :std_ulogic; +signal congr_cl_rel1_ex6_cmp_q :std_ulogic; +signal congr_cl_rel1_rel2_cmp_d :std_ulogic; +signal congr_cl_rel1_rel2_cmp_q :std_ulogic; +signal congr_cl_rel1_relu_cmp_d :std_ulogic; +signal congr_cl_rel1_relu_cmp_q :std_ulogic; +signal congr_cl_rel1_rel_upd_cmp_d :std_ulogic; +signal congr_cl_rel1_rel_upd_cmp_q :std_ulogic; +signal ex3_no_lru_upd_d :std_ulogic; +signal ex3_no_lru_upd_q :std_ulogic; +signal ex3_l1hit :std_ulogic; +signal rel2_wayA_val :std_ulogic; +signal rel2_wayB_val :std_ulogic; +signal rel2_wayC_val :std_ulogic; +signal rel2_wayD_val :std_ulogic; +signal rel2_wayE_val :std_ulogic; +signal rel2_wayF_val :std_ulogic; +signal rel2_wayG_val :std_ulogic; +signal rel2_wayH_val :std_ulogic; +signal congr_cl_full :std_ulogic; +signal empty_way :std_ulogic_vector(0 to 7); +signal full_way :std_ulogic_vector(0 to 7); +signal rel_hit :std_ulogic_vector(0 to 7); +signal rel_upd_congr_cl_d :std_ulogic_vector(3 to 7); +signal rel_upd_congr_cl_q :std_ulogic_vector(3 to 7); +signal congr_cl_ex3_byp :std_ulogic_vector(0 to 4); +signal congr_cl_ex3_sel :std_ulogic_vector(1 to 4); +signal congr_cl_rel1_ex4_m :std_ulogic; +signal congr_cl_rel1_ex5_m :std_ulogic; +signal congr_cl_rel1_p0_m :std_ulogic; +signal congr_cl_rel1_rel2_m :std_ulogic; +signal congr_cl_rel1_relu_m :std_ulogic; +signal congr_cl_rel1_p1_m :std_ulogic; +signal rel_lru_early_sel :std_ulogic_vector(0 to 6); +signal rel_lru_early_sel_b :std_ulogic_vector(0 to 6); +signal congr_cl_rel1_byp :std_ulogic_vector(0 to 5); +signal congr_cl_rel1_sel :std_ulogic_vector(1 to 5); +signal rel_way_qsel_d :std_ulogic_vector(0 to 7); +signal rel_way_qsel_q :std_ulogic_vector(0 to 7); +signal rel_tag_d :std_ulogic_vector(0 to 2); +signal rel_tag_q :std_ulogic_vector(0 to 2); +signal rel4_val_d :std_ulogic; +signal rel4_val_q :std_ulogic; +signal rel4_retry_val_d :std_ulogic; +signal rel4_retry_val_q :std_ulogic; +signal rel_wayA_upd :std_ulogic; +signal rel_wayB_upd :std_ulogic; +signal rel_wayC_upd :std_ulogic; +signal rel_wayD_upd :std_ulogic; +signal rel_wayE_upd :std_ulogic; +signal rel_wayF_upd :std_ulogic; +signal rel_wayG_upd :std_ulogic; +signal rel_wayH_upd :std_ulogic; +signal rel_wayA_set :std_ulogic; +signal rel_wayB_set :std_ulogic; +signal rel_wayC_set :std_ulogic; +signal rel_wayD_set :std_ulogic; +signal rel_wayE_set :std_ulogic; +signal rel_wayF_set :std_ulogic; +signal rel_wayG_set :std_ulogic; +signal rel_wayH_set :std_ulogic; +signal rel_wayA_mid :std_ulogic; +signal rel_wayB_mid :std_ulogic; +signal rel_wayC_mid :std_ulogic; +signal rel_wayD_mid :std_ulogic; +signal rel_wayE_mid :std_ulogic; +signal rel_wayF_mid :std_ulogic; +signal rel_wayG_mid :std_ulogic; +signal rel_wayH_mid :std_ulogic; +signal rel1_wlock_b :std_ulogic_vector(0 to 7); +signal rel2_wlock_d :std_ulogic_vector(0 to 7); +signal rel2_wlock_q :std_ulogic_vector(0 to 7); +signal rel2_wayA_lock :std_ulogic; +signal rel2_wayB_lock :std_ulogic; +signal rel2_wayC_lock :std_ulogic; +signal rel2_wayD_lock :std_ulogic; +signal rel2_wayE_lock :std_ulogic; +signal rel2_wayF_lock :std_ulogic; +signal rel2_wayG_lock :std_ulogic; +signal rel2_wayH_lock :std_ulogic; +signal rel_lock_line :std_ulogic_vector(0 to 7); +signal rel_ovrd_lru :std_ulogic_vector(0 to 6); +signal rel_ovrd_wayAB :std_ulogic_vector(0 to 1); +signal rel_ovrd_wayCD :std_ulogic_vector(0 to 1); +signal rel_ovrd_wayEF :std_ulogic_vector(0 to 1); +signal rel_ovrd_wayGH :std_ulogic_vector(0 to 1); +signal rel_ovrd_wayABCD :std_ulogic_vector(0 to 1); +signal rel_ovrd_wayEFGH :std_ulogic_vector(0 to 1); +signal rel_ovrd_wayABCDEFGH :std_ulogic_vector(0 to 1); +signal ovr_lock_det :std_ulogic; +signal ovr_lock_det_wlkon :std_ulogic; +signal ovr_lock_det_wlkoff :std_ulogic; +signal wayA_not_empty :std_ulogic; +signal wayB_not_empty :std_ulogic; +signal wayC_not_empty :std_ulogic; +signal wayD_not_empty :std_ulogic; +signal wayE_not_empty :std_ulogic; +signal wayF_not_empty :std_ulogic; +signal wayg_not_empty :std_ulogic; +signal wayH_not_empty :std_ulogic; +signal rel_way_not_empty_d :std_ulogic_vector(0 to 7); +signal rel_way_not_empty_q :std_ulogic_vector(0 to 7); +signal reld_q0_chk_val :std_ulogic; +signal reld_q0_chk_way :std_ulogic_vector(0 to 7); +signal reld_q0_way_m :std_ulogic; +signal reld_q0_set :std_ulogic; +signal reld_q0_inval :std_ulogic; +signal reld_q0_val_sel :std_ulogic_vector(0 to 1); +signal reld_q0_congr_cl_d :std_ulogic_vector(3 to 7); +signal reld_q0_congr_cl_q :std_ulogic_vector(3 to 7); +signal reld_q0_way_d :std_ulogic_vector(0 to 7); +signal reld_q0_way_q :std_ulogic_vector(0 to 7); +signal reld_q0_val_d :std_ulogic; +signal reld_q0_val_q :std_ulogic; +signal reld_q0_lock_d :std_ulogic; +signal reld_q0_lock_q :std_ulogic; +signal rel_m_q0 :std_ulogic; +signal reld_q1_chk_val :std_ulogic; +signal reld_q1_chk_way :std_ulogic_vector(0 to 7); +signal reld_q1_way_m :std_ulogic; +signal reld_q1_set :std_ulogic; +signal reld_q1_inval :std_ulogic; +signal reld_q1_val_sel :std_ulogic_vector(0 to 1); +signal reld_q1_congr_cl_d :std_ulogic_vector(3 to 7); +signal reld_q1_congr_cl_q :std_ulogic_vector(3 to 7); +signal reld_q1_way_d :std_ulogic_vector(0 to 7); +signal reld_q1_way_q :std_ulogic_vector(0 to 7); +signal reld_q1_val_d :std_ulogic; +signal reld_q1_val_q :std_ulogic; +signal reld_q1_lock_d :std_ulogic; +signal reld_q1_lock_q :std_ulogic; +signal rel_m_q1 :std_ulogic; +signal reld_q2_chk_val :std_ulogic; +signal reld_q2_chk_way :std_ulogic_vector(0 to 7); +signal reld_q2_way_m :std_ulogic; +signal reld_q2_set :std_ulogic; +signal reld_q2_inval :std_ulogic; +signal reld_q2_val_sel :std_ulogic_vector(0 to 1); +signal reld_q2_congr_cl_d :std_ulogic_vector(3 to 7); +signal reld_q2_congr_cl_q :std_ulogic_vector(3 to 7); +signal reld_q2_way_d :std_ulogic_vector(0 to 7); +signal reld_q2_way_q :std_ulogic_vector(0 to 7); +signal reld_q2_val_d :std_ulogic; +signal reld_q2_val_q :std_ulogic; +signal reld_q2_lock_d :std_ulogic; +signal reld_q2_lock_q :std_ulogic; +signal rel_m_q2 :std_ulogic; +signal reld_q3_chk_val :std_ulogic; +signal reld_q3_chk_way :std_ulogic_vector(0 to 7); +signal reld_q3_way_m :std_ulogic; +signal reld_q3_set :std_ulogic; +signal reld_q3_inval :std_ulogic; +signal reld_q3_val_sel :std_ulogic_vector(0 to 1); +signal reld_q3_congr_cl_d :std_ulogic_vector(3 to 7); +signal reld_q3_congr_cl_q :std_ulogic_vector(3 to 7); +signal reld_q3_way_d :std_ulogic_vector(0 to 7); +signal reld_q3_way_q :std_ulogic_vector(0 to 7); +signal reld_q3_val_d :std_ulogic; +signal reld_q3_val_q :std_ulogic; +signal reld_q3_lock_d :std_ulogic; +signal reld_q3_lock_q :std_ulogic; +signal rel_m_q3 :std_ulogic; +signal reld_q4_chk_val :std_ulogic; +signal reld_q4_chk_way :std_ulogic_vector(0 to 7); +signal reld_q4_way_m :std_ulogic; +signal reld_q4_set :std_ulogic; +signal reld_q4_inval :std_ulogic; +signal reld_q4_val_sel :std_ulogic_vector(0 to 1); +signal reld_q4_congr_cl_d :std_ulogic_vector(3 to 7); +signal reld_q4_congr_cl_q :std_ulogic_vector(3 to 7); +signal reld_q4_way_d :std_ulogic_vector(0 to 7); +signal reld_q4_way_q :std_ulogic_vector(0 to 7); +signal reld_q4_val_d :std_ulogic; +signal reld_q4_val_q :std_ulogic; +signal reld_q4_lock_d :std_ulogic; +signal reld_q4_lock_q :std_ulogic; +signal rel_m_q4 :std_ulogic; +signal reld_q5_chk_val :std_ulogic; +signal reld_q5_chk_way :std_ulogic_vector(0 to 7); +signal reld_q5_way_m :std_ulogic; +signal reld_q5_set :std_ulogic; +signal reld_q5_inval :std_ulogic; +signal reld_q5_val_sel :std_ulogic_vector(0 to 1); +signal reld_q5_congr_cl_d :std_ulogic_vector(3 to 7); +signal reld_q5_congr_cl_q :std_ulogic_vector(3 to 7); +signal reld_q5_way_d :std_ulogic_vector(0 to 7); +signal reld_q5_way_q :std_ulogic_vector(0 to 7); +signal reld_q5_val_d :std_ulogic; +signal reld_q5_val_q :std_ulogic; +signal reld_q5_lock_d :std_ulogic; +signal reld_q5_lock_q :std_ulogic; +signal rel_m_q5 :std_ulogic; +signal reld_q6_chk_val :std_ulogic; +signal reld_q6_chk_way :std_ulogic_vector(0 to 7); +signal reld_q6_way_m :std_ulogic; +signal reld_q6_set :std_ulogic; +signal reld_q6_inval :std_ulogic; +signal reld_q6_val_sel :std_ulogic_vector(0 to 1); +signal reld_q6_congr_cl_d :std_ulogic_vector(3 to 7); +signal reld_q6_congr_cl_q :std_ulogic_vector(3 to 7); +signal reld_q6_way_d :std_ulogic_vector(0 to 7); +signal reld_q6_way_q :std_ulogic_vector(0 to 7); +signal reld_q6_val_d :std_ulogic; +signal reld_q6_val_q :std_ulogic; +signal reld_q6_lock_d :std_ulogic; +signal reld_q6_lock_q :std_ulogic; +signal rel_m_q6 :std_ulogic; +signal reld_q7_chk_val :std_ulogic; +signal reld_q7_chk_way :std_ulogic_vector(0 to 7); +signal reld_q7_way_m :std_ulogic; +signal reld_q7_set :std_ulogic; +signal reld_q7_inval :std_ulogic; +signal reld_q7_val_sel :std_ulogic_vector(0 to 1); +signal reld_q7_congr_cl_d :std_ulogic_vector(3 to 7); +signal reld_q7_congr_cl_q :std_ulogic_vector(3 to 7); +signal reld_q7_way_d :std_ulogic_vector(0 to 7); +signal reld_q7_way_q :std_ulogic_vector(0 to 7); +signal reld_q7_val_d :std_ulogic; +signal reld_q7_val_q :std_ulogic; +signal reld_q7_lock_d :std_ulogic; +signal reld_q7_lock_q :std_ulogic; +signal rel_m_q7 :std_ulogic; +signal reld_match :std_ulogic_vector(0 to 7); +signal reld_q_sel_d :std_ulogic_vector(0 to 7); +signal reld_q_sel_q :std_ulogic_vector(0 to 7); +signal rel_val_qsel_d :std_ulogic; +signal rel_val_qsel_q :std_ulogic; +signal spr_rmt_table :std_ulogic_vector(0 to 31); +signal rel_class_id :std_ulogic_vector(0 to 1); +signal rel2_class_id_d :std_ulogic_vector(0 to 1); +signal rel2_class_id_q :std_ulogic_vector(0 to 1); +signal rel_m_q_way_b :std_ulogic_vector(0 to 7); +signal rel_m_q_way_d :std_ulogic_vector(0 to 7); +signal rel_m_q_way_q :std_ulogic_vector(0 to 7); +signal rel_m_q_lock_way :std_ulogic_vector(0 to 7); +signal rel2_lock_en_d :std_ulogic; +signal rel2_lock_en_q :std_ulogic; +signal xucr0_clo_d :std_ulogic; +signal xucr0_clo_q :std_ulogic; +signal rel_way_dwen :std_ulogic_vector(0 to 7); +signal rel24_way_dwen_stg_d :std_ulogic_vector(0 to 7); +signal rel24_way_dwen_stg_q :std_ulogic_vector(0 to 7); +signal rel_up_way_addr_d :std_ulogic_vector(0 to 2); +signal rel_up_way_addr_q :std_ulogic_vector(0 to 2); +signal rel_dcarr_addr_en_d :std_ulogic; +signal rel_dcarr_addr_en_q :std_ulogic; +signal rel_dcarr_val_upd_d :std_ulogic; +signal rel_dcarr_val_upd_q :std_ulogic; +signal rel_lru_late_sel :std_ulogic; +signal rel_lru_late_stg_pri :std_ulogic_vector(0 to 6); +signal rel_lru_late_stg_arr :std_ulogic_vector(0 to 6); +signal lru_late_sel :std_ulogic; +signal lru_late_stg_pri :std_ulogic_vector(0 to 6); +signal lru_late_stg_arr :std_ulogic_vector(0 to 6); +signal lru_early_sel :std_ulogic_vector(0 to 6); +signal lru_early_sel_b :std_ulogic_vector(0 to 6); +signal rel_hit_lru_upd :std_ulogic_vector(0 to 6); +signal ldst_hit_vec_sel :std_ulogic; +signal ldst_hit_lru_upd :std_ulogic_vector(0 to 6); +signal rel_wlock_rmt :std_ulogic_vector(0 to 7); +signal congr_cl_act_d :std_ulogic; +signal congr_cl_act_q :std_ulogic; +signal rel2_mid_val_d :std_ulogic; +signal rel2_mid_val_q :std_ulogic; +signal relq_m_way_val :std_ulogic_vector(0 to 7); +signal rel_m_q_upd :std_ulogic; +signal rel_m_q_upd_way :std_ulogic_vector(0 to 7); +signal rel_m_q_upd_lock_way :std_ulogic_vector(0 to 7); +signal reld_q_early_sel :std_ulogic_vector(0 to 7); +signal rel_way_early_qsel :std_ulogic_vector(0 to 7); +signal rel_way_early_qsel_d :std_ulogic_vector(0 to 7); +signal rel_way_early_qsel_q :std_ulogic_vector(0 to 7); +signal rel_val_early_qsel :std_ulogic; +signal rel_val_early_qsel_d :std_ulogic; +signal rel_val_early_qsel_q :std_ulogic; +signal reld_q_early_byp :std_ulogic; +signal reld_way_early_byp :std_ulogic_vector(0 to 7); +signal reld_q_val :std_ulogic_vector(0 to 7); +signal ex4_fxubyp_val_d :std_ulogic; +signal ex4_fxubyp_val_q :std_ulogic; +signal ex4_relbyp_val_d :std_ulogic; +signal ex4_relbyp_val_q :std_ulogic; +signal ex4_lru_byp_sel :std_ulogic_vector(0 to 1); +signal rel2_fxubyp_val_d :std_ulogic; +signal rel2_fxubyp_val_q :std_ulogic; +signal rel2_relbyp_val_d :std_ulogic; +signal rel2_relbyp_val_q :std_ulogic; +signal rel2_lru_byp_sel :std_ulogic_vector(0 to 1); +signal tiup :std_ulogic; +signal siv :std_ulogic_vector(0 to scan_right); +signal sov :std_ulogic_vector(0 to scan_right); + BEGIN + +tiup <= '1'; +rel2_val_d <= rel1_val; +rel2_mid_val_d <= rel_mid_val; +rel4_retry_val_d <= rel_retry_val; +rel4_val_d <= rel3_val; +rel_tag_d <= rel_st_tag; +rel_class_id <= rel1_classid; +rel2_class_id_d <= rel_class_id; +rel2_lock_en_d <= rel_lock_en; +rel2_wayA_val <= rel_way_val_a; +rel2_wayB_val <= rel_way_val_b; +rel2_wayC_val <= rel_way_val_c; +rel2_wayD_val <= rel_way_val_d; +rel2_wayE_val <= rel_way_val_e; +rel2_wayF_val <= rel_way_val_f; +rel2_wayG_val <= rel_way_val_g; +rel2_wayH_val <= rel_way_val_h; +rel2_wayA_lock <= rel_way_lock_a; +rel2_wayB_lock <= rel_way_lock_b; +rel2_wayC_lock <= rel_way_lock_c; +rel2_wayD_lock <= rel_way_lock_d; +rel2_wayE_lock <= rel_way_lock_e; +rel2_wayF_lock <= rel_way_lock_f; +rel2_wayG_lock <= rel_way_lock_g; +rel2_wayH_lock <= rel_way_lock_h; +spr_rmt_table <= spr_xucr2_rmt; +ldst_wayA_hit <= ex4_way_a_hit; +ldst_wayB_hit <= ex4_way_b_hit; +ldst_wayC_hit <= ex4_way_c_hit; +ldst_wayD_hit <= ex4_way_d_hit; +ldst_wayE_hit <= ex4_way_e_hit; +ldst_wayF_hit <= ex4_way_f_hit; +ldst_wayG_hit <= ex4_way_g_hit; +ldst_wayH_hit <= ex4_way_h_hit; +ex3_l1hit <= ex3_hit; +ex3_no_lru_upd_d <= ex2_no_lru_upd; +ex3_flush <= ex3_stg_flush; +ex4_flush <= ex4_stg_flush; +ex5_flush <= ex5_stg_flush; +ex1_congr_cl <= ex1_p_addr; +cl64size : if (cl_size=6) generate +begin + rel_early_congr_cl(3 TO 6) <= rel_addr_early(64-(dc_size-3) to 63-cl_size-1); +rel_early_congr_cl(7) <= rel_addr_early(63-cl_size) or spr_xucr0_cls; +end generate cl64size; +cl32size : if (cl_size=5) generate +begin + rel_early_congr_cl(3 TO 5) <= rel_addr_early(64-(dc_size-3) to 63-cl_size-2); +rel_early_congr_cl(6) <= rel_addr_early(63-cl_size-1) or spr_xucr0_cls; +rel_early_congr_cl(7) <= rel_addr_early(63-cl_size); +end generate cl32size; +rel_congr_cl_d <= rel_early_congr_cl; +ex2_congr_cl_d <= ex1_congr_cl; +ex3_congr_cl_d <= ex2_congr_cl_q; +ex4_congr_cl_d <= ex3_congr_cl_q; +ex5_congr_cl_d <= ex4_congr_cl_q; +ex6_congr_cl_d <= ex5_congr_cl_q; +with rel_congr_cl_q select + rel_congr_cl_lru <= + congr_cl0_lru_q when "00000", + congr_cl1_lru_q when "00001", + congr_cl2_lru_q when "00010", + congr_cl3_lru_q when "00011", + congr_cl4_lru_q when "00100", + congr_cl5_lru_q when "00101", + congr_cl6_lru_q when "00110", + congr_cl7_lru_q when "00111", + congr_cl8_lru_q when "01000", + congr_cl9_lru_q when "01001", + congr_cl10_lru_q when "01010", + congr_cl11_lru_q when "01011", + congr_cl12_lru_q when "01100", + congr_cl13_lru_q when "01101", + congr_cl14_lru_q when "01110", + congr_cl15_lru_q when "01111", + congr_cl16_lru_q when "10000", + congr_cl17_lru_q when "10001", + congr_cl18_lru_q when "10010", + congr_cl19_lru_q when "10011", + congr_cl20_lru_q when "10100", + congr_cl21_lru_q when "10101", + congr_cl22_lru_q when "10110", + congr_cl23_lru_q when "10111", + congr_cl24_lru_q when "11000", + congr_cl25_lru_q when "11001", + congr_cl26_lru_q when "11010", + congr_cl27_lru_q when "11011", + congr_cl28_lru_q when "11100", + congr_cl29_lru_q when "11101", + congr_cl30_lru_q when "11110", + congr_cl31_lru_q when others; +p1_arr_lru_rd <= rel_congr_cl_lru; +rel_m_q_upd <= (rel_congr_cl_q = rel_congr_cl_stg_q) and rel2_val_q; +rel_m_q_upd_way <= gate(rel_hit_vec, rel_m_q_upd); +rel_m_q_upd_lock_way <= gate(rel_hit_vec, (rel_m_q_upd and rel2_lock_en_q)); +rel_m_q0 <= (rel_congr_cl_q = reld_q0_congr_cl_q) and reld_q0_val_q; +rel_m_q1 <= (rel_congr_cl_q = reld_q1_congr_cl_q) and reld_q1_val_q; +rel_m_q2 <= (rel_congr_cl_q = reld_q2_congr_cl_q) and reld_q2_val_q; +rel_m_q3 <= (rel_congr_cl_q = reld_q3_congr_cl_q) and reld_q3_val_q; +rel_m_q4 <= (rel_congr_cl_q = reld_q4_congr_cl_q) and reld_q4_val_q; +rel_m_q5 <= (rel_congr_cl_q = reld_q5_congr_cl_q) and reld_q5_val_q; +rel_m_q6 <= (rel_congr_cl_q = reld_q6_congr_cl_q) and reld_q6_val_q; +rel_m_q7 <= (rel_congr_cl_q = reld_q7_congr_cl_q) and reld_q7_val_q; +relq_m_way_val <= gate(reld_q0_way_q, rel_m_q0) or + gate(reld_q1_way_q, rel_m_q1) or + gate(reld_q2_way_q, rel_m_q2) or + gate(reld_q3_way_q, rel_m_q3) or + gate(reld_q4_way_q, rel_m_q4) or + gate(reld_q5_way_q, rel_m_q5) or + gate(reld_q6_way_q, rel_m_q6) or + gate(reld_q7_way_q, rel_m_q7); +relMQWayB: rel_m_q_way_b <= not (relq_m_way_val or rel_m_q_upd_way); +rel_m_q_way_d <= not rel_m_q_way_b; +rel_m_q_lock_way <= gate(gate(reld_q0_way_q, reld_q0_lock_q), rel_m_q0) or + gate(gate(reld_q1_way_q, reld_q1_lock_q), rel_m_q1) or + gate(gate(reld_q2_way_q, reld_q2_lock_q), rel_m_q2) or + gate(gate(reld_q3_way_q, reld_q3_lock_q), rel_m_q3) or + gate(gate(reld_q4_way_q, reld_q4_lock_q), rel_m_q4) or + gate(gate(reld_q5_way_q, reld_q5_lock_q), rel_m_q5) or + gate(gate(reld_q6_way_q, reld_q6_lock_q), rel_m_q6) or + gate(gate(reld_q7_way_q, reld_q7_lock_q), rel_m_q7) or + rel_wlock_rmt; +congr_cl_rel1_ex4_cmp_d <= (rel_early_congr_cl = ex3_congr_cl_q); +congr_cl_rel1_ex5_cmp_d <= (rel_early_congr_cl = ex4_congr_cl_q); +congr_cl_rel1_ex6_cmp_d <= (rel_early_congr_cl = ex5_congr_cl_q); +congr_cl_rel1_rel2_cmp_d <= (rel_early_congr_cl = rel_congr_cl_q); +congr_cl_rel1_relu_cmp_d <= (rel_early_congr_cl = rel_congr_cl_stg_q); +congr_cl_rel1_rel_upd_cmp_d <= (rel_early_congr_cl = relu_congr_cl_q); +congr_cl_rel1_ex4_m <= congr_cl_rel1_ex4_cmp_q and ex4_c_acc; +congr_cl_rel1_ex5_m <= congr_cl_rel1_ex5_cmp_q and ex5_c_acc_q; +congr_cl_rel1_rel2_m <= congr_cl_rel1_rel2_cmp_q and rel2_val_q and not ovr_lock_det; +congr_cl_rel1_relu_m <= congr_cl_rel1_relu_cmp_q and relu_val_wen_q; +congr_cl_rel1_p0_m <= congr_cl_rel1_ex6_cmp_q and ex6_c_acc_val_q; +congr_cl_rel1_p1_m <= congr_cl_rel1_rel_upd_cmp_q and rel_val_wen_q; +congr_cl_rel1_byp(0) <= congr_cl_rel1_rel2_m; +congr_cl_rel1_byp(1) <= congr_cl_rel1_ex4_m; +congr_cl_rel1_byp(2) <= congr_cl_rel1_relu_m; +congr_cl_rel1_byp(3) <= congr_cl_rel1_ex5_m; +congr_cl_rel1_byp(4) <= congr_cl_rel1_p1_m; +congr_cl_rel1_byp(5) <= congr_cl_rel1_p0_m; +rel2_fxubyp_val_d <= congr_cl_rel1_byp(1) or congr_cl_rel1_byp(3) or congr_cl_rel1_byp(5); +rel2_relbyp_val_d <= congr_cl_rel1_byp(0) or congr_cl_rel1_byp(2) or congr_cl_rel1_byp(4); +rel2_lru_byp_sel <= rel2_fxubyp_val_q & rel2_relbyp_val_q; +congr_cl_rel1_sel(1) <= congr_cl_rel1_byp(1); +congr_cl_rel1_sel(2) <= congr_cl_rel1_byp(2) and not congr_cl_rel1_byp(1); +congr_cl_rel1_sel(3) <= congr_cl_rel1_byp(3) and not or_reduce(congr_cl_rel1_byp(1 to 2)); +congr_cl_rel1_sel(4) <= congr_cl_rel1_byp(4) and not or_reduce(congr_cl_rel1_byp(1 to 3)); +congr_cl_rel1_sel(5) <= congr_cl_rel1_byp(5) and not or_reduce(congr_cl_rel1_byp(1 to 4)); +rel_lru_late_sel <= or_reduce(congr_cl_rel1_byp(1 to 5)); +rel_lru_late_stg_pri <= gate(lru_upd, congr_cl_rel1_sel(1)) or + gate(relu_lru_upd_q, congr_cl_rel1_sel(2)) or + gate(ex5_lru_upd_q, congr_cl_rel1_sel(3)) or + gate(rel_lru_val_q, congr_cl_rel1_sel(4)) or + gate(ex6_lru_upd_q, congr_cl_rel1_sel(5)); +rel_lru_late_stg_arr <= gate(p1_arr_lru_rd, not rel_lru_late_sel) or rel_lru_late_stg_pri; +rel_lru_early_sel <= (others=>congr_cl_rel1_byp(0)); +rel_lru_early_sel_b <= (others=>(not congr_cl_rel1_byp(0))); +rel_op_lru <= not rel_congr_cl_lru_b_q; +rel_congr_cl_stg_d <= rel_congr_cl_q; +relu_congr_cl_d <= rel_congr_cl_stg_q; +rel_upd_congr_cl_d <= relu_congr_cl_q; +relu_val_wen_d <= rel2_val_q and not ovr_lock_det; +rel_val_wen_d <= relu_val_wen_q; +rel_dcarr_addr_en_d <= rel2_val_q or (rel4_val_q and not rel4_retry_val_q) or rel2_mid_val_q; +with rel_class_id select + rel_wlock_rmt <= not spr_rmt_table(0 to 7) when "11", + not spr_rmt_table(8 to 15) when "10", + not spr_rmt_table(16 to 23) when "01", + not spr_rmt_table(24 to 31) when others; +rel1WlockB: rel1_wlock_b <= not (rel_m_q_upd_lock_way or rel_m_q_lock_way); +rel2_wlock_d <= not rel1_wlock_b; +rel_lock_line(0) <= rel2_wayA_lock or rel2_wlock_q(0); +rel_lock_line(1) <= rel2_wayB_lock or rel2_wlock_q(1); +rel_lock_line(2) <= rel2_wayC_lock or rel2_wlock_q(2); +rel_lock_line(3) <= rel2_wayD_lock or rel2_wlock_q(3); +rel_lock_line(4) <= rel2_wayE_lock or rel2_wlock_q(4); +rel_lock_line(5) <= rel2_wayF_lock or rel2_wlock_q(5); +rel_lock_line(6) <= rel2_wayG_lock or rel2_wlock_q(6); +rel_lock_line(7) <= rel2_wayH_lock or rel2_wlock_q(7); +ovr_lock_det <= rel_lock_line(0) and rel_lock_line(1) and rel_lock_line(2) and rel_lock_line(3) and + rel_lock_line(4) and rel_lock_line(5) and rel_lock_line(6) and rel_lock_line(7); +ovr_lock_det_wlkon <= ovr_lock_det and rel2_val_q; +ovr_lock_det_wlkoff <= ovr_lock_det and rel2_lock_en_q and rel2_val_q; +with spr_xucr0_wlck select + xucr0_clo_d <= ovr_lock_det_wlkon when '1', + ovr_lock_det_wlkoff when others; +rel_ovrd_wayABCDEFGH <= (rel_lock_line(0) and rel_lock_line(1) and rel_lock_line(2) and rel_lock_line(3)) & + (rel_lock_line(4) and rel_lock_line(5) and rel_lock_line(6) and rel_lock_line(7)); +rel_ovrd_lru(0) <= (rel_op_lru(0) and not rel_ovrd_wayABCDEFGH(1)) or rel_ovrd_wayABCDEFGH(0); +rel_ovrd_wayABCD <= (rel_lock_line(0) and rel_lock_line(1)) & (rel_lock_line(2) and rel_lock_line(3)); +rel_ovrd_lru(1) <= (rel_op_lru(1) and not rel_ovrd_wayABCD(1)) or rel_ovrd_wayABCD(0); +rel_ovrd_wayEFGH <= (rel_lock_line(4) and rel_lock_line(5)) & (rel_lock_line(6) and rel_lock_line(7)); +rel_ovrd_lru(2) <= (rel_op_lru(2) and not rel_ovrd_wayEFGH(1)) or rel_ovrd_wayEFGH(0); +rel_ovrd_wayAB <= rel_lock_line(0 to 1); +rel_ovrd_lru(3) <= (rel_op_lru(3) and not rel_ovrd_wayAB(1)) or rel_ovrd_wayAB(0); +rel_ovrd_wayCD <= rel_lock_line(2 to 3); +rel_ovrd_lru(4) <= (rel_op_lru(4) and not rel_ovrd_wayCD(1)) or rel_ovrd_wayCD(0); +rel_ovrd_wayEF <= rel_lock_line(4 to 5); +rel_ovrd_lru(5) <= (rel_op_lru(5) and not rel_ovrd_wayEF(1)) or rel_ovrd_wayEF(0); +rel_ovrd_wayGH <= rel_lock_line(6 to 7); +rel_ovrd_lru(6) <= (rel_op_lru(6) and not rel_ovrd_wayGH(1)) or rel_ovrd_wayGH(0); +full_way(0) <= not rel_ovrd_lru(0) and not rel_ovrd_lru(1) and not rel_ovrd_lru(3); +full_way(1) <= not rel_ovrd_lru(0) and not rel_ovrd_lru(1) and rel_ovrd_lru(3); +full_way(2) <= not rel_ovrd_lru(0) and rel_ovrd_lru(1) and not rel_ovrd_lru(4); +full_way(3) <= not rel_ovrd_lru(0) and rel_ovrd_lru(1) and rel_ovrd_lru(4); +full_way(4) <= rel_ovrd_lru(0) and not rel_ovrd_lru(2) and not rel_ovrd_lru(5); +full_way(5) <= rel_ovrd_lru(0) and not rel_ovrd_lru(2) and rel_ovrd_lru(5); +full_way(6) <= rel_ovrd_lru(0) and rel_ovrd_lru(2) and not rel_ovrd_lru(6); +full_way(7) <= rel_ovrd_lru(0) and rel_ovrd_lru(2) and rel_ovrd_lru(6); +wayA_not_empty <= rel2_wayA_val or rel2_wlock_q(0) or rel_m_q_way_q(0); +wayB_not_empty <= rel2_wayB_val or rel2_wlock_q(1) or rel_m_q_way_q(1); +wayC_not_empty <= rel2_wayC_val or rel2_wlock_q(2) or rel_m_q_way_q(2); +wayD_not_empty <= rel2_wayD_val or rel2_wlock_q(3) or rel_m_q_way_q(3); +wayE_not_empty <= rel2_wayE_val or rel2_wlock_q(4) or rel_m_q_way_q(4); +wayF_not_empty <= rel2_wayF_val or rel2_wlock_q(5) or rel_m_q_way_q(5); +wayG_not_empty <= rel2_wayG_val or rel2_wlock_q(6) or rel_m_q_way_q(6); +wayH_not_empty <= rel2_wayH_val or rel2_wlock_q(7) or rel_m_q_way_q(7); +rel_way_not_empty_d <= wayA_not_empty & wayB_not_empty & wayC_not_empty & wayD_not_empty & + wayE_not_empty & wayF_not_empty & wayG_not_empty & wayH_not_empty; +congr_cl_full <= wayA_not_empty and wayB_not_empty and wayC_not_empty and wayD_not_empty and + wayE_not_empty and wayF_not_empty and wayG_not_empty and wayH_not_empty; +empty_way(0) <= not wayA_not_empty; +empty_way(1) <= ( wayA_not_empty and not wayB_not_empty); +empty_way(2) <= ( wayA_not_empty and wayB_not_empty and not wayC_not_empty); +empty_way(3) <= ( wayA_not_empty and wayB_not_empty and wayC_not_empty and not wayD_not_empty); +empty_way(4) <= ( wayA_not_empty and wayB_not_empty and wayC_not_empty and wayD_not_empty and + not wayE_not_empty); +empty_way(5) <= ( wayA_not_empty and wayB_not_empty and wayC_not_empty and wayD_not_empty and + wayE_not_empty and not wayF_not_empty); +empty_way(6) <= ( wayA_not_empty and wayB_not_empty and wayC_not_empty and wayD_not_empty and + wayE_not_empty and wayF_not_empty and not wayG_not_empty); +empty_way(7) <= ( wayA_not_empty and wayB_not_empty and wayC_not_empty and wayD_not_empty and + wayE_not_empty and wayF_not_empty and wayG_not_empty); +rel_hit <= gate(empty_way, not congr_cl_full) or gate(full_way, congr_cl_full); +rel_wayA_clr <= rel_hit(0) and rel2_val_q and not ovr_lock_det; +rel_wayB_clr <= rel_hit(1) and rel2_val_q and not ovr_lock_det; +rel_wayC_clr <= rel_hit(2) and rel2_val_q and not ovr_lock_det; +rel_wayD_clr <= rel_hit(3) and rel2_val_q and not ovr_lock_det; +rel_wayE_clr <= rel_hit(4) and rel2_val_q and not ovr_lock_det; +rel_wayF_clr <= rel_hit(5) and rel2_val_q and not ovr_lock_det; +rel_wayG_clr <= rel_hit(6) and rel2_val_q and not ovr_lock_det; +rel_wayH_clr <= rel_hit(7) and rel2_val_q and not ovr_lock_det; +rel_hit_vec <= rel_wayA_clr & rel_wayB_clr & rel_wayC_clr & rel_wayD_clr & + rel_wayE_clr & rel_wayF_clr & rel_wayG_clr & rel_wayH_clr; +rel_hit_wayA_upd <= "11" & rel_ovrd_lru(2) & "1" & rel_ovrd_lru(4 to 6); +rel_hit_wayB_upd <= "11" & rel_ovrd_lru(2) & "0" & rel_ovrd_lru(4 to 6); +rel_hit_wayC_upd <= "10" & rel_ovrd_lru(2 to 3) & "1" & rel_ovrd_lru(5 to 6); +rel_hit_wayD_upd <= "10" & rel_ovrd_lru(2 to 3) & "0" & rel_ovrd_lru(5 to 6); +rel_hit_wayE_upd <= "0" & rel_ovrd_lru(1) & "1" & rel_ovrd_lru(3 to 4) & "1" & rel_ovrd_lru(6); +rel_hit_wayF_upd <= "0" & rel_ovrd_lru(1) & "1" & rel_ovrd_lru(3 to 4) & "0" & rel_ovrd_lru(6); +rel_hit_wayG_upd <= "0" & rel_ovrd_lru(1) & "0" & rel_ovrd_lru(3 to 5) & "1"; +rel_hit_wayh_upd <= "0" & rel_ovrd_lru(1) & "0" & rel_ovrd_lru(3 to 5) & "0"; +rel_hit_lru_upd <= gate(rel_hit_wayA_upd, rel_hit_vec(0)) or gate(rel_hit_wayB_upd, rel_hit_vec(1)) or + gate(rel_hit_wayC_upd, rel_hit_vec(2)) or gate(rel_hit_wayD_upd, rel_hit_vec(3)) or + gate(rel_hit_wayE_upd, rel_hit_vec(4)) or gate(rel_hit_wayF_upd, rel_hit_vec(5)) or + gate(rel_hit_wayG_upd, rel_hit_vec(6)) or gate(rel_hit_wayH_upd, rel_hit_vec(7)); +relu_lru_upd_d <= rel_hit_lru_upd; +rel_lru_val_d <= relu_lru_upd_q; +reld_q0_chk_val <= (reld_q0_congr_cl_q = rel_congr_cl_stg_q) and reld_q0_val_q and rel2_val_q and not ovr_lock_det; +reld_q0_chk_way <= gate(reld_q0_way_q, reld_q0_chk_val); +reld_q0_way_m <= or_reduce((reld_q0_chk_way and rel_hit)); +reld_match(0) <= reld_q0_way_m; +reld_q0_set <= rel2_val_q and (rel_tag_q = tconv(0,3)); +reld_q0_inval <= (rel4_val_q and (not rel4_recirc_val or rel4_ecc_err) and reld_q_sel_q(0)) or reld_match(0); +reld_q0_val_sel <= reld_q0_set & reld_q0_inval; +with reld_q0_set select + reld_q0_congr_cl_d <= rel_congr_cl_stg_q when '1', + reld_q0_congr_cl_q when others; +with reld_q0_set select + reld_q0_way_d <= rel_hit_vec when '1', + reld_q0_way_q when others; +with reld_q0_val_sel select + reld_q0_val_d <= '0' when "01", + reld_q0_val_q when "00", + '1' when others; +reld_q_val(0) <= reld_q0_val_q; +with reld_q0_val_sel select + reld_q0_lock_d <= '0' when "01", + reld_q0_lock_q when "00", + rel2_lock_en_q when others; +reld_q_early_sel(0) <= (rel_st_tag_early = tconv(0,3)); +reld_q_sel_d(0) <= (rel_st_tag = tconv(0,3)); +reld_q1_chk_val <= (reld_q1_congr_cl_q = rel_congr_cl_stg_q) and reld_q1_val_q and rel2_val_q and not ovr_lock_det; +reld_q1_chk_way <= gate(reld_q1_way_q, reld_q1_chk_val); +reld_q1_way_m <= or_reduce((reld_q1_chk_way and rel_hit)); +reld_match(1) <= reld_q1_way_m; +reld_q1_set <= rel2_val_q and (rel_tag_q = tconv(1,3)); +reld_q1_inval <= (rel4_val_q and (not rel4_recirc_val or rel4_ecc_err) and reld_q_sel_q(1)) or reld_match(1); +reld_q1_val_sel <= reld_q1_set & reld_q1_inval; +with reld_q1_set select + reld_q1_congr_cl_d <= rel_congr_cl_stg_q when '1', + reld_q1_congr_cl_q when others; +with reld_q1_set select + reld_q1_way_d <= rel_hit_vec when '1', + reld_q1_way_q when others; +with reld_q1_val_sel select + reld_q1_val_d <= '0' when "01", + reld_q1_val_q when "00", + '1' when others; +reld_q_val(1) <= reld_q1_val_q; +with reld_q1_val_sel select + reld_q1_lock_d <= '0' when "01", + reld_q1_lock_q when "00", + rel2_lock_en_q when others; +reld_q_early_sel(1) <= (rel_st_tag_early = tconv(1,3)); +reld_q_sel_d(1) <= (rel_st_tag = tconv(1,3)); +reld_q2_chk_val <= (reld_q2_congr_cl_q = rel_congr_cl_stg_q) and reld_q2_val_q and rel2_val_q and not ovr_lock_det; +reld_q2_chk_way <= gate(reld_q2_way_q, reld_q2_chk_val); +reld_q2_way_m <= or_reduce((reld_q2_chk_way and rel_hit)); +reld_match(2) <= reld_q2_way_m; +reld_q2_set <= rel2_val_q and (rel_tag_q = tconv(2,3)); +reld_q2_inval <= (rel4_val_q and (not rel4_recirc_val or rel4_ecc_err) and reld_q_sel_q(2)) or reld_match(2); +reld_q2_val_sel <= reld_q2_set & reld_q2_inval; +with reld_q2_set select + reld_q2_congr_cl_d <= rel_congr_cl_stg_q when '1', + reld_q2_congr_cl_q when others; +with reld_q2_set select + reld_q2_way_d <= rel_hit_vec when '1', + reld_q2_way_q when others; +with reld_q2_val_sel select + reld_q2_val_d <= '0' when "01", + reld_q2_val_q when "00", + '1' when others; +reld_q_val(2) <= reld_q2_val_q; +with reld_q2_val_sel select + reld_q2_lock_d <= '0' when "01", + reld_q2_lock_q when "00", + rel2_lock_en_q when others; +reld_q_early_sel(2) <= (rel_st_tag_early = tconv(2,3)); +reld_q_sel_d(2) <= (rel_st_tag = tconv(2,3)); +reld_q3_chk_val <= (reld_q3_congr_cl_q = rel_congr_cl_stg_q) and reld_q3_val_q and rel2_val_q and not ovr_lock_det; +reld_q3_chk_way <= gate(reld_q3_way_q, reld_q3_chk_val); +reld_q3_way_m <= or_reduce((reld_q3_chk_way and rel_hit)); +reld_match(3) <= reld_q3_way_m; +reld_q3_set <= rel2_val_q and (rel_tag_q = tconv(3,3)); +reld_q3_inval <= (rel4_val_q and (not rel4_recirc_val or rel4_ecc_err) and reld_q_sel_q(3)) or reld_match(3); +reld_q3_val_sel <= reld_q3_set & reld_q3_inval; +with reld_q3_set select + reld_q3_congr_cl_d <= rel_congr_cl_stg_q when '1', + reld_q3_congr_cl_q when others; +with reld_q3_set select + reld_q3_way_d <= rel_hit_vec when '1', + reld_q3_way_q when others; +with reld_q3_val_sel select + reld_q3_val_d <= '0' when "01", + reld_q3_val_q when "00", + '1' when others; +reld_q_val(3) <= reld_q3_val_q; +with reld_q3_val_sel select + reld_q3_lock_d <= '0' when "01", + reld_q3_lock_q when "00", + rel2_lock_en_q when others; +reld_q_early_sel(3) <= (rel_st_tag_early = tconv(3,3)); +reld_q_sel_d(3) <= (rel_st_tag = tconv(3,3)); +reld_q4_chk_val <= (reld_q4_congr_cl_q = rel_congr_cl_stg_q) and reld_q4_val_q and rel2_val_q and not ovr_lock_det; +reld_q4_chk_way <= gate(reld_q4_way_q, reld_q4_chk_val); +reld_q4_way_m <= or_reduce((reld_q4_chk_way and rel_hit)); +reld_match(4) <= reld_q4_way_m; +reld_q4_set <= rel2_val_q and (rel_tag_q = tconv(4,3)); +reld_q4_inval <= (rel4_val_q and (not rel4_recirc_val or rel4_ecc_err) and reld_q_sel_q(4)) or reld_match(4); +reld_q4_val_sel <= reld_q4_set & reld_q4_inval; +with reld_q4_set select + reld_q4_congr_cl_d <= rel_congr_cl_stg_q when '1', + reld_q4_congr_cl_q when others; +with reld_q4_set select + reld_q4_way_d <= rel_hit_vec when '1', + reld_q4_way_q when others; +with reld_q4_val_sel select + reld_q4_val_d <= '0' when "01", + reld_q4_val_q when "00", + '1' when others; +reld_q_val(4) <= reld_q4_val_q; +with reld_q4_val_sel select + reld_q4_lock_d <= '0' when "01", + reld_q4_lock_q when "00", + rel2_lock_en_q when others; +reld_q_early_sel(4) <= (rel_st_tag_early = tconv(4,3)); +reld_q_sel_d(4) <= (rel_st_tag = tconv(4,3)); +reld_q5_chk_val <= (reld_q5_congr_cl_q = rel_congr_cl_stg_q) and reld_q5_val_q and rel2_val_q and not ovr_lock_det; +reld_q5_chk_way <= gate(reld_q5_way_q, reld_q5_chk_val); +reld_q5_way_m <= or_reduce((reld_q5_chk_way and rel_hit)); +reld_match(5) <= reld_q5_way_m; +reld_q5_set <= rel2_val_q and (rel_tag_q = tconv(5,3)); +reld_q5_inval <= (rel4_val_q and (not rel4_recirc_val or rel4_ecc_err) and reld_q_sel_q(5)) or reld_match(5); +reld_q5_val_sel <= reld_q5_set & reld_q5_inval; +with reld_q5_set select + reld_q5_congr_cl_d <= rel_congr_cl_stg_q when '1', + reld_q5_congr_cl_q when others; +with reld_q5_set select + reld_q5_way_d <= rel_hit_vec when '1', + reld_q5_way_q when others; +with reld_q5_val_sel select + reld_q5_val_d <= '0' when "01", + reld_q5_val_q when "00", + '1' when others; +reld_q_val(5) <= reld_q5_val_q; +with reld_q5_val_sel select + reld_q5_lock_d <= '0' when "01", + reld_q5_lock_q when "00", + rel2_lock_en_q when others; +reld_q_early_sel(5) <= (rel_st_tag_early = tconv(5,3)); +reld_q_sel_d(5) <= (rel_st_tag = tconv(5,3)); +reld_q6_chk_val <= (reld_q6_congr_cl_q = rel_congr_cl_stg_q) and reld_q6_val_q and rel2_val_q and not ovr_lock_det; +reld_q6_chk_way <= gate(reld_q6_way_q, reld_q6_chk_val); +reld_q6_way_m <= or_reduce((reld_q6_chk_way and rel_hit)); +reld_match(6) <= reld_q6_way_m; +reld_q6_set <= rel2_val_q and (rel_tag_q = tconv(6,3)); +reld_q6_inval <= (rel4_val_q and (not rel4_recirc_val or rel4_ecc_err) and reld_q_sel_q(6)) or reld_match(6); +reld_q6_val_sel <= reld_q6_set & reld_q6_inval; +with reld_q6_set select + reld_q6_congr_cl_d <= rel_congr_cl_stg_q when '1', + reld_q6_congr_cl_q when others; +with reld_q6_set select + reld_q6_way_d <= rel_hit_vec when '1', + reld_q6_way_q when others; +with reld_q6_val_sel select + reld_q6_val_d <= '0' when "01", + reld_q6_val_q when "00", + '1' when others; +reld_q_val(6) <= reld_q6_val_q; +with reld_q6_val_sel select + reld_q6_lock_d <= '0' when "01", + reld_q6_lock_q when "00", + rel2_lock_en_q when others; +reld_q_early_sel(6) <= (rel_st_tag_early = tconv(6,3)); +reld_q_sel_d(6) <= (rel_st_tag = tconv(6,3)); +reld_q7_chk_val <= (reld_q7_congr_cl_q = rel_congr_cl_stg_q) and reld_q7_val_q and rel2_val_q and not ovr_lock_det; +reld_q7_chk_way <= gate(reld_q7_way_q, reld_q7_chk_val); +reld_q7_way_m <= or_reduce((reld_q7_chk_way and rel_hit)); +reld_match(7) <= reld_q7_way_m; +reld_q7_set <= rel2_val_q and (rel_tag_q = tconv(7,3)); +reld_q7_inval <= (rel4_val_q and (not rel4_recirc_val or rel4_ecc_err) and reld_q_sel_q(7)) or reld_match(7); +reld_q7_val_sel <= reld_q7_set & reld_q7_inval; +with reld_q7_set select + reld_q7_congr_cl_d <= rel_congr_cl_stg_q when '1', + reld_q7_congr_cl_q when others; +with reld_q7_set select + reld_q7_way_d <= rel_hit_vec when '1', + reld_q7_way_q when others; +with reld_q7_val_sel select + reld_q7_val_d <= '0' when "01", + reld_q7_val_q when "00", + '1' when others; +reld_q_val(7) <= reld_q7_val_q; +with reld_q7_val_sel select + reld_q7_lock_d <= '0' when "01", + reld_q7_lock_q when "00", + rel2_lock_en_q when others; +reld_q_early_sel(7) <= (rel_st_tag_early = tconv(7,3)); +reld_q_sel_d(7) <= (rel_st_tag = tconv(7,3)); +rel_way_early_qsel <= gate(reld_q0_way_q, reld_q_early_sel(0)) or + gate(reld_q1_way_q, reld_q_early_sel(1)) or + gate(reld_q2_way_q, reld_q_early_sel(2)) or + gate(reld_q3_way_q, reld_q_early_sel(3)) or + gate(reld_q4_way_q, reld_q_early_sel(4)) or + gate(reld_q5_way_q, reld_q_early_sel(5)) or + gate(reld_q6_way_q, reld_q_early_sel(6)) or + gate(reld_q7_way_q, reld_q_early_sel(7)); +rel_val_early_qsel <= (reld_q0_val_q and reld_q_early_sel(0)) or + (reld_q1_val_q and reld_q_early_sel(1)) or + (reld_q2_val_q and reld_q_early_sel(2)) or + (reld_q3_val_q and reld_q_early_sel(3)) or + (reld_q4_val_q and reld_q_early_sel(4)) or + (reld_q5_val_q and reld_q_early_sel(5)) or + (reld_q6_val_q and reld_q_early_sel(6)) or + (reld_q7_val_q and reld_q_early_sel(7)); +reld_q_early_byp <= (rel_st_tag_early = rel_tag_q) and rel2_val_q; +reld_way_early_byp <= rel_hit_vec; +rel_way_early_qsel_d <= gate(rel_way_early_qsel, not reld_q_early_byp) or gate(reld_way_early_byp, reld_q_early_byp); +rel_val_early_qsel_d <= rel_val_early_qsel or reld_q_early_byp; +rel_way_qsel_d <= gate(reld_q0_way_q, reld_q_sel_d(0)) or + gate(reld_q1_way_q, reld_q_sel_d(1)) or + gate(reld_q2_way_q, reld_q_sel_d(2)) or + gate(reld_q3_way_q, reld_q_sel_d(3)) or + gate(reld_q4_way_q, reld_q_sel_d(4)) or + gate(reld_q5_way_q, reld_q_sel_d(5)) or + gate(reld_q6_way_q, reld_q_sel_d(6)) or + gate(reld_q7_way_q, reld_q_sel_d(7)); +rel_val_qsel_d <= (reld_q0_val_q and reld_q_sel_d(0) and not reld_match(0)) or + (reld_q1_val_q and reld_q_sel_d(1) and not reld_match(1)) or + (reld_q2_val_q and reld_q_sel_d(2) and not reld_match(2)) or + (reld_q3_val_q and reld_q_sel_d(3) and not reld_match(3)) or + (reld_q4_val_q and reld_q_sel_d(4) and not reld_match(4)) or + (reld_q5_val_q and reld_q_sel_d(5) and not reld_match(5)) or + (reld_q6_val_q and reld_q_sel_d(6) and not reld_match(6)) or + (reld_q7_val_q and reld_q_sel_d(7) and not reld_match(7)); +rel_wayA_upd <= rel_way_early_qsel_q(0) and rel_val_early_qsel_q; +rel_wayB_upd <= rel_way_early_qsel_q(1) and rel_val_early_qsel_q; +rel_wayC_upd <= rel_way_early_qsel_q(2) and rel_val_early_qsel_q; +rel_wayD_upd <= rel_way_early_qsel_q(3) and rel_val_early_qsel_q; +rel_wayE_upd <= rel_way_early_qsel_q(4) and rel_val_early_qsel_q; +rel_wayF_upd <= rel_way_early_qsel_q(5) and rel_val_early_qsel_q; +rel_wayG_upd <= rel_way_early_qsel_q(6) and rel_val_early_qsel_q; +rel_wayH_upd <= rel_way_early_qsel_q(7) and rel_val_early_qsel_q; +rel_wayA_set <= rel_way_qsel_q(0) and rel4_val_q and rel_val_qsel_q; +rel_wayB_set <= rel_way_qsel_q(1) and rel4_val_q and rel_val_qsel_q; +rel_wayC_set <= rel_way_qsel_q(2) and rel4_val_q and rel_val_qsel_q; +rel_wayD_set <= rel_way_qsel_q(3) and rel4_val_q and rel_val_qsel_q; +rel_wayE_set <= rel_way_qsel_q(4) and rel4_val_q and rel_val_qsel_q; +rel_wayF_set <= rel_way_qsel_q(5) and rel4_val_q and rel_val_qsel_q; +rel_wayG_set <= rel_way_qsel_q(6) and rel4_val_q and rel_val_qsel_q; +rel_wayH_set <= rel_way_qsel_q(7) and rel4_val_q and rel_val_qsel_q; +rel_wayA_mid <= rel_way_qsel_q(0) and rel2_mid_val_q and rel_val_qsel_q; +rel_wayB_mid <= rel_way_qsel_q(1) and rel2_mid_val_q and rel_val_qsel_q; +rel_wayC_mid <= rel_way_qsel_q(2) and rel2_mid_val_q and rel_val_qsel_q; +rel_wayD_mid <= rel_way_qsel_q(3) and rel2_mid_val_q and rel_val_qsel_q; +rel_wayE_mid <= rel_way_qsel_q(4) and rel2_mid_val_q and rel_val_qsel_q; +rel_wayF_mid <= rel_way_qsel_q(5) and rel2_mid_val_q and rel_val_qsel_q; +rel_wayG_mid <= rel_way_qsel_q(6) and rel2_mid_val_q and rel_val_qsel_q; +rel_wayH_mid <= rel_way_qsel_q(7) and rel2_mid_val_q and rel_val_qsel_q; +with ex3_congr_cl_q select + arr_congr_cl_lru <= + congr_cl0_lru_q when "00000", + congr_cl1_lru_q when "00001", + congr_cl2_lru_q when "00010", + congr_cl3_lru_q when "00011", + congr_cl4_lru_q when "00100", + congr_cl5_lru_q when "00101", + congr_cl6_lru_q when "00110", + congr_cl7_lru_q when "00111", + congr_cl8_lru_q when "01000", + congr_cl9_lru_q when "01001", + congr_cl10_lru_q when "01010", + congr_cl11_lru_q when "01011", + congr_cl12_lru_q when "01100", + congr_cl13_lru_q when "01101", + congr_cl14_lru_q when "01110", + congr_cl15_lru_q when "01111", + congr_cl16_lru_q when "10000", + congr_cl17_lru_q when "10001", + congr_cl18_lru_q when "10010", + congr_cl19_lru_q when "10011", + congr_cl20_lru_q when "10100", + congr_cl21_lru_q when "10101", + congr_cl22_lru_q when "10110", + congr_cl23_lru_q when "10111", + congr_cl24_lru_q when "11000", + congr_cl25_lru_q when "11001", + congr_cl26_lru_q when "11010", + congr_cl27_lru_q when "11011", + congr_cl28_lru_q when "11100", + congr_cl29_lru_q when "11101", + congr_cl30_lru_q when "11110", + congr_cl31_lru_q when others; +p0_arr_lru_rd <= arr_congr_cl_lru; +ex3_c_acc_val <= ex3_cache_en and not (ex3_no_lru_upd_q or spr_xucr0_dcdis or ex3_flush); +ex4_hit_d <= ex3_l1hit; +ex4_c_acc_d <= ex3_c_acc_val; +ex4_c_acc <= ex4_c_acc_q and ex4_hit_q; +ex4_c_acc_val <= ex4_c_acc and not ex4_flush; +ex5_c_acc_d <= ex4_c_acc_val; +ex5_c_acc_val <= ex5_c_acc_q and not ex5_flush; +ex6_c_acc_val_d <= ex5_c_acc_val; +congr_cl_ex3_ex4_cmp_d <= (ex2_congr_cl_q = ex3_congr_cl_q); +congr_cl_ex3_ex5_cmp_d <= (ex2_congr_cl_q = ex4_congr_cl_q); +congr_cl_ex3_ex6_cmp_d <= (ex2_congr_cl_q = ex5_congr_cl_q); +congr_cl_ex3_rel2_cmp_d <= (ex2_congr_cl_q = rel_congr_cl_q); +congr_cl_ex3_rel_upd_cmp_d <= (ex2_congr_cl_q = relu_congr_cl_q); +congr_cl_ex3_ex4_m <= congr_cl_ex3_ex4_cmp_q and ex4_c_acc; +congr_cl_ex3_ex5_m <= congr_cl_ex3_ex5_cmp_q and ex5_c_acc_q; +congr_cl_ex3_rel2_m <= congr_cl_ex3_rel2_cmp_q and rel2_val_q and not ovr_lock_det; +congr_cl_ex3_p0_m <= congr_cl_ex3_ex6_cmp_q and ex6_c_acc_val_q; +congr_cl_ex3_p1_m <= congr_cl_ex3_rel_upd_cmp_q and rel_val_wen_q; +congr_cl_ex3_byp(0) <= congr_cl_ex3_rel2_m; +congr_cl_ex3_byp(1) <= congr_cl_ex3_ex4_m; +congr_cl_ex3_byp(2) <= congr_cl_ex3_ex5_m; +congr_cl_ex3_byp(3) <= congr_cl_ex3_p1_m; +congr_cl_ex3_byp(4) <= congr_cl_ex3_p0_m; +ex4_fxubyp_val_d <= congr_cl_ex3_byp(1) or congr_cl_ex3_byp(2) or congr_cl_ex3_byp(4); +ex4_relbyp_val_d <= congr_cl_ex3_byp(0) or congr_cl_ex3_byp(3); +ex4_lru_byp_sel <= ex4_fxubyp_val_q & ex4_relbyp_val_q; +congr_cl_ex3_sel(1) <= congr_cl_ex3_byp(1); +congr_cl_ex3_sel(2) <= congr_cl_ex3_byp(2) and not congr_cl_ex3_byp(1); +congr_cl_ex3_sel(3) <= congr_cl_ex3_byp(3) and not or_reduce(congr_cl_ex3_byp(1 to 2)); +congr_cl_ex3_sel(4) <= congr_cl_ex3_byp(4) and not or_reduce(congr_cl_ex3_byp(1 to 3)); +lru_late_sel <= or_reduce(congr_cl_ex3_byp(1 to 4)); +lru_late_stg_pri <= gate(lru_upd, congr_cl_ex3_sel(1)) or + gate(ex5_lru_upd_q, congr_cl_ex3_sel(2)) or + gate(rel_lru_val_q, congr_cl_ex3_sel(3)) or + gate(ex6_lru_upd_q, congr_cl_ex3_sel(4)); +lru_late_stg_arr <= gate(p0_arr_lru_rd, not lru_late_sel) or lru_late_stg_pri; +lru_early_sel <= (others=>congr_cl_ex3_byp(0)); +lru_early_sel_b <= (others=>(not congr_cl_ex3_byp(0))); +xu_op_lru <= not congr_cl_lru_b_q; +ldst_hit_vector <= ldst_wayA_hit & ldst_wayB_hit & ldst_wayC_hit & ldst_wayD_hit & + ldst_wayE_hit & ldst_wayF_hit & ldst_wayG_hit & ldst_wayH_hit; +hit_wayA_upd <= "11" & xu_op_lru(2) & "1" & xu_op_lru(4 to 6); +hit_wayB_upd <= "11" & xu_op_lru(2) & "0" & xu_op_lru(4 to 6); +hit_wayC_upd <= "10" & xu_op_lru(2 to 3) & "1" & xu_op_lru(5 to 6); +hit_wayD_upd <= "10" & xu_op_lru(2 to 3) & "0" & xu_op_lru(5 to 6); +hit_wayE_upd <= "0" & xu_op_lru(1) & "1" & xu_op_lru(3 to 4) & "1" & xu_op_lru(6); +hit_wayF_upd <= "0" & xu_op_lru(1) & "1" & xu_op_lru(3 to 4) & "0" & xu_op_lru(6); +hit_wayG_upd <= "0" & xu_op_lru(1) & "0" & xu_op_lru(3 to 5) & "1"; +hit_wayh_upd <= "0" & xu_op_lru(1) & "0" & xu_op_lru(3 to 5) & "0"; +ldst_hit_vec_sel <= or_reduce(ldst_hit_vector); +ldst_hit_lru_upd <= gate(hit_wayA_upd, ldst_hit_vector(0)) or gate(hit_wayB_upd, ldst_hit_vector(1)) or + gate(hit_wayC_upd, ldst_hit_vector(2)) or gate(hit_wayD_upd, ldst_hit_vector(3)) or + gate(hit_wayE_upd, ldst_hit_vector(4)) or gate(hit_wayF_upd, ldst_hit_vector(5)) or + gate(hit_wayG_upd, ldst_hit_vector(6)) or gate(hit_wayH_upd, ldst_hit_vector(7)); +with ldst_hit_vec_sel select + lru_upd <= ldst_hit_lru_upd when '1', + xu_op_lru when others; +ex5_lru_upd_d <= lru_upd; +ex6_lru_upd_d <= ex5_lru_upd_q; +rel_way_dwen <= (rel_wayA_clr or rel_wayA_set or rel_wayA_mid) & (rel_wayB_clr or rel_wayB_set or rel_wayB_mid) & + (rel_wayC_clr or rel_wayC_set or rel_wayC_mid) & (rel_wayD_clr or rel_wayD_set or rel_wayD_mid) & + (rel_wayE_clr or rel_wayE_set or rel_wayE_mid) & (rel_wayF_clr or rel_wayF_set or rel_wayF_mid) & + (rel_wayG_clr or rel_wayG_set or rel_wayG_mid) & (rel_wayH_clr or rel_wayH_set or rel_wayH_mid); +rel24_way_dwen_stg_d <= rel_way_dwen; +rel_dcarr_val_upd_d <= or_reduce(rel_way_dwen) and not rel4_retry_val_q; +rel_up_way_addr_d <= gate("001", rel_way_dwen(1)) or + gate("010", rel_way_dwen(2)) or gate("011", rel_way_dwen(3)) or + gate("100", rel_way_dwen(4)) or gate("101", rel_way_dwen(5)) or + gate("110", rel_way_dwen(6)) or gate("111", rel_way_dwen(7)); +rel_up_way_addr_b <= not rel_up_way_addr_q; +rel_dcarr_addr_en <= rel_dcarr_addr_en_q; +congr_cl_act_d <= ex5_c_acc_q or relu_val_wen_q; +xu_op_cl0_lru_wen <= (ex6_congr_cl_q = tconv(0,5)) and ex6_c_acc_val_q; +rel_cl0_lru_wen <= (rel_upd_congr_cl_q = tconv(0,5)) and rel_val_wen_q; +congr_cl0_lru_wen <= xu_op_cl0_lru_wen or rel_cl0_lru_wen; +with rel_cl0_lru_wen select + rel_ldst_cl0_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl0_lru_wen select + congr_cl0_lru_d <= rel_ldst_cl0_lru when '1', + congr_cl0_lru_q when others; +xu_op_cl1_lru_wen <= (ex6_congr_cl_q = tconv(1,5)) and ex6_c_acc_val_q; +rel_cl1_lru_wen <= (rel_upd_congr_cl_q = tconv(1,5)) and rel_val_wen_q; +congr_cl1_lru_wen <= xu_op_cl1_lru_wen or rel_cl1_lru_wen; +with rel_cl1_lru_wen select + rel_ldst_cl1_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl1_lru_wen select + congr_cl1_lru_d <= rel_ldst_cl1_lru when '1', + congr_cl1_lru_q when others; +xu_op_cl2_lru_wen <= (ex6_congr_cl_q = tconv(2,5)) and ex6_c_acc_val_q; +rel_cl2_lru_wen <= (rel_upd_congr_cl_q = tconv(2,5)) and rel_val_wen_q; +congr_cl2_lru_wen <= xu_op_cl2_lru_wen or rel_cl2_lru_wen; +with rel_cl2_lru_wen select + rel_ldst_cl2_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl2_lru_wen select + congr_cl2_lru_d <= rel_ldst_cl2_lru when '1', + congr_cl2_lru_q when others; +xu_op_cl3_lru_wen <= (ex6_congr_cl_q = tconv(3,5)) and ex6_c_acc_val_q; +rel_cl3_lru_wen <= (rel_upd_congr_cl_q = tconv(3,5)) and rel_val_wen_q; +congr_cl3_lru_wen <= xu_op_cl3_lru_wen or rel_cl3_lru_wen; +with rel_cl3_lru_wen select + rel_ldst_cl3_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl3_lru_wen select + congr_cl3_lru_d <= rel_ldst_cl3_lru when '1', + congr_cl3_lru_q when others; +xu_op_cl4_lru_wen <= (ex6_congr_cl_q = tconv(4,5)) and ex6_c_acc_val_q; +rel_cl4_lru_wen <= (rel_upd_congr_cl_q = tconv(4,5)) and rel_val_wen_q; +congr_cl4_lru_wen <= xu_op_cl4_lru_wen or rel_cl4_lru_wen; +with rel_cl4_lru_wen select + rel_ldst_cl4_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl4_lru_wen select + congr_cl4_lru_d <= rel_ldst_cl4_lru when '1', + congr_cl4_lru_q when others; +xu_op_cl5_lru_wen <= (ex6_congr_cl_q = tconv(5,5)) and ex6_c_acc_val_q; +rel_cl5_lru_wen <= (rel_upd_congr_cl_q = tconv(5,5)) and rel_val_wen_q; +congr_cl5_lru_wen <= xu_op_cl5_lru_wen or rel_cl5_lru_wen; +with rel_cl5_lru_wen select + rel_ldst_cl5_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl5_lru_wen select + congr_cl5_lru_d <= rel_ldst_cl5_lru when '1', + congr_cl5_lru_q when others; +xu_op_cl6_lru_wen <= (ex6_congr_cl_q = tconv(6,5)) and ex6_c_acc_val_q; +rel_cl6_lru_wen <= (rel_upd_congr_cl_q = tconv(6,5)) and rel_val_wen_q; +congr_cl6_lru_wen <= xu_op_cl6_lru_wen or rel_cl6_lru_wen; +with rel_cl6_lru_wen select + rel_ldst_cl6_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl6_lru_wen select + congr_cl6_lru_d <= rel_ldst_cl6_lru when '1', + congr_cl6_lru_q when others; +xu_op_cl7_lru_wen <= (ex6_congr_cl_q = tconv(7,5)) and ex6_c_acc_val_q; +rel_cl7_lru_wen <= (rel_upd_congr_cl_q = tconv(7,5)) and rel_val_wen_q; +congr_cl7_lru_wen <= xu_op_cl7_lru_wen or rel_cl7_lru_wen; +with rel_cl7_lru_wen select + rel_ldst_cl7_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl7_lru_wen select + congr_cl7_lru_d <= rel_ldst_cl7_lru when '1', + congr_cl7_lru_q when others; +xu_op_cl8_lru_wen <= (ex6_congr_cl_q = tconv(8,5)) and ex6_c_acc_val_q; +rel_cl8_lru_wen <= (rel_upd_congr_cl_q = tconv(8,5)) and rel_val_wen_q; +congr_cl8_lru_wen <= xu_op_cl8_lru_wen or rel_cl8_lru_wen; +with rel_cl8_lru_wen select + rel_ldst_cl8_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl8_lru_wen select + congr_cl8_lru_d <= rel_ldst_cl8_lru when '1', + congr_cl8_lru_q when others; +xu_op_cl9_lru_wen <= (ex6_congr_cl_q = tconv(9,5)) and ex6_c_acc_val_q; +rel_cl9_lru_wen <= (rel_upd_congr_cl_q = tconv(9,5)) and rel_val_wen_q; +congr_cl9_lru_wen <= xu_op_cl9_lru_wen or rel_cl9_lru_wen; +with rel_cl9_lru_wen select + rel_ldst_cl9_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl9_lru_wen select + congr_cl9_lru_d <= rel_ldst_cl9_lru when '1', + congr_cl9_lru_q when others; +xu_op_cl10_lru_wen <= (ex6_congr_cl_q = tconv(10,5)) and ex6_c_acc_val_q; +rel_cl10_lru_wen <= (rel_upd_congr_cl_q = tconv(10,5)) and rel_val_wen_q; +congr_cl10_lru_wen <= xu_op_cl10_lru_wen or rel_cl10_lru_wen; +with rel_cl10_lru_wen select + rel_ldst_cl10_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl10_lru_wen select + congr_cl10_lru_d <= rel_ldst_cl10_lru when '1', + congr_cl10_lru_q when others; +xu_op_cl11_lru_wen <= (ex6_congr_cl_q = tconv(11,5)) and ex6_c_acc_val_q; +rel_cl11_lru_wen <= (rel_upd_congr_cl_q = tconv(11,5)) and rel_val_wen_q; +congr_cl11_lru_wen <= xu_op_cl11_lru_wen or rel_cl11_lru_wen; +with rel_cl11_lru_wen select + rel_ldst_cl11_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl11_lru_wen select + congr_cl11_lru_d <= rel_ldst_cl11_lru when '1', + congr_cl11_lru_q when others; +xu_op_cl12_lru_wen <= (ex6_congr_cl_q = tconv(12,5)) and ex6_c_acc_val_q; +rel_cl12_lru_wen <= (rel_upd_congr_cl_q = tconv(12,5)) and rel_val_wen_q; +congr_cl12_lru_wen <= xu_op_cl12_lru_wen or rel_cl12_lru_wen; +with rel_cl12_lru_wen select + rel_ldst_cl12_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl12_lru_wen select + congr_cl12_lru_d <= rel_ldst_cl12_lru when '1', + congr_cl12_lru_q when others; +xu_op_cl13_lru_wen <= (ex6_congr_cl_q = tconv(13,5)) and ex6_c_acc_val_q; +rel_cl13_lru_wen <= (rel_upd_congr_cl_q = tconv(13,5)) and rel_val_wen_q; +congr_cl13_lru_wen <= xu_op_cl13_lru_wen or rel_cl13_lru_wen; +with rel_cl13_lru_wen select + rel_ldst_cl13_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl13_lru_wen select + congr_cl13_lru_d <= rel_ldst_cl13_lru when '1', + congr_cl13_lru_q when others; +xu_op_cl14_lru_wen <= (ex6_congr_cl_q = tconv(14,5)) and ex6_c_acc_val_q; +rel_cl14_lru_wen <= (rel_upd_congr_cl_q = tconv(14,5)) and rel_val_wen_q; +congr_cl14_lru_wen <= xu_op_cl14_lru_wen or rel_cl14_lru_wen; +with rel_cl14_lru_wen select + rel_ldst_cl14_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl14_lru_wen select + congr_cl14_lru_d <= rel_ldst_cl14_lru when '1', + congr_cl14_lru_q when others; +xu_op_cl15_lru_wen <= (ex6_congr_cl_q = tconv(15,5)) and ex6_c_acc_val_q; +rel_cl15_lru_wen <= (rel_upd_congr_cl_q = tconv(15,5)) and rel_val_wen_q; +congr_cl15_lru_wen <= xu_op_cl15_lru_wen or rel_cl15_lru_wen; +with rel_cl15_lru_wen select + rel_ldst_cl15_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl15_lru_wen select + congr_cl15_lru_d <= rel_ldst_cl15_lru when '1', + congr_cl15_lru_q when others; +xu_op_cl16_lru_wen <= (ex6_congr_cl_q = tconv(16,5)) and ex6_c_acc_val_q; +rel_cl16_lru_wen <= (rel_upd_congr_cl_q = tconv(16,5)) and rel_val_wen_q; +congr_cl16_lru_wen <= xu_op_cl16_lru_wen or rel_cl16_lru_wen; +with rel_cl16_lru_wen select + rel_ldst_cl16_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl16_lru_wen select + congr_cl16_lru_d <= rel_ldst_cl16_lru when '1', + congr_cl16_lru_q when others; +xu_op_cl17_lru_wen <= (ex6_congr_cl_q = tconv(17,5)) and ex6_c_acc_val_q; +rel_cl17_lru_wen <= (rel_upd_congr_cl_q = tconv(17,5)) and rel_val_wen_q; +congr_cl17_lru_wen <= xu_op_cl17_lru_wen or rel_cl17_lru_wen; +with rel_cl17_lru_wen select + rel_ldst_cl17_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl17_lru_wen select + congr_cl17_lru_d <= rel_ldst_cl17_lru when '1', + congr_cl17_lru_q when others; +xu_op_cl18_lru_wen <= (ex6_congr_cl_q = tconv(18,5)) and ex6_c_acc_val_q; +rel_cl18_lru_wen <= (rel_upd_congr_cl_q = tconv(18,5)) and rel_val_wen_q; +congr_cl18_lru_wen <= xu_op_cl18_lru_wen or rel_cl18_lru_wen; +with rel_cl18_lru_wen select + rel_ldst_cl18_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl18_lru_wen select + congr_cl18_lru_d <= rel_ldst_cl18_lru when '1', + congr_cl18_lru_q when others; +xu_op_cl19_lru_wen <= (ex6_congr_cl_q = tconv(19,5)) and ex6_c_acc_val_q; +rel_cl19_lru_wen <= (rel_upd_congr_cl_q = tconv(19,5)) and rel_val_wen_q; +congr_cl19_lru_wen <= xu_op_cl19_lru_wen or rel_cl19_lru_wen; +with rel_cl19_lru_wen select + rel_ldst_cl19_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl19_lru_wen select + congr_cl19_lru_d <= rel_ldst_cl19_lru when '1', + congr_cl19_lru_q when others; +xu_op_cl20_lru_wen <= (ex6_congr_cl_q = tconv(20,5)) and ex6_c_acc_val_q; +rel_cl20_lru_wen <= (rel_upd_congr_cl_q = tconv(20,5)) and rel_val_wen_q; +congr_cl20_lru_wen <= xu_op_cl20_lru_wen or rel_cl20_lru_wen; +with rel_cl20_lru_wen select + rel_ldst_cl20_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl20_lru_wen select + congr_cl20_lru_d <= rel_ldst_cl20_lru when '1', + congr_cl20_lru_q when others; +xu_op_cl21_lru_wen <= (ex6_congr_cl_q = tconv(21,5)) and ex6_c_acc_val_q; +rel_cl21_lru_wen <= (rel_upd_congr_cl_q = tconv(21,5)) and rel_val_wen_q; +congr_cl21_lru_wen <= xu_op_cl21_lru_wen or rel_cl21_lru_wen; +with rel_cl21_lru_wen select + rel_ldst_cl21_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl21_lru_wen select + congr_cl21_lru_d <= rel_ldst_cl21_lru when '1', + congr_cl21_lru_q when others; +xu_op_cl22_lru_wen <= (ex6_congr_cl_q = tconv(22,5)) and ex6_c_acc_val_q; +rel_cl22_lru_wen <= (rel_upd_congr_cl_q = tconv(22,5)) and rel_val_wen_q; +congr_cl22_lru_wen <= xu_op_cl22_lru_wen or rel_cl22_lru_wen; +with rel_cl22_lru_wen select + rel_ldst_cl22_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl22_lru_wen select + congr_cl22_lru_d <= rel_ldst_cl22_lru when '1', + congr_cl22_lru_q when others; +xu_op_cl23_lru_wen <= (ex6_congr_cl_q = tconv(23,5)) and ex6_c_acc_val_q; +rel_cl23_lru_wen <= (rel_upd_congr_cl_q = tconv(23,5)) and rel_val_wen_q; +congr_cl23_lru_wen <= xu_op_cl23_lru_wen or rel_cl23_lru_wen; +with rel_cl23_lru_wen select + rel_ldst_cl23_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl23_lru_wen select + congr_cl23_lru_d <= rel_ldst_cl23_lru when '1', + congr_cl23_lru_q when others; +xu_op_cl24_lru_wen <= (ex6_congr_cl_q = tconv(24,5)) and ex6_c_acc_val_q; +rel_cl24_lru_wen <= (rel_upd_congr_cl_q = tconv(24,5)) and rel_val_wen_q; +congr_cl24_lru_wen <= xu_op_cl24_lru_wen or rel_cl24_lru_wen; +with rel_cl24_lru_wen select + rel_ldst_cl24_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl24_lru_wen select + congr_cl24_lru_d <= rel_ldst_cl24_lru when '1', + congr_cl24_lru_q when others; +xu_op_cl25_lru_wen <= (ex6_congr_cl_q = tconv(25,5)) and ex6_c_acc_val_q; +rel_cl25_lru_wen <= (rel_upd_congr_cl_q = tconv(25,5)) and rel_val_wen_q; +congr_cl25_lru_wen <= xu_op_cl25_lru_wen or rel_cl25_lru_wen; +with rel_cl25_lru_wen select + rel_ldst_cl25_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl25_lru_wen select + congr_cl25_lru_d <= rel_ldst_cl25_lru when '1', + congr_cl25_lru_q when others; +xu_op_cl26_lru_wen <= (ex6_congr_cl_q = tconv(26,5)) and ex6_c_acc_val_q; +rel_cl26_lru_wen <= (rel_upd_congr_cl_q = tconv(26,5)) and rel_val_wen_q; +congr_cl26_lru_wen <= xu_op_cl26_lru_wen or rel_cl26_lru_wen; +with rel_cl26_lru_wen select + rel_ldst_cl26_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl26_lru_wen select + congr_cl26_lru_d <= rel_ldst_cl26_lru when '1', + congr_cl26_lru_q when others; +xu_op_cl27_lru_wen <= (ex6_congr_cl_q = tconv(27,5)) and ex6_c_acc_val_q; +rel_cl27_lru_wen <= (rel_upd_congr_cl_q = tconv(27,5)) and rel_val_wen_q; +congr_cl27_lru_wen <= xu_op_cl27_lru_wen or rel_cl27_lru_wen; +with rel_cl27_lru_wen select + rel_ldst_cl27_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl27_lru_wen select + congr_cl27_lru_d <= rel_ldst_cl27_lru when '1', + congr_cl27_lru_q when others; +xu_op_cl28_lru_wen <= (ex6_congr_cl_q = tconv(28,5)) and ex6_c_acc_val_q; +rel_cl28_lru_wen <= (rel_upd_congr_cl_q = tconv(28,5)) and rel_val_wen_q; +congr_cl28_lru_wen <= xu_op_cl28_lru_wen or rel_cl28_lru_wen; +with rel_cl28_lru_wen select + rel_ldst_cl28_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl28_lru_wen select + congr_cl28_lru_d <= rel_ldst_cl28_lru when '1', + congr_cl28_lru_q when others; +xu_op_cl29_lru_wen <= (ex6_congr_cl_q = tconv(29,5)) and ex6_c_acc_val_q; +rel_cl29_lru_wen <= (rel_upd_congr_cl_q = tconv(29,5)) and rel_val_wen_q; +congr_cl29_lru_wen <= xu_op_cl29_lru_wen or rel_cl29_lru_wen; +with rel_cl29_lru_wen select + rel_ldst_cl29_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl29_lru_wen select + congr_cl29_lru_d <= rel_ldst_cl29_lru when '1', + congr_cl29_lru_q when others; +xu_op_cl30_lru_wen <= (ex6_congr_cl_q = tconv(30,5)) and ex6_c_acc_val_q; +rel_cl30_lru_wen <= (rel_upd_congr_cl_q = tconv(30,5)) and rel_val_wen_q; +congr_cl30_lru_wen <= xu_op_cl30_lru_wen or rel_cl30_lru_wen; +with rel_cl30_lru_wen select + rel_ldst_cl30_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl30_lru_wen select + congr_cl30_lru_d <= rel_ldst_cl30_lru when '1', + congr_cl30_lru_q when others; +xu_op_cl31_lru_wen <= (ex6_congr_cl_q = tconv(31,5)) and ex6_c_acc_val_q; +rel_cl31_lru_wen <= (rel_upd_congr_cl_q = tconv(31,5)) and rel_val_wen_q; +congr_cl31_lru_wen <= xu_op_cl31_lru_wen or rel_cl31_lru_wen; +with rel_cl31_lru_wen select + rel_ldst_cl31_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl31_lru_wen select + congr_cl31_lru_d <= rel_ldst_cl31_lru when '1', + congr_cl31_lru_q when others; +rel_way_clr_a <= rel_wayA_clr; +rel_way_clr_b <= rel_wayB_clr; +rel_way_clr_c <= rel_wayC_clr; +rel_way_clr_d <= rel_wayD_clr; +rel_way_clr_e <= rel_wayE_clr; +rel_way_clr_f <= rel_wayF_clr; +rel_way_clr_g <= rel_wayG_clr; +rel_way_clr_h <= rel_wayH_clr; +rel_way_upd_a <= rel_wayA_upd; +rel_way_upd_b <= rel_wayB_upd; +rel_way_upd_c <= rel_wayC_upd; +rel_way_upd_d <= rel_wayD_upd; +rel_way_upd_e <= rel_wayE_upd; +rel_way_upd_f <= rel_wayF_upd; +rel_way_upd_g <= rel_wayG_upd; +rel_way_upd_h <= rel_wayH_upd; +rel_way_wen_a <= rel_wayA_set; +rel_way_wen_b <= rel_wayB_set; +rel_way_wen_c <= rel_wayC_set; +rel_way_wen_d <= rel_wayD_set; +rel_way_wen_e <= rel_wayE_set; +rel_way_wen_f <= rel_wayF_set; +rel_way_wen_g <= rel_wayG_set; +rel_way_wen_h <= rel_wayH_set; +rel_dcarr_val_upd <= rel_dcarr_val_upd_q; +lsu_xu_spr_xucr0_clo <= xucr0_clo_q; +ex4_dir_lru <= xu_op_lru; +dc_lru_dbg_data <= rel24_way_dwen_stg_q & reld_q_val & rel_m_q_way_q & rel2_wlock_q & + rel_way_not_empty_q & ex4_lru_byp_sel & rel2_lru_byp_sel & rel_val_wen_q & + rel_op_lru & rel_lru_val_q & xucr0_clo_q & xu_op_lru & + ex6_c_acc_val_q & ex6_lru_upd_q & rel2_class_id_q & rel_tag_q & + rel4_retry_val_q & ex4_c_acc; +congr_cl0_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl0_lru_offset to congr_cl0_lru_offset + congr_cl0_lru_d'length-1), + scout => sov(congr_cl0_lru_offset to congr_cl0_lru_offset + congr_cl0_lru_d'length-1), + din => congr_cl0_lru_d, + dout => congr_cl0_lru_q); +congr_cl1_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl1_lru_offset to congr_cl1_lru_offset + congr_cl1_lru_d'length-1), + scout => sov(congr_cl1_lru_offset to congr_cl1_lru_offset + congr_cl1_lru_d'length-1), + din => congr_cl1_lru_d, + dout => congr_cl1_lru_q); +congr_cl2_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl2_lru_offset to congr_cl2_lru_offset + congr_cl2_lru_d'length-1), + scout => sov(congr_cl2_lru_offset to congr_cl2_lru_offset + congr_cl2_lru_d'length-1), + din => congr_cl2_lru_d, + dout => congr_cl2_lru_q); +congr_cl3_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl3_lru_offset to congr_cl3_lru_offset + congr_cl3_lru_d'length-1), + scout => sov(congr_cl3_lru_offset to congr_cl3_lru_offset + congr_cl3_lru_d'length-1), + din => congr_cl3_lru_d, + dout => congr_cl3_lru_q); +congr_cl4_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl4_lru_offset to congr_cl4_lru_offset + congr_cl4_lru_d'length-1), + scout => sov(congr_cl4_lru_offset to congr_cl4_lru_offset + congr_cl4_lru_d'length-1), + din => congr_cl4_lru_d, + dout => congr_cl4_lru_q); +congr_cl5_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl5_lru_offset to congr_cl5_lru_offset + congr_cl5_lru_d'length-1), + scout => sov(congr_cl5_lru_offset to congr_cl5_lru_offset + congr_cl5_lru_d'length-1), + din => congr_cl5_lru_d, + dout => congr_cl5_lru_q); +congr_cl6_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl6_lru_offset to congr_cl6_lru_offset + congr_cl6_lru_d'length-1), + scout => sov(congr_cl6_lru_offset to congr_cl6_lru_offset + congr_cl6_lru_d'length-1), + din => congr_cl6_lru_d, + dout => congr_cl6_lru_q); +congr_cl7_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl7_lru_offset to congr_cl7_lru_offset + congr_cl7_lru_d'length-1), + scout => sov(congr_cl7_lru_offset to congr_cl7_lru_offset + congr_cl7_lru_d'length-1), + din => congr_cl7_lru_d, + dout => congr_cl7_lru_q); +congr_cl8_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl8_lru_offset to congr_cl8_lru_offset + congr_cl8_lru_d'length-1), + scout => sov(congr_cl8_lru_offset to congr_cl8_lru_offset + congr_cl8_lru_d'length-1), + din => congr_cl8_lru_d, + dout => congr_cl8_lru_q); +congr_cl9_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl9_lru_offset to congr_cl9_lru_offset + congr_cl9_lru_d'length-1), + scout => sov(congr_cl9_lru_offset to congr_cl9_lru_offset + congr_cl9_lru_d'length-1), + din => congr_cl9_lru_d, + dout => congr_cl9_lru_q); +congr_cl10_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl10_lru_offset to congr_cl10_lru_offset + congr_cl10_lru_d'length-1), + scout => sov(congr_cl10_lru_offset to congr_cl10_lru_offset + congr_cl10_lru_d'length-1), + din => congr_cl10_lru_d, + dout => congr_cl10_lru_q); +congr_cl11_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl11_lru_offset to congr_cl11_lru_offset + congr_cl11_lru_d'length-1), + scout => sov(congr_cl11_lru_offset to congr_cl11_lru_offset + congr_cl11_lru_d'length-1), + din => congr_cl11_lru_d, + dout => congr_cl11_lru_q); +congr_cl12_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl12_lru_offset to congr_cl12_lru_offset + congr_cl12_lru_d'length-1), + scout => sov(congr_cl12_lru_offset to congr_cl12_lru_offset + congr_cl12_lru_d'length-1), + din => congr_cl12_lru_d, + dout => congr_cl12_lru_q); +congr_cl13_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl13_lru_offset to congr_cl13_lru_offset + congr_cl13_lru_d'length-1), + scout => sov(congr_cl13_lru_offset to congr_cl13_lru_offset + congr_cl13_lru_d'length-1), + din => congr_cl13_lru_d, + dout => congr_cl13_lru_q); +congr_cl14_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl14_lru_offset to congr_cl14_lru_offset + congr_cl14_lru_d'length-1), + scout => sov(congr_cl14_lru_offset to congr_cl14_lru_offset + congr_cl14_lru_d'length-1), + din => congr_cl14_lru_d, + dout => congr_cl14_lru_q); +congr_cl15_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl15_lru_offset to congr_cl15_lru_offset + congr_cl15_lru_d'length-1), + scout => sov(congr_cl15_lru_offset to congr_cl15_lru_offset + congr_cl15_lru_d'length-1), + din => congr_cl15_lru_d, + dout => congr_cl15_lru_q); +congr_cl16_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl16_lru_offset to congr_cl16_lru_offset + congr_cl16_lru_d'length-1), + scout => sov(congr_cl16_lru_offset to congr_cl16_lru_offset + congr_cl16_lru_d'length-1), + din => congr_cl16_lru_d, + dout => congr_cl16_lru_q); +congr_cl17_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl17_lru_offset to congr_cl17_lru_offset + congr_cl17_lru_d'length-1), + scout => sov(congr_cl17_lru_offset to congr_cl17_lru_offset + congr_cl17_lru_d'length-1), + din => congr_cl17_lru_d, + dout => congr_cl17_lru_q); +congr_cl18_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl18_lru_offset to congr_cl18_lru_offset + congr_cl18_lru_d'length-1), + scout => sov(congr_cl18_lru_offset to congr_cl18_lru_offset + congr_cl18_lru_d'length-1), + din => congr_cl18_lru_d, + dout => congr_cl18_lru_q); +congr_cl19_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl19_lru_offset to congr_cl19_lru_offset + congr_cl19_lru_d'length-1), + scout => sov(congr_cl19_lru_offset to congr_cl19_lru_offset + congr_cl19_lru_d'length-1), + din => congr_cl19_lru_d, + dout => congr_cl19_lru_q); +congr_cl20_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl20_lru_offset to congr_cl20_lru_offset + congr_cl20_lru_d'length-1), + scout => sov(congr_cl20_lru_offset to congr_cl20_lru_offset + congr_cl20_lru_d'length-1), + din => congr_cl20_lru_d, + dout => congr_cl20_lru_q); +congr_cl21_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl21_lru_offset to congr_cl21_lru_offset + congr_cl21_lru_d'length-1), + scout => sov(congr_cl21_lru_offset to congr_cl21_lru_offset + congr_cl21_lru_d'length-1), + din => congr_cl21_lru_d, + dout => congr_cl21_lru_q); +congr_cl22_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl22_lru_offset to congr_cl22_lru_offset + congr_cl22_lru_d'length-1), + scout => sov(congr_cl22_lru_offset to congr_cl22_lru_offset + congr_cl22_lru_d'length-1), + din => congr_cl22_lru_d, + dout => congr_cl22_lru_q); +congr_cl23_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl23_lru_offset to congr_cl23_lru_offset + congr_cl23_lru_d'length-1), + scout => sov(congr_cl23_lru_offset to congr_cl23_lru_offset + congr_cl23_lru_d'length-1), + din => congr_cl23_lru_d, + dout => congr_cl23_lru_q); +congr_cl24_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl24_lru_offset to congr_cl24_lru_offset + congr_cl24_lru_d'length-1), + scout => sov(congr_cl24_lru_offset to congr_cl24_lru_offset + congr_cl24_lru_d'length-1), + din => congr_cl24_lru_d, + dout => congr_cl24_lru_q); +congr_cl25_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl25_lru_offset to congr_cl25_lru_offset + congr_cl25_lru_d'length-1), + scout => sov(congr_cl25_lru_offset to congr_cl25_lru_offset + congr_cl25_lru_d'length-1), + din => congr_cl25_lru_d, + dout => congr_cl25_lru_q); +congr_cl26_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl26_lru_offset to congr_cl26_lru_offset + congr_cl26_lru_d'length-1), + scout => sov(congr_cl26_lru_offset to congr_cl26_lru_offset + congr_cl26_lru_d'length-1), + din => congr_cl26_lru_d, + dout => congr_cl26_lru_q); +congr_cl27_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl27_lru_offset to congr_cl27_lru_offset + congr_cl27_lru_d'length-1), + scout => sov(congr_cl27_lru_offset to congr_cl27_lru_offset + congr_cl27_lru_d'length-1), + din => congr_cl27_lru_d, + dout => congr_cl27_lru_q); +congr_cl28_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl28_lru_offset to congr_cl28_lru_offset + congr_cl28_lru_d'length-1), + scout => sov(congr_cl28_lru_offset to congr_cl28_lru_offset + congr_cl28_lru_d'length-1), + din => congr_cl28_lru_d, + dout => congr_cl28_lru_q); +congr_cl29_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl29_lru_offset to congr_cl29_lru_offset + congr_cl29_lru_d'length-1), + scout => sov(congr_cl29_lru_offset to congr_cl29_lru_offset + congr_cl29_lru_d'length-1), + din => congr_cl29_lru_d, + dout => congr_cl29_lru_q); +congr_cl30_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl30_lru_offset to congr_cl30_lru_offset + congr_cl30_lru_d'length-1), + scout => sov(congr_cl30_lru_offset to congr_cl30_lru_offset + congr_cl30_lru_d'length-1), + din => congr_cl30_lru_d, + dout => congr_cl30_lru_q); +congr_cl31_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl31_lru_offset to congr_cl31_lru_offset + congr_cl31_lru_d'length-1), + scout => sov(congr_cl31_lru_offset to congr_cl31_lru_offset + congr_cl31_lru_d'length-1), + din => congr_cl31_lru_d, + dout => congr_cl31_lru_q); +congr_cl_lru_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_lru_b_offset to congr_cl_lru_b_offset + congr_cl_lru_b_q'length-1), + scout => sov(congr_cl_lru_b_offset to congr_cl_lru_b_offset + congr_cl_lru_b_q'length-1), + a1 => rel_hit_lru_upd, + a2 => lru_early_sel, + b1 => lru_late_stg_arr, + b2 => lru_early_sel_b, + qb => congr_cl_lru_b_q); +rel_congr_cl_lru_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_congr_cl_lru_b_offset to rel_congr_cl_lru_b_offset + rel_congr_cl_lru_b_q'length-1), + scout => sov(rel_congr_cl_lru_b_offset to rel_congr_cl_lru_b_offset + rel_congr_cl_lru_b_q'length-1), + a1 => rel_hit_lru_upd, + a2 => rel_lru_early_sel, + b1 => rel_lru_late_stg_arr, + b2 => rel_lru_early_sel_b, + qb => rel_congr_cl_lru_b_q); +reld_q_sel_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q_sel_offset to reld_q_sel_offset + reld_q_sel_d'length-1), + scout => sov(reld_q_sel_offset to reld_q_sel_offset + reld_q_sel_d'length-1), + din => reld_q_sel_d, + dout => reld_q_sel_q); +ex4_congr_cl_reg: tri_regk +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex4_congr_cl_d, + dout => ex4_congr_cl_q); +ex5_congr_cl_reg: tri_rlmreg_p +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_congr_cl_offset to ex5_congr_cl_offset + ex5_congr_cl_d'length-1), + scout => sov(ex5_congr_cl_offset to ex5_congr_cl_offset + ex5_congr_cl_d'length-1), + din => ex5_congr_cl_d, + dout => ex5_congr_cl_q); +ex6_congr_cl_reg: tri_regk +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex5_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex6_congr_cl_d, + dout => ex6_congr_cl_q); +rel_congr_cl_reg: tri_rlmreg_p +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_congr_cl_offset to rel_congr_cl_offset + rel_congr_cl_d'length-1), + scout => sov(rel_congr_cl_offset to rel_congr_cl_offset + rel_congr_cl_d'length-1), + din => rel_congr_cl_d, + dout => rel_congr_cl_q); +rel_congr_cl_stg_reg: tri_regk +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_congr_cl_stg_d, + dout => rel_congr_cl_stg_q); +relu_congr_cl_reg: tri_rlmreg_p +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(relu_congr_cl_offset to relu_congr_cl_offset + relu_congr_cl_d'length-1), + scout => sov(relu_congr_cl_offset to relu_congr_cl_offset + relu_congr_cl_d'length-1), + din => relu_congr_cl_d, + dout => relu_congr_cl_q); +ex5_lru_upd_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_lru_upd_offset to ex5_lru_upd_offset + ex5_lru_upd_d'length-1), + scout => sov(ex5_lru_upd_offset to ex5_lru_upd_offset + ex5_lru_upd_d'length-1), + din => ex5_lru_upd_d, + dout => ex5_lru_upd_q); +ex6_lru_upd_reg: tri_regk +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex5_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex6_lru_upd_d, + dout => ex6_lru_upd_q); +rel2_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel2_val_offset), + scout => sov(rel2_val_offset), + din => rel2_val_d, + dout => rel2_val_q); +rel2_class_id_reg: tri_regk +generic map (width => 2, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel2_class_id_d, + dout => rel2_class_id_q); +relu_val_wen_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(relu_val_wen_offset), + scout => sov(relu_val_wen_offset), + din => relu_val_wen_d, + dout => relu_val_wen_q); +ex4_hit_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_hit_offset), + scout => sov(ex4_hit_offset), + din => ex4_hit_d, + dout => ex4_hit_q); +ex4_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex4_fxubyp_val_d, + dout(0) => ex4_fxubyp_val_q); +ex4_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex4_relbyp_val_d, + dout(0) => ex4_relbyp_val_q); +ex4_c_acc_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_c_acc_offset), + scout => sov(ex4_c_acc_offset), + din => ex4_c_acc_d, + dout => ex4_c_acc_q); +ex5_c_acc_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_c_acc_offset), + scout => sov(ex5_c_acc_offset), + din => ex5_c_acc_d, + dout => ex5_c_acc_q); +ex6_c_acc_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_c_acc_val_offset), + scout => sov(ex6_c_acc_val_offset), + din => ex6_c_acc_val_d, + dout => ex6_c_acc_val_q); +ex2_congr_cl_reg: tri_regk +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex2_congr_cl_d, + dout => ex2_congr_cl_q); +ex3_congr_cl_reg: tri_rlmreg_p +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_congr_cl_offset to ex3_congr_cl_offset + ex3_congr_cl_d'length-1), + scout => sov(ex3_congr_cl_offset to ex3_congr_cl_offset + ex3_congr_cl_d'length-1), + din => ex3_congr_cl_d, + dout => ex3_congr_cl_q); +rel_val_wen_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_val_wen_offset), + scout => sov(rel_val_wen_offset), + din => rel_val_wen_d, + dout => rel_val_wen_q); +rel_way_not_empty_reg: tri_regk +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_way_not_empty_d, + dout => rel_way_not_empty_q); +relu_lru_upd_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(relu_lru_upd_offset to relu_lru_upd_offset + relu_lru_upd_d'length-1), + scout => sov(relu_lru_upd_offset to relu_lru_upd_offset + relu_lru_upd_d'length-1), + din => relu_lru_upd_d, + dout => relu_lru_upd_q); +rel_lru_val_reg: tri_regk +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_lru_val_d, + dout => rel_lru_val_q); +rel_upd_congr_cl_reg: tri_regk +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_upd_congr_cl_d, + dout => rel_upd_congr_cl_q); +rel_tag_reg: tri_regk +generic map (width => 3, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_tag_d, + dout => rel_tag_q); +rel_way_qsel_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_way_qsel_offset to rel_way_qsel_offset + rel_way_qsel_d'length-1), + scout => sov(rel_way_qsel_offset to rel_way_qsel_offset + rel_way_qsel_d'length-1), + din => rel_way_qsel_d, + dout => rel_way_qsel_q); +rel_val_qsel_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_val_qsel_offset), + scout => sov(rel_val_qsel_offset), + din => rel_val_qsel_d, + dout => rel_val_qsel_q); +rel_way_early_qsel_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_way_early_qsel_offset to rel_way_early_qsel_offset + rel_way_early_qsel_d'length-1), + scout => sov(rel_way_early_qsel_offset to rel_way_early_qsel_offset + rel_way_early_qsel_d'length-1), + din => rel_way_early_qsel_d, + dout => rel_way_early_qsel_q); +rel_val_early_qsel_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_val_early_qsel_offset), + scout => sov(rel_val_early_qsel_offset), + din => rel_val_early_qsel_d, + dout => rel_val_early_qsel_q); +rel4_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel4_val_offset), + scout => sov(rel4_val_offset), + din => rel4_val_d, + dout => rel4_val_q); +rel2_mid_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel2_mid_val_offset), + scout => sov(rel2_mid_val_offset), + din => rel2_mid_val_d, + dout => rel2_mid_val_q); +rel4_retry_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel4_retry_val_offset), + scout => sov(rel4_retry_val_offset), + din => rel4_retry_val_d, + dout => rel4_retry_val_q); +rel2_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel2_fxubyp_val_d, + dout(0) => rel2_fxubyp_val_q); +rel2_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel2_relbyp_val_d, + dout(0) => rel2_relbyp_val_q); +rel2_wlock_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel2_wlock_offset to rel2_wlock_offset + rel2_wlock_d'length-1), + scout => sov(rel2_wlock_offset to rel2_wlock_offset + rel2_wlock_d'length-1), + din => rel2_wlock_d, + dout => rel2_wlock_q); +reld_q0_congr_cl_reg: tri_rlmreg_p +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q0_congr_cl_offset to reld_q0_congr_cl_offset + reld_q0_congr_cl_d'length-1), + scout => sov(reld_q0_congr_cl_offset to reld_q0_congr_cl_offset + reld_q0_congr_cl_d'length-1), + din => reld_q0_congr_cl_d, + dout => reld_q0_congr_cl_q); +reld_q0_way_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q0_way_offset to reld_q0_way_offset + reld_q0_way_d'length-1), + scout => sov(reld_q0_way_offset to reld_q0_way_offset + reld_q0_way_d'length-1), + din => reld_q0_way_d, + dout => reld_q0_way_q); +reld_q0_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q0_val_offset), + scout => sov(reld_q0_val_offset), + din => reld_q0_val_d, + dout => reld_q0_val_q); +reld_q0_lock_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q0_lock_offset), + scout => sov(reld_q0_lock_offset), + din => reld_q0_lock_d, + dout => reld_q0_lock_q); +reld_q1_congr_cl_reg: tri_rlmreg_p +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q1_congr_cl_offset to reld_q1_congr_cl_offset + reld_q1_congr_cl_d'length-1), + scout => sov(reld_q1_congr_cl_offset to reld_q1_congr_cl_offset + reld_q1_congr_cl_d'length-1), + din => reld_q1_congr_cl_d, + dout => reld_q1_congr_cl_q); +reld_q1_way_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q1_way_offset to reld_q1_way_offset + reld_q1_way_d'length-1), + scout => sov(reld_q1_way_offset to reld_q1_way_offset + reld_q1_way_d'length-1), + din => reld_q1_way_d, + dout => reld_q1_way_q); +reld_q1_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q1_val_offset), + scout => sov(reld_q1_val_offset), + din => reld_q1_val_d, + dout => reld_q1_val_q); +reld_q1_lock_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q1_lock_offset), + scout => sov(reld_q1_lock_offset), + din => reld_q1_lock_d, + dout => reld_q1_lock_q); +reld_q2_congr_cl_reg: tri_rlmreg_p +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q2_congr_cl_offset to reld_q2_congr_cl_offset + reld_q2_congr_cl_d'length-1), + scout => sov(reld_q2_congr_cl_offset to reld_q2_congr_cl_offset + reld_q2_congr_cl_d'length-1), + din => reld_q2_congr_cl_d, + dout => reld_q2_congr_cl_q); +reld_q2_way_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q2_way_offset to reld_q2_way_offset + reld_q2_way_d'length-1), + scout => sov(reld_q2_way_offset to reld_q2_way_offset + reld_q2_way_d'length-1), + din => reld_q2_way_d, + dout => reld_q2_way_q); +reld_q2_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q2_val_offset), + scout => sov(reld_q2_val_offset), + din => reld_q2_val_d, + dout => reld_q2_val_q); +reld_q2_lock_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q2_lock_offset), + scout => sov(reld_q2_lock_offset), + din => reld_q2_lock_d, + dout => reld_q2_lock_q); +reld_q3_congr_cl_reg: tri_rlmreg_p +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q3_congr_cl_offset to reld_q3_congr_cl_offset + reld_q3_congr_cl_d'length-1), + scout => sov(reld_q3_congr_cl_offset to reld_q3_congr_cl_offset + reld_q3_congr_cl_d'length-1), + din => reld_q3_congr_cl_d, + dout => reld_q3_congr_cl_q); +reld_q3_way_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q3_way_offset to reld_q3_way_offset + reld_q3_way_d'length-1), + scout => sov(reld_q3_way_offset to reld_q3_way_offset + reld_q3_way_d'length-1), + din => reld_q3_way_d, + dout => reld_q3_way_q); +reld_q3_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q3_val_offset), + scout => sov(reld_q3_val_offset), + din => reld_q3_val_d, + dout => reld_q3_val_q); +reld_q3_lock_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q3_lock_offset), + scout => sov(reld_q3_lock_offset), + din => reld_q3_lock_d, + dout => reld_q3_lock_q); +reld_q4_congr_cl_reg: tri_rlmreg_p +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q4_congr_cl_offset to reld_q4_congr_cl_offset + reld_q4_congr_cl_d'length-1), + scout => sov(reld_q4_congr_cl_offset to reld_q4_congr_cl_offset + reld_q4_congr_cl_d'length-1), + din => reld_q4_congr_cl_d, + dout => reld_q4_congr_cl_q); +reld_q4_way_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q4_way_offset to reld_q4_way_offset + reld_q4_way_d'length-1), + scout => sov(reld_q4_way_offset to reld_q4_way_offset + reld_q4_way_d'length-1), + din => reld_q4_way_d, + dout => reld_q4_way_q); +reld_q4_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q4_val_offset), + scout => sov(reld_q4_val_offset), + din => reld_q4_val_d, + dout => reld_q4_val_q); +reld_q4_lock_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q4_lock_offset), + scout => sov(reld_q4_lock_offset), + din => reld_q4_lock_d, + dout => reld_q4_lock_q); +reld_q5_congr_cl_reg: tri_rlmreg_p +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q5_congr_cl_offset to reld_q5_congr_cl_offset + reld_q5_congr_cl_d'length-1), + scout => sov(reld_q5_congr_cl_offset to reld_q5_congr_cl_offset + reld_q5_congr_cl_d'length-1), + din => reld_q5_congr_cl_d, + dout => reld_q5_congr_cl_q); +reld_q5_way_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q5_way_offset to reld_q5_way_offset + reld_q5_way_d'length-1), + scout => sov(reld_q5_way_offset to reld_q5_way_offset + reld_q5_way_d'length-1), + din => reld_q5_way_d, + dout => reld_q5_way_q); +reld_q5_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q5_val_offset), + scout => sov(reld_q5_val_offset), + din => reld_q5_val_d, + dout => reld_q5_val_q); +reld_q5_lock_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q5_lock_offset), + scout => sov(reld_q5_lock_offset), + din => reld_q5_lock_d, + dout => reld_q5_lock_q); +reld_q6_congr_cl_reg: tri_rlmreg_p +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q6_congr_cl_offset to reld_q6_congr_cl_offset + reld_q6_congr_cl_d'length-1), + scout => sov(reld_q6_congr_cl_offset to reld_q6_congr_cl_offset + reld_q6_congr_cl_d'length-1), + din => reld_q6_congr_cl_d, + dout => reld_q6_congr_cl_q); +reld_q6_way_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q6_way_offset to reld_q6_way_offset + reld_q6_way_d'length-1), + scout => sov(reld_q6_way_offset to reld_q6_way_offset + reld_q6_way_d'length-1), + din => reld_q6_way_d, + dout => reld_q6_way_q); +reld_q6_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q6_val_offset), + scout => sov(reld_q6_val_offset), + din => reld_q6_val_d, + dout => reld_q6_val_q); +reld_q6_lock_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q6_lock_offset), + scout => sov(reld_q6_lock_offset), + din => reld_q6_lock_d, + dout => reld_q6_lock_q); +reld_q7_congr_cl_reg: tri_rlmreg_p +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q7_congr_cl_offset to reld_q7_congr_cl_offset + reld_q7_congr_cl_d'length-1), + scout => sov(reld_q7_congr_cl_offset to reld_q7_congr_cl_offset + reld_q7_congr_cl_d'length-1), + din => reld_q7_congr_cl_d, + dout => reld_q7_congr_cl_q); +reld_q7_way_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q7_way_offset to reld_q7_way_offset + reld_q7_way_d'length-1), + scout => sov(reld_q7_way_offset to reld_q7_way_offset + reld_q7_way_d'length-1), + din => reld_q7_way_d, + dout => reld_q7_way_q); +reld_q7_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q7_val_offset), + scout => sov(reld_q7_val_offset), + din => reld_q7_val_d, + dout => reld_q7_val_q); +reld_q7_lock_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q7_lock_offset), + scout => sov(reld_q7_lock_offset), + din => reld_q7_lock_d, + dout => reld_q7_lock_q); +rel_m_q_way_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_m_q_way_offset to rel_m_q_way_offset + rel_m_q_way_d'length-1), + scout => sov(rel_m_q_way_offset to rel_m_q_way_offset + rel_m_q_way_d'length-1), + din => rel_m_q_way_d, + dout => rel_m_q_way_q); +ex3_no_lru_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_no_lru_upd_offset), + scout => sov(ex3_no_lru_upd_offset), + din => ex3_no_lru_upd_d, + dout => ex3_no_lru_upd_q); +rel2_lock_en_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel2_lock_en_offset), + scout => sov(rel2_lock_en_offset), + din => rel2_lock_en_d, + dout => rel2_lock_en_q); +xucr0_clo_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xucr0_clo_offset), + scout => sov(xucr0_clo_offset), + din => xucr0_clo_d, + dout => xucr0_clo_q); +rel_up_way_addr_reg: tri_rlmreg_p +generic map (width => 3, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_up_way_addr_offset to rel_up_way_addr_offset + rel_up_way_addr_d'length-1), + scout => sov(rel_up_way_addr_offset to rel_up_way_addr_offset + rel_up_way_addr_d'length-1), + din => rel_up_way_addr_d, + dout => rel_up_way_addr_q); +rel24_way_dwen_stg_reg: tri_regk +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel24_way_dwen_stg_d, + dout => rel24_way_dwen_stg_q); +rel_dcarr_addr_en_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_dcarr_addr_en_offset), + scout => sov(rel_dcarr_addr_en_offset), + din => rel_dcarr_addr_en_d, + dout => rel_dcarr_addr_en_q); +rel_dcarr_val_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_dcarr_val_upd_offset), + scout => sov(rel_dcarr_val_upd_offset), + din => rel_dcarr_val_upd_d, + dout => rel_dcarr_val_upd_q); +congr_cl_ex3_ex4_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex3_ex4_cmp_offset), + scout => sov(congr_cl_ex3_ex4_cmp_offset), + din => congr_cl_ex3_ex4_cmp_d, + dout => congr_cl_ex3_ex4_cmp_q); +congr_cl_ex3_ex5_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex3_ex5_cmp_offset), + scout => sov(congr_cl_ex3_ex5_cmp_offset), + din => congr_cl_ex3_ex5_cmp_d, + dout => congr_cl_ex3_ex5_cmp_q); +congr_cl_ex3_ex6_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex3_ex6_cmp_offset), + scout => sov(congr_cl_ex3_ex6_cmp_offset), + din => congr_cl_ex3_ex6_cmp_d, + dout => congr_cl_ex3_ex6_cmp_q); +congr_cl_ex3_rel2_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex3_rel2_cmp_offset), + scout => sov(congr_cl_ex3_rel2_cmp_offset), + din => congr_cl_ex3_rel2_cmp_d, + dout => congr_cl_ex3_rel2_cmp_q); +congr_cl_ex3_rel_upd_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex3_rel_upd_cmp_offset), + scout => sov(congr_cl_ex3_rel_upd_cmp_offset), + din => congr_cl_ex3_rel_upd_cmp_d, + dout => congr_cl_ex3_rel_upd_cmp_q); +congr_cl_rel1_ex4_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_rel1_ex4_cmp_offset), + scout => sov(congr_cl_rel1_ex4_cmp_offset), + din => congr_cl_rel1_ex4_cmp_d, + dout => congr_cl_rel1_ex4_cmp_q); +congr_cl_rel1_ex5_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_rel1_ex5_cmp_offset), + scout => sov(congr_cl_rel1_ex5_cmp_offset), + din => congr_cl_rel1_ex5_cmp_d, + dout => congr_cl_rel1_ex5_cmp_q); +congr_cl_rel1_ex6_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_rel1_ex6_cmp_offset), + scout => sov(congr_cl_rel1_ex6_cmp_offset), + din => congr_cl_rel1_ex6_cmp_d, + dout => congr_cl_rel1_ex6_cmp_q); +congr_cl_rel1_rel2_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_rel1_rel2_cmp_offset), + scout => sov(congr_cl_rel1_rel2_cmp_offset), + din => congr_cl_rel1_rel2_cmp_d, + dout => congr_cl_rel1_rel2_cmp_q); +congr_cl_rel1_relu_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_rel1_relu_cmp_offset), + scout => sov(congr_cl_rel1_relu_cmp_offset), + din => congr_cl_rel1_relu_cmp_d, + dout => congr_cl_rel1_relu_cmp_q); +congr_cl_rel1_rel_upd_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_rel1_rel_upd_cmp_offset), + scout => sov(congr_cl_rel1_rel_upd_cmp_offset), + din => congr_cl_rel1_rel_upd_cmp_d, + dout => congr_cl_rel1_rel_upd_cmp_q); +congr_cl_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_act_offset), + scout => sov(congr_cl_act_offset), + din => congr_cl_act_d, + dout => congr_cl_act_q); +siv(0 TO scan_right) <= sov(1 to scan_right) & scan_in; +scan_out <= sov(0); +END XUQ_LSU_DIR_LRU16; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_dir_lru32.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_dir_lru32.vhdl new file mode 100644 index 0000000..0314b5b --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_dir_lru32.vhdl @@ -0,0 +1,4961 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ibm, ieee, work, tri, support; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use tri.tri_latches_pkg.all; +use support.power_logic_pkg.all; + +entity xuq_lsu_dir_lru32 is +generic(expand_type : integer := 2; + dc_size : natural := 15; + lmq_entries : integer := 8; + cl_size : natural := 6); +port( + + ex1_stg_act :in std_ulogic; + ex2_stg_act :in std_ulogic; + ex3_stg_act :in std_ulogic; + ex4_stg_act :in std_ulogic; + ex5_stg_act :in std_ulogic; + rel1_stg_act :in std_ulogic; + rel2_stg_act :in std_ulogic; + rel3_stg_act :in std_ulogic; + + rel1_val :in std_ulogic; + rel1_classid :in std_ulogic_vector(0 to 1); + rel_mid_val :in std_ulogic; + rel_retry_val :in std_ulogic; + rel3_val :in std_ulogic; + rel4_recirc_val :in std_ulogic; + rel4_ecc_err :in std_ulogic; + rel_st_tag_early :in std_ulogic_vector(1 to 3); + rel_st_tag :in std_ulogic_vector(1 to 3); + rel_addr_early :in std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + rel_lock_en :in std_ulogic; + + rel_way_val_a :in std_ulogic; + rel_way_val_b :in std_ulogic; + rel_way_val_c :in std_ulogic; + rel_way_val_d :in std_ulogic; + rel_way_val_e :in std_ulogic; + rel_way_val_f :in std_ulogic; + rel_way_val_g :in std_ulogic; + rel_way_val_h :in std_ulogic; + + rel_way_lock_a :in std_ulogic; + rel_way_lock_b :in std_ulogic; + rel_way_lock_c :in std_ulogic; + rel_way_lock_d :in std_ulogic; + rel_way_lock_e :in std_ulogic; + rel_way_lock_f :in std_ulogic; + rel_way_lock_g :in std_ulogic; + rel_way_lock_h :in std_ulogic; + + ex1_p_addr :in std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + ex3_cache_en :in std_ulogic; + ex2_no_lru_upd :in std_ulogic; + + ex4_way_a_hit :in std_ulogic; + ex4_way_b_hit :in std_ulogic; + ex4_way_c_hit :in std_ulogic; + ex4_way_d_hit :in std_ulogic; + ex4_way_e_hit :in std_ulogic; + ex4_way_f_hit :in std_ulogic; + ex4_way_g_hit :in std_ulogic; + ex4_way_h_hit :in std_ulogic; + ex3_hit :in std_ulogic; + + spr_xucr2_rmt :in std_ulogic_vector(0 to 31); + spr_xucr0_wlck :in std_ulogic; + spr_xucr0_dcdis :in std_ulogic; + spr_xucr0_cls :in std_ulogic; + + ex3_stg_flush :in std_ulogic; + ex4_stg_flush :in std_ulogic; + ex5_stg_flush :in std_ulogic; + + rel_way_upd_a :out std_ulogic; + rel_way_upd_b :out std_ulogic; + rel_way_upd_c :out std_ulogic; + rel_way_upd_d :out std_ulogic; + rel_way_upd_e :out std_ulogic; + rel_way_upd_f :out std_ulogic; + rel_way_upd_g :out std_ulogic; + rel_way_upd_h :out std_ulogic; + + rel_way_wen_a :out std_ulogic; + rel_way_wen_b :out std_ulogic; + rel_way_wen_c :out std_ulogic; + rel_way_wen_d :out std_ulogic; + rel_way_wen_e :out std_ulogic; + rel_way_wen_f :out std_ulogic; + rel_way_wen_g :out std_ulogic; + rel_way_wen_h :out std_ulogic; + + rel_way_clr_a :out std_ulogic; + rel_way_clr_b :out std_ulogic; + rel_way_clr_c :out std_ulogic; + rel_way_clr_d :out std_ulogic; + rel_way_clr_e :out std_ulogic; + rel_way_clr_f :out std_ulogic; + rel_way_clr_g :out std_ulogic; + rel_way_clr_h :out std_ulogic; + rel_dcarr_val_upd :out std_ulogic; + rel_up_way_addr_b :out std_ulogic_vector(0 to 2); + rel_dcarr_addr_en :out std_ulogic; + + lsu_xu_spr_xucr0_clo :out std_ulogic; + + ex4_dir_lru :out std_ulogic_vector(0 to 6); + + dc_lru_dbg_data :out std_ulogic_vector(0 to 81); + + vdd :inout power_logic; + gnd :inout power_logic; + nclk :in clk_logic; + sg_0 :in std_ulogic; + func_sl_thold_0_b :in std_ulogic; + func_sl_force :in std_ulogic; + func_nsl_thold_0_b :in std_ulogic; + func_nsl_force :in std_ulogic; + d_mode_dc :in std_ulogic; + delay_lclkr_dc :in std_ulogic; + mpw1_dc_b :in std_ulogic; + mpw2_dc_b :in std_ulogic; + scan_in :in std_ulogic; + scan_out :out std_ulogic + ); +-- synopsys translate_off +-- synopsys translate_on +end xuq_lsu_dir_lru32; +ARCHITECTURE XUQ_LSU_DIR_LRU32 + OF XUQ_LSU_DIR_LRU32 + IS +constant congr_cl0_lru_offset :natural := 0; +constant congr_cl1_lru_offset :natural := congr_cl0_lru_offset + 7; +constant congr_cl2_lru_offset :natural := congr_cl1_lru_offset + 7; +constant congr_cl3_lru_offset :natural := congr_cl2_lru_offset + 7; +constant congr_cl4_lru_offset :natural := congr_cl3_lru_offset + 7; +constant congr_cl5_lru_offset :natural := congr_cl4_lru_offset + 7; +constant congr_cl6_lru_offset :natural := congr_cl5_lru_offset + 7; +constant congr_cl7_lru_offset :natural := congr_cl6_lru_offset + 7; +constant congr_cl8_lru_offset :natural := congr_cl7_lru_offset + 7; +constant congr_cl9_lru_offset :natural := congr_cl8_lru_offset + 7; +constant congr_cl10_lru_offset :natural := congr_cl9_lru_offset + 7; +constant congr_cl11_lru_offset :natural := congr_cl10_lru_offset + 7; +constant congr_cl12_lru_offset :natural := congr_cl11_lru_offset + 7; +constant congr_cl13_lru_offset :natural := congr_cl12_lru_offset + 7; +constant congr_cl14_lru_offset :natural := congr_cl13_lru_offset + 7; +constant congr_cl15_lru_offset :natural := congr_cl14_lru_offset + 7; +constant congr_cl16_lru_offset :natural := congr_cl15_lru_offset + 7; +constant congr_cl17_lru_offset :natural := congr_cl16_lru_offset + 7; +constant congr_cl18_lru_offset :natural := congr_cl17_lru_offset + 7; +constant congr_cl19_lru_offset :natural := congr_cl18_lru_offset + 7; +constant congr_cl20_lru_offset :natural := congr_cl19_lru_offset + 7; +constant congr_cl21_lru_offset :natural := congr_cl20_lru_offset + 7; +constant congr_cl22_lru_offset :natural := congr_cl21_lru_offset + 7; +constant congr_cl23_lru_offset :natural := congr_cl22_lru_offset + 7; +constant congr_cl24_lru_offset :natural := congr_cl23_lru_offset + 7; +constant congr_cl25_lru_offset :natural := congr_cl24_lru_offset + 7; +constant congr_cl26_lru_offset :natural := congr_cl25_lru_offset + 7; +constant congr_cl27_lru_offset :natural := congr_cl26_lru_offset + 7; +constant congr_cl28_lru_offset :natural := congr_cl27_lru_offset + 7; +constant congr_cl29_lru_offset :natural := congr_cl28_lru_offset + 7; +constant congr_cl30_lru_offset :natural := congr_cl29_lru_offset + 7; +constant congr_cl31_lru_offset :natural := congr_cl30_lru_offset + 7; +constant congr_cl32_lru_offset :natural := congr_cl31_lru_offset + 7; +constant congr_cl33_lru_offset :natural := congr_cl32_lru_offset + 7; +constant congr_cl34_lru_offset :natural := congr_cl33_lru_offset + 7; +constant congr_cl35_lru_offset :natural := congr_cl34_lru_offset + 7; +constant congr_cl36_lru_offset :natural := congr_cl35_lru_offset + 7; +constant congr_cl37_lru_offset :natural := congr_cl36_lru_offset + 7; +constant congr_cl38_lru_offset :natural := congr_cl37_lru_offset + 7; +constant congr_cl39_lru_offset :natural := congr_cl38_lru_offset + 7; +constant congr_cl40_lru_offset :natural := congr_cl39_lru_offset + 7; +constant congr_cl41_lru_offset :natural := congr_cl40_lru_offset + 7; +constant congr_cl42_lru_offset :natural := congr_cl41_lru_offset + 7; +constant congr_cl43_lru_offset :natural := congr_cl42_lru_offset + 7; +constant congr_cl44_lru_offset :natural := congr_cl43_lru_offset + 7; +constant congr_cl45_lru_offset :natural := congr_cl44_lru_offset + 7; +constant congr_cl46_lru_offset :natural := congr_cl45_lru_offset + 7; +constant congr_cl47_lru_offset :natural := congr_cl46_lru_offset + 7; +constant congr_cl48_lru_offset :natural := congr_cl47_lru_offset + 7; +constant congr_cl49_lru_offset :natural := congr_cl48_lru_offset + 7; +constant congr_cl50_lru_offset :natural := congr_cl49_lru_offset + 7; +constant congr_cl51_lru_offset :natural := congr_cl50_lru_offset + 7; +constant congr_cl52_lru_offset :natural := congr_cl51_lru_offset + 7; +constant congr_cl53_lru_offset :natural := congr_cl52_lru_offset + 7; +constant congr_cl54_lru_offset :natural := congr_cl53_lru_offset + 7; +constant congr_cl55_lru_offset :natural := congr_cl54_lru_offset + 7; +constant congr_cl56_lru_offset :natural := congr_cl55_lru_offset + 7; +constant congr_cl57_lru_offset :natural := congr_cl56_lru_offset + 7; +constant congr_cl58_lru_offset :natural := congr_cl57_lru_offset + 7; +constant congr_cl59_lru_offset :natural := congr_cl58_lru_offset + 7; +constant congr_cl60_lru_offset :natural := congr_cl59_lru_offset + 7; +constant congr_cl61_lru_offset :natural := congr_cl60_lru_offset + 7; +constant congr_cl62_lru_offset :natural := congr_cl61_lru_offset + 7; +constant congr_cl63_lru_offset :natural := congr_cl62_lru_offset + 7; +constant congr_cl_lru_b_offset :natural := congr_cl63_lru_offset + 7; +constant rel_congr_cl_lru_b_offset :natural := congr_cl_lru_b_offset + 7; +constant reld_q_sel_offset :natural := rel_congr_cl_lru_b_offset + 7; +constant ex5_congr_cl_offset :natural := reld_q_sel_offset + 8; +constant rel_congr_cl_offset :natural := ex5_congr_cl_offset + 6; +constant relu_congr_cl_offset :natural := rel_congr_cl_offset + 6; +constant ex5_lru_upd_offset :natural := relu_congr_cl_offset + 6; +constant rel2_val_offset :natural := ex5_lru_upd_offset + 7; +constant relu_val_wen_offset :natural := rel2_val_offset + 1; +constant ex4_hit_offset :natural := relu_val_wen_offset + 1; +constant ex4_c_acc_offset :natural := ex4_hit_offset + 1; +constant ex5_c_acc_offset :natural := ex4_c_acc_offset + 1; +constant ex6_c_acc_val_offset :natural := ex5_c_acc_offset + 1; +constant ex3_congr_cl_offset :natural := ex6_c_acc_val_offset + 1; +constant rel_val_wen_offset :natural := ex3_congr_cl_offset + 6; +constant relu_lru_upd_offset :natural := rel_val_wen_offset + 1; +constant rel_way_qsel_offset :natural := relu_lru_upd_offset + 7; +constant rel_val_qsel_offset :natural := rel_way_qsel_offset + 8; +constant rel_way_early_qsel_offset :natural := rel_val_qsel_offset + 1; +constant rel_val_early_qsel_offset :natural := rel_way_early_qsel_offset + 8; +constant rel4_val_offset :natural := rel_val_early_qsel_offset + 1; +constant rel2_mid_val_offset :natural := rel4_val_offset + 1; +constant rel4_retry_val_offset :natural := rel2_mid_val_offset + 1; +constant rel2_wlock_offset :natural := rel4_retry_val_offset + 1; +constant reld_q0_congr_cl_offset :natural := rel2_wlock_offset + 8; +constant reld_q1_congr_cl_offset :natural := reld_q0_congr_cl_offset + 6; +constant reld_q2_congr_cl_offset :natural := reld_q1_congr_cl_offset + 6; +constant reld_q3_congr_cl_offset :natural := reld_q2_congr_cl_offset + 6; +constant reld_q4_congr_cl_offset :natural := reld_q3_congr_cl_offset + 6; +constant reld_q5_congr_cl_offset :natural := reld_q4_congr_cl_offset + 6; +constant reld_q6_congr_cl_offset :natural := reld_q5_congr_cl_offset + 6; +constant reld_q7_congr_cl_offset :natural := reld_q6_congr_cl_offset + 6; +constant reld_q0_way_offset :natural := reld_q7_congr_cl_offset + 6; +constant reld_q1_way_offset :natural := reld_q0_way_offset + 8; +constant reld_q2_way_offset :natural := reld_q1_way_offset + 8; +constant reld_q3_way_offset :natural := reld_q2_way_offset + 8; +constant reld_q4_way_offset :natural := reld_q3_way_offset + 8; +constant reld_q5_way_offset :natural := reld_q4_way_offset + 8; +constant reld_q6_way_offset :natural := reld_q5_way_offset + 8; +constant reld_q7_way_offset :natural := reld_q6_way_offset + 8; +constant reld_q0_val_offset :natural := reld_q7_way_offset + 8; +constant reld_q1_val_offset :natural := reld_q0_val_offset + 1; +constant reld_q2_val_offset :natural := reld_q1_val_offset + 1; +constant reld_q3_val_offset :natural := reld_q2_val_offset + 1; +constant reld_q4_val_offset :natural := reld_q3_val_offset + 1; +constant reld_q5_val_offset :natural := reld_q4_val_offset + 1; +constant reld_q6_val_offset :natural := reld_q5_val_offset + 1; +constant reld_q7_val_offset :natural := reld_q6_val_offset + 1; +constant reld_q0_lock_offset :natural := reld_q7_val_offset + 1; +constant reld_q1_lock_offset :natural := reld_q0_lock_offset + 1; +constant reld_q2_lock_offset :natural := reld_q1_lock_offset + 1; +constant reld_q3_lock_offset :natural := reld_q2_lock_offset + 1; +constant reld_q4_lock_offset :natural := reld_q3_lock_offset + 1; +constant reld_q5_lock_offset :natural := reld_q4_lock_offset + 1; +constant reld_q6_lock_offset :natural := reld_q5_lock_offset + 1; +constant reld_q7_lock_offset :natural := reld_q6_lock_offset + 1; +constant rel_m_q_way_offset :natural := reld_q7_lock_offset + 1; +constant ex3_no_lru_upd_offset :natural := rel_m_q_way_offset + 8; +constant rel2_lock_en_offset :natural := ex3_no_lru_upd_offset + 1; +constant xucr0_clo_offset :natural := rel2_lock_en_offset + 1; +constant rel_up_way_addr_offset :natural := xucr0_clo_offset + 1; +constant rel_dcarr_addr_en_offset :natural := rel_up_way_addr_offset + 3; +constant rel_dcarr_val_upd_offset :natural := rel_dcarr_addr_en_offset + 1; +constant congr_cl_ex3_ex4_cmp_offset :natural := rel_dcarr_val_upd_offset + 1; +constant congr_cl_ex3_ex5_cmp_offset :natural := congr_cl_ex3_ex4_cmp_offset + 1; +constant congr_cl_ex3_ex6_cmp_offset :natural := congr_cl_ex3_ex5_cmp_offset + 1; +constant congr_cl_ex3_rel2_cmp_offset :natural := congr_cl_ex3_ex6_cmp_offset + 1; +constant congr_cl_ex3_rel_upd_cmp_offset :natural := congr_cl_ex3_rel2_cmp_offset + 1; +constant congr_cl_rel1_ex4_cmp_offset :natural := congr_cl_ex3_rel_upd_cmp_offset + 1; +constant congr_cl_rel1_ex5_cmp_offset :natural := congr_cl_rel1_ex4_cmp_offset + 1; +constant congr_cl_rel1_ex6_cmp_offset :natural := congr_cl_rel1_ex5_cmp_offset + 1; +constant congr_cl_rel1_rel2_cmp_offset :natural := congr_cl_rel1_ex6_cmp_offset + 1; +constant congr_cl_rel1_relu_cmp_offset :natural := congr_cl_rel1_rel2_cmp_offset + 1; +constant congr_cl_rel1_rel_upd_cmp_offset :natural := congr_cl_rel1_relu_cmp_offset + 1; +constant congr_cl_act_offset :natural := congr_cl_rel1_rel_upd_cmp_offset + 1; +constant scan_right :natural := congr_cl_act_offset + 1 - 1; +signal congr_cl0_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl0_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl0_lru_wen :std_ulogic; +signal xu_op_cl0_lru_wen :std_ulogic; +signal rel_cl0_lru_wen :std_ulogic; +signal rel_ldst_cl0_lru :std_ulogic_vector(0 to 6); +signal congr_cl1_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl1_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl1_lru_wen :std_ulogic; +signal xu_op_cl1_lru_wen :std_ulogic; +signal rel_cl1_lru_wen :std_ulogic; +signal rel_ldst_cl1_lru :std_ulogic_vector(0 to 6); +signal congr_cl2_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl2_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl2_lru_wen :std_ulogic; +signal xu_op_cl2_lru_wen :std_ulogic; +signal rel_cl2_lru_wen :std_ulogic; +signal rel_ldst_cl2_lru :std_ulogic_vector(0 to 6); +signal congr_cl3_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl3_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl3_lru_wen :std_ulogic; +signal xu_op_cl3_lru_wen :std_ulogic; +signal rel_cl3_lru_wen :std_ulogic; +signal rel_ldst_cl3_lru :std_ulogic_vector(0 to 6); +signal congr_cl4_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl4_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl4_lru_wen :std_ulogic; +signal xu_op_cl4_lru_wen :std_ulogic; +signal rel_cl4_lru_wen :std_ulogic; +signal rel_ldst_cl4_lru :std_ulogic_vector(0 to 6); +signal congr_cl5_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl5_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl5_lru_wen :std_ulogic; +signal xu_op_cl5_lru_wen :std_ulogic; +signal rel_cl5_lru_wen :std_ulogic; +signal rel_ldst_cl5_lru :std_ulogic_vector(0 to 6); +signal congr_cl6_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl6_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl6_lru_wen :std_ulogic; +signal xu_op_cl6_lru_wen :std_ulogic; +signal rel_cl6_lru_wen :std_ulogic; +signal rel_ldst_cl6_lru :std_ulogic_vector(0 to 6); +signal congr_cl7_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl7_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl7_lru_wen :std_ulogic; +signal xu_op_cl7_lru_wen :std_ulogic; +signal rel_cl7_lru_wen :std_ulogic; +signal rel_ldst_cl7_lru :std_ulogic_vector(0 to 6); +signal congr_cl8_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl8_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl8_lru_wen :std_ulogic; +signal xu_op_cl8_lru_wen :std_ulogic; +signal rel_cl8_lru_wen :std_ulogic; +signal rel_ldst_cl8_lru :std_ulogic_vector(0 to 6); +signal congr_cl9_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl9_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl9_lru_wen :std_ulogic; +signal xu_op_cl9_lru_wen :std_ulogic; +signal rel_cl9_lru_wen :std_ulogic; +signal rel_ldst_cl9_lru :std_ulogic_vector(0 to 6); +signal congr_cl10_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl10_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl10_lru_wen :std_ulogic; +signal xu_op_cl10_lru_wen :std_ulogic; +signal rel_cl10_lru_wen :std_ulogic; +signal rel_ldst_cl10_lru :std_ulogic_vector(0 to 6); +signal congr_cl11_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl11_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl11_lru_wen :std_ulogic; +signal xu_op_cl11_lru_wen :std_ulogic; +signal rel_cl11_lru_wen :std_ulogic; +signal rel_ldst_cl11_lru :std_ulogic_vector(0 to 6); +signal congr_cl12_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl12_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl12_lru_wen :std_ulogic; +signal xu_op_cl12_lru_wen :std_ulogic; +signal rel_cl12_lru_wen :std_ulogic; +signal rel_ldst_cl12_lru :std_ulogic_vector(0 to 6); +signal congr_cl13_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl13_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl13_lru_wen :std_ulogic; +signal xu_op_cl13_lru_wen :std_ulogic; +signal rel_cl13_lru_wen :std_ulogic; +signal rel_ldst_cl13_lru :std_ulogic_vector(0 to 6); +signal congr_cl14_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl14_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl14_lru_wen :std_ulogic; +signal xu_op_cl14_lru_wen :std_ulogic; +signal rel_cl14_lru_wen :std_ulogic; +signal rel_ldst_cl14_lru :std_ulogic_vector(0 to 6); +signal congr_cl15_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl15_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl15_lru_wen :std_ulogic; +signal xu_op_cl15_lru_wen :std_ulogic; +signal rel_cl15_lru_wen :std_ulogic; +signal rel_ldst_cl15_lru :std_ulogic_vector(0 to 6); +signal congr_cl16_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl16_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl16_lru_wen :std_ulogic; +signal xu_op_cl16_lru_wen :std_ulogic; +signal rel_cl16_lru_wen :std_ulogic; +signal rel_ldst_cl16_lru :std_ulogic_vector(0 to 6); +signal congr_cl17_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl17_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl17_lru_wen :std_ulogic; +signal xu_op_cl17_lru_wen :std_ulogic; +signal rel_cl17_lru_wen :std_ulogic; +signal rel_ldst_cl17_lru :std_ulogic_vector(0 to 6); +signal congr_cl18_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl18_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl18_lru_wen :std_ulogic; +signal xu_op_cl18_lru_wen :std_ulogic; +signal rel_cl18_lru_wen :std_ulogic; +signal rel_ldst_cl18_lru :std_ulogic_vector(0 to 6); +signal congr_cl19_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl19_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl19_lru_wen :std_ulogic; +signal xu_op_cl19_lru_wen :std_ulogic; +signal rel_cl19_lru_wen :std_ulogic; +signal rel_ldst_cl19_lru :std_ulogic_vector(0 to 6); +signal congr_cl20_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl20_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl20_lru_wen :std_ulogic; +signal xu_op_cl20_lru_wen :std_ulogic; +signal rel_cl20_lru_wen :std_ulogic; +signal rel_ldst_cl20_lru :std_ulogic_vector(0 to 6); +signal congr_cl21_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl21_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl21_lru_wen :std_ulogic; +signal xu_op_cl21_lru_wen :std_ulogic; +signal rel_cl21_lru_wen :std_ulogic; +signal rel_ldst_cl21_lru :std_ulogic_vector(0 to 6); +signal congr_cl22_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl22_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl22_lru_wen :std_ulogic; +signal xu_op_cl22_lru_wen :std_ulogic; +signal rel_cl22_lru_wen :std_ulogic; +signal rel_ldst_cl22_lru :std_ulogic_vector(0 to 6); +signal congr_cl23_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl23_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl23_lru_wen :std_ulogic; +signal xu_op_cl23_lru_wen :std_ulogic; +signal rel_cl23_lru_wen :std_ulogic; +signal rel_ldst_cl23_lru :std_ulogic_vector(0 to 6); +signal congr_cl24_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl24_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl24_lru_wen :std_ulogic; +signal xu_op_cl24_lru_wen :std_ulogic; +signal rel_cl24_lru_wen :std_ulogic; +signal rel_ldst_cl24_lru :std_ulogic_vector(0 to 6); +signal congr_cl25_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl25_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl25_lru_wen :std_ulogic; +signal xu_op_cl25_lru_wen :std_ulogic; +signal rel_cl25_lru_wen :std_ulogic; +signal rel_ldst_cl25_lru :std_ulogic_vector(0 to 6); +signal congr_cl26_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl26_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl26_lru_wen :std_ulogic; +signal xu_op_cl26_lru_wen :std_ulogic; +signal rel_cl26_lru_wen :std_ulogic; +signal rel_ldst_cl26_lru :std_ulogic_vector(0 to 6); +signal congr_cl27_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl27_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl27_lru_wen :std_ulogic; +signal xu_op_cl27_lru_wen :std_ulogic; +signal rel_cl27_lru_wen :std_ulogic; +signal rel_ldst_cl27_lru :std_ulogic_vector(0 to 6); +signal congr_cl28_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl28_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl28_lru_wen :std_ulogic; +signal xu_op_cl28_lru_wen :std_ulogic; +signal rel_cl28_lru_wen :std_ulogic; +signal rel_ldst_cl28_lru :std_ulogic_vector(0 to 6); +signal congr_cl29_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl29_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl29_lru_wen :std_ulogic; +signal xu_op_cl29_lru_wen :std_ulogic; +signal rel_cl29_lru_wen :std_ulogic; +signal rel_ldst_cl29_lru :std_ulogic_vector(0 to 6); +signal congr_cl30_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl30_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl30_lru_wen :std_ulogic; +signal xu_op_cl30_lru_wen :std_ulogic; +signal rel_cl30_lru_wen :std_ulogic; +signal rel_ldst_cl30_lru :std_ulogic_vector(0 to 6); +signal congr_cl31_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl31_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl31_lru_wen :std_ulogic; +signal xu_op_cl31_lru_wen :std_ulogic; +signal rel_cl31_lru_wen :std_ulogic; +signal rel_ldst_cl31_lru :std_ulogic_vector(0 to 6); +signal congr_cl32_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl32_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl32_lru_wen :std_ulogic; +signal xu_op_cl32_lru_wen :std_ulogic; +signal rel_cl32_lru_wen :std_ulogic; +signal rel_ldst_cl32_lru :std_ulogic_vector(0 to 6); +signal congr_cl33_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl33_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl33_lru_wen :std_ulogic; +signal xu_op_cl33_lru_wen :std_ulogic; +signal rel_cl33_lru_wen :std_ulogic; +signal rel_ldst_cl33_lru :std_ulogic_vector(0 to 6); +signal congr_cl34_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl34_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl34_lru_wen :std_ulogic; +signal xu_op_cl34_lru_wen :std_ulogic; +signal rel_cl34_lru_wen :std_ulogic; +signal rel_ldst_cl34_lru :std_ulogic_vector(0 to 6); +signal congr_cl35_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl35_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl35_lru_wen :std_ulogic; +signal xu_op_cl35_lru_wen :std_ulogic; +signal rel_cl35_lru_wen :std_ulogic; +signal rel_ldst_cl35_lru :std_ulogic_vector(0 to 6); +signal congr_cl36_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl36_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl36_lru_wen :std_ulogic; +signal xu_op_cl36_lru_wen :std_ulogic; +signal rel_cl36_lru_wen :std_ulogic; +signal rel_ldst_cl36_lru :std_ulogic_vector(0 to 6); +signal congr_cl37_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl37_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl37_lru_wen :std_ulogic; +signal xu_op_cl37_lru_wen :std_ulogic; +signal rel_cl37_lru_wen :std_ulogic; +signal rel_ldst_cl37_lru :std_ulogic_vector(0 to 6); +signal congr_cl38_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl38_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl38_lru_wen :std_ulogic; +signal xu_op_cl38_lru_wen :std_ulogic; +signal rel_cl38_lru_wen :std_ulogic; +signal rel_ldst_cl38_lru :std_ulogic_vector(0 to 6); +signal congr_cl39_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl39_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl39_lru_wen :std_ulogic; +signal xu_op_cl39_lru_wen :std_ulogic; +signal rel_cl39_lru_wen :std_ulogic; +signal rel_ldst_cl39_lru :std_ulogic_vector(0 to 6); +signal congr_cl40_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl40_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl40_lru_wen :std_ulogic; +signal xu_op_cl40_lru_wen :std_ulogic; +signal rel_cl40_lru_wen :std_ulogic; +signal rel_ldst_cl40_lru :std_ulogic_vector(0 to 6); +signal congr_cl41_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl41_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl41_lru_wen :std_ulogic; +signal xu_op_cl41_lru_wen :std_ulogic; +signal rel_cl41_lru_wen :std_ulogic; +signal rel_ldst_cl41_lru :std_ulogic_vector(0 to 6); +signal congr_cl42_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl42_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl42_lru_wen :std_ulogic; +signal xu_op_cl42_lru_wen :std_ulogic; +signal rel_cl42_lru_wen :std_ulogic; +signal rel_ldst_cl42_lru :std_ulogic_vector(0 to 6); +signal congr_cl43_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl43_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl43_lru_wen :std_ulogic; +signal xu_op_cl43_lru_wen :std_ulogic; +signal rel_cl43_lru_wen :std_ulogic; +signal rel_ldst_cl43_lru :std_ulogic_vector(0 to 6); +signal congr_cl44_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl44_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl44_lru_wen :std_ulogic; +signal xu_op_cl44_lru_wen :std_ulogic; +signal rel_cl44_lru_wen :std_ulogic; +signal rel_ldst_cl44_lru :std_ulogic_vector(0 to 6); +signal congr_cl45_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl45_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl45_lru_wen :std_ulogic; +signal xu_op_cl45_lru_wen :std_ulogic; +signal rel_cl45_lru_wen :std_ulogic; +signal rel_ldst_cl45_lru :std_ulogic_vector(0 to 6); +signal congr_cl46_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl46_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl46_lru_wen :std_ulogic; +signal xu_op_cl46_lru_wen :std_ulogic; +signal rel_cl46_lru_wen :std_ulogic; +signal rel_ldst_cl46_lru :std_ulogic_vector(0 to 6); +signal congr_cl47_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl47_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl47_lru_wen :std_ulogic; +signal xu_op_cl47_lru_wen :std_ulogic; +signal rel_cl47_lru_wen :std_ulogic; +signal rel_ldst_cl47_lru :std_ulogic_vector(0 to 6); +signal congr_cl48_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl48_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl48_lru_wen :std_ulogic; +signal xu_op_cl48_lru_wen :std_ulogic; +signal rel_cl48_lru_wen :std_ulogic; +signal rel_ldst_cl48_lru :std_ulogic_vector(0 to 6); +signal congr_cl49_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl49_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl49_lru_wen :std_ulogic; +signal xu_op_cl49_lru_wen :std_ulogic; +signal rel_cl49_lru_wen :std_ulogic; +signal rel_ldst_cl49_lru :std_ulogic_vector(0 to 6); +signal congr_cl50_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl50_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl50_lru_wen :std_ulogic; +signal xu_op_cl50_lru_wen :std_ulogic; +signal rel_cl50_lru_wen :std_ulogic; +signal rel_ldst_cl50_lru :std_ulogic_vector(0 to 6); +signal congr_cl51_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl51_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl51_lru_wen :std_ulogic; +signal xu_op_cl51_lru_wen :std_ulogic; +signal rel_cl51_lru_wen :std_ulogic; +signal rel_ldst_cl51_lru :std_ulogic_vector(0 to 6); +signal congr_cl52_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl52_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl52_lru_wen :std_ulogic; +signal xu_op_cl52_lru_wen :std_ulogic; +signal rel_cl52_lru_wen :std_ulogic; +signal rel_ldst_cl52_lru :std_ulogic_vector(0 to 6); +signal congr_cl53_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl53_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl53_lru_wen :std_ulogic; +signal xu_op_cl53_lru_wen :std_ulogic; +signal rel_cl53_lru_wen :std_ulogic; +signal rel_ldst_cl53_lru :std_ulogic_vector(0 to 6); +signal congr_cl54_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl54_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl54_lru_wen :std_ulogic; +signal xu_op_cl54_lru_wen :std_ulogic; +signal rel_cl54_lru_wen :std_ulogic; +signal rel_ldst_cl54_lru :std_ulogic_vector(0 to 6); +signal congr_cl55_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl55_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl55_lru_wen :std_ulogic; +signal xu_op_cl55_lru_wen :std_ulogic; +signal rel_cl55_lru_wen :std_ulogic; +signal rel_ldst_cl55_lru :std_ulogic_vector(0 to 6); +signal congr_cl56_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl56_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl56_lru_wen :std_ulogic; +signal xu_op_cl56_lru_wen :std_ulogic; +signal rel_cl56_lru_wen :std_ulogic; +signal rel_ldst_cl56_lru :std_ulogic_vector(0 to 6); +signal congr_cl57_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl57_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl57_lru_wen :std_ulogic; +signal xu_op_cl57_lru_wen :std_ulogic; +signal rel_cl57_lru_wen :std_ulogic; +signal rel_ldst_cl57_lru :std_ulogic_vector(0 to 6); +signal congr_cl58_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl58_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl58_lru_wen :std_ulogic; +signal xu_op_cl58_lru_wen :std_ulogic; +signal rel_cl58_lru_wen :std_ulogic; +signal rel_ldst_cl58_lru :std_ulogic_vector(0 to 6); +signal congr_cl59_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl59_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl59_lru_wen :std_ulogic; +signal xu_op_cl59_lru_wen :std_ulogic; +signal rel_cl59_lru_wen :std_ulogic; +signal rel_ldst_cl59_lru :std_ulogic_vector(0 to 6); +signal congr_cl60_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl60_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl60_lru_wen :std_ulogic; +signal xu_op_cl60_lru_wen :std_ulogic; +signal rel_cl60_lru_wen :std_ulogic; +signal rel_ldst_cl60_lru :std_ulogic_vector(0 to 6); +signal congr_cl61_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl61_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl61_lru_wen :std_ulogic; +signal xu_op_cl61_lru_wen :std_ulogic; +signal rel_cl61_lru_wen :std_ulogic; +signal rel_ldst_cl61_lru :std_ulogic_vector(0 to 6); +signal congr_cl62_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl62_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl62_lru_wen :std_ulogic; +signal xu_op_cl62_lru_wen :std_ulogic; +signal rel_cl62_lru_wen :std_ulogic; +signal rel_ldst_cl62_lru :std_ulogic_vector(0 to 6); +signal congr_cl63_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl63_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl63_lru_wen :std_ulogic; +signal xu_op_cl63_lru_wen :std_ulogic; +signal rel_cl63_lru_wen :std_ulogic; +signal rel_ldst_cl63_lru :std_ulogic_vector(0 to 6); +signal ex1_congr_cl :std_ulogic_vector(2 to 7); +signal ex2_congr_cl_d :std_ulogic_vector(2 to 7); +signal ex2_congr_cl_q :std_ulogic_vector(2 to 7); +signal ex3_congr_cl_d :std_ulogic_vector(2 to 7); +signal ex3_congr_cl_q :std_ulogic_vector(2 to 7); +signal ex4_congr_cl_d :std_ulogic_vector(2 to 7); +signal ex4_congr_cl_q :std_ulogic_vector(2 to 7); +signal ex5_congr_cl_d :std_ulogic_vector(2 to 7); +signal ex5_congr_cl_q :std_ulogic_vector(2 to 7); +signal ex6_congr_cl_d :std_ulogic_vector(2 to 7); +signal ex6_congr_cl_q :std_ulogic_vector(2 to 7); +signal rel_early_congr_cl :std_ulogic_vector(2 to 7); +signal rel_congr_cl_d :std_ulogic_vector(2 to 7); +signal rel_congr_cl_q :std_ulogic_vector(2 to 7); +signal rel_congr_cl_stg_d :std_ulogic_vector(2 to 7); +signal rel_congr_cl_stg_q :std_ulogic_vector(2 to 7); +signal relu_congr_cl_d :std_ulogic_vector(2 to 7); +signal relu_congr_cl_q :std_ulogic_vector(2 to 7); +signal rel2_val_d :std_ulogic; +signal rel2_val_q :std_ulogic; +signal relu_val_wen_d :std_ulogic; +signal relu_val_wen_q :std_ulogic; +signal rel_val_wen_d :std_ulogic; +signal rel_val_wen_q :std_ulogic; +signal congr_cl_lru_b_q :std_ulogic_vector(0 to 6); +signal rel_wayA_clr :std_ulogic; +signal rel_wayB_clr :std_ulogic; +signal rel_wayC_clr :std_ulogic; +signal rel_wayD_clr :std_ulogic; +signal rel_wayE_clr :std_ulogic; +signal rel_wayF_clr :std_ulogic; +signal rel_wayG_clr :std_ulogic; +signal rel_wayH_clr :std_ulogic; +signal rel_hit_vec :std_ulogic_vector(0 to 7); +signal hit_wayA_upd :std_ulogic_vector(0 to 6); +signal hit_wayB_upd :std_ulogic_vector(0 to 6); +signal hit_wayC_upd :std_ulogic_vector(0 to 6); +signal hit_wayD_upd :std_ulogic_vector(0 to 6); +signal hit_wayE_upd :std_ulogic_vector(0 to 6); +signal hit_wayF_upd :std_ulogic_vector(0 to 6); +signal hit_wayG_upd :std_ulogic_vector(0 to 6); +signal hit_wayh_upd :std_ulogic_vector(0 to 6); +signal rel_hit_wayA_upd :std_ulogic_vector(0 to 6); +signal rel_hit_wayB_upd :std_ulogic_vector(0 to 6); +signal rel_hit_wayC_upd :std_ulogic_vector(0 to 6); +signal rel_hit_wayD_upd :std_ulogic_vector(0 to 6); +signal rel_hit_wayE_upd :std_ulogic_vector(0 to 6); +signal rel_hit_wayF_upd :std_ulogic_vector(0 to 6); +signal rel_hit_wayG_upd :std_ulogic_vector(0 to 6); +signal rel_hit_wayh_upd :std_ulogic_vector(0 to 6); +signal ldst_wayA_hit :std_ulogic; +signal ldst_wayB_hit :std_ulogic; +signal ldst_wayC_hit :std_ulogic; +signal ldst_wayD_hit :std_ulogic; +signal ldst_wayE_hit :std_ulogic; +signal ldst_wayF_hit :std_ulogic; +signal ldst_wayG_hit :std_ulogic; +signal ldst_wayH_hit :std_ulogic; +signal lru_upd :std_ulogic_vector(0 to 6); +signal relu_lru_upd_d :std_ulogic_vector(0 to 6); +signal relu_lru_upd_q :std_ulogic_vector(0 to 6); +signal rel_lru_val_d :std_ulogic_vector(0 to 6); +signal rel_lru_val_q :std_ulogic_vector(0 to 6); +signal ex5_lru_upd_d :std_ulogic_vector(0 to 6); +signal ex5_lru_upd_q :std_ulogic_vector(0 to 6); +signal ex6_lru_upd_d :std_ulogic_vector(0 to 6); +signal ex6_lru_upd_q :std_ulogic_vector(0 to 6); +signal ex4_hit_d :std_ulogic; +signal ex4_hit_q :std_ulogic; +signal ex3_c_acc_val :std_ulogic; +signal ex4_c_acc_val :std_ulogic; +signal ex4_c_acc :std_ulogic; +signal ex4_c_acc_d :std_ulogic; +signal ex4_c_acc_q :std_ulogic; +signal ex5_c_acc_val :std_ulogic; +signal ex5_c_acc_d :std_ulogic; +signal ex5_c_acc_q :std_ulogic; +signal ex6_c_acc_val_d :std_ulogic; +signal ex6_c_acc_val_q :std_ulogic; +signal ex3_flush :std_ulogic; +signal ex4_flush :std_ulogic; +signal ex5_flush :std_ulogic; +signal xu_op_lru :std_ulogic_vector(0 to 6); +signal rel_op_lru :std_ulogic_vector(0 to 6); +signal ldst_hit_vector :std_ulogic_vector(0 to 7); +signal arr_congr_cl_lru :std_ulogic_vector(0 to 6); +signal rel_congr_cl_lru :std_ulogic_vector(0 to 6); +signal p0_arr_lru_rd :std_ulogic_vector(0 to 6); +signal p1_arr_lru_rd :std_ulogic_vector(0 to 6); +signal rel_congr_cl_lru_b_q :std_ulogic_vector(0 to 6); +signal congr_cl_ex3_ex4_m :std_ulogic; +signal congr_cl_ex3_ex5_m :std_ulogic; +signal congr_cl_ex3_p0_m :std_ulogic; +signal congr_cl_ex3_rel2_m :std_ulogic; +signal congr_cl_ex3_p1_m :std_ulogic; +signal congr_cl_ex3_ex4_cmp_d :std_ulogic; +signal congr_cl_ex3_ex4_cmp_q :std_ulogic; +signal congr_cl_ex3_ex5_cmp_d :std_ulogic; +signal congr_cl_ex3_ex5_cmp_q :std_ulogic; +signal congr_cl_ex3_ex6_cmp_d :std_ulogic; +signal congr_cl_ex3_ex6_cmp_q :std_ulogic; +signal congr_cl_ex3_rel2_cmp_d :std_ulogic; +signal congr_cl_ex3_rel2_cmp_q :std_ulogic; +signal congr_cl_ex3_rel_upd_cmp_d :std_ulogic; +signal congr_cl_ex3_rel_upd_cmp_q :std_ulogic; +signal congr_cl_rel1_ex4_cmp_d :std_ulogic; +signal congr_cl_rel1_ex4_cmp_q :std_ulogic; +signal congr_cl_rel1_ex5_cmp_d :std_ulogic; +signal congr_cl_rel1_ex5_cmp_q :std_ulogic; +signal congr_cl_rel1_ex6_cmp_d :std_ulogic; +signal congr_cl_rel1_ex6_cmp_q :std_ulogic; +signal congr_cl_rel1_rel2_cmp_d :std_ulogic; +signal congr_cl_rel1_rel2_cmp_q :std_ulogic; +signal congr_cl_rel1_relu_cmp_d :std_ulogic; +signal congr_cl_rel1_relu_cmp_q :std_ulogic; +signal congr_cl_rel1_rel_upd_cmp_d :std_ulogic; +signal congr_cl_rel1_rel_upd_cmp_q :std_ulogic; +signal ex3_no_lru_upd_d :std_ulogic; +signal ex3_no_lru_upd_q :std_ulogic; +signal ex3_l1hit :std_ulogic; +signal rel2_wayA_val :std_ulogic; +signal rel2_wayB_val :std_ulogic; +signal rel2_wayC_val :std_ulogic; +signal rel2_wayD_val :std_ulogic; +signal rel2_wayE_val :std_ulogic; +signal rel2_wayF_val :std_ulogic; +signal rel2_wayG_val :std_ulogic; +signal rel2_wayH_val :std_ulogic; +signal congr_cl_full :std_ulogic; +signal empty_way :std_ulogic_vector(0 to 7); +signal full_way :std_ulogic_vector(0 to 7); +signal rel_hit :std_ulogic_vector(0 to 7); +signal rel_upd_congr_cl_d :std_ulogic_vector(2 to 7); +signal rel_upd_congr_cl_q :std_ulogic_vector(2 to 7); +signal congr_cl_ex3_byp :std_ulogic_vector(0 to 4); +signal congr_cl_ex3_sel :std_ulogic_vector(1 to 4); +signal congr_cl_rel1_ex4_m :std_ulogic; +signal congr_cl_rel1_ex5_m :std_ulogic; +signal congr_cl_rel1_p0_m :std_ulogic; +signal congr_cl_rel1_rel2_m :std_ulogic; +signal congr_cl_rel1_relu_m :std_ulogic; +signal congr_cl_rel1_p1_m :std_ulogic; +signal rel_lru_early_sel :std_ulogic_vector(0 to 6); +signal rel_lru_early_sel_b :std_ulogic_vector(0 to 6); +signal congr_cl_rel1_byp :std_ulogic_vector(0 to 5); +signal congr_cl_rel1_sel :std_ulogic_vector(1 to 5); +signal rel_way_qsel_d :std_ulogic_vector(0 to 7); +signal rel_way_qsel_q :std_ulogic_vector(0 to 7); +signal rel_tag_d :std_ulogic_vector(0 to 2); +signal rel_tag_q :std_ulogic_vector(0 to 2); +signal rel4_val_d :std_ulogic; +signal rel4_val_q :std_ulogic; +signal rel4_retry_val_d :std_ulogic; +signal rel4_retry_val_q :std_ulogic; +signal rel_wayA_upd :std_ulogic; +signal rel_wayB_upd :std_ulogic; +signal rel_wayC_upd :std_ulogic; +signal rel_wayD_upd :std_ulogic; +signal rel_wayE_upd :std_ulogic; +signal rel_wayF_upd :std_ulogic; +signal rel_wayG_upd :std_ulogic; +signal rel_wayH_upd :std_ulogic; +signal rel_wayA_set :std_ulogic; +signal rel_wayB_set :std_ulogic; +signal rel_wayC_set :std_ulogic; +signal rel_wayD_set :std_ulogic; +signal rel_wayE_set :std_ulogic; +signal rel_wayF_set :std_ulogic; +signal rel_wayG_set :std_ulogic; +signal rel_wayH_set :std_ulogic; +signal rel_wayA_mid :std_ulogic; +signal rel_wayB_mid :std_ulogic; +signal rel_wayC_mid :std_ulogic; +signal rel_wayD_mid :std_ulogic; +signal rel_wayE_mid :std_ulogic; +signal rel_wayF_mid :std_ulogic; +signal rel_wayG_mid :std_ulogic; +signal rel_wayH_mid :std_ulogic; +signal rel1_wlock_b :std_ulogic_vector(0 to 7); +signal rel2_wlock_d :std_ulogic_vector(0 to 7); +signal rel2_wlock_q :std_ulogic_vector(0 to 7); +signal rel2_wayA_lock :std_ulogic; +signal rel2_wayB_lock :std_ulogic; +signal rel2_wayC_lock :std_ulogic; +signal rel2_wayD_lock :std_ulogic; +signal rel2_wayE_lock :std_ulogic; +signal rel2_wayF_lock :std_ulogic; +signal rel2_wayG_lock :std_ulogic; +signal rel2_wayH_lock :std_ulogic; +signal rel_lock_line :std_ulogic_vector(0 to 7); +signal rel_ovrd_lru :std_ulogic_vector(0 to 6); +signal rel_ovrd_wayAB :std_ulogic_vector(0 to 1); +signal rel_ovrd_wayCD :std_ulogic_vector(0 to 1); +signal rel_ovrd_wayEF :std_ulogic_vector(0 to 1); +signal rel_ovrd_wayGH :std_ulogic_vector(0 to 1); +signal rel_ovrd_wayABCD :std_ulogic_vector(0 to 1); +signal rel_ovrd_wayEFGH :std_ulogic_vector(0 to 1); +signal rel_ovrd_wayABCDEFGH :std_ulogic_vector(0 to 1); +signal ovr_lock_det :std_ulogic; +signal ovr_lock_det_wlkon :std_ulogic; +signal ovr_lock_det_wlkoff :std_ulogic; +signal wayA_not_empty :std_ulogic; +signal wayB_not_empty :std_ulogic; +signal wayC_not_empty :std_ulogic; +signal wayD_not_empty :std_ulogic; +signal wayE_not_empty :std_ulogic; +signal wayF_not_empty :std_ulogic; +signal wayg_not_empty :std_ulogic; +signal wayH_not_empty :std_ulogic; +signal rel_way_not_empty_d :std_ulogic_vector(0 to 7); +signal rel_way_not_empty_q :std_ulogic_vector(0 to 7); +signal reld_q0_chk_val :std_ulogic; +signal reld_q0_chk_way :std_ulogic_vector(0 to 7); +signal reld_q0_way_m :std_ulogic; +signal reld_q0_set :std_ulogic; +signal reld_q0_inval :std_ulogic; +signal reld_q0_val_sel :std_ulogic_vector(0 to 1); +signal reld_q0_congr_cl_d :std_ulogic_vector(2 to 7); +signal reld_q0_congr_cl_q :std_ulogic_vector(2 to 7); +signal reld_q0_way_d :std_ulogic_vector(0 to 7); +signal reld_q0_way_q :std_ulogic_vector(0 to 7); +signal reld_q0_val_d :std_ulogic; +signal reld_q0_val_q :std_ulogic; +signal reld_q0_lock_d :std_ulogic; +signal reld_q0_lock_q :std_ulogic; +signal rel_m_q0 :std_ulogic; +signal reld_q1_chk_val :std_ulogic; +signal reld_q1_chk_way :std_ulogic_vector(0 to 7); +signal reld_q1_way_m :std_ulogic; +signal reld_q1_set :std_ulogic; +signal reld_q1_inval :std_ulogic; +signal reld_q1_val_sel :std_ulogic_vector(0 to 1); +signal reld_q1_congr_cl_d :std_ulogic_vector(2 to 7); +signal reld_q1_congr_cl_q :std_ulogic_vector(2 to 7); +signal reld_q1_way_d :std_ulogic_vector(0 to 7); +signal reld_q1_way_q :std_ulogic_vector(0 to 7); +signal reld_q1_val_d :std_ulogic; +signal reld_q1_val_q :std_ulogic; +signal reld_q1_lock_d :std_ulogic; +signal reld_q1_lock_q :std_ulogic; +signal rel_m_q1 :std_ulogic; +signal reld_q2_chk_val :std_ulogic; +signal reld_q2_chk_way :std_ulogic_vector(0 to 7); +signal reld_q2_way_m :std_ulogic; +signal reld_q2_set :std_ulogic; +signal reld_q2_inval :std_ulogic; +signal reld_q2_val_sel :std_ulogic_vector(0 to 1); +signal reld_q2_congr_cl_d :std_ulogic_vector(2 to 7); +signal reld_q2_congr_cl_q :std_ulogic_vector(2 to 7); +signal reld_q2_way_d :std_ulogic_vector(0 to 7); +signal reld_q2_way_q :std_ulogic_vector(0 to 7); +signal reld_q2_val_d :std_ulogic; +signal reld_q2_val_q :std_ulogic; +signal reld_q2_lock_d :std_ulogic; +signal reld_q2_lock_q :std_ulogic; +signal rel_m_q2 :std_ulogic; +signal reld_q3_chk_val :std_ulogic; +signal reld_q3_chk_way :std_ulogic_vector(0 to 7); +signal reld_q3_way_m :std_ulogic; +signal reld_q3_set :std_ulogic; +signal reld_q3_inval :std_ulogic; +signal reld_q3_val_sel :std_ulogic_vector(0 to 1); +signal reld_q3_congr_cl_d :std_ulogic_vector(2 to 7); +signal reld_q3_congr_cl_q :std_ulogic_vector(2 to 7); +signal reld_q3_way_d :std_ulogic_vector(0 to 7); +signal reld_q3_way_q :std_ulogic_vector(0 to 7); +signal reld_q3_val_d :std_ulogic; +signal reld_q3_val_q :std_ulogic; +signal reld_q3_lock_d :std_ulogic; +signal reld_q3_lock_q :std_ulogic; +signal rel_m_q3 :std_ulogic; +signal reld_q4_chk_val :std_ulogic; +signal reld_q4_chk_way :std_ulogic_vector(0 to 7); +signal reld_q4_way_m :std_ulogic; +signal reld_q4_set :std_ulogic; +signal reld_q4_inval :std_ulogic; +signal reld_q4_val_sel :std_ulogic_vector(0 to 1); +signal reld_q4_congr_cl_d :std_ulogic_vector(2 to 7); +signal reld_q4_congr_cl_q :std_ulogic_vector(2 to 7); +signal reld_q4_way_d :std_ulogic_vector(0 to 7); +signal reld_q4_way_q :std_ulogic_vector(0 to 7); +signal reld_q4_val_d :std_ulogic; +signal reld_q4_val_q :std_ulogic; +signal reld_q4_lock_d :std_ulogic; +signal reld_q4_lock_q :std_ulogic; +signal rel_m_q4 :std_ulogic; +signal reld_q5_chk_val :std_ulogic; +signal reld_q5_chk_way :std_ulogic_vector(0 to 7); +signal reld_q5_way_m :std_ulogic; +signal reld_q5_set :std_ulogic; +signal reld_q5_inval :std_ulogic; +signal reld_q5_val_sel :std_ulogic_vector(0 to 1); +signal reld_q5_congr_cl_d :std_ulogic_vector(2 to 7); +signal reld_q5_congr_cl_q :std_ulogic_vector(2 to 7); +signal reld_q5_way_d :std_ulogic_vector(0 to 7); +signal reld_q5_way_q :std_ulogic_vector(0 to 7); +signal reld_q5_val_d :std_ulogic; +signal reld_q5_val_q :std_ulogic; +signal reld_q5_lock_d :std_ulogic; +signal reld_q5_lock_q :std_ulogic; +signal rel_m_q5 :std_ulogic; +signal reld_q6_chk_val :std_ulogic; +signal reld_q6_chk_way :std_ulogic_vector(0 to 7); +signal reld_q6_way_m :std_ulogic; +signal reld_q6_set :std_ulogic; +signal reld_q6_inval :std_ulogic; +signal reld_q6_val_sel :std_ulogic_vector(0 to 1); +signal reld_q6_congr_cl_d :std_ulogic_vector(2 to 7); +signal reld_q6_congr_cl_q :std_ulogic_vector(2 to 7); +signal reld_q6_way_d :std_ulogic_vector(0 to 7); +signal reld_q6_way_q :std_ulogic_vector(0 to 7); +signal reld_q6_val_d :std_ulogic; +signal reld_q6_val_q :std_ulogic; +signal reld_q6_lock_d :std_ulogic; +signal reld_q6_lock_q :std_ulogic; +signal rel_m_q6 :std_ulogic; +signal reld_q7_chk_val :std_ulogic; +signal reld_q7_chk_way :std_ulogic_vector(0 to 7); +signal reld_q7_way_m :std_ulogic; +signal reld_q7_set :std_ulogic; +signal reld_q7_inval :std_ulogic; +signal reld_q7_val_sel :std_ulogic_vector(0 to 1); +signal reld_q7_congr_cl_d :std_ulogic_vector(2 to 7); +signal reld_q7_congr_cl_q :std_ulogic_vector(2 to 7); +signal reld_q7_way_d :std_ulogic_vector(0 to 7); +signal reld_q7_way_q :std_ulogic_vector(0 to 7); +signal reld_q7_val_d :std_ulogic; +signal reld_q7_val_q :std_ulogic; +signal reld_q7_lock_d :std_ulogic; +signal reld_q7_lock_q :std_ulogic; +signal rel_m_q7 :std_ulogic; +signal reld_match :std_ulogic_vector(0 to 7); +signal reld_q_sel_d :std_ulogic_vector(0 to 7); +signal reld_q_sel_q :std_ulogic_vector(0 to 7); +signal rel_val_qsel_d :std_ulogic; +signal rel_val_qsel_q :std_ulogic; +signal spr_rmt_table :std_ulogic_vector(0 to 31); +signal rel_class_id :std_ulogic_vector(0 to 1); +signal rel2_class_id_d :std_ulogic_vector(0 to 1); +signal rel2_class_id_q :std_ulogic_vector(0 to 1); +signal rel_m_q_way_b :std_ulogic_vector(0 to 7); +signal rel_m_q_way_d :std_ulogic_vector(0 to 7); +signal rel_m_q_way_q :std_ulogic_vector(0 to 7); +signal rel_m_q_lock_way :std_ulogic_vector(0 to 7); +signal rel2_lock_en_d :std_ulogic; +signal rel2_lock_en_q :std_ulogic; +signal xucr0_clo_d :std_ulogic; +signal xucr0_clo_q :std_ulogic; +signal rel_way_dwen :std_ulogic_vector(0 to 7); +signal rel24_way_dwen_stg_d :std_ulogic_vector(0 to 7); +signal rel24_way_dwen_stg_q :std_ulogic_vector(0 to 7); +signal rel_up_way_addr_d :std_ulogic_vector(0 to 2); +signal rel_up_way_addr_q :std_ulogic_vector(0 to 2); +signal rel_dcarr_addr_en_d :std_ulogic; +signal rel_dcarr_addr_en_q :std_ulogic; +signal rel_dcarr_val_upd_d :std_ulogic; +signal rel_dcarr_val_upd_q :std_ulogic; +signal rel_lru_late_sel :std_ulogic; +signal rel_lru_late_stg_pri :std_ulogic_vector(0 to 6); +signal rel_lru_late_stg_arr :std_ulogic_vector(0 to 6); +signal lru_late_sel :std_ulogic; +signal lru_late_stg_pri :std_ulogic_vector(0 to 6); +signal lru_late_stg_arr :std_ulogic_vector(0 to 6); +signal lru_early_sel :std_ulogic_vector(0 to 6); +signal lru_early_sel_b :std_ulogic_vector(0 to 6); +signal rel_hit_lru_upd :std_ulogic_vector(0 to 6); +signal ldst_hit_vec_sel :std_ulogic; +signal ldst_hit_lru_upd :std_ulogic_vector(0 to 6); +signal rel_wlock_rmt :std_ulogic_vector(0 to 7); +signal congr_cl_act_d :std_ulogic; +signal congr_cl_act_q :std_ulogic; +signal rel2_mid_val_d :std_ulogic; +signal rel2_mid_val_q :std_ulogic; +signal relq_m_way_val :std_ulogic_vector(0 to 7); +signal rel_m_q_upd :std_ulogic; +signal rel_m_q_upd_way :std_ulogic_vector(0 to 7); +signal rel_m_q_upd_lock_way :std_ulogic_vector(0 to 7); +signal reld_q_early_sel :std_ulogic_vector(0 to 7); +signal rel_way_early_qsel :std_ulogic_vector(0 to 7); +signal rel_way_early_qsel_d :std_ulogic_vector(0 to 7); +signal rel_way_early_qsel_q :std_ulogic_vector(0 to 7); +signal rel_val_early_qsel :std_ulogic; +signal rel_val_early_qsel_d :std_ulogic; +signal rel_val_early_qsel_q :std_ulogic; +signal reld_q_early_byp :std_ulogic; +signal reld_way_early_byp :std_ulogic_vector(0 to 7); +signal reld_q_val :std_ulogic_vector(0 to 7); +signal ex4_fxubyp_val_d :std_ulogic; +signal ex4_fxubyp_val_q :std_ulogic; +signal ex4_relbyp_val_d :std_ulogic; +signal ex4_relbyp_val_q :std_ulogic; +signal ex4_lru_byp_sel :std_ulogic_vector(0 to 1); +signal rel2_fxubyp_val_d :std_ulogic; +signal rel2_fxubyp_val_q :std_ulogic; +signal rel2_relbyp_val_d :std_ulogic; +signal rel2_relbyp_val_q :std_ulogic; +signal rel2_lru_byp_sel :std_ulogic_vector(0 to 1); +signal tiup :std_ulogic; +signal siv :std_ulogic_vector(0 to scan_right); +signal sov :std_ulogic_vector(0 to scan_right); + BEGIN + +tiup <= '1'; +rel2_val_d <= rel1_val; +rel2_mid_val_d <= rel_mid_val; +rel4_retry_val_d <= rel_retry_val; +rel4_val_d <= rel3_val; +rel_tag_d <= rel_st_tag; +rel_class_id <= rel1_classid; +rel2_class_id_d <= rel_class_id; +rel2_lock_en_d <= rel_lock_en; +rel2_wayA_val <= rel_way_val_a; +rel2_wayB_val <= rel_way_val_b; +rel2_wayC_val <= rel_way_val_c; +rel2_wayD_val <= rel_way_val_d; +rel2_wayE_val <= rel_way_val_e; +rel2_wayF_val <= rel_way_val_f; +rel2_wayG_val <= rel_way_val_g; +rel2_wayH_val <= rel_way_val_h; +rel2_wayA_lock <= rel_way_lock_a; +rel2_wayB_lock <= rel_way_lock_b; +rel2_wayC_lock <= rel_way_lock_c; +rel2_wayD_lock <= rel_way_lock_d; +rel2_wayE_lock <= rel_way_lock_e; +rel2_wayF_lock <= rel_way_lock_f; +rel2_wayG_lock <= rel_way_lock_g; +rel2_wayH_lock <= rel_way_lock_h; +spr_rmt_table <= spr_xucr2_rmt; +ldst_wayA_hit <= ex4_way_a_hit; +ldst_wayB_hit <= ex4_way_b_hit; +ldst_wayC_hit <= ex4_way_c_hit; +ldst_wayD_hit <= ex4_way_d_hit; +ldst_wayE_hit <= ex4_way_e_hit; +ldst_wayF_hit <= ex4_way_f_hit; +ldst_wayG_hit <= ex4_way_g_hit; +ldst_wayH_hit <= ex4_way_h_hit; +ex3_l1hit <= ex3_hit; +ex3_no_lru_upd_d <= ex2_no_lru_upd; +ex3_flush <= ex3_stg_flush; +ex4_flush <= ex4_stg_flush; +ex5_flush <= ex5_stg_flush; +ex1_congr_cl <= ex1_p_addr; +cl64size : if (cl_size=6) generate +begin + rel_early_congr_cl(2 TO 6) <= rel_addr_early(64-(dc_size-3) to 63-cl_size-1); +rel_early_congr_cl(7) <= rel_addr_early(63-cl_size) or spr_xucr0_cls; +end generate cl64size; +cl32size : if (cl_size=5) generate +begin + rel_early_congr_cl(2 TO 5) <= rel_addr_early(64-(dc_size-3) to 63-cl_size-2); +rel_early_congr_cl(6) <= rel_addr_early(63-cl_size-1) or spr_xucr0_cls; +rel_early_congr_cl(7) <= rel_addr_early(63-cl_size); +end generate cl32size; +rel_congr_cl_d <= rel_early_congr_cl; +ex2_congr_cl_d <= ex1_congr_cl; +ex3_congr_cl_d <= ex2_congr_cl_q; +ex4_congr_cl_d <= ex3_congr_cl_q; +ex5_congr_cl_d <= ex4_congr_cl_q; +ex6_congr_cl_d <= ex5_congr_cl_q; +with rel_congr_cl_q select + rel_congr_cl_lru <= + congr_cl0_lru_q when "000000", + congr_cl1_lru_q when "000001", + congr_cl2_lru_q when "000010", + congr_cl3_lru_q when "000011", + congr_cl4_lru_q when "000100", + congr_cl5_lru_q when "000101", + congr_cl6_lru_q when "000110", + congr_cl7_lru_q when "000111", + congr_cl8_lru_q when "001000", + congr_cl9_lru_q when "001001", + congr_cl10_lru_q when "001010", + congr_cl11_lru_q when "001011", + congr_cl12_lru_q when "001100", + congr_cl13_lru_q when "001101", + congr_cl14_lru_q when "001110", + congr_cl15_lru_q when "001111", + congr_cl16_lru_q when "010000", + congr_cl17_lru_q when "010001", + congr_cl18_lru_q when "010010", + congr_cl19_lru_q when "010011", + congr_cl20_lru_q when "010100", + congr_cl21_lru_q when "010101", + congr_cl22_lru_q when "010110", + congr_cl23_lru_q when "010111", + congr_cl24_lru_q when "011000", + congr_cl25_lru_q when "011001", + congr_cl26_lru_q when "011010", + congr_cl27_lru_q when "011011", + congr_cl28_lru_q when "011100", + congr_cl29_lru_q when "011101", + congr_cl30_lru_q when "011110", + congr_cl31_lru_q when "011111", + congr_cl32_lru_q when "100000", + congr_cl33_lru_q when "100001", + congr_cl34_lru_q when "100010", + congr_cl35_lru_q when "100011", + congr_cl36_lru_q when "100100", + congr_cl37_lru_q when "100101", + congr_cl38_lru_q when "100110", + congr_cl39_lru_q when "100111", + congr_cl40_lru_q when "101000", + congr_cl41_lru_q when "101001", + congr_cl42_lru_q when "101010", + congr_cl43_lru_q when "101011", + congr_cl44_lru_q when "101100", + congr_cl45_lru_q when "101101", + congr_cl46_lru_q when "101110", + congr_cl47_lru_q when "101111", + congr_cl48_lru_q when "110000", + congr_cl49_lru_q when "110001", + congr_cl50_lru_q when "110010", + congr_cl51_lru_q when "110011", + congr_cl52_lru_q when "110100", + congr_cl53_lru_q when "110101", + congr_cl54_lru_q when "110110", + congr_cl55_lru_q when "110111", + congr_cl56_lru_q when "111000", + congr_cl57_lru_q when "111001", + congr_cl58_lru_q when "111010", + congr_cl59_lru_q when "111011", + congr_cl60_lru_q when "111100", + congr_cl61_lru_q when "111101", + congr_cl62_lru_q when "111110", + congr_cl63_lru_q when others; +p1_arr_lru_rd <= rel_congr_cl_lru; +rel_m_q_upd <= (rel_congr_cl_q = rel_congr_cl_stg_q) and rel2_val_q; +rel_m_q_upd_way <= gate(rel_hit_vec, rel_m_q_upd); +rel_m_q_upd_lock_way <= gate(rel_hit_vec, (rel_m_q_upd and rel2_lock_en_q)); +rel_m_q0 <= (rel_congr_cl_q = reld_q0_congr_cl_q) and reld_q0_val_q; +rel_m_q1 <= (rel_congr_cl_q = reld_q1_congr_cl_q) and reld_q1_val_q; +rel_m_q2 <= (rel_congr_cl_q = reld_q2_congr_cl_q) and reld_q2_val_q; +rel_m_q3 <= (rel_congr_cl_q = reld_q3_congr_cl_q) and reld_q3_val_q; +rel_m_q4 <= (rel_congr_cl_q = reld_q4_congr_cl_q) and reld_q4_val_q; +rel_m_q5 <= (rel_congr_cl_q = reld_q5_congr_cl_q) and reld_q5_val_q; +rel_m_q6 <= (rel_congr_cl_q = reld_q6_congr_cl_q) and reld_q6_val_q; +rel_m_q7 <= (rel_congr_cl_q = reld_q7_congr_cl_q) and reld_q7_val_q; +relq_m_way_val <= gate(reld_q0_way_q, rel_m_q0) or + gate(reld_q1_way_q, rel_m_q1) or + gate(reld_q2_way_q, rel_m_q2) or + gate(reld_q3_way_q, rel_m_q3) or + gate(reld_q4_way_q, rel_m_q4) or + gate(reld_q5_way_q, rel_m_q5) or + gate(reld_q6_way_q, rel_m_q6) or + gate(reld_q7_way_q, rel_m_q7); +relMQWayB: rel_m_q_way_b <= not (relq_m_way_val or rel_m_q_upd_way); +rel_m_q_way_d <= not rel_m_q_way_b; +rel_m_q_lock_way <= gate(gate(reld_q0_way_q, reld_q0_lock_q), rel_m_q0) or + gate(gate(reld_q1_way_q, reld_q1_lock_q), rel_m_q1) or + gate(gate(reld_q2_way_q, reld_q2_lock_q), rel_m_q2) or + gate(gate(reld_q3_way_q, reld_q3_lock_q), rel_m_q3) or + gate(gate(reld_q4_way_q, reld_q4_lock_q), rel_m_q4) or + gate(gate(reld_q5_way_q, reld_q5_lock_q), rel_m_q5) or + gate(gate(reld_q6_way_q, reld_q6_lock_q), rel_m_q6) or + gate(gate(reld_q7_way_q, reld_q7_lock_q), rel_m_q7) or + rel_wlock_rmt; +congr_cl_rel1_ex4_cmp_d <= (rel_early_congr_cl = ex3_congr_cl_q); +congr_cl_rel1_ex5_cmp_d <= (rel_early_congr_cl = ex4_congr_cl_q); +congr_cl_rel1_ex6_cmp_d <= (rel_early_congr_cl = ex5_congr_cl_q); +congr_cl_rel1_rel2_cmp_d <= (rel_early_congr_cl = rel_congr_cl_q); +congr_cl_rel1_relu_cmp_d <= (rel_early_congr_cl = rel_congr_cl_stg_q); +congr_cl_rel1_rel_upd_cmp_d <= (rel_early_congr_cl = relu_congr_cl_q); +congr_cl_rel1_ex4_m <= congr_cl_rel1_ex4_cmp_q and ex4_c_acc; +congr_cl_rel1_ex5_m <= congr_cl_rel1_ex5_cmp_q and ex5_c_acc_q; +congr_cl_rel1_rel2_m <= congr_cl_rel1_rel2_cmp_q and rel2_val_q and not ovr_lock_det; +congr_cl_rel1_relu_m <= congr_cl_rel1_relu_cmp_q and relu_val_wen_q; +congr_cl_rel1_p0_m <= congr_cl_rel1_ex6_cmp_q and ex6_c_acc_val_q; +congr_cl_rel1_p1_m <= congr_cl_rel1_rel_upd_cmp_q and rel_val_wen_q; +congr_cl_rel1_byp(0) <= congr_cl_rel1_rel2_m; +congr_cl_rel1_byp(1) <= congr_cl_rel1_ex4_m; +congr_cl_rel1_byp(2) <= congr_cl_rel1_relu_m; +congr_cl_rel1_byp(3) <= congr_cl_rel1_ex5_m; +congr_cl_rel1_byp(4) <= congr_cl_rel1_p1_m; +congr_cl_rel1_byp(5) <= congr_cl_rel1_p0_m; +rel2_fxubyp_val_d <= congr_cl_rel1_byp(1) or congr_cl_rel1_byp(3) or congr_cl_rel1_byp(5); +rel2_relbyp_val_d <= congr_cl_rel1_byp(0) or congr_cl_rel1_byp(2) or congr_cl_rel1_byp(4); +rel2_lru_byp_sel <= rel2_fxubyp_val_q & rel2_relbyp_val_q; +congr_cl_rel1_sel(1) <= congr_cl_rel1_byp(1); +congr_cl_rel1_sel(2) <= congr_cl_rel1_byp(2) and not congr_cl_rel1_byp(1); +congr_cl_rel1_sel(3) <= congr_cl_rel1_byp(3) and not or_reduce(congr_cl_rel1_byp(1 to 2)); +congr_cl_rel1_sel(4) <= congr_cl_rel1_byp(4) and not or_reduce(congr_cl_rel1_byp(1 to 3)); +congr_cl_rel1_sel(5) <= congr_cl_rel1_byp(5) and not or_reduce(congr_cl_rel1_byp(1 to 4)); +rel_lru_late_sel <= or_reduce(congr_cl_rel1_byp(1 to 5)); +rel_lru_late_stg_pri <= gate(lru_upd, congr_cl_rel1_sel(1)) or + gate(relu_lru_upd_q, congr_cl_rel1_sel(2)) or + gate(ex5_lru_upd_q, congr_cl_rel1_sel(3)) or + gate(rel_lru_val_q, congr_cl_rel1_sel(4)) or + gate(ex6_lru_upd_q, congr_cl_rel1_sel(5)); +rel_lru_late_stg_arr <= gate(p1_arr_lru_rd, not rel_lru_late_sel) or rel_lru_late_stg_pri; +rel_lru_early_sel <= (others=>congr_cl_rel1_byp(0)); +rel_lru_early_sel_b <= (others=>(not congr_cl_rel1_byp(0))); +rel_op_lru <= not rel_congr_cl_lru_b_q; +rel_congr_cl_stg_d <= rel_congr_cl_q; +relu_congr_cl_d <= rel_congr_cl_stg_q; +rel_upd_congr_cl_d <= relu_congr_cl_q; +relu_val_wen_d <= rel2_val_q and not ovr_lock_det; +rel_val_wen_d <= relu_val_wen_q; +rel_dcarr_addr_en_d <= rel2_val_q or (rel4_val_q and not rel4_retry_val_q) or rel2_mid_val_q; +with rel_class_id select + rel_wlock_rmt <= not spr_rmt_table(0 to 7) when "11", + not spr_rmt_table(8 to 15) when "10", + not spr_rmt_table(16 to 23) when "01", + not spr_rmt_table(24 to 31) when others; +rel1WlockB: rel1_wlock_b <= not (rel_m_q_upd_lock_way or rel_m_q_lock_way); +rel2_wlock_d <= not rel1_wlock_b; +rel_lock_line(0) <= rel2_wayA_lock or rel2_wlock_q(0); +rel_lock_line(1) <= rel2_wayB_lock or rel2_wlock_q(1); +rel_lock_line(2) <= rel2_wayC_lock or rel2_wlock_q(2); +rel_lock_line(3) <= rel2_wayD_lock or rel2_wlock_q(3); +rel_lock_line(4) <= rel2_wayE_lock or rel2_wlock_q(4); +rel_lock_line(5) <= rel2_wayF_lock or rel2_wlock_q(5); +rel_lock_line(6) <= rel2_wayG_lock or rel2_wlock_q(6); +rel_lock_line(7) <= rel2_wayH_lock or rel2_wlock_q(7); +ovr_lock_det <= rel_lock_line(0) and rel_lock_line(1) and rel_lock_line(2) and rel_lock_line(3) and + rel_lock_line(4) and rel_lock_line(5) and rel_lock_line(6) and rel_lock_line(7); +ovr_lock_det_wlkon <= ovr_lock_det and rel2_val_q; +ovr_lock_det_wlkoff <= ovr_lock_det and rel2_lock_en_q and rel2_val_q; +with spr_xucr0_wlck select + xucr0_clo_d <= ovr_lock_det_wlkon when '1', + ovr_lock_det_wlkoff when others; +rel_ovrd_wayABCDEFGH <= (rel_lock_line(0) and rel_lock_line(1) and rel_lock_line(2) and rel_lock_line(3)) & + (rel_lock_line(4) and rel_lock_line(5) and rel_lock_line(6) and rel_lock_line(7)); +rel_ovrd_lru(0) <= (rel_op_lru(0) and not rel_ovrd_wayABCDEFGH(1)) or rel_ovrd_wayABCDEFGH(0); +rel_ovrd_wayABCD <= (rel_lock_line(0) and rel_lock_line(1)) & (rel_lock_line(2) and rel_lock_line(3)); +rel_ovrd_lru(1) <= (rel_op_lru(1) and not rel_ovrd_wayABCD(1)) or rel_ovrd_wayABCD(0); +rel_ovrd_wayEFGH <= (rel_lock_line(4) and rel_lock_line(5)) & (rel_lock_line(6) and rel_lock_line(7)); +rel_ovrd_lru(2) <= (rel_op_lru(2) and not rel_ovrd_wayEFGH(1)) or rel_ovrd_wayEFGH(0); +rel_ovrd_wayAB <= rel_lock_line(0 to 1); +rel_ovrd_lru(3) <= (rel_op_lru(3) and not rel_ovrd_wayAB(1)) or rel_ovrd_wayAB(0); +rel_ovrd_wayCD <= rel_lock_line(2 to 3); +rel_ovrd_lru(4) <= (rel_op_lru(4) and not rel_ovrd_wayCD(1)) or rel_ovrd_wayCD(0); +rel_ovrd_wayEF <= rel_lock_line(4 to 5); +rel_ovrd_lru(5) <= (rel_op_lru(5) and not rel_ovrd_wayEF(1)) or rel_ovrd_wayEF(0); +rel_ovrd_wayGH <= rel_lock_line(6 to 7); +rel_ovrd_lru(6) <= (rel_op_lru(6) and not rel_ovrd_wayGH(1)) or rel_ovrd_wayGH(0); +full_way(0) <= not rel_ovrd_lru(0) and not rel_ovrd_lru(1) and not rel_ovrd_lru(3); +full_way(1) <= not rel_ovrd_lru(0) and not rel_ovrd_lru(1) and rel_ovrd_lru(3); +full_way(2) <= not rel_ovrd_lru(0) and rel_ovrd_lru(1) and not rel_ovrd_lru(4); +full_way(3) <= not rel_ovrd_lru(0) and rel_ovrd_lru(1) and rel_ovrd_lru(4); +full_way(4) <= rel_ovrd_lru(0) and not rel_ovrd_lru(2) and not rel_ovrd_lru(5); +full_way(5) <= rel_ovrd_lru(0) and not rel_ovrd_lru(2) and rel_ovrd_lru(5); +full_way(6) <= rel_ovrd_lru(0) and rel_ovrd_lru(2) and not rel_ovrd_lru(6); +full_way(7) <= rel_ovrd_lru(0) and rel_ovrd_lru(2) and rel_ovrd_lru(6); +wayA_not_empty <= rel2_wayA_val or rel2_wlock_q(0) or rel_m_q_way_q(0); +wayB_not_empty <= rel2_wayB_val or rel2_wlock_q(1) or rel_m_q_way_q(1); +wayC_not_empty <= rel2_wayC_val or rel2_wlock_q(2) or rel_m_q_way_q(2); +wayD_not_empty <= rel2_wayD_val or rel2_wlock_q(3) or rel_m_q_way_q(3); +wayE_not_empty <= rel2_wayE_val or rel2_wlock_q(4) or rel_m_q_way_q(4); +wayF_not_empty <= rel2_wayF_val or rel2_wlock_q(5) or rel_m_q_way_q(5); +wayG_not_empty <= rel2_wayG_val or rel2_wlock_q(6) or rel_m_q_way_q(6); +wayH_not_empty <= rel2_wayH_val or rel2_wlock_q(7) or rel_m_q_way_q(7); +rel_way_not_empty_d <= wayA_not_empty & wayB_not_empty & wayC_not_empty & wayD_not_empty & + wayE_not_empty & wayF_not_empty & wayG_not_empty & wayH_not_empty; +congr_cl_full <= wayA_not_empty and wayB_not_empty and wayC_not_empty and wayD_not_empty and + wayE_not_empty and wayF_not_empty and wayG_not_empty and wayH_not_empty; +empty_way(0) <= not wayA_not_empty; +empty_way(1) <= ( wayA_not_empty and not wayB_not_empty); +empty_way(2) <= ( wayA_not_empty and wayB_not_empty and not wayC_not_empty); +empty_way(3) <= ( wayA_not_empty and wayB_not_empty and wayC_not_empty and not wayD_not_empty); +empty_way(4) <= ( wayA_not_empty and wayB_not_empty and wayC_not_empty and wayD_not_empty and + not wayE_not_empty); +empty_way(5) <= ( wayA_not_empty and wayB_not_empty and wayC_not_empty and wayD_not_empty and + wayE_not_empty and not wayF_not_empty); +empty_way(6) <= ( wayA_not_empty and wayB_not_empty and wayC_not_empty and wayD_not_empty and + wayE_not_empty and wayF_not_empty and not wayG_not_empty); +empty_way(7) <= ( wayA_not_empty and wayB_not_empty and wayC_not_empty and wayD_not_empty and + wayE_not_empty and wayF_not_empty and wayG_not_empty); +rel_hit <= gate(empty_way, not congr_cl_full) or gate(full_way, congr_cl_full); +rel_wayA_clr <= rel_hit(0) and rel2_val_q and not ovr_lock_det; +rel_wayB_clr <= rel_hit(1) and rel2_val_q and not ovr_lock_det; +rel_wayC_clr <= rel_hit(2) and rel2_val_q and not ovr_lock_det; +rel_wayD_clr <= rel_hit(3) and rel2_val_q and not ovr_lock_det; +rel_wayE_clr <= rel_hit(4) and rel2_val_q and not ovr_lock_det; +rel_wayF_clr <= rel_hit(5) and rel2_val_q and not ovr_lock_det; +rel_wayG_clr <= rel_hit(6) and rel2_val_q and not ovr_lock_det; +rel_wayH_clr <= rel_hit(7) and rel2_val_q and not ovr_lock_det; +rel_hit_vec <= rel_wayA_clr & rel_wayB_clr & rel_wayC_clr & rel_wayD_clr & + rel_wayE_clr & rel_wayF_clr & rel_wayG_clr & rel_wayH_clr; +rel_hit_wayA_upd <= "11" & rel_ovrd_lru(2) & "1" & rel_ovrd_lru(4 to 6); +rel_hit_wayB_upd <= "11" & rel_ovrd_lru(2) & "0" & rel_ovrd_lru(4 to 6); +rel_hit_wayC_upd <= "10" & rel_ovrd_lru(2 to 3) & "1" & rel_ovrd_lru(5 to 6); +rel_hit_wayD_upd <= "10" & rel_ovrd_lru(2 to 3) & "0" & rel_ovrd_lru(5 to 6); +rel_hit_wayE_upd <= "0" & rel_ovrd_lru(1) & "1" & rel_ovrd_lru(3 to 4) & "1" & rel_ovrd_lru(6); +rel_hit_wayF_upd <= "0" & rel_ovrd_lru(1) & "1" & rel_ovrd_lru(3 to 4) & "0" & rel_ovrd_lru(6); +rel_hit_wayG_upd <= "0" & rel_ovrd_lru(1) & "0" & rel_ovrd_lru(3 to 5) & "1"; +rel_hit_wayh_upd <= "0" & rel_ovrd_lru(1) & "0" & rel_ovrd_lru(3 to 5) & "0"; +rel_hit_lru_upd <= gate(rel_hit_wayA_upd, rel_hit_vec(0)) or gate(rel_hit_wayB_upd, rel_hit_vec(1)) or + gate(rel_hit_wayC_upd, rel_hit_vec(2)) or gate(rel_hit_wayD_upd, rel_hit_vec(3)) or + gate(rel_hit_wayE_upd, rel_hit_vec(4)) or gate(rel_hit_wayF_upd, rel_hit_vec(5)) or + gate(rel_hit_wayG_upd, rel_hit_vec(6)) or gate(rel_hit_wayH_upd, rel_hit_vec(7)); +relu_lru_upd_d <= rel_hit_lru_upd; +rel_lru_val_d <= relu_lru_upd_q; +reld_q0_chk_val <= (reld_q0_congr_cl_q = rel_congr_cl_stg_q) and reld_q0_val_q and rel2_val_q and not ovr_lock_det; +reld_q0_chk_way <= gate(reld_q0_way_q, reld_q0_chk_val); +reld_q0_way_m <= or_reduce((reld_q0_chk_way and rel_hit)); +reld_match(0) <= reld_q0_way_m; +reld_q0_set <= rel2_val_q and (rel_tag_q = tconv(0,3)); +reld_q0_inval <= (rel4_val_q and (not rel4_recirc_val or rel4_ecc_err) and reld_q_sel_q(0)) or reld_match(0); +reld_q0_val_sel <= reld_q0_set & reld_q0_inval; +with reld_q0_set select + reld_q0_congr_cl_d <= rel_congr_cl_stg_q when '1', + reld_q0_congr_cl_q when others; +with reld_q0_set select + reld_q0_way_d <= rel_hit_vec when '1', + reld_q0_way_q when others; +with reld_q0_val_sel select + reld_q0_val_d <= '0' when "01", + reld_q0_val_q when "00", + '1' when others; +reld_q_val(0) <= reld_q0_val_q; +with reld_q0_val_sel select + reld_q0_lock_d <= '0' when "01", + reld_q0_lock_q when "00", + rel2_lock_en_q when others; +reld_q_early_sel(0) <= (rel_st_tag_early = tconv(0,3)); +reld_q_sel_d(0) <= (rel_st_tag = tconv(0,3)); +reld_q1_chk_val <= (reld_q1_congr_cl_q = rel_congr_cl_stg_q) and reld_q1_val_q and rel2_val_q and not ovr_lock_det; +reld_q1_chk_way <= gate(reld_q1_way_q, reld_q1_chk_val); +reld_q1_way_m <= or_reduce((reld_q1_chk_way and rel_hit)); +reld_match(1) <= reld_q1_way_m; +reld_q1_set <= rel2_val_q and (rel_tag_q = tconv(1,3)); +reld_q1_inval <= (rel4_val_q and (not rel4_recirc_val or rel4_ecc_err) and reld_q_sel_q(1)) or reld_match(1); +reld_q1_val_sel <= reld_q1_set & reld_q1_inval; +with reld_q1_set select + reld_q1_congr_cl_d <= rel_congr_cl_stg_q when '1', + reld_q1_congr_cl_q when others; +with reld_q1_set select + reld_q1_way_d <= rel_hit_vec when '1', + reld_q1_way_q when others; +with reld_q1_val_sel select + reld_q1_val_d <= '0' when "01", + reld_q1_val_q when "00", + '1' when others; +reld_q_val(1) <= reld_q1_val_q; +with reld_q1_val_sel select + reld_q1_lock_d <= '0' when "01", + reld_q1_lock_q when "00", + rel2_lock_en_q when others; +reld_q_early_sel(1) <= (rel_st_tag_early = tconv(1,3)); +reld_q_sel_d(1) <= (rel_st_tag = tconv(1,3)); +reld_q2_chk_val <= (reld_q2_congr_cl_q = rel_congr_cl_stg_q) and reld_q2_val_q and rel2_val_q and not ovr_lock_det; +reld_q2_chk_way <= gate(reld_q2_way_q, reld_q2_chk_val); +reld_q2_way_m <= or_reduce((reld_q2_chk_way and rel_hit)); +reld_match(2) <= reld_q2_way_m; +reld_q2_set <= rel2_val_q and (rel_tag_q = tconv(2,3)); +reld_q2_inval <= (rel4_val_q and (not rel4_recirc_val or rel4_ecc_err) and reld_q_sel_q(2)) or reld_match(2); +reld_q2_val_sel <= reld_q2_set & reld_q2_inval; +with reld_q2_set select + reld_q2_congr_cl_d <= rel_congr_cl_stg_q when '1', + reld_q2_congr_cl_q when others; +with reld_q2_set select + reld_q2_way_d <= rel_hit_vec when '1', + reld_q2_way_q when others; +with reld_q2_val_sel select + reld_q2_val_d <= '0' when "01", + reld_q2_val_q when "00", + '1' when others; +reld_q_val(2) <= reld_q2_val_q; +with reld_q2_val_sel select + reld_q2_lock_d <= '0' when "01", + reld_q2_lock_q when "00", + rel2_lock_en_q when others; +reld_q_early_sel(2) <= (rel_st_tag_early = tconv(2,3)); +reld_q_sel_d(2) <= (rel_st_tag = tconv(2,3)); +reld_q3_chk_val <= (reld_q3_congr_cl_q = rel_congr_cl_stg_q) and reld_q3_val_q and rel2_val_q and not ovr_lock_det; +reld_q3_chk_way <= gate(reld_q3_way_q, reld_q3_chk_val); +reld_q3_way_m <= or_reduce((reld_q3_chk_way and rel_hit)); +reld_match(3) <= reld_q3_way_m; +reld_q3_set <= rel2_val_q and (rel_tag_q = tconv(3,3)); +reld_q3_inval <= (rel4_val_q and (not rel4_recirc_val or rel4_ecc_err) and reld_q_sel_q(3)) or reld_match(3); +reld_q3_val_sel <= reld_q3_set & reld_q3_inval; +with reld_q3_set select + reld_q3_congr_cl_d <= rel_congr_cl_stg_q when '1', + reld_q3_congr_cl_q when others; +with reld_q3_set select + reld_q3_way_d <= rel_hit_vec when '1', + reld_q3_way_q when others; +with reld_q3_val_sel select + reld_q3_val_d <= '0' when "01", + reld_q3_val_q when "00", + '1' when others; +reld_q_val(3) <= reld_q3_val_q; +with reld_q3_val_sel select + reld_q3_lock_d <= '0' when "01", + reld_q3_lock_q when "00", + rel2_lock_en_q when others; +reld_q_early_sel(3) <= (rel_st_tag_early = tconv(3,3)); +reld_q_sel_d(3) <= (rel_st_tag = tconv(3,3)); +reld_q4_chk_val <= (reld_q4_congr_cl_q = rel_congr_cl_stg_q) and reld_q4_val_q and rel2_val_q and not ovr_lock_det; +reld_q4_chk_way <= gate(reld_q4_way_q, reld_q4_chk_val); +reld_q4_way_m <= or_reduce((reld_q4_chk_way and rel_hit)); +reld_match(4) <= reld_q4_way_m; +reld_q4_set <= rel2_val_q and (rel_tag_q = tconv(4,3)); +reld_q4_inval <= (rel4_val_q and (not rel4_recirc_val or rel4_ecc_err) and reld_q_sel_q(4)) or reld_match(4); +reld_q4_val_sel <= reld_q4_set & reld_q4_inval; +with reld_q4_set select + reld_q4_congr_cl_d <= rel_congr_cl_stg_q when '1', + reld_q4_congr_cl_q when others; +with reld_q4_set select + reld_q4_way_d <= rel_hit_vec when '1', + reld_q4_way_q when others; +with reld_q4_val_sel select + reld_q4_val_d <= '0' when "01", + reld_q4_val_q when "00", + '1' when others; +reld_q_val(4) <= reld_q4_val_q; +with reld_q4_val_sel select + reld_q4_lock_d <= '0' when "01", + reld_q4_lock_q when "00", + rel2_lock_en_q when others; +reld_q_early_sel(4) <= (rel_st_tag_early = tconv(4,3)); +reld_q_sel_d(4) <= (rel_st_tag = tconv(4,3)); +reld_q5_chk_val <= (reld_q5_congr_cl_q = rel_congr_cl_stg_q) and reld_q5_val_q and rel2_val_q and not ovr_lock_det; +reld_q5_chk_way <= gate(reld_q5_way_q, reld_q5_chk_val); +reld_q5_way_m <= or_reduce((reld_q5_chk_way and rel_hit)); +reld_match(5) <= reld_q5_way_m; +reld_q5_set <= rel2_val_q and (rel_tag_q = tconv(5,3)); +reld_q5_inval <= (rel4_val_q and (not rel4_recirc_val or rel4_ecc_err) and reld_q_sel_q(5)) or reld_match(5); +reld_q5_val_sel <= reld_q5_set & reld_q5_inval; +with reld_q5_set select + reld_q5_congr_cl_d <= rel_congr_cl_stg_q when '1', + reld_q5_congr_cl_q when others; +with reld_q5_set select + reld_q5_way_d <= rel_hit_vec when '1', + reld_q5_way_q when others; +with reld_q5_val_sel select + reld_q5_val_d <= '0' when "01", + reld_q5_val_q when "00", + '1' when others; +reld_q_val(5) <= reld_q5_val_q; +with reld_q5_val_sel select + reld_q5_lock_d <= '0' when "01", + reld_q5_lock_q when "00", + rel2_lock_en_q when others; +reld_q_early_sel(5) <= (rel_st_tag_early = tconv(5,3)); +reld_q_sel_d(5) <= (rel_st_tag = tconv(5,3)); +reld_q6_chk_val <= (reld_q6_congr_cl_q = rel_congr_cl_stg_q) and reld_q6_val_q and rel2_val_q and not ovr_lock_det; +reld_q6_chk_way <= gate(reld_q6_way_q, reld_q6_chk_val); +reld_q6_way_m <= or_reduce((reld_q6_chk_way and rel_hit)); +reld_match(6) <= reld_q6_way_m; +reld_q6_set <= rel2_val_q and (rel_tag_q = tconv(6,3)); +reld_q6_inval <= (rel4_val_q and (not rel4_recirc_val or rel4_ecc_err) and reld_q_sel_q(6)) or reld_match(6); +reld_q6_val_sel <= reld_q6_set & reld_q6_inval; +with reld_q6_set select + reld_q6_congr_cl_d <= rel_congr_cl_stg_q when '1', + reld_q6_congr_cl_q when others; +with reld_q6_set select + reld_q6_way_d <= rel_hit_vec when '1', + reld_q6_way_q when others; +with reld_q6_val_sel select + reld_q6_val_d <= '0' when "01", + reld_q6_val_q when "00", + '1' when others; +reld_q_val(6) <= reld_q6_val_q; +with reld_q6_val_sel select + reld_q6_lock_d <= '0' when "01", + reld_q6_lock_q when "00", + rel2_lock_en_q when others; +reld_q_early_sel(6) <= (rel_st_tag_early = tconv(6,3)); +reld_q_sel_d(6) <= (rel_st_tag = tconv(6,3)); +reld_q7_chk_val <= (reld_q7_congr_cl_q = rel_congr_cl_stg_q) and reld_q7_val_q and rel2_val_q and not ovr_lock_det; +reld_q7_chk_way <= gate(reld_q7_way_q, reld_q7_chk_val); +reld_q7_way_m <= or_reduce((reld_q7_chk_way and rel_hit)); +reld_match(7) <= reld_q7_way_m; +reld_q7_set <= rel2_val_q and (rel_tag_q = tconv(7,3)); +reld_q7_inval <= (rel4_val_q and (not rel4_recirc_val or rel4_ecc_err) and reld_q_sel_q(7)) or reld_match(7); +reld_q7_val_sel <= reld_q7_set & reld_q7_inval; +with reld_q7_set select + reld_q7_congr_cl_d <= rel_congr_cl_stg_q when '1', + reld_q7_congr_cl_q when others; +with reld_q7_set select + reld_q7_way_d <= rel_hit_vec when '1', + reld_q7_way_q when others; +with reld_q7_val_sel select + reld_q7_val_d <= '0' when "01", + reld_q7_val_q when "00", + '1' when others; +reld_q_val(7) <= reld_q7_val_q; +with reld_q7_val_sel select + reld_q7_lock_d <= '0' when "01", + reld_q7_lock_q when "00", + rel2_lock_en_q when others; +reld_q_early_sel(7) <= (rel_st_tag_early = tconv(7,3)); +reld_q_sel_d(7) <= (rel_st_tag = tconv(7,3)); +rel_way_early_qsel <= gate(reld_q0_way_q, reld_q_early_sel(0)) or + gate(reld_q1_way_q, reld_q_early_sel(1)) or + gate(reld_q2_way_q, reld_q_early_sel(2)) or + gate(reld_q3_way_q, reld_q_early_sel(3)) or + gate(reld_q4_way_q, reld_q_early_sel(4)) or + gate(reld_q5_way_q, reld_q_early_sel(5)) or + gate(reld_q6_way_q, reld_q_early_sel(6)) or + gate(reld_q7_way_q, reld_q_early_sel(7)); +rel_val_early_qsel <= (reld_q0_val_q and reld_q_early_sel(0)) or + (reld_q1_val_q and reld_q_early_sel(1)) or + (reld_q2_val_q and reld_q_early_sel(2)) or + (reld_q3_val_q and reld_q_early_sel(3)) or + (reld_q4_val_q and reld_q_early_sel(4)) or + (reld_q5_val_q and reld_q_early_sel(5)) or + (reld_q6_val_q and reld_q_early_sel(6)) or + (reld_q7_val_q and reld_q_early_sel(7)); +reld_q_early_byp <= (rel_st_tag_early = rel_tag_q) and rel2_val_q; +reld_way_early_byp <= rel_hit_vec; +rel_way_early_qsel_d <= gate(rel_way_early_qsel, not reld_q_early_byp) or gate(reld_way_early_byp, reld_q_early_byp); +rel_val_early_qsel_d <= rel_val_early_qsel or reld_q_early_byp; +rel_way_qsel_d <= gate(reld_q0_way_q, reld_q_sel_d(0)) or + gate(reld_q1_way_q, reld_q_sel_d(1)) or + gate(reld_q2_way_q, reld_q_sel_d(2)) or + gate(reld_q3_way_q, reld_q_sel_d(3)) or + gate(reld_q4_way_q, reld_q_sel_d(4)) or + gate(reld_q5_way_q, reld_q_sel_d(5)) or + gate(reld_q6_way_q, reld_q_sel_d(6)) or + gate(reld_q7_way_q, reld_q_sel_d(7)); +rel_val_qsel_d <= (reld_q0_val_q and reld_q_sel_d(0) and not reld_match(0)) or + (reld_q1_val_q and reld_q_sel_d(1) and not reld_match(1)) or + (reld_q2_val_q and reld_q_sel_d(2) and not reld_match(2)) or + (reld_q3_val_q and reld_q_sel_d(3) and not reld_match(3)) or + (reld_q4_val_q and reld_q_sel_d(4) and not reld_match(4)) or + (reld_q5_val_q and reld_q_sel_d(5) and not reld_match(5)) or + (reld_q6_val_q and reld_q_sel_d(6) and not reld_match(6)) or + (reld_q7_val_q and reld_q_sel_d(7) and not reld_match(7)); +rel_wayA_upd <= rel_way_early_qsel_q(0) and rel_val_early_qsel_q; +rel_wayB_upd <= rel_way_early_qsel_q(1) and rel_val_early_qsel_q; +rel_wayC_upd <= rel_way_early_qsel_q(2) and rel_val_early_qsel_q; +rel_wayD_upd <= rel_way_early_qsel_q(3) and rel_val_early_qsel_q; +rel_wayE_upd <= rel_way_early_qsel_q(4) and rel_val_early_qsel_q; +rel_wayF_upd <= rel_way_early_qsel_q(5) and rel_val_early_qsel_q; +rel_wayG_upd <= rel_way_early_qsel_q(6) and rel_val_early_qsel_q; +rel_wayH_upd <= rel_way_early_qsel_q(7) and rel_val_early_qsel_q; +rel_wayA_set <= rel_way_qsel_q(0) and rel4_val_q and rel_val_qsel_q; +rel_wayB_set <= rel_way_qsel_q(1) and rel4_val_q and rel_val_qsel_q; +rel_wayC_set <= rel_way_qsel_q(2) and rel4_val_q and rel_val_qsel_q; +rel_wayD_set <= rel_way_qsel_q(3) and rel4_val_q and rel_val_qsel_q; +rel_wayE_set <= rel_way_qsel_q(4) and rel4_val_q and rel_val_qsel_q; +rel_wayF_set <= rel_way_qsel_q(5) and rel4_val_q and rel_val_qsel_q; +rel_wayG_set <= rel_way_qsel_q(6) and rel4_val_q and rel_val_qsel_q; +rel_wayH_set <= rel_way_qsel_q(7) and rel4_val_q and rel_val_qsel_q; +rel_wayA_mid <= rel_way_qsel_q(0) and rel2_mid_val_q and rel_val_qsel_q; +rel_wayB_mid <= rel_way_qsel_q(1) and rel2_mid_val_q and rel_val_qsel_q; +rel_wayC_mid <= rel_way_qsel_q(2) and rel2_mid_val_q and rel_val_qsel_q; +rel_wayD_mid <= rel_way_qsel_q(3) and rel2_mid_val_q and rel_val_qsel_q; +rel_wayE_mid <= rel_way_qsel_q(4) and rel2_mid_val_q and rel_val_qsel_q; +rel_wayF_mid <= rel_way_qsel_q(5) and rel2_mid_val_q and rel_val_qsel_q; +rel_wayG_mid <= rel_way_qsel_q(6) and rel2_mid_val_q and rel_val_qsel_q; +rel_wayH_mid <= rel_way_qsel_q(7) and rel2_mid_val_q and rel_val_qsel_q; +with ex3_congr_cl_q select + arr_congr_cl_lru <= + congr_cl0_lru_q when "000000", + congr_cl1_lru_q when "000001", + congr_cl2_lru_q when "000010", + congr_cl3_lru_q when "000011", + congr_cl4_lru_q when "000100", + congr_cl5_lru_q when "000101", + congr_cl6_lru_q when "000110", + congr_cl7_lru_q when "000111", + congr_cl8_lru_q when "001000", + congr_cl9_lru_q when "001001", + congr_cl10_lru_q when "001010", + congr_cl11_lru_q when "001011", + congr_cl12_lru_q when "001100", + congr_cl13_lru_q when "001101", + congr_cl14_lru_q when "001110", + congr_cl15_lru_q when "001111", + congr_cl16_lru_q when "010000", + congr_cl17_lru_q when "010001", + congr_cl18_lru_q when "010010", + congr_cl19_lru_q when "010011", + congr_cl20_lru_q when "010100", + congr_cl21_lru_q when "010101", + congr_cl22_lru_q when "010110", + congr_cl23_lru_q when "010111", + congr_cl24_lru_q when "011000", + congr_cl25_lru_q when "011001", + congr_cl26_lru_q when "011010", + congr_cl27_lru_q when "011011", + congr_cl28_lru_q when "011100", + congr_cl29_lru_q when "011101", + congr_cl30_lru_q when "011110", + congr_cl31_lru_q when "011111", + congr_cl32_lru_q when "100000", + congr_cl33_lru_q when "100001", + congr_cl34_lru_q when "100010", + congr_cl35_lru_q when "100011", + congr_cl36_lru_q when "100100", + congr_cl37_lru_q when "100101", + congr_cl38_lru_q when "100110", + congr_cl39_lru_q when "100111", + congr_cl40_lru_q when "101000", + congr_cl41_lru_q when "101001", + congr_cl42_lru_q when "101010", + congr_cl43_lru_q when "101011", + congr_cl44_lru_q when "101100", + congr_cl45_lru_q when "101101", + congr_cl46_lru_q when "101110", + congr_cl47_lru_q when "101111", + congr_cl48_lru_q when "110000", + congr_cl49_lru_q when "110001", + congr_cl50_lru_q when "110010", + congr_cl51_lru_q when "110011", + congr_cl52_lru_q when "110100", + congr_cl53_lru_q when "110101", + congr_cl54_lru_q when "110110", + congr_cl55_lru_q when "110111", + congr_cl56_lru_q when "111000", + congr_cl57_lru_q when "111001", + congr_cl58_lru_q when "111010", + congr_cl59_lru_q when "111011", + congr_cl60_lru_q when "111100", + congr_cl61_lru_q when "111101", + congr_cl62_lru_q when "111110", + congr_cl63_lru_q when others; +p0_arr_lru_rd <= arr_congr_cl_lru; +ex3_c_acc_val <= ex3_cache_en and not (ex3_no_lru_upd_q or spr_xucr0_dcdis or ex3_flush); +ex4_hit_d <= ex3_l1hit; +ex4_c_acc_d <= ex3_c_acc_val; +ex4_c_acc <= ex4_c_acc_q and ex4_hit_q; +ex4_c_acc_val <= ex4_c_acc and not ex4_flush; +ex5_c_acc_d <= ex4_c_acc_val; +ex5_c_acc_val <= ex5_c_acc_q and not ex5_flush; +ex6_c_acc_val_d <= ex5_c_acc_val; +congr_cl_ex3_ex4_cmp_d <= (ex2_congr_cl_q = ex3_congr_cl_q); +congr_cl_ex3_ex5_cmp_d <= (ex2_congr_cl_q = ex4_congr_cl_q); +congr_cl_ex3_ex6_cmp_d <= (ex2_congr_cl_q = ex5_congr_cl_q); +congr_cl_ex3_rel2_cmp_d <= (ex2_congr_cl_q = rel_congr_cl_q); +congr_cl_ex3_rel_upd_cmp_d <= (ex2_congr_cl_q = relu_congr_cl_q); +congr_cl_ex3_ex4_m <= congr_cl_ex3_ex4_cmp_q and ex4_c_acc; +congr_cl_ex3_ex5_m <= congr_cl_ex3_ex5_cmp_q and ex5_c_acc_q; +congr_cl_ex3_rel2_m <= congr_cl_ex3_rel2_cmp_q and rel2_val_q and not ovr_lock_det; +congr_cl_ex3_p0_m <= congr_cl_ex3_ex6_cmp_q and ex6_c_acc_val_q; +congr_cl_ex3_p1_m <= congr_cl_ex3_rel_upd_cmp_q and rel_val_wen_q; +congr_cl_ex3_byp(0) <= congr_cl_ex3_rel2_m; +congr_cl_ex3_byp(1) <= congr_cl_ex3_ex4_m; +congr_cl_ex3_byp(2) <= congr_cl_ex3_ex5_m; +congr_cl_ex3_byp(3) <= congr_cl_ex3_p1_m; +congr_cl_ex3_byp(4) <= congr_cl_ex3_p0_m; +ex4_fxubyp_val_d <= congr_cl_ex3_byp(1) or congr_cl_ex3_byp(2) or congr_cl_ex3_byp(4); +ex4_relbyp_val_d <= congr_cl_ex3_byp(0) or congr_cl_ex3_byp(3); +ex4_lru_byp_sel <= ex4_fxubyp_val_q & ex4_relbyp_val_q; +congr_cl_ex3_sel(1) <= congr_cl_ex3_byp(1); +congr_cl_ex3_sel(2) <= congr_cl_ex3_byp(2) and not congr_cl_ex3_byp(1); +congr_cl_ex3_sel(3) <= congr_cl_ex3_byp(3) and not or_reduce(congr_cl_ex3_byp(1 to 2)); +congr_cl_ex3_sel(4) <= congr_cl_ex3_byp(4) and not or_reduce(congr_cl_ex3_byp(1 to 3)); +lru_late_sel <= or_reduce(congr_cl_ex3_byp(1 to 4)); +lru_late_stg_pri <= gate(lru_upd, congr_cl_ex3_sel(1)) or + gate(ex5_lru_upd_q, congr_cl_ex3_sel(2)) or + gate(rel_lru_val_q, congr_cl_ex3_sel(3)) or + gate(ex6_lru_upd_q, congr_cl_ex3_sel(4)); +lru_late_stg_arr <= gate(p0_arr_lru_rd, not lru_late_sel) or lru_late_stg_pri; +lru_early_sel <= (others=>congr_cl_ex3_byp(0)); +lru_early_sel_b <= (others=>(not congr_cl_ex3_byp(0))); +xu_op_lru <= not congr_cl_lru_b_q; +ldst_hit_vector <= ldst_wayA_hit & ldst_wayB_hit & ldst_wayC_hit & ldst_wayD_hit & + ldst_wayE_hit & ldst_wayF_hit & ldst_wayG_hit & ldst_wayH_hit; +hit_wayA_upd <= "11" & xu_op_lru(2) & "1" & xu_op_lru(4 to 6); +hit_wayB_upd <= "11" & xu_op_lru(2) & "0" & xu_op_lru(4 to 6); +hit_wayC_upd <= "10" & xu_op_lru(2 to 3) & "1" & xu_op_lru(5 to 6); +hit_wayD_upd <= "10" & xu_op_lru(2 to 3) & "0" & xu_op_lru(5 to 6); +hit_wayE_upd <= "0" & xu_op_lru(1) & "1" & xu_op_lru(3 to 4) & "1" & xu_op_lru(6); +hit_wayF_upd <= "0" & xu_op_lru(1) & "1" & xu_op_lru(3 to 4) & "0" & xu_op_lru(6); +hit_wayG_upd <= "0" & xu_op_lru(1) & "0" & xu_op_lru(3 to 5) & "1"; +hit_wayh_upd <= "0" & xu_op_lru(1) & "0" & xu_op_lru(3 to 5) & "0"; +ldst_hit_vec_sel <= or_reduce(ldst_hit_vector); +ldst_hit_lru_upd <= gate(hit_wayA_upd, ldst_hit_vector(0)) or gate(hit_wayB_upd, ldst_hit_vector(1)) or + gate(hit_wayC_upd, ldst_hit_vector(2)) or gate(hit_wayD_upd, ldst_hit_vector(3)) or + gate(hit_wayE_upd, ldst_hit_vector(4)) or gate(hit_wayF_upd, ldst_hit_vector(5)) or + gate(hit_wayG_upd, ldst_hit_vector(6)) or gate(hit_wayH_upd, ldst_hit_vector(7)); +with ldst_hit_vec_sel select + lru_upd <= ldst_hit_lru_upd when '1', + xu_op_lru when others; +ex5_lru_upd_d <= lru_upd; +ex6_lru_upd_d <= ex5_lru_upd_q; +rel_way_dwen <= (rel_wayA_clr or rel_wayA_set or rel_wayA_mid) & (rel_wayB_clr or rel_wayB_set or rel_wayB_mid) & + (rel_wayC_clr or rel_wayC_set or rel_wayC_mid) & (rel_wayD_clr or rel_wayD_set or rel_wayD_mid) & + (rel_wayE_clr or rel_wayE_set or rel_wayE_mid) & (rel_wayF_clr or rel_wayF_set or rel_wayF_mid) & + (rel_wayG_clr or rel_wayG_set or rel_wayG_mid) & (rel_wayH_clr or rel_wayH_set or rel_wayH_mid); +rel24_way_dwen_stg_d <= rel_way_dwen; +rel_dcarr_val_upd_d <= or_reduce(rel_way_dwen) and not rel4_retry_val_q; +rel_up_way_addr_d <= gate("001", rel_way_dwen(1)) or + gate("010", rel_way_dwen(2)) or gate("011", rel_way_dwen(3)) or + gate("100", rel_way_dwen(4)) or gate("101", rel_way_dwen(5)) or + gate("110", rel_way_dwen(6)) or gate("111", rel_way_dwen(7)); +rel_up_way_addr_b <= not rel_up_way_addr_q; +rel_dcarr_addr_en <= rel_dcarr_addr_en_q; +congr_cl_act_d <= ex5_c_acc_q or relu_val_wen_q; +xu_op_cl0_lru_wen <= (ex6_congr_cl_q = tconv(0,6)) and ex6_c_acc_val_q; +rel_cl0_lru_wen <= (rel_upd_congr_cl_q = tconv(0,6)) and rel_val_wen_q; +congr_cl0_lru_wen <= xu_op_cl0_lru_wen or rel_cl0_lru_wen; +with rel_cl0_lru_wen select + rel_ldst_cl0_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl0_lru_wen select + congr_cl0_lru_d <= rel_ldst_cl0_lru when '1', + congr_cl0_lru_q when others; +xu_op_cl1_lru_wen <= (ex6_congr_cl_q = tconv(1,6)) and ex6_c_acc_val_q; +rel_cl1_lru_wen <= (rel_upd_congr_cl_q = tconv(1,6)) and rel_val_wen_q; +congr_cl1_lru_wen <= xu_op_cl1_lru_wen or rel_cl1_lru_wen; +with rel_cl1_lru_wen select + rel_ldst_cl1_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl1_lru_wen select + congr_cl1_lru_d <= rel_ldst_cl1_lru when '1', + congr_cl1_lru_q when others; +xu_op_cl2_lru_wen <= (ex6_congr_cl_q = tconv(2,6)) and ex6_c_acc_val_q; +rel_cl2_lru_wen <= (rel_upd_congr_cl_q = tconv(2,6)) and rel_val_wen_q; +congr_cl2_lru_wen <= xu_op_cl2_lru_wen or rel_cl2_lru_wen; +with rel_cl2_lru_wen select + rel_ldst_cl2_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl2_lru_wen select + congr_cl2_lru_d <= rel_ldst_cl2_lru when '1', + congr_cl2_lru_q when others; +xu_op_cl3_lru_wen <= (ex6_congr_cl_q = tconv(3,6)) and ex6_c_acc_val_q; +rel_cl3_lru_wen <= (rel_upd_congr_cl_q = tconv(3,6)) and rel_val_wen_q; +congr_cl3_lru_wen <= xu_op_cl3_lru_wen or rel_cl3_lru_wen; +with rel_cl3_lru_wen select + rel_ldst_cl3_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl3_lru_wen select + congr_cl3_lru_d <= rel_ldst_cl3_lru when '1', + congr_cl3_lru_q when others; +xu_op_cl4_lru_wen <= (ex6_congr_cl_q = tconv(4,6)) and ex6_c_acc_val_q; +rel_cl4_lru_wen <= (rel_upd_congr_cl_q = tconv(4,6)) and rel_val_wen_q; +congr_cl4_lru_wen <= xu_op_cl4_lru_wen or rel_cl4_lru_wen; +with rel_cl4_lru_wen select + rel_ldst_cl4_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl4_lru_wen select + congr_cl4_lru_d <= rel_ldst_cl4_lru when '1', + congr_cl4_lru_q when others; +xu_op_cl5_lru_wen <= (ex6_congr_cl_q = tconv(5,6)) and ex6_c_acc_val_q; +rel_cl5_lru_wen <= (rel_upd_congr_cl_q = tconv(5,6)) and rel_val_wen_q; +congr_cl5_lru_wen <= xu_op_cl5_lru_wen or rel_cl5_lru_wen; +with rel_cl5_lru_wen select + rel_ldst_cl5_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl5_lru_wen select + congr_cl5_lru_d <= rel_ldst_cl5_lru when '1', + congr_cl5_lru_q when others; +xu_op_cl6_lru_wen <= (ex6_congr_cl_q = tconv(6,6)) and ex6_c_acc_val_q; +rel_cl6_lru_wen <= (rel_upd_congr_cl_q = tconv(6,6)) and rel_val_wen_q; +congr_cl6_lru_wen <= xu_op_cl6_lru_wen or rel_cl6_lru_wen; +with rel_cl6_lru_wen select + rel_ldst_cl6_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl6_lru_wen select + congr_cl6_lru_d <= rel_ldst_cl6_lru when '1', + congr_cl6_lru_q when others; +xu_op_cl7_lru_wen <= (ex6_congr_cl_q = tconv(7,6)) and ex6_c_acc_val_q; +rel_cl7_lru_wen <= (rel_upd_congr_cl_q = tconv(7,6)) and rel_val_wen_q; +congr_cl7_lru_wen <= xu_op_cl7_lru_wen or rel_cl7_lru_wen; +with rel_cl7_lru_wen select + rel_ldst_cl7_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl7_lru_wen select + congr_cl7_lru_d <= rel_ldst_cl7_lru when '1', + congr_cl7_lru_q when others; +xu_op_cl8_lru_wen <= (ex6_congr_cl_q = tconv(8,6)) and ex6_c_acc_val_q; +rel_cl8_lru_wen <= (rel_upd_congr_cl_q = tconv(8,6)) and rel_val_wen_q; +congr_cl8_lru_wen <= xu_op_cl8_lru_wen or rel_cl8_lru_wen; +with rel_cl8_lru_wen select + rel_ldst_cl8_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl8_lru_wen select + congr_cl8_lru_d <= rel_ldst_cl8_lru when '1', + congr_cl8_lru_q when others; +xu_op_cl9_lru_wen <= (ex6_congr_cl_q = tconv(9,6)) and ex6_c_acc_val_q; +rel_cl9_lru_wen <= (rel_upd_congr_cl_q = tconv(9,6)) and rel_val_wen_q; +congr_cl9_lru_wen <= xu_op_cl9_lru_wen or rel_cl9_lru_wen; +with rel_cl9_lru_wen select + rel_ldst_cl9_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl9_lru_wen select + congr_cl9_lru_d <= rel_ldst_cl9_lru when '1', + congr_cl9_lru_q when others; +xu_op_cl10_lru_wen <= (ex6_congr_cl_q = tconv(10,6)) and ex6_c_acc_val_q; +rel_cl10_lru_wen <= (rel_upd_congr_cl_q = tconv(10,6)) and rel_val_wen_q; +congr_cl10_lru_wen <= xu_op_cl10_lru_wen or rel_cl10_lru_wen; +with rel_cl10_lru_wen select + rel_ldst_cl10_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl10_lru_wen select + congr_cl10_lru_d <= rel_ldst_cl10_lru when '1', + congr_cl10_lru_q when others; +xu_op_cl11_lru_wen <= (ex6_congr_cl_q = tconv(11,6)) and ex6_c_acc_val_q; +rel_cl11_lru_wen <= (rel_upd_congr_cl_q = tconv(11,6)) and rel_val_wen_q; +congr_cl11_lru_wen <= xu_op_cl11_lru_wen or rel_cl11_lru_wen; +with rel_cl11_lru_wen select + rel_ldst_cl11_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl11_lru_wen select + congr_cl11_lru_d <= rel_ldst_cl11_lru when '1', + congr_cl11_lru_q when others; +xu_op_cl12_lru_wen <= (ex6_congr_cl_q = tconv(12,6)) and ex6_c_acc_val_q; +rel_cl12_lru_wen <= (rel_upd_congr_cl_q = tconv(12,6)) and rel_val_wen_q; +congr_cl12_lru_wen <= xu_op_cl12_lru_wen or rel_cl12_lru_wen; +with rel_cl12_lru_wen select + rel_ldst_cl12_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl12_lru_wen select + congr_cl12_lru_d <= rel_ldst_cl12_lru when '1', + congr_cl12_lru_q when others; +xu_op_cl13_lru_wen <= (ex6_congr_cl_q = tconv(13,6)) and ex6_c_acc_val_q; +rel_cl13_lru_wen <= (rel_upd_congr_cl_q = tconv(13,6)) and rel_val_wen_q; +congr_cl13_lru_wen <= xu_op_cl13_lru_wen or rel_cl13_lru_wen; +with rel_cl13_lru_wen select + rel_ldst_cl13_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl13_lru_wen select + congr_cl13_lru_d <= rel_ldst_cl13_lru when '1', + congr_cl13_lru_q when others; +xu_op_cl14_lru_wen <= (ex6_congr_cl_q = tconv(14,6)) and ex6_c_acc_val_q; +rel_cl14_lru_wen <= (rel_upd_congr_cl_q = tconv(14,6)) and rel_val_wen_q; +congr_cl14_lru_wen <= xu_op_cl14_lru_wen or rel_cl14_lru_wen; +with rel_cl14_lru_wen select + rel_ldst_cl14_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl14_lru_wen select + congr_cl14_lru_d <= rel_ldst_cl14_lru when '1', + congr_cl14_lru_q when others; +xu_op_cl15_lru_wen <= (ex6_congr_cl_q = tconv(15,6)) and ex6_c_acc_val_q; +rel_cl15_lru_wen <= (rel_upd_congr_cl_q = tconv(15,6)) and rel_val_wen_q; +congr_cl15_lru_wen <= xu_op_cl15_lru_wen or rel_cl15_lru_wen; +with rel_cl15_lru_wen select + rel_ldst_cl15_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl15_lru_wen select + congr_cl15_lru_d <= rel_ldst_cl15_lru when '1', + congr_cl15_lru_q when others; +xu_op_cl16_lru_wen <= (ex6_congr_cl_q = tconv(16,6)) and ex6_c_acc_val_q; +rel_cl16_lru_wen <= (rel_upd_congr_cl_q = tconv(16,6)) and rel_val_wen_q; +congr_cl16_lru_wen <= xu_op_cl16_lru_wen or rel_cl16_lru_wen; +with rel_cl16_lru_wen select + rel_ldst_cl16_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl16_lru_wen select + congr_cl16_lru_d <= rel_ldst_cl16_lru when '1', + congr_cl16_lru_q when others; +xu_op_cl17_lru_wen <= (ex6_congr_cl_q = tconv(17,6)) and ex6_c_acc_val_q; +rel_cl17_lru_wen <= (rel_upd_congr_cl_q = tconv(17,6)) and rel_val_wen_q; +congr_cl17_lru_wen <= xu_op_cl17_lru_wen or rel_cl17_lru_wen; +with rel_cl17_lru_wen select + rel_ldst_cl17_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl17_lru_wen select + congr_cl17_lru_d <= rel_ldst_cl17_lru when '1', + congr_cl17_lru_q when others; +xu_op_cl18_lru_wen <= (ex6_congr_cl_q = tconv(18,6)) and ex6_c_acc_val_q; +rel_cl18_lru_wen <= (rel_upd_congr_cl_q = tconv(18,6)) and rel_val_wen_q; +congr_cl18_lru_wen <= xu_op_cl18_lru_wen or rel_cl18_lru_wen; +with rel_cl18_lru_wen select + rel_ldst_cl18_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl18_lru_wen select + congr_cl18_lru_d <= rel_ldst_cl18_lru when '1', + congr_cl18_lru_q when others; +xu_op_cl19_lru_wen <= (ex6_congr_cl_q = tconv(19,6)) and ex6_c_acc_val_q; +rel_cl19_lru_wen <= (rel_upd_congr_cl_q = tconv(19,6)) and rel_val_wen_q; +congr_cl19_lru_wen <= xu_op_cl19_lru_wen or rel_cl19_lru_wen; +with rel_cl19_lru_wen select + rel_ldst_cl19_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl19_lru_wen select + congr_cl19_lru_d <= rel_ldst_cl19_lru when '1', + congr_cl19_lru_q when others; +xu_op_cl20_lru_wen <= (ex6_congr_cl_q = tconv(20,6)) and ex6_c_acc_val_q; +rel_cl20_lru_wen <= (rel_upd_congr_cl_q = tconv(20,6)) and rel_val_wen_q; +congr_cl20_lru_wen <= xu_op_cl20_lru_wen or rel_cl20_lru_wen; +with rel_cl20_lru_wen select + rel_ldst_cl20_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl20_lru_wen select + congr_cl20_lru_d <= rel_ldst_cl20_lru when '1', + congr_cl20_lru_q when others; +xu_op_cl21_lru_wen <= (ex6_congr_cl_q = tconv(21,6)) and ex6_c_acc_val_q; +rel_cl21_lru_wen <= (rel_upd_congr_cl_q = tconv(21,6)) and rel_val_wen_q; +congr_cl21_lru_wen <= xu_op_cl21_lru_wen or rel_cl21_lru_wen; +with rel_cl21_lru_wen select + rel_ldst_cl21_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl21_lru_wen select + congr_cl21_lru_d <= rel_ldst_cl21_lru when '1', + congr_cl21_lru_q when others; +xu_op_cl22_lru_wen <= (ex6_congr_cl_q = tconv(22,6)) and ex6_c_acc_val_q; +rel_cl22_lru_wen <= (rel_upd_congr_cl_q = tconv(22,6)) and rel_val_wen_q; +congr_cl22_lru_wen <= xu_op_cl22_lru_wen or rel_cl22_lru_wen; +with rel_cl22_lru_wen select + rel_ldst_cl22_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl22_lru_wen select + congr_cl22_lru_d <= rel_ldst_cl22_lru when '1', + congr_cl22_lru_q when others; +xu_op_cl23_lru_wen <= (ex6_congr_cl_q = tconv(23,6)) and ex6_c_acc_val_q; +rel_cl23_lru_wen <= (rel_upd_congr_cl_q = tconv(23,6)) and rel_val_wen_q; +congr_cl23_lru_wen <= xu_op_cl23_lru_wen or rel_cl23_lru_wen; +with rel_cl23_lru_wen select + rel_ldst_cl23_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl23_lru_wen select + congr_cl23_lru_d <= rel_ldst_cl23_lru when '1', + congr_cl23_lru_q when others; +xu_op_cl24_lru_wen <= (ex6_congr_cl_q = tconv(24,6)) and ex6_c_acc_val_q; +rel_cl24_lru_wen <= (rel_upd_congr_cl_q = tconv(24,6)) and rel_val_wen_q; +congr_cl24_lru_wen <= xu_op_cl24_lru_wen or rel_cl24_lru_wen; +with rel_cl24_lru_wen select + rel_ldst_cl24_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl24_lru_wen select + congr_cl24_lru_d <= rel_ldst_cl24_lru when '1', + congr_cl24_lru_q when others; +xu_op_cl25_lru_wen <= (ex6_congr_cl_q = tconv(25,6)) and ex6_c_acc_val_q; +rel_cl25_lru_wen <= (rel_upd_congr_cl_q = tconv(25,6)) and rel_val_wen_q; +congr_cl25_lru_wen <= xu_op_cl25_lru_wen or rel_cl25_lru_wen; +with rel_cl25_lru_wen select + rel_ldst_cl25_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl25_lru_wen select + congr_cl25_lru_d <= rel_ldst_cl25_lru when '1', + congr_cl25_lru_q when others; +xu_op_cl26_lru_wen <= (ex6_congr_cl_q = tconv(26,6)) and ex6_c_acc_val_q; +rel_cl26_lru_wen <= (rel_upd_congr_cl_q = tconv(26,6)) and rel_val_wen_q; +congr_cl26_lru_wen <= xu_op_cl26_lru_wen or rel_cl26_lru_wen; +with rel_cl26_lru_wen select + rel_ldst_cl26_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl26_lru_wen select + congr_cl26_lru_d <= rel_ldst_cl26_lru when '1', + congr_cl26_lru_q when others; +xu_op_cl27_lru_wen <= (ex6_congr_cl_q = tconv(27,6)) and ex6_c_acc_val_q; +rel_cl27_lru_wen <= (rel_upd_congr_cl_q = tconv(27,6)) and rel_val_wen_q; +congr_cl27_lru_wen <= xu_op_cl27_lru_wen or rel_cl27_lru_wen; +with rel_cl27_lru_wen select + rel_ldst_cl27_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl27_lru_wen select + congr_cl27_lru_d <= rel_ldst_cl27_lru when '1', + congr_cl27_lru_q when others; +xu_op_cl28_lru_wen <= (ex6_congr_cl_q = tconv(28,6)) and ex6_c_acc_val_q; +rel_cl28_lru_wen <= (rel_upd_congr_cl_q = tconv(28,6)) and rel_val_wen_q; +congr_cl28_lru_wen <= xu_op_cl28_lru_wen or rel_cl28_lru_wen; +with rel_cl28_lru_wen select + rel_ldst_cl28_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl28_lru_wen select + congr_cl28_lru_d <= rel_ldst_cl28_lru when '1', + congr_cl28_lru_q when others; +xu_op_cl29_lru_wen <= (ex6_congr_cl_q = tconv(29,6)) and ex6_c_acc_val_q; +rel_cl29_lru_wen <= (rel_upd_congr_cl_q = tconv(29,6)) and rel_val_wen_q; +congr_cl29_lru_wen <= xu_op_cl29_lru_wen or rel_cl29_lru_wen; +with rel_cl29_lru_wen select + rel_ldst_cl29_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl29_lru_wen select + congr_cl29_lru_d <= rel_ldst_cl29_lru when '1', + congr_cl29_lru_q when others; +xu_op_cl30_lru_wen <= (ex6_congr_cl_q = tconv(30,6)) and ex6_c_acc_val_q; +rel_cl30_lru_wen <= (rel_upd_congr_cl_q = tconv(30,6)) and rel_val_wen_q; +congr_cl30_lru_wen <= xu_op_cl30_lru_wen or rel_cl30_lru_wen; +with rel_cl30_lru_wen select + rel_ldst_cl30_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl30_lru_wen select + congr_cl30_lru_d <= rel_ldst_cl30_lru when '1', + congr_cl30_lru_q when others; +xu_op_cl31_lru_wen <= (ex6_congr_cl_q = tconv(31,6)) and ex6_c_acc_val_q; +rel_cl31_lru_wen <= (rel_upd_congr_cl_q = tconv(31,6)) and rel_val_wen_q; +congr_cl31_lru_wen <= xu_op_cl31_lru_wen or rel_cl31_lru_wen; +with rel_cl31_lru_wen select + rel_ldst_cl31_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl31_lru_wen select + congr_cl31_lru_d <= rel_ldst_cl31_lru when '1', + congr_cl31_lru_q when others; +xu_op_cl32_lru_wen <= (ex6_congr_cl_q = tconv(32,6)) and ex6_c_acc_val_q; +rel_cl32_lru_wen <= (rel_upd_congr_cl_q = tconv(32,6)) and rel_val_wen_q; +congr_cl32_lru_wen <= xu_op_cl32_lru_wen or rel_cl32_lru_wen; +with rel_cl32_lru_wen select + rel_ldst_cl32_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl32_lru_wen select + congr_cl32_lru_d <= rel_ldst_cl32_lru when '1', + congr_cl32_lru_q when others; +xu_op_cl33_lru_wen <= (ex6_congr_cl_q = tconv(33,6)) and ex6_c_acc_val_q; +rel_cl33_lru_wen <= (rel_upd_congr_cl_q = tconv(33,6)) and rel_val_wen_q; +congr_cl33_lru_wen <= xu_op_cl33_lru_wen or rel_cl33_lru_wen; +with rel_cl33_lru_wen select + rel_ldst_cl33_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl33_lru_wen select + congr_cl33_lru_d <= rel_ldst_cl33_lru when '1', + congr_cl33_lru_q when others; +xu_op_cl34_lru_wen <= (ex6_congr_cl_q = tconv(34,6)) and ex6_c_acc_val_q; +rel_cl34_lru_wen <= (rel_upd_congr_cl_q = tconv(34,6)) and rel_val_wen_q; +congr_cl34_lru_wen <= xu_op_cl34_lru_wen or rel_cl34_lru_wen; +with rel_cl34_lru_wen select + rel_ldst_cl34_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl34_lru_wen select + congr_cl34_lru_d <= rel_ldst_cl34_lru when '1', + congr_cl34_lru_q when others; +xu_op_cl35_lru_wen <= (ex6_congr_cl_q = tconv(35,6)) and ex6_c_acc_val_q; +rel_cl35_lru_wen <= (rel_upd_congr_cl_q = tconv(35,6)) and rel_val_wen_q; +congr_cl35_lru_wen <= xu_op_cl35_lru_wen or rel_cl35_lru_wen; +with rel_cl35_lru_wen select + rel_ldst_cl35_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl35_lru_wen select + congr_cl35_lru_d <= rel_ldst_cl35_lru when '1', + congr_cl35_lru_q when others; +xu_op_cl36_lru_wen <= (ex6_congr_cl_q = tconv(36,6)) and ex6_c_acc_val_q; +rel_cl36_lru_wen <= (rel_upd_congr_cl_q = tconv(36,6)) and rel_val_wen_q; +congr_cl36_lru_wen <= xu_op_cl36_lru_wen or rel_cl36_lru_wen; +with rel_cl36_lru_wen select + rel_ldst_cl36_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl36_lru_wen select + congr_cl36_lru_d <= rel_ldst_cl36_lru when '1', + congr_cl36_lru_q when others; +xu_op_cl37_lru_wen <= (ex6_congr_cl_q = tconv(37,6)) and ex6_c_acc_val_q; +rel_cl37_lru_wen <= (rel_upd_congr_cl_q = tconv(37,6)) and rel_val_wen_q; +congr_cl37_lru_wen <= xu_op_cl37_lru_wen or rel_cl37_lru_wen; +with rel_cl37_lru_wen select + rel_ldst_cl37_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl37_lru_wen select + congr_cl37_lru_d <= rel_ldst_cl37_lru when '1', + congr_cl37_lru_q when others; +xu_op_cl38_lru_wen <= (ex6_congr_cl_q = tconv(38,6)) and ex6_c_acc_val_q; +rel_cl38_lru_wen <= (rel_upd_congr_cl_q = tconv(38,6)) and rel_val_wen_q; +congr_cl38_lru_wen <= xu_op_cl38_lru_wen or rel_cl38_lru_wen; +with rel_cl38_lru_wen select + rel_ldst_cl38_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl38_lru_wen select + congr_cl38_lru_d <= rel_ldst_cl38_lru when '1', + congr_cl38_lru_q when others; +xu_op_cl39_lru_wen <= (ex6_congr_cl_q = tconv(39,6)) and ex6_c_acc_val_q; +rel_cl39_lru_wen <= (rel_upd_congr_cl_q = tconv(39,6)) and rel_val_wen_q; +congr_cl39_lru_wen <= xu_op_cl39_lru_wen or rel_cl39_lru_wen; +with rel_cl39_lru_wen select + rel_ldst_cl39_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl39_lru_wen select + congr_cl39_lru_d <= rel_ldst_cl39_lru when '1', + congr_cl39_lru_q when others; +xu_op_cl40_lru_wen <= (ex6_congr_cl_q = tconv(40,6)) and ex6_c_acc_val_q; +rel_cl40_lru_wen <= (rel_upd_congr_cl_q = tconv(40,6)) and rel_val_wen_q; +congr_cl40_lru_wen <= xu_op_cl40_lru_wen or rel_cl40_lru_wen; +with rel_cl40_lru_wen select + rel_ldst_cl40_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl40_lru_wen select + congr_cl40_lru_d <= rel_ldst_cl40_lru when '1', + congr_cl40_lru_q when others; +xu_op_cl41_lru_wen <= (ex6_congr_cl_q = tconv(41,6)) and ex6_c_acc_val_q; +rel_cl41_lru_wen <= (rel_upd_congr_cl_q = tconv(41,6)) and rel_val_wen_q; +congr_cl41_lru_wen <= xu_op_cl41_lru_wen or rel_cl41_lru_wen; +with rel_cl41_lru_wen select + rel_ldst_cl41_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl41_lru_wen select + congr_cl41_lru_d <= rel_ldst_cl41_lru when '1', + congr_cl41_lru_q when others; +xu_op_cl42_lru_wen <= (ex6_congr_cl_q = tconv(42,6)) and ex6_c_acc_val_q; +rel_cl42_lru_wen <= (rel_upd_congr_cl_q = tconv(42,6)) and rel_val_wen_q; +congr_cl42_lru_wen <= xu_op_cl42_lru_wen or rel_cl42_lru_wen; +with rel_cl42_lru_wen select + rel_ldst_cl42_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl42_lru_wen select + congr_cl42_lru_d <= rel_ldst_cl42_lru when '1', + congr_cl42_lru_q when others; +xu_op_cl43_lru_wen <= (ex6_congr_cl_q = tconv(43,6)) and ex6_c_acc_val_q; +rel_cl43_lru_wen <= (rel_upd_congr_cl_q = tconv(43,6)) and rel_val_wen_q; +congr_cl43_lru_wen <= xu_op_cl43_lru_wen or rel_cl43_lru_wen; +with rel_cl43_lru_wen select + rel_ldst_cl43_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl43_lru_wen select + congr_cl43_lru_d <= rel_ldst_cl43_lru when '1', + congr_cl43_lru_q when others; +xu_op_cl44_lru_wen <= (ex6_congr_cl_q = tconv(44,6)) and ex6_c_acc_val_q; +rel_cl44_lru_wen <= (rel_upd_congr_cl_q = tconv(44,6)) and rel_val_wen_q; +congr_cl44_lru_wen <= xu_op_cl44_lru_wen or rel_cl44_lru_wen; +with rel_cl44_lru_wen select + rel_ldst_cl44_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl44_lru_wen select + congr_cl44_lru_d <= rel_ldst_cl44_lru when '1', + congr_cl44_lru_q when others; +xu_op_cl45_lru_wen <= (ex6_congr_cl_q = tconv(45,6)) and ex6_c_acc_val_q; +rel_cl45_lru_wen <= (rel_upd_congr_cl_q = tconv(45,6)) and rel_val_wen_q; +congr_cl45_lru_wen <= xu_op_cl45_lru_wen or rel_cl45_lru_wen; +with rel_cl45_lru_wen select + rel_ldst_cl45_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl45_lru_wen select + congr_cl45_lru_d <= rel_ldst_cl45_lru when '1', + congr_cl45_lru_q when others; +xu_op_cl46_lru_wen <= (ex6_congr_cl_q = tconv(46,6)) and ex6_c_acc_val_q; +rel_cl46_lru_wen <= (rel_upd_congr_cl_q = tconv(46,6)) and rel_val_wen_q; +congr_cl46_lru_wen <= xu_op_cl46_lru_wen or rel_cl46_lru_wen; +with rel_cl46_lru_wen select + rel_ldst_cl46_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl46_lru_wen select + congr_cl46_lru_d <= rel_ldst_cl46_lru when '1', + congr_cl46_lru_q when others; +xu_op_cl47_lru_wen <= (ex6_congr_cl_q = tconv(47,6)) and ex6_c_acc_val_q; +rel_cl47_lru_wen <= (rel_upd_congr_cl_q = tconv(47,6)) and rel_val_wen_q; +congr_cl47_lru_wen <= xu_op_cl47_lru_wen or rel_cl47_lru_wen; +with rel_cl47_lru_wen select + rel_ldst_cl47_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl47_lru_wen select + congr_cl47_lru_d <= rel_ldst_cl47_lru when '1', + congr_cl47_lru_q when others; +xu_op_cl48_lru_wen <= (ex6_congr_cl_q = tconv(48,6)) and ex6_c_acc_val_q; +rel_cl48_lru_wen <= (rel_upd_congr_cl_q = tconv(48,6)) and rel_val_wen_q; +congr_cl48_lru_wen <= xu_op_cl48_lru_wen or rel_cl48_lru_wen; +with rel_cl48_lru_wen select + rel_ldst_cl48_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl48_lru_wen select + congr_cl48_lru_d <= rel_ldst_cl48_lru when '1', + congr_cl48_lru_q when others; +xu_op_cl49_lru_wen <= (ex6_congr_cl_q = tconv(49,6)) and ex6_c_acc_val_q; +rel_cl49_lru_wen <= (rel_upd_congr_cl_q = tconv(49,6)) and rel_val_wen_q; +congr_cl49_lru_wen <= xu_op_cl49_lru_wen or rel_cl49_lru_wen; +with rel_cl49_lru_wen select + rel_ldst_cl49_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl49_lru_wen select + congr_cl49_lru_d <= rel_ldst_cl49_lru when '1', + congr_cl49_lru_q when others; +xu_op_cl50_lru_wen <= (ex6_congr_cl_q = tconv(50,6)) and ex6_c_acc_val_q; +rel_cl50_lru_wen <= (rel_upd_congr_cl_q = tconv(50,6)) and rel_val_wen_q; +congr_cl50_lru_wen <= xu_op_cl50_lru_wen or rel_cl50_lru_wen; +with rel_cl50_lru_wen select + rel_ldst_cl50_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl50_lru_wen select + congr_cl50_lru_d <= rel_ldst_cl50_lru when '1', + congr_cl50_lru_q when others; +xu_op_cl51_lru_wen <= (ex6_congr_cl_q = tconv(51,6)) and ex6_c_acc_val_q; +rel_cl51_lru_wen <= (rel_upd_congr_cl_q = tconv(51,6)) and rel_val_wen_q; +congr_cl51_lru_wen <= xu_op_cl51_lru_wen or rel_cl51_lru_wen; +with rel_cl51_lru_wen select + rel_ldst_cl51_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl51_lru_wen select + congr_cl51_lru_d <= rel_ldst_cl51_lru when '1', + congr_cl51_lru_q when others; +xu_op_cl52_lru_wen <= (ex6_congr_cl_q = tconv(52,6)) and ex6_c_acc_val_q; +rel_cl52_lru_wen <= (rel_upd_congr_cl_q = tconv(52,6)) and rel_val_wen_q; +congr_cl52_lru_wen <= xu_op_cl52_lru_wen or rel_cl52_lru_wen; +with rel_cl52_lru_wen select + rel_ldst_cl52_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl52_lru_wen select + congr_cl52_lru_d <= rel_ldst_cl52_lru when '1', + congr_cl52_lru_q when others; +xu_op_cl53_lru_wen <= (ex6_congr_cl_q = tconv(53,6)) and ex6_c_acc_val_q; +rel_cl53_lru_wen <= (rel_upd_congr_cl_q = tconv(53,6)) and rel_val_wen_q; +congr_cl53_lru_wen <= xu_op_cl53_lru_wen or rel_cl53_lru_wen; +with rel_cl53_lru_wen select + rel_ldst_cl53_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl53_lru_wen select + congr_cl53_lru_d <= rel_ldst_cl53_lru when '1', + congr_cl53_lru_q when others; +xu_op_cl54_lru_wen <= (ex6_congr_cl_q = tconv(54,6)) and ex6_c_acc_val_q; +rel_cl54_lru_wen <= (rel_upd_congr_cl_q = tconv(54,6)) and rel_val_wen_q; +congr_cl54_lru_wen <= xu_op_cl54_lru_wen or rel_cl54_lru_wen; +with rel_cl54_lru_wen select + rel_ldst_cl54_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl54_lru_wen select + congr_cl54_lru_d <= rel_ldst_cl54_lru when '1', + congr_cl54_lru_q when others; +xu_op_cl55_lru_wen <= (ex6_congr_cl_q = tconv(55,6)) and ex6_c_acc_val_q; +rel_cl55_lru_wen <= (rel_upd_congr_cl_q = tconv(55,6)) and rel_val_wen_q; +congr_cl55_lru_wen <= xu_op_cl55_lru_wen or rel_cl55_lru_wen; +with rel_cl55_lru_wen select + rel_ldst_cl55_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl55_lru_wen select + congr_cl55_lru_d <= rel_ldst_cl55_lru when '1', + congr_cl55_lru_q when others; +xu_op_cl56_lru_wen <= (ex6_congr_cl_q = tconv(56,6)) and ex6_c_acc_val_q; +rel_cl56_lru_wen <= (rel_upd_congr_cl_q = tconv(56,6)) and rel_val_wen_q; +congr_cl56_lru_wen <= xu_op_cl56_lru_wen or rel_cl56_lru_wen; +with rel_cl56_lru_wen select + rel_ldst_cl56_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl56_lru_wen select + congr_cl56_lru_d <= rel_ldst_cl56_lru when '1', + congr_cl56_lru_q when others; +xu_op_cl57_lru_wen <= (ex6_congr_cl_q = tconv(57,6)) and ex6_c_acc_val_q; +rel_cl57_lru_wen <= (rel_upd_congr_cl_q = tconv(57,6)) and rel_val_wen_q; +congr_cl57_lru_wen <= xu_op_cl57_lru_wen or rel_cl57_lru_wen; +with rel_cl57_lru_wen select + rel_ldst_cl57_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl57_lru_wen select + congr_cl57_lru_d <= rel_ldst_cl57_lru when '1', + congr_cl57_lru_q when others; +xu_op_cl58_lru_wen <= (ex6_congr_cl_q = tconv(58,6)) and ex6_c_acc_val_q; +rel_cl58_lru_wen <= (rel_upd_congr_cl_q = tconv(58,6)) and rel_val_wen_q; +congr_cl58_lru_wen <= xu_op_cl58_lru_wen or rel_cl58_lru_wen; +with rel_cl58_lru_wen select + rel_ldst_cl58_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl58_lru_wen select + congr_cl58_lru_d <= rel_ldst_cl58_lru when '1', + congr_cl58_lru_q when others; +xu_op_cl59_lru_wen <= (ex6_congr_cl_q = tconv(59,6)) and ex6_c_acc_val_q; +rel_cl59_lru_wen <= (rel_upd_congr_cl_q = tconv(59,6)) and rel_val_wen_q; +congr_cl59_lru_wen <= xu_op_cl59_lru_wen or rel_cl59_lru_wen; +with rel_cl59_lru_wen select + rel_ldst_cl59_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl59_lru_wen select + congr_cl59_lru_d <= rel_ldst_cl59_lru when '1', + congr_cl59_lru_q when others; +xu_op_cl60_lru_wen <= (ex6_congr_cl_q = tconv(60,6)) and ex6_c_acc_val_q; +rel_cl60_lru_wen <= (rel_upd_congr_cl_q = tconv(60,6)) and rel_val_wen_q; +congr_cl60_lru_wen <= xu_op_cl60_lru_wen or rel_cl60_lru_wen; +with rel_cl60_lru_wen select + rel_ldst_cl60_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl60_lru_wen select + congr_cl60_lru_d <= rel_ldst_cl60_lru when '1', + congr_cl60_lru_q when others; +xu_op_cl61_lru_wen <= (ex6_congr_cl_q = tconv(61,6)) and ex6_c_acc_val_q; +rel_cl61_lru_wen <= (rel_upd_congr_cl_q = tconv(61,6)) and rel_val_wen_q; +congr_cl61_lru_wen <= xu_op_cl61_lru_wen or rel_cl61_lru_wen; +with rel_cl61_lru_wen select + rel_ldst_cl61_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl61_lru_wen select + congr_cl61_lru_d <= rel_ldst_cl61_lru when '1', + congr_cl61_lru_q when others; +xu_op_cl62_lru_wen <= (ex6_congr_cl_q = tconv(62,6)) and ex6_c_acc_val_q; +rel_cl62_lru_wen <= (rel_upd_congr_cl_q = tconv(62,6)) and rel_val_wen_q; +congr_cl62_lru_wen <= xu_op_cl62_lru_wen or rel_cl62_lru_wen; +with rel_cl62_lru_wen select + rel_ldst_cl62_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl62_lru_wen select + congr_cl62_lru_d <= rel_ldst_cl62_lru when '1', + congr_cl62_lru_q when others; +xu_op_cl63_lru_wen <= (ex6_congr_cl_q = tconv(63,6)) and ex6_c_acc_val_q; +rel_cl63_lru_wen <= (rel_upd_congr_cl_q = tconv(63,6)) and rel_val_wen_q; +congr_cl63_lru_wen <= xu_op_cl63_lru_wen or rel_cl63_lru_wen; +with rel_cl63_lru_wen select + rel_ldst_cl63_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +with congr_cl63_lru_wen select + congr_cl63_lru_d <= rel_ldst_cl63_lru when '1', + congr_cl63_lru_q when others; +rel_way_clr_a <= rel_wayA_clr; +rel_way_clr_b <= rel_wayB_clr; +rel_way_clr_c <= rel_wayC_clr; +rel_way_clr_d <= rel_wayD_clr; +rel_way_clr_e <= rel_wayE_clr; +rel_way_clr_f <= rel_wayF_clr; +rel_way_clr_g <= rel_wayG_clr; +rel_way_clr_h <= rel_wayH_clr; +rel_way_upd_a <= rel_wayA_upd; +rel_way_upd_b <= rel_wayB_upd; +rel_way_upd_c <= rel_wayC_upd; +rel_way_upd_d <= rel_wayD_upd; +rel_way_upd_e <= rel_wayE_upd; +rel_way_upd_f <= rel_wayF_upd; +rel_way_upd_g <= rel_wayG_upd; +rel_way_upd_h <= rel_wayH_upd; +rel_way_wen_a <= rel_wayA_set; +rel_way_wen_b <= rel_wayB_set; +rel_way_wen_c <= rel_wayC_set; +rel_way_wen_d <= rel_wayD_set; +rel_way_wen_e <= rel_wayE_set; +rel_way_wen_f <= rel_wayF_set; +rel_way_wen_g <= rel_wayG_set; +rel_way_wen_h <= rel_wayH_set; +rel_dcarr_val_upd <= rel_dcarr_val_upd_q; +lsu_xu_spr_xucr0_clo <= xucr0_clo_q; +ex4_dir_lru <= xu_op_lru; +dc_lru_dbg_data <= rel24_way_dwen_stg_q & reld_q_val & rel_m_q_way_q & rel2_wlock_q & + rel_way_not_empty_q & ex4_lru_byp_sel & rel2_lru_byp_sel & rel_val_wen_q & + rel_op_lru & rel_lru_val_q & xucr0_clo_q & xu_op_lru & + ex6_c_acc_val_q & ex6_lru_upd_q & rel2_class_id_q & rel_tag_q & + rel4_retry_val_q & ex4_c_acc; +congr_cl0_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl0_lru_offset to congr_cl0_lru_offset + congr_cl0_lru_d'length-1), + scout => sov(congr_cl0_lru_offset to congr_cl0_lru_offset + congr_cl0_lru_d'length-1), + din => congr_cl0_lru_d, + dout => congr_cl0_lru_q); +congr_cl1_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl1_lru_offset to congr_cl1_lru_offset + congr_cl1_lru_d'length-1), + scout => sov(congr_cl1_lru_offset to congr_cl1_lru_offset + congr_cl1_lru_d'length-1), + din => congr_cl1_lru_d, + dout => congr_cl1_lru_q); +congr_cl2_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl2_lru_offset to congr_cl2_lru_offset + congr_cl2_lru_d'length-1), + scout => sov(congr_cl2_lru_offset to congr_cl2_lru_offset + congr_cl2_lru_d'length-1), + din => congr_cl2_lru_d, + dout => congr_cl2_lru_q); +congr_cl3_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl3_lru_offset to congr_cl3_lru_offset + congr_cl3_lru_d'length-1), + scout => sov(congr_cl3_lru_offset to congr_cl3_lru_offset + congr_cl3_lru_d'length-1), + din => congr_cl3_lru_d, + dout => congr_cl3_lru_q); +congr_cl4_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl4_lru_offset to congr_cl4_lru_offset + congr_cl4_lru_d'length-1), + scout => sov(congr_cl4_lru_offset to congr_cl4_lru_offset + congr_cl4_lru_d'length-1), + din => congr_cl4_lru_d, + dout => congr_cl4_lru_q); +congr_cl5_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl5_lru_offset to congr_cl5_lru_offset + congr_cl5_lru_d'length-1), + scout => sov(congr_cl5_lru_offset to congr_cl5_lru_offset + congr_cl5_lru_d'length-1), + din => congr_cl5_lru_d, + dout => congr_cl5_lru_q); +congr_cl6_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl6_lru_offset to congr_cl6_lru_offset + congr_cl6_lru_d'length-1), + scout => sov(congr_cl6_lru_offset to congr_cl6_lru_offset + congr_cl6_lru_d'length-1), + din => congr_cl6_lru_d, + dout => congr_cl6_lru_q); +congr_cl7_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl7_lru_offset to congr_cl7_lru_offset + congr_cl7_lru_d'length-1), + scout => sov(congr_cl7_lru_offset to congr_cl7_lru_offset + congr_cl7_lru_d'length-1), + din => congr_cl7_lru_d, + dout => congr_cl7_lru_q); +congr_cl8_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl8_lru_offset to congr_cl8_lru_offset + congr_cl8_lru_d'length-1), + scout => sov(congr_cl8_lru_offset to congr_cl8_lru_offset + congr_cl8_lru_d'length-1), + din => congr_cl8_lru_d, + dout => congr_cl8_lru_q); +congr_cl9_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl9_lru_offset to congr_cl9_lru_offset + congr_cl9_lru_d'length-1), + scout => sov(congr_cl9_lru_offset to congr_cl9_lru_offset + congr_cl9_lru_d'length-1), + din => congr_cl9_lru_d, + dout => congr_cl9_lru_q); +congr_cl10_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl10_lru_offset to congr_cl10_lru_offset + congr_cl10_lru_d'length-1), + scout => sov(congr_cl10_lru_offset to congr_cl10_lru_offset + congr_cl10_lru_d'length-1), + din => congr_cl10_lru_d, + dout => congr_cl10_lru_q); +congr_cl11_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl11_lru_offset to congr_cl11_lru_offset + congr_cl11_lru_d'length-1), + scout => sov(congr_cl11_lru_offset to congr_cl11_lru_offset + congr_cl11_lru_d'length-1), + din => congr_cl11_lru_d, + dout => congr_cl11_lru_q); +congr_cl12_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl12_lru_offset to congr_cl12_lru_offset + congr_cl12_lru_d'length-1), + scout => sov(congr_cl12_lru_offset to congr_cl12_lru_offset + congr_cl12_lru_d'length-1), + din => congr_cl12_lru_d, + dout => congr_cl12_lru_q); +congr_cl13_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl13_lru_offset to congr_cl13_lru_offset + congr_cl13_lru_d'length-1), + scout => sov(congr_cl13_lru_offset to congr_cl13_lru_offset + congr_cl13_lru_d'length-1), + din => congr_cl13_lru_d, + dout => congr_cl13_lru_q); +congr_cl14_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl14_lru_offset to congr_cl14_lru_offset + congr_cl14_lru_d'length-1), + scout => sov(congr_cl14_lru_offset to congr_cl14_lru_offset + congr_cl14_lru_d'length-1), + din => congr_cl14_lru_d, + dout => congr_cl14_lru_q); +congr_cl15_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl15_lru_offset to congr_cl15_lru_offset + congr_cl15_lru_d'length-1), + scout => sov(congr_cl15_lru_offset to congr_cl15_lru_offset + congr_cl15_lru_d'length-1), + din => congr_cl15_lru_d, + dout => congr_cl15_lru_q); +congr_cl16_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl16_lru_offset to congr_cl16_lru_offset + congr_cl16_lru_d'length-1), + scout => sov(congr_cl16_lru_offset to congr_cl16_lru_offset + congr_cl16_lru_d'length-1), + din => congr_cl16_lru_d, + dout => congr_cl16_lru_q); +congr_cl17_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl17_lru_offset to congr_cl17_lru_offset + congr_cl17_lru_d'length-1), + scout => sov(congr_cl17_lru_offset to congr_cl17_lru_offset + congr_cl17_lru_d'length-1), + din => congr_cl17_lru_d, + dout => congr_cl17_lru_q); +congr_cl18_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl18_lru_offset to congr_cl18_lru_offset + congr_cl18_lru_d'length-1), + scout => sov(congr_cl18_lru_offset to congr_cl18_lru_offset + congr_cl18_lru_d'length-1), + din => congr_cl18_lru_d, + dout => congr_cl18_lru_q); +congr_cl19_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl19_lru_offset to congr_cl19_lru_offset + congr_cl19_lru_d'length-1), + scout => sov(congr_cl19_lru_offset to congr_cl19_lru_offset + congr_cl19_lru_d'length-1), + din => congr_cl19_lru_d, + dout => congr_cl19_lru_q); +congr_cl20_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl20_lru_offset to congr_cl20_lru_offset + congr_cl20_lru_d'length-1), + scout => sov(congr_cl20_lru_offset to congr_cl20_lru_offset + congr_cl20_lru_d'length-1), + din => congr_cl20_lru_d, + dout => congr_cl20_lru_q); +congr_cl21_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl21_lru_offset to congr_cl21_lru_offset + congr_cl21_lru_d'length-1), + scout => sov(congr_cl21_lru_offset to congr_cl21_lru_offset + congr_cl21_lru_d'length-1), + din => congr_cl21_lru_d, + dout => congr_cl21_lru_q); +congr_cl22_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl22_lru_offset to congr_cl22_lru_offset + congr_cl22_lru_d'length-1), + scout => sov(congr_cl22_lru_offset to congr_cl22_lru_offset + congr_cl22_lru_d'length-1), + din => congr_cl22_lru_d, + dout => congr_cl22_lru_q); +congr_cl23_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl23_lru_offset to congr_cl23_lru_offset + congr_cl23_lru_d'length-1), + scout => sov(congr_cl23_lru_offset to congr_cl23_lru_offset + congr_cl23_lru_d'length-1), + din => congr_cl23_lru_d, + dout => congr_cl23_lru_q); +congr_cl24_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl24_lru_offset to congr_cl24_lru_offset + congr_cl24_lru_d'length-1), + scout => sov(congr_cl24_lru_offset to congr_cl24_lru_offset + congr_cl24_lru_d'length-1), + din => congr_cl24_lru_d, + dout => congr_cl24_lru_q); +congr_cl25_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl25_lru_offset to congr_cl25_lru_offset + congr_cl25_lru_d'length-1), + scout => sov(congr_cl25_lru_offset to congr_cl25_lru_offset + congr_cl25_lru_d'length-1), + din => congr_cl25_lru_d, + dout => congr_cl25_lru_q); +congr_cl26_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl26_lru_offset to congr_cl26_lru_offset + congr_cl26_lru_d'length-1), + scout => sov(congr_cl26_lru_offset to congr_cl26_lru_offset + congr_cl26_lru_d'length-1), + din => congr_cl26_lru_d, + dout => congr_cl26_lru_q); +congr_cl27_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl27_lru_offset to congr_cl27_lru_offset + congr_cl27_lru_d'length-1), + scout => sov(congr_cl27_lru_offset to congr_cl27_lru_offset + congr_cl27_lru_d'length-1), + din => congr_cl27_lru_d, + dout => congr_cl27_lru_q); +congr_cl28_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl28_lru_offset to congr_cl28_lru_offset + congr_cl28_lru_d'length-1), + scout => sov(congr_cl28_lru_offset to congr_cl28_lru_offset + congr_cl28_lru_d'length-1), + din => congr_cl28_lru_d, + dout => congr_cl28_lru_q); +congr_cl29_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl29_lru_offset to congr_cl29_lru_offset + congr_cl29_lru_d'length-1), + scout => sov(congr_cl29_lru_offset to congr_cl29_lru_offset + congr_cl29_lru_d'length-1), + din => congr_cl29_lru_d, + dout => congr_cl29_lru_q); +congr_cl30_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl30_lru_offset to congr_cl30_lru_offset + congr_cl30_lru_d'length-1), + scout => sov(congr_cl30_lru_offset to congr_cl30_lru_offset + congr_cl30_lru_d'length-1), + din => congr_cl30_lru_d, + dout => congr_cl30_lru_q); +congr_cl31_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl31_lru_offset to congr_cl31_lru_offset + congr_cl31_lru_d'length-1), + scout => sov(congr_cl31_lru_offset to congr_cl31_lru_offset + congr_cl31_lru_d'length-1), + din => congr_cl31_lru_d, + dout => congr_cl31_lru_q); +congr_cl32_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl32_lru_offset to congr_cl32_lru_offset + congr_cl32_lru_d'length-1), + scout => sov(congr_cl32_lru_offset to congr_cl32_lru_offset + congr_cl32_lru_d'length-1), + din => congr_cl32_lru_d, + dout => congr_cl32_lru_q); +congr_cl33_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl33_lru_offset to congr_cl33_lru_offset + congr_cl33_lru_d'length-1), + scout => sov(congr_cl33_lru_offset to congr_cl33_lru_offset + congr_cl33_lru_d'length-1), + din => congr_cl33_lru_d, + dout => congr_cl33_lru_q); +congr_cl34_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl34_lru_offset to congr_cl34_lru_offset + congr_cl34_lru_d'length-1), + scout => sov(congr_cl34_lru_offset to congr_cl34_lru_offset + congr_cl34_lru_d'length-1), + din => congr_cl34_lru_d, + dout => congr_cl34_lru_q); +congr_cl35_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl35_lru_offset to congr_cl35_lru_offset + congr_cl35_lru_d'length-1), + scout => sov(congr_cl35_lru_offset to congr_cl35_lru_offset + congr_cl35_lru_d'length-1), + din => congr_cl35_lru_d, + dout => congr_cl35_lru_q); +congr_cl36_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl36_lru_offset to congr_cl36_lru_offset + congr_cl36_lru_d'length-1), + scout => sov(congr_cl36_lru_offset to congr_cl36_lru_offset + congr_cl36_lru_d'length-1), + din => congr_cl36_lru_d, + dout => congr_cl36_lru_q); +congr_cl37_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl37_lru_offset to congr_cl37_lru_offset + congr_cl37_lru_d'length-1), + scout => sov(congr_cl37_lru_offset to congr_cl37_lru_offset + congr_cl37_lru_d'length-1), + din => congr_cl37_lru_d, + dout => congr_cl37_lru_q); +congr_cl38_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl38_lru_offset to congr_cl38_lru_offset + congr_cl38_lru_d'length-1), + scout => sov(congr_cl38_lru_offset to congr_cl38_lru_offset + congr_cl38_lru_d'length-1), + din => congr_cl38_lru_d, + dout => congr_cl38_lru_q); +congr_cl39_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl39_lru_offset to congr_cl39_lru_offset + congr_cl39_lru_d'length-1), + scout => sov(congr_cl39_lru_offset to congr_cl39_lru_offset + congr_cl39_lru_d'length-1), + din => congr_cl39_lru_d, + dout => congr_cl39_lru_q); +congr_cl40_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl40_lru_offset to congr_cl40_lru_offset + congr_cl40_lru_d'length-1), + scout => sov(congr_cl40_lru_offset to congr_cl40_lru_offset + congr_cl40_lru_d'length-1), + din => congr_cl40_lru_d, + dout => congr_cl40_lru_q); +congr_cl41_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl41_lru_offset to congr_cl41_lru_offset + congr_cl41_lru_d'length-1), + scout => sov(congr_cl41_lru_offset to congr_cl41_lru_offset + congr_cl41_lru_d'length-1), + din => congr_cl41_lru_d, + dout => congr_cl41_lru_q); +congr_cl42_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl42_lru_offset to congr_cl42_lru_offset + congr_cl42_lru_d'length-1), + scout => sov(congr_cl42_lru_offset to congr_cl42_lru_offset + congr_cl42_lru_d'length-1), + din => congr_cl42_lru_d, + dout => congr_cl42_lru_q); +congr_cl43_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl43_lru_offset to congr_cl43_lru_offset + congr_cl43_lru_d'length-1), + scout => sov(congr_cl43_lru_offset to congr_cl43_lru_offset + congr_cl43_lru_d'length-1), + din => congr_cl43_lru_d, + dout => congr_cl43_lru_q); +congr_cl44_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl44_lru_offset to congr_cl44_lru_offset + congr_cl44_lru_d'length-1), + scout => sov(congr_cl44_lru_offset to congr_cl44_lru_offset + congr_cl44_lru_d'length-1), + din => congr_cl44_lru_d, + dout => congr_cl44_lru_q); +congr_cl45_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl45_lru_offset to congr_cl45_lru_offset + congr_cl45_lru_d'length-1), + scout => sov(congr_cl45_lru_offset to congr_cl45_lru_offset + congr_cl45_lru_d'length-1), + din => congr_cl45_lru_d, + dout => congr_cl45_lru_q); +congr_cl46_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl46_lru_offset to congr_cl46_lru_offset + congr_cl46_lru_d'length-1), + scout => sov(congr_cl46_lru_offset to congr_cl46_lru_offset + congr_cl46_lru_d'length-1), + din => congr_cl46_lru_d, + dout => congr_cl46_lru_q); +congr_cl47_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl47_lru_offset to congr_cl47_lru_offset + congr_cl47_lru_d'length-1), + scout => sov(congr_cl47_lru_offset to congr_cl47_lru_offset + congr_cl47_lru_d'length-1), + din => congr_cl47_lru_d, + dout => congr_cl47_lru_q); +congr_cl48_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl48_lru_offset to congr_cl48_lru_offset + congr_cl48_lru_d'length-1), + scout => sov(congr_cl48_lru_offset to congr_cl48_lru_offset + congr_cl48_lru_d'length-1), + din => congr_cl48_lru_d, + dout => congr_cl48_lru_q); +congr_cl49_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl49_lru_offset to congr_cl49_lru_offset + congr_cl49_lru_d'length-1), + scout => sov(congr_cl49_lru_offset to congr_cl49_lru_offset + congr_cl49_lru_d'length-1), + din => congr_cl49_lru_d, + dout => congr_cl49_lru_q); +congr_cl50_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl50_lru_offset to congr_cl50_lru_offset + congr_cl50_lru_d'length-1), + scout => sov(congr_cl50_lru_offset to congr_cl50_lru_offset + congr_cl50_lru_d'length-1), + din => congr_cl50_lru_d, + dout => congr_cl50_lru_q); +congr_cl51_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl51_lru_offset to congr_cl51_lru_offset + congr_cl51_lru_d'length-1), + scout => sov(congr_cl51_lru_offset to congr_cl51_lru_offset + congr_cl51_lru_d'length-1), + din => congr_cl51_lru_d, + dout => congr_cl51_lru_q); +congr_cl52_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl52_lru_offset to congr_cl52_lru_offset + congr_cl52_lru_d'length-1), + scout => sov(congr_cl52_lru_offset to congr_cl52_lru_offset + congr_cl52_lru_d'length-1), + din => congr_cl52_lru_d, + dout => congr_cl52_lru_q); +congr_cl53_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl53_lru_offset to congr_cl53_lru_offset + congr_cl53_lru_d'length-1), + scout => sov(congr_cl53_lru_offset to congr_cl53_lru_offset + congr_cl53_lru_d'length-1), + din => congr_cl53_lru_d, + dout => congr_cl53_lru_q); +congr_cl54_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl54_lru_offset to congr_cl54_lru_offset + congr_cl54_lru_d'length-1), + scout => sov(congr_cl54_lru_offset to congr_cl54_lru_offset + congr_cl54_lru_d'length-1), + din => congr_cl54_lru_d, + dout => congr_cl54_lru_q); +congr_cl55_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl55_lru_offset to congr_cl55_lru_offset + congr_cl55_lru_d'length-1), + scout => sov(congr_cl55_lru_offset to congr_cl55_lru_offset + congr_cl55_lru_d'length-1), + din => congr_cl55_lru_d, + dout => congr_cl55_lru_q); +congr_cl56_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl56_lru_offset to congr_cl56_lru_offset + congr_cl56_lru_d'length-1), + scout => sov(congr_cl56_lru_offset to congr_cl56_lru_offset + congr_cl56_lru_d'length-1), + din => congr_cl56_lru_d, + dout => congr_cl56_lru_q); +congr_cl57_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl57_lru_offset to congr_cl57_lru_offset + congr_cl57_lru_d'length-1), + scout => sov(congr_cl57_lru_offset to congr_cl57_lru_offset + congr_cl57_lru_d'length-1), + din => congr_cl57_lru_d, + dout => congr_cl57_lru_q); +congr_cl58_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl58_lru_offset to congr_cl58_lru_offset + congr_cl58_lru_d'length-1), + scout => sov(congr_cl58_lru_offset to congr_cl58_lru_offset + congr_cl58_lru_d'length-1), + din => congr_cl58_lru_d, + dout => congr_cl58_lru_q); +congr_cl59_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl59_lru_offset to congr_cl59_lru_offset + congr_cl59_lru_d'length-1), + scout => sov(congr_cl59_lru_offset to congr_cl59_lru_offset + congr_cl59_lru_d'length-1), + din => congr_cl59_lru_d, + dout => congr_cl59_lru_q); +congr_cl60_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl60_lru_offset to congr_cl60_lru_offset + congr_cl60_lru_d'length-1), + scout => sov(congr_cl60_lru_offset to congr_cl60_lru_offset + congr_cl60_lru_d'length-1), + din => congr_cl60_lru_d, + dout => congr_cl60_lru_q); +congr_cl61_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl61_lru_offset to congr_cl61_lru_offset + congr_cl61_lru_d'length-1), + scout => sov(congr_cl61_lru_offset to congr_cl61_lru_offset + congr_cl61_lru_d'length-1), + din => congr_cl61_lru_d, + dout => congr_cl61_lru_q); +congr_cl62_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl62_lru_offset to congr_cl62_lru_offset + congr_cl62_lru_d'length-1), + scout => sov(congr_cl62_lru_offset to congr_cl62_lru_offset + congr_cl62_lru_d'length-1), + din => congr_cl62_lru_d, + dout => congr_cl62_lru_q); +congr_cl63_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl63_lru_offset to congr_cl63_lru_offset + congr_cl63_lru_d'length-1), + scout => sov(congr_cl63_lru_offset to congr_cl63_lru_offset + congr_cl63_lru_d'length-1), + din => congr_cl63_lru_d, + dout => congr_cl63_lru_q); +congr_cl_lru_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_lru_b_offset to congr_cl_lru_b_offset + congr_cl_lru_b_q'length-1), + scout => sov(congr_cl_lru_b_offset to congr_cl_lru_b_offset + congr_cl_lru_b_q'length-1), + a1 => rel_hit_lru_upd, + a2 => lru_early_sel, + b1 => lru_late_stg_arr, + b2 => lru_early_sel_b, + qb => congr_cl_lru_b_q); +rel_congr_cl_lru_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_congr_cl_lru_b_offset to rel_congr_cl_lru_b_offset + rel_congr_cl_lru_b_q'length-1), + scout => sov(rel_congr_cl_lru_b_offset to rel_congr_cl_lru_b_offset + rel_congr_cl_lru_b_q'length-1), + a1 => rel_hit_lru_upd, + a2 => rel_lru_early_sel, + b1 => rel_lru_late_stg_arr, + b2 => rel_lru_early_sel_b, + qb => rel_congr_cl_lru_b_q); +reld_q_sel_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q_sel_offset to reld_q_sel_offset + reld_q_sel_d'length-1), + scout => sov(reld_q_sel_offset to reld_q_sel_offset + reld_q_sel_d'length-1), + din => reld_q_sel_d, + dout => reld_q_sel_q); +ex4_congr_cl_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex4_congr_cl_d, + dout => ex4_congr_cl_q); +ex5_congr_cl_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_congr_cl_offset to ex5_congr_cl_offset + ex5_congr_cl_d'length-1), + scout => sov(ex5_congr_cl_offset to ex5_congr_cl_offset + ex5_congr_cl_d'length-1), + din => ex5_congr_cl_d, + dout => ex5_congr_cl_q); +ex6_congr_cl_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex5_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex6_congr_cl_d, + dout => ex6_congr_cl_q); +rel_congr_cl_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_congr_cl_offset to rel_congr_cl_offset + rel_congr_cl_d'length-1), + scout => sov(rel_congr_cl_offset to rel_congr_cl_offset + rel_congr_cl_d'length-1), + din => rel_congr_cl_d, + dout => rel_congr_cl_q); +rel_congr_cl_stg_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_congr_cl_stg_d, + dout => rel_congr_cl_stg_q); +relu_congr_cl_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(relu_congr_cl_offset to relu_congr_cl_offset + relu_congr_cl_d'length-1), + scout => sov(relu_congr_cl_offset to relu_congr_cl_offset + relu_congr_cl_d'length-1), + din => relu_congr_cl_d, + dout => relu_congr_cl_q); +ex5_lru_upd_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_lru_upd_offset to ex5_lru_upd_offset + ex5_lru_upd_d'length-1), + scout => sov(ex5_lru_upd_offset to ex5_lru_upd_offset + ex5_lru_upd_d'length-1), + din => ex5_lru_upd_d, + dout => ex5_lru_upd_q); +ex6_lru_upd_reg: tri_regk +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex5_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex6_lru_upd_d, + dout => ex6_lru_upd_q); +rel2_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel2_val_offset), + scout => sov(rel2_val_offset), + din => rel2_val_d, + dout => rel2_val_q); +rel2_class_id_reg: tri_regk +generic map (width => 2, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel2_class_id_d, + dout => rel2_class_id_q); +relu_val_wen_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(relu_val_wen_offset), + scout => sov(relu_val_wen_offset), + din => relu_val_wen_d, + dout => relu_val_wen_q); +ex4_hit_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_hit_offset), + scout => sov(ex4_hit_offset), + din => ex4_hit_d, + dout => ex4_hit_q); +ex4_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex4_fxubyp_val_d, + dout(0) => ex4_fxubyp_val_q); +ex4_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex4_relbyp_val_d, + dout(0) => ex4_relbyp_val_q); +ex4_c_acc_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_c_acc_offset), + scout => sov(ex4_c_acc_offset), + din => ex4_c_acc_d, + dout => ex4_c_acc_q); +ex5_c_acc_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_c_acc_offset), + scout => sov(ex5_c_acc_offset), + din => ex5_c_acc_d, + dout => ex5_c_acc_q); +ex6_c_acc_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_c_acc_val_offset), + scout => sov(ex6_c_acc_val_offset), + din => ex6_c_acc_val_d, + dout => ex6_c_acc_val_q); +ex2_congr_cl_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex2_congr_cl_d, + dout => ex2_congr_cl_q); +ex3_congr_cl_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_congr_cl_offset to ex3_congr_cl_offset + ex3_congr_cl_d'length-1), + scout => sov(ex3_congr_cl_offset to ex3_congr_cl_offset + ex3_congr_cl_d'length-1), + din => ex3_congr_cl_d, + dout => ex3_congr_cl_q); +rel_val_wen_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_val_wen_offset), + scout => sov(rel_val_wen_offset), + din => rel_val_wen_d, + dout => rel_val_wen_q); +rel_way_not_empty_reg: tri_regk +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_way_not_empty_d, + dout => rel_way_not_empty_q); +relu_lru_upd_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(relu_lru_upd_offset to relu_lru_upd_offset + relu_lru_upd_d'length-1), + scout => sov(relu_lru_upd_offset to relu_lru_upd_offset + relu_lru_upd_d'length-1), + din => relu_lru_upd_d, + dout => relu_lru_upd_q); +rel_lru_val_reg: tri_regk +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_lru_val_d, + dout => rel_lru_val_q); +rel_upd_congr_cl_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_upd_congr_cl_d, + dout => rel_upd_congr_cl_q); +rel_tag_reg: tri_regk +generic map (width => 3, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_tag_d, + dout => rel_tag_q); +rel_way_qsel_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_way_qsel_offset to rel_way_qsel_offset + rel_way_qsel_d'length-1), + scout => sov(rel_way_qsel_offset to rel_way_qsel_offset + rel_way_qsel_d'length-1), + din => rel_way_qsel_d, + dout => rel_way_qsel_q); +rel_val_qsel_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_val_qsel_offset), + scout => sov(rel_val_qsel_offset), + din => rel_val_qsel_d, + dout => rel_val_qsel_q); +rel_way_early_qsel_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_way_early_qsel_offset to rel_way_early_qsel_offset + rel_way_early_qsel_d'length-1), + scout => sov(rel_way_early_qsel_offset to rel_way_early_qsel_offset + rel_way_early_qsel_d'length-1), + din => rel_way_early_qsel_d, + dout => rel_way_early_qsel_q); +rel_val_early_qsel_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_val_early_qsel_offset), + scout => sov(rel_val_early_qsel_offset), + din => rel_val_early_qsel_d, + dout => rel_val_early_qsel_q); +rel4_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel4_val_offset), + scout => sov(rel4_val_offset), + din => rel4_val_d, + dout => rel4_val_q); +rel2_mid_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel2_mid_val_offset), + scout => sov(rel2_mid_val_offset), + din => rel2_mid_val_d, + dout => rel2_mid_val_q); +rel4_retry_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel4_retry_val_offset), + scout => sov(rel4_retry_val_offset), + din => rel4_retry_val_d, + dout => rel4_retry_val_q); +rel2_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel2_fxubyp_val_d, + dout(0) => rel2_fxubyp_val_q); +rel2_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel2_relbyp_val_d, + dout(0) => rel2_relbyp_val_q); +rel2_wlock_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel2_wlock_offset to rel2_wlock_offset + rel2_wlock_d'length-1), + scout => sov(rel2_wlock_offset to rel2_wlock_offset + rel2_wlock_d'length-1), + din => rel2_wlock_d, + dout => rel2_wlock_q); +reld_q0_congr_cl_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q0_congr_cl_offset to reld_q0_congr_cl_offset + reld_q0_congr_cl_d'length-1), + scout => sov(reld_q0_congr_cl_offset to reld_q0_congr_cl_offset + reld_q0_congr_cl_d'length-1), + din => reld_q0_congr_cl_d, + dout => reld_q0_congr_cl_q); +reld_q0_way_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q0_way_offset to reld_q0_way_offset + reld_q0_way_d'length-1), + scout => sov(reld_q0_way_offset to reld_q0_way_offset + reld_q0_way_d'length-1), + din => reld_q0_way_d, + dout => reld_q0_way_q); +reld_q0_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q0_val_offset), + scout => sov(reld_q0_val_offset), + din => reld_q0_val_d, + dout => reld_q0_val_q); +reld_q0_lock_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q0_lock_offset), + scout => sov(reld_q0_lock_offset), + din => reld_q0_lock_d, + dout => reld_q0_lock_q); +reld_q1_congr_cl_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q1_congr_cl_offset to reld_q1_congr_cl_offset + reld_q1_congr_cl_d'length-1), + scout => sov(reld_q1_congr_cl_offset to reld_q1_congr_cl_offset + reld_q1_congr_cl_d'length-1), + din => reld_q1_congr_cl_d, + dout => reld_q1_congr_cl_q); +reld_q1_way_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q1_way_offset to reld_q1_way_offset + reld_q1_way_d'length-1), + scout => sov(reld_q1_way_offset to reld_q1_way_offset + reld_q1_way_d'length-1), + din => reld_q1_way_d, + dout => reld_q1_way_q); +reld_q1_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q1_val_offset), + scout => sov(reld_q1_val_offset), + din => reld_q1_val_d, + dout => reld_q1_val_q); +reld_q1_lock_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q1_lock_offset), + scout => sov(reld_q1_lock_offset), + din => reld_q1_lock_d, + dout => reld_q1_lock_q); +reld_q2_congr_cl_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q2_congr_cl_offset to reld_q2_congr_cl_offset + reld_q2_congr_cl_d'length-1), + scout => sov(reld_q2_congr_cl_offset to reld_q2_congr_cl_offset + reld_q2_congr_cl_d'length-1), + din => reld_q2_congr_cl_d, + dout => reld_q2_congr_cl_q); +reld_q2_way_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q2_way_offset to reld_q2_way_offset + reld_q2_way_d'length-1), + scout => sov(reld_q2_way_offset to reld_q2_way_offset + reld_q2_way_d'length-1), + din => reld_q2_way_d, + dout => reld_q2_way_q); +reld_q2_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q2_val_offset), + scout => sov(reld_q2_val_offset), + din => reld_q2_val_d, + dout => reld_q2_val_q); +reld_q2_lock_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q2_lock_offset), + scout => sov(reld_q2_lock_offset), + din => reld_q2_lock_d, + dout => reld_q2_lock_q); +reld_q3_congr_cl_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q3_congr_cl_offset to reld_q3_congr_cl_offset + reld_q3_congr_cl_d'length-1), + scout => sov(reld_q3_congr_cl_offset to reld_q3_congr_cl_offset + reld_q3_congr_cl_d'length-1), + din => reld_q3_congr_cl_d, + dout => reld_q3_congr_cl_q); +reld_q3_way_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q3_way_offset to reld_q3_way_offset + reld_q3_way_d'length-1), + scout => sov(reld_q3_way_offset to reld_q3_way_offset + reld_q3_way_d'length-1), + din => reld_q3_way_d, + dout => reld_q3_way_q); +reld_q3_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q3_val_offset), + scout => sov(reld_q3_val_offset), + din => reld_q3_val_d, + dout => reld_q3_val_q); +reld_q3_lock_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q3_lock_offset), + scout => sov(reld_q3_lock_offset), + din => reld_q3_lock_d, + dout => reld_q3_lock_q); +reld_q4_congr_cl_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q4_congr_cl_offset to reld_q4_congr_cl_offset + reld_q4_congr_cl_d'length-1), + scout => sov(reld_q4_congr_cl_offset to reld_q4_congr_cl_offset + reld_q4_congr_cl_d'length-1), + din => reld_q4_congr_cl_d, + dout => reld_q4_congr_cl_q); +reld_q4_way_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q4_way_offset to reld_q4_way_offset + reld_q4_way_d'length-1), + scout => sov(reld_q4_way_offset to reld_q4_way_offset + reld_q4_way_d'length-1), + din => reld_q4_way_d, + dout => reld_q4_way_q); +reld_q4_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q4_val_offset), + scout => sov(reld_q4_val_offset), + din => reld_q4_val_d, + dout => reld_q4_val_q); +reld_q4_lock_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q4_lock_offset), + scout => sov(reld_q4_lock_offset), + din => reld_q4_lock_d, + dout => reld_q4_lock_q); +reld_q5_congr_cl_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q5_congr_cl_offset to reld_q5_congr_cl_offset + reld_q5_congr_cl_d'length-1), + scout => sov(reld_q5_congr_cl_offset to reld_q5_congr_cl_offset + reld_q5_congr_cl_d'length-1), + din => reld_q5_congr_cl_d, + dout => reld_q5_congr_cl_q); +reld_q5_way_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q5_way_offset to reld_q5_way_offset + reld_q5_way_d'length-1), + scout => sov(reld_q5_way_offset to reld_q5_way_offset + reld_q5_way_d'length-1), + din => reld_q5_way_d, + dout => reld_q5_way_q); +reld_q5_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q5_val_offset), + scout => sov(reld_q5_val_offset), + din => reld_q5_val_d, + dout => reld_q5_val_q); +reld_q5_lock_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q5_lock_offset), + scout => sov(reld_q5_lock_offset), + din => reld_q5_lock_d, + dout => reld_q5_lock_q); +reld_q6_congr_cl_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q6_congr_cl_offset to reld_q6_congr_cl_offset + reld_q6_congr_cl_d'length-1), + scout => sov(reld_q6_congr_cl_offset to reld_q6_congr_cl_offset + reld_q6_congr_cl_d'length-1), + din => reld_q6_congr_cl_d, + dout => reld_q6_congr_cl_q); +reld_q6_way_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q6_way_offset to reld_q6_way_offset + reld_q6_way_d'length-1), + scout => sov(reld_q6_way_offset to reld_q6_way_offset + reld_q6_way_d'length-1), + din => reld_q6_way_d, + dout => reld_q6_way_q); +reld_q6_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q6_val_offset), + scout => sov(reld_q6_val_offset), + din => reld_q6_val_d, + dout => reld_q6_val_q); +reld_q6_lock_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q6_lock_offset), + scout => sov(reld_q6_lock_offset), + din => reld_q6_lock_d, + dout => reld_q6_lock_q); +reld_q7_congr_cl_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q7_congr_cl_offset to reld_q7_congr_cl_offset + reld_q7_congr_cl_d'length-1), + scout => sov(reld_q7_congr_cl_offset to reld_q7_congr_cl_offset + reld_q7_congr_cl_d'length-1), + din => reld_q7_congr_cl_d, + dout => reld_q7_congr_cl_q); +reld_q7_way_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q7_way_offset to reld_q7_way_offset + reld_q7_way_d'length-1), + scout => sov(reld_q7_way_offset to reld_q7_way_offset + reld_q7_way_d'length-1), + din => reld_q7_way_d, + dout => reld_q7_way_q); +reld_q7_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q7_val_offset), + scout => sov(reld_q7_val_offset), + din => reld_q7_val_d, + dout => reld_q7_val_q); +reld_q7_lock_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q7_lock_offset), + scout => sov(reld_q7_lock_offset), + din => reld_q7_lock_d, + dout => reld_q7_lock_q); +rel_m_q_way_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_m_q_way_offset to rel_m_q_way_offset + rel_m_q_way_d'length-1), + scout => sov(rel_m_q_way_offset to rel_m_q_way_offset + rel_m_q_way_d'length-1), + din => rel_m_q_way_d, + dout => rel_m_q_way_q); +ex3_no_lru_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_no_lru_upd_offset), + scout => sov(ex3_no_lru_upd_offset), + din => ex3_no_lru_upd_d, + dout => ex3_no_lru_upd_q); +rel2_lock_en_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel2_lock_en_offset), + scout => sov(rel2_lock_en_offset), + din => rel2_lock_en_d, + dout => rel2_lock_en_q); +xucr0_clo_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xucr0_clo_offset), + scout => sov(xucr0_clo_offset), + din => xucr0_clo_d, + dout => xucr0_clo_q); +rel_up_way_addr_reg: tri_rlmreg_p +generic map (width => 3, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_up_way_addr_offset to rel_up_way_addr_offset + rel_up_way_addr_d'length-1), + scout => sov(rel_up_way_addr_offset to rel_up_way_addr_offset + rel_up_way_addr_d'length-1), + din => rel_up_way_addr_d, + dout => rel_up_way_addr_q); +rel24_way_dwen_stg_reg: tri_regk +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel24_way_dwen_stg_d, + dout => rel24_way_dwen_stg_q); +rel_dcarr_addr_en_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_dcarr_addr_en_offset), + scout => sov(rel_dcarr_addr_en_offset), + din => rel_dcarr_addr_en_d, + dout => rel_dcarr_addr_en_q); +rel_dcarr_val_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_dcarr_val_upd_offset), + scout => sov(rel_dcarr_val_upd_offset), + din => rel_dcarr_val_upd_d, + dout => rel_dcarr_val_upd_q); +congr_cl_ex3_ex4_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex3_ex4_cmp_offset), + scout => sov(congr_cl_ex3_ex4_cmp_offset), + din => congr_cl_ex3_ex4_cmp_d, + dout => congr_cl_ex3_ex4_cmp_q); +congr_cl_ex3_ex5_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex3_ex5_cmp_offset), + scout => sov(congr_cl_ex3_ex5_cmp_offset), + din => congr_cl_ex3_ex5_cmp_d, + dout => congr_cl_ex3_ex5_cmp_q); +congr_cl_ex3_ex6_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex3_ex6_cmp_offset), + scout => sov(congr_cl_ex3_ex6_cmp_offset), + din => congr_cl_ex3_ex6_cmp_d, + dout => congr_cl_ex3_ex6_cmp_q); +congr_cl_ex3_rel2_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex3_rel2_cmp_offset), + scout => sov(congr_cl_ex3_rel2_cmp_offset), + din => congr_cl_ex3_rel2_cmp_d, + dout => congr_cl_ex3_rel2_cmp_q); +congr_cl_ex3_rel_upd_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex3_rel_upd_cmp_offset), + scout => sov(congr_cl_ex3_rel_upd_cmp_offset), + din => congr_cl_ex3_rel_upd_cmp_d, + dout => congr_cl_ex3_rel_upd_cmp_q); +congr_cl_rel1_ex4_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_rel1_ex4_cmp_offset), + scout => sov(congr_cl_rel1_ex4_cmp_offset), + din => congr_cl_rel1_ex4_cmp_d, + dout => congr_cl_rel1_ex4_cmp_q); +congr_cl_rel1_ex5_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_rel1_ex5_cmp_offset), + scout => sov(congr_cl_rel1_ex5_cmp_offset), + din => congr_cl_rel1_ex5_cmp_d, + dout => congr_cl_rel1_ex5_cmp_q); +congr_cl_rel1_ex6_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_rel1_ex6_cmp_offset), + scout => sov(congr_cl_rel1_ex6_cmp_offset), + din => congr_cl_rel1_ex6_cmp_d, + dout => congr_cl_rel1_ex6_cmp_q); +congr_cl_rel1_rel2_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_rel1_rel2_cmp_offset), + scout => sov(congr_cl_rel1_rel2_cmp_offset), + din => congr_cl_rel1_rel2_cmp_d, + dout => congr_cl_rel1_rel2_cmp_q); +congr_cl_rel1_relu_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_rel1_relu_cmp_offset), + scout => sov(congr_cl_rel1_relu_cmp_offset), + din => congr_cl_rel1_relu_cmp_d, + dout => congr_cl_rel1_relu_cmp_q); +congr_cl_rel1_rel_upd_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_rel1_rel_upd_cmp_offset), + scout => sov(congr_cl_rel1_rel_upd_cmp_offset), + din => congr_cl_rel1_rel_upd_cmp_d, + dout => congr_cl_rel1_rel_upd_cmp_q); +congr_cl_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_act_offset), + scout => sov(congr_cl_act_offset), + din => congr_cl_act_d, + dout => congr_cl_act_q); +siv(0 TO scan_right) <= sov(1 to scan_right) & scan_in; +scan_out <= sov(0); +END XUQ_LSU_DIR_LRU32; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_dir_tag.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_dir_tag.vhdl new file mode 100644 index 0000000..c7af9d6 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_dir_tag.vhdl @@ -0,0 +1,1065 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ibm, ieee, work, tri, support; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use tri.tri_latches_pkg.all; +use support.power_logic_pkg.all; + +entity xuq_lsu_dir_tag is +generic(expand_type : integer := 2; + dc_size : natural := 14; + cl_size : natural := 6; + wayDataSize : natural := 35; + parBits : natural := 4; + real_data_add : integer := 42); +port( + + ex2_stg_act :in std_ulogic; + binv2_stg_act :in std_ulogic; + + rel_addr_early :in std_ulogic_vector(64-real_data_add to 63-cl_size); + rel_way_upd_a :in std_ulogic; + rel_way_upd_b :in std_ulogic; + rel_way_upd_c :in std_ulogic; + rel_way_upd_d :in std_ulogic; + rel_way_upd_e :in std_ulogic; + rel_way_upd_f :in std_ulogic; + rel_way_upd_g :in std_ulogic; + rel_way_upd_h :in std_ulogic; + + inv1_val :in std_ulogic; + + xu_lsu_spr_xucr0_dcdis :in std_ulogic; + + ex1_p_addr_01 :in std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + ex1_p_addr_23 :in std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + ex1_p_addr_45 :in std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + ex1_p_addr_67 :in std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + ex2_ddir_acc_instr :in std_ulogic; + + pc_xu_inj_dcachedir_parity :in std_ulogic; + + dir_arr_rd_addr_01 :out std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + dir_arr_rd_addr_23 :out std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + dir_arr_rd_addr_45 :out std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + dir_arr_rd_addr_67 :out std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + dir_arr_rd_data :in std_ulogic_vector(0 to 8*wayDataSize-1); + + dir_wr_way :out std_ulogic_vector(0 to 7); + dir_arr_wr_addr :out std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + dir_arr_wr_data :out std_ulogic_vector(64-real_data_add to 64-real_data_add+wayDataSize-1); + + ex2_wayA_tag :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex2_wayB_tag :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex2_wayC_tag :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex2_wayD_tag :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex2_wayE_tag :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex2_wayF_tag :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex2_wayG_tag :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex2_wayH_tag :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + + ex3_way_tag_par_a :out std_ulogic_vector(0 to parBits-1); + ex3_way_tag_par_b :out std_ulogic_vector(0 to parBits-1); + ex3_way_tag_par_c :out std_ulogic_vector(0 to parBits-1); + ex3_way_tag_par_d :out std_ulogic_vector(0 to parBits-1); + ex3_way_tag_par_e :out std_ulogic_vector(0 to parBits-1); + ex3_way_tag_par_f :out std_ulogic_vector(0 to parBits-1); + ex3_way_tag_par_g :out std_ulogic_vector(0 to parBits-1); + ex3_way_tag_par_h :out std_ulogic_vector(0 to parBits-1); + + ex3_tag_way_perr :out std_ulogic_vector(0 to 7); + + vdd :inout power_logic; + gnd :inout power_logic; + nclk :in clk_logic; + sg_0 :in std_ulogic; + func_sl_thold_0_b :in std_ulogic; + func_sl_force :in std_ulogic; + func_slp_sl_thold_0_b :in std_ulogic; + func_slp_sl_force :in std_ulogic; + d_mode_dc :in std_ulogic; + delay_lclkr_dc :in std_ulogic; + mpw1_dc_b :in std_ulogic; + mpw2_dc_b :in std_ulogic; + scan_in :in std_ulogic; + scan_out :out std_ulogic + ); +-- synopsys translate_off +-- synopsys translate_on +end xuq_lsu_dir_tag; +architecture xuq_lsu_dir_tag of xuq_lsu_dir_tag is + +constant uprTagBit :natural := 64-real_data_add; +constant lwrTagBit :natural := 63-(dc_size-3); +constant tagSize :natural := lwrTagBit-uprTagBit+1; +constant parExtCalc :natural := 8 - (tagSize mod 8); +constant uprCClassBit :natural := 64-(dc_size-3); +constant lwrCClassBit :natural := 63-cl_size; + +signal arr_wr_addr :std_ulogic_vector(uprCClassBit to lwrCClassBit); +signal arr_wr_data :std_ulogic_vector(uprTagBit to lwrTagBit); +signal wayA_wen :std_ulogic; +signal wayB_wen :std_ulogic; +signal wayC_wen :std_ulogic; +signal wayD_wen :std_ulogic; +signal wayE_wen :std_ulogic; +signal wayF_wen :std_ulogic; +signal wayG_wen :std_ulogic; +signal wayH_wen :std_ulogic; +signal arr_wayA_tag :std_ulogic_vector(uprTagBit to lwrTagBit); +signal arr_wayB_tag :std_ulogic_vector(uprTagBit to lwrTagBit); +signal arr_wayC_tag :std_ulogic_vector(uprTagBit to lwrTagBit); +signal arr_wayD_tag :std_ulogic_vector(uprTagBit to lwrTagBit); +signal arr_wayE_tag :std_ulogic_vector(uprTagBit to lwrTagBit); +signal arr_wayF_tag :std_ulogic_vector(uprTagBit to lwrTagBit); +signal arr_wayG_tag :std_ulogic_vector(uprTagBit to lwrTagBit); +signal arr_wayH_tag :std_ulogic_vector(uprTagBit to lwrTagBit); +signal inval_val_d :std_ulogic; +signal inval_val_q :std_ulogic; +signal arr_rd_addr_01 :std_ulogic_vector(uprCClassBit to lwrCClassBit); +signal arr_rd_addr_23 :std_ulogic_vector(uprCClassBit to lwrCClassBit); +signal arr_rd_addr_45 :std_ulogic_vector(uprCClassBit to lwrCClassBit); +signal arr_rd_addr_67 :std_ulogic_vector(uprCClassBit to lwrCClassBit); +signal ex3_en_par_chk_d :std_ulogic_vector(0 to 7); +signal ex3_en_par_chk_q :std_ulogic_vector(0 to 7); +signal spr_xucr0_dcdis_d :std_ulogic; +signal spr_xucr0_dcdis_q :std_ulogic; +signal inj_dcachedir_parity_d :std_ulogic; +signal inj_dcachedir_parity_q :std_ulogic; +signal relu_addr_d :std_ulogic_vector(uprCClassBit to lwrCClassBit); +signal relu_addr_q :std_ulogic_vector(uprCClassBit to lwrCClassBit); +signal ex2_par_gen_a_1b :std_ulogic_vector(0 to parBits-1); +signal ex2_par_gen_a_2b :std_ulogic_vector(0 to parBits-1); +signal ex2_par_gen_b_1b :std_ulogic_vector(0 to parBits-1); +signal ex2_par_gen_b_2b :std_ulogic_vector(0 to parBits-1); +signal ex2_par_gen_c_1b :std_ulogic_vector(0 to parBits-1); +signal ex2_par_gen_c_2b :std_ulogic_vector(0 to parBits-1); +signal ex2_par_gen_d_1b :std_ulogic_vector(0 to parBits-1); +signal ex2_par_gen_d_2b :std_ulogic_vector(0 to parBits-1); +signal ex2_par_gen_e_1b :std_ulogic_vector(0 to parBits-1); +signal ex2_par_gen_e_2b :std_ulogic_vector(0 to parBits-1); +signal ex2_par_gen_f_1b :std_ulogic_vector(0 to parBits-1); +signal ex2_par_gen_f_2b :std_ulogic_vector(0 to parBits-1); +signal ex2_par_gen_g_1b :std_ulogic_vector(0 to parBits-1); +signal ex2_par_gen_g_2b :std_ulogic_vector(0 to parBits-1); +signal ex2_par_gen_h_1b :std_ulogic_vector(0 to parBits-1); +signal ex2_par_gen_h_2b :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_a_1b_d :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_a_2b_d :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_a_1b_q :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_a_2b_q :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_b_1b_d :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_b_2b_d :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_b_1b_q :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_b_2b_q :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_c_1b_d :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_c_2b_d :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_c_1b_q :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_c_2b_q :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_d_1b_d :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_d_2b_d :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_d_1b_q :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_d_2b_q :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_e_1b_d :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_e_2b_d :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_e_1b_q :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_e_2b_q :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_f_1b_d :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_f_2b_d :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_f_1b_q :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_f_2b_q :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_g_1b_d :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_g_2b_d :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_g_1b_q :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_g_2b_q :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_h_1b_d :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_h_2b_d :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_h_1b_q :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_h_2b_q :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_a :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_b :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_c :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_d :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_e :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_f :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_g :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_h :std_ulogic_vector(0 to parBits-1); +signal ex3_perr_det_a :std_ulogic; +signal ex3_perr_det_b :std_ulogic; +signal ex3_perr_det_c :std_ulogic; +signal ex3_perr_det_d :std_ulogic; +signal ex3_perr_det_e :std_ulogic; +signal ex3_perr_det_f :std_ulogic; +signal ex3_perr_det_g :std_ulogic; +signal ex3_perr_det_h :std_ulogic; +signal ex2_binv2_stg_act :std_ulogic; +signal rel_wrt_data_d :std_ulogic_vector(uprTagBit to uprTagBit+wayDataSize-1); +signal rel_wrt_data_q :std_ulogic_vector(uprTagBit to uprTagBit+wayDataSize-1); +signal ex3_way_tag_par_a_d :std_ulogic_vector(0 to parBits-1); +signal ex3_way_tag_par_a_q :std_ulogic_vector(0 to parBits-1); +signal ex3_way_tag_par_b_d :std_ulogic_vector(0 to parBits-1); +signal ex3_way_tag_par_b_q :std_ulogic_vector(0 to parBits-1); +signal ex3_way_tag_par_c_d :std_ulogic_vector(0 to parBits-1); +signal ex3_way_tag_par_c_q :std_ulogic_vector(0 to parBits-1); +signal ex3_way_tag_par_d_d :std_ulogic_vector(0 to parBits-1); +signal ex3_way_tag_par_d_q :std_ulogic_vector(0 to parBits-1); +signal ex3_way_tag_par_e_d :std_ulogic_vector(0 to parBits-1); +signal ex3_way_tag_par_e_q :std_ulogic_vector(0 to parBits-1); +signal ex3_way_tag_par_f_d :std_ulogic_vector(0 to parBits-1); +signal ex3_way_tag_par_f_q :std_ulogic_vector(0 to parBits-1); +signal ex3_way_tag_par_g_d :std_ulogic_vector(0 to parBits-1); +signal ex3_way_tag_par_g_q :std_ulogic_vector(0 to parBits-1); +signal ex3_way_tag_par_h_d :std_ulogic_vector(0 to parBits-1); +signal ex3_way_tag_par_h_q :std_ulogic_vector(0 to parBits-1); +signal my_spare0_lclk :clk_logic; +signal my_spare0_d1clk :std_ulogic; +signal my_spare0_d2clk :std_ulogic; +signal my_spare0_latches_d :std_ulogic_vector(0 to 15); +signal my_spare0_latches_q :std_ulogic_vector(0 to 15); +signal my_spare1_lclk :clk_logic; +signal my_spare1_d1clk :std_ulogic; +signal my_spare1_d2clk :std_ulogic; +signal my_spare1_latches_d :std_ulogic_vector(0 to 15); +signal my_spare1_latches_q :std_ulogic_vector(0 to 15); + +constant inval_val_offset :natural := 0; +constant ex3_en_par_chk_offset :natural := inval_val_offset + 1; +constant spr_xucr0_dcdis_offset :natural := ex3_en_par_chk_offset + 8; +constant inj_dcachedir_parity_offset :natural := spr_xucr0_dcdis_offset + 1; +constant relu_addr_offset :natural := inj_dcachedir_parity_offset + 1; +constant rel_wrt_data_offset :natural := relu_addr_offset + lwrCClassBit-uprCClassBit+1; +constant ex3_par_gen_a_1b_offset :natural := rel_wrt_data_offset + wayDataSize; +constant ex3_par_gen_a_2b_offset :natural := ex3_par_gen_a_1b_offset + parBits; +constant ex3_par_gen_b_1b_offset :natural := ex3_par_gen_a_2b_offset + parBits; +constant ex3_par_gen_b_2b_offset :natural := ex3_par_gen_b_1b_offset + parBits; +constant ex3_par_gen_c_1b_offset :natural := ex3_par_gen_b_2b_offset + parBits; +constant ex3_par_gen_c_2b_offset :natural := ex3_par_gen_c_1b_offset + parBits; +constant ex3_par_gen_d_1b_offset :natural := ex3_par_gen_c_2b_offset + parBits; +constant ex3_par_gen_d_2b_offset :natural := ex3_par_gen_d_1b_offset + parBits; +constant ex3_par_gen_e_1b_offset :natural := ex3_par_gen_d_2b_offset + parBits; +constant ex3_par_gen_e_2b_offset :natural := ex3_par_gen_e_1b_offset + parBits; +constant ex3_par_gen_f_1b_offset :natural := ex3_par_gen_e_2b_offset + parBits; +constant ex3_par_gen_f_2b_offset :natural := ex3_par_gen_f_1b_offset + parBits; +constant ex3_par_gen_g_1b_offset :natural := ex3_par_gen_f_2b_offset + parBits; +constant ex3_par_gen_g_2b_offset :natural := ex3_par_gen_g_1b_offset + parBits; +constant ex3_par_gen_h_1b_offset :natural := ex3_par_gen_g_2b_offset + parBits; +constant ex3_par_gen_h_2b_offset :natural := ex3_par_gen_h_1b_offset + parBits; +constant ex3_way_tag_par_a_offset :natural := ex3_par_gen_h_2b_offset + parBits; +constant ex3_way_tag_par_b_offset :natural := ex3_way_tag_par_a_offset + parBits; +constant ex3_way_tag_par_c_offset :natural := ex3_way_tag_par_b_offset + parBits; +constant ex3_way_tag_par_d_offset :natural := ex3_way_tag_par_c_offset + parBits; +constant ex3_way_tag_par_e_offset :natural := ex3_way_tag_par_d_offset + parBits; +constant ex3_way_tag_par_f_offset :natural := ex3_way_tag_par_e_offset + parBits; +constant ex3_way_tag_par_g_offset :natural := ex3_way_tag_par_f_offset + parBits; +constant ex3_way_tag_par_h_offset :natural := ex3_way_tag_par_g_offset + parBits; +constant my_spare0_latches_offset :natural := ex3_way_tag_par_h_offset + parBits; +constant my_spare1_latches_offset :natural := my_spare0_latches_offset + 16; +constant scan_right :natural := my_spare1_latches_offset + 16 - 1; + +signal tiup :std_ulogic; +signal siv :std_ulogic_vector(0 to scan_right); +signal sov :std_ulogic_vector(0 to scan_right); + +begin + +tiup <= '1'; +ex2_binv2_stg_act <= ex2_stg_act or binv2_stg_act; + +relu_addr_d <= rel_addr_early(uprCClassBit to lwrCClassBit); +wayA_wen <= rel_way_upd_a; +wayB_wen <= rel_way_upd_b; +wayC_wen <= rel_way_upd_c; +wayD_wen <= rel_way_upd_d; +wayE_wen <= rel_way_upd_e; +wayF_wen <= rel_way_upd_f; +wayG_wen <= rel_way_upd_g; +wayH_wen <= rel_way_upd_h; + +inval_val_d <= inv1_val; + +spr_xucr0_dcdis_d <= xu_lsu_spr_xucr0_dcdis; +inj_dcachedir_parity_d <= pc_xu_inj_dcachedir_parity; + + +arr_wr_addr <= relu_addr_q(uprCClassBit to lwrCClassBit); +arr_wr_data <= rel_addr_early(uprTagBit to lwrTagBit); + +arr_rd_addr_01 <= ex1_p_addr_01; +arr_rd_addr_23 <= ex1_p_addr_23; +arr_rd_addr_45 <= ex1_p_addr_45; +arr_rd_addr_67 <= ex1_p_addr_67; + + +l1dcta : entity work.xuq_lsu_dir_tag_arr(xuq_lsu_dir_tag_arr) +GENERIC MAP(expand_type => expand_type, + dc_size => dc_size, + cl_size => cl_size, + wayDataSize => wayDataSize, + parityBits => parBits, + real_data_add => real_data_add) +port map( + + waddr => arr_wr_addr, + wdata => arr_wr_data, + way_wen_a => wayA_wen, + way_wen_b => wayB_wen, + way_wen_c => wayC_wen, + way_wen_d => wayD_wen, + way_wen_e => wayE_wen, + way_wen_f => wayF_wen, + way_wen_g => wayG_wen, + way_wen_h => wayH_wen, + + raddr_01 => arr_rd_addr_01, + raddr_23 => arr_rd_addr_23, + raddr_45 => arr_rd_addr_45, + raddr_67 => arr_rd_addr_67, + inj_parity_err => inj_dcachedir_parity_q, + + dir_arr_rd_addr_01 => dir_arr_rd_addr_01, + dir_arr_rd_addr_23 => dir_arr_rd_addr_23, + dir_arr_rd_addr_45 => dir_arr_rd_addr_45, + dir_arr_rd_addr_67 => dir_arr_rd_addr_67, + dir_arr_rd_data => dir_arr_rd_data, + + dir_wr_way => dir_wr_way, + dir_arr_wr_addr => dir_arr_wr_addr, + dir_arr_wr_data => rel_wrt_data_d, + + way_tag_a => arr_wayA_tag, + way_tag_b => arr_wayB_tag, + way_tag_c => arr_wayC_tag, + way_tag_d => arr_wayD_tag, + way_tag_e => arr_wayE_tag, + way_tag_f => arr_wayF_tag, + way_tag_g => arr_wayG_tag, + way_tag_h => arr_wayH_tag, + + way_arr_par_a => ex3_way_tag_par_a_d, + way_arr_par_b => ex3_way_tag_par_b_d, + way_arr_par_c => ex3_way_tag_par_c_d, + way_arr_par_d => ex3_way_tag_par_d_d, + way_arr_par_e => ex3_way_tag_par_e_d, + way_arr_par_f => ex3_way_tag_par_f_d, + way_arr_par_g => ex3_way_tag_par_g_d, + way_arr_par_h => ex3_way_tag_par_h_d, + + par_gen_a_1b => ex2_par_gen_a_1b, + par_gen_a_2b => ex2_par_gen_a_2b, + par_gen_b_1b => ex2_par_gen_b_1b, + par_gen_b_2b => ex2_par_gen_b_2b, + par_gen_c_1b => ex2_par_gen_c_1b, + par_gen_c_2b => ex2_par_gen_c_2b, + par_gen_d_1b => ex2_par_gen_d_1b, + par_gen_d_2b => ex2_par_gen_d_2b, + par_gen_e_1b => ex2_par_gen_e_1b, + par_gen_e_2b => ex2_par_gen_e_2b, + par_gen_f_1b => ex2_par_gen_f_1b, + par_gen_f_2b => ex2_par_gen_f_2b, + par_gen_g_1b => ex2_par_gen_g_1b, + par_gen_g_2b => ex2_par_gen_g_2b, + par_gen_h_1b => ex2_par_gen_h_1b, + par_gen_h_2b => ex2_par_gen_h_2b +); + + +ex3_en_par_chk_d(0) <= (ex2_ddir_acc_instr or inval_val_q) and not spr_xucr0_dcdis_q; +ex3_en_par_chk_d(1) <= (ex2_ddir_acc_instr or inval_val_q) and not spr_xucr0_dcdis_q; +ex3_en_par_chk_d(2) <= (ex2_ddir_acc_instr or inval_val_q) and not spr_xucr0_dcdis_q; +ex3_en_par_chk_d(3) <= (ex2_ddir_acc_instr or inval_val_q) and not spr_xucr0_dcdis_q; +ex3_en_par_chk_d(4) <= (ex2_ddir_acc_instr or inval_val_q) and not spr_xucr0_dcdis_q; +ex3_en_par_chk_d(5) <= (ex2_ddir_acc_instr or inval_val_q) and not spr_xucr0_dcdis_q; +ex3_en_par_chk_d(6) <= (ex2_ddir_acc_instr or inval_val_q) and not spr_xucr0_dcdis_q; +ex3_en_par_chk_d(7) <= (ex2_ddir_acc_instr or inval_val_q) and not spr_xucr0_dcdis_q; + +ex3_par_gen_a_1b_d <= ex2_par_gen_a_1b; +ex3_par_gen_a_2b_d <= ex2_par_gen_a_2b; +ex3_par_gen_b_1b_d <= ex2_par_gen_b_1b; +ex3_par_gen_b_2b_d <= ex2_par_gen_b_2b; +ex3_par_gen_c_1b_d <= ex2_par_gen_c_1b; +ex3_par_gen_c_2b_d <= ex2_par_gen_c_2b; +ex3_par_gen_d_1b_d <= ex2_par_gen_d_1b; +ex3_par_gen_d_2b_d <= ex2_par_gen_d_2b; +ex3_par_gen_e_1b_d <= ex2_par_gen_e_1b; +ex3_par_gen_e_2b_d <= ex2_par_gen_e_2b; +ex3_par_gen_f_1b_d <= ex2_par_gen_f_1b; +ex3_par_gen_f_2b_d <= ex2_par_gen_f_2b; +ex3_par_gen_g_1b_d <= ex2_par_gen_g_1b; +ex3_par_gen_g_2b_d <= ex2_par_gen_g_2b; +ex3_par_gen_h_1b_d <= ex2_par_gen_h_1b; +ex3_par_gen_h_2b_d <= ex2_par_gen_h_2b; + +ex3_par_gen_a <= ex3_par_gen_a_1b_q xor ex3_par_gen_a_2b_q; +ex3_par_gen_b <= ex3_par_gen_b_1b_q xor ex3_par_gen_b_2b_q; +ex3_par_gen_c <= ex3_par_gen_c_1b_q xor ex3_par_gen_c_2b_q; +ex3_par_gen_d <= ex3_par_gen_d_1b_q xor ex3_par_gen_d_2b_q; +ex3_par_gen_e <= ex3_par_gen_e_1b_q xor ex3_par_gen_e_2b_q; +ex3_par_gen_f <= ex3_par_gen_f_1b_q xor ex3_par_gen_f_2b_q; +ex3_par_gen_g <= ex3_par_gen_g_1b_q xor ex3_par_gen_g_2b_q; +ex3_par_gen_h <= ex3_par_gen_h_1b_q xor ex3_par_gen_h_2b_q; + +ex3_perr_det_a <= or_reduce(ex3_way_tag_par_a_q xor ex3_par_gen_a) and ex3_en_par_chk_q(0); +ex3_perr_det_b <= or_reduce(ex3_way_tag_par_b_q xor ex3_par_gen_b) and ex3_en_par_chk_q(1); +ex3_perr_det_c <= or_reduce(ex3_way_tag_par_c_q xor ex3_par_gen_c) and ex3_en_par_chk_q(2); +ex3_perr_det_d <= or_reduce(ex3_way_tag_par_d_q xor ex3_par_gen_d) and ex3_en_par_chk_q(3); +ex3_perr_det_e <= or_reduce(ex3_way_tag_par_e_q xor ex3_par_gen_e) and ex3_en_par_chk_q(4); +ex3_perr_det_f <= or_reduce(ex3_way_tag_par_f_q xor ex3_par_gen_f) and ex3_en_par_chk_q(5); +ex3_perr_det_g <= or_reduce(ex3_way_tag_par_g_q xor ex3_par_gen_g) and ex3_en_par_chk_q(6); +ex3_perr_det_h <= or_reduce(ex3_way_tag_par_h_q xor ex3_par_gen_h) and ex3_en_par_chk_q(7); + +my_spare0_latches_d <= not my_spare0_latches_q; +my_spare1_latches_d <= not my_spare1_latches_q; + +ex2_wayA_tag <= arr_wayA_tag; +ex2_wayB_tag <= arr_wayB_tag; +ex2_wayC_tag <= arr_wayC_tag; +ex2_wayD_tag <= arr_wayD_tag; +ex2_wayE_tag <= arr_wayE_tag; +ex2_wayF_tag <= arr_wayF_tag; +ex2_wayG_tag <= arr_wayG_tag; +ex2_wayH_tag <= arr_wayH_tag; + +dir_arr_wr_data <= rel_wrt_data_q; + +ex3_way_tag_par_a <= ex3_way_tag_par_a_q; +ex3_way_tag_par_b <= ex3_way_tag_par_b_q; +ex3_way_tag_par_c <= ex3_way_tag_par_c_q; +ex3_way_tag_par_d <= ex3_way_tag_par_d_q; +ex3_way_tag_par_e <= ex3_way_tag_par_e_q; +ex3_way_tag_par_f <= ex3_way_tag_par_f_q; +ex3_way_tag_par_g <= ex3_way_tag_par_g_q; +ex3_way_tag_par_h <= ex3_way_tag_par_h_q; + +ex3_tag_way_perr <= ex3_perr_det_a & ex3_perr_det_b & ex3_perr_det_c & ex3_perr_det_d & + ex3_perr_det_e & ex3_perr_det_f & ex3_perr_det_g & ex3_perr_det_h; + + +inval_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(inval_val_offset), + scout => sov(inval_val_offset), + din => inval_val_d, + dout => inval_val_q); + +ex3_en_par_chk_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_en_par_chk_offset to ex3_en_par_chk_offset + ex3_en_par_chk_d'length-1), + scout => sov(ex3_en_par_chk_offset to ex3_en_par_chk_offset + ex3_en_par_chk_d'length-1), + din => ex3_en_par_chk_d, + dout => ex3_en_par_chk_q); + +spr_xucr0_dcdis_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(spr_xucr0_dcdis_offset), + scout => sov(spr_xucr0_dcdis_offset), + din => spr_xucr0_dcdis_d, + dout => spr_xucr0_dcdis_q); + +inj_dcachedir_parity_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(inj_dcachedir_parity_offset), + scout => sov(inj_dcachedir_parity_offset), + din => inj_dcachedir_parity_d, + dout => inj_dcachedir_parity_q); + +relu_addr_reg: tri_rlmreg_p +generic map (width => lwrCClassBit-uprCClassBit+1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(relu_addr_offset to relu_addr_offset + relu_addr_d'length-1), + scout => sov(relu_addr_offset to relu_addr_offset + relu_addr_d'length-1), + din => relu_addr_d, + dout => relu_addr_q); + +rel_wrt_data_reg: tri_rlmreg_p +generic map (width => wayDataSize, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_wrt_data_offset to rel_wrt_data_offset + rel_wrt_data_d'length-1), + scout => sov(rel_wrt_data_offset to rel_wrt_data_offset + rel_wrt_data_d'length-1), + din => rel_wrt_data_d, + dout => rel_wrt_data_q); + +ex3_par_gen_a_1b_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_par_gen_a_1b_offset to ex3_par_gen_a_1b_offset + ex3_par_gen_a_1b_d'length-1), + scout => sov(ex3_par_gen_a_1b_offset to ex3_par_gen_a_1b_offset + ex3_par_gen_a_1b_d'length-1), + din => ex3_par_gen_a_1b_d, + dout => ex3_par_gen_a_1b_q); + +ex3_par_gen_a_2b_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_par_gen_a_2b_offset to ex3_par_gen_a_2b_offset + ex3_par_gen_a_2b_d'length-1), + scout => sov(ex3_par_gen_a_2b_offset to ex3_par_gen_a_2b_offset + ex3_par_gen_a_2b_d'length-1), + din => ex3_par_gen_a_2b_d, + dout => ex3_par_gen_a_2b_q); + +ex3_par_gen_b_1b_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_par_gen_b_1b_offset to ex3_par_gen_b_1b_offset + ex3_par_gen_b_1b_d'length-1), + scout => sov(ex3_par_gen_b_1b_offset to ex3_par_gen_b_1b_offset + ex3_par_gen_b_1b_d'length-1), + din => ex3_par_gen_b_1b_d, + dout => ex3_par_gen_b_1b_q); + +ex3_par_gen_b_2b_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_par_gen_b_2b_offset to ex3_par_gen_b_2b_offset + ex3_par_gen_b_2b_d'length-1), + scout => sov(ex3_par_gen_b_2b_offset to ex3_par_gen_b_2b_offset + ex3_par_gen_b_2b_d'length-1), + din => ex3_par_gen_b_2b_d, + dout => ex3_par_gen_b_2b_q); + +ex3_par_gen_c_1b_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_par_gen_c_1b_offset to ex3_par_gen_c_1b_offset + ex3_par_gen_c_1b_d'length-1), + scout => sov(ex3_par_gen_c_1b_offset to ex3_par_gen_c_1b_offset + ex3_par_gen_c_1b_d'length-1), + din => ex3_par_gen_c_1b_d, + dout => ex3_par_gen_c_1b_q); + +ex3_par_gen_c_2b_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_par_gen_c_2b_offset to ex3_par_gen_c_2b_offset + ex3_par_gen_c_2b_d'length-1), + scout => sov(ex3_par_gen_c_2b_offset to ex3_par_gen_c_2b_offset + ex3_par_gen_c_2b_d'length-1), + din => ex3_par_gen_c_2b_d, + dout => ex3_par_gen_c_2b_q); + +ex3_par_gen_d_1b_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_par_gen_d_1b_offset to ex3_par_gen_d_1b_offset + ex3_par_gen_d_1b_d'length-1), + scout => sov(ex3_par_gen_d_1b_offset to ex3_par_gen_d_1b_offset + ex3_par_gen_d_1b_d'length-1), + din => ex3_par_gen_d_1b_d, + dout => ex3_par_gen_d_1b_q); + +ex3_par_gen_d_2b_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_par_gen_d_2b_offset to ex3_par_gen_d_2b_offset + ex3_par_gen_d_2b_d'length-1), + scout => sov(ex3_par_gen_d_2b_offset to ex3_par_gen_d_2b_offset + ex3_par_gen_d_2b_d'length-1), + din => ex3_par_gen_d_2b_d, + dout => ex3_par_gen_d_2b_q); + +ex3_par_gen_e_1b_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_par_gen_e_1b_offset to ex3_par_gen_e_1b_offset + ex3_par_gen_e_1b_d'length-1), + scout => sov(ex3_par_gen_e_1b_offset to ex3_par_gen_e_1b_offset + ex3_par_gen_e_1b_d'length-1), + din => ex3_par_gen_e_1b_d, + dout => ex3_par_gen_e_1b_q); + +ex3_par_gen_e_2b_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_par_gen_e_2b_offset to ex3_par_gen_e_2b_offset + ex3_par_gen_e_2b_d'length-1), + scout => sov(ex3_par_gen_e_2b_offset to ex3_par_gen_e_2b_offset + ex3_par_gen_e_2b_d'length-1), + din => ex3_par_gen_e_2b_d, + dout => ex3_par_gen_e_2b_q); + +ex3_par_gen_f_1b_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_par_gen_f_1b_offset to ex3_par_gen_f_1b_offset + ex3_par_gen_f_1b_d'length-1), + scout => sov(ex3_par_gen_f_1b_offset to ex3_par_gen_f_1b_offset + ex3_par_gen_f_1b_d'length-1), + din => ex3_par_gen_f_1b_d, + dout => ex3_par_gen_f_1b_q); + +ex3_par_gen_f_2b_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_par_gen_f_2b_offset to ex3_par_gen_f_2b_offset + ex3_par_gen_f_2b_d'length-1), + scout => sov(ex3_par_gen_f_2b_offset to ex3_par_gen_f_2b_offset + ex3_par_gen_f_2b_d'length-1), + din => ex3_par_gen_f_2b_d, + dout => ex3_par_gen_f_2b_q); + +ex3_par_gen_g_1b_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_par_gen_g_1b_offset to ex3_par_gen_g_1b_offset + ex3_par_gen_g_1b_d'length-1), + scout => sov(ex3_par_gen_g_1b_offset to ex3_par_gen_g_1b_offset + ex3_par_gen_g_1b_d'length-1), + din => ex3_par_gen_g_1b_d, + dout => ex3_par_gen_g_1b_q); + +ex3_par_gen_g_2b_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_par_gen_g_2b_offset to ex3_par_gen_g_2b_offset + ex3_par_gen_g_2b_d'length-1), + scout => sov(ex3_par_gen_g_2b_offset to ex3_par_gen_g_2b_offset + ex3_par_gen_g_2b_d'length-1), + din => ex3_par_gen_g_2b_d, + dout => ex3_par_gen_g_2b_q); + +ex3_par_gen_h_1b_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_par_gen_h_1b_offset to ex3_par_gen_h_1b_offset + ex3_par_gen_h_1b_d'length-1), + scout => sov(ex3_par_gen_h_1b_offset to ex3_par_gen_h_1b_offset + ex3_par_gen_h_1b_d'length-1), + din => ex3_par_gen_h_1b_d, + dout => ex3_par_gen_h_1b_q); + +ex3_par_gen_h_2b_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_par_gen_h_2b_offset to ex3_par_gen_h_2b_offset + ex3_par_gen_h_2b_d'length-1), + scout => sov(ex3_par_gen_h_2b_offset to ex3_par_gen_h_2b_offset + ex3_par_gen_h_2b_d'length-1), + din => ex3_par_gen_h_2b_d, + dout => ex3_par_gen_h_2b_q); + +ex3_way_tag_par_a_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_way_tag_par_a_offset to ex3_way_tag_par_a_offset + ex3_way_tag_par_a_d'length-1), + scout => sov(ex3_way_tag_par_a_offset to ex3_way_tag_par_a_offset + ex3_way_tag_par_a_d'length-1), + din => ex3_way_tag_par_a_d, + dout => ex3_way_tag_par_a_q); + +ex3_way_tag_par_b_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_way_tag_par_b_offset to ex3_way_tag_par_b_offset + ex3_way_tag_par_b_d'length-1), + scout => sov(ex3_way_tag_par_b_offset to ex3_way_tag_par_b_offset + ex3_way_tag_par_b_d'length-1), + din => ex3_way_tag_par_b_d, + dout => ex3_way_tag_par_b_q); + +ex3_way_tag_par_c_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_way_tag_par_c_offset to ex3_way_tag_par_c_offset + ex3_way_tag_par_c_d'length-1), + scout => sov(ex3_way_tag_par_c_offset to ex3_way_tag_par_c_offset + ex3_way_tag_par_c_d'length-1), + din => ex3_way_tag_par_c_d, + dout => ex3_way_tag_par_c_q); + +ex3_way_tag_par_d_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_way_tag_par_d_offset to ex3_way_tag_par_d_offset + ex3_way_tag_par_d_d'length-1), + scout => sov(ex3_way_tag_par_d_offset to ex3_way_tag_par_d_offset + ex3_way_tag_par_d_d'length-1), + din => ex3_way_tag_par_d_d, + dout => ex3_way_tag_par_d_q); + +ex3_way_tag_par_e_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_way_tag_par_e_offset to ex3_way_tag_par_e_offset + ex3_way_tag_par_e_d'length-1), + scout => sov(ex3_way_tag_par_e_offset to ex3_way_tag_par_e_offset + ex3_way_tag_par_e_d'length-1), + din => ex3_way_tag_par_e_d, + dout => ex3_way_tag_par_e_q); + +ex3_way_tag_par_f_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_way_tag_par_f_offset to ex3_way_tag_par_f_offset + ex3_way_tag_par_f_d'length-1), + scout => sov(ex3_way_tag_par_f_offset to ex3_way_tag_par_f_offset + ex3_way_tag_par_f_d'length-1), + din => ex3_way_tag_par_f_d, + dout => ex3_way_tag_par_f_q); + +ex3_way_tag_par_g_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_way_tag_par_g_offset to ex3_way_tag_par_g_offset + ex3_way_tag_par_g_d'length-1), + scout => sov(ex3_way_tag_par_g_offset to ex3_way_tag_par_g_offset + ex3_way_tag_par_g_d'length-1), + din => ex3_way_tag_par_g_d, + dout => ex3_way_tag_par_g_q); + +ex3_way_tag_par_h_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_way_tag_par_h_offset to ex3_way_tag_par_h_offset + ex3_way_tag_par_h_d'length-1), + scout => sov(ex3_way_tag_par_h_offset to ex3_way_tag_par_h_offset + ex3_way_tag_par_h_d'length-1), + din => ex3_way_tag_par_h_d, + dout => ex3_way_tag_par_h_q); + +my_spare0_lcb : entity tri.tri_lcbnd(tri_lcbnd) +generic map (expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + d1clk => my_spare0_d1clk, + d2clk => my_spare0_d2clk, + lclk => my_spare0_lclk); +my_spare0_latches_reg: entity tri.tri_inv_nlats(tri_inv_nlats) +generic map (width => 16, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + lclk => my_spare0_lclk, + d1clk => my_spare0_d1clk, + d2clk => my_spare0_d2clk, + scanin => siv(my_spare0_latches_offset to my_spare0_latches_offset + my_spare0_latches_d'length-1), + scanout => sov(my_spare0_latches_offset to my_spare0_latches_offset + my_spare0_latches_d'length-1), + d => my_spare0_latches_d, + qb => my_spare0_latches_q); + +my_spare1_lcb : entity tri.tri_lcbnd(tri_lcbnd) +generic map (expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + d1clk => my_spare1_d1clk, + d2clk => my_spare1_d2clk, + lclk => my_spare1_lclk); +my_spare1_latches_reg: entity tri.tri_inv_nlats(tri_inv_nlats) +generic map (width => 16, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + lclk => my_spare1_lclk, + d1clk => my_spare1_d1clk, + d2clk => my_spare1_d2clk, + scanin => siv(my_spare1_latches_offset to my_spare1_latches_offset + my_spare1_latches_d'length-1), + scanout => sov(my_spare1_latches_offset to my_spare1_latches_offset + my_spare1_latches_d'length-1), + d => my_spare1_latches_d, + qb => my_spare1_latches_q); + +siv(0 to scan_right) <= sov(1 to scan_right) & scan_in; +scan_out <= sov(0); +end xuq_lsu_dir_tag; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_dir_tag_arr.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_dir_tag_arr.vhdl new file mode 100644 index 0000000..e03bff4 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_dir_tag_arr.vhdl @@ -0,0 +1,459 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ibm, ieee, work, tri, support; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use tri.tri_latches_pkg.all; +use support.power_logic_pkg.all; + + +entity xuq_lsu_dir_tag_arr is +generic(expand_type : integer := 2; + dc_size : natural := 14; + cl_size : natural := 6; + wayDataSize : natural := 35; + parityBits : natural := 4; + real_data_add : integer := 42); + PORT ( + + waddr :in std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + wdata :in std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + way_wen_a :in std_ulogic; + way_wen_b :in std_ulogic; + way_wen_c :in std_ulogic; + way_wen_d :in std_ulogic; + way_wen_e :in std_ulogic; + way_wen_f :in std_ulogic; + way_wen_g :in std_ulogic; + way_wen_h :in std_ulogic; + + raddr_01 :in std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + raddr_23 :in std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + raddr_45 :in std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + raddr_67 :in std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + inj_parity_err :in std_ulogic; + + dir_arr_rd_addr_01 :out std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + dir_arr_rd_addr_23 :out std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + dir_arr_rd_addr_45 :out std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + dir_arr_rd_addr_67 :out std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + dir_arr_rd_data :in std_ulogic_vector(0 to 8*wayDataSize-1); + + dir_wr_way :out std_ulogic_vector(0 to 7); + dir_arr_wr_addr :out std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + dir_arr_wr_data :out std_ulogic_vector(64-real_data_add to 64-real_data_add+wayDataSize-1); + + way_tag_a :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + way_tag_b :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + way_tag_c :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + way_tag_d :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + way_tag_e :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + way_tag_f :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + way_tag_g :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + way_tag_h :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + + way_arr_par_a :out std_ulogic_vector(0 to parityBits-1); + way_arr_par_b :out std_ulogic_vector(0 to parityBits-1); + way_arr_par_c :out std_ulogic_vector(0 to parityBits-1); + way_arr_par_d :out std_ulogic_vector(0 to parityBits-1); + way_arr_par_e :out std_ulogic_vector(0 to parityBits-1); + way_arr_par_f :out std_ulogic_vector(0 to parityBits-1); + way_arr_par_g :out std_ulogic_vector(0 to parityBits-1); + way_arr_par_h :out std_ulogic_vector(0 to parityBits-1); + + par_gen_a_1b :out std_ulogic_vector(0 to parityBits-1); + par_gen_a_2b :out std_ulogic_vector(0 to parityBits-1); + par_gen_b_1b :out std_ulogic_vector(0 to parityBits-1); + par_gen_b_2b :out std_ulogic_vector(0 to parityBits-1); + par_gen_c_1b :out std_ulogic_vector(0 to parityBits-1); + par_gen_c_2b :out std_ulogic_vector(0 to parityBits-1); + par_gen_d_1b :out std_ulogic_vector(0 to parityBits-1); + par_gen_d_2b :out std_ulogic_vector(0 to parityBits-1); + par_gen_e_1b :out std_ulogic_vector(0 to parityBits-1); + par_gen_e_2b :out std_ulogic_vector(0 to parityBits-1); + par_gen_f_1b :out std_ulogic_vector(0 to parityBits-1); + par_gen_f_2b :out std_ulogic_vector(0 to parityBits-1); + par_gen_g_1b :out std_ulogic_vector(0 to parityBits-1); + par_gen_g_2b :out std_ulogic_vector(0 to parityBits-1); + par_gen_h_1b :out std_ulogic_vector(0 to parityBits-1); + par_gen_h_2b :out std_ulogic_vector(0 to parityBits-1) + ); +-- synopsys translate_off +-- synopsys translate_on +end xuq_lsu_dir_tag_arr; +architecture xuq_lsu_dir_tag_arr of xuq_lsu_dir_tag_arr is + + +constant uprTagBit :natural := 64-real_data_add; +constant lwrTagBit :natural := 63-(dc_size-3); +constant tagSize :natural := lwrTagBit-uprTagBit+1; +constant parExtCalc :natural := 8 - (tagSize mod 8); +constant parBits :natural := (tagSize+parExtCalc) / 8; + +signal wr_data :std_ulogic_vector(uprTagBit to lwrTagBit); +signal wr_wayA :std_ulogic; +signal wr_wayB :std_ulogic; +signal wr_wayC :std_ulogic; +signal wr_wayD :std_ulogic; +signal wr_wayE :std_ulogic; +signal wr_wayF :std_ulogic; +signal wr_wayG :std_ulogic; +signal wr_wayH :std_ulogic; +signal wr_way :std_ulogic_vector(0 to 7); +signal rd_wayA :std_ulogic_vector(uprTagBit to lwrTagBit); +signal rd_wayB :std_ulogic_vector(uprTagBit to lwrTagBit); +signal rd_wayC :std_ulogic_vector(uprTagBit to lwrTagBit); +signal rd_wayD :std_ulogic_vector(uprTagBit to lwrTagBit); +signal rd_wayE :std_ulogic_vector(uprTagBit to lwrTagBit); +signal rd_wayF :std_ulogic_vector(uprTagBit to lwrTagBit); +signal rd_wayG :std_ulogic_vector(uprTagBit to lwrTagBit); +signal rd_wayH :std_ulogic_vector(uprTagBit to lwrTagBit); +signal arr_rd_data :std_ulogic_vector(0 to 8*wayDataSize-1); +signal arr_parity :std_ulogic_vector(0 to parBits-1); +signal extra_byte_par :std_ulogic_vector(0 to 7); +signal arr_wr_data :std_ulogic_vector(uprTagBit to lwrTagBit+parBits); +signal rd_parA :std_ulogic_vector(0 to parBits-1); +signal rd_parB :std_ulogic_vector(0 to parBits-1); +signal rd_parC :std_ulogic_vector(0 to parBits-1); +signal rd_parD :std_ulogic_vector(0 to parBits-1); +signal rd_parE :std_ulogic_vector(0 to parBits-1); +signal rd_parF :std_ulogic_vector(0 to parBits-1); +signal rd_parG :std_ulogic_vector(0 to parBits-1); +signal rd_parH :std_ulogic_vector(0 to parBits-1); +signal extra_tagA_par :std_ulogic_vector(0 to 7); +signal extra_tagB_par :std_ulogic_vector(0 to 7); +signal extra_tagC_par :std_ulogic_vector(0 to 7); +signal extra_tagD_par :std_ulogic_vector(0 to 7); +signal extra_tagE_par :std_ulogic_vector(0 to 7); +signal extra_tagF_par :std_ulogic_vector(0 to 7); +signal extra_tagG_par :std_ulogic_vector(0 to 7); +signal extra_tagH_par :std_ulogic_vector(0 to 7); +signal par_genA_1stlvla :std_ulogic_vector(0 to parBits-1); +signal par_genA_1stlvlb :std_ulogic_vector(0 to parBits-1); +signal par_genA_1stlvlc :std_ulogic_vector(0 to parBits-1); +signal par_genA_1stlvld :std_ulogic_vector(0 to parBits-1); +signal parity_genA_1b :std_ulogic_vector(0 to parBits-1); +signal parity_genA_2b :std_ulogic_vector(0 to parBits-1); +signal par_genB_1stlvla :std_ulogic_vector(0 to parBits-1); +signal par_genB_1stlvlb :std_ulogic_vector(0 to parBits-1); +signal par_genB_1stlvlc :std_ulogic_vector(0 to parBits-1); +signal par_genB_1stlvld :std_ulogic_vector(0 to parBits-1); +signal parity_genB_1b :std_ulogic_vector(0 to parBits-1); +signal parity_genB_2b :std_ulogic_vector(0 to parBits-1); +signal par_genC_1stlvla :std_ulogic_vector(0 to parBits-1); +signal par_genC_1stlvlb :std_ulogic_vector(0 to parBits-1); +signal par_genC_1stlvlc :std_ulogic_vector(0 to parBits-1); +signal par_genC_1stlvld :std_ulogic_vector(0 to parBits-1); +signal parity_genC_1b :std_ulogic_vector(0 to parBits-1); +signal parity_genC_2b :std_ulogic_vector(0 to parBits-1); +signal par_genD_1stlvla :std_ulogic_vector(0 to parBits-1); +signal par_genD_1stlvlb :std_ulogic_vector(0 to parBits-1); +signal par_genD_1stlvlc :std_ulogic_vector(0 to parBits-1); +signal par_genD_1stlvld :std_ulogic_vector(0 to parBits-1); +signal parity_genD_1b :std_ulogic_vector(0 to parBits-1); +signal parity_genD_2b :std_ulogic_vector(0 to parBits-1); +signal par_genE_1stlvla :std_ulogic_vector(0 to parBits-1); +signal par_genE_1stlvlb :std_ulogic_vector(0 to parBits-1); +signal par_genE_1stlvlc :std_ulogic_vector(0 to parBits-1); +signal par_genE_1stlvld :std_ulogic_vector(0 to parBits-1); +signal parity_genE_1b :std_ulogic_vector(0 to parBits-1); +signal parity_genE_2b :std_ulogic_vector(0 to parBits-1); +signal par_genF_1stlvla :std_ulogic_vector(0 to parBits-1); +signal par_genF_1stlvlb :std_ulogic_vector(0 to parBits-1); +signal par_genF_1stlvlc :std_ulogic_vector(0 to parBits-1); +signal par_genF_1stlvld :std_ulogic_vector(0 to parBits-1); +signal parity_genF_1b :std_ulogic_vector(0 to parBits-1); +signal parity_genF_2b :std_ulogic_vector(0 to parBits-1); +signal par_genG_1stlvla :std_ulogic_vector(0 to parBits-1); +signal par_genG_1stlvlb :std_ulogic_vector(0 to parBits-1); +signal par_genG_1stlvlc :std_ulogic_vector(0 to parBits-1); +signal par_genG_1stlvld :std_ulogic_vector(0 to parBits-1); +signal parity_genG_1b :std_ulogic_vector(0 to parBits-1); +signal parity_genG_2b :std_ulogic_vector(0 to parBits-1); +signal par_genH_1stlvla :std_ulogic_vector(0 to parBits-1); +signal par_genH_1stlvlb :std_ulogic_vector(0 to parBits-1); +signal par_genH_1stlvlc :std_ulogic_vector(0 to parBits-1); +signal par_genH_1stlvld :std_ulogic_vector(0 to parBits-1); +signal parity_genH_1b :std_ulogic_vector(0 to parBits-1); +signal parity_genH_2b :std_ulogic_vector(0 to parBits-1); + + +begin + + +wr_wayA <= way_wen_a; +wr_wayB <= way_wen_b; +wr_wayC <= way_wen_c; +wr_wayD <= way_wen_d; +wr_wayE <= way_wen_e; +wr_wayF <= way_wen_f; +wr_wayG <= way_wen_g; +wr_wayH <= way_wen_h; +arr_rd_data <= dir_arr_rd_data; +wr_data <= wdata; + + +extra_byte : for t in 0 to 7 generate begin + R0:if(t < (tagSize mod 8)) generate begin extra_byte_par(t) <= wr_data(uprTagBit+(8*(tagSize/8))+t); + end generate; + R1:if(t >= (tagSize mod 8)) generate begin extra_byte_par(t) <= '0'; + end generate; +end generate extra_byte; + +par_gen : for i in 0 to (tagSize/8)-1 generate begin + arr_parity(i) <= xor_reduce(wr_data(8*i+uprTagBit to 8*i+uprTagBit+7)); +end generate par_gen; + +par_gen_x : if (tagSize mod 8) /= 0 generate begin + arr_parity(tagSize/8) <= xor_reduce(extra_byte_par); +end generate par_gen_x; + +arr_wr_data <= wr_data & arr_parity; + +wr_way <= wr_wayA & wr_wayB & wr_wayC & wr_wayD & + wr_wayE & wr_wayF & wr_wayG & wr_wayH; + + +rd_wayA(uprTagBit) <= arr_rd_data(0) xor inj_parity_err; +rd_wayA(uprTagBit+1 to lwrTagBit) <= arr_rd_data(1 to (0*wayDataSize)+tagSize-1); + +rd_wayB <= arr_rd_data((1*wayDataSize) to (1*wayDataSize)+tagSize-1); +rd_wayC <= arr_rd_data((2*wayDataSize) to (2*wayDataSize)+tagSize-1); +rd_wayD <= arr_rd_data((3*wayDataSize) to (3*wayDataSize)+tagSize-1); +rd_wayE <= arr_rd_data((4*wayDataSize) to (4*wayDataSize)+tagSize-1); +rd_wayF <= arr_rd_data((5*wayDataSize) to (5*wayDataSize)+tagSize-1); +rd_wayG <= arr_rd_data((6*wayDataSize) to (6*wayDataSize)+tagSize-1); +rd_wayH <= arr_rd_data((7*wayDataSize) to (7*wayDataSize)+tagSize-1); + +rd_parA <= arr_rd_data((0*wayDataSize)+tagSize to (0*wayDataSize)+tagSize+parBits-1); +rd_parB <= arr_rd_data((1*wayDataSize)+tagSize to (1*wayDataSize)+tagSize+parBits-1); +rd_parC <= arr_rd_data((2*wayDataSize)+tagSize to (2*wayDataSize)+tagSize+parBits-1); +rd_parD <= arr_rd_data((3*wayDataSize)+tagSize to (3*wayDataSize)+tagSize+parBits-1); +rd_parE <= arr_rd_data((4*wayDataSize)+tagSize to (4*wayDataSize)+tagSize+parBits-1); +rd_parF <= arr_rd_data((5*wayDataSize)+tagSize to (5*wayDataSize)+tagSize+parBits-1); +rd_parG <= arr_rd_data((6*wayDataSize)+tagSize to (6*wayDataSize)+tagSize+parBits-1); +rd_parH <= arr_rd_data((7*wayDataSize)+tagSize to (7*wayDataSize)+tagSize+parBits-1); + + +rdExtraByte : for t in 0 to 7 generate begin + R0: if(t < (tagSize mod 8)) generate + begin + extra_tagA_par(t) <= rd_wayA(uprTagBit+(8*(tagSize/8))+t); + extra_tagB_par(t) <= rd_wayB(uprTagBit+(8*(tagSize/8))+t); + extra_tagC_par(t) <= rd_wayC(uprTagBit+(8*(tagSize/8))+t); + extra_tagD_par(t) <= rd_wayD(uprTagBit+(8*(tagSize/8))+t); + extra_tagE_par(t) <= rd_wayE(uprTagBit+(8*(tagSize/8))+t); + extra_tagF_par(t) <= rd_wayF(uprTagBit+(8*(tagSize/8))+t); + extra_tagG_par(t) <= rd_wayG(uprTagBit+(8*(tagSize/8))+t); + extra_tagH_par(t) <= rd_wayH(uprTagBit+(8*(tagSize/8))+t); + end generate; + R1: if(t >= (tagSize mod 8)) generate + begin + extra_tagA_par(t) <= '0'; + extra_tagB_par(t) <= '0'; + extra_tagC_par(t) <= '0'; + extra_tagD_par(t) <= '0'; + extra_tagE_par(t) <= '0'; + extra_tagF_par(t) <= '0'; + extra_tagG_par(t) <= '0'; + extra_tagH_par(t) <= '0'; + end generate; +end generate rdExtraByte; + +rdParGen : for i in 0 to (tagSize/8)-1 generate +begin + + parA1lvla : par_genA_1stlvla(i) <= not (rd_wayA(8*i+uprTagBit+0) xor rd_wayA(8*i+uprTagBit+1)); + parA1lvlb : par_genA_1stlvlb(i) <= not (rd_wayA(8*i+uprTagBit+2) xor rd_wayA(8*i+uprTagBit+3)); + parA1lvlc : par_genA_1stlvlc(i) <= not (rd_wayA(8*i+uprTagBit+4) xor rd_wayA(8*i+uprTagBit+5)); + parA1lvld : par_genA_1stlvld(i) <= not (rd_wayA(8*i+uprTagBit+6) xor rd_wayA(8*i+uprTagBit+7)); + parGenA1b : parity_genA_1b(i) <= not (par_genA_1stlvla(i) xor par_genA_1stlvlb(i)); + parGenA2b : parity_genA_2b(i) <= not (par_genA_1stlvlc(i) xor par_genA_1stlvld(i)); + + parB1lvla : par_genB_1stlvla(i) <= not (rd_wayB(8*i+uprTagBit+0) xor rd_wayB(8*i+uprTagBit+1)); + parB1lvlb : par_genB_1stlvlb(i) <= not (rd_wayB(8*i+uprTagBit+2) xor rd_wayB(8*i+uprTagBit+3)); + parB1lvlc : par_genB_1stlvlc(i) <= not (rd_wayB(8*i+uprTagBit+4) xor rd_wayB(8*i+uprTagBit+5)); + parB1lvld : par_genB_1stlvld(i) <= not (rd_wayB(8*i+uprTagBit+6) xor rd_wayB(8*i+uprTagBit+7)); + parGenB1b : parity_genB_1b(i) <= not (par_genB_1stlvla(i) xor par_genB_1stlvlb(i)); + parGenB2b : parity_genB_2b(i) <= not (par_genB_1stlvlc(i) xor par_genB_1stlvld(i)); + + parC1lvla : par_genC_1stlvla(i) <= not (rd_wayC(8*i+uprTagBit+0) xor rd_wayC(8*i+uprTagBit+1)); + parC1lvlb : par_genC_1stlvlb(i) <= not (rd_wayC(8*i+uprTagBit+2) xor rd_wayC(8*i+uprTagBit+3)); + parC1lvlc : par_genC_1stlvlc(i) <= not (rd_wayC(8*i+uprTagBit+4) xor rd_wayC(8*i+uprTagBit+5)); + parC1lvld : par_genC_1stlvld(i) <= not (rd_wayC(8*i+uprTagBit+6) xor rd_wayC(8*i+uprTagBit+7)); + parGenC1b : parity_genC_1b(i) <= not (par_genC_1stlvla(i) xor par_genC_1stlvlb(i)); + parGenC2b : parity_genC_2b(i) <= not (par_genC_1stlvlc(i) xor par_genC_1stlvld(i)); + + parD1lvla : par_genD_1stlvla(i) <= not (rd_wayD(8*i+uprTagBit+0) xor rd_wayD(8*i+uprTagBit+1)); + parD1lvlb : par_genD_1stlvlb(i) <= not (rd_wayD(8*i+uprTagBit+2) xor rd_wayD(8*i+uprTagBit+3)); + parD1lvlc : par_genD_1stlvlc(i) <= not (rd_wayD(8*i+uprTagBit+4) xor rd_wayD(8*i+uprTagBit+5)); + parD1lvld : par_genD_1stlvld(i) <= not (rd_wayD(8*i+uprTagBit+6) xor rd_wayD(8*i+uprTagBit+7)); + parGenD1b : parity_genD_1b(i) <= not (par_genD_1stlvla(i) xor par_genD_1stlvlb(i)); + parGenD2b : parity_genD_2b(i) <= not (par_genD_1stlvlc(i) xor par_genD_1stlvld(i)); + + parE1lvla : par_genE_1stlvla(i) <= not (rd_wayE(8*i+uprTagBit+0) xor rd_wayE(8*i+uprTagBit+1)); + parE1lvlb : par_genE_1stlvlb(i) <= not (rd_wayE(8*i+uprTagBit+2) xor rd_wayE(8*i+uprTagBit+3)); + parE1lvlc : par_genE_1stlvlc(i) <= not (rd_wayE(8*i+uprTagBit+4) xor rd_wayE(8*i+uprTagBit+5)); + parE1lvld : par_genE_1stlvld(i) <= not (rd_wayE(8*i+uprTagBit+6) xor rd_wayE(8*i+uprTagBit+7)); + parGenE1b : parity_genE_1b(i) <= not (par_genE_1stlvla(i) xor par_genE_1stlvlb(i)); + parGenE2b : parity_genE_2b(i) <= not (par_genE_1stlvlc(i) xor par_genE_1stlvld(i)); + + parF1lvla : par_genF_1stlvla(i) <= not (rd_wayF(8*i+uprTagBit+0) xor rd_wayF(8*i+uprTagBit+1)); + parF1lvlb : par_genF_1stlvlb(i) <= not (rd_wayF(8*i+uprTagBit+2) xor rd_wayF(8*i+uprTagBit+3)); + parF1lvlc : par_genF_1stlvlc(i) <= not (rd_wayF(8*i+uprTagBit+4) xor rd_wayF(8*i+uprTagBit+5)); + parF1lvld : par_genF_1stlvld(i) <= not (rd_wayF(8*i+uprTagBit+6) xor rd_wayF(8*i+uprTagBit+7)); + parGenF1b : parity_genF_1b(i) <= not (par_genF_1stlvla(i) xor par_genF_1stlvlb(i)); + parGenF2b : parity_genF_2b(i) <= not (par_genF_1stlvlc(i) xor par_genF_1stlvld(i)); + + parG1lvla : par_genG_1stlvla(i) <= not (rd_wayG(8*i+uprTagBit+0) xor rd_wayG(8*i+uprTagBit+1)); + parG1lvlb : par_genG_1stlvlb(i) <= not (rd_wayG(8*i+uprTagBit+2) xor rd_wayG(8*i+uprTagBit+3)); + parG1lvlc : par_genG_1stlvlc(i) <= not (rd_wayG(8*i+uprTagBit+4) xor rd_wayG(8*i+uprTagBit+5)); + parG1lvld : par_genG_1stlvld(i) <= not (rd_wayG(8*i+uprTagBit+6) xor rd_wayG(8*i+uprTagBit+7)); + parGenG1b : parity_genG_1b(i) <= not (par_genG_1stlvla(i) xor par_genG_1stlvlb(i)); + parGenG2b : parity_genG_2b(i) <= not (par_genG_1stlvlc(i) xor par_genG_1stlvld(i)); + + parH1lvla : par_genH_1stlvla(i) <= not (rd_wayH(8*i+uprTagBit+0) xor rd_wayH(8*i+uprTagBit+1)); + parH1lvlb : par_genH_1stlvlb(i) <= not (rd_wayH(8*i+uprTagBit+2) xor rd_wayH(8*i+uprTagBit+3)); + parH1lvlc : par_genH_1stlvlc(i) <= not (rd_wayH(8*i+uprTagBit+4) xor rd_wayH(8*i+uprTagBit+5)); + parH1lvld : par_genH_1stlvld(i) <= not (rd_wayH(8*i+uprTagBit+6) xor rd_wayH(8*i+uprTagBit+7)); + parGenH1b : parity_genH_1b(i) <= not (par_genH_1stlvla(i) xor par_genH_1stlvlb(i)); + parGenH2b : parity_genH_2b(i) <= not (par_genH_1stlvlc(i) xor par_genH_1stlvld(i)); +end generate rdParGen; + +rdParGenx : if (tagSize mod 8) /= 0 generate +begin + EparA1lvla : par_genA_1stlvla(parBits-1) <= not (extra_tagA_par(0) xor extra_tagA_par(1)); + EparA1lvlb : par_genA_1stlvlb(parBits-1) <= not (extra_tagA_par(2) xor extra_tagA_par(3)); + EparA1lvlc : par_genA_1stlvlc(parBits-1) <= not (extra_tagA_par(4) xor extra_tagA_par(5)); + EparA1lvld : par_genA_1stlvld(parBits-1) <= not (extra_tagA_par(6) xor extra_tagA_par(7)); + EparGenA1b : parity_genA_1b(parBits-1) <= not (par_genA_1stlvla(parBits-1) xor par_genA_1stlvlb(parBits-1)); + EparGenA2b : parity_genA_2b(parBits-1) <= not (par_genA_1stlvlc(parBits-1) xor par_genA_1stlvld(parBits-1)); + + EparB1lvla : par_genB_1stlvla(parBits-1) <= not (extra_tagB_par(0) xor extra_tagB_par(1)); + EparB1lvlb : par_genB_1stlvlb(parBits-1) <= not (extra_tagB_par(2) xor extra_tagB_par(3)); + EparB1lvlc : par_genB_1stlvlc(parBits-1) <= not (extra_tagB_par(4) xor extra_tagB_par(5)); + EparB1lvld : par_genB_1stlvld(parBits-1) <= not (extra_tagB_par(6) xor extra_tagB_par(7)); + EparGenB1b : parity_genB_1b(parBits-1) <= not (par_genB_1stlvla(parBits-1) xor par_genB_1stlvlb(parBits-1)); + EparGenB2b : parity_genB_2b(parBits-1) <= not (par_genB_1stlvlc(parBits-1) xor par_genB_1stlvld(parBits-1)); + + EparC1lvla : par_genC_1stlvla(parBits-1) <= not (extra_tagC_par(0) xor extra_tagC_par(1)); + EparC1lvlb : par_genC_1stlvlb(parBits-1) <= not (extra_tagC_par(2) xor extra_tagC_par(3)); + EparC1lvlc : par_genC_1stlvlc(parBits-1) <= not (extra_tagC_par(4) xor extra_tagC_par(5)); + EparC1lvld : par_genC_1stlvld(parBits-1) <= not (extra_tagC_par(6) xor extra_tagC_par(7)); + EparGenC1b : parity_genC_1b(parBits-1) <= not (par_genC_1stlvla(parBits-1) xor par_genC_1stlvlb(parBits-1)); + EparGenC2b : parity_genC_2b(parBits-1) <= not (par_genC_1stlvlc(parBits-1) xor par_genC_1stlvld(parBits-1)); + + EparD1lvla : par_genD_1stlvla(parBits-1) <= not (extra_tagD_par(0) xor extra_tagD_par(1)); + EparD1lvlb : par_genD_1stlvlb(parBits-1) <= not (extra_tagD_par(2) xor extra_tagD_par(3)); + EparD1lvlc : par_genD_1stlvlc(parBits-1) <= not (extra_tagD_par(4) xor extra_tagD_par(5)); + EparD1lvld : par_genD_1stlvld(parBits-1) <= not (extra_tagD_par(6) xor extra_tagD_par(7)); + EparGenD1b : parity_genD_1b(parBits-1) <= not (par_genD_1stlvla(parBits-1) xor par_genD_1stlvlb(parBits-1)); + EparGenD2b : parity_genD_2b(parBits-1) <= not (par_genD_1stlvlc(parBits-1) xor par_genD_1stlvld(parBits-1)); + + EparE1lvla : par_genE_1stlvla(parBits-1) <= not (extra_tagE_par(0) xor extra_tagE_par(1)); + EparE1lvlb : par_genE_1stlvlb(parBits-1) <= not (extra_tagE_par(2) xor extra_tagE_par(3)); + EparE1lvlc : par_genE_1stlvlc(parBits-1) <= not (extra_tagE_par(4) xor extra_tagE_par(5)); + EparE1lvld : par_genE_1stlvld(parBits-1) <= not (extra_tagE_par(6) xor extra_tagE_par(7)); + EparGenE1b : parity_genE_1b(parBits-1) <= not (par_genE_1stlvla(parBits-1) xor par_genE_1stlvlb(parBits-1)); + EparGenE2b : parity_genE_2b(parBits-1) <= not (par_genE_1stlvlc(parBits-1) xor par_genE_1stlvld(parBits-1)); + + EparF1lvla : par_genF_1stlvla(parBits-1) <= not (extra_tagF_par(0) xor extra_tagF_par(1)); + EparF1lvlb : par_genF_1stlvlb(parBits-1) <= not (extra_tagF_par(2) xor extra_tagF_par(3)); + EparF1lvlc : par_genF_1stlvlc(parBits-1) <= not (extra_tagF_par(4) xor extra_tagF_par(5)); + EparF1lvld : par_genF_1stlvld(parBits-1) <= not (extra_tagF_par(6) xor extra_tagF_par(7)); + EparGenF1b : parity_genF_1b(parBits-1) <= not (par_genF_1stlvla(parBits-1) xor par_genF_1stlvlb(parBits-1)); + EparGenF2b : parity_genF_2b(parBits-1) <= not (par_genF_1stlvlc(parBits-1) xor par_genF_1stlvld(parBits-1)); + + EparG1lvla : par_genG_1stlvla(parBits-1) <= not (extra_tagG_par(0) xor extra_tagG_par(1)); + EparG1lvlb : par_genG_1stlvlb(parBits-1) <= not (extra_tagG_par(2) xor extra_tagG_par(3)); + EparG1lvlc : par_genG_1stlvlc(parBits-1) <= not (extra_tagG_par(4) xor extra_tagG_par(5)); + EparG1lvld : par_genG_1stlvld(parBits-1) <= not (extra_tagG_par(6) xor extra_tagG_par(7)); + EparGenG1b : parity_genG_1b(parBits-1) <= not (par_genG_1stlvla(parBits-1) xor par_genG_1stlvlb(parBits-1)); + EparGenG2b : parity_genG_2b(parBits-1) <= not (par_genG_1stlvlc(parBits-1) xor par_genG_1stlvld(parBits-1)); + + EparH1lvla : par_genH_1stlvla(parBits-1) <= not (extra_tagH_par(0) xor extra_tagH_par(1)); + EparH1lvlb : par_genH_1stlvlb(parBits-1) <= not (extra_tagH_par(2) xor extra_tagH_par(3)); + EparH1lvlc : par_genH_1stlvlc(parBits-1) <= not (extra_tagH_par(4) xor extra_tagH_par(5)); + EparH1lvld : par_genH_1stlvld(parBits-1) <= not (extra_tagH_par(6) xor extra_tagH_par(7)); + EparGenH1b : parity_genH_1b(parBits-1) <= not (par_genH_1stlvla(parBits-1) xor par_genH_1stlvlb(parBits-1)); + EparGenH2b : parity_genH_2b(parBits-1) <= not (par_genH_1stlvlc(parBits-1) xor par_genH_1stlvld(parBits-1)); +end generate rdParGenx; + + + +par_gen_a_1b <= parity_genA_1b; +par_gen_b_1b <= parity_genB_1b; +par_gen_c_1b <= parity_genC_1b; +par_gen_d_1b <= parity_genD_1b; +par_gen_e_1b <= parity_genE_1b; +par_gen_f_1b <= parity_genF_1b; +par_gen_g_1b <= parity_genG_1b; +par_gen_h_1b <= parity_genH_1b; +par_gen_a_2b <= parity_genA_2b; +par_gen_b_2b <= parity_genB_2b; +par_gen_c_2b <= parity_genC_2b; +par_gen_d_2b <= parity_genD_2b; +par_gen_e_2b <= parity_genE_2b; +par_gen_f_2b <= parity_genF_2b; +par_gen_g_2b <= parity_genG_2b; +par_gen_h_2b <= parity_genH_2b; + + +dir_wr_way <= wr_way; +dir_arr_rd_addr_01 <= raddr_01; +dir_arr_rd_addr_23 <= raddr_23; +dir_arr_rd_addr_45 <= raddr_45; +dir_arr_rd_addr_67 <= raddr_67; +dir_arr_wr_addr <= waddr; +dir_arr_wr_data <= arr_wr_data; + +way_tag_a <= rd_wayA; +way_tag_b <= rd_wayB; +way_tag_c <= rd_wayC; +way_tag_d <= rd_wayD; +way_tag_e <= rd_wayE; +way_tag_f <= rd_wayF; +way_tag_g <= rd_wayG; +way_tag_h <= rd_wayH; + +way_arr_par_a <= rd_parA; +way_arr_par_b <= rd_parB; +way_arr_par_c <= rd_parC; +way_arr_par_d <= rd_parD; +way_arr_par_e <= rd_parE; +way_arr_par_f <= rd_parF; +way_arr_par_g <= rd_parG; +way_arr_par_h <= rd_parH; + +end xuq_lsu_dir_tag_arr; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_dir_val16.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_dir_val16.vhdl new file mode 100644 index 0000000..2f256e6 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_dir_val16.vhdl @@ -0,0 +1,24723 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ibm, ieee, work, tri, support; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use tri.tri_latches_pkg.all; +use support.power_logic_pkg.all; + +entity xuq_lsu_dir_val16 is +generic(expand_type : integer := 2; + dc_size : natural := 14; + cl_size : natural := 6); +port( + + ex1_stg_act :in std_ulogic; + ex2_stg_act :in std_ulogic; + ex3_stg_act :in std_ulogic; + ex4_stg_act :in std_ulogic; + ex5_stg_act :in std_ulogic; + binv1_stg_act :in std_ulogic; + binv2_stg_act :in std_ulogic; + binv3_stg_act :in std_ulogic; + binv4_stg_act :in std_ulogic; + binv5_stg_act :in std_ulogic; + rel1_stg_act :in std_ulogic; + rel2_stg_act :in std_ulogic; + + ldq_rel1_early_v :in std_ulogic; + rel1_val :in std_ulogic; + rel_addr_early :in std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + rel_lock_en :in std_ulogic; + rel_l1dump_cslc :in std_ulogic; + rel3_l1dump_val :in std_ulogic; + rel4_ecc_err :in std_ulogic; + rel_watch_en :in std_ulogic; + rel_thrd_id :in std_ulogic_vector(0 to 3); + rel_way_clr_a :in std_ulogic; + rel_way_clr_b :in std_ulogic; + rel_way_clr_c :in std_ulogic; + rel_way_clr_d :in std_ulogic; + rel_way_clr_e :in std_ulogic; + rel_way_clr_f :in std_ulogic; + rel_way_clr_g :in std_ulogic; + rel_way_clr_h :in std_ulogic; + + ldq_rel3_early_v :in std_ulogic; + rel3_val :in std_ulogic; + rel_back_inval :in std_ulogic; + rel4_set_val :in std_ulogic; + rel4_recirc_val :in std_ulogic; + rel_way_wen_a :in std_ulogic; + rel_way_wen_b :in std_ulogic; + rel_way_wen_c :in std_ulogic; + rel_way_wen_d :in std_ulogic; + rel_way_wen_e :in std_ulogic; + rel_way_wen_f :in std_ulogic; + rel_way_wen_g :in std_ulogic; + rel_way_wen_h :in std_ulogic; + rel_up_way_addr_b :in std_ulogic_vector(0 to 2); + rel_dcarr_addr_en :in std_ulogic; + + xu_lsu_dci :in std_ulogic; + xu_lsu_spr_xucr0_clfc :in std_ulogic; + spr_xucr0_dcdis :in std_ulogic; + spr_xucr0_cls :in std_ulogic; + + ex1_thrd_id :in std_ulogic_vector(0 to 3); + ex1_p_addr :in std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + ex2_is_inval_op :in std_ulogic; + ex2_lock_set :in std_ulogic; + ex2_lock_clr :in std_ulogic; + ex3_cache_acc :in std_ulogic; + ex3_cache_en :in std_ulogic; + ex3_tag_way_perr :in std_ulogic_vector(0 to 7); + ex5_load_op_hit :in std_ulogic; + ex6_ld_par_err :in std_ulogic; + ex2_ldawx_instr :in std_ulogic; + ex2_wclr_instr :in std_ulogic; + ex2_wchk_val :in std_ulogic; + ex2_l_fld :in std_ulogic_vector(0 to 1); + ex2_store_instr :in std_ulogic; + ex3_load_val :in std_ulogic; + ex3_wimge_i_bit :in std_ulogic; + ex3_l2_request :in std_ulogic; + ex3_ldq_potential_flush :in std_ulogic; + + inv1_val :in std_ulogic; + + ex3_way_cmp_a :in std_ulogic; + ex3_way_cmp_b :in std_ulogic; + ex3_way_cmp_c :in std_ulogic; + ex3_way_cmp_d :in std_ulogic; + ex3_way_cmp_e :in std_ulogic; + ex3_way_cmp_f :in std_ulogic; + ex3_way_cmp_g :in std_ulogic; + ex3_way_cmp_h :in std_ulogic; + + ex2_stg_flush :in std_ulogic; + ex3_stg_flush :in std_ulogic; + ex4_stg_flush :in std_ulogic; + ex5_stg_flush :in std_ulogic; + + pc_xu_inj_dcachedir_multihit :in std_ulogic; + + ex4_way_a_dir :out std_ulogic_vector(0 to 5); + ex4_way_b_dir :out std_ulogic_vector(0 to 5); + ex4_way_c_dir :out std_ulogic_vector(0 to 5); + ex4_way_d_dir :out std_ulogic_vector(0 to 5); + ex4_way_e_dir :out std_ulogic_vector(0 to 5); + ex4_way_f_dir :out std_ulogic_vector(0 to 5); + ex4_way_g_dir :out std_ulogic_vector(0 to 5); + ex4_way_h_dir :out std_ulogic_vector(0 to 5); + + ex4_way_a_hit :out std_ulogic; + ex4_way_b_hit :out std_ulogic; + ex4_way_c_hit :out std_ulogic; + ex4_way_d_hit :out std_ulogic; + ex4_way_e_hit :out std_ulogic; + ex4_way_f_hit :out std_ulogic; + ex4_way_g_hit :out std_ulogic; + ex4_way_h_hit :out std_ulogic; + + ex3_cClass_upd_way_a :out std_ulogic; + ex3_cClass_upd_way_b :out std_ulogic; + ex3_cClass_upd_way_c :out std_ulogic; + ex3_cClass_upd_way_d :out std_ulogic; + ex3_cClass_upd_way_e :out std_ulogic; + ex3_cClass_upd_way_f :out std_ulogic; + ex3_cClass_upd_way_g :out std_ulogic; + ex3_cClass_upd_way_h :out std_ulogic; + + ex2_lockwatchSet_rel_coll :out std_ulogic; + ex3_wclr_all_flush :out std_ulogic; + + ex3_hit :out std_ulogic; + ex3_dir_perr_det :out std_ulogic; + ex4_dir_multihit_det :out std_ulogic; + ex4_n_lsu_ddmh_flush :out std_ulogic_vector(0 to 3); + ex4_ldq_full_flush :out std_ulogic; + ex4_miss :out std_ulogic; + ex4_snd_ld_l2 :out std_ulogic; + dcpar_err_flush :out std_ulogic; + pe_recov_begin :out std_ulogic; + + lsu_xu_ex5_cr_rslt :out std_ulogic; + + rel_way_val_a :out std_ulogic; + rel_way_val_b :out std_ulogic; + rel_way_val_c :out std_ulogic; + rel_way_val_d :out std_ulogic; + rel_way_val_e :out std_ulogic; + rel_way_val_f :out std_ulogic; + rel_way_val_g :out std_ulogic; + rel_way_val_h :out std_ulogic; + + rel_way_lock_a :out std_ulogic; + rel_way_lock_b :out std_ulogic; + rel_way_lock_c :out std_ulogic; + rel_way_lock_d :out std_ulogic; + rel_way_lock_e :out std_ulogic; + rel_way_lock_f :out std_ulogic; + rel_way_lock_g :out std_ulogic; + rel_way_lock_h :out std_ulogic; + + dcarr_up_way_addr :out std_ulogic_vector(0 to 2); + + lsu_xu_perf_events :out std_ulogic_vector(0 to 16); + + lsu_xu_spr_xucr0_cslc_xuop :out std_ulogic; + lsu_xu_spr_xucr0_cslc_binv :out std_ulogic; + + dc_val_dbg_data :out std_ulogic_vector(0 to 293); + + vdd :inout power_logic; + gnd :inout power_logic; + nclk :in clk_logic; + sg_0 :in std_ulogic; + func_sl_thold_0_b :in std_ulogic; + func_sl_force :in std_ulogic; + func_slp_sl_thold_0_b :in std_ulogic; + func_slp_sl_force :in std_ulogic; + func_nsl_thold_0_b :in std_ulogic; + func_nsl_force :in std_ulogic; + func_slp_nsl_thold_0_b :in std_ulogic; + func_slp_nsl_force :in std_ulogic; + d_mode_dc :in std_ulogic; + delay_lclkr_dc :in std_ulogic; + mpw1_dc_b :in std_ulogic; + mpw2_dc_b :in std_ulogic; + scan_in :in std_ulogic_vector(0 to 2); + scan_out :out std_ulogic_vector(0 to 2) + ); +-- synopsys translate_off +-- synopsys translate_on +end xuq_lsu_dir_val16; +ARCHITECTURE XUQ_LSU_DIR_VAL16 + OF XUQ_LSU_DIR_VAL16 + IS +constant congr_cl0_wA_offset :natural := 0; +constant congr_cl0_wB_offset :natural := congr_cl0_wA_offset + 6; +constant congr_cl0_wC_offset :natural := congr_cl0_wB_offset + 6; +constant congr_cl0_wD_offset :natural := congr_cl0_wC_offset + 6; +constant congr_cl0_wE_offset :natural := congr_cl0_wD_offset + 6; +constant congr_cl0_wF_offset :natural := congr_cl0_wE_offset + 6; +constant congr_cl0_wG_offset :natural := congr_cl0_wF_offset + 6; +constant congr_cl0_wH_offset :natural := congr_cl0_wG_offset + 6; +constant congr_cl1_wA_offset :natural := congr_cl0_wH_offset + 6; +constant congr_cl1_wB_offset :natural := congr_cl1_wA_offset + 6; +constant congr_cl1_wC_offset :natural := congr_cl1_wB_offset + 6; +constant congr_cl1_wD_offset :natural := congr_cl1_wC_offset + 6; +constant congr_cl1_wE_offset :natural := congr_cl1_wD_offset + 6; +constant congr_cl1_wF_offset :natural := congr_cl1_wE_offset + 6; +constant congr_cl1_wG_offset :natural := congr_cl1_wF_offset + 6; +constant congr_cl1_wH_offset :natural := congr_cl1_wG_offset + 6; +constant congr_cl2_wA_offset :natural := congr_cl1_wH_offset + 6; +constant congr_cl2_wB_offset :natural := congr_cl2_wA_offset + 6; +constant congr_cl2_wC_offset :natural := congr_cl2_wB_offset + 6; +constant congr_cl2_wD_offset :natural := congr_cl2_wC_offset + 6; +constant congr_cl2_wE_offset :natural := congr_cl2_wD_offset + 6; +constant congr_cl2_wF_offset :natural := congr_cl2_wE_offset + 6; +constant congr_cl2_wG_offset :natural := congr_cl2_wF_offset + 6; +constant congr_cl2_wH_offset :natural := congr_cl2_wG_offset + 6; +constant congr_cl3_wA_offset :natural := congr_cl2_wH_offset + 6; +constant congr_cl3_wB_offset :natural := congr_cl3_wA_offset + 6; +constant congr_cl3_wC_offset :natural := congr_cl3_wB_offset + 6; +constant congr_cl3_wD_offset :natural := congr_cl3_wC_offset + 6; +constant congr_cl3_wE_offset :natural := congr_cl3_wD_offset + 6; +constant congr_cl3_wF_offset :natural := congr_cl3_wE_offset + 6; +constant congr_cl3_wG_offset :natural := congr_cl3_wF_offset + 6; +constant congr_cl3_wH_offset :natural := congr_cl3_wG_offset + 6; +constant congr_cl4_wA_offset :natural := congr_cl3_wH_offset + 6; +constant congr_cl4_wB_offset :natural := congr_cl4_wA_offset + 6; +constant congr_cl4_wC_offset :natural := congr_cl4_wB_offset + 6; +constant congr_cl4_wD_offset :natural := congr_cl4_wC_offset + 6; +constant congr_cl4_wE_offset :natural := congr_cl4_wD_offset + 6; +constant congr_cl4_wF_offset :natural := congr_cl4_wE_offset + 6; +constant congr_cl4_wG_offset :natural := congr_cl4_wF_offset + 6; +constant congr_cl4_wH_offset :natural := congr_cl4_wG_offset + 6; +constant congr_cl5_wA_offset :natural := congr_cl4_wH_offset + 6; +constant congr_cl5_wB_offset :natural := congr_cl5_wA_offset + 6; +constant congr_cl5_wC_offset :natural := congr_cl5_wB_offset + 6; +constant congr_cl5_wD_offset :natural := congr_cl5_wC_offset + 6; +constant congr_cl5_wE_offset :natural := congr_cl5_wD_offset + 6; +constant congr_cl5_wF_offset :natural := congr_cl5_wE_offset + 6; +constant congr_cl5_wG_offset :natural := congr_cl5_wF_offset + 6; +constant congr_cl5_wH_offset :natural := congr_cl5_wG_offset + 6; +constant congr_cl6_wA_offset :natural := congr_cl5_wH_offset + 6; +constant congr_cl6_wB_offset :natural := congr_cl6_wA_offset + 6; +constant congr_cl6_wC_offset :natural := congr_cl6_wB_offset + 6; +constant congr_cl6_wD_offset :natural := congr_cl6_wC_offset + 6; +constant congr_cl6_wE_offset :natural := congr_cl6_wD_offset + 6; +constant congr_cl6_wF_offset :natural := congr_cl6_wE_offset + 6; +constant congr_cl6_wG_offset :natural := congr_cl6_wF_offset + 6; +constant congr_cl6_wH_offset :natural := congr_cl6_wG_offset + 6; +constant congr_cl7_wA_offset :natural := congr_cl6_wH_offset + 6; +constant congr_cl7_wB_offset :natural := congr_cl7_wA_offset + 6; +constant congr_cl7_wC_offset :natural := congr_cl7_wB_offset + 6; +constant congr_cl7_wD_offset :natural := congr_cl7_wC_offset + 6; +constant congr_cl7_wE_offset :natural := congr_cl7_wD_offset + 6; +constant congr_cl7_wF_offset :natural := congr_cl7_wE_offset + 6; +constant congr_cl7_wG_offset :natural := congr_cl7_wF_offset + 6; +constant congr_cl7_wH_offset :natural := congr_cl7_wG_offset + 6; +constant congr_cl8_wA_offset :natural := congr_cl7_wH_offset + 6; +constant congr_cl8_wB_offset :natural := congr_cl8_wA_offset + 6; +constant congr_cl8_wC_offset :natural := congr_cl8_wB_offset + 6; +constant congr_cl8_wD_offset :natural := congr_cl8_wC_offset + 6; +constant congr_cl8_wE_offset :natural := congr_cl8_wD_offset + 6; +constant congr_cl8_wF_offset :natural := congr_cl8_wE_offset + 6; +constant congr_cl8_wG_offset :natural := congr_cl8_wF_offset + 6; +constant congr_cl8_wH_offset :natural := congr_cl8_wG_offset + 6; +constant congr_cl9_wA_offset :natural := congr_cl8_wH_offset + 6; +constant congr_cl9_wB_offset :natural := congr_cl9_wA_offset + 6; +constant congr_cl9_wC_offset :natural := congr_cl9_wB_offset + 6; +constant congr_cl9_wD_offset :natural := congr_cl9_wC_offset + 6; +constant congr_cl9_wE_offset :natural := congr_cl9_wD_offset + 6; +constant congr_cl9_wF_offset :natural := congr_cl9_wE_offset + 6; +constant congr_cl9_wG_offset :natural := congr_cl9_wF_offset + 6; +constant congr_cl9_wH_offset :natural := congr_cl9_wG_offset + 6; +constant congr_cl10_wA_offset :natural := congr_cl9_wH_offset + 6; +constant congr_cl10_wB_offset :natural := congr_cl10_wA_offset + 6; +constant congr_cl10_wC_offset :natural := congr_cl10_wB_offset + 6; +constant congr_cl10_wD_offset :natural := congr_cl10_wC_offset + 6; +constant congr_cl10_wE_offset :natural := congr_cl10_wD_offset + 6; +constant congr_cl10_wF_offset :natural := congr_cl10_wE_offset + 6; +constant congr_cl10_wG_offset :natural := congr_cl10_wF_offset + 6; +constant congr_cl10_wH_offset :natural := congr_cl10_wG_offset + 6; +constant congr_cl11_wA_offset :natural := congr_cl10_wH_offset + 6; +constant congr_cl11_wB_offset :natural := congr_cl11_wA_offset + 6; +constant congr_cl11_wC_offset :natural := congr_cl11_wB_offset + 6; +constant congr_cl11_wD_offset :natural := congr_cl11_wC_offset + 6; +constant congr_cl11_wE_offset :natural := congr_cl11_wD_offset + 6; +constant congr_cl11_wF_offset :natural := congr_cl11_wE_offset + 6; +constant congr_cl11_wG_offset :natural := congr_cl11_wF_offset + 6; +constant congr_cl11_wH_offset :natural := congr_cl11_wG_offset + 6; +constant congr_cl12_wA_offset :natural := congr_cl11_wH_offset + 6; +constant congr_cl12_wB_offset :natural := congr_cl12_wA_offset + 6; +constant congr_cl12_wC_offset :natural := congr_cl12_wB_offset + 6; +constant congr_cl12_wD_offset :natural := congr_cl12_wC_offset + 6; +constant congr_cl12_wE_offset :natural := congr_cl12_wD_offset + 6; +constant congr_cl12_wF_offset :natural := congr_cl12_wE_offset + 6; +constant congr_cl12_wG_offset :natural := congr_cl12_wF_offset + 6; +constant congr_cl12_wH_offset :natural := congr_cl12_wG_offset + 6; +constant congr_cl13_wA_offset :natural := congr_cl12_wH_offset + 6; +constant congr_cl13_wB_offset :natural := congr_cl13_wA_offset + 6; +constant congr_cl13_wC_offset :natural := congr_cl13_wB_offset + 6; +constant congr_cl13_wD_offset :natural := congr_cl13_wC_offset + 6; +constant congr_cl13_wE_offset :natural := congr_cl13_wD_offset + 6; +constant congr_cl13_wF_offset :natural := congr_cl13_wE_offset + 6; +constant congr_cl13_wG_offset :natural := congr_cl13_wF_offset + 6; +constant congr_cl13_wH_offset :natural := congr_cl13_wG_offset + 6; +constant congr_cl14_wA_offset :natural := congr_cl13_wH_offset + 6; +constant congr_cl14_wB_offset :natural := congr_cl14_wA_offset + 6; +constant congr_cl14_wC_offset :natural := congr_cl14_wB_offset + 6; +constant congr_cl14_wD_offset :natural := congr_cl14_wC_offset + 6; +constant congr_cl14_wE_offset :natural := congr_cl14_wD_offset + 6; +constant congr_cl14_wF_offset :natural := congr_cl14_wE_offset + 6; +constant congr_cl14_wG_offset :natural := congr_cl14_wF_offset + 6; +constant congr_cl14_wH_offset :natural := congr_cl14_wG_offset + 6; +constant congr_cl15_wA_offset :natural := congr_cl14_wH_offset + 6; +constant congr_cl15_wB_offset :natural := congr_cl15_wA_offset + 6; +constant congr_cl15_wC_offset :natural := congr_cl15_wB_offset + 6; +constant congr_cl15_wD_offset :natural := congr_cl15_wC_offset + 6; +constant congr_cl15_wE_offset :natural := congr_cl15_wD_offset + 6; +constant congr_cl15_wF_offset :natural := congr_cl15_wE_offset + 6; +constant congr_cl15_wG_offset :natural := congr_cl15_wF_offset + 6; +constant congr_cl15_wH_offset :natural := congr_cl15_wG_offset + 6; +constant congr_cl16_wA_offset :natural := congr_cl15_wH_offset + 6; +constant congr_cl16_wB_offset :natural := congr_cl16_wA_offset + 6; +constant congr_cl16_wC_offset :natural := congr_cl16_wB_offset + 6; +constant congr_cl16_wD_offset :natural := congr_cl16_wC_offset + 6; +constant congr_cl16_wE_offset :natural := congr_cl16_wD_offset + 6; +constant congr_cl16_wF_offset :natural := congr_cl16_wE_offset + 6; +constant congr_cl16_wG_offset :natural := congr_cl16_wF_offset + 6; +constant congr_cl16_wH_offset :natural := congr_cl16_wG_offset + 6; +constant congr_cl17_wA_offset :natural := congr_cl16_wH_offset + 6; +constant congr_cl17_wB_offset :natural := congr_cl17_wA_offset + 6; +constant congr_cl17_wC_offset :natural := congr_cl17_wB_offset + 6; +constant congr_cl17_wD_offset :natural := congr_cl17_wC_offset + 6; +constant congr_cl17_wE_offset :natural := congr_cl17_wD_offset + 6; +constant congr_cl17_wF_offset :natural := congr_cl17_wE_offset + 6; +constant congr_cl17_wG_offset :natural := congr_cl17_wF_offset + 6; +constant congr_cl17_wH_offset :natural := congr_cl17_wG_offset + 6; +constant congr_cl18_wA_offset :natural := congr_cl17_wH_offset + 6; +constant congr_cl18_wB_offset :natural := congr_cl18_wA_offset + 6; +constant congr_cl18_wC_offset :natural := congr_cl18_wB_offset + 6; +constant congr_cl18_wD_offset :natural := congr_cl18_wC_offset + 6; +constant congr_cl18_wE_offset :natural := congr_cl18_wD_offset + 6; +constant congr_cl18_wF_offset :natural := congr_cl18_wE_offset + 6; +constant congr_cl18_wG_offset :natural := congr_cl18_wF_offset + 6; +constant congr_cl18_wH_offset :natural := congr_cl18_wG_offset + 6; +constant congr_cl19_wA_offset :natural := congr_cl18_wH_offset + 6; +constant congr_cl19_wB_offset :natural := congr_cl19_wA_offset + 6; +constant congr_cl19_wC_offset :natural := congr_cl19_wB_offset + 6; +constant congr_cl19_wD_offset :natural := congr_cl19_wC_offset + 6; +constant congr_cl19_wE_offset :natural := congr_cl19_wD_offset + 6; +constant congr_cl19_wF_offset :natural := congr_cl19_wE_offset + 6; +constant congr_cl19_wG_offset :natural := congr_cl19_wF_offset + 6; +constant congr_cl19_wH_offset :natural := congr_cl19_wG_offset + 6; +constant congr_cl20_wA_offset :natural := congr_cl19_wH_offset + 6; +constant congr_cl20_wB_offset :natural := congr_cl20_wA_offset + 6; +constant congr_cl20_wC_offset :natural := congr_cl20_wB_offset + 6; +constant congr_cl20_wD_offset :natural := congr_cl20_wC_offset + 6; +constant congr_cl20_wE_offset :natural := congr_cl20_wD_offset + 6; +constant congr_cl20_wF_offset :natural := congr_cl20_wE_offset + 6; +constant congr_cl20_wG_offset :natural := congr_cl20_wF_offset + 6; +constant congr_cl20_wH_offset :natural := congr_cl20_wG_offset + 6; +constant congr_cl21_wA_offset :natural := congr_cl20_wH_offset + 6; +constant congr_cl21_wB_offset :natural := congr_cl21_wA_offset + 6; +constant congr_cl21_wC_offset :natural := congr_cl21_wB_offset + 6; +constant congr_cl21_wD_offset :natural := congr_cl21_wC_offset + 6; +constant congr_cl21_wE_offset :natural := congr_cl21_wD_offset + 6; +constant congr_cl21_wF_offset :natural := congr_cl21_wE_offset + 6; +constant congr_cl21_wG_offset :natural := congr_cl21_wF_offset + 6; +constant congr_cl21_wH_offset :natural := congr_cl21_wG_offset + 6; +constant congr_cl22_wA_offset :natural := congr_cl21_wH_offset + 6; +constant congr_cl22_wB_offset :natural := congr_cl22_wA_offset + 6; +constant congr_cl22_wC_offset :natural := congr_cl22_wB_offset + 6; +constant congr_cl22_wD_offset :natural := congr_cl22_wC_offset + 6; +constant congr_cl22_wE_offset :natural := congr_cl22_wD_offset + 6; +constant congr_cl22_wF_offset :natural := congr_cl22_wE_offset + 6; +constant congr_cl22_wG_offset :natural := congr_cl22_wF_offset + 6; +constant congr_cl22_wH_offset :natural := congr_cl22_wG_offset + 6; +constant congr_cl23_wA_offset :natural := congr_cl22_wH_offset + 6; +constant congr_cl23_wB_offset :natural := congr_cl23_wA_offset + 6; +constant congr_cl23_wC_offset :natural := congr_cl23_wB_offset + 6; +constant congr_cl23_wD_offset :natural := congr_cl23_wC_offset + 6; +constant congr_cl23_wE_offset :natural := congr_cl23_wD_offset + 6; +constant congr_cl23_wF_offset :natural := congr_cl23_wE_offset + 6; +constant congr_cl23_wG_offset :natural := congr_cl23_wF_offset + 6; +constant congr_cl23_wH_offset :natural := congr_cl23_wG_offset + 6; +constant congr_cl24_wA_offset :natural := congr_cl23_wH_offset + 6; +constant congr_cl24_wB_offset :natural := congr_cl24_wA_offset + 6; +constant congr_cl24_wC_offset :natural := congr_cl24_wB_offset + 6; +constant congr_cl24_wD_offset :natural := congr_cl24_wC_offset + 6; +constant congr_cl24_wE_offset :natural := congr_cl24_wD_offset + 6; +constant congr_cl24_wF_offset :natural := congr_cl24_wE_offset + 6; +constant congr_cl24_wG_offset :natural := congr_cl24_wF_offset + 6; +constant congr_cl24_wH_offset :natural := congr_cl24_wG_offset + 6; +constant congr_cl25_wA_offset :natural := congr_cl24_wH_offset + 6; +constant congr_cl25_wB_offset :natural := congr_cl25_wA_offset + 6; +constant congr_cl25_wC_offset :natural := congr_cl25_wB_offset + 6; +constant congr_cl25_wD_offset :natural := congr_cl25_wC_offset + 6; +constant congr_cl25_wE_offset :natural := congr_cl25_wD_offset + 6; +constant congr_cl25_wF_offset :natural := congr_cl25_wE_offset + 6; +constant congr_cl25_wG_offset :natural := congr_cl25_wF_offset + 6; +constant congr_cl25_wH_offset :natural := congr_cl25_wG_offset + 6; +constant congr_cl26_wA_offset :natural := congr_cl25_wH_offset + 6; +constant congr_cl26_wB_offset :natural := congr_cl26_wA_offset + 6; +constant congr_cl26_wC_offset :natural := congr_cl26_wB_offset + 6; +constant congr_cl26_wD_offset :natural := congr_cl26_wC_offset + 6; +constant congr_cl26_wE_offset :natural := congr_cl26_wD_offset + 6; +constant congr_cl26_wF_offset :natural := congr_cl26_wE_offset + 6; +constant congr_cl26_wG_offset :natural := congr_cl26_wF_offset + 6; +constant congr_cl26_wH_offset :natural := congr_cl26_wG_offset + 6; +constant congr_cl27_wA_offset :natural := congr_cl26_wH_offset + 6; +constant congr_cl27_wB_offset :natural := congr_cl27_wA_offset + 6; +constant congr_cl27_wC_offset :natural := congr_cl27_wB_offset + 6; +constant congr_cl27_wD_offset :natural := congr_cl27_wC_offset + 6; +constant congr_cl27_wE_offset :natural := congr_cl27_wD_offset + 6; +constant congr_cl27_wF_offset :natural := congr_cl27_wE_offset + 6; +constant congr_cl27_wG_offset :natural := congr_cl27_wF_offset + 6; +constant congr_cl27_wH_offset :natural := congr_cl27_wG_offset + 6; +constant congr_cl28_wA_offset :natural := congr_cl27_wH_offset + 6; +constant congr_cl28_wB_offset :natural := congr_cl28_wA_offset + 6; +constant congr_cl28_wC_offset :natural := congr_cl28_wB_offset + 6; +constant congr_cl28_wD_offset :natural := congr_cl28_wC_offset + 6; +constant congr_cl28_wE_offset :natural := congr_cl28_wD_offset + 6; +constant congr_cl28_wF_offset :natural := congr_cl28_wE_offset + 6; +constant congr_cl28_wG_offset :natural := congr_cl28_wF_offset + 6; +constant congr_cl28_wH_offset :natural := congr_cl28_wG_offset + 6; +constant congr_cl29_wA_offset :natural := congr_cl28_wH_offset + 6; +constant congr_cl29_wB_offset :natural := congr_cl29_wA_offset + 6; +constant congr_cl29_wC_offset :natural := congr_cl29_wB_offset + 6; +constant congr_cl29_wD_offset :natural := congr_cl29_wC_offset + 6; +constant congr_cl29_wE_offset :natural := congr_cl29_wD_offset + 6; +constant congr_cl29_wF_offset :natural := congr_cl29_wE_offset + 6; +constant congr_cl29_wG_offset :natural := congr_cl29_wF_offset + 6; +constant congr_cl29_wH_offset :natural := congr_cl29_wG_offset + 6; +constant congr_cl30_wA_offset :natural := congr_cl29_wH_offset + 6; +constant congr_cl30_wB_offset :natural := congr_cl30_wA_offset + 6; +constant congr_cl30_wC_offset :natural := congr_cl30_wB_offset + 6; +constant congr_cl30_wD_offset :natural := congr_cl30_wC_offset + 6; +constant congr_cl30_wE_offset :natural := congr_cl30_wD_offset + 6; +constant congr_cl30_wF_offset :natural := congr_cl30_wE_offset + 6; +constant congr_cl30_wG_offset :natural := congr_cl30_wF_offset + 6; +constant congr_cl30_wH_offset :natural := congr_cl30_wG_offset + 6; +constant congr_cl31_wA_offset :natural := congr_cl30_wH_offset + 6; +constant congr_cl31_wB_offset :natural := congr_cl31_wA_offset + 6; +constant congr_cl31_wC_offset :natural := congr_cl31_wB_offset + 6; +constant congr_cl31_wD_offset :natural := congr_cl31_wC_offset + 6; +constant congr_cl31_wE_offset :natural := congr_cl31_wD_offset + 6; +constant congr_cl31_wF_offset :natural := congr_cl31_wE_offset + 6; +constant congr_cl31_wG_offset :natural := congr_cl31_wF_offset + 6; +constant congr_cl31_wH_offset :natural := congr_cl31_wG_offset + 6; +constant flush_wayA_data_offset :natural := congr_cl31_wH_offset + 6; +constant flush_wayB_data_offset :natural := flush_wayA_data_offset + 6; +constant flush_wayC_data_offset :natural := flush_wayB_data_offset + 6; +constant flush_wayD_data_offset :natural := flush_wayC_data_offset + 6; +constant flush_wayE_data_offset :natural := flush_wayD_data_offset + 6; +constant flush_wayF_data_offset :natural := flush_wayE_data_offset + 6; +constant flush_wayG_data_offset :natural := flush_wayF_data_offset + 6; +constant flush_wayH_data_offset :natural := flush_wayG_data_offset + 6; +constant ex3_flush_cline_offset :natural := flush_wayH_data_offset + 6; +constant ex5_congr_cl_offset :natural := ex3_flush_cline_offset + 1; +constant ex7_congr_cl_offset :natural := ex5_congr_cl_offset + 5; +constant ex8_congr_cl_offset :natural := ex7_congr_cl_offset + 5; +constant ex9_congr_cl_offset :natural := ex8_congr_cl_offset + 5; +constant wayA_val_b_offset :natural := ex9_congr_cl_offset + 5; +constant wayB_val_b_offset :natural := wayA_val_b_offset + 6; +constant wayC_val_b_offset :natural := wayB_val_b_offset + 6; +constant wayD_val_b_offset :natural := wayC_val_b_offset + 6; +constant wayE_val_b_offset :natural := wayD_val_b_offset + 6; +constant wayF_val_b_offset :natural := wayE_val_b_offset + 6; +constant wayG_val_b_offset :natural := wayF_val_b_offset + 6; +constant wayH_val_b_offset :natural := wayG_val_b_offset + 6; +constant ex3_wayA_fxubyp_val_offset :natural := wayH_val_b_offset + 6; +constant ex3_wayB_fxubyp_val_offset :natural := ex3_wayA_fxubyp_val_offset + 1; +constant ex3_wayC_fxubyp_val_offset :natural := ex3_wayB_fxubyp_val_offset + 1; +constant ex3_wayD_fxubyp_val_offset :natural := ex3_wayC_fxubyp_val_offset + 1; +constant ex3_wayE_fxubyp_val_offset :natural := ex3_wayD_fxubyp_val_offset + 1; +constant ex3_wayF_fxubyp_val_offset :natural := ex3_wayE_fxubyp_val_offset + 1; +constant ex3_wayG_fxubyp_val_offset :natural := ex3_wayF_fxubyp_val_offset + 1; +constant ex3_wayH_fxubyp_val_offset :natural := ex3_wayG_fxubyp_val_offset + 1; +constant ex3_wayA_relbyp_val_offset :natural := ex3_wayH_fxubyp_val_offset + 1; +constant ex3_wayB_relbyp_val_offset :natural := ex3_wayA_relbyp_val_offset + 1; +constant ex3_wayC_relbyp_val_offset :natural := ex3_wayB_relbyp_val_offset + 1; +constant ex3_wayD_relbyp_val_offset :natural := ex3_wayC_relbyp_val_offset + 1; +constant ex3_wayE_relbyp_val_offset :natural := ex3_wayD_relbyp_val_offset + 1; +constant ex3_wayF_relbyp_val_offset :natural := ex3_wayE_relbyp_val_offset + 1; +constant ex3_wayG_relbyp_val_offset :natural := ex3_wayF_relbyp_val_offset + 1; +constant ex3_wayH_relbyp_val_offset :natural := ex3_wayG_relbyp_val_offset + 1; +constant ex4_xuop_wayA_upd_offset :natural := ex3_wayH_relbyp_val_offset + 1; +constant ex4_xuop_wayB_upd_offset :natural := ex4_xuop_wayA_upd_offset + 1; +constant ex4_xuop_wayC_upd_offset :natural := ex4_xuop_wayB_upd_offset + 1; +constant ex4_xuop_wayD_upd_offset :natural := ex4_xuop_wayC_upd_offset + 1; +constant ex4_xuop_wayE_upd_offset :natural := ex4_xuop_wayD_upd_offset + 1; +constant ex4_xuop_wayF_upd_offset :natural := ex4_xuop_wayE_upd_offset + 1; +constant ex4_xuop_wayG_upd_offset :natural := ex4_xuop_wayF_upd_offset + 1; +constant ex4_xuop_wayH_upd_offset :natural := ex4_xuop_wayG_upd_offset + 1; +constant ex5_xuop_wayA_upd_offset :natural := ex4_xuop_wayH_upd_offset + 1; +constant ex5_xuop_wayB_upd_offset :natural := ex5_xuop_wayA_upd_offset + 1; +constant ex5_xuop_wayC_upd_offset :natural := ex5_xuop_wayB_upd_offset + 1; +constant ex5_xuop_wayD_upd_offset :natural := ex5_xuop_wayC_upd_offset + 1; +constant ex5_xuop_wayE_upd_offset :natural := ex5_xuop_wayD_upd_offset + 1; +constant ex5_xuop_wayF_upd_offset :natural := ex5_xuop_wayE_upd_offset + 1; +constant ex5_xuop_wayG_upd_offset :natural := ex5_xuop_wayF_upd_offset + 1; +constant ex5_xuop_wayH_upd_offset :natural := ex5_xuop_wayG_upd_offset + 1; +constant inval_clr_lck_wA_offset :natural := ex5_xuop_wayH_upd_offset + 1; +constant inval_clr_lck_wB_offset :natural := inval_clr_lck_wA_offset + 1; +constant inval_clr_lck_wC_offset :natural := inval_clr_lck_wB_offset + 1; +constant inval_clr_lck_wD_offset :natural := inval_clr_lck_wC_offset + 1; +constant inval_clr_lck_wE_offset :natural := inval_clr_lck_wD_offset + 1; +constant inval_clr_lck_wF_offset :natural := inval_clr_lck_wE_offset + 1; +constant inval_clr_lck_wG_offset :natural := inval_clr_lck_wF_offset + 1; +constant inval_clr_lck_wH_offset :natural := inval_clr_lck_wG_offset + 1; +constant congr_cl_m_upd_wayA_offset :natural := inval_clr_lck_wH_offset + 1; +constant congr_cl_m_upd_wayB_offset :natural := congr_cl_m_upd_wayA_offset + 1; +constant congr_cl_m_upd_wayC_offset :natural := congr_cl_m_upd_wayB_offset + 1; +constant congr_cl_m_upd_wayD_offset :natural := congr_cl_m_upd_wayC_offset + 1; +constant congr_cl_m_upd_wayE_offset :natural := congr_cl_m_upd_wayD_offset + 1; +constant congr_cl_m_upd_wayF_offset :natural := congr_cl_m_upd_wayE_offset + 1; +constant congr_cl_m_upd_wayG_offset :natural := congr_cl_m_upd_wayF_offset + 1; +constant congr_cl_m_upd_wayH_offset :natural := congr_cl_m_upd_wayG_offset + 1; +constant ex3_congr_cl_offset :natural := congr_cl_m_upd_wayH_offset + 1; +constant rel24_congr_cl_offset :natural := ex3_congr_cl_offset + 5; +constant relu_s_congr_cl_offset :natural := rel24_congr_cl_offset + 5; +constant reload_way_clr_offset :natural := relu_s_congr_cl_offset + 5; +constant ex4_watchSet_coll_offset :natural := reload_way_clr_offset + 8; +constant rel_wayA_val_b_offset :natural := ex4_watchSet_coll_offset + 1; +constant rel_wayB_val_b_offset :natural := rel_wayA_val_b_offset + 6; +constant rel_wayC_val_b_offset :natural := rel_wayB_val_b_offset + 6; +constant rel_wayD_val_b_offset :natural := rel_wayC_val_b_offset + 6; +constant rel_wayE_val_b_offset :natural := rel_wayD_val_b_offset + 6; +constant rel_wayF_val_b_offset :natural := rel_wayE_val_b_offset + 6; +constant rel_wayG_val_b_offset :natural := rel_wayF_val_b_offset + 6; +constant rel_wayH_val_b_offset :natural := rel_wayG_val_b_offset + 6; +constant rel_val_stg2_offset :natural := rel_wayH_val_b_offset + 6; +constant rel_val_clr_offset :natural := rel_val_stg2_offset + 1; +constant rel_port_upd_offset :natural := rel_val_clr_offset + 1; +constant rel_val_stg4_offset :natural := rel_port_upd_offset + 1; +constant rel_binv_stg4_offset :natural := rel_val_stg4_offset + 1; +constant back_inval_stg3_offset :natural := rel_binv_stg4_offset + 1; +constant back_inval_stg4_offset :natural := back_inval_stg3_offset + 1; +constant back_inval_stg5_offset :natural := back_inval_stg4_offset + 1; +constant binv4_ex4_xuop_upd_offset :natural := back_inval_stg5_offset + 1; +constant binv4_ex4_dir_val_offset :natural := binv4_ex4_xuop_upd_offset + 1; +constant ex4_dir_err_val_offset :natural := binv4_ex4_dir_val_offset + 1; +constant ex5_dir_err_val_offset :natural := ex4_dir_err_val_offset + 1; +constant ex6_dir_err_val_offset :natural := ex5_dir_err_val_offset + 1; +constant derr2_stg_act_offset :natural := ex6_dir_err_val_offset + 1; +constant derr3_stg_act_offset :natural := derr2_stg_act_offset + 1; +constant derr4_stg_act_offset :natural := derr3_stg_act_offset + 1; +constant derr5_stg_act_offset :natural := derr4_stg_act_offset + 1; +constant ex4_dir_multihit_val_b_offset :natural := derr5_stg_act_offset + 1; +constant ex4_n_lsu_ddmh_flush_b_offset :natural := ex4_dir_multihit_val_b_offset + 1; +constant dcarr_up_way_addr_offset :natural := ex4_n_lsu_ddmh_flush_b_offset + 4; +constant reload_wayA_data_offset :natural := dcarr_up_way_addr_offset + 3; +constant reload_wayB_data_offset :natural := reload_wayA_data_offset + 6; +constant reload_wayC_data_offset :natural := reload_wayB_data_offset + 6; +constant reload_wayD_data_offset :natural := reload_wayC_data_offset + 6; +constant reload_wayE_data_offset :natural := reload_wayD_data_offset + 6; +constant reload_wayF_data_offset :natural := reload_wayE_data_offset + 6; +constant reload_wayG_data_offset :natural := reload_wayF_data_offset + 6; +constant reload_wayH_data_offset :natural := reload_wayG_data_offset + 6; +constant binv_wayA_upd_offset :natural := reload_wayH_data_offset + 6; +constant binv_wayB_upd_offset :natural := binv_wayA_upd_offset + 1; +constant binv_wayC_upd_offset :natural := binv_wayB_upd_offset + 1; +constant binv_wayD_upd_offset :natural := binv_wayC_upd_offset + 1; +constant binv_wayE_upd_offset :natural := binv_wayD_upd_offset + 1; +constant binv_wayF_upd_offset :natural := binv_wayE_upd_offset + 1; +constant binv_wayG_upd_offset :natural := binv_wayF_upd_offset + 1; +constant binv_wayH_upd_offset :natural := binv_wayG_upd_offset + 1; +constant binv_wayA_upd2_offset :natural := binv_wayH_upd_offset + 1; +constant binv_wayB_upd2_offset :natural := binv_wayA_upd2_offset + 1; +constant binv_wayC_upd2_offset :natural := binv_wayB_upd2_offset + 1; +constant binv_wayD_upd2_offset :natural := binv_wayC_upd2_offset + 1; +constant binv_wayE_upd2_offset :natural := binv_wayD_upd2_offset + 1; +constant binv_wayF_upd2_offset :natural := binv_wayE_upd2_offset + 1; +constant binv_wayG_upd2_offset :natural := binv_wayF_upd2_offset + 1; +constant binv_wayH_upd2_offset :natural := binv_wayG_upd2_offset + 1; +constant binv_wayA_upd3_offset :natural := binv_wayH_upd2_offset + 1; +constant binv_wayB_upd3_offset :natural := binv_wayA_upd3_offset + 1; +constant binv_wayC_upd3_offset :natural := binv_wayB_upd3_offset + 1; +constant binv_wayD_upd3_offset :natural := binv_wayC_upd3_offset + 1; +constant binv_wayE_upd3_offset :natural := binv_wayD_upd3_offset + 1; +constant binv_wayF_upd3_offset :natural := binv_wayE_upd3_offset + 1; +constant binv_wayG_upd3_offset :natural := binv_wayF_upd3_offset + 1; +constant binv_wayH_upd3_offset :natural := binv_wayG_upd3_offset + 1; +constant reload_wayA_upd_offset :natural := binv_wayH_upd3_offset + 1; +constant reload_wayB_upd_offset :natural := reload_wayA_upd_offset + 1; +constant reload_wayC_upd_offset :natural := reload_wayB_upd_offset + 1; +constant reload_wayD_upd_offset :natural := reload_wayC_upd_offset + 1; +constant reload_wayE_upd_offset :natural := reload_wayD_upd_offset + 1; +constant reload_wayF_upd_offset :natural := reload_wayE_upd_offset + 1; +constant reload_wayG_upd_offset :natural := reload_wayF_upd_offset + 1; +constant reload_wayH_upd_offset :natural := reload_wayG_upd_offset + 1; +constant reload_wayA_upd2_offset :natural := reload_wayH_upd_offset + 1; +constant reload_wayB_upd2_offset :natural := reload_wayA_upd2_offset + 1; +constant reload_wayC_upd2_offset :natural := reload_wayB_upd2_offset + 1; +constant reload_wayD_upd2_offset :natural := reload_wayC_upd2_offset + 1; +constant reload_wayE_upd2_offset :natural := reload_wayD_upd2_offset + 1; +constant reload_wayF_upd2_offset :natural := reload_wayE_upd2_offset + 1; +constant reload_wayG_upd2_offset :natural := reload_wayF_upd2_offset + 1; +constant reload_wayH_upd2_offset :natural := reload_wayG_upd2_offset + 1; +constant reload_wayA_upd3_offset :natural := reload_wayH_upd2_offset + 1; +constant reload_wayB_upd3_offset :natural := reload_wayA_upd3_offset + 1; +constant reload_wayC_upd3_offset :natural := reload_wayB_upd3_offset + 1; +constant reload_wayD_upd3_offset :natural := reload_wayC_upd3_offset + 1; +constant reload_wayE_upd3_offset :natural := reload_wayD_upd3_offset + 1; +constant reload_wayF_upd3_offset :natural := reload_wayE_upd3_offset + 1; +constant reload_wayG_upd3_offset :natural := reload_wayF_upd3_offset + 1; +constant reload_wayH_upd3_offset :natural := reload_wayG_upd3_offset + 1; +constant ex3_store_instr_offset :natural := reload_wayH_upd3_offset + 1; +constant ex3_lock_set_offset :natural := ex3_store_instr_offset + 1; +constant ex4_lock_set_offset :natural := ex3_lock_set_offset + 1; +constant ex5_lock_set_offset :natural := ex4_lock_set_offset + 1; +constant ex3_lock_clr_offset :natural := ex5_lock_set_offset + 1; +constant ex3_xuop_val_offset :natural := ex3_lock_clr_offset + 1; +constant ex4_xuop_val_offset :natural := ex3_xuop_val_offset + 1; +constant ex5_xuop_val_offset :natural := ex4_xuop_val_offset + 1; +constant rel_lock_set_offset :natural := ex5_xuop_val_offset + 1; +constant dcpar_err_stg1_offset :natural := rel_lock_set_offset + 1; +constant dcpar_err_stg2_offset :natural := dcpar_err_stg1_offset + 1; +constant dcpar_err_way_offset :natural := dcpar_err_stg2_offset + 1; +constant dcpar_err_way_inval_offset :natural := dcpar_err_way_offset + 8; +constant dcpar_err_cntr_offset :natural := dcpar_err_way_inval_offset + 8; +constant dcpar_err_ind_sel_offset :natural := dcpar_err_cntr_offset + 2; +constant dcpar_err_push_queue_offset :natural := dcpar_err_ind_sel_offset + 2; +constant ex5_way_hit_offset :natural := dcpar_err_push_queue_offset + 1; +constant ex7_way_hit_offset :natural := ex5_way_hit_offset + 8; +constant ex8_way_hit_offset :natural := ex7_way_hit_offset + 8; +constant ex9_way_hit_offset :natural := ex8_way_hit_offset + 8; +constant ex4_lose_watch_offset :natural := ex9_way_hit_offset + 8; +constant xucr0_cslc_xuop_offset :natural := ex4_lose_watch_offset + 4; +constant xucr0_cslc_binv_offset :natural := xucr0_cslc_xuop_offset + 1; +constant dci_compl_offset :natural := xucr0_cslc_binv_offset + 1; +constant dci_inval_all_offset :natural := dci_compl_offset + 1; +constant inv2_val_offset :natural := dci_inval_all_offset + 1; +constant perf_lsu_evnts_offset :natural := inv2_val_offset + 1; +constant lock_flash_clear_offset :natural := perf_lsu_evnts_offset + 5; +constant lock_flash_clear_val_offset :natural := lock_flash_clear_offset + 1; +constant rel_port_wren_offset :natural := lock_flash_clear_val_offset + 1; +constant ex3_thrd_id_offset :natural := rel_port_wren_offset + 1; +constant ex5_thrd_id_offset :natural := ex3_thrd_id_offset + 4; +constant ex3_l_fld_b1_offset :natural := ex5_thrd_id_offset + 4; +constant ex3_watch_set_offset :natural := ex3_l_fld_b1_offset + 1; +constant ex4_watch_set_offset :natural := ex3_watch_set_offset + 1; +constant ex5_watch_set_offset :natural := ex4_watch_set_offset + 1; +constant ex3_watch_clr_offset :natural := ex5_watch_set_offset + 1; +constant ex3_watch_clr_all_offset :natural := ex3_watch_clr_offset + 1; +constant ex3_watch_chk_offset :natural := ex3_watch_clr_all_offset + 1; +constant ex4_watch_chk_offset :natural := ex3_watch_chk_offset + 1; +constant ex5_watch_chk_offset :natural := ex4_watch_chk_offset + 1; +constant ex3_wclr_all_upd_offset :natural := ex5_watch_chk_offset + 1; +constant ex4_wclr_all_val_offset :natural := ex3_wclr_all_upd_offset + 1; +constant ex5_wclr_all_val_offset :natural := ex4_wclr_all_val_offset + 1; +constant ex6_wclr_all_val_offset :natural := ex5_wclr_all_val_offset + 1; +constant rel_thrd_id_offset :natural := ex6_wclr_all_val_offset + 1; +constant rel_watch_set_offset :natural := rel_thrd_id_offset + 4; +constant ex5_cr_watch_offset :natural := rel_watch_set_offset + 1; +constant ex4_watch_clr_all_offset :natural := ex5_cr_watch_offset + 1; +constant ex5_watch_clr_all_offset :natural := ex4_watch_clr_all_offset + 4; +constant ex6_watch_clr_all_offset :natural := ex5_watch_clr_all_offset + 4; +constant ex5_watch_clr_all_val_offset :natural := ex6_watch_clr_all_offset + 4; +constant ex5_lost_watch_upd_offset :natural := ex5_watch_clr_all_val_offset + 1; +constant ex4_watchlost_set_offset :natural := ex5_lost_watch_upd_offset + 4; +constant ex5_watchlost_set_offset :natural := ex4_watchlost_set_offset + 4; +constant rel_lost_watch_binv_offset :natural := ex5_watchlost_set_offset + 4; +constant lost_watch_evict_ovl_offset :natural := rel_lost_watch_binv_offset + 4; +constant rel_lost_watch_upd_offset :natural := lost_watch_evict_ovl_offset + 4; +constant lost_watch_evict_val_offset :natural := rel_lost_watch_upd_offset + 4; +constant lost_watch_inter_thrd_offset :natural := lost_watch_evict_val_offset + 4; +constant stm_watchlost_state_offset :natural := lost_watch_inter_thrd_offset + 4; +constant ex5_xuop_p0_upd_offset :natural := stm_watchlost_state_offset + 4; +constant rel_val_stgu_offset :natural := ex5_xuop_p0_upd_offset + 1; +constant p0_wren_offset :natural := rel_val_stgu_offset + 1; +constant p0_wren_cpy_offset :natural := p0_wren_offset + 1; +constant p0_wren_stg_offset :natural := p0_wren_cpy_offset + 1; +constant p1_wren_offset :natural := p0_wren_stg_offset + 1; +constant p1_wren_cpy_offset :natural := p1_wren_offset + 1; +constant ex3_thrd_m_offset :natural := p1_wren_cpy_offset + 1; +constant ex4_thrd_m_offset :natural := ex3_thrd_m_offset + 1; +constant ex5_thrd_m_offset :natural := ex4_thrd_m_offset + 1; +constant ex6_thrd_m_offset :natural := ex5_thrd_m_offset + 1; +constant ex7_ld_par_err_offset :natural := ex6_thrd_m_offset + 1; +constant ex8_ld_par_err_offset :natural := ex7_ld_par_err_offset + 1; +constant ex9_ld_par_err_offset :natural := ex8_ld_par_err_offset + 1; +constant ex6_ld_valid_offset :natural := ex9_ld_par_err_offset + 1; +constant ex7_ld_valid_offset :natural := ex6_ld_valid_offset + 1; +constant ex8_ld_valid_offset :natural := ex7_ld_valid_offset + 1; +constant ex9_ld_valid_offset :natural := ex8_ld_valid_offset + 1; +constant rel_in_progress_offset :natural := ex9_ld_valid_offset + 1; +constant inj_dir_multihit_offset :natural := rel_in_progress_offset + 1; +constant congr_cl_ex2_ex3_cmp_offset :natural := inj_dir_multihit_offset + 1; +constant congr_cl_ex2_ex4_cmp_offset :natural := congr_cl_ex2_ex3_cmp_offset + 1; +constant congr_cl_ex2_ex5_cmp_offset :natural := congr_cl_ex2_ex4_cmp_offset + 1; +constant congr_cl_ex2_ex6_cmp_offset :natural := congr_cl_ex2_ex5_cmp_offset + 1; +constant congr_cl_ex3_ex4_cmp_offset :natural := congr_cl_ex2_ex6_cmp_offset + 1; +constant congr_cl_ex3_ex5_cmp_offset :natural := congr_cl_ex3_ex4_cmp_offset + 1; +constant congr_cl_ex3_ex6_cmp_offset :natural := congr_cl_ex3_ex5_cmp_offset + 1; +constant congr_cl_ex4_ex5_cmp_offset :natural := congr_cl_ex3_ex6_cmp_offset + 1; +constant congr_cl_ex4_ex6_cmp_offset :natural := congr_cl_ex4_ex5_cmp_offset + 1; +constant congr_cl_ex4_ex7_cmp_offset :natural := congr_cl_ex4_ex6_cmp_offset + 1; +constant congr_cl_ex2_relu_cmp_offset :natural := congr_cl_ex4_ex7_cmp_offset + 1; +constant congr_cl_ex2_relu_s_cmp_offset :natural := congr_cl_ex2_relu_cmp_offset + 1; +constant congr_cl_ex2_rel_upd_cmp_offset :natural := congr_cl_ex2_relu_s_cmp_offset + 1; +constant congr_cl_rel13_ex3_cmp_offset :natural := congr_cl_ex2_rel_upd_cmp_offset + 1; +constant congr_cl_rel13_ex4_cmp_offset :natural := congr_cl_rel13_ex3_cmp_offset + 1; +constant congr_cl_rel13_ex5_cmp_offset :natural := congr_cl_rel13_ex4_cmp_offset + 1; +constant congr_cl_rel13_ex6_cmp_offset :natural := congr_cl_rel13_ex5_cmp_offset + 1; +constant congr_cl_rel13_relu_cmp_offset :natural := congr_cl_rel13_ex6_cmp_offset + 1; +constant congr_cl_rel13_relu_s_cmp_offset :natural := congr_cl_rel13_relu_cmp_offset + 1; +constant congr_cl_rel13_rel_upd_cmp_offset :natural := congr_cl_rel13_relu_s_cmp_offset + 1; +constant rel24_congr_cl_ex4_cmp_offset :natural := congr_cl_rel13_rel_upd_cmp_offset + 1; +constant rel24_congr_cl_ex5_cmp_offset :natural := rel24_congr_cl_ex4_cmp_offset + 1; +constant rel24_congr_cl_ex6_cmp_offset :natural := rel24_congr_cl_ex5_cmp_offset + 1; +constant relu_congr_cl_ex5_cmp_offset :natural := rel24_congr_cl_ex6_cmp_offset + 1; +constant relu_congr_cl_ex6_cmp_offset :natural := relu_congr_cl_ex5_cmp_offset + 1; +constant relu_congr_cl_ex7_cmp_offset :natural := relu_congr_cl_ex6_cmp_offset + 1; +constant ex4_err_det_way_offset :natural := relu_congr_cl_ex7_cmp_offset + 1; +constant ex4_perr_lck_lost_offset :natural := ex4_err_det_way_offset + 8; +constant ex4_perr_watch_lost_offset :natural := ex4_perr_lck_lost_offset + 1; +constant dcperr_lock_lost_offset :natural := ex4_perr_watch_lost_offset + 4; +constant binv7_ex7_way_upd_offset :natural := dcperr_lock_lost_offset + 1; +constant binv5_ex5_dir_data_offset :natural := binv7_ex7_way_upd_offset + 8; +constant binv7_ex7_dir_data_offset :natural := binv5_ex5_dir_data_offset + 5; +constant binv5_inval_watch_val_offset :natural := binv7_ex7_dir_data_offset + 5; +constant binv5_inval_lock_val_offset :natural := binv5_inval_watch_val_offset + 4; +constant ex4_snd_ld_l2_offset :natural := binv5_inval_lock_val_offset + 1; +constant ex4_ldq_full_flush_b_offset :natural := ex4_snd_ld_l2_offset + 1; +constant ex4_miss_offset :natural := ex4_ldq_full_flush_b_offset + 1; +constant my_spare0_latches_offset :natural := ex4_miss_offset + 1; +constant my_spare1_latches_offset :natural := my_spare0_latches_offset + 17; +constant rel_l1dump_cslc_offset :natural := my_spare1_latches_offset + 16; +constant rel_in_prog_stg1_offset :natural := rel_l1dump_cslc_offset + 1; +constant rel_in_prog_stg2_offset :natural := rel_in_prog_stg1_offset + 1; +constant rel_in_prog_stg3_offset :natural := rel_in_prog_stg2_offset + 1; +constant rel_in_prog_stg4_offset :natural := rel_in_prog_stg3_offset + 1; +constant rel_in_prog_stg5_offset :natural := rel_in_prog_stg4_offset + 1; +constant dcpar_err_stg1_act_offset :natural := rel_in_prog_stg5_offset + 1; +constant dcpar_err_stg2_act_offset :natural := dcpar_err_stg1_act_offset + 1; +constant rel3_perr_stg_act_offset :natural := dcpar_err_stg2_act_offset + 1; +constant rel4_perr_stg_act_offset :natural := rel3_perr_stg_act_offset + 1; +constant scan_right :natural := rel4_perr_stg_act_offset + 1 - 1; +signal p0_congr_cl0_m :std_ulogic; +signal p1_congr_cl0_m :std_ulogic; +signal p0_congr_cl0_act_d :std_ulogic; +signal p0_congr_cl0_act_q :std_ulogic; +signal p1_congr_cl0_act_d :std_ulogic; +signal p1_congr_cl0_act_q :std_ulogic; +signal congr_cl0_act :std_ulogic; +signal congr_cl0_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl0_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu0_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd0_wayA :std_ulogic; +signal p1_way_data_upd0_wayA :std_ulogic; +signal congr_cl0_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl0_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu0_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd0_wayB :std_ulogic; +signal p1_way_data_upd0_wayB :std_ulogic; +signal congr_cl0_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl0_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu0_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd0_wayC :std_ulogic; +signal p1_way_data_upd0_wayC :std_ulogic; +signal congr_cl0_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl0_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu0_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd0_wayD :std_ulogic; +signal p1_way_data_upd0_wayD :std_ulogic; +signal congr_cl0_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl0_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu0_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd0_wayE :std_ulogic; +signal p1_way_data_upd0_wayE :std_ulogic; +signal congr_cl0_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl0_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu0_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd0_wayF :std_ulogic; +signal p1_way_data_upd0_wayF :std_ulogic; +signal congr_cl0_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl0_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu0_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd0_wayG :std_ulogic; +signal p1_way_data_upd0_wayG :std_ulogic; +signal congr_cl0_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl0_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu0_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd0_wayH :std_ulogic; +signal p1_way_data_upd0_wayH :std_ulogic; +signal p0_congr_cl1_m :std_ulogic; +signal p1_congr_cl1_m :std_ulogic; +signal p0_congr_cl1_act_d :std_ulogic; +signal p0_congr_cl1_act_q :std_ulogic; +signal p1_congr_cl1_act_d :std_ulogic; +signal p1_congr_cl1_act_q :std_ulogic; +signal congr_cl1_act :std_ulogic; +signal congr_cl1_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl1_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu1_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd1_wayA :std_ulogic; +signal p1_way_data_upd1_wayA :std_ulogic; +signal congr_cl1_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl1_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu1_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd1_wayB :std_ulogic; +signal p1_way_data_upd1_wayB :std_ulogic; +signal congr_cl1_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl1_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu1_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd1_wayC :std_ulogic; +signal p1_way_data_upd1_wayC :std_ulogic; +signal congr_cl1_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl1_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu1_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd1_wayD :std_ulogic; +signal p1_way_data_upd1_wayD :std_ulogic; +signal congr_cl1_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl1_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu1_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd1_wayE :std_ulogic; +signal p1_way_data_upd1_wayE :std_ulogic; +signal congr_cl1_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl1_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu1_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd1_wayF :std_ulogic; +signal p1_way_data_upd1_wayF :std_ulogic; +signal congr_cl1_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl1_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu1_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd1_wayG :std_ulogic; +signal p1_way_data_upd1_wayG :std_ulogic; +signal congr_cl1_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl1_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu1_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd1_wayH :std_ulogic; +signal p1_way_data_upd1_wayH :std_ulogic; +signal p0_congr_cl2_m :std_ulogic; +signal p1_congr_cl2_m :std_ulogic; +signal p0_congr_cl2_act_d :std_ulogic; +signal p0_congr_cl2_act_q :std_ulogic; +signal p1_congr_cl2_act_d :std_ulogic; +signal p1_congr_cl2_act_q :std_ulogic; +signal congr_cl2_act :std_ulogic; +signal congr_cl2_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl2_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu2_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd2_wayA :std_ulogic; +signal p1_way_data_upd2_wayA :std_ulogic; +signal congr_cl2_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl2_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu2_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd2_wayB :std_ulogic; +signal p1_way_data_upd2_wayB :std_ulogic; +signal congr_cl2_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl2_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu2_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd2_wayC :std_ulogic; +signal p1_way_data_upd2_wayC :std_ulogic; +signal congr_cl2_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl2_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu2_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd2_wayD :std_ulogic; +signal p1_way_data_upd2_wayD :std_ulogic; +signal congr_cl2_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl2_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu2_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd2_wayE :std_ulogic; +signal p1_way_data_upd2_wayE :std_ulogic; +signal congr_cl2_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl2_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu2_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd2_wayF :std_ulogic; +signal p1_way_data_upd2_wayF :std_ulogic; +signal congr_cl2_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl2_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu2_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd2_wayG :std_ulogic; +signal p1_way_data_upd2_wayG :std_ulogic; +signal congr_cl2_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl2_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu2_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd2_wayH :std_ulogic; +signal p1_way_data_upd2_wayH :std_ulogic; +signal p0_congr_cl3_m :std_ulogic; +signal p1_congr_cl3_m :std_ulogic; +signal p0_congr_cl3_act_d :std_ulogic; +signal p0_congr_cl3_act_q :std_ulogic; +signal p1_congr_cl3_act_d :std_ulogic; +signal p1_congr_cl3_act_q :std_ulogic; +signal congr_cl3_act :std_ulogic; +signal congr_cl3_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl3_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu3_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd3_wayA :std_ulogic; +signal p1_way_data_upd3_wayA :std_ulogic; +signal congr_cl3_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl3_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu3_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd3_wayB :std_ulogic; +signal p1_way_data_upd3_wayB :std_ulogic; +signal congr_cl3_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl3_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu3_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd3_wayC :std_ulogic; +signal p1_way_data_upd3_wayC :std_ulogic; +signal congr_cl3_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl3_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu3_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd3_wayD :std_ulogic; +signal p1_way_data_upd3_wayD :std_ulogic; +signal congr_cl3_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl3_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu3_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd3_wayE :std_ulogic; +signal p1_way_data_upd3_wayE :std_ulogic; +signal congr_cl3_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl3_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu3_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd3_wayF :std_ulogic; +signal p1_way_data_upd3_wayF :std_ulogic; +signal congr_cl3_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl3_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu3_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd3_wayG :std_ulogic; +signal p1_way_data_upd3_wayG :std_ulogic; +signal congr_cl3_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl3_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu3_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd3_wayH :std_ulogic; +signal p1_way_data_upd3_wayH :std_ulogic; +signal p0_congr_cl4_m :std_ulogic; +signal p1_congr_cl4_m :std_ulogic; +signal p0_congr_cl4_act_d :std_ulogic; +signal p0_congr_cl4_act_q :std_ulogic; +signal p1_congr_cl4_act_d :std_ulogic; +signal p1_congr_cl4_act_q :std_ulogic; +signal congr_cl4_act :std_ulogic; +signal congr_cl4_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl4_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu4_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd4_wayA :std_ulogic; +signal p1_way_data_upd4_wayA :std_ulogic; +signal congr_cl4_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl4_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu4_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd4_wayB :std_ulogic; +signal p1_way_data_upd4_wayB :std_ulogic; +signal congr_cl4_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl4_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu4_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd4_wayC :std_ulogic; +signal p1_way_data_upd4_wayC :std_ulogic; +signal congr_cl4_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl4_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu4_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd4_wayD :std_ulogic; +signal p1_way_data_upd4_wayD :std_ulogic; +signal congr_cl4_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl4_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu4_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd4_wayE :std_ulogic; +signal p1_way_data_upd4_wayE :std_ulogic; +signal congr_cl4_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl4_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu4_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd4_wayF :std_ulogic; +signal p1_way_data_upd4_wayF :std_ulogic; +signal congr_cl4_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl4_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu4_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd4_wayG :std_ulogic; +signal p1_way_data_upd4_wayG :std_ulogic; +signal congr_cl4_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl4_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu4_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd4_wayH :std_ulogic; +signal p1_way_data_upd4_wayH :std_ulogic; +signal p0_congr_cl5_m :std_ulogic; +signal p1_congr_cl5_m :std_ulogic; +signal p0_congr_cl5_act_d :std_ulogic; +signal p0_congr_cl5_act_q :std_ulogic; +signal p1_congr_cl5_act_d :std_ulogic; +signal p1_congr_cl5_act_q :std_ulogic; +signal congr_cl5_act :std_ulogic; +signal congr_cl5_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl5_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu5_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd5_wayA :std_ulogic; +signal p1_way_data_upd5_wayA :std_ulogic; +signal congr_cl5_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl5_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu5_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd5_wayB :std_ulogic; +signal p1_way_data_upd5_wayB :std_ulogic; +signal congr_cl5_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl5_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu5_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd5_wayC :std_ulogic; +signal p1_way_data_upd5_wayC :std_ulogic; +signal congr_cl5_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl5_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu5_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd5_wayD :std_ulogic; +signal p1_way_data_upd5_wayD :std_ulogic; +signal congr_cl5_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl5_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu5_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd5_wayE :std_ulogic; +signal p1_way_data_upd5_wayE :std_ulogic; +signal congr_cl5_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl5_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu5_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd5_wayF :std_ulogic; +signal p1_way_data_upd5_wayF :std_ulogic; +signal congr_cl5_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl5_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu5_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd5_wayG :std_ulogic; +signal p1_way_data_upd5_wayG :std_ulogic; +signal congr_cl5_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl5_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu5_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd5_wayH :std_ulogic; +signal p1_way_data_upd5_wayH :std_ulogic; +signal p0_congr_cl6_m :std_ulogic; +signal p1_congr_cl6_m :std_ulogic; +signal p0_congr_cl6_act_d :std_ulogic; +signal p0_congr_cl6_act_q :std_ulogic; +signal p1_congr_cl6_act_d :std_ulogic; +signal p1_congr_cl6_act_q :std_ulogic; +signal congr_cl6_act :std_ulogic; +signal congr_cl6_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl6_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu6_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd6_wayA :std_ulogic; +signal p1_way_data_upd6_wayA :std_ulogic; +signal congr_cl6_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl6_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu6_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd6_wayB :std_ulogic; +signal p1_way_data_upd6_wayB :std_ulogic; +signal congr_cl6_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl6_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu6_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd6_wayC :std_ulogic; +signal p1_way_data_upd6_wayC :std_ulogic; +signal congr_cl6_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl6_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu6_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd6_wayD :std_ulogic; +signal p1_way_data_upd6_wayD :std_ulogic; +signal congr_cl6_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl6_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu6_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd6_wayE :std_ulogic; +signal p1_way_data_upd6_wayE :std_ulogic; +signal congr_cl6_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl6_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu6_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd6_wayF :std_ulogic; +signal p1_way_data_upd6_wayF :std_ulogic; +signal congr_cl6_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl6_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu6_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd6_wayG :std_ulogic; +signal p1_way_data_upd6_wayG :std_ulogic; +signal congr_cl6_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl6_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu6_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd6_wayH :std_ulogic; +signal p1_way_data_upd6_wayH :std_ulogic; +signal p0_congr_cl7_m :std_ulogic; +signal p1_congr_cl7_m :std_ulogic; +signal p0_congr_cl7_act_d :std_ulogic; +signal p0_congr_cl7_act_q :std_ulogic; +signal p1_congr_cl7_act_d :std_ulogic; +signal p1_congr_cl7_act_q :std_ulogic; +signal congr_cl7_act :std_ulogic; +signal congr_cl7_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl7_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu7_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd7_wayA :std_ulogic; +signal p1_way_data_upd7_wayA :std_ulogic; +signal congr_cl7_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl7_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu7_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd7_wayB :std_ulogic; +signal p1_way_data_upd7_wayB :std_ulogic; +signal congr_cl7_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl7_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu7_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd7_wayC :std_ulogic; +signal p1_way_data_upd7_wayC :std_ulogic; +signal congr_cl7_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl7_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu7_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd7_wayD :std_ulogic; +signal p1_way_data_upd7_wayD :std_ulogic; +signal congr_cl7_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl7_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu7_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd7_wayE :std_ulogic; +signal p1_way_data_upd7_wayE :std_ulogic; +signal congr_cl7_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl7_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu7_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd7_wayF :std_ulogic; +signal p1_way_data_upd7_wayF :std_ulogic; +signal congr_cl7_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl7_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu7_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd7_wayG :std_ulogic; +signal p1_way_data_upd7_wayG :std_ulogic; +signal congr_cl7_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl7_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu7_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd7_wayH :std_ulogic; +signal p1_way_data_upd7_wayH :std_ulogic; +signal p0_congr_cl8_m :std_ulogic; +signal p1_congr_cl8_m :std_ulogic; +signal p0_congr_cl8_act_d :std_ulogic; +signal p0_congr_cl8_act_q :std_ulogic; +signal p1_congr_cl8_act_d :std_ulogic; +signal p1_congr_cl8_act_q :std_ulogic; +signal congr_cl8_act :std_ulogic; +signal congr_cl8_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl8_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu8_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd8_wayA :std_ulogic; +signal p1_way_data_upd8_wayA :std_ulogic; +signal congr_cl8_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl8_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu8_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd8_wayB :std_ulogic; +signal p1_way_data_upd8_wayB :std_ulogic; +signal congr_cl8_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl8_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu8_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd8_wayC :std_ulogic; +signal p1_way_data_upd8_wayC :std_ulogic; +signal congr_cl8_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl8_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu8_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd8_wayD :std_ulogic; +signal p1_way_data_upd8_wayD :std_ulogic; +signal congr_cl8_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl8_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu8_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd8_wayE :std_ulogic; +signal p1_way_data_upd8_wayE :std_ulogic; +signal congr_cl8_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl8_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu8_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd8_wayF :std_ulogic; +signal p1_way_data_upd8_wayF :std_ulogic; +signal congr_cl8_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl8_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu8_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd8_wayG :std_ulogic; +signal p1_way_data_upd8_wayG :std_ulogic; +signal congr_cl8_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl8_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu8_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd8_wayH :std_ulogic; +signal p1_way_data_upd8_wayH :std_ulogic; +signal p0_congr_cl9_m :std_ulogic; +signal p1_congr_cl9_m :std_ulogic; +signal p0_congr_cl9_act_d :std_ulogic; +signal p0_congr_cl9_act_q :std_ulogic; +signal p1_congr_cl9_act_d :std_ulogic; +signal p1_congr_cl9_act_q :std_ulogic; +signal congr_cl9_act :std_ulogic; +signal congr_cl9_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl9_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu9_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd9_wayA :std_ulogic; +signal p1_way_data_upd9_wayA :std_ulogic; +signal congr_cl9_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl9_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu9_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd9_wayB :std_ulogic; +signal p1_way_data_upd9_wayB :std_ulogic; +signal congr_cl9_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl9_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu9_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd9_wayC :std_ulogic; +signal p1_way_data_upd9_wayC :std_ulogic; +signal congr_cl9_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl9_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu9_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd9_wayD :std_ulogic; +signal p1_way_data_upd9_wayD :std_ulogic; +signal congr_cl9_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl9_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu9_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd9_wayE :std_ulogic; +signal p1_way_data_upd9_wayE :std_ulogic; +signal congr_cl9_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl9_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu9_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd9_wayF :std_ulogic; +signal p1_way_data_upd9_wayF :std_ulogic; +signal congr_cl9_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl9_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu9_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd9_wayG :std_ulogic; +signal p1_way_data_upd9_wayG :std_ulogic; +signal congr_cl9_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl9_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu9_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd9_wayH :std_ulogic; +signal p1_way_data_upd9_wayH :std_ulogic; +signal p0_congr_cl10_m :std_ulogic; +signal p1_congr_cl10_m :std_ulogic; +signal p0_congr_cl10_act_d :std_ulogic; +signal p0_congr_cl10_act_q :std_ulogic; +signal p1_congr_cl10_act_d :std_ulogic; +signal p1_congr_cl10_act_q :std_ulogic; +signal congr_cl10_act :std_ulogic; +signal congr_cl10_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl10_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu10_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd10_wayA :std_ulogic; +signal p1_way_data_upd10_wayA :std_ulogic; +signal congr_cl10_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl10_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu10_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd10_wayB :std_ulogic; +signal p1_way_data_upd10_wayB :std_ulogic; +signal congr_cl10_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl10_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu10_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd10_wayC :std_ulogic; +signal p1_way_data_upd10_wayC :std_ulogic; +signal congr_cl10_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl10_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu10_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd10_wayD :std_ulogic; +signal p1_way_data_upd10_wayD :std_ulogic; +signal congr_cl10_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl10_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu10_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd10_wayE :std_ulogic; +signal p1_way_data_upd10_wayE :std_ulogic; +signal congr_cl10_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl10_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu10_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd10_wayF :std_ulogic; +signal p1_way_data_upd10_wayF :std_ulogic; +signal congr_cl10_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl10_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu10_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd10_wayG :std_ulogic; +signal p1_way_data_upd10_wayG :std_ulogic; +signal congr_cl10_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl10_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu10_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd10_wayH :std_ulogic; +signal p1_way_data_upd10_wayH :std_ulogic; +signal p0_congr_cl11_m :std_ulogic; +signal p1_congr_cl11_m :std_ulogic; +signal p0_congr_cl11_act_d :std_ulogic; +signal p0_congr_cl11_act_q :std_ulogic; +signal p1_congr_cl11_act_d :std_ulogic; +signal p1_congr_cl11_act_q :std_ulogic; +signal congr_cl11_act :std_ulogic; +signal congr_cl11_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl11_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu11_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd11_wayA :std_ulogic; +signal p1_way_data_upd11_wayA :std_ulogic; +signal congr_cl11_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl11_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu11_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd11_wayB :std_ulogic; +signal p1_way_data_upd11_wayB :std_ulogic; +signal congr_cl11_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl11_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu11_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd11_wayC :std_ulogic; +signal p1_way_data_upd11_wayC :std_ulogic; +signal congr_cl11_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl11_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu11_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd11_wayD :std_ulogic; +signal p1_way_data_upd11_wayD :std_ulogic; +signal congr_cl11_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl11_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu11_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd11_wayE :std_ulogic; +signal p1_way_data_upd11_wayE :std_ulogic; +signal congr_cl11_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl11_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu11_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd11_wayF :std_ulogic; +signal p1_way_data_upd11_wayF :std_ulogic; +signal congr_cl11_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl11_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu11_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd11_wayG :std_ulogic; +signal p1_way_data_upd11_wayG :std_ulogic; +signal congr_cl11_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl11_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu11_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd11_wayH :std_ulogic; +signal p1_way_data_upd11_wayH :std_ulogic; +signal p0_congr_cl12_m :std_ulogic; +signal p1_congr_cl12_m :std_ulogic; +signal p0_congr_cl12_act_d :std_ulogic; +signal p0_congr_cl12_act_q :std_ulogic; +signal p1_congr_cl12_act_d :std_ulogic; +signal p1_congr_cl12_act_q :std_ulogic; +signal congr_cl12_act :std_ulogic; +signal congr_cl12_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl12_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu12_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd12_wayA :std_ulogic; +signal p1_way_data_upd12_wayA :std_ulogic; +signal congr_cl12_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl12_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu12_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd12_wayB :std_ulogic; +signal p1_way_data_upd12_wayB :std_ulogic; +signal congr_cl12_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl12_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu12_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd12_wayC :std_ulogic; +signal p1_way_data_upd12_wayC :std_ulogic; +signal congr_cl12_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl12_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu12_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd12_wayD :std_ulogic; +signal p1_way_data_upd12_wayD :std_ulogic; +signal congr_cl12_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl12_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu12_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd12_wayE :std_ulogic; +signal p1_way_data_upd12_wayE :std_ulogic; +signal congr_cl12_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl12_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu12_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd12_wayF :std_ulogic; +signal p1_way_data_upd12_wayF :std_ulogic; +signal congr_cl12_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl12_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu12_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd12_wayG :std_ulogic; +signal p1_way_data_upd12_wayG :std_ulogic; +signal congr_cl12_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl12_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu12_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd12_wayH :std_ulogic; +signal p1_way_data_upd12_wayH :std_ulogic; +signal p0_congr_cl13_m :std_ulogic; +signal p1_congr_cl13_m :std_ulogic; +signal p0_congr_cl13_act_d :std_ulogic; +signal p0_congr_cl13_act_q :std_ulogic; +signal p1_congr_cl13_act_d :std_ulogic; +signal p1_congr_cl13_act_q :std_ulogic; +signal congr_cl13_act :std_ulogic; +signal congr_cl13_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl13_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu13_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd13_wayA :std_ulogic; +signal p1_way_data_upd13_wayA :std_ulogic; +signal congr_cl13_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl13_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu13_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd13_wayB :std_ulogic; +signal p1_way_data_upd13_wayB :std_ulogic; +signal congr_cl13_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl13_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu13_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd13_wayC :std_ulogic; +signal p1_way_data_upd13_wayC :std_ulogic; +signal congr_cl13_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl13_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu13_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd13_wayD :std_ulogic; +signal p1_way_data_upd13_wayD :std_ulogic; +signal congr_cl13_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl13_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu13_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd13_wayE :std_ulogic; +signal p1_way_data_upd13_wayE :std_ulogic; +signal congr_cl13_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl13_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu13_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd13_wayF :std_ulogic; +signal p1_way_data_upd13_wayF :std_ulogic; +signal congr_cl13_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl13_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu13_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd13_wayG :std_ulogic; +signal p1_way_data_upd13_wayG :std_ulogic; +signal congr_cl13_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl13_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu13_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd13_wayH :std_ulogic; +signal p1_way_data_upd13_wayH :std_ulogic; +signal p0_congr_cl14_m :std_ulogic; +signal p1_congr_cl14_m :std_ulogic; +signal p0_congr_cl14_act_d :std_ulogic; +signal p0_congr_cl14_act_q :std_ulogic; +signal p1_congr_cl14_act_d :std_ulogic; +signal p1_congr_cl14_act_q :std_ulogic; +signal congr_cl14_act :std_ulogic; +signal congr_cl14_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl14_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu14_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd14_wayA :std_ulogic; +signal p1_way_data_upd14_wayA :std_ulogic; +signal congr_cl14_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl14_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu14_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd14_wayB :std_ulogic; +signal p1_way_data_upd14_wayB :std_ulogic; +signal congr_cl14_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl14_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu14_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd14_wayC :std_ulogic; +signal p1_way_data_upd14_wayC :std_ulogic; +signal congr_cl14_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl14_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu14_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd14_wayD :std_ulogic; +signal p1_way_data_upd14_wayD :std_ulogic; +signal congr_cl14_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl14_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu14_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd14_wayE :std_ulogic; +signal p1_way_data_upd14_wayE :std_ulogic; +signal congr_cl14_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl14_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu14_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd14_wayF :std_ulogic; +signal p1_way_data_upd14_wayF :std_ulogic; +signal congr_cl14_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl14_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu14_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd14_wayG :std_ulogic; +signal p1_way_data_upd14_wayG :std_ulogic; +signal congr_cl14_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl14_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu14_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd14_wayH :std_ulogic; +signal p1_way_data_upd14_wayH :std_ulogic; +signal p0_congr_cl15_m :std_ulogic; +signal p1_congr_cl15_m :std_ulogic; +signal p0_congr_cl15_act_d :std_ulogic; +signal p0_congr_cl15_act_q :std_ulogic; +signal p1_congr_cl15_act_d :std_ulogic; +signal p1_congr_cl15_act_q :std_ulogic; +signal congr_cl15_act :std_ulogic; +signal congr_cl15_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl15_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu15_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd15_wayA :std_ulogic; +signal p1_way_data_upd15_wayA :std_ulogic; +signal congr_cl15_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl15_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu15_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd15_wayB :std_ulogic; +signal p1_way_data_upd15_wayB :std_ulogic; +signal congr_cl15_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl15_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu15_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd15_wayC :std_ulogic; +signal p1_way_data_upd15_wayC :std_ulogic; +signal congr_cl15_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl15_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu15_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd15_wayD :std_ulogic; +signal p1_way_data_upd15_wayD :std_ulogic; +signal congr_cl15_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl15_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu15_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd15_wayE :std_ulogic; +signal p1_way_data_upd15_wayE :std_ulogic; +signal congr_cl15_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl15_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu15_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd15_wayF :std_ulogic; +signal p1_way_data_upd15_wayF :std_ulogic; +signal congr_cl15_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl15_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu15_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd15_wayG :std_ulogic; +signal p1_way_data_upd15_wayG :std_ulogic; +signal congr_cl15_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl15_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu15_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd15_wayH :std_ulogic; +signal p1_way_data_upd15_wayH :std_ulogic; +signal p0_congr_cl16_m :std_ulogic; +signal p1_congr_cl16_m :std_ulogic; +signal p0_congr_cl16_act_d :std_ulogic; +signal p0_congr_cl16_act_q :std_ulogic; +signal p1_congr_cl16_act_d :std_ulogic; +signal p1_congr_cl16_act_q :std_ulogic; +signal congr_cl16_act :std_ulogic; +signal congr_cl16_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl16_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu16_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd16_wayA :std_ulogic; +signal p1_way_data_upd16_wayA :std_ulogic; +signal congr_cl16_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl16_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu16_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd16_wayB :std_ulogic; +signal p1_way_data_upd16_wayB :std_ulogic; +signal congr_cl16_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl16_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu16_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd16_wayC :std_ulogic; +signal p1_way_data_upd16_wayC :std_ulogic; +signal congr_cl16_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl16_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu16_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd16_wayD :std_ulogic; +signal p1_way_data_upd16_wayD :std_ulogic; +signal congr_cl16_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl16_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu16_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd16_wayE :std_ulogic; +signal p1_way_data_upd16_wayE :std_ulogic; +signal congr_cl16_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl16_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu16_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd16_wayF :std_ulogic; +signal p1_way_data_upd16_wayF :std_ulogic; +signal congr_cl16_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl16_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu16_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd16_wayG :std_ulogic; +signal p1_way_data_upd16_wayG :std_ulogic; +signal congr_cl16_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl16_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu16_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd16_wayH :std_ulogic; +signal p1_way_data_upd16_wayH :std_ulogic; +signal p0_congr_cl17_m :std_ulogic; +signal p1_congr_cl17_m :std_ulogic; +signal p0_congr_cl17_act_d :std_ulogic; +signal p0_congr_cl17_act_q :std_ulogic; +signal p1_congr_cl17_act_d :std_ulogic; +signal p1_congr_cl17_act_q :std_ulogic; +signal congr_cl17_act :std_ulogic; +signal congr_cl17_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl17_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu17_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd17_wayA :std_ulogic; +signal p1_way_data_upd17_wayA :std_ulogic; +signal congr_cl17_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl17_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu17_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd17_wayB :std_ulogic; +signal p1_way_data_upd17_wayB :std_ulogic; +signal congr_cl17_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl17_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu17_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd17_wayC :std_ulogic; +signal p1_way_data_upd17_wayC :std_ulogic; +signal congr_cl17_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl17_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu17_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd17_wayD :std_ulogic; +signal p1_way_data_upd17_wayD :std_ulogic; +signal congr_cl17_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl17_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu17_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd17_wayE :std_ulogic; +signal p1_way_data_upd17_wayE :std_ulogic; +signal congr_cl17_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl17_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu17_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd17_wayF :std_ulogic; +signal p1_way_data_upd17_wayF :std_ulogic; +signal congr_cl17_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl17_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu17_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd17_wayG :std_ulogic; +signal p1_way_data_upd17_wayG :std_ulogic; +signal congr_cl17_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl17_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu17_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd17_wayH :std_ulogic; +signal p1_way_data_upd17_wayH :std_ulogic; +signal p0_congr_cl18_m :std_ulogic; +signal p1_congr_cl18_m :std_ulogic; +signal p0_congr_cl18_act_d :std_ulogic; +signal p0_congr_cl18_act_q :std_ulogic; +signal p1_congr_cl18_act_d :std_ulogic; +signal p1_congr_cl18_act_q :std_ulogic; +signal congr_cl18_act :std_ulogic; +signal congr_cl18_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl18_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu18_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd18_wayA :std_ulogic; +signal p1_way_data_upd18_wayA :std_ulogic; +signal congr_cl18_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl18_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu18_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd18_wayB :std_ulogic; +signal p1_way_data_upd18_wayB :std_ulogic; +signal congr_cl18_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl18_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu18_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd18_wayC :std_ulogic; +signal p1_way_data_upd18_wayC :std_ulogic; +signal congr_cl18_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl18_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu18_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd18_wayD :std_ulogic; +signal p1_way_data_upd18_wayD :std_ulogic; +signal congr_cl18_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl18_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu18_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd18_wayE :std_ulogic; +signal p1_way_data_upd18_wayE :std_ulogic; +signal congr_cl18_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl18_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu18_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd18_wayF :std_ulogic; +signal p1_way_data_upd18_wayF :std_ulogic; +signal congr_cl18_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl18_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu18_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd18_wayG :std_ulogic; +signal p1_way_data_upd18_wayG :std_ulogic; +signal congr_cl18_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl18_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu18_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd18_wayH :std_ulogic; +signal p1_way_data_upd18_wayH :std_ulogic; +signal p0_congr_cl19_m :std_ulogic; +signal p1_congr_cl19_m :std_ulogic; +signal p0_congr_cl19_act_d :std_ulogic; +signal p0_congr_cl19_act_q :std_ulogic; +signal p1_congr_cl19_act_d :std_ulogic; +signal p1_congr_cl19_act_q :std_ulogic; +signal congr_cl19_act :std_ulogic; +signal congr_cl19_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl19_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu19_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd19_wayA :std_ulogic; +signal p1_way_data_upd19_wayA :std_ulogic; +signal congr_cl19_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl19_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu19_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd19_wayB :std_ulogic; +signal p1_way_data_upd19_wayB :std_ulogic; +signal congr_cl19_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl19_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu19_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd19_wayC :std_ulogic; +signal p1_way_data_upd19_wayC :std_ulogic; +signal congr_cl19_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl19_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu19_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd19_wayD :std_ulogic; +signal p1_way_data_upd19_wayD :std_ulogic; +signal congr_cl19_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl19_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu19_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd19_wayE :std_ulogic; +signal p1_way_data_upd19_wayE :std_ulogic; +signal congr_cl19_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl19_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu19_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd19_wayF :std_ulogic; +signal p1_way_data_upd19_wayF :std_ulogic; +signal congr_cl19_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl19_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu19_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd19_wayG :std_ulogic; +signal p1_way_data_upd19_wayG :std_ulogic; +signal congr_cl19_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl19_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu19_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd19_wayH :std_ulogic; +signal p1_way_data_upd19_wayH :std_ulogic; +signal p0_congr_cl20_m :std_ulogic; +signal p1_congr_cl20_m :std_ulogic; +signal p0_congr_cl20_act_d :std_ulogic; +signal p0_congr_cl20_act_q :std_ulogic; +signal p1_congr_cl20_act_d :std_ulogic; +signal p1_congr_cl20_act_q :std_ulogic; +signal congr_cl20_act :std_ulogic; +signal congr_cl20_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl20_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu20_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd20_wayA :std_ulogic; +signal p1_way_data_upd20_wayA :std_ulogic; +signal congr_cl20_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl20_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu20_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd20_wayB :std_ulogic; +signal p1_way_data_upd20_wayB :std_ulogic; +signal congr_cl20_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl20_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu20_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd20_wayC :std_ulogic; +signal p1_way_data_upd20_wayC :std_ulogic; +signal congr_cl20_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl20_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu20_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd20_wayD :std_ulogic; +signal p1_way_data_upd20_wayD :std_ulogic; +signal congr_cl20_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl20_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu20_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd20_wayE :std_ulogic; +signal p1_way_data_upd20_wayE :std_ulogic; +signal congr_cl20_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl20_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu20_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd20_wayF :std_ulogic; +signal p1_way_data_upd20_wayF :std_ulogic; +signal congr_cl20_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl20_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu20_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd20_wayG :std_ulogic; +signal p1_way_data_upd20_wayG :std_ulogic; +signal congr_cl20_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl20_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu20_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd20_wayH :std_ulogic; +signal p1_way_data_upd20_wayH :std_ulogic; +signal p0_congr_cl21_m :std_ulogic; +signal p1_congr_cl21_m :std_ulogic; +signal p0_congr_cl21_act_d :std_ulogic; +signal p0_congr_cl21_act_q :std_ulogic; +signal p1_congr_cl21_act_d :std_ulogic; +signal p1_congr_cl21_act_q :std_ulogic; +signal congr_cl21_act :std_ulogic; +signal congr_cl21_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl21_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu21_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd21_wayA :std_ulogic; +signal p1_way_data_upd21_wayA :std_ulogic; +signal congr_cl21_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl21_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu21_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd21_wayB :std_ulogic; +signal p1_way_data_upd21_wayB :std_ulogic; +signal congr_cl21_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl21_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu21_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd21_wayC :std_ulogic; +signal p1_way_data_upd21_wayC :std_ulogic; +signal congr_cl21_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl21_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu21_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd21_wayD :std_ulogic; +signal p1_way_data_upd21_wayD :std_ulogic; +signal congr_cl21_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl21_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu21_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd21_wayE :std_ulogic; +signal p1_way_data_upd21_wayE :std_ulogic; +signal congr_cl21_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl21_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu21_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd21_wayF :std_ulogic; +signal p1_way_data_upd21_wayF :std_ulogic; +signal congr_cl21_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl21_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu21_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd21_wayG :std_ulogic; +signal p1_way_data_upd21_wayG :std_ulogic; +signal congr_cl21_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl21_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu21_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd21_wayH :std_ulogic; +signal p1_way_data_upd21_wayH :std_ulogic; +signal p0_congr_cl22_m :std_ulogic; +signal p1_congr_cl22_m :std_ulogic; +signal p0_congr_cl22_act_d :std_ulogic; +signal p0_congr_cl22_act_q :std_ulogic; +signal p1_congr_cl22_act_d :std_ulogic; +signal p1_congr_cl22_act_q :std_ulogic; +signal congr_cl22_act :std_ulogic; +signal congr_cl22_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl22_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu22_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd22_wayA :std_ulogic; +signal p1_way_data_upd22_wayA :std_ulogic; +signal congr_cl22_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl22_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu22_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd22_wayB :std_ulogic; +signal p1_way_data_upd22_wayB :std_ulogic; +signal congr_cl22_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl22_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu22_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd22_wayC :std_ulogic; +signal p1_way_data_upd22_wayC :std_ulogic; +signal congr_cl22_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl22_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu22_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd22_wayD :std_ulogic; +signal p1_way_data_upd22_wayD :std_ulogic; +signal congr_cl22_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl22_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu22_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd22_wayE :std_ulogic; +signal p1_way_data_upd22_wayE :std_ulogic; +signal congr_cl22_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl22_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu22_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd22_wayF :std_ulogic; +signal p1_way_data_upd22_wayF :std_ulogic; +signal congr_cl22_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl22_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu22_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd22_wayG :std_ulogic; +signal p1_way_data_upd22_wayG :std_ulogic; +signal congr_cl22_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl22_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu22_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd22_wayH :std_ulogic; +signal p1_way_data_upd22_wayH :std_ulogic; +signal p0_congr_cl23_m :std_ulogic; +signal p1_congr_cl23_m :std_ulogic; +signal p0_congr_cl23_act_d :std_ulogic; +signal p0_congr_cl23_act_q :std_ulogic; +signal p1_congr_cl23_act_d :std_ulogic; +signal p1_congr_cl23_act_q :std_ulogic; +signal congr_cl23_act :std_ulogic; +signal congr_cl23_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl23_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu23_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd23_wayA :std_ulogic; +signal p1_way_data_upd23_wayA :std_ulogic; +signal congr_cl23_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl23_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu23_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd23_wayB :std_ulogic; +signal p1_way_data_upd23_wayB :std_ulogic; +signal congr_cl23_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl23_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu23_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd23_wayC :std_ulogic; +signal p1_way_data_upd23_wayC :std_ulogic; +signal congr_cl23_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl23_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu23_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd23_wayD :std_ulogic; +signal p1_way_data_upd23_wayD :std_ulogic; +signal congr_cl23_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl23_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu23_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd23_wayE :std_ulogic; +signal p1_way_data_upd23_wayE :std_ulogic; +signal congr_cl23_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl23_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu23_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd23_wayF :std_ulogic; +signal p1_way_data_upd23_wayF :std_ulogic; +signal congr_cl23_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl23_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu23_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd23_wayG :std_ulogic; +signal p1_way_data_upd23_wayG :std_ulogic; +signal congr_cl23_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl23_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu23_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd23_wayH :std_ulogic; +signal p1_way_data_upd23_wayH :std_ulogic; +signal p0_congr_cl24_m :std_ulogic; +signal p1_congr_cl24_m :std_ulogic; +signal p0_congr_cl24_act_d :std_ulogic; +signal p0_congr_cl24_act_q :std_ulogic; +signal p1_congr_cl24_act_d :std_ulogic; +signal p1_congr_cl24_act_q :std_ulogic; +signal congr_cl24_act :std_ulogic; +signal congr_cl24_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl24_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu24_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd24_wayA :std_ulogic; +signal p1_way_data_upd24_wayA :std_ulogic; +signal congr_cl24_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl24_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu24_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd24_wayB :std_ulogic; +signal p1_way_data_upd24_wayB :std_ulogic; +signal congr_cl24_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl24_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu24_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd24_wayC :std_ulogic; +signal p1_way_data_upd24_wayC :std_ulogic; +signal congr_cl24_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl24_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu24_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd24_wayD :std_ulogic; +signal p1_way_data_upd24_wayD :std_ulogic; +signal congr_cl24_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl24_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu24_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd24_wayE :std_ulogic; +signal p1_way_data_upd24_wayE :std_ulogic; +signal congr_cl24_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl24_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu24_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd24_wayF :std_ulogic; +signal p1_way_data_upd24_wayF :std_ulogic; +signal congr_cl24_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl24_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu24_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd24_wayG :std_ulogic; +signal p1_way_data_upd24_wayG :std_ulogic; +signal congr_cl24_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl24_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu24_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd24_wayH :std_ulogic; +signal p1_way_data_upd24_wayH :std_ulogic; +signal p0_congr_cl25_m :std_ulogic; +signal p1_congr_cl25_m :std_ulogic; +signal p0_congr_cl25_act_d :std_ulogic; +signal p0_congr_cl25_act_q :std_ulogic; +signal p1_congr_cl25_act_d :std_ulogic; +signal p1_congr_cl25_act_q :std_ulogic; +signal congr_cl25_act :std_ulogic; +signal congr_cl25_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl25_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu25_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd25_wayA :std_ulogic; +signal p1_way_data_upd25_wayA :std_ulogic; +signal congr_cl25_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl25_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu25_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd25_wayB :std_ulogic; +signal p1_way_data_upd25_wayB :std_ulogic; +signal congr_cl25_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl25_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu25_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd25_wayC :std_ulogic; +signal p1_way_data_upd25_wayC :std_ulogic; +signal congr_cl25_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl25_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu25_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd25_wayD :std_ulogic; +signal p1_way_data_upd25_wayD :std_ulogic; +signal congr_cl25_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl25_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu25_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd25_wayE :std_ulogic; +signal p1_way_data_upd25_wayE :std_ulogic; +signal congr_cl25_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl25_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu25_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd25_wayF :std_ulogic; +signal p1_way_data_upd25_wayF :std_ulogic; +signal congr_cl25_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl25_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu25_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd25_wayG :std_ulogic; +signal p1_way_data_upd25_wayG :std_ulogic; +signal congr_cl25_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl25_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu25_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd25_wayH :std_ulogic; +signal p1_way_data_upd25_wayH :std_ulogic; +signal p0_congr_cl26_m :std_ulogic; +signal p1_congr_cl26_m :std_ulogic; +signal p0_congr_cl26_act_d :std_ulogic; +signal p0_congr_cl26_act_q :std_ulogic; +signal p1_congr_cl26_act_d :std_ulogic; +signal p1_congr_cl26_act_q :std_ulogic; +signal congr_cl26_act :std_ulogic; +signal congr_cl26_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl26_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu26_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd26_wayA :std_ulogic; +signal p1_way_data_upd26_wayA :std_ulogic; +signal congr_cl26_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl26_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu26_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd26_wayB :std_ulogic; +signal p1_way_data_upd26_wayB :std_ulogic; +signal congr_cl26_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl26_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu26_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd26_wayC :std_ulogic; +signal p1_way_data_upd26_wayC :std_ulogic; +signal congr_cl26_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl26_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu26_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd26_wayD :std_ulogic; +signal p1_way_data_upd26_wayD :std_ulogic; +signal congr_cl26_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl26_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu26_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd26_wayE :std_ulogic; +signal p1_way_data_upd26_wayE :std_ulogic; +signal congr_cl26_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl26_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu26_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd26_wayF :std_ulogic; +signal p1_way_data_upd26_wayF :std_ulogic; +signal congr_cl26_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl26_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu26_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd26_wayG :std_ulogic; +signal p1_way_data_upd26_wayG :std_ulogic; +signal congr_cl26_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl26_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu26_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd26_wayH :std_ulogic; +signal p1_way_data_upd26_wayH :std_ulogic; +signal p0_congr_cl27_m :std_ulogic; +signal p1_congr_cl27_m :std_ulogic; +signal p0_congr_cl27_act_d :std_ulogic; +signal p0_congr_cl27_act_q :std_ulogic; +signal p1_congr_cl27_act_d :std_ulogic; +signal p1_congr_cl27_act_q :std_ulogic; +signal congr_cl27_act :std_ulogic; +signal congr_cl27_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl27_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu27_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd27_wayA :std_ulogic; +signal p1_way_data_upd27_wayA :std_ulogic; +signal congr_cl27_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl27_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu27_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd27_wayB :std_ulogic; +signal p1_way_data_upd27_wayB :std_ulogic; +signal congr_cl27_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl27_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu27_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd27_wayC :std_ulogic; +signal p1_way_data_upd27_wayC :std_ulogic; +signal congr_cl27_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl27_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu27_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd27_wayD :std_ulogic; +signal p1_way_data_upd27_wayD :std_ulogic; +signal congr_cl27_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl27_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu27_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd27_wayE :std_ulogic; +signal p1_way_data_upd27_wayE :std_ulogic; +signal congr_cl27_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl27_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu27_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd27_wayF :std_ulogic; +signal p1_way_data_upd27_wayF :std_ulogic; +signal congr_cl27_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl27_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu27_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd27_wayG :std_ulogic; +signal p1_way_data_upd27_wayG :std_ulogic; +signal congr_cl27_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl27_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu27_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd27_wayH :std_ulogic; +signal p1_way_data_upd27_wayH :std_ulogic; +signal p0_congr_cl28_m :std_ulogic; +signal p1_congr_cl28_m :std_ulogic; +signal p0_congr_cl28_act_d :std_ulogic; +signal p0_congr_cl28_act_q :std_ulogic; +signal p1_congr_cl28_act_d :std_ulogic; +signal p1_congr_cl28_act_q :std_ulogic; +signal congr_cl28_act :std_ulogic; +signal congr_cl28_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl28_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu28_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd28_wayA :std_ulogic; +signal p1_way_data_upd28_wayA :std_ulogic; +signal congr_cl28_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl28_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu28_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd28_wayB :std_ulogic; +signal p1_way_data_upd28_wayB :std_ulogic; +signal congr_cl28_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl28_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu28_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd28_wayC :std_ulogic; +signal p1_way_data_upd28_wayC :std_ulogic; +signal congr_cl28_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl28_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu28_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd28_wayD :std_ulogic; +signal p1_way_data_upd28_wayD :std_ulogic; +signal congr_cl28_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl28_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu28_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd28_wayE :std_ulogic; +signal p1_way_data_upd28_wayE :std_ulogic; +signal congr_cl28_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl28_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu28_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd28_wayF :std_ulogic; +signal p1_way_data_upd28_wayF :std_ulogic; +signal congr_cl28_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl28_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu28_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd28_wayG :std_ulogic; +signal p1_way_data_upd28_wayG :std_ulogic; +signal congr_cl28_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl28_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu28_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd28_wayH :std_ulogic; +signal p1_way_data_upd28_wayH :std_ulogic; +signal p0_congr_cl29_m :std_ulogic; +signal p1_congr_cl29_m :std_ulogic; +signal p0_congr_cl29_act_d :std_ulogic; +signal p0_congr_cl29_act_q :std_ulogic; +signal p1_congr_cl29_act_d :std_ulogic; +signal p1_congr_cl29_act_q :std_ulogic; +signal congr_cl29_act :std_ulogic; +signal congr_cl29_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl29_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu29_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd29_wayA :std_ulogic; +signal p1_way_data_upd29_wayA :std_ulogic; +signal congr_cl29_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl29_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu29_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd29_wayB :std_ulogic; +signal p1_way_data_upd29_wayB :std_ulogic; +signal congr_cl29_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl29_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu29_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd29_wayC :std_ulogic; +signal p1_way_data_upd29_wayC :std_ulogic; +signal congr_cl29_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl29_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu29_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd29_wayD :std_ulogic; +signal p1_way_data_upd29_wayD :std_ulogic; +signal congr_cl29_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl29_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu29_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd29_wayE :std_ulogic; +signal p1_way_data_upd29_wayE :std_ulogic; +signal congr_cl29_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl29_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu29_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd29_wayF :std_ulogic; +signal p1_way_data_upd29_wayF :std_ulogic; +signal congr_cl29_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl29_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu29_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd29_wayG :std_ulogic; +signal p1_way_data_upd29_wayG :std_ulogic; +signal congr_cl29_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl29_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu29_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd29_wayH :std_ulogic; +signal p1_way_data_upd29_wayH :std_ulogic; +signal p0_congr_cl30_m :std_ulogic; +signal p1_congr_cl30_m :std_ulogic; +signal p0_congr_cl30_act_d :std_ulogic; +signal p0_congr_cl30_act_q :std_ulogic; +signal p1_congr_cl30_act_d :std_ulogic; +signal p1_congr_cl30_act_q :std_ulogic; +signal congr_cl30_act :std_ulogic; +signal congr_cl30_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl30_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu30_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd30_wayA :std_ulogic; +signal p1_way_data_upd30_wayA :std_ulogic; +signal congr_cl30_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl30_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu30_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd30_wayB :std_ulogic; +signal p1_way_data_upd30_wayB :std_ulogic; +signal congr_cl30_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl30_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu30_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd30_wayC :std_ulogic; +signal p1_way_data_upd30_wayC :std_ulogic; +signal congr_cl30_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl30_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu30_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd30_wayD :std_ulogic; +signal p1_way_data_upd30_wayD :std_ulogic; +signal congr_cl30_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl30_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu30_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd30_wayE :std_ulogic; +signal p1_way_data_upd30_wayE :std_ulogic; +signal congr_cl30_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl30_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu30_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd30_wayF :std_ulogic; +signal p1_way_data_upd30_wayF :std_ulogic; +signal congr_cl30_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl30_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu30_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd30_wayG :std_ulogic; +signal p1_way_data_upd30_wayG :std_ulogic; +signal congr_cl30_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl30_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu30_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd30_wayH :std_ulogic; +signal p1_way_data_upd30_wayH :std_ulogic; +signal p0_congr_cl31_m :std_ulogic; +signal p1_congr_cl31_m :std_ulogic; +signal p0_congr_cl31_act_d :std_ulogic; +signal p0_congr_cl31_act_q :std_ulogic; +signal p1_congr_cl31_act_d :std_ulogic; +signal p1_congr_cl31_act_q :std_ulogic; +signal congr_cl31_act :std_ulogic; +signal congr_cl31_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl31_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu31_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd31_wayA :std_ulogic; +signal p1_way_data_upd31_wayA :std_ulogic; +signal congr_cl31_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl31_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu31_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd31_wayB :std_ulogic; +signal p1_way_data_upd31_wayB :std_ulogic; +signal congr_cl31_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl31_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu31_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd31_wayC :std_ulogic; +signal p1_way_data_upd31_wayC :std_ulogic; +signal congr_cl31_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl31_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu31_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd31_wayD :std_ulogic; +signal p1_way_data_upd31_wayD :std_ulogic; +signal congr_cl31_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl31_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu31_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd31_wayE :std_ulogic; +signal p1_way_data_upd31_wayE :std_ulogic; +signal congr_cl31_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl31_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu31_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd31_wayF :std_ulogic; +signal p1_way_data_upd31_wayF :std_ulogic; +signal congr_cl31_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl31_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu31_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd31_wayG :std_ulogic; +signal p1_way_data_upd31_wayG :std_ulogic; +signal congr_cl31_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl31_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu31_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd31_wayH :std_ulogic; +signal p1_way_data_upd31_wayH :std_ulogic; +signal tagA_hit :std_ulogic; +signal tagA_hit_b :std_ulogic; +signal arr_wayA_val :std_ulogic_vector(0 to 5); +signal p0_arr_wayA_rd :std_ulogic_vector(0 to 5); +signal flush_wayA_d :std_ulogic_vector(0 to 5); +signal flush_wayA_q :std_ulogic_vector(0 to 5); +signal rel_wayA_clr :std_ulogic; +signal rel_wayA_set :std_ulogic; +signal rel_par_wA_clr :std_ulogic; +signal wayA_val :std_ulogic_vector(0 to 5); +signal wayA_val_b_q :std_ulogic_vector(0 to 5); +signal wayA_val_b1 :std_ulogic; +signal congr_cl_ex2_wayA_byp :std_ulogic_vector(1 to 7); +signal congr_cl_ex2_wayA_sel :std_ulogic_vector(2 to 7); +signal rel_arr_wayA_val :std_ulogic_vector(0 to 5); +signal p1_arr_wayA_rd :std_ulogic_vector(0 to 5); +signal rel_wayA_val_b_q :std_ulogic_vector(0 to 5); +signal rel_wayA_val :std_ulogic_vector(0 to 5); +signal congr_cl_rel13_wayA_byp :std_ulogic_vector(1 to 7); +signal congr_cl_rel13_wayA_sel :std_ulogic_vector(2 to 7); +signal reload_wayA_d :std_ulogic_vector(0 to 5); +signal reload_wayA_q :std_ulogic_vector(0 to 5); +signal reload_wayA_data_d :std_ulogic_vector(0 to 5); +signal reload_wayA_data_q :std_ulogic_vector(0 to 5); +signal reload_wayA_data2_d :std_ulogic_vector(0 to 5); +signal reload_wayA_data2_q :std_ulogic_vector(0 to 5); +signal reload_wayA_upd_d :std_ulogic; +signal reload_wayA_upd_q :std_ulogic; +signal reload_wayA_clr :std_ulogic; +signal reload_wayA_upd2_d :std_ulogic; +signal reload_wayA_upd2_q :std_ulogic; +signal reload_wayA_upd3_d :std_ulogic; +signal reload_wayA_upd3_q :std_ulogic; +signal reload_wayA :std_ulogic_vector(0 to 5); +signal binv_wayA_upd_d :std_ulogic; +signal binv_wayA_upd_q :std_ulogic; +signal binv_wayA_upd1 :std_ulogic; +signal binv_wayA_upd2_d :std_ulogic; +signal binv_wayA_upd2_q :std_ulogic; +signal binv_wayA_upd3_d :std_ulogic; +signal binv_wayA_upd3_q :std_ulogic; +signal flush_wayA_data1 :std_ulogic_vector(0 to 5); +signal flush_wayA_data_d :std_ulogic_vector(0 to 5); +signal flush_wayA_data_q :std_ulogic_vector(0 to 5); +signal flush_wayA_data2_d :std_ulogic_vector(0 to 5); +signal flush_wayA_data2_q :std_ulogic_vector(0 to 5); +signal xu_op_hit_wayA_b :std_ulogic; +signal xu_op_hit_wayA :std_ulogic; +signal xu_op_hit_wayA_dly_b :std_ulogic; +signal clr_val_wayA :std_ulogic; +signal upd_lck_wayA :std_ulogic_vector(0 to 1); +signal inval_clr_lck_wA_d :std_ulogic; +signal inval_clr_lck_wA_q :std_ulogic; +signal perr_way_det_wayA :std_ulogic; +signal perr_wayA_watch_lost :std_ulogic_vector(0 to 3); +signal wayA_watch_value :std_ulogic; +signal ex4_lost_wayA :std_ulogic_vector(0 to 3); +signal ex3_xuop_lost_watch_wayA :std_ulogic; +signal ex3_xuop_wayA_upd :std_ulogic; +signal ex4_xuop_wayA_upd_d :std_ulogic; +signal ex4_xuop_wayA_upd_q :std_ulogic; +signal ex4_wayA_val_d :std_ulogic_vector(0 to 5); +signal ex4_wayA_val_q :std_ulogic_vector(0 to 5); +signal rel_wayA_val_stg_d :std_ulogic_vector(0 to 5); +signal rel_wayA_val_stg_q :std_ulogic_vector(0 to 5); +signal ex5_xuop_wayA_upd_d :std_ulogic; +signal ex5_xuop_wayA_upd_q :std_ulogic; +signal congr_cl_ex3_upd_wayA :std_ulogic; +signal congr_cl_ex4_upd_wayA :std_ulogic; +signal congr_cl_ex5_upd_wayA :std_ulogic; +signal congr_cl_m_upd_wayA_d :std_ulogic; +signal congr_cl_m_upd_wayA_q :std_ulogic; +signal ex3_cClass_wayA_hit :std_ulogic; +signal wayA_later_stg_pri :std_ulogic_vector(0 to 5); +signal wayA_early_stg_pri :std_ulogic_vector(0 to 5); +signal wayA_stg_val :std_ulogic_vector(0 to 5); +signal wayA_stg_val_b :std_ulogic_vector(0 to 5); +signal rel_wayA_later_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayA_early_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayA_stg_val :std_ulogic_vector(0 to 5); +signal rel_wayA_stg_val_b :std_ulogic_vector(0 to 5); +signal wayA_early_sel :std_ulogic; +signal wayA_late_sel :std_ulogic; +signal rel_wayA_early_sel :std_ulogic; +signal rel_wayA_late_sel :std_ulogic; +signal ex3_wayA_hit :std_ulogic; +signal rel_lost_watch_wayA_evict :std_ulogic_vector(0 to 3); +signal ex3_wayA_fxubyp_val_d :std_ulogic; +signal ex3_wayA_fxubyp_val_q :std_ulogic; +signal ex4_wayA_fxubyp_val_d :std_ulogic; +signal ex4_wayA_fxubyp_val_q :std_ulogic; +signal ex3_wayA_relbyp_val_d :std_ulogic; +signal ex3_wayA_relbyp_val_q :std_ulogic; +signal ex4_wayA_relbyp_val_d :std_ulogic; +signal ex4_wayA_relbyp_val_q :std_ulogic; +signal ex4_wayA_byp_sel :std_ulogic_vector(0 to 1); +signal rel24_wayA_fxubyp_val_d :std_ulogic; +signal rel24_wayA_fxubyp_val_q :std_ulogic; +signal rel24_wayA_relbyp_val_d :std_ulogic; +signal rel24_wayA_relbyp_val_q :std_ulogic; +signal rel24_wayA_byp_sel :std_ulogic_vector(0 to 1); +signal tagB_hit :std_ulogic; +signal tagB_hit_b :std_ulogic; +signal arr_wayB_val :std_ulogic_vector(0 to 5); +signal p0_arr_wayB_rd :std_ulogic_vector(0 to 5); +signal flush_wayB_d :std_ulogic_vector(0 to 5); +signal flush_wayB_q :std_ulogic_vector(0 to 5); +signal rel_wayB_clr :std_ulogic; +signal rel_wayB_set :std_ulogic; +signal rel_par_wB_clr :std_ulogic; +signal wayB_val :std_ulogic_vector(0 to 5); +signal wayB_val_b_q :std_ulogic_vector(0 to 5); +signal wayB_val_b1 :std_ulogic; +signal congr_cl_ex2_wayB_byp :std_ulogic_vector(1 to 7); +signal congr_cl_ex2_wayB_sel :std_ulogic_vector(2 to 7); +signal rel_arr_wayB_val :std_ulogic_vector(0 to 5); +signal p1_arr_wayB_rd :std_ulogic_vector(0 to 5); +signal rel_wayB_val_b_q :std_ulogic_vector(0 to 5); +signal rel_wayB_val :std_ulogic_vector(0 to 5); +signal congr_cl_rel13_wayB_byp :std_ulogic_vector(1 to 7); +signal congr_cl_rel13_wayB_sel :std_ulogic_vector(2 to 7); +signal reload_wayB_d :std_ulogic_vector(0 to 5); +signal reload_wayB_q :std_ulogic_vector(0 to 5); +signal reload_wayB_data_d :std_ulogic_vector(0 to 5); +signal reload_wayB_data_q :std_ulogic_vector(0 to 5); +signal reload_wayB_data2_d :std_ulogic_vector(0 to 5); +signal reload_wayB_data2_q :std_ulogic_vector(0 to 5); +signal reload_wayB_upd_d :std_ulogic; +signal reload_wayB_upd_q :std_ulogic; +signal reload_wayB_clr :std_ulogic; +signal reload_wayB_upd2_d :std_ulogic; +signal reload_wayB_upd2_q :std_ulogic; +signal reload_wayB_upd3_d :std_ulogic; +signal reload_wayB_upd3_q :std_ulogic; +signal reload_wayB :std_ulogic_vector(0 to 5); +signal binv_wayB_upd_d :std_ulogic; +signal binv_wayB_upd_q :std_ulogic; +signal binv_wayB_upd1 :std_ulogic; +signal binv_wayB_upd2_d :std_ulogic; +signal binv_wayB_upd2_q :std_ulogic; +signal binv_wayB_upd3_d :std_ulogic; +signal binv_wayB_upd3_q :std_ulogic; +signal flush_wayB_data1 :std_ulogic_vector(0 to 5); +signal flush_wayB_data_d :std_ulogic_vector(0 to 5); +signal flush_wayB_data_q :std_ulogic_vector(0 to 5); +signal flush_wayB_data2_d :std_ulogic_vector(0 to 5); +signal flush_wayB_data2_q :std_ulogic_vector(0 to 5); +signal xu_op_hit_wayB_b :std_ulogic; +signal xu_op_hit_wayB :std_ulogic; +signal xu_op_hit_wayB_dly_b :std_ulogic; +signal clr_val_wayB :std_ulogic; +signal upd_lck_wayB :std_ulogic_vector(0 to 1); +signal inval_clr_lck_wB_d :std_ulogic; +signal inval_clr_lck_wB_q :std_ulogic; +signal perr_way_det_wayB :std_ulogic; +signal perr_wayB_watch_lost :std_ulogic_vector(0 to 3); +signal wayB_watch_value :std_ulogic; +signal ex4_lost_wayB :std_ulogic_vector(0 to 3); +signal ex3_xuop_lost_watch_wayB :std_ulogic; +signal ex3_xuop_wayB_upd :std_ulogic; +signal ex4_xuop_wayB_upd_d :std_ulogic; +signal ex4_xuop_wayB_upd_q :std_ulogic; +signal ex4_wayB_val_d :std_ulogic_vector(0 to 5); +signal ex4_wayB_val_q :std_ulogic_vector(0 to 5); +signal rel_wayB_val_stg_d :std_ulogic_vector(0 to 5); +signal rel_wayB_val_stg_q :std_ulogic_vector(0 to 5); +signal ex5_xuop_wayB_upd_d :std_ulogic; +signal ex5_xuop_wayB_upd_q :std_ulogic; +signal congr_cl_ex3_upd_wayB :std_ulogic; +signal congr_cl_ex4_upd_wayB :std_ulogic; +signal congr_cl_ex5_upd_wayB :std_ulogic; +signal congr_cl_m_upd_wayB_d :std_ulogic; +signal congr_cl_m_upd_wayB_q :std_ulogic; +signal ex3_cClass_wayB_hit :std_ulogic; +signal wayB_later_stg_pri :std_ulogic_vector(0 to 5); +signal wayB_early_stg_pri :std_ulogic_vector(0 to 5); +signal wayB_stg_val :std_ulogic_vector(0 to 5); +signal wayB_stg_val_b :std_ulogic_vector(0 to 5); +signal rel_wayB_later_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayB_early_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayB_stg_val :std_ulogic_vector(0 to 5); +signal rel_wayB_stg_val_b :std_ulogic_vector(0 to 5); +signal wayB_early_sel :std_ulogic; +signal wayB_late_sel :std_ulogic; +signal rel_wayB_early_sel :std_ulogic; +signal rel_wayB_late_sel :std_ulogic; +signal ex3_wayB_hit :std_ulogic; +signal rel_lost_watch_wayB_evict :std_ulogic_vector(0 to 3); +signal ex3_wayB_fxubyp_val_d :std_ulogic; +signal ex3_wayB_fxubyp_val_q :std_ulogic; +signal ex4_wayB_fxubyp_val_d :std_ulogic; +signal ex4_wayB_fxubyp_val_q :std_ulogic; +signal ex3_wayB_relbyp_val_d :std_ulogic; +signal ex3_wayB_relbyp_val_q :std_ulogic; +signal ex4_wayB_relbyp_val_d :std_ulogic; +signal ex4_wayB_relbyp_val_q :std_ulogic; +signal ex4_wayB_byp_sel :std_ulogic_vector(0 to 1); +signal rel24_wayB_fxubyp_val_d :std_ulogic; +signal rel24_wayB_fxubyp_val_q :std_ulogic; +signal rel24_wayB_relbyp_val_d :std_ulogic; +signal rel24_wayB_relbyp_val_q :std_ulogic; +signal rel24_wayB_byp_sel :std_ulogic_vector(0 to 1); +signal tagC_hit :std_ulogic; +signal tagC_hit_b :std_ulogic; +signal arr_wayC_val :std_ulogic_vector(0 to 5); +signal p0_arr_wayC_rd :std_ulogic_vector(0 to 5); +signal flush_wayC_d :std_ulogic_vector(0 to 5); +signal flush_wayC_q :std_ulogic_vector(0 to 5); +signal rel_wayC_clr :std_ulogic; +signal rel_wayC_set :std_ulogic; +signal rel_par_wC_clr :std_ulogic; +signal wayC_val :std_ulogic_vector(0 to 5); +signal wayC_val_b_q :std_ulogic_vector(0 to 5); +signal wayC_val_b1 :std_ulogic; +signal congr_cl_ex2_wayC_byp :std_ulogic_vector(1 to 7); +signal congr_cl_ex2_wayC_sel :std_ulogic_vector(2 to 7); +signal rel_arr_wayC_val :std_ulogic_vector(0 to 5); +signal p1_arr_wayC_rd :std_ulogic_vector(0 to 5); +signal rel_wayC_val_b_q :std_ulogic_vector(0 to 5); +signal rel_wayC_val :std_ulogic_vector(0 to 5); +signal congr_cl_rel13_wayC_byp :std_ulogic_vector(1 to 7); +signal congr_cl_rel13_wayC_sel :std_ulogic_vector(2 to 7); +signal reload_wayC_d :std_ulogic_vector(0 to 5); +signal reload_wayC_q :std_ulogic_vector(0 to 5); +signal reload_wayC_data_d :std_ulogic_vector(0 to 5); +signal reload_wayC_data_q :std_ulogic_vector(0 to 5); +signal reload_wayC_data2_d :std_ulogic_vector(0 to 5); +signal reload_wayC_data2_q :std_ulogic_vector(0 to 5); +signal reload_wayC_upd_d :std_ulogic; +signal reload_wayC_upd_q :std_ulogic; +signal reload_wayC_clr :std_ulogic; +signal reload_wayC_upd2_d :std_ulogic; +signal reload_wayC_upd2_q :std_ulogic; +signal reload_wayC_upd3_d :std_ulogic; +signal reload_wayC_upd3_q :std_ulogic; +signal reload_wayC :std_ulogic_vector(0 to 5); +signal binv_wayC_upd_d :std_ulogic; +signal binv_wayC_upd_q :std_ulogic; +signal binv_wayC_upd1 :std_ulogic; +signal binv_wayC_upd2_d :std_ulogic; +signal binv_wayC_upd2_q :std_ulogic; +signal binv_wayC_upd3_d :std_ulogic; +signal binv_wayC_upd3_q :std_ulogic; +signal flush_wayC_data1 :std_ulogic_vector(0 to 5); +signal flush_wayC_data_d :std_ulogic_vector(0 to 5); +signal flush_wayC_data_q :std_ulogic_vector(0 to 5); +signal flush_wayC_data2_d :std_ulogic_vector(0 to 5); +signal flush_wayC_data2_q :std_ulogic_vector(0 to 5); +signal xu_op_hit_wayC_b :std_ulogic; +signal xu_op_hit_wayC :std_ulogic; +signal xu_op_hit_wayC_dly_b :std_ulogic; +signal clr_val_wayC :std_ulogic; +signal upd_lck_wayC :std_ulogic_vector(0 to 1); +signal inval_clr_lck_wC_d :std_ulogic; +signal inval_clr_lck_wC_q :std_ulogic; +signal perr_way_det_wayC :std_ulogic; +signal perr_wayC_watch_lost :std_ulogic_vector(0 to 3); +signal wayC_watch_value :std_ulogic; +signal ex4_lost_wayC :std_ulogic_vector(0 to 3); +signal ex3_xuop_lost_watch_wayC :std_ulogic; +signal ex3_xuop_wayC_upd :std_ulogic; +signal ex4_xuop_wayC_upd_d :std_ulogic; +signal ex4_xuop_wayC_upd_q :std_ulogic; +signal ex4_wayC_val_d :std_ulogic_vector(0 to 5); +signal ex4_wayC_val_q :std_ulogic_vector(0 to 5); +signal rel_wayC_val_stg_d :std_ulogic_vector(0 to 5); +signal rel_wayC_val_stg_q :std_ulogic_vector(0 to 5); +signal ex5_xuop_wayC_upd_d :std_ulogic; +signal ex5_xuop_wayC_upd_q :std_ulogic; +signal congr_cl_ex3_upd_wayC :std_ulogic; +signal congr_cl_ex4_upd_wayC :std_ulogic; +signal congr_cl_ex5_upd_wayC :std_ulogic; +signal congr_cl_m_upd_wayC_d :std_ulogic; +signal congr_cl_m_upd_wayC_q :std_ulogic; +signal ex3_cClass_wayC_hit :std_ulogic; +signal wayC_later_stg_pri :std_ulogic_vector(0 to 5); +signal wayC_early_stg_pri :std_ulogic_vector(0 to 5); +signal wayC_stg_val :std_ulogic_vector(0 to 5); +signal wayC_stg_val_b :std_ulogic_vector(0 to 5); +signal rel_wayC_later_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayC_early_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayC_stg_val :std_ulogic_vector(0 to 5); +signal rel_wayC_stg_val_b :std_ulogic_vector(0 to 5); +signal wayC_early_sel :std_ulogic; +signal wayC_late_sel :std_ulogic; +signal rel_wayC_early_sel :std_ulogic; +signal rel_wayC_late_sel :std_ulogic; +signal ex3_wayC_hit :std_ulogic; +signal rel_lost_watch_wayC_evict :std_ulogic_vector(0 to 3); +signal ex3_wayC_fxubyp_val_d :std_ulogic; +signal ex3_wayC_fxubyp_val_q :std_ulogic; +signal ex4_wayC_fxubyp_val_d :std_ulogic; +signal ex4_wayC_fxubyp_val_q :std_ulogic; +signal ex3_wayC_relbyp_val_d :std_ulogic; +signal ex3_wayC_relbyp_val_q :std_ulogic; +signal ex4_wayC_relbyp_val_d :std_ulogic; +signal ex4_wayC_relbyp_val_q :std_ulogic; +signal ex4_wayC_byp_sel :std_ulogic_vector(0 to 1); +signal rel24_wayC_fxubyp_val_d :std_ulogic; +signal rel24_wayC_fxubyp_val_q :std_ulogic; +signal rel24_wayC_relbyp_val_d :std_ulogic; +signal rel24_wayC_relbyp_val_q :std_ulogic; +signal rel24_wayC_byp_sel :std_ulogic_vector(0 to 1); +signal tagD_hit :std_ulogic; +signal tagD_hit_b :std_ulogic; +signal arr_wayD_val :std_ulogic_vector(0 to 5); +signal p0_arr_wayD_rd :std_ulogic_vector(0 to 5); +signal flush_wayD_d :std_ulogic_vector(0 to 5); +signal flush_wayD_q :std_ulogic_vector(0 to 5); +signal rel_wayD_clr :std_ulogic; +signal rel_wayD_set :std_ulogic; +signal rel_par_wD_clr :std_ulogic; +signal wayD_val :std_ulogic_vector(0 to 5); +signal wayD_val_b_q :std_ulogic_vector(0 to 5); +signal wayD_val_b1 :std_ulogic; +signal congr_cl_ex2_wayD_byp :std_ulogic_vector(1 to 7); +signal congr_cl_ex2_wayD_sel :std_ulogic_vector(2 to 7); +signal rel_arr_wayD_val :std_ulogic_vector(0 to 5); +signal p1_arr_wayD_rd :std_ulogic_vector(0 to 5); +signal rel_wayD_val_b_q :std_ulogic_vector(0 to 5); +signal rel_wayD_val :std_ulogic_vector(0 to 5); +signal congr_cl_rel13_wayD_byp :std_ulogic_vector(1 to 7); +signal congr_cl_rel13_wayD_sel :std_ulogic_vector(2 to 7); +signal reload_wayD_d :std_ulogic_vector(0 to 5); +signal reload_wayD_q :std_ulogic_vector(0 to 5); +signal reload_wayD_data_d :std_ulogic_vector(0 to 5); +signal reload_wayD_data_q :std_ulogic_vector(0 to 5); +signal reload_wayD_data2_d :std_ulogic_vector(0 to 5); +signal reload_wayD_data2_q :std_ulogic_vector(0 to 5); +signal reload_wayD_upd_d :std_ulogic; +signal reload_wayD_upd_q :std_ulogic; +signal reload_wayD_clr :std_ulogic; +signal reload_wayD_upd2_d :std_ulogic; +signal reload_wayD_upd2_q :std_ulogic; +signal reload_wayD_upd3_d :std_ulogic; +signal reload_wayD_upd3_q :std_ulogic; +signal reload_wayD :std_ulogic_vector(0 to 5); +signal binv_wayD_upd_d :std_ulogic; +signal binv_wayD_upd_q :std_ulogic; +signal binv_wayD_upd1 :std_ulogic; +signal binv_wayD_upd2_d :std_ulogic; +signal binv_wayD_upd2_q :std_ulogic; +signal binv_wayD_upd3_d :std_ulogic; +signal binv_wayD_upd3_q :std_ulogic; +signal flush_wayD_data1 :std_ulogic_vector(0 to 5); +signal flush_wayD_data_d :std_ulogic_vector(0 to 5); +signal flush_wayD_data_q :std_ulogic_vector(0 to 5); +signal flush_wayD_data2_d :std_ulogic_vector(0 to 5); +signal flush_wayD_data2_q :std_ulogic_vector(0 to 5); +signal xu_op_hit_wayD_b :std_ulogic; +signal xu_op_hit_wayD :std_ulogic; +signal xu_op_hit_wayD_dly_b :std_ulogic; +signal clr_val_wayD :std_ulogic; +signal upd_lck_wayD :std_ulogic_vector(0 to 1); +signal inval_clr_lck_wD_d :std_ulogic; +signal inval_clr_lck_wD_q :std_ulogic; +signal perr_way_det_wayD :std_ulogic; +signal perr_wayD_watch_lost :std_ulogic_vector(0 to 3); +signal wayD_watch_value :std_ulogic; +signal ex4_lost_wayD :std_ulogic_vector(0 to 3); +signal ex3_xuop_lost_watch_wayD :std_ulogic; +signal ex3_xuop_wayD_upd :std_ulogic; +signal ex4_xuop_wayD_upd_d :std_ulogic; +signal ex4_xuop_wayD_upd_q :std_ulogic; +signal ex4_wayD_val_d :std_ulogic_vector(0 to 5); +signal ex4_wayD_val_q :std_ulogic_vector(0 to 5); +signal rel_wayD_val_stg_d :std_ulogic_vector(0 to 5); +signal rel_wayD_val_stg_q :std_ulogic_vector(0 to 5); +signal ex5_xuop_wayD_upd_d :std_ulogic; +signal ex5_xuop_wayD_upd_q :std_ulogic; +signal congr_cl_ex3_upd_wayD :std_ulogic; +signal congr_cl_ex4_upd_wayD :std_ulogic; +signal congr_cl_ex5_upd_wayD :std_ulogic; +signal congr_cl_m_upd_wayD_d :std_ulogic; +signal congr_cl_m_upd_wayD_q :std_ulogic; +signal ex3_cClass_wayD_hit :std_ulogic; +signal wayD_later_stg_pri :std_ulogic_vector(0 to 5); +signal wayD_early_stg_pri :std_ulogic_vector(0 to 5); +signal wayD_stg_val :std_ulogic_vector(0 to 5); +signal wayD_stg_val_b :std_ulogic_vector(0 to 5); +signal rel_wayD_later_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayD_early_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayD_stg_val :std_ulogic_vector(0 to 5); +signal rel_wayD_stg_val_b :std_ulogic_vector(0 to 5); +signal wayD_early_sel :std_ulogic; +signal wayD_late_sel :std_ulogic; +signal rel_wayD_early_sel :std_ulogic; +signal rel_wayD_late_sel :std_ulogic; +signal ex3_wayD_hit :std_ulogic; +signal rel_lost_watch_wayD_evict :std_ulogic_vector(0 to 3); +signal ex3_wayD_fxubyp_val_d :std_ulogic; +signal ex3_wayD_fxubyp_val_q :std_ulogic; +signal ex4_wayD_fxubyp_val_d :std_ulogic; +signal ex4_wayD_fxubyp_val_q :std_ulogic; +signal ex3_wayD_relbyp_val_d :std_ulogic; +signal ex3_wayD_relbyp_val_q :std_ulogic; +signal ex4_wayD_relbyp_val_d :std_ulogic; +signal ex4_wayD_relbyp_val_q :std_ulogic; +signal ex4_wayD_byp_sel :std_ulogic_vector(0 to 1); +signal rel24_wayD_fxubyp_val_d :std_ulogic; +signal rel24_wayD_fxubyp_val_q :std_ulogic; +signal rel24_wayD_relbyp_val_d :std_ulogic; +signal rel24_wayD_relbyp_val_q :std_ulogic; +signal rel24_wayD_byp_sel :std_ulogic_vector(0 to 1); +signal tagE_hit :std_ulogic; +signal tagE_hit_b :std_ulogic; +signal arr_wayE_val :std_ulogic_vector(0 to 5); +signal p0_arr_wayE_rd :std_ulogic_vector(0 to 5); +signal flush_wayE_d :std_ulogic_vector(0 to 5); +signal flush_wayE_q :std_ulogic_vector(0 to 5); +signal rel_wayE_clr :std_ulogic; +signal rel_wayE_set :std_ulogic; +signal rel_par_wE_clr :std_ulogic; +signal wayE_val :std_ulogic_vector(0 to 5); +signal wayE_val_b_q :std_ulogic_vector(0 to 5); +signal wayE_val_b1 :std_ulogic; +signal congr_cl_ex2_wayE_byp :std_ulogic_vector(1 to 7); +signal congr_cl_ex2_wayE_sel :std_ulogic_vector(2 to 7); +signal rel_arr_wayE_val :std_ulogic_vector(0 to 5); +signal p1_arr_wayE_rd :std_ulogic_vector(0 to 5); +signal rel_wayE_val_b_q :std_ulogic_vector(0 to 5); +signal rel_wayE_val :std_ulogic_vector(0 to 5); +signal congr_cl_rel13_wayE_byp :std_ulogic_vector(1 to 7); +signal congr_cl_rel13_wayE_sel :std_ulogic_vector(2 to 7); +signal reload_wayE_d :std_ulogic_vector(0 to 5); +signal reload_wayE_q :std_ulogic_vector(0 to 5); +signal reload_wayE_data_d :std_ulogic_vector(0 to 5); +signal reload_wayE_data_q :std_ulogic_vector(0 to 5); +signal reload_wayE_data2_d :std_ulogic_vector(0 to 5); +signal reload_wayE_data2_q :std_ulogic_vector(0 to 5); +signal reload_wayE_upd_d :std_ulogic; +signal reload_wayE_upd_q :std_ulogic; +signal reload_wayE_clr :std_ulogic; +signal reload_wayE_upd2_d :std_ulogic; +signal reload_wayE_upd2_q :std_ulogic; +signal reload_wayE_upd3_d :std_ulogic; +signal reload_wayE_upd3_q :std_ulogic; +signal reload_wayE :std_ulogic_vector(0 to 5); +signal binv_wayE_upd_d :std_ulogic; +signal binv_wayE_upd_q :std_ulogic; +signal binv_wayE_upd1 :std_ulogic; +signal binv_wayE_upd2_d :std_ulogic; +signal binv_wayE_upd2_q :std_ulogic; +signal binv_wayE_upd3_d :std_ulogic; +signal binv_wayE_upd3_q :std_ulogic; +signal flush_wayE_data1 :std_ulogic_vector(0 to 5); +signal flush_wayE_data_d :std_ulogic_vector(0 to 5); +signal flush_wayE_data_q :std_ulogic_vector(0 to 5); +signal flush_wayE_data2_d :std_ulogic_vector(0 to 5); +signal flush_wayE_data2_q :std_ulogic_vector(0 to 5); +signal xu_op_hit_wayE_b :std_ulogic; +signal xu_op_hit_wayE :std_ulogic; +signal xu_op_hit_wayE_dly_b :std_ulogic; +signal clr_val_wayE :std_ulogic; +signal upd_lck_wayE :std_ulogic_vector(0 to 1); +signal inval_clr_lck_wE_d :std_ulogic; +signal inval_clr_lck_wE_q :std_ulogic; +signal perr_way_det_wayE :std_ulogic; +signal perr_wayE_watch_lost :std_ulogic_vector(0 to 3); +signal wayE_watch_value :std_ulogic; +signal ex4_lost_wayE :std_ulogic_vector(0 to 3); +signal ex3_xuop_lost_watch_wayE :std_ulogic; +signal ex3_xuop_wayE_upd :std_ulogic; +signal ex4_xuop_wayE_upd_d :std_ulogic; +signal ex4_xuop_wayE_upd_q :std_ulogic; +signal ex4_wayE_val_d :std_ulogic_vector(0 to 5); +signal ex4_wayE_val_q :std_ulogic_vector(0 to 5); +signal rel_wayE_val_stg_d :std_ulogic_vector(0 to 5); +signal rel_wayE_val_stg_q :std_ulogic_vector(0 to 5); +signal ex5_xuop_wayE_upd_d :std_ulogic; +signal ex5_xuop_wayE_upd_q :std_ulogic; +signal congr_cl_ex3_upd_wayE :std_ulogic; +signal congr_cl_ex4_upd_wayE :std_ulogic; +signal congr_cl_ex5_upd_wayE :std_ulogic; +signal congr_cl_m_upd_wayE_d :std_ulogic; +signal congr_cl_m_upd_wayE_q :std_ulogic; +signal ex3_cClass_wayE_hit :std_ulogic; +signal wayE_later_stg_pri :std_ulogic_vector(0 to 5); +signal wayE_early_stg_pri :std_ulogic_vector(0 to 5); +signal wayE_stg_val :std_ulogic_vector(0 to 5); +signal wayE_stg_val_b :std_ulogic_vector(0 to 5); +signal rel_wayE_later_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayE_early_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayE_stg_val :std_ulogic_vector(0 to 5); +signal rel_wayE_stg_val_b :std_ulogic_vector(0 to 5); +signal wayE_early_sel :std_ulogic; +signal wayE_late_sel :std_ulogic; +signal rel_wayE_early_sel :std_ulogic; +signal rel_wayE_late_sel :std_ulogic; +signal ex3_wayE_hit :std_ulogic; +signal rel_lost_watch_wayE_evict :std_ulogic_vector(0 to 3); +signal ex3_wayE_fxubyp_val_d :std_ulogic; +signal ex3_wayE_fxubyp_val_q :std_ulogic; +signal ex4_wayE_fxubyp_val_d :std_ulogic; +signal ex4_wayE_fxubyp_val_q :std_ulogic; +signal ex3_wayE_relbyp_val_d :std_ulogic; +signal ex3_wayE_relbyp_val_q :std_ulogic; +signal ex4_wayE_relbyp_val_d :std_ulogic; +signal ex4_wayE_relbyp_val_q :std_ulogic; +signal ex4_wayE_byp_sel :std_ulogic_vector(0 to 1); +signal rel24_wayE_fxubyp_val_d :std_ulogic; +signal rel24_wayE_fxubyp_val_q :std_ulogic; +signal rel24_wayE_relbyp_val_d :std_ulogic; +signal rel24_wayE_relbyp_val_q :std_ulogic; +signal rel24_wayE_byp_sel :std_ulogic_vector(0 to 1); +signal tagF_hit :std_ulogic; +signal tagF_hit_b :std_ulogic; +signal arr_wayF_val :std_ulogic_vector(0 to 5); +signal p0_arr_wayF_rd :std_ulogic_vector(0 to 5); +signal flush_wayF_d :std_ulogic_vector(0 to 5); +signal flush_wayF_q :std_ulogic_vector(0 to 5); +signal rel_wayF_clr :std_ulogic; +signal rel_wayF_set :std_ulogic; +signal rel_par_wF_clr :std_ulogic; +signal wayF_val :std_ulogic_vector(0 to 5); +signal wayF_val_b_q :std_ulogic_vector(0 to 5); +signal wayF_val_b1 :std_ulogic; +signal congr_cl_ex2_wayF_byp :std_ulogic_vector(1 to 7); +signal congr_cl_ex2_wayF_sel :std_ulogic_vector(2 to 7); +signal rel_arr_wayF_val :std_ulogic_vector(0 to 5); +signal p1_arr_wayF_rd :std_ulogic_vector(0 to 5); +signal rel_wayF_val_b_q :std_ulogic_vector(0 to 5); +signal rel_wayF_val :std_ulogic_vector(0 to 5); +signal congr_cl_rel13_wayF_byp :std_ulogic_vector(1 to 7); +signal congr_cl_rel13_wayF_sel :std_ulogic_vector(2 to 7); +signal reload_wayF_d :std_ulogic_vector(0 to 5); +signal reload_wayF_q :std_ulogic_vector(0 to 5); +signal reload_wayF_data_d :std_ulogic_vector(0 to 5); +signal reload_wayF_data_q :std_ulogic_vector(0 to 5); +signal reload_wayF_data2_d :std_ulogic_vector(0 to 5); +signal reload_wayF_data2_q :std_ulogic_vector(0 to 5); +signal reload_wayF_upd_d :std_ulogic; +signal reload_wayF_upd_q :std_ulogic; +signal reload_wayF_clr :std_ulogic; +signal reload_wayF_upd2_d :std_ulogic; +signal reload_wayF_upd2_q :std_ulogic; +signal reload_wayF_upd3_d :std_ulogic; +signal reload_wayF_upd3_q :std_ulogic; +signal reload_wayF :std_ulogic_vector(0 to 5); +signal binv_wayF_upd_d :std_ulogic; +signal binv_wayF_upd_q :std_ulogic; +signal binv_wayF_upd1 :std_ulogic; +signal binv_wayF_upd2_d :std_ulogic; +signal binv_wayF_upd2_q :std_ulogic; +signal binv_wayF_upd3_d :std_ulogic; +signal binv_wayF_upd3_q :std_ulogic; +signal flush_wayF_data1 :std_ulogic_vector(0 to 5); +signal flush_wayF_data_d :std_ulogic_vector(0 to 5); +signal flush_wayF_data_q :std_ulogic_vector(0 to 5); +signal flush_wayF_data2_d :std_ulogic_vector(0 to 5); +signal flush_wayF_data2_q :std_ulogic_vector(0 to 5); +signal xu_op_hit_wayF_b :std_ulogic; +signal xu_op_hit_wayF :std_ulogic; +signal xu_op_hit_wayF_dly_b :std_ulogic; +signal clr_val_wayF :std_ulogic; +signal upd_lck_wayF :std_ulogic_vector(0 to 1); +signal inval_clr_lck_wF_d :std_ulogic; +signal inval_clr_lck_wF_q :std_ulogic; +signal perr_way_det_wayF :std_ulogic; +signal perr_wayF_watch_lost :std_ulogic_vector(0 to 3); +signal wayF_watch_value :std_ulogic; +signal ex4_lost_wayF :std_ulogic_vector(0 to 3); +signal ex3_xuop_lost_watch_wayF :std_ulogic; +signal ex3_xuop_wayF_upd :std_ulogic; +signal ex4_xuop_wayF_upd_d :std_ulogic; +signal ex4_xuop_wayF_upd_q :std_ulogic; +signal ex4_wayF_val_d :std_ulogic_vector(0 to 5); +signal ex4_wayF_val_q :std_ulogic_vector(0 to 5); +signal rel_wayF_val_stg_d :std_ulogic_vector(0 to 5); +signal rel_wayF_val_stg_q :std_ulogic_vector(0 to 5); +signal ex5_xuop_wayF_upd_d :std_ulogic; +signal ex5_xuop_wayF_upd_q :std_ulogic; +signal congr_cl_ex3_upd_wayF :std_ulogic; +signal congr_cl_ex4_upd_wayF :std_ulogic; +signal congr_cl_ex5_upd_wayF :std_ulogic; +signal congr_cl_m_upd_wayF_d :std_ulogic; +signal congr_cl_m_upd_wayF_q :std_ulogic; +signal ex3_cClass_wayF_hit :std_ulogic; +signal wayF_later_stg_pri :std_ulogic_vector(0 to 5); +signal wayF_early_stg_pri :std_ulogic_vector(0 to 5); +signal wayF_stg_val :std_ulogic_vector(0 to 5); +signal wayF_stg_val_b :std_ulogic_vector(0 to 5); +signal rel_wayF_later_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayF_early_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayF_stg_val :std_ulogic_vector(0 to 5); +signal rel_wayF_stg_val_b :std_ulogic_vector(0 to 5); +signal wayF_early_sel :std_ulogic; +signal wayF_late_sel :std_ulogic; +signal rel_wayF_early_sel :std_ulogic; +signal rel_wayF_late_sel :std_ulogic; +signal ex3_wayF_hit :std_ulogic; +signal rel_lost_watch_wayF_evict :std_ulogic_vector(0 to 3); +signal ex3_wayF_fxubyp_val_d :std_ulogic; +signal ex3_wayF_fxubyp_val_q :std_ulogic; +signal ex4_wayF_fxubyp_val_d :std_ulogic; +signal ex4_wayF_fxubyp_val_q :std_ulogic; +signal ex3_wayF_relbyp_val_d :std_ulogic; +signal ex3_wayF_relbyp_val_q :std_ulogic; +signal ex4_wayF_relbyp_val_d :std_ulogic; +signal ex4_wayF_relbyp_val_q :std_ulogic; +signal ex4_wayF_byp_sel :std_ulogic_vector(0 to 1); +signal rel24_wayF_fxubyp_val_d :std_ulogic; +signal rel24_wayF_fxubyp_val_q :std_ulogic; +signal rel24_wayF_relbyp_val_d :std_ulogic; +signal rel24_wayF_relbyp_val_q :std_ulogic; +signal rel24_wayF_byp_sel :std_ulogic_vector(0 to 1); +signal tagG_hit :std_ulogic; +signal tagG_hit_b :std_ulogic; +signal arr_wayG_val :std_ulogic_vector(0 to 5); +signal p0_arr_wayG_rd :std_ulogic_vector(0 to 5); +signal flush_wayG_d :std_ulogic_vector(0 to 5); +signal flush_wayG_q :std_ulogic_vector(0 to 5); +signal rel_wayG_clr :std_ulogic; +signal rel_wayG_set :std_ulogic; +signal rel_par_wG_clr :std_ulogic; +signal wayG_val :std_ulogic_vector(0 to 5); +signal wayG_val_b_q :std_ulogic_vector(0 to 5); +signal wayG_val_b1 :std_ulogic; +signal congr_cl_ex2_wayG_byp :std_ulogic_vector(1 to 7); +signal congr_cl_ex2_wayG_sel :std_ulogic_vector(2 to 7); +signal rel_arr_wayG_val :std_ulogic_vector(0 to 5); +signal p1_arr_wayG_rd :std_ulogic_vector(0 to 5); +signal rel_wayG_val_b_q :std_ulogic_vector(0 to 5); +signal rel_wayG_val :std_ulogic_vector(0 to 5); +signal congr_cl_rel13_wayG_byp :std_ulogic_vector(1 to 7); +signal congr_cl_rel13_wayG_sel :std_ulogic_vector(2 to 7); +signal reload_wayG_d :std_ulogic_vector(0 to 5); +signal reload_wayG_q :std_ulogic_vector(0 to 5); +signal reload_wayG_data_d :std_ulogic_vector(0 to 5); +signal reload_wayG_data_q :std_ulogic_vector(0 to 5); +signal reload_wayG_data2_d :std_ulogic_vector(0 to 5); +signal reload_wayG_data2_q :std_ulogic_vector(0 to 5); +signal reload_wayG_upd_d :std_ulogic; +signal reload_wayG_upd_q :std_ulogic; +signal reload_wayG_clr :std_ulogic; +signal reload_wayG_upd2_d :std_ulogic; +signal reload_wayG_upd2_q :std_ulogic; +signal reload_wayG_upd3_d :std_ulogic; +signal reload_wayG_upd3_q :std_ulogic; +signal reload_wayG :std_ulogic_vector(0 to 5); +signal binv_wayG_upd_d :std_ulogic; +signal binv_wayG_upd_q :std_ulogic; +signal binv_wayG_upd1 :std_ulogic; +signal binv_wayG_upd2_d :std_ulogic; +signal binv_wayG_upd2_q :std_ulogic; +signal binv_wayG_upd3_d :std_ulogic; +signal binv_wayG_upd3_q :std_ulogic; +signal flush_wayG_data1 :std_ulogic_vector(0 to 5); +signal flush_wayG_data_d :std_ulogic_vector(0 to 5); +signal flush_wayG_data_q :std_ulogic_vector(0 to 5); +signal flush_wayG_data2_d :std_ulogic_vector(0 to 5); +signal flush_wayG_data2_q :std_ulogic_vector(0 to 5); +signal xu_op_hit_wayG_b :std_ulogic; +signal xu_op_hit_wayG :std_ulogic; +signal xu_op_hit_wayG_dly_b :std_ulogic; +signal clr_val_wayG :std_ulogic; +signal upd_lck_wayG :std_ulogic_vector(0 to 1); +signal inval_clr_lck_wG_d :std_ulogic; +signal inval_clr_lck_wG_q :std_ulogic; +signal perr_way_det_wayG :std_ulogic; +signal perr_wayG_watch_lost :std_ulogic_vector(0 to 3); +signal wayG_watch_value :std_ulogic; +signal ex4_lost_wayG :std_ulogic_vector(0 to 3); +signal ex3_xuop_lost_watch_wayG :std_ulogic; +signal ex3_xuop_wayG_upd :std_ulogic; +signal ex4_xuop_wayG_upd_d :std_ulogic; +signal ex4_xuop_wayG_upd_q :std_ulogic; +signal ex4_wayG_val_d :std_ulogic_vector(0 to 5); +signal ex4_wayG_val_q :std_ulogic_vector(0 to 5); +signal rel_wayG_val_stg_d :std_ulogic_vector(0 to 5); +signal rel_wayG_val_stg_q :std_ulogic_vector(0 to 5); +signal ex5_xuop_wayG_upd_d :std_ulogic; +signal ex5_xuop_wayG_upd_q :std_ulogic; +signal congr_cl_ex3_upd_wayG :std_ulogic; +signal congr_cl_ex4_upd_wayG :std_ulogic; +signal congr_cl_ex5_upd_wayG :std_ulogic; +signal congr_cl_m_upd_wayG_d :std_ulogic; +signal congr_cl_m_upd_wayG_q :std_ulogic; +signal ex3_cClass_wayG_hit :std_ulogic; +signal wayG_later_stg_pri :std_ulogic_vector(0 to 5); +signal wayG_early_stg_pri :std_ulogic_vector(0 to 5); +signal wayG_stg_val :std_ulogic_vector(0 to 5); +signal wayG_stg_val_b :std_ulogic_vector(0 to 5); +signal rel_wayG_later_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayG_early_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayG_stg_val :std_ulogic_vector(0 to 5); +signal rel_wayG_stg_val_b :std_ulogic_vector(0 to 5); +signal wayG_early_sel :std_ulogic; +signal wayG_late_sel :std_ulogic; +signal rel_wayG_early_sel :std_ulogic; +signal rel_wayG_late_sel :std_ulogic; +signal ex3_wayG_hit :std_ulogic; +signal rel_lost_watch_wayG_evict :std_ulogic_vector(0 to 3); +signal ex3_wayG_fxubyp_val_d :std_ulogic; +signal ex3_wayG_fxubyp_val_q :std_ulogic; +signal ex4_wayG_fxubyp_val_d :std_ulogic; +signal ex4_wayG_fxubyp_val_q :std_ulogic; +signal ex3_wayG_relbyp_val_d :std_ulogic; +signal ex3_wayG_relbyp_val_q :std_ulogic; +signal ex4_wayG_relbyp_val_d :std_ulogic; +signal ex4_wayG_relbyp_val_q :std_ulogic; +signal ex4_wayG_byp_sel :std_ulogic_vector(0 to 1); +signal rel24_wayG_fxubyp_val_d :std_ulogic; +signal rel24_wayG_fxubyp_val_q :std_ulogic; +signal rel24_wayG_relbyp_val_d :std_ulogic; +signal rel24_wayG_relbyp_val_q :std_ulogic; +signal rel24_wayG_byp_sel :std_ulogic_vector(0 to 1); +signal tagH_hit :std_ulogic; +signal tagH_hit_b :std_ulogic; +signal arr_wayH_val :std_ulogic_vector(0 to 5); +signal p0_arr_wayH_rd :std_ulogic_vector(0 to 5); +signal flush_wayH_d :std_ulogic_vector(0 to 5); +signal flush_wayH_q :std_ulogic_vector(0 to 5); +signal rel_wayH_clr :std_ulogic; +signal rel_wayH_set :std_ulogic; +signal rel_par_wH_clr :std_ulogic; +signal wayH_val :std_ulogic_vector(0 to 5); +signal wayH_val_b_q :std_ulogic_vector(0 to 5); +signal wayH_val_b1 :std_ulogic; +signal congr_cl_ex2_wayH_byp :std_ulogic_vector(1 to 7); +signal congr_cl_ex2_wayH_sel :std_ulogic_vector(2 to 7); +signal rel_arr_wayH_val :std_ulogic_vector(0 to 5); +signal p1_arr_wayH_rd :std_ulogic_vector(0 to 5); +signal rel_wayH_val_b_q :std_ulogic_vector(0 to 5); +signal rel_wayH_val :std_ulogic_vector(0 to 5); +signal congr_cl_rel13_wayH_byp :std_ulogic_vector(1 to 7); +signal congr_cl_rel13_wayH_sel :std_ulogic_vector(2 to 7); +signal reload_wayH_d :std_ulogic_vector(0 to 5); +signal reload_wayH_q :std_ulogic_vector(0 to 5); +signal reload_wayH_data_d :std_ulogic_vector(0 to 5); +signal reload_wayH_data_q :std_ulogic_vector(0 to 5); +signal reload_wayH_data2_d :std_ulogic_vector(0 to 5); +signal reload_wayH_data2_q :std_ulogic_vector(0 to 5); +signal reload_wayH_upd_d :std_ulogic; +signal reload_wayH_upd_q :std_ulogic; +signal reload_wayH_clr :std_ulogic; +signal reload_wayH_upd2_d :std_ulogic; +signal reload_wayH_upd2_q :std_ulogic; +signal reload_wayH_upd3_d :std_ulogic; +signal reload_wayH_upd3_q :std_ulogic; +signal reload_wayH :std_ulogic_vector(0 to 5); +signal binv_wayH_upd_d :std_ulogic; +signal binv_wayH_upd_q :std_ulogic; +signal binv_wayH_upd1 :std_ulogic; +signal binv_wayH_upd2_d :std_ulogic; +signal binv_wayH_upd2_q :std_ulogic; +signal binv_wayH_upd3_d :std_ulogic; +signal binv_wayH_upd3_q :std_ulogic; +signal flush_wayH_data1 :std_ulogic_vector(0 to 5); +signal flush_wayH_data_d :std_ulogic_vector(0 to 5); +signal flush_wayH_data_q :std_ulogic_vector(0 to 5); +signal flush_wayH_data2_d :std_ulogic_vector(0 to 5); +signal flush_wayH_data2_q :std_ulogic_vector(0 to 5); +signal xu_op_hit_wayH_b :std_ulogic; +signal xu_op_hit_wayH :std_ulogic; +signal xu_op_hit_wayH_dly_b :std_ulogic; +signal clr_val_wayH :std_ulogic; +signal upd_lck_wayH :std_ulogic_vector(0 to 1); +signal inval_clr_lck_wH_d :std_ulogic; +signal inval_clr_lck_wH_q :std_ulogic; +signal perr_way_det_wayH :std_ulogic; +signal perr_wayH_watch_lost :std_ulogic_vector(0 to 3); +signal wayH_watch_value :std_ulogic; +signal ex4_lost_wayH :std_ulogic_vector(0 to 3); +signal ex3_xuop_lost_watch_wayH :std_ulogic; +signal ex3_xuop_wayH_upd :std_ulogic; +signal ex4_xuop_wayH_upd_d :std_ulogic; +signal ex4_xuop_wayH_upd_q :std_ulogic; +signal ex4_wayH_val_d :std_ulogic_vector(0 to 5); +signal ex4_wayH_val_q :std_ulogic_vector(0 to 5); +signal rel_wayH_val_stg_d :std_ulogic_vector(0 to 5); +signal rel_wayH_val_stg_q :std_ulogic_vector(0 to 5); +signal ex5_xuop_wayH_upd_d :std_ulogic; +signal ex5_xuop_wayH_upd_q :std_ulogic; +signal congr_cl_ex3_upd_wayH :std_ulogic; +signal congr_cl_ex4_upd_wayH :std_ulogic; +signal congr_cl_ex5_upd_wayH :std_ulogic; +signal congr_cl_m_upd_wayH_d :std_ulogic; +signal congr_cl_m_upd_wayH_q :std_ulogic; +signal ex3_cClass_wayH_hit :std_ulogic; +signal wayH_later_stg_pri :std_ulogic_vector(0 to 5); +signal wayH_early_stg_pri :std_ulogic_vector(0 to 5); +signal wayH_stg_val :std_ulogic_vector(0 to 5); +signal wayH_stg_val_b :std_ulogic_vector(0 to 5); +signal rel_wayH_later_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayH_early_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayH_stg_val :std_ulogic_vector(0 to 5); +signal rel_wayH_stg_val_b :std_ulogic_vector(0 to 5); +signal wayH_early_sel :std_ulogic; +signal wayH_late_sel :std_ulogic; +signal rel_wayH_early_sel :std_ulogic; +signal rel_wayH_late_sel :std_ulogic; +signal ex3_wayH_hit :std_ulogic; +signal rel_lost_watch_wayH_evict :std_ulogic_vector(0 to 3); +signal ex3_wayH_fxubyp_val_d :std_ulogic; +signal ex3_wayH_fxubyp_val_q :std_ulogic; +signal ex4_wayH_fxubyp_val_d :std_ulogic; +signal ex4_wayH_fxubyp_val_q :std_ulogic; +signal ex3_wayH_relbyp_val_d :std_ulogic; +signal ex3_wayH_relbyp_val_q :std_ulogic; +signal ex4_wayH_relbyp_val_d :std_ulogic; +signal ex4_wayH_relbyp_val_q :std_ulogic; +signal ex4_wayH_byp_sel :std_ulogic_vector(0 to 1); +signal rel24_wayH_fxubyp_val_d :std_ulogic; +signal rel24_wayH_fxubyp_val_q :std_ulogic; +signal rel24_wayH_relbyp_val_d :std_ulogic; +signal rel24_wayH_relbyp_val_q :std_ulogic; +signal rel24_wayH_byp_sel :std_ulogic_vector(0 to 1); +signal stm_upd_watchlost_tid0 :std_ulogic_vector(0 to 1); +signal upd_watch_tid0_wayA :std_ulogic_vector(0 to 1); +signal upd_watch_tid0_wayB :std_ulogic_vector(0 to 1); +signal upd_watch_tid0_wayC :std_ulogic_vector(0 to 1); +signal upd_watch_tid0_wayD :std_ulogic_vector(0 to 1); +signal upd_watch_tid0_wayE :std_ulogic_vector(0 to 1); +signal upd_watch_tid0_wayF :std_ulogic_vector(0 to 1); +signal upd_watch_tid0_wayG :std_ulogic_vector(0 to 1); +signal upd_watch_tid0_wayH :std_ulogic_vector(0 to 1); +signal stm_upd_watchlost_tid1 :std_ulogic_vector(0 to 1); +signal upd_watch_tid1_wayA :std_ulogic_vector(0 to 1); +signal upd_watch_tid1_wayB :std_ulogic_vector(0 to 1); +signal upd_watch_tid1_wayC :std_ulogic_vector(0 to 1); +signal upd_watch_tid1_wayD :std_ulogic_vector(0 to 1); +signal upd_watch_tid1_wayE :std_ulogic_vector(0 to 1); +signal upd_watch_tid1_wayF :std_ulogic_vector(0 to 1); +signal upd_watch_tid1_wayG :std_ulogic_vector(0 to 1); +signal upd_watch_tid1_wayH :std_ulogic_vector(0 to 1); +signal stm_upd_watchlost_tid2 :std_ulogic_vector(0 to 1); +signal upd_watch_tid2_wayA :std_ulogic_vector(0 to 1); +signal upd_watch_tid2_wayB :std_ulogic_vector(0 to 1); +signal upd_watch_tid2_wayC :std_ulogic_vector(0 to 1); +signal upd_watch_tid2_wayD :std_ulogic_vector(0 to 1); +signal upd_watch_tid2_wayE :std_ulogic_vector(0 to 1); +signal upd_watch_tid2_wayF :std_ulogic_vector(0 to 1); +signal upd_watch_tid2_wayG :std_ulogic_vector(0 to 1); +signal upd_watch_tid2_wayH :std_ulogic_vector(0 to 1); +signal stm_upd_watchlost_tid3 :std_ulogic_vector(0 to 1); +signal upd_watch_tid3_wayA :std_ulogic_vector(0 to 1); +signal upd_watch_tid3_wayB :std_ulogic_vector(0 to 1); +signal upd_watch_tid3_wayC :std_ulogic_vector(0 to 1); +signal upd_watch_tid3_wayD :std_ulogic_vector(0 to 1); +signal upd_watch_tid3_wayE :std_ulogic_vector(0 to 1); +signal upd_watch_tid3_wayF :std_ulogic_vector(0 to 1); +signal upd_watch_tid3_wayG :std_ulogic_vector(0 to 1); +signal upd_watch_tid3_wayH :std_ulogic_vector(0 to 1); +signal congr_cl_all_act_d :std_ulogic; +signal congr_cl_all_act_q :std_ulogic; +signal ex3_flush_cline_d :std_ulogic; +signal ex3_flush_cline_q :std_ulogic; +signal congr_cl_ex2_ex3_m :std_ulogic; +signal congr_cl_ex2_ex4_m :std_ulogic; +signal congr_cl_ex2_ex5_m :std_ulogic; +signal congr_cl_ex2_relu_m :std_ulogic; +signal congr_cl_ex2_relu_s_m :std_ulogic; +signal congr_cl_ex2_ex3_cmp_d :std_ulogic; +signal congr_cl_ex2_ex3_cmp_q :std_ulogic; +signal congr_cl_ex2_ex4_cmp_d :std_ulogic; +signal congr_cl_ex2_ex4_cmp_q :std_ulogic; +signal congr_cl_ex2_ex5_cmp_d :std_ulogic; +signal congr_cl_ex2_ex5_cmp_q :std_ulogic; +signal congr_cl_ex2_ex6_cmp_d :std_ulogic; +signal congr_cl_ex2_ex6_cmp_q :std_ulogic; +signal congr_cl_ex3_ex4_cmp_d :std_ulogic; +signal congr_cl_ex3_ex4_cmp_q :std_ulogic; +signal congr_cl_ex3_ex5_cmp_d :std_ulogic; +signal congr_cl_ex3_ex5_cmp_q :std_ulogic; +signal congr_cl_ex3_ex6_cmp_d :std_ulogic; +signal congr_cl_ex3_ex6_cmp_q :std_ulogic; +signal congr_cl_ex4_ex5_cmp_d :std_ulogic; +signal congr_cl_ex4_ex5_cmp_q :std_ulogic; +signal congr_cl_ex4_ex6_cmp_d :std_ulogic; +signal congr_cl_ex4_ex6_cmp_q :std_ulogic; +signal congr_cl_ex4_ex7_cmp_d :std_ulogic; +signal congr_cl_ex4_ex7_cmp_q :std_ulogic; +signal congr_cl_ex2_p0_cmp :std_ulogic; +signal congr_cl_ex2_relu_cmp_d :std_ulogic; +signal congr_cl_ex2_relu_cmp_q :std_ulogic; +signal congr_cl_ex2_relu_s_cmp_d :std_ulogic; +signal congr_cl_ex2_relu_s_cmp_q :std_ulogic; +signal congr_cl_ex2_rel_upd_cmp_d :std_ulogic; +signal congr_cl_ex2_rel_upd_cmp_q :std_ulogic; +signal congr_cl_ex2_p1_cmp :std_ulogic; +signal ex4_congr_cl_d :std_ulogic_vector(3 to 7); +signal ex4_congr_cl_q :std_ulogic_vector(3 to 7); +signal ex5_congr_cl_d :std_ulogic_vector(3 to 7); +signal ex5_congr_cl_q :std_ulogic_vector(3 to 7); +signal ex6_congr_cl_d :std_ulogic_vector(3 to 7); +signal ex6_congr_cl_q :std_ulogic_vector(3 to 7); +signal ex7_congr_cl_d :std_ulogic_vector(3 to 7); +signal ex7_congr_cl_q :std_ulogic_vector(3 to 7); +signal ex8_congr_cl_d :std_ulogic_vector(3 to 7); +signal ex8_congr_cl_q :std_ulogic_vector(3 to 7); +signal ex9_congr_cl_d :std_ulogic_vector(3 to 7); +signal ex9_congr_cl_q :std_ulogic_vector(3 to 7); +signal rel_early_congr_cl :std_ulogic_vector(3 to 7); +signal rel_congr_cl_d :std_ulogic_vector(3 to 7); +signal rel_congr_cl_q :std_ulogic_vector(3 to 7); +signal rel_val_stg1 :std_ulogic; +signal rel_val_stg2_d :std_ulogic; +signal rel_val_stg2_q :std_ulogic; +signal rel_val_clr_d :std_ulogic; +signal rel_val_clr_q :std_ulogic; +signal rel_val_stg3 :std_ulogic; +signal rel_val_stg4 :std_ulogic; +signal rel_val_stg4_d :std_ulogic; +signal rel_val_stg4_q :std_ulogic; +signal rel_binv_stg4_d :std_ulogic; +signal rel_binv_stg4_q :std_ulogic; +signal back_inval_stg2 :std_ulogic; +signal back_inval_stg3_d :std_ulogic; +signal back_inval_stg3_q :std_ulogic; +signal back_inval_stg4_d :std_ulogic; +signal back_inval_stg4_q :std_ulogic; +signal back_inval_stg5_d :std_ulogic; +signal back_inval_stg5_q :std_ulogic; +signal ex1_congr_cl :std_ulogic_vector(3 to 7); +signal ex2_congr_cl_d :std_ulogic_vector(3 to 7); +signal ex2_congr_cl_q :std_ulogic_vector(3 to 7); +signal ex3_congr_cl_d :std_ulogic_vector(3 to 7); +signal ex3_congr_cl_q :std_ulogic_vector(3 to 7); +signal rel24_congr_cl_d :std_ulogic_vector(3 to 7); +signal rel24_congr_cl_q :std_ulogic_vector(3 to 7); +signal p0_wren_d :std_ulogic; +signal p0_wren_q :std_ulogic; +signal p0_wren_cpy_d :std_ulogic; +signal p0_wren_cpy_q :std_ulogic; +signal p0_wren_stg_d :std_ulogic; +signal p0_wren_stg_q :std_ulogic; +signal p1_wren_d :std_ulogic; +signal p1_wren_q :std_ulogic; +signal p1_wren_cpy_d :std_ulogic; +signal p1_wren_cpy_q :std_ulogic; +signal congr_cl_rel13_ex3_m :std_ulogic; +signal congr_cl_rel13_ex4_m :std_ulogic; +signal congr_cl_rel13_ex5_m :std_ulogic; +signal congr_cl_rel13_relu_m :std_ulogic; +signal congr_cl_rel13_relu_s_m :std_ulogic; +signal congr_cl_rel13_ex3_cmp_d :std_ulogic; +signal congr_cl_rel13_ex3_cmp_q :std_ulogic; +signal congr_cl_rel13_ex4_cmp_d :std_ulogic; +signal congr_cl_rel13_ex4_cmp_q :std_ulogic; +signal congr_cl_rel13_ex5_cmp_d :std_ulogic; +signal congr_cl_rel13_ex5_cmp_q :std_ulogic; +signal congr_cl_rel13_ex6_cmp_d :std_ulogic; +signal congr_cl_rel13_ex6_cmp_q :std_ulogic; +signal congr_cl_rel13_p0_cmp :std_ulogic; +signal congr_cl_rel13_relu_cmp_d :std_ulogic; +signal congr_cl_rel13_relu_cmp_q :std_ulogic; +signal congr_cl_rel13_relu_s_cmp_d :std_ulogic; +signal congr_cl_rel13_relu_s_cmp_q :std_ulogic; +signal congr_cl_rel13_rel_upd_cmp_d :std_ulogic; +signal congr_cl_rel13_rel_upd_cmp_q :std_ulogic; +signal congr_cl_rel13_p1_cmp :std_ulogic; +signal ex3_c_acc :std_ulogic; +signal fxu_pipe_val :std_ulogic; +signal rel_set_val :std_ulogic; +signal ex3_store_instr_d :std_ulogic; +signal ex3_store_instr_q :std_ulogic; +signal ex3_lock_set_d :std_ulogic; +signal ex3_lock_set_q :std_ulogic; +signal ex4_lock_set_d :std_ulogic; +signal ex4_lock_set_q :std_ulogic; +signal ex5_lock_set_d :std_ulogic; +signal ex5_lock_set_q :std_ulogic; +signal ex3_lock_clr_d :std_ulogic; +signal ex3_lock_clr_q :std_ulogic; +signal clr_val :std_ulogic; +signal clr_lock :std_ulogic; +signal rel_val_set :std_ulogic; +signal rel_lock_set_d :std_ulogic; +signal rel_lock_set_q :std_ulogic; +signal rel_l1dump_cslc_d :std_ulogic; +signal rel_l1dump_cslc_q :std_ulogic; +signal rel_no_ovr_lock :std_ulogic; +signal rel_lock_lost :std_ulogic; +signal ex3_xuop_val :std_ulogic; +signal ex3_xuop_val_d :std_ulogic; +signal ex3_xuop_val_q :std_ulogic; +signal ex4_xuop_val :std_ulogic; +signal ex4_xuop_val_d :std_ulogic; +signal ex4_xuop_val_q :std_ulogic; +signal ex5_xuop_val :std_ulogic; +signal ex5_xuop_val_d :std_ulogic; +signal ex5_xuop_val_q :std_ulogic; +signal ex4_l_fld_b1_d :std_ulogic; +signal ex4_l_fld_b1_q :std_ulogic; +signal rel_in_progress :std_ulogic; +signal rel_in_progress_d :std_ulogic; +signal rel_in_progress_q :std_ulogic; +signal ex4_miss_q :std_ulogic; +signal ex4_way_hit_d :std_ulogic_vector(0 to 7); +signal ex4_way_hit_q :std_ulogic_vector(0 to 7); +signal ex5_way_hit_d :std_ulogic_vector(0 to 7); +signal ex5_way_hit_q :std_ulogic_vector(0 to 7); +signal ex6_way_hit_d :std_ulogic_vector(0 to 7); +signal ex6_way_hit_q :std_ulogic_vector(0 to 7); +signal ex7_way_hit_d :std_ulogic_vector(0 to 7); +signal ex7_way_hit_q :std_ulogic_vector(0 to 7); +signal ex8_way_hit_d :std_ulogic_vector(0 to 7); +signal ex8_way_hit_q :std_ulogic_vector(0 to 7); +signal ex9_way_hit_d :std_ulogic_vector(0 to 7); +signal ex9_way_hit_q :std_ulogic_vector(0 to 7); +signal dcpar_err_congr_cl :std_ulogic_vector(3 to 7); +signal dcpar_err_stg1_d :std_ulogic; +signal dcpar_err_stg1_q :std_ulogic; +signal dcpar_err_stg2_d :std_ulogic; +signal dcpar_err_stg2_q :std_ulogic; +signal dcpar_err_way_d :std_ulogic_vector(0 to 7); +signal dcpar_err_way_q :std_ulogic_vector(0 to 7); +signal dcpar_err_way_inval_d :std_ulogic_vector(0 to 7); +signal dcpar_err_way_inval_q :std_ulogic_vector(0 to 7); +signal dcpar_err_cntr_d :std_ulogic_vector(0 to 1); +signal dcpar_err_cntr_q :std_ulogic_vector(0 to 1); +signal dcpar_err_push :std_ulogic; +signal dcpar_err_rec_cmpl :std_ulogic; +signal dcpar_err_nxt_rec :std_ulogic; +signal dcpar_err_push_queue :std_ulogic; +signal dcpar_err_ind_sel :std_ulogic_vector(0 to 1); +signal dcpar_err_incr_val :std_ulogic; +signal dcpar_err_cntr_sel :std_ulogic_vector(0 to 1); +signal dcpar_err_nxt_cntr :std_ulogic_vector(0 to 1); +signal dcpar_err_rec_inprog :std_ulogic; +signal dcpar_err_ind_sel_d :std_ulogic_vector(0 to 1); +signal dcpar_err_ind_sel_q :std_ulogic_vector(0 to 1); +signal dcpar_err_push_queue_d :std_ulogic; +signal dcpar_err_push_queue_q :std_ulogic; +signal lock_finval :std_ulogic; +signal inval_clr_lck :std_ulogic; +signal xucr0_cslc_xuop_d :std_ulogic; +signal xucr0_cslc_xuop_q :std_ulogic; +signal xucr0_cslc_binv_d :std_ulogic; +signal xucr0_cslc_binv_q :std_ulogic; +signal dci_compl_d :std_ulogic; +signal dci_compl_q :std_ulogic; +signal dci_inval_all_d :std_ulogic; +signal dci_inval_all_q :std_ulogic; +signal inv2_val_d :std_ulogic; +signal inv2_val_q :std_ulogic; +signal perf_binv_hit :std_ulogic; +signal perf_lsu_evnts_d :std_ulogic_vector(0 to 4); +signal perf_lsu_evnts_q :std_ulogic_vector(0 to 4); +signal lock_flash_clear_d :std_ulogic; +signal lock_flash_clear_q :std_ulogic; +signal lock_flash_clear_val_d :std_ulogic; +signal lock_flash_clear_val_q :std_ulogic; +signal rel_port_upd_d :std_ulogic; +signal rel_port_upd_q :std_ulogic; +signal p1_upd_val :std_ulogic; +signal rel_port_wren_d :std_ulogic; +signal rel_port_wren_q :std_ulogic; +signal ex2_thrd_id_d :std_ulogic_vector(0 to 3); +signal ex2_thrd_id_q :std_ulogic_vector(0 to 3); +signal ex3_thrd_id_d :std_ulogic_vector(0 to 3); +signal ex3_thrd_id_q :std_ulogic_vector(0 to 3); +signal ex4_thrd_id_d :std_ulogic_vector(0 to 3); +signal ex4_thrd_id_q :std_ulogic_vector(0 to 3); +signal ex5_thrd_id_d :std_ulogic_vector(0 to 3); +signal ex5_thrd_id_q :std_ulogic_vector(0 to 3); +signal ex3_watch_set_d :std_ulogic; +signal ex3_watch_set_q :std_ulogic; +signal ex4_watch_set_d :std_ulogic; +signal ex4_watch_set_q :std_ulogic; +signal ex5_watch_set_d :std_ulogic; +signal ex5_watch_set_q :std_ulogic; +signal ex3_watch_clr_d :std_ulogic; +signal ex3_watch_clr_q :std_ulogic; +signal ex2_watch_clr_all :std_ulogic; +signal ex2_watch_clr_one :std_ulogic; +signal ex3_watch_clr_all_d :std_ulogic; +signal ex3_watch_clr_all_q :std_ulogic; +signal ex3_watch_clr_all :std_ulogic_vector(0 to 3); +signal ex4_watch_clr_all_d :std_ulogic_vector(0 to 3); +signal ex4_watch_clr_all_q :std_ulogic_vector(0 to 3); +signal ex5_watch_clr_all_d :std_ulogic_vector(0 to 3); +signal ex5_watch_clr_all_q :std_ulogic_vector(0 to 3); +signal ex6_watch_clr_all_d :std_ulogic_vector(0 to 3); +signal ex6_watch_clr_all_q :std_ulogic_vector(0 to 3); +signal ex5_watch_clr_all_val_d :std_ulogic; +signal ex5_watch_clr_all_val_q :std_ulogic; +signal rel_watch_set_d :std_ulogic; +signal rel_watch_set_q :std_ulogic; +signal rel_thrd_id_d :std_ulogic_vector(0 to 3); +signal rel_thrd_id_q :std_ulogic_vector(0 to 3); +signal rel_watch_lost :std_ulogic_vector(0 to 3); +signal lose_watch :std_ulogic_vector(0 to 3); +signal ex4_lose_watch_d :std_ulogic_vector(0 to 3); +signal ex4_lose_watch_q :std_ulogic_vector(0 to 3); +signal clr_watch :std_ulogic_vector(0 to 3); +signal set_watch :std_ulogic_vector(0 to 3); +signal ex4_curr_watch :std_ulogic; +signal stm_watchlost_sel :std_ulogic; +signal ex5_cr_watch_d :std_ulogic; +signal ex5_cr_watch_q :std_ulogic; +signal ex4_lost_watch :std_ulogic_vector(0 to 3); +signal ex4_lost_watch_upd :std_ulogic_vector(0 to 3); +signal ex5_lost_watch_upd_d :std_ulogic_vector(0 to 3); +signal ex5_lost_watch_upd_q :std_ulogic_vector(0 to 3); +signal ex4_watchlost_set_d :std_ulogic_vector(0 to 3); +signal ex4_watchlost_set_q :std_ulogic_vector(0 to 3); +signal ex5_watchlost_set_d :std_ulogic_vector(0 to 3); +signal ex5_watchlost_set_q :std_ulogic_vector(0 to 3); +signal rel_lost_watch_binv_d :std_ulogic_vector(0 to 3); +signal rel_lost_watch_binv_q :std_ulogic_vector(0 to 3); +signal rel_lost_watch_upd_d :std_ulogic_vector(0 to 3); +signal rel_lost_watch_upd_q :std_ulogic_vector(0 to 3); +signal rel_lost_watch_evict :std_ulogic_vector(0 to 3); +signal rel_lost_watch_evict_np :std_ulogic_vector(0 to 3); +signal lost_watch_evict_ovl_d :std_ulogic_vector(0 to 3); +signal lost_watch_evict_ovl_q :std_ulogic_vector(0 to 3); +signal lost_watch_binv :std_ulogic_vector(0 to 3); +signal lost_watch_inter_thrd_d :std_ulogic_vector(0 to 3); +signal lost_watch_inter_thrd_q :std_ulogic_vector(0 to 3); +signal stm_watchlost :std_ulogic_vector(0 to 3); +signal rel_watchlost_upd :std_ulogic_vector(0 to 3); +signal ex5_watchlost_upd :std_ulogic_vector(0 to 3); +signal stm_watchlost_state_d :std_ulogic_vector(0 to 3); +signal stm_watchlost_state_q :std_ulogic_vector(0 to 3); +signal ex5_xuop_p0_upd_d :std_ulogic; +signal ex5_xuop_p0_upd_q :std_ulogic; +signal rel_val_stg24 :std_ulogic; +signal rel_val_stgu_d :std_ulogic; +signal rel_val_stgu_q :std_ulogic; +signal relu_congr_cl_d :std_ulogic_vector(3 to 7); +signal relu_congr_cl_q :std_ulogic_vector(3 to 7); +signal relu_s_congr_cl_d :std_ulogic_vector(3 to 7); +signal relu_s_congr_cl_q :std_ulogic_vector(3 to 7); +signal ex3_thrd_m_d :std_ulogic; +signal ex3_thrd_m_q :std_ulogic; +signal ex4_thrd_m_d :std_ulogic; +signal ex4_thrd_m_q :std_ulogic; +signal ex5_thrd_m_d :std_ulogic; +signal ex5_thrd_m_q :std_ulogic; +signal ex6_thrd_m_d :std_ulogic; +signal ex6_thrd_m_q :std_ulogic; +signal ex7_ld_par_err_d :std_ulogic; +signal ex7_ld_par_err_q :std_ulogic; +signal ex8_ld_par_err_d :std_ulogic; +signal ex8_ld_par_err_q :std_ulogic; +signal ex9_ld_par_err_d :std_ulogic; +signal ex9_ld_par_err_q :std_ulogic; +signal ex6_ld_valid_d :std_ulogic; +signal ex6_ld_valid_q :std_ulogic; +signal ex7_ld_valid_d :std_ulogic; +signal ex7_ld_valid_q :std_ulogic; +signal ex8_ld_valid_d :std_ulogic; +signal ex8_ld_valid_q :std_ulogic; +signal ex9_ld_valid_d :std_ulogic; +signal ex9_ld_valid_q :std_ulogic; +signal inj_dir_multihit_b :std_ulogic; +signal inj_dir_multihit_d :std_ulogic; +signal inj_dir_multihit_q :std_ulogic; +signal binv1_ex1_stg_act :std_ulogic; +signal binv2_ex2_stg_act :std_ulogic; +signal binv3_ex3_stg_act :std_ulogic; +signal binv4_ex4_stg_act :std_ulogic; +signal binv5_ex5_stg_act :std_ulogic; +signal binv2_ex2_val_stg_act :std_ulogic; +signal binv3_ex3_val_stg_act :std_ulogic; +signal binv4_ex4_val_stg_act :std_ulogic; +signal binv5_ex5_val_stg_act :std_ulogic; +signal dcpar_err_stg1_act_d :std_ulogic; +signal dcpar_err_stg1_act_q :std_ulogic; +signal dcpar_err_stg2_act_d :std_ulogic; +signal dcpar_err_stg2_act_q :std_ulogic; +signal rel1_perr_stg_act :std_ulogic; +signal rel2_perr_stg_act :std_ulogic; +signal rel3_perr_stg_act_d :std_ulogic; +signal rel3_perr_stg_act_q :std_ulogic; +signal rel4_perr_stg_act_d :std_ulogic; +signal rel4_perr_stg_act_q :std_ulogic; +signal reload_way_clr_d :std_ulogic_vector(0 to 7); +signal reload_way_clr_q :std_ulogic_vector(0 to 7); +signal ex4_watchSet_coll_d :std_ulogic; +signal ex4_watchSet_coll_q :std_ulogic; +signal watchSet_rel_way_coll :std_ulogic_vector(0 to 7); +signal watchSet_rel_coll_val :std_ulogic_vector(0 to 3); +signal rel24_congr_cl_ex4_cmp_d :std_ulogic; +signal rel24_congr_cl_ex4_cmp_q :std_ulogic; +signal rel24_congr_cl_ex5_cmp_d :std_ulogic; +signal rel24_congr_cl_ex5_cmp_q :std_ulogic; +signal rel24_congr_cl_ex6_cmp_d :std_ulogic; +signal rel24_congr_cl_ex6_cmp_q :std_ulogic; +signal relu_congr_cl_ex5_cmp_d :std_ulogic; +signal relu_congr_cl_ex5_cmp_q :std_ulogic; +signal relu_congr_cl_ex6_cmp_d :std_ulogic; +signal relu_congr_cl_ex6_cmp_q :std_ulogic; +signal relu_congr_cl_ex7_cmp_d :std_ulogic; +signal relu_congr_cl_ex7_cmp_q :std_ulogic; +signal rel_ex5_watchSet_coll :std_ulogic; +signal rel_ex6_watchSet_coll :std_ulogic; +signal rel_ex7_watchSet_coll :std_ulogic; +signal rel_coll_val :std_ulogic; +signal relu_dir_data :std_ulogic_vector(2 to 5); +signal rel_pri_byp_sel :std_ulogic_vector(0 to 2); +signal rel_byp_dir_data :std_ulogic_vector(2 to 5); +signal rel_watchSet_coll_tid :std_ulogic_vector(0 to 3); +signal lost_watch_evict_val_d :std_ulogic_vector(0 to 3); +signal lost_watch_evict_val_q :std_ulogic_vector(0 to 3); +signal dcpar_err_lock_lost :std_ulogic_vector(0 to 7); +signal dirpar_err_lock_lost :std_ulogic_vector(0 to 7); +signal ex3_dir_perr_val :std_ulogic; +signal ex3_dir_multihit_val :std_ulogic; +signal ex4_dir_err_val_d :std_ulogic; +signal ex4_dir_err_val_q :std_ulogic; +signal ex5_dir_err_val_d :std_ulogic; +signal ex5_dir_err_val_q :std_ulogic; +signal ex6_dir_err_val_d :std_ulogic; +signal ex6_dir_err_val_q :std_ulogic; +signal derr2_stg_act_d :std_ulogic; +signal derr2_stg_act_q :std_ulogic; +signal derr3_stg_act_d :std_ulogic; +signal derr3_stg_act_q :std_ulogic; +signal derr4_stg_act_d :std_ulogic; +signal derr4_stg_act_q :std_ulogic; +signal derr5_stg_act_d :std_ulogic; +signal derr5_stg_act_q :std_ulogic; +signal ex4_err_det_way_d :std_ulogic_vector(0 to 7); +signal ex4_err_det_way_q :std_ulogic_vector(0 to 7); +signal ex4_perr_lck_lost_d :std_ulogic; +signal ex4_perr_lck_lost_q :std_ulogic; +signal ex4_perr_watch_lost_d :std_ulogic_vector(0 to 3); +signal ex4_perr_watch_lost_q :std_ulogic_vector(0 to 3); +signal dcperr_lock_lost_d :std_ulogic; +signal dcperr_lock_lost_q :std_ulogic; +signal ex4_dir_multihit_val_b_q :std_ulogic; +signal ex4_dir_multihit_val :std_ulogic; +signal binv4_ex4_lock_set :std_ulogic; +signal binv4_ex4_thrd_watch :std_ulogic_vector(0 to 3); +signal ex4_multihit_watch_lost :std_ulogic_vector(0 to 3); +signal ex4_multihit_lock_lost :std_ulogic; +signal ex3_watch_chk_d :std_ulogic; +signal ex3_watch_chk_q :std_ulogic; +signal ex4_watch_chk_d :std_ulogic; +signal ex4_watch_chk_q :std_ulogic; +signal ex5_watch_chk_d :std_ulogic; +signal ex5_watch_chk_q :std_ulogic; +signal ex5_watch_chk_cplt :std_ulogic; +signal ex5_watch_chk_succ :std_ulogic; +signal ex5_watch_dup_set :std_ulogic; +signal hit_and_01_b :std_ulogic; +signal hit_and_23_b :std_ulogic; +signal hit_and_45_b :std_ulogic; +signal hit_and_67_b :std_ulogic; +signal hit_or_01_b :std_ulogic; +signal hit_or_23_b :std_ulogic; +signal hit_or_45_b :std_ulogic; +signal hit_or_67_b :std_ulogic; +signal hit_or_13_b :std_ulogic; +signal hit_or_57_b :std_ulogic; +signal hit_or_0123 :std_ulogic; +signal hit_or_4567 :std_ulogic; +signal hit_or_1357 :std_ulogic; +signal hit_or_2367 :std_ulogic; +signal hit_and_0123 :std_ulogic; +signal hit_and_4567 :std_ulogic; +signal multi_hit_err2_0 :std_ulogic; +signal multi_hit_err2_1 :std_ulogic; +signal hit_or_01234567_b :std_ulogic; +signal ex3_dir_multihit_val_0 :std_ulogic; +signal ex3_dir_multihit_val_1 :std_ulogic; +signal ex3_dir_multihit_val_b :std_ulogic; +signal multi_hit_err3_b :std_ulogic_vector(0 to 2); +signal hit_enc_b :std_ulogic_vector(0 to 2); +signal ex3_l_fld_b1_d :std_ulogic; +signal ex3_l_fld_b1_q :std_ulogic; +signal binv4_ex4_way_upd :std_ulogic_vector(0 to 7); +signal binv5_ex5_way_upd :std_ulogic_vector(0 to 7); +signal binv6_ex6_way_upd :std_ulogic_vector(0 to 7); +signal binv7_ex7_way_upd_d :std_ulogic_vector(0 to 7); +signal binv7_ex7_way_upd_q :std_ulogic_vector(0 to 7); +signal binv4_ex4_dir_data :std_ulogic_vector(1 to 5); +signal binv5_ex5_dir_data_d :std_ulogic_vector(1 to 5); +signal binv5_ex5_dir_data_q :std_ulogic_vector(1 to 5); +signal binv6_ex6_dir_data_d :std_ulogic_vector(1 to 5); +signal binv6_ex6_dir_data_q :std_ulogic_vector(1 to 5); +signal binv7_ex7_dir_data_d :std_ulogic_vector(1 to 5); +signal binv7_ex7_dir_data_q :std_ulogic_vector(1 to 5); +signal binv4_inval_lck :std_ulogic; +signal binv4_inval_watch :std_ulogic_vector(0 to 3); +signal binv4_coll_val :std_ulogic; +signal binv4_ex5_coll :std_ulogic; +signal binv4_ex6_coll :std_ulogic; +signal binv4_ex7_coll :std_ulogic; +signal binv4_pri_byp_sel :std_ulogic_vector(0 to 2); +signal binv4_byp_dir_data :std_ulogic_vector(1 to 5); +signal binv5_inval_lock_val_d :std_ulogic; +signal binv5_inval_lock_val_q :std_ulogic; +signal binv5_inval_watch_val_d :std_ulogic_vector(0 to 3); +signal binv5_inval_watch_val_q :std_ulogic_vector(0 to 3); +signal binv5_ex5_lost_watch_upd :std_ulogic_vector(0 to 3); +signal dci_watch_lost :std_ulogic_vector(0 to 3); +signal ex3_xuop_upd_dir :std_ulogic; +signal binv3_ex3_xuop_upd :std_ulogic; +signal binv4_ex4_xuop_upd_d :std_ulogic; +signal binv4_ex4_xuop_upd_q :std_ulogic; +signal ex3_dir_acc_val :std_ulogic; +signal binv3_ex3_dir_val :std_ulogic; +signal binv4_ex4_dir_val_d :std_ulogic; +signal binv4_ex4_dir_val_q :std_ulogic; +signal ex3_l1hit :std_ulogic; +signal ex3_l1miss :std_ulogic; +signal ex4_snd_ld_l2_q :std_ulogic; +signal ex4_ldq_full_flush_b_q :std_ulogic; +signal rel_in_prog_stg1_d :std_ulogic; +signal rel_in_prog_stg1_q :std_ulogic; +signal rel_in_prog_stg2_d :std_ulogic; +signal rel_in_prog_stg2_q :std_ulogic; +signal rel_in_prog_stg3_d :std_ulogic; +signal rel_in_prog_stg3_q :std_ulogic; +signal rel_in_prog_stg4_d :std_ulogic; +signal rel_in_prog_stg4_q :std_ulogic; +signal rel_in_prog_stg5_d :std_ulogic; +signal rel_in_prog_stg5_q :std_ulogic; +signal ex4_instr_enc_d :std_ulogic_vector(0 to 3); +signal ex4_instr_enc_q :std_ulogic_vector(0 to 3); +signal ex4_wclr_all_val_d :std_ulogic; +signal ex4_wclr_all_val_q :std_ulogic; +signal ex5_wclr_all_val_d :std_ulogic; +signal ex5_wclr_all_val_q :std_ulogic; +signal ex6_wclr_all_val_d :std_ulogic; +signal ex6_wclr_all_val_q :std_ulogic; +signal ex3_wclr_all_upd_val :std_ulogic; +signal ex4_wclr_all_upd_val :std_ulogic; +signal ex5_wclr_all_upd_val :std_ulogic; +signal ex6_wclr_all_upd_val :std_ulogic; +signal ex3_wclr_all_upd_d :std_ulogic; +signal ex3_wclr_all_upd_q :std_ulogic; +signal ex4_n_lsu_ddmh_flush_b_d :std_ulogic_vector(0 to 3); +signal ex4_n_lsu_ddmh_flush_b_q :std_ulogic_vector(0 to 3); +signal ex3_xuop_up_addr_b :std_ulogic_vector(0 to 2); +signal rel_dcarr_addr_sel :std_ulogic_vector(0 to 2); +signal rel_dcarr_addr_sel_b :std_ulogic_vector(0 to 2); +signal dcarr_up_way_addr_q :std_ulogic_vector(0 to 2); +signal rel4_l1dump_val_q :std_ulogic; +signal rel4_l1dump_watch :std_ulogic; +signal lost_watch_l1dump :std_ulogic_vector(0 to 3); +signal my_lclk :clk_logic; +signal my_d1clk :std_ulogic; +signal my_d2clk :std_ulogic; +signal my_multihit_lclk :clk_logic; +signal my_multihit_d1clk :std_ulogic; +signal my_multihit_d2clk :std_ulogic; +signal my_ddmh_lclk :clk_logic; +signal my_ddmh_d1clk :std_ulogic; +signal my_ddmh_d2clk :std_ulogic; +signal ex4_miss_siv :std_ulogic; +signal ex4_miss_sov :std_ulogic; +signal my_spare0_lclk :clk_logic; +signal my_spare0_d1clk :std_ulogic; +signal my_spare0_d2clk :std_ulogic; +signal my_spare0_latches_d :std_ulogic_vector(0 to 16); +signal my_spare0_latches_q :std_ulogic_vector(0 to 16); +signal my_spare1_lclk :clk_logic; +signal my_spare1_d1clk :std_ulogic; +signal my_spare1_d2clk :std_ulogic; +signal my_spare1_latches_d :std_ulogic_vector(0 to 15); +signal my_spare1_latches_q :std_ulogic_vector(0 to 15); +signal tiup :std_ulogic; +signal siv :std_ulogic_vector(0 to scan_right); +signal sov :std_ulogic_vector(0 to scan_right); + BEGIN + +tiup <= '1'; +inv2_val_d <= inv1_val and not spr_xucr0_dcdis; +back_inval_stg2 <= inv2_val_q; +rel_val_stg1 <= rel1_val; +rel_val_stg3 <= rel3_val; +rel_set_val <= rel4_set_val; +lock_flash_clear_d <= xu_lsu_spr_xucr0_clfc; +lock_flash_clear_val_d <= lock_flash_clear_q; +dci_compl_d <= xu_lsu_dci; +dci_inval_all_d <= dci_compl_q; +lock_finval <= dci_inval_all_q or lock_flash_clear_val_q; +inj_dir_multihit_d <= pc_xu_inj_dcachedir_multihit; +ex3_l_fld_b1_d <= ex2_l_fld(1); +tagA_hit <= ex3_way_cmp_a; +rel_wayA_clr <= rel_way_clr_a; +rel_wayA_set <= rel_way_wen_a; +tagB_hit <= ex3_way_cmp_b; +rel_wayB_clr <= rel_way_clr_b; +rel_wayB_set <= rel_way_wen_b; +tagC_hit <= ex3_way_cmp_c; +rel_wayC_clr <= rel_way_clr_c; +rel_wayC_set <= rel_way_wen_c; +tagD_hit <= ex3_way_cmp_d; +rel_wayD_clr <= rel_way_clr_d; +rel_wayD_set <= rel_way_wen_d; +tagE_hit <= ex3_way_cmp_e; +rel_wayE_clr <= rel_way_clr_e; +rel_wayE_set <= rel_way_wen_e; +tagF_hit <= ex3_way_cmp_f; +rel_wayF_clr <= rel_way_clr_f; +rel_wayF_set <= rel_way_wen_f; +tagG_hit <= ex3_way_cmp_g; +rel_wayG_clr <= rel_way_clr_g; +rel_wayG_set <= rel_way_wen_g; +tagH_hit <= ex3_way_cmp_h; +rel_wayH_clr <= rel_way_clr_h; +rel_wayH_set <= rel_way_wen_h; +ex3_c_acc <= ex3_cache_en; +binv1_ex1_stg_act <= binv1_stg_act or ex1_stg_act; +binv2_ex2_stg_act <= binv2_stg_act or ex2_stg_act; +binv3_ex3_stg_act <= binv3_stg_act or ex3_stg_act; +binv4_ex4_stg_act <= binv4_stg_act or ex4_stg_act; +binv5_ex5_stg_act <= binv5_stg_act or ex5_stg_act; +binv2_ex2_val_stg_act <= derr2_stg_act_q or binv2_stg_act or ex2_stg_act; +binv3_ex3_val_stg_act <= derr3_stg_act_q or binv3_stg_act or ex3_stg_act; +binv4_ex4_val_stg_act <= derr4_stg_act_q or binv4_stg_act or ex4_stg_act; +binv5_ex5_val_stg_act <= derr5_stg_act_q or binv5_stg_act or ex5_stg_act; +rel1_perr_stg_act <= rel1_stg_act or dcpar_err_stg1_act_q; +rel2_perr_stg_act <= rel2_stg_act or dcpar_err_stg2_act_q; +rel3_perr_stg_act_d <= rel2_perr_stg_act; +rel4_perr_stg_act_d <= rel3_perr_stg_act_q; +ex1_congr_cl <= ex1_p_addr; +cl64size : if (cl_size=6) generate +begin + rel_early_congr_cl(3 TO 6) <= rel_addr_early(64-(dc_size-3) to 63-cl_size-1); +rel_early_congr_cl(7) <= rel_addr_early(63-cl_size) or spr_xucr0_cls; +end generate cl64size; +cl32size : if (cl_size=5) generate +begin + rel_early_congr_cl(3 TO 5) <= rel_addr_early(64-(dc_size-3) to 63-cl_size-2); +rel_early_congr_cl(6) <= rel_addr_early(63-cl_size-1) or spr_xucr0_cls; +rel_early_congr_cl(7) <= rel_addr_early(63-cl_size); +end generate cl32size; +ex2_congr_cl_d <= ex1_congr_cl; +ex3_congr_cl_d <= ex2_congr_cl_q; +ex4_congr_cl_d <= ex3_congr_cl_q; +ex5_congr_cl_d <= ex4_congr_cl_q; +ex6_congr_cl_d <= ex5_congr_cl_q; +with rel_in_progress select + rel_congr_cl_d <= rel_early_congr_cl when '1', + dcpar_err_congr_cl when others; +rel_val_stg2_d <= rel_val_stg1; +rel_val_clr_d <= rel_val_stg2_q or dcpar_err_stg2_q; +rel_val_stg4_d <= rel_val_stg3; +rel_val_stg4 <= rel_val_stg4_q and not rel4_recirc_val; +rel_val_set <= rel_val_stg4 and rel_set_val; +rel_binv_stg4_d <= rel_back_inval; +rel_lock_set_d <= rel_lock_en; +rel_l1dump_cslc_d <= rel_l1dump_cslc; +rel_no_ovr_lock <= rel_wayA_set or rel_wayB_set or rel_wayC_set or rel_wayD_set or + rel_wayE_set or rel_wayF_set or rel_wayG_set or rel_wayH_set; +rel_lock_lost <= rel_lock_set_q and rel_val_stg4 and rel_no_ovr_lock and rel_binv_stg4_q and not rel_set_val; +rel_watch_set_d <= rel_watch_en; +rel_thrd_id_d <= rel_thrd_id; +rel_watch_lost <= gate(rel_thrd_id_q, (rel_watch_set_q and rel_val_stg4 and rel_binv_stg4_q and not rel_set_val)); +rel_val_stg24 <= rel_val_stg2_q or rel_val_set or dcpar_err_stg2_q; +rel_val_stgu_d <= rel_val_stg24; +rel_port_wren_d <= rel_val_stgu_q; +rel_port_upd_d <= rel_val_stgu_q; +rel_in_prog_stg1_d <= ldq_rel1_early_v or ldq_rel3_early_v; +rel_in_prog_stg2_d <= rel_in_prog_stg1_q; +rel_in_prog_stg3_d <= rel_in_prog_stg2_q; +rel_in_prog_stg4_d <= rel_in_prog_stg3_q; +rel_in_prog_stg5_d <= rel_in_prog_stg4_q; +rel_in_progress <= ldq_rel1_early_v or ldq_rel3_early_v or rel_in_prog_stg1_q or rel_in_prog_stg2_q or + rel_in_prog_stg3_q or rel_in_prog_stg4_q or rel_in_prog_stg5_q; +rel_in_progress_d <= rel_in_progress; +back_inval_stg3_d <= back_inval_stg2; +back_inval_stg4_d <= back_inval_stg3_q; +back_inval_stg5_d <= back_inval_stg4_q; +ex2_thrd_id_d <= ex1_thrd_id; +ex3_store_instr_d <= ex2_store_instr and not ex2_stg_flush; +ex3_flush_cline_d <= ex2_is_inval_op and not ex2_stg_flush; +ex3_lock_set_d <= ex2_lock_set and not ex2_stg_flush; +ex4_lock_set_d <= ex3_lock_set_q and not ex3_stg_flush; +ex5_lock_set_d <= ex4_lock_set_q and not ex4_stg_flush; +ex3_lock_clr_d <= ex2_lock_clr and not ex2_stg_flush; +ex3_thrd_id_d <= ex2_thrd_id_q; +ex3_watch_set_d <= ex2_ldawx_instr and not ex2_stg_flush; +ex3_watch_clr_d <= ex2_wclr_instr and not ex2_stg_flush; +ex2_watch_clr_all <= ex2_wclr_instr and not ex2_l_fld(0); +ex2_watch_clr_one <= ex2_wclr_instr and ex2_l_fld(0); +ex3_watch_clr_all_d <= ex2_watch_clr_all and not ex2_stg_flush; +ex3_watch_chk_d <= ex2_wchk_val and not ex2_stg_flush; +ex3_xuop_val_d <= (ex2_lock_clr or ex2_lock_set or ex2_ldawx_instr or ex2_watch_clr_one or ex2_store_instr) and not ex2_stg_flush; +ex4_l_fld_b1_d <= ex3_l_fld_b1_q; +ex3_watch_clr_all <= gate(ex3_thrd_id_q, ex3_watch_clr_all_q); +ex4_wclr_all_val_d <= ex3_watch_clr_all_q and not ex3_stg_flush; +ex5_wclr_all_val_d <= ex4_wclr_all_val_q and not ex4_stg_flush; +ex6_wclr_all_val_d <= ex5_wclr_all_val_q and not ex5_stg_flush; +ex3_xuop_val <= ((ex3_xuop_val_q and ex3_c_acc) or ex3_flush_cline_q) and not spr_xucr0_dcdis; +ex4_xuop_val_d <= (ex3_xuop_val or ex3_watch_clr_all_q) and not ex3_stg_flush; +ex4_watch_clr_all_d <= gate(ex3_watch_clr_all, (not (ex3_stg_flush or spr_xucr0_dcdis))); +ex4_watch_chk_d <= ex3_watch_chk_q and not ex3_stg_flush; +ex4_watch_set_d <= ex3_watch_set_q and not ex3_stg_flush; +ex5_watch_set_d <= ex4_watch_set_q and not ex4_stg_flush; +ex3_xuop_upd_dir <= ex3_flush_cline_q or ex3_lock_clr_q or ex3_lock_set_q or ex3_watch_set_q or ex3_watch_clr_q; +binv3_ex3_xuop_upd <= back_inval_stg3_q or ex3_xuop_val; +binv4_ex4_xuop_upd_d <= binv3_ex3_xuop_upd or ((ex3_xuop_val or ex3_watch_clr_all_q) and not ex3_stg_flush); +ex3_dir_acc_val <= ex3_cache_acc and not ex3_watch_clr_all_q; +binv3_ex3_dir_val <= back_inval_stg3_q or ex3_dir_acc_val; +binv4_ex4_dir_val_d <= back_inval_stg3_q or (ex3_dir_acc_val and not ex3_stg_flush); +ex4_instr_enc_d(0) <= ex3_watch_clr_q; +ex4_instr_enc_d(1) <= back_inval_stg3_q or ex3_lock_set_q or ex3_lock_clr_q or ex3_watch_set_q; +ex4_instr_enc_d(2) <= back_inval_stg3_q or ex3_store_instr_q or ex3_watch_set_q; +ex4_instr_enc_d(3) <= back_inval_stg3_q or ex3_lock_clr_q or ex3_flush_cline_q or ex3_watch_clr_all_q; +ex4_xuop_val <= ex4_xuop_val_q and not ex4_stg_flush; +ex4_thrd_id_d <= ex3_thrd_id_q; +ex5_xuop_val_d <= ex4_xuop_val; +ex5_xuop_val <= ex5_xuop_val_q and not ex5_stg_flush; +ex5_xuop_p0_upd_d <= ex4_xuop_val; +ex5_watch_chk_d <= ex4_watch_chk_q and not ex4_stg_flush; +ex5_thrd_id_d <= ex4_thrd_id_q; +rel24_congr_cl_d <= rel_congr_cl_q; +relu_congr_cl_d <= rel24_congr_cl_q; +relu_s_congr_cl_d <= relu_congr_cl_q; +ex6_ld_valid_d <= ex5_load_op_hit and not ex5_stg_flush; +with ex2_congr_cl_q select + arr_wayA_val <= + congr_cl0_wA_q when "00000", + congr_cl1_wA_q when "00001", + congr_cl2_wA_q when "00010", + congr_cl3_wA_q when "00011", + congr_cl4_wA_q when "00100", + congr_cl5_wA_q when "00101", + congr_cl6_wA_q when "00110", + congr_cl7_wA_q when "00111", + congr_cl8_wA_q when "01000", + congr_cl9_wA_q when "01001", + congr_cl10_wA_q when "01010", + congr_cl11_wA_q when "01011", + congr_cl12_wA_q when "01100", + congr_cl13_wA_q when "01101", + congr_cl14_wA_q when "01110", + congr_cl15_wA_q when "01111", + congr_cl16_wA_q when "10000", + congr_cl17_wA_q when "10001", + congr_cl18_wA_q when "10010", + congr_cl19_wA_q when "10011", + congr_cl20_wA_q when "10100", + congr_cl21_wA_q when "10101", + congr_cl22_wA_q when "10110", + congr_cl23_wA_q when "10111", + congr_cl24_wA_q when "11000", + congr_cl25_wA_q when "11001", + congr_cl26_wA_q when "11010", + congr_cl27_wA_q when "11011", + congr_cl28_wA_q when "11100", + congr_cl29_wA_q when "11101", + congr_cl30_wA_q when "11110", + congr_cl31_wA_q when others; +p0_arr_wayA_rd <= arr_wayA_val; +with ex2_congr_cl_q select + arr_wayB_val <= + congr_cl0_wB_q when "00000", + congr_cl1_wB_q when "00001", + congr_cl2_wB_q when "00010", + congr_cl3_wB_q when "00011", + congr_cl4_wB_q when "00100", + congr_cl5_wB_q when "00101", + congr_cl6_wB_q when "00110", + congr_cl7_wB_q when "00111", + congr_cl8_wB_q when "01000", + congr_cl9_wB_q when "01001", + congr_cl10_wB_q when "01010", + congr_cl11_wB_q when "01011", + congr_cl12_wB_q when "01100", + congr_cl13_wB_q when "01101", + congr_cl14_wB_q when "01110", + congr_cl15_wB_q when "01111", + congr_cl16_wB_q when "10000", + congr_cl17_wB_q when "10001", + congr_cl18_wB_q when "10010", + congr_cl19_wB_q when "10011", + congr_cl20_wB_q when "10100", + congr_cl21_wB_q when "10101", + congr_cl22_wB_q when "10110", + congr_cl23_wB_q when "10111", + congr_cl24_wB_q when "11000", + congr_cl25_wB_q when "11001", + congr_cl26_wB_q when "11010", + congr_cl27_wB_q when "11011", + congr_cl28_wB_q when "11100", + congr_cl29_wB_q when "11101", + congr_cl30_wB_q when "11110", + congr_cl31_wB_q when others; +p0_arr_wayB_rd <= arr_wayB_val; +with ex2_congr_cl_q select + arr_wayC_val <= + congr_cl0_wC_q when "00000", + congr_cl1_wC_q when "00001", + congr_cl2_wC_q when "00010", + congr_cl3_wC_q when "00011", + congr_cl4_wC_q when "00100", + congr_cl5_wC_q when "00101", + congr_cl6_wC_q when "00110", + congr_cl7_wC_q when "00111", + congr_cl8_wC_q when "01000", + congr_cl9_wC_q when "01001", + congr_cl10_wC_q when "01010", + congr_cl11_wC_q when "01011", + congr_cl12_wC_q when "01100", + congr_cl13_wC_q when "01101", + congr_cl14_wC_q when "01110", + congr_cl15_wC_q when "01111", + congr_cl16_wC_q when "10000", + congr_cl17_wC_q when "10001", + congr_cl18_wC_q when "10010", + congr_cl19_wC_q when "10011", + congr_cl20_wC_q when "10100", + congr_cl21_wC_q when "10101", + congr_cl22_wC_q when "10110", + congr_cl23_wC_q when "10111", + congr_cl24_wC_q when "11000", + congr_cl25_wC_q when "11001", + congr_cl26_wC_q when "11010", + congr_cl27_wC_q when "11011", + congr_cl28_wC_q when "11100", + congr_cl29_wC_q when "11101", + congr_cl30_wC_q when "11110", + congr_cl31_wC_q when others; +p0_arr_wayC_rd <= arr_wayC_val; +with ex2_congr_cl_q select + arr_wayD_val <= + congr_cl0_wD_q when "00000", + congr_cl1_wD_q when "00001", + congr_cl2_wD_q when "00010", + congr_cl3_wD_q when "00011", + congr_cl4_wD_q when "00100", + congr_cl5_wD_q when "00101", + congr_cl6_wD_q when "00110", + congr_cl7_wD_q when "00111", + congr_cl8_wD_q when "01000", + congr_cl9_wD_q when "01001", + congr_cl10_wD_q when "01010", + congr_cl11_wD_q when "01011", + congr_cl12_wD_q when "01100", + congr_cl13_wD_q when "01101", + congr_cl14_wD_q when "01110", + congr_cl15_wD_q when "01111", + congr_cl16_wD_q when "10000", + congr_cl17_wD_q when "10001", + congr_cl18_wD_q when "10010", + congr_cl19_wD_q when "10011", + congr_cl20_wD_q when "10100", + congr_cl21_wD_q when "10101", + congr_cl22_wD_q when "10110", + congr_cl23_wD_q when "10111", + congr_cl24_wD_q when "11000", + congr_cl25_wD_q when "11001", + congr_cl26_wD_q when "11010", + congr_cl27_wD_q when "11011", + congr_cl28_wD_q when "11100", + congr_cl29_wD_q when "11101", + congr_cl30_wD_q when "11110", + congr_cl31_wD_q when others; +p0_arr_wayD_rd <= arr_wayD_val; +with ex2_congr_cl_q select + arr_wayE_val <= + congr_cl0_wE_q when "00000", + congr_cl1_wE_q when "00001", + congr_cl2_wE_q when "00010", + congr_cl3_wE_q when "00011", + congr_cl4_wE_q when "00100", + congr_cl5_wE_q when "00101", + congr_cl6_wE_q when "00110", + congr_cl7_wE_q when "00111", + congr_cl8_wE_q when "01000", + congr_cl9_wE_q when "01001", + congr_cl10_wE_q when "01010", + congr_cl11_wE_q when "01011", + congr_cl12_wE_q when "01100", + congr_cl13_wE_q when "01101", + congr_cl14_wE_q when "01110", + congr_cl15_wE_q when "01111", + congr_cl16_wE_q when "10000", + congr_cl17_wE_q when "10001", + congr_cl18_wE_q when "10010", + congr_cl19_wE_q when "10011", + congr_cl20_wE_q when "10100", + congr_cl21_wE_q when "10101", + congr_cl22_wE_q when "10110", + congr_cl23_wE_q when "10111", + congr_cl24_wE_q when "11000", + congr_cl25_wE_q when "11001", + congr_cl26_wE_q when "11010", + congr_cl27_wE_q when "11011", + congr_cl28_wE_q when "11100", + congr_cl29_wE_q when "11101", + congr_cl30_wE_q when "11110", + congr_cl31_wE_q when others; +p0_arr_wayE_rd <= arr_wayE_val; +with ex2_congr_cl_q select + arr_wayF_val <= + congr_cl0_wF_q when "00000", + congr_cl1_wF_q when "00001", + congr_cl2_wF_q when "00010", + congr_cl3_wF_q when "00011", + congr_cl4_wF_q when "00100", + congr_cl5_wF_q when "00101", + congr_cl6_wF_q when "00110", + congr_cl7_wF_q when "00111", + congr_cl8_wF_q when "01000", + congr_cl9_wF_q when "01001", + congr_cl10_wF_q when "01010", + congr_cl11_wF_q when "01011", + congr_cl12_wF_q when "01100", + congr_cl13_wF_q when "01101", + congr_cl14_wF_q when "01110", + congr_cl15_wF_q when "01111", + congr_cl16_wF_q when "10000", + congr_cl17_wF_q when "10001", + congr_cl18_wF_q when "10010", + congr_cl19_wF_q when "10011", + congr_cl20_wF_q when "10100", + congr_cl21_wF_q when "10101", + congr_cl22_wF_q when "10110", + congr_cl23_wF_q when "10111", + congr_cl24_wF_q when "11000", + congr_cl25_wF_q when "11001", + congr_cl26_wF_q when "11010", + congr_cl27_wF_q when "11011", + congr_cl28_wF_q when "11100", + congr_cl29_wF_q when "11101", + congr_cl30_wF_q when "11110", + congr_cl31_wF_q when others; +p0_arr_wayF_rd <= arr_wayF_val; +with ex2_congr_cl_q select + arr_wayG_val <= + congr_cl0_wG_q when "00000", + congr_cl1_wG_q when "00001", + congr_cl2_wG_q when "00010", + congr_cl3_wG_q when "00011", + congr_cl4_wG_q when "00100", + congr_cl5_wG_q when "00101", + congr_cl6_wG_q when "00110", + congr_cl7_wG_q when "00111", + congr_cl8_wG_q when "01000", + congr_cl9_wG_q when "01001", + congr_cl10_wG_q when "01010", + congr_cl11_wG_q when "01011", + congr_cl12_wG_q when "01100", + congr_cl13_wG_q when "01101", + congr_cl14_wG_q when "01110", + congr_cl15_wG_q when "01111", + congr_cl16_wG_q when "10000", + congr_cl17_wG_q when "10001", + congr_cl18_wG_q when "10010", + congr_cl19_wG_q when "10011", + congr_cl20_wG_q when "10100", + congr_cl21_wG_q when "10101", + congr_cl22_wG_q when "10110", + congr_cl23_wG_q when "10111", + congr_cl24_wG_q when "11000", + congr_cl25_wG_q when "11001", + congr_cl26_wG_q when "11010", + congr_cl27_wG_q when "11011", + congr_cl28_wG_q when "11100", + congr_cl29_wG_q when "11101", + congr_cl30_wG_q when "11110", + congr_cl31_wG_q when others; +p0_arr_wayG_rd <= arr_wayG_val; +with ex2_congr_cl_q select + arr_wayH_val <= + congr_cl0_wH_q when "00000", + congr_cl1_wH_q when "00001", + congr_cl2_wH_q when "00010", + congr_cl3_wH_q when "00011", + congr_cl4_wH_q when "00100", + congr_cl5_wH_q when "00101", + congr_cl6_wH_q when "00110", + congr_cl7_wH_q when "00111", + congr_cl8_wH_q when "01000", + congr_cl9_wH_q when "01001", + congr_cl10_wH_q when "01010", + congr_cl11_wH_q when "01011", + congr_cl12_wH_q when "01100", + congr_cl13_wH_q when "01101", + congr_cl14_wH_q when "01110", + congr_cl15_wH_q when "01111", + congr_cl16_wH_q when "10000", + congr_cl17_wH_q when "10001", + congr_cl18_wH_q when "10010", + congr_cl19_wH_q when "10011", + congr_cl20_wH_q when "10100", + congr_cl21_wH_q when "10101", + congr_cl22_wH_q when "10110", + congr_cl23_wH_q when "10111", + congr_cl24_wH_q when "11000", + congr_cl25_wH_q when "11001", + congr_cl26_wH_q when "11010", + congr_cl27_wH_q when "11011", + congr_cl28_wH_q when "11100", + congr_cl29_wH_q when "11101", + congr_cl30_wH_q when "11110", + congr_cl31_wH_q when others; +p0_arr_wayH_rd <= arr_wayH_val; +congr_cl_ex2_ex3_cmp_d <= (ex1_congr_cl = ex2_congr_cl_q); +congr_cl_ex2_ex4_cmp_d <= (ex1_congr_cl = ex3_congr_cl_q); +congr_cl_ex2_ex5_cmp_d <= (ex1_congr_cl = ex4_congr_cl_q); +congr_cl_ex2_ex6_cmp_d <= (ex1_congr_cl = ex5_congr_cl_q); +congr_cl_ex2_relu_cmp_d <= (ex1_congr_cl = rel24_congr_cl_q); +congr_cl_ex2_relu_s_cmp_d <= (ex1_congr_cl = relu_congr_cl_q); +congr_cl_ex2_rel_upd_cmp_d <= (ex1_congr_cl = relu_s_congr_cl_q); +congr_cl_ex2_p0_cmp <= congr_cl_ex2_ex6_cmp_q and p0_wren_cpy_q; +congr_cl_ex2_p1_cmp <= congr_cl_ex2_rel_upd_cmp_q and p1_wren_cpy_q; +ex3_thrd_m_d <= (ex1_thrd_id = ex2_thrd_id_q); +ex4_thrd_m_d <= (ex1_thrd_id = ex3_thrd_id_q); +ex5_thrd_m_d <= (ex1_thrd_id = ex4_thrd_id_q); +ex6_thrd_m_d <= (ex1_thrd_id = ex5_thrd_id_q); +congr_cl_ex2_ex3_m <= congr_cl_ex2_ex3_cmp_q and ((ex3_xuop_val and ex3_thrd_m_q) or back_inval_stg3_q) and not inv2_val_q; +congr_cl_ex2_ex4_m <= congr_cl_ex2_ex4_cmp_q and ((ex4_xuop_val_q and ex4_thrd_m_q) or back_inval_stg4_q) and not inv2_val_q; +congr_cl_ex2_ex5_m <= congr_cl_ex2_ex5_cmp_q and ((ex5_xuop_p0_upd_q and ex5_thrd_m_q) or back_inval_stg5_q) and not inv2_val_q; +congr_cl_ex2_relu_m <= congr_cl_ex2_relu_cmp_q and rel_val_stgu_q; +congr_cl_ex2_relu_s_m <= congr_cl_ex2_relu_s_cmp_q and p1_upd_val; +congr_cl_ex2_wayA_byp(1) <= congr_cl_ex2_ex3_m and ex3_wayA_hit; +congr_cl_ex2_wayA_byp(2) <= congr_cl_ex2_relu_m and reload_wayA_upd_q; +congr_cl_ex2_wayA_byp(3) <= congr_cl_ex2_ex4_m and binv_wayA_upd_q; +congr_cl_ex2_wayA_byp(4) <= congr_cl_ex2_relu_s_m and reload_wayA_upd2_q; +congr_cl_ex2_wayA_byp(5) <= congr_cl_ex2_ex5_m and binv_wayA_upd2_q; +congr_cl_ex2_wayA_byp(6) <= congr_cl_ex2_p1_cmp and reload_wayA_upd3_q; +congr_cl_ex2_wayA_byp(7) <= congr_cl_ex2_p0_cmp and binv_wayA_upd3_q; +ex3_wayA_fxubyp_val_d <= congr_cl_ex2_wayA_byp(1) or congr_cl_ex2_wayA_byp(3) or + congr_cl_ex2_wayA_byp(5) or congr_cl_ex2_wayA_byp(7); +ex3_wayA_relbyp_val_d <= congr_cl_ex2_wayA_byp(2) or congr_cl_ex2_wayA_byp(4) or + congr_cl_ex2_wayA_byp(6); +ex4_wayA_fxubyp_val_d <= ex3_wayA_fxubyp_val_q; +ex4_wayA_relbyp_val_d <= ex3_wayA_relbyp_val_q; +ex4_wayA_byp_sel <= ex4_wayA_fxubyp_val_q & ex4_wayA_relbyp_val_q; +congr_cl_ex2_wayA_sel(2) <= congr_cl_ex2_wayA_byp(2); +congr_cl_ex2_wayA_sel(3) <= congr_cl_ex2_wayA_byp(3) and not congr_cl_ex2_wayA_byp(2); +congr_cl_ex2_wayA_sel(4) <= congr_cl_ex2_wayA_byp(4) and not or_reduce(congr_cl_ex2_wayA_byp(2 to 3)); +congr_cl_ex2_wayA_sel(5) <= congr_cl_ex2_wayA_byp(5) and not or_reduce(congr_cl_ex2_wayA_byp(2 to 4)); +congr_cl_ex2_wayA_sel(6) <= congr_cl_ex2_wayA_byp(6) and not or_reduce(congr_cl_ex2_wayA_byp(2 to 5)); +congr_cl_ex2_wayA_sel(7) <= congr_cl_ex2_wayA_byp(7) and not or_reduce(congr_cl_ex2_wayA_byp(2 to 6)); +wayA_late_sel <= or_reduce(congr_cl_ex2_wayA_byp(2 to 7)); +wayA_later_stg_pri <= gate(p0_arr_wayA_rd, not wayA_late_sel) or + gate(reload_wayA_q, congr_cl_ex2_wayA_sel(2)) or + gate(flush_wayA_q, congr_cl_ex2_wayA_sel(3)) or + gate(reload_wayA_data_q, congr_cl_ex2_wayA_sel(4)) or + gate(flush_wayA_data_q, congr_cl_ex2_wayA_sel(5)) or + gate(reload_wayA_data2_q, congr_cl_ex2_wayA_sel(6)) or + gate(flush_wayA_data2_q, congr_cl_ex2_wayA_sel(7)); +wayA_early_sel <= congr_cl_ex2_wayA_byp(1); +wayA_early_stg_pri <= flush_wayA_d; +wayA_stg_val <= (others=>(wayA_early_sel)); +wayA_stg_val_b <= (others=>(not(wayA_early_sel))); +wayA_val(0 TO 1) <= not wayA_val_b_q(0 to 1); +wayA_val(2 TO 5) <= not wayA_val_b_q(2 to 5); +wayA_val_b1 <= not wayA_val(0); +congr_cl_ex2_wayB_byp(1) <= congr_cl_ex2_ex3_m and ex3_wayB_hit; +congr_cl_ex2_wayB_byp(2) <= congr_cl_ex2_relu_m and reload_wayB_upd_q; +congr_cl_ex2_wayB_byp(3) <= congr_cl_ex2_ex4_m and binv_wayB_upd_q; +congr_cl_ex2_wayB_byp(4) <= congr_cl_ex2_relu_s_m and reload_wayB_upd2_q; +congr_cl_ex2_wayB_byp(5) <= congr_cl_ex2_ex5_m and binv_wayB_upd2_q; +congr_cl_ex2_wayB_byp(6) <= congr_cl_ex2_p1_cmp and reload_wayB_upd3_q; +congr_cl_ex2_wayB_byp(7) <= congr_cl_ex2_p0_cmp and binv_wayB_upd3_q; +ex3_wayB_fxubyp_val_d <= congr_cl_ex2_wayB_byp(1) or congr_cl_ex2_wayB_byp(3) or + congr_cl_ex2_wayB_byp(5) or congr_cl_ex2_wayB_byp(7); +ex3_wayB_relbyp_val_d <= congr_cl_ex2_wayB_byp(2) or congr_cl_ex2_wayB_byp(4) or + congr_cl_ex2_wayB_byp(6); +ex4_wayB_fxubyp_val_d <= ex3_wayB_fxubyp_val_q; +ex4_wayB_relbyp_val_d <= ex3_wayB_relbyp_val_q; +ex4_wayB_byp_sel <= ex4_wayB_fxubyp_val_q & ex4_wayB_relbyp_val_q; +congr_cl_ex2_wayB_sel(2) <= congr_cl_ex2_wayB_byp(2); +congr_cl_ex2_wayB_sel(3) <= congr_cl_ex2_wayB_byp(3) and not congr_cl_ex2_wayB_byp(2); +congr_cl_ex2_wayB_sel(4) <= congr_cl_ex2_wayB_byp(4) and not or_reduce(congr_cl_ex2_wayB_byp(2 to 3)); +congr_cl_ex2_wayB_sel(5) <= congr_cl_ex2_wayB_byp(5) and not or_reduce(congr_cl_ex2_wayB_byp(2 to 4)); +congr_cl_ex2_wayB_sel(6) <= congr_cl_ex2_wayB_byp(6) and not or_reduce(congr_cl_ex2_wayB_byp(2 to 5)); +congr_cl_ex2_wayB_sel(7) <= congr_cl_ex2_wayB_byp(7) and not or_reduce(congr_cl_ex2_wayB_byp(2 to 6)); +wayB_late_sel <= or_reduce(congr_cl_ex2_wayB_byp(2 to 7)); +wayB_later_stg_pri <= gate(p0_arr_wayB_rd, not wayB_late_sel) or + gate(reload_wayB_q, congr_cl_ex2_wayB_sel(2)) or + gate(flush_wayB_q, congr_cl_ex2_wayB_sel(3)) or + gate(reload_wayB_data_q, congr_cl_ex2_wayB_sel(4)) or + gate(flush_wayB_data_q, congr_cl_ex2_wayB_sel(5)) or + gate(reload_wayB_data2_q, congr_cl_ex2_wayB_sel(6)) or + gate(flush_wayB_data2_q, congr_cl_ex2_wayB_sel(7)); +wayB_early_sel <= congr_cl_ex2_wayB_byp(1); +wayB_early_stg_pri <= flush_wayB_d; +wayB_stg_val <= (others=>(wayB_early_sel)); +wayB_stg_val_b <= (others=>(not(wayB_early_sel))); +wayB_val(0 TO 1) <= not wayB_val_b_q(0 to 1); +wayB_val(2 TO 5) <= not wayB_val_b_q(2 to 5); +wayB_val_b1 <= not wayB_val(0); +congr_cl_ex2_wayC_byp(1) <= congr_cl_ex2_ex3_m and ex3_wayC_hit; +congr_cl_ex2_wayC_byp(2) <= congr_cl_ex2_relu_m and reload_wayC_upd_q; +congr_cl_ex2_wayC_byp(3) <= congr_cl_ex2_ex4_m and binv_wayC_upd_q; +congr_cl_ex2_wayC_byp(4) <= congr_cl_ex2_relu_s_m and reload_wayC_upd2_q; +congr_cl_ex2_wayC_byp(5) <= congr_cl_ex2_ex5_m and binv_wayC_upd2_q; +congr_cl_ex2_wayC_byp(6) <= congr_cl_ex2_p1_cmp and reload_wayC_upd3_q; +congr_cl_ex2_wayC_byp(7) <= congr_cl_ex2_p0_cmp and binv_wayC_upd3_q; +ex3_wayC_fxubyp_val_d <= congr_cl_ex2_wayC_byp(1) or congr_cl_ex2_wayC_byp(3) or + congr_cl_ex2_wayC_byp(5) or congr_cl_ex2_wayC_byp(7); +ex3_wayC_relbyp_val_d <= congr_cl_ex2_wayC_byp(2) or congr_cl_ex2_wayC_byp(4) or + congr_cl_ex2_wayC_byp(6); +ex4_wayC_fxubyp_val_d <= ex3_wayC_fxubyp_val_q; +ex4_wayC_relbyp_val_d <= ex3_wayC_relbyp_val_q; +ex4_wayC_byp_sel <= ex4_wayC_fxubyp_val_q & ex4_wayC_relbyp_val_q; +congr_cl_ex2_wayC_sel(2) <= congr_cl_ex2_wayC_byp(2); +congr_cl_ex2_wayC_sel(3) <= congr_cl_ex2_wayC_byp(3) and not congr_cl_ex2_wayC_byp(2); +congr_cl_ex2_wayC_sel(4) <= congr_cl_ex2_wayC_byp(4) and not or_reduce(congr_cl_ex2_wayC_byp(2 to 3)); +congr_cl_ex2_wayC_sel(5) <= congr_cl_ex2_wayC_byp(5) and not or_reduce(congr_cl_ex2_wayC_byp(2 to 4)); +congr_cl_ex2_wayC_sel(6) <= congr_cl_ex2_wayC_byp(6) and not or_reduce(congr_cl_ex2_wayC_byp(2 to 5)); +congr_cl_ex2_wayC_sel(7) <= congr_cl_ex2_wayC_byp(7) and not or_reduce(congr_cl_ex2_wayC_byp(2 to 6)); +wayC_late_sel <= or_reduce(congr_cl_ex2_wayC_byp(2 to 7)); +wayC_later_stg_pri <= gate(p0_arr_wayC_rd, not wayC_late_sel) or + gate(reload_wayC_q, congr_cl_ex2_wayC_sel(2)) or + gate(flush_wayC_q, congr_cl_ex2_wayC_sel(3)) or + gate(reload_wayC_data_q, congr_cl_ex2_wayC_sel(4)) or + gate(flush_wayC_data_q, congr_cl_ex2_wayC_sel(5)) or + gate(reload_wayC_data2_q, congr_cl_ex2_wayC_sel(6)) or + gate(flush_wayC_data2_q, congr_cl_ex2_wayC_sel(7)); +wayC_early_sel <= congr_cl_ex2_wayC_byp(1); +wayC_early_stg_pri <= flush_wayC_d; +wayC_stg_val <= (others=>(wayC_early_sel)); +wayC_stg_val_b <= (others=>(not(wayC_early_sel))); +wayC_val(0 TO 1) <= not wayC_val_b_q(0 to 1); +wayC_val(2 TO 5) <= not wayC_val_b_q(2 to 5); +wayC_val_b1 <= not wayC_val(0); +congr_cl_ex2_wayD_byp(1) <= congr_cl_ex2_ex3_m and ex3_wayD_hit; +congr_cl_ex2_wayD_byp(2) <= congr_cl_ex2_relu_m and reload_wayD_upd_q; +congr_cl_ex2_wayD_byp(3) <= congr_cl_ex2_ex4_m and binv_wayD_upd_q; +congr_cl_ex2_wayD_byp(4) <= congr_cl_ex2_relu_s_m and reload_wayD_upd2_q; +congr_cl_ex2_wayD_byp(5) <= congr_cl_ex2_ex5_m and binv_wayD_upd2_q; +congr_cl_ex2_wayD_byp(6) <= congr_cl_ex2_p1_cmp and reload_wayD_upd3_q; +congr_cl_ex2_wayD_byp(7) <= congr_cl_ex2_p0_cmp and binv_wayD_upd3_q; +ex3_wayD_fxubyp_val_d <= congr_cl_ex2_wayD_byp(1) or congr_cl_ex2_wayD_byp(3) or + congr_cl_ex2_wayD_byp(5) or congr_cl_ex2_wayD_byp(7); +ex3_wayD_relbyp_val_d <= congr_cl_ex2_wayD_byp(2) or congr_cl_ex2_wayD_byp(4) or + congr_cl_ex2_wayD_byp(6); +ex4_wayD_fxubyp_val_d <= ex3_wayD_fxubyp_val_q; +ex4_wayD_relbyp_val_d <= ex3_wayD_relbyp_val_q; +ex4_wayD_byp_sel <= ex4_wayD_fxubyp_val_q & ex4_wayD_relbyp_val_q; +congr_cl_ex2_wayD_sel(2) <= congr_cl_ex2_wayD_byp(2); +congr_cl_ex2_wayD_sel(3) <= congr_cl_ex2_wayD_byp(3) and not congr_cl_ex2_wayD_byp(2); +congr_cl_ex2_wayD_sel(4) <= congr_cl_ex2_wayD_byp(4) and not or_reduce(congr_cl_ex2_wayD_byp(2 to 3)); +congr_cl_ex2_wayD_sel(5) <= congr_cl_ex2_wayD_byp(5) and not or_reduce(congr_cl_ex2_wayD_byp(2 to 4)); +congr_cl_ex2_wayD_sel(6) <= congr_cl_ex2_wayD_byp(6) and not or_reduce(congr_cl_ex2_wayD_byp(2 to 5)); +congr_cl_ex2_wayD_sel(7) <= congr_cl_ex2_wayD_byp(7) and not or_reduce(congr_cl_ex2_wayD_byp(2 to 6)); +wayD_late_sel <= or_reduce(congr_cl_ex2_wayD_byp(2 to 7)); +wayD_later_stg_pri <= gate(p0_arr_wayD_rd, not wayD_late_sel) or + gate(reload_wayD_q, congr_cl_ex2_wayD_sel(2)) or + gate(flush_wayD_q, congr_cl_ex2_wayD_sel(3)) or + gate(reload_wayD_data_q, congr_cl_ex2_wayD_sel(4)) or + gate(flush_wayD_data_q, congr_cl_ex2_wayD_sel(5)) or + gate(reload_wayD_data2_q, congr_cl_ex2_wayD_sel(6)) or + gate(flush_wayD_data2_q, congr_cl_ex2_wayD_sel(7)); +wayD_early_sel <= congr_cl_ex2_wayD_byp(1); +wayD_early_stg_pri <= flush_wayD_d; +wayD_stg_val <= (others=>(wayD_early_sel)); +wayD_stg_val_b <= (others=>(not(wayD_early_sel))); +wayD_val(0 TO 1) <= not wayD_val_b_q(0 to 1); +wayD_val(2 TO 5) <= not wayD_val_b_q(2 to 5); +wayD_val_b1 <= not wayD_val(0); +congr_cl_ex2_wayE_byp(1) <= congr_cl_ex2_ex3_m and ex3_wayE_hit; +congr_cl_ex2_wayE_byp(2) <= congr_cl_ex2_relu_m and reload_wayE_upd_q; +congr_cl_ex2_wayE_byp(3) <= congr_cl_ex2_ex4_m and binv_wayE_upd_q; +congr_cl_ex2_wayE_byp(4) <= congr_cl_ex2_relu_s_m and reload_wayE_upd2_q; +congr_cl_ex2_wayE_byp(5) <= congr_cl_ex2_ex5_m and binv_wayE_upd2_q; +congr_cl_ex2_wayE_byp(6) <= congr_cl_ex2_p1_cmp and reload_wayE_upd3_q; +congr_cl_ex2_wayE_byp(7) <= congr_cl_ex2_p0_cmp and binv_wayE_upd3_q; +ex3_wayE_fxubyp_val_d <= congr_cl_ex2_wayE_byp(1) or congr_cl_ex2_wayE_byp(3) or + congr_cl_ex2_wayE_byp(5) or congr_cl_ex2_wayE_byp(7); +ex3_wayE_relbyp_val_d <= congr_cl_ex2_wayE_byp(2) or congr_cl_ex2_wayE_byp(4) or + congr_cl_ex2_wayE_byp(6); +ex4_wayE_fxubyp_val_d <= ex3_wayE_fxubyp_val_q; +ex4_wayE_relbyp_val_d <= ex3_wayE_relbyp_val_q; +ex4_wayE_byp_sel <= ex4_wayE_fxubyp_val_q & ex4_wayE_relbyp_val_q; +congr_cl_ex2_wayE_sel(2) <= congr_cl_ex2_wayE_byp(2); +congr_cl_ex2_wayE_sel(3) <= congr_cl_ex2_wayE_byp(3) and not congr_cl_ex2_wayE_byp(2); +congr_cl_ex2_wayE_sel(4) <= congr_cl_ex2_wayE_byp(4) and not or_reduce(congr_cl_ex2_wayE_byp(2 to 3)); +congr_cl_ex2_wayE_sel(5) <= congr_cl_ex2_wayE_byp(5) and not or_reduce(congr_cl_ex2_wayE_byp(2 to 4)); +congr_cl_ex2_wayE_sel(6) <= congr_cl_ex2_wayE_byp(6) and not or_reduce(congr_cl_ex2_wayE_byp(2 to 5)); +congr_cl_ex2_wayE_sel(7) <= congr_cl_ex2_wayE_byp(7) and not or_reduce(congr_cl_ex2_wayE_byp(2 to 6)); +wayE_late_sel <= or_reduce(congr_cl_ex2_wayE_byp(2 to 7)); +wayE_later_stg_pri <= gate(p0_arr_wayE_rd, not wayE_late_sel) or + gate(reload_wayE_q, congr_cl_ex2_wayE_sel(2)) or + gate(flush_wayE_q, congr_cl_ex2_wayE_sel(3)) or + gate(reload_wayE_data_q, congr_cl_ex2_wayE_sel(4)) or + gate(flush_wayE_data_q, congr_cl_ex2_wayE_sel(5)) or + gate(reload_wayE_data2_q, congr_cl_ex2_wayE_sel(6)) or + gate(flush_wayE_data2_q, congr_cl_ex2_wayE_sel(7)); +wayE_early_sel <= congr_cl_ex2_wayE_byp(1); +wayE_early_stg_pri <= flush_wayE_d; +wayE_stg_val <= (others=>(wayE_early_sel)); +wayE_stg_val_b <= (others=>(not(wayE_early_sel))); +wayE_val(0 TO 1) <= not wayE_val_b_q(0 to 1); +wayE_val(2 TO 5) <= not wayE_val_b_q(2 to 5); +wayE_val_b1 <= not wayE_val(0); +congr_cl_ex2_wayF_byp(1) <= congr_cl_ex2_ex3_m and ex3_wayF_hit; +congr_cl_ex2_wayF_byp(2) <= congr_cl_ex2_relu_m and reload_wayF_upd_q; +congr_cl_ex2_wayF_byp(3) <= congr_cl_ex2_ex4_m and binv_wayF_upd_q; +congr_cl_ex2_wayF_byp(4) <= congr_cl_ex2_relu_s_m and reload_wayF_upd2_q; +congr_cl_ex2_wayF_byp(5) <= congr_cl_ex2_ex5_m and binv_wayF_upd2_q; +congr_cl_ex2_wayF_byp(6) <= congr_cl_ex2_p1_cmp and reload_wayF_upd3_q; +congr_cl_ex2_wayF_byp(7) <= congr_cl_ex2_p0_cmp and binv_wayF_upd3_q; +ex3_wayF_fxubyp_val_d <= congr_cl_ex2_wayF_byp(1) or congr_cl_ex2_wayF_byp(3) or + congr_cl_ex2_wayF_byp(5) or congr_cl_ex2_wayF_byp(7); +ex3_wayF_relbyp_val_d <= congr_cl_ex2_wayF_byp(2) or congr_cl_ex2_wayF_byp(4) or + congr_cl_ex2_wayF_byp(6); +ex4_wayF_fxubyp_val_d <= ex3_wayF_fxubyp_val_q; +ex4_wayF_relbyp_val_d <= ex3_wayF_relbyp_val_q; +ex4_wayF_byp_sel <= ex4_wayF_fxubyp_val_q & ex4_wayF_relbyp_val_q; +congr_cl_ex2_wayF_sel(2) <= congr_cl_ex2_wayF_byp(2); +congr_cl_ex2_wayF_sel(3) <= congr_cl_ex2_wayF_byp(3) and not congr_cl_ex2_wayF_byp(2); +congr_cl_ex2_wayF_sel(4) <= congr_cl_ex2_wayF_byp(4) and not or_reduce(congr_cl_ex2_wayF_byp(2 to 3)); +congr_cl_ex2_wayF_sel(5) <= congr_cl_ex2_wayF_byp(5) and not or_reduce(congr_cl_ex2_wayF_byp(2 to 4)); +congr_cl_ex2_wayF_sel(6) <= congr_cl_ex2_wayF_byp(6) and not or_reduce(congr_cl_ex2_wayF_byp(2 to 5)); +congr_cl_ex2_wayF_sel(7) <= congr_cl_ex2_wayF_byp(7) and not or_reduce(congr_cl_ex2_wayF_byp(2 to 6)); +wayF_late_sel <= or_reduce(congr_cl_ex2_wayF_byp(2 to 7)); +wayF_later_stg_pri <= gate(p0_arr_wayF_rd, not wayF_late_sel) or + gate(reload_wayF_q, congr_cl_ex2_wayF_sel(2)) or + gate(flush_wayF_q, congr_cl_ex2_wayF_sel(3)) or + gate(reload_wayF_data_q, congr_cl_ex2_wayF_sel(4)) or + gate(flush_wayF_data_q, congr_cl_ex2_wayF_sel(5)) or + gate(reload_wayF_data2_q, congr_cl_ex2_wayF_sel(6)) or + gate(flush_wayF_data2_q, congr_cl_ex2_wayF_sel(7)); +wayF_early_sel <= congr_cl_ex2_wayF_byp(1); +wayF_early_stg_pri <= flush_wayF_d; +wayF_stg_val <= (others=>(wayF_early_sel)); +wayF_stg_val_b <= (others=>(not(wayF_early_sel))); +wayF_val(0 TO 1) <= not wayF_val_b_q(0 to 1); +wayF_val(2 TO 5) <= not wayF_val_b_q(2 to 5); +wayF_val_b1 <= not wayF_val(0); +congr_cl_ex2_wayG_byp(1) <= congr_cl_ex2_ex3_m and ex3_wayG_hit; +congr_cl_ex2_wayG_byp(2) <= congr_cl_ex2_relu_m and reload_wayG_upd_q; +congr_cl_ex2_wayG_byp(3) <= congr_cl_ex2_ex4_m and binv_wayG_upd_q; +congr_cl_ex2_wayG_byp(4) <= congr_cl_ex2_relu_s_m and reload_wayG_upd2_q; +congr_cl_ex2_wayG_byp(5) <= congr_cl_ex2_ex5_m and binv_wayG_upd2_q; +congr_cl_ex2_wayG_byp(6) <= congr_cl_ex2_p1_cmp and reload_wayG_upd3_q; +congr_cl_ex2_wayG_byp(7) <= congr_cl_ex2_p0_cmp and binv_wayG_upd3_q; +ex3_wayG_fxubyp_val_d <= congr_cl_ex2_wayG_byp(1) or congr_cl_ex2_wayG_byp(3) or + congr_cl_ex2_wayG_byp(5) or congr_cl_ex2_wayG_byp(7); +ex3_wayG_relbyp_val_d <= congr_cl_ex2_wayG_byp(2) or congr_cl_ex2_wayG_byp(4) or + congr_cl_ex2_wayG_byp(6); +ex4_wayG_fxubyp_val_d <= ex3_wayG_fxubyp_val_q; +ex4_wayG_relbyp_val_d <= ex3_wayG_relbyp_val_q; +ex4_wayG_byp_sel <= ex4_wayG_fxubyp_val_q & ex4_wayG_relbyp_val_q; +congr_cl_ex2_wayG_sel(2) <= congr_cl_ex2_wayG_byp(2); +congr_cl_ex2_wayG_sel(3) <= congr_cl_ex2_wayG_byp(3) and not congr_cl_ex2_wayG_byp(2); +congr_cl_ex2_wayG_sel(4) <= congr_cl_ex2_wayG_byp(4) and not or_reduce(congr_cl_ex2_wayG_byp(2 to 3)); +congr_cl_ex2_wayG_sel(5) <= congr_cl_ex2_wayG_byp(5) and not or_reduce(congr_cl_ex2_wayG_byp(2 to 4)); +congr_cl_ex2_wayG_sel(6) <= congr_cl_ex2_wayG_byp(6) and not or_reduce(congr_cl_ex2_wayG_byp(2 to 5)); +congr_cl_ex2_wayG_sel(7) <= congr_cl_ex2_wayG_byp(7) and not or_reduce(congr_cl_ex2_wayG_byp(2 to 6)); +wayG_late_sel <= or_reduce(congr_cl_ex2_wayG_byp(2 to 7)); +wayG_later_stg_pri <= gate(p0_arr_wayG_rd, not wayG_late_sel) or + gate(reload_wayG_q, congr_cl_ex2_wayG_sel(2)) or + gate(flush_wayG_q, congr_cl_ex2_wayG_sel(3)) or + gate(reload_wayG_data_q, congr_cl_ex2_wayG_sel(4)) or + gate(flush_wayG_data_q, congr_cl_ex2_wayG_sel(5)) or + gate(reload_wayG_data2_q, congr_cl_ex2_wayG_sel(6)) or + gate(flush_wayG_data2_q, congr_cl_ex2_wayG_sel(7)); +wayG_early_sel <= congr_cl_ex2_wayG_byp(1); +wayG_early_stg_pri <= flush_wayG_d; +wayG_stg_val <= (others=>(wayG_early_sel)); +wayG_stg_val_b <= (others=>(not(wayG_early_sel))); +wayG_val(0 TO 1) <= not wayG_val_b_q(0 to 1); +wayG_val(2 TO 5) <= not wayG_val_b_q(2 to 5); +wayG_val_b1 <= not wayG_val(0); +congr_cl_ex2_wayH_byp(1) <= congr_cl_ex2_ex3_m and ex3_wayH_hit; +congr_cl_ex2_wayH_byp(2) <= congr_cl_ex2_relu_m and reload_wayH_upd_q; +congr_cl_ex2_wayH_byp(3) <= congr_cl_ex2_ex4_m and binv_wayH_upd_q; +congr_cl_ex2_wayH_byp(4) <= congr_cl_ex2_relu_s_m and reload_wayH_upd2_q; +congr_cl_ex2_wayH_byp(5) <= congr_cl_ex2_ex5_m and binv_wayH_upd2_q; +congr_cl_ex2_wayH_byp(6) <= congr_cl_ex2_p1_cmp and reload_wayH_upd3_q; +congr_cl_ex2_wayH_byp(7) <= congr_cl_ex2_p0_cmp and binv_wayH_upd3_q; +ex3_wayH_fxubyp_val_d <= congr_cl_ex2_wayH_byp(1) or congr_cl_ex2_wayH_byp(3) or + congr_cl_ex2_wayH_byp(5) or congr_cl_ex2_wayH_byp(7); +ex3_wayH_relbyp_val_d <= congr_cl_ex2_wayH_byp(2) or congr_cl_ex2_wayH_byp(4) or + congr_cl_ex2_wayH_byp(6); +ex4_wayH_fxubyp_val_d <= ex3_wayH_fxubyp_val_q; +ex4_wayH_relbyp_val_d <= ex3_wayH_relbyp_val_q; +ex4_wayH_byp_sel <= ex4_wayH_fxubyp_val_q & ex4_wayH_relbyp_val_q; +congr_cl_ex2_wayH_sel(2) <= congr_cl_ex2_wayH_byp(2); +congr_cl_ex2_wayH_sel(3) <= congr_cl_ex2_wayH_byp(3) and not congr_cl_ex2_wayH_byp(2); +congr_cl_ex2_wayH_sel(4) <= congr_cl_ex2_wayH_byp(4) and not or_reduce(congr_cl_ex2_wayH_byp(2 to 3)); +congr_cl_ex2_wayH_sel(5) <= congr_cl_ex2_wayH_byp(5) and not or_reduce(congr_cl_ex2_wayH_byp(2 to 4)); +congr_cl_ex2_wayH_sel(6) <= congr_cl_ex2_wayH_byp(6) and not or_reduce(congr_cl_ex2_wayH_byp(2 to 5)); +congr_cl_ex2_wayH_sel(7) <= congr_cl_ex2_wayH_byp(7) and not or_reduce(congr_cl_ex2_wayH_byp(2 to 6)); +wayH_late_sel <= or_reduce(congr_cl_ex2_wayH_byp(2 to 7)); +wayH_later_stg_pri <= gate(p0_arr_wayH_rd, not wayH_late_sel) or + gate(reload_wayH_q, congr_cl_ex2_wayH_sel(2)) or + gate(flush_wayH_q, congr_cl_ex2_wayH_sel(3)) or + gate(reload_wayH_data_q, congr_cl_ex2_wayH_sel(4)) or + gate(flush_wayH_data_q, congr_cl_ex2_wayH_sel(5)) or + gate(reload_wayH_data2_q, congr_cl_ex2_wayH_sel(6)) or + gate(flush_wayH_data2_q, congr_cl_ex2_wayH_sel(7)); +wayH_early_sel <= congr_cl_ex2_wayH_byp(1); +wayH_early_stg_pri <= flush_wayH_d; +wayH_stg_val <= (others=>(wayH_early_sel)); +wayH_stg_val_b <= (others=>(not(wayH_early_sel))); +wayH_val(0 TO 1) <= not wayH_val_b_q(0 to 1); +wayH_val(2 TO 5) <= not wayH_val_b_q(2 to 5); +wayH_val_b1 <= not wayH_val(0); +fxu_pipe_val <= ex3_c_acc or ex3_flush_cline_q; +ex3WayHitA: ex3_wayA_hit <= not (tagA_hit_b or wayA_val_b1); +ex3WayHitB: ex3_wayB_hit <= not (tagB_hit_b or wayB_val_b1); +ex3WayHitC: ex3_wayC_hit <= not (tagC_hit_b or wayC_val_b1); +ex3WayHitD: ex3_wayD_hit <= not (tagD_hit_b or wayD_val_b1); +ex3WayHitE: ex3_wayE_hit <= not (tagE_hit_b or wayE_val_b1); +ex3WayHitF: ex3_wayF_hit <= not (tagF_hit_b or wayF_val_b1); +ex3WayHitG: ex3_wayG_hit <= not (tagG_hit_b or wayG_val_b1); +ex3WayHitH: ex3_wayH_hit <= not (tagH_hit_b or wayH_val_b1); +clr_val <= ex3_flush_cline_q or back_inval_stg3_q; +clr_val_wayA <= clr_val; +inval_clr_lck_wA_d <= clr_val_wayA and wayA_val(1); +flush_wayA_d(0) <= not clr_val_wayA and wayA_val(0); +clr_val_wayB <= clr_val; +inval_clr_lck_wB_d <= clr_val_wayB and wayB_val(1); +flush_wayB_d(0) <= not clr_val_wayB and wayB_val(0); +clr_val_wayC <= clr_val; +inval_clr_lck_wC_d <= clr_val_wayC and wayC_val(1); +flush_wayC_d(0) <= not clr_val_wayC and wayC_val(0); +clr_val_wayD <= clr_val; +inval_clr_lck_wD_d <= clr_val_wayD and wayD_val(1); +flush_wayD_d(0) <= not clr_val_wayD and wayD_val(0); +clr_val_wayE <= clr_val; +inval_clr_lck_wE_d <= clr_val_wayE and wayE_val(1); +flush_wayE_d(0) <= not clr_val_wayE and wayE_val(0); +clr_val_wayF <= clr_val; +inval_clr_lck_wF_d <= clr_val_wayF and wayF_val(1); +flush_wayF_d(0) <= not clr_val_wayF and wayF_val(0); +clr_val_wayG <= clr_val; +inval_clr_lck_wG_d <= clr_val_wayG and wayG_val(1); +flush_wayG_d(0) <= not clr_val_wayG and wayG_val(0); +clr_val_wayH <= clr_val; +inval_clr_lck_wH_d <= clr_val_wayH and wayH_val(1); +flush_wayH_d(0) <= not clr_val_wayH and wayH_val(0); +clr_lock <= clr_val or ex3_lock_clr_q; +upd_lck_wayA <= clr_lock & ex3_lock_set_q; +flush_wayA_d(1) <= (wayA_val(1) and not upd_lck_wayA(0)) or + (wayA_val(0) and upd_lck_wayA(1)); +ex4_wayA_val_d <= wayA_val; +upd_lck_wayB <= clr_lock & ex3_lock_set_q; +flush_wayB_d(1) <= (wayB_val(1) and not upd_lck_wayB(0)) or + (wayB_val(0) and upd_lck_wayB(1)); +ex4_wayB_val_d <= wayB_val; +upd_lck_wayC <= clr_lock & ex3_lock_set_q; +flush_wayC_d(1) <= (wayC_val(1) and not upd_lck_wayC(0)) or + (wayC_val(0) and upd_lck_wayC(1)); +ex4_wayC_val_d <= wayC_val; +upd_lck_wayD <= clr_lock & ex3_lock_set_q; +flush_wayD_d(1) <= (wayD_val(1) and not upd_lck_wayD(0)) or + (wayD_val(0) and upd_lck_wayD(1)); +ex4_wayD_val_d <= wayD_val; +upd_lck_wayE <= clr_lock & ex3_lock_set_q; +flush_wayE_d(1) <= (wayE_val(1) and not upd_lck_wayE(0)) or + (wayE_val(0) and upd_lck_wayE(1)); +ex4_wayE_val_d <= wayE_val; +upd_lck_wayF <= clr_lock & ex3_lock_set_q; +flush_wayF_d(1) <= (wayF_val(1) and not upd_lck_wayF(0)) or + (wayF_val(0) and upd_lck_wayF(1)); +ex4_wayF_val_d <= wayF_val; +upd_lck_wayG <= clr_lock & ex3_lock_set_q; +flush_wayG_d(1) <= (wayG_val(1) and not upd_lck_wayG(0)) or + (wayG_val(0) and upd_lck_wayG(1)); +ex4_wayG_val_d <= wayG_val; +upd_lck_wayH <= clr_lock & ex3_lock_set_q; +flush_wayH_d(1) <= (wayH_val(1) and not upd_lck_wayH(0)) or + (wayH_val(0) and upd_lck_wayH(1)); +ex4_wayH_val_d <= wayH_val; +lose_watch(0) <= clr_val or (ex3_store_instr_q and ex3_c_acc and not ex3_thrd_id_q(0)); +ex4_lose_watch_d(0) <= lose_watch(0); +clr_watch(0) <= (ex3_watch_clr_q and ex3_thrd_id_q(0)) or lose_watch(0); +set_watch(0) <= ex3_watch_set_q and ex3_thrd_id_q(0); +ex4_lost_wayA(0) <= ex4_lose_watch_q(0) and ex4_way_hit_q(0) and ex4_wayA_val_q(2); +upd_watch_tid0_wayA <= (clr_watch(0) or ex3_watch_clr_all(0)) & set_watch(0); +flush_wayA_d(2) <= (wayA_val(2) and not upd_watch_tid0_wayA(0)) or + (wayA_val(0) and upd_watch_tid0_wayA(1)); +ex4_lost_wayB(0) <= ex4_lose_watch_q(0) and ex4_way_hit_q(1) and ex4_wayB_val_q(2); +upd_watch_tid0_wayB <= (clr_watch(0) or ex3_watch_clr_all(0)) & set_watch(0); +flush_wayB_d(2) <= (wayB_val(2) and not upd_watch_tid0_wayB(0)) or + (wayB_val(0) and upd_watch_tid0_wayB(1)); +ex4_lost_wayC(0) <= ex4_lose_watch_q(0) and ex4_way_hit_q(2) and ex4_wayC_val_q(2); +upd_watch_tid0_wayC <= (clr_watch(0) or ex3_watch_clr_all(0)) & set_watch(0); +flush_wayC_d(2) <= (wayC_val(2) and not upd_watch_tid0_wayC(0)) or + (wayC_val(0) and upd_watch_tid0_wayC(1)); +ex4_lost_wayD(0) <= ex4_lose_watch_q(0) and ex4_way_hit_q(3) and ex4_wayD_val_q(2); +upd_watch_tid0_wayD <= (clr_watch(0) or ex3_watch_clr_all(0)) & set_watch(0); +flush_wayD_d(2) <= (wayD_val(2) and not upd_watch_tid0_wayD(0)) or + (wayD_val(0) and upd_watch_tid0_wayD(1)); +ex4_lost_wayE(0) <= ex4_lose_watch_q(0) and ex4_way_hit_q(4) and ex4_wayE_val_q(2); +upd_watch_tid0_wayE <= (clr_watch(0) or ex3_watch_clr_all(0)) & set_watch(0); +flush_wayE_d(2) <= (wayE_val(2) and not upd_watch_tid0_wayE(0)) or + (wayE_val(0) and upd_watch_tid0_wayE(1)); +ex4_lost_wayF(0) <= ex4_lose_watch_q(0) and ex4_way_hit_q(5) and ex4_wayF_val_q(2); +upd_watch_tid0_wayF <= (clr_watch(0) or ex3_watch_clr_all(0)) & set_watch(0); +flush_wayF_d(2) <= (wayF_val(2) and not upd_watch_tid0_wayF(0)) or + (wayF_val(0) and upd_watch_tid0_wayF(1)); +ex4_lost_wayG(0) <= ex4_lose_watch_q(0) and ex4_way_hit_q(6) and ex4_wayG_val_q(2); +upd_watch_tid0_wayG <= (clr_watch(0) or ex3_watch_clr_all(0)) & set_watch(0); +flush_wayG_d(2) <= (wayG_val(2) and not upd_watch_tid0_wayG(0)) or + (wayG_val(0) and upd_watch_tid0_wayG(1)); +ex4_lost_wayH(0) <= ex4_lose_watch_q(0) and ex4_way_hit_q(7) and ex4_wayH_val_q(2); +upd_watch_tid0_wayH <= (clr_watch(0) or ex3_watch_clr_all(0)) & set_watch(0); +flush_wayH_d(2) <= (wayH_val(2) and not upd_watch_tid0_wayH(0)) or + (wayH_val(0) and upd_watch_tid0_wayH(1)); +lose_watch(1) <= clr_val or (ex3_store_instr_q and ex3_c_acc and not ex3_thrd_id_q(1)); +ex4_lose_watch_d(1) <= lose_watch(1); +clr_watch(1) <= (ex3_watch_clr_q and ex3_thrd_id_q(1)) or lose_watch(1); +set_watch(1) <= ex3_watch_set_q and ex3_thrd_id_q(1); +ex4_lost_wayA(1) <= ex4_lose_watch_q(1) and ex4_way_hit_q(0) and ex4_wayA_val_q(3); +upd_watch_tid1_wayA <= (clr_watch(1) or ex3_watch_clr_all(1)) & set_watch(1); +flush_wayA_d(3) <= (wayA_val(3) and not upd_watch_tid1_wayA(0)) or + (wayA_val(0) and upd_watch_tid1_wayA(1)); +ex4_lost_wayB(1) <= ex4_lose_watch_q(1) and ex4_way_hit_q(1) and ex4_wayB_val_q(3); +upd_watch_tid1_wayB <= (clr_watch(1) or ex3_watch_clr_all(1)) & set_watch(1); +flush_wayB_d(3) <= (wayB_val(3) and not upd_watch_tid1_wayB(0)) or + (wayB_val(0) and upd_watch_tid1_wayB(1)); +ex4_lost_wayC(1) <= ex4_lose_watch_q(1) and ex4_way_hit_q(2) and ex4_wayC_val_q(3); +upd_watch_tid1_wayC <= (clr_watch(1) or ex3_watch_clr_all(1)) & set_watch(1); +flush_wayC_d(3) <= (wayC_val(3) and not upd_watch_tid1_wayC(0)) or + (wayC_val(0) and upd_watch_tid1_wayC(1)); +ex4_lost_wayD(1) <= ex4_lose_watch_q(1) and ex4_way_hit_q(3) and ex4_wayD_val_q(3); +upd_watch_tid1_wayD <= (clr_watch(1) or ex3_watch_clr_all(1)) & set_watch(1); +flush_wayD_d(3) <= (wayD_val(3) and not upd_watch_tid1_wayD(0)) or + (wayD_val(0) and upd_watch_tid1_wayD(1)); +ex4_lost_wayE(1) <= ex4_lose_watch_q(1) and ex4_way_hit_q(4) and ex4_wayE_val_q(3); +upd_watch_tid1_wayE <= (clr_watch(1) or ex3_watch_clr_all(1)) & set_watch(1); +flush_wayE_d(3) <= (wayE_val(3) and not upd_watch_tid1_wayE(0)) or + (wayE_val(0) and upd_watch_tid1_wayE(1)); +ex4_lost_wayF(1) <= ex4_lose_watch_q(1) and ex4_way_hit_q(5) and ex4_wayF_val_q(3); +upd_watch_tid1_wayF <= (clr_watch(1) or ex3_watch_clr_all(1)) & set_watch(1); +flush_wayF_d(3) <= (wayF_val(3) and not upd_watch_tid1_wayF(0)) or + (wayF_val(0) and upd_watch_tid1_wayF(1)); +ex4_lost_wayG(1) <= ex4_lose_watch_q(1) and ex4_way_hit_q(6) and ex4_wayG_val_q(3); +upd_watch_tid1_wayG <= (clr_watch(1) or ex3_watch_clr_all(1)) & set_watch(1); +flush_wayG_d(3) <= (wayG_val(3) and not upd_watch_tid1_wayG(0)) or + (wayG_val(0) and upd_watch_tid1_wayG(1)); +ex4_lost_wayH(1) <= ex4_lose_watch_q(1) and ex4_way_hit_q(7) and ex4_wayH_val_q(3); +upd_watch_tid1_wayH <= (clr_watch(1) or ex3_watch_clr_all(1)) & set_watch(1); +flush_wayH_d(3) <= (wayH_val(3) and not upd_watch_tid1_wayH(0)) or + (wayH_val(0) and upd_watch_tid1_wayH(1)); +lose_watch(2) <= clr_val or (ex3_store_instr_q and ex3_c_acc and not ex3_thrd_id_q(2)); +ex4_lose_watch_d(2) <= lose_watch(2); +clr_watch(2) <= (ex3_watch_clr_q and ex3_thrd_id_q(2)) or lose_watch(2); +set_watch(2) <= ex3_watch_set_q and ex3_thrd_id_q(2); +ex4_lost_wayA(2) <= ex4_lose_watch_q(2) and ex4_way_hit_q(0) and ex4_wayA_val_q(4); +upd_watch_tid2_wayA <= (clr_watch(2) or ex3_watch_clr_all(2)) & set_watch(2); +flush_wayA_d(4) <= (wayA_val(4) and not upd_watch_tid2_wayA(0)) or + (wayA_val(0) and upd_watch_tid2_wayA(1)); +ex4_lost_wayB(2) <= ex4_lose_watch_q(2) and ex4_way_hit_q(1) and ex4_wayB_val_q(4); +upd_watch_tid2_wayB <= (clr_watch(2) or ex3_watch_clr_all(2)) & set_watch(2); +flush_wayB_d(4) <= (wayB_val(4) and not upd_watch_tid2_wayB(0)) or + (wayB_val(0) and upd_watch_tid2_wayB(1)); +ex4_lost_wayC(2) <= ex4_lose_watch_q(2) and ex4_way_hit_q(2) and ex4_wayC_val_q(4); +upd_watch_tid2_wayC <= (clr_watch(2) or ex3_watch_clr_all(2)) & set_watch(2); +flush_wayC_d(4) <= (wayC_val(4) and not upd_watch_tid2_wayC(0)) or + (wayC_val(0) and upd_watch_tid2_wayC(1)); +ex4_lost_wayD(2) <= ex4_lose_watch_q(2) and ex4_way_hit_q(3) and ex4_wayD_val_q(4); +upd_watch_tid2_wayD <= (clr_watch(2) or ex3_watch_clr_all(2)) & set_watch(2); +flush_wayD_d(4) <= (wayD_val(4) and not upd_watch_tid2_wayD(0)) or + (wayD_val(0) and upd_watch_tid2_wayD(1)); +ex4_lost_wayE(2) <= ex4_lose_watch_q(2) and ex4_way_hit_q(4) and ex4_wayE_val_q(4); +upd_watch_tid2_wayE <= (clr_watch(2) or ex3_watch_clr_all(2)) & set_watch(2); +flush_wayE_d(4) <= (wayE_val(4) and not upd_watch_tid2_wayE(0)) or + (wayE_val(0) and upd_watch_tid2_wayE(1)); +ex4_lost_wayF(2) <= ex4_lose_watch_q(2) and ex4_way_hit_q(5) and ex4_wayF_val_q(4); +upd_watch_tid2_wayF <= (clr_watch(2) or ex3_watch_clr_all(2)) & set_watch(2); +flush_wayF_d(4) <= (wayF_val(4) and not upd_watch_tid2_wayF(0)) or + (wayF_val(0) and upd_watch_tid2_wayF(1)); +ex4_lost_wayG(2) <= ex4_lose_watch_q(2) and ex4_way_hit_q(6) and ex4_wayG_val_q(4); +upd_watch_tid2_wayG <= (clr_watch(2) or ex3_watch_clr_all(2)) & set_watch(2); +flush_wayG_d(4) <= (wayG_val(4) and not upd_watch_tid2_wayG(0)) or + (wayG_val(0) and upd_watch_tid2_wayG(1)); +ex4_lost_wayH(2) <= ex4_lose_watch_q(2) and ex4_way_hit_q(7) and ex4_wayH_val_q(4); +upd_watch_tid2_wayH <= (clr_watch(2) or ex3_watch_clr_all(2)) & set_watch(2); +flush_wayH_d(4) <= (wayH_val(4) and not upd_watch_tid2_wayH(0)) or + (wayH_val(0) and upd_watch_tid2_wayH(1)); +lose_watch(3) <= clr_val or (ex3_store_instr_q and ex3_c_acc and not ex3_thrd_id_q(3)); +ex4_lose_watch_d(3) <= lose_watch(3); +clr_watch(3) <= (ex3_watch_clr_q and ex3_thrd_id_q(3)) or lose_watch(3); +set_watch(3) <= ex3_watch_set_q and ex3_thrd_id_q(3); +ex4_lost_wayA(3) <= ex4_lose_watch_q(3) and ex4_way_hit_q(0) and ex4_wayA_val_q(5); +upd_watch_tid3_wayA <= (clr_watch(3) or ex3_watch_clr_all(3)) & set_watch(3); +flush_wayA_d(5) <= (wayA_val(5) and not upd_watch_tid3_wayA(0)) or + (wayA_val(0) and upd_watch_tid3_wayA(1)); +ex4_lost_wayB(3) <= ex4_lose_watch_q(3) and ex4_way_hit_q(1) and ex4_wayB_val_q(5); +upd_watch_tid3_wayB <= (clr_watch(3) or ex3_watch_clr_all(3)) & set_watch(3); +flush_wayB_d(5) <= (wayB_val(5) and not upd_watch_tid3_wayB(0)) or + (wayB_val(0) and upd_watch_tid3_wayB(1)); +ex4_lost_wayC(3) <= ex4_lose_watch_q(3) and ex4_way_hit_q(2) and ex4_wayC_val_q(5); +upd_watch_tid3_wayC <= (clr_watch(3) or ex3_watch_clr_all(3)) & set_watch(3); +flush_wayC_d(5) <= (wayC_val(5) and not upd_watch_tid3_wayC(0)) or + (wayC_val(0) and upd_watch_tid3_wayC(1)); +ex4_lost_wayD(3) <= ex4_lose_watch_q(3) and ex4_way_hit_q(3) and ex4_wayD_val_q(5); +upd_watch_tid3_wayD <= (clr_watch(3) or ex3_watch_clr_all(3)) & set_watch(3); +flush_wayD_d(5) <= (wayD_val(5) and not upd_watch_tid3_wayD(0)) or + (wayD_val(0) and upd_watch_tid3_wayD(1)); +ex4_lost_wayE(3) <= ex4_lose_watch_q(3) and ex4_way_hit_q(4) and ex4_wayE_val_q(5); +upd_watch_tid3_wayE <= (clr_watch(3) or ex3_watch_clr_all(3)) & set_watch(3); +flush_wayE_d(5) <= (wayE_val(5) and not upd_watch_tid3_wayE(0)) or + (wayE_val(0) and upd_watch_tid3_wayE(1)); +ex4_lost_wayF(3) <= ex4_lose_watch_q(3) and ex4_way_hit_q(5) and ex4_wayF_val_q(5); +upd_watch_tid3_wayF <= (clr_watch(3) or ex3_watch_clr_all(3)) & set_watch(3); +flush_wayF_d(5) <= (wayF_val(5) and not upd_watch_tid3_wayF(0)) or + (wayF_val(0) and upd_watch_tid3_wayF(1)); +ex4_lost_wayG(3) <= ex4_lose_watch_q(3) and ex4_way_hit_q(6) and ex4_wayG_val_q(5); +upd_watch_tid3_wayG <= (clr_watch(3) or ex3_watch_clr_all(3)) & set_watch(3); +flush_wayG_d(5) <= (wayG_val(5) and not upd_watch_tid3_wayG(0)) or + (wayG_val(0) and upd_watch_tid3_wayG(1)); +ex4_lost_wayH(3) <= ex4_lose_watch_q(3) and ex4_way_hit_q(7) and ex4_wayH_val_q(5); +upd_watch_tid3_wayH <= (clr_watch(3) or ex3_watch_clr_all(3)) & set_watch(3); +flush_wayH_d(5) <= (wayH_val(5) and not upd_watch_tid3_wayH(0)) or + (wayH_val(0) and upd_watch_tid3_wayH(1)); +binv_wayA_upd_d <= (ex3_wayA_hit and binv3_ex3_xuop_upd); +ex3_xuop_lost_watch_wayA <= or_reduce((wayA_val(2 to 5) and not ex3_thrd_id_q)) and ex3_store_instr_q and ex3_c_acc; +ex3_xuop_wayA_upd <= (ex3_wayA_hit and (ex3_xuop_upd_dir or ex3_xuop_lost_watch_wayA)); +ex4_xuop_wayA_upd_d <= ex3_xuop_wayA_upd; +ex5_xuop_wayA_upd_d <= ex4_xuop_wayA_upd_q; +binv_wayB_upd_d <= (ex3_wayB_hit and binv3_ex3_xuop_upd); +ex3_xuop_lost_watch_wayB <= or_reduce((wayB_val(2 to 5) and not ex3_thrd_id_q)) and ex3_store_instr_q and ex3_c_acc; +ex3_xuop_wayB_upd <= (ex3_wayB_hit and (ex3_xuop_upd_dir or ex3_xuop_lost_watch_wayB)); +ex4_xuop_wayB_upd_d <= ex3_xuop_wayB_upd; +ex5_xuop_wayB_upd_d <= ex4_xuop_wayB_upd_q; +binv_wayC_upd_d <= (ex3_wayC_hit and binv3_ex3_xuop_upd); +ex3_xuop_lost_watch_wayC <= or_reduce((wayC_val(2 to 5) and not ex3_thrd_id_q)) and ex3_store_instr_q and ex3_c_acc; +ex3_xuop_wayC_upd <= (ex3_wayC_hit and (ex3_xuop_upd_dir or ex3_xuop_lost_watch_wayC)); +ex4_xuop_wayC_upd_d <= ex3_xuop_wayC_upd; +ex5_xuop_wayC_upd_d <= ex4_xuop_wayC_upd_q; +binv_wayD_upd_d <= (ex3_wayD_hit and binv3_ex3_xuop_upd); +ex3_xuop_lost_watch_wayD <= or_reduce((wayD_val(2 to 5) and not ex3_thrd_id_q)) and ex3_store_instr_q and ex3_c_acc; +ex3_xuop_wayD_upd <= (ex3_wayD_hit and (ex3_xuop_upd_dir or ex3_xuop_lost_watch_wayD)); +ex4_xuop_wayD_upd_d <= ex3_xuop_wayD_upd; +ex5_xuop_wayD_upd_d <= ex4_xuop_wayD_upd_q; +binv_wayE_upd_d <= (ex3_wayE_hit and binv3_ex3_xuop_upd); +ex3_xuop_lost_watch_wayE <= or_reduce((wayE_val(2 to 5) and not ex3_thrd_id_q)) and ex3_store_instr_q and ex3_c_acc; +ex3_xuop_wayE_upd <= (ex3_wayE_hit and (ex3_xuop_upd_dir or ex3_xuop_lost_watch_wayE)); +ex4_xuop_wayE_upd_d <= ex3_xuop_wayE_upd; +ex5_xuop_wayE_upd_d <= ex4_xuop_wayE_upd_q; +binv_wayF_upd_d <= (ex3_wayF_hit and binv3_ex3_xuop_upd); +ex3_xuop_lost_watch_wayF <= or_reduce((wayF_val(2 to 5) and not ex3_thrd_id_q)) and ex3_store_instr_q and ex3_c_acc; +ex3_xuop_wayF_upd <= (ex3_wayF_hit and (ex3_xuop_upd_dir or ex3_xuop_lost_watch_wayF)); +ex4_xuop_wayF_upd_d <= ex3_xuop_wayF_upd; +ex5_xuop_wayF_upd_d <= ex4_xuop_wayF_upd_q; +binv_wayG_upd_d <= (ex3_wayG_hit and binv3_ex3_xuop_upd); +ex3_xuop_lost_watch_wayG <= or_reduce((wayG_val(2 to 5) and not ex3_thrd_id_q)) and ex3_store_instr_q and ex3_c_acc; +ex3_xuop_wayG_upd <= (ex3_wayG_hit and (ex3_xuop_upd_dir or ex3_xuop_lost_watch_wayG)); +ex4_xuop_wayG_upd_d <= ex3_xuop_wayG_upd; +ex5_xuop_wayG_upd_d <= ex4_xuop_wayG_upd_q; +binv_wayH_upd_d <= (ex3_wayH_hit and binv3_ex3_xuop_upd); +ex3_xuop_lost_watch_wayH <= or_reduce((wayH_val(2 to 5) and not ex3_thrd_id_q)) and ex3_store_instr_q and ex3_c_acc; +ex3_xuop_wayH_upd <= (ex3_wayH_hit and (ex3_xuop_upd_dir or ex3_xuop_lost_watch_wayH)); +ex4_xuop_wayH_upd_d <= ex3_xuop_wayH_upd; +ex5_xuop_wayH_upd_d <= ex4_xuop_wayH_upd_q; +binv4_ex4_lock_set <= ex4_wayA_val_q(1) or ex4_wayB_val_q(1) or ex4_wayC_val_q(1) or ex4_wayD_val_q(1) or + ex4_wayE_val_q(1) or ex4_wayF_val_q(1) or ex4_wayG_val_q(1) or ex4_wayH_val_q(1); +binv4_ex4_thrd_watch <= ex4_wayA_val_q(2 to 5) or ex4_wayB_val_q(2 to 5) or ex4_wayC_val_q(2 to 5) or ex4_wayD_val_q(2 to 5) or + ex4_wayE_val_q(2 to 5) or ex4_wayF_val_q(2 to 5) or ex4_wayG_val_q(2 to 5) or ex4_wayH_val_q(2 to 5); +wayA_watch_value <= (ex4_thrd_id_q(0) and ex4_wayA_val_q(2)) or (ex4_thrd_id_q(1) and ex4_wayA_val_q(3)) or + (ex4_thrd_id_q(2) and ex4_wayA_val_q(4)) or (ex4_thrd_id_q(3) and ex4_wayA_val_q(5)); +wayB_watch_value <= (ex4_thrd_id_q(0) and ex4_wayB_val_q(2)) or (ex4_thrd_id_q(1) and ex4_wayB_val_q(3)) or + (ex4_thrd_id_q(2) and ex4_wayB_val_q(4)) or (ex4_thrd_id_q(3) and ex4_wayB_val_q(5)); +wayC_watch_value <= (ex4_thrd_id_q(0) and ex4_wayC_val_q(2)) or (ex4_thrd_id_q(1) and ex4_wayC_val_q(3)) or + (ex4_thrd_id_q(2) and ex4_wayC_val_q(4)) or (ex4_thrd_id_q(3) and ex4_wayC_val_q(5)); +wayD_watch_value <= (ex4_thrd_id_q(0) and ex4_wayD_val_q(2)) or (ex4_thrd_id_q(1) and ex4_wayD_val_q(3)) or + (ex4_thrd_id_q(2) and ex4_wayD_val_q(4)) or (ex4_thrd_id_q(3) and ex4_wayD_val_q(5)); +wayE_watch_value <= (ex4_thrd_id_q(0) and ex4_wayE_val_q(2)) or (ex4_thrd_id_q(1) and ex4_wayE_val_q(3)) or + (ex4_thrd_id_q(2) and ex4_wayE_val_q(4)) or (ex4_thrd_id_q(3) and ex4_wayE_val_q(5)); +wayF_watch_value <= (ex4_thrd_id_q(0) and ex4_wayF_val_q(2)) or (ex4_thrd_id_q(1) and ex4_wayF_val_q(3)) or + (ex4_thrd_id_q(2) and ex4_wayF_val_q(4)) or (ex4_thrd_id_q(3) and ex4_wayF_val_q(5)); +wayG_watch_value <= (ex4_thrd_id_q(0) and ex4_wayG_val_q(2)) or (ex4_thrd_id_q(1) and ex4_wayG_val_q(3)) or + (ex4_thrd_id_q(2) and ex4_wayG_val_q(4)) or (ex4_thrd_id_q(3) and ex4_wayG_val_q(5)); +wayH_watch_value <= (ex4_thrd_id_q(0) and ex4_wayH_val_q(2)) or (ex4_thrd_id_q(1) and ex4_wayH_val_q(3)) or + (ex4_thrd_id_q(2) and ex4_wayH_val_q(4)) or (ex4_thrd_id_q(3) and ex4_wayH_val_q(5)); +ex4_curr_watch <= (ex4_way_hit_q(0) and wayA_watch_value) or (ex4_way_hit_q(1) and wayB_watch_value) or + (ex4_way_hit_q(2) and wayC_watch_value) or (ex4_way_hit_q(3) and wayD_watch_value) or + (ex4_way_hit_q(4) and wayE_watch_value) or (ex4_way_hit_q(5) and wayF_watch_value) or + (ex4_way_hit_q(6) and wayG_watch_value) or (ex4_way_hit_q(7) and wayH_watch_value); +stm_watchlost_sel <= (ex4_thrd_id_q(0) and stm_watchlost(0)) or (ex4_thrd_id_q(1) and stm_watchlost(1)) or + (ex4_thrd_id_q(2) and stm_watchlost(2)) or (ex4_thrd_id_q(3) and stm_watchlost(3)); +with ex4_watch_set_q select + ex5_cr_watch_d <= stm_watchlost_sel when '0', + ex4_curr_watch when others; +ex4_lost_watch(0) <= ex4_lost_wayA(0) or ex4_lost_wayB(0) or ex4_lost_wayC(0) or ex4_lost_wayD(0) or + ex4_lost_wayE(0) or ex4_lost_wayF(0) or ex4_lost_wayG(0) or ex4_lost_wayH(0) or + ex4_perr_watch_lost_q(0); + WITH ex4_watchlost_set_q(0) SELECT ex4_lost_watch_upd(0) <= ex4_lost_watch(0) when '0', + ex4_l_fld_b1_q when others; +ex4_lost_watch(1) <= ex4_lost_wayA(1) or ex4_lost_wayB(1) or ex4_lost_wayC(1) or ex4_lost_wayD(1) or + ex4_lost_wayE(1) or ex4_lost_wayF(1) or ex4_lost_wayG(1) or ex4_lost_wayH(1) or + ex4_perr_watch_lost_q(1); + WITH ex4_watchlost_set_q(1) SELECT ex4_lost_watch_upd(1) <= ex4_lost_watch(1) when '0', + ex4_l_fld_b1_q when others; +ex4_lost_watch(2) <= ex4_lost_wayA(2) or ex4_lost_wayB(2) or ex4_lost_wayC(2) or ex4_lost_wayD(2) or + ex4_lost_wayE(2) or ex4_lost_wayF(2) or ex4_lost_wayG(2) or ex4_lost_wayH(2) or + ex4_perr_watch_lost_q(2); + WITH ex4_watchlost_set_q(2) SELECT ex4_lost_watch_upd(2) <= ex4_lost_watch(2) when '0', + ex4_l_fld_b1_q when others; +ex4_lost_watch(3) <= ex4_lost_wayA(3) or ex4_lost_wayB(3) or ex4_lost_wayC(3) or ex4_lost_wayD(3) or + ex4_lost_wayE(3) or ex4_lost_wayF(3) or ex4_lost_wayG(3) or ex4_lost_wayH(3) or + ex4_perr_watch_lost_q(3); + WITH ex4_watchlost_set_q(3) SELECT ex4_lost_watch_upd(3) <= ex4_lost_watch(3) when '0', + ex4_l_fld_b1_q when others; +ex4_watchSet_coll_d <= rel_val_stg2_q and ex3_watch_set_q and (rel24_congr_cl_q = ex3_congr_cl_q); +watchSet_rel_way_coll <= gate((reload_way_clr_q and ex4_way_hit_q), ex4_watchSet_coll_q); +watchSet_rel_coll_val <= gate(ex4_thrd_id_q, or_reduce(watchSet_rel_way_coll)); +ex5_lost_watch_upd_d <= ex4_lost_watch_upd or watchSet_rel_coll_val or ex4_multihit_watch_lost; +ex4_watchlost_set_d <= ex3_watch_clr_all; +ex5_watchlost_set_d <= ex4_lost_watch or ex4_watchlost_set_q or watchSet_rel_coll_val or ex4_multihit_watch_lost; +ex5_watch_clr_all_d <= gate(ex4_watch_clr_all_q, not ex4_stg_flush); +ex6_watch_clr_all_d <= gate(ex5_watch_clr_all_q, not ex5_stg_flush); +ex5_watch_clr_all_val_d <= or_reduce(ex4_watch_clr_all_q); +u_th0i: tagA_hit_b <= not tagA_hit; +u_hw0i: xu_op_hit_wayA_b <= not (wayA_val(0) and tagA_hit); +u_hw0: xu_op_hit_wayA <= not xu_op_hit_wayA_b; +u_hw0b: xu_op_hit_wayA_dly_b <= not xu_op_hit_wayA; +u_th1i: tagB_hit_b <= not tagB_hit; +u_hw1i: xu_op_hit_wayB_b <= not (wayB_val(0) and tagB_hit); +u_hw1: xu_op_hit_wayB <= not xu_op_hit_wayB_b; +u_hw1b: xu_op_hit_wayB_dly_b <= not xu_op_hit_wayB; +u_th2i: tagC_hit_b <= not tagC_hit; +u_hw2i: xu_op_hit_wayC_b <= not (wayC_val(0) and tagC_hit); +u_hw2: xu_op_hit_wayC <= not xu_op_hit_wayC_b; +u_hw2b: xu_op_hit_wayC_dly_b <= not xu_op_hit_wayC; +u_th3i: tagD_hit_b <= not tagD_hit; +u_hw3i: xu_op_hit_wayD_b <= not (wayD_val(0) and tagD_hit); +u_hw3: xu_op_hit_wayD <= not xu_op_hit_wayD_b; +u_hw3b: xu_op_hit_wayD_dly_b <= not xu_op_hit_wayD; +u_th4i: tagE_hit_b <= not tagE_hit; +u_hw4i: xu_op_hit_wayE_b <= not (wayE_val(0) and tagE_hit); +u_hw4: xu_op_hit_wayE <= not xu_op_hit_wayE_b; +u_hw4b: xu_op_hit_wayE_dly_b <= not xu_op_hit_wayE; +u_th5i: tagF_hit_b <= not tagF_hit; +u_hw5i: xu_op_hit_wayF_b <= not (wayF_val(0) and tagF_hit); +u_hw5: xu_op_hit_wayF <= not xu_op_hit_wayF_b; +u_hw5b: xu_op_hit_wayF_dly_b <= not xu_op_hit_wayF; +u_th6i: tagG_hit_b <= not tagG_hit; +u_hw6i: xu_op_hit_wayG_b <= not (wayG_val(0) and tagG_hit); +u_hw6: xu_op_hit_wayG <= not xu_op_hit_wayG_b; +u_hw6b: xu_op_hit_wayG_dly_b <= not xu_op_hit_wayG; +u_th7i: tagH_hit_b <= not tagH_hit; +u_hw7i: xu_op_hit_wayH_b <= not (wayH_val(0) and tagH_hit); +u_hw7: xu_op_hit_wayH <= not xu_op_hit_wayH_b; +u_hw7b: xu_op_hit_wayH_dly_b <= not xu_op_hit_wayH; +inval_clr_lck <= (inval_clr_lck_wA_q and binv_wayA_upd_q) or (inval_clr_lck_wB_q and binv_wayB_upd_q) or + (inval_clr_lck_wC_q and binv_wayC_upd_q) or (inval_clr_lck_wD_q and binv_wayD_upd_q) or + (inval_clr_lck_wE_q and binv_wayE_upd_q) or (inval_clr_lck_wF_q and binv_wayF_upd_q) or + (inval_clr_lck_wG_q and binv_wayG_upd_q) or (inval_clr_lck_wH_q and binv_wayH_upd_q); +xucr0_cslc_xuop_d <= inval_clr_lck and ex4_xuop_val; +xucr0_cslc_binv_d <= rel_lock_lost or dcperr_lock_lost_q or ex4_perr_lck_lost_q or + ex4_multihit_lock_lost or binv5_inval_lock_val_q or (rel_l1dump_cslc_q and not rel4_ecc_err); +ex3_cClass_upd_way_a <= ex3_cClass_wayA_hit; +ex3_cClass_upd_way_b <= ex3_cClass_wayB_hit; +ex3_cClass_upd_way_c <= ex3_cClass_wayC_hit; +ex3_cClass_upd_way_d <= ex3_cClass_wayD_hit; +ex3_cClass_upd_way_e <= ex3_cClass_wayE_hit; +ex3_cClass_upd_way_f <= ex3_cClass_wayF_hit; +ex3_cClass_upd_way_g <= ex3_cClass_wayG_hit; +ex3_cClass_upd_way_h <= ex3_cClass_wayH_hit; +u_mh1_a01: hit_and_01_b <= not( xu_op_hit_wayA and xu_op_hit_wayB ); +u_mh1_a23: hit_and_23_b <= not( xu_op_hit_wayC and xu_op_hit_wayD ); +u_mh1_a45: hit_and_45_b <= not( xu_op_hit_wayE and xu_op_hit_wayF ); +u_mh1_a67: hit_and_67_b <= not( xu_op_hit_wayG and xu_op_hit_wayH ); +u_mh1_o01: hit_or_01_b <= not( xu_op_hit_wayA or xu_op_hit_wayB ); +u_mh1_o23: hit_or_23_b <= not( xu_op_hit_wayC or xu_op_hit_wayD ); +u_mh1_o45: hit_or_45_b <= not( xu_op_hit_wayE or xu_op_hit_wayF ); +u_mh1_o67: hit_or_67_b <= not( xu_op_hit_wayG or xu_op_hit_wayH ); +u_mh1_o13: hit_or_13_b <= not( xu_op_hit_wayB or xu_op_hit_wayD ); +u_mh1_o57: hit_or_57_b <= not( xu_op_hit_wayF or xu_op_hit_wayH ); +u_mh2_o0123: hit_or_0123 <= not( hit_or_01_b and hit_or_23_b ); +u_mh2_o4567: hit_or_4567 <= not( hit_or_45_b and hit_or_67_b ); +u_mh2_o1357: hit_or_1357 <= not( hit_or_13_b and hit_or_57_b ); +u_mh2_o2367: hit_or_2367 <= not( hit_or_23_b and hit_or_67_b ); +u_mh2_a0123: hit_and_0123 <= not( hit_or_01_b or hit_or_23_b ); +u_mh2_a4567: hit_and_4567 <= not( hit_or_45_b or hit_or_67_b ); +u_mh2_err0: multi_hit_err2_0 <= not( hit_and_01_b and hit_and_23_b ); +u_mh2_err1: multi_hit_err2_1 <= not( hit_and_45_b and hit_and_67_b ); +u_mh3_o: hit_or_01234567_b <= not( hit_or_0123 or hit_or_4567 ); +u_mh3_err0: multi_hit_err3_b(0) <= not( hit_or_0123 and hit_or_4567 ); +u_mh3_err1: multi_hit_err3_b(1) <= not( hit_and_0123 or hit_and_4567 ); +u_mh3_err2: multi_hit_err3_b(2) <= not( multi_hit_err2_0 or multi_hit_err2_1 ); +u_henc_0: hit_enc_b(0) <= not( hit_or_4567 ); +u_henc_1: hit_enc_b(1) <= not( hit_or_2367 ); +u_henc_2: hit_enc_b(2) <= not( hit_or_1357 ); +u_mh4_0: ex3_dir_multihit_val_0 <= not( multi_hit_err3_b(0) and multi_hit_err3_b(1) ); +u_mh4_1: ex3_dir_multihit_val_1 <= not( multi_hit_err3_b(2) and inj_dir_multihit_b ); +u_mh5: ex3_dir_multihit_val_b <= not( ex3_dir_multihit_val_0 or ex3_dir_multihit_val_1 ); +u_mh6: ex3_dir_multihit_val <= not ex3_dir_multihit_val_b ; +ex4_n_lsu_ddmh_flush_b_d <= (others=>ex3_dir_multihit_val); +ex4_dir_multihit_val <= binv4_ex4_dir_val_q and not ex4_dir_multihit_val_b_q; +inj_dir_multihit_b <= not (inj_dir_multihit_q and binv3_ex3_dir_val); +ex4_multihit_watch_lost <= gate(binv4_ex4_thrd_watch, ex4_dir_multihit_val); +ex4_multihit_lock_lost <= binv4_ex4_lock_set and ex4_dir_multihit_val; +ex4_err_det_way_d(0) <= perr_way_det_wayA; +perr_way_det_wayA <= wayA_val(0) and ex3_tag_way_perr(0); +dirpar_err_lock_lost(0) <= wayA_val(1) and ex3_tag_way_perr(0); +perr_wayA_watch_lost <= gate(wayA_val(2 to 5),ex3_tag_way_perr(0)); +ex4_err_det_way_d(1) <= perr_way_det_wayB; +perr_way_det_wayB <= wayB_val(0) and ex3_tag_way_perr(1); +dirpar_err_lock_lost(1) <= wayB_val(1) and ex3_tag_way_perr(1); +perr_wayB_watch_lost <= gate(wayB_val(2 to 5),ex3_tag_way_perr(1)); +ex4_err_det_way_d(2) <= perr_way_det_wayC; +perr_way_det_wayC <= wayC_val(0) and ex3_tag_way_perr(2); +dirpar_err_lock_lost(2) <= wayC_val(1) and ex3_tag_way_perr(2); +perr_wayC_watch_lost <= gate(wayC_val(2 to 5),ex3_tag_way_perr(2)); +ex4_err_det_way_d(3) <= perr_way_det_wayD; +perr_way_det_wayD <= wayD_val(0) and ex3_tag_way_perr(3); +dirpar_err_lock_lost(3) <= wayD_val(1) and ex3_tag_way_perr(3); +perr_wayD_watch_lost <= gate(wayD_val(2 to 5),ex3_tag_way_perr(3)); +ex4_err_det_way_d(4) <= perr_way_det_wayE; +perr_way_det_wayE <= wayE_val(0) and ex3_tag_way_perr(4); +dirpar_err_lock_lost(4) <= wayE_val(1) and ex3_tag_way_perr(4); +perr_wayE_watch_lost <= gate(wayE_val(2 to 5),ex3_tag_way_perr(4)); +ex4_err_det_way_d(5) <= perr_way_det_wayF; +perr_way_det_wayF <= wayF_val(0) and ex3_tag_way_perr(5); +dirpar_err_lock_lost(5) <= wayF_val(1) and ex3_tag_way_perr(5); +perr_wayF_watch_lost <= gate(wayF_val(2 to 5),ex3_tag_way_perr(5)); +ex4_err_det_way_d(6) <= perr_way_det_wayG; +perr_way_det_wayG <= wayG_val(0) and ex3_tag_way_perr(6); +dirpar_err_lock_lost(6) <= wayG_val(1) and ex3_tag_way_perr(6); +perr_wayG_watch_lost <= gate(wayG_val(2 to 5),ex3_tag_way_perr(6)); +ex4_err_det_way_d(7) <= perr_way_det_wayH; +perr_way_det_wayH <= wayH_val(0) and ex3_tag_way_perr(7); +dirpar_err_lock_lost(7) <= wayH_val(1) and ex3_tag_way_perr(7); +perr_wayH_watch_lost <= gate(wayH_val(2 to 5),ex3_tag_way_perr(7)); +ex4_perr_lck_lost_d <= or_reduce(dirpar_err_lock_lost); +ex4_perr_watch_lost_d <= perr_wayA_watch_lost or perr_wayB_watch_lost or perr_wayC_watch_lost or perr_wayD_watch_lost or + perr_wayE_watch_lost or perr_wayF_watch_lost or perr_wayG_watch_lost or perr_wayH_watch_lost; +ex3_dir_perr_val <= perr_way_det_wayA or perr_way_det_wayB or perr_way_det_wayC or perr_way_det_wayD or + perr_way_det_wayE or perr_way_det_wayF or perr_way_det_wayG or perr_way_det_wayH; +ex4_dir_err_val_d <= ex3_dir_perr_val; +ex5_dir_err_val_d <= ex4_dir_err_val_q or ex4_dir_multihit_val; +ex6_dir_err_val_d <= ex5_dir_err_val_q; +derr2_stg_act_d <= ex6_dir_err_val_q; +derr3_stg_act_d <= derr2_stg_act_q; +derr4_stg_act_d <= derr3_stg_act_q; +derr5_stg_act_d <= derr4_stg_act_q; +ex3L1Hit: ex3_l1hit <= not hit_or_01234567_b; +ex3L1Miss: ex3_l1miss <= not ex3_l1hit; +ex3_hit <= not ex3_l1miss; +ex4_miss <= not ex4_miss_q; +ex4_way_hit_d <= not (xu_op_hit_wayA_dly_b & xu_op_hit_wayB_dly_b & xu_op_hit_wayC_dly_b & xu_op_hit_wayD_dly_b & + xu_op_hit_wayE_dly_b & xu_op_hit_wayF_dly_b & xu_op_hit_wayG_dly_b & xu_op_hit_wayH_dly_b); +ex5_way_hit_d <= ex4_way_hit_q; +ex6_way_hit_d <= ex5_way_hit_q; +ex3_xuop_up_addr_b <= hit_enc_b(0 to 2); +rel_dcarr_addr_sel <= (others=>rel_dcarr_addr_en); +rel_dcarr_addr_sel_b <= (others=>(not rel_dcarr_addr_en)); +congr_cl_ex3_ex4_cmp_d <= congr_cl_ex2_ex3_cmp_q; +congr_cl_ex3_ex5_cmp_d <= congr_cl_ex2_ex4_cmp_q; +congr_cl_ex3_ex6_cmp_d <= congr_cl_ex2_ex5_cmp_q; +congr_cl_ex4_ex5_cmp_d <= congr_cl_ex3_ex4_cmp_q; +congr_cl_ex4_ex6_cmp_d <= congr_cl_ex3_ex5_cmp_q; +congr_cl_ex4_ex7_cmp_d <= congr_cl_ex3_ex6_cmp_q; +binv4_ex4_way_upd <= binv_wayA_upd1 & binv_wayB_upd1 & binv_wayC_upd1 & binv_wayD_upd1 & + binv_wayE_upd1 & binv_wayF_upd1 & binv_wayG_upd1 & binv_wayH_upd1; +binv5_ex5_way_upd <= binv_wayA_upd2_q & binv_wayB_upd2_q & binv_wayC_upd2_q & binv_wayD_upd2_q & + binv_wayE_upd2_q & binv_wayF_upd2_q & binv_wayG_upd2_q & binv_wayH_upd2_q; +binv6_ex6_way_upd <= binv_wayA_upd3_q & binv_wayB_upd3_q & binv_wayC_upd3_q & binv_wayD_upd3_q & + binv_wayE_upd3_q & binv_wayF_upd3_q & binv_wayG_upd3_q & binv_wayH_upd3_q; +binv7_ex7_way_upd_d <= binv6_ex6_way_upd; +binv4_ex4_dir_data <= gate(flush_wayA_data1(1 to 5), binv4_ex4_way_upd(0)) or gate(flush_wayB_data1(1 to 5), binv4_ex4_way_upd(1)) or + gate(flush_wayC_data1(1 to 5), binv4_ex4_way_upd(2)) or gate(flush_wayD_data1(1 to 5), binv4_ex4_way_upd(3)) or + gate(flush_wayE_data1(1 to 5), binv4_ex4_way_upd(4)) or gate(flush_wayF_data1(1 to 5), binv4_ex4_way_upd(5)) or + gate(flush_wayG_data1(1 to 5), binv4_ex4_way_upd(6)) or gate(flush_wayH_data1(1 to 5), binv4_ex4_way_upd(7)); +binv5_ex5_dir_data_d <= binv4_ex4_dir_data; +binv6_ex6_dir_data_d <= binv5_ex5_dir_data_q; +binv7_ex7_dir_data_d <= binv6_ex6_dir_data_q; +binv4_inval_lck <= inval_clr_lck and back_inval_stg4_q and not binv4_coll_val; +binv4_inval_watch <= gate(ex4_lost_watch, (back_inval_stg4_q and not binv4_coll_val)); +binv4_ex5_coll <= (back_inval_stg4_q or ex4_dir_multihit_val) and congr_cl_ex4_ex5_cmp_q and or_reduce(ex4_way_hit_q and binv5_ex5_way_upd) and p0_wren_d; +binv4_ex6_coll <= (back_inval_stg4_q or ex4_dir_multihit_val) and congr_cl_ex4_ex6_cmp_q and or_reduce(ex4_way_hit_q and binv6_ex6_way_upd) and p0_wren_q; +binv4_ex7_coll <= (back_inval_stg4_q or ex4_dir_multihit_val) and congr_cl_ex4_ex7_cmp_q and or_reduce(ex4_way_hit_q and binv7_ex7_way_upd_q) and p0_wren_stg_q; +binv4_coll_val <= binv4_ex5_coll or binv4_ex6_coll or binv4_ex7_coll; +binv4_pri_byp_sel(0) <= binv4_ex5_coll; +binv4_pri_byp_sel(1) <= binv4_ex6_coll and not binv4_ex5_coll; +binv4_pri_byp_sel(2) <= binv4_ex7_coll and not (binv4_ex6_coll or binv4_ex5_coll); +binv4_byp_dir_data <= gate(binv5_ex5_dir_data_q, binv4_pri_byp_sel(0)) or + gate(binv6_ex6_dir_data_q, binv4_pri_byp_sel(1)) or + gate(binv7_ex7_dir_data_q, binv4_pri_byp_sel(2)); +binv5_inval_watch_val_d <= (binv4_byp_dir_data(2 to 5) and not binv4_ex4_dir_data(2 to 5)) or binv4_inval_watch; +binv5_inval_lock_val_d <= (binv4_byp_dir_data(1) and not binv4_ex4_dir_data(1)) or binv4_inval_lck; +dci_watch_lost <= (others=>dci_compl_q); +congr_cl_ex3_upd_wayA <= congr_cl_ex2_ex3_cmp_q and not ex3_thrd_m_q and ex3_xuop_wayA_upd and not ex3_stg_flush; +congr_cl_ex4_upd_wayA <= congr_cl_ex2_ex4_cmp_q and not ex4_thrd_m_q and ex4_xuop_wayA_upd_q and not ex4_stg_flush; +congr_cl_ex5_upd_wayA <= congr_cl_ex2_ex5_cmp_q and not ex5_thrd_m_q and ex5_xuop_wayA_upd_q and not ex5_stg_flush; +congr_cl_m_upd_wayA_d <= congr_cl_ex3_upd_wayA or congr_cl_ex4_upd_wayA or congr_cl_ex5_upd_wayA; +ex3_cClass_wayA_hit <= fxu_pipe_val and congr_cl_m_upd_wayA_q and wayA_val(0); +congr_cl_ex3_upd_wayB <= congr_cl_ex2_ex3_cmp_q and not ex3_thrd_m_q and ex3_xuop_wayB_upd and not ex3_stg_flush; +congr_cl_ex4_upd_wayB <= congr_cl_ex2_ex4_cmp_q and not ex4_thrd_m_q and ex4_xuop_wayB_upd_q and not ex4_stg_flush; +congr_cl_ex5_upd_wayB <= congr_cl_ex2_ex5_cmp_q and not ex5_thrd_m_q and ex5_xuop_wayB_upd_q and not ex5_stg_flush; +congr_cl_m_upd_wayB_d <= congr_cl_ex3_upd_wayB or congr_cl_ex4_upd_wayB or congr_cl_ex5_upd_wayB; +ex3_cClass_wayB_hit <= fxu_pipe_val and congr_cl_m_upd_wayB_q and wayB_val(0); +congr_cl_ex3_upd_wayC <= congr_cl_ex2_ex3_cmp_q and not ex3_thrd_m_q and ex3_xuop_wayC_upd and not ex3_stg_flush; +congr_cl_ex4_upd_wayC <= congr_cl_ex2_ex4_cmp_q and not ex4_thrd_m_q and ex4_xuop_wayC_upd_q and not ex4_stg_flush; +congr_cl_ex5_upd_wayC <= congr_cl_ex2_ex5_cmp_q and not ex5_thrd_m_q and ex5_xuop_wayC_upd_q and not ex5_stg_flush; +congr_cl_m_upd_wayC_d <= congr_cl_ex3_upd_wayC or congr_cl_ex4_upd_wayC or congr_cl_ex5_upd_wayC; +ex3_cClass_wayC_hit <= fxu_pipe_val and congr_cl_m_upd_wayC_q and wayC_val(0); +congr_cl_ex3_upd_wayD <= congr_cl_ex2_ex3_cmp_q and not ex3_thrd_m_q and ex3_xuop_wayD_upd and not ex3_stg_flush; +congr_cl_ex4_upd_wayD <= congr_cl_ex2_ex4_cmp_q and not ex4_thrd_m_q and ex4_xuop_wayD_upd_q and not ex4_stg_flush; +congr_cl_ex5_upd_wayD <= congr_cl_ex2_ex5_cmp_q and not ex5_thrd_m_q and ex5_xuop_wayD_upd_q and not ex5_stg_flush; +congr_cl_m_upd_wayD_d <= congr_cl_ex3_upd_wayD or congr_cl_ex4_upd_wayD or congr_cl_ex5_upd_wayD; +ex3_cClass_wayD_hit <= fxu_pipe_val and congr_cl_m_upd_wayD_q and wayD_val(0); +congr_cl_ex3_upd_wayE <= congr_cl_ex2_ex3_cmp_q and not ex3_thrd_m_q and ex3_xuop_wayE_upd and not ex3_stg_flush; +congr_cl_ex4_upd_wayE <= congr_cl_ex2_ex4_cmp_q and not ex4_thrd_m_q and ex4_xuop_wayE_upd_q and not ex4_stg_flush; +congr_cl_ex5_upd_wayE <= congr_cl_ex2_ex5_cmp_q and not ex5_thrd_m_q and ex5_xuop_wayE_upd_q and not ex5_stg_flush; +congr_cl_m_upd_wayE_d <= congr_cl_ex3_upd_wayE or congr_cl_ex4_upd_wayE or congr_cl_ex5_upd_wayE; +ex3_cClass_wayE_hit <= fxu_pipe_val and congr_cl_m_upd_wayE_q and wayE_val(0); +congr_cl_ex3_upd_wayF <= congr_cl_ex2_ex3_cmp_q and not ex3_thrd_m_q and ex3_xuop_wayF_upd and not ex3_stg_flush; +congr_cl_ex4_upd_wayF <= congr_cl_ex2_ex4_cmp_q and not ex4_thrd_m_q and ex4_xuop_wayF_upd_q and not ex4_stg_flush; +congr_cl_ex5_upd_wayF <= congr_cl_ex2_ex5_cmp_q and not ex5_thrd_m_q and ex5_xuop_wayF_upd_q and not ex5_stg_flush; +congr_cl_m_upd_wayF_d <= congr_cl_ex3_upd_wayF or congr_cl_ex4_upd_wayF or congr_cl_ex5_upd_wayF; +ex3_cClass_wayF_hit <= fxu_pipe_val and congr_cl_m_upd_wayF_q and wayF_val(0); +congr_cl_ex3_upd_wayG <= congr_cl_ex2_ex3_cmp_q and not ex3_thrd_m_q and ex3_xuop_wayG_upd and not ex3_stg_flush; +congr_cl_ex4_upd_wayG <= congr_cl_ex2_ex4_cmp_q and not ex4_thrd_m_q and ex4_xuop_wayG_upd_q and not ex4_stg_flush; +congr_cl_ex5_upd_wayG <= congr_cl_ex2_ex5_cmp_q and not ex5_thrd_m_q and ex5_xuop_wayG_upd_q and not ex5_stg_flush; +congr_cl_m_upd_wayG_d <= congr_cl_ex3_upd_wayG or congr_cl_ex4_upd_wayG or congr_cl_ex5_upd_wayG; +ex3_cClass_wayG_hit <= fxu_pipe_val and congr_cl_m_upd_wayG_q and wayG_val(0); +congr_cl_ex3_upd_wayH <= congr_cl_ex2_ex3_cmp_q and not ex3_thrd_m_q and ex3_xuop_wayH_upd and not ex3_stg_flush; +congr_cl_ex4_upd_wayH <= congr_cl_ex2_ex4_cmp_q and not ex4_thrd_m_q and ex4_xuop_wayH_upd_q and not ex4_stg_flush; +congr_cl_ex5_upd_wayH <= congr_cl_ex2_ex5_cmp_q and not ex5_thrd_m_q and ex5_xuop_wayH_upd_q and not ex5_stg_flush; +congr_cl_m_upd_wayH_d <= congr_cl_ex3_upd_wayH or congr_cl_ex4_upd_wayH or congr_cl_ex5_upd_wayH; +ex3_cClass_wayH_hit <= fxu_pipe_val and congr_cl_m_upd_wayH_q and wayH_val(0); +ex3_wclr_all_upd_val <= ex3_watch_clr_all_q and not ex3_thrd_m_q and not ex3_stg_flush; +ex4_wclr_all_upd_val <= ex4_wclr_all_val_q and not ex4_thrd_m_q and not ex4_stg_flush; +ex5_wclr_all_upd_val <= ex5_wclr_all_val_q and not ex5_thrd_m_q and not ex5_stg_flush; +ex6_wclr_all_upd_val <= ex6_wclr_all_val_q and not ex6_thrd_m_q; +ex3_wclr_all_upd_d <= ex3_wclr_all_upd_val or ex4_wclr_all_upd_val or ex5_wclr_all_upd_val or ex6_wclr_all_upd_val; +with rel_congr_cl_q select + rel_arr_wayA_val <= + congr_cl0_wA_q when "00000", + congr_cl1_wA_q when "00001", + congr_cl2_wA_q when "00010", + congr_cl3_wA_q when "00011", + congr_cl4_wA_q when "00100", + congr_cl5_wA_q when "00101", + congr_cl6_wA_q when "00110", + congr_cl7_wA_q when "00111", + congr_cl8_wA_q when "01000", + congr_cl9_wA_q when "01001", + congr_cl10_wA_q when "01010", + congr_cl11_wA_q when "01011", + congr_cl12_wA_q when "01100", + congr_cl13_wA_q when "01101", + congr_cl14_wA_q when "01110", + congr_cl15_wA_q when "01111", + congr_cl16_wA_q when "10000", + congr_cl17_wA_q when "10001", + congr_cl18_wA_q when "10010", + congr_cl19_wA_q when "10011", + congr_cl20_wA_q when "10100", + congr_cl21_wA_q when "10101", + congr_cl22_wA_q when "10110", + congr_cl23_wA_q when "10111", + congr_cl24_wA_q when "11000", + congr_cl25_wA_q when "11001", + congr_cl26_wA_q when "11010", + congr_cl27_wA_q when "11011", + congr_cl28_wA_q when "11100", + congr_cl29_wA_q when "11101", + congr_cl30_wA_q when "11110", + congr_cl31_wA_q when others; +p1_arr_wayA_rd <= rel_arr_wayA_val; +with rel_congr_cl_q select + rel_arr_wayB_val <= + congr_cl0_wB_q when "00000", + congr_cl1_wB_q when "00001", + congr_cl2_wB_q when "00010", + congr_cl3_wB_q when "00011", + congr_cl4_wB_q when "00100", + congr_cl5_wB_q when "00101", + congr_cl6_wB_q when "00110", + congr_cl7_wB_q when "00111", + congr_cl8_wB_q when "01000", + congr_cl9_wB_q when "01001", + congr_cl10_wB_q when "01010", + congr_cl11_wB_q when "01011", + congr_cl12_wB_q when "01100", + congr_cl13_wB_q when "01101", + congr_cl14_wB_q when "01110", + congr_cl15_wB_q when "01111", + congr_cl16_wB_q when "10000", + congr_cl17_wB_q when "10001", + congr_cl18_wB_q when "10010", + congr_cl19_wB_q when "10011", + congr_cl20_wB_q when "10100", + congr_cl21_wB_q when "10101", + congr_cl22_wB_q when "10110", + congr_cl23_wB_q when "10111", + congr_cl24_wB_q when "11000", + congr_cl25_wB_q when "11001", + congr_cl26_wB_q when "11010", + congr_cl27_wB_q when "11011", + congr_cl28_wB_q when "11100", + congr_cl29_wB_q when "11101", + congr_cl30_wB_q when "11110", + congr_cl31_wB_q when others; +p1_arr_wayB_rd <= rel_arr_wayB_val; +with rel_congr_cl_q select + rel_arr_wayC_val <= + congr_cl0_wC_q when "00000", + congr_cl1_wC_q when "00001", + congr_cl2_wC_q when "00010", + congr_cl3_wC_q when "00011", + congr_cl4_wC_q when "00100", + congr_cl5_wC_q when "00101", + congr_cl6_wC_q when "00110", + congr_cl7_wC_q when "00111", + congr_cl8_wC_q when "01000", + congr_cl9_wC_q when "01001", + congr_cl10_wC_q when "01010", + congr_cl11_wC_q when "01011", + congr_cl12_wC_q when "01100", + congr_cl13_wC_q when "01101", + congr_cl14_wC_q when "01110", + congr_cl15_wC_q when "01111", + congr_cl16_wC_q when "10000", + congr_cl17_wC_q when "10001", + congr_cl18_wC_q when "10010", + congr_cl19_wC_q when "10011", + congr_cl20_wC_q when "10100", + congr_cl21_wC_q when "10101", + congr_cl22_wC_q when "10110", + congr_cl23_wC_q when "10111", + congr_cl24_wC_q when "11000", + congr_cl25_wC_q when "11001", + congr_cl26_wC_q when "11010", + congr_cl27_wC_q when "11011", + congr_cl28_wC_q when "11100", + congr_cl29_wC_q when "11101", + congr_cl30_wC_q when "11110", + congr_cl31_wC_q when others; +p1_arr_wayC_rd <= rel_arr_wayC_val; +with rel_congr_cl_q select + rel_arr_wayD_val <= + congr_cl0_wD_q when "00000", + congr_cl1_wD_q when "00001", + congr_cl2_wD_q when "00010", + congr_cl3_wD_q when "00011", + congr_cl4_wD_q when "00100", + congr_cl5_wD_q when "00101", + congr_cl6_wD_q when "00110", + congr_cl7_wD_q when "00111", + congr_cl8_wD_q when "01000", + congr_cl9_wD_q when "01001", + congr_cl10_wD_q when "01010", + congr_cl11_wD_q when "01011", + congr_cl12_wD_q when "01100", + congr_cl13_wD_q when "01101", + congr_cl14_wD_q when "01110", + congr_cl15_wD_q when "01111", + congr_cl16_wD_q when "10000", + congr_cl17_wD_q when "10001", + congr_cl18_wD_q when "10010", + congr_cl19_wD_q when "10011", + congr_cl20_wD_q when "10100", + congr_cl21_wD_q when "10101", + congr_cl22_wD_q when "10110", + congr_cl23_wD_q when "10111", + congr_cl24_wD_q when "11000", + congr_cl25_wD_q when "11001", + congr_cl26_wD_q when "11010", + congr_cl27_wD_q when "11011", + congr_cl28_wD_q when "11100", + congr_cl29_wD_q when "11101", + congr_cl30_wD_q when "11110", + congr_cl31_wD_q when others; +p1_arr_wayD_rd <= rel_arr_wayD_val; +with rel_congr_cl_q select + rel_arr_wayE_val <= + congr_cl0_wE_q when "00000", + congr_cl1_wE_q when "00001", + congr_cl2_wE_q when "00010", + congr_cl3_wE_q when "00011", + congr_cl4_wE_q when "00100", + congr_cl5_wE_q when "00101", + congr_cl6_wE_q when "00110", + congr_cl7_wE_q when "00111", + congr_cl8_wE_q when "01000", + congr_cl9_wE_q when "01001", + congr_cl10_wE_q when "01010", + congr_cl11_wE_q when "01011", + congr_cl12_wE_q when "01100", + congr_cl13_wE_q when "01101", + congr_cl14_wE_q when "01110", + congr_cl15_wE_q when "01111", + congr_cl16_wE_q when "10000", + congr_cl17_wE_q when "10001", + congr_cl18_wE_q when "10010", + congr_cl19_wE_q when "10011", + congr_cl20_wE_q when "10100", + congr_cl21_wE_q when "10101", + congr_cl22_wE_q when "10110", + congr_cl23_wE_q when "10111", + congr_cl24_wE_q when "11000", + congr_cl25_wE_q when "11001", + congr_cl26_wE_q when "11010", + congr_cl27_wE_q when "11011", + congr_cl28_wE_q when "11100", + congr_cl29_wE_q when "11101", + congr_cl30_wE_q when "11110", + congr_cl31_wE_q when others; +p1_arr_wayE_rd <= rel_arr_wayE_val; +with rel_congr_cl_q select + rel_arr_wayF_val <= + congr_cl0_wF_q when "00000", + congr_cl1_wF_q when "00001", + congr_cl2_wF_q when "00010", + congr_cl3_wF_q when "00011", + congr_cl4_wF_q when "00100", + congr_cl5_wF_q when "00101", + congr_cl6_wF_q when "00110", + congr_cl7_wF_q when "00111", + congr_cl8_wF_q when "01000", + congr_cl9_wF_q when "01001", + congr_cl10_wF_q when "01010", + congr_cl11_wF_q when "01011", + congr_cl12_wF_q when "01100", + congr_cl13_wF_q when "01101", + congr_cl14_wF_q when "01110", + congr_cl15_wF_q when "01111", + congr_cl16_wF_q when "10000", + congr_cl17_wF_q when "10001", + congr_cl18_wF_q when "10010", + congr_cl19_wF_q when "10011", + congr_cl20_wF_q when "10100", + congr_cl21_wF_q when "10101", + congr_cl22_wF_q when "10110", + congr_cl23_wF_q when "10111", + congr_cl24_wF_q when "11000", + congr_cl25_wF_q when "11001", + congr_cl26_wF_q when "11010", + congr_cl27_wF_q when "11011", + congr_cl28_wF_q when "11100", + congr_cl29_wF_q when "11101", + congr_cl30_wF_q when "11110", + congr_cl31_wF_q when others; +p1_arr_wayF_rd <= rel_arr_wayF_val; +with rel_congr_cl_q select + rel_arr_wayG_val <= + congr_cl0_wG_q when "00000", + congr_cl1_wG_q when "00001", + congr_cl2_wG_q when "00010", + congr_cl3_wG_q when "00011", + congr_cl4_wG_q when "00100", + congr_cl5_wG_q when "00101", + congr_cl6_wG_q when "00110", + congr_cl7_wG_q when "00111", + congr_cl8_wG_q when "01000", + congr_cl9_wG_q when "01001", + congr_cl10_wG_q when "01010", + congr_cl11_wG_q when "01011", + congr_cl12_wG_q when "01100", + congr_cl13_wG_q when "01101", + congr_cl14_wG_q when "01110", + congr_cl15_wG_q when "01111", + congr_cl16_wG_q when "10000", + congr_cl17_wG_q when "10001", + congr_cl18_wG_q when "10010", + congr_cl19_wG_q when "10011", + congr_cl20_wG_q when "10100", + congr_cl21_wG_q when "10101", + congr_cl22_wG_q when "10110", + congr_cl23_wG_q when "10111", + congr_cl24_wG_q when "11000", + congr_cl25_wG_q when "11001", + congr_cl26_wG_q when "11010", + congr_cl27_wG_q when "11011", + congr_cl28_wG_q when "11100", + congr_cl29_wG_q when "11101", + congr_cl30_wG_q when "11110", + congr_cl31_wG_q when others; +p1_arr_wayG_rd <= rel_arr_wayG_val; +with rel_congr_cl_q select + rel_arr_wayH_val <= + congr_cl0_wH_q when "00000", + congr_cl1_wH_q when "00001", + congr_cl2_wH_q when "00010", + congr_cl3_wH_q when "00011", + congr_cl4_wH_q when "00100", + congr_cl5_wH_q when "00101", + congr_cl6_wH_q when "00110", + congr_cl7_wH_q when "00111", + congr_cl8_wH_q when "01000", + congr_cl9_wH_q when "01001", + congr_cl10_wH_q when "01010", + congr_cl11_wH_q when "01011", + congr_cl12_wH_q when "01100", + congr_cl13_wH_q when "01101", + congr_cl14_wH_q when "01110", + congr_cl15_wH_q when "01111", + congr_cl16_wH_q when "10000", + congr_cl17_wH_q when "10001", + congr_cl18_wH_q when "10010", + congr_cl19_wH_q when "10011", + congr_cl20_wH_q when "10100", + congr_cl21_wH_q when "10101", + congr_cl22_wH_q when "10110", + congr_cl23_wH_q when "10111", + congr_cl24_wH_q when "11000", + congr_cl25_wH_q when "11001", + congr_cl26_wH_q when "11010", + congr_cl27_wH_q when "11011", + congr_cl28_wH_q when "11100", + congr_cl29_wH_q when "11101", + congr_cl30_wH_q when "11110", + congr_cl31_wH_q when others; +p1_arr_wayH_rd <= rel_arr_wayH_val; +congr_cl_rel13_ex3_cmp_d <= (rel_early_congr_cl = ex2_congr_cl_q); +congr_cl_rel13_ex4_cmp_d <= (rel_early_congr_cl = ex3_congr_cl_q); +congr_cl_rel13_ex5_cmp_d <= (rel_early_congr_cl = ex4_congr_cl_q); +congr_cl_rel13_ex6_cmp_d <= (rel_early_congr_cl = ex5_congr_cl_q); +congr_cl_rel13_relu_cmp_d <= (rel_early_congr_cl = rel24_congr_cl_q); +congr_cl_rel13_relu_s_cmp_d <= (rel_early_congr_cl = relu_congr_cl_q); +congr_cl_rel13_rel_upd_cmp_d <= (rel_early_congr_cl = relu_s_congr_cl_q); +congr_cl_rel13_p0_cmp <= congr_cl_rel13_ex6_cmp_q and p0_wren_cpy_q; +congr_cl_rel13_p1_cmp <= congr_cl_rel13_rel_upd_cmp_q and p1_wren_cpy_q; +congr_cl_rel13_ex3_m <= congr_cl_rel13_ex3_cmp_q and (ex3_lock_set_q or back_inval_stg3_q); +congr_cl_rel13_ex4_m <= congr_cl_rel13_ex4_cmp_q and (ex4_lock_set_q or back_inval_stg4_q); +congr_cl_rel13_ex5_m <= congr_cl_rel13_ex5_cmp_q and (ex5_lock_set_q or back_inval_stg5_q); +congr_cl_rel13_relu_m <= congr_cl_rel13_relu_cmp_q and rel_val_stgu_q; +congr_cl_rel13_relu_s_m <= congr_cl_rel13_relu_s_cmp_q and p1_upd_val; +congr_cl_rel13_wayA_byp(1) <= congr_cl_rel13_ex3_m and ex3_wayA_hit; +congr_cl_rel13_wayA_byp(2) <= congr_cl_rel13_relu_m and reload_wayA_upd_q; +congr_cl_rel13_wayA_byp(3) <= congr_cl_rel13_ex4_m and binv_wayA_upd_q; +congr_cl_rel13_wayA_byp(4) <= congr_cl_rel13_relu_s_m and reload_wayA_upd2_q; +congr_cl_rel13_wayA_byp(5) <= congr_cl_rel13_ex5_m and binv_wayA_upd2_q; +congr_cl_rel13_wayA_byp(6) <= congr_cl_rel13_p1_cmp and reload_wayA_upd3_q; +congr_cl_rel13_wayA_byp(7) <= congr_cl_rel13_p0_cmp and binv_wayA_upd3_q; +rel24_wayA_fxubyp_val_d <= congr_cl_rel13_wayA_byp(1) or congr_cl_rel13_wayA_byp(3) or + congr_cl_rel13_wayA_byp(5) or congr_cl_rel13_wayA_byp(7); +rel24_wayA_relbyp_val_d <= congr_cl_rel13_wayA_byp(2) or congr_cl_rel13_wayA_byp(4) or + congr_cl_rel13_wayA_byp(6); +rel24_wayA_byp_sel <= rel24_wayA_fxubyp_val_q & rel24_wayA_relbyp_val_q; +congr_cl_rel13_wayA_sel(2) <= congr_cl_rel13_wayA_byp(2); +congr_cl_rel13_wayA_sel(3) <= congr_cl_rel13_wayA_byp(3) and not congr_cl_rel13_wayA_byp(2); +congr_cl_rel13_wayA_sel(4) <= congr_cl_rel13_wayA_byp(4) and not or_reduce(congr_cl_rel13_wayA_byp(2 to 3)); +congr_cl_rel13_wayA_sel(5) <= congr_cl_rel13_wayA_byp(5) and not or_reduce(congr_cl_rel13_wayA_byp(2 to 4)); +congr_cl_rel13_wayA_sel(6) <= congr_cl_rel13_wayA_byp(6) and not or_reduce(congr_cl_rel13_wayA_byp(2 to 5)); +congr_cl_rel13_wayA_sel(7) <= congr_cl_rel13_wayA_byp(7) and not or_reduce(congr_cl_rel13_wayA_byp(2 to 6)); +rel_wayA_late_sel <= or_reduce(congr_cl_rel13_wayA_byp(2 to 7)); +rel_wayA_later_stg_pri <= gate(p1_arr_wayA_rd, not rel_wayA_late_sel) or + gate(reload_wayA, congr_cl_rel13_wayA_sel(2)) or + gate(flush_wayA_q, congr_cl_rel13_wayA_sel(3)) or + gate(reload_wayA_data_q, congr_cl_rel13_wayA_sel(4)) or + gate(flush_wayA_data_q, congr_cl_rel13_wayA_sel(5)) or + gate(reload_wayA_data2_q, congr_cl_rel13_wayA_sel(6)) or + gate(flush_wayA_data2_q, congr_cl_rel13_wayA_sel(7)); +rel_wayA_early_sel <= congr_cl_rel13_wayA_byp(1); +rel_wayA_early_stg_pri <= flush_wayA_d; +rel_wayA_stg_val <= (others=>(rel_wayA_early_sel)); +rel_wayA_stg_val_b <= (others=>(not(rel_wayA_early_sel))); +rel_wayA_val <= not rel_wayA_val_b_q; +rel_wayA_val_stg_d <= rel_wayA_val; +congr_cl_rel13_wayB_byp(1) <= congr_cl_rel13_ex3_m and ex3_wayB_hit; +congr_cl_rel13_wayB_byp(2) <= congr_cl_rel13_relu_m and reload_wayB_upd_q; +congr_cl_rel13_wayB_byp(3) <= congr_cl_rel13_ex4_m and binv_wayB_upd_q; +congr_cl_rel13_wayB_byp(4) <= congr_cl_rel13_relu_s_m and reload_wayB_upd2_q; +congr_cl_rel13_wayB_byp(5) <= congr_cl_rel13_ex5_m and binv_wayB_upd2_q; +congr_cl_rel13_wayB_byp(6) <= congr_cl_rel13_p1_cmp and reload_wayB_upd3_q; +congr_cl_rel13_wayB_byp(7) <= congr_cl_rel13_p0_cmp and binv_wayB_upd3_q; +rel24_wayB_fxubyp_val_d <= congr_cl_rel13_wayB_byp(1) or congr_cl_rel13_wayB_byp(3) or + congr_cl_rel13_wayB_byp(5) or congr_cl_rel13_wayB_byp(7); +rel24_wayB_relbyp_val_d <= congr_cl_rel13_wayB_byp(2) or congr_cl_rel13_wayB_byp(4) or + congr_cl_rel13_wayB_byp(6); +rel24_wayB_byp_sel <= rel24_wayB_fxubyp_val_q & rel24_wayB_relbyp_val_q; +congr_cl_rel13_wayB_sel(2) <= congr_cl_rel13_wayB_byp(2); +congr_cl_rel13_wayB_sel(3) <= congr_cl_rel13_wayB_byp(3) and not congr_cl_rel13_wayB_byp(2); +congr_cl_rel13_wayB_sel(4) <= congr_cl_rel13_wayB_byp(4) and not or_reduce(congr_cl_rel13_wayB_byp(2 to 3)); +congr_cl_rel13_wayB_sel(5) <= congr_cl_rel13_wayB_byp(5) and not or_reduce(congr_cl_rel13_wayB_byp(2 to 4)); +congr_cl_rel13_wayB_sel(6) <= congr_cl_rel13_wayB_byp(6) and not or_reduce(congr_cl_rel13_wayB_byp(2 to 5)); +congr_cl_rel13_wayB_sel(7) <= congr_cl_rel13_wayB_byp(7) and not or_reduce(congr_cl_rel13_wayB_byp(2 to 6)); +rel_wayB_late_sel <= or_reduce(congr_cl_rel13_wayB_byp(2 to 7)); +rel_wayB_later_stg_pri <= gate(p1_arr_wayB_rd, not rel_wayB_late_sel) or + gate(reload_wayB, congr_cl_rel13_wayB_sel(2)) or + gate(flush_wayB_q, congr_cl_rel13_wayB_sel(3)) or + gate(reload_wayB_data_q, congr_cl_rel13_wayB_sel(4)) or + gate(flush_wayB_data_q, congr_cl_rel13_wayB_sel(5)) or + gate(reload_wayB_data2_q, congr_cl_rel13_wayB_sel(6)) or + gate(flush_wayB_data2_q, congr_cl_rel13_wayB_sel(7)); +rel_wayB_early_sel <= congr_cl_rel13_wayB_byp(1); +rel_wayB_early_stg_pri <= flush_wayB_d; +rel_wayB_stg_val <= (others=>(rel_wayB_early_sel)); +rel_wayB_stg_val_b <= (others=>(not(rel_wayB_early_sel))); +rel_wayB_val <= not rel_wayB_val_b_q; +rel_wayB_val_stg_d <= rel_wayB_val; +congr_cl_rel13_wayC_byp(1) <= congr_cl_rel13_ex3_m and ex3_wayC_hit; +congr_cl_rel13_wayC_byp(2) <= congr_cl_rel13_relu_m and reload_wayC_upd_q; +congr_cl_rel13_wayC_byp(3) <= congr_cl_rel13_ex4_m and binv_wayC_upd_q; +congr_cl_rel13_wayC_byp(4) <= congr_cl_rel13_relu_s_m and reload_wayC_upd2_q; +congr_cl_rel13_wayC_byp(5) <= congr_cl_rel13_ex5_m and binv_wayC_upd2_q; +congr_cl_rel13_wayC_byp(6) <= congr_cl_rel13_p1_cmp and reload_wayC_upd3_q; +congr_cl_rel13_wayC_byp(7) <= congr_cl_rel13_p0_cmp and binv_wayC_upd3_q; +rel24_wayC_fxubyp_val_d <= congr_cl_rel13_wayC_byp(1) or congr_cl_rel13_wayC_byp(3) or + congr_cl_rel13_wayC_byp(5) or congr_cl_rel13_wayC_byp(7); +rel24_wayC_relbyp_val_d <= congr_cl_rel13_wayC_byp(2) or congr_cl_rel13_wayC_byp(4) or + congr_cl_rel13_wayC_byp(6); +rel24_wayC_byp_sel <= rel24_wayC_fxubyp_val_q & rel24_wayC_relbyp_val_q; +congr_cl_rel13_wayC_sel(2) <= congr_cl_rel13_wayC_byp(2); +congr_cl_rel13_wayC_sel(3) <= congr_cl_rel13_wayC_byp(3) and not congr_cl_rel13_wayC_byp(2); +congr_cl_rel13_wayC_sel(4) <= congr_cl_rel13_wayC_byp(4) and not or_reduce(congr_cl_rel13_wayC_byp(2 to 3)); +congr_cl_rel13_wayC_sel(5) <= congr_cl_rel13_wayC_byp(5) and not or_reduce(congr_cl_rel13_wayC_byp(2 to 4)); +congr_cl_rel13_wayC_sel(6) <= congr_cl_rel13_wayC_byp(6) and not or_reduce(congr_cl_rel13_wayC_byp(2 to 5)); +congr_cl_rel13_wayC_sel(7) <= congr_cl_rel13_wayC_byp(7) and not or_reduce(congr_cl_rel13_wayC_byp(2 to 6)); +rel_wayC_late_sel <= or_reduce(congr_cl_rel13_wayC_byp(2 to 7)); +rel_wayC_later_stg_pri <= gate(p1_arr_wayC_rd, not rel_wayC_late_sel) or + gate(reload_wayC, congr_cl_rel13_wayC_sel(2)) or + gate(flush_wayC_q, congr_cl_rel13_wayC_sel(3)) or + gate(reload_wayC_data_q, congr_cl_rel13_wayC_sel(4)) or + gate(flush_wayC_data_q, congr_cl_rel13_wayC_sel(5)) or + gate(reload_wayC_data2_q, congr_cl_rel13_wayC_sel(6)) or + gate(flush_wayC_data2_q, congr_cl_rel13_wayC_sel(7)); +rel_wayC_early_sel <= congr_cl_rel13_wayC_byp(1); +rel_wayC_early_stg_pri <= flush_wayC_d; +rel_wayC_stg_val <= (others=>(rel_wayC_early_sel)); +rel_wayC_stg_val_b <= (others=>(not(rel_wayC_early_sel))); +rel_wayC_val <= not rel_wayC_val_b_q; +rel_wayC_val_stg_d <= rel_wayC_val; +congr_cl_rel13_wayD_byp(1) <= congr_cl_rel13_ex3_m and ex3_wayD_hit; +congr_cl_rel13_wayD_byp(2) <= congr_cl_rel13_relu_m and reload_wayD_upd_q; +congr_cl_rel13_wayD_byp(3) <= congr_cl_rel13_ex4_m and binv_wayD_upd_q; +congr_cl_rel13_wayD_byp(4) <= congr_cl_rel13_relu_s_m and reload_wayD_upd2_q; +congr_cl_rel13_wayD_byp(5) <= congr_cl_rel13_ex5_m and binv_wayD_upd2_q; +congr_cl_rel13_wayD_byp(6) <= congr_cl_rel13_p1_cmp and reload_wayD_upd3_q; +congr_cl_rel13_wayD_byp(7) <= congr_cl_rel13_p0_cmp and binv_wayD_upd3_q; +rel24_wayD_fxubyp_val_d <= congr_cl_rel13_wayD_byp(1) or congr_cl_rel13_wayD_byp(3) or + congr_cl_rel13_wayD_byp(5) or congr_cl_rel13_wayD_byp(7); +rel24_wayD_relbyp_val_d <= congr_cl_rel13_wayD_byp(2) or congr_cl_rel13_wayD_byp(4) or + congr_cl_rel13_wayD_byp(6); +rel24_wayD_byp_sel <= rel24_wayD_fxubyp_val_q & rel24_wayD_relbyp_val_q; +congr_cl_rel13_wayD_sel(2) <= congr_cl_rel13_wayD_byp(2); +congr_cl_rel13_wayD_sel(3) <= congr_cl_rel13_wayD_byp(3) and not congr_cl_rel13_wayD_byp(2); +congr_cl_rel13_wayD_sel(4) <= congr_cl_rel13_wayD_byp(4) and not or_reduce(congr_cl_rel13_wayD_byp(2 to 3)); +congr_cl_rel13_wayD_sel(5) <= congr_cl_rel13_wayD_byp(5) and not or_reduce(congr_cl_rel13_wayD_byp(2 to 4)); +congr_cl_rel13_wayD_sel(6) <= congr_cl_rel13_wayD_byp(6) and not or_reduce(congr_cl_rel13_wayD_byp(2 to 5)); +congr_cl_rel13_wayD_sel(7) <= congr_cl_rel13_wayD_byp(7) and not or_reduce(congr_cl_rel13_wayD_byp(2 to 6)); +rel_wayD_late_sel <= or_reduce(congr_cl_rel13_wayD_byp(2 to 7)); +rel_wayD_later_stg_pri <= gate(p1_arr_wayD_rd, not rel_wayD_late_sel) or + gate(reload_wayD, congr_cl_rel13_wayD_sel(2)) or + gate(flush_wayD_q, congr_cl_rel13_wayD_sel(3)) or + gate(reload_wayD_data_q, congr_cl_rel13_wayD_sel(4)) or + gate(flush_wayD_data_q, congr_cl_rel13_wayD_sel(5)) or + gate(reload_wayD_data2_q, congr_cl_rel13_wayD_sel(6)) or + gate(flush_wayD_data2_q, congr_cl_rel13_wayD_sel(7)); +rel_wayD_early_sel <= congr_cl_rel13_wayD_byp(1); +rel_wayD_early_stg_pri <= flush_wayD_d; +rel_wayD_stg_val <= (others=>(rel_wayD_early_sel)); +rel_wayD_stg_val_b <= (others=>(not(rel_wayD_early_sel))); +rel_wayD_val <= not rel_wayD_val_b_q; +rel_wayD_val_stg_d <= rel_wayD_val; +congr_cl_rel13_wayE_byp(1) <= congr_cl_rel13_ex3_m and ex3_wayE_hit; +congr_cl_rel13_wayE_byp(2) <= congr_cl_rel13_relu_m and reload_wayE_upd_q; +congr_cl_rel13_wayE_byp(3) <= congr_cl_rel13_ex4_m and binv_wayE_upd_q; +congr_cl_rel13_wayE_byp(4) <= congr_cl_rel13_relu_s_m and reload_wayE_upd2_q; +congr_cl_rel13_wayE_byp(5) <= congr_cl_rel13_ex5_m and binv_wayE_upd2_q; +congr_cl_rel13_wayE_byp(6) <= congr_cl_rel13_p1_cmp and reload_wayE_upd3_q; +congr_cl_rel13_wayE_byp(7) <= congr_cl_rel13_p0_cmp and binv_wayE_upd3_q; +rel24_wayE_fxubyp_val_d <= congr_cl_rel13_wayE_byp(1) or congr_cl_rel13_wayE_byp(3) or + congr_cl_rel13_wayE_byp(5) or congr_cl_rel13_wayE_byp(7); +rel24_wayE_relbyp_val_d <= congr_cl_rel13_wayE_byp(2) or congr_cl_rel13_wayE_byp(4) or + congr_cl_rel13_wayE_byp(6); +rel24_wayE_byp_sel <= rel24_wayE_fxubyp_val_q & rel24_wayE_relbyp_val_q; +congr_cl_rel13_wayE_sel(2) <= congr_cl_rel13_wayE_byp(2); +congr_cl_rel13_wayE_sel(3) <= congr_cl_rel13_wayE_byp(3) and not congr_cl_rel13_wayE_byp(2); +congr_cl_rel13_wayE_sel(4) <= congr_cl_rel13_wayE_byp(4) and not or_reduce(congr_cl_rel13_wayE_byp(2 to 3)); +congr_cl_rel13_wayE_sel(5) <= congr_cl_rel13_wayE_byp(5) and not or_reduce(congr_cl_rel13_wayE_byp(2 to 4)); +congr_cl_rel13_wayE_sel(6) <= congr_cl_rel13_wayE_byp(6) and not or_reduce(congr_cl_rel13_wayE_byp(2 to 5)); +congr_cl_rel13_wayE_sel(7) <= congr_cl_rel13_wayE_byp(7) and not or_reduce(congr_cl_rel13_wayE_byp(2 to 6)); +rel_wayE_late_sel <= or_reduce(congr_cl_rel13_wayE_byp(2 to 7)); +rel_wayE_later_stg_pri <= gate(p1_arr_wayE_rd, not rel_wayE_late_sel) or + gate(reload_wayE, congr_cl_rel13_wayE_sel(2)) or + gate(flush_wayE_q, congr_cl_rel13_wayE_sel(3)) or + gate(reload_wayE_data_q, congr_cl_rel13_wayE_sel(4)) or + gate(flush_wayE_data_q, congr_cl_rel13_wayE_sel(5)) or + gate(reload_wayE_data2_q, congr_cl_rel13_wayE_sel(6)) or + gate(flush_wayE_data2_q, congr_cl_rel13_wayE_sel(7)); +rel_wayE_early_sel <= congr_cl_rel13_wayE_byp(1); +rel_wayE_early_stg_pri <= flush_wayE_d; +rel_wayE_stg_val <= (others=>(rel_wayE_early_sel)); +rel_wayE_stg_val_b <= (others=>(not(rel_wayE_early_sel))); +rel_wayE_val <= not rel_wayE_val_b_q; +rel_wayE_val_stg_d <= rel_wayE_val; +congr_cl_rel13_wayF_byp(1) <= congr_cl_rel13_ex3_m and ex3_wayF_hit; +congr_cl_rel13_wayF_byp(2) <= congr_cl_rel13_relu_m and reload_wayF_upd_q; +congr_cl_rel13_wayF_byp(3) <= congr_cl_rel13_ex4_m and binv_wayF_upd_q; +congr_cl_rel13_wayF_byp(4) <= congr_cl_rel13_relu_s_m and reload_wayF_upd2_q; +congr_cl_rel13_wayF_byp(5) <= congr_cl_rel13_ex5_m and binv_wayF_upd2_q; +congr_cl_rel13_wayF_byp(6) <= congr_cl_rel13_p1_cmp and reload_wayF_upd3_q; +congr_cl_rel13_wayF_byp(7) <= congr_cl_rel13_p0_cmp and binv_wayF_upd3_q; +rel24_wayF_fxubyp_val_d <= congr_cl_rel13_wayF_byp(1) or congr_cl_rel13_wayF_byp(3) or + congr_cl_rel13_wayF_byp(5) or congr_cl_rel13_wayF_byp(7); +rel24_wayF_relbyp_val_d <= congr_cl_rel13_wayF_byp(2) or congr_cl_rel13_wayF_byp(4) or + congr_cl_rel13_wayF_byp(6); +rel24_wayF_byp_sel <= rel24_wayF_fxubyp_val_q & rel24_wayF_relbyp_val_q; +congr_cl_rel13_wayF_sel(2) <= congr_cl_rel13_wayF_byp(2); +congr_cl_rel13_wayF_sel(3) <= congr_cl_rel13_wayF_byp(3) and not congr_cl_rel13_wayF_byp(2); +congr_cl_rel13_wayF_sel(4) <= congr_cl_rel13_wayF_byp(4) and not or_reduce(congr_cl_rel13_wayF_byp(2 to 3)); +congr_cl_rel13_wayF_sel(5) <= congr_cl_rel13_wayF_byp(5) and not or_reduce(congr_cl_rel13_wayF_byp(2 to 4)); +congr_cl_rel13_wayF_sel(6) <= congr_cl_rel13_wayF_byp(6) and not or_reduce(congr_cl_rel13_wayF_byp(2 to 5)); +congr_cl_rel13_wayF_sel(7) <= congr_cl_rel13_wayF_byp(7) and not or_reduce(congr_cl_rel13_wayF_byp(2 to 6)); +rel_wayF_late_sel <= or_reduce(congr_cl_rel13_wayF_byp(2 to 7)); +rel_wayF_later_stg_pri <= gate(p1_arr_wayF_rd, not rel_wayF_late_sel) or + gate(reload_wayF, congr_cl_rel13_wayF_sel(2)) or + gate(flush_wayF_q, congr_cl_rel13_wayF_sel(3)) or + gate(reload_wayF_data_q, congr_cl_rel13_wayF_sel(4)) or + gate(flush_wayF_data_q, congr_cl_rel13_wayF_sel(5)) or + gate(reload_wayF_data2_q, congr_cl_rel13_wayF_sel(6)) or + gate(flush_wayF_data2_q, congr_cl_rel13_wayF_sel(7)); +rel_wayF_early_sel <= congr_cl_rel13_wayF_byp(1); +rel_wayF_early_stg_pri <= flush_wayF_d; +rel_wayF_stg_val <= (others=>(rel_wayF_early_sel)); +rel_wayF_stg_val_b <= (others=>(not(rel_wayF_early_sel))); +rel_wayF_val <= not rel_wayF_val_b_q; +rel_wayF_val_stg_d <= rel_wayF_val; +congr_cl_rel13_wayG_byp(1) <= congr_cl_rel13_ex3_m and ex3_wayG_hit; +congr_cl_rel13_wayG_byp(2) <= congr_cl_rel13_relu_m and reload_wayG_upd_q; +congr_cl_rel13_wayG_byp(3) <= congr_cl_rel13_ex4_m and binv_wayG_upd_q; +congr_cl_rel13_wayG_byp(4) <= congr_cl_rel13_relu_s_m and reload_wayG_upd2_q; +congr_cl_rel13_wayG_byp(5) <= congr_cl_rel13_ex5_m and binv_wayG_upd2_q; +congr_cl_rel13_wayG_byp(6) <= congr_cl_rel13_p1_cmp and reload_wayG_upd3_q; +congr_cl_rel13_wayG_byp(7) <= congr_cl_rel13_p0_cmp and binv_wayG_upd3_q; +rel24_wayG_fxubyp_val_d <= congr_cl_rel13_wayG_byp(1) or congr_cl_rel13_wayG_byp(3) or + congr_cl_rel13_wayG_byp(5) or congr_cl_rel13_wayG_byp(7); +rel24_wayG_relbyp_val_d <= congr_cl_rel13_wayG_byp(2) or congr_cl_rel13_wayG_byp(4) or + congr_cl_rel13_wayG_byp(6); +rel24_wayG_byp_sel <= rel24_wayG_fxubyp_val_q & rel24_wayG_relbyp_val_q; +congr_cl_rel13_wayG_sel(2) <= congr_cl_rel13_wayG_byp(2); +congr_cl_rel13_wayG_sel(3) <= congr_cl_rel13_wayG_byp(3) and not congr_cl_rel13_wayG_byp(2); +congr_cl_rel13_wayG_sel(4) <= congr_cl_rel13_wayG_byp(4) and not or_reduce(congr_cl_rel13_wayG_byp(2 to 3)); +congr_cl_rel13_wayG_sel(5) <= congr_cl_rel13_wayG_byp(5) and not or_reduce(congr_cl_rel13_wayG_byp(2 to 4)); +congr_cl_rel13_wayG_sel(6) <= congr_cl_rel13_wayG_byp(6) and not or_reduce(congr_cl_rel13_wayG_byp(2 to 5)); +congr_cl_rel13_wayG_sel(7) <= congr_cl_rel13_wayG_byp(7) and not or_reduce(congr_cl_rel13_wayG_byp(2 to 6)); +rel_wayG_late_sel <= or_reduce(congr_cl_rel13_wayG_byp(2 to 7)); +rel_wayG_later_stg_pri <= gate(p1_arr_wayG_rd, not rel_wayG_late_sel) or + gate(reload_wayG, congr_cl_rel13_wayG_sel(2)) or + gate(flush_wayG_q, congr_cl_rel13_wayG_sel(3)) or + gate(reload_wayG_data_q, congr_cl_rel13_wayG_sel(4)) or + gate(flush_wayG_data_q, congr_cl_rel13_wayG_sel(5)) or + gate(reload_wayG_data2_q, congr_cl_rel13_wayG_sel(6)) or + gate(flush_wayG_data2_q, congr_cl_rel13_wayG_sel(7)); +rel_wayG_early_sel <= congr_cl_rel13_wayG_byp(1); +rel_wayG_early_stg_pri <= flush_wayG_d; +rel_wayG_stg_val <= (others=>(rel_wayG_early_sel)); +rel_wayG_stg_val_b <= (others=>(not(rel_wayG_early_sel))); +rel_wayG_val <= not rel_wayG_val_b_q; +rel_wayG_val_stg_d <= rel_wayG_val; +congr_cl_rel13_wayH_byp(1) <= congr_cl_rel13_ex3_m and ex3_wayH_hit; +congr_cl_rel13_wayH_byp(2) <= congr_cl_rel13_relu_m and reload_wayH_upd_q; +congr_cl_rel13_wayH_byp(3) <= congr_cl_rel13_ex4_m and binv_wayH_upd_q; +congr_cl_rel13_wayH_byp(4) <= congr_cl_rel13_relu_s_m and reload_wayH_upd2_q; +congr_cl_rel13_wayH_byp(5) <= congr_cl_rel13_ex5_m and binv_wayH_upd2_q; +congr_cl_rel13_wayH_byp(6) <= congr_cl_rel13_p1_cmp and reload_wayH_upd3_q; +congr_cl_rel13_wayH_byp(7) <= congr_cl_rel13_p0_cmp and binv_wayH_upd3_q; +rel24_wayH_fxubyp_val_d <= congr_cl_rel13_wayH_byp(1) or congr_cl_rel13_wayH_byp(3) or + congr_cl_rel13_wayH_byp(5) or congr_cl_rel13_wayH_byp(7); +rel24_wayH_relbyp_val_d <= congr_cl_rel13_wayH_byp(2) or congr_cl_rel13_wayH_byp(4) or + congr_cl_rel13_wayH_byp(6); +rel24_wayH_byp_sel <= rel24_wayH_fxubyp_val_q & rel24_wayH_relbyp_val_q; +congr_cl_rel13_wayH_sel(2) <= congr_cl_rel13_wayH_byp(2); +congr_cl_rel13_wayH_sel(3) <= congr_cl_rel13_wayH_byp(3) and not congr_cl_rel13_wayH_byp(2); +congr_cl_rel13_wayH_sel(4) <= congr_cl_rel13_wayH_byp(4) and not or_reduce(congr_cl_rel13_wayH_byp(2 to 3)); +congr_cl_rel13_wayH_sel(5) <= congr_cl_rel13_wayH_byp(5) and not or_reduce(congr_cl_rel13_wayH_byp(2 to 4)); +congr_cl_rel13_wayH_sel(6) <= congr_cl_rel13_wayH_byp(6) and not or_reduce(congr_cl_rel13_wayH_byp(2 to 5)); +congr_cl_rel13_wayH_sel(7) <= congr_cl_rel13_wayH_byp(7) and not or_reduce(congr_cl_rel13_wayH_byp(2 to 6)); +rel_wayH_late_sel <= or_reduce(congr_cl_rel13_wayH_byp(2 to 7)); +rel_wayH_later_stg_pri <= gate(p1_arr_wayH_rd, not rel_wayH_late_sel) or + gate(reload_wayH, congr_cl_rel13_wayH_sel(2)) or + gate(flush_wayH_q, congr_cl_rel13_wayH_sel(3)) or + gate(reload_wayH_data_q, congr_cl_rel13_wayH_sel(4)) or + gate(flush_wayH_data_q, congr_cl_rel13_wayH_sel(5)) or + gate(reload_wayH_data2_q, congr_cl_rel13_wayH_sel(6)) or + gate(flush_wayH_data2_q, congr_cl_rel13_wayH_sel(7)); +rel_wayH_early_sel <= congr_cl_rel13_wayH_byp(1); +rel_wayH_early_stg_pri <= flush_wayH_d; +rel_wayH_stg_val <= (others=>(rel_wayH_early_sel)); +rel_wayH_stg_val_b <= (others=>(not(rel_wayH_early_sel))); +rel_wayH_val <= not rel_wayH_val_b_q; +rel_wayH_val_stg_d <= rel_wayH_val; +rel_par_wA_clr <= rel_wayA_clr or dcpar_err_way_inval_q(0); +reload_wayA_d(0) <= (not rel_par_wA_clr and rel_wayA_val(0)) or rel_wayA_set; +reload_wayA_d(1) <= (not rel_par_wA_clr and rel_wayA_val(1)) or (rel_lock_set_q and rel_wayA_set); +dcpar_err_lock_lost(0) <= rel_wayA_val(1) and dcpar_err_way_inval_q(0); +reload_wayA_d(2) <= ((not rel_par_wA_clr and rel_wayA_val(2))) or (rel_watch_set_q and rel_wayA_set and rel_thrd_id_q(0)); +reload_wayA_d(3) <= ((not rel_par_wA_clr and rel_wayA_val(3))) or (rel_watch_set_q and rel_wayA_set and rel_thrd_id_q(1)); +reload_wayA_d(4) <= ((not rel_par_wA_clr and rel_wayA_val(4))) or (rel_watch_set_q and rel_wayA_set and rel_thrd_id_q(2)); +reload_wayA_d(5) <= ((not rel_par_wA_clr and rel_wayA_val(5))) or (rel_watch_set_q and rel_wayA_set and rel_thrd_id_q(3)); +reload_wayA_upd_d <= rel_par_wA_clr or rel_wayA_set; +reload_wayA_clr <= rel_par_wA_clr; +rel_par_wB_clr <= rel_wayB_clr or dcpar_err_way_inval_q(1); +reload_wayB_d(0) <= (not rel_par_wB_clr and rel_wayB_val(0)) or rel_wayB_set; +reload_wayB_d(1) <= (not rel_par_wB_clr and rel_wayB_val(1)) or (rel_lock_set_q and rel_wayB_set); +dcpar_err_lock_lost(1) <= rel_wayB_val(1) and dcpar_err_way_inval_q(1); +reload_wayB_d(2) <= ((not rel_par_wB_clr and rel_wayB_val(2))) or (rel_watch_set_q and rel_wayB_set and rel_thrd_id_q(0)); +reload_wayB_d(3) <= ((not rel_par_wB_clr and rel_wayB_val(3))) or (rel_watch_set_q and rel_wayB_set and rel_thrd_id_q(1)); +reload_wayB_d(4) <= ((not rel_par_wB_clr and rel_wayB_val(4))) or (rel_watch_set_q and rel_wayB_set and rel_thrd_id_q(2)); +reload_wayB_d(5) <= ((not rel_par_wB_clr and rel_wayB_val(5))) or (rel_watch_set_q and rel_wayB_set and rel_thrd_id_q(3)); +reload_wayB_upd_d <= rel_par_wB_clr or rel_wayB_set; +reload_wayB_clr <= rel_par_wB_clr; +rel_par_wC_clr <= rel_wayC_clr or dcpar_err_way_inval_q(2); +reload_wayC_d(0) <= (not rel_par_wC_clr and rel_wayC_val(0)) or rel_wayC_set; +reload_wayC_d(1) <= (not rel_par_wC_clr and rel_wayC_val(1)) or (rel_lock_set_q and rel_wayC_set); +dcpar_err_lock_lost(2) <= rel_wayC_val(1) and dcpar_err_way_inval_q(2); +reload_wayC_d(2) <= ((not rel_par_wC_clr and rel_wayC_val(2))) or (rel_watch_set_q and rel_wayC_set and rel_thrd_id_q(0)); +reload_wayC_d(3) <= ((not rel_par_wC_clr and rel_wayC_val(3))) or (rel_watch_set_q and rel_wayC_set and rel_thrd_id_q(1)); +reload_wayC_d(4) <= ((not rel_par_wC_clr and rel_wayC_val(4))) or (rel_watch_set_q and rel_wayC_set and rel_thrd_id_q(2)); +reload_wayC_d(5) <= ((not rel_par_wC_clr and rel_wayC_val(5))) or (rel_watch_set_q and rel_wayC_set and rel_thrd_id_q(3)); +reload_wayC_upd_d <= rel_par_wC_clr or rel_wayC_set; +reload_wayC_clr <= rel_par_wC_clr; +rel_par_wD_clr <= rel_wayD_clr or dcpar_err_way_inval_q(3); +reload_wayD_d(0) <= (not rel_par_wD_clr and rel_wayD_val(0)) or rel_wayD_set; +reload_wayD_d(1) <= (not rel_par_wD_clr and rel_wayD_val(1)) or (rel_lock_set_q and rel_wayD_set); +dcpar_err_lock_lost(3) <= rel_wayD_val(1) and dcpar_err_way_inval_q(3); +reload_wayD_d(2) <= ((not rel_par_wD_clr and rel_wayD_val(2))) or (rel_watch_set_q and rel_wayD_set and rel_thrd_id_q(0)); +reload_wayD_d(3) <= ((not rel_par_wD_clr and rel_wayD_val(3))) or (rel_watch_set_q and rel_wayD_set and rel_thrd_id_q(1)); +reload_wayD_d(4) <= ((not rel_par_wD_clr and rel_wayD_val(4))) or (rel_watch_set_q and rel_wayD_set and rel_thrd_id_q(2)); +reload_wayD_d(5) <= ((not rel_par_wD_clr and rel_wayD_val(5))) or (rel_watch_set_q and rel_wayD_set and rel_thrd_id_q(3)); +reload_wayD_upd_d <= rel_par_wD_clr or rel_wayD_set; +reload_wayD_clr <= rel_par_wD_clr; +rel_par_wE_clr <= rel_wayE_clr or dcpar_err_way_inval_q(4); +reload_wayE_d(0) <= (not rel_par_wE_clr and rel_wayE_val(0)) or rel_wayE_set; +reload_wayE_d(1) <= (not rel_par_wE_clr and rel_wayE_val(1)) or (rel_lock_set_q and rel_wayE_set); +dcpar_err_lock_lost(4) <= rel_wayE_val(1) and dcpar_err_way_inval_q(4); +reload_wayE_d(2) <= ((not rel_par_wE_clr and rel_wayE_val(2))) or (rel_watch_set_q and rel_wayE_set and rel_thrd_id_q(0)); +reload_wayE_d(3) <= ((not rel_par_wE_clr and rel_wayE_val(3))) or (rel_watch_set_q and rel_wayE_set and rel_thrd_id_q(1)); +reload_wayE_d(4) <= ((not rel_par_wE_clr and rel_wayE_val(4))) or (rel_watch_set_q and rel_wayE_set and rel_thrd_id_q(2)); +reload_wayE_d(5) <= ((not rel_par_wE_clr and rel_wayE_val(5))) or (rel_watch_set_q and rel_wayE_set and rel_thrd_id_q(3)); +reload_wayE_upd_d <= rel_par_wE_clr or rel_wayE_set; +reload_wayE_clr <= rel_par_wE_clr; +rel_par_wF_clr <= rel_wayF_clr or dcpar_err_way_inval_q(5); +reload_wayF_d(0) <= (not rel_par_wF_clr and rel_wayF_val(0)) or rel_wayF_set; +reload_wayF_d(1) <= (not rel_par_wF_clr and rel_wayF_val(1)) or (rel_lock_set_q and rel_wayF_set); +dcpar_err_lock_lost(5) <= rel_wayF_val(1) and dcpar_err_way_inval_q(5); +reload_wayF_d(2) <= ((not rel_par_wF_clr and rel_wayF_val(2))) or (rel_watch_set_q and rel_wayF_set and rel_thrd_id_q(0)); +reload_wayF_d(3) <= ((not rel_par_wF_clr and rel_wayF_val(3))) or (rel_watch_set_q and rel_wayF_set and rel_thrd_id_q(1)); +reload_wayF_d(4) <= ((not rel_par_wF_clr and rel_wayF_val(4))) or (rel_watch_set_q and rel_wayF_set and rel_thrd_id_q(2)); +reload_wayF_d(5) <= ((not rel_par_wF_clr and rel_wayF_val(5))) or (rel_watch_set_q and rel_wayF_set and rel_thrd_id_q(3)); +reload_wayF_upd_d <= rel_par_wF_clr or rel_wayF_set; +reload_wayF_clr <= rel_par_wF_clr; +rel_par_wG_clr <= rel_wayG_clr or dcpar_err_way_inval_q(6); +reload_wayG_d(0) <= (not rel_par_wG_clr and rel_wayG_val(0)) or rel_wayG_set; +reload_wayG_d(1) <= (not rel_par_wG_clr and rel_wayG_val(1)) or (rel_lock_set_q and rel_wayG_set); +dcpar_err_lock_lost(6) <= rel_wayG_val(1) and dcpar_err_way_inval_q(6); +reload_wayG_d(2) <= ((not rel_par_wG_clr and rel_wayG_val(2))) or (rel_watch_set_q and rel_wayG_set and rel_thrd_id_q(0)); +reload_wayG_d(3) <= ((not rel_par_wG_clr and rel_wayG_val(3))) or (rel_watch_set_q and rel_wayG_set and rel_thrd_id_q(1)); +reload_wayG_d(4) <= ((not rel_par_wG_clr and rel_wayG_val(4))) or (rel_watch_set_q and rel_wayG_set and rel_thrd_id_q(2)); +reload_wayG_d(5) <= ((not rel_par_wG_clr and rel_wayG_val(5))) or (rel_watch_set_q and rel_wayG_set and rel_thrd_id_q(3)); +reload_wayG_upd_d <= rel_par_wG_clr or rel_wayG_set; +reload_wayG_clr <= rel_par_wG_clr; +rel_par_wH_clr <= rel_wayH_clr or dcpar_err_way_inval_q(7); +reload_wayH_d(0) <= (not rel_par_wH_clr and rel_wayH_val(0)) or rel_wayH_set; +reload_wayH_d(1) <= (not rel_par_wH_clr and rel_wayH_val(1)) or (rel_lock_set_q and rel_wayH_set); +dcpar_err_lock_lost(7) <= rel_wayH_val(1) and dcpar_err_way_inval_q(7); +reload_wayH_d(2) <= ((not rel_par_wH_clr and rel_wayH_val(2))) or (rel_watch_set_q and rel_wayH_set and rel_thrd_id_q(0)); +reload_wayH_d(3) <= ((not rel_par_wH_clr and rel_wayH_val(3))) or (rel_watch_set_q and rel_wayH_set and rel_thrd_id_q(1)); +reload_wayH_d(4) <= ((not rel_par_wH_clr and rel_wayH_val(4))) or (rel_watch_set_q and rel_wayH_set and rel_thrd_id_q(2)); +reload_wayH_d(5) <= ((not rel_par_wH_clr and rel_wayH_val(5))) or (rel_watch_set_q and rel_wayH_set and rel_thrd_id_q(3)); +reload_wayH_upd_d <= rel_par_wH_clr or rel_wayH_set; +reload_wayH_clr <= rel_par_wH_clr; +reload_way_clr_d <= reload_wayA_clr & reload_wayB_clr & reload_wayC_clr & reload_wayD_clr & + reload_wayE_clr & reload_wayF_clr & reload_wayG_clr & reload_wayH_clr; +rel4_l1dump_watch <= rel4_l1dump_val_q and rel_watch_set_q and not rel4_ecc_err; +lost_watch_l1dump <= gate(rel_thrd_id_q, rel4_l1dump_watch); +lost_watch_evict_ovl_d <= (gate(rel_thrd_id_q, (rel_watch_set_q and rel_val_stg4 and not + (rel_wayA_set or rel_wayB_set or rel_wayC_set or rel_wayD_set or + rel_wayE_set or rel_wayF_set or rel_wayG_set or rel_wayH_set)))) or + lost_watch_l1dump; +rel_lost_watch_wayA_evict <= gate(rel_wayA_val_stg_q(2 to 5), reload_way_clr_q(0)); +rel_lost_watch_wayB_evict <= gate(rel_wayB_val_stg_q(2 to 5), reload_way_clr_q(1)); +rel_lost_watch_wayC_evict <= gate(rel_wayC_val_stg_q(2 to 5), reload_way_clr_q(2)); +rel_lost_watch_wayD_evict <= gate(rel_wayD_val_stg_q(2 to 5), reload_way_clr_q(3)); +rel_lost_watch_wayE_evict <= gate(rel_wayE_val_stg_q(2 to 5), reload_way_clr_q(4)); +rel_lost_watch_wayF_evict <= gate(rel_wayF_val_stg_q(2 to 5), reload_way_clr_q(5)); +rel_lost_watch_wayG_evict <= gate(rel_wayG_val_stg_q(2 to 5), reload_way_clr_q(6)); +rel_lost_watch_wayH_evict <= gate(rel_wayH_val_stg_q(2 to 5), reload_way_clr_q(7)); +rel_lost_watch_binv_d <= rel_watch_lost; +rel_lost_watch_evict_np <= rel_lost_watch_wayA_evict or rel_lost_watch_wayB_evict or rel_lost_watch_wayC_evict or rel_lost_watch_wayD_evict or + rel_lost_watch_wayE_evict or rel_lost_watch_wayF_evict or rel_lost_watch_wayG_evict or rel_lost_watch_wayH_evict; +dcperr_lock_lost_d <= or_reduce(dcpar_err_lock_lost); +rel24_congr_cl_ex4_cmp_d <= congr_cl_rel13_ex3_cmp_q; +rel24_congr_cl_ex5_cmp_d <= congr_cl_rel13_ex4_cmp_q; +rel24_congr_cl_ex6_cmp_d <= congr_cl_rel13_ex5_cmp_q; +relu_congr_cl_ex5_cmp_d <= rel24_congr_cl_ex4_cmp_q; +relu_congr_cl_ex6_cmp_d <= rel24_congr_cl_ex5_cmp_q; +relu_congr_cl_ex7_cmp_d <= rel24_congr_cl_ex6_cmp_q; +relu_dir_data <= gate(reload_wayA_q(2 to 5), reload_way_clr_q(0)) or gate(reload_wayB_q(2 to 5), reload_way_clr_q(1)) or + gate(reload_wayC_q(2 to 5), reload_way_clr_q(2)) or gate(reload_wayD_q(2 to 5), reload_way_clr_q(3)) or + gate(reload_wayE_q(2 to 5), reload_way_clr_q(4)) or gate(reload_wayF_q(2 to 5), reload_way_clr_q(5)) or + gate(reload_wayG_q(2 to 5), reload_way_clr_q(6)) or gate(reload_wayH_q(2 to 5), reload_way_clr_q(7)); +rel_ex5_watchSet_coll <= rel_val_clr_q and relu_congr_cl_ex5_cmp_q and or_reduce(reload_way_clr_q and binv5_ex5_way_upd) and p0_wren_d; +rel_ex6_watchSet_coll <= rel_val_clr_q and relu_congr_cl_ex6_cmp_q and or_reduce(reload_way_clr_q and binv6_ex6_way_upd) and p0_wren_q; +rel_ex7_watchSet_coll <= rel_val_clr_q and relu_congr_cl_ex7_cmp_q and or_reduce(reload_way_clr_q and binv7_ex7_way_upd_q) and p0_wren_stg_q; +rel_coll_val <= rel_ex5_watchSet_coll or rel_ex6_watchSet_coll or rel_ex7_watchSet_coll; +rel_pri_byp_sel(0) <= rel_ex5_watchSet_coll; +rel_pri_byp_sel(1) <= rel_ex6_watchSet_coll and not rel_ex5_watchSet_coll; +rel_pri_byp_sel(2) <= rel_ex7_watchSet_coll and not (rel_ex6_watchSet_coll or rel_ex5_watchSet_coll); +rel_byp_dir_data <= gate(binv5_ex5_dir_data_q(2 to 5), rel_pri_byp_sel(0)) or + gate(binv6_ex6_dir_data_q(2 to 5), rel_pri_byp_sel(1)) or + gate(binv7_ex7_dir_data_q(2 to 5), rel_pri_byp_sel(2)); +rel_watchSet_coll_tid <= (rel_byp_dir_data and not relu_dir_data) or gate(rel_lost_watch_evict_np, (rel_val_clr_q and not rel_coll_val)); +rel_lost_watch_evict <= lost_watch_evict_ovl_q or rel_watchSet_coll_tid; +rel_lost_watch_upd_d <= rel_lost_watch_binv_q or rel_lost_watch_evict; +perf_binv_hit <= back_inval_stg4_q and or_reduce(ex4_way_hit_q); +ex5_watch_chk_cplt <= ex5_watch_chk_q and not ex5_stg_flush; +ex5_watch_chk_succ <= ex5_watch_chk_q and not (ex5_cr_watch_q or ex5_stg_flush); +ex5_watch_dup_set <= ex5_watch_set_q and ex5_cr_watch_q and not ex5_stg_flush; +lost_watch_inter_thrd_d <= gate((ex5_watchlost_set_q and not (ex5_thrd_id_q or ex5_watch_clr_all_q)), ex5_xuop_val); +lost_watch_evict_val_d <= lost_watch_evict_ovl_q or rel_watchSet_coll_tid; +lost_watch_binv <= binv5_inval_watch_val_q or rel_lost_watch_binv_q; +perf_lsu_evnts_d <= back_inval_stg4_q & perf_binv_hit & ex5_watch_chk_cplt & ex5_watch_chk_succ & ex5_watch_dup_set; +dcpar_err_push <= not ex9_ld_par_err_q; +dcpar_err_rec_cmpl <= (dcpar_err_cntr_q = "10") and dcpar_err_nxt_rec; +dcpar_err_nxt_rec <= ex9_ld_par_err_q and not rel_in_progress; +dcpar_err_push_queue <= dcpar_err_push or dcpar_err_nxt_rec; +dcpar_err_ind_sel <= dcpar_err_push & dcpar_err_rec_cmpl; +dcpar_err_ind_sel_d <= dcpar_err_ind_sel; +dcpar_err_push_queue_d <= dcpar_err_push_queue; +with dcpar_err_ind_sel select + ex7_ld_par_err_d <= ex6_ld_par_err when "10", + ex7_ld_par_err_q when "00", + '0' when others; +with dcpar_err_ind_sel select + ex8_ld_par_err_d <= ex7_ld_par_err_q when "10", + ex8_ld_par_err_q when "00", + '0' when others; +with dcpar_err_ind_sel select + ex9_ld_par_err_d <= ex8_ld_par_err_q when "10", + ex9_ld_par_err_q when "00", + '0' when others; +with dcpar_err_push_queue select + ex7_ld_valid_d <= ex6_ld_valid_q when '1', + ex7_ld_valid_q when others; +with dcpar_err_push_queue select + ex8_ld_valid_d <= ex7_ld_valid_q when '1', + ex8_ld_valid_q when others; +with dcpar_err_push_queue select + ex9_ld_valid_d <= ex8_ld_valid_q when '1', + ex9_ld_valid_q when others; +with dcpar_err_push_queue select + ex7_congr_cl_d <= ex6_congr_cl_q when '1', + ex7_congr_cl_q when others; +with dcpar_err_push_queue select + ex8_congr_cl_d <= ex7_congr_cl_q when '1', + ex8_congr_cl_q when others; +with dcpar_err_push_queue select + ex9_congr_cl_d <= ex8_congr_cl_q when '1', + ex9_congr_cl_q when others; +with dcpar_err_push_queue select + ex7_way_hit_d <= ex6_way_hit_q when '1', + ex7_way_hit_q when others; +with dcpar_err_push_queue select + ex8_way_hit_d <= ex7_way_hit_q when '1', + ex8_way_hit_q when others; +with dcpar_err_push_queue select + ex9_way_hit_d <= ex8_way_hit_q when '1', + ex9_way_hit_q when others; +dcpar_err_incr_val <= dcpar_err_nxt_rec and not (dcpar_err_cntr_q = "10"); +dcpar_err_cntr_sel <= dcpar_err_push & dcpar_err_incr_val; +dcpar_err_nxt_cntr <= std_ulogic_vector(unsigned(dcpar_err_cntr_q) + "01"); +with dcpar_err_cntr_sel select + dcpar_err_cntr_d <= dcpar_err_nxt_cntr when "01", + dcpar_err_cntr_q when "00", + "00" when others; +dcpar_err_stg1_d <= dcpar_err_nxt_rec; +dcpar_err_stg2_d <= dcpar_err_stg1_q; +dcpar_err_congr_cl <= ex9_congr_cl_q; +dcpar_err_way_d <= gate(ex9_way_hit_q, (ex9_ld_valid_q and dcpar_err_nxt_rec)); +dcpar_err_way_inval_d <= dcpar_err_way_q; +dcpar_err_flush <= ex9_ld_par_err_q; +dcpar_err_stg1_act_d <= ex9_ld_par_err_q; +dcpar_err_stg2_act_d <= dcpar_err_stg1_act_q; +dcpar_err_rec_inprog <= ex7_ld_par_err_q or ex8_ld_par_err_q or ex9_ld_par_err_q; +p0_wren_d <= back_inval_stg5_q or ex5_xuop_val or ex5_dir_err_val_q; +p0_wren_cpy_d <= back_inval_stg5_q or ex5_xuop_val or ex5_dir_err_val_q; +p0_wren_stg_d <= p0_wren_q; +p1_wren_d <= rel_port_wren_q; +p1_wren_cpy_d <= rel_port_wren_q; +p1_upd_val <= rel_port_upd_q; +reload_wayA(0) <= (reload_wayA_upd_q); +reload_wayA(1) <= reload_wayA_q(1); +reload_wayA(2 TO 5) <= reload_wayA_q(2 to 5); +reload_wayA_upd2_d <= reload_wayA_upd_q; +reload_wayA_data_d <= reload_wayA_q; +reload_wayA_upd3_d <= reload_wayA_upd2_q; +reload_wayA_data2_d <= reload_wayA_data_q; +binv_wayA_upd1 <= (binv_wayA_upd_q and ((not ex4_dir_err_val_q) or back_inval_stg4_q)) or ex4_err_det_way_q(0) or ex4_dir_multihit_val; +binv_wayA_upd2_d <= binv_wayA_upd1; +flush_wayA_data1 <= gate(flush_wayA_q, not (ex4_err_det_way_q(0) or ex4_dir_multihit_val)); +flush_wayA_data_d <= flush_wayA_data1; +binv_wayA_upd3_d <= binv_wayA_upd2_q; +flush_wayA_data2_d <= flush_wayA_data_q; +reload_wayB(0) <= (reload_wayB_upd_q); +reload_wayB(1) <= reload_wayB_q(1); +reload_wayB(2 TO 5) <= reload_wayB_q(2 to 5); +reload_wayB_upd2_d <= reload_wayB_upd_q; +reload_wayB_data_d <= reload_wayB_q; +reload_wayB_upd3_d <= reload_wayB_upd2_q; +reload_wayB_data2_d <= reload_wayB_data_q; +binv_wayB_upd1 <= (binv_wayB_upd_q and ((not ex4_dir_err_val_q) or back_inval_stg4_q)) or ex4_err_det_way_q(1) or ex4_dir_multihit_val; +binv_wayB_upd2_d <= binv_wayB_upd1; +flush_wayB_data1 <= gate(flush_wayB_q, not (ex4_err_det_way_q(1) or ex4_dir_multihit_val)); +flush_wayB_data_d <= flush_wayB_data1; +binv_wayB_upd3_d <= binv_wayB_upd2_q; +flush_wayB_data2_d <= flush_wayB_data_q; +reload_wayC(0) <= (reload_wayC_upd_q); +reload_wayC(1) <= reload_wayC_q(1); +reload_wayC(2 TO 5) <= reload_wayC_q(2 to 5); +reload_wayC_upd2_d <= reload_wayC_upd_q; +reload_wayC_data_d <= reload_wayC_q; +reload_wayC_upd3_d <= reload_wayC_upd2_q; +reload_wayC_data2_d <= reload_wayC_data_q; +binv_wayC_upd1 <= (binv_wayC_upd_q and ((not ex4_dir_err_val_q) or back_inval_stg4_q)) or ex4_err_det_way_q(2) or ex4_dir_multihit_val; +binv_wayC_upd2_d <= binv_wayC_upd1; +flush_wayC_data1 <= gate(flush_wayC_q, not (ex4_err_det_way_q(2) or ex4_dir_multihit_val)); +flush_wayC_data_d <= flush_wayC_data1; +binv_wayC_upd3_d <= binv_wayC_upd2_q; +flush_wayC_data2_d <= flush_wayC_data_q; +reload_wayD(0) <= (reload_wayD_upd_q); +reload_wayD(1) <= reload_wayD_q(1); +reload_wayD(2 TO 5) <= reload_wayD_q(2 to 5); +reload_wayD_upd2_d <= reload_wayD_upd_q; +reload_wayD_data_d <= reload_wayD_q; +reload_wayD_upd3_d <= reload_wayD_upd2_q; +reload_wayD_data2_d <= reload_wayD_data_q; +binv_wayD_upd1 <= (binv_wayD_upd_q and ((not ex4_dir_err_val_q) or back_inval_stg4_q)) or ex4_err_det_way_q(3) or ex4_dir_multihit_val; +binv_wayD_upd2_d <= binv_wayD_upd1; +flush_wayD_data1 <= gate(flush_wayD_q, not (ex4_err_det_way_q(3) or ex4_dir_multihit_val)); +flush_wayD_data_d <= flush_wayD_data1; +binv_wayD_upd3_d <= binv_wayD_upd2_q; +flush_wayD_data2_d <= flush_wayD_data_q; +reload_wayE(0) <= (reload_wayE_upd_q); +reload_wayE(1) <= reload_wayE_q(1); +reload_wayE(2 TO 5) <= reload_wayE_q(2 to 5); +reload_wayE_upd2_d <= reload_wayE_upd_q; +reload_wayE_data_d <= reload_wayE_q; +reload_wayE_upd3_d <= reload_wayE_upd2_q; +reload_wayE_data2_d <= reload_wayE_data_q; +binv_wayE_upd1 <= (binv_wayE_upd_q and ((not ex4_dir_err_val_q) or back_inval_stg4_q)) or ex4_err_det_way_q(4) or ex4_dir_multihit_val; +binv_wayE_upd2_d <= binv_wayE_upd1; +flush_wayE_data1 <= gate(flush_wayE_q, not (ex4_err_det_way_q(4) or ex4_dir_multihit_val)); +flush_wayE_data_d <= flush_wayE_data1; +binv_wayE_upd3_d <= binv_wayE_upd2_q; +flush_wayE_data2_d <= flush_wayE_data_q; +reload_wayF(0) <= (reload_wayF_upd_q); +reload_wayF(1) <= reload_wayF_q(1); +reload_wayF(2 TO 5) <= reload_wayF_q(2 to 5); +reload_wayF_upd2_d <= reload_wayF_upd_q; +reload_wayF_data_d <= reload_wayF_q; +reload_wayF_upd3_d <= reload_wayF_upd2_q; +reload_wayF_data2_d <= reload_wayF_data_q; +binv_wayF_upd1 <= (binv_wayF_upd_q and ((not ex4_dir_err_val_q) or back_inval_stg4_q)) or ex4_err_det_way_q(5) or ex4_dir_multihit_val; +binv_wayF_upd2_d <= binv_wayF_upd1; +flush_wayF_data1 <= gate(flush_wayF_q, not (ex4_err_det_way_q(5) or ex4_dir_multihit_val)); +flush_wayF_data_d <= flush_wayF_data1; +binv_wayF_upd3_d <= binv_wayF_upd2_q; +flush_wayF_data2_d <= flush_wayF_data_q; +reload_wayG(0) <= (reload_wayG_upd_q); +reload_wayG(1) <= reload_wayG_q(1); +reload_wayG(2 TO 5) <= reload_wayG_q(2 to 5); +reload_wayG_upd2_d <= reload_wayG_upd_q; +reload_wayG_data_d <= reload_wayG_q; +reload_wayG_upd3_d <= reload_wayG_upd2_q; +reload_wayG_data2_d <= reload_wayG_data_q; +binv_wayG_upd1 <= (binv_wayG_upd_q and ((not ex4_dir_err_val_q) or back_inval_stg4_q)) or ex4_err_det_way_q(6) or ex4_dir_multihit_val; +binv_wayG_upd2_d <= binv_wayG_upd1; +flush_wayG_data1 <= gate(flush_wayG_q, not (ex4_err_det_way_q(6) or ex4_dir_multihit_val)); +flush_wayG_data_d <= flush_wayG_data1; +binv_wayG_upd3_d <= binv_wayG_upd2_q; +flush_wayG_data2_d <= flush_wayG_data_q; +reload_wayH(0) <= (reload_wayH_upd_q); +reload_wayH(1) <= reload_wayH_q(1); +reload_wayH(2 TO 5) <= reload_wayH_q(2 to 5); +reload_wayH_upd2_d <= reload_wayH_upd_q; +reload_wayH_data_d <= reload_wayH_q; +reload_wayH_upd3_d <= reload_wayH_upd2_q; +reload_wayH_data2_d <= reload_wayH_data_q; +binv_wayH_upd1 <= (binv_wayH_upd_q and ((not ex4_dir_err_val_q) or back_inval_stg4_q)) or ex4_err_det_way_q(7) or ex4_dir_multihit_val; +binv_wayH_upd2_d <= binv_wayH_upd1; +flush_wayH_data1 <= gate(flush_wayH_q, not (ex4_err_det_way_q(7) or ex4_dir_multihit_val)); +flush_wayH_data_d <= flush_wayH_data1; +binv_wayH_upd3_d <= binv_wayH_upd2_q; +flush_wayH_data2_d <= flush_wayH_data_q; +congr_cl_all_act_d <= ex5_watch_clr_all_val_q or dci_compl_q or lock_flash_clear_q; +p0_congr_cl0_m <= (ex5_congr_cl_q = tconv(0,5)); +p1_congr_cl0_m <= (relu_s_congr_cl_q = tconv(0,5)); +p0_congr_cl0_act_d <= p0_congr_cl0_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl0_act_d <= p1_congr_cl0_m and rel_port_wren_q; +congr_cl0_act <= p0_congr_cl0_act_q or p1_congr_cl0_act_q or congr_cl_all_act_q; +p0_way_data_upd0_wayA <= p0_congr_cl0_act_q and binv_wayA_upd3_q; +p1_way_data_upd0_wayA <= p1_congr_cl0_act_q and reload_wayA_upd3_q; +rel_bixu0_wayA_upd(0) <= p1_way_data_upd0_wayA and p1_wren_q; +rel_bixu0_wayA_upd(1) <= p0_way_data_upd0_wayA and p0_wren_q; +p0_way_data_upd0_wayB <= p0_congr_cl0_act_q and binv_wayB_upd3_q; +p1_way_data_upd0_wayB <= p1_congr_cl0_act_q and reload_wayB_upd3_q; +rel_bixu0_wayB_upd(0) <= p1_way_data_upd0_wayB and p1_wren_q; +rel_bixu0_wayB_upd(1) <= p0_way_data_upd0_wayB and p0_wren_q; +p0_way_data_upd0_wayC <= p0_congr_cl0_act_q and binv_wayC_upd3_q; +p1_way_data_upd0_wayC <= p1_congr_cl0_act_q and reload_wayC_upd3_q; +rel_bixu0_wayC_upd(0) <= p1_way_data_upd0_wayC and p1_wren_q; +rel_bixu0_wayC_upd(1) <= p0_way_data_upd0_wayC and p0_wren_q; +p0_way_data_upd0_wayD <= p0_congr_cl0_act_q and binv_wayD_upd3_q; +p1_way_data_upd0_wayD <= p1_congr_cl0_act_q and reload_wayD_upd3_q; +rel_bixu0_wayD_upd(0) <= p1_way_data_upd0_wayD and p1_wren_q; +rel_bixu0_wayD_upd(1) <= p0_way_data_upd0_wayD and p0_wren_q; +p0_way_data_upd0_wayE <= p0_congr_cl0_act_q and binv_wayE_upd3_q; +p1_way_data_upd0_wayE <= p1_congr_cl0_act_q and reload_wayE_upd3_q; +rel_bixu0_wayE_upd(0) <= p1_way_data_upd0_wayE and p1_wren_q; +rel_bixu0_wayE_upd(1) <= p0_way_data_upd0_wayE and p0_wren_q; +p0_way_data_upd0_wayF <= p0_congr_cl0_act_q and binv_wayF_upd3_q; +p1_way_data_upd0_wayF <= p1_congr_cl0_act_q and reload_wayF_upd3_q; +rel_bixu0_wayF_upd(0) <= p1_way_data_upd0_wayF and p1_wren_q; +rel_bixu0_wayF_upd(1) <= p0_way_data_upd0_wayF and p0_wren_q; +p0_way_data_upd0_wayG <= p0_congr_cl0_act_q and binv_wayG_upd3_q; +p1_way_data_upd0_wayG <= p1_congr_cl0_act_q and reload_wayG_upd3_q; +rel_bixu0_wayG_upd(0) <= p1_way_data_upd0_wayG and p1_wren_q; +rel_bixu0_wayG_upd(1) <= p0_way_data_upd0_wayG and p0_wren_q; +p0_way_data_upd0_wayH <= p0_congr_cl0_act_q and binv_wayH_upd3_q; +p1_way_data_upd0_wayH <= p1_congr_cl0_act_q and reload_wayH_upd3_q; +rel_bixu0_wayH_upd(0) <= p1_way_data_upd0_wayH and p1_wren_q; +rel_bixu0_wayH_upd(1) <= p0_way_data_upd0_wayH and p0_wren_q; +p0_congr_cl1_m <= (ex5_congr_cl_q = tconv(1,5)); +p1_congr_cl1_m <= (relu_s_congr_cl_q = tconv(1,5)); +p0_congr_cl1_act_d <= p0_congr_cl1_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl1_act_d <= p1_congr_cl1_m and rel_port_wren_q; +congr_cl1_act <= p0_congr_cl1_act_q or p1_congr_cl1_act_q or congr_cl_all_act_q; +p0_way_data_upd1_wayA <= p0_congr_cl1_act_q and binv_wayA_upd3_q; +p1_way_data_upd1_wayA <= p1_congr_cl1_act_q and reload_wayA_upd3_q; +rel_bixu1_wayA_upd(0) <= p1_way_data_upd1_wayA and p1_wren_q; +rel_bixu1_wayA_upd(1) <= p0_way_data_upd1_wayA and p0_wren_q; +p0_way_data_upd1_wayB <= p0_congr_cl1_act_q and binv_wayB_upd3_q; +p1_way_data_upd1_wayB <= p1_congr_cl1_act_q and reload_wayB_upd3_q; +rel_bixu1_wayB_upd(0) <= p1_way_data_upd1_wayB and p1_wren_q; +rel_bixu1_wayB_upd(1) <= p0_way_data_upd1_wayB and p0_wren_q; +p0_way_data_upd1_wayC <= p0_congr_cl1_act_q and binv_wayC_upd3_q; +p1_way_data_upd1_wayC <= p1_congr_cl1_act_q and reload_wayC_upd3_q; +rel_bixu1_wayC_upd(0) <= p1_way_data_upd1_wayC and p1_wren_q; +rel_bixu1_wayC_upd(1) <= p0_way_data_upd1_wayC and p0_wren_q; +p0_way_data_upd1_wayD <= p0_congr_cl1_act_q and binv_wayD_upd3_q; +p1_way_data_upd1_wayD <= p1_congr_cl1_act_q and reload_wayD_upd3_q; +rel_bixu1_wayD_upd(0) <= p1_way_data_upd1_wayD and p1_wren_q; +rel_bixu1_wayD_upd(1) <= p0_way_data_upd1_wayD and p0_wren_q; +p0_way_data_upd1_wayE <= p0_congr_cl1_act_q and binv_wayE_upd3_q; +p1_way_data_upd1_wayE <= p1_congr_cl1_act_q and reload_wayE_upd3_q; +rel_bixu1_wayE_upd(0) <= p1_way_data_upd1_wayE and p1_wren_q; +rel_bixu1_wayE_upd(1) <= p0_way_data_upd1_wayE and p0_wren_q; +p0_way_data_upd1_wayF <= p0_congr_cl1_act_q and binv_wayF_upd3_q; +p1_way_data_upd1_wayF <= p1_congr_cl1_act_q and reload_wayF_upd3_q; +rel_bixu1_wayF_upd(0) <= p1_way_data_upd1_wayF and p1_wren_q; +rel_bixu1_wayF_upd(1) <= p0_way_data_upd1_wayF and p0_wren_q; +p0_way_data_upd1_wayG <= p0_congr_cl1_act_q and binv_wayG_upd3_q; +p1_way_data_upd1_wayG <= p1_congr_cl1_act_q and reload_wayG_upd3_q; +rel_bixu1_wayG_upd(0) <= p1_way_data_upd1_wayG and p1_wren_q; +rel_bixu1_wayG_upd(1) <= p0_way_data_upd1_wayG and p0_wren_q; +p0_way_data_upd1_wayH <= p0_congr_cl1_act_q and binv_wayH_upd3_q; +p1_way_data_upd1_wayH <= p1_congr_cl1_act_q and reload_wayH_upd3_q; +rel_bixu1_wayH_upd(0) <= p1_way_data_upd1_wayH and p1_wren_q; +rel_bixu1_wayH_upd(1) <= p0_way_data_upd1_wayH and p0_wren_q; +p0_congr_cl2_m <= (ex5_congr_cl_q = tconv(2,5)); +p1_congr_cl2_m <= (relu_s_congr_cl_q = tconv(2,5)); +p0_congr_cl2_act_d <= p0_congr_cl2_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl2_act_d <= p1_congr_cl2_m and rel_port_wren_q; +congr_cl2_act <= p0_congr_cl2_act_q or p1_congr_cl2_act_q or congr_cl_all_act_q; +p0_way_data_upd2_wayA <= p0_congr_cl2_act_q and binv_wayA_upd3_q; +p1_way_data_upd2_wayA <= p1_congr_cl2_act_q and reload_wayA_upd3_q; +rel_bixu2_wayA_upd(0) <= p1_way_data_upd2_wayA and p1_wren_q; +rel_bixu2_wayA_upd(1) <= p0_way_data_upd2_wayA and p0_wren_q; +p0_way_data_upd2_wayB <= p0_congr_cl2_act_q and binv_wayB_upd3_q; +p1_way_data_upd2_wayB <= p1_congr_cl2_act_q and reload_wayB_upd3_q; +rel_bixu2_wayB_upd(0) <= p1_way_data_upd2_wayB and p1_wren_q; +rel_bixu2_wayB_upd(1) <= p0_way_data_upd2_wayB and p0_wren_q; +p0_way_data_upd2_wayC <= p0_congr_cl2_act_q and binv_wayC_upd3_q; +p1_way_data_upd2_wayC <= p1_congr_cl2_act_q and reload_wayC_upd3_q; +rel_bixu2_wayC_upd(0) <= p1_way_data_upd2_wayC and p1_wren_q; +rel_bixu2_wayC_upd(1) <= p0_way_data_upd2_wayC and p0_wren_q; +p0_way_data_upd2_wayD <= p0_congr_cl2_act_q and binv_wayD_upd3_q; +p1_way_data_upd2_wayD <= p1_congr_cl2_act_q and reload_wayD_upd3_q; +rel_bixu2_wayD_upd(0) <= p1_way_data_upd2_wayD and p1_wren_q; +rel_bixu2_wayD_upd(1) <= p0_way_data_upd2_wayD and p0_wren_q; +p0_way_data_upd2_wayE <= p0_congr_cl2_act_q and binv_wayE_upd3_q; +p1_way_data_upd2_wayE <= p1_congr_cl2_act_q and reload_wayE_upd3_q; +rel_bixu2_wayE_upd(0) <= p1_way_data_upd2_wayE and p1_wren_q; +rel_bixu2_wayE_upd(1) <= p0_way_data_upd2_wayE and p0_wren_q; +p0_way_data_upd2_wayF <= p0_congr_cl2_act_q and binv_wayF_upd3_q; +p1_way_data_upd2_wayF <= p1_congr_cl2_act_q and reload_wayF_upd3_q; +rel_bixu2_wayF_upd(0) <= p1_way_data_upd2_wayF and p1_wren_q; +rel_bixu2_wayF_upd(1) <= p0_way_data_upd2_wayF and p0_wren_q; +p0_way_data_upd2_wayG <= p0_congr_cl2_act_q and binv_wayG_upd3_q; +p1_way_data_upd2_wayG <= p1_congr_cl2_act_q and reload_wayG_upd3_q; +rel_bixu2_wayG_upd(0) <= p1_way_data_upd2_wayG and p1_wren_q; +rel_bixu2_wayG_upd(1) <= p0_way_data_upd2_wayG and p0_wren_q; +p0_way_data_upd2_wayH <= p0_congr_cl2_act_q and binv_wayH_upd3_q; +p1_way_data_upd2_wayH <= p1_congr_cl2_act_q and reload_wayH_upd3_q; +rel_bixu2_wayH_upd(0) <= p1_way_data_upd2_wayH and p1_wren_q; +rel_bixu2_wayH_upd(1) <= p0_way_data_upd2_wayH and p0_wren_q; +p0_congr_cl3_m <= (ex5_congr_cl_q = tconv(3,5)); +p1_congr_cl3_m <= (relu_s_congr_cl_q = tconv(3,5)); +p0_congr_cl3_act_d <= p0_congr_cl3_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl3_act_d <= p1_congr_cl3_m and rel_port_wren_q; +congr_cl3_act <= p0_congr_cl3_act_q or p1_congr_cl3_act_q or congr_cl_all_act_q; +p0_way_data_upd3_wayA <= p0_congr_cl3_act_q and binv_wayA_upd3_q; +p1_way_data_upd3_wayA <= p1_congr_cl3_act_q and reload_wayA_upd3_q; +rel_bixu3_wayA_upd(0) <= p1_way_data_upd3_wayA and p1_wren_q; +rel_bixu3_wayA_upd(1) <= p0_way_data_upd3_wayA and p0_wren_q; +p0_way_data_upd3_wayB <= p0_congr_cl3_act_q and binv_wayB_upd3_q; +p1_way_data_upd3_wayB <= p1_congr_cl3_act_q and reload_wayB_upd3_q; +rel_bixu3_wayB_upd(0) <= p1_way_data_upd3_wayB and p1_wren_q; +rel_bixu3_wayB_upd(1) <= p0_way_data_upd3_wayB and p0_wren_q; +p0_way_data_upd3_wayC <= p0_congr_cl3_act_q and binv_wayC_upd3_q; +p1_way_data_upd3_wayC <= p1_congr_cl3_act_q and reload_wayC_upd3_q; +rel_bixu3_wayC_upd(0) <= p1_way_data_upd3_wayC and p1_wren_q; +rel_bixu3_wayC_upd(1) <= p0_way_data_upd3_wayC and p0_wren_q; +p0_way_data_upd3_wayD <= p0_congr_cl3_act_q and binv_wayD_upd3_q; +p1_way_data_upd3_wayD <= p1_congr_cl3_act_q and reload_wayD_upd3_q; +rel_bixu3_wayD_upd(0) <= p1_way_data_upd3_wayD and p1_wren_q; +rel_bixu3_wayD_upd(1) <= p0_way_data_upd3_wayD and p0_wren_q; +p0_way_data_upd3_wayE <= p0_congr_cl3_act_q and binv_wayE_upd3_q; +p1_way_data_upd3_wayE <= p1_congr_cl3_act_q and reload_wayE_upd3_q; +rel_bixu3_wayE_upd(0) <= p1_way_data_upd3_wayE and p1_wren_q; +rel_bixu3_wayE_upd(1) <= p0_way_data_upd3_wayE and p0_wren_q; +p0_way_data_upd3_wayF <= p0_congr_cl3_act_q and binv_wayF_upd3_q; +p1_way_data_upd3_wayF <= p1_congr_cl3_act_q and reload_wayF_upd3_q; +rel_bixu3_wayF_upd(0) <= p1_way_data_upd3_wayF and p1_wren_q; +rel_bixu3_wayF_upd(1) <= p0_way_data_upd3_wayF and p0_wren_q; +p0_way_data_upd3_wayG <= p0_congr_cl3_act_q and binv_wayG_upd3_q; +p1_way_data_upd3_wayG <= p1_congr_cl3_act_q and reload_wayG_upd3_q; +rel_bixu3_wayG_upd(0) <= p1_way_data_upd3_wayG and p1_wren_q; +rel_bixu3_wayG_upd(1) <= p0_way_data_upd3_wayG and p0_wren_q; +p0_way_data_upd3_wayH <= p0_congr_cl3_act_q and binv_wayH_upd3_q; +p1_way_data_upd3_wayH <= p1_congr_cl3_act_q and reload_wayH_upd3_q; +rel_bixu3_wayH_upd(0) <= p1_way_data_upd3_wayH and p1_wren_q; +rel_bixu3_wayH_upd(1) <= p0_way_data_upd3_wayH and p0_wren_q; +p0_congr_cl4_m <= (ex5_congr_cl_q = tconv(4,5)); +p1_congr_cl4_m <= (relu_s_congr_cl_q = tconv(4,5)); +p0_congr_cl4_act_d <= p0_congr_cl4_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl4_act_d <= p1_congr_cl4_m and rel_port_wren_q; +congr_cl4_act <= p0_congr_cl4_act_q or p1_congr_cl4_act_q or congr_cl_all_act_q; +p0_way_data_upd4_wayA <= p0_congr_cl4_act_q and binv_wayA_upd3_q; +p1_way_data_upd4_wayA <= p1_congr_cl4_act_q and reload_wayA_upd3_q; +rel_bixu4_wayA_upd(0) <= p1_way_data_upd4_wayA and p1_wren_q; +rel_bixu4_wayA_upd(1) <= p0_way_data_upd4_wayA and p0_wren_q; +p0_way_data_upd4_wayB <= p0_congr_cl4_act_q and binv_wayB_upd3_q; +p1_way_data_upd4_wayB <= p1_congr_cl4_act_q and reload_wayB_upd3_q; +rel_bixu4_wayB_upd(0) <= p1_way_data_upd4_wayB and p1_wren_q; +rel_bixu4_wayB_upd(1) <= p0_way_data_upd4_wayB and p0_wren_q; +p0_way_data_upd4_wayC <= p0_congr_cl4_act_q and binv_wayC_upd3_q; +p1_way_data_upd4_wayC <= p1_congr_cl4_act_q and reload_wayC_upd3_q; +rel_bixu4_wayC_upd(0) <= p1_way_data_upd4_wayC and p1_wren_q; +rel_bixu4_wayC_upd(1) <= p0_way_data_upd4_wayC and p0_wren_q; +p0_way_data_upd4_wayD <= p0_congr_cl4_act_q and binv_wayD_upd3_q; +p1_way_data_upd4_wayD <= p1_congr_cl4_act_q and reload_wayD_upd3_q; +rel_bixu4_wayD_upd(0) <= p1_way_data_upd4_wayD and p1_wren_q; +rel_bixu4_wayD_upd(1) <= p0_way_data_upd4_wayD and p0_wren_q; +p0_way_data_upd4_wayE <= p0_congr_cl4_act_q and binv_wayE_upd3_q; +p1_way_data_upd4_wayE <= p1_congr_cl4_act_q and reload_wayE_upd3_q; +rel_bixu4_wayE_upd(0) <= p1_way_data_upd4_wayE and p1_wren_q; +rel_bixu4_wayE_upd(1) <= p0_way_data_upd4_wayE and p0_wren_q; +p0_way_data_upd4_wayF <= p0_congr_cl4_act_q and binv_wayF_upd3_q; +p1_way_data_upd4_wayF <= p1_congr_cl4_act_q and reload_wayF_upd3_q; +rel_bixu4_wayF_upd(0) <= p1_way_data_upd4_wayF and p1_wren_q; +rel_bixu4_wayF_upd(1) <= p0_way_data_upd4_wayF and p0_wren_q; +p0_way_data_upd4_wayG <= p0_congr_cl4_act_q and binv_wayG_upd3_q; +p1_way_data_upd4_wayG <= p1_congr_cl4_act_q and reload_wayG_upd3_q; +rel_bixu4_wayG_upd(0) <= p1_way_data_upd4_wayG and p1_wren_q; +rel_bixu4_wayG_upd(1) <= p0_way_data_upd4_wayG and p0_wren_q; +p0_way_data_upd4_wayH <= p0_congr_cl4_act_q and binv_wayH_upd3_q; +p1_way_data_upd4_wayH <= p1_congr_cl4_act_q and reload_wayH_upd3_q; +rel_bixu4_wayH_upd(0) <= p1_way_data_upd4_wayH and p1_wren_q; +rel_bixu4_wayH_upd(1) <= p0_way_data_upd4_wayH and p0_wren_q; +p0_congr_cl5_m <= (ex5_congr_cl_q = tconv(5,5)); +p1_congr_cl5_m <= (relu_s_congr_cl_q = tconv(5,5)); +p0_congr_cl5_act_d <= p0_congr_cl5_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl5_act_d <= p1_congr_cl5_m and rel_port_wren_q; +congr_cl5_act <= p0_congr_cl5_act_q or p1_congr_cl5_act_q or congr_cl_all_act_q; +p0_way_data_upd5_wayA <= p0_congr_cl5_act_q and binv_wayA_upd3_q; +p1_way_data_upd5_wayA <= p1_congr_cl5_act_q and reload_wayA_upd3_q; +rel_bixu5_wayA_upd(0) <= p1_way_data_upd5_wayA and p1_wren_q; +rel_bixu5_wayA_upd(1) <= p0_way_data_upd5_wayA and p0_wren_q; +p0_way_data_upd5_wayB <= p0_congr_cl5_act_q and binv_wayB_upd3_q; +p1_way_data_upd5_wayB <= p1_congr_cl5_act_q and reload_wayB_upd3_q; +rel_bixu5_wayB_upd(0) <= p1_way_data_upd5_wayB and p1_wren_q; +rel_bixu5_wayB_upd(1) <= p0_way_data_upd5_wayB and p0_wren_q; +p0_way_data_upd5_wayC <= p0_congr_cl5_act_q and binv_wayC_upd3_q; +p1_way_data_upd5_wayC <= p1_congr_cl5_act_q and reload_wayC_upd3_q; +rel_bixu5_wayC_upd(0) <= p1_way_data_upd5_wayC and p1_wren_q; +rel_bixu5_wayC_upd(1) <= p0_way_data_upd5_wayC and p0_wren_q; +p0_way_data_upd5_wayD <= p0_congr_cl5_act_q and binv_wayD_upd3_q; +p1_way_data_upd5_wayD <= p1_congr_cl5_act_q and reload_wayD_upd3_q; +rel_bixu5_wayD_upd(0) <= p1_way_data_upd5_wayD and p1_wren_q; +rel_bixu5_wayD_upd(1) <= p0_way_data_upd5_wayD and p0_wren_q; +p0_way_data_upd5_wayE <= p0_congr_cl5_act_q and binv_wayE_upd3_q; +p1_way_data_upd5_wayE <= p1_congr_cl5_act_q and reload_wayE_upd3_q; +rel_bixu5_wayE_upd(0) <= p1_way_data_upd5_wayE and p1_wren_q; +rel_bixu5_wayE_upd(1) <= p0_way_data_upd5_wayE and p0_wren_q; +p0_way_data_upd5_wayF <= p0_congr_cl5_act_q and binv_wayF_upd3_q; +p1_way_data_upd5_wayF <= p1_congr_cl5_act_q and reload_wayF_upd3_q; +rel_bixu5_wayF_upd(0) <= p1_way_data_upd5_wayF and p1_wren_q; +rel_bixu5_wayF_upd(1) <= p0_way_data_upd5_wayF and p0_wren_q; +p0_way_data_upd5_wayG <= p0_congr_cl5_act_q and binv_wayG_upd3_q; +p1_way_data_upd5_wayG <= p1_congr_cl5_act_q and reload_wayG_upd3_q; +rel_bixu5_wayG_upd(0) <= p1_way_data_upd5_wayG and p1_wren_q; +rel_bixu5_wayG_upd(1) <= p0_way_data_upd5_wayG and p0_wren_q; +p0_way_data_upd5_wayH <= p0_congr_cl5_act_q and binv_wayH_upd3_q; +p1_way_data_upd5_wayH <= p1_congr_cl5_act_q and reload_wayH_upd3_q; +rel_bixu5_wayH_upd(0) <= p1_way_data_upd5_wayH and p1_wren_q; +rel_bixu5_wayH_upd(1) <= p0_way_data_upd5_wayH and p0_wren_q; +p0_congr_cl6_m <= (ex5_congr_cl_q = tconv(6,5)); +p1_congr_cl6_m <= (relu_s_congr_cl_q = tconv(6,5)); +p0_congr_cl6_act_d <= p0_congr_cl6_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl6_act_d <= p1_congr_cl6_m and rel_port_wren_q; +congr_cl6_act <= p0_congr_cl6_act_q or p1_congr_cl6_act_q or congr_cl_all_act_q; +p0_way_data_upd6_wayA <= p0_congr_cl6_act_q and binv_wayA_upd3_q; +p1_way_data_upd6_wayA <= p1_congr_cl6_act_q and reload_wayA_upd3_q; +rel_bixu6_wayA_upd(0) <= p1_way_data_upd6_wayA and p1_wren_q; +rel_bixu6_wayA_upd(1) <= p0_way_data_upd6_wayA and p0_wren_q; +p0_way_data_upd6_wayB <= p0_congr_cl6_act_q and binv_wayB_upd3_q; +p1_way_data_upd6_wayB <= p1_congr_cl6_act_q and reload_wayB_upd3_q; +rel_bixu6_wayB_upd(0) <= p1_way_data_upd6_wayB and p1_wren_q; +rel_bixu6_wayB_upd(1) <= p0_way_data_upd6_wayB and p0_wren_q; +p0_way_data_upd6_wayC <= p0_congr_cl6_act_q and binv_wayC_upd3_q; +p1_way_data_upd6_wayC <= p1_congr_cl6_act_q and reload_wayC_upd3_q; +rel_bixu6_wayC_upd(0) <= p1_way_data_upd6_wayC and p1_wren_q; +rel_bixu6_wayC_upd(1) <= p0_way_data_upd6_wayC and p0_wren_q; +p0_way_data_upd6_wayD <= p0_congr_cl6_act_q and binv_wayD_upd3_q; +p1_way_data_upd6_wayD <= p1_congr_cl6_act_q and reload_wayD_upd3_q; +rel_bixu6_wayD_upd(0) <= p1_way_data_upd6_wayD and p1_wren_q; +rel_bixu6_wayD_upd(1) <= p0_way_data_upd6_wayD and p0_wren_q; +p0_way_data_upd6_wayE <= p0_congr_cl6_act_q and binv_wayE_upd3_q; +p1_way_data_upd6_wayE <= p1_congr_cl6_act_q and reload_wayE_upd3_q; +rel_bixu6_wayE_upd(0) <= p1_way_data_upd6_wayE and p1_wren_q; +rel_bixu6_wayE_upd(1) <= p0_way_data_upd6_wayE and p0_wren_q; +p0_way_data_upd6_wayF <= p0_congr_cl6_act_q and binv_wayF_upd3_q; +p1_way_data_upd6_wayF <= p1_congr_cl6_act_q and reload_wayF_upd3_q; +rel_bixu6_wayF_upd(0) <= p1_way_data_upd6_wayF and p1_wren_q; +rel_bixu6_wayF_upd(1) <= p0_way_data_upd6_wayF and p0_wren_q; +p0_way_data_upd6_wayG <= p0_congr_cl6_act_q and binv_wayG_upd3_q; +p1_way_data_upd6_wayG <= p1_congr_cl6_act_q and reload_wayG_upd3_q; +rel_bixu6_wayG_upd(0) <= p1_way_data_upd6_wayG and p1_wren_q; +rel_bixu6_wayG_upd(1) <= p0_way_data_upd6_wayG and p0_wren_q; +p0_way_data_upd6_wayH <= p0_congr_cl6_act_q and binv_wayH_upd3_q; +p1_way_data_upd6_wayH <= p1_congr_cl6_act_q and reload_wayH_upd3_q; +rel_bixu6_wayH_upd(0) <= p1_way_data_upd6_wayH and p1_wren_q; +rel_bixu6_wayH_upd(1) <= p0_way_data_upd6_wayH and p0_wren_q; +p0_congr_cl7_m <= (ex5_congr_cl_q = tconv(7,5)); +p1_congr_cl7_m <= (relu_s_congr_cl_q = tconv(7,5)); +p0_congr_cl7_act_d <= p0_congr_cl7_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl7_act_d <= p1_congr_cl7_m and rel_port_wren_q; +congr_cl7_act <= p0_congr_cl7_act_q or p1_congr_cl7_act_q or congr_cl_all_act_q; +p0_way_data_upd7_wayA <= p0_congr_cl7_act_q and binv_wayA_upd3_q; +p1_way_data_upd7_wayA <= p1_congr_cl7_act_q and reload_wayA_upd3_q; +rel_bixu7_wayA_upd(0) <= p1_way_data_upd7_wayA and p1_wren_q; +rel_bixu7_wayA_upd(1) <= p0_way_data_upd7_wayA and p0_wren_q; +p0_way_data_upd7_wayB <= p0_congr_cl7_act_q and binv_wayB_upd3_q; +p1_way_data_upd7_wayB <= p1_congr_cl7_act_q and reload_wayB_upd3_q; +rel_bixu7_wayB_upd(0) <= p1_way_data_upd7_wayB and p1_wren_q; +rel_bixu7_wayB_upd(1) <= p0_way_data_upd7_wayB and p0_wren_q; +p0_way_data_upd7_wayC <= p0_congr_cl7_act_q and binv_wayC_upd3_q; +p1_way_data_upd7_wayC <= p1_congr_cl7_act_q and reload_wayC_upd3_q; +rel_bixu7_wayC_upd(0) <= p1_way_data_upd7_wayC and p1_wren_q; +rel_bixu7_wayC_upd(1) <= p0_way_data_upd7_wayC and p0_wren_q; +p0_way_data_upd7_wayD <= p0_congr_cl7_act_q and binv_wayD_upd3_q; +p1_way_data_upd7_wayD <= p1_congr_cl7_act_q and reload_wayD_upd3_q; +rel_bixu7_wayD_upd(0) <= p1_way_data_upd7_wayD and p1_wren_q; +rel_bixu7_wayD_upd(1) <= p0_way_data_upd7_wayD and p0_wren_q; +p0_way_data_upd7_wayE <= p0_congr_cl7_act_q and binv_wayE_upd3_q; +p1_way_data_upd7_wayE <= p1_congr_cl7_act_q and reload_wayE_upd3_q; +rel_bixu7_wayE_upd(0) <= p1_way_data_upd7_wayE and p1_wren_q; +rel_bixu7_wayE_upd(1) <= p0_way_data_upd7_wayE and p0_wren_q; +p0_way_data_upd7_wayF <= p0_congr_cl7_act_q and binv_wayF_upd3_q; +p1_way_data_upd7_wayF <= p1_congr_cl7_act_q and reload_wayF_upd3_q; +rel_bixu7_wayF_upd(0) <= p1_way_data_upd7_wayF and p1_wren_q; +rel_bixu7_wayF_upd(1) <= p0_way_data_upd7_wayF and p0_wren_q; +p0_way_data_upd7_wayG <= p0_congr_cl7_act_q and binv_wayG_upd3_q; +p1_way_data_upd7_wayG <= p1_congr_cl7_act_q and reload_wayG_upd3_q; +rel_bixu7_wayG_upd(0) <= p1_way_data_upd7_wayG and p1_wren_q; +rel_bixu7_wayG_upd(1) <= p0_way_data_upd7_wayG and p0_wren_q; +p0_way_data_upd7_wayH <= p0_congr_cl7_act_q and binv_wayH_upd3_q; +p1_way_data_upd7_wayH <= p1_congr_cl7_act_q and reload_wayH_upd3_q; +rel_bixu7_wayH_upd(0) <= p1_way_data_upd7_wayH and p1_wren_q; +rel_bixu7_wayH_upd(1) <= p0_way_data_upd7_wayH and p0_wren_q; +p0_congr_cl8_m <= (ex5_congr_cl_q = tconv(8,5)); +p1_congr_cl8_m <= (relu_s_congr_cl_q = tconv(8,5)); +p0_congr_cl8_act_d <= p0_congr_cl8_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl8_act_d <= p1_congr_cl8_m and rel_port_wren_q; +congr_cl8_act <= p0_congr_cl8_act_q or p1_congr_cl8_act_q or congr_cl_all_act_q; +p0_way_data_upd8_wayA <= p0_congr_cl8_act_q and binv_wayA_upd3_q; +p1_way_data_upd8_wayA <= p1_congr_cl8_act_q and reload_wayA_upd3_q; +rel_bixu8_wayA_upd(0) <= p1_way_data_upd8_wayA and p1_wren_q; +rel_bixu8_wayA_upd(1) <= p0_way_data_upd8_wayA and p0_wren_q; +p0_way_data_upd8_wayB <= p0_congr_cl8_act_q and binv_wayB_upd3_q; +p1_way_data_upd8_wayB <= p1_congr_cl8_act_q and reload_wayB_upd3_q; +rel_bixu8_wayB_upd(0) <= p1_way_data_upd8_wayB and p1_wren_q; +rel_bixu8_wayB_upd(1) <= p0_way_data_upd8_wayB and p0_wren_q; +p0_way_data_upd8_wayC <= p0_congr_cl8_act_q and binv_wayC_upd3_q; +p1_way_data_upd8_wayC <= p1_congr_cl8_act_q and reload_wayC_upd3_q; +rel_bixu8_wayC_upd(0) <= p1_way_data_upd8_wayC and p1_wren_q; +rel_bixu8_wayC_upd(1) <= p0_way_data_upd8_wayC and p0_wren_q; +p0_way_data_upd8_wayD <= p0_congr_cl8_act_q and binv_wayD_upd3_q; +p1_way_data_upd8_wayD <= p1_congr_cl8_act_q and reload_wayD_upd3_q; +rel_bixu8_wayD_upd(0) <= p1_way_data_upd8_wayD and p1_wren_q; +rel_bixu8_wayD_upd(1) <= p0_way_data_upd8_wayD and p0_wren_q; +p0_way_data_upd8_wayE <= p0_congr_cl8_act_q and binv_wayE_upd3_q; +p1_way_data_upd8_wayE <= p1_congr_cl8_act_q and reload_wayE_upd3_q; +rel_bixu8_wayE_upd(0) <= p1_way_data_upd8_wayE and p1_wren_q; +rel_bixu8_wayE_upd(1) <= p0_way_data_upd8_wayE and p0_wren_q; +p0_way_data_upd8_wayF <= p0_congr_cl8_act_q and binv_wayF_upd3_q; +p1_way_data_upd8_wayF <= p1_congr_cl8_act_q and reload_wayF_upd3_q; +rel_bixu8_wayF_upd(0) <= p1_way_data_upd8_wayF and p1_wren_q; +rel_bixu8_wayF_upd(1) <= p0_way_data_upd8_wayF and p0_wren_q; +p0_way_data_upd8_wayG <= p0_congr_cl8_act_q and binv_wayG_upd3_q; +p1_way_data_upd8_wayG <= p1_congr_cl8_act_q and reload_wayG_upd3_q; +rel_bixu8_wayG_upd(0) <= p1_way_data_upd8_wayG and p1_wren_q; +rel_bixu8_wayG_upd(1) <= p0_way_data_upd8_wayG and p0_wren_q; +p0_way_data_upd8_wayH <= p0_congr_cl8_act_q and binv_wayH_upd3_q; +p1_way_data_upd8_wayH <= p1_congr_cl8_act_q and reload_wayH_upd3_q; +rel_bixu8_wayH_upd(0) <= p1_way_data_upd8_wayH and p1_wren_q; +rel_bixu8_wayH_upd(1) <= p0_way_data_upd8_wayH and p0_wren_q; +p0_congr_cl9_m <= (ex5_congr_cl_q = tconv(9,5)); +p1_congr_cl9_m <= (relu_s_congr_cl_q = tconv(9,5)); +p0_congr_cl9_act_d <= p0_congr_cl9_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl9_act_d <= p1_congr_cl9_m and rel_port_wren_q; +congr_cl9_act <= p0_congr_cl9_act_q or p1_congr_cl9_act_q or congr_cl_all_act_q; +p0_way_data_upd9_wayA <= p0_congr_cl9_act_q and binv_wayA_upd3_q; +p1_way_data_upd9_wayA <= p1_congr_cl9_act_q and reload_wayA_upd3_q; +rel_bixu9_wayA_upd(0) <= p1_way_data_upd9_wayA and p1_wren_q; +rel_bixu9_wayA_upd(1) <= p0_way_data_upd9_wayA and p0_wren_q; +p0_way_data_upd9_wayB <= p0_congr_cl9_act_q and binv_wayB_upd3_q; +p1_way_data_upd9_wayB <= p1_congr_cl9_act_q and reload_wayB_upd3_q; +rel_bixu9_wayB_upd(0) <= p1_way_data_upd9_wayB and p1_wren_q; +rel_bixu9_wayB_upd(1) <= p0_way_data_upd9_wayB and p0_wren_q; +p0_way_data_upd9_wayC <= p0_congr_cl9_act_q and binv_wayC_upd3_q; +p1_way_data_upd9_wayC <= p1_congr_cl9_act_q and reload_wayC_upd3_q; +rel_bixu9_wayC_upd(0) <= p1_way_data_upd9_wayC and p1_wren_q; +rel_bixu9_wayC_upd(1) <= p0_way_data_upd9_wayC and p0_wren_q; +p0_way_data_upd9_wayD <= p0_congr_cl9_act_q and binv_wayD_upd3_q; +p1_way_data_upd9_wayD <= p1_congr_cl9_act_q and reload_wayD_upd3_q; +rel_bixu9_wayD_upd(0) <= p1_way_data_upd9_wayD and p1_wren_q; +rel_bixu9_wayD_upd(1) <= p0_way_data_upd9_wayD and p0_wren_q; +p0_way_data_upd9_wayE <= p0_congr_cl9_act_q and binv_wayE_upd3_q; +p1_way_data_upd9_wayE <= p1_congr_cl9_act_q and reload_wayE_upd3_q; +rel_bixu9_wayE_upd(0) <= p1_way_data_upd9_wayE and p1_wren_q; +rel_bixu9_wayE_upd(1) <= p0_way_data_upd9_wayE and p0_wren_q; +p0_way_data_upd9_wayF <= p0_congr_cl9_act_q and binv_wayF_upd3_q; +p1_way_data_upd9_wayF <= p1_congr_cl9_act_q and reload_wayF_upd3_q; +rel_bixu9_wayF_upd(0) <= p1_way_data_upd9_wayF and p1_wren_q; +rel_bixu9_wayF_upd(1) <= p0_way_data_upd9_wayF and p0_wren_q; +p0_way_data_upd9_wayG <= p0_congr_cl9_act_q and binv_wayG_upd3_q; +p1_way_data_upd9_wayG <= p1_congr_cl9_act_q and reload_wayG_upd3_q; +rel_bixu9_wayG_upd(0) <= p1_way_data_upd9_wayG and p1_wren_q; +rel_bixu9_wayG_upd(1) <= p0_way_data_upd9_wayG and p0_wren_q; +p0_way_data_upd9_wayH <= p0_congr_cl9_act_q and binv_wayH_upd3_q; +p1_way_data_upd9_wayH <= p1_congr_cl9_act_q and reload_wayH_upd3_q; +rel_bixu9_wayH_upd(0) <= p1_way_data_upd9_wayH and p1_wren_q; +rel_bixu9_wayH_upd(1) <= p0_way_data_upd9_wayH and p0_wren_q; +p0_congr_cl10_m <= (ex5_congr_cl_q = tconv(10,5)); +p1_congr_cl10_m <= (relu_s_congr_cl_q = tconv(10,5)); +p0_congr_cl10_act_d <= p0_congr_cl10_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl10_act_d <= p1_congr_cl10_m and rel_port_wren_q; +congr_cl10_act <= p0_congr_cl10_act_q or p1_congr_cl10_act_q or congr_cl_all_act_q; +p0_way_data_upd10_wayA <= p0_congr_cl10_act_q and binv_wayA_upd3_q; +p1_way_data_upd10_wayA <= p1_congr_cl10_act_q and reload_wayA_upd3_q; +rel_bixu10_wayA_upd(0) <= p1_way_data_upd10_wayA and p1_wren_q; +rel_bixu10_wayA_upd(1) <= p0_way_data_upd10_wayA and p0_wren_q; +p0_way_data_upd10_wayB <= p0_congr_cl10_act_q and binv_wayB_upd3_q; +p1_way_data_upd10_wayB <= p1_congr_cl10_act_q and reload_wayB_upd3_q; +rel_bixu10_wayB_upd(0) <= p1_way_data_upd10_wayB and p1_wren_q; +rel_bixu10_wayB_upd(1) <= p0_way_data_upd10_wayB and p0_wren_q; +p0_way_data_upd10_wayC <= p0_congr_cl10_act_q and binv_wayC_upd3_q; +p1_way_data_upd10_wayC <= p1_congr_cl10_act_q and reload_wayC_upd3_q; +rel_bixu10_wayC_upd(0) <= p1_way_data_upd10_wayC and p1_wren_q; +rel_bixu10_wayC_upd(1) <= p0_way_data_upd10_wayC and p0_wren_q; +p0_way_data_upd10_wayD <= p0_congr_cl10_act_q and binv_wayD_upd3_q; +p1_way_data_upd10_wayD <= p1_congr_cl10_act_q and reload_wayD_upd3_q; +rel_bixu10_wayD_upd(0) <= p1_way_data_upd10_wayD and p1_wren_q; +rel_bixu10_wayD_upd(1) <= p0_way_data_upd10_wayD and p0_wren_q; +p0_way_data_upd10_wayE <= p0_congr_cl10_act_q and binv_wayE_upd3_q; +p1_way_data_upd10_wayE <= p1_congr_cl10_act_q and reload_wayE_upd3_q; +rel_bixu10_wayE_upd(0) <= p1_way_data_upd10_wayE and p1_wren_q; +rel_bixu10_wayE_upd(1) <= p0_way_data_upd10_wayE and p0_wren_q; +p0_way_data_upd10_wayF <= p0_congr_cl10_act_q and binv_wayF_upd3_q; +p1_way_data_upd10_wayF <= p1_congr_cl10_act_q and reload_wayF_upd3_q; +rel_bixu10_wayF_upd(0) <= p1_way_data_upd10_wayF and p1_wren_q; +rel_bixu10_wayF_upd(1) <= p0_way_data_upd10_wayF and p0_wren_q; +p0_way_data_upd10_wayG <= p0_congr_cl10_act_q and binv_wayG_upd3_q; +p1_way_data_upd10_wayG <= p1_congr_cl10_act_q and reload_wayG_upd3_q; +rel_bixu10_wayG_upd(0) <= p1_way_data_upd10_wayG and p1_wren_q; +rel_bixu10_wayG_upd(1) <= p0_way_data_upd10_wayG and p0_wren_q; +p0_way_data_upd10_wayH <= p0_congr_cl10_act_q and binv_wayH_upd3_q; +p1_way_data_upd10_wayH <= p1_congr_cl10_act_q and reload_wayH_upd3_q; +rel_bixu10_wayH_upd(0) <= p1_way_data_upd10_wayH and p1_wren_q; +rel_bixu10_wayH_upd(1) <= p0_way_data_upd10_wayH and p0_wren_q; +p0_congr_cl11_m <= (ex5_congr_cl_q = tconv(11,5)); +p1_congr_cl11_m <= (relu_s_congr_cl_q = tconv(11,5)); +p0_congr_cl11_act_d <= p0_congr_cl11_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl11_act_d <= p1_congr_cl11_m and rel_port_wren_q; +congr_cl11_act <= p0_congr_cl11_act_q or p1_congr_cl11_act_q or congr_cl_all_act_q; +p0_way_data_upd11_wayA <= p0_congr_cl11_act_q and binv_wayA_upd3_q; +p1_way_data_upd11_wayA <= p1_congr_cl11_act_q and reload_wayA_upd3_q; +rel_bixu11_wayA_upd(0) <= p1_way_data_upd11_wayA and p1_wren_q; +rel_bixu11_wayA_upd(1) <= p0_way_data_upd11_wayA and p0_wren_q; +p0_way_data_upd11_wayB <= p0_congr_cl11_act_q and binv_wayB_upd3_q; +p1_way_data_upd11_wayB <= p1_congr_cl11_act_q and reload_wayB_upd3_q; +rel_bixu11_wayB_upd(0) <= p1_way_data_upd11_wayB and p1_wren_q; +rel_bixu11_wayB_upd(1) <= p0_way_data_upd11_wayB and p0_wren_q; +p0_way_data_upd11_wayC <= p0_congr_cl11_act_q and binv_wayC_upd3_q; +p1_way_data_upd11_wayC <= p1_congr_cl11_act_q and reload_wayC_upd3_q; +rel_bixu11_wayC_upd(0) <= p1_way_data_upd11_wayC and p1_wren_q; +rel_bixu11_wayC_upd(1) <= p0_way_data_upd11_wayC and p0_wren_q; +p0_way_data_upd11_wayD <= p0_congr_cl11_act_q and binv_wayD_upd3_q; +p1_way_data_upd11_wayD <= p1_congr_cl11_act_q and reload_wayD_upd3_q; +rel_bixu11_wayD_upd(0) <= p1_way_data_upd11_wayD and p1_wren_q; +rel_bixu11_wayD_upd(1) <= p0_way_data_upd11_wayD and p0_wren_q; +p0_way_data_upd11_wayE <= p0_congr_cl11_act_q and binv_wayE_upd3_q; +p1_way_data_upd11_wayE <= p1_congr_cl11_act_q and reload_wayE_upd3_q; +rel_bixu11_wayE_upd(0) <= p1_way_data_upd11_wayE and p1_wren_q; +rel_bixu11_wayE_upd(1) <= p0_way_data_upd11_wayE and p0_wren_q; +p0_way_data_upd11_wayF <= p0_congr_cl11_act_q and binv_wayF_upd3_q; +p1_way_data_upd11_wayF <= p1_congr_cl11_act_q and reload_wayF_upd3_q; +rel_bixu11_wayF_upd(0) <= p1_way_data_upd11_wayF and p1_wren_q; +rel_bixu11_wayF_upd(1) <= p0_way_data_upd11_wayF and p0_wren_q; +p0_way_data_upd11_wayG <= p0_congr_cl11_act_q and binv_wayG_upd3_q; +p1_way_data_upd11_wayG <= p1_congr_cl11_act_q and reload_wayG_upd3_q; +rel_bixu11_wayG_upd(0) <= p1_way_data_upd11_wayG and p1_wren_q; +rel_bixu11_wayG_upd(1) <= p0_way_data_upd11_wayG and p0_wren_q; +p0_way_data_upd11_wayH <= p0_congr_cl11_act_q and binv_wayH_upd3_q; +p1_way_data_upd11_wayH <= p1_congr_cl11_act_q and reload_wayH_upd3_q; +rel_bixu11_wayH_upd(0) <= p1_way_data_upd11_wayH and p1_wren_q; +rel_bixu11_wayH_upd(1) <= p0_way_data_upd11_wayH and p0_wren_q; +p0_congr_cl12_m <= (ex5_congr_cl_q = tconv(12,5)); +p1_congr_cl12_m <= (relu_s_congr_cl_q = tconv(12,5)); +p0_congr_cl12_act_d <= p0_congr_cl12_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl12_act_d <= p1_congr_cl12_m and rel_port_wren_q; +congr_cl12_act <= p0_congr_cl12_act_q or p1_congr_cl12_act_q or congr_cl_all_act_q; +p0_way_data_upd12_wayA <= p0_congr_cl12_act_q and binv_wayA_upd3_q; +p1_way_data_upd12_wayA <= p1_congr_cl12_act_q and reload_wayA_upd3_q; +rel_bixu12_wayA_upd(0) <= p1_way_data_upd12_wayA and p1_wren_q; +rel_bixu12_wayA_upd(1) <= p0_way_data_upd12_wayA and p0_wren_q; +p0_way_data_upd12_wayB <= p0_congr_cl12_act_q and binv_wayB_upd3_q; +p1_way_data_upd12_wayB <= p1_congr_cl12_act_q and reload_wayB_upd3_q; +rel_bixu12_wayB_upd(0) <= p1_way_data_upd12_wayB and p1_wren_q; +rel_bixu12_wayB_upd(1) <= p0_way_data_upd12_wayB and p0_wren_q; +p0_way_data_upd12_wayC <= p0_congr_cl12_act_q and binv_wayC_upd3_q; +p1_way_data_upd12_wayC <= p1_congr_cl12_act_q and reload_wayC_upd3_q; +rel_bixu12_wayC_upd(0) <= p1_way_data_upd12_wayC and p1_wren_q; +rel_bixu12_wayC_upd(1) <= p0_way_data_upd12_wayC and p0_wren_q; +p0_way_data_upd12_wayD <= p0_congr_cl12_act_q and binv_wayD_upd3_q; +p1_way_data_upd12_wayD <= p1_congr_cl12_act_q and reload_wayD_upd3_q; +rel_bixu12_wayD_upd(0) <= p1_way_data_upd12_wayD and p1_wren_q; +rel_bixu12_wayD_upd(1) <= p0_way_data_upd12_wayD and p0_wren_q; +p0_way_data_upd12_wayE <= p0_congr_cl12_act_q and binv_wayE_upd3_q; +p1_way_data_upd12_wayE <= p1_congr_cl12_act_q and reload_wayE_upd3_q; +rel_bixu12_wayE_upd(0) <= p1_way_data_upd12_wayE and p1_wren_q; +rel_bixu12_wayE_upd(1) <= p0_way_data_upd12_wayE and p0_wren_q; +p0_way_data_upd12_wayF <= p0_congr_cl12_act_q and binv_wayF_upd3_q; +p1_way_data_upd12_wayF <= p1_congr_cl12_act_q and reload_wayF_upd3_q; +rel_bixu12_wayF_upd(0) <= p1_way_data_upd12_wayF and p1_wren_q; +rel_bixu12_wayF_upd(1) <= p0_way_data_upd12_wayF and p0_wren_q; +p0_way_data_upd12_wayG <= p0_congr_cl12_act_q and binv_wayG_upd3_q; +p1_way_data_upd12_wayG <= p1_congr_cl12_act_q and reload_wayG_upd3_q; +rel_bixu12_wayG_upd(0) <= p1_way_data_upd12_wayG and p1_wren_q; +rel_bixu12_wayG_upd(1) <= p0_way_data_upd12_wayG and p0_wren_q; +p0_way_data_upd12_wayH <= p0_congr_cl12_act_q and binv_wayH_upd3_q; +p1_way_data_upd12_wayH <= p1_congr_cl12_act_q and reload_wayH_upd3_q; +rel_bixu12_wayH_upd(0) <= p1_way_data_upd12_wayH and p1_wren_q; +rel_bixu12_wayH_upd(1) <= p0_way_data_upd12_wayH and p0_wren_q; +p0_congr_cl13_m <= (ex5_congr_cl_q = tconv(13,5)); +p1_congr_cl13_m <= (relu_s_congr_cl_q = tconv(13,5)); +p0_congr_cl13_act_d <= p0_congr_cl13_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl13_act_d <= p1_congr_cl13_m and rel_port_wren_q; +congr_cl13_act <= p0_congr_cl13_act_q or p1_congr_cl13_act_q or congr_cl_all_act_q; +p0_way_data_upd13_wayA <= p0_congr_cl13_act_q and binv_wayA_upd3_q; +p1_way_data_upd13_wayA <= p1_congr_cl13_act_q and reload_wayA_upd3_q; +rel_bixu13_wayA_upd(0) <= p1_way_data_upd13_wayA and p1_wren_q; +rel_bixu13_wayA_upd(1) <= p0_way_data_upd13_wayA and p0_wren_q; +p0_way_data_upd13_wayB <= p0_congr_cl13_act_q and binv_wayB_upd3_q; +p1_way_data_upd13_wayB <= p1_congr_cl13_act_q and reload_wayB_upd3_q; +rel_bixu13_wayB_upd(0) <= p1_way_data_upd13_wayB and p1_wren_q; +rel_bixu13_wayB_upd(1) <= p0_way_data_upd13_wayB and p0_wren_q; +p0_way_data_upd13_wayC <= p0_congr_cl13_act_q and binv_wayC_upd3_q; +p1_way_data_upd13_wayC <= p1_congr_cl13_act_q and reload_wayC_upd3_q; +rel_bixu13_wayC_upd(0) <= p1_way_data_upd13_wayC and p1_wren_q; +rel_bixu13_wayC_upd(1) <= p0_way_data_upd13_wayC and p0_wren_q; +p0_way_data_upd13_wayD <= p0_congr_cl13_act_q and binv_wayD_upd3_q; +p1_way_data_upd13_wayD <= p1_congr_cl13_act_q and reload_wayD_upd3_q; +rel_bixu13_wayD_upd(0) <= p1_way_data_upd13_wayD and p1_wren_q; +rel_bixu13_wayD_upd(1) <= p0_way_data_upd13_wayD and p0_wren_q; +p0_way_data_upd13_wayE <= p0_congr_cl13_act_q and binv_wayE_upd3_q; +p1_way_data_upd13_wayE <= p1_congr_cl13_act_q and reload_wayE_upd3_q; +rel_bixu13_wayE_upd(0) <= p1_way_data_upd13_wayE and p1_wren_q; +rel_bixu13_wayE_upd(1) <= p0_way_data_upd13_wayE and p0_wren_q; +p0_way_data_upd13_wayF <= p0_congr_cl13_act_q and binv_wayF_upd3_q; +p1_way_data_upd13_wayF <= p1_congr_cl13_act_q and reload_wayF_upd3_q; +rel_bixu13_wayF_upd(0) <= p1_way_data_upd13_wayF and p1_wren_q; +rel_bixu13_wayF_upd(1) <= p0_way_data_upd13_wayF and p0_wren_q; +p0_way_data_upd13_wayG <= p0_congr_cl13_act_q and binv_wayG_upd3_q; +p1_way_data_upd13_wayG <= p1_congr_cl13_act_q and reload_wayG_upd3_q; +rel_bixu13_wayG_upd(0) <= p1_way_data_upd13_wayG and p1_wren_q; +rel_bixu13_wayG_upd(1) <= p0_way_data_upd13_wayG and p0_wren_q; +p0_way_data_upd13_wayH <= p0_congr_cl13_act_q and binv_wayH_upd3_q; +p1_way_data_upd13_wayH <= p1_congr_cl13_act_q and reload_wayH_upd3_q; +rel_bixu13_wayH_upd(0) <= p1_way_data_upd13_wayH and p1_wren_q; +rel_bixu13_wayH_upd(1) <= p0_way_data_upd13_wayH and p0_wren_q; +p0_congr_cl14_m <= (ex5_congr_cl_q = tconv(14,5)); +p1_congr_cl14_m <= (relu_s_congr_cl_q = tconv(14,5)); +p0_congr_cl14_act_d <= p0_congr_cl14_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl14_act_d <= p1_congr_cl14_m and rel_port_wren_q; +congr_cl14_act <= p0_congr_cl14_act_q or p1_congr_cl14_act_q or congr_cl_all_act_q; +p0_way_data_upd14_wayA <= p0_congr_cl14_act_q and binv_wayA_upd3_q; +p1_way_data_upd14_wayA <= p1_congr_cl14_act_q and reload_wayA_upd3_q; +rel_bixu14_wayA_upd(0) <= p1_way_data_upd14_wayA and p1_wren_q; +rel_bixu14_wayA_upd(1) <= p0_way_data_upd14_wayA and p0_wren_q; +p0_way_data_upd14_wayB <= p0_congr_cl14_act_q and binv_wayB_upd3_q; +p1_way_data_upd14_wayB <= p1_congr_cl14_act_q and reload_wayB_upd3_q; +rel_bixu14_wayB_upd(0) <= p1_way_data_upd14_wayB and p1_wren_q; +rel_bixu14_wayB_upd(1) <= p0_way_data_upd14_wayB and p0_wren_q; +p0_way_data_upd14_wayC <= p0_congr_cl14_act_q and binv_wayC_upd3_q; +p1_way_data_upd14_wayC <= p1_congr_cl14_act_q and reload_wayC_upd3_q; +rel_bixu14_wayC_upd(0) <= p1_way_data_upd14_wayC and p1_wren_q; +rel_bixu14_wayC_upd(1) <= p0_way_data_upd14_wayC and p0_wren_q; +p0_way_data_upd14_wayD <= p0_congr_cl14_act_q and binv_wayD_upd3_q; +p1_way_data_upd14_wayD <= p1_congr_cl14_act_q and reload_wayD_upd3_q; +rel_bixu14_wayD_upd(0) <= p1_way_data_upd14_wayD and p1_wren_q; +rel_bixu14_wayD_upd(1) <= p0_way_data_upd14_wayD and p0_wren_q; +p0_way_data_upd14_wayE <= p0_congr_cl14_act_q and binv_wayE_upd3_q; +p1_way_data_upd14_wayE <= p1_congr_cl14_act_q and reload_wayE_upd3_q; +rel_bixu14_wayE_upd(0) <= p1_way_data_upd14_wayE and p1_wren_q; +rel_bixu14_wayE_upd(1) <= p0_way_data_upd14_wayE and p0_wren_q; +p0_way_data_upd14_wayF <= p0_congr_cl14_act_q and binv_wayF_upd3_q; +p1_way_data_upd14_wayF <= p1_congr_cl14_act_q and reload_wayF_upd3_q; +rel_bixu14_wayF_upd(0) <= p1_way_data_upd14_wayF and p1_wren_q; +rel_bixu14_wayF_upd(1) <= p0_way_data_upd14_wayF and p0_wren_q; +p0_way_data_upd14_wayG <= p0_congr_cl14_act_q and binv_wayG_upd3_q; +p1_way_data_upd14_wayG <= p1_congr_cl14_act_q and reload_wayG_upd3_q; +rel_bixu14_wayG_upd(0) <= p1_way_data_upd14_wayG and p1_wren_q; +rel_bixu14_wayG_upd(1) <= p0_way_data_upd14_wayG and p0_wren_q; +p0_way_data_upd14_wayH <= p0_congr_cl14_act_q and binv_wayH_upd3_q; +p1_way_data_upd14_wayH <= p1_congr_cl14_act_q and reload_wayH_upd3_q; +rel_bixu14_wayH_upd(0) <= p1_way_data_upd14_wayH and p1_wren_q; +rel_bixu14_wayH_upd(1) <= p0_way_data_upd14_wayH and p0_wren_q; +p0_congr_cl15_m <= (ex5_congr_cl_q = tconv(15,5)); +p1_congr_cl15_m <= (relu_s_congr_cl_q = tconv(15,5)); +p0_congr_cl15_act_d <= p0_congr_cl15_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl15_act_d <= p1_congr_cl15_m and rel_port_wren_q; +congr_cl15_act <= p0_congr_cl15_act_q or p1_congr_cl15_act_q or congr_cl_all_act_q; +p0_way_data_upd15_wayA <= p0_congr_cl15_act_q and binv_wayA_upd3_q; +p1_way_data_upd15_wayA <= p1_congr_cl15_act_q and reload_wayA_upd3_q; +rel_bixu15_wayA_upd(0) <= p1_way_data_upd15_wayA and p1_wren_q; +rel_bixu15_wayA_upd(1) <= p0_way_data_upd15_wayA and p0_wren_q; +p0_way_data_upd15_wayB <= p0_congr_cl15_act_q and binv_wayB_upd3_q; +p1_way_data_upd15_wayB <= p1_congr_cl15_act_q and reload_wayB_upd3_q; +rel_bixu15_wayB_upd(0) <= p1_way_data_upd15_wayB and p1_wren_q; +rel_bixu15_wayB_upd(1) <= p0_way_data_upd15_wayB and p0_wren_q; +p0_way_data_upd15_wayC <= p0_congr_cl15_act_q and binv_wayC_upd3_q; +p1_way_data_upd15_wayC <= p1_congr_cl15_act_q and reload_wayC_upd3_q; +rel_bixu15_wayC_upd(0) <= p1_way_data_upd15_wayC and p1_wren_q; +rel_bixu15_wayC_upd(1) <= p0_way_data_upd15_wayC and p0_wren_q; +p0_way_data_upd15_wayD <= p0_congr_cl15_act_q and binv_wayD_upd3_q; +p1_way_data_upd15_wayD <= p1_congr_cl15_act_q and reload_wayD_upd3_q; +rel_bixu15_wayD_upd(0) <= p1_way_data_upd15_wayD and p1_wren_q; +rel_bixu15_wayD_upd(1) <= p0_way_data_upd15_wayD and p0_wren_q; +p0_way_data_upd15_wayE <= p0_congr_cl15_act_q and binv_wayE_upd3_q; +p1_way_data_upd15_wayE <= p1_congr_cl15_act_q and reload_wayE_upd3_q; +rel_bixu15_wayE_upd(0) <= p1_way_data_upd15_wayE and p1_wren_q; +rel_bixu15_wayE_upd(1) <= p0_way_data_upd15_wayE and p0_wren_q; +p0_way_data_upd15_wayF <= p0_congr_cl15_act_q and binv_wayF_upd3_q; +p1_way_data_upd15_wayF <= p1_congr_cl15_act_q and reload_wayF_upd3_q; +rel_bixu15_wayF_upd(0) <= p1_way_data_upd15_wayF and p1_wren_q; +rel_bixu15_wayF_upd(1) <= p0_way_data_upd15_wayF and p0_wren_q; +p0_way_data_upd15_wayG <= p0_congr_cl15_act_q and binv_wayG_upd3_q; +p1_way_data_upd15_wayG <= p1_congr_cl15_act_q and reload_wayG_upd3_q; +rel_bixu15_wayG_upd(0) <= p1_way_data_upd15_wayG and p1_wren_q; +rel_bixu15_wayG_upd(1) <= p0_way_data_upd15_wayG and p0_wren_q; +p0_way_data_upd15_wayH <= p0_congr_cl15_act_q and binv_wayH_upd3_q; +p1_way_data_upd15_wayH <= p1_congr_cl15_act_q and reload_wayH_upd3_q; +rel_bixu15_wayH_upd(0) <= p1_way_data_upd15_wayH and p1_wren_q; +rel_bixu15_wayH_upd(1) <= p0_way_data_upd15_wayH and p0_wren_q; +p0_congr_cl16_m <= (ex5_congr_cl_q = tconv(16,5)); +p1_congr_cl16_m <= (relu_s_congr_cl_q = tconv(16,5)); +p0_congr_cl16_act_d <= p0_congr_cl16_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl16_act_d <= p1_congr_cl16_m and rel_port_wren_q; +congr_cl16_act <= p0_congr_cl16_act_q or p1_congr_cl16_act_q or congr_cl_all_act_q; +p0_way_data_upd16_wayA <= p0_congr_cl16_act_q and binv_wayA_upd3_q; +p1_way_data_upd16_wayA <= p1_congr_cl16_act_q and reload_wayA_upd3_q; +rel_bixu16_wayA_upd(0) <= p1_way_data_upd16_wayA and p1_wren_q; +rel_bixu16_wayA_upd(1) <= p0_way_data_upd16_wayA and p0_wren_q; +p0_way_data_upd16_wayB <= p0_congr_cl16_act_q and binv_wayB_upd3_q; +p1_way_data_upd16_wayB <= p1_congr_cl16_act_q and reload_wayB_upd3_q; +rel_bixu16_wayB_upd(0) <= p1_way_data_upd16_wayB and p1_wren_q; +rel_bixu16_wayB_upd(1) <= p0_way_data_upd16_wayB and p0_wren_q; +p0_way_data_upd16_wayC <= p0_congr_cl16_act_q and binv_wayC_upd3_q; +p1_way_data_upd16_wayC <= p1_congr_cl16_act_q and reload_wayC_upd3_q; +rel_bixu16_wayC_upd(0) <= p1_way_data_upd16_wayC and p1_wren_q; +rel_bixu16_wayC_upd(1) <= p0_way_data_upd16_wayC and p0_wren_q; +p0_way_data_upd16_wayD <= p0_congr_cl16_act_q and binv_wayD_upd3_q; +p1_way_data_upd16_wayD <= p1_congr_cl16_act_q and reload_wayD_upd3_q; +rel_bixu16_wayD_upd(0) <= p1_way_data_upd16_wayD and p1_wren_q; +rel_bixu16_wayD_upd(1) <= p0_way_data_upd16_wayD and p0_wren_q; +p0_way_data_upd16_wayE <= p0_congr_cl16_act_q and binv_wayE_upd3_q; +p1_way_data_upd16_wayE <= p1_congr_cl16_act_q and reload_wayE_upd3_q; +rel_bixu16_wayE_upd(0) <= p1_way_data_upd16_wayE and p1_wren_q; +rel_bixu16_wayE_upd(1) <= p0_way_data_upd16_wayE and p0_wren_q; +p0_way_data_upd16_wayF <= p0_congr_cl16_act_q and binv_wayF_upd3_q; +p1_way_data_upd16_wayF <= p1_congr_cl16_act_q and reload_wayF_upd3_q; +rel_bixu16_wayF_upd(0) <= p1_way_data_upd16_wayF and p1_wren_q; +rel_bixu16_wayF_upd(1) <= p0_way_data_upd16_wayF and p0_wren_q; +p0_way_data_upd16_wayG <= p0_congr_cl16_act_q and binv_wayG_upd3_q; +p1_way_data_upd16_wayG <= p1_congr_cl16_act_q and reload_wayG_upd3_q; +rel_bixu16_wayG_upd(0) <= p1_way_data_upd16_wayG and p1_wren_q; +rel_bixu16_wayG_upd(1) <= p0_way_data_upd16_wayG and p0_wren_q; +p0_way_data_upd16_wayH <= p0_congr_cl16_act_q and binv_wayH_upd3_q; +p1_way_data_upd16_wayH <= p1_congr_cl16_act_q and reload_wayH_upd3_q; +rel_bixu16_wayH_upd(0) <= p1_way_data_upd16_wayH and p1_wren_q; +rel_bixu16_wayH_upd(1) <= p0_way_data_upd16_wayH and p0_wren_q; +p0_congr_cl17_m <= (ex5_congr_cl_q = tconv(17,5)); +p1_congr_cl17_m <= (relu_s_congr_cl_q = tconv(17,5)); +p0_congr_cl17_act_d <= p0_congr_cl17_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl17_act_d <= p1_congr_cl17_m and rel_port_wren_q; +congr_cl17_act <= p0_congr_cl17_act_q or p1_congr_cl17_act_q or congr_cl_all_act_q; +p0_way_data_upd17_wayA <= p0_congr_cl17_act_q and binv_wayA_upd3_q; +p1_way_data_upd17_wayA <= p1_congr_cl17_act_q and reload_wayA_upd3_q; +rel_bixu17_wayA_upd(0) <= p1_way_data_upd17_wayA and p1_wren_q; +rel_bixu17_wayA_upd(1) <= p0_way_data_upd17_wayA and p0_wren_q; +p0_way_data_upd17_wayB <= p0_congr_cl17_act_q and binv_wayB_upd3_q; +p1_way_data_upd17_wayB <= p1_congr_cl17_act_q and reload_wayB_upd3_q; +rel_bixu17_wayB_upd(0) <= p1_way_data_upd17_wayB and p1_wren_q; +rel_bixu17_wayB_upd(1) <= p0_way_data_upd17_wayB and p0_wren_q; +p0_way_data_upd17_wayC <= p0_congr_cl17_act_q and binv_wayC_upd3_q; +p1_way_data_upd17_wayC <= p1_congr_cl17_act_q and reload_wayC_upd3_q; +rel_bixu17_wayC_upd(0) <= p1_way_data_upd17_wayC and p1_wren_q; +rel_bixu17_wayC_upd(1) <= p0_way_data_upd17_wayC and p0_wren_q; +p0_way_data_upd17_wayD <= p0_congr_cl17_act_q and binv_wayD_upd3_q; +p1_way_data_upd17_wayD <= p1_congr_cl17_act_q and reload_wayD_upd3_q; +rel_bixu17_wayD_upd(0) <= p1_way_data_upd17_wayD and p1_wren_q; +rel_bixu17_wayD_upd(1) <= p0_way_data_upd17_wayD and p0_wren_q; +p0_way_data_upd17_wayE <= p0_congr_cl17_act_q and binv_wayE_upd3_q; +p1_way_data_upd17_wayE <= p1_congr_cl17_act_q and reload_wayE_upd3_q; +rel_bixu17_wayE_upd(0) <= p1_way_data_upd17_wayE and p1_wren_q; +rel_bixu17_wayE_upd(1) <= p0_way_data_upd17_wayE and p0_wren_q; +p0_way_data_upd17_wayF <= p0_congr_cl17_act_q and binv_wayF_upd3_q; +p1_way_data_upd17_wayF <= p1_congr_cl17_act_q and reload_wayF_upd3_q; +rel_bixu17_wayF_upd(0) <= p1_way_data_upd17_wayF and p1_wren_q; +rel_bixu17_wayF_upd(1) <= p0_way_data_upd17_wayF and p0_wren_q; +p0_way_data_upd17_wayG <= p0_congr_cl17_act_q and binv_wayG_upd3_q; +p1_way_data_upd17_wayG <= p1_congr_cl17_act_q and reload_wayG_upd3_q; +rel_bixu17_wayG_upd(0) <= p1_way_data_upd17_wayG and p1_wren_q; +rel_bixu17_wayG_upd(1) <= p0_way_data_upd17_wayG and p0_wren_q; +p0_way_data_upd17_wayH <= p0_congr_cl17_act_q and binv_wayH_upd3_q; +p1_way_data_upd17_wayH <= p1_congr_cl17_act_q and reload_wayH_upd3_q; +rel_bixu17_wayH_upd(0) <= p1_way_data_upd17_wayH and p1_wren_q; +rel_bixu17_wayH_upd(1) <= p0_way_data_upd17_wayH and p0_wren_q; +p0_congr_cl18_m <= (ex5_congr_cl_q = tconv(18,5)); +p1_congr_cl18_m <= (relu_s_congr_cl_q = tconv(18,5)); +p0_congr_cl18_act_d <= p0_congr_cl18_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl18_act_d <= p1_congr_cl18_m and rel_port_wren_q; +congr_cl18_act <= p0_congr_cl18_act_q or p1_congr_cl18_act_q or congr_cl_all_act_q; +p0_way_data_upd18_wayA <= p0_congr_cl18_act_q and binv_wayA_upd3_q; +p1_way_data_upd18_wayA <= p1_congr_cl18_act_q and reload_wayA_upd3_q; +rel_bixu18_wayA_upd(0) <= p1_way_data_upd18_wayA and p1_wren_q; +rel_bixu18_wayA_upd(1) <= p0_way_data_upd18_wayA and p0_wren_q; +p0_way_data_upd18_wayB <= p0_congr_cl18_act_q and binv_wayB_upd3_q; +p1_way_data_upd18_wayB <= p1_congr_cl18_act_q and reload_wayB_upd3_q; +rel_bixu18_wayB_upd(0) <= p1_way_data_upd18_wayB and p1_wren_q; +rel_bixu18_wayB_upd(1) <= p0_way_data_upd18_wayB and p0_wren_q; +p0_way_data_upd18_wayC <= p0_congr_cl18_act_q and binv_wayC_upd3_q; +p1_way_data_upd18_wayC <= p1_congr_cl18_act_q and reload_wayC_upd3_q; +rel_bixu18_wayC_upd(0) <= p1_way_data_upd18_wayC and p1_wren_q; +rel_bixu18_wayC_upd(1) <= p0_way_data_upd18_wayC and p0_wren_q; +p0_way_data_upd18_wayD <= p0_congr_cl18_act_q and binv_wayD_upd3_q; +p1_way_data_upd18_wayD <= p1_congr_cl18_act_q and reload_wayD_upd3_q; +rel_bixu18_wayD_upd(0) <= p1_way_data_upd18_wayD and p1_wren_q; +rel_bixu18_wayD_upd(1) <= p0_way_data_upd18_wayD and p0_wren_q; +p0_way_data_upd18_wayE <= p0_congr_cl18_act_q and binv_wayE_upd3_q; +p1_way_data_upd18_wayE <= p1_congr_cl18_act_q and reload_wayE_upd3_q; +rel_bixu18_wayE_upd(0) <= p1_way_data_upd18_wayE and p1_wren_q; +rel_bixu18_wayE_upd(1) <= p0_way_data_upd18_wayE and p0_wren_q; +p0_way_data_upd18_wayF <= p0_congr_cl18_act_q and binv_wayF_upd3_q; +p1_way_data_upd18_wayF <= p1_congr_cl18_act_q and reload_wayF_upd3_q; +rel_bixu18_wayF_upd(0) <= p1_way_data_upd18_wayF and p1_wren_q; +rel_bixu18_wayF_upd(1) <= p0_way_data_upd18_wayF and p0_wren_q; +p0_way_data_upd18_wayG <= p0_congr_cl18_act_q and binv_wayG_upd3_q; +p1_way_data_upd18_wayG <= p1_congr_cl18_act_q and reload_wayG_upd3_q; +rel_bixu18_wayG_upd(0) <= p1_way_data_upd18_wayG and p1_wren_q; +rel_bixu18_wayG_upd(1) <= p0_way_data_upd18_wayG and p0_wren_q; +p0_way_data_upd18_wayH <= p0_congr_cl18_act_q and binv_wayH_upd3_q; +p1_way_data_upd18_wayH <= p1_congr_cl18_act_q and reload_wayH_upd3_q; +rel_bixu18_wayH_upd(0) <= p1_way_data_upd18_wayH and p1_wren_q; +rel_bixu18_wayH_upd(1) <= p0_way_data_upd18_wayH and p0_wren_q; +p0_congr_cl19_m <= (ex5_congr_cl_q = tconv(19,5)); +p1_congr_cl19_m <= (relu_s_congr_cl_q = tconv(19,5)); +p0_congr_cl19_act_d <= p0_congr_cl19_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl19_act_d <= p1_congr_cl19_m and rel_port_wren_q; +congr_cl19_act <= p0_congr_cl19_act_q or p1_congr_cl19_act_q or congr_cl_all_act_q; +p0_way_data_upd19_wayA <= p0_congr_cl19_act_q and binv_wayA_upd3_q; +p1_way_data_upd19_wayA <= p1_congr_cl19_act_q and reload_wayA_upd3_q; +rel_bixu19_wayA_upd(0) <= p1_way_data_upd19_wayA and p1_wren_q; +rel_bixu19_wayA_upd(1) <= p0_way_data_upd19_wayA and p0_wren_q; +p0_way_data_upd19_wayB <= p0_congr_cl19_act_q and binv_wayB_upd3_q; +p1_way_data_upd19_wayB <= p1_congr_cl19_act_q and reload_wayB_upd3_q; +rel_bixu19_wayB_upd(0) <= p1_way_data_upd19_wayB and p1_wren_q; +rel_bixu19_wayB_upd(1) <= p0_way_data_upd19_wayB and p0_wren_q; +p0_way_data_upd19_wayC <= p0_congr_cl19_act_q and binv_wayC_upd3_q; +p1_way_data_upd19_wayC <= p1_congr_cl19_act_q and reload_wayC_upd3_q; +rel_bixu19_wayC_upd(0) <= p1_way_data_upd19_wayC and p1_wren_q; +rel_bixu19_wayC_upd(1) <= p0_way_data_upd19_wayC and p0_wren_q; +p0_way_data_upd19_wayD <= p0_congr_cl19_act_q and binv_wayD_upd3_q; +p1_way_data_upd19_wayD <= p1_congr_cl19_act_q and reload_wayD_upd3_q; +rel_bixu19_wayD_upd(0) <= p1_way_data_upd19_wayD and p1_wren_q; +rel_bixu19_wayD_upd(1) <= p0_way_data_upd19_wayD and p0_wren_q; +p0_way_data_upd19_wayE <= p0_congr_cl19_act_q and binv_wayE_upd3_q; +p1_way_data_upd19_wayE <= p1_congr_cl19_act_q and reload_wayE_upd3_q; +rel_bixu19_wayE_upd(0) <= p1_way_data_upd19_wayE and p1_wren_q; +rel_bixu19_wayE_upd(1) <= p0_way_data_upd19_wayE and p0_wren_q; +p0_way_data_upd19_wayF <= p0_congr_cl19_act_q and binv_wayF_upd3_q; +p1_way_data_upd19_wayF <= p1_congr_cl19_act_q and reload_wayF_upd3_q; +rel_bixu19_wayF_upd(0) <= p1_way_data_upd19_wayF and p1_wren_q; +rel_bixu19_wayF_upd(1) <= p0_way_data_upd19_wayF and p0_wren_q; +p0_way_data_upd19_wayG <= p0_congr_cl19_act_q and binv_wayG_upd3_q; +p1_way_data_upd19_wayG <= p1_congr_cl19_act_q and reload_wayG_upd3_q; +rel_bixu19_wayG_upd(0) <= p1_way_data_upd19_wayG and p1_wren_q; +rel_bixu19_wayG_upd(1) <= p0_way_data_upd19_wayG and p0_wren_q; +p0_way_data_upd19_wayH <= p0_congr_cl19_act_q and binv_wayH_upd3_q; +p1_way_data_upd19_wayH <= p1_congr_cl19_act_q and reload_wayH_upd3_q; +rel_bixu19_wayH_upd(0) <= p1_way_data_upd19_wayH and p1_wren_q; +rel_bixu19_wayH_upd(1) <= p0_way_data_upd19_wayH and p0_wren_q; +p0_congr_cl20_m <= (ex5_congr_cl_q = tconv(20,5)); +p1_congr_cl20_m <= (relu_s_congr_cl_q = tconv(20,5)); +p0_congr_cl20_act_d <= p0_congr_cl20_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl20_act_d <= p1_congr_cl20_m and rel_port_wren_q; +congr_cl20_act <= p0_congr_cl20_act_q or p1_congr_cl20_act_q or congr_cl_all_act_q; +p0_way_data_upd20_wayA <= p0_congr_cl20_act_q and binv_wayA_upd3_q; +p1_way_data_upd20_wayA <= p1_congr_cl20_act_q and reload_wayA_upd3_q; +rel_bixu20_wayA_upd(0) <= p1_way_data_upd20_wayA and p1_wren_q; +rel_bixu20_wayA_upd(1) <= p0_way_data_upd20_wayA and p0_wren_q; +p0_way_data_upd20_wayB <= p0_congr_cl20_act_q and binv_wayB_upd3_q; +p1_way_data_upd20_wayB <= p1_congr_cl20_act_q and reload_wayB_upd3_q; +rel_bixu20_wayB_upd(0) <= p1_way_data_upd20_wayB and p1_wren_q; +rel_bixu20_wayB_upd(1) <= p0_way_data_upd20_wayB and p0_wren_q; +p0_way_data_upd20_wayC <= p0_congr_cl20_act_q and binv_wayC_upd3_q; +p1_way_data_upd20_wayC <= p1_congr_cl20_act_q and reload_wayC_upd3_q; +rel_bixu20_wayC_upd(0) <= p1_way_data_upd20_wayC and p1_wren_q; +rel_bixu20_wayC_upd(1) <= p0_way_data_upd20_wayC and p0_wren_q; +p0_way_data_upd20_wayD <= p0_congr_cl20_act_q and binv_wayD_upd3_q; +p1_way_data_upd20_wayD <= p1_congr_cl20_act_q and reload_wayD_upd3_q; +rel_bixu20_wayD_upd(0) <= p1_way_data_upd20_wayD and p1_wren_q; +rel_bixu20_wayD_upd(1) <= p0_way_data_upd20_wayD and p0_wren_q; +p0_way_data_upd20_wayE <= p0_congr_cl20_act_q and binv_wayE_upd3_q; +p1_way_data_upd20_wayE <= p1_congr_cl20_act_q and reload_wayE_upd3_q; +rel_bixu20_wayE_upd(0) <= p1_way_data_upd20_wayE and p1_wren_q; +rel_bixu20_wayE_upd(1) <= p0_way_data_upd20_wayE and p0_wren_q; +p0_way_data_upd20_wayF <= p0_congr_cl20_act_q and binv_wayF_upd3_q; +p1_way_data_upd20_wayF <= p1_congr_cl20_act_q and reload_wayF_upd3_q; +rel_bixu20_wayF_upd(0) <= p1_way_data_upd20_wayF and p1_wren_q; +rel_bixu20_wayF_upd(1) <= p0_way_data_upd20_wayF and p0_wren_q; +p0_way_data_upd20_wayG <= p0_congr_cl20_act_q and binv_wayG_upd3_q; +p1_way_data_upd20_wayG <= p1_congr_cl20_act_q and reload_wayG_upd3_q; +rel_bixu20_wayG_upd(0) <= p1_way_data_upd20_wayG and p1_wren_q; +rel_bixu20_wayG_upd(1) <= p0_way_data_upd20_wayG and p0_wren_q; +p0_way_data_upd20_wayH <= p0_congr_cl20_act_q and binv_wayH_upd3_q; +p1_way_data_upd20_wayH <= p1_congr_cl20_act_q and reload_wayH_upd3_q; +rel_bixu20_wayH_upd(0) <= p1_way_data_upd20_wayH and p1_wren_q; +rel_bixu20_wayH_upd(1) <= p0_way_data_upd20_wayH and p0_wren_q; +p0_congr_cl21_m <= (ex5_congr_cl_q = tconv(21,5)); +p1_congr_cl21_m <= (relu_s_congr_cl_q = tconv(21,5)); +p0_congr_cl21_act_d <= p0_congr_cl21_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl21_act_d <= p1_congr_cl21_m and rel_port_wren_q; +congr_cl21_act <= p0_congr_cl21_act_q or p1_congr_cl21_act_q or congr_cl_all_act_q; +p0_way_data_upd21_wayA <= p0_congr_cl21_act_q and binv_wayA_upd3_q; +p1_way_data_upd21_wayA <= p1_congr_cl21_act_q and reload_wayA_upd3_q; +rel_bixu21_wayA_upd(0) <= p1_way_data_upd21_wayA and p1_wren_q; +rel_bixu21_wayA_upd(1) <= p0_way_data_upd21_wayA and p0_wren_q; +p0_way_data_upd21_wayB <= p0_congr_cl21_act_q and binv_wayB_upd3_q; +p1_way_data_upd21_wayB <= p1_congr_cl21_act_q and reload_wayB_upd3_q; +rel_bixu21_wayB_upd(0) <= p1_way_data_upd21_wayB and p1_wren_q; +rel_bixu21_wayB_upd(1) <= p0_way_data_upd21_wayB and p0_wren_q; +p0_way_data_upd21_wayC <= p0_congr_cl21_act_q and binv_wayC_upd3_q; +p1_way_data_upd21_wayC <= p1_congr_cl21_act_q and reload_wayC_upd3_q; +rel_bixu21_wayC_upd(0) <= p1_way_data_upd21_wayC and p1_wren_q; +rel_bixu21_wayC_upd(1) <= p0_way_data_upd21_wayC and p0_wren_q; +p0_way_data_upd21_wayD <= p0_congr_cl21_act_q and binv_wayD_upd3_q; +p1_way_data_upd21_wayD <= p1_congr_cl21_act_q and reload_wayD_upd3_q; +rel_bixu21_wayD_upd(0) <= p1_way_data_upd21_wayD and p1_wren_q; +rel_bixu21_wayD_upd(1) <= p0_way_data_upd21_wayD and p0_wren_q; +p0_way_data_upd21_wayE <= p0_congr_cl21_act_q and binv_wayE_upd3_q; +p1_way_data_upd21_wayE <= p1_congr_cl21_act_q and reload_wayE_upd3_q; +rel_bixu21_wayE_upd(0) <= p1_way_data_upd21_wayE and p1_wren_q; +rel_bixu21_wayE_upd(1) <= p0_way_data_upd21_wayE and p0_wren_q; +p0_way_data_upd21_wayF <= p0_congr_cl21_act_q and binv_wayF_upd3_q; +p1_way_data_upd21_wayF <= p1_congr_cl21_act_q and reload_wayF_upd3_q; +rel_bixu21_wayF_upd(0) <= p1_way_data_upd21_wayF and p1_wren_q; +rel_bixu21_wayF_upd(1) <= p0_way_data_upd21_wayF and p0_wren_q; +p0_way_data_upd21_wayG <= p0_congr_cl21_act_q and binv_wayG_upd3_q; +p1_way_data_upd21_wayG <= p1_congr_cl21_act_q and reload_wayG_upd3_q; +rel_bixu21_wayG_upd(0) <= p1_way_data_upd21_wayG and p1_wren_q; +rel_bixu21_wayG_upd(1) <= p0_way_data_upd21_wayG and p0_wren_q; +p0_way_data_upd21_wayH <= p0_congr_cl21_act_q and binv_wayH_upd3_q; +p1_way_data_upd21_wayH <= p1_congr_cl21_act_q and reload_wayH_upd3_q; +rel_bixu21_wayH_upd(0) <= p1_way_data_upd21_wayH and p1_wren_q; +rel_bixu21_wayH_upd(1) <= p0_way_data_upd21_wayH and p0_wren_q; +p0_congr_cl22_m <= (ex5_congr_cl_q = tconv(22,5)); +p1_congr_cl22_m <= (relu_s_congr_cl_q = tconv(22,5)); +p0_congr_cl22_act_d <= p0_congr_cl22_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl22_act_d <= p1_congr_cl22_m and rel_port_wren_q; +congr_cl22_act <= p0_congr_cl22_act_q or p1_congr_cl22_act_q or congr_cl_all_act_q; +p0_way_data_upd22_wayA <= p0_congr_cl22_act_q and binv_wayA_upd3_q; +p1_way_data_upd22_wayA <= p1_congr_cl22_act_q and reload_wayA_upd3_q; +rel_bixu22_wayA_upd(0) <= p1_way_data_upd22_wayA and p1_wren_q; +rel_bixu22_wayA_upd(1) <= p0_way_data_upd22_wayA and p0_wren_q; +p0_way_data_upd22_wayB <= p0_congr_cl22_act_q and binv_wayB_upd3_q; +p1_way_data_upd22_wayB <= p1_congr_cl22_act_q and reload_wayB_upd3_q; +rel_bixu22_wayB_upd(0) <= p1_way_data_upd22_wayB and p1_wren_q; +rel_bixu22_wayB_upd(1) <= p0_way_data_upd22_wayB and p0_wren_q; +p0_way_data_upd22_wayC <= p0_congr_cl22_act_q and binv_wayC_upd3_q; +p1_way_data_upd22_wayC <= p1_congr_cl22_act_q and reload_wayC_upd3_q; +rel_bixu22_wayC_upd(0) <= p1_way_data_upd22_wayC and p1_wren_q; +rel_bixu22_wayC_upd(1) <= p0_way_data_upd22_wayC and p0_wren_q; +p0_way_data_upd22_wayD <= p0_congr_cl22_act_q and binv_wayD_upd3_q; +p1_way_data_upd22_wayD <= p1_congr_cl22_act_q and reload_wayD_upd3_q; +rel_bixu22_wayD_upd(0) <= p1_way_data_upd22_wayD and p1_wren_q; +rel_bixu22_wayD_upd(1) <= p0_way_data_upd22_wayD and p0_wren_q; +p0_way_data_upd22_wayE <= p0_congr_cl22_act_q and binv_wayE_upd3_q; +p1_way_data_upd22_wayE <= p1_congr_cl22_act_q and reload_wayE_upd3_q; +rel_bixu22_wayE_upd(0) <= p1_way_data_upd22_wayE and p1_wren_q; +rel_bixu22_wayE_upd(1) <= p0_way_data_upd22_wayE and p0_wren_q; +p0_way_data_upd22_wayF <= p0_congr_cl22_act_q and binv_wayF_upd3_q; +p1_way_data_upd22_wayF <= p1_congr_cl22_act_q and reload_wayF_upd3_q; +rel_bixu22_wayF_upd(0) <= p1_way_data_upd22_wayF and p1_wren_q; +rel_bixu22_wayF_upd(1) <= p0_way_data_upd22_wayF and p0_wren_q; +p0_way_data_upd22_wayG <= p0_congr_cl22_act_q and binv_wayG_upd3_q; +p1_way_data_upd22_wayG <= p1_congr_cl22_act_q and reload_wayG_upd3_q; +rel_bixu22_wayG_upd(0) <= p1_way_data_upd22_wayG and p1_wren_q; +rel_bixu22_wayG_upd(1) <= p0_way_data_upd22_wayG and p0_wren_q; +p0_way_data_upd22_wayH <= p0_congr_cl22_act_q and binv_wayH_upd3_q; +p1_way_data_upd22_wayH <= p1_congr_cl22_act_q and reload_wayH_upd3_q; +rel_bixu22_wayH_upd(0) <= p1_way_data_upd22_wayH and p1_wren_q; +rel_bixu22_wayH_upd(1) <= p0_way_data_upd22_wayH and p0_wren_q; +p0_congr_cl23_m <= (ex5_congr_cl_q = tconv(23,5)); +p1_congr_cl23_m <= (relu_s_congr_cl_q = tconv(23,5)); +p0_congr_cl23_act_d <= p0_congr_cl23_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl23_act_d <= p1_congr_cl23_m and rel_port_wren_q; +congr_cl23_act <= p0_congr_cl23_act_q or p1_congr_cl23_act_q or congr_cl_all_act_q; +p0_way_data_upd23_wayA <= p0_congr_cl23_act_q and binv_wayA_upd3_q; +p1_way_data_upd23_wayA <= p1_congr_cl23_act_q and reload_wayA_upd3_q; +rel_bixu23_wayA_upd(0) <= p1_way_data_upd23_wayA and p1_wren_q; +rel_bixu23_wayA_upd(1) <= p0_way_data_upd23_wayA and p0_wren_q; +p0_way_data_upd23_wayB <= p0_congr_cl23_act_q and binv_wayB_upd3_q; +p1_way_data_upd23_wayB <= p1_congr_cl23_act_q and reload_wayB_upd3_q; +rel_bixu23_wayB_upd(0) <= p1_way_data_upd23_wayB and p1_wren_q; +rel_bixu23_wayB_upd(1) <= p0_way_data_upd23_wayB and p0_wren_q; +p0_way_data_upd23_wayC <= p0_congr_cl23_act_q and binv_wayC_upd3_q; +p1_way_data_upd23_wayC <= p1_congr_cl23_act_q and reload_wayC_upd3_q; +rel_bixu23_wayC_upd(0) <= p1_way_data_upd23_wayC and p1_wren_q; +rel_bixu23_wayC_upd(1) <= p0_way_data_upd23_wayC and p0_wren_q; +p0_way_data_upd23_wayD <= p0_congr_cl23_act_q and binv_wayD_upd3_q; +p1_way_data_upd23_wayD <= p1_congr_cl23_act_q and reload_wayD_upd3_q; +rel_bixu23_wayD_upd(0) <= p1_way_data_upd23_wayD and p1_wren_q; +rel_bixu23_wayD_upd(1) <= p0_way_data_upd23_wayD and p0_wren_q; +p0_way_data_upd23_wayE <= p0_congr_cl23_act_q and binv_wayE_upd3_q; +p1_way_data_upd23_wayE <= p1_congr_cl23_act_q and reload_wayE_upd3_q; +rel_bixu23_wayE_upd(0) <= p1_way_data_upd23_wayE and p1_wren_q; +rel_bixu23_wayE_upd(1) <= p0_way_data_upd23_wayE and p0_wren_q; +p0_way_data_upd23_wayF <= p0_congr_cl23_act_q and binv_wayF_upd3_q; +p1_way_data_upd23_wayF <= p1_congr_cl23_act_q and reload_wayF_upd3_q; +rel_bixu23_wayF_upd(0) <= p1_way_data_upd23_wayF and p1_wren_q; +rel_bixu23_wayF_upd(1) <= p0_way_data_upd23_wayF and p0_wren_q; +p0_way_data_upd23_wayG <= p0_congr_cl23_act_q and binv_wayG_upd3_q; +p1_way_data_upd23_wayG <= p1_congr_cl23_act_q and reload_wayG_upd3_q; +rel_bixu23_wayG_upd(0) <= p1_way_data_upd23_wayG and p1_wren_q; +rel_bixu23_wayG_upd(1) <= p0_way_data_upd23_wayG and p0_wren_q; +p0_way_data_upd23_wayH <= p0_congr_cl23_act_q and binv_wayH_upd3_q; +p1_way_data_upd23_wayH <= p1_congr_cl23_act_q and reload_wayH_upd3_q; +rel_bixu23_wayH_upd(0) <= p1_way_data_upd23_wayH and p1_wren_q; +rel_bixu23_wayH_upd(1) <= p0_way_data_upd23_wayH and p0_wren_q; +p0_congr_cl24_m <= (ex5_congr_cl_q = tconv(24,5)); +p1_congr_cl24_m <= (relu_s_congr_cl_q = tconv(24,5)); +p0_congr_cl24_act_d <= p0_congr_cl24_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl24_act_d <= p1_congr_cl24_m and rel_port_wren_q; +congr_cl24_act <= p0_congr_cl24_act_q or p1_congr_cl24_act_q or congr_cl_all_act_q; +p0_way_data_upd24_wayA <= p0_congr_cl24_act_q and binv_wayA_upd3_q; +p1_way_data_upd24_wayA <= p1_congr_cl24_act_q and reload_wayA_upd3_q; +rel_bixu24_wayA_upd(0) <= p1_way_data_upd24_wayA and p1_wren_q; +rel_bixu24_wayA_upd(1) <= p0_way_data_upd24_wayA and p0_wren_q; +p0_way_data_upd24_wayB <= p0_congr_cl24_act_q and binv_wayB_upd3_q; +p1_way_data_upd24_wayB <= p1_congr_cl24_act_q and reload_wayB_upd3_q; +rel_bixu24_wayB_upd(0) <= p1_way_data_upd24_wayB and p1_wren_q; +rel_bixu24_wayB_upd(1) <= p0_way_data_upd24_wayB and p0_wren_q; +p0_way_data_upd24_wayC <= p0_congr_cl24_act_q and binv_wayC_upd3_q; +p1_way_data_upd24_wayC <= p1_congr_cl24_act_q and reload_wayC_upd3_q; +rel_bixu24_wayC_upd(0) <= p1_way_data_upd24_wayC and p1_wren_q; +rel_bixu24_wayC_upd(1) <= p0_way_data_upd24_wayC and p0_wren_q; +p0_way_data_upd24_wayD <= p0_congr_cl24_act_q and binv_wayD_upd3_q; +p1_way_data_upd24_wayD <= p1_congr_cl24_act_q and reload_wayD_upd3_q; +rel_bixu24_wayD_upd(0) <= p1_way_data_upd24_wayD and p1_wren_q; +rel_bixu24_wayD_upd(1) <= p0_way_data_upd24_wayD and p0_wren_q; +p0_way_data_upd24_wayE <= p0_congr_cl24_act_q and binv_wayE_upd3_q; +p1_way_data_upd24_wayE <= p1_congr_cl24_act_q and reload_wayE_upd3_q; +rel_bixu24_wayE_upd(0) <= p1_way_data_upd24_wayE and p1_wren_q; +rel_bixu24_wayE_upd(1) <= p0_way_data_upd24_wayE and p0_wren_q; +p0_way_data_upd24_wayF <= p0_congr_cl24_act_q and binv_wayF_upd3_q; +p1_way_data_upd24_wayF <= p1_congr_cl24_act_q and reload_wayF_upd3_q; +rel_bixu24_wayF_upd(0) <= p1_way_data_upd24_wayF and p1_wren_q; +rel_bixu24_wayF_upd(1) <= p0_way_data_upd24_wayF and p0_wren_q; +p0_way_data_upd24_wayG <= p0_congr_cl24_act_q and binv_wayG_upd3_q; +p1_way_data_upd24_wayG <= p1_congr_cl24_act_q and reload_wayG_upd3_q; +rel_bixu24_wayG_upd(0) <= p1_way_data_upd24_wayG and p1_wren_q; +rel_bixu24_wayG_upd(1) <= p0_way_data_upd24_wayG and p0_wren_q; +p0_way_data_upd24_wayH <= p0_congr_cl24_act_q and binv_wayH_upd3_q; +p1_way_data_upd24_wayH <= p1_congr_cl24_act_q and reload_wayH_upd3_q; +rel_bixu24_wayH_upd(0) <= p1_way_data_upd24_wayH and p1_wren_q; +rel_bixu24_wayH_upd(1) <= p0_way_data_upd24_wayH and p0_wren_q; +p0_congr_cl25_m <= (ex5_congr_cl_q = tconv(25,5)); +p1_congr_cl25_m <= (relu_s_congr_cl_q = tconv(25,5)); +p0_congr_cl25_act_d <= p0_congr_cl25_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl25_act_d <= p1_congr_cl25_m and rel_port_wren_q; +congr_cl25_act <= p0_congr_cl25_act_q or p1_congr_cl25_act_q or congr_cl_all_act_q; +p0_way_data_upd25_wayA <= p0_congr_cl25_act_q and binv_wayA_upd3_q; +p1_way_data_upd25_wayA <= p1_congr_cl25_act_q and reload_wayA_upd3_q; +rel_bixu25_wayA_upd(0) <= p1_way_data_upd25_wayA and p1_wren_q; +rel_bixu25_wayA_upd(1) <= p0_way_data_upd25_wayA and p0_wren_q; +p0_way_data_upd25_wayB <= p0_congr_cl25_act_q and binv_wayB_upd3_q; +p1_way_data_upd25_wayB <= p1_congr_cl25_act_q and reload_wayB_upd3_q; +rel_bixu25_wayB_upd(0) <= p1_way_data_upd25_wayB and p1_wren_q; +rel_bixu25_wayB_upd(1) <= p0_way_data_upd25_wayB and p0_wren_q; +p0_way_data_upd25_wayC <= p0_congr_cl25_act_q and binv_wayC_upd3_q; +p1_way_data_upd25_wayC <= p1_congr_cl25_act_q and reload_wayC_upd3_q; +rel_bixu25_wayC_upd(0) <= p1_way_data_upd25_wayC and p1_wren_q; +rel_bixu25_wayC_upd(1) <= p0_way_data_upd25_wayC and p0_wren_q; +p0_way_data_upd25_wayD <= p0_congr_cl25_act_q and binv_wayD_upd3_q; +p1_way_data_upd25_wayD <= p1_congr_cl25_act_q and reload_wayD_upd3_q; +rel_bixu25_wayD_upd(0) <= p1_way_data_upd25_wayD and p1_wren_q; +rel_bixu25_wayD_upd(1) <= p0_way_data_upd25_wayD and p0_wren_q; +p0_way_data_upd25_wayE <= p0_congr_cl25_act_q and binv_wayE_upd3_q; +p1_way_data_upd25_wayE <= p1_congr_cl25_act_q and reload_wayE_upd3_q; +rel_bixu25_wayE_upd(0) <= p1_way_data_upd25_wayE and p1_wren_q; +rel_bixu25_wayE_upd(1) <= p0_way_data_upd25_wayE and p0_wren_q; +p0_way_data_upd25_wayF <= p0_congr_cl25_act_q and binv_wayF_upd3_q; +p1_way_data_upd25_wayF <= p1_congr_cl25_act_q and reload_wayF_upd3_q; +rel_bixu25_wayF_upd(0) <= p1_way_data_upd25_wayF and p1_wren_q; +rel_bixu25_wayF_upd(1) <= p0_way_data_upd25_wayF and p0_wren_q; +p0_way_data_upd25_wayG <= p0_congr_cl25_act_q and binv_wayG_upd3_q; +p1_way_data_upd25_wayG <= p1_congr_cl25_act_q and reload_wayG_upd3_q; +rel_bixu25_wayG_upd(0) <= p1_way_data_upd25_wayG and p1_wren_q; +rel_bixu25_wayG_upd(1) <= p0_way_data_upd25_wayG and p0_wren_q; +p0_way_data_upd25_wayH <= p0_congr_cl25_act_q and binv_wayH_upd3_q; +p1_way_data_upd25_wayH <= p1_congr_cl25_act_q and reload_wayH_upd3_q; +rel_bixu25_wayH_upd(0) <= p1_way_data_upd25_wayH and p1_wren_q; +rel_bixu25_wayH_upd(1) <= p0_way_data_upd25_wayH and p0_wren_q; +p0_congr_cl26_m <= (ex5_congr_cl_q = tconv(26,5)); +p1_congr_cl26_m <= (relu_s_congr_cl_q = tconv(26,5)); +p0_congr_cl26_act_d <= p0_congr_cl26_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl26_act_d <= p1_congr_cl26_m and rel_port_wren_q; +congr_cl26_act <= p0_congr_cl26_act_q or p1_congr_cl26_act_q or congr_cl_all_act_q; +p0_way_data_upd26_wayA <= p0_congr_cl26_act_q and binv_wayA_upd3_q; +p1_way_data_upd26_wayA <= p1_congr_cl26_act_q and reload_wayA_upd3_q; +rel_bixu26_wayA_upd(0) <= p1_way_data_upd26_wayA and p1_wren_q; +rel_bixu26_wayA_upd(1) <= p0_way_data_upd26_wayA and p0_wren_q; +p0_way_data_upd26_wayB <= p0_congr_cl26_act_q and binv_wayB_upd3_q; +p1_way_data_upd26_wayB <= p1_congr_cl26_act_q and reload_wayB_upd3_q; +rel_bixu26_wayB_upd(0) <= p1_way_data_upd26_wayB and p1_wren_q; +rel_bixu26_wayB_upd(1) <= p0_way_data_upd26_wayB and p0_wren_q; +p0_way_data_upd26_wayC <= p0_congr_cl26_act_q and binv_wayC_upd3_q; +p1_way_data_upd26_wayC <= p1_congr_cl26_act_q and reload_wayC_upd3_q; +rel_bixu26_wayC_upd(0) <= p1_way_data_upd26_wayC and p1_wren_q; +rel_bixu26_wayC_upd(1) <= p0_way_data_upd26_wayC and p0_wren_q; +p0_way_data_upd26_wayD <= p0_congr_cl26_act_q and binv_wayD_upd3_q; +p1_way_data_upd26_wayD <= p1_congr_cl26_act_q and reload_wayD_upd3_q; +rel_bixu26_wayD_upd(0) <= p1_way_data_upd26_wayD and p1_wren_q; +rel_bixu26_wayD_upd(1) <= p0_way_data_upd26_wayD and p0_wren_q; +p0_way_data_upd26_wayE <= p0_congr_cl26_act_q and binv_wayE_upd3_q; +p1_way_data_upd26_wayE <= p1_congr_cl26_act_q and reload_wayE_upd3_q; +rel_bixu26_wayE_upd(0) <= p1_way_data_upd26_wayE and p1_wren_q; +rel_bixu26_wayE_upd(1) <= p0_way_data_upd26_wayE and p0_wren_q; +p0_way_data_upd26_wayF <= p0_congr_cl26_act_q and binv_wayF_upd3_q; +p1_way_data_upd26_wayF <= p1_congr_cl26_act_q and reload_wayF_upd3_q; +rel_bixu26_wayF_upd(0) <= p1_way_data_upd26_wayF and p1_wren_q; +rel_bixu26_wayF_upd(1) <= p0_way_data_upd26_wayF and p0_wren_q; +p0_way_data_upd26_wayG <= p0_congr_cl26_act_q and binv_wayG_upd3_q; +p1_way_data_upd26_wayG <= p1_congr_cl26_act_q and reload_wayG_upd3_q; +rel_bixu26_wayG_upd(0) <= p1_way_data_upd26_wayG and p1_wren_q; +rel_bixu26_wayG_upd(1) <= p0_way_data_upd26_wayG and p0_wren_q; +p0_way_data_upd26_wayH <= p0_congr_cl26_act_q and binv_wayH_upd3_q; +p1_way_data_upd26_wayH <= p1_congr_cl26_act_q and reload_wayH_upd3_q; +rel_bixu26_wayH_upd(0) <= p1_way_data_upd26_wayH and p1_wren_q; +rel_bixu26_wayH_upd(1) <= p0_way_data_upd26_wayH and p0_wren_q; +p0_congr_cl27_m <= (ex5_congr_cl_q = tconv(27,5)); +p1_congr_cl27_m <= (relu_s_congr_cl_q = tconv(27,5)); +p0_congr_cl27_act_d <= p0_congr_cl27_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl27_act_d <= p1_congr_cl27_m and rel_port_wren_q; +congr_cl27_act <= p0_congr_cl27_act_q or p1_congr_cl27_act_q or congr_cl_all_act_q; +p0_way_data_upd27_wayA <= p0_congr_cl27_act_q and binv_wayA_upd3_q; +p1_way_data_upd27_wayA <= p1_congr_cl27_act_q and reload_wayA_upd3_q; +rel_bixu27_wayA_upd(0) <= p1_way_data_upd27_wayA and p1_wren_q; +rel_bixu27_wayA_upd(1) <= p0_way_data_upd27_wayA and p0_wren_q; +p0_way_data_upd27_wayB <= p0_congr_cl27_act_q and binv_wayB_upd3_q; +p1_way_data_upd27_wayB <= p1_congr_cl27_act_q and reload_wayB_upd3_q; +rel_bixu27_wayB_upd(0) <= p1_way_data_upd27_wayB and p1_wren_q; +rel_bixu27_wayB_upd(1) <= p0_way_data_upd27_wayB and p0_wren_q; +p0_way_data_upd27_wayC <= p0_congr_cl27_act_q and binv_wayC_upd3_q; +p1_way_data_upd27_wayC <= p1_congr_cl27_act_q and reload_wayC_upd3_q; +rel_bixu27_wayC_upd(0) <= p1_way_data_upd27_wayC and p1_wren_q; +rel_bixu27_wayC_upd(1) <= p0_way_data_upd27_wayC and p0_wren_q; +p0_way_data_upd27_wayD <= p0_congr_cl27_act_q and binv_wayD_upd3_q; +p1_way_data_upd27_wayD <= p1_congr_cl27_act_q and reload_wayD_upd3_q; +rel_bixu27_wayD_upd(0) <= p1_way_data_upd27_wayD and p1_wren_q; +rel_bixu27_wayD_upd(1) <= p0_way_data_upd27_wayD and p0_wren_q; +p0_way_data_upd27_wayE <= p0_congr_cl27_act_q and binv_wayE_upd3_q; +p1_way_data_upd27_wayE <= p1_congr_cl27_act_q and reload_wayE_upd3_q; +rel_bixu27_wayE_upd(0) <= p1_way_data_upd27_wayE and p1_wren_q; +rel_bixu27_wayE_upd(1) <= p0_way_data_upd27_wayE and p0_wren_q; +p0_way_data_upd27_wayF <= p0_congr_cl27_act_q and binv_wayF_upd3_q; +p1_way_data_upd27_wayF <= p1_congr_cl27_act_q and reload_wayF_upd3_q; +rel_bixu27_wayF_upd(0) <= p1_way_data_upd27_wayF and p1_wren_q; +rel_bixu27_wayF_upd(1) <= p0_way_data_upd27_wayF and p0_wren_q; +p0_way_data_upd27_wayG <= p0_congr_cl27_act_q and binv_wayG_upd3_q; +p1_way_data_upd27_wayG <= p1_congr_cl27_act_q and reload_wayG_upd3_q; +rel_bixu27_wayG_upd(0) <= p1_way_data_upd27_wayG and p1_wren_q; +rel_bixu27_wayG_upd(1) <= p0_way_data_upd27_wayG and p0_wren_q; +p0_way_data_upd27_wayH <= p0_congr_cl27_act_q and binv_wayH_upd3_q; +p1_way_data_upd27_wayH <= p1_congr_cl27_act_q and reload_wayH_upd3_q; +rel_bixu27_wayH_upd(0) <= p1_way_data_upd27_wayH and p1_wren_q; +rel_bixu27_wayH_upd(1) <= p0_way_data_upd27_wayH and p0_wren_q; +p0_congr_cl28_m <= (ex5_congr_cl_q = tconv(28,5)); +p1_congr_cl28_m <= (relu_s_congr_cl_q = tconv(28,5)); +p0_congr_cl28_act_d <= p0_congr_cl28_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl28_act_d <= p1_congr_cl28_m and rel_port_wren_q; +congr_cl28_act <= p0_congr_cl28_act_q or p1_congr_cl28_act_q or congr_cl_all_act_q; +p0_way_data_upd28_wayA <= p0_congr_cl28_act_q and binv_wayA_upd3_q; +p1_way_data_upd28_wayA <= p1_congr_cl28_act_q and reload_wayA_upd3_q; +rel_bixu28_wayA_upd(0) <= p1_way_data_upd28_wayA and p1_wren_q; +rel_bixu28_wayA_upd(1) <= p0_way_data_upd28_wayA and p0_wren_q; +p0_way_data_upd28_wayB <= p0_congr_cl28_act_q and binv_wayB_upd3_q; +p1_way_data_upd28_wayB <= p1_congr_cl28_act_q and reload_wayB_upd3_q; +rel_bixu28_wayB_upd(0) <= p1_way_data_upd28_wayB and p1_wren_q; +rel_bixu28_wayB_upd(1) <= p0_way_data_upd28_wayB and p0_wren_q; +p0_way_data_upd28_wayC <= p0_congr_cl28_act_q and binv_wayC_upd3_q; +p1_way_data_upd28_wayC <= p1_congr_cl28_act_q and reload_wayC_upd3_q; +rel_bixu28_wayC_upd(0) <= p1_way_data_upd28_wayC and p1_wren_q; +rel_bixu28_wayC_upd(1) <= p0_way_data_upd28_wayC and p0_wren_q; +p0_way_data_upd28_wayD <= p0_congr_cl28_act_q and binv_wayD_upd3_q; +p1_way_data_upd28_wayD <= p1_congr_cl28_act_q and reload_wayD_upd3_q; +rel_bixu28_wayD_upd(0) <= p1_way_data_upd28_wayD and p1_wren_q; +rel_bixu28_wayD_upd(1) <= p0_way_data_upd28_wayD and p0_wren_q; +p0_way_data_upd28_wayE <= p0_congr_cl28_act_q and binv_wayE_upd3_q; +p1_way_data_upd28_wayE <= p1_congr_cl28_act_q and reload_wayE_upd3_q; +rel_bixu28_wayE_upd(0) <= p1_way_data_upd28_wayE and p1_wren_q; +rel_bixu28_wayE_upd(1) <= p0_way_data_upd28_wayE and p0_wren_q; +p0_way_data_upd28_wayF <= p0_congr_cl28_act_q and binv_wayF_upd3_q; +p1_way_data_upd28_wayF <= p1_congr_cl28_act_q and reload_wayF_upd3_q; +rel_bixu28_wayF_upd(0) <= p1_way_data_upd28_wayF and p1_wren_q; +rel_bixu28_wayF_upd(1) <= p0_way_data_upd28_wayF and p0_wren_q; +p0_way_data_upd28_wayG <= p0_congr_cl28_act_q and binv_wayG_upd3_q; +p1_way_data_upd28_wayG <= p1_congr_cl28_act_q and reload_wayG_upd3_q; +rel_bixu28_wayG_upd(0) <= p1_way_data_upd28_wayG and p1_wren_q; +rel_bixu28_wayG_upd(1) <= p0_way_data_upd28_wayG and p0_wren_q; +p0_way_data_upd28_wayH <= p0_congr_cl28_act_q and binv_wayH_upd3_q; +p1_way_data_upd28_wayH <= p1_congr_cl28_act_q and reload_wayH_upd3_q; +rel_bixu28_wayH_upd(0) <= p1_way_data_upd28_wayH and p1_wren_q; +rel_bixu28_wayH_upd(1) <= p0_way_data_upd28_wayH and p0_wren_q; +p0_congr_cl29_m <= (ex5_congr_cl_q = tconv(29,5)); +p1_congr_cl29_m <= (relu_s_congr_cl_q = tconv(29,5)); +p0_congr_cl29_act_d <= p0_congr_cl29_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl29_act_d <= p1_congr_cl29_m and rel_port_wren_q; +congr_cl29_act <= p0_congr_cl29_act_q or p1_congr_cl29_act_q or congr_cl_all_act_q; +p0_way_data_upd29_wayA <= p0_congr_cl29_act_q and binv_wayA_upd3_q; +p1_way_data_upd29_wayA <= p1_congr_cl29_act_q and reload_wayA_upd3_q; +rel_bixu29_wayA_upd(0) <= p1_way_data_upd29_wayA and p1_wren_q; +rel_bixu29_wayA_upd(1) <= p0_way_data_upd29_wayA and p0_wren_q; +p0_way_data_upd29_wayB <= p0_congr_cl29_act_q and binv_wayB_upd3_q; +p1_way_data_upd29_wayB <= p1_congr_cl29_act_q and reload_wayB_upd3_q; +rel_bixu29_wayB_upd(0) <= p1_way_data_upd29_wayB and p1_wren_q; +rel_bixu29_wayB_upd(1) <= p0_way_data_upd29_wayB and p0_wren_q; +p0_way_data_upd29_wayC <= p0_congr_cl29_act_q and binv_wayC_upd3_q; +p1_way_data_upd29_wayC <= p1_congr_cl29_act_q and reload_wayC_upd3_q; +rel_bixu29_wayC_upd(0) <= p1_way_data_upd29_wayC and p1_wren_q; +rel_bixu29_wayC_upd(1) <= p0_way_data_upd29_wayC and p0_wren_q; +p0_way_data_upd29_wayD <= p0_congr_cl29_act_q and binv_wayD_upd3_q; +p1_way_data_upd29_wayD <= p1_congr_cl29_act_q and reload_wayD_upd3_q; +rel_bixu29_wayD_upd(0) <= p1_way_data_upd29_wayD and p1_wren_q; +rel_bixu29_wayD_upd(1) <= p0_way_data_upd29_wayD and p0_wren_q; +p0_way_data_upd29_wayE <= p0_congr_cl29_act_q and binv_wayE_upd3_q; +p1_way_data_upd29_wayE <= p1_congr_cl29_act_q and reload_wayE_upd3_q; +rel_bixu29_wayE_upd(0) <= p1_way_data_upd29_wayE and p1_wren_q; +rel_bixu29_wayE_upd(1) <= p0_way_data_upd29_wayE and p0_wren_q; +p0_way_data_upd29_wayF <= p0_congr_cl29_act_q and binv_wayF_upd3_q; +p1_way_data_upd29_wayF <= p1_congr_cl29_act_q and reload_wayF_upd3_q; +rel_bixu29_wayF_upd(0) <= p1_way_data_upd29_wayF and p1_wren_q; +rel_bixu29_wayF_upd(1) <= p0_way_data_upd29_wayF and p0_wren_q; +p0_way_data_upd29_wayG <= p0_congr_cl29_act_q and binv_wayG_upd3_q; +p1_way_data_upd29_wayG <= p1_congr_cl29_act_q and reload_wayG_upd3_q; +rel_bixu29_wayG_upd(0) <= p1_way_data_upd29_wayG and p1_wren_q; +rel_bixu29_wayG_upd(1) <= p0_way_data_upd29_wayG and p0_wren_q; +p0_way_data_upd29_wayH <= p0_congr_cl29_act_q and binv_wayH_upd3_q; +p1_way_data_upd29_wayH <= p1_congr_cl29_act_q and reload_wayH_upd3_q; +rel_bixu29_wayH_upd(0) <= p1_way_data_upd29_wayH and p1_wren_q; +rel_bixu29_wayH_upd(1) <= p0_way_data_upd29_wayH and p0_wren_q; +p0_congr_cl30_m <= (ex5_congr_cl_q = tconv(30,5)); +p1_congr_cl30_m <= (relu_s_congr_cl_q = tconv(30,5)); +p0_congr_cl30_act_d <= p0_congr_cl30_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl30_act_d <= p1_congr_cl30_m and rel_port_wren_q; +congr_cl30_act <= p0_congr_cl30_act_q or p1_congr_cl30_act_q or congr_cl_all_act_q; +p0_way_data_upd30_wayA <= p0_congr_cl30_act_q and binv_wayA_upd3_q; +p1_way_data_upd30_wayA <= p1_congr_cl30_act_q and reload_wayA_upd3_q; +rel_bixu30_wayA_upd(0) <= p1_way_data_upd30_wayA and p1_wren_q; +rel_bixu30_wayA_upd(1) <= p0_way_data_upd30_wayA and p0_wren_q; +p0_way_data_upd30_wayB <= p0_congr_cl30_act_q and binv_wayB_upd3_q; +p1_way_data_upd30_wayB <= p1_congr_cl30_act_q and reload_wayB_upd3_q; +rel_bixu30_wayB_upd(0) <= p1_way_data_upd30_wayB and p1_wren_q; +rel_bixu30_wayB_upd(1) <= p0_way_data_upd30_wayB and p0_wren_q; +p0_way_data_upd30_wayC <= p0_congr_cl30_act_q and binv_wayC_upd3_q; +p1_way_data_upd30_wayC <= p1_congr_cl30_act_q and reload_wayC_upd3_q; +rel_bixu30_wayC_upd(0) <= p1_way_data_upd30_wayC and p1_wren_q; +rel_bixu30_wayC_upd(1) <= p0_way_data_upd30_wayC and p0_wren_q; +p0_way_data_upd30_wayD <= p0_congr_cl30_act_q and binv_wayD_upd3_q; +p1_way_data_upd30_wayD <= p1_congr_cl30_act_q and reload_wayD_upd3_q; +rel_bixu30_wayD_upd(0) <= p1_way_data_upd30_wayD and p1_wren_q; +rel_bixu30_wayD_upd(1) <= p0_way_data_upd30_wayD and p0_wren_q; +p0_way_data_upd30_wayE <= p0_congr_cl30_act_q and binv_wayE_upd3_q; +p1_way_data_upd30_wayE <= p1_congr_cl30_act_q and reload_wayE_upd3_q; +rel_bixu30_wayE_upd(0) <= p1_way_data_upd30_wayE and p1_wren_q; +rel_bixu30_wayE_upd(1) <= p0_way_data_upd30_wayE and p0_wren_q; +p0_way_data_upd30_wayF <= p0_congr_cl30_act_q and binv_wayF_upd3_q; +p1_way_data_upd30_wayF <= p1_congr_cl30_act_q and reload_wayF_upd3_q; +rel_bixu30_wayF_upd(0) <= p1_way_data_upd30_wayF and p1_wren_q; +rel_bixu30_wayF_upd(1) <= p0_way_data_upd30_wayF and p0_wren_q; +p0_way_data_upd30_wayG <= p0_congr_cl30_act_q and binv_wayG_upd3_q; +p1_way_data_upd30_wayG <= p1_congr_cl30_act_q and reload_wayG_upd3_q; +rel_bixu30_wayG_upd(0) <= p1_way_data_upd30_wayG and p1_wren_q; +rel_bixu30_wayG_upd(1) <= p0_way_data_upd30_wayG and p0_wren_q; +p0_way_data_upd30_wayH <= p0_congr_cl30_act_q and binv_wayH_upd3_q; +p1_way_data_upd30_wayH <= p1_congr_cl30_act_q and reload_wayH_upd3_q; +rel_bixu30_wayH_upd(0) <= p1_way_data_upd30_wayH and p1_wren_q; +rel_bixu30_wayH_upd(1) <= p0_way_data_upd30_wayH and p0_wren_q; +p0_congr_cl31_m <= (ex5_congr_cl_q = tconv(31,5)); +p1_congr_cl31_m <= (relu_s_congr_cl_q = tconv(31,5)); +p0_congr_cl31_act_d <= p0_congr_cl31_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl31_act_d <= p1_congr_cl31_m and rel_port_wren_q; +congr_cl31_act <= p0_congr_cl31_act_q or p1_congr_cl31_act_q or congr_cl_all_act_q; +p0_way_data_upd31_wayA <= p0_congr_cl31_act_q and binv_wayA_upd3_q; +p1_way_data_upd31_wayA <= p1_congr_cl31_act_q and reload_wayA_upd3_q; +rel_bixu31_wayA_upd(0) <= p1_way_data_upd31_wayA and p1_wren_q; +rel_bixu31_wayA_upd(1) <= p0_way_data_upd31_wayA and p0_wren_q; +p0_way_data_upd31_wayB <= p0_congr_cl31_act_q and binv_wayB_upd3_q; +p1_way_data_upd31_wayB <= p1_congr_cl31_act_q and reload_wayB_upd3_q; +rel_bixu31_wayB_upd(0) <= p1_way_data_upd31_wayB and p1_wren_q; +rel_bixu31_wayB_upd(1) <= p0_way_data_upd31_wayB and p0_wren_q; +p0_way_data_upd31_wayC <= p0_congr_cl31_act_q and binv_wayC_upd3_q; +p1_way_data_upd31_wayC <= p1_congr_cl31_act_q and reload_wayC_upd3_q; +rel_bixu31_wayC_upd(0) <= p1_way_data_upd31_wayC and p1_wren_q; +rel_bixu31_wayC_upd(1) <= p0_way_data_upd31_wayC and p0_wren_q; +p0_way_data_upd31_wayD <= p0_congr_cl31_act_q and binv_wayD_upd3_q; +p1_way_data_upd31_wayD <= p1_congr_cl31_act_q and reload_wayD_upd3_q; +rel_bixu31_wayD_upd(0) <= p1_way_data_upd31_wayD and p1_wren_q; +rel_bixu31_wayD_upd(1) <= p0_way_data_upd31_wayD and p0_wren_q; +p0_way_data_upd31_wayE <= p0_congr_cl31_act_q and binv_wayE_upd3_q; +p1_way_data_upd31_wayE <= p1_congr_cl31_act_q and reload_wayE_upd3_q; +rel_bixu31_wayE_upd(0) <= p1_way_data_upd31_wayE and p1_wren_q; +rel_bixu31_wayE_upd(1) <= p0_way_data_upd31_wayE and p0_wren_q; +p0_way_data_upd31_wayF <= p0_congr_cl31_act_q and binv_wayF_upd3_q; +p1_way_data_upd31_wayF <= p1_congr_cl31_act_q and reload_wayF_upd3_q; +rel_bixu31_wayF_upd(0) <= p1_way_data_upd31_wayF and p1_wren_q; +rel_bixu31_wayF_upd(1) <= p0_way_data_upd31_wayF and p0_wren_q; +p0_way_data_upd31_wayG <= p0_congr_cl31_act_q and binv_wayG_upd3_q; +p1_way_data_upd31_wayG <= p1_congr_cl31_act_q and reload_wayG_upd3_q; +rel_bixu31_wayG_upd(0) <= p1_way_data_upd31_wayG and p1_wren_q; +rel_bixu31_wayG_upd(1) <= p0_way_data_upd31_wayG and p0_wren_q; +p0_way_data_upd31_wayH <= p0_congr_cl31_act_q and binv_wayH_upd3_q; +p1_way_data_upd31_wayH <= p1_congr_cl31_act_q and reload_wayH_upd3_q; +rel_bixu31_wayH_upd(0) <= p1_way_data_upd31_wayH and p1_wren_q; +rel_bixu31_wayH_upd(1) <= p0_way_data_upd31_wayH and p0_wren_q; +with rel_bixu0_wayA_upd select + congr_cl0_wA_d(0) <= (congr_cl0_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu0_wayA_upd select + congr_cl0_wA_d(1) <= (congr_cl0_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu0_wayA_upd select + congr_cl0_wA_d(2) <= (congr_cl0_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu0_wayA_upd select + congr_cl0_wA_d(3) <= (congr_cl0_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu0_wayA_upd select + congr_cl0_wA_d(4) <= (congr_cl0_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu0_wayA_upd select + congr_cl0_wA_d(5) <= (congr_cl0_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu1_wayA_upd select + congr_cl1_wA_d(0) <= (congr_cl1_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu1_wayA_upd select + congr_cl1_wA_d(1) <= (congr_cl1_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu1_wayA_upd select + congr_cl1_wA_d(2) <= (congr_cl1_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu1_wayA_upd select + congr_cl1_wA_d(3) <= (congr_cl1_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu1_wayA_upd select + congr_cl1_wA_d(4) <= (congr_cl1_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu1_wayA_upd select + congr_cl1_wA_d(5) <= (congr_cl1_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu2_wayA_upd select + congr_cl2_wA_d(0) <= (congr_cl2_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu2_wayA_upd select + congr_cl2_wA_d(1) <= (congr_cl2_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu2_wayA_upd select + congr_cl2_wA_d(2) <= (congr_cl2_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu2_wayA_upd select + congr_cl2_wA_d(3) <= (congr_cl2_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu2_wayA_upd select + congr_cl2_wA_d(4) <= (congr_cl2_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu2_wayA_upd select + congr_cl2_wA_d(5) <= (congr_cl2_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu3_wayA_upd select + congr_cl3_wA_d(0) <= (congr_cl3_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu3_wayA_upd select + congr_cl3_wA_d(1) <= (congr_cl3_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu3_wayA_upd select + congr_cl3_wA_d(2) <= (congr_cl3_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu3_wayA_upd select + congr_cl3_wA_d(3) <= (congr_cl3_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu3_wayA_upd select + congr_cl3_wA_d(4) <= (congr_cl3_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu3_wayA_upd select + congr_cl3_wA_d(5) <= (congr_cl3_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu4_wayA_upd select + congr_cl4_wA_d(0) <= (congr_cl4_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu4_wayA_upd select + congr_cl4_wA_d(1) <= (congr_cl4_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu4_wayA_upd select + congr_cl4_wA_d(2) <= (congr_cl4_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu4_wayA_upd select + congr_cl4_wA_d(3) <= (congr_cl4_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu4_wayA_upd select + congr_cl4_wA_d(4) <= (congr_cl4_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu4_wayA_upd select + congr_cl4_wA_d(5) <= (congr_cl4_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu5_wayA_upd select + congr_cl5_wA_d(0) <= (congr_cl5_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu5_wayA_upd select + congr_cl5_wA_d(1) <= (congr_cl5_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu5_wayA_upd select + congr_cl5_wA_d(2) <= (congr_cl5_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu5_wayA_upd select + congr_cl5_wA_d(3) <= (congr_cl5_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu5_wayA_upd select + congr_cl5_wA_d(4) <= (congr_cl5_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu5_wayA_upd select + congr_cl5_wA_d(5) <= (congr_cl5_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu6_wayA_upd select + congr_cl6_wA_d(0) <= (congr_cl6_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu6_wayA_upd select + congr_cl6_wA_d(1) <= (congr_cl6_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu6_wayA_upd select + congr_cl6_wA_d(2) <= (congr_cl6_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu6_wayA_upd select + congr_cl6_wA_d(3) <= (congr_cl6_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu6_wayA_upd select + congr_cl6_wA_d(4) <= (congr_cl6_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu6_wayA_upd select + congr_cl6_wA_d(5) <= (congr_cl6_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu7_wayA_upd select + congr_cl7_wA_d(0) <= (congr_cl7_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu7_wayA_upd select + congr_cl7_wA_d(1) <= (congr_cl7_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu7_wayA_upd select + congr_cl7_wA_d(2) <= (congr_cl7_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu7_wayA_upd select + congr_cl7_wA_d(3) <= (congr_cl7_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu7_wayA_upd select + congr_cl7_wA_d(4) <= (congr_cl7_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu7_wayA_upd select + congr_cl7_wA_d(5) <= (congr_cl7_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu8_wayA_upd select + congr_cl8_wA_d(0) <= (congr_cl8_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu8_wayA_upd select + congr_cl8_wA_d(1) <= (congr_cl8_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu8_wayA_upd select + congr_cl8_wA_d(2) <= (congr_cl8_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu8_wayA_upd select + congr_cl8_wA_d(3) <= (congr_cl8_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu8_wayA_upd select + congr_cl8_wA_d(4) <= (congr_cl8_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu8_wayA_upd select + congr_cl8_wA_d(5) <= (congr_cl8_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu9_wayA_upd select + congr_cl9_wA_d(0) <= (congr_cl9_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu9_wayA_upd select + congr_cl9_wA_d(1) <= (congr_cl9_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu9_wayA_upd select + congr_cl9_wA_d(2) <= (congr_cl9_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu9_wayA_upd select + congr_cl9_wA_d(3) <= (congr_cl9_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu9_wayA_upd select + congr_cl9_wA_d(4) <= (congr_cl9_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu9_wayA_upd select + congr_cl9_wA_d(5) <= (congr_cl9_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu10_wayA_upd select + congr_cl10_wA_d(0) <= (congr_cl10_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu10_wayA_upd select + congr_cl10_wA_d(1) <= (congr_cl10_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu10_wayA_upd select + congr_cl10_wA_d(2) <= (congr_cl10_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu10_wayA_upd select + congr_cl10_wA_d(3) <= (congr_cl10_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu10_wayA_upd select + congr_cl10_wA_d(4) <= (congr_cl10_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu10_wayA_upd select + congr_cl10_wA_d(5) <= (congr_cl10_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu11_wayA_upd select + congr_cl11_wA_d(0) <= (congr_cl11_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu11_wayA_upd select + congr_cl11_wA_d(1) <= (congr_cl11_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu11_wayA_upd select + congr_cl11_wA_d(2) <= (congr_cl11_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu11_wayA_upd select + congr_cl11_wA_d(3) <= (congr_cl11_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu11_wayA_upd select + congr_cl11_wA_d(4) <= (congr_cl11_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu11_wayA_upd select + congr_cl11_wA_d(5) <= (congr_cl11_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu12_wayA_upd select + congr_cl12_wA_d(0) <= (congr_cl12_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu12_wayA_upd select + congr_cl12_wA_d(1) <= (congr_cl12_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu12_wayA_upd select + congr_cl12_wA_d(2) <= (congr_cl12_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu12_wayA_upd select + congr_cl12_wA_d(3) <= (congr_cl12_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu12_wayA_upd select + congr_cl12_wA_d(4) <= (congr_cl12_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu12_wayA_upd select + congr_cl12_wA_d(5) <= (congr_cl12_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu13_wayA_upd select + congr_cl13_wA_d(0) <= (congr_cl13_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu13_wayA_upd select + congr_cl13_wA_d(1) <= (congr_cl13_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu13_wayA_upd select + congr_cl13_wA_d(2) <= (congr_cl13_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu13_wayA_upd select + congr_cl13_wA_d(3) <= (congr_cl13_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu13_wayA_upd select + congr_cl13_wA_d(4) <= (congr_cl13_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu13_wayA_upd select + congr_cl13_wA_d(5) <= (congr_cl13_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu14_wayA_upd select + congr_cl14_wA_d(0) <= (congr_cl14_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu14_wayA_upd select + congr_cl14_wA_d(1) <= (congr_cl14_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu14_wayA_upd select + congr_cl14_wA_d(2) <= (congr_cl14_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu14_wayA_upd select + congr_cl14_wA_d(3) <= (congr_cl14_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu14_wayA_upd select + congr_cl14_wA_d(4) <= (congr_cl14_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu14_wayA_upd select + congr_cl14_wA_d(5) <= (congr_cl14_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu15_wayA_upd select + congr_cl15_wA_d(0) <= (congr_cl15_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu15_wayA_upd select + congr_cl15_wA_d(1) <= (congr_cl15_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu15_wayA_upd select + congr_cl15_wA_d(2) <= (congr_cl15_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu15_wayA_upd select + congr_cl15_wA_d(3) <= (congr_cl15_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu15_wayA_upd select + congr_cl15_wA_d(4) <= (congr_cl15_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu15_wayA_upd select + congr_cl15_wA_d(5) <= (congr_cl15_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu16_wayA_upd select + congr_cl16_wA_d(0) <= (congr_cl16_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu16_wayA_upd select + congr_cl16_wA_d(1) <= (congr_cl16_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu16_wayA_upd select + congr_cl16_wA_d(2) <= (congr_cl16_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu16_wayA_upd select + congr_cl16_wA_d(3) <= (congr_cl16_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu16_wayA_upd select + congr_cl16_wA_d(4) <= (congr_cl16_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu16_wayA_upd select + congr_cl16_wA_d(5) <= (congr_cl16_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu17_wayA_upd select + congr_cl17_wA_d(0) <= (congr_cl17_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu17_wayA_upd select + congr_cl17_wA_d(1) <= (congr_cl17_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu17_wayA_upd select + congr_cl17_wA_d(2) <= (congr_cl17_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu17_wayA_upd select + congr_cl17_wA_d(3) <= (congr_cl17_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu17_wayA_upd select + congr_cl17_wA_d(4) <= (congr_cl17_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu17_wayA_upd select + congr_cl17_wA_d(5) <= (congr_cl17_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu18_wayA_upd select + congr_cl18_wA_d(0) <= (congr_cl18_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu18_wayA_upd select + congr_cl18_wA_d(1) <= (congr_cl18_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu18_wayA_upd select + congr_cl18_wA_d(2) <= (congr_cl18_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu18_wayA_upd select + congr_cl18_wA_d(3) <= (congr_cl18_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu18_wayA_upd select + congr_cl18_wA_d(4) <= (congr_cl18_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu18_wayA_upd select + congr_cl18_wA_d(5) <= (congr_cl18_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu19_wayA_upd select + congr_cl19_wA_d(0) <= (congr_cl19_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu19_wayA_upd select + congr_cl19_wA_d(1) <= (congr_cl19_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu19_wayA_upd select + congr_cl19_wA_d(2) <= (congr_cl19_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu19_wayA_upd select + congr_cl19_wA_d(3) <= (congr_cl19_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu19_wayA_upd select + congr_cl19_wA_d(4) <= (congr_cl19_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu19_wayA_upd select + congr_cl19_wA_d(5) <= (congr_cl19_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu20_wayA_upd select + congr_cl20_wA_d(0) <= (congr_cl20_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu20_wayA_upd select + congr_cl20_wA_d(1) <= (congr_cl20_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu20_wayA_upd select + congr_cl20_wA_d(2) <= (congr_cl20_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu20_wayA_upd select + congr_cl20_wA_d(3) <= (congr_cl20_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu20_wayA_upd select + congr_cl20_wA_d(4) <= (congr_cl20_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu20_wayA_upd select + congr_cl20_wA_d(5) <= (congr_cl20_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu21_wayA_upd select + congr_cl21_wA_d(0) <= (congr_cl21_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu21_wayA_upd select + congr_cl21_wA_d(1) <= (congr_cl21_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu21_wayA_upd select + congr_cl21_wA_d(2) <= (congr_cl21_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu21_wayA_upd select + congr_cl21_wA_d(3) <= (congr_cl21_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu21_wayA_upd select + congr_cl21_wA_d(4) <= (congr_cl21_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu21_wayA_upd select + congr_cl21_wA_d(5) <= (congr_cl21_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu22_wayA_upd select + congr_cl22_wA_d(0) <= (congr_cl22_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu22_wayA_upd select + congr_cl22_wA_d(1) <= (congr_cl22_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu22_wayA_upd select + congr_cl22_wA_d(2) <= (congr_cl22_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu22_wayA_upd select + congr_cl22_wA_d(3) <= (congr_cl22_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu22_wayA_upd select + congr_cl22_wA_d(4) <= (congr_cl22_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu22_wayA_upd select + congr_cl22_wA_d(5) <= (congr_cl22_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu23_wayA_upd select + congr_cl23_wA_d(0) <= (congr_cl23_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu23_wayA_upd select + congr_cl23_wA_d(1) <= (congr_cl23_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu23_wayA_upd select + congr_cl23_wA_d(2) <= (congr_cl23_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu23_wayA_upd select + congr_cl23_wA_d(3) <= (congr_cl23_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu23_wayA_upd select + congr_cl23_wA_d(4) <= (congr_cl23_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu23_wayA_upd select + congr_cl23_wA_d(5) <= (congr_cl23_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu24_wayA_upd select + congr_cl24_wA_d(0) <= (congr_cl24_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu24_wayA_upd select + congr_cl24_wA_d(1) <= (congr_cl24_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu24_wayA_upd select + congr_cl24_wA_d(2) <= (congr_cl24_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu24_wayA_upd select + congr_cl24_wA_d(3) <= (congr_cl24_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu24_wayA_upd select + congr_cl24_wA_d(4) <= (congr_cl24_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu24_wayA_upd select + congr_cl24_wA_d(5) <= (congr_cl24_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu25_wayA_upd select + congr_cl25_wA_d(0) <= (congr_cl25_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu25_wayA_upd select + congr_cl25_wA_d(1) <= (congr_cl25_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu25_wayA_upd select + congr_cl25_wA_d(2) <= (congr_cl25_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu25_wayA_upd select + congr_cl25_wA_d(3) <= (congr_cl25_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu25_wayA_upd select + congr_cl25_wA_d(4) <= (congr_cl25_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu25_wayA_upd select + congr_cl25_wA_d(5) <= (congr_cl25_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu26_wayA_upd select + congr_cl26_wA_d(0) <= (congr_cl26_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu26_wayA_upd select + congr_cl26_wA_d(1) <= (congr_cl26_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu26_wayA_upd select + congr_cl26_wA_d(2) <= (congr_cl26_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu26_wayA_upd select + congr_cl26_wA_d(3) <= (congr_cl26_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu26_wayA_upd select + congr_cl26_wA_d(4) <= (congr_cl26_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu26_wayA_upd select + congr_cl26_wA_d(5) <= (congr_cl26_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu27_wayA_upd select + congr_cl27_wA_d(0) <= (congr_cl27_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu27_wayA_upd select + congr_cl27_wA_d(1) <= (congr_cl27_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu27_wayA_upd select + congr_cl27_wA_d(2) <= (congr_cl27_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu27_wayA_upd select + congr_cl27_wA_d(3) <= (congr_cl27_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu27_wayA_upd select + congr_cl27_wA_d(4) <= (congr_cl27_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu27_wayA_upd select + congr_cl27_wA_d(5) <= (congr_cl27_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu28_wayA_upd select + congr_cl28_wA_d(0) <= (congr_cl28_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu28_wayA_upd select + congr_cl28_wA_d(1) <= (congr_cl28_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu28_wayA_upd select + congr_cl28_wA_d(2) <= (congr_cl28_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu28_wayA_upd select + congr_cl28_wA_d(3) <= (congr_cl28_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu28_wayA_upd select + congr_cl28_wA_d(4) <= (congr_cl28_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu28_wayA_upd select + congr_cl28_wA_d(5) <= (congr_cl28_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu29_wayA_upd select + congr_cl29_wA_d(0) <= (congr_cl29_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu29_wayA_upd select + congr_cl29_wA_d(1) <= (congr_cl29_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu29_wayA_upd select + congr_cl29_wA_d(2) <= (congr_cl29_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu29_wayA_upd select + congr_cl29_wA_d(3) <= (congr_cl29_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu29_wayA_upd select + congr_cl29_wA_d(4) <= (congr_cl29_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu29_wayA_upd select + congr_cl29_wA_d(5) <= (congr_cl29_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu30_wayA_upd select + congr_cl30_wA_d(0) <= (congr_cl30_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu30_wayA_upd select + congr_cl30_wA_d(1) <= (congr_cl30_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu30_wayA_upd select + congr_cl30_wA_d(2) <= (congr_cl30_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu30_wayA_upd select + congr_cl30_wA_d(3) <= (congr_cl30_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu30_wayA_upd select + congr_cl30_wA_d(4) <= (congr_cl30_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu30_wayA_upd select + congr_cl30_wA_d(5) <= (congr_cl30_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu31_wayA_upd select + congr_cl31_wA_d(0) <= (congr_cl31_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu31_wayA_upd select + congr_cl31_wA_d(1) <= (congr_cl31_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu31_wayA_upd select + congr_cl31_wA_d(2) <= (congr_cl31_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu31_wayA_upd select + congr_cl31_wA_d(3) <= (congr_cl31_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu31_wayA_upd select + congr_cl31_wA_d(4) <= (congr_cl31_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu31_wayA_upd select + congr_cl31_wA_d(5) <= (congr_cl31_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu0_wayB_upd select + congr_cl0_wB_d(0) <= (congr_cl0_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu0_wayB_upd select + congr_cl0_wB_d(1) <= (congr_cl0_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu0_wayB_upd select + congr_cl0_wB_d(2) <= (congr_cl0_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu0_wayB_upd select + congr_cl0_wB_d(3) <= (congr_cl0_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu0_wayB_upd select + congr_cl0_wB_d(4) <= (congr_cl0_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu0_wayB_upd select + congr_cl0_wB_d(5) <= (congr_cl0_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu1_wayB_upd select + congr_cl1_wB_d(0) <= (congr_cl1_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu1_wayB_upd select + congr_cl1_wB_d(1) <= (congr_cl1_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu1_wayB_upd select + congr_cl1_wB_d(2) <= (congr_cl1_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu1_wayB_upd select + congr_cl1_wB_d(3) <= (congr_cl1_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu1_wayB_upd select + congr_cl1_wB_d(4) <= (congr_cl1_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu1_wayB_upd select + congr_cl1_wB_d(5) <= (congr_cl1_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu2_wayB_upd select + congr_cl2_wB_d(0) <= (congr_cl2_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu2_wayB_upd select + congr_cl2_wB_d(1) <= (congr_cl2_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu2_wayB_upd select + congr_cl2_wB_d(2) <= (congr_cl2_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu2_wayB_upd select + congr_cl2_wB_d(3) <= (congr_cl2_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu2_wayB_upd select + congr_cl2_wB_d(4) <= (congr_cl2_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu2_wayB_upd select + congr_cl2_wB_d(5) <= (congr_cl2_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu3_wayB_upd select + congr_cl3_wB_d(0) <= (congr_cl3_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu3_wayB_upd select + congr_cl3_wB_d(1) <= (congr_cl3_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu3_wayB_upd select + congr_cl3_wB_d(2) <= (congr_cl3_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu3_wayB_upd select + congr_cl3_wB_d(3) <= (congr_cl3_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu3_wayB_upd select + congr_cl3_wB_d(4) <= (congr_cl3_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu3_wayB_upd select + congr_cl3_wB_d(5) <= (congr_cl3_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu4_wayB_upd select + congr_cl4_wB_d(0) <= (congr_cl4_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu4_wayB_upd select + congr_cl4_wB_d(1) <= (congr_cl4_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu4_wayB_upd select + congr_cl4_wB_d(2) <= (congr_cl4_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu4_wayB_upd select + congr_cl4_wB_d(3) <= (congr_cl4_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu4_wayB_upd select + congr_cl4_wB_d(4) <= (congr_cl4_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu4_wayB_upd select + congr_cl4_wB_d(5) <= (congr_cl4_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu5_wayB_upd select + congr_cl5_wB_d(0) <= (congr_cl5_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu5_wayB_upd select + congr_cl5_wB_d(1) <= (congr_cl5_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu5_wayB_upd select + congr_cl5_wB_d(2) <= (congr_cl5_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu5_wayB_upd select + congr_cl5_wB_d(3) <= (congr_cl5_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu5_wayB_upd select + congr_cl5_wB_d(4) <= (congr_cl5_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu5_wayB_upd select + congr_cl5_wB_d(5) <= (congr_cl5_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu6_wayB_upd select + congr_cl6_wB_d(0) <= (congr_cl6_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu6_wayB_upd select + congr_cl6_wB_d(1) <= (congr_cl6_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu6_wayB_upd select + congr_cl6_wB_d(2) <= (congr_cl6_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu6_wayB_upd select + congr_cl6_wB_d(3) <= (congr_cl6_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu6_wayB_upd select + congr_cl6_wB_d(4) <= (congr_cl6_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu6_wayB_upd select + congr_cl6_wB_d(5) <= (congr_cl6_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu7_wayB_upd select + congr_cl7_wB_d(0) <= (congr_cl7_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu7_wayB_upd select + congr_cl7_wB_d(1) <= (congr_cl7_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu7_wayB_upd select + congr_cl7_wB_d(2) <= (congr_cl7_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu7_wayB_upd select + congr_cl7_wB_d(3) <= (congr_cl7_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu7_wayB_upd select + congr_cl7_wB_d(4) <= (congr_cl7_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu7_wayB_upd select + congr_cl7_wB_d(5) <= (congr_cl7_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu8_wayB_upd select + congr_cl8_wB_d(0) <= (congr_cl8_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu8_wayB_upd select + congr_cl8_wB_d(1) <= (congr_cl8_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu8_wayB_upd select + congr_cl8_wB_d(2) <= (congr_cl8_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu8_wayB_upd select + congr_cl8_wB_d(3) <= (congr_cl8_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu8_wayB_upd select + congr_cl8_wB_d(4) <= (congr_cl8_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu8_wayB_upd select + congr_cl8_wB_d(5) <= (congr_cl8_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu9_wayB_upd select + congr_cl9_wB_d(0) <= (congr_cl9_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu9_wayB_upd select + congr_cl9_wB_d(1) <= (congr_cl9_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu9_wayB_upd select + congr_cl9_wB_d(2) <= (congr_cl9_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu9_wayB_upd select + congr_cl9_wB_d(3) <= (congr_cl9_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu9_wayB_upd select + congr_cl9_wB_d(4) <= (congr_cl9_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu9_wayB_upd select + congr_cl9_wB_d(5) <= (congr_cl9_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu10_wayB_upd select + congr_cl10_wB_d(0) <= (congr_cl10_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu10_wayB_upd select + congr_cl10_wB_d(1) <= (congr_cl10_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu10_wayB_upd select + congr_cl10_wB_d(2) <= (congr_cl10_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu10_wayB_upd select + congr_cl10_wB_d(3) <= (congr_cl10_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu10_wayB_upd select + congr_cl10_wB_d(4) <= (congr_cl10_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu10_wayB_upd select + congr_cl10_wB_d(5) <= (congr_cl10_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu11_wayB_upd select + congr_cl11_wB_d(0) <= (congr_cl11_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu11_wayB_upd select + congr_cl11_wB_d(1) <= (congr_cl11_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu11_wayB_upd select + congr_cl11_wB_d(2) <= (congr_cl11_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu11_wayB_upd select + congr_cl11_wB_d(3) <= (congr_cl11_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu11_wayB_upd select + congr_cl11_wB_d(4) <= (congr_cl11_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu11_wayB_upd select + congr_cl11_wB_d(5) <= (congr_cl11_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu12_wayB_upd select + congr_cl12_wB_d(0) <= (congr_cl12_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu12_wayB_upd select + congr_cl12_wB_d(1) <= (congr_cl12_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu12_wayB_upd select + congr_cl12_wB_d(2) <= (congr_cl12_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu12_wayB_upd select + congr_cl12_wB_d(3) <= (congr_cl12_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu12_wayB_upd select + congr_cl12_wB_d(4) <= (congr_cl12_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu12_wayB_upd select + congr_cl12_wB_d(5) <= (congr_cl12_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu13_wayB_upd select + congr_cl13_wB_d(0) <= (congr_cl13_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu13_wayB_upd select + congr_cl13_wB_d(1) <= (congr_cl13_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu13_wayB_upd select + congr_cl13_wB_d(2) <= (congr_cl13_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu13_wayB_upd select + congr_cl13_wB_d(3) <= (congr_cl13_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu13_wayB_upd select + congr_cl13_wB_d(4) <= (congr_cl13_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu13_wayB_upd select + congr_cl13_wB_d(5) <= (congr_cl13_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu14_wayB_upd select + congr_cl14_wB_d(0) <= (congr_cl14_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu14_wayB_upd select + congr_cl14_wB_d(1) <= (congr_cl14_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu14_wayB_upd select + congr_cl14_wB_d(2) <= (congr_cl14_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu14_wayB_upd select + congr_cl14_wB_d(3) <= (congr_cl14_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu14_wayB_upd select + congr_cl14_wB_d(4) <= (congr_cl14_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu14_wayB_upd select + congr_cl14_wB_d(5) <= (congr_cl14_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu15_wayB_upd select + congr_cl15_wB_d(0) <= (congr_cl15_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu15_wayB_upd select + congr_cl15_wB_d(1) <= (congr_cl15_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu15_wayB_upd select + congr_cl15_wB_d(2) <= (congr_cl15_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu15_wayB_upd select + congr_cl15_wB_d(3) <= (congr_cl15_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu15_wayB_upd select + congr_cl15_wB_d(4) <= (congr_cl15_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu15_wayB_upd select + congr_cl15_wB_d(5) <= (congr_cl15_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu16_wayB_upd select + congr_cl16_wB_d(0) <= (congr_cl16_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu16_wayB_upd select + congr_cl16_wB_d(1) <= (congr_cl16_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu16_wayB_upd select + congr_cl16_wB_d(2) <= (congr_cl16_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu16_wayB_upd select + congr_cl16_wB_d(3) <= (congr_cl16_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu16_wayB_upd select + congr_cl16_wB_d(4) <= (congr_cl16_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu16_wayB_upd select + congr_cl16_wB_d(5) <= (congr_cl16_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu17_wayB_upd select + congr_cl17_wB_d(0) <= (congr_cl17_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu17_wayB_upd select + congr_cl17_wB_d(1) <= (congr_cl17_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu17_wayB_upd select + congr_cl17_wB_d(2) <= (congr_cl17_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu17_wayB_upd select + congr_cl17_wB_d(3) <= (congr_cl17_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu17_wayB_upd select + congr_cl17_wB_d(4) <= (congr_cl17_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu17_wayB_upd select + congr_cl17_wB_d(5) <= (congr_cl17_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu18_wayB_upd select + congr_cl18_wB_d(0) <= (congr_cl18_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu18_wayB_upd select + congr_cl18_wB_d(1) <= (congr_cl18_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu18_wayB_upd select + congr_cl18_wB_d(2) <= (congr_cl18_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu18_wayB_upd select + congr_cl18_wB_d(3) <= (congr_cl18_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu18_wayB_upd select + congr_cl18_wB_d(4) <= (congr_cl18_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu18_wayB_upd select + congr_cl18_wB_d(5) <= (congr_cl18_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu19_wayB_upd select + congr_cl19_wB_d(0) <= (congr_cl19_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu19_wayB_upd select + congr_cl19_wB_d(1) <= (congr_cl19_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu19_wayB_upd select + congr_cl19_wB_d(2) <= (congr_cl19_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu19_wayB_upd select + congr_cl19_wB_d(3) <= (congr_cl19_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu19_wayB_upd select + congr_cl19_wB_d(4) <= (congr_cl19_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu19_wayB_upd select + congr_cl19_wB_d(5) <= (congr_cl19_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu20_wayB_upd select + congr_cl20_wB_d(0) <= (congr_cl20_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu20_wayB_upd select + congr_cl20_wB_d(1) <= (congr_cl20_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu20_wayB_upd select + congr_cl20_wB_d(2) <= (congr_cl20_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu20_wayB_upd select + congr_cl20_wB_d(3) <= (congr_cl20_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu20_wayB_upd select + congr_cl20_wB_d(4) <= (congr_cl20_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu20_wayB_upd select + congr_cl20_wB_d(5) <= (congr_cl20_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu21_wayB_upd select + congr_cl21_wB_d(0) <= (congr_cl21_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu21_wayB_upd select + congr_cl21_wB_d(1) <= (congr_cl21_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu21_wayB_upd select + congr_cl21_wB_d(2) <= (congr_cl21_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu21_wayB_upd select + congr_cl21_wB_d(3) <= (congr_cl21_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu21_wayB_upd select + congr_cl21_wB_d(4) <= (congr_cl21_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu21_wayB_upd select + congr_cl21_wB_d(5) <= (congr_cl21_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu22_wayB_upd select + congr_cl22_wB_d(0) <= (congr_cl22_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu22_wayB_upd select + congr_cl22_wB_d(1) <= (congr_cl22_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu22_wayB_upd select + congr_cl22_wB_d(2) <= (congr_cl22_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu22_wayB_upd select + congr_cl22_wB_d(3) <= (congr_cl22_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu22_wayB_upd select + congr_cl22_wB_d(4) <= (congr_cl22_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu22_wayB_upd select + congr_cl22_wB_d(5) <= (congr_cl22_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu23_wayB_upd select + congr_cl23_wB_d(0) <= (congr_cl23_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu23_wayB_upd select + congr_cl23_wB_d(1) <= (congr_cl23_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu23_wayB_upd select + congr_cl23_wB_d(2) <= (congr_cl23_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu23_wayB_upd select + congr_cl23_wB_d(3) <= (congr_cl23_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu23_wayB_upd select + congr_cl23_wB_d(4) <= (congr_cl23_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu23_wayB_upd select + congr_cl23_wB_d(5) <= (congr_cl23_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu24_wayB_upd select + congr_cl24_wB_d(0) <= (congr_cl24_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu24_wayB_upd select + congr_cl24_wB_d(1) <= (congr_cl24_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu24_wayB_upd select + congr_cl24_wB_d(2) <= (congr_cl24_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu24_wayB_upd select + congr_cl24_wB_d(3) <= (congr_cl24_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu24_wayB_upd select + congr_cl24_wB_d(4) <= (congr_cl24_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu24_wayB_upd select + congr_cl24_wB_d(5) <= (congr_cl24_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu25_wayB_upd select + congr_cl25_wB_d(0) <= (congr_cl25_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu25_wayB_upd select + congr_cl25_wB_d(1) <= (congr_cl25_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu25_wayB_upd select + congr_cl25_wB_d(2) <= (congr_cl25_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu25_wayB_upd select + congr_cl25_wB_d(3) <= (congr_cl25_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu25_wayB_upd select + congr_cl25_wB_d(4) <= (congr_cl25_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu25_wayB_upd select + congr_cl25_wB_d(5) <= (congr_cl25_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu26_wayB_upd select + congr_cl26_wB_d(0) <= (congr_cl26_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu26_wayB_upd select + congr_cl26_wB_d(1) <= (congr_cl26_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu26_wayB_upd select + congr_cl26_wB_d(2) <= (congr_cl26_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu26_wayB_upd select + congr_cl26_wB_d(3) <= (congr_cl26_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu26_wayB_upd select + congr_cl26_wB_d(4) <= (congr_cl26_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu26_wayB_upd select + congr_cl26_wB_d(5) <= (congr_cl26_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu27_wayB_upd select + congr_cl27_wB_d(0) <= (congr_cl27_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu27_wayB_upd select + congr_cl27_wB_d(1) <= (congr_cl27_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu27_wayB_upd select + congr_cl27_wB_d(2) <= (congr_cl27_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu27_wayB_upd select + congr_cl27_wB_d(3) <= (congr_cl27_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu27_wayB_upd select + congr_cl27_wB_d(4) <= (congr_cl27_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu27_wayB_upd select + congr_cl27_wB_d(5) <= (congr_cl27_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu28_wayB_upd select + congr_cl28_wB_d(0) <= (congr_cl28_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu28_wayB_upd select + congr_cl28_wB_d(1) <= (congr_cl28_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu28_wayB_upd select + congr_cl28_wB_d(2) <= (congr_cl28_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu28_wayB_upd select + congr_cl28_wB_d(3) <= (congr_cl28_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu28_wayB_upd select + congr_cl28_wB_d(4) <= (congr_cl28_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu28_wayB_upd select + congr_cl28_wB_d(5) <= (congr_cl28_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu29_wayB_upd select + congr_cl29_wB_d(0) <= (congr_cl29_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu29_wayB_upd select + congr_cl29_wB_d(1) <= (congr_cl29_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu29_wayB_upd select + congr_cl29_wB_d(2) <= (congr_cl29_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu29_wayB_upd select + congr_cl29_wB_d(3) <= (congr_cl29_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu29_wayB_upd select + congr_cl29_wB_d(4) <= (congr_cl29_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu29_wayB_upd select + congr_cl29_wB_d(5) <= (congr_cl29_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu30_wayB_upd select + congr_cl30_wB_d(0) <= (congr_cl30_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu30_wayB_upd select + congr_cl30_wB_d(1) <= (congr_cl30_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu30_wayB_upd select + congr_cl30_wB_d(2) <= (congr_cl30_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu30_wayB_upd select + congr_cl30_wB_d(3) <= (congr_cl30_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu30_wayB_upd select + congr_cl30_wB_d(4) <= (congr_cl30_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu30_wayB_upd select + congr_cl30_wB_d(5) <= (congr_cl30_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu31_wayB_upd select + congr_cl31_wB_d(0) <= (congr_cl31_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu31_wayB_upd select + congr_cl31_wB_d(1) <= (congr_cl31_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu31_wayB_upd select + congr_cl31_wB_d(2) <= (congr_cl31_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu31_wayB_upd select + congr_cl31_wB_d(3) <= (congr_cl31_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu31_wayB_upd select + congr_cl31_wB_d(4) <= (congr_cl31_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu31_wayB_upd select + congr_cl31_wB_d(5) <= (congr_cl31_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu0_wayC_upd select + congr_cl0_wC_d(0) <= (congr_cl0_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu0_wayC_upd select + congr_cl0_wC_d(1) <= (congr_cl0_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu0_wayC_upd select + congr_cl0_wC_d(2) <= (congr_cl0_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu0_wayC_upd select + congr_cl0_wC_d(3) <= (congr_cl0_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu0_wayC_upd select + congr_cl0_wC_d(4) <= (congr_cl0_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu0_wayC_upd select + congr_cl0_wC_d(5) <= (congr_cl0_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu1_wayC_upd select + congr_cl1_wC_d(0) <= (congr_cl1_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu1_wayC_upd select + congr_cl1_wC_d(1) <= (congr_cl1_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu1_wayC_upd select + congr_cl1_wC_d(2) <= (congr_cl1_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu1_wayC_upd select + congr_cl1_wC_d(3) <= (congr_cl1_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu1_wayC_upd select + congr_cl1_wC_d(4) <= (congr_cl1_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu1_wayC_upd select + congr_cl1_wC_d(5) <= (congr_cl1_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu2_wayC_upd select + congr_cl2_wC_d(0) <= (congr_cl2_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu2_wayC_upd select + congr_cl2_wC_d(1) <= (congr_cl2_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu2_wayC_upd select + congr_cl2_wC_d(2) <= (congr_cl2_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu2_wayC_upd select + congr_cl2_wC_d(3) <= (congr_cl2_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu2_wayC_upd select + congr_cl2_wC_d(4) <= (congr_cl2_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu2_wayC_upd select + congr_cl2_wC_d(5) <= (congr_cl2_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu3_wayC_upd select + congr_cl3_wC_d(0) <= (congr_cl3_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu3_wayC_upd select + congr_cl3_wC_d(1) <= (congr_cl3_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu3_wayC_upd select + congr_cl3_wC_d(2) <= (congr_cl3_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu3_wayC_upd select + congr_cl3_wC_d(3) <= (congr_cl3_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu3_wayC_upd select + congr_cl3_wC_d(4) <= (congr_cl3_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu3_wayC_upd select + congr_cl3_wC_d(5) <= (congr_cl3_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu4_wayC_upd select + congr_cl4_wC_d(0) <= (congr_cl4_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu4_wayC_upd select + congr_cl4_wC_d(1) <= (congr_cl4_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu4_wayC_upd select + congr_cl4_wC_d(2) <= (congr_cl4_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu4_wayC_upd select + congr_cl4_wC_d(3) <= (congr_cl4_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu4_wayC_upd select + congr_cl4_wC_d(4) <= (congr_cl4_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu4_wayC_upd select + congr_cl4_wC_d(5) <= (congr_cl4_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu5_wayC_upd select + congr_cl5_wC_d(0) <= (congr_cl5_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu5_wayC_upd select + congr_cl5_wC_d(1) <= (congr_cl5_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu5_wayC_upd select + congr_cl5_wC_d(2) <= (congr_cl5_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu5_wayC_upd select + congr_cl5_wC_d(3) <= (congr_cl5_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu5_wayC_upd select + congr_cl5_wC_d(4) <= (congr_cl5_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu5_wayC_upd select + congr_cl5_wC_d(5) <= (congr_cl5_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu6_wayC_upd select + congr_cl6_wC_d(0) <= (congr_cl6_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu6_wayC_upd select + congr_cl6_wC_d(1) <= (congr_cl6_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu6_wayC_upd select + congr_cl6_wC_d(2) <= (congr_cl6_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu6_wayC_upd select + congr_cl6_wC_d(3) <= (congr_cl6_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu6_wayC_upd select + congr_cl6_wC_d(4) <= (congr_cl6_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu6_wayC_upd select + congr_cl6_wC_d(5) <= (congr_cl6_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu7_wayC_upd select + congr_cl7_wC_d(0) <= (congr_cl7_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu7_wayC_upd select + congr_cl7_wC_d(1) <= (congr_cl7_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu7_wayC_upd select + congr_cl7_wC_d(2) <= (congr_cl7_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu7_wayC_upd select + congr_cl7_wC_d(3) <= (congr_cl7_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu7_wayC_upd select + congr_cl7_wC_d(4) <= (congr_cl7_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu7_wayC_upd select + congr_cl7_wC_d(5) <= (congr_cl7_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu8_wayC_upd select + congr_cl8_wC_d(0) <= (congr_cl8_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu8_wayC_upd select + congr_cl8_wC_d(1) <= (congr_cl8_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu8_wayC_upd select + congr_cl8_wC_d(2) <= (congr_cl8_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu8_wayC_upd select + congr_cl8_wC_d(3) <= (congr_cl8_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu8_wayC_upd select + congr_cl8_wC_d(4) <= (congr_cl8_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu8_wayC_upd select + congr_cl8_wC_d(5) <= (congr_cl8_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu9_wayC_upd select + congr_cl9_wC_d(0) <= (congr_cl9_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu9_wayC_upd select + congr_cl9_wC_d(1) <= (congr_cl9_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu9_wayC_upd select + congr_cl9_wC_d(2) <= (congr_cl9_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu9_wayC_upd select + congr_cl9_wC_d(3) <= (congr_cl9_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu9_wayC_upd select + congr_cl9_wC_d(4) <= (congr_cl9_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu9_wayC_upd select + congr_cl9_wC_d(5) <= (congr_cl9_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu10_wayC_upd select + congr_cl10_wC_d(0) <= (congr_cl10_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu10_wayC_upd select + congr_cl10_wC_d(1) <= (congr_cl10_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu10_wayC_upd select + congr_cl10_wC_d(2) <= (congr_cl10_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu10_wayC_upd select + congr_cl10_wC_d(3) <= (congr_cl10_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu10_wayC_upd select + congr_cl10_wC_d(4) <= (congr_cl10_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu10_wayC_upd select + congr_cl10_wC_d(5) <= (congr_cl10_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu11_wayC_upd select + congr_cl11_wC_d(0) <= (congr_cl11_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu11_wayC_upd select + congr_cl11_wC_d(1) <= (congr_cl11_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu11_wayC_upd select + congr_cl11_wC_d(2) <= (congr_cl11_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu11_wayC_upd select + congr_cl11_wC_d(3) <= (congr_cl11_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu11_wayC_upd select + congr_cl11_wC_d(4) <= (congr_cl11_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu11_wayC_upd select + congr_cl11_wC_d(5) <= (congr_cl11_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu12_wayC_upd select + congr_cl12_wC_d(0) <= (congr_cl12_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu12_wayC_upd select + congr_cl12_wC_d(1) <= (congr_cl12_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu12_wayC_upd select + congr_cl12_wC_d(2) <= (congr_cl12_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu12_wayC_upd select + congr_cl12_wC_d(3) <= (congr_cl12_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu12_wayC_upd select + congr_cl12_wC_d(4) <= (congr_cl12_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu12_wayC_upd select + congr_cl12_wC_d(5) <= (congr_cl12_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu13_wayC_upd select + congr_cl13_wC_d(0) <= (congr_cl13_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu13_wayC_upd select + congr_cl13_wC_d(1) <= (congr_cl13_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu13_wayC_upd select + congr_cl13_wC_d(2) <= (congr_cl13_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu13_wayC_upd select + congr_cl13_wC_d(3) <= (congr_cl13_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu13_wayC_upd select + congr_cl13_wC_d(4) <= (congr_cl13_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu13_wayC_upd select + congr_cl13_wC_d(5) <= (congr_cl13_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu14_wayC_upd select + congr_cl14_wC_d(0) <= (congr_cl14_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu14_wayC_upd select + congr_cl14_wC_d(1) <= (congr_cl14_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu14_wayC_upd select + congr_cl14_wC_d(2) <= (congr_cl14_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu14_wayC_upd select + congr_cl14_wC_d(3) <= (congr_cl14_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu14_wayC_upd select + congr_cl14_wC_d(4) <= (congr_cl14_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu14_wayC_upd select + congr_cl14_wC_d(5) <= (congr_cl14_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu15_wayC_upd select + congr_cl15_wC_d(0) <= (congr_cl15_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu15_wayC_upd select + congr_cl15_wC_d(1) <= (congr_cl15_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu15_wayC_upd select + congr_cl15_wC_d(2) <= (congr_cl15_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu15_wayC_upd select + congr_cl15_wC_d(3) <= (congr_cl15_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu15_wayC_upd select + congr_cl15_wC_d(4) <= (congr_cl15_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu15_wayC_upd select + congr_cl15_wC_d(5) <= (congr_cl15_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu16_wayC_upd select + congr_cl16_wC_d(0) <= (congr_cl16_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu16_wayC_upd select + congr_cl16_wC_d(1) <= (congr_cl16_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu16_wayC_upd select + congr_cl16_wC_d(2) <= (congr_cl16_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu16_wayC_upd select + congr_cl16_wC_d(3) <= (congr_cl16_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu16_wayC_upd select + congr_cl16_wC_d(4) <= (congr_cl16_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu16_wayC_upd select + congr_cl16_wC_d(5) <= (congr_cl16_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu17_wayC_upd select + congr_cl17_wC_d(0) <= (congr_cl17_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu17_wayC_upd select + congr_cl17_wC_d(1) <= (congr_cl17_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu17_wayC_upd select + congr_cl17_wC_d(2) <= (congr_cl17_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu17_wayC_upd select + congr_cl17_wC_d(3) <= (congr_cl17_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu17_wayC_upd select + congr_cl17_wC_d(4) <= (congr_cl17_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu17_wayC_upd select + congr_cl17_wC_d(5) <= (congr_cl17_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu18_wayC_upd select + congr_cl18_wC_d(0) <= (congr_cl18_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu18_wayC_upd select + congr_cl18_wC_d(1) <= (congr_cl18_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu18_wayC_upd select + congr_cl18_wC_d(2) <= (congr_cl18_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu18_wayC_upd select + congr_cl18_wC_d(3) <= (congr_cl18_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu18_wayC_upd select + congr_cl18_wC_d(4) <= (congr_cl18_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu18_wayC_upd select + congr_cl18_wC_d(5) <= (congr_cl18_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu19_wayC_upd select + congr_cl19_wC_d(0) <= (congr_cl19_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu19_wayC_upd select + congr_cl19_wC_d(1) <= (congr_cl19_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu19_wayC_upd select + congr_cl19_wC_d(2) <= (congr_cl19_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu19_wayC_upd select + congr_cl19_wC_d(3) <= (congr_cl19_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu19_wayC_upd select + congr_cl19_wC_d(4) <= (congr_cl19_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu19_wayC_upd select + congr_cl19_wC_d(5) <= (congr_cl19_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu20_wayC_upd select + congr_cl20_wC_d(0) <= (congr_cl20_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu20_wayC_upd select + congr_cl20_wC_d(1) <= (congr_cl20_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu20_wayC_upd select + congr_cl20_wC_d(2) <= (congr_cl20_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu20_wayC_upd select + congr_cl20_wC_d(3) <= (congr_cl20_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu20_wayC_upd select + congr_cl20_wC_d(4) <= (congr_cl20_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu20_wayC_upd select + congr_cl20_wC_d(5) <= (congr_cl20_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu21_wayC_upd select + congr_cl21_wC_d(0) <= (congr_cl21_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu21_wayC_upd select + congr_cl21_wC_d(1) <= (congr_cl21_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu21_wayC_upd select + congr_cl21_wC_d(2) <= (congr_cl21_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu21_wayC_upd select + congr_cl21_wC_d(3) <= (congr_cl21_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu21_wayC_upd select + congr_cl21_wC_d(4) <= (congr_cl21_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu21_wayC_upd select + congr_cl21_wC_d(5) <= (congr_cl21_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu22_wayC_upd select + congr_cl22_wC_d(0) <= (congr_cl22_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu22_wayC_upd select + congr_cl22_wC_d(1) <= (congr_cl22_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu22_wayC_upd select + congr_cl22_wC_d(2) <= (congr_cl22_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu22_wayC_upd select + congr_cl22_wC_d(3) <= (congr_cl22_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu22_wayC_upd select + congr_cl22_wC_d(4) <= (congr_cl22_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu22_wayC_upd select + congr_cl22_wC_d(5) <= (congr_cl22_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu23_wayC_upd select + congr_cl23_wC_d(0) <= (congr_cl23_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu23_wayC_upd select + congr_cl23_wC_d(1) <= (congr_cl23_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu23_wayC_upd select + congr_cl23_wC_d(2) <= (congr_cl23_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu23_wayC_upd select + congr_cl23_wC_d(3) <= (congr_cl23_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu23_wayC_upd select + congr_cl23_wC_d(4) <= (congr_cl23_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu23_wayC_upd select + congr_cl23_wC_d(5) <= (congr_cl23_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu24_wayC_upd select + congr_cl24_wC_d(0) <= (congr_cl24_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu24_wayC_upd select + congr_cl24_wC_d(1) <= (congr_cl24_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu24_wayC_upd select + congr_cl24_wC_d(2) <= (congr_cl24_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu24_wayC_upd select + congr_cl24_wC_d(3) <= (congr_cl24_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu24_wayC_upd select + congr_cl24_wC_d(4) <= (congr_cl24_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu24_wayC_upd select + congr_cl24_wC_d(5) <= (congr_cl24_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu25_wayC_upd select + congr_cl25_wC_d(0) <= (congr_cl25_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu25_wayC_upd select + congr_cl25_wC_d(1) <= (congr_cl25_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu25_wayC_upd select + congr_cl25_wC_d(2) <= (congr_cl25_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu25_wayC_upd select + congr_cl25_wC_d(3) <= (congr_cl25_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu25_wayC_upd select + congr_cl25_wC_d(4) <= (congr_cl25_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu25_wayC_upd select + congr_cl25_wC_d(5) <= (congr_cl25_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu26_wayC_upd select + congr_cl26_wC_d(0) <= (congr_cl26_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu26_wayC_upd select + congr_cl26_wC_d(1) <= (congr_cl26_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu26_wayC_upd select + congr_cl26_wC_d(2) <= (congr_cl26_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu26_wayC_upd select + congr_cl26_wC_d(3) <= (congr_cl26_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu26_wayC_upd select + congr_cl26_wC_d(4) <= (congr_cl26_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu26_wayC_upd select + congr_cl26_wC_d(5) <= (congr_cl26_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu27_wayC_upd select + congr_cl27_wC_d(0) <= (congr_cl27_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu27_wayC_upd select + congr_cl27_wC_d(1) <= (congr_cl27_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu27_wayC_upd select + congr_cl27_wC_d(2) <= (congr_cl27_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu27_wayC_upd select + congr_cl27_wC_d(3) <= (congr_cl27_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu27_wayC_upd select + congr_cl27_wC_d(4) <= (congr_cl27_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu27_wayC_upd select + congr_cl27_wC_d(5) <= (congr_cl27_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu28_wayC_upd select + congr_cl28_wC_d(0) <= (congr_cl28_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu28_wayC_upd select + congr_cl28_wC_d(1) <= (congr_cl28_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu28_wayC_upd select + congr_cl28_wC_d(2) <= (congr_cl28_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu28_wayC_upd select + congr_cl28_wC_d(3) <= (congr_cl28_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu28_wayC_upd select + congr_cl28_wC_d(4) <= (congr_cl28_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu28_wayC_upd select + congr_cl28_wC_d(5) <= (congr_cl28_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu29_wayC_upd select + congr_cl29_wC_d(0) <= (congr_cl29_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu29_wayC_upd select + congr_cl29_wC_d(1) <= (congr_cl29_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu29_wayC_upd select + congr_cl29_wC_d(2) <= (congr_cl29_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu29_wayC_upd select + congr_cl29_wC_d(3) <= (congr_cl29_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu29_wayC_upd select + congr_cl29_wC_d(4) <= (congr_cl29_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu29_wayC_upd select + congr_cl29_wC_d(5) <= (congr_cl29_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu30_wayC_upd select + congr_cl30_wC_d(0) <= (congr_cl30_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu30_wayC_upd select + congr_cl30_wC_d(1) <= (congr_cl30_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu30_wayC_upd select + congr_cl30_wC_d(2) <= (congr_cl30_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu30_wayC_upd select + congr_cl30_wC_d(3) <= (congr_cl30_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu30_wayC_upd select + congr_cl30_wC_d(4) <= (congr_cl30_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu30_wayC_upd select + congr_cl30_wC_d(5) <= (congr_cl30_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu31_wayC_upd select + congr_cl31_wC_d(0) <= (congr_cl31_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu31_wayC_upd select + congr_cl31_wC_d(1) <= (congr_cl31_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu31_wayC_upd select + congr_cl31_wC_d(2) <= (congr_cl31_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu31_wayC_upd select + congr_cl31_wC_d(3) <= (congr_cl31_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu31_wayC_upd select + congr_cl31_wC_d(4) <= (congr_cl31_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu31_wayC_upd select + congr_cl31_wC_d(5) <= (congr_cl31_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu0_wayD_upd select + congr_cl0_wD_d(0) <= (congr_cl0_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu0_wayD_upd select + congr_cl0_wD_d(1) <= (congr_cl0_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu0_wayD_upd select + congr_cl0_wD_d(2) <= (congr_cl0_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu0_wayD_upd select + congr_cl0_wD_d(3) <= (congr_cl0_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu0_wayD_upd select + congr_cl0_wD_d(4) <= (congr_cl0_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu0_wayD_upd select + congr_cl0_wD_d(5) <= (congr_cl0_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu1_wayD_upd select + congr_cl1_wD_d(0) <= (congr_cl1_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu1_wayD_upd select + congr_cl1_wD_d(1) <= (congr_cl1_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu1_wayD_upd select + congr_cl1_wD_d(2) <= (congr_cl1_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu1_wayD_upd select + congr_cl1_wD_d(3) <= (congr_cl1_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu1_wayD_upd select + congr_cl1_wD_d(4) <= (congr_cl1_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu1_wayD_upd select + congr_cl1_wD_d(5) <= (congr_cl1_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu2_wayD_upd select + congr_cl2_wD_d(0) <= (congr_cl2_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu2_wayD_upd select + congr_cl2_wD_d(1) <= (congr_cl2_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu2_wayD_upd select + congr_cl2_wD_d(2) <= (congr_cl2_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu2_wayD_upd select + congr_cl2_wD_d(3) <= (congr_cl2_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu2_wayD_upd select + congr_cl2_wD_d(4) <= (congr_cl2_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu2_wayD_upd select + congr_cl2_wD_d(5) <= (congr_cl2_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu3_wayD_upd select + congr_cl3_wD_d(0) <= (congr_cl3_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu3_wayD_upd select + congr_cl3_wD_d(1) <= (congr_cl3_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu3_wayD_upd select + congr_cl3_wD_d(2) <= (congr_cl3_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu3_wayD_upd select + congr_cl3_wD_d(3) <= (congr_cl3_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu3_wayD_upd select + congr_cl3_wD_d(4) <= (congr_cl3_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu3_wayD_upd select + congr_cl3_wD_d(5) <= (congr_cl3_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu4_wayD_upd select + congr_cl4_wD_d(0) <= (congr_cl4_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu4_wayD_upd select + congr_cl4_wD_d(1) <= (congr_cl4_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu4_wayD_upd select + congr_cl4_wD_d(2) <= (congr_cl4_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu4_wayD_upd select + congr_cl4_wD_d(3) <= (congr_cl4_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu4_wayD_upd select + congr_cl4_wD_d(4) <= (congr_cl4_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu4_wayD_upd select + congr_cl4_wD_d(5) <= (congr_cl4_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu5_wayD_upd select + congr_cl5_wD_d(0) <= (congr_cl5_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu5_wayD_upd select + congr_cl5_wD_d(1) <= (congr_cl5_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu5_wayD_upd select + congr_cl5_wD_d(2) <= (congr_cl5_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu5_wayD_upd select + congr_cl5_wD_d(3) <= (congr_cl5_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu5_wayD_upd select + congr_cl5_wD_d(4) <= (congr_cl5_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu5_wayD_upd select + congr_cl5_wD_d(5) <= (congr_cl5_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu6_wayD_upd select + congr_cl6_wD_d(0) <= (congr_cl6_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu6_wayD_upd select + congr_cl6_wD_d(1) <= (congr_cl6_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu6_wayD_upd select + congr_cl6_wD_d(2) <= (congr_cl6_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu6_wayD_upd select + congr_cl6_wD_d(3) <= (congr_cl6_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu6_wayD_upd select + congr_cl6_wD_d(4) <= (congr_cl6_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu6_wayD_upd select + congr_cl6_wD_d(5) <= (congr_cl6_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu7_wayD_upd select + congr_cl7_wD_d(0) <= (congr_cl7_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu7_wayD_upd select + congr_cl7_wD_d(1) <= (congr_cl7_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu7_wayD_upd select + congr_cl7_wD_d(2) <= (congr_cl7_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu7_wayD_upd select + congr_cl7_wD_d(3) <= (congr_cl7_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu7_wayD_upd select + congr_cl7_wD_d(4) <= (congr_cl7_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu7_wayD_upd select + congr_cl7_wD_d(5) <= (congr_cl7_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu8_wayD_upd select + congr_cl8_wD_d(0) <= (congr_cl8_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu8_wayD_upd select + congr_cl8_wD_d(1) <= (congr_cl8_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu8_wayD_upd select + congr_cl8_wD_d(2) <= (congr_cl8_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu8_wayD_upd select + congr_cl8_wD_d(3) <= (congr_cl8_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu8_wayD_upd select + congr_cl8_wD_d(4) <= (congr_cl8_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu8_wayD_upd select + congr_cl8_wD_d(5) <= (congr_cl8_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu9_wayD_upd select + congr_cl9_wD_d(0) <= (congr_cl9_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu9_wayD_upd select + congr_cl9_wD_d(1) <= (congr_cl9_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu9_wayD_upd select + congr_cl9_wD_d(2) <= (congr_cl9_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu9_wayD_upd select + congr_cl9_wD_d(3) <= (congr_cl9_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu9_wayD_upd select + congr_cl9_wD_d(4) <= (congr_cl9_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu9_wayD_upd select + congr_cl9_wD_d(5) <= (congr_cl9_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu10_wayD_upd select + congr_cl10_wD_d(0) <= (congr_cl10_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu10_wayD_upd select + congr_cl10_wD_d(1) <= (congr_cl10_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu10_wayD_upd select + congr_cl10_wD_d(2) <= (congr_cl10_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu10_wayD_upd select + congr_cl10_wD_d(3) <= (congr_cl10_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu10_wayD_upd select + congr_cl10_wD_d(4) <= (congr_cl10_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu10_wayD_upd select + congr_cl10_wD_d(5) <= (congr_cl10_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu11_wayD_upd select + congr_cl11_wD_d(0) <= (congr_cl11_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu11_wayD_upd select + congr_cl11_wD_d(1) <= (congr_cl11_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu11_wayD_upd select + congr_cl11_wD_d(2) <= (congr_cl11_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu11_wayD_upd select + congr_cl11_wD_d(3) <= (congr_cl11_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu11_wayD_upd select + congr_cl11_wD_d(4) <= (congr_cl11_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu11_wayD_upd select + congr_cl11_wD_d(5) <= (congr_cl11_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu12_wayD_upd select + congr_cl12_wD_d(0) <= (congr_cl12_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu12_wayD_upd select + congr_cl12_wD_d(1) <= (congr_cl12_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu12_wayD_upd select + congr_cl12_wD_d(2) <= (congr_cl12_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu12_wayD_upd select + congr_cl12_wD_d(3) <= (congr_cl12_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu12_wayD_upd select + congr_cl12_wD_d(4) <= (congr_cl12_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu12_wayD_upd select + congr_cl12_wD_d(5) <= (congr_cl12_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu13_wayD_upd select + congr_cl13_wD_d(0) <= (congr_cl13_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu13_wayD_upd select + congr_cl13_wD_d(1) <= (congr_cl13_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu13_wayD_upd select + congr_cl13_wD_d(2) <= (congr_cl13_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu13_wayD_upd select + congr_cl13_wD_d(3) <= (congr_cl13_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu13_wayD_upd select + congr_cl13_wD_d(4) <= (congr_cl13_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu13_wayD_upd select + congr_cl13_wD_d(5) <= (congr_cl13_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu14_wayD_upd select + congr_cl14_wD_d(0) <= (congr_cl14_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu14_wayD_upd select + congr_cl14_wD_d(1) <= (congr_cl14_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu14_wayD_upd select + congr_cl14_wD_d(2) <= (congr_cl14_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu14_wayD_upd select + congr_cl14_wD_d(3) <= (congr_cl14_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu14_wayD_upd select + congr_cl14_wD_d(4) <= (congr_cl14_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu14_wayD_upd select + congr_cl14_wD_d(5) <= (congr_cl14_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu15_wayD_upd select + congr_cl15_wD_d(0) <= (congr_cl15_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu15_wayD_upd select + congr_cl15_wD_d(1) <= (congr_cl15_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu15_wayD_upd select + congr_cl15_wD_d(2) <= (congr_cl15_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu15_wayD_upd select + congr_cl15_wD_d(3) <= (congr_cl15_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu15_wayD_upd select + congr_cl15_wD_d(4) <= (congr_cl15_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu15_wayD_upd select + congr_cl15_wD_d(5) <= (congr_cl15_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu16_wayD_upd select + congr_cl16_wD_d(0) <= (congr_cl16_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu16_wayD_upd select + congr_cl16_wD_d(1) <= (congr_cl16_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu16_wayD_upd select + congr_cl16_wD_d(2) <= (congr_cl16_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu16_wayD_upd select + congr_cl16_wD_d(3) <= (congr_cl16_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu16_wayD_upd select + congr_cl16_wD_d(4) <= (congr_cl16_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu16_wayD_upd select + congr_cl16_wD_d(5) <= (congr_cl16_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu17_wayD_upd select + congr_cl17_wD_d(0) <= (congr_cl17_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu17_wayD_upd select + congr_cl17_wD_d(1) <= (congr_cl17_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu17_wayD_upd select + congr_cl17_wD_d(2) <= (congr_cl17_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu17_wayD_upd select + congr_cl17_wD_d(3) <= (congr_cl17_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu17_wayD_upd select + congr_cl17_wD_d(4) <= (congr_cl17_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu17_wayD_upd select + congr_cl17_wD_d(5) <= (congr_cl17_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu18_wayD_upd select + congr_cl18_wD_d(0) <= (congr_cl18_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu18_wayD_upd select + congr_cl18_wD_d(1) <= (congr_cl18_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu18_wayD_upd select + congr_cl18_wD_d(2) <= (congr_cl18_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu18_wayD_upd select + congr_cl18_wD_d(3) <= (congr_cl18_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu18_wayD_upd select + congr_cl18_wD_d(4) <= (congr_cl18_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu18_wayD_upd select + congr_cl18_wD_d(5) <= (congr_cl18_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu19_wayD_upd select + congr_cl19_wD_d(0) <= (congr_cl19_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu19_wayD_upd select + congr_cl19_wD_d(1) <= (congr_cl19_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu19_wayD_upd select + congr_cl19_wD_d(2) <= (congr_cl19_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu19_wayD_upd select + congr_cl19_wD_d(3) <= (congr_cl19_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu19_wayD_upd select + congr_cl19_wD_d(4) <= (congr_cl19_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu19_wayD_upd select + congr_cl19_wD_d(5) <= (congr_cl19_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu20_wayD_upd select + congr_cl20_wD_d(0) <= (congr_cl20_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu20_wayD_upd select + congr_cl20_wD_d(1) <= (congr_cl20_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu20_wayD_upd select + congr_cl20_wD_d(2) <= (congr_cl20_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu20_wayD_upd select + congr_cl20_wD_d(3) <= (congr_cl20_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu20_wayD_upd select + congr_cl20_wD_d(4) <= (congr_cl20_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu20_wayD_upd select + congr_cl20_wD_d(5) <= (congr_cl20_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu21_wayD_upd select + congr_cl21_wD_d(0) <= (congr_cl21_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu21_wayD_upd select + congr_cl21_wD_d(1) <= (congr_cl21_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu21_wayD_upd select + congr_cl21_wD_d(2) <= (congr_cl21_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu21_wayD_upd select + congr_cl21_wD_d(3) <= (congr_cl21_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu21_wayD_upd select + congr_cl21_wD_d(4) <= (congr_cl21_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu21_wayD_upd select + congr_cl21_wD_d(5) <= (congr_cl21_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu22_wayD_upd select + congr_cl22_wD_d(0) <= (congr_cl22_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu22_wayD_upd select + congr_cl22_wD_d(1) <= (congr_cl22_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu22_wayD_upd select + congr_cl22_wD_d(2) <= (congr_cl22_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu22_wayD_upd select + congr_cl22_wD_d(3) <= (congr_cl22_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu22_wayD_upd select + congr_cl22_wD_d(4) <= (congr_cl22_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu22_wayD_upd select + congr_cl22_wD_d(5) <= (congr_cl22_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu23_wayD_upd select + congr_cl23_wD_d(0) <= (congr_cl23_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu23_wayD_upd select + congr_cl23_wD_d(1) <= (congr_cl23_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu23_wayD_upd select + congr_cl23_wD_d(2) <= (congr_cl23_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu23_wayD_upd select + congr_cl23_wD_d(3) <= (congr_cl23_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu23_wayD_upd select + congr_cl23_wD_d(4) <= (congr_cl23_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu23_wayD_upd select + congr_cl23_wD_d(5) <= (congr_cl23_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu24_wayD_upd select + congr_cl24_wD_d(0) <= (congr_cl24_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu24_wayD_upd select + congr_cl24_wD_d(1) <= (congr_cl24_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu24_wayD_upd select + congr_cl24_wD_d(2) <= (congr_cl24_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu24_wayD_upd select + congr_cl24_wD_d(3) <= (congr_cl24_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu24_wayD_upd select + congr_cl24_wD_d(4) <= (congr_cl24_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu24_wayD_upd select + congr_cl24_wD_d(5) <= (congr_cl24_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu25_wayD_upd select + congr_cl25_wD_d(0) <= (congr_cl25_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu25_wayD_upd select + congr_cl25_wD_d(1) <= (congr_cl25_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu25_wayD_upd select + congr_cl25_wD_d(2) <= (congr_cl25_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu25_wayD_upd select + congr_cl25_wD_d(3) <= (congr_cl25_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu25_wayD_upd select + congr_cl25_wD_d(4) <= (congr_cl25_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu25_wayD_upd select + congr_cl25_wD_d(5) <= (congr_cl25_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu26_wayD_upd select + congr_cl26_wD_d(0) <= (congr_cl26_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu26_wayD_upd select + congr_cl26_wD_d(1) <= (congr_cl26_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu26_wayD_upd select + congr_cl26_wD_d(2) <= (congr_cl26_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu26_wayD_upd select + congr_cl26_wD_d(3) <= (congr_cl26_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu26_wayD_upd select + congr_cl26_wD_d(4) <= (congr_cl26_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu26_wayD_upd select + congr_cl26_wD_d(5) <= (congr_cl26_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu27_wayD_upd select + congr_cl27_wD_d(0) <= (congr_cl27_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu27_wayD_upd select + congr_cl27_wD_d(1) <= (congr_cl27_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu27_wayD_upd select + congr_cl27_wD_d(2) <= (congr_cl27_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu27_wayD_upd select + congr_cl27_wD_d(3) <= (congr_cl27_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu27_wayD_upd select + congr_cl27_wD_d(4) <= (congr_cl27_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu27_wayD_upd select + congr_cl27_wD_d(5) <= (congr_cl27_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu28_wayD_upd select + congr_cl28_wD_d(0) <= (congr_cl28_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu28_wayD_upd select + congr_cl28_wD_d(1) <= (congr_cl28_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu28_wayD_upd select + congr_cl28_wD_d(2) <= (congr_cl28_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu28_wayD_upd select + congr_cl28_wD_d(3) <= (congr_cl28_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu28_wayD_upd select + congr_cl28_wD_d(4) <= (congr_cl28_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu28_wayD_upd select + congr_cl28_wD_d(5) <= (congr_cl28_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu29_wayD_upd select + congr_cl29_wD_d(0) <= (congr_cl29_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu29_wayD_upd select + congr_cl29_wD_d(1) <= (congr_cl29_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu29_wayD_upd select + congr_cl29_wD_d(2) <= (congr_cl29_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu29_wayD_upd select + congr_cl29_wD_d(3) <= (congr_cl29_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu29_wayD_upd select + congr_cl29_wD_d(4) <= (congr_cl29_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu29_wayD_upd select + congr_cl29_wD_d(5) <= (congr_cl29_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu30_wayD_upd select + congr_cl30_wD_d(0) <= (congr_cl30_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu30_wayD_upd select + congr_cl30_wD_d(1) <= (congr_cl30_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu30_wayD_upd select + congr_cl30_wD_d(2) <= (congr_cl30_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu30_wayD_upd select + congr_cl30_wD_d(3) <= (congr_cl30_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu30_wayD_upd select + congr_cl30_wD_d(4) <= (congr_cl30_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu30_wayD_upd select + congr_cl30_wD_d(5) <= (congr_cl30_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu31_wayD_upd select + congr_cl31_wD_d(0) <= (congr_cl31_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu31_wayD_upd select + congr_cl31_wD_d(1) <= (congr_cl31_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu31_wayD_upd select + congr_cl31_wD_d(2) <= (congr_cl31_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu31_wayD_upd select + congr_cl31_wD_d(3) <= (congr_cl31_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu31_wayD_upd select + congr_cl31_wD_d(4) <= (congr_cl31_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu31_wayD_upd select + congr_cl31_wD_d(5) <= (congr_cl31_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu0_wayE_upd select + congr_cl0_wE_d(0) <= (congr_cl0_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu0_wayE_upd select + congr_cl0_wE_d(1) <= (congr_cl0_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu0_wayE_upd select + congr_cl0_wE_d(2) <= (congr_cl0_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu0_wayE_upd select + congr_cl0_wE_d(3) <= (congr_cl0_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu0_wayE_upd select + congr_cl0_wE_d(4) <= (congr_cl0_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu0_wayE_upd select + congr_cl0_wE_d(5) <= (congr_cl0_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu1_wayE_upd select + congr_cl1_wE_d(0) <= (congr_cl1_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu1_wayE_upd select + congr_cl1_wE_d(1) <= (congr_cl1_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu1_wayE_upd select + congr_cl1_wE_d(2) <= (congr_cl1_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu1_wayE_upd select + congr_cl1_wE_d(3) <= (congr_cl1_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu1_wayE_upd select + congr_cl1_wE_d(4) <= (congr_cl1_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu1_wayE_upd select + congr_cl1_wE_d(5) <= (congr_cl1_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu2_wayE_upd select + congr_cl2_wE_d(0) <= (congr_cl2_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu2_wayE_upd select + congr_cl2_wE_d(1) <= (congr_cl2_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu2_wayE_upd select + congr_cl2_wE_d(2) <= (congr_cl2_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu2_wayE_upd select + congr_cl2_wE_d(3) <= (congr_cl2_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu2_wayE_upd select + congr_cl2_wE_d(4) <= (congr_cl2_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu2_wayE_upd select + congr_cl2_wE_d(5) <= (congr_cl2_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu3_wayE_upd select + congr_cl3_wE_d(0) <= (congr_cl3_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu3_wayE_upd select + congr_cl3_wE_d(1) <= (congr_cl3_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu3_wayE_upd select + congr_cl3_wE_d(2) <= (congr_cl3_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu3_wayE_upd select + congr_cl3_wE_d(3) <= (congr_cl3_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu3_wayE_upd select + congr_cl3_wE_d(4) <= (congr_cl3_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu3_wayE_upd select + congr_cl3_wE_d(5) <= (congr_cl3_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu4_wayE_upd select + congr_cl4_wE_d(0) <= (congr_cl4_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu4_wayE_upd select + congr_cl4_wE_d(1) <= (congr_cl4_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu4_wayE_upd select + congr_cl4_wE_d(2) <= (congr_cl4_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu4_wayE_upd select + congr_cl4_wE_d(3) <= (congr_cl4_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu4_wayE_upd select + congr_cl4_wE_d(4) <= (congr_cl4_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu4_wayE_upd select + congr_cl4_wE_d(5) <= (congr_cl4_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu5_wayE_upd select + congr_cl5_wE_d(0) <= (congr_cl5_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu5_wayE_upd select + congr_cl5_wE_d(1) <= (congr_cl5_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu5_wayE_upd select + congr_cl5_wE_d(2) <= (congr_cl5_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu5_wayE_upd select + congr_cl5_wE_d(3) <= (congr_cl5_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu5_wayE_upd select + congr_cl5_wE_d(4) <= (congr_cl5_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu5_wayE_upd select + congr_cl5_wE_d(5) <= (congr_cl5_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu6_wayE_upd select + congr_cl6_wE_d(0) <= (congr_cl6_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu6_wayE_upd select + congr_cl6_wE_d(1) <= (congr_cl6_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu6_wayE_upd select + congr_cl6_wE_d(2) <= (congr_cl6_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu6_wayE_upd select + congr_cl6_wE_d(3) <= (congr_cl6_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu6_wayE_upd select + congr_cl6_wE_d(4) <= (congr_cl6_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu6_wayE_upd select + congr_cl6_wE_d(5) <= (congr_cl6_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu7_wayE_upd select + congr_cl7_wE_d(0) <= (congr_cl7_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu7_wayE_upd select + congr_cl7_wE_d(1) <= (congr_cl7_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu7_wayE_upd select + congr_cl7_wE_d(2) <= (congr_cl7_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu7_wayE_upd select + congr_cl7_wE_d(3) <= (congr_cl7_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu7_wayE_upd select + congr_cl7_wE_d(4) <= (congr_cl7_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu7_wayE_upd select + congr_cl7_wE_d(5) <= (congr_cl7_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu8_wayE_upd select + congr_cl8_wE_d(0) <= (congr_cl8_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu8_wayE_upd select + congr_cl8_wE_d(1) <= (congr_cl8_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu8_wayE_upd select + congr_cl8_wE_d(2) <= (congr_cl8_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu8_wayE_upd select + congr_cl8_wE_d(3) <= (congr_cl8_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu8_wayE_upd select + congr_cl8_wE_d(4) <= (congr_cl8_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu8_wayE_upd select + congr_cl8_wE_d(5) <= (congr_cl8_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu9_wayE_upd select + congr_cl9_wE_d(0) <= (congr_cl9_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu9_wayE_upd select + congr_cl9_wE_d(1) <= (congr_cl9_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu9_wayE_upd select + congr_cl9_wE_d(2) <= (congr_cl9_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu9_wayE_upd select + congr_cl9_wE_d(3) <= (congr_cl9_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu9_wayE_upd select + congr_cl9_wE_d(4) <= (congr_cl9_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu9_wayE_upd select + congr_cl9_wE_d(5) <= (congr_cl9_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu10_wayE_upd select + congr_cl10_wE_d(0) <= (congr_cl10_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu10_wayE_upd select + congr_cl10_wE_d(1) <= (congr_cl10_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu10_wayE_upd select + congr_cl10_wE_d(2) <= (congr_cl10_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu10_wayE_upd select + congr_cl10_wE_d(3) <= (congr_cl10_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu10_wayE_upd select + congr_cl10_wE_d(4) <= (congr_cl10_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu10_wayE_upd select + congr_cl10_wE_d(5) <= (congr_cl10_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu11_wayE_upd select + congr_cl11_wE_d(0) <= (congr_cl11_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu11_wayE_upd select + congr_cl11_wE_d(1) <= (congr_cl11_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu11_wayE_upd select + congr_cl11_wE_d(2) <= (congr_cl11_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu11_wayE_upd select + congr_cl11_wE_d(3) <= (congr_cl11_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu11_wayE_upd select + congr_cl11_wE_d(4) <= (congr_cl11_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu11_wayE_upd select + congr_cl11_wE_d(5) <= (congr_cl11_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu12_wayE_upd select + congr_cl12_wE_d(0) <= (congr_cl12_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu12_wayE_upd select + congr_cl12_wE_d(1) <= (congr_cl12_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu12_wayE_upd select + congr_cl12_wE_d(2) <= (congr_cl12_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu12_wayE_upd select + congr_cl12_wE_d(3) <= (congr_cl12_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu12_wayE_upd select + congr_cl12_wE_d(4) <= (congr_cl12_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu12_wayE_upd select + congr_cl12_wE_d(5) <= (congr_cl12_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu13_wayE_upd select + congr_cl13_wE_d(0) <= (congr_cl13_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu13_wayE_upd select + congr_cl13_wE_d(1) <= (congr_cl13_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu13_wayE_upd select + congr_cl13_wE_d(2) <= (congr_cl13_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu13_wayE_upd select + congr_cl13_wE_d(3) <= (congr_cl13_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu13_wayE_upd select + congr_cl13_wE_d(4) <= (congr_cl13_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu13_wayE_upd select + congr_cl13_wE_d(5) <= (congr_cl13_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu14_wayE_upd select + congr_cl14_wE_d(0) <= (congr_cl14_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu14_wayE_upd select + congr_cl14_wE_d(1) <= (congr_cl14_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu14_wayE_upd select + congr_cl14_wE_d(2) <= (congr_cl14_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu14_wayE_upd select + congr_cl14_wE_d(3) <= (congr_cl14_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu14_wayE_upd select + congr_cl14_wE_d(4) <= (congr_cl14_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu14_wayE_upd select + congr_cl14_wE_d(5) <= (congr_cl14_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu15_wayE_upd select + congr_cl15_wE_d(0) <= (congr_cl15_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu15_wayE_upd select + congr_cl15_wE_d(1) <= (congr_cl15_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu15_wayE_upd select + congr_cl15_wE_d(2) <= (congr_cl15_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu15_wayE_upd select + congr_cl15_wE_d(3) <= (congr_cl15_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu15_wayE_upd select + congr_cl15_wE_d(4) <= (congr_cl15_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu15_wayE_upd select + congr_cl15_wE_d(5) <= (congr_cl15_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu16_wayE_upd select + congr_cl16_wE_d(0) <= (congr_cl16_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu16_wayE_upd select + congr_cl16_wE_d(1) <= (congr_cl16_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu16_wayE_upd select + congr_cl16_wE_d(2) <= (congr_cl16_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu16_wayE_upd select + congr_cl16_wE_d(3) <= (congr_cl16_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu16_wayE_upd select + congr_cl16_wE_d(4) <= (congr_cl16_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu16_wayE_upd select + congr_cl16_wE_d(5) <= (congr_cl16_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu17_wayE_upd select + congr_cl17_wE_d(0) <= (congr_cl17_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu17_wayE_upd select + congr_cl17_wE_d(1) <= (congr_cl17_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu17_wayE_upd select + congr_cl17_wE_d(2) <= (congr_cl17_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu17_wayE_upd select + congr_cl17_wE_d(3) <= (congr_cl17_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu17_wayE_upd select + congr_cl17_wE_d(4) <= (congr_cl17_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu17_wayE_upd select + congr_cl17_wE_d(5) <= (congr_cl17_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu18_wayE_upd select + congr_cl18_wE_d(0) <= (congr_cl18_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu18_wayE_upd select + congr_cl18_wE_d(1) <= (congr_cl18_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu18_wayE_upd select + congr_cl18_wE_d(2) <= (congr_cl18_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu18_wayE_upd select + congr_cl18_wE_d(3) <= (congr_cl18_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu18_wayE_upd select + congr_cl18_wE_d(4) <= (congr_cl18_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu18_wayE_upd select + congr_cl18_wE_d(5) <= (congr_cl18_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu19_wayE_upd select + congr_cl19_wE_d(0) <= (congr_cl19_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu19_wayE_upd select + congr_cl19_wE_d(1) <= (congr_cl19_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu19_wayE_upd select + congr_cl19_wE_d(2) <= (congr_cl19_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu19_wayE_upd select + congr_cl19_wE_d(3) <= (congr_cl19_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu19_wayE_upd select + congr_cl19_wE_d(4) <= (congr_cl19_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu19_wayE_upd select + congr_cl19_wE_d(5) <= (congr_cl19_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu20_wayE_upd select + congr_cl20_wE_d(0) <= (congr_cl20_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu20_wayE_upd select + congr_cl20_wE_d(1) <= (congr_cl20_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu20_wayE_upd select + congr_cl20_wE_d(2) <= (congr_cl20_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu20_wayE_upd select + congr_cl20_wE_d(3) <= (congr_cl20_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu20_wayE_upd select + congr_cl20_wE_d(4) <= (congr_cl20_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu20_wayE_upd select + congr_cl20_wE_d(5) <= (congr_cl20_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu21_wayE_upd select + congr_cl21_wE_d(0) <= (congr_cl21_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu21_wayE_upd select + congr_cl21_wE_d(1) <= (congr_cl21_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu21_wayE_upd select + congr_cl21_wE_d(2) <= (congr_cl21_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu21_wayE_upd select + congr_cl21_wE_d(3) <= (congr_cl21_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu21_wayE_upd select + congr_cl21_wE_d(4) <= (congr_cl21_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu21_wayE_upd select + congr_cl21_wE_d(5) <= (congr_cl21_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu22_wayE_upd select + congr_cl22_wE_d(0) <= (congr_cl22_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu22_wayE_upd select + congr_cl22_wE_d(1) <= (congr_cl22_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu22_wayE_upd select + congr_cl22_wE_d(2) <= (congr_cl22_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu22_wayE_upd select + congr_cl22_wE_d(3) <= (congr_cl22_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu22_wayE_upd select + congr_cl22_wE_d(4) <= (congr_cl22_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu22_wayE_upd select + congr_cl22_wE_d(5) <= (congr_cl22_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu23_wayE_upd select + congr_cl23_wE_d(0) <= (congr_cl23_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu23_wayE_upd select + congr_cl23_wE_d(1) <= (congr_cl23_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu23_wayE_upd select + congr_cl23_wE_d(2) <= (congr_cl23_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu23_wayE_upd select + congr_cl23_wE_d(3) <= (congr_cl23_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu23_wayE_upd select + congr_cl23_wE_d(4) <= (congr_cl23_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu23_wayE_upd select + congr_cl23_wE_d(5) <= (congr_cl23_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu24_wayE_upd select + congr_cl24_wE_d(0) <= (congr_cl24_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu24_wayE_upd select + congr_cl24_wE_d(1) <= (congr_cl24_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu24_wayE_upd select + congr_cl24_wE_d(2) <= (congr_cl24_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu24_wayE_upd select + congr_cl24_wE_d(3) <= (congr_cl24_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu24_wayE_upd select + congr_cl24_wE_d(4) <= (congr_cl24_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu24_wayE_upd select + congr_cl24_wE_d(5) <= (congr_cl24_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu25_wayE_upd select + congr_cl25_wE_d(0) <= (congr_cl25_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu25_wayE_upd select + congr_cl25_wE_d(1) <= (congr_cl25_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu25_wayE_upd select + congr_cl25_wE_d(2) <= (congr_cl25_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu25_wayE_upd select + congr_cl25_wE_d(3) <= (congr_cl25_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu25_wayE_upd select + congr_cl25_wE_d(4) <= (congr_cl25_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu25_wayE_upd select + congr_cl25_wE_d(5) <= (congr_cl25_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu26_wayE_upd select + congr_cl26_wE_d(0) <= (congr_cl26_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu26_wayE_upd select + congr_cl26_wE_d(1) <= (congr_cl26_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu26_wayE_upd select + congr_cl26_wE_d(2) <= (congr_cl26_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu26_wayE_upd select + congr_cl26_wE_d(3) <= (congr_cl26_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu26_wayE_upd select + congr_cl26_wE_d(4) <= (congr_cl26_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu26_wayE_upd select + congr_cl26_wE_d(5) <= (congr_cl26_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu27_wayE_upd select + congr_cl27_wE_d(0) <= (congr_cl27_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu27_wayE_upd select + congr_cl27_wE_d(1) <= (congr_cl27_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu27_wayE_upd select + congr_cl27_wE_d(2) <= (congr_cl27_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu27_wayE_upd select + congr_cl27_wE_d(3) <= (congr_cl27_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu27_wayE_upd select + congr_cl27_wE_d(4) <= (congr_cl27_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu27_wayE_upd select + congr_cl27_wE_d(5) <= (congr_cl27_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu28_wayE_upd select + congr_cl28_wE_d(0) <= (congr_cl28_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu28_wayE_upd select + congr_cl28_wE_d(1) <= (congr_cl28_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu28_wayE_upd select + congr_cl28_wE_d(2) <= (congr_cl28_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu28_wayE_upd select + congr_cl28_wE_d(3) <= (congr_cl28_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu28_wayE_upd select + congr_cl28_wE_d(4) <= (congr_cl28_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu28_wayE_upd select + congr_cl28_wE_d(5) <= (congr_cl28_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu29_wayE_upd select + congr_cl29_wE_d(0) <= (congr_cl29_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu29_wayE_upd select + congr_cl29_wE_d(1) <= (congr_cl29_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu29_wayE_upd select + congr_cl29_wE_d(2) <= (congr_cl29_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu29_wayE_upd select + congr_cl29_wE_d(3) <= (congr_cl29_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu29_wayE_upd select + congr_cl29_wE_d(4) <= (congr_cl29_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu29_wayE_upd select + congr_cl29_wE_d(5) <= (congr_cl29_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu30_wayE_upd select + congr_cl30_wE_d(0) <= (congr_cl30_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu30_wayE_upd select + congr_cl30_wE_d(1) <= (congr_cl30_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu30_wayE_upd select + congr_cl30_wE_d(2) <= (congr_cl30_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu30_wayE_upd select + congr_cl30_wE_d(3) <= (congr_cl30_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu30_wayE_upd select + congr_cl30_wE_d(4) <= (congr_cl30_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu30_wayE_upd select + congr_cl30_wE_d(5) <= (congr_cl30_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu31_wayE_upd select + congr_cl31_wE_d(0) <= (congr_cl31_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu31_wayE_upd select + congr_cl31_wE_d(1) <= (congr_cl31_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu31_wayE_upd select + congr_cl31_wE_d(2) <= (congr_cl31_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu31_wayE_upd select + congr_cl31_wE_d(3) <= (congr_cl31_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu31_wayE_upd select + congr_cl31_wE_d(4) <= (congr_cl31_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu31_wayE_upd select + congr_cl31_wE_d(5) <= (congr_cl31_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu0_wayF_upd select + congr_cl0_wF_d(0) <= (congr_cl0_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu0_wayF_upd select + congr_cl0_wF_d(1) <= (congr_cl0_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu0_wayF_upd select + congr_cl0_wF_d(2) <= (congr_cl0_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu0_wayF_upd select + congr_cl0_wF_d(3) <= (congr_cl0_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu0_wayF_upd select + congr_cl0_wF_d(4) <= (congr_cl0_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu0_wayF_upd select + congr_cl0_wF_d(5) <= (congr_cl0_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu1_wayF_upd select + congr_cl1_wF_d(0) <= (congr_cl1_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu1_wayF_upd select + congr_cl1_wF_d(1) <= (congr_cl1_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu1_wayF_upd select + congr_cl1_wF_d(2) <= (congr_cl1_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu1_wayF_upd select + congr_cl1_wF_d(3) <= (congr_cl1_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu1_wayF_upd select + congr_cl1_wF_d(4) <= (congr_cl1_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu1_wayF_upd select + congr_cl1_wF_d(5) <= (congr_cl1_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu2_wayF_upd select + congr_cl2_wF_d(0) <= (congr_cl2_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu2_wayF_upd select + congr_cl2_wF_d(1) <= (congr_cl2_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu2_wayF_upd select + congr_cl2_wF_d(2) <= (congr_cl2_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu2_wayF_upd select + congr_cl2_wF_d(3) <= (congr_cl2_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu2_wayF_upd select + congr_cl2_wF_d(4) <= (congr_cl2_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu2_wayF_upd select + congr_cl2_wF_d(5) <= (congr_cl2_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu3_wayF_upd select + congr_cl3_wF_d(0) <= (congr_cl3_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu3_wayF_upd select + congr_cl3_wF_d(1) <= (congr_cl3_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu3_wayF_upd select + congr_cl3_wF_d(2) <= (congr_cl3_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu3_wayF_upd select + congr_cl3_wF_d(3) <= (congr_cl3_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu3_wayF_upd select + congr_cl3_wF_d(4) <= (congr_cl3_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu3_wayF_upd select + congr_cl3_wF_d(5) <= (congr_cl3_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu4_wayF_upd select + congr_cl4_wF_d(0) <= (congr_cl4_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu4_wayF_upd select + congr_cl4_wF_d(1) <= (congr_cl4_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu4_wayF_upd select + congr_cl4_wF_d(2) <= (congr_cl4_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu4_wayF_upd select + congr_cl4_wF_d(3) <= (congr_cl4_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu4_wayF_upd select + congr_cl4_wF_d(4) <= (congr_cl4_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu4_wayF_upd select + congr_cl4_wF_d(5) <= (congr_cl4_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu5_wayF_upd select + congr_cl5_wF_d(0) <= (congr_cl5_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu5_wayF_upd select + congr_cl5_wF_d(1) <= (congr_cl5_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu5_wayF_upd select + congr_cl5_wF_d(2) <= (congr_cl5_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu5_wayF_upd select + congr_cl5_wF_d(3) <= (congr_cl5_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu5_wayF_upd select + congr_cl5_wF_d(4) <= (congr_cl5_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu5_wayF_upd select + congr_cl5_wF_d(5) <= (congr_cl5_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu6_wayF_upd select + congr_cl6_wF_d(0) <= (congr_cl6_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu6_wayF_upd select + congr_cl6_wF_d(1) <= (congr_cl6_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu6_wayF_upd select + congr_cl6_wF_d(2) <= (congr_cl6_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu6_wayF_upd select + congr_cl6_wF_d(3) <= (congr_cl6_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu6_wayF_upd select + congr_cl6_wF_d(4) <= (congr_cl6_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu6_wayF_upd select + congr_cl6_wF_d(5) <= (congr_cl6_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu7_wayF_upd select + congr_cl7_wF_d(0) <= (congr_cl7_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu7_wayF_upd select + congr_cl7_wF_d(1) <= (congr_cl7_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu7_wayF_upd select + congr_cl7_wF_d(2) <= (congr_cl7_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu7_wayF_upd select + congr_cl7_wF_d(3) <= (congr_cl7_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu7_wayF_upd select + congr_cl7_wF_d(4) <= (congr_cl7_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu7_wayF_upd select + congr_cl7_wF_d(5) <= (congr_cl7_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu8_wayF_upd select + congr_cl8_wF_d(0) <= (congr_cl8_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu8_wayF_upd select + congr_cl8_wF_d(1) <= (congr_cl8_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu8_wayF_upd select + congr_cl8_wF_d(2) <= (congr_cl8_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu8_wayF_upd select + congr_cl8_wF_d(3) <= (congr_cl8_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu8_wayF_upd select + congr_cl8_wF_d(4) <= (congr_cl8_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu8_wayF_upd select + congr_cl8_wF_d(5) <= (congr_cl8_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu9_wayF_upd select + congr_cl9_wF_d(0) <= (congr_cl9_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu9_wayF_upd select + congr_cl9_wF_d(1) <= (congr_cl9_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu9_wayF_upd select + congr_cl9_wF_d(2) <= (congr_cl9_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu9_wayF_upd select + congr_cl9_wF_d(3) <= (congr_cl9_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu9_wayF_upd select + congr_cl9_wF_d(4) <= (congr_cl9_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu9_wayF_upd select + congr_cl9_wF_d(5) <= (congr_cl9_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu10_wayF_upd select + congr_cl10_wF_d(0) <= (congr_cl10_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu10_wayF_upd select + congr_cl10_wF_d(1) <= (congr_cl10_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu10_wayF_upd select + congr_cl10_wF_d(2) <= (congr_cl10_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu10_wayF_upd select + congr_cl10_wF_d(3) <= (congr_cl10_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu10_wayF_upd select + congr_cl10_wF_d(4) <= (congr_cl10_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu10_wayF_upd select + congr_cl10_wF_d(5) <= (congr_cl10_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu11_wayF_upd select + congr_cl11_wF_d(0) <= (congr_cl11_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu11_wayF_upd select + congr_cl11_wF_d(1) <= (congr_cl11_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu11_wayF_upd select + congr_cl11_wF_d(2) <= (congr_cl11_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu11_wayF_upd select + congr_cl11_wF_d(3) <= (congr_cl11_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu11_wayF_upd select + congr_cl11_wF_d(4) <= (congr_cl11_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu11_wayF_upd select + congr_cl11_wF_d(5) <= (congr_cl11_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu12_wayF_upd select + congr_cl12_wF_d(0) <= (congr_cl12_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu12_wayF_upd select + congr_cl12_wF_d(1) <= (congr_cl12_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu12_wayF_upd select + congr_cl12_wF_d(2) <= (congr_cl12_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu12_wayF_upd select + congr_cl12_wF_d(3) <= (congr_cl12_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu12_wayF_upd select + congr_cl12_wF_d(4) <= (congr_cl12_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu12_wayF_upd select + congr_cl12_wF_d(5) <= (congr_cl12_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu13_wayF_upd select + congr_cl13_wF_d(0) <= (congr_cl13_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu13_wayF_upd select + congr_cl13_wF_d(1) <= (congr_cl13_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu13_wayF_upd select + congr_cl13_wF_d(2) <= (congr_cl13_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu13_wayF_upd select + congr_cl13_wF_d(3) <= (congr_cl13_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu13_wayF_upd select + congr_cl13_wF_d(4) <= (congr_cl13_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu13_wayF_upd select + congr_cl13_wF_d(5) <= (congr_cl13_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu14_wayF_upd select + congr_cl14_wF_d(0) <= (congr_cl14_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu14_wayF_upd select + congr_cl14_wF_d(1) <= (congr_cl14_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu14_wayF_upd select + congr_cl14_wF_d(2) <= (congr_cl14_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu14_wayF_upd select + congr_cl14_wF_d(3) <= (congr_cl14_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu14_wayF_upd select + congr_cl14_wF_d(4) <= (congr_cl14_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu14_wayF_upd select + congr_cl14_wF_d(5) <= (congr_cl14_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu15_wayF_upd select + congr_cl15_wF_d(0) <= (congr_cl15_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu15_wayF_upd select + congr_cl15_wF_d(1) <= (congr_cl15_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu15_wayF_upd select + congr_cl15_wF_d(2) <= (congr_cl15_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu15_wayF_upd select + congr_cl15_wF_d(3) <= (congr_cl15_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu15_wayF_upd select + congr_cl15_wF_d(4) <= (congr_cl15_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu15_wayF_upd select + congr_cl15_wF_d(5) <= (congr_cl15_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu16_wayF_upd select + congr_cl16_wF_d(0) <= (congr_cl16_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu16_wayF_upd select + congr_cl16_wF_d(1) <= (congr_cl16_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu16_wayF_upd select + congr_cl16_wF_d(2) <= (congr_cl16_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu16_wayF_upd select + congr_cl16_wF_d(3) <= (congr_cl16_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu16_wayF_upd select + congr_cl16_wF_d(4) <= (congr_cl16_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu16_wayF_upd select + congr_cl16_wF_d(5) <= (congr_cl16_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu17_wayF_upd select + congr_cl17_wF_d(0) <= (congr_cl17_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu17_wayF_upd select + congr_cl17_wF_d(1) <= (congr_cl17_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu17_wayF_upd select + congr_cl17_wF_d(2) <= (congr_cl17_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu17_wayF_upd select + congr_cl17_wF_d(3) <= (congr_cl17_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu17_wayF_upd select + congr_cl17_wF_d(4) <= (congr_cl17_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu17_wayF_upd select + congr_cl17_wF_d(5) <= (congr_cl17_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu18_wayF_upd select + congr_cl18_wF_d(0) <= (congr_cl18_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu18_wayF_upd select + congr_cl18_wF_d(1) <= (congr_cl18_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu18_wayF_upd select + congr_cl18_wF_d(2) <= (congr_cl18_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu18_wayF_upd select + congr_cl18_wF_d(3) <= (congr_cl18_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu18_wayF_upd select + congr_cl18_wF_d(4) <= (congr_cl18_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu18_wayF_upd select + congr_cl18_wF_d(5) <= (congr_cl18_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu19_wayF_upd select + congr_cl19_wF_d(0) <= (congr_cl19_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu19_wayF_upd select + congr_cl19_wF_d(1) <= (congr_cl19_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu19_wayF_upd select + congr_cl19_wF_d(2) <= (congr_cl19_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu19_wayF_upd select + congr_cl19_wF_d(3) <= (congr_cl19_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu19_wayF_upd select + congr_cl19_wF_d(4) <= (congr_cl19_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu19_wayF_upd select + congr_cl19_wF_d(5) <= (congr_cl19_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu20_wayF_upd select + congr_cl20_wF_d(0) <= (congr_cl20_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu20_wayF_upd select + congr_cl20_wF_d(1) <= (congr_cl20_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu20_wayF_upd select + congr_cl20_wF_d(2) <= (congr_cl20_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu20_wayF_upd select + congr_cl20_wF_d(3) <= (congr_cl20_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu20_wayF_upd select + congr_cl20_wF_d(4) <= (congr_cl20_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu20_wayF_upd select + congr_cl20_wF_d(5) <= (congr_cl20_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu21_wayF_upd select + congr_cl21_wF_d(0) <= (congr_cl21_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu21_wayF_upd select + congr_cl21_wF_d(1) <= (congr_cl21_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu21_wayF_upd select + congr_cl21_wF_d(2) <= (congr_cl21_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu21_wayF_upd select + congr_cl21_wF_d(3) <= (congr_cl21_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu21_wayF_upd select + congr_cl21_wF_d(4) <= (congr_cl21_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu21_wayF_upd select + congr_cl21_wF_d(5) <= (congr_cl21_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu22_wayF_upd select + congr_cl22_wF_d(0) <= (congr_cl22_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu22_wayF_upd select + congr_cl22_wF_d(1) <= (congr_cl22_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu22_wayF_upd select + congr_cl22_wF_d(2) <= (congr_cl22_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu22_wayF_upd select + congr_cl22_wF_d(3) <= (congr_cl22_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu22_wayF_upd select + congr_cl22_wF_d(4) <= (congr_cl22_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu22_wayF_upd select + congr_cl22_wF_d(5) <= (congr_cl22_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu23_wayF_upd select + congr_cl23_wF_d(0) <= (congr_cl23_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu23_wayF_upd select + congr_cl23_wF_d(1) <= (congr_cl23_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu23_wayF_upd select + congr_cl23_wF_d(2) <= (congr_cl23_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu23_wayF_upd select + congr_cl23_wF_d(3) <= (congr_cl23_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu23_wayF_upd select + congr_cl23_wF_d(4) <= (congr_cl23_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu23_wayF_upd select + congr_cl23_wF_d(5) <= (congr_cl23_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu24_wayF_upd select + congr_cl24_wF_d(0) <= (congr_cl24_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu24_wayF_upd select + congr_cl24_wF_d(1) <= (congr_cl24_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu24_wayF_upd select + congr_cl24_wF_d(2) <= (congr_cl24_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu24_wayF_upd select + congr_cl24_wF_d(3) <= (congr_cl24_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu24_wayF_upd select + congr_cl24_wF_d(4) <= (congr_cl24_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu24_wayF_upd select + congr_cl24_wF_d(5) <= (congr_cl24_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu25_wayF_upd select + congr_cl25_wF_d(0) <= (congr_cl25_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu25_wayF_upd select + congr_cl25_wF_d(1) <= (congr_cl25_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu25_wayF_upd select + congr_cl25_wF_d(2) <= (congr_cl25_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu25_wayF_upd select + congr_cl25_wF_d(3) <= (congr_cl25_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu25_wayF_upd select + congr_cl25_wF_d(4) <= (congr_cl25_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu25_wayF_upd select + congr_cl25_wF_d(5) <= (congr_cl25_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu26_wayF_upd select + congr_cl26_wF_d(0) <= (congr_cl26_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu26_wayF_upd select + congr_cl26_wF_d(1) <= (congr_cl26_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu26_wayF_upd select + congr_cl26_wF_d(2) <= (congr_cl26_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu26_wayF_upd select + congr_cl26_wF_d(3) <= (congr_cl26_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu26_wayF_upd select + congr_cl26_wF_d(4) <= (congr_cl26_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu26_wayF_upd select + congr_cl26_wF_d(5) <= (congr_cl26_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu27_wayF_upd select + congr_cl27_wF_d(0) <= (congr_cl27_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu27_wayF_upd select + congr_cl27_wF_d(1) <= (congr_cl27_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu27_wayF_upd select + congr_cl27_wF_d(2) <= (congr_cl27_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu27_wayF_upd select + congr_cl27_wF_d(3) <= (congr_cl27_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu27_wayF_upd select + congr_cl27_wF_d(4) <= (congr_cl27_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu27_wayF_upd select + congr_cl27_wF_d(5) <= (congr_cl27_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu28_wayF_upd select + congr_cl28_wF_d(0) <= (congr_cl28_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu28_wayF_upd select + congr_cl28_wF_d(1) <= (congr_cl28_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu28_wayF_upd select + congr_cl28_wF_d(2) <= (congr_cl28_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu28_wayF_upd select + congr_cl28_wF_d(3) <= (congr_cl28_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu28_wayF_upd select + congr_cl28_wF_d(4) <= (congr_cl28_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu28_wayF_upd select + congr_cl28_wF_d(5) <= (congr_cl28_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu29_wayF_upd select + congr_cl29_wF_d(0) <= (congr_cl29_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu29_wayF_upd select + congr_cl29_wF_d(1) <= (congr_cl29_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu29_wayF_upd select + congr_cl29_wF_d(2) <= (congr_cl29_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu29_wayF_upd select + congr_cl29_wF_d(3) <= (congr_cl29_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu29_wayF_upd select + congr_cl29_wF_d(4) <= (congr_cl29_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu29_wayF_upd select + congr_cl29_wF_d(5) <= (congr_cl29_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu30_wayF_upd select + congr_cl30_wF_d(0) <= (congr_cl30_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu30_wayF_upd select + congr_cl30_wF_d(1) <= (congr_cl30_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu30_wayF_upd select + congr_cl30_wF_d(2) <= (congr_cl30_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu30_wayF_upd select + congr_cl30_wF_d(3) <= (congr_cl30_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu30_wayF_upd select + congr_cl30_wF_d(4) <= (congr_cl30_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu30_wayF_upd select + congr_cl30_wF_d(5) <= (congr_cl30_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu31_wayF_upd select + congr_cl31_wF_d(0) <= (congr_cl31_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu31_wayF_upd select + congr_cl31_wF_d(1) <= (congr_cl31_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu31_wayF_upd select + congr_cl31_wF_d(2) <= (congr_cl31_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu31_wayF_upd select + congr_cl31_wF_d(3) <= (congr_cl31_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu31_wayF_upd select + congr_cl31_wF_d(4) <= (congr_cl31_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu31_wayF_upd select + congr_cl31_wF_d(5) <= (congr_cl31_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu0_wayG_upd select + congr_cl0_wG_d(0) <= (congr_cl0_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu0_wayG_upd select + congr_cl0_wG_d(1) <= (congr_cl0_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu0_wayG_upd select + congr_cl0_wG_d(2) <= (congr_cl0_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu0_wayG_upd select + congr_cl0_wG_d(3) <= (congr_cl0_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu0_wayG_upd select + congr_cl0_wG_d(4) <= (congr_cl0_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu0_wayG_upd select + congr_cl0_wG_d(5) <= (congr_cl0_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu1_wayG_upd select + congr_cl1_wG_d(0) <= (congr_cl1_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu1_wayG_upd select + congr_cl1_wG_d(1) <= (congr_cl1_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu1_wayG_upd select + congr_cl1_wG_d(2) <= (congr_cl1_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu1_wayG_upd select + congr_cl1_wG_d(3) <= (congr_cl1_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu1_wayG_upd select + congr_cl1_wG_d(4) <= (congr_cl1_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu1_wayG_upd select + congr_cl1_wG_d(5) <= (congr_cl1_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu2_wayG_upd select + congr_cl2_wG_d(0) <= (congr_cl2_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu2_wayG_upd select + congr_cl2_wG_d(1) <= (congr_cl2_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu2_wayG_upd select + congr_cl2_wG_d(2) <= (congr_cl2_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu2_wayG_upd select + congr_cl2_wG_d(3) <= (congr_cl2_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu2_wayG_upd select + congr_cl2_wG_d(4) <= (congr_cl2_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu2_wayG_upd select + congr_cl2_wG_d(5) <= (congr_cl2_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu3_wayG_upd select + congr_cl3_wG_d(0) <= (congr_cl3_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu3_wayG_upd select + congr_cl3_wG_d(1) <= (congr_cl3_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu3_wayG_upd select + congr_cl3_wG_d(2) <= (congr_cl3_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu3_wayG_upd select + congr_cl3_wG_d(3) <= (congr_cl3_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu3_wayG_upd select + congr_cl3_wG_d(4) <= (congr_cl3_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu3_wayG_upd select + congr_cl3_wG_d(5) <= (congr_cl3_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu4_wayG_upd select + congr_cl4_wG_d(0) <= (congr_cl4_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu4_wayG_upd select + congr_cl4_wG_d(1) <= (congr_cl4_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu4_wayG_upd select + congr_cl4_wG_d(2) <= (congr_cl4_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu4_wayG_upd select + congr_cl4_wG_d(3) <= (congr_cl4_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu4_wayG_upd select + congr_cl4_wG_d(4) <= (congr_cl4_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu4_wayG_upd select + congr_cl4_wG_d(5) <= (congr_cl4_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu5_wayG_upd select + congr_cl5_wG_d(0) <= (congr_cl5_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu5_wayG_upd select + congr_cl5_wG_d(1) <= (congr_cl5_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu5_wayG_upd select + congr_cl5_wG_d(2) <= (congr_cl5_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu5_wayG_upd select + congr_cl5_wG_d(3) <= (congr_cl5_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu5_wayG_upd select + congr_cl5_wG_d(4) <= (congr_cl5_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu5_wayG_upd select + congr_cl5_wG_d(5) <= (congr_cl5_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu6_wayG_upd select + congr_cl6_wG_d(0) <= (congr_cl6_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu6_wayG_upd select + congr_cl6_wG_d(1) <= (congr_cl6_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu6_wayG_upd select + congr_cl6_wG_d(2) <= (congr_cl6_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu6_wayG_upd select + congr_cl6_wG_d(3) <= (congr_cl6_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu6_wayG_upd select + congr_cl6_wG_d(4) <= (congr_cl6_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu6_wayG_upd select + congr_cl6_wG_d(5) <= (congr_cl6_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu7_wayG_upd select + congr_cl7_wG_d(0) <= (congr_cl7_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu7_wayG_upd select + congr_cl7_wG_d(1) <= (congr_cl7_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu7_wayG_upd select + congr_cl7_wG_d(2) <= (congr_cl7_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu7_wayG_upd select + congr_cl7_wG_d(3) <= (congr_cl7_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu7_wayG_upd select + congr_cl7_wG_d(4) <= (congr_cl7_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu7_wayG_upd select + congr_cl7_wG_d(5) <= (congr_cl7_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu8_wayG_upd select + congr_cl8_wG_d(0) <= (congr_cl8_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu8_wayG_upd select + congr_cl8_wG_d(1) <= (congr_cl8_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu8_wayG_upd select + congr_cl8_wG_d(2) <= (congr_cl8_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu8_wayG_upd select + congr_cl8_wG_d(3) <= (congr_cl8_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu8_wayG_upd select + congr_cl8_wG_d(4) <= (congr_cl8_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu8_wayG_upd select + congr_cl8_wG_d(5) <= (congr_cl8_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu9_wayG_upd select + congr_cl9_wG_d(0) <= (congr_cl9_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu9_wayG_upd select + congr_cl9_wG_d(1) <= (congr_cl9_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu9_wayG_upd select + congr_cl9_wG_d(2) <= (congr_cl9_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu9_wayG_upd select + congr_cl9_wG_d(3) <= (congr_cl9_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu9_wayG_upd select + congr_cl9_wG_d(4) <= (congr_cl9_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu9_wayG_upd select + congr_cl9_wG_d(5) <= (congr_cl9_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu10_wayG_upd select + congr_cl10_wG_d(0) <= (congr_cl10_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu10_wayG_upd select + congr_cl10_wG_d(1) <= (congr_cl10_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu10_wayG_upd select + congr_cl10_wG_d(2) <= (congr_cl10_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu10_wayG_upd select + congr_cl10_wG_d(3) <= (congr_cl10_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu10_wayG_upd select + congr_cl10_wG_d(4) <= (congr_cl10_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu10_wayG_upd select + congr_cl10_wG_d(5) <= (congr_cl10_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu11_wayG_upd select + congr_cl11_wG_d(0) <= (congr_cl11_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu11_wayG_upd select + congr_cl11_wG_d(1) <= (congr_cl11_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu11_wayG_upd select + congr_cl11_wG_d(2) <= (congr_cl11_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu11_wayG_upd select + congr_cl11_wG_d(3) <= (congr_cl11_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu11_wayG_upd select + congr_cl11_wG_d(4) <= (congr_cl11_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu11_wayG_upd select + congr_cl11_wG_d(5) <= (congr_cl11_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu12_wayG_upd select + congr_cl12_wG_d(0) <= (congr_cl12_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu12_wayG_upd select + congr_cl12_wG_d(1) <= (congr_cl12_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu12_wayG_upd select + congr_cl12_wG_d(2) <= (congr_cl12_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu12_wayG_upd select + congr_cl12_wG_d(3) <= (congr_cl12_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu12_wayG_upd select + congr_cl12_wG_d(4) <= (congr_cl12_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu12_wayG_upd select + congr_cl12_wG_d(5) <= (congr_cl12_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu13_wayG_upd select + congr_cl13_wG_d(0) <= (congr_cl13_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu13_wayG_upd select + congr_cl13_wG_d(1) <= (congr_cl13_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu13_wayG_upd select + congr_cl13_wG_d(2) <= (congr_cl13_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu13_wayG_upd select + congr_cl13_wG_d(3) <= (congr_cl13_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu13_wayG_upd select + congr_cl13_wG_d(4) <= (congr_cl13_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu13_wayG_upd select + congr_cl13_wG_d(5) <= (congr_cl13_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu14_wayG_upd select + congr_cl14_wG_d(0) <= (congr_cl14_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu14_wayG_upd select + congr_cl14_wG_d(1) <= (congr_cl14_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu14_wayG_upd select + congr_cl14_wG_d(2) <= (congr_cl14_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu14_wayG_upd select + congr_cl14_wG_d(3) <= (congr_cl14_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu14_wayG_upd select + congr_cl14_wG_d(4) <= (congr_cl14_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu14_wayG_upd select + congr_cl14_wG_d(5) <= (congr_cl14_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu15_wayG_upd select + congr_cl15_wG_d(0) <= (congr_cl15_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu15_wayG_upd select + congr_cl15_wG_d(1) <= (congr_cl15_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu15_wayG_upd select + congr_cl15_wG_d(2) <= (congr_cl15_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu15_wayG_upd select + congr_cl15_wG_d(3) <= (congr_cl15_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu15_wayG_upd select + congr_cl15_wG_d(4) <= (congr_cl15_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu15_wayG_upd select + congr_cl15_wG_d(5) <= (congr_cl15_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu16_wayG_upd select + congr_cl16_wG_d(0) <= (congr_cl16_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu16_wayG_upd select + congr_cl16_wG_d(1) <= (congr_cl16_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu16_wayG_upd select + congr_cl16_wG_d(2) <= (congr_cl16_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu16_wayG_upd select + congr_cl16_wG_d(3) <= (congr_cl16_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu16_wayG_upd select + congr_cl16_wG_d(4) <= (congr_cl16_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu16_wayG_upd select + congr_cl16_wG_d(5) <= (congr_cl16_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu17_wayG_upd select + congr_cl17_wG_d(0) <= (congr_cl17_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu17_wayG_upd select + congr_cl17_wG_d(1) <= (congr_cl17_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu17_wayG_upd select + congr_cl17_wG_d(2) <= (congr_cl17_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu17_wayG_upd select + congr_cl17_wG_d(3) <= (congr_cl17_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu17_wayG_upd select + congr_cl17_wG_d(4) <= (congr_cl17_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu17_wayG_upd select + congr_cl17_wG_d(5) <= (congr_cl17_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu18_wayG_upd select + congr_cl18_wG_d(0) <= (congr_cl18_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu18_wayG_upd select + congr_cl18_wG_d(1) <= (congr_cl18_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu18_wayG_upd select + congr_cl18_wG_d(2) <= (congr_cl18_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu18_wayG_upd select + congr_cl18_wG_d(3) <= (congr_cl18_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu18_wayG_upd select + congr_cl18_wG_d(4) <= (congr_cl18_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu18_wayG_upd select + congr_cl18_wG_d(5) <= (congr_cl18_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu19_wayG_upd select + congr_cl19_wG_d(0) <= (congr_cl19_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu19_wayG_upd select + congr_cl19_wG_d(1) <= (congr_cl19_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu19_wayG_upd select + congr_cl19_wG_d(2) <= (congr_cl19_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu19_wayG_upd select + congr_cl19_wG_d(3) <= (congr_cl19_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu19_wayG_upd select + congr_cl19_wG_d(4) <= (congr_cl19_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu19_wayG_upd select + congr_cl19_wG_d(5) <= (congr_cl19_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu20_wayG_upd select + congr_cl20_wG_d(0) <= (congr_cl20_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu20_wayG_upd select + congr_cl20_wG_d(1) <= (congr_cl20_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu20_wayG_upd select + congr_cl20_wG_d(2) <= (congr_cl20_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu20_wayG_upd select + congr_cl20_wG_d(3) <= (congr_cl20_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu20_wayG_upd select + congr_cl20_wG_d(4) <= (congr_cl20_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu20_wayG_upd select + congr_cl20_wG_d(5) <= (congr_cl20_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu21_wayG_upd select + congr_cl21_wG_d(0) <= (congr_cl21_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu21_wayG_upd select + congr_cl21_wG_d(1) <= (congr_cl21_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu21_wayG_upd select + congr_cl21_wG_d(2) <= (congr_cl21_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu21_wayG_upd select + congr_cl21_wG_d(3) <= (congr_cl21_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu21_wayG_upd select + congr_cl21_wG_d(4) <= (congr_cl21_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu21_wayG_upd select + congr_cl21_wG_d(5) <= (congr_cl21_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu22_wayG_upd select + congr_cl22_wG_d(0) <= (congr_cl22_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu22_wayG_upd select + congr_cl22_wG_d(1) <= (congr_cl22_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu22_wayG_upd select + congr_cl22_wG_d(2) <= (congr_cl22_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu22_wayG_upd select + congr_cl22_wG_d(3) <= (congr_cl22_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu22_wayG_upd select + congr_cl22_wG_d(4) <= (congr_cl22_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu22_wayG_upd select + congr_cl22_wG_d(5) <= (congr_cl22_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu23_wayG_upd select + congr_cl23_wG_d(0) <= (congr_cl23_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu23_wayG_upd select + congr_cl23_wG_d(1) <= (congr_cl23_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu23_wayG_upd select + congr_cl23_wG_d(2) <= (congr_cl23_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu23_wayG_upd select + congr_cl23_wG_d(3) <= (congr_cl23_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu23_wayG_upd select + congr_cl23_wG_d(4) <= (congr_cl23_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu23_wayG_upd select + congr_cl23_wG_d(5) <= (congr_cl23_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu24_wayG_upd select + congr_cl24_wG_d(0) <= (congr_cl24_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu24_wayG_upd select + congr_cl24_wG_d(1) <= (congr_cl24_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu24_wayG_upd select + congr_cl24_wG_d(2) <= (congr_cl24_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu24_wayG_upd select + congr_cl24_wG_d(3) <= (congr_cl24_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu24_wayG_upd select + congr_cl24_wG_d(4) <= (congr_cl24_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu24_wayG_upd select + congr_cl24_wG_d(5) <= (congr_cl24_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu25_wayG_upd select + congr_cl25_wG_d(0) <= (congr_cl25_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu25_wayG_upd select + congr_cl25_wG_d(1) <= (congr_cl25_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu25_wayG_upd select + congr_cl25_wG_d(2) <= (congr_cl25_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu25_wayG_upd select + congr_cl25_wG_d(3) <= (congr_cl25_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu25_wayG_upd select + congr_cl25_wG_d(4) <= (congr_cl25_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu25_wayG_upd select + congr_cl25_wG_d(5) <= (congr_cl25_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu26_wayG_upd select + congr_cl26_wG_d(0) <= (congr_cl26_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu26_wayG_upd select + congr_cl26_wG_d(1) <= (congr_cl26_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu26_wayG_upd select + congr_cl26_wG_d(2) <= (congr_cl26_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu26_wayG_upd select + congr_cl26_wG_d(3) <= (congr_cl26_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu26_wayG_upd select + congr_cl26_wG_d(4) <= (congr_cl26_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu26_wayG_upd select + congr_cl26_wG_d(5) <= (congr_cl26_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu27_wayG_upd select + congr_cl27_wG_d(0) <= (congr_cl27_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu27_wayG_upd select + congr_cl27_wG_d(1) <= (congr_cl27_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu27_wayG_upd select + congr_cl27_wG_d(2) <= (congr_cl27_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu27_wayG_upd select + congr_cl27_wG_d(3) <= (congr_cl27_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu27_wayG_upd select + congr_cl27_wG_d(4) <= (congr_cl27_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu27_wayG_upd select + congr_cl27_wG_d(5) <= (congr_cl27_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu28_wayG_upd select + congr_cl28_wG_d(0) <= (congr_cl28_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu28_wayG_upd select + congr_cl28_wG_d(1) <= (congr_cl28_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu28_wayG_upd select + congr_cl28_wG_d(2) <= (congr_cl28_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu28_wayG_upd select + congr_cl28_wG_d(3) <= (congr_cl28_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu28_wayG_upd select + congr_cl28_wG_d(4) <= (congr_cl28_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu28_wayG_upd select + congr_cl28_wG_d(5) <= (congr_cl28_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu29_wayG_upd select + congr_cl29_wG_d(0) <= (congr_cl29_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu29_wayG_upd select + congr_cl29_wG_d(1) <= (congr_cl29_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu29_wayG_upd select + congr_cl29_wG_d(2) <= (congr_cl29_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu29_wayG_upd select + congr_cl29_wG_d(3) <= (congr_cl29_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu29_wayG_upd select + congr_cl29_wG_d(4) <= (congr_cl29_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu29_wayG_upd select + congr_cl29_wG_d(5) <= (congr_cl29_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu30_wayG_upd select + congr_cl30_wG_d(0) <= (congr_cl30_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu30_wayG_upd select + congr_cl30_wG_d(1) <= (congr_cl30_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu30_wayG_upd select + congr_cl30_wG_d(2) <= (congr_cl30_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu30_wayG_upd select + congr_cl30_wG_d(3) <= (congr_cl30_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu30_wayG_upd select + congr_cl30_wG_d(4) <= (congr_cl30_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu30_wayG_upd select + congr_cl30_wG_d(5) <= (congr_cl30_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu31_wayG_upd select + congr_cl31_wG_d(0) <= (congr_cl31_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu31_wayG_upd select + congr_cl31_wG_d(1) <= (congr_cl31_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu31_wayG_upd select + congr_cl31_wG_d(2) <= (congr_cl31_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu31_wayG_upd select + congr_cl31_wG_d(3) <= (congr_cl31_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu31_wayG_upd select + congr_cl31_wG_d(4) <= (congr_cl31_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu31_wayG_upd select + congr_cl31_wG_d(5) <= (congr_cl31_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu0_wayH_upd select + congr_cl0_wH_d(0) <= (congr_cl0_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu0_wayH_upd select + congr_cl0_wH_d(1) <= (congr_cl0_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu0_wayH_upd select + congr_cl0_wH_d(2) <= (congr_cl0_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu0_wayH_upd select + congr_cl0_wH_d(3) <= (congr_cl0_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu0_wayH_upd select + congr_cl0_wH_d(4) <= (congr_cl0_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu0_wayH_upd select + congr_cl0_wH_d(5) <= (congr_cl0_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu1_wayH_upd select + congr_cl1_wH_d(0) <= (congr_cl1_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu1_wayH_upd select + congr_cl1_wH_d(1) <= (congr_cl1_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu1_wayH_upd select + congr_cl1_wH_d(2) <= (congr_cl1_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu1_wayH_upd select + congr_cl1_wH_d(3) <= (congr_cl1_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu1_wayH_upd select + congr_cl1_wH_d(4) <= (congr_cl1_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu1_wayH_upd select + congr_cl1_wH_d(5) <= (congr_cl1_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu2_wayH_upd select + congr_cl2_wH_d(0) <= (congr_cl2_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu2_wayH_upd select + congr_cl2_wH_d(1) <= (congr_cl2_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu2_wayH_upd select + congr_cl2_wH_d(2) <= (congr_cl2_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu2_wayH_upd select + congr_cl2_wH_d(3) <= (congr_cl2_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu2_wayH_upd select + congr_cl2_wH_d(4) <= (congr_cl2_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu2_wayH_upd select + congr_cl2_wH_d(5) <= (congr_cl2_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu3_wayH_upd select + congr_cl3_wH_d(0) <= (congr_cl3_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu3_wayH_upd select + congr_cl3_wH_d(1) <= (congr_cl3_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu3_wayH_upd select + congr_cl3_wH_d(2) <= (congr_cl3_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu3_wayH_upd select + congr_cl3_wH_d(3) <= (congr_cl3_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu3_wayH_upd select + congr_cl3_wH_d(4) <= (congr_cl3_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu3_wayH_upd select + congr_cl3_wH_d(5) <= (congr_cl3_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu4_wayH_upd select + congr_cl4_wH_d(0) <= (congr_cl4_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu4_wayH_upd select + congr_cl4_wH_d(1) <= (congr_cl4_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu4_wayH_upd select + congr_cl4_wH_d(2) <= (congr_cl4_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu4_wayH_upd select + congr_cl4_wH_d(3) <= (congr_cl4_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu4_wayH_upd select + congr_cl4_wH_d(4) <= (congr_cl4_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu4_wayH_upd select + congr_cl4_wH_d(5) <= (congr_cl4_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu5_wayH_upd select + congr_cl5_wH_d(0) <= (congr_cl5_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu5_wayH_upd select + congr_cl5_wH_d(1) <= (congr_cl5_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu5_wayH_upd select + congr_cl5_wH_d(2) <= (congr_cl5_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu5_wayH_upd select + congr_cl5_wH_d(3) <= (congr_cl5_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu5_wayH_upd select + congr_cl5_wH_d(4) <= (congr_cl5_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu5_wayH_upd select + congr_cl5_wH_d(5) <= (congr_cl5_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu6_wayH_upd select + congr_cl6_wH_d(0) <= (congr_cl6_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu6_wayH_upd select + congr_cl6_wH_d(1) <= (congr_cl6_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu6_wayH_upd select + congr_cl6_wH_d(2) <= (congr_cl6_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu6_wayH_upd select + congr_cl6_wH_d(3) <= (congr_cl6_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu6_wayH_upd select + congr_cl6_wH_d(4) <= (congr_cl6_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu6_wayH_upd select + congr_cl6_wH_d(5) <= (congr_cl6_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu7_wayH_upd select + congr_cl7_wH_d(0) <= (congr_cl7_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu7_wayH_upd select + congr_cl7_wH_d(1) <= (congr_cl7_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu7_wayH_upd select + congr_cl7_wH_d(2) <= (congr_cl7_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu7_wayH_upd select + congr_cl7_wH_d(3) <= (congr_cl7_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu7_wayH_upd select + congr_cl7_wH_d(4) <= (congr_cl7_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu7_wayH_upd select + congr_cl7_wH_d(5) <= (congr_cl7_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu8_wayH_upd select + congr_cl8_wH_d(0) <= (congr_cl8_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu8_wayH_upd select + congr_cl8_wH_d(1) <= (congr_cl8_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu8_wayH_upd select + congr_cl8_wH_d(2) <= (congr_cl8_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu8_wayH_upd select + congr_cl8_wH_d(3) <= (congr_cl8_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu8_wayH_upd select + congr_cl8_wH_d(4) <= (congr_cl8_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu8_wayH_upd select + congr_cl8_wH_d(5) <= (congr_cl8_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu9_wayH_upd select + congr_cl9_wH_d(0) <= (congr_cl9_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu9_wayH_upd select + congr_cl9_wH_d(1) <= (congr_cl9_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu9_wayH_upd select + congr_cl9_wH_d(2) <= (congr_cl9_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu9_wayH_upd select + congr_cl9_wH_d(3) <= (congr_cl9_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu9_wayH_upd select + congr_cl9_wH_d(4) <= (congr_cl9_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu9_wayH_upd select + congr_cl9_wH_d(5) <= (congr_cl9_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu10_wayH_upd select + congr_cl10_wH_d(0) <= (congr_cl10_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu10_wayH_upd select + congr_cl10_wH_d(1) <= (congr_cl10_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu10_wayH_upd select + congr_cl10_wH_d(2) <= (congr_cl10_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu10_wayH_upd select + congr_cl10_wH_d(3) <= (congr_cl10_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu10_wayH_upd select + congr_cl10_wH_d(4) <= (congr_cl10_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu10_wayH_upd select + congr_cl10_wH_d(5) <= (congr_cl10_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu11_wayH_upd select + congr_cl11_wH_d(0) <= (congr_cl11_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu11_wayH_upd select + congr_cl11_wH_d(1) <= (congr_cl11_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu11_wayH_upd select + congr_cl11_wH_d(2) <= (congr_cl11_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu11_wayH_upd select + congr_cl11_wH_d(3) <= (congr_cl11_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu11_wayH_upd select + congr_cl11_wH_d(4) <= (congr_cl11_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu11_wayH_upd select + congr_cl11_wH_d(5) <= (congr_cl11_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu12_wayH_upd select + congr_cl12_wH_d(0) <= (congr_cl12_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu12_wayH_upd select + congr_cl12_wH_d(1) <= (congr_cl12_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu12_wayH_upd select + congr_cl12_wH_d(2) <= (congr_cl12_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu12_wayH_upd select + congr_cl12_wH_d(3) <= (congr_cl12_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu12_wayH_upd select + congr_cl12_wH_d(4) <= (congr_cl12_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu12_wayH_upd select + congr_cl12_wH_d(5) <= (congr_cl12_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu13_wayH_upd select + congr_cl13_wH_d(0) <= (congr_cl13_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu13_wayH_upd select + congr_cl13_wH_d(1) <= (congr_cl13_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu13_wayH_upd select + congr_cl13_wH_d(2) <= (congr_cl13_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu13_wayH_upd select + congr_cl13_wH_d(3) <= (congr_cl13_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu13_wayH_upd select + congr_cl13_wH_d(4) <= (congr_cl13_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu13_wayH_upd select + congr_cl13_wH_d(5) <= (congr_cl13_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu14_wayH_upd select + congr_cl14_wH_d(0) <= (congr_cl14_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu14_wayH_upd select + congr_cl14_wH_d(1) <= (congr_cl14_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu14_wayH_upd select + congr_cl14_wH_d(2) <= (congr_cl14_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu14_wayH_upd select + congr_cl14_wH_d(3) <= (congr_cl14_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu14_wayH_upd select + congr_cl14_wH_d(4) <= (congr_cl14_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu14_wayH_upd select + congr_cl14_wH_d(5) <= (congr_cl14_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu15_wayH_upd select + congr_cl15_wH_d(0) <= (congr_cl15_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu15_wayH_upd select + congr_cl15_wH_d(1) <= (congr_cl15_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu15_wayH_upd select + congr_cl15_wH_d(2) <= (congr_cl15_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu15_wayH_upd select + congr_cl15_wH_d(3) <= (congr_cl15_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu15_wayH_upd select + congr_cl15_wH_d(4) <= (congr_cl15_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu15_wayH_upd select + congr_cl15_wH_d(5) <= (congr_cl15_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu16_wayH_upd select + congr_cl16_wH_d(0) <= (congr_cl16_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu16_wayH_upd select + congr_cl16_wH_d(1) <= (congr_cl16_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu16_wayH_upd select + congr_cl16_wH_d(2) <= (congr_cl16_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu16_wayH_upd select + congr_cl16_wH_d(3) <= (congr_cl16_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu16_wayH_upd select + congr_cl16_wH_d(4) <= (congr_cl16_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu16_wayH_upd select + congr_cl16_wH_d(5) <= (congr_cl16_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu17_wayH_upd select + congr_cl17_wH_d(0) <= (congr_cl17_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu17_wayH_upd select + congr_cl17_wH_d(1) <= (congr_cl17_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu17_wayH_upd select + congr_cl17_wH_d(2) <= (congr_cl17_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu17_wayH_upd select + congr_cl17_wH_d(3) <= (congr_cl17_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu17_wayH_upd select + congr_cl17_wH_d(4) <= (congr_cl17_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu17_wayH_upd select + congr_cl17_wH_d(5) <= (congr_cl17_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu18_wayH_upd select + congr_cl18_wH_d(0) <= (congr_cl18_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu18_wayH_upd select + congr_cl18_wH_d(1) <= (congr_cl18_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu18_wayH_upd select + congr_cl18_wH_d(2) <= (congr_cl18_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu18_wayH_upd select + congr_cl18_wH_d(3) <= (congr_cl18_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu18_wayH_upd select + congr_cl18_wH_d(4) <= (congr_cl18_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu18_wayH_upd select + congr_cl18_wH_d(5) <= (congr_cl18_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu19_wayH_upd select + congr_cl19_wH_d(0) <= (congr_cl19_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu19_wayH_upd select + congr_cl19_wH_d(1) <= (congr_cl19_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu19_wayH_upd select + congr_cl19_wH_d(2) <= (congr_cl19_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu19_wayH_upd select + congr_cl19_wH_d(3) <= (congr_cl19_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu19_wayH_upd select + congr_cl19_wH_d(4) <= (congr_cl19_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu19_wayH_upd select + congr_cl19_wH_d(5) <= (congr_cl19_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu20_wayH_upd select + congr_cl20_wH_d(0) <= (congr_cl20_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu20_wayH_upd select + congr_cl20_wH_d(1) <= (congr_cl20_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu20_wayH_upd select + congr_cl20_wH_d(2) <= (congr_cl20_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu20_wayH_upd select + congr_cl20_wH_d(3) <= (congr_cl20_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu20_wayH_upd select + congr_cl20_wH_d(4) <= (congr_cl20_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu20_wayH_upd select + congr_cl20_wH_d(5) <= (congr_cl20_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu21_wayH_upd select + congr_cl21_wH_d(0) <= (congr_cl21_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu21_wayH_upd select + congr_cl21_wH_d(1) <= (congr_cl21_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu21_wayH_upd select + congr_cl21_wH_d(2) <= (congr_cl21_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu21_wayH_upd select + congr_cl21_wH_d(3) <= (congr_cl21_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu21_wayH_upd select + congr_cl21_wH_d(4) <= (congr_cl21_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu21_wayH_upd select + congr_cl21_wH_d(5) <= (congr_cl21_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu22_wayH_upd select + congr_cl22_wH_d(0) <= (congr_cl22_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu22_wayH_upd select + congr_cl22_wH_d(1) <= (congr_cl22_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu22_wayH_upd select + congr_cl22_wH_d(2) <= (congr_cl22_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu22_wayH_upd select + congr_cl22_wH_d(3) <= (congr_cl22_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu22_wayH_upd select + congr_cl22_wH_d(4) <= (congr_cl22_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu22_wayH_upd select + congr_cl22_wH_d(5) <= (congr_cl22_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu23_wayH_upd select + congr_cl23_wH_d(0) <= (congr_cl23_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu23_wayH_upd select + congr_cl23_wH_d(1) <= (congr_cl23_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu23_wayH_upd select + congr_cl23_wH_d(2) <= (congr_cl23_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu23_wayH_upd select + congr_cl23_wH_d(3) <= (congr_cl23_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu23_wayH_upd select + congr_cl23_wH_d(4) <= (congr_cl23_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu23_wayH_upd select + congr_cl23_wH_d(5) <= (congr_cl23_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu24_wayH_upd select + congr_cl24_wH_d(0) <= (congr_cl24_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu24_wayH_upd select + congr_cl24_wH_d(1) <= (congr_cl24_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu24_wayH_upd select + congr_cl24_wH_d(2) <= (congr_cl24_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu24_wayH_upd select + congr_cl24_wH_d(3) <= (congr_cl24_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu24_wayH_upd select + congr_cl24_wH_d(4) <= (congr_cl24_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu24_wayH_upd select + congr_cl24_wH_d(5) <= (congr_cl24_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu25_wayH_upd select + congr_cl25_wH_d(0) <= (congr_cl25_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu25_wayH_upd select + congr_cl25_wH_d(1) <= (congr_cl25_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu25_wayH_upd select + congr_cl25_wH_d(2) <= (congr_cl25_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu25_wayH_upd select + congr_cl25_wH_d(3) <= (congr_cl25_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu25_wayH_upd select + congr_cl25_wH_d(4) <= (congr_cl25_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu25_wayH_upd select + congr_cl25_wH_d(5) <= (congr_cl25_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu26_wayH_upd select + congr_cl26_wH_d(0) <= (congr_cl26_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu26_wayH_upd select + congr_cl26_wH_d(1) <= (congr_cl26_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu26_wayH_upd select + congr_cl26_wH_d(2) <= (congr_cl26_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu26_wayH_upd select + congr_cl26_wH_d(3) <= (congr_cl26_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu26_wayH_upd select + congr_cl26_wH_d(4) <= (congr_cl26_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu26_wayH_upd select + congr_cl26_wH_d(5) <= (congr_cl26_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu27_wayH_upd select + congr_cl27_wH_d(0) <= (congr_cl27_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu27_wayH_upd select + congr_cl27_wH_d(1) <= (congr_cl27_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu27_wayH_upd select + congr_cl27_wH_d(2) <= (congr_cl27_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu27_wayH_upd select + congr_cl27_wH_d(3) <= (congr_cl27_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu27_wayH_upd select + congr_cl27_wH_d(4) <= (congr_cl27_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu27_wayH_upd select + congr_cl27_wH_d(5) <= (congr_cl27_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu28_wayH_upd select + congr_cl28_wH_d(0) <= (congr_cl28_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu28_wayH_upd select + congr_cl28_wH_d(1) <= (congr_cl28_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu28_wayH_upd select + congr_cl28_wH_d(2) <= (congr_cl28_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu28_wayH_upd select + congr_cl28_wH_d(3) <= (congr_cl28_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu28_wayH_upd select + congr_cl28_wH_d(4) <= (congr_cl28_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu28_wayH_upd select + congr_cl28_wH_d(5) <= (congr_cl28_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu29_wayH_upd select + congr_cl29_wH_d(0) <= (congr_cl29_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu29_wayH_upd select + congr_cl29_wH_d(1) <= (congr_cl29_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu29_wayH_upd select + congr_cl29_wH_d(2) <= (congr_cl29_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu29_wayH_upd select + congr_cl29_wH_d(3) <= (congr_cl29_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu29_wayH_upd select + congr_cl29_wH_d(4) <= (congr_cl29_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu29_wayH_upd select + congr_cl29_wH_d(5) <= (congr_cl29_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu30_wayH_upd select + congr_cl30_wH_d(0) <= (congr_cl30_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu30_wayH_upd select + congr_cl30_wH_d(1) <= (congr_cl30_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu30_wayH_upd select + congr_cl30_wH_d(2) <= (congr_cl30_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu30_wayH_upd select + congr_cl30_wH_d(3) <= (congr_cl30_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu30_wayH_upd select + congr_cl30_wH_d(4) <= (congr_cl30_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu30_wayH_upd select + congr_cl30_wH_d(5) <= (congr_cl30_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu31_wayH_upd select + congr_cl31_wH_d(0) <= (congr_cl31_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu31_wayH_upd select + congr_cl31_wH_d(1) <= (congr_cl31_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu31_wayH_upd select + congr_cl31_wH_d(2) <= (congr_cl31_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu31_wayH_upd select + congr_cl31_wH_d(3) <= (congr_cl31_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu31_wayH_upd select + congr_cl31_wH_d(4) <= (congr_cl31_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu31_wayH_upd select + congr_cl31_wH_d(5) <= (congr_cl31_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with stm_upd_watchlost_tid0 select + stm_watchlost(0) <= stm_watchlost_state_q(0) when "00", + binv5_ex5_lost_watch_upd(0) when "01", + rel_lost_watch_upd_q(0) when others; +stm_upd_watchlost_tid0 <= rel_watchlost_upd(0) & ex5_watchlost_upd(0); +with stm_upd_watchlost_tid1 select + stm_watchlost(1) <= stm_watchlost_state_q(1) when "00", + binv5_ex5_lost_watch_upd(1) when "01", + rel_lost_watch_upd_q(1) when others; +stm_upd_watchlost_tid1 <= rel_watchlost_upd(1) & ex5_watchlost_upd(1); +with stm_upd_watchlost_tid2 select + stm_watchlost(2) <= stm_watchlost_state_q(2) when "00", + binv5_ex5_lost_watch_upd(2) when "01", + rel_lost_watch_upd_q(2) when others; +stm_upd_watchlost_tid2 <= rel_watchlost_upd(2) & ex5_watchlost_upd(2); +with stm_upd_watchlost_tid3 select + stm_watchlost(3) <= stm_watchlost_state_q(3) when "00", + binv5_ex5_lost_watch_upd(3) when "01", + rel_lost_watch_upd_q(3) when others; +stm_upd_watchlost_tid3 <= rel_watchlost_upd(3) & ex5_watchlost_upd(3); +rel_watchlost_upd <= rel_lost_watch_upd_q; +ex5_watchlost_upd <= gate(ex5_watchlost_set_q, p0_wren_d) or binv5_inval_watch_val_q or dci_watch_lost; +binv5_ex5_lost_watch_upd <= ex5_lost_watch_upd_q or binv5_inval_watch_val_q or dci_watch_lost; +stm_watchlost_state_d <= stm_watchlost; +my_spare0_latches_d <= not my_spare0_latches_q; + +rel4_l1dump_val_q <= not my_spare1_latches_q(0); +my_spare1_latches_d(0) <= rel3_l1dump_val; +my_spare1_latches_d(1 TO 15) <= not my_spare1_latches_q(1 to 15); + +ex4_way_a_hit <= ex4_way_hit_q(0); +ex4_way_b_hit <= ex4_way_hit_q(1); +ex4_way_c_hit <= ex4_way_hit_q(2); +ex4_way_d_hit <= ex4_way_hit_q(3); +ex4_way_e_hit <= ex4_way_hit_q(4); +ex4_way_f_hit <= ex4_way_hit_q(5); +ex4_way_g_hit <= ex4_way_hit_q(6); +ex4_way_h_hit <= ex4_way_hit_q(7); +ex4_way_a_dir <= ex4_wayA_val_q; +ex4_way_b_dir <= ex4_wayB_val_q; +ex4_way_c_dir <= ex4_wayC_val_q; +ex4_way_d_dir <= ex4_wayD_val_q; +ex4_way_e_dir <= ex4_wayE_val_q; +ex4_way_f_dir <= ex4_wayF_val_q; +ex4_way_g_dir <= ex4_wayG_val_q; +ex4_way_h_dir <= ex4_wayH_val_q; +ex4_ldq_full_flush <= not ex4_ldq_full_flush_b_q; +ex4_snd_ld_l2 <= not ex4_snd_ld_l2_q; +dcarr_up_way_addr <= dcarr_up_way_addr_q; +pe_recov_begin <= not dcpar_err_rec_inprog; +lsu_xu_ex5_cr_rslt <= ex5_cr_watch_q; +rel_way_val_a <= rel_wayA_val(0); +rel_way_lock_a <= rel_wayA_val(1); +rel_way_val_b <= rel_wayB_val(0); +rel_way_lock_b <= rel_wayB_val(1); +rel_way_val_c <= rel_wayC_val(0); +rel_way_lock_c <= rel_wayC_val(1); +rel_way_val_d <= rel_wayD_val(0); +rel_way_lock_d <= rel_wayD_val(1); +rel_way_val_e <= rel_wayE_val(0); +rel_way_lock_e <= rel_wayE_val(1); +rel_way_val_f <= rel_wayF_val(0); +rel_way_lock_f <= rel_wayF_val(1); +rel_way_val_g <= rel_wayG_val(0); +rel_way_lock_g <= rel_wayG_val(1); +rel_way_val_h <= rel_wayH_val(0); +rel_way_lock_h <= rel_wayH_val(1); +lsu_xu_perf_events <= lost_watch_inter_thrd_q & lost_watch_evict_val_q & lost_watch_binv & perf_lsu_evnts_q; +ex3_dir_perr_det <= ex3_dir_perr_val; +ex4_dir_multihit_det <= ex4_dir_multihit_val; +ex4_n_lsu_ddmh_flush <= not ex4_n_lsu_ddmh_flush_b_q; +ex2_lockwatchSet_rel_coll <= rel1_val and (ex2_lock_set or ex2_ldawx_instr) and (rel_congr_cl_q = ex2_congr_cl_q); +ex3_wclr_all_flush <= ex3_wclr_all_upd_q and fxu_pipe_val; +dc_val_dbg_data <= ex4_wayA_val_q & ex4_wayB_val_q & ex4_wayC_val_q & ex4_wayD_val_q & + ex4_wayE_val_q & ex4_wayF_val_q & ex4_wayG_val_q & ex4_wayH_val_q & + rel_wayA_val_stg_q & rel_wayB_val_stg_q & rel_wayC_val_stg_q & rel_wayD_val_stg_q & + rel_wayE_val_stg_q & rel_wayF_val_stg_q & rel_wayG_val_stg_q & rel_wayH_val_stg_q & + flush_wayA_data_q & flush_wayB_data_q & flush_wayC_data_q & flush_wayD_data_q & + flush_wayE_data_q & flush_wayF_data_q & flush_wayG_data_q & flush_wayH_data_q & + reload_wayA_data_q & reload_wayB_data_q & reload_wayC_data_q & reload_wayD_data_q & + reload_wayE_data_q & reload_wayF_data_q & reload_wayG_data_q & reload_wayH_data_q & + binv_wayA_upd2_q & binv_wayB_upd2_q & binv_wayC_upd2_q & binv_wayD_upd2_q & + binv_wayE_upd2_q & binv_wayF_upd2_q & binv_wayG_upd2_q & binv_wayH_upd2_q & + reload_wayA_upd2_q & reload_wayB_upd2_q & reload_wayC_upd2_q & reload_wayD_upd2_q & + reload_wayE_upd2_q & reload_wayF_upd2_q & reload_wayG_upd2_q & reload_wayH_upd2_q & + ex4_way_hit_q & ex4_congr_cl_q & rel24_congr_cl_q & ex4_instr_enc_q & + rel24_wayA_byp_sel & rel24_wayB_byp_sel & rel24_wayC_byp_sel & rel24_wayD_byp_sel & + rel24_wayE_byp_sel & rel24_wayF_byp_sel & rel24_wayG_byp_sel & rel24_wayH_byp_sel & + ex4_wayA_byp_sel & ex4_wayB_byp_sel & ex4_wayC_byp_sel & ex4_wayD_byp_sel & + ex4_wayE_byp_sel & ex4_wayF_byp_sel & ex4_wayG_byp_sel & ex4_wayH_byp_sel & + ex4_dir_multihit_val & ex4_dir_err_val_q & rel_lost_watch_upd_q & stm_watchlost_state_q & + rel_lock_set_q & rel_watch_set_q & rel_binv_stg4_q & rel4_recirc_val & + ex7_ld_par_err_q & ex9_ld_par_err_q & rel_in_progress_q & dcpar_err_ind_sel_q & + dcpar_err_cntr_q & dcpar_err_push_queue_q & dcpar_err_way_q & dcpar_err_stg2_q & + binv4_ex4_xuop_upd_q; +lsu_xu_spr_xucr0_cslc_xuop <= xucr0_cslc_xuop_q; +lsu_xu_spr_xucr0_cslc_binv <= xucr0_cslc_binv_q; +congr_cl0_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl0_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl0_wA_offset to congr_cl0_wA_offset + congr_cl0_wA_d'length-1), + scout => sov(congr_cl0_wA_offset to congr_cl0_wA_offset + congr_cl0_wA_d'length-1), + din => congr_cl0_wA_d, + dout => congr_cl0_wA_q); +congr_cl0_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl0_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl0_wB_offset to congr_cl0_wB_offset + congr_cl0_wB_d'length-1), + scout => sov(congr_cl0_wB_offset to congr_cl0_wB_offset + congr_cl0_wB_d'length-1), + din => congr_cl0_wB_d, + dout => congr_cl0_wB_q); +congr_cl0_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl0_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl0_wC_offset to congr_cl0_wC_offset + congr_cl0_wC_d'length-1), + scout => sov(congr_cl0_wC_offset to congr_cl0_wC_offset + congr_cl0_wC_d'length-1), + din => congr_cl0_wC_d, + dout => congr_cl0_wC_q); +congr_cl0_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl0_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl0_wD_offset to congr_cl0_wD_offset + congr_cl0_wD_d'length-1), + scout => sov(congr_cl0_wD_offset to congr_cl0_wD_offset + congr_cl0_wD_d'length-1), + din => congr_cl0_wD_d, + dout => congr_cl0_wD_q); +congr_cl0_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl0_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl0_wE_offset to congr_cl0_wE_offset + congr_cl0_wE_d'length-1), + scout => sov(congr_cl0_wE_offset to congr_cl0_wE_offset + congr_cl0_wE_d'length-1), + din => congr_cl0_wE_d, + dout => congr_cl0_wE_q); +congr_cl0_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl0_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl0_wF_offset to congr_cl0_wF_offset + congr_cl0_wF_d'length-1), + scout => sov(congr_cl0_wF_offset to congr_cl0_wF_offset + congr_cl0_wF_d'length-1), + din => congr_cl0_wF_d, + dout => congr_cl0_wF_q); +congr_cl0_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl0_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl0_wG_offset to congr_cl0_wG_offset + congr_cl0_wG_d'length-1), + scout => sov(congr_cl0_wG_offset to congr_cl0_wG_offset + congr_cl0_wG_d'length-1), + din => congr_cl0_wG_d, + dout => congr_cl0_wG_q); +congr_cl0_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl0_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl0_wH_offset to congr_cl0_wH_offset + congr_cl0_wH_d'length-1), + scout => sov(congr_cl0_wH_offset to congr_cl0_wH_offset + congr_cl0_wH_d'length-1), + din => congr_cl0_wH_d, + dout => congr_cl0_wH_q); +congr_cl1_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl1_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl1_wA_offset to congr_cl1_wA_offset + congr_cl1_wA_d'length-1), + scout => sov(congr_cl1_wA_offset to congr_cl1_wA_offset + congr_cl1_wA_d'length-1), + din => congr_cl1_wA_d, + dout => congr_cl1_wA_q); +congr_cl1_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl1_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl1_wB_offset to congr_cl1_wB_offset + congr_cl1_wB_d'length-1), + scout => sov(congr_cl1_wB_offset to congr_cl1_wB_offset + congr_cl1_wB_d'length-1), + din => congr_cl1_wB_d, + dout => congr_cl1_wB_q); +congr_cl1_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl1_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl1_wC_offset to congr_cl1_wC_offset + congr_cl1_wC_d'length-1), + scout => sov(congr_cl1_wC_offset to congr_cl1_wC_offset + congr_cl1_wC_d'length-1), + din => congr_cl1_wC_d, + dout => congr_cl1_wC_q); +congr_cl1_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl1_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl1_wD_offset to congr_cl1_wD_offset + congr_cl1_wD_d'length-1), + scout => sov(congr_cl1_wD_offset to congr_cl1_wD_offset + congr_cl1_wD_d'length-1), + din => congr_cl1_wD_d, + dout => congr_cl1_wD_q); +congr_cl1_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl1_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl1_wE_offset to congr_cl1_wE_offset + congr_cl1_wE_d'length-1), + scout => sov(congr_cl1_wE_offset to congr_cl1_wE_offset + congr_cl1_wE_d'length-1), + din => congr_cl1_wE_d, + dout => congr_cl1_wE_q); +congr_cl1_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl1_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl1_wF_offset to congr_cl1_wF_offset + congr_cl1_wF_d'length-1), + scout => sov(congr_cl1_wF_offset to congr_cl1_wF_offset + congr_cl1_wF_d'length-1), + din => congr_cl1_wF_d, + dout => congr_cl1_wF_q); +congr_cl1_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl1_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl1_wG_offset to congr_cl1_wG_offset + congr_cl1_wG_d'length-1), + scout => sov(congr_cl1_wG_offset to congr_cl1_wG_offset + congr_cl1_wG_d'length-1), + din => congr_cl1_wG_d, + dout => congr_cl1_wG_q); +congr_cl1_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl1_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl1_wH_offset to congr_cl1_wH_offset + congr_cl1_wH_d'length-1), + scout => sov(congr_cl1_wH_offset to congr_cl1_wH_offset + congr_cl1_wH_d'length-1), + din => congr_cl1_wH_d, + dout => congr_cl1_wH_q); +congr_cl2_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl2_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl2_wA_offset to congr_cl2_wA_offset + congr_cl2_wA_d'length-1), + scout => sov(congr_cl2_wA_offset to congr_cl2_wA_offset + congr_cl2_wA_d'length-1), + din => congr_cl2_wA_d, + dout => congr_cl2_wA_q); +congr_cl2_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl2_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl2_wB_offset to congr_cl2_wB_offset + congr_cl2_wB_d'length-1), + scout => sov(congr_cl2_wB_offset to congr_cl2_wB_offset + congr_cl2_wB_d'length-1), + din => congr_cl2_wB_d, + dout => congr_cl2_wB_q); +congr_cl2_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl2_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl2_wC_offset to congr_cl2_wC_offset + congr_cl2_wC_d'length-1), + scout => sov(congr_cl2_wC_offset to congr_cl2_wC_offset + congr_cl2_wC_d'length-1), + din => congr_cl2_wC_d, + dout => congr_cl2_wC_q); +congr_cl2_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl2_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl2_wD_offset to congr_cl2_wD_offset + congr_cl2_wD_d'length-1), + scout => sov(congr_cl2_wD_offset to congr_cl2_wD_offset + congr_cl2_wD_d'length-1), + din => congr_cl2_wD_d, + dout => congr_cl2_wD_q); +congr_cl2_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl2_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl2_wE_offset to congr_cl2_wE_offset + congr_cl2_wE_d'length-1), + scout => sov(congr_cl2_wE_offset to congr_cl2_wE_offset + congr_cl2_wE_d'length-1), + din => congr_cl2_wE_d, + dout => congr_cl2_wE_q); +congr_cl2_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl2_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl2_wF_offset to congr_cl2_wF_offset + congr_cl2_wF_d'length-1), + scout => sov(congr_cl2_wF_offset to congr_cl2_wF_offset + congr_cl2_wF_d'length-1), + din => congr_cl2_wF_d, + dout => congr_cl2_wF_q); +congr_cl2_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl2_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl2_wG_offset to congr_cl2_wG_offset + congr_cl2_wG_d'length-1), + scout => sov(congr_cl2_wG_offset to congr_cl2_wG_offset + congr_cl2_wG_d'length-1), + din => congr_cl2_wG_d, + dout => congr_cl2_wG_q); +congr_cl2_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl2_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl2_wH_offset to congr_cl2_wH_offset + congr_cl2_wH_d'length-1), + scout => sov(congr_cl2_wH_offset to congr_cl2_wH_offset + congr_cl2_wH_d'length-1), + din => congr_cl2_wH_d, + dout => congr_cl2_wH_q); +congr_cl3_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl3_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl3_wA_offset to congr_cl3_wA_offset + congr_cl3_wA_d'length-1), + scout => sov(congr_cl3_wA_offset to congr_cl3_wA_offset + congr_cl3_wA_d'length-1), + din => congr_cl3_wA_d, + dout => congr_cl3_wA_q); +congr_cl3_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl3_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl3_wB_offset to congr_cl3_wB_offset + congr_cl3_wB_d'length-1), + scout => sov(congr_cl3_wB_offset to congr_cl3_wB_offset + congr_cl3_wB_d'length-1), + din => congr_cl3_wB_d, + dout => congr_cl3_wB_q); +congr_cl3_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl3_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl3_wC_offset to congr_cl3_wC_offset + congr_cl3_wC_d'length-1), + scout => sov(congr_cl3_wC_offset to congr_cl3_wC_offset + congr_cl3_wC_d'length-1), + din => congr_cl3_wC_d, + dout => congr_cl3_wC_q); +congr_cl3_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl3_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl3_wD_offset to congr_cl3_wD_offset + congr_cl3_wD_d'length-1), + scout => sov(congr_cl3_wD_offset to congr_cl3_wD_offset + congr_cl3_wD_d'length-1), + din => congr_cl3_wD_d, + dout => congr_cl3_wD_q); +congr_cl3_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl3_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl3_wE_offset to congr_cl3_wE_offset + congr_cl3_wE_d'length-1), + scout => sov(congr_cl3_wE_offset to congr_cl3_wE_offset + congr_cl3_wE_d'length-1), + din => congr_cl3_wE_d, + dout => congr_cl3_wE_q); +congr_cl3_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl3_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl3_wF_offset to congr_cl3_wF_offset + congr_cl3_wF_d'length-1), + scout => sov(congr_cl3_wF_offset to congr_cl3_wF_offset + congr_cl3_wF_d'length-1), + din => congr_cl3_wF_d, + dout => congr_cl3_wF_q); +congr_cl3_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl3_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl3_wG_offset to congr_cl3_wG_offset + congr_cl3_wG_d'length-1), + scout => sov(congr_cl3_wG_offset to congr_cl3_wG_offset + congr_cl3_wG_d'length-1), + din => congr_cl3_wG_d, + dout => congr_cl3_wG_q); +congr_cl3_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl3_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl3_wH_offset to congr_cl3_wH_offset + congr_cl3_wH_d'length-1), + scout => sov(congr_cl3_wH_offset to congr_cl3_wH_offset + congr_cl3_wH_d'length-1), + din => congr_cl3_wH_d, + dout => congr_cl3_wH_q); +congr_cl4_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl4_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl4_wA_offset to congr_cl4_wA_offset + congr_cl4_wA_d'length-1), + scout => sov(congr_cl4_wA_offset to congr_cl4_wA_offset + congr_cl4_wA_d'length-1), + din => congr_cl4_wA_d, + dout => congr_cl4_wA_q); +congr_cl4_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl4_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl4_wB_offset to congr_cl4_wB_offset + congr_cl4_wB_d'length-1), + scout => sov(congr_cl4_wB_offset to congr_cl4_wB_offset + congr_cl4_wB_d'length-1), + din => congr_cl4_wB_d, + dout => congr_cl4_wB_q); +congr_cl4_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl4_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl4_wC_offset to congr_cl4_wC_offset + congr_cl4_wC_d'length-1), + scout => sov(congr_cl4_wC_offset to congr_cl4_wC_offset + congr_cl4_wC_d'length-1), + din => congr_cl4_wC_d, + dout => congr_cl4_wC_q); +congr_cl4_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl4_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl4_wD_offset to congr_cl4_wD_offset + congr_cl4_wD_d'length-1), + scout => sov(congr_cl4_wD_offset to congr_cl4_wD_offset + congr_cl4_wD_d'length-1), + din => congr_cl4_wD_d, + dout => congr_cl4_wD_q); +congr_cl4_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl4_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl4_wE_offset to congr_cl4_wE_offset + congr_cl4_wE_d'length-1), + scout => sov(congr_cl4_wE_offset to congr_cl4_wE_offset + congr_cl4_wE_d'length-1), + din => congr_cl4_wE_d, + dout => congr_cl4_wE_q); +congr_cl4_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl4_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl4_wF_offset to congr_cl4_wF_offset + congr_cl4_wF_d'length-1), + scout => sov(congr_cl4_wF_offset to congr_cl4_wF_offset + congr_cl4_wF_d'length-1), + din => congr_cl4_wF_d, + dout => congr_cl4_wF_q); +congr_cl4_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl4_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl4_wG_offset to congr_cl4_wG_offset + congr_cl4_wG_d'length-1), + scout => sov(congr_cl4_wG_offset to congr_cl4_wG_offset + congr_cl4_wG_d'length-1), + din => congr_cl4_wG_d, + dout => congr_cl4_wG_q); +congr_cl4_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl4_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl4_wH_offset to congr_cl4_wH_offset + congr_cl4_wH_d'length-1), + scout => sov(congr_cl4_wH_offset to congr_cl4_wH_offset + congr_cl4_wH_d'length-1), + din => congr_cl4_wH_d, + dout => congr_cl4_wH_q); +congr_cl5_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl5_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl5_wA_offset to congr_cl5_wA_offset + congr_cl5_wA_d'length-1), + scout => sov(congr_cl5_wA_offset to congr_cl5_wA_offset + congr_cl5_wA_d'length-1), + din => congr_cl5_wA_d, + dout => congr_cl5_wA_q); +congr_cl5_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl5_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl5_wB_offset to congr_cl5_wB_offset + congr_cl5_wB_d'length-1), + scout => sov(congr_cl5_wB_offset to congr_cl5_wB_offset + congr_cl5_wB_d'length-1), + din => congr_cl5_wB_d, + dout => congr_cl5_wB_q); +congr_cl5_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl5_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl5_wC_offset to congr_cl5_wC_offset + congr_cl5_wC_d'length-1), + scout => sov(congr_cl5_wC_offset to congr_cl5_wC_offset + congr_cl5_wC_d'length-1), + din => congr_cl5_wC_d, + dout => congr_cl5_wC_q); +congr_cl5_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl5_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl5_wD_offset to congr_cl5_wD_offset + congr_cl5_wD_d'length-1), + scout => sov(congr_cl5_wD_offset to congr_cl5_wD_offset + congr_cl5_wD_d'length-1), + din => congr_cl5_wD_d, + dout => congr_cl5_wD_q); +congr_cl5_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl5_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl5_wE_offset to congr_cl5_wE_offset + congr_cl5_wE_d'length-1), + scout => sov(congr_cl5_wE_offset to congr_cl5_wE_offset + congr_cl5_wE_d'length-1), + din => congr_cl5_wE_d, + dout => congr_cl5_wE_q); +congr_cl5_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl5_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl5_wF_offset to congr_cl5_wF_offset + congr_cl5_wF_d'length-1), + scout => sov(congr_cl5_wF_offset to congr_cl5_wF_offset + congr_cl5_wF_d'length-1), + din => congr_cl5_wF_d, + dout => congr_cl5_wF_q); +congr_cl5_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl5_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl5_wG_offset to congr_cl5_wG_offset + congr_cl5_wG_d'length-1), + scout => sov(congr_cl5_wG_offset to congr_cl5_wG_offset + congr_cl5_wG_d'length-1), + din => congr_cl5_wG_d, + dout => congr_cl5_wG_q); +congr_cl5_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl5_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl5_wH_offset to congr_cl5_wH_offset + congr_cl5_wH_d'length-1), + scout => sov(congr_cl5_wH_offset to congr_cl5_wH_offset + congr_cl5_wH_d'length-1), + din => congr_cl5_wH_d, + dout => congr_cl5_wH_q); +congr_cl6_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl6_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl6_wA_offset to congr_cl6_wA_offset + congr_cl6_wA_d'length-1), + scout => sov(congr_cl6_wA_offset to congr_cl6_wA_offset + congr_cl6_wA_d'length-1), + din => congr_cl6_wA_d, + dout => congr_cl6_wA_q); +congr_cl6_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl6_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl6_wB_offset to congr_cl6_wB_offset + congr_cl6_wB_d'length-1), + scout => sov(congr_cl6_wB_offset to congr_cl6_wB_offset + congr_cl6_wB_d'length-1), + din => congr_cl6_wB_d, + dout => congr_cl6_wB_q); +congr_cl6_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl6_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl6_wC_offset to congr_cl6_wC_offset + congr_cl6_wC_d'length-1), + scout => sov(congr_cl6_wC_offset to congr_cl6_wC_offset + congr_cl6_wC_d'length-1), + din => congr_cl6_wC_d, + dout => congr_cl6_wC_q); +congr_cl6_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl6_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl6_wD_offset to congr_cl6_wD_offset + congr_cl6_wD_d'length-1), + scout => sov(congr_cl6_wD_offset to congr_cl6_wD_offset + congr_cl6_wD_d'length-1), + din => congr_cl6_wD_d, + dout => congr_cl6_wD_q); +congr_cl6_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl6_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl6_wE_offset to congr_cl6_wE_offset + congr_cl6_wE_d'length-1), + scout => sov(congr_cl6_wE_offset to congr_cl6_wE_offset + congr_cl6_wE_d'length-1), + din => congr_cl6_wE_d, + dout => congr_cl6_wE_q); +congr_cl6_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl6_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl6_wF_offset to congr_cl6_wF_offset + congr_cl6_wF_d'length-1), + scout => sov(congr_cl6_wF_offset to congr_cl6_wF_offset + congr_cl6_wF_d'length-1), + din => congr_cl6_wF_d, + dout => congr_cl6_wF_q); +congr_cl6_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl6_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl6_wG_offset to congr_cl6_wG_offset + congr_cl6_wG_d'length-1), + scout => sov(congr_cl6_wG_offset to congr_cl6_wG_offset + congr_cl6_wG_d'length-1), + din => congr_cl6_wG_d, + dout => congr_cl6_wG_q); +congr_cl6_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl6_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl6_wH_offset to congr_cl6_wH_offset + congr_cl6_wH_d'length-1), + scout => sov(congr_cl6_wH_offset to congr_cl6_wH_offset + congr_cl6_wH_d'length-1), + din => congr_cl6_wH_d, + dout => congr_cl6_wH_q); +congr_cl7_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl7_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl7_wA_offset to congr_cl7_wA_offset + congr_cl7_wA_d'length-1), + scout => sov(congr_cl7_wA_offset to congr_cl7_wA_offset + congr_cl7_wA_d'length-1), + din => congr_cl7_wA_d, + dout => congr_cl7_wA_q); +congr_cl7_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl7_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl7_wB_offset to congr_cl7_wB_offset + congr_cl7_wB_d'length-1), + scout => sov(congr_cl7_wB_offset to congr_cl7_wB_offset + congr_cl7_wB_d'length-1), + din => congr_cl7_wB_d, + dout => congr_cl7_wB_q); +congr_cl7_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl7_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl7_wC_offset to congr_cl7_wC_offset + congr_cl7_wC_d'length-1), + scout => sov(congr_cl7_wC_offset to congr_cl7_wC_offset + congr_cl7_wC_d'length-1), + din => congr_cl7_wC_d, + dout => congr_cl7_wC_q); +congr_cl7_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl7_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl7_wD_offset to congr_cl7_wD_offset + congr_cl7_wD_d'length-1), + scout => sov(congr_cl7_wD_offset to congr_cl7_wD_offset + congr_cl7_wD_d'length-1), + din => congr_cl7_wD_d, + dout => congr_cl7_wD_q); +congr_cl7_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl7_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl7_wE_offset to congr_cl7_wE_offset + congr_cl7_wE_d'length-1), + scout => sov(congr_cl7_wE_offset to congr_cl7_wE_offset + congr_cl7_wE_d'length-1), + din => congr_cl7_wE_d, + dout => congr_cl7_wE_q); +congr_cl7_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl7_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl7_wF_offset to congr_cl7_wF_offset + congr_cl7_wF_d'length-1), + scout => sov(congr_cl7_wF_offset to congr_cl7_wF_offset + congr_cl7_wF_d'length-1), + din => congr_cl7_wF_d, + dout => congr_cl7_wF_q); +congr_cl7_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl7_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl7_wG_offset to congr_cl7_wG_offset + congr_cl7_wG_d'length-1), + scout => sov(congr_cl7_wG_offset to congr_cl7_wG_offset + congr_cl7_wG_d'length-1), + din => congr_cl7_wG_d, + dout => congr_cl7_wG_q); +congr_cl7_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl7_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl7_wH_offset to congr_cl7_wH_offset + congr_cl7_wH_d'length-1), + scout => sov(congr_cl7_wH_offset to congr_cl7_wH_offset + congr_cl7_wH_d'length-1), + din => congr_cl7_wH_d, + dout => congr_cl7_wH_q); +congr_cl8_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl8_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl8_wA_offset to congr_cl8_wA_offset + congr_cl8_wA_d'length-1), + scout => sov(congr_cl8_wA_offset to congr_cl8_wA_offset + congr_cl8_wA_d'length-1), + din => congr_cl8_wA_d, + dout => congr_cl8_wA_q); +congr_cl8_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl8_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl8_wB_offset to congr_cl8_wB_offset + congr_cl8_wB_d'length-1), + scout => sov(congr_cl8_wB_offset to congr_cl8_wB_offset + congr_cl8_wB_d'length-1), + din => congr_cl8_wB_d, + dout => congr_cl8_wB_q); +congr_cl8_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl8_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl8_wC_offset to congr_cl8_wC_offset + congr_cl8_wC_d'length-1), + scout => sov(congr_cl8_wC_offset to congr_cl8_wC_offset + congr_cl8_wC_d'length-1), + din => congr_cl8_wC_d, + dout => congr_cl8_wC_q); +congr_cl8_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl8_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl8_wD_offset to congr_cl8_wD_offset + congr_cl8_wD_d'length-1), + scout => sov(congr_cl8_wD_offset to congr_cl8_wD_offset + congr_cl8_wD_d'length-1), + din => congr_cl8_wD_d, + dout => congr_cl8_wD_q); +congr_cl8_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl8_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl8_wE_offset to congr_cl8_wE_offset + congr_cl8_wE_d'length-1), + scout => sov(congr_cl8_wE_offset to congr_cl8_wE_offset + congr_cl8_wE_d'length-1), + din => congr_cl8_wE_d, + dout => congr_cl8_wE_q); +congr_cl8_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl8_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl8_wF_offset to congr_cl8_wF_offset + congr_cl8_wF_d'length-1), + scout => sov(congr_cl8_wF_offset to congr_cl8_wF_offset + congr_cl8_wF_d'length-1), + din => congr_cl8_wF_d, + dout => congr_cl8_wF_q); +congr_cl8_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl8_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl8_wG_offset to congr_cl8_wG_offset + congr_cl8_wG_d'length-1), + scout => sov(congr_cl8_wG_offset to congr_cl8_wG_offset + congr_cl8_wG_d'length-1), + din => congr_cl8_wG_d, + dout => congr_cl8_wG_q); +congr_cl8_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl8_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl8_wH_offset to congr_cl8_wH_offset + congr_cl8_wH_d'length-1), + scout => sov(congr_cl8_wH_offset to congr_cl8_wH_offset + congr_cl8_wH_d'length-1), + din => congr_cl8_wH_d, + dout => congr_cl8_wH_q); +congr_cl9_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl9_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl9_wA_offset to congr_cl9_wA_offset + congr_cl9_wA_d'length-1), + scout => sov(congr_cl9_wA_offset to congr_cl9_wA_offset + congr_cl9_wA_d'length-1), + din => congr_cl9_wA_d, + dout => congr_cl9_wA_q); +congr_cl9_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl9_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl9_wB_offset to congr_cl9_wB_offset + congr_cl9_wB_d'length-1), + scout => sov(congr_cl9_wB_offset to congr_cl9_wB_offset + congr_cl9_wB_d'length-1), + din => congr_cl9_wB_d, + dout => congr_cl9_wB_q); +congr_cl9_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl9_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl9_wC_offset to congr_cl9_wC_offset + congr_cl9_wC_d'length-1), + scout => sov(congr_cl9_wC_offset to congr_cl9_wC_offset + congr_cl9_wC_d'length-1), + din => congr_cl9_wC_d, + dout => congr_cl9_wC_q); +congr_cl9_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl9_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl9_wD_offset to congr_cl9_wD_offset + congr_cl9_wD_d'length-1), + scout => sov(congr_cl9_wD_offset to congr_cl9_wD_offset + congr_cl9_wD_d'length-1), + din => congr_cl9_wD_d, + dout => congr_cl9_wD_q); +congr_cl9_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl9_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl9_wE_offset to congr_cl9_wE_offset + congr_cl9_wE_d'length-1), + scout => sov(congr_cl9_wE_offset to congr_cl9_wE_offset + congr_cl9_wE_d'length-1), + din => congr_cl9_wE_d, + dout => congr_cl9_wE_q); +congr_cl9_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl9_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl9_wF_offset to congr_cl9_wF_offset + congr_cl9_wF_d'length-1), + scout => sov(congr_cl9_wF_offset to congr_cl9_wF_offset + congr_cl9_wF_d'length-1), + din => congr_cl9_wF_d, + dout => congr_cl9_wF_q); +congr_cl9_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl9_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl9_wG_offset to congr_cl9_wG_offset + congr_cl9_wG_d'length-1), + scout => sov(congr_cl9_wG_offset to congr_cl9_wG_offset + congr_cl9_wG_d'length-1), + din => congr_cl9_wG_d, + dout => congr_cl9_wG_q); +congr_cl9_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl9_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl9_wH_offset to congr_cl9_wH_offset + congr_cl9_wH_d'length-1), + scout => sov(congr_cl9_wH_offset to congr_cl9_wH_offset + congr_cl9_wH_d'length-1), + din => congr_cl9_wH_d, + dout => congr_cl9_wH_q); +congr_cl10_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl10_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl10_wA_offset to congr_cl10_wA_offset + congr_cl10_wA_d'length-1), + scout => sov(congr_cl10_wA_offset to congr_cl10_wA_offset + congr_cl10_wA_d'length-1), + din => congr_cl10_wA_d, + dout => congr_cl10_wA_q); +congr_cl10_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl10_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl10_wB_offset to congr_cl10_wB_offset + congr_cl10_wB_d'length-1), + scout => sov(congr_cl10_wB_offset to congr_cl10_wB_offset + congr_cl10_wB_d'length-1), + din => congr_cl10_wB_d, + dout => congr_cl10_wB_q); +congr_cl10_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl10_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl10_wC_offset to congr_cl10_wC_offset + congr_cl10_wC_d'length-1), + scout => sov(congr_cl10_wC_offset to congr_cl10_wC_offset + congr_cl10_wC_d'length-1), + din => congr_cl10_wC_d, + dout => congr_cl10_wC_q); +congr_cl10_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl10_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl10_wD_offset to congr_cl10_wD_offset + congr_cl10_wD_d'length-1), + scout => sov(congr_cl10_wD_offset to congr_cl10_wD_offset + congr_cl10_wD_d'length-1), + din => congr_cl10_wD_d, + dout => congr_cl10_wD_q); +congr_cl10_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl10_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl10_wE_offset to congr_cl10_wE_offset + congr_cl10_wE_d'length-1), + scout => sov(congr_cl10_wE_offset to congr_cl10_wE_offset + congr_cl10_wE_d'length-1), + din => congr_cl10_wE_d, + dout => congr_cl10_wE_q); +congr_cl10_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl10_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl10_wF_offset to congr_cl10_wF_offset + congr_cl10_wF_d'length-1), + scout => sov(congr_cl10_wF_offset to congr_cl10_wF_offset + congr_cl10_wF_d'length-1), + din => congr_cl10_wF_d, + dout => congr_cl10_wF_q); +congr_cl10_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl10_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl10_wG_offset to congr_cl10_wG_offset + congr_cl10_wG_d'length-1), + scout => sov(congr_cl10_wG_offset to congr_cl10_wG_offset + congr_cl10_wG_d'length-1), + din => congr_cl10_wG_d, + dout => congr_cl10_wG_q); +congr_cl10_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl10_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl10_wH_offset to congr_cl10_wH_offset + congr_cl10_wH_d'length-1), + scout => sov(congr_cl10_wH_offset to congr_cl10_wH_offset + congr_cl10_wH_d'length-1), + din => congr_cl10_wH_d, + dout => congr_cl10_wH_q); +congr_cl11_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl11_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl11_wA_offset to congr_cl11_wA_offset + congr_cl11_wA_d'length-1), + scout => sov(congr_cl11_wA_offset to congr_cl11_wA_offset + congr_cl11_wA_d'length-1), + din => congr_cl11_wA_d, + dout => congr_cl11_wA_q); +congr_cl11_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl11_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl11_wB_offset to congr_cl11_wB_offset + congr_cl11_wB_d'length-1), + scout => sov(congr_cl11_wB_offset to congr_cl11_wB_offset + congr_cl11_wB_d'length-1), + din => congr_cl11_wB_d, + dout => congr_cl11_wB_q); +congr_cl11_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl11_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl11_wC_offset to congr_cl11_wC_offset + congr_cl11_wC_d'length-1), + scout => sov(congr_cl11_wC_offset to congr_cl11_wC_offset + congr_cl11_wC_d'length-1), + din => congr_cl11_wC_d, + dout => congr_cl11_wC_q); +congr_cl11_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl11_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl11_wD_offset to congr_cl11_wD_offset + congr_cl11_wD_d'length-1), + scout => sov(congr_cl11_wD_offset to congr_cl11_wD_offset + congr_cl11_wD_d'length-1), + din => congr_cl11_wD_d, + dout => congr_cl11_wD_q); +congr_cl11_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl11_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl11_wE_offset to congr_cl11_wE_offset + congr_cl11_wE_d'length-1), + scout => sov(congr_cl11_wE_offset to congr_cl11_wE_offset + congr_cl11_wE_d'length-1), + din => congr_cl11_wE_d, + dout => congr_cl11_wE_q); +congr_cl11_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl11_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl11_wF_offset to congr_cl11_wF_offset + congr_cl11_wF_d'length-1), + scout => sov(congr_cl11_wF_offset to congr_cl11_wF_offset + congr_cl11_wF_d'length-1), + din => congr_cl11_wF_d, + dout => congr_cl11_wF_q); +congr_cl11_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl11_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl11_wG_offset to congr_cl11_wG_offset + congr_cl11_wG_d'length-1), + scout => sov(congr_cl11_wG_offset to congr_cl11_wG_offset + congr_cl11_wG_d'length-1), + din => congr_cl11_wG_d, + dout => congr_cl11_wG_q); +congr_cl11_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl11_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl11_wH_offset to congr_cl11_wH_offset + congr_cl11_wH_d'length-1), + scout => sov(congr_cl11_wH_offset to congr_cl11_wH_offset + congr_cl11_wH_d'length-1), + din => congr_cl11_wH_d, + dout => congr_cl11_wH_q); +congr_cl12_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl12_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl12_wA_offset to congr_cl12_wA_offset + congr_cl12_wA_d'length-1), + scout => sov(congr_cl12_wA_offset to congr_cl12_wA_offset + congr_cl12_wA_d'length-1), + din => congr_cl12_wA_d, + dout => congr_cl12_wA_q); +congr_cl12_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl12_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl12_wB_offset to congr_cl12_wB_offset + congr_cl12_wB_d'length-1), + scout => sov(congr_cl12_wB_offset to congr_cl12_wB_offset + congr_cl12_wB_d'length-1), + din => congr_cl12_wB_d, + dout => congr_cl12_wB_q); +congr_cl12_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl12_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl12_wC_offset to congr_cl12_wC_offset + congr_cl12_wC_d'length-1), + scout => sov(congr_cl12_wC_offset to congr_cl12_wC_offset + congr_cl12_wC_d'length-1), + din => congr_cl12_wC_d, + dout => congr_cl12_wC_q); +congr_cl12_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl12_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl12_wD_offset to congr_cl12_wD_offset + congr_cl12_wD_d'length-1), + scout => sov(congr_cl12_wD_offset to congr_cl12_wD_offset + congr_cl12_wD_d'length-1), + din => congr_cl12_wD_d, + dout => congr_cl12_wD_q); +congr_cl12_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl12_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl12_wE_offset to congr_cl12_wE_offset + congr_cl12_wE_d'length-1), + scout => sov(congr_cl12_wE_offset to congr_cl12_wE_offset + congr_cl12_wE_d'length-1), + din => congr_cl12_wE_d, + dout => congr_cl12_wE_q); +congr_cl12_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl12_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl12_wF_offset to congr_cl12_wF_offset + congr_cl12_wF_d'length-1), + scout => sov(congr_cl12_wF_offset to congr_cl12_wF_offset + congr_cl12_wF_d'length-1), + din => congr_cl12_wF_d, + dout => congr_cl12_wF_q); +congr_cl12_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl12_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl12_wG_offset to congr_cl12_wG_offset + congr_cl12_wG_d'length-1), + scout => sov(congr_cl12_wG_offset to congr_cl12_wG_offset + congr_cl12_wG_d'length-1), + din => congr_cl12_wG_d, + dout => congr_cl12_wG_q); +congr_cl12_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl12_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl12_wH_offset to congr_cl12_wH_offset + congr_cl12_wH_d'length-1), + scout => sov(congr_cl12_wH_offset to congr_cl12_wH_offset + congr_cl12_wH_d'length-1), + din => congr_cl12_wH_d, + dout => congr_cl12_wH_q); +congr_cl13_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl13_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl13_wA_offset to congr_cl13_wA_offset + congr_cl13_wA_d'length-1), + scout => sov(congr_cl13_wA_offset to congr_cl13_wA_offset + congr_cl13_wA_d'length-1), + din => congr_cl13_wA_d, + dout => congr_cl13_wA_q); +congr_cl13_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl13_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl13_wB_offset to congr_cl13_wB_offset + congr_cl13_wB_d'length-1), + scout => sov(congr_cl13_wB_offset to congr_cl13_wB_offset + congr_cl13_wB_d'length-1), + din => congr_cl13_wB_d, + dout => congr_cl13_wB_q); +congr_cl13_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl13_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl13_wC_offset to congr_cl13_wC_offset + congr_cl13_wC_d'length-1), + scout => sov(congr_cl13_wC_offset to congr_cl13_wC_offset + congr_cl13_wC_d'length-1), + din => congr_cl13_wC_d, + dout => congr_cl13_wC_q); +congr_cl13_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl13_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl13_wD_offset to congr_cl13_wD_offset + congr_cl13_wD_d'length-1), + scout => sov(congr_cl13_wD_offset to congr_cl13_wD_offset + congr_cl13_wD_d'length-1), + din => congr_cl13_wD_d, + dout => congr_cl13_wD_q); +congr_cl13_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl13_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl13_wE_offset to congr_cl13_wE_offset + congr_cl13_wE_d'length-1), + scout => sov(congr_cl13_wE_offset to congr_cl13_wE_offset + congr_cl13_wE_d'length-1), + din => congr_cl13_wE_d, + dout => congr_cl13_wE_q); +congr_cl13_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl13_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl13_wF_offset to congr_cl13_wF_offset + congr_cl13_wF_d'length-1), + scout => sov(congr_cl13_wF_offset to congr_cl13_wF_offset + congr_cl13_wF_d'length-1), + din => congr_cl13_wF_d, + dout => congr_cl13_wF_q); +congr_cl13_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl13_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl13_wG_offset to congr_cl13_wG_offset + congr_cl13_wG_d'length-1), + scout => sov(congr_cl13_wG_offset to congr_cl13_wG_offset + congr_cl13_wG_d'length-1), + din => congr_cl13_wG_d, + dout => congr_cl13_wG_q); +congr_cl13_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl13_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl13_wH_offset to congr_cl13_wH_offset + congr_cl13_wH_d'length-1), + scout => sov(congr_cl13_wH_offset to congr_cl13_wH_offset + congr_cl13_wH_d'length-1), + din => congr_cl13_wH_d, + dout => congr_cl13_wH_q); +congr_cl14_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl14_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl14_wA_offset to congr_cl14_wA_offset + congr_cl14_wA_d'length-1), + scout => sov(congr_cl14_wA_offset to congr_cl14_wA_offset + congr_cl14_wA_d'length-1), + din => congr_cl14_wA_d, + dout => congr_cl14_wA_q); +congr_cl14_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl14_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl14_wB_offset to congr_cl14_wB_offset + congr_cl14_wB_d'length-1), + scout => sov(congr_cl14_wB_offset to congr_cl14_wB_offset + congr_cl14_wB_d'length-1), + din => congr_cl14_wB_d, + dout => congr_cl14_wB_q); +congr_cl14_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl14_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl14_wC_offset to congr_cl14_wC_offset + congr_cl14_wC_d'length-1), + scout => sov(congr_cl14_wC_offset to congr_cl14_wC_offset + congr_cl14_wC_d'length-1), + din => congr_cl14_wC_d, + dout => congr_cl14_wC_q); +congr_cl14_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl14_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl14_wD_offset to congr_cl14_wD_offset + congr_cl14_wD_d'length-1), + scout => sov(congr_cl14_wD_offset to congr_cl14_wD_offset + congr_cl14_wD_d'length-1), + din => congr_cl14_wD_d, + dout => congr_cl14_wD_q); +congr_cl14_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl14_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl14_wE_offset to congr_cl14_wE_offset + congr_cl14_wE_d'length-1), + scout => sov(congr_cl14_wE_offset to congr_cl14_wE_offset + congr_cl14_wE_d'length-1), + din => congr_cl14_wE_d, + dout => congr_cl14_wE_q); +congr_cl14_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl14_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl14_wF_offset to congr_cl14_wF_offset + congr_cl14_wF_d'length-1), + scout => sov(congr_cl14_wF_offset to congr_cl14_wF_offset + congr_cl14_wF_d'length-1), + din => congr_cl14_wF_d, + dout => congr_cl14_wF_q); +congr_cl14_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl14_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl14_wG_offset to congr_cl14_wG_offset + congr_cl14_wG_d'length-1), + scout => sov(congr_cl14_wG_offset to congr_cl14_wG_offset + congr_cl14_wG_d'length-1), + din => congr_cl14_wG_d, + dout => congr_cl14_wG_q); +congr_cl14_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl14_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl14_wH_offset to congr_cl14_wH_offset + congr_cl14_wH_d'length-1), + scout => sov(congr_cl14_wH_offset to congr_cl14_wH_offset + congr_cl14_wH_d'length-1), + din => congr_cl14_wH_d, + dout => congr_cl14_wH_q); +congr_cl15_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl15_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl15_wA_offset to congr_cl15_wA_offset + congr_cl15_wA_d'length-1), + scout => sov(congr_cl15_wA_offset to congr_cl15_wA_offset + congr_cl15_wA_d'length-1), + din => congr_cl15_wA_d, + dout => congr_cl15_wA_q); +congr_cl15_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl15_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl15_wB_offset to congr_cl15_wB_offset + congr_cl15_wB_d'length-1), + scout => sov(congr_cl15_wB_offset to congr_cl15_wB_offset + congr_cl15_wB_d'length-1), + din => congr_cl15_wB_d, + dout => congr_cl15_wB_q); +congr_cl15_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl15_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl15_wC_offset to congr_cl15_wC_offset + congr_cl15_wC_d'length-1), + scout => sov(congr_cl15_wC_offset to congr_cl15_wC_offset + congr_cl15_wC_d'length-1), + din => congr_cl15_wC_d, + dout => congr_cl15_wC_q); +congr_cl15_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl15_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl15_wD_offset to congr_cl15_wD_offset + congr_cl15_wD_d'length-1), + scout => sov(congr_cl15_wD_offset to congr_cl15_wD_offset + congr_cl15_wD_d'length-1), + din => congr_cl15_wD_d, + dout => congr_cl15_wD_q); +congr_cl15_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl15_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl15_wE_offset to congr_cl15_wE_offset + congr_cl15_wE_d'length-1), + scout => sov(congr_cl15_wE_offset to congr_cl15_wE_offset + congr_cl15_wE_d'length-1), + din => congr_cl15_wE_d, + dout => congr_cl15_wE_q); +congr_cl15_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl15_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl15_wF_offset to congr_cl15_wF_offset + congr_cl15_wF_d'length-1), + scout => sov(congr_cl15_wF_offset to congr_cl15_wF_offset + congr_cl15_wF_d'length-1), + din => congr_cl15_wF_d, + dout => congr_cl15_wF_q); +congr_cl15_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl15_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl15_wG_offset to congr_cl15_wG_offset + congr_cl15_wG_d'length-1), + scout => sov(congr_cl15_wG_offset to congr_cl15_wG_offset + congr_cl15_wG_d'length-1), + din => congr_cl15_wG_d, + dout => congr_cl15_wG_q); +congr_cl15_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl15_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl15_wH_offset to congr_cl15_wH_offset + congr_cl15_wH_d'length-1), + scout => sov(congr_cl15_wH_offset to congr_cl15_wH_offset + congr_cl15_wH_d'length-1), + din => congr_cl15_wH_d, + dout => congr_cl15_wH_q); +congr_cl16_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl16_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl16_wA_offset to congr_cl16_wA_offset + congr_cl16_wA_d'length-1), + scout => sov(congr_cl16_wA_offset to congr_cl16_wA_offset + congr_cl16_wA_d'length-1), + din => congr_cl16_wA_d, + dout => congr_cl16_wA_q); +congr_cl16_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl16_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl16_wB_offset to congr_cl16_wB_offset + congr_cl16_wB_d'length-1), + scout => sov(congr_cl16_wB_offset to congr_cl16_wB_offset + congr_cl16_wB_d'length-1), + din => congr_cl16_wB_d, + dout => congr_cl16_wB_q); +congr_cl16_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl16_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl16_wC_offset to congr_cl16_wC_offset + congr_cl16_wC_d'length-1), + scout => sov(congr_cl16_wC_offset to congr_cl16_wC_offset + congr_cl16_wC_d'length-1), + din => congr_cl16_wC_d, + dout => congr_cl16_wC_q); +congr_cl16_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl16_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl16_wD_offset to congr_cl16_wD_offset + congr_cl16_wD_d'length-1), + scout => sov(congr_cl16_wD_offset to congr_cl16_wD_offset + congr_cl16_wD_d'length-1), + din => congr_cl16_wD_d, + dout => congr_cl16_wD_q); +congr_cl16_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl16_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl16_wE_offset to congr_cl16_wE_offset + congr_cl16_wE_d'length-1), + scout => sov(congr_cl16_wE_offset to congr_cl16_wE_offset + congr_cl16_wE_d'length-1), + din => congr_cl16_wE_d, + dout => congr_cl16_wE_q); +congr_cl16_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl16_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl16_wF_offset to congr_cl16_wF_offset + congr_cl16_wF_d'length-1), + scout => sov(congr_cl16_wF_offset to congr_cl16_wF_offset + congr_cl16_wF_d'length-1), + din => congr_cl16_wF_d, + dout => congr_cl16_wF_q); +congr_cl16_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl16_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl16_wG_offset to congr_cl16_wG_offset + congr_cl16_wG_d'length-1), + scout => sov(congr_cl16_wG_offset to congr_cl16_wG_offset + congr_cl16_wG_d'length-1), + din => congr_cl16_wG_d, + dout => congr_cl16_wG_q); +congr_cl16_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl16_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl16_wH_offset to congr_cl16_wH_offset + congr_cl16_wH_d'length-1), + scout => sov(congr_cl16_wH_offset to congr_cl16_wH_offset + congr_cl16_wH_d'length-1), + din => congr_cl16_wH_d, + dout => congr_cl16_wH_q); +congr_cl17_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl17_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl17_wA_offset to congr_cl17_wA_offset + congr_cl17_wA_d'length-1), + scout => sov(congr_cl17_wA_offset to congr_cl17_wA_offset + congr_cl17_wA_d'length-1), + din => congr_cl17_wA_d, + dout => congr_cl17_wA_q); +congr_cl17_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl17_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl17_wB_offset to congr_cl17_wB_offset + congr_cl17_wB_d'length-1), + scout => sov(congr_cl17_wB_offset to congr_cl17_wB_offset + congr_cl17_wB_d'length-1), + din => congr_cl17_wB_d, + dout => congr_cl17_wB_q); +congr_cl17_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl17_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl17_wC_offset to congr_cl17_wC_offset + congr_cl17_wC_d'length-1), + scout => sov(congr_cl17_wC_offset to congr_cl17_wC_offset + congr_cl17_wC_d'length-1), + din => congr_cl17_wC_d, + dout => congr_cl17_wC_q); +congr_cl17_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl17_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl17_wD_offset to congr_cl17_wD_offset + congr_cl17_wD_d'length-1), + scout => sov(congr_cl17_wD_offset to congr_cl17_wD_offset + congr_cl17_wD_d'length-1), + din => congr_cl17_wD_d, + dout => congr_cl17_wD_q); +congr_cl17_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl17_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl17_wE_offset to congr_cl17_wE_offset + congr_cl17_wE_d'length-1), + scout => sov(congr_cl17_wE_offset to congr_cl17_wE_offset + congr_cl17_wE_d'length-1), + din => congr_cl17_wE_d, + dout => congr_cl17_wE_q); +congr_cl17_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl17_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl17_wF_offset to congr_cl17_wF_offset + congr_cl17_wF_d'length-1), + scout => sov(congr_cl17_wF_offset to congr_cl17_wF_offset + congr_cl17_wF_d'length-1), + din => congr_cl17_wF_d, + dout => congr_cl17_wF_q); +congr_cl17_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl17_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl17_wG_offset to congr_cl17_wG_offset + congr_cl17_wG_d'length-1), + scout => sov(congr_cl17_wG_offset to congr_cl17_wG_offset + congr_cl17_wG_d'length-1), + din => congr_cl17_wG_d, + dout => congr_cl17_wG_q); +congr_cl17_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl17_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl17_wH_offset to congr_cl17_wH_offset + congr_cl17_wH_d'length-1), + scout => sov(congr_cl17_wH_offset to congr_cl17_wH_offset + congr_cl17_wH_d'length-1), + din => congr_cl17_wH_d, + dout => congr_cl17_wH_q); +congr_cl18_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl18_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl18_wA_offset to congr_cl18_wA_offset + congr_cl18_wA_d'length-1), + scout => sov(congr_cl18_wA_offset to congr_cl18_wA_offset + congr_cl18_wA_d'length-1), + din => congr_cl18_wA_d, + dout => congr_cl18_wA_q); +congr_cl18_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl18_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl18_wB_offset to congr_cl18_wB_offset + congr_cl18_wB_d'length-1), + scout => sov(congr_cl18_wB_offset to congr_cl18_wB_offset + congr_cl18_wB_d'length-1), + din => congr_cl18_wB_d, + dout => congr_cl18_wB_q); +congr_cl18_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl18_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl18_wC_offset to congr_cl18_wC_offset + congr_cl18_wC_d'length-1), + scout => sov(congr_cl18_wC_offset to congr_cl18_wC_offset + congr_cl18_wC_d'length-1), + din => congr_cl18_wC_d, + dout => congr_cl18_wC_q); +congr_cl18_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl18_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl18_wD_offset to congr_cl18_wD_offset + congr_cl18_wD_d'length-1), + scout => sov(congr_cl18_wD_offset to congr_cl18_wD_offset + congr_cl18_wD_d'length-1), + din => congr_cl18_wD_d, + dout => congr_cl18_wD_q); +congr_cl18_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl18_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl18_wE_offset to congr_cl18_wE_offset + congr_cl18_wE_d'length-1), + scout => sov(congr_cl18_wE_offset to congr_cl18_wE_offset + congr_cl18_wE_d'length-1), + din => congr_cl18_wE_d, + dout => congr_cl18_wE_q); +congr_cl18_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl18_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl18_wF_offset to congr_cl18_wF_offset + congr_cl18_wF_d'length-1), + scout => sov(congr_cl18_wF_offset to congr_cl18_wF_offset + congr_cl18_wF_d'length-1), + din => congr_cl18_wF_d, + dout => congr_cl18_wF_q); +congr_cl18_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl18_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl18_wG_offset to congr_cl18_wG_offset + congr_cl18_wG_d'length-1), + scout => sov(congr_cl18_wG_offset to congr_cl18_wG_offset + congr_cl18_wG_d'length-1), + din => congr_cl18_wG_d, + dout => congr_cl18_wG_q); +congr_cl18_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl18_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl18_wH_offset to congr_cl18_wH_offset + congr_cl18_wH_d'length-1), + scout => sov(congr_cl18_wH_offset to congr_cl18_wH_offset + congr_cl18_wH_d'length-1), + din => congr_cl18_wH_d, + dout => congr_cl18_wH_q); +congr_cl19_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl19_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl19_wA_offset to congr_cl19_wA_offset + congr_cl19_wA_d'length-1), + scout => sov(congr_cl19_wA_offset to congr_cl19_wA_offset + congr_cl19_wA_d'length-1), + din => congr_cl19_wA_d, + dout => congr_cl19_wA_q); +congr_cl19_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl19_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl19_wB_offset to congr_cl19_wB_offset + congr_cl19_wB_d'length-1), + scout => sov(congr_cl19_wB_offset to congr_cl19_wB_offset + congr_cl19_wB_d'length-1), + din => congr_cl19_wB_d, + dout => congr_cl19_wB_q); +congr_cl19_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl19_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl19_wC_offset to congr_cl19_wC_offset + congr_cl19_wC_d'length-1), + scout => sov(congr_cl19_wC_offset to congr_cl19_wC_offset + congr_cl19_wC_d'length-1), + din => congr_cl19_wC_d, + dout => congr_cl19_wC_q); +congr_cl19_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl19_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl19_wD_offset to congr_cl19_wD_offset + congr_cl19_wD_d'length-1), + scout => sov(congr_cl19_wD_offset to congr_cl19_wD_offset + congr_cl19_wD_d'length-1), + din => congr_cl19_wD_d, + dout => congr_cl19_wD_q); +congr_cl19_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl19_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl19_wE_offset to congr_cl19_wE_offset + congr_cl19_wE_d'length-1), + scout => sov(congr_cl19_wE_offset to congr_cl19_wE_offset + congr_cl19_wE_d'length-1), + din => congr_cl19_wE_d, + dout => congr_cl19_wE_q); +congr_cl19_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl19_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl19_wF_offset to congr_cl19_wF_offset + congr_cl19_wF_d'length-1), + scout => sov(congr_cl19_wF_offset to congr_cl19_wF_offset + congr_cl19_wF_d'length-1), + din => congr_cl19_wF_d, + dout => congr_cl19_wF_q); +congr_cl19_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl19_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl19_wG_offset to congr_cl19_wG_offset + congr_cl19_wG_d'length-1), + scout => sov(congr_cl19_wG_offset to congr_cl19_wG_offset + congr_cl19_wG_d'length-1), + din => congr_cl19_wG_d, + dout => congr_cl19_wG_q); +congr_cl19_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl19_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl19_wH_offset to congr_cl19_wH_offset + congr_cl19_wH_d'length-1), + scout => sov(congr_cl19_wH_offset to congr_cl19_wH_offset + congr_cl19_wH_d'length-1), + din => congr_cl19_wH_d, + dout => congr_cl19_wH_q); +congr_cl20_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl20_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl20_wA_offset to congr_cl20_wA_offset + congr_cl20_wA_d'length-1), + scout => sov(congr_cl20_wA_offset to congr_cl20_wA_offset + congr_cl20_wA_d'length-1), + din => congr_cl20_wA_d, + dout => congr_cl20_wA_q); +congr_cl20_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl20_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl20_wB_offset to congr_cl20_wB_offset + congr_cl20_wB_d'length-1), + scout => sov(congr_cl20_wB_offset to congr_cl20_wB_offset + congr_cl20_wB_d'length-1), + din => congr_cl20_wB_d, + dout => congr_cl20_wB_q); +congr_cl20_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl20_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl20_wC_offset to congr_cl20_wC_offset + congr_cl20_wC_d'length-1), + scout => sov(congr_cl20_wC_offset to congr_cl20_wC_offset + congr_cl20_wC_d'length-1), + din => congr_cl20_wC_d, + dout => congr_cl20_wC_q); +congr_cl20_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl20_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl20_wD_offset to congr_cl20_wD_offset + congr_cl20_wD_d'length-1), + scout => sov(congr_cl20_wD_offset to congr_cl20_wD_offset + congr_cl20_wD_d'length-1), + din => congr_cl20_wD_d, + dout => congr_cl20_wD_q); +congr_cl20_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl20_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl20_wE_offset to congr_cl20_wE_offset + congr_cl20_wE_d'length-1), + scout => sov(congr_cl20_wE_offset to congr_cl20_wE_offset + congr_cl20_wE_d'length-1), + din => congr_cl20_wE_d, + dout => congr_cl20_wE_q); +congr_cl20_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl20_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl20_wF_offset to congr_cl20_wF_offset + congr_cl20_wF_d'length-1), + scout => sov(congr_cl20_wF_offset to congr_cl20_wF_offset + congr_cl20_wF_d'length-1), + din => congr_cl20_wF_d, + dout => congr_cl20_wF_q); +congr_cl20_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl20_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl20_wG_offset to congr_cl20_wG_offset + congr_cl20_wG_d'length-1), + scout => sov(congr_cl20_wG_offset to congr_cl20_wG_offset + congr_cl20_wG_d'length-1), + din => congr_cl20_wG_d, + dout => congr_cl20_wG_q); +congr_cl20_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl20_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl20_wH_offset to congr_cl20_wH_offset + congr_cl20_wH_d'length-1), + scout => sov(congr_cl20_wH_offset to congr_cl20_wH_offset + congr_cl20_wH_d'length-1), + din => congr_cl20_wH_d, + dout => congr_cl20_wH_q); +congr_cl21_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl21_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl21_wA_offset to congr_cl21_wA_offset + congr_cl21_wA_d'length-1), + scout => sov(congr_cl21_wA_offset to congr_cl21_wA_offset + congr_cl21_wA_d'length-1), + din => congr_cl21_wA_d, + dout => congr_cl21_wA_q); +congr_cl21_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl21_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl21_wB_offset to congr_cl21_wB_offset + congr_cl21_wB_d'length-1), + scout => sov(congr_cl21_wB_offset to congr_cl21_wB_offset + congr_cl21_wB_d'length-1), + din => congr_cl21_wB_d, + dout => congr_cl21_wB_q); +congr_cl21_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl21_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl21_wC_offset to congr_cl21_wC_offset + congr_cl21_wC_d'length-1), + scout => sov(congr_cl21_wC_offset to congr_cl21_wC_offset + congr_cl21_wC_d'length-1), + din => congr_cl21_wC_d, + dout => congr_cl21_wC_q); +congr_cl21_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl21_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl21_wD_offset to congr_cl21_wD_offset + congr_cl21_wD_d'length-1), + scout => sov(congr_cl21_wD_offset to congr_cl21_wD_offset + congr_cl21_wD_d'length-1), + din => congr_cl21_wD_d, + dout => congr_cl21_wD_q); +congr_cl21_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl21_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl21_wE_offset to congr_cl21_wE_offset + congr_cl21_wE_d'length-1), + scout => sov(congr_cl21_wE_offset to congr_cl21_wE_offset + congr_cl21_wE_d'length-1), + din => congr_cl21_wE_d, + dout => congr_cl21_wE_q); +congr_cl21_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl21_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl21_wF_offset to congr_cl21_wF_offset + congr_cl21_wF_d'length-1), + scout => sov(congr_cl21_wF_offset to congr_cl21_wF_offset + congr_cl21_wF_d'length-1), + din => congr_cl21_wF_d, + dout => congr_cl21_wF_q); +congr_cl21_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl21_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl21_wG_offset to congr_cl21_wG_offset + congr_cl21_wG_d'length-1), + scout => sov(congr_cl21_wG_offset to congr_cl21_wG_offset + congr_cl21_wG_d'length-1), + din => congr_cl21_wG_d, + dout => congr_cl21_wG_q); +congr_cl21_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl21_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl21_wH_offset to congr_cl21_wH_offset + congr_cl21_wH_d'length-1), + scout => sov(congr_cl21_wH_offset to congr_cl21_wH_offset + congr_cl21_wH_d'length-1), + din => congr_cl21_wH_d, + dout => congr_cl21_wH_q); +congr_cl22_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl22_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl22_wA_offset to congr_cl22_wA_offset + congr_cl22_wA_d'length-1), + scout => sov(congr_cl22_wA_offset to congr_cl22_wA_offset + congr_cl22_wA_d'length-1), + din => congr_cl22_wA_d, + dout => congr_cl22_wA_q); +congr_cl22_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl22_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl22_wB_offset to congr_cl22_wB_offset + congr_cl22_wB_d'length-1), + scout => sov(congr_cl22_wB_offset to congr_cl22_wB_offset + congr_cl22_wB_d'length-1), + din => congr_cl22_wB_d, + dout => congr_cl22_wB_q); +congr_cl22_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl22_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl22_wC_offset to congr_cl22_wC_offset + congr_cl22_wC_d'length-1), + scout => sov(congr_cl22_wC_offset to congr_cl22_wC_offset + congr_cl22_wC_d'length-1), + din => congr_cl22_wC_d, + dout => congr_cl22_wC_q); +congr_cl22_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl22_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl22_wD_offset to congr_cl22_wD_offset + congr_cl22_wD_d'length-1), + scout => sov(congr_cl22_wD_offset to congr_cl22_wD_offset + congr_cl22_wD_d'length-1), + din => congr_cl22_wD_d, + dout => congr_cl22_wD_q); +congr_cl22_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl22_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl22_wE_offset to congr_cl22_wE_offset + congr_cl22_wE_d'length-1), + scout => sov(congr_cl22_wE_offset to congr_cl22_wE_offset + congr_cl22_wE_d'length-1), + din => congr_cl22_wE_d, + dout => congr_cl22_wE_q); +congr_cl22_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl22_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl22_wF_offset to congr_cl22_wF_offset + congr_cl22_wF_d'length-1), + scout => sov(congr_cl22_wF_offset to congr_cl22_wF_offset + congr_cl22_wF_d'length-1), + din => congr_cl22_wF_d, + dout => congr_cl22_wF_q); +congr_cl22_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl22_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl22_wG_offset to congr_cl22_wG_offset + congr_cl22_wG_d'length-1), + scout => sov(congr_cl22_wG_offset to congr_cl22_wG_offset + congr_cl22_wG_d'length-1), + din => congr_cl22_wG_d, + dout => congr_cl22_wG_q); +congr_cl22_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl22_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl22_wH_offset to congr_cl22_wH_offset + congr_cl22_wH_d'length-1), + scout => sov(congr_cl22_wH_offset to congr_cl22_wH_offset + congr_cl22_wH_d'length-1), + din => congr_cl22_wH_d, + dout => congr_cl22_wH_q); +congr_cl23_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl23_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl23_wA_offset to congr_cl23_wA_offset + congr_cl23_wA_d'length-1), + scout => sov(congr_cl23_wA_offset to congr_cl23_wA_offset + congr_cl23_wA_d'length-1), + din => congr_cl23_wA_d, + dout => congr_cl23_wA_q); +congr_cl23_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl23_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl23_wB_offset to congr_cl23_wB_offset + congr_cl23_wB_d'length-1), + scout => sov(congr_cl23_wB_offset to congr_cl23_wB_offset + congr_cl23_wB_d'length-1), + din => congr_cl23_wB_d, + dout => congr_cl23_wB_q); +congr_cl23_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl23_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl23_wC_offset to congr_cl23_wC_offset + congr_cl23_wC_d'length-1), + scout => sov(congr_cl23_wC_offset to congr_cl23_wC_offset + congr_cl23_wC_d'length-1), + din => congr_cl23_wC_d, + dout => congr_cl23_wC_q); +congr_cl23_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl23_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl23_wD_offset to congr_cl23_wD_offset + congr_cl23_wD_d'length-1), + scout => sov(congr_cl23_wD_offset to congr_cl23_wD_offset + congr_cl23_wD_d'length-1), + din => congr_cl23_wD_d, + dout => congr_cl23_wD_q); +congr_cl23_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl23_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl23_wE_offset to congr_cl23_wE_offset + congr_cl23_wE_d'length-1), + scout => sov(congr_cl23_wE_offset to congr_cl23_wE_offset + congr_cl23_wE_d'length-1), + din => congr_cl23_wE_d, + dout => congr_cl23_wE_q); +congr_cl23_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl23_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl23_wF_offset to congr_cl23_wF_offset + congr_cl23_wF_d'length-1), + scout => sov(congr_cl23_wF_offset to congr_cl23_wF_offset + congr_cl23_wF_d'length-1), + din => congr_cl23_wF_d, + dout => congr_cl23_wF_q); +congr_cl23_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl23_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl23_wG_offset to congr_cl23_wG_offset + congr_cl23_wG_d'length-1), + scout => sov(congr_cl23_wG_offset to congr_cl23_wG_offset + congr_cl23_wG_d'length-1), + din => congr_cl23_wG_d, + dout => congr_cl23_wG_q); +congr_cl23_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl23_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl23_wH_offset to congr_cl23_wH_offset + congr_cl23_wH_d'length-1), + scout => sov(congr_cl23_wH_offset to congr_cl23_wH_offset + congr_cl23_wH_d'length-1), + din => congr_cl23_wH_d, + dout => congr_cl23_wH_q); +congr_cl24_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl24_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl24_wA_offset to congr_cl24_wA_offset + congr_cl24_wA_d'length-1), + scout => sov(congr_cl24_wA_offset to congr_cl24_wA_offset + congr_cl24_wA_d'length-1), + din => congr_cl24_wA_d, + dout => congr_cl24_wA_q); +congr_cl24_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl24_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl24_wB_offset to congr_cl24_wB_offset + congr_cl24_wB_d'length-1), + scout => sov(congr_cl24_wB_offset to congr_cl24_wB_offset + congr_cl24_wB_d'length-1), + din => congr_cl24_wB_d, + dout => congr_cl24_wB_q); +congr_cl24_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl24_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl24_wC_offset to congr_cl24_wC_offset + congr_cl24_wC_d'length-1), + scout => sov(congr_cl24_wC_offset to congr_cl24_wC_offset + congr_cl24_wC_d'length-1), + din => congr_cl24_wC_d, + dout => congr_cl24_wC_q); +congr_cl24_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl24_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl24_wD_offset to congr_cl24_wD_offset + congr_cl24_wD_d'length-1), + scout => sov(congr_cl24_wD_offset to congr_cl24_wD_offset + congr_cl24_wD_d'length-1), + din => congr_cl24_wD_d, + dout => congr_cl24_wD_q); +congr_cl24_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl24_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl24_wE_offset to congr_cl24_wE_offset + congr_cl24_wE_d'length-1), + scout => sov(congr_cl24_wE_offset to congr_cl24_wE_offset + congr_cl24_wE_d'length-1), + din => congr_cl24_wE_d, + dout => congr_cl24_wE_q); +congr_cl24_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl24_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl24_wF_offset to congr_cl24_wF_offset + congr_cl24_wF_d'length-1), + scout => sov(congr_cl24_wF_offset to congr_cl24_wF_offset + congr_cl24_wF_d'length-1), + din => congr_cl24_wF_d, + dout => congr_cl24_wF_q); +congr_cl24_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl24_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl24_wG_offset to congr_cl24_wG_offset + congr_cl24_wG_d'length-1), + scout => sov(congr_cl24_wG_offset to congr_cl24_wG_offset + congr_cl24_wG_d'length-1), + din => congr_cl24_wG_d, + dout => congr_cl24_wG_q); +congr_cl24_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl24_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl24_wH_offset to congr_cl24_wH_offset + congr_cl24_wH_d'length-1), + scout => sov(congr_cl24_wH_offset to congr_cl24_wH_offset + congr_cl24_wH_d'length-1), + din => congr_cl24_wH_d, + dout => congr_cl24_wH_q); +congr_cl25_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl25_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl25_wA_offset to congr_cl25_wA_offset + congr_cl25_wA_d'length-1), + scout => sov(congr_cl25_wA_offset to congr_cl25_wA_offset + congr_cl25_wA_d'length-1), + din => congr_cl25_wA_d, + dout => congr_cl25_wA_q); +congr_cl25_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl25_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl25_wB_offset to congr_cl25_wB_offset + congr_cl25_wB_d'length-1), + scout => sov(congr_cl25_wB_offset to congr_cl25_wB_offset + congr_cl25_wB_d'length-1), + din => congr_cl25_wB_d, + dout => congr_cl25_wB_q); +congr_cl25_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl25_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl25_wC_offset to congr_cl25_wC_offset + congr_cl25_wC_d'length-1), + scout => sov(congr_cl25_wC_offset to congr_cl25_wC_offset + congr_cl25_wC_d'length-1), + din => congr_cl25_wC_d, + dout => congr_cl25_wC_q); +congr_cl25_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl25_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl25_wD_offset to congr_cl25_wD_offset + congr_cl25_wD_d'length-1), + scout => sov(congr_cl25_wD_offset to congr_cl25_wD_offset + congr_cl25_wD_d'length-1), + din => congr_cl25_wD_d, + dout => congr_cl25_wD_q); +congr_cl25_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl25_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl25_wE_offset to congr_cl25_wE_offset + congr_cl25_wE_d'length-1), + scout => sov(congr_cl25_wE_offset to congr_cl25_wE_offset + congr_cl25_wE_d'length-1), + din => congr_cl25_wE_d, + dout => congr_cl25_wE_q); +congr_cl25_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl25_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl25_wF_offset to congr_cl25_wF_offset + congr_cl25_wF_d'length-1), + scout => sov(congr_cl25_wF_offset to congr_cl25_wF_offset + congr_cl25_wF_d'length-1), + din => congr_cl25_wF_d, + dout => congr_cl25_wF_q); +congr_cl25_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl25_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl25_wG_offset to congr_cl25_wG_offset + congr_cl25_wG_d'length-1), + scout => sov(congr_cl25_wG_offset to congr_cl25_wG_offset + congr_cl25_wG_d'length-1), + din => congr_cl25_wG_d, + dout => congr_cl25_wG_q); +congr_cl25_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl25_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl25_wH_offset to congr_cl25_wH_offset + congr_cl25_wH_d'length-1), + scout => sov(congr_cl25_wH_offset to congr_cl25_wH_offset + congr_cl25_wH_d'length-1), + din => congr_cl25_wH_d, + dout => congr_cl25_wH_q); +congr_cl26_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl26_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl26_wA_offset to congr_cl26_wA_offset + congr_cl26_wA_d'length-1), + scout => sov(congr_cl26_wA_offset to congr_cl26_wA_offset + congr_cl26_wA_d'length-1), + din => congr_cl26_wA_d, + dout => congr_cl26_wA_q); +congr_cl26_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl26_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl26_wB_offset to congr_cl26_wB_offset + congr_cl26_wB_d'length-1), + scout => sov(congr_cl26_wB_offset to congr_cl26_wB_offset + congr_cl26_wB_d'length-1), + din => congr_cl26_wB_d, + dout => congr_cl26_wB_q); +congr_cl26_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl26_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl26_wC_offset to congr_cl26_wC_offset + congr_cl26_wC_d'length-1), + scout => sov(congr_cl26_wC_offset to congr_cl26_wC_offset + congr_cl26_wC_d'length-1), + din => congr_cl26_wC_d, + dout => congr_cl26_wC_q); +congr_cl26_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl26_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl26_wD_offset to congr_cl26_wD_offset + congr_cl26_wD_d'length-1), + scout => sov(congr_cl26_wD_offset to congr_cl26_wD_offset + congr_cl26_wD_d'length-1), + din => congr_cl26_wD_d, + dout => congr_cl26_wD_q); +congr_cl26_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl26_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl26_wE_offset to congr_cl26_wE_offset + congr_cl26_wE_d'length-1), + scout => sov(congr_cl26_wE_offset to congr_cl26_wE_offset + congr_cl26_wE_d'length-1), + din => congr_cl26_wE_d, + dout => congr_cl26_wE_q); +congr_cl26_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl26_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl26_wF_offset to congr_cl26_wF_offset + congr_cl26_wF_d'length-1), + scout => sov(congr_cl26_wF_offset to congr_cl26_wF_offset + congr_cl26_wF_d'length-1), + din => congr_cl26_wF_d, + dout => congr_cl26_wF_q); +congr_cl26_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl26_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl26_wG_offset to congr_cl26_wG_offset + congr_cl26_wG_d'length-1), + scout => sov(congr_cl26_wG_offset to congr_cl26_wG_offset + congr_cl26_wG_d'length-1), + din => congr_cl26_wG_d, + dout => congr_cl26_wG_q); +congr_cl26_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl26_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl26_wH_offset to congr_cl26_wH_offset + congr_cl26_wH_d'length-1), + scout => sov(congr_cl26_wH_offset to congr_cl26_wH_offset + congr_cl26_wH_d'length-1), + din => congr_cl26_wH_d, + dout => congr_cl26_wH_q); +congr_cl27_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl27_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl27_wA_offset to congr_cl27_wA_offset + congr_cl27_wA_d'length-1), + scout => sov(congr_cl27_wA_offset to congr_cl27_wA_offset + congr_cl27_wA_d'length-1), + din => congr_cl27_wA_d, + dout => congr_cl27_wA_q); +congr_cl27_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl27_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl27_wB_offset to congr_cl27_wB_offset + congr_cl27_wB_d'length-1), + scout => sov(congr_cl27_wB_offset to congr_cl27_wB_offset + congr_cl27_wB_d'length-1), + din => congr_cl27_wB_d, + dout => congr_cl27_wB_q); +congr_cl27_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl27_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl27_wC_offset to congr_cl27_wC_offset + congr_cl27_wC_d'length-1), + scout => sov(congr_cl27_wC_offset to congr_cl27_wC_offset + congr_cl27_wC_d'length-1), + din => congr_cl27_wC_d, + dout => congr_cl27_wC_q); +congr_cl27_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl27_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl27_wD_offset to congr_cl27_wD_offset + congr_cl27_wD_d'length-1), + scout => sov(congr_cl27_wD_offset to congr_cl27_wD_offset + congr_cl27_wD_d'length-1), + din => congr_cl27_wD_d, + dout => congr_cl27_wD_q); +congr_cl27_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl27_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl27_wE_offset to congr_cl27_wE_offset + congr_cl27_wE_d'length-1), + scout => sov(congr_cl27_wE_offset to congr_cl27_wE_offset + congr_cl27_wE_d'length-1), + din => congr_cl27_wE_d, + dout => congr_cl27_wE_q); +congr_cl27_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl27_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl27_wF_offset to congr_cl27_wF_offset + congr_cl27_wF_d'length-1), + scout => sov(congr_cl27_wF_offset to congr_cl27_wF_offset + congr_cl27_wF_d'length-1), + din => congr_cl27_wF_d, + dout => congr_cl27_wF_q); +congr_cl27_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl27_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl27_wG_offset to congr_cl27_wG_offset + congr_cl27_wG_d'length-1), + scout => sov(congr_cl27_wG_offset to congr_cl27_wG_offset + congr_cl27_wG_d'length-1), + din => congr_cl27_wG_d, + dout => congr_cl27_wG_q); +congr_cl27_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl27_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl27_wH_offset to congr_cl27_wH_offset + congr_cl27_wH_d'length-1), + scout => sov(congr_cl27_wH_offset to congr_cl27_wH_offset + congr_cl27_wH_d'length-1), + din => congr_cl27_wH_d, + dout => congr_cl27_wH_q); +congr_cl28_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl28_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl28_wA_offset to congr_cl28_wA_offset + congr_cl28_wA_d'length-1), + scout => sov(congr_cl28_wA_offset to congr_cl28_wA_offset + congr_cl28_wA_d'length-1), + din => congr_cl28_wA_d, + dout => congr_cl28_wA_q); +congr_cl28_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl28_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl28_wB_offset to congr_cl28_wB_offset + congr_cl28_wB_d'length-1), + scout => sov(congr_cl28_wB_offset to congr_cl28_wB_offset + congr_cl28_wB_d'length-1), + din => congr_cl28_wB_d, + dout => congr_cl28_wB_q); +congr_cl28_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl28_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl28_wC_offset to congr_cl28_wC_offset + congr_cl28_wC_d'length-1), + scout => sov(congr_cl28_wC_offset to congr_cl28_wC_offset + congr_cl28_wC_d'length-1), + din => congr_cl28_wC_d, + dout => congr_cl28_wC_q); +congr_cl28_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl28_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl28_wD_offset to congr_cl28_wD_offset + congr_cl28_wD_d'length-1), + scout => sov(congr_cl28_wD_offset to congr_cl28_wD_offset + congr_cl28_wD_d'length-1), + din => congr_cl28_wD_d, + dout => congr_cl28_wD_q); +congr_cl28_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl28_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl28_wE_offset to congr_cl28_wE_offset + congr_cl28_wE_d'length-1), + scout => sov(congr_cl28_wE_offset to congr_cl28_wE_offset + congr_cl28_wE_d'length-1), + din => congr_cl28_wE_d, + dout => congr_cl28_wE_q); +congr_cl28_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl28_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl28_wF_offset to congr_cl28_wF_offset + congr_cl28_wF_d'length-1), + scout => sov(congr_cl28_wF_offset to congr_cl28_wF_offset + congr_cl28_wF_d'length-1), + din => congr_cl28_wF_d, + dout => congr_cl28_wF_q); +congr_cl28_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl28_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl28_wG_offset to congr_cl28_wG_offset + congr_cl28_wG_d'length-1), + scout => sov(congr_cl28_wG_offset to congr_cl28_wG_offset + congr_cl28_wG_d'length-1), + din => congr_cl28_wG_d, + dout => congr_cl28_wG_q); +congr_cl28_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl28_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl28_wH_offset to congr_cl28_wH_offset + congr_cl28_wH_d'length-1), + scout => sov(congr_cl28_wH_offset to congr_cl28_wH_offset + congr_cl28_wH_d'length-1), + din => congr_cl28_wH_d, + dout => congr_cl28_wH_q); +congr_cl29_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl29_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl29_wA_offset to congr_cl29_wA_offset + congr_cl29_wA_d'length-1), + scout => sov(congr_cl29_wA_offset to congr_cl29_wA_offset + congr_cl29_wA_d'length-1), + din => congr_cl29_wA_d, + dout => congr_cl29_wA_q); +congr_cl29_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl29_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl29_wB_offset to congr_cl29_wB_offset + congr_cl29_wB_d'length-1), + scout => sov(congr_cl29_wB_offset to congr_cl29_wB_offset + congr_cl29_wB_d'length-1), + din => congr_cl29_wB_d, + dout => congr_cl29_wB_q); +congr_cl29_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl29_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl29_wC_offset to congr_cl29_wC_offset + congr_cl29_wC_d'length-1), + scout => sov(congr_cl29_wC_offset to congr_cl29_wC_offset + congr_cl29_wC_d'length-1), + din => congr_cl29_wC_d, + dout => congr_cl29_wC_q); +congr_cl29_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl29_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl29_wD_offset to congr_cl29_wD_offset + congr_cl29_wD_d'length-1), + scout => sov(congr_cl29_wD_offset to congr_cl29_wD_offset + congr_cl29_wD_d'length-1), + din => congr_cl29_wD_d, + dout => congr_cl29_wD_q); +congr_cl29_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl29_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl29_wE_offset to congr_cl29_wE_offset + congr_cl29_wE_d'length-1), + scout => sov(congr_cl29_wE_offset to congr_cl29_wE_offset + congr_cl29_wE_d'length-1), + din => congr_cl29_wE_d, + dout => congr_cl29_wE_q); +congr_cl29_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl29_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl29_wF_offset to congr_cl29_wF_offset + congr_cl29_wF_d'length-1), + scout => sov(congr_cl29_wF_offset to congr_cl29_wF_offset + congr_cl29_wF_d'length-1), + din => congr_cl29_wF_d, + dout => congr_cl29_wF_q); +congr_cl29_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl29_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl29_wG_offset to congr_cl29_wG_offset + congr_cl29_wG_d'length-1), + scout => sov(congr_cl29_wG_offset to congr_cl29_wG_offset + congr_cl29_wG_d'length-1), + din => congr_cl29_wG_d, + dout => congr_cl29_wG_q); +congr_cl29_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl29_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl29_wH_offset to congr_cl29_wH_offset + congr_cl29_wH_d'length-1), + scout => sov(congr_cl29_wH_offset to congr_cl29_wH_offset + congr_cl29_wH_d'length-1), + din => congr_cl29_wH_d, + dout => congr_cl29_wH_q); +congr_cl30_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl30_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl30_wA_offset to congr_cl30_wA_offset + congr_cl30_wA_d'length-1), + scout => sov(congr_cl30_wA_offset to congr_cl30_wA_offset + congr_cl30_wA_d'length-1), + din => congr_cl30_wA_d, + dout => congr_cl30_wA_q); +congr_cl30_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl30_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl30_wB_offset to congr_cl30_wB_offset + congr_cl30_wB_d'length-1), + scout => sov(congr_cl30_wB_offset to congr_cl30_wB_offset + congr_cl30_wB_d'length-1), + din => congr_cl30_wB_d, + dout => congr_cl30_wB_q); +congr_cl30_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl30_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl30_wC_offset to congr_cl30_wC_offset + congr_cl30_wC_d'length-1), + scout => sov(congr_cl30_wC_offset to congr_cl30_wC_offset + congr_cl30_wC_d'length-1), + din => congr_cl30_wC_d, + dout => congr_cl30_wC_q); +congr_cl30_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl30_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl30_wD_offset to congr_cl30_wD_offset + congr_cl30_wD_d'length-1), + scout => sov(congr_cl30_wD_offset to congr_cl30_wD_offset + congr_cl30_wD_d'length-1), + din => congr_cl30_wD_d, + dout => congr_cl30_wD_q); +congr_cl30_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl30_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl30_wE_offset to congr_cl30_wE_offset + congr_cl30_wE_d'length-1), + scout => sov(congr_cl30_wE_offset to congr_cl30_wE_offset + congr_cl30_wE_d'length-1), + din => congr_cl30_wE_d, + dout => congr_cl30_wE_q); +congr_cl30_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl30_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl30_wF_offset to congr_cl30_wF_offset + congr_cl30_wF_d'length-1), + scout => sov(congr_cl30_wF_offset to congr_cl30_wF_offset + congr_cl30_wF_d'length-1), + din => congr_cl30_wF_d, + dout => congr_cl30_wF_q); +congr_cl30_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl30_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl30_wG_offset to congr_cl30_wG_offset + congr_cl30_wG_d'length-1), + scout => sov(congr_cl30_wG_offset to congr_cl30_wG_offset + congr_cl30_wG_d'length-1), + din => congr_cl30_wG_d, + dout => congr_cl30_wG_q); +congr_cl30_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl30_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl30_wH_offset to congr_cl30_wH_offset + congr_cl30_wH_d'length-1), + scout => sov(congr_cl30_wH_offset to congr_cl30_wH_offset + congr_cl30_wH_d'length-1), + din => congr_cl30_wH_d, + dout => congr_cl30_wH_q); +congr_cl31_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl31_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl31_wA_offset to congr_cl31_wA_offset + congr_cl31_wA_d'length-1), + scout => sov(congr_cl31_wA_offset to congr_cl31_wA_offset + congr_cl31_wA_d'length-1), + din => congr_cl31_wA_d, + dout => congr_cl31_wA_q); +congr_cl31_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl31_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl31_wB_offset to congr_cl31_wB_offset + congr_cl31_wB_d'length-1), + scout => sov(congr_cl31_wB_offset to congr_cl31_wB_offset + congr_cl31_wB_d'length-1), + din => congr_cl31_wB_d, + dout => congr_cl31_wB_q); +congr_cl31_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl31_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl31_wC_offset to congr_cl31_wC_offset + congr_cl31_wC_d'length-1), + scout => sov(congr_cl31_wC_offset to congr_cl31_wC_offset + congr_cl31_wC_d'length-1), + din => congr_cl31_wC_d, + dout => congr_cl31_wC_q); +congr_cl31_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl31_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl31_wD_offset to congr_cl31_wD_offset + congr_cl31_wD_d'length-1), + scout => sov(congr_cl31_wD_offset to congr_cl31_wD_offset + congr_cl31_wD_d'length-1), + din => congr_cl31_wD_d, + dout => congr_cl31_wD_q); +congr_cl31_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl31_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl31_wE_offset to congr_cl31_wE_offset + congr_cl31_wE_d'length-1), + scout => sov(congr_cl31_wE_offset to congr_cl31_wE_offset + congr_cl31_wE_d'length-1), + din => congr_cl31_wE_d, + dout => congr_cl31_wE_q); +congr_cl31_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl31_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl31_wF_offset to congr_cl31_wF_offset + congr_cl31_wF_d'length-1), + scout => sov(congr_cl31_wF_offset to congr_cl31_wF_offset + congr_cl31_wF_d'length-1), + din => congr_cl31_wF_d, + dout => congr_cl31_wF_q); +congr_cl31_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl31_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl31_wG_offset to congr_cl31_wG_offset + congr_cl31_wG_d'length-1), + scout => sov(congr_cl31_wG_offset to congr_cl31_wG_offset + congr_cl31_wG_d'length-1), + din => congr_cl31_wG_d, + dout => congr_cl31_wG_q); +congr_cl31_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl31_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl31_wH_offset to congr_cl31_wH_offset + congr_cl31_wH_d'length-1), + scout => sov(congr_cl31_wH_offset to congr_cl31_wH_offset + congr_cl31_wH_d'length-1), + din => congr_cl31_wH_d, + dout => congr_cl31_wH_q); +congr_cl_all_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => congr_cl_all_act_d, + dout(0) => congr_cl_all_act_q); +p0_congr_cl0_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl0_act_d, + dout(0) => p0_congr_cl0_act_q); +p0_congr_cl1_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl1_act_d, + dout(0) => p0_congr_cl1_act_q); +p0_congr_cl2_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl2_act_d, + dout(0) => p0_congr_cl2_act_q); +p0_congr_cl3_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl3_act_d, + dout(0) => p0_congr_cl3_act_q); +p0_congr_cl4_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl4_act_d, + dout(0) => p0_congr_cl4_act_q); +p0_congr_cl5_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl5_act_d, + dout(0) => p0_congr_cl5_act_q); +p0_congr_cl6_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl6_act_d, + dout(0) => p0_congr_cl6_act_q); +p0_congr_cl7_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl7_act_d, + dout(0) => p0_congr_cl7_act_q); +p0_congr_cl8_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl8_act_d, + dout(0) => p0_congr_cl8_act_q); +p0_congr_cl9_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl9_act_d, + dout(0) => p0_congr_cl9_act_q); +p0_congr_cl10_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl10_act_d, + dout(0) => p0_congr_cl10_act_q); +p0_congr_cl11_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl11_act_d, + dout(0) => p0_congr_cl11_act_q); +p0_congr_cl12_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl12_act_d, + dout(0) => p0_congr_cl12_act_q); +p0_congr_cl13_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl13_act_d, + dout(0) => p0_congr_cl13_act_q); +p0_congr_cl14_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl14_act_d, + dout(0) => p0_congr_cl14_act_q); +p0_congr_cl15_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl15_act_d, + dout(0) => p0_congr_cl15_act_q); +p0_congr_cl16_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl16_act_d, + dout(0) => p0_congr_cl16_act_q); +p0_congr_cl17_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl17_act_d, + dout(0) => p0_congr_cl17_act_q); +p0_congr_cl18_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl18_act_d, + dout(0) => p0_congr_cl18_act_q); +p0_congr_cl19_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl19_act_d, + dout(0) => p0_congr_cl19_act_q); +p0_congr_cl20_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl20_act_d, + dout(0) => p0_congr_cl20_act_q); +p0_congr_cl21_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl21_act_d, + dout(0) => p0_congr_cl21_act_q); +p0_congr_cl22_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl22_act_d, + dout(0) => p0_congr_cl22_act_q); +p0_congr_cl23_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl23_act_d, + dout(0) => p0_congr_cl23_act_q); +p0_congr_cl24_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl24_act_d, + dout(0) => p0_congr_cl24_act_q); +p0_congr_cl25_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl25_act_d, + dout(0) => p0_congr_cl25_act_q); +p0_congr_cl26_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl26_act_d, + dout(0) => p0_congr_cl26_act_q); +p0_congr_cl27_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl27_act_d, + dout(0) => p0_congr_cl27_act_q); +p0_congr_cl28_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl28_act_d, + dout(0) => p0_congr_cl28_act_q); +p0_congr_cl29_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl29_act_d, + dout(0) => p0_congr_cl29_act_q); +p0_congr_cl30_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl30_act_d, + dout(0) => p0_congr_cl30_act_q); +p0_congr_cl31_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl31_act_d, + dout(0) => p0_congr_cl31_act_q); +p1_congr_cl0_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl0_act_d, + dout(0) => p1_congr_cl0_act_q); +p1_congr_cl1_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl1_act_d, + dout(0) => p1_congr_cl1_act_q); +p1_congr_cl2_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl2_act_d, + dout(0) => p1_congr_cl2_act_q); +p1_congr_cl3_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl3_act_d, + dout(0) => p1_congr_cl3_act_q); +p1_congr_cl4_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl4_act_d, + dout(0) => p1_congr_cl4_act_q); +p1_congr_cl5_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl5_act_d, + dout(0) => p1_congr_cl5_act_q); +p1_congr_cl6_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl6_act_d, + dout(0) => p1_congr_cl6_act_q); +p1_congr_cl7_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl7_act_d, + dout(0) => p1_congr_cl7_act_q); +p1_congr_cl8_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl8_act_d, + dout(0) => p1_congr_cl8_act_q); +p1_congr_cl9_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl9_act_d, + dout(0) => p1_congr_cl9_act_q); +p1_congr_cl10_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl10_act_d, + dout(0) => p1_congr_cl10_act_q); +p1_congr_cl11_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl11_act_d, + dout(0) => p1_congr_cl11_act_q); +p1_congr_cl12_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl12_act_d, + dout(0) => p1_congr_cl12_act_q); +p1_congr_cl13_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl13_act_d, + dout(0) => p1_congr_cl13_act_q); +p1_congr_cl14_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl14_act_d, + dout(0) => p1_congr_cl14_act_q); +p1_congr_cl15_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl15_act_d, + dout(0) => p1_congr_cl15_act_q); +p1_congr_cl16_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl16_act_d, + dout(0) => p1_congr_cl16_act_q); +p1_congr_cl17_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl17_act_d, + dout(0) => p1_congr_cl17_act_q); +p1_congr_cl18_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl18_act_d, + dout(0) => p1_congr_cl18_act_q); +p1_congr_cl19_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl19_act_d, + dout(0) => p1_congr_cl19_act_q); +p1_congr_cl20_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl20_act_d, + dout(0) => p1_congr_cl20_act_q); +p1_congr_cl21_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl21_act_d, + dout(0) => p1_congr_cl21_act_q); +p1_congr_cl22_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl22_act_d, + dout(0) => p1_congr_cl22_act_q); +p1_congr_cl23_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl23_act_d, + dout(0) => p1_congr_cl23_act_q); +p1_congr_cl24_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl24_act_d, + dout(0) => p1_congr_cl24_act_q); +p1_congr_cl25_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl25_act_d, + dout(0) => p1_congr_cl25_act_q); +p1_congr_cl26_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl26_act_d, + dout(0) => p1_congr_cl26_act_q); +p1_congr_cl27_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl27_act_d, + dout(0) => p1_congr_cl27_act_q); +p1_congr_cl28_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl28_act_d, + dout(0) => p1_congr_cl28_act_q); +p1_congr_cl29_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl29_act_d, + dout(0) => p1_congr_cl29_act_q); +p1_congr_cl30_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl30_act_d, + dout(0) => p1_congr_cl30_act_q); +p1_congr_cl31_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl31_act_d, + dout(0) => p1_congr_cl31_act_q); +flush_wayA_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayA_d, + dout => flush_wayA_q); +flush_wayA_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv4_ex4_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(flush_wayA_data_offset to flush_wayA_data_offset + flush_wayA_data_d'length-1), + scout => sov(flush_wayA_data_offset to flush_wayA_data_offset + flush_wayA_data_d'length-1), + din => flush_wayA_data_d, + dout => flush_wayA_data_q); +flush_wayA_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv5_ex5_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayA_data2_d, + dout => flush_wayA_data2_q); +flush_wayB_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayB_d, + dout => flush_wayB_q); +flush_wayB_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv4_ex4_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(flush_wayB_data_offset to flush_wayB_data_offset + flush_wayB_data_d'length-1), + scout => sov(flush_wayB_data_offset to flush_wayB_data_offset + flush_wayB_data_d'length-1), + din => flush_wayB_data_d, + dout => flush_wayB_data_q); +flush_wayB_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv5_ex5_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayB_data2_d, + dout => flush_wayB_data2_q); +flush_wayC_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayC_d, + dout => flush_wayC_q); +flush_wayC_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv4_ex4_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(flush_wayC_data_offset to flush_wayC_data_offset + flush_wayC_data_d'length-1), + scout => sov(flush_wayC_data_offset to flush_wayC_data_offset + flush_wayC_data_d'length-1), + din => flush_wayC_data_d, + dout => flush_wayC_data_q); +flush_wayC_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv5_ex5_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayC_data2_d, + dout => flush_wayC_data2_q); +flush_wayD_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayD_d, + dout => flush_wayD_q); +flush_wayD_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv4_ex4_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(flush_wayD_data_offset to flush_wayD_data_offset + flush_wayD_data_d'length-1), + scout => sov(flush_wayD_data_offset to flush_wayD_data_offset + flush_wayD_data_d'length-1), + din => flush_wayD_data_d, + dout => flush_wayD_data_q); +flush_wayD_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv5_ex5_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayD_data2_d, + dout => flush_wayD_data2_q); +flush_wayE_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayE_d, + dout => flush_wayE_q); +flush_wayE_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv4_ex4_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(flush_wayE_data_offset to flush_wayE_data_offset + flush_wayE_data_d'length-1), + scout => sov(flush_wayE_data_offset to flush_wayE_data_offset + flush_wayE_data_d'length-1), + din => flush_wayE_data_d, + dout => flush_wayE_data_q); +flush_wayE_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv5_ex5_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayE_data2_d, + dout => flush_wayE_data2_q); +flush_wayF_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayF_d, + dout => flush_wayF_q); +flush_wayF_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv4_ex4_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(flush_wayF_data_offset to flush_wayF_data_offset + flush_wayF_data_d'length-1), + scout => sov(flush_wayF_data_offset to flush_wayF_data_offset + flush_wayF_data_d'length-1), + din => flush_wayF_data_d, + dout => flush_wayF_data_q); +flush_wayF_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv5_ex5_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayF_data2_d, + dout => flush_wayF_data2_q); +flush_wayG_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayG_d, + dout => flush_wayG_q); +flush_wayG_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv4_ex4_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(flush_wayG_data_offset to flush_wayG_data_offset + flush_wayG_data_d'length-1), + scout => sov(flush_wayG_data_offset to flush_wayG_data_offset + flush_wayG_data_d'length-1), + din => flush_wayG_data_d, + dout => flush_wayG_data_q); +flush_wayG_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv5_ex5_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayG_data2_d, + dout => flush_wayG_data2_q); +flush_wayH_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayH_d, + dout => flush_wayH_q); +flush_wayH_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv4_ex4_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(flush_wayH_data_offset to flush_wayH_data_offset + flush_wayH_data_d'length-1), + scout => sov(flush_wayH_data_offset to flush_wayH_data_offset + flush_wayH_data_d'length-1), + din => flush_wayH_data_d, + dout => flush_wayH_data_q); +flush_wayH_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv5_ex5_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayH_data2_d, + dout => flush_wayH_data2_q); +ex3_flush_cline_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_flush_cline_offset), + scout => sov(ex3_flush_cline_offset), + din => ex3_flush_cline_d, + dout => ex3_flush_cline_q); +ex4_congr_cl_reg: tri_regk +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex4_congr_cl_d, + dout => ex4_congr_cl_q); +ex5_congr_cl_reg: tri_rlmreg_p +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv4_ex4_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_congr_cl_offset to ex5_congr_cl_offset + ex5_congr_cl_d'length-1), + scout => sov(ex5_congr_cl_offset to ex5_congr_cl_offset + ex5_congr_cl_d'length-1), + din => ex5_congr_cl_d, + dout => ex5_congr_cl_q); +ex6_congr_cl_reg: tri_regk +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv5_ex5_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex6_congr_cl_d, + dout => ex6_congr_cl_q); +ex7_congr_cl_reg: tri_rlmreg_p +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex7_congr_cl_offset to ex7_congr_cl_offset + ex7_congr_cl_d'length-1), + scout => sov(ex7_congr_cl_offset to ex7_congr_cl_offset + ex7_congr_cl_d'length-1), + din => ex7_congr_cl_d, + dout => ex7_congr_cl_q); +ex8_congr_cl_reg: tri_rlmreg_p +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex8_congr_cl_offset to ex8_congr_cl_offset + ex8_congr_cl_d'length-1), + scout => sov(ex8_congr_cl_offset to ex8_congr_cl_offset + ex8_congr_cl_d'length-1), + din => ex8_congr_cl_d, + dout => ex8_congr_cl_q); +ex9_congr_cl_reg: tri_rlmreg_p +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex9_congr_cl_offset to ex9_congr_cl_offset + ex9_congr_cl_d'length-1), + scout => sov(ex9_congr_cl_offset to ex9_congr_cl_offset + ex9_congr_cl_d'length-1), + din => ex9_congr_cl_d, + dout => ex9_congr_cl_q); +wayA_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(wayA_val_b_offset to wayA_val_b_offset + wayA_val_b_q'length-1), + scout => sov(wayA_val_b_offset to wayA_val_b_offset + wayA_val_b_q'length-1), + a1 => wayA_early_stg_pri, + a2 => wayA_stg_val, + b1 => wayA_later_stg_pri, + b2 => wayA_stg_val_b, + qb => wayA_val_b_q); +wayB_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(wayB_val_b_offset to wayB_val_b_offset + wayB_val_b_q'length-1), + scout => sov(wayB_val_b_offset to wayB_val_b_offset + wayB_val_b_q'length-1), + a1 => wayB_early_stg_pri, + a2 => wayB_stg_val, + b1 => wayB_later_stg_pri, + b2 => wayB_stg_val_b, + qb => wayB_val_b_q); +wayC_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(wayC_val_b_offset to wayC_val_b_offset + wayC_val_b_q'length-1), + scout => sov(wayC_val_b_offset to wayC_val_b_offset + wayC_val_b_q'length-1), + a1 => wayC_early_stg_pri, + a2 => wayC_stg_val, + b1 => wayC_later_stg_pri, + b2 => wayC_stg_val_b, + qb => wayC_val_b_q); +wayD_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(wayD_val_b_offset to wayD_val_b_offset + wayD_val_b_q'length-1), + scout => sov(wayD_val_b_offset to wayD_val_b_offset + wayD_val_b_q'length-1), + a1 => wayD_early_stg_pri, + a2 => wayD_stg_val, + b1 => wayD_later_stg_pri, + b2 => wayD_stg_val_b, + qb => wayD_val_b_q); +wayE_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(wayE_val_b_offset to wayE_val_b_offset + wayE_val_b_q'length-1), + scout => sov(wayE_val_b_offset to wayE_val_b_offset + wayE_val_b_q'length-1), + a1 => wayE_early_stg_pri, + a2 => wayE_stg_val, + b1 => wayE_later_stg_pri, + b2 => wayE_stg_val_b, + qb => wayE_val_b_q); +wayF_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(wayF_val_b_offset to wayF_val_b_offset + wayF_val_b_q'length-1), + scout => sov(wayF_val_b_offset to wayF_val_b_offset + wayF_val_b_q'length-1), + a1 => wayF_early_stg_pri, + a2 => wayF_stg_val, + b1 => wayF_later_stg_pri, + b2 => wayF_stg_val_b, + qb => wayF_val_b_q); +wayG_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(wayG_val_b_offset to wayG_val_b_offset + wayG_val_b_q'length-1), + scout => sov(wayG_val_b_offset to wayG_val_b_offset + wayG_val_b_q'length-1), + a1 => wayG_early_stg_pri, + a2 => wayG_stg_val, + b1 => wayG_later_stg_pri, + b2 => wayG_stg_val_b, + qb => wayG_val_b_q); +wayH_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(wayH_val_b_offset to wayH_val_b_offset + wayH_val_b_q'length-1), + scout => sov(wayH_val_b_offset to wayH_val_b_offset + wayH_val_b_q'length-1), + a1 => wayH_early_stg_pri, + a2 => wayH_stg_val, + b1 => wayH_later_stg_pri, + b2 => wayH_stg_val_b, + qb => wayH_val_b_q); +ex3_wayA_fxubyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayA_fxubyp_val_offset), + scout => sov(ex3_wayA_fxubyp_val_offset), + din => ex3_wayA_fxubyp_val_d, + dout => ex3_wayA_fxubyp_val_q); +ex3_wayB_fxubyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayB_fxubyp_val_offset), + scout => sov(ex3_wayB_fxubyp_val_offset), + din => ex3_wayB_fxubyp_val_d, + dout => ex3_wayB_fxubyp_val_q); +ex3_wayC_fxubyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayC_fxubyp_val_offset), + scout => sov(ex3_wayC_fxubyp_val_offset), + din => ex3_wayC_fxubyp_val_d, + dout => ex3_wayC_fxubyp_val_q); +ex3_wayD_fxubyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayD_fxubyp_val_offset), + scout => sov(ex3_wayD_fxubyp_val_offset), + din => ex3_wayD_fxubyp_val_d, + dout => ex3_wayD_fxubyp_val_q); +ex3_wayE_fxubyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayE_fxubyp_val_offset), + scout => sov(ex3_wayE_fxubyp_val_offset), + din => ex3_wayE_fxubyp_val_d, + dout => ex3_wayE_fxubyp_val_q); +ex3_wayF_fxubyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayF_fxubyp_val_offset), + scout => sov(ex3_wayF_fxubyp_val_offset), + din => ex3_wayF_fxubyp_val_d, + dout => ex3_wayF_fxubyp_val_q); +ex3_wayG_fxubyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayG_fxubyp_val_offset), + scout => sov(ex3_wayG_fxubyp_val_offset), + din => ex3_wayG_fxubyp_val_d, + dout => ex3_wayG_fxubyp_val_q); +ex3_wayH_fxubyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayH_fxubyp_val_offset), + scout => sov(ex3_wayH_fxubyp_val_offset), + din => ex3_wayH_fxubyp_val_d, + dout => ex3_wayH_fxubyp_val_q); +ex4_wayA_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayA_fxubyp_val_d, + dout(0) => ex4_wayA_fxubyp_val_q); +ex4_wayB_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayB_fxubyp_val_d, + dout(0) => ex4_wayB_fxubyp_val_q); +ex4_wayC_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayC_fxubyp_val_d, + dout(0) => ex4_wayC_fxubyp_val_q); +ex4_wayD_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayD_fxubyp_val_d, + dout(0) => ex4_wayD_fxubyp_val_q); +ex4_wayE_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayE_fxubyp_val_d, + dout(0) => ex4_wayE_fxubyp_val_q); +ex4_wayF_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayF_fxubyp_val_d, + dout(0) => ex4_wayF_fxubyp_val_q); +ex4_wayG_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayG_fxubyp_val_d, + dout(0) => ex4_wayG_fxubyp_val_q); +ex4_wayH_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayH_fxubyp_val_d, + dout(0) => ex4_wayH_fxubyp_val_q); +ex3_wayA_relbyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayA_relbyp_val_offset), + scout => sov(ex3_wayA_relbyp_val_offset), + din => ex3_wayA_relbyp_val_d, + dout => ex3_wayA_relbyp_val_q); +ex3_wayB_relbyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayB_relbyp_val_offset), + scout => sov(ex3_wayB_relbyp_val_offset), + din => ex3_wayB_relbyp_val_d, + dout => ex3_wayB_relbyp_val_q); +ex3_wayC_relbyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayC_relbyp_val_offset), + scout => sov(ex3_wayC_relbyp_val_offset), + din => ex3_wayC_relbyp_val_d, + dout => ex3_wayC_relbyp_val_q); +ex3_wayD_relbyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayD_relbyp_val_offset), + scout => sov(ex3_wayD_relbyp_val_offset), + din => ex3_wayD_relbyp_val_d, + dout => ex3_wayD_relbyp_val_q); +ex3_wayE_relbyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayE_relbyp_val_offset), + scout => sov(ex3_wayE_relbyp_val_offset), + din => ex3_wayE_relbyp_val_d, + dout => ex3_wayE_relbyp_val_q); +ex3_wayF_relbyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayF_relbyp_val_offset), + scout => sov(ex3_wayF_relbyp_val_offset), + din => ex3_wayF_relbyp_val_d, + dout => ex3_wayF_relbyp_val_q); +ex3_wayG_relbyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayG_relbyp_val_offset), + scout => sov(ex3_wayG_relbyp_val_offset), + din => ex3_wayG_relbyp_val_d, + dout => ex3_wayG_relbyp_val_q); +ex3_wayH_relbyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayH_relbyp_val_offset), + scout => sov(ex3_wayH_relbyp_val_offset), + din => ex3_wayH_relbyp_val_d, + dout => ex3_wayH_relbyp_val_q); +ex4_wayA_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayA_relbyp_val_d, + dout(0) => ex4_wayA_relbyp_val_q); +ex4_wayB_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayB_relbyp_val_d, + dout(0) => ex4_wayB_relbyp_val_q); +ex4_wayC_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayC_relbyp_val_d, + dout(0) => ex4_wayC_relbyp_val_q); +ex4_wayD_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayD_relbyp_val_d, + dout(0) => ex4_wayD_relbyp_val_q); +ex4_wayE_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayE_relbyp_val_d, + dout(0) => ex4_wayE_relbyp_val_q); +ex4_wayF_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayF_relbyp_val_d, + dout(0) => ex4_wayF_relbyp_val_q); +ex4_wayG_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayG_relbyp_val_d, + dout(0) => ex4_wayG_relbyp_val_q); +ex4_wayH_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayH_relbyp_val_d, + dout(0) => ex4_wayH_relbyp_val_q); +ex4_xuop_wayA_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_xuop_wayA_upd_offset), + scout => sov(ex4_xuop_wayA_upd_offset), + din => ex4_xuop_wayA_upd_d, + dout => ex4_xuop_wayA_upd_q); +ex4_xuop_wayB_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_xuop_wayB_upd_offset), + scout => sov(ex4_xuop_wayB_upd_offset), + din => ex4_xuop_wayB_upd_d, + dout => ex4_xuop_wayB_upd_q); +ex4_xuop_wayC_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_xuop_wayC_upd_offset), + scout => sov(ex4_xuop_wayC_upd_offset), + din => ex4_xuop_wayC_upd_d, + dout => ex4_xuop_wayC_upd_q); +ex4_xuop_wayD_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_xuop_wayD_upd_offset), + scout => sov(ex4_xuop_wayD_upd_offset), + din => ex4_xuop_wayD_upd_d, + dout => ex4_xuop_wayD_upd_q); +ex4_xuop_wayE_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_xuop_wayE_upd_offset), + scout => sov(ex4_xuop_wayE_upd_offset), + din => ex4_xuop_wayE_upd_d, + dout => ex4_xuop_wayE_upd_q); +ex4_xuop_wayF_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_xuop_wayF_upd_offset), + scout => sov(ex4_xuop_wayF_upd_offset), + din => ex4_xuop_wayF_upd_d, + dout => ex4_xuop_wayF_upd_q); +ex4_xuop_wayG_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_xuop_wayG_upd_offset), + scout => sov(ex4_xuop_wayG_upd_offset), + din => ex4_xuop_wayG_upd_d, + dout => ex4_xuop_wayG_upd_q); +ex4_xuop_wayH_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_xuop_wayH_upd_offset), + scout => sov(ex4_xuop_wayH_upd_offset), + din => ex4_xuop_wayH_upd_d, + dout => ex4_xuop_wayH_upd_q); +ex5_xuop_wayA_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_xuop_wayA_upd_offset), + scout => sov(ex5_xuop_wayA_upd_offset), + din => ex5_xuop_wayA_upd_d, + dout => ex5_xuop_wayA_upd_q); +ex5_xuop_wayB_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_xuop_wayB_upd_offset), + scout => sov(ex5_xuop_wayB_upd_offset), + din => ex5_xuop_wayB_upd_d, + dout => ex5_xuop_wayB_upd_q); +ex5_xuop_wayC_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_xuop_wayC_upd_offset), + scout => sov(ex5_xuop_wayC_upd_offset), + din => ex5_xuop_wayC_upd_d, + dout => ex5_xuop_wayC_upd_q); +ex5_xuop_wayD_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_xuop_wayD_upd_offset), + scout => sov(ex5_xuop_wayD_upd_offset), + din => ex5_xuop_wayD_upd_d, + dout => ex5_xuop_wayD_upd_q); +ex5_xuop_wayE_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_xuop_wayE_upd_offset), + scout => sov(ex5_xuop_wayE_upd_offset), + din => ex5_xuop_wayE_upd_d, + dout => ex5_xuop_wayE_upd_q); +ex5_xuop_wayF_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_xuop_wayF_upd_offset), + scout => sov(ex5_xuop_wayF_upd_offset), + din => ex5_xuop_wayF_upd_d, + dout => ex5_xuop_wayF_upd_q); +ex5_xuop_wayG_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_xuop_wayG_upd_offset), + scout => sov(ex5_xuop_wayG_upd_offset), + din => ex5_xuop_wayG_upd_d, + dout => ex5_xuop_wayG_upd_q); +ex5_xuop_wayH_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_xuop_wayH_upd_offset), + scout => sov(ex5_xuop_wayH_upd_offset), + din => ex5_xuop_wayH_upd_d, + dout => ex5_xuop_wayH_upd_q); +inval_clr_lck_wA_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(inval_clr_lck_wA_offset), + scout => sov(inval_clr_lck_wA_offset), + din => inval_clr_lck_wA_d, + dout => inval_clr_lck_wA_q); +inval_clr_lck_wB_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(inval_clr_lck_wB_offset), + scout => sov(inval_clr_lck_wB_offset), + din => inval_clr_lck_wB_d, + dout => inval_clr_lck_wB_q); +inval_clr_lck_wC_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(inval_clr_lck_wC_offset), + scout => sov(inval_clr_lck_wC_offset), + din => inval_clr_lck_wC_d, + dout => inval_clr_lck_wC_q); +inval_clr_lck_wD_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(inval_clr_lck_wD_offset), + scout => sov(inval_clr_lck_wD_offset), + din => inval_clr_lck_wD_d, + dout => inval_clr_lck_wD_q); +inval_clr_lck_wE_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(inval_clr_lck_wE_offset), + scout => sov(inval_clr_lck_wE_offset), + din => inval_clr_lck_wE_d, + dout => inval_clr_lck_wE_q); +inval_clr_lck_wF_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(inval_clr_lck_wF_offset), + scout => sov(inval_clr_lck_wF_offset), + din => inval_clr_lck_wF_d, + dout => inval_clr_lck_wF_q); +inval_clr_lck_wG_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(inval_clr_lck_wG_offset), + scout => sov(inval_clr_lck_wG_offset), + din => inval_clr_lck_wG_d, + dout => inval_clr_lck_wG_q); +inval_clr_lck_wH_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(inval_clr_lck_wH_offset), + scout => sov(inval_clr_lck_wH_offset), + din => inval_clr_lck_wH_d, + dout => inval_clr_lck_wH_q); +ex4_wayA_val_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex4_wayA_val_d, + dout => ex4_wayA_val_q); +ex4_wayB_val_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex4_wayB_val_d, + dout => ex4_wayB_val_q); +ex4_wayC_val_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex4_wayC_val_d, + dout => ex4_wayC_val_q); +ex4_wayD_val_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex4_wayD_val_d, + dout => ex4_wayD_val_q); +ex4_wayE_val_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex4_wayE_val_d, + dout => ex4_wayE_val_q); +ex4_wayF_val_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex4_wayF_val_d, + dout => ex4_wayF_val_q); +ex4_wayG_val_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex4_wayG_val_d, + dout => ex4_wayG_val_q); +ex4_wayH_val_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex4_wayH_val_d, + dout => ex4_wayH_val_q); +congr_cl_m_upd_wayA_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_m_upd_wayA_offset), + scout => sov(congr_cl_m_upd_wayA_offset), + din => congr_cl_m_upd_wayA_d, + dout => congr_cl_m_upd_wayA_q); +congr_cl_m_upd_wayB_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_m_upd_wayB_offset), + scout => sov(congr_cl_m_upd_wayB_offset), + din => congr_cl_m_upd_wayB_d, + dout => congr_cl_m_upd_wayB_q); +congr_cl_m_upd_wayC_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_m_upd_wayC_offset), + scout => sov(congr_cl_m_upd_wayC_offset), + din => congr_cl_m_upd_wayC_d, + dout => congr_cl_m_upd_wayC_q); +congr_cl_m_upd_wayD_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_m_upd_wayD_offset), + scout => sov(congr_cl_m_upd_wayD_offset), + din => congr_cl_m_upd_wayD_d, + dout => congr_cl_m_upd_wayD_q); +congr_cl_m_upd_wayE_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_m_upd_wayE_offset), + scout => sov(congr_cl_m_upd_wayE_offset), + din => congr_cl_m_upd_wayE_d, + dout => congr_cl_m_upd_wayE_q); +congr_cl_m_upd_wayF_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_m_upd_wayF_offset), + scout => sov(congr_cl_m_upd_wayF_offset), + din => congr_cl_m_upd_wayF_d, + dout => congr_cl_m_upd_wayF_q); +congr_cl_m_upd_wayG_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_m_upd_wayG_offset), + scout => sov(congr_cl_m_upd_wayG_offset), + din => congr_cl_m_upd_wayG_d, + dout => congr_cl_m_upd_wayG_q); +congr_cl_m_upd_wayH_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_m_upd_wayH_offset), + scout => sov(congr_cl_m_upd_wayH_offset), + din => congr_cl_m_upd_wayH_d, + dout => congr_cl_m_upd_wayH_q); +ex2_congr_cl_reg: tri_regk +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv1_ex1_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex2_congr_cl_d, + dout => ex2_congr_cl_q); +ex3_congr_cl_reg: tri_rlmreg_p +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_congr_cl_offset to ex3_congr_cl_offset + ex3_congr_cl_d'length-1), + scout => sov(ex3_congr_cl_offset to ex3_congr_cl_offset + ex3_congr_cl_d'length-1), + din => ex3_congr_cl_d, + dout => ex3_congr_cl_q); +rel_congr_cl_reg: tri_regk +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_congr_cl_d, + dout => rel_congr_cl_q); +rel24_congr_cl_reg: tri_rlmreg_p +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel24_congr_cl_offset to rel24_congr_cl_offset + rel24_congr_cl_d'length-1), + scout => sov(rel24_congr_cl_offset to rel24_congr_cl_offset + rel24_congr_cl_d'length-1), + din => rel24_congr_cl_d, + dout => rel24_congr_cl_q); +relu_congr_cl_reg: tri_regk +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => relu_congr_cl_d, + dout => relu_congr_cl_q); +relu_s_congr_cl_reg: tri_rlmreg_p +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_perr_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(relu_s_congr_cl_offset to relu_s_congr_cl_offset + relu_s_congr_cl_d'length-1), + scout => sov(relu_s_congr_cl_offset to relu_s_congr_cl_offset + relu_s_congr_cl_d'length-1), + din => relu_s_congr_cl_d, + dout => relu_s_congr_cl_q); +reload_way_clr_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_way_clr_offset to reload_way_clr_offset + reload_way_clr_d'length-1), + scout => sov(reload_way_clr_offset to reload_way_clr_offset + reload_way_clr_d'length-1), + din => reload_way_clr_d, + dout => reload_way_clr_q); +ex4_watchSet_coll_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_watchSet_coll_offset), + scout => sov(ex4_watchSet_coll_offset), + din => ex4_watchSet_coll_d, + dout => ex4_watchSet_coll_q); +rel_wayA_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_wayA_val_b_offset to rel_wayA_val_b_offset + rel_wayA_val_b_q'length-1), + scout => sov(rel_wayA_val_b_offset to rel_wayA_val_b_offset + rel_wayA_val_b_q'length-1), + a1 => rel_wayA_early_stg_pri, + a2 => rel_wayA_stg_val, + b1 => rel_wayA_later_stg_pri, + b2 => rel_wayA_stg_val_b, + qb => rel_wayA_val_b_q); +rel_wayB_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_wayB_val_b_offset to rel_wayB_val_b_offset + rel_wayB_val_b_q'length-1), + scout => sov(rel_wayB_val_b_offset to rel_wayB_val_b_offset + rel_wayB_val_b_q'length-1), + a1 => rel_wayB_early_stg_pri, + a2 => rel_wayB_stg_val, + b1 => rel_wayB_later_stg_pri, + b2 => rel_wayB_stg_val_b, + qb => rel_wayB_val_b_q); +rel_wayC_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_wayC_val_b_offset to rel_wayC_val_b_offset + rel_wayC_val_b_q'length-1), + scout => sov(rel_wayC_val_b_offset to rel_wayC_val_b_offset + rel_wayC_val_b_q'length-1), + a1 => rel_wayC_early_stg_pri, + a2 => rel_wayC_stg_val, + b1 => rel_wayC_later_stg_pri, + b2 => rel_wayC_stg_val_b, + qb => rel_wayC_val_b_q); +rel_wayD_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_wayD_val_b_offset to rel_wayD_val_b_offset + rel_wayD_val_b_q'length-1), + scout => sov(rel_wayD_val_b_offset to rel_wayD_val_b_offset + rel_wayD_val_b_q'length-1), + a1 => rel_wayD_early_stg_pri, + a2 => rel_wayD_stg_val, + b1 => rel_wayD_later_stg_pri, + b2 => rel_wayD_stg_val_b, + qb => rel_wayD_val_b_q); +rel_wayE_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_wayE_val_b_offset to rel_wayE_val_b_offset + rel_wayE_val_b_q'length-1), + scout => sov(rel_wayE_val_b_offset to rel_wayE_val_b_offset + rel_wayE_val_b_q'length-1), + a1 => rel_wayE_early_stg_pri, + a2 => rel_wayE_stg_val, + b1 => rel_wayE_later_stg_pri, + b2 => rel_wayE_stg_val_b, + qb => rel_wayE_val_b_q); +rel_wayF_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_wayF_val_b_offset to rel_wayF_val_b_offset + rel_wayF_val_b_q'length-1), + scout => sov(rel_wayF_val_b_offset to rel_wayF_val_b_offset + rel_wayF_val_b_q'length-1), + a1 => rel_wayF_early_stg_pri, + a2 => rel_wayF_stg_val, + b1 => rel_wayF_later_stg_pri, + b2 => rel_wayF_stg_val_b, + qb => rel_wayF_val_b_q); +rel_wayG_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_wayG_val_b_offset to rel_wayG_val_b_offset + rel_wayG_val_b_q'length-1), + scout => sov(rel_wayG_val_b_offset to rel_wayG_val_b_offset + rel_wayG_val_b_q'length-1), + a1 => rel_wayG_early_stg_pri, + a2 => rel_wayG_stg_val, + b1 => rel_wayG_later_stg_pri, + b2 => rel_wayG_stg_val_b, + qb => rel_wayG_val_b_q); +rel_wayH_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_wayH_val_b_offset to rel_wayH_val_b_offset + rel_wayH_val_b_q'length-1), + scout => sov(rel_wayH_val_b_offset to rel_wayH_val_b_offset + rel_wayH_val_b_q'length-1), + a1 => rel_wayH_early_stg_pri, + a2 => rel_wayH_stg_val, + b1 => rel_wayH_later_stg_pri, + b2 => rel_wayH_stg_val_b, + qb => rel_wayH_val_b_q); +rel24_wayA_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayA_fxubyp_val_d, + dout(0) => rel24_wayA_fxubyp_val_q); +rel24_wayB_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayB_fxubyp_val_d, + dout(0) => rel24_wayB_fxubyp_val_q); +rel24_wayC_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayC_fxubyp_val_d, + dout(0) => rel24_wayC_fxubyp_val_q); +rel24_wayD_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayD_fxubyp_val_d, + dout(0) => rel24_wayD_fxubyp_val_q); +rel24_wayE_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayE_fxubyp_val_d, + dout(0) => rel24_wayE_fxubyp_val_q); +rel24_wayF_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayF_fxubyp_val_d, + dout(0) => rel24_wayF_fxubyp_val_q); +rel24_wayG_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayG_fxubyp_val_d, + dout(0) => rel24_wayG_fxubyp_val_q); +rel24_wayH_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayH_fxubyp_val_d, + dout(0) => rel24_wayH_fxubyp_val_q); +rel24_wayA_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayA_relbyp_val_d, + dout(0) => rel24_wayA_relbyp_val_q); +rel24_wayB_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayB_relbyp_val_d, + dout(0) => rel24_wayB_relbyp_val_q); +rel24_wayC_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayC_relbyp_val_d, + dout(0) => rel24_wayC_relbyp_val_q); +rel24_wayD_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayD_relbyp_val_d, + dout(0) => rel24_wayD_relbyp_val_q); +rel24_wayE_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayE_relbyp_val_d, + dout(0) => rel24_wayE_relbyp_val_q); +rel24_wayF_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayF_relbyp_val_d, + dout(0) => rel24_wayF_relbyp_val_q); +rel24_wayG_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayG_relbyp_val_d, + dout(0) => rel24_wayG_relbyp_val_q); +rel24_wayH_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayH_relbyp_val_d, + dout(0) => rel24_wayH_relbyp_val_q); +rel_val_stg2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_val_stg2_offset), + scout => sov(rel_val_stg2_offset), + din => rel_val_stg2_d, + dout => rel_val_stg2_q); +rel_val_clr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_val_clr_offset), + scout => sov(rel_val_clr_offset), + din => rel_val_clr_d, + dout => rel_val_clr_q); +rel_port_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_port_upd_offset), + scout => sov(rel_port_upd_offset), + din => rel_port_upd_d, + dout => rel_port_upd_q); +rel_val_stg4_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_val_stg4_offset), + scout => sov(rel_val_stg4_offset), + din => rel_val_stg4_d, + dout => rel_val_stg4_q); +rel_binv_stg4_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_binv_stg4_offset), + scout => sov(rel_binv_stg4_offset), + din => rel_binv_stg4_d, + dout => rel_binv_stg4_q); +back_inval_stg3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(back_inval_stg3_offset), + scout => sov(back_inval_stg3_offset), + din => back_inval_stg3_d, + dout => back_inval_stg3_q); +back_inval_stg4_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(back_inval_stg4_offset), + scout => sov(back_inval_stg4_offset), + din => back_inval_stg4_d, + dout => back_inval_stg4_q); +back_inval_stg5_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(back_inval_stg5_offset), + scout => sov(back_inval_stg5_offset), + din => back_inval_stg5_d, + dout => back_inval_stg5_q); +binv4_ex4_xuop_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv4_ex4_xuop_upd_offset), + scout => sov(binv4_ex4_xuop_upd_offset), + din => binv4_ex4_xuop_upd_d, + dout => binv4_ex4_xuop_upd_q); +binv4_ex4_dir_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv4_ex4_dir_val_offset), + scout => sov(binv4_ex4_dir_val_offset), + din => binv4_ex4_dir_val_d, + dout => binv4_ex4_dir_val_q); +ex4_dir_err_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_dir_err_val_offset), + scout => sov(ex4_dir_err_val_offset), + din => ex4_dir_err_val_d, + dout => ex4_dir_err_val_q); +ex5_dir_err_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_dir_err_val_offset), + scout => sov(ex5_dir_err_val_offset), + din => ex5_dir_err_val_d, + dout => ex5_dir_err_val_q); +ex6_dir_err_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_dir_err_val_offset), + scout => sov(ex6_dir_err_val_offset), + din => ex6_dir_err_val_d, + dout => ex6_dir_err_val_q); +derr2_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(derr2_stg_act_offset), + scout => sov(derr2_stg_act_offset), + din => derr2_stg_act_d, + dout => derr2_stg_act_q); +derr3_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(derr3_stg_act_offset), + scout => sov(derr3_stg_act_offset), + din => derr3_stg_act_d, + dout => derr3_stg_act_q); +derr4_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(derr4_stg_act_offset), + scout => sov(derr4_stg_act_offset), + din => derr4_stg_act_d, + dout => derr4_stg_act_q); +derr5_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(derr5_stg_act_offset), + scout => sov(derr5_stg_act_offset), + din => derr5_stg_act_d, + dout => derr5_stg_act_q); +my_multihit_lcb : entity tri.tri_lcbnd(tri_lcbnd) +generic map (expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + d1clk => my_multihit_d1clk, + d2clk => my_multihit_d2clk, + lclk => my_multihit_lclk); +ex4_dir_multihit_val_b_reg: entity tri.tri_inv_nlats(tri_inv_nlats) +generic map (width => 1, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + lclk => my_multihit_lclk, + d1clk => my_multihit_d1clk, + d2clk => my_multihit_d2clk, + scanin(0) => siv(ex4_dir_multihit_val_b_offset), + scanout(0) => sov(ex4_dir_multihit_val_b_offset), + d(0) => ex3_dir_multihit_val, + qb(0) => ex4_dir_multihit_val_b_q); +my_ddmh_lcb : entity tri.tri_lcbnd(tri_lcbnd) +generic map (expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + d1clk => my_ddmh_d1clk, + d2clk => my_ddmh_d2clk, + lclk => my_ddmh_lclk); +ex4_n_lsu_ddmh_flush_b_reg: entity tri.tri_inv_nlats(tri_inv_nlats) +generic map (width => 4, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + lclk => my_ddmh_lclk, + d1clk => my_ddmh_d1clk, + d2clk => my_ddmh_d2clk, + scanin => siv(ex4_n_lsu_ddmh_flush_b_offset to ex4_n_lsu_ddmh_flush_b_offset + ex4_n_lsu_ddmh_flush_b_d'length-1), + scanout => sov(ex4_n_lsu_ddmh_flush_b_offset to ex4_n_lsu_ddmh_flush_b_offset + ex4_n_lsu_ddmh_flush_b_d'length-1), + d => ex4_n_lsu_ddmh_flush_b_d, + qb => ex4_n_lsu_ddmh_flush_b_q); +dcarr_up_way_addr_reg: entity tri.tri_aoi22_nlats +generic map (width => 3, init => "000", expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + lclk => my_ddmh_lclk, + d1clk => my_ddmh_d1clk, + d2clk => my_ddmh_d2clk, + scanin => siv(dcarr_up_way_addr_offset to dcarr_up_way_addr_offset + dcarr_up_way_addr_q'length-1), + scanout => sov(dcarr_up_way_addr_offset to dcarr_up_way_addr_offset + dcarr_up_way_addr_q'length-1), + a1 => rel_up_way_addr_b, + a2 => rel_dcarr_addr_sel, + b1 => ex3_xuop_up_addr_b, + b2 => rel_dcarr_addr_sel_b, + qb => dcarr_up_way_addr_q); +reload_wayA_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayA_d, + dout => reload_wayA_q); +reload_wayB_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayB_d, + dout => reload_wayB_q); +reload_wayC_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayC_d, + dout => reload_wayC_q); +reload_wayD_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayD_d, + dout => reload_wayD_q); +reload_wayE_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayE_d, + dout => reload_wayE_q); +reload_wayF_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayF_d, + dout => reload_wayF_q); +reload_wayG_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayG_d, + dout => reload_wayG_q); +reload_wayH_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayH_d, + dout => reload_wayH_q); +rel_wayA_val_stg_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_wayA_val_stg_d, + dout => rel_wayA_val_stg_q); +rel_wayB_val_stg_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_wayB_val_stg_d, + dout => rel_wayB_val_stg_q); +rel_wayC_val_stg_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_wayC_val_stg_d, + dout => rel_wayC_val_stg_q); +rel_wayD_val_stg_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_wayD_val_stg_d, + dout => rel_wayD_val_stg_q); +rel_wayE_val_stg_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_wayE_val_stg_d, + dout => rel_wayE_val_stg_q); +rel_wayF_val_stg_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_wayF_val_stg_d, + dout => rel_wayF_val_stg_q); +rel_wayG_val_stg_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_wayG_val_stg_d, + dout => rel_wayG_val_stg_q); +rel_wayH_val_stg_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_wayH_val_stg_d, + dout => rel_wayH_val_stg_q); +reload_wayA_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_perr_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayA_data_offset to reload_wayA_data_offset + reload_wayA_data_d'length-1), + scout => sov(reload_wayA_data_offset to reload_wayA_data_offset + reload_wayA_data_d'length-1), + din => reload_wayA_data_d, + dout => reload_wayA_data_q); +reload_wayB_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_perr_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayB_data_offset to reload_wayB_data_offset + reload_wayB_data_d'length-1), + scout => sov(reload_wayB_data_offset to reload_wayB_data_offset + reload_wayB_data_d'length-1), + din => reload_wayB_data_d, + dout => reload_wayB_data_q); +reload_wayC_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_perr_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayC_data_offset to reload_wayC_data_offset + reload_wayC_data_d'length-1), + scout => sov(reload_wayC_data_offset to reload_wayC_data_offset + reload_wayC_data_d'length-1), + din => reload_wayC_data_d, + dout => reload_wayC_data_q); +reload_wayD_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_perr_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayD_data_offset to reload_wayD_data_offset + reload_wayD_data_d'length-1), + scout => sov(reload_wayD_data_offset to reload_wayD_data_offset + reload_wayD_data_d'length-1), + din => reload_wayD_data_d, + dout => reload_wayD_data_q); +reload_wayE_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_perr_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayE_data_offset to reload_wayE_data_offset + reload_wayE_data_d'length-1), + scout => sov(reload_wayE_data_offset to reload_wayE_data_offset + reload_wayE_data_d'length-1), + din => reload_wayE_data_d, + dout => reload_wayE_data_q); +reload_wayF_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_perr_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayF_data_offset to reload_wayF_data_offset + reload_wayF_data_d'length-1), + scout => sov(reload_wayF_data_offset to reload_wayF_data_offset + reload_wayF_data_d'length-1), + din => reload_wayF_data_d, + dout => reload_wayF_data_q); +reload_wayG_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_perr_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayG_data_offset to reload_wayG_data_offset + reload_wayG_data_d'length-1), + scout => sov(reload_wayG_data_offset to reload_wayG_data_offset + reload_wayG_data_d'length-1), + din => reload_wayG_data_d, + dout => reload_wayG_data_q); +reload_wayH_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_perr_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayH_data_offset to reload_wayH_data_offset + reload_wayH_data_d'length-1), + scout => sov(reload_wayH_data_offset to reload_wayH_data_offset + reload_wayH_data_d'length-1), + din => reload_wayH_data_d, + dout => reload_wayH_data_q); +reload_wayA_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel4_perr_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayA_data2_d, + dout => reload_wayA_data2_q); +reload_wayB_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel4_perr_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayB_data2_d, + dout => reload_wayB_data2_q); +reload_wayC_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel4_perr_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayC_data2_d, + dout => reload_wayC_data2_q); +reload_wayD_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel4_perr_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayD_data2_d, + dout => reload_wayD_data2_q); +reload_wayE_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel4_perr_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayE_data2_d, + dout => reload_wayE_data2_q); +reload_wayF_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel4_perr_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayF_data2_d, + dout => reload_wayF_data2_q); +reload_wayG_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel4_perr_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayG_data2_d, + dout => reload_wayG_data2_q); +reload_wayH_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel4_perr_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayH_data2_d, + dout => reload_wayH_data2_q); +binv_wayA_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayA_upd_offset), + scout => sov(binv_wayA_upd_offset), + din => binv_wayA_upd_d, + dout => binv_wayA_upd_q); +binv_wayB_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayB_upd_offset), + scout => sov(binv_wayB_upd_offset), + din => binv_wayB_upd_d, + dout => binv_wayB_upd_q); +binv_wayC_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayC_upd_offset), + scout => sov(binv_wayC_upd_offset), + din => binv_wayC_upd_d, + dout => binv_wayC_upd_q); +binv_wayD_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayD_upd_offset), + scout => sov(binv_wayD_upd_offset), + din => binv_wayD_upd_d, + dout => binv_wayD_upd_q); +binv_wayE_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayE_upd_offset), + scout => sov(binv_wayE_upd_offset), + din => binv_wayE_upd_d, + dout => binv_wayE_upd_q); +binv_wayF_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayF_upd_offset), + scout => sov(binv_wayF_upd_offset), + din => binv_wayF_upd_d, + dout => binv_wayF_upd_q); +binv_wayG_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayG_upd_offset), + scout => sov(binv_wayG_upd_offset), + din => binv_wayG_upd_d, + dout => binv_wayG_upd_q); +binv_wayH_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayH_upd_offset), + scout => sov(binv_wayH_upd_offset), + din => binv_wayH_upd_d, + dout => binv_wayH_upd_q); +binv_wayA_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayA_upd2_offset), + scout => sov(binv_wayA_upd2_offset), + din => binv_wayA_upd2_d, + dout => binv_wayA_upd2_q); +binv_wayB_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayB_upd2_offset), + scout => sov(binv_wayB_upd2_offset), + din => binv_wayB_upd2_d, + dout => binv_wayB_upd2_q); +binv_wayC_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayC_upd2_offset), + scout => sov(binv_wayC_upd2_offset), + din => binv_wayC_upd2_d, + dout => binv_wayC_upd2_q); +binv_wayD_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayD_upd2_offset), + scout => sov(binv_wayD_upd2_offset), + din => binv_wayD_upd2_d, + dout => binv_wayD_upd2_q); +binv_wayE_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayE_upd2_offset), + scout => sov(binv_wayE_upd2_offset), + din => binv_wayE_upd2_d, + dout => binv_wayE_upd2_q); +binv_wayF_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayF_upd2_offset), + scout => sov(binv_wayF_upd2_offset), + din => binv_wayF_upd2_d, + dout => binv_wayF_upd2_q); +binv_wayG_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayG_upd2_offset), + scout => sov(binv_wayG_upd2_offset), + din => binv_wayG_upd2_d, + dout => binv_wayG_upd2_q); +binv_wayH_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayH_upd2_offset), + scout => sov(binv_wayH_upd2_offset), + din => binv_wayH_upd2_d, + dout => binv_wayH_upd2_q); +binv_wayA_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayA_upd3_offset), + scout => sov(binv_wayA_upd3_offset), + din => binv_wayA_upd3_d, + dout => binv_wayA_upd3_q); +binv_wayB_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayB_upd3_offset), + scout => sov(binv_wayB_upd3_offset), + din => binv_wayB_upd3_d, + dout => binv_wayB_upd3_q); +binv_wayC_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayC_upd3_offset), + scout => sov(binv_wayC_upd3_offset), + din => binv_wayC_upd3_d, + dout => binv_wayC_upd3_q); +binv_wayD_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayD_upd3_offset), + scout => sov(binv_wayD_upd3_offset), + din => binv_wayD_upd3_d, + dout => binv_wayD_upd3_q); +binv_wayE_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayE_upd3_offset), + scout => sov(binv_wayE_upd3_offset), + din => binv_wayE_upd3_d, + dout => binv_wayE_upd3_q); +binv_wayF_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayF_upd3_offset), + scout => sov(binv_wayF_upd3_offset), + din => binv_wayF_upd3_d, + dout => binv_wayF_upd3_q); +binv_wayG_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayG_upd3_offset), + scout => sov(binv_wayG_upd3_offset), + din => binv_wayG_upd3_d, + dout => binv_wayG_upd3_q); +binv_wayH_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayH_upd3_offset), + scout => sov(binv_wayH_upd3_offset), + din => binv_wayH_upd3_d, + dout => binv_wayH_upd3_q); +reload_wayA_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayA_upd_offset), + scout => sov(reload_wayA_upd_offset), + din => reload_wayA_upd_d, + dout => reload_wayA_upd_q); +reload_wayB_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayB_upd_offset), + scout => sov(reload_wayB_upd_offset), + din => reload_wayB_upd_d, + dout => reload_wayB_upd_q); +reload_wayC_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayC_upd_offset), + scout => sov(reload_wayC_upd_offset), + din => reload_wayC_upd_d, + dout => reload_wayC_upd_q); +reload_wayD_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayD_upd_offset), + scout => sov(reload_wayD_upd_offset), + din => reload_wayD_upd_d, + dout => reload_wayD_upd_q); +reload_wayE_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayE_upd_offset), + scout => sov(reload_wayE_upd_offset), + din => reload_wayE_upd_d, + dout => reload_wayE_upd_q); +reload_wayF_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayF_upd_offset), + scout => sov(reload_wayF_upd_offset), + din => reload_wayF_upd_d, + dout => reload_wayF_upd_q); +reload_wayG_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayG_upd_offset), + scout => sov(reload_wayG_upd_offset), + din => reload_wayG_upd_d, + dout => reload_wayG_upd_q); +reload_wayH_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayH_upd_offset), + scout => sov(reload_wayH_upd_offset), + din => reload_wayH_upd_d, + dout => reload_wayH_upd_q); +reload_wayA_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayA_upd2_offset), + scout => sov(reload_wayA_upd2_offset), + din => reload_wayA_upd2_d, + dout => reload_wayA_upd2_q); +reload_wayB_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayB_upd2_offset), + scout => sov(reload_wayB_upd2_offset), + din => reload_wayB_upd2_d, + dout => reload_wayB_upd2_q); +reload_wayC_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayC_upd2_offset), + scout => sov(reload_wayC_upd2_offset), + din => reload_wayC_upd2_d, + dout => reload_wayC_upd2_q); +reload_wayD_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayD_upd2_offset), + scout => sov(reload_wayD_upd2_offset), + din => reload_wayD_upd2_d, + dout => reload_wayD_upd2_q); +reload_wayE_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayE_upd2_offset), + scout => sov(reload_wayE_upd2_offset), + din => reload_wayE_upd2_d, + dout => reload_wayE_upd2_q); +reload_wayF_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayF_upd2_offset), + scout => sov(reload_wayF_upd2_offset), + din => reload_wayF_upd2_d, + dout => reload_wayF_upd2_q); +reload_wayG_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayG_upd2_offset), + scout => sov(reload_wayG_upd2_offset), + din => reload_wayG_upd2_d, + dout => reload_wayG_upd2_q); +reload_wayH_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayH_upd2_offset), + scout => sov(reload_wayH_upd2_offset), + din => reload_wayH_upd2_d, + dout => reload_wayH_upd2_q); +reload_wayA_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayA_upd3_offset), + scout => sov(reload_wayA_upd3_offset), + din => reload_wayA_upd3_d, + dout => reload_wayA_upd3_q); +reload_wayB_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayB_upd3_offset), + scout => sov(reload_wayB_upd3_offset), + din => reload_wayB_upd3_d, + dout => reload_wayB_upd3_q); +reload_wayC_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayC_upd3_offset), + scout => sov(reload_wayC_upd3_offset), + din => reload_wayC_upd3_d, + dout => reload_wayC_upd3_q); +reload_wayD_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayD_upd3_offset), + scout => sov(reload_wayD_upd3_offset), + din => reload_wayD_upd3_d, + dout => reload_wayD_upd3_q); +reload_wayE_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayE_upd3_offset), + scout => sov(reload_wayE_upd3_offset), + din => reload_wayE_upd3_d, + dout => reload_wayE_upd3_q); +reload_wayF_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayF_upd3_offset), + scout => sov(reload_wayF_upd3_offset), + din => reload_wayF_upd3_d, + dout => reload_wayF_upd3_q); +reload_wayG_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayG_upd3_offset), + scout => sov(reload_wayG_upd3_offset), + din => reload_wayG_upd3_d, + dout => reload_wayG_upd3_q); +reload_wayH_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayH_upd3_offset), + scout => sov(reload_wayH_upd3_offset), + din => reload_wayH_upd3_d, + dout => reload_wayH_upd3_q); +ex3_store_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_store_instr_offset), + scout => sov(ex3_store_instr_offset), + din => ex3_store_instr_d, + dout => ex3_store_instr_q); +ex3_lock_set_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_lock_set_offset), + scout => sov(ex3_lock_set_offset), + din => ex3_lock_set_d, + dout => ex3_lock_set_q); +ex4_lock_set_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_lock_set_offset), + scout => sov(ex4_lock_set_offset), + din => ex4_lock_set_d, + dout => ex4_lock_set_q); +ex5_lock_set_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_lock_set_offset), + scout => sov(ex5_lock_set_offset), + din => ex5_lock_set_d, + dout => ex5_lock_set_q); +ex3_lock_clr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_lock_clr_offset), + scout => sov(ex3_lock_clr_offset), + din => ex3_lock_clr_d, + dout => ex3_lock_clr_q); +ex3_xuop_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_xuop_val_offset), + scout => sov(ex3_xuop_val_offset), + din => ex3_xuop_val_d, + dout => ex3_xuop_val_q); +ex4_xuop_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_xuop_val_offset), + scout => sov(ex4_xuop_val_offset), + din => ex4_xuop_val_d, + dout => ex4_xuop_val_q); +ex5_xuop_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_xuop_val_offset), + scout => sov(ex5_xuop_val_offset), + din => ex5_xuop_val_d, + dout => ex5_xuop_val_q); +ex4_l_fld_b1_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex4_l_fld_b1_d, + dout(0) => ex4_l_fld_b1_q); +ex4_instr_enc_reg: tri_regk +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex4_instr_enc_d, + dout => ex4_instr_enc_q); +rel_lock_set_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_lock_set_offset), + scout => sov(rel_lock_set_offset), + din => rel_lock_set_d, + dout => rel_lock_set_q); +dcpar_err_stg1_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dcpar_err_stg1_offset), + scout => sov(dcpar_err_stg1_offset), + din => dcpar_err_stg1_d, + dout => dcpar_err_stg1_q); +dcpar_err_stg2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dcpar_err_stg2_offset), + scout => sov(dcpar_err_stg2_offset), + din => dcpar_err_stg2_d, + dout => dcpar_err_stg2_q); +dcpar_err_way_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dcpar_err_way_offset to dcpar_err_way_offset + dcpar_err_way_d'length-1), + scout => sov(dcpar_err_way_offset to dcpar_err_way_offset + dcpar_err_way_d'length-1), + din => dcpar_err_way_d, + dout => dcpar_err_way_q); +dcpar_err_way_inval_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dcpar_err_way_inval_offset to dcpar_err_way_inval_offset + dcpar_err_way_inval_d'length-1), + scout => sov(dcpar_err_way_inval_offset to dcpar_err_way_inval_offset + dcpar_err_way_inval_d'length-1), + din => dcpar_err_way_inval_d, + dout => dcpar_err_way_inval_q); +dcpar_err_cntr_reg: tri_rlmreg_p +generic map (width => 2, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dcpar_err_cntr_offset to dcpar_err_cntr_offset + dcpar_err_cntr_d'length-1), + scout => sov(dcpar_err_cntr_offset to dcpar_err_cntr_offset + dcpar_err_cntr_d'length-1), + din => dcpar_err_cntr_d, + dout => dcpar_err_cntr_q); +dcpar_err_ind_sel_reg: tri_rlmreg_p +generic map (width => 2, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dcpar_err_ind_sel_offset to dcpar_err_ind_sel_offset + dcpar_err_ind_sel_d'length-1), + scout => sov(dcpar_err_ind_sel_offset to dcpar_err_ind_sel_offset + dcpar_err_ind_sel_d'length-1), + din => dcpar_err_ind_sel_d, + dout => dcpar_err_ind_sel_q); +dcpar_err_push_queue_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dcpar_err_push_queue_offset), + scout => sov(dcpar_err_push_queue_offset), + din => dcpar_err_push_queue_d, + dout => dcpar_err_push_queue_q); +ex4_way_hit_reg: tri_regk +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex4_way_hit_d, + dout => ex4_way_hit_q); +ex5_way_hit_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv4_ex4_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_way_hit_offset to ex5_way_hit_offset + ex5_way_hit_d'length-1), + scout => sov(ex5_way_hit_offset to ex5_way_hit_offset + ex5_way_hit_d'length-1), + din => ex5_way_hit_d, + dout => ex5_way_hit_q); +ex6_way_hit_reg: tri_regk +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex5_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex6_way_hit_d, + dout => ex6_way_hit_q); +ex7_way_hit_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex7_way_hit_offset to ex7_way_hit_offset + ex7_way_hit_d'length-1), + scout => sov(ex7_way_hit_offset to ex7_way_hit_offset + ex7_way_hit_d'length-1), + din => ex7_way_hit_d, + dout => ex7_way_hit_q); +ex8_way_hit_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex8_way_hit_offset to ex8_way_hit_offset + ex8_way_hit_d'length-1), + scout => sov(ex8_way_hit_offset to ex8_way_hit_offset + ex8_way_hit_d'length-1), + din => ex8_way_hit_d, + dout => ex8_way_hit_q); +ex9_way_hit_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex9_way_hit_offset to ex9_way_hit_offset + ex9_way_hit_d'length-1), + scout => sov(ex9_way_hit_offset to ex9_way_hit_offset + ex9_way_hit_d'length-1), + din => ex9_way_hit_d, + dout => ex9_way_hit_q); +ex4_lose_watch_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_lose_watch_offset to ex4_lose_watch_offset + ex4_lose_watch_d'length-1), + scout => sov(ex4_lose_watch_offset to ex4_lose_watch_offset + ex4_lose_watch_d'length-1), + din => ex4_lose_watch_d, + dout => ex4_lose_watch_q); +xucr0_cslc_xuop_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xucr0_cslc_xuop_offset), + scout => sov(xucr0_cslc_xuop_offset), + din => xucr0_cslc_xuop_d, + dout => xucr0_cslc_xuop_q); +xucr0_cslc_binv_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(xucr0_cslc_binv_offset), + scout => sov(xucr0_cslc_binv_offset), + din => xucr0_cslc_binv_d, + dout => xucr0_cslc_binv_q); +dci_compl_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dci_compl_offset), + scout => sov(dci_compl_offset), + din => dci_compl_d, + dout => dci_compl_q); +dci_inval_all_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dci_inval_all_offset), + scout => sov(dci_inval_all_offset), + din => dci_inval_all_d, + dout => dci_inval_all_q); +inv2_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(inv2_val_offset), + scout => sov(inv2_val_offset), + din => inv2_val_d, + dout => inv2_val_q); +perf_lsu_evnts_reg: tri_rlmreg_p +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(perf_lsu_evnts_offset to perf_lsu_evnts_offset + perf_lsu_evnts_d'length-1), + scout => sov(perf_lsu_evnts_offset to perf_lsu_evnts_offset + perf_lsu_evnts_d'length-1), + din => perf_lsu_evnts_d, + dout => perf_lsu_evnts_q); +lock_flash_clear_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(lock_flash_clear_offset), + scout => sov(lock_flash_clear_offset), + din => lock_flash_clear_d, + dout => lock_flash_clear_q); +lock_flash_clear_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(lock_flash_clear_val_offset), + scout => sov(lock_flash_clear_val_offset), + din => lock_flash_clear_val_d, + dout => lock_flash_clear_val_q); +rel_port_wren_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_port_wren_offset), + scout => sov(rel_port_wren_offset), + din => rel_port_wren_d, + dout => rel_port_wren_q); +ex2_thrd_id_reg: tri_regk +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex2_thrd_id_d, + dout => ex2_thrd_id_q); +ex3_thrd_id_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_thrd_id_offset to ex3_thrd_id_offset + ex3_thrd_id_d'length-1), + scout => sov(ex3_thrd_id_offset to ex3_thrd_id_offset + ex3_thrd_id_d'length-1), + din => ex3_thrd_id_d, + dout => ex3_thrd_id_q); +ex4_thrd_id_reg: tri_regk +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex4_thrd_id_d, + dout => ex4_thrd_id_q); +ex5_thrd_id_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_thrd_id_offset to ex5_thrd_id_offset + ex5_thrd_id_d'length-1), + scout => sov(ex5_thrd_id_offset to ex5_thrd_id_offset + ex5_thrd_id_d'length-1), + din => ex5_thrd_id_d, + dout => ex5_thrd_id_q); +ex3_l_fld_b1_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_l_fld_b1_offset), + scout => sov(ex3_l_fld_b1_offset), + din => ex3_l_fld_b1_d, + dout => ex3_l_fld_b1_q); +ex3_watch_set_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_watch_set_offset), + scout => sov(ex3_watch_set_offset), + din => ex3_watch_set_d, + dout => ex3_watch_set_q); +ex4_watch_set_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_watch_set_offset), + scout => sov(ex4_watch_set_offset), + din => ex4_watch_set_d, + dout => ex4_watch_set_q); +ex5_watch_set_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_watch_set_offset), + scout => sov(ex5_watch_set_offset), + din => ex5_watch_set_d, + dout => ex5_watch_set_q); +ex3_watch_clr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_watch_clr_offset), + scout => sov(ex3_watch_clr_offset), + din => ex3_watch_clr_d, + dout => ex3_watch_clr_q); +ex3_watch_clr_all_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_watch_clr_all_offset), + scout => sov(ex3_watch_clr_all_offset), + din => ex3_watch_clr_all_d, + dout => ex3_watch_clr_all_q); +ex3_watch_chk_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_watch_chk_offset), + scout => sov(ex3_watch_chk_offset), + din => ex3_watch_chk_d, + dout => ex3_watch_chk_q); +ex4_watch_chk_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_watch_chk_offset), + scout => sov(ex4_watch_chk_offset), + din => ex4_watch_chk_d, + dout => ex4_watch_chk_q); +ex5_watch_chk_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_watch_chk_offset), + scout => sov(ex5_watch_chk_offset), + din => ex5_watch_chk_d, + dout => ex5_watch_chk_q); +ex3_wclr_all_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wclr_all_upd_offset), + scout => sov(ex3_wclr_all_upd_offset), + din => ex3_wclr_all_upd_d, + dout => ex3_wclr_all_upd_q); +ex4_wclr_all_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_wclr_all_val_offset), + scout => sov(ex4_wclr_all_val_offset), + din => ex4_wclr_all_val_d, + dout => ex4_wclr_all_val_q); +ex5_wclr_all_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_wclr_all_val_offset), + scout => sov(ex5_wclr_all_val_offset), + din => ex5_wclr_all_val_d, + dout => ex5_wclr_all_val_q); +ex6_wclr_all_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_wclr_all_val_offset), + scout => sov(ex6_wclr_all_val_offset), + din => ex6_wclr_all_val_d, + dout => ex6_wclr_all_val_q); +rel_thrd_id_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_thrd_id_offset to rel_thrd_id_offset + rel_thrd_id_d'length-1), + scout => sov(rel_thrd_id_offset to rel_thrd_id_offset + rel_thrd_id_d'length-1), + din => rel_thrd_id_d, + dout => rel_thrd_id_q); +rel_watch_set_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_watch_set_offset), + scout => sov(rel_watch_set_offset), + din => rel_watch_set_d, + dout => rel_watch_set_q); +ex5_cr_watch_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_cr_watch_offset), + scout => sov(ex5_cr_watch_offset), + din => ex5_cr_watch_d, + dout => ex5_cr_watch_q); +ex4_watch_clr_all_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_watch_clr_all_offset to ex4_watch_clr_all_offset + ex4_watch_clr_all_d'length-1), + scout => sov(ex4_watch_clr_all_offset to ex4_watch_clr_all_offset + ex4_watch_clr_all_d'length-1), + din => ex4_watch_clr_all_d, + dout => ex4_watch_clr_all_q); +ex5_watch_clr_all_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_watch_clr_all_offset to ex5_watch_clr_all_offset + ex5_watch_clr_all_d'length-1), + scout => sov(ex5_watch_clr_all_offset to ex5_watch_clr_all_offset + ex5_watch_clr_all_d'length-1), + din => ex5_watch_clr_all_d, + dout => ex5_watch_clr_all_q); +ex6_watch_clr_all_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_watch_clr_all_offset to ex6_watch_clr_all_offset + ex6_watch_clr_all_d'length-1), + scout => sov(ex6_watch_clr_all_offset to ex6_watch_clr_all_offset + ex6_watch_clr_all_d'length-1), + din => ex6_watch_clr_all_d, + dout => ex6_watch_clr_all_q); +ex5_watch_clr_all_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_watch_clr_all_val_offset), + scout => sov(ex5_watch_clr_all_val_offset), + din => ex5_watch_clr_all_val_d, + dout => ex5_watch_clr_all_val_q); +ex5_lost_watch_upd_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_lost_watch_upd_offset to ex5_lost_watch_upd_offset + ex5_lost_watch_upd_d'length-1), + scout => sov(ex5_lost_watch_upd_offset to ex5_lost_watch_upd_offset + ex5_lost_watch_upd_d'length-1), + din => ex5_lost_watch_upd_d, + dout => ex5_lost_watch_upd_q); +ex4_watchlost_set_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_watchlost_set_offset to ex4_watchlost_set_offset + ex4_watchlost_set_d'length-1), + scout => sov(ex4_watchlost_set_offset to ex4_watchlost_set_offset + ex4_watchlost_set_d'length-1), + din => ex4_watchlost_set_d, + dout => ex4_watchlost_set_q); +ex5_watchlost_set_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_watchlost_set_offset to ex5_watchlost_set_offset + ex5_watchlost_set_d'length-1), + scout => sov(ex5_watchlost_set_offset to ex5_watchlost_set_offset + ex5_watchlost_set_d'length-1), + din => ex5_watchlost_set_d, + dout => ex5_watchlost_set_q); +rel_lost_watch_binv_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_lost_watch_binv_offset to rel_lost_watch_binv_offset + rel_lost_watch_binv_d'length-1), + scout => sov(rel_lost_watch_binv_offset to rel_lost_watch_binv_offset + rel_lost_watch_binv_d'length-1), + din => rel_lost_watch_binv_d, + dout => rel_lost_watch_binv_q); +lost_watch_evict_ovl_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(lost_watch_evict_ovl_offset to lost_watch_evict_ovl_offset + lost_watch_evict_ovl_d'length-1), + scout => sov(lost_watch_evict_ovl_offset to lost_watch_evict_ovl_offset + lost_watch_evict_ovl_d'length-1), + din => lost_watch_evict_ovl_d, + dout => lost_watch_evict_ovl_q); +rel_lost_watch_upd_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_lost_watch_upd_offset to rel_lost_watch_upd_offset + rel_lost_watch_upd_d'length-1), + scout => sov(rel_lost_watch_upd_offset to rel_lost_watch_upd_offset + rel_lost_watch_upd_d'length-1), + din => rel_lost_watch_upd_d, + dout => rel_lost_watch_upd_q); +lost_watch_evict_val_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(lost_watch_evict_val_offset to lost_watch_evict_val_offset + lost_watch_evict_val_d'length-1), + scout => sov(lost_watch_evict_val_offset to lost_watch_evict_val_offset + lost_watch_evict_val_d'length-1), + din => lost_watch_evict_val_d, + dout => lost_watch_evict_val_q); +lost_watch_inter_thrd_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(lost_watch_inter_thrd_offset to lost_watch_inter_thrd_offset + lost_watch_inter_thrd_d'length-1), + scout => sov(lost_watch_inter_thrd_offset to lost_watch_inter_thrd_offset + lost_watch_inter_thrd_d'length-1), + din => lost_watch_inter_thrd_d, + dout => lost_watch_inter_thrd_q); +stm_watchlost_state_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(stm_watchlost_state_offset to stm_watchlost_state_offset + stm_watchlost_state_d'length-1), + scout => sov(stm_watchlost_state_offset to stm_watchlost_state_offset + stm_watchlost_state_d'length-1), + din => stm_watchlost_state_d, + dout => stm_watchlost_state_q); +ex5_xuop_p0_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_xuop_p0_upd_offset), + scout => sov(ex5_xuop_p0_upd_offset), + din => ex5_xuop_p0_upd_d, + dout => ex5_xuop_p0_upd_q); +rel_val_stgu_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_val_stgu_offset), + scout => sov(rel_val_stgu_offset), + din => rel_val_stgu_d, + dout => rel_val_stgu_q); +p0_wren_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(p0_wren_offset), + scout => sov(p0_wren_offset), + din => p0_wren_d, + dout => p0_wren_q); +p0_wren_cpy_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(p0_wren_cpy_offset), + scout => sov(p0_wren_cpy_offset), + din => p0_wren_cpy_d, + dout => p0_wren_cpy_q); +p0_wren_stg_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(p0_wren_stg_offset), + scout => sov(p0_wren_stg_offset), + din => p0_wren_stg_d, + dout => p0_wren_stg_q); +p1_wren_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(p1_wren_offset), + scout => sov(p1_wren_offset), + din => p1_wren_d, + dout => p1_wren_q); +p1_wren_cpy_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(p1_wren_cpy_offset), + scout => sov(p1_wren_cpy_offset), + din => p1_wren_cpy_d, + dout => p1_wren_cpy_q); +ex3_thrd_m_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_thrd_m_offset), + scout => sov(ex3_thrd_m_offset), + din => ex3_thrd_m_d, + dout => ex3_thrd_m_q); +ex4_thrd_m_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_thrd_m_offset), + scout => sov(ex4_thrd_m_offset), + din => ex4_thrd_m_d, + dout => ex4_thrd_m_q); +ex5_thrd_m_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_thrd_m_offset), + scout => sov(ex5_thrd_m_offset), + din => ex5_thrd_m_d, + dout => ex5_thrd_m_q); +ex6_thrd_m_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_thrd_m_offset), + scout => sov(ex6_thrd_m_offset), + din => ex6_thrd_m_d, + dout => ex6_thrd_m_q); +ex7_ld_par_err_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex7_ld_par_err_offset), + scout => sov(ex7_ld_par_err_offset), + din => ex7_ld_par_err_d, + dout => ex7_ld_par_err_q); +ex8_ld_par_err_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex8_ld_par_err_offset), + scout => sov(ex8_ld_par_err_offset), + din => ex8_ld_par_err_d, + dout => ex8_ld_par_err_q); +ex9_ld_par_err_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex9_ld_par_err_offset), + scout => sov(ex9_ld_par_err_offset), + din => ex9_ld_par_err_d, + dout => ex9_ld_par_err_q); +ex6_ld_valid_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_ld_valid_offset), + scout => sov(ex6_ld_valid_offset), + din => ex6_ld_valid_d, + dout => ex6_ld_valid_q); +ex7_ld_valid_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex7_ld_valid_offset), + scout => sov(ex7_ld_valid_offset), + din => ex7_ld_valid_d, + dout => ex7_ld_valid_q); +ex8_ld_valid_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex8_ld_valid_offset), + scout => sov(ex8_ld_valid_offset), + din => ex8_ld_valid_d, + dout => ex8_ld_valid_q); +ex9_ld_valid_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex9_ld_valid_offset), + scout => sov(ex9_ld_valid_offset), + din => ex9_ld_valid_d, + dout => ex9_ld_valid_q); +rel_in_progress_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_in_progress_offset), + scout => sov(rel_in_progress_offset), + din => rel_in_progress_d, + dout => rel_in_progress_q); +inj_dir_multihit_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(inj_dir_multihit_offset), + scout => sov(inj_dir_multihit_offset), + din => inj_dir_multihit_d, + dout => inj_dir_multihit_q); +congr_cl_ex2_ex3_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex2_ex3_cmp_offset), + scout => sov(congr_cl_ex2_ex3_cmp_offset), + din => congr_cl_ex2_ex3_cmp_d, + dout => congr_cl_ex2_ex3_cmp_q); +congr_cl_ex2_ex4_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex2_ex4_cmp_offset), + scout => sov(congr_cl_ex2_ex4_cmp_offset), + din => congr_cl_ex2_ex4_cmp_d, + dout => congr_cl_ex2_ex4_cmp_q); +congr_cl_ex2_ex5_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex2_ex5_cmp_offset), + scout => sov(congr_cl_ex2_ex5_cmp_offset), + din => congr_cl_ex2_ex5_cmp_d, + dout => congr_cl_ex2_ex5_cmp_q); +congr_cl_ex2_ex6_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex2_ex6_cmp_offset), + scout => sov(congr_cl_ex2_ex6_cmp_offset), + din => congr_cl_ex2_ex6_cmp_d, + dout => congr_cl_ex2_ex6_cmp_q); +congr_cl_ex3_ex4_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex3_ex4_cmp_offset), + scout => sov(congr_cl_ex3_ex4_cmp_offset), + din => congr_cl_ex3_ex4_cmp_d, + dout => congr_cl_ex3_ex4_cmp_q); +congr_cl_ex3_ex5_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex3_ex5_cmp_offset), + scout => sov(congr_cl_ex3_ex5_cmp_offset), + din => congr_cl_ex3_ex5_cmp_d, + dout => congr_cl_ex3_ex5_cmp_q); +congr_cl_ex3_ex6_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex3_ex6_cmp_offset), + scout => sov(congr_cl_ex3_ex6_cmp_offset), + din => congr_cl_ex3_ex6_cmp_d, + dout => congr_cl_ex3_ex6_cmp_q); +congr_cl_ex4_ex5_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex4_ex5_cmp_offset), + scout => sov(congr_cl_ex4_ex5_cmp_offset), + din => congr_cl_ex4_ex5_cmp_d, + dout => congr_cl_ex4_ex5_cmp_q); +congr_cl_ex4_ex6_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex4_ex6_cmp_offset), + scout => sov(congr_cl_ex4_ex6_cmp_offset), + din => congr_cl_ex4_ex6_cmp_d, + dout => congr_cl_ex4_ex6_cmp_q); +congr_cl_ex4_ex7_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex4_ex7_cmp_offset), + scout => sov(congr_cl_ex4_ex7_cmp_offset), + din => congr_cl_ex4_ex7_cmp_d, + dout => congr_cl_ex4_ex7_cmp_q); +congr_cl_ex2_relu_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex2_relu_cmp_offset), + scout => sov(congr_cl_ex2_relu_cmp_offset), + din => congr_cl_ex2_relu_cmp_d, + dout => congr_cl_ex2_relu_cmp_q); +congr_cl_ex2_relu_s_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex2_relu_s_cmp_offset), + scout => sov(congr_cl_ex2_relu_s_cmp_offset), + din => congr_cl_ex2_relu_s_cmp_d, + dout => congr_cl_ex2_relu_s_cmp_q); +congr_cl_ex2_rel_upd_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex2_rel_upd_cmp_offset), + scout => sov(congr_cl_ex2_rel_upd_cmp_offset), + din => congr_cl_ex2_rel_upd_cmp_d, + dout => congr_cl_ex2_rel_upd_cmp_q); +congr_cl_rel13_ex3_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_rel13_ex3_cmp_offset), + scout => sov(congr_cl_rel13_ex3_cmp_offset), + din => congr_cl_rel13_ex3_cmp_d, + dout => congr_cl_rel13_ex3_cmp_q); +congr_cl_rel13_ex4_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_rel13_ex4_cmp_offset), + scout => sov(congr_cl_rel13_ex4_cmp_offset), + din => congr_cl_rel13_ex4_cmp_d, + dout => congr_cl_rel13_ex4_cmp_q); +congr_cl_rel13_ex5_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_rel13_ex5_cmp_offset), + scout => sov(congr_cl_rel13_ex5_cmp_offset), + din => congr_cl_rel13_ex5_cmp_d, + dout => congr_cl_rel13_ex5_cmp_q); +congr_cl_rel13_ex6_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_rel13_ex6_cmp_offset), + scout => sov(congr_cl_rel13_ex6_cmp_offset), + din => congr_cl_rel13_ex6_cmp_d, + dout => congr_cl_rel13_ex6_cmp_q); +congr_cl_rel13_relu_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_rel13_relu_cmp_offset), + scout => sov(congr_cl_rel13_relu_cmp_offset), + din => congr_cl_rel13_relu_cmp_d, + dout => congr_cl_rel13_relu_cmp_q); +congr_cl_rel13_relu_s_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_rel13_relu_s_cmp_offset), + scout => sov(congr_cl_rel13_relu_s_cmp_offset), + din => congr_cl_rel13_relu_s_cmp_d, + dout => congr_cl_rel13_relu_s_cmp_q); +congr_cl_rel13_rel_upd_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_rel13_rel_upd_cmp_offset), + scout => sov(congr_cl_rel13_rel_upd_cmp_offset), + din => congr_cl_rel13_rel_upd_cmp_d, + dout => congr_cl_rel13_rel_upd_cmp_q); +rel24_congr_cl_ex4_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel24_congr_cl_ex4_cmp_offset), + scout => sov(rel24_congr_cl_ex4_cmp_offset), + din => rel24_congr_cl_ex4_cmp_d, + dout => rel24_congr_cl_ex4_cmp_q); +rel24_congr_cl_ex5_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel24_congr_cl_ex5_cmp_offset), + scout => sov(rel24_congr_cl_ex5_cmp_offset), + din => rel24_congr_cl_ex5_cmp_d, + dout => rel24_congr_cl_ex5_cmp_q); +rel24_congr_cl_ex6_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel24_congr_cl_ex6_cmp_offset), + scout => sov(rel24_congr_cl_ex6_cmp_offset), + din => rel24_congr_cl_ex6_cmp_d, + dout => rel24_congr_cl_ex6_cmp_q); +relu_congr_cl_ex5_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(relu_congr_cl_ex5_cmp_offset), + scout => sov(relu_congr_cl_ex5_cmp_offset), + din => relu_congr_cl_ex5_cmp_d, + dout => relu_congr_cl_ex5_cmp_q); +relu_congr_cl_ex6_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(relu_congr_cl_ex6_cmp_offset), + scout => sov(relu_congr_cl_ex6_cmp_offset), + din => relu_congr_cl_ex6_cmp_d, + dout => relu_congr_cl_ex6_cmp_q); +relu_congr_cl_ex7_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(relu_congr_cl_ex7_cmp_offset), + scout => sov(relu_congr_cl_ex7_cmp_offset), + din => relu_congr_cl_ex7_cmp_d, + dout => relu_congr_cl_ex7_cmp_q); +ex4_err_det_way_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_err_det_way_offset to ex4_err_det_way_offset + ex4_err_det_way_d'length-1), + scout => sov(ex4_err_det_way_offset to ex4_err_det_way_offset + ex4_err_det_way_d'length-1), + din => ex4_err_det_way_d, + dout => ex4_err_det_way_q); +ex4_perr_lck_lost_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_perr_lck_lost_offset), + scout => sov(ex4_perr_lck_lost_offset), + din => ex4_perr_lck_lost_d, + dout => ex4_perr_lck_lost_q); +ex4_perr_watch_lost_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_perr_watch_lost_offset to ex4_perr_watch_lost_offset + ex4_perr_watch_lost_d'length-1), + scout => sov(ex4_perr_watch_lost_offset to ex4_perr_watch_lost_offset + ex4_perr_watch_lost_d'length-1), + din => ex4_perr_watch_lost_d, + dout => ex4_perr_watch_lost_q); +dcperr_lock_lost_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dcperr_lock_lost_offset), + scout => sov(dcperr_lock_lost_offset), + din => dcperr_lock_lost_d, + dout => dcperr_lock_lost_q); +binv7_ex7_way_upd_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv7_ex7_way_upd_offset to binv7_ex7_way_upd_offset + binv7_ex7_way_upd_d'length-1), + scout => sov(binv7_ex7_way_upd_offset to binv7_ex7_way_upd_offset + binv7_ex7_way_upd_d'length-1), + din => binv7_ex7_way_upd_d, + dout => binv7_ex7_way_upd_q); +binv5_ex5_dir_data_reg: tri_rlmreg_p +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv4_ex4_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv5_ex5_dir_data_offset to binv5_ex5_dir_data_offset + binv5_ex5_dir_data_d'length-1), + scout => sov(binv5_ex5_dir_data_offset to binv5_ex5_dir_data_offset + binv5_ex5_dir_data_d'length-1), + din => binv5_ex5_dir_data_d, + dout => binv5_ex5_dir_data_q); +binv6_ex6_dir_data_reg: tri_regk +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv5_ex5_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => binv6_ex6_dir_data_d, + dout => binv6_ex6_dir_data_q); +binv7_ex7_dir_data_reg: tri_rlmreg_p +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv7_ex7_dir_data_offset to binv7_ex7_dir_data_offset + binv7_ex7_dir_data_d'length-1), + scout => sov(binv7_ex7_dir_data_offset to binv7_ex7_dir_data_offset + binv7_ex7_dir_data_d'length-1), + din => binv7_ex7_dir_data_d, + dout => binv7_ex7_dir_data_q); +binv5_inval_watch_val_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv5_inval_watch_val_offset to binv5_inval_watch_val_offset + binv5_inval_watch_val_d'length-1), + scout => sov(binv5_inval_watch_val_offset to binv5_inval_watch_val_offset + binv5_inval_watch_val_d'length-1), + din => binv5_inval_watch_val_d, + dout => binv5_inval_watch_val_q); +binv5_inval_lock_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv5_inval_lock_val_offset), + scout => sov(binv5_inval_lock_val_offset), + din => binv5_inval_lock_val_d, + dout => binv5_inval_lock_val_q); +my_lcb : entity tri.tri_lcbnd(tri_lcbnd) +generic map (expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + d1clk => my_d1clk, + d2clk => my_d2clk, + lclk => my_lclk); +ex4_snd_ld_l2_reg: entity tri.tri_oai22_nlats(tri_oai22_nlats) +generic map (width => 1, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + lclk => my_lclk, + d1clk => my_d1clk, + d2clk => my_d2clk, + scanin(0) => siv(ex4_snd_ld_l2_offset), + scanout(0) => sov(ex4_snd_ld_l2_offset), + a1(0) => ex3_wimge_i_bit, + a2(0) => hit_or_01234567_b, + b1(0) => ex3_load_val, + b2(0) => ex3_load_val, + qb(0) => ex4_snd_ld_l2_q); +ex4_ldq_full_flush_b_reg: entity tri.tri_oai22_nlats(tri_oai22_nlats) +generic map (width => 1, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + lclk => my_lclk, + d1clk => my_d1clk, + d2clk => my_d2clk, + scanin(0) => siv(ex4_ldq_full_flush_b_offset), + scanout(0) => sov(ex4_ldq_full_flush_b_offset), + a1(0) => ex3_l2_request, + a2(0) => hit_or_01234567_b, + b1(0) => ex3_ldq_potential_flush, + b2(0) => ex3_ldq_potential_flush, + qb(0) => ex4_ldq_full_flush_b_q); +ex4_miss_reg: entity tri.tri_inv_nlats(tri_inv_nlats) +generic map (width => 1, init => "1", expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + lclk => my_lclk, + d1clk => my_d1clk, + d2clk => my_d2clk, + scanin(0) => ex4_miss_siv, + scanout(0) => ex4_miss_sov, + d(0) => ex3_l1miss, + qb(0) => ex4_miss_q); +ex4_miss_siv <= not siv(ex4_miss_offset); +sov(ex4_miss_offset) <= not ex4_miss_sov; +my_spare0_lcb : entity tri.tri_lcbnd(tri_lcbnd) +generic map (expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + d1clk => my_spare0_d1clk, + d2clk => my_spare0_d2clk, + lclk => my_spare0_lclk); +my_spare0_latches_reg: entity tri.tri_inv_nlats(tri_inv_nlats) +generic map (width => 17, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + lclk => my_spare0_lclk, + d1clk => my_spare0_d1clk, + d2clk => my_spare0_d2clk, + scanin => siv(my_spare0_latches_offset to my_spare0_latches_offset + my_spare0_latches_d'length-1), + scanout => sov(my_spare0_latches_offset to my_spare0_latches_offset + my_spare0_latches_d'length-1), + d => my_spare0_latches_d, + qb => my_spare0_latches_q); +my_spare1_lcb : entity tri.tri_lcbnd(tri_lcbnd) +generic map (expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + d1clk => my_spare1_d1clk, + d2clk => my_spare1_d2clk, + lclk => my_spare1_lclk); +my_spare1_latches_reg: entity tri.tri_inv_nlats(tri_inv_nlats) +generic map (width => 16, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + lclk => my_spare1_lclk, + d1clk => my_spare1_d1clk, + d2clk => my_spare1_d2clk, + scanin => siv(my_spare1_latches_offset to my_spare1_latches_offset + my_spare1_latches_d'length-1), + scanout => sov(my_spare1_latches_offset to my_spare1_latches_offset + my_spare1_latches_d'length-1), + d => my_spare1_latches_d, + qb => my_spare1_latches_q); +rel_l1dump_cslc_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_l1dump_cslc_offset), + scout => sov(rel_l1dump_cslc_offset), + din => rel_l1dump_cslc_d, + dout => rel_l1dump_cslc_q); +rel_in_prog_stg1_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_in_prog_stg1_offset), + scout => sov(rel_in_prog_stg1_offset), + din => rel_in_prog_stg1_d, + dout => rel_in_prog_stg1_q); +rel_in_prog_stg2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_in_prog_stg2_offset), + scout => sov(rel_in_prog_stg2_offset), + din => rel_in_prog_stg2_d, + dout => rel_in_prog_stg2_q); +rel_in_prog_stg3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_in_prog_stg3_offset), + scout => sov(rel_in_prog_stg3_offset), + din => rel_in_prog_stg3_d, + dout => rel_in_prog_stg3_q); +rel_in_prog_stg4_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_in_prog_stg4_offset), + scout => sov(rel_in_prog_stg4_offset), + din => rel_in_prog_stg4_d, + dout => rel_in_prog_stg4_q); +rel_in_prog_stg5_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_in_prog_stg5_offset), + scout => sov(rel_in_prog_stg5_offset), + din => rel_in_prog_stg5_d, + dout => rel_in_prog_stg5_q); +dcpar_err_stg1_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dcpar_err_stg1_act_offset), + scout => sov(dcpar_err_stg1_act_offset), + din => dcpar_err_stg1_act_d, + dout => dcpar_err_stg1_act_q); +dcpar_err_stg2_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dcpar_err_stg2_act_offset), + scout => sov(dcpar_err_stg2_act_offset), + din => dcpar_err_stg2_act_d, + dout => dcpar_err_stg2_act_q); +rel3_perr_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel3_perr_stg_act_offset), + scout => sov(rel3_perr_stg_act_offset), + din => rel3_perr_stg_act_d, + dout => rel3_perr_stg_act_q); +rel4_perr_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel4_perr_stg_act_offset), + scout => sov(rel4_perr_stg_act_offset), + din => rel4_perr_stg_act_d, + dout => rel4_perr_stg_act_q); +siv(0 TO 1247) <= sov(1 to 1247) & scan_in(0); +scan_out(0) <= sov(0); +siv(1248 TO scan_right) <= sov(1249 to scan_right) & scan_in(1); +scan_out(1) <= sov(1248); +scan_out(2) <= scan_in(2); +END XUQ_LSU_DIR_VAL16; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_dir_val32.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_dir_val32.vhdl new file mode 100644 index 0000000..054dd0e --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_dir_val32.vhdl @@ -0,0 +1,39548 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ibm, ieee, work, tri, support; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use tri.tri_latches_pkg.all; +use support.power_logic_pkg.all; + +entity xuq_lsu_dir_val32 is +generic(expand_type : integer := 2; + dc_size : natural := 15; + cl_size : natural := 6); +port( + + ex1_stg_act :in std_ulogic; + ex2_stg_act :in std_ulogic; + ex3_stg_act :in std_ulogic; + ex4_stg_act :in std_ulogic; + ex5_stg_act :in std_ulogic; + binv1_stg_act :in std_ulogic; + binv2_stg_act :in std_ulogic; + binv3_stg_act :in std_ulogic; + binv4_stg_act :in std_ulogic; + binv5_stg_act :in std_ulogic; + rel1_stg_act :in std_ulogic; + rel2_stg_act :in std_ulogic; + + ldq_rel1_early_v :in std_ulogic; + rel1_val :in std_ulogic; + rel_addr_early :in std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + rel_lock_en :in std_ulogic; + rel_l1dump_cslc :in std_ulogic; + rel3_l1dump_val :in std_ulogic; + rel4_ecc_err :in std_ulogic; + rel_watch_en :in std_ulogic; + rel_thrd_id :in std_ulogic_vector(0 to 3); + rel_way_clr_a :in std_ulogic; + rel_way_clr_b :in std_ulogic; + rel_way_clr_c :in std_ulogic; + rel_way_clr_d :in std_ulogic; + rel_way_clr_e :in std_ulogic; + rel_way_clr_f :in std_ulogic; + rel_way_clr_g :in std_ulogic; + rel_way_clr_h :in std_ulogic; + + ldq_rel3_early_v :in std_ulogic; + rel3_val :in std_ulogic; + rel_back_inval :in std_ulogic; + rel4_set_val :in std_ulogic; + rel4_recirc_val :in std_ulogic; + rel_way_wen_a :in std_ulogic; + rel_way_wen_b :in std_ulogic; + rel_way_wen_c :in std_ulogic; + rel_way_wen_d :in std_ulogic; + rel_way_wen_e :in std_ulogic; + rel_way_wen_f :in std_ulogic; + rel_way_wen_g :in std_ulogic; + rel_way_wen_h :in std_ulogic; + rel_up_way_addr_b :in std_ulogic_vector(0 to 2); + rel_dcarr_addr_en :in std_ulogic; + + xu_lsu_dci :in std_ulogic; + xu_lsu_spr_xucr0_clfc :in std_ulogic; + spr_xucr0_dcdis :in std_ulogic; + spr_xucr0_cls :in std_ulogic; + + ex1_thrd_id :in std_ulogic_vector(0 to 3); + ex1_p_addr :in std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + ex2_is_inval_op :in std_ulogic; + ex2_lock_set :in std_ulogic; + ex2_lock_clr :in std_ulogic; + ex3_cache_acc :in std_ulogic; + ex3_cache_en :in std_ulogic; + ex3_tag_way_perr :in std_ulogic_vector(0 to 7); + ex5_load_op_hit :in std_ulogic; + ex6_ld_par_err :in std_ulogic; + ex2_ldawx_instr :in std_ulogic; + ex2_wclr_instr :in std_ulogic; + ex2_wchk_val :in std_ulogic; + ex2_l_fld :in std_ulogic_vector(0 to 1); + ex2_store_instr :in std_ulogic; + ex3_load_val :in std_ulogic; + ex3_wimge_i_bit :in std_ulogic; + ex3_l2_request :in std_ulogic; + ex3_ldq_potential_flush :in std_ulogic; + + inv1_val :in std_ulogic; + + ex3_way_cmp_a :in std_ulogic; + ex3_way_cmp_b :in std_ulogic; + ex3_way_cmp_c :in std_ulogic; + ex3_way_cmp_d :in std_ulogic; + ex3_way_cmp_e :in std_ulogic; + ex3_way_cmp_f :in std_ulogic; + ex3_way_cmp_g :in std_ulogic; + ex3_way_cmp_h :in std_ulogic; + + ex2_stg_flush :in std_ulogic; + ex3_stg_flush :in std_ulogic; + ex4_stg_flush :in std_ulogic; + ex5_stg_flush :in std_ulogic; + + pc_xu_inj_dcachedir_multihit :in std_ulogic; + + ex4_way_a_dir :out std_ulogic_vector(0 to 5); + ex4_way_b_dir :out std_ulogic_vector(0 to 5); + ex4_way_c_dir :out std_ulogic_vector(0 to 5); + ex4_way_d_dir :out std_ulogic_vector(0 to 5); + ex4_way_e_dir :out std_ulogic_vector(0 to 5); + ex4_way_f_dir :out std_ulogic_vector(0 to 5); + ex4_way_g_dir :out std_ulogic_vector(0 to 5); + ex4_way_h_dir :out std_ulogic_vector(0 to 5); + + ex4_way_a_hit :out std_ulogic; + ex4_way_b_hit :out std_ulogic; + ex4_way_c_hit :out std_ulogic; + ex4_way_d_hit :out std_ulogic; + ex4_way_e_hit :out std_ulogic; + ex4_way_f_hit :out std_ulogic; + ex4_way_g_hit :out std_ulogic; + ex4_way_h_hit :out std_ulogic; + + ex3_cClass_upd_way_a :out std_ulogic; + ex3_cClass_upd_way_b :out std_ulogic; + ex3_cClass_upd_way_c :out std_ulogic; + ex3_cClass_upd_way_d :out std_ulogic; + ex3_cClass_upd_way_e :out std_ulogic; + ex3_cClass_upd_way_f :out std_ulogic; + ex3_cClass_upd_way_g :out std_ulogic; + ex3_cClass_upd_way_h :out std_ulogic; + + ex2_lockwatchSet_rel_coll :out std_ulogic; + ex3_wclr_all_flush :out std_ulogic; + + ex3_hit :out std_ulogic; + ex3_dir_perr_det :out std_ulogic; + ex4_dir_multihit_det :out std_ulogic; + ex4_n_lsu_ddmh_flush :out std_ulogic_vector(0 to 3); + ex4_ldq_full_flush :out std_ulogic; + ex4_miss :out std_ulogic; + ex4_snd_ld_l2 :out std_ulogic; + dcpar_err_flush :out std_ulogic; + pe_recov_begin :out std_ulogic; + + lsu_xu_ex5_cr_rslt :out std_ulogic; + + rel_way_val_a :out std_ulogic; + rel_way_val_b :out std_ulogic; + rel_way_val_c :out std_ulogic; + rel_way_val_d :out std_ulogic; + rel_way_val_e :out std_ulogic; + rel_way_val_f :out std_ulogic; + rel_way_val_g :out std_ulogic; + rel_way_val_h :out std_ulogic; + + rel_way_lock_a :out std_ulogic; + rel_way_lock_b :out std_ulogic; + rel_way_lock_c :out std_ulogic; + rel_way_lock_d :out std_ulogic; + rel_way_lock_e :out std_ulogic; + rel_way_lock_f :out std_ulogic; + rel_way_lock_g :out std_ulogic; + rel_way_lock_h :out std_ulogic; + + dcarr_up_way_addr :out std_ulogic_vector(0 to 2); + + lsu_xu_perf_events :out std_ulogic_vector(0 to 16); + + lsu_xu_spr_xucr0_cslc_xuop :out std_ulogic; + lsu_xu_spr_xucr0_cslc_binv :out std_ulogic; + + dc_val_dbg_data :out std_ulogic_vector(0 to 293); + + vdd :inout power_logic; + gnd :inout power_logic; + nclk :in clk_logic; + sg_0 :in std_ulogic; + func_sl_thold_0_b :in std_ulogic; + func_sl_force :in std_ulogic; + func_slp_sl_thold_0_b :in std_ulogic; + func_slp_sl_force :in std_ulogic; + func_nsl_thold_0_b :in std_ulogic; + func_nsl_force :in std_ulogic; + func_slp_nsl_thold_0_b :in std_ulogic; + func_slp_nsl_force :in std_ulogic; + d_mode_dc :in std_ulogic; + delay_lclkr_dc :in std_ulogic; + mpw1_dc_b :in std_ulogic; + mpw2_dc_b :in std_ulogic; + scan_in :in std_ulogic_vector(0 to 2); + scan_out :out std_ulogic_vector(0 to 2) + ); +-- synopsys translate_off +-- synopsys translate_on +end xuq_lsu_dir_val32; +ARCHITECTURE XUQ_LSU_DIR_VAL32 + OF XUQ_LSU_DIR_VAL32 + IS +constant congr_cl0_wA_offset :natural := 0; +constant congr_cl0_wB_offset :natural := congr_cl0_wA_offset + 6; +constant congr_cl0_wC_offset :natural := congr_cl0_wB_offset + 6; +constant congr_cl0_wD_offset :natural := congr_cl0_wC_offset + 6; +constant congr_cl0_wE_offset :natural := congr_cl0_wD_offset + 6; +constant congr_cl0_wF_offset :natural := congr_cl0_wE_offset + 6; +constant congr_cl0_wG_offset :natural := congr_cl0_wF_offset + 6; +constant congr_cl0_wH_offset :natural := congr_cl0_wG_offset + 6; +constant congr_cl1_wA_offset :natural := congr_cl0_wH_offset + 6; +constant congr_cl1_wB_offset :natural := congr_cl1_wA_offset + 6; +constant congr_cl1_wC_offset :natural := congr_cl1_wB_offset + 6; +constant congr_cl1_wD_offset :natural := congr_cl1_wC_offset + 6; +constant congr_cl1_wE_offset :natural := congr_cl1_wD_offset + 6; +constant congr_cl1_wF_offset :natural := congr_cl1_wE_offset + 6; +constant congr_cl1_wG_offset :natural := congr_cl1_wF_offset + 6; +constant congr_cl1_wH_offset :natural := congr_cl1_wG_offset + 6; +constant congr_cl2_wA_offset :natural := congr_cl1_wH_offset + 6; +constant congr_cl2_wB_offset :natural := congr_cl2_wA_offset + 6; +constant congr_cl2_wC_offset :natural := congr_cl2_wB_offset + 6; +constant congr_cl2_wD_offset :natural := congr_cl2_wC_offset + 6; +constant congr_cl2_wE_offset :natural := congr_cl2_wD_offset + 6; +constant congr_cl2_wF_offset :natural := congr_cl2_wE_offset + 6; +constant congr_cl2_wG_offset :natural := congr_cl2_wF_offset + 6; +constant congr_cl2_wH_offset :natural := congr_cl2_wG_offset + 6; +constant congr_cl3_wA_offset :natural := congr_cl2_wH_offset + 6; +constant congr_cl3_wB_offset :natural := congr_cl3_wA_offset + 6; +constant congr_cl3_wC_offset :natural := congr_cl3_wB_offset + 6; +constant congr_cl3_wD_offset :natural := congr_cl3_wC_offset + 6; +constant congr_cl3_wE_offset :natural := congr_cl3_wD_offset + 6; +constant congr_cl3_wF_offset :natural := congr_cl3_wE_offset + 6; +constant congr_cl3_wG_offset :natural := congr_cl3_wF_offset + 6; +constant congr_cl3_wH_offset :natural := congr_cl3_wG_offset + 6; +constant congr_cl4_wA_offset :natural := congr_cl3_wH_offset + 6; +constant congr_cl4_wB_offset :natural := congr_cl4_wA_offset + 6; +constant congr_cl4_wC_offset :natural := congr_cl4_wB_offset + 6; +constant congr_cl4_wD_offset :natural := congr_cl4_wC_offset + 6; +constant congr_cl4_wE_offset :natural := congr_cl4_wD_offset + 6; +constant congr_cl4_wF_offset :natural := congr_cl4_wE_offset + 6; +constant congr_cl4_wG_offset :natural := congr_cl4_wF_offset + 6; +constant congr_cl4_wH_offset :natural := congr_cl4_wG_offset + 6; +constant congr_cl5_wA_offset :natural := congr_cl4_wH_offset + 6; +constant congr_cl5_wB_offset :natural := congr_cl5_wA_offset + 6; +constant congr_cl5_wC_offset :natural := congr_cl5_wB_offset + 6; +constant congr_cl5_wD_offset :natural := congr_cl5_wC_offset + 6; +constant congr_cl5_wE_offset :natural := congr_cl5_wD_offset + 6; +constant congr_cl5_wF_offset :natural := congr_cl5_wE_offset + 6; +constant congr_cl5_wG_offset :natural := congr_cl5_wF_offset + 6; +constant congr_cl5_wH_offset :natural := congr_cl5_wG_offset + 6; +constant congr_cl6_wA_offset :natural := congr_cl5_wH_offset + 6; +constant congr_cl6_wB_offset :natural := congr_cl6_wA_offset + 6; +constant congr_cl6_wC_offset :natural := congr_cl6_wB_offset + 6; +constant congr_cl6_wD_offset :natural := congr_cl6_wC_offset + 6; +constant congr_cl6_wE_offset :natural := congr_cl6_wD_offset + 6; +constant congr_cl6_wF_offset :natural := congr_cl6_wE_offset + 6; +constant congr_cl6_wG_offset :natural := congr_cl6_wF_offset + 6; +constant congr_cl6_wH_offset :natural := congr_cl6_wG_offset + 6; +constant congr_cl7_wA_offset :natural := congr_cl6_wH_offset + 6; +constant congr_cl7_wB_offset :natural := congr_cl7_wA_offset + 6; +constant congr_cl7_wC_offset :natural := congr_cl7_wB_offset + 6; +constant congr_cl7_wD_offset :natural := congr_cl7_wC_offset + 6; +constant congr_cl7_wE_offset :natural := congr_cl7_wD_offset + 6; +constant congr_cl7_wF_offset :natural := congr_cl7_wE_offset + 6; +constant congr_cl7_wG_offset :natural := congr_cl7_wF_offset + 6; +constant congr_cl7_wH_offset :natural := congr_cl7_wG_offset + 6; +constant congr_cl8_wA_offset :natural := congr_cl7_wH_offset + 6; +constant congr_cl8_wB_offset :natural := congr_cl8_wA_offset + 6; +constant congr_cl8_wC_offset :natural := congr_cl8_wB_offset + 6; +constant congr_cl8_wD_offset :natural := congr_cl8_wC_offset + 6; +constant congr_cl8_wE_offset :natural := congr_cl8_wD_offset + 6; +constant congr_cl8_wF_offset :natural := congr_cl8_wE_offset + 6; +constant congr_cl8_wG_offset :natural := congr_cl8_wF_offset + 6; +constant congr_cl8_wH_offset :natural := congr_cl8_wG_offset + 6; +constant congr_cl9_wA_offset :natural := congr_cl8_wH_offset + 6; +constant congr_cl9_wB_offset :natural := congr_cl9_wA_offset + 6; +constant congr_cl9_wC_offset :natural := congr_cl9_wB_offset + 6; +constant congr_cl9_wD_offset :natural := congr_cl9_wC_offset + 6; +constant congr_cl9_wE_offset :natural := congr_cl9_wD_offset + 6; +constant congr_cl9_wF_offset :natural := congr_cl9_wE_offset + 6; +constant congr_cl9_wG_offset :natural := congr_cl9_wF_offset + 6; +constant congr_cl9_wH_offset :natural := congr_cl9_wG_offset + 6; +constant congr_cl10_wA_offset :natural := congr_cl9_wH_offset + 6; +constant congr_cl10_wB_offset :natural := congr_cl10_wA_offset + 6; +constant congr_cl10_wC_offset :natural := congr_cl10_wB_offset + 6; +constant congr_cl10_wD_offset :natural := congr_cl10_wC_offset + 6; +constant congr_cl10_wE_offset :natural := congr_cl10_wD_offset + 6; +constant congr_cl10_wF_offset :natural := congr_cl10_wE_offset + 6; +constant congr_cl10_wG_offset :natural := congr_cl10_wF_offset + 6; +constant congr_cl10_wH_offset :natural := congr_cl10_wG_offset + 6; +constant congr_cl11_wA_offset :natural := congr_cl10_wH_offset + 6; +constant congr_cl11_wB_offset :natural := congr_cl11_wA_offset + 6; +constant congr_cl11_wC_offset :natural := congr_cl11_wB_offset + 6; +constant congr_cl11_wD_offset :natural := congr_cl11_wC_offset + 6; +constant congr_cl11_wE_offset :natural := congr_cl11_wD_offset + 6; +constant congr_cl11_wF_offset :natural := congr_cl11_wE_offset + 6; +constant congr_cl11_wG_offset :natural := congr_cl11_wF_offset + 6; +constant congr_cl11_wH_offset :natural := congr_cl11_wG_offset + 6; +constant congr_cl12_wA_offset :natural := congr_cl11_wH_offset + 6; +constant congr_cl12_wB_offset :natural := congr_cl12_wA_offset + 6; +constant congr_cl12_wC_offset :natural := congr_cl12_wB_offset + 6; +constant congr_cl12_wD_offset :natural := congr_cl12_wC_offset + 6; +constant congr_cl12_wE_offset :natural := congr_cl12_wD_offset + 6; +constant congr_cl12_wF_offset :natural := congr_cl12_wE_offset + 6; +constant congr_cl12_wG_offset :natural := congr_cl12_wF_offset + 6; +constant congr_cl12_wH_offset :natural := congr_cl12_wG_offset + 6; +constant congr_cl13_wA_offset :natural := congr_cl12_wH_offset + 6; +constant congr_cl13_wB_offset :natural := congr_cl13_wA_offset + 6; +constant congr_cl13_wC_offset :natural := congr_cl13_wB_offset + 6; +constant congr_cl13_wD_offset :natural := congr_cl13_wC_offset + 6; +constant congr_cl13_wE_offset :natural := congr_cl13_wD_offset + 6; +constant congr_cl13_wF_offset :natural := congr_cl13_wE_offset + 6; +constant congr_cl13_wG_offset :natural := congr_cl13_wF_offset + 6; +constant congr_cl13_wH_offset :natural := congr_cl13_wG_offset + 6; +constant congr_cl14_wA_offset :natural := congr_cl13_wH_offset + 6; +constant congr_cl14_wB_offset :natural := congr_cl14_wA_offset + 6; +constant congr_cl14_wC_offset :natural := congr_cl14_wB_offset + 6; +constant congr_cl14_wD_offset :natural := congr_cl14_wC_offset + 6; +constant congr_cl14_wE_offset :natural := congr_cl14_wD_offset + 6; +constant congr_cl14_wF_offset :natural := congr_cl14_wE_offset + 6; +constant congr_cl14_wG_offset :natural := congr_cl14_wF_offset + 6; +constant congr_cl14_wH_offset :natural := congr_cl14_wG_offset + 6; +constant congr_cl15_wA_offset :natural := congr_cl14_wH_offset + 6; +constant congr_cl15_wB_offset :natural := congr_cl15_wA_offset + 6; +constant congr_cl15_wC_offset :natural := congr_cl15_wB_offset + 6; +constant congr_cl15_wD_offset :natural := congr_cl15_wC_offset + 6; +constant congr_cl15_wE_offset :natural := congr_cl15_wD_offset + 6; +constant congr_cl15_wF_offset :natural := congr_cl15_wE_offset + 6; +constant congr_cl15_wG_offset :natural := congr_cl15_wF_offset + 6; +constant congr_cl15_wH_offset :natural := congr_cl15_wG_offset + 6; +constant congr_cl16_wA_offset :natural := congr_cl15_wH_offset + 6; +constant congr_cl16_wB_offset :natural := congr_cl16_wA_offset + 6; +constant congr_cl16_wC_offset :natural := congr_cl16_wB_offset + 6; +constant congr_cl16_wD_offset :natural := congr_cl16_wC_offset + 6; +constant congr_cl16_wE_offset :natural := congr_cl16_wD_offset + 6; +constant congr_cl16_wF_offset :natural := congr_cl16_wE_offset + 6; +constant congr_cl16_wG_offset :natural := congr_cl16_wF_offset + 6; +constant congr_cl16_wH_offset :natural := congr_cl16_wG_offset + 6; +constant congr_cl17_wA_offset :natural := congr_cl16_wH_offset + 6; +constant congr_cl17_wB_offset :natural := congr_cl17_wA_offset + 6; +constant congr_cl17_wC_offset :natural := congr_cl17_wB_offset + 6; +constant congr_cl17_wD_offset :natural := congr_cl17_wC_offset + 6; +constant congr_cl17_wE_offset :natural := congr_cl17_wD_offset + 6; +constant congr_cl17_wF_offset :natural := congr_cl17_wE_offset + 6; +constant congr_cl17_wG_offset :natural := congr_cl17_wF_offset + 6; +constant congr_cl17_wH_offset :natural := congr_cl17_wG_offset + 6; +constant congr_cl18_wA_offset :natural := congr_cl17_wH_offset + 6; +constant congr_cl18_wB_offset :natural := congr_cl18_wA_offset + 6; +constant congr_cl18_wC_offset :natural := congr_cl18_wB_offset + 6; +constant congr_cl18_wD_offset :natural := congr_cl18_wC_offset + 6; +constant congr_cl18_wE_offset :natural := congr_cl18_wD_offset + 6; +constant congr_cl18_wF_offset :natural := congr_cl18_wE_offset + 6; +constant congr_cl18_wG_offset :natural := congr_cl18_wF_offset + 6; +constant congr_cl18_wH_offset :natural := congr_cl18_wG_offset + 6; +constant congr_cl19_wA_offset :natural := congr_cl18_wH_offset + 6; +constant congr_cl19_wB_offset :natural := congr_cl19_wA_offset + 6; +constant congr_cl19_wC_offset :natural := congr_cl19_wB_offset + 6; +constant congr_cl19_wD_offset :natural := congr_cl19_wC_offset + 6; +constant congr_cl19_wE_offset :natural := congr_cl19_wD_offset + 6; +constant congr_cl19_wF_offset :natural := congr_cl19_wE_offset + 6; +constant congr_cl19_wG_offset :natural := congr_cl19_wF_offset + 6; +constant congr_cl19_wH_offset :natural := congr_cl19_wG_offset + 6; +constant congr_cl20_wA_offset :natural := congr_cl19_wH_offset + 6; +constant congr_cl20_wB_offset :natural := congr_cl20_wA_offset + 6; +constant congr_cl20_wC_offset :natural := congr_cl20_wB_offset + 6; +constant congr_cl20_wD_offset :natural := congr_cl20_wC_offset + 6; +constant congr_cl20_wE_offset :natural := congr_cl20_wD_offset + 6; +constant congr_cl20_wF_offset :natural := congr_cl20_wE_offset + 6; +constant congr_cl20_wG_offset :natural := congr_cl20_wF_offset + 6; +constant congr_cl20_wH_offset :natural := congr_cl20_wG_offset + 6; +constant congr_cl21_wA_offset :natural := congr_cl20_wH_offset + 6; +constant congr_cl21_wB_offset :natural := congr_cl21_wA_offset + 6; +constant congr_cl21_wC_offset :natural := congr_cl21_wB_offset + 6; +constant congr_cl21_wD_offset :natural := congr_cl21_wC_offset + 6; +constant congr_cl21_wE_offset :natural := congr_cl21_wD_offset + 6; +constant congr_cl21_wF_offset :natural := congr_cl21_wE_offset + 6; +constant congr_cl21_wG_offset :natural := congr_cl21_wF_offset + 6; +constant congr_cl21_wH_offset :natural := congr_cl21_wG_offset + 6; +constant congr_cl22_wA_offset :natural := congr_cl21_wH_offset + 6; +constant congr_cl22_wB_offset :natural := congr_cl22_wA_offset + 6; +constant congr_cl22_wC_offset :natural := congr_cl22_wB_offset + 6; +constant congr_cl22_wD_offset :natural := congr_cl22_wC_offset + 6; +constant congr_cl22_wE_offset :natural := congr_cl22_wD_offset + 6; +constant congr_cl22_wF_offset :natural := congr_cl22_wE_offset + 6; +constant congr_cl22_wG_offset :natural := congr_cl22_wF_offset + 6; +constant congr_cl22_wH_offset :natural := congr_cl22_wG_offset + 6; +constant congr_cl23_wA_offset :natural := congr_cl22_wH_offset + 6; +constant congr_cl23_wB_offset :natural := congr_cl23_wA_offset + 6; +constant congr_cl23_wC_offset :natural := congr_cl23_wB_offset + 6; +constant congr_cl23_wD_offset :natural := congr_cl23_wC_offset + 6; +constant congr_cl23_wE_offset :natural := congr_cl23_wD_offset + 6; +constant congr_cl23_wF_offset :natural := congr_cl23_wE_offset + 6; +constant congr_cl23_wG_offset :natural := congr_cl23_wF_offset + 6; +constant congr_cl23_wH_offset :natural := congr_cl23_wG_offset + 6; +constant congr_cl24_wA_offset :natural := congr_cl23_wH_offset + 6; +constant congr_cl24_wB_offset :natural := congr_cl24_wA_offset + 6; +constant congr_cl24_wC_offset :natural := congr_cl24_wB_offset + 6; +constant congr_cl24_wD_offset :natural := congr_cl24_wC_offset + 6; +constant congr_cl24_wE_offset :natural := congr_cl24_wD_offset + 6; +constant congr_cl24_wF_offset :natural := congr_cl24_wE_offset + 6; +constant congr_cl24_wG_offset :natural := congr_cl24_wF_offset + 6; +constant congr_cl24_wH_offset :natural := congr_cl24_wG_offset + 6; +constant congr_cl25_wA_offset :natural := congr_cl24_wH_offset + 6; +constant congr_cl25_wB_offset :natural := congr_cl25_wA_offset + 6; +constant congr_cl25_wC_offset :natural := congr_cl25_wB_offset + 6; +constant congr_cl25_wD_offset :natural := congr_cl25_wC_offset + 6; +constant congr_cl25_wE_offset :natural := congr_cl25_wD_offset + 6; +constant congr_cl25_wF_offset :natural := congr_cl25_wE_offset + 6; +constant congr_cl25_wG_offset :natural := congr_cl25_wF_offset + 6; +constant congr_cl25_wH_offset :natural := congr_cl25_wG_offset + 6; +constant congr_cl26_wA_offset :natural := congr_cl25_wH_offset + 6; +constant congr_cl26_wB_offset :natural := congr_cl26_wA_offset + 6; +constant congr_cl26_wC_offset :natural := congr_cl26_wB_offset + 6; +constant congr_cl26_wD_offset :natural := congr_cl26_wC_offset + 6; +constant congr_cl26_wE_offset :natural := congr_cl26_wD_offset + 6; +constant congr_cl26_wF_offset :natural := congr_cl26_wE_offset + 6; +constant congr_cl26_wG_offset :natural := congr_cl26_wF_offset + 6; +constant congr_cl26_wH_offset :natural := congr_cl26_wG_offset + 6; +constant congr_cl27_wA_offset :natural := congr_cl26_wH_offset + 6; +constant congr_cl27_wB_offset :natural := congr_cl27_wA_offset + 6; +constant congr_cl27_wC_offset :natural := congr_cl27_wB_offset + 6; +constant congr_cl27_wD_offset :natural := congr_cl27_wC_offset + 6; +constant congr_cl27_wE_offset :natural := congr_cl27_wD_offset + 6; +constant congr_cl27_wF_offset :natural := congr_cl27_wE_offset + 6; +constant congr_cl27_wG_offset :natural := congr_cl27_wF_offset + 6; +constant congr_cl27_wH_offset :natural := congr_cl27_wG_offset + 6; +constant congr_cl28_wA_offset :natural := congr_cl27_wH_offset + 6; +constant congr_cl28_wB_offset :natural := congr_cl28_wA_offset + 6; +constant congr_cl28_wC_offset :natural := congr_cl28_wB_offset + 6; +constant congr_cl28_wD_offset :natural := congr_cl28_wC_offset + 6; +constant congr_cl28_wE_offset :natural := congr_cl28_wD_offset + 6; +constant congr_cl28_wF_offset :natural := congr_cl28_wE_offset + 6; +constant congr_cl28_wG_offset :natural := congr_cl28_wF_offset + 6; +constant congr_cl28_wH_offset :natural := congr_cl28_wG_offset + 6; +constant congr_cl29_wA_offset :natural := congr_cl28_wH_offset + 6; +constant congr_cl29_wB_offset :natural := congr_cl29_wA_offset + 6; +constant congr_cl29_wC_offset :natural := congr_cl29_wB_offset + 6; +constant congr_cl29_wD_offset :natural := congr_cl29_wC_offset + 6; +constant congr_cl29_wE_offset :natural := congr_cl29_wD_offset + 6; +constant congr_cl29_wF_offset :natural := congr_cl29_wE_offset + 6; +constant congr_cl29_wG_offset :natural := congr_cl29_wF_offset + 6; +constant congr_cl29_wH_offset :natural := congr_cl29_wG_offset + 6; +constant congr_cl30_wA_offset :natural := congr_cl29_wH_offset + 6; +constant congr_cl30_wB_offset :natural := congr_cl30_wA_offset + 6; +constant congr_cl30_wC_offset :natural := congr_cl30_wB_offset + 6; +constant congr_cl30_wD_offset :natural := congr_cl30_wC_offset + 6; +constant congr_cl30_wE_offset :natural := congr_cl30_wD_offset + 6; +constant congr_cl30_wF_offset :natural := congr_cl30_wE_offset + 6; +constant congr_cl30_wG_offset :natural := congr_cl30_wF_offset + 6; +constant congr_cl30_wH_offset :natural := congr_cl30_wG_offset + 6; +constant congr_cl31_wA_offset :natural := congr_cl30_wH_offset + 6; +constant congr_cl31_wB_offset :natural := congr_cl31_wA_offset + 6; +constant congr_cl31_wC_offset :natural := congr_cl31_wB_offset + 6; +constant congr_cl31_wD_offset :natural := congr_cl31_wC_offset + 6; +constant congr_cl31_wE_offset :natural := congr_cl31_wD_offset + 6; +constant congr_cl31_wF_offset :natural := congr_cl31_wE_offset + 6; +constant congr_cl31_wG_offset :natural := congr_cl31_wF_offset + 6; +constant congr_cl31_wH_offset :natural := congr_cl31_wG_offset + 6; +constant congr_cl32_wA_offset :natural := congr_cl31_wH_offset + 6; +constant congr_cl32_wB_offset :natural := congr_cl32_wA_offset + 6; +constant congr_cl32_wC_offset :natural := congr_cl32_wB_offset + 6; +constant congr_cl32_wD_offset :natural := congr_cl32_wC_offset + 6; +constant congr_cl32_wE_offset :natural := congr_cl32_wD_offset + 6; +constant congr_cl32_wF_offset :natural := congr_cl32_wE_offset + 6; +constant congr_cl32_wG_offset :natural := congr_cl32_wF_offset + 6; +constant congr_cl32_wH_offset :natural := congr_cl32_wG_offset + 6; +constant congr_cl33_wA_offset :natural := congr_cl32_wH_offset + 6; +constant congr_cl33_wB_offset :natural := congr_cl33_wA_offset + 6; +constant congr_cl33_wC_offset :natural := congr_cl33_wB_offset + 6; +constant congr_cl33_wD_offset :natural := congr_cl33_wC_offset + 6; +constant congr_cl33_wE_offset :natural := congr_cl33_wD_offset + 6; +constant congr_cl33_wF_offset :natural := congr_cl33_wE_offset + 6; +constant congr_cl33_wG_offset :natural := congr_cl33_wF_offset + 6; +constant congr_cl33_wH_offset :natural := congr_cl33_wG_offset + 6; +constant congr_cl34_wA_offset :natural := congr_cl33_wH_offset + 6; +constant congr_cl34_wB_offset :natural := congr_cl34_wA_offset + 6; +constant congr_cl34_wC_offset :natural := congr_cl34_wB_offset + 6; +constant congr_cl34_wD_offset :natural := congr_cl34_wC_offset + 6; +constant congr_cl34_wE_offset :natural := congr_cl34_wD_offset + 6; +constant congr_cl34_wF_offset :natural := congr_cl34_wE_offset + 6; +constant congr_cl34_wG_offset :natural := congr_cl34_wF_offset + 6; +constant congr_cl34_wH_offset :natural := congr_cl34_wG_offset + 6; +constant congr_cl35_wA_offset :natural := congr_cl34_wH_offset + 6; +constant congr_cl35_wB_offset :natural := congr_cl35_wA_offset + 6; +constant congr_cl35_wC_offset :natural := congr_cl35_wB_offset + 6; +constant congr_cl35_wD_offset :natural := congr_cl35_wC_offset + 6; +constant congr_cl35_wE_offset :natural := congr_cl35_wD_offset + 6; +constant congr_cl35_wF_offset :natural := congr_cl35_wE_offset + 6; +constant congr_cl35_wG_offset :natural := congr_cl35_wF_offset + 6; +constant congr_cl35_wH_offset :natural := congr_cl35_wG_offset + 6; +constant congr_cl36_wA_offset :natural := congr_cl35_wH_offset + 6; +constant congr_cl36_wB_offset :natural := congr_cl36_wA_offset + 6; +constant congr_cl36_wC_offset :natural := congr_cl36_wB_offset + 6; +constant congr_cl36_wD_offset :natural := congr_cl36_wC_offset + 6; +constant congr_cl36_wE_offset :natural := congr_cl36_wD_offset + 6; +constant congr_cl36_wF_offset :natural := congr_cl36_wE_offset + 6; +constant congr_cl36_wG_offset :natural := congr_cl36_wF_offset + 6; +constant congr_cl36_wH_offset :natural := congr_cl36_wG_offset + 6; +constant congr_cl37_wA_offset :natural := congr_cl36_wH_offset + 6; +constant congr_cl37_wB_offset :natural := congr_cl37_wA_offset + 6; +constant congr_cl37_wC_offset :natural := congr_cl37_wB_offset + 6; +constant congr_cl37_wD_offset :natural := congr_cl37_wC_offset + 6; +constant congr_cl37_wE_offset :natural := congr_cl37_wD_offset + 6; +constant congr_cl37_wF_offset :natural := congr_cl37_wE_offset + 6; +constant congr_cl37_wG_offset :natural := congr_cl37_wF_offset + 6; +constant congr_cl37_wH_offset :natural := congr_cl37_wG_offset + 6; +constant congr_cl38_wA_offset :natural := congr_cl37_wH_offset + 6; +constant congr_cl38_wB_offset :natural := congr_cl38_wA_offset + 6; +constant congr_cl38_wC_offset :natural := congr_cl38_wB_offset + 6; +constant congr_cl38_wD_offset :natural := congr_cl38_wC_offset + 6; +constant congr_cl38_wE_offset :natural := congr_cl38_wD_offset + 6; +constant congr_cl38_wF_offset :natural := congr_cl38_wE_offset + 6; +constant congr_cl38_wG_offset :natural := congr_cl38_wF_offset + 6; +constant congr_cl38_wH_offset :natural := congr_cl38_wG_offset + 6; +constant congr_cl39_wA_offset :natural := congr_cl38_wH_offset + 6; +constant congr_cl39_wB_offset :natural := congr_cl39_wA_offset + 6; +constant congr_cl39_wC_offset :natural := congr_cl39_wB_offset + 6; +constant congr_cl39_wD_offset :natural := congr_cl39_wC_offset + 6; +constant congr_cl39_wE_offset :natural := congr_cl39_wD_offset + 6; +constant congr_cl39_wF_offset :natural := congr_cl39_wE_offset + 6; +constant congr_cl39_wG_offset :natural := congr_cl39_wF_offset + 6; +constant congr_cl39_wH_offset :natural := congr_cl39_wG_offset + 6; +constant congr_cl40_wA_offset :natural := congr_cl39_wH_offset + 6; +constant congr_cl40_wB_offset :natural := congr_cl40_wA_offset + 6; +constant congr_cl40_wC_offset :natural := congr_cl40_wB_offset + 6; +constant congr_cl40_wD_offset :natural := congr_cl40_wC_offset + 6; +constant congr_cl40_wE_offset :natural := congr_cl40_wD_offset + 6; +constant congr_cl40_wF_offset :natural := congr_cl40_wE_offset + 6; +constant congr_cl40_wG_offset :natural := congr_cl40_wF_offset + 6; +constant congr_cl40_wH_offset :natural := congr_cl40_wG_offset + 6; +constant congr_cl41_wA_offset :natural := congr_cl40_wH_offset + 6; +constant congr_cl41_wB_offset :natural := congr_cl41_wA_offset + 6; +constant congr_cl41_wC_offset :natural := congr_cl41_wB_offset + 6; +constant congr_cl41_wD_offset :natural := congr_cl41_wC_offset + 6; +constant congr_cl41_wE_offset :natural := congr_cl41_wD_offset + 6; +constant congr_cl41_wF_offset :natural := congr_cl41_wE_offset + 6; +constant congr_cl41_wG_offset :natural := congr_cl41_wF_offset + 6; +constant congr_cl41_wH_offset :natural := congr_cl41_wG_offset + 6; +constant congr_cl42_wA_offset :natural := congr_cl41_wH_offset + 6; +constant congr_cl42_wB_offset :natural := congr_cl42_wA_offset + 6; +constant congr_cl42_wC_offset :natural := congr_cl42_wB_offset + 6; +constant congr_cl42_wD_offset :natural := congr_cl42_wC_offset + 6; +constant congr_cl42_wE_offset :natural := congr_cl42_wD_offset + 6; +constant congr_cl42_wF_offset :natural := congr_cl42_wE_offset + 6; +constant congr_cl42_wG_offset :natural := congr_cl42_wF_offset + 6; +constant congr_cl42_wH_offset :natural := congr_cl42_wG_offset + 6; +constant congr_cl43_wA_offset :natural := congr_cl42_wH_offset + 6; +constant congr_cl43_wB_offset :natural := congr_cl43_wA_offset + 6; +constant congr_cl43_wC_offset :natural := congr_cl43_wB_offset + 6; +constant congr_cl43_wD_offset :natural := congr_cl43_wC_offset + 6; +constant congr_cl43_wE_offset :natural := congr_cl43_wD_offset + 6; +constant congr_cl43_wF_offset :natural := congr_cl43_wE_offset + 6; +constant congr_cl43_wG_offset :natural := congr_cl43_wF_offset + 6; +constant congr_cl43_wH_offset :natural := congr_cl43_wG_offset + 6; +constant congr_cl44_wA_offset :natural := congr_cl43_wH_offset + 6; +constant congr_cl44_wB_offset :natural := congr_cl44_wA_offset + 6; +constant congr_cl44_wC_offset :natural := congr_cl44_wB_offset + 6; +constant congr_cl44_wD_offset :natural := congr_cl44_wC_offset + 6; +constant congr_cl44_wE_offset :natural := congr_cl44_wD_offset + 6; +constant congr_cl44_wF_offset :natural := congr_cl44_wE_offset + 6; +constant congr_cl44_wG_offset :natural := congr_cl44_wF_offset + 6; +constant congr_cl44_wH_offset :natural := congr_cl44_wG_offset + 6; +constant congr_cl45_wA_offset :natural := congr_cl44_wH_offset + 6; +constant congr_cl45_wB_offset :natural := congr_cl45_wA_offset + 6; +constant congr_cl45_wC_offset :natural := congr_cl45_wB_offset + 6; +constant congr_cl45_wD_offset :natural := congr_cl45_wC_offset + 6; +constant congr_cl45_wE_offset :natural := congr_cl45_wD_offset + 6; +constant congr_cl45_wF_offset :natural := congr_cl45_wE_offset + 6; +constant congr_cl45_wG_offset :natural := congr_cl45_wF_offset + 6; +constant congr_cl45_wH_offset :natural := congr_cl45_wG_offset + 6; +constant congr_cl46_wA_offset :natural := congr_cl45_wH_offset + 6; +constant congr_cl46_wB_offset :natural := congr_cl46_wA_offset + 6; +constant congr_cl46_wC_offset :natural := congr_cl46_wB_offset + 6; +constant congr_cl46_wD_offset :natural := congr_cl46_wC_offset + 6; +constant congr_cl46_wE_offset :natural := congr_cl46_wD_offset + 6; +constant congr_cl46_wF_offset :natural := congr_cl46_wE_offset + 6; +constant congr_cl46_wG_offset :natural := congr_cl46_wF_offset + 6; +constant congr_cl46_wH_offset :natural := congr_cl46_wG_offset + 6; +constant congr_cl47_wA_offset :natural := congr_cl46_wH_offset + 6; +constant congr_cl47_wB_offset :natural := congr_cl47_wA_offset + 6; +constant congr_cl47_wC_offset :natural := congr_cl47_wB_offset + 6; +constant congr_cl47_wD_offset :natural := congr_cl47_wC_offset + 6; +constant congr_cl47_wE_offset :natural := congr_cl47_wD_offset + 6; +constant congr_cl47_wF_offset :natural := congr_cl47_wE_offset + 6; +constant congr_cl47_wG_offset :natural := congr_cl47_wF_offset + 6; +constant congr_cl47_wH_offset :natural := congr_cl47_wG_offset + 6; +constant congr_cl48_wA_offset :natural := congr_cl47_wH_offset + 6; +constant congr_cl48_wB_offset :natural := congr_cl48_wA_offset + 6; +constant congr_cl48_wC_offset :natural := congr_cl48_wB_offset + 6; +constant congr_cl48_wD_offset :natural := congr_cl48_wC_offset + 6; +constant congr_cl48_wE_offset :natural := congr_cl48_wD_offset + 6; +constant congr_cl48_wF_offset :natural := congr_cl48_wE_offset + 6; +constant congr_cl48_wG_offset :natural := congr_cl48_wF_offset + 6; +constant congr_cl48_wH_offset :natural := congr_cl48_wG_offset + 6; +constant congr_cl49_wA_offset :natural := congr_cl48_wH_offset + 6; +constant congr_cl49_wB_offset :natural := congr_cl49_wA_offset + 6; +constant congr_cl49_wC_offset :natural := congr_cl49_wB_offset + 6; +constant congr_cl49_wD_offset :natural := congr_cl49_wC_offset + 6; +constant congr_cl49_wE_offset :natural := congr_cl49_wD_offset + 6; +constant congr_cl49_wF_offset :natural := congr_cl49_wE_offset + 6; +constant congr_cl49_wG_offset :natural := congr_cl49_wF_offset + 6; +constant congr_cl49_wH_offset :natural := congr_cl49_wG_offset + 6; +constant congr_cl50_wA_offset :natural := congr_cl49_wH_offset + 6; +constant congr_cl50_wB_offset :natural := congr_cl50_wA_offset + 6; +constant congr_cl50_wC_offset :natural := congr_cl50_wB_offset + 6; +constant congr_cl50_wD_offset :natural := congr_cl50_wC_offset + 6; +constant congr_cl50_wE_offset :natural := congr_cl50_wD_offset + 6; +constant congr_cl50_wF_offset :natural := congr_cl50_wE_offset + 6; +constant congr_cl50_wG_offset :natural := congr_cl50_wF_offset + 6; +constant congr_cl50_wH_offset :natural := congr_cl50_wG_offset + 6; +constant congr_cl51_wA_offset :natural := congr_cl50_wH_offset + 6; +constant congr_cl51_wB_offset :natural := congr_cl51_wA_offset + 6; +constant congr_cl51_wC_offset :natural := congr_cl51_wB_offset + 6; +constant congr_cl51_wD_offset :natural := congr_cl51_wC_offset + 6; +constant congr_cl51_wE_offset :natural := congr_cl51_wD_offset + 6; +constant congr_cl51_wF_offset :natural := congr_cl51_wE_offset + 6; +constant congr_cl51_wG_offset :natural := congr_cl51_wF_offset + 6; +constant congr_cl51_wH_offset :natural := congr_cl51_wG_offset + 6; +constant congr_cl52_wA_offset :natural := congr_cl51_wH_offset + 6; +constant congr_cl52_wB_offset :natural := congr_cl52_wA_offset + 6; +constant congr_cl52_wC_offset :natural := congr_cl52_wB_offset + 6; +constant congr_cl52_wD_offset :natural := congr_cl52_wC_offset + 6; +constant congr_cl52_wE_offset :natural := congr_cl52_wD_offset + 6; +constant congr_cl52_wF_offset :natural := congr_cl52_wE_offset + 6; +constant congr_cl52_wG_offset :natural := congr_cl52_wF_offset + 6; +constant congr_cl52_wH_offset :natural := congr_cl52_wG_offset + 6; +constant congr_cl53_wA_offset :natural := congr_cl52_wH_offset + 6; +constant congr_cl53_wB_offset :natural := congr_cl53_wA_offset + 6; +constant congr_cl53_wC_offset :natural := congr_cl53_wB_offset + 6; +constant congr_cl53_wD_offset :natural := congr_cl53_wC_offset + 6; +constant congr_cl53_wE_offset :natural := congr_cl53_wD_offset + 6; +constant congr_cl53_wF_offset :natural := congr_cl53_wE_offset + 6; +constant congr_cl53_wG_offset :natural := congr_cl53_wF_offset + 6; +constant congr_cl53_wH_offset :natural := congr_cl53_wG_offset + 6; +constant congr_cl54_wA_offset :natural := congr_cl53_wH_offset + 6; +constant congr_cl54_wB_offset :natural := congr_cl54_wA_offset + 6; +constant congr_cl54_wC_offset :natural := congr_cl54_wB_offset + 6; +constant congr_cl54_wD_offset :natural := congr_cl54_wC_offset + 6; +constant congr_cl54_wE_offset :natural := congr_cl54_wD_offset + 6; +constant congr_cl54_wF_offset :natural := congr_cl54_wE_offset + 6; +constant congr_cl54_wG_offset :natural := congr_cl54_wF_offset + 6; +constant congr_cl54_wH_offset :natural := congr_cl54_wG_offset + 6; +constant congr_cl55_wA_offset :natural := congr_cl54_wH_offset + 6; +constant congr_cl55_wB_offset :natural := congr_cl55_wA_offset + 6; +constant congr_cl55_wC_offset :natural := congr_cl55_wB_offset + 6; +constant congr_cl55_wD_offset :natural := congr_cl55_wC_offset + 6; +constant congr_cl55_wE_offset :natural := congr_cl55_wD_offset + 6; +constant congr_cl55_wF_offset :natural := congr_cl55_wE_offset + 6; +constant congr_cl55_wG_offset :natural := congr_cl55_wF_offset + 6; +constant congr_cl55_wH_offset :natural := congr_cl55_wG_offset + 6; +constant congr_cl56_wA_offset :natural := congr_cl55_wH_offset + 6; +constant congr_cl56_wB_offset :natural := congr_cl56_wA_offset + 6; +constant congr_cl56_wC_offset :natural := congr_cl56_wB_offset + 6; +constant congr_cl56_wD_offset :natural := congr_cl56_wC_offset + 6; +constant congr_cl56_wE_offset :natural := congr_cl56_wD_offset + 6; +constant congr_cl56_wF_offset :natural := congr_cl56_wE_offset + 6; +constant congr_cl56_wG_offset :natural := congr_cl56_wF_offset + 6; +constant congr_cl56_wH_offset :natural := congr_cl56_wG_offset + 6; +constant congr_cl57_wA_offset :natural := congr_cl56_wH_offset + 6; +constant congr_cl57_wB_offset :natural := congr_cl57_wA_offset + 6; +constant congr_cl57_wC_offset :natural := congr_cl57_wB_offset + 6; +constant congr_cl57_wD_offset :natural := congr_cl57_wC_offset + 6; +constant congr_cl57_wE_offset :natural := congr_cl57_wD_offset + 6; +constant congr_cl57_wF_offset :natural := congr_cl57_wE_offset + 6; +constant congr_cl57_wG_offset :natural := congr_cl57_wF_offset + 6; +constant congr_cl57_wH_offset :natural := congr_cl57_wG_offset + 6; +constant congr_cl58_wA_offset :natural := congr_cl57_wH_offset + 6; +constant congr_cl58_wB_offset :natural := congr_cl58_wA_offset + 6; +constant congr_cl58_wC_offset :natural := congr_cl58_wB_offset + 6; +constant congr_cl58_wD_offset :natural := congr_cl58_wC_offset + 6; +constant congr_cl58_wE_offset :natural := congr_cl58_wD_offset + 6; +constant congr_cl58_wF_offset :natural := congr_cl58_wE_offset + 6; +constant congr_cl58_wG_offset :natural := congr_cl58_wF_offset + 6; +constant congr_cl58_wH_offset :natural := congr_cl58_wG_offset + 6; +constant congr_cl59_wA_offset :natural := congr_cl58_wH_offset + 6; +constant congr_cl59_wB_offset :natural := congr_cl59_wA_offset + 6; +constant congr_cl59_wC_offset :natural := congr_cl59_wB_offset + 6; +constant congr_cl59_wD_offset :natural := congr_cl59_wC_offset + 6; +constant congr_cl59_wE_offset :natural := congr_cl59_wD_offset + 6; +constant congr_cl59_wF_offset :natural := congr_cl59_wE_offset + 6; +constant congr_cl59_wG_offset :natural := congr_cl59_wF_offset + 6; +constant congr_cl59_wH_offset :natural := congr_cl59_wG_offset + 6; +constant congr_cl60_wA_offset :natural := congr_cl59_wH_offset + 6; +constant congr_cl60_wB_offset :natural := congr_cl60_wA_offset + 6; +constant congr_cl60_wC_offset :natural := congr_cl60_wB_offset + 6; +constant congr_cl60_wD_offset :natural := congr_cl60_wC_offset + 6; +constant congr_cl60_wE_offset :natural := congr_cl60_wD_offset + 6; +constant congr_cl60_wF_offset :natural := congr_cl60_wE_offset + 6; +constant congr_cl60_wG_offset :natural := congr_cl60_wF_offset + 6; +constant congr_cl60_wH_offset :natural := congr_cl60_wG_offset + 6; +constant congr_cl61_wA_offset :natural := congr_cl60_wH_offset + 6; +constant congr_cl61_wB_offset :natural := congr_cl61_wA_offset + 6; +constant congr_cl61_wC_offset :natural := congr_cl61_wB_offset + 6; +constant congr_cl61_wD_offset :natural := congr_cl61_wC_offset + 6; +constant congr_cl61_wE_offset :natural := congr_cl61_wD_offset + 6; +constant congr_cl61_wF_offset :natural := congr_cl61_wE_offset + 6; +constant congr_cl61_wG_offset :natural := congr_cl61_wF_offset + 6; +constant congr_cl61_wH_offset :natural := congr_cl61_wG_offset + 6; +constant congr_cl62_wA_offset :natural := congr_cl61_wH_offset + 6; +constant congr_cl62_wB_offset :natural := congr_cl62_wA_offset + 6; +constant congr_cl62_wC_offset :natural := congr_cl62_wB_offset + 6; +constant congr_cl62_wD_offset :natural := congr_cl62_wC_offset + 6; +constant congr_cl62_wE_offset :natural := congr_cl62_wD_offset + 6; +constant congr_cl62_wF_offset :natural := congr_cl62_wE_offset + 6; +constant congr_cl62_wG_offset :natural := congr_cl62_wF_offset + 6; +constant congr_cl62_wH_offset :natural := congr_cl62_wG_offset + 6; +constant congr_cl63_wA_offset :natural := congr_cl62_wH_offset + 6; +constant congr_cl63_wB_offset :natural := congr_cl63_wA_offset + 6; +constant congr_cl63_wC_offset :natural := congr_cl63_wB_offset + 6; +constant congr_cl63_wD_offset :natural := congr_cl63_wC_offset + 6; +constant congr_cl63_wE_offset :natural := congr_cl63_wD_offset + 6; +constant congr_cl63_wF_offset :natural := congr_cl63_wE_offset + 6; +constant congr_cl63_wG_offset :natural := congr_cl63_wF_offset + 6; +constant congr_cl63_wH_offset :natural := congr_cl63_wG_offset + 6; +constant flush_wayA_data_offset :natural := congr_cl63_wH_offset + 6; +constant flush_wayB_data_offset :natural := flush_wayA_data_offset + 6; +constant flush_wayC_data_offset :natural := flush_wayB_data_offset + 6; +constant flush_wayD_data_offset :natural := flush_wayC_data_offset + 6; +constant flush_wayE_data_offset :natural := flush_wayD_data_offset + 6; +constant flush_wayF_data_offset :natural := flush_wayE_data_offset + 6; +constant flush_wayG_data_offset :natural := flush_wayF_data_offset + 6; +constant flush_wayH_data_offset :natural := flush_wayG_data_offset + 6; +constant ex3_flush_cline_offset :natural := flush_wayH_data_offset + 6; +constant ex5_congr_cl_offset :natural := ex3_flush_cline_offset + 1; +constant ex7_congr_cl_offset :natural := ex5_congr_cl_offset + 6; +constant ex8_congr_cl_offset :natural := ex7_congr_cl_offset + 6; +constant ex9_congr_cl_offset :natural := ex8_congr_cl_offset + 6; +constant wayA_val_b_offset :natural := ex9_congr_cl_offset + 6; +constant wayB_val_b_offset :natural := wayA_val_b_offset + 6; +constant wayC_val_b_offset :natural := wayB_val_b_offset + 6; +constant wayD_val_b_offset :natural := wayC_val_b_offset + 6; +constant wayE_val_b_offset :natural := wayD_val_b_offset + 6; +constant wayF_val_b_offset :natural := wayE_val_b_offset + 6; +constant wayG_val_b_offset :natural := wayF_val_b_offset + 6; +constant wayH_val_b_offset :natural := wayG_val_b_offset + 6; +constant ex3_wayA_fxubyp_val_offset :natural := wayH_val_b_offset + 6; +constant ex3_wayB_fxubyp_val_offset :natural := ex3_wayA_fxubyp_val_offset + 1; +constant ex3_wayC_fxubyp_val_offset :natural := ex3_wayB_fxubyp_val_offset + 1; +constant ex3_wayD_fxubyp_val_offset :natural := ex3_wayC_fxubyp_val_offset + 1; +constant ex3_wayE_fxubyp_val_offset :natural := ex3_wayD_fxubyp_val_offset + 1; +constant ex3_wayF_fxubyp_val_offset :natural := ex3_wayE_fxubyp_val_offset + 1; +constant ex3_wayG_fxubyp_val_offset :natural := ex3_wayF_fxubyp_val_offset + 1; +constant ex3_wayH_fxubyp_val_offset :natural := ex3_wayG_fxubyp_val_offset + 1; +constant ex3_wayA_relbyp_val_offset :natural := ex3_wayH_fxubyp_val_offset + 1; +constant ex3_wayB_relbyp_val_offset :natural := ex3_wayA_relbyp_val_offset + 1; +constant ex3_wayC_relbyp_val_offset :natural := ex3_wayB_relbyp_val_offset + 1; +constant ex3_wayD_relbyp_val_offset :natural := ex3_wayC_relbyp_val_offset + 1; +constant ex3_wayE_relbyp_val_offset :natural := ex3_wayD_relbyp_val_offset + 1; +constant ex3_wayF_relbyp_val_offset :natural := ex3_wayE_relbyp_val_offset + 1; +constant ex3_wayG_relbyp_val_offset :natural := ex3_wayF_relbyp_val_offset + 1; +constant ex3_wayH_relbyp_val_offset :natural := ex3_wayG_relbyp_val_offset + 1; +constant ex4_xuop_wayA_upd_offset :natural := ex3_wayH_relbyp_val_offset + 1; +constant ex4_xuop_wayB_upd_offset :natural := ex4_xuop_wayA_upd_offset + 1; +constant ex4_xuop_wayC_upd_offset :natural := ex4_xuop_wayB_upd_offset + 1; +constant ex4_xuop_wayD_upd_offset :natural := ex4_xuop_wayC_upd_offset + 1; +constant ex4_xuop_wayE_upd_offset :natural := ex4_xuop_wayD_upd_offset + 1; +constant ex4_xuop_wayF_upd_offset :natural := ex4_xuop_wayE_upd_offset + 1; +constant ex4_xuop_wayG_upd_offset :natural := ex4_xuop_wayF_upd_offset + 1; +constant ex4_xuop_wayH_upd_offset :natural := ex4_xuop_wayG_upd_offset + 1; +constant ex5_xuop_wayA_upd_offset :natural := ex4_xuop_wayH_upd_offset + 1; +constant ex5_xuop_wayB_upd_offset :natural := ex5_xuop_wayA_upd_offset + 1; +constant ex5_xuop_wayC_upd_offset :natural := ex5_xuop_wayB_upd_offset + 1; +constant ex5_xuop_wayD_upd_offset :natural := ex5_xuop_wayC_upd_offset + 1; +constant ex5_xuop_wayE_upd_offset :natural := ex5_xuop_wayD_upd_offset + 1; +constant ex5_xuop_wayF_upd_offset :natural := ex5_xuop_wayE_upd_offset + 1; +constant ex5_xuop_wayG_upd_offset :natural := ex5_xuop_wayF_upd_offset + 1; +constant ex5_xuop_wayH_upd_offset :natural := ex5_xuop_wayG_upd_offset + 1; +constant inval_clr_lck_wA_offset :natural := ex5_xuop_wayH_upd_offset + 1; +constant inval_clr_lck_wB_offset :natural := inval_clr_lck_wA_offset + 1; +constant inval_clr_lck_wC_offset :natural := inval_clr_lck_wB_offset + 1; +constant inval_clr_lck_wD_offset :natural := inval_clr_lck_wC_offset + 1; +constant inval_clr_lck_wE_offset :natural := inval_clr_lck_wD_offset + 1; +constant inval_clr_lck_wF_offset :natural := inval_clr_lck_wE_offset + 1; +constant inval_clr_lck_wG_offset :natural := inval_clr_lck_wF_offset + 1; +constant inval_clr_lck_wH_offset :natural := inval_clr_lck_wG_offset + 1; +constant congr_cl_m_upd_wayA_offset :natural := inval_clr_lck_wH_offset + 1; +constant congr_cl_m_upd_wayB_offset :natural := congr_cl_m_upd_wayA_offset + 1; +constant congr_cl_m_upd_wayC_offset :natural := congr_cl_m_upd_wayB_offset + 1; +constant congr_cl_m_upd_wayD_offset :natural := congr_cl_m_upd_wayC_offset + 1; +constant congr_cl_m_upd_wayE_offset :natural := congr_cl_m_upd_wayD_offset + 1; +constant congr_cl_m_upd_wayF_offset :natural := congr_cl_m_upd_wayE_offset + 1; +constant congr_cl_m_upd_wayG_offset :natural := congr_cl_m_upd_wayF_offset + 1; +constant congr_cl_m_upd_wayH_offset :natural := congr_cl_m_upd_wayG_offset + 1; +constant ex3_congr_cl_offset :natural := congr_cl_m_upd_wayH_offset + 1; +constant rel24_congr_cl_offset :natural := ex3_congr_cl_offset + 6; +constant relu_s_congr_cl_offset :natural := rel24_congr_cl_offset + 6; +constant reload_way_clr_offset :natural := relu_s_congr_cl_offset + 6; +constant ex4_watchSet_coll_offset :natural := reload_way_clr_offset + 8; +constant rel_wayA_val_b_offset :natural := ex4_watchSet_coll_offset + 1; +constant rel_wayB_val_b_offset :natural := rel_wayA_val_b_offset + 6; +constant rel_wayC_val_b_offset :natural := rel_wayB_val_b_offset + 6; +constant rel_wayD_val_b_offset :natural := rel_wayC_val_b_offset + 6; +constant rel_wayE_val_b_offset :natural := rel_wayD_val_b_offset + 6; +constant rel_wayF_val_b_offset :natural := rel_wayE_val_b_offset + 6; +constant rel_wayG_val_b_offset :natural := rel_wayF_val_b_offset + 6; +constant rel_wayH_val_b_offset :natural := rel_wayG_val_b_offset + 6; +constant rel_val_stg2_offset :natural := rel_wayH_val_b_offset + 6; +constant rel_val_clr_offset :natural := rel_val_stg2_offset + 1; +constant rel_port_upd_offset :natural := rel_val_clr_offset + 1; +constant rel_val_stg4_offset :natural := rel_port_upd_offset + 1; +constant rel_binv_stg4_offset :natural := rel_val_stg4_offset + 1; +constant back_inval_stg3_offset :natural := rel_binv_stg4_offset + 1; +constant back_inval_stg4_offset :natural := back_inval_stg3_offset + 1; +constant back_inval_stg5_offset :natural := back_inval_stg4_offset + 1; +constant binv4_ex4_xuop_upd_offset :natural := back_inval_stg5_offset + 1; +constant binv4_ex4_dir_val_offset :natural := binv4_ex4_xuop_upd_offset + 1; +constant ex4_dir_err_val_offset :natural := binv4_ex4_dir_val_offset + 1; +constant ex5_dir_err_val_offset :natural := ex4_dir_err_val_offset + 1; +constant ex6_dir_err_val_offset :natural := ex5_dir_err_val_offset + 1; +constant derr2_stg_act_offset :natural := ex6_dir_err_val_offset + 1; +constant derr3_stg_act_offset :natural := derr2_stg_act_offset + 1; +constant derr4_stg_act_offset :natural := derr3_stg_act_offset + 1; +constant derr5_stg_act_offset :natural := derr4_stg_act_offset + 1; +constant ex4_dir_multihit_val_b_offset :natural := derr5_stg_act_offset + 1; +constant ex4_n_lsu_ddmh_flush_b_offset :natural := ex4_dir_multihit_val_b_offset + 1; +constant dcarr_up_way_addr_offset :natural := ex4_n_lsu_ddmh_flush_b_offset + 4; +constant reload_wayA_data_offset :natural := dcarr_up_way_addr_offset + 3; +constant reload_wayB_data_offset :natural := reload_wayA_data_offset + 6; +constant reload_wayC_data_offset :natural := reload_wayB_data_offset + 6; +constant reload_wayD_data_offset :natural := reload_wayC_data_offset + 6; +constant reload_wayE_data_offset :natural := reload_wayD_data_offset + 6; +constant reload_wayF_data_offset :natural := reload_wayE_data_offset + 6; +constant reload_wayG_data_offset :natural := reload_wayF_data_offset + 6; +constant reload_wayH_data_offset :natural := reload_wayG_data_offset + 6; +constant binv_wayA_upd_offset :natural := reload_wayH_data_offset + 6; +constant binv_wayB_upd_offset :natural := binv_wayA_upd_offset + 1; +constant binv_wayC_upd_offset :natural := binv_wayB_upd_offset + 1; +constant binv_wayD_upd_offset :natural := binv_wayC_upd_offset + 1; +constant binv_wayE_upd_offset :natural := binv_wayD_upd_offset + 1; +constant binv_wayF_upd_offset :natural := binv_wayE_upd_offset + 1; +constant binv_wayG_upd_offset :natural := binv_wayF_upd_offset + 1; +constant binv_wayH_upd_offset :natural := binv_wayG_upd_offset + 1; +constant binv_wayA_upd2_offset :natural := binv_wayH_upd_offset + 1; +constant binv_wayB_upd2_offset :natural := binv_wayA_upd2_offset + 1; +constant binv_wayC_upd2_offset :natural := binv_wayB_upd2_offset + 1; +constant binv_wayD_upd2_offset :natural := binv_wayC_upd2_offset + 1; +constant binv_wayE_upd2_offset :natural := binv_wayD_upd2_offset + 1; +constant binv_wayF_upd2_offset :natural := binv_wayE_upd2_offset + 1; +constant binv_wayG_upd2_offset :natural := binv_wayF_upd2_offset + 1; +constant binv_wayH_upd2_offset :natural := binv_wayG_upd2_offset + 1; +constant binv_wayA_upd3_offset :natural := binv_wayH_upd2_offset + 1; +constant binv_wayB_upd3_offset :natural := binv_wayA_upd3_offset + 1; +constant binv_wayC_upd3_offset :natural := binv_wayB_upd3_offset + 1; +constant binv_wayD_upd3_offset :natural := binv_wayC_upd3_offset + 1; +constant binv_wayE_upd3_offset :natural := binv_wayD_upd3_offset + 1; +constant binv_wayF_upd3_offset :natural := binv_wayE_upd3_offset + 1; +constant binv_wayG_upd3_offset :natural := binv_wayF_upd3_offset + 1; +constant binv_wayH_upd3_offset :natural := binv_wayG_upd3_offset + 1; +constant reload_wayA_upd_offset :natural := binv_wayH_upd3_offset + 1; +constant reload_wayB_upd_offset :natural := reload_wayA_upd_offset + 1; +constant reload_wayC_upd_offset :natural := reload_wayB_upd_offset + 1; +constant reload_wayD_upd_offset :natural := reload_wayC_upd_offset + 1; +constant reload_wayE_upd_offset :natural := reload_wayD_upd_offset + 1; +constant reload_wayF_upd_offset :natural := reload_wayE_upd_offset + 1; +constant reload_wayG_upd_offset :natural := reload_wayF_upd_offset + 1; +constant reload_wayH_upd_offset :natural := reload_wayG_upd_offset + 1; +constant reload_wayA_upd2_offset :natural := reload_wayH_upd_offset + 1; +constant reload_wayB_upd2_offset :natural := reload_wayA_upd2_offset + 1; +constant reload_wayC_upd2_offset :natural := reload_wayB_upd2_offset + 1; +constant reload_wayD_upd2_offset :natural := reload_wayC_upd2_offset + 1; +constant reload_wayE_upd2_offset :natural := reload_wayD_upd2_offset + 1; +constant reload_wayF_upd2_offset :natural := reload_wayE_upd2_offset + 1; +constant reload_wayG_upd2_offset :natural := reload_wayF_upd2_offset + 1; +constant reload_wayH_upd2_offset :natural := reload_wayG_upd2_offset + 1; +constant reload_wayA_upd3_offset :natural := reload_wayH_upd2_offset + 1; +constant reload_wayB_upd3_offset :natural := reload_wayA_upd3_offset + 1; +constant reload_wayC_upd3_offset :natural := reload_wayB_upd3_offset + 1; +constant reload_wayD_upd3_offset :natural := reload_wayC_upd3_offset + 1; +constant reload_wayE_upd3_offset :natural := reload_wayD_upd3_offset + 1; +constant reload_wayF_upd3_offset :natural := reload_wayE_upd3_offset + 1; +constant reload_wayG_upd3_offset :natural := reload_wayF_upd3_offset + 1; +constant reload_wayH_upd3_offset :natural := reload_wayG_upd3_offset + 1; +constant ex3_store_instr_offset :natural := reload_wayH_upd3_offset + 1; +constant ex3_lock_set_offset :natural := ex3_store_instr_offset + 1; +constant ex4_lock_set_offset :natural := ex3_lock_set_offset + 1; +constant ex5_lock_set_offset :natural := ex4_lock_set_offset + 1; +constant ex3_lock_clr_offset :natural := ex5_lock_set_offset + 1; +constant ex3_xuop_val_offset :natural := ex3_lock_clr_offset + 1; +constant ex4_xuop_val_offset :natural := ex3_xuop_val_offset + 1; +constant ex5_xuop_val_offset :natural := ex4_xuop_val_offset + 1; +constant rel_lock_set_offset :natural := ex5_xuop_val_offset + 1; +constant dcpar_err_stg1_offset :natural := rel_lock_set_offset + 1; +constant dcpar_err_stg2_offset :natural := dcpar_err_stg1_offset + 1; +constant dcpar_err_way_offset :natural := dcpar_err_stg2_offset + 1; +constant dcpar_err_way_inval_offset :natural := dcpar_err_way_offset + 8; +constant dcpar_err_cntr_offset :natural := dcpar_err_way_inval_offset + 8; +constant dcpar_err_ind_sel_offset :natural := dcpar_err_cntr_offset + 2; +constant dcpar_err_push_queue_offset :natural := dcpar_err_ind_sel_offset + 2; +constant ex5_way_hit_offset :natural := dcpar_err_push_queue_offset + 1; +constant ex7_way_hit_offset :natural := ex5_way_hit_offset + 8; +constant ex8_way_hit_offset :natural := ex7_way_hit_offset + 8; +constant ex9_way_hit_offset :natural := ex8_way_hit_offset + 8; +constant ex4_lose_watch_offset :natural := ex9_way_hit_offset + 8; +constant xucr0_cslc_xuop_offset :natural := ex4_lose_watch_offset + 4; +constant xucr0_cslc_binv_offset :natural := xucr0_cslc_xuop_offset + 1; +constant dci_compl_offset :natural := xucr0_cslc_binv_offset + 1; +constant dci_inval_all_offset :natural := dci_compl_offset + 1; +constant inv2_val_offset :natural := dci_inval_all_offset + 1; +constant perf_lsu_evnts_offset :natural := inv2_val_offset + 1; +constant lock_flash_clear_offset :natural := perf_lsu_evnts_offset + 5; +constant lock_flash_clear_val_offset :natural := lock_flash_clear_offset + 1; +constant rel_port_wren_offset :natural := lock_flash_clear_val_offset + 1; +constant ex3_thrd_id_offset :natural := rel_port_wren_offset + 1; +constant ex5_thrd_id_offset :natural := ex3_thrd_id_offset + 4; +constant ex3_l_fld_b1_offset :natural := ex5_thrd_id_offset + 4; +constant ex3_watch_set_offset :natural := ex3_l_fld_b1_offset + 1; +constant ex4_watch_set_offset :natural := ex3_watch_set_offset + 1; +constant ex5_watch_set_offset :natural := ex4_watch_set_offset + 1; +constant ex3_watch_clr_offset :natural := ex5_watch_set_offset + 1; +constant ex3_watch_clr_all_offset :natural := ex3_watch_clr_offset + 1; +constant ex3_watch_chk_offset :natural := ex3_watch_clr_all_offset + 1; +constant ex4_watch_chk_offset :natural := ex3_watch_chk_offset + 1; +constant ex5_watch_chk_offset :natural := ex4_watch_chk_offset + 1; +constant ex3_wclr_all_upd_offset :natural := ex5_watch_chk_offset + 1; +constant ex4_wclr_all_val_offset :natural := ex3_wclr_all_upd_offset + 1; +constant ex5_wclr_all_val_offset :natural := ex4_wclr_all_val_offset + 1; +constant ex6_wclr_all_val_offset :natural := ex5_wclr_all_val_offset + 1; +constant rel_thrd_id_offset :natural := ex6_wclr_all_val_offset + 1; +constant rel_watch_set_offset :natural := rel_thrd_id_offset + 4; +constant ex5_cr_watch_offset :natural := rel_watch_set_offset + 1; +constant ex4_watch_clr_all_offset :natural := ex5_cr_watch_offset + 1; +constant ex5_watch_clr_all_offset :natural := ex4_watch_clr_all_offset + 4; +constant ex6_watch_clr_all_offset :natural := ex5_watch_clr_all_offset + 4; +constant ex5_watch_clr_all_val_offset :natural := ex6_watch_clr_all_offset + 4; +constant ex5_lost_watch_upd_offset :natural := ex5_watch_clr_all_val_offset + 1; +constant ex4_watchlost_set_offset :natural := ex5_lost_watch_upd_offset + 4; +constant ex5_watchlost_set_offset :natural := ex4_watchlost_set_offset + 4; +constant rel_lost_watch_binv_offset :natural := ex5_watchlost_set_offset + 4; +constant lost_watch_evict_ovl_offset :natural := rel_lost_watch_binv_offset + 4; +constant rel_lost_watch_upd_offset :natural := lost_watch_evict_ovl_offset + 4; +constant lost_watch_evict_val_offset :natural := rel_lost_watch_upd_offset + 4; +constant lost_watch_inter_thrd_offset :natural := lost_watch_evict_val_offset + 4; +constant stm_watchlost_state_offset :natural := lost_watch_inter_thrd_offset + 4; +constant ex5_xuop_p0_upd_offset :natural := stm_watchlost_state_offset + 4; +constant rel_val_stgu_offset :natural := ex5_xuop_p0_upd_offset + 1; +constant p0_wren_offset :natural := rel_val_stgu_offset + 1; +constant p0_wren_cpy_offset :natural := p0_wren_offset + 1; +constant p0_wren_stg_offset :natural := p0_wren_cpy_offset + 1; +constant p1_wren_offset :natural := p0_wren_stg_offset + 1; +constant p1_wren_cpy_offset :natural := p1_wren_offset + 1; +constant ex3_thrd_m_offset :natural := p1_wren_cpy_offset + 1; +constant ex4_thrd_m_offset :natural := ex3_thrd_m_offset + 1; +constant ex5_thrd_m_offset :natural := ex4_thrd_m_offset + 1; +constant ex6_thrd_m_offset :natural := ex5_thrd_m_offset + 1; +constant ex7_ld_par_err_offset :natural := ex6_thrd_m_offset + 1; +constant ex8_ld_par_err_offset :natural := ex7_ld_par_err_offset + 1; +constant ex9_ld_par_err_offset :natural := ex8_ld_par_err_offset + 1; +constant ex6_ld_valid_offset :natural := ex9_ld_par_err_offset + 1; +constant ex7_ld_valid_offset :natural := ex6_ld_valid_offset + 1; +constant ex8_ld_valid_offset :natural := ex7_ld_valid_offset + 1; +constant ex9_ld_valid_offset :natural := ex8_ld_valid_offset + 1; +constant rel_in_progress_offset :natural := ex9_ld_valid_offset + 1; +constant inj_dir_multihit_offset :natural := rel_in_progress_offset + 1; +constant congr_cl_ex2_ex3_cmp_offset :natural := inj_dir_multihit_offset + 1; +constant congr_cl_ex2_ex4_cmp_offset :natural := congr_cl_ex2_ex3_cmp_offset + 1; +constant congr_cl_ex2_ex5_cmp_offset :natural := congr_cl_ex2_ex4_cmp_offset + 1; +constant congr_cl_ex2_ex6_cmp_offset :natural := congr_cl_ex2_ex5_cmp_offset + 1; +constant congr_cl_ex3_ex4_cmp_offset :natural := congr_cl_ex2_ex6_cmp_offset + 1; +constant congr_cl_ex3_ex5_cmp_offset :natural := congr_cl_ex3_ex4_cmp_offset + 1; +constant congr_cl_ex3_ex6_cmp_offset :natural := congr_cl_ex3_ex5_cmp_offset + 1; +constant congr_cl_ex4_ex5_cmp_offset :natural := congr_cl_ex3_ex6_cmp_offset + 1; +constant congr_cl_ex4_ex6_cmp_offset :natural := congr_cl_ex4_ex5_cmp_offset + 1; +constant congr_cl_ex4_ex7_cmp_offset :natural := congr_cl_ex4_ex6_cmp_offset + 1; +constant congr_cl_ex2_relu_cmp_offset :natural := congr_cl_ex4_ex7_cmp_offset + 1; +constant congr_cl_ex2_relu_s_cmp_offset :natural := congr_cl_ex2_relu_cmp_offset + 1; +constant congr_cl_ex2_rel_upd_cmp_offset :natural := congr_cl_ex2_relu_s_cmp_offset + 1; +constant congr_cl_rel13_ex3_cmp_offset :natural := congr_cl_ex2_rel_upd_cmp_offset + 1; +constant congr_cl_rel13_ex4_cmp_offset :natural := congr_cl_rel13_ex3_cmp_offset + 1; +constant congr_cl_rel13_ex5_cmp_offset :natural := congr_cl_rel13_ex4_cmp_offset + 1; +constant congr_cl_rel13_ex6_cmp_offset :natural := congr_cl_rel13_ex5_cmp_offset + 1; +constant congr_cl_rel13_relu_cmp_offset :natural := congr_cl_rel13_ex6_cmp_offset + 1; +constant congr_cl_rel13_relu_s_cmp_offset :natural := congr_cl_rel13_relu_cmp_offset + 1; +constant congr_cl_rel13_rel_upd_cmp_offset :natural := congr_cl_rel13_relu_s_cmp_offset + 1; +constant rel24_congr_cl_ex4_cmp_offset :natural := congr_cl_rel13_rel_upd_cmp_offset + 1; +constant rel24_congr_cl_ex5_cmp_offset :natural := rel24_congr_cl_ex4_cmp_offset + 1; +constant rel24_congr_cl_ex6_cmp_offset :natural := rel24_congr_cl_ex5_cmp_offset + 1; +constant relu_congr_cl_ex5_cmp_offset :natural := rel24_congr_cl_ex6_cmp_offset + 1; +constant relu_congr_cl_ex6_cmp_offset :natural := relu_congr_cl_ex5_cmp_offset + 1; +constant relu_congr_cl_ex7_cmp_offset :natural := relu_congr_cl_ex6_cmp_offset + 1; +constant ex4_err_det_way_offset :natural := relu_congr_cl_ex7_cmp_offset + 1; +constant ex4_perr_lck_lost_offset :natural := ex4_err_det_way_offset + 8; +constant ex4_perr_watch_lost_offset :natural := ex4_perr_lck_lost_offset + 1; +constant dcperr_lock_lost_offset :natural := ex4_perr_watch_lost_offset + 4; +constant binv7_ex7_way_upd_offset :natural := dcperr_lock_lost_offset + 1; +constant binv5_ex5_dir_data_offset :natural := binv7_ex7_way_upd_offset + 8; +constant binv7_ex7_dir_data_offset :natural := binv5_ex5_dir_data_offset + 5; +constant binv5_inval_watch_val_offset :natural := binv7_ex7_dir_data_offset + 5; +constant binv5_inval_lock_val_offset :natural := binv5_inval_watch_val_offset + 4; +constant ex4_snd_ld_l2_offset :natural := binv5_inval_lock_val_offset + 1; +constant ex4_ldq_full_flush_b_offset :natural := ex4_snd_ld_l2_offset + 1; +constant ex4_miss_offset :natural := ex4_ldq_full_flush_b_offset + 1; +constant my_spare0_latches_offset :natural := ex4_miss_offset + 1; +constant my_spare1_latches_offset :natural := my_spare0_latches_offset + 17; +constant rel_l1dump_cslc_offset :natural := my_spare1_latches_offset + 16; +constant rel_in_prog_stg1_offset :natural := rel_l1dump_cslc_offset + 1; +constant rel_in_prog_stg2_offset :natural := rel_in_prog_stg1_offset + 1; +constant rel_in_prog_stg3_offset :natural := rel_in_prog_stg2_offset + 1; +constant rel_in_prog_stg4_offset :natural := rel_in_prog_stg3_offset + 1; +constant rel_in_prog_stg5_offset :natural := rel_in_prog_stg4_offset + 1; +constant dcpar_err_stg1_act_offset :natural := rel_in_prog_stg5_offset + 1; +constant dcpar_err_stg2_act_offset :natural := dcpar_err_stg1_act_offset + 1; +constant rel3_perr_stg_act_offset :natural := dcpar_err_stg2_act_offset + 1; +constant rel4_perr_stg_act_offset :natural := rel3_perr_stg_act_offset + 1; +constant scan_right :natural := rel4_perr_stg_act_offset + 1 - 1; +signal p0_congr_cl0_m :std_ulogic; +signal p1_congr_cl0_m :std_ulogic; +signal p0_congr_cl0_act_d :std_ulogic; +signal p0_congr_cl0_act_q :std_ulogic; +signal p1_congr_cl0_act_d :std_ulogic; +signal p1_congr_cl0_act_q :std_ulogic; +signal congr_cl0_act :std_ulogic; +signal congr_cl0_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl0_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu0_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd0_wayA :std_ulogic; +signal p1_way_data_upd0_wayA :std_ulogic; +signal congr_cl0_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl0_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu0_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd0_wayB :std_ulogic; +signal p1_way_data_upd0_wayB :std_ulogic; +signal congr_cl0_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl0_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu0_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd0_wayC :std_ulogic; +signal p1_way_data_upd0_wayC :std_ulogic; +signal congr_cl0_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl0_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu0_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd0_wayD :std_ulogic; +signal p1_way_data_upd0_wayD :std_ulogic; +signal congr_cl0_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl0_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu0_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd0_wayE :std_ulogic; +signal p1_way_data_upd0_wayE :std_ulogic; +signal congr_cl0_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl0_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu0_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd0_wayF :std_ulogic; +signal p1_way_data_upd0_wayF :std_ulogic; +signal congr_cl0_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl0_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu0_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd0_wayG :std_ulogic; +signal p1_way_data_upd0_wayG :std_ulogic; +signal congr_cl0_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl0_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu0_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd0_wayH :std_ulogic; +signal p1_way_data_upd0_wayH :std_ulogic; +signal p0_congr_cl1_m :std_ulogic; +signal p1_congr_cl1_m :std_ulogic; +signal p0_congr_cl1_act_d :std_ulogic; +signal p0_congr_cl1_act_q :std_ulogic; +signal p1_congr_cl1_act_d :std_ulogic; +signal p1_congr_cl1_act_q :std_ulogic; +signal congr_cl1_act :std_ulogic; +signal congr_cl1_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl1_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu1_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd1_wayA :std_ulogic; +signal p1_way_data_upd1_wayA :std_ulogic; +signal congr_cl1_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl1_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu1_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd1_wayB :std_ulogic; +signal p1_way_data_upd1_wayB :std_ulogic; +signal congr_cl1_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl1_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu1_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd1_wayC :std_ulogic; +signal p1_way_data_upd1_wayC :std_ulogic; +signal congr_cl1_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl1_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu1_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd1_wayD :std_ulogic; +signal p1_way_data_upd1_wayD :std_ulogic; +signal congr_cl1_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl1_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu1_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd1_wayE :std_ulogic; +signal p1_way_data_upd1_wayE :std_ulogic; +signal congr_cl1_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl1_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu1_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd1_wayF :std_ulogic; +signal p1_way_data_upd1_wayF :std_ulogic; +signal congr_cl1_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl1_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu1_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd1_wayG :std_ulogic; +signal p1_way_data_upd1_wayG :std_ulogic; +signal congr_cl1_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl1_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu1_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd1_wayH :std_ulogic; +signal p1_way_data_upd1_wayH :std_ulogic; +signal p0_congr_cl2_m :std_ulogic; +signal p1_congr_cl2_m :std_ulogic; +signal p0_congr_cl2_act_d :std_ulogic; +signal p0_congr_cl2_act_q :std_ulogic; +signal p1_congr_cl2_act_d :std_ulogic; +signal p1_congr_cl2_act_q :std_ulogic; +signal congr_cl2_act :std_ulogic; +signal congr_cl2_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl2_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu2_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd2_wayA :std_ulogic; +signal p1_way_data_upd2_wayA :std_ulogic; +signal congr_cl2_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl2_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu2_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd2_wayB :std_ulogic; +signal p1_way_data_upd2_wayB :std_ulogic; +signal congr_cl2_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl2_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu2_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd2_wayC :std_ulogic; +signal p1_way_data_upd2_wayC :std_ulogic; +signal congr_cl2_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl2_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu2_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd2_wayD :std_ulogic; +signal p1_way_data_upd2_wayD :std_ulogic; +signal congr_cl2_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl2_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu2_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd2_wayE :std_ulogic; +signal p1_way_data_upd2_wayE :std_ulogic; +signal congr_cl2_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl2_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu2_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd2_wayF :std_ulogic; +signal p1_way_data_upd2_wayF :std_ulogic; +signal congr_cl2_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl2_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu2_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd2_wayG :std_ulogic; +signal p1_way_data_upd2_wayG :std_ulogic; +signal congr_cl2_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl2_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu2_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd2_wayH :std_ulogic; +signal p1_way_data_upd2_wayH :std_ulogic; +signal p0_congr_cl3_m :std_ulogic; +signal p1_congr_cl3_m :std_ulogic; +signal p0_congr_cl3_act_d :std_ulogic; +signal p0_congr_cl3_act_q :std_ulogic; +signal p1_congr_cl3_act_d :std_ulogic; +signal p1_congr_cl3_act_q :std_ulogic; +signal congr_cl3_act :std_ulogic; +signal congr_cl3_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl3_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu3_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd3_wayA :std_ulogic; +signal p1_way_data_upd3_wayA :std_ulogic; +signal congr_cl3_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl3_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu3_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd3_wayB :std_ulogic; +signal p1_way_data_upd3_wayB :std_ulogic; +signal congr_cl3_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl3_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu3_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd3_wayC :std_ulogic; +signal p1_way_data_upd3_wayC :std_ulogic; +signal congr_cl3_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl3_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu3_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd3_wayD :std_ulogic; +signal p1_way_data_upd3_wayD :std_ulogic; +signal congr_cl3_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl3_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu3_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd3_wayE :std_ulogic; +signal p1_way_data_upd3_wayE :std_ulogic; +signal congr_cl3_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl3_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu3_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd3_wayF :std_ulogic; +signal p1_way_data_upd3_wayF :std_ulogic; +signal congr_cl3_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl3_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu3_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd3_wayG :std_ulogic; +signal p1_way_data_upd3_wayG :std_ulogic; +signal congr_cl3_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl3_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu3_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd3_wayH :std_ulogic; +signal p1_way_data_upd3_wayH :std_ulogic; +signal p0_congr_cl4_m :std_ulogic; +signal p1_congr_cl4_m :std_ulogic; +signal p0_congr_cl4_act_d :std_ulogic; +signal p0_congr_cl4_act_q :std_ulogic; +signal p1_congr_cl4_act_d :std_ulogic; +signal p1_congr_cl4_act_q :std_ulogic; +signal congr_cl4_act :std_ulogic; +signal congr_cl4_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl4_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu4_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd4_wayA :std_ulogic; +signal p1_way_data_upd4_wayA :std_ulogic; +signal congr_cl4_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl4_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu4_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd4_wayB :std_ulogic; +signal p1_way_data_upd4_wayB :std_ulogic; +signal congr_cl4_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl4_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu4_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd4_wayC :std_ulogic; +signal p1_way_data_upd4_wayC :std_ulogic; +signal congr_cl4_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl4_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu4_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd4_wayD :std_ulogic; +signal p1_way_data_upd4_wayD :std_ulogic; +signal congr_cl4_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl4_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu4_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd4_wayE :std_ulogic; +signal p1_way_data_upd4_wayE :std_ulogic; +signal congr_cl4_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl4_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu4_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd4_wayF :std_ulogic; +signal p1_way_data_upd4_wayF :std_ulogic; +signal congr_cl4_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl4_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu4_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd4_wayG :std_ulogic; +signal p1_way_data_upd4_wayG :std_ulogic; +signal congr_cl4_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl4_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu4_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd4_wayH :std_ulogic; +signal p1_way_data_upd4_wayH :std_ulogic; +signal p0_congr_cl5_m :std_ulogic; +signal p1_congr_cl5_m :std_ulogic; +signal p0_congr_cl5_act_d :std_ulogic; +signal p0_congr_cl5_act_q :std_ulogic; +signal p1_congr_cl5_act_d :std_ulogic; +signal p1_congr_cl5_act_q :std_ulogic; +signal congr_cl5_act :std_ulogic; +signal congr_cl5_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl5_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu5_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd5_wayA :std_ulogic; +signal p1_way_data_upd5_wayA :std_ulogic; +signal congr_cl5_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl5_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu5_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd5_wayB :std_ulogic; +signal p1_way_data_upd5_wayB :std_ulogic; +signal congr_cl5_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl5_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu5_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd5_wayC :std_ulogic; +signal p1_way_data_upd5_wayC :std_ulogic; +signal congr_cl5_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl5_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu5_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd5_wayD :std_ulogic; +signal p1_way_data_upd5_wayD :std_ulogic; +signal congr_cl5_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl5_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu5_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd5_wayE :std_ulogic; +signal p1_way_data_upd5_wayE :std_ulogic; +signal congr_cl5_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl5_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu5_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd5_wayF :std_ulogic; +signal p1_way_data_upd5_wayF :std_ulogic; +signal congr_cl5_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl5_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu5_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd5_wayG :std_ulogic; +signal p1_way_data_upd5_wayG :std_ulogic; +signal congr_cl5_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl5_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu5_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd5_wayH :std_ulogic; +signal p1_way_data_upd5_wayH :std_ulogic; +signal p0_congr_cl6_m :std_ulogic; +signal p1_congr_cl6_m :std_ulogic; +signal p0_congr_cl6_act_d :std_ulogic; +signal p0_congr_cl6_act_q :std_ulogic; +signal p1_congr_cl6_act_d :std_ulogic; +signal p1_congr_cl6_act_q :std_ulogic; +signal congr_cl6_act :std_ulogic; +signal congr_cl6_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl6_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu6_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd6_wayA :std_ulogic; +signal p1_way_data_upd6_wayA :std_ulogic; +signal congr_cl6_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl6_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu6_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd6_wayB :std_ulogic; +signal p1_way_data_upd6_wayB :std_ulogic; +signal congr_cl6_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl6_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu6_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd6_wayC :std_ulogic; +signal p1_way_data_upd6_wayC :std_ulogic; +signal congr_cl6_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl6_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu6_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd6_wayD :std_ulogic; +signal p1_way_data_upd6_wayD :std_ulogic; +signal congr_cl6_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl6_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu6_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd6_wayE :std_ulogic; +signal p1_way_data_upd6_wayE :std_ulogic; +signal congr_cl6_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl6_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu6_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd6_wayF :std_ulogic; +signal p1_way_data_upd6_wayF :std_ulogic; +signal congr_cl6_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl6_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu6_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd6_wayG :std_ulogic; +signal p1_way_data_upd6_wayG :std_ulogic; +signal congr_cl6_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl6_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu6_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd6_wayH :std_ulogic; +signal p1_way_data_upd6_wayH :std_ulogic; +signal p0_congr_cl7_m :std_ulogic; +signal p1_congr_cl7_m :std_ulogic; +signal p0_congr_cl7_act_d :std_ulogic; +signal p0_congr_cl7_act_q :std_ulogic; +signal p1_congr_cl7_act_d :std_ulogic; +signal p1_congr_cl7_act_q :std_ulogic; +signal congr_cl7_act :std_ulogic; +signal congr_cl7_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl7_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu7_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd7_wayA :std_ulogic; +signal p1_way_data_upd7_wayA :std_ulogic; +signal congr_cl7_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl7_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu7_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd7_wayB :std_ulogic; +signal p1_way_data_upd7_wayB :std_ulogic; +signal congr_cl7_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl7_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu7_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd7_wayC :std_ulogic; +signal p1_way_data_upd7_wayC :std_ulogic; +signal congr_cl7_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl7_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu7_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd7_wayD :std_ulogic; +signal p1_way_data_upd7_wayD :std_ulogic; +signal congr_cl7_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl7_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu7_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd7_wayE :std_ulogic; +signal p1_way_data_upd7_wayE :std_ulogic; +signal congr_cl7_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl7_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu7_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd7_wayF :std_ulogic; +signal p1_way_data_upd7_wayF :std_ulogic; +signal congr_cl7_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl7_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu7_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd7_wayG :std_ulogic; +signal p1_way_data_upd7_wayG :std_ulogic; +signal congr_cl7_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl7_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu7_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd7_wayH :std_ulogic; +signal p1_way_data_upd7_wayH :std_ulogic; +signal p0_congr_cl8_m :std_ulogic; +signal p1_congr_cl8_m :std_ulogic; +signal p0_congr_cl8_act_d :std_ulogic; +signal p0_congr_cl8_act_q :std_ulogic; +signal p1_congr_cl8_act_d :std_ulogic; +signal p1_congr_cl8_act_q :std_ulogic; +signal congr_cl8_act :std_ulogic; +signal congr_cl8_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl8_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu8_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd8_wayA :std_ulogic; +signal p1_way_data_upd8_wayA :std_ulogic; +signal congr_cl8_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl8_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu8_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd8_wayB :std_ulogic; +signal p1_way_data_upd8_wayB :std_ulogic; +signal congr_cl8_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl8_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu8_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd8_wayC :std_ulogic; +signal p1_way_data_upd8_wayC :std_ulogic; +signal congr_cl8_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl8_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu8_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd8_wayD :std_ulogic; +signal p1_way_data_upd8_wayD :std_ulogic; +signal congr_cl8_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl8_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu8_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd8_wayE :std_ulogic; +signal p1_way_data_upd8_wayE :std_ulogic; +signal congr_cl8_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl8_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu8_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd8_wayF :std_ulogic; +signal p1_way_data_upd8_wayF :std_ulogic; +signal congr_cl8_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl8_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu8_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd8_wayG :std_ulogic; +signal p1_way_data_upd8_wayG :std_ulogic; +signal congr_cl8_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl8_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu8_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd8_wayH :std_ulogic; +signal p1_way_data_upd8_wayH :std_ulogic; +signal p0_congr_cl9_m :std_ulogic; +signal p1_congr_cl9_m :std_ulogic; +signal p0_congr_cl9_act_d :std_ulogic; +signal p0_congr_cl9_act_q :std_ulogic; +signal p1_congr_cl9_act_d :std_ulogic; +signal p1_congr_cl9_act_q :std_ulogic; +signal congr_cl9_act :std_ulogic; +signal congr_cl9_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl9_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu9_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd9_wayA :std_ulogic; +signal p1_way_data_upd9_wayA :std_ulogic; +signal congr_cl9_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl9_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu9_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd9_wayB :std_ulogic; +signal p1_way_data_upd9_wayB :std_ulogic; +signal congr_cl9_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl9_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu9_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd9_wayC :std_ulogic; +signal p1_way_data_upd9_wayC :std_ulogic; +signal congr_cl9_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl9_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu9_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd9_wayD :std_ulogic; +signal p1_way_data_upd9_wayD :std_ulogic; +signal congr_cl9_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl9_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu9_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd9_wayE :std_ulogic; +signal p1_way_data_upd9_wayE :std_ulogic; +signal congr_cl9_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl9_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu9_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd9_wayF :std_ulogic; +signal p1_way_data_upd9_wayF :std_ulogic; +signal congr_cl9_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl9_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu9_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd9_wayG :std_ulogic; +signal p1_way_data_upd9_wayG :std_ulogic; +signal congr_cl9_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl9_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu9_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd9_wayH :std_ulogic; +signal p1_way_data_upd9_wayH :std_ulogic; +signal p0_congr_cl10_m :std_ulogic; +signal p1_congr_cl10_m :std_ulogic; +signal p0_congr_cl10_act_d :std_ulogic; +signal p0_congr_cl10_act_q :std_ulogic; +signal p1_congr_cl10_act_d :std_ulogic; +signal p1_congr_cl10_act_q :std_ulogic; +signal congr_cl10_act :std_ulogic; +signal congr_cl10_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl10_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu10_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd10_wayA :std_ulogic; +signal p1_way_data_upd10_wayA :std_ulogic; +signal congr_cl10_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl10_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu10_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd10_wayB :std_ulogic; +signal p1_way_data_upd10_wayB :std_ulogic; +signal congr_cl10_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl10_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu10_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd10_wayC :std_ulogic; +signal p1_way_data_upd10_wayC :std_ulogic; +signal congr_cl10_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl10_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu10_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd10_wayD :std_ulogic; +signal p1_way_data_upd10_wayD :std_ulogic; +signal congr_cl10_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl10_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu10_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd10_wayE :std_ulogic; +signal p1_way_data_upd10_wayE :std_ulogic; +signal congr_cl10_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl10_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu10_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd10_wayF :std_ulogic; +signal p1_way_data_upd10_wayF :std_ulogic; +signal congr_cl10_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl10_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu10_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd10_wayG :std_ulogic; +signal p1_way_data_upd10_wayG :std_ulogic; +signal congr_cl10_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl10_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu10_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd10_wayH :std_ulogic; +signal p1_way_data_upd10_wayH :std_ulogic; +signal p0_congr_cl11_m :std_ulogic; +signal p1_congr_cl11_m :std_ulogic; +signal p0_congr_cl11_act_d :std_ulogic; +signal p0_congr_cl11_act_q :std_ulogic; +signal p1_congr_cl11_act_d :std_ulogic; +signal p1_congr_cl11_act_q :std_ulogic; +signal congr_cl11_act :std_ulogic; +signal congr_cl11_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl11_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu11_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd11_wayA :std_ulogic; +signal p1_way_data_upd11_wayA :std_ulogic; +signal congr_cl11_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl11_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu11_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd11_wayB :std_ulogic; +signal p1_way_data_upd11_wayB :std_ulogic; +signal congr_cl11_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl11_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu11_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd11_wayC :std_ulogic; +signal p1_way_data_upd11_wayC :std_ulogic; +signal congr_cl11_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl11_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu11_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd11_wayD :std_ulogic; +signal p1_way_data_upd11_wayD :std_ulogic; +signal congr_cl11_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl11_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu11_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd11_wayE :std_ulogic; +signal p1_way_data_upd11_wayE :std_ulogic; +signal congr_cl11_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl11_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu11_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd11_wayF :std_ulogic; +signal p1_way_data_upd11_wayF :std_ulogic; +signal congr_cl11_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl11_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu11_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd11_wayG :std_ulogic; +signal p1_way_data_upd11_wayG :std_ulogic; +signal congr_cl11_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl11_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu11_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd11_wayH :std_ulogic; +signal p1_way_data_upd11_wayH :std_ulogic; +signal p0_congr_cl12_m :std_ulogic; +signal p1_congr_cl12_m :std_ulogic; +signal p0_congr_cl12_act_d :std_ulogic; +signal p0_congr_cl12_act_q :std_ulogic; +signal p1_congr_cl12_act_d :std_ulogic; +signal p1_congr_cl12_act_q :std_ulogic; +signal congr_cl12_act :std_ulogic; +signal congr_cl12_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl12_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu12_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd12_wayA :std_ulogic; +signal p1_way_data_upd12_wayA :std_ulogic; +signal congr_cl12_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl12_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu12_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd12_wayB :std_ulogic; +signal p1_way_data_upd12_wayB :std_ulogic; +signal congr_cl12_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl12_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu12_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd12_wayC :std_ulogic; +signal p1_way_data_upd12_wayC :std_ulogic; +signal congr_cl12_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl12_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu12_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd12_wayD :std_ulogic; +signal p1_way_data_upd12_wayD :std_ulogic; +signal congr_cl12_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl12_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu12_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd12_wayE :std_ulogic; +signal p1_way_data_upd12_wayE :std_ulogic; +signal congr_cl12_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl12_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu12_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd12_wayF :std_ulogic; +signal p1_way_data_upd12_wayF :std_ulogic; +signal congr_cl12_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl12_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu12_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd12_wayG :std_ulogic; +signal p1_way_data_upd12_wayG :std_ulogic; +signal congr_cl12_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl12_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu12_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd12_wayH :std_ulogic; +signal p1_way_data_upd12_wayH :std_ulogic; +signal p0_congr_cl13_m :std_ulogic; +signal p1_congr_cl13_m :std_ulogic; +signal p0_congr_cl13_act_d :std_ulogic; +signal p0_congr_cl13_act_q :std_ulogic; +signal p1_congr_cl13_act_d :std_ulogic; +signal p1_congr_cl13_act_q :std_ulogic; +signal congr_cl13_act :std_ulogic; +signal congr_cl13_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl13_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu13_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd13_wayA :std_ulogic; +signal p1_way_data_upd13_wayA :std_ulogic; +signal congr_cl13_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl13_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu13_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd13_wayB :std_ulogic; +signal p1_way_data_upd13_wayB :std_ulogic; +signal congr_cl13_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl13_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu13_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd13_wayC :std_ulogic; +signal p1_way_data_upd13_wayC :std_ulogic; +signal congr_cl13_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl13_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu13_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd13_wayD :std_ulogic; +signal p1_way_data_upd13_wayD :std_ulogic; +signal congr_cl13_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl13_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu13_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd13_wayE :std_ulogic; +signal p1_way_data_upd13_wayE :std_ulogic; +signal congr_cl13_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl13_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu13_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd13_wayF :std_ulogic; +signal p1_way_data_upd13_wayF :std_ulogic; +signal congr_cl13_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl13_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu13_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd13_wayG :std_ulogic; +signal p1_way_data_upd13_wayG :std_ulogic; +signal congr_cl13_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl13_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu13_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd13_wayH :std_ulogic; +signal p1_way_data_upd13_wayH :std_ulogic; +signal p0_congr_cl14_m :std_ulogic; +signal p1_congr_cl14_m :std_ulogic; +signal p0_congr_cl14_act_d :std_ulogic; +signal p0_congr_cl14_act_q :std_ulogic; +signal p1_congr_cl14_act_d :std_ulogic; +signal p1_congr_cl14_act_q :std_ulogic; +signal congr_cl14_act :std_ulogic; +signal congr_cl14_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl14_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu14_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd14_wayA :std_ulogic; +signal p1_way_data_upd14_wayA :std_ulogic; +signal congr_cl14_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl14_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu14_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd14_wayB :std_ulogic; +signal p1_way_data_upd14_wayB :std_ulogic; +signal congr_cl14_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl14_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu14_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd14_wayC :std_ulogic; +signal p1_way_data_upd14_wayC :std_ulogic; +signal congr_cl14_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl14_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu14_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd14_wayD :std_ulogic; +signal p1_way_data_upd14_wayD :std_ulogic; +signal congr_cl14_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl14_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu14_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd14_wayE :std_ulogic; +signal p1_way_data_upd14_wayE :std_ulogic; +signal congr_cl14_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl14_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu14_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd14_wayF :std_ulogic; +signal p1_way_data_upd14_wayF :std_ulogic; +signal congr_cl14_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl14_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu14_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd14_wayG :std_ulogic; +signal p1_way_data_upd14_wayG :std_ulogic; +signal congr_cl14_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl14_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu14_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd14_wayH :std_ulogic; +signal p1_way_data_upd14_wayH :std_ulogic; +signal p0_congr_cl15_m :std_ulogic; +signal p1_congr_cl15_m :std_ulogic; +signal p0_congr_cl15_act_d :std_ulogic; +signal p0_congr_cl15_act_q :std_ulogic; +signal p1_congr_cl15_act_d :std_ulogic; +signal p1_congr_cl15_act_q :std_ulogic; +signal congr_cl15_act :std_ulogic; +signal congr_cl15_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl15_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu15_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd15_wayA :std_ulogic; +signal p1_way_data_upd15_wayA :std_ulogic; +signal congr_cl15_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl15_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu15_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd15_wayB :std_ulogic; +signal p1_way_data_upd15_wayB :std_ulogic; +signal congr_cl15_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl15_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu15_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd15_wayC :std_ulogic; +signal p1_way_data_upd15_wayC :std_ulogic; +signal congr_cl15_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl15_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu15_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd15_wayD :std_ulogic; +signal p1_way_data_upd15_wayD :std_ulogic; +signal congr_cl15_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl15_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu15_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd15_wayE :std_ulogic; +signal p1_way_data_upd15_wayE :std_ulogic; +signal congr_cl15_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl15_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu15_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd15_wayF :std_ulogic; +signal p1_way_data_upd15_wayF :std_ulogic; +signal congr_cl15_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl15_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu15_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd15_wayG :std_ulogic; +signal p1_way_data_upd15_wayG :std_ulogic; +signal congr_cl15_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl15_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu15_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd15_wayH :std_ulogic; +signal p1_way_data_upd15_wayH :std_ulogic; +signal p0_congr_cl16_m :std_ulogic; +signal p1_congr_cl16_m :std_ulogic; +signal p0_congr_cl16_act_d :std_ulogic; +signal p0_congr_cl16_act_q :std_ulogic; +signal p1_congr_cl16_act_d :std_ulogic; +signal p1_congr_cl16_act_q :std_ulogic; +signal congr_cl16_act :std_ulogic; +signal congr_cl16_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl16_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu16_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd16_wayA :std_ulogic; +signal p1_way_data_upd16_wayA :std_ulogic; +signal congr_cl16_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl16_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu16_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd16_wayB :std_ulogic; +signal p1_way_data_upd16_wayB :std_ulogic; +signal congr_cl16_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl16_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu16_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd16_wayC :std_ulogic; +signal p1_way_data_upd16_wayC :std_ulogic; +signal congr_cl16_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl16_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu16_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd16_wayD :std_ulogic; +signal p1_way_data_upd16_wayD :std_ulogic; +signal congr_cl16_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl16_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu16_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd16_wayE :std_ulogic; +signal p1_way_data_upd16_wayE :std_ulogic; +signal congr_cl16_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl16_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu16_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd16_wayF :std_ulogic; +signal p1_way_data_upd16_wayF :std_ulogic; +signal congr_cl16_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl16_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu16_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd16_wayG :std_ulogic; +signal p1_way_data_upd16_wayG :std_ulogic; +signal congr_cl16_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl16_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu16_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd16_wayH :std_ulogic; +signal p1_way_data_upd16_wayH :std_ulogic; +signal p0_congr_cl17_m :std_ulogic; +signal p1_congr_cl17_m :std_ulogic; +signal p0_congr_cl17_act_d :std_ulogic; +signal p0_congr_cl17_act_q :std_ulogic; +signal p1_congr_cl17_act_d :std_ulogic; +signal p1_congr_cl17_act_q :std_ulogic; +signal congr_cl17_act :std_ulogic; +signal congr_cl17_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl17_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu17_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd17_wayA :std_ulogic; +signal p1_way_data_upd17_wayA :std_ulogic; +signal congr_cl17_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl17_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu17_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd17_wayB :std_ulogic; +signal p1_way_data_upd17_wayB :std_ulogic; +signal congr_cl17_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl17_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu17_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd17_wayC :std_ulogic; +signal p1_way_data_upd17_wayC :std_ulogic; +signal congr_cl17_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl17_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu17_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd17_wayD :std_ulogic; +signal p1_way_data_upd17_wayD :std_ulogic; +signal congr_cl17_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl17_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu17_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd17_wayE :std_ulogic; +signal p1_way_data_upd17_wayE :std_ulogic; +signal congr_cl17_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl17_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu17_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd17_wayF :std_ulogic; +signal p1_way_data_upd17_wayF :std_ulogic; +signal congr_cl17_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl17_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu17_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd17_wayG :std_ulogic; +signal p1_way_data_upd17_wayG :std_ulogic; +signal congr_cl17_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl17_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu17_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd17_wayH :std_ulogic; +signal p1_way_data_upd17_wayH :std_ulogic; +signal p0_congr_cl18_m :std_ulogic; +signal p1_congr_cl18_m :std_ulogic; +signal p0_congr_cl18_act_d :std_ulogic; +signal p0_congr_cl18_act_q :std_ulogic; +signal p1_congr_cl18_act_d :std_ulogic; +signal p1_congr_cl18_act_q :std_ulogic; +signal congr_cl18_act :std_ulogic; +signal congr_cl18_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl18_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu18_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd18_wayA :std_ulogic; +signal p1_way_data_upd18_wayA :std_ulogic; +signal congr_cl18_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl18_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu18_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd18_wayB :std_ulogic; +signal p1_way_data_upd18_wayB :std_ulogic; +signal congr_cl18_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl18_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu18_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd18_wayC :std_ulogic; +signal p1_way_data_upd18_wayC :std_ulogic; +signal congr_cl18_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl18_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu18_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd18_wayD :std_ulogic; +signal p1_way_data_upd18_wayD :std_ulogic; +signal congr_cl18_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl18_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu18_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd18_wayE :std_ulogic; +signal p1_way_data_upd18_wayE :std_ulogic; +signal congr_cl18_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl18_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu18_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd18_wayF :std_ulogic; +signal p1_way_data_upd18_wayF :std_ulogic; +signal congr_cl18_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl18_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu18_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd18_wayG :std_ulogic; +signal p1_way_data_upd18_wayG :std_ulogic; +signal congr_cl18_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl18_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu18_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd18_wayH :std_ulogic; +signal p1_way_data_upd18_wayH :std_ulogic; +signal p0_congr_cl19_m :std_ulogic; +signal p1_congr_cl19_m :std_ulogic; +signal p0_congr_cl19_act_d :std_ulogic; +signal p0_congr_cl19_act_q :std_ulogic; +signal p1_congr_cl19_act_d :std_ulogic; +signal p1_congr_cl19_act_q :std_ulogic; +signal congr_cl19_act :std_ulogic; +signal congr_cl19_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl19_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu19_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd19_wayA :std_ulogic; +signal p1_way_data_upd19_wayA :std_ulogic; +signal congr_cl19_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl19_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu19_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd19_wayB :std_ulogic; +signal p1_way_data_upd19_wayB :std_ulogic; +signal congr_cl19_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl19_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu19_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd19_wayC :std_ulogic; +signal p1_way_data_upd19_wayC :std_ulogic; +signal congr_cl19_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl19_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu19_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd19_wayD :std_ulogic; +signal p1_way_data_upd19_wayD :std_ulogic; +signal congr_cl19_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl19_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu19_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd19_wayE :std_ulogic; +signal p1_way_data_upd19_wayE :std_ulogic; +signal congr_cl19_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl19_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu19_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd19_wayF :std_ulogic; +signal p1_way_data_upd19_wayF :std_ulogic; +signal congr_cl19_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl19_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu19_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd19_wayG :std_ulogic; +signal p1_way_data_upd19_wayG :std_ulogic; +signal congr_cl19_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl19_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu19_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd19_wayH :std_ulogic; +signal p1_way_data_upd19_wayH :std_ulogic; +signal p0_congr_cl20_m :std_ulogic; +signal p1_congr_cl20_m :std_ulogic; +signal p0_congr_cl20_act_d :std_ulogic; +signal p0_congr_cl20_act_q :std_ulogic; +signal p1_congr_cl20_act_d :std_ulogic; +signal p1_congr_cl20_act_q :std_ulogic; +signal congr_cl20_act :std_ulogic; +signal congr_cl20_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl20_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu20_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd20_wayA :std_ulogic; +signal p1_way_data_upd20_wayA :std_ulogic; +signal congr_cl20_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl20_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu20_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd20_wayB :std_ulogic; +signal p1_way_data_upd20_wayB :std_ulogic; +signal congr_cl20_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl20_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu20_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd20_wayC :std_ulogic; +signal p1_way_data_upd20_wayC :std_ulogic; +signal congr_cl20_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl20_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu20_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd20_wayD :std_ulogic; +signal p1_way_data_upd20_wayD :std_ulogic; +signal congr_cl20_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl20_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu20_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd20_wayE :std_ulogic; +signal p1_way_data_upd20_wayE :std_ulogic; +signal congr_cl20_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl20_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu20_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd20_wayF :std_ulogic; +signal p1_way_data_upd20_wayF :std_ulogic; +signal congr_cl20_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl20_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu20_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd20_wayG :std_ulogic; +signal p1_way_data_upd20_wayG :std_ulogic; +signal congr_cl20_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl20_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu20_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd20_wayH :std_ulogic; +signal p1_way_data_upd20_wayH :std_ulogic; +signal p0_congr_cl21_m :std_ulogic; +signal p1_congr_cl21_m :std_ulogic; +signal p0_congr_cl21_act_d :std_ulogic; +signal p0_congr_cl21_act_q :std_ulogic; +signal p1_congr_cl21_act_d :std_ulogic; +signal p1_congr_cl21_act_q :std_ulogic; +signal congr_cl21_act :std_ulogic; +signal congr_cl21_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl21_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu21_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd21_wayA :std_ulogic; +signal p1_way_data_upd21_wayA :std_ulogic; +signal congr_cl21_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl21_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu21_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd21_wayB :std_ulogic; +signal p1_way_data_upd21_wayB :std_ulogic; +signal congr_cl21_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl21_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu21_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd21_wayC :std_ulogic; +signal p1_way_data_upd21_wayC :std_ulogic; +signal congr_cl21_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl21_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu21_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd21_wayD :std_ulogic; +signal p1_way_data_upd21_wayD :std_ulogic; +signal congr_cl21_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl21_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu21_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd21_wayE :std_ulogic; +signal p1_way_data_upd21_wayE :std_ulogic; +signal congr_cl21_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl21_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu21_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd21_wayF :std_ulogic; +signal p1_way_data_upd21_wayF :std_ulogic; +signal congr_cl21_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl21_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu21_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd21_wayG :std_ulogic; +signal p1_way_data_upd21_wayG :std_ulogic; +signal congr_cl21_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl21_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu21_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd21_wayH :std_ulogic; +signal p1_way_data_upd21_wayH :std_ulogic; +signal p0_congr_cl22_m :std_ulogic; +signal p1_congr_cl22_m :std_ulogic; +signal p0_congr_cl22_act_d :std_ulogic; +signal p0_congr_cl22_act_q :std_ulogic; +signal p1_congr_cl22_act_d :std_ulogic; +signal p1_congr_cl22_act_q :std_ulogic; +signal congr_cl22_act :std_ulogic; +signal congr_cl22_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl22_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu22_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd22_wayA :std_ulogic; +signal p1_way_data_upd22_wayA :std_ulogic; +signal congr_cl22_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl22_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu22_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd22_wayB :std_ulogic; +signal p1_way_data_upd22_wayB :std_ulogic; +signal congr_cl22_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl22_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu22_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd22_wayC :std_ulogic; +signal p1_way_data_upd22_wayC :std_ulogic; +signal congr_cl22_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl22_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu22_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd22_wayD :std_ulogic; +signal p1_way_data_upd22_wayD :std_ulogic; +signal congr_cl22_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl22_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu22_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd22_wayE :std_ulogic; +signal p1_way_data_upd22_wayE :std_ulogic; +signal congr_cl22_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl22_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu22_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd22_wayF :std_ulogic; +signal p1_way_data_upd22_wayF :std_ulogic; +signal congr_cl22_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl22_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu22_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd22_wayG :std_ulogic; +signal p1_way_data_upd22_wayG :std_ulogic; +signal congr_cl22_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl22_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu22_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd22_wayH :std_ulogic; +signal p1_way_data_upd22_wayH :std_ulogic; +signal p0_congr_cl23_m :std_ulogic; +signal p1_congr_cl23_m :std_ulogic; +signal p0_congr_cl23_act_d :std_ulogic; +signal p0_congr_cl23_act_q :std_ulogic; +signal p1_congr_cl23_act_d :std_ulogic; +signal p1_congr_cl23_act_q :std_ulogic; +signal congr_cl23_act :std_ulogic; +signal congr_cl23_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl23_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu23_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd23_wayA :std_ulogic; +signal p1_way_data_upd23_wayA :std_ulogic; +signal congr_cl23_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl23_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu23_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd23_wayB :std_ulogic; +signal p1_way_data_upd23_wayB :std_ulogic; +signal congr_cl23_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl23_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu23_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd23_wayC :std_ulogic; +signal p1_way_data_upd23_wayC :std_ulogic; +signal congr_cl23_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl23_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu23_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd23_wayD :std_ulogic; +signal p1_way_data_upd23_wayD :std_ulogic; +signal congr_cl23_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl23_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu23_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd23_wayE :std_ulogic; +signal p1_way_data_upd23_wayE :std_ulogic; +signal congr_cl23_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl23_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu23_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd23_wayF :std_ulogic; +signal p1_way_data_upd23_wayF :std_ulogic; +signal congr_cl23_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl23_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu23_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd23_wayG :std_ulogic; +signal p1_way_data_upd23_wayG :std_ulogic; +signal congr_cl23_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl23_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu23_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd23_wayH :std_ulogic; +signal p1_way_data_upd23_wayH :std_ulogic; +signal p0_congr_cl24_m :std_ulogic; +signal p1_congr_cl24_m :std_ulogic; +signal p0_congr_cl24_act_d :std_ulogic; +signal p0_congr_cl24_act_q :std_ulogic; +signal p1_congr_cl24_act_d :std_ulogic; +signal p1_congr_cl24_act_q :std_ulogic; +signal congr_cl24_act :std_ulogic; +signal congr_cl24_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl24_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu24_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd24_wayA :std_ulogic; +signal p1_way_data_upd24_wayA :std_ulogic; +signal congr_cl24_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl24_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu24_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd24_wayB :std_ulogic; +signal p1_way_data_upd24_wayB :std_ulogic; +signal congr_cl24_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl24_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu24_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd24_wayC :std_ulogic; +signal p1_way_data_upd24_wayC :std_ulogic; +signal congr_cl24_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl24_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu24_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd24_wayD :std_ulogic; +signal p1_way_data_upd24_wayD :std_ulogic; +signal congr_cl24_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl24_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu24_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd24_wayE :std_ulogic; +signal p1_way_data_upd24_wayE :std_ulogic; +signal congr_cl24_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl24_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu24_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd24_wayF :std_ulogic; +signal p1_way_data_upd24_wayF :std_ulogic; +signal congr_cl24_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl24_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu24_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd24_wayG :std_ulogic; +signal p1_way_data_upd24_wayG :std_ulogic; +signal congr_cl24_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl24_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu24_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd24_wayH :std_ulogic; +signal p1_way_data_upd24_wayH :std_ulogic; +signal p0_congr_cl25_m :std_ulogic; +signal p1_congr_cl25_m :std_ulogic; +signal p0_congr_cl25_act_d :std_ulogic; +signal p0_congr_cl25_act_q :std_ulogic; +signal p1_congr_cl25_act_d :std_ulogic; +signal p1_congr_cl25_act_q :std_ulogic; +signal congr_cl25_act :std_ulogic; +signal congr_cl25_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl25_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu25_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd25_wayA :std_ulogic; +signal p1_way_data_upd25_wayA :std_ulogic; +signal congr_cl25_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl25_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu25_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd25_wayB :std_ulogic; +signal p1_way_data_upd25_wayB :std_ulogic; +signal congr_cl25_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl25_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu25_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd25_wayC :std_ulogic; +signal p1_way_data_upd25_wayC :std_ulogic; +signal congr_cl25_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl25_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu25_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd25_wayD :std_ulogic; +signal p1_way_data_upd25_wayD :std_ulogic; +signal congr_cl25_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl25_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu25_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd25_wayE :std_ulogic; +signal p1_way_data_upd25_wayE :std_ulogic; +signal congr_cl25_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl25_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu25_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd25_wayF :std_ulogic; +signal p1_way_data_upd25_wayF :std_ulogic; +signal congr_cl25_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl25_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu25_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd25_wayG :std_ulogic; +signal p1_way_data_upd25_wayG :std_ulogic; +signal congr_cl25_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl25_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu25_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd25_wayH :std_ulogic; +signal p1_way_data_upd25_wayH :std_ulogic; +signal p0_congr_cl26_m :std_ulogic; +signal p1_congr_cl26_m :std_ulogic; +signal p0_congr_cl26_act_d :std_ulogic; +signal p0_congr_cl26_act_q :std_ulogic; +signal p1_congr_cl26_act_d :std_ulogic; +signal p1_congr_cl26_act_q :std_ulogic; +signal congr_cl26_act :std_ulogic; +signal congr_cl26_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl26_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu26_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd26_wayA :std_ulogic; +signal p1_way_data_upd26_wayA :std_ulogic; +signal congr_cl26_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl26_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu26_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd26_wayB :std_ulogic; +signal p1_way_data_upd26_wayB :std_ulogic; +signal congr_cl26_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl26_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu26_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd26_wayC :std_ulogic; +signal p1_way_data_upd26_wayC :std_ulogic; +signal congr_cl26_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl26_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu26_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd26_wayD :std_ulogic; +signal p1_way_data_upd26_wayD :std_ulogic; +signal congr_cl26_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl26_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu26_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd26_wayE :std_ulogic; +signal p1_way_data_upd26_wayE :std_ulogic; +signal congr_cl26_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl26_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu26_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd26_wayF :std_ulogic; +signal p1_way_data_upd26_wayF :std_ulogic; +signal congr_cl26_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl26_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu26_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd26_wayG :std_ulogic; +signal p1_way_data_upd26_wayG :std_ulogic; +signal congr_cl26_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl26_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu26_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd26_wayH :std_ulogic; +signal p1_way_data_upd26_wayH :std_ulogic; +signal p0_congr_cl27_m :std_ulogic; +signal p1_congr_cl27_m :std_ulogic; +signal p0_congr_cl27_act_d :std_ulogic; +signal p0_congr_cl27_act_q :std_ulogic; +signal p1_congr_cl27_act_d :std_ulogic; +signal p1_congr_cl27_act_q :std_ulogic; +signal congr_cl27_act :std_ulogic; +signal congr_cl27_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl27_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu27_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd27_wayA :std_ulogic; +signal p1_way_data_upd27_wayA :std_ulogic; +signal congr_cl27_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl27_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu27_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd27_wayB :std_ulogic; +signal p1_way_data_upd27_wayB :std_ulogic; +signal congr_cl27_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl27_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu27_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd27_wayC :std_ulogic; +signal p1_way_data_upd27_wayC :std_ulogic; +signal congr_cl27_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl27_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu27_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd27_wayD :std_ulogic; +signal p1_way_data_upd27_wayD :std_ulogic; +signal congr_cl27_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl27_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu27_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd27_wayE :std_ulogic; +signal p1_way_data_upd27_wayE :std_ulogic; +signal congr_cl27_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl27_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu27_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd27_wayF :std_ulogic; +signal p1_way_data_upd27_wayF :std_ulogic; +signal congr_cl27_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl27_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu27_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd27_wayG :std_ulogic; +signal p1_way_data_upd27_wayG :std_ulogic; +signal congr_cl27_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl27_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu27_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd27_wayH :std_ulogic; +signal p1_way_data_upd27_wayH :std_ulogic; +signal p0_congr_cl28_m :std_ulogic; +signal p1_congr_cl28_m :std_ulogic; +signal p0_congr_cl28_act_d :std_ulogic; +signal p0_congr_cl28_act_q :std_ulogic; +signal p1_congr_cl28_act_d :std_ulogic; +signal p1_congr_cl28_act_q :std_ulogic; +signal congr_cl28_act :std_ulogic; +signal congr_cl28_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl28_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu28_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd28_wayA :std_ulogic; +signal p1_way_data_upd28_wayA :std_ulogic; +signal congr_cl28_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl28_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu28_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd28_wayB :std_ulogic; +signal p1_way_data_upd28_wayB :std_ulogic; +signal congr_cl28_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl28_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu28_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd28_wayC :std_ulogic; +signal p1_way_data_upd28_wayC :std_ulogic; +signal congr_cl28_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl28_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu28_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd28_wayD :std_ulogic; +signal p1_way_data_upd28_wayD :std_ulogic; +signal congr_cl28_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl28_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu28_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd28_wayE :std_ulogic; +signal p1_way_data_upd28_wayE :std_ulogic; +signal congr_cl28_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl28_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu28_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd28_wayF :std_ulogic; +signal p1_way_data_upd28_wayF :std_ulogic; +signal congr_cl28_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl28_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu28_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd28_wayG :std_ulogic; +signal p1_way_data_upd28_wayG :std_ulogic; +signal congr_cl28_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl28_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu28_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd28_wayH :std_ulogic; +signal p1_way_data_upd28_wayH :std_ulogic; +signal p0_congr_cl29_m :std_ulogic; +signal p1_congr_cl29_m :std_ulogic; +signal p0_congr_cl29_act_d :std_ulogic; +signal p0_congr_cl29_act_q :std_ulogic; +signal p1_congr_cl29_act_d :std_ulogic; +signal p1_congr_cl29_act_q :std_ulogic; +signal congr_cl29_act :std_ulogic; +signal congr_cl29_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl29_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu29_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd29_wayA :std_ulogic; +signal p1_way_data_upd29_wayA :std_ulogic; +signal congr_cl29_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl29_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu29_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd29_wayB :std_ulogic; +signal p1_way_data_upd29_wayB :std_ulogic; +signal congr_cl29_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl29_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu29_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd29_wayC :std_ulogic; +signal p1_way_data_upd29_wayC :std_ulogic; +signal congr_cl29_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl29_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu29_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd29_wayD :std_ulogic; +signal p1_way_data_upd29_wayD :std_ulogic; +signal congr_cl29_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl29_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu29_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd29_wayE :std_ulogic; +signal p1_way_data_upd29_wayE :std_ulogic; +signal congr_cl29_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl29_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu29_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd29_wayF :std_ulogic; +signal p1_way_data_upd29_wayF :std_ulogic; +signal congr_cl29_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl29_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu29_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd29_wayG :std_ulogic; +signal p1_way_data_upd29_wayG :std_ulogic; +signal congr_cl29_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl29_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu29_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd29_wayH :std_ulogic; +signal p1_way_data_upd29_wayH :std_ulogic; +signal p0_congr_cl30_m :std_ulogic; +signal p1_congr_cl30_m :std_ulogic; +signal p0_congr_cl30_act_d :std_ulogic; +signal p0_congr_cl30_act_q :std_ulogic; +signal p1_congr_cl30_act_d :std_ulogic; +signal p1_congr_cl30_act_q :std_ulogic; +signal congr_cl30_act :std_ulogic; +signal congr_cl30_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl30_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu30_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd30_wayA :std_ulogic; +signal p1_way_data_upd30_wayA :std_ulogic; +signal congr_cl30_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl30_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu30_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd30_wayB :std_ulogic; +signal p1_way_data_upd30_wayB :std_ulogic; +signal congr_cl30_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl30_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu30_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd30_wayC :std_ulogic; +signal p1_way_data_upd30_wayC :std_ulogic; +signal congr_cl30_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl30_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu30_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd30_wayD :std_ulogic; +signal p1_way_data_upd30_wayD :std_ulogic; +signal congr_cl30_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl30_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu30_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd30_wayE :std_ulogic; +signal p1_way_data_upd30_wayE :std_ulogic; +signal congr_cl30_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl30_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu30_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd30_wayF :std_ulogic; +signal p1_way_data_upd30_wayF :std_ulogic; +signal congr_cl30_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl30_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu30_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd30_wayG :std_ulogic; +signal p1_way_data_upd30_wayG :std_ulogic; +signal congr_cl30_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl30_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu30_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd30_wayH :std_ulogic; +signal p1_way_data_upd30_wayH :std_ulogic; +signal p0_congr_cl31_m :std_ulogic; +signal p1_congr_cl31_m :std_ulogic; +signal p0_congr_cl31_act_d :std_ulogic; +signal p0_congr_cl31_act_q :std_ulogic; +signal p1_congr_cl31_act_d :std_ulogic; +signal p1_congr_cl31_act_q :std_ulogic; +signal congr_cl31_act :std_ulogic; +signal congr_cl31_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl31_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu31_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd31_wayA :std_ulogic; +signal p1_way_data_upd31_wayA :std_ulogic; +signal congr_cl31_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl31_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu31_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd31_wayB :std_ulogic; +signal p1_way_data_upd31_wayB :std_ulogic; +signal congr_cl31_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl31_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu31_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd31_wayC :std_ulogic; +signal p1_way_data_upd31_wayC :std_ulogic; +signal congr_cl31_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl31_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu31_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd31_wayD :std_ulogic; +signal p1_way_data_upd31_wayD :std_ulogic; +signal congr_cl31_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl31_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu31_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd31_wayE :std_ulogic; +signal p1_way_data_upd31_wayE :std_ulogic; +signal congr_cl31_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl31_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu31_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd31_wayF :std_ulogic; +signal p1_way_data_upd31_wayF :std_ulogic; +signal congr_cl31_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl31_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu31_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd31_wayG :std_ulogic; +signal p1_way_data_upd31_wayG :std_ulogic; +signal congr_cl31_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl31_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu31_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd31_wayH :std_ulogic; +signal p1_way_data_upd31_wayH :std_ulogic; +signal p0_congr_cl32_m :std_ulogic; +signal p1_congr_cl32_m :std_ulogic; +signal p0_congr_cl32_act_d :std_ulogic; +signal p0_congr_cl32_act_q :std_ulogic; +signal p1_congr_cl32_act_d :std_ulogic; +signal p1_congr_cl32_act_q :std_ulogic; +signal congr_cl32_act :std_ulogic; +signal congr_cl32_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl32_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu32_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd32_wayA :std_ulogic; +signal p1_way_data_upd32_wayA :std_ulogic; +signal congr_cl32_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl32_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu32_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd32_wayB :std_ulogic; +signal p1_way_data_upd32_wayB :std_ulogic; +signal congr_cl32_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl32_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu32_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd32_wayC :std_ulogic; +signal p1_way_data_upd32_wayC :std_ulogic; +signal congr_cl32_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl32_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu32_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd32_wayD :std_ulogic; +signal p1_way_data_upd32_wayD :std_ulogic; +signal congr_cl32_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl32_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu32_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd32_wayE :std_ulogic; +signal p1_way_data_upd32_wayE :std_ulogic; +signal congr_cl32_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl32_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu32_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd32_wayF :std_ulogic; +signal p1_way_data_upd32_wayF :std_ulogic; +signal congr_cl32_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl32_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu32_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd32_wayG :std_ulogic; +signal p1_way_data_upd32_wayG :std_ulogic; +signal congr_cl32_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl32_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu32_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd32_wayH :std_ulogic; +signal p1_way_data_upd32_wayH :std_ulogic; +signal p0_congr_cl33_m :std_ulogic; +signal p1_congr_cl33_m :std_ulogic; +signal p0_congr_cl33_act_d :std_ulogic; +signal p0_congr_cl33_act_q :std_ulogic; +signal p1_congr_cl33_act_d :std_ulogic; +signal p1_congr_cl33_act_q :std_ulogic; +signal congr_cl33_act :std_ulogic; +signal congr_cl33_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl33_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu33_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd33_wayA :std_ulogic; +signal p1_way_data_upd33_wayA :std_ulogic; +signal congr_cl33_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl33_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu33_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd33_wayB :std_ulogic; +signal p1_way_data_upd33_wayB :std_ulogic; +signal congr_cl33_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl33_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu33_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd33_wayC :std_ulogic; +signal p1_way_data_upd33_wayC :std_ulogic; +signal congr_cl33_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl33_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu33_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd33_wayD :std_ulogic; +signal p1_way_data_upd33_wayD :std_ulogic; +signal congr_cl33_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl33_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu33_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd33_wayE :std_ulogic; +signal p1_way_data_upd33_wayE :std_ulogic; +signal congr_cl33_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl33_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu33_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd33_wayF :std_ulogic; +signal p1_way_data_upd33_wayF :std_ulogic; +signal congr_cl33_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl33_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu33_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd33_wayG :std_ulogic; +signal p1_way_data_upd33_wayG :std_ulogic; +signal congr_cl33_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl33_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu33_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd33_wayH :std_ulogic; +signal p1_way_data_upd33_wayH :std_ulogic; +signal p0_congr_cl34_m :std_ulogic; +signal p1_congr_cl34_m :std_ulogic; +signal p0_congr_cl34_act_d :std_ulogic; +signal p0_congr_cl34_act_q :std_ulogic; +signal p1_congr_cl34_act_d :std_ulogic; +signal p1_congr_cl34_act_q :std_ulogic; +signal congr_cl34_act :std_ulogic; +signal congr_cl34_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl34_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu34_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd34_wayA :std_ulogic; +signal p1_way_data_upd34_wayA :std_ulogic; +signal congr_cl34_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl34_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu34_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd34_wayB :std_ulogic; +signal p1_way_data_upd34_wayB :std_ulogic; +signal congr_cl34_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl34_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu34_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd34_wayC :std_ulogic; +signal p1_way_data_upd34_wayC :std_ulogic; +signal congr_cl34_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl34_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu34_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd34_wayD :std_ulogic; +signal p1_way_data_upd34_wayD :std_ulogic; +signal congr_cl34_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl34_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu34_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd34_wayE :std_ulogic; +signal p1_way_data_upd34_wayE :std_ulogic; +signal congr_cl34_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl34_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu34_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd34_wayF :std_ulogic; +signal p1_way_data_upd34_wayF :std_ulogic; +signal congr_cl34_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl34_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu34_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd34_wayG :std_ulogic; +signal p1_way_data_upd34_wayG :std_ulogic; +signal congr_cl34_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl34_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu34_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd34_wayH :std_ulogic; +signal p1_way_data_upd34_wayH :std_ulogic; +signal p0_congr_cl35_m :std_ulogic; +signal p1_congr_cl35_m :std_ulogic; +signal p0_congr_cl35_act_d :std_ulogic; +signal p0_congr_cl35_act_q :std_ulogic; +signal p1_congr_cl35_act_d :std_ulogic; +signal p1_congr_cl35_act_q :std_ulogic; +signal congr_cl35_act :std_ulogic; +signal congr_cl35_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl35_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu35_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd35_wayA :std_ulogic; +signal p1_way_data_upd35_wayA :std_ulogic; +signal congr_cl35_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl35_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu35_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd35_wayB :std_ulogic; +signal p1_way_data_upd35_wayB :std_ulogic; +signal congr_cl35_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl35_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu35_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd35_wayC :std_ulogic; +signal p1_way_data_upd35_wayC :std_ulogic; +signal congr_cl35_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl35_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu35_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd35_wayD :std_ulogic; +signal p1_way_data_upd35_wayD :std_ulogic; +signal congr_cl35_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl35_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu35_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd35_wayE :std_ulogic; +signal p1_way_data_upd35_wayE :std_ulogic; +signal congr_cl35_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl35_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu35_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd35_wayF :std_ulogic; +signal p1_way_data_upd35_wayF :std_ulogic; +signal congr_cl35_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl35_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu35_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd35_wayG :std_ulogic; +signal p1_way_data_upd35_wayG :std_ulogic; +signal congr_cl35_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl35_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu35_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd35_wayH :std_ulogic; +signal p1_way_data_upd35_wayH :std_ulogic; +signal p0_congr_cl36_m :std_ulogic; +signal p1_congr_cl36_m :std_ulogic; +signal p0_congr_cl36_act_d :std_ulogic; +signal p0_congr_cl36_act_q :std_ulogic; +signal p1_congr_cl36_act_d :std_ulogic; +signal p1_congr_cl36_act_q :std_ulogic; +signal congr_cl36_act :std_ulogic; +signal congr_cl36_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl36_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu36_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd36_wayA :std_ulogic; +signal p1_way_data_upd36_wayA :std_ulogic; +signal congr_cl36_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl36_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu36_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd36_wayB :std_ulogic; +signal p1_way_data_upd36_wayB :std_ulogic; +signal congr_cl36_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl36_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu36_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd36_wayC :std_ulogic; +signal p1_way_data_upd36_wayC :std_ulogic; +signal congr_cl36_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl36_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu36_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd36_wayD :std_ulogic; +signal p1_way_data_upd36_wayD :std_ulogic; +signal congr_cl36_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl36_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu36_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd36_wayE :std_ulogic; +signal p1_way_data_upd36_wayE :std_ulogic; +signal congr_cl36_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl36_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu36_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd36_wayF :std_ulogic; +signal p1_way_data_upd36_wayF :std_ulogic; +signal congr_cl36_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl36_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu36_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd36_wayG :std_ulogic; +signal p1_way_data_upd36_wayG :std_ulogic; +signal congr_cl36_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl36_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu36_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd36_wayH :std_ulogic; +signal p1_way_data_upd36_wayH :std_ulogic; +signal p0_congr_cl37_m :std_ulogic; +signal p1_congr_cl37_m :std_ulogic; +signal p0_congr_cl37_act_d :std_ulogic; +signal p0_congr_cl37_act_q :std_ulogic; +signal p1_congr_cl37_act_d :std_ulogic; +signal p1_congr_cl37_act_q :std_ulogic; +signal congr_cl37_act :std_ulogic; +signal congr_cl37_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl37_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu37_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd37_wayA :std_ulogic; +signal p1_way_data_upd37_wayA :std_ulogic; +signal congr_cl37_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl37_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu37_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd37_wayB :std_ulogic; +signal p1_way_data_upd37_wayB :std_ulogic; +signal congr_cl37_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl37_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu37_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd37_wayC :std_ulogic; +signal p1_way_data_upd37_wayC :std_ulogic; +signal congr_cl37_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl37_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu37_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd37_wayD :std_ulogic; +signal p1_way_data_upd37_wayD :std_ulogic; +signal congr_cl37_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl37_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu37_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd37_wayE :std_ulogic; +signal p1_way_data_upd37_wayE :std_ulogic; +signal congr_cl37_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl37_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu37_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd37_wayF :std_ulogic; +signal p1_way_data_upd37_wayF :std_ulogic; +signal congr_cl37_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl37_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu37_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd37_wayG :std_ulogic; +signal p1_way_data_upd37_wayG :std_ulogic; +signal congr_cl37_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl37_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu37_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd37_wayH :std_ulogic; +signal p1_way_data_upd37_wayH :std_ulogic; +signal p0_congr_cl38_m :std_ulogic; +signal p1_congr_cl38_m :std_ulogic; +signal p0_congr_cl38_act_d :std_ulogic; +signal p0_congr_cl38_act_q :std_ulogic; +signal p1_congr_cl38_act_d :std_ulogic; +signal p1_congr_cl38_act_q :std_ulogic; +signal congr_cl38_act :std_ulogic; +signal congr_cl38_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl38_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu38_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd38_wayA :std_ulogic; +signal p1_way_data_upd38_wayA :std_ulogic; +signal congr_cl38_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl38_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu38_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd38_wayB :std_ulogic; +signal p1_way_data_upd38_wayB :std_ulogic; +signal congr_cl38_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl38_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu38_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd38_wayC :std_ulogic; +signal p1_way_data_upd38_wayC :std_ulogic; +signal congr_cl38_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl38_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu38_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd38_wayD :std_ulogic; +signal p1_way_data_upd38_wayD :std_ulogic; +signal congr_cl38_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl38_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu38_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd38_wayE :std_ulogic; +signal p1_way_data_upd38_wayE :std_ulogic; +signal congr_cl38_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl38_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu38_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd38_wayF :std_ulogic; +signal p1_way_data_upd38_wayF :std_ulogic; +signal congr_cl38_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl38_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu38_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd38_wayG :std_ulogic; +signal p1_way_data_upd38_wayG :std_ulogic; +signal congr_cl38_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl38_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu38_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd38_wayH :std_ulogic; +signal p1_way_data_upd38_wayH :std_ulogic; +signal p0_congr_cl39_m :std_ulogic; +signal p1_congr_cl39_m :std_ulogic; +signal p0_congr_cl39_act_d :std_ulogic; +signal p0_congr_cl39_act_q :std_ulogic; +signal p1_congr_cl39_act_d :std_ulogic; +signal p1_congr_cl39_act_q :std_ulogic; +signal congr_cl39_act :std_ulogic; +signal congr_cl39_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl39_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu39_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd39_wayA :std_ulogic; +signal p1_way_data_upd39_wayA :std_ulogic; +signal congr_cl39_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl39_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu39_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd39_wayB :std_ulogic; +signal p1_way_data_upd39_wayB :std_ulogic; +signal congr_cl39_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl39_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu39_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd39_wayC :std_ulogic; +signal p1_way_data_upd39_wayC :std_ulogic; +signal congr_cl39_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl39_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu39_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd39_wayD :std_ulogic; +signal p1_way_data_upd39_wayD :std_ulogic; +signal congr_cl39_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl39_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu39_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd39_wayE :std_ulogic; +signal p1_way_data_upd39_wayE :std_ulogic; +signal congr_cl39_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl39_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu39_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd39_wayF :std_ulogic; +signal p1_way_data_upd39_wayF :std_ulogic; +signal congr_cl39_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl39_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu39_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd39_wayG :std_ulogic; +signal p1_way_data_upd39_wayG :std_ulogic; +signal congr_cl39_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl39_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu39_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd39_wayH :std_ulogic; +signal p1_way_data_upd39_wayH :std_ulogic; +signal p0_congr_cl40_m :std_ulogic; +signal p1_congr_cl40_m :std_ulogic; +signal p0_congr_cl40_act_d :std_ulogic; +signal p0_congr_cl40_act_q :std_ulogic; +signal p1_congr_cl40_act_d :std_ulogic; +signal p1_congr_cl40_act_q :std_ulogic; +signal congr_cl40_act :std_ulogic; +signal congr_cl40_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl40_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu40_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd40_wayA :std_ulogic; +signal p1_way_data_upd40_wayA :std_ulogic; +signal congr_cl40_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl40_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu40_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd40_wayB :std_ulogic; +signal p1_way_data_upd40_wayB :std_ulogic; +signal congr_cl40_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl40_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu40_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd40_wayC :std_ulogic; +signal p1_way_data_upd40_wayC :std_ulogic; +signal congr_cl40_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl40_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu40_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd40_wayD :std_ulogic; +signal p1_way_data_upd40_wayD :std_ulogic; +signal congr_cl40_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl40_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu40_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd40_wayE :std_ulogic; +signal p1_way_data_upd40_wayE :std_ulogic; +signal congr_cl40_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl40_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu40_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd40_wayF :std_ulogic; +signal p1_way_data_upd40_wayF :std_ulogic; +signal congr_cl40_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl40_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu40_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd40_wayG :std_ulogic; +signal p1_way_data_upd40_wayG :std_ulogic; +signal congr_cl40_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl40_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu40_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd40_wayH :std_ulogic; +signal p1_way_data_upd40_wayH :std_ulogic; +signal p0_congr_cl41_m :std_ulogic; +signal p1_congr_cl41_m :std_ulogic; +signal p0_congr_cl41_act_d :std_ulogic; +signal p0_congr_cl41_act_q :std_ulogic; +signal p1_congr_cl41_act_d :std_ulogic; +signal p1_congr_cl41_act_q :std_ulogic; +signal congr_cl41_act :std_ulogic; +signal congr_cl41_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl41_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu41_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd41_wayA :std_ulogic; +signal p1_way_data_upd41_wayA :std_ulogic; +signal congr_cl41_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl41_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu41_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd41_wayB :std_ulogic; +signal p1_way_data_upd41_wayB :std_ulogic; +signal congr_cl41_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl41_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu41_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd41_wayC :std_ulogic; +signal p1_way_data_upd41_wayC :std_ulogic; +signal congr_cl41_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl41_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu41_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd41_wayD :std_ulogic; +signal p1_way_data_upd41_wayD :std_ulogic; +signal congr_cl41_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl41_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu41_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd41_wayE :std_ulogic; +signal p1_way_data_upd41_wayE :std_ulogic; +signal congr_cl41_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl41_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu41_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd41_wayF :std_ulogic; +signal p1_way_data_upd41_wayF :std_ulogic; +signal congr_cl41_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl41_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu41_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd41_wayG :std_ulogic; +signal p1_way_data_upd41_wayG :std_ulogic; +signal congr_cl41_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl41_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu41_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd41_wayH :std_ulogic; +signal p1_way_data_upd41_wayH :std_ulogic; +signal p0_congr_cl42_m :std_ulogic; +signal p1_congr_cl42_m :std_ulogic; +signal p0_congr_cl42_act_d :std_ulogic; +signal p0_congr_cl42_act_q :std_ulogic; +signal p1_congr_cl42_act_d :std_ulogic; +signal p1_congr_cl42_act_q :std_ulogic; +signal congr_cl42_act :std_ulogic; +signal congr_cl42_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl42_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu42_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd42_wayA :std_ulogic; +signal p1_way_data_upd42_wayA :std_ulogic; +signal congr_cl42_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl42_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu42_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd42_wayB :std_ulogic; +signal p1_way_data_upd42_wayB :std_ulogic; +signal congr_cl42_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl42_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu42_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd42_wayC :std_ulogic; +signal p1_way_data_upd42_wayC :std_ulogic; +signal congr_cl42_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl42_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu42_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd42_wayD :std_ulogic; +signal p1_way_data_upd42_wayD :std_ulogic; +signal congr_cl42_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl42_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu42_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd42_wayE :std_ulogic; +signal p1_way_data_upd42_wayE :std_ulogic; +signal congr_cl42_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl42_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu42_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd42_wayF :std_ulogic; +signal p1_way_data_upd42_wayF :std_ulogic; +signal congr_cl42_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl42_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu42_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd42_wayG :std_ulogic; +signal p1_way_data_upd42_wayG :std_ulogic; +signal congr_cl42_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl42_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu42_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd42_wayH :std_ulogic; +signal p1_way_data_upd42_wayH :std_ulogic; +signal p0_congr_cl43_m :std_ulogic; +signal p1_congr_cl43_m :std_ulogic; +signal p0_congr_cl43_act_d :std_ulogic; +signal p0_congr_cl43_act_q :std_ulogic; +signal p1_congr_cl43_act_d :std_ulogic; +signal p1_congr_cl43_act_q :std_ulogic; +signal congr_cl43_act :std_ulogic; +signal congr_cl43_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl43_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu43_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd43_wayA :std_ulogic; +signal p1_way_data_upd43_wayA :std_ulogic; +signal congr_cl43_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl43_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu43_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd43_wayB :std_ulogic; +signal p1_way_data_upd43_wayB :std_ulogic; +signal congr_cl43_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl43_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu43_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd43_wayC :std_ulogic; +signal p1_way_data_upd43_wayC :std_ulogic; +signal congr_cl43_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl43_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu43_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd43_wayD :std_ulogic; +signal p1_way_data_upd43_wayD :std_ulogic; +signal congr_cl43_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl43_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu43_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd43_wayE :std_ulogic; +signal p1_way_data_upd43_wayE :std_ulogic; +signal congr_cl43_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl43_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu43_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd43_wayF :std_ulogic; +signal p1_way_data_upd43_wayF :std_ulogic; +signal congr_cl43_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl43_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu43_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd43_wayG :std_ulogic; +signal p1_way_data_upd43_wayG :std_ulogic; +signal congr_cl43_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl43_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu43_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd43_wayH :std_ulogic; +signal p1_way_data_upd43_wayH :std_ulogic; +signal p0_congr_cl44_m :std_ulogic; +signal p1_congr_cl44_m :std_ulogic; +signal p0_congr_cl44_act_d :std_ulogic; +signal p0_congr_cl44_act_q :std_ulogic; +signal p1_congr_cl44_act_d :std_ulogic; +signal p1_congr_cl44_act_q :std_ulogic; +signal congr_cl44_act :std_ulogic; +signal congr_cl44_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl44_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu44_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd44_wayA :std_ulogic; +signal p1_way_data_upd44_wayA :std_ulogic; +signal congr_cl44_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl44_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu44_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd44_wayB :std_ulogic; +signal p1_way_data_upd44_wayB :std_ulogic; +signal congr_cl44_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl44_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu44_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd44_wayC :std_ulogic; +signal p1_way_data_upd44_wayC :std_ulogic; +signal congr_cl44_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl44_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu44_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd44_wayD :std_ulogic; +signal p1_way_data_upd44_wayD :std_ulogic; +signal congr_cl44_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl44_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu44_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd44_wayE :std_ulogic; +signal p1_way_data_upd44_wayE :std_ulogic; +signal congr_cl44_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl44_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu44_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd44_wayF :std_ulogic; +signal p1_way_data_upd44_wayF :std_ulogic; +signal congr_cl44_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl44_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu44_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd44_wayG :std_ulogic; +signal p1_way_data_upd44_wayG :std_ulogic; +signal congr_cl44_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl44_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu44_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd44_wayH :std_ulogic; +signal p1_way_data_upd44_wayH :std_ulogic; +signal p0_congr_cl45_m :std_ulogic; +signal p1_congr_cl45_m :std_ulogic; +signal p0_congr_cl45_act_d :std_ulogic; +signal p0_congr_cl45_act_q :std_ulogic; +signal p1_congr_cl45_act_d :std_ulogic; +signal p1_congr_cl45_act_q :std_ulogic; +signal congr_cl45_act :std_ulogic; +signal congr_cl45_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl45_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu45_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd45_wayA :std_ulogic; +signal p1_way_data_upd45_wayA :std_ulogic; +signal congr_cl45_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl45_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu45_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd45_wayB :std_ulogic; +signal p1_way_data_upd45_wayB :std_ulogic; +signal congr_cl45_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl45_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu45_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd45_wayC :std_ulogic; +signal p1_way_data_upd45_wayC :std_ulogic; +signal congr_cl45_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl45_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu45_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd45_wayD :std_ulogic; +signal p1_way_data_upd45_wayD :std_ulogic; +signal congr_cl45_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl45_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu45_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd45_wayE :std_ulogic; +signal p1_way_data_upd45_wayE :std_ulogic; +signal congr_cl45_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl45_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu45_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd45_wayF :std_ulogic; +signal p1_way_data_upd45_wayF :std_ulogic; +signal congr_cl45_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl45_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu45_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd45_wayG :std_ulogic; +signal p1_way_data_upd45_wayG :std_ulogic; +signal congr_cl45_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl45_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu45_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd45_wayH :std_ulogic; +signal p1_way_data_upd45_wayH :std_ulogic; +signal p0_congr_cl46_m :std_ulogic; +signal p1_congr_cl46_m :std_ulogic; +signal p0_congr_cl46_act_d :std_ulogic; +signal p0_congr_cl46_act_q :std_ulogic; +signal p1_congr_cl46_act_d :std_ulogic; +signal p1_congr_cl46_act_q :std_ulogic; +signal congr_cl46_act :std_ulogic; +signal congr_cl46_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl46_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu46_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd46_wayA :std_ulogic; +signal p1_way_data_upd46_wayA :std_ulogic; +signal congr_cl46_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl46_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu46_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd46_wayB :std_ulogic; +signal p1_way_data_upd46_wayB :std_ulogic; +signal congr_cl46_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl46_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu46_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd46_wayC :std_ulogic; +signal p1_way_data_upd46_wayC :std_ulogic; +signal congr_cl46_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl46_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu46_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd46_wayD :std_ulogic; +signal p1_way_data_upd46_wayD :std_ulogic; +signal congr_cl46_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl46_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu46_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd46_wayE :std_ulogic; +signal p1_way_data_upd46_wayE :std_ulogic; +signal congr_cl46_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl46_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu46_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd46_wayF :std_ulogic; +signal p1_way_data_upd46_wayF :std_ulogic; +signal congr_cl46_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl46_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu46_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd46_wayG :std_ulogic; +signal p1_way_data_upd46_wayG :std_ulogic; +signal congr_cl46_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl46_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu46_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd46_wayH :std_ulogic; +signal p1_way_data_upd46_wayH :std_ulogic; +signal p0_congr_cl47_m :std_ulogic; +signal p1_congr_cl47_m :std_ulogic; +signal p0_congr_cl47_act_d :std_ulogic; +signal p0_congr_cl47_act_q :std_ulogic; +signal p1_congr_cl47_act_d :std_ulogic; +signal p1_congr_cl47_act_q :std_ulogic; +signal congr_cl47_act :std_ulogic; +signal congr_cl47_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl47_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu47_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd47_wayA :std_ulogic; +signal p1_way_data_upd47_wayA :std_ulogic; +signal congr_cl47_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl47_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu47_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd47_wayB :std_ulogic; +signal p1_way_data_upd47_wayB :std_ulogic; +signal congr_cl47_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl47_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu47_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd47_wayC :std_ulogic; +signal p1_way_data_upd47_wayC :std_ulogic; +signal congr_cl47_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl47_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu47_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd47_wayD :std_ulogic; +signal p1_way_data_upd47_wayD :std_ulogic; +signal congr_cl47_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl47_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu47_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd47_wayE :std_ulogic; +signal p1_way_data_upd47_wayE :std_ulogic; +signal congr_cl47_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl47_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu47_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd47_wayF :std_ulogic; +signal p1_way_data_upd47_wayF :std_ulogic; +signal congr_cl47_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl47_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu47_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd47_wayG :std_ulogic; +signal p1_way_data_upd47_wayG :std_ulogic; +signal congr_cl47_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl47_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu47_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd47_wayH :std_ulogic; +signal p1_way_data_upd47_wayH :std_ulogic; +signal p0_congr_cl48_m :std_ulogic; +signal p1_congr_cl48_m :std_ulogic; +signal p0_congr_cl48_act_d :std_ulogic; +signal p0_congr_cl48_act_q :std_ulogic; +signal p1_congr_cl48_act_d :std_ulogic; +signal p1_congr_cl48_act_q :std_ulogic; +signal congr_cl48_act :std_ulogic; +signal congr_cl48_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl48_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu48_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd48_wayA :std_ulogic; +signal p1_way_data_upd48_wayA :std_ulogic; +signal congr_cl48_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl48_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu48_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd48_wayB :std_ulogic; +signal p1_way_data_upd48_wayB :std_ulogic; +signal congr_cl48_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl48_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu48_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd48_wayC :std_ulogic; +signal p1_way_data_upd48_wayC :std_ulogic; +signal congr_cl48_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl48_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu48_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd48_wayD :std_ulogic; +signal p1_way_data_upd48_wayD :std_ulogic; +signal congr_cl48_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl48_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu48_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd48_wayE :std_ulogic; +signal p1_way_data_upd48_wayE :std_ulogic; +signal congr_cl48_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl48_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu48_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd48_wayF :std_ulogic; +signal p1_way_data_upd48_wayF :std_ulogic; +signal congr_cl48_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl48_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu48_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd48_wayG :std_ulogic; +signal p1_way_data_upd48_wayG :std_ulogic; +signal congr_cl48_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl48_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu48_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd48_wayH :std_ulogic; +signal p1_way_data_upd48_wayH :std_ulogic; +signal p0_congr_cl49_m :std_ulogic; +signal p1_congr_cl49_m :std_ulogic; +signal p0_congr_cl49_act_d :std_ulogic; +signal p0_congr_cl49_act_q :std_ulogic; +signal p1_congr_cl49_act_d :std_ulogic; +signal p1_congr_cl49_act_q :std_ulogic; +signal congr_cl49_act :std_ulogic; +signal congr_cl49_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl49_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu49_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd49_wayA :std_ulogic; +signal p1_way_data_upd49_wayA :std_ulogic; +signal congr_cl49_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl49_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu49_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd49_wayB :std_ulogic; +signal p1_way_data_upd49_wayB :std_ulogic; +signal congr_cl49_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl49_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu49_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd49_wayC :std_ulogic; +signal p1_way_data_upd49_wayC :std_ulogic; +signal congr_cl49_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl49_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu49_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd49_wayD :std_ulogic; +signal p1_way_data_upd49_wayD :std_ulogic; +signal congr_cl49_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl49_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu49_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd49_wayE :std_ulogic; +signal p1_way_data_upd49_wayE :std_ulogic; +signal congr_cl49_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl49_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu49_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd49_wayF :std_ulogic; +signal p1_way_data_upd49_wayF :std_ulogic; +signal congr_cl49_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl49_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu49_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd49_wayG :std_ulogic; +signal p1_way_data_upd49_wayG :std_ulogic; +signal congr_cl49_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl49_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu49_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd49_wayH :std_ulogic; +signal p1_way_data_upd49_wayH :std_ulogic; +signal p0_congr_cl50_m :std_ulogic; +signal p1_congr_cl50_m :std_ulogic; +signal p0_congr_cl50_act_d :std_ulogic; +signal p0_congr_cl50_act_q :std_ulogic; +signal p1_congr_cl50_act_d :std_ulogic; +signal p1_congr_cl50_act_q :std_ulogic; +signal congr_cl50_act :std_ulogic; +signal congr_cl50_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl50_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu50_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd50_wayA :std_ulogic; +signal p1_way_data_upd50_wayA :std_ulogic; +signal congr_cl50_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl50_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu50_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd50_wayB :std_ulogic; +signal p1_way_data_upd50_wayB :std_ulogic; +signal congr_cl50_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl50_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu50_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd50_wayC :std_ulogic; +signal p1_way_data_upd50_wayC :std_ulogic; +signal congr_cl50_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl50_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu50_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd50_wayD :std_ulogic; +signal p1_way_data_upd50_wayD :std_ulogic; +signal congr_cl50_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl50_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu50_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd50_wayE :std_ulogic; +signal p1_way_data_upd50_wayE :std_ulogic; +signal congr_cl50_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl50_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu50_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd50_wayF :std_ulogic; +signal p1_way_data_upd50_wayF :std_ulogic; +signal congr_cl50_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl50_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu50_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd50_wayG :std_ulogic; +signal p1_way_data_upd50_wayG :std_ulogic; +signal congr_cl50_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl50_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu50_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd50_wayH :std_ulogic; +signal p1_way_data_upd50_wayH :std_ulogic; +signal p0_congr_cl51_m :std_ulogic; +signal p1_congr_cl51_m :std_ulogic; +signal p0_congr_cl51_act_d :std_ulogic; +signal p0_congr_cl51_act_q :std_ulogic; +signal p1_congr_cl51_act_d :std_ulogic; +signal p1_congr_cl51_act_q :std_ulogic; +signal congr_cl51_act :std_ulogic; +signal congr_cl51_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl51_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu51_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd51_wayA :std_ulogic; +signal p1_way_data_upd51_wayA :std_ulogic; +signal congr_cl51_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl51_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu51_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd51_wayB :std_ulogic; +signal p1_way_data_upd51_wayB :std_ulogic; +signal congr_cl51_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl51_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu51_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd51_wayC :std_ulogic; +signal p1_way_data_upd51_wayC :std_ulogic; +signal congr_cl51_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl51_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu51_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd51_wayD :std_ulogic; +signal p1_way_data_upd51_wayD :std_ulogic; +signal congr_cl51_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl51_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu51_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd51_wayE :std_ulogic; +signal p1_way_data_upd51_wayE :std_ulogic; +signal congr_cl51_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl51_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu51_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd51_wayF :std_ulogic; +signal p1_way_data_upd51_wayF :std_ulogic; +signal congr_cl51_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl51_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu51_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd51_wayG :std_ulogic; +signal p1_way_data_upd51_wayG :std_ulogic; +signal congr_cl51_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl51_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu51_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd51_wayH :std_ulogic; +signal p1_way_data_upd51_wayH :std_ulogic; +signal p0_congr_cl52_m :std_ulogic; +signal p1_congr_cl52_m :std_ulogic; +signal p0_congr_cl52_act_d :std_ulogic; +signal p0_congr_cl52_act_q :std_ulogic; +signal p1_congr_cl52_act_d :std_ulogic; +signal p1_congr_cl52_act_q :std_ulogic; +signal congr_cl52_act :std_ulogic; +signal congr_cl52_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl52_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu52_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd52_wayA :std_ulogic; +signal p1_way_data_upd52_wayA :std_ulogic; +signal congr_cl52_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl52_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu52_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd52_wayB :std_ulogic; +signal p1_way_data_upd52_wayB :std_ulogic; +signal congr_cl52_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl52_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu52_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd52_wayC :std_ulogic; +signal p1_way_data_upd52_wayC :std_ulogic; +signal congr_cl52_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl52_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu52_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd52_wayD :std_ulogic; +signal p1_way_data_upd52_wayD :std_ulogic; +signal congr_cl52_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl52_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu52_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd52_wayE :std_ulogic; +signal p1_way_data_upd52_wayE :std_ulogic; +signal congr_cl52_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl52_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu52_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd52_wayF :std_ulogic; +signal p1_way_data_upd52_wayF :std_ulogic; +signal congr_cl52_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl52_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu52_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd52_wayG :std_ulogic; +signal p1_way_data_upd52_wayG :std_ulogic; +signal congr_cl52_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl52_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu52_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd52_wayH :std_ulogic; +signal p1_way_data_upd52_wayH :std_ulogic; +signal p0_congr_cl53_m :std_ulogic; +signal p1_congr_cl53_m :std_ulogic; +signal p0_congr_cl53_act_d :std_ulogic; +signal p0_congr_cl53_act_q :std_ulogic; +signal p1_congr_cl53_act_d :std_ulogic; +signal p1_congr_cl53_act_q :std_ulogic; +signal congr_cl53_act :std_ulogic; +signal congr_cl53_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl53_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu53_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd53_wayA :std_ulogic; +signal p1_way_data_upd53_wayA :std_ulogic; +signal congr_cl53_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl53_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu53_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd53_wayB :std_ulogic; +signal p1_way_data_upd53_wayB :std_ulogic; +signal congr_cl53_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl53_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu53_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd53_wayC :std_ulogic; +signal p1_way_data_upd53_wayC :std_ulogic; +signal congr_cl53_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl53_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu53_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd53_wayD :std_ulogic; +signal p1_way_data_upd53_wayD :std_ulogic; +signal congr_cl53_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl53_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu53_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd53_wayE :std_ulogic; +signal p1_way_data_upd53_wayE :std_ulogic; +signal congr_cl53_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl53_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu53_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd53_wayF :std_ulogic; +signal p1_way_data_upd53_wayF :std_ulogic; +signal congr_cl53_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl53_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu53_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd53_wayG :std_ulogic; +signal p1_way_data_upd53_wayG :std_ulogic; +signal congr_cl53_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl53_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu53_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd53_wayH :std_ulogic; +signal p1_way_data_upd53_wayH :std_ulogic; +signal p0_congr_cl54_m :std_ulogic; +signal p1_congr_cl54_m :std_ulogic; +signal p0_congr_cl54_act_d :std_ulogic; +signal p0_congr_cl54_act_q :std_ulogic; +signal p1_congr_cl54_act_d :std_ulogic; +signal p1_congr_cl54_act_q :std_ulogic; +signal congr_cl54_act :std_ulogic; +signal congr_cl54_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl54_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu54_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd54_wayA :std_ulogic; +signal p1_way_data_upd54_wayA :std_ulogic; +signal congr_cl54_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl54_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu54_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd54_wayB :std_ulogic; +signal p1_way_data_upd54_wayB :std_ulogic; +signal congr_cl54_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl54_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu54_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd54_wayC :std_ulogic; +signal p1_way_data_upd54_wayC :std_ulogic; +signal congr_cl54_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl54_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu54_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd54_wayD :std_ulogic; +signal p1_way_data_upd54_wayD :std_ulogic; +signal congr_cl54_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl54_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu54_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd54_wayE :std_ulogic; +signal p1_way_data_upd54_wayE :std_ulogic; +signal congr_cl54_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl54_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu54_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd54_wayF :std_ulogic; +signal p1_way_data_upd54_wayF :std_ulogic; +signal congr_cl54_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl54_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu54_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd54_wayG :std_ulogic; +signal p1_way_data_upd54_wayG :std_ulogic; +signal congr_cl54_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl54_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu54_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd54_wayH :std_ulogic; +signal p1_way_data_upd54_wayH :std_ulogic; +signal p0_congr_cl55_m :std_ulogic; +signal p1_congr_cl55_m :std_ulogic; +signal p0_congr_cl55_act_d :std_ulogic; +signal p0_congr_cl55_act_q :std_ulogic; +signal p1_congr_cl55_act_d :std_ulogic; +signal p1_congr_cl55_act_q :std_ulogic; +signal congr_cl55_act :std_ulogic; +signal congr_cl55_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl55_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu55_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd55_wayA :std_ulogic; +signal p1_way_data_upd55_wayA :std_ulogic; +signal congr_cl55_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl55_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu55_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd55_wayB :std_ulogic; +signal p1_way_data_upd55_wayB :std_ulogic; +signal congr_cl55_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl55_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu55_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd55_wayC :std_ulogic; +signal p1_way_data_upd55_wayC :std_ulogic; +signal congr_cl55_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl55_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu55_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd55_wayD :std_ulogic; +signal p1_way_data_upd55_wayD :std_ulogic; +signal congr_cl55_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl55_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu55_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd55_wayE :std_ulogic; +signal p1_way_data_upd55_wayE :std_ulogic; +signal congr_cl55_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl55_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu55_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd55_wayF :std_ulogic; +signal p1_way_data_upd55_wayF :std_ulogic; +signal congr_cl55_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl55_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu55_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd55_wayG :std_ulogic; +signal p1_way_data_upd55_wayG :std_ulogic; +signal congr_cl55_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl55_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu55_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd55_wayH :std_ulogic; +signal p1_way_data_upd55_wayH :std_ulogic; +signal p0_congr_cl56_m :std_ulogic; +signal p1_congr_cl56_m :std_ulogic; +signal p0_congr_cl56_act_d :std_ulogic; +signal p0_congr_cl56_act_q :std_ulogic; +signal p1_congr_cl56_act_d :std_ulogic; +signal p1_congr_cl56_act_q :std_ulogic; +signal congr_cl56_act :std_ulogic; +signal congr_cl56_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl56_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu56_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd56_wayA :std_ulogic; +signal p1_way_data_upd56_wayA :std_ulogic; +signal congr_cl56_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl56_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu56_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd56_wayB :std_ulogic; +signal p1_way_data_upd56_wayB :std_ulogic; +signal congr_cl56_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl56_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu56_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd56_wayC :std_ulogic; +signal p1_way_data_upd56_wayC :std_ulogic; +signal congr_cl56_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl56_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu56_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd56_wayD :std_ulogic; +signal p1_way_data_upd56_wayD :std_ulogic; +signal congr_cl56_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl56_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu56_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd56_wayE :std_ulogic; +signal p1_way_data_upd56_wayE :std_ulogic; +signal congr_cl56_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl56_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu56_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd56_wayF :std_ulogic; +signal p1_way_data_upd56_wayF :std_ulogic; +signal congr_cl56_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl56_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu56_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd56_wayG :std_ulogic; +signal p1_way_data_upd56_wayG :std_ulogic; +signal congr_cl56_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl56_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu56_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd56_wayH :std_ulogic; +signal p1_way_data_upd56_wayH :std_ulogic; +signal p0_congr_cl57_m :std_ulogic; +signal p1_congr_cl57_m :std_ulogic; +signal p0_congr_cl57_act_d :std_ulogic; +signal p0_congr_cl57_act_q :std_ulogic; +signal p1_congr_cl57_act_d :std_ulogic; +signal p1_congr_cl57_act_q :std_ulogic; +signal congr_cl57_act :std_ulogic; +signal congr_cl57_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl57_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu57_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd57_wayA :std_ulogic; +signal p1_way_data_upd57_wayA :std_ulogic; +signal congr_cl57_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl57_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu57_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd57_wayB :std_ulogic; +signal p1_way_data_upd57_wayB :std_ulogic; +signal congr_cl57_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl57_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu57_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd57_wayC :std_ulogic; +signal p1_way_data_upd57_wayC :std_ulogic; +signal congr_cl57_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl57_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu57_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd57_wayD :std_ulogic; +signal p1_way_data_upd57_wayD :std_ulogic; +signal congr_cl57_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl57_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu57_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd57_wayE :std_ulogic; +signal p1_way_data_upd57_wayE :std_ulogic; +signal congr_cl57_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl57_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu57_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd57_wayF :std_ulogic; +signal p1_way_data_upd57_wayF :std_ulogic; +signal congr_cl57_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl57_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu57_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd57_wayG :std_ulogic; +signal p1_way_data_upd57_wayG :std_ulogic; +signal congr_cl57_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl57_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu57_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd57_wayH :std_ulogic; +signal p1_way_data_upd57_wayH :std_ulogic; +signal p0_congr_cl58_m :std_ulogic; +signal p1_congr_cl58_m :std_ulogic; +signal p0_congr_cl58_act_d :std_ulogic; +signal p0_congr_cl58_act_q :std_ulogic; +signal p1_congr_cl58_act_d :std_ulogic; +signal p1_congr_cl58_act_q :std_ulogic; +signal congr_cl58_act :std_ulogic; +signal congr_cl58_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl58_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu58_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd58_wayA :std_ulogic; +signal p1_way_data_upd58_wayA :std_ulogic; +signal congr_cl58_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl58_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu58_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd58_wayB :std_ulogic; +signal p1_way_data_upd58_wayB :std_ulogic; +signal congr_cl58_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl58_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu58_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd58_wayC :std_ulogic; +signal p1_way_data_upd58_wayC :std_ulogic; +signal congr_cl58_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl58_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu58_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd58_wayD :std_ulogic; +signal p1_way_data_upd58_wayD :std_ulogic; +signal congr_cl58_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl58_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu58_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd58_wayE :std_ulogic; +signal p1_way_data_upd58_wayE :std_ulogic; +signal congr_cl58_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl58_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu58_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd58_wayF :std_ulogic; +signal p1_way_data_upd58_wayF :std_ulogic; +signal congr_cl58_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl58_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu58_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd58_wayG :std_ulogic; +signal p1_way_data_upd58_wayG :std_ulogic; +signal congr_cl58_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl58_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu58_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd58_wayH :std_ulogic; +signal p1_way_data_upd58_wayH :std_ulogic; +signal p0_congr_cl59_m :std_ulogic; +signal p1_congr_cl59_m :std_ulogic; +signal p0_congr_cl59_act_d :std_ulogic; +signal p0_congr_cl59_act_q :std_ulogic; +signal p1_congr_cl59_act_d :std_ulogic; +signal p1_congr_cl59_act_q :std_ulogic; +signal congr_cl59_act :std_ulogic; +signal congr_cl59_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl59_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu59_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd59_wayA :std_ulogic; +signal p1_way_data_upd59_wayA :std_ulogic; +signal congr_cl59_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl59_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu59_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd59_wayB :std_ulogic; +signal p1_way_data_upd59_wayB :std_ulogic; +signal congr_cl59_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl59_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu59_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd59_wayC :std_ulogic; +signal p1_way_data_upd59_wayC :std_ulogic; +signal congr_cl59_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl59_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu59_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd59_wayD :std_ulogic; +signal p1_way_data_upd59_wayD :std_ulogic; +signal congr_cl59_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl59_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu59_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd59_wayE :std_ulogic; +signal p1_way_data_upd59_wayE :std_ulogic; +signal congr_cl59_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl59_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu59_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd59_wayF :std_ulogic; +signal p1_way_data_upd59_wayF :std_ulogic; +signal congr_cl59_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl59_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu59_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd59_wayG :std_ulogic; +signal p1_way_data_upd59_wayG :std_ulogic; +signal congr_cl59_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl59_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu59_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd59_wayH :std_ulogic; +signal p1_way_data_upd59_wayH :std_ulogic; +signal p0_congr_cl60_m :std_ulogic; +signal p1_congr_cl60_m :std_ulogic; +signal p0_congr_cl60_act_d :std_ulogic; +signal p0_congr_cl60_act_q :std_ulogic; +signal p1_congr_cl60_act_d :std_ulogic; +signal p1_congr_cl60_act_q :std_ulogic; +signal congr_cl60_act :std_ulogic; +signal congr_cl60_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl60_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu60_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd60_wayA :std_ulogic; +signal p1_way_data_upd60_wayA :std_ulogic; +signal congr_cl60_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl60_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu60_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd60_wayB :std_ulogic; +signal p1_way_data_upd60_wayB :std_ulogic; +signal congr_cl60_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl60_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu60_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd60_wayC :std_ulogic; +signal p1_way_data_upd60_wayC :std_ulogic; +signal congr_cl60_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl60_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu60_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd60_wayD :std_ulogic; +signal p1_way_data_upd60_wayD :std_ulogic; +signal congr_cl60_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl60_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu60_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd60_wayE :std_ulogic; +signal p1_way_data_upd60_wayE :std_ulogic; +signal congr_cl60_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl60_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu60_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd60_wayF :std_ulogic; +signal p1_way_data_upd60_wayF :std_ulogic; +signal congr_cl60_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl60_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu60_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd60_wayG :std_ulogic; +signal p1_way_data_upd60_wayG :std_ulogic; +signal congr_cl60_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl60_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu60_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd60_wayH :std_ulogic; +signal p1_way_data_upd60_wayH :std_ulogic; +signal p0_congr_cl61_m :std_ulogic; +signal p1_congr_cl61_m :std_ulogic; +signal p0_congr_cl61_act_d :std_ulogic; +signal p0_congr_cl61_act_q :std_ulogic; +signal p1_congr_cl61_act_d :std_ulogic; +signal p1_congr_cl61_act_q :std_ulogic; +signal congr_cl61_act :std_ulogic; +signal congr_cl61_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl61_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu61_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd61_wayA :std_ulogic; +signal p1_way_data_upd61_wayA :std_ulogic; +signal congr_cl61_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl61_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu61_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd61_wayB :std_ulogic; +signal p1_way_data_upd61_wayB :std_ulogic; +signal congr_cl61_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl61_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu61_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd61_wayC :std_ulogic; +signal p1_way_data_upd61_wayC :std_ulogic; +signal congr_cl61_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl61_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu61_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd61_wayD :std_ulogic; +signal p1_way_data_upd61_wayD :std_ulogic; +signal congr_cl61_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl61_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu61_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd61_wayE :std_ulogic; +signal p1_way_data_upd61_wayE :std_ulogic; +signal congr_cl61_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl61_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu61_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd61_wayF :std_ulogic; +signal p1_way_data_upd61_wayF :std_ulogic; +signal congr_cl61_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl61_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu61_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd61_wayG :std_ulogic; +signal p1_way_data_upd61_wayG :std_ulogic; +signal congr_cl61_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl61_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu61_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd61_wayH :std_ulogic; +signal p1_way_data_upd61_wayH :std_ulogic; +signal p0_congr_cl62_m :std_ulogic; +signal p1_congr_cl62_m :std_ulogic; +signal p0_congr_cl62_act_d :std_ulogic; +signal p0_congr_cl62_act_q :std_ulogic; +signal p1_congr_cl62_act_d :std_ulogic; +signal p1_congr_cl62_act_q :std_ulogic; +signal congr_cl62_act :std_ulogic; +signal congr_cl62_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl62_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu62_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd62_wayA :std_ulogic; +signal p1_way_data_upd62_wayA :std_ulogic; +signal congr_cl62_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl62_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu62_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd62_wayB :std_ulogic; +signal p1_way_data_upd62_wayB :std_ulogic; +signal congr_cl62_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl62_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu62_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd62_wayC :std_ulogic; +signal p1_way_data_upd62_wayC :std_ulogic; +signal congr_cl62_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl62_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu62_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd62_wayD :std_ulogic; +signal p1_way_data_upd62_wayD :std_ulogic; +signal congr_cl62_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl62_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu62_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd62_wayE :std_ulogic; +signal p1_way_data_upd62_wayE :std_ulogic; +signal congr_cl62_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl62_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu62_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd62_wayF :std_ulogic; +signal p1_way_data_upd62_wayF :std_ulogic; +signal congr_cl62_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl62_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu62_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd62_wayG :std_ulogic; +signal p1_way_data_upd62_wayG :std_ulogic; +signal congr_cl62_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl62_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu62_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd62_wayH :std_ulogic; +signal p1_way_data_upd62_wayH :std_ulogic; +signal p0_congr_cl63_m :std_ulogic; +signal p1_congr_cl63_m :std_ulogic; +signal p0_congr_cl63_act_d :std_ulogic; +signal p0_congr_cl63_act_q :std_ulogic; +signal p1_congr_cl63_act_d :std_ulogic; +signal p1_congr_cl63_act_q :std_ulogic; +signal congr_cl63_act :std_ulogic; +signal congr_cl63_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl63_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu63_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd63_wayA :std_ulogic; +signal p1_way_data_upd63_wayA :std_ulogic; +signal congr_cl63_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl63_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu63_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd63_wayB :std_ulogic; +signal p1_way_data_upd63_wayB :std_ulogic; +signal congr_cl63_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl63_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu63_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd63_wayC :std_ulogic; +signal p1_way_data_upd63_wayC :std_ulogic; +signal congr_cl63_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl63_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu63_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd63_wayD :std_ulogic; +signal p1_way_data_upd63_wayD :std_ulogic; +signal congr_cl63_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl63_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu63_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd63_wayE :std_ulogic; +signal p1_way_data_upd63_wayE :std_ulogic; +signal congr_cl63_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl63_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu63_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd63_wayF :std_ulogic; +signal p1_way_data_upd63_wayF :std_ulogic; +signal congr_cl63_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl63_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu63_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd63_wayG :std_ulogic; +signal p1_way_data_upd63_wayG :std_ulogic; +signal congr_cl63_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl63_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu63_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd63_wayH :std_ulogic; +signal p1_way_data_upd63_wayH :std_ulogic; +signal tagA_hit :std_ulogic; +signal tagA_hit_b :std_ulogic; +signal arr_wayA_val :std_ulogic_vector(0 to 5); +signal p0_arr_wayA_rd :std_ulogic_vector(0 to 5); +signal flush_wayA_d :std_ulogic_vector(0 to 5); +signal flush_wayA_q :std_ulogic_vector(0 to 5); +signal rel_wayA_clr :std_ulogic; +signal rel_wayA_set :std_ulogic; +signal rel_par_wA_clr :std_ulogic; +signal wayA_val :std_ulogic_vector(0 to 5); +signal wayA_val_b_q :std_ulogic_vector(0 to 5); +signal wayA_val_b1 :std_ulogic; +signal congr_cl_ex2_wayA_byp :std_ulogic_vector(1 to 7); +signal congr_cl_ex2_wayA_sel :std_ulogic_vector(2 to 7); +signal rel_arr_wayA_val :std_ulogic_vector(0 to 5); +signal p1_arr_wayA_rd :std_ulogic_vector(0 to 5); +signal rel_wayA_val_b_q :std_ulogic_vector(0 to 5); +signal rel_wayA_val :std_ulogic_vector(0 to 5); +signal congr_cl_rel13_wayA_byp :std_ulogic_vector(1 to 7); +signal congr_cl_rel13_wayA_sel :std_ulogic_vector(2 to 7); +signal reload_wayA_d :std_ulogic_vector(0 to 5); +signal reload_wayA_q :std_ulogic_vector(0 to 5); +signal reload_wayA_data_d :std_ulogic_vector(0 to 5); +signal reload_wayA_data_q :std_ulogic_vector(0 to 5); +signal reload_wayA_data2_d :std_ulogic_vector(0 to 5); +signal reload_wayA_data2_q :std_ulogic_vector(0 to 5); +signal reload_wayA_upd_d :std_ulogic; +signal reload_wayA_upd_q :std_ulogic; +signal reload_wayA_clr :std_ulogic; +signal reload_wayA_upd2_d :std_ulogic; +signal reload_wayA_upd2_q :std_ulogic; +signal reload_wayA_upd3_d :std_ulogic; +signal reload_wayA_upd3_q :std_ulogic; +signal reload_wayA :std_ulogic_vector(0 to 5); +signal binv_wayA_upd_d :std_ulogic; +signal binv_wayA_upd_q :std_ulogic; +signal binv_wayA_upd1 :std_ulogic; +signal binv_wayA_upd2_d :std_ulogic; +signal binv_wayA_upd2_q :std_ulogic; +signal binv_wayA_upd3_d :std_ulogic; +signal binv_wayA_upd3_q :std_ulogic; +signal flush_wayA_data1 :std_ulogic_vector(0 to 5); +signal flush_wayA_data_d :std_ulogic_vector(0 to 5); +signal flush_wayA_data_q :std_ulogic_vector(0 to 5); +signal flush_wayA_data2_d :std_ulogic_vector(0 to 5); +signal flush_wayA_data2_q :std_ulogic_vector(0 to 5); +signal xu_op_hit_wayA_b :std_ulogic; +signal xu_op_hit_wayA :std_ulogic; +signal xu_op_hit_wayA_dly_b :std_ulogic; +signal clr_val_wayA :std_ulogic; +signal upd_lck_wayA :std_ulogic_vector(0 to 1); +signal inval_clr_lck_wA_d :std_ulogic; +signal inval_clr_lck_wA_q :std_ulogic; +signal perr_way_det_wayA :std_ulogic; +signal perr_wayA_watch_lost :std_ulogic_vector(0 to 3); +signal wayA_watch_value :std_ulogic; +signal ex4_lost_wayA :std_ulogic_vector(0 to 3); +signal ex3_xuop_lost_watch_wayA :std_ulogic; +signal ex3_xuop_wayA_upd :std_ulogic; +signal ex4_xuop_wayA_upd_d :std_ulogic; +signal ex4_xuop_wayA_upd_q :std_ulogic; +signal ex4_wayA_val_d :std_ulogic_vector(0 to 5); +signal ex4_wayA_val_q :std_ulogic_vector(0 to 5); +signal rel_wayA_val_stg_d :std_ulogic_vector(0 to 5); +signal rel_wayA_val_stg_q :std_ulogic_vector(0 to 5); +signal ex5_xuop_wayA_upd_d :std_ulogic; +signal ex5_xuop_wayA_upd_q :std_ulogic; +signal congr_cl_ex3_upd_wayA :std_ulogic; +signal congr_cl_ex4_upd_wayA :std_ulogic; +signal congr_cl_ex5_upd_wayA :std_ulogic; +signal congr_cl_m_upd_wayA_d :std_ulogic; +signal congr_cl_m_upd_wayA_q :std_ulogic; +signal ex3_cClass_wayA_hit :std_ulogic; +signal wayA_later_stg_pri :std_ulogic_vector(0 to 5); +signal wayA_early_stg_pri :std_ulogic_vector(0 to 5); +signal wayA_stg_val :std_ulogic_vector(0 to 5); +signal wayA_stg_val_b :std_ulogic_vector(0 to 5); +signal rel_wayA_later_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayA_early_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayA_stg_val :std_ulogic_vector(0 to 5); +signal rel_wayA_stg_val_b :std_ulogic_vector(0 to 5); +signal wayA_early_sel :std_ulogic; +signal wayA_late_sel :std_ulogic; +signal rel_wayA_early_sel :std_ulogic; +signal rel_wayA_late_sel :std_ulogic; +signal ex3_wayA_hit :std_ulogic; +signal rel_lost_watch_wayA_evict :std_ulogic_vector(0 to 3); +signal ex3_wayA_fxubyp_val_d :std_ulogic; +signal ex3_wayA_fxubyp_val_q :std_ulogic; +signal ex4_wayA_fxubyp_val_d :std_ulogic; +signal ex4_wayA_fxubyp_val_q :std_ulogic; +signal ex3_wayA_relbyp_val_d :std_ulogic; +signal ex3_wayA_relbyp_val_q :std_ulogic; +signal ex4_wayA_relbyp_val_d :std_ulogic; +signal ex4_wayA_relbyp_val_q :std_ulogic; +signal ex4_wayA_byp_sel :std_ulogic_vector(0 to 1); +signal rel24_wayA_fxubyp_val_d :std_ulogic; +signal rel24_wayA_fxubyp_val_q :std_ulogic; +signal rel24_wayA_relbyp_val_d :std_ulogic; +signal rel24_wayA_relbyp_val_q :std_ulogic; +signal rel24_wayA_byp_sel :std_ulogic_vector(0 to 1); +signal tagB_hit :std_ulogic; +signal tagB_hit_b :std_ulogic; +signal arr_wayB_val :std_ulogic_vector(0 to 5); +signal p0_arr_wayB_rd :std_ulogic_vector(0 to 5); +signal flush_wayB_d :std_ulogic_vector(0 to 5); +signal flush_wayB_q :std_ulogic_vector(0 to 5); +signal rel_wayB_clr :std_ulogic; +signal rel_wayB_set :std_ulogic; +signal rel_par_wB_clr :std_ulogic; +signal wayB_val :std_ulogic_vector(0 to 5); +signal wayB_val_b_q :std_ulogic_vector(0 to 5); +signal wayB_val_b1 :std_ulogic; +signal congr_cl_ex2_wayB_byp :std_ulogic_vector(1 to 7); +signal congr_cl_ex2_wayB_sel :std_ulogic_vector(2 to 7); +signal rel_arr_wayB_val :std_ulogic_vector(0 to 5); +signal p1_arr_wayB_rd :std_ulogic_vector(0 to 5); +signal rel_wayB_val_b_q :std_ulogic_vector(0 to 5); +signal rel_wayB_val :std_ulogic_vector(0 to 5); +signal congr_cl_rel13_wayB_byp :std_ulogic_vector(1 to 7); +signal congr_cl_rel13_wayB_sel :std_ulogic_vector(2 to 7); +signal reload_wayB_d :std_ulogic_vector(0 to 5); +signal reload_wayB_q :std_ulogic_vector(0 to 5); +signal reload_wayB_data_d :std_ulogic_vector(0 to 5); +signal reload_wayB_data_q :std_ulogic_vector(0 to 5); +signal reload_wayB_data2_d :std_ulogic_vector(0 to 5); +signal reload_wayB_data2_q :std_ulogic_vector(0 to 5); +signal reload_wayB_upd_d :std_ulogic; +signal reload_wayB_upd_q :std_ulogic; +signal reload_wayB_clr :std_ulogic; +signal reload_wayB_upd2_d :std_ulogic; +signal reload_wayB_upd2_q :std_ulogic; +signal reload_wayB_upd3_d :std_ulogic; +signal reload_wayB_upd3_q :std_ulogic; +signal reload_wayB :std_ulogic_vector(0 to 5); +signal binv_wayB_upd_d :std_ulogic; +signal binv_wayB_upd_q :std_ulogic; +signal binv_wayB_upd1 :std_ulogic; +signal binv_wayB_upd2_d :std_ulogic; +signal binv_wayB_upd2_q :std_ulogic; +signal binv_wayB_upd3_d :std_ulogic; +signal binv_wayB_upd3_q :std_ulogic; +signal flush_wayB_data1 :std_ulogic_vector(0 to 5); +signal flush_wayB_data_d :std_ulogic_vector(0 to 5); +signal flush_wayB_data_q :std_ulogic_vector(0 to 5); +signal flush_wayB_data2_d :std_ulogic_vector(0 to 5); +signal flush_wayB_data2_q :std_ulogic_vector(0 to 5); +signal xu_op_hit_wayB_b :std_ulogic; +signal xu_op_hit_wayB :std_ulogic; +signal xu_op_hit_wayB_dly_b :std_ulogic; +signal clr_val_wayB :std_ulogic; +signal upd_lck_wayB :std_ulogic_vector(0 to 1); +signal inval_clr_lck_wB_d :std_ulogic; +signal inval_clr_lck_wB_q :std_ulogic; +signal perr_way_det_wayB :std_ulogic; +signal perr_wayB_watch_lost :std_ulogic_vector(0 to 3); +signal wayB_watch_value :std_ulogic; +signal ex4_lost_wayB :std_ulogic_vector(0 to 3); +signal ex3_xuop_lost_watch_wayB :std_ulogic; +signal ex3_xuop_wayB_upd :std_ulogic; +signal ex4_xuop_wayB_upd_d :std_ulogic; +signal ex4_xuop_wayB_upd_q :std_ulogic; +signal ex4_wayB_val_d :std_ulogic_vector(0 to 5); +signal ex4_wayB_val_q :std_ulogic_vector(0 to 5); +signal rel_wayB_val_stg_d :std_ulogic_vector(0 to 5); +signal rel_wayB_val_stg_q :std_ulogic_vector(0 to 5); +signal ex5_xuop_wayB_upd_d :std_ulogic; +signal ex5_xuop_wayB_upd_q :std_ulogic; +signal congr_cl_ex3_upd_wayB :std_ulogic; +signal congr_cl_ex4_upd_wayB :std_ulogic; +signal congr_cl_ex5_upd_wayB :std_ulogic; +signal congr_cl_m_upd_wayB_d :std_ulogic; +signal congr_cl_m_upd_wayB_q :std_ulogic; +signal ex3_cClass_wayB_hit :std_ulogic; +signal wayB_later_stg_pri :std_ulogic_vector(0 to 5); +signal wayB_early_stg_pri :std_ulogic_vector(0 to 5); +signal wayB_stg_val :std_ulogic_vector(0 to 5); +signal wayB_stg_val_b :std_ulogic_vector(0 to 5); +signal rel_wayB_later_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayB_early_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayB_stg_val :std_ulogic_vector(0 to 5); +signal rel_wayB_stg_val_b :std_ulogic_vector(0 to 5); +signal wayB_early_sel :std_ulogic; +signal wayB_late_sel :std_ulogic; +signal rel_wayB_early_sel :std_ulogic; +signal rel_wayB_late_sel :std_ulogic; +signal ex3_wayB_hit :std_ulogic; +signal rel_lost_watch_wayB_evict :std_ulogic_vector(0 to 3); +signal ex3_wayB_fxubyp_val_d :std_ulogic; +signal ex3_wayB_fxubyp_val_q :std_ulogic; +signal ex4_wayB_fxubyp_val_d :std_ulogic; +signal ex4_wayB_fxubyp_val_q :std_ulogic; +signal ex3_wayB_relbyp_val_d :std_ulogic; +signal ex3_wayB_relbyp_val_q :std_ulogic; +signal ex4_wayB_relbyp_val_d :std_ulogic; +signal ex4_wayB_relbyp_val_q :std_ulogic; +signal ex4_wayB_byp_sel :std_ulogic_vector(0 to 1); +signal rel24_wayB_fxubyp_val_d :std_ulogic; +signal rel24_wayB_fxubyp_val_q :std_ulogic; +signal rel24_wayB_relbyp_val_d :std_ulogic; +signal rel24_wayB_relbyp_val_q :std_ulogic; +signal rel24_wayB_byp_sel :std_ulogic_vector(0 to 1); +signal tagC_hit :std_ulogic; +signal tagC_hit_b :std_ulogic; +signal arr_wayC_val :std_ulogic_vector(0 to 5); +signal p0_arr_wayC_rd :std_ulogic_vector(0 to 5); +signal flush_wayC_d :std_ulogic_vector(0 to 5); +signal flush_wayC_q :std_ulogic_vector(0 to 5); +signal rel_wayC_clr :std_ulogic; +signal rel_wayC_set :std_ulogic; +signal rel_par_wC_clr :std_ulogic; +signal wayC_val :std_ulogic_vector(0 to 5); +signal wayC_val_b_q :std_ulogic_vector(0 to 5); +signal wayC_val_b1 :std_ulogic; +signal congr_cl_ex2_wayC_byp :std_ulogic_vector(1 to 7); +signal congr_cl_ex2_wayC_sel :std_ulogic_vector(2 to 7); +signal rel_arr_wayC_val :std_ulogic_vector(0 to 5); +signal p1_arr_wayC_rd :std_ulogic_vector(0 to 5); +signal rel_wayC_val_b_q :std_ulogic_vector(0 to 5); +signal rel_wayC_val :std_ulogic_vector(0 to 5); +signal congr_cl_rel13_wayC_byp :std_ulogic_vector(1 to 7); +signal congr_cl_rel13_wayC_sel :std_ulogic_vector(2 to 7); +signal reload_wayC_d :std_ulogic_vector(0 to 5); +signal reload_wayC_q :std_ulogic_vector(0 to 5); +signal reload_wayC_data_d :std_ulogic_vector(0 to 5); +signal reload_wayC_data_q :std_ulogic_vector(0 to 5); +signal reload_wayC_data2_d :std_ulogic_vector(0 to 5); +signal reload_wayC_data2_q :std_ulogic_vector(0 to 5); +signal reload_wayC_upd_d :std_ulogic; +signal reload_wayC_upd_q :std_ulogic; +signal reload_wayC_clr :std_ulogic; +signal reload_wayC_upd2_d :std_ulogic; +signal reload_wayC_upd2_q :std_ulogic; +signal reload_wayC_upd3_d :std_ulogic; +signal reload_wayC_upd3_q :std_ulogic; +signal reload_wayC :std_ulogic_vector(0 to 5); +signal binv_wayC_upd_d :std_ulogic; +signal binv_wayC_upd_q :std_ulogic; +signal binv_wayC_upd1 :std_ulogic; +signal binv_wayC_upd2_d :std_ulogic; +signal binv_wayC_upd2_q :std_ulogic; +signal binv_wayC_upd3_d :std_ulogic; +signal binv_wayC_upd3_q :std_ulogic; +signal flush_wayC_data1 :std_ulogic_vector(0 to 5); +signal flush_wayC_data_d :std_ulogic_vector(0 to 5); +signal flush_wayC_data_q :std_ulogic_vector(0 to 5); +signal flush_wayC_data2_d :std_ulogic_vector(0 to 5); +signal flush_wayC_data2_q :std_ulogic_vector(0 to 5); +signal xu_op_hit_wayC_b :std_ulogic; +signal xu_op_hit_wayC :std_ulogic; +signal xu_op_hit_wayC_dly_b :std_ulogic; +signal clr_val_wayC :std_ulogic; +signal upd_lck_wayC :std_ulogic_vector(0 to 1); +signal inval_clr_lck_wC_d :std_ulogic; +signal inval_clr_lck_wC_q :std_ulogic; +signal perr_way_det_wayC :std_ulogic; +signal perr_wayC_watch_lost :std_ulogic_vector(0 to 3); +signal wayC_watch_value :std_ulogic; +signal ex4_lost_wayC :std_ulogic_vector(0 to 3); +signal ex3_xuop_lost_watch_wayC :std_ulogic; +signal ex3_xuop_wayC_upd :std_ulogic; +signal ex4_xuop_wayC_upd_d :std_ulogic; +signal ex4_xuop_wayC_upd_q :std_ulogic; +signal ex4_wayC_val_d :std_ulogic_vector(0 to 5); +signal ex4_wayC_val_q :std_ulogic_vector(0 to 5); +signal rel_wayC_val_stg_d :std_ulogic_vector(0 to 5); +signal rel_wayC_val_stg_q :std_ulogic_vector(0 to 5); +signal ex5_xuop_wayC_upd_d :std_ulogic; +signal ex5_xuop_wayC_upd_q :std_ulogic; +signal congr_cl_ex3_upd_wayC :std_ulogic; +signal congr_cl_ex4_upd_wayC :std_ulogic; +signal congr_cl_ex5_upd_wayC :std_ulogic; +signal congr_cl_m_upd_wayC_d :std_ulogic; +signal congr_cl_m_upd_wayC_q :std_ulogic; +signal ex3_cClass_wayC_hit :std_ulogic; +signal wayC_later_stg_pri :std_ulogic_vector(0 to 5); +signal wayC_early_stg_pri :std_ulogic_vector(0 to 5); +signal wayC_stg_val :std_ulogic_vector(0 to 5); +signal wayC_stg_val_b :std_ulogic_vector(0 to 5); +signal rel_wayC_later_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayC_early_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayC_stg_val :std_ulogic_vector(0 to 5); +signal rel_wayC_stg_val_b :std_ulogic_vector(0 to 5); +signal wayC_early_sel :std_ulogic; +signal wayC_late_sel :std_ulogic; +signal rel_wayC_early_sel :std_ulogic; +signal rel_wayC_late_sel :std_ulogic; +signal ex3_wayC_hit :std_ulogic; +signal rel_lost_watch_wayC_evict :std_ulogic_vector(0 to 3); +signal ex3_wayC_fxubyp_val_d :std_ulogic; +signal ex3_wayC_fxubyp_val_q :std_ulogic; +signal ex4_wayC_fxubyp_val_d :std_ulogic; +signal ex4_wayC_fxubyp_val_q :std_ulogic; +signal ex3_wayC_relbyp_val_d :std_ulogic; +signal ex3_wayC_relbyp_val_q :std_ulogic; +signal ex4_wayC_relbyp_val_d :std_ulogic; +signal ex4_wayC_relbyp_val_q :std_ulogic; +signal ex4_wayC_byp_sel :std_ulogic_vector(0 to 1); +signal rel24_wayC_fxubyp_val_d :std_ulogic; +signal rel24_wayC_fxubyp_val_q :std_ulogic; +signal rel24_wayC_relbyp_val_d :std_ulogic; +signal rel24_wayC_relbyp_val_q :std_ulogic; +signal rel24_wayC_byp_sel :std_ulogic_vector(0 to 1); +signal tagD_hit :std_ulogic; +signal tagD_hit_b :std_ulogic; +signal arr_wayD_val :std_ulogic_vector(0 to 5); +signal p0_arr_wayD_rd :std_ulogic_vector(0 to 5); +signal flush_wayD_d :std_ulogic_vector(0 to 5); +signal flush_wayD_q :std_ulogic_vector(0 to 5); +signal rel_wayD_clr :std_ulogic; +signal rel_wayD_set :std_ulogic; +signal rel_par_wD_clr :std_ulogic; +signal wayD_val :std_ulogic_vector(0 to 5); +signal wayD_val_b_q :std_ulogic_vector(0 to 5); +signal wayD_val_b1 :std_ulogic; +signal congr_cl_ex2_wayD_byp :std_ulogic_vector(1 to 7); +signal congr_cl_ex2_wayD_sel :std_ulogic_vector(2 to 7); +signal rel_arr_wayD_val :std_ulogic_vector(0 to 5); +signal p1_arr_wayD_rd :std_ulogic_vector(0 to 5); +signal rel_wayD_val_b_q :std_ulogic_vector(0 to 5); +signal rel_wayD_val :std_ulogic_vector(0 to 5); +signal congr_cl_rel13_wayD_byp :std_ulogic_vector(1 to 7); +signal congr_cl_rel13_wayD_sel :std_ulogic_vector(2 to 7); +signal reload_wayD_d :std_ulogic_vector(0 to 5); +signal reload_wayD_q :std_ulogic_vector(0 to 5); +signal reload_wayD_data_d :std_ulogic_vector(0 to 5); +signal reload_wayD_data_q :std_ulogic_vector(0 to 5); +signal reload_wayD_data2_d :std_ulogic_vector(0 to 5); +signal reload_wayD_data2_q :std_ulogic_vector(0 to 5); +signal reload_wayD_upd_d :std_ulogic; +signal reload_wayD_upd_q :std_ulogic; +signal reload_wayD_clr :std_ulogic; +signal reload_wayD_upd2_d :std_ulogic; +signal reload_wayD_upd2_q :std_ulogic; +signal reload_wayD_upd3_d :std_ulogic; +signal reload_wayD_upd3_q :std_ulogic; +signal reload_wayD :std_ulogic_vector(0 to 5); +signal binv_wayD_upd_d :std_ulogic; +signal binv_wayD_upd_q :std_ulogic; +signal binv_wayD_upd1 :std_ulogic; +signal binv_wayD_upd2_d :std_ulogic; +signal binv_wayD_upd2_q :std_ulogic; +signal binv_wayD_upd3_d :std_ulogic; +signal binv_wayD_upd3_q :std_ulogic; +signal flush_wayD_data1 :std_ulogic_vector(0 to 5); +signal flush_wayD_data_d :std_ulogic_vector(0 to 5); +signal flush_wayD_data_q :std_ulogic_vector(0 to 5); +signal flush_wayD_data2_d :std_ulogic_vector(0 to 5); +signal flush_wayD_data2_q :std_ulogic_vector(0 to 5); +signal xu_op_hit_wayD_b :std_ulogic; +signal xu_op_hit_wayD :std_ulogic; +signal xu_op_hit_wayD_dly_b :std_ulogic; +signal clr_val_wayD :std_ulogic; +signal upd_lck_wayD :std_ulogic_vector(0 to 1); +signal inval_clr_lck_wD_d :std_ulogic; +signal inval_clr_lck_wD_q :std_ulogic; +signal perr_way_det_wayD :std_ulogic; +signal perr_wayD_watch_lost :std_ulogic_vector(0 to 3); +signal wayD_watch_value :std_ulogic; +signal ex4_lost_wayD :std_ulogic_vector(0 to 3); +signal ex3_xuop_lost_watch_wayD :std_ulogic; +signal ex3_xuop_wayD_upd :std_ulogic; +signal ex4_xuop_wayD_upd_d :std_ulogic; +signal ex4_xuop_wayD_upd_q :std_ulogic; +signal ex4_wayD_val_d :std_ulogic_vector(0 to 5); +signal ex4_wayD_val_q :std_ulogic_vector(0 to 5); +signal rel_wayD_val_stg_d :std_ulogic_vector(0 to 5); +signal rel_wayD_val_stg_q :std_ulogic_vector(0 to 5); +signal ex5_xuop_wayD_upd_d :std_ulogic; +signal ex5_xuop_wayD_upd_q :std_ulogic; +signal congr_cl_ex3_upd_wayD :std_ulogic; +signal congr_cl_ex4_upd_wayD :std_ulogic; +signal congr_cl_ex5_upd_wayD :std_ulogic; +signal congr_cl_m_upd_wayD_d :std_ulogic; +signal congr_cl_m_upd_wayD_q :std_ulogic; +signal ex3_cClass_wayD_hit :std_ulogic; +signal wayD_later_stg_pri :std_ulogic_vector(0 to 5); +signal wayD_early_stg_pri :std_ulogic_vector(0 to 5); +signal wayD_stg_val :std_ulogic_vector(0 to 5); +signal wayD_stg_val_b :std_ulogic_vector(0 to 5); +signal rel_wayD_later_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayD_early_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayD_stg_val :std_ulogic_vector(0 to 5); +signal rel_wayD_stg_val_b :std_ulogic_vector(0 to 5); +signal wayD_early_sel :std_ulogic; +signal wayD_late_sel :std_ulogic; +signal rel_wayD_early_sel :std_ulogic; +signal rel_wayD_late_sel :std_ulogic; +signal ex3_wayD_hit :std_ulogic; +signal rel_lost_watch_wayD_evict :std_ulogic_vector(0 to 3); +signal ex3_wayD_fxubyp_val_d :std_ulogic; +signal ex3_wayD_fxubyp_val_q :std_ulogic; +signal ex4_wayD_fxubyp_val_d :std_ulogic; +signal ex4_wayD_fxubyp_val_q :std_ulogic; +signal ex3_wayD_relbyp_val_d :std_ulogic; +signal ex3_wayD_relbyp_val_q :std_ulogic; +signal ex4_wayD_relbyp_val_d :std_ulogic; +signal ex4_wayD_relbyp_val_q :std_ulogic; +signal ex4_wayD_byp_sel :std_ulogic_vector(0 to 1); +signal rel24_wayD_fxubyp_val_d :std_ulogic; +signal rel24_wayD_fxubyp_val_q :std_ulogic; +signal rel24_wayD_relbyp_val_d :std_ulogic; +signal rel24_wayD_relbyp_val_q :std_ulogic; +signal rel24_wayD_byp_sel :std_ulogic_vector(0 to 1); +signal tagE_hit :std_ulogic; +signal tagE_hit_b :std_ulogic; +signal arr_wayE_val :std_ulogic_vector(0 to 5); +signal p0_arr_wayE_rd :std_ulogic_vector(0 to 5); +signal flush_wayE_d :std_ulogic_vector(0 to 5); +signal flush_wayE_q :std_ulogic_vector(0 to 5); +signal rel_wayE_clr :std_ulogic; +signal rel_wayE_set :std_ulogic; +signal rel_par_wE_clr :std_ulogic; +signal wayE_val :std_ulogic_vector(0 to 5); +signal wayE_val_b_q :std_ulogic_vector(0 to 5); +signal wayE_val_b1 :std_ulogic; +signal congr_cl_ex2_wayE_byp :std_ulogic_vector(1 to 7); +signal congr_cl_ex2_wayE_sel :std_ulogic_vector(2 to 7); +signal rel_arr_wayE_val :std_ulogic_vector(0 to 5); +signal p1_arr_wayE_rd :std_ulogic_vector(0 to 5); +signal rel_wayE_val_b_q :std_ulogic_vector(0 to 5); +signal rel_wayE_val :std_ulogic_vector(0 to 5); +signal congr_cl_rel13_wayE_byp :std_ulogic_vector(1 to 7); +signal congr_cl_rel13_wayE_sel :std_ulogic_vector(2 to 7); +signal reload_wayE_d :std_ulogic_vector(0 to 5); +signal reload_wayE_q :std_ulogic_vector(0 to 5); +signal reload_wayE_data_d :std_ulogic_vector(0 to 5); +signal reload_wayE_data_q :std_ulogic_vector(0 to 5); +signal reload_wayE_data2_d :std_ulogic_vector(0 to 5); +signal reload_wayE_data2_q :std_ulogic_vector(0 to 5); +signal reload_wayE_upd_d :std_ulogic; +signal reload_wayE_upd_q :std_ulogic; +signal reload_wayE_clr :std_ulogic; +signal reload_wayE_upd2_d :std_ulogic; +signal reload_wayE_upd2_q :std_ulogic; +signal reload_wayE_upd3_d :std_ulogic; +signal reload_wayE_upd3_q :std_ulogic; +signal reload_wayE :std_ulogic_vector(0 to 5); +signal binv_wayE_upd_d :std_ulogic; +signal binv_wayE_upd_q :std_ulogic; +signal binv_wayE_upd1 :std_ulogic; +signal binv_wayE_upd2_d :std_ulogic; +signal binv_wayE_upd2_q :std_ulogic; +signal binv_wayE_upd3_d :std_ulogic; +signal binv_wayE_upd3_q :std_ulogic; +signal flush_wayE_data1 :std_ulogic_vector(0 to 5); +signal flush_wayE_data_d :std_ulogic_vector(0 to 5); +signal flush_wayE_data_q :std_ulogic_vector(0 to 5); +signal flush_wayE_data2_d :std_ulogic_vector(0 to 5); +signal flush_wayE_data2_q :std_ulogic_vector(0 to 5); +signal xu_op_hit_wayE_b :std_ulogic; +signal xu_op_hit_wayE :std_ulogic; +signal xu_op_hit_wayE_dly_b :std_ulogic; +signal clr_val_wayE :std_ulogic; +signal upd_lck_wayE :std_ulogic_vector(0 to 1); +signal inval_clr_lck_wE_d :std_ulogic; +signal inval_clr_lck_wE_q :std_ulogic; +signal perr_way_det_wayE :std_ulogic; +signal perr_wayE_watch_lost :std_ulogic_vector(0 to 3); +signal wayE_watch_value :std_ulogic; +signal ex4_lost_wayE :std_ulogic_vector(0 to 3); +signal ex3_xuop_lost_watch_wayE :std_ulogic; +signal ex3_xuop_wayE_upd :std_ulogic; +signal ex4_xuop_wayE_upd_d :std_ulogic; +signal ex4_xuop_wayE_upd_q :std_ulogic; +signal ex4_wayE_val_d :std_ulogic_vector(0 to 5); +signal ex4_wayE_val_q :std_ulogic_vector(0 to 5); +signal rel_wayE_val_stg_d :std_ulogic_vector(0 to 5); +signal rel_wayE_val_stg_q :std_ulogic_vector(0 to 5); +signal ex5_xuop_wayE_upd_d :std_ulogic; +signal ex5_xuop_wayE_upd_q :std_ulogic; +signal congr_cl_ex3_upd_wayE :std_ulogic; +signal congr_cl_ex4_upd_wayE :std_ulogic; +signal congr_cl_ex5_upd_wayE :std_ulogic; +signal congr_cl_m_upd_wayE_d :std_ulogic; +signal congr_cl_m_upd_wayE_q :std_ulogic; +signal ex3_cClass_wayE_hit :std_ulogic; +signal wayE_later_stg_pri :std_ulogic_vector(0 to 5); +signal wayE_early_stg_pri :std_ulogic_vector(0 to 5); +signal wayE_stg_val :std_ulogic_vector(0 to 5); +signal wayE_stg_val_b :std_ulogic_vector(0 to 5); +signal rel_wayE_later_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayE_early_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayE_stg_val :std_ulogic_vector(0 to 5); +signal rel_wayE_stg_val_b :std_ulogic_vector(0 to 5); +signal wayE_early_sel :std_ulogic; +signal wayE_late_sel :std_ulogic; +signal rel_wayE_early_sel :std_ulogic; +signal rel_wayE_late_sel :std_ulogic; +signal ex3_wayE_hit :std_ulogic; +signal rel_lost_watch_wayE_evict :std_ulogic_vector(0 to 3); +signal ex3_wayE_fxubyp_val_d :std_ulogic; +signal ex3_wayE_fxubyp_val_q :std_ulogic; +signal ex4_wayE_fxubyp_val_d :std_ulogic; +signal ex4_wayE_fxubyp_val_q :std_ulogic; +signal ex3_wayE_relbyp_val_d :std_ulogic; +signal ex3_wayE_relbyp_val_q :std_ulogic; +signal ex4_wayE_relbyp_val_d :std_ulogic; +signal ex4_wayE_relbyp_val_q :std_ulogic; +signal ex4_wayE_byp_sel :std_ulogic_vector(0 to 1); +signal rel24_wayE_fxubyp_val_d :std_ulogic; +signal rel24_wayE_fxubyp_val_q :std_ulogic; +signal rel24_wayE_relbyp_val_d :std_ulogic; +signal rel24_wayE_relbyp_val_q :std_ulogic; +signal rel24_wayE_byp_sel :std_ulogic_vector(0 to 1); +signal tagF_hit :std_ulogic; +signal tagF_hit_b :std_ulogic; +signal arr_wayF_val :std_ulogic_vector(0 to 5); +signal p0_arr_wayF_rd :std_ulogic_vector(0 to 5); +signal flush_wayF_d :std_ulogic_vector(0 to 5); +signal flush_wayF_q :std_ulogic_vector(0 to 5); +signal rel_wayF_clr :std_ulogic; +signal rel_wayF_set :std_ulogic; +signal rel_par_wF_clr :std_ulogic; +signal wayF_val :std_ulogic_vector(0 to 5); +signal wayF_val_b_q :std_ulogic_vector(0 to 5); +signal wayF_val_b1 :std_ulogic; +signal congr_cl_ex2_wayF_byp :std_ulogic_vector(1 to 7); +signal congr_cl_ex2_wayF_sel :std_ulogic_vector(2 to 7); +signal rel_arr_wayF_val :std_ulogic_vector(0 to 5); +signal p1_arr_wayF_rd :std_ulogic_vector(0 to 5); +signal rel_wayF_val_b_q :std_ulogic_vector(0 to 5); +signal rel_wayF_val :std_ulogic_vector(0 to 5); +signal congr_cl_rel13_wayF_byp :std_ulogic_vector(1 to 7); +signal congr_cl_rel13_wayF_sel :std_ulogic_vector(2 to 7); +signal reload_wayF_d :std_ulogic_vector(0 to 5); +signal reload_wayF_q :std_ulogic_vector(0 to 5); +signal reload_wayF_data_d :std_ulogic_vector(0 to 5); +signal reload_wayF_data_q :std_ulogic_vector(0 to 5); +signal reload_wayF_data2_d :std_ulogic_vector(0 to 5); +signal reload_wayF_data2_q :std_ulogic_vector(0 to 5); +signal reload_wayF_upd_d :std_ulogic; +signal reload_wayF_upd_q :std_ulogic; +signal reload_wayF_clr :std_ulogic; +signal reload_wayF_upd2_d :std_ulogic; +signal reload_wayF_upd2_q :std_ulogic; +signal reload_wayF_upd3_d :std_ulogic; +signal reload_wayF_upd3_q :std_ulogic; +signal reload_wayF :std_ulogic_vector(0 to 5); +signal binv_wayF_upd_d :std_ulogic; +signal binv_wayF_upd_q :std_ulogic; +signal binv_wayF_upd1 :std_ulogic; +signal binv_wayF_upd2_d :std_ulogic; +signal binv_wayF_upd2_q :std_ulogic; +signal binv_wayF_upd3_d :std_ulogic; +signal binv_wayF_upd3_q :std_ulogic; +signal flush_wayF_data1 :std_ulogic_vector(0 to 5); +signal flush_wayF_data_d :std_ulogic_vector(0 to 5); +signal flush_wayF_data_q :std_ulogic_vector(0 to 5); +signal flush_wayF_data2_d :std_ulogic_vector(0 to 5); +signal flush_wayF_data2_q :std_ulogic_vector(0 to 5); +signal xu_op_hit_wayF_b :std_ulogic; +signal xu_op_hit_wayF :std_ulogic; +signal xu_op_hit_wayF_dly_b :std_ulogic; +signal clr_val_wayF :std_ulogic; +signal upd_lck_wayF :std_ulogic_vector(0 to 1); +signal inval_clr_lck_wF_d :std_ulogic; +signal inval_clr_lck_wF_q :std_ulogic; +signal perr_way_det_wayF :std_ulogic; +signal perr_wayF_watch_lost :std_ulogic_vector(0 to 3); +signal wayF_watch_value :std_ulogic; +signal ex4_lost_wayF :std_ulogic_vector(0 to 3); +signal ex3_xuop_lost_watch_wayF :std_ulogic; +signal ex3_xuop_wayF_upd :std_ulogic; +signal ex4_xuop_wayF_upd_d :std_ulogic; +signal ex4_xuop_wayF_upd_q :std_ulogic; +signal ex4_wayF_val_d :std_ulogic_vector(0 to 5); +signal ex4_wayF_val_q :std_ulogic_vector(0 to 5); +signal rel_wayF_val_stg_d :std_ulogic_vector(0 to 5); +signal rel_wayF_val_stg_q :std_ulogic_vector(0 to 5); +signal ex5_xuop_wayF_upd_d :std_ulogic; +signal ex5_xuop_wayF_upd_q :std_ulogic; +signal congr_cl_ex3_upd_wayF :std_ulogic; +signal congr_cl_ex4_upd_wayF :std_ulogic; +signal congr_cl_ex5_upd_wayF :std_ulogic; +signal congr_cl_m_upd_wayF_d :std_ulogic; +signal congr_cl_m_upd_wayF_q :std_ulogic; +signal ex3_cClass_wayF_hit :std_ulogic; +signal wayF_later_stg_pri :std_ulogic_vector(0 to 5); +signal wayF_early_stg_pri :std_ulogic_vector(0 to 5); +signal wayF_stg_val :std_ulogic_vector(0 to 5); +signal wayF_stg_val_b :std_ulogic_vector(0 to 5); +signal rel_wayF_later_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayF_early_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayF_stg_val :std_ulogic_vector(0 to 5); +signal rel_wayF_stg_val_b :std_ulogic_vector(0 to 5); +signal wayF_early_sel :std_ulogic; +signal wayF_late_sel :std_ulogic; +signal rel_wayF_early_sel :std_ulogic; +signal rel_wayF_late_sel :std_ulogic; +signal ex3_wayF_hit :std_ulogic; +signal rel_lost_watch_wayF_evict :std_ulogic_vector(0 to 3); +signal ex3_wayF_fxubyp_val_d :std_ulogic; +signal ex3_wayF_fxubyp_val_q :std_ulogic; +signal ex4_wayF_fxubyp_val_d :std_ulogic; +signal ex4_wayF_fxubyp_val_q :std_ulogic; +signal ex3_wayF_relbyp_val_d :std_ulogic; +signal ex3_wayF_relbyp_val_q :std_ulogic; +signal ex4_wayF_relbyp_val_d :std_ulogic; +signal ex4_wayF_relbyp_val_q :std_ulogic; +signal ex4_wayF_byp_sel :std_ulogic_vector(0 to 1); +signal rel24_wayF_fxubyp_val_d :std_ulogic; +signal rel24_wayF_fxubyp_val_q :std_ulogic; +signal rel24_wayF_relbyp_val_d :std_ulogic; +signal rel24_wayF_relbyp_val_q :std_ulogic; +signal rel24_wayF_byp_sel :std_ulogic_vector(0 to 1); +signal tagG_hit :std_ulogic; +signal tagG_hit_b :std_ulogic; +signal arr_wayG_val :std_ulogic_vector(0 to 5); +signal p0_arr_wayG_rd :std_ulogic_vector(0 to 5); +signal flush_wayG_d :std_ulogic_vector(0 to 5); +signal flush_wayG_q :std_ulogic_vector(0 to 5); +signal rel_wayG_clr :std_ulogic; +signal rel_wayG_set :std_ulogic; +signal rel_par_wG_clr :std_ulogic; +signal wayG_val :std_ulogic_vector(0 to 5); +signal wayG_val_b_q :std_ulogic_vector(0 to 5); +signal wayG_val_b1 :std_ulogic; +signal congr_cl_ex2_wayG_byp :std_ulogic_vector(1 to 7); +signal congr_cl_ex2_wayG_sel :std_ulogic_vector(2 to 7); +signal rel_arr_wayG_val :std_ulogic_vector(0 to 5); +signal p1_arr_wayG_rd :std_ulogic_vector(0 to 5); +signal rel_wayG_val_b_q :std_ulogic_vector(0 to 5); +signal rel_wayG_val :std_ulogic_vector(0 to 5); +signal congr_cl_rel13_wayG_byp :std_ulogic_vector(1 to 7); +signal congr_cl_rel13_wayG_sel :std_ulogic_vector(2 to 7); +signal reload_wayG_d :std_ulogic_vector(0 to 5); +signal reload_wayG_q :std_ulogic_vector(0 to 5); +signal reload_wayG_data_d :std_ulogic_vector(0 to 5); +signal reload_wayG_data_q :std_ulogic_vector(0 to 5); +signal reload_wayG_data2_d :std_ulogic_vector(0 to 5); +signal reload_wayG_data2_q :std_ulogic_vector(0 to 5); +signal reload_wayG_upd_d :std_ulogic; +signal reload_wayG_upd_q :std_ulogic; +signal reload_wayG_clr :std_ulogic; +signal reload_wayG_upd2_d :std_ulogic; +signal reload_wayG_upd2_q :std_ulogic; +signal reload_wayG_upd3_d :std_ulogic; +signal reload_wayG_upd3_q :std_ulogic; +signal reload_wayG :std_ulogic_vector(0 to 5); +signal binv_wayG_upd_d :std_ulogic; +signal binv_wayG_upd_q :std_ulogic; +signal binv_wayG_upd1 :std_ulogic; +signal binv_wayG_upd2_d :std_ulogic; +signal binv_wayG_upd2_q :std_ulogic; +signal binv_wayG_upd3_d :std_ulogic; +signal binv_wayG_upd3_q :std_ulogic; +signal flush_wayG_data1 :std_ulogic_vector(0 to 5); +signal flush_wayG_data_d :std_ulogic_vector(0 to 5); +signal flush_wayG_data_q :std_ulogic_vector(0 to 5); +signal flush_wayG_data2_d :std_ulogic_vector(0 to 5); +signal flush_wayG_data2_q :std_ulogic_vector(0 to 5); +signal xu_op_hit_wayG_b :std_ulogic; +signal xu_op_hit_wayG :std_ulogic; +signal xu_op_hit_wayG_dly_b :std_ulogic; +signal clr_val_wayG :std_ulogic; +signal upd_lck_wayG :std_ulogic_vector(0 to 1); +signal inval_clr_lck_wG_d :std_ulogic; +signal inval_clr_lck_wG_q :std_ulogic; +signal perr_way_det_wayG :std_ulogic; +signal perr_wayG_watch_lost :std_ulogic_vector(0 to 3); +signal wayG_watch_value :std_ulogic; +signal ex4_lost_wayG :std_ulogic_vector(0 to 3); +signal ex3_xuop_lost_watch_wayG :std_ulogic; +signal ex3_xuop_wayG_upd :std_ulogic; +signal ex4_xuop_wayG_upd_d :std_ulogic; +signal ex4_xuop_wayG_upd_q :std_ulogic; +signal ex4_wayG_val_d :std_ulogic_vector(0 to 5); +signal ex4_wayG_val_q :std_ulogic_vector(0 to 5); +signal rel_wayG_val_stg_d :std_ulogic_vector(0 to 5); +signal rel_wayG_val_stg_q :std_ulogic_vector(0 to 5); +signal ex5_xuop_wayG_upd_d :std_ulogic; +signal ex5_xuop_wayG_upd_q :std_ulogic; +signal congr_cl_ex3_upd_wayG :std_ulogic; +signal congr_cl_ex4_upd_wayG :std_ulogic; +signal congr_cl_ex5_upd_wayG :std_ulogic; +signal congr_cl_m_upd_wayG_d :std_ulogic; +signal congr_cl_m_upd_wayG_q :std_ulogic; +signal ex3_cClass_wayG_hit :std_ulogic; +signal wayG_later_stg_pri :std_ulogic_vector(0 to 5); +signal wayG_early_stg_pri :std_ulogic_vector(0 to 5); +signal wayG_stg_val :std_ulogic_vector(0 to 5); +signal wayG_stg_val_b :std_ulogic_vector(0 to 5); +signal rel_wayG_later_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayG_early_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayG_stg_val :std_ulogic_vector(0 to 5); +signal rel_wayG_stg_val_b :std_ulogic_vector(0 to 5); +signal wayG_early_sel :std_ulogic; +signal wayG_late_sel :std_ulogic; +signal rel_wayG_early_sel :std_ulogic; +signal rel_wayG_late_sel :std_ulogic; +signal ex3_wayG_hit :std_ulogic; +signal rel_lost_watch_wayG_evict :std_ulogic_vector(0 to 3); +signal ex3_wayG_fxubyp_val_d :std_ulogic; +signal ex3_wayG_fxubyp_val_q :std_ulogic; +signal ex4_wayG_fxubyp_val_d :std_ulogic; +signal ex4_wayG_fxubyp_val_q :std_ulogic; +signal ex3_wayG_relbyp_val_d :std_ulogic; +signal ex3_wayG_relbyp_val_q :std_ulogic; +signal ex4_wayG_relbyp_val_d :std_ulogic; +signal ex4_wayG_relbyp_val_q :std_ulogic; +signal ex4_wayG_byp_sel :std_ulogic_vector(0 to 1); +signal rel24_wayG_fxubyp_val_d :std_ulogic; +signal rel24_wayG_fxubyp_val_q :std_ulogic; +signal rel24_wayG_relbyp_val_d :std_ulogic; +signal rel24_wayG_relbyp_val_q :std_ulogic; +signal rel24_wayG_byp_sel :std_ulogic_vector(0 to 1); +signal tagH_hit :std_ulogic; +signal tagH_hit_b :std_ulogic; +signal arr_wayH_val :std_ulogic_vector(0 to 5); +signal p0_arr_wayH_rd :std_ulogic_vector(0 to 5); +signal flush_wayH_d :std_ulogic_vector(0 to 5); +signal flush_wayH_q :std_ulogic_vector(0 to 5); +signal rel_wayH_clr :std_ulogic; +signal rel_wayH_set :std_ulogic; +signal rel_par_wH_clr :std_ulogic; +signal wayH_val :std_ulogic_vector(0 to 5); +signal wayH_val_b_q :std_ulogic_vector(0 to 5); +signal wayH_val_b1 :std_ulogic; +signal congr_cl_ex2_wayH_byp :std_ulogic_vector(1 to 7); +signal congr_cl_ex2_wayH_sel :std_ulogic_vector(2 to 7); +signal rel_arr_wayH_val :std_ulogic_vector(0 to 5); +signal p1_arr_wayH_rd :std_ulogic_vector(0 to 5); +signal rel_wayH_val_b_q :std_ulogic_vector(0 to 5); +signal rel_wayH_val :std_ulogic_vector(0 to 5); +signal congr_cl_rel13_wayH_byp :std_ulogic_vector(1 to 7); +signal congr_cl_rel13_wayH_sel :std_ulogic_vector(2 to 7); +signal reload_wayH_d :std_ulogic_vector(0 to 5); +signal reload_wayH_q :std_ulogic_vector(0 to 5); +signal reload_wayH_data_d :std_ulogic_vector(0 to 5); +signal reload_wayH_data_q :std_ulogic_vector(0 to 5); +signal reload_wayH_data2_d :std_ulogic_vector(0 to 5); +signal reload_wayH_data2_q :std_ulogic_vector(0 to 5); +signal reload_wayH_upd_d :std_ulogic; +signal reload_wayH_upd_q :std_ulogic; +signal reload_wayH_clr :std_ulogic; +signal reload_wayH_upd2_d :std_ulogic; +signal reload_wayH_upd2_q :std_ulogic; +signal reload_wayH_upd3_d :std_ulogic; +signal reload_wayH_upd3_q :std_ulogic; +signal reload_wayH :std_ulogic_vector(0 to 5); +signal binv_wayH_upd_d :std_ulogic; +signal binv_wayH_upd_q :std_ulogic; +signal binv_wayH_upd1 :std_ulogic; +signal binv_wayH_upd2_d :std_ulogic; +signal binv_wayH_upd2_q :std_ulogic; +signal binv_wayH_upd3_d :std_ulogic; +signal binv_wayH_upd3_q :std_ulogic; +signal flush_wayH_data1 :std_ulogic_vector(0 to 5); +signal flush_wayH_data_d :std_ulogic_vector(0 to 5); +signal flush_wayH_data_q :std_ulogic_vector(0 to 5); +signal flush_wayH_data2_d :std_ulogic_vector(0 to 5); +signal flush_wayH_data2_q :std_ulogic_vector(0 to 5); +signal xu_op_hit_wayH_b :std_ulogic; +signal xu_op_hit_wayH :std_ulogic; +signal xu_op_hit_wayH_dly_b :std_ulogic; +signal clr_val_wayH :std_ulogic; +signal upd_lck_wayH :std_ulogic_vector(0 to 1); +signal inval_clr_lck_wH_d :std_ulogic; +signal inval_clr_lck_wH_q :std_ulogic; +signal perr_way_det_wayH :std_ulogic; +signal perr_wayH_watch_lost :std_ulogic_vector(0 to 3); +signal wayH_watch_value :std_ulogic; +signal ex4_lost_wayH :std_ulogic_vector(0 to 3); +signal ex3_xuop_lost_watch_wayH :std_ulogic; +signal ex3_xuop_wayH_upd :std_ulogic; +signal ex4_xuop_wayH_upd_d :std_ulogic; +signal ex4_xuop_wayH_upd_q :std_ulogic; +signal ex4_wayH_val_d :std_ulogic_vector(0 to 5); +signal ex4_wayH_val_q :std_ulogic_vector(0 to 5); +signal rel_wayH_val_stg_d :std_ulogic_vector(0 to 5); +signal rel_wayH_val_stg_q :std_ulogic_vector(0 to 5); +signal ex5_xuop_wayH_upd_d :std_ulogic; +signal ex5_xuop_wayH_upd_q :std_ulogic; +signal congr_cl_ex3_upd_wayH :std_ulogic; +signal congr_cl_ex4_upd_wayH :std_ulogic; +signal congr_cl_ex5_upd_wayH :std_ulogic; +signal congr_cl_m_upd_wayH_d :std_ulogic; +signal congr_cl_m_upd_wayH_q :std_ulogic; +signal ex3_cClass_wayH_hit :std_ulogic; +signal wayH_later_stg_pri :std_ulogic_vector(0 to 5); +signal wayH_early_stg_pri :std_ulogic_vector(0 to 5); +signal wayH_stg_val :std_ulogic_vector(0 to 5); +signal wayH_stg_val_b :std_ulogic_vector(0 to 5); +signal rel_wayH_later_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayH_early_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayH_stg_val :std_ulogic_vector(0 to 5); +signal rel_wayH_stg_val_b :std_ulogic_vector(0 to 5); +signal wayH_early_sel :std_ulogic; +signal wayH_late_sel :std_ulogic; +signal rel_wayH_early_sel :std_ulogic; +signal rel_wayH_late_sel :std_ulogic; +signal ex3_wayH_hit :std_ulogic; +signal rel_lost_watch_wayH_evict :std_ulogic_vector(0 to 3); +signal ex3_wayH_fxubyp_val_d :std_ulogic; +signal ex3_wayH_fxubyp_val_q :std_ulogic; +signal ex4_wayH_fxubyp_val_d :std_ulogic; +signal ex4_wayH_fxubyp_val_q :std_ulogic; +signal ex3_wayH_relbyp_val_d :std_ulogic; +signal ex3_wayH_relbyp_val_q :std_ulogic; +signal ex4_wayH_relbyp_val_d :std_ulogic; +signal ex4_wayH_relbyp_val_q :std_ulogic; +signal ex4_wayH_byp_sel :std_ulogic_vector(0 to 1); +signal rel24_wayH_fxubyp_val_d :std_ulogic; +signal rel24_wayH_fxubyp_val_q :std_ulogic; +signal rel24_wayH_relbyp_val_d :std_ulogic; +signal rel24_wayH_relbyp_val_q :std_ulogic; +signal rel24_wayH_byp_sel :std_ulogic_vector(0 to 1); +signal stm_upd_watchlost_tid0 :std_ulogic_vector(0 to 1); +signal upd_watch_tid0_wayA :std_ulogic_vector(0 to 1); +signal upd_watch_tid0_wayB :std_ulogic_vector(0 to 1); +signal upd_watch_tid0_wayC :std_ulogic_vector(0 to 1); +signal upd_watch_tid0_wayD :std_ulogic_vector(0 to 1); +signal upd_watch_tid0_wayE :std_ulogic_vector(0 to 1); +signal upd_watch_tid0_wayF :std_ulogic_vector(0 to 1); +signal upd_watch_tid0_wayG :std_ulogic_vector(0 to 1); +signal upd_watch_tid0_wayH :std_ulogic_vector(0 to 1); +signal stm_upd_watchlost_tid1 :std_ulogic_vector(0 to 1); +signal upd_watch_tid1_wayA :std_ulogic_vector(0 to 1); +signal upd_watch_tid1_wayB :std_ulogic_vector(0 to 1); +signal upd_watch_tid1_wayC :std_ulogic_vector(0 to 1); +signal upd_watch_tid1_wayD :std_ulogic_vector(0 to 1); +signal upd_watch_tid1_wayE :std_ulogic_vector(0 to 1); +signal upd_watch_tid1_wayF :std_ulogic_vector(0 to 1); +signal upd_watch_tid1_wayG :std_ulogic_vector(0 to 1); +signal upd_watch_tid1_wayH :std_ulogic_vector(0 to 1); +signal stm_upd_watchlost_tid2 :std_ulogic_vector(0 to 1); +signal upd_watch_tid2_wayA :std_ulogic_vector(0 to 1); +signal upd_watch_tid2_wayB :std_ulogic_vector(0 to 1); +signal upd_watch_tid2_wayC :std_ulogic_vector(0 to 1); +signal upd_watch_tid2_wayD :std_ulogic_vector(0 to 1); +signal upd_watch_tid2_wayE :std_ulogic_vector(0 to 1); +signal upd_watch_tid2_wayF :std_ulogic_vector(0 to 1); +signal upd_watch_tid2_wayG :std_ulogic_vector(0 to 1); +signal upd_watch_tid2_wayH :std_ulogic_vector(0 to 1); +signal stm_upd_watchlost_tid3 :std_ulogic_vector(0 to 1); +signal upd_watch_tid3_wayA :std_ulogic_vector(0 to 1); +signal upd_watch_tid3_wayB :std_ulogic_vector(0 to 1); +signal upd_watch_tid3_wayC :std_ulogic_vector(0 to 1); +signal upd_watch_tid3_wayD :std_ulogic_vector(0 to 1); +signal upd_watch_tid3_wayE :std_ulogic_vector(0 to 1); +signal upd_watch_tid3_wayF :std_ulogic_vector(0 to 1); +signal upd_watch_tid3_wayG :std_ulogic_vector(0 to 1); +signal upd_watch_tid3_wayH :std_ulogic_vector(0 to 1); +signal congr_cl_all_act_d :std_ulogic; +signal congr_cl_all_act_q :std_ulogic; +signal ex3_flush_cline_d :std_ulogic; +signal ex3_flush_cline_q :std_ulogic; +signal congr_cl_ex2_ex3_m :std_ulogic; +signal congr_cl_ex2_ex4_m :std_ulogic; +signal congr_cl_ex2_ex5_m :std_ulogic; +signal congr_cl_ex2_relu_m :std_ulogic; +signal congr_cl_ex2_relu_s_m :std_ulogic; +signal congr_cl_ex2_ex3_cmp_d :std_ulogic; +signal congr_cl_ex2_ex3_cmp_q :std_ulogic; +signal congr_cl_ex2_ex4_cmp_d :std_ulogic; +signal congr_cl_ex2_ex4_cmp_q :std_ulogic; +signal congr_cl_ex2_ex5_cmp_d :std_ulogic; +signal congr_cl_ex2_ex5_cmp_q :std_ulogic; +signal congr_cl_ex2_ex6_cmp_d :std_ulogic; +signal congr_cl_ex2_ex6_cmp_q :std_ulogic; +signal congr_cl_ex3_ex4_cmp_d :std_ulogic; +signal congr_cl_ex3_ex4_cmp_q :std_ulogic; +signal congr_cl_ex3_ex5_cmp_d :std_ulogic; +signal congr_cl_ex3_ex5_cmp_q :std_ulogic; +signal congr_cl_ex3_ex6_cmp_d :std_ulogic; +signal congr_cl_ex3_ex6_cmp_q :std_ulogic; +signal congr_cl_ex4_ex5_cmp_d :std_ulogic; +signal congr_cl_ex4_ex5_cmp_q :std_ulogic; +signal congr_cl_ex4_ex6_cmp_d :std_ulogic; +signal congr_cl_ex4_ex6_cmp_q :std_ulogic; +signal congr_cl_ex4_ex7_cmp_d :std_ulogic; +signal congr_cl_ex4_ex7_cmp_q :std_ulogic; +signal congr_cl_ex2_p0_cmp :std_ulogic; +signal congr_cl_ex2_relu_cmp_d :std_ulogic; +signal congr_cl_ex2_relu_cmp_q :std_ulogic; +signal congr_cl_ex2_relu_s_cmp_d :std_ulogic; +signal congr_cl_ex2_relu_s_cmp_q :std_ulogic; +signal congr_cl_ex2_rel_upd_cmp_d :std_ulogic; +signal congr_cl_ex2_rel_upd_cmp_q :std_ulogic; +signal congr_cl_ex2_p1_cmp :std_ulogic; +signal ex4_congr_cl_d :std_ulogic_vector(2 to 7); +signal ex4_congr_cl_q :std_ulogic_vector(2 to 7); +signal ex5_congr_cl_d :std_ulogic_vector(2 to 7); +signal ex5_congr_cl_q :std_ulogic_vector(2 to 7); +signal ex6_congr_cl_d :std_ulogic_vector(2 to 7); +signal ex6_congr_cl_q :std_ulogic_vector(2 to 7); +signal ex7_congr_cl_d :std_ulogic_vector(2 to 7); +signal ex7_congr_cl_q :std_ulogic_vector(2 to 7); +signal ex8_congr_cl_d :std_ulogic_vector(2 to 7); +signal ex8_congr_cl_q :std_ulogic_vector(2 to 7); +signal ex9_congr_cl_d :std_ulogic_vector(2 to 7); +signal ex9_congr_cl_q :std_ulogic_vector(2 to 7); +signal rel_early_congr_cl :std_ulogic_vector(2 to 7); +signal rel_congr_cl_d :std_ulogic_vector(2 to 7); +signal rel_congr_cl_q :std_ulogic_vector(2 to 7); +signal rel_val_stg1 :std_ulogic; +signal rel_val_stg2_d :std_ulogic; +signal rel_val_stg2_q :std_ulogic; +signal rel_val_clr_d :std_ulogic; +signal rel_val_clr_q :std_ulogic; +signal rel_val_stg3 :std_ulogic; +signal rel_val_stg4 :std_ulogic; +signal rel_val_stg4_d :std_ulogic; +signal rel_val_stg4_q :std_ulogic; +signal rel_binv_stg4_d :std_ulogic; +signal rel_binv_stg4_q :std_ulogic; +signal back_inval_stg2 :std_ulogic; +signal back_inval_stg3_d :std_ulogic; +signal back_inval_stg3_q :std_ulogic; +signal back_inval_stg4_d :std_ulogic; +signal back_inval_stg4_q :std_ulogic; +signal back_inval_stg5_d :std_ulogic; +signal back_inval_stg5_q :std_ulogic; +signal ex1_congr_cl :std_ulogic_vector(2 to 7); +signal ex2_congr_cl_d :std_ulogic_vector(2 to 7); +signal ex2_congr_cl_q :std_ulogic_vector(2 to 7); +signal ex3_congr_cl_d :std_ulogic_vector(2 to 7); +signal ex3_congr_cl_q :std_ulogic_vector(2 to 7); +signal rel24_congr_cl_d :std_ulogic_vector(2 to 7); +signal rel24_congr_cl_q :std_ulogic_vector(2 to 7); +signal p0_wren_d :std_ulogic; +signal p0_wren_q :std_ulogic; +signal p0_wren_cpy_d :std_ulogic; +signal p0_wren_cpy_q :std_ulogic; +signal p0_wren_stg_d :std_ulogic; +signal p0_wren_stg_q :std_ulogic; +signal p1_wren_d :std_ulogic; +signal p1_wren_q :std_ulogic; +signal p1_wren_cpy_d :std_ulogic; +signal p1_wren_cpy_q :std_ulogic; +signal congr_cl_rel13_ex3_m :std_ulogic; +signal congr_cl_rel13_ex4_m :std_ulogic; +signal congr_cl_rel13_ex5_m :std_ulogic; +signal congr_cl_rel13_relu_m :std_ulogic; +signal congr_cl_rel13_relu_s_m :std_ulogic; +signal congr_cl_rel13_ex3_cmp_d :std_ulogic; +signal congr_cl_rel13_ex3_cmp_q :std_ulogic; +signal congr_cl_rel13_ex4_cmp_d :std_ulogic; +signal congr_cl_rel13_ex4_cmp_q :std_ulogic; +signal congr_cl_rel13_ex5_cmp_d :std_ulogic; +signal congr_cl_rel13_ex5_cmp_q :std_ulogic; +signal congr_cl_rel13_ex6_cmp_d :std_ulogic; +signal congr_cl_rel13_ex6_cmp_q :std_ulogic; +signal congr_cl_rel13_p0_cmp :std_ulogic; +signal congr_cl_rel13_relu_cmp_d :std_ulogic; +signal congr_cl_rel13_relu_cmp_q :std_ulogic; +signal congr_cl_rel13_relu_s_cmp_d :std_ulogic; +signal congr_cl_rel13_relu_s_cmp_q :std_ulogic; +signal congr_cl_rel13_rel_upd_cmp_d :std_ulogic; +signal congr_cl_rel13_rel_upd_cmp_q :std_ulogic; +signal congr_cl_rel13_p1_cmp :std_ulogic; +signal ex3_c_acc :std_ulogic; +signal fxu_pipe_val :std_ulogic; +signal rel_set_val :std_ulogic; +signal ex3_store_instr_d :std_ulogic; +signal ex3_store_instr_q :std_ulogic; +signal ex3_lock_set_d :std_ulogic; +signal ex3_lock_set_q :std_ulogic; +signal ex4_lock_set_d :std_ulogic; +signal ex4_lock_set_q :std_ulogic; +signal ex5_lock_set_d :std_ulogic; +signal ex5_lock_set_q :std_ulogic; +signal ex3_lock_clr_d :std_ulogic; +signal ex3_lock_clr_q :std_ulogic; +signal clr_val :std_ulogic; +signal clr_lock :std_ulogic; +signal rel_val_set :std_ulogic; +signal rel_lock_set_d :std_ulogic; +signal rel_lock_set_q :std_ulogic; +signal rel_l1dump_cslc_d :std_ulogic; +signal rel_l1dump_cslc_q :std_ulogic; +signal rel_no_ovr_lock :std_ulogic; +signal rel_lock_lost :std_ulogic; +signal ex3_xuop_val :std_ulogic; +signal ex3_xuop_val_d :std_ulogic; +signal ex3_xuop_val_q :std_ulogic; +signal ex4_xuop_val :std_ulogic; +signal ex4_xuop_val_d :std_ulogic; +signal ex4_xuop_val_q :std_ulogic; +signal ex5_xuop_val :std_ulogic; +signal ex5_xuop_val_d :std_ulogic; +signal ex5_xuop_val_q :std_ulogic; +signal ex4_l_fld_b1_d :std_ulogic; +signal ex4_l_fld_b1_q :std_ulogic; +signal rel_in_progress :std_ulogic; +signal rel_in_progress_d :std_ulogic; +signal rel_in_progress_q :std_ulogic; +signal ex4_miss_q :std_ulogic; +signal ex4_way_hit_d :std_ulogic_vector(0 to 7); +signal ex4_way_hit_q :std_ulogic_vector(0 to 7); +signal ex5_way_hit_d :std_ulogic_vector(0 to 7); +signal ex5_way_hit_q :std_ulogic_vector(0 to 7); +signal ex6_way_hit_d :std_ulogic_vector(0 to 7); +signal ex6_way_hit_q :std_ulogic_vector(0 to 7); +signal ex7_way_hit_d :std_ulogic_vector(0 to 7); +signal ex7_way_hit_q :std_ulogic_vector(0 to 7); +signal ex8_way_hit_d :std_ulogic_vector(0 to 7); +signal ex8_way_hit_q :std_ulogic_vector(0 to 7); +signal ex9_way_hit_d :std_ulogic_vector(0 to 7); +signal ex9_way_hit_q :std_ulogic_vector(0 to 7); +signal dcpar_err_congr_cl :std_ulogic_vector(2 to 7); +signal dcpar_err_stg1_d :std_ulogic; +signal dcpar_err_stg1_q :std_ulogic; +signal dcpar_err_stg2_d :std_ulogic; +signal dcpar_err_stg2_q :std_ulogic; +signal dcpar_err_way_d :std_ulogic_vector(0 to 7); +signal dcpar_err_way_q :std_ulogic_vector(0 to 7); +signal dcpar_err_way_inval_d :std_ulogic_vector(0 to 7); +signal dcpar_err_way_inval_q :std_ulogic_vector(0 to 7); +signal dcpar_err_cntr_d :std_ulogic_vector(0 to 1); +signal dcpar_err_cntr_q :std_ulogic_vector(0 to 1); +signal dcpar_err_push :std_ulogic; +signal dcpar_err_rec_cmpl :std_ulogic; +signal dcpar_err_nxt_rec :std_ulogic; +signal dcpar_err_push_queue :std_ulogic; +signal dcpar_err_ind_sel :std_ulogic_vector(0 to 1); +signal dcpar_err_incr_val :std_ulogic; +signal dcpar_err_cntr_sel :std_ulogic_vector(0 to 1); +signal dcpar_err_nxt_cntr :std_ulogic_vector(0 to 1); +signal dcpar_err_rec_inprog :std_ulogic; +signal dcpar_err_ind_sel_d :std_ulogic_vector(0 to 1); +signal dcpar_err_ind_sel_q :std_ulogic_vector(0 to 1); +signal dcpar_err_push_queue_d :std_ulogic; +signal dcpar_err_push_queue_q :std_ulogic; +signal lock_finval :std_ulogic; +signal inval_clr_lck :std_ulogic; +signal xucr0_cslc_xuop_d :std_ulogic; +signal xucr0_cslc_xuop_q :std_ulogic; +signal xucr0_cslc_binv_d :std_ulogic; +signal xucr0_cslc_binv_q :std_ulogic; +signal dci_compl_d :std_ulogic; +signal dci_compl_q :std_ulogic; +signal dci_inval_all_d :std_ulogic; +signal dci_inval_all_q :std_ulogic; +signal inv2_val_d :std_ulogic; +signal inv2_val_q :std_ulogic; +signal perf_binv_hit :std_ulogic; +signal perf_lsu_evnts_d :std_ulogic_vector(0 to 4); +signal perf_lsu_evnts_q :std_ulogic_vector(0 to 4); +signal lock_flash_clear_d :std_ulogic; +signal lock_flash_clear_q :std_ulogic; +signal lock_flash_clear_val_d :std_ulogic; +signal lock_flash_clear_val_q :std_ulogic; +signal rel_port_upd_d :std_ulogic; +signal rel_port_upd_q :std_ulogic; +signal p1_upd_val :std_ulogic; +signal rel_port_wren_d :std_ulogic; +signal rel_port_wren_q :std_ulogic; +signal ex2_thrd_id_d :std_ulogic_vector(0 to 3); +signal ex2_thrd_id_q :std_ulogic_vector(0 to 3); +signal ex3_thrd_id_d :std_ulogic_vector(0 to 3); +signal ex3_thrd_id_q :std_ulogic_vector(0 to 3); +signal ex4_thrd_id_d :std_ulogic_vector(0 to 3); +signal ex4_thrd_id_q :std_ulogic_vector(0 to 3); +signal ex5_thrd_id_d :std_ulogic_vector(0 to 3); +signal ex5_thrd_id_q :std_ulogic_vector(0 to 3); +signal ex3_watch_set_d :std_ulogic; +signal ex3_watch_set_q :std_ulogic; +signal ex4_watch_set_d :std_ulogic; +signal ex4_watch_set_q :std_ulogic; +signal ex5_watch_set_d :std_ulogic; +signal ex5_watch_set_q :std_ulogic; +signal ex3_watch_clr_d :std_ulogic; +signal ex3_watch_clr_q :std_ulogic; +signal ex2_watch_clr_all :std_ulogic; +signal ex2_watch_clr_one :std_ulogic; +signal ex3_watch_clr_all_d :std_ulogic; +signal ex3_watch_clr_all_q :std_ulogic; +signal ex3_watch_clr_all :std_ulogic_vector(0 to 3); +signal ex4_watch_clr_all_d :std_ulogic_vector(0 to 3); +signal ex4_watch_clr_all_q :std_ulogic_vector(0 to 3); +signal ex5_watch_clr_all_d :std_ulogic_vector(0 to 3); +signal ex5_watch_clr_all_q :std_ulogic_vector(0 to 3); +signal ex6_watch_clr_all_d :std_ulogic_vector(0 to 3); +signal ex6_watch_clr_all_q :std_ulogic_vector(0 to 3); +signal ex5_watch_clr_all_val_d :std_ulogic; +signal ex5_watch_clr_all_val_q :std_ulogic; +signal rel_watch_set_d :std_ulogic; +signal rel_watch_set_q :std_ulogic; +signal rel_thrd_id_d :std_ulogic_vector(0 to 3); +signal rel_thrd_id_q :std_ulogic_vector(0 to 3); +signal rel_watch_lost :std_ulogic_vector(0 to 3); +signal lose_watch :std_ulogic_vector(0 to 3); +signal ex4_lose_watch_d :std_ulogic_vector(0 to 3); +signal ex4_lose_watch_q :std_ulogic_vector(0 to 3); +signal clr_watch :std_ulogic_vector(0 to 3); +signal set_watch :std_ulogic_vector(0 to 3); +signal ex4_curr_watch :std_ulogic; +signal stm_watchlost_sel :std_ulogic; +signal ex5_cr_watch_d :std_ulogic; +signal ex5_cr_watch_q :std_ulogic; +signal ex4_lost_watch :std_ulogic_vector(0 to 3); +signal ex4_lost_watch_upd :std_ulogic_vector(0 to 3); +signal ex5_lost_watch_upd_d :std_ulogic_vector(0 to 3); +signal ex5_lost_watch_upd_q :std_ulogic_vector(0 to 3); +signal ex4_watchlost_set_d :std_ulogic_vector(0 to 3); +signal ex4_watchlost_set_q :std_ulogic_vector(0 to 3); +signal ex5_watchlost_set_d :std_ulogic_vector(0 to 3); +signal ex5_watchlost_set_q :std_ulogic_vector(0 to 3); +signal rel_lost_watch_binv_d :std_ulogic_vector(0 to 3); +signal rel_lost_watch_binv_q :std_ulogic_vector(0 to 3); +signal rel_lost_watch_upd_d :std_ulogic_vector(0 to 3); +signal rel_lost_watch_upd_q :std_ulogic_vector(0 to 3); +signal rel_lost_watch_evict :std_ulogic_vector(0 to 3); +signal rel_lost_watch_evict_np :std_ulogic_vector(0 to 3); +signal lost_watch_evict_ovl_d :std_ulogic_vector(0 to 3); +signal lost_watch_evict_ovl_q :std_ulogic_vector(0 to 3); +signal lost_watch_binv :std_ulogic_vector(0 to 3); +signal lost_watch_inter_thrd_d :std_ulogic_vector(0 to 3); +signal lost_watch_inter_thrd_q :std_ulogic_vector(0 to 3); +signal stm_watchlost :std_ulogic_vector(0 to 3); +signal rel_watchlost_upd :std_ulogic_vector(0 to 3); +signal ex5_watchlost_upd :std_ulogic_vector(0 to 3); +signal stm_watchlost_state_d :std_ulogic_vector(0 to 3); +signal stm_watchlost_state_q :std_ulogic_vector(0 to 3); +signal ex5_xuop_p0_upd_d :std_ulogic; +signal ex5_xuop_p0_upd_q :std_ulogic; +signal rel_val_stg24 :std_ulogic; +signal rel_val_stgu_d :std_ulogic; +signal rel_val_stgu_q :std_ulogic; +signal relu_congr_cl_d :std_ulogic_vector(2 to 7); +signal relu_congr_cl_q :std_ulogic_vector(2 to 7); +signal relu_s_congr_cl_d :std_ulogic_vector(2 to 7); +signal relu_s_congr_cl_q :std_ulogic_vector(2 to 7); +signal ex3_thrd_m_d :std_ulogic; +signal ex3_thrd_m_q :std_ulogic; +signal ex4_thrd_m_d :std_ulogic; +signal ex4_thrd_m_q :std_ulogic; +signal ex5_thrd_m_d :std_ulogic; +signal ex5_thrd_m_q :std_ulogic; +signal ex6_thrd_m_d :std_ulogic; +signal ex6_thrd_m_q :std_ulogic; +signal ex7_ld_par_err_d :std_ulogic; +signal ex7_ld_par_err_q :std_ulogic; +signal ex8_ld_par_err_d :std_ulogic; +signal ex8_ld_par_err_q :std_ulogic; +signal ex9_ld_par_err_d :std_ulogic; +signal ex9_ld_par_err_q :std_ulogic; +signal ex6_ld_valid_d :std_ulogic; +signal ex6_ld_valid_q :std_ulogic; +signal ex7_ld_valid_d :std_ulogic; +signal ex7_ld_valid_q :std_ulogic; +signal ex8_ld_valid_d :std_ulogic; +signal ex8_ld_valid_q :std_ulogic; +signal ex9_ld_valid_d :std_ulogic; +signal ex9_ld_valid_q :std_ulogic; +signal inj_dir_multihit_b :std_ulogic; +signal inj_dir_multihit_d :std_ulogic; +signal inj_dir_multihit_q :std_ulogic; +signal binv1_ex1_stg_act :std_ulogic; +signal binv2_ex2_stg_act :std_ulogic; +signal binv3_ex3_stg_act :std_ulogic; +signal binv4_ex4_stg_act :std_ulogic; +signal binv5_ex5_stg_act :std_ulogic; +signal binv2_ex2_val_stg_act :std_ulogic; +signal binv3_ex3_val_stg_act :std_ulogic; +signal binv4_ex4_val_stg_act :std_ulogic; +signal binv5_ex5_val_stg_act :std_ulogic; +signal dcpar_err_stg1_act_d :std_ulogic; +signal dcpar_err_stg1_act_q :std_ulogic; +signal dcpar_err_stg2_act_d :std_ulogic; +signal dcpar_err_stg2_act_q :std_ulogic; +signal rel1_perr_stg_act :std_ulogic; +signal rel2_perr_stg_act :std_ulogic; +signal rel3_perr_stg_act_d :std_ulogic; +signal rel3_perr_stg_act_q :std_ulogic; +signal rel4_perr_stg_act_d :std_ulogic; +signal rel4_perr_stg_act_q :std_ulogic; +signal reload_way_clr_d :std_ulogic_vector(0 to 7); +signal reload_way_clr_q :std_ulogic_vector(0 to 7); +signal ex4_watchSet_coll_d :std_ulogic; +signal ex4_watchSet_coll_q :std_ulogic; +signal watchSet_rel_way_coll :std_ulogic_vector(0 to 7); +signal watchSet_rel_coll_val :std_ulogic_vector(0 to 3); +signal rel24_congr_cl_ex4_cmp_d :std_ulogic; +signal rel24_congr_cl_ex4_cmp_q :std_ulogic; +signal rel24_congr_cl_ex5_cmp_d :std_ulogic; +signal rel24_congr_cl_ex5_cmp_q :std_ulogic; +signal rel24_congr_cl_ex6_cmp_d :std_ulogic; +signal rel24_congr_cl_ex6_cmp_q :std_ulogic; +signal relu_congr_cl_ex5_cmp_d :std_ulogic; +signal relu_congr_cl_ex5_cmp_q :std_ulogic; +signal relu_congr_cl_ex6_cmp_d :std_ulogic; +signal relu_congr_cl_ex6_cmp_q :std_ulogic; +signal relu_congr_cl_ex7_cmp_d :std_ulogic; +signal relu_congr_cl_ex7_cmp_q :std_ulogic; +signal rel_ex5_watchSet_coll :std_ulogic; +signal rel_ex6_watchSet_coll :std_ulogic; +signal rel_ex7_watchSet_coll :std_ulogic; +signal rel_coll_val :std_ulogic; +signal relu_dir_data :std_ulogic_vector(2 to 5); +signal rel_pri_byp_sel :std_ulogic_vector(0 to 2); +signal rel_byp_dir_data :std_ulogic_vector(2 to 5); +signal rel_watchSet_coll_tid :std_ulogic_vector(0 to 3); +signal lost_watch_evict_val_d :std_ulogic_vector(0 to 3); +signal lost_watch_evict_val_q :std_ulogic_vector(0 to 3); +signal dcpar_err_lock_lost :std_ulogic_vector(0 to 7); +signal dirpar_err_lock_lost :std_ulogic_vector(0 to 7); +signal ex3_dir_perr_val :std_ulogic; +signal ex3_dir_multihit_val :std_ulogic; +signal ex4_dir_err_val_d :std_ulogic; +signal ex4_dir_err_val_q :std_ulogic; +signal ex5_dir_err_val_d :std_ulogic; +signal ex5_dir_err_val_q :std_ulogic; +signal ex6_dir_err_val_d :std_ulogic; +signal ex6_dir_err_val_q :std_ulogic; +signal derr2_stg_act_d :std_ulogic; +signal derr2_stg_act_q :std_ulogic; +signal derr3_stg_act_d :std_ulogic; +signal derr3_stg_act_q :std_ulogic; +signal derr4_stg_act_d :std_ulogic; +signal derr4_stg_act_q :std_ulogic; +signal derr5_stg_act_d :std_ulogic; +signal derr5_stg_act_q :std_ulogic; +signal ex4_err_det_way_d :std_ulogic_vector(0 to 7); +signal ex4_err_det_way_q :std_ulogic_vector(0 to 7); +signal ex4_perr_lck_lost_d :std_ulogic; +signal ex4_perr_lck_lost_q :std_ulogic; +signal ex4_perr_watch_lost_d :std_ulogic_vector(0 to 3); +signal ex4_perr_watch_lost_q :std_ulogic_vector(0 to 3); +signal dcperr_lock_lost_d :std_ulogic; +signal dcperr_lock_lost_q :std_ulogic; +signal ex4_dir_multihit_val_b_q :std_ulogic; +signal ex4_dir_multihit_val :std_ulogic; +signal binv4_ex4_lock_set :std_ulogic; +signal binv4_ex4_thrd_watch :std_ulogic_vector(0 to 3); +signal ex4_multihit_watch_lost :std_ulogic_vector(0 to 3); +signal ex4_multihit_lock_lost :std_ulogic; +signal ex3_watch_chk_d :std_ulogic; +signal ex3_watch_chk_q :std_ulogic; +signal ex4_watch_chk_d :std_ulogic; +signal ex4_watch_chk_q :std_ulogic; +signal ex5_watch_chk_d :std_ulogic; +signal ex5_watch_chk_q :std_ulogic; +signal ex5_watch_chk_cplt :std_ulogic; +signal ex5_watch_chk_succ :std_ulogic; +signal ex5_watch_dup_set :std_ulogic; +signal hit_and_01_b :std_ulogic; +signal hit_and_23_b :std_ulogic; +signal hit_and_45_b :std_ulogic; +signal hit_and_67_b :std_ulogic; +signal hit_or_01_b :std_ulogic; +signal hit_or_23_b :std_ulogic; +signal hit_or_45_b :std_ulogic; +signal hit_or_67_b :std_ulogic; +signal hit_or_13_b :std_ulogic; +signal hit_or_57_b :std_ulogic; +signal hit_or_0123 :std_ulogic; +signal hit_or_4567 :std_ulogic; +signal hit_or_1357 :std_ulogic; +signal hit_or_2367 :std_ulogic; +signal hit_and_0123 :std_ulogic; +signal hit_and_4567 :std_ulogic; +signal multi_hit_err2_0 :std_ulogic; +signal multi_hit_err2_1 :std_ulogic; +signal hit_or_01234567_b :std_ulogic; +signal ex3_dir_multihit_val_0 :std_ulogic; +signal ex3_dir_multihit_val_1 :std_ulogic; +signal ex3_dir_multihit_val_b :std_ulogic; +signal multi_hit_err3_b :std_ulogic_vector(0 to 2); +signal hit_enc_b :std_ulogic_vector(0 to 2); +signal ex3_l_fld_b1_d :std_ulogic; +signal ex3_l_fld_b1_q :std_ulogic; +signal binv4_ex4_way_upd :std_ulogic_vector(0 to 7); +signal binv5_ex5_way_upd :std_ulogic_vector(0 to 7); +signal binv6_ex6_way_upd :std_ulogic_vector(0 to 7); +signal binv7_ex7_way_upd_d :std_ulogic_vector(0 to 7); +signal binv7_ex7_way_upd_q :std_ulogic_vector(0 to 7); +signal binv4_ex4_dir_data :std_ulogic_vector(1 to 5); +signal binv5_ex5_dir_data_d :std_ulogic_vector(1 to 5); +signal binv5_ex5_dir_data_q :std_ulogic_vector(1 to 5); +signal binv6_ex6_dir_data_d :std_ulogic_vector(1 to 5); +signal binv6_ex6_dir_data_q :std_ulogic_vector(1 to 5); +signal binv7_ex7_dir_data_d :std_ulogic_vector(1 to 5); +signal binv7_ex7_dir_data_q :std_ulogic_vector(1 to 5); +signal binv4_inval_lck :std_ulogic; +signal binv4_inval_watch :std_ulogic_vector(0 to 3); +signal binv4_coll_val :std_ulogic; +signal binv4_ex5_coll :std_ulogic; +signal binv4_ex6_coll :std_ulogic; +signal binv4_ex7_coll :std_ulogic; +signal binv4_pri_byp_sel :std_ulogic_vector(0 to 2); +signal binv4_byp_dir_data :std_ulogic_vector(1 to 5); +signal binv5_inval_lock_val_d :std_ulogic; +signal binv5_inval_lock_val_q :std_ulogic; +signal binv5_inval_watch_val_d :std_ulogic_vector(0 to 3); +signal binv5_inval_watch_val_q :std_ulogic_vector(0 to 3); +signal binv5_ex5_lost_watch_upd :std_ulogic_vector(0 to 3); +signal dci_watch_lost :std_ulogic_vector(0 to 3); +signal ex3_xuop_upd_dir :std_ulogic; +signal binv3_ex3_xuop_upd :std_ulogic; +signal binv4_ex4_xuop_upd_d :std_ulogic; +signal binv4_ex4_xuop_upd_q :std_ulogic; +signal ex3_dir_acc_val :std_ulogic; +signal binv3_ex3_dir_val :std_ulogic; +signal binv4_ex4_dir_val_d :std_ulogic; +signal binv4_ex4_dir_val_q :std_ulogic; +signal ex3_l1hit :std_ulogic; +signal ex3_l1miss :std_ulogic; +signal ex4_snd_ld_l2_q :std_ulogic; +signal ex4_ldq_full_flush_b_q :std_ulogic; +signal rel_in_prog_stg1_d :std_ulogic; +signal rel_in_prog_stg1_q :std_ulogic; +signal rel_in_prog_stg2_d :std_ulogic; +signal rel_in_prog_stg2_q :std_ulogic; +signal rel_in_prog_stg3_d :std_ulogic; +signal rel_in_prog_stg3_q :std_ulogic; +signal rel_in_prog_stg4_d :std_ulogic; +signal rel_in_prog_stg4_q :std_ulogic; +signal rel_in_prog_stg5_d :std_ulogic; +signal rel_in_prog_stg5_q :std_ulogic; +signal ex4_instr_enc_d :std_ulogic_vector(0 to 3); +signal ex4_instr_enc_q :std_ulogic_vector(0 to 3); +signal ex4_wclr_all_val_d :std_ulogic; +signal ex4_wclr_all_val_q :std_ulogic; +signal ex5_wclr_all_val_d :std_ulogic; +signal ex5_wclr_all_val_q :std_ulogic; +signal ex6_wclr_all_val_d :std_ulogic; +signal ex6_wclr_all_val_q :std_ulogic; +signal ex3_wclr_all_upd_val :std_ulogic; +signal ex4_wclr_all_upd_val :std_ulogic; +signal ex5_wclr_all_upd_val :std_ulogic; +signal ex6_wclr_all_upd_val :std_ulogic; +signal ex3_wclr_all_upd_d :std_ulogic; +signal ex3_wclr_all_upd_q :std_ulogic; +signal ex4_n_lsu_ddmh_flush_b_d :std_ulogic_vector(0 to 3); +signal ex4_n_lsu_ddmh_flush_b_q :std_ulogic_vector(0 to 3); +signal ex3_xuop_up_addr_b :std_ulogic_vector(0 to 2); +signal rel_dcarr_addr_sel :std_ulogic_vector(0 to 2); +signal rel_dcarr_addr_sel_b :std_ulogic_vector(0 to 2); +signal dcarr_up_way_addr_q :std_ulogic_vector(0 to 2); +signal rel4_l1dump_val_q :std_ulogic; +signal rel4_l1dump_watch :std_ulogic; +signal lost_watch_l1dump :std_ulogic_vector(0 to 3); +signal my_lclk :clk_logic; +signal my_d1clk :std_ulogic; +signal my_d2clk :std_ulogic; +signal my_multihit_lclk :clk_logic; +signal my_multihit_d1clk :std_ulogic; +signal my_multihit_d2clk :std_ulogic; +signal my_ddmh_lclk :clk_logic; +signal my_ddmh_d1clk :std_ulogic; +signal my_ddmh_d2clk :std_ulogic; +signal ex4_miss_siv :std_ulogic; +signal ex4_miss_sov :std_ulogic; +signal my_spare0_lclk :clk_logic; +signal my_spare0_d1clk :std_ulogic; +signal my_spare0_d2clk :std_ulogic; +signal my_spare0_latches_d :std_ulogic_vector(0 to 16); +signal my_spare0_latches_q :std_ulogic_vector(0 to 16); +signal my_spare1_lclk :clk_logic; +signal my_spare1_d1clk :std_ulogic; +signal my_spare1_d2clk :std_ulogic; +signal my_spare1_latches_d :std_ulogic_vector(0 to 15); +signal my_spare1_latches_q :std_ulogic_vector(0 to 15); +signal tiup :std_ulogic; +signal siv :std_ulogic_vector(0 to scan_right); +signal sov :std_ulogic_vector(0 to scan_right); + BEGIN + +tiup <= '1'; +inv2_val_d <= inv1_val and not spr_xucr0_dcdis; +back_inval_stg2 <= inv2_val_q; +rel_val_stg1 <= rel1_val; +rel_val_stg3 <= rel3_val; +rel_set_val <= rel4_set_val; +lock_flash_clear_d <= xu_lsu_spr_xucr0_clfc; +lock_flash_clear_val_d <= lock_flash_clear_q; +dci_compl_d <= xu_lsu_dci; +dci_inval_all_d <= dci_compl_q; +lock_finval <= dci_inval_all_q or lock_flash_clear_val_q; +inj_dir_multihit_d <= pc_xu_inj_dcachedir_multihit; +ex3_l_fld_b1_d <= ex2_l_fld(1); +tagA_hit <= ex3_way_cmp_a; +rel_wayA_clr <= rel_way_clr_a; +rel_wayA_set <= rel_way_wen_a; +tagB_hit <= ex3_way_cmp_b; +rel_wayB_clr <= rel_way_clr_b; +rel_wayB_set <= rel_way_wen_b; +tagC_hit <= ex3_way_cmp_c; +rel_wayC_clr <= rel_way_clr_c; +rel_wayC_set <= rel_way_wen_c; +tagD_hit <= ex3_way_cmp_d; +rel_wayD_clr <= rel_way_clr_d; +rel_wayD_set <= rel_way_wen_d; +tagE_hit <= ex3_way_cmp_e; +rel_wayE_clr <= rel_way_clr_e; +rel_wayE_set <= rel_way_wen_e; +tagF_hit <= ex3_way_cmp_f; +rel_wayF_clr <= rel_way_clr_f; +rel_wayF_set <= rel_way_wen_f; +tagG_hit <= ex3_way_cmp_g; +rel_wayG_clr <= rel_way_clr_g; +rel_wayG_set <= rel_way_wen_g; +tagH_hit <= ex3_way_cmp_h; +rel_wayH_clr <= rel_way_clr_h; +rel_wayH_set <= rel_way_wen_h; +ex3_c_acc <= ex3_cache_en; +binv1_ex1_stg_act <= binv1_stg_act or ex1_stg_act; +binv2_ex2_stg_act <= binv2_stg_act or ex2_stg_act; +binv3_ex3_stg_act <= binv3_stg_act or ex3_stg_act; +binv4_ex4_stg_act <= binv4_stg_act or ex4_stg_act; +binv5_ex5_stg_act <= binv5_stg_act or ex5_stg_act; +binv2_ex2_val_stg_act <= derr2_stg_act_q or binv2_stg_act or ex2_stg_act; +binv3_ex3_val_stg_act <= derr3_stg_act_q or binv3_stg_act or ex3_stg_act; +binv4_ex4_val_stg_act <= derr4_stg_act_q or binv4_stg_act or ex4_stg_act; +binv5_ex5_val_stg_act <= derr5_stg_act_q or binv5_stg_act or ex5_stg_act; +rel1_perr_stg_act <= rel1_stg_act or dcpar_err_stg1_act_q; +rel2_perr_stg_act <= rel2_stg_act or dcpar_err_stg2_act_q; +rel3_perr_stg_act_d <= rel2_perr_stg_act; +rel4_perr_stg_act_d <= rel3_perr_stg_act_q; +ex1_congr_cl <= ex1_p_addr; +cl64size : if (cl_size=6) generate +begin + rel_early_congr_cl(2 TO 6) <= rel_addr_early(64-(dc_size-3) to 63-cl_size-1); +rel_early_congr_cl(7) <= rel_addr_early(63-cl_size) or spr_xucr0_cls; +end generate cl64size; +cl32size : if (cl_size=5) generate +begin + rel_early_congr_cl(2 TO 5) <= rel_addr_early(64-(dc_size-3) to 63-cl_size-2); +rel_early_congr_cl(6) <= rel_addr_early(63-cl_size-1) or spr_xucr0_cls; +rel_early_congr_cl(7) <= rel_addr_early(63-cl_size); +end generate cl32size; +ex2_congr_cl_d <= ex1_congr_cl; +ex3_congr_cl_d <= ex2_congr_cl_q; +ex4_congr_cl_d <= ex3_congr_cl_q; +ex5_congr_cl_d <= ex4_congr_cl_q; +ex6_congr_cl_d <= ex5_congr_cl_q; +with rel_in_progress select + rel_congr_cl_d <= rel_early_congr_cl when '1', + dcpar_err_congr_cl when others; +rel_val_stg2_d <= rel_val_stg1; +rel_val_clr_d <= rel_val_stg2_q or dcpar_err_stg2_q; +rel_val_stg4_d <= rel_val_stg3; +rel_val_stg4 <= rel_val_stg4_q and not rel4_recirc_val; +rel_val_set <= rel_val_stg4 and rel_set_val; +rel_binv_stg4_d <= rel_back_inval; +rel_lock_set_d <= rel_lock_en; +rel_l1dump_cslc_d <= rel_l1dump_cslc; +rel_no_ovr_lock <= rel_wayA_set or rel_wayB_set or rel_wayC_set or rel_wayD_set or + rel_wayE_set or rel_wayF_set or rel_wayG_set or rel_wayH_set; +rel_lock_lost <= rel_lock_set_q and rel_val_stg4 and rel_no_ovr_lock and rel_binv_stg4_q and not rel_set_val; +rel_watch_set_d <= rel_watch_en; +rel_thrd_id_d <= rel_thrd_id; +rel_watch_lost <= gate(rel_thrd_id_q, (rel_watch_set_q and rel_val_stg4 and rel_binv_stg4_q and not rel_set_val)); +rel_val_stg24 <= rel_val_stg2_q or rel_val_set or dcpar_err_stg2_q; +rel_val_stgu_d <= rel_val_stg24; +rel_port_wren_d <= rel_val_stgu_q; +rel_port_upd_d <= rel_val_stgu_q; +rel_in_prog_stg1_d <= ldq_rel1_early_v or ldq_rel3_early_v; +rel_in_prog_stg2_d <= rel_in_prog_stg1_q; +rel_in_prog_stg3_d <= rel_in_prog_stg2_q; +rel_in_prog_stg4_d <= rel_in_prog_stg3_q; +rel_in_prog_stg5_d <= rel_in_prog_stg4_q; +rel_in_progress <= ldq_rel1_early_v or ldq_rel3_early_v or rel_in_prog_stg1_q or rel_in_prog_stg2_q or + rel_in_prog_stg3_q or rel_in_prog_stg4_q or rel_in_prog_stg5_q; +rel_in_progress_d <= rel_in_progress; +back_inval_stg3_d <= back_inval_stg2; +back_inval_stg4_d <= back_inval_stg3_q; +back_inval_stg5_d <= back_inval_stg4_q; +ex2_thrd_id_d <= ex1_thrd_id; +ex3_store_instr_d <= ex2_store_instr and not ex2_stg_flush; +ex3_flush_cline_d <= ex2_is_inval_op and not ex2_stg_flush; +ex3_lock_set_d <= ex2_lock_set and not ex2_stg_flush; +ex4_lock_set_d <= ex3_lock_set_q and not ex3_stg_flush; +ex5_lock_set_d <= ex4_lock_set_q and not ex4_stg_flush; +ex3_lock_clr_d <= ex2_lock_clr and not ex2_stg_flush; +ex3_thrd_id_d <= ex2_thrd_id_q; +ex3_watch_set_d <= ex2_ldawx_instr and not ex2_stg_flush; +ex3_watch_clr_d <= ex2_wclr_instr and not ex2_stg_flush; +ex2_watch_clr_all <= ex2_wclr_instr and not ex2_l_fld(0); +ex2_watch_clr_one <= ex2_wclr_instr and ex2_l_fld(0); +ex3_watch_clr_all_d <= ex2_watch_clr_all and not ex2_stg_flush; +ex3_watch_chk_d <= ex2_wchk_val and not ex2_stg_flush; +ex3_xuop_val_d <= (ex2_lock_clr or ex2_lock_set or ex2_ldawx_instr or ex2_watch_clr_one or ex2_store_instr) and not ex2_stg_flush; +ex4_l_fld_b1_d <= ex3_l_fld_b1_q; +ex3_watch_clr_all <= gate(ex3_thrd_id_q, ex3_watch_clr_all_q); +ex4_wclr_all_val_d <= ex3_watch_clr_all_q and not ex3_stg_flush; +ex5_wclr_all_val_d <= ex4_wclr_all_val_q and not ex4_stg_flush; +ex6_wclr_all_val_d <= ex5_wclr_all_val_q and not ex5_stg_flush; +ex3_xuop_val <= ((ex3_xuop_val_q and ex3_c_acc) or ex3_flush_cline_q) and not spr_xucr0_dcdis; +ex4_xuop_val_d <= (ex3_xuop_val or ex3_watch_clr_all_q) and not ex3_stg_flush; +ex4_watch_clr_all_d <= gate(ex3_watch_clr_all, (not (ex3_stg_flush or spr_xucr0_dcdis))); +ex4_watch_chk_d <= ex3_watch_chk_q and not ex3_stg_flush; +ex4_watch_set_d <= ex3_watch_set_q and not ex3_stg_flush; +ex5_watch_set_d <= ex4_watch_set_q and not ex4_stg_flush; +ex3_xuop_upd_dir <= ex3_flush_cline_q or ex3_lock_clr_q or ex3_lock_set_q or ex3_watch_set_q or ex3_watch_clr_q; +binv3_ex3_xuop_upd <= back_inval_stg3_q or ex3_xuop_val; +binv4_ex4_xuop_upd_d <= binv3_ex3_xuop_upd or ((ex3_xuop_val or ex3_watch_clr_all_q) and not ex3_stg_flush); +ex3_dir_acc_val <= ex3_cache_acc and not ex3_watch_clr_all_q; +binv3_ex3_dir_val <= back_inval_stg3_q or ex3_dir_acc_val; +binv4_ex4_dir_val_d <= back_inval_stg3_q or (ex3_dir_acc_val and not ex3_stg_flush); +ex4_instr_enc_d(0) <= ex3_watch_clr_q; +ex4_instr_enc_d(1) <= back_inval_stg3_q or ex3_lock_set_q or ex3_lock_clr_q or ex3_watch_set_q; +ex4_instr_enc_d(2) <= back_inval_stg3_q or ex3_store_instr_q or ex3_watch_set_q; +ex4_instr_enc_d(3) <= back_inval_stg3_q or ex3_lock_clr_q or ex3_flush_cline_q or ex3_watch_clr_all_q; +ex4_xuop_val <= ex4_xuop_val_q and not ex4_stg_flush; +ex4_thrd_id_d <= ex3_thrd_id_q; +ex5_xuop_val_d <= ex4_xuop_val; +ex5_xuop_val <= ex5_xuop_val_q and not ex5_stg_flush; +ex5_xuop_p0_upd_d <= ex4_xuop_val; +ex5_watch_chk_d <= ex4_watch_chk_q and not ex4_stg_flush; +ex5_thrd_id_d <= ex4_thrd_id_q; +rel24_congr_cl_d <= rel_congr_cl_q; +relu_congr_cl_d <= rel24_congr_cl_q; +relu_s_congr_cl_d <= relu_congr_cl_q; +ex6_ld_valid_d <= ex5_load_op_hit and not ex5_stg_flush; +with ex2_congr_cl_q select + arr_wayA_val <= + congr_cl0_wA_q when "000000", + congr_cl1_wA_q when "000001", + congr_cl2_wA_q when "000010", + congr_cl3_wA_q when "000011", + congr_cl4_wA_q when "000100", + congr_cl5_wA_q when "000101", + congr_cl6_wA_q when "000110", + congr_cl7_wA_q when "000111", + congr_cl8_wA_q when "001000", + congr_cl9_wA_q when "001001", + congr_cl10_wA_q when "001010", + congr_cl11_wA_q when "001011", + congr_cl12_wA_q when "001100", + congr_cl13_wA_q when "001101", + congr_cl14_wA_q when "001110", + congr_cl15_wA_q when "001111", + congr_cl16_wA_q when "010000", + congr_cl17_wA_q when "010001", + congr_cl18_wA_q when "010010", + congr_cl19_wA_q when "010011", + congr_cl20_wA_q when "010100", + congr_cl21_wA_q when "010101", + congr_cl22_wA_q when "010110", + congr_cl23_wA_q when "010111", + congr_cl24_wA_q when "011000", + congr_cl25_wA_q when "011001", + congr_cl26_wA_q when "011010", + congr_cl27_wA_q when "011011", + congr_cl28_wA_q when "011100", + congr_cl29_wA_q when "011101", + congr_cl30_wA_q when "011110", + congr_cl31_wA_q when "011111", + congr_cl32_wA_q when "100000", + congr_cl33_wA_q when "100001", + congr_cl34_wA_q when "100010", + congr_cl35_wA_q when "100011", + congr_cl36_wA_q when "100100", + congr_cl37_wA_q when "100101", + congr_cl38_wA_q when "100110", + congr_cl39_wA_q when "100111", + congr_cl40_wA_q when "101000", + congr_cl41_wA_q when "101001", + congr_cl42_wA_q when "101010", + congr_cl43_wA_q when "101011", + congr_cl44_wA_q when "101100", + congr_cl45_wA_q when "101101", + congr_cl46_wA_q when "101110", + congr_cl47_wA_q when "101111", + congr_cl48_wA_q when "110000", + congr_cl49_wA_q when "110001", + congr_cl50_wA_q when "110010", + congr_cl51_wA_q when "110011", + congr_cl52_wA_q when "110100", + congr_cl53_wA_q when "110101", + congr_cl54_wA_q when "110110", + congr_cl55_wA_q when "110111", + congr_cl56_wA_q when "111000", + congr_cl57_wA_q when "111001", + congr_cl58_wA_q when "111010", + congr_cl59_wA_q when "111011", + congr_cl60_wA_q when "111100", + congr_cl61_wA_q when "111101", + congr_cl62_wA_q when "111110", + congr_cl63_wA_q when others; +p0_arr_wayA_rd <= arr_wayA_val; +with ex2_congr_cl_q select + arr_wayB_val <= + congr_cl0_wB_q when "000000", + congr_cl1_wB_q when "000001", + congr_cl2_wB_q when "000010", + congr_cl3_wB_q when "000011", + congr_cl4_wB_q when "000100", + congr_cl5_wB_q when "000101", + congr_cl6_wB_q when "000110", + congr_cl7_wB_q when "000111", + congr_cl8_wB_q when "001000", + congr_cl9_wB_q when "001001", + congr_cl10_wB_q when "001010", + congr_cl11_wB_q when "001011", + congr_cl12_wB_q when "001100", + congr_cl13_wB_q when "001101", + congr_cl14_wB_q when "001110", + congr_cl15_wB_q when "001111", + congr_cl16_wB_q when "010000", + congr_cl17_wB_q when "010001", + congr_cl18_wB_q when "010010", + congr_cl19_wB_q when "010011", + congr_cl20_wB_q when "010100", + congr_cl21_wB_q when "010101", + congr_cl22_wB_q when "010110", + congr_cl23_wB_q when "010111", + congr_cl24_wB_q when "011000", + congr_cl25_wB_q when "011001", + congr_cl26_wB_q when "011010", + congr_cl27_wB_q when "011011", + congr_cl28_wB_q when "011100", + congr_cl29_wB_q when "011101", + congr_cl30_wB_q when "011110", + congr_cl31_wB_q when "011111", + congr_cl32_wB_q when "100000", + congr_cl33_wB_q when "100001", + congr_cl34_wB_q when "100010", + congr_cl35_wB_q when "100011", + congr_cl36_wB_q when "100100", + congr_cl37_wB_q when "100101", + congr_cl38_wB_q when "100110", + congr_cl39_wB_q when "100111", + congr_cl40_wB_q when "101000", + congr_cl41_wB_q when "101001", + congr_cl42_wB_q when "101010", + congr_cl43_wB_q when "101011", + congr_cl44_wB_q when "101100", + congr_cl45_wB_q when "101101", + congr_cl46_wB_q when "101110", + congr_cl47_wB_q when "101111", + congr_cl48_wB_q when "110000", + congr_cl49_wB_q when "110001", + congr_cl50_wB_q when "110010", + congr_cl51_wB_q when "110011", + congr_cl52_wB_q when "110100", + congr_cl53_wB_q when "110101", + congr_cl54_wB_q when "110110", + congr_cl55_wB_q when "110111", + congr_cl56_wB_q when "111000", + congr_cl57_wB_q when "111001", + congr_cl58_wB_q when "111010", + congr_cl59_wB_q when "111011", + congr_cl60_wB_q when "111100", + congr_cl61_wB_q when "111101", + congr_cl62_wB_q when "111110", + congr_cl63_wB_q when others; +p0_arr_wayB_rd <= arr_wayB_val; +with ex2_congr_cl_q select + arr_wayC_val <= + congr_cl0_wC_q when "000000", + congr_cl1_wC_q when "000001", + congr_cl2_wC_q when "000010", + congr_cl3_wC_q when "000011", + congr_cl4_wC_q when "000100", + congr_cl5_wC_q when "000101", + congr_cl6_wC_q when "000110", + congr_cl7_wC_q when "000111", + congr_cl8_wC_q when "001000", + congr_cl9_wC_q when "001001", + congr_cl10_wC_q when "001010", + congr_cl11_wC_q when "001011", + congr_cl12_wC_q when "001100", + congr_cl13_wC_q when "001101", + congr_cl14_wC_q when "001110", + congr_cl15_wC_q when "001111", + congr_cl16_wC_q when "010000", + congr_cl17_wC_q when "010001", + congr_cl18_wC_q when "010010", + congr_cl19_wC_q when "010011", + congr_cl20_wC_q when "010100", + congr_cl21_wC_q when "010101", + congr_cl22_wC_q when "010110", + congr_cl23_wC_q when "010111", + congr_cl24_wC_q when "011000", + congr_cl25_wC_q when "011001", + congr_cl26_wC_q when "011010", + congr_cl27_wC_q when "011011", + congr_cl28_wC_q when "011100", + congr_cl29_wC_q when "011101", + congr_cl30_wC_q when "011110", + congr_cl31_wC_q when "011111", + congr_cl32_wC_q when "100000", + congr_cl33_wC_q when "100001", + congr_cl34_wC_q when "100010", + congr_cl35_wC_q when "100011", + congr_cl36_wC_q when "100100", + congr_cl37_wC_q when "100101", + congr_cl38_wC_q when "100110", + congr_cl39_wC_q when "100111", + congr_cl40_wC_q when "101000", + congr_cl41_wC_q when "101001", + congr_cl42_wC_q when "101010", + congr_cl43_wC_q when "101011", + congr_cl44_wC_q when "101100", + congr_cl45_wC_q when "101101", + congr_cl46_wC_q when "101110", + congr_cl47_wC_q when "101111", + congr_cl48_wC_q when "110000", + congr_cl49_wC_q when "110001", + congr_cl50_wC_q when "110010", + congr_cl51_wC_q when "110011", + congr_cl52_wC_q when "110100", + congr_cl53_wC_q when "110101", + congr_cl54_wC_q when "110110", + congr_cl55_wC_q when "110111", + congr_cl56_wC_q when "111000", + congr_cl57_wC_q when "111001", + congr_cl58_wC_q when "111010", + congr_cl59_wC_q when "111011", + congr_cl60_wC_q when "111100", + congr_cl61_wC_q when "111101", + congr_cl62_wC_q when "111110", + congr_cl63_wC_q when others; +p0_arr_wayC_rd <= arr_wayC_val; +with ex2_congr_cl_q select + arr_wayD_val <= + congr_cl0_wD_q when "000000", + congr_cl1_wD_q when "000001", + congr_cl2_wD_q when "000010", + congr_cl3_wD_q when "000011", + congr_cl4_wD_q when "000100", + congr_cl5_wD_q when "000101", + congr_cl6_wD_q when "000110", + congr_cl7_wD_q when "000111", + congr_cl8_wD_q when "001000", + congr_cl9_wD_q when "001001", + congr_cl10_wD_q when "001010", + congr_cl11_wD_q when "001011", + congr_cl12_wD_q when "001100", + congr_cl13_wD_q when "001101", + congr_cl14_wD_q when "001110", + congr_cl15_wD_q when "001111", + congr_cl16_wD_q when "010000", + congr_cl17_wD_q when "010001", + congr_cl18_wD_q when "010010", + congr_cl19_wD_q when "010011", + congr_cl20_wD_q when "010100", + congr_cl21_wD_q when "010101", + congr_cl22_wD_q when "010110", + congr_cl23_wD_q when "010111", + congr_cl24_wD_q when "011000", + congr_cl25_wD_q when "011001", + congr_cl26_wD_q when "011010", + congr_cl27_wD_q when "011011", + congr_cl28_wD_q when "011100", + congr_cl29_wD_q when "011101", + congr_cl30_wD_q when "011110", + congr_cl31_wD_q when "011111", + congr_cl32_wD_q when "100000", + congr_cl33_wD_q when "100001", + congr_cl34_wD_q when "100010", + congr_cl35_wD_q when "100011", + congr_cl36_wD_q when "100100", + congr_cl37_wD_q when "100101", + congr_cl38_wD_q when "100110", + congr_cl39_wD_q when "100111", + congr_cl40_wD_q when "101000", + congr_cl41_wD_q when "101001", + congr_cl42_wD_q when "101010", + congr_cl43_wD_q when "101011", + congr_cl44_wD_q when "101100", + congr_cl45_wD_q when "101101", + congr_cl46_wD_q when "101110", + congr_cl47_wD_q when "101111", + congr_cl48_wD_q when "110000", + congr_cl49_wD_q when "110001", + congr_cl50_wD_q when "110010", + congr_cl51_wD_q when "110011", + congr_cl52_wD_q when "110100", + congr_cl53_wD_q when "110101", + congr_cl54_wD_q when "110110", + congr_cl55_wD_q when "110111", + congr_cl56_wD_q when "111000", + congr_cl57_wD_q when "111001", + congr_cl58_wD_q when "111010", + congr_cl59_wD_q when "111011", + congr_cl60_wD_q when "111100", + congr_cl61_wD_q when "111101", + congr_cl62_wD_q when "111110", + congr_cl63_wD_q when others; +p0_arr_wayD_rd <= arr_wayD_val; +with ex2_congr_cl_q select + arr_wayE_val <= + congr_cl0_wE_q when "000000", + congr_cl1_wE_q when "000001", + congr_cl2_wE_q when "000010", + congr_cl3_wE_q when "000011", + congr_cl4_wE_q when "000100", + congr_cl5_wE_q when "000101", + congr_cl6_wE_q when "000110", + congr_cl7_wE_q when "000111", + congr_cl8_wE_q when "001000", + congr_cl9_wE_q when "001001", + congr_cl10_wE_q when "001010", + congr_cl11_wE_q when "001011", + congr_cl12_wE_q when "001100", + congr_cl13_wE_q when "001101", + congr_cl14_wE_q when "001110", + congr_cl15_wE_q when "001111", + congr_cl16_wE_q when "010000", + congr_cl17_wE_q when "010001", + congr_cl18_wE_q when "010010", + congr_cl19_wE_q when "010011", + congr_cl20_wE_q when "010100", + congr_cl21_wE_q when "010101", + congr_cl22_wE_q when "010110", + congr_cl23_wE_q when "010111", + congr_cl24_wE_q when "011000", + congr_cl25_wE_q when "011001", + congr_cl26_wE_q when "011010", + congr_cl27_wE_q when "011011", + congr_cl28_wE_q when "011100", + congr_cl29_wE_q when "011101", + congr_cl30_wE_q when "011110", + congr_cl31_wE_q when "011111", + congr_cl32_wE_q when "100000", + congr_cl33_wE_q when "100001", + congr_cl34_wE_q when "100010", + congr_cl35_wE_q when "100011", + congr_cl36_wE_q when "100100", + congr_cl37_wE_q when "100101", + congr_cl38_wE_q when "100110", + congr_cl39_wE_q when "100111", + congr_cl40_wE_q when "101000", + congr_cl41_wE_q when "101001", + congr_cl42_wE_q when "101010", + congr_cl43_wE_q when "101011", + congr_cl44_wE_q when "101100", + congr_cl45_wE_q when "101101", + congr_cl46_wE_q when "101110", + congr_cl47_wE_q when "101111", + congr_cl48_wE_q when "110000", + congr_cl49_wE_q when "110001", + congr_cl50_wE_q when "110010", + congr_cl51_wE_q when "110011", + congr_cl52_wE_q when "110100", + congr_cl53_wE_q when "110101", + congr_cl54_wE_q when "110110", + congr_cl55_wE_q when "110111", + congr_cl56_wE_q when "111000", + congr_cl57_wE_q when "111001", + congr_cl58_wE_q when "111010", + congr_cl59_wE_q when "111011", + congr_cl60_wE_q when "111100", + congr_cl61_wE_q when "111101", + congr_cl62_wE_q when "111110", + congr_cl63_wE_q when others; +p0_arr_wayE_rd <= arr_wayE_val; +with ex2_congr_cl_q select + arr_wayF_val <= + congr_cl0_wF_q when "000000", + congr_cl1_wF_q when "000001", + congr_cl2_wF_q when "000010", + congr_cl3_wF_q when "000011", + congr_cl4_wF_q when "000100", + congr_cl5_wF_q when "000101", + congr_cl6_wF_q when "000110", + congr_cl7_wF_q when "000111", + congr_cl8_wF_q when "001000", + congr_cl9_wF_q when "001001", + congr_cl10_wF_q when "001010", + congr_cl11_wF_q when "001011", + congr_cl12_wF_q when "001100", + congr_cl13_wF_q when "001101", + congr_cl14_wF_q when "001110", + congr_cl15_wF_q when "001111", + congr_cl16_wF_q when "010000", + congr_cl17_wF_q when "010001", + congr_cl18_wF_q when "010010", + congr_cl19_wF_q when "010011", + congr_cl20_wF_q when "010100", + congr_cl21_wF_q when "010101", + congr_cl22_wF_q when "010110", + congr_cl23_wF_q when "010111", + congr_cl24_wF_q when "011000", + congr_cl25_wF_q when "011001", + congr_cl26_wF_q when "011010", + congr_cl27_wF_q when "011011", + congr_cl28_wF_q when "011100", + congr_cl29_wF_q when "011101", + congr_cl30_wF_q when "011110", + congr_cl31_wF_q when "011111", + congr_cl32_wF_q when "100000", + congr_cl33_wF_q when "100001", + congr_cl34_wF_q when "100010", + congr_cl35_wF_q when "100011", + congr_cl36_wF_q when "100100", + congr_cl37_wF_q when "100101", + congr_cl38_wF_q when "100110", + congr_cl39_wF_q when "100111", + congr_cl40_wF_q when "101000", + congr_cl41_wF_q when "101001", + congr_cl42_wF_q when "101010", + congr_cl43_wF_q when "101011", + congr_cl44_wF_q when "101100", + congr_cl45_wF_q when "101101", + congr_cl46_wF_q when "101110", + congr_cl47_wF_q when "101111", + congr_cl48_wF_q when "110000", + congr_cl49_wF_q when "110001", + congr_cl50_wF_q when "110010", + congr_cl51_wF_q when "110011", + congr_cl52_wF_q when "110100", + congr_cl53_wF_q when "110101", + congr_cl54_wF_q when "110110", + congr_cl55_wF_q when "110111", + congr_cl56_wF_q when "111000", + congr_cl57_wF_q when "111001", + congr_cl58_wF_q when "111010", + congr_cl59_wF_q when "111011", + congr_cl60_wF_q when "111100", + congr_cl61_wF_q when "111101", + congr_cl62_wF_q when "111110", + congr_cl63_wF_q when others; +p0_arr_wayF_rd <= arr_wayF_val; +with ex2_congr_cl_q select + arr_wayG_val <= + congr_cl0_wG_q when "000000", + congr_cl1_wG_q when "000001", + congr_cl2_wG_q when "000010", + congr_cl3_wG_q when "000011", + congr_cl4_wG_q when "000100", + congr_cl5_wG_q when "000101", + congr_cl6_wG_q when "000110", + congr_cl7_wG_q when "000111", + congr_cl8_wG_q when "001000", + congr_cl9_wG_q when "001001", + congr_cl10_wG_q when "001010", + congr_cl11_wG_q when "001011", + congr_cl12_wG_q when "001100", + congr_cl13_wG_q when "001101", + congr_cl14_wG_q when "001110", + congr_cl15_wG_q when "001111", + congr_cl16_wG_q when "010000", + congr_cl17_wG_q when "010001", + congr_cl18_wG_q when "010010", + congr_cl19_wG_q when "010011", + congr_cl20_wG_q when "010100", + congr_cl21_wG_q when "010101", + congr_cl22_wG_q when "010110", + congr_cl23_wG_q when "010111", + congr_cl24_wG_q when "011000", + congr_cl25_wG_q when "011001", + congr_cl26_wG_q when "011010", + congr_cl27_wG_q when "011011", + congr_cl28_wG_q when "011100", + congr_cl29_wG_q when "011101", + congr_cl30_wG_q when "011110", + congr_cl31_wG_q when "011111", + congr_cl32_wG_q when "100000", + congr_cl33_wG_q when "100001", + congr_cl34_wG_q when "100010", + congr_cl35_wG_q when "100011", + congr_cl36_wG_q when "100100", + congr_cl37_wG_q when "100101", + congr_cl38_wG_q when "100110", + congr_cl39_wG_q when "100111", + congr_cl40_wG_q when "101000", + congr_cl41_wG_q when "101001", + congr_cl42_wG_q when "101010", + congr_cl43_wG_q when "101011", + congr_cl44_wG_q when "101100", + congr_cl45_wG_q when "101101", + congr_cl46_wG_q when "101110", + congr_cl47_wG_q when "101111", + congr_cl48_wG_q when "110000", + congr_cl49_wG_q when "110001", + congr_cl50_wG_q when "110010", + congr_cl51_wG_q when "110011", + congr_cl52_wG_q when "110100", + congr_cl53_wG_q when "110101", + congr_cl54_wG_q when "110110", + congr_cl55_wG_q when "110111", + congr_cl56_wG_q when "111000", + congr_cl57_wG_q when "111001", + congr_cl58_wG_q when "111010", + congr_cl59_wG_q when "111011", + congr_cl60_wG_q when "111100", + congr_cl61_wG_q when "111101", + congr_cl62_wG_q when "111110", + congr_cl63_wG_q when others; +p0_arr_wayG_rd <= arr_wayG_val; +with ex2_congr_cl_q select + arr_wayH_val <= + congr_cl0_wH_q when "000000", + congr_cl1_wH_q when "000001", + congr_cl2_wH_q when "000010", + congr_cl3_wH_q when "000011", + congr_cl4_wH_q when "000100", + congr_cl5_wH_q when "000101", + congr_cl6_wH_q when "000110", + congr_cl7_wH_q when "000111", + congr_cl8_wH_q when "001000", + congr_cl9_wH_q when "001001", + congr_cl10_wH_q when "001010", + congr_cl11_wH_q when "001011", + congr_cl12_wH_q when "001100", + congr_cl13_wH_q when "001101", + congr_cl14_wH_q when "001110", + congr_cl15_wH_q when "001111", + congr_cl16_wH_q when "010000", + congr_cl17_wH_q when "010001", + congr_cl18_wH_q when "010010", + congr_cl19_wH_q when "010011", + congr_cl20_wH_q when "010100", + congr_cl21_wH_q when "010101", + congr_cl22_wH_q when "010110", + congr_cl23_wH_q when "010111", + congr_cl24_wH_q when "011000", + congr_cl25_wH_q when "011001", + congr_cl26_wH_q when "011010", + congr_cl27_wH_q when "011011", + congr_cl28_wH_q when "011100", + congr_cl29_wH_q when "011101", + congr_cl30_wH_q when "011110", + congr_cl31_wH_q when "011111", + congr_cl32_wH_q when "100000", + congr_cl33_wH_q when "100001", + congr_cl34_wH_q when "100010", + congr_cl35_wH_q when "100011", + congr_cl36_wH_q when "100100", + congr_cl37_wH_q when "100101", + congr_cl38_wH_q when "100110", + congr_cl39_wH_q when "100111", + congr_cl40_wH_q when "101000", + congr_cl41_wH_q when "101001", + congr_cl42_wH_q when "101010", + congr_cl43_wH_q when "101011", + congr_cl44_wH_q when "101100", + congr_cl45_wH_q when "101101", + congr_cl46_wH_q when "101110", + congr_cl47_wH_q when "101111", + congr_cl48_wH_q when "110000", + congr_cl49_wH_q when "110001", + congr_cl50_wH_q when "110010", + congr_cl51_wH_q when "110011", + congr_cl52_wH_q when "110100", + congr_cl53_wH_q when "110101", + congr_cl54_wH_q when "110110", + congr_cl55_wH_q when "110111", + congr_cl56_wH_q when "111000", + congr_cl57_wH_q when "111001", + congr_cl58_wH_q when "111010", + congr_cl59_wH_q when "111011", + congr_cl60_wH_q when "111100", + congr_cl61_wH_q when "111101", + congr_cl62_wH_q when "111110", + congr_cl63_wH_q when others; +p0_arr_wayH_rd <= arr_wayH_val; +congr_cl_ex2_ex3_cmp_d <= (ex1_congr_cl = ex2_congr_cl_q); +congr_cl_ex2_ex4_cmp_d <= (ex1_congr_cl = ex3_congr_cl_q); +congr_cl_ex2_ex5_cmp_d <= (ex1_congr_cl = ex4_congr_cl_q); +congr_cl_ex2_ex6_cmp_d <= (ex1_congr_cl = ex5_congr_cl_q); +congr_cl_ex2_relu_cmp_d <= (ex1_congr_cl = rel24_congr_cl_q); +congr_cl_ex2_relu_s_cmp_d <= (ex1_congr_cl = relu_congr_cl_q); +congr_cl_ex2_rel_upd_cmp_d <= (ex1_congr_cl = relu_s_congr_cl_q); +congr_cl_ex2_p0_cmp <= congr_cl_ex2_ex6_cmp_q and p0_wren_cpy_q; +congr_cl_ex2_p1_cmp <= congr_cl_ex2_rel_upd_cmp_q and p1_wren_cpy_q; +ex3_thrd_m_d <= (ex1_thrd_id = ex2_thrd_id_q); +ex4_thrd_m_d <= (ex1_thrd_id = ex3_thrd_id_q); +ex5_thrd_m_d <= (ex1_thrd_id = ex4_thrd_id_q); +ex6_thrd_m_d <= (ex1_thrd_id = ex5_thrd_id_q); +congr_cl_ex2_ex3_m <= congr_cl_ex2_ex3_cmp_q and ((ex3_xuop_val and ex3_thrd_m_q) or back_inval_stg3_q) and not inv2_val_q; +congr_cl_ex2_ex4_m <= congr_cl_ex2_ex4_cmp_q and ((ex4_xuop_val_q and ex4_thrd_m_q) or back_inval_stg4_q) and not inv2_val_q; +congr_cl_ex2_ex5_m <= congr_cl_ex2_ex5_cmp_q and ((ex5_xuop_p0_upd_q and ex5_thrd_m_q) or back_inval_stg5_q) and not inv2_val_q; +congr_cl_ex2_relu_m <= congr_cl_ex2_relu_cmp_q and rel_val_stgu_q; +congr_cl_ex2_relu_s_m <= congr_cl_ex2_relu_s_cmp_q and p1_upd_val; +congr_cl_ex2_wayA_byp(1) <= congr_cl_ex2_ex3_m and ex3_wayA_hit; +congr_cl_ex2_wayA_byp(2) <= congr_cl_ex2_relu_m and reload_wayA_upd_q; +congr_cl_ex2_wayA_byp(3) <= congr_cl_ex2_ex4_m and binv_wayA_upd_q; +congr_cl_ex2_wayA_byp(4) <= congr_cl_ex2_relu_s_m and reload_wayA_upd2_q; +congr_cl_ex2_wayA_byp(5) <= congr_cl_ex2_ex5_m and binv_wayA_upd2_q; +congr_cl_ex2_wayA_byp(6) <= congr_cl_ex2_p1_cmp and reload_wayA_upd3_q; +congr_cl_ex2_wayA_byp(7) <= congr_cl_ex2_p0_cmp and binv_wayA_upd3_q; +ex3_wayA_fxubyp_val_d <= congr_cl_ex2_wayA_byp(1) or congr_cl_ex2_wayA_byp(3) or + congr_cl_ex2_wayA_byp(5) or congr_cl_ex2_wayA_byp(7); +ex3_wayA_relbyp_val_d <= congr_cl_ex2_wayA_byp(2) or congr_cl_ex2_wayA_byp(4) or + congr_cl_ex2_wayA_byp(6); +ex4_wayA_fxubyp_val_d <= ex3_wayA_fxubyp_val_q; +ex4_wayA_relbyp_val_d <= ex3_wayA_relbyp_val_q; +ex4_wayA_byp_sel <= ex4_wayA_fxubyp_val_q & ex4_wayA_relbyp_val_q; +congr_cl_ex2_wayA_sel(2) <= congr_cl_ex2_wayA_byp(2); +congr_cl_ex2_wayA_sel(3) <= congr_cl_ex2_wayA_byp(3) and not congr_cl_ex2_wayA_byp(2); +congr_cl_ex2_wayA_sel(4) <= congr_cl_ex2_wayA_byp(4) and not or_reduce(congr_cl_ex2_wayA_byp(2 to 3)); +congr_cl_ex2_wayA_sel(5) <= congr_cl_ex2_wayA_byp(5) and not or_reduce(congr_cl_ex2_wayA_byp(2 to 4)); +congr_cl_ex2_wayA_sel(6) <= congr_cl_ex2_wayA_byp(6) and not or_reduce(congr_cl_ex2_wayA_byp(2 to 5)); +congr_cl_ex2_wayA_sel(7) <= congr_cl_ex2_wayA_byp(7) and not or_reduce(congr_cl_ex2_wayA_byp(2 to 6)); +wayA_late_sel <= or_reduce(congr_cl_ex2_wayA_byp(2 to 7)); +wayA_later_stg_pri <= gate(p0_arr_wayA_rd, not wayA_late_sel) or + gate(reload_wayA_q, congr_cl_ex2_wayA_sel(2)) or + gate(flush_wayA_q, congr_cl_ex2_wayA_sel(3)) or + gate(reload_wayA_data_q, congr_cl_ex2_wayA_sel(4)) or + gate(flush_wayA_data_q, congr_cl_ex2_wayA_sel(5)) or + gate(reload_wayA_data2_q, congr_cl_ex2_wayA_sel(6)) or + gate(flush_wayA_data2_q, congr_cl_ex2_wayA_sel(7)); +wayA_early_sel <= congr_cl_ex2_wayA_byp(1); +wayA_early_stg_pri <= flush_wayA_d; +wayA_stg_val <= (others=>(wayA_early_sel)); +wayA_stg_val_b <= (others=>(not(wayA_early_sel))); +wayA_val(0 TO 1) <= not wayA_val_b_q(0 to 1); +wayA_val(2 TO 5) <= not wayA_val_b_q(2 to 5); +wayA_val_b1 <= not wayA_val(0); +congr_cl_ex2_wayB_byp(1) <= congr_cl_ex2_ex3_m and ex3_wayB_hit; +congr_cl_ex2_wayB_byp(2) <= congr_cl_ex2_relu_m and reload_wayB_upd_q; +congr_cl_ex2_wayB_byp(3) <= congr_cl_ex2_ex4_m and binv_wayB_upd_q; +congr_cl_ex2_wayB_byp(4) <= congr_cl_ex2_relu_s_m and reload_wayB_upd2_q; +congr_cl_ex2_wayB_byp(5) <= congr_cl_ex2_ex5_m and binv_wayB_upd2_q; +congr_cl_ex2_wayB_byp(6) <= congr_cl_ex2_p1_cmp and reload_wayB_upd3_q; +congr_cl_ex2_wayB_byp(7) <= congr_cl_ex2_p0_cmp and binv_wayB_upd3_q; +ex3_wayB_fxubyp_val_d <= congr_cl_ex2_wayB_byp(1) or congr_cl_ex2_wayB_byp(3) or + congr_cl_ex2_wayB_byp(5) or congr_cl_ex2_wayB_byp(7); +ex3_wayB_relbyp_val_d <= congr_cl_ex2_wayB_byp(2) or congr_cl_ex2_wayB_byp(4) or + congr_cl_ex2_wayB_byp(6); +ex4_wayB_fxubyp_val_d <= ex3_wayB_fxubyp_val_q; +ex4_wayB_relbyp_val_d <= ex3_wayB_relbyp_val_q; +ex4_wayB_byp_sel <= ex4_wayB_fxubyp_val_q & ex4_wayB_relbyp_val_q; +congr_cl_ex2_wayB_sel(2) <= congr_cl_ex2_wayB_byp(2); +congr_cl_ex2_wayB_sel(3) <= congr_cl_ex2_wayB_byp(3) and not congr_cl_ex2_wayB_byp(2); +congr_cl_ex2_wayB_sel(4) <= congr_cl_ex2_wayB_byp(4) and not or_reduce(congr_cl_ex2_wayB_byp(2 to 3)); +congr_cl_ex2_wayB_sel(5) <= congr_cl_ex2_wayB_byp(5) and not or_reduce(congr_cl_ex2_wayB_byp(2 to 4)); +congr_cl_ex2_wayB_sel(6) <= congr_cl_ex2_wayB_byp(6) and not or_reduce(congr_cl_ex2_wayB_byp(2 to 5)); +congr_cl_ex2_wayB_sel(7) <= congr_cl_ex2_wayB_byp(7) and not or_reduce(congr_cl_ex2_wayB_byp(2 to 6)); +wayB_late_sel <= or_reduce(congr_cl_ex2_wayB_byp(2 to 7)); +wayB_later_stg_pri <= gate(p0_arr_wayB_rd, not wayB_late_sel) or + gate(reload_wayB_q, congr_cl_ex2_wayB_sel(2)) or + gate(flush_wayB_q, congr_cl_ex2_wayB_sel(3)) or + gate(reload_wayB_data_q, congr_cl_ex2_wayB_sel(4)) or + gate(flush_wayB_data_q, congr_cl_ex2_wayB_sel(5)) or + gate(reload_wayB_data2_q, congr_cl_ex2_wayB_sel(6)) or + gate(flush_wayB_data2_q, congr_cl_ex2_wayB_sel(7)); +wayB_early_sel <= congr_cl_ex2_wayB_byp(1); +wayB_early_stg_pri <= flush_wayB_d; +wayB_stg_val <= (others=>(wayB_early_sel)); +wayB_stg_val_b <= (others=>(not(wayB_early_sel))); +wayB_val(0 TO 1) <= not wayB_val_b_q(0 to 1); +wayB_val(2 TO 5) <= not wayB_val_b_q(2 to 5); +wayB_val_b1 <= not wayB_val(0); +congr_cl_ex2_wayC_byp(1) <= congr_cl_ex2_ex3_m and ex3_wayC_hit; +congr_cl_ex2_wayC_byp(2) <= congr_cl_ex2_relu_m and reload_wayC_upd_q; +congr_cl_ex2_wayC_byp(3) <= congr_cl_ex2_ex4_m and binv_wayC_upd_q; +congr_cl_ex2_wayC_byp(4) <= congr_cl_ex2_relu_s_m and reload_wayC_upd2_q; +congr_cl_ex2_wayC_byp(5) <= congr_cl_ex2_ex5_m and binv_wayC_upd2_q; +congr_cl_ex2_wayC_byp(6) <= congr_cl_ex2_p1_cmp and reload_wayC_upd3_q; +congr_cl_ex2_wayC_byp(7) <= congr_cl_ex2_p0_cmp and binv_wayC_upd3_q; +ex3_wayC_fxubyp_val_d <= congr_cl_ex2_wayC_byp(1) or congr_cl_ex2_wayC_byp(3) or + congr_cl_ex2_wayC_byp(5) or congr_cl_ex2_wayC_byp(7); +ex3_wayC_relbyp_val_d <= congr_cl_ex2_wayC_byp(2) or congr_cl_ex2_wayC_byp(4) or + congr_cl_ex2_wayC_byp(6); +ex4_wayC_fxubyp_val_d <= ex3_wayC_fxubyp_val_q; +ex4_wayC_relbyp_val_d <= ex3_wayC_relbyp_val_q; +ex4_wayC_byp_sel <= ex4_wayC_fxubyp_val_q & ex4_wayC_relbyp_val_q; +congr_cl_ex2_wayC_sel(2) <= congr_cl_ex2_wayC_byp(2); +congr_cl_ex2_wayC_sel(3) <= congr_cl_ex2_wayC_byp(3) and not congr_cl_ex2_wayC_byp(2); +congr_cl_ex2_wayC_sel(4) <= congr_cl_ex2_wayC_byp(4) and not or_reduce(congr_cl_ex2_wayC_byp(2 to 3)); +congr_cl_ex2_wayC_sel(5) <= congr_cl_ex2_wayC_byp(5) and not or_reduce(congr_cl_ex2_wayC_byp(2 to 4)); +congr_cl_ex2_wayC_sel(6) <= congr_cl_ex2_wayC_byp(6) and not or_reduce(congr_cl_ex2_wayC_byp(2 to 5)); +congr_cl_ex2_wayC_sel(7) <= congr_cl_ex2_wayC_byp(7) and not or_reduce(congr_cl_ex2_wayC_byp(2 to 6)); +wayC_late_sel <= or_reduce(congr_cl_ex2_wayC_byp(2 to 7)); +wayC_later_stg_pri <= gate(p0_arr_wayC_rd, not wayC_late_sel) or + gate(reload_wayC_q, congr_cl_ex2_wayC_sel(2)) or + gate(flush_wayC_q, congr_cl_ex2_wayC_sel(3)) or + gate(reload_wayC_data_q, congr_cl_ex2_wayC_sel(4)) or + gate(flush_wayC_data_q, congr_cl_ex2_wayC_sel(5)) or + gate(reload_wayC_data2_q, congr_cl_ex2_wayC_sel(6)) or + gate(flush_wayC_data2_q, congr_cl_ex2_wayC_sel(7)); +wayC_early_sel <= congr_cl_ex2_wayC_byp(1); +wayC_early_stg_pri <= flush_wayC_d; +wayC_stg_val <= (others=>(wayC_early_sel)); +wayC_stg_val_b <= (others=>(not(wayC_early_sel))); +wayC_val(0 TO 1) <= not wayC_val_b_q(0 to 1); +wayC_val(2 TO 5) <= not wayC_val_b_q(2 to 5); +wayC_val_b1 <= not wayC_val(0); +congr_cl_ex2_wayD_byp(1) <= congr_cl_ex2_ex3_m and ex3_wayD_hit; +congr_cl_ex2_wayD_byp(2) <= congr_cl_ex2_relu_m and reload_wayD_upd_q; +congr_cl_ex2_wayD_byp(3) <= congr_cl_ex2_ex4_m and binv_wayD_upd_q; +congr_cl_ex2_wayD_byp(4) <= congr_cl_ex2_relu_s_m and reload_wayD_upd2_q; +congr_cl_ex2_wayD_byp(5) <= congr_cl_ex2_ex5_m and binv_wayD_upd2_q; +congr_cl_ex2_wayD_byp(6) <= congr_cl_ex2_p1_cmp and reload_wayD_upd3_q; +congr_cl_ex2_wayD_byp(7) <= congr_cl_ex2_p0_cmp and binv_wayD_upd3_q; +ex3_wayD_fxubyp_val_d <= congr_cl_ex2_wayD_byp(1) or congr_cl_ex2_wayD_byp(3) or + congr_cl_ex2_wayD_byp(5) or congr_cl_ex2_wayD_byp(7); +ex3_wayD_relbyp_val_d <= congr_cl_ex2_wayD_byp(2) or congr_cl_ex2_wayD_byp(4) or + congr_cl_ex2_wayD_byp(6); +ex4_wayD_fxubyp_val_d <= ex3_wayD_fxubyp_val_q; +ex4_wayD_relbyp_val_d <= ex3_wayD_relbyp_val_q; +ex4_wayD_byp_sel <= ex4_wayD_fxubyp_val_q & ex4_wayD_relbyp_val_q; +congr_cl_ex2_wayD_sel(2) <= congr_cl_ex2_wayD_byp(2); +congr_cl_ex2_wayD_sel(3) <= congr_cl_ex2_wayD_byp(3) and not congr_cl_ex2_wayD_byp(2); +congr_cl_ex2_wayD_sel(4) <= congr_cl_ex2_wayD_byp(4) and not or_reduce(congr_cl_ex2_wayD_byp(2 to 3)); +congr_cl_ex2_wayD_sel(5) <= congr_cl_ex2_wayD_byp(5) and not or_reduce(congr_cl_ex2_wayD_byp(2 to 4)); +congr_cl_ex2_wayD_sel(6) <= congr_cl_ex2_wayD_byp(6) and not or_reduce(congr_cl_ex2_wayD_byp(2 to 5)); +congr_cl_ex2_wayD_sel(7) <= congr_cl_ex2_wayD_byp(7) and not or_reduce(congr_cl_ex2_wayD_byp(2 to 6)); +wayD_late_sel <= or_reduce(congr_cl_ex2_wayD_byp(2 to 7)); +wayD_later_stg_pri <= gate(p0_arr_wayD_rd, not wayD_late_sel) or + gate(reload_wayD_q, congr_cl_ex2_wayD_sel(2)) or + gate(flush_wayD_q, congr_cl_ex2_wayD_sel(3)) or + gate(reload_wayD_data_q, congr_cl_ex2_wayD_sel(4)) or + gate(flush_wayD_data_q, congr_cl_ex2_wayD_sel(5)) or + gate(reload_wayD_data2_q, congr_cl_ex2_wayD_sel(6)) or + gate(flush_wayD_data2_q, congr_cl_ex2_wayD_sel(7)); +wayD_early_sel <= congr_cl_ex2_wayD_byp(1); +wayD_early_stg_pri <= flush_wayD_d; +wayD_stg_val <= (others=>(wayD_early_sel)); +wayD_stg_val_b <= (others=>(not(wayD_early_sel))); +wayD_val(0 TO 1) <= not wayD_val_b_q(0 to 1); +wayD_val(2 TO 5) <= not wayD_val_b_q(2 to 5); +wayD_val_b1 <= not wayD_val(0); +congr_cl_ex2_wayE_byp(1) <= congr_cl_ex2_ex3_m and ex3_wayE_hit; +congr_cl_ex2_wayE_byp(2) <= congr_cl_ex2_relu_m and reload_wayE_upd_q; +congr_cl_ex2_wayE_byp(3) <= congr_cl_ex2_ex4_m and binv_wayE_upd_q; +congr_cl_ex2_wayE_byp(4) <= congr_cl_ex2_relu_s_m and reload_wayE_upd2_q; +congr_cl_ex2_wayE_byp(5) <= congr_cl_ex2_ex5_m and binv_wayE_upd2_q; +congr_cl_ex2_wayE_byp(6) <= congr_cl_ex2_p1_cmp and reload_wayE_upd3_q; +congr_cl_ex2_wayE_byp(7) <= congr_cl_ex2_p0_cmp and binv_wayE_upd3_q; +ex3_wayE_fxubyp_val_d <= congr_cl_ex2_wayE_byp(1) or congr_cl_ex2_wayE_byp(3) or + congr_cl_ex2_wayE_byp(5) or congr_cl_ex2_wayE_byp(7); +ex3_wayE_relbyp_val_d <= congr_cl_ex2_wayE_byp(2) or congr_cl_ex2_wayE_byp(4) or + congr_cl_ex2_wayE_byp(6); +ex4_wayE_fxubyp_val_d <= ex3_wayE_fxubyp_val_q; +ex4_wayE_relbyp_val_d <= ex3_wayE_relbyp_val_q; +ex4_wayE_byp_sel <= ex4_wayE_fxubyp_val_q & ex4_wayE_relbyp_val_q; +congr_cl_ex2_wayE_sel(2) <= congr_cl_ex2_wayE_byp(2); +congr_cl_ex2_wayE_sel(3) <= congr_cl_ex2_wayE_byp(3) and not congr_cl_ex2_wayE_byp(2); +congr_cl_ex2_wayE_sel(4) <= congr_cl_ex2_wayE_byp(4) and not or_reduce(congr_cl_ex2_wayE_byp(2 to 3)); +congr_cl_ex2_wayE_sel(5) <= congr_cl_ex2_wayE_byp(5) and not or_reduce(congr_cl_ex2_wayE_byp(2 to 4)); +congr_cl_ex2_wayE_sel(6) <= congr_cl_ex2_wayE_byp(6) and not or_reduce(congr_cl_ex2_wayE_byp(2 to 5)); +congr_cl_ex2_wayE_sel(7) <= congr_cl_ex2_wayE_byp(7) and not or_reduce(congr_cl_ex2_wayE_byp(2 to 6)); +wayE_late_sel <= or_reduce(congr_cl_ex2_wayE_byp(2 to 7)); +wayE_later_stg_pri <= gate(p0_arr_wayE_rd, not wayE_late_sel) or + gate(reload_wayE_q, congr_cl_ex2_wayE_sel(2)) or + gate(flush_wayE_q, congr_cl_ex2_wayE_sel(3)) or + gate(reload_wayE_data_q, congr_cl_ex2_wayE_sel(4)) or + gate(flush_wayE_data_q, congr_cl_ex2_wayE_sel(5)) or + gate(reload_wayE_data2_q, congr_cl_ex2_wayE_sel(6)) or + gate(flush_wayE_data2_q, congr_cl_ex2_wayE_sel(7)); +wayE_early_sel <= congr_cl_ex2_wayE_byp(1); +wayE_early_stg_pri <= flush_wayE_d; +wayE_stg_val <= (others=>(wayE_early_sel)); +wayE_stg_val_b <= (others=>(not(wayE_early_sel))); +wayE_val(0 TO 1) <= not wayE_val_b_q(0 to 1); +wayE_val(2 TO 5) <= not wayE_val_b_q(2 to 5); +wayE_val_b1 <= not wayE_val(0); +congr_cl_ex2_wayF_byp(1) <= congr_cl_ex2_ex3_m and ex3_wayF_hit; +congr_cl_ex2_wayF_byp(2) <= congr_cl_ex2_relu_m and reload_wayF_upd_q; +congr_cl_ex2_wayF_byp(3) <= congr_cl_ex2_ex4_m and binv_wayF_upd_q; +congr_cl_ex2_wayF_byp(4) <= congr_cl_ex2_relu_s_m and reload_wayF_upd2_q; +congr_cl_ex2_wayF_byp(5) <= congr_cl_ex2_ex5_m and binv_wayF_upd2_q; +congr_cl_ex2_wayF_byp(6) <= congr_cl_ex2_p1_cmp and reload_wayF_upd3_q; +congr_cl_ex2_wayF_byp(7) <= congr_cl_ex2_p0_cmp and binv_wayF_upd3_q; +ex3_wayF_fxubyp_val_d <= congr_cl_ex2_wayF_byp(1) or congr_cl_ex2_wayF_byp(3) or + congr_cl_ex2_wayF_byp(5) or congr_cl_ex2_wayF_byp(7); +ex3_wayF_relbyp_val_d <= congr_cl_ex2_wayF_byp(2) or congr_cl_ex2_wayF_byp(4) or + congr_cl_ex2_wayF_byp(6); +ex4_wayF_fxubyp_val_d <= ex3_wayF_fxubyp_val_q; +ex4_wayF_relbyp_val_d <= ex3_wayF_relbyp_val_q; +ex4_wayF_byp_sel <= ex4_wayF_fxubyp_val_q & ex4_wayF_relbyp_val_q; +congr_cl_ex2_wayF_sel(2) <= congr_cl_ex2_wayF_byp(2); +congr_cl_ex2_wayF_sel(3) <= congr_cl_ex2_wayF_byp(3) and not congr_cl_ex2_wayF_byp(2); +congr_cl_ex2_wayF_sel(4) <= congr_cl_ex2_wayF_byp(4) and not or_reduce(congr_cl_ex2_wayF_byp(2 to 3)); +congr_cl_ex2_wayF_sel(5) <= congr_cl_ex2_wayF_byp(5) and not or_reduce(congr_cl_ex2_wayF_byp(2 to 4)); +congr_cl_ex2_wayF_sel(6) <= congr_cl_ex2_wayF_byp(6) and not or_reduce(congr_cl_ex2_wayF_byp(2 to 5)); +congr_cl_ex2_wayF_sel(7) <= congr_cl_ex2_wayF_byp(7) and not or_reduce(congr_cl_ex2_wayF_byp(2 to 6)); +wayF_late_sel <= or_reduce(congr_cl_ex2_wayF_byp(2 to 7)); +wayF_later_stg_pri <= gate(p0_arr_wayF_rd, not wayF_late_sel) or + gate(reload_wayF_q, congr_cl_ex2_wayF_sel(2)) or + gate(flush_wayF_q, congr_cl_ex2_wayF_sel(3)) or + gate(reload_wayF_data_q, congr_cl_ex2_wayF_sel(4)) or + gate(flush_wayF_data_q, congr_cl_ex2_wayF_sel(5)) or + gate(reload_wayF_data2_q, congr_cl_ex2_wayF_sel(6)) or + gate(flush_wayF_data2_q, congr_cl_ex2_wayF_sel(7)); +wayF_early_sel <= congr_cl_ex2_wayF_byp(1); +wayF_early_stg_pri <= flush_wayF_d; +wayF_stg_val <= (others=>(wayF_early_sel)); +wayF_stg_val_b <= (others=>(not(wayF_early_sel))); +wayF_val(0 TO 1) <= not wayF_val_b_q(0 to 1); +wayF_val(2 TO 5) <= not wayF_val_b_q(2 to 5); +wayF_val_b1 <= not wayF_val(0); +congr_cl_ex2_wayG_byp(1) <= congr_cl_ex2_ex3_m and ex3_wayG_hit; +congr_cl_ex2_wayG_byp(2) <= congr_cl_ex2_relu_m and reload_wayG_upd_q; +congr_cl_ex2_wayG_byp(3) <= congr_cl_ex2_ex4_m and binv_wayG_upd_q; +congr_cl_ex2_wayG_byp(4) <= congr_cl_ex2_relu_s_m and reload_wayG_upd2_q; +congr_cl_ex2_wayG_byp(5) <= congr_cl_ex2_ex5_m and binv_wayG_upd2_q; +congr_cl_ex2_wayG_byp(6) <= congr_cl_ex2_p1_cmp and reload_wayG_upd3_q; +congr_cl_ex2_wayG_byp(7) <= congr_cl_ex2_p0_cmp and binv_wayG_upd3_q; +ex3_wayG_fxubyp_val_d <= congr_cl_ex2_wayG_byp(1) or congr_cl_ex2_wayG_byp(3) or + congr_cl_ex2_wayG_byp(5) or congr_cl_ex2_wayG_byp(7); +ex3_wayG_relbyp_val_d <= congr_cl_ex2_wayG_byp(2) or congr_cl_ex2_wayG_byp(4) or + congr_cl_ex2_wayG_byp(6); +ex4_wayG_fxubyp_val_d <= ex3_wayG_fxubyp_val_q; +ex4_wayG_relbyp_val_d <= ex3_wayG_relbyp_val_q; +ex4_wayG_byp_sel <= ex4_wayG_fxubyp_val_q & ex4_wayG_relbyp_val_q; +congr_cl_ex2_wayG_sel(2) <= congr_cl_ex2_wayG_byp(2); +congr_cl_ex2_wayG_sel(3) <= congr_cl_ex2_wayG_byp(3) and not congr_cl_ex2_wayG_byp(2); +congr_cl_ex2_wayG_sel(4) <= congr_cl_ex2_wayG_byp(4) and not or_reduce(congr_cl_ex2_wayG_byp(2 to 3)); +congr_cl_ex2_wayG_sel(5) <= congr_cl_ex2_wayG_byp(5) and not or_reduce(congr_cl_ex2_wayG_byp(2 to 4)); +congr_cl_ex2_wayG_sel(6) <= congr_cl_ex2_wayG_byp(6) and not or_reduce(congr_cl_ex2_wayG_byp(2 to 5)); +congr_cl_ex2_wayG_sel(7) <= congr_cl_ex2_wayG_byp(7) and not or_reduce(congr_cl_ex2_wayG_byp(2 to 6)); +wayG_late_sel <= or_reduce(congr_cl_ex2_wayG_byp(2 to 7)); +wayG_later_stg_pri <= gate(p0_arr_wayG_rd, not wayG_late_sel) or + gate(reload_wayG_q, congr_cl_ex2_wayG_sel(2)) or + gate(flush_wayG_q, congr_cl_ex2_wayG_sel(3)) or + gate(reload_wayG_data_q, congr_cl_ex2_wayG_sel(4)) or + gate(flush_wayG_data_q, congr_cl_ex2_wayG_sel(5)) or + gate(reload_wayG_data2_q, congr_cl_ex2_wayG_sel(6)) or + gate(flush_wayG_data2_q, congr_cl_ex2_wayG_sel(7)); +wayG_early_sel <= congr_cl_ex2_wayG_byp(1); +wayG_early_stg_pri <= flush_wayG_d; +wayG_stg_val <= (others=>(wayG_early_sel)); +wayG_stg_val_b <= (others=>(not(wayG_early_sel))); +wayG_val(0 TO 1) <= not wayG_val_b_q(0 to 1); +wayG_val(2 TO 5) <= not wayG_val_b_q(2 to 5); +wayG_val_b1 <= not wayG_val(0); +congr_cl_ex2_wayH_byp(1) <= congr_cl_ex2_ex3_m and ex3_wayH_hit; +congr_cl_ex2_wayH_byp(2) <= congr_cl_ex2_relu_m and reload_wayH_upd_q; +congr_cl_ex2_wayH_byp(3) <= congr_cl_ex2_ex4_m and binv_wayH_upd_q; +congr_cl_ex2_wayH_byp(4) <= congr_cl_ex2_relu_s_m and reload_wayH_upd2_q; +congr_cl_ex2_wayH_byp(5) <= congr_cl_ex2_ex5_m and binv_wayH_upd2_q; +congr_cl_ex2_wayH_byp(6) <= congr_cl_ex2_p1_cmp and reload_wayH_upd3_q; +congr_cl_ex2_wayH_byp(7) <= congr_cl_ex2_p0_cmp and binv_wayH_upd3_q; +ex3_wayH_fxubyp_val_d <= congr_cl_ex2_wayH_byp(1) or congr_cl_ex2_wayH_byp(3) or + congr_cl_ex2_wayH_byp(5) or congr_cl_ex2_wayH_byp(7); +ex3_wayH_relbyp_val_d <= congr_cl_ex2_wayH_byp(2) or congr_cl_ex2_wayH_byp(4) or + congr_cl_ex2_wayH_byp(6); +ex4_wayH_fxubyp_val_d <= ex3_wayH_fxubyp_val_q; +ex4_wayH_relbyp_val_d <= ex3_wayH_relbyp_val_q; +ex4_wayH_byp_sel <= ex4_wayH_fxubyp_val_q & ex4_wayH_relbyp_val_q; +congr_cl_ex2_wayH_sel(2) <= congr_cl_ex2_wayH_byp(2); +congr_cl_ex2_wayH_sel(3) <= congr_cl_ex2_wayH_byp(3) and not congr_cl_ex2_wayH_byp(2); +congr_cl_ex2_wayH_sel(4) <= congr_cl_ex2_wayH_byp(4) and not or_reduce(congr_cl_ex2_wayH_byp(2 to 3)); +congr_cl_ex2_wayH_sel(5) <= congr_cl_ex2_wayH_byp(5) and not or_reduce(congr_cl_ex2_wayH_byp(2 to 4)); +congr_cl_ex2_wayH_sel(6) <= congr_cl_ex2_wayH_byp(6) and not or_reduce(congr_cl_ex2_wayH_byp(2 to 5)); +congr_cl_ex2_wayH_sel(7) <= congr_cl_ex2_wayH_byp(7) and not or_reduce(congr_cl_ex2_wayH_byp(2 to 6)); +wayH_late_sel <= or_reduce(congr_cl_ex2_wayH_byp(2 to 7)); +wayH_later_stg_pri <= gate(p0_arr_wayH_rd, not wayH_late_sel) or + gate(reload_wayH_q, congr_cl_ex2_wayH_sel(2)) or + gate(flush_wayH_q, congr_cl_ex2_wayH_sel(3)) or + gate(reload_wayH_data_q, congr_cl_ex2_wayH_sel(4)) or + gate(flush_wayH_data_q, congr_cl_ex2_wayH_sel(5)) or + gate(reload_wayH_data2_q, congr_cl_ex2_wayH_sel(6)) or + gate(flush_wayH_data2_q, congr_cl_ex2_wayH_sel(7)); +wayH_early_sel <= congr_cl_ex2_wayH_byp(1); +wayH_early_stg_pri <= flush_wayH_d; +wayH_stg_val <= (others=>(wayH_early_sel)); +wayH_stg_val_b <= (others=>(not(wayH_early_sel))); +wayH_val(0 TO 1) <= not wayH_val_b_q(0 to 1); +wayH_val(2 TO 5) <= not wayH_val_b_q(2 to 5); +wayH_val_b1 <= not wayH_val(0); +fxu_pipe_val <= ex3_c_acc or ex3_flush_cline_q; +ex3WayHitA: ex3_wayA_hit <= not (tagA_hit_b or wayA_val_b1); +ex3WayHitB: ex3_wayB_hit <= not (tagB_hit_b or wayB_val_b1); +ex3WayHitC: ex3_wayC_hit <= not (tagC_hit_b or wayC_val_b1); +ex3WayHitD: ex3_wayD_hit <= not (tagD_hit_b or wayD_val_b1); +ex3WayHitE: ex3_wayE_hit <= not (tagE_hit_b or wayE_val_b1); +ex3WayHitF: ex3_wayF_hit <= not (tagF_hit_b or wayF_val_b1); +ex3WayHitG: ex3_wayG_hit <= not (tagG_hit_b or wayG_val_b1); +ex3WayHitH: ex3_wayH_hit <= not (tagH_hit_b or wayH_val_b1); +clr_val <= ex3_flush_cline_q or back_inval_stg3_q; +clr_val_wayA <= clr_val; +inval_clr_lck_wA_d <= clr_val_wayA and wayA_val(1); +flush_wayA_d(0) <= not clr_val_wayA and wayA_val(0); +clr_val_wayB <= clr_val; +inval_clr_lck_wB_d <= clr_val_wayB and wayB_val(1); +flush_wayB_d(0) <= not clr_val_wayB and wayB_val(0); +clr_val_wayC <= clr_val; +inval_clr_lck_wC_d <= clr_val_wayC and wayC_val(1); +flush_wayC_d(0) <= not clr_val_wayC and wayC_val(0); +clr_val_wayD <= clr_val; +inval_clr_lck_wD_d <= clr_val_wayD and wayD_val(1); +flush_wayD_d(0) <= not clr_val_wayD and wayD_val(0); +clr_val_wayE <= clr_val; +inval_clr_lck_wE_d <= clr_val_wayE and wayE_val(1); +flush_wayE_d(0) <= not clr_val_wayE and wayE_val(0); +clr_val_wayF <= clr_val; +inval_clr_lck_wF_d <= clr_val_wayF and wayF_val(1); +flush_wayF_d(0) <= not clr_val_wayF and wayF_val(0); +clr_val_wayG <= clr_val; +inval_clr_lck_wG_d <= clr_val_wayG and wayG_val(1); +flush_wayG_d(0) <= not clr_val_wayG and wayG_val(0); +clr_val_wayH <= clr_val; +inval_clr_lck_wH_d <= clr_val_wayH and wayH_val(1); +flush_wayH_d(0) <= not clr_val_wayH and wayH_val(0); +clr_lock <= clr_val or ex3_lock_clr_q; +upd_lck_wayA <= clr_lock & ex3_lock_set_q; +flush_wayA_d(1) <= (wayA_val(1) and not upd_lck_wayA(0)) or + (wayA_val(0) and upd_lck_wayA(1)); +ex4_wayA_val_d <= wayA_val; +upd_lck_wayB <= clr_lock & ex3_lock_set_q; +flush_wayB_d(1) <= (wayB_val(1) and not upd_lck_wayB(0)) or + (wayB_val(0) and upd_lck_wayB(1)); +ex4_wayB_val_d <= wayB_val; +upd_lck_wayC <= clr_lock & ex3_lock_set_q; +flush_wayC_d(1) <= (wayC_val(1) and not upd_lck_wayC(0)) or + (wayC_val(0) and upd_lck_wayC(1)); +ex4_wayC_val_d <= wayC_val; +upd_lck_wayD <= clr_lock & ex3_lock_set_q; +flush_wayD_d(1) <= (wayD_val(1) and not upd_lck_wayD(0)) or + (wayD_val(0) and upd_lck_wayD(1)); +ex4_wayD_val_d <= wayD_val; +upd_lck_wayE <= clr_lock & ex3_lock_set_q; +flush_wayE_d(1) <= (wayE_val(1) and not upd_lck_wayE(0)) or + (wayE_val(0) and upd_lck_wayE(1)); +ex4_wayE_val_d <= wayE_val; +upd_lck_wayF <= clr_lock & ex3_lock_set_q; +flush_wayF_d(1) <= (wayF_val(1) and not upd_lck_wayF(0)) or + (wayF_val(0) and upd_lck_wayF(1)); +ex4_wayF_val_d <= wayF_val; +upd_lck_wayG <= clr_lock & ex3_lock_set_q; +flush_wayG_d(1) <= (wayG_val(1) and not upd_lck_wayG(0)) or + (wayG_val(0) and upd_lck_wayG(1)); +ex4_wayG_val_d <= wayG_val; +upd_lck_wayH <= clr_lock & ex3_lock_set_q; +flush_wayH_d(1) <= (wayH_val(1) and not upd_lck_wayH(0)) or + (wayH_val(0) and upd_lck_wayH(1)); +ex4_wayH_val_d <= wayH_val; +lose_watch(0) <= clr_val or (ex3_store_instr_q and ex3_c_acc and not ex3_thrd_id_q(0)); +ex4_lose_watch_d(0) <= lose_watch(0); +clr_watch(0) <= (ex3_watch_clr_q and ex3_thrd_id_q(0)) or lose_watch(0); +set_watch(0) <= ex3_watch_set_q and ex3_thrd_id_q(0); +ex4_lost_wayA(0) <= ex4_lose_watch_q(0) and ex4_way_hit_q(0) and ex4_wayA_val_q(2); +upd_watch_tid0_wayA <= (clr_watch(0) or ex3_watch_clr_all(0)) & set_watch(0); +flush_wayA_d(2) <= (wayA_val(2) and not upd_watch_tid0_wayA(0)) or + (wayA_val(0) and upd_watch_tid0_wayA(1)); +ex4_lost_wayB(0) <= ex4_lose_watch_q(0) and ex4_way_hit_q(1) and ex4_wayB_val_q(2); +upd_watch_tid0_wayB <= (clr_watch(0) or ex3_watch_clr_all(0)) & set_watch(0); +flush_wayB_d(2) <= (wayB_val(2) and not upd_watch_tid0_wayB(0)) or + (wayB_val(0) and upd_watch_tid0_wayB(1)); +ex4_lost_wayC(0) <= ex4_lose_watch_q(0) and ex4_way_hit_q(2) and ex4_wayC_val_q(2); +upd_watch_tid0_wayC <= (clr_watch(0) or ex3_watch_clr_all(0)) & set_watch(0); +flush_wayC_d(2) <= (wayC_val(2) and not upd_watch_tid0_wayC(0)) or + (wayC_val(0) and upd_watch_tid0_wayC(1)); +ex4_lost_wayD(0) <= ex4_lose_watch_q(0) and ex4_way_hit_q(3) and ex4_wayD_val_q(2); +upd_watch_tid0_wayD <= (clr_watch(0) or ex3_watch_clr_all(0)) & set_watch(0); +flush_wayD_d(2) <= (wayD_val(2) and not upd_watch_tid0_wayD(0)) or + (wayD_val(0) and upd_watch_tid0_wayD(1)); +ex4_lost_wayE(0) <= ex4_lose_watch_q(0) and ex4_way_hit_q(4) and ex4_wayE_val_q(2); +upd_watch_tid0_wayE <= (clr_watch(0) or ex3_watch_clr_all(0)) & set_watch(0); +flush_wayE_d(2) <= (wayE_val(2) and not upd_watch_tid0_wayE(0)) or + (wayE_val(0) and upd_watch_tid0_wayE(1)); +ex4_lost_wayF(0) <= ex4_lose_watch_q(0) and ex4_way_hit_q(5) and ex4_wayF_val_q(2); +upd_watch_tid0_wayF <= (clr_watch(0) or ex3_watch_clr_all(0)) & set_watch(0); +flush_wayF_d(2) <= (wayF_val(2) and not upd_watch_tid0_wayF(0)) or + (wayF_val(0) and upd_watch_tid0_wayF(1)); +ex4_lost_wayG(0) <= ex4_lose_watch_q(0) and ex4_way_hit_q(6) and ex4_wayG_val_q(2); +upd_watch_tid0_wayG <= (clr_watch(0) or ex3_watch_clr_all(0)) & set_watch(0); +flush_wayG_d(2) <= (wayG_val(2) and not upd_watch_tid0_wayG(0)) or + (wayG_val(0) and upd_watch_tid0_wayG(1)); +ex4_lost_wayH(0) <= ex4_lose_watch_q(0) and ex4_way_hit_q(7) and ex4_wayH_val_q(2); +upd_watch_tid0_wayH <= (clr_watch(0) or ex3_watch_clr_all(0)) & set_watch(0); +flush_wayH_d(2) <= (wayH_val(2) and not upd_watch_tid0_wayH(0)) or + (wayH_val(0) and upd_watch_tid0_wayH(1)); +lose_watch(1) <= clr_val or (ex3_store_instr_q and ex3_c_acc and not ex3_thrd_id_q(1)); +ex4_lose_watch_d(1) <= lose_watch(1); +clr_watch(1) <= (ex3_watch_clr_q and ex3_thrd_id_q(1)) or lose_watch(1); +set_watch(1) <= ex3_watch_set_q and ex3_thrd_id_q(1); +ex4_lost_wayA(1) <= ex4_lose_watch_q(1) and ex4_way_hit_q(0) and ex4_wayA_val_q(3); +upd_watch_tid1_wayA <= (clr_watch(1) or ex3_watch_clr_all(1)) & set_watch(1); +flush_wayA_d(3) <= (wayA_val(3) and not upd_watch_tid1_wayA(0)) or + (wayA_val(0) and upd_watch_tid1_wayA(1)); +ex4_lost_wayB(1) <= ex4_lose_watch_q(1) and ex4_way_hit_q(1) and ex4_wayB_val_q(3); +upd_watch_tid1_wayB <= (clr_watch(1) or ex3_watch_clr_all(1)) & set_watch(1); +flush_wayB_d(3) <= (wayB_val(3) and not upd_watch_tid1_wayB(0)) or + (wayB_val(0) and upd_watch_tid1_wayB(1)); +ex4_lost_wayC(1) <= ex4_lose_watch_q(1) and ex4_way_hit_q(2) and ex4_wayC_val_q(3); +upd_watch_tid1_wayC <= (clr_watch(1) or ex3_watch_clr_all(1)) & set_watch(1); +flush_wayC_d(3) <= (wayC_val(3) and not upd_watch_tid1_wayC(0)) or + (wayC_val(0) and upd_watch_tid1_wayC(1)); +ex4_lost_wayD(1) <= ex4_lose_watch_q(1) and ex4_way_hit_q(3) and ex4_wayD_val_q(3); +upd_watch_tid1_wayD <= (clr_watch(1) or ex3_watch_clr_all(1)) & set_watch(1); +flush_wayD_d(3) <= (wayD_val(3) and not upd_watch_tid1_wayD(0)) or + (wayD_val(0) and upd_watch_tid1_wayD(1)); +ex4_lost_wayE(1) <= ex4_lose_watch_q(1) and ex4_way_hit_q(4) and ex4_wayE_val_q(3); +upd_watch_tid1_wayE <= (clr_watch(1) or ex3_watch_clr_all(1)) & set_watch(1); +flush_wayE_d(3) <= (wayE_val(3) and not upd_watch_tid1_wayE(0)) or + (wayE_val(0) and upd_watch_tid1_wayE(1)); +ex4_lost_wayF(1) <= ex4_lose_watch_q(1) and ex4_way_hit_q(5) and ex4_wayF_val_q(3); +upd_watch_tid1_wayF <= (clr_watch(1) or ex3_watch_clr_all(1)) & set_watch(1); +flush_wayF_d(3) <= (wayF_val(3) and not upd_watch_tid1_wayF(0)) or + (wayF_val(0) and upd_watch_tid1_wayF(1)); +ex4_lost_wayG(1) <= ex4_lose_watch_q(1) and ex4_way_hit_q(6) and ex4_wayG_val_q(3); +upd_watch_tid1_wayG <= (clr_watch(1) or ex3_watch_clr_all(1)) & set_watch(1); +flush_wayG_d(3) <= (wayG_val(3) and not upd_watch_tid1_wayG(0)) or + (wayG_val(0) and upd_watch_tid1_wayG(1)); +ex4_lost_wayH(1) <= ex4_lose_watch_q(1) and ex4_way_hit_q(7) and ex4_wayH_val_q(3); +upd_watch_tid1_wayH <= (clr_watch(1) or ex3_watch_clr_all(1)) & set_watch(1); +flush_wayH_d(3) <= (wayH_val(3) and not upd_watch_tid1_wayH(0)) or + (wayH_val(0) and upd_watch_tid1_wayH(1)); +lose_watch(2) <= clr_val or (ex3_store_instr_q and ex3_c_acc and not ex3_thrd_id_q(2)); +ex4_lose_watch_d(2) <= lose_watch(2); +clr_watch(2) <= (ex3_watch_clr_q and ex3_thrd_id_q(2)) or lose_watch(2); +set_watch(2) <= ex3_watch_set_q and ex3_thrd_id_q(2); +ex4_lost_wayA(2) <= ex4_lose_watch_q(2) and ex4_way_hit_q(0) and ex4_wayA_val_q(4); +upd_watch_tid2_wayA <= (clr_watch(2) or ex3_watch_clr_all(2)) & set_watch(2); +flush_wayA_d(4) <= (wayA_val(4) and not upd_watch_tid2_wayA(0)) or + (wayA_val(0) and upd_watch_tid2_wayA(1)); +ex4_lost_wayB(2) <= ex4_lose_watch_q(2) and ex4_way_hit_q(1) and ex4_wayB_val_q(4); +upd_watch_tid2_wayB <= (clr_watch(2) or ex3_watch_clr_all(2)) & set_watch(2); +flush_wayB_d(4) <= (wayB_val(4) and not upd_watch_tid2_wayB(0)) or + (wayB_val(0) and upd_watch_tid2_wayB(1)); +ex4_lost_wayC(2) <= ex4_lose_watch_q(2) and ex4_way_hit_q(2) and ex4_wayC_val_q(4); +upd_watch_tid2_wayC <= (clr_watch(2) or ex3_watch_clr_all(2)) & set_watch(2); +flush_wayC_d(4) <= (wayC_val(4) and not upd_watch_tid2_wayC(0)) or + (wayC_val(0) and upd_watch_tid2_wayC(1)); +ex4_lost_wayD(2) <= ex4_lose_watch_q(2) and ex4_way_hit_q(3) and ex4_wayD_val_q(4); +upd_watch_tid2_wayD <= (clr_watch(2) or ex3_watch_clr_all(2)) & set_watch(2); +flush_wayD_d(4) <= (wayD_val(4) and not upd_watch_tid2_wayD(0)) or + (wayD_val(0) and upd_watch_tid2_wayD(1)); +ex4_lost_wayE(2) <= ex4_lose_watch_q(2) and ex4_way_hit_q(4) and ex4_wayE_val_q(4); +upd_watch_tid2_wayE <= (clr_watch(2) or ex3_watch_clr_all(2)) & set_watch(2); +flush_wayE_d(4) <= (wayE_val(4) and not upd_watch_tid2_wayE(0)) or + (wayE_val(0) and upd_watch_tid2_wayE(1)); +ex4_lost_wayF(2) <= ex4_lose_watch_q(2) and ex4_way_hit_q(5) and ex4_wayF_val_q(4); +upd_watch_tid2_wayF <= (clr_watch(2) or ex3_watch_clr_all(2)) & set_watch(2); +flush_wayF_d(4) <= (wayF_val(4) and not upd_watch_tid2_wayF(0)) or + (wayF_val(0) and upd_watch_tid2_wayF(1)); +ex4_lost_wayG(2) <= ex4_lose_watch_q(2) and ex4_way_hit_q(6) and ex4_wayG_val_q(4); +upd_watch_tid2_wayG <= (clr_watch(2) or ex3_watch_clr_all(2)) & set_watch(2); +flush_wayG_d(4) <= (wayG_val(4) and not upd_watch_tid2_wayG(0)) or + (wayG_val(0) and upd_watch_tid2_wayG(1)); +ex4_lost_wayH(2) <= ex4_lose_watch_q(2) and ex4_way_hit_q(7) and ex4_wayH_val_q(4); +upd_watch_tid2_wayH <= (clr_watch(2) or ex3_watch_clr_all(2)) & set_watch(2); +flush_wayH_d(4) <= (wayH_val(4) and not upd_watch_tid2_wayH(0)) or + (wayH_val(0) and upd_watch_tid2_wayH(1)); +lose_watch(3) <= clr_val or (ex3_store_instr_q and ex3_c_acc and not ex3_thrd_id_q(3)); +ex4_lose_watch_d(3) <= lose_watch(3); +clr_watch(3) <= (ex3_watch_clr_q and ex3_thrd_id_q(3)) or lose_watch(3); +set_watch(3) <= ex3_watch_set_q and ex3_thrd_id_q(3); +ex4_lost_wayA(3) <= ex4_lose_watch_q(3) and ex4_way_hit_q(0) and ex4_wayA_val_q(5); +upd_watch_tid3_wayA <= (clr_watch(3) or ex3_watch_clr_all(3)) & set_watch(3); +flush_wayA_d(5) <= (wayA_val(5) and not upd_watch_tid3_wayA(0)) or + (wayA_val(0) and upd_watch_tid3_wayA(1)); +ex4_lost_wayB(3) <= ex4_lose_watch_q(3) and ex4_way_hit_q(1) and ex4_wayB_val_q(5); +upd_watch_tid3_wayB <= (clr_watch(3) or ex3_watch_clr_all(3)) & set_watch(3); +flush_wayB_d(5) <= (wayB_val(5) and not upd_watch_tid3_wayB(0)) or + (wayB_val(0) and upd_watch_tid3_wayB(1)); +ex4_lost_wayC(3) <= ex4_lose_watch_q(3) and ex4_way_hit_q(2) and ex4_wayC_val_q(5); +upd_watch_tid3_wayC <= (clr_watch(3) or ex3_watch_clr_all(3)) & set_watch(3); +flush_wayC_d(5) <= (wayC_val(5) and not upd_watch_tid3_wayC(0)) or + (wayC_val(0) and upd_watch_tid3_wayC(1)); +ex4_lost_wayD(3) <= ex4_lose_watch_q(3) and ex4_way_hit_q(3) and ex4_wayD_val_q(5); +upd_watch_tid3_wayD <= (clr_watch(3) or ex3_watch_clr_all(3)) & set_watch(3); +flush_wayD_d(5) <= (wayD_val(5) and not upd_watch_tid3_wayD(0)) or + (wayD_val(0) and upd_watch_tid3_wayD(1)); +ex4_lost_wayE(3) <= ex4_lose_watch_q(3) and ex4_way_hit_q(4) and ex4_wayE_val_q(5); +upd_watch_tid3_wayE <= (clr_watch(3) or ex3_watch_clr_all(3)) & set_watch(3); +flush_wayE_d(5) <= (wayE_val(5) and not upd_watch_tid3_wayE(0)) or + (wayE_val(0) and upd_watch_tid3_wayE(1)); +ex4_lost_wayF(3) <= ex4_lose_watch_q(3) and ex4_way_hit_q(5) and ex4_wayF_val_q(5); +upd_watch_tid3_wayF <= (clr_watch(3) or ex3_watch_clr_all(3)) & set_watch(3); +flush_wayF_d(5) <= (wayF_val(5) and not upd_watch_tid3_wayF(0)) or + (wayF_val(0) and upd_watch_tid3_wayF(1)); +ex4_lost_wayG(3) <= ex4_lose_watch_q(3) and ex4_way_hit_q(6) and ex4_wayG_val_q(5); +upd_watch_tid3_wayG <= (clr_watch(3) or ex3_watch_clr_all(3)) & set_watch(3); +flush_wayG_d(5) <= (wayG_val(5) and not upd_watch_tid3_wayG(0)) or + (wayG_val(0) and upd_watch_tid3_wayG(1)); +ex4_lost_wayH(3) <= ex4_lose_watch_q(3) and ex4_way_hit_q(7) and ex4_wayH_val_q(5); +upd_watch_tid3_wayH <= (clr_watch(3) or ex3_watch_clr_all(3)) & set_watch(3); +flush_wayH_d(5) <= (wayH_val(5) and not upd_watch_tid3_wayH(0)) or + (wayH_val(0) and upd_watch_tid3_wayH(1)); +binv_wayA_upd_d <= (ex3_wayA_hit and binv3_ex3_xuop_upd); +ex3_xuop_lost_watch_wayA <= or_reduce((wayA_val(2 to 5) and not ex3_thrd_id_q)) and ex3_store_instr_q and ex3_c_acc; +ex3_xuop_wayA_upd <= (ex3_wayA_hit and (ex3_xuop_upd_dir or ex3_xuop_lost_watch_wayA)); +ex4_xuop_wayA_upd_d <= ex3_xuop_wayA_upd; +ex5_xuop_wayA_upd_d <= ex4_xuop_wayA_upd_q; +binv_wayB_upd_d <= (ex3_wayB_hit and binv3_ex3_xuop_upd); +ex3_xuop_lost_watch_wayB <= or_reduce((wayB_val(2 to 5) and not ex3_thrd_id_q)) and ex3_store_instr_q and ex3_c_acc; +ex3_xuop_wayB_upd <= (ex3_wayB_hit and (ex3_xuop_upd_dir or ex3_xuop_lost_watch_wayB)); +ex4_xuop_wayB_upd_d <= ex3_xuop_wayB_upd; +ex5_xuop_wayB_upd_d <= ex4_xuop_wayB_upd_q; +binv_wayC_upd_d <= (ex3_wayC_hit and binv3_ex3_xuop_upd); +ex3_xuop_lost_watch_wayC <= or_reduce((wayC_val(2 to 5) and not ex3_thrd_id_q)) and ex3_store_instr_q and ex3_c_acc; +ex3_xuop_wayC_upd <= (ex3_wayC_hit and (ex3_xuop_upd_dir or ex3_xuop_lost_watch_wayC)); +ex4_xuop_wayC_upd_d <= ex3_xuop_wayC_upd; +ex5_xuop_wayC_upd_d <= ex4_xuop_wayC_upd_q; +binv_wayD_upd_d <= (ex3_wayD_hit and binv3_ex3_xuop_upd); +ex3_xuop_lost_watch_wayD <= or_reduce((wayD_val(2 to 5) and not ex3_thrd_id_q)) and ex3_store_instr_q and ex3_c_acc; +ex3_xuop_wayD_upd <= (ex3_wayD_hit and (ex3_xuop_upd_dir or ex3_xuop_lost_watch_wayD)); +ex4_xuop_wayD_upd_d <= ex3_xuop_wayD_upd; +ex5_xuop_wayD_upd_d <= ex4_xuop_wayD_upd_q; +binv_wayE_upd_d <= (ex3_wayE_hit and binv3_ex3_xuop_upd); +ex3_xuop_lost_watch_wayE <= or_reduce((wayE_val(2 to 5) and not ex3_thrd_id_q)) and ex3_store_instr_q and ex3_c_acc; +ex3_xuop_wayE_upd <= (ex3_wayE_hit and (ex3_xuop_upd_dir or ex3_xuop_lost_watch_wayE)); +ex4_xuop_wayE_upd_d <= ex3_xuop_wayE_upd; +ex5_xuop_wayE_upd_d <= ex4_xuop_wayE_upd_q; +binv_wayF_upd_d <= (ex3_wayF_hit and binv3_ex3_xuop_upd); +ex3_xuop_lost_watch_wayF <= or_reduce((wayF_val(2 to 5) and not ex3_thrd_id_q)) and ex3_store_instr_q and ex3_c_acc; +ex3_xuop_wayF_upd <= (ex3_wayF_hit and (ex3_xuop_upd_dir or ex3_xuop_lost_watch_wayF)); +ex4_xuop_wayF_upd_d <= ex3_xuop_wayF_upd; +ex5_xuop_wayF_upd_d <= ex4_xuop_wayF_upd_q; +binv_wayG_upd_d <= (ex3_wayG_hit and binv3_ex3_xuop_upd); +ex3_xuop_lost_watch_wayG <= or_reduce((wayG_val(2 to 5) and not ex3_thrd_id_q)) and ex3_store_instr_q and ex3_c_acc; +ex3_xuop_wayG_upd <= (ex3_wayG_hit and (ex3_xuop_upd_dir or ex3_xuop_lost_watch_wayG)); +ex4_xuop_wayG_upd_d <= ex3_xuop_wayG_upd; +ex5_xuop_wayG_upd_d <= ex4_xuop_wayG_upd_q; +binv_wayH_upd_d <= (ex3_wayH_hit and binv3_ex3_xuop_upd); +ex3_xuop_lost_watch_wayH <= or_reduce((wayH_val(2 to 5) and not ex3_thrd_id_q)) and ex3_store_instr_q and ex3_c_acc; +ex3_xuop_wayH_upd <= (ex3_wayH_hit and (ex3_xuop_upd_dir or ex3_xuop_lost_watch_wayH)); +ex4_xuop_wayH_upd_d <= ex3_xuop_wayH_upd; +ex5_xuop_wayH_upd_d <= ex4_xuop_wayH_upd_q; +binv4_ex4_lock_set <= ex4_wayA_val_q(1) or ex4_wayB_val_q(1) or ex4_wayC_val_q(1) or ex4_wayD_val_q(1) or + ex4_wayE_val_q(1) or ex4_wayF_val_q(1) or ex4_wayG_val_q(1) or ex4_wayH_val_q(1); +binv4_ex4_thrd_watch <= ex4_wayA_val_q(2 to 5) or ex4_wayB_val_q(2 to 5) or ex4_wayC_val_q(2 to 5) or ex4_wayD_val_q(2 to 5) or + ex4_wayE_val_q(2 to 5) or ex4_wayF_val_q(2 to 5) or ex4_wayG_val_q(2 to 5) or ex4_wayH_val_q(2 to 5); +wayA_watch_value <= (ex4_thrd_id_q(0) and ex4_wayA_val_q(2)) or (ex4_thrd_id_q(1) and ex4_wayA_val_q(3)) or + (ex4_thrd_id_q(2) and ex4_wayA_val_q(4)) or (ex4_thrd_id_q(3) and ex4_wayA_val_q(5)); +wayB_watch_value <= (ex4_thrd_id_q(0) and ex4_wayB_val_q(2)) or (ex4_thrd_id_q(1) and ex4_wayB_val_q(3)) or + (ex4_thrd_id_q(2) and ex4_wayB_val_q(4)) or (ex4_thrd_id_q(3) and ex4_wayB_val_q(5)); +wayC_watch_value <= (ex4_thrd_id_q(0) and ex4_wayC_val_q(2)) or (ex4_thrd_id_q(1) and ex4_wayC_val_q(3)) or + (ex4_thrd_id_q(2) and ex4_wayC_val_q(4)) or (ex4_thrd_id_q(3) and ex4_wayC_val_q(5)); +wayD_watch_value <= (ex4_thrd_id_q(0) and ex4_wayD_val_q(2)) or (ex4_thrd_id_q(1) and ex4_wayD_val_q(3)) or + (ex4_thrd_id_q(2) and ex4_wayD_val_q(4)) or (ex4_thrd_id_q(3) and ex4_wayD_val_q(5)); +wayE_watch_value <= (ex4_thrd_id_q(0) and ex4_wayE_val_q(2)) or (ex4_thrd_id_q(1) and ex4_wayE_val_q(3)) or + (ex4_thrd_id_q(2) and ex4_wayE_val_q(4)) or (ex4_thrd_id_q(3) and ex4_wayE_val_q(5)); +wayF_watch_value <= (ex4_thrd_id_q(0) and ex4_wayF_val_q(2)) or (ex4_thrd_id_q(1) and ex4_wayF_val_q(3)) or + (ex4_thrd_id_q(2) and ex4_wayF_val_q(4)) or (ex4_thrd_id_q(3) and ex4_wayF_val_q(5)); +wayG_watch_value <= (ex4_thrd_id_q(0) and ex4_wayG_val_q(2)) or (ex4_thrd_id_q(1) and ex4_wayG_val_q(3)) or + (ex4_thrd_id_q(2) and ex4_wayG_val_q(4)) or (ex4_thrd_id_q(3) and ex4_wayG_val_q(5)); +wayH_watch_value <= (ex4_thrd_id_q(0) and ex4_wayH_val_q(2)) or (ex4_thrd_id_q(1) and ex4_wayH_val_q(3)) or + (ex4_thrd_id_q(2) and ex4_wayH_val_q(4)) or (ex4_thrd_id_q(3) and ex4_wayH_val_q(5)); +ex4_curr_watch <= (ex4_way_hit_q(0) and wayA_watch_value) or (ex4_way_hit_q(1) and wayB_watch_value) or + (ex4_way_hit_q(2) and wayC_watch_value) or (ex4_way_hit_q(3) and wayD_watch_value) or + (ex4_way_hit_q(4) and wayE_watch_value) or (ex4_way_hit_q(5) and wayF_watch_value) or + (ex4_way_hit_q(6) and wayG_watch_value) or (ex4_way_hit_q(7) and wayH_watch_value); +stm_watchlost_sel <= (ex4_thrd_id_q(0) and stm_watchlost(0)) or (ex4_thrd_id_q(1) and stm_watchlost(1)) or + (ex4_thrd_id_q(2) and stm_watchlost(2)) or (ex4_thrd_id_q(3) and stm_watchlost(3)); +with ex4_watch_set_q select + ex5_cr_watch_d <= stm_watchlost_sel when '0', + ex4_curr_watch when others; +ex4_lost_watch(0) <= ex4_lost_wayA(0) or ex4_lost_wayB(0) or ex4_lost_wayC(0) or ex4_lost_wayD(0) or + ex4_lost_wayE(0) or ex4_lost_wayF(0) or ex4_lost_wayG(0) or ex4_lost_wayH(0) or + ex4_perr_watch_lost_q(0); + WITH ex4_watchlost_set_q(0) SELECT ex4_lost_watch_upd(0) <= ex4_lost_watch(0) when '0', + ex4_l_fld_b1_q when others; +ex4_lost_watch(1) <= ex4_lost_wayA(1) or ex4_lost_wayB(1) or ex4_lost_wayC(1) or ex4_lost_wayD(1) or + ex4_lost_wayE(1) or ex4_lost_wayF(1) or ex4_lost_wayG(1) or ex4_lost_wayH(1) or + ex4_perr_watch_lost_q(1); + WITH ex4_watchlost_set_q(1) SELECT ex4_lost_watch_upd(1) <= ex4_lost_watch(1) when '0', + ex4_l_fld_b1_q when others; +ex4_lost_watch(2) <= ex4_lost_wayA(2) or ex4_lost_wayB(2) or ex4_lost_wayC(2) or ex4_lost_wayD(2) or + ex4_lost_wayE(2) or ex4_lost_wayF(2) or ex4_lost_wayG(2) or ex4_lost_wayH(2) or + ex4_perr_watch_lost_q(2); + WITH ex4_watchlost_set_q(2) SELECT ex4_lost_watch_upd(2) <= ex4_lost_watch(2) when '0', + ex4_l_fld_b1_q when others; +ex4_lost_watch(3) <= ex4_lost_wayA(3) or ex4_lost_wayB(3) or ex4_lost_wayC(3) or ex4_lost_wayD(3) or + ex4_lost_wayE(3) or ex4_lost_wayF(3) or ex4_lost_wayG(3) or ex4_lost_wayH(3) or + ex4_perr_watch_lost_q(3); + WITH ex4_watchlost_set_q(3) SELECT ex4_lost_watch_upd(3) <= ex4_lost_watch(3) when '0', + ex4_l_fld_b1_q when others; +ex4_watchSet_coll_d <= rel_val_stg2_q and ex3_watch_set_q and (rel24_congr_cl_q = ex3_congr_cl_q); +watchSet_rel_way_coll <= gate((reload_way_clr_q and ex4_way_hit_q), ex4_watchSet_coll_q); +watchSet_rel_coll_val <= gate(ex4_thrd_id_q, or_reduce(watchSet_rel_way_coll)); +ex5_lost_watch_upd_d <= ex4_lost_watch_upd or watchSet_rel_coll_val or ex4_multihit_watch_lost; +ex4_watchlost_set_d <= ex3_watch_clr_all; +ex5_watchlost_set_d <= ex4_lost_watch or ex4_watchlost_set_q or watchSet_rel_coll_val or ex4_multihit_watch_lost; +ex5_watch_clr_all_d <= gate(ex4_watch_clr_all_q, not ex4_stg_flush); +ex6_watch_clr_all_d <= gate(ex5_watch_clr_all_q, not ex5_stg_flush); +ex5_watch_clr_all_val_d <= or_reduce(ex4_watch_clr_all_q); +u_th0i: tagA_hit_b <= not tagA_hit; +u_hw0i: xu_op_hit_wayA_b <= not (wayA_val(0) and tagA_hit); +u_hw0: xu_op_hit_wayA <= not xu_op_hit_wayA_b; +u_hw0b: xu_op_hit_wayA_dly_b <= not xu_op_hit_wayA; +u_th1i: tagB_hit_b <= not tagB_hit; +u_hw1i: xu_op_hit_wayB_b <= not (wayB_val(0) and tagB_hit); +u_hw1: xu_op_hit_wayB <= not xu_op_hit_wayB_b; +u_hw1b: xu_op_hit_wayB_dly_b <= not xu_op_hit_wayB; +u_th2i: tagC_hit_b <= not tagC_hit; +u_hw2i: xu_op_hit_wayC_b <= not (wayC_val(0) and tagC_hit); +u_hw2: xu_op_hit_wayC <= not xu_op_hit_wayC_b; +u_hw2b: xu_op_hit_wayC_dly_b <= not xu_op_hit_wayC; +u_th3i: tagD_hit_b <= not tagD_hit; +u_hw3i: xu_op_hit_wayD_b <= not (wayD_val(0) and tagD_hit); +u_hw3: xu_op_hit_wayD <= not xu_op_hit_wayD_b; +u_hw3b: xu_op_hit_wayD_dly_b <= not xu_op_hit_wayD; +u_th4i: tagE_hit_b <= not tagE_hit; +u_hw4i: xu_op_hit_wayE_b <= not (wayE_val(0) and tagE_hit); +u_hw4: xu_op_hit_wayE <= not xu_op_hit_wayE_b; +u_hw4b: xu_op_hit_wayE_dly_b <= not xu_op_hit_wayE; +u_th5i: tagF_hit_b <= not tagF_hit; +u_hw5i: xu_op_hit_wayF_b <= not (wayF_val(0) and tagF_hit); +u_hw5: xu_op_hit_wayF <= not xu_op_hit_wayF_b; +u_hw5b: xu_op_hit_wayF_dly_b <= not xu_op_hit_wayF; +u_th6i: tagG_hit_b <= not tagG_hit; +u_hw6i: xu_op_hit_wayG_b <= not (wayG_val(0) and tagG_hit); +u_hw6: xu_op_hit_wayG <= not xu_op_hit_wayG_b; +u_hw6b: xu_op_hit_wayG_dly_b <= not xu_op_hit_wayG; +u_th7i: tagH_hit_b <= not tagH_hit; +u_hw7i: xu_op_hit_wayH_b <= not (wayH_val(0) and tagH_hit); +u_hw7: xu_op_hit_wayH <= not xu_op_hit_wayH_b; +u_hw7b: xu_op_hit_wayH_dly_b <= not xu_op_hit_wayH; +inval_clr_lck <= (inval_clr_lck_wA_q and binv_wayA_upd_q) or (inval_clr_lck_wB_q and binv_wayB_upd_q) or + (inval_clr_lck_wC_q and binv_wayC_upd_q) or (inval_clr_lck_wD_q and binv_wayD_upd_q) or + (inval_clr_lck_wE_q and binv_wayE_upd_q) or (inval_clr_lck_wF_q and binv_wayF_upd_q) or + (inval_clr_lck_wG_q and binv_wayG_upd_q) or (inval_clr_lck_wH_q and binv_wayH_upd_q); +xucr0_cslc_xuop_d <= inval_clr_lck and ex4_xuop_val; +xucr0_cslc_binv_d <= rel_lock_lost or dcperr_lock_lost_q or ex4_perr_lck_lost_q or + ex4_multihit_lock_lost or binv5_inval_lock_val_q or (rel_l1dump_cslc_q and not rel4_ecc_err); +ex3_cClass_upd_way_a <= ex3_cClass_wayA_hit; +ex3_cClass_upd_way_b <= ex3_cClass_wayB_hit; +ex3_cClass_upd_way_c <= ex3_cClass_wayC_hit; +ex3_cClass_upd_way_d <= ex3_cClass_wayD_hit; +ex3_cClass_upd_way_e <= ex3_cClass_wayE_hit; +ex3_cClass_upd_way_f <= ex3_cClass_wayF_hit; +ex3_cClass_upd_way_g <= ex3_cClass_wayG_hit; +ex3_cClass_upd_way_h <= ex3_cClass_wayH_hit; +u_mh1_a01: hit_and_01_b <= not( xu_op_hit_wayA and xu_op_hit_wayB ); +u_mh1_a23: hit_and_23_b <= not( xu_op_hit_wayC and xu_op_hit_wayD ); +u_mh1_a45: hit_and_45_b <= not( xu_op_hit_wayE and xu_op_hit_wayF ); +u_mh1_a67: hit_and_67_b <= not( xu_op_hit_wayG and xu_op_hit_wayH ); +u_mh1_o01: hit_or_01_b <= not( xu_op_hit_wayA or xu_op_hit_wayB ); +u_mh1_o23: hit_or_23_b <= not( xu_op_hit_wayC or xu_op_hit_wayD ); +u_mh1_o45: hit_or_45_b <= not( xu_op_hit_wayE or xu_op_hit_wayF ); +u_mh1_o67: hit_or_67_b <= not( xu_op_hit_wayG or xu_op_hit_wayH ); +u_mh1_o13: hit_or_13_b <= not( xu_op_hit_wayB or xu_op_hit_wayD ); +u_mh1_o57: hit_or_57_b <= not( xu_op_hit_wayF or xu_op_hit_wayH ); +u_mh2_o0123: hit_or_0123 <= not( hit_or_01_b and hit_or_23_b ); +u_mh2_o4567: hit_or_4567 <= not( hit_or_45_b and hit_or_67_b ); +u_mh2_o1357: hit_or_1357 <= not( hit_or_13_b and hit_or_57_b ); +u_mh2_o2367: hit_or_2367 <= not( hit_or_23_b and hit_or_67_b ); +u_mh2_a0123: hit_and_0123 <= not( hit_or_01_b or hit_or_23_b ); +u_mh2_a4567: hit_and_4567 <= not( hit_or_45_b or hit_or_67_b ); +u_mh2_err0: multi_hit_err2_0 <= not( hit_and_01_b and hit_and_23_b ); +u_mh2_err1: multi_hit_err2_1 <= not( hit_and_45_b and hit_and_67_b ); +u_mh3_o: hit_or_01234567_b <= not( hit_or_0123 or hit_or_4567 ); +u_mh3_err0: multi_hit_err3_b(0) <= not( hit_or_0123 and hit_or_4567 ); +u_mh3_err1: multi_hit_err3_b(1) <= not( hit_and_0123 or hit_and_4567 ); +u_mh3_err2: multi_hit_err3_b(2) <= not( multi_hit_err2_0 or multi_hit_err2_1 ); +u_henc_0: hit_enc_b(0) <= not( hit_or_4567 ); +u_henc_1: hit_enc_b(1) <= not( hit_or_2367 ); +u_henc_2: hit_enc_b(2) <= not( hit_or_1357 ); +u_mh4_0: ex3_dir_multihit_val_0 <= not( multi_hit_err3_b(0) and multi_hit_err3_b(1) ); +u_mh4_1: ex3_dir_multihit_val_1 <= not( multi_hit_err3_b(2) and inj_dir_multihit_b ); +u_mh5: ex3_dir_multihit_val_b <= not( ex3_dir_multihit_val_0 or ex3_dir_multihit_val_1 ); +u_mh6: ex3_dir_multihit_val <= not ex3_dir_multihit_val_b ; +ex4_n_lsu_ddmh_flush_b_d <= (others=>ex3_dir_multihit_val); +ex4_dir_multihit_val <= binv4_ex4_dir_val_q and not ex4_dir_multihit_val_b_q; +inj_dir_multihit_b <= not (inj_dir_multihit_q and binv3_ex3_dir_val); +ex4_multihit_watch_lost <= gate(binv4_ex4_thrd_watch, ex4_dir_multihit_val); +ex4_multihit_lock_lost <= binv4_ex4_lock_set and ex4_dir_multihit_val; +ex4_err_det_way_d(0) <= perr_way_det_wayA; +perr_way_det_wayA <= wayA_val(0) and ex3_tag_way_perr(0); +dirpar_err_lock_lost(0) <= wayA_val(1) and ex3_tag_way_perr(0); +perr_wayA_watch_lost <= gate(wayA_val(2 to 5),ex3_tag_way_perr(0)); +ex4_err_det_way_d(1) <= perr_way_det_wayB; +perr_way_det_wayB <= wayB_val(0) and ex3_tag_way_perr(1); +dirpar_err_lock_lost(1) <= wayB_val(1) and ex3_tag_way_perr(1); +perr_wayB_watch_lost <= gate(wayB_val(2 to 5),ex3_tag_way_perr(1)); +ex4_err_det_way_d(2) <= perr_way_det_wayC; +perr_way_det_wayC <= wayC_val(0) and ex3_tag_way_perr(2); +dirpar_err_lock_lost(2) <= wayC_val(1) and ex3_tag_way_perr(2); +perr_wayC_watch_lost <= gate(wayC_val(2 to 5),ex3_tag_way_perr(2)); +ex4_err_det_way_d(3) <= perr_way_det_wayD; +perr_way_det_wayD <= wayD_val(0) and ex3_tag_way_perr(3); +dirpar_err_lock_lost(3) <= wayD_val(1) and ex3_tag_way_perr(3); +perr_wayD_watch_lost <= gate(wayD_val(2 to 5),ex3_tag_way_perr(3)); +ex4_err_det_way_d(4) <= perr_way_det_wayE; +perr_way_det_wayE <= wayE_val(0) and ex3_tag_way_perr(4); +dirpar_err_lock_lost(4) <= wayE_val(1) and ex3_tag_way_perr(4); +perr_wayE_watch_lost <= gate(wayE_val(2 to 5),ex3_tag_way_perr(4)); +ex4_err_det_way_d(5) <= perr_way_det_wayF; +perr_way_det_wayF <= wayF_val(0) and ex3_tag_way_perr(5); +dirpar_err_lock_lost(5) <= wayF_val(1) and ex3_tag_way_perr(5); +perr_wayF_watch_lost <= gate(wayF_val(2 to 5),ex3_tag_way_perr(5)); +ex4_err_det_way_d(6) <= perr_way_det_wayG; +perr_way_det_wayG <= wayG_val(0) and ex3_tag_way_perr(6); +dirpar_err_lock_lost(6) <= wayG_val(1) and ex3_tag_way_perr(6); +perr_wayG_watch_lost <= gate(wayG_val(2 to 5),ex3_tag_way_perr(6)); +ex4_err_det_way_d(7) <= perr_way_det_wayH; +perr_way_det_wayH <= wayH_val(0) and ex3_tag_way_perr(7); +dirpar_err_lock_lost(7) <= wayH_val(1) and ex3_tag_way_perr(7); +perr_wayH_watch_lost <= gate(wayH_val(2 to 5),ex3_tag_way_perr(7)); +ex4_perr_lck_lost_d <= or_reduce(dirpar_err_lock_lost); +ex4_perr_watch_lost_d <= perr_wayA_watch_lost or perr_wayB_watch_lost or perr_wayC_watch_lost or perr_wayD_watch_lost or + perr_wayE_watch_lost or perr_wayF_watch_lost or perr_wayG_watch_lost or perr_wayH_watch_lost; +ex3_dir_perr_val <= perr_way_det_wayA or perr_way_det_wayB or perr_way_det_wayC or perr_way_det_wayD or + perr_way_det_wayE or perr_way_det_wayF or perr_way_det_wayG or perr_way_det_wayH; +ex4_dir_err_val_d <= ex3_dir_perr_val; +ex5_dir_err_val_d <= ex4_dir_err_val_q or ex4_dir_multihit_val; +ex6_dir_err_val_d <= ex5_dir_err_val_q; +derr2_stg_act_d <= ex6_dir_err_val_q; +derr3_stg_act_d <= derr2_stg_act_q; +derr4_stg_act_d <= derr3_stg_act_q; +derr5_stg_act_d <= derr4_stg_act_q; +ex3L1Hit: ex3_l1hit <= not hit_or_01234567_b; +ex3L1Miss: ex3_l1miss <= not ex3_l1hit; +ex3_hit <= not ex3_l1miss; +ex4_miss <= not ex4_miss_q; +ex4_way_hit_d <= not (xu_op_hit_wayA_dly_b & xu_op_hit_wayB_dly_b & xu_op_hit_wayC_dly_b & xu_op_hit_wayD_dly_b & + xu_op_hit_wayE_dly_b & xu_op_hit_wayF_dly_b & xu_op_hit_wayG_dly_b & xu_op_hit_wayH_dly_b); +ex5_way_hit_d <= ex4_way_hit_q; +ex6_way_hit_d <= ex5_way_hit_q; +ex3_xuop_up_addr_b <= hit_enc_b(0 to 2); +rel_dcarr_addr_sel <= (others=>rel_dcarr_addr_en); +rel_dcarr_addr_sel_b <= (others=>(not rel_dcarr_addr_en)); +congr_cl_ex3_ex4_cmp_d <= congr_cl_ex2_ex3_cmp_q; +congr_cl_ex3_ex5_cmp_d <= congr_cl_ex2_ex4_cmp_q; +congr_cl_ex3_ex6_cmp_d <= congr_cl_ex2_ex5_cmp_q; +congr_cl_ex4_ex5_cmp_d <= congr_cl_ex3_ex4_cmp_q; +congr_cl_ex4_ex6_cmp_d <= congr_cl_ex3_ex5_cmp_q; +congr_cl_ex4_ex7_cmp_d <= congr_cl_ex3_ex6_cmp_q; +binv4_ex4_way_upd <= binv_wayA_upd1 & binv_wayB_upd1 & binv_wayC_upd1 & binv_wayD_upd1 & + binv_wayE_upd1 & binv_wayF_upd1 & binv_wayG_upd1 & binv_wayH_upd1; +binv5_ex5_way_upd <= binv_wayA_upd2_q & binv_wayB_upd2_q & binv_wayC_upd2_q & binv_wayD_upd2_q & + binv_wayE_upd2_q & binv_wayF_upd2_q & binv_wayG_upd2_q & binv_wayH_upd2_q; +binv6_ex6_way_upd <= binv_wayA_upd3_q & binv_wayB_upd3_q & binv_wayC_upd3_q & binv_wayD_upd3_q & + binv_wayE_upd3_q & binv_wayF_upd3_q & binv_wayG_upd3_q & binv_wayH_upd3_q; +binv7_ex7_way_upd_d <= binv6_ex6_way_upd; +binv4_ex4_dir_data <= gate(flush_wayA_data1(1 to 5), binv4_ex4_way_upd(0)) or gate(flush_wayB_data1(1 to 5), binv4_ex4_way_upd(1)) or + gate(flush_wayC_data1(1 to 5), binv4_ex4_way_upd(2)) or gate(flush_wayD_data1(1 to 5), binv4_ex4_way_upd(3)) or + gate(flush_wayE_data1(1 to 5), binv4_ex4_way_upd(4)) or gate(flush_wayF_data1(1 to 5), binv4_ex4_way_upd(5)) or + gate(flush_wayG_data1(1 to 5), binv4_ex4_way_upd(6)) or gate(flush_wayH_data1(1 to 5), binv4_ex4_way_upd(7)); +binv5_ex5_dir_data_d <= binv4_ex4_dir_data; +binv6_ex6_dir_data_d <= binv5_ex5_dir_data_q; +binv7_ex7_dir_data_d <= binv6_ex6_dir_data_q; +binv4_inval_lck <= inval_clr_lck and back_inval_stg4_q and not binv4_coll_val; +binv4_inval_watch <= gate(ex4_lost_watch, (back_inval_stg4_q and not binv4_coll_val)); +binv4_ex5_coll <= (back_inval_stg4_q or ex4_dir_multihit_val) and congr_cl_ex4_ex5_cmp_q and or_reduce(ex4_way_hit_q and binv5_ex5_way_upd) and p0_wren_d; +binv4_ex6_coll <= (back_inval_stg4_q or ex4_dir_multihit_val) and congr_cl_ex4_ex6_cmp_q and or_reduce(ex4_way_hit_q and binv6_ex6_way_upd) and p0_wren_q; +binv4_ex7_coll <= (back_inval_stg4_q or ex4_dir_multihit_val) and congr_cl_ex4_ex7_cmp_q and or_reduce(ex4_way_hit_q and binv7_ex7_way_upd_q) and p0_wren_stg_q; +binv4_coll_val <= binv4_ex5_coll or binv4_ex6_coll or binv4_ex7_coll; +binv4_pri_byp_sel(0) <= binv4_ex5_coll; +binv4_pri_byp_sel(1) <= binv4_ex6_coll and not binv4_ex5_coll; +binv4_pri_byp_sel(2) <= binv4_ex7_coll and not (binv4_ex6_coll or binv4_ex5_coll); +binv4_byp_dir_data <= gate(binv5_ex5_dir_data_q, binv4_pri_byp_sel(0)) or + gate(binv6_ex6_dir_data_q, binv4_pri_byp_sel(1)) or + gate(binv7_ex7_dir_data_q, binv4_pri_byp_sel(2)); +binv5_inval_watch_val_d <= (binv4_byp_dir_data(2 to 5) and not binv4_ex4_dir_data(2 to 5)) or binv4_inval_watch; +binv5_inval_lock_val_d <= (binv4_byp_dir_data(1) and not binv4_ex4_dir_data(1)) or binv4_inval_lck; +dci_watch_lost <= (others=>dci_compl_q); +congr_cl_ex3_upd_wayA <= congr_cl_ex2_ex3_cmp_q and not ex3_thrd_m_q and ex3_xuop_wayA_upd and not ex3_stg_flush; +congr_cl_ex4_upd_wayA <= congr_cl_ex2_ex4_cmp_q and not ex4_thrd_m_q and ex4_xuop_wayA_upd_q and not ex4_stg_flush; +congr_cl_ex5_upd_wayA <= congr_cl_ex2_ex5_cmp_q and not ex5_thrd_m_q and ex5_xuop_wayA_upd_q and not ex5_stg_flush; +congr_cl_m_upd_wayA_d <= congr_cl_ex3_upd_wayA or congr_cl_ex4_upd_wayA or congr_cl_ex5_upd_wayA; +ex3_cClass_wayA_hit <= fxu_pipe_val and congr_cl_m_upd_wayA_q and wayA_val(0); +congr_cl_ex3_upd_wayB <= congr_cl_ex2_ex3_cmp_q and not ex3_thrd_m_q and ex3_xuop_wayB_upd and not ex3_stg_flush; +congr_cl_ex4_upd_wayB <= congr_cl_ex2_ex4_cmp_q and not ex4_thrd_m_q and ex4_xuop_wayB_upd_q and not ex4_stg_flush; +congr_cl_ex5_upd_wayB <= congr_cl_ex2_ex5_cmp_q and not ex5_thrd_m_q and ex5_xuop_wayB_upd_q and not ex5_stg_flush; +congr_cl_m_upd_wayB_d <= congr_cl_ex3_upd_wayB or congr_cl_ex4_upd_wayB or congr_cl_ex5_upd_wayB; +ex3_cClass_wayB_hit <= fxu_pipe_val and congr_cl_m_upd_wayB_q and wayB_val(0); +congr_cl_ex3_upd_wayC <= congr_cl_ex2_ex3_cmp_q and not ex3_thrd_m_q and ex3_xuop_wayC_upd and not ex3_stg_flush; +congr_cl_ex4_upd_wayC <= congr_cl_ex2_ex4_cmp_q and not ex4_thrd_m_q and ex4_xuop_wayC_upd_q and not ex4_stg_flush; +congr_cl_ex5_upd_wayC <= congr_cl_ex2_ex5_cmp_q and not ex5_thrd_m_q and ex5_xuop_wayC_upd_q and not ex5_stg_flush; +congr_cl_m_upd_wayC_d <= congr_cl_ex3_upd_wayC or congr_cl_ex4_upd_wayC or congr_cl_ex5_upd_wayC; +ex3_cClass_wayC_hit <= fxu_pipe_val and congr_cl_m_upd_wayC_q and wayC_val(0); +congr_cl_ex3_upd_wayD <= congr_cl_ex2_ex3_cmp_q and not ex3_thrd_m_q and ex3_xuop_wayD_upd and not ex3_stg_flush; +congr_cl_ex4_upd_wayD <= congr_cl_ex2_ex4_cmp_q and not ex4_thrd_m_q and ex4_xuop_wayD_upd_q and not ex4_stg_flush; +congr_cl_ex5_upd_wayD <= congr_cl_ex2_ex5_cmp_q and not ex5_thrd_m_q and ex5_xuop_wayD_upd_q and not ex5_stg_flush; +congr_cl_m_upd_wayD_d <= congr_cl_ex3_upd_wayD or congr_cl_ex4_upd_wayD or congr_cl_ex5_upd_wayD; +ex3_cClass_wayD_hit <= fxu_pipe_val and congr_cl_m_upd_wayD_q and wayD_val(0); +congr_cl_ex3_upd_wayE <= congr_cl_ex2_ex3_cmp_q and not ex3_thrd_m_q and ex3_xuop_wayE_upd and not ex3_stg_flush; +congr_cl_ex4_upd_wayE <= congr_cl_ex2_ex4_cmp_q and not ex4_thrd_m_q and ex4_xuop_wayE_upd_q and not ex4_stg_flush; +congr_cl_ex5_upd_wayE <= congr_cl_ex2_ex5_cmp_q and not ex5_thrd_m_q and ex5_xuop_wayE_upd_q and not ex5_stg_flush; +congr_cl_m_upd_wayE_d <= congr_cl_ex3_upd_wayE or congr_cl_ex4_upd_wayE or congr_cl_ex5_upd_wayE; +ex3_cClass_wayE_hit <= fxu_pipe_val and congr_cl_m_upd_wayE_q and wayE_val(0); +congr_cl_ex3_upd_wayF <= congr_cl_ex2_ex3_cmp_q and not ex3_thrd_m_q and ex3_xuop_wayF_upd and not ex3_stg_flush; +congr_cl_ex4_upd_wayF <= congr_cl_ex2_ex4_cmp_q and not ex4_thrd_m_q and ex4_xuop_wayF_upd_q and not ex4_stg_flush; +congr_cl_ex5_upd_wayF <= congr_cl_ex2_ex5_cmp_q and not ex5_thrd_m_q and ex5_xuop_wayF_upd_q and not ex5_stg_flush; +congr_cl_m_upd_wayF_d <= congr_cl_ex3_upd_wayF or congr_cl_ex4_upd_wayF or congr_cl_ex5_upd_wayF; +ex3_cClass_wayF_hit <= fxu_pipe_val and congr_cl_m_upd_wayF_q and wayF_val(0); +congr_cl_ex3_upd_wayG <= congr_cl_ex2_ex3_cmp_q and not ex3_thrd_m_q and ex3_xuop_wayG_upd and not ex3_stg_flush; +congr_cl_ex4_upd_wayG <= congr_cl_ex2_ex4_cmp_q and not ex4_thrd_m_q and ex4_xuop_wayG_upd_q and not ex4_stg_flush; +congr_cl_ex5_upd_wayG <= congr_cl_ex2_ex5_cmp_q and not ex5_thrd_m_q and ex5_xuop_wayG_upd_q and not ex5_stg_flush; +congr_cl_m_upd_wayG_d <= congr_cl_ex3_upd_wayG or congr_cl_ex4_upd_wayG or congr_cl_ex5_upd_wayG; +ex3_cClass_wayG_hit <= fxu_pipe_val and congr_cl_m_upd_wayG_q and wayG_val(0); +congr_cl_ex3_upd_wayH <= congr_cl_ex2_ex3_cmp_q and not ex3_thrd_m_q and ex3_xuop_wayH_upd and not ex3_stg_flush; +congr_cl_ex4_upd_wayH <= congr_cl_ex2_ex4_cmp_q and not ex4_thrd_m_q and ex4_xuop_wayH_upd_q and not ex4_stg_flush; +congr_cl_ex5_upd_wayH <= congr_cl_ex2_ex5_cmp_q and not ex5_thrd_m_q and ex5_xuop_wayH_upd_q and not ex5_stg_flush; +congr_cl_m_upd_wayH_d <= congr_cl_ex3_upd_wayH or congr_cl_ex4_upd_wayH or congr_cl_ex5_upd_wayH; +ex3_cClass_wayH_hit <= fxu_pipe_val and congr_cl_m_upd_wayH_q and wayH_val(0); +ex3_wclr_all_upd_val <= ex3_watch_clr_all_q and not ex3_thrd_m_q and not ex3_stg_flush; +ex4_wclr_all_upd_val <= ex4_wclr_all_val_q and not ex4_thrd_m_q and not ex4_stg_flush; +ex5_wclr_all_upd_val <= ex5_wclr_all_val_q and not ex5_thrd_m_q and not ex5_stg_flush; +ex6_wclr_all_upd_val <= ex6_wclr_all_val_q and not ex6_thrd_m_q; +ex3_wclr_all_upd_d <= ex3_wclr_all_upd_val or ex4_wclr_all_upd_val or ex5_wclr_all_upd_val or ex6_wclr_all_upd_val; +with rel_congr_cl_q select + rel_arr_wayA_val <= + congr_cl0_wA_q when "000000", + congr_cl1_wA_q when "000001", + congr_cl2_wA_q when "000010", + congr_cl3_wA_q when "000011", + congr_cl4_wA_q when "000100", + congr_cl5_wA_q when "000101", + congr_cl6_wA_q when "000110", + congr_cl7_wA_q when "000111", + congr_cl8_wA_q when "001000", + congr_cl9_wA_q when "001001", + congr_cl10_wA_q when "001010", + congr_cl11_wA_q when "001011", + congr_cl12_wA_q when "001100", + congr_cl13_wA_q when "001101", + congr_cl14_wA_q when "001110", + congr_cl15_wA_q when "001111", + congr_cl16_wA_q when "010000", + congr_cl17_wA_q when "010001", + congr_cl18_wA_q when "010010", + congr_cl19_wA_q when "010011", + congr_cl20_wA_q when "010100", + congr_cl21_wA_q when "010101", + congr_cl22_wA_q when "010110", + congr_cl23_wA_q when "010111", + congr_cl24_wA_q when "011000", + congr_cl25_wA_q when "011001", + congr_cl26_wA_q when "011010", + congr_cl27_wA_q when "011011", + congr_cl28_wA_q when "011100", + congr_cl29_wA_q when "011101", + congr_cl30_wA_q when "011110", + congr_cl31_wA_q when "011111", + congr_cl32_wA_q when "100000", + congr_cl33_wA_q when "100001", + congr_cl34_wA_q when "100010", + congr_cl35_wA_q when "100011", + congr_cl36_wA_q when "100100", + congr_cl37_wA_q when "100101", + congr_cl38_wA_q when "100110", + congr_cl39_wA_q when "100111", + congr_cl40_wA_q when "101000", + congr_cl41_wA_q when "101001", + congr_cl42_wA_q when "101010", + congr_cl43_wA_q when "101011", + congr_cl44_wA_q when "101100", + congr_cl45_wA_q when "101101", + congr_cl46_wA_q when "101110", + congr_cl47_wA_q when "101111", + congr_cl48_wA_q when "110000", + congr_cl49_wA_q when "110001", + congr_cl50_wA_q when "110010", + congr_cl51_wA_q when "110011", + congr_cl52_wA_q when "110100", + congr_cl53_wA_q when "110101", + congr_cl54_wA_q when "110110", + congr_cl55_wA_q when "110111", + congr_cl56_wA_q when "111000", + congr_cl57_wA_q when "111001", + congr_cl58_wA_q when "111010", + congr_cl59_wA_q when "111011", + congr_cl60_wA_q when "111100", + congr_cl61_wA_q when "111101", + congr_cl62_wA_q when "111110", + congr_cl63_wA_q when others; +p1_arr_wayA_rd <= rel_arr_wayA_val; +with rel_congr_cl_q select + rel_arr_wayB_val <= + congr_cl0_wB_q when "000000", + congr_cl1_wB_q when "000001", + congr_cl2_wB_q when "000010", + congr_cl3_wB_q when "000011", + congr_cl4_wB_q when "000100", + congr_cl5_wB_q when "000101", + congr_cl6_wB_q when "000110", + congr_cl7_wB_q when "000111", + congr_cl8_wB_q when "001000", + congr_cl9_wB_q when "001001", + congr_cl10_wB_q when "001010", + congr_cl11_wB_q when "001011", + congr_cl12_wB_q when "001100", + congr_cl13_wB_q when "001101", + congr_cl14_wB_q when "001110", + congr_cl15_wB_q when "001111", + congr_cl16_wB_q when "010000", + congr_cl17_wB_q when "010001", + congr_cl18_wB_q when "010010", + congr_cl19_wB_q when "010011", + congr_cl20_wB_q when "010100", + congr_cl21_wB_q when "010101", + congr_cl22_wB_q when "010110", + congr_cl23_wB_q when "010111", + congr_cl24_wB_q when "011000", + congr_cl25_wB_q when "011001", + congr_cl26_wB_q when "011010", + congr_cl27_wB_q when "011011", + congr_cl28_wB_q when "011100", + congr_cl29_wB_q when "011101", + congr_cl30_wB_q when "011110", + congr_cl31_wB_q when "011111", + congr_cl32_wB_q when "100000", + congr_cl33_wB_q when "100001", + congr_cl34_wB_q when "100010", + congr_cl35_wB_q when "100011", + congr_cl36_wB_q when "100100", + congr_cl37_wB_q when "100101", + congr_cl38_wB_q when "100110", + congr_cl39_wB_q when "100111", + congr_cl40_wB_q when "101000", + congr_cl41_wB_q when "101001", + congr_cl42_wB_q when "101010", + congr_cl43_wB_q when "101011", + congr_cl44_wB_q when "101100", + congr_cl45_wB_q when "101101", + congr_cl46_wB_q when "101110", + congr_cl47_wB_q when "101111", + congr_cl48_wB_q when "110000", + congr_cl49_wB_q when "110001", + congr_cl50_wB_q when "110010", + congr_cl51_wB_q when "110011", + congr_cl52_wB_q when "110100", + congr_cl53_wB_q when "110101", + congr_cl54_wB_q when "110110", + congr_cl55_wB_q when "110111", + congr_cl56_wB_q when "111000", + congr_cl57_wB_q when "111001", + congr_cl58_wB_q when "111010", + congr_cl59_wB_q when "111011", + congr_cl60_wB_q when "111100", + congr_cl61_wB_q when "111101", + congr_cl62_wB_q when "111110", + congr_cl63_wB_q when others; +p1_arr_wayB_rd <= rel_arr_wayB_val; +with rel_congr_cl_q select + rel_arr_wayC_val <= + congr_cl0_wC_q when "000000", + congr_cl1_wC_q when "000001", + congr_cl2_wC_q when "000010", + congr_cl3_wC_q when "000011", + congr_cl4_wC_q when "000100", + congr_cl5_wC_q when "000101", + congr_cl6_wC_q when "000110", + congr_cl7_wC_q when "000111", + congr_cl8_wC_q when "001000", + congr_cl9_wC_q when "001001", + congr_cl10_wC_q when "001010", + congr_cl11_wC_q when "001011", + congr_cl12_wC_q when "001100", + congr_cl13_wC_q when "001101", + congr_cl14_wC_q when "001110", + congr_cl15_wC_q when "001111", + congr_cl16_wC_q when "010000", + congr_cl17_wC_q when "010001", + congr_cl18_wC_q when "010010", + congr_cl19_wC_q when "010011", + congr_cl20_wC_q when "010100", + congr_cl21_wC_q when "010101", + congr_cl22_wC_q when "010110", + congr_cl23_wC_q when "010111", + congr_cl24_wC_q when "011000", + congr_cl25_wC_q when "011001", + congr_cl26_wC_q when "011010", + congr_cl27_wC_q when "011011", + congr_cl28_wC_q when "011100", + congr_cl29_wC_q when "011101", + congr_cl30_wC_q when "011110", + congr_cl31_wC_q when "011111", + congr_cl32_wC_q when "100000", + congr_cl33_wC_q when "100001", + congr_cl34_wC_q when "100010", + congr_cl35_wC_q when "100011", + congr_cl36_wC_q when "100100", + congr_cl37_wC_q when "100101", + congr_cl38_wC_q when "100110", + congr_cl39_wC_q when "100111", + congr_cl40_wC_q when "101000", + congr_cl41_wC_q when "101001", + congr_cl42_wC_q when "101010", + congr_cl43_wC_q when "101011", + congr_cl44_wC_q when "101100", + congr_cl45_wC_q when "101101", + congr_cl46_wC_q when "101110", + congr_cl47_wC_q when "101111", + congr_cl48_wC_q when "110000", + congr_cl49_wC_q when "110001", + congr_cl50_wC_q when "110010", + congr_cl51_wC_q when "110011", + congr_cl52_wC_q when "110100", + congr_cl53_wC_q when "110101", + congr_cl54_wC_q when "110110", + congr_cl55_wC_q when "110111", + congr_cl56_wC_q when "111000", + congr_cl57_wC_q when "111001", + congr_cl58_wC_q when "111010", + congr_cl59_wC_q when "111011", + congr_cl60_wC_q when "111100", + congr_cl61_wC_q when "111101", + congr_cl62_wC_q when "111110", + congr_cl63_wC_q when others; +p1_arr_wayC_rd <= rel_arr_wayC_val; +with rel_congr_cl_q select + rel_arr_wayD_val <= + congr_cl0_wD_q when "000000", + congr_cl1_wD_q when "000001", + congr_cl2_wD_q when "000010", + congr_cl3_wD_q when "000011", + congr_cl4_wD_q when "000100", + congr_cl5_wD_q when "000101", + congr_cl6_wD_q when "000110", + congr_cl7_wD_q when "000111", + congr_cl8_wD_q when "001000", + congr_cl9_wD_q when "001001", + congr_cl10_wD_q when "001010", + congr_cl11_wD_q when "001011", + congr_cl12_wD_q when "001100", + congr_cl13_wD_q when "001101", + congr_cl14_wD_q when "001110", + congr_cl15_wD_q when "001111", + congr_cl16_wD_q when "010000", + congr_cl17_wD_q when "010001", + congr_cl18_wD_q when "010010", + congr_cl19_wD_q when "010011", + congr_cl20_wD_q when "010100", + congr_cl21_wD_q when "010101", + congr_cl22_wD_q when "010110", + congr_cl23_wD_q when "010111", + congr_cl24_wD_q when "011000", + congr_cl25_wD_q when "011001", + congr_cl26_wD_q when "011010", + congr_cl27_wD_q when "011011", + congr_cl28_wD_q when "011100", + congr_cl29_wD_q when "011101", + congr_cl30_wD_q when "011110", + congr_cl31_wD_q when "011111", + congr_cl32_wD_q when "100000", + congr_cl33_wD_q when "100001", + congr_cl34_wD_q when "100010", + congr_cl35_wD_q when "100011", + congr_cl36_wD_q when "100100", + congr_cl37_wD_q when "100101", + congr_cl38_wD_q when "100110", + congr_cl39_wD_q when "100111", + congr_cl40_wD_q when "101000", + congr_cl41_wD_q when "101001", + congr_cl42_wD_q when "101010", + congr_cl43_wD_q when "101011", + congr_cl44_wD_q when "101100", + congr_cl45_wD_q when "101101", + congr_cl46_wD_q when "101110", + congr_cl47_wD_q when "101111", + congr_cl48_wD_q when "110000", + congr_cl49_wD_q when "110001", + congr_cl50_wD_q when "110010", + congr_cl51_wD_q when "110011", + congr_cl52_wD_q when "110100", + congr_cl53_wD_q when "110101", + congr_cl54_wD_q when "110110", + congr_cl55_wD_q when "110111", + congr_cl56_wD_q when "111000", + congr_cl57_wD_q when "111001", + congr_cl58_wD_q when "111010", + congr_cl59_wD_q when "111011", + congr_cl60_wD_q when "111100", + congr_cl61_wD_q when "111101", + congr_cl62_wD_q when "111110", + congr_cl63_wD_q when others; +p1_arr_wayD_rd <= rel_arr_wayD_val; +with rel_congr_cl_q select + rel_arr_wayE_val <= + congr_cl0_wE_q when "000000", + congr_cl1_wE_q when "000001", + congr_cl2_wE_q when "000010", + congr_cl3_wE_q when "000011", + congr_cl4_wE_q when "000100", + congr_cl5_wE_q when "000101", + congr_cl6_wE_q when "000110", + congr_cl7_wE_q when "000111", + congr_cl8_wE_q when "001000", + congr_cl9_wE_q when "001001", + congr_cl10_wE_q when "001010", + congr_cl11_wE_q when "001011", + congr_cl12_wE_q when "001100", + congr_cl13_wE_q when "001101", + congr_cl14_wE_q when "001110", + congr_cl15_wE_q when "001111", + congr_cl16_wE_q when "010000", + congr_cl17_wE_q when "010001", + congr_cl18_wE_q when "010010", + congr_cl19_wE_q when "010011", + congr_cl20_wE_q when "010100", + congr_cl21_wE_q when "010101", + congr_cl22_wE_q when "010110", + congr_cl23_wE_q when "010111", + congr_cl24_wE_q when "011000", + congr_cl25_wE_q when "011001", + congr_cl26_wE_q when "011010", + congr_cl27_wE_q when "011011", + congr_cl28_wE_q when "011100", + congr_cl29_wE_q when "011101", + congr_cl30_wE_q when "011110", + congr_cl31_wE_q when "011111", + congr_cl32_wE_q when "100000", + congr_cl33_wE_q when "100001", + congr_cl34_wE_q when "100010", + congr_cl35_wE_q when "100011", + congr_cl36_wE_q when "100100", + congr_cl37_wE_q when "100101", + congr_cl38_wE_q when "100110", + congr_cl39_wE_q when "100111", + congr_cl40_wE_q when "101000", + congr_cl41_wE_q when "101001", + congr_cl42_wE_q when "101010", + congr_cl43_wE_q when "101011", + congr_cl44_wE_q when "101100", + congr_cl45_wE_q when "101101", + congr_cl46_wE_q when "101110", + congr_cl47_wE_q when "101111", + congr_cl48_wE_q when "110000", + congr_cl49_wE_q when "110001", + congr_cl50_wE_q when "110010", + congr_cl51_wE_q when "110011", + congr_cl52_wE_q when "110100", + congr_cl53_wE_q when "110101", + congr_cl54_wE_q when "110110", + congr_cl55_wE_q when "110111", + congr_cl56_wE_q when "111000", + congr_cl57_wE_q when "111001", + congr_cl58_wE_q when "111010", + congr_cl59_wE_q when "111011", + congr_cl60_wE_q when "111100", + congr_cl61_wE_q when "111101", + congr_cl62_wE_q when "111110", + congr_cl63_wE_q when others; +p1_arr_wayE_rd <= rel_arr_wayE_val; +with rel_congr_cl_q select + rel_arr_wayF_val <= + congr_cl0_wF_q when "000000", + congr_cl1_wF_q when "000001", + congr_cl2_wF_q when "000010", + congr_cl3_wF_q when "000011", + congr_cl4_wF_q when "000100", + congr_cl5_wF_q when "000101", + congr_cl6_wF_q when "000110", + congr_cl7_wF_q when "000111", + congr_cl8_wF_q when "001000", + congr_cl9_wF_q when "001001", + congr_cl10_wF_q when "001010", + congr_cl11_wF_q when "001011", + congr_cl12_wF_q when "001100", + congr_cl13_wF_q when "001101", + congr_cl14_wF_q when "001110", + congr_cl15_wF_q when "001111", + congr_cl16_wF_q when "010000", + congr_cl17_wF_q when "010001", + congr_cl18_wF_q when "010010", + congr_cl19_wF_q when "010011", + congr_cl20_wF_q when "010100", + congr_cl21_wF_q when "010101", + congr_cl22_wF_q when "010110", + congr_cl23_wF_q when "010111", + congr_cl24_wF_q when "011000", + congr_cl25_wF_q when "011001", + congr_cl26_wF_q when "011010", + congr_cl27_wF_q when "011011", + congr_cl28_wF_q when "011100", + congr_cl29_wF_q when "011101", + congr_cl30_wF_q when "011110", + congr_cl31_wF_q when "011111", + congr_cl32_wF_q when "100000", + congr_cl33_wF_q when "100001", + congr_cl34_wF_q when "100010", + congr_cl35_wF_q when "100011", + congr_cl36_wF_q when "100100", + congr_cl37_wF_q when "100101", + congr_cl38_wF_q when "100110", + congr_cl39_wF_q when "100111", + congr_cl40_wF_q when "101000", + congr_cl41_wF_q when "101001", + congr_cl42_wF_q when "101010", + congr_cl43_wF_q when "101011", + congr_cl44_wF_q when "101100", + congr_cl45_wF_q when "101101", + congr_cl46_wF_q when "101110", + congr_cl47_wF_q when "101111", + congr_cl48_wF_q when "110000", + congr_cl49_wF_q when "110001", + congr_cl50_wF_q when "110010", + congr_cl51_wF_q when "110011", + congr_cl52_wF_q when "110100", + congr_cl53_wF_q when "110101", + congr_cl54_wF_q when "110110", + congr_cl55_wF_q when "110111", + congr_cl56_wF_q when "111000", + congr_cl57_wF_q when "111001", + congr_cl58_wF_q when "111010", + congr_cl59_wF_q when "111011", + congr_cl60_wF_q when "111100", + congr_cl61_wF_q when "111101", + congr_cl62_wF_q when "111110", + congr_cl63_wF_q when others; +p1_arr_wayF_rd <= rel_arr_wayF_val; +with rel_congr_cl_q select + rel_arr_wayG_val <= + congr_cl0_wG_q when "000000", + congr_cl1_wG_q when "000001", + congr_cl2_wG_q when "000010", + congr_cl3_wG_q when "000011", + congr_cl4_wG_q when "000100", + congr_cl5_wG_q when "000101", + congr_cl6_wG_q when "000110", + congr_cl7_wG_q when "000111", + congr_cl8_wG_q when "001000", + congr_cl9_wG_q when "001001", + congr_cl10_wG_q when "001010", + congr_cl11_wG_q when "001011", + congr_cl12_wG_q when "001100", + congr_cl13_wG_q when "001101", + congr_cl14_wG_q when "001110", + congr_cl15_wG_q when "001111", + congr_cl16_wG_q when "010000", + congr_cl17_wG_q when "010001", + congr_cl18_wG_q when "010010", + congr_cl19_wG_q when "010011", + congr_cl20_wG_q when "010100", + congr_cl21_wG_q when "010101", + congr_cl22_wG_q when "010110", + congr_cl23_wG_q when "010111", + congr_cl24_wG_q when "011000", + congr_cl25_wG_q when "011001", + congr_cl26_wG_q when "011010", + congr_cl27_wG_q when "011011", + congr_cl28_wG_q when "011100", + congr_cl29_wG_q when "011101", + congr_cl30_wG_q when "011110", + congr_cl31_wG_q when "011111", + congr_cl32_wG_q when "100000", + congr_cl33_wG_q when "100001", + congr_cl34_wG_q when "100010", + congr_cl35_wG_q when "100011", + congr_cl36_wG_q when "100100", + congr_cl37_wG_q when "100101", + congr_cl38_wG_q when "100110", + congr_cl39_wG_q when "100111", + congr_cl40_wG_q when "101000", + congr_cl41_wG_q when "101001", + congr_cl42_wG_q when "101010", + congr_cl43_wG_q when "101011", + congr_cl44_wG_q when "101100", + congr_cl45_wG_q when "101101", + congr_cl46_wG_q when "101110", + congr_cl47_wG_q when "101111", + congr_cl48_wG_q when "110000", + congr_cl49_wG_q when "110001", + congr_cl50_wG_q when "110010", + congr_cl51_wG_q when "110011", + congr_cl52_wG_q when "110100", + congr_cl53_wG_q when "110101", + congr_cl54_wG_q when "110110", + congr_cl55_wG_q when "110111", + congr_cl56_wG_q when "111000", + congr_cl57_wG_q when "111001", + congr_cl58_wG_q when "111010", + congr_cl59_wG_q when "111011", + congr_cl60_wG_q when "111100", + congr_cl61_wG_q when "111101", + congr_cl62_wG_q when "111110", + congr_cl63_wG_q when others; +p1_arr_wayG_rd <= rel_arr_wayG_val; +with rel_congr_cl_q select + rel_arr_wayH_val <= + congr_cl0_wH_q when "000000", + congr_cl1_wH_q when "000001", + congr_cl2_wH_q when "000010", + congr_cl3_wH_q when "000011", + congr_cl4_wH_q when "000100", + congr_cl5_wH_q when "000101", + congr_cl6_wH_q when "000110", + congr_cl7_wH_q when "000111", + congr_cl8_wH_q when "001000", + congr_cl9_wH_q when "001001", + congr_cl10_wH_q when "001010", + congr_cl11_wH_q when "001011", + congr_cl12_wH_q when "001100", + congr_cl13_wH_q when "001101", + congr_cl14_wH_q when "001110", + congr_cl15_wH_q when "001111", + congr_cl16_wH_q when "010000", + congr_cl17_wH_q when "010001", + congr_cl18_wH_q when "010010", + congr_cl19_wH_q when "010011", + congr_cl20_wH_q when "010100", + congr_cl21_wH_q when "010101", + congr_cl22_wH_q when "010110", + congr_cl23_wH_q when "010111", + congr_cl24_wH_q when "011000", + congr_cl25_wH_q when "011001", + congr_cl26_wH_q when "011010", + congr_cl27_wH_q when "011011", + congr_cl28_wH_q when "011100", + congr_cl29_wH_q when "011101", + congr_cl30_wH_q when "011110", + congr_cl31_wH_q when "011111", + congr_cl32_wH_q when "100000", + congr_cl33_wH_q when "100001", + congr_cl34_wH_q when "100010", + congr_cl35_wH_q when "100011", + congr_cl36_wH_q when "100100", + congr_cl37_wH_q when "100101", + congr_cl38_wH_q when "100110", + congr_cl39_wH_q when "100111", + congr_cl40_wH_q when "101000", + congr_cl41_wH_q when "101001", + congr_cl42_wH_q when "101010", + congr_cl43_wH_q when "101011", + congr_cl44_wH_q when "101100", + congr_cl45_wH_q when "101101", + congr_cl46_wH_q when "101110", + congr_cl47_wH_q when "101111", + congr_cl48_wH_q when "110000", + congr_cl49_wH_q when "110001", + congr_cl50_wH_q when "110010", + congr_cl51_wH_q when "110011", + congr_cl52_wH_q when "110100", + congr_cl53_wH_q when "110101", + congr_cl54_wH_q when "110110", + congr_cl55_wH_q when "110111", + congr_cl56_wH_q when "111000", + congr_cl57_wH_q when "111001", + congr_cl58_wH_q when "111010", + congr_cl59_wH_q when "111011", + congr_cl60_wH_q when "111100", + congr_cl61_wH_q when "111101", + congr_cl62_wH_q when "111110", + congr_cl63_wH_q when others; +p1_arr_wayH_rd <= rel_arr_wayH_val; +congr_cl_rel13_ex3_cmp_d <= (rel_early_congr_cl = ex2_congr_cl_q); +congr_cl_rel13_ex4_cmp_d <= (rel_early_congr_cl = ex3_congr_cl_q); +congr_cl_rel13_ex5_cmp_d <= (rel_early_congr_cl = ex4_congr_cl_q); +congr_cl_rel13_ex6_cmp_d <= (rel_early_congr_cl = ex5_congr_cl_q); +congr_cl_rel13_relu_cmp_d <= (rel_early_congr_cl = rel24_congr_cl_q); +congr_cl_rel13_relu_s_cmp_d <= (rel_early_congr_cl = relu_congr_cl_q); +congr_cl_rel13_rel_upd_cmp_d <= (rel_early_congr_cl = relu_s_congr_cl_q); +congr_cl_rel13_p0_cmp <= congr_cl_rel13_ex6_cmp_q and p0_wren_cpy_q; +congr_cl_rel13_p1_cmp <= congr_cl_rel13_rel_upd_cmp_q and p1_wren_cpy_q; +congr_cl_rel13_ex3_m <= congr_cl_rel13_ex3_cmp_q and (ex3_lock_set_q or back_inval_stg3_q); +congr_cl_rel13_ex4_m <= congr_cl_rel13_ex4_cmp_q and (ex4_lock_set_q or back_inval_stg4_q); +congr_cl_rel13_ex5_m <= congr_cl_rel13_ex5_cmp_q and (ex5_lock_set_q or back_inval_stg5_q); +congr_cl_rel13_relu_m <= congr_cl_rel13_relu_cmp_q and rel_val_stgu_q; +congr_cl_rel13_relu_s_m <= congr_cl_rel13_relu_s_cmp_q and p1_upd_val; +congr_cl_rel13_wayA_byp(1) <= congr_cl_rel13_ex3_m and ex3_wayA_hit; +congr_cl_rel13_wayA_byp(2) <= congr_cl_rel13_relu_m and reload_wayA_upd_q; +congr_cl_rel13_wayA_byp(3) <= congr_cl_rel13_ex4_m and binv_wayA_upd_q; +congr_cl_rel13_wayA_byp(4) <= congr_cl_rel13_relu_s_m and reload_wayA_upd2_q; +congr_cl_rel13_wayA_byp(5) <= congr_cl_rel13_ex5_m and binv_wayA_upd2_q; +congr_cl_rel13_wayA_byp(6) <= congr_cl_rel13_p1_cmp and reload_wayA_upd3_q; +congr_cl_rel13_wayA_byp(7) <= congr_cl_rel13_p0_cmp and binv_wayA_upd3_q; +rel24_wayA_fxubyp_val_d <= congr_cl_rel13_wayA_byp(1) or congr_cl_rel13_wayA_byp(3) or + congr_cl_rel13_wayA_byp(5) or congr_cl_rel13_wayA_byp(7); +rel24_wayA_relbyp_val_d <= congr_cl_rel13_wayA_byp(2) or congr_cl_rel13_wayA_byp(4) or + congr_cl_rel13_wayA_byp(6); +rel24_wayA_byp_sel <= rel24_wayA_fxubyp_val_q & rel24_wayA_relbyp_val_q; +congr_cl_rel13_wayA_sel(2) <= congr_cl_rel13_wayA_byp(2); +congr_cl_rel13_wayA_sel(3) <= congr_cl_rel13_wayA_byp(3) and not congr_cl_rel13_wayA_byp(2); +congr_cl_rel13_wayA_sel(4) <= congr_cl_rel13_wayA_byp(4) and not or_reduce(congr_cl_rel13_wayA_byp(2 to 3)); +congr_cl_rel13_wayA_sel(5) <= congr_cl_rel13_wayA_byp(5) and not or_reduce(congr_cl_rel13_wayA_byp(2 to 4)); +congr_cl_rel13_wayA_sel(6) <= congr_cl_rel13_wayA_byp(6) and not or_reduce(congr_cl_rel13_wayA_byp(2 to 5)); +congr_cl_rel13_wayA_sel(7) <= congr_cl_rel13_wayA_byp(7) and not or_reduce(congr_cl_rel13_wayA_byp(2 to 6)); +rel_wayA_late_sel <= or_reduce(congr_cl_rel13_wayA_byp(2 to 7)); +rel_wayA_later_stg_pri <= gate(p1_arr_wayA_rd, not rel_wayA_late_sel) or + gate(reload_wayA, congr_cl_rel13_wayA_sel(2)) or + gate(flush_wayA_q, congr_cl_rel13_wayA_sel(3)) or + gate(reload_wayA_data_q, congr_cl_rel13_wayA_sel(4)) or + gate(flush_wayA_data_q, congr_cl_rel13_wayA_sel(5)) or + gate(reload_wayA_data2_q, congr_cl_rel13_wayA_sel(6)) or + gate(flush_wayA_data2_q, congr_cl_rel13_wayA_sel(7)); +rel_wayA_early_sel <= congr_cl_rel13_wayA_byp(1); +rel_wayA_early_stg_pri <= flush_wayA_d; +rel_wayA_stg_val <= (others=>(rel_wayA_early_sel)); +rel_wayA_stg_val_b <= (others=>(not(rel_wayA_early_sel))); +rel_wayA_val <= not rel_wayA_val_b_q; +rel_wayA_val_stg_d <= rel_wayA_val; +congr_cl_rel13_wayB_byp(1) <= congr_cl_rel13_ex3_m and ex3_wayB_hit; +congr_cl_rel13_wayB_byp(2) <= congr_cl_rel13_relu_m and reload_wayB_upd_q; +congr_cl_rel13_wayB_byp(3) <= congr_cl_rel13_ex4_m and binv_wayB_upd_q; +congr_cl_rel13_wayB_byp(4) <= congr_cl_rel13_relu_s_m and reload_wayB_upd2_q; +congr_cl_rel13_wayB_byp(5) <= congr_cl_rel13_ex5_m and binv_wayB_upd2_q; +congr_cl_rel13_wayB_byp(6) <= congr_cl_rel13_p1_cmp and reload_wayB_upd3_q; +congr_cl_rel13_wayB_byp(7) <= congr_cl_rel13_p0_cmp and binv_wayB_upd3_q; +rel24_wayB_fxubyp_val_d <= congr_cl_rel13_wayB_byp(1) or congr_cl_rel13_wayB_byp(3) or + congr_cl_rel13_wayB_byp(5) or congr_cl_rel13_wayB_byp(7); +rel24_wayB_relbyp_val_d <= congr_cl_rel13_wayB_byp(2) or congr_cl_rel13_wayB_byp(4) or + congr_cl_rel13_wayB_byp(6); +rel24_wayB_byp_sel <= rel24_wayB_fxubyp_val_q & rel24_wayB_relbyp_val_q; +congr_cl_rel13_wayB_sel(2) <= congr_cl_rel13_wayB_byp(2); +congr_cl_rel13_wayB_sel(3) <= congr_cl_rel13_wayB_byp(3) and not congr_cl_rel13_wayB_byp(2); +congr_cl_rel13_wayB_sel(4) <= congr_cl_rel13_wayB_byp(4) and not or_reduce(congr_cl_rel13_wayB_byp(2 to 3)); +congr_cl_rel13_wayB_sel(5) <= congr_cl_rel13_wayB_byp(5) and not or_reduce(congr_cl_rel13_wayB_byp(2 to 4)); +congr_cl_rel13_wayB_sel(6) <= congr_cl_rel13_wayB_byp(6) and not or_reduce(congr_cl_rel13_wayB_byp(2 to 5)); +congr_cl_rel13_wayB_sel(7) <= congr_cl_rel13_wayB_byp(7) and not or_reduce(congr_cl_rel13_wayB_byp(2 to 6)); +rel_wayB_late_sel <= or_reduce(congr_cl_rel13_wayB_byp(2 to 7)); +rel_wayB_later_stg_pri <= gate(p1_arr_wayB_rd, not rel_wayB_late_sel) or + gate(reload_wayB, congr_cl_rel13_wayB_sel(2)) or + gate(flush_wayB_q, congr_cl_rel13_wayB_sel(3)) or + gate(reload_wayB_data_q, congr_cl_rel13_wayB_sel(4)) or + gate(flush_wayB_data_q, congr_cl_rel13_wayB_sel(5)) or + gate(reload_wayB_data2_q, congr_cl_rel13_wayB_sel(6)) or + gate(flush_wayB_data2_q, congr_cl_rel13_wayB_sel(7)); +rel_wayB_early_sel <= congr_cl_rel13_wayB_byp(1); +rel_wayB_early_stg_pri <= flush_wayB_d; +rel_wayB_stg_val <= (others=>(rel_wayB_early_sel)); +rel_wayB_stg_val_b <= (others=>(not(rel_wayB_early_sel))); +rel_wayB_val <= not rel_wayB_val_b_q; +rel_wayB_val_stg_d <= rel_wayB_val; +congr_cl_rel13_wayC_byp(1) <= congr_cl_rel13_ex3_m and ex3_wayC_hit; +congr_cl_rel13_wayC_byp(2) <= congr_cl_rel13_relu_m and reload_wayC_upd_q; +congr_cl_rel13_wayC_byp(3) <= congr_cl_rel13_ex4_m and binv_wayC_upd_q; +congr_cl_rel13_wayC_byp(4) <= congr_cl_rel13_relu_s_m and reload_wayC_upd2_q; +congr_cl_rel13_wayC_byp(5) <= congr_cl_rel13_ex5_m and binv_wayC_upd2_q; +congr_cl_rel13_wayC_byp(6) <= congr_cl_rel13_p1_cmp and reload_wayC_upd3_q; +congr_cl_rel13_wayC_byp(7) <= congr_cl_rel13_p0_cmp and binv_wayC_upd3_q; +rel24_wayC_fxubyp_val_d <= congr_cl_rel13_wayC_byp(1) or congr_cl_rel13_wayC_byp(3) or + congr_cl_rel13_wayC_byp(5) or congr_cl_rel13_wayC_byp(7); +rel24_wayC_relbyp_val_d <= congr_cl_rel13_wayC_byp(2) or congr_cl_rel13_wayC_byp(4) or + congr_cl_rel13_wayC_byp(6); +rel24_wayC_byp_sel <= rel24_wayC_fxubyp_val_q & rel24_wayC_relbyp_val_q; +congr_cl_rel13_wayC_sel(2) <= congr_cl_rel13_wayC_byp(2); +congr_cl_rel13_wayC_sel(3) <= congr_cl_rel13_wayC_byp(3) and not congr_cl_rel13_wayC_byp(2); +congr_cl_rel13_wayC_sel(4) <= congr_cl_rel13_wayC_byp(4) and not or_reduce(congr_cl_rel13_wayC_byp(2 to 3)); +congr_cl_rel13_wayC_sel(5) <= congr_cl_rel13_wayC_byp(5) and not or_reduce(congr_cl_rel13_wayC_byp(2 to 4)); +congr_cl_rel13_wayC_sel(6) <= congr_cl_rel13_wayC_byp(6) and not or_reduce(congr_cl_rel13_wayC_byp(2 to 5)); +congr_cl_rel13_wayC_sel(7) <= congr_cl_rel13_wayC_byp(7) and not or_reduce(congr_cl_rel13_wayC_byp(2 to 6)); +rel_wayC_late_sel <= or_reduce(congr_cl_rel13_wayC_byp(2 to 7)); +rel_wayC_later_stg_pri <= gate(p1_arr_wayC_rd, not rel_wayC_late_sel) or + gate(reload_wayC, congr_cl_rel13_wayC_sel(2)) or + gate(flush_wayC_q, congr_cl_rel13_wayC_sel(3)) or + gate(reload_wayC_data_q, congr_cl_rel13_wayC_sel(4)) or + gate(flush_wayC_data_q, congr_cl_rel13_wayC_sel(5)) or + gate(reload_wayC_data2_q, congr_cl_rel13_wayC_sel(6)) or + gate(flush_wayC_data2_q, congr_cl_rel13_wayC_sel(7)); +rel_wayC_early_sel <= congr_cl_rel13_wayC_byp(1); +rel_wayC_early_stg_pri <= flush_wayC_d; +rel_wayC_stg_val <= (others=>(rel_wayC_early_sel)); +rel_wayC_stg_val_b <= (others=>(not(rel_wayC_early_sel))); +rel_wayC_val <= not rel_wayC_val_b_q; +rel_wayC_val_stg_d <= rel_wayC_val; +congr_cl_rel13_wayD_byp(1) <= congr_cl_rel13_ex3_m and ex3_wayD_hit; +congr_cl_rel13_wayD_byp(2) <= congr_cl_rel13_relu_m and reload_wayD_upd_q; +congr_cl_rel13_wayD_byp(3) <= congr_cl_rel13_ex4_m and binv_wayD_upd_q; +congr_cl_rel13_wayD_byp(4) <= congr_cl_rel13_relu_s_m and reload_wayD_upd2_q; +congr_cl_rel13_wayD_byp(5) <= congr_cl_rel13_ex5_m and binv_wayD_upd2_q; +congr_cl_rel13_wayD_byp(6) <= congr_cl_rel13_p1_cmp and reload_wayD_upd3_q; +congr_cl_rel13_wayD_byp(7) <= congr_cl_rel13_p0_cmp and binv_wayD_upd3_q; +rel24_wayD_fxubyp_val_d <= congr_cl_rel13_wayD_byp(1) or congr_cl_rel13_wayD_byp(3) or + congr_cl_rel13_wayD_byp(5) or congr_cl_rel13_wayD_byp(7); +rel24_wayD_relbyp_val_d <= congr_cl_rel13_wayD_byp(2) or congr_cl_rel13_wayD_byp(4) or + congr_cl_rel13_wayD_byp(6); +rel24_wayD_byp_sel <= rel24_wayD_fxubyp_val_q & rel24_wayD_relbyp_val_q; +congr_cl_rel13_wayD_sel(2) <= congr_cl_rel13_wayD_byp(2); +congr_cl_rel13_wayD_sel(3) <= congr_cl_rel13_wayD_byp(3) and not congr_cl_rel13_wayD_byp(2); +congr_cl_rel13_wayD_sel(4) <= congr_cl_rel13_wayD_byp(4) and not or_reduce(congr_cl_rel13_wayD_byp(2 to 3)); +congr_cl_rel13_wayD_sel(5) <= congr_cl_rel13_wayD_byp(5) and not or_reduce(congr_cl_rel13_wayD_byp(2 to 4)); +congr_cl_rel13_wayD_sel(6) <= congr_cl_rel13_wayD_byp(6) and not or_reduce(congr_cl_rel13_wayD_byp(2 to 5)); +congr_cl_rel13_wayD_sel(7) <= congr_cl_rel13_wayD_byp(7) and not or_reduce(congr_cl_rel13_wayD_byp(2 to 6)); +rel_wayD_late_sel <= or_reduce(congr_cl_rel13_wayD_byp(2 to 7)); +rel_wayD_later_stg_pri <= gate(p1_arr_wayD_rd, not rel_wayD_late_sel) or + gate(reload_wayD, congr_cl_rel13_wayD_sel(2)) or + gate(flush_wayD_q, congr_cl_rel13_wayD_sel(3)) or + gate(reload_wayD_data_q, congr_cl_rel13_wayD_sel(4)) or + gate(flush_wayD_data_q, congr_cl_rel13_wayD_sel(5)) or + gate(reload_wayD_data2_q, congr_cl_rel13_wayD_sel(6)) or + gate(flush_wayD_data2_q, congr_cl_rel13_wayD_sel(7)); +rel_wayD_early_sel <= congr_cl_rel13_wayD_byp(1); +rel_wayD_early_stg_pri <= flush_wayD_d; +rel_wayD_stg_val <= (others=>(rel_wayD_early_sel)); +rel_wayD_stg_val_b <= (others=>(not(rel_wayD_early_sel))); +rel_wayD_val <= not rel_wayD_val_b_q; +rel_wayD_val_stg_d <= rel_wayD_val; +congr_cl_rel13_wayE_byp(1) <= congr_cl_rel13_ex3_m and ex3_wayE_hit; +congr_cl_rel13_wayE_byp(2) <= congr_cl_rel13_relu_m and reload_wayE_upd_q; +congr_cl_rel13_wayE_byp(3) <= congr_cl_rel13_ex4_m and binv_wayE_upd_q; +congr_cl_rel13_wayE_byp(4) <= congr_cl_rel13_relu_s_m and reload_wayE_upd2_q; +congr_cl_rel13_wayE_byp(5) <= congr_cl_rel13_ex5_m and binv_wayE_upd2_q; +congr_cl_rel13_wayE_byp(6) <= congr_cl_rel13_p1_cmp and reload_wayE_upd3_q; +congr_cl_rel13_wayE_byp(7) <= congr_cl_rel13_p0_cmp and binv_wayE_upd3_q; +rel24_wayE_fxubyp_val_d <= congr_cl_rel13_wayE_byp(1) or congr_cl_rel13_wayE_byp(3) or + congr_cl_rel13_wayE_byp(5) or congr_cl_rel13_wayE_byp(7); +rel24_wayE_relbyp_val_d <= congr_cl_rel13_wayE_byp(2) or congr_cl_rel13_wayE_byp(4) or + congr_cl_rel13_wayE_byp(6); +rel24_wayE_byp_sel <= rel24_wayE_fxubyp_val_q & rel24_wayE_relbyp_val_q; +congr_cl_rel13_wayE_sel(2) <= congr_cl_rel13_wayE_byp(2); +congr_cl_rel13_wayE_sel(3) <= congr_cl_rel13_wayE_byp(3) and not congr_cl_rel13_wayE_byp(2); +congr_cl_rel13_wayE_sel(4) <= congr_cl_rel13_wayE_byp(4) and not or_reduce(congr_cl_rel13_wayE_byp(2 to 3)); +congr_cl_rel13_wayE_sel(5) <= congr_cl_rel13_wayE_byp(5) and not or_reduce(congr_cl_rel13_wayE_byp(2 to 4)); +congr_cl_rel13_wayE_sel(6) <= congr_cl_rel13_wayE_byp(6) and not or_reduce(congr_cl_rel13_wayE_byp(2 to 5)); +congr_cl_rel13_wayE_sel(7) <= congr_cl_rel13_wayE_byp(7) and not or_reduce(congr_cl_rel13_wayE_byp(2 to 6)); +rel_wayE_late_sel <= or_reduce(congr_cl_rel13_wayE_byp(2 to 7)); +rel_wayE_later_stg_pri <= gate(p1_arr_wayE_rd, not rel_wayE_late_sel) or + gate(reload_wayE, congr_cl_rel13_wayE_sel(2)) or + gate(flush_wayE_q, congr_cl_rel13_wayE_sel(3)) or + gate(reload_wayE_data_q, congr_cl_rel13_wayE_sel(4)) or + gate(flush_wayE_data_q, congr_cl_rel13_wayE_sel(5)) or + gate(reload_wayE_data2_q, congr_cl_rel13_wayE_sel(6)) or + gate(flush_wayE_data2_q, congr_cl_rel13_wayE_sel(7)); +rel_wayE_early_sel <= congr_cl_rel13_wayE_byp(1); +rel_wayE_early_stg_pri <= flush_wayE_d; +rel_wayE_stg_val <= (others=>(rel_wayE_early_sel)); +rel_wayE_stg_val_b <= (others=>(not(rel_wayE_early_sel))); +rel_wayE_val <= not rel_wayE_val_b_q; +rel_wayE_val_stg_d <= rel_wayE_val; +congr_cl_rel13_wayF_byp(1) <= congr_cl_rel13_ex3_m and ex3_wayF_hit; +congr_cl_rel13_wayF_byp(2) <= congr_cl_rel13_relu_m and reload_wayF_upd_q; +congr_cl_rel13_wayF_byp(3) <= congr_cl_rel13_ex4_m and binv_wayF_upd_q; +congr_cl_rel13_wayF_byp(4) <= congr_cl_rel13_relu_s_m and reload_wayF_upd2_q; +congr_cl_rel13_wayF_byp(5) <= congr_cl_rel13_ex5_m and binv_wayF_upd2_q; +congr_cl_rel13_wayF_byp(6) <= congr_cl_rel13_p1_cmp and reload_wayF_upd3_q; +congr_cl_rel13_wayF_byp(7) <= congr_cl_rel13_p0_cmp and binv_wayF_upd3_q; +rel24_wayF_fxubyp_val_d <= congr_cl_rel13_wayF_byp(1) or congr_cl_rel13_wayF_byp(3) or + congr_cl_rel13_wayF_byp(5) or congr_cl_rel13_wayF_byp(7); +rel24_wayF_relbyp_val_d <= congr_cl_rel13_wayF_byp(2) or congr_cl_rel13_wayF_byp(4) or + congr_cl_rel13_wayF_byp(6); +rel24_wayF_byp_sel <= rel24_wayF_fxubyp_val_q & rel24_wayF_relbyp_val_q; +congr_cl_rel13_wayF_sel(2) <= congr_cl_rel13_wayF_byp(2); +congr_cl_rel13_wayF_sel(3) <= congr_cl_rel13_wayF_byp(3) and not congr_cl_rel13_wayF_byp(2); +congr_cl_rel13_wayF_sel(4) <= congr_cl_rel13_wayF_byp(4) and not or_reduce(congr_cl_rel13_wayF_byp(2 to 3)); +congr_cl_rel13_wayF_sel(5) <= congr_cl_rel13_wayF_byp(5) and not or_reduce(congr_cl_rel13_wayF_byp(2 to 4)); +congr_cl_rel13_wayF_sel(6) <= congr_cl_rel13_wayF_byp(6) and not or_reduce(congr_cl_rel13_wayF_byp(2 to 5)); +congr_cl_rel13_wayF_sel(7) <= congr_cl_rel13_wayF_byp(7) and not or_reduce(congr_cl_rel13_wayF_byp(2 to 6)); +rel_wayF_late_sel <= or_reduce(congr_cl_rel13_wayF_byp(2 to 7)); +rel_wayF_later_stg_pri <= gate(p1_arr_wayF_rd, not rel_wayF_late_sel) or + gate(reload_wayF, congr_cl_rel13_wayF_sel(2)) or + gate(flush_wayF_q, congr_cl_rel13_wayF_sel(3)) or + gate(reload_wayF_data_q, congr_cl_rel13_wayF_sel(4)) or + gate(flush_wayF_data_q, congr_cl_rel13_wayF_sel(5)) or + gate(reload_wayF_data2_q, congr_cl_rel13_wayF_sel(6)) or + gate(flush_wayF_data2_q, congr_cl_rel13_wayF_sel(7)); +rel_wayF_early_sel <= congr_cl_rel13_wayF_byp(1); +rel_wayF_early_stg_pri <= flush_wayF_d; +rel_wayF_stg_val <= (others=>(rel_wayF_early_sel)); +rel_wayF_stg_val_b <= (others=>(not(rel_wayF_early_sel))); +rel_wayF_val <= not rel_wayF_val_b_q; +rel_wayF_val_stg_d <= rel_wayF_val; +congr_cl_rel13_wayG_byp(1) <= congr_cl_rel13_ex3_m and ex3_wayG_hit; +congr_cl_rel13_wayG_byp(2) <= congr_cl_rel13_relu_m and reload_wayG_upd_q; +congr_cl_rel13_wayG_byp(3) <= congr_cl_rel13_ex4_m and binv_wayG_upd_q; +congr_cl_rel13_wayG_byp(4) <= congr_cl_rel13_relu_s_m and reload_wayG_upd2_q; +congr_cl_rel13_wayG_byp(5) <= congr_cl_rel13_ex5_m and binv_wayG_upd2_q; +congr_cl_rel13_wayG_byp(6) <= congr_cl_rel13_p1_cmp and reload_wayG_upd3_q; +congr_cl_rel13_wayG_byp(7) <= congr_cl_rel13_p0_cmp and binv_wayG_upd3_q; +rel24_wayG_fxubyp_val_d <= congr_cl_rel13_wayG_byp(1) or congr_cl_rel13_wayG_byp(3) or + congr_cl_rel13_wayG_byp(5) or congr_cl_rel13_wayG_byp(7); +rel24_wayG_relbyp_val_d <= congr_cl_rel13_wayG_byp(2) or congr_cl_rel13_wayG_byp(4) or + congr_cl_rel13_wayG_byp(6); +rel24_wayG_byp_sel <= rel24_wayG_fxubyp_val_q & rel24_wayG_relbyp_val_q; +congr_cl_rel13_wayG_sel(2) <= congr_cl_rel13_wayG_byp(2); +congr_cl_rel13_wayG_sel(3) <= congr_cl_rel13_wayG_byp(3) and not congr_cl_rel13_wayG_byp(2); +congr_cl_rel13_wayG_sel(4) <= congr_cl_rel13_wayG_byp(4) and not or_reduce(congr_cl_rel13_wayG_byp(2 to 3)); +congr_cl_rel13_wayG_sel(5) <= congr_cl_rel13_wayG_byp(5) and not or_reduce(congr_cl_rel13_wayG_byp(2 to 4)); +congr_cl_rel13_wayG_sel(6) <= congr_cl_rel13_wayG_byp(6) and not or_reduce(congr_cl_rel13_wayG_byp(2 to 5)); +congr_cl_rel13_wayG_sel(7) <= congr_cl_rel13_wayG_byp(7) and not or_reduce(congr_cl_rel13_wayG_byp(2 to 6)); +rel_wayG_late_sel <= or_reduce(congr_cl_rel13_wayG_byp(2 to 7)); +rel_wayG_later_stg_pri <= gate(p1_arr_wayG_rd, not rel_wayG_late_sel) or + gate(reload_wayG, congr_cl_rel13_wayG_sel(2)) or + gate(flush_wayG_q, congr_cl_rel13_wayG_sel(3)) or + gate(reload_wayG_data_q, congr_cl_rel13_wayG_sel(4)) or + gate(flush_wayG_data_q, congr_cl_rel13_wayG_sel(5)) or + gate(reload_wayG_data2_q, congr_cl_rel13_wayG_sel(6)) or + gate(flush_wayG_data2_q, congr_cl_rel13_wayG_sel(7)); +rel_wayG_early_sel <= congr_cl_rel13_wayG_byp(1); +rel_wayG_early_stg_pri <= flush_wayG_d; +rel_wayG_stg_val <= (others=>(rel_wayG_early_sel)); +rel_wayG_stg_val_b <= (others=>(not(rel_wayG_early_sel))); +rel_wayG_val <= not rel_wayG_val_b_q; +rel_wayG_val_stg_d <= rel_wayG_val; +congr_cl_rel13_wayH_byp(1) <= congr_cl_rel13_ex3_m and ex3_wayH_hit; +congr_cl_rel13_wayH_byp(2) <= congr_cl_rel13_relu_m and reload_wayH_upd_q; +congr_cl_rel13_wayH_byp(3) <= congr_cl_rel13_ex4_m and binv_wayH_upd_q; +congr_cl_rel13_wayH_byp(4) <= congr_cl_rel13_relu_s_m and reload_wayH_upd2_q; +congr_cl_rel13_wayH_byp(5) <= congr_cl_rel13_ex5_m and binv_wayH_upd2_q; +congr_cl_rel13_wayH_byp(6) <= congr_cl_rel13_p1_cmp and reload_wayH_upd3_q; +congr_cl_rel13_wayH_byp(7) <= congr_cl_rel13_p0_cmp and binv_wayH_upd3_q; +rel24_wayH_fxubyp_val_d <= congr_cl_rel13_wayH_byp(1) or congr_cl_rel13_wayH_byp(3) or + congr_cl_rel13_wayH_byp(5) or congr_cl_rel13_wayH_byp(7); +rel24_wayH_relbyp_val_d <= congr_cl_rel13_wayH_byp(2) or congr_cl_rel13_wayH_byp(4) or + congr_cl_rel13_wayH_byp(6); +rel24_wayH_byp_sel <= rel24_wayH_fxubyp_val_q & rel24_wayH_relbyp_val_q; +congr_cl_rel13_wayH_sel(2) <= congr_cl_rel13_wayH_byp(2); +congr_cl_rel13_wayH_sel(3) <= congr_cl_rel13_wayH_byp(3) and not congr_cl_rel13_wayH_byp(2); +congr_cl_rel13_wayH_sel(4) <= congr_cl_rel13_wayH_byp(4) and not or_reduce(congr_cl_rel13_wayH_byp(2 to 3)); +congr_cl_rel13_wayH_sel(5) <= congr_cl_rel13_wayH_byp(5) and not or_reduce(congr_cl_rel13_wayH_byp(2 to 4)); +congr_cl_rel13_wayH_sel(6) <= congr_cl_rel13_wayH_byp(6) and not or_reduce(congr_cl_rel13_wayH_byp(2 to 5)); +congr_cl_rel13_wayH_sel(7) <= congr_cl_rel13_wayH_byp(7) and not or_reduce(congr_cl_rel13_wayH_byp(2 to 6)); +rel_wayH_late_sel <= or_reduce(congr_cl_rel13_wayH_byp(2 to 7)); +rel_wayH_later_stg_pri <= gate(p1_arr_wayH_rd, not rel_wayH_late_sel) or + gate(reload_wayH, congr_cl_rel13_wayH_sel(2)) or + gate(flush_wayH_q, congr_cl_rel13_wayH_sel(3)) or + gate(reload_wayH_data_q, congr_cl_rel13_wayH_sel(4)) or + gate(flush_wayH_data_q, congr_cl_rel13_wayH_sel(5)) or + gate(reload_wayH_data2_q, congr_cl_rel13_wayH_sel(6)) or + gate(flush_wayH_data2_q, congr_cl_rel13_wayH_sel(7)); +rel_wayH_early_sel <= congr_cl_rel13_wayH_byp(1); +rel_wayH_early_stg_pri <= flush_wayH_d; +rel_wayH_stg_val <= (others=>(rel_wayH_early_sel)); +rel_wayH_stg_val_b <= (others=>(not(rel_wayH_early_sel))); +rel_wayH_val <= not rel_wayH_val_b_q; +rel_wayH_val_stg_d <= rel_wayH_val; +rel_par_wA_clr <= rel_wayA_clr or dcpar_err_way_inval_q(0); +reload_wayA_d(0) <= (not rel_par_wA_clr and rel_wayA_val(0)) or rel_wayA_set; +reload_wayA_d(1) <= (not rel_par_wA_clr and rel_wayA_val(1)) or (rel_lock_set_q and rel_wayA_set); +dcpar_err_lock_lost(0) <= rel_wayA_val(1) and dcpar_err_way_inval_q(0); +reload_wayA_d(2) <= ((not rel_par_wA_clr and rel_wayA_val(2))) or (rel_watch_set_q and rel_wayA_set and rel_thrd_id_q(0)); +reload_wayA_d(3) <= ((not rel_par_wA_clr and rel_wayA_val(3))) or (rel_watch_set_q and rel_wayA_set and rel_thrd_id_q(1)); +reload_wayA_d(4) <= ((not rel_par_wA_clr and rel_wayA_val(4))) or (rel_watch_set_q and rel_wayA_set and rel_thrd_id_q(2)); +reload_wayA_d(5) <= ((not rel_par_wA_clr and rel_wayA_val(5))) or (rel_watch_set_q and rel_wayA_set and rel_thrd_id_q(3)); +reload_wayA_upd_d <= rel_par_wA_clr or rel_wayA_set; +reload_wayA_clr <= rel_par_wA_clr; +rel_par_wB_clr <= rel_wayB_clr or dcpar_err_way_inval_q(1); +reload_wayB_d(0) <= (not rel_par_wB_clr and rel_wayB_val(0)) or rel_wayB_set; +reload_wayB_d(1) <= (not rel_par_wB_clr and rel_wayB_val(1)) or (rel_lock_set_q and rel_wayB_set); +dcpar_err_lock_lost(1) <= rel_wayB_val(1) and dcpar_err_way_inval_q(1); +reload_wayB_d(2) <= ((not rel_par_wB_clr and rel_wayB_val(2))) or (rel_watch_set_q and rel_wayB_set and rel_thrd_id_q(0)); +reload_wayB_d(3) <= ((not rel_par_wB_clr and rel_wayB_val(3))) or (rel_watch_set_q and rel_wayB_set and rel_thrd_id_q(1)); +reload_wayB_d(4) <= ((not rel_par_wB_clr and rel_wayB_val(4))) or (rel_watch_set_q and rel_wayB_set and rel_thrd_id_q(2)); +reload_wayB_d(5) <= ((not rel_par_wB_clr and rel_wayB_val(5))) or (rel_watch_set_q and rel_wayB_set and rel_thrd_id_q(3)); +reload_wayB_upd_d <= rel_par_wB_clr or rel_wayB_set; +reload_wayB_clr <= rel_par_wB_clr; +rel_par_wC_clr <= rel_wayC_clr or dcpar_err_way_inval_q(2); +reload_wayC_d(0) <= (not rel_par_wC_clr and rel_wayC_val(0)) or rel_wayC_set; +reload_wayC_d(1) <= (not rel_par_wC_clr and rel_wayC_val(1)) or (rel_lock_set_q and rel_wayC_set); +dcpar_err_lock_lost(2) <= rel_wayC_val(1) and dcpar_err_way_inval_q(2); +reload_wayC_d(2) <= ((not rel_par_wC_clr and rel_wayC_val(2))) or (rel_watch_set_q and rel_wayC_set and rel_thrd_id_q(0)); +reload_wayC_d(3) <= ((not rel_par_wC_clr and rel_wayC_val(3))) or (rel_watch_set_q and rel_wayC_set and rel_thrd_id_q(1)); +reload_wayC_d(4) <= ((not rel_par_wC_clr and rel_wayC_val(4))) or (rel_watch_set_q and rel_wayC_set and rel_thrd_id_q(2)); +reload_wayC_d(5) <= ((not rel_par_wC_clr and rel_wayC_val(5))) or (rel_watch_set_q and rel_wayC_set and rel_thrd_id_q(3)); +reload_wayC_upd_d <= rel_par_wC_clr or rel_wayC_set; +reload_wayC_clr <= rel_par_wC_clr; +rel_par_wD_clr <= rel_wayD_clr or dcpar_err_way_inval_q(3); +reload_wayD_d(0) <= (not rel_par_wD_clr and rel_wayD_val(0)) or rel_wayD_set; +reload_wayD_d(1) <= (not rel_par_wD_clr and rel_wayD_val(1)) or (rel_lock_set_q and rel_wayD_set); +dcpar_err_lock_lost(3) <= rel_wayD_val(1) and dcpar_err_way_inval_q(3); +reload_wayD_d(2) <= ((not rel_par_wD_clr and rel_wayD_val(2))) or (rel_watch_set_q and rel_wayD_set and rel_thrd_id_q(0)); +reload_wayD_d(3) <= ((not rel_par_wD_clr and rel_wayD_val(3))) or (rel_watch_set_q and rel_wayD_set and rel_thrd_id_q(1)); +reload_wayD_d(4) <= ((not rel_par_wD_clr and rel_wayD_val(4))) or (rel_watch_set_q and rel_wayD_set and rel_thrd_id_q(2)); +reload_wayD_d(5) <= ((not rel_par_wD_clr and rel_wayD_val(5))) or (rel_watch_set_q and rel_wayD_set and rel_thrd_id_q(3)); +reload_wayD_upd_d <= rel_par_wD_clr or rel_wayD_set; +reload_wayD_clr <= rel_par_wD_clr; +rel_par_wE_clr <= rel_wayE_clr or dcpar_err_way_inval_q(4); +reload_wayE_d(0) <= (not rel_par_wE_clr and rel_wayE_val(0)) or rel_wayE_set; +reload_wayE_d(1) <= (not rel_par_wE_clr and rel_wayE_val(1)) or (rel_lock_set_q and rel_wayE_set); +dcpar_err_lock_lost(4) <= rel_wayE_val(1) and dcpar_err_way_inval_q(4); +reload_wayE_d(2) <= ((not rel_par_wE_clr and rel_wayE_val(2))) or (rel_watch_set_q and rel_wayE_set and rel_thrd_id_q(0)); +reload_wayE_d(3) <= ((not rel_par_wE_clr and rel_wayE_val(3))) or (rel_watch_set_q and rel_wayE_set and rel_thrd_id_q(1)); +reload_wayE_d(4) <= ((not rel_par_wE_clr and rel_wayE_val(4))) or (rel_watch_set_q and rel_wayE_set and rel_thrd_id_q(2)); +reload_wayE_d(5) <= ((not rel_par_wE_clr and rel_wayE_val(5))) or (rel_watch_set_q and rel_wayE_set and rel_thrd_id_q(3)); +reload_wayE_upd_d <= rel_par_wE_clr or rel_wayE_set; +reload_wayE_clr <= rel_par_wE_clr; +rel_par_wF_clr <= rel_wayF_clr or dcpar_err_way_inval_q(5); +reload_wayF_d(0) <= (not rel_par_wF_clr and rel_wayF_val(0)) or rel_wayF_set; +reload_wayF_d(1) <= (not rel_par_wF_clr and rel_wayF_val(1)) or (rel_lock_set_q and rel_wayF_set); +dcpar_err_lock_lost(5) <= rel_wayF_val(1) and dcpar_err_way_inval_q(5); +reload_wayF_d(2) <= ((not rel_par_wF_clr and rel_wayF_val(2))) or (rel_watch_set_q and rel_wayF_set and rel_thrd_id_q(0)); +reload_wayF_d(3) <= ((not rel_par_wF_clr and rel_wayF_val(3))) or (rel_watch_set_q and rel_wayF_set and rel_thrd_id_q(1)); +reload_wayF_d(4) <= ((not rel_par_wF_clr and rel_wayF_val(4))) or (rel_watch_set_q and rel_wayF_set and rel_thrd_id_q(2)); +reload_wayF_d(5) <= ((not rel_par_wF_clr and rel_wayF_val(5))) or (rel_watch_set_q and rel_wayF_set and rel_thrd_id_q(3)); +reload_wayF_upd_d <= rel_par_wF_clr or rel_wayF_set; +reload_wayF_clr <= rel_par_wF_clr; +rel_par_wG_clr <= rel_wayG_clr or dcpar_err_way_inval_q(6); +reload_wayG_d(0) <= (not rel_par_wG_clr and rel_wayG_val(0)) or rel_wayG_set; +reload_wayG_d(1) <= (not rel_par_wG_clr and rel_wayG_val(1)) or (rel_lock_set_q and rel_wayG_set); +dcpar_err_lock_lost(6) <= rel_wayG_val(1) and dcpar_err_way_inval_q(6); +reload_wayG_d(2) <= ((not rel_par_wG_clr and rel_wayG_val(2))) or (rel_watch_set_q and rel_wayG_set and rel_thrd_id_q(0)); +reload_wayG_d(3) <= ((not rel_par_wG_clr and rel_wayG_val(3))) or (rel_watch_set_q and rel_wayG_set and rel_thrd_id_q(1)); +reload_wayG_d(4) <= ((not rel_par_wG_clr and rel_wayG_val(4))) or (rel_watch_set_q and rel_wayG_set and rel_thrd_id_q(2)); +reload_wayG_d(5) <= ((not rel_par_wG_clr and rel_wayG_val(5))) or (rel_watch_set_q and rel_wayG_set and rel_thrd_id_q(3)); +reload_wayG_upd_d <= rel_par_wG_clr or rel_wayG_set; +reload_wayG_clr <= rel_par_wG_clr; +rel_par_wH_clr <= rel_wayH_clr or dcpar_err_way_inval_q(7); +reload_wayH_d(0) <= (not rel_par_wH_clr and rel_wayH_val(0)) or rel_wayH_set; +reload_wayH_d(1) <= (not rel_par_wH_clr and rel_wayH_val(1)) or (rel_lock_set_q and rel_wayH_set); +dcpar_err_lock_lost(7) <= rel_wayH_val(1) and dcpar_err_way_inval_q(7); +reload_wayH_d(2) <= ((not rel_par_wH_clr and rel_wayH_val(2))) or (rel_watch_set_q and rel_wayH_set and rel_thrd_id_q(0)); +reload_wayH_d(3) <= ((not rel_par_wH_clr and rel_wayH_val(3))) or (rel_watch_set_q and rel_wayH_set and rel_thrd_id_q(1)); +reload_wayH_d(4) <= ((not rel_par_wH_clr and rel_wayH_val(4))) or (rel_watch_set_q and rel_wayH_set and rel_thrd_id_q(2)); +reload_wayH_d(5) <= ((not rel_par_wH_clr and rel_wayH_val(5))) or (rel_watch_set_q and rel_wayH_set and rel_thrd_id_q(3)); +reload_wayH_upd_d <= rel_par_wH_clr or rel_wayH_set; +reload_wayH_clr <= rel_par_wH_clr; +reload_way_clr_d <= reload_wayA_clr & reload_wayB_clr & reload_wayC_clr & reload_wayD_clr & + reload_wayE_clr & reload_wayF_clr & reload_wayG_clr & reload_wayH_clr; +rel4_l1dump_watch <= rel4_l1dump_val_q and rel_watch_set_q and not rel4_ecc_err; +lost_watch_l1dump <= gate(rel_thrd_id_q, rel4_l1dump_watch); +lost_watch_evict_ovl_d <= (gate(rel_thrd_id_q, (rel_watch_set_q and rel_val_stg4 and not + (rel_wayA_set or rel_wayB_set or rel_wayC_set or rel_wayD_set or + rel_wayE_set or rel_wayF_set or rel_wayG_set or rel_wayH_set)))) or + lost_watch_l1dump; +rel_lost_watch_wayA_evict <= gate(rel_wayA_val_stg_q(2 to 5), reload_way_clr_q(0)); +rel_lost_watch_wayB_evict <= gate(rel_wayB_val_stg_q(2 to 5), reload_way_clr_q(1)); +rel_lost_watch_wayC_evict <= gate(rel_wayC_val_stg_q(2 to 5), reload_way_clr_q(2)); +rel_lost_watch_wayD_evict <= gate(rel_wayD_val_stg_q(2 to 5), reload_way_clr_q(3)); +rel_lost_watch_wayE_evict <= gate(rel_wayE_val_stg_q(2 to 5), reload_way_clr_q(4)); +rel_lost_watch_wayF_evict <= gate(rel_wayF_val_stg_q(2 to 5), reload_way_clr_q(5)); +rel_lost_watch_wayG_evict <= gate(rel_wayG_val_stg_q(2 to 5), reload_way_clr_q(6)); +rel_lost_watch_wayH_evict <= gate(rel_wayH_val_stg_q(2 to 5), reload_way_clr_q(7)); +rel_lost_watch_binv_d <= rel_watch_lost; +rel_lost_watch_evict_np <= rel_lost_watch_wayA_evict or rel_lost_watch_wayB_evict or rel_lost_watch_wayC_evict or rel_lost_watch_wayD_evict or + rel_lost_watch_wayE_evict or rel_lost_watch_wayF_evict or rel_lost_watch_wayG_evict or rel_lost_watch_wayH_evict; +dcperr_lock_lost_d <= or_reduce(dcpar_err_lock_lost); +rel24_congr_cl_ex4_cmp_d <= congr_cl_rel13_ex3_cmp_q; +rel24_congr_cl_ex5_cmp_d <= congr_cl_rel13_ex4_cmp_q; +rel24_congr_cl_ex6_cmp_d <= congr_cl_rel13_ex5_cmp_q; +relu_congr_cl_ex5_cmp_d <= rel24_congr_cl_ex4_cmp_q; +relu_congr_cl_ex6_cmp_d <= rel24_congr_cl_ex5_cmp_q; +relu_congr_cl_ex7_cmp_d <= rel24_congr_cl_ex6_cmp_q; +relu_dir_data <= gate(reload_wayA_q(2 to 5), reload_way_clr_q(0)) or gate(reload_wayB_q(2 to 5), reload_way_clr_q(1)) or + gate(reload_wayC_q(2 to 5), reload_way_clr_q(2)) or gate(reload_wayD_q(2 to 5), reload_way_clr_q(3)) or + gate(reload_wayE_q(2 to 5), reload_way_clr_q(4)) or gate(reload_wayF_q(2 to 5), reload_way_clr_q(5)) or + gate(reload_wayG_q(2 to 5), reload_way_clr_q(6)) or gate(reload_wayH_q(2 to 5), reload_way_clr_q(7)); +rel_ex5_watchSet_coll <= rel_val_clr_q and relu_congr_cl_ex5_cmp_q and or_reduce(reload_way_clr_q and binv5_ex5_way_upd) and p0_wren_d; +rel_ex6_watchSet_coll <= rel_val_clr_q and relu_congr_cl_ex6_cmp_q and or_reduce(reload_way_clr_q and binv6_ex6_way_upd) and p0_wren_q; +rel_ex7_watchSet_coll <= rel_val_clr_q and relu_congr_cl_ex7_cmp_q and or_reduce(reload_way_clr_q and binv7_ex7_way_upd_q) and p0_wren_stg_q; +rel_coll_val <= rel_ex5_watchSet_coll or rel_ex6_watchSet_coll or rel_ex7_watchSet_coll; +rel_pri_byp_sel(0) <= rel_ex5_watchSet_coll; +rel_pri_byp_sel(1) <= rel_ex6_watchSet_coll and not rel_ex5_watchSet_coll; +rel_pri_byp_sel(2) <= rel_ex7_watchSet_coll and not (rel_ex6_watchSet_coll or rel_ex5_watchSet_coll); +rel_byp_dir_data <= gate(binv5_ex5_dir_data_q(2 to 5), rel_pri_byp_sel(0)) or + gate(binv6_ex6_dir_data_q(2 to 5), rel_pri_byp_sel(1)) or + gate(binv7_ex7_dir_data_q(2 to 5), rel_pri_byp_sel(2)); +rel_watchSet_coll_tid <= (rel_byp_dir_data and not relu_dir_data) or gate(rel_lost_watch_evict_np, (rel_val_clr_q and not rel_coll_val)); +rel_lost_watch_evict <= lost_watch_evict_ovl_q or rel_watchSet_coll_tid; +rel_lost_watch_upd_d <= rel_lost_watch_binv_q or rel_lost_watch_evict; +perf_binv_hit <= back_inval_stg4_q and or_reduce(ex4_way_hit_q); +ex5_watch_chk_cplt <= ex5_watch_chk_q and not ex5_stg_flush; +ex5_watch_chk_succ <= ex5_watch_chk_q and not (ex5_cr_watch_q or ex5_stg_flush); +ex5_watch_dup_set <= ex5_watch_set_q and ex5_cr_watch_q and not ex5_stg_flush; +lost_watch_inter_thrd_d <= gate((ex5_watchlost_set_q and not (ex5_thrd_id_q or ex5_watch_clr_all_q)), ex5_xuop_val); +lost_watch_evict_val_d <= lost_watch_evict_ovl_q or rel_watchSet_coll_tid; +lost_watch_binv <= binv5_inval_watch_val_q or rel_lost_watch_binv_q; +perf_lsu_evnts_d <= back_inval_stg4_q & perf_binv_hit & ex5_watch_chk_cplt & ex5_watch_chk_succ & ex5_watch_dup_set; +dcpar_err_push <= not ex9_ld_par_err_q; +dcpar_err_rec_cmpl <= (dcpar_err_cntr_q = "10") and dcpar_err_nxt_rec; +dcpar_err_nxt_rec <= ex9_ld_par_err_q and not rel_in_progress; +dcpar_err_push_queue <= dcpar_err_push or dcpar_err_nxt_rec; +dcpar_err_ind_sel <= dcpar_err_push & dcpar_err_rec_cmpl; +dcpar_err_ind_sel_d <= dcpar_err_ind_sel; +dcpar_err_push_queue_d <= dcpar_err_push_queue; +with dcpar_err_ind_sel select + ex7_ld_par_err_d <= ex6_ld_par_err when "10", + ex7_ld_par_err_q when "00", + '0' when others; +with dcpar_err_ind_sel select + ex8_ld_par_err_d <= ex7_ld_par_err_q when "10", + ex8_ld_par_err_q when "00", + '0' when others; +with dcpar_err_ind_sel select + ex9_ld_par_err_d <= ex8_ld_par_err_q when "10", + ex9_ld_par_err_q when "00", + '0' when others; +with dcpar_err_push_queue select + ex7_ld_valid_d <= ex6_ld_valid_q when '1', + ex7_ld_valid_q when others; +with dcpar_err_push_queue select + ex8_ld_valid_d <= ex7_ld_valid_q when '1', + ex8_ld_valid_q when others; +with dcpar_err_push_queue select + ex9_ld_valid_d <= ex8_ld_valid_q when '1', + ex9_ld_valid_q when others; +with dcpar_err_push_queue select + ex7_congr_cl_d <= ex6_congr_cl_q when '1', + ex7_congr_cl_q when others; +with dcpar_err_push_queue select + ex8_congr_cl_d <= ex7_congr_cl_q when '1', + ex8_congr_cl_q when others; +with dcpar_err_push_queue select + ex9_congr_cl_d <= ex8_congr_cl_q when '1', + ex9_congr_cl_q when others; +with dcpar_err_push_queue select + ex7_way_hit_d <= ex6_way_hit_q when '1', + ex7_way_hit_q when others; +with dcpar_err_push_queue select + ex8_way_hit_d <= ex7_way_hit_q when '1', + ex8_way_hit_q when others; +with dcpar_err_push_queue select + ex9_way_hit_d <= ex8_way_hit_q when '1', + ex9_way_hit_q when others; +dcpar_err_incr_val <= dcpar_err_nxt_rec and not (dcpar_err_cntr_q = "10"); +dcpar_err_cntr_sel <= dcpar_err_push & dcpar_err_incr_val; +dcpar_err_nxt_cntr <= std_ulogic_vector(unsigned(dcpar_err_cntr_q) + "01"); +with dcpar_err_cntr_sel select + dcpar_err_cntr_d <= dcpar_err_nxt_cntr when "01", + dcpar_err_cntr_q when "00", + "00" when others; +dcpar_err_stg1_d <= dcpar_err_nxt_rec; +dcpar_err_stg2_d <= dcpar_err_stg1_q; +dcpar_err_congr_cl <= ex9_congr_cl_q; +dcpar_err_way_d <= gate(ex9_way_hit_q, (ex9_ld_valid_q and dcpar_err_nxt_rec)); +dcpar_err_way_inval_d <= dcpar_err_way_q; +dcpar_err_flush <= ex9_ld_par_err_q; +dcpar_err_stg1_act_d <= ex9_ld_par_err_q; +dcpar_err_stg2_act_d <= dcpar_err_stg1_act_q; +dcpar_err_rec_inprog <= ex7_ld_par_err_q or ex8_ld_par_err_q or ex9_ld_par_err_q; +p0_wren_d <= back_inval_stg5_q or ex5_xuop_val or ex5_dir_err_val_q; +p0_wren_cpy_d <= back_inval_stg5_q or ex5_xuop_val or ex5_dir_err_val_q; +p0_wren_stg_d <= p0_wren_q; +p1_wren_d <= rel_port_wren_q; +p1_wren_cpy_d <= rel_port_wren_q; +p1_upd_val <= rel_port_upd_q; +reload_wayA(0) <= (reload_wayA_upd_q); +reload_wayA(1) <= reload_wayA_q(1); +reload_wayA(2 TO 5) <= reload_wayA_q(2 to 5); +reload_wayA_upd2_d <= reload_wayA_upd_q; +reload_wayA_data_d <= reload_wayA_q; +reload_wayA_upd3_d <= reload_wayA_upd2_q; +reload_wayA_data2_d <= reload_wayA_data_q; +binv_wayA_upd1 <= (binv_wayA_upd_q and ((not ex4_dir_err_val_q) or back_inval_stg4_q)) or ex4_err_det_way_q(0) or ex4_dir_multihit_val; +binv_wayA_upd2_d <= binv_wayA_upd1; +flush_wayA_data1 <= gate(flush_wayA_q, not (ex4_err_det_way_q(0) or ex4_dir_multihit_val)); +flush_wayA_data_d <= flush_wayA_data1; +binv_wayA_upd3_d <= binv_wayA_upd2_q; +flush_wayA_data2_d <= flush_wayA_data_q; +reload_wayB(0) <= (reload_wayB_upd_q); +reload_wayB(1) <= reload_wayB_q(1); +reload_wayB(2 TO 5) <= reload_wayB_q(2 to 5); +reload_wayB_upd2_d <= reload_wayB_upd_q; +reload_wayB_data_d <= reload_wayB_q; +reload_wayB_upd3_d <= reload_wayB_upd2_q; +reload_wayB_data2_d <= reload_wayB_data_q; +binv_wayB_upd1 <= (binv_wayB_upd_q and ((not ex4_dir_err_val_q) or back_inval_stg4_q)) or ex4_err_det_way_q(1) or ex4_dir_multihit_val; +binv_wayB_upd2_d <= binv_wayB_upd1; +flush_wayB_data1 <= gate(flush_wayB_q, not (ex4_err_det_way_q(1) or ex4_dir_multihit_val)); +flush_wayB_data_d <= flush_wayB_data1; +binv_wayB_upd3_d <= binv_wayB_upd2_q; +flush_wayB_data2_d <= flush_wayB_data_q; +reload_wayC(0) <= (reload_wayC_upd_q); +reload_wayC(1) <= reload_wayC_q(1); +reload_wayC(2 TO 5) <= reload_wayC_q(2 to 5); +reload_wayC_upd2_d <= reload_wayC_upd_q; +reload_wayC_data_d <= reload_wayC_q; +reload_wayC_upd3_d <= reload_wayC_upd2_q; +reload_wayC_data2_d <= reload_wayC_data_q; +binv_wayC_upd1 <= (binv_wayC_upd_q and ((not ex4_dir_err_val_q) or back_inval_stg4_q)) or ex4_err_det_way_q(2) or ex4_dir_multihit_val; +binv_wayC_upd2_d <= binv_wayC_upd1; +flush_wayC_data1 <= gate(flush_wayC_q, not (ex4_err_det_way_q(2) or ex4_dir_multihit_val)); +flush_wayC_data_d <= flush_wayC_data1; +binv_wayC_upd3_d <= binv_wayC_upd2_q; +flush_wayC_data2_d <= flush_wayC_data_q; +reload_wayD(0) <= (reload_wayD_upd_q); +reload_wayD(1) <= reload_wayD_q(1); +reload_wayD(2 TO 5) <= reload_wayD_q(2 to 5); +reload_wayD_upd2_d <= reload_wayD_upd_q; +reload_wayD_data_d <= reload_wayD_q; +reload_wayD_upd3_d <= reload_wayD_upd2_q; +reload_wayD_data2_d <= reload_wayD_data_q; +binv_wayD_upd1 <= (binv_wayD_upd_q and ((not ex4_dir_err_val_q) or back_inval_stg4_q)) or ex4_err_det_way_q(3) or ex4_dir_multihit_val; +binv_wayD_upd2_d <= binv_wayD_upd1; +flush_wayD_data1 <= gate(flush_wayD_q, not (ex4_err_det_way_q(3) or ex4_dir_multihit_val)); +flush_wayD_data_d <= flush_wayD_data1; +binv_wayD_upd3_d <= binv_wayD_upd2_q; +flush_wayD_data2_d <= flush_wayD_data_q; +reload_wayE(0) <= (reload_wayE_upd_q); +reload_wayE(1) <= reload_wayE_q(1); +reload_wayE(2 TO 5) <= reload_wayE_q(2 to 5); +reload_wayE_upd2_d <= reload_wayE_upd_q; +reload_wayE_data_d <= reload_wayE_q; +reload_wayE_upd3_d <= reload_wayE_upd2_q; +reload_wayE_data2_d <= reload_wayE_data_q; +binv_wayE_upd1 <= (binv_wayE_upd_q and ((not ex4_dir_err_val_q) or back_inval_stg4_q)) or ex4_err_det_way_q(4) or ex4_dir_multihit_val; +binv_wayE_upd2_d <= binv_wayE_upd1; +flush_wayE_data1 <= gate(flush_wayE_q, not (ex4_err_det_way_q(4) or ex4_dir_multihit_val)); +flush_wayE_data_d <= flush_wayE_data1; +binv_wayE_upd3_d <= binv_wayE_upd2_q; +flush_wayE_data2_d <= flush_wayE_data_q; +reload_wayF(0) <= (reload_wayF_upd_q); +reload_wayF(1) <= reload_wayF_q(1); +reload_wayF(2 TO 5) <= reload_wayF_q(2 to 5); +reload_wayF_upd2_d <= reload_wayF_upd_q; +reload_wayF_data_d <= reload_wayF_q; +reload_wayF_upd3_d <= reload_wayF_upd2_q; +reload_wayF_data2_d <= reload_wayF_data_q; +binv_wayF_upd1 <= (binv_wayF_upd_q and ((not ex4_dir_err_val_q) or back_inval_stg4_q)) or ex4_err_det_way_q(5) or ex4_dir_multihit_val; +binv_wayF_upd2_d <= binv_wayF_upd1; +flush_wayF_data1 <= gate(flush_wayF_q, not (ex4_err_det_way_q(5) or ex4_dir_multihit_val)); +flush_wayF_data_d <= flush_wayF_data1; +binv_wayF_upd3_d <= binv_wayF_upd2_q; +flush_wayF_data2_d <= flush_wayF_data_q; +reload_wayG(0) <= (reload_wayG_upd_q); +reload_wayG(1) <= reload_wayG_q(1); +reload_wayG(2 TO 5) <= reload_wayG_q(2 to 5); +reload_wayG_upd2_d <= reload_wayG_upd_q; +reload_wayG_data_d <= reload_wayG_q; +reload_wayG_upd3_d <= reload_wayG_upd2_q; +reload_wayG_data2_d <= reload_wayG_data_q; +binv_wayG_upd1 <= (binv_wayG_upd_q and ((not ex4_dir_err_val_q) or back_inval_stg4_q)) or ex4_err_det_way_q(6) or ex4_dir_multihit_val; +binv_wayG_upd2_d <= binv_wayG_upd1; +flush_wayG_data1 <= gate(flush_wayG_q, not (ex4_err_det_way_q(6) or ex4_dir_multihit_val)); +flush_wayG_data_d <= flush_wayG_data1; +binv_wayG_upd3_d <= binv_wayG_upd2_q; +flush_wayG_data2_d <= flush_wayG_data_q; +reload_wayH(0) <= (reload_wayH_upd_q); +reload_wayH(1) <= reload_wayH_q(1); +reload_wayH(2 TO 5) <= reload_wayH_q(2 to 5); +reload_wayH_upd2_d <= reload_wayH_upd_q; +reload_wayH_data_d <= reload_wayH_q; +reload_wayH_upd3_d <= reload_wayH_upd2_q; +reload_wayH_data2_d <= reload_wayH_data_q; +binv_wayH_upd1 <= (binv_wayH_upd_q and ((not ex4_dir_err_val_q) or back_inval_stg4_q)) or ex4_err_det_way_q(7) or ex4_dir_multihit_val; +binv_wayH_upd2_d <= binv_wayH_upd1; +flush_wayH_data1 <= gate(flush_wayH_q, not (ex4_err_det_way_q(7) or ex4_dir_multihit_val)); +flush_wayH_data_d <= flush_wayH_data1; +binv_wayH_upd3_d <= binv_wayH_upd2_q; +flush_wayH_data2_d <= flush_wayH_data_q; +congr_cl_all_act_d <= ex5_watch_clr_all_val_q or dci_compl_q or lock_flash_clear_q; +p0_congr_cl0_m <= (ex5_congr_cl_q = tconv(0,6)); +p1_congr_cl0_m <= (relu_s_congr_cl_q = tconv(0,6)); +p0_congr_cl0_act_d <= p0_congr_cl0_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl0_act_d <= p1_congr_cl0_m and rel_port_wren_q; +congr_cl0_act <= p0_congr_cl0_act_q or p1_congr_cl0_act_q or congr_cl_all_act_q; +p0_way_data_upd0_wayA <= p0_congr_cl0_act_q and binv_wayA_upd3_q; +p1_way_data_upd0_wayA <= p1_congr_cl0_act_q and reload_wayA_upd3_q; +rel_bixu0_wayA_upd(0) <= p1_way_data_upd0_wayA and p1_wren_q; +rel_bixu0_wayA_upd(1) <= p0_way_data_upd0_wayA and p0_wren_q; +p0_way_data_upd0_wayB <= p0_congr_cl0_act_q and binv_wayB_upd3_q; +p1_way_data_upd0_wayB <= p1_congr_cl0_act_q and reload_wayB_upd3_q; +rel_bixu0_wayB_upd(0) <= p1_way_data_upd0_wayB and p1_wren_q; +rel_bixu0_wayB_upd(1) <= p0_way_data_upd0_wayB and p0_wren_q; +p0_way_data_upd0_wayC <= p0_congr_cl0_act_q and binv_wayC_upd3_q; +p1_way_data_upd0_wayC <= p1_congr_cl0_act_q and reload_wayC_upd3_q; +rel_bixu0_wayC_upd(0) <= p1_way_data_upd0_wayC and p1_wren_q; +rel_bixu0_wayC_upd(1) <= p0_way_data_upd0_wayC and p0_wren_q; +p0_way_data_upd0_wayD <= p0_congr_cl0_act_q and binv_wayD_upd3_q; +p1_way_data_upd0_wayD <= p1_congr_cl0_act_q and reload_wayD_upd3_q; +rel_bixu0_wayD_upd(0) <= p1_way_data_upd0_wayD and p1_wren_q; +rel_bixu0_wayD_upd(1) <= p0_way_data_upd0_wayD and p0_wren_q; +p0_way_data_upd0_wayE <= p0_congr_cl0_act_q and binv_wayE_upd3_q; +p1_way_data_upd0_wayE <= p1_congr_cl0_act_q and reload_wayE_upd3_q; +rel_bixu0_wayE_upd(0) <= p1_way_data_upd0_wayE and p1_wren_q; +rel_bixu0_wayE_upd(1) <= p0_way_data_upd0_wayE and p0_wren_q; +p0_way_data_upd0_wayF <= p0_congr_cl0_act_q and binv_wayF_upd3_q; +p1_way_data_upd0_wayF <= p1_congr_cl0_act_q and reload_wayF_upd3_q; +rel_bixu0_wayF_upd(0) <= p1_way_data_upd0_wayF and p1_wren_q; +rel_bixu0_wayF_upd(1) <= p0_way_data_upd0_wayF and p0_wren_q; +p0_way_data_upd0_wayG <= p0_congr_cl0_act_q and binv_wayG_upd3_q; +p1_way_data_upd0_wayG <= p1_congr_cl0_act_q and reload_wayG_upd3_q; +rel_bixu0_wayG_upd(0) <= p1_way_data_upd0_wayG and p1_wren_q; +rel_bixu0_wayG_upd(1) <= p0_way_data_upd0_wayG and p0_wren_q; +p0_way_data_upd0_wayH <= p0_congr_cl0_act_q and binv_wayH_upd3_q; +p1_way_data_upd0_wayH <= p1_congr_cl0_act_q and reload_wayH_upd3_q; +rel_bixu0_wayH_upd(0) <= p1_way_data_upd0_wayH and p1_wren_q; +rel_bixu0_wayH_upd(1) <= p0_way_data_upd0_wayH and p0_wren_q; +p0_congr_cl1_m <= (ex5_congr_cl_q = tconv(1,6)); +p1_congr_cl1_m <= (relu_s_congr_cl_q = tconv(1,6)); +p0_congr_cl1_act_d <= p0_congr_cl1_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl1_act_d <= p1_congr_cl1_m and rel_port_wren_q; +congr_cl1_act <= p0_congr_cl1_act_q or p1_congr_cl1_act_q or congr_cl_all_act_q; +p0_way_data_upd1_wayA <= p0_congr_cl1_act_q and binv_wayA_upd3_q; +p1_way_data_upd1_wayA <= p1_congr_cl1_act_q and reload_wayA_upd3_q; +rel_bixu1_wayA_upd(0) <= p1_way_data_upd1_wayA and p1_wren_q; +rel_bixu1_wayA_upd(1) <= p0_way_data_upd1_wayA and p0_wren_q; +p0_way_data_upd1_wayB <= p0_congr_cl1_act_q and binv_wayB_upd3_q; +p1_way_data_upd1_wayB <= p1_congr_cl1_act_q and reload_wayB_upd3_q; +rel_bixu1_wayB_upd(0) <= p1_way_data_upd1_wayB and p1_wren_q; +rel_bixu1_wayB_upd(1) <= p0_way_data_upd1_wayB and p0_wren_q; +p0_way_data_upd1_wayC <= p0_congr_cl1_act_q and binv_wayC_upd3_q; +p1_way_data_upd1_wayC <= p1_congr_cl1_act_q and reload_wayC_upd3_q; +rel_bixu1_wayC_upd(0) <= p1_way_data_upd1_wayC and p1_wren_q; +rel_bixu1_wayC_upd(1) <= p0_way_data_upd1_wayC and p0_wren_q; +p0_way_data_upd1_wayD <= p0_congr_cl1_act_q and binv_wayD_upd3_q; +p1_way_data_upd1_wayD <= p1_congr_cl1_act_q and reload_wayD_upd3_q; +rel_bixu1_wayD_upd(0) <= p1_way_data_upd1_wayD and p1_wren_q; +rel_bixu1_wayD_upd(1) <= p0_way_data_upd1_wayD and p0_wren_q; +p0_way_data_upd1_wayE <= p0_congr_cl1_act_q and binv_wayE_upd3_q; +p1_way_data_upd1_wayE <= p1_congr_cl1_act_q and reload_wayE_upd3_q; +rel_bixu1_wayE_upd(0) <= p1_way_data_upd1_wayE and p1_wren_q; +rel_bixu1_wayE_upd(1) <= p0_way_data_upd1_wayE and p0_wren_q; +p0_way_data_upd1_wayF <= p0_congr_cl1_act_q and binv_wayF_upd3_q; +p1_way_data_upd1_wayF <= p1_congr_cl1_act_q and reload_wayF_upd3_q; +rel_bixu1_wayF_upd(0) <= p1_way_data_upd1_wayF and p1_wren_q; +rel_bixu1_wayF_upd(1) <= p0_way_data_upd1_wayF and p0_wren_q; +p0_way_data_upd1_wayG <= p0_congr_cl1_act_q and binv_wayG_upd3_q; +p1_way_data_upd1_wayG <= p1_congr_cl1_act_q and reload_wayG_upd3_q; +rel_bixu1_wayG_upd(0) <= p1_way_data_upd1_wayG and p1_wren_q; +rel_bixu1_wayG_upd(1) <= p0_way_data_upd1_wayG and p0_wren_q; +p0_way_data_upd1_wayH <= p0_congr_cl1_act_q and binv_wayH_upd3_q; +p1_way_data_upd1_wayH <= p1_congr_cl1_act_q and reload_wayH_upd3_q; +rel_bixu1_wayH_upd(0) <= p1_way_data_upd1_wayH and p1_wren_q; +rel_bixu1_wayH_upd(1) <= p0_way_data_upd1_wayH and p0_wren_q; +p0_congr_cl2_m <= (ex5_congr_cl_q = tconv(2,6)); +p1_congr_cl2_m <= (relu_s_congr_cl_q = tconv(2,6)); +p0_congr_cl2_act_d <= p0_congr_cl2_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl2_act_d <= p1_congr_cl2_m and rel_port_wren_q; +congr_cl2_act <= p0_congr_cl2_act_q or p1_congr_cl2_act_q or congr_cl_all_act_q; +p0_way_data_upd2_wayA <= p0_congr_cl2_act_q and binv_wayA_upd3_q; +p1_way_data_upd2_wayA <= p1_congr_cl2_act_q and reload_wayA_upd3_q; +rel_bixu2_wayA_upd(0) <= p1_way_data_upd2_wayA and p1_wren_q; +rel_bixu2_wayA_upd(1) <= p0_way_data_upd2_wayA and p0_wren_q; +p0_way_data_upd2_wayB <= p0_congr_cl2_act_q and binv_wayB_upd3_q; +p1_way_data_upd2_wayB <= p1_congr_cl2_act_q and reload_wayB_upd3_q; +rel_bixu2_wayB_upd(0) <= p1_way_data_upd2_wayB and p1_wren_q; +rel_bixu2_wayB_upd(1) <= p0_way_data_upd2_wayB and p0_wren_q; +p0_way_data_upd2_wayC <= p0_congr_cl2_act_q and binv_wayC_upd3_q; +p1_way_data_upd2_wayC <= p1_congr_cl2_act_q and reload_wayC_upd3_q; +rel_bixu2_wayC_upd(0) <= p1_way_data_upd2_wayC and p1_wren_q; +rel_bixu2_wayC_upd(1) <= p0_way_data_upd2_wayC and p0_wren_q; +p0_way_data_upd2_wayD <= p0_congr_cl2_act_q and binv_wayD_upd3_q; +p1_way_data_upd2_wayD <= p1_congr_cl2_act_q and reload_wayD_upd3_q; +rel_bixu2_wayD_upd(0) <= p1_way_data_upd2_wayD and p1_wren_q; +rel_bixu2_wayD_upd(1) <= p0_way_data_upd2_wayD and p0_wren_q; +p0_way_data_upd2_wayE <= p0_congr_cl2_act_q and binv_wayE_upd3_q; +p1_way_data_upd2_wayE <= p1_congr_cl2_act_q and reload_wayE_upd3_q; +rel_bixu2_wayE_upd(0) <= p1_way_data_upd2_wayE and p1_wren_q; +rel_bixu2_wayE_upd(1) <= p0_way_data_upd2_wayE and p0_wren_q; +p0_way_data_upd2_wayF <= p0_congr_cl2_act_q and binv_wayF_upd3_q; +p1_way_data_upd2_wayF <= p1_congr_cl2_act_q and reload_wayF_upd3_q; +rel_bixu2_wayF_upd(0) <= p1_way_data_upd2_wayF and p1_wren_q; +rel_bixu2_wayF_upd(1) <= p0_way_data_upd2_wayF and p0_wren_q; +p0_way_data_upd2_wayG <= p0_congr_cl2_act_q and binv_wayG_upd3_q; +p1_way_data_upd2_wayG <= p1_congr_cl2_act_q and reload_wayG_upd3_q; +rel_bixu2_wayG_upd(0) <= p1_way_data_upd2_wayG and p1_wren_q; +rel_bixu2_wayG_upd(1) <= p0_way_data_upd2_wayG and p0_wren_q; +p0_way_data_upd2_wayH <= p0_congr_cl2_act_q and binv_wayH_upd3_q; +p1_way_data_upd2_wayH <= p1_congr_cl2_act_q and reload_wayH_upd3_q; +rel_bixu2_wayH_upd(0) <= p1_way_data_upd2_wayH and p1_wren_q; +rel_bixu2_wayH_upd(1) <= p0_way_data_upd2_wayH and p0_wren_q; +p0_congr_cl3_m <= (ex5_congr_cl_q = tconv(3,6)); +p1_congr_cl3_m <= (relu_s_congr_cl_q = tconv(3,6)); +p0_congr_cl3_act_d <= p0_congr_cl3_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl3_act_d <= p1_congr_cl3_m and rel_port_wren_q; +congr_cl3_act <= p0_congr_cl3_act_q or p1_congr_cl3_act_q or congr_cl_all_act_q; +p0_way_data_upd3_wayA <= p0_congr_cl3_act_q and binv_wayA_upd3_q; +p1_way_data_upd3_wayA <= p1_congr_cl3_act_q and reload_wayA_upd3_q; +rel_bixu3_wayA_upd(0) <= p1_way_data_upd3_wayA and p1_wren_q; +rel_bixu3_wayA_upd(1) <= p0_way_data_upd3_wayA and p0_wren_q; +p0_way_data_upd3_wayB <= p0_congr_cl3_act_q and binv_wayB_upd3_q; +p1_way_data_upd3_wayB <= p1_congr_cl3_act_q and reload_wayB_upd3_q; +rel_bixu3_wayB_upd(0) <= p1_way_data_upd3_wayB and p1_wren_q; +rel_bixu3_wayB_upd(1) <= p0_way_data_upd3_wayB and p0_wren_q; +p0_way_data_upd3_wayC <= p0_congr_cl3_act_q and binv_wayC_upd3_q; +p1_way_data_upd3_wayC <= p1_congr_cl3_act_q and reload_wayC_upd3_q; +rel_bixu3_wayC_upd(0) <= p1_way_data_upd3_wayC and p1_wren_q; +rel_bixu3_wayC_upd(1) <= p0_way_data_upd3_wayC and p0_wren_q; +p0_way_data_upd3_wayD <= p0_congr_cl3_act_q and binv_wayD_upd3_q; +p1_way_data_upd3_wayD <= p1_congr_cl3_act_q and reload_wayD_upd3_q; +rel_bixu3_wayD_upd(0) <= p1_way_data_upd3_wayD and p1_wren_q; +rel_bixu3_wayD_upd(1) <= p0_way_data_upd3_wayD and p0_wren_q; +p0_way_data_upd3_wayE <= p0_congr_cl3_act_q and binv_wayE_upd3_q; +p1_way_data_upd3_wayE <= p1_congr_cl3_act_q and reload_wayE_upd3_q; +rel_bixu3_wayE_upd(0) <= p1_way_data_upd3_wayE and p1_wren_q; +rel_bixu3_wayE_upd(1) <= p0_way_data_upd3_wayE and p0_wren_q; +p0_way_data_upd3_wayF <= p0_congr_cl3_act_q and binv_wayF_upd3_q; +p1_way_data_upd3_wayF <= p1_congr_cl3_act_q and reload_wayF_upd3_q; +rel_bixu3_wayF_upd(0) <= p1_way_data_upd3_wayF and p1_wren_q; +rel_bixu3_wayF_upd(1) <= p0_way_data_upd3_wayF and p0_wren_q; +p0_way_data_upd3_wayG <= p0_congr_cl3_act_q and binv_wayG_upd3_q; +p1_way_data_upd3_wayG <= p1_congr_cl3_act_q and reload_wayG_upd3_q; +rel_bixu3_wayG_upd(0) <= p1_way_data_upd3_wayG and p1_wren_q; +rel_bixu3_wayG_upd(1) <= p0_way_data_upd3_wayG and p0_wren_q; +p0_way_data_upd3_wayH <= p0_congr_cl3_act_q and binv_wayH_upd3_q; +p1_way_data_upd3_wayH <= p1_congr_cl3_act_q and reload_wayH_upd3_q; +rel_bixu3_wayH_upd(0) <= p1_way_data_upd3_wayH and p1_wren_q; +rel_bixu3_wayH_upd(1) <= p0_way_data_upd3_wayH and p0_wren_q; +p0_congr_cl4_m <= (ex5_congr_cl_q = tconv(4,6)); +p1_congr_cl4_m <= (relu_s_congr_cl_q = tconv(4,6)); +p0_congr_cl4_act_d <= p0_congr_cl4_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl4_act_d <= p1_congr_cl4_m and rel_port_wren_q; +congr_cl4_act <= p0_congr_cl4_act_q or p1_congr_cl4_act_q or congr_cl_all_act_q; +p0_way_data_upd4_wayA <= p0_congr_cl4_act_q and binv_wayA_upd3_q; +p1_way_data_upd4_wayA <= p1_congr_cl4_act_q and reload_wayA_upd3_q; +rel_bixu4_wayA_upd(0) <= p1_way_data_upd4_wayA and p1_wren_q; +rel_bixu4_wayA_upd(1) <= p0_way_data_upd4_wayA and p0_wren_q; +p0_way_data_upd4_wayB <= p0_congr_cl4_act_q and binv_wayB_upd3_q; +p1_way_data_upd4_wayB <= p1_congr_cl4_act_q and reload_wayB_upd3_q; +rel_bixu4_wayB_upd(0) <= p1_way_data_upd4_wayB and p1_wren_q; +rel_bixu4_wayB_upd(1) <= p0_way_data_upd4_wayB and p0_wren_q; +p0_way_data_upd4_wayC <= p0_congr_cl4_act_q and binv_wayC_upd3_q; +p1_way_data_upd4_wayC <= p1_congr_cl4_act_q and reload_wayC_upd3_q; +rel_bixu4_wayC_upd(0) <= p1_way_data_upd4_wayC and p1_wren_q; +rel_bixu4_wayC_upd(1) <= p0_way_data_upd4_wayC and p0_wren_q; +p0_way_data_upd4_wayD <= p0_congr_cl4_act_q and binv_wayD_upd3_q; +p1_way_data_upd4_wayD <= p1_congr_cl4_act_q and reload_wayD_upd3_q; +rel_bixu4_wayD_upd(0) <= p1_way_data_upd4_wayD and p1_wren_q; +rel_bixu4_wayD_upd(1) <= p0_way_data_upd4_wayD and p0_wren_q; +p0_way_data_upd4_wayE <= p0_congr_cl4_act_q and binv_wayE_upd3_q; +p1_way_data_upd4_wayE <= p1_congr_cl4_act_q and reload_wayE_upd3_q; +rel_bixu4_wayE_upd(0) <= p1_way_data_upd4_wayE and p1_wren_q; +rel_bixu4_wayE_upd(1) <= p0_way_data_upd4_wayE and p0_wren_q; +p0_way_data_upd4_wayF <= p0_congr_cl4_act_q and binv_wayF_upd3_q; +p1_way_data_upd4_wayF <= p1_congr_cl4_act_q and reload_wayF_upd3_q; +rel_bixu4_wayF_upd(0) <= p1_way_data_upd4_wayF and p1_wren_q; +rel_bixu4_wayF_upd(1) <= p0_way_data_upd4_wayF and p0_wren_q; +p0_way_data_upd4_wayG <= p0_congr_cl4_act_q and binv_wayG_upd3_q; +p1_way_data_upd4_wayG <= p1_congr_cl4_act_q and reload_wayG_upd3_q; +rel_bixu4_wayG_upd(0) <= p1_way_data_upd4_wayG and p1_wren_q; +rel_bixu4_wayG_upd(1) <= p0_way_data_upd4_wayG and p0_wren_q; +p0_way_data_upd4_wayH <= p0_congr_cl4_act_q and binv_wayH_upd3_q; +p1_way_data_upd4_wayH <= p1_congr_cl4_act_q and reload_wayH_upd3_q; +rel_bixu4_wayH_upd(0) <= p1_way_data_upd4_wayH and p1_wren_q; +rel_bixu4_wayH_upd(1) <= p0_way_data_upd4_wayH and p0_wren_q; +p0_congr_cl5_m <= (ex5_congr_cl_q = tconv(5,6)); +p1_congr_cl5_m <= (relu_s_congr_cl_q = tconv(5,6)); +p0_congr_cl5_act_d <= p0_congr_cl5_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl5_act_d <= p1_congr_cl5_m and rel_port_wren_q; +congr_cl5_act <= p0_congr_cl5_act_q or p1_congr_cl5_act_q or congr_cl_all_act_q; +p0_way_data_upd5_wayA <= p0_congr_cl5_act_q and binv_wayA_upd3_q; +p1_way_data_upd5_wayA <= p1_congr_cl5_act_q and reload_wayA_upd3_q; +rel_bixu5_wayA_upd(0) <= p1_way_data_upd5_wayA and p1_wren_q; +rel_bixu5_wayA_upd(1) <= p0_way_data_upd5_wayA and p0_wren_q; +p0_way_data_upd5_wayB <= p0_congr_cl5_act_q and binv_wayB_upd3_q; +p1_way_data_upd5_wayB <= p1_congr_cl5_act_q and reload_wayB_upd3_q; +rel_bixu5_wayB_upd(0) <= p1_way_data_upd5_wayB and p1_wren_q; +rel_bixu5_wayB_upd(1) <= p0_way_data_upd5_wayB and p0_wren_q; +p0_way_data_upd5_wayC <= p0_congr_cl5_act_q and binv_wayC_upd3_q; +p1_way_data_upd5_wayC <= p1_congr_cl5_act_q and reload_wayC_upd3_q; +rel_bixu5_wayC_upd(0) <= p1_way_data_upd5_wayC and p1_wren_q; +rel_bixu5_wayC_upd(1) <= p0_way_data_upd5_wayC and p0_wren_q; +p0_way_data_upd5_wayD <= p0_congr_cl5_act_q and binv_wayD_upd3_q; +p1_way_data_upd5_wayD <= p1_congr_cl5_act_q and reload_wayD_upd3_q; +rel_bixu5_wayD_upd(0) <= p1_way_data_upd5_wayD and p1_wren_q; +rel_bixu5_wayD_upd(1) <= p0_way_data_upd5_wayD and p0_wren_q; +p0_way_data_upd5_wayE <= p0_congr_cl5_act_q and binv_wayE_upd3_q; +p1_way_data_upd5_wayE <= p1_congr_cl5_act_q and reload_wayE_upd3_q; +rel_bixu5_wayE_upd(0) <= p1_way_data_upd5_wayE and p1_wren_q; +rel_bixu5_wayE_upd(1) <= p0_way_data_upd5_wayE and p0_wren_q; +p0_way_data_upd5_wayF <= p0_congr_cl5_act_q and binv_wayF_upd3_q; +p1_way_data_upd5_wayF <= p1_congr_cl5_act_q and reload_wayF_upd3_q; +rel_bixu5_wayF_upd(0) <= p1_way_data_upd5_wayF and p1_wren_q; +rel_bixu5_wayF_upd(1) <= p0_way_data_upd5_wayF and p0_wren_q; +p0_way_data_upd5_wayG <= p0_congr_cl5_act_q and binv_wayG_upd3_q; +p1_way_data_upd5_wayG <= p1_congr_cl5_act_q and reload_wayG_upd3_q; +rel_bixu5_wayG_upd(0) <= p1_way_data_upd5_wayG and p1_wren_q; +rel_bixu5_wayG_upd(1) <= p0_way_data_upd5_wayG and p0_wren_q; +p0_way_data_upd5_wayH <= p0_congr_cl5_act_q and binv_wayH_upd3_q; +p1_way_data_upd5_wayH <= p1_congr_cl5_act_q and reload_wayH_upd3_q; +rel_bixu5_wayH_upd(0) <= p1_way_data_upd5_wayH and p1_wren_q; +rel_bixu5_wayH_upd(1) <= p0_way_data_upd5_wayH and p0_wren_q; +p0_congr_cl6_m <= (ex5_congr_cl_q = tconv(6,6)); +p1_congr_cl6_m <= (relu_s_congr_cl_q = tconv(6,6)); +p0_congr_cl6_act_d <= p0_congr_cl6_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl6_act_d <= p1_congr_cl6_m and rel_port_wren_q; +congr_cl6_act <= p0_congr_cl6_act_q or p1_congr_cl6_act_q or congr_cl_all_act_q; +p0_way_data_upd6_wayA <= p0_congr_cl6_act_q and binv_wayA_upd3_q; +p1_way_data_upd6_wayA <= p1_congr_cl6_act_q and reload_wayA_upd3_q; +rel_bixu6_wayA_upd(0) <= p1_way_data_upd6_wayA and p1_wren_q; +rel_bixu6_wayA_upd(1) <= p0_way_data_upd6_wayA and p0_wren_q; +p0_way_data_upd6_wayB <= p0_congr_cl6_act_q and binv_wayB_upd3_q; +p1_way_data_upd6_wayB <= p1_congr_cl6_act_q and reload_wayB_upd3_q; +rel_bixu6_wayB_upd(0) <= p1_way_data_upd6_wayB and p1_wren_q; +rel_bixu6_wayB_upd(1) <= p0_way_data_upd6_wayB and p0_wren_q; +p0_way_data_upd6_wayC <= p0_congr_cl6_act_q and binv_wayC_upd3_q; +p1_way_data_upd6_wayC <= p1_congr_cl6_act_q and reload_wayC_upd3_q; +rel_bixu6_wayC_upd(0) <= p1_way_data_upd6_wayC and p1_wren_q; +rel_bixu6_wayC_upd(1) <= p0_way_data_upd6_wayC and p0_wren_q; +p0_way_data_upd6_wayD <= p0_congr_cl6_act_q and binv_wayD_upd3_q; +p1_way_data_upd6_wayD <= p1_congr_cl6_act_q and reload_wayD_upd3_q; +rel_bixu6_wayD_upd(0) <= p1_way_data_upd6_wayD and p1_wren_q; +rel_bixu6_wayD_upd(1) <= p0_way_data_upd6_wayD and p0_wren_q; +p0_way_data_upd6_wayE <= p0_congr_cl6_act_q and binv_wayE_upd3_q; +p1_way_data_upd6_wayE <= p1_congr_cl6_act_q and reload_wayE_upd3_q; +rel_bixu6_wayE_upd(0) <= p1_way_data_upd6_wayE and p1_wren_q; +rel_bixu6_wayE_upd(1) <= p0_way_data_upd6_wayE and p0_wren_q; +p0_way_data_upd6_wayF <= p0_congr_cl6_act_q and binv_wayF_upd3_q; +p1_way_data_upd6_wayF <= p1_congr_cl6_act_q and reload_wayF_upd3_q; +rel_bixu6_wayF_upd(0) <= p1_way_data_upd6_wayF and p1_wren_q; +rel_bixu6_wayF_upd(1) <= p0_way_data_upd6_wayF and p0_wren_q; +p0_way_data_upd6_wayG <= p0_congr_cl6_act_q and binv_wayG_upd3_q; +p1_way_data_upd6_wayG <= p1_congr_cl6_act_q and reload_wayG_upd3_q; +rel_bixu6_wayG_upd(0) <= p1_way_data_upd6_wayG and p1_wren_q; +rel_bixu6_wayG_upd(1) <= p0_way_data_upd6_wayG and p0_wren_q; +p0_way_data_upd6_wayH <= p0_congr_cl6_act_q and binv_wayH_upd3_q; +p1_way_data_upd6_wayH <= p1_congr_cl6_act_q and reload_wayH_upd3_q; +rel_bixu6_wayH_upd(0) <= p1_way_data_upd6_wayH and p1_wren_q; +rel_bixu6_wayH_upd(1) <= p0_way_data_upd6_wayH and p0_wren_q; +p0_congr_cl7_m <= (ex5_congr_cl_q = tconv(7,6)); +p1_congr_cl7_m <= (relu_s_congr_cl_q = tconv(7,6)); +p0_congr_cl7_act_d <= p0_congr_cl7_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl7_act_d <= p1_congr_cl7_m and rel_port_wren_q; +congr_cl7_act <= p0_congr_cl7_act_q or p1_congr_cl7_act_q or congr_cl_all_act_q; +p0_way_data_upd7_wayA <= p0_congr_cl7_act_q and binv_wayA_upd3_q; +p1_way_data_upd7_wayA <= p1_congr_cl7_act_q and reload_wayA_upd3_q; +rel_bixu7_wayA_upd(0) <= p1_way_data_upd7_wayA and p1_wren_q; +rel_bixu7_wayA_upd(1) <= p0_way_data_upd7_wayA and p0_wren_q; +p0_way_data_upd7_wayB <= p0_congr_cl7_act_q and binv_wayB_upd3_q; +p1_way_data_upd7_wayB <= p1_congr_cl7_act_q and reload_wayB_upd3_q; +rel_bixu7_wayB_upd(0) <= p1_way_data_upd7_wayB and p1_wren_q; +rel_bixu7_wayB_upd(1) <= p0_way_data_upd7_wayB and p0_wren_q; +p0_way_data_upd7_wayC <= p0_congr_cl7_act_q and binv_wayC_upd3_q; +p1_way_data_upd7_wayC <= p1_congr_cl7_act_q and reload_wayC_upd3_q; +rel_bixu7_wayC_upd(0) <= p1_way_data_upd7_wayC and p1_wren_q; +rel_bixu7_wayC_upd(1) <= p0_way_data_upd7_wayC and p0_wren_q; +p0_way_data_upd7_wayD <= p0_congr_cl7_act_q and binv_wayD_upd3_q; +p1_way_data_upd7_wayD <= p1_congr_cl7_act_q and reload_wayD_upd3_q; +rel_bixu7_wayD_upd(0) <= p1_way_data_upd7_wayD and p1_wren_q; +rel_bixu7_wayD_upd(1) <= p0_way_data_upd7_wayD and p0_wren_q; +p0_way_data_upd7_wayE <= p0_congr_cl7_act_q and binv_wayE_upd3_q; +p1_way_data_upd7_wayE <= p1_congr_cl7_act_q and reload_wayE_upd3_q; +rel_bixu7_wayE_upd(0) <= p1_way_data_upd7_wayE and p1_wren_q; +rel_bixu7_wayE_upd(1) <= p0_way_data_upd7_wayE and p0_wren_q; +p0_way_data_upd7_wayF <= p0_congr_cl7_act_q and binv_wayF_upd3_q; +p1_way_data_upd7_wayF <= p1_congr_cl7_act_q and reload_wayF_upd3_q; +rel_bixu7_wayF_upd(0) <= p1_way_data_upd7_wayF and p1_wren_q; +rel_bixu7_wayF_upd(1) <= p0_way_data_upd7_wayF and p0_wren_q; +p0_way_data_upd7_wayG <= p0_congr_cl7_act_q and binv_wayG_upd3_q; +p1_way_data_upd7_wayG <= p1_congr_cl7_act_q and reload_wayG_upd3_q; +rel_bixu7_wayG_upd(0) <= p1_way_data_upd7_wayG and p1_wren_q; +rel_bixu7_wayG_upd(1) <= p0_way_data_upd7_wayG and p0_wren_q; +p0_way_data_upd7_wayH <= p0_congr_cl7_act_q and binv_wayH_upd3_q; +p1_way_data_upd7_wayH <= p1_congr_cl7_act_q and reload_wayH_upd3_q; +rel_bixu7_wayH_upd(0) <= p1_way_data_upd7_wayH and p1_wren_q; +rel_bixu7_wayH_upd(1) <= p0_way_data_upd7_wayH and p0_wren_q; +p0_congr_cl8_m <= (ex5_congr_cl_q = tconv(8,6)); +p1_congr_cl8_m <= (relu_s_congr_cl_q = tconv(8,6)); +p0_congr_cl8_act_d <= p0_congr_cl8_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl8_act_d <= p1_congr_cl8_m and rel_port_wren_q; +congr_cl8_act <= p0_congr_cl8_act_q or p1_congr_cl8_act_q or congr_cl_all_act_q; +p0_way_data_upd8_wayA <= p0_congr_cl8_act_q and binv_wayA_upd3_q; +p1_way_data_upd8_wayA <= p1_congr_cl8_act_q and reload_wayA_upd3_q; +rel_bixu8_wayA_upd(0) <= p1_way_data_upd8_wayA and p1_wren_q; +rel_bixu8_wayA_upd(1) <= p0_way_data_upd8_wayA and p0_wren_q; +p0_way_data_upd8_wayB <= p0_congr_cl8_act_q and binv_wayB_upd3_q; +p1_way_data_upd8_wayB <= p1_congr_cl8_act_q and reload_wayB_upd3_q; +rel_bixu8_wayB_upd(0) <= p1_way_data_upd8_wayB and p1_wren_q; +rel_bixu8_wayB_upd(1) <= p0_way_data_upd8_wayB and p0_wren_q; +p0_way_data_upd8_wayC <= p0_congr_cl8_act_q and binv_wayC_upd3_q; +p1_way_data_upd8_wayC <= p1_congr_cl8_act_q and reload_wayC_upd3_q; +rel_bixu8_wayC_upd(0) <= p1_way_data_upd8_wayC and p1_wren_q; +rel_bixu8_wayC_upd(1) <= p0_way_data_upd8_wayC and p0_wren_q; +p0_way_data_upd8_wayD <= p0_congr_cl8_act_q and binv_wayD_upd3_q; +p1_way_data_upd8_wayD <= p1_congr_cl8_act_q and reload_wayD_upd3_q; +rel_bixu8_wayD_upd(0) <= p1_way_data_upd8_wayD and p1_wren_q; +rel_bixu8_wayD_upd(1) <= p0_way_data_upd8_wayD and p0_wren_q; +p0_way_data_upd8_wayE <= p0_congr_cl8_act_q and binv_wayE_upd3_q; +p1_way_data_upd8_wayE <= p1_congr_cl8_act_q and reload_wayE_upd3_q; +rel_bixu8_wayE_upd(0) <= p1_way_data_upd8_wayE and p1_wren_q; +rel_bixu8_wayE_upd(1) <= p0_way_data_upd8_wayE and p0_wren_q; +p0_way_data_upd8_wayF <= p0_congr_cl8_act_q and binv_wayF_upd3_q; +p1_way_data_upd8_wayF <= p1_congr_cl8_act_q and reload_wayF_upd3_q; +rel_bixu8_wayF_upd(0) <= p1_way_data_upd8_wayF and p1_wren_q; +rel_bixu8_wayF_upd(1) <= p0_way_data_upd8_wayF and p0_wren_q; +p0_way_data_upd8_wayG <= p0_congr_cl8_act_q and binv_wayG_upd3_q; +p1_way_data_upd8_wayG <= p1_congr_cl8_act_q and reload_wayG_upd3_q; +rel_bixu8_wayG_upd(0) <= p1_way_data_upd8_wayG and p1_wren_q; +rel_bixu8_wayG_upd(1) <= p0_way_data_upd8_wayG and p0_wren_q; +p0_way_data_upd8_wayH <= p0_congr_cl8_act_q and binv_wayH_upd3_q; +p1_way_data_upd8_wayH <= p1_congr_cl8_act_q and reload_wayH_upd3_q; +rel_bixu8_wayH_upd(0) <= p1_way_data_upd8_wayH and p1_wren_q; +rel_bixu8_wayH_upd(1) <= p0_way_data_upd8_wayH and p0_wren_q; +p0_congr_cl9_m <= (ex5_congr_cl_q = tconv(9,6)); +p1_congr_cl9_m <= (relu_s_congr_cl_q = tconv(9,6)); +p0_congr_cl9_act_d <= p0_congr_cl9_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl9_act_d <= p1_congr_cl9_m and rel_port_wren_q; +congr_cl9_act <= p0_congr_cl9_act_q or p1_congr_cl9_act_q or congr_cl_all_act_q; +p0_way_data_upd9_wayA <= p0_congr_cl9_act_q and binv_wayA_upd3_q; +p1_way_data_upd9_wayA <= p1_congr_cl9_act_q and reload_wayA_upd3_q; +rel_bixu9_wayA_upd(0) <= p1_way_data_upd9_wayA and p1_wren_q; +rel_bixu9_wayA_upd(1) <= p0_way_data_upd9_wayA and p0_wren_q; +p0_way_data_upd9_wayB <= p0_congr_cl9_act_q and binv_wayB_upd3_q; +p1_way_data_upd9_wayB <= p1_congr_cl9_act_q and reload_wayB_upd3_q; +rel_bixu9_wayB_upd(0) <= p1_way_data_upd9_wayB and p1_wren_q; +rel_bixu9_wayB_upd(1) <= p0_way_data_upd9_wayB and p0_wren_q; +p0_way_data_upd9_wayC <= p0_congr_cl9_act_q and binv_wayC_upd3_q; +p1_way_data_upd9_wayC <= p1_congr_cl9_act_q and reload_wayC_upd3_q; +rel_bixu9_wayC_upd(0) <= p1_way_data_upd9_wayC and p1_wren_q; +rel_bixu9_wayC_upd(1) <= p0_way_data_upd9_wayC and p0_wren_q; +p0_way_data_upd9_wayD <= p0_congr_cl9_act_q and binv_wayD_upd3_q; +p1_way_data_upd9_wayD <= p1_congr_cl9_act_q and reload_wayD_upd3_q; +rel_bixu9_wayD_upd(0) <= p1_way_data_upd9_wayD and p1_wren_q; +rel_bixu9_wayD_upd(1) <= p0_way_data_upd9_wayD and p0_wren_q; +p0_way_data_upd9_wayE <= p0_congr_cl9_act_q and binv_wayE_upd3_q; +p1_way_data_upd9_wayE <= p1_congr_cl9_act_q and reload_wayE_upd3_q; +rel_bixu9_wayE_upd(0) <= p1_way_data_upd9_wayE and p1_wren_q; +rel_bixu9_wayE_upd(1) <= p0_way_data_upd9_wayE and p0_wren_q; +p0_way_data_upd9_wayF <= p0_congr_cl9_act_q and binv_wayF_upd3_q; +p1_way_data_upd9_wayF <= p1_congr_cl9_act_q and reload_wayF_upd3_q; +rel_bixu9_wayF_upd(0) <= p1_way_data_upd9_wayF and p1_wren_q; +rel_bixu9_wayF_upd(1) <= p0_way_data_upd9_wayF and p0_wren_q; +p0_way_data_upd9_wayG <= p0_congr_cl9_act_q and binv_wayG_upd3_q; +p1_way_data_upd9_wayG <= p1_congr_cl9_act_q and reload_wayG_upd3_q; +rel_bixu9_wayG_upd(0) <= p1_way_data_upd9_wayG and p1_wren_q; +rel_bixu9_wayG_upd(1) <= p0_way_data_upd9_wayG and p0_wren_q; +p0_way_data_upd9_wayH <= p0_congr_cl9_act_q and binv_wayH_upd3_q; +p1_way_data_upd9_wayH <= p1_congr_cl9_act_q and reload_wayH_upd3_q; +rel_bixu9_wayH_upd(0) <= p1_way_data_upd9_wayH and p1_wren_q; +rel_bixu9_wayH_upd(1) <= p0_way_data_upd9_wayH and p0_wren_q; +p0_congr_cl10_m <= (ex5_congr_cl_q = tconv(10,6)); +p1_congr_cl10_m <= (relu_s_congr_cl_q = tconv(10,6)); +p0_congr_cl10_act_d <= p0_congr_cl10_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl10_act_d <= p1_congr_cl10_m and rel_port_wren_q; +congr_cl10_act <= p0_congr_cl10_act_q or p1_congr_cl10_act_q or congr_cl_all_act_q; +p0_way_data_upd10_wayA <= p0_congr_cl10_act_q and binv_wayA_upd3_q; +p1_way_data_upd10_wayA <= p1_congr_cl10_act_q and reload_wayA_upd3_q; +rel_bixu10_wayA_upd(0) <= p1_way_data_upd10_wayA and p1_wren_q; +rel_bixu10_wayA_upd(1) <= p0_way_data_upd10_wayA and p0_wren_q; +p0_way_data_upd10_wayB <= p0_congr_cl10_act_q and binv_wayB_upd3_q; +p1_way_data_upd10_wayB <= p1_congr_cl10_act_q and reload_wayB_upd3_q; +rel_bixu10_wayB_upd(0) <= p1_way_data_upd10_wayB and p1_wren_q; +rel_bixu10_wayB_upd(1) <= p0_way_data_upd10_wayB and p0_wren_q; +p0_way_data_upd10_wayC <= p0_congr_cl10_act_q and binv_wayC_upd3_q; +p1_way_data_upd10_wayC <= p1_congr_cl10_act_q and reload_wayC_upd3_q; +rel_bixu10_wayC_upd(0) <= p1_way_data_upd10_wayC and p1_wren_q; +rel_bixu10_wayC_upd(1) <= p0_way_data_upd10_wayC and p0_wren_q; +p0_way_data_upd10_wayD <= p0_congr_cl10_act_q and binv_wayD_upd3_q; +p1_way_data_upd10_wayD <= p1_congr_cl10_act_q and reload_wayD_upd3_q; +rel_bixu10_wayD_upd(0) <= p1_way_data_upd10_wayD and p1_wren_q; +rel_bixu10_wayD_upd(1) <= p0_way_data_upd10_wayD and p0_wren_q; +p0_way_data_upd10_wayE <= p0_congr_cl10_act_q and binv_wayE_upd3_q; +p1_way_data_upd10_wayE <= p1_congr_cl10_act_q and reload_wayE_upd3_q; +rel_bixu10_wayE_upd(0) <= p1_way_data_upd10_wayE and p1_wren_q; +rel_bixu10_wayE_upd(1) <= p0_way_data_upd10_wayE and p0_wren_q; +p0_way_data_upd10_wayF <= p0_congr_cl10_act_q and binv_wayF_upd3_q; +p1_way_data_upd10_wayF <= p1_congr_cl10_act_q and reload_wayF_upd3_q; +rel_bixu10_wayF_upd(0) <= p1_way_data_upd10_wayF and p1_wren_q; +rel_bixu10_wayF_upd(1) <= p0_way_data_upd10_wayF and p0_wren_q; +p0_way_data_upd10_wayG <= p0_congr_cl10_act_q and binv_wayG_upd3_q; +p1_way_data_upd10_wayG <= p1_congr_cl10_act_q and reload_wayG_upd3_q; +rel_bixu10_wayG_upd(0) <= p1_way_data_upd10_wayG and p1_wren_q; +rel_bixu10_wayG_upd(1) <= p0_way_data_upd10_wayG and p0_wren_q; +p0_way_data_upd10_wayH <= p0_congr_cl10_act_q and binv_wayH_upd3_q; +p1_way_data_upd10_wayH <= p1_congr_cl10_act_q and reload_wayH_upd3_q; +rel_bixu10_wayH_upd(0) <= p1_way_data_upd10_wayH and p1_wren_q; +rel_bixu10_wayH_upd(1) <= p0_way_data_upd10_wayH and p0_wren_q; +p0_congr_cl11_m <= (ex5_congr_cl_q = tconv(11,6)); +p1_congr_cl11_m <= (relu_s_congr_cl_q = tconv(11,6)); +p0_congr_cl11_act_d <= p0_congr_cl11_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl11_act_d <= p1_congr_cl11_m and rel_port_wren_q; +congr_cl11_act <= p0_congr_cl11_act_q or p1_congr_cl11_act_q or congr_cl_all_act_q; +p0_way_data_upd11_wayA <= p0_congr_cl11_act_q and binv_wayA_upd3_q; +p1_way_data_upd11_wayA <= p1_congr_cl11_act_q and reload_wayA_upd3_q; +rel_bixu11_wayA_upd(0) <= p1_way_data_upd11_wayA and p1_wren_q; +rel_bixu11_wayA_upd(1) <= p0_way_data_upd11_wayA and p0_wren_q; +p0_way_data_upd11_wayB <= p0_congr_cl11_act_q and binv_wayB_upd3_q; +p1_way_data_upd11_wayB <= p1_congr_cl11_act_q and reload_wayB_upd3_q; +rel_bixu11_wayB_upd(0) <= p1_way_data_upd11_wayB and p1_wren_q; +rel_bixu11_wayB_upd(1) <= p0_way_data_upd11_wayB and p0_wren_q; +p0_way_data_upd11_wayC <= p0_congr_cl11_act_q and binv_wayC_upd3_q; +p1_way_data_upd11_wayC <= p1_congr_cl11_act_q and reload_wayC_upd3_q; +rel_bixu11_wayC_upd(0) <= p1_way_data_upd11_wayC and p1_wren_q; +rel_bixu11_wayC_upd(1) <= p0_way_data_upd11_wayC and p0_wren_q; +p0_way_data_upd11_wayD <= p0_congr_cl11_act_q and binv_wayD_upd3_q; +p1_way_data_upd11_wayD <= p1_congr_cl11_act_q and reload_wayD_upd3_q; +rel_bixu11_wayD_upd(0) <= p1_way_data_upd11_wayD and p1_wren_q; +rel_bixu11_wayD_upd(1) <= p0_way_data_upd11_wayD and p0_wren_q; +p0_way_data_upd11_wayE <= p0_congr_cl11_act_q and binv_wayE_upd3_q; +p1_way_data_upd11_wayE <= p1_congr_cl11_act_q and reload_wayE_upd3_q; +rel_bixu11_wayE_upd(0) <= p1_way_data_upd11_wayE and p1_wren_q; +rel_bixu11_wayE_upd(1) <= p0_way_data_upd11_wayE and p0_wren_q; +p0_way_data_upd11_wayF <= p0_congr_cl11_act_q and binv_wayF_upd3_q; +p1_way_data_upd11_wayF <= p1_congr_cl11_act_q and reload_wayF_upd3_q; +rel_bixu11_wayF_upd(0) <= p1_way_data_upd11_wayF and p1_wren_q; +rel_bixu11_wayF_upd(1) <= p0_way_data_upd11_wayF and p0_wren_q; +p0_way_data_upd11_wayG <= p0_congr_cl11_act_q and binv_wayG_upd3_q; +p1_way_data_upd11_wayG <= p1_congr_cl11_act_q and reload_wayG_upd3_q; +rel_bixu11_wayG_upd(0) <= p1_way_data_upd11_wayG and p1_wren_q; +rel_bixu11_wayG_upd(1) <= p0_way_data_upd11_wayG and p0_wren_q; +p0_way_data_upd11_wayH <= p0_congr_cl11_act_q and binv_wayH_upd3_q; +p1_way_data_upd11_wayH <= p1_congr_cl11_act_q and reload_wayH_upd3_q; +rel_bixu11_wayH_upd(0) <= p1_way_data_upd11_wayH and p1_wren_q; +rel_bixu11_wayH_upd(1) <= p0_way_data_upd11_wayH and p0_wren_q; +p0_congr_cl12_m <= (ex5_congr_cl_q = tconv(12,6)); +p1_congr_cl12_m <= (relu_s_congr_cl_q = tconv(12,6)); +p0_congr_cl12_act_d <= p0_congr_cl12_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl12_act_d <= p1_congr_cl12_m and rel_port_wren_q; +congr_cl12_act <= p0_congr_cl12_act_q or p1_congr_cl12_act_q or congr_cl_all_act_q; +p0_way_data_upd12_wayA <= p0_congr_cl12_act_q and binv_wayA_upd3_q; +p1_way_data_upd12_wayA <= p1_congr_cl12_act_q and reload_wayA_upd3_q; +rel_bixu12_wayA_upd(0) <= p1_way_data_upd12_wayA and p1_wren_q; +rel_bixu12_wayA_upd(1) <= p0_way_data_upd12_wayA and p0_wren_q; +p0_way_data_upd12_wayB <= p0_congr_cl12_act_q and binv_wayB_upd3_q; +p1_way_data_upd12_wayB <= p1_congr_cl12_act_q and reload_wayB_upd3_q; +rel_bixu12_wayB_upd(0) <= p1_way_data_upd12_wayB and p1_wren_q; +rel_bixu12_wayB_upd(1) <= p0_way_data_upd12_wayB and p0_wren_q; +p0_way_data_upd12_wayC <= p0_congr_cl12_act_q and binv_wayC_upd3_q; +p1_way_data_upd12_wayC <= p1_congr_cl12_act_q and reload_wayC_upd3_q; +rel_bixu12_wayC_upd(0) <= p1_way_data_upd12_wayC and p1_wren_q; +rel_bixu12_wayC_upd(1) <= p0_way_data_upd12_wayC and p0_wren_q; +p0_way_data_upd12_wayD <= p0_congr_cl12_act_q and binv_wayD_upd3_q; +p1_way_data_upd12_wayD <= p1_congr_cl12_act_q and reload_wayD_upd3_q; +rel_bixu12_wayD_upd(0) <= p1_way_data_upd12_wayD and p1_wren_q; +rel_bixu12_wayD_upd(1) <= p0_way_data_upd12_wayD and p0_wren_q; +p0_way_data_upd12_wayE <= p0_congr_cl12_act_q and binv_wayE_upd3_q; +p1_way_data_upd12_wayE <= p1_congr_cl12_act_q and reload_wayE_upd3_q; +rel_bixu12_wayE_upd(0) <= p1_way_data_upd12_wayE and p1_wren_q; +rel_bixu12_wayE_upd(1) <= p0_way_data_upd12_wayE and p0_wren_q; +p0_way_data_upd12_wayF <= p0_congr_cl12_act_q and binv_wayF_upd3_q; +p1_way_data_upd12_wayF <= p1_congr_cl12_act_q and reload_wayF_upd3_q; +rel_bixu12_wayF_upd(0) <= p1_way_data_upd12_wayF and p1_wren_q; +rel_bixu12_wayF_upd(1) <= p0_way_data_upd12_wayF and p0_wren_q; +p0_way_data_upd12_wayG <= p0_congr_cl12_act_q and binv_wayG_upd3_q; +p1_way_data_upd12_wayG <= p1_congr_cl12_act_q and reload_wayG_upd3_q; +rel_bixu12_wayG_upd(0) <= p1_way_data_upd12_wayG and p1_wren_q; +rel_bixu12_wayG_upd(1) <= p0_way_data_upd12_wayG and p0_wren_q; +p0_way_data_upd12_wayH <= p0_congr_cl12_act_q and binv_wayH_upd3_q; +p1_way_data_upd12_wayH <= p1_congr_cl12_act_q and reload_wayH_upd3_q; +rel_bixu12_wayH_upd(0) <= p1_way_data_upd12_wayH and p1_wren_q; +rel_bixu12_wayH_upd(1) <= p0_way_data_upd12_wayH and p0_wren_q; +p0_congr_cl13_m <= (ex5_congr_cl_q = tconv(13,6)); +p1_congr_cl13_m <= (relu_s_congr_cl_q = tconv(13,6)); +p0_congr_cl13_act_d <= p0_congr_cl13_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl13_act_d <= p1_congr_cl13_m and rel_port_wren_q; +congr_cl13_act <= p0_congr_cl13_act_q or p1_congr_cl13_act_q or congr_cl_all_act_q; +p0_way_data_upd13_wayA <= p0_congr_cl13_act_q and binv_wayA_upd3_q; +p1_way_data_upd13_wayA <= p1_congr_cl13_act_q and reload_wayA_upd3_q; +rel_bixu13_wayA_upd(0) <= p1_way_data_upd13_wayA and p1_wren_q; +rel_bixu13_wayA_upd(1) <= p0_way_data_upd13_wayA and p0_wren_q; +p0_way_data_upd13_wayB <= p0_congr_cl13_act_q and binv_wayB_upd3_q; +p1_way_data_upd13_wayB <= p1_congr_cl13_act_q and reload_wayB_upd3_q; +rel_bixu13_wayB_upd(0) <= p1_way_data_upd13_wayB and p1_wren_q; +rel_bixu13_wayB_upd(1) <= p0_way_data_upd13_wayB and p0_wren_q; +p0_way_data_upd13_wayC <= p0_congr_cl13_act_q and binv_wayC_upd3_q; +p1_way_data_upd13_wayC <= p1_congr_cl13_act_q and reload_wayC_upd3_q; +rel_bixu13_wayC_upd(0) <= p1_way_data_upd13_wayC and p1_wren_q; +rel_bixu13_wayC_upd(1) <= p0_way_data_upd13_wayC and p0_wren_q; +p0_way_data_upd13_wayD <= p0_congr_cl13_act_q and binv_wayD_upd3_q; +p1_way_data_upd13_wayD <= p1_congr_cl13_act_q and reload_wayD_upd3_q; +rel_bixu13_wayD_upd(0) <= p1_way_data_upd13_wayD and p1_wren_q; +rel_bixu13_wayD_upd(1) <= p0_way_data_upd13_wayD and p0_wren_q; +p0_way_data_upd13_wayE <= p0_congr_cl13_act_q and binv_wayE_upd3_q; +p1_way_data_upd13_wayE <= p1_congr_cl13_act_q and reload_wayE_upd3_q; +rel_bixu13_wayE_upd(0) <= p1_way_data_upd13_wayE and p1_wren_q; +rel_bixu13_wayE_upd(1) <= p0_way_data_upd13_wayE and p0_wren_q; +p0_way_data_upd13_wayF <= p0_congr_cl13_act_q and binv_wayF_upd3_q; +p1_way_data_upd13_wayF <= p1_congr_cl13_act_q and reload_wayF_upd3_q; +rel_bixu13_wayF_upd(0) <= p1_way_data_upd13_wayF and p1_wren_q; +rel_bixu13_wayF_upd(1) <= p0_way_data_upd13_wayF and p0_wren_q; +p0_way_data_upd13_wayG <= p0_congr_cl13_act_q and binv_wayG_upd3_q; +p1_way_data_upd13_wayG <= p1_congr_cl13_act_q and reload_wayG_upd3_q; +rel_bixu13_wayG_upd(0) <= p1_way_data_upd13_wayG and p1_wren_q; +rel_bixu13_wayG_upd(1) <= p0_way_data_upd13_wayG and p0_wren_q; +p0_way_data_upd13_wayH <= p0_congr_cl13_act_q and binv_wayH_upd3_q; +p1_way_data_upd13_wayH <= p1_congr_cl13_act_q and reload_wayH_upd3_q; +rel_bixu13_wayH_upd(0) <= p1_way_data_upd13_wayH and p1_wren_q; +rel_bixu13_wayH_upd(1) <= p0_way_data_upd13_wayH and p0_wren_q; +p0_congr_cl14_m <= (ex5_congr_cl_q = tconv(14,6)); +p1_congr_cl14_m <= (relu_s_congr_cl_q = tconv(14,6)); +p0_congr_cl14_act_d <= p0_congr_cl14_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl14_act_d <= p1_congr_cl14_m and rel_port_wren_q; +congr_cl14_act <= p0_congr_cl14_act_q or p1_congr_cl14_act_q or congr_cl_all_act_q; +p0_way_data_upd14_wayA <= p0_congr_cl14_act_q and binv_wayA_upd3_q; +p1_way_data_upd14_wayA <= p1_congr_cl14_act_q and reload_wayA_upd3_q; +rel_bixu14_wayA_upd(0) <= p1_way_data_upd14_wayA and p1_wren_q; +rel_bixu14_wayA_upd(1) <= p0_way_data_upd14_wayA and p0_wren_q; +p0_way_data_upd14_wayB <= p0_congr_cl14_act_q and binv_wayB_upd3_q; +p1_way_data_upd14_wayB <= p1_congr_cl14_act_q and reload_wayB_upd3_q; +rel_bixu14_wayB_upd(0) <= p1_way_data_upd14_wayB and p1_wren_q; +rel_bixu14_wayB_upd(1) <= p0_way_data_upd14_wayB and p0_wren_q; +p0_way_data_upd14_wayC <= p0_congr_cl14_act_q and binv_wayC_upd3_q; +p1_way_data_upd14_wayC <= p1_congr_cl14_act_q and reload_wayC_upd3_q; +rel_bixu14_wayC_upd(0) <= p1_way_data_upd14_wayC and p1_wren_q; +rel_bixu14_wayC_upd(1) <= p0_way_data_upd14_wayC and p0_wren_q; +p0_way_data_upd14_wayD <= p0_congr_cl14_act_q and binv_wayD_upd3_q; +p1_way_data_upd14_wayD <= p1_congr_cl14_act_q and reload_wayD_upd3_q; +rel_bixu14_wayD_upd(0) <= p1_way_data_upd14_wayD and p1_wren_q; +rel_bixu14_wayD_upd(1) <= p0_way_data_upd14_wayD and p0_wren_q; +p0_way_data_upd14_wayE <= p0_congr_cl14_act_q and binv_wayE_upd3_q; +p1_way_data_upd14_wayE <= p1_congr_cl14_act_q and reload_wayE_upd3_q; +rel_bixu14_wayE_upd(0) <= p1_way_data_upd14_wayE and p1_wren_q; +rel_bixu14_wayE_upd(1) <= p0_way_data_upd14_wayE and p0_wren_q; +p0_way_data_upd14_wayF <= p0_congr_cl14_act_q and binv_wayF_upd3_q; +p1_way_data_upd14_wayF <= p1_congr_cl14_act_q and reload_wayF_upd3_q; +rel_bixu14_wayF_upd(0) <= p1_way_data_upd14_wayF and p1_wren_q; +rel_bixu14_wayF_upd(1) <= p0_way_data_upd14_wayF and p0_wren_q; +p0_way_data_upd14_wayG <= p0_congr_cl14_act_q and binv_wayG_upd3_q; +p1_way_data_upd14_wayG <= p1_congr_cl14_act_q and reload_wayG_upd3_q; +rel_bixu14_wayG_upd(0) <= p1_way_data_upd14_wayG and p1_wren_q; +rel_bixu14_wayG_upd(1) <= p0_way_data_upd14_wayG and p0_wren_q; +p0_way_data_upd14_wayH <= p0_congr_cl14_act_q and binv_wayH_upd3_q; +p1_way_data_upd14_wayH <= p1_congr_cl14_act_q and reload_wayH_upd3_q; +rel_bixu14_wayH_upd(0) <= p1_way_data_upd14_wayH and p1_wren_q; +rel_bixu14_wayH_upd(1) <= p0_way_data_upd14_wayH and p0_wren_q; +p0_congr_cl15_m <= (ex5_congr_cl_q = tconv(15,6)); +p1_congr_cl15_m <= (relu_s_congr_cl_q = tconv(15,6)); +p0_congr_cl15_act_d <= p0_congr_cl15_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl15_act_d <= p1_congr_cl15_m and rel_port_wren_q; +congr_cl15_act <= p0_congr_cl15_act_q or p1_congr_cl15_act_q or congr_cl_all_act_q; +p0_way_data_upd15_wayA <= p0_congr_cl15_act_q and binv_wayA_upd3_q; +p1_way_data_upd15_wayA <= p1_congr_cl15_act_q and reload_wayA_upd3_q; +rel_bixu15_wayA_upd(0) <= p1_way_data_upd15_wayA and p1_wren_q; +rel_bixu15_wayA_upd(1) <= p0_way_data_upd15_wayA and p0_wren_q; +p0_way_data_upd15_wayB <= p0_congr_cl15_act_q and binv_wayB_upd3_q; +p1_way_data_upd15_wayB <= p1_congr_cl15_act_q and reload_wayB_upd3_q; +rel_bixu15_wayB_upd(0) <= p1_way_data_upd15_wayB and p1_wren_q; +rel_bixu15_wayB_upd(1) <= p0_way_data_upd15_wayB and p0_wren_q; +p0_way_data_upd15_wayC <= p0_congr_cl15_act_q and binv_wayC_upd3_q; +p1_way_data_upd15_wayC <= p1_congr_cl15_act_q and reload_wayC_upd3_q; +rel_bixu15_wayC_upd(0) <= p1_way_data_upd15_wayC and p1_wren_q; +rel_bixu15_wayC_upd(1) <= p0_way_data_upd15_wayC and p0_wren_q; +p0_way_data_upd15_wayD <= p0_congr_cl15_act_q and binv_wayD_upd3_q; +p1_way_data_upd15_wayD <= p1_congr_cl15_act_q and reload_wayD_upd3_q; +rel_bixu15_wayD_upd(0) <= p1_way_data_upd15_wayD and p1_wren_q; +rel_bixu15_wayD_upd(1) <= p0_way_data_upd15_wayD and p0_wren_q; +p0_way_data_upd15_wayE <= p0_congr_cl15_act_q and binv_wayE_upd3_q; +p1_way_data_upd15_wayE <= p1_congr_cl15_act_q and reload_wayE_upd3_q; +rel_bixu15_wayE_upd(0) <= p1_way_data_upd15_wayE and p1_wren_q; +rel_bixu15_wayE_upd(1) <= p0_way_data_upd15_wayE and p0_wren_q; +p0_way_data_upd15_wayF <= p0_congr_cl15_act_q and binv_wayF_upd3_q; +p1_way_data_upd15_wayF <= p1_congr_cl15_act_q and reload_wayF_upd3_q; +rel_bixu15_wayF_upd(0) <= p1_way_data_upd15_wayF and p1_wren_q; +rel_bixu15_wayF_upd(1) <= p0_way_data_upd15_wayF and p0_wren_q; +p0_way_data_upd15_wayG <= p0_congr_cl15_act_q and binv_wayG_upd3_q; +p1_way_data_upd15_wayG <= p1_congr_cl15_act_q and reload_wayG_upd3_q; +rel_bixu15_wayG_upd(0) <= p1_way_data_upd15_wayG and p1_wren_q; +rel_bixu15_wayG_upd(1) <= p0_way_data_upd15_wayG and p0_wren_q; +p0_way_data_upd15_wayH <= p0_congr_cl15_act_q and binv_wayH_upd3_q; +p1_way_data_upd15_wayH <= p1_congr_cl15_act_q and reload_wayH_upd3_q; +rel_bixu15_wayH_upd(0) <= p1_way_data_upd15_wayH and p1_wren_q; +rel_bixu15_wayH_upd(1) <= p0_way_data_upd15_wayH and p0_wren_q; +p0_congr_cl16_m <= (ex5_congr_cl_q = tconv(16,6)); +p1_congr_cl16_m <= (relu_s_congr_cl_q = tconv(16,6)); +p0_congr_cl16_act_d <= p0_congr_cl16_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl16_act_d <= p1_congr_cl16_m and rel_port_wren_q; +congr_cl16_act <= p0_congr_cl16_act_q or p1_congr_cl16_act_q or congr_cl_all_act_q; +p0_way_data_upd16_wayA <= p0_congr_cl16_act_q and binv_wayA_upd3_q; +p1_way_data_upd16_wayA <= p1_congr_cl16_act_q and reload_wayA_upd3_q; +rel_bixu16_wayA_upd(0) <= p1_way_data_upd16_wayA and p1_wren_q; +rel_bixu16_wayA_upd(1) <= p0_way_data_upd16_wayA and p0_wren_q; +p0_way_data_upd16_wayB <= p0_congr_cl16_act_q and binv_wayB_upd3_q; +p1_way_data_upd16_wayB <= p1_congr_cl16_act_q and reload_wayB_upd3_q; +rel_bixu16_wayB_upd(0) <= p1_way_data_upd16_wayB and p1_wren_q; +rel_bixu16_wayB_upd(1) <= p0_way_data_upd16_wayB and p0_wren_q; +p0_way_data_upd16_wayC <= p0_congr_cl16_act_q and binv_wayC_upd3_q; +p1_way_data_upd16_wayC <= p1_congr_cl16_act_q and reload_wayC_upd3_q; +rel_bixu16_wayC_upd(0) <= p1_way_data_upd16_wayC and p1_wren_q; +rel_bixu16_wayC_upd(1) <= p0_way_data_upd16_wayC and p0_wren_q; +p0_way_data_upd16_wayD <= p0_congr_cl16_act_q and binv_wayD_upd3_q; +p1_way_data_upd16_wayD <= p1_congr_cl16_act_q and reload_wayD_upd3_q; +rel_bixu16_wayD_upd(0) <= p1_way_data_upd16_wayD and p1_wren_q; +rel_bixu16_wayD_upd(1) <= p0_way_data_upd16_wayD and p0_wren_q; +p0_way_data_upd16_wayE <= p0_congr_cl16_act_q and binv_wayE_upd3_q; +p1_way_data_upd16_wayE <= p1_congr_cl16_act_q and reload_wayE_upd3_q; +rel_bixu16_wayE_upd(0) <= p1_way_data_upd16_wayE and p1_wren_q; +rel_bixu16_wayE_upd(1) <= p0_way_data_upd16_wayE and p0_wren_q; +p0_way_data_upd16_wayF <= p0_congr_cl16_act_q and binv_wayF_upd3_q; +p1_way_data_upd16_wayF <= p1_congr_cl16_act_q and reload_wayF_upd3_q; +rel_bixu16_wayF_upd(0) <= p1_way_data_upd16_wayF and p1_wren_q; +rel_bixu16_wayF_upd(1) <= p0_way_data_upd16_wayF and p0_wren_q; +p0_way_data_upd16_wayG <= p0_congr_cl16_act_q and binv_wayG_upd3_q; +p1_way_data_upd16_wayG <= p1_congr_cl16_act_q and reload_wayG_upd3_q; +rel_bixu16_wayG_upd(0) <= p1_way_data_upd16_wayG and p1_wren_q; +rel_bixu16_wayG_upd(1) <= p0_way_data_upd16_wayG and p0_wren_q; +p0_way_data_upd16_wayH <= p0_congr_cl16_act_q and binv_wayH_upd3_q; +p1_way_data_upd16_wayH <= p1_congr_cl16_act_q and reload_wayH_upd3_q; +rel_bixu16_wayH_upd(0) <= p1_way_data_upd16_wayH and p1_wren_q; +rel_bixu16_wayH_upd(1) <= p0_way_data_upd16_wayH and p0_wren_q; +p0_congr_cl17_m <= (ex5_congr_cl_q = tconv(17,6)); +p1_congr_cl17_m <= (relu_s_congr_cl_q = tconv(17,6)); +p0_congr_cl17_act_d <= p0_congr_cl17_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl17_act_d <= p1_congr_cl17_m and rel_port_wren_q; +congr_cl17_act <= p0_congr_cl17_act_q or p1_congr_cl17_act_q or congr_cl_all_act_q; +p0_way_data_upd17_wayA <= p0_congr_cl17_act_q and binv_wayA_upd3_q; +p1_way_data_upd17_wayA <= p1_congr_cl17_act_q and reload_wayA_upd3_q; +rel_bixu17_wayA_upd(0) <= p1_way_data_upd17_wayA and p1_wren_q; +rel_bixu17_wayA_upd(1) <= p0_way_data_upd17_wayA and p0_wren_q; +p0_way_data_upd17_wayB <= p0_congr_cl17_act_q and binv_wayB_upd3_q; +p1_way_data_upd17_wayB <= p1_congr_cl17_act_q and reload_wayB_upd3_q; +rel_bixu17_wayB_upd(0) <= p1_way_data_upd17_wayB and p1_wren_q; +rel_bixu17_wayB_upd(1) <= p0_way_data_upd17_wayB and p0_wren_q; +p0_way_data_upd17_wayC <= p0_congr_cl17_act_q and binv_wayC_upd3_q; +p1_way_data_upd17_wayC <= p1_congr_cl17_act_q and reload_wayC_upd3_q; +rel_bixu17_wayC_upd(0) <= p1_way_data_upd17_wayC and p1_wren_q; +rel_bixu17_wayC_upd(1) <= p0_way_data_upd17_wayC and p0_wren_q; +p0_way_data_upd17_wayD <= p0_congr_cl17_act_q and binv_wayD_upd3_q; +p1_way_data_upd17_wayD <= p1_congr_cl17_act_q and reload_wayD_upd3_q; +rel_bixu17_wayD_upd(0) <= p1_way_data_upd17_wayD and p1_wren_q; +rel_bixu17_wayD_upd(1) <= p0_way_data_upd17_wayD and p0_wren_q; +p0_way_data_upd17_wayE <= p0_congr_cl17_act_q and binv_wayE_upd3_q; +p1_way_data_upd17_wayE <= p1_congr_cl17_act_q and reload_wayE_upd3_q; +rel_bixu17_wayE_upd(0) <= p1_way_data_upd17_wayE and p1_wren_q; +rel_bixu17_wayE_upd(1) <= p0_way_data_upd17_wayE and p0_wren_q; +p0_way_data_upd17_wayF <= p0_congr_cl17_act_q and binv_wayF_upd3_q; +p1_way_data_upd17_wayF <= p1_congr_cl17_act_q and reload_wayF_upd3_q; +rel_bixu17_wayF_upd(0) <= p1_way_data_upd17_wayF and p1_wren_q; +rel_bixu17_wayF_upd(1) <= p0_way_data_upd17_wayF and p0_wren_q; +p0_way_data_upd17_wayG <= p0_congr_cl17_act_q and binv_wayG_upd3_q; +p1_way_data_upd17_wayG <= p1_congr_cl17_act_q and reload_wayG_upd3_q; +rel_bixu17_wayG_upd(0) <= p1_way_data_upd17_wayG and p1_wren_q; +rel_bixu17_wayG_upd(1) <= p0_way_data_upd17_wayG and p0_wren_q; +p0_way_data_upd17_wayH <= p0_congr_cl17_act_q and binv_wayH_upd3_q; +p1_way_data_upd17_wayH <= p1_congr_cl17_act_q and reload_wayH_upd3_q; +rel_bixu17_wayH_upd(0) <= p1_way_data_upd17_wayH and p1_wren_q; +rel_bixu17_wayH_upd(1) <= p0_way_data_upd17_wayH and p0_wren_q; +p0_congr_cl18_m <= (ex5_congr_cl_q = tconv(18,6)); +p1_congr_cl18_m <= (relu_s_congr_cl_q = tconv(18,6)); +p0_congr_cl18_act_d <= p0_congr_cl18_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl18_act_d <= p1_congr_cl18_m and rel_port_wren_q; +congr_cl18_act <= p0_congr_cl18_act_q or p1_congr_cl18_act_q or congr_cl_all_act_q; +p0_way_data_upd18_wayA <= p0_congr_cl18_act_q and binv_wayA_upd3_q; +p1_way_data_upd18_wayA <= p1_congr_cl18_act_q and reload_wayA_upd3_q; +rel_bixu18_wayA_upd(0) <= p1_way_data_upd18_wayA and p1_wren_q; +rel_bixu18_wayA_upd(1) <= p0_way_data_upd18_wayA and p0_wren_q; +p0_way_data_upd18_wayB <= p0_congr_cl18_act_q and binv_wayB_upd3_q; +p1_way_data_upd18_wayB <= p1_congr_cl18_act_q and reload_wayB_upd3_q; +rel_bixu18_wayB_upd(0) <= p1_way_data_upd18_wayB and p1_wren_q; +rel_bixu18_wayB_upd(1) <= p0_way_data_upd18_wayB and p0_wren_q; +p0_way_data_upd18_wayC <= p0_congr_cl18_act_q and binv_wayC_upd3_q; +p1_way_data_upd18_wayC <= p1_congr_cl18_act_q and reload_wayC_upd3_q; +rel_bixu18_wayC_upd(0) <= p1_way_data_upd18_wayC and p1_wren_q; +rel_bixu18_wayC_upd(1) <= p0_way_data_upd18_wayC and p0_wren_q; +p0_way_data_upd18_wayD <= p0_congr_cl18_act_q and binv_wayD_upd3_q; +p1_way_data_upd18_wayD <= p1_congr_cl18_act_q and reload_wayD_upd3_q; +rel_bixu18_wayD_upd(0) <= p1_way_data_upd18_wayD and p1_wren_q; +rel_bixu18_wayD_upd(1) <= p0_way_data_upd18_wayD and p0_wren_q; +p0_way_data_upd18_wayE <= p0_congr_cl18_act_q and binv_wayE_upd3_q; +p1_way_data_upd18_wayE <= p1_congr_cl18_act_q and reload_wayE_upd3_q; +rel_bixu18_wayE_upd(0) <= p1_way_data_upd18_wayE and p1_wren_q; +rel_bixu18_wayE_upd(1) <= p0_way_data_upd18_wayE and p0_wren_q; +p0_way_data_upd18_wayF <= p0_congr_cl18_act_q and binv_wayF_upd3_q; +p1_way_data_upd18_wayF <= p1_congr_cl18_act_q and reload_wayF_upd3_q; +rel_bixu18_wayF_upd(0) <= p1_way_data_upd18_wayF and p1_wren_q; +rel_bixu18_wayF_upd(1) <= p0_way_data_upd18_wayF and p0_wren_q; +p0_way_data_upd18_wayG <= p0_congr_cl18_act_q and binv_wayG_upd3_q; +p1_way_data_upd18_wayG <= p1_congr_cl18_act_q and reload_wayG_upd3_q; +rel_bixu18_wayG_upd(0) <= p1_way_data_upd18_wayG and p1_wren_q; +rel_bixu18_wayG_upd(1) <= p0_way_data_upd18_wayG and p0_wren_q; +p0_way_data_upd18_wayH <= p0_congr_cl18_act_q and binv_wayH_upd3_q; +p1_way_data_upd18_wayH <= p1_congr_cl18_act_q and reload_wayH_upd3_q; +rel_bixu18_wayH_upd(0) <= p1_way_data_upd18_wayH and p1_wren_q; +rel_bixu18_wayH_upd(1) <= p0_way_data_upd18_wayH and p0_wren_q; +p0_congr_cl19_m <= (ex5_congr_cl_q = tconv(19,6)); +p1_congr_cl19_m <= (relu_s_congr_cl_q = tconv(19,6)); +p0_congr_cl19_act_d <= p0_congr_cl19_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl19_act_d <= p1_congr_cl19_m and rel_port_wren_q; +congr_cl19_act <= p0_congr_cl19_act_q or p1_congr_cl19_act_q or congr_cl_all_act_q; +p0_way_data_upd19_wayA <= p0_congr_cl19_act_q and binv_wayA_upd3_q; +p1_way_data_upd19_wayA <= p1_congr_cl19_act_q and reload_wayA_upd3_q; +rel_bixu19_wayA_upd(0) <= p1_way_data_upd19_wayA and p1_wren_q; +rel_bixu19_wayA_upd(1) <= p0_way_data_upd19_wayA and p0_wren_q; +p0_way_data_upd19_wayB <= p0_congr_cl19_act_q and binv_wayB_upd3_q; +p1_way_data_upd19_wayB <= p1_congr_cl19_act_q and reload_wayB_upd3_q; +rel_bixu19_wayB_upd(0) <= p1_way_data_upd19_wayB and p1_wren_q; +rel_bixu19_wayB_upd(1) <= p0_way_data_upd19_wayB and p0_wren_q; +p0_way_data_upd19_wayC <= p0_congr_cl19_act_q and binv_wayC_upd3_q; +p1_way_data_upd19_wayC <= p1_congr_cl19_act_q and reload_wayC_upd3_q; +rel_bixu19_wayC_upd(0) <= p1_way_data_upd19_wayC and p1_wren_q; +rel_bixu19_wayC_upd(1) <= p0_way_data_upd19_wayC and p0_wren_q; +p0_way_data_upd19_wayD <= p0_congr_cl19_act_q and binv_wayD_upd3_q; +p1_way_data_upd19_wayD <= p1_congr_cl19_act_q and reload_wayD_upd3_q; +rel_bixu19_wayD_upd(0) <= p1_way_data_upd19_wayD and p1_wren_q; +rel_bixu19_wayD_upd(1) <= p0_way_data_upd19_wayD and p0_wren_q; +p0_way_data_upd19_wayE <= p0_congr_cl19_act_q and binv_wayE_upd3_q; +p1_way_data_upd19_wayE <= p1_congr_cl19_act_q and reload_wayE_upd3_q; +rel_bixu19_wayE_upd(0) <= p1_way_data_upd19_wayE and p1_wren_q; +rel_bixu19_wayE_upd(1) <= p0_way_data_upd19_wayE and p0_wren_q; +p0_way_data_upd19_wayF <= p0_congr_cl19_act_q and binv_wayF_upd3_q; +p1_way_data_upd19_wayF <= p1_congr_cl19_act_q and reload_wayF_upd3_q; +rel_bixu19_wayF_upd(0) <= p1_way_data_upd19_wayF and p1_wren_q; +rel_bixu19_wayF_upd(1) <= p0_way_data_upd19_wayF and p0_wren_q; +p0_way_data_upd19_wayG <= p0_congr_cl19_act_q and binv_wayG_upd3_q; +p1_way_data_upd19_wayG <= p1_congr_cl19_act_q and reload_wayG_upd3_q; +rel_bixu19_wayG_upd(0) <= p1_way_data_upd19_wayG and p1_wren_q; +rel_bixu19_wayG_upd(1) <= p0_way_data_upd19_wayG and p0_wren_q; +p0_way_data_upd19_wayH <= p0_congr_cl19_act_q and binv_wayH_upd3_q; +p1_way_data_upd19_wayH <= p1_congr_cl19_act_q and reload_wayH_upd3_q; +rel_bixu19_wayH_upd(0) <= p1_way_data_upd19_wayH and p1_wren_q; +rel_bixu19_wayH_upd(1) <= p0_way_data_upd19_wayH and p0_wren_q; +p0_congr_cl20_m <= (ex5_congr_cl_q = tconv(20,6)); +p1_congr_cl20_m <= (relu_s_congr_cl_q = tconv(20,6)); +p0_congr_cl20_act_d <= p0_congr_cl20_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl20_act_d <= p1_congr_cl20_m and rel_port_wren_q; +congr_cl20_act <= p0_congr_cl20_act_q or p1_congr_cl20_act_q or congr_cl_all_act_q; +p0_way_data_upd20_wayA <= p0_congr_cl20_act_q and binv_wayA_upd3_q; +p1_way_data_upd20_wayA <= p1_congr_cl20_act_q and reload_wayA_upd3_q; +rel_bixu20_wayA_upd(0) <= p1_way_data_upd20_wayA and p1_wren_q; +rel_bixu20_wayA_upd(1) <= p0_way_data_upd20_wayA and p0_wren_q; +p0_way_data_upd20_wayB <= p0_congr_cl20_act_q and binv_wayB_upd3_q; +p1_way_data_upd20_wayB <= p1_congr_cl20_act_q and reload_wayB_upd3_q; +rel_bixu20_wayB_upd(0) <= p1_way_data_upd20_wayB and p1_wren_q; +rel_bixu20_wayB_upd(1) <= p0_way_data_upd20_wayB and p0_wren_q; +p0_way_data_upd20_wayC <= p0_congr_cl20_act_q and binv_wayC_upd3_q; +p1_way_data_upd20_wayC <= p1_congr_cl20_act_q and reload_wayC_upd3_q; +rel_bixu20_wayC_upd(0) <= p1_way_data_upd20_wayC and p1_wren_q; +rel_bixu20_wayC_upd(1) <= p0_way_data_upd20_wayC and p0_wren_q; +p0_way_data_upd20_wayD <= p0_congr_cl20_act_q and binv_wayD_upd3_q; +p1_way_data_upd20_wayD <= p1_congr_cl20_act_q and reload_wayD_upd3_q; +rel_bixu20_wayD_upd(0) <= p1_way_data_upd20_wayD and p1_wren_q; +rel_bixu20_wayD_upd(1) <= p0_way_data_upd20_wayD and p0_wren_q; +p0_way_data_upd20_wayE <= p0_congr_cl20_act_q and binv_wayE_upd3_q; +p1_way_data_upd20_wayE <= p1_congr_cl20_act_q and reload_wayE_upd3_q; +rel_bixu20_wayE_upd(0) <= p1_way_data_upd20_wayE and p1_wren_q; +rel_bixu20_wayE_upd(1) <= p0_way_data_upd20_wayE and p0_wren_q; +p0_way_data_upd20_wayF <= p0_congr_cl20_act_q and binv_wayF_upd3_q; +p1_way_data_upd20_wayF <= p1_congr_cl20_act_q and reload_wayF_upd3_q; +rel_bixu20_wayF_upd(0) <= p1_way_data_upd20_wayF and p1_wren_q; +rel_bixu20_wayF_upd(1) <= p0_way_data_upd20_wayF and p0_wren_q; +p0_way_data_upd20_wayG <= p0_congr_cl20_act_q and binv_wayG_upd3_q; +p1_way_data_upd20_wayG <= p1_congr_cl20_act_q and reload_wayG_upd3_q; +rel_bixu20_wayG_upd(0) <= p1_way_data_upd20_wayG and p1_wren_q; +rel_bixu20_wayG_upd(1) <= p0_way_data_upd20_wayG and p0_wren_q; +p0_way_data_upd20_wayH <= p0_congr_cl20_act_q and binv_wayH_upd3_q; +p1_way_data_upd20_wayH <= p1_congr_cl20_act_q and reload_wayH_upd3_q; +rel_bixu20_wayH_upd(0) <= p1_way_data_upd20_wayH and p1_wren_q; +rel_bixu20_wayH_upd(1) <= p0_way_data_upd20_wayH and p0_wren_q; +p0_congr_cl21_m <= (ex5_congr_cl_q = tconv(21,6)); +p1_congr_cl21_m <= (relu_s_congr_cl_q = tconv(21,6)); +p0_congr_cl21_act_d <= p0_congr_cl21_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl21_act_d <= p1_congr_cl21_m and rel_port_wren_q; +congr_cl21_act <= p0_congr_cl21_act_q or p1_congr_cl21_act_q or congr_cl_all_act_q; +p0_way_data_upd21_wayA <= p0_congr_cl21_act_q and binv_wayA_upd3_q; +p1_way_data_upd21_wayA <= p1_congr_cl21_act_q and reload_wayA_upd3_q; +rel_bixu21_wayA_upd(0) <= p1_way_data_upd21_wayA and p1_wren_q; +rel_bixu21_wayA_upd(1) <= p0_way_data_upd21_wayA and p0_wren_q; +p0_way_data_upd21_wayB <= p0_congr_cl21_act_q and binv_wayB_upd3_q; +p1_way_data_upd21_wayB <= p1_congr_cl21_act_q and reload_wayB_upd3_q; +rel_bixu21_wayB_upd(0) <= p1_way_data_upd21_wayB and p1_wren_q; +rel_bixu21_wayB_upd(1) <= p0_way_data_upd21_wayB and p0_wren_q; +p0_way_data_upd21_wayC <= p0_congr_cl21_act_q and binv_wayC_upd3_q; +p1_way_data_upd21_wayC <= p1_congr_cl21_act_q and reload_wayC_upd3_q; +rel_bixu21_wayC_upd(0) <= p1_way_data_upd21_wayC and p1_wren_q; +rel_bixu21_wayC_upd(1) <= p0_way_data_upd21_wayC and p0_wren_q; +p0_way_data_upd21_wayD <= p0_congr_cl21_act_q and binv_wayD_upd3_q; +p1_way_data_upd21_wayD <= p1_congr_cl21_act_q and reload_wayD_upd3_q; +rel_bixu21_wayD_upd(0) <= p1_way_data_upd21_wayD and p1_wren_q; +rel_bixu21_wayD_upd(1) <= p0_way_data_upd21_wayD and p0_wren_q; +p0_way_data_upd21_wayE <= p0_congr_cl21_act_q and binv_wayE_upd3_q; +p1_way_data_upd21_wayE <= p1_congr_cl21_act_q and reload_wayE_upd3_q; +rel_bixu21_wayE_upd(0) <= p1_way_data_upd21_wayE and p1_wren_q; +rel_bixu21_wayE_upd(1) <= p0_way_data_upd21_wayE and p0_wren_q; +p0_way_data_upd21_wayF <= p0_congr_cl21_act_q and binv_wayF_upd3_q; +p1_way_data_upd21_wayF <= p1_congr_cl21_act_q and reload_wayF_upd3_q; +rel_bixu21_wayF_upd(0) <= p1_way_data_upd21_wayF and p1_wren_q; +rel_bixu21_wayF_upd(1) <= p0_way_data_upd21_wayF and p0_wren_q; +p0_way_data_upd21_wayG <= p0_congr_cl21_act_q and binv_wayG_upd3_q; +p1_way_data_upd21_wayG <= p1_congr_cl21_act_q and reload_wayG_upd3_q; +rel_bixu21_wayG_upd(0) <= p1_way_data_upd21_wayG and p1_wren_q; +rel_bixu21_wayG_upd(1) <= p0_way_data_upd21_wayG and p0_wren_q; +p0_way_data_upd21_wayH <= p0_congr_cl21_act_q and binv_wayH_upd3_q; +p1_way_data_upd21_wayH <= p1_congr_cl21_act_q and reload_wayH_upd3_q; +rel_bixu21_wayH_upd(0) <= p1_way_data_upd21_wayH and p1_wren_q; +rel_bixu21_wayH_upd(1) <= p0_way_data_upd21_wayH and p0_wren_q; +p0_congr_cl22_m <= (ex5_congr_cl_q = tconv(22,6)); +p1_congr_cl22_m <= (relu_s_congr_cl_q = tconv(22,6)); +p0_congr_cl22_act_d <= p0_congr_cl22_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl22_act_d <= p1_congr_cl22_m and rel_port_wren_q; +congr_cl22_act <= p0_congr_cl22_act_q or p1_congr_cl22_act_q or congr_cl_all_act_q; +p0_way_data_upd22_wayA <= p0_congr_cl22_act_q and binv_wayA_upd3_q; +p1_way_data_upd22_wayA <= p1_congr_cl22_act_q and reload_wayA_upd3_q; +rel_bixu22_wayA_upd(0) <= p1_way_data_upd22_wayA and p1_wren_q; +rel_bixu22_wayA_upd(1) <= p0_way_data_upd22_wayA and p0_wren_q; +p0_way_data_upd22_wayB <= p0_congr_cl22_act_q and binv_wayB_upd3_q; +p1_way_data_upd22_wayB <= p1_congr_cl22_act_q and reload_wayB_upd3_q; +rel_bixu22_wayB_upd(0) <= p1_way_data_upd22_wayB and p1_wren_q; +rel_bixu22_wayB_upd(1) <= p0_way_data_upd22_wayB and p0_wren_q; +p0_way_data_upd22_wayC <= p0_congr_cl22_act_q and binv_wayC_upd3_q; +p1_way_data_upd22_wayC <= p1_congr_cl22_act_q and reload_wayC_upd3_q; +rel_bixu22_wayC_upd(0) <= p1_way_data_upd22_wayC and p1_wren_q; +rel_bixu22_wayC_upd(1) <= p0_way_data_upd22_wayC and p0_wren_q; +p0_way_data_upd22_wayD <= p0_congr_cl22_act_q and binv_wayD_upd3_q; +p1_way_data_upd22_wayD <= p1_congr_cl22_act_q and reload_wayD_upd3_q; +rel_bixu22_wayD_upd(0) <= p1_way_data_upd22_wayD and p1_wren_q; +rel_bixu22_wayD_upd(1) <= p0_way_data_upd22_wayD and p0_wren_q; +p0_way_data_upd22_wayE <= p0_congr_cl22_act_q and binv_wayE_upd3_q; +p1_way_data_upd22_wayE <= p1_congr_cl22_act_q and reload_wayE_upd3_q; +rel_bixu22_wayE_upd(0) <= p1_way_data_upd22_wayE and p1_wren_q; +rel_bixu22_wayE_upd(1) <= p0_way_data_upd22_wayE and p0_wren_q; +p0_way_data_upd22_wayF <= p0_congr_cl22_act_q and binv_wayF_upd3_q; +p1_way_data_upd22_wayF <= p1_congr_cl22_act_q and reload_wayF_upd3_q; +rel_bixu22_wayF_upd(0) <= p1_way_data_upd22_wayF and p1_wren_q; +rel_bixu22_wayF_upd(1) <= p0_way_data_upd22_wayF and p0_wren_q; +p0_way_data_upd22_wayG <= p0_congr_cl22_act_q and binv_wayG_upd3_q; +p1_way_data_upd22_wayG <= p1_congr_cl22_act_q and reload_wayG_upd3_q; +rel_bixu22_wayG_upd(0) <= p1_way_data_upd22_wayG and p1_wren_q; +rel_bixu22_wayG_upd(1) <= p0_way_data_upd22_wayG and p0_wren_q; +p0_way_data_upd22_wayH <= p0_congr_cl22_act_q and binv_wayH_upd3_q; +p1_way_data_upd22_wayH <= p1_congr_cl22_act_q and reload_wayH_upd3_q; +rel_bixu22_wayH_upd(0) <= p1_way_data_upd22_wayH and p1_wren_q; +rel_bixu22_wayH_upd(1) <= p0_way_data_upd22_wayH and p0_wren_q; +p0_congr_cl23_m <= (ex5_congr_cl_q = tconv(23,6)); +p1_congr_cl23_m <= (relu_s_congr_cl_q = tconv(23,6)); +p0_congr_cl23_act_d <= p0_congr_cl23_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl23_act_d <= p1_congr_cl23_m and rel_port_wren_q; +congr_cl23_act <= p0_congr_cl23_act_q or p1_congr_cl23_act_q or congr_cl_all_act_q; +p0_way_data_upd23_wayA <= p0_congr_cl23_act_q and binv_wayA_upd3_q; +p1_way_data_upd23_wayA <= p1_congr_cl23_act_q and reload_wayA_upd3_q; +rel_bixu23_wayA_upd(0) <= p1_way_data_upd23_wayA and p1_wren_q; +rel_bixu23_wayA_upd(1) <= p0_way_data_upd23_wayA and p0_wren_q; +p0_way_data_upd23_wayB <= p0_congr_cl23_act_q and binv_wayB_upd3_q; +p1_way_data_upd23_wayB <= p1_congr_cl23_act_q and reload_wayB_upd3_q; +rel_bixu23_wayB_upd(0) <= p1_way_data_upd23_wayB and p1_wren_q; +rel_bixu23_wayB_upd(1) <= p0_way_data_upd23_wayB and p0_wren_q; +p0_way_data_upd23_wayC <= p0_congr_cl23_act_q and binv_wayC_upd3_q; +p1_way_data_upd23_wayC <= p1_congr_cl23_act_q and reload_wayC_upd3_q; +rel_bixu23_wayC_upd(0) <= p1_way_data_upd23_wayC and p1_wren_q; +rel_bixu23_wayC_upd(1) <= p0_way_data_upd23_wayC and p0_wren_q; +p0_way_data_upd23_wayD <= p0_congr_cl23_act_q and binv_wayD_upd3_q; +p1_way_data_upd23_wayD <= p1_congr_cl23_act_q and reload_wayD_upd3_q; +rel_bixu23_wayD_upd(0) <= p1_way_data_upd23_wayD and p1_wren_q; +rel_bixu23_wayD_upd(1) <= p0_way_data_upd23_wayD and p0_wren_q; +p0_way_data_upd23_wayE <= p0_congr_cl23_act_q and binv_wayE_upd3_q; +p1_way_data_upd23_wayE <= p1_congr_cl23_act_q and reload_wayE_upd3_q; +rel_bixu23_wayE_upd(0) <= p1_way_data_upd23_wayE and p1_wren_q; +rel_bixu23_wayE_upd(1) <= p0_way_data_upd23_wayE and p0_wren_q; +p0_way_data_upd23_wayF <= p0_congr_cl23_act_q and binv_wayF_upd3_q; +p1_way_data_upd23_wayF <= p1_congr_cl23_act_q and reload_wayF_upd3_q; +rel_bixu23_wayF_upd(0) <= p1_way_data_upd23_wayF and p1_wren_q; +rel_bixu23_wayF_upd(1) <= p0_way_data_upd23_wayF and p0_wren_q; +p0_way_data_upd23_wayG <= p0_congr_cl23_act_q and binv_wayG_upd3_q; +p1_way_data_upd23_wayG <= p1_congr_cl23_act_q and reload_wayG_upd3_q; +rel_bixu23_wayG_upd(0) <= p1_way_data_upd23_wayG and p1_wren_q; +rel_bixu23_wayG_upd(1) <= p0_way_data_upd23_wayG and p0_wren_q; +p0_way_data_upd23_wayH <= p0_congr_cl23_act_q and binv_wayH_upd3_q; +p1_way_data_upd23_wayH <= p1_congr_cl23_act_q and reload_wayH_upd3_q; +rel_bixu23_wayH_upd(0) <= p1_way_data_upd23_wayH and p1_wren_q; +rel_bixu23_wayH_upd(1) <= p0_way_data_upd23_wayH and p0_wren_q; +p0_congr_cl24_m <= (ex5_congr_cl_q = tconv(24,6)); +p1_congr_cl24_m <= (relu_s_congr_cl_q = tconv(24,6)); +p0_congr_cl24_act_d <= p0_congr_cl24_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl24_act_d <= p1_congr_cl24_m and rel_port_wren_q; +congr_cl24_act <= p0_congr_cl24_act_q or p1_congr_cl24_act_q or congr_cl_all_act_q; +p0_way_data_upd24_wayA <= p0_congr_cl24_act_q and binv_wayA_upd3_q; +p1_way_data_upd24_wayA <= p1_congr_cl24_act_q and reload_wayA_upd3_q; +rel_bixu24_wayA_upd(0) <= p1_way_data_upd24_wayA and p1_wren_q; +rel_bixu24_wayA_upd(1) <= p0_way_data_upd24_wayA and p0_wren_q; +p0_way_data_upd24_wayB <= p0_congr_cl24_act_q and binv_wayB_upd3_q; +p1_way_data_upd24_wayB <= p1_congr_cl24_act_q and reload_wayB_upd3_q; +rel_bixu24_wayB_upd(0) <= p1_way_data_upd24_wayB and p1_wren_q; +rel_bixu24_wayB_upd(1) <= p0_way_data_upd24_wayB and p0_wren_q; +p0_way_data_upd24_wayC <= p0_congr_cl24_act_q and binv_wayC_upd3_q; +p1_way_data_upd24_wayC <= p1_congr_cl24_act_q and reload_wayC_upd3_q; +rel_bixu24_wayC_upd(0) <= p1_way_data_upd24_wayC and p1_wren_q; +rel_bixu24_wayC_upd(1) <= p0_way_data_upd24_wayC and p0_wren_q; +p0_way_data_upd24_wayD <= p0_congr_cl24_act_q and binv_wayD_upd3_q; +p1_way_data_upd24_wayD <= p1_congr_cl24_act_q and reload_wayD_upd3_q; +rel_bixu24_wayD_upd(0) <= p1_way_data_upd24_wayD and p1_wren_q; +rel_bixu24_wayD_upd(1) <= p0_way_data_upd24_wayD and p0_wren_q; +p0_way_data_upd24_wayE <= p0_congr_cl24_act_q and binv_wayE_upd3_q; +p1_way_data_upd24_wayE <= p1_congr_cl24_act_q and reload_wayE_upd3_q; +rel_bixu24_wayE_upd(0) <= p1_way_data_upd24_wayE and p1_wren_q; +rel_bixu24_wayE_upd(1) <= p0_way_data_upd24_wayE and p0_wren_q; +p0_way_data_upd24_wayF <= p0_congr_cl24_act_q and binv_wayF_upd3_q; +p1_way_data_upd24_wayF <= p1_congr_cl24_act_q and reload_wayF_upd3_q; +rel_bixu24_wayF_upd(0) <= p1_way_data_upd24_wayF and p1_wren_q; +rel_bixu24_wayF_upd(1) <= p0_way_data_upd24_wayF and p0_wren_q; +p0_way_data_upd24_wayG <= p0_congr_cl24_act_q and binv_wayG_upd3_q; +p1_way_data_upd24_wayG <= p1_congr_cl24_act_q and reload_wayG_upd3_q; +rel_bixu24_wayG_upd(0) <= p1_way_data_upd24_wayG and p1_wren_q; +rel_bixu24_wayG_upd(1) <= p0_way_data_upd24_wayG and p0_wren_q; +p0_way_data_upd24_wayH <= p0_congr_cl24_act_q and binv_wayH_upd3_q; +p1_way_data_upd24_wayH <= p1_congr_cl24_act_q and reload_wayH_upd3_q; +rel_bixu24_wayH_upd(0) <= p1_way_data_upd24_wayH and p1_wren_q; +rel_bixu24_wayH_upd(1) <= p0_way_data_upd24_wayH and p0_wren_q; +p0_congr_cl25_m <= (ex5_congr_cl_q = tconv(25,6)); +p1_congr_cl25_m <= (relu_s_congr_cl_q = tconv(25,6)); +p0_congr_cl25_act_d <= p0_congr_cl25_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl25_act_d <= p1_congr_cl25_m and rel_port_wren_q; +congr_cl25_act <= p0_congr_cl25_act_q or p1_congr_cl25_act_q or congr_cl_all_act_q; +p0_way_data_upd25_wayA <= p0_congr_cl25_act_q and binv_wayA_upd3_q; +p1_way_data_upd25_wayA <= p1_congr_cl25_act_q and reload_wayA_upd3_q; +rel_bixu25_wayA_upd(0) <= p1_way_data_upd25_wayA and p1_wren_q; +rel_bixu25_wayA_upd(1) <= p0_way_data_upd25_wayA and p0_wren_q; +p0_way_data_upd25_wayB <= p0_congr_cl25_act_q and binv_wayB_upd3_q; +p1_way_data_upd25_wayB <= p1_congr_cl25_act_q and reload_wayB_upd3_q; +rel_bixu25_wayB_upd(0) <= p1_way_data_upd25_wayB and p1_wren_q; +rel_bixu25_wayB_upd(1) <= p0_way_data_upd25_wayB and p0_wren_q; +p0_way_data_upd25_wayC <= p0_congr_cl25_act_q and binv_wayC_upd3_q; +p1_way_data_upd25_wayC <= p1_congr_cl25_act_q and reload_wayC_upd3_q; +rel_bixu25_wayC_upd(0) <= p1_way_data_upd25_wayC and p1_wren_q; +rel_bixu25_wayC_upd(1) <= p0_way_data_upd25_wayC and p0_wren_q; +p0_way_data_upd25_wayD <= p0_congr_cl25_act_q and binv_wayD_upd3_q; +p1_way_data_upd25_wayD <= p1_congr_cl25_act_q and reload_wayD_upd3_q; +rel_bixu25_wayD_upd(0) <= p1_way_data_upd25_wayD and p1_wren_q; +rel_bixu25_wayD_upd(1) <= p0_way_data_upd25_wayD and p0_wren_q; +p0_way_data_upd25_wayE <= p0_congr_cl25_act_q and binv_wayE_upd3_q; +p1_way_data_upd25_wayE <= p1_congr_cl25_act_q and reload_wayE_upd3_q; +rel_bixu25_wayE_upd(0) <= p1_way_data_upd25_wayE and p1_wren_q; +rel_bixu25_wayE_upd(1) <= p0_way_data_upd25_wayE and p0_wren_q; +p0_way_data_upd25_wayF <= p0_congr_cl25_act_q and binv_wayF_upd3_q; +p1_way_data_upd25_wayF <= p1_congr_cl25_act_q and reload_wayF_upd3_q; +rel_bixu25_wayF_upd(0) <= p1_way_data_upd25_wayF and p1_wren_q; +rel_bixu25_wayF_upd(1) <= p0_way_data_upd25_wayF and p0_wren_q; +p0_way_data_upd25_wayG <= p0_congr_cl25_act_q and binv_wayG_upd3_q; +p1_way_data_upd25_wayG <= p1_congr_cl25_act_q and reload_wayG_upd3_q; +rel_bixu25_wayG_upd(0) <= p1_way_data_upd25_wayG and p1_wren_q; +rel_bixu25_wayG_upd(1) <= p0_way_data_upd25_wayG and p0_wren_q; +p0_way_data_upd25_wayH <= p0_congr_cl25_act_q and binv_wayH_upd3_q; +p1_way_data_upd25_wayH <= p1_congr_cl25_act_q and reload_wayH_upd3_q; +rel_bixu25_wayH_upd(0) <= p1_way_data_upd25_wayH and p1_wren_q; +rel_bixu25_wayH_upd(1) <= p0_way_data_upd25_wayH and p0_wren_q; +p0_congr_cl26_m <= (ex5_congr_cl_q = tconv(26,6)); +p1_congr_cl26_m <= (relu_s_congr_cl_q = tconv(26,6)); +p0_congr_cl26_act_d <= p0_congr_cl26_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl26_act_d <= p1_congr_cl26_m and rel_port_wren_q; +congr_cl26_act <= p0_congr_cl26_act_q or p1_congr_cl26_act_q or congr_cl_all_act_q; +p0_way_data_upd26_wayA <= p0_congr_cl26_act_q and binv_wayA_upd3_q; +p1_way_data_upd26_wayA <= p1_congr_cl26_act_q and reload_wayA_upd3_q; +rel_bixu26_wayA_upd(0) <= p1_way_data_upd26_wayA and p1_wren_q; +rel_bixu26_wayA_upd(1) <= p0_way_data_upd26_wayA and p0_wren_q; +p0_way_data_upd26_wayB <= p0_congr_cl26_act_q and binv_wayB_upd3_q; +p1_way_data_upd26_wayB <= p1_congr_cl26_act_q and reload_wayB_upd3_q; +rel_bixu26_wayB_upd(0) <= p1_way_data_upd26_wayB and p1_wren_q; +rel_bixu26_wayB_upd(1) <= p0_way_data_upd26_wayB and p0_wren_q; +p0_way_data_upd26_wayC <= p0_congr_cl26_act_q and binv_wayC_upd3_q; +p1_way_data_upd26_wayC <= p1_congr_cl26_act_q and reload_wayC_upd3_q; +rel_bixu26_wayC_upd(0) <= p1_way_data_upd26_wayC and p1_wren_q; +rel_bixu26_wayC_upd(1) <= p0_way_data_upd26_wayC and p0_wren_q; +p0_way_data_upd26_wayD <= p0_congr_cl26_act_q and binv_wayD_upd3_q; +p1_way_data_upd26_wayD <= p1_congr_cl26_act_q and reload_wayD_upd3_q; +rel_bixu26_wayD_upd(0) <= p1_way_data_upd26_wayD and p1_wren_q; +rel_bixu26_wayD_upd(1) <= p0_way_data_upd26_wayD and p0_wren_q; +p0_way_data_upd26_wayE <= p0_congr_cl26_act_q and binv_wayE_upd3_q; +p1_way_data_upd26_wayE <= p1_congr_cl26_act_q and reload_wayE_upd3_q; +rel_bixu26_wayE_upd(0) <= p1_way_data_upd26_wayE and p1_wren_q; +rel_bixu26_wayE_upd(1) <= p0_way_data_upd26_wayE and p0_wren_q; +p0_way_data_upd26_wayF <= p0_congr_cl26_act_q and binv_wayF_upd3_q; +p1_way_data_upd26_wayF <= p1_congr_cl26_act_q and reload_wayF_upd3_q; +rel_bixu26_wayF_upd(0) <= p1_way_data_upd26_wayF and p1_wren_q; +rel_bixu26_wayF_upd(1) <= p0_way_data_upd26_wayF and p0_wren_q; +p0_way_data_upd26_wayG <= p0_congr_cl26_act_q and binv_wayG_upd3_q; +p1_way_data_upd26_wayG <= p1_congr_cl26_act_q and reload_wayG_upd3_q; +rel_bixu26_wayG_upd(0) <= p1_way_data_upd26_wayG and p1_wren_q; +rel_bixu26_wayG_upd(1) <= p0_way_data_upd26_wayG and p0_wren_q; +p0_way_data_upd26_wayH <= p0_congr_cl26_act_q and binv_wayH_upd3_q; +p1_way_data_upd26_wayH <= p1_congr_cl26_act_q and reload_wayH_upd3_q; +rel_bixu26_wayH_upd(0) <= p1_way_data_upd26_wayH and p1_wren_q; +rel_bixu26_wayH_upd(1) <= p0_way_data_upd26_wayH and p0_wren_q; +p0_congr_cl27_m <= (ex5_congr_cl_q = tconv(27,6)); +p1_congr_cl27_m <= (relu_s_congr_cl_q = tconv(27,6)); +p0_congr_cl27_act_d <= p0_congr_cl27_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl27_act_d <= p1_congr_cl27_m and rel_port_wren_q; +congr_cl27_act <= p0_congr_cl27_act_q or p1_congr_cl27_act_q or congr_cl_all_act_q; +p0_way_data_upd27_wayA <= p0_congr_cl27_act_q and binv_wayA_upd3_q; +p1_way_data_upd27_wayA <= p1_congr_cl27_act_q and reload_wayA_upd3_q; +rel_bixu27_wayA_upd(0) <= p1_way_data_upd27_wayA and p1_wren_q; +rel_bixu27_wayA_upd(1) <= p0_way_data_upd27_wayA and p0_wren_q; +p0_way_data_upd27_wayB <= p0_congr_cl27_act_q and binv_wayB_upd3_q; +p1_way_data_upd27_wayB <= p1_congr_cl27_act_q and reload_wayB_upd3_q; +rel_bixu27_wayB_upd(0) <= p1_way_data_upd27_wayB and p1_wren_q; +rel_bixu27_wayB_upd(1) <= p0_way_data_upd27_wayB and p0_wren_q; +p0_way_data_upd27_wayC <= p0_congr_cl27_act_q and binv_wayC_upd3_q; +p1_way_data_upd27_wayC <= p1_congr_cl27_act_q and reload_wayC_upd3_q; +rel_bixu27_wayC_upd(0) <= p1_way_data_upd27_wayC and p1_wren_q; +rel_bixu27_wayC_upd(1) <= p0_way_data_upd27_wayC and p0_wren_q; +p0_way_data_upd27_wayD <= p0_congr_cl27_act_q and binv_wayD_upd3_q; +p1_way_data_upd27_wayD <= p1_congr_cl27_act_q and reload_wayD_upd3_q; +rel_bixu27_wayD_upd(0) <= p1_way_data_upd27_wayD and p1_wren_q; +rel_bixu27_wayD_upd(1) <= p0_way_data_upd27_wayD and p0_wren_q; +p0_way_data_upd27_wayE <= p0_congr_cl27_act_q and binv_wayE_upd3_q; +p1_way_data_upd27_wayE <= p1_congr_cl27_act_q and reload_wayE_upd3_q; +rel_bixu27_wayE_upd(0) <= p1_way_data_upd27_wayE and p1_wren_q; +rel_bixu27_wayE_upd(1) <= p0_way_data_upd27_wayE and p0_wren_q; +p0_way_data_upd27_wayF <= p0_congr_cl27_act_q and binv_wayF_upd3_q; +p1_way_data_upd27_wayF <= p1_congr_cl27_act_q and reload_wayF_upd3_q; +rel_bixu27_wayF_upd(0) <= p1_way_data_upd27_wayF and p1_wren_q; +rel_bixu27_wayF_upd(1) <= p0_way_data_upd27_wayF and p0_wren_q; +p0_way_data_upd27_wayG <= p0_congr_cl27_act_q and binv_wayG_upd3_q; +p1_way_data_upd27_wayG <= p1_congr_cl27_act_q and reload_wayG_upd3_q; +rel_bixu27_wayG_upd(0) <= p1_way_data_upd27_wayG and p1_wren_q; +rel_bixu27_wayG_upd(1) <= p0_way_data_upd27_wayG and p0_wren_q; +p0_way_data_upd27_wayH <= p0_congr_cl27_act_q and binv_wayH_upd3_q; +p1_way_data_upd27_wayH <= p1_congr_cl27_act_q and reload_wayH_upd3_q; +rel_bixu27_wayH_upd(0) <= p1_way_data_upd27_wayH and p1_wren_q; +rel_bixu27_wayH_upd(1) <= p0_way_data_upd27_wayH and p0_wren_q; +p0_congr_cl28_m <= (ex5_congr_cl_q = tconv(28,6)); +p1_congr_cl28_m <= (relu_s_congr_cl_q = tconv(28,6)); +p0_congr_cl28_act_d <= p0_congr_cl28_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl28_act_d <= p1_congr_cl28_m and rel_port_wren_q; +congr_cl28_act <= p0_congr_cl28_act_q or p1_congr_cl28_act_q or congr_cl_all_act_q; +p0_way_data_upd28_wayA <= p0_congr_cl28_act_q and binv_wayA_upd3_q; +p1_way_data_upd28_wayA <= p1_congr_cl28_act_q and reload_wayA_upd3_q; +rel_bixu28_wayA_upd(0) <= p1_way_data_upd28_wayA and p1_wren_q; +rel_bixu28_wayA_upd(1) <= p0_way_data_upd28_wayA and p0_wren_q; +p0_way_data_upd28_wayB <= p0_congr_cl28_act_q and binv_wayB_upd3_q; +p1_way_data_upd28_wayB <= p1_congr_cl28_act_q and reload_wayB_upd3_q; +rel_bixu28_wayB_upd(0) <= p1_way_data_upd28_wayB and p1_wren_q; +rel_bixu28_wayB_upd(1) <= p0_way_data_upd28_wayB and p0_wren_q; +p0_way_data_upd28_wayC <= p0_congr_cl28_act_q and binv_wayC_upd3_q; +p1_way_data_upd28_wayC <= p1_congr_cl28_act_q and reload_wayC_upd3_q; +rel_bixu28_wayC_upd(0) <= p1_way_data_upd28_wayC and p1_wren_q; +rel_bixu28_wayC_upd(1) <= p0_way_data_upd28_wayC and p0_wren_q; +p0_way_data_upd28_wayD <= p0_congr_cl28_act_q and binv_wayD_upd3_q; +p1_way_data_upd28_wayD <= p1_congr_cl28_act_q and reload_wayD_upd3_q; +rel_bixu28_wayD_upd(0) <= p1_way_data_upd28_wayD and p1_wren_q; +rel_bixu28_wayD_upd(1) <= p0_way_data_upd28_wayD and p0_wren_q; +p0_way_data_upd28_wayE <= p0_congr_cl28_act_q and binv_wayE_upd3_q; +p1_way_data_upd28_wayE <= p1_congr_cl28_act_q and reload_wayE_upd3_q; +rel_bixu28_wayE_upd(0) <= p1_way_data_upd28_wayE and p1_wren_q; +rel_bixu28_wayE_upd(1) <= p0_way_data_upd28_wayE and p0_wren_q; +p0_way_data_upd28_wayF <= p0_congr_cl28_act_q and binv_wayF_upd3_q; +p1_way_data_upd28_wayF <= p1_congr_cl28_act_q and reload_wayF_upd3_q; +rel_bixu28_wayF_upd(0) <= p1_way_data_upd28_wayF and p1_wren_q; +rel_bixu28_wayF_upd(1) <= p0_way_data_upd28_wayF and p0_wren_q; +p0_way_data_upd28_wayG <= p0_congr_cl28_act_q and binv_wayG_upd3_q; +p1_way_data_upd28_wayG <= p1_congr_cl28_act_q and reload_wayG_upd3_q; +rel_bixu28_wayG_upd(0) <= p1_way_data_upd28_wayG and p1_wren_q; +rel_bixu28_wayG_upd(1) <= p0_way_data_upd28_wayG and p0_wren_q; +p0_way_data_upd28_wayH <= p0_congr_cl28_act_q and binv_wayH_upd3_q; +p1_way_data_upd28_wayH <= p1_congr_cl28_act_q and reload_wayH_upd3_q; +rel_bixu28_wayH_upd(0) <= p1_way_data_upd28_wayH and p1_wren_q; +rel_bixu28_wayH_upd(1) <= p0_way_data_upd28_wayH and p0_wren_q; +p0_congr_cl29_m <= (ex5_congr_cl_q = tconv(29,6)); +p1_congr_cl29_m <= (relu_s_congr_cl_q = tconv(29,6)); +p0_congr_cl29_act_d <= p0_congr_cl29_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl29_act_d <= p1_congr_cl29_m and rel_port_wren_q; +congr_cl29_act <= p0_congr_cl29_act_q or p1_congr_cl29_act_q or congr_cl_all_act_q; +p0_way_data_upd29_wayA <= p0_congr_cl29_act_q and binv_wayA_upd3_q; +p1_way_data_upd29_wayA <= p1_congr_cl29_act_q and reload_wayA_upd3_q; +rel_bixu29_wayA_upd(0) <= p1_way_data_upd29_wayA and p1_wren_q; +rel_bixu29_wayA_upd(1) <= p0_way_data_upd29_wayA and p0_wren_q; +p0_way_data_upd29_wayB <= p0_congr_cl29_act_q and binv_wayB_upd3_q; +p1_way_data_upd29_wayB <= p1_congr_cl29_act_q and reload_wayB_upd3_q; +rel_bixu29_wayB_upd(0) <= p1_way_data_upd29_wayB and p1_wren_q; +rel_bixu29_wayB_upd(1) <= p0_way_data_upd29_wayB and p0_wren_q; +p0_way_data_upd29_wayC <= p0_congr_cl29_act_q and binv_wayC_upd3_q; +p1_way_data_upd29_wayC <= p1_congr_cl29_act_q and reload_wayC_upd3_q; +rel_bixu29_wayC_upd(0) <= p1_way_data_upd29_wayC and p1_wren_q; +rel_bixu29_wayC_upd(1) <= p0_way_data_upd29_wayC and p0_wren_q; +p0_way_data_upd29_wayD <= p0_congr_cl29_act_q and binv_wayD_upd3_q; +p1_way_data_upd29_wayD <= p1_congr_cl29_act_q and reload_wayD_upd3_q; +rel_bixu29_wayD_upd(0) <= p1_way_data_upd29_wayD and p1_wren_q; +rel_bixu29_wayD_upd(1) <= p0_way_data_upd29_wayD and p0_wren_q; +p0_way_data_upd29_wayE <= p0_congr_cl29_act_q and binv_wayE_upd3_q; +p1_way_data_upd29_wayE <= p1_congr_cl29_act_q and reload_wayE_upd3_q; +rel_bixu29_wayE_upd(0) <= p1_way_data_upd29_wayE and p1_wren_q; +rel_bixu29_wayE_upd(1) <= p0_way_data_upd29_wayE and p0_wren_q; +p0_way_data_upd29_wayF <= p0_congr_cl29_act_q and binv_wayF_upd3_q; +p1_way_data_upd29_wayF <= p1_congr_cl29_act_q and reload_wayF_upd3_q; +rel_bixu29_wayF_upd(0) <= p1_way_data_upd29_wayF and p1_wren_q; +rel_bixu29_wayF_upd(1) <= p0_way_data_upd29_wayF and p0_wren_q; +p0_way_data_upd29_wayG <= p0_congr_cl29_act_q and binv_wayG_upd3_q; +p1_way_data_upd29_wayG <= p1_congr_cl29_act_q and reload_wayG_upd3_q; +rel_bixu29_wayG_upd(0) <= p1_way_data_upd29_wayG and p1_wren_q; +rel_bixu29_wayG_upd(1) <= p0_way_data_upd29_wayG and p0_wren_q; +p0_way_data_upd29_wayH <= p0_congr_cl29_act_q and binv_wayH_upd3_q; +p1_way_data_upd29_wayH <= p1_congr_cl29_act_q and reload_wayH_upd3_q; +rel_bixu29_wayH_upd(0) <= p1_way_data_upd29_wayH and p1_wren_q; +rel_bixu29_wayH_upd(1) <= p0_way_data_upd29_wayH and p0_wren_q; +p0_congr_cl30_m <= (ex5_congr_cl_q = tconv(30,6)); +p1_congr_cl30_m <= (relu_s_congr_cl_q = tconv(30,6)); +p0_congr_cl30_act_d <= p0_congr_cl30_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl30_act_d <= p1_congr_cl30_m and rel_port_wren_q; +congr_cl30_act <= p0_congr_cl30_act_q or p1_congr_cl30_act_q or congr_cl_all_act_q; +p0_way_data_upd30_wayA <= p0_congr_cl30_act_q and binv_wayA_upd3_q; +p1_way_data_upd30_wayA <= p1_congr_cl30_act_q and reload_wayA_upd3_q; +rel_bixu30_wayA_upd(0) <= p1_way_data_upd30_wayA and p1_wren_q; +rel_bixu30_wayA_upd(1) <= p0_way_data_upd30_wayA and p0_wren_q; +p0_way_data_upd30_wayB <= p0_congr_cl30_act_q and binv_wayB_upd3_q; +p1_way_data_upd30_wayB <= p1_congr_cl30_act_q and reload_wayB_upd3_q; +rel_bixu30_wayB_upd(0) <= p1_way_data_upd30_wayB and p1_wren_q; +rel_bixu30_wayB_upd(1) <= p0_way_data_upd30_wayB and p0_wren_q; +p0_way_data_upd30_wayC <= p0_congr_cl30_act_q and binv_wayC_upd3_q; +p1_way_data_upd30_wayC <= p1_congr_cl30_act_q and reload_wayC_upd3_q; +rel_bixu30_wayC_upd(0) <= p1_way_data_upd30_wayC and p1_wren_q; +rel_bixu30_wayC_upd(1) <= p0_way_data_upd30_wayC and p0_wren_q; +p0_way_data_upd30_wayD <= p0_congr_cl30_act_q and binv_wayD_upd3_q; +p1_way_data_upd30_wayD <= p1_congr_cl30_act_q and reload_wayD_upd3_q; +rel_bixu30_wayD_upd(0) <= p1_way_data_upd30_wayD and p1_wren_q; +rel_bixu30_wayD_upd(1) <= p0_way_data_upd30_wayD and p0_wren_q; +p0_way_data_upd30_wayE <= p0_congr_cl30_act_q and binv_wayE_upd3_q; +p1_way_data_upd30_wayE <= p1_congr_cl30_act_q and reload_wayE_upd3_q; +rel_bixu30_wayE_upd(0) <= p1_way_data_upd30_wayE and p1_wren_q; +rel_bixu30_wayE_upd(1) <= p0_way_data_upd30_wayE and p0_wren_q; +p0_way_data_upd30_wayF <= p0_congr_cl30_act_q and binv_wayF_upd3_q; +p1_way_data_upd30_wayF <= p1_congr_cl30_act_q and reload_wayF_upd3_q; +rel_bixu30_wayF_upd(0) <= p1_way_data_upd30_wayF and p1_wren_q; +rel_bixu30_wayF_upd(1) <= p0_way_data_upd30_wayF and p0_wren_q; +p0_way_data_upd30_wayG <= p0_congr_cl30_act_q and binv_wayG_upd3_q; +p1_way_data_upd30_wayG <= p1_congr_cl30_act_q and reload_wayG_upd3_q; +rel_bixu30_wayG_upd(0) <= p1_way_data_upd30_wayG and p1_wren_q; +rel_bixu30_wayG_upd(1) <= p0_way_data_upd30_wayG and p0_wren_q; +p0_way_data_upd30_wayH <= p0_congr_cl30_act_q and binv_wayH_upd3_q; +p1_way_data_upd30_wayH <= p1_congr_cl30_act_q and reload_wayH_upd3_q; +rel_bixu30_wayH_upd(0) <= p1_way_data_upd30_wayH and p1_wren_q; +rel_bixu30_wayH_upd(1) <= p0_way_data_upd30_wayH and p0_wren_q; +p0_congr_cl31_m <= (ex5_congr_cl_q = tconv(31,6)); +p1_congr_cl31_m <= (relu_s_congr_cl_q = tconv(31,6)); +p0_congr_cl31_act_d <= p0_congr_cl31_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl31_act_d <= p1_congr_cl31_m and rel_port_wren_q; +congr_cl31_act <= p0_congr_cl31_act_q or p1_congr_cl31_act_q or congr_cl_all_act_q; +p0_way_data_upd31_wayA <= p0_congr_cl31_act_q and binv_wayA_upd3_q; +p1_way_data_upd31_wayA <= p1_congr_cl31_act_q and reload_wayA_upd3_q; +rel_bixu31_wayA_upd(0) <= p1_way_data_upd31_wayA and p1_wren_q; +rel_bixu31_wayA_upd(1) <= p0_way_data_upd31_wayA and p0_wren_q; +p0_way_data_upd31_wayB <= p0_congr_cl31_act_q and binv_wayB_upd3_q; +p1_way_data_upd31_wayB <= p1_congr_cl31_act_q and reload_wayB_upd3_q; +rel_bixu31_wayB_upd(0) <= p1_way_data_upd31_wayB and p1_wren_q; +rel_bixu31_wayB_upd(1) <= p0_way_data_upd31_wayB and p0_wren_q; +p0_way_data_upd31_wayC <= p0_congr_cl31_act_q and binv_wayC_upd3_q; +p1_way_data_upd31_wayC <= p1_congr_cl31_act_q and reload_wayC_upd3_q; +rel_bixu31_wayC_upd(0) <= p1_way_data_upd31_wayC and p1_wren_q; +rel_bixu31_wayC_upd(1) <= p0_way_data_upd31_wayC and p0_wren_q; +p0_way_data_upd31_wayD <= p0_congr_cl31_act_q and binv_wayD_upd3_q; +p1_way_data_upd31_wayD <= p1_congr_cl31_act_q and reload_wayD_upd3_q; +rel_bixu31_wayD_upd(0) <= p1_way_data_upd31_wayD and p1_wren_q; +rel_bixu31_wayD_upd(1) <= p0_way_data_upd31_wayD and p0_wren_q; +p0_way_data_upd31_wayE <= p0_congr_cl31_act_q and binv_wayE_upd3_q; +p1_way_data_upd31_wayE <= p1_congr_cl31_act_q and reload_wayE_upd3_q; +rel_bixu31_wayE_upd(0) <= p1_way_data_upd31_wayE and p1_wren_q; +rel_bixu31_wayE_upd(1) <= p0_way_data_upd31_wayE and p0_wren_q; +p0_way_data_upd31_wayF <= p0_congr_cl31_act_q and binv_wayF_upd3_q; +p1_way_data_upd31_wayF <= p1_congr_cl31_act_q and reload_wayF_upd3_q; +rel_bixu31_wayF_upd(0) <= p1_way_data_upd31_wayF and p1_wren_q; +rel_bixu31_wayF_upd(1) <= p0_way_data_upd31_wayF and p0_wren_q; +p0_way_data_upd31_wayG <= p0_congr_cl31_act_q and binv_wayG_upd3_q; +p1_way_data_upd31_wayG <= p1_congr_cl31_act_q and reload_wayG_upd3_q; +rel_bixu31_wayG_upd(0) <= p1_way_data_upd31_wayG and p1_wren_q; +rel_bixu31_wayG_upd(1) <= p0_way_data_upd31_wayG and p0_wren_q; +p0_way_data_upd31_wayH <= p0_congr_cl31_act_q and binv_wayH_upd3_q; +p1_way_data_upd31_wayH <= p1_congr_cl31_act_q and reload_wayH_upd3_q; +rel_bixu31_wayH_upd(0) <= p1_way_data_upd31_wayH and p1_wren_q; +rel_bixu31_wayH_upd(1) <= p0_way_data_upd31_wayH and p0_wren_q; +p0_congr_cl32_m <= (ex5_congr_cl_q = tconv(32,6)); +p1_congr_cl32_m <= (relu_s_congr_cl_q = tconv(32,6)); +p0_congr_cl32_act_d <= p0_congr_cl32_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl32_act_d <= p1_congr_cl32_m and rel_port_wren_q; +congr_cl32_act <= p0_congr_cl32_act_q or p1_congr_cl32_act_q or congr_cl_all_act_q; +p0_way_data_upd32_wayA <= p0_congr_cl32_act_q and binv_wayA_upd3_q; +p1_way_data_upd32_wayA <= p1_congr_cl32_act_q and reload_wayA_upd3_q; +rel_bixu32_wayA_upd(0) <= p1_way_data_upd32_wayA and p1_wren_q; +rel_bixu32_wayA_upd(1) <= p0_way_data_upd32_wayA and p0_wren_q; +p0_way_data_upd32_wayB <= p0_congr_cl32_act_q and binv_wayB_upd3_q; +p1_way_data_upd32_wayB <= p1_congr_cl32_act_q and reload_wayB_upd3_q; +rel_bixu32_wayB_upd(0) <= p1_way_data_upd32_wayB and p1_wren_q; +rel_bixu32_wayB_upd(1) <= p0_way_data_upd32_wayB and p0_wren_q; +p0_way_data_upd32_wayC <= p0_congr_cl32_act_q and binv_wayC_upd3_q; +p1_way_data_upd32_wayC <= p1_congr_cl32_act_q and reload_wayC_upd3_q; +rel_bixu32_wayC_upd(0) <= p1_way_data_upd32_wayC and p1_wren_q; +rel_bixu32_wayC_upd(1) <= p0_way_data_upd32_wayC and p0_wren_q; +p0_way_data_upd32_wayD <= p0_congr_cl32_act_q and binv_wayD_upd3_q; +p1_way_data_upd32_wayD <= p1_congr_cl32_act_q and reload_wayD_upd3_q; +rel_bixu32_wayD_upd(0) <= p1_way_data_upd32_wayD and p1_wren_q; +rel_bixu32_wayD_upd(1) <= p0_way_data_upd32_wayD and p0_wren_q; +p0_way_data_upd32_wayE <= p0_congr_cl32_act_q and binv_wayE_upd3_q; +p1_way_data_upd32_wayE <= p1_congr_cl32_act_q and reload_wayE_upd3_q; +rel_bixu32_wayE_upd(0) <= p1_way_data_upd32_wayE and p1_wren_q; +rel_bixu32_wayE_upd(1) <= p0_way_data_upd32_wayE and p0_wren_q; +p0_way_data_upd32_wayF <= p0_congr_cl32_act_q and binv_wayF_upd3_q; +p1_way_data_upd32_wayF <= p1_congr_cl32_act_q and reload_wayF_upd3_q; +rel_bixu32_wayF_upd(0) <= p1_way_data_upd32_wayF and p1_wren_q; +rel_bixu32_wayF_upd(1) <= p0_way_data_upd32_wayF and p0_wren_q; +p0_way_data_upd32_wayG <= p0_congr_cl32_act_q and binv_wayG_upd3_q; +p1_way_data_upd32_wayG <= p1_congr_cl32_act_q and reload_wayG_upd3_q; +rel_bixu32_wayG_upd(0) <= p1_way_data_upd32_wayG and p1_wren_q; +rel_bixu32_wayG_upd(1) <= p0_way_data_upd32_wayG and p0_wren_q; +p0_way_data_upd32_wayH <= p0_congr_cl32_act_q and binv_wayH_upd3_q; +p1_way_data_upd32_wayH <= p1_congr_cl32_act_q and reload_wayH_upd3_q; +rel_bixu32_wayH_upd(0) <= p1_way_data_upd32_wayH and p1_wren_q; +rel_bixu32_wayH_upd(1) <= p0_way_data_upd32_wayH and p0_wren_q; +p0_congr_cl33_m <= (ex5_congr_cl_q = tconv(33,6)); +p1_congr_cl33_m <= (relu_s_congr_cl_q = tconv(33,6)); +p0_congr_cl33_act_d <= p0_congr_cl33_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl33_act_d <= p1_congr_cl33_m and rel_port_wren_q; +congr_cl33_act <= p0_congr_cl33_act_q or p1_congr_cl33_act_q or congr_cl_all_act_q; +p0_way_data_upd33_wayA <= p0_congr_cl33_act_q and binv_wayA_upd3_q; +p1_way_data_upd33_wayA <= p1_congr_cl33_act_q and reload_wayA_upd3_q; +rel_bixu33_wayA_upd(0) <= p1_way_data_upd33_wayA and p1_wren_q; +rel_bixu33_wayA_upd(1) <= p0_way_data_upd33_wayA and p0_wren_q; +p0_way_data_upd33_wayB <= p0_congr_cl33_act_q and binv_wayB_upd3_q; +p1_way_data_upd33_wayB <= p1_congr_cl33_act_q and reload_wayB_upd3_q; +rel_bixu33_wayB_upd(0) <= p1_way_data_upd33_wayB and p1_wren_q; +rel_bixu33_wayB_upd(1) <= p0_way_data_upd33_wayB and p0_wren_q; +p0_way_data_upd33_wayC <= p0_congr_cl33_act_q and binv_wayC_upd3_q; +p1_way_data_upd33_wayC <= p1_congr_cl33_act_q and reload_wayC_upd3_q; +rel_bixu33_wayC_upd(0) <= p1_way_data_upd33_wayC and p1_wren_q; +rel_bixu33_wayC_upd(1) <= p0_way_data_upd33_wayC and p0_wren_q; +p0_way_data_upd33_wayD <= p0_congr_cl33_act_q and binv_wayD_upd3_q; +p1_way_data_upd33_wayD <= p1_congr_cl33_act_q and reload_wayD_upd3_q; +rel_bixu33_wayD_upd(0) <= p1_way_data_upd33_wayD and p1_wren_q; +rel_bixu33_wayD_upd(1) <= p0_way_data_upd33_wayD and p0_wren_q; +p0_way_data_upd33_wayE <= p0_congr_cl33_act_q and binv_wayE_upd3_q; +p1_way_data_upd33_wayE <= p1_congr_cl33_act_q and reload_wayE_upd3_q; +rel_bixu33_wayE_upd(0) <= p1_way_data_upd33_wayE and p1_wren_q; +rel_bixu33_wayE_upd(1) <= p0_way_data_upd33_wayE and p0_wren_q; +p0_way_data_upd33_wayF <= p0_congr_cl33_act_q and binv_wayF_upd3_q; +p1_way_data_upd33_wayF <= p1_congr_cl33_act_q and reload_wayF_upd3_q; +rel_bixu33_wayF_upd(0) <= p1_way_data_upd33_wayF and p1_wren_q; +rel_bixu33_wayF_upd(1) <= p0_way_data_upd33_wayF and p0_wren_q; +p0_way_data_upd33_wayG <= p0_congr_cl33_act_q and binv_wayG_upd3_q; +p1_way_data_upd33_wayG <= p1_congr_cl33_act_q and reload_wayG_upd3_q; +rel_bixu33_wayG_upd(0) <= p1_way_data_upd33_wayG and p1_wren_q; +rel_bixu33_wayG_upd(1) <= p0_way_data_upd33_wayG and p0_wren_q; +p0_way_data_upd33_wayH <= p0_congr_cl33_act_q and binv_wayH_upd3_q; +p1_way_data_upd33_wayH <= p1_congr_cl33_act_q and reload_wayH_upd3_q; +rel_bixu33_wayH_upd(0) <= p1_way_data_upd33_wayH and p1_wren_q; +rel_bixu33_wayH_upd(1) <= p0_way_data_upd33_wayH and p0_wren_q; +p0_congr_cl34_m <= (ex5_congr_cl_q = tconv(34,6)); +p1_congr_cl34_m <= (relu_s_congr_cl_q = tconv(34,6)); +p0_congr_cl34_act_d <= p0_congr_cl34_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl34_act_d <= p1_congr_cl34_m and rel_port_wren_q; +congr_cl34_act <= p0_congr_cl34_act_q or p1_congr_cl34_act_q or congr_cl_all_act_q; +p0_way_data_upd34_wayA <= p0_congr_cl34_act_q and binv_wayA_upd3_q; +p1_way_data_upd34_wayA <= p1_congr_cl34_act_q and reload_wayA_upd3_q; +rel_bixu34_wayA_upd(0) <= p1_way_data_upd34_wayA and p1_wren_q; +rel_bixu34_wayA_upd(1) <= p0_way_data_upd34_wayA and p0_wren_q; +p0_way_data_upd34_wayB <= p0_congr_cl34_act_q and binv_wayB_upd3_q; +p1_way_data_upd34_wayB <= p1_congr_cl34_act_q and reload_wayB_upd3_q; +rel_bixu34_wayB_upd(0) <= p1_way_data_upd34_wayB and p1_wren_q; +rel_bixu34_wayB_upd(1) <= p0_way_data_upd34_wayB and p0_wren_q; +p0_way_data_upd34_wayC <= p0_congr_cl34_act_q and binv_wayC_upd3_q; +p1_way_data_upd34_wayC <= p1_congr_cl34_act_q and reload_wayC_upd3_q; +rel_bixu34_wayC_upd(0) <= p1_way_data_upd34_wayC and p1_wren_q; +rel_bixu34_wayC_upd(1) <= p0_way_data_upd34_wayC and p0_wren_q; +p0_way_data_upd34_wayD <= p0_congr_cl34_act_q and binv_wayD_upd3_q; +p1_way_data_upd34_wayD <= p1_congr_cl34_act_q and reload_wayD_upd3_q; +rel_bixu34_wayD_upd(0) <= p1_way_data_upd34_wayD and p1_wren_q; +rel_bixu34_wayD_upd(1) <= p0_way_data_upd34_wayD and p0_wren_q; +p0_way_data_upd34_wayE <= p0_congr_cl34_act_q and binv_wayE_upd3_q; +p1_way_data_upd34_wayE <= p1_congr_cl34_act_q and reload_wayE_upd3_q; +rel_bixu34_wayE_upd(0) <= p1_way_data_upd34_wayE and p1_wren_q; +rel_bixu34_wayE_upd(1) <= p0_way_data_upd34_wayE and p0_wren_q; +p0_way_data_upd34_wayF <= p0_congr_cl34_act_q and binv_wayF_upd3_q; +p1_way_data_upd34_wayF <= p1_congr_cl34_act_q and reload_wayF_upd3_q; +rel_bixu34_wayF_upd(0) <= p1_way_data_upd34_wayF and p1_wren_q; +rel_bixu34_wayF_upd(1) <= p0_way_data_upd34_wayF and p0_wren_q; +p0_way_data_upd34_wayG <= p0_congr_cl34_act_q and binv_wayG_upd3_q; +p1_way_data_upd34_wayG <= p1_congr_cl34_act_q and reload_wayG_upd3_q; +rel_bixu34_wayG_upd(0) <= p1_way_data_upd34_wayG and p1_wren_q; +rel_bixu34_wayG_upd(1) <= p0_way_data_upd34_wayG and p0_wren_q; +p0_way_data_upd34_wayH <= p0_congr_cl34_act_q and binv_wayH_upd3_q; +p1_way_data_upd34_wayH <= p1_congr_cl34_act_q and reload_wayH_upd3_q; +rel_bixu34_wayH_upd(0) <= p1_way_data_upd34_wayH and p1_wren_q; +rel_bixu34_wayH_upd(1) <= p0_way_data_upd34_wayH and p0_wren_q; +p0_congr_cl35_m <= (ex5_congr_cl_q = tconv(35,6)); +p1_congr_cl35_m <= (relu_s_congr_cl_q = tconv(35,6)); +p0_congr_cl35_act_d <= p0_congr_cl35_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl35_act_d <= p1_congr_cl35_m and rel_port_wren_q; +congr_cl35_act <= p0_congr_cl35_act_q or p1_congr_cl35_act_q or congr_cl_all_act_q; +p0_way_data_upd35_wayA <= p0_congr_cl35_act_q and binv_wayA_upd3_q; +p1_way_data_upd35_wayA <= p1_congr_cl35_act_q and reload_wayA_upd3_q; +rel_bixu35_wayA_upd(0) <= p1_way_data_upd35_wayA and p1_wren_q; +rel_bixu35_wayA_upd(1) <= p0_way_data_upd35_wayA and p0_wren_q; +p0_way_data_upd35_wayB <= p0_congr_cl35_act_q and binv_wayB_upd3_q; +p1_way_data_upd35_wayB <= p1_congr_cl35_act_q and reload_wayB_upd3_q; +rel_bixu35_wayB_upd(0) <= p1_way_data_upd35_wayB and p1_wren_q; +rel_bixu35_wayB_upd(1) <= p0_way_data_upd35_wayB and p0_wren_q; +p0_way_data_upd35_wayC <= p0_congr_cl35_act_q and binv_wayC_upd3_q; +p1_way_data_upd35_wayC <= p1_congr_cl35_act_q and reload_wayC_upd3_q; +rel_bixu35_wayC_upd(0) <= p1_way_data_upd35_wayC and p1_wren_q; +rel_bixu35_wayC_upd(1) <= p0_way_data_upd35_wayC and p0_wren_q; +p0_way_data_upd35_wayD <= p0_congr_cl35_act_q and binv_wayD_upd3_q; +p1_way_data_upd35_wayD <= p1_congr_cl35_act_q and reload_wayD_upd3_q; +rel_bixu35_wayD_upd(0) <= p1_way_data_upd35_wayD and p1_wren_q; +rel_bixu35_wayD_upd(1) <= p0_way_data_upd35_wayD and p0_wren_q; +p0_way_data_upd35_wayE <= p0_congr_cl35_act_q and binv_wayE_upd3_q; +p1_way_data_upd35_wayE <= p1_congr_cl35_act_q and reload_wayE_upd3_q; +rel_bixu35_wayE_upd(0) <= p1_way_data_upd35_wayE and p1_wren_q; +rel_bixu35_wayE_upd(1) <= p0_way_data_upd35_wayE and p0_wren_q; +p0_way_data_upd35_wayF <= p0_congr_cl35_act_q and binv_wayF_upd3_q; +p1_way_data_upd35_wayF <= p1_congr_cl35_act_q and reload_wayF_upd3_q; +rel_bixu35_wayF_upd(0) <= p1_way_data_upd35_wayF and p1_wren_q; +rel_bixu35_wayF_upd(1) <= p0_way_data_upd35_wayF and p0_wren_q; +p0_way_data_upd35_wayG <= p0_congr_cl35_act_q and binv_wayG_upd3_q; +p1_way_data_upd35_wayG <= p1_congr_cl35_act_q and reload_wayG_upd3_q; +rel_bixu35_wayG_upd(0) <= p1_way_data_upd35_wayG and p1_wren_q; +rel_bixu35_wayG_upd(1) <= p0_way_data_upd35_wayG and p0_wren_q; +p0_way_data_upd35_wayH <= p0_congr_cl35_act_q and binv_wayH_upd3_q; +p1_way_data_upd35_wayH <= p1_congr_cl35_act_q and reload_wayH_upd3_q; +rel_bixu35_wayH_upd(0) <= p1_way_data_upd35_wayH and p1_wren_q; +rel_bixu35_wayH_upd(1) <= p0_way_data_upd35_wayH and p0_wren_q; +p0_congr_cl36_m <= (ex5_congr_cl_q = tconv(36,6)); +p1_congr_cl36_m <= (relu_s_congr_cl_q = tconv(36,6)); +p0_congr_cl36_act_d <= p0_congr_cl36_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl36_act_d <= p1_congr_cl36_m and rel_port_wren_q; +congr_cl36_act <= p0_congr_cl36_act_q or p1_congr_cl36_act_q or congr_cl_all_act_q; +p0_way_data_upd36_wayA <= p0_congr_cl36_act_q and binv_wayA_upd3_q; +p1_way_data_upd36_wayA <= p1_congr_cl36_act_q and reload_wayA_upd3_q; +rel_bixu36_wayA_upd(0) <= p1_way_data_upd36_wayA and p1_wren_q; +rel_bixu36_wayA_upd(1) <= p0_way_data_upd36_wayA and p0_wren_q; +p0_way_data_upd36_wayB <= p0_congr_cl36_act_q and binv_wayB_upd3_q; +p1_way_data_upd36_wayB <= p1_congr_cl36_act_q and reload_wayB_upd3_q; +rel_bixu36_wayB_upd(0) <= p1_way_data_upd36_wayB and p1_wren_q; +rel_bixu36_wayB_upd(1) <= p0_way_data_upd36_wayB and p0_wren_q; +p0_way_data_upd36_wayC <= p0_congr_cl36_act_q and binv_wayC_upd3_q; +p1_way_data_upd36_wayC <= p1_congr_cl36_act_q and reload_wayC_upd3_q; +rel_bixu36_wayC_upd(0) <= p1_way_data_upd36_wayC and p1_wren_q; +rel_bixu36_wayC_upd(1) <= p0_way_data_upd36_wayC and p0_wren_q; +p0_way_data_upd36_wayD <= p0_congr_cl36_act_q and binv_wayD_upd3_q; +p1_way_data_upd36_wayD <= p1_congr_cl36_act_q and reload_wayD_upd3_q; +rel_bixu36_wayD_upd(0) <= p1_way_data_upd36_wayD and p1_wren_q; +rel_bixu36_wayD_upd(1) <= p0_way_data_upd36_wayD and p0_wren_q; +p0_way_data_upd36_wayE <= p0_congr_cl36_act_q and binv_wayE_upd3_q; +p1_way_data_upd36_wayE <= p1_congr_cl36_act_q and reload_wayE_upd3_q; +rel_bixu36_wayE_upd(0) <= p1_way_data_upd36_wayE and p1_wren_q; +rel_bixu36_wayE_upd(1) <= p0_way_data_upd36_wayE and p0_wren_q; +p0_way_data_upd36_wayF <= p0_congr_cl36_act_q and binv_wayF_upd3_q; +p1_way_data_upd36_wayF <= p1_congr_cl36_act_q and reload_wayF_upd3_q; +rel_bixu36_wayF_upd(0) <= p1_way_data_upd36_wayF and p1_wren_q; +rel_bixu36_wayF_upd(1) <= p0_way_data_upd36_wayF and p0_wren_q; +p0_way_data_upd36_wayG <= p0_congr_cl36_act_q and binv_wayG_upd3_q; +p1_way_data_upd36_wayG <= p1_congr_cl36_act_q and reload_wayG_upd3_q; +rel_bixu36_wayG_upd(0) <= p1_way_data_upd36_wayG and p1_wren_q; +rel_bixu36_wayG_upd(1) <= p0_way_data_upd36_wayG and p0_wren_q; +p0_way_data_upd36_wayH <= p0_congr_cl36_act_q and binv_wayH_upd3_q; +p1_way_data_upd36_wayH <= p1_congr_cl36_act_q and reload_wayH_upd3_q; +rel_bixu36_wayH_upd(0) <= p1_way_data_upd36_wayH and p1_wren_q; +rel_bixu36_wayH_upd(1) <= p0_way_data_upd36_wayH and p0_wren_q; +p0_congr_cl37_m <= (ex5_congr_cl_q = tconv(37,6)); +p1_congr_cl37_m <= (relu_s_congr_cl_q = tconv(37,6)); +p0_congr_cl37_act_d <= p0_congr_cl37_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl37_act_d <= p1_congr_cl37_m and rel_port_wren_q; +congr_cl37_act <= p0_congr_cl37_act_q or p1_congr_cl37_act_q or congr_cl_all_act_q; +p0_way_data_upd37_wayA <= p0_congr_cl37_act_q and binv_wayA_upd3_q; +p1_way_data_upd37_wayA <= p1_congr_cl37_act_q and reload_wayA_upd3_q; +rel_bixu37_wayA_upd(0) <= p1_way_data_upd37_wayA and p1_wren_q; +rel_bixu37_wayA_upd(1) <= p0_way_data_upd37_wayA and p0_wren_q; +p0_way_data_upd37_wayB <= p0_congr_cl37_act_q and binv_wayB_upd3_q; +p1_way_data_upd37_wayB <= p1_congr_cl37_act_q and reload_wayB_upd3_q; +rel_bixu37_wayB_upd(0) <= p1_way_data_upd37_wayB and p1_wren_q; +rel_bixu37_wayB_upd(1) <= p0_way_data_upd37_wayB and p0_wren_q; +p0_way_data_upd37_wayC <= p0_congr_cl37_act_q and binv_wayC_upd3_q; +p1_way_data_upd37_wayC <= p1_congr_cl37_act_q and reload_wayC_upd3_q; +rel_bixu37_wayC_upd(0) <= p1_way_data_upd37_wayC and p1_wren_q; +rel_bixu37_wayC_upd(1) <= p0_way_data_upd37_wayC and p0_wren_q; +p0_way_data_upd37_wayD <= p0_congr_cl37_act_q and binv_wayD_upd3_q; +p1_way_data_upd37_wayD <= p1_congr_cl37_act_q and reload_wayD_upd3_q; +rel_bixu37_wayD_upd(0) <= p1_way_data_upd37_wayD and p1_wren_q; +rel_bixu37_wayD_upd(1) <= p0_way_data_upd37_wayD and p0_wren_q; +p0_way_data_upd37_wayE <= p0_congr_cl37_act_q and binv_wayE_upd3_q; +p1_way_data_upd37_wayE <= p1_congr_cl37_act_q and reload_wayE_upd3_q; +rel_bixu37_wayE_upd(0) <= p1_way_data_upd37_wayE and p1_wren_q; +rel_bixu37_wayE_upd(1) <= p0_way_data_upd37_wayE and p0_wren_q; +p0_way_data_upd37_wayF <= p0_congr_cl37_act_q and binv_wayF_upd3_q; +p1_way_data_upd37_wayF <= p1_congr_cl37_act_q and reload_wayF_upd3_q; +rel_bixu37_wayF_upd(0) <= p1_way_data_upd37_wayF and p1_wren_q; +rel_bixu37_wayF_upd(1) <= p0_way_data_upd37_wayF and p0_wren_q; +p0_way_data_upd37_wayG <= p0_congr_cl37_act_q and binv_wayG_upd3_q; +p1_way_data_upd37_wayG <= p1_congr_cl37_act_q and reload_wayG_upd3_q; +rel_bixu37_wayG_upd(0) <= p1_way_data_upd37_wayG and p1_wren_q; +rel_bixu37_wayG_upd(1) <= p0_way_data_upd37_wayG and p0_wren_q; +p0_way_data_upd37_wayH <= p0_congr_cl37_act_q and binv_wayH_upd3_q; +p1_way_data_upd37_wayH <= p1_congr_cl37_act_q and reload_wayH_upd3_q; +rel_bixu37_wayH_upd(0) <= p1_way_data_upd37_wayH and p1_wren_q; +rel_bixu37_wayH_upd(1) <= p0_way_data_upd37_wayH and p0_wren_q; +p0_congr_cl38_m <= (ex5_congr_cl_q = tconv(38,6)); +p1_congr_cl38_m <= (relu_s_congr_cl_q = tconv(38,6)); +p0_congr_cl38_act_d <= p0_congr_cl38_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl38_act_d <= p1_congr_cl38_m and rel_port_wren_q; +congr_cl38_act <= p0_congr_cl38_act_q or p1_congr_cl38_act_q or congr_cl_all_act_q; +p0_way_data_upd38_wayA <= p0_congr_cl38_act_q and binv_wayA_upd3_q; +p1_way_data_upd38_wayA <= p1_congr_cl38_act_q and reload_wayA_upd3_q; +rel_bixu38_wayA_upd(0) <= p1_way_data_upd38_wayA and p1_wren_q; +rel_bixu38_wayA_upd(1) <= p0_way_data_upd38_wayA and p0_wren_q; +p0_way_data_upd38_wayB <= p0_congr_cl38_act_q and binv_wayB_upd3_q; +p1_way_data_upd38_wayB <= p1_congr_cl38_act_q and reload_wayB_upd3_q; +rel_bixu38_wayB_upd(0) <= p1_way_data_upd38_wayB and p1_wren_q; +rel_bixu38_wayB_upd(1) <= p0_way_data_upd38_wayB and p0_wren_q; +p0_way_data_upd38_wayC <= p0_congr_cl38_act_q and binv_wayC_upd3_q; +p1_way_data_upd38_wayC <= p1_congr_cl38_act_q and reload_wayC_upd3_q; +rel_bixu38_wayC_upd(0) <= p1_way_data_upd38_wayC and p1_wren_q; +rel_bixu38_wayC_upd(1) <= p0_way_data_upd38_wayC and p0_wren_q; +p0_way_data_upd38_wayD <= p0_congr_cl38_act_q and binv_wayD_upd3_q; +p1_way_data_upd38_wayD <= p1_congr_cl38_act_q and reload_wayD_upd3_q; +rel_bixu38_wayD_upd(0) <= p1_way_data_upd38_wayD and p1_wren_q; +rel_bixu38_wayD_upd(1) <= p0_way_data_upd38_wayD and p0_wren_q; +p0_way_data_upd38_wayE <= p0_congr_cl38_act_q and binv_wayE_upd3_q; +p1_way_data_upd38_wayE <= p1_congr_cl38_act_q and reload_wayE_upd3_q; +rel_bixu38_wayE_upd(0) <= p1_way_data_upd38_wayE and p1_wren_q; +rel_bixu38_wayE_upd(1) <= p0_way_data_upd38_wayE and p0_wren_q; +p0_way_data_upd38_wayF <= p0_congr_cl38_act_q and binv_wayF_upd3_q; +p1_way_data_upd38_wayF <= p1_congr_cl38_act_q and reload_wayF_upd3_q; +rel_bixu38_wayF_upd(0) <= p1_way_data_upd38_wayF and p1_wren_q; +rel_bixu38_wayF_upd(1) <= p0_way_data_upd38_wayF and p0_wren_q; +p0_way_data_upd38_wayG <= p0_congr_cl38_act_q and binv_wayG_upd3_q; +p1_way_data_upd38_wayG <= p1_congr_cl38_act_q and reload_wayG_upd3_q; +rel_bixu38_wayG_upd(0) <= p1_way_data_upd38_wayG and p1_wren_q; +rel_bixu38_wayG_upd(1) <= p0_way_data_upd38_wayG and p0_wren_q; +p0_way_data_upd38_wayH <= p0_congr_cl38_act_q and binv_wayH_upd3_q; +p1_way_data_upd38_wayH <= p1_congr_cl38_act_q and reload_wayH_upd3_q; +rel_bixu38_wayH_upd(0) <= p1_way_data_upd38_wayH and p1_wren_q; +rel_bixu38_wayH_upd(1) <= p0_way_data_upd38_wayH and p0_wren_q; +p0_congr_cl39_m <= (ex5_congr_cl_q = tconv(39,6)); +p1_congr_cl39_m <= (relu_s_congr_cl_q = tconv(39,6)); +p0_congr_cl39_act_d <= p0_congr_cl39_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl39_act_d <= p1_congr_cl39_m and rel_port_wren_q; +congr_cl39_act <= p0_congr_cl39_act_q or p1_congr_cl39_act_q or congr_cl_all_act_q; +p0_way_data_upd39_wayA <= p0_congr_cl39_act_q and binv_wayA_upd3_q; +p1_way_data_upd39_wayA <= p1_congr_cl39_act_q and reload_wayA_upd3_q; +rel_bixu39_wayA_upd(0) <= p1_way_data_upd39_wayA and p1_wren_q; +rel_bixu39_wayA_upd(1) <= p0_way_data_upd39_wayA and p0_wren_q; +p0_way_data_upd39_wayB <= p0_congr_cl39_act_q and binv_wayB_upd3_q; +p1_way_data_upd39_wayB <= p1_congr_cl39_act_q and reload_wayB_upd3_q; +rel_bixu39_wayB_upd(0) <= p1_way_data_upd39_wayB and p1_wren_q; +rel_bixu39_wayB_upd(1) <= p0_way_data_upd39_wayB and p0_wren_q; +p0_way_data_upd39_wayC <= p0_congr_cl39_act_q and binv_wayC_upd3_q; +p1_way_data_upd39_wayC <= p1_congr_cl39_act_q and reload_wayC_upd3_q; +rel_bixu39_wayC_upd(0) <= p1_way_data_upd39_wayC and p1_wren_q; +rel_bixu39_wayC_upd(1) <= p0_way_data_upd39_wayC and p0_wren_q; +p0_way_data_upd39_wayD <= p0_congr_cl39_act_q and binv_wayD_upd3_q; +p1_way_data_upd39_wayD <= p1_congr_cl39_act_q and reload_wayD_upd3_q; +rel_bixu39_wayD_upd(0) <= p1_way_data_upd39_wayD and p1_wren_q; +rel_bixu39_wayD_upd(1) <= p0_way_data_upd39_wayD and p0_wren_q; +p0_way_data_upd39_wayE <= p0_congr_cl39_act_q and binv_wayE_upd3_q; +p1_way_data_upd39_wayE <= p1_congr_cl39_act_q and reload_wayE_upd3_q; +rel_bixu39_wayE_upd(0) <= p1_way_data_upd39_wayE and p1_wren_q; +rel_bixu39_wayE_upd(1) <= p0_way_data_upd39_wayE and p0_wren_q; +p0_way_data_upd39_wayF <= p0_congr_cl39_act_q and binv_wayF_upd3_q; +p1_way_data_upd39_wayF <= p1_congr_cl39_act_q and reload_wayF_upd3_q; +rel_bixu39_wayF_upd(0) <= p1_way_data_upd39_wayF and p1_wren_q; +rel_bixu39_wayF_upd(1) <= p0_way_data_upd39_wayF and p0_wren_q; +p0_way_data_upd39_wayG <= p0_congr_cl39_act_q and binv_wayG_upd3_q; +p1_way_data_upd39_wayG <= p1_congr_cl39_act_q and reload_wayG_upd3_q; +rel_bixu39_wayG_upd(0) <= p1_way_data_upd39_wayG and p1_wren_q; +rel_bixu39_wayG_upd(1) <= p0_way_data_upd39_wayG and p0_wren_q; +p0_way_data_upd39_wayH <= p0_congr_cl39_act_q and binv_wayH_upd3_q; +p1_way_data_upd39_wayH <= p1_congr_cl39_act_q and reload_wayH_upd3_q; +rel_bixu39_wayH_upd(0) <= p1_way_data_upd39_wayH and p1_wren_q; +rel_bixu39_wayH_upd(1) <= p0_way_data_upd39_wayH and p0_wren_q; +p0_congr_cl40_m <= (ex5_congr_cl_q = tconv(40,6)); +p1_congr_cl40_m <= (relu_s_congr_cl_q = tconv(40,6)); +p0_congr_cl40_act_d <= p0_congr_cl40_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl40_act_d <= p1_congr_cl40_m and rel_port_wren_q; +congr_cl40_act <= p0_congr_cl40_act_q or p1_congr_cl40_act_q or congr_cl_all_act_q; +p0_way_data_upd40_wayA <= p0_congr_cl40_act_q and binv_wayA_upd3_q; +p1_way_data_upd40_wayA <= p1_congr_cl40_act_q and reload_wayA_upd3_q; +rel_bixu40_wayA_upd(0) <= p1_way_data_upd40_wayA and p1_wren_q; +rel_bixu40_wayA_upd(1) <= p0_way_data_upd40_wayA and p0_wren_q; +p0_way_data_upd40_wayB <= p0_congr_cl40_act_q and binv_wayB_upd3_q; +p1_way_data_upd40_wayB <= p1_congr_cl40_act_q and reload_wayB_upd3_q; +rel_bixu40_wayB_upd(0) <= p1_way_data_upd40_wayB and p1_wren_q; +rel_bixu40_wayB_upd(1) <= p0_way_data_upd40_wayB and p0_wren_q; +p0_way_data_upd40_wayC <= p0_congr_cl40_act_q and binv_wayC_upd3_q; +p1_way_data_upd40_wayC <= p1_congr_cl40_act_q and reload_wayC_upd3_q; +rel_bixu40_wayC_upd(0) <= p1_way_data_upd40_wayC and p1_wren_q; +rel_bixu40_wayC_upd(1) <= p0_way_data_upd40_wayC and p0_wren_q; +p0_way_data_upd40_wayD <= p0_congr_cl40_act_q and binv_wayD_upd3_q; +p1_way_data_upd40_wayD <= p1_congr_cl40_act_q and reload_wayD_upd3_q; +rel_bixu40_wayD_upd(0) <= p1_way_data_upd40_wayD and p1_wren_q; +rel_bixu40_wayD_upd(1) <= p0_way_data_upd40_wayD and p0_wren_q; +p0_way_data_upd40_wayE <= p0_congr_cl40_act_q and binv_wayE_upd3_q; +p1_way_data_upd40_wayE <= p1_congr_cl40_act_q and reload_wayE_upd3_q; +rel_bixu40_wayE_upd(0) <= p1_way_data_upd40_wayE and p1_wren_q; +rel_bixu40_wayE_upd(1) <= p0_way_data_upd40_wayE and p0_wren_q; +p0_way_data_upd40_wayF <= p0_congr_cl40_act_q and binv_wayF_upd3_q; +p1_way_data_upd40_wayF <= p1_congr_cl40_act_q and reload_wayF_upd3_q; +rel_bixu40_wayF_upd(0) <= p1_way_data_upd40_wayF and p1_wren_q; +rel_bixu40_wayF_upd(1) <= p0_way_data_upd40_wayF and p0_wren_q; +p0_way_data_upd40_wayG <= p0_congr_cl40_act_q and binv_wayG_upd3_q; +p1_way_data_upd40_wayG <= p1_congr_cl40_act_q and reload_wayG_upd3_q; +rel_bixu40_wayG_upd(0) <= p1_way_data_upd40_wayG and p1_wren_q; +rel_bixu40_wayG_upd(1) <= p0_way_data_upd40_wayG and p0_wren_q; +p0_way_data_upd40_wayH <= p0_congr_cl40_act_q and binv_wayH_upd3_q; +p1_way_data_upd40_wayH <= p1_congr_cl40_act_q and reload_wayH_upd3_q; +rel_bixu40_wayH_upd(0) <= p1_way_data_upd40_wayH and p1_wren_q; +rel_bixu40_wayH_upd(1) <= p0_way_data_upd40_wayH and p0_wren_q; +p0_congr_cl41_m <= (ex5_congr_cl_q = tconv(41,6)); +p1_congr_cl41_m <= (relu_s_congr_cl_q = tconv(41,6)); +p0_congr_cl41_act_d <= p0_congr_cl41_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl41_act_d <= p1_congr_cl41_m and rel_port_wren_q; +congr_cl41_act <= p0_congr_cl41_act_q or p1_congr_cl41_act_q or congr_cl_all_act_q; +p0_way_data_upd41_wayA <= p0_congr_cl41_act_q and binv_wayA_upd3_q; +p1_way_data_upd41_wayA <= p1_congr_cl41_act_q and reload_wayA_upd3_q; +rel_bixu41_wayA_upd(0) <= p1_way_data_upd41_wayA and p1_wren_q; +rel_bixu41_wayA_upd(1) <= p0_way_data_upd41_wayA and p0_wren_q; +p0_way_data_upd41_wayB <= p0_congr_cl41_act_q and binv_wayB_upd3_q; +p1_way_data_upd41_wayB <= p1_congr_cl41_act_q and reload_wayB_upd3_q; +rel_bixu41_wayB_upd(0) <= p1_way_data_upd41_wayB and p1_wren_q; +rel_bixu41_wayB_upd(1) <= p0_way_data_upd41_wayB and p0_wren_q; +p0_way_data_upd41_wayC <= p0_congr_cl41_act_q and binv_wayC_upd3_q; +p1_way_data_upd41_wayC <= p1_congr_cl41_act_q and reload_wayC_upd3_q; +rel_bixu41_wayC_upd(0) <= p1_way_data_upd41_wayC and p1_wren_q; +rel_bixu41_wayC_upd(1) <= p0_way_data_upd41_wayC and p0_wren_q; +p0_way_data_upd41_wayD <= p0_congr_cl41_act_q and binv_wayD_upd3_q; +p1_way_data_upd41_wayD <= p1_congr_cl41_act_q and reload_wayD_upd3_q; +rel_bixu41_wayD_upd(0) <= p1_way_data_upd41_wayD and p1_wren_q; +rel_bixu41_wayD_upd(1) <= p0_way_data_upd41_wayD and p0_wren_q; +p0_way_data_upd41_wayE <= p0_congr_cl41_act_q and binv_wayE_upd3_q; +p1_way_data_upd41_wayE <= p1_congr_cl41_act_q and reload_wayE_upd3_q; +rel_bixu41_wayE_upd(0) <= p1_way_data_upd41_wayE and p1_wren_q; +rel_bixu41_wayE_upd(1) <= p0_way_data_upd41_wayE and p0_wren_q; +p0_way_data_upd41_wayF <= p0_congr_cl41_act_q and binv_wayF_upd3_q; +p1_way_data_upd41_wayF <= p1_congr_cl41_act_q and reload_wayF_upd3_q; +rel_bixu41_wayF_upd(0) <= p1_way_data_upd41_wayF and p1_wren_q; +rel_bixu41_wayF_upd(1) <= p0_way_data_upd41_wayF and p0_wren_q; +p0_way_data_upd41_wayG <= p0_congr_cl41_act_q and binv_wayG_upd3_q; +p1_way_data_upd41_wayG <= p1_congr_cl41_act_q and reload_wayG_upd3_q; +rel_bixu41_wayG_upd(0) <= p1_way_data_upd41_wayG and p1_wren_q; +rel_bixu41_wayG_upd(1) <= p0_way_data_upd41_wayG and p0_wren_q; +p0_way_data_upd41_wayH <= p0_congr_cl41_act_q and binv_wayH_upd3_q; +p1_way_data_upd41_wayH <= p1_congr_cl41_act_q and reload_wayH_upd3_q; +rel_bixu41_wayH_upd(0) <= p1_way_data_upd41_wayH and p1_wren_q; +rel_bixu41_wayH_upd(1) <= p0_way_data_upd41_wayH and p0_wren_q; +p0_congr_cl42_m <= (ex5_congr_cl_q = tconv(42,6)); +p1_congr_cl42_m <= (relu_s_congr_cl_q = tconv(42,6)); +p0_congr_cl42_act_d <= p0_congr_cl42_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl42_act_d <= p1_congr_cl42_m and rel_port_wren_q; +congr_cl42_act <= p0_congr_cl42_act_q or p1_congr_cl42_act_q or congr_cl_all_act_q; +p0_way_data_upd42_wayA <= p0_congr_cl42_act_q and binv_wayA_upd3_q; +p1_way_data_upd42_wayA <= p1_congr_cl42_act_q and reload_wayA_upd3_q; +rel_bixu42_wayA_upd(0) <= p1_way_data_upd42_wayA and p1_wren_q; +rel_bixu42_wayA_upd(1) <= p0_way_data_upd42_wayA and p0_wren_q; +p0_way_data_upd42_wayB <= p0_congr_cl42_act_q and binv_wayB_upd3_q; +p1_way_data_upd42_wayB <= p1_congr_cl42_act_q and reload_wayB_upd3_q; +rel_bixu42_wayB_upd(0) <= p1_way_data_upd42_wayB and p1_wren_q; +rel_bixu42_wayB_upd(1) <= p0_way_data_upd42_wayB and p0_wren_q; +p0_way_data_upd42_wayC <= p0_congr_cl42_act_q and binv_wayC_upd3_q; +p1_way_data_upd42_wayC <= p1_congr_cl42_act_q and reload_wayC_upd3_q; +rel_bixu42_wayC_upd(0) <= p1_way_data_upd42_wayC and p1_wren_q; +rel_bixu42_wayC_upd(1) <= p0_way_data_upd42_wayC and p0_wren_q; +p0_way_data_upd42_wayD <= p0_congr_cl42_act_q and binv_wayD_upd3_q; +p1_way_data_upd42_wayD <= p1_congr_cl42_act_q and reload_wayD_upd3_q; +rel_bixu42_wayD_upd(0) <= p1_way_data_upd42_wayD and p1_wren_q; +rel_bixu42_wayD_upd(1) <= p0_way_data_upd42_wayD and p0_wren_q; +p0_way_data_upd42_wayE <= p0_congr_cl42_act_q and binv_wayE_upd3_q; +p1_way_data_upd42_wayE <= p1_congr_cl42_act_q and reload_wayE_upd3_q; +rel_bixu42_wayE_upd(0) <= p1_way_data_upd42_wayE and p1_wren_q; +rel_bixu42_wayE_upd(1) <= p0_way_data_upd42_wayE and p0_wren_q; +p0_way_data_upd42_wayF <= p0_congr_cl42_act_q and binv_wayF_upd3_q; +p1_way_data_upd42_wayF <= p1_congr_cl42_act_q and reload_wayF_upd3_q; +rel_bixu42_wayF_upd(0) <= p1_way_data_upd42_wayF and p1_wren_q; +rel_bixu42_wayF_upd(1) <= p0_way_data_upd42_wayF and p0_wren_q; +p0_way_data_upd42_wayG <= p0_congr_cl42_act_q and binv_wayG_upd3_q; +p1_way_data_upd42_wayG <= p1_congr_cl42_act_q and reload_wayG_upd3_q; +rel_bixu42_wayG_upd(0) <= p1_way_data_upd42_wayG and p1_wren_q; +rel_bixu42_wayG_upd(1) <= p0_way_data_upd42_wayG and p0_wren_q; +p0_way_data_upd42_wayH <= p0_congr_cl42_act_q and binv_wayH_upd3_q; +p1_way_data_upd42_wayH <= p1_congr_cl42_act_q and reload_wayH_upd3_q; +rel_bixu42_wayH_upd(0) <= p1_way_data_upd42_wayH and p1_wren_q; +rel_bixu42_wayH_upd(1) <= p0_way_data_upd42_wayH and p0_wren_q; +p0_congr_cl43_m <= (ex5_congr_cl_q = tconv(43,6)); +p1_congr_cl43_m <= (relu_s_congr_cl_q = tconv(43,6)); +p0_congr_cl43_act_d <= p0_congr_cl43_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl43_act_d <= p1_congr_cl43_m and rel_port_wren_q; +congr_cl43_act <= p0_congr_cl43_act_q or p1_congr_cl43_act_q or congr_cl_all_act_q; +p0_way_data_upd43_wayA <= p0_congr_cl43_act_q and binv_wayA_upd3_q; +p1_way_data_upd43_wayA <= p1_congr_cl43_act_q and reload_wayA_upd3_q; +rel_bixu43_wayA_upd(0) <= p1_way_data_upd43_wayA and p1_wren_q; +rel_bixu43_wayA_upd(1) <= p0_way_data_upd43_wayA and p0_wren_q; +p0_way_data_upd43_wayB <= p0_congr_cl43_act_q and binv_wayB_upd3_q; +p1_way_data_upd43_wayB <= p1_congr_cl43_act_q and reload_wayB_upd3_q; +rel_bixu43_wayB_upd(0) <= p1_way_data_upd43_wayB and p1_wren_q; +rel_bixu43_wayB_upd(1) <= p0_way_data_upd43_wayB and p0_wren_q; +p0_way_data_upd43_wayC <= p0_congr_cl43_act_q and binv_wayC_upd3_q; +p1_way_data_upd43_wayC <= p1_congr_cl43_act_q and reload_wayC_upd3_q; +rel_bixu43_wayC_upd(0) <= p1_way_data_upd43_wayC and p1_wren_q; +rel_bixu43_wayC_upd(1) <= p0_way_data_upd43_wayC and p0_wren_q; +p0_way_data_upd43_wayD <= p0_congr_cl43_act_q and binv_wayD_upd3_q; +p1_way_data_upd43_wayD <= p1_congr_cl43_act_q and reload_wayD_upd3_q; +rel_bixu43_wayD_upd(0) <= p1_way_data_upd43_wayD and p1_wren_q; +rel_bixu43_wayD_upd(1) <= p0_way_data_upd43_wayD and p0_wren_q; +p0_way_data_upd43_wayE <= p0_congr_cl43_act_q and binv_wayE_upd3_q; +p1_way_data_upd43_wayE <= p1_congr_cl43_act_q and reload_wayE_upd3_q; +rel_bixu43_wayE_upd(0) <= p1_way_data_upd43_wayE and p1_wren_q; +rel_bixu43_wayE_upd(1) <= p0_way_data_upd43_wayE and p0_wren_q; +p0_way_data_upd43_wayF <= p0_congr_cl43_act_q and binv_wayF_upd3_q; +p1_way_data_upd43_wayF <= p1_congr_cl43_act_q and reload_wayF_upd3_q; +rel_bixu43_wayF_upd(0) <= p1_way_data_upd43_wayF and p1_wren_q; +rel_bixu43_wayF_upd(1) <= p0_way_data_upd43_wayF and p0_wren_q; +p0_way_data_upd43_wayG <= p0_congr_cl43_act_q and binv_wayG_upd3_q; +p1_way_data_upd43_wayG <= p1_congr_cl43_act_q and reload_wayG_upd3_q; +rel_bixu43_wayG_upd(0) <= p1_way_data_upd43_wayG and p1_wren_q; +rel_bixu43_wayG_upd(1) <= p0_way_data_upd43_wayG and p0_wren_q; +p0_way_data_upd43_wayH <= p0_congr_cl43_act_q and binv_wayH_upd3_q; +p1_way_data_upd43_wayH <= p1_congr_cl43_act_q and reload_wayH_upd3_q; +rel_bixu43_wayH_upd(0) <= p1_way_data_upd43_wayH and p1_wren_q; +rel_bixu43_wayH_upd(1) <= p0_way_data_upd43_wayH and p0_wren_q; +p0_congr_cl44_m <= (ex5_congr_cl_q = tconv(44,6)); +p1_congr_cl44_m <= (relu_s_congr_cl_q = tconv(44,6)); +p0_congr_cl44_act_d <= p0_congr_cl44_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl44_act_d <= p1_congr_cl44_m and rel_port_wren_q; +congr_cl44_act <= p0_congr_cl44_act_q or p1_congr_cl44_act_q or congr_cl_all_act_q; +p0_way_data_upd44_wayA <= p0_congr_cl44_act_q and binv_wayA_upd3_q; +p1_way_data_upd44_wayA <= p1_congr_cl44_act_q and reload_wayA_upd3_q; +rel_bixu44_wayA_upd(0) <= p1_way_data_upd44_wayA and p1_wren_q; +rel_bixu44_wayA_upd(1) <= p0_way_data_upd44_wayA and p0_wren_q; +p0_way_data_upd44_wayB <= p0_congr_cl44_act_q and binv_wayB_upd3_q; +p1_way_data_upd44_wayB <= p1_congr_cl44_act_q and reload_wayB_upd3_q; +rel_bixu44_wayB_upd(0) <= p1_way_data_upd44_wayB and p1_wren_q; +rel_bixu44_wayB_upd(1) <= p0_way_data_upd44_wayB and p0_wren_q; +p0_way_data_upd44_wayC <= p0_congr_cl44_act_q and binv_wayC_upd3_q; +p1_way_data_upd44_wayC <= p1_congr_cl44_act_q and reload_wayC_upd3_q; +rel_bixu44_wayC_upd(0) <= p1_way_data_upd44_wayC and p1_wren_q; +rel_bixu44_wayC_upd(1) <= p0_way_data_upd44_wayC and p0_wren_q; +p0_way_data_upd44_wayD <= p0_congr_cl44_act_q and binv_wayD_upd3_q; +p1_way_data_upd44_wayD <= p1_congr_cl44_act_q and reload_wayD_upd3_q; +rel_bixu44_wayD_upd(0) <= p1_way_data_upd44_wayD and p1_wren_q; +rel_bixu44_wayD_upd(1) <= p0_way_data_upd44_wayD and p0_wren_q; +p0_way_data_upd44_wayE <= p0_congr_cl44_act_q and binv_wayE_upd3_q; +p1_way_data_upd44_wayE <= p1_congr_cl44_act_q and reload_wayE_upd3_q; +rel_bixu44_wayE_upd(0) <= p1_way_data_upd44_wayE and p1_wren_q; +rel_bixu44_wayE_upd(1) <= p0_way_data_upd44_wayE and p0_wren_q; +p0_way_data_upd44_wayF <= p0_congr_cl44_act_q and binv_wayF_upd3_q; +p1_way_data_upd44_wayF <= p1_congr_cl44_act_q and reload_wayF_upd3_q; +rel_bixu44_wayF_upd(0) <= p1_way_data_upd44_wayF and p1_wren_q; +rel_bixu44_wayF_upd(1) <= p0_way_data_upd44_wayF and p0_wren_q; +p0_way_data_upd44_wayG <= p0_congr_cl44_act_q and binv_wayG_upd3_q; +p1_way_data_upd44_wayG <= p1_congr_cl44_act_q and reload_wayG_upd3_q; +rel_bixu44_wayG_upd(0) <= p1_way_data_upd44_wayG and p1_wren_q; +rel_bixu44_wayG_upd(1) <= p0_way_data_upd44_wayG and p0_wren_q; +p0_way_data_upd44_wayH <= p0_congr_cl44_act_q and binv_wayH_upd3_q; +p1_way_data_upd44_wayH <= p1_congr_cl44_act_q and reload_wayH_upd3_q; +rel_bixu44_wayH_upd(0) <= p1_way_data_upd44_wayH and p1_wren_q; +rel_bixu44_wayH_upd(1) <= p0_way_data_upd44_wayH and p0_wren_q; +p0_congr_cl45_m <= (ex5_congr_cl_q = tconv(45,6)); +p1_congr_cl45_m <= (relu_s_congr_cl_q = tconv(45,6)); +p0_congr_cl45_act_d <= p0_congr_cl45_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl45_act_d <= p1_congr_cl45_m and rel_port_wren_q; +congr_cl45_act <= p0_congr_cl45_act_q or p1_congr_cl45_act_q or congr_cl_all_act_q; +p0_way_data_upd45_wayA <= p0_congr_cl45_act_q and binv_wayA_upd3_q; +p1_way_data_upd45_wayA <= p1_congr_cl45_act_q and reload_wayA_upd3_q; +rel_bixu45_wayA_upd(0) <= p1_way_data_upd45_wayA and p1_wren_q; +rel_bixu45_wayA_upd(1) <= p0_way_data_upd45_wayA and p0_wren_q; +p0_way_data_upd45_wayB <= p0_congr_cl45_act_q and binv_wayB_upd3_q; +p1_way_data_upd45_wayB <= p1_congr_cl45_act_q and reload_wayB_upd3_q; +rel_bixu45_wayB_upd(0) <= p1_way_data_upd45_wayB and p1_wren_q; +rel_bixu45_wayB_upd(1) <= p0_way_data_upd45_wayB and p0_wren_q; +p0_way_data_upd45_wayC <= p0_congr_cl45_act_q and binv_wayC_upd3_q; +p1_way_data_upd45_wayC <= p1_congr_cl45_act_q and reload_wayC_upd3_q; +rel_bixu45_wayC_upd(0) <= p1_way_data_upd45_wayC and p1_wren_q; +rel_bixu45_wayC_upd(1) <= p0_way_data_upd45_wayC and p0_wren_q; +p0_way_data_upd45_wayD <= p0_congr_cl45_act_q and binv_wayD_upd3_q; +p1_way_data_upd45_wayD <= p1_congr_cl45_act_q and reload_wayD_upd3_q; +rel_bixu45_wayD_upd(0) <= p1_way_data_upd45_wayD and p1_wren_q; +rel_bixu45_wayD_upd(1) <= p0_way_data_upd45_wayD and p0_wren_q; +p0_way_data_upd45_wayE <= p0_congr_cl45_act_q and binv_wayE_upd3_q; +p1_way_data_upd45_wayE <= p1_congr_cl45_act_q and reload_wayE_upd3_q; +rel_bixu45_wayE_upd(0) <= p1_way_data_upd45_wayE and p1_wren_q; +rel_bixu45_wayE_upd(1) <= p0_way_data_upd45_wayE and p0_wren_q; +p0_way_data_upd45_wayF <= p0_congr_cl45_act_q and binv_wayF_upd3_q; +p1_way_data_upd45_wayF <= p1_congr_cl45_act_q and reload_wayF_upd3_q; +rel_bixu45_wayF_upd(0) <= p1_way_data_upd45_wayF and p1_wren_q; +rel_bixu45_wayF_upd(1) <= p0_way_data_upd45_wayF and p0_wren_q; +p0_way_data_upd45_wayG <= p0_congr_cl45_act_q and binv_wayG_upd3_q; +p1_way_data_upd45_wayG <= p1_congr_cl45_act_q and reload_wayG_upd3_q; +rel_bixu45_wayG_upd(0) <= p1_way_data_upd45_wayG and p1_wren_q; +rel_bixu45_wayG_upd(1) <= p0_way_data_upd45_wayG and p0_wren_q; +p0_way_data_upd45_wayH <= p0_congr_cl45_act_q and binv_wayH_upd3_q; +p1_way_data_upd45_wayH <= p1_congr_cl45_act_q and reload_wayH_upd3_q; +rel_bixu45_wayH_upd(0) <= p1_way_data_upd45_wayH and p1_wren_q; +rel_bixu45_wayH_upd(1) <= p0_way_data_upd45_wayH and p0_wren_q; +p0_congr_cl46_m <= (ex5_congr_cl_q = tconv(46,6)); +p1_congr_cl46_m <= (relu_s_congr_cl_q = tconv(46,6)); +p0_congr_cl46_act_d <= p0_congr_cl46_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl46_act_d <= p1_congr_cl46_m and rel_port_wren_q; +congr_cl46_act <= p0_congr_cl46_act_q or p1_congr_cl46_act_q or congr_cl_all_act_q; +p0_way_data_upd46_wayA <= p0_congr_cl46_act_q and binv_wayA_upd3_q; +p1_way_data_upd46_wayA <= p1_congr_cl46_act_q and reload_wayA_upd3_q; +rel_bixu46_wayA_upd(0) <= p1_way_data_upd46_wayA and p1_wren_q; +rel_bixu46_wayA_upd(1) <= p0_way_data_upd46_wayA and p0_wren_q; +p0_way_data_upd46_wayB <= p0_congr_cl46_act_q and binv_wayB_upd3_q; +p1_way_data_upd46_wayB <= p1_congr_cl46_act_q and reload_wayB_upd3_q; +rel_bixu46_wayB_upd(0) <= p1_way_data_upd46_wayB and p1_wren_q; +rel_bixu46_wayB_upd(1) <= p0_way_data_upd46_wayB and p0_wren_q; +p0_way_data_upd46_wayC <= p0_congr_cl46_act_q and binv_wayC_upd3_q; +p1_way_data_upd46_wayC <= p1_congr_cl46_act_q and reload_wayC_upd3_q; +rel_bixu46_wayC_upd(0) <= p1_way_data_upd46_wayC and p1_wren_q; +rel_bixu46_wayC_upd(1) <= p0_way_data_upd46_wayC and p0_wren_q; +p0_way_data_upd46_wayD <= p0_congr_cl46_act_q and binv_wayD_upd3_q; +p1_way_data_upd46_wayD <= p1_congr_cl46_act_q and reload_wayD_upd3_q; +rel_bixu46_wayD_upd(0) <= p1_way_data_upd46_wayD and p1_wren_q; +rel_bixu46_wayD_upd(1) <= p0_way_data_upd46_wayD and p0_wren_q; +p0_way_data_upd46_wayE <= p0_congr_cl46_act_q and binv_wayE_upd3_q; +p1_way_data_upd46_wayE <= p1_congr_cl46_act_q and reload_wayE_upd3_q; +rel_bixu46_wayE_upd(0) <= p1_way_data_upd46_wayE and p1_wren_q; +rel_bixu46_wayE_upd(1) <= p0_way_data_upd46_wayE and p0_wren_q; +p0_way_data_upd46_wayF <= p0_congr_cl46_act_q and binv_wayF_upd3_q; +p1_way_data_upd46_wayF <= p1_congr_cl46_act_q and reload_wayF_upd3_q; +rel_bixu46_wayF_upd(0) <= p1_way_data_upd46_wayF and p1_wren_q; +rel_bixu46_wayF_upd(1) <= p0_way_data_upd46_wayF and p0_wren_q; +p0_way_data_upd46_wayG <= p0_congr_cl46_act_q and binv_wayG_upd3_q; +p1_way_data_upd46_wayG <= p1_congr_cl46_act_q and reload_wayG_upd3_q; +rel_bixu46_wayG_upd(0) <= p1_way_data_upd46_wayG and p1_wren_q; +rel_bixu46_wayG_upd(1) <= p0_way_data_upd46_wayG and p0_wren_q; +p0_way_data_upd46_wayH <= p0_congr_cl46_act_q and binv_wayH_upd3_q; +p1_way_data_upd46_wayH <= p1_congr_cl46_act_q and reload_wayH_upd3_q; +rel_bixu46_wayH_upd(0) <= p1_way_data_upd46_wayH and p1_wren_q; +rel_bixu46_wayH_upd(1) <= p0_way_data_upd46_wayH and p0_wren_q; +p0_congr_cl47_m <= (ex5_congr_cl_q = tconv(47,6)); +p1_congr_cl47_m <= (relu_s_congr_cl_q = tconv(47,6)); +p0_congr_cl47_act_d <= p0_congr_cl47_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl47_act_d <= p1_congr_cl47_m and rel_port_wren_q; +congr_cl47_act <= p0_congr_cl47_act_q or p1_congr_cl47_act_q or congr_cl_all_act_q; +p0_way_data_upd47_wayA <= p0_congr_cl47_act_q and binv_wayA_upd3_q; +p1_way_data_upd47_wayA <= p1_congr_cl47_act_q and reload_wayA_upd3_q; +rel_bixu47_wayA_upd(0) <= p1_way_data_upd47_wayA and p1_wren_q; +rel_bixu47_wayA_upd(1) <= p0_way_data_upd47_wayA and p0_wren_q; +p0_way_data_upd47_wayB <= p0_congr_cl47_act_q and binv_wayB_upd3_q; +p1_way_data_upd47_wayB <= p1_congr_cl47_act_q and reload_wayB_upd3_q; +rel_bixu47_wayB_upd(0) <= p1_way_data_upd47_wayB and p1_wren_q; +rel_bixu47_wayB_upd(1) <= p0_way_data_upd47_wayB and p0_wren_q; +p0_way_data_upd47_wayC <= p0_congr_cl47_act_q and binv_wayC_upd3_q; +p1_way_data_upd47_wayC <= p1_congr_cl47_act_q and reload_wayC_upd3_q; +rel_bixu47_wayC_upd(0) <= p1_way_data_upd47_wayC and p1_wren_q; +rel_bixu47_wayC_upd(1) <= p0_way_data_upd47_wayC and p0_wren_q; +p0_way_data_upd47_wayD <= p0_congr_cl47_act_q and binv_wayD_upd3_q; +p1_way_data_upd47_wayD <= p1_congr_cl47_act_q and reload_wayD_upd3_q; +rel_bixu47_wayD_upd(0) <= p1_way_data_upd47_wayD and p1_wren_q; +rel_bixu47_wayD_upd(1) <= p0_way_data_upd47_wayD and p0_wren_q; +p0_way_data_upd47_wayE <= p0_congr_cl47_act_q and binv_wayE_upd3_q; +p1_way_data_upd47_wayE <= p1_congr_cl47_act_q and reload_wayE_upd3_q; +rel_bixu47_wayE_upd(0) <= p1_way_data_upd47_wayE and p1_wren_q; +rel_bixu47_wayE_upd(1) <= p0_way_data_upd47_wayE and p0_wren_q; +p0_way_data_upd47_wayF <= p0_congr_cl47_act_q and binv_wayF_upd3_q; +p1_way_data_upd47_wayF <= p1_congr_cl47_act_q and reload_wayF_upd3_q; +rel_bixu47_wayF_upd(0) <= p1_way_data_upd47_wayF and p1_wren_q; +rel_bixu47_wayF_upd(1) <= p0_way_data_upd47_wayF and p0_wren_q; +p0_way_data_upd47_wayG <= p0_congr_cl47_act_q and binv_wayG_upd3_q; +p1_way_data_upd47_wayG <= p1_congr_cl47_act_q and reload_wayG_upd3_q; +rel_bixu47_wayG_upd(0) <= p1_way_data_upd47_wayG and p1_wren_q; +rel_bixu47_wayG_upd(1) <= p0_way_data_upd47_wayG and p0_wren_q; +p0_way_data_upd47_wayH <= p0_congr_cl47_act_q and binv_wayH_upd3_q; +p1_way_data_upd47_wayH <= p1_congr_cl47_act_q and reload_wayH_upd3_q; +rel_bixu47_wayH_upd(0) <= p1_way_data_upd47_wayH and p1_wren_q; +rel_bixu47_wayH_upd(1) <= p0_way_data_upd47_wayH and p0_wren_q; +p0_congr_cl48_m <= (ex5_congr_cl_q = tconv(48,6)); +p1_congr_cl48_m <= (relu_s_congr_cl_q = tconv(48,6)); +p0_congr_cl48_act_d <= p0_congr_cl48_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl48_act_d <= p1_congr_cl48_m and rel_port_wren_q; +congr_cl48_act <= p0_congr_cl48_act_q or p1_congr_cl48_act_q or congr_cl_all_act_q; +p0_way_data_upd48_wayA <= p0_congr_cl48_act_q and binv_wayA_upd3_q; +p1_way_data_upd48_wayA <= p1_congr_cl48_act_q and reload_wayA_upd3_q; +rel_bixu48_wayA_upd(0) <= p1_way_data_upd48_wayA and p1_wren_q; +rel_bixu48_wayA_upd(1) <= p0_way_data_upd48_wayA and p0_wren_q; +p0_way_data_upd48_wayB <= p0_congr_cl48_act_q and binv_wayB_upd3_q; +p1_way_data_upd48_wayB <= p1_congr_cl48_act_q and reload_wayB_upd3_q; +rel_bixu48_wayB_upd(0) <= p1_way_data_upd48_wayB and p1_wren_q; +rel_bixu48_wayB_upd(1) <= p0_way_data_upd48_wayB and p0_wren_q; +p0_way_data_upd48_wayC <= p0_congr_cl48_act_q and binv_wayC_upd3_q; +p1_way_data_upd48_wayC <= p1_congr_cl48_act_q and reload_wayC_upd3_q; +rel_bixu48_wayC_upd(0) <= p1_way_data_upd48_wayC and p1_wren_q; +rel_bixu48_wayC_upd(1) <= p0_way_data_upd48_wayC and p0_wren_q; +p0_way_data_upd48_wayD <= p0_congr_cl48_act_q and binv_wayD_upd3_q; +p1_way_data_upd48_wayD <= p1_congr_cl48_act_q and reload_wayD_upd3_q; +rel_bixu48_wayD_upd(0) <= p1_way_data_upd48_wayD and p1_wren_q; +rel_bixu48_wayD_upd(1) <= p0_way_data_upd48_wayD and p0_wren_q; +p0_way_data_upd48_wayE <= p0_congr_cl48_act_q and binv_wayE_upd3_q; +p1_way_data_upd48_wayE <= p1_congr_cl48_act_q and reload_wayE_upd3_q; +rel_bixu48_wayE_upd(0) <= p1_way_data_upd48_wayE and p1_wren_q; +rel_bixu48_wayE_upd(1) <= p0_way_data_upd48_wayE and p0_wren_q; +p0_way_data_upd48_wayF <= p0_congr_cl48_act_q and binv_wayF_upd3_q; +p1_way_data_upd48_wayF <= p1_congr_cl48_act_q and reload_wayF_upd3_q; +rel_bixu48_wayF_upd(0) <= p1_way_data_upd48_wayF and p1_wren_q; +rel_bixu48_wayF_upd(1) <= p0_way_data_upd48_wayF and p0_wren_q; +p0_way_data_upd48_wayG <= p0_congr_cl48_act_q and binv_wayG_upd3_q; +p1_way_data_upd48_wayG <= p1_congr_cl48_act_q and reload_wayG_upd3_q; +rel_bixu48_wayG_upd(0) <= p1_way_data_upd48_wayG and p1_wren_q; +rel_bixu48_wayG_upd(1) <= p0_way_data_upd48_wayG and p0_wren_q; +p0_way_data_upd48_wayH <= p0_congr_cl48_act_q and binv_wayH_upd3_q; +p1_way_data_upd48_wayH <= p1_congr_cl48_act_q and reload_wayH_upd3_q; +rel_bixu48_wayH_upd(0) <= p1_way_data_upd48_wayH and p1_wren_q; +rel_bixu48_wayH_upd(1) <= p0_way_data_upd48_wayH and p0_wren_q; +p0_congr_cl49_m <= (ex5_congr_cl_q = tconv(49,6)); +p1_congr_cl49_m <= (relu_s_congr_cl_q = tconv(49,6)); +p0_congr_cl49_act_d <= p0_congr_cl49_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl49_act_d <= p1_congr_cl49_m and rel_port_wren_q; +congr_cl49_act <= p0_congr_cl49_act_q or p1_congr_cl49_act_q or congr_cl_all_act_q; +p0_way_data_upd49_wayA <= p0_congr_cl49_act_q and binv_wayA_upd3_q; +p1_way_data_upd49_wayA <= p1_congr_cl49_act_q and reload_wayA_upd3_q; +rel_bixu49_wayA_upd(0) <= p1_way_data_upd49_wayA and p1_wren_q; +rel_bixu49_wayA_upd(1) <= p0_way_data_upd49_wayA and p0_wren_q; +p0_way_data_upd49_wayB <= p0_congr_cl49_act_q and binv_wayB_upd3_q; +p1_way_data_upd49_wayB <= p1_congr_cl49_act_q and reload_wayB_upd3_q; +rel_bixu49_wayB_upd(0) <= p1_way_data_upd49_wayB and p1_wren_q; +rel_bixu49_wayB_upd(1) <= p0_way_data_upd49_wayB and p0_wren_q; +p0_way_data_upd49_wayC <= p0_congr_cl49_act_q and binv_wayC_upd3_q; +p1_way_data_upd49_wayC <= p1_congr_cl49_act_q and reload_wayC_upd3_q; +rel_bixu49_wayC_upd(0) <= p1_way_data_upd49_wayC and p1_wren_q; +rel_bixu49_wayC_upd(1) <= p0_way_data_upd49_wayC and p0_wren_q; +p0_way_data_upd49_wayD <= p0_congr_cl49_act_q and binv_wayD_upd3_q; +p1_way_data_upd49_wayD <= p1_congr_cl49_act_q and reload_wayD_upd3_q; +rel_bixu49_wayD_upd(0) <= p1_way_data_upd49_wayD and p1_wren_q; +rel_bixu49_wayD_upd(1) <= p0_way_data_upd49_wayD and p0_wren_q; +p0_way_data_upd49_wayE <= p0_congr_cl49_act_q and binv_wayE_upd3_q; +p1_way_data_upd49_wayE <= p1_congr_cl49_act_q and reload_wayE_upd3_q; +rel_bixu49_wayE_upd(0) <= p1_way_data_upd49_wayE and p1_wren_q; +rel_bixu49_wayE_upd(1) <= p0_way_data_upd49_wayE and p0_wren_q; +p0_way_data_upd49_wayF <= p0_congr_cl49_act_q and binv_wayF_upd3_q; +p1_way_data_upd49_wayF <= p1_congr_cl49_act_q and reload_wayF_upd3_q; +rel_bixu49_wayF_upd(0) <= p1_way_data_upd49_wayF and p1_wren_q; +rel_bixu49_wayF_upd(1) <= p0_way_data_upd49_wayF and p0_wren_q; +p0_way_data_upd49_wayG <= p0_congr_cl49_act_q and binv_wayG_upd3_q; +p1_way_data_upd49_wayG <= p1_congr_cl49_act_q and reload_wayG_upd3_q; +rel_bixu49_wayG_upd(0) <= p1_way_data_upd49_wayG and p1_wren_q; +rel_bixu49_wayG_upd(1) <= p0_way_data_upd49_wayG and p0_wren_q; +p0_way_data_upd49_wayH <= p0_congr_cl49_act_q and binv_wayH_upd3_q; +p1_way_data_upd49_wayH <= p1_congr_cl49_act_q and reload_wayH_upd3_q; +rel_bixu49_wayH_upd(0) <= p1_way_data_upd49_wayH and p1_wren_q; +rel_bixu49_wayH_upd(1) <= p0_way_data_upd49_wayH and p0_wren_q; +p0_congr_cl50_m <= (ex5_congr_cl_q = tconv(50,6)); +p1_congr_cl50_m <= (relu_s_congr_cl_q = tconv(50,6)); +p0_congr_cl50_act_d <= p0_congr_cl50_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl50_act_d <= p1_congr_cl50_m and rel_port_wren_q; +congr_cl50_act <= p0_congr_cl50_act_q or p1_congr_cl50_act_q or congr_cl_all_act_q; +p0_way_data_upd50_wayA <= p0_congr_cl50_act_q and binv_wayA_upd3_q; +p1_way_data_upd50_wayA <= p1_congr_cl50_act_q and reload_wayA_upd3_q; +rel_bixu50_wayA_upd(0) <= p1_way_data_upd50_wayA and p1_wren_q; +rel_bixu50_wayA_upd(1) <= p0_way_data_upd50_wayA and p0_wren_q; +p0_way_data_upd50_wayB <= p0_congr_cl50_act_q and binv_wayB_upd3_q; +p1_way_data_upd50_wayB <= p1_congr_cl50_act_q and reload_wayB_upd3_q; +rel_bixu50_wayB_upd(0) <= p1_way_data_upd50_wayB and p1_wren_q; +rel_bixu50_wayB_upd(1) <= p0_way_data_upd50_wayB and p0_wren_q; +p0_way_data_upd50_wayC <= p0_congr_cl50_act_q and binv_wayC_upd3_q; +p1_way_data_upd50_wayC <= p1_congr_cl50_act_q and reload_wayC_upd3_q; +rel_bixu50_wayC_upd(0) <= p1_way_data_upd50_wayC and p1_wren_q; +rel_bixu50_wayC_upd(1) <= p0_way_data_upd50_wayC and p0_wren_q; +p0_way_data_upd50_wayD <= p0_congr_cl50_act_q and binv_wayD_upd3_q; +p1_way_data_upd50_wayD <= p1_congr_cl50_act_q and reload_wayD_upd3_q; +rel_bixu50_wayD_upd(0) <= p1_way_data_upd50_wayD and p1_wren_q; +rel_bixu50_wayD_upd(1) <= p0_way_data_upd50_wayD and p0_wren_q; +p0_way_data_upd50_wayE <= p0_congr_cl50_act_q and binv_wayE_upd3_q; +p1_way_data_upd50_wayE <= p1_congr_cl50_act_q and reload_wayE_upd3_q; +rel_bixu50_wayE_upd(0) <= p1_way_data_upd50_wayE and p1_wren_q; +rel_bixu50_wayE_upd(1) <= p0_way_data_upd50_wayE and p0_wren_q; +p0_way_data_upd50_wayF <= p0_congr_cl50_act_q and binv_wayF_upd3_q; +p1_way_data_upd50_wayF <= p1_congr_cl50_act_q and reload_wayF_upd3_q; +rel_bixu50_wayF_upd(0) <= p1_way_data_upd50_wayF and p1_wren_q; +rel_bixu50_wayF_upd(1) <= p0_way_data_upd50_wayF and p0_wren_q; +p0_way_data_upd50_wayG <= p0_congr_cl50_act_q and binv_wayG_upd3_q; +p1_way_data_upd50_wayG <= p1_congr_cl50_act_q and reload_wayG_upd3_q; +rel_bixu50_wayG_upd(0) <= p1_way_data_upd50_wayG and p1_wren_q; +rel_bixu50_wayG_upd(1) <= p0_way_data_upd50_wayG and p0_wren_q; +p0_way_data_upd50_wayH <= p0_congr_cl50_act_q and binv_wayH_upd3_q; +p1_way_data_upd50_wayH <= p1_congr_cl50_act_q and reload_wayH_upd3_q; +rel_bixu50_wayH_upd(0) <= p1_way_data_upd50_wayH and p1_wren_q; +rel_bixu50_wayH_upd(1) <= p0_way_data_upd50_wayH and p0_wren_q; +p0_congr_cl51_m <= (ex5_congr_cl_q = tconv(51,6)); +p1_congr_cl51_m <= (relu_s_congr_cl_q = tconv(51,6)); +p0_congr_cl51_act_d <= p0_congr_cl51_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl51_act_d <= p1_congr_cl51_m and rel_port_wren_q; +congr_cl51_act <= p0_congr_cl51_act_q or p1_congr_cl51_act_q or congr_cl_all_act_q; +p0_way_data_upd51_wayA <= p0_congr_cl51_act_q and binv_wayA_upd3_q; +p1_way_data_upd51_wayA <= p1_congr_cl51_act_q and reload_wayA_upd3_q; +rel_bixu51_wayA_upd(0) <= p1_way_data_upd51_wayA and p1_wren_q; +rel_bixu51_wayA_upd(1) <= p0_way_data_upd51_wayA and p0_wren_q; +p0_way_data_upd51_wayB <= p0_congr_cl51_act_q and binv_wayB_upd3_q; +p1_way_data_upd51_wayB <= p1_congr_cl51_act_q and reload_wayB_upd3_q; +rel_bixu51_wayB_upd(0) <= p1_way_data_upd51_wayB and p1_wren_q; +rel_bixu51_wayB_upd(1) <= p0_way_data_upd51_wayB and p0_wren_q; +p0_way_data_upd51_wayC <= p0_congr_cl51_act_q and binv_wayC_upd3_q; +p1_way_data_upd51_wayC <= p1_congr_cl51_act_q and reload_wayC_upd3_q; +rel_bixu51_wayC_upd(0) <= p1_way_data_upd51_wayC and p1_wren_q; +rel_bixu51_wayC_upd(1) <= p0_way_data_upd51_wayC and p0_wren_q; +p0_way_data_upd51_wayD <= p0_congr_cl51_act_q and binv_wayD_upd3_q; +p1_way_data_upd51_wayD <= p1_congr_cl51_act_q and reload_wayD_upd3_q; +rel_bixu51_wayD_upd(0) <= p1_way_data_upd51_wayD and p1_wren_q; +rel_bixu51_wayD_upd(1) <= p0_way_data_upd51_wayD and p0_wren_q; +p0_way_data_upd51_wayE <= p0_congr_cl51_act_q and binv_wayE_upd3_q; +p1_way_data_upd51_wayE <= p1_congr_cl51_act_q and reload_wayE_upd3_q; +rel_bixu51_wayE_upd(0) <= p1_way_data_upd51_wayE and p1_wren_q; +rel_bixu51_wayE_upd(1) <= p0_way_data_upd51_wayE and p0_wren_q; +p0_way_data_upd51_wayF <= p0_congr_cl51_act_q and binv_wayF_upd3_q; +p1_way_data_upd51_wayF <= p1_congr_cl51_act_q and reload_wayF_upd3_q; +rel_bixu51_wayF_upd(0) <= p1_way_data_upd51_wayF and p1_wren_q; +rel_bixu51_wayF_upd(1) <= p0_way_data_upd51_wayF and p0_wren_q; +p0_way_data_upd51_wayG <= p0_congr_cl51_act_q and binv_wayG_upd3_q; +p1_way_data_upd51_wayG <= p1_congr_cl51_act_q and reload_wayG_upd3_q; +rel_bixu51_wayG_upd(0) <= p1_way_data_upd51_wayG and p1_wren_q; +rel_bixu51_wayG_upd(1) <= p0_way_data_upd51_wayG and p0_wren_q; +p0_way_data_upd51_wayH <= p0_congr_cl51_act_q and binv_wayH_upd3_q; +p1_way_data_upd51_wayH <= p1_congr_cl51_act_q and reload_wayH_upd3_q; +rel_bixu51_wayH_upd(0) <= p1_way_data_upd51_wayH and p1_wren_q; +rel_bixu51_wayH_upd(1) <= p0_way_data_upd51_wayH and p0_wren_q; +p0_congr_cl52_m <= (ex5_congr_cl_q = tconv(52,6)); +p1_congr_cl52_m <= (relu_s_congr_cl_q = tconv(52,6)); +p0_congr_cl52_act_d <= p0_congr_cl52_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl52_act_d <= p1_congr_cl52_m and rel_port_wren_q; +congr_cl52_act <= p0_congr_cl52_act_q or p1_congr_cl52_act_q or congr_cl_all_act_q; +p0_way_data_upd52_wayA <= p0_congr_cl52_act_q and binv_wayA_upd3_q; +p1_way_data_upd52_wayA <= p1_congr_cl52_act_q and reload_wayA_upd3_q; +rel_bixu52_wayA_upd(0) <= p1_way_data_upd52_wayA and p1_wren_q; +rel_bixu52_wayA_upd(1) <= p0_way_data_upd52_wayA and p0_wren_q; +p0_way_data_upd52_wayB <= p0_congr_cl52_act_q and binv_wayB_upd3_q; +p1_way_data_upd52_wayB <= p1_congr_cl52_act_q and reload_wayB_upd3_q; +rel_bixu52_wayB_upd(0) <= p1_way_data_upd52_wayB and p1_wren_q; +rel_bixu52_wayB_upd(1) <= p0_way_data_upd52_wayB and p0_wren_q; +p0_way_data_upd52_wayC <= p0_congr_cl52_act_q and binv_wayC_upd3_q; +p1_way_data_upd52_wayC <= p1_congr_cl52_act_q and reload_wayC_upd3_q; +rel_bixu52_wayC_upd(0) <= p1_way_data_upd52_wayC and p1_wren_q; +rel_bixu52_wayC_upd(1) <= p0_way_data_upd52_wayC and p0_wren_q; +p0_way_data_upd52_wayD <= p0_congr_cl52_act_q and binv_wayD_upd3_q; +p1_way_data_upd52_wayD <= p1_congr_cl52_act_q and reload_wayD_upd3_q; +rel_bixu52_wayD_upd(0) <= p1_way_data_upd52_wayD and p1_wren_q; +rel_bixu52_wayD_upd(1) <= p0_way_data_upd52_wayD and p0_wren_q; +p0_way_data_upd52_wayE <= p0_congr_cl52_act_q and binv_wayE_upd3_q; +p1_way_data_upd52_wayE <= p1_congr_cl52_act_q and reload_wayE_upd3_q; +rel_bixu52_wayE_upd(0) <= p1_way_data_upd52_wayE and p1_wren_q; +rel_bixu52_wayE_upd(1) <= p0_way_data_upd52_wayE and p0_wren_q; +p0_way_data_upd52_wayF <= p0_congr_cl52_act_q and binv_wayF_upd3_q; +p1_way_data_upd52_wayF <= p1_congr_cl52_act_q and reload_wayF_upd3_q; +rel_bixu52_wayF_upd(0) <= p1_way_data_upd52_wayF and p1_wren_q; +rel_bixu52_wayF_upd(1) <= p0_way_data_upd52_wayF and p0_wren_q; +p0_way_data_upd52_wayG <= p0_congr_cl52_act_q and binv_wayG_upd3_q; +p1_way_data_upd52_wayG <= p1_congr_cl52_act_q and reload_wayG_upd3_q; +rel_bixu52_wayG_upd(0) <= p1_way_data_upd52_wayG and p1_wren_q; +rel_bixu52_wayG_upd(1) <= p0_way_data_upd52_wayG and p0_wren_q; +p0_way_data_upd52_wayH <= p0_congr_cl52_act_q and binv_wayH_upd3_q; +p1_way_data_upd52_wayH <= p1_congr_cl52_act_q and reload_wayH_upd3_q; +rel_bixu52_wayH_upd(0) <= p1_way_data_upd52_wayH and p1_wren_q; +rel_bixu52_wayH_upd(1) <= p0_way_data_upd52_wayH and p0_wren_q; +p0_congr_cl53_m <= (ex5_congr_cl_q = tconv(53,6)); +p1_congr_cl53_m <= (relu_s_congr_cl_q = tconv(53,6)); +p0_congr_cl53_act_d <= p0_congr_cl53_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl53_act_d <= p1_congr_cl53_m and rel_port_wren_q; +congr_cl53_act <= p0_congr_cl53_act_q or p1_congr_cl53_act_q or congr_cl_all_act_q; +p0_way_data_upd53_wayA <= p0_congr_cl53_act_q and binv_wayA_upd3_q; +p1_way_data_upd53_wayA <= p1_congr_cl53_act_q and reload_wayA_upd3_q; +rel_bixu53_wayA_upd(0) <= p1_way_data_upd53_wayA and p1_wren_q; +rel_bixu53_wayA_upd(1) <= p0_way_data_upd53_wayA and p0_wren_q; +p0_way_data_upd53_wayB <= p0_congr_cl53_act_q and binv_wayB_upd3_q; +p1_way_data_upd53_wayB <= p1_congr_cl53_act_q and reload_wayB_upd3_q; +rel_bixu53_wayB_upd(0) <= p1_way_data_upd53_wayB and p1_wren_q; +rel_bixu53_wayB_upd(1) <= p0_way_data_upd53_wayB and p0_wren_q; +p0_way_data_upd53_wayC <= p0_congr_cl53_act_q and binv_wayC_upd3_q; +p1_way_data_upd53_wayC <= p1_congr_cl53_act_q and reload_wayC_upd3_q; +rel_bixu53_wayC_upd(0) <= p1_way_data_upd53_wayC and p1_wren_q; +rel_bixu53_wayC_upd(1) <= p0_way_data_upd53_wayC and p0_wren_q; +p0_way_data_upd53_wayD <= p0_congr_cl53_act_q and binv_wayD_upd3_q; +p1_way_data_upd53_wayD <= p1_congr_cl53_act_q and reload_wayD_upd3_q; +rel_bixu53_wayD_upd(0) <= p1_way_data_upd53_wayD and p1_wren_q; +rel_bixu53_wayD_upd(1) <= p0_way_data_upd53_wayD and p0_wren_q; +p0_way_data_upd53_wayE <= p0_congr_cl53_act_q and binv_wayE_upd3_q; +p1_way_data_upd53_wayE <= p1_congr_cl53_act_q and reload_wayE_upd3_q; +rel_bixu53_wayE_upd(0) <= p1_way_data_upd53_wayE and p1_wren_q; +rel_bixu53_wayE_upd(1) <= p0_way_data_upd53_wayE and p0_wren_q; +p0_way_data_upd53_wayF <= p0_congr_cl53_act_q and binv_wayF_upd3_q; +p1_way_data_upd53_wayF <= p1_congr_cl53_act_q and reload_wayF_upd3_q; +rel_bixu53_wayF_upd(0) <= p1_way_data_upd53_wayF and p1_wren_q; +rel_bixu53_wayF_upd(1) <= p0_way_data_upd53_wayF and p0_wren_q; +p0_way_data_upd53_wayG <= p0_congr_cl53_act_q and binv_wayG_upd3_q; +p1_way_data_upd53_wayG <= p1_congr_cl53_act_q and reload_wayG_upd3_q; +rel_bixu53_wayG_upd(0) <= p1_way_data_upd53_wayG and p1_wren_q; +rel_bixu53_wayG_upd(1) <= p0_way_data_upd53_wayG and p0_wren_q; +p0_way_data_upd53_wayH <= p0_congr_cl53_act_q and binv_wayH_upd3_q; +p1_way_data_upd53_wayH <= p1_congr_cl53_act_q and reload_wayH_upd3_q; +rel_bixu53_wayH_upd(0) <= p1_way_data_upd53_wayH and p1_wren_q; +rel_bixu53_wayH_upd(1) <= p0_way_data_upd53_wayH and p0_wren_q; +p0_congr_cl54_m <= (ex5_congr_cl_q = tconv(54,6)); +p1_congr_cl54_m <= (relu_s_congr_cl_q = tconv(54,6)); +p0_congr_cl54_act_d <= p0_congr_cl54_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl54_act_d <= p1_congr_cl54_m and rel_port_wren_q; +congr_cl54_act <= p0_congr_cl54_act_q or p1_congr_cl54_act_q or congr_cl_all_act_q; +p0_way_data_upd54_wayA <= p0_congr_cl54_act_q and binv_wayA_upd3_q; +p1_way_data_upd54_wayA <= p1_congr_cl54_act_q and reload_wayA_upd3_q; +rel_bixu54_wayA_upd(0) <= p1_way_data_upd54_wayA and p1_wren_q; +rel_bixu54_wayA_upd(1) <= p0_way_data_upd54_wayA and p0_wren_q; +p0_way_data_upd54_wayB <= p0_congr_cl54_act_q and binv_wayB_upd3_q; +p1_way_data_upd54_wayB <= p1_congr_cl54_act_q and reload_wayB_upd3_q; +rel_bixu54_wayB_upd(0) <= p1_way_data_upd54_wayB and p1_wren_q; +rel_bixu54_wayB_upd(1) <= p0_way_data_upd54_wayB and p0_wren_q; +p0_way_data_upd54_wayC <= p0_congr_cl54_act_q and binv_wayC_upd3_q; +p1_way_data_upd54_wayC <= p1_congr_cl54_act_q and reload_wayC_upd3_q; +rel_bixu54_wayC_upd(0) <= p1_way_data_upd54_wayC and p1_wren_q; +rel_bixu54_wayC_upd(1) <= p0_way_data_upd54_wayC and p0_wren_q; +p0_way_data_upd54_wayD <= p0_congr_cl54_act_q and binv_wayD_upd3_q; +p1_way_data_upd54_wayD <= p1_congr_cl54_act_q and reload_wayD_upd3_q; +rel_bixu54_wayD_upd(0) <= p1_way_data_upd54_wayD and p1_wren_q; +rel_bixu54_wayD_upd(1) <= p0_way_data_upd54_wayD and p0_wren_q; +p0_way_data_upd54_wayE <= p0_congr_cl54_act_q and binv_wayE_upd3_q; +p1_way_data_upd54_wayE <= p1_congr_cl54_act_q and reload_wayE_upd3_q; +rel_bixu54_wayE_upd(0) <= p1_way_data_upd54_wayE and p1_wren_q; +rel_bixu54_wayE_upd(1) <= p0_way_data_upd54_wayE and p0_wren_q; +p0_way_data_upd54_wayF <= p0_congr_cl54_act_q and binv_wayF_upd3_q; +p1_way_data_upd54_wayF <= p1_congr_cl54_act_q and reload_wayF_upd3_q; +rel_bixu54_wayF_upd(0) <= p1_way_data_upd54_wayF and p1_wren_q; +rel_bixu54_wayF_upd(1) <= p0_way_data_upd54_wayF and p0_wren_q; +p0_way_data_upd54_wayG <= p0_congr_cl54_act_q and binv_wayG_upd3_q; +p1_way_data_upd54_wayG <= p1_congr_cl54_act_q and reload_wayG_upd3_q; +rel_bixu54_wayG_upd(0) <= p1_way_data_upd54_wayG and p1_wren_q; +rel_bixu54_wayG_upd(1) <= p0_way_data_upd54_wayG and p0_wren_q; +p0_way_data_upd54_wayH <= p0_congr_cl54_act_q and binv_wayH_upd3_q; +p1_way_data_upd54_wayH <= p1_congr_cl54_act_q and reload_wayH_upd3_q; +rel_bixu54_wayH_upd(0) <= p1_way_data_upd54_wayH and p1_wren_q; +rel_bixu54_wayH_upd(1) <= p0_way_data_upd54_wayH and p0_wren_q; +p0_congr_cl55_m <= (ex5_congr_cl_q = tconv(55,6)); +p1_congr_cl55_m <= (relu_s_congr_cl_q = tconv(55,6)); +p0_congr_cl55_act_d <= p0_congr_cl55_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl55_act_d <= p1_congr_cl55_m and rel_port_wren_q; +congr_cl55_act <= p0_congr_cl55_act_q or p1_congr_cl55_act_q or congr_cl_all_act_q; +p0_way_data_upd55_wayA <= p0_congr_cl55_act_q and binv_wayA_upd3_q; +p1_way_data_upd55_wayA <= p1_congr_cl55_act_q and reload_wayA_upd3_q; +rel_bixu55_wayA_upd(0) <= p1_way_data_upd55_wayA and p1_wren_q; +rel_bixu55_wayA_upd(1) <= p0_way_data_upd55_wayA and p0_wren_q; +p0_way_data_upd55_wayB <= p0_congr_cl55_act_q and binv_wayB_upd3_q; +p1_way_data_upd55_wayB <= p1_congr_cl55_act_q and reload_wayB_upd3_q; +rel_bixu55_wayB_upd(0) <= p1_way_data_upd55_wayB and p1_wren_q; +rel_bixu55_wayB_upd(1) <= p0_way_data_upd55_wayB and p0_wren_q; +p0_way_data_upd55_wayC <= p0_congr_cl55_act_q and binv_wayC_upd3_q; +p1_way_data_upd55_wayC <= p1_congr_cl55_act_q and reload_wayC_upd3_q; +rel_bixu55_wayC_upd(0) <= p1_way_data_upd55_wayC and p1_wren_q; +rel_bixu55_wayC_upd(1) <= p0_way_data_upd55_wayC and p0_wren_q; +p0_way_data_upd55_wayD <= p0_congr_cl55_act_q and binv_wayD_upd3_q; +p1_way_data_upd55_wayD <= p1_congr_cl55_act_q and reload_wayD_upd3_q; +rel_bixu55_wayD_upd(0) <= p1_way_data_upd55_wayD and p1_wren_q; +rel_bixu55_wayD_upd(1) <= p0_way_data_upd55_wayD and p0_wren_q; +p0_way_data_upd55_wayE <= p0_congr_cl55_act_q and binv_wayE_upd3_q; +p1_way_data_upd55_wayE <= p1_congr_cl55_act_q and reload_wayE_upd3_q; +rel_bixu55_wayE_upd(0) <= p1_way_data_upd55_wayE and p1_wren_q; +rel_bixu55_wayE_upd(1) <= p0_way_data_upd55_wayE and p0_wren_q; +p0_way_data_upd55_wayF <= p0_congr_cl55_act_q and binv_wayF_upd3_q; +p1_way_data_upd55_wayF <= p1_congr_cl55_act_q and reload_wayF_upd3_q; +rel_bixu55_wayF_upd(0) <= p1_way_data_upd55_wayF and p1_wren_q; +rel_bixu55_wayF_upd(1) <= p0_way_data_upd55_wayF and p0_wren_q; +p0_way_data_upd55_wayG <= p0_congr_cl55_act_q and binv_wayG_upd3_q; +p1_way_data_upd55_wayG <= p1_congr_cl55_act_q and reload_wayG_upd3_q; +rel_bixu55_wayG_upd(0) <= p1_way_data_upd55_wayG and p1_wren_q; +rel_bixu55_wayG_upd(1) <= p0_way_data_upd55_wayG and p0_wren_q; +p0_way_data_upd55_wayH <= p0_congr_cl55_act_q and binv_wayH_upd3_q; +p1_way_data_upd55_wayH <= p1_congr_cl55_act_q and reload_wayH_upd3_q; +rel_bixu55_wayH_upd(0) <= p1_way_data_upd55_wayH and p1_wren_q; +rel_bixu55_wayH_upd(1) <= p0_way_data_upd55_wayH and p0_wren_q; +p0_congr_cl56_m <= (ex5_congr_cl_q = tconv(56,6)); +p1_congr_cl56_m <= (relu_s_congr_cl_q = tconv(56,6)); +p0_congr_cl56_act_d <= p0_congr_cl56_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl56_act_d <= p1_congr_cl56_m and rel_port_wren_q; +congr_cl56_act <= p0_congr_cl56_act_q or p1_congr_cl56_act_q or congr_cl_all_act_q; +p0_way_data_upd56_wayA <= p0_congr_cl56_act_q and binv_wayA_upd3_q; +p1_way_data_upd56_wayA <= p1_congr_cl56_act_q and reload_wayA_upd3_q; +rel_bixu56_wayA_upd(0) <= p1_way_data_upd56_wayA and p1_wren_q; +rel_bixu56_wayA_upd(1) <= p0_way_data_upd56_wayA and p0_wren_q; +p0_way_data_upd56_wayB <= p0_congr_cl56_act_q and binv_wayB_upd3_q; +p1_way_data_upd56_wayB <= p1_congr_cl56_act_q and reload_wayB_upd3_q; +rel_bixu56_wayB_upd(0) <= p1_way_data_upd56_wayB and p1_wren_q; +rel_bixu56_wayB_upd(1) <= p0_way_data_upd56_wayB and p0_wren_q; +p0_way_data_upd56_wayC <= p0_congr_cl56_act_q and binv_wayC_upd3_q; +p1_way_data_upd56_wayC <= p1_congr_cl56_act_q and reload_wayC_upd3_q; +rel_bixu56_wayC_upd(0) <= p1_way_data_upd56_wayC and p1_wren_q; +rel_bixu56_wayC_upd(1) <= p0_way_data_upd56_wayC and p0_wren_q; +p0_way_data_upd56_wayD <= p0_congr_cl56_act_q and binv_wayD_upd3_q; +p1_way_data_upd56_wayD <= p1_congr_cl56_act_q and reload_wayD_upd3_q; +rel_bixu56_wayD_upd(0) <= p1_way_data_upd56_wayD and p1_wren_q; +rel_bixu56_wayD_upd(1) <= p0_way_data_upd56_wayD and p0_wren_q; +p0_way_data_upd56_wayE <= p0_congr_cl56_act_q and binv_wayE_upd3_q; +p1_way_data_upd56_wayE <= p1_congr_cl56_act_q and reload_wayE_upd3_q; +rel_bixu56_wayE_upd(0) <= p1_way_data_upd56_wayE and p1_wren_q; +rel_bixu56_wayE_upd(1) <= p0_way_data_upd56_wayE and p0_wren_q; +p0_way_data_upd56_wayF <= p0_congr_cl56_act_q and binv_wayF_upd3_q; +p1_way_data_upd56_wayF <= p1_congr_cl56_act_q and reload_wayF_upd3_q; +rel_bixu56_wayF_upd(0) <= p1_way_data_upd56_wayF and p1_wren_q; +rel_bixu56_wayF_upd(1) <= p0_way_data_upd56_wayF and p0_wren_q; +p0_way_data_upd56_wayG <= p0_congr_cl56_act_q and binv_wayG_upd3_q; +p1_way_data_upd56_wayG <= p1_congr_cl56_act_q and reload_wayG_upd3_q; +rel_bixu56_wayG_upd(0) <= p1_way_data_upd56_wayG and p1_wren_q; +rel_bixu56_wayG_upd(1) <= p0_way_data_upd56_wayG and p0_wren_q; +p0_way_data_upd56_wayH <= p0_congr_cl56_act_q and binv_wayH_upd3_q; +p1_way_data_upd56_wayH <= p1_congr_cl56_act_q and reload_wayH_upd3_q; +rel_bixu56_wayH_upd(0) <= p1_way_data_upd56_wayH and p1_wren_q; +rel_bixu56_wayH_upd(1) <= p0_way_data_upd56_wayH and p0_wren_q; +p0_congr_cl57_m <= (ex5_congr_cl_q = tconv(57,6)); +p1_congr_cl57_m <= (relu_s_congr_cl_q = tconv(57,6)); +p0_congr_cl57_act_d <= p0_congr_cl57_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl57_act_d <= p1_congr_cl57_m and rel_port_wren_q; +congr_cl57_act <= p0_congr_cl57_act_q or p1_congr_cl57_act_q or congr_cl_all_act_q; +p0_way_data_upd57_wayA <= p0_congr_cl57_act_q and binv_wayA_upd3_q; +p1_way_data_upd57_wayA <= p1_congr_cl57_act_q and reload_wayA_upd3_q; +rel_bixu57_wayA_upd(0) <= p1_way_data_upd57_wayA and p1_wren_q; +rel_bixu57_wayA_upd(1) <= p0_way_data_upd57_wayA and p0_wren_q; +p0_way_data_upd57_wayB <= p0_congr_cl57_act_q and binv_wayB_upd3_q; +p1_way_data_upd57_wayB <= p1_congr_cl57_act_q and reload_wayB_upd3_q; +rel_bixu57_wayB_upd(0) <= p1_way_data_upd57_wayB and p1_wren_q; +rel_bixu57_wayB_upd(1) <= p0_way_data_upd57_wayB and p0_wren_q; +p0_way_data_upd57_wayC <= p0_congr_cl57_act_q and binv_wayC_upd3_q; +p1_way_data_upd57_wayC <= p1_congr_cl57_act_q and reload_wayC_upd3_q; +rel_bixu57_wayC_upd(0) <= p1_way_data_upd57_wayC and p1_wren_q; +rel_bixu57_wayC_upd(1) <= p0_way_data_upd57_wayC and p0_wren_q; +p0_way_data_upd57_wayD <= p0_congr_cl57_act_q and binv_wayD_upd3_q; +p1_way_data_upd57_wayD <= p1_congr_cl57_act_q and reload_wayD_upd3_q; +rel_bixu57_wayD_upd(0) <= p1_way_data_upd57_wayD and p1_wren_q; +rel_bixu57_wayD_upd(1) <= p0_way_data_upd57_wayD and p0_wren_q; +p0_way_data_upd57_wayE <= p0_congr_cl57_act_q and binv_wayE_upd3_q; +p1_way_data_upd57_wayE <= p1_congr_cl57_act_q and reload_wayE_upd3_q; +rel_bixu57_wayE_upd(0) <= p1_way_data_upd57_wayE and p1_wren_q; +rel_bixu57_wayE_upd(1) <= p0_way_data_upd57_wayE and p0_wren_q; +p0_way_data_upd57_wayF <= p0_congr_cl57_act_q and binv_wayF_upd3_q; +p1_way_data_upd57_wayF <= p1_congr_cl57_act_q and reload_wayF_upd3_q; +rel_bixu57_wayF_upd(0) <= p1_way_data_upd57_wayF and p1_wren_q; +rel_bixu57_wayF_upd(1) <= p0_way_data_upd57_wayF and p0_wren_q; +p0_way_data_upd57_wayG <= p0_congr_cl57_act_q and binv_wayG_upd3_q; +p1_way_data_upd57_wayG <= p1_congr_cl57_act_q and reload_wayG_upd3_q; +rel_bixu57_wayG_upd(0) <= p1_way_data_upd57_wayG and p1_wren_q; +rel_bixu57_wayG_upd(1) <= p0_way_data_upd57_wayG and p0_wren_q; +p0_way_data_upd57_wayH <= p0_congr_cl57_act_q and binv_wayH_upd3_q; +p1_way_data_upd57_wayH <= p1_congr_cl57_act_q and reload_wayH_upd3_q; +rel_bixu57_wayH_upd(0) <= p1_way_data_upd57_wayH and p1_wren_q; +rel_bixu57_wayH_upd(1) <= p0_way_data_upd57_wayH and p0_wren_q; +p0_congr_cl58_m <= (ex5_congr_cl_q = tconv(58,6)); +p1_congr_cl58_m <= (relu_s_congr_cl_q = tconv(58,6)); +p0_congr_cl58_act_d <= p0_congr_cl58_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl58_act_d <= p1_congr_cl58_m and rel_port_wren_q; +congr_cl58_act <= p0_congr_cl58_act_q or p1_congr_cl58_act_q or congr_cl_all_act_q; +p0_way_data_upd58_wayA <= p0_congr_cl58_act_q and binv_wayA_upd3_q; +p1_way_data_upd58_wayA <= p1_congr_cl58_act_q and reload_wayA_upd3_q; +rel_bixu58_wayA_upd(0) <= p1_way_data_upd58_wayA and p1_wren_q; +rel_bixu58_wayA_upd(1) <= p0_way_data_upd58_wayA and p0_wren_q; +p0_way_data_upd58_wayB <= p0_congr_cl58_act_q and binv_wayB_upd3_q; +p1_way_data_upd58_wayB <= p1_congr_cl58_act_q and reload_wayB_upd3_q; +rel_bixu58_wayB_upd(0) <= p1_way_data_upd58_wayB and p1_wren_q; +rel_bixu58_wayB_upd(1) <= p0_way_data_upd58_wayB and p0_wren_q; +p0_way_data_upd58_wayC <= p0_congr_cl58_act_q and binv_wayC_upd3_q; +p1_way_data_upd58_wayC <= p1_congr_cl58_act_q and reload_wayC_upd3_q; +rel_bixu58_wayC_upd(0) <= p1_way_data_upd58_wayC and p1_wren_q; +rel_bixu58_wayC_upd(1) <= p0_way_data_upd58_wayC and p0_wren_q; +p0_way_data_upd58_wayD <= p0_congr_cl58_act_q and binv_wayD_upd3_q; +p1_way_data_upd58_wayD <= p1_congr_cl58_act_q and reload_wayD_upd3_q; +rel_bixu58_wayD_upd(0) <= p1_way_data_upd58_wayD and p1_wren_q; +rel_bixu58_wayD_upd(1) <= p0_way_data_upd58_wayD and p0_wren_q; +p0_way_data_upd58_wayE <= p0_congr_cl58_act_q and binv_wayE_upd3_q; +p1_way_data_upd58_wayE <= p1_congr_cl58_act_q and reload_wayE_upd3_q; +rel_bixu58_wayE_upd(0) <= p1_way_data_upd58_wayE and p1_wren_q; +rel_bixu58_wayE_upd(1) <= p0_way_data_upd58_wayE and p0_wren_q; +p0_way_data_upd58_wayF <= p0_congr_cl58_act_q and binv_wayF_upd3_q; +p1_way_data_upd58_wayF <= p1_congr_cl58_act_q and reload_wayF_upd3_q; +rel_bixu58_wayF_upd(0) <= p1_way_data_upd58_wayF and p1_wren_q; +rel_bixu58_wayF_upd(1) <= p0_way_data_upd58_wayF and p0_wren_q; +p0_way_data_upd58_wayG <= p0_congr_cl58_act_q and binv_wayG_upd3_q; +p1_way_data_upd58_wayG <= p1_congr_cl58_act_q and reload_wayG_upd3_q; +rel_bixu58_wayG_upd(0) <= p1_way_data_upd58_wayG and p1_wren_q; +rel_bixu58_wayG_upd(1) <= p0_way_data_upd58_wayG and p0_wren_q; +p0_way_data_upd58_wayH <= p0_congr_cl58_act_q and binv_wayH_upd3_q; +p1_way_data_upd58_wayH <= p1_congr_cl58_act_q and reload_wayH_upd3_q; +rel_bixu58_wayH_upd(0) <= p1_way_data_upd58_wayH and p1_wren_q; +rel_bixu58_wayH_upd(1) <= p0_way_data_upd58_wayH and p0_wren_q; +p0_congr_cl59_m <= (ex5_congr_cl_q = tconv(59,6)); +p1_congr_cl59_m <= (relu_s_congr_cl_q = tconv(59,6)); +p0_congr_cl59_act_d <= p0_congr_cl59_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl59_act_d <= p1_congr_cl59_m and rel_port_wren_q; +congr_cl59_act <= p0_congr_cl59_act_q or p1_congr_cl59_act_q or congr_cl_all_act_q; +p0_way_data_upd59_wayA <= p0_congr_cl59_act_q and binv_wayA_upd3_q; +p1_way_data_upd59_wayA <= p1_congr_cl59_act_q and reload_wayA_upd3_q; +rel_bixu59_wayA_upd(0) <= p1_way_data_upd59_wayA and p1_wren_q; +rel_bixu59_wayA_upd(1) <= p0_way_data_upd59_wayA and p0_wren_q; +p0_way_data_upd59_wayB <= p0_congr_cl59_act_q and binv_wayB_upd3_q; +p1_way_data_upd59_wayB <= p1_congr_cl59_act_q and reload_wayB_upd3_q; +rel_bixu59_wayB_upd(0) <= p1_way_data_upd59_wayB and p1_wren_q; +rel_bixu59_wayB_upd(1) <= p0_way_data_upd59_wayB and p0_wren_q; +p0_way_data_upd59_wayC <= p0_congr_cl59_act_q and binv_wayC_upd3_q; +p1_way_data_upd59_wayC <= p1_congr_cl59_act_q and reload_wayC_upd3_q; +rel_bixu59_wayC_upd(0) <= p1_way_data_upd59_wayC and p1_wren_q; +rel_bixu59_wayC_upd(1) <= p0_way_data_upd59_wayC and p0_wren_q; +p0_way_data_upd59_wayD <= p0_congr_cl59_act_q and binv_wayD_upd3_q; +p1_way_data_upd59_wayD <= p1_congr_cl59_act_q and reload_wayD_upd3_q; +rel_bixu59_wayD_upd(0) <= p1_way_data_upd59_wayD and p1_wren_q; +rel_bixu59_wayD_upd(1) <= p0_way_data_upd59_wayD and p0_wren_q; +p0_way_data_upd59_wayE <= p0_congr_cl59_act_q and binv_wayE_upd3_q; +p1_way_data_upd59_wayE <= p1_congr_cl59_act_q and reload_wayE_upd3_q; +rel_bixu59_wayE_upd(0) <= p1_way_data_upd59_wayE and p1_wren_q; +rel_bixu59_wayE_upd(1) <= p0_way_data_upd59_wayE and p0_wren_q; +p0_way_data_upd59_wayF <= p0_congr_cl59_act_q and binv_wayF_upd3_q; +p1_way_data_upd59_wayF <= p1_congr_cl59_act_q and reload_wayF_upd3_q; +rel_bixu59_wayF_upd(0) <= p1_way_data_upd59_wayF and p1_wren_q; +rel_bixu59_wayF_upd(1) <= p0_way_data_upd59_wayF and p0_wren_q; +p0_way_data_upd59_wayG <= p0_congr_cl59_act_q and binv_wayG_upd3_q; +p1_way_data_upd59_wayG <= p1_congr_cl59_act_q and reload_wayG_upd3_q; +rel_bixu59_wayG_upd(0) <= p1_way_data_upd59_wayG and p1_wren_q; +rel_bixu59_wayG_upd(1) <= p0_way_data_upd59_wayG and p0_wren_q; +p0_way_data_upd59_wayH <= p0_congr_cl59_act_q and binv_wayH_upd3_q; +p1_way_data_upd59_wayH <= p1_congr_cl59_act_q and reload_wayH_upd3_q; +rel_bixu59_wayH_upd(0) <= p1_way_data_upd59_wayH and p1_wren_q; +rel_bixu59_wayH_upd(1) <= p0_way_data_upd59_wayH and p0_wren_q; +p0_congr_cl60_m <= (ex5_congr_cl_q = tconv(60,6)); +p1_congr_cl60_m <= (relu_s_congr_cl_q = tconv(60,6)); +p0_congr_cl60_act_d <= p0_congr_cl60_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl60_act_d <= p1_congr_cl60_m and rel_port_wren_q; +congr_cl60_act <= p0_congr_cl60_act_q or p1_congr_cl60_act_q or congr_cl_all_act_q; +p0_way_data_upd60_wayA <= p0_congr_cl60_act_q and binv_wayA_upd3_q; +p1_way_data_upd60_wayA <= p1_congr_cl60_act_q and reload_wayA_upd3_q; +rel_bixu60_wayA_upd(0) <= p1_way_data_upd60_wayA and p1_wren_q; +rel_bixu60_wayA_upd(1) <= p0_way_data_upd60_wayA and p0_wren_q; +p0_way_data_upd60_wayB <= p0_congr_cl60_act_q and binv_wayB_upd3_q; +p1_way_data_upd60_wayB <= p1_congr_cl60_act_q and reload_wayB_upd3_q; +rel_bixu60_wayB_upd(0) <= p1_way_data_upd60_wayB and p1_wren_q; +rel_bixu60_wayB_upd(1) <= p0_way_data_upd60_wayB and p0_wren_q; +p0_way_data_upd60_wayC <= p0_congr_cl60_act_q and binv_wayC_upd3_q; +p1_way_data_upd60_wayC <= p1_congr_cl60_act_q and reload_wayC_upd3_q; +rel_bixu60_wayC_upd(0) <= p1_way_data_upd60_wayC and p1_wren_q; +rel_bixu60_wayC_upd(1) <= p0_way_data_upd60_wayC and p0_wren_q; +p0_way_data_upd60_wayD <= p0_congr_cl60_act_q and binv_wayD_upd3_q; +p1_way_data_upd60_wayD <= p1_congr_cl60_act_q and reload_wayD_upd3_q; +rel_bixu60_wayD_upd(0) <= p1_way_data_upd60_wayD and p1_wren_q; +rel_bixu60_wayD_upd(1) <= p0_way_data_upd60_wayD and p0_wren_q; +p0_way_data_upd60_wayE <= p0_congr_cl60_act_q and binv_wayE_upd3_q; +p1_way_data_upd60_wayE <= p1_congr_cl60_act_q and reload_wayE_upd3_q; +rel_bixu60_wayE_upd(0) <= p1_way_data_upd60_wayE and p1_wren_q; +rel_bixu60_wayE_upd(1) <= p0_way_data_upd60_wayE and p0_wren_q; +p0_way_data_upd60_wayF <= p0_congr_cl60_act_q and binv_wayF_upd3_q; +p1_way_data_upd60_wayF <= p1_congr_cl60_act_q and reload_wayF_upd3_q; +rel_bixu60_wayF_upd(0) <= p1_way_data_upd60_wayF and p1_wren_q; +rel_bixu60_wayF_upd(1) <= p0_way_data_upd60_wayF and p0_wren_q; +p0_way_data_upd60_wayG <= p0_congr_cl60_act_q and binv_wayG_upd3_q; +p1_way_data_upd60_wayG <= p1_congr_cl60_act_q and reload_wayG_upd3_q; +rel_bixu60_wayG_upd(0) <= p1_way_data_upd60_wayG and p1_wren_q; +rel_bixu60_wayG_upd(1) <= p0_way_data_upd60_wayG and p0_wren_q; +p0_way_data_upd60_wayH <= p0_congr_cl60_act_q and binv_wayH_upd3_q; +p1_way_data_upd60_wayH <= p1_congr_cl60_act_q and reload_wayH_upd3_q; +rel_bixu60_wayH_upd(0) <= p1_way_data_upd60_wayH and p1_wren_q; +rel_bixu60_wayH_upd(1) <= p0_way_data_upd60_wayH and p0_wren_q; +p0_congr_cl61_m <= (ex5_congr_cl_q = tconv(61,6)); +p1_congr_cl61_m <= (relu_s_congr_cl_q = tconv(61,6)); +p0_congr_cl61_act_d <= p0_congr_cl61_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl61_act_d <= p1_congr_cl61_m and rel_port_wren_q; +congr_cl61_act <= p0_congr_cl61_act_q or p1_congr_cl61_act_q or congr_cl_all_act_q; +p0_way_data_upd61_wayA <= p0_congr_cl61_act_q and binv_wayA_upd3_q; +p1_way_data_upd61_wayA <= p1_congr_cl61_act_q and reload_wayA_upd3_q; +rel_bixu61_wayA_upd(0) <= p1_way_data_upd61_wayA and p1_wren_q; +rel_bixu61_wayA_upd(1) <= p0_way_data_upd61_wayA and p0_wren_q; +p0_way_data_upd61_wayB <= p0_congr_cl61_act_q and binv_wayB_upd3_q; +p1_way_data_upd61_wayB <= p1_congr_cl61_act_q and reload_wayB_upd3_q; +rel_bixu61_wayB_upd(0) <= p1_way_data_upd61_wayB and p1_wren_q; +rel_bixu61_wayB_upd(1) <= p0_way_data_upd61_wayB and p0_wren_q; +p0_way_data_upd61_wayC <= p0_congr_cl61_act_q and binv_wayC_upd3_q; +p1_way_data_upd61_wayC <= p1_congr_cl61_act_q and reload_wayC_upd3_q; +rel_bixu61_wayC_upd(0) <= p1_way_data_upd61_wayC and p1_wren_q; +rel_bixu61_wayC_upd(1) <= p0_way_data_upd61_wayC and p0_wren_q; +p0_way_data_upd61_wayD <= p0_congr_cl61_act_q and binv_wayD_upd3_q; +p1_way_data_upd61_wayD <= p1_congr_cl61_act_q and reload_wayD_upd3_q; +rel_bixu61_wayD_upd(0) <= p1_way_data_upd61_wayD and p1_wren_q; +rel_bixu61_wayD_upd(1) <= p0_way_data_upd61_wayD and p0_wren_q; +p0_way_data_upd61_wayE <= p0_congr_cl61_act_q and binv_wayE_upd3_q; +p1_way_data_upd61_wayE <= p1_congr_cl61_act_q and reload_wayE_upd3_q; +rel_bixu61_wayE_upd(0) <= p1_way_data_upd61_wayE and p1_wren_q; +rel_bixu61_wayE_upd(1) <= p0_way_data_upd61_wayE and p0_wren_q; +p0_way_data_upd61_wayF <= p0_congr_cl61_act_q and binv_wayF_upd3_q; +p1_way_data_upd61_wayF <= p1_congr_cl61_act_q and reload_wayF_upd3_q; +rel_bixu61_wayF_upd(0) <= p1_way_data_upd61_wayF and p1_wren_q; +rel_bixu61_wayF_upd(1) <= p0_way_data_upd61_wayF and p0_wren_q; +p0_way_data_upd61_wayG <= p0_congr_cl61_act_q and binv_wayG_upd3_q; +p1_way_data_upd61_wayG <= p1_congr_cl61_act_q and reload_wayG_upd3_q; +rel_bixu61_wayG_upd(0) <= p1_way_data_upd61_wayG and p1_wren_q; +rel_bixu61_wayG_upd(1) <= p0_way_data_upd61_wayG and p0_wren_q; +p0_way_data_upd61_wayH <= p0_congr_cl61_act_q and binv_wayH_upd3_q; +p1_way_data_upd61_wayH <= p1_congr_cl61_act_q and reload_wayH_upd3_q; +rel_bixu61_wayH_upd(0) <= p1_way_data_upd61_wayH and p1_wren_q; +rel_bixu61_wayH_upd(1) <= p0_way_data_upd61_wayH and p0_wren_q; +p0_congr_cl62_m <= (ex5_congr_cl_q = tconv(62,6)); +p1_congr_cl62_m <= (relu_s_congr_cl_q = tconv(62,6)); +p0_congr_cl62_act_d <= p0_congr_cl62_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl62_act_d <= p1_congr_cl62_m and rel_port_wren_q; +congr_cl62_act <= p0_congr_cl62_act_q or p1_congr_cl62_act_q or congr_cl_all_act_q; +p0_way_data_upd62_wayA <= p0_congr_cl62_act_q and binv_wayA_upd3_q; +p1_way_data_upd62_wayA <= p1_congr_cl62_act_q and reload_wayA_upd3_q; +rel_bixu62_wayA_upd(0) <= p1_way_data_upd62_wayA and p1_wren_q; +rel_bixu62_wayA_upd(1) <= p0_way_data_upd62_wayA and p0_wren_q; +p0_way_data_upd62_wayB <= p0_congr_cl62_act_q and binv_wayB_upd3_q; +p1_way_data_upd62_wayB <= p1_congr_cl62_act_q and reload_wayB_upd3_q; +rel_bixu62_wayB_upd(0) <= p1_way_data_upd62_wayB and p1_wren_q; +rel_bixu62_wayB_upd(1) <= p0_way_data_upd62_wayB and p0_wren_q; +p0_way_data_upd62_wayC <= p0_congr_cl62_act_q and binv_wayC_upd3_q; +p1_way_data_upd62_wayC <= p1_congr_cl62_act_q and reload_wayC_upd3_q; +rel_bixu62_wayC_upd(0) <= p1_way_data_upd62_wayC and p1_wren_q; +rel_bixu62_wayC_upd(1) <= p0_way_data_upd62_wayC and p0_wren_q; +p0_way_data_upd62_wayD <= p0_congr_cl62_act_q and binv_wayD_upd3_q; +p1_way_data_upd62_wayD <= p1_congr_cl62_act_q and reload_wayD_upd3_q; +rel_bixu62_wayD_upd(0) <= p1_way_data_upd62_wayD and p1_wren_q; +rel_bixu62_wayD_upd(1) <= p0_way_data_upd62_wayD and p0_wren_q; +p0_way_data_upd62_wayE <= p0_congr_cl62_act_q and binv_wayE_upd3_q; +p1_way_data_upd62_wayE <= p1_congr_cl62_act_q and reload_wayE_upd3_q; +rel_bixu62_wayE_upd(0) <= p1_way_data_upd62_wayE and p1_wren_q; +rel_bixu62_wayE_upd(1) <= p0_way_data_upd62_wayE and p0_wren_q; +p0_way_data_upd62_wayF <= p0_congr_cl62_act_q and binv_wayF_upd3_q; +p1_way_data_upd62_wayF <= p1_congr_cl62_act_q and reload_wayF_upd3_q; +rel_bixu62_wayF_upd(0) <= p1_way_data_upd62_wayF and p1_wren_q; +rel_bixu62_wayF_upd(1) <= p0_way_data_upd62_wayF and p0_wren_q; +p0_way_data_upd62_wayG <= p0_congr_cl62_act_q and binv_wayG_upd3_q; +p1_way_data_upd62_wayG <= p1_congr_cl62_act_q and reload_wayG_upd3_q; +rel_bixu62_wayG_upd(0) <= p1_way_data_upd62_wayG and p1_wren_q; +rel_bixu62_wayG_upd(1) <= p0_way_data_upd62_wayG and p0_wren_q; +p0_way_data_upd62_wayH <= p0_congr_cl62_act_q and binv_wayH_upd3_q; +p1_way_data_upd62_wayH <= p1_congr_cl62_act_q and reload_wayH_upd3_q; +rel_bixu62_wayH_upd(0) <= p1_way_data_upd62_wayH and p1_wren_q; +rel_bixu62_wayH_upd(1) <= p0_way_data_upd62_wayH and p0_wren_q; +p0_congr_cl63_m <= (ex5_congr_cl_q = tconv(63,6)); +p1_congr_cl63_m <= (relu_s_congr_cl_q = tconv(63,6)); +p0_congr_cl63_act_d <= p0_congr_cl63_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl63_act_d <= p1_congr_cl63_m and rel_port_wren_q; +congr_cl63_act <= p0_congr_cl63_act_q or p1_congr_cl63_act_q or congr_cl_all_act_q; +p0_way_data_upd63_wayA <= p0_congr_cl63_act_q and binv_wayA_upd3_q; +p1_way_data_upd63_wayA <= p1_congr_cl63_act_q and reload_wayA_upd3_q; +rel_bixu63_wayA_upd(0) <= p1_way_data_upd63_wayA and p1_wren_q; +rel_bixu63_wayA_upd(1) <= p0_way_data_upd63_wayA and p0_wren_q; +p0_way_data_upd63_wayB <= p0_congr_cl63_act_q and binv_wayB_upd3_q; +p1_way_data_upd63_wayB <= p1_congr_cl63_act_q and reload_wayB_upd3_q; +rel_bixu63_wayB_upd(0) <= p1_way_data_upd63_wayB and p1_wren_q; +rel_bixu63_wayB_upd(1) <= p0_way_data_upd63_wayB and p0_wren_q; +p0_way_data_upd63_wayC <= p0_congr_cl63_act_q and binv_wayC_upd3_q; +p1_way_data_upd63_wayC <= p1_congr_cl63_act_q and reload_wayC_upd3_q; +rel_bixu63_wayC_upd(0) <= p1_way_data_upd63_wayC and p1_wren_q; +rel_bixu63_wayC_upd(1) <= p0_way_data_upd63_wayC and p0_wren_q; +p0_way_data_upd63_wayD <= p0_congr_cl63_act_q and binv_wayD_upd3_q; +p1_way_data_upd63_wayD <= p1_congr_cl63_act_q and reload_wayD_upd3_q; +rel_bixu63_wayD_upd(0) <= p1_way_data_upd63_wayD and p1_wren_q; +rel_bixu63_wayD_upd(1) <= p0_way_data_upd63_wayD and p0_wren_q; +p0_way_data_upd63_wayE <= p0_congr_cl63_act_q and binv_wayE_upd3_q; +p1_way_data_upd63_wayE <= p1_congr_cl63_act_q and reload_wayE_upd3_q; +rel_bixu63_wayE_upd(0) <= p1_way_data_upd63_wayE and p1_wren_q; +rel_bixu63_wayE_upd(1) <= p0_way_data_upd63_wayE and p0_wren_q; +p0_way_data_upd63_wayF <= p0_congr_cl63_act_q and binv_wayF_upd3_q; +p1_way_data_upd63_wayF <= p1_congr_cl63_act_q and reload_wayF_upd3_q; +rel_bixu63_wayF_upd(0) <= p1_way_data_upd63_wayF and p1_wren_q; +rel_bixu63_wayF_upd(1) <= p0_way_data_upd63_wayF and p0_wren_q; +p0_way_data_upd63_wayG <= p0_congr_cl63_act_q and binv_wayG_upd3_q; +p1_way_data_upd63_wayG <= p1_congr_cl63_act_q and reload_wayG_upd3_q; +rel_bixu63_wayG_upd(0) <= p1_way_data_upd63_wayG and p1_wren_q; +rel_bixu63_wayG_upd(1) <= p0_way_data_upd63_wayG and p0_wren_q; +p0_way_data_upd63_wayH <= p0_congr_cl63_act_q and binv_wayH_upd3_q; +p1_way_data_upd63_wayH <= p1_congr_cl63_act_q and reload_wayH_upd3_q; +rel_bixu63_wayH_upd(0) <= p1_way_data_upd63_wayH and p1_wren_q; +rel_bixu63_wayH_upd(1) <= p0_way_data_upd63_wayH and p0_wren_q; +with rel_bixu0_wayA_upd select + congr_cl0_wA_d(0) <= (congr_cl0_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu0_wayA_upd select + congr_cl0_wA_d(1) <= (congr_cl0_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu0_wayA_upd select + congr_cl0_wA_d(2) <= (congr_cl0_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu0_wayA_upd select + congr_cl0_wA_d(3) <= (congr_cl0_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu0_wayA_upd select + congr_cl0_wA_d(4) <= (congr_cl0_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu0_wayA_upd select + congr_cl0_wA_d(5) <= (congr_cl0_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu1_wayA_upd select + congr_cl1_wA_d(0) <= (congr_cl1_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu1_wayA_upd select + congr_cl1_wA_d(1) <= (congr_cl1_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu1_wayA_upd select + congr_cl1_wA_d(2) <= (congr_cl1_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu1_wayA_upd select + congr_cl1_wA_d(3) <= (congr_cl1_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu1_wayA_upd select + congr_cl1_wA_d(4) <= (congr_cl1_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu1_wayA_upd select + congr_cl1_wA_d(5) <= (congr_cl1_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu2_wayA_upd select + congr_cl2_wA_d(0) <= (congr_cl2_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu2_wayA_upd select + congr_cl2_wA_d(1) <= (congr_cl2_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu2_wayA_upd select + congr_cl2_wA_d(2) <= (congr_cl2_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu2_wayA_upd select + congr_cl2_wA_d(3) <= (congr_cl2_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu2_wayA_upd select + congr_cl2_wA_d(4) <= (congr_cl2_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu2_wayA_upd select + congr_cl2_wA_d(5) <= (congr_cl2_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu3_wayA_upd select + congr_cl3_wA_d(0) <= (congr_cl3_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu3_wayA_upd select + congr_cl3_wA_d(1) <= (congr_cl3_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu3_wayA_upd select + congr_cl3_wA_d(2) <= (congr_cl3_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu3_wayA_upd select + congr_cl3_wA_d(3) <= (congr_cl3_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu3_wayA_upd select + congr_cl3_wA_d(4) <= (congr_cl3_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu3_wayA_upd select + congr_cl3_wA_d(5) <= (congr_cl3_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu4_wayA_upd select + congr_cl4_wA_d(0) <= (congr_cl4_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu4_wayA_upd select + congr_cl4_wA_d(1) <= (congr_cl4_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu4_wayA_upd select + congr_cl4_wA_d(2) <= (congr_cl4_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu4_wayA_upd select + congr_cl4_wA_d(3) <= (congr_cl4_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu4_wayA_upd select + congr_cl4_wA_d(4) <= (congr_cl4_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu4_wayA_upd select + congr_cl4_wA_d(5) <= (congr_cl4_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu5_wayA_upd select + congr_cl5_wA_d(0) <= (congr_cl5_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu5_wayA_upd select + congr_cl5_wA_d(1) <= (congr_cl5_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu5_wayA_upd select + congr_cl5_wA_d(2) <= (congr_cl5_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu5_wayA_upd select + congr_cl5_wA_d(3) <= (congr_cl5_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu5_wayA_upd select + congr_cl5_wA_d(4) <= (congr_cl5_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu5_wayA_upd select + congr_cl5_wA_d(5) <= (congr_cl5_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu6_wayA_upd select + congr_cl6_wA_d(0) <= (congr_cl6_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu6_wayA_upd select + congr_cl6_wA_d(1) <= (congr_cl6_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu6_wayA_upd select + congr_cl6_wA_d(2) <= (congr_cl6_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu6_wayA_upd select + congr_cl6_wA_d(3) <= (congr_cl6_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu6_wayA_upd select + congr_cl6_wA_d(4) <= (congr_cl6_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu6_wayA_upd select + congr_cl6_wA_d(5) <= (congr_cl6_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu7_wayA_upd select + congr_cl7_wA_d(0) <= (congr_cl7_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu7_wayA_upd select + congr_cl7_wA_d(1) <= (congr_cl7_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu7_wayA_upd select + congr_cl7_wA_d(2) <= (congr_cl7_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu7_wayA_upd select + congr_cl7_wA_d(3) <= (congr_cl7_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu7_wayA_upd select + congr_cl7_wA_d(4) <= (congr_cl7_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu7_wayA_upd select + congr_cl7_wA_d(5) <= (congr_cl7_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu8_wayA_upd select + congr_cl8_wA_d(0) <= (congr_cl8_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu8_wayA_upd select + congr_cl8_wA_d(1) <= (congr_cl8_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu8_wayA_upd select + congr_cl8_wA_d(2) <= (congr_cl8_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu8_wayA_upd select + congr_cl8_wA_d(3) <= (congr_cl8_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu8_wayA_upd select + congr_cl8_wA_d(4) <= (congr_cl8_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu8_wayA_upd select + congr_cl8_wA_d(5) <= (congr_cl8_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu9_wayA_upd select + congr_cl9_wA_d(0) <= (congr_cl9_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu9_wayA_upd select + congr_cl9_wA_d(1) <= (congr_cl9_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu9_wayA_upd select + congr_cl9_wA_d(2) <= (congr_cl9_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu9_wayA_upd select + congr_cl9_wA_d(3) <= (congr_cl9_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu9_wayA_upd select + congr_cl9_wA_d(4) <= (congr_cl9_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu9_wayA_upd select + congr_cl9_wA_d(5) <= (congr_cl9_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu10_wayA_upd select + congr_cl10_wA_d(0) <= (congr_cl10_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu10_wayA_upd select + congr_cl10_wA_d(1) <= (congr_cl10_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu10_wayA_upd select + congr_cl10_wA_d(2) <= (congr_cl10_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu10_wayA_upd select + congr_cl10_wA_d(3) <= (congr_cl10_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu10_wayA_upd select + congr_cl10_wA_d(4) <= (congr_cl10_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu10_wayA_upd select + congr_cl10_wA_d(5) <= (congr_cl10_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu11_wayA_upd select + congr_cl11_wA_d(0) <= (congr_cl11_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu11_wayA_upd select + congr_cl11_wA_d(1) <= (congr_cl11_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu11_wayA_upd select + congr_cl11_wA_d(2) <= (congr_cl11_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu11_wayA_upd select + congr_cl11_wA_d(3) <= (congr_cl11_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu11_wayA_upd select + congr_cl11_wA_d(4) <= (congr_cl11_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu11_wayA_upd select + congr_cl11_wA_d(5) <= (congr_cl11_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu12_wayA_upd select + congr_cl12_wA_d(0) <= (congr_cl12_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu12_wayA_upd select + congr_cl12_wA_d(1) <= (congr_cl12_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu12_wayA_upd select + congr_cl12_wA_d(2) <= (congr_cl12_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu12_wayA_upd select + congr_cl12_wA_d(3) <= (congr_cl12_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu12_wayA_upd select + congr_cl12_wA_d(4) <= (congr_cl12_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu12_wayA_upd select + congr_cl12_wA_d(5) <= (congr_cl12_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu13_wayA_upd select + congr_cl13_wA_d(0) <= (congr_cl13_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu13_wayA_upd select + congr_cl13_wA_d(1) <= (congr_cl13_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu13_wayA_upd select + congr_cl13_wA_d(2) <= (congr_cl13_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu13_wayA_upd select + congr_cl13_wA_d(3) <= (congr_cl13_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu13_wayA_upd select + congr_cl13_wA_d(4) <= (congr_cl13_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu13_wayA_upd select + congr_cl13_wA_d(5) <= (congr_cl13_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu14_wayA_upd select + congr_cl14_wA_d(0) <= (congr_cl14_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu14_wayA_upd select + congr_cl14_wA_d(1) <= (congr_cl14_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu14_wayA_upd select + congr_cl14_wA_d(2) <= (congr_cl14_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu14_wayA_upd select + congr_cl14_wA_d(3) <= (congr_cl14_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu14_wayA_upd select + congr_cl14_wA_d(4) <= (congr_cl14_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu14_wayA_upd select + congr_cl14_wA_d(5) <= (congr_cl14_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu15_wayA_upd select + congr_cl15_wA_d(0) <= (congr_cl15_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu15_wayA_upd select + congr_cl15_wA_d(1) <= (congr_cl15_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu15_wayA_upd select + congr_cl15_wA_d(2) <= (congr_cl15_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu15_wayA_upd select + congr_cl15_wA_d(3) <= (congr_cl15_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu15_wayA_upd select + congr_cl15_wA_d(4) <= (congr_cl15_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu15_wayA_upd select + congr_cl15_wA_d(5) <= (congr_cl15_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu16_wayA_upd select + congr_cl16_wA_d(0) <= (congr_cl16_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu16_wayA_upd select + congr_cl16_wA_d(1) <= (congr_cl16_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu16_wayA_upd select + congr_cl16_wA_d(2) <= (congr_cl16_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu16_wayA_upd select + congr_cl16_wA_d(3) <= (congr_cl16_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu16_wayA_upd select + congr_cl16_wA_d(4) <= (congr_cl16_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu16_wayA_upd select + congr_cl16_wA_d(5) <= (congr_cl16_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu17_wayA_upd select + congr_cl17_wA_d(0) <= (congr_cl17_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu17_wayA_upd select + congr_cl17_wA_d(1) <= (congr_cl17_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu17_wayA_upd select + congr_cl17_wA_d(2) <= (congr_cl17_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu17_wayA_upd select + congr_cl17_wA_d(3) <= (congr_cl17_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu17_wayA_upd select + congr_cl17_wA_d(4) <= (congr_cl17_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu17_wayA_upd select + congr_cl17_wA_d(5) <= (congr_cl17_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu18_wayA_upd select + congr_cl18_wA_d(0) <= (congr_cl18_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu18_wayA_upd select + congr_cl18_wA_d(1) <= (congr_cl18_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu18_wayA_upd select + congr_cl18_wA_d(2) <= (congr_cl18_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu18_wayA_upd select + congr_cl18_wA_d(3) <= (congr_cl18_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu18_wayA_upd select + congr_cl18_wA_d(4) <= (congr_cl18_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu18_wayA_upd select + congr_cl18_wA_d(5) <= (congr_cl18_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu19_wayA_upd select + congr_cl19_wA_d(0) <= (congr_cl19_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu19_wayA_upd select + congr_cl19_wA_d(1) <= (congr_cl19_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu19_wayA_upd select + congr_cl19_wA_d(2) <= (congr_cl19_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu19_wayA_upd select + congr_cl19_wA_d(3) <= (congr_cl19_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu19_wayA_upd select + congr_cl19_wA_d(4) <= (congr_cl19_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu19_wayA_upd select + congr_cl19_wA_d(5) <= (congr_cl19_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu20_wayA_upd select + congr_cl20_wA_d(0) <= (congr_cl20_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu20_wayA_upd select + congr_cl20_wA_d(1) <= (congr_cl20_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu20_wayA_upd select + congr_cl20_wA_d(2) <= (congr_cl20_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu20_wayA_upd select + congr_cl20_wA_d(3) <= (congr_cl20_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu20_wayA_upd select + congr_cl20_wA_d(4) <= (congr_cl20_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu20_wayA_upd select + congr_cl20_wA_d(5) <= (congr_cl20_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu21_wayA_upd select + congr_cl21_wA_d(0) <= (congr_cl21_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu21_wayA_upd select + congr_cl21_wA_d(1) <= (congr_cl21_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu21_wayA_upd select + congr_cl21_wA_d(2) <= (congr_cl21_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu21_wayA_upd select + congr_cl21_wA_d(3) <= (congr_cl21_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu21_wayA_upd select + congr_cl21_wA_d(4) <= (congr_cl21_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu21_wayA_upd select + congr_cl21_wA_d(5) <= (congr_cl21_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu22_wayA_upd select + congr_cl22_wA_d(0) <= (congr_cl22_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu22_wayA_upd select + congr_cl22_wA_d(1) <= (congr_cl22_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu22_wayA_upd select + congr_cl22_wA_d(2) <= (congr_cl22_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu22_wayA_upd select + congr_cl22_wA_d(3) <= (congr_cl22_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu22_wayA_upd select + congr_cl22_wA_d(4) <= (congr_cl22_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu22_wayA_upd select + congr_cl22_wA_d(5) <= (congr_cl22_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu23_wayA_upd select + congr_cl23_wA_d(0) <= (congr_cl23_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu23_wayA_upd select + congr_cl23_wA_d(1) <= (congr_cl23_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu23_wayA_upd select + congr_cl23_wA_d(2) <= (congr_cl23_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu23_wayA_upd select + congr_cl23_wA_d(3) <= (congr_cl23_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu23_wayA_upd select + congr_cl23_wA_d(4) <= (congr_cl23_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu23_wayA_upd select + congr_cl23_wA_d(5) <= (congr_cl23_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu24_wayA_upd select + congr_cl24_wA_d(0) <= (congr_cl24_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu24_wayA_upd select + congr_cl24_wA_d(1) <= (congr_cl24_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu24_wayA_upd select + congr_cl24_wA_d(2) <= (congr_cl24_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu24_wayA_upd select + congr_cl24_wA_d(3) <= (congr_cl24_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu24_wayA_upd select + congr_cl24_wA_d(4) <= (congr_cl24_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu24_wayA_upd select + congr_cl24_wA_d(5) <= (congr_cl24_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu25_wayA_upd select + congr_cl25_wA_d(0) <= (congr_cl25_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu25_wayA_upd select + congr_cl25_wA_d(1) <= (congr_cl25_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu25_wayA_upd select + congr_cl25_wA_d(2) <= (congr_cl25_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu25_wayA_upd select + congr_cl25_wA_d(3) <= (congr_cl25_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu25_wayA_upd select + congr_cl25_wA_d(4) <= (congr_cl25_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu25_wayA_upd select + congr_cl25_wA_d(5) <= (congr_cl25_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu26_wayA_upd select + congr_cl26_wA_d(0) <= (congr_cl26_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu26_wayA_upd select + congr_cl26_wA_d(1) <= (congr_cl26_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu26_wayA_upd select + congr_cl26_wA_d(2) <= (congr_cl26_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu26_wayA_upd select + congr_cl26_wA_d(3) <= (congr_cl26_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu26_wayA_upd select + congr_cl26_wA_d(4) <= (congr_cl26_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu26_wayA_upd select + congr_cl26_wA_d(5) <= (congr_cl26_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu27_wayA_upd select + congr_cl27_wA_d(0) <= (congr_cl27_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu27_wayA_upd select + congr_cl27_wA_d(1) <= (congr_cl27_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu27_wayA_upd select + congr_cl27_wA_d(2) <= (congr_cl27_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu27_wayA_upd select + congr_cl27_wA_d(3) <= (congr_cl27_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu27_wayA_upd select + congr_cl27_wA_d(4) <= (congr_cl27_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu27_wayA_upd select + congr_cl27_wA_d(5) <= (congr_cl27_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu28_wayA_upd select + congr_cl28_wA_d(0) <= (congr_cl28_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu28_wayA_upd select + congr_cl28_wA_d(1) <= (congr_cl28_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu28_wayA_upd select + congr_cl28_wA_d(2) <= (congr_cl28_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu28_wayA_upd select + congr_cl28_wA_d(3) <= (congr_cl28_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu28_wayA_upd select + congr_cl28_wA_d(4) <= (congr_cl28_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu28_wayA_upd select + congr_cl28_wA_d(5) <= (congr_cl28_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu29_wayA_upd select + congr_cl29_wA_d(0) <= (congr_cl29_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu29_wayA_upd select + congr_cl29_wA_d(1) <= (congr_cl29_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu29_wayA_upd select + congr_cl29_wA_d(2) <= (congr_cl29_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu29_wayA_upd select + congr_cl29_wA_d(3) <= (congr_cl29_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu29_wayA_upd select + congr_cl29_wA_d(4) <= (congr_cl29_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu29_wayA_upd select + congr_cl29_wA_d(5) <= (congr_cl29_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu30_wayA_upd select + congr_cl30_wA_d(0) <= (congr_cl30_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu30_wayA_upd select + congr_cl30_wA_d(1) <= (congr_cl30_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu30_wayA_upd select + congr_cl30_wA_d(2) <= (congr_cl30_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu30_wayA_upd select + congr_cl30_wA_d(3) <= (congr_cl30_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu30_wayA_upd select + congr_cl30_wA_d(4) <= (congr_cl30_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu30_wayA_upd select + congr_cl30_wA_d(5) <= (congr_cl30_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu31_wayA_upd select + congr_cl31_wA_d(0) <= (congr_cl31_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu31_wayA_upd select + congr_cl31_wA_d(1) <= (congr_cl31_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu31_wayA_upd select + congr_cl31_wA_d(2) <= (congr_cl31_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu31_wayA_upd select + congr_cl31_wA_d(3) <= (congr_cl31_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu31_wayA_upd select + congr_cl31_wA_d(4) <= (congr_cl31_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu31_wayA_upd select + congr_cl31_wA_d(5) <= (congr_cl31_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu32_wayA_upd select + congr_cl32_wA_d(0) <= (congr_cl32_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu32_wayA_upd select + congr_cl32_wA_d(1) <= (congr_cl32_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu32_wayA_upd select + congr_cl32_wA_d(2) <= (congr_cl32_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu32_wayA_upd select + congr_cl32_wA_d(3) <= (congr_cl32_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu32_wayA_upd select + congr_cl32_wA_d(4) <= (congr_cl32_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu32_wayA_upd select + congr_cl32_wA_d(5) <= (congr_cl32_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu33_wayA_upd select + congr_cl33_wA_d(0) <= (congr_cl33_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu33_wayA_upd select + congr_cl33_wA_d(1) <= (congr_cl33_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu33_wayA_upd select + congr_cl33_wA_d(2) <= (congr_cl33_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu33_wayA_upd select + congr_cl33_wA_d(3) <= (congr_cl33_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu33_wayA_upd select + congr_cl33_wA_d(4) <= (congr_cl33_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu33_wayA_upd select + congr_cl33_wA_d(5) <= (congr_cl33_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu34_wayA_upd select + congr_cl34_wA_d(0) <= (congr_cl34_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu34_wayA_upd select + congr_cl34_wA_d(1) <= (congr_cl34_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu34_wayA_upd select + congr_cl34_wA_d(2) <= (congr_cl34_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu34_wayA_upd select + congr_cl34_wA_d(3) <= (congr_cl34_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu34_wayA_upd select + congr_cl34_wA_d(4) <= (congr_cl34_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu34_wayA_upd select + congr_cl34_wA_d(5) <= (congr_cl34_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu35_wayA_upd select + congr_cl35_wA_d(0) <= (congr_cl35_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu35_wayA_upd select + congr_cl35_wA_d(1) <= (congr_cl35_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu35_wayA_upd select + congr_cl35_wA_d(2) <= (congr_cl35_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu35_wayA_upd select + congr_cl35_wA_d(3) <= (congr_cl35_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu35_wayA_upd select + congr_cl35_wA_d(4) <= (congr_cl35_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu35_wayA_upd select + congr_cl35_wA_d(5) <= (congr_cl35_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu36_wayA_upd select + congr_cl36_wA_d(0) <= (congr_cl36_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu36_wayA_upd select + congr_cl36_wA_d(1) <= (congr_cl36_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu36_wayA_upd select + congr_cl36_wA_d(2) <= (congr_cl36_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu36_wayA_upd select + congr_cl36_wA_d(3) <= (congr_cl36_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu36_wayA_upd select + congr_cl36_wA_d(4) <= (congr_cl36_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu36_wayA_upd select + congr_cl36_wA_d(5) <= (congr_cl36_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu37_wayA_upd select + congr_cl37_wA_d(0) <= (congr_cl37_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu37_wayA_upd select + congr_cl37_wA_d(1) <= (congr_cl37_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu37_wayA_upd select + congr_cl37_wA_d(2) <= (congr_cl37_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu37_wayA_upd select + congr_cl37_wA_d(3) <= (congr_cl37_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu37_wayA_upd select + congr_cl37_wA_d(4) <= (congr_cl37_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu37_wayA_upd select + congr_cl37_wA_d(5) <= (congr_cl37_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu38_wayA_upd select + congr_cl38_wA_d(0) <= (congr_cl38_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu38_wayA_upd select + congr_cl38_wA_d(1) <= (congr_cl38_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu38_wayA_upd select + congr_cl38_wA_d(2) <= (congr_cl38_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu38_wayA_upd select + congr_cl38_wA_d(3) <= (congr_cl38_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu38_wayA_upd select + congr_cl38_wA_d(4) <= (congr_cl38_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu38_wayA_upd select + congr_cl38_wA_d(5) <= (congr_cl38_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu39_wayA_upd select + congr_cl39_wA_d(0) <= (congr_cl39_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu39_wayA_upd select + congr_cl39_wA_d(1) <= (congr_cl39_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu39_wayA_upd select + congr_cl39_wA_d(2) <= (congr_cl39_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu39_wayA_upd select + congr_cl39_wA_d(3) <= (congr_cl39_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu39_wayA_upd select + congr_cl39_wA_d(4) <= (congr_cl39_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu39_wayA_upd select + congr_cl39_wA_d(5) <= (congr_cl39_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu40_wayA_upd select + congr_cl40_wA_d(0) <= (congr_cl40_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu40_wayA_upd select + congr_cl40_wA_d(1) <= (congr_cl40_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu40_wayA_upd select + congr_cl40_wA_d(2) <= (congr_cl40_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu40_wayA_upd select + congr_cl40_wA_d(3) <= (congr_cl40_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu40_wayA_upd select + congr_cl40_wA_d(4) <= (congr_cl40_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu40_wayA_upd select + congr_cl40_wA_d(5) <= (congr_cl40_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu41_wayA_upd select + congr_cl41_wA_d(0) <= (congr_cl41_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu41_wayA_upd select + congr_cl41_wA_d(1) <= (congr_cl41_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu41_wayA_upd select + congr_cl41_wA_d(2) <= (congr_cl41_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu41_wayA_upd select + congr_cl41_wA_d(3) <= (congr_cl41_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu41_wayA_upd select + congr_cl41_wA_d(4) <= (congr_cl41_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu41_wayA_upd select + congr_cl41_wA_d(5) <= (congr_cl41_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu42_wayA_upd select + congr_cl42_wA_d(0) <= (congr_cl42_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu42_wayA_upd select + congr_cl42_wA_d(1) <= (congr_cl42_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu42_wayA_upd select + congr_cl42_wA_d(2) <= (congr_cl42_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu42_wayA_upd select + congr_cl42_wA_d(3) <= (congr_cl42_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu42_wayA_upd select + congr_cl42_wA_d(4) <= (congr_cl42_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu42_wayA_upd select + congr_cl42_wA_d(5) <= (congr_cl42_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu43_wayA_upd select + congr_cl43_wA_d(0) <= (congr_cl43_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu43_wayA_upd select + congr_cl43_wA_d(1) <= (congr_cl43_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu43_wayA_upd select + congr_cl43_wA_d(2) <= (congr_cl43_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu43_wayA_upd select + congr_cl43_wA_d(3) <= (congr_cl43_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu43_wayA_upd select + congr_cl43_wA_d(4) <= (congr_cl43_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu43_wayA_upd select + congr_cl43_wA_d(5) <= (congr_cl43_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu44_wayA_upd select + congr_cl44_wA_d(0) <= (congr_cl44_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu44_wayA_upd select + congr_cl44_wA_d(1) <= (congr_cl44_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu44_wayA_upd select + congr_cl44_wA_d(2) <= (congr_cl44_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu44_wayA_upd select + congr_cl44_wA_d(3) <= (congr_cl44_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu44_wayA_upd select + congr_cl44_wA_d(4) <= (congr_cl44_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu44_wayA_upd select + congr_cl44_wA_d(5) <= (congr_cl44_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu45_wayA_upd select + congr_cl45_wA_d(0) <= (congr_cl45_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu45_wayA_upd select + congr_cl45_wA_d(1) <= (congr_cl45_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu45_wayA_upd select + congr_cl45_wA_d(2) <= (congr_cl45_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu45_wayA_upd select + congr_cl45_wA_d(3) <= (congr_cl45_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu45_wayA_upd select + congr_cl45_wA_d(4) <= (congr_cl45_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu45_wayA_upd select + congr_cl45_wA_d(5) <= (congr_cl45_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu46_wayA_upd select + congr_cl46_wA_d(0) <= (congr_cl46_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu46_wayA_upd select + congr_cl46_wA_d(1) <= (congr_cl46_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu46_wayA_upd select + congr_cl46_wA_d(2) <= (congr_cl46_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu46_wayA_upd select + congr_cl46_wA_d(3) <= (congr_cl46_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu46_wayA_upd select + congr_cl46_wA_d(4) <= (congr_cl46_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu46_wayA_upd select + congr_cl46_wA_d(5) <= (congr_cl46_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu47_wayA_upd select + congr_cl47_wA_d(0) <= (congr_cl47_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu47_wayA_upd select + congr_cl47_wA_d(1) <= (congr_cl47_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu47_wayA_upd select + congr_cl47_wA_d(2) <= (congr_cl47_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu47_wayA_upd select + congr_cl47_wA_d(3) <= (congr_cl47_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu47_wayA_upd select + congr_cl47_wA_d(4) <= (congr_cl47_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu47_wayA_upd select + congr_cl47_wA_d(5) <= (congr_cl47_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu48_wayA_upd select + congr_cl48_wA_d(0) <= (congr_cl48_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu48_wayA_upd select + congr_cl48_wA_d(1) <= (congr_cl48_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu48_wayA_upd select + congr_cl48_wA_d(2) <= (congr_cl48_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu48_wayA_upd select + congr_cl48_wA_d(3) <= (congr_cl48_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu48_wayA_upd select + congr_cl48_wA_d(4) <= (congr_cl48_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu48_wayA_upd select + congr_cl48_wA_d(5) <= (congr_cl48_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu49_wayA_upd select + congr_cl49_wA_d(0) <= (congr_cl49_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu49_wayA_upd select + congr_cl49_wA_d(1) <= (congr_cl49_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu49_wayA_upd select + congr_cl49_wA_d(2) <= (congr_cl49_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu49_wayA_upd select + congr_cl49_wA_d(3) <= (congr_cl49_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu49_wayA_upd select + congr_cl49_wA_d(4) <= (congr_cl49_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu49_wayA_upd select + congr_cl49_wA_d(5) <= (congr_cl49_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu50_wayA_upd select + congr_cl50_wA_d(0) <= (congr_cl50_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu50_wayA_upd select + congr_cl50_wA_d(1) <= (congr_cl50_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu50_wayA_upd select + congr_cl50_wA_d(2) <= (congr_cl50_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu50_wayA_upd select + congr_cl50_wA_d(3) <= (congr_cl50_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu50_wayA_upd select + congr_cl50_wA_d(4) <= (congr_cl50_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu50_wayA_upd select + congr_cl50_wA_d(5) <= (congr_cl50_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu51_wayA_upd select + congr_cl51_wA_d(0) <= (congr_cl51_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu51_wayA_upd select + congr_cl51_wA_d(1) <= (congr_cl51_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu51_wayA_upd select + congr_cl51_wA_d(2) <= (congr_cl51_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu51_wayA_upd select + congr_cl51_wA_d(3) <= (congr_cl51_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu51_wayA_upd select + congr_cl51_wA_d(4) <= (congr_cl51_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu51_wayA_upd select + congr_cl51_wA_d(5) <= (congr_cl51_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu52_wayA_upd select + congr_cl52_wA_d(0) <= (congr_cl52_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu52_wayA_upd select + congr_cl52_wA_d(1) <= (congr_cl52_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu52_wayA_upd select + congr_cl52_wA_d(2) <= (congr_cl52_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu52_wayA_upd select + congr_cl52_wA_d(3) <= (congr_cl52_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu52_wayA_upd select + congr_cl52_wA_d(4) <= (congr_cl52_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu52_wayA_upd select + congr_cl52_wA_d(5) <= (congr_cl52_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu53_wayA_upd select + congr_cl53_wA_d(0) <= (congr_cl53_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu53_wayA_upd select + congr_cl53_wA_d(1) <= (congr_cl53_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu53_wayA_upd select + congr_cl53_wA_d(2) <= (congr_cl53_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu53_wayA_upd select + congr_cl53_wA_d(3) <= (congr_cl53_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu53_wayA_upd select + congr_cl53_wA_d(4) <= (congr_cl53_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu53_wayA_upd select + congr_cl53_wA_d(5) <= (congr_cl53_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu54_wayA_upd select + congr_cl54_wA_d(0) <= (congr_cl54_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu54_wayA_upd select + congr_cl54_wA_d(1) <= (congr_cl54_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu54_wayA_upd select + congr_cl54_wA_d(2) <= (congr_cl54_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu54_wayA_upd select + congr_cl54_wA_d(3) <= (congr_cl54_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu54_wayA_upd select + congr_cl54_wA_d(4) <= (congr_cl54_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu54_wayA_upd select + congr_cl54_wA_d(5) <= (congr_cl54_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu55_wayA_upd select + congr_cl55_wA_d(0) <= (congr_cl55_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu55_wayA_upd select + congr_cl55_wA_d(1) <= (congr_cl55_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu55_wayA_upd select + congr_cl55_wA_d(2) <= (congr_cl55_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu55_wayA_upd select + congr_cl55_wA_d(3) <= (congr_cl55_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu55_wayA_upd select + congr_cl55_wA_d(4) <= (congr_cl55_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu55_wayA_upd select + congr_cl55_wA_d(5) <= (congr_cl55_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu56_wayA_upd select + congr_cl56_wA_d(0) <= (congr_cl56_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu56_wayA_upd select + congr_cl56_wA_d(1) <= (congr_cl56_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu56_wayA_upd select + congr_cl56_wA_d(2) <= (congr_cl56_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu56_wayA_upd select + congr_cl56_wA_d(3) <= (congr_cl56_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu56_wayA_upd select + congr_cl56_wA_d(4) <= (congr_cl56_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu56_wayA_upd select + congr_cl56_wA_d(5) <= (congr_cl56_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu57_wayA_upd select + congr_cl57_wA_d(0) <= (congr_cl57_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu57_wayA_upd select + congr_cl57_wA_d(1) <= (congr_cl57_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu57_wayA_upd select + congr_cl57_wA_d(2) <= (congr_cl57_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu57_wayA_upd select + congr_cl57_wA_d(3) <= (congr_cl57_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu57_wayA_upd select + congr_cl57_wA_d(4) <= (congr_cl57_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu57_wayA_upd select + congr_cl57_wA_d(5) <= (congr_cl57_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu58_wayA_upd select + congr_cl58_wA_d(0) <= (congr_cl58_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu58_wayA_upd select + congr_cl58_wA_d(1) <= (congr_cl58_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu58_wayA_upd select + congr_cl58_wA_d(2) <= (congr_cl58_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu58_wayA_upd select + congr_cl58_wA_d(3) <= (congr_cl58_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu58_wayA_upd select + congr_cl58_wA_d(4) <= (congr_cl58_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu58_wayA_upd select + congr_cl58_wA_d(5) <= (congr_cl58_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu59_wayA_upd select + congr_cl59_wA_d(0) <= (congr_cl59_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu59_wayA_upd select + congr_cl59_wA_d(1) <= (congr_cl59_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu59_wayA_upd select + congr_cl59_wA_d(2) <= (congr_cl59_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu59_wayA_upd select + congr_cl59_wA_d(3) <= (congr_cl59_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu59_wayA_upd select + congr_cl59_wA_d(4) <= (congr_cl59_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu59_wayA_upd select + congr_cl59_wA_d(5) <= (congr_cl59_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu60_wayA_upd select + congr_cl60_wA_d(0) <= (congr_cl60_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu60_wayA_upd select + congr_cl60_wA_d(1) <= (congr_cl60_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu60_wayA_upd select + congr_cl60_wA_d(2) <= (congr_cl60_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu60_wayA_upd select + congr_cl60_wA_d(3) <= (congr_cl60_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu60_wayA_upd select + congr_cl60_wA_d(4) <= (congr_cl60_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu60_wayA_upd select + congr_cl60_wA_d(5) <= (congr_cl60_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu61_wayA_upd select + congr_cl61_wA_d(0) <= (congr_cl61_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu61_wayA_upd select + congr_cl61_wA_d(1) <= (congr_cl61_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu61_wayA_upd select + congr_cl61_wA_d(2) <= (congr_cl61_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu61_wayA_upd select + congr_cl61_wA_d(3) <= (congr_cl61_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu61_wayA_upd select + congr_cl61_wA_d(4) <= (congr_cl61_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu61_wayA_upd select + congr_cl61_wA_d(5) <= (congr_cl61_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu62_wayA_upd select + congr_cl62_wA_d(0) <= (congr_cl62_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu62_wayA_upd select + congr_cl62_wA_d(1) <= (congr_cl62_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu62_wayA_upd select + congr_cl62_wA_d(2) <= (congr_cl62_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu62_wayA_upd select + congr_cl62_wA_d(3) <= (congr_cl62_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu62_wayA_upd select + congr_cl62_wA_d(4) <= (congr_cl62_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu62_wayA_upd select + congr_cl62_wA_d(5) <= (congr_cl62_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu63_wayA_upd select + congr_cl63_wA_d(0) <= (congr_cl63_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu63_wayA_upd select + congr_cl63_wA_d(1) <= (congr_cl63_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +with rel_bixu63_wayA_upd select + congr_cl63_wA_d(2) <= (congr_cl63_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu63_wayA_upd select + congr_cl63_wA_d(3) <= (congr_cl63_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu63_wayA_upd select + congr_cl63_wA_d(4) <= (congr_cl63_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu63_wayA_upd select + congr_cl63_wA_d(5) <= (congr_cl63_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu0_wayB_upd select + congr_cl0_wB_d(0) <= (congr_cl0_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu0_wayB_upd select + congr_cl0_wB_d(1) <= (congr_cl0_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu0_wayB_upd select + congr_cl0_wB_d(2) <= (congr_cl0_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu0_wayB_upd select + congr_cl0_wB_d(3) <= (congr_cl0_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu0_wayB_upd select + congr_cl0_wB_d(4) <= (congr_cl0_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu0_wayB_upd select + congr_cl0_wB_d(5) <= (congr_cl0_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu1_wayB_upd select + congr_cl1_wB_d(0) <= (congr_cl1_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu1_wayB_upd select + congr_cl1_wB_d(1) <= (congr_cl1_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu1_wayB_upd select + congr_cl1_wB_d(2) <= (congr_cl1_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu1_wayB_upd select + congr_cl1_wB_d(3) <= (congr_cl1_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu1_wayB_upd select + congr_cl1_wB_d(4) <= (congr_cl1_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu1_wayB_upd select + congr_cl1_wB_d(5) <= (congr_cl1_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu2_wayB_upd select + congr_cl2_wB_d(0) <= (congr_cl2_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu2_wayB_upd select + congr_cl2_wB_d(1) <= (congr_cl2_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu2_wayB_upd select + congr_cl2_wB_d(2) <= (congr_cl2_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu2_wayB_upd select + congr_cl2_wB_d(3) <= (congr_cl2_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu2_wayB_upd select + congr_cl2_wB_d(4) <= (congr_cl2_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu2_wayB_upd select + congr_cl2_wB_d(5) <= (congr_cl2_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu3_wayB_upd select + congr_cl3_wB_d(0) <= (congr_cl3_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu3_wayB_upd select + congr_cl3_wB_d(1) <= (congr_cl3_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu3_wayB_upd select + congr_cl3_wB_d(2) <= (congr_cl3_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu3_wayB_upd select + congr_cl3_wB_d(3) <= (congr_cl3_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu3_wayB_upd select + congr_cl3_wB_d(4) <= (congr_cl3_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu3_wayB_upd select + congr_cl3_wB_d(5) <= (congr_cl3_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu4_wayB_upd select + congr_cl4_wB_d(0) <= (congr_cl4_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu4_wayB_upd select + congr_cl4_wB_d(1) <= (congr_cl4_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu4_wayB_upd select + congr_cl4_wB_d(2) <= (congr_cl4_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu4_wayB_upd select + congr_cl4_wB_d(3) <= (congr_cl4_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu4_wayB_upd select + congr_cl4_wB_d(4) <= (congr_cl4_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu4_wayB_upd select + congr_cl4_wB_d(5) <= (congr_cl4_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu5_wayB_upd select + congr_cl5_wB_d(0) <= (congr_cl5_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu5_wayB_upd select + congr_cl5_wB_d(1) <= (congr_cl5_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu5_wayB_upd select + congr_cl5_wB_d(2) <= (congr_cl5_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu5_wayB_upd select + congr_cl5_wB_d(3) <= (congr_cl5_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu5_wayB_upd select + congr_cl5_wB_d(4) <= (congr_cl5_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu5_wayB_upd select + congr_cl5_wB_d(5) <= (congr_cl5_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu6_wayB_upd select + congr_cl6_wB_d(0) <= (congr_cl6_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu6_wayB_upd select + congr_cl6_wB_d(1) <= (congr_cl6_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu6_wayB_upd select + congr_cl6_wB_d(2) <= (congr_cl6_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu6_wayB_upd select + congr_cl6_wB_d(3) <= (congr_cl6_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu6_wayB_upd select + congr_cl6_wB_d(4) <= (congr_cl6_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu6_wayB_upd select + congr_cl6_wB_d(5) <= (congr_cl6_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu7_wayB_upd select + congr_cl7_wB_d(0) <= (congr_cl7_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu7_wayB_upd select + congr_cl7_wB_d(1) <= (congr_cl7_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu7_wayB_upd select + congr_cl7_wB_d(2) <= (congr_cl7_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu7_wayB_upd select + congr_cl7_wB_d(3) <= (congr_cl7_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu7_wayB_upd select + congr_cl7_wB_d(4) <= (congr_cl7_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu7_wayB_upd select + congr_cl7_wB_d(5) <= (congr_cl7_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu8_wayB_upd select + congr_cl8_wB_d(0) <= (congr_cl8_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu8_wayB_upd select + congr_cl8_wB_d(1) <= (congr_cl8_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu8_wayB_upd select + congr_cl8_wB_d(2) <= (congr_cl8_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu8_wayB_upd select + congr_cl8_wB_d(3) <= (congr_cl8_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu8_wayB_upd select + congr_cl8_wB_d(4) <= (congr_cl8_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu8_wayB_upd select + congr_cl8_wB_d(5) <= (congr_cl8_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu9_wayB_upd select + congr_cl9_wB_d(0) <= (congr_cl9_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu9_wayB_upd select + congr_cl9_wB_d(1) <= (congr_cl9_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu9_wayB_upd select + congr_cl9_wB_d(2) <= (congr_cl9_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu9_wayB_upd select + congr_cl9_wB_d(3) <= (congr_cl9_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu9_wayB_upd select + congr_cl9_wB_d(4) <= (congr_cl9_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu9_wayB_upd select + congr_cl9_wB_d(5) <= (congr_cl9_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu10_wayB_upd select + congr_cl10_wB_d(0) <= (congr_cl10_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu10_wayB_upd select + congr_cl10_wB_d(1) <= (congr_cl10_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu10_wayB_upd select + congr_cl10_wB_d(2) <= (congr_cl10_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu10_wayB_upd select + congr_cl10_wB_d(3) <= (congr_cl10_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu10_wayB_upd select + congr_cl10_wB_d(4) <= (congr_cl10_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu10_wayB_upd select + congr_cl10_wB_d(5) <= (congr_cl10_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu11_wayB_upd select + congr_cl11_wB_d(0) <= (congr_cl11_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu11_wayB_upd select + congr_cl11_wB_d(1) <= (congr_cl11_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu11_wayB_upd select + congr_cl11_wB_d(2) <= (congr_cl11_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu11_wayB_upd select + congr_cl11_wB_d(3) <= (congr_cl11_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu11_wayB_upd select + congr_cl11_wB_d(4) <= (congr_cl11_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu11_wayB_upd select + congr_cl11_wB_d(5) <= (congr_cl11_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu12_wayB_upd select + congr_cl12_wB_d(0) <= (congr_cl12_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu12_wayB_upd select + congr_cl12_wB_d(1) <= (congr_cl12_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu12_wayB_upd select + congr_cl12_wB_d(2) <= (congr_cl12_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu12_wayB_upd select + congr_cl12_wB_d(3) <= (congr_cl12_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu12_wayB_upd select + congr_cl12_wB_d(4) <= (congr_cl12_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu12_wayB_upd select + congr_cl12_wB_d(5) <= (congr_cl12_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu13_wayB_upd select + congr_cl13_wB_d(0) <= (congr_cl13_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu13_wayB_upd select + congr_cl13_wB_d(1) <= (congr_cl13_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu13_wayB_upd select + congr_cl13_wB_d(2) <= (congr_cl13_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu13_wayB_upd select + congr_cl13_wB_d(3) <= (congr_cl13_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu13_wayB_upd select + congr_cl13_wB_d(4) <= (congr_cl13_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu13_wayB_upd select + congr_cl13_wB_d(5) <= (congr_cl13_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu14_wayB_upd select + congr_cl14_wB_d(0) <= (congr_cl14_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu14_wayB_upd select + congr_cl14_wB_d(1) <= (congr_cl14_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu14_wayB_upd select + congr_cl14_wB_d(2) <= (congr_cl14_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu14_wayB_upd select + congr_cl14_wB_d(3) <= (congr_cl14_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu14_wayB_upd select + congr_cl14_wB_d(4) <= (congr_cl14_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu14_wayB_upd select + congr_cl14_wB_d(5) <= (congr_cl14_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu15_wayB_upd select + congr_cl15_wB_d(0) <= (congr_cl15_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu15_wayB_upd select + congr_cl15_wB_d(1) <= (congr_cl15_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu15_wayB_upd select + congr_cl15_wB_d(2) <= (congr_cl15_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu15_wayB_upd select + congr_cl15_wB_d(3) <= (congr_cl15_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu15_wayB_upd select + congr_cl15_wB_d(4) <= (congr_cl15_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu15_wayB_upd select + congr_cl15_wB_d(5) <= (congr_cl15_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu16_wayB_upd select + congr_cl16_wB_d(0) <= (congr_cl16_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu16_wayB_upd select + congr_cl16_wB_d(1) <= (congr_cl16_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu16_wayB_upd select + congr_cl16_wB_d(2) <= (congr_cl16_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu16_wayB_upd select + congr_cl16_wB_d(3) <= (congr_cl16_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu16_wayB_upd select + congr_cl16_wB_d(4) <= (congr_cl16_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu16_wayB_upd select + congr_cl16_wB_d(5) <= (congr_cl16_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu17_wayB_upd select + congr_cl17_wB_d(0) <= (congr_cl17_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu17_wayB_upd select + congr_cl17_wB_d(1) <= (congr_cl17_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu17_wayB_upd select + congr_cl17_wB_d(2) <= (congr_cl17_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu17_wayB_upd select + congr_cl17_wB_d(3) <= (congr_cl17_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu17_wayB_upd select + congr_cl17_wB_d(4) <= (congr_cl17_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu17_wayB_upd select + congr_cl17_wB_d(5) <= (congr_cl17_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu18_wayB_upd select + congr_cl18_wB_d(0) <= (congr_cl18_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu18_wayB_upd select + congr_cl18_wB_d(1) <= (congr_cl18_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu18_wayB_upd select + congr_cl18_wB_d(2) <= (congr_cl18_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu18_wayB_upd select + congr_cl18_wB_d(3) <= (congr_cl18_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu18_wayB_upd select + congr_cl18_wB_d(4) <= (congr_cl18_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu18_wayB_upd select + congr_cl18_wB_d(5) <= (congr_cl18_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu19_wayB_upd select + congr_cl19_wB_d(0) <= (congr_cl19_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu19_wayB_upd select + congr_cl19_wB_d(1) <= (congr_cl19_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu19_wayB_upd select + congr_cl19_wB_d(2) <= (congr_cl19_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu19_wayB_upd select + congr_cl19_wB_d(3) <= (congr_cl19_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu19_wayB_upd select + congr_cl19_wB_d(4) <= (congr_cl19_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu19_wayB_upd select + congr_cl19_wB_d(5) <= (congr_cl19_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu20_wayB_upd select + congr_cl20_wB_d(0) <= (congr_cl20_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu20_wayB_upd select + congr_cl20_wB_d(1) <= (congr_cl20_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu20_wayB_upd select + congr_cl20_wB_d(2) <= (congr_cl20_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu20_wayB_upd select + congr_cl20_wB_d(3) <= (congr_cl20_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu20_wayB_upd select + congr_cl20_wB_d(4) <= (congr_cl20_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu20_wayB_upd select + congr_cl20_wB_d(5) <= (congr_cl20_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu21_wayB_upd select + congr_cl21_wB_d(0) <= (congr_cl21_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu21_wayB_upd select + congr_cl21_wB_d(1) <= (congr_cl21_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu21_wayB_upd select + congr_cl21_wB_d(2) <= (congr_cl21_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu21_wayB_upd select + congr_cl21_wB_d(3) <= (congr_cl21_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu21_wayB_upd select + congr_cl21_wB_d(4) <= (congr_cl21_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu21_wayB_upd select + congr_cl21_wB_d(5) <= (congr_cl21_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu22_wayB_upd select + congr_cl22_wB_d(0) <= (congr_cl22_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu22_wayB_upd select + congr_cl22_wB_d(1) <= (congr_cl22_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu22_wayB_upd select + congr_cl22_wB_d(2) <= (congr_cl22_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu22_wayB_upd select + congr_cl22_wB_d(3) <= (congr_cl22_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu22_wayB_upd select + congr_cl22_wB_d(4) <= (congr_cl22_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu22_wayB_upd select + congr_cl22_wB_d(5) <= (congr_cl22_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu23_wayB_upd select + congr_cl23_wB_d(0) <= (congr_cl23_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu23_wayB_upd select + congr_cl23_wB_d(1) <= (congr_cl23_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu23_wayB_upd select + congr_cl23_wB_d(2) <= (congr_cl23_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu23_wayB_upd select + congr_cl23_wB_d(3) <= (congr_cl23_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu23_wayB_upd select + congr_cl23_wB_d(4) <= (congr_cl23_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu23_wayB_upd select + congr_cl23_wB_d(5) <= (congr_cl23_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu24_wayB_upd select + congr_cl24_wB_d(0) <= (congr_cl24_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu24_wayB_upd select + congr_cl24_wB_d(1) <= (congr_cl24_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu24_wayB_upd select + congr_cl24_wB_d(2) <= (congr_cl24_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu24_wayB_upd select + congr_cl24_wB_d(3) <= (congr_cl24_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu24_wayB_upd select + congr_cl24_wB_d(4) <= (congr_cl24_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu24_wayB_upd select + congr_cl24_wB_d(5) <= (congr_cl24_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu25_wayB_upd select + congr_cl25_wB_d(0) <= (congr_cl25_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu25_wayB_upd select + congr_cl25_wB_d(1) <= (congr_cl25_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu25_wayB_upd select + congr_cl25_wB_d(2) <= (congr_cl25_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu25_wayB_upd select + congr_cl25_wB_d(3) <= (congr_cl25_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu25_wayB_upd select + congr_cl25_wB_d(4) <= (congr_cl25_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu25_wayB_upd select + congr_cl25_wB_d(5) <= (congr_cl25_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu26_wayB_upd select + congr_cl26_wB_d(0) <= (congr_cl26_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu26_wayB_upd select + congr_cl26_wB_d(1) <= (congr_cl26_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu26_wayB_upd select + congr_cl26_wB_d(2) <= (congr_cl26_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu26_wayB_upd select + congr_cl26_wB_d(3) <= (congr_cl26_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu26_wayB_upd select + congr_cl26_wB_d(4) <= (congr_cl26_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu26_wayB_upd select + congr_cl26_wB_d(5) <= (congr_cl26_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu27_wayB_upd select + congr_cl27_wB_d(0) <= (congr_cl27_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu27_wayB_upd select + congr_cl27_wB_d(1) <= (congr_cl27_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu27_wayB_upd select + congr_cl27_wB_d(2) <= (congr_cl27_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu27_wayB_upd select + congr_cl27_wB_d(3) <= (congr_cl27_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu27_wayB_upd select + congr_cl27_wB_d(4) <= (congr_cl27_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu27_wayB_upd select + congr_cl27_wB_d(5) <= (congr_cl27_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu28_wayB_upd select + congr_cl28_wB_d(0) <= (congr_cl28_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu28_wayB_upd select + congr_cl28_wB_d(1) <= (congr_cl28_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu28_wayB_upd select + congr_cl28_wB_d(2) <= (congr_cl28_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu28_wayB_upd select + congr_cl28_wB_d(3) <= (congr_cl28_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu28_wayB_upd select + congr_cl28_wB_d(4) <= (congr_cl28_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu28_wayB_upd select + congr_cl28_wB_d(5) <= (congr_cl28_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu29_wayB_upd select + congr_cl29_wB_d(0) <= (congr_cl29_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu29_wayB_upd select + congr_cl29_wB_d(1) <= (congr_cl29_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu29_wayB_upd select + congr_cl29_wB_d(2) <= (congr_cl29_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu29_wayB_upd select + congr_cl29_wB_d(3) <= (congr_cl29_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu29_wayB_upd select + congr_cl29_wB_d(4) <= (congr_cl29_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu29_wayB_upd select + congr_cl29_wB_d(5) <= (congr_cl29_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu30_wayB_upd select + congr_cl30_wB_d(0) <= (congr_cl30_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu30_wayB_upd select + congr_cl30_wB_d(1) <= (congr_cl30_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu30_wayB_upd select + congr_cl30_wB_d(2) <= (congr_cl30_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu30_wayB_upd select + congr_cl30_wB_d(3) <= (congr_cl30_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu30_wayB_upd select + congr_cl30_wB_d(4) <= (congr_cl30_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu30_wayB_upd select + congr_cl30_wB_d(5) <= (congr_cl30_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu31_wayB_upd select + congr_cl31_wB_d(0) <= (congr_cl31_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu31_wayB_upd select + congr_cl31_wB_d(1) <= (congr_cl31_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu31_wayB_upd select + congr_cl31_wB_d(2) <= (congr_cl31_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu31_wayB_upd select + congr_cl31_wB_d(3) <= (congr_cl31_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu31_wayB_upd select + congr_cl31_wB_d(4) <= (congr_cl31_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu31_wayB_upd select + congr_cl31_wB_d(5) <= (congr_cl31_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu32_wayB_upd select + congr_cl32_wB_d(0) <= (congr_cl32_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu32_wayB_upd select + congr_cl32_wB_d(1) <= (congr_cl32_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu32_wayB_upd select + congr_cl32_wB_d(2) <= (congr_cl32_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu32_wayB_upd select + congr_cl32_wB_d(3) <= (congr_cl32_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu32_wayB_upd select + congr_cl32_wB_d(4) <= (congr_cl32_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu32_wayB_upd select + congr_cl32_wB_d(5) <= (congr_cl32_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu33_wayB_upd select + congr_cl33_wB_d(0) <= (congr_cl33_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu33_wayB_upd select + congr_cl33_wB_d(1) <= (congr_cl33_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu33_wayB_upd select + congr_cl33_wB_d(2) <= (congr_cl33_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu33_wayB_upd select + congr_cl33_wB_d(3) <= (congr_cl33_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu33_wayB_upd select + congr_cl33_wB_d(4) <= (congr_cl33_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu33_wayB_upd select + congr_cl33_wB_d(5) <= (congr_cl33_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu34_wayB_upd select + congr_cl34_wB_d(0) <= (congr_cl34_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu34_wayB_upd select + congr_cl34_wB_d(1) <= (congr_cl34_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu34_wayB_upd select + congr_cl34_wB_d(2) <= (congr_cl34_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu34_wayB_upd select + congr_cl34_wB_d(3) <= (congr_cl34_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu34_wayB_upd select + congr_cl34_wB_d(4) <= (congr_cl34_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu34_wayB_upd select + congr_cl34_wB_d(5) <= (congr_cl34_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu35_wayB_upd select + congr_cl35_wB_d(0) <= (congr_cl35_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu35_wayB_upd select + congr_cl35_wB_d(1) <= (congr_cl35_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu35_wayB_upd select + congr_cl35_wB_d(2) <= (congr_cl35_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu35_wayB_upd select + congr_cl35_wB_d(3) <= (congr_cl35_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu35_wayB_upd select + congr_cl35_wB_d(4) <= (congr_cl35_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu35_wayB_upd select + congr_cl35_wB_d(5) <= (congr_cl35_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu36_wayB_upd select + congr_cl36_wB_d(0) <= (congr_cl36_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu36_wayB_upd select + congr_cl36_wB_d(1) <= (congr_cl36_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu36_wayB_upd select + congr_cl36_wB_d(2) <= (congr_cl36_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu36_wayB_upd select + congr_cl36_wB_d(3) <= (congr_cl36_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu36_wayB_upd select + congr_cl36_wB_d(4) <= (congr_cl36_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu36_wayB_upd select + congr_cl36_wB_d(5) <= (congr_cl36_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu37_wayB_upd select + congr_cl37_wB_d(0) <= (congr_cl37_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu37_wayB_upd select + congr_cl37_wB_d(1) <= (congr_cl37_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu37_wayB_upd select + congr_cl37_wB_d(2) <= (congr_cl37_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu37_wayB_upd select + congr_cl37_wB_d(3) <= (congr_cl37_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu37_wayB_upd select + congr_cl37_wB_d(4) <= (congr_cl37_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu37_wayB_upd select + congr_cl37_wB_d(5) <= (congr_cl37_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu38_wayB_upd select + congr_cl38_wB_d(0) <= (congr_cl38_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu38_wayB_upd select + congr_cl38_wB_d(1) <= (congr_cl38_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu38_wayB_upd select + congr_cl38_wB_d(2) <= (congr_cl38_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu38_wayB_upd select + congr_cl38_wB_d(3) <= (congr_cl38_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu38_wayB_upd select + congr_cl38_wB_d(4) <= (congr_cl38_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu38_wayB_upd select + congr_cl38_wB_d(5) <= (congr_cl38_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu39_wayB_upd select + congr_cl39_wB_d(0) <= (congr_cl39_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu39_wayB_upd select + congr_cl39_wB_d(1) <= (congr_cl39_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu39_wayB_upd select + congr_cl39_wB_d(2) <= (congr_cl39_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu39_wayB_upd select + congr_cl39_wB_d(3) <= (congr_cl39_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu39_wayB_upd select + congr_cl39_wB_d(4) <= (congr_cl39_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu39_wayB_upd select + congr_cl39_wB_d(5) <= (congr_cl39_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu40_wayB_upd select + congr_cl40_wB_d(0) <= (congr_cl40_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu40_wayB_upd select + congr_cl40_wB_d(1) <= (congr_cl40_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu40_wayB_upd select + congr_cl40_wB_d(2) <= (congr_cl40_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu40_wayB_upd select + congr_cl40_wB_d(3) <= (congr_cl40_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu40_wayB_upd select + congr_cl40_wB_d(4) <= (congr_cl40_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu40_wayB_upd select + congr_cl40_wB_d(5) <= (congr_cl40_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu41_wayB_upd select + congr_cl41_wB_d(0) <= (congr_cl41_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu41_wayB_upd select + congr_cl41_wB_d(1) <= (congr_cl41_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu41_wayB_upd select + congr_cl41_wB_d(2) <= (congr_cl41_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu41_wayB_upd select + congr_cl41_wB_d(3) <= (congr_cl41_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu41_wayB_upd select + congr_cl41_wB_d(4) <= (congr_cl41_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu41_wayB_upd select + congr_cl41_wB_d(5) <= (congr_cl41_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu42_wayB_upd select + congr_cl42_wB_d(0) <= (congr_cl42_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu42_wayB_upd select + congr_cl42_wB_d(1) <= (congr_cl42_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu42_wayB_upd select + congr_cl42_wB_d(2) <= (congr_cl42_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu42_wayB_upd select + congr_cl42_wB_d(3) <= (congr_cl42_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu42_wayB_upd select + congr_cl42_wB_d(4) <= (congr_cl42_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu42_wayB_upd select + congr_cl42_wB_d(5) <= (congr_cl42_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu43_wayB_upd select + congr_cl43_wB_d(0) <= (congr_cl43_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu43_wayB_upd select + congr_cl43_wB_d(1) <= (congr_cl43_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu43_wayB_upd select + congr_cl43_wB_d(2) <= (congr_cl43_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu43_wayB_upd select + congr_cl43_wB_d(3) <= (congr_cl43_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu43_wayB_upd select + congr_cl43_wB_d(4) <= (congr_cl43_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu43_wayB_upd select + congr_cl43_wB_d(5) <= (congr_cl43_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu44_wayB_upd select + congr_cl44_wB_d(0) <= (congr_cl44_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu44_wayB_upd select + congr_cl44_wB_d(1) <= (congr_cl44_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu44_wayB_upd select + congr_cl44_wB_d(2) <= (congr_cl44_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu44_wayB_upd select + congr_cl44_wB_d(3) <= (congr_cl44_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu44_wayB_upd select + congr_cl44_wB_d(4) <= (congr_cl44_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu44_wayB_upd select + congr_cl44_wB_d(5) <= (congr_cl44_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu45_wayB_upd select + congr_cl45_wB_d(0) <= (congr_cl45_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu45_wayB_upd select + congr_cl45_wB_d(1) <= (congr_cl45_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu45_wayB_upd select + congr_cl45_wB_d(2) <= (congr_cl45_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu45_wayB_upd select + congr_cl45_wB_d(3) <= (congr_cl45_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu45_wayB_upd select + congr_cl45_wB_d(4) <= (congr_cl45_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu45_wayB_upd select + congr_cl45_wB_d(5) <= (congr_cl45_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu46_wayB_upd select + congr_cl46_wB_d(0) <= (congr_cl46_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu46_wayB_upd select + congr_cl46_wB_d(1) <= (congr_cl46_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu46_wayB_upd select + congr_cl46_wB_d(2) <= (congr_cl46_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu46_wayB_upd select + congr_cl46_wB_d(3) <= (congr_cl46_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu46_wayB_upd select + congr_cl46_wB_d(4) <= (congr_cl46_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu46_wayB_upd select + congr_cl46_wB_d(5) <= (congr_cl46_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu47_wayB_upd select + congr_cl47_wB_d(0) <= (congr_cl47_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu47_wayB_upd select + congr_cl47_wB_d(1) <= (congr_cl47_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu47_wayB_upd select + congr_cl47_wB_d(2) <= (congr_cl47_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu47_wayB_upd select + congr_cl47_wB_d(3) <= (congr_cl47_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu47_wayB_upd select + congr_cl47_wB_d(4) <= (congr_cl47_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu47_wayB_upd select + congr_cl47_wB_d(5) <= (congr_cl47_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu48_wayB_upd select + congr_cl48_wB_d(0) <= (congr_cl48_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu48_wayB_upd select + congr_cl48_wB_d(1) <= (congr_cl48_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu48_wayB_upd select + congr_cl48_wB_d(2) <= (congr_cl48_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu48_wayB_upd select + congr_cl48_wB_d(3) <= (congr_cl48_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu48_wayB_upd select + congr_cl48_wB_d(4) <= (congr_cl48_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu48_wayB_upd select + congr_cl48_wB_d(5) <= (congr_cl48_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu49_wayB_upd select + congr_cl49_wB_d(0) <= (congr_cl49_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu49_wayB_upd select + congr_cl49_wB_d(1) <= (congr_cl49_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu49_wayB_upd select + congr_cl49_wB_d(2) <= (congr_cl49_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu49_wayB_upd select + congr_cl49_wB_d(3) <= (congr_cl49_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu49_wayB_upd select + congr_cl49_wB_d(4) <= (congr_cl49_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu49_wayB_upd select + congr_cl49_wB_d(5) <= (congr_cl49_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu50_wayB_upd select + congr_cl50_wB_d(0) <= (congr_cl50_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu50_wayB_upd select + congr_cl50_wB_d(1) <= (congr_cl50_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu50_wayB_upd select + congr_cl50_wB_d(2) <= (congr_cl50_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu50_wayB_upd select + congr_cl50_wB_d(3) <= (congr_cl50_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu50_wayB_upd select + congr_cl50_wB_d(4) <= (congr_cl50_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu50_wayB_upd select + congr_cl50_wB_d(5) <= (congr_cl50_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu51_wayB_upd select + congr_cl51_wB_d(0) <= (congr_cl51_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu51_wayB_upd select + congr_cl51_wB_d(1) <= (congr_cl51_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu51_wayB_upd select + congr_cl51_wB_d(2) <= (congr_cl51_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu51_wayB_upd select + congr_cl51_wB_d(3) <= (congr_cl51_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu51_wayB_upd select + congr_cl51_wB_d(4) <= (congr_cl51_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu51_wayB_upd select + congr_cl51_wB_d(5) <= (congr_cl51_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu52_wayB_upd select + congr_cl52_wB_d(0) <= (congr_cl52_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu52_wayB_upd select + congr_cl52_wB_d(1) <= (congr_cl52_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu52_wayB_upd select + congr_cl52_wB_d(2) <= (congr_cl52_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu52_wayB_upd select + congr_cl52_wB_d(3) <= (congr_cl52_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu52_wayB_upd select + congr_cl52_wB_d(4) <= (congr_cl52_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu52_wayB_upd select + congr_cl52_wB_d(5) <= (congr_cl52_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu53_wayB_upd select + congr_cl53_wB_d(0) <= (congr_cl53_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu53_wayB_upd select + congr_cl53_wB_d(1) <= (congr_cl53_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu53_wayB_upd select + congr_cl53_wB_d(2) <= (congr_cl53_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu53_wayB_upd select + congr_cl53_wB_d(3) <= (congr_cl53_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu53_wayB_upd select + congr_cl53_wB_d(4) <= (congr_cl53_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu53_wayB_upd select + congr_cl53_wB_d(5) <= (congr_cl53_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu54_wayB_upd select + congr_cl54_wB_d(0) <= (congr_cl54_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu54_wayB_upd select + congr_cl54_wB_d(1) <= (congr_cl54_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu54_wayB_upd select + congr_cl54_wB_d(2) <= (congr_cl54_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu54_wayB_upd select + congr_cl54_wB_d(3) <= (congr_cl54_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu54_wayB_upd select + congr_cl54_wB_d(4) <= (congr_cl54_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu54_wayB_upd select + congr_cl54_wB_d(5) <= (congr_cl54_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu55_wayB_upd select + congr_cl55_wB_d(0) <= (congr_cl55_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu55_wayB_upd select + congr_cl55_wB_d(1) <= (congr_cl55_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu55_wayB_upd select + congr_cl55_wB_d(2) <= (congr_cl55_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu55_wayB_upd select + congr_cl55_wB_d(3) <= (congr_cl55_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu55_wayB_upd select + congr_cl55_wB_d(4) <= (congr_cl55_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu55_wayB_upd select + congr_cl55_wB_d(5) <= (congr_cl55_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu56_wayB_upd select + congr_cl56_wB_d(0) <= (congr_cl56_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu56_wayB_upd select + congr_cl56_wB_d(1) <= (congr_cl56_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu56_wayB_upd select + congr_cl56_wB_d(2) <= (congr_cl56_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu56_wayB_upd select + congr_cl56_wB_d(3) <= (congr_cl56_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu56_wayB_upd select + congr_cl56_wB_d(4) <= (congr_cl56_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu56_wayB_upd select + congr_cl56_wB_d(5) <= (congr_cl56_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu57_wayB_upd select + congr_cl57_wB_d(0) <= (congr_cl57_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu57_wayB_upd select + congr_cl57_wB_d(1) <= (congr_cl57_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu57_wayB_upd select + congr_cl57_wB_d(2) <= (congr_cl57_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu57_wayB_upd select + congr_cl57_wB_d(3) <= (congr_cl57_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu57_wayB_upd select + congr_cl57_wB_d(4) <= (congr_cl57_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu57_wayB_upd select + congr_cl57_wB_d(5) <= (congr_cl57_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu58_wayB_upd select + congr_cl58_wB_d(0) <= (congr_cl58_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu58_wayB_upd select + congr_cl58_wB_d(1) <= (congr_cl58_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu58_wayB_upd select + congr_cl58_wB_d(2) <= (congr_cl58_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu58_wayB_upd select + congr_cl58_wB_d(3) <= (congr_cl58_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu58_wayB_upd select + congr_cl58_wB_d(4) <= (congr_cl58_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu58_wayB_upd select + congr_cl58_wB_d(5) <= (congr_cl58_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu59_wayB_upd select + congr_cl59_wB_d(0) <= (congr_cl59_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu59_wayB_upd select + congr_cl59_wB_d(1) <= (congr_cl59_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu59_wayB_upd select + congr_cl59_wB_d(2) <= (congr_cl59_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu59_wayB_upd select + congr_cl59_wB_d(3) <= (congr_cl59_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu59_wayB_upd select + congr_cl59_wB_d(4) <= (congr_cl59_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu59_wayB_upd select + congr_cl59_wB_d(5) <= (congr_cl59_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu60_wayB_upd select + congr_cl60_wB_d(0) <= (congr_cl60_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu60_wayB_upd select + congr_cl60_wB_d(1) <= (congr_cl60_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu60_wayB_upd select + congr_cl60_wB_d(2) <= (congr_cl60_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu60_wayB_upd select + congr_cl60_wB_d(3) <= (congr_cl60_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu60_wayB_upd select + congr_cl60_wB_d(4) <= (congr_cl60_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu60_wayB_upd select + congr_cl60_wB_d(5) <= (congr_cl60_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu61_wayB_upd select + congr_cl61_wB_d(0) <= (congr_cl61_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu61_wayB_upd select + congr_cl61_wB_d(1) <= (congr_cl61_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu61_wayB_upd select + congr_cl61_wB_d(2) <= (congr_cl61_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu61_wayB_upd select + congr_cl61_wB_d(3) <= (congr_cl61_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu61_wayB_upd select + congr_cl61_wB_d(4) <= (congr_cl61_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu61_wayB_upd select + congr_cl61_wB_d(5) <= (congr_cl61_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu62_wayB_upd select + congr_cl62_wB_d(0) <= (congr_cl62_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu62_wayB_upd select + congr_cl62_wB_d(1) <= (congr_cl62_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu62_wayB_upd select + congr_cl62_wB_d(2) <= (congr_cl62_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu62_wayB_upd select + congr_cl62_wB_d(3) <= (congr_cl62_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu62_wayB_upd select + congr_cl62_wB_d(4) <= (congr_cl62_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu62_wayB_upd select + congr_cl62_wB_d(5) <= (congr_cl62_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu63_wayB_upd select + congr_cl63_wB_d(0) <= (congr_cl63_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu63_wayB_upd select + congr_cl63_wB_d(1) <= (congr_cl63_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +with rel_bixu63_wayB_upd select + congr_cl63_wB_d(2) <= (congr_cl63_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu63_wayB_upd select + congr_cl63_wB_d(3) <= (congr_cl63_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu63_wayB_upd select + congr_cl63_wB_d(4) <= (congr_cl63_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu63_wayB_upd select + congr_cl63_wB_d(5) <= (congr_cl63_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu0_wayC_upd select + congr_cl0_wC_d(0) <= (congr_cl0_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu0_wayC_upd select + congr_cl0_wC_d(1) <= (congr_cl0_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu0_wayC_upd select + congr_cl0_wC_d(2) <= (congr_cl0_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu0_wayC_upd select + congr_cl0_wC_d(3) <= (congr_cl0_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu0_wayC_upd select + congr_cl0_wC_d(4) <= (congr_cl0_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu0_wayC_upd select + congr_cl0_wC_d(5) <= (congr_cl0_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu1_wayC_upd select + congr_cl1_wC_d(0) <= (congr_cl1_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu1_wayC_upd select + congr_cl1_wC_d(1) <= (congr_cl1_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu1_wayC_upd select + congr_cl1_wC_d(2) <= (congr_cl1_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu1_wayC_upd select + congr_cl1_wC_d(3) <= (congr_cl1_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu1_wayC_upd select + congr_cl1_wC_d(4) <= (congr_cl1_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu1_wayC_upd select + congr_cl1_wC_d(5) <= (congr_cl1_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu2_wayC_upd select + congr_cl2_wC_d(0) <= (congr_cl2_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu2_wayC_upd select + congr_cl2_wC_d(1) <= (congr_cl2_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu2_wayC_upd select + congr_cl2_wC_d(2) <= (congr_cl2_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu2_wayC_upd select + congr_cl2_wC_d(3) <= (congr_cl2_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu2_wayC_upd select + congr_cl2_wC_d(4) <= (congr_cl2_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu2_wayC_upd select + congr_cl2_wC_d(5) <= (congr_cl2_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu3_wayC_upd select + congr_cl3_wC_d(0) <= (congr_cl3_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu3_wayC_upd select + congr_cl3_wC_d(1) <= (congr_cl3_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu3_wayC_upd select + congr_cl3_wC_d(2) <= (congr_cl3_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu3_wayC_upd select + congr_cl3_wC_d(3) <= (congr_cl3_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu3_wayC_upd select + congr_cl3_wC_d(4) <= (congr_cl3_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu3_wayC_upd select + congr_cl3_wC_d(5) <= (congr_cl3_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu4_wayC_upd select + congr_cl4_wC_d(0) <= (congr_cl4_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu4_wayC_upd select + congr_cl4_wC_d(1) <= (congr_cl4_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu4_wayC_upd select + congr_cl4_wC_d(2) <= (congr_cl4_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu4_wayC_upd select + congr_cl4_wC_d(3) <= (congr_cl4_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu4_wayC_upd select + congr_cl4_wC_d(4) <= (congr_cl4_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu4_wayC_upd select + congr_cl4_wC_d(5) <= (congr_cl4_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu5_wayC_upd select + congr_cl5_wC_d(0) <= (congr_cl5_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu5_wayC_upd select + congr_cl5_wC_d(1) <= (congr_cl5_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu5_wayC_upd select + congr_cl5_wC_d(2) <= (congr_cl5_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu5_wayC_upd select + congr_cl5_wC_d(3) <= (congr_cl5_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu5_wayC_upd select + congr_cl5_wC_d(4) <= (congr_cl5_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu5_wayC_upd select + congr_cl5_wC_d(5) <= (congr_cl5_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu6_wayC_upd select + congr_cl6_wC_d(0) <= (congr_cl6_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu6_wayC_upd select + congr_cl6_wC_d(1) <= (congr_cl6_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu6_wayC_upd select + congr_cl6_wC_d(2) <= (congr_cl6_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu6_wayC_upd select + congr_cl6_wC_d(3) <= (congr_cl6_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu6_wayC_upd select + congr_cl6_wC_d(4) <= (congr_cl6_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu6_wayC_upd select + congr_cl6_wC_d(5) <= (congr_cl6_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu7_wayC_upd select + congr_cl7_wC_d(0) <= (congr_cl7_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu7_wayC_upd select + congr_cl7_wC_d(1) <= (congr_cl7_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu7_wayC_upd select + congr_cl7_wC_d(2) <= (congr_cl7_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu7_wayC_upd select + congr_cl7_wC_d(3) <= (congr_cl7_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu7_wayC_upd select + congr_cl7_wC_d(4) <= (congr_cl7_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu7_wayC_upd select + congr_cl7_wC_d(5) <= (congr_cl7_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu8_wayC_upd select + congr_cl8_wC_d(0) <= (congr_cl8_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu8_wayC_upd select + congr_cl8_wC_d(1) <= (congr_cl8_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu8_wayC_upd select + congr_cl8_wC_d(2) <= (congr_cl8_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu8_wayC_upd select + congr_cl8_wC_d(3) <= (congr_cl8_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu8_wayC_upd select + congr_cl8_wC_d(4) <= (congr_cl8_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu8_wayC_upd select + congr_cl8_wC_d(5) <= (congr_cl8_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu9_wayC_upd select + congr_cl9_wC_d(0) <= (congr_cl9_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu9_wayC_upd select + congr_cl9_wC_d(1) <= (congr_cl9_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu9_wayC_upd select + congr_cl9_wC_d(2) <= (congr_cl9_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu9_wayC_upd select + congr_cl9_wC_d(3) <= (congr_cl9_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu9_wayC_upd select + congr_cl9_wC_d(4) <= (congr_cl9_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu9_wayC_upd select + congr_cl9_wC_d(5) <= (congr_cl9_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu10_wayC_upd select + congr_cl10_wC_d(0) <= (congr_cl10_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu10_wayC_upd select + congr_cl10_wC_d(1) <= (congr_cl10_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu10_wayC_upd select + congr_cl10_wC_d(2) <= (congr_cl10_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu10_wayC_upd select + congr_cl10_wC_d(3) <= (congr_cl10_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu10_wayC_upd select + congr_cl10_wC_d(4) <= (congr_cl10_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu10_wayC_upd select + congr_cl10_wC_d(5) <= (congr_cl10_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu11_wayC_upd select + congr_cl11_wC_d(0) <= (congr_cl11_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu11_wayC_upd select + congr_cl11_wC_d(1) <= (congr_cl11_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu11_wayC_upd select + congr_cl11_wC_d(2) <= (congr_cl11_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu11_wayC_upd select + congr_cl11_wC_d(3) <= (congr_cl11_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu11_wayC_upd select + congr_cl11_wC_d(4) <= (congr_cl11_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu11_wayC_upd select + congr_cl11_wC_d(5) <= (congr_cl11_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu12_wayC_upd select + congr_cl12_wC_d(0) <= (congr_cl12_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu12_wayC_upd select + congr_cl12_wC_d(1) <= (congr_cl12_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu12_wayC_upd select + congr_cl12_wC_d(2) <= (congr_cl12_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu12_wayC_upd select + congr_cl12_wC_d(3) <= (congr_cl12_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu12_wayC_upd select + congr_cl12_wC_d(4) <= (congr_cl12_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu12_wayC_upd select + congr_cl12_wC_d(5) <= (congr_cl12_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu13_wayC_upd select + congr_cl13_wC_d(0) <= (congr_cl13_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu13_wayC_upd select + congr_cl13_wC_d(1) <= (congr_cl13_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu13_wayC_upd select + congr_cl13_wC_d(2) <= (congr_cl13_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu13_wayC_upd select + congr_cl13_wC_d(3) <= (congr_cl13_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu13_wayC_upd select + congr_cl13_wC_d(4) <= (congr_cl13_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu13_wayC_upd select + congr_cl13_wC_d(5) <= (congr_cl13_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu14_wayC_upd select + congr_cl14_wC_d(0) <= (congr_cl14_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu14_wayC_upd select + congr_cl14_wC_d(1) <= (congr_cl14_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu14_wayC_upd select + congr_cl14_wC_d(2) <= (congr_cl14_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu14_wayC_upd select + congr_cl14_wC_d(3) <= (congr_cl14_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu14_wayC_upd select + congr_cl14_wC_d(4) <= (congr_cl14_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu14_wayC_upd select + congr_cl14_wC_d(5) <= (congr_cl14_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu15_wayC_upd select + congr_cl15_wC_d(0) <= (congr_cl15_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu15_wayC_upd select + congr_cl15_wC_d(1) <= (congr_cl15_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu15_wayC_upd select + congr_cl15_wC_d(2) <= (congr_cl15_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu15_wayC_upd select + congr_cl15_wC_d(3) <= (congr_cl15_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu15_wayC_upd select + congr_cl15_wC_d(4) <= (congr_cl15_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu15_wayC_upd select + congr_cl15_wC_d(5) <= (congr_cl15_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu16_wayC_upd select + congr_cl16_wC_d(0) <= (congr_cl16_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu16_wayC_upd select + congr_cl16_wC_d(1) <= (congr_cl16_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu16_wayC_upd select + congr_cl16_wC_d(2) <= (congr_cl16_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu16_wayC_upd select + congr_cl16_wC_d(3) <= (congr_cl16_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu16_wayC_upd select + congr_cl16_wC_d(4) <= (congr_cl16_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu16_wayC_upd select + congr_cl16_wC_d(5) <= (congr_cl16_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu17_wayC_upd select + congr_cl17_wC_d(0) <= (congr_cl17_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu17_wayC_upd select + congr_cl17_wC_d(1) <= (congr_cl17_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu17_wayC_upd select + congr_cl17_wC_d(2) <= (congr_cl17_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu17_wayC_upd select + congr_cl17_wC_d(3) <= (congr_cl17_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu17_wayC_upd select + congr_cl17_wC_d(4) <= (congr_cl17_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu17_wayC_upd select + congr_cl17_wC_d(5) <= (congr_cl17_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu18_wayC_upd select + congr_cl18_wC_d(0) <= (congr_cl18_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu18_wayC_upd select + congr_cl18_wC_d(1) <= (congr_cl18_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu18_wayC_upd select + congr_cl18_wC_d(2) <= (congr_cl18_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu18_wayC_upd select + congr_cl18_wC_d(3) <= (congr_cl18_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu18_wayC_upd select + congr_cl18_wC_d(4) <= (congr_cl18_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu18_wayC_upd select + congr_cl18_wC_d(5) <= (congr_cl18_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu19_wayC_upd select + congr_cl19_wC_d(0) <= (congr_cl19_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu19_wayC_upd select + congr_cl19_wC_d(1) <= (congr_cl19_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu19_wayC_upd select + congr_cl19_wC_d(2) <= (congr_cl19_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu19_wayC_upd select + congr_cl19_wC_d(3) <= (congr_cl19_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu19_wayC_upd select + congr_cl19_wC_d(4) <= (congr_cl19_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu19_wayC_upd select + congr_cl19_wC_d(5) <= (congr_cl19_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu20_wayC_upd select + congr_cl20_wC_d(0) <= (congr_cl20_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu20_wayC_upd select + congr_cl20_wC_d(1) <= (congr_cl20_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu20_wayC_upd select + congr_cl20_wC_d(2) <= (congr_cl20_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu20_wayC_upd select + congr_cl20_wC_d(3) <= (congr_cl20_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu20_wayC_upd select + congr_cl20_wC_d(4) <= (congr_cl20_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu20_wayC_upd select + congr_cl20_wC_d(5) <= (congr_cl20_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu21_wayC_upd select + congr_cl21_wC_d(0) <= (congr_cl21_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu21_wayC_upd select + congr_cl21_wC_d(1) <= (congr_cl21_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu21_wayC_upd select + congr_cl21_wC_d(2) <= (congr_cl21_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu21_wayC_upd select + congr_cl21_wC_d(3) <= (congr_cl21_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu21_wayC_upd select + congr_cl21_wC_d(4) <= (congr_cl21_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu21_wayC_upd select + congr_cl21_wC_d(5) <= (congr_cl21_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu22_wayC_upd select + congr_cl22_wC_d(0) <= (congr_cl22_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu22_wayC_upd select + congr_cl22_wC_d(1) <= (congr_cl22_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu22_wayC_upd select + congr_cl22_wC_d(2) <= (congr_cl22_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu22_wayC_upd select + congr_cl22_wC_d(3) <= (congr_cl22_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu22_wayC_upd select + congr_cl22_wC_d(4) <= (congr_cl22_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu22_wayC_upd select + congr_cl22_wC_d(5) <= (congr_cl22_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu23_wayC_upd select + congr_cl23_wC_d(0) <= (congr_cl23_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu23_wayC_upd select + congr_cl23_wC_d(1) <= (congr_cl23_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu23_wayC_upd select + congr_cl23_wC_d(2) <= (congr_cl23_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu23_wayC_upd select + congr_cl23_wC_d(3) <= (congr_cl23_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu23_wayC_upd select + congr_cl23_wC_d(4) <= (congr_cl23_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu23_wayC_upd select + congr_cl23_wC_d(5) <= (congr_cl23_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu24_wayC_upd select + congr_cl24_wC_d(0) <= (congr_cl24_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu24_wayC_upd select + congr_cl24_wC_d(1) <= (congr_cl24_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu24_wayC_upd select + congr_cl24_wC_d(2) <= (congr_cl24_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu24_wayC_upd select + congr_cl24_wC_d(3) <= (congr_cl24_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu24_wayC_upd select + congr_cl24_wC_d(4) <= (congr_cl24_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu24_wayC_upd select + congr_cl24_wC_d(5) <= (congr_cl24_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu25_wayC_upd select + congr_cl25_wC_d(0) <= (congr_cl25_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu25_wayC_upd select + congr_cl25_wC_d(1) <= (congr_cl25_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu25_wayC_upd select + congr_cl25_wC_d(2) <= (congr_cl25_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu25_wayC_upd select + congr_cl25_wC_d(3) <= (congr_cl25_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu25_wayC_upd select + congr_cl25_wC_d(4) <= (congr_cl25_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu25_wayC_upd select + congr_cl25_wC_d(5) <= (congr_cl25_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu26_wayC_upd select + congr_cl26_wC_d(0) <= (congr_cl26_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu26_wayC_upd select + congr_cl26_wC_d(1) <= (congr_cl26_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu26_wayC_upd select + congr_cl26_wC_d(2) <= (congr_cl26_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu26_wayC_upd select + congr_cl26_wC_d(3) <= (congr_cl26_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu26_wayC_upd select + congr_cl26_wC_d(4) <= (congr_cl26_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu26_wayC_upd select + congr_cl26_wC_d(5) <= (congr_cl26_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu27_wayC_upd select + congr_cl27_wC_d(0) <= (congr_cl27_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu27_wayC_upd select + congr_cl27_wC_d(1) <= (congr_cl27_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu27_wayC_upd select + congr_cl27_wC_d(2) <= (congr_cl27_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu27_wayC_upd select + congr_cl27_wC_d(3) <= (congr_cl27_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu27_wayC_upd select + congr_cl27_wC_d(4) <= (congr_cl27_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu27_wayC_upd select + congr_cl27_wC_d(5) <= (congr_cl27_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu28_wayC_upd select + congr_cl28_wC_d(0) <= (congr_cl28_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu28_wayC_upd select + congr_cl28_wC_d(1) <= (congr_cl28_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu28_wayC_upd select + congr_cl28_wC_d(2) <= (congr_cl28_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu28_wayC_upd select + congr_cl28_wC_d(3) <= (congr_cl28_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu28_wayC_upd select + congr_cl28_wC_d(4) <= (congr_cl28_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu28_wayC_upd select + congr_cl28_wC_d(5) <= (congr_cl28_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu29_wayC_upd select + congr_cl29_wC_d(0) <= (congr_cl29_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu29_wayC_upd select + congr_cl29_wC_d(1) <= (congr_cl29_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu29_wayC_upd select + congr_cl29_wC_d(2) <= (congr_cl29_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu29_wayC_upd select + congr_cl29_wC_d(3) <= (congr_cl29_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu29_wayC_upd select + congr_cl29_wC_d(4) <= (congr_cl29_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu29_wayC_upd select + congr_cl29_wC_d(5) <= (congr_cl29_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu30_wayC_upd select + congr_cl30_wC_d(0) <= (congr_cl30_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu30_wayC_upd select + congr_cl30_wC_d(1) <= (congr_cl30_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu30_wayC_upd select + congr_cl30_wC_d(2) <= (congr_cl30_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu30_wayC_upd select + congr_cl30_wC_d(3) <= (congr_cl30_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu30_wayC_upd select + congr_cl30_wC_d(4) <= (congr_cl30_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu30_wayC_upd select + congr_cl30_wC_d(5) <= (congr_cl30_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu31_wayC_upd select + congr_cl31_wC_d(0) <= (congr_cl31_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu31_wayC_upd select + congr_cl31_wC_d(1) <= (congr_cl31_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu31_wayC_upd select + congr_cl31_wC_d(2) <= (congr_cl31_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu31_wayC_upd select + congr_cl31_wC_d(3) <= (congr_cl31_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu31_wayC_upd select + congr_cl31_wC_d(4) <= (congr_cl31_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu31_wayC_upd select + congr_cl31_wC_d(5) <= (congr_cl31_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu32_wayC_upd select + congr_cl32_wC_d(0) <= (congr_cl32_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu32_wayC_upd select + congr_cl32_wC_d(1) <= (congr_cl32_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu32_wayC_upd select + congr_cl32_wC_d(2) <= (congr_cl32_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu32_wayC_upd select + congr_cl32_wC_d(3) <= (congr_cl32_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu32_wayC_upd select + congr_cl32_wC_d(4) <= (congr_cl32_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu32_wayC_upd select + congr_cl32_wC_d(5) <= (congr_cl32_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu33_wayC_upd select + congr_cl33_wC_d(0) <= (congr_cl33_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu33_wayC_upd select + congr_cl33_wC_d(1) <= (congr_cl33_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu33_wayC_upd select + congr_cl33_wC_d(2) <= (congr_cl33_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu33_wayC_upd select + congr_cl33_wC_d(3) <= (congr_cl33_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu33_wayC_upd select + congr_cl33_wC_d(4) <= (congr_cl33_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu33_wayC_upd select + congr_cl33_wC_d(5) <= (congr_cl33_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu34_wayC_upd select + congr_cl34_wC_d(0) <= (congr_cl34_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu34_wayC_upd select + congr_cl34_wC_d(1) <= (congr_cl34_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu34_wayC_upd select + congr_cl34_wC_d(2) <= (congr_cl34_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu34_wayC_upd select + congr_cl34_wC_d(3) <= (congr_cl34_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu34_wayC_upd select + congr_cl34_wC_d(4) <= (congr_cl34_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu34_wayC_upd select + congr_cl34_wC_d(5) <= (congr_cl34_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu35_wayC_upd select + congr_cl35_wC_d(0) <= (congr_cl35_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu35_wayC_upd select + congr_cl35_wC_d(1) <= (congr_cl35_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu35_wayC_upd select + congr_cl35_wC_d(2) <= (congr_cl35_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu35_wayC_upd select + congr_cl35_wC_d(3) <= (congr_cl35_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu35_wayC_upd select + congr_cl35_wC_d(4) <= (congr_cl35_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu35_wayC_upd select + congr_cl35_wC_d(5) <= (congr_cl35_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu36_wayC_upd select + congr_cl36_wC_d(0) <= (congr_cl36_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu36_wayC_upd select + congr_cl36_wC_d(1) <= (congr_cl36_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu36_wayC_upd select + congr_cl36_wC_d(2) <= (congr_cl36_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu36_wayC_upd select + congr_cl36_wC_d(3) <= (congr_cl36_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu36_wayC_upd select + congr_cl36_wC_d(4) <= (congr_cl36_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu36_wayC_upd select + congr_cl36_wC_d(5) <= (congr_cl36_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu37_wayC_upd select + congr_cl37_wC_d(0) <= (congr_cl37_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu37_wayC_upd select + congr_cl37_wC_d(1) <= (congr_cl37_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu37_wayC_upd select + congr_cl37_wC_d(2) <= (congr_cl37_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu37_wayC_upd select + congr_cl37_wC_d(3) <= (congr_cl37_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu37_wayC_upd select + congr_cl37_wC_d(4) <= (congr_cl37_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu37_wayC_upd select + congr_cl37_wC_d(5) <= (congr_cl37_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu38_wayC_upd select + congr_cl38_wC_d(0) <= (congr_cl38_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu38_wayC_upd select + congr_cl38_wC_d(1) <= (congr_cl38_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu38_wayC_upd select + congr_cl38_wC_d(2) <= (congr_cl38_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu38_wayC_upd select + congr_cl38_wC_d(3) <= (congr_cl38_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu38_wayC_upd select + congr_cl38_wC_d(4) <= (congr_cl38_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu38_wayC_upd select + congr_cl38_wC_d(5) <= (congr_cl38_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu39_wayC_upd select + congr_cl39_wC_d(0) <= (congr_cl39_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu39_wayC_upd select + congr_cl39_wC_d(1) <= (congr_cl39_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu39_wayC_upd select + congr_cl39_wC_d(2) <= (congr_cl39_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu39_wayC_upd select + congr_cl39_wC_d(3) <= (congr_cl39_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu39_wayC_upd select + congr_cl39_wC_d(4) <= (congr_cl39_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu39_wayC_upd select + congr_cl39_wC_d(5) <= (congr_cl39_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu40_wayC_upd select + congr_cl40_wC_d(0) <= (congr_cl40_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu40_wayC_upd select + congr_cl40_wC_d(1) <= (congr_cl40_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu40_wayC_upd select + congr_cl40_wC_d(2) <= (congr_cl40_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu40_wayC_upd select + congr_cl40_wC_d(3) <= (congr_cl40_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu40_wayC_upd select + congr_cl40_wC_d(4) <= (congr_cl40_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu40_wayC_upd select + congr_cl40_wC_d(5) <= (congr_cl40_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu41_wayC_upd select + congr_cl41_wC_d(0) <= (congr_cl41_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu41_wayC_upd select + congr_cl41_wC_d(1) <= (congr_cl41_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu41_wayC_upd select + congr_cl41_wC_d(2) <= (congr_cl41_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu41_wayC_upd select + congr_cl41_wC_d(3) <= (congr_cl41_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu41_wayC_upd select + congr_cl41_wC_d(4) <= (congr_cl41_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu41_wayC_upd select + congr_cl41_wC_d(5) <= (congr_cl41_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu42_wayC_upd select + congr_cl42_wC_d(0) <= (congr_cl42_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu42_wayC_upd select + congr_cl42_wC_d(1) <= (congr_cl42_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu42_wayC_upd select + congr_cl42_wC_d(2) <= (congr_cl42_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu42_wayC_upd select + congr_cl42_wC_d(3) <= (congr_cl42_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu42_wayC_upd select + congr_cl42_wC_d(4) <= (congr_cl42_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu42_wayC_upd select + congr_cl42_wC_d(5) <= (congr_cl42_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu43_wayC_upd select + congr_cl43_wC_d(0) <= (congr_cl43_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu43_wayC_upd select + congr_cl43_wC_d(1) <= (congr_cl43_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu43_wayC_upd select + congr_cl43_wC_d(2) <= (congr_cl43_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu43_wayC_upd select + congr_cl43_wC_d(3) <= (congr_cl43_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu43_wayC_upd select + congr_cl43_wC_d(4) <= (congr_cl43_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu43_wayC_upd select + congr_cl43_wC_d(5) <= (congr_cl43_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu44_wayC_upd select + congr_cl44_wC_d(0) <= (congr_cl44_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu44_wayC_upd select + congr_cl44_wC_d(1) <= (congr_cl44_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu44_wayC_upd select + congr_cl44_wC_d(2) <= (congr_cl44_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu44_wayC_upd select + congr_cl44_wC_d(3) <= (congr_cl44_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu44_wayC_upd select + congr_cl44_wC_d(4) <= (congr_cl44_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu44_wayC_upd select + congr_cl44_wC_d(5) <= (congr_cl44_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu45_wayC_upd select + congr_cl45_wC_d(0) <= (congr_cl45_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu45_wayC_upd select + congr_cl45_wC_d(1) <= (congr_cl45_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu45_wayC_upd select + congr_cl45_wC_d(2) <= (congr_cl45_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu45_wayC_upd select + congr_cl45_wC_d(3) <= (congr_cl45_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu45_wayC_upd select + congr_cl45_wC_d(4) <= (congr_cl45_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu45_wayC_upd select + congr_cl45_wC_d(5) <= (congr_cl45_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu46_wayC_upd select + congr_cl46_wC_d(0) <= (congr_cl46_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu46_wayC_upd select + congr_cl46_wC_d(1) <= (congr_cl46_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu46_wayC_upd select + congr_cl46_wC_d(2) <= (congr_cl46_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu46_wayC_upd select + congr_cl46_wC_d(3) <= (congr_cl46_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu46_wayC_upd select + congr_cl46_wC_d(4) <= (congr_cl46_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu46_wayC_upd select + congr_cl46_wC_d(5) <= (congr_cl46_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu47_wayC_upd select + congr_cl47_wC_d(0) <= (congr_cl47_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu47_wayC_upd select + congr_cl47_wC_d(1) <= (congr_cl47_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu47_wayC_upd select + congr_cl47_wC_d(2) <= (congr_cl47_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu47_wayC_upd select + congr_cl47_wC_d(3) <= (congr_cl47_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu47_wayC_upd select + congr_cl47_wC_d(4) <= (congr_cl47_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu47_wayC_upd select + congr_cl47_wC_d(5) <= (congr_cl47_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu48_wayC_upd select + congr_cl48_wC_d(0) <= (congr_cl48_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu48_wayC_upd select + congr_cl48_wC_d(1) <= (congr_cl48_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu48_wayC_upd select + congr_cl48_wC_d(2) <= (congr_cl48_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu48_wayC_upd select + congr_cl48_wC_d(3) <= (congr_cl48_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu48_wayC_upd select + congr_cl48_wC_d(4) <= (congr_cl48_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu48_wayC_upd select + congr_cl48_wC_d(5) <= (congr_cl48_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu49_wayC_upd select + congr_cl49_wC_d(0) <= (congr_cl49_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu49_wayC_upd select + congr_cl49_wC_d(1) <= (congr_cl49_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu49_wayC_upd select + congr_cl49_wC_d(2) <= (congr_cl49_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu49_wayC_upd select + congr_cl49_wC_d(3) <= (congr_cl49_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu49_wayC_upd select + congr_cl49_wC_d(4) <= (congr_cl49_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu49_wayC_upd select + congr_cl49_wC_d(5) <= (congr_cl49_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu50_wayC_upd select + congr_cl50_wC_d(0) <= (congr_cl50_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu50_wayC_upd select + congr_cl50_wC_d(1) <= (congr_cl50_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu50_wayC_upd select + congr_cl50_wC_d(2) <= (congr_cl50_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu50_wayC_upd select + congr_cl50_wC_d(3) <= (congr_cl50_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu50_wayC_upd select + congr_cl50_wC_d(4) <= (congr_cl50_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu50_wayC_upd select + congr_cl50_wC_d(5) <= (congr_cl50_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu51_wayC_upd select + congr_cl51_wC_d(0) <= (congr_cl51_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu51_wayC_upd select + congr_cl51_wC_d(1) <= (congr_cl51_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu51_wayC_upd select + congr_cl51_wC_d(2) <= (congr_cl51_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu51_wayC_upd select + congr_cl51_wC_d(3) <= (congr_cl51_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu51_wayC_upd select + congr_cl51_wC_d(4) <= (congr_cl51_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu51_wayC_upd select + congr_cl51_wC_d(5) <= (congr_cl51_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu52_wayC_upd select + congr_cl52_wC_d(0) <= (congr_cl52_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu52_wayC_upd select + congr_cl52_wC_d(1) <= (congr_cl52_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu52_wayC_upd select + congr_cl52_wC_d(2) <= (congr_cl52_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu52_wayC_upd select + congr_cl52_wC_d(3) <= (congr_cl52_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu52_wayC_upd select + congr_cl52_wC_d(4) <= (congr_cl52_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu52_wayC_upd select + congr_cl52_wC_d(5) <= (congr_cl52_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu53_wayC_upd select + congr_cl53_wC_d(0) <= (congr_cl53_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu53_wayC_upd select + congr_cl53_wC_d(1) <= (congr_cl53_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu53_wayC_upd select + congr_cl53_wC_d(2) <= (congr_cl53_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu53_wayC_upd select + congr_cl53_wC_d(3) <= (congr_cl53_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu53_wayC_upd select + congr_cl53_wC_d(4) <= (congr_cl53_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu53_wayC_upd select + congr_cl53_wC_d(5) <= (congr_cl53_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu54_wayC_upd select + congr_cl54_wC_d(0) <= (congr_cl54_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu54_wayC_upd select + congr_cl54_wC_d(1) <= (congr_cl54_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu54_wayC_upd select + congr_cl54_wC_d(2) <= (congr_cl54_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu54_wayC_upd select + congr_cl54_wC_d(3) <= (congr_cl54_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu54_wayC_upd select + congr_cl54_wC_d(4) <= (congr_cl54_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu54_wayC_upd select + congr_cl54_wC_d(5) <= (congr_cl54_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu55_wayC_upd select + congr_cl55_wC_d(0) <= (congr_cl55_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu55_wayC_upd select + congr_cl55_wC_d(1) <= (congr_cl55_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu55_wayC_upd select + congr_cl55_wC_d(2) <= (congr_cl55_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu55_wayC_upd select + congr_cl55_wC_d(3) <= (congr_cl55_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu55_wayC_upd select + congr_cl55_wC_d(4) <= (congr_cl55_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu55_wayC_upd select + congr_cl55_wC_d(5) <= (congr_cl55_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu56_wayC_upd select + congr_cl56_wC_d(0) <= (congr_cl56_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu56_wayC_upd select + congr_cl56_wC_d(1) <= (congr_cl56_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu56_wayC_upd select + congr_cl56_wC_d(2) <= (congr_cl56_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu56_wayC_upd select + congr_cl56_wC_d(3) <= (congr_cl56_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu56_wayC_upd select + congr_cl56_wC_d(4) <= (congr_cl56_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu56_wayC_upd select + congr_cl56_wC_d(5) <= (congr_cl56_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu57_wayC_upd select + congr_cl57_wC_d(0) <= (congr_cl57_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu57_wayC_upd select + congr_cl57_wC_d(1) <= (congr_cl57_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu57_wayC_upd select + congr_cl57_wC_d(2) <= (congr_cl57_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu57_wayC_upd select + congr_cl57_wC_d(3) <= (congr_cl57_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu57_wayC_upd select + congr_cl57_wC_d(4) <= (congr_cl57_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu57_wayC_upd select + congr_cl57_wC_d(5) <= (congr_cl57_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu58_wayC_upd select + congr_cl58_wC_d(0) <= (congr_cl58_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu58_wayC_upd select + congr_cl58_wC_d(1) <= (congr_cl58_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu58_wayC_upd select + congr_cl58_wC_d(2) <= (congr_cl58_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu58_wayC_upd select + congr_cl58_wC_d(3) <= (congr_cl58_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu58_wayC_upd select + congr_cl58_wC_d(4) <= (congr_cl58_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu58_wayC_upd select + congr_cl58_wC_d(5) <= (congr_cl58_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu59_wayC_upd select + congr_cl59_wC_d(0) <= (congr_cl59_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu59_wayC_upd select + congr_cl59_wC_d(1) <= (congr_cl59_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu59_wayC_upd select + congr_cl59_wC_d(2) <= (congr_cl59_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu59_wayC_upd select + congr_cl59_wC_d(3) <= (congr_cl59_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu59_wayC_upd select + congr_cl59_wC_d(4) <= (congr_cl59_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu59_wayC_upd select + congr_cl59_wC_d(5) <= (congr_cl59_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu60_wayC_upd select + congr_cl60_wC_d(0) <= (congr_cl60_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu60_wayC_upd select + congr_cl60_wC_d(1) <= (congr_cl60_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu60_wayC_upd select + congr_cl60_wC_d(2) <= (congr_cl60_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu60_wayC_upd select + congr_cl60_wC_d(3) <= (congr_cl60_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu60_wayC_upd select + congr_cl60_wC_d(4) <= (congr_cl60_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu60_wayC_upd select + congr_cl60_wC_d(5) <= (congr_cl60_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu61_wayC_upd select + congr_cl61_wC_d(0) <= (congr_cl61_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu61_wayC_upd select + congr_cl61_wC_d(1) <= (congr_cl61_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu61_wayC_upd select + congr_cl61_wC_d(2) <= (congr_cl61_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu61_wayC_upd select + congr_cl61_wC_d(3) <= (congr_cl61_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu61_wayC_upd select + congr_cl61_wC_d(4) <= (congr_cl61_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu61_wayC_upd select + congr_cl61_wC_d(5) <= (congr_cl61_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu62_wayC_upd select + congr_cl62_wC_d(0) <= (congr_cl62_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu62_wayC_upd select + congr_cl62_wC_d(1) <= (congr_cl62_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu62_wayC_upd select + congr_cl62_wC_d(2) <= (congr_cl62_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu62_wayC_upd select + congr_cl62_wC_d(3) <= (congr_cl62_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu62_wayC_upd select + congr_cl62_wC_d(4) <= (congr_cl62_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu62_wayC_upd select + congr_cl62_wC_d(5) <= (congr_cl62_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu63_wayC_upd select + congr_cl63_wC_d(0) <= (congr_cl63_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu63_wayC_upd select + congr_cl63_wC_d(1) <= (congr_cl63_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +with rel_bixu63_wayC_upd select + congr_cl63_wC_d(2) <= (congr_cl63_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu63_wayC_upd select + congr_cl63_wC_d(3) <= (congr_cl63_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu63_wayC_upd select + congr_cl63_wC_d(4) <= (congr_cl63_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu63_wayC_upd select + congr_cl63_wC_d(5) <= (congr_cl63_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu0_wayD_upd select + congr_cl0_wD_d(0) <= (congr_cl0_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu0_wayD_upd select + congr_cl0_wD_d(1) <= (congr_cl0_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu0_wayD_upd select + congr_cl0_wD_d(2) <= (congr_cl0_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu0_wayD_upd select + congr_cl0_wD_d(3) <= (congr_cl0_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu0_wayD_upd select + congr_cl0_wD_d(4) <= (congr_cl0_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu0_wayD_upd select + congr_cl0_wD_d(5) <= (congr_cl0_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu1_wayD_upd select + congr_cl1_wD_d(0) <= (congr_cl1_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu1_wayD_upd select + congr_cl1_wD_d(1) <= (congr_cl1_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu1_wayD_upd select + congr_cl1_wD_d(2) <= (congr_cl1_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu1_wayD_upd select + congr_cl1_wD_d(3) <= (congr_cl1_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu1_wayD_upd select + congr_cl1_wD_d(4) <= (congr_cl1_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu1_wayD_upd select + congr_cl1_wD_d(5) <= (congr_cl1_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu2_wayD_upd select + congr_cl2_wD_d(0) <= (congr_cl2_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu2_wayD_upd select + congr_cl2_wD_d(1) <= (congr_cl2_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu2_wayD_upd select + congr_cl2_wD_d(2) <= (congr_cl2_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu2_wayD_upd select + congr_cl2_wD_d(3) <= (congr_cl2_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu2_wayD_upd select + congr_cl2_wD_d(4) <= (congr_cl2_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu2_wayD_upd select + congr_cl2_wD_d(5) <= (congr_cl2_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu3_wayD_upd select + congr_cl3_wD_d(0) <= (congr_cl3_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu3_wayD_upd select + congr_cl3_wD_d(1) <= (congr_cl3_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu3_wayD_upd select + congr_cl3_wD_d(2) <= (congr_cl3_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu3_wayD_upd select + congr_cl3_wD_d(3) <= (congr_cl3_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu3_wayD_upd select + congr_cl3_wD_d(4) <= (congr_cl3_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu3_wayD_upd select + congr_cl3_wD_d(5) <= (congr_cl3_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu4_wayD_upd select + congr_cl4_wD_d(0) <= (congr_cl4_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu4_wayD_upd select + congr_cl4_wD_d(1) <= (congr_cl4_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu4_wayD_upd select + congr_cl4_wD_d(2) <= (congr_cl4_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu4_wayD_upd select + congr_cl4_wD_d(3) <= (congr_cl4_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu4_wayD_upd select + congr_cl4_wD_d(4) <= (congr_cl4_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu4_wayD_upd select + congr_cl4_wD_d(5) <= (congr_cl4_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu5_wayD_upd select + congr_cl5_wD_d(0) <= (congr_cl5_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu5_wayD_upd select + congr_cl5_wD_d(1) <= (congr_cl5_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu5_wayD_upd select + congr_cl5_wD_d(2) <= (congr_cl5_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu5_wayD_upd select + congr_cl5_wD_d(3) <= (congr_cl5_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu5_wayD_upd select + congr_cl5_wD_d(4) <= (congr_cl5_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu5_wayD_upd select + congr_cl5_wD_d(5) <= (congr_cl5_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu6_wayD_upd select + congr_cl6_wD_d(0) <= (congr_cl6_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu6_wayD_upd select + congr_cl6_wD_d(1) <= (congr_cl6_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu6_wayD_upd select + congr_cl6_wD_d(2) <= (congr_cl6_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu6_wayD_upd select + congr_cl6_wD_d(3) <= (congr_cl6_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu6_wayD_upd select + congr_cl6_wD_d(4) <= (congr_cl6_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu6_wayD_upd select + congr_cl6_wD_d(5) <= (congr_cl6_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu7_wayD_upd select + congr_cl7_wD_d(0) <= (congr_cl7_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu7_wayD_upd select + congr_cl7_wD_d(1) <= (congr_cl7_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu7_wayD_upd select + congr_cl7_wD_d(2) <= (congr_cl7_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu7_wayD_upd select + congr_cl7_wD_d(3) <= (congr_cl7_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu7_wayD_upd select + congr_cl7_wD_d(4) <= (congr_cl7_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu7_wayD_upd select + congr_cl7_wD_d(5) <= (congr_cl7_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu8_wayD_upd select + congr_cl8_wD_d(0) <= (congr_cl8_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu8_wayD_upd select + congr_cl8_wD_d(1) <= (congr_cl8_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu8_wayD_upd select + congr_cl8_wD_d(2) <= (congr_cl8_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu8_wayD_upd select + congr_cl8_wD_d(3) <= (congr_cl8_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu8_wayD_upd select + congr_cl8_wD_d(4) <= (congr_cl8_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu8_wayD_upd select + congr_cl8_wD_d(5) <= (congr_cl8_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu9_wayD_upd select + congr_cl9_wD_d(0) <= (congr_cl9_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu9_wayD_upd select + congr_cl9_wD_d(1) <= (congr_cl9_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu9_wayD_upd select + congr_cl9_wD_d(2) <= (congr_cl9_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu9_wayD_upd select + congr_cl9_wD_d(3) <= (congr_cl9_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu9_wayD_upd select + congr_cl9_wD_d(4) <= (congr_cl9_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu9_wayD_upd select + congr_cl9_wD_d(5) <= (congr_cl9_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu10_wayD_upd select + congr_cl10_wD_d(0) <= (congr_cl10_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu10_wayD_upd select + congr_cl10_wD_d(1) <= (congr_cl10_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu10_wayD_upd select + congr_cl10_wD_d(2) <= (congr_cl10_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu10_wayD_upd select + congr_cl10_wD_d(3) <= (congr_cl10_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu10_wayD_upd select + congr_cl10_wD_d(4) <= (congr_cl10_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu10_wayD_upd select + congr_cl10_wD_d(5) <= (congr_cl10_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu11_wayD_upd select + congr_cl11_wD_d(0) <= (congr_cl11_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu11_wayD_upd select + congr_cl11_wD_d(1) <= (congr_cl11_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu11_wayD_upd select + congr_cl11_wD_d(2) <= (congr_cl11_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu11_wayD_upd select + congr_cl11_wD_d(3) <= (congr_cl11_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu11_wayD_upd select + congr_cl11_wD_d(4) <= (congr_cl11_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu11_wayD_upd select + congr_cl11_wD_d(5) <= (congr_cl11_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu12_wayD_upd select + congr_cl12_wD_d(0) <= (congr_cl12_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu12_wayD_upd select + congr_cl12_wD_d(1) <= (congr_cl12_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu12_wayD_upd select + congr_cl12_wD_d(2) <= (congr_cl12_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu12_wayD_upd select + congr_cl12_wD_d(3) <= (congr_cl12_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu12_wayD_upd select + congr_cl12_wD_d(4) <= (congr_cl12_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu12_wayD_upd select + congr_cl12_wD_d(5) <= (congr_cl12_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu13_wayD_upd select + congr_cl13_wD_d(0) <= (congr_cl13_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu13_wayD_upd select + congr_cl13_wD_d(1) <= (congr_cl13_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu13_wayD_upd select + congr_cl13_wD_d(2) <= (congr_cl13_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu13_wayD_upd select + congr_cl13_wD_d(3) <= (congr_cl13_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu13_wayD_upd select + congr_cl13_wD_d(4) <= (congr_cl13_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu13_wayD_upd select + congr_cl13_wD_d(5) <= (congr_cl13_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu14_wayD_upd select + congr_cl14_wD_d(0) <= (congr_cl14_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu14_wayD_upd select + congr_cl14_wD_d(1) <= (congr_cl14_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu14_wayD_upd select + congr_cl14_wD_d(2) <= (congr_cl14_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu14_wayD_upd select + congr_cl14_wD_d(3) <= (congr_cl14_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu14_wayD_upd select + congr_cl14_wD_d(4) <= (congr_cl14_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu14_wayD_upd select + congr_cl14_wD_d(5) <= (congr_cl14_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu15_wayD_upd select + congr_cl15_wD_d(0) <= (congr_cl15_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu15_wayD_upd select + congr_cl15_wD_d(1) <= (congr_cl15_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu15_wayD_upd select + congr_cl15_wD_d(2) <= (congr_cl15_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu15_wayD_upd select + congr_cl15_wD_d(3) <= (congr_cl15_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu15_wayD_upd select + congr_cl15_wD_d(4) <= (congr_cl15_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu15_wayD_upd select + congr_cl15_wD_d(5) <= (congr_cl15_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu16_wayD_upd select + congr_cl16_wD_d(0) <= (congr_cl16_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu16_wayD_upd select + congr_cl16_wD_d(1) <= (congr_cl16_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu16_wayD_upd select + congr_cl16_wD_d(2) <= (congr_cl16_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu16_wayD_upd select + congr_cl16_wD_d(3) <= (congr_cl16_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu16_wayD_upd select + congr_cl16_wD_d(4) <= (congr_cl16_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu16_wayD_upd select + congr_cl16_wD_d(5) <= (congr_cl16_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu17_wayD_upd select + congr_cl17_wD_d(0) <= (congr_cl17_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu17_wayD_upd select + congr_cl17_wD_d(1) <= (congr_cl17_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu17_wayD_upd select + congr_cl17_wD_d(2) <= (congr_cl17_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu17_wayD_upd select + congr_cl17_wD_d(3) <= (congr_cl17_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu17_wayD_upd select + congr_cl17_wD_d(4) <= (congr_cl17_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu17_wayD_upd select + congr_cl17_wD_d(5) <= (congr_cl17_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu18_wayD_upd select + congr_cl18_wD_d(0) <= (congr_cl18_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu18_wayD_upd select + congr_cl18_wD_d(1) <= (congr_cl18_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu18_wayD_upd select + congr_cl18_wD_d(2) <= (congr_cl18_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu18_wayD_upd select + congr_cl18_wD_d(3) <= (congr_cl18_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu18_wayD_upd select + congr_cl18_wD_d(4) <= (congr_cl18_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu18_wayD_upd select + congr_cl18_wD_d(5) <= (congr_cl18_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu19_wayD_upd select + congr_cl19_wD_d(0) <= (congr_cl19_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu19_wayD_upd select + congr_cl19_wD_d(1) <= (congr_cl19_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu19_wayD_upd select + congr_cl19_wD_d(2) <= (congr_cl19_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu19_wayD_upd select + congr_cl19_wD_d(3) <= (congr_cl19_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu19_wayD_upd select + congr_cl19_wD_d(4) <= (congr_cl19_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu19_wayD_upd select + congr_cl19_wD_d(5) <= (congr_cl19_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu20_wayD_upd select + congr_cl20_wD_d(0) <= (congr_cl20_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu20_wayD_upd select + congr_cl20_wD_d(1) <= (congr_cl20_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu20_wayD_upd select + congr_cl20_wD_d(2) <= (congr_cl20_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu20_wayD_upd select + congr_cl20_wD_d(3) <= (congr_cl20_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu20_wayD_upd select + congr_cl20_wD_d(4) <= (congr_cl20_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu20_wayD_upd select + congr_cl20_wD_d(5) <= (congr_cl20_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu21_wayD_upd select + congr_cl21_wD_d(0) <= (congr_cl21_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu21_wayD_upd select + congr_cl21_wD_d(1) <= (congr_cl21_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu21_wayD_upd select + congr_cl21_wD_d(2) <= (congr_cl21_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu21_wayD_upd select + congr_cl21_wD_d(3) <= (congr_cl21_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu21_wayD_upd select + congr_cl21_wD_d(4) <= (congr_cl21_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu21_wayD_upd select + congr_cl21_wD_d(5) <= (congr_cl21_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu22_wayD_upd select + congr_cl22_wD_d(0) <= (congr_cl22_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu22_wayD_upd select + congr_cl22_wD_d(1) <= (congr_cl22_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu22_wayD_upd select + congr_cl22_wD_d(2) <= (congr_cl22_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu22_wayD_upd select + congr_cl22_wD_d(3) <= (congr_cl22_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu22_wayD_upd select + congr_cl22_wD_d(4) <= (congr_cl22_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu22_wayD_upd select + congr_cl22_wD_d(5) <= (congr_cl22_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu23_wayD_upd select + congr_cl23_wD_d(0) <= (congr_cl23_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu23_wayD_upd select + congr_cl23_wD_d(1) <= (congr_cl23_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu23_wayD_upd select + congr_cl23_wD_d(2) <= (congr_cl23_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu23_wayD_upd select + congr_cl23_wD_d(3) <= (congr_cl23_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu23_wayD_upd select + congr_cl23_wD_d(4) <= (congr_cl23_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu23_wayD_upd select + congr_cl23_wD_d(5) <= (congr_cl23_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu24_wayD_upd select + congr_cl24_wD_d(0) <= (congr_cl24_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu24_wayD_upd select + congr_cl24_wD_d(1) <= (congr_cl24_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu24_wayD_upd select + congr_cl24_wD_d(2) <= (congr_cl24_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu24_wayD_upd select + congr_cl24_wD_d(3) <= (congr_cl24_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu24_wayD_upd select + congr_cl24_wD_d(4) <= (congr_cl24_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu24_wayD_upd select + congr_cl24_wD_d(5) <= (congr_cl24_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu25_wayD_upd select + congr_cl25_wD_d(0) <= (congr_cl25_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu25_wayD_upd select + congr_cl25_wD_d(1) <= (congr_cl25_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu25_wayD_upd select + congr_cl25_wD_d(2) <= (congr_cl25_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu25_wayD_upd select + congr_cl25_wD_d(3) <= (congr_cl25_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu25_wayD_upd select + congr_cl25_wD_d(4) <= (congr_cl25_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu25_wayD_upd select + congr_cl25_wD_d(5) <= (congr_cl25_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu26_wayD_upd select + congr_cl26_wD_d(0) <= (congr_cl26_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu26_wayD_upd select + congr_cl26_wD_d(1) <= (congr_cl26_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu26_wayD_upd select + congr_cl26_wD_d(2) <= (congr_cl26_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu26_wayD_upd select + congr_cl26_wD_d(3) <= (congr_cl26_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu26_wayD_upd select + congr_cl26_wD_d(4) <= (congr_cl26_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu26_wayD_upd select + congr_cl26_wD_d(5) <= (congr_cl26_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu27_wayD_upd select + congr_cl27_wD_d(0) <= (congr_cl27_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu27_wayD_upd select + congr_cl27_wD_d(1) <= (congr_cl27_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu27_wayD_upd select + congr_cl27_wD_d(2) <= (congr_cl27_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu27_wayD_upd select + congr_cl27_wD_d(3) <= (congr_cl27_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu27_wayD_upd select + congr_cl27_wD_d(4) <= (congr_cl27_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu27_wayD_upd select + congr_cl27_wD_d(5) <= (congr_cl27_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu28_wayD_upd select + congr_cl28_wD_d(0) <= (congr_cl28_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu28_wayD_upd select + congr_cl28_wD_d(1) <= (congr_cl28_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu28_wayD_upd select + congr_cl28_wD_d(2) <= (congr_cl28_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu28_wayD_upd select + congr_cl28_wD_d(3) <= (congr_cl28_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu28_wayD_upd select + congr_cl28_wD_d(4) <= (congr_cl28_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu28_wayD_upd select + congr_cl28_wD_d(5) <= (congr_cl28_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu29_wayD_upd select + congr_cl29_wD_d(0) <= (congr_cl29_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu29_wayD_upd select + congr_cl29_wD_d(1) <= (congr_cl29_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu29_wayD_upd select + congr_cl29_wD_d(2) <= (congr_cl29_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu29_wayD_upd select + congr_cl29_wD_d(3) <= (congr_cl29_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu29_wayD_upd select + congr_cl29_wD_d(4) <= (congr_cl29_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu29_wayD_upd select + congr_cl29_wD_d(5) <= (congr_cl29_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu30_wayD_upd select + congr_cl30_wD_d(0) <= (congr_cl30_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu30_wayD_upd select + congr_cl30_wD_d(1) <= (congr_cl30_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu30_wayD_upd select + congr_cl30_wD_d(2) <= (congr_cl30_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu30_wayD_upd select + congr_cl30_wD_d(3) <= (congr_cl30_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu30_wayD_upd select + congr_cl30_wD_d(4) <= (congr_cl30_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu30_wayD_upd select + congr_cl30_wD_d(5) <= (congr_cl30_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu31_wayD_upd select + congr_cl31_wD_d(0) <= (congr_cl31_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu31_wayD_upd select + congr_cl31_wD_d(1) <= (congr_cl31_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu31_wayD_upd select + congr_cl31_wD_d(2) <= (congr_cl31_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu31_wayD_upd select + congr_cl31_wD_d(3) <= (congr_cl31_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu31_wayD_upd select + congr_cl31_wD_d(4) <= (congr_cl31_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu31_wayD_upd select + congr_cl31_wD_d(5) <= (congr_cl31_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu32_wayD_upd select + congr_cl32_wD_d(0) <= (congr_cl32_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu32_wayD_upd select + congr_cl32_wD_d(1) <= (congr_cl32_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu32_wayD_upd select + congr_cl32_wD_d(2) <= (congr_cl32_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu32_wayD_upd select + congr_cl32_wD_d(3) <= (congr_cl32_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu32_wayD_upd select + congr_cl32_wD_d(4) <= (congr_cl32_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu32_wayD_upd select + congr_cl32_wD_d(5) <= (congr_cl32_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu33_wayD_upd select + congr_cl33_wD_d(0) <= (congr_cl33_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu33_wayD_upd select + congr_cl33_wD_d(1) <= (congr_cl33_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu33_wayD_upd select + congr_cl33_wD_d(2) <= (congr_cl33_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu33_wayD_upd select + congr_cl33_wD_d(3) <= (congr_cl33_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu33_wayD_upd select + congr_cl33_wD_d(4) <= (congr_cl33_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu33_wayD_upd select + congr_cl33_wD_d(5) <= (congr_cl33_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu34_wayD_upd select + congr_cl34_wD_d(0) <= (congr_cl34_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu34_wayD_upd select + congr_cl34_wD_d(1) <= (congr_cl34_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu34_wayD_upd select + congr_cl34_wD_d(2) <= (congr_cl34_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu34_wayD_upd select + congr_cl34_wD_d(3) <= (congr_cl34_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu34_wayD_upd select + congr_cl34_wD_d(4) <= (congr_cl34_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu34_wayD_upd select + congr_cl34_wD_d(5) <= (congr_cl34_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu35_wayD_upd select + congr_cl35_wD_d(0) <= (congr_cl35_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu35_wayD_upd select + congr_cl35_wD_d(1) <= (congr_cl35_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu35_wayD_upd select + congr_cl35_wD_d(2) <= (congr_cl35_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu35_wayD_upd select + congr_cl35_wD_d(3) <= (congr_cl35_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu35_wayD_upd select + congr_cl35_wD_d(4) <= (congr_cl35_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu35_wayD_upd select + congr_cl35_wD_d(5) <= (congr_cl35_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu36_wayD_upd select + congr_cl36_wD_d(0) <= (congr_cl36_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu36_wayD_upd select + congr_cl36_wD_d(1) <= (congr_cl36_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu36_wayD_upd select + congr_cl36_wD_d(2) <= (congr_cl36_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu36_wayD_upd select + congr_cl36_wD_d(3) <= (congr_cl36_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu36_wayD_upd select + congr_cl36_wD_d(4) <= (congr_cl36_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu36_wayD_upd select + congr_cl36_wD_d(5) <= (congr_cl36_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu37_wayD_upd select + congr_cl37_wD_d(0) <= (congr_cl37_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu37_wayD_upd select + congr_cl37_wD_d(1) <= (congr_cl37_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu37_wayD_upd select + congr_cl37_wD_d(2) <= (congr_cl37_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu37_wayD_upd select + congr_cl37_wD_d(3) <= (congr_cl37_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu37_wayD_upd select + congr_cl37_wD_d(4) <= (congr_cl37_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu37_wayD_upd select + congr_cl37_wD_d(5) <= (congr_cl37_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu38_wayD_upd select + congr_cl38_wD_d(0) <= (congr_cl38_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu38_wayD_upd select + congr_cl38_wD_d(1) <= (congr_cl38_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu38_wayD_upd select + congr_cl38_wD_d(2) <= (congr_cl38_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu38_wayD_upd select + congr_cl38_wD_d(3) <= (congr_cl38_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu38_wayD_upd select + congr_cl38_wD_d(4) <= (congr_cl38_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu38_wayD_upd select + congr_cl38_wD_d(5) <= (congr_cl38_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu39_wayD_upd select + congr_cl39_wD_d(0) <= (congr_cl39_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu39_wayD_upd select + congr_cl39_wD_d(1) <= (congr_cl39_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu39_wayD_upd select + congr_cl39_wD_d(2) <= (congr_cl39_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu39_wayD_upd select + congr_cl39_wD_d(3) <= (congr_cl39_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu39_wayD_upd select + congr_cl39_wD_d(4) <= (congr_cl39_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu39_wayD_upd select + congr_cl39_wD_d(5) <= (congr_cl39_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu40_wayD_upd select + congr_cl40_wD_d(0) <= (congr_cl40_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu40_wayD_upd select + congr_cl40_wD_d(1) <= (congr_cl40_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu40_wayD_upd select + congr_cl40_wD_d(2) <= (congr_cl40_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu40_wayD_upd select + congr_cl40_wD_d(3) <= (congr_cl40_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu40_wayD_upd select + congr_cl40_wD_d(4) <= (congr_cl40_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu40_wayD_upd select + congr_cl40_wD_d(5) <= (congr_cl40_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu41_wayD_upd select + congr_cl41_wD_d(0) <= (congr_cl41_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu41_wayD_upd select + congr_cl41_wD_d(1) <= (congr_cl41_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu41_wayD_upd select + congr_cl41_wD_d(2) <= (congr_cl41_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu41_wayD_upd select + congr_cl41_wD_d(3) <= (congr_cl41_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu41_wayD_upd select + congr_cl41_wD_d(4) <= (congr_cl41_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu41_wayD_upd select + congr_cl41_wD_d(5) <= (congr_cl41_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu42_wayD_upd select + congr_cl42_wD_d(0) <= (congr_cl42_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu42_wayD_upd select + congr_cl42_wD_d(1) <= (congr_cl42_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu42_wayD_upd select + congr_cl42_wD_d(2) <= (congr_cl42_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu42_wayD_upd select + congr_cl42_wD_d(3) <= (congr_cl42_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu42_wayD_upd select + congr_cl42_wD_d(4) <= (congr_cl42_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu42_wayD_upd select + congr_cl42_wD_d(5) <= (congr_cl42_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu43_wayD_upd select + congr_cl43_wD_d(0) <= (congr_cl43_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu43_wayD_upd select + congr_cl43_wD_d(1) <= (congr_cl43_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu43_wayD_upd select + congr_cl43_wD_d(2) <= (congr_cl43_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu43_wayD_upd select + congr_cl43_wD_d(3) <= (congr_cl43_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu43_wayD_upd select + congr_cl43_wD_d(4) <= (congr_cl43_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu43_wayD_upd select + congr_cl43_wD_d(5) <= (congr_cl43_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu44_wayD_upd select + congr_cl44_wD_d(0) <= (congr_cl44_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu44_wayD_upd select + congr_cl44_wD_d(1) <= (congr_cl44_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu44_wayD_upd select + congr_cl44_wD_d(2) <= (congr_cl44_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu44_wayD_upd select + congr_cl44_wD_d(3) <= (congr_cl44_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu44_wayD_upd select + congr_cl44_wD_d(4) <= (congr_cl44_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu44_wayD_upd select + congr_cl44_wD_d(5) <= (congr_cl44_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu45_wayD_upd select + congr_cl45_wD_d(0) <= (congr_cl45_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu45_wayD_upd select + congr_cl45_wD_d(1) <= (congr_cl45_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu45_wayD_upd select + congr_cl45_wD_d(2) <= (congr_cl45_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu45_wayD_upd select + congr_cl45_wD_d(3) <= (congr_cl45_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu45_wayD_upd select + congr_cl45_wD_d(4) <= (congr_cl45_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu45_wayD_upd select + congr_cl45_wD_d(5) <= (congr_cl45_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu46_wayD_upd select + congr_cl46_wD_d(0) <= (congr_cl46_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu46_wayD_upd select + congr_cl46_wD_d(1) <= (congr_cl46_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu46_wayD_upd select + congr_cl46_wD_d(2) <= (congr_cl46_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu46_wayD_upd select + congr_cl46_wD_d(3) <= (congr_cl46_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu46_wayD_upd select + congr_cl46_wD_d(4) <= (congr_cl46_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu46_wayD_upd select + congr_cl46_wD_d(5) <= (congr_cl46_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu47_wayD_upd select + congr_cl47_wD_d(0) <= (congr_cl47_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu47_wayD_upd select + congr_cl47_wD_d(1) <= (congr_cl47_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu47_wayD_upd select + congr_cl47_wD_d(2) <= (congr_cl47_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu47_wayD_upd select + congr_cl47_wD_d(3) <= (congr_cl47_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu47_wayD_upd select + congr_cl47_wD_d(4) <= (congr_cl47_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu47_wayD_upd select + congr_cl47_wD_d(5) <= (congr_cl47_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu48_wayD_upd select + congr_cl48_wD_d(0) <= (congr_cl48_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu48_wayD_upd select + congr_cl48_wD_d(1) <= (congr_cl48_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu48_wayD_upd select + congr_cl48_wD_d(2) <= (congr_cl48_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu48_wayD_upd select + congr_cl48_wD_d(3) <= (congr_cl48_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu48_wayD_upd select + congr_cl48_wD_d(4) <= (congr_cl48_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu48_wayD_upd select + congr_cl48_wD_d(5) <= (congr_cl48_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu49_wayD_upd select + congr_cl49_wD_d(0) <= (congr_cl49_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu49_wayD_upd select + congr_cl49_wD_d(1) <= (congr_cl49_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu49_wayD_upd select + congr_cl49_wD_d(2) <= (congr_cl49_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu49_wayD_upd select + congr_cl49_wD_d(3) <= (congr_cl49_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu49_wayD_upd select + congr_cl49_wD_d(4) <= (congr_cl49_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu49_wayD_upd select + congr_cl49_wD_d(5) <= (congr_cl49_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu50_wayD_upd select + congr_cl50_wD_d(0) <= (congr_cl50_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu50_wayD_upd select + congr_cl50_wD_d(1) <= (congr_cl50_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu50_wayD_upd select + congr_cl50_wD_d(2) <= (congr_cl50_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu50_wayD_upd select + congr_cl50_wD_d(3) <= (congr_cl50_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu50_wayD_upd select + congr_cl50_wD_d(4) <= (congr_cl50_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu50_wayD_upd select + congr_cl50_wD_d(5) <= (congr_cl50_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu51_wayD_upd select + congr_cl51_wD_d(0) <= (congr_cl51_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu51_wayD_upd select + congr_cl51_wD_d(1) <= (congr_cl51_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu51_wayD_upd select + congr_cl51_wD_d(2) <= (congr_cl51_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu51_wayD_upd select + congr_cl51_wD_d(3) <= (congr_cl51_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu51_wayD_upd select + congr_cl51_wD_d(4) <= (congr_cl51_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu51_wayD_upd select + congr_cl51_wD_d(5) <= (congr_cl51_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu52_wayD_upd select + congr_cl52_wD_d(0) <= (congr_cl52_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu52_wayD_upd select + congr_cl52_wD_d(1) <= (congr_cl52_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu52_wayD_upd select + congr_cl52_wD_d(2) <= (congr_cl52_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu52_wayD_upd select + congr_cl52_wD_d(3) <= (congr_cl52_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu52_wayD_upd select + congr_cl52_wD_d(4) <= (congr_cl52_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu52_wayD_upd select + congr_cl52_wD_d(5) <= (congr_cl52_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu53_wayD_upd select + congr_cl53_wD_d(0) <= (congr_cl53_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu53_wayD_upd select + congr_cl53_wD_d(1) <= (congr_cl53_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu53_wayD_upd select + congr_cl53_wD_d(2) <= (congr_cl53_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu53_wayD_upd select + congr_cl53_wD_d(3) <= (congr_cl53_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu53_wayD_upd select + congr_cl53_wD_d(4) <= (congr_cl53_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu53_wayD_upd select + congr_cl53_wD_d(5) <= (congr_cl53_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu54_wayD_upd select + congr_cl54_wD_d(0) <= (congr_cl54_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu54_wayD_upd select + congr_cl54_wD_d(1) <= (congr_cl54_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu54_wayD_upd select + congr_cl54_wD_d(2) <= (congr_cl54_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu54_wayD_upd select + congr_cl54_wD_d(3) <= (congr_cl54_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu54_wayD_upd select + congr_cl54_wD_d(4) <= (congr_cl54_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu54_wayD_upd select + congr_cl54_wD_d(5) <= (congr_cl54_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu55_wayD_upd select + congr_cl55_wD_d(0) <= (congr_cl55_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu55_wayD_upd select + congr_cl55_wD_d(1) <= (congr_cl55_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu55_wayD_upd select + congr_cl55_wD_d(2) <= (congr_cl55_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu55_wayD_upd select + congr_cl55_wD_d(3) <= (congr_cl55_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu55_wayD_upd select + congr_cl55_wD_d(4) <= (congr_cl55_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu55_wayD_upd select + congr_cl55_wD_d(5) <= (congr_cl55_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu56_wayD_upd select + congr_cl56_wD_d(0) <= (congr_cl56_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu56_wayD_upd select + congr_cl56_wD_d(1) <= (congr_cl56_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu56_wayD_upd select + congr_cl56_wD_d(2) <= (congr_cl56_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu56_wayD_upd select + congr_cl56_wD_d(3) <= (congr_cl56_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu56_wayD_upd select + congr_cl56_wD_d(4) <= (congr_cl56_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu56_wayD_upd select + congr_cl56_wD_d(5) <= (congr_cl56_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu57_wayD_upd select + congr_cl57_wD_d(0) <= (congr_cl57_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu57_wayD_upd select + congr_cl57_wD_d(1) <= (congr_cl57_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu57_wayD_upd select + congr_cl57_wD_d(2) <= (congr_cl57_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu57_wayD_upd select + congr_cl57_wD_d(3) <= (congr_cl57_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu57_wayD_upd select + congr_cl57_wD_d(4) <= (congr_cl57_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu57_wayD_upd select + congr_cl57_wD_d(5) <= (congr_cl57_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu58_wayD_upd select + congr_cl58_wD_d(0) <= (congr_cl58_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu58_wayD_upd select + congr_cl58_wD_d(1) <= (congr_cl58_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu58_wayD_upd select + congr_cl58_wD_d(2) <= (congr_cl58_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu58_wayD_upd select + congr_cl58_wD_d(3) <= (congr_cl58_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu58_wayD_upd select + congr_cl58_wD_d(4) <= (congr_cl58_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu58_wayD_upd select + congr_cl58_wD_d(5) <= (congr_cl58_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu59_wayD_upd select + congr_cl59_wD_d(0) <= (congr_cl59_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu59_wayD_upd select + congr_cl59_wD_d(1) <= (congr_cl59_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu59_wayD_upd select + congr_cl59_wD_d(2) <= (congr_cl59_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu59_wayD_upd select + congr_cl59_wD_d(3) <= (congr_cl59_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu59_wayD_upd select + congr_cl59_wD_d(4) <= (congr_cl59_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu59_wayD_upd select + congr_cl59_wD_d(5) <= (congr_cl59_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu60_wayD_upd select + congr_cl60_wD_d(0) <= (congr_cl60_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu60_wayD_upd select + congr_cl60_wD_d(1) <= (congr_cl60_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu60_wayD_upd select + congr_cl60_wD_d(2) <= (congr_cl60_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu60_wayD_upd select + congr_cl60_wD_d(3) <= (congr_cl60_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu60_wayD_upd select + congr_cl60_wD_d(4) <= (congr_cl60_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu60_wayD_upd select + congr_cl60_wD_d(5) <= (congr_cl60_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu61_wayD_upd select + congr_cl61_wD_d(0) <= (congr_cl61_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu61_wayD_upd select + congr_cl61_wD_d(1) <= (congr_cl61_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu61_wayD_upd select + congr_cl61_wD_d(2) <= (congr_cl61_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu61_wayD_upd select + congr_cl61_wD_d(3) <= (congr_cl61_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu61_wayD_upd select + congr_cl61_wD_d(4) <= (congr_cl61_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu61_wayD_upd select + congr_cl61_wD_d(5) <= (congr_cl61_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu62_wayD_upd select + congr_cl62_wD_d(0) <= (congr_cl62_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu62_wayD_upd select + congr_cl62_wD_d(1) <= (congr_cl62_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu62_wayD_upd select + congr_cl62_wD_d(2) <= (congr_cl62_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu62_wayD_upd select + congr_cl62_wD_d(3) <= (congr_cl62_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu62_wayD_upd select + congr_cl62_wD_d(4) <= (congr_cl62_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu62_wayD_upd select + congr_cl62_wD_d(5) <= (congr_cl62_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu63_wayD_upd select + congr_cl63_wD_d(0) <= (congr_cl63_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu63_wayD_upd select + congr_cl63_wD_d(1) <= (congr_cl63_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +with rel_bixu63_wayD_upd select + congr_cl63_wD_d(2) <= (congr_cl63_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu63_wayD_upd select + congr_cl63_wD_d(3) <= (congr_cl63_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu63_wayD_upd select + congr_cl63_wD_d(4) <= (congr_cl63_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu63_wayD_upd select + congr_cl63_wD_d(5) <= (congr_cl63_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu0_wayE_upd select + congr_cl0_wE_d(0) <= (congr_cl0_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu0_wayE_upd select + congr_cl0_wE_d(1) <= (congr_cl0_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu0_wayE_upd select + congr_cl0_wE_d(2) <= (congr_cl0_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu0_wayE_upd select + congr_cl0_wE_d(3) <= (congr_cl0_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu0_wayE_upd select + congr_cl0_wE_d(4) <= (congr_cl0_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu0_wayE_upd select + congr_cl0_wE_d(5) <= (congr_cl0_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu1_wayE_upd select + congr_cl1_wE_d(0) <= (congr_cl1_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu1_wayE_upd select + congr_cl1_wE_d(1) <= (congr_cl1_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu1_wayE_upd select + congr_cl1_wE_d(2) <= (congr_cl1_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu1_wayE_upd select + congr_cl1_wE_d(3) <= (congr_cl1_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu1_wayE_upd select + congr_cl1_wE_d(4) <= (congr_cl1_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu1_wayE_upd select + congr_cl1_wE_d(5) <= (congr_cl1_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu2_wayE_upd select + congr_cl2_wE_d(0) <= (congr_cl2_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu2_wayE_upd select + congr_cl2_wE_d(1) <= (congr_cl2_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu2_wayE_upd select + congr_cl2_wE_d(2) <= (congr_cl2_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu2_wayE_upd select + congr_cl2_wE_d(3) <= (congr_cl2_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu2_wayE_upd select + congr_cl2_wE_d(4) <= (congr_cl2_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu2_wayE_upd select + congr_cl2_wE_d(5) <= (congr_cl2_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu3_wayE_upd select + congr_cl3_wE_d(0) <= (congr_cl3_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu3_wayE_upd select + congr_cl3_wE_d(1) <= (congr_cl3_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu3_wayE_upd select + congr_cl3_wE_d(2) <= (congr_cl3_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu3_wayE_upd select + congr_cl3_wE_d(3) <= (congr_cl3_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu3_wayE_upd select + congr_cl3_wE_d(4) <= (congr_cl3_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu3_wayE_upd select + congr_cl3_wE_d(5) <= (congr_cl3_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu4_wayE_upd select + congr_cl4_wE_d(0) <= (congr_cl4_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu4_wayE_upd select + congr_cl4_wE_d(1) <= (congr_cl4_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu4_wayE_upd select + congr_cl4_wE_d(2) <= (congr_cl4_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu4_wayE_upd select + congr_cl4_wE_d(3) <= (congr_cl4_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu4_wayE_upd select + congr_cl4_wE_d(4) <= (congr_cl4_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu4_wayE_upd select + congr_cl4_wE_d(5) <= (congr_cl4_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu5_wayE_upd select + congr_cl5_wE_d(0) <= (congr_cl5_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu5_wayE_upd select + congr_cl5_wE_d(1) <= (congr_cl5_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu5_wayE_upd select + congr_cl5_wE_d(2) <= (congr_cl5_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu5_wayE_upd select + congr_cl5_wE_d(3) <= (congr_cl5_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu5_wayE_upd select + congr_cl5_wE_d(4) <= (congr_cl5_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu5_wayE_upd select + congr_cl5_wE_d(5) <= (congr_cl5_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu6_wayE_upd select + congr_cl6_wE_d(0) <= (congr_cl6_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu6_wayE_upd select + congr_cl6_wE_d(1) <= (congr_cl6_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu6_wayE_upd select + congr_cl6_wE_d(2) <= (congr_cl6_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu6_wayE_upd select + congr_cl6_wE_d(3) <= (congr_cl6_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu6_wayE_upd select + congr_cl6_wE_d(4) <= (congr_cl6_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu6_wayE_upd select + congr_cl6_wE_d(5) <= (congr_cl6_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu7_wayE_upd select + congr_cl7_wE_d(0) <= (congr_cl7_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu7_wayE_upd select + congr_cl7_wE_d(1) <= (congr_cl7_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu7_wayE_upd select + congr_cl7_wE_d(2) <= (congr_cl7_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu7_wayE_upd select + congr_cl7_wE_d(3) <= (congr_cl7_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu7_wayE_upd select + congr_cl7_wE_d(4) <= (congr_cl7_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu7_wayE_upd select + congr_cl7_wE_d(5) <= (congr_cl7_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu8_wayE_upd select + congr_cl8_wE_d(0) <= (congr_cl8_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu8_wayE_upd select + congr_cl8_wE_d(1) <= (congr_cl8_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu8_wayE_upd select + congr_cl8_wE_d(2) <= (congr_cl8_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu8_wayE_upd select + congr_cl8_wE_d(3) <= (congr_cl8_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu8_wayE_upd select + congr_cl8_wE_d(4) <= (congr_cl8_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu8_wayE_upd select + congr_cl8_wE_d(5) <= (congr_cl8_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu9_wayE_upd select + congr_cl9_wE_d(0) <= (congr_cl9_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu9_wayE_upd select + congr_cl9_wE_d(1) <= (congr_cl9_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu9_wayE_upd select + congr_cl9_wE_d(2) <= (congr_cl9_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu9_wayE_upd select + congr_cl9_wE_d(3) <= (congr_cl9_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu9_wayE_upd select + congr_cl9_wE_d(4) <= (congr_cl9_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu9_wayE_upd select + congr_cl9_wE_d(5) <= (congr_cl9_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu10_wayE_upd select + congr_cl10_wE_d(0) <= (congr_cl10_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu10_wayE_upd select + congr_cl10_wE_d(1) <= (congr_cl10_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu10_wayE_upd select + congr_cl10_wE_d(2) <= (congr_cl10_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu10_wayE_upd select + congr_cl10_wE_d(3) <= (congr_cl10_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu10_wayE_upd select + congr_cl10_wE_d(4) <= (congr_cl10_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu10_wayE_upd select + congr_cl10_wE_d(5) <= (congr_cl10_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu11_wayE_upd select + congr_cl11_wE_d(0) <= (congr_cl11_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu11_wayE_upd select + congr_cl11_wE_d(1) <= (congr_cl11_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu11_wayE_upd select + congr_cl11_wE_d(2) <= (congr_cl11_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu11_wayE_upd select + congr_cl11_wE_d(3) <= (congr_cl11_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu11_wayE_upd select + congr_cl11_wE_d(4) <= (congr_cl11_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu11_wayE_upd select + congr_cl11_wE_d(5) <= (congr_cl11_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu12_wayE_upd select + congr_cl12_wE_d(0) <= (congr_cl12_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu12_wayE_upd select + congr_cl12_wE_d(1) <= (congr_cl12_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu12_wayE_upd select + congr_cl12_wE_d(2) <= (congr_cl12_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu12_wayE_upd select + congr_cl12_wE_d(3) <= (congr_cl12_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu12_wayE_upd select + congr_cl12_wE_d(4) <= (congr_cl12_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu12_wayE_upd select + congr_cl12_wE_d(5) <= (congr_cl12_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu13_wayE_upd select + congr_cl13_wE_d(0) <= (congr_cl13_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu13_wayE_upd select + congr_cl13_wE_d(1) <= (congr_cl13_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu13_wayE_upd select + congr_cl13_wE_d(2) <= (congr_cl13_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu13_wayE_upd select + congr_cl13_wE_d(3) <= (congr_cl13_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu13_wayE_upd select + congr_cl13_wE_d(4) <= (congr_cl13_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu13_wayE_upd select + congr_cl13_wE_d(5) <= (congr_cl13_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu14_wayE_upd select + congr_cl14_wE_d(0) <= (congr_cl14_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu14_wayE_upd select + congr_cl14_wE_d(1) <= (congr_cl14_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu14_wayE_upd select + congr_cl14_wE_d(2) <= (congr_cl14_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu14_wayE_upd select + congr_cl14_wE_d(3) <= (congr_cl14_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu14_wayE_upd select + congr_cl14_wE_d(4) <= (congr_cl14_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu14_wayE_upd select + congr_cl14_wE_d(5) <= (congr_cl14_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu15_wayE_upd select + congr_cl15_wE_d(0) <= (congr_cl15_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu15_wayE_upd select + congr_cl15_wE_d(1) <= (congr_cl15_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu15_wayE_upd select + congr_cl15_wE_d(2) <= (congr_cl15_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu15_wayE_upd select + congr_cl15_wE_d(3) <= (congr_cl15_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu15_wayE_upd select + congr_cl15_wE_d(4) <= (congr_cl15_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu15_wayE_upd select + congr_cl15_wE_d(5) <= (congr_cl15_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu16_wayE_upd select + congr_cl16_wE_d(0) <= (congr_cl16_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu16_wayE_upd select + congr_cl16_wE_d(1) <= (congr_cl16_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu16_wayE_upd select + congr_cl16_wE_d(2) <= (congr_cl16_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu16_wayE_upd select + congr_cl16_wE_d(3) <= (congr_cl16_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu16_wayE_upd select + congr_cl16_wE_d(4) <= (congr_cl16_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu16_wayE_upd select + congr_cl16_wE_d(5) <= (congr_cl16_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu17_wayE_upd select + congr_cl17_wE_d(0) <= (congr_cl17_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu17_wayE_upd select + congr_cl17_wE_d(1) <= (congr_cl17_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu17_wayE_upd select + congr_cl17_wE_d(2) <= (congr_cl17_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu17_wayE_upd select + congr_cl17_wE_d(3) <= (congr_cl17_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu17_wayE_upd select + congr_cl17_wE_d(4) <= (congr_cl17_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu17_wayE_upd select + congr_cl17_wE_d(5) <= (congr_cl17_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu18_wayE_upd select + congr_cl18_wE_d(0) <= (congr_cl18_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu18_wayE_upd select + congr_cl18_wE_d(1) <= (congr_cl18_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu18_wayE_upd select + congr_cl18_wE_d(2) <= (congr_cl18_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu18_wayE_upd select + congr_cl18_wE_d(3) <= (congr_cl18_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu18_wayE_upd select + congr_cl18_wE_d(4) <= (congr_cl18_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu18_wayE_upd select + congr_cl18_wE_d(5) <= (congr_cl18_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu19_wayE_upd select + congr_cl19_wE_d(0) <= (congr_cl19_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu19_wayE_upd select + congr_cl19_wE_d(1) <= (congr_cl19_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu19_wayE_upd select + congr_cl19_wE_d(2) <= (congr_cl19_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu19_wayE_upd select + congr_cl19_wE_d(3) <= (congr_cl19_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu19_wayE_upd select + congr_cl19_wE_d(4) <= (congr_cl19_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu19_wayE_upd select + congr_cl19_wE_d(5) <= (congr_cl19_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu20_wayE_upd select + congr_cl20_wE_d(0) <= (congr_cl20_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu20_wayE_upd select + congr_cl20_wE_d(1) <= (congr_cl20_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu20_wayE_upd select + congr_cl20_wE_d(2) <= (congr_cl20_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu20_wayE_upd select + congr_cl20_wE_d(3) <= (congr_cl20_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu20_wayE_upd select + congr_cl20_wE_d(4) <= (congr_cl20_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu20_wayE_upd select + congr_cl20_wE_d(5) <= (congr_cl20_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu21_wayE_upd select + congr_cl21_wE_d(0) <= (congr_cl21_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu21_wayE_upd select + congr_cl21_wE_d(1) <= (congr_cl21_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu21_wayE_upd select + congr_cl21_wE_d(2) <= (congr_cl21_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu21_wayE_upd select + congr_cl21_wE_d(3) <= (congr_cl21_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu21_wayE_upd select + congr_cl21_wE_d(4) <= (congr_cl21_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu21_wayE_upd select + congr_cl21_wE_d(5) <= (congr_cl21_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu22_wayE_upd select + congr_cl22_wE_d(0) <= (congr_cl22_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu22_wayE_upd select + congr_cl22_wE_d(1) <= (congr_cl22_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu22_wayE_upd select + congr_cl22_wE_d(2) <= (congr_cl22_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu22_wayE_upd select + congr_cl22_wE_d(3) <= (congr_cl22_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu22_wayE_upd select + congr_cl22_wE_d(4) <= (congr_cl22_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu22_wayE_upd select + congr_cl22_wE_d(5) <= (congr_cl22_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu23_wayE_upd select + congr_cl23_wE_d(0) <= (congr_cl23_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu23_wayE_upd select + congr_cl23_wE_d(1) <= (congr_cl23_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu23_wayE_upd select + congr_cl23_wE_d(2) <= (congr_cl23_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu23_wayE_upd select + congr_cl23_wE_d(3) <= (congr_cl23_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu23_wayE_upd select + congr_cl23_wE_d(4) <= (congr_cl23_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu23_wayE_upd select + congr_cl23_wE_d(5) <= (congr_cl23_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu24_wayE_upd select + congr_cl24_wE_d(0) <= (congr_cl24_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu24_wayE_upd select + congr_cl24_wE_d(1) <= (congr_cl24_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu24_wayE_upd select + congr_cl24_wE_d(2) <= (congr_cl24_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu24_wayE_upd select + congr_cl24_wE_d(3) <= (congr_cl24_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu24_wayE_upd select + congr_cl24_wE_d(4) <= (congr_cl24_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu24_wayE_upd select + congr_cl24_wE_d(5) <= (congr_cl24_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu25_wayE_upd select + congr_cl25_wE_d(0) <= (congr_cl25_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu25_wayE_upd select + congr_cl25_wE_d(1) <= (congr_cl25_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu25_wayE_upd select + congr_cl25_wE_d(2) <= (congr_cl25_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu25_wayE_upd select + congr_cl25_wE_d(3) <= (congr_cl25_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu25_wayE_upd select + congr_cl25_wE_d(4) <= (congr_cl25_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu25_wayE_upd select + congr_cl25_wE_d(5) <= (congr_cl25_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu26_wayE_upd select + congr_cl26_wE_d(0) <= (congr_cl26_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu26_wayE_upd select + congr_cl26_wE_d(1) <= (congr_cl26_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu26_wayE_upd select + congr_cl26_wE_d(2) <= (congr_cl26_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu26_wayE_upd select + congr_cl26_wE_d(3) <= (congr_cl26_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu26_wayE_upd select + congr_cl26_wE_d(4) <= (congr_cl26_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu26_wayE_upd select + congr_cl26_wE_d(5) <= (congr_cl26_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu27_wayE_upd select + congr_cl27_wE_d(0) <= (congr_cl27_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu27_wayE_upd select + congr_cl27_wE_d(1) <= (congr_cl27_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu27_wayE_upd select + congr_cl27_wE_d(2) <= (congr_cl27_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu27_wayE_upd select + congr_cl27_wE_d(3) <= (congr_cl27_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu27_wayE_upd select + congr_cl27_wE_d(4) <= (congr_cl27_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu27_wayE_upd select + congr_cl27_wE_d(5) <= (congr_cl27_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu28_wayE_upd select + congr_cl28_wE_d(0) <= (congr_cl28_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu28_wayE_upd select + congr_cl28_wE_d(1) <= (congr_cl28_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu28_wayE_upd select + congr_cl28_wE_d(2) <= (congr_cl28_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu28_wayE_upd select + congr_cl28_wE_d(3) <= (congr_cl28_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu28_wayE_upd select + congr_cl28_wE_d(4) <= (congr_cl28_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu28_wayE_upd select + congr_cl28_wE_d(5) <= (congr_cl28_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu29_wayE_upd select + congr_cl29_wE_d(0) <= (congr_cl29_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu29_wayE_upd select + congr_cl29_wE_d(1) <= (congr_cl29_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu29_wayE_upd select + congr_cl29_wE_d(2) <= (congr_cl29_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu29_wayE_upd select + congr_cl29_wE_d(3) <= (congr_cl29_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu29_wayE_upd select + congr_cl29_wE_d(4) <= (congr_cl29_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu29_wayE_upd select + congr_cl29_wE_d(5) <= (congr_cl29_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu30_wayE_upd select + congr_cl30_wE_d(0) <= (congr_cl30_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu30_wayE_upd select + congr_cl30_wE_d(1) <= (congr_cl30_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu30_wayE_upd select + congr_cl30_wE_d(2) <= (congr_cl30_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu30_wayE_upd select + congr_cl30_wE_d(3) <= (congr_cl30_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu30_wayE_upd select + congr_cl30_wE_d(4) <= (congr_cl30_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu30_wayE_upd select + congr_cl30_wE_d(5) <= (congr_cl30_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu31_wayE_upd select + congr_cl31_wE_d(0) <= (congr_cl31_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu31_wayE_upd select + congr_cl31_wE_d(1) <= (congr_cl31_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu31_wayE_upd select + congr_cl31_wE_d(2) <= (congr_cl31_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu31_wayE_upd select + congr_cl31_wE_d(3) <= (congr_cl31_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu31_wayE_upd select + congr_cl31_wE_d(4) <= (congr_cl31_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu31_wayE_upd select + congr_cl31_wE_d(5) <= (congr_cl31_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu32_wayE_upd select + congr_cl32_wE_d(0) <= (congr_cl32_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu32_wayE_upd select + congr_cl32_wE_d(1) <= (congr_cl32_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu32_wayE_upd select + congr_cl32_wE_d(2) <= (congr_cl32_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu32_wayE_upd select + congr_cl32_wE_d(3) <= (congr_cl32_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu32_wayE_upd select + congr_cl32_wE_d(4) <= (congr_cl32_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu32_wayE_upd select + congr_cl32_wE_d(5) <= (congr_cl32_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu33_wayE_upd select + congr_cl33_wE_d(0) <= (congr_cl33_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu33_wayE_upd select + congr_cl33_wE_d(1) <= (congr_cl33_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu33_wayE_upd select + congr_cl33_wE_d(2) <= (congr_cl33_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu33_wayE_upd select + congr_cl33_wE_d(3) <= (congr_cl33_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu33_wayE_upd select + congr_cl33_wE_d(4) <= (congr_cl33_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu33_wayE_upd select + congr_cl33_wE_d(5) <= (congr_cl33_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu34_wayE_upd select + congr_cl34_wE_d(0) <= (congr_cl34_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu34_wayE_upd select + congr_cl34_wE_d(1) <= (congr_cl34_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu34_wayE_upd select + congr_cl34_wE_d(2) <= (congr_cl34_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu34_wayE_upd select + congr_cl34_wE_d(3) <= (congr_cl34_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu34_wayE_upd select + congr_cl34_wE_d(4) <= (congr_cl34_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu34_wayE_upd select + congr_cl34_wE_d(5) <= (congr_cl34_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu35_wayE_upd select + congr_cl35_wE_d(0) <= (congr_cl35_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu35_wayE_upd select + congr_cl35_wE_d(1) <= (congr_cl35_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu35_wayE_upd select + congr_cl35_wE_d(2) <= (congr_cl35_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu35_wayE_upd select + congr_cl35_wE_d(3) <= (congr_cl35_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu35_wayE_upd select + congr_cl35_wE_d(4) <= (congr_cl35_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu35_wayE_upd select + congr_cl35_wE_d(5) <= (congr_cl35_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu36_wayE_upd select + congr_cl36_wE_d(0) <= (congr_cl36_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu36_wayE_upd select + congr_cl36_wE_d(1) <= (congr_cl36_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu36_wayE_upd select + congr_cl36_wE_d(2) <= (congr_cl36_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu36_wayE_upd select + congr_cl36_wE_d(3) <= (congr_cl36_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu36_wayE_upd select + congr_cl36_wE_d(4) <= (congr_cl36_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu36_wayE_upd select + congr_cl36_wE_d(5) <= (congr_cl36_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu37_wayE_upd select + congr_cl37_wE_d(0) <= (congr_cl37_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu37_wayE_upd select + congr_cl37_wE_d(1) <= (congr_cl37_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu37_wayE_upd select + congr_cl37_wE_d(2) <= (congr_cl37_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu37_wayE_upd select + congr_cl37_wE_d(3) <= (congr_cl37_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu37_wayE_upd select + congr_cl37_wE_d(4) <= (congr_cl37_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu37_wayE_upd select + congr_cl37_wE_d(5) <= (congr_cl37_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu38_wayE_upd select + congr_cl38_wE_d(0) <= (congr_cl38_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu38_wayE_upd select + congr_cl38_wE_d(1) <= (congr_cl38_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu38_wayE_upd select + congr_cl38_wE_d(2) <= (congr_cl38_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu38_wayE_upd select + congr_cl38_wE_d(3) <= (congr_cl38_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu38_wayE_upd select + congr_cl38_wE_d(4) <= (congr_cl38_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu38_wayE_upd select + congr_cl38_wE_d(5) <= (congr_cl38_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu39_wayE_upd select + congr_cl39_wE_d(0) <= (congr_cl39_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu39_wayE_upd select + congr_cl39_wE_d(1) <= (congr_cl39_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu39_wayE_upd select + congr_cl39_wE_d(2) <= (congr_cl39_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu39_wayE_upd select + congr_cl39_wE_d(3) <= (congr_cl39_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu39_wayE_upd select + congr_cl39_wE_d(4) <= (congr_cl39_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu39_wayE_upd select + congr_cl39_wE_d(5) <= (congr_cl39_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu40_wayE_upd select + congr_cl40_wE_d(0) <= (congr_cl40_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu40_wayE_upd select + congr_cl40_wE_d(1) <= (congr_cl40_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu40_wayE_upd select + congr_cl40_wE_d(2) <= (congr_cl40_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu40_wayE_upd select + congr_cl40_wE_d(3) <= (congr_cl40_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu40_wayE_upd select + congr_cl40_wE_d(4) <= (congr_cl40_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu40_wayE_upd select + congr_cl40_wE_d(5) <= (congr_cl40_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu41_wayE_upd select + congr_cl41_wE_d(0) <= (congr_cl41_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu41_wayE_upd select + congr_cl41_wE_d(1) <= (congr_cl41_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu41_wayE_upd select + congr_cl41_wE_d(2) <= (congr_cl41_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu41_wayE_upd select + congr_cl41_wE_d(3) <= (congr_cl41_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu41_wayE_upd select + congr_cl41_wE_d(4) <= (congr_cl41_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu41_wayE_upd select + congr_cl41_wE_d(5) <= (congr_cl41_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu42_wayE_upd select + congr_cl42_wE_d(0) <= (congr_cl42_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu42_wayE_upd select + congr_cl42_wE_d(1) <= (congr_cl42_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu42_wayE_upd select + congr_cl42_wE_d(2) <= (congr_cl42_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu42_wayE_upd select + congr_cl42_wE_d(3) <= (congr_cl42_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu42_wayE_upd select + congr_cl42_wE_d(4) <= (congr_cl42_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu42_wayE_upd select + congr_cl42_wE_d(5) <= (congr_cl42_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu43_wayE_upd select + congr_cl43_wE_d(0) <= (congr_cl43_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu43_wayE_upd select + congr_cl43_wE_d(1) <= (congr_cl43_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu43_wayE_upd select + congr_cl43_wE_d(2) <= (congr_cl43_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu43_wayE_upd select + congr_cl43_wE_d(3) <= (congr_cl43_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu43_wayE_upd select + congr_cl43_wE_d(4) <= (congr_cl43_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu43_wayE_upd select + congr_cl43_wE_d(5) <= (congr_cl43_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu44_wayE_upd select + congr_cl44_wE_d(0) <= (congr_cl44_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu44_wayE_upd select + congr_cl44_wE_d(1) <= (congr_cl44_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu44_wayE_upd select + congr_cl44_wE_d(2) <= (congr_cl44_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu44_wayE_upd select + congr_cl44_wE_d(3) <= (congr_cl44_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu44_wayE_upd select + congr_cl44_wE_d(4) <= (congr_cl44_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu44_wayE_upd select + congr_cl44_wE_d(5) <= (congr_cl44_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu45_wayE_upd select + congr_cl45_wE_d(0) <= (congr_cl45_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu45_wayE_upd select + congr_cl45_wE_d(1) <= (congr_cl45_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu45_wayE_upd select + congr_cl45_wE_d(2) <= (congr_cl45_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu45_wayE_upd select + congr_cl45_wE_d(3) <= (congr_cl45_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu45_wayE_upd select + congr_cl45_wE_d(4) <= (congr_cl45_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu45_wayE_upd select + congr_cl45_wE_d(5) <= (congr_cl45_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu46_wayE_upd select + congr_cl46_wE_d(0) <= (congr_cl46_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu46_wayE_upd select + congr_cl46_wE_d(1) <= (congr_cl46_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu46_wayE_upd select + congr_cl46_wE_d(2) <= (congr_cl46_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu46_wayE_upd select + congr_cl46_wE_d(3) <= (congr_cl46_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu46_wayE_upd select + congr_cl46_wE_d(4) <= (congr_cl46_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu46_wayE_upd select + congr_cl46_wE_d(5) <= (congr_cl46_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu47_wayE_upd select + congr_cl47_wE_d(0) <= (congr_cl47_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu47_wayE_upd select + congr_cl47_wE_d(1) <= (congr_cl47_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu47_wayE_upd select + congr_cl47_wE_d(2) <= (congr_cl47_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu47_wayE_upd select + congr_cl47_wE_d(3) <= (congr_cl47_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu47_wayE_upd select + congr_cl47_wE_d(4) <= (congr_cl47_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu47_wayE_upd select + congr_cl47_wE_d(5) <= (congr_cl47_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu48_wayE_upd select + congr_cl48_wE_d(0) <= (congr_cl48_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu48_wayE_upd select + congr_cl48_wE_d(1) <= (congr_cl48_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu48_wayE_upd select + congr_cl48_wE_d(2) <= (congr_cl48_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu48_wayE_upd select + congr_cl48_wE_d(3) <= (congr_cl48_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu48_wayE_upd select + congr_cl48_wE_d(4) <= (congr_cl48_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu48_wayE_upd select + congr_cl48_wE_d(5) <= (congr_cl48_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu49_wayE_upd select + congr_cl49_wE_d(0) <= (congr_cl49_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu49_wayE_upd select + congr_cl49_wE_d(1) <= (congr_cl49_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu49_wayE_upd select + congr_cl49_wE_d(2) <= (congr_cl49_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu49_wayE_upd select + congr_cl49_wE_d(3) <= (congr_cl49_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu49_wayE_upd select + congr_cl49_wE_d(4) <= (congr_cl49_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu49_wayE_upd select + congr_cl49_wE_d(5) <= (congr_cl49_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu50_wayE_upd select + congr_cl50_wE_d(0) <= (congr_cl50_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu50_wayE_upd select + congr_cl50_wE_d(1) <= (congr_cl50_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu50_wayE_upd select + congr_cl50_wE_d(2) <= (congr_cl50_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu50_wayE_upd select + congr_cl50_wE_d(3) <= (congr_cl50_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu50_wayE_upd select + congr_cl50_wE_d(4) <= (congr_cl50_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu50_wayE_upd select + congr_cl50_wE_d(5) <= (congr_cl50_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu51_wayE_upd select + congr_cl51_wE_d(0) <= (congr_cl51_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu51_wayE_upd select + congr_cl51_wE_d(1) <= (congr_cl51_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu51_wayE_upd select + congr_cl51_wE_d(2) <= (congr_cl51_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu51_wayE_upd select + congr_cl51_wE_d(3) <= (congr_cl51_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu51_wayE_upd select + congr_cl51_wE_d(4) <= (congr_cl51_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu51_wayE_upd select + congr_cl51_wE_d(5) <= (congr_cl51_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu52_wayE_upd select + congr_cl52_wE_d(0) <= (congr_cl52_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu52_wayE_upd select + congr_cl52_wE_d(1) <= (congr_cl52_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu52_wayE_upd select + congr_cl52_wE_d(2) <= (congr_cl52_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu52_wayE_upd select + congr_cl52_wE_d(3) <= (congr_cl52_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu52_wayE_upd select + congr_cl52_wE_d(4) <= (congr_cl52_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu52_wayE_upd select + congr_cl52_wE_d(5) <= (congr_cl52_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu53_wayE_upd select + congr_cl53_wE_d(0) <= (congr_cl53_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu53_wayE_upd select + congr_cl53_wE_d(1) <= (congr_cl53_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu53_wayE_upd select + congr_cl53_wE_d(2) <= (congr_cl53_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu53_wayE_upd select + congr_cl53_wE_d(3) <= (congr_cl53_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu53_wayE_upd select + congr_cl53_wE_d(4) <= (congr_cl53_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu53_wayE_upd select + congr_cl53_wE_d(5) <= (congr_cl53_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu54_wayE_upd select + congr_cl54_wE_d(0) <= (congr_cl54_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu54_wayE_upd select + congr_cl54_wE_d(1) <= (congr_cl54_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu54_wayE_upd select + congr_cl54_wE_d(2) <= (congr_cl54_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu54_wayE_upd select + congr_cl54_wE_d(3) <= (congr_cl54_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu54_wayE_upd select + congr_cl54_wE_d(4) <= (congr_cl54_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu54_wayE_upd select + congr_cl54_wE_d(5) <= (congr_cl54_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu55_wayE_upd select + congr_cl55_wE_d(0) <= (congr_cl55_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu55_wayE_upd select + congr_cl55_wE_d(1) <= (congr_cl55_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu55_wayE_upd select + congr_cl55_wE_d(2) <= (congr_cl55_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu55_wayE_upd select + congr_cl55_wE_d(3) <= (congr_cl55_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu55_wayE_upd select + congr_cl55_wE_d(4) <= (congr_cl55_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu55_wayE_upd select + congr_cl55_wE_d(5) <= (congr_cl55_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu56_wayE_upd select + congr_cl56_wE_d(0) <= (congr_cl56_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu56_wayE_upd select + congr_cl56_wE_d(1) <= (congr_cl56_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu56_wayE_upd select + congr_cl56_wE_d(2) <= (congr_cl56_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu56_wayE_upd select + congr_cl56_wE_d(3) <= (congr_cl56_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu56_wayE_upd select + congr_cl56_wE_d(4) <= (congr_cl56_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu56_wayE_upd select + congr_cl56_wE_d(5) <= (congr_cl56_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu57_wayE_upd select + congr_cl57_wE_d(0) <= (congr_cl57_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu57_wayE_upd select + congr_cl57_wE_d(1) <= (congr_cl57_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu57_wayE_upd select + congr_cl57_wE_d(2) <= (congr_cl57_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu57_wayE_upd select + congr_cl57_wE_d(3) <= (congr_cl57_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu57_wayE_upd select + congr_cl57_wE_d(4) <= (congr_cl57_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu57_wayE_upd select + congr_cl57_wE_d(5) <= (congr_cl57_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu58_wayE_upd select + congr_cl58_wE_d(0) <= (congr_cl58_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu58_wayE_upd select + congr_cl58_wE_d(1) <= (congr_cl58_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu58_wayE_upd select + congr_cl58_wE_d(2) <= (congr_cl58_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu58_wayE_upd select + congr_cl58_wE_d(3) <= (congr_cl58_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu58_wayE_upd select + congr_cl58_wE_d(4) <= (congr_cl58_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu58_wayE_upd select + congr_cl58_wE_d(5) <= (congr_cl58_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu59_wayE_upd select + congr_cl59_wE_d(0) <= (congr_cl59_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu59_wayE_upd select + congr_cl59_wE_d(1) <= (congr_cl59_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu59_wayE_upd select + congr_cl59_wE_d(2) <= (congr_cl59_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu59_wayE_upd select + congr_cl59_wE_d(3) <= (congr_cl59_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu59_wayE_upd select + congr_cl59_wE_d(4) <= (congr_cl59_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu59_wayE_upd select + congr_cl59_wE_d(5) <= (congr_cl59_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu60_wayE_upd select + congr_cl60_wE_d(0) <= (congr_cl60_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu60_wayE_upd select + congr_cl60_wE_d(1) <= (congr_cl60_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu60_wayE_upd select + congr_cl60_wE_d(2) <= (congr_cl60_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu60_wayE_upd select + congr_cl60_wE_d(3) <= (congr_cl60_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu60_wayE_upd select + congr_cl60_wE_d(4) <= (congr_cl60_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu60_wayE_upd select + congr_cl60_wE_d(5) <= (congr_cl60_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu61_wayE_upd select + congr_cl61_wE_d(0) <= (congr_cl61_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu61_wayE_upd select + congr_cl61_wE_d(1) <= (congr_cl61_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu61_wayE_upd select + congr_cl61_wE_d(2) <= (congr_cl61_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu61_wayE_upd select + congr_cl61_wE_d(3) <= (congr_cl61_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu61_wayE_upd select + congr_cl61_wE_d(4) <= (congr_cl61_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu61_wayE_upd select + congr_cl61_wE_d(5) <= (congr_cl61_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu62_wayE_upd select + congr_cl62_wE_d(0) <= (congr_cl62_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu62_wayE_upd select + congr_cl62_wE_d(1) <= (congr_cl62_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu62_wayE_upd select + congr_cl62_wE_d(2) <= (congr_cl62_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu62_wayE_upd select + congr_cl62_wE_d(3) <= (congr_cl62_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu62_wayE_upd select + congr_cl62_wE_d(4) <= (congr_cl62_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu62_wayE_upd select + congr_cl62_wE_d(5) <= (congr_cl62_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu63_wayE_upd select + congr_cl63_wE_d(0) <= (congr_cl63_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu63_wayE_upd select + congr_cl63_wE_d(1) <= (congr_cl63_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +with rel_bixu63_wayE_upd select + congr_cl63_wE_d(2) <= (congr_cl63_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu63_wayE_upd select + congr_cl63_wE_d(3) <= (congr_cl63_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu63_wayE_upd select + congr_cl63_wE_d(4) <= (congr_cl63_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu63_wayE_upd select + congr_cl63_wE_d(5) <= (congr_cl63_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu0_wayF_upd select + congr_cl0_wF_d(0) <= (congr_cl0_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu0_wayF_upd select + congr_cl0_wF_d(1) <= (congr_cl0_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu0_wayF_upd select + congr_cl0_wF_d(2) <= (congr_cl0_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu0_wayF_upd select + congr_cl0_wF_d(3) <= (congr_cl0_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu0_wayF_upd select + congr_cl0_wF_d(4) <= (congr_cl0_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu0_wayF_upd select + congr_cl0_wF_d(5) <= (congr_cl0_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu1_wayF_upd select + congr_cl1_wF_d(0) <= (congr_cl1_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu1_wayF_upd select + congr_cl1_wF_d(1) <= (congr_cl1_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu1_wayF_upd select + congr_cl1_wF_d(2) <= (congr_cl1_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu1_wayF_upd select + congr_cl1_wF_d(3) <= (congr_cl1_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu1_wayF_upd select + congr_cl1_wF_d(4) <= (congr_cl1_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu1_wayF_upd select + congr_cl1_wF_d(5) <= (congr_cl1_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu2_wayF_upd select + congr_cl2_wF_d(0) <= (congr_cl2_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu2_wayF_upd select + congr_cl2_wF_d(1) <= (congr_cl2_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu2_wayF_upd select + congr_cl2_wF_d(2) <= (congr_cl2_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu2_wayF_upd select + congr_cl2_wF_d(3) <= (congr_cl2_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu2_wayF_upd select + congr_cl2_wF_d(4) <= (congr_cl2_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu2_wayF_upd select + congr_cl2_wF_d(5) <= (congr_cl2_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu3_wayF_upd select + congr_cl3_wF_d(0) <= (congr_cl3_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu3_wayF_upd select + congr_cl3_wF_d(1) <= (congr_cl3_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu3_wayF_upd select + congr_cl3_wF_d(2) <= (congr_cl3_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu3_wayF_upd select + congr_cl3_wF_d(3) <= (congr_cl3_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu3_wayF_upd select + congr_cl3_wF_d(4) <= (congr_cl3_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu3_wayF_upd select + congr_cl3_wF_d(5) <= (congr_cl3_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu4_wayF_upd select + congr_cl4_wF_d(0) <= (congr_cl4_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu4_wayF_upd select + congr_cl4_wF_d(1) <= (congr_cl4_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu4_wayF_upd select + congr_cl4_wF_d(2) <= (congr_cl4_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu4_wayF_upd select + congr_cl4_wF_d(3) <= (congr_cl4_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu4_wayF_upd select + congr_cl4_wF_d(4) <= (congr_cl4_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu4_wayF_upd select + congr_cl4_wF_d(5) <= (congr_cl4_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu5_wayF_upd select + congr_cl5_wF_d(0) <= (congr_cl5_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu5_wayF_upd select + congr_cl5_wF_d(1) <= (congr_cl5_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu5_wayF_upd select + congr_cl5_wF_d(2) <= (congr_cl5_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu5_wayF_upd select + congr_cl5_wF_d(3) <= (congr_cl5_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu5_wayF_upd select + congr_cl5_wF_d(4) <= (congr_cl5_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu5_wayF_upd select + congr_cl5_wF_d(5) <= (congr_cl5_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu6_wayF_upd select + congr_cl6_wF_d(0) <= (congr_cl6_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu6_wayF_upd select + congr_cl6_wF_d(1) <= (congr_cl6_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu6_wayF_upd select + congr_cl6_wF_d(2) <= (congr_cl6_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu6_wayF_upd select + congr_cl6_wF_d(3) <= (congr_cl6_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu6_wayF_upd select + congr_cl6_wF_d(4) <= (congr_cl6_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu6_wayF_upd select + congr_cl6_wF_d(5) <= (congr_cl6_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu7_wayF_upd select + congr_cl7_wF_d(0) <= (congr_cl7_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu7_wayF_upd select + congr_cl7_wF_d(1) <= (congr_cl7_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu7_wayF_upd select + congr_cl7_wF_d(2) <= (congr_cl7_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu7_wayF_upd select + congr_cl7_wF_d(3) <= (congr_cl7_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu7_wayF_upd select + congr_cl7_wF_d(4) <= (congr_cl7_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu7_wayF_upd select + congr_cl7_wF_d(5) <= (congr_cl7_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu8_wayF_upd select + congr_cl8_wF_d(0) <= (congr_cl8_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu8_wayF_upd select + congr_cl8_wF_d(1) <= (congr_cl8_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu8_wayF_upd select + congr_cl8_wF_d(2) <= (congr_cl8_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu8_wayF_upd select + congr_cl8_wF_d(3) <= (congr_cl8_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu8_wayF_upd select + congr_cl8_wF_d(4) <= (congr_cl8_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu8_wayF_upd select + congr_cl8_wF_d(5) <= (congr_cl8_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu9_wayF_upd select + congr_cl9_wF_d(0) <= (congr_cl9_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu9_wayF_upd select + congr_cl9_wF_d(1) <= (congr_cl9_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu9_wayF_upd select + congr_cl9_wF_d(2) <= (congr_cl9_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu9_wayF_upd select + congr_cl9_wF_d(3) <= (congr_cl9_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu9_wayF_upd select + congr_cl9_wF_d(4) <= (congr_cl9_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu9_wayF_upd select + congr_cl9_wF_d(5) <= (congr_cl9_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu10_wayF_upd select + congr_cl10_wF_d(0) <= (congr_cl10_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu10_wayF_upd select + congr_cl10_wF_d(1) <= (congr_cl10_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu10_wayF_upd select + congr_cl10_wF_d(2) <= (congr_cl10_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu10_wayF_upd select + congr_cl10_wF_d(3) <= (congr_cl10_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu10_wayF_upd select + congr_cl10_wF_d(4) <= (congr_cl10_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu10_wayF_upd select + congr_cl10_wF_d(5) <= (congr_cl10_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu11_wayF_upd select + congr_cl11_wF_d(0) <= (congr_cl11_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu11_wayF_upd select + congr_cl11_wF_d(1) <= (congr_cl11_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu11_wayF_upd select + congr_cl11_wF_d(2) <= (congr_cl11_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu11_wayF_upd select + congr_cl11_wF_d(3) <= (congr_cl11_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu11_wayF_upd select + congr_cl11_wF_d(4) <= (congr_cl11_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu11_wayF_upd select + congr_cl11_wF_d(5) <= (congr_cl11_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu12_wayF_upd select + congr_cl12_wF_d(0) <= (congr_cl12_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu12_wayF_upd select + congr_cl12_wF_d(1) <= (congr_cl12_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu12_wayF_upd select + congr_cl12_wF_d(2) <= (congr_cl12_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu12_wayF_upd select + congr_cl12_wF_d(3) <= (congr_cl12_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu12_wayF_upd select + congr_cl12_wF_d(4) <= (congr_cl12_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu12_wayF_upd select + congr_cl12_wF_d(5) <= (congr_cl12_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu13_wayF_upd select + congr_cl13_wF_d(0) <= (congr_cl13_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu13_wayF_upd select + congr_cl13_wF_d(1) <= (congr_cl13_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu13_wayF_upd select + congr_cl13_wF_d(2) <= (congr_cl13_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu13_wayF_upd select + congr_cl13_wF_d(3) <= (congr_cl13_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu13_wayF_upd select + congr_cl13_wF_d(4) <= (congr_cl13_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu13_wayF_upd select + congr_cl13_wF_d(5) <= (congr_cl13_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu14_wayF_upd select + congr_cl14_wF_d(0) <= (congr_cl14_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu14_wayF_upd select + congr_cl14_wF_d(1) <= (congr_cl14_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu14_wayF_upd select + congr_cl14_wF_d(2) <= (congr_cl14_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu14_wayF_upd select + congr_cl14_wF_d(3) <= (congr_cl14_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu14_wayF_upd select + congr_cl14_wF_d(4) <= (congr_cl14_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu14_wayF_upd select + congr_cl14_wF_d(5) <= (congr_cl14_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu15_wayF_upd select + congr_cl15_wF_d(0) <= (congr_cl15_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu15_wayF_upd select + congr_cl15_wF_d(1) <= (congr_cl15_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu15_wayF_upd select + congr_cl15_wF_d(2) <= (congr_cl15_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu15_wayF_upd select + congr_cl15_wF_d(3) <= (congr_cl15_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu15_wayF_upd select + congr_cl15_wF_d(4) <= (congr_cl15_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu15_wayF_upd select + congr_cl15_wF_d(5) <= (congr_cl15_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu16_wayF_upd select + congr_cl16_wF_d(0) <= (congr_cl16_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu16_wayF_upd select + congr_cl16_wF_d(1) <= (congr_cl16_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu16_wayF_upd select + congr_cl16_wF_d(2) <= (congr_cl16_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu16_wayF_upd select + congr_cl16_wF_d(3) <= (congr_cl16_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu16_wayF_upd select + congr_cl16_wF_d(4) <= (congr_cl16_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu16_wayF_upd select + congr_cl16_wF_d(5) <= (congr_cl16_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu17_wayF_upd select + congr_cl17_wF_d(0) <= (congr_cl17_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu17_wayF_upd select + congr_cl17_wF_d(1) <= (congr_cl17_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu17_wayF_upd select + congr_cl17_wF_d(2) <= (congr_cl17_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu17_wayF_upd select + congr_cl17_wF_d(3) <= (congr_cl17_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu17_wayF_upd select + congr_cl17_wF_d(4) <= (congr_cl17_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu17_wayF_upd select + congr_cl17_wF_d(5) <= (congr_cl17_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu18_wayF_upd select + congr_cl18_wF_d(0) <= (congr_cl18_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu18_wayF_upd select + congr_cl18_wF_d(1) <= (congr_cl18_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu18_wayF_upd select + congr_cl18_wF_d(2) <= (congr_cl18_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu18_wayF_upd select + congr_cl18_wF_d(3) <= (congr_cl18_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu18_wayF_upd select + congr_cl18_wF_d(4) <= (congr_cl18_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu18_wayF_upd select + congr_cl18_wF_d(5) <= (congr_cl18_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu19_wayF_upd select + congr_cl19_wF_d(0) <= (congr_cl19_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu19_wayF_upd select + congr_cl19_wF_d(1) <= (congr_cl19_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu19_wayF_upd select + congr_cl19_wF_d(2) <= (congr_cl19_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu19_wayF_upd select + congr_cl19_wF_d(3) <= (congr_cl19_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu19_wayF_upd select + congr_cl19_wF_d(4) <= (congr_cl19_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu19_wayF_upd select + congr_cl19_wF_d(5) <= (congr_cl19_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu20_wayF_upd select + congr_cl20_wF_d(0) <= (congr_cl20_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu20_wayF_upd select + congr_cl20_wF_d(1) <= (congr_cl20_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu20_wayF_upd select + congr_cl20_wF_d(2) <= (congr_cl20_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu20_wayF_upd select + congr_cl20_wF_d(3) <= (congr_cl20_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu20_wayF_upd select + congr_cl20_wF_d(4) <= (congr_cl20_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu20_wayF_upd select + congr_cl20_wF_d(5) <= (congr_cl20_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu21_wayF_upd select + congr_cl21_wF_d(0) <= (congr_cl21_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu21_wayF_upd select + congr_cl21_wF_d(1) <= (congr_cl21_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu21_wayF_upd select + congr_cl21_wF_d(2) <= (congr_cl21_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu21_wayF_upd select + congr_cl21_wF_d(3) <= (congr_cl21_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu21_wayF_upd select + congr_cl21_wF_d(4) <= (congr_cl21_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu21_wayF_upd select + congr_cl21_wF_d(5) <= (congr_cl21_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu22_wayF_upd select + congr_cl22_wF_d(0) <= (congr_cl22_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu22_wayF_upd select + congr_cl22_wF_d(1) <= (congr_cl22_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu22_wayF_upd select + congr_cl22_wF_d(2) <= (congr_cl22_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu22_wayF_upd select + congr_cl22_wF_d(3) <= (congr_cl22_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu22_wayF_upd select + congr_cl22_wF_d(4) <= (congr_cl22_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu22_wayF_upd select + congr_cl22_wF_d(5) <= (congr_cl22_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu23_wayF_upd select + congr_cl23_wF_d(0) <= (congr_cl23_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu23_wayF_upd select + congr_cl23_wF_d(1) <= (congr_cl23_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu23_wayF_upd select + congr_cl23_wF_d(2) <= (congr_cl23_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu23_wayF_upd select + congr_cl23_wF_d(3) <= (congr_cl23_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu23_wayF_upd select + congr_cl23_wF_d(4) <= (congr_cl23_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu23_wayF_upd select + congr_cl23_wF_d(5) <= (congr_cl23_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu24_wayF_upd select + congr_cl24_wF_d(0) <= (congr_cl24_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu24_wayF_upd select + congr_cl24_wF_d(1) <= (congr_cl24_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu24_wayF_upd select + congr_cl24_wF_d(2) <= (congr_cl24_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu24_wayF_upd select + congr_cl24_wF_d(3) <= (congr_cl24_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu24_wayF_upd select + congr_cl24_wF_d(4) <= (congr_cl24_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu24_wayF_upd select + congr_cl24_wF_d(5) <= (congr_cl24_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu25_wayF_upd select + congr_cl25_wF_d(0) <= (congr_cl25_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu25_wayF_upd select + congr_cl25_wF_d(1) <= (congr_cl25_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu25_wayF_upd select + congr_cl25_wF_d(2) <= (congr_cl25_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu25_wayF_upd select + congr_cl25_wF_d(3) <= (congr_cl25_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu25_wayF_upd select + congr_cl25_wF_d(4) <= (congr_cl25_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu25_wayF_upd select + congr_cl25_wF_d(5) <= (congr_cl25_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu26_wayF_upd select + congr_cl26_wF_d(0) <= (congr_cl26_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu26_wayF_upd select + congr_cl26_wF_d(1) <= (congr_cl26_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu26_wayF_upd select + congr_cl26_wF_d(2) <= (congr_cl26_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu26_wayF_upd select + congr_cl26_wF_d(3) <= (congr_cl26_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu26_wayF_upd select + congr_cl26_wF_d(4) <= (congr_cl26_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu26_wayF_upd select + congr_cl26_wF_d(5) <= (congr_cl26_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu27_wayF_upd select + congr_cl27_wF_d(0) <= (congr_cl27_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu27_wayF_upd select + congr_cl27_wF_d(1) <= (congr_cl27_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu27_wayF_upd select + congr_cl27_wF_d(2) <= (congr_cl27_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu27_wayF_upd select + congr_cl27_wF_d(3) <= (congr_cl27_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu27_wayF_upd select + congr_cl27_wF_d(4) <= (congr_cl27_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu27_wayF_upd select + congr_cl27_wF_d(5) <= (congr_cl27_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu28_wayF_upd select + congr_cl28_wF_d(0) <= (congr_cl28_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu28_wayF_upd select + congr_cl28_wF_d(1) <= (congr_cl28_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu28_wayF_upd select + congr_cl28_wF_d(2) <= (congr_cl28_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu28_wayF_upd select + congr_cl28_wF_d(3) <= (congr_cl28_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu28_wayF_upd select + congr_cl28_wF_d(4) <= (congr_cl28_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu28_wayF_upd select + congr_cl28_wF_d(5) <= (congr_cl28_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu29_wayF_upd select + congr_cl29_wF_d(0) <= (congr_cl29_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu29_wayF_upd select + congr_cl29_wF_d(1) <= (congr_cl29_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu29_wayF_upd select + congr_cl29_wF_d(2) <= (congr_cl29_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu29_wayF_upd select + congr_cl29_wF_d(3) <= (congr_cl29_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu29_wayF_upd select + congr_cl29_wF_d(4) <= (congr_cl29_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu29_wayF_upd select + congr_cl29_wF_d(5) <= (congr_cl29_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu30_wayF_upd select + congr_cl30_wF_d(0) <= (congr_cl30_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu30_wayF_upd select + congr_cl30_wF_d(1) <= (congr_cl30_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu30_wayF_upd select + congr_cl30_wF_d(2) <= (congr_cl30_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu30_wayF_upd select + congr_cl30_wF_d(3) <= (congr_cl30_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu30_wayF_upd select + congr_cl30_wF_d(4) <= (congr_cl30_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu30_wayF_upd select + congr_cl30_wF_d(5) <= (congr_cl30_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu31_wayF_upd select + congr_cl31_wF_d(0) <= (congr_cl31_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu31_wayF_upd select + congr_cl31_wF_d(1) <= (congr_cl31_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu31_wayF_upd select + congr_cl31_wF_d(2) <= (congr_cl31_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu31_wayF_upd select + congr_cl31_wF_d(3) <= (congr_cl31_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu31_wayF_upd select + congr_cl31_wF_d(4) <= (congr_cl31_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu31_wayF_upd select + congr_cl31_wF_d(5) <= (congr_cl31_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu32_wayF_upd select + congr_cl32_wF_d(0) <= (congr_cl32_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu32_wayF_upd select + congr_cl32_wF_d(1) <= (congr_cl32_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu32_wayF_upd select + congr_cl32_wF_d(2) <= (congr_cl32_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu32_wayF_upd select + congr_cl32_wF_d(3) <= (congr_cl32_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu32_wayF_upd select + congr_cl32_wF_d(4) <= (congr_cl32_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu32_wayF_upd select + congr_cl32_wF_d(5) <= (congr_cl32_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu33_wayF_upd select + congr_cl33_wF_d(0) <= (congr_cl33_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu33_wayF_upd select + congr_cl33_wF_d(1) <= (congr_cl33_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu33_wayF_upd select + congr_cl33_wF_d(2) <= (congr_cl33_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu33_wayF_upd select + congr_cl33_wF_d(3) <= (congr_cl33_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu33_wayF_upd select + congr_cl33_wF_d(4) <= (congr_cl33_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu33_wayF_upd select + congr_cl33_wF_d(5) <= (congr_cl33_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu34_wayF_upd select + congr_cl34_wF_d(0) <= (congr_cl34_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu34_wayF_upd select + congr_cl34_wF_d(1) <= (congr_cl34_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu34_wayF_upd select + congr_cl34_wF_d(2) <= (congr_cl34_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu34_wayF_upd select + congr_cl34_wF_d(3) <= (congr_cl34_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu34_wayF_upd select + congr_cl34_wF_d(4) <= (congr_cl34_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu34_wayF_upd select + congr_cl34_wF_d(5) <= (congr_cl34_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu35_wayF_upd select + congr_cl35_wF_d(0) <= (congr_cl35_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu35_wayF_upd select + congr_cl35_wF_d(1) <= (congr_cl35_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu35_wayF_upd select + congr_cl35_wF_d(2) <= (congr_cl35_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu35_wayF_upd select + congr_cl35_wF_d(3) <= (congr_cl35_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu35_wayF_upd select + congr_cl35_wF_d(4) <= (congr_cl35_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu35_wayF_upd select + congr_cl35_wF_d(5) <= (congr_cl35_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu36_wayF_upd select + congr_cl36_wF_d(0) <= (congr_cl36_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu36_wayF_upd select + congr_cl36_wF_d(1) <= (congr_cl36_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu36_wayF_upd select + congr_cl36_wF_d(2) <= (congr_cl36_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu36_wayF_upd select + congr_cl36_wF_d(3) <= (congr_cl36_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu36_wayF_upd select + congr_cl36_wF_d(4) <= (congr_cl36_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu36_wayF_upd select + congr_cl36_wF_d(5) <= (congr_cl36_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu37_wayF_upd select + congr_cl37_wF_d(0) <= (congr_cl37_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu37_wayF_upd select + congr_cl37_wF_d(1) <= (congr_cl37_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu37_wayF_upd select + congr_cl37_wF_d(2) <= (congr_cl37_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu37_wayF_upd select + congr_cl37_wF_d(3) <= (congr_cl37_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu37_wayF_upd select + congr_cl37_wF_d(4) <= (congr_cl37_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu37_wayF_upd select + congr_cl37_wF_d(5) <= (congr_cl37_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu38_wayF_upd select + congr_cl38_wF_d(0) <= (congr_cl38_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu38_wayF_upd select + congr_cl38_wF_d(1) <= (congr_cl38_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu38_wayF_upd select + congr_cl38_wF_d(2) <= (congr_cl38_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu38_wayF_upd select + congr_cl38_wF_d(3) <= (congr_cl38_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu38_wayF_upd select + congr_cl38_wF_d(4) <= (congr_cl38_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu38_wayF_upd select + congr_cl38_wF_d(5) <= (congr_cl38_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu39_wayF_upd select + congr_cl39_wF_d(0) <= (congr_cl39_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu39_wayF_upd select + congr_cl39_wF_d(1) <= (congr_cl39_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu39_wayF_upd select + congr_cl39_wF_d(2) <= (congr_cl39_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu39_wayF_upd select + congr_cl39_wF_d(3) <= (congr_cl39_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu39_wayF_upd select + congr_cl39_wF_d(4) <= (congr_cl39_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu39_wayF_upd select + congr_cl39_wF_d(5) <= (congr_cl39_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu40_wayF_upd select + congr_cl40_wF_d(0) <= (congr_cl40_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu40_wayF_upd select + congr_cl40_wF_d(1) <= (congr_cl40_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu40_wayF_upd select + congr_cl40_wF_d(2) <= (congr_cl40_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu40_wayF_upd select + congr_cl40_wF_d(3) <= (congr_cl40_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu40_wayF_upd select + congr_cl40_wF_d(4) <= (congr_cl40_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu40_wayF_upd select + congr_cl40_wF_d(5) <= (congr_cl40_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu41_wayF_upd select + congr_cl41_wF_d(0) <= (congr_cl41_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu41_wayF_upd select + congr_cl41_wF_d(1) <= (congr_cl41_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu41_wayF_upd select + congr_cl41_wF_d(2) <= (congr_cl41_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu41_wayF_upd select + congr_cl41_wF_d(3) <= (congr_cl41_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu41_wayF_upd select + congr_cl41_wF_d(4) <= (congr_cl41_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu41_wayF_upd select + congr_cl41_wF_d(5) <= (congr_cl41_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu42_wayF_upd select + congr_cl42_wF_d(0) <= (congr_cl42_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu42_wayF_upd select + congr_cl42_wF_d(1) <= (congr_cl42_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu42_wayF_upd select + congr_cl42_wF_d(2) <= (congr_cl42_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu42_wayF_upd select + congr_cl42_wF_d(3) <= (congr_cl42_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu42_wayF_upd select + congr_cl42_wF_d(4) <= (congr_cl42_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu42_wayF_upd select + congr_cl42_wF_d(5) <= (congr_cl42_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu43_wayF_upd select + congr_cl43_wF_d(0) <= (congr_cl43_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu43_wayF_upd select + congr_cl43_wF_d(1) <= (congr_cl43_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu43_wayF_upd select + congr_cl43_wF_d(2) <= (congr_cl43_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu43_wayF_upd select + congr_cl43_wF_d(3) <= (congr_cl43_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu43_wayF_upd select + congr_cl43_wF_d(4) <= (congr_cl43_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu43_wayF_upd select + congr_cl43_wF_d(5) <= (congr_cl43_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu44_wayF_upd select + congr_cl44_wF_d(0) <= (congr_cl44_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu44_wayF_upd select + congr_cl44_wF_d(1) <= (congr_cl44_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu44_wayF_upd select + congr_cl44_wF_d(2) <= (congr_cl44_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu44_wayF_upd select + congr_cl44_wF_d(3) <= (congr_cl44_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu44_wayF_upd select + congr_cl44_wF_d(4) <= (congr_cl44_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu44_wayF_upd select + congr_cl44_wF_d(5) <= (congr_cl44_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu45_wayF_upd select + congr_cl45_wF_d(0) <= (congr_cl45_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu45_wayF_upd select + congr_cl45_wF_d(1) <= (congr_cl45_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu45_wayF_upd select + congr_cl45_wF_d(2) <= (congr_cl45_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu45_wayF_upd select + congr_cl45_wF_d(3) <= (congr_cl45_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu45_wayF_upd select + congr_cl45_wF_d(4) <= (congr_cl45_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu45_wayF_upd select + congr_cl45_wF_d(5) <= (congr_cl45_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu46_wayF_upd select + congr_cl46_wF_d(0) <= (congr_cl46_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu46_wayF_upd select + congr_cl46_wF_d(1) <= (congr_cl46_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu46_wayF_upd select + congr_cl46_wF_d(2) <= (congr_cl46_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu46_wayF_upd select + congr_cl46_wF_d(3) <= (congr_cl46_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu46_wayF_upd select + congr_cl46_wF_d(4) <= (congr_cl46_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu46_wayF_upd select + congr_cl46_wF_d(5) <= (congr_cl46_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu47_wayF_upd select + congr_cl47_wF_d(0) <= (congr_cl47_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu47_wayF_upd select + congr_cl47_wF_d(1) <= (congr_cl47_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu47_wayF_upd select + congr_cl47_wF_d(2) <= (congr_cl47_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu47_wayF_upd select + congr_cl47_wF_d(3) <= (congr_cl47_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu47_wayF_upd select + congr_cl47_wF_d(4) <= (congr_cl47_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu47_wayF_upd select + congr_cl47_wF_d(5) <= (congr_cl47_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu48_wayF_upd select + congr_cl48_wF_d(0) <= (congr_cl48_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu48_wayF_upd select + congr_cl48_wF_d(1) <= (congr_cl48_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu48_wayF_upd select + congr_cl48_wF_d(2) <= (congr_cl48_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu48_wayF_upd select + congr_cl48_wF_d(3) <= (congr_cl48_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu48_wayF_upd select + congr_cl48_wF_d(4) <= (congr_cl48_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu48_wayF_upd select + congr_cl48_wF_d(5) <= (congr_cl48_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu49_wayF_upd select + congr_cl49_wF_d(0) <= (congr_cl49_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu49_wayF_upd select + congr_cl49_wF_d(1) <= (congr_cl49_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu49_wayF_upd select + congr_cl49_wF_d(2) <= (congr_cl49_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu49_wayF_upd select + congr_cl49_wF_d(3) <= (congr_cl49_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu49_wayF_upd select + congr_cl49_wF_d(4) <= (congr_cl49_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu49_wayF_upd select + congr_cl49_wF_d(5) <= (congr_cl49_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu50_wayF_upd select + congr_cl50_wF_d(0) <= (congr_cl50_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu50_wayF_upd select + congr_cl50_wF_d(1) <= (congr_cl50_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu50_wayF_upd select + congr_cl50_wF_d(2) <= (congr_cl50_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu50_wayF_upd select + congr_cl50_wF_d(3) <= (congr_cl50_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu50_wayF_upd select + congr_cl50_wF_d(4) <= (congr_cl50_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu50_wayF_upd select + congr_cl50_wF_d(5) <= (congr_cl50_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu51_wayF_upd select + congr_cl51_wF_d(0) <= (congr_cl51_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu51_wayF_upd select + congr_cl51_wF_d(1) <= (congr_cl51_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu51_wayF_upd select + congr_cl51_wF_d(2) <= (congr_cl51_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu51_wayF_upd select + congr_cl51_wF_d(3) <= (congr_cl51_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu51_wayF_upd select + congr_cl51_wF_d(4) <= (congr_cl51_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu51_wayF_upd select + congr_cl51_wF_d(5) <= (congr_cl51_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu52_wayF_upd select + congr_cl52_wF_d(0) <= (congr_cl52_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu52_wayF_upd select + congr_cl52_wF_d(1) <= (congr_cl52_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu52_wayF_upd select + congr_cl52_wF_d(2) <= (congr_cl52_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu52_wayF_upd select + congr_cl52_wF_d(3) <= (congr_cl52_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu52_wayF_upd select + congr_cl52_wF_d(4) <= (congr_cl52_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu52_wayF_upd select + congr_cl52_wF_d(5) <= (congr_cl52_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu53_wayF_upd select + congr_cl53_wF_d(0) <= (congr_cl53_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu53_wayF_upd select + congr_cl53_wF_d(1) <= (congr_cl53_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu53_wayF_upd select + congr_cl53_wF_d(2) <= (congr_cl53_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu53_wayF_upd select + congr_cl53_wF_d(3) <= (congr_cl53_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu53_wayF_upd select + congr_cl53_wF_d(4) <= (congr_cl53_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu53_wayF_upd select + congr_cl53_wF_d(5) <= (congr_cl53_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu54_wayF_upd select + congr_cl54_wF_d(0) <= (congr_cl54_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu54_wayF_upd select + congr_cl54_wF_d(1) <= (congr_cl54_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu54_wayF_upd select + congr_cl54_wF_d(2) <= (congr_cl54_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu54_wayF_upd select + congr_cl54_wF_d(3) <= (congr_cl54_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu54_wayF_upd select + congr_cl54_wF_d(4) <= (congr_cl54_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu54_wayF_upd select + congr_cl54_wF_d(5) <= (congr_cl54_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu55_wayF_upd select + congr_cl55_wF_d(0) <= (congr_cl55_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu55_wayF_upd select + congr_cl55_wF_d(1) <= (congr_cl55_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu55_wayF_upd select + congr_cl55_wF_d(2) <= (congr_cl55_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu55_wayF_upd select + congr_cl55_wF_d(3) <= (congr_cl55_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu55_wayF_upd select + congr_cl55_wF_d(4) <= (congr_cl55_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu55_wayF_upd select + congr_cl55_wF_d(5) <= (congr_cl55_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu56_wayF_upd select + congr_cl56_wF_d(0) <= (congr_cl56_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu56_wayF_upd select + congr_cl56_wF_d(1) <= (congr_cl56_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu56_wayF_upd select + congr_cl56_wF_d(2) <= (congr_cl56_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu56_wayF_upd select + congr_cl56_wF_d(3) <= (congr_cl56_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu56_wayF_upd select + congr_cl56_wF_d(4) <= (congr_cl56_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu56_wayF_upd select + congr_cl56_wF_d(5) <= (congr_cl56_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu57_wayF_upd select + congr_cl57_wF_d(0) <= (congr_cl57_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu57_wayF_upd select + congr_cl57_wF_d(1) <= (congr_cl57_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu57_wayF_upd select + congr_cl57_wF_d(2) <= (congr_cl57_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu57_wayF_upd select + congr_cl57_wF_d(3) <= (congr_cl57_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu57_wayF_upd select + congr_cl57_wF_d(4) <= (congr_cl57_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu57_wayF_upd select + congr_cl57_wF_d(5) <= (congr_cl57_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu58_wayF_upd select + congr_cl58_wF_d(0) <= (congr_cl58_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu58_wayF_upd select + congr_cl58_wF_d(1) <= (congr_cl58_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu58_wayF_upd select + congr_cl58_wF_d(2) <= (congr_cl58_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu58_wayF_upd select + congr_cl58_wF_d(3) <= (congr_cl58_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu58_wayF_upd select + congr_cl58_wF_d(4) <= (congr_cl58_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu58_wayF_upd select + congr_cl58_wF_d(5) <= (congr_cl58_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu59_wayF_upd select + congr_cl59_wF_d(0) <= (congr_cl59_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu59_wayF_upd select + congr_cl59_wF_d(1) <= (congr_cl59_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu59_wayF_upd select + congr_cl59_wF_d(2) <= (congr_cl59_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu59_wayF_upd select + congr_cl59_wF_d(3) <= (congr_cl59_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu59_wayF_upd select + congr_cl59_wF_d(4) <= (congr_cl59_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu59_wayF_upd select + congr_cl59_wF_d(5) <= (congr_cl59_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu60_wayF_upd select + congr_cl60_wF_d(0) <= (congr_cl60_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu60_wayF_upd select + congr_cl60_wF_d(1) <= (congr_cl60_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu60_wayF_upd select + congr_cl60_wF_d(2) <= (congr_cl60_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu60_wayF_upd select + congr_cl60_wF_d(3) <= (congr_cl60_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu60_wayF_upd select + congr_cl60_wF_d(4) <= (congr_cl60_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu60_wayF_upd select + congr_cl60_wF_d(5) <= (congr_cl60_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu61_wayF_upd select + congr_cl61_wF_d(0) <= (congr_cl61_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu61_wayF_upd select + congr_cl61_wF_d(1) <= (congr_cl61_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu61_wayF_upd select + congr_cl61_wF_d(2) <= (congr_cl61_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu61_wayF_upd select + congr_cl61_wF_d(3) <= (congr_cl61_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu61_wayF_upd select + congr_cl61_wF_d(4) <= (congr_cl61_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu61_wayF_upd select + congr_cl61_wF_d(5) <= (congr_cl61_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu62_wayF_upd select + congr_cl62_wF_d(0) <= (congr_cl62_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu62_wayF_upd select + congr_cl62_wF_d(1) <= (congr_cl62_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu62_wayF_upd select + congr_cl62_wF_d(2) <= (congr_cl62_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu62_wayF_upd select + congr_cl62_wF_d(3) <= (congr_cl62_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu62_wayF_upd select + congr_cl62_wF_d(4) <= (congr_cl62_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu62_wayF_upd select + congr_cl62_wF_d(5) <= (congr_cl62_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu63_wayF_upd select + congr_cl63_wF_d(0) <= (congr_cl63_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu63_wayF_upd select + congr_cl63_wF_d(1) <= (congr_cl63_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +with rel_bixu63_wayF_upd select + congr_cl63_wF_d(2) <= (congr_cl63_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu63_wayF_upd select + congr_cl63_wF_d(3) <= (congr_cl63_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu63_wayF_upd select + congr_cl63_wF_d(4) <= (congr_cl63_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu63_wayF_upd select + congr_cl63_wF_d(5) <= (congr_cl63_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu0_wayG_upd select + congr_cl0_wG_d(0) <= (congr_cl0_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu0_wayG_upd select + congr_cl0_wG_d(1) <= (congr_cl0_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu0_wayG_upd select + congr_cl0_wG_d(2) <= (congr_cl0_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu0_wayG_upd select + congr_cl0_wG_d(3) <= (congr_cl0_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu0_wayG_upd select + congr_cl0_wG_d(4) <= (congr_cl0_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu0_wayG_upd select + congr_cl0_wG_d(5) <= (congr_cl0_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu1_wayG_upd select + congr_cl1_wG_d(0) <= (congr_cl1_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu1_wayG_upd select + congr_cl1_wG_d(1) <= (congr_cl1_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu1_wayG_upd select + congr_cl1_wG_d(2) <= (congr_cl1_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu1_wayG_upd select + congr_cl1_wG_d(3) <= (congr_cl1_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu1_wayG_upd select + congr_cl1_wG_d(4) <= (congr_cl1_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu1_wayG_upd select + congr_cl1_wG_d(5) <= (congr_cl1_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu2_wayG_upd select + congr_cl2_wG_d(0) <= (congr_cl2_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu2_wayG_upd select + congr_cl2_wG_d(1) <= (congr_cl2_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu2_wayG_upd select + congr_cl2_wG_d(2) <= (congr_cl2_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu2_wayG_upd select + congr_cl2_wG_d(3) <= (congr_cl2_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu2_wayG_upd select + congr_cl2_wG_d(4) <= (congr_cl2_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu2_wayG_upd select + congr_cl2_wG_d(5) <= (congr_cl2_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu3_wayG_upd select + congr_cl3_wG_d(0) <= (congr_cl3_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu3_wayG_upd select + congr_cl3_wG_d(1) <= (congr_cl3_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu3_wayG_upd select + congr_cl3_wG_d(2) <= (congr_cl3_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu3_wayG_upd select + congr_cl3_wG_d(3) <= (congr_cl3_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu3_wayG_upd select + congr_cl3_wG_d(4) <= (congr_cl3_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu3_wayG_upd select + congr_cl3_wG_d(5) <= (congr_cl3_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu4_wayG_upd select + congr_cl4_wG_d(0) <= (congr_cl4_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu4_wayG_upd select + congr_cl4_wG_d(1) <= (congr_cl4_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu4_wayG_upd select + congr_cl4_wG_d(2) <= (congr_cl4_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu4_wayG_upd select + congr_cl4_wG_d(3) <= (congr_cl4_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu4_wayG_upd select + congr_cl4_wG_d(4) <= (congr_cl4_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu4_wayG_upd select + congr_cl4_wG_d(5) <= (congr_cl4_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu5_wayG_upd select + congr_cl5_wG_d(0) <= (congr_cl5_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu5_wayG_upd select + congr_cl5_wG_d(1) <= (congr_cl5_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu5_wayG_upd select + congr_cl5_wG_d(2) <= (congr_cl5_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu5_wayG_upd select + congr_cl5_wG_d(3) <= (congr_cl5_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu5_wayG_upd select + congr_cl5_wG_d(4) <= (congr_cl5_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu5_wayG_upd select + congr_cl5_wG_d(5) <= (congr_cl5_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu6_wayG_upd select + congr_cl6_wG_d(0) <= (congr_cl6_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu6_wayG_upd select + congr_cl6_wG_d(1) <= (congr_cl6_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu6_wayG_upd select + congr_cl6_wG_d(2) <= (congr_cl6_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu6_wayG_upd select + congr_cl6_wG_d(3) <= (congr_cl6_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu6_wayG_upd select + congr_cl6_wG_d(4) <= (congr_cl6_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu6_wayG_upd select + congr_cl6_wG_d(5) <= (congr_cl6_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu7_wayG_upd select + congr_cl7_wG_d(0) <= (congr_cl7_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu7_wayG_upd select + congr_cl7_wG_d(1) <= (congr_cl7_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu7_wayG_upd select + congr_cl7_wG_d(2) <= (congr_cl7_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu7_wayG_upd select + congr_cl7_wG_d(3) <= (congr_cl7_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu7_wayG_upd select + congr_cl7_wG_d(4) <= (congr_cl7_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu7_wayG_upd select + congr_cl7_wG_d(5) <= (congr_cl7_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu8_wayG_upd select + congr_cl8_wG_d(0) <= (congr_cl8_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu8_wayG_upd select + congr_cl8_wG_d(1) <= (congr_cl8_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu8_wayG_upd select + congr_cl8_wG_d(2) <= (congr_cl8_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu8_wayG_upd select + congr_cl8_wG_d(3) <= (congr_cl8_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu8_wayG_upd select + congr_cl8_wG_d(4) <= (congr_cl8_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu8_wayG_upd select + congr_cl8_wG_d(5) <= (congr_cl8_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu9_wayG_upd select + congr_cl9_wG_d(0) <= (congr_cl9_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu9_wayG_upd select + congr_cl9_wG_d(1) <= (congr_cl9_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu9_wayG_upd select + congr_cl9_wG_d(2) <= (congr_cl9_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu9_wayG_upd select + congr_cl9_wG_d(3) <= (congr_cl9_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu9_wayG_upd select + congr_cl9_wG_d(4) <= (congr_cl9_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu9_wayG_upd select + congr_cl9_wG_d(5) <= (congr_cl9_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu10_wayG_upd select + congr_cl10_wG_d(0) <= (congr_cl10_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu10_wayG_upd select + congr_cl10_wG_d(1) <= (congr_cl10_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu10_wayG_upd select + congr_cl10_wG_d(2) <= (congr_cl10_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu10_wayG_upd select + congr_cl10_wG_d(3) <= (congr_cl10_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu10_wayG_upd select + congr_cl10_wG_d(4) <= (congr_cl10_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu10_wayG_upd select + congr_cl10_wG_d(5) <= (congr_cl10_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu11_wayG_upd select + congr_cl11_wG_d(0) <= (congr_cl11_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu11_wayG_upd select + congr_cl11_wG_d(1) <= (congr_cl11_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu11_wayG_upd select + congr_cl11_wG_d(2) <= (congr_cl11_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu11_wayG_upd select + congr_cl11_wG_d(3) <= (congr_cl11_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu11_wayG_upd select + congr_cl11_wG_d(4) <= (congr_cl11_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu11_wayG_upd select + congr_cl11_wG_d(5) <= (congr_cl11_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu12_wayG_upd select + congr_cl12_wG_d(0) <= (congr_cl12_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu12_wayG_upd select + congr_cl12_wG_d(1) <= (congr_cl12_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu12_wayG_upd select + congr_cl12_wG_d(2) <= (congr_cl12_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu12_wayG_upd select + congr_cl12_wG_d(3) <= (congr_cl12_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu12_wayG_upd select + congr_cl12_wG_d(4) <= (congr_cl12_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu12_wayG_upd select + congr_cl12_wG_d(5) <= (congr_cl12_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu13_wayG_upd select + congr_cl13_wG_d(0) <= (congr_cl13_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu13_wayG_upd select + congr_cl13_wG_d(1) <= (congr_cl13_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu13_wayG_upd select + congr_cl13_wG_d(2) <= (congr_cl13_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu13_wayG_upd select + congr_cl13_wG_d(3) <= (congr_cl13_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu13_wayG_upd select + congr_cl13_wG_d(4) <= (congr_cl13_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu13_wayG_upd select + congr_cl13_wG_d(5) <= (congr_cl13_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu14_wayG_upd select + congr_cl14_wG_d(0) <= (congr_cl14_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu14_wayG_upd select + congr_cl14_wG_d(1) <= (congr_cl14_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu14_wayG_upd select + congr_cl14_wG_d(2) <= (congr_cl14_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu14_wayG_upd select + congr_cl14_wG_d(3) <= (congr_cl14_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu14_wayG_upd select + congr_cl14_wG_d(4) <= (congr_cl14_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu14_wayG_upd select + congr_cl14_wG_d(5) <= (congr_cl14_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu15_wayG_upd select + congr_cl15_wG_d(0) <= (congr_cl15_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu15_wayG_upd select + congr_cl15_wG_d(1) <= (congr_cl15_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu15_wayG_upd select + congr_cl15_wG_d(2) <= (congr_cl15_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu15_wayG_upd select + congr_cl15_wG_d(3) <= (congr_cl15_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu15_wayG_upd select + congr_cl15_wG_d(4) <= (congr_cl15_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu15_wayG_upd select + congr_cl15_wG_d(5) <= (congr_cl15_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu16_wayG_upd select + congr_cl16_wG_d(0) <= (congr_cl16_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu16_wayG_upd select + congr_cl16_wG_d(1) <= (congr_cl16_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu16_wayG_upd select + congr_cl16_wG_d(2) <= (congr_cl16_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu16_wayG_upd select + congr_cl16_wG_d(3) <= (congr_cl16_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu16_wayG_upd select + congr_cl16_wG_d(4) <= (congr_cl16_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu16_wayG_upd select + congr_cl16_wG_d(5) <= (congr_cl16_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu17_wayG_upd select + congr_cl17_wG_d(0) <= (congr_cl17_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu17_wayG_upd select + congr_cl17_wG_d(1) <= (congr_cl17_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu17_wayG_upd select + congr_cl17_wG_d(2) <= (congr_cl17_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu17_wayG_upd select + congr_cl17_wG_d(3) <= (congr_cl17_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu17_wayG_upd select + congr_cl17_wG_d(4) <= (congr_cl17_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu17_wayG_upd select + congr_cl17_wG_d(5) <= (congr_cl17_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu18_wayG_upd select + congr_cl18_wG_d(0) <= (congr_cl18_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu18_wayG_upd select + congr_cl18_wG_d(1) <= (congr_cl18_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu18_wayG_upd select + congr_cl18_wG_d(2) <= (congr_cl18_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu18_wayG_upd select + congr_cl18_wG_d(3) <= (congr_cl18_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu18_wayG_upd select + congr_cl18_wG_d(4) <= (congr_cl18_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu18_wayG_upd select + congr_cl18_wG_d(5) <= (congr_cl18_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu19_wayG_upd select + congr_cl19_wG_d(0) <= (congr_cl19_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu19_wayG_upd select + congr_cl19_wG_d(1) <= (congr_cl19_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu19_wayG_upd select + congr_cl19_wG_d(2) <= (congr_cl19_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu19_wayG_upd select + congr_cl19_wG_d(3) <= (congr_cl19_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu19_wayG_upd select + congr_cl19_wG_d(4) <= (congr_cl19_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu19_wayG_upd select + congr_cl19_wG_d(5) <= (congr_cl19_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu20_wayG_upd select + congr_cl20_wG_d(0) <= (congr_cl20_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu20_wayG_upd select + congr_cl20_wG_d(1) <= (congr_cl20_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu20_wayG_upd select + congr_cl20_wG_d(2) <= (congr_cl20_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu20_wayG_upd select + congr_cl20_wG_d(3) <= (congr_cl20_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu20_wayG_upd select + congr_cl20_wG_d(4) <= (congr_cl20_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu20_wayG_upd select + congr_cl20_wG_d(5) <= (congr_cl20_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu21_wayG_upd select + congr_cl21_wG_d(0) <= (congr_cl21_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu21_wayG_upd select + congr_cl21_wG_d(1) <= (congr_cl21_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu21_wayG_upd select + congr_cl21_wG_d(2) <= (congr_cl21_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu21_wayG_upd select + congr_cl21_wG_d(3) <= (congr_cl21_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu21_wayG_upd select + congr_cl21_wG_d(4) <= (congr_cl21_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu21_wayG_upd select + congr_cl21_wG_d(5) <= (congr_cl21_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu22_wayG_upd select + congr_cl22_wG_d(0) <= (congr_cl22_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu22_wayG_upd select + congr_cl22_wG_d(1) <= (congr_cl22_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu22_wayG_upd select + congr_cl22_wG_d(2) <= (congr_cl22_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu22_wayG_upd select + congr_cl22_wG_d(3) <= (congr_cl22_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu22_wayG_upd select + congr_cl22_wG_d(4) <= (congr_cl22_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu22_wayG_upd select + congr_cl22_wG_d(5) <= (congr_cl22_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu23_wayG_upd select + congr_cl23_wG_d(0) <= (congr_cl23_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu23_wayG_upd select + congr_cl23_wG_d(1) <= (congr_cl23_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu23_wayG_upd select + congr_cl23_wG_d(2) <= (congr_cl23_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu23_wayG_upd select + congr_cl23_wG_d(3) <= (congr_cl23_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu23_wayG_upd select + congr_cl23_wG_d(4) <= (congr_cl23_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu23_wayG_upd select + congr_cl23_wG_d(5) <= (congr_cl23_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu24_wayG_upd select + congr_cl24_wG_d(0) <= (congr_cl24_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu24_wayG_upd select + congr_cl24_wG_d(1) <= (congr_cl24_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu24_wayG_upd select + congr_cl24_wG_d(2) <= (congr_cl24_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu24_wayG_upd select + congr_cl24_wG_d(3) <= (congr_cl24_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu24_wayG_upd select + congr_cl24_wG_d(4) <= (congr_cl24_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu24_wayG_upd select + congr_cl24_wG_d(5) <= (congr_cl24_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu25_wayG_upd select + congr_cl25_wG_d(0) <= (congr_cl25_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu25_wayG_upd select + congr_cl25_wG_d(1) <= (congr_cl25_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu25_wayG_upd select + congr_cl25_wG_d(2) <= (congr_cl25_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu25_wayG_upd select + congr_cl25_wG_d(3) <= (congr_cl25_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu25_wayG_upd select + congr_cl25_wG_d(4) <= (congr_cl25_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu25_wayG_upd select + congr_cl25_wG_d(5) <= (congr_cl25_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu26_wayG_upd select + congr_cl26_wG_d(0) <= (congr_cl26_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu26_wayG_upd select + congr_cl26_wG_d(1) <= (congr_cl26_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu26_wayG_upd select + congr_cl26_wG_d(2) <= (congr_cl26_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu26_wayG_upd select + congr_cl26_wG_d(3) <= (congr_cl26_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu26_wayG_upd select + congr_cl26_wG_d(4) <= (congr_cl26_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu26_wayG_upd select + congr_cl26_wG_d(5) <= (congr_cl26_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu27_wayG_upd select + congr_cl27_wG_d(0) <= (congr_cl27_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu27_wayG_upd select + congr_cl27_wG_d(1) <= (congr_cl27_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu27_wayG_upd select + congr_cl27_wG_d(2) <= (congr_cl27_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu27_wayG_upd select + congr_cl27_wG_d(3) <= (congr_cl27_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu27_wayG_upd select + congr_cl27_wG_d(4) <= (congr_cl27_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu27_wayG_upd select + congr_cl27_wG_d(5) <= (congr_cl27_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu28_wayG_upd select + congr_cl28_wG_d(0) <= (congr_cl28_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu28_wayG_upd select + congr_cl28_wG_d(1) <= (congr_cl28_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu28_wayG_upd select + congr_cl28_wG_d(2) <= (congr_cl28_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu28_wayG_upd select + congr_cl28_wG_d(3) <= (congr_cl28_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu28_wayG_upd select + congr_cl28_wG_d(4) <= (congr_cl28_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu28_wayG_upd select + congr_cl28_wG_d(5) <= (congr_cl28_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu29_wayG_upd select + congr_cl29_wG_d(0) <= (congr_cl29_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu29_wayG_upd select + congr_cl29_wG_d(1) <= (congr_cl29_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu29_wayG_upd select + congr_cl29_wG_d(2) <= (congr_cl29_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu29_wayG_upd select + congr_cl29_wG_d(3) <= (congr_cl29_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu29_wayG_upd select + congr_cl29_wG_d(4) <= (congr_cl29_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu29_wayG_upd select + congr_cl29_wG_d(5) <= (congr_cl29_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu30_wayG_upd select + congr_cl30_wG_d(0) <= (congr_cl30_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu30_wayG_upd select + congr_cl30_wG_d(1) <= (congr_cl30_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu30_wayG_upd select + congr_cl30_wG_d(2) <= (congr_cl30_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu30_wayG_upd select + congr_cl30_wG_d(3) <= (congr_cl30_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu30_wayG_upd select + congr_cl30_wG_d(4) <= (congr_cl30_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu30_wayG_upd select + congr_cl30_wG_d(5) <= (congr_cl30_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu31_wayG_upd select + congr_cl31_wG_d(0) <= (congr_cl31_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu31_wayG_upd select + congr_cl31_wG_d(1) <= (congr_cl31_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu31_wayG_upd select + congr_cl31_wG_d(2) <= (congr_cl31_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu31_wayG_upd select + congr_cl31_wG_d(3) <= (congr_cl31_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu31_wayG_upd select + congr_cl31_wG_d(4) <= (congr_cl31_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu31_wayG_upd select + congr_cl31_wG_d(5) <= (congr_cl31_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu32_wayG_upd select + congr_cl32_wG_d(0) <= (congr_cl32_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu32_wayG_upd select + congr_cl32_wG_d(1) <= (congr_cl32_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu32_wayG_upd select + congr_cl32_wG_d(2) <= (congr_cl32_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu32_wayG_upd select + congr_cl32_wG_d(3) <= (congr_cl32_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu32_wayG_upd select + congr_cl32_wG_d(4) <= (congr_cl32_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu32_wayG_upd select + congr_cl32_wG_d(5) <= (congr_cl32_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu33_wayG_upd select + congr_cl33_wG_d(0) <= (congr_cl33_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu33_wayG_upd select + congr_cl33_wG_d(1) <= (congr_cl33_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu33_wayG_upd select + congr_cl33_wG_d(2) <= (congr_cl33_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu33_wayG_upd select + congr_cl33_wG_d(3) <= (congr_cl33_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu33_wayG_upd select + congr_cl33_wG_d(4) <= (congr_cl33_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu33_wayG_upd select + congr_cl33_wG_d(5) <= (congr_cl33_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu34_wayG_upd select + congr_cl34_wG_d(0) <= (congr_cl34_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu34_wayG_upd select + congr_cl34_wG_d(1) <= (congr_cl34_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu34_wayG_upd select + congr_cl34_wG_d(2) <= (congr_cl34_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu34_wayG_upd select + congr_cl34_wG_d(3) <= (congr_cl34_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu34_wayG_upd select + congr_cl34_wG_d(4) <= (congr_cl34_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu34_wayG_upd select + congr_cl34_wG_d(5) <= (congr_cl34_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu35_wayG_upd select + congr_cl35_wG_d(0) <= (congr_cl35_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu35_wayG_upd select + congr_cl35_wG_d(1) <= (congr_cl35_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu35_wayG_upd select + congr_cl35_wG_d(2) <= (congr_cl35_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu35_wayG_upd select + congr_cl35_wG_d(3) <= (congr_cl35_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu35_wayG_upd select + congr_cl35_wG_d(4) <= (congr_cl35_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu35_wayG_upd select + congr_cl35_wG_d(5) <= (congr_cl35_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu36_wayG_upd select + congr_cl36_wG_d(0) <= (congr_cl36_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu36_wayG_upd select + congr_cl36_wG_d(1) <= (congr_cl36_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu36_wayG_upd select + congr_cl36_wG_d(2) <= (congr_cl36_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu36_wayG_upd select + congr_cl36_wG_d(3) <= (congr_cl36_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu36_wayG_upd select + congr_cl36_wG_d(4) <= (congr_cl36_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu36_wayG_upd select + congr_cl36_wG_d(5) <= (congr_cl36_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu37_wayG_upd select + congr_cl37_wG_d(0) <= (congr_cl37_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu37_wayG_upd select + congr_cl37_wG_d(1) <= (congr_cl37_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu37_wayG_upd select + congr_cl37_wG_d(2) <= (congr_cl37_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu37_wayG_upd select + congr_cl37_wG_d(3) <= (congr_cl37_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu37_wayG_upd select + congr_cl37_wG_d(4) <= (congr_cl37_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu37_wayG_upd select + congr_cl37_wG_d(5) <= (congr_cl37_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu38_wayG_upd select + congr_cl38_wG_d(0) <= (congr_cl38_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu38_wayG_upd select + congr_cl38_wG_d(1) <= (congr_cl38_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu38_wayG_upd select + congr_cl38_wG_d(2) <= (congr_cl38_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu38_wayG_upd select + congr_cl38_wG_d(3) <= (congr_cl38_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu38_wayG_upd select + congr_cl38_wG_d(4) <= (congr_cl38_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu38_wayG_upd select + congr_cl38_wG_d(5) <= (congr_cl38_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu39_wayG_upd select + congr_cl39_wG_d(0) <= (congr_cl39_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu39_wayG_upd select + congr_cl39_wG_d(1) <= (congr_cl39_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu39_wayG_upd select + congr_cl39_wG_d(2) <= (congr_cl39_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu39_wayG_upd select + congr_cl39_wG_d(3) <= (congr_cl39_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu39_wayG_upd select + congr_cl39_wG_d(4) <= (congr_cl39_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu39_wayG_upd select + congr_cl39_wG_d(5) <= (congr_cl39_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu40_wayG_upd select + congr_cl40_wG_d(0) <= (congr_cl40_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu40_wayG_upd select + congr_cl40_wG_d(1) <= (congr_cl40_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu40_wayG_upd select + congr_cl40_wG_d(2) <= (congr_cl40_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu40_wayG_upd select + congr_cl40_wG_d(3) <= (congr_cl40_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu40_wayG_upd select + congr_cl40_wG_d(4) <= (congr_cl40_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu40_wayG_upd select + congr_cl40_wG_d(5) <= (congr_cl40_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu41_wayG_upd select + congr_cl41_wG_d(0) <= (congr_cl41_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu41_wayG_upd select + congr_cl41_wG_d(1) <= (congr_cl41_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu41_wayG_upd select + congr_cl41_wG_d(2) <= (congr_cl41_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu41_wayG_upd select + congr_cl41_wG_d(3) <= (congr_cl41_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu41_wayG_upd select + congr_cl41_wG_d(4) <= (congr_cl41_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu41_wayG_upd select + congr_cl41_wG_d(5) <= (congr_cl41_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu42_wayG_upd select + congr_cl42_wG_d(0) <= (congr_cl42_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu42_wayG_upd select + congr_cl42_wG_d(1) <= (congr_cl42_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu42_wayG_upd select + congr_cl42_wG_d(2) <= (congr_cl42_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu42_wayG_upd select + congr_cl42_wG_d(3) <= (congr_cl42_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu42_wayG_upd select + congr_cl42_wG_d(4) <= (congr_cl42_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu42_wayG_upd select + congr_cl42_wG_d(5) <= (congr_cl42_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu43_wayG_upd select + congr_cl43_wG_d(0) <= (congr_cl43_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu43_wayG_upd select + congr_cl43_wG_d(1) <= (congr_cl43_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu43_wayG_upd select + congr_cl43_wG_d(2) <= (congr_cl43_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu43_wayG_upd select + congr_cl43_wG_d(3) <= (congr_cl43_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu43_wayG_upd select + congr_cl43_wG_d(4) <= (congr_cl43_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu43_wayG_upd select + congr_cl43_wG_d(5) <= (congr_cl43_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu44_wayG_upd select + congr_cl44_wG_d(0) <= (congr_cl44_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu44_wayG_upd select + congr_cl44_wG_d(1) <= (congr_cl44_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu44_wayG_upd select + congr_cl44_wG_d(2) <= (congr_cl44_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu44_wayG_upd select + congr_cl44_wG_d(3) <= (congr_cl44_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu44_wayG_upd select + congr_cl44_wG_d(4) <= (congr_cl44_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu44_wayG_upd select + congr_cl44_wG_d(5) <= (congr_cl44_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu45_wayG_upd select + congr_cl45_wG_d(0) <= (congr_cl45_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu45_wayG_upd select + congr_cl45_wG_d(1) <= (congr_cl45_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu45_wayG_upd select + congr_cl45_wG_d(2) <= (congr_cl45_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu45_wayG_upd select + congr_cl45_wG_d(3) <= (congr_cl45_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu45_wayG_upd select + congr_cl45_wG_d(4) <= (congr_cl45_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu45_wayG_upd select + congr_cl45_wG_d(5) <= (congr_cl45_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu46_wayG_upd select + congr_cl46_wG_d(0) <= (congr_cl46_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu46_wayG_upd select + congr_cl46_wG_d(1) <= (congr_cl46_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu46_wayG_upd select + congr_cl46_wG_d(2) <= (congr_cl46_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu46_wayG_upd select + congr_cl46_wG_d(3) <= (congr_cl46_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu46_wayG_upd select + congr_cl46_wG_d(4) <= (congr_cl46_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu46_wayG_upd select + congr_cl46_wG_d(5) <= (congr_cl46_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu47_wayG_upd select + congr_cl47_wG_d(0) <= (congr_cl47_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu47_wayG_upd select + congr_cl47_wG_d(1) <= (congr_cl47_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu47_wayG_upd select + congr_cl47_wG_d(2) <= (congr_cl47_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu47_wayG_upd select + congr_cl47_wG_d(3) <= (congr_cl47_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu47_wayG_upd select + congr_cl47_wG_d(4) <= (congr_cl47_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu47_wayG_upd select + congr_cl47_wG_d(5) <= (congr_cl47_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu48_wayG_upd select + congr_cl48_wG_d(0) <= (congr_cl48_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu48_wayG_upd select + congr_cl48_wG_d(1) <= (congr_cl48_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu48_wayG_upd select + congr_cl48_wG_d(2) <= (congr_cl48_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu48_wayG_upd select + congr_cl48_wG_d(3) <= (congr_cl48_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu48_wayG_upd select + congr_cl48_wG_d(4) <= (congr_cl48_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu48_wayG_upd select + congr_cl48_wG_d(5) <= (congr_cl48_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu49_wayG_upd select + congr_cl49_wG_d(0) <= (congr_cl49_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu49_wayG_upd select + congr_cl49_wG_d(1) <= (congr_cl49_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu49_wayG_upd select + congr_cl49_wG_d(2) <= (congr_cl49_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu49_wayG_upd select + congr_cl49_wG_d(3) <= (congr_cl49_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu49_wayG_upd select + congr_cl49_wG_d(4) <= (congr_cl49_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu49_wayG_upd select + congr_cl49_wG_d(5) <= (congr_cl49_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu50_wayG_upd select + congr_cl50_wG_d(0) <= (congr_cl50_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu50_wayG_upd select + congr_cl50_wG_d(1) <= (congr_cl50_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu50_wayG_upd select + congr_cl50_wG_d(2) <= (congr_cl50_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu50_wayG_upd select + congr_cl50_wG_d(3) <= (congr_cl50_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu50_wayG_upd select + congr_cl50_wG_d(4) <= (congr_cl50_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu50_wayG_upd select + congr_cl50_wG_d(5) <= (congr_cl50_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu51_wayG_upd select + congr_cl51_wG_d(0) <= (congr_cl51_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu51_wayG_upd select + congr_cl51_wG_d(1) <= (congr_cl51_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu51_wayG_upd select + congr_cl51_wG_d(2) <= (congr_cl51_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu51_wayG_upd select + congr_cl51_wG_d(3) <= (congr_cl51_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu51_wayG_upd select + congr_cl51_wG_d(4) <= (congr_cl51_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu51_wayG_upd select + congr_cl51_wG_d(5) <= (congr_cl51_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu52_wayG_upd select + congr_cl52_wG_d(0) <= (congr_cl52_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu52_wayG_upd select + congr_cl52_wG_d(1) <= (congr_cl52_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu52_wayG_upd select + congr_cl52_wG_d(2) <= (congr_cl52_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu52_wayG_upd select + congr_cl52_wG_d(3) <= (congr_cl52_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu52_wayG_upd select + congr_cl52_wG_d(4) <= (congr_cl52_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu52_wayG_upd select + congr_cl52_wG_d(5) <= (congr_cl52_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu53_wayG_upd select + congr_cl53_wG_d(0) <= (congr_cl53_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu53_wayG_upd select + congr_cl53_wG_d(1) <= (congr_cl53_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu53_wayG_upd select + congr_cl53_wG_d(2) <= (congr_cl53_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu53_wayG_upd select + congr_cl53_wG_d(3) <= (congr_cl53_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu53_wayG_upd select + congr_cl53_wG_d(4) <= (congr_cl53_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu53_wayG_upd select + congr_cl53_wG_d(5) <= (congr_cl53_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu54_wayG_upd select + congr_cl54_wG_d(0) <= (congr_cl54_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu54_wayG_upd select + congr_cl54_wG_d(1) <= (congr_cl54_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu54_wayG_upd select + congr_cl54_wG_d(2) <= (congr_cl54_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu54_wayG_upd select + congr_cl54_wG_d(3) <= (congr_cl54_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu54_wayG_upd select + congr_cl54_wG_d(4) <= (congr_cl54_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu54_wayG_upd select + congr_cl54_wG_d(5) <= (congr_cl54_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu55_wayG_upd select + congr_cl55_wG_d(0) <= (congr_cl55_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu55_wayG_upd select + congr_cl55_wG_d(1) <= (congr_cl55_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu55_wayG_upd select + congr_cl55_wG_d(2) <= (congr_cl55_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu55_wayG_upd select + congr_cl55_wG_d(3) <= (congr_cl55_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu55_wayG_upd select + congr_cl55_wG_d(4) <= (congr_cl55_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu55_wayG_upd select + congr_cl55_wG_d(5) <= (congr_cl55_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu56_wayG_upd select + congr_cl56_wG_d(0) <= (congr_cl56_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu56_wayG_upd select + congr_cl56_wG_d(1) <= (congr_cl56_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu56_wayG_upd select + congr_cl56_wG_d(2) <= (congr_cl56_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu56_wayG_upd select + congr_cl56_wG_d(3) <= (congr_cl56_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu56_wayG_upd select + congr_cl56_wG_d(4) <= (congr_cl56_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu56_wayG_upd select + congr_cl56_wG_d(5) <= (congr_cl56_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu57_wayG_upd select + congr_cl57_wG_d(0) <= (congr_cl57_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu57_wayG_upd select + congr_cl57_wG_d(1) <= (congr_cl57_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu57_wayG_upd select + congr_cl57_wG_d(2) <= (congr_cl57_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu57_wayG_upd select + congr_cl57_wG_d(3) <= (congr_cl57_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu57_wayG_upd select + congr_cl57_wG_d(4) <= (congr_cl57_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu57_wayG_upd select + congr_cl57_wG_d(5) <= (congr_cl57_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu58_wayG_upd select + congr_cl58_wG_d(0) <= (congr_cl58_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu58_wayG_upd select + congr_cl58_wG_d(1) <= (congr_cl58_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu58_wayG_upd select + congr_cl58_wG_d(2) <= (congr_cl58_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu58_wayG_upd select + congr_cl58_wG_d(3) <= (congr_cl58_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu58_wayG_upd select + congr_cl58_wG_d(4) <= (congr_cl58_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu58_wayG_upd select + congr_cl58_wG_d(5) <= (congr_cl58_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu59_wayG_upd select + congr_cl59_wG_d(0) <= (congr_cl59_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu59_wayG_upd select + congr_cl59_wG_d(1) <= (congr_cl59_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu59_wayG_upd select + congr_cl59_wG_d(2) <= (congr_cl59_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu59_wayG_upd select + congr_cl59_wG_d(3) <= (congr_cl59_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu59_wayG_upd select + congr_cl59_wG_d(4) <= (congr_cl59_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu59_wayG_upd select + congr_cl59_wG_d(5) <= (congr_cl59_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu60_wayG_upd select + congr_cl60_wG_d(0) <= (congr_cl60_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu60_wayG_upd select + congr_cl60_wG_d(1) <= (congr_cl60_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu60_wayG_upd select + congr_cl60_wG_d(2) <= (congr_cl60_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu60_wayG_upd select + congr_cl60_wG_d(3) <= (congr_cl60_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu60_wayG_upd select + congr_cl60_wG_d(4) <= (congr_cl60_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu60_wayG_upd select + congr_cl60_wG_d(5) <= (congr_cl60_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu61_wayG_upd select + congr_cl61_wG_d(0) <= (congr_cl61_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu61_wayG_upd select + congr_cl61_wG_d(1) <= (congr_cl61_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu61_wayG_upd select + congr_cl61_wG_d(2) <= (congr_cl61_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu61_wayG_upd select + congr_cl61_wG_d(3) <= (congr_cl61_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu61_wayG_upd select + congr_cl61_wG_d(4) <= (congr_cl61_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu61_wayG_upd select + congr_cl61_wG_d(5) <= (congr_cl61_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu62_wayG_upd select + congr_cl62_wG_d(0) <= (congr_cl62_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu62_wayG_upd select + congr_cl62_wG_d(1) <= (congr_cl62_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu62_wayG_upd select + congr_cl62_wG_d(2) <= (congr_cl62_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu62_wayG_upd select + congr_cl62_wG_d(3) <= (congr_cl62_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu62_wayG_upd select + congr_cl62_wG_d(4) <= (congr_cl62_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu62_wayG_upd select + congr_cl62_wG_d(5) <= (congr_cl62_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu63_wayG_upd select + congr_cl63_wG_d(0) <= (congr_cl63_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu63_wayG_upd select + congr_cl63_wG_d(1) <= (congr_cl63_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +with rel_bixu63_wayG_upd select + congr_cl63_wG_d(2) <= (congr_cl63_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu63_wayG_upd select + congr_cl63_wG_d(3) <= (congr_cl63_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu63_wayG_upd select + congr_cl63_wG_d(4) <= (congr_cl63_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu63_wayG_upd select + congr_cl63_wG_d(5) <= (congr_cl63_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu0_wayH_upd select + congr_cl0_wH_d(0) <= (congr_cl0_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu0_wayH_upd select + congr_cl0_wH_d(1) <= (congr_cl0_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu0_wayH_upd select + congr_cl0_wH_d(2) <= (congr_cl0_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu0_wayH_upd select + congr_cl0_wH_d(3) <= (congr_cl0_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu0_wayH_upd select + congr_cl0_wH_d(4) <= (congr_cl0_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu0_wayH_upd select + congr_cl0_wH_d(5) <= (congr_cl0_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu1_wayH_upd select + congr_cl1_wH_d(0) <= (congr_cl1_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu1_wayH_upd select + congr_cl1_wH_d(1) <= (congr_cl1_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu1_wayH_upd select + congr_cl1_wH_d(2) <= (congr_cl1_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu1_wayH_upd select + congr_cl1_wH_d(3) <= (congr_cl1_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu1_wayH_upd select + congr_cl1_wH_d(4) <= (congr_cl1_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu1_wayH_upd select + congr_cl1_wH_d(5) <= (congr_cl1_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu2_wayH_upd select + congr_cl2_wH_d(0) <= (congr_cl2_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu2_wayH_upd select + congr_cl2_wH_d(1) <= (congr_cl2_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu2_wayH_upd select + congr_cl2_wH_d(2) <= (congr_cl2_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu2_wayH_upd select + congr_cl2_wH_d(3) <= (congr_cl2_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu2_wayH_upd select + congr_cl2_wH_d(4) <= (congr_cl2_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu2_wayH_upd select + congr_cl2_wH_d(5) <= (congr_cl2_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu3_wayH_upd select + congr_cl3_wH_d(0) <= (congr_cl3_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu3_wayH_upd select + congr_cl3_wH_d(1) <= (congr_cl3_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu3_wayH_upd select + congr_cl3_wH_d(2) <= (congr_cl3_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu3_wayH_upd select + congr_cl3_wH_d(3) <= (congr_cl3_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu3_wayH_upd select + congr_cl3_wH_d(4) <= (congr_cl3_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu3_wayH_upd select + congr_cl3_wH_d(5) <= (congr_cl3_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu4_wayH_upd select + congr_cl4_wH_d(0) <= (congr_cl4_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu4_wayH_upd select + congr_cl4_wH_d(1) <= (congr_cl4_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu4_wayH_upd select + congr_cl4_wH_d(2) <= (congr_cl4_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu4_wayH_upd select + congr_cl4_wH_d(3) <= (congr_cl4_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu4_wayH_upd select + congr_cl4_wH_d(4) <= (congr_cl4_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu4_wayH_upd select + congr_cl4_wH_d(5) <= (congr_cl4_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu5_wayH_upd select + congr_cl5_wH_d(0) <= (congr_cl5_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu5_wayH_upd select + congr_cl5_wH_d(1) <= (congr_cl5_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu5_wayH_upd select + congr_cl5_wH_d(2) <= (congr_cl5_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu5_wayH_upd select + congr_cl5_wH_d(3) <= (congr_cl5_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu5_wayH_upd select + congr_cl5_wH_d(4) <= (congr_cl5_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu5_wayH_upd select + congr_cl5_wH_d(5) <= (congr_cl5_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu6_wayH_upd select + congr_cl6_wH_d(0) <= (congr_cl6_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu6_wayH_upd select + congr_cl6_wH_d(1) <= (congr_cl6_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu6_wayH_upd select + congr_cl6_wH_d(2) <= (congr_cl6_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu6_wayH_upd select + congr_cl6_wH_d(3) <= (congr_cl6_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu6_wayH_upd select + congr_cl6_wH_d(4) <= (congr_cl6_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu6_wayH_upd select + congr_cl6_wH_d(5) <= (congr_cl6_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu7_wayH_upd select + congr_cl7_wH_d(0) <= (congr_cl7_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu7_wayH_upd select + congr_cl7_wH_d(1) <= (congr_cl7_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu7_wayH_upd select + congr_cl7_wH_d(2) <= (congr_cl7_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu7_wayH_upd select + congr_cl7_wH_d(3) <= (congr_cl7_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu7_wayH_upd select + congr_cl7_wH_d(4) <= (congr_cl7_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu7_wayH_upd select + congr_cl7_wH_d(5) <= (congr_cl7_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu8_wayH_upd select + congr_cl8_wH_d(0) <= (congr_cl8_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu8_wayH_upd select + congr_cl8_wH_d(1) <= (congr_cl8_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu8_wayH_upd select + congr_cl8_wH_d(2) <= (congr_cl8_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu8_wayH_upd select + congr_cl8_wH_d(3) <= (congr_cl8_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu8_wayH_upd select + congr_cl8_wH_d(4) <= (congr_cl8_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu8_wayH_upd select + congr_cl8_wH_d(5) <= (congr_cl8_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu9_wayH_upd select + congr_cl9_wH_d(0) <= (congr_cl9_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu9_wayH_upd select + congr_cl9_wH_d(1) <= (congr_cl9_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu9_wayH_upd select + congr_cl9_wH_d(2) <= (congr_cl9_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu9_wayH_upd select + congr_cl9_wH_d(3) <= (congr_cl9_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu9_wayH_upd select + congr_cl9_wH_d(4) <= (congr_cl9_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu9_wayH_upd select + congr_cl9_wH_d(5) <= (congr_cl9_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu10_wayH_upd select + congr_cl10_wH_d(0) <= (congr_cl10_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu10_wayH_upd select + congr_cl10_wH_d(1) <= (congr_cl10_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu10_wayH_upd select + congr_cl10_wH_d(2) <= (congr_cl10_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu10_wayH_upd select + congr_cl10_wH_d(3) <= (congr_cl10_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu10_wayH_upd select + congr_cl10_wH_d(4) <= (congr_cl10_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu10_wayH_upd select + congr_cl10_wH_d(5) <= (congr_cl10_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu11_wayH_upd select + congr_cl11_wH_d(0) <= (congr_cl11_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu11_wayH_upd select + congr_cl11_wH_d(1) <= (congr_cl11_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu11_wayH_upd select + congr_cl11_wH_d(2) <= (congr_cl11_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu11_wayH_upd select + congr_cl11_wH_d(3) <= (congr_cl11_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu11_wayH_upd select + congr_cl11_wH_d(4) <= (congr_cl11_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu11_wayH_upd select + congr_cl11_wH_d(5) <= (congr_cl11_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu12_wayH_upd select + congr_cl12_wH_d(0) <= (congr_cl12_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu12_wayH_upd select + congr_cl12_wH_d(1) <= (congr_cl12_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu12_wayH_upd select + congr_cl12_wH_d(2) <= (congr_cl12_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu12_wayH_upd select + congr_cl12_wH_d(3) <= (congr_cl12_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu12_wayH_upd select + congr_cl12_wH_d(4) <= (congr_cl12_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu12_wayH_upd select + congr_cl12_wH_d(5) <= (congr_cl12_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu13_wayH_upd select + congr_cl13_wH_d(0) <= (congr_cl13_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu13_wayH_upd select + congr_cl13_wH_d(1) <= (congr_cl13_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu13_wayH_upd select + congr_cl13_wH_d(2) <= (congr_cl13_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu13_wayH_upd select + congr_cl13_wH_d(3) <= (congr_cl13_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu13_wayH_upd select + congr_cl13_wH_d(4) <= (congr_cl13_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu13_wayH_upd select + congr_cl13_wH_d(5) <= (congr_cl13_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu14_wayH_upd select + congr_cl14_wH_d(0) <= (congr_cl14_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu14_wayH_upd select + congr_cl14_wH_d(1) <= (congr_cl14_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu14_wayH_upd select + congr_cl14_wH_d(2) <= (congr_cl14_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu14_wayH_upd select + congr_cl14_wH_d(3) <= (congr_cl14_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu14_wayH_upd select + congr_cl14_wH_d(4) <= (congr_cl14_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu14_wayH_upd select + congr_cl14_wH_d(5) <= (congr_cl14_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu15_wayH_upd select + congr_cl15_wH_d(0) <= (congr_cl15_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu15_wayH_upd select + congr_cl15_wH_d(1) <= (congr_cl15_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu15_wayH_upd select + congr_cl15_wH_d(2) <= (congr_cl15_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu15_wayH_upd select + congr_cl15_wH_d(3) <= (congr_cl15_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu15_wayH_upd select + congr_cl15_wH_d(4) <= (congr_cl15_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu15_wayH_upd select + congr_cl15_wH_d(5) <= (congr_cl15_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu16_wayH_upd select + congr_cl16_wH_d(0) <= (congr_cl16_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu16_wayH_upd select + congr_cl16_wH_d(1) <= (congr_cl16_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu16_wayH_upd select + congr_cl16_wH_d(2) <= (congr_cl16_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu16_wayH_upd select + congr_cl16_wH_d(3) <= (congr_cl16_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu16_wayH_upd select + congr_cl16_wH_d(4) <= (congr_cl16_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu16_wayH_upd select + congr_cl16_wH_d(5) <= (congr_cl16_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu17_wayH_upd select + congr_cl17_wH_d(0) <= (congr_cl17_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu17_wayH_upd select + congr_cl17_wH_d(1) <= (congr_cl17_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu17_wayH_upd select + congr_cl17_wH_d(2) <= (congr_cl17_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu17_wayH_upd select + congr_cl17_wH_d(3) <= (congr_cl17_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu17_wayH_upd select + congr_cl17_wH_d(4) <= (congr_cl17_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu17_wayH_upd select + congr_cl17_wH_d(5) <= (congr_cl17_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu18_wayH_upd select + congr_cl18_wH_d(0) <= (congr_cl18_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu18_wayH_upd select + congr_cl18_wH_d(1) <= (congr_cl18_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu18_wayH_upd select + congr_cl18_wH_d(2) <= (congr_cl18_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu18_wayH_upd select + congr_cl18_wH_d(3) <= (congr_cl18_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu18_wayH_upd select + congr_cl18_wH_d(4) <= (congr_cl18_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu18_wayH_upd select + congr_cl18_wH_d(5) <= (congr_cl18_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu19_wayH_upd select + congr_cl19_wH_d(0) <= (congr_cl19_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu19_wayH_upd select + congr_cl19_wH_d(1) <= (congr_cl19_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu19_wayH_upd select + congr_cl19_wH_d(2) <= (congr_cl19_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu19_wayH_upd select + congr_cl19_wH_d(3) <= (congr_cl19_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu19_wayH_upd select + congr_cl19_wH_d(4) <= (congr_cl19_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu19_wayH_upd select + congr_cl19_wH_d(5) <= (congr_cl19_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu20_wayH_upd select + congr_cl20_wH_d(0) <= (congr_cl20_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu20_wayH_upd select + congr_cl20_wH_d(1) <= (congr_cl20_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu20_wayH_upd select + congr_cl20_wH_d(2) <= (congr_cl20_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu20_wayH_upd select + congr_cl20_wH_d(3) <= (congr_cl20_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu20_wayH_upd select + congr_cl20_wH_d(4) <= (congr_cl20_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu20_wayH_upd select + congr_cl20_wH_d(5) <= (congr_cl20_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu21_wayH_upd select + congr_cl21_wH_d(0) <= (congr_cl21_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu21_wayH_upd select + congr_cl21_wH_d(1) <= (congr_cl21_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu21_wayH_upd select + congr_cl21_wH_d(2) <= (congr_cl21_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu21_wayH_upd select + congr_cl21_wH_d(3) <= (congr_cl21_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu21_wayH_upd select + congr_cl21_wH_d(4) <= (congr_cl21_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu21_wayH_upd select + congr_cl21_wH_d(5) <= (congr_cl21_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu22_wayH_upd select + congr_cl22_wH_d(0) <= (congr_cl22_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu22_wayH_upd select + congr_cl22_wH_d(1) <= (congr_cl22_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu22_wayH_upd select + congr_cl22_wH_d(2) <= (congr_cl22_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu22_wayH_upd select + congr_cl22_wH_d(3) <= (congr_cl22_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu22_wayH_upd select + congr_cl22_wH_d(4) <= (congr_cl22_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu22_wayH_upd select + congr_cl22_wH_d(5) <= (congr_cl22_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu23_wayH_upd select + congr_cl23_wH_d(0) <= (congr_cl23_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu23_wayH_upd select + congr_cl23_wH_d(1) <= (congr_cl23_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu23_wayH_upd select + congr_cl23_wH_d(2) <= (congr_cl23_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu23_wayH_upd select + congr_cl23_wH_d(3) <= (congr_cl23_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu23_wayH_upd select + congr_cl23_wH_d(4) <= (congr_cl23_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu23_wayH_upd select + congr_cl23_wH_d(5) <= (congr_cl23_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu24_wayH_upd select + congr_cl24_wH_d(0) <= (congr_cl24_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu24_wayH_upd select + congr_cl24_wH_d(1) <= (congr_cl24_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu24_wayH_upd select + congr_cl24_wH_d(2) <= (congr_cl24_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu24_wayH_upd select + congr_cl24_wH_d(3) <= (congr_cl24_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu24_wayH_upd select + congr_cl24_wH_d(4) <= (congr_cl24_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu24_wayH_upd select + congr_cl24_wH_d(5) <= (congr_cl24_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu25_wayH_upd select + congr_cl25_wH_d(0) <= (congr_cl25_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu25_wayH_upd select + congr_cl25_wH_d(1) <= (congr_cl25_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu25_wayH_upd select + congr_cl25_wH_d(2) <= (congr_cl25_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu25_wayH_upd select + congr_cl25_wH_d(3) <= (congr_cl25_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu25_wayH_upd select + congr_cl25_wH_d(4) <= (congr_cl25_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu25_wayH_upd select + congr_cl25_wH_d(5) <= (congr_cl25_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu26_wayH_upd select + congr_cl26_wH_d(0) <= (congr_cl26_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu26_wayH_upd select + congr_cl26_wH_d(1) <= (congr_cl26_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu26_wayH_upd select + congr_cl26_wH_d(2) <= (congr_cl26_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu26_wayH_upd select + congr_cl26_wH_d(3) <= (congr_cl26_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu26_wayH_upd select + congr_cl26_wH_d(4) <= (congr_cl26_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu26_wayH_upd select + congr_cl26_wH_d(5) <= (congr_cl26_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu27_wayH_upd select + congr_cl27_wH_d(0) <= (congr_cl27_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu27_wayH_upd select + congr_cl27_wH_d(1) <= (congr_cl27_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu27_wayH_upd select + congr_cl27_wH_d(2) <= (congr_cl27_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu27_wayH_upd select + congr_cl27_wH_d(3) <= (congr_cl27_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu27_wayH_upd select + congr_cl27_wH_d(4) <= (congr_cl27_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu27_wayH_upd select + congr_cl27_wH_d(5) <= (congr_cl27_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu28_wayH_upd select + congr_cl28_wH_d(0) <= (congr_cl28_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu28_wayH_upd select + congr_cl28_wH_d(1) <= (congr_cl28_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu28_wayH_upd select + congr_cl28_wH_d(2) <= (congr_cl28_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu28_wayH_upd select + congr_cl28_wH_d(3) <= (congr_cl28_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu28_wayH_upd select + congr_cl28_wH_d(4) <= (congr_cl28_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu28_wayH_upd select + congr_cl28_wH_d(5) <= (congr_cl28_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu29_wayH_upd select + congr_cl29_wH_d(0) <= (congr_cl29_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu29_wayH_upd select + congr_cl29_wH_d(1) <= (congr_cl29_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu29_wayH_upd select + congr_cl29_wH_d(2) <= (congr_cl29_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu29_wayH_upd select + congr_cl29_wH_d(3) <= (congr_cl29_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu29_wayH_upd select + congr_cl29_wH_d(4) <= (congr_cl29_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu29_wayH_upd select + congr_cl29_wH_d(5) <= (congr_cl29_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu30_wayH_upd select + congr_cl30_wH_d(0) <= (congr_cl30_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu30_wayH_upd select + congr_cl30_wH_d(1) <= (congr_cl30_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu30_wayH_upd select + congr_cl30_wH_d(2) <= (congr_cl30_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu30_wayH_upd select + congr_cl30_wH_d(3) <= (congr_cl30_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu30_wayH_upd select + congr_cl30_wH_d(4) <= (congr_cl30_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu30_wayH_upd select + congr_cl30_wH_d(5) <= (congr_cl30_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu31_wayH_upd select + congr_cl31_wH_d(0) <= (congr_cl31_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu31_wayH_upd select + congr_cl31_wH_d(1) <= (congr_cl31_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu31_wayH_upd select + congr_cl31_wH_d(2) <= (congr_cl31_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu31_wayH_upd select + congr_cl31_wH_d(3) <= (congr_cl31_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu31_wayH_upd select + congr_cl31_wH_d(4) <= (congr_cl31_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu31_wayH_upd select + congr_cl31_wH_d(5) <= (congr_cl31_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu32_wayH_upd select + congr_cl32_wH_d(0) <= (congr_cl32_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu32_wayH_upd select + congr_cl32_wH_d(1) <= (congr_cl32_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu32_wayH_upd select + congr_cl32_wH_d(2) <= (congr_cl32_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu32_wayH_upd select + congr_cl32_wH_d(3) <= (congr_cl32_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu32_wayH_upd select + congr_cl32_wH_d(4) <= (congr_cl32_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu32_wayH_upd select + congr_cl32_wH_d(5) <= (congr_cl32_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu33_wayH_upd select + congr_cl33_wH_d(0) <= (congr_cl33_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu33_wayH_upd select + congr_cl33_wH_d(1) <= (congr_cl33_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu33_wayH_upd select + congr_cl33_wH_d(2) <= (congr_cl33_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu33_wayH_upd select + congr_cl33_wH_d(3) <= (congr_cl33_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu33_wayH_upd select + congr_cl33_wH_d(4) <= (congr_cl33_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu33_wayH_upd select + congr_cl33_wH_d(5) <= (congr_cl33_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu34_wayH_upd select + congr_cl34_wH_d(0) <= (congr_cl34_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu34_wayH_upd select + congr_cl34_wH_d(1) <= (congr_cl34_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu34_wayH_upd select + congr_cl34_wH_d(2) <= (congr_cl34_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu34_wayH_upd select + congr_cl34_wH_d(3) <= (congr_cl34_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu34_wayH_upd select + congr_cl34_wH_d(4) <= (congr_cl34_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu34_wayH_upd select + congr_cl34_wH_d(5) <= (congr_cl34_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu35_wayH_upd select + congr_cl35_wH_d(0) <= (congr_cl35_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu35_wayH_upd select + congr_cl35_wH_d(1) <= (congr_cl35_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu35_wayH_upd select + congr_cl35_wH_d(2) <= (congr_cl35_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu35_wayH_upd select + congr_cl35_wH_d(3) <= (congr_cl35_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu35_wayH_upd select + congr_cl35_wH_d(4) <= (congr_cl35_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu35_wayH_upd select + congr_cl35_wH_d(5) <= (congr_cl35_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu36_wayH_upd select + congr_cl36_wH_d(0) <= (congr_cl36_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu36_wayH_upd select + congr_cl36_wH_d(1) <= (congr_cl36_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu36_wayH_upd select + congr_cl36_wH_d(2) <= (congr_cl36_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu36_wayH_upd select + congr_cl36_wH_d(3) <= (congr_cl36_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu36_wayH_upd select + congr_cl36_wH_d(4) <= (congr_cl36_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu36_wayH_upd select + congr_cl36_wH_d(5) <= (congr_cl36_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu37_wayH_upd select + congr_cl37_wH_d(0) <= (congr_cl37_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu37_wayH_upd select + congr_cl37_wH_d(1) <= (congr_cl37_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu37_wayH_upd select + congr_cl37_wH_d(2) <= (congr_cl37_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu37_wayH_upd select + congr_cl37_wH_d(3) <= (congr_cl37_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu37_wayH_upd select + congr_cl37_wH_d(4) <= (congr_cl37_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu37_wayH_upd select + congr_cl37_wH_d(5) <= (congr_cl37_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu38_wayH_upd select + congr_cl38_wH_d(0) <= (congr_cl38_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu38_wayH_upd select + congr_cl38_wH_d(1) <= (congr_cl38_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu38_wayH_upd select + congr_cl38_wH_d(2) <= (congr_cl38_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu38_wayH_upd select + congr_cl38_wH_d(3) <= (congr_cl38_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu38_wayH_upd select + congr_cl38_wH_d(4) <= (congr_cl38_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu38_wayH_upd select + congr_cl38_wH_d(5) <= (congr_cl38_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu39_wayH_upd select + congr_cl39_wH_d(0) <= (congr_cl39_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu39_wayH_upd select + congr_cl39_wH_d(1) <= (congr_cl39_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu39_wayH_upd select + congr_cl39_wH_d(2) <= (congr_cl39_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu39_wayH_upd select + congr_cl39_wH_d(3) <= (congr_cl39_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu39_wayH_upd select + congr_cl39_wH_d(4) <= (congr_cl39_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu39_wayH_upd select + congr_cl39_wH_d(5) <= (congr_cl39_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu40_wayH_upd select + congr_cl40_wH_d(0) <= (congr_cl40_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu40_wayH_upd select + congr_cl40_wH_d(1) <= (congr_cl40_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu40_wayH_upd select + congr_cl40_wH_d(2) <= (congr_cl40_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu40_wayH_upd select + congr_cl40_wH_d(3) <= (congr_cl40_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu40_wayH_upd select + congr_cl40_wH_d(4) <= (congr_cl40_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu40_wayH_upd select + congr_cl40_wH_d(5) <= (congr_cl40_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu41_wayH_upd select + congr_cl41_wH_d(0) <= (congr_cl41_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu41_wayH_upd select + congr_cl41_wH_d(1) <= (congr_cl41_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu41_wayH_upd select + congr_cl41_wH_d(2) <= (congr_cl41_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu41_wayH_upd select + congr_cl41_wH_d(3) <= (congr_cl41_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu41_wayH_upd select + congr_cl41_wH_d(4) <= (congr_cl41_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu41_wayH_upd select + congr_cl41_wH_d(5) <= (congr_cl41_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu42_wayH_upd select + congr_cl42_wH_d(0) <= (congr_cl42_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu42_wayH_upd select + congr_cl42_wH_d(1) <= (congr_cl42_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu42_wayH_upd select + congr_cl42_wH_d(2) <= (congr_cl42_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu42_wayH_upd select + congr_cl42_wH_d(3) <= (congr_cl42_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu42_wayH_upd select + congr_cl42_wH_d(4) <= (congr_cl42_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu42_wayH_upd select + congr_cl42_wH_d(5) <= (congr_cl42_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu43_wayH_upd select + congr_cl43_wH_d(0) <= (congr_cl43_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu43_wayH_upd select + congr_cl43_wH_d(1) <= (congr_cl43_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu43_wayH_upd select + congr_cl43_wH_d(2) <= (congr_cl43_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu43_wayH_upd select + congr_cl43_wH_d(3) <= (congr_cl43_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu43_wayH_upd select + congr_cl43_wH_d(4) <= (congr_cl43_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu43_wayH_upd select + congr_cl43_wH_d(5) <= (congr_cl43_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu44_wayH_upd select + congr_cl44_wH_d(0) <= (congr_cl44_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu44_wayH_upd select + congr_cl44_wH_d(1) <= (congr_cl44_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu44_wayH_upd select + congr_cl44_wH_d(2) <= (congr_cl44_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu44_wayH_upd select + congr_cl44_wH_d(3) <= (congr_cl44_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu44_wayH_upd select + congr_cl44_wH_d(4) <= (congr_cl44_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu44_wayH_upd select + congr_cl44_wH_d(5) <= (congr_cl44_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu45_wayH_upd select + congr_cl45_wH_d(0) <= (congr_cl45_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu45_wayH_upd select + congr_cl45_wH_d(1) <= (congr_cl45_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu45_wayH_upd select + congr_cl45_wH_d(2) <= (congr_cl45_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu45_wayH_upd select + congr_cl45_wH_d(3) <= (congr_cl45_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu45_wayH_upd select + congr_cl45_wH_d(4) <= (congr_cl45_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu45_wayH_upd select + congr_cl45_wH_d(5) <= (congr_cl45_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu46_wayH_upd select + congr_cl46_wH_d(0) <= (congr_cl46_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu46_wayH_upd select + congr_cl46_wH_d(1) <= (congr_cl46_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu46_wayH_upd select + congr_cl46_wH_d(2) <= (congr_cl46_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu46_wayH_upd select + congr_cl46_wH_d(3) <= (congr_cl46_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu46_wayH_upd select + congr_cl46_wH_d(4) <= (congr_cl46_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu46_wayH_upd select + congr_cl46_wH_d(5) <= (congr_cl46_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu47_wayH_upd select + congr_cl47_wH_d(0) <= (congr_cl47_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu47_wayH_upd select + congr_cl47_wH_d(1) <= (congr_cl47_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu47_wayH_upd select + congr_cl47_wH_d(2) <= (congr_cl47_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu47_wayH_upd select + congr_cl47_wH_d(3) <= (congr_cl47_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu47_wayH_upd select + congr_cl47_wH_d(4) <= (congr_cl47_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu47_wayH_upd select + congr_cl47_wH_d(5) <= (congr_cl47_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu48_wayH_upd select + congr_cl48_wH_d(0) <= (congr_cl48_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu48_wayH_upd select + congr_cl48_wH_d(1) <= (congr_cl48_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu48_wayH_upd select + congr_cl48_wH_d(2) <= (congr_cl48_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu48_wayH_upd select + congr_cl48_wH_d(3) <= (congr_cl48_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu48_wayH_upd select + congr_cl48_wH_d(4) <= (congr_cl48_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu48_wayH_upd select + congr_cl48_wH_d(5) <= (congr_cl48_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu49_wayH_upd select + congr_cl49_wH_d(0) <= (congr_cl49_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu49_wayH_upd select + congr_cl49_wH_d(1) <= (congr_cl49_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu49_wayH_upd select + congr_cl49_wH_d(2) <= (congr_cl49_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu49_wayH_upd select + congr_cl49_wH_d(3) <= (congr_cl49_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu49_wayH_upd select + congr_cl49_wH_d(4) <= (congr_cl49_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu49_wayH_upd select + congr_cl49_wH_d(5) <= (congr_cl49_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu50_wayH_upd select + congr_cl50_wH_d(0) <= (congr_cl50_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu50_wayH_upd select + congr_cl50_wH_d(1) <= (congr_cl50_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu50_wayH_upd select + congr_cl50_wH_d(2) <= (congr_cl50_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu50_wayH_upd select + congr_cl50_wH_d(3) <= (congr_cl50_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu50_wayH_upd select + congr_cl50_wH_d(4) <= (congr_cl50_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu50_wayH_upd select + congr_cl50_wH_d(5) <= (congr_cl50_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu51_wayH_upd select + congr_cl51_wH_d(0) <= (congr_cl51_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu51_wayH_upd select + congr_cl51_wH_d(1) <= (congr_cl51_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu51_wayH_upd select + congr_cl51_wH_d(2) <= (congr_cl51_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu51_wayH_upd select + congr_cl51_wH_d(3) <= (congr_cl51_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu51_wayH_upd select + congr_cl51_wH_d(4) <= (congr_cl51_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu51_wayH_upd select + congr_cl51_wH_d(5) <= (congr_cl51_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu52_wayH_upd select + congr_cl52_wH_d(0) <= (congr_cl52_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu52_wayH_upd select + congr_cl52_wH_d(1) <= (congr_cl52_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu52_wayH_upd select + congr_cl52_wH_d(2) <= (congr_cl52_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu52_wayH_upd select + congr_cl52_wH_d(3) <= (congr_cl52_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu52_wayH_upd select + congr_cl52_wH_d(4) <= (congr_cl52_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu52_wayH_upd select + congr_cl52_wH_d(5) <= (congr_cl52_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu53_wayH_upd select + congr_cl53_wH_d(0) <= (congr_cl53_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu53_wayH_upd select + congr_cl53_wH_d(1) <= (congr_cl53_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu53_wayH_upd select + congr_cl53_wH_d(2) <= (congr_cl53_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu53_wayH_upd select + congr_cl53_wH_d(3) <= (congr_cl53_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu53_wayH_upd select + congr_cl53_wH_d(4) <= (congr_cl53_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu53_wayH_upd select + congr_cl53_wH_d(5) <= (congr_cl53_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu54_wayH_upd select + congr_cl54_wH_d(0) <= (congr_cl54_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu54_wayH_upd select + congr_cl54_wH_d(1) <= (congr_cl54_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu54_wayH_upd select + congr_cl54_wH_d(2) <= (congr_cl54_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu54_wayH_upd select + congr_cl54_wH_d(3) <= (congr_cl54_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu54_wayH_upd select + congr_cl54_wH_d(4) <= (congr_cl54_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu54_wayH_upd select + congr_cl54_wH_d(5) <= (congr_cl54_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu55_wayH_upd select + congr_cl55_wH_d(0) <= (congr_cl55_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu55_wayH_upd select + congr_cl55_wH_d(1) <= (congr_cl55_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu55_wayH_upd select + congr_cl55_wH_d(2) <= (congr_cl55_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu55_wayH_upd select + congr_cl55_wH_d(3) <= (congr_cl55_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu55_wayH_upd select + congr_cl55_wH_d(4) <= (congr_cl55_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu55_wayH_upd select + congr_cl55_wH_d(5) <= (congr_cl55_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu56_wayH_upd select + congr_cl56_wH_d(0) <= (congr_cl56_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu56_wayH_upd select + congr_cl56_wH_d(1) <= (congr_cl56_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu56_wayH_upd select + congr_cl56_wH_d(2) <= (congr_cl56_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu56_wayH_upd select + congr_cl56_wH_d(3) <= (congr_cl56_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu56_wayH_upd select + congr_cl56_wH_d(4) <= (congr_cl56_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu56_wayH_upd select + congr_cl56_wH_d(5) <= (congr_cl56_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu57_wayH_upd select + congr_cl57_wH_d(0) <= (congr_cl57_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu57_wayH_upd select + congr_cl57_wH_d(1) <= (congr_cl57_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu57_wayH_upd select + congr_cl57_wH_d(2) <= (congr_cl57_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu57_wayH_upd select + congr_cl57_wH_d(3) <= (congr_cl57_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu57_wayH_upd select + congr_cl57_wH_d(4) <= (congr_cl57_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu57_wayH_upd select + congr_cl57_wH_d(5) <= (congr_cl57_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu58_wayH_upd select + congr_cl58_wH_d(0) <= (congr_cl58_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu58_wayH_upd select + congr_cl58_wH_d(1) <= (congr_cl58_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu58_wayH_upd select + congr_cl58_wH_d(2) <= (congr_cl58_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu58_wayH_upd select + congr_cl58_wH_d(3) <= (congr_cl58_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu58_wayH_upd select + congr_cl58_wH_d(4) <= (congr_cl58_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu58_wayH_upd select + congr_cl58_wH_d(5) <= (congr_cl58_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu59_wayH_upd select + congr_cl59_wH_d(0) <= (congr_cl59_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu59_wayH_upd select + congr_cl59_wH_d(1) <= (congr_cl59_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu59_wayH_upd select + congr_cl59_wH_d(2) <= (congr_cl59_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu59_wayH_upd select + congr_cl59_wH_d(3) <= (congr_cl59_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu59_wayH_upd select + congr_cl59_wH_d(4) <= (congr_cl59_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu59_wayH_upd select + congr_cl59_wH_d(5) <= (congr_cl59_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu60_wayH_upd select + congr_cl60_wH_d(0) <= (congr_cl60_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu60_wayH_upd select + congr_cl60_wH_d(1) <= (congr_cl60_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu60_wayH_upd select + congr_cl60_wH_d(2) <= (congr_cl60_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu60_wayH_upd select + congr_cl60_wH_d(3) <= (congr_cl60_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu60_wayH_upd select + congr_cl60_wH_d(4) <= (congr_cl60_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu60_wayH_upd select + congr_cl60_wH_d(5) <= (congr_cl60_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu61_wayH_upd select + congr_cl61_wH_d(0) <= (congr_cl61_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu61_wayH_upd select + congr_cl61_wH_d(1) <= (congr_cl61_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu61_wayH_upd select + congr_cl61_wH_d(2) <= (congr_cl61_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu61_wayH_upd select + congr_cl61_wH_d(3) <= (congr_cl61_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu61_wayH_upd select + congr_cl61_wH_d(4) <= (congr_cl61_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu61_wayH_upd select + congr_cl61_wH_d(5) <= (congr_cl61_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu62_wayH_upd select + congr_cl62_wH_d(0) <= (congr_cl62_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu62_wayH_upd select + congr_cl62_wH_d(1) <= (congr_cl62_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu62_wayH_upd select + congr_cl62_wH_d(2) <= (congr_cl62_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu62_wayH_upd select + congr_cl62_wH_d(3) <= (congr_cl62_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu62_wayH_upd select + congr_cl62_wH_d(4) <= (congr_cl62_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu62_wayH_upd select + congr_cl62_wH_d(5) <= (congr_cl62_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with rel_bixu63_wayH_upd select + congr_cl63_wH_d(0) <= (congr_cl63_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +with rel_bixu63_wayH_upd select + congr_cl63_wH_d(1) <= (congr_cl63_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +with rel_bixu63_wayH_upd select + congr_cl63_wH_d(2) <= (congr_cl63_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +with rel_bixu63_wayH_upd select + congr_cl63_wH_d(3) <= (congr_cl63_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +with rel_bixu63_wayH_upd select + congr_cl63_wH_d(4) <= (congr_cl63_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +with rel_bixu63_wayH_upd select + congr_cl63_wH_d(5) <= (congr_cl63_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +with stm_upd_watchlost_tid0 select + stm_watchlost(0) <= stm_watchlost_state_q(0) when "00", + binv5_ex5_lost_watch_upd(0) when "01", + rel_lost_watch_upd_q(0) when others; +stm_upd_watchlost_tid0 <= rel_watchlost_upd(0) & ex5_watchlost_upd(0); +with stm_upd_watchlost_tid1 select + stm_watchlost(1) <= stm_watchlost_state_q(1) when "00", + binv5_ex5_lost_watch_upd(1) when "01", + rel_lost_watch_upd_q(1) when others; +stm_upd_watchlost_tid1 <= rel_watchlost_upd(1) & ex5_watchlost_upd(1); +with stm_upd_watchlost_tid2 select + stm_watchlost(2) <= stm_watchlost_state_q(2) when "00", + binv5_ex5_lost_watch_upd(2) when "01", + rel_lost_watch_upd_q(2) when others; +stm_upd_watchlost_tid2 <= rel_watchlost_upd(2) & ex5_watchlost_upd(2); +with stm_upd_watchlost_tid3 select + stm_watchlost(3) <= stm_watchlost_state_q(3) when "00", + binv5_ex5_lost_watch_upd(3) when "01", + rel_lost_watch_upd_q(3) when others; +stm_upd_watchlost_tid3 <= rel_watchlost_upd(3) & ex5_watchlost_upd(3); +rel_watchlost_upd <= rel_lost_watch_upd_q; +ex5_watchlost_upd <= gate(ex5_watchlost_set_q, p0_wren_d) or binv5_inval_watch_val_q or dci_watch_lost; +binv5_ex5_lost_watch_upd <= ex5_lost_watch_upd_q or binv5_inval_watch_val_q or dci_watch_lost; +stm_watchlost_state_d <= stm_watchlost; +rel4_l1dump_val_q <= not my_spare0_latches_q(0); +my_spare0_latches_d(0) <= rel3_l1dump_val; +my_spare0_latches_d(1 TO 16) <= not my_spare0_latches_q(1 to 16); +my_spare1_latches_d <= not my_spare1_latches_q; +ex4_way_a_hit <= ex4_way_hit_q(0); +ex4_way_b_hit <= ex4_way_hit_q(1); +ex4_way_c_hit <= ex4_way_hit_q(2); +ex4_way_d_hit <= ex4_way_hit_q(3); +ex4_way_e_hit <= ex4_way_hit_q(4); +ex4_way_f_hit <= ex4_way_hit_q(5); +ex4_way_g_hit <= ex4_way_hit_q(6); +ex4_way_h_hit <= ex4_way_hit_q(7); +ex4_way_a_dir <= ex4_wayA_val_q; +ex4_way_b_dir <= ex4_wayB_val_q; +ex4_way_c_dir <= ex4_wayC_val_q; +ex4_way_d_dir <= ex4_wayD_val_q; +ex4_way_e_dir <= ex4_wayE_val_q; +ex4_way_f_dir <= ex4_wayF_val_q; +ex4_way_g_dir <= ex4_wayG_val_q; +ex4_way_h_dir <= ex4_wayH_val_q; +ex4_ldq_full_flush <= not ex4_ldq_full_flush_b_q; +ex4_snd_ld_l2 <= not ex4_snd_ld_l2_q; +dcarr_up_way_addr <= dcarr_up_way_addr_q; +pe_recov_begin <= not dcpar_err_rec_inprog; +lsu_xu_ex5_cr_rslt <= ex5_cr_watch_q; +rel_way_val_a <= rel_wayA_val(0); +rel_way_lock_a <= rel_wayA_val(1); +rel_way_val_b <= rel_wayB_val(0); +rel_way_lock_b <= rel_wayB_val(1); +rel_way_val_c <= rel_wayC_val(0); +rel_way_lock_c <= rel_wayC_val(1); +rel_way_val_d <= rel_wayD_val(0); +rel_way_lock_d <= rel_wayD_val(1); +rel_way_val_e <= rel_wayE_val(0); +rel_way_lock_e <= rel_wayE_val(1); +rel_way_val_f <= rel_wayF_val(0); +rel_way_lock_f <= rel_wayF_val(1); +rel_way_val_g <= rel_wayG_val(0); +rel_way_lock_g <= rel_wayG_val(1); +rel_way_val_h <= rel_wayH_val(0); +rel_way_lock_h <= rel_wayH_val(1); +lsu_xu_perf_events <= lost_watch_inter_thrd_q & lost_watch_evict_val_q & lost_watch_binv & perf_lsu_evnts_q; +ex3_dir_perr_det <= ex3_dir_perr_val; +ex4_dir_multihit_det <= ex4_dir_multihit_val; +ex4_n_lsu_ddmh_flush <= not ex4_n_lsu_ddmh_flush_b_q; +ex2_lockwatchSet_rel_coll <= rel1_val and (ex2_lock_set or ex2_ldawx_instr) and (rel_congr_cl_q = ex2_congr_cl_q); +ex3_wclr_all_flush <= ex3_wclr_all_upd_q and fxu_pipe_val; +dc_val_dbg_data <= (others=>'0'); +lsu_xu_spr_xucr0_cslc_xuop <= xucr0_cslc_xuop_q; +lsu_xu_spr_xucr0_cslc_binv <= xucr0_cslc_binv_q; +congr_cl0_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl0_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl0_wA_offset to congr_cl0_wA_offset + congr_cl0_wA_d'length-1), + scout => sov(congr_cl0_wA_offset to congr_cl0_wA_offset + congr_cl0_wA_d'length-1), + din => congr_cl0_wA_d, + dout => congr_cl0_wA_q); +congr_cl0_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl0_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl0_wB_offset to congr_cl0_wB_offset + congr_cl0_wB_d'length-1), + scout => sov(congr_cl0_wB_offset to congr_cl0_wB_offset + congr_cl0_wB_d'length-1), + din => congr_cl0_wB_d, + dout => congr_cl0_wB_q); +congr_cl0_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl0_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl0_wC_offset to congr_cl0_wC_offset + congr_cl0_wC_d'length-1), + scout => sov(congr_cl0_wC_offset to congr_cl0_wC_offset + congr_cl0_wC_d'length-1), + din => congr_cl0_wC_d, + dout => congr_cl0_wC_q); +congr_cl0_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl0_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl0_wD_offset to congr_cl0_wD_offset + congr_cl0_wD_d'length-1), + scout => sov(congr_cl0_wD_offset to congr_cl0_wD_offset + congr_cl0_wD_d'length-1), + din => congr_cl0_wD_d, + dout => congr_cl0_wD_q); +congr_cl0_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl0_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl0_wE_offset to congr_cl0_wE_offset + congr_cl0_wE_d'length-1), + scout => sov(congr_cl0_wE_offset to congr_cl0_wE_offset + congr_cl0_wE_d'length-1), + din => congr_cl0_wE_d, + dout => congr_cl0_wE_q); +congr_cl0_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl0_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl0_wF_offset to congr_cl0_wF_offset + congr_cl0_wF_d'length-1), + scout => sov(congr_cl0_wF_offset to congr_cl0_wF_offset + congr_cl0_wF_d'length-1), + din => congr_cl0_wF_d, + dout => congr_cl0_wF_q); +congr_cl0_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl0_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl0_wG_offset to congr_cl0_wG_offset + congr_cl0_wG_d'length-1), + scout => sov(congr_cl0_wG_offset to congr_cl0_wG_offset + congr_cl0_wG_d'length-1), + din => congr_cl0_wG_d, + dout => congr_cl0_wG_q); +congr_cl0_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl0_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl0_wH_offset to congr_cl0_wH_offset + congr_cl0_wH_d'length-1), + scout => sov(congr_cl0_wH_offset to congr_cl0_wH_offset + congr_cl0_wH_d'length-1), + din => congr_cl0_wH_d, + dout => congr_cl0_wH_q); +congr_cl1_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl1_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl1_wA_offset to congr_cl1_wA_offset + congr_cl1_wA_d'length-1), + scout => sov(congr_cl1_wA_offset to congr_cl1_wA_offset + congr_cl1_wA_d'length-1), + din => congr_cl1_wA_d, + dout => congr_cl1_wA_q); +congr_cl1_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl1_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl1_wB_offset to congr_cl1_wB_offset + congr_cl1_wB_d'length-1), + scout => sov(congr_cl1_wB_offset to congr_cl1_wB_offset + congr_cl1_wB_d'length-1), + din => congr_cl1_wB_d, + dout => congr_cl1_wB_q); +congr_cl1_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl1_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl1_wC_offset to congr_cl1_wC_offset + congr_cl1_wC_d'length-1), + scout => sov(congr_cl1_wC_offset to congr_cl1_wC_offset + congr_cl1_wC_d'length-1), + din => congr_cl1_wC_d, + dout => congr_cl1_wC_q); +congr_cl1_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl1_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl1_wD_offset to congr_cl1_wD_offset + congr_cl1_wD_d'length-1), + scout => sov(congr_cl1_wD_offset to congr_cl1_wD_offset + congr_cl1_wD_d'length-1), + din => congr_cl1_wD_d, + dout => congr_cl1_wD_q); +congr_cl1_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl1_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl1_wE_offset to congr_cl1_wE_offset + congr_cl1_wE_d'length-1), + scout => sov(congr_cl1_wE_offset to congr_cl1_wE_offset + congr_cl1_wE_d'length-1), + din => congr_cl1_wE_d, + dout => congr_cl1_wE_q); +congr_cl1_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl1_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl1_wF_offset to congr_cl1_wF_offset + congr_cl1_wF_d'length-1), + scout => sov(congr_cl1_wF_offset to congr_cl1_wF_offset + congr_cl1_wF_d'length-1), + din => congr_cl1_wF_d, + dout => congr_cl1_wF_q); +congr_cl1_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl1_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl1_wG_offset to congr_cl1_wG_offset + congr_cl1_wG_d'length-1), + scout => sov(congr_cl1_wG_offset to congr_cl1_wG_offset + congr_cl1_wG_d'length-1), + din => congr_cl1_wG_d, + dout => congr_cl1_wG_q); +congr_cl1_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl1_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl1_wH_offset to congr_cl1_wH_offset + congr_cl1_wH_d'length-1), + scout => sov(congr_cl1_wH_offset to congr_cl1_wH_offset + congr_cl1_wH_d'length-1), + din => congr_cl1_wH_d, + dout => congr_cl1_wH_q); +congr_cl2_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl2_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl2_wA_offset to congr_cl2_wA_offset + congr_cl2_wA_d'length-1), + scout => sov(congr_cl2_wA_offset to congr_cl2_wA_offset + congr_cl2_wA_d'length-1), + din => congr_cl2_wA_d, + dout => congr_cl2_wA_q); +congr_cl2_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl2_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl2_wB_offset to congr_cl2_wB_offset + congr_cl2_wB_d'length-1), + scout => sov(congr_cl2_wB_offset to congr_cl2_wB_offset + congr_cl2_wB_d'length-1), + din => congr_cl2_wB_d, + dout => congr_cl2_wB_q); +congr_cl2_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl2_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl2_wC_offset to congr_cl2_wC_offset + congr_cl2_wC_d'length-1), + scout => sov(congr_cl2_wC_offset to congr_cl2_wC_offset + congr_cl2_wC_d'length-1), + din => congr_cl2_wC_d, + dout => congr_cl2_wC_q); +congr_cl2_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl2_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl2_wD_offset to congr_cl2_wD_offset + congr_cl2_wD_d'length-1), + scout => sov(congr_cl2_wD_offset to congr_cl2_wD_offset + congr_cl2_wD_d'length-1), + din => congr_cl2_wD_d, + dout => congr_cl2_wD_q); +congr_cl2_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl2_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl2_wE_offset to congr_cl2_wE_offset + congr_cl2_wE_d'length-1), + scout => sov(congr_cl2_wE_offset to congr_cl2_wE_offset + congr_cl2_wE_d'length-1), + din => congr_cl2_wE_d, + dout => congr_cl2_wE_q); +congr_cl2_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl2_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl2_wF_offset to congr_cl2_wF_offset + congr_cl2_wF_d'length-1), + scout => sov(congr_cl2_wF_offset to congr_cl2_wF_offset + congr_cl2_wF_d'length-1), + din => congr_cl2_wF_d, + dout => congr_cl2_wF_q); +congr_cl2_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl2_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl2_wG_offset to congr_cl2_wG_offset + congr_cl2_wG_d'length-1), + scout => sov(congr_cl2_wG_offset to congr_cl2_wG_offset + congr_cl2_wG_d'length-1), + din => congr_cl2_wG_d, + dout => congr_cl2_wG_q); +congr_cl2_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl2_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl2_wH_offset to congr_cl2_wH_offset + congr_cl2_wH_d'length-1), + scout => sov(congr_cl2_wH_offset to congr_cl2_wH_offset + congr_cl2_wH_d'length-1), + din => congr_cl2_wH_d, + dout => congr_cl2_wH_q); +congr_cl3_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl3_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl3_wA_offset to congr_cl3_wA_offset + congr_cl3_wA_d'length-1), + scout => sov(congr_cl3_wA_offset to congr_cl3_wA_offset + congr_cl3_wA_d'length-1), + din => congr_cl3_wA_d, + dout => congr_cl3_wA_q); +congr_cl3_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl3_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl3_wB_offset to congr_cl3_wB_offset + congr_cl3_wB_d'length-1), + scout => sov(congr_cl3_wB_offset to congr_cl3_wB_offset + congr_cl3_wB_d'length-1), + din => congr_cl3_wB_d, + dout => congr_cl3_wB_q); +congr_cl3_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl3_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl3_wC_offset to congr_cl3_wC_offset + congr_cl3_wC_d'length-1), + scout => sov(congr_cl3_wC_offset to congr_cl3_wC_offset + congr_cl3_wC_d'length-1), + din => congr_cl3_wC_d, + dout => congr_cl3_wC_q); +congr_cl3_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl3_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl3_wD_offset to congr_cl3_wD_offset + congr_cl3_wD_d'length-1), + scout => sov(congr_cl3_wD_offset to congr_cl3_wD_offset + congr_cl3_wD_d'length-1), + din => congr_cl3_wD_d, + dout => congr_cl3_wD_q); +congr_cl3_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl3_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl3_wE_offset to congr_cl3_wE_offset + congr_cl3_wE_d'length-1), + scout => sov(congr_cl3_wE_offset to congr_cl3_wE_offset + congr_cl3_wE_d'length-1), + din => congr_cl3_wE_d, + dout => congr_cl3_wE_q); +congr_cl3_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl3_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl3_wF_offset to congr_cl3_wF_offset + congr_cl3_wF_d'length-1), + scout => sov(congr_cl3_wF_offset to congr_cl3_wF_offset + congr_cl3_wF_d'length-1), + din => congr_cl3_wF_d, + dout => congr_cl3_wF_q); +congr_cl3_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl3_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl3_wG_offset to congr_cl3_wG_offset + congr_cl3_wG_d'length-1), + scout => sov(congr_cl3_wG_offset to congr_cl3_wG_offset + congr_cl3_wG_d'length-1), + din => congr_cl3_wG_d, + dout => congr_cl3_wG_q); +congr_cl3_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl3_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl3_wH_offset to congr_cl3_wH_offset + congr_cl3_wH_d'length-1), + scout => sov(congr_cl3_wH_offset to congr_cl3_wH_offset + congr_cl3_wH_d'length-1), + din => congr_cl3_wH_d, + dout => congr_cl3_wH_q); +congr_cl4_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl4_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl4_wA_offset to congr_cl4_wA_offset + congr_cl4_wA_d'length-1), + scout => sov(congr_cl4_wA_offset to congr_cl4_wA_offset + congr_cl4_wA_d'length-1), + din => congr_cl4_wA_d, + dout => congr_cl4_wA_q); +congr_cl4_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl4_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl4_wB_offset to congr_cl4_wB_offset + congr_cl4_wB_d'length-1), + scout => sov(congr_cl4_wB_offset to congr_cl4_wB_offset + congr_cl4_wB_d'length-1), + din => congr_cl4_wB_d, + dout => congr_cl4_wB_q); +congr_cl4_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl4_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl4_wC_offset to congr_cl4_wC_offset + congr_cl4_wC_d'length-1), + scout => sov(congr_cl4_wC_offset to congr_cl4_wC_offset + congr_cl4_wC_d'length-1), + din => congr_cl4_wC_d, + dout => congr_cl4_wC_q); +congr_cl4_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl4_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl4_wD_offset to congr_cl4_wD_offset + congr_cl4_wD_d'length-1), + scout => sov(congr_cl4_wD_offset to congr_cl4_wD_offset + congr_cl4_wD_d'length-1), + din => congr_cl4_wD_d, + dout => congr_cl4_wD_q); +congr_cl4_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl4_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl4_wE_offset to congr_cl4_wE_offset + congr_cl4_wE_d'length-1), + scout => sov(congr_cl4_wE_offset to congr_cl4_wE_offset + congr_cl4_wE_d'length-1), + din => congr_cl4_wE_d, + dout => congr_cl4_wE_q); +congr_cl4_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl4_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl4_wF_offset to congr_cl4_wF_offset + congr_cl4_wF_d'length-1), + scout => sov(congr_cl4_wF_offset to congr_cl4_wF_offset + congr_cl4_wF_d'length-1), + din => congr_cl4_wF_d, + dout => congr_cl4_wF_q); +congr_cl4_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl4_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl4_wG_offset to congr_cl4_wG_offset + congr_cl4_wG_d'length-1), + scout => sov(congr_cl4_wG_offset to congr_cl4_wG_offset + congr_cl4_wG_d'length-1), + din => congr_cl4_wG_d, + dout => congr_cl4_wG_q); +congr_cl4_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl4_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl4_wH_offset to congr_cl4_wH_offset + congr_cl4_wH_d'length-1), + scout => sov(congr_cl4_wH_offset to congr_cl4_wH_offset + congr_cl4_wH_d'length-1), + din => congr_cl4_wH_d, + dout => congr_cl4_wH_q); +congr_cl5_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl5_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl5_wA_offset to congr_cl5_wA_offset + congr_cl5_wA_d'length-1), + scout => sov(congr_cl5_wA_offset to congr_cl5_wA_offset + congr_cl5_wA_d'length-1), + din => congr_cl5_wA_d, + dout => congr_cl5_wA_q); +congr_cl5_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl5_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl5_wB_offset to congr_cl5_wB_offset + congr_cl5_wB_d'length-1), + scout => sov(congr_cl5_wB_offset to congr_cl5_wB_offset + congr_cl5_wB_d'length-1), + din => congr_cl5_wB_d, + dout => congr_cl5_wB_q); +congr_cl5_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl5_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl5_wC_offset to congr_cl5_wC_offset + congr_cl5_wC_d'length-1), + scout => sov(congr_cl5_wC_offset to congr_cl5_wC_offset + congr_cl5_wC_d'length-1), + din => congr_cl5_wC_d, + dout => congr_cl5_wC_q); +congr_cl5_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl5_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl5_wD_offset to congr_cl5_wD_offset + congr_cl5_wD_d'length-1), + scout => sov(congr_cl5_wD_offset to congr_cl5_wD_offset + congr_cl5_wD_d'length-1), + din => congr_cl5_wD_d, + dout => congr_cl5_wD_q); +congr_cl5_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl5_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl5_wE_offset to congr_cl5_wE_offset + congr_cl5_wE_d'length-1), + scout => sov(congr_cl5_wE_offset to congr_cl5_wE_offset + congr_cl5_wE_d'length-1), + din => congr_cl5_wE_d, + dout => congr_cl5_wE_q); +congr_cl5_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl5_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl5_wF_offset to congr_cl5_wF_offset + congr_cl5_wF_d'length-1), + scout => sov(congr_cl5_wF_offset to congr_cl5_wF_offset + congr_cl5_wF_d'length-1), + din => congr_cl5_wF_d, + dout => congr_cl5_wF_q); +congr_cl5_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl5_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl5_wG_offset to congr_cl5_wG_offset + congr_cl5_wG_d'length-1), + scout => sov(congr_cl5_wG_offset to congr_cl5_wG_offset + congr_cl5_wG_d'length-1), + din => congr_cl5_wG_d, + dout => congr_cl5_wG_q); +congr_cl5_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl5_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl5_wH_offset to congr_cl5_wH_offset + congr_cl5_wH_d'length-1), + scout => sov(congr_cl5_wH_offset to congr_cl5_wH_offset + congr_cl5_wH_d'length-1), + din => congr_cl5_wH_d, + dout => congr_cl5_wH_q); +congr_cl6_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl6_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl6_wA_offset to congr_cl6_wA_offset + congr_cl6_wA_d'length-1), + scout => sov(congr_cl6_wA_offset to congr_cl6_wA_offset + congr_cl6_wA_d'length-1), + din => congr_cl6_wA_d, + dout => congr_cl6_wA_q); +congr_cl6_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl6_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl6_wB_offset to congr_cl6_wB_offset + congr_cl6_wB_d'length-1), + scout => sov(congr_cl6_wB_offset to congr_cl6_wB_offset + congr_cl6_wB_d'length-1), + din => congr_cl6_wB_d, + dout => congr_cl6_wB_q); +congr_cl6_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl6_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl6_wC_offset to congr_cl6_wC_offset + congr_cl6_wC_d'length-1), + scout => sov(congr_cl6_wC_offset to congr_cl6_wC_offset + congr_cl6_wC_d'length-1), + din => congr_cl6_wC_d, + dout => congr_cl6_wC_q); +congr_cl6_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl6_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl6_wD_offset to congr_cl6_wD_offset + congr_cl6_wD_d'length-1), + scout => sov(congr_cl6_wD_offset to congr_cl6_wD_offset + congr_cl6_wD_d'length-1), + din => congr_cl6_wD_d, + dout => congr_cl6_wD_q); +congr_cl6_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl6_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl6_wE_offset to congr_cl6_wE_offset + congr_cl6_wE_d'length-1), + scout => sov(congr_cl6_wE_offset to congr_cl6_wE_offset + congr_cl6_wE_d'length-1), + din => congr_cl6_wE_d, + dout => congr_cl6_wE_q); +congr_cl6_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl6_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl6_wF_offset to congr_cl6_wF_offset + congr_cl6_wF_d'length-1), + scout => sov(congr_cl6_wF_offset to congr_cl6_wF_offset + congr_cl6_wF_d'length-1), + din => congr_cl6_wF_d, + dout => congr_cl6_wF_q); +congr_cl6_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl6_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl6_wG_offset to congr_cl6_wG_offset + congr_cl6_wG_d'length-1), + scout => sov(congr_cl6_wG_offset to congr_cl6_wG_offset + congr_cl6_wG_d'length-1), + din => congr_cl6_wG_d, + dout => congr_cl6_wG_q); +congr_cl6_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl6_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl6_wH_offset to congr_cl6_wH_offset + congr_cl6_wH_d'length-1), + scout => sov(congr_cl6_wH_offset to congr_cl6_wH_offset + congr_cl6_wH_d'length-1), + din => congr_cl6_wH_d, + dout => congr_cl6_wH_q); +congr_cl7_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl7_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl7_wA_offset to congr_cl7_wA_offset + congr_cl7_wA_d'length-1), + scout => sov(congr_cl7_wA_offset to congr_cl7_wA_offset + congr_cl7_wA_d'length-1), + din => congr_cl7_wA_d, + dout => congr_cl7_wA_q); +congr_cl7_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl7_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl7_wB_offset to congr_cl7_wB_offset + congr_cl7_wB_d'length-1), + scout => sov(congr_cl7_wB_offset to congr_cl7_wB_offset + congr_cl7_wB_d'length-1), + din => congr_cl7_wB_d, + dout => congr_cl7_wB_q); +congr_cl7_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl7_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl7_wC_offset to congr_cl7_wC_offset + congr_cl7_wC_d'length-1), + scout => sov(congr_cl7_wC_offset to congr_cl7_wC_offset + congr_cl7_wC_d'length-1), + din => congr_cl7_wC_d, + dout => congr_cl7_wC_q); +congr_cl7_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl7_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl7_wD_offset to congr_cl7_wD_offset + congr_cl7_wD_d'length-1), + scout => sov(congr_cl7_wD_offset to congr_cl7_wD_offset + congr_cl7_wD_d'length-1), + din => congr_cl7_wD_d, + dout => congr_cl7_wD_q); +congr_cl7_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl7_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl7_wE_offset to congr_cl7_wE_offset + congr_cl7_wE_d'length-1), + scout => sov(congr_cl7_wE_offset to congr_cl7_wE_offset + congr_cl7_wE_d'length-1), + din => congr_cl7_wE_d, + dout => congr_cl7_wE_q); +congr_cl7_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl7_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl7_wF_offset to congr_cl7_wF_offset + congr_cl7_wF_d'length-1), + scout => sov(congr_cl7_wF_offset to congr_cl7_wF_offset + congr_cl7_wF_d'length-1), + din => congr_cl7_wF_d, + dout => congr_cl7_wF_q); +congr_cl7_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl7_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl7_wG_offset to congr_cl7_wG_offset + congr_cl7_wG_d'length-1), + scout => sov(congr_cl7_wG_offset to congr_cl7_wG_offset + congr_cl7_wG_d'length-1), + din => congr_cl7_wG_d, + dout => congr_cl7_wG_q); +congr_cl7_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl7_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl7_wH_offset to congr_cl7_wH_offset + congr_cl7_wH_d'length-1), + scout => sov(congr_cl7_wH_offset to congr_cl7_wH_offset + congr_cl7_wH_d'length-1), + din => congr_cl7_wH_d, + dout => congr_cl7_wH_q); +congr_cl8_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl8_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl8_wA_offset to congr_cl8_wA_offset + congr_cl8_wA_d'length-1), + scout => sov(congr_cl8_wA_offset to congr_cl8_wA_offset + congr_cl8_wA_d'length-1), + din => congr_cl8_wA_d, + dout => congr_cl8_wA_q); +congr_cl8_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl8_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl8_wB_offset to congr_cl8_wB_offset + congr_cl8_wB_d'length-1), + scout => sov(congr_cl8_wB_offset to congr_cl8_wB_offset + congr_cl8_wB_d'length-1), + din => congr_cl8_wB_d, + dout => congr_cl8_wB_q); +congr_cl8_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl8_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl8_wC_offset to congr_cl8_wC_offset + congr_cl8_wC_d'length-1), + scout => sov(congr_cl8_wC_offset to congr_cl8_wC_offset + congr_cl8_wC_d'length-1), + din => congr_cl8_wC_d, + dout => congr_cl8_wC_q); +congr_cl8_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl8_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl8_wD_offset to congr_cl8_wD_offset + congr_cl8_wD_d'length-1), + scout => sov(congr_cl8_wD_offset to congr_cl8_wD_offset + congr_cl8_wD_d'length-1), + din => congr_cl8_wD_d, + dout => congr_cl8_wD_q); +congr_cl8_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl8_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl8_wE_offset to congr_cl8_wE_offset + congr_cl8_wE_d'length-1), + scout => sov(congr_cl8_wE_offset to congr_cl8_wE_offset + congr_cl8_wE_d'length-1), + din => congr_cl8_wE_d, + dout => congr_cl8_wE_q); +congr_cl8_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl8_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl8_wF_offset to congr_cl8_wF_offset + congr_cl8_wF_d'length-1), + scout => sov(congr_cl8_wF_offset to congr_cl8_wF_offset + congr_cl8_wF_d'length-1), + din => congr_cl8_wF_d, + dout => congr_cl8_wF_q); +congr_cl8_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl8_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl8_wG_offset to congr_cl8_wG_offset + congr_cl8_wG_d'length-1), + scout => sov(congr_cl8_wG_offset to congr_cl8_wG_offset + congr_cl8_wG_d'length-1), + din => congr_cl8_wG_d, + dout => congr_cl8_wG_q); +congr_cl8_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl8_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl8_wH_offset to congr_cl8_wH_offset + congr_cl8_wH_d'length-1), + scout => sov(congr_cl8_wH_offset to congr_cl8_wH_offset + congr_cl8_wH_d'length-1), + din => congr_cl8_wH_d, + dout => congr_cl8_wH_q); +congr_cl9_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl9_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl9_wA_offset to congr_cl9_wA_offset + congr_cl9_wA_d'length-1), + scout => sov(congr_cl9_wA_offset to congr_cl9_wA_offset + congr_cl9_wA_d'length-1), + din => congr_cl9_wA_d, + dout => congr_cl9_wA_q); +congr_cl9_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl9_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl9_wB_offset to congr_cl9_wB_offset + congr_cl9_wB_d'length-1), + scout => sov(congr_cl9_wB_offset to congr_cl9_wB_offset + congr_cl9_wB_d'length-1), + din => congr_cl9_wB_d, + dout => congr_cl9_wB_q); +congr_cl9_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl9_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl9_wC_offset to congr_cl9_wC_offset + congr_cl9_wC_d'length-1), + scout => sov(congr_cl9_wC_offset to congr_cl9_wC_offset + congr_cl9_wC_d'length-1), + din => congr_cl9_wC_d, + dout => congr_cl9_wC_q); +congr_cl9_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl9_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl9_wD_offset to congr_cl9_wD_offset + congr_cl9_wD_d'length-1), + scout => sov(congr_cl9_wD_offset to congr_cl9_wD_offset + congr_cl9_wD_d'length-1), + din => congr_cl9_wD_d, + dout => congr_cl9_wD_q); +congr_cl9_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl9_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl9_wE_offset to congr_cl9_wE_offset + congr_cl9_wE_d'length-1), + scout => sov(congr_cl9_wE_offset to congr_cl9_wE_offset + congr_cl9_wE_d'length-1), + din => congr_cl9_wE_d, + dout => congr_cl9_wE_q); +congr_cl9_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl9_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl9_wF_offset to congr_cl9_wF_offset + congr_cl9_wF_d'length-1), + scout => sov(congr_cl9_wF_offset to congr_cl9_wF_offset + congr_cl9_wF_d'length-1), + din => congr_cl9_wF_d, + dout => congr_cl9_wF_q); +congr_cl9_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl9_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl9_wG_offset to congr_cl9_wG_offset + congr_cl9_wG_d'length-1), + scout => sov(congr_cl9_wG_offset to congr_cl9_wG_offset + congr_cl9_wG_d'length-1), + din => congr_cl9_wG_d, + dout => congr_cl9_wG_q); +congr_cl9_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl9_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl9_wH_offset to congr_cl9_wH_offset + congr_cl9_wH_d'length-1), + scout => sov(congr_cl9_wH_offset to congr_cl9_wH_offset + congr_cl9_wH_d'length-1), + din => congr_cl9_wH_d, + dout => congr_cl9_wH_q); +congr_cl10_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl10_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl10_wA_offset to congr_cl10_wA_offset + congr_cl10_wA_d'length-1), + scout => sov(congr_cl10_wA_offset to congr_cl10_wA_offset + congr_cl10_wA_d'length-1), + din => congr_cl10_wA_d, + dout => congr_cl10_wA_q); +congr_cl10_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl10_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl10_wB_offset to congr_cl10_wB_offset + congr_cl10_wB_d'length-1), + scout => sov(congr_cl10_wB_offset to congr_cl10_wB_offset + congr_cl10_wB_d'length-1), + din => congr_cl10_wB_d, + dout => congr_cl10_wB_q); +congr_cl10_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl10_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl10_wC_offset to congr_cl10_wC_offset + congr_cl10_wC_d'length-1), + scout => sov(congr_cl10_wC_offset to congr_cl10_wC_offset + congr_cl10_wC_d'length-1), + din => congr_cl10_wC_d, + dout => congr_cl10_wC_q); +congr_cl10_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl10_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl10_wD_offset to congr_cl10_wD_offset + congr_cl10_wD_d'length-1), + scout => sov(congr_cl10_wD_offset to congr_cl10_wD_offset + congr_cl10_wD_d'length-1), + din => congr_cl10_wD_d, + dout => congr_cl10_wD_q); +congr_cl10_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl10_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl10_wE_offset to congr_cl10_wE_offset + congr_cl10_wE_d'length-1), + scout => sov(congr_cl10_wE_offset to congr_cl10_wE_offset + congr_cl10_wE_d'length-1), + din => congr_cl10_wE_d, + dout => congr_cl10_wE_q); +congr_cl10_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl10_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl10_wF_offset to congr_cl10_wF_offset + congr_cl10_wF_d'length-1), + scout => sov(congr_cl10_wF_offset to congr_cl10_wF_offset + congr_cl10_wF_d'length-1), + din => congr_cl10_wF_d, + dout => congr_cl10_wF_q); +congr_cl10_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl10_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl10_wG_offset to congr_cl10_wG_offset + congr_cl10_wG_d'length-1), + scout => sov(congr_cl10_wG_offset to congr_cl10_wG_offset + congr_cl10_wG_d'length-1), + din => congr_cl10_wG_d, + dout => congr_cl10_wG_q); +congr_cl10_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl10_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl10_wH_offset to congr_cl10_wH_offset + congr_cl10_wH_d'length-1), + scout => sov(congr_cl10_wH_offset to congr_cl10_wH_offset + congr_cl10_wH_d'length-1), + din => congr_cl10_wH_d, + dout => congr_cl10_wH_q); +congr_cl11_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl11_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl11_wA_offset to congr_cl11_wA_offset + congr_cl11_wA_d'length-1), + scout => sov(congr_cl11_wA_offset to congr_cl11_wA_offset + congr_cl11_wA_d'length-1), + din => congr_cl11_wA_d, + dout => congr_cl11_wA_q); +congr_cl11_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl11_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl11_wB_offset to congr_cl11_wB_offset + congr_cl11_wB_d'length-1), + scout => sov(congr_cl11_wB_offset to congr_cl11_wB_offset + congr_cl11_wB_d'length-1), + din => congr_cl11_wB_d, + dout => congr_cl11_wB_q); +congr_cl11_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl11_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl11_wC_offset to congr_cl11_wC_offset + congr_cl11_wC_d'length-1), + scout => sov(congr_cl11_wC_offset to congr_cl11_wC_offset + congr_cl11_wC_d'length-1), + din => congr_cl11_wC_d, + dout => congr_cl11_wC_q); +congr_cl11_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl11_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl11_wD_offset to congr_cl11_wD_offset + congr_cl11_wD_d'length-1), + scout => sov(congr_cl11_wD_offset to congr_cl11_wD_offset + congr_cl11_wD_d'length-1), + din => congr_cl11_wD_d, + dout => congr_cl11_wD_q); +congr_cl11_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl11_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl11_wE_offset to congr_cl11_wE_offset + congr_cl11_wE_d'length-1), + scout => sov(congr_cl11_wE_offset to congr_cl11_wE_offset + congr_cl11_wE_d'length-1), + din => congr_cl11_wE_d, + dout => congr_cl11_wE_q); +congr_cl11_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl11_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl11_wF_offset to congr_cl11_wF_offset + congr_cl11_wF_d'length-1), + scout => sov(congr_cl11_wF_offset to congr_cl11_wF_offset + congr_cl11_wF_d'length-1), + din => congr_cl11_wF_d, + dout => congr_cl11_wF_q); +congr_cl11_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl11_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl11_wG_offset to congr_cl11_wG_offset + congr_cl11_wG_d'length-1), + scout => sov(congr_cl11_wG_offset to congr_cl11_wG_offset + congr_cl11_wG_d'length-1), + din => congr_cl11_wG_d, + dout => congr_cl11_wG_q); +congr_cl11_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl11_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl11_wH_offset to congr_cl11_wH_offset + congr_cl11_wH_d'length-1), + scout => sov(congr_cl11_wH_offset to congr_cl11_wH_offset + congr_cl11_wH_d'length-1), + din => congr_cl11_wH_d, + dout => congr_cl11_wH_q); +congr_cl12_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl12_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl12_wA_offset to congr_cl12_wA_offset + congr_cl12_wA_d'length-1), + scout => sov(congr_cl12_wA_offset to congr_cl12_wA_offset + congr_cl12_wA_d'length-1), + din => congr_cl12_wA_d, + dout => congr_cl12_wA_q); +congr_cl12_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl12_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl12_wB_offset to congr_cl12_wB_offset + congr_cl12_wB_d'length-1), + scout => sov(congr_cl12_wB_offset to congr_cl12_wB_offset + congr_cl12_wB_d'length-1), + din => congr_cl12_wB_d, + dout => congr_cl12_wB_q); +congr_cl12_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl12_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl12_wC_offset to congr_cl12_wC_offset + congr_cl12_wC_d'length-1), + scout => sov(congr_cl12_wC_offset to congr_cl12_wC_offset + congr_cl12_wC_d'length-1), + din => congr_cl12_wC_d, + dout => congr_cl12_wC_q); +congr_cl12_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl12_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl12_wD_offset to congr_cl12_wD_offset + congr_cl12_wD_d'length-1), + scout => sov(congr_cl12_wD_offset to congr_cl12_wD_offset + congr_cl12_wD_d'length-1), + din => congr_cl12_wD_d, + dout => congr_cl12_wD_q); +congr_cl12_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl12_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl12_wE_offset to congr_cl12_wE_offset + congr_cl12_wE_d'length-1), + scout => sov(congr_cl12_wE_offset to congr_cl12_wE_offset + congr_cl12_wE_d'length-1), + din => congr_cl12_wE_d, + dout => congr_cl12_wE_q); +congr_cl12_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl12_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl12_wF_offset to congr_cl12_wF_offset + congr_cl12_wF_d'length-1), + scout => sov(congr_cl12_wF_offset to congr_cl12_wF_offset + congr_cl12_wF_d'length-1), + din => congr_cl12_wF_d, + dout => congr_cl12_wF_q); +congr_cl12_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl12_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl12_wG_offset to congr_cl12_wG_offset + congr_cl12_wG_d'length-1), + scout => sov(congr_cl12_wG_offset to congr_cl12_wG_offset + congr_cl12_wG_d'length-1), + din => congr_cl12_wG_d, + dout => congr_cl12_wG_q); +congr_cl12_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl12_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl12_wH_offset to congr_cl12_wH_offset + congr_cl12_wH_d'length-1), + scout => sov(congr_cl12_wH_offset to congr_cl12_wH_offset + congr_cl12_wH_d'length-1), + din => congr_cl12_wH_d, + dout => congr_cl12_wH_q); +congr_cl13_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl13_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl13_wA_offset to congr_cl13_wA_offset + congr_cl13_wA_d'length-1), + scout => sov(congr_cl13_wA_offset to congr_cl13_wA_offset + congr_cl13_wA_d'length-1), + din => congr_cl13_wA_d, + dout => congr_cl13_wA_q); +congr_cl13_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl13_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl13_wB_offset to congr_cl13_wB_offset + congr_cl13_wB_d'length-1), + scout => sov(congr_cl13_wB_offset to congr_cl13_wB_offset + congr_cl13_wB_d'length-1), + din => congr_cl13_wB_d, + dout => congr_cl13_wB_q); +congr_cl13_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl13_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl13_wC_offset to congr_cl13_wC_offset + congr_cl13_wC_d'length-1), + scout => sov(congr_cl13_wC_offset to congr_cl13_wC_offset + congr_cl13_wC_d'length-1), + din => congr_cl13_wC_d, + dout => congr_cl13_wC_q); +congr_cl13_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl13_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl13_wD_offset to congr_cl13_wD_offset + congr_cl13_wD_d'length-1), + scout => sov(congr_cl13_wD_offset to congr_cl13_wD_offset + congr_cl13_wD_d'length-1), + din => congr_cl13_wD_d, + dout => congr_cl13_wD_q); +congr_cl13_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl13_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl13_wE_offset to congr_cl13_wE_offset + congr_cl13_wE_d'length-1), + scout => sov(congr_cl13_wE_offset to congr_cl13_wE_offset + congr_cl13_wE_d'length-1), + din => congr_cl13_wE_d, + dout => congr_cl13_wE_q); +congr_cl13_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl13_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl13_wF_offset to congr_cl13_wF_offset + congr_cl13_wF_d'length-1), + scout => sov(congr_cl13_wF_offset to congr_cl13_wF_offset + congr_cl13_wF_d'length-1), + din => congr_cl13_wF_d, + dout => congr_cl13_wF_q); +congr_cl13_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl13_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl13_wG_offset to congr_cl13_wG_offset + congr_cl13_wG_d'length-1), + scout => sov(congr_cl13_wG_offset to congr_cl13_wG_offset + congr_cl13_wG_d'length-1), + din => congr_cl13_wG_d, + dout => congr_cl13_wG_q); +congr_cl13_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl13_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl13_wH_offset to congr_cl13_wH_offset + congr_cl13_wH_d'length-1), + scout => sov(congr_cl13_wH_offset to congr_cl13_wH_offset + congr_cl13_wH_d'length-1), + din => congr_cl13_wH_d, + dout => congr_cl13_wH_q); +congr_cl14_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl14_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl14_wA_offset to congr_cl14_wA_offset + congr_cl14_wA_d'length-1), + scout => sov(congr_cl14_wA_offset to congr_cl14_wA_offset + congr_cl14_wA_d'length-1), + din => congr_cl14_wA_d, + dout => congr_cl14_wA_q); +congr_cl14_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl14_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl14_wB_offset to congr_cl14_wB_offset + congr_cl14_wB_d'length-1), + scout => sov(congr_cl14_wB_offset to congr_cl14_wB_offset + congr_cl14_wB_d'length-1), + din => congr_cl14_wB_d, + dout => congr_cl14_wB_q); +congr_cl14_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl14_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl14_wC_offset to congr_cl14_wC_offset + congr_cl14_wC_d'length-1), + scout => sov(congr_cl14_wC_offset to congr_cl14_wC_offset + congr_cl14_wC_d'length-1), + din => congr_cl14_wC_d, + dout => congr_cl14_wC_q); +congr_cl14_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl14_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl14_wD_offset to congr_cl14_wD_offset + congr_cl14_wD_d'length-1), + scout => sov(congr_cl14_wD_offset to congr_cl14_wD_offset + congr_cl14_wD_d'length-1), + din => congr_cl14_wD_d, + dout => congr_cl14_wD_q); +congr_cl14_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl14_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl14_wE_offset to congr_cl14_wE_offset + congr_cl14_wE_d'length-1), + scout => sov(congr_cl14_wE_offset to congr_cl14_wE_offset + congr_cl14_wE_d'length-1), + din => congr_cl14_wE_d, + dout => congr_cl14_wE_q); +congr_cl14_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl14_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl14_wF_offset to congr_cl14_wF_offset + congr_cl14_wF_d'length-1), + scout => sov(congr_cl14_wF_offset to congr_cl14_wF_offset + congr_cl14_wF_d'length-1), + din => congr_cl14_wF_d, + dout => congr_cl14_wF_q); +congr_cl14_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl14_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl14_wG_offset to congr_cl14_wG_offset + congr_cl14_wG_d'length-1), + scout => sov(congr_cl14_wG_offset to congr_cl14_wG_offset + congr_cl14_wG_d'length-1), + din => congr_cl14_wG_d, + dout => congr_cl14_wG_q); +congr_cl14_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl14_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl14_wH_offset to congr_cl14_wH_offset + congr_cl14_wH_d'length-1), + scout => sov(congr_cl14_wH_offset to congr_cl14_wH_offset + congr_cl14_wH_d'length-1), + din => congr_cl14_wH_d, + dout => congr_cl14_wH_q); +congr_cl15_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl15_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl15_wA_offset to congr_cl15_wA_offset + congr_cl15_wA_d'length-1), + scout => sov(congr_cl15_wA_offset to congr_cl15_wA_offset + congr_cl15_wA_d'length-1), + din => congr_cl15_wA_d, + dout => congr_cl15_wA_q); +congr_cl15_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl15_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl15_wB_offset to congr_cl15_wB_offset + congr_cl15_wB_d'length-1), + scout => sov(congr_cl15_wB_offset to congr_cl15_wB_offset + congr_cl15_wB_d'length-1), + din => congr_cl15_wB_d, + dout => congr_cl15_wB_q); +congr_cl15_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl15_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl15_wC_offset to congr_cl15_wC_offset + congr_cl15_wC_d'length-1), + scout => sov(congr_cl15_wC_offset to congr_cl15_wC_offset + congr_cl15_wC_d'length-1), + din => congr_cl15_wC_d, + dout => congr_cl15_wC_q); +congr_cl15_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl15_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl15_wD_offset to congr_cl15_wD_offset + congr_cl15_wD_d'length-1), + scout => sov(congr_cl15_wD_offset to congr_cl15_wD_offset + congr_cl15_wD_d'length-1), + din => congr_cl15_wD_d, + dout => congr_cl15_wD_q); +congr_cl15_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl15_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl15_wE_offset to congr_cl15_wE_offset + congr_cl15_wE_d'length-1), + scout => sov(congr_cl15_wE_offset to congr_cl15_wE_offset + congr_cl15_wE_d'length-1), + din => congr_cl15_wE_d, + dout => congr_cl15_wE_q); +congr_cl15_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl15_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl15_wF_offset to congr_cl15_wF_offset + congr_cl15_wF_d'length-1), + scout => sov(congr_cl15_wF_offset to congr_cl15_wF_offset + congr_cl15_wF_d'length-1), + din => congr_cl15_wF_d, + dout => congr_cl15_wF_q); +congr_cl15_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl15_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl15_wG_offset to congr_cl15_wG_offset + congr_cl15_wG_d'length-1), + scout => sov(congr_cl15_wG_offset to congr_cl15_wG_offset + congr_cl15_wG_d'length-1), + din => congr_cl15_wG_d, + dout => congr_cl15_wG_q); +congr_cl15_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl15_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl15_wH_offset to congr_cl15_wH_offset + congr_cl15_wH_d'length-1), + scout => sov(congr_cl15_wH_offset to congr_cl15_wH_offset + congr_cl15_wH_d'length-1), + din => congr_cl15_wH_d, + dout => congr_cl15_wH_q); +congr_cl16_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl16_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl16_wA_offset to congr_cl16_wA_offset + congr_cl16_wA_d'length-1), + scout => sov(congr_cl16_wA_offset to congr_cl16_wA_offset + congr_cl16_wA_d'length-1), + din => congr_cl16_wA_d, + dout => congr_cl16_wA_q); +congr_cl16_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl16_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl16_wB_offset to congr_cl16_wB_offset + congr_cl16_wB_d'length-1), + scout => sov(congr_cl16_wB_offset to congr_cl16_wB_offset + congr_cl16_wB_d'length-1), + din => congr_cl16_wB_d, + dout => congr_cl16_wB_q); +congr_cl16_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl16_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl16_wC_offset to congr_cl16_wC_offset + congr_cl16_wC_d'length-1), + scout => sov(congr_cl16_wC_offset to congr_cl16_wC_offset + congr_cl16_wC_d'length-1), + din => congr_cl16_wC_d, + dout => congr_cl16_wC_q); +congr_cl16_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl16_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl16_wD_offset to congr_cl16_wD_offset + congr_cl16_wD_d'length-1), + scout => sov(congr_cl16_wD_offset to congr_cl16_wD_offset + congr_cl16_wD_d'length-1), + din => congr_cl16_wD_d, + dout => congr_cl16_wD_q); +congr_cl16_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl16_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl16_wE_offset to congr_cl16_wE_offset + congr_cl16_wE_d'length-1), + scout => sov(congr_cl16_wE_offset to congr_cl16_wE_offset + congr_cl16_wE_d'length-1), + din => congr_cl16_wE_d, + dout => congr_cl16_wE_q); +congr_cl16_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl16_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl16_wF_offset to congr_cl16_wF_offset + congr_cl16_wF_d'length-1), + scout => sov(congr_cl16_wF_offset to congr_cl16_wF_offset + congr_cl16_wF_d'length-1), + din => congr_cl16_wF_d, + dout => congr_cl16_wF_q); +congr_cl16_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl16_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl16_wG_offset to congr_cl16_wG_offset + congr_cl16_wG_d'length-1), + scout => sov(congr_cl16_wG_offset to congr_cl16_wG_offset + congr_cl16_wG_d'length-1), + din => congr_cl16_wG_d, + dout => congr_cl16_wG_q); +congr_cl16_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl16_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl16_wH_offset to congr_cl16_wH_offset + congr_cl16_wH_d'length-1), + scout => sov(congr_cl16_wH_offset to congr_cl16_wH_offset + congr_cl16_wH_d'length-1), + din => congr_cl16_wH_d, + dout => congr_cl16_wH_q); +congr_cl17_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl17_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl17_wA_offset to congr_cl17_wA_offset + congr_cl17_wA_d'length-1), + scout => sov(congr_cl17_wA_offset to congr_cl17_wA_offset + congr_cl17_wA_d'length-1), + din => congr_cl17_wA_d, + dout => congr_cl17_wA_q); +congr_cl17_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl17_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl17_wB_offset to congr_cl17_wB_offset + congr_cl17_wB_d'length-1), + scout => sov(congr_cl17_wB_offset to congr_cl17_wB_offset + congr_cl17_wB_d'length-1), + din => congr_cl17_wB_d, + dout => congr_cl17_wB_q); +congr_cl17_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl17_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl17_wC_offset to congr_cl17_wC_offset + congr_cl17_wC_d'length-1), + scout => sov(congr_cl17_wC_offset to congr_cl17_wC_offset + congr_cl17_wC_d'length-1), + din => congr_cl17_wC_d, + dout => congr_cl17_wC_q); +congr_cl17_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl17_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl17_wD_offset to congr_cl17_wD_offset + congr_cl17_wD_d'length-1), + scout => sov(congr_cl17_wD_offset to congr_cl17_wD_offset + congr_cl17_wD_d'length-1), + din => congr_cl17_wD_d, + dout => congr_cl17_wD_q); +congr_cl17_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl17_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl17_wE_offset to congr_cl17_wE_offset + congr_cl17_wE_d'length-1), + scout => sov(congr_cl17_wE_offset to congr_cl17_wE_offset + congr_cl17_wE_d'length-1), + din => congr_cl17_wE_d, + dout => congr_cl17_wE_q); +congr_cl17_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl17_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl17_wF_offset to congr_cl17_wF_offset + congr_cl17_wF_d'length-1), + scout => sov(congr_cl17_wF_offset to congr_cl17_wF_offset + congr_cl17_wF_d'length-1), + din => congr_cl17_wF_d, + dout => congr_cl17_wF_q); +congr_cl17_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl17_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl17_wG_offset to congr_cl17_wG_offset + congr_cl17_wG_d'length-1), + scout => sov(congr_cl17_wG_offset to congr_cl17_wG_offset + congr_cl17_wG_d'length-1), + din => congr_cl17_wG_d, + dout => congr_cl17_wG_q); +congr_cl17_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl17_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl17_wH_offset to congr_cl17_wH_offset + congr_cl17_wH_d'length-1), + scout => sov(congr_cl17_wH_offset to congr_cl17_wH_offset + congr_cl17_wH_d'length-1), + din => congr_cl17_wH_d, + dout => congr_cl17_wH_q); +congr_cl18_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl18_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl18_wA_offset to congr_cl18_wA_offset + congr_cl18_wA_d'length-1), + scout => sov(congr_cl18_wA_offset to congr_cl18_wA_offset + congr_cl18_wA_d'length-1), + din => congr_cl18_wA_d, + dout => congr_cl18_wA_q); +congr_cl18_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl18_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl18_wB_offset to congr_cl18_wB_offset + congr_cl18_wB_d'length-1), + scout => sov(congr_cl18_wB_offset to congr_cl18_wB_offset + congr_cl18_wB_d'length-1), + din => congr_cl18_wB_d, + dout => congr_cl18_wB_q); +congr_cl18_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl18_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl18_wC_offset to congr_cl18_wC_offset + congr_cl18_wC_d'length-1), + scout => sov(congr_cl18_wC_offset to congr_cl18_wC_offset + congr_cl18_wC_d'length-1), + din => congr_cl18_wC_d, + dout => congr_cl18_wC_q); +congr_cl18_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl18_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl18_wD_offset to congr_cl18_wD_offset + congr_cl18_wD_d'length-1), + scout => sov(congr_cl18_wD_offset to congr_cl18_wD_offset + congr_cl18_wD_d'length-1), + din => congr_cl18_wD_d, + dout => congr_cl18_wD_q); +congr_cl18_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl18_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl18_wE_offset to congr_cl18_wE_offset + congr_cl18_wE_d'length-1), + scout => sov(congr_cl18_wE_offset to congr_cl18_wE_offset + congr_cl18_wE_d'length-1), + din => congr_cl18_wE_d, + dout => congr_cl18_wE_q); +congr_cl18_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl18_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl18_wF_offset to congr_cl18_wF_offset + congr_cl18_wF_d'length-1), + scout => sov(congr_cl18_wF_offset to congr_cl18_wF_offset + congr_cl18_wF_d'length-1), + din => congr_cl18_wF_d, + dout => congr_cl18_wF_q); +congr_cl18_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl18_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl18_wG_offset to congr_cl18_wG_offset + congr_cl18_wG_d'length-1), + scout => sov(congr_cl18_wG_offset to congr_cl18_wG_offset + congr_cl18_wG_d'length-1), + din => congr_cl18_wG_d, + dout => congr_cl18_wG_q); +congr_cl18_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl18_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl18_wH_offset to congr_cl18_wH_offset + congr_cl18_wH_d'length-1), + scout => sov(congr_cl18_wH_offset to congr_cl18_wH_offset + congr_cl18_wH_d'length-1), + din => congr_cl18_wH_d, + dout => congr_cl18_wH_q); +congr_cl19_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl19_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl19_wA_offset to congr_cl19_wA_offset + congr_cl19_wA_d'length-1), + scout => sov(congr_cl19_wA_offset to congr_cl19_wA_offset + congr_cl19_wA_d'length-1), + din => congr_cl19_wA_d, + dout => congr_cl19_wA_q); +congr_cl19_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl19_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl19_wB_offset to congr_cl19_wB_offset + congr_cl19_wB_d'length-1), + scout => sov(congr_cl19_wB_offset to congr_cl19_wB_offset + congr_cl19_wB_d'length-1), + din => congr_cl19_wB_d, + dout => congr_cl19_wB_q); +congr_cl19_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl19_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl19_wC_offset to congr_cl19_wC_offset + congr_cl19_wC_d'length-1), + scout => sov(congr_cl19_wC_offset to congr_cl19_wC_offset + congr_cl19_wC_d'length-1), + din => congr_cl19_wC_d, + dout => congr_cl19_wC_q); +congr_cl19_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl19_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl19_wD_offset to congr_cl19_wD_offset + congr_cl19_wD_d'length-1), + scout => sov(congr_cl19_wD_offset to congr_cl19_wD_offset + congr_cl19_wD_d'length-1), + din => congr_cl19_wD_d, + dout => congr_cl19_wD_q); +congr_cl19_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl19_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl19_wE_offset to congr_cl19_wE_offset + congr_cl19_wE_d'length-1), + scout => sov(congr_cl19_wE_offset to congr_cl19_wE_offset + congr_cl19_wE_d'length-1), + din => congr_cl19_wE_d, + dout => congr_cl19_wE_q); +congr_cl19_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl19_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl19_wF_offset to congr_cl19_wF_offset + congr_cl19_wF_d'length-1), + scout => sov(congr_cl19_wF_offset to congr_cl19_wF_offset + congr_cl19_wF_d'length-1), + din => congr_cl19_wF_d, + dout => congr_cl19_wF_q); +congr_cl19_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl19_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl19_wG_offset to congr_cl19_wG_offset + congr_cl19_wG_d'length-1), + scout => sov(congr_cl19_wG_offset to congr_cl19_wG_offset + congr_cl19_wG_d'length-1), + din => congr_cl19_wG_d, + dout => congr_cl19_wG_q); +congr_cl19_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl19_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl19_wH_offset to congr_cl19_wH_offset + congr_cl19_wH_d'length-1), + scout => sov(congr_cl19_wH_offset to congr_cl19_wH_offset + congr_cl19_wH_d'length-1), + din => congr_cl19_wH_d, + dout => congr_cl19_wH_q); +congr_cl20_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl20_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl20_wA_offset to congr_cl20_wA_offset + congr_cl20_wA_d'length-1), + scout => sov(congr_cl20_wA_offset to congr_cl20_wA_offset + congr_cl20_wA_d'length-1), + din => congr_cl20_wA_d, + dout => congr_cl20_wA_q); +congr_cl20_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl20_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl20_wB_offset to congr_cl20_wB_offset + congr_cl20_wB_d'length-1), + scout => sov(congr_cl20_wB_offset to congr_cl20_wB_offset + congr_cl20_wB_d'length-1), + din => congr_cl20_wB_d, + dout => congr_cl20_wB_q); +congr_cl20_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl20_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl20_wC_offset to congr_cl20_wC_offset + congr_cl20_wC_d'length-1), + scout => sov(congr_cl20_wC_offset to congr_cl20_wC_offset + congr_cl20_wC_d'length-1), + din => congr_cl20_wC_d, + dout => congr_cl20_wC_q); +congr_cl20_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl20_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl20_wD_offset to congr_cl20_wD_offset + congr_cl20_wD_d'length-1), + scout => sov(congr_cl20_wD_offset to congr_cl20_wD_offset + congr_cl20_wD_d'length-1), + din => congr_cl20_wD_d, + dout => congr_cl20_wD_q); +congr_cl20_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl20_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl20_wE_offset to congr_cl20_wE_offset + congr_cl20_wE_d'length-1), + scout => sov(congr_cl20_wE_offset to congr_cl20_wE_offset + congr_cl20_wE_d'length-1), + din => congr_cl20_wE_d, + dout => congr_cl20_wE_q); +congr_cl20_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl20_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl20_wF_offset to congr_cl20_wF_offset + congr_cl20_wF_d'length-1), + scout => sov(congr_cl20_wF_offset to congr_cl20_wF_offset + congr_cl20_wF_d'length-1), + din => congr_cl20_wF_d, + dout => congr_cl20_wF_q); +congr_cl20_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl20_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl20_wG_offset to congr_cl20_wG_offset + congr_cl20_wG_d'length-1), + scout => sov(congr_cl20_wG_offset to congr_cl20_wG_offset + congr_cl20_wG_d'length-1), + din => congr_cl20_wG_d, + dout => congr_cl20_wG_q); +congr_cl20_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl20_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl20_wH_offset to congr_cl20_wH_offset + congr_cl20_wH_d'length-1), + scout => sov(congr_cl20_wH_offset to congr_cl20_wH_offset + congr_cl20_wH_d'length-1), + din => congr_cl20_wH_d, + dout => congr_cl20_wH_q); +congr_cl21_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl21_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl21_wA_offset to congr_cl21_wA_offset + congr_cl21_wA_d'length-1), + scout => sov(congr_cl21_wA_offset to congr_cl21_wA_offset + congr_cl21_wA_d'length-1), + din => congr_cl21_wA_d, + dout => congr_cl21_wA_q); +congr_cl21_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl21_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl21_wB_offset to congr_cl21_wB_offset + congr_cl21_wB_d'length-1), + scout => sov(congr_cl21_wB_offset to congr_cl21_wB_offset + congr_cl21_wB_d'length-1), + din => congr_cl21_wB_d, + dout => congr_cl21_wB_q); +congr_cl21_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl21_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl21_wC_offset to congr_cl21_wC_offset + congr_cl21_wC_d'length-1), + scout => sov(congr_cl21_wC_offset to congr_cl21_wC_offset + congr_cl21_wC_d'length-1), + din => congr_cl21_wC_d, + dout => congr_cl21_wC_q); +congr_cl21_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl21_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl21_wD_offset to congr_cl21_wD_offset + congr_cl21_wD_d'length-1), + scout => sov(congr_cl21_wD_offset to congr_cl21_wD_offset + congr_cl21_wD_d'length-1), + din => congr_cl21_wD_d, + dout => congr_cl21_wD_q); +congr_cl21_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl21_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl21_wE_offset to congr_cl21_wE_offset + congr_cl21_wE_d'length-1), + scout => sov(congr_cl21_wE_offset to congr_cl21_wE_offset + congr_cl21_wE_d'length-1), + din => congr_cl21_wE_d, + dout => congr_cl21_wE_q); +congr_cl21_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl21_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl21_wF_offset to congr_cl21_wF_offset + congr_cl21_wF_d'length-1), + scout => sov(congr_cl21_wF_offset to congr_cl21_wF_offset + congr_cl21_wF_d'length-1), + din => congr_cl21_wF_d, + dout => congr_cl21_wF_q); +congr_cl21_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl21_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl21_wG_offset to congr_cl21_wG_offset + congr_cl21_wG_d'length-1), + scout => sov(congr_cl21_wG_offset to congr_cl21_wG_offset + congr_cl21_wG_d'length-1), + din => congr_cl21_wG_d, + dout => congr_cl21_wG_q); +congr_cl21_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl21_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl21_wH_offset to congr_cl21_wH_offset + congr_cl21_wH_d'length-1), + scout => sov(congr_cl21_wH_offset to congr_cl21_wH_offset + congr_cl21_wH_d'length-1), + din => congr_cl21_wH_d, + dout => congr_cl21_wH_q); +congr_cl22_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl22_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl22_wA_offset to congr_cl22_wA_offset + congr_cl22_wA_d'length-1), + scout => sov(congr_cl22_wA_offset to congr_cl22_wA_offset + congr_cl22_wA_d'length-1), + din => congr_cl22_wA_d, + dout => congr_cl22_wA_q); +congr_cl22_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl22_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl22_wB_offset to congr_cl22_wB_offset + congr_cl22_wB_d'length-1), + scout => sov(congr_cl22_wB_offset to congr_cl22_wB_offset + congr_cl22_wB_d'length-1), + din => congr_cl22_wB_d, + dout => congr_cl22_wB_q); +congr_cl22_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl22_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl22_wC_offset to congr_cl22_wC_offset + congr_cl22_wC_d'length-1), + scout => sov(congr_cl22_wC_offset to congr_cl22_wC_offset + congr_cl22_wC_d'length-1), + din => congr_cl22_wC_d, + dout => congr_cl22_wC_q); +congr_cl22_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl22_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl22_wD_offset to congr_cl22_wD_offset + congr_cl22_wD_d'length-1), + scout => sov(congr_cl22_wD_offset to congr_cl22_wD_offset + congr_cl22_wD_d'length-1), + din => congr_cl22_wD_d, + dout => congr_cl22_wD_q); +congr_cl22_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl22_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl22_wE_offset to congr_cl22_wE_offset + congr_cl22_wE_d'length-1), + scout => sov(congr_cl22_wE_offset to congr_cl22_wE_offset + congr_cl22_wE_d'length-1), + din => congr_cl22_wE_d, + dout => congr_cl22_wE_q); +congr_cl22_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl22_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl22_wF_offset to congr_cl22_wF_offset + congr_cl22_wF_d'length-1), + scout => sov(congr_cl22_wF_offset to congr_cl22_wF_offset + congr_cl22_wF_d'length-1), + din => congr_cl22_wF_d, + dout => congr_cl22_wF_q); +congr_cl22_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl22_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl22_wG_offset to congr_cl22_wG_offset + congr_cl22_wG_d'length-1), + scout => sov(congr_cl22_wG_offset to congr_cl22_wG_offset + congr_cl22_wG_d'length-1), + din => congr_cl22_wG_d, + dout => congr_cl22_wG_q); +congr_cl22_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl22_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl22_wH_offset to congr_cl22_wH_offset + congr_cl22_wH_d'length-1), + scout => sov(congr_cl22_wH_offset to congr_cl22_wH_offset + congr_cl22_wH_d'length-1), + din => congr_cl22_wH_d, + dout => congr_cl22_wH_q); +congr_cl23_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl23_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl23_wA_offset to congr_cl23_wA_offset + congr_cl23_wA_d'length-1), + scout => sov(congr_cl23_wA_offset to congr_cl23_wA_offset + congr_cl23_wA_d'length-1), + din => congr_cl23_wA_d, + dout => congr_cl23_wA_q); +congr_cl23_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl23_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl23_wB_offset to congr_cl23_wB_offset + congr_cl23_wB_d'length-1), + scout => sov(congr_cl23_wB_offset to congr_cl23_wB_offset + congr_cl23_wB_d'length-1), + din => congr_cl23_wB_d, + dout => congr_cl23_wB_q); +congr_cl23_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl23_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl23_wC_offset to congr_cl23_wC_offset + congr_cl23_wC_d'length-1), + scout => sov(congr_cl23_wC_offset to congr_cl23_wC_offset + congr_cl23_wC_d'length-1), + din => congr_cl23_wC_d, + dout => congr_cl23_wC_q); +congr_cl23_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl23_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl23_wD_offset to congr_cl23_wD_offset + congr_cl23_wD_d'length-1), + scout => sov(congr_cl23_wD_offset to congr_cl23_wD_offset + congr_cl23_wD_d'length-1), + din => congr_cl23_wD_d, + dout => congr_cl23_wD_q); +congr_cl23_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl23_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl23_wE_offset to congr_cl23_wE_offset + congr_cl23_wE_d'length-1), + scout => sov(congr_cl23_wE_offset to congr_cl23_wE_offset + congr_cl23_wE_d'length-1), + din => congr_cl23_wE_d, + dout => congr_cl23_wE_q); +congr_cl23_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl23_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl23_wF_offset to congr_cl23_wF_offset + congr_cl23_wF_d'length-1), + scout => sov(congr_cl23_wF_offset to congr_cl23_wF_offset + congr_cl23_wF_d'length-1), + din => congr_cl23_wF_d, + dout => congr_cl23_wF_q); +congr_cl23_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl23_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl23_wG_offset to congr_cl23_wG_offset + congr_cl23_wG_d'length-1), + scout => sov(congr_cl23_wG_offset to congr_cl23_wG_offset + congr_cl23_wG_d'length-1), + din => congr_cl23_wG_d, + dout => congr_cl23_wG_q); +congr_cl23_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl23_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl23_wH_offset to congr_cl23_wH_offset + congr_cl23_wH_d'length-1), + scout => sov(congr_cl23_wH_offset to congr_cl23_wH_offset + congr_cl23_wH_d'length-1), + din => congr_cl23_wH_d, + dout => congr_cl23_wH_q); +congr_cl24_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl24_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl24_wA_offset to congr_cl24_wA_offset + congr_cl24_wA_d'length-1), + scout => sov(congr_cl24_wA_offset to congr_cl24_wA_offset + congr_cl24_wA_d'length-1), + din => congr_cl24_wA_d, + dout => congr_cl24_wA_q); +congr_cl24_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl24_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl24_wB_offset to congr_cl24_wB_offset + congr_cl24_wB_d'length-1), + scout => sov(congr_cl24_wB_offset to congr_cl24_wB_offset + congr_cl24_wB_d'length-1), + din => congr_cl24_wB_d, + dout => congr_cl24_wB_q); +congr_cl24_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl24_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl24_wC_offset to congr_cl24_wC_offset + congr_cl24_wC_d'length-1), + scout => sov(congr_cl24_wC_offset to congr_cl24_wC_offset + congr_cl24_wC_d'length-1), + din => congr_cl24_wC_d, + dout => congr_cl24_wC_q); +congr_cl24_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl24_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl24_wD_offset to congr_cl24_wD_offset + congr_cl24_wD_d'length-1), + scout => sov(congr_cl24_wD_offset to congr_cl24_wD_offset + congr_cl24_wD_d'length-1), + din => congr_cl24_wD_d, + dout => congr_cl24_wD_q); +congr_cl24_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl24_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl24_wE_offset to congr_cl24_wE_offset + congr_cl24_wE_d'length-1), + scout => sov(congr_cl24_wE_offset to congr_cl24_wE_offset + congr_cl24_wE_d'length-1), + din => congr_cl24_wE_d, + dout => congr_cl24_wE_q); +congr_cl24_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl24_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl24_wF_offset to congr_cl24_wF_offset + congr_cl24_wF_d'length-1), + scout => sov(congr_cl24_wF_offset to congr_cl24_wF_offset + congr_cl24_wF_d'length-1), + din => congr_cl24_wF_d, + dout => congr_cl24_wF_q); +congr_cl24_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl24_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl24_wG_offset to congr_cl24_wG_offset + congr_cl24_wG_d'length-1), + scout => sov(congr_cl24_wG_offset to congr_cl24_wG_offset + congr_cl24_wG_d'length-1), + din => congr_cl24_wG_d, + dout => congr_cl24_wG_q); +congr_cl24_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl24_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl24_wH_offset to congr_cl24_wH_offset + congr_cl24_wH_d'length-1), + scout => sov(congr_cl24_wH_offset to congr_cl24_wH_offset + congr_cl24_wH_d'length-1), + din => congr_cl24_wH_d, + dout => congr_cl24_wH_q); +congr_cl25_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl25_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl25_wA_offset to congr_cl25_wA_offset + congr_cl25_wA_d'length-1), + scout => sov(congr_cl25_wA_offset to congr_cl25_wA_offset + congr_cl25_wA_d'length-1), + din => congr_cl25_wA_d, + dout => congr_cl25_wA_q); +congr_cl25_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl25_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl25_wB_offset to congr_cl25_wB_offset + congr_cl25_wB_d'length-1), + scout => sov(congr_cl25_wB_offset to congr_cl25_wB_offset + congr_cl25_wB_d'length-1), + din => congr_cl25_wB_d, + dout => congr_cl25_wB_q); +congr_cl25_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl25_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl25_wC_offset to congr_cl25_wC_offset + congr_cl25_wC_d'length-1), + scout => sov(congr_cl25_wC_offset to congr_cl25_wC_offset + congr_cl25_wC_d'length-1), + din => congr_cl25_wC_d, + dout => congr_cl25_wC_q); +congr_cl25_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl25_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl25_wD_offset to congr_cl25_wD_offset + congr_cl25_wD_d'length-1), + scout => sov(congr_cl25_wD_offset to congr_cl25_wD_offset + congr_cl25_wD_d'length-1), + din => congr_cl25_wD_d, + dout => congr_cl25_wD_q); +congr_cl25_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl25_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl25_wE_offset to congr_cl25_wE_offset + congr_cl25_wE_d'length-1), + scout => sov(congr_cl25_wE_offset to congr_cl25_wE_offset + congr_cl25_wE_d'length-1), + din => congr_cl25_wE_d, + dout => congr_cl25_wE_q); +congr_cl25_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl25_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl25_wF_offset to congr_cl25_wF_offset + congr_cl25_wF_d'length-1), + scout => sov(congr_cl25_wF_offset to congr_cl25_wF_offset + congr_cl25_wF_d'length-1), + din => congr_cl25_wF_d, + dout => congr_cl25_wF_q); +congr_cl25_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl25_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl25_wG_offset to congr_cl25_wG_offset + congr_cl25_wG_d'length-1), + scout => sov(congr_cl25_wG_offset to congr_cl25_wG_offset + congr_cl25_wG_d'length-1), + din => congr_cl25_wG_d, + dout => congr_cl25_wG_q); +congr_cl25_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl25_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl25_wH_offset to congr_cl25_wH_offset + congr_cl25_wH_d'length-1), + scout => sov(congr_cl25_wH_offset to congr_cl25_wH_offset + congr_cl25_wH_d'length-1), + din => congr_cl25_wH_d, + dout => congr_cl25_wH_q); +congr_cl26_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl26_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl26_wA_offset to congr_cl26_wA_offset + congr_cl26_wA_d'length-1), + scout => sov(congr_cl26_wA_offset to congr_cl26_wA_offset + congr_cl26_wA_d'length-1), + din => congr_cl26_wA_d, + dout => congr_cl26_wA_q); +congr_cl26_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl26_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl26_wB_offset to congr_cl26_wB_offset + congr_cl26_wB_d'length-1), + scout => sov(congr_cl26_wB_offset to congr_cl26_wB_offset + congr_cl26_wB_d'length-1), + din => congr_cl26_wB_d, + dout => congr_cl26_wB_q); +congr_cl26_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl26_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl26_wC_offset to congr_cl26_wC_offset + congr_cl26_wC_d'length-1), + scout => sov(congr_cl26_wC_offset to congr_cl26_wC_offset + congr_cl26_wC_d'length-1), + din => congr_cl26_wC_d, + dout => congr_cl26_wC_q); +congr_cl26_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl26_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl26_wD_offset to congr_cl26_wD_offset + congr_cl26_wD_d'length-1), + scout => sov(congr_cl26_wD_offset to congr_cl26_wD_offset + congr_cl26_wD_d'length-1), + din => congr_cl26_wD_d, + dout => congr_cl26_wD_q); +congr_cl26_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl26_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl26_wE_offset to congr_cl26_wE_offset + congr_cl26_wE_d'length-1), + scout => sov(congr_cl26_wE_offset to congr_cl26_wE_offset + congr_cl26_wE_d'length-1), + din => congr_cl26_wE_d, + dout => congr_cl26_wE_q); +congr_cl26_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl26_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl26_wF_offset to congr_cl26_wF_offset + congr_cl26_wF_d'length-1), + scout => sov(congr_cl26_wF_offset to congr_cl26_wF_offset + congr_cl26_wF_d'length-1), + din => congr_cl26_wF_d, + dout => congr_cl26_wF_q); +congr_cl26_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl26_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl26_wG_offset to congr_cl26_wG_offset + congr_cl26_wG_d'length-1), + scout => sov(congr_cl26_wG_offset to congr_cl26_wG_offset + congr_cl26_wG_d'length-1), + din => congr_cl26_wG_d, + dout => congr_cl26_wG_q); +congr_cl26_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl26_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl26_wH_offset to congr_cl26_wH_offset + congr_cl26_wH_d'length-1), + scout => sov(congr_cl26_wH_offset to congr_cl26_wH_offset + congr_cl26_wH_d'length-1), + din => congr_cl26_wH_d, + dout => congr_cl26_wH_q); +congr_cl27_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl27_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl27_wA_offset to congr_cl27_wA_offset + congr_cl27_wA_d'length-1), + scout => sov(congr_cl27_wA_offset to congr_cl27_wA_offset + congr_cl27_wA_d'length-1), + din => congr_cl27_wA_d, + dout => congr_cl27_wA_q); +congr_cl27_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl27_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl27_wB_offset to congr_cl27_wB_offset + congr_cl27_wB_d'length-1), + scout => sov(congr_cl27_wB_offset to congr_cl27_wB_offset + congr_cl27_wB_d'length-1), + din => congr_cl27_wB_d, + dout => congr_cl27_wB_q); +congr_cl27_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl27_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl27_wC_offset to congr_cl27_wC_offset + congr_cl27_wC_d'length-1), + scout => sov(congr_cl27_wC_offset to congr_cl27_wC_offset + congr_cl27_wC_d'length-1), + din => congr_cl27_wC_d, + dout => congr_cl27_wC_q); +congr_cl27_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl27_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl27_wD_offset to congr_cl27_wD_offset + congr_cl27_wD_d'length-1), + scout => sov(congr_cl27_wD_offset to congr_cl27_wD_offset + congr_cl27_wD_d'length-1), + din => congr_cl27_wD_d, + dout => congr_cl27_wD_q); +congr_cl27_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl27_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl27_wE_offset to congr_cl27_wE_offset + congr_cl27_wE_d'length-1), + scout => sov(congr_cl27_wE_offset to congr_cl27_wE_offset + congr_cl27_wE_d'length-1), + din => congr_cl27_wE_d, + dout => congr_cl27_wE_q); +congr_cl27_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl27_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl27_wF_offset to congr_cl27_wF_offset + congr_cl27_wF_d'length-1), + scout => sov(congr_cl27_wF_offset to congr_cl27_wF_offset + congr_cl27_wF_d'length-1), + din => congr_cl27_wF_d, + dout => congr_cl27_wF_q); +congr_cl27_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl27_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl27_wG_offset to congr_cl27_wG_offset + congr_cl27_wG_d'length-1), + scout => sov(congr_cl27_wG_offset to congr_cl27_wG_offset + congr_cl27_wG_d'length-1), + din => congr_cl27_wG_d, + dout => congr_cl27_wG_q); +congr_cl27_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl27_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl27_wH_offset to congr_cl27_wH_offset + congr_cl27_wH_d'length-1), + scout => sov(congr_cl27_wH_offset to congr_cl27_wH_offset + congr_cl27_wH_d'length-1), + din => congr_cl27_wH_d, + dout => congr_cl27_wH_q); +congr_cl28_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl28_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl28_wA_offset to congr_cl28_wA_offset + congr_cl28_wA_d'length-1), + scout => sov(congr_cl28_wA_offset to congr_cl28_wA_offset + congr_cl28_wA_d'length-1), + din => congr_cl28_wA_d, + dout => congr_cl28_wA_q); +congr_cl28_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl28_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl28_wB_offset to congr_cl28_wB_offset + congr_cl28_wB_d'length-1), + scout => sov(congr_cl28_wB_offset to congr_cl28_wB_offset + congr_cl28_wB_d'length-1), + din => congr_cl28_wB_d, + dout => congr_cl28_wB_q); +congr_cl28_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl28_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl28_wC_offset to congr_cl28_wC_offset + congr_cl28_wC_d'length-1), + scout => sov(congr_cl28_wC_offset to congr_cl28_wC_offset + congr_cl28_wC_d'length-1), + din => congr_cl28_wC_d, + dout => congr_cl28_wC_q); +congr_cl28_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl28_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl28_wD_offset to congr_cl28_wD_offset + congr_cl28_wD_d'length-1), + scout => sov(congr_cl28_wD_offset to congr_cl28_wD_offset + congr_cl28_wD_d'length-1), + din => congr_cl28_wD_d, + dout => congr_cl28_wD_q); +congr_cl28_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl28_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl28_wE_offset to congr_cl28_wE_offset + congr_cl28_wE_d'length-1), + scout => sov(congr_cl28_wE_offset to congr_cl28_wE_offset + congr_cl28_wE_d'length-1), + din => congr_cl28_wE_d, + dout => congr_cl28_wE_q); +congr_cl28_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl28_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl28_wF_offset to congr_cl28_wF_offset + congr_cl28_wF_d'length-1), + scout => sov(congr_cl28_wF_offset to congr_cl28_wF_offset + congr_cl28_wF_d'length-1), + din => congr_cl28_wF_d, + dout => congr_cl28_wF_q); +congr_cl28_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl28_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl28_wG_offset to congr_cl28_wG_offset + congr_cl28_wG_d'length-1), + scout => sov(congr_cl28_wG_offset to congr_cl28_wG_offset + congr_cl28_wG_d'length-1), + din => congr_cl28_wG_d, + dout => congr_cl28_wG_q); +congr_cl28_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl28_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl28_wH_offset to congr_cl28_wH_offset + congr_cl28_wH_d'length-1), + scout => sov(congr_cl28_wH_offset to congr_cl28_wH_offset + congr_cl28_wH_d'length-1), + din => congr_cl28_wH_d, + dout => congr_cl28_wH_q); +congr_cl29_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl29_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl29_wA_offset to congr_cl29_wA_offset + congr_cl29_wA_d'length-1), + scout => sov(congr_cl29_wA_offset to congr_cl29_wA_offset + congr_cl29_wA_d'length-1), + din => congr_cl29_wA_d, + dout => congr_cl29_wA_q); +congr_cl29_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl29_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl29_wB_offset to congr_cl29_wB_offset + congr_cl29_wB_d'length-1), + scout => sov(congr_cl29_wB_offset to congr_cl29_wB_offset + congr_cl29_wB_d'length-1), + din => congr_cl29_wB_d, + dout => congr_cl29_wB_q); +congr_cl29_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl29_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl29_wC_offset to congr_cl29_wC_offset + congr_cl29_wC_d'length-1), + scout => sov(congr_cl29_wC_offset to congr_cl29_wC_offset + congr_cl29_wC_d'length-1), + din => congr_cl29_wC_d, + dout => congr_cl29_wC_q); +congr_cl29_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl29_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl29_wD_offset to congr_cl29_wD_offset + congr_cl29_wD_d'length-1), + scout => sov(congr_cl29_wD_offset to congr_cl29_wD_offset + congr_cl29_wD_d'length-1), + din => congr_cl29_wD_d, + dout => congr_cl29_wD_q); +congr_cl29_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl29_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl29_wE_offset to congr_cl29_wE_offset + congr_cl29_wE_d'length-1), + scout => sov(congr_cl29_wE_offset to congr_cl29_wE_offset + congr_cl29_wE_d'length-1), + din => congr_cl29_wE_d, + dout => congr_cl29_wE_q); +congr_cl29_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl29_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl29_wF_offset to congr_cl29_wF_offset + congr_cl29_wF_d'length-1), + scout => sov(congr_cl29_wF_offset to congr_cl29_wF_offset + congr_cl29_wF_d'length-1), + din => congr_cl29_wF_d, + dout => congr_cl29_wF_q); +congr_cl29_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl29_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl29_wG_offset to congr_cl29_wG_offset + congr_cl29_wG_d'length-1), + scout => sov(congr_cl29_wG_offset to congr_cl29_wG_offset + congr_cl29_wG_d'length-1), + din => congr_cl29_wG_d, + dout => congr_cl29_wG_q); +congr_cl29_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl29_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl29_wH_offset to congr_cl29_wH_offset + congr_cl29_wH_d'length-1), + scout => sov(congr_cl29_wH_offset to congr_cl29_wH_offset + congr_cl29_wH_d'length-1), + din => congr_cl29_wH_d, + dout => congr_cl29_wH_q); +congr_cl30_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl30_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl30_wA_offset to congr_cl30_wA_offset + congr_cl30_wA_d'length-1), + scout => sov(congr_cl30_wA_offset to congr_cl30_wA_offset + congr_cl30_wA_d'length-1), + din => congr_cl30_wA_d, + dout => congr_cl30_wA_q); +congr_cl30_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl30_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl30_wB_offset to congr_cl30_wB_offset + congr_cl30_wB_d'length-1), + scout => sov(congr_cl30_wB_offset to congr_cl30_wB_offset + congr_cl30_wB_d'length-1), + din => congr_cl30_wB_d, + dout => congr_cl30_wB_q); +congr_cl30_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl30_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl30_wC_offset to congr_cl30_wC_offset + congr_cl30_wC_d'length-1), + scout => sov(congr_cl30_wC_offset to congr_cl30_wC_offset + congr_cl30_wC_d'length-1), + din => congr_cl30_wC_d, + dout => congr_cl30_wC_q); +congr_cl30_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl30_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl30_wD_offset to congr_cl30_wD_offset + congr_cl30_wD_d'length-1), + scout => sov(congr_cl30_wD_offset to congr_cl30_wD_offset + congr_cl30_wD_d'length-1), + din => congr_cl30_wD_d, + dout => congr_cl30_wD_q); +congr_cl30_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl30_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl30_wE_offset to congr_cl30_wE_offset + congr_cl30_wE_d'length-1), + scout => sov(congr_cl30_wE_offset to congr_cl30_wE_offset + congr_cl30_wE_d'length-1), + din => congr_cl30_wE_d, + dout => congr_cl30_wE_q); +congr_cl30_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl30_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl30_wF_offset to congr_cl30_wF_offset + congr_cl30_wF_d'length-1), + scout => sov(congr_cl30_wF_offset to congr_cl30_wF_offset + congr_cl30_wF_d'length-1), + din => congr_cl30_wF_d, + dout => congr_cl30_wF_q); +congr_cl30_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl30_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl30_wG_offset to congr_cl30_wG_offset + congr_cl30_wG_d'length-1), + scout => sov(congr_cl30_wG_offset to congr_cl30_wG_offset + congr_cl30_wG_d'length-1), + din => congr_cl30_wG_d, + dout => congr_cl30_wG_q); +congr_cl30_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl30_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl30_wH_offset to congr_cl30_wH_offset + congr_cl30_wH_d'length-1), + scout => sov(congr_cl30_wH_offset to congr_cl30_wH_offset + congr_cl30_wH_d'length-1), + din => congr_cl30_wH_d, + dout => congr_cl30_wH_q); +congr_cl31_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl31_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl31_wA_offset to congr_cl31_wA_offset + congr_cl31_wA_d'length-1), + scout => sov(congr_cl31_wA_offset to congr_cl31_wA_offset + congr_cl31_wA_d'length-1), + din => congr_cl31_wA_d, + dout => congr_cl31_wA_q); +congr_cl31_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl31_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl31_wB_offset to congr_cl31_wB_offset + congr_cl31_wB_d'length-1), + scout => sov(congr_cl31_wB_offset to congr_cl31_wB_offset + congr_cl31_wB_d'length-1), + din => congr_cl31_wB_d, + dout => congr_cl31_wB_q); +congr_cl31_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl31_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl31_wC_offset to congr_cl31_wC_offset + congr_cl31_wC_d'length-1), + scout => sov(congr_cl31_wC_offset to congr_cl31_wC_offset + congr_cl31_wC_d'length-1), + din => congr_cl31_wC_d, + dout => congr_cl31_wC_q); +congr_cl31_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl31_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl31_wD_offset to congr_cl31_wD_offset + congr_cl31_wD_d'length-1), + scout => sov(congr_cl31_wD_offset to congr_cl31_wD_offset + congr_cl31_wD_d'length-1), + din => congr_cl31_wD_d, + dout => congr_cl31_wD_q); +congr_cl31_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl31_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl31_wE_offset to congr_cl31_wE_offset + congr_cl31_wE_d'length-1), + scout => sov(congr_cl31_wE_offset to congr_cl31_wE_offset + congr_cl31_wE_d'length-1), + din => congr_cl31_wE_d, + dout => congr_cl31_wE_q); +congr_cl31_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl31_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl31_wF_offset to congr_cl31_wF_offset + congr_cl31_wF_d'length-1), + scout => sov(congr_cl31_wF_offset to congr_cl31_wF_offset + congr_cl31_wF_d'length-1), + din => congr_cl31_wF_d, + dout => congr_cl31_wF_q); +congr_cl31_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl31_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl31_wG_offset to congr_cl31_wG_offset + congr_cl31_wG_d'length-1), + scout => sov(congr_cl31_wG_offset to congr_cl31_wG_offset + congr_cl31_wG_d'length-1), + din => congr_cl31_wG_d, + dout => congr_cl31_wG_q); +congr_cl31_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl31_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl31_wH_offset to congr_cl31_wH_offset + congr_cl31_wH_d'length-1), + scout => sov(congr_cl31_wH_offset to congr_cl31_wH_offset + congr_cl31_wH_d'length-1), + din => congr_cl31_wH_d, + dout => congr_cl31_wH_q); +congr_cl32_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl32_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl32_wA_offset to congr_cl32_wA_offset + congr_cl32_wA_d'length-1), + scout => sov(congr_cl32_wA_offset to congr_cl32_wA_offset + congr_cl32_wA_d'length-1), + din => congr_cl32_wA_d, + dout => congr_cl32_wA_q); +congr_cl32_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl32_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl32_wB_offset to congr_cl32_wB_offset + congr_cl32_wB_d'length-1), + scout => sov(congr_cl32_wB_offset to congr_cl32_wB_offset + congr_cl32_wB_d'length-1), + din => congr_cl32_wB_d, + dout => congr_cl32_wB_q); +congr_cl32_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl32_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl32_wC_offset to congr_cl32_wC_offset + congr_cl32_wC_d'length-1), + scout => sov(congr_cl32_wC_offset to congr_cl32_wC_offset + congr_cl32_wC_d'length-1), + din => congr_cl32_wC_d, + dout => congr_cl32_wC_q); +congr_cl32_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl32_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl32_wD_offset to congr_cl32_wD_offset + congr_cl32_wD_d'length-1), + scout => sov(congr_cl32_wD_offset to congr_cl32_wD_offset + congr_cl32_wD_d'length-1), + din => congr_cl32_wD_d, + dout => congr_cl32_wD_q); +congr_cl32_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl32_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl32_wE_offset to congr_cl32_wE_offset + congr_cl32_wE_d'length-1), + scout => sov(congr_cl32_wE_offset to congr_cl32_wE_offset + congr_cl32_wE_d'length-1), + din => congr_cl32_wE_d, + dout => congr_cl32_wE_q); +congr_cl32_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl32_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl32_wF_offset to congr_cl32_wF_offset + congr_cl32_wF_d'length-1), + scout => sov(congr_cl32_wF_offset to congr_cl32_wF_offset + congr_cl32_wF_d'length-1), + din => congr_cl32_wF_d, + dout => congr_cl32_wF_q); +congr_cl32_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl32_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl32_wG_offset to congr_cl32_wG_offset + congr_cl32_wG_d'length-1), + scout => sov(congr_cl32_wG_offset to congr_cl32_wG_offset + congr_cl32_wG_d'length-1), + din => congr_cl32_wG_d, + dout => congr_cl32_wG_q); +congr_cl32_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl32_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl32_wH_offset to congr_cl32_wH_offset + congr_cl32_wH_d'length-1), + scout => sov(congr_cl32_wH_offset to congr_cl32_wH_offset + congr_cl32_wH_d'length-1), + din => congr_cl32_wH_d, + dout => congr_cl32_wH_q); +congr_cl33_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl33_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl33_wA_offset to congr_cl33_wA_offset + congr_cl33_wA_d'length-1), + scout => sov(congr_cl33_wA_offset to congr_cl33_wA_offset + congr_cl33_wA_d'length-1), + din => congr_cl33_wA_d, + dout => congr_cl33_wA_q); +congr_cl33_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl33_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl33_wB_offset to congr_cl33_wB_offset + congr_cl33_wB_d'length-1), + scout => sov(congr_cl33_wB_offset to congr_cl33_wB_offset + congr_cl33_wB_d'length-1), + din => congr_cl33_wB_d, + dout => congr_cl33_wB_q); +congr_cl33_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl33_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl33_wC_offset to congr_cl33_wC_offset + congr_cl33_wC_d'length-1), + scout => sov(congr_cl33_wC_offset to congr_cl33_wC_offset + congr_cl33_wC_d'length-1), + din => congr_cl33_wC_d, + dout => congr_cl33_wC_q); +congr_cl33_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl33_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl33_wD_offset to congr_cl33_wD_offset + congr_cl33_wD_d'length-1), + scout => sov(congr_cl33_wD_offset to congr_cl33_wD_offset + congr_cl33_wD_d'length-1), + din => congr_cl33_wD_d, + dout => congr_cl33_wD_q); +congr_cl33_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl33_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl33_wE_offset to congr_cl33_wE_offset + congr_cl33_wE_d'length-1), + scout => sov(congr_cl33_wE_offset to congr_cl33_wE_offset + congr_cl33_wE_d'length-1), + din => congr_cl33_wE_d, + dout => congr_cl33_wE_q); +congr_cl33_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl33_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl33_wF_offset to congr_cl33_wF_offset + congr_cl33_wF_d'length-1), + scout => sov(congr_cl33_wF_offset to congr_cl33_wF_offset + congr_cl33_wF_d'length-1), + din => congr_cl33_wF_d, + dout => congr_cl33_wF_q); +congr_cl33_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl33_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl33_wG_offset to congr_cl33_wG_offset + congr_cl33_wG_d'length-1), + scout => sov(congr_cl33_wG_offset to congr_cl33_wG_offset + congr_cl33_wG_d'length-1), + din => congr_cl33_wG_d, + dout => congr_cl33_wG_q); +congr_cl33_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl33_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl33_wH_offset to congr_cl33_wH_offset + congr_cl33_wH_d'length-1), + scout => sov(congr_cl33_wH_offset to congr_cl33_wH_offset + congr_cl33_wH_d'length-1), + din => congr_cl33_wH_d, + dout => congr_cl33_wH_q); +congr_cl34_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl34_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl34_wA_offset to congr_cl34_wA_offset + congr_cl34_wA_d'length-1), + scout => sov(congr_cl34_wA_offset to congr_cl34_wA_offset + congr_cl34_wA_d'length-1), + din => congr_cl34_wA_d, + dout => congr_cl34_wA_q); +congr_cl34_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl34_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl34_wB_offset to congr_cl34_wB_offset + congr_cl34_wB_d'length-1), + scout => sov(congr_cl34_wB_offset to congr_cl34_wB_offset + congr_cl34_wB_d'length-1), + din => congr_cl34_wB_d, + dout => congr_cl34_wB_q); +congr_cl34_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl34_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl34_wC_offset to congr_cl34_wC_offset + congr_cl34_wC_d'length-1), + scout => sov(congr_cl34_wC_offset to congr_cl34_wC_offset + congr_cl34_wC_d'length-1), + din => congr_cl34_wC_d, + dout => congr_cl34_wC_q); +congr_cl34_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl34_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl34_wD_offset to congr_cl34_wD_offset + congr_cl34_wD_d'length-1), + scout => sov(congr_cl34_wD_offset to congr_cl34_wD_offset + congr_cl34_wD_d'length-1), + din => congr_cl34_wD_d, + dout => congr_cl34_wD_q); +congr_cl34_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl34_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl34_wE_offset to congr_cl34_wE_offset + congr_cl34_wE_d'length-1), + scout => sov(congr_cl34_wE_offset to congr_cl34_wE_offset + congr_cl34_wE_d'length-1), + din => congr_cl34_wE_d, + dout => congr_cl34_wE_q); +congr_cl34_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl34_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl34_wF_offset to congr_cl34_wF_offset + congr_cl34_wF_d'length-1), + scout => sov(congr_cl34_wF_offset to congr_cl34_wF_offset + congr_cl34_wF_d'length-1), + din => congr_cl34_wF_d, + dout => congr_cl34_wF_q); +congr_cl34_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl34_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl34_wG_offset to congr_cl34_wG_offset + congr_cl34_wG_d'length-1), + scout => sov(congr_cl34_wG_offset to congr_cl34_wG_offset + congr_cl34_wG_d'length-1), + din => congr_cl34_wG_d, + dout => congr_cl34_wG_q); +congr_cl34_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl34_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl34_wH_offset to congr_cl34_wH_offset + congr_cl34_wH_d'length-1), + scout => sov(congr_cl34_wH_offset to congr_cl34_wH_offset + congr_cl34_wH_d'length-1), + din => congr_cl34_wH_d, + dout => congr_cl34_wH_q); +congr_cl35_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl35_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl35_wA_offset to congr_cl35_wA_offset + congr_cl35_wA_d'length-1), + scout => sov(congr_cl35_wA_offset to congr_cl35_wA_offset + congr_cl35_wA_d'length-1), + din => congr_cl35_wA_d, + dout => congr_cl35_wA_q); +congr_cl35_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl35_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl35_wB_offset to congr_cl35_wB_offset + congr_cl35_wB_d'length-1), + scout => sov(congr_cl35_wB_offset to congr_cl35_wB_offset + congr_cl35_wB_d'length-1), + din => congr_cl35_wB_d, + dout => congr_cl35_wB_q); +congr_cl35_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl35_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl35_wC_offset to congr_cl35_wC_offset + congr_cl35_wC_d'length-1), + scout => sov(congr_cl35_wC_offset to congr_cl35_wC_offset + congr_cl35_wC_d'length-1), + din => congr_cl35_wC_d, + dout => congr_cl35_wC_q); +congr_cl35_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl35_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl35_wD_offset to congr_cl35_wD_offset + congr_cl35_wD_d'length-1), + scout => sov(congr_cl35_wD_offset to congr_cl35_wD_offset + congr_cl35_wD_d'length-1), + din => congr_cl35_wD_d, + dout => congr_cl35_wD_q); +congr_cl35_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl35_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl35_wE_offset to congr_cl35_wE_offset + congr_cl35_wE_d'length-1), + scout => sov(congr_cl35_wE_offset to congr_cl35_wE_offset + congr_cl35_wE_d'length-1), + din => congr_cl35_wE_d, + dout => congr_cl35_wE_q); +congr_cl35_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl35_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl35_wF_offset to congr_cl35_wF_offset + congr_cl35_wF_d'length-1), + scout => sov(congr_cl35_wF_offset to congr_cl35_wF_offset + congr_cl35_wF_d'length-1), + din => congr_cl35_wF_d, + dout => congr_cl35_wF_q); +congr_cl35_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl35_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl35_wG_offset to congr_cl35_wG_offset + congr_cl35_wG_d'length-1), + scout => sov(congr_cl35_wG_offset to congr_cl35_wG_offset + congr_cl35_wG_d'length-1), + din => congr_cl35_wG_d, + dout => congr_cl35_wG_q); +congr_cl35_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl35_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl35_wH_offset to congr_cl35_wH_offset + congr_cl35_wH_d'length-1), + scout => sov(congr_cl35_wH_offset to congr_cl35_wH_offset + congr_cl35_wH_d'length-1), + din => congr_cl35_wH_d, + dout => congr_cl35_wH_q); +congr_cl36_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl36_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl36_wA_offset to congr_cl36_wA_offset + congr_cl36_wA_d'length-1), + scout => sov(congr_cl36_wA_offset to congr_cl36_wA_offset + congr_cl36_wA_d'length-1), + din => congr_cl36_wA_d, + dout => congr_cl36_wA_q); +congr_cl36_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl36_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl36_wB_offset to congr_cl36_wB_offset + congr_cl36_wB_d'length-1), + scout => sov(congr_cl36_wB_offset to congr_cl36_wB_offset + congr_cl36_wB_d'length-1), + din => congr_cl36_wB_d, + dout => congr_cl36_wB_q); +congr_cl36_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl36_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl36_wC_offset to congr_cl36_wC_offset + congr_cl36_wC_d'length-1), + scout => sov(congr_cl36_wC_offset to congr_cl36_wC_offset + congr_cl36_wC_d'length-1), + din => congr_cl36_wC_d, + dout => congr_cl36_wC_q); +congr_cl36_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl36_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl36_wD_offset to congr_cl36_wD_offset + congr_cl36_wD_d'length-1), + scout => sov(congr_cl36_wD_offset to congr_cl36_wD_offset + congr_cl36_wD_d'length-1), + din => congr_cl36_wD_d, + dout => congr_cl36_wD_q); +congr_cl36_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl36_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl36_wE_offset to congr_cl36_wE_offset + congr_cl36_wE_d'length-1), + scout => sov(congr_cl36_wE_offset to congr_cl36_wE_offset + congr_cl36_wE_d'length-1), + din => congr_cl36_wE_d, + dout => congr_cl36_wE_q); +congr_cl36_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl36_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl36_wF_offset to congr_cl36_wF_offset + congr_cl36_wF_d'length-1), + scout => sov(congr_cl36_wF_offset to congr_cl36_wF_offset + congr_cl36_wF_d'length-1), + din => congr_cl36_wF_d, + dout => congr_cl36_wF_q); +congr_cl36_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl36_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl36_wG_offset to congr_cl36_wG_offset + congr_cl36_wG_d'length-1), + scout => sov(congr_cl36_wG_offset to congr_cl36_wG_offset + congr_cl36_wG_d'length-1), + din => congr_cl36_wG_d, + dout => congr_cl36_wG_q); +congr_cl36_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl36_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl36_wH_offset to congr_cl36_wH_offset + congr_cl36_wH_d'length-1), + scout => sov(congr_cl36_wH_offset to congr_cl36_wH_offset + congr_cl36_wH_d'length-1), + din => congr_cl36_wH_d, + dout => congr_cl36_wH_q); +congr_cl37_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl37_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl37_wA_offset to congr_cl37_wA_offset + congr_cl37_wA_d'length-1), + scout => sov(congr_cl37_wA_offset to congr_cl37_wA_offset + congr_cl37_wA_d'length-1), + din => congr_cl37_wA_d, + dout => congr_cl37_wA_q); +congr_cl37_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl37_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl37_wB_offset to congr_cl37_wB_offset + congr_cl37_wB_d'length-1), + scout => sov(congr_cl37_wB_offset to congr_cl37_wB_offset + congr_cl37_wB_d'length-1), + din => congr_cl37_wB_d, + dout => congr_cl37_wB_q); +congr_cl37_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl37_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl37_wC_offset to congr_cl37_wC_offset + congr_cl37_wC_d'length-1), + scout => sov(congr_cl37_wC_offset to congr_cl37_wC_offset + congr_cl37_wC_d'length-1), + din => congr_cl37_wC_d, + dout => congr_cl37_wC_q); +congr_cl37_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl37_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl37_wD_offset to congr_cl37_wD_offset + congr_cl37_wD_d'length-1), + scout => sov(congr_cl37_wD_offset to congr_cl37_wD_offset + congr_cl37_wD_d'length-1), + din => congr_cl37_wD_d, + dout => congr_cl37_wD_q); +congr_cl37_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl37_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl37_wE_offset to congr_cl37_wE_offset + congr_cl37_wE_d'length-1), + scout => sov(congr_cl37_wE_offset to congr_cl37_wE_offset + congr_cl37_wE_d'length-1), + din => congr_cl37_wE_d, + dout => congr_cl37_wE_q); +congr_cl37_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl37_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl37_wF_offset to congr_cl37_wF_offset + congr_cl37_wF_d'length-1), + scout => sov(congr_cl37_wF_offset to congr_cl37_wF_offset + congr_cl37_wF_d'length-1), + din => congr_cl37_wF_d, + dout => congr_cl37_wF_q); +congr_cl37_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl37_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl37_wG_offset to congr_cl37_wG_offset + congr_cl37_wG_d'length-1), + scout => sov(congr_cl37_wG_offset to congr_cl37_wG_offset + congr_cl37_wG_d'length-1), + din => congr_cl37_wG_d, + dout => congr_cl37_wG_q); +congr_cl37_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl37_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl37_wH_offset to congr_cl37_wH_offset + congr_cl37_wH_d'length-1), + scout => sov(congr_cl37_wH_offset to congr_cl37_wH_offset + congr_cl37_wH_d'length-1), + din => congr_cl37_wH_d, + dout => congr_cl37_wH_q); +congr_cl38_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl38_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl38_wA_offset to congr_cl38_wA_offset + congr_cl38_wA_d'length-1), + scout => sov(congr_cl38_wA_offset to congr_cl38_wA_offset + congr_cl38_wA_d'length-1), + din => congr_cl38_wA_d, + dout => congr_cl38_wA_q); +congr_cl38_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl38_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl38_wB_offset to congr_cl38_wB_offset + congr_cl38_wB_d'length-1), + scout => sov(congr_cl38_wB_offset to congr_cl38_wB_offset + congr_cl38_wB_d'length-1), + din => congr_cl38_wB_d, + dout => congr_cl38_wB_q); +congr_cl38_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl38_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl38_wC_offset to congr_cl38_wC_offset + congr_cl38_wC_d'length-1), + scout => sov(congr_cl38_wC_offset to congr_cl38_wC_offset + congr_cl38_wC_d'length-1), + din => congr_cl38_wC_d, + dout => congr_cl38_wC_q); +congr_cl38_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl38_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl38_wD_offset to congr_cl38_wD_offset + congr_cl38_wD_d'length-1), + scout => sov(congr_cl38_wD_offset to congr_cl38_wD_offset + congr_cl38_wD_d'length-1), + din => congr_cl38_wD_d, + dout => congr_cl38_wD_q); +congr_cl38_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl38_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl38_wE_offset to congr_cl38_wE_offset + congr_cl38_wE_d'length-1), + scout => sov(congr_cl38_wE_offset to congr_cl38_wE_offset + congr_cl38_wE_d'length-1), + din => congr_cl38_wE_d, + dout => congr_cl38_wE_q); +congr_cl38_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl38_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl38_wF_offset to congr_cl38_wF_offset + congr_cl38_wF_d'length-1), + scout => sov(congr_cl38_wF_offset to congr_cl38_wF_offset + congr_cl38_wF_d'length-1), + din => congr_cl38_wF_d, + dout => congr_cl38_wF_q); +congr_cl38_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl38_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl38_wG_offset to congr_cl38_wG_offset + congr_cl38_wG_d'length-1), + scout => sov(congr_cl38_wG_offset to congr_cl38_wG_offset + congr_cl38_wG_d'length-1), + din => congr_cl38_wG_d, + dout => congr_cl38_wG_q); +congr_cl38_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl38_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl38_wH_offset to congr_cl38_wH_offset + congr_cl38_wH_d'length-1), + scout => sov(congr_cl38_wH_offset to congr_cl38_wH_offset + congr_cl38_wH_d'length-1), + din => congr_cl38_wH_d, + dout => congr_cl38_wH_q); +congr_cl39_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl39_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl39_wA_offset to congr_cl39_wA_offset + congr_cl39_wA_d'length-1), + scout => sov(congr_cl39_wA_offset to congr_cl39_wA_offset + congr_cl39_wA_d'length-1), + din => congr_cl39_wA_d, + dout => congr_cl39_wA_q); +congr_cl39_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl39_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl39_wB_offset to congr_cl39_wB_offset + congr_cl39_wB_d'length-1), + scout => sov(congr_cl39_wB_offset to congr_cl39_wB_offset + congr_cl39_wB_d'length-1), + din => congr_cl39_wB_d, + dout => congr_cl39_wB_q); +congr_cl39_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl39_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl39_wC_offset to congr_cl39_wC_offset + congr_cl39_wC_d'length-1), + scout => sov(congr_cl39_wC_offset to congr_cl39_wC_offset + congr_cl39_wC_d'length-1), + din => congr_cl39_wC_d, + dout => congr_cl39_wC_q); +congr_cl39_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl39_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl39_wD_offset to congr_cl39_wD_offset + congr_cl39_wD_d'length-1), + scout => sov(congr_cl39_wD_offset to congr_cl39_wD_offset + congr_cl39_wD_d'length-1), + din => congr_cl39_wD_d, + dout => congr_cl39_wD_q); +congr_cl39_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl39_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl39_wE_offset to congr_cl39_wE_offset + congr_cl39_wE_d'length-1), + scout => sov(congr_cl39_wE_offset to congr_cl39_wE_offset + congr_cl39_wE_d'length-1), + din => congr_cl39_wE_d, + dout => congr_cl39_wE_q); +congr_cl39_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl39_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl39_wF_offset to congr_cl39_wF_offset + congr_cl39_wF_d'length-1), + scout => sov(congr_cl39_wF_offset to congr_cl39_wF_offset + congr_cl39_wF_d'length-1), + din => congr_cl39_wF_d, + dout => congr_cl39_wF_q); +congr_cl39_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl39_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl39_wG_offset to congr_cl39_wG_offset + congr_cl39_wG_d'length-1), + scout => sov(congr_cl39_wG_offset to congr_cl39_wG_offset + congr_cl39_wG_d'length-1), + din => congr_cl39_wG_d, + dout => congr_cl39_wG_q); +congr_cl39_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl39_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl39_wH_offset to congr_cl39_wH_offset + congr_cl39_wH_d'length-1), + scout => sov(congr_cl39_wH_offset to congr_cl39_wH_offset + congr_cl39_wH_d'length-1), + din => congr_cl39_wH_d, + dout => congr_cl39_wH_q); +congr_cl40_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl40_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl40_wA_offset to congr_cl40_wA_offset + congr_cl40_wA_d'length-1), + scout => sov(congr_cl40_wA_offset to congr_cl40_wA_offset + congr_cl40_wA_d'length-1), + din => congr_cl40_wA_d, + dout => congr_cl40_wA_q); +congr_cl40_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl40_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl40_wB_offset to congr_cl40_wB_offset + congr_cl40_wB_d'length-1), + scout => sov(congr_cl40_wB_offset to congr_cl40_wB_offset + congr_cl40_wB_d'length-1), + din => congr_cl40_wB_d, + dout => congr_cl40_wB_q); +congr_cl40_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl40_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl40_wC_offset to congr_cl40_wC_offset + congr_cl40_wC_d'length-1), + scout => sov(congr_cl40_wC_offset to congr_cl40_wC_offset + congr_cl40_wC_d'length-1), + din => congr_cl40_wC_d, + dout => congr_cl40_wC_q); +congr_cl40_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl40_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl40_wD_offset to congr_cl40_wD_offset + congr_cl40_wD_d'length-1), + scout => sov(congr_cl40_wD_offset to congr_cl40_wD_offset + congr_cl40_wD_d'length-1), + din => congr_cl40_wD_d, + dout => congr_cl40_wD_q); +congr_cl40_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl40_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl40_wE_offset to congr_cl40_wE_offset + congr_cl40_wE_d'length-1), + scout => sov(congr_cl40_wE_offset to congr_cl40_wE_offset + congr_cl40_wE_d'length-1), + din => congr_cl40_wE_d, + dout => congr_cl40_wE_q); +congr_cl40_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl40_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl40_wF_offset to congr_cl40_wF_offset + congr_cl40_wF_d'length-1), + scout => sov(congr_cl40_wF_offset to congr_cl40_wF_offset + congr_cl40_wF_d'length-1), + din => congr_cl40_wF_d, + dout => congr_cl40_wF_q); +congr_cl40_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl40_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl40_wG_offset to congr_cl40_wG_offset + congr_cl40_wG_d'length-1), + scout => sov(congr_cl40_wG_offset to congr_cl40_wG_offset + congr_cl40_wG_d'length-1), + din => congr_cl40_wG_d, + dout => congr_cl40_wG_q); +congr_cl40_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl40_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl40_wH_offset to congr_cl40_wH_offset + congr_cl40_wH_d'length-1), + scout => sov(congr_cl40_wH_offset to congr_cl40_wH_offset + congr_cl40_wH_d'length-1), + din => congr_cl40_wH_d, + dout => congr_cl40_wH_q); +congr_cl41_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl41_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl41_wA_offset to congr_cl41_wA_offset + congr_cl41_wA_d'length-1), + scout => sov(congr_cl41_wA_offset to congr_cl41_wA_offset + congr_cl41_wA_d'length-1), + din => congr_cl41_wA_d, + dout => congr_cl41_wA_q); +congr_cl41_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl41_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl41_wB_offset to congr_cl41_wB_offset + congr_cl41_wB_d'length-1), + scout => sov(congr_cl41_wB_offset to congr_cl41_wB_offset + congr_cl41_wB_d'length-1), + din => congr_cl41_wB_d, + dout => congr_cl41_wB_q); +congr_cl41_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl41_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl41_wC_offset to congr_cl41_wC_offset + congr_cl41_wC_d'length-1), + scout => sov(congr_cl41_wC_offset to congr_cl41_wC_offset + congr_cl41_wC_d'length-1), + din => congr_cl41_wC_d, + dout => congr_cl41_wC_q); +congr_cl41_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl41_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl41_wD_offset to congr_cl41_wD_offset + congr_cl41_wD_d'length-1), + scout => sov(congr_cl41_wD_offset to congr_cl41_wD_offset + congr_cl41_wD_d'length-1), + din => congr_cl41_wD_d, + dout => congr_cl41_wD_q); +congr_cl41_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl41_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl41_wE_offset to congr_cl41_wE_offset + congr_cl41_wE_d'length-1), + scout => sov(congr_cl41_wE_offset to congr_cl41_wE_offset + congr_cl41_wE_d'length-1), + din => congr_cl41_wE_d, + dout => congr_cl41_wE_q); +congr_cl41_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl41_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl41_wF_offset to congr_cl41_wF_offset + congr_cl41_wF_d'length-1), + scout => sov(congr_cl41_wF_offset to congr_cl41_wF_offset + congr_cl41_wF_d'length-1), + din => congr_cl41_wF_d, + dout => congr_cl41_wF_q); +congr_cl41_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl41_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl41_wG_offset to congr_cl41_wG_offset + congr_cl41_wG_d'length-1), + scout => sov(congr_cl41_wG_offset to congr_cl41_wG_offset + congr_cl41_wG_d'length-1), + din => congr_cl41_wG_d, + dout => congr_cl41_wG_q); +congr_cl41_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl41_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl41_wH_offset to congr_cl41_wH_offset + congr_cl41_wH_d'length-1), + scout => sov(congr_cl41_wH_offset to congr_cl41_wH_offset + congr_cl41_wH_d'length-1), + din => congr_cl41_wH_d, + dout => congr_cl41_wH_q); +congr_cl42_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl42_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl42_wA_offset to congr_cl42_wA_offset + congr_cl42_wA_d'length-1), + scout => sov(congr_cl42_wA_offset to congr_cl42_wA_offset + congr_cl42_wA_d'length-1), + din => congr_cl42_wA_d, + dout => congr_cl42_wA_q); +congr_cl42_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl42_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl42_wB_offset to congr_cl42_wB_offset + congr_cl42_wB_d'length-1), + scout => sov(congr_cl42_wB_offset to congr_cl42_wB_offset + congr_cl42_wB_d'length-1), + din => congr_cl42_wB_d, + dout => congr_cl42_wB_q); +congr_cl42_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl42_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl42_wC_offset to congr_cl42_wC_offset + congr_cl42_wC_d'length-1), + scout => sov(congr_cl42_wC_offset to congr_cl42_wC_offset + congr_cl42_wC_d'length-1), + din => congr_cl42_wC_d, + dout => congr_cl42_wC_q); +congr_cl42_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl42_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl42_wD_offset to congr_cl42_wD_offset + congr_cl42_wD_d'length-1), + scout => sov(congr_cl42_wD_offset to congr_cl42_wD_offset + congr_cl42_wD_d'length-1), + din => congr_cl42_wD_d, + dout => congr_cl42_wD_q); +congr_cl42_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl42_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl42_wE_offset to congr_cl42_wE_offset + congr_cl42_wE_d'length-1), + scout => sov(congr_cl42_wE_offset to congr_cl42_wE_offset + congr_cl42_wE_d'length-1), + din => congr_cl42_wE_d, + dout => congr_cl42_wE_q); +congr_cl42_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl42_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl42_wF_offset to congr_cl42_wF_offset + congr_cl42_wF_d'length-1), + scout => sov(congr_cl42_wF_offset to congr_cl42_wF_offset + congr_cl42_wF_d'length-1), + din => congr_cl42_wF_d, + dout => congr_cl42_wF_q); +congr_cl42_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl42_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl42_wG_offset to congr_cl42_wG_offset + congr_cl42_wG_d'length-1), + scout => sov(congr_cl42_wG_offset to congr_cl42_wG_offset + congr_cl42_wG_d'length-1), + din => congr_cl42_wG_d, + dout => congr_cl42_wG_q); +congr_cl42_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl42_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl42_wH_offset to congr_cl42_wH_offset + congr_cl42_wH_d'length-1), + scout => sov(congr_cl42_wH_offset to congr_cl42_wH_offset + congr_cl42_wH_d'length-1), + din => congr_cl42_wH_d, + dout => congr_cl42_wH_q); +congr_cl43_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl43_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl43_wA_offset to congr_cl43_wA_offset + congr_cl43_wA_d'length-1), + scout => sov(congr_cl43_wA_offset to congr_cl43_wA_offset + congr_cl43_wA_d'length-1), + din => congr_cl43_wA_d, + dout => congr_cl43_wA_q); +congr_cl43_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl43_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl43_wB_offset to congr_cl43_wB_offset + congr_cl43_wB_d'length-1), + scout => sov(congr_cl43_wB_offset to congr_cl43_wB_offset + congr_cl43_wB_d'length-1), + din => congr_cl43_wB_d, + dout => congr_cl43_wB_q); +congr_cl43_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl43_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl43_wC_offset to congr_cl43_wC_offset + congr_cl43_wC_d'length-1), + scout => sov(congr_cl43_wC_offset to congr_cl43_wC_offset + congr_cl43_wC_d'length-1), + din => congr_cl43_wC_d, + dout => congr_cl43_wC_q); +congr_cl43_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl43_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl43_wD_offset to congr_cl43_wD_offset + congr_cl43_wD_d'length-1), + scout => sov(congr_cl43_wD_offset to congr_cl43_wD_offset + congr_cl43_wD_d'length-1), + din => congr_cl43_wD_d, + dout => congr_cl43_wD_q); +congr_cl43_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl43_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl43_wE_offset to congr_cl43_wE_offset + congr_cl43_wE_d'length-1), + scout => sov(congr_cl43_wE_offset to congr_cl43_wE_offset + congr_cl43_wE_d'length-1), + din => congr_cl43_wE_d, + dout => congr_cl43_wE_q); +congr_cl43_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl43_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl43_wF_offset to congr_cl43_wF_offset + congr_cl43_wF_d'length-1), + scout => sov(congr_cl43_wF_offset to congr_cl43_wF_offset + congr_cl43_wF_d'length-1), + din => congr_cl43_wF_d, + dout => congr_cl43_wF_q); +congr_cl43_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl43_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl43_wG_offset to congr_cl43_wG_offset + congr_cl43_wG_d'length-1), + scout => sov(congr_cl43_wG_offset to congr_cl43_wG_offset + congr_cl43_wG_d'length-1), + din => congr_cl43_wG_d, + dout => congr_cl43_wG_q); +congr_cl43_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl43_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl43_wH_offset to congr_cl43_wH_offset + congr_cl43_wH_d'length-1), + scout => sov(congr_cl43_wH_offset to congr_cl43_wH_offset + congr_cl43_wH_d'length-1), + din => congr_cl43_wH_d, + dout => congr_cl43_wH_q); +congr_cl44_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl44_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl44_wA_offset to congr_cl44_wA_offset + congr_cl44_wA_d'length-1), + scout => sov(congr_cl44_wA_offset to congr_cl44_wA_offset + congr_cl44_wA_d'length-1), + din => congr_cl44_wA_d, + dout => congr_cl44_wA_q); +congr_cl44_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl44_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl44_wB_offset to congr_cl44_wB_offset + congr_cl44_wB_d'length-1), + scout => sov(congr_cl44_wB_offset to congr_cl44_wB_offset + congr_cl44_wB_d'length-1), + din => congr_cl44_wB_d, + dout => congr_cl44_wB_q); +congr_cl44_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl44_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl44_wC_offset to congr_cl44_wC_offset + congr_cl44_wC_d'length-1), + scout => sov(congr_cl44_wC_offset to congr_cl44_wC_offset + congr_cl44_wC_d'length-1), + din => congr_cl44_wC_d, + dout => congr_cl44_wC_q); +congr_cl44_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl44_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl44_wD_offset to congr_cl44_wD_offset + congr_cl44_wD_d'length-1), + scout => sov(congr_cl44_wD_offset to congr_cl44_wD_offset + congr_cl44_wD_d'length-1), + din => congr_cl44_wD_d, + dout => congr_cl44_wD_q); +congr_cl44_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl44_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl44_wE_offset to congr_cl44_wE_offset + congr_cl44_wE_d'length-1), + scout => sov(congr_cl44_wE_offset to congr_cl44_wE_offset + congr_cl44_wE_d'length-1), + din => congr_cl44_wE_d, + dout => congr_cl44_wE_q); +congr_cl44_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl44_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl44_wF_offset to congr_cl44_wF_offset + congr_cl44_wF_d'length-1), + scout => sov(congr_cl44_wF_offset to congr_cl44_wF_offset + congr_cl44_wF_d'length-1), + din => congr_cl44_wF_d, + dout => congr_cl44_wF_q); +congr_cl44_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl44_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl44_wG_offset to congr_cl44_wG_offset + congr_cl44_wG_d'length-1), + scout => sov(congr_cl44_wG_offset to congr_cl44_wG_offset + congr_cl44_wG_d'length-1), + din => congr_cl44_wG_d, + dout => congr_cl44_wG_q); +congr_cl44_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl44_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl44_wH_offset to congr_cl44_wH_offset + congr_cl44_wH_d'length-1), + scout => sov(congr_cl44_wH_offset to congr_cl44_wH_offset + congr_cl44_wH_d'length-1), + din => congr_cl44_wH_d, + dout => congr_cl44_wH_q); +congr_cl45_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl45_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl45_wA_offset to congr_cl45_wA_offset + congr_cl45_wA_d'length-1), + scout => sov(congr_cl45_wA_offset to congr_cl45_wA_offset + congr_cl45_wA_d'length-1), + din => congr_cl45_wA_d, + dout => congr_cl45_wA_q); +congr_cl45_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl45_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl45_wB_offset to congr_cl45_wB_offset + congr_cl45_wB_d'length-1), + scout => sov(congr_cl45_wB_offset to congr_cl45_wB_offset + congr_cl45_wB_d'length-1), + din => congr_cl45_wB_d, + dout => congr_cl45_wB_q); +congr_cl45_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl45_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl45_wC_offset to congr_cl45_wC_offset + congr_cl45_wC_d'length-1), + scout => sov(congr_cl45_wC_offset to congr_cl45_wC_offset + congr_cl45_wC_d'length-1), + din => congr_cl45_wC_d, + dout => congr_cl45_wC_q); +congr_cl45_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl45_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl45_wD_offset to congr_cl45_wD_offset + congr_cl45_wD_d'length-1), + scout => sov(congr_cl45_wD_offset to congr_cl45_wD_offset + congr_cl45_wD_d'length-1), + din => congr_cl45_wD_d, + dout => congr_cl45_wD_q); +congr_cl45_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl45_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl45_wE_offset to congr_cl45_wE_offset + congr_cl45_wE_d'length-1), + scout => sov(congr_cl45_wE_offset to congr_cl45_wE_offset + congr_cl45_wE_d'length-1), + din => congr_cl45_wE_d, + dout => congr_cl45_wE_q); +congr_cl45_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl45_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl45_wF_offset to congr_cl45_wF_offset + congr_cl45_wF_d'length-1), + scout => sov(congr_cl45_wF_offset to congr_cl45_wF_offset + congr_cl45_wF_d'length-1), + din => congr_cl45_wF_d, + dout => congr_cl45_wF_q); +congr_cl45_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl45_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl45_wG_offset to congr_cl45_wG_offset + congr_cl45_wG_d'length-1), + scout => sov(congr_cl45_wG_offset to congr_cl45_wG_offset + congr_cl45_wG_d'length-1), + din => congr_cl45_wG_d, + dout => congr_cl45_wG_q); +congr_cl45_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl45_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl45_wH_offset to congr_cl45_wH_offset + congr_cl45_wH_d'length-1), + scout => sov(congr_cl45_wH_offset to congr_cl45_wH_offset + congr_cl45_wH_d'length-1), + din => congr_cl45_wH_d, + dout => congr_cl45_wH_q); +congr_cl46_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl46_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl46_wA_offset to congr_cl46_wA_offset + congr_cl46_wA_d'length-1), + scout => sov(congr_cl46_wA_offset to congr_cl46_wA_offset + congr_cl46_wA_d'length-1), + din => congr_cl46_wA_d, + dout => congr_cl46_wA_q); +congr_cl46_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl46_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl46_wB_offset to congr_cl46_wB_offset + congr_cl46_wB_d'length-1), + scout => sov(congr_cl46_wB_offset to congr_cl46_wB_offset + congr_cl46_wB_d'length-1), + din => congr_cl46_wB_d, + dout => congr_cl46_wB_q); +congr_cl46_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl46_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl46_wC_offset to congr_cl46_wC_offset + congr_cl46_wC_d'length-1), + scout => sov(congr_cl46_wC_offset to congr_cl46_wC_offset + congr_cl46_wC_d'length-1), + din => congr_cl46_wC_d, + dout => congr_cl46_wC_q); +congr_cl46_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl46_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl46_wD_offset to congr_cl46_wD_offset + congr_cl46_wD_d'length-1), + scout => sov(congr_cl46_wD_offset to congr_cl46_wD_offset + congr_cl46_wD_d'length-1), + din => congr_cl46_wD_d, + dout => congr_cl46_wD_q); +congr_cl46_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl46_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl46_wE_offset to congr_cl46_wE_offset + congr_cl46_wE_d'length-1), + scout => sov(congr_cl46_wE_offset to congr_cl46_wE_offset + congr_cl46_wE_d'length-1), + din => congr_cl46_wE_d, + dout => congr_cl46_wE_q); +congr_cl46_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl46_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl46_wF_offset to congr_cl46_wF_offset + congr_cl46_wF_d'length-1), + scout => sov(congr_cl46_wF_offset to congr_cl46_wF_offset + congr_cl46_wF_d'length-1), + din => congr_cl46_wF_d, + dout => congr_cl46_wF_q); +congr_cl46_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl46_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl46_wG_offset to congr_cl46_wG_offset + congr_cl46_wG_d'length-1), + scout => sov(congr_cl46_wG_offset to congr_cl46_wG_offset + congr_cl46_wG_d'length-1), + din => congr_cl46_wG_d, + dout => congr_cl46_wG_q); +congr_cl46_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl46_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl46_wH_offset to congr_cl46_wH_offset + congr_cl46_wH_d'length-1), + scout => sov(congr_cl46_wH_offset to congr_cl46_wH_offset + congr_cl46_wH_d'length-1), + din => congr_cl46_wH_d, + dout => congr_cl46_wH_q); +congr_cl47_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl47_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl47_wA_offset to congr_cl47_wA_offset + congr_cl47_wA_d'length-1), + scout => sov(congr_cl47_wA_offset to congr_cl47_wA_offset + congr_cl47_wA_d'length-1), + din => congr_cl47_wA_d, + dout => congr_cl47_wA_q); +congr_cl47_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl47_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl47_wB_offset to congr_cl47_wB_offset + congr_cl47_wB_d'length-1), + scout => sov(congr_cl47_wB_offset to congr_cl47_wB_offset + congr_cl47_wB_d'length-1), + din => congr_cl47_wB_d, + dout => congr_cl47_wB_q); +congr_cl47_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl47_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl47_wC_offset to congr_cl47_wC_offset + congr_cl47_wC_d'length-1), + scout => sov(congr_cl47_wC_offset to congr_cl47_wC_offset + congr_cl47_wC_d'length-1), + din => congr_cl47_wC_d, + dout => congr_cl47_wC_q); +congr_cl47_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl47_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl47_wD_offset to congr_cl47_wD_offset + congr_cl47_wD_d'length-1), + scout => sov(congr_cl47_wD_offset to congr_cl47_wD_offset + congr_cl47_wD_d'length-1), + din => congr_cl47_wD_d, + dout => congr_cl47_wD_q); +congr_cl47_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl47_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl47_wE_offset to congr_cl47_wE_offset + congr_cl47_wE_d'length-1), + scout => sov(congr_cl47_wE_offset to congr_cl47_wE_offset + congr_cl47_wE_d'length-1), + din => congr_cl47_wE_d, + dout => congr_cl47_wE_q); +congr_cl47_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl47_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl47_wF_offset to congr_cl47_wF_offset + congr_cl47_wF_d'length-1), + scout => sov(congr_cl47_wF_offset to congr_cl47_wF_offset + congr_cl47_wF_d'length-1), + din => congr_cl47_wF_d, + dout => congr_cl47_wF_q); +congr_cl47_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl47_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl47_wG_offset to congr_cl47_wG_offset + congr_cl47_wG_d'length-1), + scout => sov(congr_cl47_wG_offset to congr_cl47_wG_offset + congr_cl47_wG_d'length-1), + din => congr_cl47_wG_d, + dout => congr_cl47_wG_q); +congr_cl47_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl47_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl47_wH_offset to congr_cl47_wH_offset + congr_cl47_wH_d'length-1), + scout => sov(congr_cl47_wH_offset to congr_cl47_wH_offset + congr_cl47_wH_d'length-1), + din => congr_cl47_wH_d, + dout => congr_cl47_wH_q); +congr_cl48_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl48_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl48_wA_offset to congr_cl48_wA_offset + congr_cl48_wA_d'length-1), + scout => sov(congr_cl48_wA_offset to congr_cl48_wA_offset + congr_cl48_wA_d'length-1), + din => congr_cl48_wA_d, + dout => congr_cl48_wA_q); +congr_cl48_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl48_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl48_wB_offset to congr_cl48_wB_offset + congr_cl48_wB_d'length-1), + scout => sov(congr_cl48_wB_offset to congr_cl48_wB_offset + congr_cl48_wB_d'length-1), + din => congr_cl48_wB_d, + dout => congr_cl48_wB_q); +congr_cl48_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl48_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl48_wC_offset to congr_cl48_wC_offset + congr_cl48_wC_d'length-1), + scout => sov(congr_cl48_wC_offset to congr_cl48_wC_offset + congr_cl48_wC_d'length-1), + din => congr_cl48_wC_d, + dout => congr_cl48_wC_q); +congr_cl48_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl48_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl48_wD_offset to congr_cl48_wD_offset + congr_cl48_wD_d'length-1), + scout => sov(congr_cl48_wD_offset to congr_cl48_wD_offset + congr_cl48_wD_d'length-1), + din => congr_cl48_wD_d, + dout => congr_cl48_wD_q); +congr_cl48_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl48_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl48_wE_offset to congr_cl48_wE_offset + congr_cl48_wE_d'length-1), + scout => sov(congr_cl48_wE_offset to congr_cl48_wE_offset + congr_cl48_wE_d'length-1), + din => congr_cl48_wE_d, + dout => congr_cl48_wE_q); +congr_cl48_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl48_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl48_wF_offset to congr_cl48_wF_offset + congr_cl48_wF_d'length-1), + scout => sov(congr_cl48_wF_offset to congr_cl48_wF_offset + congr_cl48_wF_d'length-1), + din => congr_cl48_wF_d, + dout => congr_cl48_wF_q); +congr_cl48_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl48_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl48_wG_offset to congr_cl48_wG_offset + congr_cl48_wG_d'length-1), + scout => sov(congr_cl48_wG_offset to congr_cl48_wG_offset + congr_cl48_wG_d'length-1), + din => congr_cl48_wG_d, + dout => congr_cl48_wG_q); +congr_cl48_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl48_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl48_wH_offset to congr_cl48_wH_offset + congr_cl48_wH_d'length-1), + scout => sov(congr_cl48_wH_offset to congr_cl48_wH_offset + congr_cl48_wH_d'length-1), + din => congr_cl48_wH_d, + dout => congr_cl48_wH_q); +congr_cl49_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl49_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl49_wA_offset to congr_cl49_wA_offset + congr_cl49_wA_d'length-1), + scout => sov(congr_cl49_wA_offset to congr_cl49_wA_offset + congr_cl49_wA_d'length-1), + din => congr_cl49_wA_d, + dout => congr_cl49_wA_q); +congr_cl49_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl49_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl49_wB_offset to congr_cl49_wB_offset + congr_cl49_wB_d'length-1), + scout => sov(congr_cl49_wB_offset to congr_cl49_wB_offset + congr_cl49_wB_d'length-1), + din => congr_cl49_wB_d, + dout => congr_cl49_wB_q); +congr_cl49_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl49_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl49_wC_offset to congr_cl49_wC_offset + congr_cl49_wC_d'length-1), + scout => sov(congr_cl49_wC_offset to congr_cl49_wC_offset + congr_cl49_wC_d'length-1), + din => congr_cl49_wC_d, + dout => congr_cl49_wC_q); +congr_cl49_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl49_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl49_wD_offset to congr_cl49_wD_offset + congr_cl49_wD_d'length-1), + scout => sov(congr_cl49_wD_offset to congr_cl49_wD_offset + congr_cl49_wD_d'length-1), + din => congr_cl49_wD_d, + dout => congr_cl49_wD_q); +congr_cl49_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl49_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl49_wE_offset to congr_cl49_wE_offset + congr_cl49_wE_d'length-1), + scout => sov(congr_cl49_wE_offset to congr_cl49_wE_offset + congr_cl49_wE_d'length-1), + din => congr_cl49_wE_d, + dout => congr_cl49_wE_q); +congr_cl49_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl49_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl49_wF_offset to congr_cl49_wF_offset + congr_cl49_wF_d'length-1), + scout => sov(congr_cl49_wF_offset to congr_cl49_wF_offset + congr_cl49_wF_d'length-1), + din => congr_cl49_wF_d, + dout => congr_cl49_wF_q); +congr_cl49_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl49_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl49_wG_offset to congr_cl49_wG_offset + congr_cl49_wG_d'length-1), + scout => sov(congr_cl49_wG_offset to congr_cl49_wG_offset + congr_cl49_wG_d'length-1), + din => congr_cl49_wG_d, + dout => congr_cl49_wG_q); +congr_cl49_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl49_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl49_wH_offset to congr_cl49_wH_offset + congr_cl49_wH_d'length-1), + scout => sov(congr_cl49_wH_offset to congr_cl49_wH_offset + congr_cl49_wH_d'length-1), + din => congr_cl49_wH_d, + dout => congr_cl49_wH_q); +congr_cl50_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl50_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl50_wA_offset to congr_cl50_wA_offset + congr_cl50_wA_d'length-1), + scout => sov(congr_cl50_wA_offset to congr_cl50_wA_offset + congr_cl50_wA_d'length-1), + din => congr_cl50_wA_d, + dout => congr_cl50_wA_q); +congr_cl50_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl50_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl50_wB_offset to congr_cl50_wB_offset + congr_cl50_wB_d'length-1), + scout => sov(congr_cl50_wB_offset to congr_cl50_wB_offset + congr_cl50_wB_d'length-1), + din => congr_cl50_wB_d, + dout => congr_cl50_wB_q); +congr_cl50_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl50_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl50_wC_offset to congr_cl50_wC_offset + congr_cl50_wC_d'length-1), + scout => sov(congr_cl50_wC_offset to congr_cl50_wC_offset + congr_cl50_wC_d'length-1), + din => congr_cl50_wC_d, + dout => congr_cl50_wC_q); +congr_cl50_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl50_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl50_wD_offset to congr_cl50_wD_offset + congr_cl50_wD_d'length-1), + scout => sov(congr_cl50_wD_offset to congr_cl50_wD_offset + congr_cl50_wD_d'length-1), + din => congr_cl50_wD_d, + dout => congr_cl50_wD_q); +congr_cl50_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl50_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl50_wE_offset to congr_cl50_wE_offset + congr_cl50_wE_d'length-1), + scout => sov(congr_cl50_wE_offset to congr_cl50_wE_offset + congr_cl50_wE_d'length-1), + din => congr_cl50_wE_d, + dout => congr_cl50_wE_q); +congr_cl50_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl50_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl50_wF_offset to congr_cl50_wF_offset + congr_cl50_wF_d'length-1), + scout => sov(congr_cl50_wF_offset to congr_cl50_wF_offset + congr_cl50_wF_d'length-1), + din => congr_cl50_wF_d, + dout => congr_cl50_wF_q); +congr_cl50_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl50_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl50_wG_offset to congr_cl50_wG_offset + congr_cl50_wG_d'length-1), + scout => sov(congr_cl50_wG_offset to congr_cl50_wG_offset + congr_cl50_wG_d'length-1), + din => congr_cl50_wG_d, + dout => congr_cl50_wG_q); +congr_cl50_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl50_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl50_wH_offset to congr_cl50_wH_offset + congr_cl50_wH_d'length-1), + scout => sov(congr_cl50_wH_offset to congr_cl50_wH_offset + congr_cl50_wH_d'length-1), + din => congr_cl50_wH_d, + dout => congr_cl50_wH_q); +congr_cl51_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl51_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl51_wA_offset to congr_cl51_wA_offset + congr_cl51_wA_d'length-1), + scout => sov(congr_cl51_wA_offset to congr_cl51_wA_offset + congr_cl51_wA_d'length-1), + din => congr_cl51_wA_d, + dout => congr_cl51_wA_q); +congr_cl51_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl51_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl51_wB_offset to congr_cl51_wB_offset + congr_cl51_wB_d'length-1), + scout => sov(congr_cl51_wB_offset to congr_cl51_wB_offset + congr_cl51_wB_d'length-1), + din => congr_cl51_wB_d, + dout => congr_cl51_wB_q); +congr_cl51_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl51_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl51_wC_offset to congr_cl51_wC_offset + congr_cl51_wC_d'length-1), + scout => sov(congr_cl51_wC_offset to congr_cl51_wC_offset + congr_cl51_wC_d'length-1), + din => congr_cl51_wC_d, + dout => congr_cl51_wC_q); +congr_cl51_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl51_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl51_wD_offset to congr_cl51_wD_offset + congr_cl51_wD_d'length-1), + scout => sov(congr_cl51_wD_offset to congr_cl51_wD_offset + congr_cl51_wD_d'length-1), + din => congr_cl51_wD_d, + dout => congr_cl51_wD_q); +congr_cl51_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl51_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl51_wE_offset to congr_cl51_wE_offset + congr_cl51_wE_d'length-1), + scout => sov(congr_cl51_wE_offset to congr_cl51_wE_offset + congr_cl51_wE_d'length-1), + din => congr_cl51_wE_d, + dout => congr_cl51_wE_q); +congr_cl51_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl51_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl51_wF_offset to congr_cl51_wF_offset + congr_cl51_wF_d'length-1), + scout => sov(congr_cl51_wF_offset to congr_cl51_wF_offset + congr_cl51_wF_d'length-1), + din => congr_cl51_wF_d, + dout => congr_cl51_wF_q); +congr_cl51_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl51_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl51_wG_offset to congr_cl51_wG_offset + congr_cl51_wG_d'length-1), + scout => sov(congr_cl51_wG_offset to congr_cl51_wG_offset + congr_cl51_wG_d'length-1), + din => congr_cl51_wG_d, + dout => congr_cl51_wG_q); +congr_cl51_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl51_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl51_wH_offset to congr_cl51_wH_offset + congr_cl51_wH_d'length-1), + scout => sov(congr_cl51_wH_offset to congr_cl51_wH_offset + congr_cl51_wH_d'length-1), + din => congr_cl51_wH_d, + dout => congr_cl51_wH_q); +congr_cl52_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl52_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl52_wA_offset to congr_cl52_wA_offset + congr_cl52_wA_d'length-1), + scout => sov(congr_cl52_wA_offset to congr_cl52_wA_offset + congr_cl52_wA_d'length-1), + din => congr_cl52_wA_d, + dout => congr_cl52_wA_q); +congr_cl52_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl52_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl52_wB_offset to congr_cl52_wB_offset + congr_cl52_wB_d'length-1), + scout => sov(congr_cl52_wB_offset to congr_cl52_wB_offset + congr_cl52_wB_d'length-1), + din => congr_cl52_wB_d, + dout => congr_cl52_wB_q); +congr_cl52_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl52_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl52_wC_offset to congr_cl52_wC_offset + congr_cl52_wC_d'length-1), + scout => sov(congr_cl52_wC_offset to congr_cl52_wC_offset + congr_cl52_wC_d'length-1), + din => congr_cl52_wC_d, + dout => congr_cl52_wC_q); +congr_cl52_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl52_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl52_wD_offset to congr_cl52_wD_offset + congr_cl52_wD_d'length-1), + scout => sov(congr_cl52_wD_offset to congr_cl52_wD_offset + congr_cl52_wD_d'length-1), + din => congr_cl52_wD_d, + dout => congr_cl52_wD_q); +congr_cl52_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl52_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl52_wE_offset to congr_cl52_wE_offset + congr_cl52_wE_d'length-1), + scout => sov(congr_cl52_wE_offset to congr_cl52_wE_offset + congr_cl52_wE_d'length-1), + din => congr_cl52_wE_d, + dout => congr_cl52_wE_q); +congr_cl52_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl52_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl52_wF_offset to congr_cl52_wF_offset + congr_cl52_wF_d'length-1), + scout => sov(congr_cl52_wF_offset to congr_cl52_wF_offset + congr_cl52_wF_d'length-1), + din => congr_cl52_wF_d, + dout => congr_cl52_wF_q); +congr_cl52_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl52_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl52_wG_offset to congr_cl52_wG_offset + congr_cl52_wG_d'length-1), + scout => sov(congr_cl52_wG_offset to congr_cl52_wG_offset + congr_cl52_wG_d'length-1), + din => congr_cl52_wG_d, + dout => congr_cl52_wG_q); +congr_cl52_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl52_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl52_wH_offset to congr_cl52_wH_offset + congr_cl52_wH_d'length-1), + scout => sov(congr_cl52_wH_offset to congr_cl52_wH_offset + congr_cl52_wH_d'length-1), + din => congr_cl52_wH_d, + dout => congr_cl52_wH_q); +congr_cl53_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl53_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl53_wA_offset to congr_cl53_wA_offset + congr_cl53_wA_d'length-1), + scout => sov(congr_cl53_wA_offset to congr_cl53_wA_offset + congr_cl53_wA_d'length-1), + din => congr_cl53_wA_d, + dout => congr_cl53_wA_q); +congr_cl53_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl53_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl53_wB_offset to congr_cl53_wB_offset + congr_cl53_wB_d'length-1), + scout => sov(congr_cl53_wB_offset to congr_cl53_wB_offset + congr_cl53_wB_d'length-1), + din => congr_cl53_wB_d, + dout => congr_cl53_wB_q); +congr_cl53_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl53_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl53_wC_offset to congr_cl53_wC_offset + congr_cl53_wC_d'length-1), + scout => sov(congr_cl53_wC_offset to congr_cl53_wC_offset + congr_cl53_wC_d'length-1), + din => congr_cl53_wC_d, + dout => congr_cl53_wC_q); +congr_cl53_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl53_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl53_wD_offset to congr_cl53_wD_offset + congr_cl53_wD_d'length-1), + scout => sov(congr_cl53_wD_offset to congr_cl53_wD_offset + congr_cl53_wD_d'length-1), + din => congr_cl53_wD_d, + dout => congr_cl53_wD_q); +congr_cl53_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl53_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl53_wE_offset to congr_cl53_wE_offset + congr_cl53_wE_d'length-1), + scout => sov(congr_cl53_wE_offset to congr_cl53_wE_offset + congr_cl53_wE_d'length-1), + din => congr_cl53_wE_d, + dout => congr_cl53_wE_q); +congr_cl53_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl53_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl53_wF_offset to congr_cl53_wF_offset + congr_cl53_wF_d'length-1), + scout => sov(congr_cl53_wF_offset to congr_cl53_wF_offset + congr_cl53_wF_d'length-1), + din => congr_cl53_wF_d, + dout => congr_cl53_wF_q); +congr_cl53_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl53_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl53_wG_offset to congr_cl53_wG_offset + congr_cl53_wG_d'length-1), + scout => sov(congr_cl53_wG_offset to congr_cl53_wG_offset + congr_cl53_wG_d'length-1), + din => congr_cl53_wG_d, + dout => congr_cl53_wG_q); +congr_cl53_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl53_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl53_wH_offset to congr_cl53_wH_offset + congr_cl53_wH_d'length-1), + scout => sov(congr_cl53_wH_offset to congr_cl53_wH_offset + congr_cl53_wH_d'length-1), + din => congr_cl53_wH_d, + dout => congr_cl53_wH_q); +congr_cl54_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl54_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl54_wA_offset to congr_cl54_wA_offset + congr_cl54_wA_d'length-1), + scout => sov(congr_cl54_wA_offset to congr_cl54_wA_offset + congr_cl54_wA_d'length-1), + din => congr_cl54_wA_d, + dout => congr_cl54_wA_q); +congr_cl54_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl54_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl54_wB_offset to congr_cl54_wB_offset + congr_cl54_wB_d'length-1), + scout => sov(congr_cl54_wB_offset to congr_cl54_wB_offset + congr_cl54_wB_d'length-1), + din => congr_cl54_wB_d, + dout => congr_cl54_wB_q); +congr_cl54_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl54_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl54_wC_offset to congr_cl54_wC_offset + congr_cl54_wC_d'length-1), + scout => sov(congr_cl54_wC_offset to congr_cl54_wC_offset + congr_cl54_wC_d'length-1), + din => congr_cl54_wC_d, + dout => congr_cl54_wC_q); +congr_cl54_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl54_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl54_wD_offset to congr_cl54_wD_offset + congr_cl54_wD_d'length-1), + scout => sov(congr_cl54_wD_offset to congr_cl54_wD_offset + congr_cl54_wD_d'length-1), + din => congr_cl54_wD_d, + dout => congr_cl54_wD_q); +congr_cl54_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl54_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl54_wE_offset to congr_cl54_wE_offset + congr_cl54_wE_d'length-1), + scout => sov(congr_cl54_wE_offset to congr_cl54_wE_offset + congr_cl54_wE_d'length-1), + din => congr_cl54_wE_d, + dout => congr_cl54_wE_q); +congr_cl54_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl54_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl54_wF_offset to congr_cl54_wF_offset + congr_cl54_wF_d'length-1), + scout => sov(congr_cl54_wF_offset to congr_cl54_wF_offset + congr_cl54_wF_d'length-1), + din => congr_cl54_wF_d, + dout => congr_cl54_wF_q); +congr_cl54_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl54_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl54_wG_offset to congr_cl54_wG_offset + congr_cl54_wG_d'length-1), + scout => sov(congr_cl54_wG_offset to congr_cl54_wG_offset + congr_cl54_wG_d'length-1), + din => congr_cl54_wG_d, + dout => congr_cl54_wG_q); +congr_cl54_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl54_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl54_wH_offset to congr_cl54_wH_offset + congr_cl54_wH_d'length-1), + scout => sov(congr_cl54_wH_offset to congr_cl54_wH_offset + congr_cl54_wH_d'length-1), + din => congr_cl54_wH_d, + dout => congr_cl54_wH_q); +congr_cl55_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl55_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl55_wA_offset to congr_cl55_wA_offset + congr_cl55_wA_d'length-1), + scout => sov(congr_cl55_wA_offset to congr_cl55_wA_offset + congr_cl55_wA_d'length-1), + din => congr_cl55_wA_d, + dout => congr_cl55_wA_q); +congr_cl55_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl55_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl55_wB_offset to congr_cl55_wB_offset + congr_cl55_wB_d'length-1), + scout => sov(congr_cl55_wB_offset to congr_cl55_wB_offset + congr_cl55_wB_d'length-1), + din => congr_cl55_wB_d, + dout => congr_cl55_wB_q); +congr_cl55_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl55_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl55_wC_offset to congr_cl55_wC_offset + congr_cl55_wC_d'length-1), + scout => sov(congr_cl55_wC_offset to congr_cl55_wC_offset + congr_cl55_wC_d'length-1), + din => congr_cl55_wC_d, + dout => congr_cl55_wC_q); +congr_cl55_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl55_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl55_wD_offset to congr_cl55_wD_offset + congr_cl55_wD_d'length-1), + scout => sov(congr_cl55_wD_offset to congr_cl55_wD_offset + congr_cl55_wD_d'length-1), + din => congr_cl55_wD_d, + dout => congr_cl55_wD_q); +congr_cl55_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl55_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl55_wE_offset to congr_cl55_wE_offset + congr_cl55_wE_d'length-1), + scout => sov(congr_cl55_wE_offset to congr_cl55_wE_offset + congr_cl55_wE_d'length-1), + din => congr_cl55_wE_d, + dout => congr_cl55_wE_q); +congr_cl55_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl55_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl55_wF_offset to congr_cl55_wF_offset + congr_cl55_wF_d'length-1), + scout => sov(congr_cl55_wF_offset to congr_cl55_wF_offset + congr_cl55_wF_d'length-1), + din => congr_cl55_wF_d, + dout => congr_cl55_wF_q); +congr_cl55_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl55_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl55_wG_offset to congr_cl55_wG_offset + congr_cl55_wG_d'length-1), + scout => sov(congr_cl55_wG_offset to congr_cl55_wG_offset + congr_cl55_wG_d'length-1), + din => congr_cl55_wG_d, + dout => congr_cl55_wG_q); +congr_cl55_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl55_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl55_wH_offset to congr_cl55_wH_offset + congr_cl55_wH_d'length-1), + scout => sov(congr_cl55_wH_offset to congr_cl55_wH_offset + congr_cl55_wH_d'length-1), + din => congr_cl55_wH_d, + dout => congr_cl55_wH_q); +congr_cl56_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl56_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl56_wA_offset to congr_cl56_wA_offset + congr_cl56_wA_d'length-1), + scout => sov(congr_cl56_wA_offset to congr_cl56_wA_offset + congr_cl56_wA_d'length-1), + din => congr_cl56_wA_d, + dout => congr_cl56_wA_q); +congr_cl56_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl56_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl56_wB_offset to congr_cl56_wB_offset + congr_cl56_wB_d'length-1), + scout => sov(congr_cl56_wB_offset to congr_cl56_wB_offset + congr_cl56_wB_d'length-1), + din => congr_cl56_wB_d, + dout => congr_cl56_wB_q); +congr_cl56_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl56_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl56_wC_offset to congr_cl56_wC_offset + congr_cl56_wC_d'length-1), + scout => sov(congr_cl56_wC_offset to congr_cl56_wC_offset + congr_cl56_wC_d'length-1), + din => congr_cl56_wC_d, + dout => congr_cl56_wC_q); +congr_cl56_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl56_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl56_wD_offset to congr_cl56_wD_offset + congr_cl56_wD_d'length-1), + scout => sov(congr_cl56_wD_offset to congr_cl56_wD_offset + congr_cl56_wD_d'length-1), + din => congr_cl56_wD_d, + dout => congr_cl56_wD_q); +congr_cl56_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl56_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl56_wE_offset to congr_cl56_wE_offset + congr_cl56_wE_d'length-1), + scout => sov(congr_cl56_wE_offset to congr_cl56_wE_offset + congr_cl56_wE_d'length-1), + din => congr_cl56_wE_d, + dout => congr_cl56_wE_q); +congr_cl56_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl56_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl56_wF_offset to congr_cl56_wF_offset + congr_cl56_wF_d'length-1), + scout => sov(congr_cl56_wF_offset to congr_cl56_wF_offset + congr_cl56_wF_d'length-1), + din => congr_cl56_wF_d, + dout => congr_cl56_wF_q); +congr_cl56_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl56_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl56_wG_offset to congr_cl56_wG_offset + congr_cl56_wG_d'length-1), + scout => sov(congr_cl56_wG_offset to congr_cl56_wG_offset + congr_cl56_wG_d'length-1), + din => congr_cl56_wG_d, + dout => congr_cl56_wG_q); +congr_cl56_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl56_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl56_wH_offset to congr_cl56_wH_offset + congr_cl56_wH_d'length-1), + scout => sov(congr_cl56_wH_offset to congr_cl56_wH_offset + congr_cl56_wH_d'length-1), + din => congr_cl56_wH_d, + dout => congr_cl56_wH_q); +congr_cl57_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl57_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl57_wA_offset to congr_cl57_wA_offset + congr_cl57_wA_d'length-1), + scout => sov(congr_cl57_wA_offset to congr_cl57_wA_offset + congr_cl57_wA_d'length-1), + din => congr_cl57_wA_d, + dout => congr_cl57_wA_q); +congr_cl57_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl57_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl57_wB_offset to congr_cl57_wB_offset + congr_cl57_wB_d'length-1), + scout => sov(congr_cl57_wB_offset to congr_cl57_wB_offset + congr_cl57_wB_d'length-1), + din => congr_cl57_wB_d, + dout => congr_cl57_wB_q); +congr_cl57_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl57_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl57_wC_offset to congr_cl57_wC_offset + congr_cl57_wC_d'length-1), + scout => sov(congr_cl57_wC_offset to congr_cl57_wC_offset + congr_cl57_wC_d'length-1), + din => congr_cl57_wC_d, + dout => congr_cl57_wC_q); +congr_cl57_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl57_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl57_wD_offset to congr_cl57_wD_offset + congr_cl57_wD_d'length-1), + scout => sov(congr_cl57_wD_offset to congr_cl57_wD_offset + congr_cl57_wD_d'length-1), + din => congr_cl57_wD_d, + dout => congr_cl57_wD_q); +congr_cl57_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl57_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl57_wE_offset to congr_cl57_wE_offset + congr_cl57_wE_d'length-1), + scout => sov(congr_cl57_wE_offset to congr_cl57_wE_offset + congr_cl57_wE_d'length-1), + din => congr_cl57_wE_d, + dout => congr_cl57_wE_q); +congr_cl57_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl57_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl57_wF_offset to congr_cl57_wF_offset + congr_cl57_wF_d'length-1), + scout => sov(congr_cl57_wF_offset to congr_cl57_wF_offset + congr_cl57_wF_d'length-1), + din => congr_cl57_wF_d, + dout => congr_cl57_wF_q); +congr_cl57_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl57_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl57_wG_offset to congr_cl57_wG_offset + congr_cl57_wG_d'length-1), + scout => sov(congr_cl57_wG_offset to congr_cl57_wG_offset + congr_cl57_wG_d'length-1), + din => congr_cl57_wG_d, + dout => congr_cl57_wG_q); +congr_cl57_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl57_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl57_wH_offset to congr_cl57_wH_offset + congr_cl57_wH_d'length-1), + scout => sov(congr_cl57_wH_offset to congr_cl57_wH_offset + congr_cl57_wH_d'length-1), + din => congr_cl57_wH_d, + dout => congr_cl57_wH_q); +congr_cl58_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl58_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl58_wA_offset to congr_cl58_wA_offset + congr_cl58_wA_d'length-1), + scout => sov(congr_cl58_wA_offset to congr_cl58_wA_offset + congr_cl58_wA_d'length-1), + din => congr_cl58_wA_d, + dout => congr_cl58_wA_q); +congr_cl58_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl58_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl58_wB_offset to congr_cl58_wB_offset + congr_cl58_wB_d'length-1), + scout => sov(congr_cl58_wB_offset to congr_cl58_wB_offset + congr_cl58_wB_d'length-1), + din => congr_cl58_wB_d, + dout => congr_cl58_wB_q); +congr_cl58_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl58_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl58_wC_offset to congr_cl58_wC_offset + congr_cl58_wC_d'length-1), + scout => sov(congr_cl58_wC_offset to congr_cl58_wC_offset + congr_cl58_wC_d'length-1), + din => congr_cl58_wC_d, + dout => congr_cl58_wC_q); +congr_cl58_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl58_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl58_wD_offset to congr_cl58_wD_offset + congr_cl58_wD_d'length-1), + scout => sov(congr_cl58_wD_offset to congr_cl58_wD_offset + congr_cl58_wD_d'length-1), + din => congr_cl58_wD_d, + dout => congr_cl58_wD_q); +congr_cl58_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl58_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl58_wE_offset to congr_cl58_wE_offset + congr_cl58_wE_d'length-1), + scout => sov(congr_cl58_wE_offset to congr_cl58_wE_offset + congr_cl58_wE_d'length-1), + din => congr_cl58_wE_d, + dout => congr_cl58_wE_q); +congr_cl58_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl58_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl58_wF_offset to congr_cl58_wF_offset + congr_cl58_wF_d'length-1), + scout => sov(congr_cl58_wF_offset to congr_cl58_wF_offset + congr_cl58_wF_d'length-1), + din => congr_cl58_wF_d, + dout => congr_cl58_wF_q); +congr_cl58_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl58_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl58_wG_offset to congr_cl58_wG_offset + congr_cl58_wG_d'length-1), + scout => sov(congr_cl58_wG_offset to congr_cl58_wG_offset + congr_cl58_wG_d'length-1), + din => congr_cl58_wG_d, + dout => congr_cl58_wG_q); +congr_cl58_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl58_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl58_wH_offset to congr_cl58_wH_offset + congr_cl58_wH_d'length-1), + scout => sov(congr_cl58_wH_offset to congr_cl58_wH_offset + congr_cl58_wH_d'length-1), + din => congr_cl58_wH_d, + dout => congr_cl58_wH_q); +congr_cl59_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl59_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl59_wA_offset to congr_cl59_wA_offset + congr_cl59_wA_d'length-1), + scout => sov(congr_cl59_wA_offset to congr_cl59_wA_offset + congr_cl59_wA_d'length-1), + din => congr_cl59_wA_d, + dout => congr_cl59_wA_q); +congr_cl59_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl59_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl59_wB_offset to congr_cl59_wB_offset + congr_cl59_wB_d'length-1), + scout => sov(congr_cl59_wB_offset to congr_cl59_wB_offset + congr_cl59_wB_d'length-1), + din => congr_cl59_wB_d, + dout => congr_cl59_wB_q); +congr_cl59_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl59_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl59_wC_offset to congr_cl59_wC_offset + congr_cl59_wC_d'length-1), + scout => sov(congr_cl59_wC_offset to congr_cl59_wC_offset + congr_cl59_wC_d'length-1), + din => congr_cl59_wC_d, + dout => congr_cl59_wC_q); +congr_cl59_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl59_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl59_wD_offset to congr_cl59_wD_offset + congr_cl59_wD_d'length-1), + scout => sov(congr_cl59_wD_offset to congr_cl59_wD_offset + congr_cl59_wD_d'length-1), + din => congr_cl59_wD_d, + dout => congr_cl59_wD_q); +congr_cl59_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl59_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl59_wE_offset to congr_cl59_wE_offset + congr_cl59_wE_d'length-1), + scout => sov(congr_cl59_wE_offset to congr_cl59_wE_offset + congr_cl59_wE_d'length-1), + din => congr_cl59_wE_d, + dout => congr_cl59_wE_q); +congr_cl59_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl59_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl59_wF_offset to congr_cl59_wF_offset + congr_cl59_wF_d'length-1), + scout => sov(congr_cl59_wF_offset to congr_cl59_wF_offset + congr_cl59_wF_d'length-1), + din => congr_cl59_wF_d, + dout => congr_cl59_wF_q); +congr_cl59_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl59_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl59_wG_offset to congr_cl59_wG_offset + congr_cl59_wG_d'length-1), + scout => sov(congr_cl59_wG_offset to congr_cl59_wG_offset + congr_cl59_wG_d'length-1), + din => congr_cl59_wG_d, + dout => congr_cl59_wG_q); +congr_cl59_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl59_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl59_wH_offset to congr_cl59_wH_offset + congr_cl59_wH_d'length-1), + scout => sov(congr_cl59_wH_offset to congr_cl59_wH_offset + congr_cl59_wH_d'length-1), + din => congr_cl59_wH_d, + dout => congr_cl59_wH_q); +congr_cl60_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl60_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl60_wA_offset to congr_cl60_wA_offset + congr_cl60_wA_d'length-1), + scout => sov(congr_cl60_wA_offset to congr_cl60_wA_offset + congr_cl60_wA_d'length-1), + din => congr_cl60_wA_d, + dout => congr_cl60_wA_q); +congr_cl60_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl60_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl60_wB_offset to congr_cl60_wB_offset + congr_cl60_wB_d'length-1), + scout => sov(congr_cl60_wB_offset to congr_cl60_wB_offset + congr_cl60_wB_d'length-1), + din => congr_cl60_wB_d, + dout => congr_cl60_wB_q); +congr_cl60_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl60_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl60_wC_offset to congr_cl60_wC_offset + congr_cl60_wC_d'length-1), + scout => sov(congr_cl60_wC_offset to congr_cl60_wC_offset + congr_cl60_wC_d'length-1), + din => congr_cl60_wC_d, + dout => congr_cl60_wC_q); +congr_cl60_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl60_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl60_wD_offset to congr_cl60_wD_offset + congr_cl60_wD_d'length-1), + scout => sov(congr_cl60_wD_offset to congr_cl60_wD_offset + congr_cl60_wD_d'length-1), + din => congr_cl60_wD_d, + dout => congr_cl60_wD_q); +congr_cl60_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl60_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl60_wE_offset to congr_cl60_wE_offset + congr_cl60_wE_d'length-1), + scout => sov(congr_cl60_wE_offset to congr_cl60_wE_offset + congr_cl60_wE_d'length-1), + din => congr_cl60_wE_d, + dout => congr_cl60_wE_q); +congr_cl60_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl60_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl60_wF_offset to congr_cl60_wF_offset + congr_cl60_wF_d'length-1), + scout => sov(congr_cl60_wF_offset to congr_cl60_wF_offset + congr_cl60_wF_d'length-1), + din => congr_cl60_wF_d, + dout => congr_cl60_wF_q); +congr_cl60_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl60_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl60_wG_offset to congr_cl60_wG_offset + congr_cl60_wG_d'length-1), + scout => sov(congr_cl60_wG_offset to congr_cl60_wG_offset + congr_cl60_wG_d'length-1), + din => congr_cl60_wG_d, + dout => congr_cl60_wG_q); +congr_cl60_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl60_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl60_wH_offset to congr_cl60_wH_offset + congr_cl60_wH_d'length-1), + scout => sov(congr_cl60_wH_offset to congr_cl60_wH_offset + congr_cl60_wH_d'length-1), + din => congr_cl60_wH_d, + dout => congr_cl60_wH_q); +congr_cl61_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl61_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl61_wA_offset to congr_cl61_wA_offset + congr_cl61_wA_d'length-1), + scout => sov(congr_cl61_wA_offset to congr_cl61_wA_offset + congr_cl61_wA_d'length-1), + din => congr_cl61_wA_d, + dout => congr_cl61_wA_q); +congr_cl61_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl61_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl61_wB_offset to congr_cl61_wB_offset + congr_cl61_wB_d'length-1), + scout => sov(congr_cl61_wB_offset to congr_cl61_wB_offset + congr_cl61_wB_d'length-1), + din => congr_cl61_wB_d, + dout => congr_cl61_wB_q); +congr_cl61_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl61_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl61_wC_offset to congr_cl61_wC_offset + congr_cl61_wC_d'length-1), + scout => sov(congr_cl61_wC_offset to congr_cl61_wC_offset + congr_cl61_wC_d'length-1), + din => congr_cl61_wC_d, + dout => congr_cl61_wC_q); +congr_cl61_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl61_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl61_wD_offset to congr_cl61_wD_offset + congr_cl61_wD_d'length-1), + scout => sov(congr_cl61_wD_offset to congr_cl61_wD_offset + congr_cl61_wD_d'length-1), + din => congr_cl61_wD_d, + dout => congr_cl61_wD_q); +congr_cl61_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl61_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl61_wE_offset to congr_cl61_wE_offset + congr_cl61_wE_d'length-1), + scout => sov(congr_cl61_wE_offset to congr_cl61_wE_offset + congr_cl61_wE_d'length-1), + din => congr_cl61_wE_d, + dout => congr_cl61_wE_q); +congr_cl61_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl61_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl61_wF_offset to congr_cl61_wF_offset + congr_cl61_wF_d'length-1), + scout => sov(congr_cl61_wF_offset to congr_cl61_wF_offset + congr_cl61_wF_d'length-1), + din => congr_cl61_wF_d, + dout => congr_cl61_wF_q); +congr_cl61_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl61_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl61_wG_offset to congr_cl61_wG_offset + congr_cl61_wG_d'length-1), + scout => sov(congr_cl61_wG_offset to congr_cl61_wG_offset + congr_cl61_wG_d'length-1), + din => congr_cl61_wG_d, + dout => congr_cl61_wG_q); +congr_cl61_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl61_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl61_wH_offset to congr_cl61_wH_offset + congr_cl61_wH_d'length-1), + scout => sov(congr_cl61_wH_offset to congr_cl61_wH_offset + congr_cl61_wH_d'length-1), + din => congr_cl61_wH_d, + dout => congr_cl61_wH_q); +congr_cl62_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl62_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl62_wA_offset to congr_cl62_wA_offset + congr_cl62_wA_d'length-1), + scout => sov(congr_cl62_wA_offset to congr_cl62_wA_offset + congr_cl62_wA_d'length-1), + din => congr_cl62_wA_d, + dout => congr_cl62_wA_q); +congr_cl62_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl62_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl62_wB_offset to congr_cl62_wB_offset + congr_cl62_wB_d'length-1), + scout => sov(congr_cl62_wB_offset to congr_cl62_wB_offset + congr_cl62_wB_d'length-1), + din => congr_cl62_wB_d, + dout => congr_cl62_wB_q); +congr_cl62_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl62_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl62_wC_offset to congr_cl62_wC_offset + congr_cl62_wC_d'length-1), + scout => sov(congr_cl62_wC_offset to congr_cl62_wC_offset + congr_cl62_wC_d'length-1), + din => congr_cl62_wC_d, + dout => congr_cl62_wC_q); +congr_cl62_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl62_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl62_wD_offset to congr_cl62_wD_offset + congr_cl62_wD_d'length-1), + scout => sov(congr_cl62_wD_offset to congr_cl62_wD_offset + congr_cl62_wD_d'length-1), + din => congr_cl62_wD_d, + dout => congr_cl62_wD_q); +congr_cl62_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl62_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl62_wE_offset to congr_cl62_wE_offset + congr_cl62_wE_d'length-1), + scout => sov(congr_cl62_wE_offset to congr_cl62_wE_offset + congr_cl62_wE_d'length-1), + din => congr_cl62_wE_d, + dout => congr_cl62_wE_q); +congr_cl62_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl62_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl62_wF_offset to congr_cl62_wF_offset + congr_cl62_wF_d'length-1), + scout => sov(congr_cl62_wF_offset to congr_cl62_wF_offset + congr_cl62_wF_d'length-1), + din => congr_cl62_wF_d, + dout => congr_cl62_wF_q); +congr_cl62_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl62_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl62_wG_offset to congr_cl62_wG_offset + congr_cl62_wG_d'length-1), + scout => sov(congr_cl62_wG_offset to congr_cl62_wG_offset + congr_cl62_wG_d'length-1), + din => congr_cl62_wG_d, + dout => congr_cl62_wG_q); +congr_cl62_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl62_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl62_wH_offset to congr_cl62_wH_offset + congr_cl62_wH_d'length-1), + scout => sov(congr_cl62_wH_offset to congr_cl62_wH_offset + congr_cl62_wH_d'length-1), + din => congr_cl62_wH_d, + dout => congr_cl62_wH_q); +congr_cl63_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl63_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl63_wA_offset to congr_cl63_wA_offset + congr_cl63_wA_d'length-1), + scout => sov(congr_cl63_wA_offset to congr_cl63_wA_offset + congr_cl63_wA_d'length-1), + din => congr_cl63_wA_d, + dout => congr_cl63_wA_q); +congr_cl63_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl63_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl63_wB_offset to congr_cl63_wB_offset + congr_cl63_wB_d'length-1), + scout => sov(congr_cl63_wB_offset to congr_cl63_wB_offset + congr_cl63_wB_d'length-1), + din => congr_cl63_wB_d, + dout => congr_cl63_wB_q); +congr_cl63_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl63_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl63_wC_offset to congr_cl63_wC_offset + congr_cl63_wC_d'length-1), + scout => sov(congr_cl63_wC_offset to congr_cl63_wC_offset + congr_cl63_wC_d'length-1), + din => congr_cl63_wC_d, + dout => congr_cl63_wC_q); +congr_cl63_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl63_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl63_wD_offset to congr_cl63_wD_offset + congr_cl63_wD_d'length-1), + scout => sov(congr_cl63_wD_offset to congr_cl63_wD_offset + congr_cl63_wD_d'length-1), + din => congr_cl63_wD_d, + dout => congr_cl63_wD_q); +congr_cl63_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl63_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl63_wE_offset to congr_cl63_wE_offset + congr_cl63_wE_d'length-1), + scout => sov(congr_cl63_wE_offset to congr_cl63_wE_offset + congr_cl63_wE_d'length-1), + din => congr_cl63_wE_d, + dout => congr_cl63_wE_q); +congr_cl63_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl63_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl63_wF_offset to congr_cl63_wF_offset + congr_cl63_wF_d'length-1), + scout => sov(congr_cl63_wF_offset to congr_cl63_wF_offset + congr_cl63_wF_d'length-1), + din => congr_cl63_wF_d, + dout => congr_cl63_wF_q); +congr_cl63_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl63_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl63_wG_offset to congr_cl63_wG_offset + congr_cl63_wG_d'length-1), + scout => sov(congr_cl63_wG_offset to congr_cl63_wG_offset + congr_cl63_wG_d'length-1), + din => congr_cl63_wG_d, + dout => congr_cl63_wG_q); +congr_cl63_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl63_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl63_wH_offset to congr_cl63_wH_offset + congr_cl63_wH_d'length-1), + scout => sov(congr_cl63_wH_offset to congr_cl63_wH_offset + congr_cl63_wH_d'length-1), + din => congr_cl63_wH_d, + dout => congr_cl63_wH_q); +congr_cl_all_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => congr_cl_all_act_d, + dout(0) => congr_cl_all_act_q); +p0_congr_cl0_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl0_act_d, + dout(0) => p0_congr_cl0_act_q); +p0_congr_cl1_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl1_act_d, + dout(0) => p0_congr_cl1_act_q); +p0_congr_cl2_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl2_act_d, + dout(0) => p0_congr_cl2_act_q); +p0_congr_cl3_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl3_act_d, + dout(0) => p0_congr_cl3_act_q); +p0_congr_cl4_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl4_act_d, + dout(0) => p0_congr_cl4_act_q); +p0_congr_cl5_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl5_act_d, + dout(0) => p0_congr_cl5_act_q); +p0_congr_cl6_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl6_act_d, + dout(0) => p0_congr_cl6_act_q); +p0_congr_cl7_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl7_act_d, + dout(0) => p0_congr_cl7_act_q); +p0_congr_cl8_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl8_act_d, + dout(0) => p0_congr_cl8_act_q); +p0_congr_cl9_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl9_act_d, + dout(0) => p0_congr_cl9_act_q); +p0_congr_cl10_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl10_act_d, + dout(0) => p0_congr_cl10_act_q); +p0_congr_cl11_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl11_act_d, + dout(0) => p0_congr_cl11_act_q); +p0_congr_cl12_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl12_act_d, + dout(0) => p0_congr_cl12_act_q); +p0_congr_cl13_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl13_act_d, + dout(0) => p0_congr_cl13_act_q); +p0_congr_cl14_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl14_act_d, + dout(0) => p0_congr_cl14_act_q); +p0_congr_cl15_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl15_act_d, + dout(0) => p0_congr_cl15_act_q); +p0_congr_cl16_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl16_act_d, + dout(0) => p0_congr_cl16_act_q); +p0_congr_cl17_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl17_act_d, + dout(0) => p0_congr_cl17_act_q); +p0_congr_cl18_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl18_act_d, + dout(0) => p0_congr_cl18_act_q); +p0_congr_cl19_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl19_act_d, + dout(0) => p0_congr_cl19_act_q); +p0_congr_cl20_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl20_act_d, + dout(0) => p0_congr_cl20_act_q); +p0_congr_cl21_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl21_act_d, + dout(0) => p0_congr_cl21_act_q); +p0_congr_cl22_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl22_act_d, + dout(0) => p0_congr_cl22_act_q); +p0_congr_cl23_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl23_act_d, + dout(0) => p0_congr_cl23_act_q); +p0_congr_cl24_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl24_act_d, + dout(0) => p0_congr_cl24_act_q); +p0_congr_cl25_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl25_act_d, + dout(0) => p0_congr_cl25_act_q); +p0_congr_cl26_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl26_act_d, + dout(0) => p0_congr_cl26_act_q); +p0_congr_cl27_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl27_act_d, + dout(0) => p0_congr_cl27_act_q); +p0_congr_cl28_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl28_act_d, + dout(0) => p0_congr_cl28_act_q); +p0_congr_cl29_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl29_act_d, + dout(0) => p0_congr_cl29_act_q); +p0_congr_cl30_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl30_act_d, + dout(0) => p0_congr_cl30_act_q); +p0_congr_cl31_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl31_act_d, + dout(0) => p0_congr_cl31_act_q); +p0_congr_cl32_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl32_act_d, + dout(0) => p0_congr_cl32_act_q); +p0_congr_cl33_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl33_act_d, + dout(0) => p0_congr_cl33_act_q); +p0_congr_cl34_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl34_act_d, + dout(0) => p0_congr_cl34_act_q); +p0_congr_cl35_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl35_act_d, + dout(0) => p0_congr_cl35_act_q); +p0_congr_cl36_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl36_act_d, + dout(0) => p0_congr_cl36_act_q); +p0_congr_cl37_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl37_act_d, + dout(0) => p0_congr_cl37_act_q); +p0_congr_cl38_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl38_act_d, + dout(0) => p0_congr_cl38_act_q); +p0_congr_cl39_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl39_act_d, + dout(0) => p0_congr_cl39_act_q); +p0_congr_cl40_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl40_act_d, + dout(0) => p0_congr_cl40_act_q); +p0_congr_cl41_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl41_act_d, + dout(0) => p0_congr_cl41_act_q); +p0_congr_cl42_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl42_act_d, + dout(0) => p0_congr_cl42_act_q); +p0_congr_cl43_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl43_act_d, + dout(0) => p0_congr_cl43_act_q); +p0_congr_cl44_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl44_act_d, + dout(0) => p0_congr_cl44_act_q); +p0_congr_cl45_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl45_act_d, + dout(0) => p0_congr_cl45_act_q); +p0_congr_cl46_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl46_act_d, + dout(0) => p0_congr_cl46_act_q); +p0_congr_cl47_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl47_act_d, + dout(0) => p0_congr_cl47_act_q); +p0_congr_cl48_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl48_act_d, + dout(0) => p0_congr_cl48_act_q); +p0_congr_cl49_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl49_act_d, + dout(0) => p0_congr_cl49_act_q); +p0_congr_cl50_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl50_act_d, + dout(0) => p0_congr_cl50_act_q); +p0_congr_cl51_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl51_act_d, + dout(0) => p0_congr_cl51_act_q); +p0_congr_cl52_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl52_act_d, + dout(0) => p0_congr_cl52_act_q); +p0_congr_cl53_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl53_act_d, + dout(0) => p0_congr_cl53_act_q); +p0_congr_cl54_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl54_act_d, + dout(0) => p0_congr_cl54_act_q); +p0_congr_cl55_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl55_act_d, + dout(0) => p0_congr_cl55_act_q); +p0_congr_cl56_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl56_act_d, + dout(0) => p0_congr_cl56_act_q); +p0_congr_cl57_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl57_act_d, + dout(0) => p0_congr_cl57_act_q); +p0_congr_cl58_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl58_act_d, + dout(0) => p0_congr_cl58_act_q); +p0_congr_cl59_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl59_act_d, + dout(0) => p0_congr_cl59_act_q); +p0_congr_cl60_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl60_act_d, + dout(0) => p0_congr_cl60_act_q); +p0_congr_cl61_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl61_act_d, + dout(0) => p0_congr_cl61_act_q); +p0_congr_cl62_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl62_act_d, + dout(0) => p0_congr_cl62_act_q); +p0_congr_cl63_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl63_act_d, + dout(0) => p0_congr_cl63_act_q); +p1_congr_cl0_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl0_act_d, + dout(0) => p1_congr_cl0_act_q); +p1_congr_cl1_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl1_act_d, + dout(0) => p1_congr_cl1_act_q); +p1_congr_cl2_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl2_act_d, + dout(0) => p1_congr_cl2_act_q); +p1_congr_cl3_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl3_act_d, + dout(0) => p1_congr_cl3_act_q); +p1_congr_cl4_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl4_act_d, + dout(0) => p1_congr_cl4_act_q); +p1_congr_cl5_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl5_act_d, + dout(0) => p1_congr_cl5_act_q); +p1_congr_cl6_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl6_act_d, + dout(0) => p1_congr_cl6_act_q); +p1_congr_cl7_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl7_act_d, + dout(0) => p1_congr_cl7_act_q); +p1_congr_cl8_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl8_act_d, + dout(0) => p1_congr_cl8_act_q); +p1_congr_cl9_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl9_act_d, + dout(0) => p1_congr_cl9_act_q); +p1_congr_cl10_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl10_act_d, + dout(0) => p1_congr_cl10_act_q); +p1_congr_cl11_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl11_act_d, + dout(0) => p1_congr_cl11_act_q); +p1_congr_cl12_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl12_act_d, + dout(0) => p1_congr_cl12_act_q); +p1_congr_cl13_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl13_act_d, + dout(0) => p1_congr_cl13_act_q); +p1_congr_cl14_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl14_act_d, + dout(0) => p1_congr_cl14_act_q); +p1_congr_cl15_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl15_act_d, + dout(0) => p1_congr_cl15_act_q); +p1_congr_cl16_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl16_act_d, + dout(0) => p1_congr_cl16_act_q); +p1_congr_cl17_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl17_act_d, + dout(0) => p1_congr_cl17_act_q); +p1_congr_cl18_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl18_act_d, + dout(0) => p1_congr_cl18_act_q); +p1_congr_cl19_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl19_act_d, + dout(0) => p1_congr_cl19_act_q); +p1_congr_cl20_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl20_act_d, + dout(0) => p1_congr_cl20_act_q); +p1_congr_cl21_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl21_act_d, + dout(0) => p1_congr_cl21_act_q); +p1_congr_cl22_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl22_act_d, + dout(0) => p1_congr_cl22_act_q); +p1_congr_cl23_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl23_act_d, + dout(0) => p1_congr_cl23_act_q); +p1_congr_cl24_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl24_act_d, + dout(0) => p1_congr_cl24_act_q); +p1_congr_cl25_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl25_act_d, + dout(0) => p1_congr_cl25_act_q); +p1_congr_cl26_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl26_act_d, + dout(0) => p1_congr_cl26_act_q); +p1_congr_cl27_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl27_act_d, + dout(0) => p1_congr_cl27_act_q); +p1_congr_cl28_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl28_act_d, + dout(0) => p1_congr_cl28_act_q); +p1_congr_cl29_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl29_act_d, + dout(0) => p1_congr_cl29_act_q); +p1_congr_cl30_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl30_act_d, + dout(0) => p1_congr_cl30_act_q); +p1_congr_cl31_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl31_act_d, + dout(0) => p1_congr_cl31_act_q); +p1_congr_cl32_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl32_act_d, + dout(0) => p1_congr_cl32_act_q); +p1_congr_cl33_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl33_act_d, + dout(0) => p1_congr_cl33_act_q); +p1_congr_cl34_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl34_act_d, + dout(0) => p1_congr_cl34_act_q); +p1_congr_cl35_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl35_act_d, + dout(0) => p1_congr_cl35_act_q); +p1_congr_cl36_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl36_act_d, + dout(0) => p1_congr_cl36_act_q); +p1_congr_cl37_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl37_act_d, + dout(0) => p1_congr_cl37_act_q); +p1_congr_cl38_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl38_act_d, + dout(0) => p1_congr_cl38_act_q); +p1_congr_cl39_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl39_act_d, + dout(0) => p1_congr_cl39_act_q); +p1_congr_cl40_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl40_act_d, + dout(0) => p1_congr_cl40_act_q); +p1_congr_cl41_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl41_act_d, + dout(0) => p1_congr_cl41_act_q); +p1_congr_cl42_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl42_act_d, + dout(0) => p1_congr_cl42_act_q); +p1_congr_cl43_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl43_act_d, + dout(0) => p1_congr_cl43_act_q); +p1_congr_cl44_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl44_act_d, + dout(0) => p1_congr_cl44_act_q); +p1_congr_cl45_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl45_act_d, + dout(0) => p1_congr_cl45_act_q); +p1_congr_cl46_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl46_act_d, + dout(0) => p1_congr_cl46_act_q); +p1_congr_cl47_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl47_act_d, + dout(0) => p1_congr_cl47_act_q); +p1_congr_cl48_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl48_act_d, + dout(0) => p1_congr_cl48_act_q); +p1_congr_cl49_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl49_act_d, + dout(0) => p1_congr_cl49_act_q); +p1_congr_cl50_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl50_act_d, + dout(0) => p1_congr_cl50_act_q); +p1_congr_cl51_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl51_act_d, + dout(0) => p1_congr_cl51_act_q); +p1_congr_cl52_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl52_act_d, + dout(0) => p1_congr_cl52_act_q); +p1_congr_cl53_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl53_act_d, + dout(0) => p1_congr_cl53_act_q); +p1_congr_cl54_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl54_act_d, + dout(0) => p1_congr_cl54_act_q); +p1_congr_cl55_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl55_act_d, + dout(0) => p1_congr_cl55_act_q); +p1_congr_cl56_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl56_act_d, + dout(0) => p1_congr_cl56_act_q); +p1_congr_cl57_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl57_act_d, + dout(0) => p1_congr_cl57_act_q); +p1_congr_cl58_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl58_act_d, + dout(0) => p1_congr_cl58_act_q); +p1_congr_cl59_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl59_act_d, + dout(0) => p1_congr_cl59_act_q); +p1_congr_cl60_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl60_act_d, + dout(0) => p1_congr_cl60_act_q); +p1_congr_cl61_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl61_act_d, + dout(0) => p1_congr_cl61_act_q); +p1_congr_cl62_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl62_act_d, + dout(0) => p1_congr_cl62_act_q); +p1_congr_cl63_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl63_act_d, + dout(0) => p1_congr_cl63_act_q); +flush_wayA_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayA_d, + dout => flush_wayA_q); +flush_wayA_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv4_ex4_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(flush_wayA_data_offset to flush_wayA_data_offset + flush_wayA_data_d'length-1), + scout => sov(flush_wayA_data_offset to flush_wayA_data_offset + flush_wayA_data_d'length-1), + din => flush_wayA_data_d, + dout => flush_wayA_data_q); +flush_wayA_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv5_ex5_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayA_data2_d, + dout => flush_wayA_data2_q); +flush_wayB_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayB_d, + dout => flush_wayB_q); +flush_wayB_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv4_ex4_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(flush_wayB_data_offset to flush_wayB_data_offset + flush_wayB_data_d'length-1), + scout => sov(flush_wayB_data_offset to flush_wayB_data_offset + flush_wayB_data_d'length-1), + din => flush_wayB_data_d, + dout => flush_wayB_data_q); +flush_wayB_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv5_ex5_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayB_data2_d, + dout => flush_wayB_data2_q); +flush_wayC_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayC_d, + dout => flush_wayC_q); +flush_wayC_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv4_ex4_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(flush_wayC_data_offset to flush_wayC_data_offset + flush_wayC_data_d'length-1), + scout => sov(flush_wayC_data_offset to flush_wayC_data_offset + flush_wayC_data_d'length-1), + din => flush_wayC_data_d, + dout => flush_wayC_data_q); +flush_wayC_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv5_ex5_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayC_data2_d, + dout => flush_wayC_data2_q); +flush_wayD_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayD_d, + dout => flush_wayD_q); +flush_wayD_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv4_ex4_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(flush_wayD_data_offset to flush_wayD_data_offset + flush_wayD_data_d'length-1), + scout => sov(flush_wayD_data_offset to flush_wayD_data_offset + flush_wayD_data_d'length-1), + din => flush_wayD_data_d, + dout => flush_wayD_data_q); +flush_wayD_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv5_ex5_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayD_data2_d, + dout => flush_wayD_data2_q); +flush_wayE_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayE_d, + dout => flush_wayE_q); +flush_wayE_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv4_ex4_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(flush_wayE_data_offset to flush_wayE_data_offset + flush_wayE_data_d'length-1), + scout => sov(flush_wayE_data_offset to flush_wayE_data_offset + flush_wayE_data_d'length-1), + din => flush_wayE_data_d, + dout => flush_wayE_data_q); +flush_wayE_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv5_ex5_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayE_data2_d, + dout => flush_wayE_data2_q); +flush_wayF_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayF_d, + dout => flush_wayF_q); +flush_wayF_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv4_ex4_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(flush_wayF_data_offset to flush_wayF_data_offset + flush_wayF_data_d'length-1), + scout => sov(flush_wayF_data_offset to flush_wayF_data_offset + flush_wayF_data_d'length-1), + din => flush_wayF_data_d, + dout => flush_wayF_data_q); +flush_wayF_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv5_ex5_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayF_data2_d, + dout => flush_wayF_data2_q); +flush_wayG_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayG_d, + dout => flush_wayG_q); +flush_wayG_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv4_ex4_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(flush_wayG_data_offset to flush_wayG_data_offset + flush_wayG_data_d'length-1), + scout => sov(flush_wayG_data_offset to flush_wayG_data_offset + flush_wayG_data_d'length-1), + din => flush_wayG_data_d, + dout => flush_wayG_data_q); +flush_wayG_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv5_ex5_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayG_data2_d, + dout => flush_wayG_data2_q); +flush_wayH_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayH_d, + dout => flush_wayH_q); +flush_wayH_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv4_ex4_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(flush_wayH_data_offset to flush_wayH_data_offset + flush_wayH_data_d'length-1), + scout => sov(flush_wayH_data_offset to flush_wayH_data_offset + flush_wayH_data_d'length-1), + din => flush_wayH_data_d, + dout => flush_wayH_data_q); +flush_wayH_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv5_ex5_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayH_data2_d, + dout => flush_wayH_data2_q); +ex3_flush_cline_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_flush_cline_offset), + scout => sov(ex3_flush_cline_offset), + din => ex3_flush_cline_d, + dout => ex3_flush_cline_q); +ex4_congr_cl_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex4_congr_cl_d, + dout => ex4_congr_cl_q); +ex5_congr_cl_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv4_ex4_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_congr_cl_offset to ex5_congr_cl_offset + ex5_congr_cl_d'length-1), + scout => sov(ex5_congr_cl_offset to ex5_congr_cl_offset + ex5_congr_cl_d'length-1), + din => ex5_congr_cl_d, + dout => ex5_congr_cl_q); +ex6_congr_cl_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv5_ex5_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex6_congr_cl_d, + dout => ex6_congr_cl_q); +ex7_congr_cl_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex7_congr_cl_offset to ex7_congr_cl_offset + ex7_congr_cl_d'length-1), + scout => sov(ex7_congr_cl_offset to ex7_congr_cl_offset + ex7_congr_cl_d'length-1), + din => ex7_congr_cl_d, + dout => ex7_congr_cl_q); +ex8_congr_cl_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex8_congr_cl_offset to ex8_congr_cl_offset + ex8_congr_cl_d'length-1), + scout => sov(ex8_congr_cl_offset to ex8_congr_cl_offset + ex8_congr_cl_d'length-1), + din => ex8_congr_cl_d, + dout => ex8_congr_cl_q); +ex9_congr_cl_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex9_congr_cl_offset to ex9_congr_cl_offset + ex9_congr_cl_d'length-1), + scout => sov(ex9_congr_cl_offset to ex9_congr_cl_offset + ex9_congr_cl_d'length-1), + din => ex9_congr_cl_d, + dout => ex9_congr_cl_q); +wayA_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(wayA_val_b_offset to wayA_val_b_offset + wayA_val_b_q'length-1), + scout => sov(wayA_val_b_offset to wayA_val_b_offset + wayA_val_b_q'length-1), + a1 => wayA_early_stg_pri, + a2 => wayA_stg_val, + b1 => wayA_later_stg_pri, + b2 => wayA_stg_val_b, + qb => wayA_val_b_q); +wayB_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(wayB_val_b_offset to wayB_val_b_offset + wayB_val_b_q'length-1), + scout => sov(wayB_val_b_offset to wayB_val_b_offset + wayB_val_b_q'length-1), + a1 => wayB_early_stg_pri, + a2 => wayB_stg_val, + b1 => wayB_later_stg_pri, + b2 => wayB_stg_val_b, + qb => wayB_val_b_q); +wayC_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(wayC_val_b_offset to wayC_val_b_offset + wayC_val_b_q'length-1), + scout => sov(wayC_val_b_offset to wayC_val_b_offset + wayC_val_b_q'length-1), + a1 => wayC_early_stg_pri, + a2 => wayC_stg_val, + b1 => wayC_later_stg_pri, + b2 => wayC_stg_val_b, + qb => wayC_val_b_q); +wayD_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(wayD_val_b_offset to wayD_val_b_offset + wayD_val_b_q'length-1), + scout => sov(wayD_val_b_offset to wayD_val_b_offset + wayD_val_b_q'length-1), + a1 => wayD_early_stg_pri, + a2 => wayD_stg_val, + b1 => wayD_later_stg_pri, + b2 => wayD_stg_val_b, + qb => wayD_val_b_q); +wayE_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(wayE_val_b_offset to wayE_val_b_offset + wayE_val_b_q'length-1), + scout => sov(wayE_val_b_offset to wayE_val_b_offset + wayE_val_b_q'length-1), + a1 => wayE_early_stg_pri, + a2 => wayE_stg_val, + b1 => wayE_later_stg_pri, + b2 => wayE_stg_val_b, + qb => wayE_val_b_q); +wayF_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(wayF_val_b_offset to wayF_val_b_offset + wayF_val_b_q'length-1), + scout => sov(wayF_val_b_offset to wayF_val_b_offset + wayF_val_b_q'length-1), + a1 => wayF_early_stg_pri, + a2 => wayF_stg_val, + b1 => wayF_later_stg_pri, + b2 => wayF_stg_val_b, + qb => wayF_val_b_q); +wayG_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(wayG_val_b_offset to wayG_val_b_offset + wayG_val_b_q'length-1), + scout => sov(wayG_val_b_offset to wayG_val_b_offset + wayG_val_b_q'length-1), + a1 => wayG_early_stg_pri, + a2 => wayG_stg_val, + b1 => wayG_later_stg_pri, + b2 => wayG_stg_val_b, + qb => wayG_val_b_q); +wayH_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(wayH_val_b_offset to wayH_val_b_offset + wayH_val_b_q'length-1), + scout => sov(wayH_val_b_offset to wayH_val_b_offset + wayH_val_b_q'length-1), + a1 => wayH_early_stg_pri, + a2 => wayH_stg_val, + b1 => wayH_later_stg_pri, + b2 => wayH_stg_val_b, + qb => wayH_val_b_q); +ex3_wayA_fxubyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayA_fxubyp_val_offset), + scout => sov(ex3_wayA_fxubyp_val_offset), + din => ex3_wayA_fxubyp_val_d, + dout => ex3_wayA_fxubyp_val_q); +ex3_wayB_fxubyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayB_fxubyp_val_offset), + scout => sov(ex3_wayB_fxubyp_val_offset), + din => ex3_wayB_fxubyp_val_d, + dout => ex3_wayB_fxubyp_val_q); +ex3_wayC_fxubyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayC_fxubyp_val_offset), + scout => sov(ex3_wayC_fxubyp_val_offset), + din => ex3_wayC_fxubyp_val_d, + dout => ex3_wayC_fxubyp_val_q); +ex3_wayD_fxubyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayD_fxubyp_val_offset), + scout => sov(ex3_wayD_fxubyp_val_offset), + din => ex3_wayD_fxubyp_val_d, + dout => ex3_wayD_fxubyp_val_q); +ex3_wayE_fxubyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayE_fxubyp_val_offset), + scout => sov(ex3_wayE_fxubyp_val_offset), + din => ex3_wayE_fxubyp_val_d, + dout => ex3_wayE_fxubyp_val_q); +ex3_wayF_fxubyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayF_fxubyp_val_offset), + scout => sov(ex3_wayF_fxubyp_val_offset), + din => ex3_wayF_fxubyp_val_d, + dout => ex3_wayF_fxubyp_val_q); +ex3_wayG_fxubyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayG_fxubyp_val_offset), + scout => sov(ex3_wayG_fxubyp_val_offset), + din => ex3_wayG_fxubyp_val_d, + dout => ex3_wayG_fxubyp_val_q); +ex3_wayH_fxubyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayH_fxubyp_val_offset), + scout => sov(ex3_wayH_fxubyp_val_offset), + din => ex3_wayH_fxubyp_val_d, + dout => ex3_wayH_fxubyp_val_q); +ex4_wayA_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayA_fxubyp_val_d, + dout(0) => ex4_wayA_fxubyp_val_q); +ex4_wayB_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayB_fxubyp_val_d, + dout(0) => ex4_wayB_fxubyp_val_q); +ex4_wayC_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayC_fxubyp_val_d, + dout(0) => ex4_wayC_fxubyp_val_q); +ex4_wayD_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayD_fxubyp_val_d, + dout(0) => ex4_wayD_fxubyp_val_q); +ex4_wayE_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayE_fxubyp_val_d, + dout(0) => ex4_wayE_fxubyp_val_q); +ex4_wayF_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayF_fxubyp_val_d, + dout(0) => ex4_wayF_fxubyp_val_q); +ex4_wayG_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayG_fxubyp_val_d, + dout(0) => ex4_wayG_fxubyp_val_q); +ex4_wayH_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayH_fxubyp_val_d, + dout(0) => ex4_wayH_fxubyp_val_q); +ex3_wayA_relbyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayA_relbyp_val_offset), + scout => sov(ex3_wayA_relbyp_val_offset), + din => ex3_wayA_relbyp_val_d, + dout => ex3_wayA_relbyp_val_q); +ex3_wayB_relbyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayB_relbyp_val_offset), + scout => sov(ex3_wayB_relbyp_val_offset), + din => ex3_wayB_relbyp_val_d, + dout => ex3_wayB_relbyp_val_q); +ex3_wayC_relbyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayC_relbyp_val_offset), + scout => sov(ex3_wayC_relbyp_val_offset), + din => ex3_wayC_relbyp_val_d, + dout => ex3_wayC_relbyp_val_q); +ex3_wayD_relbyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayD_relbyp_val_offset), + scout => sov(ex3_wayD_relbyp_val_offset), + din => ex3_wayD_relbyp_val_d, + dout => ex3_wayD_relbyp_val_q); +ex3_wayE_relbyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayE_relbyp_val_offset), + scout => sov(ex3_wayE_relbyp_val_offset), + din => ex3_wayE_relbyp_val_d, + dout => ex3_wayE_relbyp_val_q); +ex3_wayF_relbyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayF_relbyp_val_offset), + scout => sov(ex3_wayF_relbyp_val_offset), + din => ex3_wayF_relbyp_val_d, + dout => ex3_wayF_relbyp_val_q); +ex3_wayG_relbyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayG_relbyp_val_offset), + scout => sov(ex3_wayG_relbyp_val_offset), + din => ex3_wayG_relbyp_val_d, + dout => ex3_wayG_relbyp_val_q); +ex3_wayH_relbyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayH_relbyp_val_offset), + scout => sov(ex3_wayH_relbyp_val_offset), + din => ex3_wayH_relbyp_val_d, + dout => ex3_wayH_relbyp_val_q); +ex4_wayA_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayA_relbyp_val_d, + dout(0) => ex4_wayA_relbyp_val_q); +ex4_wayB_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayB_relbyp_val_d, + dout(0) => ex4_wayB_relbyp_val_q); +ex4_wayC_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayC_relbyp_val_d, + dout(0) => ex4_wayC_relbyp_val_q); +ex4_wayD_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayD_relbyp_val_d, + dout(0) => ex4_wayD_relbyp_val_q); +ex4_wayE_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayE_relbyp_val_d, + dout(0) => ex4_wayE_relbyp_val_q); +ex4_wayF_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayF_relbyp_val_d, + dout(0) => ex4_wayF_relbyp_val_q); +ex4_wayG_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayG_relbyp_val_d, + dout(0) => ex4_wayG_relbyp_val_q); +ex4_wayH_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayH_relbyp_val_d, + dout(0) => ex4_wayH_relbyp_val_q); +ex4_xuop_wayA_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_xuop_wayA_upd_offset), + scout => sov(ex4_xuop_wayA_upd_offset), + din => ex4_xuop_wayA_upd_d, + dout => ex4_xuop_wayA_upd_q); +ex4_xuop_wayB_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_xuop_wayB_upd_offset), + scout => sov(ex4_xuop_wayB_upd_offset), + din => ex4_xuop_wayB_upd_d, + dout => ex4_xuop_wayB_upd_q); +ex4_xuop_wayC_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_xuop_wayC_upd_offset), + scout => sov(ex4_xuop_wayC_upd_offset), + din => ex4_xuop_wayC_upd_d, + dout => ex4_xuop_wayC_upd_q); +ex4_xuop_wayD_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_xuop_wayD_upd_offset), + scout => sov(ex4_xuop_wayD_upd_offset), + din => ex4_xuop_wayD_upd_d, + dout => ex4_xuop_wayD_upd_q); +ex4_xuop_wayE_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_xuop_wayE_upd_offset), + scout => sov(ex4_xuop_wayE_upd_offset), + din => ex4_xuop_wayE_upd_d, + dout => ex4_xuop_wayE_upd_q); +ex4_xuop_wayF_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_xuop_wayF_upd_offset), + scout => sov(ex4_xuop_wayF_upd_offset), + din => ex4_xuop_wayF_upd_d, + dout => ex4_xuop_wayF_upd_q); +ex4_xuop_wayG_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_xuop_wayG_upd_offset), + scout => sov(ex4_xuop_wayG_upd_offset), + din => ex4_xuop_wayG_upd_d, + dout => ex4_xuop_wayG_upd_q); +ex4_xuop_wayH_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_xuop_wayH_upd_offset), + scout => sov(ex4_xuop_wayH_upd_offset), + din => ex4_xuop_wayH_upd_d, + dout => ex4_xuop_wayH_upd_q); +ex5_xuop_wayA_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_xuop_wayA_upd_offset), + scout => sov(ex5_xuop_wayA_upd_offset), + din => ex5_xuop_wayA_upd_d, + dout => ex5_xuop_wayA_upd_q); +ex5_xuop_wayB_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_xuop_wayB_upd_offset), + scout => sov(ex5_xuop_wayB_upd_offset), + din => ex5_xuop_wayB_upd_d, + dout => ex5_xuop_wayB_upd_q); +ex5_xuop_wayC_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_xuop_wayC_upd_offset), + scout => sov(ex5_xuop_wayC_upd_offset), + din => ex5_xuop_wayC_upd_d, + dout => ex5_xuop_wayC_upd_q); +ex5_xuop_wayD_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_xuop_wayD_upd_offset), + scout => sov(ex5_xuop_wayD_upd_offset), + din => ex5_xuop_wayD_upd_d, + dout => ex5_xuop_wayD_upd_q); +ex5_xuop_wayE_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_xuop_wayE_upd_offset), + scout => sov(ex5_xuop_wayE_upd_offset), + din => ex5_xuop_wayE_upd_d, + dout => ex5_xuop_wayE_upd_q); +ex5_xuop_wayF_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_xuop_wayF_upd_offset), + scout => sov(ex5_xuop_wayF_upd_offset), + din => ex5_xuop_wayF_upd_d, + dout => ex5_xuop_wayF_upd_q); +ex5_xuop_wayG_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_xuop_wayG_upd_offset), + scout => sov(ex5_xuop_wayG_upd_offset), + din => ex5_xuop_wayG_upd_d, + dout => ex5_xuop_wayG_upd_q); +ex5_xuop_wayH_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_xuop_wayH_upd_offset), + scout => sov(ex5_xuop_wayH_upd_offset), + din => ex5_xuop_wayH_upd_d, + dout => ex5_xuop_wayH_upd_q); +inval_clr_lck_wA_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(inval_clr_lck_wA_offset), + scout => sov(inval_clr_lck_wA_offset), + din => inval_clr_lck_wA_d, + dout => inval_clr_lck_wA_q); +inval_clr_lck_wB_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(inval_clr_lck_wB_offset), + scout => sov(inval_clr_lck_wB_offset), + din => inval_clr_lck_wB_d, + dout => inval_clr_lck_wB_q); +inval_clr_lck_wC_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(inval_clr_lck_wC_offset), + scout => sov(inval_clr_lck_wC_offset), + din => inval_clr_lck_wC_d, + dout => inval_clr_lck_wC_q); +inval_clr_lck_wD_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(inval_clr_lck_wD_offset), + scout => sov(inval_clr_lck_wD_offset), + din => inval_clr_lck_wD_d, + dout => inval_clr_lck_wD_q); +inval_clr_lck_wE_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(inval_clr_lck_wE_offset), + scout => sov(inval_clr_lck_wE_offset), + din => inval_clr_lck_wE_d, + dout => inval_clr_lck_wE_q); +inval_clr_lck_wF_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(inval_clr_lck_wF_offset), + scout => sov(inval_clr_lck_wF_offset), + din => inval_clr_lck_wF_d, + dout => inval_clr_lck_wF_q); +inval_clr_lck_wG_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(inval_clr_lck_wG_offset), + scout => sov(inval_clr_lck_wG_offset), + din => inval_clr_lck_wG_d, + dout => inval_clr_lck_wG_q); +inval_clr_lck_wH_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(inval_clr_lck_wH_offset), + scout => sov(inval_clr_lck_wH_offset), + din => inval_clr_lck_wH_d, + dout => inval_clr_lck_wH_q); +ex4_wayA_val_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex4_wayA_val_d, + dout => ex4_wayA_val_q); +ex4_wayB_val_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex4_wayB_val_d, + dout => ex4_wayB_val_q); +ex4_wayC_val_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex4_wayC_val_d, + dout => ex4_wayC_val_q); +ex4_wayD_val_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex4_wayD_val_d, + dout => ex4_wayD_val_q); +ex4_wayE_val_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex4_wayE_val_d, + dout => ex4_wayE_val_q); +ex4_wayF_val_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex4_wayF_val_d, + dout => ex4_wayF_val_q); +ex4_wayG_val_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex4_wayG_val_d, + dout => ex4_wayG_val_q); +ex4_wayH_val_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex4_wayH_val_d, + dout => ex4_wayH_val_q); +congr_cl_m_upd_wayA_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_m_upd_wayA_offset), + scout => sov(congr_cl_m_upd_wayA_offset), + din => congr_cl_m_upd_wayA_d, + dout => congr_cl_m_upd_wayA_q); +congr_cl_m_upd_wayB_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_m_upd_wayB_offset), + scout => sov(congr_cl_m_upd_wayB_offset), + din => congr_cl_m_upd_wayB_d, + dout => congr_cl_m_upd_wayB_q); +congr_cl_m_upd_wayC_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_m_upd_wayC_offset), + scout => sov(congr_cl_m_upd_wayC_offset), + din => congr_cl_m_upd_wayC_d, + dout => congr_cl_m_upd_wayC_q); +congr_cl_m_upd_wayD_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_m_upd_wayD_offset), + scout => sov(congr_cl_m_upd_wayD_offset), + din => congr_cl_m_upd_wayD_d, + dout => congr_cl_m_upd_wayD_q); +congr_cl_m_upd_wayE_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_m_upd_wayE_offset), + scout => sov(congr_cl_m_upd_wayE_offset), + din => congr_cl_m_upd_wayE_d, + dout => congr_cl_m_upd_wayE_q); +congr_cl_m_upd_wayF_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_m_upd_wayF_offset), + scout => sov(congr_cl_m_upd_wayF_offset), + din => congr_cl_m_upd_wayF_d, + dout => congr_cl_m_upd_wayF_q); +congr_cl_m_upd_wayG_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_m_upd_wayG_offset), + scout => sov(congr_cl_m_upd_wayG_offset), + din => congr_cl_m_upd_wayG_d, + dout => congr_cl_m_upd_wayG_q); +congr_cl_m_upd_wayH_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_m_upd_wayH_offset), + scout => sov(congr_cl_m_upd_wayH_offset), + din => congr_cl_m_upd_wayH_d, + dout => congr_cl_m_upd_wayH_q); +ex2_congr_cl_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv1_ex1_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex2_congr_cl_d, + dout => ex2_congr_cl_q); +ex3_congr_cl_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_congr_cl_offset to ex3_congr_cl_offset + ex3_congr_cl_d'length-1), + scout => sov(ex3_congr_cl_offset to ex3_congr_cl_offset + ex3_congr_cl_d'length-1), + din => ex3_congr_cl_d, + dout => ex3_congr_cl_q); +rel_congr_cl_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_congr_cl_d, + dout => rel_congr_cl_q); +rel24_congr_cl_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel24_congr_cl_offset to rel24_congr_cl_offset + rel24_congr_cl_d'length-1), + scout => sov(rel24_congr_cl_offset to rel24_congr_cl_offset + rel24_congr_cl_d'length-1), + din => rel24_congr_cl_d, + dout => rel24_congr_cl_q); +relu_congr_cl_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => relu_congr_cl_d, + dout => relu_congr_cl_q); +relu_s_congr_cl_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_perr_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(relu_s_congr_cl_offset to relu_s_congr_cl_offset + relu_s_congr_cl_d'length-1), + scout => sov(relu_s_congr_cl_offset to relu_s_congr_cl_offset + relu_s_congr_cl_d'length-1), + din => relu_s_congr_cl_d, + dout => relu_s_congr_cl_q); +reload_way_clr_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_way_clr_offset to reload_way_clr_offset + reload_way_clr_d'length-1), + scout => sov(reload_way_clr_offset to reload_way_clr_offset + reload_way_clr_d'length-1), + din => reload_way_clr_d, + dout => reload_way_clr_q); +ex4_watchSet_coll_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_watchSet_coll_offset), + scout => sov(ex4_watchSet_coll_offset), + din => ex4_watchSet_coll_d, + dout => ex4_watchSet_coll_q); +rel_wayA_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_wayA_val_b_offset to rel_wayA_val_b_offset + rel_wayA_val_b_q'length-1), + scout => sov(rel_wayA_val_b_offset to rel_wayA_val_b_offset + rel_wayA_val_b_q'length-1), + a1 => rel_wayA_early_stg_pri, + a2 => rel_wayA_stg_val, + b1 => rel_wayA_later_stg_pri, + b2 => rel_wayA_stg_val_b, + qb => rel_wayA_val_b_q); +rel_wayB_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_wayB_val_b_offset to rel_wayB_val_b_offset + rel_wayB_val_b_q'length-1), + scout => sov(rel_wayB_val_b_offset to rel_wayB_val_b_offset + rel_wayB_val_b_q'length-1), + a1 => rel_wayB_early_stg_pri, + a2 => rel_wayB_stg_val, + b1 => rel_wayB_later_stg_pri, + b2 => rel_wayB_stg_val_b, + qb => rel_wayB_val_b_q); +rel_wayC_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_wayC_val_b_offset to rel_wayC_val_b_offset + rel_wayC_val_b_q'length-1), + scout => sov(rel_wayC_val_b_offset to rel_wayC_val_b_offset + rel_wayC_val_b_q'length-1), + a1 => rel_wayC_early_stg_pri, + a2 => rel_wayC_stg_val, + b1 => rel_wayC_later_stg_pri, + b2 => rel_wayC_stg_val_b, + qb => rel_wayC_val_b_q); +rel_wayD_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_wayD_val_b_offset to rel_wayD_val_b_offset + rel_wayD_val_b_q'length-1), + scout => sov(rel_wayD_val_b_offset to rel_wayD_val_b_offset + rel_wayD_val_b_q'length-1), + a1 => rel_wayD_early_stg_pri, + a2 => rel_wayD_stg_val, + b1 => rel_wayD_later_stg_pri, + b2 => rel_wayD_stg_val_b, + qb => rel_wayD_val_b_q); +rel_wayE_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_wayE_val_b_offset to rel_wayE_val_b_offset + rel_wayE_val_b_q'length-1), + scout => sov(rel_wayE_val_b_offset to rel_wayE_val_b_offset + rel_wayE_val_b_q'length-1), + a1 => rel_wayE_early_stg_pri, + a2 => rel_wayE_stg_val, + b1 => rel_wayE_later_stg_pri, + b2 => rel_wayE_stg_val_b, + qb => rel_wayE_val_b_q); +rel_wayF_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_wayF_val_b_offset to rel_wayF_val_b_offset + rel_wayF_val_b_q'length-1), + scout => sov(rel_wayF_val_b_offset to rel_wayF_val_b_offset + rel_wayF_val_b_q'length-1), + a1 => rel_wayF_early_stg_pri, + a2 => rel_wayF_stg_val, + b1 => rel_wayF_later_stg_pri, + b2 => rel_wayF_stg_val_b, + qb => rel_wayF_val_b_q); +rel_wayG_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_wayG_val_b_offset to rel_wayG_val_b_offset + rel_wayG_val_b_q'length-1), + scout => sov(rel_wayG_val_b_offset to rel_wayG_val_b_offset + rel_wayG_val_b_q'length-1), + a1 => rel_wayG_early_stg_pri, + a2 => rel_wayG_stg_val, + b1 => rel_wayG_later_stg_pri, + b2 => rel_wayG_stg_val_b, + qb => rel_wayG_val_b_q); +rel_wayH_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_wayH_val_b_offset to rel_wayH_val_b_offset + rel_wayH_val_b_q'length-1), + scout => sov(rel_wayH_val_b_offset to rel_wayH_val_b_offset + rel_wayH_val_b_q'length-1), + a1 => rel_wayH_early_stg_pri, + a2 => rel_wayH_stg_val, + b1 => rel_wayH_later_stg_pri, + b2 => rel_wayH_stg_val_b, + qb => rel_wayH_val_b_q); +rel24_wayA_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayA_fxubyp_val_d, + dout(0) => rel24_wayA_fxubyp_val_q); +rel24_wayB_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayB_fxubyp_val_d, + dout(0) => rel24_wayB_fxubyp_val_q); +rel24_wayC_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayC_fxubyp_val_d, + dout(0) => rel24_wayC_fxubyp_val_q); +rel24_wayD_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayD_fxubyp_val_d, + dout(0) => rel24_wayD_fxubyp_val_q); +rel24_wayE_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayE_fxubyp_val_d, + dout(0) => rel24_wayE_fxubyp_val_q); +rel24_wayF_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayF_fxubyp_val_d, + dout(0) => rel24_wayF_fxubyp_val_q); +rel24_wayG_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayG_fxubyp_val_d, + dout(0) => rel24_wayG_fxubyp_val_q); +rel24_wayH_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayH_fxubyp_val_d, + dout(0) => rel24_wayH_fxubyp_val_q); +rel24_wayA_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayA_relbyp_val_d, + dout(0) => rel24_wayA_relbyp_val_q); +rel24_wayB_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayB_relbyp_val_d, + dout(0) => rel24_wayB_relbyp_val_q); +rel24_wayC_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayC_relbyp_val_d, + dout(0) => rel24_wayC_relbyp_val_q); +rel24_wayD_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayD_relbyp_val_d, + dout(0) => rel24_wayD_relbyp_val_q); +rel24_wayE_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayE_relbyp_val_d, + dout(0) => rel24_wayE_relbyp_val_q); +rel24_wayF_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayF_relbyp_val_d, + dout(0) => rel24_wayF_relbyp_val_q); +rel24_wayG_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayG_relbyp_val_d, + dout(0) => rel24_wayG_relbyp_val_q); +rel24_wayH_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayH_relbyp_val_d, + dout(0) => rel24_wayH_relbyp_val_q); +rel_val_stg2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_val_stg2_offset), + scout => sov(rel_val_stg2_offset), + din => rel_val_stg2_d, + dout => rel_val_stg2_q); +rel_val_clr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_val_clr_offset), + scout => sov(rel_val_clr_offset), + din => rel_val_clr_d, + dout => rel_val_clr_q); +rel_port_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_port_upd_offset), + scout => sov(rel_port_upd_offset), + din => rel_port_upd_d, + dout => rel_port_upd_q); +rel_val_stg4_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_val_stg4_offset), + scout => sov(rel_val_stg4_offset), + din => rel_val_stg4_d, + dout => rel_val_stg4_q); +rel_binv_stg4_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_binv_stg4_offset), + scout => sov(rel_binv_stg4_offset), + din => rel_binv_stg4_d, + dout => rel_binv_stg4_q); +back_inval_stg3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(back_inval_stg3_offset), + scout => sov(back_inval_stg3_offset), + din => back_inval_stg3_d, + dout => back_inval_stg3_q); +back_inval_stg4_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(back_inval_stg4_offset), + scout => sov(back_inval_stg4_offset), + din => back_inval_stg4_d, + dout => back_inval_stg4_q); +back_inval_stg5_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(back_inval_stg5_offset), + scout => sov(back_inval_stg5_offset), + din => back_inval_stg5_d, + dout => back_inval_stg5_q); +binv4_ex4_xuop_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv4_ex4_xuop_upd_offset), + scout => sov(binv4_ex4_xuop_upd_offset), + din => binv4_ex4_xuop_upd_d, + dout => binv4_ex4_xuop_upd_q); +binv4_ex4_dir_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv4_ex4_dir_val_offset), + scout => sov(binv4_ex4_dir_val_offset), + din => binv4_ex4_dir_val_d, + dout => binv4_ex4_dir_val_q); +ex4_dir_err_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_dir_err_val_offset), + scout => sov(ex4_dir_err_val_offset), + din => ex4_dir_err_val_d, + dout => ex4_dir_err_val_q); +ex5_dir_err_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_dir_err_val_offset), + scout => sov(ex5_dir_err_val_offset), + din => ex5_dir_err_val_d, + dout => ex5_dir_err_val_q); +ex6_dir_err_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_dir_err_val_offset), + scout => sov(ex6_dir_err_val_offset), + din => ex6_dir_err_val_d, + dout => ex6_dir_err_val_q); +derr2_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(derr2_stg_act_offset), + scout => sov(derr2_stg_act_offset), + din => derr2_stg_act_d, + dout => derr2_stg_act_q); +derr3_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(derr3_stg_act_offset), + scout => sov(derr3_stg_act_offset), + din => derr3_stg_act_d, + dout => derr3_stg_act_q); +derr4_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(derr4_stg_act_offset), + scout => sov(derr4_stg_act_offset), + din => derr4_stg_act_d, + dout => derr4_stg_act_q); +derr5_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(derr5_stg_act_offset), + scout => sov(derr5_stg_act_offset), + din => derr5_stg_act_d, + dout => derr5_stg_act_q); +my_multihit_lcb : entity tri.tri_lcbnd(tri_lcbnd) +generic map (expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + d1clk => my_multihit_d1clk, + d2clk => my_multihit_d2clk, + lclk => my_multihit_lclk); +ex4_dir_multihit_val_b_reg: entity tri.tri_inv_nlats(tri_inv_nlats) +generic map (width => 1, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + lclk => my_multihit_lclk, + d1clk => my_multihit_d1clk, + d2clk => my_multihit_d2clk, + scanin(0) => siv(ex4_dir_multihit_val_b_offset), + scanout(0) => sov(ex4_dir_multihit_val_b_offset), + d(0) => ex3_dir_multihit_val, + qb(0) => ex4_dir_multihit_val_b_q); +my_ddmh_lcb : entity tri.tri_lcbnd(tri_lcbnd) +generic map (expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + d1clk => my_ddmh_d1clk, + d2clk => my_ddmh_d2clk, + lclk => my_ddmh_lclk); +ex4_n_lsu_ddmh_flush_b_reg: entity tri.tri_inv_nlats(tri_inv_nlats) +generic map (width => 4, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + lclk => my_ddmh_lclk, + d1clk => my_ddmh_d1clk, + d2clk => my_ddmh_d2clk, + scanin => siv(ex4_n_lsu_ddmh_flush_b_offset to ex4_n_lsu_ddmh_flush_b_offset + ex4_n_lsu_ddmh_flush_b_d'length-1), + scanout => sov(ex4_n_lsu_ddmh_flush_b_offset to ex4_n_lsu_ddmh_flush_b_offset + ex4_n_lsu_ddmh_flush_b_d'length-1), + d => ex4_n_lsu_ddmh_flush_b_d, + qb => ex4_n_lsu_ddmh_flush_b_q); +dcarr_up_way_addr_reg: entity tri.tri_aoi22_nlats +generic map (width => 3, init => "000", expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + lclk => my_ddmh_lclk, + d1clk => my_ddmh_d1clk, + d2clk => my_ddmh_d2clk, + scanin => siv(dcarr_up_way_addr_offset to dcarr_up_way_addr_offset + dcarr_up_way_addr_q'length-1), + scanout => sov(dcarr_up_way_addr_offset to dcarr_up_way_addr_offset + dcarr_up_way_addr_q'length-1), + a1 => rel_up_way_addr_b, + a2 => rel_dcarr_addr_sel, + b1 => ex3_xuop_up_addr_b, + b2 => rel_dcarr_addr_sel_b, + qb => dcarr_up_way_addr_q); +reload_wayA_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayA_d, + dout => reload_wayA_q); +reload_wayB_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayB_d, + dout => reload_wayB_q); +reload_wayC_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayC_d, + dout => reload_wayC_q); +reload_wayD_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayD_d, + dout => reload_wayD_q); +reload_wayE_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayE_d, + dout => reload_wayE_q); +reload_wayF_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayF_d, + dout => reload_wayF_q); +reload_wayG_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayG_d, + dout => reload_wayG_q); +reload_wayH_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayH_d, + dout => reload_wayH_q); +rel_wayA_val_stg_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_wayA_val_stg_d, + dout => rel_wayA_val_stg_q); +rel_wayB_val_stg_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_wayB_val_stg_d, + dout => rel_wayB_val_stg_q); +rel_wayC_val_stg_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_wayC_val_stg_d, + dout => rel_wayC_val_stg_q); +rel_wayD_val_stg_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_wayD_val_stg_d, + dout => rel_wayD_val_stg_q); +rel_wayE_val_stg_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_wayE_val_stg_d, + dout => rel_wayE_val_stg_q); +rel_wayF_val_stg_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_wayF_val_stg_d, + dout => rel_wayF_val_stg_q); +rel_wayG_val_stg_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_wayG_val_stg_d, + dout => rel_wayG_val_stg_q); +rel_wayH_val_stg_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_wayH_val_stg_d, + dout => rel_wayH_val_stg_q); +reload_wayA_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_perr_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayA_data_offset to reload_wayA_data_offset + reload_wayA_data_d'length-1), + scout => sov(reload_wayA_data_offset to reload_wayA_data_offset + reload_wayA_data_d'length-1), + din => reload_wayA_data_d, + dout => reload_wayA_data_q); +reload_wayB_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_perr_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayB_data_offset to reload_wayB_data_offset + reload_wayB_data_d'length-1), + scout => sov(reload_wayB_data_offset to reload_wayB_data_offset + reload_wayB_data_d'length-1), + din => reload_wayB_data_d, + dout => reload_wayB_data_q); +reload_wayC_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_perr_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayC_data_offset to reload_wayC_data_offset + reload_wayC_data_d'length-1), + scout => sov(reload_wayC_data_offset to reload_wayC_data_offset + reload_wayC_data_d'length-1), + din => reload_wayC_data_d, + dout => reload_wayC_data_q); +reload_wayD_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_perr_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayD_data_offset to reload_wayD_data_offset + reload_wayD_data_d'length-1), + scout => sov(reload_wayD_data_offset to reload_wayD_data_offset + reload_wayD_data_d'length-1), + din => reload_wayD_data_d, + dout => reload_wayD_data_q); +reload_wayE_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_perr_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayE_data_offset to reload_wayE_data_offset + reload_wayE_data_d'length-1), + scout => sov(reload_wayE_data_offset to reload_wayE_data_offset + reload_wayE_data_d'length-1), + din => reload_wayE_data_d, + dout => reload_wayE_data_q); +reload_wayF_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_perr_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayF_data_offset to reload_wayF_data_offset + reload_wayF_data_d'length-1), + scout => sov(reload_wayF_data_offset to reload_wayF_data_offset + reload_wayF_data_d'length-1), + din => reload_wayF_data_d, + dout => reload_wayF_data_q); +reload_wayG_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_perr_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayG_data_offset to reload_wayG_data_offset + reload_wayG_data_d'length-1), + scout => sov(reload_wayG_data_offset to reload_wayG_data_offset + reload_wayG_data_d'length-1), + din => reload_wayG_data_d, + dout => reload_wayG_data_q); +reload_wayH_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_perr_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayH_data_offset to reload_wayH_data_offset + reload_wayH_data_d'length-1), + scout => sov(reload_wayH_data_offset to reload_wayH_data_offset + reload_wayH_data_d'length-1), + din => reload_wayH_data_d, + dout => reload_wayH_data_q); +reload_wayA_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel4_perr_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayA_data2_d, + dout => reload_wayA_data2_q); +reload_wayB_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel4_perr_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayB_data2_d, + dout => reload_wayB_data2_q); +reload_wayC_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel4_perr_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayC_data2_d, + dout => reload_wayC_data2_q); +reload_wayD_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel4_perr_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayD_data2_d, + dout => reload_wayD_data2_q); +reload_wayE_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel4_perr_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayE_data2_d, + dout => reload_wayE_data2_q); +reload_wayF_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel4_perr_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayF_data2_d, + dout => reload_wayF_data2_q); +reload_wayG_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel4_perr_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayG_data2_d, + dout => reload_wayG_data2_q); +reload_wayH_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel4_perr_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayH_data2_d, + dout => reload_wayH_data2_q); +binv_wayA_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayA_upd_offset), + scout => sov(binv_wayA_upd_offset), + din => binv_wayA_upd_d, + dout => binv_wayA_upd_q); +binv_wayB_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayB_upd_offset), + scout => sov(binv_wayB_upd_offset), + din => binv_wayB_upd_d, + dout => binv_wayB_upd_q); +binv_wayC_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayC_upd_offset), + scout => sov(binv_wayC_upd_offset), + din => binv_wayC_upd_d, + dout => binv_wayC_upd_q); +binv_wayD_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayD_upd_offset), + scout => sov(binv_wayD_upd_offset), + din => binv_wayD_upd_d, + dout => binv_wayD_upd_q); +binv_wayE_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayE_upd_offset), + scout => sov(binv_wayE_upd_offset), + din => binv_wayE_upd_d, + dout => binv_wayE_upd_q); +binv_wayF_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayF_upd_offset), + scout => sov(binv_wayF_upd_offset), + din => binv_wayF_upd_d, + dout => binv_wayF_upd_q); +binv_wayG_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayG_upd_offset), + scout => sov(binv_wayG_upd_offset), + din => binv_wayG_upd_d, + dout => binv_wayG_upd_q); +binv_wayH_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayH_upd_offset), + scout => sov(binv_wayH_upd_offset), + din => binv_wayH_upd_d, + dout => binv_wayH_upd_q); +binv_wayA_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayA_upd2_offset), + scout => sov(binv_wayA_upd2_offset), + din => binv_wayA_upd2_d, + dout => binv_wayA_upd2_q); +binv_wayB_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayB_upd2_offset), + scout => sov(binv_wayB_upd2_offset), + din => binv_wayB_upd2_d, + dout => binv_wayB_upd2_q); +binv_wayC_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayC_upd2_offset), + scout => sov(binv_wayC_upd2_offset), + din => binv_wayC_upd2_d, + dout => binv_wayC_upd2_q); +binv_wayD_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayD_upd2_offset), + scout => sov(binv_wayD_upd2_offset), + din => binv_wayD_upd2_d, + dout => binv_wayD_upd2_q); +binv_wayE_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayE_upd2_offset), + scout => sov(binv_wayE_upd2_offset), + din => binv_wayE_upd2_d, + dout => binv_wayE_upd2_q); +binv_wayF_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayF_upd2_offset), + scout => sov(binv_wayF_upd2_offset), + din => binv_wayF_upd2_d, + dout => binv_wayF_upd2_q); +binv_wayG_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayG_upd2_offset), + scout => sov(binv_wayG_upd2_offset), + din => binv_wayG_upd2_d, + dout => binv_wayG_upd2_q); +binv_wayH_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayH_upd2_offset), + scout => sov(binv_wayH_upd2_offset), + din => binv_wayH_upd2_d, + dout => binv_wayH_upd2_q); +binv_wayA_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayA_upd3_offset), + scout => sov(binv_wayA_upd3_offset), + din => binv_wayA_upd3_d, + dout => binv_wayA_upd3_q); +binv_wayB_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayB_upd3_offset), + scout => sov(binv_wayB_upd3_offset), + din => binv_wayB_upd3_d, + dout => binv_wayB_upd3_q); +binv_wayC_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayC_upd3_offset), + scout => sov(binv_wayC_upd3_offset), + din => binv_wayC_upd3_d, + dout => binv_wayC_upd3_q); +binv_wayD_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayD_upd3_offset), + scout => sov(binv_wayD_upd3_offset), + din => binv_wayD_upd3_d, + dout => binv_wayD_upd3_q); +binv_wayE_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayE_upd3_offset), + scout => sov(binv_wayE_upd3_offset), + din => binv_wayE_upd3_d, + dout => binv_wayE_upd3_q); +binv_wayF_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayF_upd3_offset), + scout => sov(binv_wayF_upd3_offset), + din => binv_wayF_upd3_d, + dout => binv_wayF_upd3_q); +binv_wayG_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayG_upd3_offset), + scout => sov(binv_wayG_upd3_offset), + din => binv_wayG_upd3_d, + dout => binv_wayG_upd3_q); +binv_wayH_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayH_upd3_offset), + scout => sov(binv_wayH_upd3_offset), + din => binv_wayH_upd3_d, + dout => binv_wayH_upd3_q); +reload_wayA_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayA_upd_offset), + scout => sov(reload_wayA_upd_offset), + din => reload_wayA_upd_d, + dout => reload_wayA_upd_q); +reload_wayB_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayB_upd_offset), + scout => sov(reload_wayB_upd_offset), + din => reload_wayB_upd_d, + dout => reload_wayB_upd_q); +reload_wayC_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayC_upd_offset), + scout => sov(reload_wayC_upd_offset), + din => reload_wayC_upd_d, + dout => reload_wayC_upd_q); +reload_wayD_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayD_upd_offset), + scout => sov(reload_wayD_upd_offset), + din => reload_wayD_upd_d, + dout => reload_wayD_upd_q); +reload_wayE_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayE_upd_offset), + scout => sov(reload_wayE_upd_offset), + din => reload_wayE_upd_d, + dout => reload_wayE_upd_q); +reload_wayF_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayF_upd_offset), + scout => sov(reload_wayF_upd_offset), + din => reload_wayF_upd_d, + dout => reload_wayF_upd_q); +reload_wayG_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayG_upd_offset), + scout => sov(reload_wayG_upd_offset), + din => reload_wayG_upd_d, + dout => reload_wayG_upd_q); +reload_wayH_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayH_upd_offset), + scout => sov(reload_wayH_upd_offset), + din => reload_wayH_upd_d, + dout => reload_wayH_upd_q); +reload_wayA_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayA_upd2_offset), + scout => sov(reload_wayA_upd2_offset), + din => reload_wayA_upd2_d, + dout => reload_wayA_upd2_q); +reload_wayB_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayB_upd2_offset), + scout => sov(reload_wayB_upd2_offset), + din => reload_wayB_upd2_d, + dout => reload_wayB_upd2_q); +reload_wayC_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayC_upd2_offset), + scout => sov(reload_wayC_upd2_offset), + din => reload_wayC_upd2_d, + dout => reload_wayC_upd2_q); +reload_wayD_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayD_upd2_offset), + scout => sov(reload_wayD_upd2_offset), + din => reload_wayD_upd2_d, + dout => reload_wayD_upd2_q); +reload_wayE_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayE_upd2_offset), + scout => sov(reload_wayE_upd2_offset), + din => reload_wayE_upd2_d, + dout => reload_wayE_upd2_q); +reload_wayF_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayF_upd2_offset), + scout => sov(reload_wayF_upd2_offset), + din => reload_wayF_upd2_d, + dout => reload_wayF_upd2_q); +reload_wayG_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayG_upd2_offset), + scout => sov(reload_wayG_upd2_offset), + din => reload_wayG_upd2_d, + dout => reload_wayG_upd2_q); +reload_wayH_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayH_upd2_offset), + scout => sov(reload_wayH_upd2_offset), + din => reload_wayH_upd2_d, + dout => reload_wayH_upd2_q); +reload_wayA_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayA_upd3_offset), + scout => sov(reload_wayA_upd3_offset), + din => reload_wayA_upd3_d, + dout => reload_wayA_upd3_q); +reload_wayB_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayB_upd3_offset), + scout => sov(reload_wayB_upd3_offset), + din => reload_wayB_upd3_d, + dout => reload_wayB_upd3_q); +reload_wayC_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayC_upd3_offset), + scout => sov(reload_wayC_upd3_offset), + din => reload_wayC_upd3_d, + dout => reload_wayC_upd3_q); +reload_wayD_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayD_upd3_offset), + scout => sov(reload_wayD_upd3_offset), + din => reload_wayD_upd3_d, + dout => reload_wayD_upd3_q); +reload_wayE_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayE_upd3_offset), + scout => sov(reload_wayE_upd3_offset), + din => reload_wayE_upd3_d, + dout => reload_wayE_upd3_q); +reload_wayF_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayF_upd3_offset), + scout => sov(reload_wayF_upd3_offset), + din => reload_wayF_upd3_d, + dout => reload_wayF_upd3_q); +reload_wayG_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayG_upd3_offset), + scout => sov(reload_wayG_upd3_offset), + din => reload_wayG_upd3_d, + dout => reload_wayG_upd3_q); +reload_wayH_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayH_upd3_offset), + scout => sov(reload_wayH_upd3_offset), + din => reload_wayH_upd3_d, + dout => reload_wayH_upd3_q); +ex3_store_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_store_instr_offset), + scout => sov(ex3_store_instr_offset), + din => ex3_store_instr_d, + dout => ex3_store_instr_q); +ex3_lock_set_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_lock_set_offset), + scout => sov(ex3_lock_set_offset), + din => ex3_lock_set_d, + dout => ex3_lock_set_q); +ex4_lock_set_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_lock_set_offset), + scout => sov(ex4_lock_set_offset), + din => ex4_lock_set_d, + dout => ex4_lock_set_q); +ex5_lock_set_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_lock_set_offset), + scout => sov(ex5_lock_set_offset), + din => ex5_lock_set_d, + dout => ex5_lock_set_q); +ex3_lock_clr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_lock_clr_offset), + scout => sov(ex3_lock_clr_offset), + din => ex3_lock_clr_d, + dout => ex3_lock_clr_q); +ex3_xuop_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_xuop_val_offset), + scout => sov(ex3_xuop_val_offset), + din => ex3_xuop_val_d, + dout => ex3_xuop_val_q); +ex4_xuop_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_xuop_val_offset), + scout => sov(ex4_xuop_val_offset), + din => ex4_xuop_val_d, + dout => ex4_xuop_val_q); +ex5_xuop_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_xuop_val_offset), + scout => sov(ex5_xuop_val_offset), + din => ex5_xuop_val_d, + dout => ex5_xuop_val_q); +ex4_l_fld_b1_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex4_l_fld_b1_d, + dout(0) => ex4_l_fld_b1_q); +ex4_instr_enc_reg: tri_regk +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex4_instr_enc_d, + dout => ex4_instr_enc_q); +rel_lock_set_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_lock_set_offset), + scout => sov(rel_lock_set_offset), + din => rel_lock_set_d, + dout => rel_lock_set_q); +dcpar_err_stg1_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dcpar_err_stg1_offset), + scout => sov(dcpar_err_stg1_offset), + din => dcpar_err_stg1_d, + dout => dcpar_err_stg1_q); +dcpar_err_stg2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dcpar_err_stg2_offset), + scout => sov(dcpar_err_stg2_offset), + din => dcpar_err_stg2_d, + dout => dcpar_err_stg2_q); +dcpar_err_way_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dcpar_err_way_offset to dcpar_err_way_offset + dcpar_err_way_d'length-1), + scout => sov(dcpar_err_way_offset to dcpar_err_way_offset + dcpar_err_way_d'length-1), + din => dcpar_err_way_d, + dout => dcpar_err_way_q); +dcpar_err_way_inval_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dcpar_err_way_inval_offset to dcpar_err_way_inval_offset + dcpar_err_way_inval_d'length-1), + scout => sov(dcpar_err_way_inval_offset to dcpar_err_way_inval_offset + dcpar_err_way_inval_d'length-1), + din => dcpar_err_way_inval_d, + dout => dcpar_err_way_inval_q); +dcpar_err_cntr_reg: tri_rlmreg_p +generic map (width => 2, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dcpar_err_cntr_offset to dcpar_err_cntr_offset + dcpar_err_cntr_d'length-1), + scout => sov(dcpar_err_cntr_offset to dcpar_err_cntr_offset + dcpar_err_cntr_d'length-1), + din => dcpar_err_cntr_d, + dout => dcpar_err_cntr_q); +dcpar_err_ind_sel_reg: tri_rlmreg_p +generic map (width => 2, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dcpar_err_ind_sel_offset to dcpar_err_ind_sel_offset + dcpar_err_ind_sel_d'length-1), + scout => sov(dcpar_err_ind_sel_offset to dcpar_err_ind_sel_offset + dcpar_err_ind_sel_d'length-1), + din => dcpar_err_ind_sel_d, + dout => dcpar_err_ind_sel_q); +dcpar_err_push_queue_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dcpar_err_push_queue_offset), + scout => sov(dcpar_err_push_queue_offset), + din => dcpar_err_push_queue_d, + dout => dcpar_err_push_queue_q); +ex4_way_hit_reg: tri_regk +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex4_way_hit_d, + dout => ex4_way_hit_q); +ex5_way_hit_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv4_ex4_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_way_hit_offset to ex5_way_hit_offset + ex5_way_hit_d'length-1), + scout => sov(ex5_way_hit_offset to ex5_way_hit_offset + ex5_way_hit_d'length-1), + din => ex5_way_hit_d, + dout => ex5_way_hit_q); +ex6_way_hit_reg: tri_regk +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex5_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex6_way_hit_d, + dout => ex6_way_hit_q); +ex7_way_hit_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex7_way_hit_offset to ex7_way_hit_offset + ex7_way_hit_d'length-1), + scout => sov(ex7_way_hit_offset to ex7_way_hit_offset + ex7_way_hit_d'length-1), + din => ex7_way_hit_d, + dout => ex7_way_hit_q); +ex8_way_hit_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex8_way_hit_offset to ex8_way_hit_offset + ex8_way_hit_d'length-1), + scout => sov(ex8_way_hit_offset to ex8_way_hit_offset + ex8_way_hit_d'length-1), + din => ex8_way_hit_d, + dout => ex8_way_hit_q); +ex9_way_hit_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex9_way_hit_offset to ex9_way_hit_offset + ex9_way_hit_d'length-1), + scout => sov(ex9_way_hit_offset to ex9_way_hit_offset + ex9_way_hit_d'length-1), + din => ex9_way_hit_d, + dout => ex9_way_hit_q); +ex4_lose_watch_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_lose_watch_offset to ex4_lose_watch_offset + ex4_lose_watch_d'length-1), + scout => sov(ex4_lose_watch_offset to ex4_lose_watch_offset + ex4_lose_watch_d'length-1), + din => ex4_lose_watch_d, + dout => ex4_lose_watch_q); +xucr0_cslc_xuop_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xucr0_cslc_xuop_offset), + scout => sov(xucr0_cslc_xuop_offset), + din => xucr0_cslc_xuop_d, + dout => xucr0_cslc_xuop_q); +xucr0_cslc_binv_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(xucr0_cslc_binv_offset), + scout => sov(xucr0_cslc_binv_offset), + din => xucr0_cslc_binv_d, + dout => xucr0_cslc_binv_q); +dci_compl_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dci_compl_offset), + scout => sov(dci_compl_offset), + din => dci_compl_d, + dout => dci_compl_q); +dci_inval_all_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dci_inval_all_offset), + scout => sov(dci_inval_all_offset), + din => dci_inval_all_d, + dout => dci_inval_all_q); +inv2_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(inv2_val_offset), + scout => sov(inv2_val_offset), + din => inv2_val_d, + dout => inv2_val_q); +perf_lsu_evnts_reg: tri_rlmreg_p +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(perf_lsu_evnts_offset to perf_lsu_evnts_offset + perf_lsu_evnts_d'length-1), + scout => sov(perf_lsu_evnts_offset to perf_lsu_evnts_offset + perf_lsu_evnts_d'length-1), + din => perf_lsu_evnts_d, + dout => perf_lsu_evnts_q); +lock_flash_clear_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(lock_flash_clear_offset), + scout => sov(lock_flash_clear_offset), + din => lock_flash_clear_d, + dout => lock_flash_clear_q); +lock_flash_clear_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(lock_flash_clear_val_offset), + scout => sov(lock_flash_clear_val_offset), + din => lock_flash_clear_val_d, + dout => lock_flash_clear_val_q); +rel_port_wren_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_port_wren_offset), + scout => sov(rel_port_wren_offset), + din => rel_port_wren_d, + dout => rel_port_wren_q); +ex2_thrd_id_reg: tri_regk +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex2_thrd_id_d, + dout => ex2_thrd_id_q); +ex3_thrd_id_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_thrd_id_offset to ex3_thrd_id_offset + ex3_thrd_id_d'length-1), + scout => sov(ex3_thrd_id_offset to ex3_thrd_id_offset + ex3_thrd_id_d'length-1), + din => ex3_thrd_id_d, + dout => ex3_thrd_id_q); +ex4_thrd_id_reg: tri_regk +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex4_thrd_id_d, + dout => ex4_thrd_id_q); +ex5_thrd_id_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_thrd_id_offset to ex5_thrd_id_offset + ex5_thrd_id_d'length-1), + scout => sov(ex5_thrd_id_offset to ex5_thrd_id_offset + ex5_thrd_id_d'length-1), + din => ex5_thrd_id_d, + dout => ex5_thrd_id_q); +ex3_l_fld_b1_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_l_fld_b1_offset), + scout => sov(ex3_l_fld_b1_offset), + din => ex3_l_fld_b1_d, + dout => ex3_l_fld_b1_q); +ex3_watch_set_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_watch_set_offset), + scout => sov(ex3_watch_set_offset), + din => ex3_watch_set_d, + dout => ex3_watch_set_q); +ex4_watch_set_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_watch_set_offset), + scout => sov(ex4_watch_set_offset), + din => ex4_watch_set_d, + dout => ex4_watch_set_q); +ex5_watch_set_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_watch_set_offset), + scout => sov(ex5_watch_set_offset), + din => ex5_watch_set_d, + dout => ex5_watch_set_q); +ex3_watch_clr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_watch_clr_offset), + scout => sov(ex3_watch_clr_offset), + din => ex3_watch_clr_d, + dout => ex3_watch_clr_q); +ex3_watch_clr_all_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_watch_clr_all_offset), + scout => sov(ex3_watch_clr_all_offset), + din => ex3_watch_clr_all_d, + dout => ex3_watch_clr_all_q); +ex3_watch_chk_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_watch_chk_offset), + scout => sov(ex3_watch_chk_offset), + din => ex3_watch_chk_d, + dout => ex3_watch_chk_q); +ex4_watch_chk_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_watch_chk_offset), + scout => sov(ex4_watch_chk_offset), + din => ex4_watch_chk_d, + dout => ex4_watch_chk_q); +ex5_watch_chk_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_watch_chk_offset), + scout => sov(ex5_watch_chk_offset), + din => ex5_watch_chk_d, + dout => ex5_watch_chk_q); +ex3_wclr_all_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wclr_all_upd_offset), + scout => sov(ex3_wclr_all_upd_offset), + din => ex3_wclr_all_upd_d, + dout => ex3_wclr_all_upd_q); +ex4_wclr_all_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_wclr_all_val_offset), + scout => sov(ex4_wclr_all_val_offset), + din => ex4_wclr_all_val_d, + dout => ex4_wclr_all_val_q); +ex5_wclr_all_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_wclr_all_val_offset), + scout => sov(ex5_wclr_all_val_offset), + din => ex5_wclr_all_val_d, + dout => ex5_wclr_all_val_q); +ex6_wclr_all_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_wclr_all_val_offset), + scout => sov(ex6_wclr_all_val_offset), + din => ex6_wclr_all_val_d, + dout => ex6_wclr_all_val_q); +rel_thrd_id_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_thrd_id_offset to rel_thrd_id_offset + rel_thrd_id_d'length-1), + scout => sov(rel_thrd_id_offset to rel_thrd_id_offset + rel_thrd_id_d'length-1), + din => rel_thrd_id_d, + dout => rel_thrd_id_q); +rel_watch_set_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_watch_set_offset), + scout => sov(rel_watch_set_offset), + din => rel_watch_set_d, + dout => rel_watch_set_q); +ex5_cr_watch_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_cr_watch_offset), + scout => sov(ex5_cr_watch_offset), + din => ex5_cr_watch_d, + dout => ex5_cr_watch_q); +ex4_watch_clr_all_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_watch_clr_all_offset to ex4_watch_clr_all_offset + ex4_watch_clr_all_d'length-1), + scout => sov(ex4_watch_clr_all_offset to ex4_watch_clr_all_offset + ex4_watch_clr_all_d'length-1), + din => ex4_watch_clr_all_d, + dout => ex4_watch_clr_all_q); +ex5_watch_clr_all_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_watch_clr_all_offset to ex5_watch_clr_all_offset + ex5_watch_clr_all_d'length-1), + scout => sov(ex5_watch_clr_all_offset to ex5_watch_clr_all_offset + ex5_watch_clr_all_d'length-1), + din => ex5_watch_clr_all_d, + dout => ex5_watch_clr_all_q); +ex6_watch_clr_all_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_watch_clr_all_offset to ex6_watch_clr_all_offset + ex6_watch_clr_all_d'length-1), + scout => sov(ex6_watch_clr_all_offset to ex6_watch_clr_all_offset + ex6_watch_clr_all_d'length-1), + din => ex6_watch_clr_all_d, + dout => ex6_watch_clr_all_q); +ex5_watch_clr_all_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_watch_clr_all_val_offset), + scout => sov(ex5_watch_clr_all_val_offset), + din => ex5_watch_clr_all_val_d, + dout => ex5_watch_clr_all_val_q); +ex5_lost_watch_upd_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_lost_watch_upd_offset to ex5_lost_watch_upd_offset + ex5_lost_watch_upd_d'length-1), + scout => sov(ex5_lost_watch_upd_offset to ex5_lost_watch_upd_offset + ex5_lost_watch_upd_d'length-1), + din => ex5_lost_watch_upd_d, + dout => ex5_lost_watch_upd_q); +ex4_watchlost_set_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_watchlost_set_offset to ex4_watchlost_set_offset + ex4_watchlost_set_d'length-1), + scout => sov(ex4_watchlost_set_offset to ex4_watchlost_set_offset + ex4_watchlost_set_d'length-1), + din => ex4_watchlost_set_d, + dout => ex4_watchlost_set_q); +ex5_watchlost_set_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_watchlost_set_offset to ex5_watchlost_set_offset + ex5_watchlost_set_d'length-1), + scout => sov(ex5_watchlost_set_offset to ex5_watchlost_set_offset + ex5_watchlost_set_d'length-1), + din => ex5_watchlost_set_d, + dout => ex5_watchlost_set_q); +rel_lost_watch_binv_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_lost_watch_binv_offset to rel_lost_watch_binv_offset + rel_lost_watch_binv_d'length-1), + scout => sov(rel_lost_watch_binv_offset to rel_lost_watch_binv_offset + rel_lost_watch_binv_d'length-1), + din => rel_lost_watch_binv_d, + dout => rel_lost_watch_binv_q); +lost_watch_evict_ovl_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(lost_watch_evict_ovl_offset to lost_watch_evict_ovl_offset + lost_watch_evict_ovl_d'length-1), + scout => sov(lost_watch_evict_ovl_offset to lost_watch_evict_ovl_offset + lost_watch_evict_ovl_d'length-1), + din => lost_watch_evict_ovl_d, + dout => lost_watch_evict_ovl_q); +rel_lost_watch_upd_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_lost_watch_upd_offset to rel_lost_watch_upd_offset + rel_lost_watch_upd_d'length-1), + scout => sov(rel_lost_watch_upd_offset to rel_lost_watch_upd_offset + rel_lost_watch_upd_d'length-1), + din => rel_lost_watch_upd_d, + dout => rel_lost_watch_upd_q); +lost_watch_evict_val_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(lost_watch_evict_val_offset to lost_watch_evict_val_offset + lost_watch_evict_val_d'length-1), + scout => sov(lost_watch_evict_val_offset to lost_watch_evict_val_offset + lost_watch_evict_val_d'length-1), + din => lost_watch_evict_val_d, + dout => lost_watch_evict_val_q); +lost_watch_inter_thrd_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(lost_watch_inter_thrd_offset to lost_watch_inter_thrd_offset + lost_watch_inter_thrd_d'length-1), + scout => sov(lost_watch_inter_thrd_offset to lost_watch_inter_thrd_offset + lost_watch_inter_thrd_d'length-1), + din => lost_watch_inter_thrd_d, + dout => lost_watch_inter_thrd_q); +stm_watchlost_state_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(stm_watchlost_state_offset to stm_watchlost_state_offset + stm_watchlost_state_d'length-1), + scout => sov(stm_watchlost_state_offset to stm_watchlost_state_offset + stm_watchlost_state_d'length-1), + din => stm_watchlost_state_d, + dout => stm_watchlost_state_q); +ex5_xuop_p0_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_xuop_p0_upd_offset), + scout => sov(ex5_xuop_p0_upd_offset), + din => ex5_xuop_p0_upd_d, + dout => ex5_xuop_p0_upd_q); +rel_val_stgu_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_val_stgu_offset), + scout => sov(rel_val_stgu_offset), + din => rel_val_stgu_d, + dout => rel_val_stgu_q); +p0_wren_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(p0_wren_offset), + scout => sov(p0_wren_offset), + din => p0_wren_d, + dout => p0_wren_q); +p0_wren_cpy_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(p0_wren_cpy_offset), + scout => sov(p0_wren_cpy_offset), + din => p0_wren_cpy_d, + dout => p0_wren_cpy_q); +p0_wren_stg_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(p0_wren_stg_offset), + scout => sov(p0_wren_stg_offset), + din => p0_wren_stg_d, + dout => p0_wren_stg_q); +p1_wren_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(p1_wren_offset), + scout => sov(p1_wren_offset), + din => p1_wren_d, + dout => p1_wren_q); +p1_wren_cpy_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(p1_wren_cpy_offset), + scout => sov(p1_wren_cpy_offset), + din => p1_wren_cpy_d, + dout => p1_wren_cpy_q); +ex3_thrd_m_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_thrd_m_offset), + scout => sov(ex3_thrd_m_offset), + din => ex3_thrd_m_d, + dout => ex3_thrd_m_q); +ex4_thrd_m_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_thrd_m_offset), + scout => sov(ex4_thrd_m_offset), + din => ex4_thrd_m_d, + dout => ex4_thrd_m_q); +ex5_thrd_m_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_thrd_m_offset), + scout => sov(ex5_thrd_m_offset), + din => ex5_thrd_m_d, + dout => ex5_thrd_m_q); +ex6_thrd_m_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_thrd_m_offset), + scout => sov(ex6_thrd_m_offset), + din => ex6_thrd_m_d, + dout => ex6_thrd_m_q); +ex7_ld_par_err_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex7_ld_par_err_offset), + scout => sov(ex7_ld_par_err_offset), + din => ex7_ld_par_err_d, + dout => ex7_ld_par_err_q); +ex8_ld_par_err_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex8_ld_par_err_offset), + scout => sov(ex8_ld_par_err_offset), + din => ex8_ld_par_err_d, + dout => ex8_ld_par_err_q); +ex9_ld_par_err_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex9_ld_par_err_offset), + scout => sov(ex9_ld_par_err_offset), + din => ex9_ld_par_err_d, + dout => ex9_ld_par_err_q); +ex6_ld_valid_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_ld_valid_offset), + scout => sov(ex6_ld_valid_offset), + din => ex6_ld_valid_d, + dout => ex6_ld_valid_q); +ex7_ld_valid_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex7_ld_valid_offset), + scout => sov(ex7_ld_valid_offset), + din => ex7_ld_valid_d, + dout => ex7_ld_valid_q); +ex8_ld_valid_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex8_ld_valid_offset), + scout => sov(ex8_ld_valid_offset), + din => ex8_ld_valid_d, + dout => ex8_ld_valid_q); +ex9_ld_valid_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex9_ld_valid_offset), + scout => sov(ex9_ld_valid_offset), + din => ex9_ld_valid_d, + dout => ex9_ld_valid_q); +rel_in_progress_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_in_progress_offset), + scout => sov(rel_in_progress_offset), + din => rel_in_progress_d, + dout => rel_in_progress_q); +inj_dir_multihit_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(inj_dir_multihit_offset), + scout => sov(inj_dir_multihit_offset), + din => inj_dir_multihit_d, + dout => inj_dir_multihit_q); +congr_cl_ex2_ex3_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex2_ex3_cmp_offset), + scout => sov(congr_cl_ex2_ex3_cmp_offset), + din => congr_cl_ex2_ex3_cmp_d, + dout => congr_cl_ex2_ex3_cmp_q); +congr_cl_ex2_ex4_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex2_ex4_cmp_offset), + scout => sov(congr_cl_ex2_ex4_cmp_offset), + din => congr_cl_ex2_ex4_cmp_d, + dout => congr_cl_ex2_ex4_cmp_q); +congr_cl_ex2_ex5_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex2_ex5_cmp_offset), + scout => sov(congr_cl_ex2_ex5_cmp_offset), + din => congr_cl_ex2_ex5_cmp_d, + dout => congr_cl_ex2_ex5_cmp_q); +congr_cl_ex2_ex6_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex2_ex6_cmp_offset), + scout => sov(congr_cl_ex2_ex6_cmp_offset), + din => congr_cl_ex2_ex6_cmp_d, + dout => congr_cl_ex2_ex6_cmp_q); +congr_cl_ex3_ex4_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex3_ex4_cmp_offset), + scout => sov(congr_cl_ex3_ex4_cmp_offset), + din => congr_cl_ex3_ex4_cmp_d, + dout => congr_cl_ex3_ex4_cmp_q); +congr_cl_ex3_ex5_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex3_ex5_cmp_offset), + scout => sov(congr_cl_ex3_ex5_cmp_offset), + din => congr_cl_ex3_ex5_cmp_d, + dout => congr_cl_ex3_ex5_cmp_q); +congr_cl_ex3_ex6_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex3_ex6_cmp_offset), + scout => sov(congr_cl_ex3_ex6_cmp_offset), + din => congr_cl_ex3_ex6_cmp_d, + dout => congr_cl_ex3_ex6_cmp_q); +congr_cl_ex4_ex5_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex4_ex5_cmp_offset), + scout => sov(congr_cl_ex4_ex5_cmp_offset), + din => congr_cl_ex4_ex5_cmp_d, + dout => congr_cl_ex4_ex5_cmp_q); +congr_cl_ex4_ex6_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex4_ex6_cmp_offset), + scout => sov(congr_cl_ex4_ex6_cmp_offset), + din => congr_cl_ex4_ex6_cmp_d, + dout => congr_cl_ex4_ex6_cmp_q); +congr_cl_ex4_ex7_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex4_ex7_cmp_offset), + scout => sov(congr_cl_ex4_ex7_cmp_offset), + din => congr_cl_ex4_ex7_cmp_d, + dout => congr_cl_ex4_ex7_cmp_q); +congr_cl_ex2_relu_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex2_relu_cmp_offset), + scout => sov(congr_cl_ex2_relu_cmp_offset), + din => congr_cl_ex2_relu_cmp_d, + dout => congr_cl_ex2_relu_cmp_q); +congr_cl_ex2_relu_s_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex2_relu_s_cmp_offset), + scout => sov(congr_cl_ex2_relu_s_cmp_offset), + din => congr_cl_ex2_relu_s_cmp_d, + dout => congr_cl_ex2_relu_s_cmp_q); +congr_cl_ex2_rel_upd_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex2_rel_upd_cmp_offset), + scout => sov(congr_cl_ex2_rel_upd_cmp_offset), + din => congr_cl_ex2_rel_upd_cmp_d, + dout => congr_cl_ex2_rel_upd_cmp_q); +congr_cl_rel13_ex3_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_rel13_ex3_cmp_offset), + scout => sov(congr_cl_rel13_ex3_cmp_offset), + din => congr_cl_rel13_ex3_cmp_d, + dout => congr_cl_rel13_ex3_cmp_q); +congr_cl_rel13_ex4_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_rel13_ex4_cmp_offset), + scout => sov(congr_cl_rel13_ex4_cmp_offset), + din => congr_cl_rel13_ex4_cmp_d, + dout => congr_cl_rel13_ex4_cmp_q); +congr_cl_rel13_ex5_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_rel13_ex5_cmp_offset), + scout => sov(congr_cl_rel13_ex5_cmp_offset), + din => congr_cl_rel13_ex5_cmp_d, + dout => congr_cl_rel13_ex5_cmp_q); +congr_cl_rel13_ex6_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_rel13_ex6_cmp_offset), + scout => sov(congr_cl_rel13_ex6_cmp_offset), + din => congr_cl_rel13_ex6_cmp_d, + dout => congr_cl_rel13_ex6_cmp_q); +congr_cl_rel13_relu_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_rel13_relu_cmp_offset), + scout => sov(congr_cl_rel13_relu_cmp_offset), + din => congr_cl_rel13_relu_cmp_d, + dout => congr_cl_rel13_relu_cmp_q); +congr_cl_rel13_relu_s_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_rel13_relu_s_cmp_offset), + scout => sov(congr_cl_rel13_relu_s_cmp_offset), + din => congr_cl_rel13_relu_s_cmp_d, + dout => congr_cl_rel13_relu_s_cmp_q); +congr_cl_rel13_rel_upd_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_rel13_rel_upd_cmp_offset), + scout => sov(congr_cl_rel13_rel_upd_cmp_offset), + din => congr_cl_rel13_rel_upd_cmp_d, + dout => congr_cl_rel13_rel_upd_cmp_q); +rel24_congr_cl_ex4_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel24_congr_cl_ex4_cmp_offset), + scout => sov(rel24_congr_cl_ex4_cmp_offset), + din => rel24_congr_cl_ex4_cmp_d, + dout => rel24_congr_cl_ex4_cmp_q); +rel24_congr_cl_ex5_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel24_congr_cl_ex5_cmp_offset), + scout => sov(rel24_congr_cl_ex5_cmp_offset), + din => rel24_congr_cl_ex5_cmp_d, + dout => rel24_congr_cl_ex5_cmp_q); +rel24_congr_cl_ex6_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel24_congr_cl_ex6_cmp_offset), + scout => sov(rel24_congr_cl_ex6_cmp_offset), + din => rel24_congr_cl_ex6_cmp_d, + dout => rel24_congr_cl_ex6_cmp_q); +relu_congr_cl_ex5_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(relu_congr_cl_ex5_cmp_offset), + scout => sov(relu_congr_cl_ex5_cmp_offset), + din => relu_congr_cl_ex5_cmp_d, + dout => relu_congr_cl_ex5_cmp_q); +relu_congr_cl_ex6_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(relu_congr_cl_ex6_cmp_offset), + scout => sov(relu_congr_cl_ex6_cmp_offset), + din => relu_congr_cl_ex6_cmp_d, + dout => relu_congr_cl_ex6_cmp_q); +relu_congr_cl_ex7_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(relu_congr_cl_ex7_cmp_offset), + scout => sov(relu_congr_cl_ex7_cmp_offset), + din => relu_congr_cl_ex7_cmp_d, + dout => relu_congr_cl_ex7_cmp_q); +ex4_err_det_way_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_err_det_way_offset to ex4_err_det_way_offset + ex4_err_det_way_d'length-1), + scout => sov(ex4_err_det_way_offset to ex4_err_det_way_offset + ex4_err_det_way_d'length-1), + din => ex4_err_det_way_d, + dout => ex4_err_det_way_q); +ex4_perr_lck_lost_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_perr_lck_lost_offset), + scout => sov(ex4_perr_lck_lost_offset), + din => ex4_perr_lck_lost_d, + dout => ex4_perr_lck_lost_q); +ex4_perr_watch_lost_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_perr_watch_lost_offset to ex4_perr_watch_lost_offset + ex4_perr_watch_lost_d'length-1), + scout => sov(ex4_perr_watch_lost_offset to ex4_perr_watch_lost_offset + ex4_perr_watch_lost_d'length-1), + din => ex4_perr_watch_lost_d, + dout => ex4_perr_watch_lost_q); +dcperr_lock_lost_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dcperr_lock_lost_offset), + scout => sov(dcperr_lock_lost_offset), + din => dcperr_lock_lost_d, + dout => dcperr_lock_lost_q); +binv7_ex7_way_upd_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv7_ex7_way_upd_offset to binv7_ex7_way_upd_offset + binv7_ex7_way_upd_d'length-1), + scout => sov(binv7_ex7_way_upd_offset to binv7_ex7_way_upd_offset + binv7_ex7_way_upd_d'length-1), + din => binv7_ex7_way_upd_d, + dout => binv7_ex7_way_upd_q); +binv5_ex5_dir_data_reg: tri_rlmreg_p +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv4_ex4_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv5_ex5_dir_data_offset to binv5_ex5_dir_data_offset + binv5_ex5_dir_data_d'length-1), + scout => sov(binv5_ex5_dir_data_offset to binv5_ex5_dir_data_offset + binv5_ex5_dir_data_d'length-1), + din => binv5_ex5_dir_data_d, + dout => binv5_ex5_dir_data_q); +binv6_ex6_dir_data_reg: tri_regk +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv5_ex5_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => binv6_ex6_dir_data_d, + dout => binv6_ex6_dir_data_q); +binv7_ex7_dir_data_reg: tri_rlmreg_p +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv7_ex7_dir_data_offset to binv7_ex7_dir_data_offset + binv7_ex7_dir_data_d'length-1), + scout => sov(binv7_ex7_dir_data_offset to binv7_ex7_dir_data_offset + binv7_ex7_dir_data_d'length-1), + din => binv7_ex7_dir_data_d, + dout => binv7_ex7_dir_data_q); +binv5_inval_watch_val_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv5_inval_watch_val_offset to binv5_inval_watch_val_offset + binv5_inval_watch_val_d'length-1), + scout => sov(binv5_inval_watch_val_offset to binv5_inval_watch_val_offset + binv5_inval_watch_val_d'length-1), + din => binv5_inval_watch_val_d, + dout => binv5_inval_watch_val_q); +binv5_inval_lock_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv5_inval_lock_val_offset), + scout => sov(binv5_inval_lock_val_offset), + din => binv5_inval_lock_val_d, + dout => binv5_inval_lock_val_q); +my_lcb : entity tri.tri_lcbnd(tri_lcbnd) +generic map (expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + d1clk => my_d1clk, + d2clk => my_d2clk, + lclk => my_lclk); +ex4_snd_ld_l2_reg: entity tri.tri_oai22_nlats(tri_oai22_nlats) +generic map (width => 1, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + lclk => my_lclk, + d1clk => my_d1clk, + d2clk => my_d2clk, + scanin(0) => siv(ex4_snd_ld_l2_offset), + scanout(0) => sov(ex4_snd_ld_l2_offset), + a1(0) => ex3_wimge_i_bit, + a2(0) => hit_or_01234567_b, + b1(0) => ex3_load_val, + b2(0) => ex3_load_val, + qb(0) => ex4_snd_ld_l2_q); +ex4_ldq_full_flush_b_reg: entity tri.tri_oai22_nlats(tri_oai22_nlats) +generic map (width => 1, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + lclk => my_lclk, + d1clk => my_d1clk, + d2clk => my_d2clk, + scanin(0) => siv(ex4_ldq_full_flush_b_offset), + scanout(0) => sov(ex4_ldq_full_flush_b_offset), + a1(0) => ex3_l2_request, + a2(0) => hit_or_01234567_b, + b1(0) => ex3_ldq_potential_flush, + b2(0) => ex3_ldq_potential_flush, + qb(0) => ex4_ldq_full_flush_b_q); +ex4_miss_reg: entity tri.tri_inv_nlats(tri_inv_nlats) +generic map (width => 1, init => "1", expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + lclk => my_lclk, + d1clk => my_d1clk, + d2clk => my_d2clk, + scanin(0) => ex4_miss_siv, + scanout(0) => ex4_miss_sov, + d(0) => ex3_l1miss, + qb(0) => ex4_miss_q); +ex4_miss_siv <= not siv(ex4_miss_offset); +sov(ex4_miss_offset) <= not ex4_miss_sov; +my_spare0_lcb : entity tri.tri_lcbnd(tri_lcbnd) +generic map (expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + d1clk => my_spare0_d1clk, + d2clk => my_spare0_d2clk, + lclk => my_spare0_lclk); +my_spare0_latches_reg: entity tri.tri_inv_nlats(tri_inv_nlats) +generic map (width => 17, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + lclk => my_spare0_lclk, + d1clk => my_spare0_d1clk, + d2clk => my_spare0_d2clk, + scanin => siv(my_spare0_latches_offset to my_spare0_latches_offset + my_spare0_latches_d'length-1), + scanout => sov(my_spare0_latches_offset to my_spare0_latches_offset + my_spare0_latches_d'length-1), + d => my_spare0_latches_d, + qb => my_spare0_latches_q); +my_spare1_lcb : entity tri.tri_lcbnd(tri_lcbnd) +generic map (expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + d1clk => my_spare1_d1clk, + d2clk => my_spare1_d2clk, + lclk => my_spare1_lclk); +my_spare1_latches_reg: entity tri.tri_inv_nlats(tri_inv_nlats) +generic map (width => 16, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + lclk => my_spare1_lclk, + d1clk => my_spare1_d1clk, + d2clk => my_spare1_d2clk, + scanin => siv(my_spare1_latches_offset to my_spare1_latches_offset + my_spare1_latches_d'length-1), + scanout => sov(my_spare1_latches_offset to my_spare1_latches_offset + my_spare1_latches_d'length-1), + d => my_spare1_latches_d, + qb => my_spare1_latches_q); +rel_l1dump_cslc_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_l1dump_cslc_offset), + scout => sov(rel_l1dump_cslc_offset), + din => rel_l1dump_cslc_d, + dout => rel_l1dump_cslc_q); +rel_in_prog_stg1_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_in_prog_stg1_offset), + scout => sov(rel_in_prog_stg1_offset), + din => rel_in_prog_stg1_d, + dout => rel_in_prog_stg1_q); +rel_in_prog_stg2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_in_prog_stg2_offset), + scout => sov(rel_in_prog_stg2_offset), + din => rel_in_prog_stg2_d, + dout => rel_in_prog_stg2_q); +rel_in_prog_stg3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_in_prog_stg3_offset), + scout => sov(rel_in_prog_stg3_offset), + din => rel_in_prog_stg3_d, + dout => rel_in_prog_stg3_q); +rel_in_prog_stg4_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_in_prog_stg4_offset), + scout => sov(rel_in_prog_stg4_offset), + din => rel_in_prog_stg4_d, + dout => rel_in_prog_stg4_q); +rel_in_prog_stg5_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_in_prog_stg5_offset), + scout => sov(rel_in_prog_stg5_offset), + din => rel_in_prog_stg5_d, + dout => rel_in_prog_stg5_q); +dcpar_err_stg1_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dcpar_err_stg1_act_offset), + scout => sov(dcpar_err_stg1_act_offset), + din => dcpar_err_stg1_act_d, + dout => dcpar_err_stg1_act_q); +dcpar_err_stg2_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dcpar_err_stg2_act_offset), + scout => sov(dcpar_err_stg2_act_offset), + din => dcpar_err_stg2_act_d, + dout => dcpar_err_stg2_act_q); +rel3_perr_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel3_perr_stg_act_offset), + scout => sov(rel3_perr_stg_act_offset), + din => rel3_perr_stg_act_d, + dout => rel3_perr_stg_act_q); +rel4_perr_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel4_perr_stg_act_offset), + scout => sov(rel4_perr_stg_act_offset), + din => rel4_perr_stg_act_d, + dout => rel4_perr_stg_act_q); +siv(0 TO 1247) <= sov(1 to 1247) & scan_in(0); +scan_out(0) <= sov(0); +siv(1248 TO scan_right) <= sov(1249 to scan_right) & scan_in(1); +scan_out(1) <= sov(1248); +scan_out(2) <= scan_in(2); +END XUQ_LSU_DIR_VAL32; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_fgen.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_fgen.vhdl new file mode 100644 index 0000000..635909d --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_fgen.vhdl @@ -0,0 +1,920 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ibm, ieee, work, tri, support; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use tri.tri_latches_pkg.all; +use support.power_logic_pkg.all; + + +entity xuq_lsu_fgen is +generic(expand_type : integer := 2; + real_data_add : integer := 42); +port( + + ex2_cache_acc :in std_ulogic; + ex2_ldst_fexcpt :in std_ulogic; + ex2_mv_reg_op :in std_ulogic; + ex2_axu_op :in std_ulogic; + rf1_thrd_id :in std_ulogic_vector(0 to 3); + ex1_thrd_id :in std_ulogic_vector(0 to 3); + ex2_thrd_id :in std_ulogic_vector(0 to 3); + ex3_thrd_id :in std_ulogic_vector(0 to 3); + ex4_thrd_id :in std_ulogic_vector(0 to 3); + ex5_thrd_id :in std_ulogic_vector(0 to 3); + ex2_optype32 :in std_ulogic; + ex2_optype16 :in std_ulogic; + ex2_optype8 :in std_ulogic; + ex2_optype4 :in std_ulogic; + ex2_optype2 :in std_ulogic; + ex2_p_addr_lwr :in std_ulogic_vector(57 to 63); + ex2_icswx_type :in std_ulogic; + ex2_store_instr :in std_ulogic; + ex2_load_instr :in std_ulogic; + ex2_dcbz_instr :in std_ulogic; + ex2_lock_instr :in std_ulogic; + ex2_ldawx_instr :in std_ulogic; + ex2_lm_dep_hit :in std_ulogic; + ex3_lsq_flush :in std_ulogic; + derat_xu_ex3_noop_touch :in std_ulogic_vector(0 to 3); + ex3_wimge_w_bit :in std_ulogic; + ex3_wimge_i_bit :in std_ulogic; + ex3_targ_match_b1 :in std_ulogic; + ex2_targ_match_b2 :in std_ulogic; + + ex3_cClass_collision :in std_ulogic; + ex2_lockwatchSet_rel_coll :in std_ulogic; + ex3_wclr_all_flush :in std_ulogic; + + xu_lsu_spr_xucr0_aflsta :in std_ulogic; + xu_lsu_spr_xucr0_flsta :in std_ulogic; + xu_lsu_spr_xucr0_l2siw :in std_ulogic; + + ldq_rel_ci :in std_ulogic; + ldq_rel_axu_val :in std_ulogic; + + xu_lsu_rf1_flush :in std_ulogic_vector(0 to 3); + xu_lsu_ex1_flush :in std_ulogic_vector(0 to 3); + xu_lsu_ex2_flush :in std_ulogic_vector(0 to 3); + xu_lsu_ex3_flush :in std_ulogic_vector(0 to 3); + xu_lsu_ex4_flush :in std_ulogic_vector(0 to 3); + xu_lsu_ex5_flush :in std_ulogic_vector(0 to 3); + + rf1_stg_flush :out std_ulogic; + ex1_stg_flush :out std_ulogic; + ex2_stg_flush :out std_ulogic; + ex3_stg_flush :out std_ulogic; + ex4_stg_flush :out std_ulogic; + ex5_stg_flush :out std_ulogic; + ex3_excp_det :out std_ulogic; + lsu_xu_ex3_dep_flush :out std_ulogic; + lsu_xu_ex3_n_flush_req :out std_ulogic; + + lsu_xu_perf_events :out std_ulogic_vector(0 to 3); + + lsu_xu_ex3_align :out std_ulogic_vector(0 to 3); + lsu_xu_ex3_dsi :out std_ulogic_vector(0 to 3); + lsu_xu_ex3_inval_align_2ucode :out std_ulogic; + + dc_fgen_dbg_data :out std_ulogic_vector(0 to 1); + + vdd :inout power_logic; + gnd :inout power_logic; + nclk :in clk_logic; + sg_0 :in std_ulogic; + func_sl_thold_0_b :in std_ulogic; + func_sl_force :in std_ulogic; + func_nsl_thold_0_b :in std_ulogic; + func_nsl_force :in std_ulogic; + d_mode_dc :in std_ulogic; + delay_lclkr_dc :in std_ulogic; + mpw1_dc_b :in std_ulogic; + mpw2_dc_b :in std_ulogic; + scan_in :in std_ulogic; + scan_out :out std_ulogic +); +-- synopsys translate_off +-- synopsys translate_on +end xuq_lsu_fgen; +architecture xuq_lsu_fgen of xuq_lsu_fgen is + + + +constant ex3_flush_cond_offset :natural := 0; +constant ex3_valid_lock_offset :natural := ex3_flush_cond_offset + 1; +constant ex3_prealign_int_offset :natural := ex3_valid_lock_offset + 1; +constant ex3_prealign_int_ld_offset :natural := ex3_prealign_int_offset + 1; +constant ex3_preflush_2ucode_offset :natural := ex3_prealign_int_ld_offset + 1; +constant ex3_preflush_2ucode_ld_offset :natural := ex3_preflush_2ucode_offset + 1; +constant rel_is_ci_offset :natural := ex3_preflush_2ucode_ld_offset + 1; +constant rel_is_axu_offset :natural := rel_is_ci_offset + 1; +constant ex3_is_dcbz_offset :natural := rel_is_axu_offset + 1; +constant ex5_misalign_flush_offset :natural := ex3_is_dcbz_offset + 1; +constant spr_xucr0_aflsta_offset :natural := ex5_misalign_flush_offset + 1; +constant spr_xucr0_flsta_offset :natural := spr_xucr0_aflsta_offset + 1; +constant spr_xucr0_l2siw_offset :natural := spr_xucr0_flsta_offset + 1; +constant ex3_dep_flush_offset :natural := spr_xucr0_l2siw_offset + 1; +constant ex5_dep_flush_offset :natural := ex3_dep_flush_offset + 1; +constant ex3_rel_collision_offset :natural := ex5_dep_flush_offset + 1; +constant ex5_rel_collision_offset :natural := ex3_rel_collision_offset + 1; +constant ex5_cClass_collision_offset :natural := ex5_rel_collision_offset + 1; +constant scan_right :natural := ex5_cClass_collision_offset + 1 - 1; + +signal optype32 :std_ulogic; +signal optype16 :std_ulogic; +signal optype8 :std_ulogic; +signal optype4 :std_ulogic; +signal optype2 :std_ulogic; +signal ex2_32Bop32_unal :std_ulogic; +signal ex2_32Bop16_unal :std_ulogic; +signal ex2_32Bop8_unal :std_ulogic; +signal ex2_32Bop4_unal :std_ulogic; +signal ex2_32Bop2_unal :std_ulogic; +signal ex2_32Bunal_op :std_ulogic; +signal ex2_32Bop16_unal_ld :std_ulogic; +signal ex2_32Bop8_unal_ld :std_ulogic; +signal ex2_32Bop4_unal_ld :std_ulogic; +signal ex2_32Bop2_unal_ld :std_ulogic; +signal ex2_unal_ld_op :std_ulogic; +signal ex2_is_store :std_ulogic; +signal ex2_is_load :std_ulogic; +signal ex2_phy_addr :std_ulogic_vector(57 to 63); +signal rf1_th_id :std_ulogic_vector(0 to 3); +signal ex1_th_id :std_ulogic_vector(0 to 3); +signal ex2_th_id :std_ulogic_vector(0 to 3); +signal ex3_th_id :std_ulogic_vector(0 to 3); +signal ex4_th_id :std_ulogic_vector(0 to 3); +signal ex5_th_id :std_ulogic_vector(0 to 3); +signal ex2_is_lock :std_ulogic; +signal wt_ci_trans :std_ulogic; +signal ex2_valid_lock :std_ulogic; +signal rf1_if_flush_val :std_ulogic; +signal ex1_if_flush_val :std_ulogic; +signal ex2_if_flush_val :std_ulogic; +signal ex3_if_flush_val :std_ulogic; +signal ex4_if_flush_val :std_ulogic; +signal ex5_if_flush_val :std_ulogic; +signal ex3_flush_cond_d :std_ulogic; +signal ex3_flush_cond_q :std_ulogic; +signal ex2_rel_val_flush :std_ulogic; +signal ex2_rel_collision :std_ulogic; +signal ex3_rel_collision_d :std_ulogic; +signal ex3_rel_collision_q :std_ulogic; +signal ex4_rel_collision_d :std_ulogic; +signal ex4_rel_collision_q :std_ulogic; +signal ex5_rel_collision_d :std_ulogic; +signal ex5_rel_collision_q :std_ulogic; +signal ex6_rel_collision_d :std_ulogic; +signal ex6_rel_collision_q :std_ulogic; +signal ex2_is_dcbz :std_ulogic; +signal ex3_valid_lock_d :std_ulogic; +signal ex3_valid_lock_q :std_ulogic; +signal ex3_prealign_int_d :std_ulogic; +signal ex3_prealign_int_q :std_ulogic; +signal ex3_prealign_int_ld_d :std_ulogic; +signal ex3_prealign_int_ld_q :std_ulogic; +signal force_align_int :std_ulogic; +signal ex3_flush_2ucode :std_ulogic; +signal ex3_preflush_2ucode_d :std_ulogic; +signal ex3_preflush_2ucode_q :std_ulogic; +signal ex3_preflush_2ucode_ld_d :std_ulogic; +signal ex3_preflush_2ucode_ld_q :std_ulogic; +signal interface_16B :std_ulogic; +signal ex2_waw_haz :std_ulogic; +signal ex2_raw_haz :std_ulogic; +signal force_align_int_a :std_ulogic; +signal force_align_int_x :std_ulogic; +signal ex2_op32_unal :std_ulogic; +signal ex2_op16_unal :std_ulogic; +signal ex2_op8_unal :std_ulogic; +signal ex2_op4_unal :std_ulogic; +signal ex2_op2_unal :std_ulogic; +signal ex2_unal_op :std_ulogic; +signal ex3_resrc_collision :std_ulogic; +signal ex3_dir_collision :std_ulogic; +signal rel_is_ci_d :std_ulogic; +signal rel_is_ci_q :std_ulogic; +signal rel_is_axu_d :std_ulogic; +signal rel_is_axu_q :std_ulogic; +signal rel_ci_st_collision :std_ulogic; +signal rel_ci_ld_collision :std_ulogic; +signal ex4_misalign_flush_d :std_ulogic; +signal ex4_misalign_flush_q :std_ulogic; +signal ex5_misalign_flush_d :std_ulogic; +signal ex5_misalign_flush_q :std_ulogic; +signal ex6_misalign_flush_d :std_ulogic; +signal ex6_misalign_flush_q :std_ulogic; +signal spr_xucr0_aflsta_d :std_ulogic; +signal spr_xucr0_aflsta_q :std_ulogic; +signal spr_xucr0_flsta_d :std_ulogic; +signal spr_xucr0_flsta_q :std_ulogic; +signal spr_xucr0_l2siw_d :std_ulogic; +signal spr_xucr0_l2siw_q :std_ulogic; +signal ex3_noop_touch :std_ulogic; +signal ex3_dep_flush :std_ulogic; +signal ex3_dep_flush_d :std_ulogic; +signal ex3_dep_flush_q :std_ulogic; +signal ex4_dep_flush_d :std_ulogic; +signal ex4_dep_flush_q :std_ulogic; +signal ex5_dep_flush_d :std_ulogic; +signal ex5_dep_flush_q :std_ulogic; +signal ex6_dep_flush_d :std_ulogic; +signal ex6_dep_flush_q :std_ulogic; +signal ex3_n_flush_rq_b :std_ulogic; +signal ex3_n_flush_rq :std_ulogic; +signal ex4_n_flush_rq_d :std_ulogic; +signal ex4_n_flush_rq_q :std_ulogic; +signal ex2_icswx_unal :std_ulogic; +signal ex3_is_dcbz_d :std_ulogic; +signal ex3_is_dcbz_q :std_ulogic; +signal ex3_dsi_int :std_ulogic; +signal ex3_align_int :std_ulogic; +signal ex3_dcbz_err :std_ulogic; +signal ex2_store_cross :std_ulogic; +signal ex4_cClass_collision_d :std_ulogic; +signal ex4_cClass_collision_q :std_ulogic; +signal ex5_cClass_collision_d :std_ulogic; +signal ex5_cClass_collision_q :std_ulogic; +signal ex6_cClass_collision_d :std_ulogic; +signal ex6_cClass_collision_q :std_ulogic; +signal ex3_n_flush_oth1_b :std_ulogic; +signal ex3_n_flush_oth1 :std_ulogic; + +signal tiup :std_ulogic; +signal siv :std_ulogic_vector(0 to scan_right); +signal sov :std_ulogic_vector(0 to scan_right); + + + +begin + +tiup <= '1'; + +ex3_noop_touch <= or_reduce(derat_xu_ex3_noop_touch); +ex2_phy_addr <= ex2_p_addr_lwr; + +optype32 <= ex2_optype32; +optype16 <= ex2_optype16; +optype8 <= ex2_optype8; +optype4 <= ex2_optype4; +optype2 <= ex2_optype2; + +ex2_is_load <= ex2_load_instr; +ex2_is_store <= ex2_store_instr; +ex2_is_dcbz <= ex2_dcbz_instr; +ex2_is_lock <= ex2_lock_instr; +ex3_is_dcbz_d <= ex2_is_dcbz and ex2_cache_acc and not ex2_if_flush_val; + +rf1_th_id <= rf1_thrd_id; +ex1_th_id <= ex1_thrd_id; +ex2_th_id <= ex2_thrd_id; +ex3_th_id <= ex3_thrd_id; +ex4_th_id <= ex4_thrd_id; +ex5_th_id <= ex5_thrd_id; + +ex2_waw_haz <= ex2_targ_match_b2; +ex2_raw_haz <= ex2_lm_dep_hit; + +rel_is_ci_d <= ldq_rel_ci; +rel_is_axu_d <= ldq_rel_axu_val; +rel_ci_st_collision <= rel_is_ci_q and (((ex2_is_store or ex2_icswx_type) and ex2_cache_acc) or ex2_mv_reg_op); +rel_ci_ld_collision <= rel_is_ci_q and rel_is_axu_q and ex2_is_load and ex2_axu_op and ex2_cache_acc; + +spr_xucr0_aflsta_d <= xu_lsu_spr_xucr0_aflsta; +spr_xucr0_flsta_d <= xu_lsu_spr_xucr0_flsta; +spr_xucr0_l2siw_d <= xu_lsu_spr_xucr0_l2siw; + +force_align_int_a <= ex2_cache_acc and ex2_axu_op and (spr_xucr0_aflsta_q or ex2_ldst_fexcpt); +force_align_int_x <= ex2_cache_acc and not ex2_axu_op and spr_xucr0_flsta_q; +force_align_int <= force_align_int_x or force_align_int_a or ex2_is_lock or ex2_ldawx_instr; + +interface_16B <= not spr_xucr0_l2siw_q; + + +wt_ci_trans <= ex3_wimge_w_bit or ex3_wimge_i_bit; + + +ex2_op32_unal <= optype32 and (ex2_phy_addr(59) or ex2_phy_addr(60) or ex2_phy_addr(61) or ex2_phy_addr(62) or ex2_phy_addr(63)); +ex2_op16_unal <= optype16 and (ex2_phy_addr(60) or ex2_phy_addr(61) or ex2_phy_addr(62) or ex2_phy_addr(63)); +ex2_op8_unal <= optype8 and (ex2_phy_addr(61) or ex2_phy_addr(62) or ex2_phy_addr(63)); +ex2_op4_unal <= optype4 and (ex2_phy_addr(62) or ex2_phy_addr(63)); +ex2_op2_unal <= optype2 and ex2_phy_addr(63); +ex2_unal_op <= ex2_op32_unal or ex2_op16_unal or ex2_op8_unal or ex2_op4_unal or ex2_op2_unal; + +ex2_icswx_unal <= ex2_icswx_type and or_reduce(ex2_phy_addr); + +ex2_store_cross <= interface_16B and ex2_is_store; + +ex2_32Bop32_unal <= optype32 and (ex2_phy_addr(59) or ex2_phy_addr(60) or ex2_phy_addr(61) or ex2_phy_addr(62) or ex2_phy_addr(63)); +ex2_32Bop16_unal <= optype16 and (ex2_store_cross or ex2_phy_addr(59)) and (ex2_phy_addr(60) or ex2_phy_addr(61) or ex2_phy_addr(62) or ex2_phy_addr(63)); +ex2_32Bop8_unal <= optype8 and (ex2_store_cross or ex2_phy_addr(59)) and ex2_phy_addr(60) and (ex2_phy_addr(61) or ex2_phy_addr(62) or ex2_phy_addr(63)); +ex2_32Bop4_unal <= optype4 and (ex2_store_cross or ex2_phy_addr(59)) and ex2_phy_addr(60) and ex2_phy_addr(61) and (ex2_phy_addr(62) or ex2_phy_addr(63)); +ex2_32Bop2_unal <= optype2 and (ex2_store_cross or ex2_phy_addr(59)) and ex2_phy_addr(60) and ex2_phy_addr(61) and ex2_phy_addr(62) and ex2_phy_addr(63); +ex2_32Bunal_op <= ex2_32Bop32_unal or ex2_32Bop16_unal or ex2_32Bop8_unal or ex2_32Bop4_unal or ex2_32Bop2_unal; + +ex2_32Bop16_unal_ld <= optype16 and ex2_is_load and (ex2_phy_addr(60) or ex2_phy_addr(61) or ex2_phy_addr(62) or ex2_phy_addr(63)); +ex2_32Bop8_unal_ld <= optype8 and ex2_is_load and ex2_phy_addr(60) and (ex2_phy_addr(61) or ex2_phy_addr(62) or ex2_phy_addr(63)); +ex2_32Bop4_unal_ld <= optype4 and ex2_is_load and ex2_phy_addr(60) and ex2_phy_addr(61) and (ex2_phy_addr(62) or ex2_phy_addr(63)); +ex2_32Bop2_unal_ld <= optype2 and ex2_is_load and ex2_phy_addr(60) and ex2_phy_addr(61) and ex2_phy_addr(62) and ex2_phy_addr(63); +ex2_unal_ld_op <= ex2_32Bop16_unal_ld or ex2_32Bop8_unal_ld or ex2_32Bop4_unal_ld or ex2_32Bop2_unal_ld; + +ex3_preflush_2ucode_d <= (not (ex2_is_lock or ex2_ldawx_instr or ex2_icswx_type)) and ex2_32Bunal_op and ex2_cache_acc and not ex2_if_flush_val; +ex3_preflush_2ucode_ld_d <= (not (ex2_is_lock or ex2_ldawx_instr or ex2_icswx_type)) and ex2_unal_ld_op and ex2_cache_acc and not ex2_if_flush_val; +ex3_flush_2ucode <= ex3_preflush_2ucode_q or (ex3_preflush_2ucode_ld_q and ex3_wimge_i_bit); + +ex3_prealign_int_d <= (ex2_icswx_unal or (force_align_int and (ex2_unal_op or ex2_32Bunal_op))) and ex2_cache_acc and not ex2_if_flush_val; +ex3_prealign_int_ld_d <= force_align_int and ex2_unal_ld_op and ex2_cache_acc and not ex2_if_flush_val; + +ex3_dcbz_err <= ex3_is_dcbz_q and wt_ci_trans; +ex3_align_int <= ex3_prealign_int_q or (ex3_prealign_int_ld_q and ex3_wimge_i_bit) or ex3_dcbz_err; + +ex4_misalign_flush_d <= ex3_flush_2ucode or ex3_prealign_int_q or (ex3_prealign_int_ld_q and ex3_wimge_i_bit); +ex5_misalign_flush_d <= ex4_misalign_flush_q; +ex6_misalign_flush_d <= ex5_misalign_flush_q; + + + +ex2_valid_lock <= ex2_is_lock and ex2_cache_acc and not ex2_if_flush_val; + +ex3_valid_lock_d <= ex2_valid_lock; +ex3_dsi_int <= ex3_valid_lock_q and wt_ci_trans; + +ex3_dep_flush_d <= (ex2_raw_haz or ex2_waw_haz) and not ex2_if_flush_val; +ex3_dep_flush <= ex3_dep_flush_q or ex3_targ_match_b1; +ex4_dep_flush_d <= ex3_dep_flush; +ex5_dep_flush_d <= ex4_dep_flush_q; +ex6_dep_flush_d <= ex5_dep_flush_q; + +ex3_excp_det <= ex3_noop_touch; + + +rf1_if_flush_val <= (xu_lsu_rf1_flush(0) and rf1_th_id(0)) or + (xu_lsu_rf1_flush(1) and rf1_th_id(1)) or + (xu_lsu_rf1_flush(2) and rf1_th_id(2)) or + (xu_lsu_rf1_flush(3) and rf1_th_id(3)); + +ex1_if_flush_val <= (xu_lsu_ex1_flush(0) and ex1_th_id(0)) or + (xu_lsu_ex1_flush(1) and ex1_th_id(1)) or + (xu_lsu_ex1_flush(2) and ex1_th_id(2)) or + (xu_lsu_ex1_flush(3) and ex1_th_id(3)); + +ex2_if_flush_val <= (xu_lsu_ex2_flush(0) and ex2_th_id(0)) or + (xu_lsu_ex2_flush(1) and ex2_th_id(1)) or + (xu_lsu_ex2_flush(2) and ex2_th_id(2)) or + (xu_lsu_ex2_flush(3) and ex2_th_id(3)); + +ex3_if_flush_val <= (xu_lsu_ex3_flush(0) and ex3_th_id(0)) or + (xu_lsu_ex3_flush(1) and ex3_th_id(1)) or + (xu_lsu_ex3_flush(2) and ex3_th_id(2)) or + (xu_lsu_ex3_flush(3) and ex3_th_id(3)); + +ex4_if_flush_val <= (xu_lsu_ex4_flush(0) and ex4_th_id(0)) or + (xu_lsu_ex4_flush(1) and ex4_th_id(1)) or + (xu_lsu_ex4_flush(2) and ex4_th_id(2)) or + (xu_lsu_ex4_flush(3) and ex4_th_id(3)); + +ex5_if_flush_val <= (xu_lsu_ex5_flush(0) and ex5_th_id(0)) or + (xu_lsu_ex5_flush(1) and ex5_th_id(1)) or + (xu_lsu_ex5_flush(2) and ex5_th_id(2)) or + (xu_lsu_ex5_flush(3) and ex5_th_id(3)); + +ex2_rel_val_flush <= rel_ci_st_collision or rel_ci_ld_collision or ex2_lockwatchSet_rel_coll; +ex2_rel_collision <= ex2_rel_val_flush and not ex2_if_flush_val; +ex3_rel_collision_d <= ex2_rel_collision; +ex4_rel_collision_d <= ex3_rel_collision_q; +ex5_rel_collision_d <= ex4_rel_collision_q; +ex6_rel_collision_d <= ex5_rel_collision_q; + + +rf1_stg_flush <= rf1_if_flush_val; + +ex1_stg_flush <= ex1_if_flush_val; + +ex2_stg_flush <= ex2_if_flush_val; + +ex3_flush_cond_d <= ex2_rel_collision; +ex3_resrc_collision <= ex3_flush_cond_q; +ex3_dir_collision <= ex3_cClass_collision or ex3_wclr_all_flush; +ex4_cClass_collision_d <= ex3_dir_collision; +ex5_cClass_collision_d <= ex4_cClass_collision_q; +ex6_cClass_collision_d <= ex5_cClass_collision_q; + +ex3NFlushoth1B: ex3_n_flush_oth1_b <= not (ex3_resrc_collision or ex3_lsq_flush); +ex3NFlushoth1: ex3_n_flush_oth1 <= not ex3_n_flush_oth1_b; +ex3NFlushRqB: ex3_n_flush_rq_b <= not (ex3_n_flush_oth1 or ex3_dir_collision); +ex3NFlushRq: ex3_n_flush_rq <= not ex3_n_flush_rq_b; + +ex4_n_flush_rq_d <= ex3_n_flush_rq; + +ex3_stg_flush <= ex3_if_flush_val; + +lsu_xu_ex3_n_flush_req <= ex3_n_flush_rq; +lsu_xu_ex3_inval_align_2ucode <= ex3_flush_2ucode and not ex3_flush_cond_q; +lsu_xu_ex3_dep_flush <= ex3_dep_flush; +lsu_xu_ex3_dsi <= gate(ex3_th_id, ex3_dsi_int); +lsu_xu_ex3_align <= gate(ex3_th_id, ex3_align_int); + +dc_fgen_dbg_data <= rel_is_ci_q & ex4_n_flush_rq_q; + +lsu_xu_perf_events <= ex6_misalign_flush_q & ex6_rel_collision_q & + ex6_cClass_collision_q & ex6_dep_flush_q; + +ex4_stg_flush <= ex4_if_flush_val; + +ex5_stg_flush <= ex5_if_flush_val; + + +ex3_flush_cond_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_flush_cond_offset), + scout => sov(ex3_flush_cond_offset), + din => ex3_flush_cond_d, + dout => ex3_flush_cond_q); + +ex4_n_flush_rq_reg: tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex4_n_flush_rq_d, + dout(0) => ex4_n_flush_rq_q); + +ex3_valid_lock_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_valid_lock_offset), + scout => sov(ex3_valid_lock_offset), + din => ex3_valid_lock_d, + dout => ex3_valid_lock_q); + +ex3_prealign_int_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_prealign_int_offset), + scout => sov(ex3_prealign_int_offset), + din => ex3_prealign_int_d, + dout => ex3_prealign_int_q); + +ex3_prealign_int_ld_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_prealign_int_ld_offset), + scout => sov(ex3_prealign_int_ld_offset), + din => ex3_prealign_int_ld_d, + dout => ex3_prealign_int_ld_q); + +ex3_preflush_2ucode_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_preflush_2ucode_offset), + scout => sov(ex3_preflush_2ucode_offset), + din => ex3_preflush_2ucode_d, + dout => ex3_preflush_2ucode_q); + +ex3_preflush_2ucode_ld_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_preflush_2ucode_ld_offset), + scout => sov(ex3_preflush_2ucode_ld_offset), + din => ex3_preflush_2ucode_ld_d, + dout => ex3_preflush_2ucode_ld_q); + +rel_is_ci_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_is_ci_offset), + scout => sov(rel_is_ci_offset), + din => rel_is_ci_d, + dout => rel_is_ci_q); + +rel_is_axu_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_is_axu_offset), + scout => sov(rel_is_axu_offset), + din => rel_is_axu_d, + dout => rel_is_axu_q); + +ex3_is_dcbz_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_dcbz_offset), + scout => sov(ex3_is_dcbz_offset), + din => ex3_is_dcbz_d, + dout => ex3_is_dcbz_q); + +ex4_misalign_flush_reg: tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex4_misalign_flush_d, + dout(0) => ex4_misalign_flush_q); + +ex5_misalign_flush_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_misalign_flush_offset), + scout => sov(ex5_misalign_flush_offset), + din => ex5_misalign_flush_d, + dout => ex5_misalign_flush_q); + +ex6_misalign_flush_reg: tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex6_misalign_flush_d, + dout(0) => ex6_misalign_flush_q); + +spr_xucr0_aflsta_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(spr_xucr0_aflsta_offset), + scout => sov(spr_xucr0_aflsta_offset), + din => spr_xucr0_aflsta_d, + dout => spr_xucr0_aflsta_q); + +spr_xucr0_flsta_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(spr_xucr0_flsta_offset), + scout => sov(spr_xucr0_flsta_offset), + din => spr_xucr0_flsta_d, + dout => spr_xucr0_flsta_q); + +spr_xucr0_l2siw_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(spr_xucr0_l2siw_offset), + scout => sov(spr_xucr0_l2siw_offset), + din => spr_xucr0_l2siw_d, + dout => spr_xucr0_l2siw_q); + +ex3_dep_flush_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_dep_flush_offset), + scout => sov(ex3_dep_flush_offset), + din => ex3_dep_flush_d, + dout => ex3_dep_flush_q); + +ex4_dep_flush_reg: tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex4_dep_flush_d, + dout(0) => ex4_dep_flush_q); + +ex5_dep_flush_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_dep_flush_offset), + scout => sov(ex5_dep_flush_offset), + din => ex5_dep_flush_d, + dout => ex5_dep_flush_q); + +ex6_dep_flush_reg: tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex6_dep_flush_d, + dout(0) => ex6_dep_flush_q); + +ex3_rel_collision_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_rel_collision_offset), + scout => sov(ex3_rel_collision_offset), + din => ex3_rel_collision_d, + dout => ex3_rel_collision_q); + +ex4_rel_collision_reg: tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex4_rel_collision_d, + dout(0) => ex4_rel_collision_q); + +ex5_rel_collision_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_rel_collision_offset), + scout => sov(ex5_rel_collision_offset), + din => ex5_rel_collision_d, + dout => ex5_rel_collision_q); + +ex6_rel_collision_reg: tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex6_rel_collision_d, + dout(0) => ex6_rel_collision_q); + +ex4_cClass_collision_reg: tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex4_cClass_collision_d, + dout(0) => ex4_cClass_collision_q); + +ex5_cClass_collision_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_cClass_collision_offset), + scout => sov(ex5_cClass_collision_offset), + din => ex5_cClass_collision_d, + dout => ex5_cClass_collision_q); + +ex6_cClass_collision_reg: tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex6_cClass_collision_d, + dout(0) => ex6_cClass_collision_q); + +siv(0 to scan_right) <= sov(1 to scan_right) & scan_in; +scan_out <= sov(0); + +end xuq_lsu_fgen; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_l2cmdq.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_l2cmdq.vhdl new file mode 100644 index 0000000..b413d04 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_l2cmdq.vhdl @@ -0,0 +1,8943 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +LIBRARY ieee; +LIBRARY ibm; +USE ieee.std_logic_1164.all ; +use ieee.numeric_std.all; +USE ibm.std_ulogic_support.all ; +USE ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; + +library support; +use support.power_logic_pkg.all; + +library tri; +use tri.tri_latches_pkg.all; + + +ENTITY xuq_lsu_l2cmdq IS + generic(expand_type : integer := 2; + lmq_entries : integer := 8; + dc_size : natural := 14; + cl_size : natural := 6; + real_data_add : integer := 42; + a2mode : integer := 1; + load_credits : integer := 4; + store_credits : integer := 20; + st_data_32B_mode : integer := 1 ); + PORT ( + ex3_thrd_id :in std_ulogic_vector(0 to 3); + ex3_l_s_q_val :in std_ulogic; + ex3_drop_ld_req :in std_ulogic; + ex3_drop_touch :in std_ulogic; + ex3_cache_inh :in std_ulogic; + ex3_load_instr :in std_ulogic; + ex3_store_instr :in std_ulogic; + ex3_cache_acc :in std_ulogic; + ex3_p_addr_lwr :in std_ulogic_vector(58 to 63); + ex3_opsize :in std_ulogic_vector(0 to 5); + ex3_rot_sel :in std_ulogic_vector(0 to 4); + ex3_byte_en :in std_ulogic_vector(0 to 31); + ex4_256st_data :in std_ulogic_vector(0 to 255); + ex3_target_gpr :in std_ulogic_vector(0 to 8); + ex3_axu_op_val :in std_ulogic; + ex3_le_mode :in std_ulogic; + ex3_larx_instr :in std_ulogic; + ex3_stx_instr :in std_ulogic; + ex3_dcbt_instr :in std_ulogic; + ex3_dcbf_instr :in std_ulogic; + ex3_dcbtst_instr :in std_ulogic; + ex3_dcbst_instr :in std_ulogic; + ex3_dcbz_instr :in std_ulogic; + ex3_dcbi_instr :in std_ulogic; + ex3_icbi_instr :in std_ulogic; + ex3_sync_instr :in std_ulogic; + ex3_l_fld :in std_ulogic_vector(0 to 1); + ex3_mbar_instr :in std_ulogic; + ex3_wimge_bits :in std_ulogic_vector(0 to 4); + ex3_usr_bits :in std_ulogic_vector(0 to 3); + ex3_stg_flush :in std_ulogic; + ex4_stg_flush :in std_ulogic; + xu_lsu_ex5_flush :in std_ulogic_vector(0 to 3); + ex3_byp_l1 :in std_ulogic; + ex3_algebraic :in std_ulogic; + xu_lsu_ex4_dvc1_en :in std_ulogic; + xu_lsu_ex4_dvc2_en :in std_ulogic; + + ex3_dcbtls_instr :in std_ulogic; + ex3_dcbtstls_instr :in std_ulogic; + ex3_dcblc_instr :in std_ulogic; + ex3_dci_instr :in std_ulogic; + ex3_ici_instr :in std_ulogic; + ex3_icblc_instr :in std_ulogic; + ex3_icbt_instr :in std_ulogic; + ex3_icbtls_instr :in std_ulogic; + ex3_tlbsync_instr :in std_ulogic; + ex3_local_dcbf :in std_ulogic; + ex3_icswx_instr :in std_ulogic; + ex3_icswx_dot :in std_ulogic; + ex3_icswx_epid :in std_ulogic; + ex3_classid :in std_ulogic_vector(0 to 1); + ex3_lock_en :in std_ulogic; + ex3_th_fld_l2 :in std_ulogic; + ex4_drop_rel :in std_ulogic; + ex3_load_l1hit :in std_ulogic; + ex3_mutex_hint :in std_ulogic; + ex3_msgsnd_instr :in std_ulogic; + ex3_watch_en :in std_ulogic; + ex3_mtspr_trace :in std_ulogic; + ex3_stg_act :in std_ulogic; + ex4_stg_act :in std_ulogic; + + ex4_ld_entry :in std_ulogic_vector(0 to (26+(real_data_add-1))); + + ex1_src0_vld :in std_ulogic; + ex1_src0_reg :in std_ulogic_vector(0 to 7); + ex1_src1_vld :in std_ulogic; + ex1_src1_reg :in std_ulogic_vector(0 to 7); + ex1_targ_vld :in std_ulogic; + ex1_targ_reg :in std_ulogic_vector(0 to 7); + ex1_check_watch :in std_ulogic_vector(0 to 3); + ex2_lm_dep_hit :out std_ulogic; + + ex6_ld_par_err :in std_ulogic; + pe_recov_begin :in std_ulogic; + ex7_targ_match :in std_ulogic; + ex8_targ_match :in std_ulogic; + + + an_ac_req_ld_pop :in std_ulogic; + an_ac_req_st_pop :in std_ulogic; + an_ac_req_st_pop_thrd :in std_ulogic_vector(0 to 2); + an_ac_req_st_gather :in std_ulogic; + + an_ac_reld_data_coming :in std_ulogic; + an_ac_reld_data_val :in std_ulogic; + an_ac_reld_core_tag :in std_ulogic_vector(0 to 4); + an_ac_reld_qw :in std_ulogic_vector(57 to 59); + an_ac_reld_data :in std_ulogic_vector(0 to 127); + an_ac_reld_ditc :in std_ulogic; + an_ac_reld_crit_qw :in std_ulogic; + an_ac_reld_l1_dump :in std_ulogic; + + an_ac_reld_ecc_err :in std_ulogic; + an_ac_reld_ecc_err_ue :in std_ulogic; + + an_ac_back_inv :in std_ulogic; + an_ac_back_inv_addr :in std_ulogic_vector(64-real_data_add to 63); + an_ac_back_inv_target_bit1 :in std_ulogic; + an_ac_back_inv_target_bit4 :in std_ulogic; + + an_ac_req_spare_ctrl_a1 :in std_ulogic_vector(0 to 3); + an_ac_stcx_complete :in std_ulogic_vector(0 to 3); + xu_iu_stcx_complete :out std_ulogic_vector(0 to 3); + xu_iu_reld_core_tag_clone :out std_ulogic_vector(1 to 4); + xu_iu_reld_data_coming_clone :out std_ulogic; + xu_iu_reld_data_vld_clone :out std_ulogic; + xu_iu_reld_ditc_clone :out std_ulogic; + + lsu_reld_data_vld :out std_ulogic; + lsu_reld_core_tag :out std_ulogic_vector(3 to 4); + lsu_reld_qw :out std_ulogic_vector(58 to 59); + lsu_reld_ditc :out std_ulogic; + lsu_reld_ecc_err :out std_ulogic; + lsu_reld_data :out std_ulogic_vector(0 to 127); + + lsu_req_st_pop :out std_ulogic; + lsu_req_st_pop_thrd :out std_ulogic_vector(0 to 2); + + i_x_ra :in std_ulogic_vector(64-real_data_add to 59); + i_x_request :in std_ulogic; + i_x_wimge :in std_ulogic_vector(0 to 4); + i_x_thread :in std_ulogic_vector(0 to 3); + i_x_userdef :in std_ulogic_vector(0 to 3); + + mm_xu_lsu_req :in std_ulogic_vector(0 to 3); + mm_xu_lsu_ttype :in std_ulogic_vector(0 to 1); + mm_xu_lsu_wimge :in std_ulogic_vector(0 to 4); + mm_xu_lsu_u :in std_ulogic_vector(0 to 3); + mm_xu_lsu_addr :in std_ulogic_vector(64-real_data_add to 63); + mm_xu_lsu_lpid :in std_ulogic_vector(0 to 7); + mm_xu_lsu_gs :in std_ulogic; + mm_xu_lsu_ind :in std_ulogic; + mm_xu_lsu_lbit :in std_ulogic; + + mm_xu_lsu_lpidr :in std_ulogic_vector(0 to 7); + xu_lsu_msr_gs :in std_ulogic_vector(0 to 3); + xu_lsu_msr_pr :in std_ulogic_vector(0 to 3); + xu_lsu_msr_ds :in std_ulogic_vector(0 to 3); + mm_xu_derat_pid0 :in std_ulogic_vector(0 to 13); + mm_xu_derat_pid1 :in std_ulogic_vector(0 to 13); + mm_xu_derat_pid2 :in std_ulogic_vector(0 to 13); + mm_xu_derat_pid3 :in std_ulogic_vector(0 to 13); + xu_derat_epsc0_epr :in std_ulogic; + xu_derat_epsc0_eas :in std_ulogic; + xu_derat_epsc0_egs :in std_ulogic; + xu_derat_epsc0_elpid :in std_ulogic_vector(40 to 47); + xu_derat_epsc0_epid :in std_ulogic_vector(50 to 63); + xu_derat_epsc1_epr :in std_ulogic; + xu_derat_epsc1_eas :in std_ulogic; + xu_derat_epsc1_egs :in std_ulogic; + xu_derat_epsc1_elpid :in std_ulogic_vector(40 to 47); + xu_derat_epsc1_epid :in std_ulogic_vector(50 to 63); + xu_derat_epsc2_epr :in std_ulogic; + xu_derat_epsc2_eas :in std_ulogic; + xu_derat_epsc2_egs :in std_ulogic; + xu_derat_epsc2_elpid :in std_ulogic_vector(40 to 47); + xu_derat_epsc2_epid :in std_ulogic_vector(50 to 63); + xu_derat_epsc3_epr :in std_ulogic; + xu_derat_epsc3_eas :in std_ulogic; + xu_derat_epsc3_egs :in std_ulogic; + xu_derat_epsc3_elpid :in std_ulogic_vector(40 to 47); + xu_derat_epsc3_epid :in std_ulogic_vector(50 to 63); + + + bx_lsu_ob_pwr_tok :in std_ulogic; + bx_lsu_ob_req_val :in std_ulogic; + bx_lsu_ob_ditc_val :in std_ulogic; + bx_lsu_ob_thrd :in std_ulogic_vector(0 to 1); + bx_lsu_ob_qw :in std_ulogic_vector(58 to 59); + bx_lsu_ob_dest :in std_ulogic_vector(0 to 14); + bx_lsu_ob_data :in std_ulogic_vector(0 to 127); + bx_lsu_ob_addr :in std_ulogic_vector(64-real_data_add to 57); + lsu_bx_cmd_avail :out std_ulogic; + lsu_bx_cmd_sent :out std_ulogic; + lsu_bx_cmd_stall :out std_ulogic; + + spr_xucr0_clkg_ctl_b3 :in std_ulogic; + xu_lsu_spr_xucr0_rel :in std_ulogic; + xu_lsu_spr_xucr0_l2siw :in std_ulogic; + xu_lsu_spr_xucr0_cred :in std_ulogic; + xu_lsu_spr_xucr0_mbar_ack :in std_ulogic; + xu_lsu_spr_xucr0_tlbsync :in std_ulogic; + xu_lsu_spr_xucr0_cls :in std_ulogic; + + xu_mm_lsu_token :out std_ulogic; + + + lsu_xu_ldq_barr_done :out std_ulogic_vector(0 to 3); + lsu_xu_sync_barr_done :out std_ulogic_vector(0 to 3); + + + ldq_rel_op_size :out std_ulogic_vector(0 to 5); + ldq_rel_thrd_id :out std_ulogic_vector(0 to 3); + ldq_rel_addr_early :out std_ulogic_vector(64-real_data_add to 57); + ldq_rel_addr :out std_ulogic_vector(64-real_data_add to 58); + ldq_rel_data_val_early :out std_ulogic; + ldq_rel_data_val :out std_ulogic; + ldq_rel_tag_early :out std_ulogic_vector(2 to 4); + ldq_rel_tag :out std_ulogic_vector(2 to 4); + ldq_rel1_val :out std_ulogic; + ldq_rel1_early_v :out std_ulogic; + ldq_rel_mid_val :out std_ulogic; + ldq_rel_retry_val :out std_ulogic; + ldq_rel3_val :out std_ulogic; + ldq_rel3_early_v :out std_ulogic; + ldq_rel_ta_gpr :out std_ulogic_vector(0 to 8); + ldq_rel_rot_sel :out std_ulogic_vector(0 to 4); + ldq_rel_axu_val :out std_ulogic; + ldq_rel_upd_gpr :out std_ulogic; + ldq_rel_le_mode :out std_ulogic; + ldq_rel_algebraic :out std_ulogic; + ldq_rel_set_val :out std_ulogic; + ldq_rel_256_data :out std_ulogic_vector(0 to 255); + ldq_rel_ecc_err :out std_ulogic; + + + ldq_rel_classid :out std_ulogic_vector(0 to 1); + ldq_rel_lock_en :out std_ulogic; + ldq_rel_ci :out std_ulogic; + ldq_rel_dvc1_en :out std_ulogic; + ldq_rel_dvc2_en :out std_ulogic; + ldq_rel_watch_en :out std_ulogic; + ldq_rel_back_invalidated :out std_ulogic; + + ldq_recirc_rel_val :in std_ulogic; + + ldq_rel_beat_crit_qw :out std_ulogic; + ldq_rel_beat_crit_qw_block :out std_ulogic; + + l1dump_cslc :out std_ulogic; + ldq_rel3_l1dump_val :out std_ulogic; + + is2_l2_inv_val :out std_ulogic; + is2_l2_inv_p_addr :out std_ulogic_vector(64-real_data_add to 63-cl_size); + + + ex3_stq_flush :out std_ulogic; + ex3_ig_flush :out std_ulogic; + ex3_ld_queue_full :out std_ulogic; + + gpr_ecc_err_flush_tid :out std_ulogic_vector(0 to 3); + xu_iu_ex4_loadmiss_qentry :out std_ulogic_vector(0 to lmq_entries-1); + xu_iu_ex4_loadmiss_target :out std_ulogic_vector(0 to 8); + xu_iu_ex4_loadmiss_target_type :out std_ulogic_vector(0 to 1); + xu_iu_ex4_loadmiss_tid :out std_ulogic_vector(0 to 3); + xu_iu_ex5_loadmiss_qentry :out std_ulogic_vector(0 to lmq_entries-1); + xu_iu_ex5_loadmiss_target :out std_ulogic_vector(0 to 8); + xu_iu_ex5_loadmiss_target_type :out std_ulogic_vector(0 to 1); + xu_iu_ex5_loadmiss_tid :out std_ulogic_vector(0 to 3); + xu_iu_complete_qentry :out std_ulogic_vector(0 to lmq_entries-1); + xu_iu_complete_tid :out std_ulogic_vector(0 to 3); + xu_iu_complete_target_type :out std_ulogic_vector(0 to 1); + + xu_iu_larx_done_tid :out std_ulogic_vector(0 to 3); + + xu_lsu_ex5_set_barr :in std_ulogic_vector(0 to 3); + + xu_mm_lmq_stq_empty :out std_ulogic; + + lsu_xu_quiesce :out std_ulogic_vector(0 to 3); + + + lsu_xu_dbell_val :out std_ulogic; + lsu_xu_dbell_type :out std_ulogic_vector(0 to 4); + lsu_xu_dbell_brdcast :out std_ulogic; + lsu_xu_dbell_lpid_match :out std_ulogic; + lsu_xu_dbell_pirtag :out std_ulogic_vector(50 to 63); + + + + ac_an_req_pwr_token :out std_ulogic; + ac_an_req :out std_ulogic; + ac_an_req_ra :out std_ulogic_vector(64-real_data_add to 63); + ac_an_req_ttype :out std_ulogic_vector(0 to 5); + ac_an_req_thread :out std_ulogic_vector(0 to 2); + ac_an_req_wimg_w :out std_ulogic; + ac_an_req_wimg_i :out std_ulogic; + ac_an_req_wimg_m :out std_ulogic; + ac_an_req_wimg_g :out std_ulogic; + ac_an_req_endian :out std_ulogic; + ac_an_req_user_defined :out std_ulogic_vector(0 to 3); + ac_an_req_spare_ctrl_a0 :out std_ulogic_vector(0 to 3); + ac_an_req_ld_core_tag :out std_ulogic_vector(0 to 4); + ac_an_req_ld_xfr_len :out std_ulogic_vector(0 to 2); + ac_an_st_byte_enbl :out std_ulogic_vector(0 to 15+(st_data_32B_mode*16)); + ac_an_st_data :out std_ulogic_vector(0 to 127+(st_data_32B_mode*128)); + ac_an_st_data_pwr_token :out std_ulogic; + + + cmp_lmq_entry_act :out std_ulogic; + cmp_ex3_p_addr_o :in std_ulogic_vector(64-real_data_add to 57); + cmp_ldq_comp_val :out std_ulogic_vector(0 to 7); + cmp_ldq_match :in std_ulogic_vector(0 to 7); + cmp_ldq_fnd :in std_ulogic; + + cmp_l_q_wrt_en :out std_ulogic_vector(0 to 7); + cmp_ld_ex7_recov :out std_ulogic; + cmp_ex7_ld_recov_addr :out std_ulogic_vector(64-real_data_add to 57); + + cmp_ex4_loadmiss_qentry :out std_ulogic_vector(0 to 7); + cmp_ex4_ld_addr :in std_ulogic_vector(64-real_data_add to 57); + + cmp_l_q_rd_en :out std_ulogic_vector(0 to 7); + cmp_l_miss_entry_addr :in std_ulogic_vector(64-real_data_add to 57); + + cmp_rel_tag_1hot :out std_ulogic_vector(0 to 7); + cmp_rel_addr :in std_ulogic_vector(64-real_data_add to 57); + + cmp_back_inv_addr :out std_ulogic_vector(64-real_data_add to 57); + cmp_back_inv_cmp_val :out std_ulogic_vector(0 to 7); + cmp_back_inv_addr_hit :in std_ulogic_vector(0 to 7); + + cmp_s_m_queue0_addr :out std_ulogic_vector(64-real_data_add to 57); + cmp_st_entry0_val :out std_ulogic ; + cmp_ex3addr_hit_stq :in std_ulogic ; + + cmp_ex4_st_entry_addr :out std_ulogic_vector(64-real_data_add to 57); + cmp_ex4_st_val :out std_ulogic ; + cmp_ex3addr_hit_ex4st :in std_ulogic ; + + ac_an_reld_ditc_pop_int : in std_ulogic_vector(0 to 3); + ac_an_reld_ditc_pop_q : out std_ulogic_vector(0 to 3); + bx_ib_empty_int : in std_ulogic_vector(0 to 3); + bx_ib_empty_q : out std_ulogic_vector(0 to 3); + + + + lsu_xu_perf_events :out std_ulogic_vector(0 to 8); + + lmq_pe_recov_state :out std_ulogic; + + lmq_dbg_dcache_pe :out std_ulogic_vector(1 to 60); + lmq_dbg_l2req :out std_ulogic_vector(0 to 212); + lmq_dbg_rel :out std_ulogic_vector(0 to 140); + lmq_dbg_binv :out std_ulogic_vector(0 to 44); + lmq_dbg_pops :out std_ulogic_vector(0 to 5); + lmq_dbg_grp0 :out std_ulogic_vector(0 to 81); + lmq_dbg_grp1 :out std_ulogic_vector(0 to 81); + lmq_dbg_grp2 :out std_ulogic_vector(0 to 87); + lmq_dbg_grp3 :out std_ulogic_vector(0 to 87); + lmq_dbg_grp4 :out std_ulogic_vector(0 to 87); + lmq_dbg_grp5 :out std_ulogic_vector(0 to 87); + lmq_dbg_grp6 :out std_ulogic_vector(0 to 87); + + vdd : inout power_logic; + gnd : inout power_logic; + + l2_data_ecc_err_ue :out std_ulogic_vector(0 to 3); + xu_pc_err_l2intrf_ecc :out std_ulogic; + xu_pc_err_l2intrf_ue :out std_ulogic; + xu_pc_err_invld_reld :out std_ulogic; + xu_pc_err_l2credit_overrun :out std_ulogic; + + an_ac_coreid :in std_ulogic_vector(6 to 7); + + nclk :in clk_logic; + sg_0 :in std_ulogic; + func_sl_thold_0_b :in std_ulogic; + func_sl_force :in std_ulogic; + func_slp_sl_thold_0_b :in std_ulogic; + func_slp_sl_force :in std_ulogic; + cfg_slp_sl_thold_0_b :in std_ulogic; + cfg_slp_sl_force :in std_ulogic; + d_mode_dc :in std_ulogic; + delay_lclkr_dc :in std_ulogic; + mpw1_dc_b :in std_ulogic; + mpw2_dc_b :in std_ulogic; + scan_dis_dc_b :in std_ulogic; + bcfg_scan_in :in std_ulogic; + bcfg_scan_out :out std_ulogic; + scan_in :in std_ulogic_vector(0 to 2); + scan_out :out std_ulogic_vector(0 to 2) + ); + + + + + + +END ; + +ARCHITECTURE xuq_lsu_l2cmdq OF xuq_lsu_l2cmdq IS + +constant REAL_IFAR_length : integer := (real_data_add-4); + +signal c_inh :std_ulogic; +signal ctrl_incr_cmdseq :std_ulogic; +signal ctrl_decr_cmdseq :std_ulogic; +signal ctrl_hold_cmdseq :std_ulogic; +signal cmd_seq_incr :std_ulogic_vector(0 to 4); +signal cmd_seq_decr :std_ulogic_vector(0 to 4); +signal cmd_seq_d :std_ulogic_vector(0 to 4); +signal cmd_seq_l2 :std_ulogic_vector(0 to 4); +signal new_ld_cmd_seq :std_ulogic_vector(0 to 4); +signal cmd_seq_rd_incr :std_ulogic_vector(0 to 4); +signal cmd_seq_rd_d :std_ulogic_vector(0 to 4); +signal cmd_seq_rd_l2 :std_ulogic_vector(0 to 4); +signal ld_q_seq_wrap :std_ulogic; + +signal ld_queue_entry :std_ulogic_vector(0 to 53); +signal ld_queue_addrlo :std_ulogic_vector(57 to 63); +signal st_val :std_ulogic; +signal st_flush :std_ulogic; +signal flush_if_store :std_ulogic; +signal nxt_st_cred_tkn :std_ulogic; +signal sync_flush :std_ulogic; +signal s_m_queue0_d :std_ulogic_vector(0 to (58+(real_data_add-1))); +signal s_m_queue0 :std_ulogic_vector(0 to (58+(real_data_add-1))); +signal ex3_st_entry :std_ulogic_vector(0 to (58+(real_data_add-1))); +signal ex4_st_entry_act :std_ulogic; +signal ex4_st_entry_l2 :std_ulogic_vector(0 to (58+(real_data_add-1))); +signal st_entry0_val_d :std_ulogic; +signal st_entry0_val_l2 :std_ulogic; +signal st_entry0_val_clone_l2 :std_ulogic; +signal ex4_st_val_d :std_ulogic; +signal ex4_st_val_l2 :std_ulogic; +signal ex4_st_valid :std_ulogic; +signal ex5_st_val_l2 :std_ulogic; +signal ex5_st_val_for_flush :std_ulogic; +signal ex6_st_val_l2 :std_ulogic; +signal ex4_st_addr :std_ulogic_vector(64-real_data_add to 63); + +signal ld_m_val :std_ulogic; +signal ex4_ld_m_val :std_ulogic; +signal ex4_ld_m_val_not_fl :std_ulogic; +signal ex4_drop_ld_req :std_ulogic; +signal ex4_drop_touch :std_ulogic; + + +signal my_ex4_flush_l2 :std_ulogic; +signal ld_flush :std_ulogic; +signal ld_queue_full :std_ulogic; +signal comp_val :std_ulogic_vector(0 to lmq_entries-1); +signal l_m_q_cpy :std_ulogic_vector(0 to lmq_entries-1); +signal l_m_q_cpy_nofl :std_ulogic_vector(0 to lmq_entries-1); +signal ex4_lmq_cpy_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal ex5_lmq_cpy_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal l_m_fnd_nofl :std_ulogic; +signal l_q_wrt_en :std_ulogic_vector(0 to lmq_entries-1); +signal ld_entry_val_d :std_ulogic_vector(0 to lmq_entries-1); +signal ld_entry_val_l2 :std_ulogic_vector(0 to lmq_entries-1); + +type load_queue_array is array(0 to lmq_entries-1) of std_ulogic_vector(0 to 53); +signal l_m_queue_d :load_queue_array; +signal l_m_queue :load_queue_array; +type load_queue_addrlo_array is array(0 to lmq_entries-1) of std_ulogic_vector(57 to 63); +signal l_m_queue_addrlo_d :load_queue_addrlo_array; +signal l_m_queue_addrlo :load_queue_addrlo_array; +signal ex4_ld_recov_entry :std_ulogic_vector(0 to 53); +signal ex4_ld_recov_addrlo :std_ulogic_vector(58 to 63); +signal ex4_ld_entry_d :std_ulogic_vector(0 to 14); +signal ex4_ld_entry_l2 :std_ulogic_vector(0 to 14); +signal ex4_classid_l2 :std_ulogic_vector(0 to 1); +signal ex4_ld_recov :std_ulogic_vector(0 to (54+(real_data_add-1))); +signal ex5_ld_recov_d :std_ulogic_vector(0 to (54+(real_data_add-1))); +signal ex6_ld_recov_d :std_ulogic_vector(0 to (54+(real_data_add-1))); +signal ex7_ld_recov_d :std_ulogic_vector(0 to (54+(real_data_add-1))); +signal ex5_ld_recov_l2 :std_ulogic_vector(0 to (54+(real_data_add-1))); +signal ex6_ld_recov_l2 :std_ulogic_vector(0 to (54+(real_data_add-1))); +signal ex7_ld_recov_l2 :std_ulogic_vector(0 to (54+(real_data_add-1))); +signal ex4_ld_entry_hit_st_d :std_ulogic; +signal ex4_ld_entry_hit_st_l2 :std_ulogic; +signal ex4_touch :std_ulogic; +signal ex4_l2only :std_ulogic; +signal ex4_ld_recov_val_d :std_ulogic; +signal ex4_ld_recov_val_l2 :std_ulogic; +signal ex5_ld_recov_val_d :std_ulogic; +signal ex5_ld_recov_val_l2 :std_ulogic; +signal ex5_ld_recov_val_not_fl :std_ulogic; +signal ex6_ld_recov_val_l2 :std_ulogic; +signal ex6_ld_recov_val_not_fl :std_ulogic; +signal ex7_ld_recov_val_l2 :std_ulogic; +signal ex4_ld_recov_ld_hit_st :std_ulogic; +signal ex4_ld_recov_extra :std_ulogic_vector(0 to 3); +signal ex5_ld_recov_extra_d :std_ulogic_vector(0 to 3); +signal ex6_ld_recov_extra_d :std_ulogic_vector(0 to 3); +signal ex7_ld_recov_extra_d :std_ulogic_vector(0 to 3); +signal ex5_ld_recov_extra_l2 :std_ulogic_vector(0 to 3); +signal ex6_ld_recov_extra_l2 :std_ulogic_vector(0 to 3); +signal ex7_ld_recov_extra_l2 :std_ulogic_vector(0 to 3); +signal ex8_ld_recov_extra_l2 :std_ulogic_vector(1 to 3); +signal pe_recov_state_d :std_ulogic; +signal pe_recov_state_l2 :std_ulogic; +signal pe_recov_state_dly_l2 :std_ulogic; +signal pe_recov_ld_num_d :std_ulogic_vector(1 to 3); +signal pe_recov_ld_num_l2 :std_ulogic_vector(1 to 3); +signal pe_recov_ld_val_d :std_ulogic; +signal pe_recov_ld_val_l2 :std_ulogic; +signal pe_recov_stall :std_ulogic; +signal recov_ignr_flush_d :std_ulogic; +signal set_st_hit_recov_ld :std_ulogic; +signal reset_st_hit_recov_ld :std_ulogic; +signal stq_hit_ex6_recov :std_ulogic; +signal ex4st_hit_ex6_recov :std_ulogic; +signal st_hit_recov_ld_d :std_ulogic; +signal st_hit_recov_ld_l2 :std_ulogic; +signal blk_st_for_pe_recov :std_ulogic; +signal blk_st_cred_pop :std_ulogic; + + + +type rel_queue_array is array(0 to lmq_entries-1) of std_ulogic_vector(0 to 33); +signal rel_entry :rel_queue_array; + +signal rel_addr_d :std_ulogic_vector(64-real_data_add to 58); +signal rel_size_d :std_ulogic_vector(0 to 5); +signal rel_rot_sel_d :std_ulogic_vector(0 to 4); +signal rel_th_id_d :std_ulogic_vector(0 to 3); +signal l_m_rel_c_i_beat0_d :std_ulogic_vector(0 to lmq_entries-1); +signal l_m_rel_c_i_val :std_ulogic_vector(0 to lmq_entries-1); +signal l_m_rel_hit_beat0_d :std_ulogic_vector(0 to lmq_entries-1); +signal l_m_rel_hit_beat1_d :std_ulogic_vector(0 to lmq_entries-1); +signal l_m_rel_hit_beat2_d :std_ulogic_vector(0 to lmq_entries-1); +signal l_m_rel_hit_beat3_d :std_ulogic_vector(0 to lmq_entries-1); +signal l_m_rel_hit_beat4_d :std_ulogic_vector(0 to lmq_entries-1); +signal l_m_rel_hit_beat5_d :std_ulogic_vector(0 to lmq_entries-1); +signal l_m_rel_hit_beat6_d :std_ulogic_vector(0 to lmq_entries-1); +signal l_m_rel_hit_beat7_d :std_ulogic_vector(0 to lmq_entries-1); +signal l_m_rel_inprog_d :std_ulogic_vector(0 to lmq_entries-1); +signal l_m_rel_c_i_beat0_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal l_m_rel_hit_beat0_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal l_m_rel_hit_beat1_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal l_m_rel_hit_beat2_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal l_m_rel_hit_beat3_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal l_m_rel_hit_beat4_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal l_m_rel_hit_beat5_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal l_m_rel_hit_beat6_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal l_m_rel_hit_beat7_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal l_m_rel_inprog_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal rel_done_ecc_err :std_ulogic; +signal ld_m_rel_done_d :std_ulogic_vector(0 to lmq_entries-1); +signal ld_m_rel_done_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal ld_m_rel_done_no_retry :std_ulogic_vector(0 to lmq_entries-1); +signal ld_m_rel_done_dly_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal ld_m_rel_done_dly2_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal reset_lmq_entry_rel :std_ulogic_vector(0 to lmq_entries-1); +signal reset_lmq_entry :std_ulogic_vector(0 to lmq_entries-1); +signal reset_ldq_hit_barr :std_ulogic_vector(0 to lmq_entries-1); +signal ldq_retry_d :std_ulogic_vector(0 to lmq_entries-1); +signal ldq_retry_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal ldq_retry_ready :std_ulogic_vector(0 to lmq_entries-1); +signal start_ldq_retry :std_ulogic_vector(0 to lmq_entries-1); +signal retry_started_d :std_ulogic_vector(0 to lmq_entries-1); +signal retry_started_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal ldq_retry_or :std_ulogic; + +signal any_ld_entry_val :std_ulogic; +signal selected_ld_entry_val :std_ulogic; +signal selected_entry_flushed :std_ulogic; +signal cmd_seq_rd_incr_val :std_ulogic; +signal ldq_rd_seq_match_next :std_ulogic_vector(0 to lmq_entries-1); +signal ldq_rd_seq_match_curr :std_ulogic_vector(0 to lmq_entries-1); +signal ldq_rd_seq_match_d :std_ulogic_vector(0 to lmq_entries-1); +signal ldq_rd_seq_match_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal l_q_rd_en :std_ulogic_vector(0 to lmq_entries-1); +signal rd_seq_hit :std_ulogic_vector(0 to lmq_entries-1); +signal rd_seq_num_exits :std_ulogic; +signal rd_seq_num_skip :std_ulogic; +signal blk_ld_for_pe_recov_d :std_ulogic; +signal blk_ld_for_pe_recov_l2 :std_ulogic; + + +signal l_miss_entry :std_ulogic_vector(0 to 53); +signal l_miss_addrlo :std_ulogic_vector(58 to 63); +signal store_sent :std_ulogic; +signal ex5_store_sent :std_ulogic; +signal ex4_sel_st_req :std_ulogic; +signal cred_pop :std_ulogic; +signal ex5_sel_st_req :std_ulogic; +signal load_sent :std_ulogic; +signal load_sent_dbglat_l2 :std_ulogic; +signal load_flushed :std_ulogic; +signal mmu_sent :std_ulogic; +signal mmu_sent_l2 :std_ulogic; +signal mmu_ld_sent :std_ulogic; +signal mmu_st_sent :std_ulogic; +signal l_m_tag :std_ulogic_vector(2 to 4); +signal iu_thrd :std_ulogic_vector(0 to 1); +signal ld_tag :std_ulogic_vector(1 to 4); + + +signal l_m_rel_val_c_i_dly :std_ulogic_vector(0 to lmq_entries-1); + +signal rel_addr_l2 :std_ulogic_vector(64-real_data_add to 58); +signal rel_size_l2 :std_ulogic_vector(0 to 5); +signal rel_rot_sel_l2 :std_ulogic_vector(0 to 4); +signal rel_th_id_l2 :std_ulogic_vector(0 to 3); +signal rel_tar_gpr_d :std_ulogic_vector(0 to 8); +signal rel_tar_gpr_l2 :std_ulogic_vector(0 to 8); + + +signal rel_cache_inh_d :std_ulogic; +signal rel_cache_inh_l2 :std_ulogic; +signal rel_le_mode_d :std_ulogic; +signal rel_vpr_val_d :std_ulogic; +signal rel_vpr_val_l2 :std_ulogic; +signal dcbt_instr :std_ulogic; +signal touch_instr :std_ulogic; +signal l2only_instr :std_ulogic; +signal rel_dcbt_d :std_ulogic; +signal rel_dcbt_l2 :std_ulogic; +signal rel_le_mode_l2 :std_ulogic; +signal rel_algebraic_d :std_ulogic; +signal rel_algebraic_l2 :std_ulogic; +signal rel_lock_en_d :std_ulogic; +signal rel_lock_en_l2 :std_ulogic; +signal rel_classid_d :std_ulogic_vector(0 to 1); +signal rel_classid_l2 :std_ulogic_vector(0 to 1); +signal rel_l2only_d :std_ulogic; +signal rel_l2only_l2 :std_ulogic; +signal rel_l2only_dly_l2 :std_ulogic; +signal rel_dvc1_d :std_ulogic; +signal rel_dvc1_l2 :std_ulogic; +signal rel_dvc2_d :std_ulogic; +signal rel_dvc2_l2 :std_ulogic; +signal rel_watch_en_d :std_ulogic; +signal rel_watch_en_l2 :std_ulogic; +signal lmq_drop_rel_d :std_ulogic_vector(0 to lmq_entries-1); +signal lmq_drop_rel_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal lmq_dvc1_en_d :std_ulogic_vector(0 to lmq_entries-1); +signal lmq_dvc2_en_d :std_ulogic_vector(0 to lmq_entries-1); +signal lmq_dvc1_en_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal lmq_dvc2_en_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal ldq_rel1_val_buf :std_ulogic; +signal ldq_rel_mid_val_buf :std_ulogic; +signal ldq_rel3_val_buf :std_ulogic; +signal ldq_rel_retry_val_buf :std_ulogic; +signal ldq_rel_data_val_buf :std_ulogic; +signal ldq_rel_upd_gpr_buf :std_ulogic; +signal ldq_rel_set_val_buf :std_ulogic; +signal l2only_from_queue :std_ulogic; + + +signal rel_q_entry :std_ulogic_vector(0 to 33); +signal rel_q_addrlo_58 :std_ulogic; + +signal l_m_fnd_stg :std_ulogic; + +signal ld_rel_val_d :std_ulogic_vector(0 to lmq_entries-1); +signal ld_rel_val_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal l_m_q_hit_st_d :std_ulogic_vector(0 to lmq_entries-1); +signal l_m_q_hit_st_l2 :std_ulogic_vector(0 to lmq_entries-1); + +signal ex3_new_target_gpr :std_ulogic_vector(0 to 8); +signal cmd_type_ld :std_ulogic_vector(0 to 5); +signal cmd_type_st :std_ulogic_vector(0 to 5); +signal load_val :std_ulogic; +signal load_l1hit_val :std_ulogic; +signal ex4_load_l1hit_val :std_ulogic; +signal hwsync_val :std_ulogic; +signal lwsync_val :std_ulogic; +signal mbar_val :std_ulogic; +signal ldq_barr_done :std_ulogic_vector(0 to 3); +signal ldq_barr_done_l2 :std_ulogic_vector(0 to 3); +signal sync_done_tid :std_ulogic_vector(0 to 3); +signal sync_done_tid_l2 :std_ulogic_vector(0 to 3); +signal lmq_barr_done_tid :std_ulogic_vector(0 to 3); +signal ldq_barr_active_d :std_ulogic_vector(0 to 3); +signal ldq_barr_active_l2 :std_ulogic_vector(0 to 3); +signal lmq_collision_t0_d :std_ulogic_vector(0 to lmq_entries-1); +signal lmq_collision_t0_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal lmq_collision_t1_d :std_ulogic_vector(0 to lmq_entries-1); +signal lmq_collision_t1_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal lmq_collision_t2_d :std_ulogic_vector(0 to lmq_entries-1); +signal lmq_collision_t2_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal lmq_collision_t3_d :std_ulogic_vector(0 to lmq_entries-1); +signal lmq_collision_t3_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal dcbf_l_val :std_ulogic; +signal dcbf_g_val :std_ulogic; +signal dcbt_l2only_val :std_ulogic; +signal dcbt_l1l2_val :std_ulogic; +signal dcbtls_l2only_val :std_ulogic; +signal dcbtls_l1l2_val :std_ulogic; +signal dcbtst_l2only_val :std_ulogic; +signal dcbtst_l1l2_val :std_ulogic; +signal dcbtstls_l2only_val :std_ulogic; +signal dcbtstls_l1l2_val :std_ulogic; + + +signal ifetch_req_l2 :std_ulogic; +signal ifetch_ra_l2 :std_ulogic_vector(64-real_data_add to 59); +signal ifetch_thread_l2 :std_ulogic_vector(0 to 3); +signal ifetch_userdef_l2 :std_ulogic_vector(0 to 3); +signal ifetch_wimge_l2 :std_ulogic_vector(0 to 4); +signal iu_f_tid0_val :std_ulogic; +signal iu_f_tid1_val :std_ulogic; +signal iu_f_tid2_val :std_ulogic; +signal iu_f_tid3_val :std_ulogic; +signal iu_seq_rd_incr :std_ulogic_vector(0 to 2); +signal iu_seq_rd_d :std_ulogic_vector(0 to 2); +signal iu_seq_rd_l2 :std_ulogic_vector(0 to 2); +signal iu_seq_incr :std_ulogic_vector(0 to 2); +signal iu_seq_d :std_ulogic_vector(0 to 2); +signal iu_seq_l2 :std_ulogic_vector(0 to 2); +signal iu_queue_entry :std_ulogic_vector(0 to (REAL_IFAR_length+11)); +signal iu_f_q0_val_upd :std_ulogic_vector(0 to 1); +signal i_f_q0_val_d :std_ulogic; +signal i_f_q0_val_l2 :std_ulogic; +signal i_f_q0_d :std_ulogic_vector(0 to (REAL_IFAR_length+11)); +signal i_f_q0_l2 :std_ulogic_vector(0 to (REAL_IFAR_length+11)); +signal iu_f_q1_val_upd :std_ulogic_vector(0 to 1); +signal i_f_q1_val_d :std_ulogic; +signal i_f_q1_val_l2 :std_ulogic; +signal i_f_q1_d :std_ulogic_vector(0 to (REAL_IFAR_length+11)); +signal i_f_q1_l2 :std_ulogic_vector(0 to (REAL_IFAR_length+11)); +signal iu_f_q2_val_upd :std_ulogic_vector(0 to 1); +signal i_f_q2_val_d :std_ulogic; +signal i_f_q2_val_l2 :std_ulogic; +signal i_f_q2_d :std_ulogic_vector(0 to (REAL_IFAR_length+11)); +signal i_f_q2_l2 :std_ulogic_vector(0 to (REAL_IFAR_length+11)); +signal iu_f_q3_val_upd :std_ulogic_vector(0 to 1); +signal i_f_q3_val_d :std_ulogic; +signal i_f_q3_val_l2 :std_ulogic; +signal i_f_q3_d :std_ulogic_vector(0 to (REAL_IFAR_length+11)); +signal i_f_q3_l2 :std_ulogic_vector(0 to (REAL_IFAR_length+11)); +signal iu_f_q0_sel :std_ulogic; +signal iu_f_q1_sel :std_ulogic; +signal iu_f_q2_sel :std_ulogic; +signal iu_f_q3_sel :std_ulogic; +signal iu_f_q_sel :std_ulogic_vector(0 to 1); +signal iu_f_sel_entry :std_ulogic_vector(0 to (9+REAL_IFAR_length-1)); +signal i_f_q0_sent :std_ulogic; +signal i_f_q1_sent :std_ulogic; +signal i_f_q2_sent :std_ulogic; +signal i_f_q3_sent :std_ulogic; +signal iu_val_req :std_ulogic; +signal iu_sent_val :std_ulogic; +signal sel_if_req :std_ulogic; +signal sel_ld_req :std_ulogic; +signal sel_mm_req :std_ulogic; +signal send_if_req_d :std_ulogic; +signal send_if_req_l2 :std_ulogic; +signal send_ld_req_d :std_ulogic; +signal send_ld_req_l2 :std_ulogic; +signal send_mm_req_d :std_ulogic; +signal send_mm_req_l2 :std_ulogic; +signal iu_f_entry :std_ulogic_vector(0 to (real_data_add-1+54)); +signal iu_mmu_entry :std_ulogic_vector(0 to (real_data_add-1+54)); +signal ldmq_entry :std_ulogic_vector(0 to (real_data_add-1+54)); +signal store_entry :std_ulogic_vector(0 to (real_data_add-1+54)); +signal st_req :std_ulogic_vector(0 to (real_data_add-1+54)); +signal ob_store :std_ulogic_vector(0 to (real_data_add-1+54)); +signal st_recycle_entry :std_ulogic_vector(0 to (real_data_add-1+54)); +signal st_recycle_d :std_ulogic_vector(0 to (real_data_add-1+54)); +signal st_recycle_l2 :std_ulogic_vector(0 to (real_data_add-1+54)); +signal st_recycle_act :std_ulogic; +signal st_recycle_v_d :std_ulogic; +signal st_recycle_v_l2 :std_ulogic; +signal ld_st_request :std_ulogic_vector(0 to (real_data_add-1+54)); +signal mmuq_req :std_ulogic_vector(0 to (real_data_add-1+54)); +signal iu_val :std_ulogic; +signal ld_q_val :std_ulogic; +signal ld_q_req :std_ulogic; +signal state_trans :std_ulogic; +signal mmu_q_val :std_ulogic; +signal reld_data_vld_l2 :std_ulogic; +signal reld_data_vld_dplus1_l2 :std_ulogic; + +signal load_credit :std_ulogic; +signal store_credit :std_ulogic; +signal one_st_cred :std_ulogic; +signal ld_credit_pre :std_ulogic; +signal st_credit_pre :std_ulogic; +signal load_credit_used :std_ulogic; +signal decr_load_cnt_lcu0 :std_ulogic; +signal dec_by2_ld_cnt_lcu0 :std_ulogic; +signal hold_load_cnt_lcu0 :std_ulogic; +signal incr_load_cnt_lcu1 :std_ulogic; +signal decr_load_cnt_lcu1 :std_ulogic; +signal hold_load_cnt_lcu1 :std_ulogic; +signal load_cmd_count_incr :std_ulogic_vector(0 to 3); +signal load_cmd_count_decr :std_ulogic_vector(0 to 3); +signal load_cmd_count_decrby2 :std_ulogic_vector(0 to 3); +signal load_cmd_count_lcu0 :std_ulogic_vector(0 to 3); +signal load_cmd_count_lcu1 :std_ulogic_vector(0 to 3); +signal load_cmd_count_d :std_ulogic_vector(0 to 3); +signal load_cmd_count_l2 :std_ulogic_vector(0 to 3); +signal store_cmd_count_incr :std_ulogic_vector(0 to 5); +signal store_cmd_count_decr :std_ulogic_vector(0 to 5); +signal store_cmd_count_decby2 :std_ulogic_vector(0 to 5); +signal store_cmd_count_decby3 :std_ulogic_vector(0 to 5); +signal store_cmd_count_d :std_ulogic_vector(0 to 5); +signal store_cmd_count_l2 :std_ulogic_vector(0 to 5); +signal incr_store_cmd :std_ulogic; +signal decr_store_cmd :std_ulogic; +signal dec_by2_st_cmd :std_ulogic; +signal dec_by3_st_cmd :std_ulogic; +signal hold_store_cmd :std_ulogic; +signal st_count_ctrl :std_ulogic_vector(0 to 3); +signal err_cred_overrun_d :std_ulogic; +signal err_cred_overrun_l2 :std_ulogic; + +signal l2req_resend_d :std_ulogic; +signal l2req_resend_l2 :std_ulogic; +signal l2req_recycle_d :std_ulogic; +signal l2req_recycle_l2 :std_ulogic; +signal l2req_pwr_token :std_ulogic; +signal l2req_pwr_token_l2 :std_ulogic; +signal l2req :std_ulogic; +signal l2req_gated :std_ulogic; +signal l2req_l2 :std_ulogic; +signal l2req_st_data_ptoken :std_ulogic; +signal l2req_st_data_ptoken_l2 :std_ulogic; +signal l2req_ra :std_ulogic_vector(64-real_data_add to 63); +signal l2req_ra_l2 :std_ulogic_vector(64-real_data_add to 63); +signal l2req_st_byte_enbl :std_ulogic_vector(0 to 15+(st_data_32B_mode*16)); +signal l2req_st_byte_enbl_l2 :std_ulogic_vector(0 to 15+(st_data_32B_mode*16)); +signal l2req_ld_core_tag :std_ulogic_vector(0 to 4); +signal l2req_ld_core_tag_l2 :std_ulogic_vector(0 to 4); +signal l2req_thread :std_ulogic_vector(0 to 2); +signal l2req_thread_l2 :std_ulogic_vector(0 to 2); +signal l2req_ttype :std_ulogic_vector(0 to 5); +signal l2req_ttype_l2 :std_ulogic_vector(0 to 5); +signal l2req_wimg :std_ulogic_vector(0 to 3); +signal l2req_wimg_l2 :std_ulogic_vector(0 to 3); +signal l2req_ld_xfr_len :std_ulogic_vector(0 to 2); +signal l2req_ld_xfr_len_l2 :std_ulogic_vector(0 to 2); +signal l2req_endian :std_ulogic; +signal l2req_endian_l2 :std_ulogic; +signal l2req_user :std_ulogic_vector(0 to 3); +signal l2req_user_l2 :std_ulogic_vector(0 to 3); +signal ex4_st_data_mux :std_ulogic_vector(0 to 127+(st_data_32B_mode*128)); +signal ex4_st_data_mux2 :std_ulogic_vector(0 to 127+(st_data_32B_mode*128)); +signal ex5_st_data_mux1 :std_ulogic_vector(0 to 127); +signal ex5_st_data_mux2 :std_ulogic_vector(0 to 127); +signal ex5_st_data_mux :std_ulogic_vector(0 to 127+(st_data_32B_mode*128)); +signal ex5_st_data_l2 :std_ulogic_vector(0 to 127+(st_data_32B_mode*128)); +signal ex6_st_data_l2 :std_ulogic_vector(0 to 127+(st_data_32B_mode*128)); + +signal sync_done :std_ulogic; +signal rel_tag_l2 :std_ulogic_vector(1 to 4); +signal rel_tag_dplus1_l2 :std_ulogic_vector(1 to 4); +signal rel_data_val :std_ulogic_vector(0 to lmq_entries-1); +signal start_rel :std_ulogic_vector(0 to lmq_entries-1); +signal rel_data_val_dplus1 :std_ulogic_vector(0 to lmq_entries-1); +signal set_data_ecc_err :std_ulogic_vector(0 to lmq_entries-1); +signal data_ecc_err_d :std_ulogic_vector(0 to lmq_entries-1); +signal data_ecc_err_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal set_data_ecc_ue :std_ulogic_vector(0 to lmq_entries-1); +signal data_ecc_ue_d :std_ulogic_vector(0 to lmq_entries-1); +signal data_ecc_ue_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal rel_tag_1hot :std_ulogic_vector(0 to lmq_entries-1); +signal I1_G1_thrd0 :std_ulogic; +signal I1_G1_thrd1 :std_ulogic; +signal I1_G1_thrd2 :std_ulogic; +signal I1_G1_thrd3 :std_ulogic; +signal I1_G1_flush :std_ulogic; +signal ex4_l2cmdq_flush_d :std_ulogic_vector(0 to 4); +signal ex4_l2cmdq_flush_l2 :std_ulogic_vector(0 to 4); +signal ex4_st_I1_G1_val :std_ulogic; +signal st_entry_I1_G1_val :std_ulogic; +signal ex3_wimg_g_gated :std_ulogic; +signal ecc_err :std_ulogic_vector(0 to lmq_entries-1); +signal rel_vpr_compl :std_ulogic; +signal rel_compl :std_ulogic; +signal update_gpr :std_ulogic; +signal update_gpr_l2 :std_ulogic; +signal set_gpr_updated_prev :std_ulogic_vector(0 to lmq_entries-1); +signal selectedQ_gpr_update_prev :std_ulogic; +signal selectedQ_ecc_err :std_ulogic; +signal rel_beat_crit_qw_block_d :std_ulogic; +signal gpr_updated_prev_d :std_ulogic_vector(0 to lmq_entries-1); +signal gpr_updated_prev_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal gpr_updated_dly1_d :std_ulogic_vector(0 to lmq_entries-1); +signal gpr_updated_dly2_d :std_ulogic_vector(0 to lmq_entries-1); +signal gpr_updated_dly1_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal gpr_updated_dly2_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal set_gpr_ecc_err :std_ulogic_vector(0 to lmq_entries-1); +signal reset_gpr_ecc_err :std_ulogic_vector(0 to lmq_entries-1); +signal gpr_ecc_err_d :std_ulogic_vector(0 to lmq_entries-1); +signal gpr_ecc_err_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal complete_qentry :std_ulogic_vector(0 to lmq_entries-1); +signal even_beat :std_ulogic_vector(0 to lmq_entries-1); +signal ldm_complete_qentry :std_ulogic_vector(0 to lmq_entries-1); +signal ldm_comp_qentry_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal ci_16B_comp_qentry :std_ulogic_vector(0 to lmq_entries-1); +signal larx_done :std_ulogic_vector(0 to lmq_entries-1); +signal complete_tid_d :std_ulogic_vector(0 to 3); +signal larx_done_tid_d :std_ulogic_vector(0 to 3); +signal larx_done_tid_l2 :std_ulogic_vector(0 to 3); +signal complete_target_type_d :std_ulogic_vector(0 to 1); + +signal mmq_act :std_ulogic; +signal mmu_q_val_d :std_ulogic; +signal mmu_q_val_l2 :std_ulogic; +signal mm_req_val_d :std_ulogic; +signal mm_req_val_l2 :std_ulogic; +signal mmu_command :std_ulogic_vector(0 to (25+real_data_add)); +signal mmu_q_entry_d :std_ulogic_vector(0 to (25+real_data_add)); +signal mmu_q_entry_l2 :std_ulogic_vector(0 to (25+real_data_add)); + +signal my_beat1 :std_ulogic; +signal my_beat1_early :std_ulogic; +signal my_beat_last_d :std_ulogic; +signal my_beat_last_l2 :std_ulogic; +signal my_beat_mid :std_ulogic; +signal my_beat_odd :std_ulogic; +signal my_noncache_beat :std_ulogic; +signal my_ldq_retry :std_ulogic; + +signal rel_A_data_d :std_ulogic_vector(0 to 127); +signal rel_A_data_l2 :std_ulogic_vector(0 to 127); +signal rel_B_data_d :std_ulogic_vector(0 to 127); +signal rel_B_data_l2 :std_ulogic_vector(0 to 127); +signal set_rel_A_data :std_ulogic; +signal set_rel_B_data :std_ulogic; +signal send_rel_A_data_d :std_ulogic; +signal send_rel_A_data_l2 :std_ulogic; + +signal anaclat_data_coming :std_ulogic; +signal anaclat_reld_crit_qw :std_ulogic; +signal anaclat_data_val :std_ulogic; +signal anaclat_ditc :std_ulogic; +signal anaclat_tag :std_ulogic_vector(0 to 4); +signal anaclat_qw :std_ulogic_vector(57 to 59); +signal anaclat_data :std_ulogic_vector(0 to 127); +signal anaclat_ecc_err :std_ulogic; +signal anaclat_ecc_err_ue :std_ulogic; +signal beat_ecc_err :std_ulogic; +signal ue_mchk_v :std_ulogic; +signal ue_mchk_valid_d :std_ulogic_vector(0 to 3); +signal ue_mchk_valid_l2 :std_ulogic_vector(0 to 3); +signal anaclat_l1_dump :std_ulogic; +signal dminus1_l1_dump :std_ulogic; +signal dminus1_l1_dump_gated :std_ulogic; +signal l1_dump :std_ulogic; +signal anaclat_back_inv :std_ulogic; +signal anaclat_back_inv_addr :std_ulogic_vector(64-real_data_add to 63); +signal anaclat_back_inv_target_1 :std_ulogic; +signal anaclat_back_inv_target_4 :std_ulogic; +signal anaclat_ld_pop :std_ulogic; +signal anaclat_st_pop :std_ulogic; +signal anaclat_st_pop_thrd :std_ulogic_vector(0 to 2); +signal anaclat_st_gather :std_ulogic; +signal anaclat_coreid :std_ulogic_vector(6 to 7); +signal data_val_for_rel :std_ulogic; +signal data_val_dminus2 :std_ulogic; +signal data_val_dminus1_l2 :std_ulogic; +signal ldq_rel_retry_val_l2 :std_ulogic; +signal ldq_rel_retry_val_dly_l2 :std_ulogic; +signal rel_intf_v_dminus1_l2 :std_ulogic; +signal rel_intf_v_l2 :std_ulogic; +signal rel_intf_v_dplus1_l2 :std_ulogic; +signal tag_dminus2 :std_ulogic_vector(1 to 4); +signal ldq_retry_tag :std_ulogic_vector(1 to 4); +signal tag_dminus1_l2 :std_ulogic_vector(1 to 4); +signal tag_dminus1_cpy_l2 :std_ulogic_vector(2 to 4); +signal tag_dminus1_act :std_ulogic; +signal tag_dminus1_1hot_d :std_ulogic_vector(0 to lmq_entries-1); +signal tag_dminus1_1hot_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal qw_dminus1_l2 :std_ulogic_vector(57 to 59); +signal qw_l2 :std_ulogic_vector(57 to 59); +signal back_inv_val_d :std_ulogic; +signal back_inv_val_l2 :std_ulogic; +signal dbell_val_d :std_ulogic; +signal dbell_val_l2 :std_ulogic; +signal lpidr_l2 :std_ulogic_vector(0 to 7); +signal rel_set_val :std_ulogic_vector(0 to lmq_entries-1); +signal rel_cacheable :std_ulogic_vector(0 to lmq_entries-1); +signal rel_set_val_or :std_ulogic; +signal lmq_back_invalidated_d :std_ulogic_vector(0 to lmq_entries-1); +signal lmq_back_invalidated_l2 :std_ulogic_vector(0 to lmq_entries-1); + +signal ex3_loadmiss_qentry :std_ulogic_vector(0 to lmq_entries-1); +signal ex4_loadmiss_qentry :std_ulogic_vector(0 to lmq_entries-1); +signal ex5_loadmiss_qentry_d :std_ulogic_vector(0 to lmq_entries-1); +signal ex6_loadmiss_qentry_d :std_ulogic_vector(0 to lmq_entries-1); +signal ex7_loadmiss_qentry_d :std_ulogic_vector(0 to lmq_entries-1); +signal ex5_loadmiss_qentry :std_ulogic_vector(0 to lmq_entries-1); +signal ex6_loadmiss_qentry :std_ulogic_vector(0 to lmq_entries-1); +signal ex7_loadmiss_qentry :std_ulogic_vector(0 to lmq_entries-1); +signal ex3_loadmiss_target :std_ulogic_vector(0 to 8); +signal ex3_loadmiss_target_type :std_ulogic_vector(0 to 1); +signal ex3_loadmiss_tid :std_ulogic_vector(0 to 3); +signal ex4_loadmiss_tid :std_ulogic_vector(0 to 3); +signal ex4_loadmiss_target :std_ulogic_vector(0 to 8); +signal ex4_loadmiss_target_type :std_ulogic_vector(0 to 1); +signal ex4_loadmiss_tid_gated1 :std_ulogic_vector(0 to 3); +signal ex4_loadmiss_tid_gated :std_ulogic_vector(0 to 3); +signal ex5_loadmiss_tid :std_ulogic_vector(0 to 3); + +signal xu_mm_lmq_stq_empty_d :std_ulogic; +signal lmq_empty :std_ulogic; +signal pe_recov_empty_d :std_ulogic; +signal pe_recov_empty_l2 :std_ulogic; + +signal err_l2intrf_ecc_d :std_ulogic; +signal err_l2intrf_ue_d :std_ulogic; +signal err_l2intrf_ecc_l2 :std_ulogic; +signal err_l2intrf_ue_l2 :std_ulogic; + +signal src0_hit :std_ulogic_vector(0 to lmq_entries-1); +signal src1_hit :std_ulogic_vector(0 to lmq_entries-1); +signal targ_hit :std_ulogic_vector(0 to lmq_entries-1); +signal watch_bit_v_t0 :std_ulogic_vector(0 to lmq_entries-1); +signal watch_bit_v_t1 :std_ulogic_vector(0 to lmq_entries-1); +signal watch_bit_v_t2 :std_ulogic_vector(0 to lmq_entries-1); +signal watch_bit_v_t3 :std_ulogic_vector(0 to lmq_entries-1); +signal ex1_lm_dep_hit :std_ulogic; +signal ex2_lm_dep_hit_buf :std_ulogic; +signal watch_hit_t0 :std_ulogic; +signal watch_hit_t1 :std_ulogic; +signal watch_hit_t2 :std_ulogic; +signal watch_hit_t3 :std_ulogic; +signal watch_hit :std_ulogic; + +signal lq_rd_en_is_ex5 :std_ulogic; +signal lq_rd_en_is_ex6 :std_ulogic; + + +signal lmq_quiesce :std_ulogic_vector(0 to 3); +signal mmu_quiesce :std_ulogic_vector(0 to 3); +signal stq_quiesce :std_ulogic_vector(0 to 3); +signal quiesce_d :std_ulogic_vector(0 to 3); + +signal ex3_flush_all :std_ulogic; +signal ex4_flush_load :std_ulogic; +signal ex4_flush_load_wo_drop :std_ulogic; +signal ex4_flush_store :std_ulogic; +signal ex5_load :std_ulogic; +signal ex6_load_sent_l2 :std_ulogic; +signal ex6_store_sent_l2 :std_ulogic; +signal ex5_flush_d :std_ulogic; +signal ex5_flush_l2 :std_ulogic; +signal my_ex5_flush :std_ulogic; +signal ex5_flush_load_all :std_ulogic; +signal ex5_flush_load_local :std_ulogic; +signal ex4_p_addr_59 :std_ulogic; +signal ex5_stg_flush :std_ulogic; +signal ex5_flush_store :std_ulogic; +signal my_ex5_flush_store :std_ulogic; +signal ex6_flush_l2 :std_ulogic; + + +signal copy_st_be_for_16B_mode :std_ulogic; +signal copy_st_data_for_16B_mode :std_ulogic; + +signal err_invld_reld_d :std_ulogic; +signal err_invld_reld_l2 :std_ulogic; + +signal ex7_ld_par_err :std_ulogic; +signal ex8_ld_par_err_l2 :std_ulogic; +signal ex4_ld_queue_full :std_ulogic; +signal ex4_ld_queue_full_l2 :std_ulogic; +signal ex5_ld_queue_full_d :std_ulogic; +signal ex5_ld_queue_full_l2 :std_ulogic; +signal ex4_st_queue_full :std_ulogic; +signal ex4_st_queue_full_l2 :std_ulogic; +signal ex5_st_queue_full_l2 :std_ulogic; +signal ex4_ldhld_sthld_coll :std_ulogic; +signal ex5_ldhld_sthld_coll_l2 :std_ulogic; +signal ex3_i1_g1_coll :std_ulogic; +signal ex4_i1_g1_coll_l2 :std_ulogic; +signal ex5_i1_g1_coll_l2 :std_ulogic; +signal ld_miss_latency_d :std_ulogic; +signal ld_miss_latency_l2 :std_ulogic; +signal lsu_perf_events :std_ulogic_vector(0 to 3); +signal lsu_perf_events_l2 :std_ulogic_vector(0 to 3); +signal ex3_val_req :std_ulogic; +signal ex4_val_req :std_ulogic; +signal ex4_thrd_encode :std_ulogic_vector(0 to 1); +signal ex4_thrd_id :std_ulogic_vector(0 to 3); +signal ex5_thrd_id :std_ulogic_vector(0 to 3); + +signal ob_pwr_tok_l2 :std_ulogic; +signal ob_req_val_mux :std_ulogic; +signal ob_req_val_l2 :std_ulogic; +signal ob_req_val_clone_l2 :std_ulogic; +signal ob_ditc_val_mux :std_ulogic; +signal ob_ditc_val_l2 :std_ulogic; +signal ob_ditc_val_clone_l2 :std_ulogic; +signal ob_thrd_mux :std_ulogic_vector(0 to 1); +signal ob_thrd_l2 :std_ulogic_vector(0 to 1); +signal ob_qw_mux :std_ulogic_vector(58 to 59); +signal ob_qw_l2 :std_ulogic_vector(58 to 59); +signal ob_dest_mux :std_ulogic_vector(0 to 14); +signal ob_dest_l2 :std_ulogic_vector(0 to 14); +signal ob_addr_mux :std_ulogic_vector(64-real_data_add to 57); +signal ob_addr_l2 :std_ulogic_vector(64-real_data_add to 57); +signal ob_data_mux :std_ulogic_vector(0 to 127); +signal ob_data_l2 :std_ulogic_vector(0 to 127); +signal bx_cmd_sent_d :std_ulogic; +signal bx_cmd_sent_l2 :std_ulogic; +signal bx_cmd_stall_d :std_ulogic; +signal bx_cmd_stall_l2 :std_ulogic; +signal bx_stall_dly_or :std_ulogic; +signal bx_stall_dly_d :std_ulogic_vector(0 to 3); +signal bx_stall_dly_l2 :std_ulogic_vector(0 to 3); +signal msr_gs_l2 :std_ulogic_vector(0 to 3); +signal msr_pr_l2 :std_ulogic_vector(0 to 3); +signal msr_ds_l2 :std_ulogic_vector(0 to 3); +signal msr_hv :std_ulogic; +signal msr_pr :std_ulogic; +signal msr_ds :std_ulogic; +signal pid :std_ulogic_vector(0 to 13); +signal pid0_l2 :std_ulogic_vector(0 to 13); +signal pid1_l2 :std_ulogic_vector(0 to 13); +signal pid2_l2 :std_ulogic_vector(0 to 13); +signal pid3_l2 :std_ulogic_vector(0 to 13); +signal ditc_dat :std_ulogic_vector(0 to 127); +signal ex4_icswx_extra_data :std_ulogic_vector(0 to 24); +signal stq_icswx_extra_data_d :std_ulogic_vector(0 to 24); +signal stq_icswx_extra_data_l2 :std_ulogic_vector(0 to 24); +signal icswx_dat :std_ulogic_vector(0 to 127); +signal epsc_epr :std_ulogic; +signal epsc_eas :std_ulogic; +signal epsc_egs :std_ulogic; +signal epsc_elpid :std_ulogic_vector(40 to 47); +signal epsc_epid :std_ulogic_vector(50 to 63); + +signal my_xucr0_d :std_ulogic_vector(0 to 5); +signal my_xucr0_l2 :std_ulogic_vector(0 to 5); +signal my_xucr0_rel :std_ulogic; +signal my_xucr0_l2siw :std_ulogic; +signal my_xucr0_cred :std_ulogic; +signal my_xucr0_mbar_ack :std_ulogic; +signal my_xucr0_tlbsync :std_ulogic; +signal my_xucr0_cls :std_ulogic; + +signal ex3_p_addr :std_ulogic_vector(64-real_data_add to 63); + +signal clkg_ctl_override_q :std_ulogic; +signal ldq_active_d :std_ulogic; +signal ldq_active_l2 :std_ulogic; +signal ldq_active_dly_d :std_ulogic; +signal ldq_active_dly_l2 :std_ulogic; +signal ldq_act :std_ulogic; +signal stq_active_d :std_ulogic; +signal stq_active_l2 :std_ulogic; +signal stq_act :std_ulogic; +signal lmq_entry_act :std_ulogic; +signal ifetch_act :std_ulogic; +signal iuq_act :std_ulogic; +signal ob_act :std_ulogic; +signal pe_act :std_ulogic; +signal dminus1_act :std_ulogic; +signal dplus1_act :std_ulogic; +signal rel_data_act :std_ulogic; +signal bi_act :std_ulogic; +signal ex6_ld_recov_act :std_ulogic; +signal ex7_ld_recov_act :std_ulogic; +signal ex8_ld_recov_act :std_ulogic; +signal l2req_act :std_ulogic; +signal st_data_act :std_ulogic; + +signal data_val_for_drel :std_ulogic; +signal data_val_for_recirc :std_ulogic; + +signal spare_0_lclk :clk_logic; +signal spare_1_lclk :clk_logic; +signal spare_4_lclk :clk_logic; +signal spare_0_d1clk :std_ulogic; +signal spare_1_d1clk :std_ulogic; +signal spare_4_d1clk :std_ulogic; +signal spare_0_d2clk :std_ulogic; +signal spare_1_d2clk :std_ulogic; +signal spare_4_d2clk :std_ulogic; +signal spare_0_d :std_ulogic_vector(0 to 7); +signal spare_1_d :std_ulogic_vector(0 to 4); +signal spare_4_d :std_ulogic_vector(0 to 7); +signal spare_0_l2 :std_ulogic_vector(0 to 7); +signal spare_1_l2 :std_ulogic_vector(0 to 4); +signal spare_4_l2 :std_ulogic_vector(0 to 7); + +signal dbg_d :std_ulogic_vector(0 to 40+lmq_entries-1); +signal dbg_L2 :std_ulogic_vector(0 to 40+lmq_entries-1); + + +signal unused :std_ulogic_vector(0 to 3); + +constant clkg_ctl_override_offset : natural := 0; +constant ldq_active_offset : natural :=clkg_ctl_override_offset + 1; +constant ldq_active_dly_offset : natural :=ldq_active_offset + 1; +constant stq_active_offset : natural :=ldq_active_dly_offset + 1; +constant ex7_ld_par_err_offset : natural :=stq_active_offset + 1; +constant ex8_ld_par_err_offset : natural :=ex7_ld_par_err_offset + 1; +constant my_ex4_flush_offset : natural :=ex8_ld_par_err_offset + 1; +constant pe_recov_empty_offset : natural :=my_ex4_flush_offset + 1; +constant pe_recov_state_offset : natural :=pe_recov_empty_offset + 1; + +constant pe_recov_state_dly_offset : natural :=pe_recov_state_offset + 1; +constant pe_recov_ld_num_offset : natural :=pe_recov_state_dly_offset + 1; + +constant pe_recov_ld_val_offset : natural :=pe_recov_ld_num_offset + pe_recov_ld_num_l2'length; +constant my_xucr0_offset : natural :=pe_recov_ld_val_offset + 1; +constant anac_data_coming_offset : natural :=my_xucr0_offset + my_xucr0_l2'length; +constant anac_reld_crit_qw_offset : natural :=anac_data_coming_offset + 1; +constant anac_data_val_offset : natural :=anac_reld_crit_qw_offset + 1; +constant anac_ditc_offset : natural :=anac_data_val_offset + 1; +constant anac_tag_offset : natural :=anac_ditc_offset + 1; +constant anac_qw_offset : natural :=anac_tag_offset + anaclat_tag'length; +constant anac_data_offset : natural :=anac_qw_offset + anaclat_qw'length; +constant anac_ecc_err_offset : natural :=anac_data_offset + anaclat_data'length; +constant anac_ecc_err_ue_offset : natural :=anac_ecc_err_offset + 1; +constant ue_mchk_val_offset : natural := anac_ecc_err_ue_offset + 1; +constant anac_l1_dump_offset : natural := ue_mchk_val_offset + ue_mchk_valid_l2'length; +constant dminus1_l1_dump_offset : natural := anac_l1_dump_offset + 1; +constant l1_dump_offset : natural := dminus1_l1_dump_offset + 1; +constant anac_back_inv_offset : natural := l1_dump_offset + 1; +constant anac_back_inv_addr_offset : natural := anac_back_inv_offset + 1; +constant anac_back_inv_target1_offset : natural := anac_back_inv_addr_offset + anaclat_back_inv_addr'length; +constant anac_back_inv_target4_offset : natural :=anac_back_inv_target1_offset + 1; +constant data_val_dminus1_offset : natural :=anac_back_inv_target4_offset + 1; +constant spare_0_offset : natural :=data_val_dminus1_offset + 1; +constant ldq_rel_retry_val_offset : natural :=spare_0_offset + spare_0_l2'length; +constant ldq_rel_retry_val_dly_offset : natural :=ldq_rel_retry_val_offset + 1; +constant rel_intf_v_dminus1_offset : natural :=ldq_rel_retry_val_dly_offset + 1; +constant rel_intf_v_offset : natural :=rel_intf_v_dminus1_offset + 1; +constant rel_intf_v_dplus1_offset : natural :=rel_intf_v_offset + 1; +constant retry_started_offset : natural :=rel_intf_v_dplus1_offset + 1; + +constant tag_dminus1_offset : natural :=retry_started_offset + retry_started_l2'length; +constant tag_dminus1_cpy_offset : natural :=tag_dminus1_offset + tag_dminus1_l2'length; +constant tag_dminus1_1hot_offset : natural :=tag_dminus1_cpy_offset + tag_dminus1_cpy_l2'length; +constant qw_dminus1_offset : natural :=tag_dminus1_1hot_offset + tag_dminus1_1hot_l2'length; + +constant qw_offset : natural :=qw_dminus1_offset + qw_dminus1_l2'length; +constant back_inv_val_offset : natural :=qw_offset + qw_l2'length; +constant dbell_val_offset : natural :=back_inv_val_offset + 1; +constant anac_ld_pop_offset : natural :=dbell_val_offset + 1; +constant anac_st_pop_offset : natural :=anac_ld_pop_offset + 1; +constant anac_st_pop_thrd_offset : natural :=anac_st_pop_offset + 1; +constant anac_st_gather_offset : natural :=anac_st_pop_thrd_offset + anaclat_st_pop_thrd'length; +constant coreid_offset : natural :=anac_st_gather_offset + 1; +constant stcx_complete_offset : natural :=coreid_offset + anaclat_coreid'length; +constant xu_iu_reld_core_tag_offset : natural :=stcx_complete_offset + xu_iu_stcx_complete'length; +constant xu_iu_reld_data_vld_offset : natural :=xu_iu_reld_core_tag_offset + xu_iu_reld_core_tag_clone'length; +constant xu_iu_reld_data_coming_offset : natural :=xu_iu_reld_data_vld_offset + 1; +constant xu_iu_reld_ditc_offset : natural :=xu_iu_reld_data_coming_offset + 1; +constant lpidr_offset : natural :=xu_iu_reld_ditc_offset + 1; +constant cmd_seq_offset : natural :=lpidr_offset + lpidr_l2'length; +constant cmd_seq_rd_offset : natural :=cmd_seq_offset + cmd_seq_l2'length; +constant ex4_load_l1hit_val_offset : natural :=cmd_seq_rd_offset + cmd_seq_rd_l2'length; +constant ex4_st_val_offset : natural :=ex4_load_l1hit_val_offset + 1; +constant ex5_st_val_offset : natural :=ex4_st_val_offset + 1; +constant ex6_st_val_offset : natural :=ex5_st_val_offset + 1; +constant st_entry0_val_offset : natural :=ex6_st_val_offset + 1; +constant st_entry0_val_clone_offset : natural :=st_entry0_val_offset + 1; +constant ex4_st_entry_offset : natural :=st_entry0_val_clone_offset + 1; +constant s_m_queue0_offset : natural :=ex4_st_entry_offset + ex4_st_entry_l2'length; + + +constant ex4_ld_m_val_offset : natural :=s_m_queue0_offset + s_m_queue0'length; + +constant spare_1_offset : natural :=ex4_ld_m_val_offset + 1; +constant ex4_classid_offset : natural :=spare_1_offset + spare_1_l2'length; +constant ex4_ld_entry_hit_st_offset : natural :=ex4_classid_offset + ex4_classid_l2'length; +constant ex4_drop_ld_req_offset : natural :=ex4_ld_entry_hit_st_offset + 1; + +constant ex4_drop_touch_offset : natural :=ex4_drop_ld_req_offset + 1; +constant lmq_drop_rel_offset : natural :=ex4_drop_touch_offset + 1; + +constant lmq_dvc1_en_offset : natural :=lmq_drop_rel_offset + lmq_drop_rel_l2'length; +constant lmq_dvc2_en_offset : natural :=lmq_dvc1_en_offset + lmq_dvc1_en_l2'length; +constant l_m_queue_offset : natural :=lmq_dvc2_en_offset + lmq_dvc2_en_l2'length; +constant l_m_queue_addrlo_offset : natural :=l_m_queue_offset + lmq_entries * l_m_queue(0)'length; +constant ex4_ld_recov_offset : natural :=l_m_queue_addrlo_offset + lmq_entries * l_m_queue_addrlo(0)'length; +constant ex4_ld_recov_val_offset : natural :=ex4_ld_recov_offset + ex4_ld_entry_l2'length; +constant ex5_ld_recov_offset : natural :=ex4_ld_recov_val_offset + 1; +constant ex6_ld_recov_offset : natural :=ex5_ld_recov_offset + ex5_ld_recov_l2'length; +constant ex7_ld_recov_offset : natural :=ex6_ld_recov_offset + ex6_ld_recov_l2'length; +constant ex5_ld_recov_extra_offset : natural :=ex7_ld_recov_offset + ex7_ld_recov_l2'length; +constant ex6_ld_recov_extra_offset : natural :=ex5_ld_recov_extra_offset + ex5_ld_recov_extra_l2'length; +constant ex7_ld_recov_extra_offset : natural :=ex6_ld_recov_extra_offset + ex6_ld_recov_extra_l2'length; +constant ex8_ld_recov_extra_offset : natural :=ex7_ld_recov_extra_offset + ex7_ld_recov_extra_l2'length; +constant ex5_ld_recov_val_offset : natural :=ex8_ld_recov_extra_offset + ex8_ld_recov_extra_l2'length; +constant ex6_ld_recov_val_offset : natural :=ex5_ld_recov_val_offset + 1; +constant ex7_ld_recov_val_offset : natural :=ex6_ld_recov_val_offset + 1; +constant st_hit_recov_ld_offset : natural :=ex7_ld_recov_val_offset + 1; +constant l_m_fnd_offset : natural :=st_hit_recov_ld_offset + 1; +constant ex4_lmq_cpy_offset : natural :=l_m_fnd_offset + 1; +constant ex5_lmq_cpy_offset : natural :=ex4_lmq_cpy_offset + ex4_lmq_cpy_l2'length; +constant lm_dep_hit_offset : natural :=ex5_lmq_cpy_offset + ex5_lmq_cpy_l2'length; +constant lmq_back_invalidated_offset : natural :=lm_dep_hit_offset + 1; +constant ld_entry_val_offset : natural :=lmq_back_invalidated_offset + lmq_back_invalidated_l2'length; +constant ld_rel_val_offset : natural :=ld_entry_val_offset + ld_entry_val_l2'length; +constant l_m_q_hit_st_offset : natural :=ld_rel_val_offset + ld_rel_val_l2'length; +constant ifetch_req_offset : natural :=l_m_q_hit_st_offset + l_m_q_hit_st_l2'length; +constant ifetch_ra_offset : natural :=ifetch_req_offset + 1; +constant ifetch_wimge_offset : natural :=ifetch_ra_offset + ifetch_ra_l2'length; +constant ifetch_thread_offset : natural :=ifetch_wimge_offset + ifetch_wimge_l2'length; +constant ifetch_userdef_offset : natural :=ifetch_thread_offset + ifetch_thread_l2'length; +constant iu_seq_offset : natural :=ifetch_userdef_offset + ifetch_userdef_l2'length; +constant iu_seq_rd_offset : natural :=iu_seq_offset + iu_seq_l2'length; +constant i_f_q0_val_offset : natural :=iu_seq_rd_offset + iu_seq_rd_l2'length; +constant i_f_q0_offset : natural :=i_f_q0_val_offset + 1; +constant i_f_q1_val_offset : natural :=i_f_q0_offset + i_f_q0_l2'length; +constant i_f_q1_offset : natural :=i_f_q1_val_offset + 1; +constant i_f_q2_val_offset : natural :=i_f_q1_offset + i_f_q1_l2'length; +constant i_f_q2_offset : natural :=i_f_q2_val_offset + 1; +constant i_f_q3_val_offset : natural :=i_f_q2_offset + i_f_q2_l2'length; +constant i_f_q3_offset : natural :=i_f_q3_val_offset + 1; +constant mm_req_val_offset : natural :=i_f_q3_offset + i_f_q3_l2'length; +constant mmu_q_val_offset : natural :=mm_req_val_offset + 1; +constant mmu_q_entry_offset : natural :=mmu_q_val_offset + 1; +constant cred_overrun_offset : natural :=mmu_q_entry_offset + mmu_q_entry_l2'length; +constant reld_ditc_pop_offset : natural :=cred_overrun_offset + 1; +constant bx_ib_empty_offset : natural :=reld_ditc_pop_offset + ac_an_reld_ditc_pop_q'length; +constant send_if_req_offset : natural :=bx_ib_empty_offset + bx_ib_empty_q'length; +constant send_ld_req_offset : natural :=send_if_req_offset + 1; +constant send_mm_req_offset : natural :=send_ld_req_offset + 1; +constant l_m_rel_hit_beat0_offset : natural :=send_mm_req_offset + 1; +constant l_m_rel_hit_beat1_offset : natural :=l_m_rel_hit_beat0_offset + l_m_rel_hit_beat0_l2'length; +constant l_m_rel_hit_beat2_offset : natural :=l_m_rel_hit_beat1_offset + l_m_rel_hit_beat1_l2'length; +constant l_m_rel_hit_beat3_offset : natural :=l_m_rel_hit_beat2_offset + l_m_rel_hit_beat2_l2'length; +constant l_m_rel_hit_beat4_offset : natural :=l_m_rel_hit_beat3_offset + l_m_rel_hit_beat3_l2'length; +constant l_m_rel_hit_beat5_offset : natural :=l_m_rel_hit_beat4_offset + l_m_rel_hit_beat4_l2'length; +constant l_m_rel_hit_beat6_offset : natural :=l_m_rel_hit_beat5_offset + l_m_rel_hit_beat5_l2'length; +constant l_m_rel_hit_beat7_offset : natural :=l_m_rel_hit_beat6_offset + l_m_rel_hit_beat6_l2'length; +constant l_m_rel_inprog_offset : natural :=l_m_rel_hit_beat7_offset + l_m_rel_hit_beat7_l2'length; +constant l_m_rel_c_i_beat0_offset : natural :=l_m_rel_inprog_offset + l_m_rel_inprog_l2'length; +constant l_m_rel_c_i_val_offset : natural :=l_m_rel_c_i_beat0_offset + l_m_rel_c_i_beat0_l2'length; +constant rel_addr_offset : natural :=l_m_rel_c_i_val_offset + l_m_rel_val_c_i_dly'length; +constant rel_size_offset : natural :=rel_addr_offset + rel_addr_l2'length; +constant rel_cache_inh_offset : natural :=rel_size_offset + rel_size_l2'length; +constant rel_rot_sel_offset : natural :=rel_cache_inh_offset + 1; +constant rel_th_id_offset : natural :=rel_rot_sel_offset + rel_rot_sel_l2'length; +constant rel_tar_gpr_offset : natural :=rel_th_id_offset + rel_th_id_l2'length; +constant rel_vpr_val_offset : natural :=rel_tar_gpr_offset + rel_tar_gpr_l2'length; +constant rel_le_mode_offset : natural :=rel_vpr_val_offset + 1; +constant rel_dcbt_offset : natural :=rel_le_mode_offset + 1; +constant rel_algebraic_offset : natural :=rel_dcbt_offset + 1; +constant rel_l2only_offset : natural :=rel_algebraic_offset + 1; +constant rel_l2only_dly_offset : natural :=rel_l2only_offset + 1; +constant rel_lock_en_offset : natural :=rel_l2only_dly_offset + 1; +constant rel_classid_offset : natural :=rel_lock_en_offset + 1; +constant rel_dvc1_offset : natural :=rel_classid_offset + rel_classid_l2'length; +constant rel_dvc2_offset : natural :=rel_dvc1_offset + 1; +constant rel_watch_en_offset : natural :=rel_dvc2_offset + 1; +constant reld_data_vld_offset : natural :=rel_watch_en_offset + 1; +constant rel_tag_offset : natural :=reld_data_vld_offset + 1; +constant reld_data_vld_dplus1_offset : natural :=rel_tag_offset + rel_tag_l2'length; +constant rel_tag_dplus1_offset : natural :=reld_data_vld_dplus1_offset + 1; +constant data_ecc_err_offset : natural :=rel_tag_dplus1_offset + rel_tag_dplus1_l2'length; +constant data_ecc_ue_offset : natural :=data_ecc_err_offset + data_ecc_err_l2'length; +constant ld_m_rel_done_offset : natural :=data_ecc_ue_offset + data_ecc_ue_l2'length; +constant ldq_retry_offset : natural :=ld_m_rel_done_offset + ld_m_rel_done_l2'length; +constant ld_m_rel_done_dly_offset : natural :=ldq_retry_offset + ldq_retry_l2'length; +constant ld_m_rel_done_dly2_offset : natural :=ld_m_rel_done_dly_offset + ld_m_rel_done_dly_l2'length; +constant blk_ld_for_pe_recov_offset : natural :=ld_m_rel_done_dly2_offset + ld_m_rel_done_dly2_l2'length; +constant ldq_rd_seq_match_offset : natural :=blk_ld_for_pe_recov_offset + 1; +constant ob_pwr_tok_offset : natural :=ldq_rd_seq_match_offset + ldq_rd_seq_match_l2'length; +constant ob_req_val_offset : natural :=ob_pwr_tok_offset + 1; +constant ob_req_val_clone_offset : natural :=ob_req_val_offset + 1; +constant ob_ditc_val_offset : natural :=ob_req_val_clone_offset + 1; +constant ob_ditc_val_clone_offset : natural :=ob_ditc_val_offset + 1; +constant ob_thrd_offset : natural :=ob_ditc_val_clone_offset + 1; +constant ob_qw_offset : natural :=ob_thrd_offset + ob_thrd_l2'length; +constant ob_dest_offset : natural :=ob_qw_offset + ob_qw_l2'length; +constant ob_addr_offset : natural :=ob_dest_offset + ob_dest_l2'length; +constant ob_data_offset : natural :=ob_addr_offset + ob_addr_l2'length; +constant ex5_sel_st_req_offset : natural :=ob_data_offset + ob_data_l2'length; +constant bx_cmd_sent_offset : natural :=ex5_sel_st_req_offset + 1; +constant bx_cmd_stall_offset : natural :=bx_cmd_sent_offset + 1; +constant bx_stall_dly_offset : natural :=bx_cmd_stall_offset + 1; +constant xu_mm_lsu_token_offset : natural :=bx_stall_dly_offset + bx_stall_dly_l2'length; +constant ex4_val_req_offset : natural :=xu_mm_lsu_token_offset + 1; +constant ex4_thrd_id_offset : natural :=ex4_val_req_offset + 1; +constant ex5_thrd_id_offset : natural :=ex4_thrd_id_offset + ex4_thrd_id'length; +constant lmq_collision_t0_offset : natural :=ex5_thrd_id_offset + ex5_thrd_id'length; +constant lmq_collision_t1_offset : natural :=lmq_collision_t0_offset + lmq_collision_t0_l2'length; +constant lmq_collision_t2_offset : natural :=lmq_collision_t1_offset + lmq_collision_t1_l2'length; +constant lmq_collision_t3_offset : natural :=lmq_collision_t2_offset + lmq_collision_t2_l2'length; +constant ldq_barr_active_offset : natural :=lmq_collision_t3_offset + lmq_collision_t3_l2'length; +constant l2req_resend_offset : natural :=ldq_barr_active_offset + ldq_barr_active_l2'length; +constant l2req_recycle_offset : natural :=l2req_resend_offset + 1; +constant l2req_pwr_token_offset : natural :=l2req_recycle_offset + 1; +constant l2req_st_data_ptoken_offset : natural :=l2req_pwr_token_offset + 1; +constant l2req_ttype_offset : natural :=l2req_st_data_ptoken_offset+ 1; +constant l2req_wimg_offset : natural :=l2req_ttype_offset + l2req_ttype'length; +constant l2req_user_offset : natural :=l2req_wimg_offset + l2req_wimg'length; +constant l2req_offset : natural :=l2req_user_offset + l2req_user'length; +constant l2req_ld_core_tag_offset : natural :=l2req_offset + 1; +constant l2req_ra_offset : natural :=l2req_ld_core_tag_offset + l2req_ld_core_tag'length; +constant l2req_st_byte_enbl_offset : natural :=l2req_ra_offset + l2req_ra'length; +constant l2req_thread_offset : natural :=l2req_st_byte_enbl_offset + l2req_st_byte_enbl'length; +constant l2req_endian_offset : natural :=l2req_thread_offset + l2req_thread'length; +constant l2req_ld_xfr_len_offset : natural :=l2req_endian_offset + 1; +constant spare_ctrl_a0_offset : natural :=l2req_ld_xfr_len_offset + l2req_ld_xfr_len'length; +constant spare_ctrl_a1_offset : natural :=spare_ctrl_a0_offset + ac_an_req_spare_ctrl_a0'length; +constant st_recycle_offset : natural :=spare_ctrl_a1_offset + an_ac_req_spare_ctrl_a1'length; +constant st_recycle_v_offset : natural :=st_recycle_offset + st_recycle_l2'length; +constant ex6_load_sent_offset : natural :=st_recycle_v_offset + 1; +constant load_sent_dbglat_offset : natural :=ex6_load_sent_offset + 1; +constant ex6_store_sent_offset : natural :=load_sent_dbglat_offset + 1; +constant ex5_flush_offset : natural :=ex6_store_sent_offset + 1; +constant ex6_flush_offset : natural :=ex5_flush_offset + 1; +constant msr_gs_offset : natural :=ex6_flush_offset + 1; +constant msr_pr_offset : natural :=msr_gs_offset + msr_gs_l2'length; +constant msr_ds_offset : natural :=msr_pr_offset + msr_pr_l2'length; +constant pid0_offset : natural :=msr_ds_offset + msr_ds_l2'length; +constant pid1_offset : natural :=pid0_offset + pid0_l2'length; +constant pid2_offset : natural :=pid1_offset + pid1_l2'length; +constant pid3_offset : natural :=pid2_offset + pid2_l2'length; +constant stq_icswx_extra_data_offset : natural :=pid3_offset + pid3_l2'length; +constant ex4_p_addr_59_offset : natural :=stq_icswx_extra_data_offset + stq_icswx_extra_data_l2'length; +constant ex5_st_data_offset : natural :=ex4_p_addr_59_offset + 1; +constant ex6_st_data_offset : natural :=ex5_st_data_offset + ex5_st_data_l2'length; +constant ex4_l2cmdq_flush_offset : natural :=ex6_st_data_offset + ac_an_st_data'length; +constant my_beat_last_offset : natural :=ex4_l2cmdq_flush_offset + ex4_l2cmdq_flush_l2'length; +constant loadmiss_qentry_offset : natural :=my_beat_last_offset + 1; +constant ex5_loadmiss_qentry_offset : natural :=loadmiss_qentry_offset + ex4_loadmiss_qentry'length; +constant ex6_loadmiss_qentry_offset : natural :=ex5_loadmiss_qentry_offset + ex5_loadmiss_qentry'length; +constant ex7_loadmiss_qentry_offset : natural :=ex6_loadmiss_qentry_offset + ex6_loadmiss_qentry'length; +constant ex4_loadmiss_target_offset : natural :=ex7_loadmiss_qentry_offset + ex7_loadmiss_qentry'length; +constant loadmiss_target_offset : natural :=ex4_loadmiss_target_offset + xu_iu_ex5_loadmiss_target'length; +constant ex4_loadmiss_target_type_offset : natural :=loadmiss_target_offset + xu_iu_ex5_loadmiss_target'length; +constant loadmiss_target_type_offset : natural :=ex4_loadmiss_target_type_offset + ex4_loadmiss_target_type'length; +constant ex4_loadmiss_tid_offset : natural :=loadmiss_target_type_offset + xu_iu_ex5_loadmiss_target_type'length; +constant loadmiss_tid_offset : natural :=ex4_loadmiss_tid_offset + ex4_loadmiss_tid'length; +constant ldm_comp_qentry_offset : natural :=loadmiss_tid_offset + xu_iu_ex5_loadmiss_tid'length; +constant complete_qentry_offset : natural :=ldm_comp_qentry_offset + ldm_comp_qentry_l2'length; +constant complete_tid_offset : natural :=complete_qentry_offset + xu_iu_complete_qentry'length; +constant complete_target_type_offset : natural :=complete_tid_offset + xu_iu_complete_tid'length; +constant larx_done_tid_offset : natural :=complete_target_type_offset + xu_iu_complete_target_type'length; +constant update_gpr_offset : natural :=larx_done_tid_offset + xu_iu_larx_done_tid'length; +constant rel_beat_crit_qw_offset : natural :=update_gpr_offset + 1; +constant rel_beat_crit_qw_block_offset : natural :=rel_beat_crit_qw_offset + 1; +constant gpr_updated_prev_offset : natural :=rel_beat_crit_qw_block_offset + 1; +constant gpr_updated_dly1_offset : natural :=gpr_updated_prev_offset + gpr_updated_prev_l2'length; +constant gpr_updated_dly2_offset : natural :=gpr_updated_dly1_offset + gpr_updated_dly1_l2'length; +constant gpr_ecc_err_offset : natural :=gpr_updated_dly2_offset + gpr_updated_dly2_l2'length; +constant spare_4_offset : natural :=gpr_ecc_err_offset + gpr_ecc_err_l2'length; +constant rel_A_data_offset : natural :=spare_4_offset + spare_4_l2'length; +constant rel_B_data_offset : natural :=rel_A_data_offset + rel_A_data_l2'length; +constant send_rel_A_data_offset : natural :=rel_B_data_offset + rel_B_data_l2'length * a2mode; +constant ldq_barr_done_offset : natural :=send_rel_A_data_offset + 1 * a2mode; +constant sync_done_tid_offset : natural :=ldq_barr_done_offset + ldq_barr_done'length; +constant lmq_stq_empty_offset : natural :=sync_done_tid_offset + sync_done_tid'length; +constant quiesce_offset : natural :=lmq_stq_empty_offset + 1; +constant err_l2intrf_ecc_offset : natural :=quiesce_offset + lsu_xu_quiesce'length; +constant err_l2intrf_ue_offset : natural :=err_l2intrf_ecc_offset + 1; +constant err_invld_reld_offset : natural :=err_l2intrf_ue_offset + 1; +constant ex4_ld_queue_full_offset : natural :=err_invld_reld_offset + 1; +constant ex5_ld_queue_full_offset : natural :=ex4_ld_queue_full_offset + 1; +constant ex4_st_queue_full_offset : natural :=ex5_ld_queue_full_offset + 1; +constant ex5_st_queue_full_offset : natural :=ex4_st_queue_full_offset + 1; +constant ex5_ldhld_sthld_coll_offset : natural :=ex5_st_queue_full_offset + 1; +constant ex4_i1_g1_coll_offset : natural :=ex5_ldhld_sthld_coll_offset + 1; +constant ex5_i1_g1_coll_offset : natural :=ex4_i1_g1_coll_offset + 1; +constant ld_miss_latency_offset : natural :=ex5_i1_g1_coll_offset + 1; +constant lsu_perf_events_offset : natural :=ld_miss_latency_offset + 1; +constant dbg_offset : natural :=lsu_perf_events_offset + lsu_perf_events_l2'length; +constant scan_right : natural :=dbg_offset + dbg_l2'length; + +signal siv : std_ulogic_vector(0 to scan_right-1); +signal sov : std_ulogic_vector(0 to scan_right-1); + + +constant load_cmd_count_offset : natural :=0; +constant store_cmd_count_offset : natural :=load_cmd_count_offset + load_cmd_count_l2'length; +constant bcfg_scan_right : natural :=store_cmd_count_offset + store_cmd_count_l2'length; + +signal bcfg_siv : std_ulogic_vector(0 to bcfg_scan_right-1); +signal bcfg_sov : std_ulogic_vector(0 to bcfg_scan_right-1); + + +signal unused_signals : std_ulogic; + +begin + +unused_signals <= or_reduce(unused & ex4_ld_recov_entry(48) & ex7_ld_recov_l2(22 to 26) & l_miss_entry(0) & l_miss_entry(13 to 17) & l_miss_entry(22 to 38) & l_miss_entry(47 to 52) & ld_st_request(38) & anaclat_data_coming & anaclat_reld_crit_qw & anaclat_tag(0)); + +ex3_p_addr <= cmp_ex3_p_addr_o & ex3_p_addr_lwr; + + +ldq_active_d <= ex3_stg_act or pe_recov_ld_val_l2 or + (ldq_active_l2 and not lmq_empty); + +latch_clkg_ctl_override : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(clkg_ctl_override_offset to clkg_ctl_override_offset), + scout => sov(clkg_ctl_override_offset to clkg_ctl_override_offset), + din(0) => spr_xucr0_clkg_ctl_b3, + dout(0) => clkg_ctl_override_q); + +latch_ldq_active : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ldq_active_offset to ldq_active_offset), + scout => sov(ldq_active_offset to ldq_active_offset), + din(0) => ldq_active_d, + dout(0) => ldq_active_l2); + +ldq_active_dly_d <= ldq_active_l2; + +latch_ldq_active_dly : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ldq_active_dly_offset to ldq_active_dly_offset), + scout => sov(ldq_active_dly_offset to ldq_active_dly_offset), + din(0) => ldq_active_dly_d, + dout(0) => ldq_active_dly_l2); + +ldq_act <= ex3_stg_act or pe_recov_ld_val_l2 or ldq_active_l2 or ldq_active_dly_l2 or clkg_ctl_override_q; + +stq_active_d <= ex4_st_val_l2 or (l2req_recycle_l2 and ex7_ld_par_err) or + (stq_active_l2 and st_entry0_val_l2); + +latch_stq_active : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => stq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(stq_active_offset to stq_active_offset), + scout => sov(stq_active_offset to stq_active_offset), + din(0) => stq_active_d, + dout(0) => stq_active_l2); + +stq_act <= ex4_st_val_l2 or stq_active_l2 or (l2req_recycle_l2 and ex7_ld_par_err) or st_recycle_act or clkg_ctl_override_q; + + + + +c_inh <= ex3_cache_inh or ex3_byp_l1; + +dcbt_instr <= ex3_dcbt_instr or ex3_dcbtst_instr or ex3_dcbtls_instr or ex3_dcbtstls_instr; + +touch_instr <= ex3_dcbt_instr or ex3_dcbtst_instr or ex3_dcbtls_instr or ex3_dcbtstls_instr or + ex3_icbt_instr or ex3_icbtls_instr; + +l2only_instr <= (dcbt_instr and ex3_th_fld_l2) or ex3_icbt_instr or ex3_icbtls_instr; + +latch_ex7_ld_par_err : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex7_ld_par_err_offset to ex7_ld_par_err_offset), + scout => sov(ex7_ld_par_err_offset to ex7_ld_par_err_offset), + din(0) => ex6_ld_par_err, + dout(0) => ex7_ld_par_err); + +latch_ex8_ld_par_err : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex8_ld_par_err_offset to ex8_ld_par_err_offset), + scout => sov(ex8_ld_par_err_offset to ex8_ld_par_err_offset), + din(0) => ex7_ld_par_err, + dout(0) => ex8_ld_par_err_l2); + +latch_my_ex4_flush : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(my_ex4_flush_offset to my_ex4_flush_offset), + scout => sov(my_ex4_flush_offset to my_ex4_flush_offset), + din(0) => ex3_flush_all, + dout(0) => my_ex4_flush_l2); + + + +pe_recov_empty_d <= lmq_empty and pe_recov_state_l2; + +latch_pe_recov_empty : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(pe_recov_empty_offset to pe_recov_empty_offset), + scout => sov(pe_recov_empty_offset to pe_recov_empty_offset), + din(0) => pe_recov_empty_d, + dout(0) => pe_recov_empty_l2); + +pe_recov_state_d <= ex7_ld_par_err or + (pe_recov_state_l2 and not (pe_recov_ld_num_l2(3) and lmq_empty and pe_recov_empty_l2 and not pe_recov_ld_val_l2)); + +latch_pe_recov_state : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(pe_recov_state_offset to pe_recov_state_offset), + scout => sov(pe_recov_state_offset to pe_recov_state_offset), + din(0) => pe_recov_state_d, + dout(0) => pe_recov_state_l2); + +latch_pe_recov_state_dly : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(pe_recov_state_dly_offset to pe_recov_state_dly_offset), + scout => sov(pe_recov_state_dly_offset to pe_recov_state_dly_offset), + din(0) => pe_recov_state_l2, + dout(0) => pe_recov_state_dly_l2); + +lmq_pe_recov_state <= pe_recov_state_l2; + +pe_recov_ld_num_d(1) <= (pe_recov_state_l2 and lmq_empty and pe_recov_empty_l2 and (pe_recov_ld_num_l2="000")) or + (pe_recov_ld_num_l2(1) and not (lmq_empty and pe_recov_empty_l2)); +pe_recov_ld_num_d(2) <= (pe_recov_ld_num_l2(1) and lmq_empty and pe_recov_empty_l2) or + (pe_recov_ld_num_l2(2) and not (lmq_empty and pe_recov_empty_l2 and not pe_recov_ld_val_l2)); +pe_recov_ld_num_d(3) <= (pe_recov_ld_num_l2(2) and lmq_empty and pe_recov_empty_l2 and not pe_recov_ld_val_l2) or + (pe_recov_ld_num_l2(3) and not (lmq_empty and pe_recov_empty_l2 and not pe_recov_ld_val_l2)); + +pe_act <= pe_recov_state_l2 or clkg_ctl_override_q; + +latch_pe_recov_ld_num : tri_rlmreg_p + generic map (width => pe_recov_ld_num_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => pe_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(pe_recov_ld_num_offset to pe_recov_ld_num_offset + pe_recov_ld_num_l2'length-1), + scout => sov(pe_recov_ld_num_offset to pe_recov_ld_num_offset + pe_recov_ld_num_l2'length-1), + din => pe_recov_ld_num_d(1 to 3), + dout => pe_recov_ld_num_l2(1 to 3)); + +pe_recov_stall <= (ex7_ld_par_err or pe_recov_state_l2) and not (lmq_empty and pe_recov_empty_l2); + + +pe_recov_ld_val_d <= pe_recov_state_l2 and lmq_empty and not ld_m_val and + (ex7_ld_recov_val_l2 or (ex6_ld_recov_val_l2 and not pe_recov_stall)); + +latch_pe_recov_ld_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(pe_recov_ld_val_offset to pe_recov_ld_val_offset), + scout => sov(pe_recov_ld_val_offset to pe_recov_ld_val_offset), + din(0) => pe_recov_ld_val_d, + dout(0) => pe_recov_ld_val_l2); + + +recov_ignr_flush_d <= or_reduce(pe_recov_ld_num_l2); + + + + + + + +ex3_flush_all <= ex3_stg_flush or I1_G1_flush; + +ex4_flush_load <= (ex7_ld_par_err or ex8_ld_par_err_l2 or ex4_drop_ld_req or l_m_fnd_stg or my_ex4_flush_l2) and not recov_ignr_flush_d; + +ex4_flush_load_wo_drop <= ex7_ld_par_err or l_m_fnd_stg or my_ex4_flush_l2 or + (ex4_drop_touch and ex4_ld_recov(38)); +ex4_flush_store <= (ex7_ld_par_err or ex8_ld_par_err_l2 or l_m_fnd_stg or (ex4_load_l1hit_val and not ex4_drop_ld_req) or my_ex4_flush_l2) or + ((ex4_st_entry_l2(0 to 4) = "10010") and ex4_drop_ld_req); + +ex5_flush_load_all <= my_ex5_flush and not recov_ignr_flush_d; +ex5_flush_load_local <= ex5_flush_l2 and not recov_ignr_flush_d; + +my_xucr0_d <= xu_lsu_spr_xucr0_rel & xu_lsu_spr_xucr0_l2siw & xu_lsu_spr_xucr0_cred & + xu_lsu_spr_xucr0_mbar_ack & xu_lsu_spr_xucr0_tlbsync & xu_lsu_spr_xucr0_cls; + +latch_my_xucr0 : tri_rlmreg_p + generic map (width => my_xucr0_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(my_xucr0_offset to my_xucr0_offset + my_xucr0_l2'length-1), + scout => sov(my_xucr0_offset to my_xucr0_offset + my_xucr0_l2'length-1), + din => my_xucr0_d, + dout => my_xucr0_l2); + +my_xucr0_rel <= my_xucr0_l2(0); +my_xucr0_l2siw <= my_xucr0_l2(1); +my_xucr0_cred <= my_xucr0_l2(2); +my_xucr0_mbar_ack <= my_xucr0_l2(3); +my_xucr0_tlbsync <= my_xucr0_l2(4); +my_xucr0_cls <= my_xucr0_l2(5); + + + +latch_anac_data_coming : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(anac_data_coming_offset to anac_data_coming_offset), + scout => sov(anac_data_coming_offset to anac_data_coming_offset), + din(0) => an_ac_reld_data_coming, + dout(0) => anaclat_data_coming); + +latch_anac_reld_crit_qw : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(anac_reld_crit_qw_offset to anac_reld_crit_qw_offset), + scout => sov(anac_reld_crit_qw_offset to anac_reld_crit_qw_offset), + din(0) => an_ac_reld_crit_qw, + dout(0) => anaclat_reld_crit_qw); + +latch_anac_ditc : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(anac_ditc_offset to anac_ditc_offset), + scout => sov(anac_ditc_offset to anac_ditc_offset), + din(0) => an_ac_reld_ditc, + dout(0) => anaclat_ditc); + +latch_anac_data_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(anac_data_val_offset to anac_data_val_offset), + scout => sov(anac_data_val_offset to anac_data_val_offset), + din(0) => an_ac_reld_data_val, + dout(0) => anaclat_data_val); + +ldqretry: process (ldq_retry_l2, retry_started_l2) + variable b: std_ulogic; +begin + b := '0'; + for i in 0 to lmq_entries-1 loop + b := (ldq_retry_l2(i) and not retry_started_l2(i)) or b; + end loop; + ldq_retry_or <= b; +end process; + +data_val_for_rel <= anaclat_data_val and not anaclat_ditc; +data_val_dminus2 <= data_val_for_rel or ldq_retry_or; +data_val_for_drel <= anaclat_data_val and not (anaclat_ditc or anaclat_tag(1)); +data_val_for_recirc <= ldq_retry_or and not data_val_for_drel; + +latch_data_val_dminus1 : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(data_val_dminus1_offset to data_val_dminus1_offset), + scout => sov(data_val_dminus1_offset to data_val_dminus1_offset), + din(0) => data_val_dminus2, + dout(0) => data_val_dminus1_l2); + +latch_ldq_rel_retry_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ldq_rel_retry_val_offset to ldq_rel_retry_val_offset), + scout => sov(ldq_rel_retry_val_offset to ldq_rel_retry_val_offset), + din(0) => data_val_for_recirc, + dout(0) => ldq_rel_retry_val_l2); + +latch_ldq_rel_retry_val_dly : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ldq_rel_retry_val_dly_offset to ldq_rel_retry_val_dly_offset), + scout => sov(ldq_rel_retry_val_dly_offset to ldq_rel_retry_val_dly_offset), + din(0) => ldq_rel_retry_val_l2, + dout(0) => ldq_rel_retry_val_dly_l2); + +latch_rel_intf_v_dminus1 : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(rel_intf_v_dminus1_offset to rel_intf_v_dminus1_offset), + scout => sov(rel_intf_v_dminus1_offset to rel_intf_v_dminus1_offset), + din(0) => anaclat_data_val, + dout(0) => rel_intf_v_dminus1_l2); +latch_rel_intf_v : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(rel_intf_v_offset to rel_intf_v_offset), + scout => sov(rel_intf_v_offset to rel_intf_v_offset), + din(0) => rel_intf_v_dminus1_l2, + dout(0) => rel_intf_v_l2); +latch_rel_intf_v_dplus1 : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(rel_intf_v_dplus1_offset to rel_intf_v_dplus1_offset), + scout => sov(rel_intf_v_dplus1_offset to rel_intf_v_dplus1_offset), + din(0) => rel_intf_v_l2, + dout(0) => rel_intf_v_dplus1_l2); + +latch_anac_tag : tri_rlmreg_p + generic map (width => anaclat_tag'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(anac_tag_offset to anac_tag_offset + anaclat_tag'length-1), + scout => sov(anac_tag_offset to anac_tag_offset + anaclat_tag'length-1), + din => an_ac_reld_core_tag, + dout => anaclat_tag); + +ldq_retry_tag(1) <= '0'; + +ldq_retry_tag4: if lmq_entries=4 generate begin + ldq_retry_tag(2 to 4) <= "000" when ldq_retry_ready(0)='1' else + "001" when ldq_retry_ready(1)='1' else + "010" when ldq_retry_ready(2)='1' else + "011"; +end generate; + +ldq_retry_tag8: if lmq_entries=8 generate begin + ldq_retry_tag(2 to 4) <= "000" when ldq_retry_ready(0)='1' else + "001" when ldq_retry_ready(1)='1' else + "010" when ldq_retry_ready(2)='1' else + "011" when ldq_retry_ready(3)='1' else + "100" when ldq_retry_ready(4)='1' else + "101" when ldq_retry_ready(5)='1' else + "110" when ldq_retry_ready(6)='1' else + "111"; +end generate; + +ldq_retry_ready(0) <= ldq_retry_l2(0) and not retry_started_l2(0); +start_ldq_retry(0) <= ldq_retry_ready(0) and not data_val_for_rel; +retry_started_d(0) <= start_ldq_retry(0) or + (retry_started_l2(0) and not ld_m_rel_done_l2(0)); +start_ldq_retry(1) <= ldq_retry_ready(1) and not data_val_for_rel and not ldq_retry_ready(0); + +retry_started: for i in 1 to lmq_entries-1 generate begin + ldq_retry_ready(i) <= ldq_retry_l2(i) and not retry_started_l2(i); + igt1: if i > 1 generate begin + start_ldq_retry(i) <= ldq_retry_ready(i) and not data_val_for_rel and + not or_reduce(ldq_retry_ready(0 to i-1)); + end generate; + retry_started_d(i) <= start_ldq_retry(i) or + (retry_started_l2(i) and not ld_m_rel_done_l2(i)); +end generate; + +latch_retry_started : tri_rlmreg_p + generic map (width => retry_started_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(retry_started_offset to retry_started_offset + retry_started_l2'length-1), + scout => sov(retry_started_offset to retry_started_offset + retry_started_l2'length-1), + din => retry_started_d(0 to lmq_entries-1), + dout => retry_started_l2(0 to lmq_entries-1)); + +tag_dminus2 <= ldq_retry_tag when (ldq_retry_or and not data_val_for_rel)='1' else + anaclat_tag(1 to 4); + +tag_dminus1_act <= anaclat_data_val or ldq_retry_or or clkg_ctl_override_q; + +tag_dminus1_1hot_n8gen: if lmq_entries /= 8 generate begin + tag_dminus1_1hot_gen : for i in 0 to lmq_entries-1 generate begin + tag_dminus1_1hot_d(i) <= (tag_dminus2(1 to 4) = tconv(i, 4)); + end generate tag_dminus1_1hot_gen; +end generate tag_dminus1_1hot_n8gen; + +tag_dminus1_1hot_8gen: if lmq_entries=8 generate begin + tag_dminus1_1hot_d(0) <= not tag_dminus2(1) and not tag_dminus2(2) and not tag_dminus2(3) and not tag_dminus2(4); + tag_dminus1_1hot_d(1) <= not tag_dminus2(1) and not tag_dminus2(2) and not tag_dminus2(3) and tag_dminus2(4); + tag_dminus1_1hot_d(2) <= not tag_dminus2(1) and not tag_dminus2(2) and tag_dminus2(3) and not tag_dminus2(4); + tag_dminus1_1hot_d(3) <= not tag_dminus2(1) and not tag_dminus2(2) and tag_dminus2(3) and tag_dminus2(4); + tag_dminus1_1hot_d(4) <= not tag_dminus2(1) and tag_dminus2(2) and not tag_dminus2(3) and not tag_dminus2(4); + tag_dminus1_1hot_d(5) <= not tag_dminus2(1) and tag_dminus2(2) and not tag_dminus2(3) and tag_dminus2(4); + tag_dminus1_1hot_d(6) <= not tag_dminus2(1) and tag_dminus2(2) and tag_dminus2(3) and not tag_dminus2(4); + tag_dminus1_1hot_d(7) <= not tag_dminus2(1) and tag_dminus2(2) and tag_dminus2(3) and tag_dminus2(4); +end generate tag_dminus1_1hot_8gen; + + +latch_tag_dminus1 : tri_rlmreg_p + generic map (width => tag_dminus1_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => tag_dminus1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(tag_dminus1_offset to tag_dminus1_offset + tag_dminus1_l2'length-1), + scout => sov(tag_dminus1_offset to tag_dminus1_offset + tag_dminus1_l2'length-1), + din => tag_dminus2, + dout => tag_dminus1_l2); + +latch_tag_dminus1_cpy : tri_rlmreg_p + generic map (width => tag_dminus1_cpy_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => tag_dminus1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(tag_dminus1_cpy_offset to tag_dminus1_cpy_offset + tag_dminus1_cpy_l2'length-1), + scout => sov(tag_dminus1_cpy_offset to tag_dminus1_cpy_offset + tag_dminus1_cpy_l2'length-1), + din => tag_dminus2(2 to 4), + dout => tag_dminus1_cpy_l2); +latch_tag_dminus1_1hot : tri_rlmreg_p + generic map (width => tag_dminus1_1hot_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => tag_dminus1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(tag_dminus1_1hot_offset to tag_dminus1_1hot_offset + tag_dminus1_1hot_l2'length-1), + scout => sov(tag_dminus1_1hot_offset to tag_dminus1_1hot_offset + tag_dminus1_1hot_l2'length-1), + din => tag_dminus1_1hot_d, + dout => tag_dminus1_1hot_l2); + +latch_anac_qw : tri_rlmreg_p + generic map (width => anaclat_qw'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(anac_qw_offset to anac_qw_offset + anaclat_qw'length-1), + scout => sov(anac_qw_offset to anac_qw_offset + anaclat_qw'length-1), + din => an_ac_reld_qw, + dout => anaclat_qw); + +latch_qw_dminus1 : tri_rlmreg_p + generic map (width => qw_dminus1_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => tag_dminus1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(qw_dminus1_offset to qw_dminus1_offset + qw_dminus1_l2'length-1), + scout => sov(qw_dminus1_offset to qw_dminus1_offset + qw_dminus1_l2'length-1), + din => anaclat_qw, + dout => qw_dminus1_l2); + +dminus1_act <= data_val_dminus1_l2 or clkg_ctl_override_q; + +latch_qw : tri_rlmreg_p + generic map (width => qw_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dminus1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(qw_offset to qw_offset + qw_l2'length-1), + scout => sov(qw_offset to qw_offset + qw_l2'length-1), + din => qw_dminus1_l2, + dout => qw_l2); + +rel_data_act <= rel_intf_v_dminus1_l2 or clkg_ctl_override_q; + +latch_anac_data : tri_rlmreg_p + generic map (width => anaclat_data'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => rel_data_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(anac_data_offset to anac_data_offset + anaclat_data'length-1), + scout => sov(anac_data_offset to anac_data_offset + anaclat_data'length-1), + din => an_ac_reld_data, + dout => anaclat_data); + +latch_anac_ecc_err : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(anac_ecc_err_offset to anac_ecc_err_offset), + scout => sov(anac_ecc_err_offset to anac_ecc_err_offset), + din(0) => an_ac_reld_ecc_err, + dout(0) => anaclat_ecc_err); + +latch_anac_ecc_err_ue : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(anac_ecc_err_ue_offset to anac_ecc_err_ue_offset), + scout => sov(anac_ecc_err_ue_offset to anac_ecc_err_ue_offset), + din(0) => an_ac_reld_ecc_err_ue, + dout(0) => anaclat_ecc_err_ue); + + +beat_ecc_err <= anaclat_ecc_err and rel_intf_v_dplus1_l2; + +ue_mchk_v <= (rel_addr_l2(58) = qw_l2(58)) and reld_data_vld_l2 and not ldq_rel_retry_val_dly_l2 and not rel_tag_l2(1) and + ((rel_addr_l2(57) = qw_l2(57)) or not my_xucr0_cls); + +ue_mchk_valid_d(0 to 3) <= gate_and(ue_mchk_v, rel_th_id_l2(0 to 3)); + +l2_data_ecc_err_ue <= gate_and((anaclat_ecc_err_ue and rel_intf_v_dplus1_l2), ue_mchk_valid_l2(0 to 3)); + +latch_ue_mchk_val : tri_rlmreg_p + generic map (width => ue_mchk_valid_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ue_mchk_val_offset to ue_mchk_val_offset + ue_mchk_valid_l2'length-1), + scout => sov(ue_mchk_val_offset to ue_mchk_val_offset + ue_mchk_valid_l2'length-1), + din => ue_mchk_valid_d, + dout => ue_mchk_valid_l2); + +latch_anac_l1_dump : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(anac_l1_dump_offset to anac_l1_dump_offset), + scout => sov(anac_l1_dump_offset to anac_l1_dump_offset), + din(0) => an_ac_reld_l1_dump, + dout(0) => anaclat_l1_dump); +latch_dminus1_l1_dump : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => tag_dminus1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(dminus1_l1_dump_offset to dminus1_l1_dump_offset), + scout => sov(dminus1_l1_dump_offset to dminus1_l1_dump_offset), + din(0) => anaclat_l1_dump, + dout(0) => dminus1_l1_dump); + +dminus1_l1_dump_gated <= dminus1_l1_dump and rel_intf_v_dminus1_l2; + +latch_l1_dump : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dminus1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(l1_dump_offset to l1_dump_offset), + scout => sov(l1_dump_offset to l1_dump_offset), + din(0) => dminus1_l1_dump_gated, + dout(0) => l1_dump); + +latch_anac_back_inv : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(anac_back_inv_offset to anac_back_inv_offset), + scout => sov(anac_back_inv_offset to anac_back_inv_offset), + din(0) => an_ac_back_inv, + dout(0) => anaclat_back_inv); + +bi_act <= anaclat_back_inv or clkg_ctl_override_q; + +latch_anac_back_inv_addr : tri_rlmreg_p + generic map (width => anaclat_back_inv_addr'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => bi_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(anac_back_inv_addr_offset to anac_back_inv_addr_offset + anaclat_back_inv_addr'length-1), + scout => sov(anac_back_inv_addr_offset to anac_back_inv_addr_offset + anaclat_back_inv_addr'length-1), + din => an_ac_back_inv_addr, + dout => anaclat_back_inv_addr); + +latch_anac_back_inv_target1 : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(anac_back_inv_target1_offset to anac_back_inv_target1_offset), + scout => sov(anac_back_inv_target1_offset to anac_back_inv_target1_offset), + din(0) => an_ac_back_inv_target_bit1, + dout(0) => anaclat_back_inv_target_1); + +latch_anac_back_inv_target4 : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(anac_back_inv_target4_offset to anac_back_inv_target4_offset), + scout => sov(anac_back_inv_target4_offset to anac_back_inv_target4_offset), + din(0) => an_ac_back_inv_target_bit4, + dout(0) => anaclat_back_inv_target_4); + +back_inv_val_d <= anaclat_back_inv and anaclat_back_inv_target_1; +dbell_val_d <= anaclat_back_inv and anaclat_back_inv_target_4; + +latch_back_inv_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(back_inv_val_offset to back_inv_val_offset), + scout => sov(back_inv_val_offset to back_inv_val_offset), + din(0) => back_inv_val_d, + dout(0) => back_inv_val_l2); + +latch_dbell_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(dbell_val_offset to dbell_val_offset), + scout => sov(dbell_val_offset to dbell_val_offset), + din(0) => dbell_val_d, + dout(0) => dbell_val_l2); + +latch_anac_ld_pop : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(anac_ld_pop_offset to anac_ld_pop_offset), + scout => sov(anac_ld_pop_offset to anac_ld_pop_offset), + din(0) => an_ac_req_ld_pop, + dout(0) => anaclat_ld_pop); +latch_anac_st_pop : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(anac_st_pop_offset to anac_st_pop_offset), + scout => sov(anac_st_pop_offset to anac_st_pop_offset), + din(0) => an_ac_req_st_pop, + dout(0) => anaclat_st_pop); +latch_anac_st_pop_thrd : tri_rlmreg_p + generic map (width => anaclat_st_pop_thrd'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(anac_st_pop_thrd_offset to anac_st_pop_thrd_offset + anaclat_st_pop_thrd'length-1), + scout => sov(anac_st_pop_thrd_offset to anac_st_pop_thrd_offset + anaclat_st_pop_thrd'length-1), + din => an_ac_req_st_pop_thrd, + dout => anaclat_st_pop_thrd); +latch_anac_st_gather : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(anac_st_gather_offset to anac_st_gather_offset), + scout => sov(anac_st_gather_offset to anac_st_gather_offset), + din(0) => an_ac_req_st_gather, + dout(0) => anaclat_st_gather); + +latch_coreid : tri_rlmreg_p + generic map (width => anaclat_coreid'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(coreid_offset to coreid_offset + anaclat_coreid'length-1), + scout => sov(coreid_offset to coreid_offset + anaclat_coreid'length-1), + din => an_ac_coreid, + dout => anaclat_coreid); + +latch_stcx_complete : tri_rlmreg_p + generic map (width => xu_iu_stcx_complete'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(stcx_complete_offset to stcx_complete_offset + xu_iu_stcx_complete'length-1), + scout => sov(stcx_complete_offset to stcx_complete_offset + xu_iu_stcx_complete'length-1), + din => an_ac_stcx_complete, + dout => xu_iu_stcx_complete); + +latch_xu_iu_reld_core_tag : tri_rlmreg_p + generic map (width => xu_iu_reld_core_tag_clone'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(xu_iu_reld_core_tag_offset to xu_iu_reld_core_tag_offset + xu_iu_reld_core_tag_clone'length-1), + scout => sov(xu_iu_reld_core_tag_offset to xu_iu_reld_core_tag_offset + xu_iu_reld_core_tag_clone'length-1), + din => an_ac_reld_core_tag(1 to 4), + dout => xu_iu_reld_core_tag_clone); +latch_xu_iu_reld_data_vld : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(xu_iu_reld_data_vld_offset to xu_iu_reld_data_vld_offset), + scout => sov(xu_iu_reld_data_vld_offset to xu_iu_reld_data_vld_offset), + din(0) => an_ac_reld_data_val, + dout(0) => xu_iu_reld_data_vld_clone); +latch_xu_iu_reld_data_coming : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(xu_iu_reld_data_coming_offset to xu_iu_reld_data_coming_offset), + scout => sov(xu_iu_reld_data_coming_offset to xu_iu_reld_data_coming_offset), + din(0) => an_ac_reld_data_coming, + dout(0) => xu_iu_reld_data_coming_clone); +latch_xu_iu_reld_ditc : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(xu_iu_reld_ditc_offset to xu_iu_reld_ditc_offset), + scout => sov(xu_iu_reld_ditc_offset to xu_iu_reld_ditc_offset), + din(0) => an_ac_reld_ditc, + dout(0) => xu_iu_reld_ditc_clone); + + + + lsu_reld_data_vld <= anaclat_data_val; + lsu_reld_core_tag <= anaclat_tag(3 to 4); + lsu_reld_qw <= anaclat_qw(58 to 59); + lsu_reld_ditc <= anaclat_ditc; + lsu_reld_data <= anaclat_data; + lsu_req_st_pop <= anaclat_st_pop; + lsu_req_st_pop_thrd <= anaclat_st_pop_thrd; + lsu_reld_ecc_err <= anaclat_ecc_err or anaclat_ecc_err_ue; + + +latch_lpidr : tri_rlmreg_p + generic map (width => lpidr_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(lpidr_offset to lpidr_offset + lpidr_l2'length-1), + scout => sov(lpidr_offset to lpidr_offset + lpidr_l2'length-1), + din => mm_xu_lsu_lpidr(0 to 7), + dout => lpidr_l2(0 to 7)); + +lsu_xu_dbell_val <= dbell_val_l2; +lsu_xu_dbell_type(0 to 4) <= anaclat_back_inv_addr(32 to 36); +lsu_xu_dbell_brdcast <= anaclat_back_inv_addr(37); +lsu_xu_dbell_lpid_match <= (anaclat_back_inv_addr(42 to 49) = lpidr_l2(0 to 7)) or + (anaclat_back_inv_addr(42 to 49) = x"00"); +lsu_xu_dbell_pirtag(50 to 63) <= anaclat_back_inv_addr(50 to 63); + + +cmd_seq_incr(0 to 4) <= std_ulogic_vector(unsigned(cmd_seq_l2) + 1); +cmd_seq_decr(0 to 4) <= std_ulogic_vector(unsigned(cmd_seq_l2) - 1); + +ctrl_incr_cmdseq <= ld_m_val and not (ex4_flush_load and ex4_ld_m_val); +ctrl_decr_cmdseq <= (not ld_m_val and (ex4_flush_load and ex4_ld_m_val)); +ctrl_hold_cmdseq <= ( ld_m_val and (ex4_flush_load and ex4_ld_m_val)) or + (not ld_m_val and not (ex4_flush_load and ex4_ld_m_val)); + + +cmd_seq_d(0 to 4) <= gate_and(ctrl_incr_cmdseq , cmd_seq_incr(0 to 4)) or + gate_and(ctrl_decr_cmdseq , cmd_seq_decr(0 to 4)) or + gate_and(ctrl_hold_cmdseq , cmd_seq_l2(0 to 4)); + +latch_cmd_seq : tri_rlmreg_p + generic map (width => cmd_seq_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(cmd_seq_offset to cmd_seq_offset + cmd_seq_l2'length-1), + scout => sov(cmd_seq_offset to cmd_seq_offset + cmd_seq_l2'length-1), + din => cmd_seq_d(0 to 4), + dout => cmd_seq_l2(0 to 4)); + +new_ld_cmd_seq(0 to 4) <= cmd_seq_decr(0 to 4) when (ld_m_val and ex4_flush_load and ex4_ld_m_val) = '1' else + cmd_seq_l2(0 to 4); + + +ld_q_seq_wrap <= (cmd_seq_l2 = cmd_seq_rd_l2) and or_reduce(ld_entry_val_l2); + + +cmd_seq_rd_incr(0 to 4) <= std_ulogic_vector(unsigned(cmd_seq_rd_l2) + 1); + +cmd_seq_rd_d(0 to 4) <= cmd_seq_rd_incr(0 to 4) when (load_sent or selected_entry_flushed or rd_seq_num_skip)='1' else + cmd_seq_rd_l2(0 to 4); + +latch_cmd_seq_rd : tri_rlmreg_p + generic map (width => cmd_seq_rd_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(cmd_seq_rd_offset to cmd_seq_rd_offset + cmd_seq_rd_l2'length-1), + scout => sov(cmd_seq_rd_offset to cmd_seq_rd_offset + cmd_seq_rd_l2'length-1), + din => cmd_seq_rd_d(0 to 4), + dout => cmd_seq_rd_l2(0 to 4)); + + +ex3_new_target_gpr <= ex3_target_gpr or (0 to 8 => touch_instr); + +ld_queue_entry <= c_inh & cmd_type_ld(0 to 5) & ex3_opsize(0 to 5) & ex3_rot_sel(0 to 4) & + ex3_thrd_id(0 to 3) & new_ld_cmd_seq(0 to 4) & ex3_new_target_gpr(0 to 8) & + ex3_axu_op_val & ex3_le_mode & touch_instr & + ex3_wimge_bits(0 to 3) & ex3_usr_bits(0 to 3) & ex3_algebraic & l2only_instr & + ex3_lock_en & ex3_classid & ex3_watch_en & ex3_wimge_bits(4) when pe_recov_ld_val_l2='0' else + ex7_ld_recov_l2(0 to 21) & new_ld_cmd_seq(0 to 4) & + ex7_ld_recov_l2(27 to 53); + +ld_queue_addrlo <= ex3_p_addr(57 to 63) when pe_recov_ld_val_l2='0' else + ex7_ld_recov_l2((54+real_data_add-6-1) to (54+real_data_add-1)); + +cmp_ld_ex7_recov <= pe_recov_ld_val_l2; + +load_val <= ex3_load_instr and not (ex3_dcbt_instr or ex3_dcbtst_instr or + ex3_dcbtls_instr or ex3_dcbtstls_instr or + ex3_larx_instr or ex3_icbt_instr or ex3_icbtls_instr); + +load_l1hit_val <= ex3_load_l1hit and not ex3_larx_instr; + +latch_ex4_load_l1hit_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_load_l1hit_val_offset to ex4_load_l1hit_val_offset), + scout => sov(ex4_load_l1hit_val_offset to ex4_load_l1hit_val_offset), + din(0) => load_l1hit_val, + dout(0) => ex4_load_l1hit_val); + +dcbf_l_val <= ex3_dcbf_instr and (ex3_l_fld="01"); +dcbf_g_val <= ex3_dcbf_instr and ((ex3_l_fld="00") or (ex3_l_fld="10")); +hwsync_val <= (ex3_sync_instr and ((ex3_l_fld /= "01") or my_xucr0_mbar_ack) ) or + (ex3_mbar_instr and my_xucr0_mbar_ack); +lwsync_val <= ex3_sync_instr and (ex3_l_fld = "01") and not my_xucr0_mbar_ack; +mbar_val <= ex3_mbar_instr and not my_xucr0_mbar_ack; + +dcbt_l2only_val <= ex3_dcbt_instr and ex3_th_fld_l2; +dcbt_l1l2_val <= ex3_dcbt_instr and not ex3_th_fld_l2; +dcbtls_l2only_val <= ex3_dcbtls_instr and ex3_th_fld_l2; +dcbtls_l1l2_val <= ex3_dcbtls_instr and not ex3_th_fld_l2; +dcbtst_l2only_val <= ex3_dcbtst_instr and ex3_th_fld_l2; +dcbtst_l1l2_val <= ex3_dcbtst_instr and not ex3_th_fld_l2; +dcbtstls_l2only_val <= ex3_dcbtstls_instr and ex3_th_fld_l2; +dcbtstls_l1l2_val <= ex3_dcbtstls_instr and not ex3_th_fld_l2; + + +cmd_type_ld(0 to 5) <= gate_and( load_val , "001000") or + gate_and( ex3_larx_instr , ("0010" & ex3_mutex_hint & "1") ) or + gate_and( dcbt_l1l2_val , "001111") or + gate_and( dcbt_l2only_val , "000111") or + gate_and( dcbtls_l1l2_val , "011111") or + gate_and( dcbtls_l2only_val , "010111") or + gate_and( dcbtst_l1l2_val , "001101") or + gate_and( dcbtst_l2only_val , "000101") or + gate_and( dcbtstls_l1l2_val , "011101") or + gate_and( dcbtstls_l2only_val, "010101") or + gate_and( ex3_icbt_instr , "000100") or + gate_and( ex3_icbtls_instr , "010100"); + +cmd_type_st(0 to 5) <= gate_and( ex3_store_instr , "100000") or + gate_and( ex3_stx_instr , "101001") or + gate_and( ex3_icbi_instr , "111110") or + gate_and( dcbf_l_val , "110110") or + gate_and( dcbf_g_val , "110111") or + gate_and( ex3_dcbi_instr , "111111") or + gate_and( ex3_dcbz_instr , "100001") or + gate_and( ex3_dcbst_instr , "110101") or + gate_and( hwsync_val , "101011") or + gate_and( mbar_val , "110010") or + gate_and( lwsync_val , "101010") or + gate_and( ex3_tlbsync_instr , "111010") or + gate_and( ex3_icblc_instr , "100100") or + gate_and( ex3_dcblc_instr , "100101") or + gate_and( ex3_dci_instr , "101111") or + gate_and( ex3_ici_instr , "101110") or + gate_and( ex3_msgsnd_instr , "101101") or + gate_and( ex3_icswx_instr , "100110") or + gate_and( ex3_icswx_dot , "100111") or + gate_and( ex3_mtspr_trace , "101100") or + gate_and( load_l1hit_val , "110100"); + + +ex3_st_entry <= cmd_type_st(0 to 5) & + ex3_byte_en(0 to 31) & + ex3_thrd_id(0 to 3) & + ex3_wimge_bits(4) & + ex3_wimge_bits(0 to 3) & + ex3_usr_bits(0 to 3) & + ex3_opsize(0 to 5) & + ex3_icswx_epid & + ex3_p_addr; + +ex4_thrd_encode(0) <= ex4_thrd_id(2) or ex4_thrd_id(3); +ex4_thrd_encode(1) <= ex4_thrd_id(1) or ex4_thrd_id(3); + +ex4_st_addr <= ex4_st_entry_l2(58 to (58+real_data_add-1)) when ex4_st_entry_l2(0 to 5)/="101100" else + (0 to real_data_add-35 => '0') & + anaclat_coreid(6 to 7) & + ex4_thrd_encode(0 to 1) & + ex4_st_entry_l2(58+real_data_add-14 to 58+real_data_add-5) & + '0' & + ex4_st_entry_l2(58+real_data_add-4) & + ex4_st_entry_l2(58+real_data_add-1) & + ex4_st_entry_l2(58+real_data_add-2) & + ex4_st_entry_l2(58+real_data_add-3) & + "000000000000000"; + + +s_m_queue0_d <= s_m_queue0 when (st_entry0_val_l2 and (not (store_credit and ex5_sel_st_req) or + st_recycle_V_l2 or + (l2req_recycle_l2 and ex7_ld_par_err)))='1' else + ex4_st_entry_l2(0 to 57) & ex4_st_addr; + + +st_val <= (((ex3_l_s_q_val and not ex3_load_instr) or load_l1hit_val) and + not flush_if_store and not ex3_stg_flush and not I1_G1_flush); + + +thrd_hit_p: process (l_m_queue(0)(18 to 21), l_m_queue(1)(18 to 21), l_m_queue(2)(18 to 21), l_m_queue(3)(18 to 21), l_m_queue(4)(18 to 21), l_m_queue(5)(18 to 21), l_m_queue(6)(18 to 21), l_m_queue(7)(18 to 21), ld_rel_val_l2, ex3_thrd_id, ex3_sync_instr, ex3_mbar_instr, ex3_tlbsync_instr) + variable b0, b1, b2, b3: std_ulogic; +begin + b0 := '0'; + b1 := '0'; + b2 := '0'; + b3 := '0'; + for i in 0 to lmq_entries-1 loop + b0 := (l_m_queue(i)(18) and ld_rel_val_l2(i)) or b0; + b1 := (l_m_queue(i)(19) and ld_rel_val_l2(i)) or b1; + b2 := (l_m_queue(i)(20) and ld_rel_val_l2(i)) or b2; + b3 := (l_m_queue(i)(21) and ld_rel_val_l2(i)) or b3; + end loop; + sync_flush <= ((ex3_thrd_id(0) and b0) or + (ex3_thrd_id(1) and b1) or + (ex3_thrd_id(2) and b2) or + (ex3_thrd_id(3) and b3)) and + (ex3_sync_instr or ex3_mbar_instr or ex3_tlbsync_instr); +end process; + + + +nxt_st_cred_tkn <= (st_entry0_val_l2 and not (ex5_flush_store and ex5_st_val_l2)) or ob_req_val_l2 or ob_ditc_val_l2 or + (mmu_q_val and not mmu_q_entry_l2(0)); +flush_if_store <= (one_st_cred and nxt_st_cred_tkn and ex4_st_val_l2) or + (not store_credit and (st_entry0_val_l2 or ex4_st_val_l2)) or + (my_xucr0_cred and (st_entry0_val_l2 or ex4_st_val_l2)); + +st_flush <= (not ex3_load_instr and flush_if_store) or sync_flush; + + + + + + + + + + + + + + + + + + + + +st_entry0_val_d <= (ex4_st_val_l2 and not ex4_flush_store) or + (st_entry0_val_l2 and not (store_credit and ex5_sel_st_req) and not (my_ex5_flush_store and ex5_st_val_l2 and not ex8_ld_par_err_l2)) or + (((l2req_recycle_l2 and ex7_ld_par_err and not (my_ex5_flush_store and ex5_st_val_l2)) or st_recycle_V_l2) and + st_entry0_val_l2 and not (my_ex5_flush_store and ex5_st_val_l2 and not ex8_ld_par_err_l2)); +ex4_st_val_d <= st_val; + + + +latch_ex4_st_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_st_val_offset to ex4_st_val_offset), + scout => sov(ex4_st_val_offset to ex4_st_val_offset), + din(0) => ex4_st_val_d, + dout(0) => ex4_st_val_l2); + +ex4_st_valid <= ex4_st_val_l2 and not ex4_flush_store; + +latch_ex5_st_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex5_st_val_offset to ex5_st_val_offset), + scout => sov(ex5_st_val_offset to ex5_st_val_offset), + din(0) => ex4_st_valid, + dout(0) => ex5_st_val_l2); + +latch_ex6_st_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex6_st_val_offset to ex6_st_val_offset), + scout => sov(ex6_st_val_offset to ex6_st_val_offset), + din(0) => ex5_st_val_l2, + dout(0) => ex6_st_val_l2); + +latch_s_m_queue0_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(st_entry0_val_offset to st_entry0_val_offset), + scout => sov(st_entry0_val_offset to st_entry0_val_offset), + din(0) => st_entry0_val_d, + dout(0) => st_entry0_val_l2); + +latch_s_m_queue0_val_clone : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(st_entry0_val_clone_offset to st_entry0_val_clone_offset), + scout => sov(st_entry0_val_clone_offset to st_entry0_val_clone_offset), + din(0) => st_entry0_val_d, + dout(0) => st_entry0_val_clone_l2); + +ex4_st_entry_act <= ex3_stg_act or ex3_dci_instr or ex3_ici_instr or clkg_ctl_override_q; + +latch_ex4_st_entry : tri_rlmreg_p + generic map (width => ex4_st_entry_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ex4_st_entry_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_st_entry_offset to ex4_st_entry_offset + ex4_st_entry_l2'length-1), + scout => sov(ex4_st_entry_offset to ex4_st_entry_offset + ex4_st_entry_l2'length-1), + din => ex3_st_entry, + dout => ex4_st_entry_l2); + +latch_s_m_queue0 : tri_rlmreg_p + generic map (width => s_m_queue0'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => stq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(s_m_queue0_offset to s_m_queue0_offset + s_m_queue0'length-1), + scout => sov(s_m_queue0_offset to s_m_queue0_offset + s_m_queue0'length-1), + din => s_m_queue0_d, + dout => s_m_queue0); + + + + + + + +ld_m_val <= (ex3_l_s_q_val and ex3_load_instr and not ld_queue_full and not ld_q_seq_wrap) or + pe_recov_ld_val_l2; + +ld_flush <= ex3_load_instr and (ld_queue_full or ld_q_seq_wrap); +ex4_ld_queue_full <= ld_flush and ex3_l_s_q_val; +ex4_st_queue_full <= st_flush and ex3_l_s_q_val; +ex4_ldhld_sthld_coll <= l_m_fnd_stg and ex4_val_req; +ex3_i1_g1_coll <= I1_G1_flush and ex3_l_s_q_val; + +ld_miss_latency_d <= (ld_entry_val_l2(0) and ex6_loadmiss_qentry(0) and not ex6_flush_l2) or + (ld_miss_latency_l2 and ld_entry_val_l2(0)); + + +lsu_perf_events <= ex5_ld_queue_full_l2 & ex5_st_queue_full_l2 & ex5_ldhld_sthld_coll_l2 & ex5_i1_g1_coll_l2; +lsu_xu_perf_events <= lsu_perf_events_l2 & larx_done_tid_l2 & ld_miss_latency_l2; + + + + + +latch_ex4_ld_m_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_ld_m_val_offset to ex4_ld_m_val_offset), + scout => sov(ex4_ld_m_val_offset to ex4_ld_m_val_offset), + din(0) => ld_m_val, + dout(0) => ex4_ld_m_val); + +ex4_ld_m_val_not_fl <= ex4_ld_m_val and not ex4_flush_load; + + +latch_ex4_drop_ld_req : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_drop_ld_req_offset to ex4_drop_ld_req_offset), + scout => sov(ex4_drop_ld_req_offset to ex4_drop_ld_req_offset), + din(0) => ex3_drop_ld_req, + dout(0) => ex4_drop_ld_req); + +latch_ex4_drop_touch : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_drop_touch_offset to ex4_drop_touch_offset), + scout => sov(ex4_drop_touch_offset to ex4_drop_touch_offset), + din(0) => ex3_drop_touch, + dout(0) => ex4_drop_touch); + + + +latch_ex4_ld_queue_full : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_ld_queue_full_offset to ex4_ld_queue_full_offset), + scout => sov(ex4_ld_queue_full_offset to ex4_ld_queue_full_offset), + din(0) => ex4_ld_queue_full, + dout(0) => ex4_ld_queue_full_l2); + +ex5_ld_queue_full_d <= ex4_ld_queue_full_l2 and not ex4_drop_ld_req; + +latch_ex5_ld_queue_full : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex5_ld_queue_full_offset to ex5_ld_queue_full_offset), + scout => sov(ex5_ld_queue_full_offset to ex5_ld_queue_full_offset), + din(0) => ex5_ld_queue_full_d, + dout(0) => ex5_ld_queue_full_l2); + +latch_ex4_st_queue_full : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_st_queue_full_offset to ex4_st_queue_full_offset), + scout => sov(ex4_st_queue_full_offset to ex4_st_queue_full_offset), + din(0) => ex4_st_queue_full, + dout(0) => ex4_st_queue_full_l2); + +latch_ex5_st_queue_full : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex5_st_queue_full_offset to ex5_st_queue_full_offset), + scout => sov(ex5_st_queue_full_offset to ex5_st_queue_full_offset), + din(0) => ex4_st_queue_full_l2, + dout(0) => ex5_st_queue_full_l2); + +latch_ex5_ldhld_sthld_coll : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex5_ldhld_sthld_coll_offset to ex5_ldhld_sthld_coll_offset), + scout => sov(ex5_ldhld_sthld_coll_offset to ex5_ldhld_sthld_coll_offset), + din(0) => ex4_ldhld_sthld_coll, + dout(0) => ex5_ldhld_sthld_coll_l2); + +latch_ex4_i1_g1_coll : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_i1_g1_coll_offset to ex4_i1_g1_coll_offset), + scout => sov(ex4_i1_g1_coll_offset to ex4_i1_g1_coll_offset), + din(0) => ex3_i1_g1_coll, + dout(0) => ex4_i1_g1_coll_l2); + +latch_ex5_i1_g1_coll : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex5_i1_g1_coll_offset to ex5_i1_g1_coll_offset), + scout => sov(ex5_i1_g1_coll_offset to ex5_i1_g1_coll_offset), + din(0) => ex4_i1_g1_coll_l2, + dout(0) => ex5_i1_g1_coll_l2); + +latch_ld_miss_latency : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ld_miss_latency_offset to ld_miss_latency_offset), + scout => sov(ld_miss_latency_offset to ld_miss_latency_offset), + din(0) => ld_miss_latency_d, + dout(0) => ld_miss_latency_l2); + +latch_lsu_perf_events : tri_rlmreg_p + generic map (width => lsu_perf_events_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(lsu_perf_events_offset to lsu_perf_events_offset + lsu_perf_events_l2'length-1), + scout => sov(lsu_perf_events_offset to lsu_perf_events_offset + lsu_perf_events_l2'length-1), + din => lsu_perf_events, + dout => lsu_perf_events_l2); + +ldqfull: process (ld_rel_val_l2) + variable b: std_ulogic; +begin + b := '1'; + for i in 0 to lmq_entries-1 loop + b := ld_rel_val_l2(i) and b; + end loop; + ld_queue_full <= b; +end process; + +ex3_ld_queue_full <= ld_queue_full or ld_q_seq_wrap; + + +ex4_st_I1_G1_val <= ex4_st_entry_l2(44) and ex4_st_entry_l2(46) and ex4_st_val_l2; +st_entry_I1_G1_val <= s_m_queue0(44) and s_m_queue0(46) and st_entry0_val_l2; + +I1_G1_p: process (l_m_queue(0)(18 to 21), l_m_queue(1)(18 to 21), l_m_queue(2)(18 to 21), l_m_queue(3)(18 to 21), l_m_queue(4)(18 to 21), l_m_queue(5)(18 to 21), l_m_queue(6)(18 to 21), l_m_queue(7)(18 to 21), l_m_queue(0)(40), l_m_queue(1)(40), l_m_queue(2)(40), l_m_queue(3)(40), l_m_queue(4)(40), l_m_queue(5)(40), l_m_queue(6)(40), l_m_queue(7)(40), l_m_queue(0)(42), l_m_queue(1)(42), l_m_queue(2)(42), l_m_queue(3)(42), l_m_queue(4)(42), l_m_queue(5)(42), l_m_queue(6)(42), l_m_queue(7)(42), ld_rel_val_l2, st_entry_I1_G1_val, s_m_queue0(38 to 41), ex4_st_I1_G1_val, ex4_st_entry_l2(38 to 41)) + variable b0, b1, b2, b3: std_ulogic; +begin + b0 := '0'; + b1 := '0'; + b2 := '0'; + b3 := '0'; + for i in 0 to lmq_entries-1 loop + b0 := (l_m_queue(i)(40) and l_m_queue(i)(42) and l_m_queue(i)(18) and ld_rel_val_l2(i)) or b0; + b1 := (l_m_queue(i)(40) and l_m_queue(i)(42) and l_m_queue(i)(19) and ld_rel_val_l2(i)) or b1; + b2 := (l_m_queue(i)(40) and l_m_queue(i)(42) and l_m_queue(i)(20) and ld_rel_val_l2(i)) or b2; + b3 := (l_m_queue(i)(40) and l_m_queue(i)(42) and l_m_queue(i)(21) and ld_rel_val_l2(i)) or b3; + end loop; + I1_G1_thrd0 <= b0 or (ex4_st_I1_G1_val and ex4_st_entry_l2(38)) or (st_entry_I1_G1_val and s_m_queue0(38)); + I1_G1_thrd1 <= b1 or (ex4_st_I1_G1_val and ex4_st_entry_l2(39)) or (st_entry_I1_G1_val and s_m_queue0(39)); + I1_G1_thrd2 <= b2 or (ex4_st_I1_G1_val and ex4_st_entry_l2(40)) or (st_entry_I1_G1_val and s_m_queue0(40)); + I1_G1_thrd3 <= b3 or (ex4_st_I1_G1_val and ex4_st_entry_l2(41)) or (st_entry_I1_G1_val and s_m_queue0(41)); +end process; + +ex3_wimg_g_gated <= ex3_wimge_bits(3) and not (ex3_msgsnd_instr or ex3_dci_instr or ex3_ici_instr or ex3_mtspr_trace or + ex3_sync_instr or ex3_mbar_instr or ex3_tlbsync_instr); + +I1_G1_flush <= (ex3_wimge_bits(1) and ex3_wimg_g_gated and ex3_thrd_id(0) and I1_G1_thrd0) or + (ex3_wimge_bits(1) and ex3_wimg_g_gated and ex3_thrd_id(1) and I1_G1_thrd1) or + (ex3_wimge_bits(1) and ex3_wimg_g_gated and ex3_thrd_id(2) and I1_G1_thrd2) or + (ex3_wimge_bits(1) and ex3_wimg_g_gated and ex3_thrd_id(3) and I1_G1_thrd3); + + + + + +addr_comp: for i in 0 to lmq_entries-1 generate begin + comp_val(i) <= ld_rel_val_l2(i) and ex3_cache_acc and not(ex4_drop_ld_req and ex4_loadmiss_qentry(i)) and not(my_ex4_flush_l2 and ex4_loadmiss_qentry(i)); + cmp_ldq_comp_val(i) <= comp_val(i); + l_m_q_cpy(i) <= cmp_ldq_match(i); + l_m_q_cpy_nofl(i) <= l_m_q_cpy(i) and comp_val(i) and not ex3_stg_flush; +end generate; + + + + + +l_m_fnd_nofl <= cmp_ldq_fnd and not ex3_stg_flush; + +entry_found_latch : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(l_m_fnd_offset to l_m_fnd_offset), + scout => sov(l_m_fnd_offset to l_m_fnd_offset), + din(0) => l_m_fnd_nofl, + dout(0) => l_m_fnd_stg); + + +latch_ex4_lmq_cpy : tri_rlmreg_p + generic map (width => ex4_lmq_cpy_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_lmq_cpy_offset to ex4_lmq_cpy_offset + ex4_lmq_cpy_l2'length-1), + scout => sov(ex4_lmq_cpy_offset to ex4_lmq_cpy_offset + ex4_lmq_cpy_l2'length-1), + din => l_m_q_cpy_nofl(0 to lmq_entries-1), + dout => ex4_lmq_cpy_l2(0 to lmq_entries-1)); +latch_ex5_lmq_cpy : tri_rlmreg_p + generic map (width => ex5_lmq_cpy_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex5_lmq_cpy_offset to ex5_lmq_cpy_offset + ex5_lmq_cpy_l2'length-1), + scout => sov(ex5_lmq_cpy_offset to ex5_lmq_cpy_offset + ex5_lmq_cpy_l2'length-1), + din => ex4_lmq_cpy_l2(0 to lmq_entries-1), + dout => ex5_lmq_cpy_l2(0 to lmq_entries-1)); + + + +targetgpr_comp: for i in 0 to lmq_entries-1 generate begin + src0_hit(i) <= (ex1_src0_reg(0 to 7) = l_m_queue(i)(28 to 35)) and ld_rel_val_l2(i) and not (ex4_drop_ld_req and ex4_loadmiss_qentry(i)) and + not l_m_queue(i)(36) and not l_m_queue(i)(38) and not gpr_updated_dly2_l2(i); + src1_hit(i) <= (ex1_src1_reg(0 to 7) = l_m_queue(i)(28 to 35)) and ld_rel_val_l2(i) and not (ex4_drop_ld_req and ex4_loadmiss_qentry(i)) and + not l_m_queue(i)(36) and not l_m_queue(i)(38) and not gpr_updated_dly2_l2(i); + targ_hit(i) <= (ex1_targ_reg(0 to 7) = l_m_queue(i)(28 to 35)) and ld_rel_val_l2(i) and not (ex4_drop_ld_req and ex4_loadmiss_qentry(i)) and + not l_m_queue(i)(36) and not l_m_queue(i)(38) and not gpr_updated_dly2_l2(i); + + watch_bit_v_t0(i) <= ld_rel_val_l2(i) and l_m_queue(i)(52) and l_m_queue(i)(18); + watch_bit_v_t1(i) <= ld_rel_val_l2(i) and l_m_queue(i)(52) and l_m_queue(i)(19); + watch_bit_v_t2(i) <= ld_rel_val_l2(i) and l_m_queue(i)(52) and l_m_queue(i)(20); + watch_bit_v_t3(i) <= ld_rel_val_l2(i) and l_m_queue(i)(52) and l_m_queue(i)(21); +end generate; + +watch_hit_t0 <= or_reduce(watch_bit_v_t0) and ex1_check_watch(0); +watch_hit_t1 <= or_reduce(watch_bit_v_t1) and ex1_check_watch(1); +watch_hit_t2 <= or_reduce(watch_bit_v_t2) and ex1_check_watch(2); +watch_hit_t3 <= or_reduce(watch_bit_v_t3) and ex1_check_watch(3); + +watch_hit <= watch_hit_t0 or watch_hit_t1 or watch_hit_t2 or watch_hit_t3; + +lm_dep_hit_or: process (src0_hit, src1_hit, targ_hit, ex1_src0_vld, ex1_src1_vld, ex1_targ_vld, watch_hit) + variable src0_hit_or: std_ulogic; + variable src1_hit_or: std_ulogic; + variable targ_hit_or: std_ulogic; +begin + src0_hit_or := '0'; + src1_hit_or := '0'; + targ_hit_or := '0'; + for i in 0 to lmq_entries-1 loop + src0_hit_or := src0_hit(i) or src0_hit_or; + src1_hit_or := src1_hit(i) or src1_hit_or; + targ_hit_or := targ_hit(i) or targ_hit_or; + end loop; + ex1_lm_dep_hit <= (src0_hit_or and ex1_src0_vld) or + (src1_hit_or and ex1_src1_vld) or + (targ_hit_or and ex1_targ_vld) or watch_hit; +end process; + +lm_dep_hit_latch : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(lm_dep_hit_offset to lm_dep_hit_offset), + scout => sov(lm_dep_hit_offset to lm_dep_hit_offset), + din(0) => ex1_lm_dep_hit, + dout(0) => ex2_lm_dep_hit_buf); + +ex2_lm_dep_hit <= ex2_lm_dep_hit_buf; + + +cmp_back_inv_addr <= anaclat_back_inv_addr(64-real_data_add to 57); + +back_inv_addr_comp: for i in 0 to lmq_entries-1 generate begin +cmp_back_inv_cmp_val(i) <= back_inv_val_l2 and + ld_rel_val_l2(i) and not ld_entry_val_l2(i) and not ex4_loadmiss_qentry(i); + +lmq_back_invalidated_d(i) <= (cmp_back_inv_addr_hit(i) and not reset_lmq_entry(i) ) or + (lmq_back_invalidated_l2(i) and not reset_lmq_entry(i) ); + +end generate; + +latch_lmq_back_invalidated : tri_rlmreg_p + generic map (width => lmq_back_invalidated_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(lmq_back_invalidated_offset to lmq_back_invalidated_offset + lmq_back_invalidated_l2'length-1), + scout => sov(lmq_back_invalidated_offset to lmq_back_invalidated_offset + lmq_back_invalidated_l2'length-1), + din => lmq_back_invalidated_d(0 to lmq_entries-1), + dout => lmq_back_invalidated_l2(0 to lmq_entries-1)); + + + + + + +l_q_wrt_en(0) <= ld_m_val and ((not ld_rel_val_l2(0) and not pe_recov_ld_val_l2) or + (ex7_loadmiss_qentry(0) and pe_recov_ld_val_l2)); + +wrten: for i in 1 to lmq_entries-1 generate begin + wrten_p: process (ld_rel_val_l2(0 to i), ld_m_val, ex7_loadmiss_qentry(i), pe_recov_ld_val_l2) + variable b: std_ulogic; + begin + b := '1'; + for j in 0 to i-1 loop + b := ld_rel_val_l2(j) and b; + end loop; + l_q_wrt_en(i) <= ld_m_val and ((not ld_rel_val_l2(i) and b and not pe_recov_ld_val_l2) or + (ex7_loadmiss_qentry(i) and pe_recov_ld_val_l2)); + end process; +end generate; +cmp_l_q_wrt_en <= l_q_wrt_en; + + + +rel_done_ecc_err_p: process (ld_m_rel_done_l2, data_ecc_err_l2) + variable b: std_ulogic; +begin + b := '0'; + for i in 0 to lmq_entries-1 loop + b := (ld_m_rel_done_l2(i) and data_ecc_err_l2(i)) or b; + end loop; + rel_done_ecc_err <= b; +end process; + + +cmp_s_m_queue0_addr <= s_m_queue0(58 to (58+real_data_add-6-1)); +cmp_st_entry0_val <= st_entry0_val_l2; +cmp_ex4_st_entry_addr <= ex4_st_entry_l2(58 to (58+real_data_add-6-1)); +cmp_ex4_st_val <= ex4_st_val_l2; + +lmq_entry_act <= ex3_stg_act or pe_recov_ld_val_l2 or clkg_ctl_override_q; +cmp_lmq_entry_act <= lmq_entry_act; + +ldqueue: for i in 0 to lmq_entries-1 generate begin + + + + ld_entry_val_d(i) <= (ex4_loadmiss_qentry(i) and not ex4_flush_load) or + (ld_entry_val_l2(i) and not (load_sent and l_q_rd_en(i)) and + not(ex5_loadmiss_qentry(i) and (ex7_ld_par_err or ex5_flush_load_local)) and + not(ex6_loadmiss_qentry(i) and (ex7_ld_par_err or ex6_flush_l2))); + + + + + reset_lmq_entry(i) <= reset_lmq_entry_rel(i) or + (ex4_loadmiss_qentry(i) and ex4_flush_load) or + (ex5_loadmiss_qentry(i) and ex5_flush_load_local) or + (ex5_loadmiss_qentry(i) and pe_recov_stall and ex6_flush_l2) or + (ex5_loadmiss_qentry(i) and ex7_ld_par_err) or + (ex6_loadmiss_qentry(i) and ex7_ld_par_err) or + (ex6_loadmiss_qentry(i) and not ex4_loadmiss_qentry(i) and ex6_flush_l2); + + reset_ldq_hit_barr(i) <= ld_m_rel_done_no_retry(i) or ld_m_rel_done_dly_l2(i) or reset_lmq_entry(i); + + + ld_rel_val_d(i) <= l_q_wrt_en(i) or + (ld_rel_val_l2(i) and not reset_lmq_entry(i)); + + + with l_q_wrt_en(i) select + l_m_queue_d(i) <= ld_queue_entry when '1', + l_m_queue(i) when others; + + with l_q_wrt_en(i) select + l_m_queue_addrlo_d(i) <= ld_queue_addrlo(57 to 63) when '1', + l_m_queue_addrlo(i) when others; + + + latch_l_m_queue : tri_rlmreg_p + generic map (width => l_m_queue(i)'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => lmq_entry_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(l_m_queue_offset+(i*l_m_queue(i)'length) to l_m_queue_offset+(i*l_m_queue(i)'length) + l_m_queue(i)'length-1), + scout => sov(l_m_queue_offset+(i*l_m_queue(i)'length) to l_m_queue_offset+(i*l_m_queue(i)'length) + l_m_queue(i)'length-1), + din => l_m_queue_d(i), + dout => l_m_queue(i)); + + latch_l_m_queue_addrlo : tri_rlmreg_p + generic map (width => l_m_queue_addrlo(i)'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => lmq_entry_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(l_m_queue_addrlo_offset+(i*l_m_queue_addrlo(i)'length) to l_m_queue_addrlo_offset+(i*l_m_queue_addrlo(i)'length) + l_m_queue_addrlo(i)'length-1), + scout => sov(l_m_queue_addrlo_offset+(i*l_m_queue_addrlo(i)'length) to l_m_queue_addrlo_offset+(i*l_m_queue_addrlo(i)'length) + l_m_queue_addrlo(i)'length-1), + din => l_m_queue_addrlo_d(i), + dout => l_m_queue_addrlo(i)); + + + l_m_q_hit_st_d(i) <= (cmp_ex3addr_hit_stq and l_q_wrt_en(i) and not store_sent and not pe_recov_ld_val_l2) or + (cmp_ex3addr_hit_ex4st and l_q_wrt_en(i) and not pe_recov_ld_val_l2) or + (ex7_ld_recov_extra_l2(0) and not store_sent and l_q_wrt_en(i) and pe_recov_ld_val_l2) or + (l_m_q_hit_st_l2(i) and (not store_sent and st_entry0_val_l2) and not reset_lmq_entry(i)); + + lmq_drop_rel_d(i) <= (ex4_drop_rel and (ex4_loadmiss_qentry(i) and not pe_recov_state_l2)) or + (ex8_ld_recov_extra_l2(1) and (ex4_loadmiss_qentry(i) and pe_recov_state_l2)) or + (lmq_drop_rel_l2(i) and not ex4_loadmiss_qentry(i)); + + lmq_dvc1_en_d(i) <= (xu_lsu_ex4_dvc1_en and (ex4_loadmiss_qentry(i) and not pe_recov_state_l2)) or + (ex8_ld_recov_extra_l2(2) and (ex4_loadmiss_qentry(i) and pe_recov_state_l2)) or + (lmq_dvc1_en_l2(i) and not ex4_loadmiss_qentry(i)); + + lmq_dvc2_en_d(i) <= (xu_lsu_ex4_dvc2_en and (ex4_loadmiss_qentry(i) and not pe_recov_state_l2)) or + (ex8_ld_recov_extra_l2(3) and (ex4_loadmiss_qentry(i) and pe_recov_state_l2)) or + (lmq_dvc2_en_l2(i) and not ex4_loadmiss_qentry(i)); + +end generate; + +latch_l_m_entry_val : tri_rlmreg_p + generic map (width => ld_entry_val_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ld_entry_val_offset to ld_entry_val_offset + ld_entry_val_l2'length-1), + scout => sov(ld_entry_val_offset to ld_entry_val_offset + ld_entry_val_l2'length-1), + din => ld_entry_val_d, + dout => ld_entry_val_l2); +latch_l_m_rel_val : tri_rlmreg_p + generic map (width => ld_rel_val_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ld_rel_val_offset to ld_rel_val_offset + ld_rel_val_l2'length-1), + scout => sov(ld_rel_val_offset to ld_rel_val_offset + ld_rel_val_l2'length-1), + din => ld_rel_val_d, + dout => ld_rel_val_l2); +latch_l_m_q_hit_st : tri_rlmreg_p + generic map (width => l_m_q_hit_st_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(l_m_q_hit_st_offset to l_m_q_hit_st_offset + l_m_q_hit_st_l2'length-1), + scout => sov(l_m_q_hit_st_offset to l_m_q_hit_st_offset + l_m_q_hit_st_l2'length-1), + din => l_m_q_hit_st_d, + dout => l_m_q_hit_st_l2); + +latch_lmq_drop_rel : tri_rlmreg_p + generic map (width => lmq_drop_rel_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(lmq_drop_rel_offset to lmq_drop_rel_offset + lmq_drop_rel_l2'length-1), + scout => sov(lmq_drop_rel_offset to lmq_drop_rel_offset + lmq_drop_rel_l2'length-1), + din => lmq_drop_rel_d, + dout => lmq_drop_rel_l2); + +latch_lmq_dvc1_en : tri_rlmreg_p + generic map (width => lmq_dvc1_en_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(lmq_dvc1_en_offset to lmq_dvc1_en_offset + lmq_dvc1_en_l2'length-1), + scout => sov(lmq_dvc1_en_offset to lmq_dvc1_en_offset + lmq_dvc1_en_l2'length-1), + din => lmq_dvc1_en_d, + dout => lmq_dvc1_en_l2); + +latch_lmq_dvc2_en : tri_rlmreg_p + generic map (width => lmq_dvc2_en_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(lmq_dvc2_en_offset to lmq_dvc2_en_offset + lmq_dvc2_en_l2'length-1), + scout => sov(lmq_dvc2_en_offset to lmq_dvc2_en_offset + lmq_dvc2_en_l2'length-1), + din => lmq_dvc2_en_d, + dout => lmq_dvc2_en_l2); + + +ex4_ld_entry_d <= cmd_type_ld(0 to 5) & + ex3_wimge_bits(0 to 4) & + ex3_usr_bits(0 to 3); + +latch_ex4_ld_recov : tri_rlmreg_p + generic map (width => ex4_ld_entry_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => lmq_entry_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_ld_recov_offset to ex4_ld_recov_offset + ex4_ld_entry_l2'length-1), + scout => sov(ex4_ld_recov_offset to ex4_ld_recov_offset + ex4_ld_entry_l2'length-1), + din => ex4_ld_entry_d, + dout => ex4_ld_entry_l2); + +latch_ex4_classid : tri_rlmreg_p + generic map (width => ex4_classid_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => lmq_entry_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_classid_offset to ex4_classid_offset + ex4_classid_l2'length-1), + scout => sov(ex4_classid_offset to ex4_classid_offset + ex4_classid_l2'length-1), + din => ex3_classid(0 to 1), + dout => ex4_classid_l2); + +ex4_ld_recov_val_d <= ex3_l_s_q_val and ex3_load_instr; + +latch_ex4_ld_recov_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_ld_recov_val_offset to ex4_ld_recov_val_offset), + scout => sov(ex4_ld_recov_val_offset to ex4_ld_recov_val_offset), + din(0) => ex4_ld_recov_val_d, + dout(0) => ex4_ld_recov_val_l2); + +ex4_ld_entry_hit_st_d <= (cmp_ex3addr_hit_stq and not store_sent and not pe_recov_ld_val_l2) or + (cmp_ex3addr_hit_ex4st and not pe_recov_ld_val_l2); + +latch_ex4_ld_entry_hit_st : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_ld_entry_hit_st_offset to ex4_ld_entry_hit_st_offset), + scout => sov(ex4_ld_entry_hit_st_offset to ex4_ld_entry_hit_st_offset), + din(0) => ex4_ld_entry_hit_st_d, + dout(0) => ex4_ld_entry_hit_st_l2); + +ex4_ld_recov_mux: process(ex4_loadmiss_qentry, l_m_queue, l_m_queue_addrlo(0)(58 to 63), l_m_queue_addrlo(1)(58 to 63), l_m_queue_addrlo(2)(58 to 63), l_m_queue_addrlo(3)(58 to 63), l_m_queue_addrlo(4)(58 to 63), l_m_queue_addrlo(5)(58 to 63), l_m_queue_addrlo(6)(58 to 63), l_m_queue_addrlo(7)(58 to 63), l_m_q_hit_st_l2) + variable b: std_ulogic_vector(0 to 53); + variable c: std_ulogic; + variable d: std_ulogic_vector(58 to 63); +begin + b := (others => '0') ; + d := (others => '0') ; + c := '0'; + for i in 0 to lmq_entries-1 loop + b := gate_and(ex4_loadmiss_qentry(i), l_m_queue(i)) or b; + d := gate_and(ex4_loadmiss_qentry(i), l_m_queue_addrlo(i)(58 to 63)) or d; + c := (ex4_loadmiss_qentry(i) and l_m_q_hit_st_l2(i)) or c; + end loop; + ex4_ld_recov_entry <= b; + ex4_ld_recov_addrlo <= d; + ex4_ld_recov_ld_hit_st <= c; +end process; + +ex4_touch <= ( ex4_ld_entry_l2(0 to 5) = "001111") or + ( ex4_ld_entry_l2(0 to 5) = "000111") or + ( ex4_ld_entry_l2(0 to 5) = "011111") or + ( ex4_ld_entry_l2(0 to 5) = "010111") or + ( ex4_ld_entry_l2(0 to 5) = "001101") or + ( ex4_ld_entry_l2(0 to 5) = "000101") or + ( ex4_ld_entry_l2(0 to 5) = "011101") or + ( ex4_ld_entry_l2(0 to 5) = "010101") or + ( ex4_ld_entry_l2(0 to 5) = "000100") or + ( ex4_ld_entry_l2(0 to 5) = "010100"); + +ex4_l2only <=( ex4_ld_entry_l2(0 to 5) = "000111") or + ( ex4_ld_entry_l2(0 to 5) = "010111") or + ( ex4_ld_entry_l2(0 to 5) = "000101") or + ( ex4_ld_entry_l2(0 to 5) = "010101") or + ( ex4_ld_entry_l2(0 to 5) = "000100") or + ( ex4_ld_entry_l2(0 to 5) = "010100"); + +ex4_ld_recov <= ex4_ld_recov_entry(0 to 53) & cmp_ex4_ld_addr & ex4_ld_recov_addrlo(58 to 63) when ex4_ld_m_val='1' else + ex4_ld_entry(0) & + ex4_ld_entry_l2(0 to 5) & + ex4_ld_entry(1 to 6) & + ex4_ld_entry(7 to 11) & + ex4_thrd_id(0 to 3) & + cmd_seq_l2(0 to 4) & + ex4_ld_entry(12 to 20) & + ex4_ld_entry(21) & + ex4_ld_entry(22) & + ex4_touch & + ex4_ld_entry_l2(6 to 9) & + ex4_ld_entry_l2(11 to 14) & + ex4_ld_entry(23) & + ex4_l2only & + ex4_ld_entry(24) & + ex4_classid_l2(0 to 1) & + ex4_ld_entry(25) & + ex4_ld_entry_l2(10) & + ex4_ld_entry(26 to (26+(real_data_add-1))); + + +ex5_ld_recov_d <= ex4_ld_recov when pe_recov_stall='0' else + ex5_ld_recov_l2; + +latch_ex5_ld_recov : tri_rlmreg_p + generic map (width => ex5_ld_recov_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ex4_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex5_ld_recov_offset to ex5_ld_recov_offset + ex5_ld_recov_l2'length-1), + scout => sov(ex5_ld_recov_offset to ex5_ld_recov_offset + ex5_ld_recov_l2'length-1), + din => ex5_ld_recov_d, + dout => ex5_ld_recov_l2); + + +ex6_ld_recov_d <= ex5_ld_recov_l2 when pe_recov_stall='0' else + ex6_ld_recov_l2(0 to 37) & '1' & ex6_ld_recov_l2(39 to (54+(real_data_add-1))) when (pe_recov_state_l2 and not pe_recov_state_dly_l2 and ex7_targ_match)='1' else + ex6_ld_recov_l2; + +ex6_ld_recov_act <= ex5_ld_recov_val_l2 or clkg_ctl_override_q or ex6_ld_recov_val_l2; + +latch_ex6_ld_recov : tri_rlmreg_p + generic map (width => ex6_ld_recov_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ex6_ld_recov_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex6_ld_recov_offset to ex6_ld_recov_offset + ex6_ld_recov_l2'length-1), + scout => sov(ex6_ld_recov_offset to ex6_ld_recov_offset + ex6_ld_recov_l2'length-1), + din => ex6_ld_recov_d, + dout => ex6_ld_recov_l2); + + +ex7_ld_recov_d <= ex6_ld_recov_l2 when pe_recov_stall='0' else + ex7_ld_recov_l2(0 to 37) & '1' & ex7_ld_recov_l2(39 to (54+(real_data_add-1))) when (pe_recov_state_l2 and not pe_recov_state_dly_l2 and ex8_targ_match)='1' else + ex7_ld_recov_l2; + +ex7_ld_recov_act <= ex6_ld_recov_val_l2 or clkg_ctl_override_q or ex7_ld_recov_val_l2; + +latch_ex7_ld_recov : tri_rlmreg_p + generic map (width => ex7_ld_recov_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ex7_ld_recov_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex7_ld_recov_offset to ex7_ld_recov_offset + ex7_ld_recov_l2'length-1), + scout => sov(ex7_ld_recov_offset to ex7_ld_recov_offset + ex7_ld_recov_l2'length-1), + din => ex7_ld_recov_d, + dout => ex7_ld_recov_l2); + +cmp_ex7_ld_recov_addr <= ex7_ld_recov_l2((54) to (54+real_data_add-6-1)); + +ex4_ld_recov_extra(0) <= ex4_ld_recov_ld_hit_st when ex4_ld_m_val='1' else + ex4_ld_entry_hit_st_l2; + +ex4_ld_recov_extra(1) <= '0'; +ex4_ld_recov_extra(2) <= xu_lsu_ex4_dvc1_en; +ex4_ld_recov_extra(3) <= xu_lsu_ex4_dvc2_en; + +ex5_ld_recov_extra_d(0) <= ex4_ld_recov_extra(0) and (not store_sent and st_entry0_val_l2) when pe_recov_stall='0' else + (ex5_ld_recov_extra_l2(0) and (not store_sent and st_entry0_val_l2)) or + (ex7_ld_par_err and not pe_recov_state_l2); + +ex5_ld_recov_extra_d(1 to 3) <= ex4_ld_recov_extra(1 to 3) when pe_recov_stall='0' else + ex5_ld_recov_extra_l2(1 to 3); + +latch_ex5_ld_recov_extra : tri_rlmreg_p + generic map (width => ex5_ld_recov_extra_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ex4_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex5_ld_recov_extra_offset to ex5_ld_recov_extra_offset + ex5_ld_recov_extra_l2'length-1), + scout => sov(ex5_ld_recov_extra_offset to ex5_ld_recov_extra_offset + ex5_ld_recov_extra_l2'length-1), + din => ex5_ld_recov_extra_d, + dout => ex5_ld_recov_extra_l2); + +ex6_ld_recov_extra_d(0) <= ex5_ld_recov_extra_l2(0) and (not store_sent and st_entry0_val_l2) when pe_recov_stall='0' else + ex6_ld_recov_extra_l2(0) and (not store_sent and st_entry0_val_l2); + +ex6_ld_recov_extra_d(1 to 3) <= ex5_ld_recov_extra_l2(1 to 3) when pe_recov_stall='0' else + ex6_ld_recov_extra_l2(1 to 3); + +latch_ex6_ld_recov_extra : tri_rlmreg_p + generic map (width => ex6_ld_recov_extra_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ex6_ld_recov_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex6_ld_recov_extra_offset to ex6_ld_recov_extra_offset + ex6_ld_recov_extra_l2'length-1), + scout => sov(ex6_ld_recov_extra_offset to ex6_ld_recov_extra_offset + ex6_ld_recov_extra_l2'length-1), + din => ex6_ld_recov_extra_d, + dout => ex6_ld_recov_extra_l2); + +ex7_ld_recov_extra_d(0) <= ex6_ld_recov_extra_l2(0) and (not store_sent and st_entry0_val_l2) when pe_recov_stall='0' else + ex7_ld_recov_extra_l2(0) and (not store_sent and st_entry0_val_l2); + +ex7_ld_recov_extra_d(1 to 3) <= ex6_ld_recov_extra_l2(1 to 3) when pe_recov_stall='0' else + ex7_ld_recov_extra_l2(1 to 3); + +latch_ex7_ld_recov_extra : tri_rlmreg_p + generic map (width => ex7_ld_recov_extra_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ex7_ld_recov_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex7_ld_recov_extra_offset to ex7_ld_recov_extra_offset + ex7_ld_recov_extra_l2'length-1), + scout => sov(ex7_ld_recov_extra_offset to ex7_ld_recov_extra_offset + ex7_ld_recov_extra_l2'length-1), + din => ex7_ld_recov_extra_d, + dout => ex7_ld_recov_extra_l2); + +ex8_ld_recov_act <= ex7_ld_recov_val_l2 or clkg_ctl_override_q; + +latch_ex8_ld_recov_extra : tri_rlmreg_p + generic map (width => ex8_ld_recov_extra_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ex8_ld_recov_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex8_ld_recov_extra_offset to ex8_ld_recov_extra_offset + ex8_ld_recov_extra_l2'length-1), + scout => sov(ex8_ld_recov_extra_offset to ex8_ld_recov_extra_offset + ex8_ld_recov_extra_l2'length-1), + din => ex7_ld_recov_extra_l2(1 to 3), + dout => ex8_ld_recov_extra_l2); + + + + +ex5_ld_recov_val_d <= ((ex4_ld_m_val or ex4_ld_recov_val_l2) and not ex4_flush_load_wo_drop and not pe_recov_stall) or + (ex5_ld_recov_val_l2 and pe_recov_stall and pe_recov_state_l2 and not ex6_flush_l2) or + (ex5_ld_recov_val_l2 and pe_recov_stall and ex7_ld_par_err and not pe_recov_state_l2 and not ex5_flush_load_local); + +latch_ex5_ld_recov_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex5_ld_recov_val_offset to ex5_ld_recov_val_offset), + scout => sov(ex5_ld_recov_val_offset to ex5_ld_recov_val_offset), + din(0) => ex5_ld_recov_val_d, + dout(0) => ex5_ld_recov_val_l2); + +ex5_ld_recov_val_not_fl <= (ex5_ld_recov_val_l2 and not ex5_flush_load_local and not ex7_ld_par_err and not pe_recov_state_l2) or + (ex5_ld_recov_val_l2 and not pe_recov_stall and pe_recov_state_l2) or + (ex6_ld_recov_val_l2 and pe_recov_stall and not (ex6_flush_l2 and not pe_recov_state_l2)); + +latch_ex6_ld_recov_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex6_ld_recov_val_offset to ex6_ld_recov_val_offset), + scout => sov(ex6_ld_recov_val_offset to ex6_ld_recov_val_offset), + din(0) => ex5_ld_recov_val_not_fl, + dout(0) => ex6_ld_recov_val_l2); + +ex6_ld_recov_val_not_fl <= (ex6_ld_recov_val_l2 and not ex6_flush_l2 and not ex7_ld_par_err and not pe_recov_state_l2) or + (ex6_ld_recov_val_l2 and not pe_recov_stall and pe_recov_state_l2) or + (ex7_ld_recov_val_l2 and pe_recov_stall); + + +latch_ex7_ld_recov_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex7_ld_recov_val_offset to ex7_ld_recov_val_offset), + scout => sov(ex7_ld_recov_val_offset to ex7_ld_recov_val_offset), + din(0) => ex6_ld_recov_val_not_fl, + dout(0) => ex7_ld_recov_val_l2); + + + +stq_hit_ex6_recov <= (ex6_ld_recov_l2((54) to (54+real_data_add-7-1)) = s_m_queue0(58 to (58+real_data_add-7-1))) and + ((ex6_ld_recov_l2(54+real_data_add-6-1) = s_m_queue0(58+real_data_add-6-1)) or my_xucr0_cls) and + st_entry0_val_l2 and ex6_ld_recov_val_not_fl; + +ex4st_hit_ex6_recov <= (ex6_ld_recov_l2((54) to (54+real_data_add-7-1)) = ex4_st_entry_l2(58 to (58+real_data_add-7-1))) and + ((ex6_ld_recov_l2(54+real_data_add-6-1) = ex4_st_entry_l2(58+real_data_add-6-1)) or my_xucr0_cls) and + ex4_st_val_l2 and ex6_ld_recov_val_not_fl; + +set_st_hit_recov_ld <= stq_hit_ex6_recov or ex4st_hit_ex6_recov; + + +reset_st_hit_recov_ld <= not (pe_recov_state_l2 or ex7_ld_par_err) or + (pe_recov_ld_num_l2(1) and lmq_empty and not ex7_ld_recov_val_l2) or + ((pe_recov_ld_num_l2(1) or pe_recov_ld_num_l2(2)) and lmq_empty and ex7_ld_recov_val_l2 and ex7_ld_recov_extra_l2(0)); + +st_hit_recov_ld_d <= (set_st_hit_recov_ld and not ex6_ld_recov_extra_l2(0)) or + (st_recycle_v_l2 and st_entry0_val_l2 and store_sent) or + (st_hit_recov_ld_l2 and not reset_st_hit_recov_ld); + +blk_st_for_pe_recov <= ex7_ld_par_err or (pe_recov_state_l2 and st_hit_recov_ld_l2); + +blk_st_cred_pop <= blk_st_for_pe_recov and not pe_recov_state_d; + +latch_st_hit_recov_ld : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(st_hit_recov_ld_offset to st_hit_recov_ld_offset), + scout => sov(st_hit_recov_ld_offset to st_hit_recov_ld_offset), + din(0) => st_hit_recov_ld_d, + dout(0) => st_hit_recov_ld_l2); + + + +ifetch_act <= i_x_request or clkg_ctl_override_q; + +latch_ifetch_req : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ifetch_req_offset to ifetch_req_offset), + scout => sov(ifetch_req_offset to ifetch_req_offset), + din(0) => i_x_request, + dout(0) => ifetch_req_l2); + +latch_ifetch_ra : tri_rlmreg_p + generic map (width => ifetch_ra_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ifetch_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ifetch_ra_offset to ifetch_ra_offset + ifetch_ra_l2'length-1), + scout => sov(ifetch_ra_offset to ifetch_ra_offset + ifetch_ra_l2'length-1), + din => i_x_ra, + dout => ifetch_ra_l2); + +latch_ifetch_wimge : tri_rlmreg_p + generic map (width => ifetch_wimge_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ifetch_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ifetch_wimge_offset to ifetch_wimge_offset + ifetch_wimge_l2'length-1), + scout => sov(ifetch_wimge_offset to ifetch_wimge_offset + ifetch_wimge_l2'length-1), + din => i_x_wimge, + dout => ifetch_wimge_l2); + +latch_ifetch_thread : tri_rlmreg_p + generic map (width => ifetch_thread_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ifetch_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ifetch_thread_offset to ifetch_thread_offset + ifetch_thread_l2'length-1), + scout => sov(ifetch_thread_offset to ifetch_thread_offset + ifetch_thread_l2'length-1), + din => i_x_thread, + dout => ifetch_thread_l2); + +latch_ifetch_userdef : tri_rlmreg_p + generic map (width => ifetch_userdef_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ifetch_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ifetch_userdef_offset to ifetch_userdef_offset + ifetch_userdef_l2'length-1), + scout => sov(ifetch_userdef_offset to ifetch_userdef_offset + ifetch_userdef_l2'length-1), + din => i_x_userdef, + dout => ifetch_userdef_l2); + +iu_f_tid0_val <= ifetch_req_l2 and ifetch_thread_l2(0); +iu_f_tid1_val <= ifetch_req_l2 and ifetch_thread_l2(1); +iu_f_tid2_val <= ifetch_req_l2 and ifetch_thread_l2(2); +iu_f_tid3_val <= ifetch_req_l2 and ifetch_thread_l2(3); + +iu_seq_incr <= std_ulogic_vector(unsigned(iu_seq_l2) + 1); + +iu_seq_d <= iu_seq_incr when ifetch_req_l2 = '1' else + iu_seq_l2; + +latch_iu_seq : tri_rlmreg_p + generic map (width => iu_seq_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => iuq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(iu_seq_offset to iu_seq_offset + iu_seq_l2'length-1), + scout => sov(iu_seq_offset to iu_seq_offset + iu_seq_l2'length-1), + din => iu_seq_d(0 to 2), + dout => iu_seq_l2(0 to 2)); + +iu_seq_rd_incr <= std_ulogic_vector(unsigned(iu_seq_rd_l2) + 1); + +iu_seq_rd_d <= iu_seq_rd_incr when iu_sent_val = '1' else + iu_seq_rd_l2; + +latch_iu_seq_rd : tri_rlmreg_p + generic map (width => iu_seq_rd_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => iuq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(iu_seq_rd_offset to iu_seq_rd_offset + iu_seq_rd_l2'length-1), + scout => sov(iu_seq_rd_offset to iu_seq_rd_offset + iu_seq_rd_l2'length-1), + din => iu_seq_rd_d, + dout => iu_seq_rd_l2); + + +iu_queue_entry <= ifetch_wimge_l2(0 to 4) & ifetch_userdef_l2(0 to 3) & ifetch_ra_l2 & iu_seq_l2; + + +iuq_act <= ifetch_req_l2 or iu_val_req or clkg_ctl_override_q; + +iu_f_q0_val_upd <= iu_f_tid0_val & i_f_q0_sent; + +with iu_f_q0_val_upd select + i_f_q0_val_d <= '1' when "10", + '0' when "01", + i_f_q0_val_l2 when others; + +with iu_f_tid0_val select + i_f_q0_d <= iu_queue_entry when '1', + i_f_q0_l2 when others; + +latch_iu_q0_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => iuq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(i_f_q0_val_offset to i_f_q0_val_offset), + scout => sov(i_f_q0_val_offset to i_f_q0_val_offset), + din(0) => i_f_q0_val_d, + dout(0) => i_f_q0_val_l2); + +latch_iu_q0 : tri_rlmreg_p + generic map (width => i_f_q0_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => iuq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(i_f_q0_offset to i_f_q0_offset + i_f_q0_l2'length-1), + scout => sov(i_f_q0_offset to i_f_q0_offset + i_f_q0_l2'length-1), + din => i_f_q0_d, + dout => i_f_q0_l2); + + +iu_f_q1_val_upd <= iu_f_tid1_val & i_f_q1_sent; + +with iu_f_q1_val_upd select + i_f_q1_val_d <= '1' when "10", + '0' when "01", + i_f_q1_val_l2 when others; + +with iu_f_tid1_val select + i_f_q1_d <= iu_queue_entry when '1', + i_f_q1_l2 when others; + +latch_iu_q1_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => iuq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(i_f_q1_val_offset to i_f_q1_val_offset), + scout => sov(i_f_q1_val_offset to i_f_q1_val_offset), + din(0) => i_f_q1_val_d, + dout(0) => i_f_q1_val_l2); + +latch_iu_q1 : tri_rlmreg_p + generic map (width => i_f_q1_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => iuq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(i_f_q1_offset to i_f_q1_offset + i_f_q1_l2'length-1), + scout => sov(i_f_q1_offset to i_f_q1_offset + i_f_q1_l2'length-1), + din => i_f_q1_d, + dout => i_f_q1_l2); + + +iu_f_q2_val_upd <= iu_f_tid2_val & i_f_q2_sent; + +with iu_f_q2_val_upd select + i_f_q2_val_d <= '1' when "10", + '0' when "01", + i_f_q2_val_l2 when others; + +with iu_f_tid2_val select + i_f_q2_d <= iu_queue_entry when '1', + i_f_q2_l2 when others; + +latch_iu_q2_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => iuq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(i_f_q2_val_offset to i_f_q2_val_offset), + scout => sov(i_f_q2_val_offset to i_f_q2_val_offset), + din(0) => i_f_q2_val_d, + dout(0) => i_f_q2_val_l2); + +latch_iu_q2 : tri_rlmreg_p + generic map (width => i_f_q2_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => iuq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(i_f_q2_offset to i_f_q2_offset + i_f_q2_l2'length-1), + scout => sov(i_f_q2_offset to i_f_q2_offset + i_f_q2_l2'length-1), + din => i_f_q2_d, + dout => i_f_q2_l2); + + +iu_f_q3_val_upd <= iu_f_tid3_val & i_f_q3_sent; + +with iu_f_q3_val_upd select + i_f_q3_val_d <= '1' when "10", + '0' when "01", + i_f_q3_val_l2 when others; + +with iu_f_tid3_val select + i_f_q3_d <= iu_queue_entry when '1', + i_f_q3_l2 when others; + +latch_iu_q3_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => iuq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(i_f_q3_val_offset to i_f_q3_val_offset), + scout => sov(i_f_q3_val_offset to i_f_q3_val_offset), + din(0) => i_f_q3_val_d, + dout(0) => i_f_q3_val_l2); + +latch_iu_q3 : tri_rlmreg_p + generic map (width => i_f_q3_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => iuq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(i_f_q3_offset to i_f_q3_offset + i_f_q3_l2'length-1), + scout => sov(i_f_q3_offset to i_f_q3_offset + i_f_q3_l2'length-1), + din => i_f_q3_d, + dout => i_f_q3_l2); + + + +mm_req_val_d <= not (mm_xu_lsu_req(0 to 3) = "0000"); + +mmq_act <= mm_req_val_d or clkg_ctl_override_q; + +mmu_q_val_d <= (not (mm_xu_lsu_req(0 to 3) = "0000")) or + (not mmu_sent and mmu_q_val_l2); + +mmu_command <= mm_xu_lsu_ttype(0 to 1) & + mm_xu_lsu_req(0 to 3) & + mm_xu_lsu_wimge(0 to 4) & + mm_xu_lsu_u(0 to 3) & + mm_xu_lsu_lpid(0 to 7) & + mm_xu_lsu_ind & + mm_xu_lsu_gs & + mm_xu_lsu_lbit & + mm_xu_lsu_addr(64-real_data_add to 63); + +mmu_q_entry_d <= mmu_command when mmu_q_val_l2 = '0' else + mmu_q_entry_l2; + +latch_mm_req_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(mm_req_val_offset to mm_req_val_offset), + scout => sov(mm_req_val_offset to mm_req_val_offset), + din(0) => mm_req_val_d, + dout(0) => mm_req_val_l2); + +latch_mmu_q_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(mmu_q_val_offset to mmu_q_val_offset), + scout => sov(mmu_q_val_offset to mmu_q_val_offset), + din(0) => mmu_q_val_d, + dout(0) => mmu_q_val_l2); + +latch_mmu_q_entry : tri_rlmreg_p + generic map (width => mmu_q_entry_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => mmq_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(mmu_q_entry_offset to mmu_q_entry_offset + mmu_q_entry_l2'length-1), + scout => sov(mmu_q_entry_offset to mmu_q_entry_offset + mmu_q_entry_l2'length-1), + din => mmu_q_entry_d, + dout => mmu_q_entry_l2); + + + + + +load_cmd_count_incr(0 to 3) <= std_ulogic_vector(unsigned(load_cmd_count_l2) + 1); +load_cmd_count_decr(0 to 3) <= std_ulogic_vector(unsigned(load_cmd_count_l2) - 1); +load_cmd_count_decrby2(0 to 3) <= std_ulogic_vector(unsigned(load_cmd_count_l2) - 2); + +load_credit_used <= load_sent or iu_sent_val or mmu_ld_sent; + + +decr_load_cnt_lcu0 <= ( anaclat_ld_pop and not (ex6_load_sent_l2 and (ex6_flush_l2 or ex7_ld_par_err))) or + (not anaclat_ld_pop and (ex6_load_sent_l2 and (ex6_flush_l2 or ex7_ld_par_err))); +dec_by2_ld_cnt_lcu0 <= anaclat_ld_pop and (ex6_load_sent_l2 and (ex6_flush_l2 or ex7_ld_par_err)); +hold_load_cnt_lcu0 <= (not anaclat_ld_pop and not (ex6_load_sent_l2 and (ex6_flush_l2 or ex7_ld_par_err))); + +incr_load_cnt_lcu1 <= not anaclat_ld_pop and not (ex6_load_sent_l2 and (ex6_flush_l2 or ex7_ld_par_err)); +decr_load_cnt_lcu1 <= ( anaclat_ld_pop and (ex6_load_sent_l2 and (ex6_flush_l2 or ex7_ld_par_err))); +hold_load_cnt_lcu1 <= (not anaclat_ld_pop and (ex6_load_sent_l2 and (ex6_flush_l2 or ex7_ld_par_err))) or + ( anaclat_ld_pop and not (ex6_load_sent_l2 and (ex6_flush_l2 or ex7_ld_par_err))); + + + +load_cmd_count_lcu0(0 to 3) <= gate_and(decr_load_cnt_lcu0, load_cmd_count_decr(0 to 3)) or + gate_and(dec_by2_ld_cnt_lcu0, load_cmd_count_decrby2(0 to 3)) or + gate_and(hold_load_cnt_lcu0, load_cmd_count_l2); +load_cmd_count_lcu1(0 to 3) <= gate_and(incr_load_cnt_lcu1, load_cmd_count_incr(0 to 3)) or + gate_and(decr_load_cnt_lcu1, load_cmd_count_decr(0 to 3)) or + gate_and(hold_load_cnt_lcu1, load_cmd_count_l2); + +load_cmd_count_d(0 to 3) <= gate_and(not load_credit_used, load_cmd_count_lcu0) or + gate_and( load_credit_used, load_cmd_count_lcu1); + +latch_load_cmd_count : tri_rlmreg_p + generic map (width => load_cmd_count_l2'length, init => 6, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => cfg_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => cfg_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => bcfg_siv(load_cmd_count_offset to load_cmd_count_offset + load_cmd_count_l2'length-1), + scout => bcfg_sov(load_cmd_count_offset to load_cmd_count_offset + load_cmd_count_l2'length-1), + din => load_cmd_count_d(0 to 3), + dout => load_cmd_count_l2(0 to 3) ); + +ld_credit_pre <= not load_cmd_count_l2(0); + +load_credit <= ld_credit_pre and not (my_xucr0_cred and not st_credit_pre); + + +store_cmd_count_incr(0 to 5) <= std_ulogic_vector(unsigned(store_cmd_count_l2) + 1); +store_cmd_count_decr(0 to 5) <= std_ulogic_vector(unsigned(store_cmd_count_l2) - 1); +store_cmd_count_decby2(0 to 5) <= std_ulogic_vector(unsigned(store_cmd_count_l2) - 2); +store_cmd_count_decby3(0 to 5) <= std_ulogic_vector(unsigned(store_cmd_count_l2) - 3); + + +st_count_ctrl(0) <= store_sent or mmu_st_sent; +st_count_ctrl(1) <= anaclat_st_pop; +st_count_ctrl(2) <= anaclat_st_gather; +st_count_ctrl(3) <= (ex6_store_sent_l2 and ex6_flush_l2) or + (l2req_recycle_l2 and ex7_ld_par_err); + +incr_store_cmd <= st_count_ctrl="1000"; + +decr_store_cmd <= (st_count_ctrl="0001") or + (st_count_ctrl="0010") or + (st_count_ctrl="0100") or + (st_count_ctrl="1011") or + (st_count_ctrl="1101") or + (st_count_ctrl="1110"); + +dec_by2_st_cmd <= (st_count_ctrl="0011") or + (st_count_ctrl="0101") or + (st_count_ctrl="0110") or + (st_count_ctrl="1111"); + +dec_by3_st_cmd <= (st_count_ctrl="0111"); + +hold_store_cmd <= (st_count_ctrl="0000") or + (st_count_ctrl="1001") or + (st_count_ctrl="1100") or + (st_count_ctrl="1010"); + + +store_cmd_count_d(0 to 5) <= gate_and(incr_store_cmd, store_cmd_count_incr(0 to 5)) or + gate_and(decr_store_cmd, store_cmd_count_decr(0 to 5)) or + gate_and(dec_by2_st_cmd, store_cmd_count_decby2(0 to 5)) or + gate_and(dec_by3_st_cmd, store_cmd_count_decby3(0 to 5)) or + gate_and(hold_store_cmd, store_cmd_count_l2(0 to 5)); + +latch_store_cmd_count : tri_rlmreg_p + generic map (width => store_cmd_count_l2'length, init => 28, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => cfg_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => cfg_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => bcfg_siv(store_cmd_count_offset to store_cmd_count_offset + store_cmd_count_l2'length-1), + scout => bcfg_sov(store_cmd_count_offset to store_cmd_count_offset + store_cmd_count_l2'length-1), + din => store_cmd_count_d(0 to 5), + dout => store_cmd_count_l2(0 to 5) ); + + +st_credit_pre <= not store_cmd_count_l2(0); + +store_credit <= st_credit_pre and not (my_xucr0_cred and not ld_credit_pre ) and not blk_st_for_pe_recov; +one_st_cred <= store_cmd_count_l2="011111"; + +iu_f_q0_sel <= (iu_seq_rd_l2 = i_f_q0_l2((REAL_IFAR_length+9) to (REAL_IFAR_length+11))) and i_f_q0_val_l2; +iu_f_q1_sel <= (iu_seq_rd_l2 = i_f_q1_l2((REAL_IFAR_length+9) to (REAL_IFAR_length+11))) and i_f_q1_val_l2; +iu_f_q2_sel <= (iu_seq_rd_l2 = i_f_q2_l2((REAL_IFAR_length+9) to (REAL_IFAR_length+11))) and i_f_q2_val_l2; +iu_f_q3_sel <= (iu_seq_rd_l2 = i_f_q3_l2((REAL_IFAR_length+9) to (REAL_IFAR_length+11))) and i_f_q3_val_l2; + +iu_f_q_sel(0) <= (not iu_f_q0_sel and not iu_f_q1_sel and not iu_f_q2_sel and iu_f_q3_sel) or + (not iu_f_q0_sel and not iu_f_q1_sel and iu_f_q2_sel and not iu_f_q3_sel); + +iu_f_q_sel(1) <= (not iu_f_q0_sel and not iu_f_q1_sel and not iu_f_q2_sel and iu_f_q3_sel) or + (not iu_f_q0_sel and iu_f_q1_sel and not iu_f_q2_sel and not iu_f_q3_sel); + +with iu_f_q_sel select + iu_f_sel_entry <= i_f_q3_l2(0 to (9+REAL_IFAR_length-1)) when "11", + i_f_q2_l2(0 to (9+REAL_IFAR_length-1)) when "10", + i_f_q1_l2(0 to (9+REAL_IFAR_length-1)) when "01", + i_f_q0_l2(0 to (9+REAL_IFAR_length-1)) when others; + +i_f_q0_sent <= iu_f_q0_sel and load_credit and send_if_req_l2 and not (ex5_sel_st_req or ((ob_req_val_l2 or ob_ditc_val_l2 or st_recycle_v_l2) and store_credit)) and + not (l2req_resend_l2 and ex7_ld_par_err); +i_f_q1_sent <= iu_f_q1_sel and load_credit and send_if_req_l2 and not (ex5_sel_st_req or ((ob_req_val_l2 or ob_ditc_val_l2 or st_recycle_v_l2) and store_credit)) and + not (l2req_resend_l2 and ex7_ld_par_err); +i_f_q2_sent <= iu_f_q2_sel and load_credit and send_if_req_l2 and not (ex5_sel_st_req or ((ob_req_val_l2 or ob_ditc_val_l2 or st_recycle_v_l2) and store_credit)) and + not (l2req_resend_l2 and ex7_ld_par_err); +i_f_q3_sent <= iu_f_q3_sel and load_credit and send_if_req_l2 and not (ex5_sel_st_req or ((ob_req_val_l2 or ob_ditc_val_l2 or st_recycle_v_l2) and store_credit)) and + not (l2req_resend_l2 and ex7_ld_par_err); + +iu_val_req <= i_f_q0_val_l2 or i_f_q1_val_l2 or i_f_q2_val_l2 or i_f_q3_val_l2; + +iu_sent_val <= iu_val_req and load_credit and send_if_req_l2 and + not (ex5_sel_st_req or ((ob_req_val_l2 or ob_ditc_val_l2 or st_recycle_v_l2) and store_credit)) and + not (l2req_resend_l2 and ex7_ld_par_err); + +iu_val <= iu_val_req or ifetch_req_l2; +ld_q_val <= ex4_ld_m_val_not_fl or + (selected_ld_entry_val and not (lq_rd_en_is_ex5 and ex5_flush_load_local) and not (lq_rd_en_is_ex6 and ex6_flush_l2) ); + +ld_q_req <= ex4_ld_m_val_not_fl; + +mmu_q_val <= mmu_q_val_l2 and not mm_req_val_l2; + +state_trans <= ((ifetch_req_l2 or ld_q_req or mm_req_val_l2) and not (iu_val_req or selected_ld_entry_val or mmu_q_val_l2)) or + (load_sent or load_flushed or iu_sent_val or mmu_sent) or + (send_if_req_l2 and not iu_val) or (send_ld_req_l2 and not ld_q_val) or (send_mm_req_l2 and not mmu_q_val_l2); + + + +sel_if_req <= ( iu_val and not ld_q_val and not mmu_q_val_l2 ) or + ( iu_val and not ld_q_val and mmu_q_val_l2 and send_mm_req_l2) or + ( iu_val and ld_q_val and not mmu_q_val_l2 and send_ld_req_l2) or + ( iu_val and ld_q_val and not mmu_q_val_l2 and send_mm_req_l2) or + ( iu_val and ld_q_val and mmu_q_val_l2 and send_mm_req_l2) or + (not iu_val and not ld_q_val and not mmu_q_val_l2 and send_if_req_l2); + +sel_ld_req <= (not iu_val and ld_q_val and not mmu_q_val_l2 ) or + (not iu_val and ld_q_val and mmu_q_val_l2 and send_if_req_l2) or + (not iu_val and ld_q_val and mmu_q_val_l2 and send_mm_req_l2) or + ( iu_val and ld_q_val and not mmu_q_val_l2 and send_if_req_l2) or + ( iu_val and ld_q_val and mmu_q_val_l2 and send_if_req_l2) or + (not iu_val and not ld_q_val and not mmu_q_val_l2 and send_ld_req_l2); + +sel_mm_req <= (not iu_val and not ld_q_val and mmu_q_val_l2 ) or + (not iu_val and ld_q_val and mmu_q_val_l2 and send_ld_req_l2) or + ( iu_val and not ld_q_val and mmu_q_val_l2 and send_if_req_l2) or + ( iu_val and not ld_q_val and mmu_q_val_l2 and send_ld_req_l2) or + ( iu_val and ld_q_val and mmu_q_val_l2 and send_ld_req_l2) or + (not iu_val and not ld_q_val and not mmu_q_val_l2 and send_mm_req_l2); + + +with state_trans select + send_if_req_d <= sel_if_req when '1', + send_if_req_l2 when others; + +with state_trans select + send_ld_req_d <= sel_ld_req when '1', + send_ld_req_l2 when others; + +with state_trans select + send_mm_req_d <= sel_mm_req when '1', + send_mm_req_l2 when others; + +latch_send_if_req : tri_rlmreg_p + generic map (width => 1, init => 1, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(send_if_req_offset to send_if_req_offset), + scout => sov(send_if_req_offset to send_if_req_offset), + din(0) => send_if_req_d, + dout(0) => send_if_req_l2); + +latch_send_ld_req : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(send_ld_req_offset to send_ld_req_offset), + scout => sov(send_ld_req_offset to send_ld_req_offset), + din(0) => send_ld_req_d, + dout(0) => send_ld_req_l2); + +latch_send_mm_req : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(send_mm_req_offset to send_mm_req_offset), + scout => sov(send_mm_req_offset to send_mm_req_offset), + din(0) => send_mm_req_d, + dout(0) => send_mm_req_l2); + + + + + +latch_reld_data_vld : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(reld_data_vld_offset to reld_data_vld_offset), + scout => sov(reld_data_vld_offset to reld_data_vld_offset), + din(0) => data_val_dminus1_l2, + dout(0) => reld_data_vld_l2); + +latch_rel_tag : tri_rlmreg_p + generic map (width => rel_tag_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dminus1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(rel_tag_offset to rel_tag_offset + rel_tag_l2'length-1), + scout => sov(rel_tag_offset to rel_tag_offset + rel_tag_l2'length-1), + din => tag_dminus1_l2, + dout => rel_tag_l2 ); + + + +latch_reld_data_vld_dplus1 : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(reld_data_vld_dplus1_offset to reld_data_vld_dplus1_offset), + scout => sov(reld_data_vld_dplus1_offset to reld_data_vld_dplus1_offset), + din(0) => reld_data_vld_l2, + dout(0) => reld_data_vld_dplus1_l2); + +dplus1_act <= reld_data_vld_l2 or clkg_ctl_override_q; + +latch_rel_tag_dplus1 : tri_rlmreg_p + generic map (width => rel_tag_dplus1_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dplus1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(rel_tag_dplus1_offset to rel_tag_dplus1_offset + rel_tag_dplus1_l2'length-1), + scout => sov(rel_tag_dplus1_offset to rel_tag_dplus1_offset + rel_tag_dplus1_l2'length-1), + din => rel_tag_l2, + dout => rel_tag_dplus1_l2); + + + + + + + + +rel_entry_gen: for i in 0 to lmq_entries-1 generate begin + rel_entry(i) <= l_m_queue(i)(0) & + l_m_queue(i)(7 to 12) & + l_m_queue(i)(13 to 17) & + l_m_queue(i)(18 to 21) & + l_m_queue(i)(27 to 35) & + l_m_queue(i)(36) & + l_m_queue(i)(37) & + l_m_queue(i)(38) & + l_m_queue(i)(47) & + (l_m_queue(i)(48) or lmq_drop_rel_l2(i)) & + l_m_queue(i)(49) & + l_m_queue(i)(50 to 51) & + l_m_queue(i)(52); + + rel_tag_1hot(i) <= tag_dminus1_1hot_l2(i); + + cmp_rel_tag_1hot(i) <= rel_tag_1hot(i); + + rel_data_val(i) <= data_val_dminus1_l2 and rel_tag_1hot(i); + + start_rel(i) <= rel_data_val(i) and not l_m_rel_inprog_l2(i); + + + + + + + + rel_data_val_dplus1(i) <= reld_data_vld_dplus1_l2 and (rel_tag_dplus1_l2(1 to 4) = tconv(i, 4)) and rel_intf_v_dplus1_l2; + + set_data_ecc_err(i) <= beat_ecc_err and rel_data_val_dplus1(i); + + data_ecc_err_d(i) <= set_data_ecc_err(i) or + (not ld_m_rel_done_dly2_l2(i) and data_ecc_err_l2(i) ); + + set_data_ecc_ue(i) <= anaclat_ecc_err_ue and rel_data_val_dplus1(i); + + data_ecc_ue_d(i) <= set_data_ecc_ue(i) or + (not ld_m_rel_done_dly2_l2(i) and data_ecc_ue_l2(i) ); + +end generate; + + +latch_data_ecc_err : tri_rlmreg_p + generic map (width => data_ecc_err_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(data_ecc_err_offset to data_ecc_err_offset + data_ecc_err_l2'length-1), + scout => sov(data_ecc_err_offset to data_ecc_err_offset + data_ecc_err_l2'length-1), + din => data_ecc_err_d, + dout => data_ecc_err_l2 ); + +latch_data_ecc_ue : tri_rlmreg_p + generic map (width => data_ecc_ue_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(data_ecc_ue_offset to data_ecc_ue_offset + data_ecc_ue_l2'length-1), + scout => sov(data_ecc_ue_offset to data_ecc_ue_offset + data_ecc_ue_l2'length-1), + din => data_ecc_ue_d, + dout => data_ecc_ue_l2 ); + + + + + +q4: if lmq_entries=4 generate begin + with tag_dminus1_l2(1 to 4) select + rel_q_entry <= rel_entry(0) when "0000", + rel_entry(1) when "0001", + rel_entry(2) when "0010", + rel_entry(3) when "0011", + (others => '0') when others; + with tag_dminus1_l2(1 to 4) select + rel_q_addrlo_58 <= l_m_queue_addrlo(0)(58) when "0000", + l_m_queue_addrlo(1)(58) when "0001", + l_m_queue_addrlo(2)(58) when "0010", + l_m_queue_addrlo(3)(58) when "0011", + '0' when others; + + with tag_dminus1_l2(1 to 4) select + rel_dvc1_d <= lmq_dvc1_en_l2(0) when "0000", + lmq_dvc1_en_l2(1) when "0001", + lmq_dvc1_en_l2(2) when "0010", + lmq_dvc1_en_l2(3) when "0011", + '0' when others; + + with tag_dminus1_l2(1 to 4) select + rel_dvc2_d <= lmq_dvc2_en_l2(0) when "0000", + lmq_dvc2_en_l2(1) when "0001", + lmq_dvc2_en_l2(2) when "0010", + lmq_dvc2_en_l2(3) when "0011", + '0' when others; + +end generate; + +q8: if lmq_entries=8 generate begin + with tag_dminus1_l2(1 to 4) select + rel_q_entry <= rel_entry(0) when "0000", + rel_entry(1) when "0001", + rel_entry(2) when "0010", + rel_entry(3) when "0011", + rel_entry(4) when "0100", + rel_entry(5) when "0101", + rel_entry(6) when "0110", + rel_entry(7) when "0111", + (others => '0') when others; + with tag_dminus1_l2(1 to 4) select + rel_q_addrlo_58 <= l_m_queue_addrlo(0)(58) when "0000", + l_m_queue_addrlo(1)(58) when "0001", + l_m_queue_addrlo(2)(58) when "0010", + l_m_queue_addrlo(3)(58) when "0011", + l_m_queue_addrlo(4)(58) when "0100", + l_m_queue_addrlo(5)(58) when "0101", + l_m_queue_addrlo(6)(58) when "0110", + l_m_queue_addrlo(7)(58) when "0111", + '0' when others; + + with tag_dminus1_l2(1 to 4) select + rel_dvc1_d <= lmq_dvc1_en_l2(0) when "0000", + lmq_dvc1_en_l2(1) when "0001", + lmq_dvc1_en_l2(2) when "0010", + lmq_dvc1_en_l2(3) when "0011", + lmq_dvc1_en_l2(4) when "0100", + lmq_dvc1_en_l2(5) when "0101", + lmq_dvc1_en_l2(6) when "0110", + lmq_dvc1_en_l2(7) when "0111", + '0' when others; + + with tag_dminus1_l2(1 to 4) select + rel_dvc2_d <= lmq_dvc2_en_l2(0) when "0000", + lmq_dvc2_en_l2(1) when "0001", + lmq_dvc2_en_l2(2) when "0010", + lmq_dvc2_en_l2(3) when "0011", + lmq_dvc2_en_l2(4) when "0100", + lmq_dvc2_en_l2(5) when "0101", + lmq_dvc2_en_l2(6) when "0110", + lmq_dvc2_en_l2(7) when "0111", + '0' when others; + +end generate; + +rel_cache_inh_d <= rel_q_entry(0) and data_val_dminus1_l2 and not tag_dminus1_l2(1); +rel_size_d(0 to 5) <= rel_q_entry(1 to 6); +rel_rot_sel_d(0 to 4) <= rel_q_entry(7 to 11); +rel_th_id_d(0 to 3) <= rel_q_entry(12 to 15); +rel_tar_gpr_d(0 to 8) <= rel_q_entry(16 to 24); +rel_vpr_val_d <= rel_q_entry(25); +rel_le_mode_d <= rel_q_entry(26); +rel_dcbt_d <= rel_q_entry(27); +rel_algebraic_d <= rel_q_entry(28); +rel_l2only_d <= rel_q_entry(29) or (dminus1_l1_dump and rel_intf_v_dminus1_l2); +rel_lock_en_d <= rel_q_entry(30); +rel_classid_d <= rel_q_entry(31 to 32); +rel_watch_en_d <= rel_q_entry(33); +rel_addr_d <= cmp_rel_addr & rel_q_addrlo_58; + + + + +rel_beats_gen: for i in 0 to lmq_entries-1 generate begin + + l_m_rel_c_i_beat0_d(i) <= (start_rel(i) and rel_cache_inh_d and rel_size_d(0)) or + (l_m_rel_c_i_beat0_l2(i) and not rel_data_val(i)); + + l_m_rel_c_i_val(i) <= (start_rel(i) and rel_cache_inh_d and not rel_size_d(0)) or + (l_m_rel_c_i_beat0_l2(i) and rel_data_val(i) ); + + + + + l_m_rel_hit_beat0_d(i) <= (start_rel(i) and not rel_cache_inh_d ) or (l_m_rel_hit_beat0_l2(i) and not rel_data_val(i)); + l_m_rel_hit_beat1_d(i) <= (l_m_rel_hit_beat0_l2(i) and rel_data_val(i) ) or (l_m_rel_hit_beat1_l2(i) and not rel_data_val(i) ); + l_m_rel_hit_beat2_d(i) <= (l_m_rel_hit_beat1_l2(i) and rel_data_val(i) ) or (l_m_rel_hit_beat2_l2(i) and not rel_data_val(i) ) or + (ld_m_rel_done_l2(i) and ldq_recirc_rel_val and not ecc_err(i) and not my_xucr0_cls); + l_m_rel_hit_beat3_d(i) <= (l_m_rel_hit_beat2_l2(i) and rel_data_val(i) ) or (l_m_rel_hit_beat3_l2(i) and not rel_data_val(i) and my_xucr0_cls); + l_m_rel_hit_beat4_d(i) <= (l_m_rel_hit_beat3_l2(i) and rel_data_val(i) and my_xucr0_cls) or (l_m_rel_hit_beat4_l2(i) and not rel_data_val(i) ); + l_m_rel_hit_beat5_d(i) <= (l_m_rel_hit_beat4_l2(i) and rel_data_val(i) ) or (l_m_rel_hit_beat5_l2(i) and not rel_data_val(i) ); + l_m_rel_hit_beat6_d(i) <= (l_m_rel_hit_beat5_l2(i) and rel_data_val(i) ) or (l_m_rel_hit_beat6_l2(i) and not rel_data_val(i) ) or + (ld_m_rel_done_l2(i) and ldq_recirc_rel_val and not ecc_err(i) and my_xucr0_cls); + l_m_rel_hit_beat7_d(i) <= (l_m_rel_hit_beat6_l2(i) and rel_data_val(i) ); + l_m_rel_inprog_d(i) <= l_m_rel_hit_beat0_d(i) or l_m_rel_c_i_beat0_d(i) or + (ld_m_rel_done_l2(i) and ldq_recirc_rel_val and not ecc_err(i)) or + (l_m_rel_inprog_l2(i) and not (l_m_rel_hit_beat3_l2(i) and not my_xucr0_cls) and + not (l_m_rel_hit_beat7_l2(i) and my_xucr0_cls) and + not l_m_rel_val_c_i_dly(i)); + +end generate; + +latch_rel_hit_beat0 : tri_rlmreg_p + generic map (width => l_m_rel_hit_beat0_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(l_m_rel_hit_beat0_offset to l_m_rel_hit_beat0_offset + l_m_rel_hit_beat0_l2'length-1), + scout => sov(l_m_rel_hit_beat0_offset to l_m_rel_hit_beat0_offset + l_m_rel_hit_beat0_l2'length-1), + din => l_m_rel_hit_beat0_d, + dout => l_m_rel_hit_beat0_l2); +latch_rel_hit_beat1 : tri_rlmreg_p + generic map (width => l_m_rel_hit_beat1_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(l_m_rel_hit_beat1_offset to l_m_rel_hit_beat1_offset + l_m_rel_hit_beat1_l2'length-1), + scout => sov(l_m_rel_hit_beat1_offset to l_m_rel_hit_beat1_offset + l_m_rel_hit_beat1_l2'length-1), + din => l_m_rel_hit_beat1_d, + dout => l_m_rel_hit_beat1_l2); +latch_rel_hit_beat2 : tri_rlmreg_p + generic map (width => l_m_rel_hit_beat2_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(l_m_rel_hit_beat2_offset to l_m_rel_hit_beat2_offset + l_m_rel_hit_beat2_l2'length-1), + scout => sov(l_m_rel_hit_beat2_offset to l_m_rel_hit_beat2_offset + l_m_rel_hit_beat2_l2'length-1), + din => l_m_rel_hit_beat2_d, + dout => l_m_rel_hit_beat2_l2); +latch_rel_hit_beat3 : tri_rlmreg_p + generic map (width => l_m_rel_hit_beat3_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(l_m_rel_hit_beat3_offset to l_m_rel_hit_beat3_offset + l_m_rel_hit_beat3_l2'length-1), + scout => sov(l_m_rel_hit_beat3_offset to l_m_rel_hit_beat3_offset + l_m_rel_hit_beat3_l2'length-1), + din => l_m_rel_hit_beat3_d, + dout => l_m_rel_hit_beat3_l2); + + latch_rel_hit_beat4 : tri_rlmreg_p + generic map (width => l_m_rel_hit_beat4_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(l_m_rel_hit_beat4_offset to l_m_rel_hit_beat4_offset + l_m_rel_hit_beat4_l2'length-1), + scout => sov(l_m_rel_hit_beat4_offset to l_m_rel_hit_beat4_offset + l_m_rel_hit_beat4_l2'length-1), + din => l_m_rel_hit_beat4_d, + dout => l_m_rel_hit_beat4_l2); + latch_rel_hit_beat5 : tri_rlmreg_p + generic map (width => l_m_rel_hit_beat5_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(l_m_rel_hit_beat5_offset to l_m_rel_hit_beat5_offset + l_m_rel_hit_beat5_l2'length-1), + scout => sov(l_m_rel_hit_beat5_offset to l_m_rel_hit_beat5_offset + l_m_rel_hit_beat5_l2'length-1), + din => l_m_rel_hit_beat5_d, + dout => l_m_rel_hit_beat5_l2); + latch_rel_hit_beat6 : tri_rlmreg_p + generic map (width => l_m_rel_hit_beat6_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(l_m_rel_hit_beat6_offset to l_m_rel_hit_beat6_offset + l_m_rel_hit_beat6_l2'length-1), + scout => sov(l_m_rel_hit_beat6_offset to l_m_rel_hit_beat6_offset + l_m_rel_hit_beat6_l2'length-1), + din => l_m_rel_hit_beat6_d, + dout => l_m_rel_hit_beat6_l2); + latch_rel_hit_beat7 : tri_rlmreg_p + generic map (width => l_m_rel_hit_beat7_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(l_m_rel_hit_beat7_offset to l_m_rel_hit_beat7_offset + l_m_rel_hit_beat7_l2'length-1), + scout => sov(l_m_rel_hit_beat7_offset to l_m_rel_hit_beat7_offset + l_m_rel_hit_beat7_l2'length-1), + din => l_m_rel_hit_beat7_d, + dout => l_m_rel_hit_beat7_l2); + +latch_rel_inprog : tri_rlmreg_p + generic map (width => l_m_rel_inprog_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(l_m_rel_inprog_offset to l_m_rel_inprog_offset + l_m_rel_inprog_l2'length-1), + scout => sov(l_m_rel_inprog_offset to l_m_rel_inprog_offset + l_m_rel_inprog_l2'length-1), + din => l_m_rel_inprog_d, + dout => l_m_rel_inprog_l2); + +latch_rel_c_i_beat0 : tri_rlmreg_p + generic map (width => l_m_rel_c_i_beat0_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(l_m_rel_c_i_beat0_offset to l_m_rel_c_i_beat0_offset + l_m_rel_c_i_beat0_l2'length-1), + scout => sov(l_m_rel_c_i_beat0_offset to l_m_rel_c_i_beat0_offset + l_m_rel_c_i_beat0_l2'length-1), + din => l_m_rel_c_i_beat0_d, + dout => l_m_rel_c_i_beat0_l2); + +latch_rel_c_i_val : tri_rlmreg_p + generic map (width => l_m_rel_val_c_i_dly'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(l_m_rel_c_i_val_offset to l_m_rel_c_i_val_offset + l_m_rel_val_c_i_dly'length-1), + scout => sov(l_m_rel_c_i_val_offset to l_m_rel_c_i_val_offset + l_m_rel_val_c_i_dly'length-1), + din => l_m_rel_c_i_val, + dout => l_m_rel_val_c_i_dly); + + + +latch_rel_addr : tri_rlmreg_p + generic map (width => rel_addr_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dminus1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(rel_addr_offset to rel_addr_offset + rel_addr_l2'length-1), + scout => sov(rel_addr_offset to rel_addr_offset + rel_addr_l2'length-1), + din => rel_addr_d, + dout => rel_addr_l2); +latch_rel_cache_inh : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(rel_cache_inh_offset to rel_cache_inh_offset), + scout => sov(rel_cache_inh_offset to rel_cache_inh_offset), + din(0) => rel_cache_inh_d, + dout(0) => rel_cache_inh_l2); +latch_rel_size : tri_rlmreg_p + generic map (width => rel_size_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dminus1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(rel_size_offset to rel_size_offset + rel_size_l2'length-1), + scout => sov(rel_size_offset to rel_size_offset + rel_size_l2'length-1), + din => rel_size_d, + dout => rel_size_l2); +latch_rel_rot_sel : tri_rlmreg_p + generic map (width => rel_rot_sel_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dminus1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(rel_rot_sel_offset to rel_rot_sel_offset + rel_rot_sel_l2'length-1), + scout => sov(rel_rot_sel_offset to rel_rot_sel_offset + rel_rot_sel_l2'length-1), + din => rel_rot_sel_d, + dout => rel_rot_sel_l2); +latch_rel_th_id : tri_rlmreg_p + generic map (width => rel_th_id_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dminus1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(rel_th_id_offset to rel_th_id_offset + rel_th_id_l2'length-1), + scout => sov(rel_th_id_offset to rel_th_id_offset + rel_th_id_l2'length-1), + din => rel_th_id_d, + dout => rel_th_id_l2); +latch_rel_tar_gpr : tri_rlmreg_p + generic map (width => rel_tar_gpr_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dminus1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(rel_tar_gpr_offset to rel_tar_gpr_offset + rel_tar_gpr_l2'length-1), + scout => sov(rel_tar_gpr_offset to rel_tar_gpr_offset + rel_tar_gpr_l2'length-1), + din => rel_tar_gpr_d, + dout => rel_tar_gpr_l2); +latch_rel_vpr_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dminus1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(rel_vpr_val_offset to rel_vpr_val_offset), + scout => sov(rel_vpr_val_offset to rel_vpr_val_offset), + din(0) => rel_vpr_val_d, + dout(0) => rel_vpr_val_l2); +latch_rel_le_mode : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(rel_le_mode_offset to rel_le_mode_offset), + scout => sov(rel_le_mode_offset to rel_le_mode_offset), + din(0) => rel_le_mode_d, + dout(0) => rel_le_mode_l2); +latch_rel_dcbt : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dminus1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(rel_dcbt_offset to rel_dcbt_offset), + scout => sov(rel_dcbt_offset to rel_dcbt_offset), + din(0) => rel_dcbt_d, + dout(0) => rel_dcbt_l2); +latch_rel_algebraic : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dminus1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(rel_algebraic_offset to rel_algebraic_offset), + scout => sov(rel_algebraic_offset to rel_algebraic_offset), + din(0) => rel_algebraic_d, + dout(0) => rel_algebraic_l2); +latch_rel_l2only : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dminus1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(rel_l2only_offset to rel_l2only_offset), + scout => sov(rel_l2only_offset to rel_l2only_offset), + din(0) => rel_l2only_d, + dout(0) => rel_l2only_l2); +latch_rel_l2only_dly : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(rel_l2only_dly_offset to rel_l2only_dly_offset), + scout => sov(rel_l2only_dly_offset to rel_l2only_dly_offset), + din(0) => rel_l2only_l2, + dout(0) => rel_l2only_dly_l2); +latch_rel_lock_en : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dminus1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(rel_lock_en_offset to rel_lock_en_offset), + scout => sov(rel_lock_en_offset to rel_lock_en_offset), + din(0) => rel_lock_en_d, + dout(0) => rel_lock_en_l2); +latch_rel_classid : tri_rlmreg_p + generic map (width => rel_classid_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dminus1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(rel_classid_offset to rel_classid_offset + rel_classid_l2'length-1), + scout => sov(rel_classid_offset to rel_classid_offset + rel_classid_l2'length-1), + din => rel_classid_d, + dout => rel_classid_l2); +latch_rel_dvc1 : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dminus1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(rel_dvc1_offset to rel_dvc1_offset), + scout => sov(rel_dvc1_offset to rel_dvc1_offset), + din(0) => rel_dvc1_d, + dout(0) => rel_dvc1_l2); +latch_rel_dvc2 : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dminus1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(rel_dvc2_offset to rel_dvc2_offset), + scout => sov(rel_dvc2_offset to rel_dvc2_offset), + din(0) => rel_dvc2_d, + dout(0) => rel_dvc2_l2); +latch_rel_watch_en : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dminus1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(rel_watch_en_offset to rel_watch_en_offset), + scout => sov(rel_watch_en_offset to rel_watch_en_offset), + din(0) => rel_watch_en_d, + dout(0) => rel_watch_en_l2); + + + + +rel_done_g: for i in 0 to lmq_entries-1 generate begin + ld_m_rel_done_d(i) <= (l_m_rel_hit_beat3_l2(i) and not my_xucr0_cls) or + (l_m_rel_hit_beat7_l2(i) and my_xucr0_cls) or + l_m_rel_val_c_i_dly(i); + + ldq_retry_d(i) <= (ld_m_rel_done_l2(i) and ldq_recirc_rel_val and not ecc_err(i)) or + (ldq_retry_l2(i) and not ld_m_rel_done_l2(i)); +end generate; + + +latch_ld_m_rel_done : tri_rlmreg_p + generic map (width => ld_m_rel_done_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ld_m_rel_done_offset to ld_m_rel_done_offset + ld_m_rel_done_l2'length-1), + scout => sov(ld_m_rel_done_offset to ld_m_rel_done_offset + ld_m_rel_done_l2'length-1), + din => ld_m_rel_done_d(0 to lmq_entries-1), + dout => ld_m_rel_done_l2(0 to lmq_entries-1)); + +ld_m_rel_done_no_retry <= not gate_and(ldq_recirc_rel_val, not ecc_err) and ld_m_rel_done_l2; + +latch_ldq_retry : tri_rlmreg_p + generic map (width => ldq_retry_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ldq_retry_offset to ldq_retry_offset + ldq_retry_l2'length-1), + scout => sov(ldq_retry_offset to ldq_retry_offset + ldq_retry_l2'length-1), + din => ldq_retry_d(0 to lmq_entries-1), + dout => ldq_retry_l2(0 to lmq_entries-1)); + +latch_ld_m_rel_done_dly : tri_rlmreg_p + generic map (width => ld_m_rel_done_dly_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ld_m_rel_done_dly_offset to ld_m_rel_done_dly_offset + ld_m_rel_done_dly_l2'length-1), + scout => sov(ld_m_rel_done_dly_offset to ld_m_rel_done_dly_offset + ld_m_rel_done_dly_l2'length-1), + din => ld_m_rel_done_no_retry(0 to lmq_entries-1), + dout => ld_m_rel_done_dly_l2(0 to lmq_entries-1)); + +latch_ld_m_rel_done_dly2 : tri_rlmreg_p + generic map (width => ld_m_rel_done_dly2_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ld_m_rel_done_dly2_offset to ld_m_rel_done_dly2_offset + ld_m_rel_done_dly2_l2'length-1), + scout => sov(ld_m_rel_done_dly2_offset to ld_m_rel_done_dly2_offset + ld_m_rel_done_dly2_l2'length-1), + din => ld_m_rel_done_dly_l2(0 to lmq_entries-1), + dout => ld_m_rel_done_dly2_l2(0 to lmq_entries-1)); + +reset_lmq_gen: for i in 0 to lmq_entries-1 generate begin + reset_lmq_entry_rel(i) <= ld_m_rel_done_dly2_l2(i) and not data_ecc_err_l2(i); +end generate; + + + + +any_ld_val_p: process (ld_entry_val_l2) + variable b: std_ulogic; +begin + b := '0'; + for i in 0 to lmq_entries-1 loop + b := ld_entry_val_l2(i) or b; + end loop; + any_ld_entry_val <= b; +end process; + + + + +blk_ld_for_pe_recov_d <= ex7_ld_par_err or + (blk_ld_for_pe_recov_l2 and not pe_recov_begin); +latch_blk_ld_for_pe_recov : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(blk_ld_for_pe_recov_offset to blk_ld_for_pe_recov_offset), + scout => sov(blk_ld_for_pe_recov_offset to blk_ld_for_pe_recov_offset), + din(0) => blk_ld_for_pe_recov_d, + dout(0) => blk_ld_for_pe_recov_l2 ); + +lq_rd_en_gen: for i in 0 to lmq_entries-1 generate begin + + ldq_rd_seq_match_curr(i) <= l_m_queue(i)(22 to 26) = cmd_seq_rd_l2(0 to 4); + ldq_rd_seq_match_next(i) <= l_m_queue(i)(22 to 26) = cmd_seq_rd_incr(0 to 4); + + l_q_rd_en(i) <= ldq_rd_seq_match_l2(i) and ld_entry_val_l2(i) and not l_m_q_hit_st_l2(i) and not ex7_ld_par_err and not blk_ld_for_pe_recov_l2; + rd_seq_hit(i) <= ldq_rd_seq_match_l2(i) and ld_entry_val_l2(i); +end generate; + +cmp_l_q_rd_en <= l_q_rd_en; + +cmd_seq_rd_incr_val <= load_sent or selected_entry_flushed or rd_seq_num_skip; + +with cmd_seq_rd_incr_val select + ldq_rd_seq_match_d <= ldq_rd_seq_match_next when '1', + ldq_rd_seq_match_curr when others; + +latch_ldq_rd_seq_match : tri_rlmreg_p + generic map (width => ldq_rd_seq_match_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ldq_rd_seq_match_offset to ldq_rd_seq_match_offset + ldq_rd_seq_match_l2'length-1), + scout => sov(ldq_rd_seq_match_offset to ldq_rd_seq_match_offset + ldq_rd_seq_match_l2'length-1), + din => ldq_rd_seq_match_d(0 to lmq_entries-1), + dout => ldq_rd_seq_match_l2(0 to lmq_entries-1)); + +selected_ld_val_p: process (l_q_rd_en, rd_seq_hit) + variable b,c : std_ulogic; +begin + b := '0'; + c := '0'; + for i in 0 to lmq_entries-1 loop + b := l_q_rd_en(i) or b; + c := rd_seq_hit(i) or c; + end loop; + selected_ld_entry_val <= b; + rd_seq_num_exits <= c; +end process; + +rd_seq_num_skip <= any_ld_entry_val and not rd_seq_num_exits; + + + +q4_lmentry: if lmq_entries=4 generate begin + l_miss_entry <= gate_and(l_q_rd_en(0), l_m_queue(0)) or + gate_and(l_q_rd_en(1), l_m_queue(1)) or + gate_and(l_q_rd_en(2), l_m_queue(2)) or + gate_and(l_q_rd_en(3), l_m_queue(3)); + l_miss_addrlo <= gate_and(l_q_rd_en(0), l_m_queue_addrlo(0)(58 to 63)) or + gate_and(l_q_rd_en(1), l_m_queue_addrlo(1)(58 to 63)) or + gate_and(l_q_rd_en(2), l_m_queue_addrlo(2)(58 to 63)) or + gate_and(l_q_rd_en(3), l_m_queue_addrlo(3)(58 to 63)); + + lq_rd_en_is_ex5 <= (rd_seq_hit(0) and ex5_loadmiss_qentry(0)) or + (rd_seq_hit(1) and ex5_loadmiss_qentry(1)) or + (rd_seq_hit(2) and ex5_loadmiss_qentry(2)) or + (rd_seq_hit(3) and ex5_loadmiss_qentry(3)); + lq_rd_en_is_ex6 <= (rd_seq_hit(0) and ex6_loadmiss_qentry(0)) or + (rd_seq_hit(1) and ex6_loadmiss_qentry(1)) or + (rd_seq_hit(2) and ex6_loadmiss_qentry(2)) or + (rd_seq_hit(3) and ex6_loadmiss_qentry(3)); +end generate; + +q8_lmentry: if lmq_entries=8 generate begin + l_miss_entry <= gate_and(l_q_rd_en(0), l_m_queue(0)) or + gate_and(l_q_rd_en(1), l_m_queue(1)) or + gate_and(l_q_rd_en(2), l_m_queue(2)) or + gate_and(l_q_rd_en(3), l_m_queue(3)) or + gate_and(l_q_rd_en(4), l_m_queue(4)) or + gate_and(l_q_rd_en(5), l_m_queue(5)) or + gate_and(l_q_rd_en(6), l_m_queue(6)) or + gate_and(l_q_rd_en(7), l_m_queue(7)); + l_miss_addrlo <= gate_and(l_q_rd_en(0), l_m_queue_addrlo(0)(58 to 63)) or + gate_and(l_q_rd_en(1), l_m_queue_addrlo(1)(58 to 63)) or + gate_and(l_q_rd_en(2), l_m_queue_addrlo(2)(58 to 63)) or + gate_and(l_q_rd_en(3), l_m_queue_addrlo(3)(58 to 63)) or + gate_and(l_q_rd_en(4), l_m_queue_addrlo(4)(58 to 63)) or + gate_and(l_q_rd_en(5), l_m_queue_addrlo(5)(58 to 63)) or + gate_and(l_q_rd_en(6), l_m_queue_addrlo(6)(58 to 63)) or + gate_and(l_q_rd_en(7), l_m_queue_addrlo(7)(58 to 63)); + + lq_rd_en_is_ex5 <= (rd_seq_hit(0) and ex5_loadmiss_qentry(0)) or + (rd_seq_hit(1) and ex5_loadmiss_qentry(1)) or + (rd_seq_hit(2) and ex5_loadmiss_qentry(2)) or + (rd_seq_hit(3) and ex5_loadmiss_qentry(3)) or + (rd_seq_hit(4) and ex5_loadmiss_qentry(4)) or + (rd_seq_hit(5) and ex5_loadmiss_qentry(5)) or + (rd_seq_hit(6) and ex5_loadmiss_qentry(6)) or + (rd_seq_hit(7) and ex5_loadmiss_qentry(7)); + lq_rd_en_is_ex6 <= (rd_seq_hit(0) and ex6_loadmiss_qentry(0)) or + (rd_seq_hit(1) and ex6_loadmiss_qentry(1)) or + (rd_seq_hit(2) and ex6_loadmiss_qentry(2)) or + (rd_seq_hit(3) and ex6_loadmiss_qentry(3)) or + (rd_seq_hit(4) and ex6_loadmiss_qentry(4)) or + (rd_seq_hit(5) and ex6_loadmiss_qentry(5)) or + (rd_seq_hit(6) and ex6_loadmiss_qentry(6)) or + (rd_seq_hit(7) and ex6_loadmiss_qentry(7)); +end generate; + + + + + + + + + +iu_f_entry(0 to 5) <= "000000"; +iu_f_entry(6 to 37) <= x"00000000"; +iu_f_entry(38 to 41) <= iu_f_q0_sel & iu_f_q1_sel & iu_f_q2_sel & iu_f_q3_sel; +iu_f_entry(42 to 46) <= iu_f_sel_entry(0 to 4); +iu_f_entry(47 to 49) <= "110"; + + +iu_f_entry(50 to 53) <= iu_f_sel_entry(5 to 8); +iu_f_entry(54 to (54+real_data_add-1)) <= iu_f_sel_entry(9 to (9+REAL_IFAR_length-1)) & "0000"; + +iu_thrd(0) <= iu_f_q2_sel or iu_f_q3_sel; +iu_thrd(1) <= iu_f_q1_sel or iu_f_q3_sel; + +ldmq_entry(0 to 5) <= l_miss_entry(1 to 6); +ldmq_entry(6 to 37) <= x"00000000"; +ldmq_entry(38 to 41) <= l_miss_entry(18 to 21); +ldmq_entry(42 to 45) <= l_miss_entry(39 to 42); +ldmq_entry(46) <= l_miss_entry(53); +ldmq_entry(47 to 49) <= "001" when l_miss_entry(12) = '1' else + "010" when l_miss_entry(11) = '1' else + "100" when l_miss_entry(10) = '1' else + "101" when l_miss_entry(9) = '1' else + "110" when l_miss_entry(8) = '1' else + "111" when l_miss_entry(7) = '1' else + "000"; +ldmq_entry(50 to 53) <= l_miss_entry(43 to 46); +ldmq_entry(54 to (54+real_data_add-1)) <= cmp_l_miss_entry_addr & l_miss_addrlo; + +with mmu_q_entry_l2(0 to 1) select + mmuq_req(0 to 5) <= "111100" when "00", + "111011" when "01", + "000010" when "10", + "000010" when others; + +mmuq_req(6 to 37) <= x"00000000"; +mmuq_req(38 to 41) <= mmu_q_entry_l2(2 to 5); +mmuq_req(42 to 45) <= mmu_q_entry_l2(6 to 9); +mmuq_req(46) <= mmu_q_entry_l2(10); +mmuq_req(47 to 49) <= "000"; +mmuq_req(50 to 53) <= mmu_q_entry_l2(11 to 14); +mmuq_req(54 to (54+real_data_add-1)) <= mmu_q_entry_l2(26 to (26+real_data_add-1)); + + +iu_mmu_entry <= gate_and(send_if_req_l2, iu_f_entry) or + gate_and(send_mm_req_l2, mmuq_req); + +ld_tag(1 to 4) <= gate_and(send_if_req_l2, "10" & iu_thrd) or + gate_and(send_ld_req_l2, '0' & l_m_tag) or + gate_and(send_mm_req_l2, "110" & mmu_q_entry_l2(1) ); + + +store_entry(0 to 5) <= s_m_queue0(0 to 5); +store_entry(6 to 37) <= s_m_queue0(6 to 37); +store_entry(38 to 41) <= s_m_queue0(38 to 41); +store_entry(42 to 45) <= s_m_queue0(43 to 46); +store_entry(46) <= s_m_queue0(42); +store_entry(47 to 49) <= "001" when s_m_queue0(56) = '1' else + "010" when s_m_queue0(55) = '1' else + "100" when s_m_queue0(54) = '1' else + "101" when s_m_queue0(53) = '1' else + "110" when s_m_queue0(52) = '1' else + "111" when s_m_queue0(51) = '1' else + "000"; +store_entry(50 to 53) <= s_m_queue0(47 to 50); +store_entry(54 to (54+real_data_add-1)) <= s_m_queue0(58 to (58+real_data_add-1)); + + +latch_ob_pwr_tok : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_pwr_tok_offset to ob_pwr_tok_offset), + scout => sov(ob_pwr_tok_offset to ob_pwr_tok_offset), + din(0) => bx_lsu_ob_pwr_tok, + dout(0) => ob_pwr_tok_l2 ); + +ob_act <= ob_pwr_tok_l2 or ob_req_val_l2 or ob_ditc_val_l2 or clkg_ctl_override_q; + +ob_req_val_mux <= ob_req_val_l2 when bx_cmd_stall_d='1' else + bx_lsu_ob_req_val and not bx_stall_dly_or; +latch_ob_req_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_req_val_offset to ob_req_val_offset), + scout => sov(ob_req_val_offset to ob_req_val_offset), + din(0) => ob_req_val_mux, + dout(0) => ob_req_val_l2 ); +latch_ob_req_val_clone : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_req_val_clone_offset to ob_req_val_clone_offset), + scout => sov(ob_req_val_clone_offset to ob_req_val_clone_offset), + din(0) => ob_req_val_mux, + dout(0) => ob_req_val_clone_l2 ); + +ob_ditc_val_mux <= ob_ditc_val_l2 when bx_cmd_stall_d='1' else + bx_lsu_ob_ditc_val and not bx_stall_dly_or; +latch_ob_ditc_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_ditc_val_offset to ob_ditc_val_offset), + scout => sov(ob_ditc_val_offset to ob_ditc_val_offset), + din(0) => ob_ditc_val_mux, + dout(0) => ob_ditc_val_l2 ); +latch_ob_ditc_val_clone : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_ditc_val_clone_offset to ob_ditc_val_clone_offset), + scout => sov(ob_ditc_val_clone_offset to ob_ditc_val_clone_offset), + din(0) => ob_ditc_val_mux, + dout(0) => ob_ditc_val_clone_l2 ); + +lsu_bx_cmd_avail <= not (ob_req_val_l2 or ob_ditc_val_l2); + +ob_thrd_mux <= ob_thrd_l2 when bx_cmd_stall_d='1' else + bx_lsu_ob_thrd; +latch_ob_thrd : tri_rlmreg_p + generic map (width => ob_thrd_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_thrd_offset to ob_thrd_offset + ob_thrd_l2'length-1), + scout => sov(ob_thrd_offset to ob_thrd_offset + ob_thrd_l2'length-1), + din => ob_thrd_mux, + dout => ob_thrd_l2 ); + +ob_qw_mux <= ob_qw_l2 when bx_cmd_stall_d='1' else + bx_lsu_ob_qw; +latch_ob_qw : tri_rlmreg_p + generic map (width => ob_qw_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_qw_offset to ob_qw_offset + ob_qw_l2'length-1), + scout => sov(ob_qw_offset to ob_qw_offset + ob_qw_l2'length-1), + din => ob_qw_mux, + dout => ob_qw_l2 ); + +ob_dest_mux <= ob_dest_l2 when bx_cmd_stall_d='1' else + bx_lsu_ob_dest; +latch_ob_dest : tri_rlmreg_p + generic map (width => ob_dest_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_dest_offset to ob_dest_offset + ob_dest_l2'length-1), + scout => sov(ob_dest_offset to ob_dest_offset + ob_dest_l2'length-1), + din => ob_dest_mux, + dout => ob_dest_l2 ); + +ob_addr_mux <= ob_addr_l2 when bx_cmd_stall_d='1' else + bx_lsu_ob_addr; +latch_ob_addr : tri_rlmreg_p + generic map (width => ob_addr_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_addr_offset to ob_addr_offset + ob_addr_l2'length-1), + scout => sov(ob_addr_offset to ob_addr_offset + ob_addr_l2'length-1), + din => ob_addr_mux, + dout => ob_addr_l2 ); + +ob_data_mux <= ob_data_l2 when bx_cmd_stall_d='1' else + bx_lsu_ob_data; +latch_ob_data : tri_rlmreg_p + generic map (width => ob_data_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_data_offset to ob_data_offset + ob_data_l2'length-1), + scout => sov(ob_data_offset to ob_data_offset + ob_data_l2'length-1), + din => ob_data_mux, + dout => ob_data_l2 ); + +ob_store(0 to 5) <= "100000" when ob_req_val_l2='1' else + "100010"; + +ob_store(6 to 37) <= x"00000000" when ob_ditc_val_l2='1' else + x"FFFF0000" when ob_qw_l2(59)='0' else + x"0000FFFF"; +ob_store(38) <= ob_thrd_l2(0 to 1)="00"; +ob_store(39) <= ob_thrd_l2(0 to 1)="01"; +ob_store(40) <= ob_thrd_l2(0 to 1)="10"; +ob_store(41) <= ob_thrd_l2(0 to 1)="11"; +ob_store(42 to 45) <= "1010"; +ob_store(46) <= '0'; +ob_store(47 to 49) <= "110"; +ob_store(50 to 53) <= "0000"; +ob_store(54 to (54+real_data_add-7)) <= ob_addr_l2; +ob_store((54+real_data_add-6) to (54+real_data_add-5)) <= ob_qw_l2(58 to 59); +ob_store((54+real_data_add-4) to (54+real_data_add-1)) <= "0000"; + + +st_req <= st_recycle_l2 when st_recycle_v_l2='1' else + store_entry when st_entry0_val_l2='1' else + ob_store; + +ld_st_request <= st_req when (ex5_sel_st_req or ((ob_req_val_l2 or ob_ditc_val_l2 or st_recycle_v_l2) and store_credit)) = '1' else + ldmq_entry when send_ld_req_l2 = '1' else + iu_mmu_entry; + + +cred_pop <= anaclat_st_pop or anaclat_st_gather or (my_xucr0_cred and anaclat_ld_pop) or blk_st_cred_pop; +ex4_sel_st_req <= ( ( (ex4_st_val_l2 and not ex4_flush_store) and + ( (store_credit and not one_st_cred ) or + (one_st_cred and not nxt_st_cred_tkn) or + (one_st_cred and nxt_st_cred_tkn and cred_pop) or + (not store_credit and not st_entry0_val_l2 and cred_pop) ) ) or + (st_entry0_val_l2 and not (ex5_flush_store and ex5_st_val_l2) and (store_credit or cred_pop)) ); + +latch_ex5_sel_st_req : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => stq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex5_sel_st_req_offset to ex5_sel_st_req_offset), + scout => sov(ex5_sel_st_req_offset to ex5_sel_st_req_offset), + din(0) => ex4_sel_st_req, + dout(0) => ex5_sel_st_req ); + + +store_sent <= (st_entry0_val_l2 and store_credit and not (ex5_flush_store and ex5_st_val_l2) and ex5_sel_st_req) or + ((ob_req_val_l2 or ob_ditc_val_l2) and store_credit and not st_entry0_val_l2 and not st_recycle_v_l2 and not (l2req_resend_l2 and ex7_ld_par_err)) or + (st_recycle_v_l2 and store_credit); + + +load_sent <= not ex5_sel_st_req and send_ld_req_l2 and load_credit and selected_ld_entry_val and + not (lq_rd_en_is_ex5 and ex5_flush_load_local) and + not (lq_rd_en_is_ex6 and ex6_flush_l2) and + not ((ob_req_val_l2 or ob_ditc_val_l2 or st_recycle_v_l2) and store_credit); + +load_flushed <= send_ld_req_l2 and selected_ld_entry_val and + ((lq_rd_en_is_ex5 and ex5_flush_load_local) or (lq_rd_en_is_ex6 and ex6_flush_l2)); + +selected_entry_flushed <= selected_ld_entry_val and + ((lq_rd_en_is_ex5 and ex5_flush_load_local) or (lq_rd_en_is_ex6 and ex6_flush_l2)); + +mmu_st_sent <= store_credit and not st_entry0_val_l2 and not ob_req_val_l2 and not ob_ditc_val_l2 and + send_mm_req_l2 and mmu_q_val and not mmu_q_entry_l2(0) and not (l2req_resend_l2 and ex7_ld_par_err) and + not ex5_sel_st_req and not st_recycle_v_l2; + + +mmu_ld_sent <= load_credit and not ex5_sel_st_req and send_mm_req_l2 and mmu_q_val and mmu_q_entry_l2(0) and + not (l2req_resend_l2 and ex7_ld_par_err) and + not ((ob_req_val_l2 or ob_ditc_val_l2 or st_recycle_v_l2) and store_credit); +mmu_sent <= mmu_st_sent or mmu_ld_sent or (l2req_resend_l2 and ex7_ld_par_err and mmu_sent_l2); + + +l2req_resend_d <= mmu_sent or bx_cmd_sent_d or iu_sent_val or + (load_sent and not lq_rd_en_is_ex5 and not (ex5_flush_load_all and lq_rd_en_is_ex5)) or + (l2req_resend_l2 and ex7_ld_par_err); +l2req_recycle_d <= store_sent and not (ob_req_val_l2 or ob_ditc_val_l2); + + + +bx_cmd_sent_d <= (ob_req_val_l2 or ob_ditc_val_l2) and store_credit and + not (st_entry0_val_l2 ) and not st_recycle_v_l2 and + not (l2req_resend_l2 and ex7_ld_par_err); + + +bx_cmd_stall_d <= (ob_req_val_l2 or ob_ditc_val_l2) and + (not store_credit or (st_entry0_val_l2 ) or st_recycle_v_l2 or + (l2req_resend_l2 and ex7_ld_par_err)); + +latch_bx_cmd_sent : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(bx_cmd_sent_offset to bx_cmd_sent_offset), + scout => sov(bx_cmd_sent_offset to bx_cmd_sent_offset), + din(0) => bx_cmd_sent_d, + dout(0) => bx_cmd_sent_l2 ); + +lsu_bx_cmd_sent <= bx_cmd_sent_l2; + +latch_bx_cmd_stall : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(bx_cmd_stall_offset to bx_cmd_stall_offset), + scout => sov(bx_cmd_stall_offset to bx_cmd_stall_offset), + din(0) => bx_cmd_stall_d, + dout(0) => bx_cmd_stall_l2 ); + +lsu_bx_cmd_stall <= bx_cmd_stall_l2; + +bx_stall_dly_d(0) <= bx_cmd_stall_l2; +bx_stall_dly_d(1) <= bx_stall_dly_l2(0); +bx_stall_dly_d(2) <= bx_stall_dly_l2(1); +bx_stall_dly_d(3) <= bx_stall_dly_l2(3); + +bx_stall_dly_or <= not(bx_stall_dly_l2(0 to 2)="000") or bx_cmd_stall_l2; + +latch_bx_stall_dly : tri_rlmreg_p + generic map (width => bx_stall_dly_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(bx_stall_dly_offset to bx_stall_dly_offset + bx_stall_dly_l2'length-1), + scout => sov(bx_stall_dly_offset to bx_stall_dly_offset + bx_stall_dly_l2'length-1), + din => bx_stall_dly_d(0 to 3), + dout => bx_stall_dly_l2(0 to 3) ); + +latch_xu_mm_lsu_token : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(xu_mm_lsu_token_offset to xu_mm_lsu_token_offset), + scout => sov(xu_mm_lsu_token_offset to xu_mm_lsu_token_offset), + din(0) => mmu_sent, + dout(0) => mmu_sent_l2 ); + +xu_mm_lsu_token <= mmu_sent_l2 and not ex7_ld_par_err; + + + +ex3_val_req <= (ex3_local_dcbf or ex3_l_s_q_val) and not ex3_stg_flush; + +latch_ex4_val_req : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_val_req_offset to ex4_val_req_offset), + scout => sov(ex4_val_req_offset to ex4_val_req_offset), + din(0) => ex3_val_req, + dout(0) => ex4_val_req ); +latch_ex4_thrd_id : tri_rlmreg_p + generic map (width => ex4_thrd_id'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ex4_st_entry_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_thrd_id_offset to ex4_thrd_id_offset + ex4_thrd_id'length-1), + scout => sov(ex4_thrd_id_offset to ex4_thrd_id_offset + ex4_thrd_id'length-1), + din => ex3_thrd_id(0 to 3), + dout => ex4_thrd_id(0 to 3) ); +latch_ex5_thrd_id : tri_rlmreg_p + generic map (width => ex5_thrd_id'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex5_thrd_id_offset to ex5_thrd_id_offset + ex5_thrd_id'length-1), + scout => sov(ex5_thrd_id_offset to ex5_thrd_id_offset + ex5_thrd_id'length-1), + din => ex4_thrd_id(0 to 3), + dout => ex5_thrd_id(0 to 3) ); + + + + +lmq_collision: for i in 0 to lmq_entries-1 generate begin + lmq_collision_t0_d(i) <= ( (ex5_lmq_cpy_l2(i) and ld_rel_val_l2(i) and not ex4_loadmiss_qentry(i) and xu_lsu_ex5_set_barr(0)) or + lmq_collision_t0_l2(i)) and not reset_ldq_hit_barr(i); + lmq_collision_t1_d(i) <= ( (ex5_lmq_cpy_l2(i) and ld_rel_val_l2(i) and not ex4_loadmiss_qentry(i) and xu_lsu_ex5_set_barr(1)) or + lmq_collision_t1_l2(i)) and not reset_ldq_hit_barr(i); + lmq_collision_t2_d(i) <= ( (ex5_lmq_cpy_l2(i) and ld_rel_val_l2(i) and not ex4_loadmiss_qentry(i) and xu_lsu_ex5_set_barr(2)) or + lmq_collision_t2_l2(i)) and not reset_ldq_hit_barr(i); + lmq_collision_t3_d(i) <= ( (ex5_lmq_cpy_l2(i) and ld_rel_val_l2(i) and not ex4_loadmiss_qentry(i) and xu_lsu_ex5_set_barr(3)) or + lmq_collision_t3_l2(i)) and not reset_ldq_hit_barr(i); +end generate; + + +lmq_barr_done_p: process (reset_ldq_hit_barr, lmq_collision_t0_l2, lmq_collision_t1_l2, lmq_collision_t2_l2, lmq_collision_t3_l2, ex5_lmq_cpy_l2, xu_lsu_ex5_set_barr, ld_rel_val_l2, ex4_loadmiss_qentry ) + variable b: std_ulogic_vector(0 to 3); +begin + b := "0000"; + for i in 0 to lmq_entries-1 loop + b(0) := (reset_ldq_hit_barr(i) and lmq_collision_t0_l2(i)) or + (ex5_lmq_cpy_l2(i) and xu_lsu_ex5_set_barr(0) and (not ld_rel_val_l2(i) or reset_ldq_hit_barr(i) or (ld_rel_val_l2(i) and ex4_loadmiss_qentry(i)))) or b(0); + b(1) := (reset_ldq_hit_barr(i) and lmq_collision_t1_l2(i)) or + (ex5_lmq_cpy_l2(i) and xu_lsu_ex5_set_barr(1) and (not ld_rel_val_l2(i) or reset_ldq_hit_barr(i) or (ld_rel_val_l2(i) and ex4_loadmiss_qentry(i)))) or b(1); + b(2) := (reset_ldq_hit_barr(i) and lmq_collision_t2_l2(i)) or + (ex5_lmq_cpy_l2(i) and xu_lsu_ex5_set_barr(2) and (not ld_rel_val_l2(i) or reset_ldq_hit_barr(i) or (ld_rel_val_l2(i) and ex4_loadmiss_qentry(i)))) or b(2); + b(3) := (reset_ldq_hit_barr(i) and lmq_collision_t3_l2(i)) or + (ex5_lmq_cpy_l2(i) and xu_lsu_ex5_set_barr(3) and (not ld_rel_val_l2(i) or reset_ldq_hit_barr(i) or (ld_rel_val_l2(i) and ex4_loadmiss_qentry(i)))) or b(3); + end loop; + lmq_barr_done_tid(0 to 3) <= b; +end process; + + +latch_lmq_collision_t0 : tri_rlmreg_p + generic map (width => lmq_collision_t0_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(lmq_collision_t0_offset to lmq_collision_t0_offset + lmq_collision_t0_l2'length-1), + scout => sov(lmq_collision_t0_offset to lmq_collision_t0_offset + lmq_collision_t0_l2'length-1), + din => lmq_collision_t0_d, + dout => lmq_collision_t0_l2 ); + +latch_lmq_collision_t1 : tri_rlmreg_p + generic map (width => lmq_collision_t1_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(lmq_collision_t1_offset to lmq_collision_t1_offset + lmq_collision_t1_l2'length-1), + scout => sov(lmq_collision_t1_offset to lmq_collision_t1_offset + lmq_collision_t1_l2'length-1), + din => lmq_collision_t1_d, + dout => lmq_collision_t1_l2 ); + +latch_lmq_collision_t2 : tri_rlmreg_p + generic map (width => lmq_collision_t2_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(lmq_collision_t2_offset to lmq_collision_t2_offset + lmq_collision_t2_l2'length-1), + scout => sov(lmq_collision_t2_offset to lmq_collision_t2_offset + lmq_collision_t2_l2'length-1), + din => lmq_collision_t2_d, + dout => lmq_collision_t2_l2 ); + +latch_lmq_collision_t3 : tri_rlmreg_p + generic map (width => lmq_collision_t3_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(lmq_collision_t3_offset to lmq_collision_t3_offset + lmq_collision_t3_l2'length-1), + scout => sov(lmq_collision_t3_offset to lmq_collision_t3_offset + lmq_collision_t3_l2'length-1), + din => lmq_collision_t3_d, + dout => lmq_collision_t3_l2 ); + +ldq_barr_active_d(0 to 3) <= (xu_lsu_ex5_set_barr(0 to 3) and not lmq_barr_done_tid(0 to 3)) or + (ldq_barr_active_l2(0 to 3) and not lmq_barr_done_tid(0 to 3)); + +latch_ldq_barr_active : tri_rlmreg_p + generic map (width => ldq_barr_active_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ldq_barr_active_offset to ldq_barr_active_offset + ldq_barr_active_l2'length-1), + scout => sov(ldq_barr_active_offset to ldq_barr_active_offset + ldq_barr_active_l2'length-1), + din => ldq_barr_active_d(0 to 3), + dout => ldq_barr_active_l2(0 to 3) ); + + +sync_done <= store_sent and ( ((s_m_queue0(0 to 5) = "110010") or (s_m_queue0(0 to 5) = "101010")) or + (not my_xucr0_tlbsync and ( s_m_queue0(0 to 5) = "111010"))) and + not (ex5_stg_flush and ex5_st_val_for_flush) and st_entry0_val_l2; + + + + +sync_done_tid <= gate_and(sync_done, s_m_queue0(38 to 41)); +ldq_barr_done <= lmq_barr_done_tid(0 to 3) and (ldq_barr_active_l2(0 to 3) or xu_lsu_ex5_set_barr(0 to 3)); + + +latch_ldq_barr_done : tri_rlmreg_p + generic map (width => ldq_barr_done'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ldq_barr_done_offset to ldq_barr_done_offset + ldq_barr_done'length-1), + scout => sov(ldq_barr_done_offset to ldq_barr_done_offset + ldq_barr_done'length-1), + din => ldq_barr_done(0 to 3), + dout => ldq_barr_done_l2(0 to 3) ); + +lsu_xu_ldq_barr_done <= ldq_barr_done_l2; + +latch_sync_done_tid : tri_rlmreg_p + generic map (width => sync_done_tid'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(sync_done_tid_offset to sync_done_tid_offset + sync_done_tid'length-1), + scout => sov(sync_done_tid_offset to sync_done_tid_offset + sync_done_tid'length-1), + din => sync_done_tid(0 to 3), + dout => sync_done_tid_l2(0 to 3) ); + +lsu_xu_sync_barr_done <= sync_done_tid_l2; + + +q4_tag: if lmq_entries=4 generate begin + l_m_tag(2) <= '0'; + l_m_tag(3) <= l_q_rd_en(2) or l_q_rd_en(3); + l_m_tag(4) <= l_q_rd_en(1) or l_q_rd_en(3); +end generate; + +q8_tag: if lmq_entries=8 generate begin + l_m_tag(2) <= l_q_rd_en(4) or l_q_rd_en(5) or l_q_rd_en(6) or l_q_rd_en(7); + l_m_tag(3) <= l_q_rd_en(2) or l_q_rd_en(3) or l_q_rd_en(6) or l_q_rd_en(7); + l_m_tag(4) <= l_q_rd_en(1) or l_q_rd_en(3) or l_q_rd_en(5) or l_q_rd_en(7); +end generate; + + + + + + + + + + + + +l2req_pwr_token <= iu_val or any_ld_entry_val or st_entry0_val_l2 or ex4_ld_m_val or ex4_st_val_l2 or + mmu_q_val_l2 or + ob_req_val_l2 or ob_ditc_val_l2 or ob_pwr_tok_l2 or l2req_resend_d or st_recycle_v_l2 or (l2req_recycle_l2 and ex7_ld_par_err); + + +ex5_st_val_for_flush <= ex5_st_val_l2; + +l2req <= (load_sent and not (lq_rd_en_is_ex5 and ex5_flush_load_all) ) or + (store_sent and not (ex5_stg_flush and ex5_st_val_for_flush)) or + iu_sent_val or mmu_sent when (l2req_resend_l2 and ex7_ld_par_err) = '0' else + '1'; + +l2req_gated <= l2req and not ex6_ld_par_err; + +l2req_st_data_ptoken <= (ex4_st_val_l2 and not ex4_flush_store and + ((ex4_st_entry_l2(0 to 5)="100000") or (ex4_st_entry_l2(0 to 4)="10011") or (ex4_st_entry_l2(0 to 5)="101001"))) or + (st_entry0_val_l2 and ((s_m_queue0(0 to 5)="100000") or (s_m_queue0(0 to 4)="10011") or (s_m_queue0(0 to 5)="101001"))) or + ob_req_val_l2 or ob_ditc_val_l2 or ob_pwr_tok_l2 or mmu_st_sent or bx_cmd_sent_d or + (mmu_q_val_l2 and (mmu_q_entry_l2(0 to 1)="00")) or st_recycle_v_l2 or + ((l2req_resend_l2 or l2req_recycle_l2) and ex7_ld_par_err); + +l2req_ld_core_tag(0) <= '0'; +l2req_ld_core_tag(1 to 4) <= ld_tag(1 to 4) when (l2req_resend_l2 and ex7_ld_par_err) = '0' else + l2req_ld_core_tag_l2(1 to 4); + +l2req_ra <= ld_st_request(54 to (54+real_data_add-1)) when (l2req_resend_l2 and ex7_ld_par_err) = '0' else + l2req_ra_l2; + +std_be_16: if st_data_32B_mode=0 generate begin + l2req_st_byte_enbl <= l2req_st_byte_enbl_l2 when (l2req_resend_l2 and ex7_ld_par_err) = '1' else + ld_st_request(6 to 21) when st_req(54+real_data_add-1-4) = '0' else + ld_st_request(22 to 37); + + st_recycle_entry(6 to 37) <= l2req_st_byte_enbl_l2(0 to 15) & l2req_st_byte_enbl_l2(0 to 15); + +end generate; + +copy_st_be_for_16B_mode <= st_req(54+real_data_add-1-4) and not my_xucr0_l2siw; + +std_be_32: if st_data_32B_mode=1 generate begin + l2req_st_byte_enbl(0 to 15) <= l2req_st_byte_enbl_l2(0 to 15) when (l2req_resend_l2 and ex7_ld_par_err) = '1' else + ld_st_request(6 to 21) when copy_st_be_for_16B_mode = '0' else + ld_st_request(22 to 37); + l2req_st_byte_enbl(16 to 31) <= l2req_st_byte_enbl_l2(16 to 31) when (l2req_resend_l2 and ex7_ld_par_err) = '1' else + ld_st_request(22 to 37); + + st_recycle_entry(6 to 37) <= l2req_st_byte_enbl_l2(0 to 31); +end generate; + +l2req_thread(0) <= ld_st_request(40) or ld_st_request(41) when (l2req_resend_l2 and ex7_ld_par_err) = '0' else + l2req_thread_l2(0); +l2req_thread(1) <= ld_st_request(39) or ld_st_request(41) when (l2req_resend_l2 and ex7_ld_par_err) = '0' else + l2req_thread_l2(1); + +l2req_thread(2) <= not st_entry0_val_l2 and (ob_req_val_l2 or ob_ditc_val_l2) and store_credit when (l2req_resend_l2 and ex7_ld_par_err) = '0' else + l2req_thread_l2(2); +l2req_ttype(0 to 5) <= ld_st_request(0 to 5) when (l2req_resend_l2 and ex7_ld_par_err) = '0' else + l2req_ttype_l2(0 to 5); +l2req_wimg <= ld_st_request(42 to 45) when (l2req_resend_l2 and ex7_ld_par_err) = '0' else + l2req_wimg_l2; +l2req_user <= ld_st_request(50 to 53) when (l2req_resend_l2 and ex7_ld_par_err) = '0' else + l2req_user_l2; +l2req_endian <= ld_st_request(46) when (l2req_resend_l2 and ex7_ld_par_err) = '0' else + l2req_endian_l2; +l2req_ld_xfr_len <= ld_st_request(47 to 49) when (l2req_resend_l2 and ex7_ld_par_err) = '0' else + l2req_ld_xfr_len_l2; + + + +latch_l2req_resend : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(l2req_resend_offset to l2req_resend_offset), + scout => sov(l2req_resend_offset to l2req_resend_offset), + din(0) => l2req_resend_d, + dout(0) => l2req_resend_l2); + +latch_l2req_recycle : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(l2req_recycle_offset to l2req_recycle_offset), + scout => sov(l2req_recycle_offset to l2req_recycle_offset), + din(0) => l2req_recycle_d, + dout(0) => l2req_recycle_l2); + +latch_l2req_pwr_token : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(l2req_pwr_token_offset to l2req_pwr_token_offset), + scout => sov(l2req_pwr_token_offset to l2req_pwr_token_offset), + din(0) => l2req_pwr_token, + dout(0) => l2req_pwr_token_l2 ); + +ac_an_req_pwr_token <= l2req_pwr_token_l2; + +latch_l2req_st_data_ptoken : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(l2req_st_data_ptoken_offset to l2req_st_data_ptoken_offset), + scout => sov(l2req_st_data_ptoken_offset to l2req_st_data_ptoken_offset), + din(0) => l2req_st_data_ptoken, + dout(0) => l2req_st_data_ptoken_l2 ); + +ac_an_st_data_pwr_token <= l2req_st_data_ptoken_l2; + +latch_l2req : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(l2req_offset to l2req_offset), + scout => sov(l2req_offset to l2req_offset), + din(0) => l2req_gated, + dout(0) => l2req_l2 ); +ac_an_req <= l2req_l2; + +l2req_act <= l2req_pwr_token_l2 or clkg_ctl_override_q; + +latch_l2req_ld_core_tag : tri_rlmreg_p + generic map (width => l2req_ld_core_tag'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => l2req_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(l2req_ld_core_tag_offset to l2req_ld_core_tag_offset + l2req_ld_core_tag'length-1), + scout => sov(l2req_ld_core_tag_offset to l2req_ld_core_tag_offset + l2req_ld_core_tag'length-1), + din => l2req_ld_core_tag, + dout => l2req_ld_core_tag_l2 ); +ac_an_req_ld_core_tag <= l2req_ld_core_tag_l2; + +latch_l2req_ra : tri_rlmreg_p + generic map (width => l2req_ra'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => l2req_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(l2req_ra_offset to l2req_ra_offset + l2req_ra'length-1), + scout => sov(l2req_ra_offset to l2req_ra_offset + l2req_ra'length-1), + din => l2req_ra, + dout => l2req_ra_l2 ); +ac_an_req_ra <= l2req_ra_l2; + +latch_l2req_st_byte_enbl : tri_rlmreg_p + generic map (width => l2req_st_byte_enbl'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => l2req_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(l2req_st_byte_enbl_offset to l2req_st_byte_enbl_offset + l2req_st_byte_enbl'length-1), + scout => sov(l2req_st_byte_enbl_offset to l2req_st_byte_enbl_offset + l2req_st_byte_enbl'length-1), + din => l2req_st_byte_enbl, + dout => l2req_st_byte_enbl_l2 ); +ac_an_st_byte_enbl <= l2req_st_byte_enbl_l2; + +latch_l2req_thread : tri_rlmreg_p + generic map (width => l2req_thread'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => l2req_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(l2req_thread_offset to l2req_thread_offset + l2req_thread'length-1), + scout => sov(l2req_thread_offset to l2req_thread_offset + l2req_thread'length-1), + din => l2req_thread(0 to 2), + dout => l2req_thread_l2(0 to 2) ); +ac_an_req_thread(0 to 2) <= l2req_thread_l2(0 to 2); + +latch_l2req_ttype : tri_rlmreg_p + generic map (width => l2req_ttype'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => l2req_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(l2req_ttype_offset to l2req_ttype_offset + l2req_ttype'length-1), + scout => sov(l2req_ttype_offset to l2req_ttype_offset + l2req_ttype'length-1), + din => l2req_ttype(0 to 5), + dout => l2req_ttype_l2(0 to 5) ); +ac_an_req_ttype <= l2req_ttype_l2; + +latch_l2req_wimg : tri_rlmreg_p + generic map (width => l2req_wimg'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => l2req_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(l2req_wimg_offset to l2req_wimg_offset + l2req_wimg'length-1), + scout => sov(l2req_wimg_offset to l2req_wimg_offset + l2req_wimg'length-1), + din => l2req_wimg(0 to 3), + dout => l2req_wimg_l2(0 to 3) ); +ac_an_req_wimg_w <= l2req_wimg_l2(0); +ac_an_req_wimg_i <= l2req_wimg_l2(1); +ac_an_req_wimg_m <= l2req_wimg_l2(2); +ac_an_req_wimg_g <= l2req_wimg_l2(3); + + +latch_l2req_endian : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => l2req_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(l2req_endian_offset to l2req_endian_offset), + scout => sov(l2req_endian_offset to l2req_endian_offset), + din(0) => l2req_endian, + dout(0) => l2req_endian_l2 ); +ac_an_req_endian <= l2req_endian_l2; + + +latch_l2req_user : tri_rlmreg_p + generic map (width => l2req_user'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => l2req_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(l2req_user_offset to l2req_user_offset + l2req_user'length-1), + scout => sov(l2req_user_offset to l2req_user_offset + l2req_user'length-1), + din => l2req_user(0 to 3), + dout => l2req_user_l2(0 to 3) ); +ac_an_req_user_defined <= l2req_user_l2; + +latch_l2req_ld_xfr_len : tri_rlmreg_p + generic map (width => l2req_ld_xfr_len'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => l2req_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(l2req_ld_xfr_len_offset to l2req_ld_xfr_len_offset + l2req_ld_xfr_len'length-1), + scout => sov(l2req_ld_xfr_len_offset to l2req_ld_xfr_len_offset + l2req_ld_xfr_len'length-1), + din => l2req_ld_xfr_len(0 to 2), + dout => l2req_ld_xfr_len_l2 ); +ac_an_req_ld_xfr_len <= l2req_ld_xfr_len_l2; + +latch_spare_ctrl_a0 : tri_rlmreg_p + generic map (width => ac_an_req_spare_ctrl_a0'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '0', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(spare_ctrl_a0_offset to spare_ctrl_a0_offset + ac_an_req_spare_ctrl_a0'length-1), + scout => sov(spare_ctrl_a0_offset to spare_ctrl_a0_offset + ac_an_req_spare_ctrl_a0'length-1), + din => "0000", + dout => ac_an_req_spare_ctrl_a0 ); + +latch_spare_ctrl_a1 : tri_rlmreg_p + generic map (width => an_ac_req_spare_ctrl_a1'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '0', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(spare_ctrl_a1_offset to spare_ctrl_a1_offset + an_ac_req_spare_ctrl_a1'length-1), + scout => sov(spare_ctrl_a1_offset to spare_ctrl_a1_offset + an_ac_req_spare_ctrl_a1'length-1), + din => an_ac_req_spare_ctrl_a1, + dout => unused(0 to 3) ); + + + +st_recycle_entry(0 to 5) <= l2req_ttype_l2; + + +st_recycle_entry(38) <= l2req_thread_l2(0 to 1) = "00"; +st_recycle_entry(39) <= l2req_thread_l2(0 to 1) = "01"; +st_recycle_entry(40) <= l2req_thread_l2(0 to 1) = "10"; +st_recycle_entry(41) <= l2req_thread_l2(0 to 1) = "11"; +st_recycle_entry(42 to 45) <= l2req_wimg_l2; +st_recycle_entry(46) <= l2req_endian_l2; +st_recycle_entry(47 to 49) <= l2req_ld_xfr_len_l2; +st_recycle_entry(50 to 53) <= l2req_user_l2; +st_recycle_entry(54 to (54+real_data_add-1)) <= l2req_ra_l2; + +st_recycle_d <= st_recycle_entry when st_recycle_v_l2='0' else + st_recycle_l2; + +st_recycle_act <= l2req_l2 or st_recycle_v_l2 or ex7_ld_par_err or clkg_ctl_override_q; + +latch_st_recycle : tri_rlmreg_p + generic map (width => st_recycle_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => st_recycle_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(st_recycle_offset to st_recycle_offset + st_recycle_l2'length-1), + scout => sov(st_recycle_offset to st_recycle_offset + st_recycle_l2'length-1), + din => st_recycle_d, + dout => st_recycle_l2 ); + +st_recycle_v_d <= (l2req_recycle_l2 and ex7_ld_par_err and not (ex6_flush_l2 and ex6_st_val_l2)) or + (st_recycle_v_l2 and not store_sent); + +latch_st_recycle_v : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => st_recycle_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(st_recycle_v_offset to st_recycle_v_offset), + scout => sov(st_recycle_v_offset to st_recycle_v_offset), + din(0) => st_recycle_v_d, + dout(0) => st_recycle_v_l2 ); + + +ex5_load <= load_sent and lq_rd_en_is_ex5; + +latch_ex6_load_sent : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex6_load_sent_offset to ex6_load_sent_offset), + scout => sov(ex6_load_sent_offset to ex6_load_sent_offset), + din(0) => ex5_load, + dout(0) => ex6_load_sent_l2 ); + +latch_load_sent_dbglat : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(load_sent_dbglat_offset to load_sent_dbglat_offset), + scout => sov(load_sent_dbglat_offset to load_sent_dbglat_offset), + din(0) => load_sent, + dout(0) => load_sent_dbglat_l2 ); + +ex5_store_sent <= store_sent and ex5_st_val_for_flush; + +latch_ex6_store_sent : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => stq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex6_store_sent_offset to ex6_store_sent_offset), + scout => sov(ex6_store_sent_offset to ex6_store_sent_offset), + din(0) => ex5_store_sent, + dout(0) => ex6_store_sent_l2 ); + + +ex5_flush_d <= ex4_stg_flush; + +latch_ex5_flush : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex5_flush_offset to ex5_flush_offset), + scout => sov(ex5_flush_offset to ex5_flush_offset), + din(0) => ex5_flush_d, + dout(0) => ex5_flush_l2 ); + + +ex5_stg_flush <= ((xu_lsu_ex5_flush(0) and ex5_thrd_id(0)) or + (xu_lsu_ex5_flush(1) and ex5_thrd_id(1)) or + (xu_lsu_ex5_flush(2) and ex5_thrd_id(2)) or + (xu_lsu_ex5_flush(3) and ex5_thrd_id(3))) and + not pe_recov_state_l2; + +my_ex5_flush <= ex5_stg_flush or ex5_flush_l2; + +ex5_flush_store <= ex5_flush_l2; +my_ex5_flush_store <= (ex5_stg_flush or ex5_flush_l2); + +latch_ex6_flush : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex6_flush_offset to ex6_flush_offset), + scout => sov(ex6_flush_offset to ex6_flush_offset), + din(0) => ex5_stg_flush, + dout(0) => ex6_flush_l2 ); + + + +latch_msr_gs : tri_rlmreg_p + generic map (width => msr_gs_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ex4_st_entry_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(msr_gs_offset to msr_gs_offset + msr_gs_l2'length-1), + scout => sov(msr_gs_offset to msr_gs_offset + msr_gs_l2'length-1), + din => xu_lsu_msr_gs(0 to 3), + dout => msr_gs_l2 ); + +latch_msr_pr : tri_rlmreg_p + generic map (width => msr_pr_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ex4_st_entry_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(msr_pr_offset to msr_pr_offset + msr_pr_l2'length-1), + scout => sov(msr_pr_offset to msr_pr_offset + msr_pr_l2'length-1), + din => xu_lsu_msr_pr(0 to 3), + dout => msr_pr_l2 ); + +latch_msr_ds : tri_rlmreg_p + generic map (width => msr_ds_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ex4_st_entry_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(msr_ds_offset to msr_ds_offset + msr_ds_l2'length-1), + scout => sov(msr_ds_offset to msr_ds_offset + msr_ds_l2'length-1), + din => xu_lsu_msr_ds(0 to 3), + dout => msr_ds_l2 ); + +latch_pid0 : tri_rlmreg_p + generic map (width => pid0_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ex4_st_entry_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(pid0_offset to pid0_offset + pid0_l2'length-1), + scout => sov(pid0_offset to pid0_offset + pid0_l2'length-1), + din => mm_xu_derat_pid0(0 to 13), + dout => pid0_l2 ); + +latch_pid1 : tri_rlmreg_p + generic map (width => pid1_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ex4_st_entry_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(pid1_offset to pid1_offset + pid1_l2'length-1), + scout => sov(pid1_offset to pid1_offset + pid1_l2'length-1), + din => mm_xu_derat_pid1(0 to 13), + dout => pid1_l2 ); + +latch_pid2 : tri_rlmreg_p + generic map (width => pid2_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ex4_st_entry_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(pid2_offset to pid2_offset + pid2_l2'length-1), + scout => sov(pid2_offset to pid2_offset + pid2_l2'length-1), + din => mm_xu_derat_pid2(0 to 13), + dout => pid2_l2 ); + +latch_pid3 : tri_rlmreg_p + generic map (width => pid3_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ex4_st_entry_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(pid3_offset to pid3_offset + pid3_l2'length-1), + scout => sov(pid3_offset to pid3_offset + pid3_l2'length-1), + din => mm_xu_derat_pid3(0 to 13), + dout => pid3_l2 ); + + +msr_hv <= or_reduce(not msr_gs_l2(0 to 3) and ex4_st_entry_l2(38 to 41)); +msr_pr <= or_reduce(msr_pr_l2(0 to 3) and ex4_st_entry_l2(38 to 41)); +msr_ds <= or_reduce(msr_ds_l2(0 to 3) and ex4_st_entry_l2(38 to 41)); +pid(0 to 13) <= gate_and(ex4_st_entry_l2(38) , pid0_l2(0 to 13)) or + gate_and(ex4_st_entry_l2(39) , pid1_l2(0 to 13)) or + gate_and(ex4_st_entry_l2(40) , pid2_l2(0 to 13)) or + gate_and(ex4_st_entry_l2(41) , pid3_l2(0 to 13)); + + +ditc_dat <= "00000000" & + "00" & + "000001" & + ob_dest_l2(0 to 14) & '0' & + "00000000" & + "0000000000000000" & + x"000000000000000000"; + +epsc_epr <= (xu_derat_epsc0_epr and ex4_st_entry_l2(38)) or + (xu_derat_epsc1_epr and ex4_st_entry_l2(39)) or + (xu_derat_epsc2_epr and ex4_st_entry_l2(40)) or + (xu_derat_epsc3_epr and ex4_st_entry_l2(41)); + +epsc_eas <= (xu_derat_epsc0_eas and ex4_st_entry_l2(38)) or + (xu_derat_epsc1_eas and ex4_st_entry_l2(39)) or + (xu_derat_epsc2_eas and ex4_st_entry_l2(40)) or + (xu_derat_epsc3_eas and ex4_st_entry_l2(41)); + +epsc_egs <= (xu_derat_epsc0_egs and ex4_st_entry_l2(38)) or + (xu_derat_epsc1_egs and ex4_st_entry_l2(39)) or + (xu_derat_epsc2_egs and ex4_st_entry_l2(40)) or + (xu_derat_epsc3_egs and ex4_st_entry_l2(41)); + +epsc_elpid <= (gate_and(ex4_st_entry_l2(38), xu_derat_epsc0_elpid)) or + (gate_and(ex4_st_entry_l2(39), xu_derat_epsc1_elpid)) or + (gate_and(ex4_st_entry_l2(40), xu_derat_epsc2_elpid)) or + (gate_and(ex4_st_entry_l2(41), xu_derat_epsc3_elpid)); + +epsc_epid <= (gate_and(ex4_st_entry_l2(38), xu_derat_epsc0_epid)) or + (gate_and(ex4_st_entry_l2(39), xu_derat_epsc1_epid)) or + (gate_and(ex4_st_entry_l2(40), xu_derat_epsc2_epid)) or + (gate_and(ex4_st_entry_l2(41), xu_derat_epsc3_epid)); + +ex4_icswx_extra_data(0 to 2) <= not epsc_egs & epsc_epr & epsc_eas when ex4_st_entry_l2(57)='1' else + msr_hv & msr_pr & msr_ds; + +ex4_icswx_extra_data(3 to 24) <= epsc_elpid & epsc_epid when ex4_st_entry_l2(57)='1' else + lpidr_l2(0 to 7) & pid(0 to 13); + +stq_icswx_extra_data_d <= stq_icswx_extra_data_l2 when (st_entry0_val_l2 and not (store_credit and ex5_sel_st_req))='1' else + ex4_icswx_extra_data; + +latch_stq_icswx_extra_data : tri_rlmreg_p + generic map (width => stq_icswx_extra_data_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => stq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(stq_icswx_extra_data_offset to stq_icswx_extra_data_offset + stq_icswx_extra_data_l2'length-1), + scout => sov(stq_icswx_extra_data_offset to stq_icswx_extra_data_offset + stq_icswx_extra_data_l2'length-1), + din => stq_icswx_extra_data_d, + dout => stq_icswx_extra_data_l2 ); + +icswx_dat(0 to 31) <= stq_icswx_extra_data_l2(0 to 2) & "0000000" & ex5_st_data_l2(10 to 31); + +icswx_dat(32 to 55) <= stq_icswx_extra_data_l2(3 to 10) & "00" & stq_icswx_extra_data_l2(11 to 24); + +icswx_dat(56 to 127) <= ex5_st_data_l2(56 to 127); + +latch_ex4_p_addr_59 : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ex3_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_p_addr_59_offset to ex4_p_addr_59_offset), + scout => sov(ex4_p_addr_59_offset to ex4_p_addr_59_offset), + din(0) => ex3_p_addr(59), + dout(0) => ex4_p_addr_59 ); + +std16B: if st_data_32B_mode=0 generate begin + + ex4_st_data_mux(0 to 127) <= + ex4_256st_data(0 to 127) when ex4_p_addr_59 = '0' else + ex4_256st_data(128 to 255); +end generate; + +copy_st_data_for_16B_mode <= ex4_p_addr_59 and not my_xucr0_l2siw; + +std32B: if st_data_32B_mode=1 generate begin + ex4_st_data_mux(0 to 127) <= ex4_256st_data(0 to 127) when copy_st_data_for_16B_mode = '0' else + ex4_256st_data(128 to 255); + ex4_st_data_mux(128 to 255) <= ex4_256st_data(128 to 255); + + ex5_st_data_mux(128 to 255) <= ex6_st_data_l2(128 to 255) when (((l2req_resend_l2 or l2req_recycle_l2) and ex7_ld_par_err) or + st_recycle_v_l2) = '1' else + ex5_st_data_l2(128 to 255) when st_entry0_val_clone_l2='1' else + ob_data_l2(0 to 127); + +end generate; + + + +ex4_st_data_mux2 <= ex5_st_data_l2 when ((l2req_recycle_l2 and ex7_ld_par_err) or st_recycle_v_l2) = '1' else + ex4_st_data_mux when (st_entry0_val_l2 and not (store_credit and ex5_sel_st_req))='0' else + ex5_st_data_l2; + +latch_ex5_st_data : tri_rlmreg_p + generic map (width => ex5_st_data_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => stq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex5_st_data_offset to ex5_st_data_offset + ex5_st_data_l2'length-1), + scout => sov(ex5_st_data_offset to ex5_st_data_offset + ex5_st_data_l2'length-1), + din => ex4_st_data_mux2, + dout => ex5_st_data_l2 ); + + +ex5_st_data_mux1(0 to 127) <= icswx_dat(0 to 127) when s_m_queue0(0 to 4)="10011" else + ex5_st_data_l2(0 to 127); + +ex5_st_data_mux2(0 to 127) <= ob_data_l2(0 to 127) when ob_req_val_clone_l2='1' else + ditc_dat(0 to 127) when ob_ditc_val_clone_l2='1' else + ex5_st_data_l2(0 to 31) & + mmu_q_entry_l2(15 to 22) & + "00000" & + mmu_q_entry_l2(23 to 25) & + ex5_st_data_l2(48 to 127); + +ex5_st_data_mux(0 to 127) <= ex6_st_data_l2(0 to 127) when (((l2req_resend_l2 or l2req_recycle_l2) and ex7_ld_par_err) or + st_recycle_v_l2) = '1' else + ex5_st_data_mux1 when st_entry0_val_clone_l2='1' else + ex5_st_data_mux2; + +st_data_act <= l2req_st_data_ptoken_l2 or clkg_ctl_override_q; + +latch_ex6_st_data : tri_rlmreg_p + generic map (width => ac_an_st_data'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => st_data_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex6_st_data_offset to ex6_st_data_offset + ac_an_st_data'length-1), + scout => sov(ex6_st_data_offset to ex6_st_data_offset + ac_an_st_data'length-1), + din => ex5_st_data_mux, + dout => ex6_st_data_l2 ); +ac_an_st_data <= ex6_st_data_l2; + +ex3_stq_flush <= flush_if_store or sync_flush; +ex3_ig_flush <= I1_G1_flush; +ex4_l2cmdq_flush_d <= I1_G1_flush & flush_if_store & sync_flush & ld_queue_full & ld_q_seq_wrap; +latch_ex4_l2cmdq_flush : tri_rlmreg_p + generic map (width => ex4_l2cmdq_flush_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_l2cmdq_flush_offset to ex4_l2cmdq_flush_offset + ex4_l2cmdq_flush_l2'length-1), + scout => sov(ex4_l2cmdq_flush_offset to ex4_l2cmdq_flush_offset + ex4_l2cmdq_flush_l2'length-1), + din => ex4_l2cmdq_flush_d, + dout => ex4_l2cmdq_flush_l2 ); + + +ldq_rel_op_size(0 to 5) <= rel_size_l2(0 to 5); +ldq_rel_thrd_id(0 to 3) <= rel_th_id_l2(0 to 3); +ldq_rel_ci <= rel_cache_inh_l2; + + + + + + + +my_beat1_p: process (l_m_rel_hit_beat0_l2, l_m_rel_hit_beat1_l2, rel_tag_l2, rel_data_val) + variable b: std_ulogic; + variable c: std_ulogic; +begin + b := '0'; + c := '0'; + for i in 0 to lmq_entries-1 loop + b := (l_m_rel_hit_beat1_l2(i) and (rel_tag_l2(1 to 4) = tconv(i, 4)) ) or b; + c := (l_m_rel_hit_beat0_l2(i) and rel_data_val(i)) or c; + end loop; + my_beat1 <= b; + my_beat1_early <= c; +end process; + + + +my_beat_mid_p: process (l_m_rel_hit_beat3_l2, l_m_rel_hit_beat5_l2, rel_tag_l2, my_xucr0_cls) + variable b: std_ulogic; +begin + b := '0'; + for i in 0 to lmq_entries-1 loop + b := ((l_m_rel_hit_beat3_l2(i) or l_m_rel_hit_beat5_l2(i)) and + (rel_tag_l2(1 to 4) = tconv(i, 4)) and my_xucr0_cls ) or b; + end loop; + my_beat_mid <= b; +end process; + +my_beat_last_p: process (l_m_rel_hit_beat2_l2, l_m_rel_hit_beat6_l2, rel_data_val, my_xucr0_cls, rel_tag_l2, ldq_retry_l2) + variable b: std_ulogic; + variable c: std_ulogic; +begin + b := '0'; + c := '0'; + for i in 0 to lmq_entries-1 loop + b := (((l_m_rel_hit_beat2_l2(i) and rel_data_val(i) and not my_xucr0_cls) or (l_m_rel_hit_beat6_l2(i) and rel_data_val(i) and my_xucr0_cls)) ) or b; + c := (ldq_retry_l2(i) and (rel_tag_l2(1 to 4) = tconv(i, 4))) or c; + end loop; + my_beat_last_d <= b; + my_ldq_retry <= c; +end process; + +latch_my_beat_last : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(my_beat_last_offset to my_beat_last_offset), + scout => sov(my_beat_last_offset to my_beat_last_offset), + din(0) => my_beat_last_d, + dout(0) => my_beat_last_l2 ); + +my_beat_odd_p: process (l_m_rel_hit_beat1_l2, l_m_rel_hit_beat3_l2, l_m_rel_hit_beat5_l2, l_m_rel_hit_beat7_l2, rel_tag_l2) + variable b: std_ulogic; +begin + b := '0'; + for i in 0 to lmq_entries-1 loop + b := ((l_m_rel_hit_beat1_l2(i) or l_m_rel_hit_beat3_l2(i) or l_m_rel_hit_beat5_l2(i) or l_m_rel_hit_beat7_l2(i)) and + (rel_tag_l2(1 to 4) = tconv(i, 4)) ) or b; + end loop; + my_beat_odd <= b; +end process; + +ldq_rel1_val_buf <= reld_data_vld_l2 and not rel_cache_inh_l2 and not rel_l2only_l2 and + not rel_tag_l2(1) and my_beat1; +ldq_rel1_val <= ldq_rel1_val_buf; + +ldq_rel1_early_v <= my_beat1_early; + +ldq_rel_mid_val_buf <= reld_data_vld_l2 and not rel_cache_inh_l2 and not rel_l2only_l2 and + not rel_tag_l2(1) and my_beat_mid; +ldq_rel_mid_val <= ldq_rel_mid_val_buf; + +ldq_rel3_val_buf <= reld_data_vld_l2 and not rel_cache_inh_l2 and not rel_l2only_l2 and + not rel_tag_l2(1) and my_beat_last_l2; +ldq_rel3_val <= ldq_rel3_val_buf; + +ldq_rel3_early_v <= my_beat_last_d; + +l2only_from_queue_p: process (l_m_queue(0)(48), l_m_queue(1)(48), l_m_queue(2)(48), l_m_queue(3)(48), l_m_queue(4)(48), l_m_queue(5)(48), l_m_queue(6)(48), l_m_queue(7)(48), rel_tag_l2) + variable b: std_ulogic; +begin + b := '0'; + for i in 0 to lmq_entries-1 loop + b := (l_m_queue(i)(48) and (rel_tag_l2(1 to 4) = tconv(i, 4)) ) or b; + end loop; + l2only_from_queue <= b; +end process; + +l1dump_cslc <= reld_data_vld_l2 and not rel_cache_inh_l2 and not rel_tag_l2(1) and my_beat_last_l2 and + l1_dump and rel_lock_en_l2 and not l2only_from_queue; + +ldq_rel3_l1dump_val <= reld_data_vld_l2 and not rel_cache_inh_l2 and not rel_tag_l2(1) and my_beat_last_l2 and l1_dump; + + + +ldq_rel_data_val_buf <= reld_data_vld_l2 and not rel_cache_inh_l2 and not (rel_l2only_l2 and not (l1_dump and rel_intf_v_l2)) and + my_beat_odd and not my_ldq_retry; +ldq_rel_data_val <= ldq_rel_data_val_buf; + +ldq_rel_data_val_early <= data_val_dminus1_l2; + +ldq_rel_retry_val_buf <= ldq_rel_retry_val_dly_l2 and not rel_cache_inh_l2 and not rel_l2only_l2 and + not rel_tag_l2(1) and my_beat_last_l2; +ldq_rel_retry_val <= ldq_rel_retry_val_buf; + + + + + + + + +ldq_rel_ta_gpr(0 to 8) <= rel_tar_gpr_l2(0 to 8); + +ex3_loadmiss_qentry(0 to lmq_entries-1) <= l_q_wrt_en(0 to lmq_entries-1); +ex3_loadmiss_target(0 to 8) <= ex3_new_target_gpr(0 to 8); +ex3_loadmiss_target_type(0 to 1) <= "01" when (ld_m_val and ex3_axu_op_val) = '1' else + "10" when ld_m_val = '1' else + "00"; +ex3_loadmiss_tid(0 to 3) <= gate_and(ld_m_val, ex3_thrd_id(0 to 3)); + + +latch_loadmiss_qentry : tri_rlmreg_p + generic map (width => ex4_loadmiss_qentry'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(loadmiss_qentry_offset to loadmiss_qentry_offset + ex4_loadmiss_qentry'length-1), + scout => sov(loadmiss_qentry_offset to loadmiss_qentry_offset + ex4_loadmiss_qentry'length-1), + din => ex3_loadmiss_qentry(0 to lmq_entries-1), + dout => ex4_loadmiss_qentry(0 to lmq_entries-1) ); + +cmp_ex4_loadmiss_qentry <= ex4_loadmiss_qentry; +xu_iu_ex4_loadmiss_qentry(0 to lmq_entries-1) <= gate_and(not ex4_drop_ld_req, ex4_loadmiss_qentry(0 to lmq_entries-1)); + +ex5_loadmiss_qentry_d <= ex4_loadmiss_qentry when pe_recov_stall='0' else + ex5_loadmiss_qentry; + +latch_ex5_loadmiss_qentry : tri_rlmreg_p + generic map (width => ex5_loadmiss_qentry'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex5_loadmiss_qentry_offset to ex5_loadmiss_qentry_offset + ex5_loadmiss_qentry'length-1), + scout => sov(ex5_loadmiss_qentry_offset to ex5_loadmiss_qentry_offset + ex5_loadmiss_qentry'length-1), + din => ex5_loadmiss_qentry_d(0 to lmq_entries-1), + dout => ex5_loadmiss_qentry(0 to lmq_entries-1) ); + +xu_iu_ex5_loadmiss_qentry(0 to lmq_entries-1) <= ex5_loadmiss_qentry(0 to lmq_entries-1); + +ex6_loadmiss_qentry_d <= ex5_loadmiss_qentry when pe_recov_stall='0' else + ex6_loadmiss_qentry; + +latch_ex6_loadmiss_qentry : tri_rlmreg_p + generic map (width => ex6_loadmiss_qentry'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex6_loadmiss_qentry_offset to ex6_loadmiss_qentry_offset + ex6_loadmiss_qentry'length-1), + scout => sov(ex6_loadmiss_qentry_offset to ex6_loadmiss_qentry_offset + ex6_loadmiss_qentry'length-1), + din => ex6_loadmiss_qentry_d(0 to lmq_entries-1), + dout => ex6_loadmiss_qentry(0 to lmq_entries-1) ); + +ex7_loadmiss_qentry_d <= "10000000" when (ex6_loadmiss_qentry="00000000") and (pe_recov_stall='0') else + ex6_loadmiss_qentry when pe_recov_stall='0' else + ex7_loadmiss_qentry; + +latch_ex7_loadmiss_qentry : tri_rlmreg_p + generic map (width => ex7_loadmiss_qentry'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex7_loadmiss_qentry_offset to ex7_loadmiss_qentry_offset + ex7_loadmiss_qentry'length-1), + scout => sov(ex7_loadmiss_qentry_offset to ex7_loadmiss_qentry_offset + ex7_loadmiss_qentry'length-1), + din => ex7_loadmiss_qentry_d(0 to lmq_entries-1), + dout => ex7_loadmiss_qentry(0 to lmq_entries-1) ); + +latch_ex4_loadmiss_target : tri_rlmreg_p + generic map (width => ex4_loadmiss_target'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_loadmiss_target_offset to ex4_loadmiss_target_offset + ex4_loadmiss_target'length-1), + scout => sov(ex4_loadmiss_target_offset to ex4_loadmiss_target_offset + ex4_loadmiss_target'length-1), + din => ex3_loadmiss_target(0 to 8), + dout => ex4_loadmiss_target(0 to 8) ); + +xu_iu_ex4_loadmiss_target(0 to 8) <= ex4_loadmiss_target(0 to 8); + +latch_loadmiss_target : tri_rlmreg_p + generic map (width => xu_iu_ex5_loadmiss_target'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(loadmiss_target_offset to loadmiss_target_offset + xu_iu_ex5_loadmiss_target'length-1), + scout => sov(loadmiss_target_offset to loadmiss_target_offset + xu_iu_ex5_loadmiss_target'length-1), + din => ex4_loadmiss_target(0 to 8), + dout => xu_iu_ex5_loadmiss_target(0 to 8) ); + +latch_ex4_loadmiss_target_type : tri_rlmreg_p + generic map (width => ex4_loadmiss_target_type'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_loadmiss_target_type_offset to ex4_loadmiss_target_type_offset + ex4_loadmiss_target_type'length-1), + scout => sov(ex4_loadmiss_target_type_offset to ex4_loadmiss_target_type_offset + ex4_loadmiss_target_type'length-1), + din => ex3_loadmiss_target_type(0 to 1), + dout => ex4_loadmiss_target_type(0 to 1) ); + +xu_iu_ex4_loadmiss_target_type(0 to 1) <= ex4_loadmiss_target_type(0 to 1); + +latch_loadmiss_target_type : tri_rlmreg_p + generic map (width => xu_iu_ex5_loadmiss_target_type'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(loadmiss_target_type_offset to loadmiss_target_type_offset + xu_iu_ex5_loadmiss_target_type'length-1), + scout => sov(loadmiss_target_type_offset to loadmiss_target_type_offset + xu_iu_ex5_loadmiss_target_type'length-1), + din => ex4_loadmiss_target_type(0 to 1), + dout => xu_iu_ex5_loadmiss_target_type(0 to 1) ); + +latch_ex4_loadmiss_tid : tri_rlmreg_p + generic map (width => ex4_loadmiss_tid'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_loadmiss_tid_offset to ex4_loadmiss_tid_offset + ex4_loadmiss_tid'length-1), + scout => sov(ex4_loadmiss_tid_offset to ex4_loadmiss_tid_offset + ex4_loadmiss_tid'length-1), + din => ex3_loadmiss_tid(0 to 3), + dout => ex4_loadmiss_tid(0 to 3) ); + + +xu_iu_ex4_loadmiss_tid(0 to 3) <= gate_and(not ex4_drop_ld_req, ex4_loadmiss_tid(0 to 3)); + +ex4_loadmiss_tid_gated1(0 to 3) <= gate_and(not ex4_flush_load, ex4_loadmiss_tid(0 to 3)); +ex4_loadmiss_tid_gated(0 to 3) <= gate_and(not ex4_stg_flush, ex4_loadmiss_tid_gated1(0 to 3)); + +latch_loadmiss_tid : tri_rlmreg_p + generic map (width => xu_iu_ex5_loadmiss_tid'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(loadmiss_tid_offset to loadmiss_tid_offset + xu_iu_ex5_loadmiss_tid'length-1), + scout => sov(loadmiss_tid_offset to loadmiss_tid_offset + xu_iu_ex5_loadmiss_tid'length-1), + din => ex4_loadmiss_tid_gated(0 to 3), + dout => ex5_loadmiss_tid(0 to 3) ); + +xu_iu_ex5_loadmiss_tid(0 to 3) <= ex5_loadmiss_tid(0 to 3); + + + + + +complete_q: for i in 0 to lmq_entries-1 generate begin + ecc_err(i) <= beat_ecc_err or data_ecc_err_l2(i); + + + + + + ci_16B_comp_qentry(i) <= data_val_for_rel and (anaclat_tag(1 to 4) = tconv(i, 4)) and l_m_queue(i)(0) and not l_m_queue(i)(7) and not gpr_ecc_err_l2(i); + + even_beat(i) <= l_m_rel_hit_beat0_l2(i) or l_m_rel_hit_beat2_l2(i) or l_m_rel_c_i_beat0_l2(i) or + l_m_rel_hit_beat4_l2(i) or l_m_rel_hit_beat6_l2(i); + + ldm_complete_qentry(i) <= (data_val_dminus1_l2 and (tag_dminus1_l2(1 to 4) = tconv(i, 4))) and + not even_beat(i) and + (l_m_queue_addrlo(i)(58) = qw_dminus1_l2(58)) and + ((l_m_queue_addrlo(i)(57) = qw_dminus1_l2(57)) or not my_xucr0_cls) and + not gpr_updated_prev_l2(i) and not gpr_ecc_err_l2(i) and + not (l_m_queue(i)(0) and not l_m_queue(i)(7)); + + + larx_done(i) <= (l_m_queue(i)(1 to 4) = "0010") and l_m_queue(i)(6) and + ld_m_rel_done_no_retry(i) and not ecc_err(i); + + + complete_qentry(i) <= (ldm_complete_qentry(i) and my_xucr0_rel) or + (ldm_comp_qentry_l2(i) and not my_xucr0_rel) or + ci_16B_comp_qentry(i); + +end generate; + + +latch_ldm_comp_qentry : tri_rlmreg_p + generic map (width => ldm_comp_qentry_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ldm_comp_qentry_offset to ldm_comp_qentry_offset + ldm_comp_qentry_l2'length-1), + scout => sov(ldm_comp_qentry_offset to ldm_comp_qentry_offset + ldm_comp_qentry_l2'length-1), + din => ldm_complete_qentry(0 to lmq_entries-1), + dout => ldm_comp_qentry_l2(0 to lmq_entries-1) ); + + +compl_tid_q4: if lmq_entries=4 generate begin + complete_tid_d(0 to 3) <= gate_and(complete_qentry(0), rel_entry(0)(12 to 15)) or + gate_and(complete_qentry(1), rel_entry(1)(12 to 15)) or + gate_and(complete_qentry(2), rel_entry(2)(12 to 15)) or + gate_and(complete_qentry(3), rel_entry(3)(12 to 15)); + + larx_done_tid_d(0 to 3) <= gate_and(larx_done(0), rel_entry(0)(12 to 15)) or + gate_and(larx_done(1), rel_entry(1)(12 to 15)) or + gate_and(larx_done(2), rel_entry(2)(12 to 15)) or + gate_and(larx_done(3), rel_entry(3)(12 to 15)); + + rel_vpr_compl <= (complete_qentry(0) and rel_entry(0)(25)) or + (complete_qentry(1) and rel_entry(1)(25)) or + (complete_qentry(2) and rel_entry(2)(25)) or + (complete_qentry(3) and rel_entry(3)(25)); + + rel_compl <= complete_qentry(0) or complete_qentry(1) or complete_qentry(2) or complete_qentry(3); + +end generate; + +compl_tid_q8: if lmq_entries=8 generate begin + complete_tid_d(0 to 3) <= gate_and(complete_qentry(0), rel_entry(0)(12 to 15)) or + gate_and(complete_qentry(1), rel_entry(1)(12 to 15)) or + gate_and(complete_qentry(2), rel_entry(2)(12 to 15)) or + gate_and(complete_qentry(3), rel_entry(3)(12 to 15)) or + gate_and(complete_qentry(4), rel_entry(4)(12 to 15)) or + gate_and(complete_qentry(5), rel_entry(5)(12 to 15)) or + gate_and(complete_qentry(6), rel_entry(6)(12 to 15)) or + gate_and(complete_qentry(7), rel_entry(7)(12 to 15)); + + larx_done_tid_d(0 to 3) <= gate_and(larx_done(0), rel_entry(0)(12 to 15)) or + gate_and(larx_done(1), rel_entry(1)(12 to 15)) or + gate_and(larx_done(2), rel_entry(2)(12 to 15)) or + gate_and(larx_done(3), rel_entry(3)(12 to 15)) or + gate_and(larx_done(4), rel_entry(4)(12 to 15)) or + gate_and(larx_done(5), rel_entry(5)(12 to 15)) or + gate_and(larx_done(6), rel_entry(6)(12 to 15)) or + gate_and(larx_done(7), rel_entry(7)(12 to 15)); + + rel_vpr_compl <= (complete_qentry(0) and rel_entry(0)(25)) or + (complete_qentry(1) and rel_entry(1)(25)) or + (complete_qentry(2) and rel_entry(2)(25)) or + (complete_qentry(3) and rel_entry(3)(25)) or + (complete_qentry(4) and rel_entry(4)(25)) or + (complete_qentry(5) and rel_entry(5)(25)) or + (complete_qentry(6) and rel_entry(6)(25)) or + (complete_qentry(7) and rel_entry(7)(25)); + + rel_compl <= complete_qentry(0) or complete_qentry(1) or complete_qentry(2) or complete_qentry(3) or + complete_qentry(4) or complete_qentry(5) or complete_qentry(6) or complete_qentry(7); + +end generate; + +complete_target_type_d(0 to 1) <= "01" when rel_vpr_compl = '1' else + "10" when rel_compl = '1' else + "00"; + +latch_complete_qentry : tri_rlmreg_p + generic map (width => xu_iu_complete_qentry'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(complete_qentry_offset to complete_qentry_offset + xu_iu_complete_qentry'length-1), + scout => sov(complete_qentry_offset to complete_qentry_offset + xu_iu_complete_qentry'length-1), + din => complete_qentry(0 to lmq_entries-1), + dout => xu_iu_complete_qentry(0 to lmq_entries-1) ); + +latch_complete_tid : tri_rlmreg_p + generic map (width => xu_iu_complete_tid'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(complete_tid_offset to complete_tid_offset + xu_iu_complete_tid'length-1), + scout => sov(complete_tid_offset to complete_tid_offset + xu_iu_complete_tid'length-1), + din => complete_tid_d(0 to 3), + dout => xu_iu_complete_tid(0 to 3) ); + +latch_complete_target_type : tri_rlmreg_p + generic map (width => xu_iu_complete_target_type'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(complete_target_type_offset to complete_target_type_offset + xu_iu_complete_target_type'length-1), + scout => sov(complete_target_type_offset to complete_target_type_offset + xu_iu_complete_target_type'length-1), + din => complete_target_type_d(0 to 1), + dout => xu_iu_complete_target_type(0 to 1) ); + +latch_larx_done_tid : tri_rlmreg_p + generic map (width => xu_iu_larx_done_tid'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(larx_done_tid_offset to larx_done_tid_offset + xu_iu_larx_done_tid'length-1), + scout => sov(larx_done_tid_offset to larx_done_tid_offset + xu_iu_larx_done_tid'length-1), + din => larx_done_tid_d(0 to 3), + dout => larx_done_tid_l2(0 to 3) ); + +xu_iu_larx_done_tid <= larx_done_tid_l2; + + + + +ldq_rel_addr_early(64-real_data_add to 57) <= rel_addr_d(64-real_data_add to 57); + +ldq_rel_addr(64-real_data_add to 57) <= rel_addr_l2(64-real_data_add to 57); +ldq_rel_addr(58) <= qw_l2(58); + + +ldq_rel_tag_early(2 to 4) <= tag_dminus1_cpy_l2(2 to 4); +ldq_rel_tag(2 to 4) <= rel_tag_l2(2 to 4); + +ldq_rel_axu_val <= rel_vpr_val_l2; + + +my_noncache_beat_p: process (l_m_rel_val_c_i_dly, rel_tag_l2) + variable b: std_ulogic; +begin + b := '0'; + for i in 0 to lmq_entries-1 loop + b := (l_m_rel_val_c_i_dly(i) and (rel_tag_l2(1 to 4) = tconv(i, 4)) ) or b; + end loop; + my_noncache_beat <= b; +end process; + +update_gpr <= not rel_dcbt_l2 and (rel_addr_l2(58) = qw_l2(58)) and reld_data_vld_l2 and not ldq_rel_retry_val_dly_l2 and not rel_tag_l2(1) and + (my_beat1 or my_beat_last_l2 or my_beat_mid or my_noncache_beat) and + ((rel_addr_l2(57) = qw_l2(57)) or not my_xucr0_cls); + +latch_update_gpr : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(update_gpr_offset to update_gpr_offset), + scout => sov(update_gpr_offset to update_gpr_offset), + din(0) => update_gpr, + dout(0) => update_gpr_l2 ); +latch_rel_beat_crit_qw : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(rel_beat_crit_qw_offset to rel_beat_crit_qw_offset), + scout => sov(rel_beat_crit_qw_offset to rel_beat_crit_qw_offset), + din(0) => update_gpr, + dout(0) => ldq_rel_beat_crit_qw ); + +gpr_updated: for i in 0 to lmq_entries-1 generate begin + set_gpr_updated_prev(i) <= update_gpr_l2 and not ecc_err(i) and + (rel_tag_dplus1_l2(1 to 4) = tconv(i, 4)) and + not (ld_m_rel_done_l2(i) and not rel_done_ecc_err); + + gpr_updated_prev_d(i) <= set_gpr_updated_prev(i) or + (gpr_updated_prev_l2(i) and not reset_lmq_entry(i) ); + + gpr_updated_dly1_d(i) <= gpr_updated_prev_l2(i) and not reset_lmq_entry(i); + + gpr_updated_dly2_d(i) <= gpr_updated_dly1_l2(i) and not reset_lmq_entry(i); + + + set_gpr_ecc_err(i) <= update_gpr_l2 and ecc_err(i) and + (rel_tag_dplus1_l2(1 to 4) = tconv(i, 4)); + + reset_gpr_ecc_err(i) <= update_gpr_l2 and (not ecc_err(i) or ld_m_rel_done_dly2_l2(i)) and + (rel_tag_dplus1_l2(1 to 4) = tconv(i, 4)); + + gpr_ecc_err_d(i) <= (set_gpr_ecc_err(i) and not reset_gpr_ecc_err(i)) or + (not reset_gpr_ecc_err(i) and gpr_ecc_err_l2(i)); + +end generate; + +latch_gpr_updated_prev : tri_rlmreg_p + generic map (width => gpr_updated_prev_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(gpr_updated_prev_offset to gpr_updated_prev_offset + gpr_updated_prev_l2'length-1), + scout => sov(gpr_updated_prev_offset to gpr_updated_prev_offset + gpr_updated_prev_l2'length-1), + din => gpr_updated_prev_d(0 to lmq_entries-1), + dout => gpr_updated_prev_l2(0 to lmq_entries-1) ); + +latch_gpr_updated_dly1 : tri_rlmreg_p + generic map (width => gpr_updated_dly1_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(gpr_updated_dly1_offset to gpr_updated_dly1_offset + gpr_updated_dly1_l2'length-1), + scout => sov(gpr_updated_dly1_offset to gpr_updated_dly1_offset + gpr_updated_dly1_l2'length-1), + din => gpr_updated_dly1_d(0 to lmq_entries-1), + dout => gpr_updated_dly1_l2(0 to lmq_entries-1) ); + +latch_gpr_updated_dly2 : tri_rlmreg_p + generic map (width => gpr_updated_dly2_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(gpr_updated_dly2_offset to gpr_updated_dly2_offset + gpr_updated_dly2_l2'length-1), + scout => sov(gpr_updated_dly2_offset to gpr_updated_dly2_offset + gpr_updated_dly2_l2'length-1), + din => gpr_updated_dly2_d(0 to lmq_entries-1), + dout => gpr_updated_dly2_l2(0 to lmq_entries-1) ); + +latch_gpr_ecc_err : tri_rlmreg_p + generic map (width => gpr_ecc_err_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(gpr_ecc_err_offset to gpr_ecc_err_offset + gpr_ecc_err_l2'length-1), + scout => sov(gpr_ecc_err_offset to gpr_ecc_err_offset + gpr_ecc_err_l2'length-1), + din => gpr_ecc_err_d(0 to lmq_entries-1), + dout => gpr_ecc_err_l2(0 to lmq_entries-1) ); + + +sel_gpr_upd_q4: if lmq_entries=4 generate begin + selectedQ_gpr_update_prev <= (gpr_updated_prev_l2(0) and (rel_tag_dplus1_l2(1 to 4) = "0000")) or + (gpr_updated_prev_l2(1) and (rel_tag_dplus1_l2(1 to 4) = "0001")) or + (gpr_updated_prev_l2(2) and (rel_tag_dplus1_l2(1 to 4) = "0010")) or + (gpr_updated_prev_l2(3) and (rel_tag_dplus1_l2(1 to 4) = "0011")); + + selectedQ_ecc_err <= (data_ecc_err_l2(0) and not ld_m_rel_done_dly2_l2(0) and (rel_tag_dplus1_l2(1 to 4) = "0000")) or + (data_ecc_err_l2(1) and not ld_m_rel_done_dly2_l2(1) and (rel_tag_dplus1_l2(1 to 4) = "0001")) or + (data_ecc_err_l2(2) and not ld_m_rel_done_dly2_l2(2) and (rel_tag_dplus1_l2(1 to 4) = "0010")) or + (data_ecc_err_l2(3) and not ld_m_rel_done_dly2_l2(3) and (rel_tag_dplus1_l2(1 to 4) = "0011")); +end generate; + +sel_gpr_upd_q8: if lmq_entries=8 generate begin + selectedQ_gpr_update_prev <= (gpr_updated_prev_l2(0) and (rel_tag_dplus1_l2(1 to 4) = "0000")) or + (gpr_updated_prev_l2(1) and (rel_tag_dplus1_l2(1 to 4) = "0001")) or + (gpr_updated_prev_l2(2) and (rel_tag_dplus1_l2(1 to 4) = "0010")) or + (gpr_updated_prev_l2(3) and (rel_tag_dplus1_l2(1 to 4) = "0011")) or + (gpr_updated_prev_l2(4) and (rel_tag_dplus1_l2(1 to 4) = "0100")) or + (gpr_updated_prev_l2(5) and (rel_tag_dplus1_l2(1 to 4) = "0101")) or + (gpr_updated_prev_l2(6) and (rel_tag_dplus1_l2(1 to 4) = "0110")) or + (gpr_updated_prev_l2(7) and (rel_tag_dplus1_l2(1 to 4) = "0111")); + + selectedQ_ecc_err <= (data_ecc_err_l2(0) and not ld_m_rel_done_dly2_l2(0) and (rel_tag_dplus1_l2(1 to 4) = "0000")) or + (data_ecc_err_l2(1) and not ld_m_rel_done_dly2_l2(1) and (rel_tag_dplus1_l2(1 to 4) = "0001")) or + (data_ecc_err_l2(2) and not ld_m_rel_done_dly2_l2(2) and (rel_tag_dplus1_l2(1 to 4) = "0010")) or + (data_ecc_err_l2(3) and not ld_m_rel_done_dly2_l2(3) and (rel_tag_dplus1_l2(1 to 4) = "0011")) or + (data_ecc_err_l2(4) and not ld_m_rel_done_dly2_l2(4) and (rel_tag_dplus1_l2(1 to 4) = "0100")) or + (data_ecc_err_l2(5) and not ld_m_rel_done_dly2_l2(5) and (rel_tag_dplus1_l2(1 to 4) = "0101")) or + (data_ecc_err_l2(6) and not ld_m_rel_done_dly2_l2(6) and (rel_tag_dplus1_l2(1 to 4) = "0110")) or + (data_ecc_err_l2(7) and not ld_m_rel_done_dly2_l2(7) and (rel_tag_dplus1_l2(1 to 4) = "0111")); +end generate; + +ldq_rel_upd_gpr_buf <= update_gpr_l2 and not beat_ecc_err and + not selectedQ_ecc_err and + not selectedQ_gpr_update_prev; +ldq_rel_upd_gpr <= ldq_rel_upd_gpr_buf; + +ldq_rel_ecc_err <= beat_ecc_err or rel_done_ecc_err; + +rel_beat_crit_qw_block_d <= beat_ecc_err or selectedQ_ecc_err or selectedQ_gpr_update_prev; +latch_rel_beat_crit_qw_block : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(rel_beat_crit_qw_block_offset to rel_beat_crit_qw_block_offset), + scout => sov(rel_beat_crit_qw_block_offset to rel_beat_crit_qw_block_offset), + din(0) => rel_beat_crit_qw_block_d, + dout(0) => ldq_rel_beat_crit_qw_block ); + +flush_gpr_ecc_err: process(gpr_ecc_err_l2, l_m_queue(0)(18 to 21), l_m_queue(1)(18 to 21), l_m_queue(2)(18 to 21), l_m_queue(3)(18 to 21), l_m_queue(4)(18 to 21), l_m_queue(5)(18 to 21), l_m_queue(6)(18 to 21), l_m_queue(7)(18 to 21)) + variable b: std_ulogic_vector(0 to 3); +begin + b := "0000"; + for i in 0 to lmq_entries-1 loop + b := gate_and(gpr_ecc_err_l2(i), l_m_queue(i)(18 to 21)) or b; + end loop; + gpr_ecc_err_flush_tid(0 to 3) <= b; +end process; + + + + +rel_cacheable_p: for i in 0 to lmq_entries-1 generate begin + rel_cacheable(i) <= not rel_entry(i)(0) and not rel_entry(i)(29) and not lmq_back_invalidated_l2(i); + + rel_set_val(i) <= ld_m_rel_done_l2(i) and + not data_ecc_err_l2(i) and not data_ecc_ue_l2(i) and + rel_cacheable(i); +end generate; + +rel_set_val_or_p: process (rel_set_val) + variable b: std_ulogic; +begin + b := '0'; + for i in 0 to lmq_entries-1 loop + b := rel_set_val(i) or b; + end loop; + rel_set_val_or <= b; +end process; + + +ldq_rel_set_val_buf <= rel_set_val_or and + not beat_ecc_err and not (anaclat_ecc_err_ue and rel_intf_v_dplus1_l2) and + not rel_l2only_dly_l2 and not pe_recov_state_l2; + +ldq_rel_set_val <= ldq_rel_set_val_buf; + +ldq_rel_le_mode <= rel_le_mode_l2; +ldq_rel_rot_sel <= rel_rot_sel_l2; +ldq_rel_algebraic <= rel_algebraic_l2; +ldq_rel_lock_en <= rel_lock_en_l2; +ldq_rel_classid <= rel_classid_l2; +ldq_rel_dvc1_en <= rel_dvc1_l2; +ldq_rel_dvc2_en <= rel_dvc2_l2; +ldq_rel_watch_en <= rel_watch_en_l2; + + + +rel_bi_p: process (lmq_back_invalidated_l2, rel_tag_l2) + variable b: std_ulogic; +begin + b := '0'; + for i in 0 to lmq_entries-1 loop + b := (lmq_back_invalidated_l2(i) and (rel_tag_l2(1 to 4) = tconv(i, 4)) ) or b; + end loop; + ldq_rel_back_invalidated <= b; +end process; + + + + + + + + + + + + + + + +rel_data_a2mode: if a2mode=1 generate begin + set_rel_A_data <= reld_data_vld_l2 and send_rel_A_data_l2; + set_rel_B_data <= reld_data_vld_l2 and not send_rel_A_data_l2; + + rel_A_data_d(0 to 127) <= anaclat_data(0 to 127) when set_rel_A_data = '1' else + rel_A_data_l2(0 to 127); + + rel_B_data_d(0 to 127) <= anaclat_data(0 to 127) when set_rel_B_data = '1' else + rel_B_data_l2(0 to 127); +end generate; + +rel_data_nota2mode: if a2mode=0 generate begin + rel_A_data_d(0 to 127) <= anaclat_data(0 to 127); + + set_rel_A_data <= '0'; + set_rel_B_data <= '0'; + rel_B_data_d(0 to 127) <= (others=>'0'); + rel_B_data_l2(0 to 127) <= (others=>'0'); + +end generate; + +latch_rel_A_data : tri_rlmreg_p + generic map (width => rel_A_data_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dplus1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(rel_A_data_offset to rel_A_data_offset + rel_A_data_l2'length-1), + scout => sov(rel_A_data_offset to rel_A_data_offset + rel_A_data_l2'length-1), + din => rel_A_data_d(0 to 127), + dout => rel_A_data_l2(0 to 127) ); + +rel_B_data_a2mode: if a2mode=1 generate begin + latch_rel_B_data : tri_rlmreg_p + generic map (width => rel_B_data_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dplus1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(rel_B_data_offset to rel_B_data_offset + rel_B_data_l2'length-1), + scout => sov(rel_B_data_offset to rel_B_data_offset + rel_B_data_l2'length-1), + din => rel_B_data_d(0 to 127), + dout => rel_B_data_l2(0 to 127) ); +end generate; + +rel_data_256_a2mode: if a2mode=1 generate begin + send_rel_A_data_d <= not send_rel_A_data_l2 or my_xucr0_rel; + + latch_send_rel_A_data : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(send_rel_A_data_offset to send_rel_A_data_offset), + scout => sov(send_rel_A_data_offset to send_rel_A_data_offset), + din(0) => send_rel_A_data_d, + dout(0) => send_rel_A_data_l2 ); + + ldq_rel_256_data(0 to 127) <= anaclat_data(0 to 127) when qw_l2(59) = '0' else + rel_A_data_l2(0 to 127) when send_rel_A_data_l2 = '1' else + rel_B_data_l2(0 to 127); + + ldq_rel_256_data(128 to 255) <= anaclat_data(0 to 127) when qw_l2(59) = '1' else + rel_A_data_l2(0 to 127) when send_rel_A_data_l2 = '1' else + rel_B_data_l2(0 to 127); +end generate; + + +rel_data_256_nota2mode: if a2mode=0 generate begin + send_rel_A_data_d <= '0'; + send_rel_A_data_l2 <= '0'; + + ldq_rel_256_data(0 to 127) <= anaclat_data(0 to 127) when qw_l2(59) = '0' else + rel_A_data_l2(0 to 127); + + ldq_rel_256_data(128 to 255) <= rel_A_data_l2(0 to 127) when qw_l2(59) = '0' else + anaclat_data(0 to 127); +end generate; + + +lmq_empty <= ld_rel_val_l2(0 to lmq_entries-1) = (0 to lmq_entries-1 => '0'); + +xu_mm_lmq_stq_empty_d <= lmq_empty and not st_entry0_val_l2 and not ex4_st_val_l2 and not pe_recov_state_l2; + +latch_lmq_stq_empty : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(lmq_stq_empty_offset to lmq_stq_empty_offset), + scout => sov(lmq_stq_empty_offset to lmq_stq_empty_offset), + din(0) => xu_mm_lmq_stq_empty_d, + dout(0) => xu_mm_lmq_stq_empty ); + + +lmq_q: process(ld_rel_val_l2, l_m_queue(0)(18 to 21), l_m_queue(1)(18 to 21), l_m_queue(2)(18 to 21), l_m_queue(3)(18 to 21), l_m_queue(4)(18 to 21), l_m_queue(5)(18 to 21), l_m_queue(6)(18 to 21), l_m_queue(7)(18 to 21)) + variable b: std_ulogic_vector(0 to 3); +begin + b := "1111"; + for i in 0 to lmq_entries-1 loop + b := not (gate_and(ld_rel_val_l2(i), l_m_queue(i)(18 to 21)) ) and b; + end loop; + lmq_quiesce(0 to 3) <= b; +end process; + +mmu_quiesce(0 to 3) <= not (gate_and(mmu_q_val_l2, mmu_q_entry_l2(2 to 5)) ); + +stq_quiesce(0 to 3) <= not (gate_and(st_entry0_val_l2, s_m_queue0(38 to 41)) ); + +quiesce_d(0 to 3) <= gate_and(not pe_recov_state_l2, stq_quiesce(0 to 3) and lmq_quiesce(0 to 3) and mmu_quiesce(0 to 3)); + +latch_quiesce : tri_rlmreg_p + generic map (width => lsu_xu_quiesce'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(quiesce_offset to quiesce_offset + lsu_xu_quiesce'length-1), + scout => sov(quiesce_offset to quiesce_offset + lsu_xu_quiesce'length-1), + din => quiesce_d(0 to 3), + dout => lsu_xu_quiesce(0 to 3) ); + + +is2_l2_inv_val <= back_inv_val_l2; + +is2_l2_inv_p_addr <= anaclat_back_inv_addr(64-real_data_add to 63-cl_size); + + + + +err_l2intrf_ecc_d <= beat_ecc_err and rel_intf_v_dplus1_l2; + +err_l2intrf_ue_d <= anaclat_ecc_err_ue and rel_intf_v_dplus1_l2; + +latch_err_l2intrf_ecc : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(err_l2intrf_ecc_offset to err_l2intrf_ecc_offset), + scout => sov(err_l2intrf_ecc_offset to err_l2intrf_ecc_offset), + din(0) => err_l2intrf_ecc_d, + dout(0) => err_l2intrf_ecc_l2 ); + +latch_err_l2intrf_ue : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(err_l2intrf_ue_offset to err_l2intrf_ue_offset), + scout => sov(err_l2intrf_ue_offset to err_l2intrf_ue_offset), + din(0) => err_l2intrf_ue_d, + dout(0) => err_l2intrf_ue_l2 ); + +invld_reld: process(ld_rel_val_l2, tag_dminus1_l2, data_val_dminus1_l2) + variable b: std_ulogic; +begin + b := '0'; + for i in 0 to lmq_entries-1 loop + b := (data_val_dminus1_l2 and (tag_dminus1_l2(1 to 4)=tconv(i,4)) and not ld_rel_val_l2(i)) or b; + end loop; + err_invld_reld_d <= b; +end process; + +latch_err_invld_reld : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(err_invld_reld_offset to err_invld_reld_offset), + scout => sov(err_invld_reld_offset to err_invld_reld_offset), + din(0) => err_invld_reld_d, + dout(0) => err_invld_reld_l2 ); + + +err_cred_overrun_d <= store_cmd_count_l2(0 to 1)="11" or load_cmd_count_l2(0 to 1)="11"; + +latch_cred_overrun : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(cred_overrun_offset to cred_overrun_offset), + scout => sov(cred_overrun_offset to cred_overrun_offset), + din(0) => err_cred_overrun_d, + dout(0) => err_cred_overrun_l2); + + +err_rpt : tri_direct_err_rpt + generic map (width => 4) + port map (vd => vdd, + gd => gnd, + err_in(0) => err_l2intrf_ecc_l2, + err_in(1) => err_l2intrf_ue_l2, + err_in(2) => err_invld_reld_l2, + err_in(3) => err_cred_overrun_l2, + err_out(0) => xu_pc_err_l2intrf_ecc, + err_out(1) => xu_pc_err_l2intrf_ue, + err_out(2) => xu_pc_err_invld_reld, + err_out(3) => xu_pc_err_l2credit_overrun); + + + +latch_reld_ditc_pop : tri_rlmreg_p + generic map (width => ac_an_reld_ditc_pop_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(reld_ditc_pop_offset to reld_ditc_pop_offset + ac_an_reld_ditc_pop_q'length-1), + scout => sov(reld_ditc_pop_offset to reld_ditc_pop_offset + ac_an_reld_ditc_pop_q'length-1), + din => ac_an_reld_ditc_pop_int(0 to 3), + dout => ac_an_reld_ditc_pop_q(0 to 3) ); + +latch_bx_ib_empty : tri_rlmreg_p + generic map (width => bx_ib_empty_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(bx_ib_empty_offset to bx_ib_empty_offset + bx_ib_empty_q'length-1), + scout => sov(bx_ib_empty_offset to bx_ib_empty_offset + bx_ib_empty_q'length-1), + din => bx_ib_empty_int(0 to 3), + dout => bx_ib_empty_q(0 to 3) ); + + + + +spare_0_lcb: entity tri.tri_lcbnd(tri_lcbnd) + port map(vd => vdd, + gd => gnd, + act => '0', + nclk => nclk, + forcee => func_sl_force, + thold_b => func_sl_thold_0_b, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + sg => sg_0, + lclk => spare_0_lclk, + d1clk => spare_0_d1clk, + d2clk => spare_0_d2clk); +spare_0_latch : entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width => spare_0_l2'length, expand_type => expand_type, btr => "NLI0001_X2_A12TH", init=>(spare_0_l2'range=>'0')) + port map (vd => vdd, gd => gnd, + LCLK => spare_0_lclk, + D1CLK => spare_0_d1clk, + D2CLK => spare_0_d2clk, + SCANIN => siv(spare_0_offset to spare_0_offset + spare_0_l2'length-1), + SCANOUT => sov(spare_0_offset to spare_0_offset + spare_0_l2'length-1), + D => spare_0_d, + QB => spare_0_l2); +spare_0_d <= not spare_0_l2; + +spare_1_lcb: entity tri.tri_lcbnd(tri_lcbnd) + port map(vd => vdd, + gd => gnd, + act => '0', + nclk => nclk, + forcee => func_sl_force, + thold_b => func_sl_thold_0_b, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + sg => sg_0, + lclk => spare_1_lclk, + d1clk => spare_1_d1clk, + d2clk => spare_1_d2clk); +spare_1_latch : entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width => spare_1_l2'length, expand_type => expand_type, btr => "NLI0001_X2_A12TH", init=>(spare_1_l2'range=>'0')) + port map (vd => vdd, gd => gnd, + LCLK => spare_1_lclk, + D1CLK => spare_1_d1clk, + D2CLK => spare_1_d2clk, + SCANIN => siv(spare_1_offset to spare_1_offset + spare_1_l2'length-1), + SCANOUT => sov(spare_1_offset to spare_1_offset + spare_1_l2'length-1), + D => spare_1_d, + QB => spare_1_l2); +spare_1_d <= not spare_1_l2; + + +spare_4_lcb: entity tri.tri_lcbnd(tri_lcbnd) + port map(vd => vdd, + gd => gnd, + act => '0', + nclk => nclk, + forcee => func_sl_force, + thold_b => func_sl_thold_0_b, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + sg => sg_0, + lclk => spare_4_lclk, + d1clk => spare_4_d1clk, + d2clk => spare_4_d2clk); +spare_4_latch : entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width => spare_4_l2'length, expand_type => expand_type, btr => "NLI0001_X2_A12TH", init=>(spare_4_l2'range=>'0')) + port map (vd => vdd, gd => gnd, + LCLK => spare_4_lclk, + D1CLK => spare_4_d1clk, + D2CLK => spare_4_d2clk, + SCANIN => siv(spare_4_offset to spare_4_offset + spare_4_l2'length-1), + SCANOUT => sov(spare_4_offset to spare_4_offset + spare_4_l2'length-1), + D => spare_4_d, + QB => spare_4_l2); +spare_4_d <= not spare_4_l2; + + + + +dbg_d(0 to 7) <= l_q_rd_en; +dbg_d(8 to 11) <= ex4st_hit_ex6_recov & + stq_hit_ex6_recov & + blk_st_for_pe_recov & + blk_st_cred_pop; +dbg_d(12 to 13) <= lq_rd_en_is_ex5 & lq_rd_en_is_ex6; +dbg_d(14) <= selected_entry_flushed; +dbg_d(15 to 26) <= cmd_type_st(0 to 5) & cmd_type_ld(0 to 5); +dbg_d(27) <= load_flushed; +dbg_d(28) <= rd_seq_num_skip; +dbg_d(29) <= nxt_st_cred_tkn; +dbg_d(30) <= cred_pop; +dbg_d(31) <= store_sent; +dbg_d(32) <= ex4_flush_store; +dbg_d(33) <= mmu_st_sent; +dbg_d(34 to 37) <= i_f_q0_sent & i_f_q1_sent & i_f_q2_sent & i_f_q3_sent; +dbg_d(38) <= iu_sent_val; +dbg_d(39) <= mmu_sent; +dbg_d(40 to 40+lmq_entries-1) <= complete_qentry; + +latch_dbg : tri_rlmreg_p + generic map (width => dbg_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(dbg_offset to dbg_offset + dbg_l2'length-1), + scout => sov(dbg_offset to dbg_offset + dbg_l2'length-1), + din => dbg_d, + dout => dbg_l2 ); + +lmq_dbg_l2req <= l2req_l2 & + l2req_ld_core_tag_l2 & + l2req_ra_l2 & + l2req_st_byte_enbl_l2(0 to 15) & + l2req_thread_l2 & + l2req_ttype_l2 & + l2req_wimg_l2 & + l2req_endian_l2 & + l2req_user_l2 & + l2req_ld_xfr_len_l2 & + ex6_st_data_l2(0 to 127); + +lmq_dbg_rel <= anaclat_data_coming & + anaclat_data_val & + anaclat_reld_crit_qw & + anaclat_ditc & + anaclat_l1_dump & + anaclat_tag(1 to 4) & + anaclat_qw(58 to 59) & + anaclat_ecc_err & + anaclat_ecc_err_ue & + anaclat_data(0 to 127); + +lmq_dbg_binv <= anaclat_back_inv & + anaclat_back_inv_addr & + anaclat_back_inv_target_1 & + anaclat_back_inv_target_4; + +lmq_dbg_pops <= anaclat_ld_pop & + anaclat_st_gather & + anaclat_st_pop & + anaclat_st_pop_thrd; + +lmq_dbg_dcache_pe <= l2req_resend_l2 & + l2req_recycle_l2 & + ex6_ld_recov_val_l2 & + ex6_ld_recov_extra_l2(0) & + ex7_ld_recov_val_l2 & + ex7_ld_recov_extra_l2(0) & + ex7_ld_recov_l2(1 to 6) & + ex7_ld_recov_l2(18 to 21) & + ex7_ld_recov_l2(53 to (53+(real_data_add-2))) & + st_hit_recov_ld_l2 & + pe_recov_state_l2 & + blk_ld_for_pe_recov_l2; + +lmq_dbg_grp0 <= l_m_rel_hit_beat0_l2 & + l_m_rel_hit_beat1_l2 & + l_m_rel_hit_beat2_l2 & + l_m_rel_hit_beat3_l2 & + l_m_rel_val_c_i_dly & + lmq_back_invalidated_l2(0 to lmq_entries-1) & + dbg_l2(40 to 40+lmq_entries-1) & + ldq_retry_l2(0 to lmq_entries-1) & + retry_started_l2(0 to lmq_entries-1) & + gpr_ecc_err_l2(0 to lmq_entries-1) & + "00"; + +lmq_dbg_grp1 <= l_m_rel_hit_beat0_l2 & + l_m_rel_hit_beat1_l2 & + l_m_rel_hit_beat2_l2 & + l_m_rel_hit_beat3_l2 & + l_m_rel_val_c_i_dly & + gpr_ecc_err_l2(0 to lmq_entries-1) & + data_ecc_err_l2(0 to lmq_entries-1) & + data_ecc_ue_l2(0 to lmq_entries-1) & + gpr_updated_prev_l2(0 to lmq_entries-1) & + anaclat_data_val & + anaclat_reld_crit_qw & + anaclat_tag(1 to 4) & + anaclat_qw(58 to 59) & + anaclat_ecc_err & + anaclat_ecc_err_ue; + +lmq_dbg_grp2 <= ex4_l2cmdq_flush_l2(0) & + ex4_l2cmdq_flush_l2(3) & + ex4_drop_ld_req & + ex5_flush_l2 & + ex5_stg_flush & + dbg_l2(21 to 26) & + ex4_loadmiss_qentry(0 to lmq_entries-1) & + ld_entry_val_l2(0 to lmq_entries-1) & + ld_rel_val_l2(0 to lmq_entries-1) & + ex4_lmq_cpy_l2(0 to lmq_entries-1) & + send_if_req_l2 & + send_ld_req_l2 & + send_mm_req_l2 & + load_cmd_count_l2 & + load_sent_dbglat_l2 & + dbg_l2(27) & + dbg_l2(14) & + ex6_load_sent_l2 & + ex6_flush_l2 & + cmd_seq_l2 & + dbg_l2(0 to 7) & + dbg_l2(28) & + dbg_l2(12) & + dbg_l2(13) & + l_m_q_hit_st_l2(0 to lmq_entries-1) & + lmq_drop_rel_l2(0 to lmq_entries-1) & + ex4_l2cmdq_flush_l2(4); + +lmq_dbg_grp3 <= ex4_l2cmdq_flush_l2(2) & + ex4_l2cmdq_flush_l2(1) & + ex4_l2cmdq_flush_l2(0) & + l_m_fnd_stg & + ex5_flush_l2 & + ex5_stg_flush & + ex4_st_val_l2 & + st_entry0_val_l2 & + s_m_queue0(0 to 5) & + s_m_queue0(58 to (58+real_data_add-6-1)) & + store_cmd_count_l2 & + dbg_l2(29) & + dbg_l2(30) & + ex5_sel_st_req & + dbg_l2(31) & + dbg_l2(32) & + ex5_flush_store & + ex6_store_sent_l2 & + ex6_flush_l2 & + l2req_l2 & + l2req_thread_l2 & + l2req_ttype_l2 & + ob_req_val_l2 & + ob_ditc_val_l2 & + bx_cmd_stall_l2 & + bx_cmd_sent_l2 & + dbg_l2(8 to 11) & + st_recycle_v_l2 & + l2req_resend_l2 & + l2req_recycle_l2 & + dbg_l2(33) & + mmu_q_val & + mmu_q_entry_l2(0); + +lmq_dbg_grp4 <= ifetch_req_l2 & + ifetch_ra_l2 & + ifetch_thread_l2 & + i_f_q0_val_l2 & + i_f_q1_val_l2 & + i_f_q2_val_l2 & + i_f_q3_val_l2 & + send_if_req_l2 & + send_ld_req_l2 & + send_mm_req_l2 & + dbg_l2(34 to 37) & + dbg_l2(38) & + l2req_l2 & + l2req_thread_l2 & + l2req_ttype_l2 & + l2req_ld_core_tag_l2 & + l2req_wimg_l2 & + anaclat_data_val & + anaclat_reld_crit_qw & + anaclat_tag(1 to 4) & + anaclat_qw(58 to 59) & + anaclat_ecc_err & + anaclat_ecc_err_ue & + load_credit & + store_credit & + ex5_sel_st_req & + '0' ; + +lmq_dbg_grp5 <= mm_req_val_l2 & + mmu_q_val_l2 & + mmu_q_entry_l2 & + send_if_req_l2 & + send_ld_req_l2 & + send_mm_req_l2 & + dbg_l2(39) & + l2req_l2 & + l2req_thread_l2 & + l2req_ttype_l2 & + "0000"; + +lmq_dbg_grp6 <= ex3_stg_flush & + ex4_l2cmdq_flush_l2(0) & + ex4_l2cmdq_flush_l2(2) & + ex4_l2cmdq_flush_l2(1) & + ex4_l2cmdq_flush_l2(3) & + ex4_drop_ld_req & + l_m_fnd_stg & + ex4_stg_flush & + my_ex4_flush_l2 & + ex5_stg_flush & + ex2_lm_dep_hit_buf & + ex3_thrd_id(0 to 3) & + dbg_l2(15 to 20) & + dbg_l2(21 to 26) & + ex4_lmq_cpy_l2(0 to lmq_entries-1) & + lmq_collision_t0_l2(0 to lmq_entries-1) & + lmq_collision_t1_l2(0 to lmq_entries-1) & + lmq_collision_t2_l2(0 to lmq_entries-1) & + lmq_collision_t3_l2(0 to lmq_entries-1) & + ldq_barr_active_l2(0 to 3) & + ldq_barr_done_l2(0 to 3) & + sync_done_tid_l2(0 to 3) & + ld_rel_val_l2 & + st_entry0_val_l2; + + + +siv(0 to l_m_queue_addrlo_offset-1) <= sov(1 to l_m_queue_addrlo_offset-1) & scan_in(0); +scan_out(0) <= sov(0) and scan_dis_dc_b; + + +siv(l_m_queue_addrlo_offset to l2req_ld_core_tag_offset-1) <= sov(l_m_queue_addrlo_offset+1 to l2req_ld_core_tag_offset-1) & scan_in(1); +scan_out(1) <= sov(l_m_queue_addrlo_offset) and scan_dis_dc_b; + + +siv(l2req_ld_core_tag_offset to siv'right) <= sov(l2req_ld_core_tag_offset+1 to siv'right) & scan_in(2); +scan_out(2) <= sov(l2req_ld_core_tag_offset) and scan_dis_dc_b; + +bcfg_siv(0 to bcfg_siv'right) <= bcfg_sov(1 to bcfg_siv'right) & bcfg_scan_in; +bcfg_scan_out <= bcfg_sov(0) and scan_dis_dc_b; + +end xuq_lsu_l2cmdq; + + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_mux41.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_mux41.vhdl new file mode 100644 index 0000000..db51f21 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_mux41.vhdl @@ -0,0 +1,66 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; use ieee.std_logic_1164.all; +library support; + use support.power_logic_pkg.all; + +entity xuq_lsu_mux41 is + port ( + vdd :inout power_logic; + gnd :inout power_logic; + D0 :in std_ulogic; + D1 :in std_ulogic; + D2 :in std_ulogic; + D3 :in std_ulogic; + S0 :in std_ulogic; + S1 :in std_ulogic; + S2 :in std_ulogic; + S3 :in std_ulogic; + Y :out std_ulogic + ); + + + +end entity xuq_lsu_mux41; + +architecture xuq_lsu_mux41 of xuq_lsu_mux41 is + +signal y0_b :std_ulogic; +signal y1_b :std_ulogic; + + +begin + +u_y0: y0_b <= not( (D0 and S0) or (D1 and S1) ); +u_y1: y1_b <= not( (D2 and S2) or (D3 and S3) ); +u_y: Y <= not(y0_b and y1_b); + +end xuq_lsu_mux41; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_perf.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_perf.vhdl new file mode 100644 index 0000000..db00015 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_lsu_perf.vhdl @@ -0,0 +1,281 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee,ibm,support,work,tri,clib; +use ieee.std_logic_1164.all; +use support.power_logic_pkg.all; +use tri.tri_latches_pkg.all; + +entity xuq_lsu_perf is +generic( expand_type :integer := 2); +port( + + lsu_perf_events :in std_ulogic_vector(0 to 46); + + pc_xu_event_bus_enable :in std_ulogic; + pc_xu_event_count_mode :in std_ulogic_vector(0 to 2); + pc_xu_lsu_event_mux_ctrls :in std_ulogic_vector(0 to 47); + pc_xu_cache_par_err_event :in std_ulogic; + + spr_msr_gs :in std_ulogic_vector(0 to 3); + spr_msr_pr :in std_ulogic_vector(0 to 3); + + xu_pc_lsu_event_data :out std_ulogic_vector(0 to 7); + + vdd :inout power_logic; + gnd :inout power_logic; + nclk :in clk_logic; + sg_0 :in std_ulogic; + func_slp_sl_thold_0_b :in std_ulogic; + func_slp_sl_force :in std_ulogic; + d_mode_dc :in std_ulogic; + delay_lclkr_dc :in std_ulogic; + mpw1_dc_b :in std_ulogic; + mpw2_dc_b :in std_ulogic; + scan_in :in std_ulogic; + scan_out :out std_ulogic +); + +-- synopsys translate_off + +-- synopsys translate_on +end xuq_lsu_perf; +architecture xuq_lsu_perf of xuq_lsu_perf is + + +signal t0_events : std_ulogic_vector(0 to 31); +signal t1_events : std_ulogic_vector(0 to 31); +signal t2_events : std_ulogic_vector(0 to 31); +signal t3_events : std_ulogic_vector(0 to 31); +signal t0_lsu_events : std_ulogic_vector(0 to 31); +signal t1_lsu_events : std_ulogic_vector(0 to 31); +signal t2_lsu_events : std_ulogic_vector(0 to 31); +signal t3_lsu_events : std_ulogic_vector(0 to 31); +signal t0_lsu_events_tmp : std_ulogic_vector(0 to 23); +signal t1_lsu_events_tmp : std_ulogic_vector(0 to 23); +signal t2_lsu_events_tmp : std_ulogic_vector(0 to 23); +signal t3_lsu_events_tmp : std_ulogic_vector(0 to 23); +signal event_en_q, event_en_d : std_ulogic_vector(0 to 3); +signal event_data_q, event_data_d : std_ulogic_vector(xu_pc_lsu_event_data'range); +signal event_mux_ctrls_q, event_mux_ctrls_d : std_ulogic_vector(0 to 47); +signal lsu_perf_events_q : std_ulogic_vector(0 to 46); +signal pc_event_count_mode_q : std_ulogic_vector(0 to 2); +signal pc_cache_par_err_event_q : std_ulogic; +signal pc_event_bus_enable_q : std_ulogic; + +constant event_en_offset : integer := 0; +constant event_data_offset : integer := event_en_offset + event_en_q'length; +constant event_mux_ctrls_offset : integer := event_data_offset + event_data_q'length; +constant lsu_perf_events_offset : integer := event_mux_ctrls_offset + event_mux_ctrls_q'length; +constant pc_event_count_mode_offset : integer := lsu_perf_events_offset + lsu_perf_events_q'length; +constant pc_cache_par_err_event_offset : integer := pc_event_count_mode_offset + pc_event_count_mode_q'length; +constant pc_event_bus_enable_offset : integer := pc_cache_par_err_event_offset + 1; +constant scan_right : integer := pc_event_bus_enable_offset + 1; + +signal siv : std_ulogic_vector(0 to scan_right-1); +signal sov : std_ulogic_vector(0 to scan_right-1); +signal tiup : std_ulogic; + +begin + +tiup <= '1'; + + +event_en_d <= ( spr_msr_pr and (0 to 3=>pc_event_count_mode_q(0))) or + (not spr_msr_pr and spr_msr_gs and (0 to 3=>pc_event_count_mode_q(1))) or + (not spr_msr_pr and not spr_msr_gs and (0 to 3=>pc_event_count_mode_q(2))); + +event_mux_ctrls_d <= pc_xu_lsu_event_mux_ctrls; + + + +t0_lsu_events_tmp <= (lsu_perf_events_q(4 to 20) & lsu_perf_events_q(35 to 41)) and (0 to 23=>lsu_perf_events_q(0)); +t1_lsu_events_tmp <= (lsu_perf_events_q(4 to 20) & lsu_perf_events_q(35 to 41)) and (0 to 23=>lsu_perf_events_q(1)); +t2_lsu_events_tmp <= (lsu_perf_events_q(4 to 20) & lsu_perf_events_q(35 to 41)) and (0 to 23=>lsu_perf_events_q(2)); +t3_lsu_events_tmp <= (lsu_perf_events_q(4 to 20) & lsu_perf_events_q(35 to 41)) and (0 to 23=>lsu_perf_events_q(3)); + +t0_lsu_events <= t0_lsu_events_tmp & lsu_perf_events_q(42) & lsu_perf_events_q(21) & lsu_perf_events_q(25) & lsu_perf_events_q(29) & + lsu_perf_events_q(33 to 34) & pc_cache_par_err_event_q & lsu_perf_events_q(46); +t1_lsu_events <= t1_lsu_events_tmp & lsu_perf_events_q(43) & lsu_perf_events_q(22) & lsu_perf_events_q(26) & lsu_perf_events_q(30) & + lsu_perf_events_q(33 to 34) & pc_cache_par_err_event_q & lsu_perf_events_q(46); +t2_lsu_events <= t2_lsu_events_tmp & lsu_perf_events_q(44) & lsu_perf_events_q(23) & lsu_perf_events_q(27) & lsu_perf_events_q(31) & + lsu_perf_events_q(33 to 34) & pc_cache_par_err_event_q & lsu_perf_events_q(46); +t3_lsu_events <= t3_lsu_events_tmp & lsu_perf_events_q(45) & lsu_perf_events_q(24) & lsu_perf_events_q(28) & lsu_perf_events_q(32) & + lsu_perf_events_q(33 to 34) & pc_cache_par_err_event_q & lsu_perf_events_q(46); + +t0_events(0 to 31) <= t0_lsu_events and (0 to 31=>event_en_q(0)); +t1_events(0 to 31) <= t1_lsu_events and (0 to 31=>event_en_q(1)); +t2_events(0 to 31) <= t2_lsu_events and (0 to 31=>event_en_q(2)); +t3_events(0 to 31) <= t3_lsu_events and (0 to 31=>event_en_q(3)); + + +xuq_lsu_perf_mux1 : entity clib.c_event_mux(c_event_mux) +generic map(events_in => 128) +port map( + vd => vdd, + gd => gnd, + t0_events => t0_events, + t1_events => t1_events, + t2_events => t2_events, + t3_events => t3_events, + select_bits => event_mux_ctrls_q, + event_bits => event_data_d +); + +xu_pc_lsu_event_data <= event_data_q; + +event_en_latch : tri_rlmreg_p +generic map (width => event_en_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => pc_event_bus_enable_q, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(event_en_offset to event_en_offset + event_en_q'length-1), + scout => sov(event_en_offset to event_en_offset + event_en_q'length-1), + din => event_en_d, + dout => event_en_q); + +event_data_latch : tri_rlmreg_p +generic map (width => event_data_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => pc_event_bus_enable_q, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(event_data_offset to event_data_offset + event_data_q'length-1), + scout => sov(event_data_offset to event_data_offset + event_data_q'length-1), + din => event_data_d, + dout => event_data_q); + +event_mux_ctrls_latch : tri_rlmreg_p +generic map (width => event_mux_ctrls_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => pc_event_bus_enable_q, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(event_mux_ctrls_offset to event_mux_ctrls_offset + event_mux_ctrls_q'length-1), + scout => sov(event_mux_ctrls_offset to event_mux_ctrls_offset + event_mux_ctrls_q'length-1), + din => event_mux_ctrls_d, + dout => event_mux_ctrls_q); + +lsu_perf_events_latch : tri_rlmreg_p +generic map (width => lsu_perf_events_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => pc_event_bus_enable_q, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(lsu_perf_events_offset to lsu_perf_events_offset + lsu_perf_events_q'length-1), + scout => sov(lsu_perf_events_offset to lsu_perf_events_offset + lsu_perf_events_q'length-1), + din => lsu_perf_events, + dout => lsu_perf_events_q); + +pc_event_count_mode_latch : tri_rlmreg_p +generic map (width => pc_event_count_mode_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => pc_event_bus_enable_q, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(pc_event_count_mode_offset to pc_event_count_mode_offset + pc_event_count_mode_q'length-1), + scout => sov(pc_event_count_mode_offset to pc_event_count_mode_offset + pc_event_count_mode_q'length-1), + din => pc_xu_event_count_mode, + dout => pc_event_count_mode_q); + +pc_cache_par_err_event_latch : tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => pc_event_bus_enable_q, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(pc_cache_par_err_event_offset), + scout => sov(pc_cache_par_err_event_offset), + din => pc_xu_cache_par_err_event, + dout => pc_cache_par_err_event_q); + +pc_event_bus_enable_latch : tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(pc_event_bus_enable_offset), + scout => sov(pc_event_bus_enable_offset), + din => pc_xu_event_bus_enable, + dout => pc_event_bus_enable_q); + +siv(0 to siv'right) <= sov(1 to siv'right) & scan_in; +scan_out <= sov(0); + +end architecture xuq_lsu_perf; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_perf.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_perf.vhdl new file mode 100644 index 0000000..a07213c --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_perf.vhdl @@ -0,0 +1,364 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee,ibm,support,work,tri,clib; +use ieee.std_logic_1164.all; +use support.power_logic_pkg.all; +use tri.tri_latches_pkg.all; + +entity xuq_perf is +generic( + expand_type : integer := 2); +port( + nclk : in clk_logic; + + func_sl_thold_2 : in std_ulogic; + sg_2 : in std_ulogic; + clkoff_dc_b : in std_ulogic; + d_mode_dc : in std_ulogic; + delay_lclkr_dc : in std_ulogic; + mpw1_dc_b : in std_ulogic; + mpw2_dc_b : in std_ulogic; + pc_xu_ccflush_dc : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + cpl_perf_tx_events : in std_ulogic_vector(0 to 75); + spr_perf_tx_events : in std_ulogic_vector(0 to 31); + byp_perf_tx_events : in std_ulogic_vector(0 to 11); + fxa_perf_muldiv_in_use : in std_ulogic; + + pc_xu_event_bus_enable : in std_ulogic; + pc_xu_event_count_mode : in std_ulogic_vector(0 to 2); + pc_xu_event_mux_ctrls : in std_ulogic_vector(0 to 47); + + xu_pc_event_data : out std_ulogic_vector(0 to 7); + + spr_msr_gs : in std_ulogic_vector(0 to 3); + spr_msr_pr : in std_ulogic_vector(0 to 3); + + vdd : inout power_logic; + gnd : inout power_logic +); + +-- synopsys translate_off + +-- synopsys translate_on +end xuq_perf; +architecture xuq_perf of xuq_perf is + +signal event_en_q, event_en_d : std_ulogic_vector(0 to 3); +signal event_data_q, event_data_d : std_ulogic_vector(xu_pc_event_data'range); +signal event_mux_ctrls_q, event_mux_ctrls_d : std_ulogic_vector(0 to 47); +signal cpl_perf_tx_events_q : std_ulogic_vector(0 to 75); +signal spr_perf_tx_events_q : std_ulogic_vector(0 to 31); +signal byp_perf_tx_events_q : std_ulogic_vector(0 to 11); +signal muldiv_in_use_q : std_ulogic; +signal processor_busy_q, processor_busy_d : std_ulogic; +signal br_commit_q, br_commit_d : std_ulogic; +signal br_mispred_q, br_mispred_d : std_ulogic; +signal br_ta_mispred_q, br_ta_mispred_d : std_ulogic; +signal pc_event_count_mode_q : std_ulogic_vector(0 to 2); +signal pc_event_bus_enable_q : std_ulogic; +constant event_en_offset : integer := 0; +constant event_data_offset : integer := event_en_offset + event_en_q'length; +constant event_mux_ctrls_offset : integer := event_data_offset + event_data_q'length; +constant cpl_perf_tx_events_offset : integer := event_mux_ctrls_offset + event_mux_ctrls_q'length; +constant spr_perf_tx_events_offset : integer := cpl_perf_tx_events_offset + cpl_perf_tx_events_q'length; +constant byp_perf_tx_events_offset : integer := spr_perf_tx_events_offset + spr_perf_tx_events_q'length; +constant muldiv_in_use_offset : integer := byp_perf_tx_events_offset + byp_perf_tx_events_q'length; +constant processor_busy_offset : integer := muldiv_in_use_offset + 1; +constant br_commit_offset : integer := processor_busy_offset + 1; +constant br_mispred_offset : integer := br_commit_offset + 1; +constant br_ta_mispred_offset : integer := br_mispred_offset + 1; +constant pc_event_count_mode_offset : integer := br_ta_mispred_offset + 1; +constant pc_event_bus_enable_offset : integer := pc_event_count_mode_offset + pc_event_count_mode_q'length; +constant scan_right : integer := pc_event_bus_enable_offset + 1; +signal siv : std_ulogic_vector(0 to scan_right-1); +signal sov : std_ulogic_vector(0 to scan_right-1); + +signal tiup : std_ulogic; +signal func_sl_thold_1 : std_ulogic; +signal sg_1 : std_ulogic; +signal func_sl_thold_0 : std_ulogic; +signal sg_0 : std_ulogic; +signal func_sl_force : std_ulogic; +signal func_sl_thold_0_b : std_ulogic; +signal t0_events, t0_events_in : std_ulogic_vector(0 to 31); +signal t1_events, t1_events_in : std_ulogic_vector(0 to 31); +signal t2_events, t2_events_in : std_ulogic_vector(0 to 31); +signal t3_events, t3_events_in : std_ulogic_vector(0 to 31); + +begin + +tiup <= '1'; + + +processor_busy_d <= spr_perf_tx_events_q(00) or spr_perf_tx_events_q(08) or spr_perf_tx_events_q(16) or spr_perf_tx_events_q(24); + +br_commit_d <= cpl_perf_tx_events_q(04) or cpl_perf_tx_events_q(04+19) or cpl_perf_tx_events_q(04+38) or cpl_perf_tx_events_q(04+57); +br_mispred_d <= cpl_perf_tx_events_q(05) or cpl_perf_tx_events_q(05+19) or cpl_perf_tx_events_q(05+38) or cpl_perf_tx_events_q(05+57); +br_ta_mispred_d <= cpl_perf_tx_events_q(07) or cpl_perf_tx_events_q(07+19) or cpl_perf_tx_events_q(07+38) or cpl_perf_tx_events_q(07+57); + +t0_events_in <= processor_busy_q & spr_perf_tx_events_q(00 to 07) & cpl_perf_tx_events_q(00 to 18) & byp_perf_tx_events_q(00 to 02) & muldiv_in_use_q; +t1_events_in <= br_commit_q & spr_perf_tx_events_q(08 to 15) & cpl_perf_tx_events_q(19 to 37) & byp_perf_tx_events_q(03 to 05) & muldiv_in_use_q; +t2_events_in <= br_mispred_q & spr_perf_tx_events_q(16 to 23) & cpl_perf_tx_events_q(38 to 56) & byp_perf_tx_events_q(06 to 08) & muldiv_in_use_q; +t3_events_in <= br_ta_mispred_q & spr_perf_tx_events_q(24 to 31) & cpl_perf_tx_events_q(57 to 75) & byp_perf_tx_events_q(09 to 11) & muldiv_in_use_q; + +t0_events <= t0_events_in and (0 to 31=>event_en_q(0)); +t1_events <= t1_events_in and (0 to 31=>event_en_q(1)); +t2_events <= t2_events_in and (0 to 31=>event_en_q(2)); +t3_events <= t3_events_in and (0 to 31=>event_en_q(3)); + +xu_pc_event_data <= event_data_q; + +event_mux_ctrls_d <= pc_xu_event_mux_ctrls; + +event_en_d <= ( spr_msr_pr and (0 to 3=>pc_event_count_mode_q(0))) or + (not spr_msr_pr and spr_msr_gs and (0 to 3=>pc_event_count_mode_q(1))) or + (not spr_msr_pr and not spr_msr_gs and (0 to 3=>pc_event_count_mode_q(2))); + +xuq_perf_mux1 : entity clib.c_event_mux(c_event_mux) +generic map(events_in => 128) +port map( + vd => vdd, + gd => gnd, + t0_events => t0_events, + t1_events => t1_events, + t2_events => t2_events, + t3_events => t3_events, + select_bits => event_mux_ctrls_q, + event_bits => event_data_d +); + +event_en_latch : tri_rlmreg_p + generic map (width => event_en_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => pc_event_bus_enable_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(event_en_offset to event_en_offset + event_en_q'length-1), + scout => sov(event_en_offset to event_en_offset + event_en_q'length-1), + din => event_en_d, + dout => event_en_q); +event_data_latch : tri_rlmreg_p + generic map (width => event_data_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => pc_event_bus_enable_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(event_data_offset to event_data_offset + event_data_q'length-1), + scout => sov(event_data_offset to event_data_offset + event_data_q'length-1), + din => event_data_d, + dout => event_data_q); +event_mux_ctrls_latch : tri_rlmreg_p + generic map (width => event_mux_ctrls_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => pc_event_bus_enable_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(event_mux_ctrls_offset to event_mux_ctrls_offset + event_mux_ctrls_q'length-1), + scout => sov(event_mux_ctrls_offset to event_mux_ctrls_offset + event_mux_ctrls_q'length-1), + din => event_mux_ctrls_d, + dout => event_mux_ctrls_q); +cpl_perf_tx_events_latch : tri_rlmreg_p + generic map (width => cpl_perf_tx_events_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => pc_event_bus_enable_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(cpl_perf_tx_events_offset to cpl_perf_tx_events_offset + cpl_perf_tx_events_q'length-1), + scout => sov(cpl_perf_tx_events_offset to cpl_perf_tx_events_offset + cpl_perf_tx_events_q'length-1), + din => cpl_perf_tx_events, + dout => cpl_perf_tx_events_q); +spr_perf_tx_events_latch : tri_rlmreg_p + generic map (width => spr_perf_tx_events_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => pc_event_bus_enable_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(spr_perf_tx_events_offset to spr_perf_tx_events_offset + spr_perf_tx_events_q'length-1), + scout => sov(spr_perf_tx_events_offset to spr_perf_tx_events_offset + spr_perf_tx_events_q'length-1), + din => spr_perf_tx_events, + dout => spr_perf_tx_events_q); +byp_perf_tx_events_latch : tri_rlmreg_p + generic map (width => byp_perf_tx_events_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => pc_event_bus_enable_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(byp_perf_tx_events_offset to byp_perf_tx_events_offset + byp_perf_tx_events_q'length-1), + scout => sov(byp_perf_tx_events_offset to byp_perf_tx_events_offset + byp_perf_tx_events_q'length-1), + din => byp_perf_tx_events, + dout => byp_perf_tx_events_q); +muldiv_in_use_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => pc_event_bus_enable_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(muldiv_in_use_offset), + scout => sov(muldiv_in_use_offset), + din => fxa_perf_muldiv_in_use, + dout => muldiv_in_use_q); +processor_busy_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => pc_event_bus_enable_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(processor_busy_offset), + scout => sov(processor_busy_offset), + din => processor_busy_d, + dout => processor_busy_q); +br_commit_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => pc_event_bus_enable_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(br_commit_offset), + scout => sov(br_commit_offset), + din => br_commit_d, + dout => br_commit_q); +br_mispred_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => pc_event_bus_enable_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(br_mispred_offset), + scout => sov(br_mispred_offset), + din => br_mispred_d, + dout => br_mispred_q); +br_ta_mispred_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => pc_event_bus_enable_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(br_ta_mispred_offset), + scout => sov(br_ta_mispred_offset), + din => br_ta_mispred_d, + dout => br_ta_mispred_q); +pc_event_count_mode_latch : tri_rlmreg_p + generic map (width => pc_event_count_mode_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => pc_event_bus_enable_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(pc_event_count_mode_offset to pc_event_count_mode_offset + pc_event_count_mode_q'length-1), + scout => sov(pc_event_count_mode_offset to pc_event_count_mode_offset + pc_event_count_mode_q'length-1), + din => pc_xu_event_count_mode, + dout => pc_event_count_mode_q); +pc_event_bus_enable_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(pc_event_bus_enable_offset), + scout => sov(pc_event_bus_enable_offset), + din => pc_xu_event_bus_enable, + dout => pc_event_bus_enable_q); + +perv_2to1_reg: tri_plat + generic map (width => 2, expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_xu_ccflush_dc, + din(0) => func_sl_thold_2, + din(1) => sg_2, + q(0) => func_sl_thold_1, + q(1) => sg_1); + +perv_1to0_reg: tri_plat + generic map (width => 2, expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_xu_ccflush_dc, + din(0) => func_sl_thold_1, + din(1) => sg_1, + q(0) => func_sl_thold_0, + q(1) => sg_0); + +perv_lcbor_func_sl: tri_lcbor + generic map (expand_type => expand_type) +port map (clkoff_b => clkoff_dc_b, + thold => func_sl_thold_0, + sg => sg_0, + act_dis => '0', + forcee => func_sl_force, + thold_b => func_sl_thold_0_b); + + +siv(0 to siv'right) <= sov(1 to siv'right) & scan_in; +scan_out <= sov(0); + +end architecture xuq_perf; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_perv.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_perv.vhdl new file mode 100644 index 0000000..e9b2b7f --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_perv.vhdl @@ -0,0 +1,395 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee,ibm,support,tri,work; +use ieee.std_logic_1164.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; +use support.power_logic_pkg.all; +use tri.tri_latches_pkg.all; +use work.xuq_pkg.all; + +entity xuq_perv is +generic(expand_type : integer := 2 ); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + an_ac_scan_dis_dc_b : in std_ulogic; + pc_xu_sg_3 : in std_ulogic_vector(0 to 4); + pc_xu_func_sl_thold_3 : in std_ulogic_vector(0 to 4); + pc_xu_func_slp_sl_thold_3 : in std_ulogic_vector(0 to 4); + pc_xu_func_nsl_thold_3 : in std_ulogic; + pc_xu_func_slp_nsl_thold_3 : in std_ulogic; + pc_xu_gptr_sl_thold_3 : in std_ulogic; + pc_xu_abst_sl_thold_3 : in std_ulogic; + pc_xu_abst_slp_sl_thold_3 : in std_ulogic; + pc_xu_regf_sl_thold_3 : in std_ulogic; + pc_xu_regf_slp_sl_thold_3 : in std_ulogic; + pc_xu_time_sl_thold_3 : in std_ulogic; + pc_xu_cfg_sl_thold_3 : in std_ulogic; + pc_xu_cfg_slp_sl_thold_3 : in std_ulogic; + pc_xu_ary_nsl_thold_3 : in std_ulogic; + pc_xu_ary_slp_nsl_thold_3 : in std_ulogic; + pc_xu_repr_sl_thold_3 : in std_ulogic; + pc_xu_bolt_sl_thold_3 : in std_ulogic; + pc_xu_bo_enable_3 : in std_ulogic; + pc_xu_fce_3 : in std_ulogic_vector(0 to 1); + pc_xu_ccflush_dc : in std_ulogic; + an_ac_scan_diag_dc : in std_ulogic; + sg_2 : out std_ulogic_vector(0 to 3); + fce_2 : out std_ulogic_vector(0 to 1); + func_sl_thold_2 : out std_ulogic_vector(0 to 3); + func_slp_sl_thold_2 : out std_ulogic_vector(0 to 1); + func_nsl_thold_2 : out std_ulogic; + func_slp_nsl_thold_2 : out std_ulogic; + abst_sl_thold_2 : out std_ulogic; + abst_slp_sl_thold_2 : out std_ulogic; + regf_sl_thold_2 : out std_ulogic; + regf_slp_sl_thold_2 : out std_ulogic; + time_sl_thold_2 : out std_ulogic; + gptr_sl_thold_2 : out std_ulogic; + ary_nsl_thold_2 : out std_ulogic; + ary_slp_nsl_thold_2 : out std_ulogic; + repr_sl_thold_2 : out std_ulogic; + cfg_sl_thold_2 : out std_ulogic; + cfg_slp_sl_thold_2 : out std_ulogic; + bolt_sl_thold_2 : out std_ulogic; + bo_enable_2 : out std_ulogic; + sg_0 : out std_ulogic; + sg_1 : out std_ulogic; + ary_nsl_thold_0 : out std_ulogic; + abst_sl_thold_0 : out std_ulogic; + time_sl_thold_0 : out std_ulogic; + repr_sl_thold_0 : out std_ulogic; + clkoff_dc_b : out std_ulogic; + d_mode_dc : out std_ulogic; + delay_lclkr_dc : out std_ulogic_vector(0 to 4); + mpw1_dc_b : out std_ulogic_vector(0 to 4); + mpw2_dc_b : out std_ulogic; + g6t_clkoff_dc_b : out std_ulogic; + g6t_d_mode_dc : out std_ulogic; + g6t_delay_lclkr_dc : out std_ulogic_vector(0 to 4); + g6t_mpw1_dc_b : out std_ulogic_vector(0 to 4); + g6t_mpw2_dc_b : out std_ulogic; + g8t_clkoff_dc_b : out std_ulogic; + g8t_d_mode_dc : out std_ulogic; + g8t_delay_lclkr_dc : out std_ulogic_vector(0 to 4); + g8t_mpw1_dc_b : out std_ulogic_vector(0 to 4); + g8t_mpw2_dc_b : out std_ulogic; + cam_clkoff_dc_b : out std_ulogic; + cam_d_mode_dc : out std_ulogic; + cam_delay_lclkr_dc : out std_ulogic_vector(0 to 4); + cam_act_dis_dc : out std_ulogic; + cam_mpw1_dc_b : out std_ulogic_vector(0 to 4); + cam_mpw2_dc_b : out std_ulogic; + gptr_scan_in : in std_ulogic; + gptr_scan_out : out std_ulogic +); + +-- synopsys translate_off +-- synopsys translate_on + +end xuq_perv; +architecture xuq_perv of xuq_perv is + +signal gptr_sov, gptr_siv : std_ulogic_vector(0 to 3); +signal perv_sg_2 : std_ulogic_vector(0 to 3); +signal perv_sg_2_b : std_ulogic_vector(0 to 3); +signal gptr_sl_thold_2_int : std_ulogic; +signal gptr_sl_thold_2_int_b : std_ulogic; +signal gptr_sl_thold_1, sg_1_int : std_ulogic; +signal gptr_sl_thold_0, sg_0_int : std_ulogic; +signal time_sl_thold_0_int : std_ulogic; +signal ary_nsl_thold_2_int : std_ulogic; +signal ary_nsl_thold_2_int_b : std_ulogic; +signal ary_slp_nsl_thold_2_int : std_ulogic; +signal abst_sl_thold_2_int : std_ulogic; +signal abst_sl_thold_2_int_b : std_ulogic; +signal abst_slp_sl_thold_2_int : std_ulogic; +signal regf_sl_thold_2_int : std_ulogic; +signal regf_slp_sl_thold_2_int : std_ulogic; +signal func_slp_nsl_thold_2_int : std_ulogic; +signal time_sl_thold_2_int : std_ulogic; +signal time_sl_thold_2_int_b : std_ulogic; +signal repr_sl_thold_2_int : std_ulogic; +signal repr_sl_thold_2_int_b : std_ulogic; +signal ary_nsl_thold_1 : std_ulogic; +signal abst_sl_thold_1 : std_ulogic; +signal time_sl_thold_1 : std_ulogic; +signal repr_sl_thold_1 : std_ulogic; +signal func_sl_thold_2_int : std_ulogic_vector(0 to 3); +signal bolt_sl_thold_2_int : std_ulogic; +signal bo_enable_2_int : std_ulogic; +signal fce_2_int : std_ulogic_vector(0 to 1); +signal func_slp_sl_thold_2_int : std_ulogic_vector(0 to 1); +signal cfg_sl_thold_2_int : std_ulogic; +signal cfg_slp_sl_thold_2_int : std_ulogic; +signal func_nsl_thold_2_int : std_ulogic; +signal clkoff_dc_b_int : std_ulogic; +signal d_mode_dc_int : std_ulogic; +signal delay_lclkr_dc_int : std_ulogic_vector(0 to 4); +signal mpw1_dc_b_int : std_ulogic_vector(0 to 4); +signal mpw2_dc_b_int : std_ulogic; +signal g6t_clkoff_dc_b_int : std_ulogic; +signal g6t_d_mode_dc_int : std_ulogic; +signal g6t_delay_lclkr_dc_int : std_ulogic_vector(0 to 4); +signal g6t_mpw1_dc_b_int : std_ulogic_vector(0 to 4); +signal g6t_mpw2_dc_b_int : std_ulogic; +signal g8t_clkoff_dc_b_int : std_ulogic; +signal g8t_d_mode_dc_int : std_ulogic; +signal g8t_delay_lclkr_dc_int : std_ulogic_vector(0 to 4); +signal g8t_mpw1_dc_b_int : std_ulogic_vector(0 to 4); +signal g8t_mpw2_dc_b_int : std_ulogic; +signal cam_clkoff_dc_b_int : std_ulogic; +signal cam_d_mode_dc_int : std_ulogic; +signal cam_delay_lclkr_dc_int : std_ulogic_vector(0 to 4); +signal cam_mpw1_dc_b_int : std_ulogic_vector(0 to 4); +signal cam_mpw2_dc_b_int : std_ulogic; + +begin + +perv_3to2_reg: tri_plat + generic map (width => 27, expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_xu_ccflush_dc, + din(0 to 3) => pc_xu_func_sl_thold_3(0 to 3), + din(4 to 5) => pc_xu_func_slp_sl_thold_3(0 to 1), + din(6) => pc_xu_gptr_sl_thold_3, + din(7 to 10) => pc_xu_sg_3(0 to 3), + din(11 to 12) => pc_xu_fce_3(0 to 1), + din(13) => pc_xu_func_nsl_thold_3, + din(14) => pc_xu_abst_sl_thold_3, + din(15) => pc_xu_abst_slp_sl_thold_3, + din(16) => pc_xu_time_sl_thold_3, + din(17) => pc_xu_ary_nsl_thold_3, + din(18) => pc_xu_ary_slp_nsl_thold_3, + din(19) => pc_xu_cfg_sl_thold_3, + din(20) => pc_xu_cfg_slp_sl_thold_3, + din(21) => pc_xu_repr_sl_thold_3, + din(22) => pc_xu_regf_sl_thold_3, + din(23) => pc_xu_regf_slp_sl_thold_3, + din(24) => pc_xu_func_slp_nsl_thold_3, + din(25) => pc_xu_bolt_sl_thold_3, + din(26) => pc_xu_bo_enable_3, + q(0 to 3) => func_sl_thold_2_int(0 to 3), + q(4 to 5) => func_slp_sl_thold_2_int(0 to 1), + q(6) => gptr_sl_thold_2_int, + q(7 to 10) => perv_sg_2(0 to 3), + q(11 to 12) => fce_2_int(0 to 1), + q(13) => func_nsl_thold_2_int, + q(14) => abst_sl_thold_2_int, + q(15) => abst_slp_sl_thold_2_int, + q(16) => time_sl_thold_2_int, + q(17) => ary_nsl_thold_2_int, + q(18) => ary_slp_nsl_thold_2_int, + q(19) => cfg_sl_thold_2_int, + q(20) => cfg_slp_sl_thold_2_int, + q(21) => repr_sl_thold_2_int, + q(22) => regf_sl_thold_2_int, + q(23) => regf_slp_sl_thold_2_int, + q(24) => func_slp_nsl_thold_2_int, + q(25) => bolt_sl_thold_2_int, + q(26) => bo_enable_2_int); + +sg_2 <= perv_sg_2; +perv_sg_2_b <= perv_sg_2; +sg_1 <= sg_1_int; +sg_0 <= sg_0_int; + +ary_nsl_thold_2 <= ary_nsl_thold_2_int; +ary_nsl_thold_2_int_b<= ary_nsl_thold_2_int; +ary_slp_nsl_thold_2 <= ary_slp_nsl_thold_2_int; +abst_sl_thold_2 <= abst_sl_thold_2_int; +abst_sl_thold_2_int_b <= abst_sl_thold_2_int; +abst_slp_sl_thold_2 <= abst_slp_sl_thold_2_int; +regf_sl_thold_2 <= regf_sl_thold_2_int; +regf_slp_sl_thold_2 <= regf_slp_sl_thold_2_int; +time_sl_thold_2 <= time_sl_thold_2_int; +time_sl_thold_2_int_b <= time_sl_thold_2_int; +repr_sl_thold_2 <= repr_sl_thold_2_int; +repr_sl_thold_2_int_b <= repr_sl_thold_2_int; +func_sl_thold_2 <= func_sl_thold_2_int; +bolt_sl_thold_2 <= bolt_sl_thold_2_int; +bo_enable_2 <= bo_enable_2_int; +fce_2 <= fce_2_int; +func_slp_sl_thold_2 <= func_slp_sl_thold_2_int; +cfg_sl_thold_2 <= cfg_sl_thold_2_int; +cfg_slp_sl_thold_2 <= cfg_slp_sl_thold_2_int; +func_nsl_thold_2 <= func_nsl_thold_2_int; +func_slp_nsl_thold_2 <= func_slp_nsl_thold_2_int; +clkoff_dc_b <= clkoff_dc_b_int; +d_mode_dc <= d_mode_dc_int; +delay_lclkr_dc <= delay_lclkr_dc_int; +mpw1_dc_b <= mpw1_dc_b_int; +mpw2_dc_b <= mpw2_dc_b_int; +time_sl_thold_0 <= time_sl_thold_0_int; + +g6t_clkoff_dc_b <= g6t_clkoff_dc_b_int; +g6t_d_mode_dc <= g6t_d_mode_dc_int; +g6t_delay_lclkr_dc <= g6t_delay_lclkr_dc_int; +g6t_mpw1_dc_b <= g6t_mpw1_dc_b_int; +g6t_mpw2_dc_b <= g6t_mpw2_dc_b_int; + +g8t_clkoff_dc_b <= g8t_clkoff_dc_b_int; +g8t_d_mode_dc <= g8t_d_mode_dc_int; +g8t_delay_lclkr_dc <= g8t_delay_lclkr_dc_int; +g8t_mpw1_dc_b <= g8t_mpw1_dc_b_int; +g8t_mpw2_dc_b <= g8t_mpw2_dc_b_int; + +cam_clkoff_dc_b <= cam_clkoff_dc_b_int; +cam_delay_lclkr_dc <= cam_delay_lclkr_dc_int; +cam_act_dis_dc <= '0'; +cam_d_mode_dc <= cam_d_mode_dc_int; +cam_mpw1_dc_b <= cam_mpw1_dc_b_int; +cam_mpw2_dc_b <= cam_mpw2_dc_b_int; + +gptr_sl_thold_2 <= gptr_sl_thold_2_int; +gptr_sl_thold_2_int_b <= gptr_sl_thold_2_int; + +perv_2to1_reg: tri_plat + generic map (width => 6, expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_xu_ccflush_dc, + din(0) => gptr_sl_thold_2_int_b, + din(1) => perv_sg_2_b(0), + din(2) => ary_nsl_thold_2_int_b, + din(3) => abst_sl_thold_2_int_b, + din(4) => time_sl_thold_2_int_b, + din(5) => repr_sl_thold_2_int_b, + q(0) => gptr_sl_thold_1, + q(1) => sg_1_int, + q(2) => ary_nsl_thold_1, + q(3) => abst_sl_thold_1, + q(4) => time_sl_thold_1, + q(5) => repr_sl_thold_1); + +perv_1to0_reg: tri_plat + generic map (width => 6, expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_xu_ccflush_dc, + din(0) => gptr_sl_thold_1, + din(1) => sg_1_int, + din(2) => ary_nsl_thold_1, + din(3) => abst_sl_thold_1, + din(4) => time_sl_thold_1, + din(5) => repr_sl_thold_1, + q(0) => gptr_sl_thold_0, + q(1) => sg_0_int, + q(2) => ary_nsl_thold_0, + q(3) => abst_sl_thold_0, + q(4) => time_sl_thold_0_int, + q(5) => repr_sl_thold_0); + +perv_lcbctrl_0: tri_lcbcntl_mac + generic map (expand_type => expand_type) +port map ( + vdd => vdd, + gnd => gnd, + sg => sg_0_int, + nclk => nclk, + scan_in => gptr_siv(3), + scan_diag_dc => an_ac_scan_diag_dc, + thold => gptr_sl_thold_0, + clkoff_dc_b => clkoff_dc_b_int, + delay_lclkr_dc => delay_lclkr_dc_int(0 to 4), + act_dis_dc => open, + d_mode_dc => d_mode_dc_int, + mpw1_dc_b => mpw1_dc_b_int(0 to 4), + mpw2_dc_b => mpw2_dc_b_int, + scan_out => gptr_sov(3)); + +perv_lcbctrl_g6t_0: tri_lcbcntl_array_mac + generic map (expand_type => expand_type) +port map ( + vdd => vdd, + gnd => gnd, + sg => sg_0_int, + nclk => nclk, + scan_in => gptr_siv(0), + scan_diag_dc => an_ac_scan_diag_dc, + thold => gptr_sl_thold_0, + clkoff_dc_b => g6t_clkoff_dc_b_int, + delay_lclkr_dc => g6t_delay_lclkr_dc_int(0 to 4), + act_dis_dc => open, + d_mode_dc => g6t_d_mode_dc_int, + mpw1_dc_b => g6t_mpw1_dc_b_int(0 to 4), + mpw2_dc_b => g6t_mpw2_dc_b_int, + scan_out => gptr_sov(0)); + +perv_lcbctrl_g8t_0: tri_lcbcntl_array_mac + generic map (expand_type => expand_type) +port map ( + vdd => vdd, + gnd => gnd, + sg => sg_0_int, + nclk => nclk, + scan_in => gptr_siv(1), + scan_diag_dc => an_ac_scan_diag_dc, + thold => gptr_sl_thold_0, + clkoff_dc_b => g8t_clkoff_dc_b_int, + delay_lclkr_dc => g8t_delay_lclkr_dc_int(0 to 4), + act_dis_dc => open, + d_mode_dc => g8t_d_mode_dc_int, + mpw1_dc_b => g8t_mpw1_dc_b_int(0 to 4), + mpw2_dc_b => g8t_mpw2_dc_b_int, + scan_out => gptr_sov(1)); + +perv_lcbctrl_cam_0: tri_lcbcntl_array_mac + generic map (expand_type => expand_type) +port map ( + vdd => vdd, + gnd => gnd, + sg => sg_0_int, + nclk => nclk, + scan_in => gptr_siv(2), + scan_diag_dc => an_ac_scan_diag_dc, + thold => gptr_sl_thold_0, + clkoff_dc_b => cam_clkoff_dc_b_int, + delay_lclkr_dc => cam_delay_lclkr_dc_int(0 to 4), + act_dis_dc => open, + d_mode_dc => cam_d_mode_dc_int, + mpw1_dc_b => cam_mpw1_dc_b_int(0 to 4), + mpw2_dc_b => cam_mpw2_dc_b_int, + scan_out => gptr_sov(2)); + +gptr_siv(0 to gptr_siv'right) <= gptr_sov(1 to gptr_siv'right) & gptr_scan_in; +gptr_scan_out <= gptr_sov(0) and an_ac_scan_dis_dc_b; + +mark_unused(pc_xu_func_sl_thold_3(4)); +mark_unused(pc_xu_func_slp_sl_thold_3(2 to 4)); +mark_unused(pc_xu_sg_3(4)); + +end xuq_perv; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_pkg.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_pkg.vhdl new file mode 100644 index 0000000..f1da692 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_pkg.vhdl @@ -0,0 +1,144 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee,ibm; +use ieee.std_logic_1164.all; + +package xuq_pkg is + subtype s1 is std_ulogic; + subtype s2 is std_ulogic_vector(0 to 1); + subtype s3 is std_ulogic_vector(0 to 2); + subtype s4 is std_ulogic_vector(0 to 3); + subtype s5 is std_ulogic_vector(0 to 4); + subtype s6 is std_ulogic_vector(0 to 5); + subtype s7 is std_ulogic_vector(0 to 6); + + function fanout(in0 : std_ulogic; size : natural) return std_ulogic_vector; + function fanout(in0 : std_ulogic_vector; size : natural) return std_ulogic_vector; + function encode( input : std_ulogic_vector) return std_ulogic_vector; + function or_reduce_t(in0 : std_ulogic_vector; threads : integer) return std_ulogic_vector; + function mux_t(in0 : std_ulogic_vector; gate : std_ulogic_vector) return std_ulogic_vector; + procedure mark_unused(input : std_ulogic); + procedure mark_unused(input : std_ulogic_vector); + + +end xuq_pkg; + +package body xuq_pkg is + + procedure mark_unused(input : std_ulogic) is + variable unused : std_ulogic; + -- synopsys translate_off + -- synopsys translate_on + begin + unused := input; + end mark_unused; + + procedure mark_unused(input : std_ulogic_vector) is + variable unused : std_ulogic_vector(input'range); + -- synopsys translate_off + -- synopsys translate_on + begin + unused := input; + end mark_unused; + + + function fanout(in0 : std_ulogic_vector; size : natural) return std_ulogic_vector is + variable result : std_ulogic_vector(0 to size-1); + variable fan : natural; + begin + fan := in0'length; + for i in 0 to size-1 loop + result(i) := in0(i mod fan); + end loop; + return result; + end fanout; + + function fanout(in0 : std_ulogic; size : natural) return std_ulogic_vector is + variable result : std_ulogic_vector(0 to size-1); + begin + result := (others=>in0); + return result; + end fanout; + + + function mux_t(in0 : std_ulogic_vector; gate : std_ulogic_vector) return std_ulogic_vector is + variable in1 : std_ulogic_vector(0 to in0'length-1); + variable result : std_ulogic_vector(0 to in0'length/gate'length-1); + begin + + in1 := in0; + result := (others=>'0'); + for i in 0 to result'length-1 loop + for t in 0 to gate'length-1 loop + result(i) := result(i) or (in1(i+t*result'length) and gate(t)); + end loop; + end loop; + return result; + end mux_t; + + function or_reduce_t(in0 : std_ulogic_vector; threads : integer) return std_ulogic_vector is + variable in1 : std_ulogic_vector(0 to in0'length-1); + variable result : std_ulogic_vector(0 to in0'length/threads-1); + begin + in1 := in0; + result := (others=>'0'); + for i in 0 to result'length-1 loop + for t in 0 to threads-1 loop + result(i) := result(i) or in1(i+t*result'length); + end loop; + end loop; + return result; + end or_reduce_t; + + + function encode( input : std_ulogic_vector) return std_ulogic_vector is + variable result : std_ulogic_vector(3 downto 0); + begin + if (input'length = 1) then + return("0"); + elsif (input'length = 2) then + return(input(input'right to input'right)); + elsif (input'length = 4) then + case s4'(input) is + when "0001" => result := "0011"; + when "0010" => result := "0010"; + when "0100" => result := "0001"; + when others => result := "0000"; + end case; + return(result(1 downto 0)); + else + assert (TRUE) + report "Length field is too large" + severity error; + return("X"); + end if; + end; + +end xuq_pkg; + diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_spr.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_spr.vhdl new file mode 100644 index 0000000..1c83c08 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_spr.vhdl @@ -0,0 +1,1608 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee,ibm,support,work,tri,clib; +use ieee.std_logic_1164.all; +use support.power_logic_pkg.all; +use ibm.std_ulogic_function_support.all; +use tri.tri_latches_pkg.all; + +entity xuq_spr is +generic( + hvmode : integer := 1; + a2mode : integer := 1; + expand_type : integer := 2; + threads : integer := 4; + regsize : integer := 64; + eff_ifar : integer := 62; + spr_xucr0_init_mod : integer := 0); +port( + nclk : in clk_logic; + + an_ac_coreid : in std_ulogic_vector(54 to 61); + spr_pvr_version_dc : in std_ulogic_vector(8 to 15); + spr_pvr_revision_dc : in std_ulogic_vector(12 to 15); + an_ac_ext_interrupt : in std_ulogic_vector(0 to threads-1); + an_ac_crit_interrupt : in std_ulogic_vector(0 to threads-1); + an_ac_perf_interrupt : in std_ulogic_vector(0 to threads-1); + an_ac_reservation_vld : in std_ulogic_vector(0 to threads-1); + an_ac_tb_update_pulse : in std_ulogic; + an_ac_tb_update_enable : in std_ulogic; + an_ac_sleep_en : in std_ulogic_vector(0 to threads-1); + an_ac_hang_pulse : in std_ulogic_vector(0 to threads-1); + ac_tc_machine_check : out std_ulogic_vector(0 to threads-1); + an_ac_external_mchk : in std_ulogic_vector(0 to threads-1); + pc_xu_instr_trace_mode : in std_ulogic; + pc_xu_instr_trace_tid : in std_ulogic_vector(0 to 1); + + an_ac_scan_dis_dc_b : in std_ulogic; + an_ac_scan_diag_dc : in std_ulogic; + pc_xu_ccflush_dc : in std_ulogic; + clkoff_dc_b : in std_ulogic; + d_mode_dc : in std_ulogic; + delay_lclkr_dc : in std_ulogic; + mpw1_dc_b : in std_ulogic; + mpw2_dc_b : in std_ulogic; + func_sl_thold_2 : in std_ulogic; + func_slp_sl_thold_2 : in std_ulogic; + func_nsl_thold_2 : in std_ulogic; + func_slp_nsl_thold_2 : in std_ulogic; + cfg_sl_thold_2 : in std_ulogic; + cfg_slp_sl_thold_2 : in std_ulogic; + ary_nsl_thold_2 : in std_ulogic; + time_sl_thold_2 : in std_ulogic; + abst_sl_thold_2 : in std_ulogic; + repr_sl_thold_2 : in std_ulogic; + gptr_sl_thold_2 : in std_ulogic; + bolt_sl_thold_2 : in std_ulogic; + sg_2 : in std_ulogic; + fce_2 : in std_ulogic; + func_scan_in : in std_ulogic_vector(0 to threads+1); + func_scan_out : out std_ulogic_vector(0 to threads+1); + bcfg_scan_in : in std_ulogic; + bcfg_scan_out : out std_ulogic; + ccfg_scan_in : in std_ulogic; + ccfg_scan_out : out std_ulogic; + dcfg_scan_in : in std_ulogic; + dcfg_scan_out : out std_ulogic; + time_scan_in : in std_ulogic; + time_scan_out : out std_ulogic; + abst_scan_in : in std_ulogic; + abst_scan_out : out std_ulogic; + repr_scan_in : in std_ulogic; + repr_scan_out : out std_ulogic; + gptr_scan_in : in std_ulogic; + gptr_scan_out : out std_ulogic; + + dec_spr_rf0_tid : in std_ulogic_vector(0 to threads-1); + dec_spr_rf0_instr : in std_ulogic_vector(0 to 31); + dec_spr_rf1_val : in std_ulogic_vector(0 to threads-1); + dec_spr_ex1_epid_instr : in std_ulogic; + dec_spr_ex4_val : in std_ulogic_vector(0 to threads-1); + + spr_byp_ex3_spr_rt : out std_ulogic_vector(64-regsize to 63); + + fxu_spr_ex1_rs2 : in std_ulogic_vector(42 to 55); + + fxu_spr_ex1_rs0 : in std_ulogic_vector(52 to 63); + fxu_spr_ex1_rs1 : in std_ulogic_vector(54 to 63); + mux_spr_ex2_rt : in std_ulogic_vector(64-regsize to 63); + + cpl_spr_ex5_act : in std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_int : in std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_gint : in std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_cint : in std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_mcint : in std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_nia : in std_ulogic_vector(0 to eff_ifar*threads-1); + cpl_spr_ex5_esr : in std_ulogic_vector(0 to 17*threads-1); + cpl_spr_ex5_mcsr : in std_ulogic_vector(0 to 15*threads-1); + cpl_spr_ex5_dbsr : in std_ulogic_vector(0 to 19*threads-1); + cpl_spr_ex5_dear_update : in std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_dear_update_saved : in std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_dear_save : in std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_dbsr_update : in std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_esr_update : in std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_srr0_dec : in std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_force_gsrr : in std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_dbsr_ide : in std_ulogic_vector(0 to threads-1); + spr_cpl_dbsr_ide : out std_ulogic_vector(0 to threads-1); + + spr_cpl_external_mchk : out std_ulogic_vector(0 to threads-1); + spr_cpl_ext_interrupt : out std_ulogic_vector(0 to threads-1); + spr_cpl_dec_interrupt : out std_ulogic_vector(0 to threads-1); + spr_cpl_udec_interrupt : out std_ulogic_vector(0 to threads-1); + spr_cpl_perf_interrupt : out std_ulogic_vector(0 to threads-1); + spr_cpl_fit_interrupt : out std_ulogic_vector(0 to threads-1); + spr_cpl_crit_interrupt : out std_ulogic_vector(0 to threads-1); + spr_cpl_wdog_interrupt : out std_ulogic_vector(0 to threads-1); + spr_cpl_dbell_interrupt : out std_ulogic_vector(0 to threads-1); + spr_cpl_cdbell_interrupt : out std_ulogic_vector(0 to threads-1); + spr_cpl_gdbell_interrupt : out std_ulogic_vector(0 to threads-1); + spr_cpl_gcdbell_interrupt : out std_ulogic_vector(0 to threads-1); + spr_cpl_gmcdbell_interrupt : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_dbell_taken : in std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_cdbell_taken : in std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_gdbell_taken : in std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_gcdbell_taken : in std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_gmcdbell_taken : in std_ulogic_vector(0 to threads-1); + + lsu_xu_dbell_val : in std_ulogic; + lsu_xu_dbell_type : in std_ulogic_vector(0 to 4); + lsu_xu_dbell_brdcast : in std_ulogic; + lsu_xu_dbell_lpid_match : in std_ulogic; + lsu_xu_dbell_pirtag : in std_ulogic_vector(50 to 63); + + xu_lsu_slowspr_val : out std_ulogic; + xu_lsu_slowspr_rw : out std_ulogic; + xu_lsu_slowspr_etid : out std_ulogic_vector(0 to 1); + xu_lsu_slowspr_addr : out std_ulogic_vector(11 to 20); + xu_lsu_slowspr_data : out std_ulogic_vector(64-regsize to 63); + + ac_an_dcr_act : out std_ulogic; + ac_an_dcr_val : out std_ulogic; + ac_an_dcr_read : out std_ulogic; + ac_an_dcr_user : out std_ulogic; + ac_an_dcr_etid : out std_ulogic_vector(0 to 1); + ac_an_dcr_addr : out std_ulogic_vector(11 to 20); + ac_an_dcr_data : out std_ulogic_vector(64-regsize to 63); + + xu_ex4_flush : in std_ulogic_vector(0 to threads-1); + xu_ex5_flush : in std_ulogic_vector(0 to threads-1); + + spr_cpl_fp_precise : out std_ulogic_vector(0 to threads-1); + spr_cpl_ex3_spr_hypv : out std_ulogic; + spr_cpl_ex3_spr_illeg : out std_ulogic; + spr_cpl_ex3_spr_priv : out std_ulogic; + spr_cpl_ex3_ct_le : out std_ulogic_vector(0 to threads-1); + spr_cpl_ex3_ct_be : out std_ulogic_vector(0 to threads-1); + + cpl_spr_stop : in std_ulogic_vector(0 to threads-1); + xu_pc_running : out std_ulogic_vector(0 to threads-1); + xu_iu_run_thread : out std_ulogic_vector(0 to threads-1); + xu_iu_single_instr_mode : out std_ulogic_vector(0 to threads-1); + xu_iu_raise_iss_pri : out std_ulogic_vector(0 to threads-1); + spr_cpl_ex2_run_ctl_flush : out std_ulogic_vector(0 to threads-1); + xu_pc_spr_ccr0_we : out std_ulogic_vector(0 to threads-1); + + iu_xu_quiesce : in std_ulogic_vector(0 to threads-1); + lsu_xu_quiesce : in std_ulogic_vector(0 to threads-1); + mm_xu_quiesce : in std_ulogic_vector(0 to threads-1); + bx_xu_quiesce : in std_ulogic_vector(0 to threads-1); + cpl_spr_quiesce : in std_ulogic_vector(0 to threads-1); + spr_cpl_quiesce : out std_ulogic_vector(0 to threads-1); + + pc_xu_extirpts_dis_on_stop : in std_ulogic; + pc_xu_timebase_dis_on_stop : in std_ulogic; + pc_xu_decrem_dis_on_stop : in std_ulogic; + + pc_xu_ram_mode : in std_ulogic; + pc_xu_ram_thread : in std_ulogic_vector(0 to 1); + pc_xu_msrovride_enab : in std_ulogic; + pc_xu_msrovride_pr : in std_ulogic; + pc_xu_msrovride_gs : in std_ulogic; + pc_xu_msrovride_de : in std_ulogic; + + cpl_spr_ex5_instr_cpl : in std_ulogic_vector(0 to threads-1); + xu_pc_err_llbust_attempt : out std_ulogic_vector(0 to threads-1); + xu_pc_err_llbust_failed : out std_ulogic_vector(0 to threads-1); + + spr_byp_ex4_is_mtxer : out std_ulogic_vector(0 to threads-1); + spr_byp_ex4_is_mfxer : out std_ulogic_vector(0 to threads-1); + + pc_xu_reset_wd_complete : in std_ulogic; + pc_xu_reset_1_complete : in std_ulogic; + pc_xu_reset_2_complete : in std_ulogic; + pc_xu_reset_3_complete : in std_ulogic; + ac_tc_reset_1_request : out std_ulogic; + ac_tc_reset_2_request : out std_ulogic; + ac_tc_reset_3_request : out std_ulogic; + ac_tc_reset_wd_request : out std_ulogic; + + pc_xu_inj_llbust_attempt : in std_ulogic_vector(0 to threads-1); + pc_xu_inj_llbust_failed : in std_ulogic_vector(0 to threads-1); + pc_xu_inj_wdt_reset : in std_ulogic_vector(0 to threads-1); + xu_pc_err_wdt_reset : out std_ulogic_vector(0 to threads-1); + + spr_cpl_ex3_sprg_ce : out std_ulogic; + spr_cpl_ex3_sprg_ue : out std_ulogic; + pc_xu_inj_sprg_ecc : in std_ulogic_vector(0 to threads-1); + xu_pc_err_sprg_ecc : out std_ulogic_vector(0 to threads-1); + + spr_perf_tx_events : out std_ulogic_vector(0 to 8*threads-1); + xu_lsu_mtspr_trace_en : out std_ulogic_vector(0 to threads-1); + + cpl_spr_dbcr0_edm : in std_ulogic_vector(0 to threads-1); + spr_bit_act : out std_ulogic; + spr_xucr0_clkg_ctl : out std_ulogic_vector(0 to 3); + spr_cpl_iac1_en : out std_ulogic_vector(0 to threads-1); + spr_cpl_iac2_en : out std_ulogic_vector(0 to threads-1); + spr_cpl_iac3_en : out std_ulogic_vector(0 to threads-1); + spr_cpl_iac4_en : out std_ulogic_vector(0 to threads-1); + lsu_xu_spr_xucr0_cslc_xuop : in std_ulogic; + lsu_xu_spr_xucr0_cslc_binv : in std_ulogic; + lsu_xu_spr_xucr0_clo : in std_ulogic; + lsu_xu_spr_xucr0_cul : in std_ulogic; + lsu_xu_spr_epsc_egs : in std_ulogic_vector(0 to threads-1); + lsu_xu_spr_epsc_epr : in std_ulogic_vector(0 to threads-1); + spr_epcr_extgs : out std_ulogic_vector(0 to threads-1); + spr_msr_de : out std_ulogic_vector(0 to threads-1); + spr_msr_pr : out std_ulogic_vector(0 to threads-1); + spr_msr_is : out std_ulogic_vector(0 to threads-1); + spr_msr_cm : out std_ulogic_vector(0 to threads-1); + spr_msr_gs : out std_ulogic_vector(0 to threads-1); + spr_msr_ee : out std_ulogic_vector(0 to threads-1); + spr_msr_ce : out std_ulogic_vector(0 to threads-1); + spr_msr_me : out std_ulogic_vector(0 to threads-1); + xu_lsu_spr_xucr0_clfc : out std_ulogic; + xu_pc_spr_ccr0_pme : out std_ulogic_vector(0 to 1); + spr_ccr2_en_dcr : out std_ulogic; + spr_ccr2_en_pc : out std_ulogic; + xu_iu_spr_ccr2_ifratsc : out std_ulogic_vector(0 to 8); + xu_iu_spr_ccr2_ifrat : out std_ulogic; + xu_lsu_spr_ccr2_dfratsc : out std_ulogic_vector(0 to 8); + xu_lsu_spr_ccr2_dfrat : out std_ulogic; + spr_ccr2_ucode_dis : out std_ulogic; + spr_ccr2_ap : out std_ulogic_vector(0 to 3); + spr_ccr2_en_attn : out std_ulogic; + spr_ccr2_en_ditc : out std_ulogic; + spr_ccr2_en_icswx : out std_ulogic; + spr_ccr2_notlb : out std_ulogic; + xu_lsu_spr_xucr0_mbar_ack : out std_ulogic; + xu_lsu_spr_xucr0_tlbsync : out std_ulogic; + spr_dec_spr_xucr0_ssdly : out std_ulogic_vector(0 to 4); + spr_xucr0_cls : out std_ulogic; + xu_lsu_spr_xucr0_aflsta : out std_ulogic; + spr_xucr0_mddp : out std_ulogic; + xu_lsu_spr_xucr0_cred : out std_ulogic; + xu_lsu_spr_xucr0_rel : out std_ulogic; + spr_xucr0_mdcp : out std_ulogic; + xu_lsu_spr_xucr0_flsta : out std_ulogic; + xu_lsu_spr_xucr0_l2siw : out std_ulogic; + xu_lsu_spr_xucr0_flh2l2 : out std_ulogic; + xu_lsu_spr_xucr0_dcdis : out std_ulogic; + xu_lsu_spr_xucr0_wlk : out std_ulogic; + spr_dbcr0_idm : out std_ulogic_vector(0 to threads-1); + spr_dbcr0_icmp : out std_ulogic_vector(0 to threads-1); + spr_dbcr0_brt : out std_ulogic_vector(0 to threads-1); + spr_dbcr0_irpt : out std_ulogic_vector(0 to threads-1); + spr_dbcr0_trap : out std_ulogic_vector(0 to threads-1); + spr_dbcr0_dac1 : out std_ulogic_vector(0 to 2*threads-1); + spr_dbcr0_dac2 : out std_ulogic_vector(0 to 2*threads-1); + spr_dbcr0_ret : out std_ulogic_vector(0 to threads-1); + spr_dbcr0_dac3 : out std_ulogic_vector(0 to 2*threads-1); + spr_dbcr0_dac4 : out std_ulogic_vector(0 to 2*threads-1); + spr_dbcr1_iac12m : out std_ulogic_vector(0 to threads-1); + spr_dbcr1_iac34m : out std_ulogic_vector(0 to threads-1); + spr_epcr_dtlbgs : out std_ulogic_vector(0 to threads-1); + spr_epcr_itlbgs : out std_ulogic_vector(0 to threads-1); + spr_epcr_dsigs : out std_ulogic_vector(0 to threads-1); + spr_epcr_isigs : out std_ulogic_vector(0 to threads-1); + spr_epcr_duvd : out std_ulogic_vector(0 to threads-1); + spr_epcr_dgtmi : out std_ulogic_vector(0 to threads-1); + xu_mm_spr_epcr_dmiuh : out std_ulogic_vector(0 to threads-1); + spr_msr_ucle : out std_ulogic_vector(0 to threads-1); + spr_msr_spv : out std_ulogic_vector(0 to threads-1); + spr_msr_fp : out std_ulogic_vector(0 to threads-1); + spr_msr_ds : out std_ulogic_vector(0 to threads-1); + spr_msrp_uclep : out std_ulogic_vector(0 to threads-1); + + bo_enable_2 : in std_ulogic; + pc_xu_bo_reset : in std_ulogic; + pc_xu_bo_unload : in std_ulogic; + pc_xu_bo_repair : in std_ulogic; + pc_xu_bo_shdata : in std_ulogic; + pc_xu_bo_select : in std_ulogic; + xu_pc_bo_fail : out std_ulogic; + xu_pc_bo_diagout : out std_ulogic; + an_ac_lbist_ary_wrt_thru_dc : in std_ulogic; + pc_xu_abist_ena_dc : in std_ulogic; + pc_xu_abist_g8t_wenb : in std_ulogic; + pc_xu_abist_waddr_0 : in std_ulogic_vector(4 to 9); + pc_xu_abist_di_0 : in std_ulogic_vector(0 to 3); + pc_xu_abist_g8t1p_renb_0 : in std_ulogic; + pc_xu_abist_raddr_0 : in std_ulogic_vector(4 to 9); + pc_xu_abist_wl32_comp_ena : in std_ulogic; + pc_xu_abist_raw_dc_b : in std_ulogic; + pc_xu_abist_g8t_dcomp : in std_ulogic_vector(0 to 3); + pc_xu_abist_g8t_bw_1 : in std_ulogic; + pc_xu_abist_g8t_bw_0 : in std_ulogic; + + lsu_xu_cmd_debug : in std_ulogic_vector(0 to 175); + pc_xu_trace_bus_enable : in std_ulogic; + spr_debug_mux_ctrls : in std_ulogic_vector(0 to 15); + spr_debug_data_in : in std_ulogic_vector(0 to 87); + spr_debug_data_out : out std_ulogic_vector(0 to 87); + spr_trigger_data_in : in std_ulogic_vector(0 to 11); + spr_trigger_data_out : out std_ulogic_vector(0 to 11); + + vcs : inout power_logic; + vdd : inout power_logic; + gnd : inout power_logic +); + +-- synopsys translate_off + +-- synopsys translate_on +end xuq_spr; +architecture xuq_spr of xuq_spr is + + +signal reset_1_request_q, reset_1_request_d : std_ulogic; +signal reset_2_request_q, reset_2_request_d : std_ulogic; +signal reset_3_request_q, reset_3_request_d : std_ulogic; +signal reset_wd_request_q,reset_wd_request_d : std_ulogic; +signal trace_bus_enable_q : std_ulogic; +signal debug_mux_ctrls_q : std_ulogic_vector(0 to 15); +signal debug_data_out_q, debug_data_out_d : std_ulogic_vector(0 to 87); +signal trigger_data_out_q, trigger_data_out_d : std_ulogic_vector(0 to 11); +constant trace_bus_enable_offset : integer := 0; +constant debug_mux_ctrls_offset : integer := trace_bus_enable_offset + 1; +constant debug_data_out_offset : integer := debug_mux_ctrls_offset + debug_mux_ctrls_q'length; +constant trigger_data_out_offset : integer := debug_data_out_offset + debug_data_out_q'length; +constant xu_spr_cspr_offset : integer := trigger_data_out_offset + trigger_data_out_q'length; +constant scan_right : integer := xu_spr_cspr_offset + 1; +signal siv : std_ulogic_vector(0 to scan_right-1); +signal sov : std_ulogic_vector(0 to scan_right-1); +signal abist_g8t_wenb_q : std_ulogic; +signal abist_waddr_0_q : std_ulogic_vector(4 to 9); +signal abist_di_0_q : std_ulogic_vector(0 to 3); +signal abist_g8t1p_renb_0_q : std_ulogic; +signal abist_raddr_0_q : std_ulogic_vector(4 to 9); +signal abist_wl32_comp_ena_q : std_ulogic; +signal abist_g8t_dcomp_q : std_ulogic_vector(0 to 3); +signal abist_g8t_bw_1_q : std_ulogic; +signal abist_g8t_bw_0_q : std_ulogic; +constant xu_spr_aspr_offset_abst : integer := 1; +constant abist_g8t_wenb_offset_abst : integer := xu_spr_aspr_offset_abst + 1; +constant abist_waddr_0_offset_abst : integer := abist_g8t_wenb_offset_abst + 1; +constant abist_di_0_offset_abst : integer := abist_waddr_0_offset_abst + abist_waddr_0_q'length; +constant abist_g8t1p_renb_0_offset_abst : integer := abist_di_0_offset_abst + abist_di_0_q'length; +constant abist_raddr_0_offset_abst : integer := abist_g8t1p_renb_0_offset_abst + 1; +constant abist_wl32_comp_ena_offset_abst : integer := abist_raddr_0_offset_abst + abist_raddr_0_q'length; +constant abist_g8t_dcomp_offset_abst : integer := abist_wl32_comp_ena_offset_abst + 1; +constant abist_g8t_bw_1_offset_abst : integer := abist_g8t_dcomp_offset_abst + abist_g8t_dcomp_q'length; +constant abist_g8t_bw_0_offset_abst : integer := abist_g8t_bw_1_offset_abst + 1; +constant scan_right_abst : integer := abist_g8t_bw_0_offset_abst + 2; +signal siv_abst : std_ulogic_vector(0 to scan_right_abst-1); +signal sov_abst : std_ulogic_vector(0 to scan_right_abst-1); +signal siv_bcfg : std_ulogic_vector(0 to 2); +signal sov_bcfg : std_ulogic_vector(0 to 2); +signal siv_ccfg : std_ulogic_vector(0 to threads+2); +signal sov_ccfg : std_ulogic_vector(0 to threads+2); +signal siv_dcfg : std_ulogic_vector(0 to threads+1); +signal sov_dcfg : std_ulogic_vector(0 to threads+1); +signal siv_time : std_ulogic_vector(0 to 2); +signal sov_time : std_ulogic_vector(0 to 2); +signal siv_gptr : std_ulogic_vector(0 to 2); +signal sov_gptr : std_ulogic_vector(0 to 2); +signal siv_repr : std_ulogic_vector(0 to 2); +signal sov_repr : std_ulogic_vector(0 to 2); +signal func_scan_rpwr_in : std_ulogic_vector(0 to threads+1); +signal func_scan_rpwr_out : std_ulogic_vector(0 to threads+1); +signal func_scan_gate_out : std_ulogic_vector(0 to threads+1); +signal g8t_clkoff_dc_b : std_ulogic; +signal g8t_d_mode_dc : std_ulogic; +signal g8t_mpw1_dc_b : std_ulogic_vector(0 to 4); +signal g8t_mpw2_dc_b : std_ulogic; +signal g8t_delay_lclkr_dc : std_ulogic_vector(0 to 4); +signal func_slp_nsl_thold_1 : std_ulogic; +signal func_nsl_thold_1 : std_ulogic; +signal func_slp_sl_thold_1 : std_ulogic; +signal func_sl_thold_1 : std_ulogic; +signal time_sl_thold_1 : std_ulogic; +signal abst_sl_thold_1 : std_ulogic; +signal repr_sl_thold_1 : std_ulogic; +signal gptr_sl_thold_1 : std_ulogic; +signal bolt_sl_thold_1 : std_ulogic; +signal ary_nsl_thold_1 : std_ulogic; +signal cfg_sl_thold_1 : std_ulogic; +signal cfg_slp_sl_thold_1 : std_ulogic; +signal fce_1 : std_ulogic; +signal sg_1 : std_ulogic; +signal func_slp_nsl_thold_0 : std_ulogic; +signal func_nsl_thold_0 : std_ulogic_vector(0 to threads); +signal func_slp_sl_thold_0 : std_ulogic_vector(0 to threads); +signal func_sl_thold_0 : std_ulogic_vector(0 to threads); +signal cfg_sl_thold_0 : std_ulogic_vector(0 to threads); +signal cfg_slp_sl_thold_0 : std_ulogic; +signal fce_0 : std_ulogic_vector(0 to threads); +signal sg_0 : std_ulogic_vector(0 to threads); +signal cfg_slp_sl_force : std_ulogic; +signal cfg_slp_sl_thold_0_b : std_ulogic; +signal bcfg_slp_sl_force : std_ulogic; +signal bcfg_slp_sl_thold_0_b : std_ulogic; +signal cfg_sl_force : std_ulogic_vector(0 to threads); +signal cfg_sl_thold_0_b : std_ulogic_vector(0 to threads); +signal bcfg_sl_force : std_ulogic_vector(0 to 0); +signal bcfg_sl_thold_0_b : std_ulogic_vector(0 to 0); +signal ccfg_sl_force : std_ulogic_vector(0 to threads); +signal ccfg_sl_thold_0_b : std_ulogic_vector(0 to threads); +signal dcfg_sl_force : std_ulogic_vector(1 to threads); +signal dcfg_sl_thold_0_b : std_ulogic_vector(1 to threads); +signal func_sl_force : std_ulogic_vector(0 to threads); +signal func_sl_thold_0_b : std_ulogic_vector(0 to threads); +signal func_slp_sl_force : std_ulogic_vector(0 to threads); +signal func_slp_sl_thold_0_b : std_ulogic_vector(0 to threads); +signal func_nsl_force : std_ulogic_vector(0 to threads); +signal func_nsl_thold_0_b : std_ulogic_vector(0 to threads); +signal func_slp_nsl_force : std_ulogic; +signal func_slp_nsl_thold_0_b : std_ulogic; +signal repr_sl_thold_0 : std_ulogic; +signal gptr_sl_thold_0 : std_ulogic; +signal bolt_sl_thold_0 : std_ulogic; +signal time_sl_thold_0 : std_ulogic; +signal abst_sl_force : std_ulogic; +signal abst_sl_thold_0 : std_ulogic; +signal abst_sl_thold_0_b : std_ulogic; +signal ary_nsl_thold_0 : std_ulogic; +signal so_force : std_ulogic; +signal abst_so_thold_0_b : std_ulogic; +signal bcfg_so_thold_0_b : std_ulogic; +signal ccfg_so_thold_0_b : std_ulogic; +signal dcfg_so_thold_0_b : std_ulogic; +signal time_so_thold_0_b : std_ulogic; +signal repr_so_thold_0_b : std_ulogic; +signal gptr_so_thold_0_b : std_ulogic; +signal func_so_thold_0_b : std_ulogic; +signal cspr_tspr_ex1_instr : std_ulogic_vector(0 to 31); +signal cspr_tspr_ex2_tid : std_ulogic_vector(0 to threads-1); +signal cspr_tspr_ex5_is_mtmsr : std_ulogic; +signal cspr_tspr_ex5_is_mtspr : std_ulogic; +signal cspr_tspr_ex5_instr : std_ulogic_vector(11 to 20); +signal cspr_tspr_ex5_is_wrtee : std_ulogic; +signal cspr_tspr_ex5_is_wrteei : std_ulogic; +signal cspr_tspr_timebase_taps : std_ulogic_vector(0 to 9); +signal tspr_cspr_ex3_tspr_rt : std_ulogic_vector(0 to regsize*threads-1); +signal tspr_cspr_illeg_mtspr_b : std_ulogic_vector(0 to threads-1); +signal tspr_cspr_illeg_mfspr_b : std_ulogic_vector(0 to threads-1); +signal tspr_cspr_hypv_mtspr : std_ulogic_vector(0 to threads-1); +signal tspr_cspr_hypv_mfspr : std_ulogic_vector(0 to threads-1); +signal tspr_cspr_freeze_timers : std_ulogic_vector(0 to threads-1); +signal cspr_aspr_ex5_we : std_ulogic; +signal cspr_aspr_ex5_waddr : std_ulogic_vector(0 to 5); +signal cspr_aspr_rf1_re : std_ulogic; +signal cspr_aspr_rf1_raddr : std_ulogic_vector(0 to 5); +signal aspr_cspr_ex1_rdata : std_ulogic_vector(64-regsize to 72-(64/regsize)); +signal cspr_tspr_msrovride_en : std_ulogic_vector(0 to threads-1); +signal cspr_tspr_ram_mode : std_ulogic_vector(0 to threads-1); +signal tspr_epcr_extgs : std_ulogic_vector(0 to threads-1); +signal tspr_msr_de : std_ulogic_vector(0 to threads-1); +signal tspr_msr_pr : std_ulogic_vector(0 to threads-1); +signal tspr_msr_is : std_ulogic_vector(0 to threads-1); +signal tspr_msr_cm : std_ulogic_vector(0 to threads-1); +signal tspr_msr_gs : std_ulogic_vector(0 to threads-1); +signal tspr_msr_ee : std_ulogic_vector(0 to threads-1); +signal tspr_msr_ce : std_ulogic_vector(0 to threads-1); +signal tspr_msr_me : std_ulogic_vector(0 to threads-1); +signal tspr_fp_precise : std_ulogic_vector(0 to threads-1); +signal cspr_tspr_llen : std_ulogic_vector(0 to threads-1); +signal cspr_tspr_llpri : std_ulogic_vector(0 to threads-1); +signal tspr_cspr_lldet : std_ulogic_vector(0 to threads-1); +signal tspr_cspr_llpulse : std_ulogic_vector(0 to threads-1); +signal cspr_tspr_dec_dbg_dis : std_ulogic_vector(0 to threads-1); +signal reset_1_request : std_ulogic_vector(0 to threads-1); +signal reset_2_request : std_ulogic_vector(0 to threads-1); +signal reset_3_request : std_ulogic_vector(0 to threads-1); +signal reset_wd_request : std_ulogic_vector(0 to threads-1); +signal cspr_tspr_crit_mask : std_ulogic_vector(0 to threads-1); +signal cspr_tspr_ext_mask : std_ulogic_vector(0 to threads-1); +signal cspr_tspr_dec_mask : std_ulogic_vector(0 to threads-1); +signal cspr_tspr_fit_mask : std_ulogic_vector(0 to threads-1); +signal cspr_tspr_wdog_mask : std_ulogic_vector(0 to threads-1); +signal cspr_tspr_udec_mask : std_ulogic_vector(0 to threads-1); +signal cspr_tspr_perf_mask : std_ulogic_vector(0 to threads-1); +signal tspr_cspr_pm_wake_up : std_ulogic_vector(0 to threads-1); +signal tspr_cspr_async_int : std_ulogic_vector(0 to 3*threads-1); +signal reset_wd_complete : std_ulogic; +signal reset_1_complete : std_ulogic; +signal reset_2_complete : std_ulogic; +signal reset_3_complete : std_ulogic; +signal timer_update : std_ulogic; +signal cspr_tspr_dbell_pirtag : std_ulogic_vector(50 to 63); +signal tspr_cspr_gpir_match : std_ulogic_vector(0 to threads-1); +signal ex5_spr_wd : std_ulogic_vector(64-regsize to 64+8-(64/regsize)); +signal cspr_tspr_rf1_act : std_ulogic; +signal cspr_xucr0_clkg_ctl : std_ulogic_vector(0 to 4); +signal instr_trace_mode : std_ulogic_vector(0 to threads-1); +signal tspr_debug : std_ulogic_vector(0 to 12*threads-1); +signal cspr_debug0 : std_ulogic_vector(0 to 39); +signal cspr_debug1 : std_ulogic_vector(0 to 87); +signal dbg_group0, dbg_group1 : std_ulogic_vector(0 to 87); +signal dbg_group2, dbg_group3 : std_ulogic_vector(0 to 87); +signal trg_group0, trg_group1 : std_ulogic_vector(0 to 11); +signal trg_group2, trg_group3 : std_ulogic_vector(0 to 11); +signal tidn, tiup : std_ulogic; + +begin + +tidn <= '0'; +tiup <= '1'; + + +spr_epcr_extgs <= tspr_epcr_extgs; +spr_msr_de <= tspr_msr_de; +spr_msr_pr <= tspr_msr_pr; +spr_msr_is <= tspr_msr_is; +spr_msr_cm <= tspr_msr_cm; +spr_msr_gs <= tspr_msr_gs; +spr_msr_ee <= tspr_msr_ee; +spr_msr_ce <= tspr_msr_ce; +spr_msr_me <= tspr_msr_me; +spr_cpl_fp_precise <= tspr_fp_precise; +reset_1_request_d <= or_reduce(reset_1_request); +reset_2_request_d <= or_reduce(reset_2_request); +reset_3_request_d <= or_reduce(reset_3_request); +reset_wd_request_d <= or_reduce(reset_wd_request); +ac_tc_reset_1_request <= reset_1_request_q; +ac_tc_reset_2_request <= reset_2_request_q; +ac_tc_reset_3_request <= reset_3_request_q; +ac_tc_reset_wd_request <= reset_wd_request_q; +spr_xucr0_clkg_ctl <= cspr_xucr0_clkg_ctl(0 to 3); + + +xu_spr_cspr : entity work.xuq_spr_cspr(xuq_spr_cspr) +generic map( + hvmode => hvmode, + a2mode => a2mode, + expand_type => expand_type, + threads => threads, + regsize => regsize, + eff_ifar => eff_ifar, + spr_xucr0_init_mod => spr_xucr0_init_mod) +port map( + nclk => nclk, + an_ac_sleep_en => an_ac_sleep_en, + an_ac_reservation_vld => an_ac_reservation_vld, + an_ac_tb_update_enable => an_ac_tb_update_enable, + an_ac_tb_update_pulse => an_ac_tb_update_pulse, + an_ac_coreid => an_ac_coreid, + pc_xu_instr_trace_mode => pc_xu_instr_trace_mode, + pc_xu_instr_trace_tid => pc_xu_instr_trace_tid, + instr_trace_mode => instr_trace_mode, + spr_pvr_version_dc => spr_pvr_version_dc, + spr_pvr_revision_dc => spr_pvr_revision_dc, + d_mode_dc => d_mode_dc, + delay_lclkr_dc(0) => delay_lclkr_dc, + mpw1_dc_b(0) => mpw1_dc_b, + mpw2_dc_b => mpw2_dc_b, + bcfg_sl_force => bcfg_sl_force(0), + bcfg_sl_thold_0_b => bcfg_sl_thold_0_b(0), + bcfg_slp_sl_force => bcfg_slp_sl_force, + bcfg_slp_sl_thold_0_b => bcfg_slp_sl_thold_0_b, + ccfg_sl_force => ccfg_sl_force(0), + ccfg_sl_thold_0_b => ccfg_sl_thold_0_b(0), + func_sl_force => func_sl_force(0), + func_sl_thold_0_b => func_sl_thold_0_b(0), + func_slp_sl_force => func_slp_sl_force(0), + func_slp_sl_thold_0_b => func_slp_sl_thold_0_b(0), + + func_nsl_force => func_nsl_force(0), + func_nsl_thold_0_b => func_nsl_thold_0_b(0), + func_slp_nsl_force => func_slp_nsl_force, + func_slp_nsl_thold_0_b => func_slp_nsl_thold_0_b, + + sg_0 => sg_0(0), + scan_in(0) => func_scan_rpwr_in(threads), + scan_in(1) => siv(xu_spr_cspr_offset), + scan_out(0) => func_scan_rpwr_out(threads), + scan_out(1) => sov(xu_spr_cspr_offset), + bcfg_scan_in => siv_bcfg(1), + bcfg_scan_out => sov_bcfg(1), + ccfg_scan_in => siv_ccfg(1), + ccfg_scan_out => sov_ccfg(1), + cspr_tspr_rf1_act => cspr_tspr_rf1_act, + dec_spr_rf0_tid => dec_spr_rf0_tid, + dec_spr_rf0_instr => dec_spr_rf0_instr, + dec_spr_rf1_val => dec_spr_rf1_val, + dec_spr_ex4_val => dec_spr_ex4_val, + tspr_cspr_ex3_tspr_rt => tspr_cspr_ex3_tspr_rt, + spr_byp_ex3_spr_rt => spr_byp_ex3_spr_rt, + mux_spr_ex2_rt => mux_spr_ex2_rt, + fxu_spr_ex1_rs0 => fxu_spr_ex1_rs0, + fxu_spr_ex1_rs1 => fxu_spr_ex1_rs1, + ex5_spr_wd => ex5_spr_wd, + cspr_tspr_ex1_instr => cspr_tspr_ex1_instr, + cspr_tspr_ex2_tid => cspr_tspr_ex2_tid, + cspr_tspr_ex5_is_mtmsr => cspr_tspr_ex5_is_mtmsr, + cspr_tspr_ex5_is_mtspr => cspr_tspr_ex5_is_mtspr, + cspr_tspr_ex5_is_wrtee => cspr_tspr_ex5_is_wrtee, + cspr_tspr_ex5_is_wrteei => cspr_tspr_ex5_is_wrteei, + cspr_tspr_ex5_instr => cspr_tspr_ex5_instr, + cspr_tspr_timebase_taps => cspr_tspr_timebase_taps, + timer_update => timer_update, + cspr_tspr_dec_dbg_dis => cspr_tspr_dec_dbg_dis, + tspr_cspr_illeg_mtspr_b => tspr_cspr_illeg_mtspr_b, + tspr_cspr_illeg_mfspr_b => tspr_cspr_illeg_mfspr_b, + tspr_cspr_hypv_mtspr => tspr_cspr_hypv_mtspr, + tspr_cspr_hypv_mfspr => tspr_cspr_hypv_mfspr, + cspr_aspr_ex5_we => cspr_aspr_ex5_we, + cspr_aspr_ex5_waddr => cspr_aspr_ex5_waddr, + cspr_aspr_rf1_re => cspr_aspr_rf1_re, + cspr_aspr_rf1_raddr => cspr_aspr_rf1_raddr, + aspr_cspr_ex1_rdata => aspr_cspr_ex1_rdata(64-regsize to 72-(64/regsize)), + xu_lsu_slowspr_val => xu_lsu_slowspr_val, + xu_lsu_slowspr_rw => xu_lsu_slowspr_rw, + xu_lsu_slowspr_etid => xu_lsu_slowspr_etid, + xu_lsu_slowspr_addr => xu_lsu_slowspr_addr, + xu_lsu_slowspr_data => xu_lsu_slowspr_data, + ac_an_dcr_act => ac_an_dcr_act, + ac_an_dcr_val => ac_an_dcr_val, + ac_an_dcr_read => ac_an_dcr_read, + ac_an_dcr_user => ac_an_dcr_user, + ac_an_dcr_etid => ac_an_dcr_etid, + ac_an_dcr_addr => ac_an_dcr_addr, + ac_an_dcr_data => ac_an_dcr_data, + xu_ex4_flush => xu_ex4_flush, + xu_ex5_flush => xu_ex5_flush, + spr_cpl_ex3_spr_hypv => spr_cpl_ex3_spr_hypv, + spr_cpl_ex3_spr_illeg => spr_cpl_ex3_spr_illeg, + spr_cpl_ex3_spr_priv => spr_cpl_ex3_spr_priv, + cpl_spr_stop => cpl_spr_stop, + xu_iu_run_thread => xu_iu_run_thread, + spr_cpl_ex2_run_ctl_flush => spr_cpl_ex2_run_ctl_flush, + xu_pc_spr_ccr0_we => xu_pc_spr_ccr0_we, + iu_xu_quiesce => iu_xu_quiesce, + lsu_xu_quiesce => lsu_xu_quiesce, + mm_xu_quiesce => mm_xu_quiesce, + bx_xu_quiesce => bx_xu_quiesce, + cpl_spr_quiesce => cpl_spr_quiesce, + xu_pc_running => xu_pc_running, + spr_cpl_quiesce => spr_cpl_quiesce, + pc_xu_extirpts_dis_on_stop => pc_xu_extirpts_dis_on_stop, + pc_xu_timebase_dis_on_stop => pc_xu_timebase_dis_on_stop, + pc_xu_decrem_dis_on_stop => pc_xu_decrem_dis_on_stop, + pc_xu_ram_mode => pc_xu_ram_mode, + pc_xu_ram_thread => pc_xu_ram_thread, + pc_xu_msrovride_enab => pc_xu_msrovride_enab, + cspr_tspr_msrovride_en => cspr_tspr_msrovride_en, + cspr_tspr_ram_mode => cspr_tspr_ram_mode, + cspr_tspr_llen => cspr_tspr_llen, + cspr_tspr_llpri => cspr_tspr_llpri, + tspr_cspr_lldet => tspr_cspr_lldet, + tspr_cspr_llpulse => tspr_cspr_llpulse, + pc_xu_reset_wd_complete => pc_xu_reset_wd_complete, + pc_xu_reset_1_complete => pc_xu_reset_1_complete, + pc_xu_reset_2_complete => pc_xu_reset_2_complete, + pc_xu_reset_3_complete => pc_xu_reset_3_complete, + reset_wd_complete => reset_wd_complete, + reset_1_complete => reset_1_complete, + reset_2_complete => reset_2_complete, + reset_3_complete => reset_3_complete, + cspr_tspr_crit_mask => cspr_tspr_crit_mask, + cspr_tspr_ext_mask => cspr_tspr_ext_mask, + cspr_tspr_dec_mask => cspr_tspr_dec_mask, + cspr_tspr_fit_mask => cspr_tspr_fit_mask, + cspr_tspr_wdog_mask => cspr_tspr_wdog_mask, + cspr_tspr_udec_mask => cspr_tspr_udec_mask, + cspr_tspr_perf_mask => cspr_tspr_perf_mask, + tspr_cspr_pm_wake_up => tspr_cspr_pm_wake_up, + spr_cpl_dbell_interrupt => spr_cpl_dbell_interrupt, + spr_cpl_cdbell_interrupt => spr_cpl_cdbell_interrupt, + spr_cpl_gdbell_interrupt => spr_cpl_gdbell_interrupt, + spr_cpl_gcdbell_interrupt => spr_cpl_gcdbell_interrupt, + spr_cpl_gmcdbell_interrupt => spr_cpl_gmcdbell_interrupt, + cpl_spr_ex5_dbell_taken => cpl_spr_ex5_dbell_taken, + cpl_spr_ex5_cdbell_taken => cpl_spr_ex5_cdbell_taken, + cpl_spr_ex5_gdbell_taken => cpl_spr_ex5_gdbell_taken, + cpl_spr_ex5_gcdbell_taken => cpl_spr_ex5_gcdbell_taken, + cpl_spr_ex5_gmcdbell_taken => cpl_spr_ex5_gmcdbell_taken, + cspr_tspr_dbell_pirtag => cspr_tspr_dbell_pirtag, + tspr_cspr_gpir_match => tspr_cspr_gpir_match, + lsu_xu_dbell_val => lsu_xu_dbell_val, + lsu_xu_dbell_type => lsu_xu_dbell_type, + lsu_xu_dbell_brdcast => lsu_xu_dbell_brdcast, + lsu_xu_dbell_lpid_match => lsu_xu_dbell_lpid_match, + lsu_xu_dbell_pirtag => lsu_xu_dbell_pirtag, + spr_cpl_ex3_sprg_ce => spr_cpl_ex3_sprg_ce, + spr_cpl_ex3_sprg_ue => spr_cpl_ex3_sprg_ue, + pc_xu_inj_sprg_ecc => pc_xu_inj_sprg_ecc, + xu_pc_err_sprg_ecc => xu_pc_err_sprg_ecc, + tspr_cspr_freeze_timers => tspr_cspr_freeze_timers, + tspr_cspr_async_int => tspr_cspr_async_int, + spr_perf_tx_events => spr_perf_tx_events, + xu_lsu_mtspr_trace_en => xu_lsu_mtspr_trace_en, + lsu_xu_spr_xucr0_cslc_xuop => lsu_xu_spr_xucr0_cslc_xuop, + lsu_xu_spr_xucr0_cslc_binv => lsu_xu_spr_xucr0_cslc_binv, + lsu_xu_spr_xucr0_clo => lsu_xu_spr_xucr0_clo, + lsu_xu_spr_xucr0_cul => lsu_xu_spr_xucr0_cul, + tspr_msr_gs => tspr_msr_gs, + tspr_msr_pr => tspr_msr_pr, + tspr_msr_ee => tspr_msr_ee, + tspr_msr_ce => tspr_msr_ce, + tspr_msr_me => tspr_msr_me, + cspr_xucr0_clkg_ctl => cspr_xucr0_clkg_ctl, + xu_lsu_spr_xucr0_clfc => xu_lsu_spr_xucr0_clfc, + spr_bit_act => spr_bit_act, + xu_pc_spr_ccr0_pme => xu_pc_spr_ccr0_pme, + spr_ccr2_en_dcr => spr_ccr2_en_dcr, + spr_ccr2_en_pc => spr_ccr2_en_pc, + xu_iu_spr_ccr2_ifratsc => xu_iu_spr_ccr2_ifratsc, + xu_iu_spr_ccr2_ifrat => xu_iu_spr_ccr2_ifrat, + xu_lsu_spr_ccr2_dfratsc => xu_lsu_spr_ccr2_dfratsc, + xu_lsu_spr_ccr2_dfrat => xu_lsu_spr_ccr2_dfrat, + spr_ccr2_ucode_dis => spr_ccr2_ucode_dis, + spr_ccr2_ap => spr_ccr2_ap, + spr_ccr2_en_attn => spr_ccr2_en_attn, + spr_ccr2_en_ditc => spr_ccr2_en_ditc, + spr_ccr2_en_icswx => spr_ccr2_en_icswx, + spr_ccr2_notlb => spr_ccr2_notlb, + xu_lsu_spr_xucr0_mbar_ack => xu_lsu_spr_xucr0_mbar_ack, + xu_lsu_spr_xucr0_tlbsync => xu_lsu_spr_xucr0_tlbsync, + spr_dec_spr_xucr0_ssdly => spr_dec_spr_xucr0_ssdly, + spr_xucr0_cls => spr_xucr0_cls, + xu_lsu_spr_xucr0_aflsta => xu_lsu_spr_xucr0_aflsta, + spr_xucr0_mddp => spr_xucr0_mddp, + xu_lsu_spr_xucr0_cred => xu_lsu_spr_xucr0_cred, + xu_lsu_spr_xucr0_rel => xu_lsu_spr_xucr0_rel, + spr_xucr0_mdcp => spr_xucr0_mdcp, + xu_lsu_spr_xucr0_flsta => xu_lsu_spr_xucr0_flsta, + xu_lsu_spr_xucr0_l2siw => xu_lsu_spr_xucr0_l2siw, + xu_lsu_spr_xucr0_flh2l2 => xu_lsu_spr_xucr0_flh2l2, + xu_lsu_spr_xucr0_dcdis => xu_lsu_spr_xucr0_dcdis, + xu_lsu_spr_xucr0_wlk => xu_lsu_spr_xucr0_wlk, + cspr_debug0 => cspr_debug0, + cspr_debug1 => cspr_debug1, + vdd => vdd, + gnd => gnd +); + +thread : for t in 0 to threads-1 generate +xu_spr_tspr : entity work.xuq_spr_tspr(xuq_spr_tspr) +generic map( + hvmode => hvmode, + a2mode => a2mode, + expand_type => expand_type, + regsize => regsize, + eff_ifar => eff_ifar) +port map( + nclk => nclk, + an_ac_ext_interrupt => an_ac_ext_interrupt(t), + an_ac_crit_interrupt => an_ac_crit_interrupt(t), + an_ac_perf_interrupt => an_ac_perf_interrupt(t), + an_ac_hang_pulse => an_ac_hang_pulse(t), + ac_tc_machine_check => ac_tc_machine_check(t), + an_ac_external_mchk => an_ac_external_mchk(t), + instr_trace_mode => instr_trace_mode(t), + d_mode_dc => d_mode_dc, + delay_lclkr_dc(0) => delay_lclkr_dc, + mpw1_dc_b(0) => mpw1_dc_b, + mpw2_dc_b => mpw2_dc_b, + func_sl_force => func_sl_force(1+t), + func_sl_thold_0_b => func_sl_thold_0_b(1+t), + func_nsl_force => func_nsl_force(1+t), + func_nsl_thold_0_b => func_nsl_thold_0_b(1+t), + func_slp_sl_force => func_slp_sl_force(1+t), + func_slp_sl_thold_0_b => func_slp_sl_thold_0_b(1+t), + ccfg_sl_force => ccfg_sl_force(1+t), + ccfg_sl_thold_0_b => ccfg_sl_thold_0_b(1+t), + dcfg_sl_force => dcfg_sl_force(1+t), + dcfg_sl_thold_0_b => dcfg_sl_thold_0_b(1+t), + sg_0 => sg_0(1+t), + scan_in => func_scan_rpwr_in(t), + scan_out => func_scan_rpwr_out(t), + ccfg_scan_in => siv_ccfg(2+t), + ccfg_scan_out => sov_ccfg(2+t), + dcfg_scan_in => siv_dcfg(1+t), + dcfg_scan_out => sov_dcfg(1+t), + cspr_tspr_rf1_act => cspr_tspr_rf1_act, + cspr_tspr_ex1_instr => cspr_tspr_ex1_instr, + cspr_tspr_ex2_tid => cspr_tspr_ex2_tid(t), + tspr_cspr_ex3_tspr_rt => tspr_cspr_ex3_tspr_rt(regsize*t to regsize*(t+1)-1), + dec_spr_ex4_val => dec_spr_ex4_val(t), + cspr_tspr_ex5_is_mtmsr => cspr_tspr_ex5_is_mtmsr, + cspr_tspr_ex5_is_mtspr => cspr_tspr_ex5_is_mtspr, + cspr_tspr_ex5_is_wrtee => cspr_tspr_ex5_is_wrtee, + cspr_tspr_ex5_is_wrteei => cspr_tspr_ex5_is_wrteei, + cspr_tspr_ex5_instr => cspr_tspr_ex5_instr, + ex5_spr_wd => ex5_spr_wd(64-regsize to 63), + cspr_tspr_dec_dbg_dis => cspr_tspr_dec_dbg_dis(t), + tspr_cspr_illeg_mtspr_b => tspr_cspr_illeg_mtspr_b(t), + tspr_cspr_illeg_mfspr_b => tspr_cspr_illeg_mfspr_b(t), + tspr_cspr_hypv_mtspr => tspr_cspr_hypv_mtspr(t), + tspr_cspr_hypv_mfspr => tspr_cspr_hypv_mfspr(t), + cpl_spr_ex5_act => cpl_spr_ex5_act(t), + cpl_spr_ex5_int => cpl_spr_ex5_int(t), + cpl_spr_ex5_gint => cpl_spr_ex5_gint(t), + cpl_spr_ex5_cint => cpl_spr_ex5_cint(t), + cpl_spr_ex5_mcint => cpl_spr_ex5_mcint(t), + cpl_spr_ex5_nia => cpl_spr_ex5_nia(eff_ifar*t to eff_ifar*(t+1)-1), + cpl_spr_ex5_esr => cpl_spr_ex5_esr(17*t to 17*(t+1)-1), + cpl_spr_ex5_mcsr => cpl_spr_ex5_mcsr(15*t to 15*(t+1)-1), + cpl_spr_ex5_dbsr => cpl_spr_ex5_dbsr(19*t to 19*(t+1)-1), + cpl_spr_ex5_dear_update => cpl_spr_ex5_dear_update(t), + cpl_spr_ex5_dear_update_saved => cpl_spr_ex5_dear_update_saved(t), + cpl_spr_ex5_dear_save => cpl_spr_ex5_dear_save(t), + cpl_spr_ex5_dbsr_update => cpl_spr_ex5_dbsr_update(t), + cpl_spr_ex5_esr_update => cpl_spr_ex5_esr_update(t), + cpl_spr_ex5_srr0_dec => cpl_spr_ex5_srr0_dec(t), + cpl_spr_ex5_force_gsrr => cpl_spr_ex5_force_gsrr(t), + cpl_spr_ex5_dbsr_ide => cpl_spr_ex5_dbsr_ide(t), + spr_cpl_dbsr_ide => spr_cpl_dbsr_ide(t), + spr_cpl_external_mchk => spr_cpl_external_mchk(t), + spr_cpl_ext_interrupt => spr_cpl_ext_interrupt(t), + spr_cpl_dec_interrupt => spr_cpl_dec_interrupt(t), + spr_cpl_udec_interrupt => spr_cpl_udec_interrupt(t), + spr_cpl_perf_interrupt => spr_cpl_perf_interrupt(t), + spr_cpl_fit_interrupt => spr_cpl_fit_interrupt(t), + spr_cpl_crit_interrupt => spr_cpl_crit_interrupt(t), + spr_cpl_wdog_interrupt => spr_cpl_wdog_interrupt(t), + cspr_tspr_crit_mask => cspr_tspr_crit_mask(t), + cspr_tspr_ext_mask => cspr_tspr_ext_mask(t), + cspr_tspr_dec_mask => cspr_tspr_dec_mask(t), + cspr_tspr_fit_mask => cspr_tspr_fit_mask(t), + cspr_tspr_wdog_mask => cspr_tspr_wdog_mask(t), + cspr_tspr_udec_mask => cspr_tspr_udec_mask(t), + cspr_tspr_perf_mask => cspr_tspr_perf_mask(t), + tspr_cspr_pm_wake_up => tspr_cspr_pm_wake_up(t), + tspr_cspr_async_int => tspr_cspr_async_int(3*t to 3*(t+1)-1), + dec_spr_ex1_epid_instr => dec_spr_ex1_epid_instr, + fxu_spr_ex1_rs2 => fxu_spr_ex1_rs2, + spr_cpl_ex3_ct_be => spr_cpl_ex3_ct_be(t), + spr_cpl_ex3_ct_le => spr_cpl_ex3_ct_le(t), + cspr_tspr_dbell_pirtag => cspr_tspr_dbell_pirtag, + tspr_cspr_gpir_match => tspr_cspr_gpir_match(t), + cspr_tspr_timebase_taps => cspr_tspr_timebase_taps, + timer_update => timer_update, + spr_cpl_iac1_en => spr_cpl_iac1_en(t), + spr_cpl_iac2_en => spr_cpl_iac2_en(t), + spr_cpl_iac3_en => spr_cpl_iac3_en(t), + spr_cpl_iac4_en => spr_cpl_iac4_en(t), + tspr_cspr_freeze_timers => tspr_cspr_freeze_timers(t), + xu_ex4_flush => xu_ex4_flush(t), + xu_ex5_flush => xu_ex5_flush(t), + xu_iu_single_instr_mode => xu_iu_single_instr_mode(t), + xu_iu_raise_iss_pri => xu_iu_raise_iss_pri(t), + cpl_spr_ex5_instr_cpl => cpl_spr_ex5_instr_cpl(t), + cspr_tspr_llen => cspr_tspr_llen(t), + cspr_tspr_llpri => cspr_tspr_llpri(t), + tspr_cspr_lldet => tspr_cspr_lldet(t), + tspr_cspr_llpulse => tspr_cspr_llpulse(t), + xu_pc_err_llbust_attempt => xu_pc_err_llbust_attempt(t), + xu_pc_err_llbust_failed => xu_pc_err_llbust_failed(t), + pc_xu_inj_llbust_attempt => pc_xu_inj_llbust_attempt(t), + pc_xu_inj_llbust_failed => pc_xu_inj_llbust_failed(t), + pc_xu_inj_wdt_reset => pc_xu_inj_wdt_reset(t), + spr_byp_ex4_is_mtxer => spr_byp_ex4_is_mtxer(t), + spr_byp_ex4_is_mfxer => spr_byp_ex4_is_mfxer(t), + reset_wd_complete => reset_wd_complete, + reset_1_complete => reset_1_complete, + reset_2_complete => reset_2_complete, + reset_3_complete => reset_3_complete, + reset_1_request => reset_1_request(t), + reset_2_request => reset_2_request(t), + reset_3_request => reset_3_request(t), + reset_wd_request => reset_wd_request(t), + xu_pc_err_wdt_reset => xu_pc_err_wdt_reset(t), + cspr_tspr_ram_mode => cspr_tspr_ram_mode(t), + cspr_tspr_msrovride_en => cspr_tspr_msrovride_en(t), + pc_xu_msrovride_pr => pc_xu_msrovride_pr, + pc_xu_msrovride_gs => pc_xu_msrovride_gs, + pc_xu_msrovride_de => pc_xu_msrovride_de, + cpl_spr_dbcr0_edm => cpl_spr_dbcr0_edm(t), + lsu_xu_spr_epsc_egs => lsu_xu_spr_epsc_egs(t), + lsu_xu_spr_epsc_epr => lsu_xu_spr_epsc_epr(t), + tspr_epcr_extgs => tspr_epcr_extgs(t), + tspr_fp_precise => tspr_fp_precise(t), + tspr_msr_de => tspr_msr_de(t), + tspr_msr_pr => tspr_msr_pr(t), + tspr_msr_is => tspr_msr_is(t), + tspr_msr_cm => tspr_msr_cm(t), + tspr_msr_gs => tspr_msr_gs(t), + tspr_msr_ee => tspr_msr_ee(t), + tspr_msr_ce => tspr_msr_ce(t), + tspr_msr_me => tspr_msr_me(t), + cspr_xucr0_clkg_ctl => cspr_xucr0_clkg_ctl(4 to 4), + spr_dbcr0_idm => spr_dbcr0_idm(t), + spr_dbcr0_icmp => spr_dbcr0_icmp(t), + spr_dbcr0_brt => spr_dbcr0_brt(t), + spr_dbcr0_irpt => spr_dbcr0_irpt(t), + spr_dbcr0_trap => spr_dbcr0_trap(t), + spr_dbcr0_dac1 => spr_dbcr0_dac1(2*t to 2*(t+1)-1), + spr_dbcr0_dac2 => spr_dbcr0_dac2(2*t to 2*(t+1)-1), + spr_dbcr0_ret => spr_dbcr0_ret(t), + spr_dbcr0_dac3 => spr_dbcr0_dac3(2*t to 2*(t+1)-1), + spr_dbcr0_dac4 => spr_dbcr0_dac4(2*t to 2*(t+1)-1), + spr_dbcr1_iac12m => spr_dbcr1_iac12m(t), + spr_dbcr1_iac34m => spr_dbcr1_iac34m(t), + spr_epcr_dtlbgs => spr_epcr_dtlbgs(t), + spr_epcr_itlbgs => spr_epcr_itlbgs(t), + spr_epcr_dsigs => spr_epcr_dsigs(t), + spr_epcr_isigs => spr_epcr_isigs(t), + spr_epcr_duvd => spr_epcr_duvd(t), + spr_epcr_dgtmi => spr_epcr_dgtmi(t), + xu_mm_spr_epcr_dmiuh => xu_mm_spr_epcr_dmiuh(t), + spr_msr_ucle => spr_msr_ucle(t), + spr_msr_spv => spr_msr_spv(t), + spr_msr_fp => spr_msr_fp(t), + spr_msr_ds => spr_msr_ds(t), + spr_msrp_uclep => spr_msrp_uclep(t), + tspr_debug => tspr_debug(12*t to 12*(t+1)-1), + vdd => vdd, + gnd => gnd +); +end generate; + + +xu_spr_aspr : entity tri.tri_64x72_1r1w(tri_64x72_1r1w) +generic map( + expand_type => expand_type, + regsize => regsize) +port map ( + vdd => vdd, + vcs => vcs, + gnd => gnd, + nclk => nclk, + sg_0 => sg_0(0), + abst_sl_thold_0 => abst_sl_thold_0, + ary_nsl_thold_0 => ary_nsl_thold_0, + time_sl_thold_0 => time_sl_thold_0, + repr_sl_thold_0 => repr_sl_thold_0, + rd0_act => cspr_aspr_rf1_re, + rd0_adr => cspr_aspr_rf1_raddr, + do0 => aspr_cspr_ex1_rdata, + wr_act => cspr_aspr_ex5_we, + wr_adr => cspr_aspr_ex5_waddr, + di => ex5_spr_wd, + abst_scan_in => siv_abst(xu_spr_aspr_offset_abst), + abst_scan_out => sov_abst(xu_spr_aspr_offset_abst), + time_scan_in => siv_time(1), + time_scan_out => sov_time(1), + repr_scan_in => siv_repr(1), + repr_scan_out => sov_repr(1), + scan_dis_dc_b => an_ac_scan_dis_dc_b, + scan_diag_dc => an_ac_scan_diag_dc, + ccflush_dc => pc_xu_ccflush_dc, + clkoff_dc_b => g8t_clkoff_dc_b, + d_mode_dc => g8t_d_mode_dc, + mpw1_dc_b => g8t_mpw1_dc_b, + mpw2_dc_b => g8t_mpw2_dc_b, + delay_lclkr_dc => g8t_delay_lclkr_dc, + lcb_bolt_sl_thold_0 => bolt_sl_thold_0, + pc_bo_enable_2 => bo_enable_2, + pc_bo_reset => pc_xu_bo_reset, + pc_bo_unload => pc_xu_bo_unload, + pc_bo_repair => pc_xu_bo_repair, + pc_bo_shdata => pc_xu_bo_shdata, + pc_bo_select => pc_xu_bo_select, + bo_pc_failout => xu_pc_bo_fail, + bo_pc_diagloop => xu_pc_bo_diagout, + tri_lcb_mpw1_dc_b => mpw1_dc_b, + tri_lcb_mpw2_dc_b => mpw2_dc_b, + tri_lcb_delay_lclkr_dc => delay_lclkr_dc, + tri_lcb_clkoff_dc_b => clkoff_dc_b, + tri_lcb_act_dis_dc => tidn, + abist_bw_odd => abist_g8t_bw_1_q, + abist_bw_even => abist_g8t_bw_0_q, + tc_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc, + abist_ena_1 => pc_xu_abist_ena_dc, + wr_abst_act => abist_g8t_wenb_q, + abist_wr_adr => abist_waddr_0_q, + abist_di => abist_di_0_q, + rd0_abst_act => abist_g8t1p_renb_0_q, + abist_rd0_adr => abist_raddr_0_q, + abist_g8t_rd0_comp_ena => abist_wl32_comp_ena_q, + abist_raw_dc_b => pc_xu_abist_raw_dc_b, + obs0_abist_cmp => abist_g8t_dcomp_q + ); + +xu_debug_mux : entity clib.c_debug_mux4(c_debug_mux4) +port map( + vd => vdd, + gd => gnd, + select_bits => debug_mux_ctrls_q, + trace_data_in => spr_debug_data_in, + trigger_data_in => spr_trigger_data_in, + dbg_group0 => dbg_group0, + dbg_group1 => dbg_group1, + dbg_group2 => dbg_group2, + dbg_group3 => dbg_group3, + trg_group0 => trg_group0, + trg_group1 => trg_group1, + trg_group2 => trg_group2, + trg_group3 => trg_group3, + trigger_data_out => trigger_data_out_d, + trace_data_out => debug_data_out_d); + +dbg_group0 <= cspr_debug0 & tspr_debug; +dbg_group1 <= cspr_debug1; +dbg_group2 <= lsu_xu_cmd_debug(0 to 87); +dbg_group3 <= lsu_xu_cmd_debug(88 to 175); +trg_group0 <= (others=>'0'); +trg_group1 <= (others=>'0'); +trg_group2 <= (others=>'0'); +trg_group3 <= (others=>'0'); + +spr_trigger_data_out <= trigger_data_out_q; +spr_debug_data_out <= debug_data_out_q; + + +reset_1_request_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_nsl_force(0), + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b(0), + din(0) => reset_1_request_d, + dout(0) => reset_1_request_q); +reset_2_request_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_nsl_force(0), + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b(0), + din(0) => reset_2_request_d, + dout(0) => reset_2_request_q); +reset_3_request_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_nsl_force(0), + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b(0), + din(0) => reset_3_request_d, + dout(0) => reset_3_request_q); +reset_wd_request_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_nsl_force(0), + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b(0), + din(0) => reset_wd_request_d, + dout(0) => reset_wd_request_q); +trace_bus_enable_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force(0), + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b(0), + sg => sg_0(0), + scin => siv(trace_bus_enable_offset), + scout => sov(trace_bus_enable_offset), + din => pc_xu_trace_bus_enable , + dout => trace_bus_enable_q); +debug_mux_ctrls_latch : tri_rlmreg_p + generic map (width => debug_mux_ctrls_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_slp_sl_force(0), + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b(0), + sg => sg_0(0), + scin => siv(debug_mux_ctrls_offset to debug_mux_ctrls_offset + debug_mux_ctrls_q'length-1), + scout => sov(debug_mux_ctrls_offset to debug_mux_ctrls_offset + debug_mux_ctrls_q'length-1), + din => spr_debug_mux_ctrls , + dout => debug_mux_ctrls_q); +debug_data_out_latch : tri_rlmreg_p + generic map (width => debug_data_out_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_slp_sl_force(0), + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b(0), + sg => sg_0(0), + scin => siv(debug_data_out_offset to debug_data_out_offset + debug_data_out_q'length-1), + scout => sov(debug_data_out_offset to debug_data_out_offset + debug_data_out_q'length-1), + din => debug_data_out_d, + dout => debug_data_out_q); +trigger_data_out_latch : tri_rlmreg_p + generic map (width => trigger_data_out_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_slp_sl_force(0), + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b(0), + sg => sg_0(0), + scin => siv(trigger_data_out_offset to trigger_data_out_offset + trigger_data_out_q'length-1), + scout => sov(trigger_data_out_offset to trigger_data_out_offset + trigger_data_out_q'length-1), + din => trigger_data_out_d, + dout => trigger_data_out_q); +abist_g8t_wenb_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => pc_xu_abist_ena_dc, + forcee => abst_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => abst_sl_thold_0_b, + sg => sg_0(0), + scin => siv_abst(abist_g8t_wenb_offset_abst), + scout => sov_abst(abist_g8t_wenb_offset_abst), + din => pc_xu_abist_g8t_wenb, + dout => abist_g8t_wenb_q); +abist_waddr_0_latch : tri_rlmreg_p + generic map (width => abist_waddr_0_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => pc_xu_abist_ena_dc, + forcee => abst_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => abst_sl_thold_0_b, + sg => sg_0(0), + scin => siv_abst(abist_waddr_0_offset_abst to abist_waddr_0_offset_abst + abist_waddr_0_q'length-1), + scout => sov_abst(abist_waddr_0_offset_abst to abist_waddr_0_offset_abst + abist_waddr_0_q'length-1), + din => pc_xu_abist_waddr_0, + dout => abist_waddr_0_q); +abist_di_0_latch : tri_rlmreg_p + generic map (width => abist_di_0_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => pc_xu_abist_ena_dc, + forcee => abst_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => abst_sl_thold_0_b, + sg => sg_0(0), + scin => siv_abst(abist_di_0_offset_abst to abist_di_0_offset_abst + abist_di_0_q'length-1), + scout => sov_abst(abist_di_0_offset_abst to abist_di_0_offset_abst + abist_di_0_q'length-1), + din => pc_xu_abist_di_0, + dout => abist_di_0_q); +abist_g8t1p_renb_0_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => pc_xu_abist_ena_dc, + forcee => abst_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => abst_sl_thold_0_b, + sg => sg_0(0), + scin => siv_abst(abist_g8t1p_renb_0_offset_abst), + scout => sov_abst(abist_g8t1p_renb_0_offset_abst), + din => pc_xu_abist_g8t1p_renb_0, + dout => abist_g8t1p_renb_0_q); +abist_raddr_0_latch : tri_rlmreg_p + generic map (width => abist_raddr_0_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => pc_xu_abist_ena_dc, + forcee => abst_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => abst_sl_thold_0_b, + sg => sg_0(0), + scin => siv_abst(abist_raddr_0_offset_abst to abist_raddr_0_offset_abst + abist_raddr_0_q'length-1), + scout => sov_abst(abist_raddr_0_offset_abst to abist_raddr_0_offset_abst + abist_raddr_0_q'length-1), + din => pc_xu_abist_raddr_0, + dout => abist_raddr_0_q); +abist_wl32_comp_ena_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => pc_xu_abist_ena_dc, + forcee => abst_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => abst_sl_thold_0_b, + sg => sg_0(0), + scin => siv_abst(abist_wl32_comp_ena_offset_abst), + scout => sov_abst(abist_wl32_comp_ena_offset_abst), + din => pc_xu_abist_wl32_comp_ena, + dout => abist_wl32_comp_ena_q); +abist_g8t_dcomp_latch : tri_rlmreg_p + generic map (width => abist_g8t_dcomp_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => pc_xu_abist_ena_dc, + forcee => abst_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => abst_sl_thold_0_b, + sg => sg_0(0), + scin => siv_abst(abist_g8t_dcomp_offset_abst to abist_g8t_dcomp_offset_abst + abist_g8t_dcomp_q'length-1), + scout => sov_abst(abist_g8t_dcomp_offset_abst to abist_g8t_dcomp_offset_abst + abist_g8t_dcomp_q'length-1), + din => pc_xu_abist_g8t_dcomp, + dout => abist_g8t_dcomp_q); +abist_g8t_bw_1_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => pc_xu_abist_ena_dc, + forcee => abst_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => abst_sl_thold_0_b, + sg => sg_0(0), + scin => siv_abst(abist_g8t_bw_1_offset_abst), + scout => sov_abst(abist_g8t_bw_1_offset_abst), + din => pc_xu_abist_g8t_bw_1, + dout => abist_g8t_bw_1_q); +abist_g8t_bw_0_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => pc_xu_abist_ena_dc, + forcee => abst_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => abst_sl_thold_0_b, + sg => sg_0(0), + scin => siv_abst(abist_g8t_bw_0_offset_abst), + scout => sov_abst(abist_g8t_bw_0_offset_abst), + din => pc_xu_abist_g8t_bw_0, + dout => abist_g8t_bw_0_q); +abst_scan_in_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc, + thold_b => abst_so_thold_0_b, + scin => siv_abst(siv_abst'left to siv_abst'left), + scout => sov_abst(siv_abst'left to siv_abst'left), + dout => open); +abst_scan_out_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc, + thold_b => abst_so_thold_0_b, + scin => siv_abst(siv_abst'right to siv_abst'right), + scout => sov_abst(siv_abst'right to siv_abst'right), + dout => open); +bcfg_scan_in_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc, + thold_b => bcfg_so_thold_0_b, + scin => siv_bcfg(siv_bcfg'left to siv_bcfg'left), + scout => sov_bcfg(siv_bcfg'left to siv_bcfg'left), + dout => open); +bcfg_scan_out_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc, + thold_b => bcfg_so_thold_0_b, + scin => siv_bcfg(siv_bcfg'right to siv_bcfg'right), + scout => sov_bcfg(siv_bcfg'right to siv_bcfg'right), + dout => open); +ccfg_scan_in_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc, + thold_b => ccfg_so_thold_0_b, + scin => siv_ccfg(siv_ccfg'left to siv_ccfg'left), + scout => sov_ccfg(siv_ccfg'left to siv_ccfg'left), + dout => open); +ccfg_scan_out_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc, + thold_b => ccfg_so_thold_0_b, + scin => siv_ccfg(siv_ccfg'right to siv_ccfg'right), + scout => sov_ccfg(siv_ccfg'right to siv_ccfg'right), + dout => open); +dcfg_scan_in_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc, + thold_b => dcfg_so_thold_0_b, + scin => siv_dcfg(siv_dcfg'left to siv_dcfg'left), + scout => sov_dcfg(siv_dcfg'left to siv_dcfg'left), + dout => open); +dcfg_scan_out_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc, + thold_b => dcfg_so_thold_0_b, + scin => siv_dcfg(siv_dcfg'right to siv_dcfg'right), + scout => sov_dcfg(siv_dcfg'right to siv_dcfg'right), + dout => open); +time_scan_in_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc, + thold_b => time_so_thold_0_b, + scin => siv_time(siv_time'left to siv_time'left), + scout => sov_time(siv_time'left to siv_time'left), + dout => open); +time_scan_out_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc, + thold_b => time_so_thold_0_b, + scin => siv_time(siv_time'right to siv_time'right), + scout => sov_time(siv_time'right to siv_time'right), + dout => open); +repr_scan_in_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc, + thold_b => repr_so_thold_0_b, + scin => siv_repr(siv_repr'left to siv_repr'left), + scout => sov_repr(siv_repr'left to siv_repr'left), + dout => open); +repr_scan_out_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc, + thold_b => repr_so_thold_0_b, + scin => siv_repr(siv_repr'right to siv_repr'right), + scout => sov_repr(siv_repr'right to siv_repr'right), + dout => open); +gptr_scan_in_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => tiup, + thold_b => gptr_so_thold_0_b, + scin => siv_gptr(siv_gptr'left to siv_gptr'left), + scout => sov_gptr(siv_gptr'left to siv_gptr'left), + dout => open); +gptr_scan_out_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => tiup, + thold_b => gptr_so_thold_0_b, + scin => siv_gptr(siv_gptr'right to siv_gptr'right), + scout => sov_gptr(siv_gptr'right to siv_gptr'right), + dout => open); +func_scan_in_latch : tri_regs + generic map (width => func_scan_in'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc, + thold_b => func_so_thold_0_b, + scin => func_scan_in, + scout => func_scan_rpwr_in, + dout => open); +func_scan_out_latch : tri_regs + generic map (width => func_scan_rpwr_out'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc, + thold_b => func_so_thold_0_b, + scin => func_scan_rpwr_out, + scout => func_scan_gate_out, + dout => open); + +lcbctrl_g8t: tri_lcbcntl_array_mac + generic map (expand_type => expand_type) +port map ( + vdd => vdd, + gnd => gnd, + sg => sg_0(0), + nclk => nclk, + scan_in => siv_gptr(1), + scan_diag_dc => an_ac_scan_diag_dc, + thold => gptr_sl_thold_0, + clkoff_dc_b => g8t_clkoff_dc_b, + delay_lclkr_dc => g8t_delay_lclkr_dc(0 to 4), + act_dis_dc => open, + d_mode_dc => g8t_d_mode_dc, + mpw1_dc_b => g8t_mpw1_dc_b(0 to 4), + mpw2_dc_b => g8t_mpw2_dc_b, + scan_out => sov_gptr(1)); + +perv_2to1_reg: tri_plat + generic map (width => 14, expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_xu_ccflush_dc, + din(0) => func_slp_sl_thold_2, + din(1) => func_sl_thold_2, + din(2) => func_slp_nsl_thold_2, + din(3) => func_nsl_thold_2, + din(4) => time_sl_thold_2, + din(5) => repr_sl_thold_2, + din(6) => gptr_sl_thold_2, + din(7) => bolt_sl_thold_2, + din(8) => abst_sl_thold_2, + din(9) => ary_nsl_thold_2, + din(10) => cfg_sl_thold_2, + din(11) => cfg_slp_sl_thold_2, + din(12) => sg_2, + din(13) => fce_2, + q(0) => func_slp_sl_thold_1, + q(1) => func_sl_thold_1, + q(2) => func_slp_nsl_thold_1, + q(3) => func_nsl_thold_1, + q(4) => time_sl_thold_1, + q(5) => repr_sl_thold_1, + q(6) => gptr_sl_thold_1, + q(7) => bolt_sl_thold_1, + q(8) => abst_sl_thold_1, + q(9) => ary_nsl_thold_1, + q(10) => cfg_sl_thold_1, + q(11) => cfg_slp_sl_thold_1, + q(12) => sg_1, + q(13) => fce_1); + + +perv_1to0_reg_gen : for t in 0 to threads generate + perv_1to0_reg: tri_plat + generic map (width => 6, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_xu_ccflush_dc, + din(0) => func_slp_sl_thold_1, + din(1) => func_sl_thold_1, + din(2) => func_nsl_thold_1, + din(3) => cfg_sl_thold_1, + din(4) => sg_1, + din(5) => fce_1, + q(0) => func_slp_sl_thold_0(t), + q(1) => func_sl_thold_0(t), + q(2) => func_nsl_thold_0(t), + q(3) => cfg_sl_thold_0(t), + q(4) => sg_0(t), + q(5) => fce_0(t)); + + perv_lcbor_cfg_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_dc_b, + thold => cfg_sl_thold_0(t), + sg => sg_0(t), + act_dis => tidn, + forcee => cfg_sl_force(t), + thold_b => cfg_sl_thold_0_b(t)); + + perv_lcbor_func_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_dc_b, + thold => func_sl_thold_0(t), + sg => sg_0(t), + act_dis => tidn, + forcee => func_sl_force(t), + thold_b => func_sl_thold_0_b(t)); + + perv_lcbor_func_slp_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_dc_b, + thold => func_slp_sl_thold_0(t), + sg => sg_0(t), + act_dis => tidn, + forcee => func_slp_sl_force(t), + thold_b => func_slp_sl_thold_0_b(t)); + + perv_lcbor_func_nsl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_dc_b, + thold => func_nsl_thold_0(t), + sg => fce_0(t), + act_dis => tidn, + forcee => func_nsl_force(t), + thold_b => func_nsl_thold_0_b(t)); +end generate; + + ccfg_sl_force <= cfg_sl_force; + ccfg_sl_thold_0_b <= cfg_sl_thold_0_b; + dcfg_sl_force(1 to 4) <= cfg_sl_force(1 to 4); + dcfg_sl_thold_0_b(1 to 4) <= cfg_sl_thold_0_b(1 to 4); + + bcfg_sl_force(0) <= cfg_sl_force(0); + bcfg_sl_thold_0_b(0) <= cfg_sl_thold_0_b(0); + + bcfg_slp_sl_force <= cfg_slp_sl_force; + bcfg_slp_sl_thold_0_b <= cfg_slp_sl_thold_0_b; + + perv_lcbor_cfg_slp_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_dc_b, + thold => cfg_slp_sl_thold_0, + sg => sg_0(0), + act_dis => tidn, + forcee => cfg_slp_sl_force, + thold_b => cfg_slp_sl_thold_0_b); + + perv_lcbor_func_slp_nsl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_dc_b, + thold => func_slp_nsl_thold_0, + sg => fce_0(0), + act_dis => tidn, + forcee => func_slp_nsl_force, + thold_b => func_slp_nsl_thold_0_b); + +perv_1to0_reg: tri_plat + generic map (width => 8, expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_xu_ccflush_dc, + din(0) => abst_sl_thold_1, + din(1) => ary_nsl_thold_1, + din(2) => time_sl_thold_1, + din(3) => repr_sl_thold_1, + din(4) => gptr_sl_thold_1, + din(5) => bolt_sl_thold_1, + din(6) => func_slp_nsl_thold_1, + din(7) => cfg_slp_sl_thold_1, + q(0) => abst_sl_thold_0, + q(1) => ary_nsl_thold_0, + q(2) => time_sl_thold_0, + q(3) => repr_sl_thold_0, + q(4) => gptr_sl_thold_0, + q(5) => bolt_sl_thold_0, + q(6) => func_slp_nsl_thold_0, + q(7) => cfg_slp_sl_thold_0); + +perv_lcbor_abst_sl: tri_lcbor + generic map (expand_type => expand_type) +port map (clkoff_b => clkoff_dc_b, + thold => abst_sl_thold_0, + sg => sg_0(0), + act_dis => tidn, + forcee => abst_sl_force, + thold_b => abst_sl_thold_0_b); + + + so_force <= sg_0(0); +abst_so_thold_0_b <= not abst_sl_thold_0; +bcfg_so_thold_0_b <= not cfg_sl_thold_0(0); +ccfg_so_thold_0_b <= not cfg_sl_thold_0(0); +dcfg_so_thold_0_b <= not cfg_sl_thold_0(0); +time_so_thold_0_b <= not time_sl_thold_0; +repr_so_thold_0_b <= not repr_sl_thold_0; +gptr_so_thold_0_b <= not gptr_sl_thold_0; +func_so_thold_0_b <= not func_sl_thold_0(0); + + +func_scan_out <= gate(func_scan_gate_out,an_ac_scan_dis_dc_b); + +siv(0 to siv'right) <= sov(1 to siv'right) & func_scan_rpwr_in(threads+1); +func_scan_rpwr_out(threads+1) <= sov(0); + +siv_abst(0 to siv_abst'right) <= sov_abst(1 to sov_abst'right) & abst_scan_in; +abst_scan_out <= sov_abst(0) and an_ac_scan_dis_dc_b; + +siv_bcfg(0 to siv_bcfg'right) <= sov_bcfg(1 to siv_bcfg'right) & bcfg_scan_in; +bcfg_scan_out <= sov_bcfg(0) and an_ac_scan_dis_dc_b; + +siv_ccfg(0 to siv_ccfg'right) <= sov_ccfg(1 to siv_ccfg'right) & ccfg_scan_in; +ccfg_scan_out <= sov_ccfg(0) and an_ac_scan_dis_dc_b; + +siv_dcfg(0 to siv_dcfg'right) <= sov_dcfg(1 to siv_dcfg'right) & dcfg_scan_in; +dcfg_scan_out <= sov_dcfg(0) and an_ac_scan_dis_dc_b; + +siv_time(0 to siv_time'right) <= sov_time(1 to siv_time'right) & time_scan_in; +time_scan_out <= sov_time(0) and an_ac_scan_dis_dc_b; + +siv_repr(0 to siv_repr'right) <= sov_repr(1 to siv_repr'right) & repr_scan_in; +repr_scan_out <= sov_repr(0) and an_ac_scan_dis_dc_b; + +siv_gptr(0 to siv_gptr'right) <= sov_gptr(1 to siv_gptr'right) & gptr_scan_in; +gptr_scan_out <= sov_gptr(0) and an_ac_scan_dis_dc_b; + +end architecture xuq_spr; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_spr_cspr.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_spr_cspr.vhdl new file mode 100644 index 0000000..282e591 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_spr_cspr.vhdl @@ -0,0 +1,4778 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee,ibm,support,work,tri; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use support.power_logic_pkg.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use tri.tri_latches_pkg.all; +use work.xuq_pkg.all; + +entity xuq_spr_cspr is +generic( + hvmode : integer := 1; + a2mode : integer := 1; + expand_type : integer := 2; + threads : integer := 4; + regsize : integer := 64; + eff_ifar : integer := 62; + spr_xucr0_init_mod : integer := 0); +port( + nclk : in clk_logic; + + an_ac_reservation_vld : in std_ulogic_vector(0 to threads-1); + an_ac_tb_update_enable : in std_ulogic; + an_ac_tb_update_pulse : in std_ulogic; + an_ac_sleep_en : in std_ulogic_vector(0 to threads-1); + an_ac_coreid : in std_ulogic_vector(54 to 61); + spr_pvr_version_dc : in std_ulogic_vector(8 to 15); + spr_pvr_revision_dc : in std_ulogic_vector(12 to 15); + pc_xu_instr_trace_mode : in std_ulogic; + pc_xu_instr_trace_tid : in std_ulogic_vector(0 to 1); + instr_trace_mode : out std_ulogic_vector(0 to threads-1); + + d_mode_dc : in std_ulogic; + delay_lclkr_dc : in std_ulogic_vector(0 to 0); + mpw1_dc_b : in std_ulogic_vector(0 to 0); + mpw2_dc_b : in std_ulogic; + + bcfg_sl_force : in std_ulogic; + bcfg_sl_thold_0_b : in std_ulogic; + bcfg_slp_sl_force : in std_ulogic; + bcfg_slp_sl_thold_0_b : in std_ulogic; + ccfg_sl_force : in std_ulogic; + ccfg_sl_thold_0_b : in std_ulogic; + func_sl_force : in std_ulogic; + func_sl_thold_0_b : in std_ulogic; + func_slp_sl_force : in std_ulogic; + func_slp_sl_thold_0_b : in std_ulogic; + func_nsl_force : in std_ulogic; + func_nsl_thold_0_b : in std_ulogic; + func_slp_nsl_force : in std_ulogic; + func_slp_nsl_thold_0_b : in std_ulogic; + sg_0 : in std_ulogic; + scan_in : in std_ulogic_vector(0 to 1); + scan_out : out std_ulogic_vector(0 to 1); + bcfg_scan_in : in std_ulogic; + bcfg_scan_out : out std_ulogic; + ccfg_scan_in : in std_ulogic; + ccfg_scan_out : out std_ulogic; + + cspr_tspr_rf1_act : out std_ulogic; + + dec_spr_rf0_tid : in std_ulogic_vector(0 to threads-1); + dec_spr_rf0_instr : in std_ulogic_vector(0 to 31); + dec_spr_rf1_val : in std_ulogic_vector(0 to 3); + dec_spr_ex4_val : in std_ulogic_vector(0 to threads-1); + + tspr_cspr_ex3_tspr_rt : in std_ulogic_vector(0 to regsize*threads-1); + spr_byp_ex3_spr_rt : out std_ulogic_vector(64-regsize to 63); + + fxu_spr_ex1_rs0 : in std_ulogic_vector(52 to 63); + fxu_spr_ex1_rs1 : in std_ulogic_vector(54 to 63); + mux_spr_ex2_rt : in std_ulogic_vector(64-regsize to 63); + ex5_spr_wd : out std_ulogic_vector(64-regsize to 64+8-(64/regsize)); + + cspr_tspr_ex2_tid : out std_ulogic_vector(0 to threads-1); + cspr_tspr_ex1_instr : out std_ulogic_vector(0 to 31); + cspr_tspr_ex5_is_mtmsr : out std_ulogic; + cspr_tspr_ex5_is_mtspr : out std_ulogic; + cspr_tspr_ex5_is_wrtee : out std_ulogic; + cspr_tspr_ex5_is_wrteei : out std_ulogic; + cspr_tspr_ex5_instr : out std_ulogic_vector(11 to 20); + cspr_tspr_dec_dbg_dis : out std_ulogic_vector(0 to threads-1); + + tspr_cspr_illeg_mtspr_b : in std_ulogic_vector(0 to threads-1); + tspr_cspr_illeg_mfspr_b : in std_ulogic_vector(0 to threads-1); + tspr_cspr_hypv_mtspr : in std_ulogic_vector(0 to threads-1); + tspr_cspr_hypv_mfspr : in std_ulogic_vector(0 to threads-1); + + cspr_aspr_ex5_we : out std_ulogic; + cspr_aspr_ex5_waddr : out std_ulogic_vector(0 to 5); + cspr_aspr_rf1_re : out std_ulogic; + cspr_aspr_rf1_raddr : out std_ulogic_vector(0 to 5); + aspr_cspr_ex1_rdata : in std_ulogic_vector(64-regsize to 72-(64/regsize)); + + xu_lsu_slowspr_val : out std_ulogic; + xu_lsu_slowspr_rw : out std_ulogic; + xu_lsu_slowspr_etid : out std_ulogic_vector(0 to 1); + xu_lsu_slowspr_addr : out std_ulogic_vector(11 to 20); + xu_lsu_slowspr_data : out std_ulogic_vector(64-regsize to 63); + + ac_an_dcr_act : out std_ulogic; + ac_an_dcr_val : out std_ulogic; + ac_an_dcr_read : out std_ulogic; + ac_an_dcr_user : out std_ulogic; + ac_an_dcr_etid : out std_ulogic_vector(0 to 1); + ac_an_dcr_addr : out std_ulogic_vector(11 to 20); + ac_an_dcr_data : out std_ulogic_vector(64-regsize to 63); + + xu_ex4_flush : in std_ulogic_vector(0 to threads-1); + xu_ex5_flush : in std_ulogic_vector(0 to threads-1); + + spr_cpl_ex3_spr_hypv : out std_ulogic; + spr_cpl_ex3_spr_illeg : out std_ulogic; + spr_cpl_ex3_spr_priv : out std_ulogic; + + cspr_tspr_timebase_taps : out std_ulogic_vector(0 to 9); + timer_update : out std_ulogic; + + cpl_spr_stop : in std_ulogic_vector(0 to threads-1); + xu_iu_run_thread : out std_ulogic_vector(0 to threads-1); + spr_cpl_ex2_run_ctl_flush : out std_ulogic_vector(0 to threads-1); + xu_pc_spr_ccr0_we : out std_ulogic_vector(0 to threads-1); + + iu_xu_quiesce : in std_ulogic_vector(0 to threads-1); + lsu_xu_quiesce : in std_ulogic_vector(0 to threads-1); + mm_xu_quiesce : in std_ulogic_vector(0 to threads-1); + bx_xu_quiesce : in std_ulogic_vector(0 to threads-1); + cpl_spr_quiesce : in std_ulogic_vector(0 to threads-1); + xu_pc_running : out std_ulogic_vector(0 to threads-1); + spr_cpl_quiesce : out std_ulogic_vector(0 to threads-1); + + pc_xu_extirpts_dis_on_stop : in std_ulogic; + pc_xu_timebase_dis_on_stop : in std_ulogic; + pc_xu_decrem_dis_on_stop : in std_ulogic; + + pc_xu_ram_mode : in std_ulogic; + pc_xu_ram_thread : in std_ulogic_vector(0 to 1); + pc_xu_msrovride_enab : in std_ulogic; + cspr_tspr_msrovride_en : out std_ulogic_vector(0 to threads-1); + cspr_tspr_ram_mode : out std_ulogic_vector(0 to threads-1); + + cspr_tspr_llen : out std_ulogic_vector(0 to threads-1); + cspr_tspr_llpri : out std_ulogic_vector(0 to threads-1); + tspr_cspr_lldet : in std_ulogic_vector(0 to threads-1); + tspr_cspr_llpulse : in std_ulogic_vector(0 to threads-1); + + pc_xu_reset_wd_complete : in std_ulogic; + pc_xu_reset_3_complete : in std_ulogic; + pc_xu_reset_2_complete : in std_ulogic; + pc_xu_reset_1_complete : in std_ulogic; + reset_wd_complete : out std_ulogic; + reset_3_complete : out std_ulogic; + reset_2_complete : out std_ulogic; + reset_1_complete : out std_ulogic; + + cspr_tspr_crit_mask : out std_ulogic_vector(0 to threads-1); + cspr_tspr_ext_mask : out std_ulogic_vector(0 to threads-1); + cspr_tspr_dec_mask : out std_ulogic_vector(0 to threads-1); + cspr_tspr_fit_mask : out std_ulogic_vector(0 to threads-1); + cspr_tspr_wdog_mask : out std_ulogic_vector(0 to threads-1); + cspr_tspr_udec_mask : out std_ulogic_vector(0 to threads-1); + cspr_tspr_perf_mask : out std_ulogic_vector(0 to threads-1); + + tspr_cspr_pm_wake_up : in std_ulogic_vector(0 to threads-1); + + spr_cpl_dbell_interrupt : out std_ulogic_vector(0 to threads-1); + spr_cpl_cdbell_interrupt : out std_ulogic_vector(0 to threads-1); + spr_cpl_gdbell_interrupt : out std_ulogic_vector(0 to threads-1); + spr_cpl_gcdbell_interrupt : out std_ulogic_vector(0 to threads-1); + spr_cpl_gmcdbell_interrupt : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_dbell_taken : in std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_cdbell_taken : in std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_gdbell_taken : in std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_gcdbell_taken : in std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_gmcdbell_taken : in std_ulogic_vector(0 to threads-1); + + lsu_xu_dbell_val : in std_ulogic; + lsu_xu_dbell_type : in std_ulogic_vector(0 to 4); + lsu_xu_dbell_brdcast : in std_ulogic; + lsu_xu_dbell_lpid_match : in std_ulogic; + lsu_xu_dbell_pirtag : in std_ulogic_vector(50 to 63); + cspr_tspr_dbell_pirtag : out std_ulogic_vector(50 to 63); + tspr_cspr_gpir_match : in std_ulogic_vector(0 to threads-1); + + xu_pc_err_sprg_ecc : out std_ulogic_vector(0 to threads-1); + spr_cpl_ex3_sprg_ce : out std_ulogic; + spr_cpl_ex3_sprg_ue : out std_ulogic; + pc_xu_inj_sprg_ecc : in std_ulogic_vector(0 to threads-1); + + tspr_cspr_freeze_timers : in std_ulogic_vector(0 to threads-1); + tspr_cspr_async_int : in std_ulogic_vector(0 to 3*threads-1); + + + spr_perf_tx_events : out std_ulogic_vector(0 to 8*threads-1); + + xu_lsu_mtspr_trace_en : out std_ulogic_vector(0 to threads-1); + + lsu_xu_spr_xucr0_cslc_xuop : in std_ulogic; + lsu_xu_spr_xucr0_cslc_binv : in std_ulogic; + lsu_xu_spr_xucr0_clo : in std_ulogic; + lsu_xu_spr_xucr0_cul : in std_ulogic; + tspr_msr_ee : in std_ulogic_vector(0 to threads-1); + tspr_msr_ce : in std_ulogic_vector(0 to threads-1); + tspr_msr_me : in std_ulogic_vector(0 to threads-1); + tspr_msr_gs : in std_ulogic_vector(0 to threads-1); + tspr_msr_pr : in std_ulogic_vector(0 to threads-1); + cspr_xucr0_clkg_ctl : out std_ulogic_vector(0 to 4); + xu_lsu_spr_xucr0_clfc : out std_ulogic; + spr_bit_act : out std_ulogic; + xu_pc_spr_ccr0_pme : out std_ulogic_vector(0 to 1); + spr_ccr2_en_dcr : out std_ulogic; + spr_ccr2_en_pc : out std_ulogic; + xu_iu_spr_ccr2_ifratsc : out std_ulogic_vector(0 to 8); + xu_iu_spr_ccr2_ifrat : out std_ulogic; + xu_lsu_spr_ccr2_dfratsc : out std_ulogic_vector(0 to 8); + xu_lsu_spr_ccr2_dfrat : out std_ulogic; + spr_ccr2_ucode_dis : out std_ulogic; + spr_ccr2_ap : out std_ulogic_vector(0 to 3); + spr_ccr2_en_attn : out std_ulogic; + spr_ccr2_en_ditc : out std_ulogic; + spr_ccr2_en_icswx : out std_ulogic; + spr_ccr2_notlb : out std_ulogic; + xu_lsu_spr_xucr0_mbar_ack : out std_ulogic; + xu_lsu_spr_xucr0_tlbsync : out std_ulogic; + spr_dec_spr_xucr0_ssdly : out std_ulogic_vector(0 to 4); + spr_xucr0_cls : out std_ulogic; + xu_lsu_spr_xucr0_aflsta : out std_ulogic; + spr_xucr0_mddp : out std_ulogic; + xu_lsu_spr_xucr0_cred : out std_ulogic; + xu_lsu_spr_xucr0_rel : out std_ulogic; + spr_xucr0_mdcp : out std_ulogic; + xu_lsu_spr_xucr0_flsta : out std_ulogic; + xu_lsu_spr_xucr0_l2siw : out std_ulogic; + xu_lsu_spr_xucr0_flh2l2 : out std_ulogic; + xu_lsu_spr_xucr0_dcdis : out std_ulogic; + xu_lsu_spr_xucr0_wlk : out std_ulogic; + + cspr_debug0 : out std_ulogic_vector(0 to 39); + cspr_debug1 : out std_ulogic_vector(0 to 87); + + vdd : inout power_logic; + gnd : inout power_logic +); + +-- synopsys translate_off + +-- synopsys translate_on +end xuq_spr_cspr; +architecture xuq_spr_cspr of xuq_spr_cspr is + +constant DRF1 : natural := 0; +constant DEX1 : natural := 0; +constant DEX2 : natural := 0; +constant DEX3 : natural := 0; +constant DEX4 : natural := 0; +constant DEX5 : natural := 0; +constant DEX6 : natural := 0; +constant DWR : natural := 0; +constant DX : natural := 0; +constant a2hvmode : natural := ((a2mode+hvmode) mod 1); +subtype TID is std_ulogic_vector(0 to threads-1); +subtype DO is std_ulogic_vector(65-regsize to 64); +signal ccr0_d , ccr0_q : std_ulogic_vector(58 to 63); +signal ccr1_d , ccr1_q : std_ulogic_vector(40 to 63); +signal ccr2_d , ccr2_q : std_ulogic_vector(32 to 63); +signal tbl_d , tbl_q : std_ulogic_vector(32 to 63); +signal tbu_d , tbu_q : std_ulogic_vector(32 to 63); +signal tens_d , tens_q : std_ulogic_vector(60 to 63); +signal xucr0_d , xucr0_q : std_ulogic_vector(33 to 63); +constant ccr1_offset : natural := 0; +constant tbl_offset : natural := ccr1_offset + ccr1_q'length; +constant tbu_offset : natural := tbl_offset + tbl_q'length; +constant last_reg_offset : natural := tbu_offset + tbu_q'length; +constant ccr0_offset_bcfg : natural := 0; +constant tens_offset_bcfg : natural := ccr0_offset_bcfg + ccr0_q'length; +constant last_reg_offset_bcfg : natural := tens_offset_bcfg + tens_q'length; +constant ccr2_offset_ccfg : natural := 0; +constant xucr0_offset_ccfg : natural := ccr2_offset_ccfg + ccr2_q'length; +constant last_reg_offset_ccfg : natural := xucr0_offset_ccfg + xucr0_q'length; +constant last_reg_offset_dcfg : natural := 1; +signal exx_act_q, exx_act_d : std_ulogic_vector(0 to 5); +signal rf1_instr_q : std_ulogic_vector(0 to 31); +signal rf1_aspr_act_q, rf1_aspr_act_d : std_ulogic; +signal rf1_aspr_tid_q, rf1_aspr_tid_d : std_ulogic_vector(0 to 1); +signal rf1_msr_gs_q, rf1_msr_gs_d : std_ulogic; +signal ex1_tid_q, rf1_tid : std_ulogic_vector(0 to 1); +signal ex1_is_mfspr_q, rf1_is_mfspr : std_ulogic; +signal ex1_is_mtspr_q, rf1_is_mtspr : std_ulogic; +signal ex1_instr_q : std_ulogic_vector(0 to 31); +signal ex1_aspr_re_q, rf1_aspr_re : std_ulogic_vector(2-regsize/32 to 1); +signal ex1_aspr_ce_addr_q, rf1_aspr_addr : std_ulogic_vector(0 to 3); +signal ex2_tid_q : std_ulogic_vector(0 to 1); +signal ex2_is_mfmsr_q, ex1_is_mfmsr : std_ulogic; +signal ex2_is_mfspr_q : std_ulogic; +signal ex2_is_mftb_q, ex1_is_mftb : std_ulogic; +signal ex2_is_mtmsr_q, ex1_is_mtmsr : std_ulogic; +signal ex2_is_mtspr_q : std_ulogic; +signal ex2_is_wait_q, ex1_is_wait : std_ulogic; +signal ex2_wait_wc_q : std_ulogic_vector(9 to 10); +signal ex2_is_msgclr_q, ex1_is_msgclr : std_ulogic; +signal ex2_instr_q, ex2_instr_d : std_ulogic_vector(11 to 20); +signal ex2_rs0_q : std_ulogic_vector(52 to 63); +signal ex2_msr_gs_q, ex2_msr_gs_d : std_ulogic_vector(0 to 0); +signal ex2_tenc_we_q, ex1_tenc_we : std_ulogic; +signal ex2_ccr0_we_q, ex1_ccr0_we : std_ulogic; +signal ex2_aspr_rdata_q, ex2_aspr_rdata_d : std_ulogic_vector(aspr_cspr_ex1_rdata'range); +signal ex2_dcrn_q : std_ulogic_vector(54 to 63); +signal ex2_dcr_val_q, ex1_dcr_val : std_ulogic; +signal ex2_aspr_ce_addr_q : std_ulogic_vector(0 to 3); +signal ex2_aspr_re_q : std_ulogic_vector(2-regsize/32 to 1); +signal ex2_dcr_read_q, ex1_dcr_read : std_ulogic; +signal ex2_dcr_user_q, ex1_dcr_user : std_ulogic; +signal ex2_is_wrtee_q, ex1_is_wrtee : std_ulogic; +signal ex2_is_wrteei_q, ex1_is_wrteei : std_ulogic; +signal ex3_tid_q : std_ulogic_vector(0 to 1); +signal ex3_is_mtmsr_q : std_ulogic; +signal ex3_is_mtspr_q : std_ulogic; +signal ex3_wait_wc_q : std_ulogic_vector(9 to 10); +signal ex3_is_msgclr_q : std_ulogic; +signal ex3_instr_q, ex3_instr_d : std_ulogic_vector(11 to 20); +signal ex3_cspr_rt_q, ex2_cspr_rt : std_ulogic_vector(64-regsize to 63); +signal ex3_hypv_spr_q, ex3_hypv_spr_d : std_ulogic; +signal ex3_illeg_spr_q, ex3_illeg_spr_d : std_ulogic; +signal ex3_priv_spr_q, ex3_priv_spr_d : std_ulogic; +signal ex3_sspr_val_q, ex2_sspr_val : std_ulogic; +signal ex3_rt_q : std_ulogic_vector(64-regsize to 63); +signal ex3_is_mfspr_q : std_ulogic; +signal ex3_wait_q, ex2_wait : std_ulogic; +signal ex3_corr_rdata_q, ex2_corr_rdata : std_ulogic_vector(64-regsize to 63); +signal ex3_sprg_ce_q, ex2_sprg_ce : std_ulogic; +signal ex3_sprg_ue_q, ex2_sprg_ue : std_ulogic; +signal ex3_aspr_ce_addr_q : std_ulogic_vector(0 to 3); +signal ex3_dcr_read_q : std_ulogic; +signal ex3_aspr_re_q : std_ulogic_vector(2-regsize/32 to 1); +signal ex3_dcr_val_q : std_ulogic; +signal ex3_dcr_user_q : std_ulogic; +signal ex3_is_wrtee_q : std_ulogic; +signal ex3_is_wrteei_q : std_ulogic; +signal ex3_msr_gs_q, ex3_msr_gs_d : std_ulogic; +signal ex4_tid_q : std_ulogic_vector(0 to 1); +signal ex4_is_mtmsr_q : std_ulogic; +signal ex4_is_mtspr_q : std_ulogic; +signal ex4_wait_wc_q : std_ulogic_vector(9 to 10); +signal ex4_is_msgclr_q : std_ulogic; +signal ex4_instr_q : std_ulogic_vector(11 to 20); +signal ex4_sspr_val_q : std_ulogic; +signal ex4_rt_q : std_ulogic_vector(64-regsize to 63); +signal ex4_is_mfspr_q : std_ulogic; +signal ex4_dcr_read_q : std_ulogic; +signal ex4_wait_q : std_ulogic; +signal ex4_corr_rdata_q : std_ulogic_vector(64-regsize to 63); +signal ex4_sprg_ce_q, ex4_sprg_ce_d : std_ulogic_vector(0 to regsize/8); +signal ex4_aspr_ce_addr_q : std_ulogic_vector(0 to 3); +signal ex4_dcr_val_q : std_ulogic; +signal ex4_dcr_user_q : std_ulogic; +signal ex4_is_wrtee_q : std_ulogic; +signal ex4_is_wrteei_q : std_ulogic; +signal ex4_aspr_we_q, ex3_aspr_we : std_ulogic; +signal ex4_aspr_addr_q, ex3_aspr_addr : std_ulogic_vector(0 to 3); +signal ex5_val_q, ex5_val_d : std_ulogic_vector(0 to threads-1); +signal ex5_tid_q : std_ulogic_vector(0 to 1); +signal ex5_is_mtmsr_q : std_ulogic; +signal ex5_is_mtspr_q : std_ulogic; +signal ex5_wait_wc_q : std_ulogic_vector(9 to 10); +signal ex5_is_msgclr_q : std_ulogic; +signal ex5_instr_q : std_ulogic_vector(11 to 20); +signal ex5_sspr_val_q : std_ulogic; +signal ex5_aspr_we_q, ex5_aspr_we_d : std_ulogic_vector(0 to threads-1); +signal ex5_rt_q, ex5_rt_d : std_ulogic_vector(64-regsize to 64+8-(64/regsize)); +signal ex5_rt_q_b : std_ulogic_vector(64-regsize to 64+8-(64/regsize)); +signal ex5_wait_q : std_ulogic; +signal ex5_sprg_ce_q : std_ulogic; +signal ex5_dcr_val_q, ex4_dcr_val : std_ulogic; +signal ex5_dcr_read_q : std_ulogic; +signal ex5_dcr_user_q : std_ulogic; +signal ex5_aspr_addr_q, ex5_aspr_addr_d : std_ulogic_vector(0 to 3); +signal ex5_is_wrtee_q : std_ulogic; +signal ex5_is_wrteei_q : std_ulogic; +signal ex6_valid_q, ex5_valid : std_ulogic_vector(0 to threads-1); +signal ex6_val_q, ex5_val : std_ulogic; +signal ex6_tid_q : std_ulogic_vector(0 to 1); +signal ex6_dbell_taken_q : std_ulogic_vector(0 to threads-1); +signal ex6_cdbell_taken_q : std_ulogic_vector(0 to threads-1); +signal ex6_gdbell_taken_q : std_ulogic_vector(0 to threads-1); +signal ex6_gcdbell_taken_q : std_ulogic_vector(0 to threads-1); +signal ex6_gmcdbell_taken_q : std_ulogic_vector(0 to threads-1); +signal ex6_rt_q : std_ulogic_vector(64-regsize to 63); +signal ex6_instr_q : std_ulogic_vector(11 to 20); +signal ex6_is_mtspr_q : std_ulogic; +signal ex6_wait_wc_q : std_ulogic_vector(9 to 10); +signal ex6_is_msgclr_q : std_ulogic; +signal ex6_sspr_val_q : std_ulogic; +signal ex6_set_xucr0_cslc_q, ex6_set_xucr0_cslc_d : std_ulogic; +signal ex6_set_xucr0_cul_q, ex6_set_xucr0_cul_d : std_ulogic; +signal ex6_set_xucr0_clo_q, ex6_set_xucr0_clo_d : std_ulogic; +signal ex6_wait_q : std_ulogic; +signal ex6_sprg_ce_q, ex5_sprg_ce : std_ulogic_vector(0 to threads-1); +signal ex6_dcr_val_q, ex5_dcr_val : std_ulogic; +signal ex6_dcr_read_q : std_ulogic; +signal ex6_dcr_user_q : std_ulogic; +signal ex2_any_mfspr_q, ex2_any_mfspr_d : std_ulogic; +signal ex2_any_mtspr_q, ex2_any_mtspr_d : std_ulogic; +signal ex3_any_mfspr_q : std_ulogic; +signal ex3_any_mtspr_q : std_ulogic; +signal ex4_any_mfspr_q : std_ulogic; +signal ex4_any_mtspr_q : std_ulogic; +signal ex5_any_mfspr_q : std_ulogic; +signal ex5_any_mtspr_q : std_ulogic; +signal running_q, running_d : std_ulogic_vector(0 to threads-1); +signal llpri_q, llpri_d : std_ulogic_vector(0 to threads-1); +signal dec_dbg_dis_q, dec_dbg_dis_d : std_ulogic_vector(0 to threads-1); +signal tb_dbg_dis_q, tb_dbg_dis_d : std_ulogic; +signal tb_act_q, tb_act_d : std_ulogic; +signal ext_dbg_dis_q, ext_dbg_dis_d : std_ulogic_vector(0 to threads-1); +signal ram_mode_q : std_ulogic; +signal ram_thread_q : std_ulogic_vector(0 to 1); +signal msrovride_enab_q : std_ulogic; +signal waitimpl_val_q, waitimpl_val_d : std_ulogic_vector(0 to threads-1); +signal waitrsv_val_q, waitrsv_val_d : std_ulogic_vector(0 to threads-1); +signal an_ac_reservation_vld_q : std_ulogic_vector(0 to threads-1); +signal an_ac_sleep_en_q : std_ulogic_vector(0 to threads-1); +signal an_ac_coreid_q : std_ulogic_vector(54 to 61); +signal tb_update_enable_q : std_ulogic; +signal tb_update_pulse_q : std_ulogic; +signal tb_update_pulse_1_q : std_ulogic; +signal pc_xu_reset_wd_complete_q : std_ulogic; +signal pc_xu_reset_3_complete_q : std_ulogic; +signal pc_xu_reset_2_complete_q : std_ulogic; +signal pc_xu_reset_1_complete_q : std_ulogic; +signal lsu_xu_dbell_val_q : std_ulogic; +signal lsu_xu_dbell_type_q : std_ulogic_vector(0 to 4); +signal lsu_xu_dbell_brdcast_q : std_ulogic; +signal lsu_xu_dbell_lpid_match_q : std_ulogic; +signal lsu_xu_dbell_pirtag_q : std_ulogic_vector(50 to 63); +signal dbell_present_q, dbell_present_d : std_ulogic_vector(0 to threads-1); +signal cdbell_present_q, cdbell_present_d : std_ulogic_vector(0 to threads-1); +signal gdbell_present_q, gdbell_present_d : std_ulogic_vector(0 to threads-1); +signal gcdbell_present_q, gcdbell_present_d : std_ulogic_vector(0 to threads-1); +signal gmcdbell_present_q, gmcdbell_present_d : std_ulogic_vector(0 to threads-1); +signal xucr0_clfc_q, xucr0_clfc_d : std_ulogic; +signal iu_run_thread_q, iu_run_thread_d : std_ulogic_vector(0 to threads-1); +signal perf_event_q, perf_event_d : std_ulogic_vector(0 to 3*threads-1); +signal inj_sprg_ecc_q : std_ulogic_vector(0 to threads-1); +signal dbell_interrupt_q, dbell_interrupt : std_ulogic_vector(0 to threads-1); +signal cdbell_interrupt_q, cdbell_interrupt : std_ulogic_vector(0 to threads-1); +signal gdbell_interrupt_q, gdbell_interrupt : std_ulogic_vector(0 to threads-1); +signal gcdbell_interrupt_q, gcdbell_interrupt : std_ulogic_vector(0 to threads-1); +signal gmcdbell_interrupt_q, gmcdbell_interrupt : std_ulogic_vector(0 to threads-1); +signal iu_quiesce_q : std_ulogic_vector(0 to threads-1); +signal lsu_quiesce_q : std_ulogic_vector(0 to threads-1); +signal mm_quiesce_q : std_ulogic_vector(0 to threads-1); +signal bx_quiesce_q : std_ulogic_vector(0 to threads-1); +signal quiesce_q, quiesce_d : std_ulogic_vector(0 to threads-1); +signal cpl_quiesce_q, cpl_quiesce_d : std_ulogic_vector(0 to threads-1); +signal quiesced_4cpl_q, quiesced_4cpl_d : std_ulogic_vector(0 to threads-1); +signal quiesced_q, quiesced_d : std_ulogic_vector(0 to threads-1); +signal instr_trace_mode_q : std_ulogic; +signal instr_trace_tid_q : std_ulogic_vector(0 to 1); +signal timer_update_q : std_ulogic; +signal spare_0_q, spare_0_d : std_ulogic_vector(0 to 15); +constant exx_act_offset : integer := last_reg_offset; +constant rf1_instr_offset : integer := exx_act_offset + exx_act_q'length; +constant rf1_aspr_act_offset : integer := rf1_instr_offset + rf1_instr_q'length; +constant rf1_aspr_tid_offset : integer := rf1_aspr_act_offset + 1; +constant rf1_msr_gs_offset : integer := rf1_aspr_tid_offset + rf1_aspr_tid_q'length; +constant ex1_tid_offset : integer := rf1_msr_gs_offset + 1; +constant ex1_is_mfspr_offset : integer := ex1_tid_offset + ex1_tid_q'length; +constant ex1_is_mtspr_offset : integer := ex1_is_mfspr_offset + 1; +constant ex1_instr_offset : integer := ex1_is_mtspr_offset + 1; +constant ex1_aspr_re_offset : integer := ex1_instr_offset + ex1_instr_q'length; +constant ex1_aspr_ce_addr_offset : integer := ex1_aspr_re_offset + ex1_aspr_re_q'length; +constant ex2_aspr_rdata_offset : integer := ex1_aspr_ce_addr_offset + ex1_aspr_ce_addr_q'length; +constant ex3_tid_offset : integer := ex2_aspr_rdata_offset + ex2_aspr_rdata_q'length; +constant ex3_is_mtmsr_offset : integer := ex3_tid_offset + ex3_tid_q'length; +constant ex3_is_mtspr_offset : integer := ex3_is_mtmsr_offset + 1; +constant ex3_wait_wc_offset : integer := ex3_is_mtspr_offset + 1; +constant ex3_is_msgclr_offset : integer := ex3_wait_wc_offset + ex3_wait_wc_q'length; +constant ex3_instr_offset : integer := ex3_is_msgclr_offset + 1; +constant ex3_cspr_rt_offset : integer := ex3_instr_offset + ex3_instr_q'length; +constant ex3_hypv_spr_offset : integer := ex3_cspr_rt_offset + ex3_cspr_rt_q'length; +constant ex3_illeg_spr_offset : integer := ex3_hypv_spr_offset + 1; +constant ex3_priv_spr_offset : integer := ex3_illeg_spr_offset + 1; +constant ex3_sspr_val_offset : integer := ex3_priv_spr_offset + 1; +constant ex3_rt_offset : integer := ex3_sspr_val_offset + 1; +constant ex3_is_mfspr_offset : integer := ex3_rt_offset + ex3_rt_q'length; +constant ex3_wait_offset : integer := ex3_is_mfspr_offset + 1; +constant ex3_corr_rdata_offset : integer := ex3_wait_offset + 1; +constant ex3_sprg_ce_offset : integer := ex3_corr_rdata_offset + ex3_corr_rdata_q'length; +constant ex3_sprg_ue_offset : integer := ex3_sprg_ce_offset + 1; +constant ex3_aspr_ce_addr_offset : integer := ex3_sprg_ue_offset + 1; +constant ex3_dcr_read_offset : integer := ex3_aspr_ce_addr_offset + ex3_aspr_ce_addr_q'length; +constant ex3_aspr_re_offset : integer := ex3_dcr_read_offset + 1; +constant ex3_dcr_val_offset : integer := ex3_aspr_re_offset + ex3_aspr_re_q'length; +constant ex3_dcr_user_offset : integer := ex3_dcr_val_offset + 1; +constant ex3_is_wrtee_offset : integer := ex3_dcr_user_offset + 1; +constant ex3_is_wrteei_offset : integer := ex3_is_wrtee_offset + 1; +constant ex3_msr_gs_offset : integer := ex3_is_wrteei_offset + 1; +constant ex4_aspr_we_offset : integer := ex3_msr_gs_offset + 1; +constant ex4_aspr_addr_offset : integer := ex4_aspr_we_offset + 1; +constant ex5_val_offset : integer := ex4_aspr_addr_offset + ex4_aspr_addr_q'length; +constant ex5_tid_offset : integer := ex5_val_offset + ex5_val_q'length; +constant ex5_is_mtmsr_offset : integer := ex5_tid_offset + ex5_tid_q'length; +constant ex5_is_mtspr_offset : integer := ex5_is_mtmsr_offset + 1; +constant ex5_wait_wc_offset : integer := ex5_is_mtspr_offset + 1; +constant ex5_is_msgclr_offset : integer := ex5_wait_wc_offset + ex5_wait_wc_q'length; +constant ex5_instr_offset : integer := ex5_is_msgclr_offset + 1; +constant ex5_sspr_val_offset : integer := ex5_instr_offset + ex5_instr_q'length; +constant ex5_aspr_we_offset : integer := ex5_sspr_val_offset + 1; +constant ex5_rt_offset : integer := ex5_aspr_we_offset + ex5_aspr_we_q'length; +constant ex5_wait_offset : integer := ex5_rt_offset + ex5_rt_q'length; +constant ex5_sprg_ce_offset : integer := ex5_wait_offset + 1; +constant ex5_dcr_val_offset : integer := ex5_sprg_ce_offset + 1; +constant ex5_dcr_read_offset : integer := ex5_dcr_val_offset + 1; +constant ex5_dcr_user_offset : integer := ex5_dcr_read_offset + 1; +constant ex5_aspr_addr_offset : integer := ex5_dcr_user_offset + 1; +constant ex5_is_wrtee_offset : integer := ex5_aspr_addr_offset + ex5_aspr_addr_q'length; +constant ex5_is_wrteei_offset : integer := ex5_is_wrtee_offset + 1; +constant ex3_any_mfspr_offset : integer := ex5_is_wrteei_offset + 1; +constant ex3_any_mtspr_offset : integer := ex3_any_mfspr_offset + 1; +constant ex5_any_mfspr_offset : integer := ex3_any_mtspr_offset + 1; +constant ex5_any_mtspr_offset : integer := ex5_any_mfspr_offset + 1; +constant ex6_valid_offset : integer := ex5_any_mtspr_offset + 1; +constant ex6_val_offset : integer := ex6_valid_offset + ex6_valid_q'length; +constant running_offset : integer := ex6_val_offset + 1; +constant llpri_offset : integer := running_offset + running_q'length; +constant dec_dbg_dis_offset : integer := llpri_offset + llpri_q'length; +constant tb_dbg_dis_offset : integer := dec_dbg_dis_offset + dec_dbg_dis_q'length; +constant tb_act_offset : integer := tb_dbg_dis_offset + 1; +constant ext_dbg_dis_offset : integer := tb_act_offset + 1; +constant ram_mode_offset : integer := ext_dbg_dis_offset + ext_dbg_dis_q'length; +constant ram_thread_offset : integer := ram_mode_offset + 1; +constant msrovride_enab_offset : integer := ram_thread_offset + ram_thread_q'length; +constant waitimpl_val_offset : integer := msrovride_enab_offset + 1; +constant waitrsv_val_offset : integer := waitimpl_val_offset + waitimpl_val_q'length; +constant an_ac_reservation_vld_offset : integer := waitrsv_val_offset + waitrsv_val_q'length; +constant an_ac_sleep_en_offset : integer := an_ac_reservation_vld_offset + an_ac_reservation_vld_q'length; +constant an_ac_coreid_offset : integer := an_ac_sleep_en_offset + an_ac_sleep_en_q'length; +constant tb_update_enable_offset : integer := an_ac_coreid_offset + an_ac_coreid_q'length; +constant tb_update_pulse_offset : integer := tb_update_enable_offset + 1; +constant tb_update_pulse_1_offset : integer := tb_update_pulse_offset + 1; +constant pc_xu_reset_wd_complete_offset : integer := tb_update_pulse_1_offset + 1; +constant pc_xu_reset_3_complete_offset : integer := pc_xu_reset_wd_complete_offset + 1; +constant pc_xu_reset_2_complete_offset : integer := pc_xu_reset_3_complete_offset + 1; +constant pc_xu_reset_1_complete_offset : integer := pc_xu_reset_2_complete_offset + 1; +constant lsu_xu_dbell_val_offset : integer := pc_xu_reset_1_complete_offset + 1; +constant lsu_xu_dbell_type_offset : integer := lsu_xu_dbell_val_offset + 1; +constant lsu_xu_dbell_brdcast_offset : integer := lsu_xu_dbell_type_offset + lsu_xu_dbell_type_q'length; +constant lsu_xu_dbell_lpid_match_offset : integer := lsu_xu_dbell_brdcast_offset + 1; +constant lsu_xu_dbell_pirtag_offset : integer := lsu_xu_dbell_lpid_match_offset + 1; +constant dbell_present_offset : integer := lsu_xu_dbell_pirtag_offset + lsu_xu_dbell_pirtag_q'length; +constant cdbell_present_offset : integer := dbell_present_offset + dbell_present_q'length; +constant gdbell_present_offset : integer := cdbell_present_offset + cdbell_present_q'length; +constant gcdbell_present_offset : integer := gdbell_present_offset + gdbell_present_q'length; +constant gmcdbell_present_offset : integer := gcdbell_present_offset + gcdbell_present_q'length; +constant xucr0_clfc_offset : integer := gmcdbell_present_offset + gmcdbell_present_q'length; +constant iu_run_thread_offset : integer := xucr0_clfc_offset + 1; +constant perf_event_offset : integer := iu_run_thread_offset + iu_run_thread_q'length; +constant inj_sprg_ecc_offset : integer := perf_event_offset + perf_event_q'length; +constant dbell_interrupt_offset : integer := inj_sprg_ecc_offset + inj_sprg_ecc_q'length; +constant cdbell_interrupt_offset : integer := dbell_interrupt_offset + dbell_interrupt_q'length; +constant gdbell_interrupt_offset : integer := cdbell_interrupt_offset + cdbell_interrupt_q'length; +constant gcdbell_interrupt_offset : integer := gdbell_interrupt_offset + gdbell_interrupt_q'length; +constant gmcdbell_interrupt_offset : integer := gcdbell_interrupt_offset + gcdbell_interrupt_q'length; +constant iu_quiesce_offset : integer := gmcdbell_interrupt_offset + gmcdbell_interrupt_q'length; +constant lsu_quiesce_offset : integer := iu_quiesce_offset + iu_quiesce_q'length; +constant mm_quiesce_offset : integer := lsu_quiesce_offset + lsu_quiesce_q'length; +constant bx_quiesce_offset : integer := mm_quiesce_offset + mm_quiesce_q'length; +constant quiesce_offset : integer := bx_quiesce_offset + bx_quiesce_q'length; +constant cpl_quiesce_offset : integer := quiesce_offset + quiesce_q'length; +constant quiesced_4cpl_offset : integer := cpl_quiesce_offset + cpl_quiesce_q'length; +constant quiesced_offset : integer := quiesced_4cpl_offset + quiesced_4cpl_q'length; +constant instr_trace_mode_offset : integer := quiesced_offset + quiesced_q'length; +constant instr_trace_tid_offset : integer := instr_trace_mode_offset + 1; +constant timer_update_offset : integer := instr_trace_tid_offset + instr_trace_tid_q'length; +constant spare_0_offset : integer := timer_update_offset + 1; +constant quiesced_ctr_offset : integer := spare_0_offset + spare_0_q'length; +constant quiesced_4cpl_ctr_offset : integer := quiesced_ctr_offset + 1; +constant scan_right : integer := quiesced_4cpl_ctr_offset + 1; +signal siv : std_ulogic_vector(0 to scan_right-1); +signal sov : std_ulogic_vector(0 to scan_right-1); +constant scan_right_bcfg : integer := last_reg_offset_bcfg; +signal siv_bcfg : std_ulogic_vector(0 to scan_right_bcfg-1); +signal sov_bcfg : std_ulogic_vector(0 to scan_right_bcfg-1); +constant scan_right_ccfg : integer := last_reg_offset_ccfg; +signal siv_ccfg : std_ulogic_vector(0 to scan_right_ccfg-1); +signal sov_ccfg : std_ulogic_vector(0 to scan_right_ccfg-1); +signal tiup : std_ulogic; +signal tidn : std_ulogic_vector(00 to 61); +signal spare_0_lclk : clk_logic; +signal spare_0_d1clk, spare_0_d2clk : std_ulogic; +signal tb : std_ulogic_vector(00 to 63); +signal rf1_opcode_is_31, ex1_opcode_is_31 : boolean; +signal rf1_instr : std_ulogic_vector(11 to 20); +signal ex1_tid : std_ulogic_vector(0 to threads-1); +signal ex1_is_mtdcr, ex1_is_mtdcrux, ex1_is_mtdcrx : std_ulogic; +signal ex1_is_mfdcr, ex1_is_mfdcrux, ex1_is_mfdcrx : std_ulogic; +signal ex1_is_mfcr, ex1_is_mtcrf : std_ulogic; +signal ex1_dcr_instr : std_ulogic; +signal ex2_tid : std_ulogic_vector(0 to threads-1); +signal ex2_illeg_mfspr : std_ulogic; +signal ex2_illeg_mtspr : std_ulogic; +signal ex2_illeg_mftb : std_ulogic; +signal ex2_hypv_mfspr : std_ulogic; +signal ex2_hypv_mtspr : std_ulogic; +signal ex2_instr : std_ulogic_vector(11 to 20); +signal ex2_slowspr_range_priv : std_ulogic; +signal ex2_slowspr_range_hypv : std_ulogic; +signal ex2_slowspr_range : std_ulogic; +signal ex2_wait_flush : std_ulogic_vector(0 to threads-1); +signal ex2_ccr0_flush : std_ulogic_vector(0 to threads-1); +signal ex2_tenc_flush : std_ulogic_vector(0 to threads-1); +signal ex3_tspr_rt : std_ulogic_vector(64-regsize to 63); +signal ex4_rt, ex4_rt_inj : std_ulogic_vector(64-regsize to 63); +signal ex4_tid : std_ulogic_vector(0 to threads-1); +signal ex5_tid : std_ulogic_vector(0 to threads-1); +signal ex3_instr : std_ulogic_vector(11 to 20); +signal llunmasked,llmasked : std_ulogic; +signal llpulse,llpres,llpri_inc : std_ulogic; +signal llmask : std_ulogic_vector(0 to threads-1); +signal ram_tid : std_ulogic_vector(0 to threads-1); +signal pm_wake_up : std_ulogic_vector(0 to threads-1); +signal ccr0_di, ccr0_wen : std_ulogic_vector(ccr0_q'range); +signal dbell_pir_match : std_ulogic; +signal dbell_pir_thread : std_ulogic_vector(0 to threads-1); +signal spr_ccr0_we_rev, spr_tens_ten_rev : std_ulogic_vector(0 to threads-1); +signal set_dbell, clr_dbell : std_ulogic_vector(0 to threads-1); +signal set_cdbell, clr_cdbell : std_ulogic_vector(0 to threads-1); +signal set_gdbell, clr_gdbell : std_ulogic_vector(0 to threads-1); +signal set_gcdbell, clr_gcdbell : std_ulogic_vector(0 to threads-1); +signal set_gmcdbell, clr_gmcdbell : std_ulogic_vector(0 to threads-1); +signal tb_update_pulse : std_ulogic; +signal spr_tensr : std_ulogic_vector(0 to threads-1); +signal ex6_instr : std_ulogic_vector(11 to 20); +signal ex6_is_mtspr : std_ulogic; +signal ex6_val : std_ulogic; +signal ex6_tid : std_ulogic_vector(0 to threads-1); +signal tb_q : std_ulogic_vector(0 to 63); +signal crit_mask, base_mask, dec_mask, fit_mask : std_ulogic_vector(0 to threads-1); +signal ex6_wait : std_ulogic_vector(0 to threads-1); +signal ex6_any_valid : std_ulogic; +signal ex5_flush : std_ulogic; +signal xucr0_di : std_ulogic_vector(xucr0_q'range); +signal ex4_eccgen_data : std_ulogic_vector(64-regsize to 72-(64/regsize)); +signal ex4_eccgen_syn : std_ulogic_vector(64 to 72-(64/regsize)); +signal ex2_eccchk_syn, ex2_eccchk_syn_b : std_ulogic_vector(64 to 72-(64/regsize)); +signal ram_mode : std_ulogic_vector(0 to threads-1); +signal ex4_is_mfsspr_b : std_ulogic; +signal encorr : std_ulogic; +signal ex3_sprg_ce : std_ulogic; +signal ex3_aspr_rt : std_ulogic_vector(64-regsize to 63); +signal ex6_spr_wd : std_ulogic_vector(64-regsize to 63); +signal quiesce_ctr_zero_b, cpl_quiesce_ctr_zero_b : std_ulogic_vector(0 to threads-1); +signal quiesce_b_q, cpl_quiesce_b_q : std_ulogic_vector(0 to threads-1); +signal running : std_ulogic_vector(0 to threads-1); +signal timer_update_int : std_ulogic; +signal exx_act : std_ulogic_vector(0 to 5); +signal exx_act_data : std_ulogic_vector(1 to 5); +signal rf0_act : std_ulogic; +signal ex4_inj_ecc : std_ulogic; +signal version : std_ulogic_vector(32 to 47); +signal revision : std_ulogic_vector(48 to 63); +signal revision_minor : std_ulogic_vector(0 to 3); +signal instr_trace_tid : std_ulogic_vector(0 to threads-1); +signal ex3_sprg_ue : std_ulogic; +signal dbell_act : std_ulogic; + +signal spr_ccr0_we : std_ulogic_vector(0 to 3); +signal spr_ccr2_en_dcr_int : std_ulogic; +signal spr_ccr2_en_trace : std_ulogic; +signal spr_tens_ten : std_ulogic_vector(0 to 3); +signal spr_xucr0_clkg_ctl : std_ulogic_vector(0 to 4); +signal spr_xucr0_trace_um : std_ulogic_vector(0 to 3); +signal spr_xucr0_tcs : std_ulogic; +signal ex6_ccr0_di : std_ulogic_vector(ccr0_q'range); +signal ex6_ccr1_di : std_ulogic_vector(ccr1_q'range); +signal ex6_ccr2_di : std_ulogic_vector(ccr2_q'range); +signal ex6_tbl_di : std_ulogic_vector(tbl_q'range); +signal ex6_tbu_di : std_ulogic_vector(tbu_q'range); +signal ex6_tens_di : std_ulogic_vector(tens_q'range); +signal ex6_xucr0_di : std_ulogic_vector(xucr0_q'range); +signal + rf1_gsprg0_re , rf1_gsprg1_re , rf1_gsprg2_re , rf1_gsprg3_re + , rf1_sprg0_re , rf1_sprg1_re , rf1_sprg2_re , rf1_sprg3_re + , rf1_sprg4_re , rf1_sprg5_re , rf1_sprg6_re , rf1_sprg7_re + , rf1_sprg8_re , rf1_vrsave_re + : std_ulogic; +signal + rf1_gsprg0_rdec, rf1_gsprg1_rdec, rf1_gsprg2_rdec, rf1_gsprg3_rdec + , rf1_sprg0_rdec , rf1_sprg1_rdec , rf1_sprg2_rdec , rf1_sprg3_rdec + , rf1_sprg4_rdec , rf1_sprg5_rdec , rf1_sprg6_rdec , rf1_sprg7_rdec + , rf1_sprg8_rdec , rf1_vrsave_rdec + : std_ulogic; +signal + ex2_ccr0_re , ex2_ccr1_re , ex2_ccr2_re , ex2_dac1_re + , ex2_dac2_re , ex2_dac3_re , ex2_dac4_re , ex2_givpr_re + , ex2_iac1_re , ex2_iac2_re , ex2_iac3_re , ex2_iac4_re + , ex2_ivpr_re , ex2_pir_re , ex2_pvr_re , ex2_tb_re + , ex2_tbu_re , ex2_tenc_re , ex2_tens_re , ex2_tensr_re + , ex2_tir_re , ex2_xucr0_re , ex2_xucr3_re , ex2_xucr4_re + : std_ulogic; +signal + ex2_dvc1_re , ex2_dvc2_re , ex2_eplc_re , ex2_epsc_re + , ex2_eptcfg_re , ex2_immr_re , ex2_imr_re , ex2_iucr0_re + , ex2_iucr1_re , ex2_iucr2_re , ex2_iudbg0_re , ex2_iudbg1_re + , ex2_iudbg2_re , ex2_iulfsr_re , ex2_iullcr_re , ex2_lper_re + , ex2_lperu_re , ex2_lpidr_re , ex2_lratcfg_re , ex2_lratps_re + , ex2_mas0_re , ex2_mas0_mas1_re, ex2_mas1_re , ex2_mas2_re + , ex2_mas2u_re , ex2_mas3_re , ex2_mas4_re , ex2_mas5_re + , ex2_mas5_mas6_re, ex2_mas6_re , ex2_mas7_re , ex2_mas7_mas3_re + , ex2_mas8_re , ex2_mas8_mas1_re, ex2_mmucfg_re , ex2_mmucr0_re + , ex2_mmucr1_re , ex2_mmucr2_re , ex2_mmucr3_re , ex2_mmucsr0_re + , ex2_pid_re , ex2_ppr32_re , ex2_tlb0cfg_re , ex2_tlb0ps_re + , ex2_xucr2_re , ex2_xudbg0_re , ex2_xudbg1_re , ex2_xudbg2_re + : std_ulogic; +signal ex2_sprg8_re, ex2_sprg8_we : std_ulogic; +signal + ex2_ccr0_we , ex2_ccr1_we , ex2_ccr2_we , ex2_dac1_we + , ex2_dac2_we , ex2_dac3_we , ex2_dac4_we , ex2_givpr_we + , ex2_iac1_we , ex2_iac2_we , ex2_iac3_we , ex2_iac4_we + , ex2_ivpr_we , ex2_tbl_we , ex2_tbu_we , ex2_tenc_we + , ex2_tens_we , ex2_trace_we , ex2_xucr0_we , ex2_xucr3_we + , ex2_xucr4_we + : std_ulogic; +signal + ex2_dvc1_we , ex2_dvc2_we , ex2_eplc_we , ex2_epsc_we + , ex2_immr_we , ex2_imr_we , ex2_iucr0_we , ex2_iucr1_we + , ex2_iucr2_we , ex2_iudbg0_we , ex2_iulfsr_we , ex2_iullcr_we + , ex2_lper_we , ex2_lperu_we , ex2_lpidr_we , ex2_mas0_we + , ex2_mas0_mas1_we, ex2_mas1_we , ex2_mas2_we , ex2_mas2u_we + , ex2_mas3_we , ex2_mas4_we , ex2_mas5_we , ex2_mas5_mas6_we + , ex2_mas6_we , ex2_mas7_we , ex2_mas7_mas3_we, ex2_mas8_we + , ex2_mas8_mas1_we, ex2_mmucr0_we , ex2_mmucr1_we , ex2_mmucr2_we + , ex2_mmucr3_we , ex2_mmucsr0_we , ex2_pid_we , ex2_ppr32_we + , ex2_xucr2_we , ex2_xudbg0_we + : std_ulogic; +signal + ex2_ccr0_rdec , ex2_ccr1_rdec , ex2_ccr2_rdec , ex2_dac1_rdec + , ex2_dac2_rdec , ex2_dac3_rdec , ex2_dac4_rdec , ex2_givpr_rdec + , ex2_iac1_rdec , ex2_iac2_rdec , ex2_iac3_rdec , ex2_iac4_rdec + , ex2_ivpr_rdec , ex2_pir_rdec , ex2_pvr_rdec , ex2_tb_rdec + , ex2_tbu_rdec , ex2_tenc_rdec , ex2_tens_rdec , ex2_tensr_rdec + , ex2_tir_rdec , ex2_xucr0_rdec , ex2_xucr3_rdec , ex2_xucr4_rdec + : std_ulogic; +signal + ex2_dvc1_rdec , ex2_dvc2_rdec , ex2_eplc_rdec , ex2_epsc_rdec + , ex2_eptcfg_rdec, ex2_immr_rdec , ex2_imr_rdec , ex2_iucr0_rdec + , ex2_iucr1_rdec , ex2_iucr2_rdec , ex2_iudbg0_rdec, ex2_iudbg1_rdec + , ex2_iudbg2_rdec, ex2_iulfsr_rdec, ex2_iullcr_rdec, ex2_lper_rdec + , ex2_lperu_rdec , ex2_lpidr_rdec , ex2_lratcfg_rdec, ex2_lratps_rdec + , ex2_mas0_rdec , ex2_mas0_mas1_rdec, ex2_mas1_rdec , ex2_mas2_rdec + , ex2_mas2u_rdec , ex2_mas3_rdec , ex2_mas4_rdec , ex2_mas5_rdec + , ex2_mas5_mas6_rdec, ex2_mas6_rdec , ex2_mas7_rdec , ex2_mas7_mas3_rdec + , ex2_mas8_rdec , ex2_mas8_mas1_rdec, ex2_mmucfg_rdec, ex2_mmucr0_rdec + , ex2_mmucr1_rdec, ex2_mmucr2_rdec, ex2_mmucr3_rdec, ex2_mmucsr0_rdec + , ex2_pid_rdec , ex2_ppr32_rdec , ex2_tlb0cfg_rdec, ex2_tlb0ps_rdec + , ex2_xucr2_rdec , ex2_xudbg0_rdec, ex2_xudbg1_rdec, ex2_xudbg2_rdec + : std_ulogic; +signal + ex2_gsprg0_rdec, ex2_gsprg1_rdec, ex2_gsprg2_rdec, ex2_gsprg3_rdec + , ex2_sprg0_rdec , ex2_sprg1_rdec , ex2_sprg2_rdec , ex2_sprg3_rdec + , ex2_sprg4_rdec , ex2_sprg5_rdec , ex2_sprg6_rdec , ex2_sprg7_rdec + , ex2_sprg8_rdec , ex2_vrsave_rdec + : std_ulogic; +signal + ex2_ccr0_wdec , ex2_ccr1_wdec , ex2_ccr2_wdec , ex2_dac1_wdec + , ex2_dac2_wdec , ex2_dac3_wdec , ex2_dac4_wdec , ex2_givpr_wdec + , ex2_iac1_wdec , ex2_iac2_wdec , ex2_iac3_wdec , ex2_iac4_wdec + , ex2_ivpr_wdec , ex2_tbl_wdec , ex2_tbu_wdec , ex2_tenc_wdec + , ex2_tens_wdec , ex2_trace_wdec , ex2_xucr0_wdec , ex2_xucr3_wdec + , ex2_xucr4_wdec + : std_ulogic; +signal + ex2_gsprg0_wdec, ex2_gsprg1_wdec, ex2_gsprg2_wdec, ex2_gsprg3_wdec + , ex2_sprg0_wdec , ex2_sprg1_wdec , ex2_sprg2_wdec , ex2_sprg3_wdec + , ex2_sprg4_wdec , ex2_sprg5_wdec , ex2_sprg6_wdec , ex2_sprg7_wdec + , ex2_sprg8_wdec , ex2_vrsave_wdec + : std_ulogic; +signal + ex2_dvc1_wdec , ex2_dvc2_wdec , ex2_eplc_wdec , ex2_epsc_wdec + , ex2_immr_wdec , ex2_imr_wdec , ex2_iucr0_wdec , ex2_iucr1_wdec + , ex2_iucr2_wdec , ex2_iudbg0_wdec, ex2_iulfsr_wdec, ex2_iullcr_wdec + , ex2_lper_wdec , ex2_lperu_wdec , ex2_lpidr_wdec , ex2_mas0_wdec + , ex2_mas0_mas1_wdec, ex2_mas1_wdec , ex2_mas2_wdec , ex2_mas2u_wdec + , ex2_mas3_wdec , ex2_mas4_wdec , ex2_mas5_wdec , ex2_mas5_mas6_wdec + , ex2_mas6_wdec , ex2_mas7_wdec , ex2_mas7_mas3_wdec, ex2_mas8_wdec + , ex2_mas8_mas1_wdec, ex2_mmucr0_wdec, ex2_mmucr1_wdec, ex2_mmucr2_wdec + , ex2_mmucr3_wdec, ex2_mmucsr0_wdec, ex2_pid_wdec , ex2_ppr32_wdec + , ex2_xucr2_wdec , ex2_xudbg0_wdec + : std_ulogic; +signal + ex3_gsprg0_wdec, ex3_gsprg1_wdec, ex3_gsprg2_wdec, ex3_gsprg3_wdec + , ex3_sprg0_wdec , ex3_sprg1_wdec , ex3_sprg2_wdec , ex3_sprg3_wdec + , ex3_sprg4_wdec , ex3_sprg5_wdec , ex3_sprg6_wdec , ex3_sprg7_wdec + , ex3_sprg8_wdec , ex3_vrsave_wdec + : std_ulogic; +signal + ex3_gsprg0_we , ex3_gsprg1_we , ex3_gsprg2_we , ex3_gsprg3_we + , ex3_sprg0_we , ex3_sprg1_we , ex3_sprg2_we , ex3_sprg3_we + , ex3_sprg4_we , ex3_sprg5_we , ex3_sprg6_we , ex3_sprg7_we + , ex3_sprg8_we , ex3_vrsave_we + : std_ulogic; +signal + ex6_ccr0_wdec , ex6_ccr1_wdec , ex6_ccr2_wdec , ex6_tbl_wdec + , ex6_tbu_wdec , ex6_tenc_wdec , ex6_tens_wdec , ex6_xucr0_wdec + : std_ulogic; +signal + ex6_ccr0_we , ex6_ccr1_we , ex6_ccr2_we , ex6_tbl_we + , ex6_tbu_we , ex6_tenc_we , ex6_tens_we , ex6_xucr0_we + : std_ulogic; +signal + ccr0_act , ccr1_act , ccr2_act , pir_act + , pvr_act , tb_act , tbl_act , tbu_act + , tenc_act , tens_act , tensr_act , tir_act + , xucr0_act + : std_ulogic; +signal + ccr0_do , ccr1_do , ccr2_do , pir_do + , pvr_do , tb_do , tbl_do , tbu_do + , tenc_do , tens_do , tensr_do , tir_do + , xucr0_do + : std_ulogic_vector(0 to 64); + +begin + + +tiup <= '1'; +tidn <= (others=>'0'); + +cspr_xucr0_clkg_ctl <= spr_xucr0_clkg_ctl; + +rf1_aspr_act_d <= rf0_act; + +rf0_act <= or_reduce(dec_spr_rf0_tid) or spr_xucr0_clkg_ctl(4); +exx_act_d <= rf0_act & exx_act(0 to 4); + +exx_act(0) <= (exx_act_q(0) and or_reduce(dec_spr_rf1_val)) or spr_xucr0_clkg_ctl(4); +exx_act(1) <= exx_act_q(1); +exx_act(2) <= exx_act_q(2); +exx_act(3) <= exx_act_q(3); +exx_act(4) <= exx_act_q(4); +exx_act(5) <= exx_act_q(5); + +exx_act_data(1) <= exx_act(1); +exx_act_data(2) <= exx_act(2); +exx_act_data(3) <= exx_act(3); +exx_act_data(4) <= exx_act(4); +exx_act_data(5) <= exx_act(5); + +cspr_tspr_rf1_act <= exx_act(0); + +dbell_act <= lsu_xu_dbell_val or spr_xucr0_clkg_ctl(4); + +spr_bit_act <= '1'; + +rf1_opcode_is_31 <= rf1_instr_q(0 to 5) = "011111"; +ex1_opcode_is_31 <= ex1_instr_q(0 to 5) = "011111"; +rf1_is_mfspr <= '1' when rf1_opcode_is_31 and rf1_instr_q(21 to 30) = "0101010011" else '0'; +rf1_is_mtspr <= '1' when rf1_opcode_is_31 and rf1_instr_q(21 to 30) = "0111010011" else '0'; +ex1_is_mfmsr <= '1' when ex1_opcode_is_31 and ex1_instr_q(21 to 30) = "0001010011" else '0'; +ex1_is_mtmsr <= '1' when ex1_opcode_is_31 and ex1_instr_q(21 to 30) = "0010010010" else '0'; +ex1_is_mftb <= '1' when ex1_opcode_is_31 and ex1_instr_q(21 to 30) = "0101110011" else '0'; +ex1_is_wait <= '1' when ex1_opcode_is_31 and ex1_instr_q(21 to 30) = "0000111110" else '0'; +ex1_is_msgclr <= '1' when ex1_opcode_is_31 and ex1_instr_q(21 to 30) = "0011101110" else '0'; +ex1_is_wrtee <= '1' when ex1_opcode_is_31 and ex1_instr_q(21 to 30) = "0010000011" else '0'; +ex1_is_wrteei <= '1' when ex1_opcode_is_31 and ex1_instr_q(21 to 30) = "0010100011" else '0'; +ex1_is_mtdcr <= '1' when ex1_opcode_is_31 and ex1_instr_q(21 to 30) = "0111000011" else '0'; +ex1_is_mtdcrux <= '1' when ex1_opcode_is_31 and ex1_instr_q(21 to 30) = "0110100011" else '0'; +ex1_is_mtdcrx <= '1' when ex1_opcode_is_31 and ex1_instr_q(21 to 30) = "0110000011" else '0'; +ex1_is_mfdcr <= '1' when ex1_opcode_is_31 and ex1_instr_q(21 to 30) = "0101000011" else '0'; +ex1_is_mfdcrux <= '1' when ex1_opcode_is_31 and ex1_instr_q(21 to 30) = "0100100011" else '0'; +ex1_is_mfdcrx <= '1' when ex1_opcode_is_31 and ex1_instr_q(21 to 30) = "0100000011" else '0'; +ex1_is_mfcr <= '1' when ex1_opcode_is_31 and ex1_instr_q(21 to 30) = "0000010011" else '0'; +ex1_is_mtcrf <= '1' when ex1_opcode_is_31 and ex1_instr_q(21 to 30) = "0010010000" else '0'; + +ex1_dcr_instr <= ex1_is_mtdcrux or ex1_is_mtdcrx or ex1_is_mtdcr or ex1_dcr_read; +ex1_dcr_read <= ex1_is_mfdcrux or ex1_is_mfdcrx or ex1_is_mfdcr; +ex1_dcr_user <= ex1_is_mtdcrux or ex1_is_mfdcrux; +ex1_dcr_val <= ex1_dcr_instr and spr_ccr2_en_dcr_int; + +ex2_any_mfspr_d <= ex1_is_mfspr_q or ex1_is_mfmsr or ex1_is_mftb or ex1_is_mfcr; +ex2_any_mtspr_d <= ex1_is_mtspr_q or ex1_is_mtmsr or ex1_is_mtcrf or ex1_is_wrtee or ex1_is_wrteei; + +xu_pc_spr_ccr0_we <= spr_ccr0_we_rev and quiesced_q; +spr_ccr0_we_rev <= reverse(spr_ccr0_we); +spr_tens_ten_rev <= reverse(spr_tens_ten); + +quiesce_b_q <= not (quiesce_q and not running_q); +quiesce_d <= iu_quiesce_q and + lsu_quiesce_q and + mm_quiesce_q and + bx_quiesce_q; + +cpl_quiesce_b_q <= not cpl_quiesce_q; +cpl_quiesce_d <= cpl_spr_quiesce and not running_q; + +quiesced_d <= quiesce_q and not quiesce_ctr_zero_b and + cpl_quiesce_q and not cpl_quiesce_ctr_zero_b; + +xu_pc_running <= running; + +quiesced_4cpl_d <= lsu_quiesce_q; +spr_cpl_quiesce <= quiesced_4cpl_q; + +running <= running_q or not quiesced_q; +running_d <= (cpl_spr_stop nor spr_ccr0_we_rev) and spr_tens_ten_rev; +iu_run_thread_d <= running_q and llmask; +xu_iu_run_thread <= iu_run_thread_q; + +spr_tensr <= spr_tens_ten or reverse(running); + +ex6_any_valid <= or_reduce(ex6_valid_q); +ex1_tenc_we <= (ex1_instr_q(11 to 20) = "1011101101"); +ex1_ccr0_we <= (ex1_instr_q(11 to 20) = "1000011111"); + +pm_wake_up_gen : for t in 0 to threads-1 generate + + +waitimpl_val_d(t) <= '0' when pm_wake_up(t) ='1' else + ex6_wait_wc_q(9) when ex6_wait(t) ='1' else + waitimpl_val_q(t); + +waitrsv_val_d(t) <= '0' when pm_wake_up(t) ='1' else + ex6_wait_wc_q(10) when ex6_wait(t) ='1' else + waitrsv_val_q(t); + +crit_mask(t) <= not(ext_dbg_dis_q(t) or not spr_tens_ten_rev(t) or (spr_ccr0_we_rev(t) and not ccr1_q(60-6*t))); +base_mask(t) <= not(ext_dbg_dis_q(t) or not spr_tens_ten_rev(t) or (spr_ccr0_we_rev(t) and not ccr1_q(61-6*t))); +dec_mask(t) <= not(ext_dbg_dis_q(t) or not spr_tens_ten_rev(t) or (spr_ccr0_we_rev(t) and not ccr1_q(62-6*t))); +fit_mask(t) <= not(ext_dbg_dis_q(t) or not spr_tens_ten_rev(t) or (spr_ccr0_we_rev(t) and not ccr1_q(63-6*t))); + +cspr_tspr_crit_mask(t) <= crit_mask(t); +cspr_tspr_ext_mask(t) <= base_mask(t); +cspr_tspr_dec_mask(t) <= dec_mask(t); +cspr_tspr_fit_mask(t) <= fit_mask(t); +cspr_tspr_wdog_mask(t) <= crit_mask(t); +cspr_tspr_udec_mask(t) <= dec_mask(t); +cspr_tspr_perf_mask(t) <= base_mask(t); + +ex2_wait_flush(t) <= ex2_tid(t) and ex2_is_wait_q and + ((ex2_wait_wc_q = "00") or + (ex2_wait_wc_q = "01" and an_ac_reservation_vld_q(t) and not ccr1_q(58-6*t)) or + (ex2_wait_wc_q = "10" and an_ac_sleep_en_q(t) and not ccr1_q(59-6*t))); + +ex2_ccr0_flush(t) <= ex2_is_mtspr_q and ex2_ccr0_we_q and ex2_rs0_q(55-t) and ex2_rs0_q(63-t); + +ex2_tenc_flush(t) <= ex2_is_mtspr_q and ex2_tenc_we_q and ex2_rs0_q(63-t); + + +end generate; + +ex2_wait <= or_reduce(ex2_wait_flush); + +with s3'(ex2_is_wait_q & ex2_ccr0_we_q & ex2_tenc_we_q) select + spr_cpl_ex2_run_ctl_flush <= ex2_wait_flush when "100", + ex2_ccr0_flush when "010", + ex2_tenc_flush when "001", + (others=>'0') when others; + +pm_wake_up <= (not an_ac_reservation_vld_q and waitrsv_val_q ) or + ( not an_ac_sleep_en_q and waitimpl_val_q) or + tspr_cspr_pm_wake_up or + dbell_interrupt_q or + cdbell_interrupt_q or + gdbell_interrupt_q or + gcdbell_interrupt_q or + gmcdbell_interrupt_q; + +ex6_wait <= gate(ex6_tid,(ex6_any_valid and ex6_wait_q)); + + +tb_dbg_dis_d <= and_reduce(cpl_spr_stop) and pc_xu_timebase_dis_on_stop; +dec_dbg_dis_d <= gate(cpl_spr_stop,pc_xu_decrem_dis_on_stop); +ext_dbg_dis_d <= gate(cpl_spr_stop,pc_xu_extirpts_dis_on_stop); + +cspr_tspr_llen <= running_q; +cspr_tspr_llpri <= llpri_q; +llpres <= or_reduce( tspr_cspr_lldet); +llunmasked <= or_reduce( llpri_q and tspr_cspr_lldet); +llmasked <= or_reduce(not llpri_q and tspr_cspr_lldet); +llpulse <= or_reduce( llpri_q and tspr_cspr_llpulse); + +llpri_inc <= (llpres and not llunmasked) or + (llpulse and llmasked and llunmasked); + +llpri_d <= llpri_q(threads-1) & llpri_q(0 to threads-2); + +llmask <= (llpri_q and tspr_cspr_lldet) or not (0 to threads-1=>llpres); + + + +with s2'(instr_trace_tid_q) select + instr_trace_tid <= "1000" when "00", + "0100" when "01", + "0010" when "10", + "0001" when others; + +instr_trace_mode <= gate(instr_trace_tid,instr_trace_mode_q); + +with s4'(dec_spr_rf0_tid) select + rf1_aspr_tid_d <= "00" when "1000", + "01" when "0100", + "10" when "0010", + "11" when others; + +with dec_spr_rf1_val select + rf1_tid <= "00" when "1000", + "01" when "0100", + "10" when "0010", + "11" when others; +with ex1_tid_q select + ex1_tid <= "1000" when "00", + "0100" when "01", + "0010" when "10", + "0001" when others; +with ex2_tid_q select + ex2_tid <= "1000" when "00", + "0100" when "01", + "0010" when "10", + "0001" when others; + +with ex4_tid_q select + ex4_tid <= "1000" when "00", + "0100" when "01", + "0010" when "10", + "0001" when others; + +with ex5_tid_q select + ex5_tid <= "1000" when "00", + "0100" when "01", + "0010" when "10", + "0001" when others; + +with ex6_tid_q select + ex6_tid <= "1000" when "00", + "0100" when "01", + "0010" when "10", + "0001" when others; +with ram_thread_q select + ram_tid <= "1000" when "00", + "0100" when "01", + "0010" when "10", + "0001" when others; + +rf1_instr <= rf1_instr_q(11 to 20); +ex2_instr_d <= gate(ex1_instr_q(11 to 20),(ex1_is_mfspr_q or ex1_is_mtspr_q or ex1_is_wrteei or ex1_is_wait or ex1_is_mftb)); +ex2_instr <= ex2_instr_q(11 to 20); +ex3_instr_d <= ex2_instr_q or gate(ex2_dcrn_q,ex2_dcr_val_q); + +rf1_msr_gs_d <= or_reduce(tspr_msr_gs and dec_spr_rf0_tid); +ex2_msr_gs_d <= (others=>or_reduce(tspr_msr_gs and ex1_tid)); +ex3_msr_gs_d <= or_reduce(tspr_msr_gs and ex2_tid); + +ex5_val_d <= dec_spr_ex4_val and not xu_ex4_flush; +ex5_valid <= ex5_val_q and not xu_ex5_flush; +ex5_val <= or_reduce(ex5_valid); +ex5_spr_wd <= ex5_rt_q; +ex5_rt_q_b <= ex5_rt_q; +ex3_instr <= ex3_instr_q; + +ex6_val <= ex6_val_q; +ex6_spr_wd <= ex6_rt_q; +ex6_instr <= ex6_instr_q; +ex6_is_mtspr <= ex6_is_mtspr_q; + +ram_mode <= gate(ram_tid,ram_mode_q); +cspr_tspr_ram_mode <= ram_mode; + +cspr_tspr_msrovride_en <= gate(ram_mode,msrovride_enab_q); + +perf_count : for t in 0 to threads-1 generate + perf_event_d(0+3*t) <= running(t); + perf_event_d(1+3*t) <= ex5_valid(t) and ex5_any_mfspr_q; + perf_event_d(2+3*t) <= ex5_valid(t) and ex5_any_mtspr_q; + + spr_perf_tx_events(0+8*t) <= perf_event_q(0+3*t); + spr_perf_tx_events(1+8*t) <= tb_act_q; + spr_perf_tx_events(2+8*t) <= perf_event_q(1+3*t); + spr_perf_tx_events(3+8*t) <= perf_event_q(2+3*t); + spr_perf_tx_events(4+8*t) <= waitrsv_val_q(t); + spr_perf_tx_events(5+8*t) <= tspr_cspr_async_int(0+3*t); + spr_perf_tx_events(6+8*t) <= tspr_cspr_async_int(1+3*t); + spr_perf_tx_events(7+8*t) <= tspr_cspr_async_int(2+3*t); +end generate; + +ccr0_act <= spr_xucr0_clkg_ctl(4) or ex6_ccr0_we or or_reduce(pm_wake_up) or ex6_wait_q; + +ccr0_wen <= (0 to 1=>ex6_ccr0_we) & gate(ex6_spr_wd(56-threads to 55),ex6_ccr0_we); + +ccr0_di <= (ex6_ccr0_di and ccr0_wen) or + ( ccr0_q and not ccr0_wen); + +ccr0_d(62-threads to 63-threads) <= ccr0_di(62-threads to 63-threads); +ccr0_d(64-threads to 63) <= (ccr0_di(64-threads to 63) or reverse(ex6_wait)) and not reverse(pm_wake_up); + +ccr1_act <= ex6_ccr1_we; +ccr1_d <= ex6_ccr1_di; + +ccr2_act <= ex6_ccr2_we; +ccr2_d <= ex6_ccr2_di; + +pir_act <= tiup; + +pvr_act <= tiup; + +version <= x"00" & spr_pvr_version_dc(8 to 15); +revision <= x"0" & spr_pvr_revision_dc(12 to 15) & x"0" & revision_minor; +revision_minor <= x"0"; + +tb_update_pulse <= (tb_update_pulse_q xor tb_update_pulse_1_q); + +timer_update_int <= tb_update_enable_q and (tb_update_pulse or not spr_xucr0_tcs); +timer_update <= timer_update_q; + +tb_act_d <= not tb_dbg_dis_q and + not or_reduce(tspr_cspr_freeze_timers) and + timer_update_int; + +tb_act <= tb_act_q; +tb_q <= tbu_q & tbl_q; +tb <= std_ulogic_vector(unsigned(tb_q)+1); + +tbl_act <= tb_act or ex6_tbl_we; +with (ex6_tbl_we) select + tbl_d <= ex6_tbl_di when '1', + tb(32 to 63) when others; + +tbu_act <= tb_act or ex6_tbu_we; +with (ex6_tbu_we) select + tbu_d <= ex6_tbu_di when '1', + tb(0 to 31) when others; + +tenc_act <= tiup; + +tens_act <= ex6_tenc_we or ex6_tens_we; +tens_d <= (tens_q and not ex6_tens_di) when ex6_tenc_we='1' else + (tens_q or ex6_tens_di); +tensr_act <= tiup; + +tir_act <= tiup; + +ex5_flush <= or_reduce(xu_ex5_flush and ex5_tid); + +ex6_set_xucr0_cslc_d <=(lsu_xu_spr_xucr0_cslc_xuop and not ex5_flush) or + lsu_xu_spr_xucr0_cslc_binv; + +ex6_set_xucr0_cul_d <=(lsu_xu_spr_xucr0_cul and not ex5_flush); + +ex6_set_xucr0_clo_d <= lsu_xu_spr_xucr0_clo; + +xucr0_act <= spr_xucr0_clkg_ctl(4) or ex6_xucr0_we or + ex6_set_xucr0_cslc_q or ex6_set_xucr0_cul_q or ex6_set_xucr0_clo_q; + +xucr0_d <= xucr0_di(xucr0_q'left to 60) & + (xucr0_di(61) or ex6_set_xucr0_cslc_q) & + (xucr0_di(62) or ex6_set_xucr0_cul_q) & + (xucr0_di(63) or ex6_set_xucr0_clo_q); + +with (ex6_xucr0_we) select + xucr0_di <= ex6_xucr0_di when '1', + xucr0_q when others; + + +cspr_tspr_timebase_taps(8) <= tbl_q(32+23); +cspr_tspr_timebase_taps(7) <= tbl_q(32+11); +cspr_tspr_timebase_taps(6) <= tbl_q(32+ 7); +cspr_tspr_timebase_taps(5) <= tbl_q(32+21); +cspr_tspr_timebase_taps(4) <= tbl_q(32+17); +cspr_tspr_timebase_taps(3) <= tbl_q(32+13); +cspr_tspr_timebase_taps(2) <= tbl_q(32+ 9); +cspr_tspr_timebase_taps(1) <= tbl_q(32+ 5); +cspr_tspr_timebase_taps(0) <= tbl_q(32+ 1); + +cspr_tspr_timebase_taps(9) <= tbl_q(32+ 7); + + +cspr_tspr_ex2_tid <= ex2_tid; +cspr_tspr_ex1_instr <= ex1_instr_q; +cspr_tspr_ex5_is_mtmsr <= ex5_is_mtmsr_q; +cspr_tspr_ex5_is_mtspr <= ex5_is_mtspr_q; +cspr_tspr_ex5_instr <= ex5_instr_q; +cspr_tspr_dec_dbg_dis <= dec_dbg_dis_q; + +reset_wd_complete <= pc_xu_reset_wd_complete_q; +reset_3_complete <= pc_xu_reset_3_complete_q; +reset_2_complete <= pc_xu_reset_2_complete_q; +reset_1_complete <= pc_xu_reset_1_complete_q; + +cspr_tspr_ex5_is_wrtee <= ex5_is_wrtee_q; +cspr_tspr_ex5_is_wrteei <= ex5_is_wrteei_q; + +cspr_aspr_ex5_we <= or_reduce(ex5_aspr_we_q and not xu_ex5_flush); +cspr_aspr_ex5_waddr <= ex5_aspr_addr_q & ex5_tid_q; +cspr_aspr_rf1_re <= rf1_aspr_re(1) and rf1_aspr_act_q; +cspr_aspr_rf1_raddr <= rf1_aspr_addr & rf1_aspr_tid_q; + +xu_lsu_slowspr_val <= ex6_val_q and ex6_sspr_val_q; +xu_lsu_slowspr_rw <= not ex6_is_mtspr_q; +xu_lsu_slowspr_etid <= ex6_tid_q; +xu_lsu_slowspr_addr <= ex6_instr_q(16 to 20) & ex6_instr_q(11 to 15); +xu_lsu_slowspr_data <= ex6_spr_wd; + +ex4_dcr_val <= exx_act(4) and ex4_dcr_val_q; +ex5_dcr_val <= ex5_val and ex5_dcr_val_q; + +ac_an_dcr_act <= ex5_dcr_val_q; +ac_an_dcr_val <= ex6_dcr_val_q; +ac_an_dcr_read <= ex6_dcr_read_q; +ac_an_dcr_user <= ex6_dcr_user_q; +ac_an_dcr_etid <= ex6_tid_q; +ac_an_dcr_addr <= ex6_instr_q(11 to 20); +ac_an_dcr_data <= ex6_spr_wd; + +spr_cpl_ex3_spr_hypv <= ex3_hypv_spr_q; +spr_cpl_ex3_spr_illeg <= ex3_illeg_spr_q; +spr_cpl_ex3_spr_priv <= ex3_priv_spr_q; + +xu_lsu_mtspr_trace_en <= gate((spr_xucr0_trace_um or not tspr_msr_pr),spr_ccr2_en_trace); + +dbell_pir_match <= (lsu_xu_dbell_pirtag_q(50 to 61) = pir_do(51 to 62)); + +with lsu_xu_dbell_pirtag_q(62 to 63) select + dbell_pir_thread <= "1000" when "00", + "0100" when "01", + "0010" when "10", + "0001" when "11", + "0000" when others; + +cspr_tspr_dbell_pirtag <= lsu_xu_dbell_pirtag_q; + +dbell : for t in 0 to threads-1 generate + +set_dbell(t) <= lsu_xu_dbell_val_q and lsu_xu_dbell_type_q = "00000" and lsu_xu_dbell_lpid_match_q and (lsu_xu_dbell_brdcast_q or (dbell_pir_match and dbell_pir_thread(t))); +set_cdbell(t) <= lsu_xu_dbell_val_q and lsu_xu_dbell_type_q = "00001" and lsu_xu_dbell_lpid_match_q and (lsu_xu_dbell_brdcast_q or (dbell_pir_match and dbell_pir_thread(t))); +set_gdbell(t) <= lsu_xu_dbell_val_q and lsu_xu_dbell_type_q = "00010" and lsu_xu_dbell_lpid_match_q and (lsu_xu_dbell_brdcast_q or tspr_cspr_gpir_match(t)); +set_gcdbell(t) <= lsu_xu_dbell_val_q and lsu_xu_dbell_type_q = "00011" and lsu_xu_dbell_lpid_match_q and (lsu_xu_dbell_brdcast_q or tspr_cspr_gpir_match(t)); +set_gmcdbell(t) <= lsu_xu_dbell_val_q and lsu_xu_dbell_type_q = "00100" and lsu_xu_dbell_lpid_match_q and (lsu_xu_dbell_brdcast_q or tspr_cspr_gpir_match(t)); + +clr_dbell(t) <= ex6_valid_q(t) and ex6_is_msgclr_q and (ex6_spr_wd(32 to 36) = "00000"); +clr_cdbell(t) <= ex6_valid_q(t) and ex6_is_msgclr_q and (ex6_spr_wd(32 to 36) = "00001"); +clr_gdbell(t) <= ex6_valid_q(t) and ex6_is_msgclr_q and (ex6_spr_wd(32 to 36) = "00010"); +clr_gcdbell(t) <= ex6_valid_q(t) and ex6_is_msgclr_q and (ex6_spr_wd(32 to 36) = "00011"); +clr_gmcdbell(t) <= ex6_valid_q(t) and ex6_is_msgclr_q and (ex6_spr_wd(32 to 36) = "00100"); + +end generate; + +dbell_present_d <= set_dbell or (dbell_present_q and not (clr_dbell or ex6_dbell_taken_q )); +cdbell_present_d <= set_cdbell or (cdbell_present_q and not (clr_cdbell or ex6_cdbell_taken_q )); +gdbell_present_d <= set_gdbell or (gdbell_present_q and not (clr_gdbell or ex6_gdbell_taken_q )); +gcdbell_present_d <= set_gcdbell or (gcdbell_present_q and not (clr_gcdbell or ex6_gcdbell_taken_q )); +gmcdbell_present_d <= set_gmcdbell or (gmcdbell_present_q and not (clr_gmcdbell or ex6_gmcdbell_taken_q)); + +dbell_interrupt <= dbell_present_q and base_mask and (tspr_msr_ee or tspr_msr_gs); +cdbell_interrupt <= cdbell_present_q and crit_mask and (tspr_msr_ce or tspr_msr_gs); +gdbell_interrupt <= gdbell_present_q and base_mask and tspr_msr_ee and tspr_msr_gs; +gcdbell_interrupt <= gcdbell_present_q and crit_mask and tspr_msr_ce and tspr_msr_gs; +gmcdbell_interrupt <= gmcdbell_present_q and crit_mask and tspr_msr_me and tspr_msr_gs; + +spr_cpl_dbell_interrupt <= dbell_interrupt_q; +spr_cpl_cdbell_interrupt <= cdbell_interrupt_q; +spr_cpl_gdbell_interrupt <= gdbell_interrupt_q; +spr_cpl_gcdbell_interrupt <= gcdbell_interrupt_q; +spr_cpl_gmcdbell_interrupt <= gmcdbell_interrupt_q; + +cspr_debug0 <= ex6_valid_q & + ex1_instr_q & + ex3_hypv_spr_q & + ex3_illeg_spr_q & + ex3_priv_spr_q & + timer_update_q ; + +cspr_debug1 <= lsu_xu_dbell_val_q & + lsu_xu_dbell_type_q & + lsu_xu_dbell_lpid_match_q & + lsu_xu_dbell_brdcast_q & + lsu_xu_dbell_pirtag_q & + spr_ccr0_we_rev & + quiesced_q & + iu_quiesce_q & + lsu_quiesce_q & + mm_quiesce_q & + bx_quiesce_q & + cpl_quiesce_q & + running & + iu_run_thread_q & + pm_wake_up & + an_ac_reservation_vld_q & + an_ac_sleep_en_q & + waitimpl_val_q & + waitrsv_val_q & + llpri_q & + tspr_cspr_lldet & "00"; + +spr_cpl_ex3_sprg_ce <= ex3_sprg_ce; +spr_cpl_ex3_sprg_ue <= ex3_sprg_ue; + +ex2_aspr_rdata_d(64-regsize) <= aspr_cspr_ex1_rdata(64-regsize); +ex2_aspr_rdata_d(65-regsize to 72-(64/regsize)) <= aspr_cspr_ex1_rdata(65-regsize to 72-(64/regsize)); + +ex2_eccchk_syn_b <= not ex2_eccchk_syn; + +xuq_spr_rd_eccgen : entity work.xuq_eccgen(xuq_eccgen) +generic map(regsize => regsize) +port map(din => ex2_aspr_rdata_q, + Syn => ex2_eccchk_syn); + +xuq_spr_eccchk : entity work.xuq_eccchk(xuq_eccchk) +generic map(regsize => regsize) +port map(din => ex2_aspr_rdata_q(64-regsize to 63), + EnCorr => encorr, + NSyn => ex2_eccchk_syn_b, + Corrd => ex2_corr_rdata, + SBE => ex2_sprg_ce, + UE => ex2_sprg_ue); + +encorr <= '1'; + +ex5_sprg_ce <= gate(ex5_valid,ex5_sprg_ce_q); + +xu_spr_cspr_ce_err_rpt : entity tri.tri_direct_err_rpt(tri_direct_err_rpt) +generic map(width => threads, expand_type => expand_type) +port map ( vd => vdd, gd => gnd, + err_in => ex6_sprg_ce_q, + err_out => xu_pc_err_sprg_ecc); + +ex3_aspr_rt(32 to 63) <= gate(ex3_corr_rdata_q(32 to 63), ex3_aspr_re_q(1)); +aspr_rt : if regsize > 32 generate +ex3_aspr_rt(64-regsize to 31) <= gate(ex3_corr_rdata_q(64-regsize to 31),ex3_aspr_re_q(0)); +end generate; + +ex3_tspr_rt <= or_reduce_t(tspr_cspr_ex3_tspr_rt,threads); + +spr_byp_ex3_spr_rt <= (ex3_cspr_rt_q and not (64-regsize to 63=>ex3_sspr_val_q)) or ex3_tspr_rt or ex3_aspr_rt; + +ex2_ccr0_rdec <= (ex2_instr(11 to 20) = "1000011111"); +ex2_ccr1_rdec <= (ex2_instr(11 to 20) = "1000111111"); +ex2_ccr2_rdec <= (ex2_instr(11 to 20) = "1001011111"); +ex2_dac1_rdec <= (ex2_instr(11 to 20) = "1110001001"); +ex2_dac2_rdec <= (ex2_instr(11 to 20) = "1110101001"); +ex2_dac3_rdec <= (ex2_instr(11 to 20) = "1000111010"); +ex2_dac4_rdec <= (ex2_instr(11 to 20) = "1001011010"); +ex2_givpr_rdec <= (ex2_instr(11 to 20) = "1111101101"); +ex2_iac1_rdec <= (ex2_instr(11 to 20) = "1100001001"); +ex2_iac2_rdec <= (ex2_instr(11 to 20) = "1100101001"); +ex2_iac3_rdec <= (ex2_instr(11 to 20) = "1101001001"); +ex2_iac4_rdec <= (ex2_instr(11 to 20) = "1101101001"); +ex2_ivpr_rdec <= (ex2_instr(11 to 20) = "1111100001"); +ex2_pir_rdec <= (ex2_instr(11 to 20) = "1111001000"); +ex2_pvr_rdec <= (ex2_instr(11 to 20) = "1111101000"); +ex2_tb_rdec <= (ex2_instr(11 to 20) = "0110001000"); +ex2_tbu_rdec <= ((ex2_instr(11 to 20) = "0110101000")); +ex2_tenc_rdec <= (ex2_instr(11 to 20) = "1011101101"); +ex2_tens_rdec <= (ex2_instr(11 to 20) = "1011001101"); +ex2_tensr_rdec <= (ex2_instr(11 to 20) = "1010101101"); +ex2_tir_rdec <= (ex2_instr(11 to 20) = "1111001101"); +ex2_xucr0_rdec <= (ex2_instr(11 to 20) = "1011011111"); +ex2_xucr3_rdec <= (ex2_instr(11 to 20) = "1010011010"); +ex2_xucr4_rdec <= (ex2_instr(11 to 20) = "1010111010"); +ex2_ccr0_re <= ex2_ccr0_rdec; +ex2_ccr1_re <= ex2_ccr1_rdec; +ex2_ccr2_re <= ex2_ccr2_rdec; +ex2_dac1_re <= ex2_dac1_rdec; +ex2_dac2_re <= ex2_dac2_rdec; +ex2_dac3_re <= ex2_dac3_rdec; +ex2_dac4_re <= ex2_dac4_rdec; +ex2_givpr_re <= ex2_givpr_rdec; +ex2_iac1_re <= ex2_iac1_rdec; +ex2_iac2_re <= ex2_iac2_rdec; +ex2_iac3_re <= ex2_iac3_rdec; +ex2_iac4_re <= ex2_iac4_rdec; +ex2_ivpr_re <= ex2_ivpr_rdec; +ex2_pir_re <= ex2_pir_rdec and not ex2_msr_gs_q(0); +ex2_pvr_re <= ex2_pvr_rdec; +ex2_tb_re <= ex2_tb_rdec; +ex2_tbu_re <= ex2_tbu_rdec; +ex2_tenc_re <= ex2_tenc_rdec; +ex2_tens_re <= ex2_tens_rdec; +ex2_tensr_re <= ex2_tensr_rdec; +ex2_tir_re <= ex2_tir_rdec; +ex2_xucr0_re <= ex2_xucr0_rdec; +ex2_xucr3_re <= ex2_xucr3_rdec; +ex2_xucr4_re <= ex2_xucr4_rdec; + +readmux_00 : if a2mode = 0 and hvmode = 0 generate +ex2_cspr_rt <= + (ccr0_do(DO'range) and (DO'range => ex2_ccr0_re )) or + (ccr1_do(DO'range) and (DO'range => ex2_ccr1_re )) or + (ccr2_do(DO'range) and (DO'range => ex2_ccr2_re )) or + (pir_do(DO'range) and (DO'range => ex2_pir_re )) or + (pvr_do(DO'range) and (DO'range => ex2_pvr_re )) or + (tb_do(DO'range) and (DO'range => ex2_tb_re )) or + (tbu_do(DO'range) and (DO'range => ex2_tbu_re )) or + (tenc_do(DO'range) and (DO'range => ex2_tenc_re )) or + (tens_do(DO'range) and (DO'range => ex2_tens_re )) or + (tensr_do(DO'range) and (DO'range => ex2_tensr_re )) or + (tir_do(DO'range) and (DO'range => ex2_tir_re )) or + (xucr0_do(DO'range) and (DO'range => ex2_xucr0_re )); +end generate; +readmux_01 : if a2mode = 0 and hvmode = 1 generate +ex2_cspr_rt <= + (ccr0_do(DO'range) and (DO'range => ex2_ccr0_re )) or + (ccr1_do(DO'range) and (DO'range => ex2_ccr1_re )) or + (ccr2_do(DO'range) and (DO'range => ex2_ccr2_re )) or + (pir_do(DO'range) and (DO'range => ex2_pir_re )) or + (pvr_do(DO'range) and (DO'range => ex2_pvr_re )) or + (tb_do(DO'range) and (DO'range => ex2_tb_re )) or + (tbu_do(DO'range) and (DO'range => ex2_tbu_re )) or + (tenc_do(DO'range) and (DO'range => ex2_tenc_re )) or + (tens_do(DO'range) and (DO'range => ex2_tens_re )) or + (tensr_do(DO'range) and (DO'range => ex2_tensr_re )) or + (tir_do(DO'range) and (DO'range => ex2_tir_re )) or + (xucr0_do(DO'range) and (DO'range => ex2_xucr0_re )); +end generate; +readmux_10 : if a2mode = 1 and hvmode = 0 generate +ex2_cspr_rt <= + (ccr0_do(DO'range) and (DO'range => ex2_ccr0_re )) or + (ccr1_do(DO'range) and (DO'range => ex2_ccr1_re )) or + (ccr2_do(DO'range) and (DO'range => ex2_ccr2_re )) or + (pir_do(DO'range) and (DO'range => ex2_pir_re )) or + (pvr_do(DO'range) and (DO'range => ex2_pvr_re )) or + (tb_do(DO'range) and (DO'range => ex2_tb_re )) or + (tbu_do(DO'range) and (DO'range => ex2_tbu_re )) or + (tenc_do(DO'range) and (DO'range => ex2_tenc_re )) or + (tens_do(DO'range) and (DO'range => ex2_tens_re )) or + (tensr_do(DO'range) and (DO'range => ex2_tensr_re )) or + (tir_do(DO'range) and (DO'range => ex2_tir_re )) or + (xucr0_do(DO'range) and (DO'range => ex2_xucr0_re )); +end generate; +readmux_11 : if a2mode = 1 and hvmode = 1 generate +ex2_cspr_rt <= + (ccr0_do(DO'range) and (DO'range => ex2_ccr0_re )) or + (ccr1_do(DO'range) and (DO'range => ex2_ccr1_re )) or + (ccr2_do(DO'range) and (DO'range => ex2_ccr2_re )) or + (pir_do(DO'range) and (DO'range => ex2_pir_re )) or + (pvr_do(DO'range) and (DO'range => ex2_pvr_re )) or + (tb_do(DO'range) and (DO'range => ex2_tb_re )) or + (tbu_do(DO'range) and (DO'range => ex2_tbu_re )) or + (tenc_do(DO'range) and (DO'range => ex2_tenc_re )) or + (tens_do(DO'range) and (DO'range => ex2_tens_re )) or + (tensr_do(DO'range) and (DO'range => ex2_tensr_re )) or + (tir_do(DO'range) and (DO'range => ex2_tir_re )) or + (xucr0_do(DO'range) and (DO'range => ex2_xucr0_re )); +end generate; + +ex6_ccr0_wdec <= (ex6_instr(11 to 20) = "1000011111"); +ex6_ccr1_wdec <= (ex6_instr(11 to 20) = "1000111111"); +ex6_ccr2_wdec <= (ex6_instr(11 to 20) = "1001011111"); +ex6_tbl_wdec <= (ex6_instr(11 to 20) = "1110001000"); +ex6_tbu_wdec <= ((ex6_instr(11 to 20) = "1110101000")); +ex6_tenc_wdec <= (ex6_instr(11 to 20) = "1011101101"); +ex6_tens_wdec <= (ex6_instr(11 to 20) = "1011001101"); +ex6_xucr0_wdec <= (ex6_instr(11 to 20) = "1011011111"); +ex6_ccr0_we <= ex6_val and ex6_is_mtspr and ex6_ccr0_wdec; +ex6_ccr1_we <= ex6_val and ex6_is_mtspr and ex6_ccr1_wdec; +ex6_ccr2_we <= ex6_val and ex6_is_mtspr and ex6_ccr2_wdec; +ex6_tbl_we <= ex6_val and ex6_is_mtspr and ex6_tbl_wdec; +ex6_tbu_we <= ex6_val and ex6_is_mtspr and ex6_tbu_wdec; +ex6_tenc_we <= ex6_val and ex6_is_mtspr and ex6_tenc_wdec; +ex6_tens_we <= ex6_val and ex6_is_mtspr and ex6_tens_wdec; +ex6_xucr0_we <= ex6_val and ex6_is_mtspr and ex6_xucr0_wdec; + +rf1_gsprg0_rdec <= (rf1_instr(11 to 20) = "1000001011"); +rf1_gsprg1_rdec <= (rf1_instr(11 to 20) = "1000101011"); +rf1_gsprg2_rdec <= (rf1_instr(11 to 20) = "1001001011"); +rf1_gsprg3_rdec <= (rf1_instr(11 to 20) = "1001101011"); +rf1_sprg0_rdec <= (rf1_instr(11 to 20) = "1000001000"); +rf1_sprg1_rdec <= (rf1_instr(11 to 20) = "1000101000"); +rf1_sprg2_rdec <= (rf1_instr(11 to 20) = "1001001000"); +rf1_sprg3_rdec <= ((rf1_instr(11 to 20) = "1001101000") or + (rf1_instr(11 to 20) = "0001101000")); +rf1_sprg4_rdec <= ((rf1_instr(11 to 20) = "1010001000") or + (rf1_instr(11 to 20) = "0010001000")); +rf1_sprg5_rdec <= ((rf1_instr(11 to 20) = "1010101000") or + (rf1_instr(11 to 20) = "0010101000")); +rf1_sprg6_rdec <= ((rf1_instr(11 to 20) = "1011001000") or + (rf1_instr(11 to 20) = "0011001000")); +rf1_sprg7_rdec <= ((rf1_instr(11 to 20) = "1011101000") or + (rf1_instr(11 to 20) = "0011101000")); +rf1_sprg8_rdec <= (rf1_instr(11 to 20) = "1110010010"); +rf1_vrsave_rdec <= (rf1_instr(11 to 20) = "0000001000"); +rf1_gsprg0_re <= (rf1_gsprg0_rdec or (rf1_sprg0_rdec and rf1_msr_gs_q)); +rf1_gsprg1_re <= (rf1_gsprg1_rdec or (rf1_sprg1_rdec and rf1_msr_gs_q)); +rf1_gsprg2_re <= (rf1_gsprg2_rdec or (rf1_sprg2_rdec and rf1_msr_gs_q)); +rf1_gsprg3_re <= (rf1_gsprg3_rdec or (rf1_sprg3_rdec and rf1_msr_gs_q)); +rf1_sprg0_re <= rf1_sprg0_rdec and not rf1_msr_gs_q; +rf1_sprg1_re <= rf1_sprg1_rdec and not rf1_msr_gs_q; +rf1_sprg2_re <= rf1_sprg2_rdec and not rf1_msr_gs_q; +rf1_sprg3_re <= rf1_sprg3_rdec and not rf1_msr_gs_q; +rf1_sprg4_re <= rf1_sprg4_rdec; +rf1_sprg5_re <= rf1_sprg5_rdec; +rf1_sprg6_re <= rf1_sprg6_rdec; +rf1_sprg7_re <= rf1_sprg7_rdec; +rf1_sprg8_re <= rf1_sprg8_rdec; +rf1_vrsave_re <= rf1_vrsave_rdec; + +rf1_aspr_re(1) <= rf1_is_mfspr and ( + rf1_gsprg0_re or rf1_gsprg1_re or rf1_gsprg2_re + or rf1_gsprg3_re or rf1_sprg0_re or rf1_sprg1_re + or rf1_sprg2_re or rf1_sprg3_re or rf1_sprg4_re + or rf1_sprg5_re or rf1_sprg6_re or rf1_sprg7_re + or rf1_sprg8_re or rf1_vrsave_re ); + +rf1_aspr_re0_gen : if regsize > 32 generate +rf1_aspr_re(0) <= rf1_aspr_re(1) and not ( + rf1_vrsave_re ); +end generate; + +rf1_aspr_addr <= + ("0000" and (0 to 3=> rf1_gsprg0_re )) or + ("0001" and (0 to 3=> rf1_gsprg1_re )) or + ("0010" and (0 to 3=> rf1_gsprg2_re )) or + ("0011" and (0 to 3=> rf1_gsprg3_re )) or + ("0100" and (0 to 3=> rf1_sprg0_re )) or + ("0101" and (0 to 3=> rf1_sprg1_re )) or + ("0110" and (0 to 3=> rf1_sprg2_re )) or + ("0111" and (0 to 3=> rf1_sprg3_re )) or + ("1000" and (0 to 3=> rf1_sprg4_re )) or + ("1001" and (0 to 3=> rf1_sprg5_re )) or + ("1010" and (0 to 3=> rf1_sprg6_re )) or + ("1011" and (0 to 3=> rf1_sprg7_re )) or + ("1100" and (0 to 3=> rf1_sprg8_re )) or + ("1101" and (0 to 3=> rf1_vrsave_re )); + + +ex3_sprg_ue <= ex3_sprg_ue_q and ex3_aspr_re_q(0); +ex3_sprg_ce <= ex3_sprg_ce_q and ex3_aspr_re_q(0); +ex4_sprg_ce_d <= (others=>ex3_sprg_ce); + +ex4_inj_ecc <= or_reduce(inj_sprg_ecc_q and ex4_tid) and ex4_aspr_we_q and not ex4_sprg_ce_q(0); + +ex4_rt <= (ex4_corr_rdata_q and fanout(ex4_sprg_ce_q(0 to regsize/8-1),regsize)) or + (ex4_rt_q and not fanout(ex4_sprg_ce_q(0 to regsize/8-1),regsize)); + +ex4_rt_inj(63) <= ex4_rt(63) xor ex4_inj_ecc; +ex4_rt_inj(64-regsize to 62) <= ex4_rt(64-regsize to 62); + +ex4_eccgen_data <= ex4_rt & tidn(0 to 8-(64/regsize)); + +xuq_spr_wr_eccgen : entity work.xuq_eccgen(xuq_eccgen) +generic map(regsize => regsize) +port map(din => ex4_eccgen_data, + Syn => ex4_eccgen_syn); + +ex4_is_mfsspr_b <= not (ex4_sspr_val_q and ex4_is_mfspr_q); + +ex5_rt_d <= gate(ex4_rt_inj,ex4_is_mfsspr_b) & ex4_eccgen_syn; + +ex5_aspr_we_d <= dec_spr_ex4_val and not xu_ex4_flush and (0 to threads-1=>(ex4_aspr_we_q or ex4_sprg_ce_q(0))); + +ex3_aspr_we <= ex3_is_mtspr_q and ( + ex3_gsprg0_we or ex3_gsprg1_we or ex3_gsprg2_we + or ex3_gsprg3_we or ex3_sprg0_we or ex3_sprg1_we + or ex3_sprg2_we or ex3_sprg3_we or ex3_sprg4_we + or ex3_sprg5_we or ex3_sprg6_we or ex3_sprg7_we + or ex3_sprg8_we or ex3_vrsave_we ); + +ex3_gsprg0_wdec <= (ex3_instr(11 to 20) = "1000001011"); +ex3_gsprg1_wdec <= (ex3_instr(11 to 20) = "1000101011"); +ex3_gsprg2_wdec <= (ex3_instr(11 to 20) = "1001001011"); +ex3_gsprg3_wdec <= (ex3_instr(11 to 20) = "1001101011"); +ex3_sprg0_wdec <= (ex3_instr(11 to 20) = "1000001000"); +ex3_sprg1_wdec <= (ex3_instr(11 to 20) = "1000101000"); +ex3_sprg2_wdec <= (ex3_instr(11 to 20) = "1001001000"); +ex3_sprg3_wdec <= ((ex3_instr(11 to 20) = "1001101000")); +ex3_sprg4_wdec <= ((ex3_instr(11 to 20) = "1010001000")); +ex3_sprg5_wdec <= ((ex3_instr(11 to 20) = "1010101000")); +ex3_sprg6_wdec <= ((ex3_instr(11 to 20) = "1011001000")); +ex3_sprg7_wdec <= ((ex3_instr(11 to 20) = "1011101000")); +ex3_sprg8_wdec <= (ex3_instr(11 to 20) = "1110010010"); +ex3_vrsave_wdec <= (ex3_instr(11 to 20) = "0000001000"); +ex3_gsprg0_we <= (ex3_gsprg0_wdec or (ex3_sprg0_wdec and ex3_msr_gs_q)); +ex3_gsprg1_we <= (ex3_gsprg1_wdec or (ex3_sprg1_wdec and ex3_msr_gs_q)); +ex3_gsprg2_we <= (ex3_gsprg2_wdec or (ex3_sprg2_wdec and ex3_msr_gs_q)); +ex3_gsprg3_we <= (ex3_gsprg3_wdec or (ex3_sprg3_wdec and ex3_msr_gs_q)); +ex3_sprg0_we <= ex3_sprg0_wdec and not ex3_msr_gs_q; +ex3_sprg1_we <= ex3_sprg1_wdec and not ex3_msr_gs_q; +ex3_sprg2_we <= ex3_sprg2_wdec and not ex3_msr_gs_q; +ex3_sprg3_we <= ex3_sprg3_wdec and not ex3_msr_gs_q; +ex3_sprg4_we <= ex3_sprg4_wdec; +ex3_sprg5_we <= ex3_sprg5_wdec; +ex3_sprg6_we <= ex3_sprg6_wdec; +ex3_sprg7_we <= ex3_sprg7_wdec; +ex3_sprg8_we <= ex3_sprg8_wdec; +ex3_vrsave_we <= ex3_vrsave_wdec; +ex3_aspr_addr <= + ("0000" and (0 to 3=> ex3_gsprg0_we )) or + ("0001" and (0 to 3=> ex3_gsprg1_we )) or + ("0010" and (0 to 3=> ex3_gsprg2_we )) or + ("0011" and (0 to 3=> ex3_gsprg3_we )) or + ("0100" and (0 to 3=> ex3_sprg0_we )) or + ("0101" and (0 to 3=> ex3_sprg1_we )) or + ("0110" and (0 to 3=> ex3_sprg2_we )) or + ("0111" and (0 to 3=> ex3_sprg3_we )) or + ("1000" and (0 to 3=> ex3_sprg4_we )) or + ("1001" and (0 to 3=> ex3_sprg5_we )) or + ("1010" and (0 to 3=> ex3_sprg6_we )) or + ("1011" and (0 to 3=> ex3_sprg7_we )) or + ("1100" and (0 to 3=> ex3_sprg8_we )) or + ("1101" and (0 to 3=> ex3_vrsave_we )); + +with ex4_sprg_ce_q(regsize/8) select + ex5_aspr_addr_d <= ex4_aspr_ce_addr_q when '1', + ex4_aspr_addr_q when others; + +ex2_dvc1_rdec <= (ex2_instr(11 to 20) = "1111001001"); +ex2_dvc2_rdec <= (ex2_instr(11 to 20) = "1111101001"); +ex2_eplc_rdec <= (ex2_instr(11 to 20) = "1001111101"); +ex2_epsc_rdec <= (ex2_instr(11 to 20) = "1010011101"); +ex2_eptcfg_rdec <= (ex2_instr(11 to 20) = "1111001010"); +ex2_immr_rdec <= (ex2_instr(11 to 20) = "1000111011"); +ex2_imr_rdec <= (ex2_instr(11 to 20) = "1000011011"); +ex2_iucr0_rdec <= (ex2_instr(11 to 20) = "1001111111"); +ex2_iucr1_rdec <= (ex2_instr(11 to 20) = "1001111011"); +ex2_iucr2_rdec <= (ex2_instr(11 to 20) = "1010011011"); +ex2_iudbg0_rdec <= (ex2_instr(11 to 20) = "1100011011"); +ex2_iudbg1_rdec <= (ex2_instr(11 to 20) = "1100111011"); +ex2_iudbg2_rdec <= (ex2_instr(11 to 20) = "1101011011"); +ex2_iulfsr_rdec <= (ex2_instr(11 to 20) = "1101111011"); +ex2_iullcr_rdec <= (ex2_instr(11 to 20) = "1110011011"); +ex2_lper_rdec <= (ex2_instr(11 to 20) = "1100000001"); +ex2_lperu_rdec <= (ex2_instr(11 to 20) = "1100100001"); +ex2_lpidr_rdec <= (ex2_instr(11 to 20) = "1001001010"); +ex2_lratcfg_rdec <= (ex2_instr(11 to 20) = "1011001010"); +ex2_lratps_rdec <= (ex2_instr(11 to 20) = "1011101010"); +ex2_mas0_rdec <= (ex2_instr(11 to 20) = "1000010011"); +ex2_mas0_mas1_rdec<= (ex2_instr(11 to 20) = "1010101011"); +ex2_mas1_rdec <= (ex2_instr(11 to 20) = "1000110011"); +ex2_mas2_rdec <= (ex2_instr(11 to 20) = "1001010011"); +ex2_mas2u_rdec <= (ex2_instr(11 to 20) = "1011110011"); +ex2_mas3_rdec <= (ex2_instr(11 to 20) = "1001110011"); +ex2_mas4_rdec <= (ex2_instr(11 to 20) = "1010010011"); +ex2_mas5_rdec <= (ex2_instr(11 to 20) = "1001101010"); +ex2_mas5_mas6_rdec<= (ex2_instr(11 to 20) = "1110001010"); +ex2_mas6_rdec <= (ex2_instr(11 to 20) = "1011010011"); +ex2_mas7_rdec <= (ex2_instr(11 to 20) = "1000011101"); +ex2_mas7_mas3_rdec<= (ex2_instr(11 to 20) = "1010001011"); +ex2_mas8_rdec <= (ex2_instr(11 to 20) = "1010101010"); +ex2_mas8_mas1_rdec<= (ex2_instr(11 to 20) = "1110101010"); +ex2_mmucfg_rdec <= (ex2_instr(11 to 20) = "1011111111"); +ex2_mmucr0_rdec <= (ex2_instr(11 to 20) = "1110011111"); +ex2_mmucr1_rdec <= (ex2_instr(11 to 20) = "1110111111"); +ex2_mmucr2_rdec <= (ex2_instr(11 to 20) = "1111011111"); +ex2_mmucr3_rdec <= (ex2_instr(11 to 20) = "1111111111"); +ex2_mmucsr0_rdec <= (ex2_instr(11 to 20) = "1010011111"); +ex2_pid_rdec <= (ex2_instr(11 to 20) = "1000000001"); +ex2_ppr32_rdec <= (ex2_instr(11 to 20) = "0001011100"); +ex2_tlb0cfg_rdec <= (ex2_instr(11 to 20) = "1000010101"); +ex2_tlb0ps_rdec <= (ex2_instr(11 to 20) = "1100001010"); +ex2_xucr2_rdec <= (ex2_instr(11 to 20) = "1100011111"); +ex2_xudbg0_rdec <= (ex2_instr(11 to 20) = "1010111011"); +ex2_xudbg1_rdec <= (ex2_instr(11 to 20) = "1011011011"); +ex2_xudbg2_rdec <= (ex2_instr(11 to 20) = "1011111011"); +ex2_dvc1_re <= ex2_dvc1_rdec; +ex2_dvc2_re <= ex2_dvc2_rdec; +ex2_eplc_re <= ex2_eplc_rdec; +ex2_epsc_re <= ex2_epsc_rdec; +ex2_eptcfg_re <= ex2_eptcfg_rdec; +ex2_immr_re <= ex2_immr_rdec; +ex2_imr_re <= ex2_imr_rdec; +ex2_iucr0_re <= ex2_iucr0_rdec; +ex2_iucr1_re <= ex2_iucr1_rdec; +ex2_iucr2_re <= ex2_iucr2_rdec; +ex2_iudbg0_re <= ex2_iudbg0_rdec; +ex2_iudbg1_re <= ex2_iudbg1_rdec; +ex2_iudbg2_re <= ex2_iudbg2_rdec; +ex2_iulfsr_re <= ex2_iulfsr_rdec; +ex2_iullcr_re <= ex2_iullcr_rdec; +ex2_lper_re <= ex2_lper_rdec; +ex2_lperu_re <= ex2_lperu_rdec; +ex2_lpidr_re <= ex2_lpidr_rdec; +ex2_lratcfg_re <= ex2_lratcfg_rdec; +ex2_lratps_re <= ex2_lratps_rdec; +ex2_mas0_re <= ex2_mas0_rdec; +ex2_mas0_mas1_re <= ex2_mas0_mas1_rdec; +ex2_mas1_re <= ex2_mas1_rdec; +ex2_mas2_re <= ex2_mas2_rdec; +ex2_mas2u_re <= ex2_mas2u_rdec; +ex2_mas3_re <= ex2_mas3_rdec; +ex2_mas4_re <= ex2_mas4_rdec; +ex2_mas5_re <= ex2_mas5_rdec; +ex2_mas5_mas6_re <= ex2_mas5_mas6_rdec; +ex2_mas6_re <= ex2_mas6_rdec; +ex2_mas7_re <= ex2_mas7_rdec; +ex2_mas7_mas3_re <= ex2_mas7_mas3_rdec; +ex2_mas8_re <= ex2_mas8_rdec; +ex2_mas8_mas1_re <= ex2_mas8_mas1_rdec; +ex2_mmucfg_re <= ex2_mmucfg_rdec; +ex2_mmucr0_re <= ex2_mmucr0_rdec; +ex2_mmucr1_re <= ex2_mmucr1_rdec; +ex2_mmucr2_re <= ex2_mmucr2_rdec; +ex2_mmucr3_re <= ex2_mmucr3_rdec; +ex2_mmucsr0_re <= ex2_mmucsr0_rdec; +ex2_pid_re <= ex2_pid_rdec; +ex2_ppr32_re <= ex2_ppr32_rdec; +ex2_tlb0cfg_re <= ex2_tlb0cfg_rdec; +ex2_tlb0ps_re <= ex2_tlb0ps_rdec; +ex2_xucr2_re <= ex2_xucr2_rdec; +ex2_xudbg0_re <= ex2_xudbg0_rdec; +ex2_xudbg1_re <= ex2_xudbg1_rdec; +ex2_xudbg2_re <= ex2_xudbg2_rdec; +ex2_dvc1_wdec <= ex2_dvc1_rdec; +ex2_dvc2_wdec <= ex2_dvc2_rdec; +ex2_eplc_wdec <= ex2_eplc_rdec; +ex2_epsc_wdec <= ex2_epsc_rdec; +ex2_immr_wdec <= ex2_immr_rdec; +ex2_imr_wdec <= ex2_imr_rdec; +ex2_iucr0_wdec <= ex2_iucr0_rdec; +ex2_iucr1_wdec <= ex2_iucr1_rdec; +ex2_iucr2_wdec <= ex2_iucr2_rdec; +ex2_iudbg0_wdec <= ex2_iudbg0_rdec; +ex2_iulfsr_wdec <= ex2_iulfsr_rdec; +ex2_iullcr_wdec <= ex2_iullcr_rdec; +ex2_lper_wdec <= ex2_lper_rdec; +ex2_lperu_wdec <= ex2_lperu_rdec; +ex2_lpidr_wdec <= ex2_lpidr_rdec; +ex2_mas0_wdec <= ex2_mas0_rdec; +ex2_mas0_mas1_wdec<= ex2_mas0_mas1_rdec; +ex2_mas1_wdec <= ex2_mas1_rdec; +ex2_mas2_wdec <= ex2_mas2_rdec; +ex2_mas2u_wdec <= ex2_mas2u_rdec; +ex2_mas3_wdec <= ex2_mas3_rdec; +ex2_mas4_wdec <= ex2_mas4_rdec; +ex2_mas5_wdec <= ex2_mas5_rdec; +ex2_mas5_mas6_wdec<= ex2_mas5_mas6_rdec; +ex2_mas6_wdec <= ex2_mas6_rdec; +ex2_mas7_wdec <= ex2_mas7_rdec; +ex2_mas7_mas3_wdec<= ex2_mas7_mas3_rdec; +ex2_mas8_wdec <= ex2_mas8_rdec; +ex2_mas8_mas1_wdec<= ex2_mas8_mas1_rdec; +ex2_mmucr0_wdec <= ex2_mmucr0_rdec; +ex2_mmucr1_wdec <= ex2_mmucr1_rdec; +ex2_mmucr2_wdec <= ex2_mmucr2_rdec; +ex2_mmucr3_wdec <= ex2_mmucr3_rdec; +ex2_mmucsr0_wdec <= ex2_mmucsr0_rdec; +ex2_pid_wdec <= ex2_pid_rdec; +ex2_ppr32_wdec <= ex2_ppr32_rdec; +ex2_xucr2_wdec <= ex2_xucr2_rdec; +ex2_xudbg0_wdec <= ex2_xudbg0_rdec; +ex2_dvc1_we <= ex2_dvc1_wdec; +ex2_dvc2_we <= ex2_dvc2_wdec; +ex2_eplc_we <= ex2_eplc_wdec; +ex2_epsc_we <= ex2_epsc_wdec; +ex2_immr_we <= ex2_immr_wdec; +ex2_imr_we <= ex2_imr_wdec; +ex2_iucr0_we <= ex2_iucr0_wdec; +ex2_iucr1_we <= ex2_iucr1_wdec; +ex2_iucr2_we <= ex2_iucr2_wdec; +ex2_iudbg0_we <= ex2_iudbg0_wdec; +ex2_iulfsr_we <= ex2_iulfsr_wdec; +ex2_iullcr_we <= ex2_iullcr_wdec; +ex2_lper_we <= ex2_lper_wdec; +ex2_lperu_we <= ex2_lperu_wdec; +ex2_lpidr_we <= ex2_lpidr_wdec; +ex2_mas0_we <= ex2_mas0_wdec; +ex2_mas0_mas1_we <= ex2_mas0_mas1_wdec; +ex2_mas1_we <= ex2_mas1_wdec; +ex2_mas2_we <= ex2_mas2_wdec; +ex2_mas2u_we <= ex2_mas2u_wdec; +ex2_mas3_we <= ex2_mas3_wdec; +ex2_mas4_we <= ex2_mas4_wdec; +ex2_mas5_we <= ex2_mas5_wdec; +ex2_mas5_mas6_we <= ex2_mas5_mas6_wdec; +ex2_mas6_we <= ex2_mas6_wdec; +ex2_mas7_we <= ex2_mas7_wdec; +ex2_mas7_mas3_we <= ex2_mas7_mas3_wdec; +ex2_mas8_we <= ex2_mas8_wdec; +ex2_mas8_mas1_we <= ex2_mas8_mas1_wdec; +ex2_mmucr0_we <= ex2_mmucr0_wdec; +ex2_mmucr1_we <= ex2_mmucr1_wdec; +ex2_mmucr2_we <= ex2_mmucr2_wdec; +ex2_mmucr3_we <= ex2_mmucr3_wdec; +ex2_mmucsr0_we <= ex2_mmucsr0_wdec; +ex2_pid_we <= ex2_pid_wdec; +ex2_ppr32_we <= ex2_ppr32_wdec; +ex2_xucr2_we <= ex2_xucr2_wdec; +ex2_xudbg0_we <= ex2_xudbg0_wdec; +ex2_slowspr_range_hypv <= ex2_instr(11) and ex2_instr(16 to 20) = "11110"; +ex2_slowspr_range_priv <= ex2_instr(11) and ex2_instr(16 to 20) = "11100"; +ex2_slowspr_range <= ex2_slowspr_range_priv or ex2_slowspr_range_hypv; + +ex2_illeg_mftb <= ex2_is_mftb_q and not (ex2_instr(11 to 14) = "0110" and + ex2_instr(16 to 20) = "01000"); + +ex2_sspr_val <=(ex2_is_mtspr_q and (ex2_slowspr_range or + ex2_dvc1_we or ex2_dvc2_we or ex2_eplc_we + or ex2_epsc_we or ex2_immr_we or ex2_imr_we + or ex2_iucr0_we or ex2_iucr1_we or ex2_iucr2_we + or ex2_iudbg0_we or ex2_iulfsr_we or ex2_iullcr_we + or ex2_lper_we or ex2_lperu_we or ex2_lpidr_we + or ex2_mas0_we or ex2_mas0_mas1_we or ex2_mas1_we + or ex2_mas2_we or ex2_mas2u_we or ex2_mas3_we + or ex2_mas4_we or ex2_mas5_we or ex2_mas5_mas6_we + or ex2_mas6_we or ex2_mas7_we or ex2_mas7_mas3_we + or ex2_mas8_we or ex2_mas8_mas1_we or ex2_mmucr0_we + or ex2_mmucr1_we or ex2_mmucr2_we or ex2_mmucr3_we + or ex2_mmucsr0_we or ex2_pid_we or ex2_ppr32_we + or ex2_xucr2_we or ex2_xudbg0_we )) or + (ex2_is_mfspr_q and (ex2_slowspr_range or + ex2_dvc1_re or ex2_dvc2_re or ex2_eplc_re + or ex2_epsc_re or ex2_eptcfg_re or ex2_immr_re + or ex2_imr_re or ex2_iucr0_re or ex2_iucr1_re + or ex2_iucr2_re or ex2_iudbg0_re or ex2_iudbg1_re + or ex2_iudbg2_re or ex2_iulfsr_re or ex2_iullcr_re + or ex2_lper_re or ex2_lperu_re or ex2_lpidr_re + or ex2_lratcfg_re or ex2_lratps_re or ex2_mas0_re + or ex2_mas0_mas1_re or ex2_mas1_re or ex2_mas2_re + or ex2_mas2u_re or ex2_mas3_re or ex2_mas4_re + or ex2_mas5_re or ex2_mas5_mas6_re or ex2_mas6_re + or ex2_mas7_re or ex2_mas7_mas3_re or ex2_mas8_re + or ex2_mas8_mas1_re or ex2_mmucfg_re or ex2_mmucr0_re + or ex2_mmucr1_re or ex2_mmucr2_re or ex2_mmucr3_re + or ex2_mmucsr0_re or ex2_pid_re or ex2_ppr32_re + or ex2_tlb0cfg_re or ex2_tlb0ps_re or ex2_xucr2_re + or ex2_xudbg0_re or ex2_xudbg1_re or ex2_xudbg2_re )); + +ex2_gsprg0_rdec <= (ex2_instr(11 to 20) = "1000001011"); +ex2_gsprg1_rdec <= (ex2_instr(11 to 20) = "1000101011"); +ex2_gsprg2_rdec <= (ex2_instr(11 to 20) = "1001001011"); +ex2_gsprg3_rdec <= (ex2_instr(11 to 20) = "1001101011"); +ex2_sprg0_rdec <= (ex2_instr(11 to 20) = "1000001000"); +ex2_sprg1_rdec <= (ex2_instr(11 to 20) = "1000101000"); +ex2_sprg2_rdec <= (ex2_instr(11 to 20) = "1001001000"); +ex2_sprg3_rdec <= ((ex2_instr(11 to 20) = "1001101000") or + (ex2_instr(11 to 20) = "0001101000")); +ex2_sprg4_rdec <= ((ex2_instr(11 to 20) = "1010001000") or + (ex2_instr(11 to 20) = "0010001000")); +ex2_sprg5_rdec <= ((ex2_instr(11 to 20) = "1010101000") or + (ex2_instr(11 to 20) = "0010101000")); +ex2_sprg6_rdec <= ((ex2_instr(11 to 20) = "1011001000") or + (ex2_instr(11 to 20) = "0011001000")); +ex2_sprg7_rdec <= ((ex2_instr(11 to 20) = "1011101000") or + (ex2_instr(11 to 20) = "0011101000")); +ex2_sprg8_rdec <= (ex2_instr(11 to 20) = "1110010010"); +ex2_vrsave_rdec <= (ex2_instr(11 to 20) = "0000001000"); +ex2_gsprg0_wdec <= (ex2_instr(11 to 20) = "1000001011"); +ex2_gsprg1_wdec <= (ex2_instr(11 to 20) = "1000101011"); +ex2_gsprg2_wdec <= (ex2_instr(11 to 20) = "1001001011"); +ex2_gsprg3_wdec <= (ex2_instr(11 to 20) = "1001101011"); +ex2_sprg0_wdec <= (ex2_instr(11 to 20) = "1000001000"); +ex2_sprg1_wdec <= (ex2_instr(11 to 20) = "1000101000"); +ex2_sprg2_wdec <= (ex2_instr(11 to 20) = "1001001000"); +ex2_sprg3_wdec <= ((ex2_instr(11 to 20) = "1001101000")); +ex2_sprg4_wdec <= ((ex2_instr(11 to 20) = "1010001000")); +ex2_sprg5_wdec <= ((ex2_instr(11 to 20) = "1010101000")); +ex2_sprg6_wdec <= ((ex2_instr(11 to 20) = "1011001000")); +ex2_sprg7_wdec <= ((ex2_instr(11 to 20) = "1011101000")); +ex2_sprg8_wdec <= (ex2_instr(11 to 20) = "1110010010"); +ex2_vrsave_wdec <= (ex2_instr(11 to 20) = "0000001000"); +ex2_sprg8_re <= ex2_sprg8_rdec; +ex2_sprg8_we <= ex2_sprg8_wdec; +ex2_ccr0_wdec <= ex2_ccr0_rdec; +ex2_ccr1_wdec <= ex2_ccr1_rdec; +ex2_ccr2_wdec <= ex2_ccr2_rdec; +ex2_dac1_wdec <= ex2_dac1_rdec; +ex2_dac2_wdec <= ex2_dac2_rdec; +ex2_dac3_wdec <= ex2_dac3_rdec; +ex2_dac4_wdec <= ex2_dac4_rdec; +ex2_givpr_wdec <= (ex2_instr(11 to 20) = "1111101101"); +ex2_iac1_wdec <= ex2_iac1_rdec; +ex2_iac2_wdec <= ex2_iac2_rdec; +ex2_iac3_wdec <= ex2_iac3_rdec; +ex2_iac4_wdec <= ex2_iac4_rdec; +ex2_ivpr_wdec <= ex2_ivpr_rdec; +ex2_tbl_wdec <= (ex2_instr(11 to 20) = "1110001000"); +ex2_tbu_wdec <= ((ex2_instr(11 to 20) = "1110101000")); +ex2_tenc_wdec <= ex2_tenc_rdec; +ex2_tens_wdec <= ex2_tens_rdec; +ex2_trace_wdec <= (ex2_instr(11 to 20) = "0111011111"); +ex2_xucr0_wdec <= ex2_xucr0_rdec; +ex2_xucr3_wdec <= ex2_xucr3_rdec; +ex2_xucr4_wdec <= ex2_xucr4_rdec; +ex2_ccr0_we <= ex2_ccr0_wdec; +ex2_ccr1_we <= ex2_ccr1_wdec; +ex2_ccr2_we <= ex2_ccr2_wdec; +ex2_dac1_we <= ex2_dac1_wdec; +ex2_dac2_we <= ex2_dac2_wdec; +ex2_dac3_we <= ex2_dac3_wdec; +ex2_dac4_we <= ex2_dac4_wdec; +ex2_givpr_we <= ex2_givpr_wdec; +ex2_iac1_we <= ex2_iac1_wdec; +ex2_iac2_we <= ex2_iac2_wdec; +ex2_iac3_we <= ex2_iac3_wdec; +ex2_iac4_we <= ex2_iac4_wdec; +ex2_ivpr_we <= ex2_ivpr_wdec; +ex2_tbl_we <= ex2_tbl_wdec; +ex2_tbu_we <= ex2_tbu_wdec; +ex2_tenc_we <= ex2_tenc_wdec; +ex2_tens_we <= ex2_tens_wdec; +ex2_trace_we <= ex2_trace_wdec; +ex2_xucr0_we <= ex2_xucr0_wdec; +ex2_xucr3_we <= ex2_xucr3_wdec; +ex2_xucr4_we <= ex2_xucr4_wdec; + + +ill_spr_00 : if a2mode = 0 and hvmode = 0 generate +ex2_illeg_mfspr <= ex2_is_mfspr_q and not ( + ex2_ccr0_rdec or ex2_ccr1_rdec or ex2_ccr2_rdec + or ex2_dac3_rdec or ex2_dac4_rdec or ex2_iac1_rdec + or ex2_iac2_rdec or ex2_ivpr_rdec or ex2_pir_rdec + or ex2_pvr_rdec or ex2_tb_rdec or ex2_tbu_rdec + or ex2_tenc_rdec or ex2_tens_rdec or ex2_tensr_rdec + or ex2_tir_rdec or ex2_xucr0_rdec or ex2_xucr3_rdec + or ex2_xucr4_rdec or + ex2_sprg0_rdec or ex2_sprg1_rdec or ex2_sprg2_rdec + or ex2_sprg3_rdec or ex2_sprg4_rdec or ex2_sprg5_rdec + or ex2_sprg6_rdec or ex2_sprg7_rdec or ex2_sprg8_rdec + or ex2_vrsave_rdec or + ex2_iucr0_rdec or ex2_iucr1_rdec or ex2_iucr2_rdec + or ex2_iudbg0_rdec or ex2_iudbg1_rdec or ex2_iudbg2_rdec + or ex2_iulfsr_rdec or ex2_iullcr_rdec or ex2_lpidr_rdec + or ex2_pid_rdec or ex2_ppr32_rdec or ex2_xucr2_rdec + or ex2_xudbg0_rdec or ex2_xudbg1_rdec or ex2_xudbg2_rdec or + ex2_slowspr_range or + or_reduce(tspr_cspr_illeg_mfspr_b and ex2_tid)); + +ex2_illeg_mtspr <= ex2_is_mtspr_q and not ( + ex2_ccr0_wdec or ex2_ccr1_wdec or ex2_ccr2_wdec + or ex2_dac3_wdec or ex2_dac4_wdec or ex2_iac1_wdec + or ex2_iac2_wdec or ex2_ivpr_wdec or ex2_tbl_wdec + or ex2_tbu_wdec or ex2_tenc_wdec or ex2_tens_wdec + or ex2_trace_wdec or ex2_xucr0_wdec or ex2_xucr3_wdec + or ex2_xucr4_wdec or + ex2_sprg0_wdec or ex2_sprg1_wdec or ex2_sprg2_wdec + or ex2_sprg3_wdec or ex2_sprg4_wdec or ex2_sprg5_wdec + or ex2_sprg6_wdec or ex2_sprg7_wdec or ex2_sprg8_wdec + or ex2_vrsave_wdec or + ex2_iucr0_wdec or ex2_iucr1_wdec or ex2_iucr2_wdec + or ex2_iudbg0_wdec or ex2_iulfsr_wdec or ex2_iullcr_wdec + or ex2_lpidr_wdec or ex2_pid_wdec or ex2_ppr32_wdec + or ex2_xucr2_wdec or ex2_xudbg0_wdec or + ex2_slowspr_range or + or_reduce(tspr_cspr_illeg_mtspr_b and ex2_tid)); + +ex2_hypv_mfspr <= ex2_is_mfspr_q and ( + ex2_ccr0_re or ex2_ccr1_re or ex2_ccr2_re + or ex2_dac3_re or ex2_dac4_re or ex2_iac1_re + or ex2_iac2_re or ex2_ivpr_re or ex2_tenc_re + or ex2_tens_re or ex2_tensr_re or ex2_tir_re + or ex2_xucr0_re or ex2_xucr3_re or ex2_xucr4_re or + ex2_sprg8_re or + ex2_iucr0_re or ex2_iucr1_re or ex2_iucr2_re + or ex2_iudbg0_re or ex2_iudbg1_re or ex2_iudbg2_re + or ex2_iulfsr_re or ex2_iullcr_re or ex2_lpidr_re + or ex2_xucr2_re or ex2_xudbg0_re or ex2_xudbg1_re + or ex2_xudbg2_re or + ex2_slowspr_range_hypv or + or_reduce(tspr_cspr_hypv_mfspr and ex2_tid)); + +ex2_hypv_mtspr <= ex2_is_mtspr_q and ( + ex2_ccr0_we or ex2_ccr1_we or ex2_ccr2_we + or ex2_dac3_we or ex2_dac4_we or ex2_iac1_we + or ex2_iac2_we or ex2_ivpr_we or ex2_tbl_we + or ex2_tbu_we or ex2_tenc_we or ex2_tens_we + or ex2_xucr0_we or ex2_xucr3_we or ex2_xucr4_we or + ex2_sprg8_we or + ex2_iucr0_we or ex2_iucr1_we or ex2_iucr2_we + or ex2_iudbg0_we or ex2_iulfsr_we or ex2_iullcr_we + or ex2_lpidr_we or ex2_xucr2_we or ex2_xudbg0_we or + ex2_slowspr_range_hypv or + or_reduce(tspr_cspr_hypv_mtspr and ex2_tid)); + +end generate; +ill_spr_01 : if a2mode = 0 and hvmode = 1 generate +ex2_illeg_mfspr <= ex2_is_mfspr_q and not ( + ex2_ccr0_rdec or ex2_ccr1_rdec or ex2_ccr2_rdec + or ex2_dac3_rdec or ex2_dac4_rdec or ex2_givpr_rdec + or ex2_iac1_rdec or ex2_iac2_rdec or ex2_ivpr_rdec + or ex2_pir_rdec or ex2_pvr_rdec or ex2_tb_rdec + or ex2_tbu_rdec or ex2_tenc_rdec or ex2_tens_rdec + or ex2_tensr_rdec or ex2_tir_rdec or ex2_xucr0_rdec + or ex2_xucr3_rdec or ex2_xucr4_rdec or + ex2_gsprg0_rdec or ex2_gsprg1_rdec or ex2_gsprg2_rdec + or ex2_gsprg3_rdec or ex2_sprg0_rdec or ex2_sprg1_rdec + or ex2_sprg2_rdec or ex2_sprg3_rdec or ex2_sprg4_rdec + or ex2_sprg5_rdec or ex2_sprg6_rdec or ex2_sprg7_rdec + or ex2_sprg8_rdec or ex2_vrsave_rdec or + ex2_eplc_rdec or ex2_epsc_rdec or ex2_eptcfg_rdec + or ex2_iucr0_rdec or ex2_iucr1_rdec or ex2_iucr2_rdec + or ex2_iudbg0_rdec or ex2_iudbg1_rdec or ex2_iudbg2_rdec + or ex2_iulfsr_rdec or ex2_iullcr_rdec or ex2_lper_rdec + or ex2_lperu_rdec or ex2_lpidr_rdec or ex2_lratcfg_rdec + or ex2_lratps_rdec or ex2_mas0_rdec or ex2_mas0_mas1_rdec + or ex2_mas1_rdec or ex2_mas2_rdec or ex2_mas2u_rdec + or ex2_mas3_rdec or ex2_mas4_rdec or ex2_mas5_rdec + or ex2_mas5_mas6_rdec or ex2_mas6_rdec or ex2_mas7_rdec + or ex2_mas7_mas3_rdec or ex2_mas8_rdec or ex2_mas8_mas1_rdec + or ex2_mmucfg_rdec or ex2_mmucr3_rdec or ex2_mmucsr0_rdec + or ex2_pid_rdec or ex2_ppr32_rdec or ex2_tlb0cfg_rdec + or ex2_tlb0ps_rdec or ex2_xucr2_rdec or ex2_xudbg0_rdec + or ex2_xudbg1_rdec or ex2_xudbg2_rdec or + ex2_slowspr_range or + or_reduce(tspr_cspr_illeg_mfspr_b and ex2_tid)); + +ex2_illeg_mtspr <= ex2_is_mtspr_q and not ( + ex2_ccr0_wdec or ex2_ccr1_wdec or ex2_ccr2_wdec + or ex2_dac3_wdec or ex2_dac4_wdec or ex2_givpr_wdec + or ex2_iac1_wdec or ex2_iac2_wdec or ex2_ivpr_wdec + or ex2_tbl_wdec or ex2_tbu_wdec or ex2_tenc_wdec + or ex2_tens_wdec or ex2_trace_wdec or ex2_xucr0_wdec + or ex2_xucr3_wdec or ex2_xucr4_wdec or + ex2_gsprg0_wdec or ex2_gsprg1_wdec or ex2_gsprg2_wdec + or ex2_gsprg3_wdec or ex2_sprg0_wdec or ex2_sprg1_wdec + or ex2_sprg2_wdec or ex2_sprg3_wdec or ex2_sprg4_wdec + or ex2_sprg5_wdec or ex2_sprg6_wdec or ex2_sprg7_wdec + or ex2_sprg8_wdec or ex2_vrsave_wdec or + ex2_eplc_wdec or ex2_epsc_wdec or ex2_iucr0_wdec + or ex2_iucr1_wdec or ex2_iucr2_wdec or ex2_iudbg0_wdec + or ex2_iulfsr_wdec or ex2_iullcr_wdec or ex2_lper_wdec + or ex2_lperu_wdec or ex2_lpidr_wdec or ex2_mas0_wdec + or ex2_mas0_mas1_wdec or ex2_mas1_wdec or ex2_mas2_wdec + or ex2_mas2u_wdec or ex2_mas3_wdec or ex2_mas4_wdec + or ex2_mas5_wdec or ex2_mas5_mas6_wdec or ex2_mas6_wdec + or ex2_mas7_wdec or ex2_mas7_mas3_wdec or ex2_mas8_wdec + or ex2_mas8_mas1_wdec or ex2_mmucr3_wdec or ex2_mmucsr0_wdec + or ex2_pid_wdec or ex2_ppr32_wdec or ex2_xucr2_wdec + or ex2_xudbg0_wdec or + ex2_slowspr_range or + or_reduce(tspr_cspr_illeg_mtspr_b and ex2_tid)); + +ex2_hypv_mfspr <= ex2_is_mfspr_q and ( + ex2_ccr0_re or ex2_ccr1_re or ex2_ccr2_re + or ex2_dac3_re or ex2_dac4_re or ex2_iac1_re + or ex2_iac2_re or ex2_ivpr_re or ex2_tenc_re + or ex2_tens_re or ex2_tensr_re or ex2_tir_re + or ex2_xucr0_re or ex2_xucr3_re or ex2_xucr4_re or + ex2_sprg8_re or + ex2_eptcfg_re or ex2_iucr0_re or ex2_iucr1_re + or ex2_iucr2_re or ex2_iudbg0_re or ex2_iudbg1_re + or ex2_iudbg2_re or ex2_iulfsr_re or ex2_iullcr_re + or ex2_lper_re or ex2_lperu_re or ex2_lpidr_re + or ex2_lratcfg_re or ex2_lratps_re or ex2_mas5_re + or ex2_mas5_mas6_re or ex2_mas8_re or ex2_mas8_mas1_re + or ex2_mmucfg_re or ex2_mmucsr0_re or ex2_tlb0cfg_re + or ex2_tlb0ps_re or ex2_xucr2_re or ex2_xudbg0_re + or ex2_xudbg1_re or ex2_xudbg2_re or + ex2_slowspr_range_hypv or + or_reduce(tspr_cspr_hypv_mfspr and ex2_tid)); + +ex2_hypv_mtspr <= ex2_is_mtspr_q and ( + ex2_ccr0_we or ex2_ccr1_we or ex2_ccr2_we + or ex2_dac3_we or ex2_dac4_we or ex2_givpr_we + or ex2_iac1_we or ex2_iac2_we or ex2_ivpr_we + or ex2_tbl_we or ex2_tbu_we or ex2_tenc_we + or ex2_tens_we or ex2_xucr0_we or ex2_xucr3_we + or ex2_xucr4_we or + ex2_sprg8_we or + ex2_iucr0_we or ex2_iucr1_we or ex2_iucr2_we + or ex2_iudbg0_we or ex2_iulfsr_we or ex2_iullcr_we + or ex2_lper_we or ex2_lperu_we or ex2_lpidr_we + or ex2_mas5_we or ex2_mas5_mas6_we or ex2_mas8_we + or ex2_mas8_mas1_we or ex2_mmucsr0_we or ex2_xucr2_we + or ex2_xudbg0_we or + ex2_slowspr_range_hypv or + or_reduce(tspr_cspr_hypv_mtspr and ex2_tid)); + +end generate; +ill_spr_10 : if a2mode = 1 and hvmode = 0 generate +ex2_illeg_mfspr <= ex2_is_mfspr_q and not ( + ex2_ccr0_rdec or ex2_ccr1_rdec or ex2_ccr2_rdec + or ex2_dac1_rdec or ex2_dac2_rdec or ex2_dac3_rdec + or ex2_dac4_rdec or ex2_iac1_rdec or ex2_iac2_rdec + or ex2_iac3_rdec or ex2_iac4_rdec or ex2_ivpr_rdec + or ex2_pir_rdec or ex2_pvr_rdec or ex2_tb_rdec + or ex2_tbu_rdec or ex2_tenc_rdec or ex2_tens_rdec + or ex2_tensr_rdec or ex2_tir_rdec or ex2_xucr0_rdec + or ex2_xucr3_rdec or ex2_xucr4_rdec or + ex2_sprg0_rdec or ex2_sprg1_rdec or ex2_sprg2_rdec + or ex2_sprg3_rdec or ex2_sprg4_rdec or ex2_sprg5_rdec + or ex2_sprg6_rdec or ex2_sprg7_rdec or ex2_sprg8_rdec + or ex2_vrsave_rdec or + ex2_dvc1_rdec or ex2_dvc2_rdec or ex2_immr_rdec + or ex2_imr_rdec or ex2_iucr0_rdec or ex2_iucr1_rdec + or ex2_iucr2_rdec or ex2_iudbg0_rdec or ex2_iudbg1_rdec + or ex2_iudbg2_rdec or ex2_iulfsr_rdec or ex2_iullcr_rdec + or ex2_lpidr_rdec or ex2_mmucr0_rdec or ex2_mmucr1_rdec + or ex2_mmucr2_rdec or ex2_pid_rdec or ex2_ppr32_rdec + or ex2_xucr2_rdec or ex2_xudbg0_rdec or ex2_xudbg1_rdec + or ex2_xudbg2_rdec or + ex2_slowspr_range or + or_reduce(tspr_cspr_illeg_mfspr_b and ex2_tid)); + +ex2_illeg_mtspr <= ex2_is_mtspr_q and not ( + ex2_ccr0_wdec or ex2_ccr1_wdec or ex2_ccr2_wdec + or ex2_dac1_wdec or ex2_dac2_wdec or ex2_dac3_wdec + or ex2_dac4_wdec or ex2_iac1_wdec or ex2_iac2_wdec + or ex2_iac3_wdec or ex2_iac4_wdec or ex2_ivpr_wdec + or ex2_tbl_wdec or ex2_tbu_wdec or ex2_tenc_wdec + or ex2_tens_wdec or ex2_trace_wdec or ex2_xucr0_wdec + or ex2_xucr3_wdec or ex2_xucr4_wdec or + ex2_sprg0_wdec or ex2_sprg1_wdec or ex2_sprg2_wdec + or ex2_sprg3_wdec or ex2_sprg4_wdec or ex2_sprg5_wdec + or ex2_sprg6_wdec or ex2_sprg7_wdec or ex2_sprg8_wdec + or ex2_vrsave_wdec or + ex2_dvc1_wdec or ex2_dvc2_wdec or ex2_immr_wdec + or ex2_imr_wdec or ex2_iucr0_wdec or ex2_iucr1_wdec + or ex2_iucr2_wdec or ex2_iudbg0_wdec or ex2_iulfsr_wdec + or ex2_iullcr_wdec or ex2_lpidr_wdec or ex2_mmucr0_wdec + or ex2_mmucr1_wdec or ex2_mmucr2_wdec or ex2_pid_wdec + or ex2_ppr32_wdec or ex2_xucr2_wdec or ex2_xudbg0_wdec or + ex2_slowspr_range or + or_reduce(tspr_cspr_illeg_mtspr_b and ex2_tid)); + +ex2_hypv_mfspr <= ex2_is_mfspr_q and ( + ex2_ccr0_re or ex2_ccr1_re or ex2_ccr2_re + or ex2_dac1_re or ex2_dac2_re or ex2_dac3_re + or ex2_dac4_re or ex2_iac1_re or ex2_iac2_re + or ex2_iac3_re or ex2_iac4_re or ex2_ivpr_re + or ex2_tenc_re or ex2_tens_re or ex2_tensr_re + or ex2_tir_re or ex2_xucr0_re or ex2_xucr3_re + or ex2_xucr4_re or + ex2_sprg8_re or + ex2_dvc1_re or ex2_dvc2_re or ex2_immr_re + or ex2_imr_re or ex2_iucr0_re or ex2_iucr1_re + or ex2_iucr2_re or ex2_iudbg0_re or ex2_iudbg1_re + or ex2_iudbg2_re or ex2_iulfsr_re or ex2_iullcr_re + or ex2_lpidr_re or ex2_mmucr0_re or ex2_mmucr1_re + or ex2_mmucr2_re or ex2_xucr2_re or ex2_xudbg0_re + or ex2_xudbg1_re or ex2_xudbg2_re or + ex2_slowspr_range_hypv or + or_reduce(tspr_cspr_hypv_mfspr and ex2_tid)); + +ex2_hypv_mtspr <= ex2_is_mtspr_q and ( + ex2_ccr0_we or ex2_ccr1_we or ex2_ccr2_we + or ex2_dac1_we or ex2_dac2_we or ex2_dac3_we + or ex2_dac4_we or ex2_iac1_we or ex2_iac2_we + or ex2_iac3_we or ex2_iac4_we or ex2_ivpr_we + or ex2_tbl_we or ex2_tbu_we or ex2_tenc_we + or ex2_tens_we or ex2_xucr0_we or ex2_xucr3_we + or ex2_xucr4_we or + ex2_sprg8_we or + ex2_dvc1_we or ex2_dvc2_we or ex2_immr_we + or ex2_imr_we or ex2_iucr0_we or ex2_iucr1_we + or ex2_iucr2_we or ex2_iudbg0_we or ex2_iulfsr_we + or ex2_iullcr_we or ex2_lpidr_we or ex2_mmucr0_we + or ex2_mmucr1_we or ex2_mmucr2_we or ex2_xucr2_we + or ex2_xudbg0_we or + ex2_slowspr_range_hypv or + or_reduce(tspr_cspr_hypv_mtspr and ex2_tid)); + +end generate; +ill_spr_11 : if a2mode = 1 and hvmode = 1 generate +ex2_illeg_mfspr <= ex2_is_mfspr_q and not ( + ex2_ccr0_rdec or ex2_ccr1_rdec or ex2_ccr2_rdec + or ex2_dac1_rdec or ex2_dac2_rdec or ex2_dac3_rdec + or ex2_dac4_rdec or ex2_givpr_rdec or ex2_iac1_rdec + or ex2_iac2_rdec or ex2_iac3_rdec or ex2_iac4_rdec + or ex2_ivpr_rdec or ex2_pir_rdec or ex2_pvr_rdec + or ex2_tb_rdec or ex2_tbu_rdec or ex2_tenc_rdec + or ex2_tens_rdec or ex2_tensr_rdec or ex2_tir_rdec + or ex2_xucr0_rdec or ex2_xucr3_rdec or ex2_xucr4_rdec or + ex2_gsprg0_rdec or ex2_gsprg1_rdec or ex2_gsprg2_rdec + or ex2_gsprg3_rdec or ex2_sprg0_rdec or ex2_sprg1_rdec + or ex2_sprg2_rdec or ex2_sprg3_rdec or ex2_sprg4_rdec + or ex2_sprg5_rdec or ex2_sprg6_rdec or ex2_sprg7_rdec + or ex2_sprg8_rdec or ex2_vrsave_rdec or + ex2_dvc1_rdec or ex2_dvc2_rdec or ex2_eplc_rdec + or ex2_epsc_rdec or ex2_eptcfg_rdec or ex2_immr_rdec + or ex2_imr_rdec or ex2_iucr0_rdec or ex2_iucr1_rdec + or ex2_iucr2_rdec or ex2_iudbg0_rdec or ex2_iudbg1_rdec + or ex2_iudbg2_rdec or ex2_iulfsr_rdec or ex2_iullcr_rdec + or ex2_lper_rdec or ex2_lperu_rdec or ex2_lpidr_rdec + or ex2_lratcfg_rdec or ex2_lratps_rdec or ex2_mas0_rdec + or ex2_mas0_mas1_rdec or ex2_mas1_rdec or ex2_mas2_rdec + or ex2_mas2u_rdec or ex2_mas3_rdec or ex2_mas4_rdec + or ex2_mas5_rdec or ex2_mas5_mas6_rdec or ex2_mas6_rdec + or ex2_mas7_rdec or ex2_mas7_mas3_rdec or ex2_mas8_rdec + or ex2_mas8_mas1_rdec or ex2_mmucfg_rdec or ex2_mmucr0_rdec + or ex2_mmucr1_rdec or ex2_mmucr2_rdec or ex2_mmucr3_rdec + or ex2_mmucsr0_rdec or ex2_pid_rdec or ex2_ppr32_rdec + or ex2_tlb0cfg_rdec or ex2_tlb0ps_rdec or ex2_xucr2_rdec + or ex2_xudbg0_rdec or ex2_xudbg1_rdec or ex2_xudbg2_rdec or + ex2_slowspr_range or + or_reduce(tspr_cspr_illeg_mfspr_b and ex2_tid)); + +ex2_illeg_mtspr <= ex2_is_mtspr_q and not ( + ex2_ccr0_wdec or ex2_ccr1_wdec or ex2_ccr2_wdec + or ex2_dac1_wdec or ex2_dac2_wdec or ex2_dac3_wdec + or ex2_dac4_wdec or ex2_givpr_wdec or ex2_iac1_wdec + or ex2_iac2_wdec or ex2_iac3_wdec or ex2_iac4_wdec + or ex2_ivpr_wdec or ex2_tbl_wdec or ex2_tbu_wdec + or ex2_tenc_wdec or ex2_tens_wdec or ex2_trace_wdec + or ex2_xucr0_wdec or ex2_xucr3_wdec or ex2_xucr4_wdec or + ex2_gsprg0_wdec or ex2_gsprg1_wdec or ex2_gsprg2_wdec + or ex2_gsprg3_wdec or ex2_sprg0_wdec or ex2_sprg1_wdec + or ex2_sprg2_wdec or ex2_sprg3_wdec or ex2_sprg4_wdec + or ex2_sprg5_wdec or ex2_sprg6_wdec or ex2_sprg7_wdec + or ex2_sprg8_wdec or ex2_vrsave_wdec or + ex2_dvc1_wdec or ex2_dvc2_wdec or ex2_eplc_wdec + or ex2_epsc_wdec or ex2_immr_wdec or ex2_imr_wdec + or ex2_iucr0_wdec or ex2_iucr1_wdec or ex2_iucr2_wdec + or ex2_iudbg0_wdec or ex2_iulfsr_wdec or ex2_iullcr_wdec + or ex2_lper_wdec or ex2_lperu_wdec or ex2_lpidr_wdec + or ex2_mas0_wdec or ex2_mas0_mas1_wdec or ex2_mas1_wdec + or ex2_mas2_wdec or ex2_mas2u_wdec or ex2_mas3_wdec + or ex2_mas4_wdec or ex2_mas5_wdec or ex2_mas5_mas6_wdec + or ex2_mas6_wdec or ex2_mas7_wdec or ex2_mas7_mas3_wdec + or ex2_mas8_wdec or ex2_mas8_mas1_wdec or ex2_mmucr0_wdec + or ex2_mmucr1_wdec or ex2_mmucr2_wdec or ex2_mmucr3_wdec + or ex2_mmucsr0_wdec or ex2_pid_wdec or ex2_ppr32_wdec + or ex2_xucr2_wdec or ex2_xudbg0_wdec or + ex2_slowspr_range or + or_reduce(tspr_cspr_illeg_mtspr_b and ex2_tid)); + +ex2_hypv_mfspr <= ex2_is_mfspr_q and ( + ex2_ccr0_re or ex2_ccr1_re or ex2_ccr2_re + or ex2_dac1_re or ex2_dac2_re or ex2_dac3_re + or ex2_dac4_re or ex2_iac1_re or ex2_iac2_re + or ex2_iac3_re or ex2_iac4_re or ex2_ivpr_re + or ex2_tenc_re or ex2_tens_re or ex2_tensr_re + or ex2_tir_re or ex2_xucr0_re or ex2_xucr3_re + or ex2_xucr4_re or + ex2_sprg8_re or + ex2_dvc1_re or ex2_dvc2_re or ex2_eptcfg_re + or ex2_immr_re or ex2_imr_re or ex2_iucr0_re + or ex2_iucr1_re or ex2_iucr2_re or ex2_iudbg0_re + or ex2_iudbg1_re or ex2_iudbg2_re or ex2_iulfsr_re + or ex2_iullcr_re or ex2_lper_re or ex2_lperu_re + or ex2_lpidr_re or ex2_lratcfg_re or ex2_lratps_re + or ex2_mas5_re or ex2_mas5_mas6_re or ex2_mas8_re + or ex2_mas8_mas1_re or ex2_mmucfg_re or ex2_mmucr0_re + or ex2_mmucr1_re or ex2_mmucr2_re or ex2_mmucsr0_re + or ex2_tlb0cfg_re or ex2_tlb0ps_re or ex2_xucr2_re + or ex2_xudbg0_re or ex2_xudbg1_re or ex2_xudbg2_re or + ex2_slowspr_range_hypv or + or_reduce(tspr_cspr_hypv_mfspr and ex2_tid)); + +ex2_hypv_mtspr <= ex2_is_mtspr_q and ( + ex2_ccr0_we or ex2_ccr1_we or ex2_ccr2_we + or ex2_dac1_we or ex2_dac2_we or ex2_dac3_we + or ex2_dac4_we or ex2_givpr_we or ex2_iac1_we + or ex2_iac2_we or ex2_iac3_we or ex2_iac4_we + or ex2_ivpr_we or ex2_tbl_we or ex2_tbu_we + or ex2_tenc_we or ex2_tens_we or ex2_xucr0_we + or ex2_xucr3_we or ex2_xucr4_we or + ex2_sprg8_we or + ex2_dvc1_we or ex2_dvc2_we or ex2_immr_we + or ex2_imr_we or ex2_iucr0_we or ex2_iucr1_we + or ex2_iucr2_we or ex2_iudbg0_we or ex2_iulfsr_we + or ex2_iullcr_we or ex2_lper_we or ex2_lperu_we + or ex2_lpidr_we or ex2_mas5_we or ex2_mas5_mas6_we + or ex2_mas8_we or ex2_mas8_mas1_we or ex2_mmucr0_we + or ex2_mmucr1_we or ex2_mmucr2_we or ex2_mmucsr0_we + or ex2_xucr2_we or ex2_xudbg0_we or + ex2_slowspr_range_hypv or + or_reduce(tspr_cspr_hypv_mtspr and ex2_tid)); + +end generate; + +ex3_hypv_spr_d <= ex2_hypv_mfspr or ex2_hypv_mtspr; + +ex3_illeg_spr_d <= ex2_illeg_mfspr or ex2_illeg_mtspr or ex2_illeg_mftb; + +ex3_priv_spr_d <= (ex2_instr_q(11) and (ex2_is_mtspr_q or ex2_is_mfspr_q)) or + ex2_is_mtmsr_q or ex2_is_mfmsr_q; + +xu_pc_spr_ccr0_pme <= ccr0_q(58 to 59); +spr_ccr0_we <= ccr0_q(60 to 63); +spr_ccr2_en_dcr <= spr_ccr2_en_dcr_int; +spr_ccr2_en_dcr_int <= ccr2_q(32); +spr_ccr2_en_trace <= ccr2_q(33); +spr_ccr2_en_pc <= ccr2_q(34); +xu_iu_spr_ccr2_ifratsc <= ccr2_q(35 to 43); +xu_iu_spr_ccr2_ifrat <= ccr2_q(44); +xu_lsu_spr_ccr2_dfratsc <= ccr2_q(45 to 53); +xu_lsu_spr_ccr2_dfrat <= ccr2_q(54); +spr_ccr2_ucode_dis <= ccr2_q(55); +spr_ccr2_ap <= ccr2_q(56 to 59); +spr_ccr2_en_attn <= ccr2_q(60); +spr_ccr2_en_ditc <= ccr2_q(61); +spr_ccr2_en_icswx <= ccr2_q(62); +spr_ccr2_notlb <= ccr2_q(63); +spr_tens_ten <= tens_q(60 to 63); +spr_xucr0_clkg_ctl <= xucr0_q(33 to 37); +spr_xucr0_trace_um <= xucr0_q(38 to 41); +xu_lsu_spr_xucr0_mbar_ack <= xucr0_q(42); +xu_lsu_spr_xucr0_tlbsync <= xucr0_q(43); +spr_dec_spr_xucr0_ssdly <= xucr0_q(44 to 48); +spr_xucr0_cls <= xucr0_q(49); +xu_lsu_spr_xucr0_aflsta <= xucr0_q(50); +spr_xucr0_mddp <= xucr0_q(51); +xu_lsu_spr_xucr0_cred <= xucr0_q(52); +xu_lsu_spr_xucr0_rel <= xucr0_q(53); +spr_xucr0_mdcp <= xucr0_q(54); +spr_xucr0_tcs <= xucr0_q(55); +xu_lsu_spr_xucr0_flsta <= xucr0_q(56); +xu_lsu_spr_xucr0_l2siw <= xucr0_q(57); +xu_lsu_spr_xucr0_flh2l2 <= xucr0_q(58); +xu_lsu_spr_xucr0_dcdis <= xucr0_q(59); +xu_lsu_spr_xucr0_wlk <= xucr0_q(60); +xucr0_clfc_d <= ex6_xucr0_we and ex6_spr_wd(63); +xu_lsu_spr_xucr0_clfc <= xucr0_clfc_q; + +ex6_ccr0_di <= ex6_spr_wd(32 to 33) & + ex6_spr_wd(60 to 63) ; +ccr0_do <= tidn(0 to 0) & + tidn(0 to 31) & + ccr0_q(58 to 59) & + tidn(34 to 51) & + "0000" & + tidn(56 to 59) & + ccr0_q(60 to 63) ; +ex6_ccr1_di <= ex6_spr_wd(34 to 39) & + ex6_spr_wd(42 to 47) & + ex6_spr_wd(50 to 55) & + ex6_spr_wd(58 to 63) ; +ccr1_do <= tidn(0 to 0) & + tidn(0 to 31) & + tidn(32 to 33) & + ccr1_q(40 to 45) & + tidn(40 to 41) & + ccr1_q(46 to 51) & + tidn(48 to 49) & + ccr1_q(52 to 57) & + tidn(56 to 57) & + ccr1_q(58 to 63) ; +ex6_ccr2_di <= ex6_spr_wd(32 to 32) & + ex6_spr_wd(33 to 33) & + ex6_spr_wd(34 to 34) & + ex6_spr_wd(35 to 43) & + ex6_spr_wd(44 to 44) & + ex6_spr_wd(45 to 53) & + ex6_spr_wd(54 to 54) & + ex6_spr_wd(55 to 55) & + ex6_spr_wd(56 to 59) & + ex6_spr_wd(60 to 60) & + ex6_spr_wd(61 to 61) & + ex6_spr_wd(62 to 62) & + ex6_spr_wd(63 to 63) ; +ccr2_do <= tidn(0 to 0) & + tidn(0 to 31) & + ccr2_q(32 to 32) & + ccr2_q(33 to 33) & + ccr2_q(34 to 34) & + ccr2_q(35 to 43) & + ccr2_q(44 to 44) & + ccr2_q(45 to 53) & + ccr2_q(54 to 54) & + ccr2_q(55 to 55) & + ccr2_q(56 to 59) & + ccr2_q(60 to 60) & + ccr2_q(61 to 61) & + ccr2_q(62 to 62) & + ccr2_q(63 to 63) ; +pir_do <= tidn(0 to 0) & + tidn(0 to 31) & + tidn(32 to 53) & + an_ac_coreid_q(54 to 61) & + ex2_tid_q(0 to 1) ; +pvr_do <= tidn(0 to 0) & + tidn(0 to 31) & + version(32 to 47) & + revision(48 to 63) ; +tb_do <= tidn(0 to 0) & + tbu_q(32 to 63) & + tbl_q(32 to 63) ; +ex6_tbl_di <= ex6_spr_wd(32 to 63) ; +tbl_do <= tidn(0 to 0) & + tidn(0 to 31) & + tbl_q(32 to 63) ; +ex6_tbu_di <= ex6_spr_wd(32 to 63) ; +tbu_do <= tidn(0 to 0) & + tidn(0 to 31) & + tbu_q(32 to 63) ; +tenc_do <= tidn(0 to 0) & + tidn(0 to 31) & + tidn(32 to 59) & + tens_q(60 to 63) ; +ex6_tens_di <= ex6_spr_wd(60 to 63) ; +tens_do <= tidn(0 to 0) & + tidn(0 to 31) & + tidn(32 to 59) & + tens_q(60 to 63) ; +tensr_do <= tidn(0 to 0) & + tidn(0 to 31) & + tidn(32 to 59) & + spr_tensr(0 to 3) ; +tir_do <= tidn(0 to 0) & + tidn(0 to 31) & + tidn(32 to 61) & + ex2_tid_q(0 to 1) ; +ex6_xucr0_di <= ex6_spr_wd(32 to 36) & + ex6_spr_wd(37 to 40) & + ex6_spr_wd(41 to 41) & + ex6_spr_wd(42 to 42) & + xucr0_q(44 to 48) & + xucr0_q(49 to 49) & + ex6_spr_wd(49 to 49) & + ex6_spr_wd(50 to 50) & + ex6_spr_wd(51 to 51) & + xucr0_q(53 to 53) & + ex6_spr_wd(53 to 53) & + ex6_spr_wd(54 to 54) & + ex6_spr_wd(55 to 55) & + xucr0_q(57 to 57) & + xucr0_q(58 to 58) & + ex6_spr_wd(58 to 58) & + ex6_spr_wd(59 to 59) & + ex6_spr_wd(60 to 60) & + ex6_spr_wd(61 to 61) & + ex6_spr_wd(62 to 62) ; +xucr0_do <= tidn(0 to 0) & + tidn(0 to 31) & + xucr0_q(33 to 37) & + xucr0_q(38 to 41) & + xucr0_q(42 to 42) & + xucr0_q(43 to 43) & + xucr0_q(44 to 48) & + xucr0_q(49 to 49) & + xucr0_q(50 to 50) & + xucr0_q(51 to 51) & + xucr0_q(52 to 52) & + xucr0_q(53 to 53) & + xucr0_q(54 to 54) & + xucr0_q(55 to 55) & + xucr0_q(56 to 56) & + xucr0_q(57 to 57) & + xucr0_q(58 to 58) & + xucr0_q(59 to 59) & + xucr0_q(60 to 60) & + xucr0_q(61 to 61) & + xucr0_q(62 to 62) & + xucr0_q(63 to 63) & + '0' ; + +mark_unused(ccr0_do(0 to 64-regsize)); +mark_unused(ccr1_do(0 to 64-regsize)); +mark_unused(ccr2_do(0 to 64-regsize)); +mark_unused(pir_do(0 to 64-regsize)); +mark_unused(pvr_do(0 to 64-regsize)); +mark_unused(tb_do(0 to 64-regsize)); +mark_unused(tbl_do(0 to 64-regsize)); +mark_unused(tbu_do(0 to 64-regsize)); +mark_unused(tenc_do(0 to 64-regsize)); +mark_unused(tens_do(0 to 64-regsize)); +mark_unused(tensr_do(0 to 64-regsize)); +mark_unused(tir_do(0 to 64-regsize)); +mark_unused(xucr0_do(0 to 64-regsize)); +mark_unused(ex2_rs0_q(56 to 59)); +mark_unused(tbl_do(1 to 64)); +mark_unused(ex2_trace_we); +mark_unused(ex2_givpr_re); +mark_unused(pir_act); +mark_unused(pvr_act); +mark_unused(tenc_act); +mark_unused(tensr_act); +mark_unused(tir_act); +mark_unused(exx_act_data(1)); + +ccr0_latch : tri_ser_rlmreg_p +generic map(width => ccr0_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => ccr0_act, + forcee => bcfg_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => bcfg_slp_sl_thold_0_b, + sg => sg_0, + scin => siv_bcfg(ccr0_offset_bcfg to ccr0_offset_bcfg + ccr0_q'length-1), + scout => sov_bcfg(ccr0_offset_bcfg to ccr0_offset_bcfg + ccr0_q'length-1), + din => ccr0_d, + dout => ccr0_q); +ccr1_latch : tri_ser_rlmreg_p +generic map(width => ccr1_q'length, init => 3994575, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => ccr1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ccr1_offset to ccr1_offset + ccr1_q'length-1), + scout => sov(ccr1_offset to ccr1_offset + ccr1_q'length-1), + din => ccr1_d, + dout => ccr1_q); +ccr2_latch : tri_ser_rlmreg_p +generic map(width => ccr2_q'length, init => 1, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => ccr2_act, + forcee => ccfg_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => ccfg_sl_thold_0_b, + sg => sg_0, + scin => siv_ccfg(ccr2_offset_ccfg to ccr2_offset_ccfg + ccr2_q'length-1), + scout => sov_ccfg(ccr2_offset_ccfg to ccr2_offset_ccfg + ccr2_q'length-1), + din => ccr2_d, + dout => ccr2_q); +tbl_latch : tri_ser_rlmreg_p +generic map(width => tbl_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => tbl_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(tbl_offset to tbl_offset + tbl_q'length-1), + scout => sov(tbl_offset to tbl_offset + tbl_q'length-1), + din => tbl_d, + dout => tbl_q); +tbu_latch : tri_ser_rlmreg_p +generic map(width => tbu_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => tbu_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(tbu_offset to tbu_offset + tbu_q'length-1), + scout => sov(tbu_offset to tbu_offset + tbu_q'length-1), + din => tbu_d, + dout => tbu_q); +tens_latch : tri_ser_rlmreg_p +generic map(width => tens_q'length, init => 1, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => tens_act, + forcee => bcfg_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => bcfg_sl_thold_0_b, + sg => sg_0, + scin => siv_bcfg(tens_offset_bcfg to tens_offset_bcfg + tens_q'length-1), + scout => sov_bcfg(tens_offset_bcfg to tens_offset_bcfg + tens_q'length-1), + din => tens_d, + dout => tens_q); +xucr0_latch : tri_ser_rlmreg_p +generic map(width => xucr0_q'length, init => (230496 + spr_xucr0_init_mod), expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => xucr0_act, + forcee => ccfg_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => ccfg_sl_thold_0_b, + sg => sg_0, + scin => siv_ccfg(xucr0_offset_ccfg to xucr0_offset_ccfg + xucr0_q'length-1), + scout => sov_ccfg(xucr0_offset_ccfg to xucr0_offset_ccfg + xucr0_q'length-1), + din => xucr0_d, + dout => xucr0_q); + + +exx_act_latch : tri_rlmreg_p + generic map (width => exx_act_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(exx_act_offset to exx_act_offset + exx_act_q'length-1), + scout => sov(exx_act_offset to exx_act_offset + exx_act_q'length-1), + din => exx_act_d, + dout => exx_act_q); +rf1_instr_latch : tri_rlmreg_p + generic map (width => rf1_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DRF1), + mpw1_b => mpw1_dc_b(DRF1), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf1_instr_offset to rf1_instr_offset + rf1_instr_q'length-1), + scout => sov(rf1_instr_offset to rf1_instr_offset + rf1_instr_q'length-1), + din => dec_spr_rf0_instr , + dout => rf1_instr_q); +rf1_aspr_act_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DRF1), + mpw1_b => mpw1_dc_b(DRF1), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf1_aspr_act_offset), + scout => sov(rf1_aspr_act_offset), + din => rf1_aspr_act_d, + dout => rf1_aspr_act_q); +rf1_aspr_tid_latch : tri_rlmreg_p + generic map (width => rf1_aspr_tid_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DRF1), + mpw1_b => mpw1_dc_b(DRF1), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf1_aspr_tid_offset to rf1_aspr_tid_offset + rf1_aspr_tid_q'length-1), + scout => sov(rf1_aspr_tid_offset to rf1_aspr_tid_offset + rf1_aspr_tid_q'length-1), + din => rf1_aspr_tid_d, + dout => rf1_aspr_tid_q); +rf1_msr_gs_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DRF1), + mpw1_b => mpw1_dc_b(DRF1), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf1_msr_gs_offset), + scout => sov(rf1_msr_gs_offset), + din => rf1_msr_gs_d, + dout => rf1_msr_gs_q); +ex1_tid_latch : tri_rlmreg_p + generic map (width => ex1_tid_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX1), + mpw1_b => mpw1_dc_b(DEX1), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_tid_offset to ex1_tid_offset + ex1_tid_q'length-1), + scout => sov(ex1_tid_offset to ex1_tid_offset + ex1_tid_q'length-1), + din => rf1_tid, + dout => ex1_tid_q); +ex1_is_mfspr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX1), + mpw1_b => mpw1_dc_b(DEX1), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_mfspr_offset), + scout => sov(ex1_is_mfspr_offset), + din => rf1_is_mfspr, + dout => ex1_is_mfspr_q); +ex1_is_mtspr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX1), + mpw1_b => mpw1_dc_b(DEX1), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_mtspr_offset), + scout => sov(ex1_is_mtspr_offset), + din => rf1_is_mtspr, + dout => ex1_is_mtspr_q); +ex1_instr_latch : tri_rlmreg_p + generic map (width => ex1_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX1), + mpw1_b => mpw1_dc_b(DEX1), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_instr_offset to ex1_instr_offset + ex1_instr_q'length-1), + scout => sov(ex1_instr_offset to ex1_instr_offset + ex1_instr_q'length-1), + din => rf1_instr_q , + dout => ex1_instr_q); +ex1_aspr_re_latch : tri_rlmreg_p + generic map (width => ex1_aspr_re_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX1), + mpw1_b => mpw1_dc_b(DEX1), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_aspr_re_offset to ex1_aspr_re_offset + ex1_aspr_re_q'length-1), + scout => sov(ex1_aspr_re_offset to ex1_aspr_re_offset + ex1_aspr_re_q'length-1), + din => rf1_aspr_re, + dout => ex1_aspr_re_q); +ex1_aspr_ce_addr_latch : tri_rlmreg_p + generic map (width => ex1_aspr_ce_addr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX1), + mpw1_b => mpw1_dc_b(DEX1), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_aspr_ce_addr_offset to ex1_aspr_ce_addr_offset + ex1_aspr_ce_addr_q'length-1), + scout => sov(ex1_aspr_ce_addr_offset to ex1_aspr_ce_addr_offset + ex1_aspr_ce_addr_q'length-1), + din => rf1_aspr_addr, + dout => ex1_aspr_ce_addr_q); +ex2_tid_latch : tri_regk + generic map (width => ex2_tid_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex1_tid_q , + dout => ex2_tid_q); +ex2_is_mfmsr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_mfmsr, + dout(0) => ex2_is_mfmsr_q); +ex2_is_mfspr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_mfspr_q , + dout(0) => ex2_is_mfspr_q); +ex2_is_mftb_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_mftb, + dout(0) => ex2_is_mftb_q); +ex2_is_mtmsr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_mtmsr, + dout(0) => ex2_is_mtmsr_q); +ex2_is_mtspr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_mtspr_q , + dout(0) => ex2_is_mtspr_q); +ex2_is_wait_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_wait, + dout(0) => ex2_is_wait_q); +ex2_wait_wc_latch : tri_regk + generic map (width => ex2_wait_wc_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act_data(1), + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex1_instr_q(9 to 10) , + dout => ex2_wait_wc_q); +ex2_is_msgclr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_msgclr, + dout(0) => ex2_is_msgclr_q); +ex2_instr_latch : tri_regk + generic map (width => ex2_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex2_instr_d, + dout => ex2_instr_q); +ex2_rs0_latch : tri_regk + generic map (width => ex2_rs0_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => fxu_spr_ex1_rs0 , + dout => ex2_rs0_q); +ex2_msr_gs_latch : tri_regk + generic map (width => ex2_msr_gs_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex2_msr_gs_d, + dout => ex2_msr_gs_q); +ex2_tenc_we_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_tenc_we, + dout(0) => ex2_tenc_we_q); +ex2_ccr0_we_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_ccr0_we, + dout(0) => ex2_ccr0_we_q); +ex2_aspr_rdata_latch : tri_rlmreg_p + generic map (width => ex2_aspr_rdata_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act_data(1), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_aspr_rdata_offset to ex2_aspr_rdata_offset + ex2_aspr_rdata_q'length-1), + scout => sov(ex2_aspr_rdata_offset to ex2_aspr_rdata_offset + ex2_aspr_rdata_q'length-1), + din => ex2_aspr_rdata_d, + dout => ex2_aspr_rdata_q); +ex2_dcrn_latch : tri_regk + generic map (width => ex2_dcrn_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act_data(1), + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => fxu_spr_ex1_rs1 , + dout => ex2_dcrn_q); +ex2_dcr_val_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_dcr_val, + dout(0) => ex2_dcr_val_q); +ex2_aspr_ce_addr_latch : tri_regk + generic map (width => ex2_aspr_ce_addr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex1_aspr_ce_addr_q , + dout => ex2_aspr_ce_addr_q); +ex2_aspr_re_latch : tri_regk + generic map (width => ex2_aspr_re_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex1_aspr_re_q , + dout => ex2_aspr_re_q); +ex2_dcr_read_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_dcr_read, + dout(0) => ex2_dcr_read_q); +ex2_dcr_user_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_dcr_user, + dout(0) => ex2_dcr_user_q); +ex2_is_wrtee_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_wrtee, + dout(0) => ex2_is_wrtee_q); +ex2_is_wrteei_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_wrteei, + dout(0) => ex2_is_wrteei_q); +ex3_tid_latch : tri_rlmreg_p + generic map (width => ex3_tid_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_tid_offset to ex3_tid_offset + ex3_tid_q'length-1), + scout => sov(ex3_tid_offset to ex3_tid_offset + ex3_tid_q'length-1), + din => ex2_tid_q , + dout => ex3_tid_q); +ex3_is_mtmsr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_mtmsr_offset), + scout => sov(ex3_is_mtmsr_offset), + din => ex2_is_mtmsr_q , + dout => ex3_is_mtmsr_q); +ex3_is_mtspr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_mtspr_offset), + scout => sov(ex3_is_mtspr_offset), + din => ex2_is_mtspr_q , + dout => ex3_is_mtspr_q); +ex3_wait_wc_latch : tri_rlmreg_p + generic map (width => ex3_wait_wc_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act_data(2), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wait_wc_offset to ex3_wait_wc_offset + ex3_wait_wc_q'length-1), + scout => sov(ex3_wait_wc_offset to ex3_wait_wc_offset + ex3_wait_wc_q'length-1), + din => ex2_wait_wc_q , + dout => ex3_wait_wc_q); +ex3_is_msgclr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_msgclr_offset), + scout => sov(ex3_is_msgclr_offset), + din => ex2_is_msgclr_q , + dout => ex3_is_msgclr_q); +ex3_instr_latch : tri_rlmreg_p + generic map (width => ex3_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_instr_offset to ex3_instr_offset + ex3_instr_q'length-1), + scout => sov(ex3_instr_offset to ex3_instr_offset + ex3_instr_q'length-1), + din => ex3_instr_d, + dout => ex3_instr_q); +ex3_cspr_rt_latch : tri_rlmreg_p + generic map (width => ex3_cspr_rt_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act_data(2), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_cspr_rt_offset to ex3_cspr_rt_offset + ex3_cspr_rt_q'length-1), + scout => sov(ex3_cspr_rt_offset to ex3_cspr_rt_offset + ex3_cspr_rt_q'length-1), + din => ex2_cspr_rt, + dout => ex3_cspr_rt_q); +ex3_hypv_spr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_hypv_spr_offset), + scout => sov(ex3_hypv_spr_offset), + din => ex3_hypv_spr_d, + dout => ex3_hypv_spr_q); +ex3_illeg_spr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_illeg_spr_offset), + scout => sov(ex3_illeg_spr_offset), + din => ex3_illeg_spr_d, + dout => ex3_illeg_spr_q); +ex3_priv_spr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_priv_spr_offset), + scout => sov(ex3_priv_spr_offset), + din => ex3_priv_spr_d, + dout => ex3_priv_spr_q); +ex3_sspr_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_sspr_val_offset), + scout => sov(ex3_sspr_val_offset), + din => ex2_sspr_val, + dout => ex3_sspr_val_q); +ex3_rt_latch : tri_rlmreg_p + generic map (width => ex3_rt_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act_data(2), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_rt_offset to ex3_rt_offset + ex3_rt_q'length-1), + scout => sov(ex3_rt_offset to ex3_rt_offset + ex3_rt_q'length-1), + din => mux_spr_ex2_rt , + dout => ex3_rt_q); +ex3_is_mfspr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_mfspr_offset), + scout => sov(ex3_is_mfspr_offset), + din => ex2_is_mfspr_q , + dout => ex3_is_mfspr_q); +ex3_wait_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wait_offset), + scout => sov(ex3_wait_offset), + din => ex2_wait, + dout => ex3_wait_q); +ex3_corr_rdata_latch : tri_rlmreg_p + generic map (width => ex3_corr_rdata_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act_data(2), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_corr_rdata_offset to ex3_corr_rdata_offset + ex3_corr_rdata_q'length-1), + scout => sov(ex3_corr_rdata_offset to ex3_corr_rdata_offset + ex3_corr_rdata_q'length-1), + din => ex2_corr_rdata, + dout => ex3_corr_rdata_q); +ex3_sprg_ce_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_sprg_ce_offset), + scout => sov(ex3_sprg_ce_offset), + din => ex2_sprg_ce, + dout => ex3_sprg_ce_q); +ex3_sprg_ue_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_sprg_ue_offset), + scout => sov(ex3_sprg_ue_offset), + din => ex2_sprg_ue, + dout => ex3_sprg_ue_q); +ex3_aspr_ce_addr_latch : tri_rlmreg_p + generic map (width => ex3_aspr_ce_addr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_aspr_ce_addr_offset to ex3_aspr_ce_addr_offset + ex3_aspr_ce_addr_q'length-1), + scout => sov(ex3_aspr_ce_addr_offset to ex3_aspr_ce_addr_offset + ex3_aspr_ce_addr_q'length-1), + din => ex2_aspr_ce_addr_q , + dout => ex3_aspr_ce_addr_q); +ex3_dcr_read_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_dcr_read_offset), + scout => sov(ex3_dcr_read_offset), + din => ex2_dcr_read_q , + dout => ex3_dcr_read_q); +ex3_aspr_re_latch : tri_rlmreg_p + generic map (width => ex3_aspr_re_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_aspr_re_offset to ex3_aspr_re_offset + ex3_aspr_re_q'length-1), + scout => sov(ex3_aspr_re_offset to ex3_aspr_re_offset + ex3_aspr_re_q'length-1), + din => ex2_aspr_re_q , + dout => ex3_aspr_re_q); +ex3_dcr_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_dcr_val_offset), + scout => sov(ex3_dcr_val_offset), + din => ex2_dcr_val_q , + dout => ex3_dcr_val_q); +ex3_dcr_user_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_dcr_user_offset), + scout => sov(ex3_dcr_user_offset), + din => ex2_dcr_user_q , + dout => ex3_dcr_user_q); +ex3_is_wrtee_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_wrtee_offset), + scout => sov(ex3_is_wrtee_offset), + din => ex2_is_wrtee_q , + dout => ex3_is_wrtee_q); +ex3_is_wrteei_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_wrteei_offset), + scout => sov(ex3_is_wrteei_offset), + din => ex2_is_wrteei_q , + dout => ex3_is_wrteei_q); +ex3_msr_gs_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_msr_gs_offset), + scout => sov(ex3_msr_gs_offset), + din => ex3_msr_gs_d, + dout => ex3_msr_gs_q); +ex4_tid_latch : tri_regk + generic map (width => ex4_tid_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX4), + mpw1_b => mpw1_dc_b(DEX4), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex3_tid_q , + dout => ex4_tid_q); +ex4_is_mtmsr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX4), + mpw1_b => mpw1_dc_b(DEX4), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_is_mtmsr_q , + dout(0) => ex4_is_mtmsr_q); +ex4_is_mtspr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX4), + mpw1_b => mpw1_dc_b(DEX4), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_is_mtspr_q , + dout(0) => ex4_is_mtspr_q); +ex4_wait_wc_latch : tri_regk + generic map (width => ex4_wait_wc_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX4), + mpw1_b => mpw1_dc_b(DEX4), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex3_wait_wc_q , + dout => ex4_wait_wc_q); +ex4_is_msgclr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX4), + mpw1_b => mpw1_dc_b(DEX4), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_is_msgclr_q , + dout(0) => ex4_is_msgclr_q); +ex4_instr_latch : tri_regk + generic map (width => ex4_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX4), + mpw1_b => mpw1_dc_b(DEX4), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex3_instr_q , + dout => ex4_instr_q); +ex4_sspr_val_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX4), + mpw1_b => mpw1_dc_b(DEX4), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_sspr_val_q , + dout(0) => ex4_sspr_val_q); +ex4_rt_latch : tri_regk + generic map (width => ex4_rt_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act_data(3), + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX4), + mpw1_b => mpw1_dc_b(DEX4), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex3_rt_q , + dout => ex4_rt_q); +ex4_is_mfspr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX4), + mpw1_b => mpw1_dc_b(DEX4), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_is_mfspr_q , + dout(0) => ex4_is_mfspr_q); +ex4_dcr_read_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX4), + mpw1_b => mpw1_dc_b(DEX4), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_dcr_read_q , + dout(0) => ex4_dcr_read_q); +ex4_wait_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX4), + mpw1_b => mpw1_dc_b(DEX4), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_wait_q , + dout(0) => ex4_wait_q); +ex4_corr_rdata_latch : tri_regk + generic map (width => ex4_corr_rdata_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act_data(3), + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX4), + mpw1_b => mpw1_dc_b(DEX4), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex3_corr_rdata_q , + dout => ex4_corr_rdata_q); +ex4_sprg_ce_latch : tri_regk + generic map (width => ex4_sprg_ce_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act_data(3), + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX4), + mpw1_b => mpw1_dc_b(DEX4), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex4_sprg_ce_d, + dout => ex4_sprg_ce_q); +ex4_aspr_ce_addr_latch : tri_regk + generic map (width => ex4_aspr_ce_addr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex3_sprg_ce , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX4), + mpw1_b => mpw1_dc_b(DEX4), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex3_aspr_ce_addr_q , + dout => ex4_aspr_ce_addr_q); +ex4_dcr_val_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX4), + mpw1_b => mpw1_dc_b(DEX4), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_dcr_val_q , + dout(0) => ex4_dcr_val_q); +ex4_dcr_user_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX4), + mpw1_b => mpw1_dc_b(DEX4), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_dcr_user_q , + dout(0) => ex4_dcr_user_q); +ex4_is_wrtee_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX4), + mpw1_b => mpw1_dc_b(DEX4), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_is_wrtee_q , + dout(0) => ex4_is_wrtee_q); +ex4_is_wrteei_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX4), + mpw1_b => mpw1_dc_b(DEX4), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_is_wrteei_q , + dout(0) => ex4_is_wrteei_q); +ex4_aspr_we_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX4), + mpw1_b => mpw1_dc_b(DEX4), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_aspr_we_offset), + scout => sov(ex4_aspr_we_offset), + din => ex3_aspr_we, + dout => ex4_aspr_we_q); +ex4_aspr_addr_latch : tri_rlmreg_p + generic map (width => ex4_aspr_addr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX4), + mpw1_b => mpw1_dc_b(DEX4), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_aspr_addr_offset to ex4_aspr_addr_offset + ex4_aspr_addr_q'length-1), + scout => sov(ex4_aspr_addr_offset to ex4_aspr_addr_offset + ex4_aspr_addr_q'length-1), + din => ex3_aspr_addr, + dout => ex4_aspr_addr_q); +ex5_val_latch : tri_rlmreg_p + generic map (width => ex5_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX5), + mpw1_b => mpw1_dc_b(DEX5), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_val_offset to ex5_val_offset + ex5_val_q'length-1), + scout => sov(ex5_val_offset to ex5_val_offset + ex5_val_q'length-1), + din => ex5_val_d, + dout => ex5_val_q); +ex5_tid_latch : tri_rlmreg_p + generic map (width => ex5_tid_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX5), + mpw1_b => mpw1_dc_b(DEX5), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_tid_offset to ex5_tid_offset + ex5_tid_q'length-1), + scout => sov(ex5_tid_offset to ex5_tid_offset + ex5_tid_q'length-1), + din => ex4_tid_q , + dout => ex5_tid_q); +ex5_is_mtmsr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX5), + mpw1_b => mpw1_dc_b(DEX5), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_is_mtmsr_offset), + scout => sov(ex5_is_mtmsr_offset), + din => ex4_is_mtmsr_q , + dout => ex5_is_mtmsr_q); +ex5_is_mtspr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX5), + mpw1_b => mpw1_dc_b(DEX5), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_is_mtspr_offset), + scout => sov(ex5_is_mtspr_offset), + din => ex4_is_mtspr_q , + dout => ex5_is_mtspr_q); +ex5_wait_wc_latch : tri_rlmreg_p + generic map (width => ex5_wait_wc_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act_data(4), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX5), + mpw1_b => mpw1_dc_b(DEX5), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_wait_wc_offset to ex5_wait_wc_offset + ex5_wait_wc_q'length-1), + scout => sov(ex5_wait_wc_offset to ex5_wait_wc_offset + ex5_wait_wc_q'length-1), + din => ex4_wait_wc_q , + dout => ex5_wait_wc_q); +ex5_is_msgclr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX5), + mpw1_b => mpw1_dc_b(DEX5), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_is_msgclr_offset), + scout => sov(ex5_is_msgclr_offset), + din => ex4_is_msgclr_q , + dout => ex5_is_msgclr_q); +ex5_instr_latch : tri_rlmreg_p + generic map (width => ex5_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX5), + mpw1_b => mpw1_dc_b(DEX5), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_instr_offset to ex5_instr_offset + ex5_instr_q'length-1), + scout => sov(ex5_instr_offset to ex5_instr_offset + ex5_instr_q'length-1), + din => ex4_instr_q , + dout => ex5_instr_q); +ex5_sspr_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX5), + mpw1_b => mpw1_dc_b(DEX5), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_sspr_val_offset), + scout => sov(ex5_sspr_val_offset), + din => ex4_sspr_val_q , + dout => ex5_sspr_val_q); +ex5_aspr_we_latch : tri_rlmreg_p + generic map (width => ex5_aspr_we_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX5), + mpw1_b => mpw1_dc_b(DEX5), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_aspr_we_offset to ex5_aspr_we_offset + ex5_aspr_we_q'length-1), + scout => sov(ex5_aspr_we_offset to ex5_aspr_we_offset + ex5_aspr_we_q'length-1), + din => ex5_aspr_we_d, + dout => ex5_aspr_we_q); +ex5_rt_latch : tri_rlmreg_p + generic map (width => ex5_rt_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act_data(4), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX5), + mpw1_b => mpw1_dc_b(DEX5), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_rt_offset to ex5_rt_offset + ex5_rt_q'length-1), + scout => sov(ex5_rt_offset to ex5_rt_offset + ex5_rt_q'length-1), + din => ex5_rt_d, + dout => ex5_rt_q); +ex5_wait_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX5), + mpw1_b => mpw1_dc_b(DEX5), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_wait_offset), + scout => sov(ex5_wait_offset), + din => ex4_wait_q , + dout => ex5_wait_q); +ex5_sprg_ce_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX5), + mpw1_b => mpw1_dc_b(DEX5), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_sprg_ce_offset), + scout => sov(ex5_sprg_ce_offset), + din => ex4_sprg_ce_q(0) , + dout => ex5_sprg_ce_q); +ex5_dcr_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX5), + mpw1_b => mpw1_dc_b(DEX5), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_dcr_val_offset), + scout => sov(ex5_dcr_val_offset), + din => ex4_dcr_val, + dout => ex5_dcr_val_q); +ex5_dcr_read_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX5), + mpw1_b => mpw1_dc_b(DEX5), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_dcr_read_offset), + scout => sov(ex5_dcr_read_offset), + din => ex4_dcr_read_q , + dout => ex5_dcr_read_q); +ex5_dcr_user_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX5), + mpw1_b => mpw1_dc_b(DEX5), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_dcr_user_offset), + scout => sov(ex5_dcr_user_offset), + din => ex4_dcr_user_q , + dout => ex5_dcr_user_q); +ex5_aspr_addr_latch : tri_rlmreg_p + generic map (width => ex5_aspr_addr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX5), + mpw1_b => mpw1_dc_b(DEX5), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_aspr_addr_offset to ex5_aspr_addr_offset + ex5_aspr_addr_q'length-1), + scout => sov(ex5_aspr_addr_offset to ex5_aspr_addr_offset + ex5_aspr_addr_q'length-1), + din => ex5_aspr_addr_d, + dout => ex5_aspr_addr_q); +ex5_is_wrtee_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX5), + mpw1_b => mpw1_dc_b(DEX5), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_is_wrtee_offset), + scout => sov(ex5_is_wrtee_offset), + din => ex4_is_wrtee_q , + dout => ex5_is_wrtee_q); +ex5_is_wrteei_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX5), + mpw1_b => mpw1_dc_b(DEX5), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_is_wrteei_offset), + scout => sov(ex5_is_wrteei_offset), + din => ex4_is_wrteei_q , + dout => ex5_is_wrteei_q); +ex6_valid_latch : tri_rlmreg_p + generic map (width => ex6_valid_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_valid_offset to ex6_valid_offset + ex6_valid_q'length-1), + scout => sov(ex6_valid_offset to ex6_valid_offset + ex6_valid_q'length-1), + din => ex5_valid, + dout => ex6_valid_q); +ex6_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_val_offset), + scout => sov(ex6_val_offset), + din => ex5_val, + dout => ex6_val_q); +ex6_tid_latch : tri_regk + generic map (width => ex6_tid_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(5) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex5_tid_q , + dout => ex6_tid_q); +ex6_dbell_taken_latch : tri_regk + generic map (width => ex6_dbell_taken_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => cpl_spr_ex5_dbell_taken , + dout => ex6_dbell_taken_q); +ex6_cdbell_taken_latch : tri_regk + generic map (width => ex6_cdbell_taken_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => cpl_spr_ex5_cdbell_taken , + dout => ex6_cdbell_taken_q); +ex6_gdbell_taken_latch : tri_regk + generic map (width => ex6_gdbell_taken_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => cpl_spr_ex5_gdbell_taken , + dout => ex6_gdbell_taken_q); +ex6_gcdbell_taken_latch : tri_regk + generic map (width => ex6_gcdbell_taken_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => cpl_spr_ex5_gcdbell_taken , + dout => ex6_gcdbell_taken_q); +ex6_gmcdbell_taken_latch : tri_regk + generic map (width => ex6_gmcdbell_taken_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => cpl_spr_ex5_gmcdbell_taken , + dout => ex6_gmcdbell_taken_q); +ex6_rt_latch : tri_regk + generic map (width => ex6_rt_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act_data(5), + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex5_rt_q_b(64-regsize to 63) , + dout => ex6_rt_q); +ex6_instr_latch : tri_regk + generic map (width => ex6_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(5) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex5_instr_q , + dout => ex6_instr_q); +ex6_is_mtspr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(5) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex5_is_mtspr_q , + dout(0) => ex6_is_mtspr_q); +ex6_wait_wc_latch : tri_regk + generic map (width => ex6_wait_wc_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act_data(5), + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex5_wait_wc_q , + dout => ex6_wait_wc_q); +ex6_is_msgclr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(5) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex5_is_msgclr_q , + dout(0) => ex6_is_msgclr_q); +ex6_sspr_val_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(5) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex5_sspr_val_q , + dout(0) => ex6_sspr_val_q); +ex6_set_xucr0_cslc_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex6_set_xucr0_cslc_d, + dout(0) => ex6_set_xucr0_cslc_q); +ex6_set_xucr0_cul_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex6_set_xucr0_cul_d, + dout(0) => ex6_set_xucr0_cul_q); +ex6_set_xucr0_clo_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex6_set_xucr0_clo_d, + dout(0) => ex6_set_xucr0_clo_q); +ex6_wait_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(5) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex5_wait_q , + dout(0) => ex6_wait_q); +ex6_sprg_ce_latch : tri_regk + generic map (width => ex6_sprg_ce_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(5) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex5_sprg_ce, + dout => ex6_sprg_ce_q); +ex6_dcr_val_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(5) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex5_dcr_val, + dout(0) => ex6_dcr_val_q); +ex6_dcr_read_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(5) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex5_dcr_read_q , + dout(0) => ex6_dcr_read_q); +ex6_dcr_user_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(5) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex5_dcr_user_q , + dout(0) => ex6_dcr_user_q); +ex2_any_mfspr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_any_mfspr_d, + dout(0) => ex2_any_mfspr_q); +ex2_any_mtspr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_any_mtspr_d, + dout(0) => ex2_any_mtspr_q); +ex3_any_mfspr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_any_mfspr_offset), + scout => sov(ex3_any_mfspr_offset), + din => ex2_any_mfspr_q , + dout => ex3_any_mfspr_q); +ex3_any_mtspr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_any_mtspr_offset), + scout => sov(ex3_any_mtspr_offset), + din => ex2_any_mtspr_q , + dout => ex3_any_mtspr_q); +ex4_any_mfspr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX4), + mpw1_b => mpw1_dc_b(DEX4), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_any_mfspr_q , + dout(0) => ex4_any_mfspr_q); +ex4_any_mtspr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX4), + mpw1_b => mpw1_dc_b(DEX4), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_any_mtspr_q , + dout(0) => ex4_any_mtspr_q); +ex5_any_mfspr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX5), + mpw1_b => mpw1_dc_b(DEX5), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_any_mfspr_offset), + scout => sov(ex5_any_mfspr_offset), + din => ex4_any_mfspr_q , + dout => ex5_any_mfspr_q); +ex5_any_mtspr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX5), + mpw1_b => mpw1_dc_b(DEX5), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_any_mtspr_offset), + scout => sov(ex5_any_mtspr_offset), + din => ex4_any_mtspr_q , + dout => ex5_any_mtspr_q); +running_latch : tri_rlmreg_p + generic map (width => running_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(running_offset to running_offset + running_q'length-1), + scout => sov(running_offset to running_offset + running_q'length-1), + din => running_d, + dout => running_q); +llpri_latch : tri_rlmreg_p + generic map (width => llpri_q'length, init => 8, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => llpri_inc , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(llpri_offset to llpri_offset + llpri_q'length-1), + scout => sov(llpri_offset to llpri_offset + llpri_q'length-1), + din => llpri_d, + dout => llpri_q); +dec_dbg_dis_latch : tri_rlmreg_p + generic map (width => dec_dbg_dis_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(dec_dbg_dis_offset to dec_dbg_dis_offset + dec_dbg_dis_q'length-1), + scout => sov(dec_dbg_dis_offset to dec_dbg_dis_offset + dec_dbg_dis_q'length-1), + din => dec_dbg_dis_d, + dout => dec_dbg_dis_q); +tb_dbg_dis_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(tb_dbg_dis_offset), + scout => sov(tb_dbg_dis_offset), + din => tb_dbg_dis_d, + dout => tb_dbg_dis_q); +tb_act_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(tb_act_offset), + scout => sov(tb_act_offset), + din => tb_act_d, + dout => tb_act_q); +ext_dbg_dis_latch : tri_rlmreg_p + generic map (width => ext_dbg_dis_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ext_dbg_dis_offset to ext_dbg_dis_offset + ext_dbg_dis_q'length-1), + scout => sov(ext_dbg_dis_offset to ext_dbg_dis_offset + ext_dbg_dis_q'length-1), + din => ext_dbg_dis_d, + dout => ext_dbg_dis_q); +ram_mode_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ram_mode_offset), + scout => sov(ram_mode_offset), + din => pc_xu_ram_mode , + dout => ram_mode_q); +ram_thread_latch : tri_rlmreg_p + generic map (width => ram_thread_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ram_thread_offset to ram_thread_offset + ram_thread_q'length-1), + scout => sov(ram_thread_offset to ram_thread_offset + ram_thread_q'length-1), + din => pc_xu_ram_thread , + dout => ram_thread_q); +msrovride_enab_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(msrovride_enab_offset), + scout => sov(msrovride_enab_offset), + din => pc_xu_msrovride_enab , + dout => msrovride_enab_q); +waitimpl_val_latch : tri_rlmreg_p + generic map (width => waitimpl_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(waitimpl_val_offset to waitimpl_val_offset + waitimpl_val_q'length-1), + scout => sov(waitimpl_val_offset to waitimpl_val_offset + waitimpl_val_q'length-1), + din => waitimpl_val_d, + dout => waitimpl_val_q); +waitrsv_val_latch : tri_rlmreg_p + generic map (width => waitrsv_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(waitrsv_val_offset to waitrsv_val_offset + waitrsv_val_q'length-1), + scout => sov(waitrsv_val_offset to waitrsv_val_offset + waitrsv_val_q'length-1), + din => waitrsv_val_d, + dout => waitrsv_val_q); +an_ac_reservation_vld_latch : tri_rlmreg_p + generic map (width => an_ac_reservation_vld_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(an_ac_reservation_vld_offset to an_ac_reservation_vld_offset + an_ac_reservation_vld_q'length-1), + scout => sov(an_ac_reservation_vld_offset to an_ac_reservation_vld_offset + an_ac_reservation_vld_q'length-1), + din => an_ac_reservation_vld , + dout => an_ac_reservation_vld_q); +an_ac_sleep_en_latch : tri_rlmreg_p + generic map (width => an_ac_sleep_en_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(an_ac_sleep_en_offset to an_ac_sleep_en_offset + an_ac_sleep_en_q'length-1), + scout => sov(an_ac_sleep_en_offset to an_ac_sleep_en_offset + an_ac_sleep_en_q'length-1), + din => an_ac_sleep_en , + dout => an_ac_sleep_en_q); +an_ac_coreid_latch : tri_rlmreg_p + generic map (width => an_ac_coreid_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(an_ac_coreid_offset to an_ac_coreid_offset + an_ac_coreid_q'length-1), + scout => sov(an_ac_coreid_offset to an_ac_coreid_offset + an_ac_coreid_q'length-1), + din => an_ac_coreid , + dout => an_ac_coreid_q); +tb_update_enable_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(tb_update_enable_offset), + scout => sov(tb_update_enable_offset), + din => an_ac_tb_update_enable , + dout => tb_update_enable_q); +tb_update_pulse_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(tb_update_pulse_offset), + scout => sov(tb_update_pulse_offset), + din => an_ac_tb_update_pulse , + dout => tb_update_pulse_q); +tb_update_pulse_1_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(tb_update_pulse_1_offset), + scout => sov(tb_update_pulse_1_offset), + din => tb_update_pulse_q , + dout => tb_update_pulse_1_q); +pc_xu_reset_wd_complete_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(pc_xu_reset_wd_complete_offset), + scout => sov(pc_xu_reset_wd_complete_offset), + din => pc_xu_reset_wd_complete , + dout => pc_xu_reset_wd_complete_q); +pc_xu_reset_3_complete_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(pc_xu_reset_3_complete_offset), + scout => sov(pc_xu_reset_3_complete_offset), + din => pc_xu_reset_3_complete , + dout => pc_xu_reset_3_complete_q); +pc_xu_reset_2_complete_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(pc_xu_reset_2_complete_offset), + scout => sov(pc_xu_reset_2_complete_offset), + din => pc_xu_reset_2_complete , + dout => pc_xu_reset_2_complete_q); +pc_xu_reset_1_complete_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(pc_xu_reset_1_complete_offset), + scout => sov(pc_xu_reset_1_complete_offset), + din => pc_xu_reset_1_complete , + dout => pc_xu_reset_1_complete_q); +lsu_xu_dbell_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(lsu_xu_dbell_val_offset), + scout => sov(lsu_xu_dbell_val_offset), + din => lsu_xu_dbell_val , + dout => lsu_xu_dbell_val_q); +lsu_xu_dbell_type_latch : tri_rlmreg_p + generic map (width => lsu_xu_dbell_type_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => dbell_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(lsu_xu_dbell_type_offset to lsu_xu_dbell_type_offset + lsu_xu_dbell_type_q'length-1), + scout => sov(lsu_xu_dbell_type_offset to lsu_xu_dbell_type_offset + lsu_xu_dbell_type_q'length-1), + din => lsu_xu_dbell_type , + dout => lsu_xu_dbell_type_q); +lsu_xu_dbell_brdcast_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => dbell_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(lsu_xu_dbell_brdcast_offset), + scout => sov(lsu_xu_dbell_brdcast_offset), + din => lsu_xu_dbell_brdcast , + dout => lsu_xu_dbell_brdcast_q); +lsu_xu_dbell_lpid_match_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => dbell_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(lsu_xu_dbell_lpid_match_offset), + scout => sov(lsu_xu_dbell_lpid_match_offset), + din => lsu_xu_dbell_lpid_match , + dout => lsu_xu_dbell_lpid_match_q); +lsu_xu_dbell_pirtag_latch : tri_rlmreg_p + generic map (width => lsu_xu_dbell_pirtag_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => dbell_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(lsu_xu_dbell_pirtag_offset to lsu_xu_dbell_pirtag_offset + lsu_xu_dbell_pirtag_q'length-1), + scout => sov(lsu_xu_dbell_pirtag_offset to lsu_xu_dbell_pirtag_offset + lsu_xu_dbell_pirtag_q'length-1), + din => lsu_xu_dbell_pirtag , + dout => lsu_xu_dbell_pirtag_q); +dbell_present_latch : tri_rlmreg_p + generic map (width => dbell_present_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(dbell_present_offset to dbell_present_offset + dbell_present_q'length-1), + scout => sov(dbell_present_offset to dbell_present_offset + dbell_present_q'length-1), + din => dbell_present_d, + dout => dbell_present_q); +cdbell_present_latch : tri_rlmreg_p + generic map (width => cdbell_present_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(cdbell_present_offset to cdbell_present_offset + cdbell_present_q'length-1), + scout => sov(cdbell_present_offset to cdbell_present_offset + cdbell_present_q'length-1), + din => cdbell_present_d, + dout => cdbell_present_q); +gdbell_present_latch : tri_rlmreg_p + generic map (width => gdbell_present_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(gdbell_present_offset to gdbell_present_offset + gdbell_present_q'length-1), + scout => sov(gdbell_present_offset to gdbell_present_offset + gdbell_present_q'length-1), + din => gdbell_present_d, + dout => gdbell_present_q); +gcdbell_present_latch : tri_rlmreg_p + generic map (width => gcdbell_present_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(gcdbell_present_offset to gcdbell_present_offset + gcdbell_present_q'length-1), + scout => sov(gcdbell_present_offset to gcdbell_present_offset + gcdbell_present_q'length-1), + din => gcdbell_present_d, + dout => gcdbell_present_q); +gmcdbell_present_latch : tri_rlmreg_p + generic map (width => gmcdbell_present_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(gmcdbell_present_offset to gmcdbell_present_offset + gmcdbell_present_q'length-1), + scout => sov(gmcdbell_present_offset to gmcdbell_present_offset + gmcdbell_present_q'length-1), + din => gmcdbell_present_d, + dout => gmcdbell_present_q); +xucr0_clfc_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(xucr0_clfc_offset), + scout => sov(xucr0_clfc_offset), + din => xucr0_clfc_d, + dout => xucr0_clfc_q); +iu_run_thread_latch : tri_rlmreg_p + generic map (width => iu_run_thread_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(iu_run_thread_offset to iu_run_thread_offset + iu_run_thread_q'length-1), + scout => sov(iu_run_thread_offset to iu_run_thread_offset + iu_run_thread_q'length-1), + din => iu_run_thread_d, + dout => iu_run_thread_q); +perf_event_latch : tri_rlmreg_p + generic map (width => perf_event_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(perf_event_offset to perf_event_offset + perf_event_q'length-1), + scout => sov(perf_event_offset to perf_event_offset + perf_event_q'length-1), + din => perf_event_d, + dout => perf_event_q); +inj_sprg_ecc_latch : tri_rlmreg_p + generic map (width => inj_sprg_ecc_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(inj_sprg_ecc_offset to inj_sprg_ecc_offset + inj_sprg_ecc_q'length-1), + scout => sov(inj_sprg_ecc_offset to inj_sprg_ecc_offset + inj_sprg_ecc_q'length-1), + din => pc_xu_inj_sprg_ecc , + dout => inj_sprg_ecc_q); +dbell_interrupt_latch : tri_rlmreg_p + generic map (width => dbell_interrupt_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(dbell_interrupt_offset to dbell_interrupt_offset + dbell_interrupt_q'length-1), + scout => sov(dbell_interrupt_offset to dbell_interrupt_offset + dbell_interrupt_q'length-1), + din => dbell_interrupt, + dout => dbell_interrupt_q); +cdbell_interrupt_latch : tri_rlmreg_p + generic map (width => cdbell_interrupt_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(cdbell_interrupt_offset to cdbell_interrupt_offset + cdbell_interrupt_q'length-1), + scout => sov(cdbell_interrupt_offset to cdbell_interrupt_offset + cdbell_interrupt_q'length-1), + din => cdbell_interrupt, + dout => cdbell_interrupt_q); +gdbell_interrupt_latch : tri_rlmreg_p + generic map (width => gdbell_interrupt_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(gdbell_interrupt_offset to gdbell_interrupt_offset + gdbell_interrupt_q'length-1), + scout => sov(gdbell_interrupt_offset to gdbell_interrupt_offset + gdbell_interrupt_q'length-1), + din => gdbell_interrupt, + dout => gdbell_interrupt_q); +gcdbell_interrupt_latch : tri_rlmreg_p + generic map (width => gcdbell_interrupt_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(gcdbell_interrupt_offset to gcdbell_interrupt_offset + gcdbell_interrupt_q'length-1), + scout => sov(gcdbell_interrupt_offset to gcdbell_interrupt_offset + gcdbell_interrupt_q'length-1), + din => gcdbell_interrupt, + dout => gcdbell_interrupt_q); +gmcdbell_interrupt_latch : tri_rlmreg_p + generic map (width => gmcdbell_interrupt_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(gmcdbell_interrupt_offset to gmcdbell_interrupt_offset + gmcdbell_interrupt_q'length-1), + scout => sov(gmcdbell_interrupt_offset to gmcdbell_interrupt_offset + gmcdbell_interrupt_q'length-1), + din => gmcdbell_interrupt, + dout => gmcdbell_interrupt_q); +iu_quiesce_latch : tri_rlmreg_p + generic map (width => iu_quiesce_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(iu_quiesce_offset to iu_quiesce_offset + iu_quiesce_q'length-1), + scout => sov(iu_quiesce_offset to iu_quiesce_offset + iu_quiesce_q'length-1), + din => iu_xu_quiesce , + dout => iu_quiesce_q); +lsu_quiesce_latch : tri_rlmreg_p + generic map (width => lsu_quiesce_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(lsu_quiesce_offset to lsu_quiesce_offset + lsu_quiesce_q'length-1), + scout => sov(lsu_quiesce_offset to lsu_quiesce_offset + lsu_quiesce_q'length-1), + din => lsu_xu_quiesce , + dout => lsu_quiesce_q); +mm_quiesce_latch : tri_rlmreg_p + generic map (width => mm_quiesce_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(mm_quiesce_offset to mm_quiesce_offset + mm_quiesce_q'length-1), + scout => sov(mm_quiesce_offset to mm_quiesce_offset + mm_quiesce_q'length-1), + din => mm_xu_quiesce , + dout => mm_quiesce_q); +bx_quiesce_latch : tri_rlmreg_p + generic map (width => bx_quiesce_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(bx_quiesce_offset to bx_quiesce_offset + bx_quiesce_q'length-1), + scout => sov(bx_quiesce_offset to bx_quiesce_offset + bx_quiesce_q'length-1), + din => bx_xu_quiesce , + dout => bx_quiesce_q); +quiesce_latch : tri_rlmreg_p + generic map (width => quiesce_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(quiesce_offset to quiesce_offset + quiesce_q'length-1), + scout => sov(quiesce_offset to quiesce_offset + quiesce_q'length-1), + din => quiesce_d, + dout => quiesce_q); +cpl_quiesce_latch : tri_rlmreg_p + generic map (width => cpl_quiesce_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(cpl_quiesce_offset to cpl_quiesce_offset + cpl_quiesce_q'length-1), + scout => sov(cpl_quiesce_offset to cpl_quiesce_offset + cpl_quiesce_q'length-1), + din => cpl_quiesce_d, + dout => cpl_quiesce_q); +quiesced_4cpl_latch : tri_rlmreg_p + generic map (width => quiesced_4cpl_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(quiesced_4cpl_offset to quiesced_4cpl_offset + quiesced_4cpl_q'length-1), + scout => sov(quiesced_4cpl_offset to quiesced_4cpl_offset + quiesced_4cpl_q'length-1), + din => quiesced_4cpl_d, + dout => quiesced_4cpl_q); +quiesced_latch : tri_rlmreg_p + generic map (width => quiesced_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(quiesced_offset to quiesced_offset + quiesced_q'length-1), + scout => sov(quiesced_offset to quiesced_offset + quiesced_q'length-1), + din => quiesced_d, + dout => quiesced_q); +instr_trace_mode_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(instr_trace_mode_offset), + scout => sov(instr_trace_mode_offset), + din => pc_xu_instr_trace_mode , + dout => instr_trace_mode_q); +instr_trace_tid_latch : tri_rlmreg_p + generic map (width => instr_trace_tid_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(instr_trace_tid_offset to instr_trace_tid_offset + instr_trace_tid_q'length-1), + scout => sov(instr_trace_tid_offset to instr_trace_tid_offset + instr_trace_tid_q'length-1), + din => pc_xu_instr_trace_tid , + dout => instr_trace_tid_q); +timer_update_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(timer_update_offset), + scout => sov(timer_update_offset), + din => timer_update_int, + dout => timer_update_q); + +spare_0_lcb: entity tri.tri_lcbnd(tri_lcbnd) + port map(vd => vdd, + gd => gnd, + act => tidn(0), + nclk => nclk, + forcee => func_sl_force, + thold_b => func_sl_thold_0_b, + delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), + mpw2_b => mpw2_dc_b, + sg => sg_0, + lclk => spare_0_lclk, + d1clk => spare_0_d1clk, + d2clk => spare_0_d2clk); +spare_0_latch : entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width => spare_0_q'length, expand_type => expand_type, btr => "NLI0001_X2_A12TH", init=>(spare_0_q'range=>'0')) + port map (vd => vdd, gd => gnd, + LCLK => spare_0_lclk, + D1CLK => spare_0_d1clk, + D2CLK => spare_0_d2clk, + SCANIN => siv(spare_0_offset to spare_0_offset + spare_0_q'length-1), + SCANOUT => sov(spare_0_offset to spare_0_offset + spare_0_q'length-1), + D => spare_0_d, + QB => spare_0_q); +spare_0_d <= not spare_0_q; +mark_unused(spare_0_q); + + +quiesced_fctr : entity work.xuq_cpl_fctr(xuq_cpl_fctr) +generic map (threads => threads, expand_type => expand_type, passthru => 0) +port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(quiesced_ctr_offset), + scout => sov(quiesced_ctr_offset), + delay => "1111", + din => quiesce_b_q, + dout => quiesce_ctr_zero_b); +quiesced_4cpl_fctr : entity work.xuq_cpl_fctr(xuq_cpl_fctr) +generic map (threads => threads, expand_type => expand_type, passthru => 0) +port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(quiesced_4cpl_ctr_offset), + scout => sov(quiesced_4cpl_ctr_offset), + delay => "1111", + din => cpl_quiesce_b_q, + dout => cpl_quiesce_ctr_zero_b); + + +siv( 0 to 399) <= sov( 1 to 399) & scan_in(0); +scan_out(0) <= sov( 0); + +siv(400 to siv'right) <= sov(401 to siv'right) & scan_in(1); +scan_out(1) <= sov(400); + + +bcfg_l : if sov_bcfg'length > 1 generate +siv_bcfg(0 to scan_right_bcfg-1) <= sov_bcfg(1 to scan_right_bcfg-1) & bcfg_scan_in; +bcfg_scan_out <= sov_bcfg(0); +end generate; +bcfg_s : if sov_bcfg'length <= 1 generate +bcfg_scan_out <= bcfg_scan_in; +sov_bcfg <= (others=>'0'); +siv_bcfg <= (others=>'0'); +end generate; + +ccfg_l : if sov_ccfg'length > 1 generate +siv_ccfg(0 to scan_right_ccfg-1) <= sov_ccfg(1 to scan_right_ccfg-1) & ccfg_scan_in; +ccfg_scan_out <= sov_ccfg(0); +end generate; +ccfg_s : if sov_ccfg'length <= 1 generate +ccfg_scan_out <= ccfg_scan_in; +sov_ccfg <= (others=>'0'); +siv_ccfg <= (others=>'0'); +end generate; + + + + +end architecture xuq_spr_cspr; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_spr_dacen.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_spr_dacen.vhdl new file mode 100644 index 0000000..ef5e045 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_spr_dacen.vhdl @@ -0,0 +1,78 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee; +use ieee.std_logic_1164.all; + +entity xuq_spr_dacen is +generic( + threads : integer := 4); +port( + spr_msr_pr : in std_ulogic_vector(0 to threads-1); + spr_msr_ds : in std_ulogic_vector(0 to threads-1); + + spr_dbcr0_dac : in std_ulogic_vector(0 to 2*threads-1); + spr_dbcr_dac_us : in std_ulogic_vector(0 to 2*threads-1); + spr_dbcr_dac_er : in std_ulogic_vector(0 to 2*threads-1); + + val : in std_ulogic_vector(0 to threads-1); + load : in std_ulogic; + store : in std_ulogic; + + dacr_en : out std_ulogic_vector(0 to threads-1); + dacw_en : out std_ulogic_vector(0 to threads-1) +); + +-- synopsys translate_off +-- synopsys translate_on + +end xuq_spr_dacen; +architecture xuq_spr_dacen of xuq_spr_dacen is + +signal dac_ld_en,dac_st_en : std_ulogic_vector(0 to threads-1); +signal dac_us_en,dac_er_en : std_ulogic_vector(0 to threads-1); + +begin + +dacen_gen : for t in 0 to threads-1 generate + + dac_ld_en(t) <= spr_dbcr0_dac(0+2*t) and load; + dac_st_en(t) <= spr_dbcr0_dac(1+2*t) and store; + + dac_us_en(t) <= (not spr_dbcr_dac_us(0+2*t) and not spr_dbcr_dac_us(1+2*t)) or + ( spr_dbcr_dac_us(0+2*t) and (spr_dbcr_dac_us(1+2*t) xnor spr_msr_pr(t))); + + dac_er_en(t) <= (not spr_dbcr_dac_er(0+2*t) and not spr_dbcr_dac_er(1+2*t)) or + ( spr_dbcr_dac_er(0+2*t) and (spr_dbcr_dac_er(1+2*t) xnor spr_msr_ds(t))); + + dacr_en(t) <= val(t) and dac_ld_en(t) and dac_us_en(t) and dac_er_en(t); + dacw_en(t) <= val(t) and dac_st_en(t) and dac_us_en(t) and dac_er_en(t); + +end generate; + +end architecture xuq_spr_dacen; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_spr_dvccmp.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_spr_dvccmp.vhdl new file mode 100644 index 0000000..2b82540 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_spr_dvccmp.vhdl @@ -0,0 +1,82 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee,ibm; +use ieee.std_logic_1164.all; +use ibm.std_ulogic_function_support.all; + +library tri; +use tri.tri_latches_pkg.all; +entity xuq_spr_dvccmp is +generic( + regsize : integer := 64); +port( + en : in std_ulogic; + en00 : in std_ulogic := '1'; + cmp : in std_ulogic_vector(8-regsize/8 to 7); + dvcm : in std_ulogic_vector(0 to 1); + dvcbe : in std_ulogic_vector(8-regsize/8 to 7); + dvc_cmpr : out std_ulogic +); + + +-- synopsys translate_off +-- synopsys translate_on +end xuq_spr_dvccmp; +architecture xuq_spr_dvccmp of xuq_spr_dvccmp is + +signal cmp_mask_or,cmp_mask_and : std_ulogic_vector(8-regsize/8 to 7); +signal cmp_and,cmp_or,cmp_andor : std_ulogic; + +begin + + cmp_mask_or <= gate((cmp or not dvcbe),or_reduce(dvcbe)); + cmp_mask_and <= (cmp and dvcbe); + + cmp_and <= and_reduce(cmp_mask_or); + + cmp_or <= or_reduce(cmp_mask_and); + + cmp_andor_gen32 : if regsize = 32 generate + cmp_andor <= (and_reduce(cmp_mask_or(4 to 5)) and or_reduce(dvcbe(4 to 5))) or + (and_reduce(cmp_mask_or(6 to 7)) and or_reduce(dvcbe(6 to 7))); + end generate; + cmp_andor_gen64 : if regsize = 64 generate + cmp_andor <= (and_reduce(cmp_mask_or(0 to 1)) and or_reduce(dvcbe(0 to 1))) or + (and_reduce(cmp_mask_or(2 to 3)) and or_reduce(dvcbe(2 to 3))) or + (and_reduce(cmp_mask_or(4 to 5)) and or_reduce(dvcbe(4 to 5))) or + (and_reduce(cmp_mask_or(6 to 7)) and or_reduce(dvcbe(6 to 7))); + end generate; + + with dvcm(0 to 1) select + dvc_cmpr <= en and en00 when "00", + en and cmp_and when "01", + en and cmp_or when "10", + en and cmp_andor when others; + +end architecture xuq_spr_dvccmp; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_spr_tspr.vhdl b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_spr_tspr.vhdl new file mode 100644 index 0000000..f518d8d --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/src/work/xuq_spr_tspr.vhdl @@ -0,0 +1,4259 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee,ibm,support,work,tri; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use support.power_logic_pkg.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use tri.tri_latches_pkg.all; +use work.xuq_pkg.all; + +entity xuq_spr_tspr is +generic( + hvmode : integer := 1; + a2mode : integer := 1; + expand_type : integer := 2; + regsize : integer := 64; + eff_ifar : integer := 62); +port( + nclk : in clk_logic; + + an_ac_ext_interrupt : in std_ulogic; + an_ac_crit_interrupt : in std_ulogic; + an_ac_perf_interrupt : in std_ulogic; + an_ac_hang_pulse : in std_ulogic; + ac_tc_machine_check : out std_ulogic; + an_ac_external_mchk : in std_ulogic; + instr_trace_mode : in std_ulogic; + + d_mode_dc : in std_ulogic; + delay_lclkr_dc : in std_ulogic_vector(0 to 0); + mpw1_dc_b : in std_ulogic_vector(0 to 0); + mpw2_dc_b : in std_ulogic; + ccfg_sl_force : in std_ulogic; + ccfg_sl_thold_0_b : in std_ulogic; + dcfg_sl_force : in std_ulogic; + dcfg_sl_thold_0_b : in std_ulogic; + func_sl_force : in std_ulogic; + func_sl_thold_0_b : in std_ulogic; + func_slp_sl_force : in std_ulogic; + func_slp_sl_thold_0_b : in std_ulogic; + func_nsl_force : in std_ulogic; + func_nsl_thold_0_b : in std_ulogic; + sg_0 : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + ccfg_scan_in : in std_ulogic; + ccfg_scan_out : out std_ulogic; + dcfg_scan_in : in std_ulogic; + dcfg_scan_out : out std_ulogic; + + cspr_tspr_rf1_act : in std_ulogic; + + cspr_tspr_ex1_instr : in std_ulogic_vector(0 to 31); + cspr_tspr_ex2_tid : in std_ulogic; + tspr_cspr_ex3_tspr_rt : out std_ulogic_vector(64-regsize to 63); + + dec_spr_ex4_val : in std_ulogic; + cspr_tspr_ex5_is_mtmsr : in std_ulogic; + cspr_tspr_ex5_is_mtspr : in std_ulogic; + cspr_tspr_ex5_is_wrtee : in std_ulogic; + cspr_tspr_ex5_is_wrteei : in std_ulogic; + cspr_tspr_ex5_instr : in std_ulogic_vector(11 to 20); + ex5_spr_wd : in std_ulogic_vector(64-regsize to 63); + + cspr_tspr_dec_dbg_dis : in std_ulogic; + + dec_spr_ex1_epid_instr : in std_ulogic; + fxu_spr_ex1_rs2 : in std_ulogic_vector(42 to 55); + spr_cpl_ex3_ct_be : out std_ulogic; + spr_cpl_ex3_ct_le : out std_ulogic; + + tspr_cspr_illeg_mtspr_b : out std_ulogic; + tspr_cspr_illeg_mfspr_b : out std_ulogic; + tspr_cspr_hypv_mtspr : out std_ulogic; + tspr_cspr_hypv_mfspr : out std_ulogic; + + cpl_spr_ex5_act : in std_ulogic; + cpl_spr_ex5_int : in std_ulogic; + cpl_spr_ex5_gint : in std_ulogic; + cpl_spr_ex5_cint : in std_ulogic; + cpl_spr_ex5_mcint : in std_ulogic; + cpl_spr_ex5_nia : in std_ulogic_vector(62-eff_ifar to 61); + cpl_spr_ex5_esr : in std_ulogic_vector(0 to 16); + cpl_spr_ex5_mcsr : in std_ulogic_vector(0 to 14); + cpl_spr_ex5_dbsr : in std_ulogic_vector(0 to 18); + cpl_spr_ex5_dear_save : in std_ulogic; + cpl_spr_ex5_dear_update : in std_ulogic; + cpl_spr_ex5_dear_update_saved : in std_ulogic; + cpl_spr_ex5_dbsr_update : in std_ulogic; + cpl_spr_ex5_esr_update : in std_ulogic; + cpl_spr_ex5_srr0_dec : in std_ulogic; + cpl_spr_ex5_force_gsrr : in std_ulogic; + cpl_spr_ex5_dbsr_ide : in std_ulogic; + spr_cpl_dbsr_ide : out std_ulogic; + + spr_cpl_external_mchk : out std_ulogic; + spr_cpl_ext_interrupt : out std_ulogic; + spr_cpl_dec_interrupt : out std_ulogic; + spr_cpl_udec_interrupt : out std_ulogic; + spr_cpl_perf_interrupt : out std_ulogic; + spr_cpl_fit_interrupt : out std_ulogic; + spr_cpl_crit_interrupt : out std_ulogic; + spr_cpl_wdog_interrupt : out std_ulogic; + + cspr_tspr_crit_mask : in std_ulogic; + cspr_tspr_wdog_mask : in std_ulogic; + cspr_tspr_dec_mask : in std_ulogic; + cspr_tspr_udec_mask : in std_ulogic; + cspr_tspr_perf_mask : in std_ulogic; + cspr_tspr_fit_mask : in std_ulogic; + cspr_tspr_ext_mask : in std_ulogic; + + tspr_cspr_pm_wake_up : out std_ulogic; + tspr_cspr_async_int : out std_ulogic_vector(0 to 2); + + cspr_tspr_dbell_pirtag : in std_ulogic_vector(50 to 63); + tspr_cspr_gpir_match : out std_ulogic; + + cspr_tspr_timebase_taps : in std_ulogic_vector(0 to 9); + timer_update : in std_ulogic; + + spr_cpl_iac1_en : out std_ulogic; + spr_cpl_iac2_en : out std_ulogic; + spr_cpl_iac3_en : out std_ulogic; + spr_cpl_iac4_en : out std_ulogic; + tspr_cspr_freeze_timers : out std_ulogic; + + xu_ex4_flush : in std_ulogic; + xu_ex5_flush : in std_ulogic; + + xu_iu_single_instr_mode : out std_ulogic; + xu_iu_raise_iss_pri : out std_ulogic; + + cpl_spr_ex5_instr_cpl : in std_ulogic; + cspr_tspr_llen : in std_ulogic; + cspr_tspr_llpri : in std_ulogic; + tspr_cspr_lldet : out std_ulogic; + tspr_cspr_llpulse : out std_ulogic; + xu_pc_err_llbust_attempt : out std_ulogic; + xu_pc_err_llbust_failed : out std_ulogic; + pc_xu_inj_llbust_attempt : in std_ulogic; + pc_xu_inj_llbust_failed : in std_ulogic; + + pc_xu_inj_wdt_reset : in std_ulogic; + reset_wd_complete : in std_ulogic; + reset_1_complete : in std_ulogic; + reset_2_complete : in std_ulogic; + reset_3_complete : in std_ulogic; + reset_1_request : out std_ulogic; + reset_2_request : out std_ulogic; + reset_3_request : out std_ulogic; + reset_wd_request : out std_ulogic; + xu_pc_err_wdt_reset : out std_ulogic; + + spr_byp_ex4_is_mtxer : out std_ulogic; + spr_byp_ex4_is_mfxer : out std_ulogic; + + cspr_tspr_ram_mode : in std_ulogic; + cspr_tspr_msrovride_en : in std_ulogic; + pc_xu_msrovride_pr : in std_ulogic; + pc_xu_msrovride_gs : in std_ulogic; + pc_xu_msrovride_de : in std_ulogic; + + cpl_spr_dbcr0_edm : in std_ulogic; + lsu_xu_spr_epsc_egs : in std_ulogic; + lsu_xu_spr_epsc_epr : in std_ulogic; + tspr_msr_de : out std_ulogic; + tspr_msr_cm : out std_ulogic; + tspr_msr_pr : out std_ulogic; + tspr_msr_is : out std_ulogic; + tspr_msr_gs : out std_ulogic; + tspr_msr_ee : out std_ulogic; + tspr_msr_ce : out std_ulogic; + tspr_msr_me : out std_ulogic; + tspr_fp_precise : out std_ulogic; + tspr_epcr_extgs : out std_ulogic; + cspr_xucr0_clkg_ctl : in std_ulogic_vector(4 to 4); + spr_dbcr0_idm : out std_ulogic; + spr_dbcr0_icmp : out std_ulogic; + spr_dbcr0_brt : out std_ulogic; + spr_dbcr0_irpt : out std_ulogic; + spr_dbcr0_trap : out std_ulogic; + spr_dbcr0_dac1 : out std_ulogic_vector(0 to 1); + spr_dbcr0_dac2 : out std_ulogic_vector(0 to 1); + spr_dbcr0_ret : out std_ulogic; + spr_dbcr0_dac3 : out std_ulogic_vector(0 to 1); + spr_dbcr0_dac4 : out std_ulogic_vector(0 to 1); + spr_dbcr1_iac12m : out std_ulogic; + spr_dbcr1_iac34m : out std_ulogic; + spr_epcr_dtlbgs : out std_ulogic; + spr_epcr_itlbgs : out std_ulogic; + spr_epcr_dsigs : out std_ulogic; + spr_epcr_isigs : out std_ulogic; + spr_epcr_duvd : out std_ulogic; + spr_epcr_dgtmi : out std_ulogic; + xu_mm_spr_epcr_dmiuh : out std_ulogic; + spr_msr_ucle : out std_ulogic; + spr_msr_spv : out std_ulogic; + spr_msr_fp : out std_ulogic; + spr_msr_ds : out std_ulogic; + spr_msrp_uclep : out std_ulogic; + + tspr_debug : out std_ulogic_vector(0 to 11); + + vdd : inout power_logic; + gnd : inout power_logic +); + +-- synopsys translate_off + +-- synopsys translate_on +end xuq_spr_tspr; +architecture xuq_spr_tspr of xuq_spr_tspr is + +constant DEX2 : natural := 0; +constant DEX3 : natural := 0; +constant DEX4 : natural := 0; +constant DEX5 : natural := 0; +constant DEX6 : natural := 0; +constant DWR : natural := 0; +constant DX : natural := 0; +subtype s2 is std_ulogic_vector(0 to 1); +subtype s3 is std_ulogic_vector(0 to 2); +subtype s4 is std_ulogic_vector(0 to 3); +subtype s5 is std_ulogic_vector(0 to 4); +subtype DO is std_ulogic_vector(65-regsize to 64); +constant MSR_CM : natural := 50; +constant MSR_GS : natural := 51; +constant MSR_UCLE : natural := 52; +constant MSR_SPV : natural := 53; +constant MSR_CE : natural := 54; +constant MSR_EE : natural := 55; +constant MSR_PR : natural := 56; +constant MSR_FP : natural := 57; +constant MSR_ME : natural := 58; +constant MSR_FE0 : natural := 59; +constant MSR_DE : natural := 60; +constant MSR_FE1 : natural := 61; +constant MSR_IS : natural := 62; +constant MSR_DS : natural := 63; +constant MSRP_UCLEP : natural := 62; +constant MSRP_DEP : natural := 63; +signal acop_d , acop_q : std_ulogic_vector(32 to 63); +signal ccr3_d , ccr3_q : std_ulogic_vector(62 to 63); +signal csrr0_d , csrr0_q : std_ulogic_vector(64-(eff_ifar) to 63); +signal csrr1_d , csrr1_q : std_ulogic_vector(50 to 63); +signal dbcr0_d , dbcr0_q : std_ulogic_vector(43 to 63); +signal dbcr1_d , dbcr1_q : std_ulogic_vector(46 to 63); +signal dbsr_d , dbsr_q : std_ulogic_vector(44 to 63); +signal dear_d , dear_q : std_ulogic_vector(64-(regsize) to 63); +signal dec_d , dec_q : std_ulogic_vector(32 to 63); +signal decar_d , decar_q : std_ulogic_vector(32 to 63); +signal epcr_d , epcr_q : std_ulogic_vector(54 to 63); +signal esr_d , esr_q : std_ulogic_vector(47 to 63); +signal gdear_d , gdear_q : std_ulogic_vector(64-(regsize) to 63); +signal gesr_d , gesr_q : std_ulogic_vector(47 to 63); +signal gpir_d , gpir_q : std_ulogic_vector(32 to 63); +signal gsrr0_d , gsrr0_q : std_ulogic_vector(64-(eff_ifar) to 63); +signal gsrr1_d , gsrr1_q : std_ulogic_vector(50 to 63); +signal hacop_d , hacop_q : std_ulogic_vector(32 to 63); +signal mcsr_d , mcsr_q : std_ulogic_vector(49 to 63); +signal mcsrr0_d , mcsrr0_q : std_ulogic_vector(64-(eff_ifar) to 63); +signal mcsrr1_d , mcsrr1_q : std_ulogic_vector(50 to 63); +signal msr_d , msr_q : std_ulogic_vector(50 to 63); +signal msrp_d , msrp_q : std_ulogic_vector(62 to 63); +signal srr0_d , srr0_q : std_ulogic_vector(64-(eff_ifar) to 63); +signal srr1_d , srr1_q : std_ulogic_vector(50 to 63); +signal tcr_d , tcr_q : std_ulogic_vector(52 to 63); +signal tsr_d , tsr_q : std_ulogic_vector(59 to 63); +signal udec_d , udec_q : std_ulogic_vector(32 to 63); +signal xucr1_d , xucr1_q : std_ulogic_vector(59 to 63); +constant acop_offset : natural := 0; +constant csrr0_offset : natural := acop_offset + acop_q'length*a2mode; +constant csrr1_offset : natural := csrr0_offset + csrr0_q'length*a2mode; +constant dbcr1_offset : natural := csrr1_offset + csrr1_q'length*a2mode; +constant dbsr_offset : natural := dbcr1_offset + dbcr1_q'length; +constant dear_offset : natural := dbsr_offset + dbsr_q'length; +constant dec_offset : natural := dear_offset + dear_q'length; +constant decar_offset : natural := dec_offset + dec_q'length; +constant epcr_offset : natural := decar_offset + decar_q'length*a2mode; +constant esr_offset : natural := epcr_offset + epcr_q'length*hvmode; +constant gdear_offset : natural := esr_offset + esr_q'length; +constant gesr_offset : natural := gdear_offset + gdear_q'length*hvmode; +constant gpir_offset : natural := gesr_offset + gesr_q'length*hvmode; +constant gsrr0_offset : natural := gpir_offset + gpir_q'length*hvmode; +constant gsrr1_offset : natural := gsrr0_offset + gsrr0_q'length*hvmode; +constant hacop_offset : natural := gsrr1_offset + gsrr1_q'length*hvmode; +constant mcsr_offset : natural := hacop_offset + hacop_q'length*hvmode; +constant mcsrr0_offset : natural := mcsr_offset + mcsr_q'length*a2mode; +constant mcsrr1_offset : natural := mcsrr0_offset + mcsrr0_q'length*a2mode; +constant msrp_offset : natural := mcsrr1_offset + mcsrr1_q'length*a2mode; +constant srr0_offset : natural := msrp_offset + msrp_q'length*hvmode; +constant srr1_offset : natural := srr0_offset + srr0_q'length; +constant tcr_offset : natural := srr1_offset + srr1_q'length; +constant tsr_offset : natural := tcr_offset + tcr_q'length*a2mode; +constant udec_offset : natural := tsr_offset + tsr_q'length*a2mode; +constant last_reg_offset : natural := udec_offset + udec_q'length*a2mode; +constant last_reg_offset_bcfg : natural := 1; +constant ccr3_offset_ccfg : natural := 0; +constant msr_offset_ccfg : natural := ccr3_offset_ccfg + ccr3_q'length; +constant xucr1_offset_ccfg : natural := msr_offset_ccfg + msr_q'length; +constant last_reg_offset_ccfg : natural := xucr1_offset_ccfg + xucr1_q'length; +constant dbcr0_offset_dcfg : natural := 0; +constant last_reg_offset_dcfg : natural := dbcr0_offset_dcfg + dbcr0_q'length; +signal exx_act_q, exx_act_d : std_ulogic_vector(1 to 5); +signal ex2_is_mfspr_q, ex1_is_mfspr : std_ulogic; +signal ex2_is_mtspr_q, ex1_is_mtspr : std_ulogic; +signal ex2_is_mfmsr_q, ex1_is_mfmsr : std_ulogic; +signal ex2_instr_q, ex2_instr_d : std_ulogic_vector(11 to 20); +signal ex3_is_mtxer_q, ex3_is_mtxer_d : std_ulogic; +signal ex3_is_mfxer_q, ex3_is_mfxer_d : std_ulogic; +signal ex2_rfi_q, ex2_rfi_d : std_ulogic; +signal ex2_rfgi_q, ex2_rfgi_d : std_ulogic; +signal ex2_rfci_q, ex1_is_rfci : std_ulogic; +signal ex2_rfmci_q, ex1_is_rfmci : std_ulogic; +signal ex3_rfi_q : std_ulogic; +signal ex3_rfgi_q : std_ulogic; +signal ex3_rfci_q : std_ulogic; +signal ex3_rfmci_q : std_ulogic; +signal ex4_is_mfxer_q : std_ulogic; +signal ex4_is_mtxer_q : std_ulogic; +signal ex4_rfi_q : std_ulogic; +signal ex4_rfgi_q : std_ulogic; +signal ex4_rfci_q : std_ulogic; +signal ex4_rfmci_q : std_ulogic; +signal ex5_val_q, ex4_val : std_ulogic; +signal ex5_rfi_q : std_ulogic; +signal ex5_rfgi_q : std_ulogic; +signal ex5_rfci_q : std_ulogic; +signal ex5_rfmci_q : std_ulogic; +signal ex6_val_q, ex5_val : std_ulogic; +signal ex6_rfi_q : std_ulogic; +signal ex6_rfgi_q : std_ulogic; +signal ex6_rfci_q : std_ulogic; +signal ex6_rfmci_q : std_ulogic; +signal ex6_wrtee_q : std_ulogic; +signal ex6_wrteei_q : std_ulogic; +signal ex6_is_mtmsr_q : std_ulogic; +signal ex6_is_mtspr_q : std_ulogic; +signal ex6_instr_q : std_ulogic_vector(11 to 20); +signal ex6_int_q : std_ulogic; +signal ex6_gint_q : std_ulogic; +signal ex6_cint_q : std_ulogic; +signal ex6_mcint_q : std_ulogic; +signal ex6_nia_q : std_ulogic_vector(62-eff_ifar to 61); +signal ex6_esr_q : std_ulogic_vector(0 to 16); +signal ex6_mcsr_q : std_ulogic_vector(0 to 14); +signal ex6_dbsr_q : std_ulogic_vector(0 to 18); +signal ex6_dear_save_q : std_ulogic; +signal ex6_dear_update_q : std_ulogic; +signal ex6_dear_update_saved_q : std_ulogic; +signal ex6_dbsr_update_q : std_ulogic; +signal ex6_esr_update_q : std_ulogic; +signal ex6_srr0_dec_q : std_ulogic; +signal ex6_force_gsrr_q : std_ulogic; +signal ex6_dbsr_ide_q : std_ulogic; +signal ex6_spr_wd_q : std_ulogic_vector(64-regsize to 63); +signal fit_tb_tap_q, fit_tb_tap_d : std_ulogic; +signal wdog_tb_tap_q, wdog_tb_tap_d : std_ulogic; +signal hang_pulse_q, hang_pulse_d : std_ulogic_vector(0 to 3); +signal lltap_q, lltap_d : std_ulogic; +signal llcnt_q, llcnt_d : std_ulogic_vector(0 to 1); +signal msrovride_pr_q : std_ulogic; +signal msrovride_gs_q : std_ulogic; +signal msrovride_de_q : std_ulogic; +signal an_ac_ext_interrupt_q : std_ulogic; +signal an_ac_crit_interrupt_q : std_ulogic; +signal an_ac_perf_interrupt_q : std_ulogic; +signal dear_tmp_q, dear_tmp_d : std_ulogic_vector(dear_q'range); +signal mux_msr_gs_q, mux_msr_gs_d : std_ulogic_vector(0 to 3); +signal mux_msr_pr_q, mux_msr_pr_d : std_ulogic_vector(0 to 0); +signal ex3_tspr_rt_q, ex3_tspr_rt_d : std_ulogic_vector(64-regsize to 63); +signal err_llbust_attempt_q, err_llbust_attempt_d : std_ulogic; +signal err_llbust_failed_q, err_llbust_failed_d : std_ulogic; +signal inj_llbust_attempt_q : std_ulogic; +signal inj_llbust_failed_q : std_ulogic; +signal ex2_rs2_q : std_ulogic_vector(42 to 55); +signal ex3_ct_q, ex3_ct_d : std_ulogic_vector(0 to 1); +signal an_ac_external_mchk_q : std_ulogic; +signal mchk_int_q, mchk_int : std_ulogic; +signal mchk_interrupt_q, mchk_interrupt : std_ulogic; +signal crit_interrupt_q, crit_interrupt : std_ulogic; +signal wdog_interrupt_q, wdog_interrupt : std_ulogic; +signal dec_interrupt_q, dec_interrupt : std_ulogic; +signal udec_interrupt_q, udec_interrupt : std_ulogic; +signal perf_interrupt_q, perf_interrupt : std_ulogic; +signal fit_interrupt_q, fit_interrupt : std_ulogic; +signal ext_interrupt_q, ext_interrupt : std_ulogic; +signal single_instr_mode_q, single_instr_mode_d : std_ulogic; +signal single_instr_mode_2_q : std_ulogic; +signal machine_check_q, machine_check_d : std_ulogic; +signal raise_iss_pri_q, raise_iss_pri_d : std_ulogic; +signal raise_iss_pri_2_q : std_ulogic; +signal epsc_egs_q : std_ulogic; +signal epsc_epr_q : std_ulogic; +signal ex2_epid_instr_q : std_ulogic; +signal pc_xu_inj_wdt_reset_q : std_ulogic; +signal err_wdt_reset_q, err_wdt_reset_d : std_ulogic; +signal ex3_tid_rpwr_q, ex3_tid_rpwr_d : std_ulogic_vector(0 to regsize/8-1); +signal ram_mode_q : std_ulogic; +signal timebase_taps_q : std_ulogic_vector(cspr_tspr_timebase_taps'range); +signal dbsr_mrr_q, dbsr_mrr_d : std_ulogic_vector(0 to 1); +signal tsr_wrs_q, tsr_wrs_d : std_ulogic_vector(0 to 1); +signal iac1_en_q, iac1_en_d : std_ulogic; +signal iac2_en_q, iac2_en_d : std_ulogic; +signal iac3_en_q, iac3_en_d : std_ulogic; +signal iac4_en_q, iac4_en_d : std_ulogic; +signal spare_0_q, spare_0_d : std_ulogic_vector(0 to 13); +constant exx_act_offset : integer := last_reg_offset; +constant ex3_is_mtxer_offset : integer := exx_act_offset + exx_act_q'length; +constant ex3_is_mfxer_offset : integer := ex3_is_mtxer_offset + 1; +constant ex3_rfi_offset : integer := ex3_is_mfxer_offset + 1; +constant ex3_rfgi_offset : integer := ex3_rfi_offset + 1; +constant ex3_rfci_offset : integer := ex3_rfgi_offset + 1; +constant ex3_rfmci_offset : integer := ex3_rfci_offset + 1; +constant ex5_val_offset : integer := ex3_rfmci_offset + 1; +constant ex5_rfi_offset : integer := ex5_val_offset + 1; +constant ex5_rfgi_offset : integer := ex5_rfi_offset + 1; +constant ex5_rfci_offset : integer := ex5_rfgi_offset + 1; +constant ex5_rfmci_offset : integer := ex5_rfci_offset + 1; +constant ex6_val_offset : integer := ex5_rfmci_offset + 1; +constant fit_tb_tap_offset : integer := ex6_val_offset + 1; +constant wdog_tb_tap_offset : integer := fit_tb_tap_offset + 1; +constant hang_pulse_offset : integer := wdog_tb_tap_offset + 1; +constant lltap_offset : integer := hang_pulse_offset + hang_pulse_q'length; +constant llcnt_offset : integer := lltap_offset + 1; +constant msrovride_pr_offset : integer := llcnt_offset + llcnt_q'length; +constant msrovride_gs_offset : integer := msrovride_pr_offset + 1; +constant msrovride_de_offset : integer := msrovride_gs_offset + 1; +constant an_ac_ext_interrupt_offset : integer := msrovride_de_offset + 1; +constant an_ac_crit_interrupt_offset : integer := an_ac_ext_interrupt_offset + 1; +constant an_ac_perf_interrupt_offset : integer := an_ac_crit_interrupt_offset + 1; +constant dear_tmp_offset : integer := an_ac_perf_interrupt_offset + 1; +constant mux_msr_gs_offset : integer := dear_tmp_offset + dear_tmp_q'length; +constant mux_msr_pr_offset : integer := mux_msr_gs_offset + mux_msr_gs_q'length; +constant ex3_tspr_rt_offset : integer := mux_msr_pr_offset + mux_msr_pr_q'length; +constant err_llbust_attempt_offset : integer := ex3_tspr_rt_offset + ex3_tspr_rt_q'length; +constant err_llbust_failed_offset : integer := err_llbust_attempt_offset + 1; +constant inj_llbust_attempt_offset : integer := err_llbust_failed_offset + 1; +constant inj_llbust_failed_offset : integer := inj_llbust_attempt_offset + 1; +constant ex3_ct_offset : integer := inj_llbust_failed_offset + 1; +constant an_ac_external_mchk_offset : integer := ex3_ct_offset + ex3_ct_q'length; +constant mchk_int_offset : integer := an_ac_external_mchk_offset + 1; +constant mchk_interrupt_offset : integer := mchk_int_offset + 1; +constant crit_interrupt_offset : integer := mchk_interrupt_offset + 1; +constant wdog_interrupt_offset : integer := crit_interrupt_offset + 1; +constant dec_interrupt_offset : integer := wdog_interrupt_offset + 1; +constant udec_interrupt_offset : integer := dec_interrupt_offset + 1; +constant perf_interrupt_offset : integer := udec_interrupt_offset + 1; +constant fit_interrupt_offset : integer := perf_interrupt_offset + 1; +constant ext_interrupt_offset : integer := fit_interrupt_offset + 1; +constant single_instr_mode_offset : integer := ext_interrupt_offset + 1; +constant single_instr_mode_2_offset : integer := single_instr_mode_offset + 1; +constant machine_check_offset : integer := single_instr_mode_2_offset + 1; +constant raise_iss_pri_offset : integer := machine_check_offset + 1; +constant raise_iss_pri_2_offset : integer := raise_iss_pri_offset + 1; +constant epsc_egs_offset : integer := raise_iss_pri_2_offset + 1; +constant epsc_epr_offset : integer := epsc_egs_offset + 1; +constant pc_xu_inj_wdt_reset_offset : integer := epsc_epr_offset + 1; +constant err_wdt_reset_offset : integer := pc_xu_inj_wdt_reset_offset + 1; +constant ex3_tid_rpwr_offset : integer := err_wdt_reset_offset + 1; +constant ram_mode_offset : integer := ex3_tid_rpwr_offset + ex3_tid_rpwr_q'length; +constant timebase_taps_offset : integer := ram_mode_offset + 1; +constant dbsr_mrr_offset : integer := timebase_taps_offset + timebase_taps_q'length; +constant tsr_wrs_offset : integer := dbsr_mrr_offset + dbsr_mrr_q'length; +constant iac1_en_offset : integer := tsr_wrs_offset + tsr_wrs_q'length; +constant iac2_en_offset : integer := iac1_en_offset + 1; +constant iac3_en_offset : integer := iac2_en_offset + 1; +constant iac4_en_offset : integer := iac3_en_offset + 1; +constant spare_0_offset : integer := iac4_en_offset + 1; +constant scan_right : integer := spare_0_offset + spare_0_q'length; +signal siv : std_ulogic_vector(0 to scan_right-1); +signal sov : std_ulogic_vector(0 to scan_right-1); +constant scan_right_ccfg : integer := last_reg_offset_ccfg; +signal siv_ccfg : std_ulogic_vector(0 to scan_right_ccfg-1); +signal sov_ccfg : std_ulogic_vector(0 to scan_right_ccfg-1); +constant scan_right_dcfg : integer := last_reg_offset_dcfg; +signal siv_dcfg : std_ulogic_vector(0 to scan_right_dcfg-1); +signal sov_dcfg : std_ulogic_vector(0 to scan_right_dcfg-1); +signal tiup : std_ulogic; +signal tidn : std_ulogic_vector(00 to 63); +signal spare_0_lclk : clk_logic; +signal spare_0_d1clk, spare_0_d2clk : std_ulogic; +signal ex1_opcode_is_31 : boolean; +signal ex1_opcode_is_19 : boolean; +signal ex1_is_rfi, ex1_is_rfgi : std_ulogic; +signal ex2_is_mfmsr : std_ulogic; +signal ex2_is_mfspr : std_ulogic; +signal ex2_is_mtspr : std_ulogic; +signal ex2_instr : std_ulogic_vector(11 to 20); +signal ex6_val : std_ulogic; +signal ex6_is_mtmsr : std_ulogic; +signal ex6_is_mtspr : std_ulogic; +signal ex6_instr : std_ulogic_vector(11 to 20); +signal ex6_any_int, ex6_any_hint : std_ulogic; +signal ex6_msr_di2 : std_ulogic_vector(msr_q'range); +signal ex6_msr_mask : std_ulogic_vector(msr_q'range); +signal ex6_msr_mux : std_ulogic_vector(msr_q'range); +signal ex6_msr_in : std_ulogic_vector(msr_q'range); +signal ex6_csrr1_d,ex6_mcsrr1_d : std_ulogic_vector(msr_q'range); +signal ex6_gsrr1_d,ex6_srr1_d : std_ulogic_vector(msr_q'range); +signal ex6_rfgi_msr : std_ulogic_vector(msr_q'range); +signal ex6_nia_srr0 : std_ulogic_vector(srr0_q'range); +signal ex6_nia_srr0_dec : std_ulogic_vector(srr0_q'range); +signal ex6_dec_zero,ex6_dec_upper_zero : std_ulogic; +signal ex6_udec_zero,ex6_udec_upper_zero : std_ulogic; +signal ex6_set_tsr_udis : std_ulogic; +signal ex6_set_tsr_dis : std_ulogic; +signal ex6_set_tsr_fis : std_ulogic; +signal ex6_set_tsr_wis : std_ulogic; +signal ex6_set_tsr_enw : std_ulogic; +signal ex6_set_tsr : std_ulogic_vector(tsr_q'range); +signal ex6_spr_wd : std_ulogic_vector(64-regsize to 63); +signal wdog_pulse : std_ulogic; +signal lltbtap, llpulse, llreset : std_ulogic; +signal llstate : std_ulogic_vector(0 to 1); +signal set_dbsr_ide : std_ulogic; +signal set_dbsr : std_ulogic_vector(dbsr_q'range); +signal dec_running, udec_running : std_ulogic; +signal dbcr0_freeze_timers : std_ulogic; +signal dbsr_event : std_ulogic; +signal mux_msr_gs, mux_msr_pr : std_ulogic; +signal mux_msr_de : std_ulogic; +signal hang_pulse : std_ulogic; +signal dear_di : std_ulogic_vector(dear_q'range); +signal ex2_srr0_re2, ex2_gsrr0_re2 : std_ulogic; +signal ex2_csrr0_re2, ex2_mcsrr0_re2 : std_ulogic; +signal ex2_icswx_gs, ex2_icswx_pr : std_ulogic; +signal ex2_acop_ct, ex2_cop_ct : std_ulogic_vector(32 to 63); +signal iac_us_en, iac_er_en : std_ulogic_vector(1 to 4); +signal udec_en : std_ulogic; +signal ex2_ct : std_ulogic_vector(0 to 1); +signal ex6_rfi, ex6_rfgi : std_ulogic; +signal ex6_rfci, ex6_rfmci : std_ulogic; +signal ex6_wrteei, ex6_wrtee : std_ulogic; +signal reset_complete : std_ulogic_vector(0 to 1); +signal wdog_reset_1 : std_ulogic; +signal wdog_reset_2 : std_ulogic; +signal wdog_reset_3 : std_ulogic; +signal tb_tap_edge : std_ulogic_vector(cspr_tspr_timebase_taps'range); +signal exx_act, exx_act_data : std_ulogic_vector(1 to 5); +signal ex5_int_act : std_ulogic; +signal ex1_is_wrteei : std_ulogic; +signal dbsr_mrr_act, tsr_wrs_act : std_ulogic; +signal reset_complete_act : std_ulogic; +signal ex6_gint_nia_sel : std_ulogic; +signal fp_precise : std_ulogic; +signal dbsr_di : std_ulogic_vector(dbsr_q'range); + +signal spr_acop_ct : std_ulogic_vector(0 to 31); +signal spr_ccr3_en_eepri : std_ulogic; +signal spr_ccr3_si : std_ulogic; +signal spr_dbcr0_rst : std_ulogic_vector(0 to 1); +signal spr_dbcr0_iac1 : std_ulogic; +signal spr_dbcr0_iac2 : std_ulogic; +signal spr_dbcr0_iac3 : std_ulogic; +signal spr_dbcr0_iac4 : std_ulogic; +signal spr_dbcr0_ft : std_ulogic; +signal spr_dbcr1_iac1us : std_ulogic_vector(0 to 1); +signal spr_dbcr1_iac1er : std_ulogic_vector(0 to 1); +signal spr_dbcr1_iac2us : std_ulogic_vector(0 to 1); +signal spr_dbcr1_iac2er : std_ulogic_vector(0 to 1); +signal spr_dbcr1_iac3us : std_ulogic_vector(0 to 1); +signal spr_dbcr1_iac3er : std_ulogic_vector(0 to 1); +signal spr_dbcr1_iac4us : std_ulogic_vector(0 to 1); +signal spr_dbcr1_iac4er : std_ulogic_vector(0 to 1); +signal spr_dbsr_ide : std_ulogic; +signal spr_epcr_extgs : std_ulogic; +signal spr_epcr_icm : std_ulogic; +signal spr_epcr_gicm : std_ulogic; +signal spr_hacop_ct : std_ulogic_vector(0 to 31); +signal spr_msr_cm : std_ulogic; +signal spr_msr_gs : std_ulogic; +signal spr_msr_ce : std_ulogic; +signal spr_msr_ee : std_ulogic; +signal spr_msr_pr : std_ulogic; +signal spr_msr_me : std_ulogic; +signal spr_msr_fe0 : std_ulogic; +signal spr_msr_de : std_ulogic; +signal spr_msr_fe1 : std_ulogic; +signal spr_msr_is : std_ulogic; +signal spr_tcr_wp : std_ulogic_vector(0 to 1); +signal spr_tcr_wrc : std_ulogic_vector(0 to 1); +signal spr_tcr_wie : std_ulogic; +signal spr_tcr_die : std_ulogic; +signal spr_tcr_fp : std_ulogic_vector(0 to 1); +signal spr_tcr_fie : std_ulogic; +signal spr_tcr_are : std_ulogic; +signal spr_tcr_udie : std_ulogic; +signal spr_tcr_ud : std_ulogic; +signal spr_tsr_enw : std_ulogic; +signal spr_tsr_wis : std_ulogic; +signal spr_tsr_dis : std_ulogic; +signal spr_tsr_fis : std_ulogic; +signal spr_tsr_udis : std_ulogic; +signal spr_xucr1_ll_tb_sel : std_ulogic_vector(0 to 2); +signal spr_xucr1_ll_sel : std_ulogic; +signal spr_xucr1_ll_en : std_ulogic; +signal ex6_acop_di : std_ulogic_vector(acop_q'range); +signal ex6_ccr3_di : std_ulogic_vector(ccr3_q'range); +signal ex6_csrr0_di : std_ulogic_vector(csrr0_q'range); +signal ex6_csrr1_di : std_ulogic_vector(csrr1_q'range); +signal ex6_dbcr0_di : std_ulogic_vector(dbcr0_q'range); +signal ex6_dbcr1_di : std_ulogic_vector(dbcr1_q'range); +signal ex6_dbsr_di : std_ulogic_vector(dbsr_q'range); +signal ex6_dear_di : std_ulogic_vector(dear_q'range); +signal ex6_dec_di : std_ulogic_vector(dec_q'range); +signal ex6_decar_di : std_ulogic_vector(decar_q'range); +signal ex6_epcr_di : std_ulogic_vector(epcr_q'range); +signal ex6_esr_di : std_ulogic_vector(esr_q'range); +signal ex6_gdear_di : std_ulogic_vector(gdear_q'range); +signal ex6_gesr_di : std_ulogic_vector(gesr_q'range); +signal ex6_gpir_di : std_ulogic_vector(gpir_q'range); +signal ex6_gsrr0_di : std_ulogic_vector(gsrr0_q'range); +signal ex6_gsrr1_di : std_ulogic_vector(gsrr1_q'range); +signal ex6_hacop_di : std_ulogic_vector(hacop_q'range); +signal ex6_mcsr_di : std_ulogic_vector(mcsr_q'range); +signal ex6_mcsrr0_di : std_ulogic_vector(mcsrr0_q'range); +signal ex6_mcsrr1_di : std_ulogic_vector(mcsrr1_q'range); +signal ex6_msr_di : std_ulogic_vector(msr_q'range); +signal ex6_msrp_di : std_ulogic_vector(msrp_q'range); +signal ex6_srr0_di : std_ulogic_vector(srr0_q'range); +signal ex6_srr1_di : std_ulogic_vector(srr1_q'range); +signal ex6_tcr_di : std_ulogic_vector(tcr_q'range); +signal ex6_tsr_di : std_ulogic_vector(tsr_q'range); +signal ex6_udec_di : std_ulogic_vector(udec_q'range); +signal ex6_xucr1_di : std_ulogic_vector(xucr1_q'range); +signal + ex2_acop_rdec , ex2_ccr3_rdec , ex2_csrr0_rdec , ex2_csrr1_rdec + , ex2_ctr_rdec , ex2_dbcr0_rdec , ex2_dbcr1_rdec , ex2_dbcr2_rdec + , ex2_dbcr3_rdec , ex2_dbsr_rdec , ex2_dear_rdec , ex2_dec_rdec + , ex2_decar_rdec , ex2_epcr_rdec , ex2_esr_rdec , ex2_gdear_rdec + , ex2_gesr_rdec , ex2_gpir_rdec , ex2_gsrr0_rdec , ex2_gsrr1_rdec + , ex2_hacop_rdec , ex2_iar_rdec , ex2_lr_rdec , ex2_mcsr_rdec + , ex2_mcsrr0_rdec, ex2_mcsrr1_rdec, ex2_msrp_rdec , ex2_srr0_rdec + , ex2_srr1_rdec , ex2_tcr_rdec , ex2_tsr_rdec , ex2_udec_rdec + , ex2_xer_rdec , ex2_xucr1_rdec + : std_ulogic; +signal + ex2_acop_re , ex2_ccr3_re , ex2_csrr0_re , ex2_csrr1_re + , ex2_ctr_re , ex2_dbcr0_re , ex2_dbcr1_re , ex2_dbcr2_re + , ex2_dbcr3_re , ex2_dbsr_re , ex2_dear_re , ex2_dec_re + , ex2_decar_re , ex2_epcr_re , ex2_esr_re , ex2_gdear_re + , ex2_gesr_re , ex2_gpir_re , ex2_gsrr0_re , ex2_gsrr1_re + , ex2_hacop_re , ex2_iar_re , ex2_lr_re , ex2_mcsr_re + , ex2_mcsrr0_re , ex2_mcsrr1_re , ex2_msrp_re , ex2_srr0_re + , ex2_srr1_re , ex2_tcr_re , ex2_tsr_re , ex2_udec_re + , ex2_xer_re , ex2_xucr1_re + : std_ulogic; +signal ex2_pir_rdec : std_ulogic; +signal + ex2_acop_we , ex2_ccr3_we , ex2_csrr0_we , ex2_csrr1_we + , ex2_ctr_we , ex2_dbcr0_we , ex2_dbcr1_we , ex2_dbcr2_we + , ex2_dbcr3_we , ex2_dbsr_we , ex2_dbsrwr_we , ex2_dear_we + , ex2_dec_we , ex2_decar_we , ex2_epcr_we , ex2_esr_we + , ex2_gdear_we , ex2_gesr_we , ex2_gpir_we , ex2_gsrr0_we + , ex2_gsrr1_we , ex2_hacop_we , ex2_iar_we , ex2_lr_we + , ex2_mcsr_we , ex2_mcsrr0_we , ex2_mcsrr1_we , ex2_msrp_we + , ex2_srr0_we , ex2_srr1_we , ex2_tcr_we , ex2_tsr_we + , ex2_udec_we , ex2_xer_we , ex2_xucr1_we + : std_ulogic; +signal + ex2_acop_wdec , ex2_ccr3_wdec , ex2_csrr0_wdec , ex2_csrr1_wdec + , ex2_ctr_wdec , ex2_dbcr0_wdec , ex2_dbcr1_wdec , ex2_dbcr2_wdec + , ex2_dbcr3_wdec , ex2_dbsr_wdec , ex2_dbsrwr_wdec, ex2_dear_wdec + , ex2_dec_wdec , ex2_decar_wdec , ex2_epcr_wdec , ex2_esr_wdec + , ex2_gdear_wdec , ex2_gesr_wdec , ex2_gpir_wdec , ex2_gsrr0_wdec + , ex2_gsrr1_wdec , ex2_hacop_wdec , ex2_iar_wdec , ex2_lr_wdec + , ex2_mcsr_wdec , ex2_mcsrr0_wdec, ex2_mcsrr1_wdec, ex2_msrp_wdec + , ex2_srr0_wdec , ex2_srr1_wdec , ex2_tcr_wdec , ex2_tsr_wdec + , ex2_udec_wdec , ex2_xer_wdec , ex2_xucr1_wdec + : std_ulogic; +signal + ex6_acop_wdec , ex6_ccr3_wdec , ex6_csrr0_wdec , ex6_csrr1_wdec + , ex6_dbcr0_wdec , ex6_dbcr1_wdec , ex6_dbsr_wdec , ex6_dbsrwr_wdec + , ex6_dear_wdec , ex6_dec_wdec , ex6_decar_wdec , ex6_epcr_wdec + , ex6_esr_wdec , ex6_gdear_wdec , ex6_gesr_wdec , ex6_gpir_wdec + , ex6_gsrr0_wdec , ex6_gsrr1_wdec , ex6_hacop_wdec , ex6_mcsr_wdec + , ex6_mcsrr0_wdec, ex6_mcsrr1_wdec, ex6_msr_wdec , ex6_msrp_wdec + , ex6_srr0_wdec , ex6_srr1_wdec , ex6_tcr_wdec , ex6_tsr_wdec + , ex6_udec_wdec , ex6_xucr1_wdec + : std_ulogic; +signal + ex6_acop_we , ex6_ccr3_we , ex6_csrr0_we , ex6_csrr1_we + , ex6_dbcr0_we , ex6_dbcr1_we , ex6_dbsr_we , ex6_dbsrwr_we + , ex6_dear_we , ex6_dec_we , ex6_decar_we , ex6_epcr_we + , ex6_esr_we , ex6_gdear_we , ex6_gesr_we , ex6_gpir_we + , ex6_gsrr0_we , ex6_gsrr1_we , ex6_hacop_we , ex6_mcsr_we + , ex6_mcsrr0_we , ex6_mcsrr1_we , ex6_msr_we , ex6_msrp_we + , ex6_srr0_we , ex6_srr1_we , ex6_tcr_we , ex6_tsr_we + , ex6_udec_we , ex6_xucr1_we + : std_ulogic; +signal + acop_act , ccr3_act , csrr0_act , csrr1_act + , dbcr0_act , dbcr1_act , dbsr_act , dear_act + , dec_act , decar_act , epcr_act , esr_act + , gdear_act , gesr_act , gpir_act , gsrr0_act + , gsrr1_act , hacop_act , mcsr_act , mcsrr0_act + , mcsrr1_act , msr_act , msrp_act , srr0_act + , srr1_act , tcr_act , tsr_act , udec_act + , xucr1_act + : std_ulogic; +signal + acop_do , ccr3_do , csrr0_do , csrr1_do + , dbcr0_do , dbcr1_do , dbsr_do , dear_do + , dec_do , decar_do , epcr_do , esr_do + , gdear_do , gesr_do , gpir_do , gsrr0_do + , gsrr1_do , hacop_do , mcsr_do , mcsrr0_do + , mcsrr1_do , msr_do , msrp_do , srr0_do + , srr1_do , tcr_do , tsr_do , udec_do + , xucr1_do + : std_ulogic_vector(0 to 64); + +begin + + +tiup <= '1'; +tidn <= (others=>'0'); + +exx_act_d <= cspr_tspr_rf1_act & exx_act(1 to 4); + +exx_act(1) <= exx_act_q(1); +exx_act(2) <= exx_act_q(2); +exx_act(3) <= exx_act_q(3); +exx_act(4) <= exx_act_q(4); +exx_act(5) <= exx_act_q(5); + +exx_act_data(1) <= exx_act(1); +exx_act_data(2) <= exx_act(2); +exx_act_data(3) <= exx_act(3); +exx_act_data(4) <= exx_act(4); +exx_act_data(5) <= exx_act(5); + +ex5_int_act <= cpl_spr_ex5_act or cspr_xucr0_clkg_ctl(4); + +ex1_opcode_is_31 <= cspr_tspr_ex1_instr(0 to 5) = "011111"; +ex1_opcode_is_19 <= cspr_tspr_ex1_instr(0 to 5) = "010011"; +ex1_is_mfspr <= '1' when ex1_opcode_is_31 and cspr_tspr_ex1_instr(21 to 30) = "0101010011" else '0'; +ex1_is_mtspr <= '1' when ex1_opcode_is_31 and cspr_tspr_ex1_instr(21 to 30) = "0111010011" else '0'; +ex1_is_mfmsr <= '1' when ex1_opcode_is_31 and cspr_tspr_ex1_instr(21 to 30) = "0001010011" else '0'; +ex1_is_rfi <= '1' when ex1_opcode_is_19 and cspr_tspr_ex1_instr(21 to 30) = "0000110010" else '0'; +ex1_is_rfgi <= '1' when ex1_opcode_is_19 and cspr_tspr_ex1_instr(21 to 30) = "0001100110" else '0'; +ex1_is_rfci <= '1' when ex1_opcode_is_19 and cspr_tspr_ex1_instr(21 to 30) = "0000110011" else '0'; +ex1_is_rfmci <= '1' when ex1_opcode_is_19 and cspr_tspr_ex1_instr(21 to 30) = "0000100110" else '0'; +ex1_is_wrteei <= '1' when ex1_opcode_is_31 and cspr_tspr_ex1_instr(21 to 30) = "0010100011" else '0'; + +ex2_instr_d <= gate(cspr_tspr_ex1_instr(11 to 20),(ex1_is_mfspr or ex1_is_mtspr or ex1_is_wrteei)); + +ex2_is_mfmsr <= ex2_is_mfmsr_q; +ex2_is_mfspr <= ex2_is_mfspr_q; +ex2_is_mtspr <= ex2_is_mtspr_q; +ex2_instr <= ex2_instr_q; +ex6_is_mtmsr <= ex6_is_mtmsr_q; +ex6_is_mtspr <= ex6_is_mtspr_q; +ex6_instr <= ex6_instr_q; +ex6_spr_wd <= ex6_spr_wd_q; + +ex4_val <= dec_spr_ex4_val and not xu_ex4_flush; +ex5_val <= ex5_val_q and not xu_ex5_flush; +ex6_val <= ex6_val_q; +ex2_rfgi_d <=(ex1_is_rfi and mux_msr_gs_q(0)) or ex1_is_rfgi; +ex2_rfi_d <= ex1_is_rfi and not mux_msr_gs_q(0); +ex6_any_int <= ex6_int_q or ex6_cint_q or ex6_mcint_q or ex6_gint_q; +ex6_any_hint <= ex6_int_q or ex6_cint_q or ex6_mcint_q; +ex6_rfi <= ex6_val and ex6_rfi_q; +ex6_rfgi <= ex6_val and ex6_rfgi_q; +ex6_rfci <= ex6_val and ex6_rfci_q; +ex6_rfmci <= ex6_val and ex6_rfmci_q; +ex6_wrteei <= ex6_val and ex6_wrteei_q; +ex6_wrtee <= ex6_val and ex6_wrtee_q; + +ex3_tid_rpwr_d <= (others=>cspr_tspr_ex2_tid); + +tb_tap_edge <= cspr_tspr_timebase_taps and not timebase_taps_q; + + +acop_act <= ex6_acop_we; +acop_d <= ex6_acop_di; + +ccr3_act <= ex6_ccr3_we; +ccr3_d <= ex6_ccr3_di; + +csrr0_act <= ex6_csrr0_we or ex6_cint_q; + +with ex6_cint_q select + csrr0_d <= ex6_nia_srr0 when '1', + ex6_csrr0_di when others; + +csrr1_act <= ex6_csrr1_we or ex6_cint_q; + +csrr1_gen_64 : if regsize = 64 generate + ex6_csrr1_d <= ex6_csrr1_di; +end generate; +csrr1_gen_32 : if regsize = 32 generate + ex6_csrr1_d(MSR_CM) <= '0'; + ex6_csrr1_d(MSR_GS to MSR_DS) <= ex6_csrr1_di(MSR_GS to MSR_DS); +end generate; + +with ex6_cint_q select + csrr1_d <= msr_q when '1', + ex6_csrr1_d when others; + +dbcr0_act <= ex6_dbcr0_we; +dbcr0_d <= ex6_dbcr0_di; + +dbcr1_act <= ex6_dbcr1_we; +dbcr1_d <= ex6_dbcr1_di; + +reset_complete_act <= or_reduce(reset_complete); + +dbsr_mrr_act <= reset_complete_act or ex6_dbsr_we or ex6_dbsrwr_we; + +dbsr_mrr_d <= reset_complete when reset_complete_act ='1' else + ex6_spr_wd(34 to 35) when ex6_dbsrwr_we ='1' else + (dbsr_mrr_q and not ex6_spr_wd(34 to 35)); + +dbsr_act <= ex6_dbsr_we or ex6_dbsrwr_we or ex6_dbsr_update_q; + +set_dbsr_ide <= ((ex6_dbsr_q(0) or or_reduce(ex6_dbsr_q(3 to 18))) and not msr_q(60)) or ex6_dbsr_ide_q; +set_dbsr <= set_dbsr_ide & ex6_dbsr_q(0 to 18); + +dbsr_d <= dbsr_di or gate(set_dbsr,ex6_dbsr_update_q); +dbsr_di <= ex6_dbsr_di when ex6_dbsrwr_we ='1' else + (dbsr_q and not ex6_dbsr_di) when ex6_dbsr_we ='1' else + dbsr_q; + +dear_act <= ex6_dear_we or (ex6_dear_update_q and not ex6_gint_q); + +dear_tmp_d(32 to 63) <= ex6_dear_di(32 to 63); +dear_di(32 to 63) <= ex6_dear_di(32 to 63); +xuq_cpl_dear_mask_gen0 : if (64-regsize) < 32 generate + dear_di(dear_d'left to 31) <= ex6_dear_di(dear_d'left to 31) and (dear_d'left to 31=>(spr_msr_cm or not ex6_dear_update_q)); + dear_tmp_d(dear_d'left to 31) <= ex6_dear_di(dear_d'left to 31) and (dear_d'left to 31=> spr_msr_cm); +end generate; + +with ex6_dear_update_saved_q select + dear_d <= dear_tmp_q when '1', + dear_di when others; + +gdear_act <= ex6_gdear_we or (ex6_dear_update_q and ex6_gint_q); + +gdear_d <= dear_d; + +dec_running <= timer_update and not (not spr_tcr_are and ex6_dec_zero) and not cspr_tspr_dec_dbg_dis and not dbcr0_freeze_timers; + +dec_act <= ex6_dec_we or dec_running; + +dec_d <= ex6_dec_di when ex6_dec_we ='1' else + decar_q when (ex6_set_tsr_dis and spr_tcr_are) ='1' else + std_ulogic_vector(unsigned(dec_q) - 1); + +udec_running <= timer_update and not ex6_udec_zero and not cspr_tspr_dec_dbg_dis and not dbcr0_freeze_timers; + +udec_act <= ex6_udec_we or udec_running; + +udec_d <= ex6_udec_di when ex6_udec_we ='1' else + std_ulogic_vector(unsigned(udec_q) - 1); + +decar_act <= ex6_decar_we; +decar_d <= ex6_decar_di; + +epcr_act <= ex6_epcr_we; +epcr_d <= ex6_epcr_di; + +esr_act <= ex6_esr_we or (ex6_esr_update_q and ex6_int_q); + +esr_d <= ex6_esr_q when ex6_esr_update_q ='1' else + ex6_esr_di when ex6_esr_we ='1' else + esr_q; + +gesr_act <= ex6_gesr_we or (ex6_esr_update_q and ex6_gint_q); + +gesr_d <= ex6_esr_q when ex6_esr_update_q ='1' else + ex6_gesr_di when ex6_gesr_we ='1' else + gesr_q; + +gpir_act <= ex6_gpir_we; +gpir_d <= ex6_gpir_di; + +hacop_act <= ex6_hacop_we; +hacop_d <= ex6_hacop_di; + +mcsr_act <= ex6_mcsr_we or ex6_mcint_q; + +mcsr_d <= ex6_mcsr_q when ex6_mcint_q ='1' else + ex6_mcsr_di when ex6_mcsr_we ='1' else + mcsr_q; + +mcsrr0_act <= ex6_mcsrr0_we or ex6_mcint_q; + +with ex6_mcint_q select + mcsrr0_d <= ex6_nia_srr0 when '1', + ex6_mcsrr0_di when others; + +mcsrr1_act <= ex6_mcsrr1_we or ex6_mcint_q; + +mcsrr1_gen_64 : if regsize = 64 generate + ex6_mcsrr1_d <= ex6_mcsrr1_di; +end generate; +mcsrr1_gen_32 : if regsize = 32 generate + ex6_mcsrr1_d(MSR_CM) <= '0'; + ex6_mcsrr1_d(MSR_GS to MSR_DS) <= ex6_mcsrr1_di(MSR_GS to MSR_DS); +end generate; + +with ex6_mcint_q select + mcsrr1_d <= msr_q when '1', + ex6_mcsrr1_d when others; + +msr_act <= cspr_xucr0_clkg_ctl(4) or + ex6_any_int or ex6_msr_we or + ex6_wrteei_q or ex6_wrtee_q or + ex6_rfi_q or ex6_rfgi_q or ex6_rfci_q or ex6_rfmci_q; + + +with (msrp_q(MSRP_UCLEP) and msr_q(MSR_GS)) select + ex6_msr_di2(MSR_UCLE) <= msr_q(MSR_UCLE) when '1', + ex6_msr_di(MSR_UCLE) when others; + +with (msrp_q(MSRP_DEP) and msr_q(MSR_GS)) select + ex6_msr_di2(MSR_DE) <= msr_q(MSR_DE) when '1', + ex6_msr_di(MSR_DE) when others; + +ex6_msr_di2(MSR_CM) <= ex6_msr_di(MSR_CM); +ex6_msr_di2(MSR_GS) <= ex6_msr_di(MSR_GS) or msr_q(MSR_GS); +ex6_msr_di2(MSR_SPV to MSR_FE0) <= ex6_msr_di(MSR_SPV to MSR_FE0); +ex6_msr_di2(MSR_FE1 to MSR_DS) <= ex6_msr_di(MSR_FE1 to MSR_DS); + + +ex6_msr_mask(MSR_CM) <= '0'; +ex6_msr_mask(MSR_GS) <= ex6_any_hint; +ex6_msr_mask(MSR_UCLE) <= ex6_any_hint or (ex6_gint_q and not msrp_q(MSRP_UCLEP)); +ex6_msr_mask(MSR_SPV) <= ex6_any_int; +ex6_msr_mask(MSR_CE) <= ex6_mcint_q or ex6_cint_q; +ex6_msr_mask(MSR_EE) <= ex6_any_int; +ex6_msr_mask(MSR_PR to MSR_FP) <= (others=>ex6_any_int); +ex6_msr_mask(MSR_ME) <= ex6_mcint_q; +ex6_msr_mask(MSR_FE0) <= ex6_any_int; +ex6_msr_mask(MSR_DE) <= ex6_mcint_q or ex6_cint_q; +ex6_msr_mask(MSR_FE1 to MSR_DS) <= (others=>ex6_any_int); + +with s5'(ex6_rfi & ex6_rfgi & ex6_rfci & ex6_rfmci & ex6_msr_we) select + ex6_msr_mux <= srr1_q when "10000", + ex6_rfgi_msr when "01000", + csrr1_q when "00100", + mcsrr1_q when "00010", + ex6_msr_di2 when "00001", + msr_q when others; + +ex6_msr_in(51 to 54) <= ex6_msr_mux(51 to 54); +ex6_msr_in(56 to 63) <= ex6_msr_mux(56 to 63); + +with s2'(ex6_any_hint & ex6_gint_q) select + ex6_msr_in(MSR_CM) <= spr_epcr_icm when "10", + spr_epcr_gicm when "01", + ex6_msr_mux(MSR_CM) when others; + +with s2'(ex6_wrteei & ex6_wrtee) select + ex6_msr_in(MSR_EE) <= ex6_instr_q(16) when "10", + ex6_spr_wd(48) when "01", + ex6_msr_mux(MSR_EE) when others; + +msr_gen_64 : if regsize = 64 generate + msr_d <= ex6_msr_in and not ex6_msr_mask; +end generate; +msr_gen_32 : if regsize = 32 generate + msr_d(MSR_CM) <= '0'; + msr_d(MSR_GS to MSR_DS) <= ex6_msr_in(MSR_GS to MSR_DS) and not ex6_msr_mask(MSR_GS to MSR_DS); +end generate; + +ex6_rfgi_msr(MSR_CM) <= gsrr1_q(MSR_CM); +ex6_rfgi_msr(MSR_SPV to MSR_FE0) <= gsrr1_q(MSR_SPV to MSR_FE0); +ex6_rfgi_msr(MSR_FE1 to MSR_DS) <= gsrr1_q(MSR_FE1 to MSR_DS); + +with (msr_q(MSR_GS)) select + ex6_rfgi_msr(MSR_GS) <= msr_q(MSR_GS) when '1', + gsrr1_q(MSR_GS) when others; + +with (msrp_q(MSRP_UCLEP) and msr_q(MSR_GS)) select + ex6_rfgi_msr(MSR_UCLE) <= msr_q(MSR_UCLE) when '1', + gsrr1_q(MSR_UCLE) when others; + +with (msrp_q(MSRP_DEP) and msr_q(MSR_GS)) select + ex6_rfgi_msr(MSR_DE) <= msr_q(MSR_DE) when '1', + gsrr1_q(MSR_DE) when others; + +msrp_act <= ex6_msrp_we; +msrp_d <= ex6_msrp_di; + +srr0_act <= ex6_srr0_we or (ex6_int_q and not ex6_force_gsrr_q); + +ex6_nia_srr0_dec <= (ex6_nia_q'left to 60=>'0') & ex6_srr0_dec_q; +ex6_nia_srr0 <= std_ulogic_vector(unsigned(ex6_nia_q) - unsigned(ex6_nia_srr0_dec)); + +with ex6_int_q select + srr0_d <= ex6_nia_srr0 when '1', + ex6_srr0_di when others; + +srr1_act <= ex6_srr1_we or (ex6_int_q and not ex6_force_gsrr_q); + +srr1_gen_64 : if regsize = 64 generate + ex6_srr1_d <= ex6_srr1_di; +end generate; +srr1_gen_32 : if regsize = 32 generate + ex6_srr1_d(MSR_CM) <= '0'; + ex6_srr1_d(MSR_GS to MSR_DS) <= ex6_srr1_di(MSR_GS to MSR_DS); +end generate; + +with ex6_int_q select + srr1_d <= msr_q when '1', + ex6_srr1_d when others; + + +ex6_gint_nia_sel <= ex6_gint_q or (ex6_int_q and ex6_force_gsrr_q); + +gsrr0_act <= ex6_gsrr0_we or ex6_gint_nia_sel; + + +with ex6_gint_nia_sel select + gsrr0_d <= ex6_nia_srr0 when '1', + ex6_gsrr0_di when others; + +gsrr1_act <= ex6_gsrr1_we or ex6_gint_nia_sel; + +gsrr1_gen_64 : if regsize = 64 generate + ex6_gsrr1_d <= ex6_gsrr1_di; +end generate; +gsrr1_gen_32 : if regsize = 32 generate + ex6_gsrr1_d(MSR_CM) <= '0'; + ex6_gsrr1_d(MSR_GS to MSR_DS) <= ex6_gsrr1_di(MSR_GS to MSR_DS); +end generate; + +with ex6_gint_nia_sel select + gsrr1_d <= msr_q when '1', + ex6_gsrr1_d when others; + +tcr_act <= ex6_tcr_we; +tcr_d <= ex6_tcr_di; + +tsr_wrs_act <= (reset_wd_complete and reset_complete_act) or ex6_tsr_we; + +tsr_wrs_d <= reset_complete when (reset_wd_complete and reset_complete_act) ='1' else + (tsr_wrs_q and not ex6_spr_wd(34 to 35)); + +tsr_act <= cspr_xucr0_clkg_ctl(4) or ex6_tsr_we or or_reduce(ex6_set_tsr); + +tsr_d <= ex6_set_tsr or (tsr_q and not (ex6_tsr_di and (tsr_q'range=>ex6_tsr_we))); + +xucr1_act <= ex6_xucr1_we; +xucr1_d <= ex6_xucr1_di; + +with spr_xucr1_ll_tb_sel select + lltbtap <= tb_tap_edge(8) when "000", + tb_tap_edge(5) when "001", + tb_tap_edge(4) when "010", + tb_tap_edge(3) when "011", + tb_tap_edge(7) when "100", + tb_tap_edge(2) when "101", + tb_tap_edge(6) when "110", + tb_tap_edge(1) when others; + +hang_pulse_d <= an_ac_hang_pulse & hang_pulse_q(0 to 2); +hang_pulse <= hang_pulse_q(2) and not hang_pulse_q(3); + + +with spr_xucr1_ll_sel select + lltap_d <= hang_pulse when '1', + lltbtap when others; + +llpulse <= not llcnt_q(0) and + cspr_tspr_llen and + spr_xucr1_ll_en and + lltap_q; + +llreset <= (cpl_spr_ex5_instr_cpl and not ((inj_llbust_attempt_q and not llcnt_q(0)) or inj_llbust_failed_q)) or not cspr_tspr_llen; + +with s2'(llpulse & llreset) select + llcnt_d <= "00" when "01", + "00" when "11", +std_ulogic_vector(signed(llcnt_q) + 1) when "10", + llcnt_q when others; + +tspr_cspr_lldet <= llcnt_q(0) and spr_xucr1_ll_en; +tspr_cspr_llpulse <= llpulse; + +llstate(0) <= llcnt_q(0); +llstate(1) <= llcnt_q(1) or (llcnt_q(0) and not cspr_tspr_llpri); + +raise_iss_pri_d <= (not spr_msr_ee and spr_ccr3_en_eepri) or + (llcnt_q(0) and spr_xucr1_ll_en); +xu_iu_raise_iss_pri <= raise_iss_pri_2_q; + +err_llbust_attempt_d <= llstate(0) and not llstate(1); +err_llbust_failed_d <= llstate(0) and cspr_tspr_llen and spr_xucr1_ll_en and lltap_q and cspr_tspr_llpri; + +xu_spr_tspr_llbust_err_rpt : entity tri.tri_direct_err_rpt(tri_direct_err_rpt) +generic map(width => 2, expand_type => expand_type) +port map ( vd => vdd, gd => gnd, + err_in(0) => err_llbust_attempt_q, + err_in(1) => err_llbust_failed_q, + err_out(0) => xu_pc_err_llbust_attempt, + err_out(1) => xu_pc_err_llbust_failed); + +ex6_dec_upper_zero <= not or_reduce(dec_q(32 to 62)); +ex6_set_tsr_dis <= dec_running and ex6_dec_upper_zero and dec_q(63); +ex6_dec_zero <= ex6_dec_upper_zero and not dec_q(63); + +ex6_udec_upper_zero <= not or_reduce(udec_q(32 to 62)); +ex6_set_tsr_udis <= udec_running and ex6_udec_upper_zero and udec_q(63); +ex6_udec_zero <= ex6_udec_upper_zero and not udec_q(63); + +with spr_tcr_fp select + fit_tb_tap_d <= tb_tap_edge(5) when "00", + tb_tap_edge(4) when "01", + tb_tap_edge(3) when "10", + tb_tap_edge(2) when others; + +ex6_set_tsr_fis <= fit_tb_tap_q; + +with spr_tcr_wp select + wdog_tb_tap_d <= tb_tap_edge(3) when "00", + tb_tap_edge(2) when "01", + tb_tap_edge(9) when "10", + tb_tap_edge(0) when others; + +wdog_pulse <= wdog_tb_tap_q or pc_xu_inj_wdt_reset_q; + +ex6_set_tsr_enw <= wdog_pulse and not spr_tsr_enw; +ex6_set_tsr_wis <= wdog_pulse and spr_tsr_enw and not spr_tsr_wis; + +ex6_set_tsr <= ex6_set_tsr_enw & + ex6_set_tsr_wis & + ex6_set_tsr_dis & + ex6_set_tsr_fis & + ex6_set_tsr_udis; + + +reset_complete <= "11" when reset_3_complete='1' else + "10" when reset_2_complete='1' else + "01" when reset_1_complete='1' else + "00"; + +wdog_reset_1 <= spr_tsr_enw and spr_tsr_wis and (spr_tcr_wrc="01"); +wdog_reset_2 <= spr_tsr_enw and spr_tsr_wis and (spr_tcr_wrc="10"); +wdog_reset_3 <= spr_tsr_enw and spr_tsr_wis and (spr_tcr_wrc="11"); +reset_wd_request <= spr_tsr_enw and spr_tsr_wis and not (spr_tcr_wrc="00"); + +reset_1_request <= wdog_reset_1 or (spr_dbcr0_rst="01"); +reset_2_request <= wdog_reset_2 or (spr_dbcr0_rst="10"); +reset_3_request <= wdog_reset_3 or (spr_dbcr0_rst="11"); +err_wdt_reset_d <= spr_tsr_enw and spr_tsr_wis and or_reduce(spr_tcr_wrc); + +xu_spr_tspr_wdt_err_rpt : entity tri.tri_direct_err_rpt(tri_direct_err_rpt) +generic map (width => 1, expand_type => expand_type) +port map (vd => vdd, gd => gnd, + err_in(0) => err_wdt_reset_q, + err_out(0) => xu_pc_err_wdt_reset); + +dbcr0_freeze_timers <= spr_dbcr0_ft and (spr_dbsr_ide or dbsr_event); +tspr_cspr_freeze_timers <= dbcr0_freeze_timers; + + +ex2_icswx_gs <= epsc_egs_q when ex2_epid_instr_q='1' else spr_msr_gs; +ex2_icswx_pr <= epsc_epr_q when ex2_epid_instr_q='1' else spr_msr_pr; + +ex2_acop_ct <= gate_or(not ex2_icswx_pr,spr_acop_ct); + +ex2_cop_ct <= spr_hacop_ct and ex2_acop_ct; + +ex3_ct_d(0) <= ex2_ct(0) or (not ex2_icswx_pr and not ex2_icswx_gs); +ex3_ct_d(1) <= ex2_ct(1) or (not ex2_icswx_pr and not ex2_icswx_gs); + +with ex2_rs2_q(42 to 47) select + ex2_ct(0)<= ex2_cop_ct(32) when "100000", + ex2_cop_ct(33) when "100001", + ex2_cop_ct(34) when "100010", + ex2_cop_ct(35) when "100011", + ex2_cop_ct(36) when "100100", + ex2_cop_ct(37) when "100101", + ex2_cop_ct(38) when "100110", + ex2_cop_ct(39) when "100111", + ex2_cop_ct(40) when "101000", + ex2_cop_ct(41) when "101001", + ex2_cop_ct(42) when "101010", + ex2_cop_ct(43) when "101011", + ex2_cop_ct(44) when "101100", + ex2_cop_ct(45) when "101101", + ex2_cop_ct(46) when "101110", + ex2_cop_ct(47) when "101111", + ex2_cop_ct(48) when "110000", + ex2_cop_ct(49) when "110001", + ex2_cop_ct(50) when "110010", + ex2_cop_ct(51) when "110011", + ex2_cop_ct(52) when "110100", + ex2_cop_ct(53) when "110101", + ex2_cop_ct(54) when "110110", + ex2_cop_ct(55) when "110111", + ex2_cop_ct(56) when "111000", + ex2_cop_ct(57) when "111001", + ex2_cop_ct(58) when "111010", + ex2_cop_ct(59) when "111011", + ex2_cop_ct(60) when "111100", + ex2_cop_ct(61) when "111101", + ex2_cop_ct(62) when "111110", + ex2_cop_ct(63) when "111111", + '0' when others; + +with ex2_rs2_q(50 to 55) select + ex2_ct(1)<= ex2_cop_ct(32) when "100000", + ex2_cop_ct(33) when "100001", + ex2_cop_ct(34) when "100010", + ex2_cop_ct(35) when "100011", + ex2_cop_ct(36) when "100100", + ex2_cop_ct(37) when "100101", + ex2_cop_ct(38) when "100110", + ex2_cop_ct(39) when "100111", + ex2_cop_ct(40) when "101000", + ex2_cop_ct(41) when "101001", + ex2_cop_ct(42) when "101010", + ex2_cop_ct(43) when "101011", + ex2_cop_ct(44) when "101100", + ex2_cop_ct(45) when "101101", + ex2_cop_ct(46) when "101110", + ex2_cop_ct(47) when "101111", + ex2_cop_ct(48) when "110000", + ex2_cop_ct(49) when "110001", + ex2_cop_ct(50) when "110010", + ex2_cop_ct(51) when "110011", + ex2_cop_ct(52) when "110100", + ex2_cop_ct(53) when "110101", + ex2_cop_ct(54) when "110110", + ex2_cop_ct(55) when "110111", + ex2_cop_ct(56) when "111000", + ex2_cop_ct(57) when "111001", + ex2_cop_ct(58) when "111010", + ex2_cop_ct(59) when "111011", + ex2_cop_ct(60) when "111100", + ex2_cop_ct(61) when "111101", + ex2_cop_ct(62) when "111110", + ex2_cop_ct(63) when "111111", + '0' when others; + +spr_cpl_ex3_ct_be <= ex3_ct_q(0); +spr_cpl_ex3_ct_le <= ex3_ct_q(1); + + +iac_us_en(1) <= (not spr_dbcr1_iac1us(0) and not spr_dbcr1_iac1us(1)) or + ( spr_dbcr1_iac1us(0) and (spr_dbcr1_iac1us(1) xnor spr_msr_pr)); + +iac_us_en(2) <= (not spr_dbcr1_iac2us(0) and not spr_dbcr1_iac2us(1)) or + ( spr_dbcr1_iac2us(0) and (spr_dbcr1_iac2us(1) xnor spr_msr_pr)); + +iac_us_en(3) <= (not spr_dbcr1_iac3us(0) and not spr_dbcr1_iac3us(1)) or + ( spr_dbcr1_iac3us(0) and (spr_dbcr1_iac3us(1) xnor spr_msr_pr)); + +iac_us_en(4) <= (not spr_dbcr1_iac4us(0) and not spr_dbcr1_iac4us(1)) or + ( spr_dbcr1_iac4us(0) and (spr_dbcr1_iac4us(1) xnor spr_msr_pr)); + +iac_er_en(1) <= (not spr_dbcr1_iac1er(0) and not spr_dbcr1_iac1er(1)) or + ( spr_dbcr1_iac1er(0) and (spr_dbcr1_iac1er(1) xnor spr_msr_is)); + +iac_er_en(2) <= (not spr_dbcr1_iac2er(0) and not spr_dbcr1_iac2er(1)) or + ( spr_dbcr1_iac2er(0) and (spr_dbcr1_iac2er(1) xnor spr_msr_is)); + +iac_er_en(3) <= (not spr_dbcr1_iac3er(0) and not spr_dbcr1_iac3er(1)) or + ( spr_dbcr1_iac3er(0) and (spr_dbcr1_iac3er(1) xnor spr_msr_is)); + +iac_er_en(4) <= (not spr_dbcr1_iac4er(0) and not spr_dbcr1_iac4er(1)) or + ( spr_dbcr1_iac4er(0) and (spr_dbcr1_iac4er(1) xnor spr_msr_is)); + +iac1_en_d <= spr_dbcr0_iac1 and iac_us_en(1) and iac_er_en(1); +iac2_en_d <= spr_dbcr0_iac2 and iac_us_en(2) and iac_er_en(2); +iac3_en_d <= spr_dbcr0_iac3 and iac_us_en(3) and iac_er_en(3); +iac4_en_d <= spr_dbcr0_iac4 and iac_us_en(4) and iac_er_en(4); +spr_cpl_iac1_en <= iac1_en_q; +spr_cpl_iac2_en <= iac2_en_q; +spr_cpl_iac3_en <= iac3_en_q; +spr_cpl_iac4_en <= iac4_en_q; + +spr_cpl_crit_interrupt <= crit_interrupt_q; +spr_cpl_wdog_interrupt <= wdog_interrupt_q; +spr_cpl_dec_interrupt <= dec_interrupt_q; +spr_cpl_udec_interrupt <= udec_interrupt_q; +spr_cpl_perf_interrupt <= perf_interrupt_q; +spr_cpl_fit_interrupt <= fit_interrupt_q; +spr_cpl_ext_interrupt <= ext_interrupt_q; +spr_cpl_external_mchk <= mchk_interrupt_q; + +mchk_int <= cspr_tspr_crit_mask and an_ac_external_mchk_q; + +mchk_interrupt <= cspr_tspr_crit_mask and an_ac_external_mchk_q and (spr_msr_gs or spr_msr_me); +crit_interrupt <= cspr_tspr_crit_mask and an_ac_crit_interrupt_q and (spr_msr_gs or spr_msr_ce); +wdog_interrupt <= cspr_tspr_wdog_mask and spr_tsr_wis and (spr_msr_gs or spr_msr_ce) and spr_tcr_wie; +dec_interrupt <= cspr_tspr_dec_mask and spr_tsr_dis and (spr_msr_gs or spr_msr_ee) and spr_tcr_die; +udec_interrupt <= cspr_tspr_udec_mask and spr_tsr_udis and (spr_msr_gs or spr_msr_ee) and spr_tcr_udie; +perf_interrupt <= cspr_tspr_perf_mask and an_ac_perf_interrupt_q and (spr_msr_gs or spr_msr_ee); +fit_interrupt <= cspr_tspr_fit_mask and spr_tsr_fis and (spr_msr_gs or spr_msr_ee) and spr_tcr_fie; +ext_interrupt <= cspr_tspr_ext_mask and an_ac_ext_interrupt_q and (( spr_epcr_extgs and spr_msr_gs and spr_msr_ee) or + (not spr_epcr_extgs and (spr_msr_gs or spr_msr_ee))); +tspr_cspr_pm_wake_up <= ex6_any_int or + mchk_interrupt_q or + crit_interrupt_q or + wdog_interrupt_q or + dec_interrupt_q or + udec_interrupt_q or + perf_interrupt_q or + fit_interrupt_q or + ext_interrupt_q; + +tspr_cspr_async_int <= an_ac_ext_interrupt_q & an_ac_crit_interrupt_q & an_ac_perf_interrupt_q; + +tspr_cspr_gpir_match <= '1' when cspr_tspr_dbell_pirtag = gpir_do(51 to 64) else '0'; + +with cspr_tspr_msrovride_en select + mux_msr_pr <= msrovride_pr_q when '1', + spr_msr_pr when others; + +with cspr_tspr_msrovride_en select + mux_msr_gs <= msrovride_gs_q when '1', + spr_msr_gs when others; + +with cspr_tspr_msrovride_en select + mux_msr_de <= msrovride_de_q when '1', + spr_msr_de when others; + + +mux_msr_gs_d <= (others=>mux_msr_gs); +mux_msr_pr_d <= (others=>mux_msr_pr); + +udec_en <= ram_mode_q or spr_tcr_ud; + +tspr_fp_precise <= fp_precise; +fp_precise <= (spr_msr_fe0 or spr_msr_fe1); + +tspr_msr_de <= mux_msr_de; +tspr_msr_cm <= spr_msr_cm; +tspr_msr_is <= spr_msr_is; +tspr_msr_gs <= mux_msr_gs_q(3); +tspr_msr_pr <= mux_msr_pr_q(0); +tspr_msr_ee <= spr_msr_ee; +tspr_msr_ce <= spr_msr_ce; +tspr_msr_me <= spr_msr_me; +tspr_epcr_extgs <= spr_epcr_extgs; +dbsr_event <= or_reduce(dbsr_q(45 to 63)); +spr_cpl_dbsr_ide <= spr_dbsr_ide and dbsr_event; +single_instr_mode_d <= spr_ccr3_si or (fp_precise and msr_q(MSR_FP)) or instr_trace_mode; +xu_iu_single_instr_mode <= single_instr_mode_2_q; +machine_check_d <= or_reduce(mcsr_q); +ac_tc_machine_check <= machine_check_q; + +tspr_debug <= ex6_int_q & + ex6_gint_q & + ex6_cint_q & + ex6_mcint_q & + ex6_esr_update_q & + ex6_dbsr_update_q & + ex6_dear_update_q & + ex6_dear_save_q & + ex6_dear_update_saved_q & + an_ac_crit_interrupt_q & + an_ac_perf_interrupt_q & + an_ac_ext_interrupt_q; + + +spr_byp_ex4_is_mtxer <= ex4_is_mtxer_q; +spr_byp_ex4_is_mfxer <= ex4_is_mfxer_q; +ex3_is_mfxer_d <= ex2_is_mfspr and ex2_xer_rdec; +ex3_is_mtxer_d <= ex2_is_mtspr and ex2_xer_rdec; + +ex2_srr0_re2 <= ex2_rfi_q; +ex2_gsrr0_re2 <= ex2_rfgi_q; +ex2_csrr0_re2 <= ex2_rfci_q; +ex2_mcsrr0_re2 <= ex2_rfmci_q; + +readmux_00 : if a2mode = 0 and hvmode = 0 generate +ex3_tspr_rt_d <= + (ccr3_do(DO'range) and (DO'range => ex2_ccr3_re )) or + (dbcr0_do(DO'range) and (DO'range => ex2_dbcr0_re )) or + (dbcr1_do(DO'range) and (DO'range => ex2_dbcr1_re )) or + (dbsr_do(DO'range) and (DO'range => ex2_dbsr_re )) or + (dear_do(DO'range) and (DO'range => ex2_dear_re )) or + (dec_do(DO'range) and (DO'range => ex2_dec_re )) or + (esr_do(DO'range) and (DO'range => ex2_esr_re )) or + (msr_do(DO'range) and (DO'range => ex2_is_mfmsr )) or + (srr0_do(DO'range) and (DO'range => (ex2_srr0_re or ex2_srr0_re2))) or + (srr1_do(DO'range) and (DO'range => ex2_srr1_re )) or + (xucr1_do(DO'range) and (DO'range => ex2_xucr1_re )); +end generate; +readmux_01 : if a2mode = 0 and hvmode = 1 generate +ex3_tspr_rt_d <= + (ccr3_do(DO'range) and (DO'range => ex2_ccr3_re )) or + (dbcr0_do(DO'range) and (DO'range => ex2_dbcr0_re )) or + (dbcr1_do(DO'range) and (DO'range => ex2_dbcr1_re )) or + (dbsr_do(DO'range) and (DO'range => ex2_dbsr_re )) or + (dear_do(DO'range) and (DO'range => ex2_dear_re )) or + (dec_do(DO'range) and (DO'range => ex2_dec_re )) or + (epcr_do(DO'range) and (DO'range => ex2_epcr_re )) or + (esr_do(DO'range) and (DO'range => ex2_esr_re )) or + (gdear_do(DO'range) and (DO'range => ex2_gdear_re )) or + (gesr_do(DO'range) and (DO'range => ex2_gesr_re )) or + (gpir_do(DO'range) and (DO'range => ex2_gpir_re )) or + (gsrr0_do(DO'range) and (DO'range => (ex2_gsrr0_re or ex2_gsrr0_re2))) or + (gsrr1_do(DO'range) and (DO'range => ex2_gsrr1_re )) or + (hacop_do(DO'range) and (DO'range => ex2_hacop_re )) or + (msr_do(DO'range) and (DO'range => ex2_is_mfmsr )) or + (msrp_do(DO'range) and (DO'range => ex2_msrp_re )) or + (srr0_do(DO'range) and (DO'range => (ex2_srr0_re or ex2_srr0_re2))) or + (srr1_do(DO'range) and (DO'range => ex2_srr1_re )) or + (xucr1_do(DO'range) and (DO'range => ex2_xucr1_re )); +end generate; +readmux_10 : if a2mode = 1 and hvmode = 0 generate +ex3_tspr_rt_d <= + (acop_do(DO'range) and (DO'range => ex2_acop_re )) or + (ccr3_do(DO'range) and (DO'range => ex2_ccr3_re )) or + (csrr0_do(DO'range) and (DO'range => (ex2_csrr0_re or ex2_csrr0_re2))) or + (csrr1_do(DO'range) and (DO'range => ex2_csrr1_re )) or + (dbcr0_do(DO'range) and (DO'range => ex2_dbcr0_re )) or + (dbcr1_do(DO'range) and (DO'range => ex2_dbcr1_re )) or + (dbsr_do(DO'range) and (DO'range => ex2_dbsr_re )) or + (dear_do(DO'range) and (DO'range => ex2_dear_re )) or + (dec_do(DO'range) and (DO'range => ex2_dec_re )) or + (decar_do(DO'range) and (DO'range => ex2_decar_re )) or + (esr_do(DO'range) and (DO'range => ex2_esr_re )) or + (mcsr_do(DO'range) and (DO'range => ex2_mcsr_re )) or + (mcsrr0_do(DO'range) and (DO'range => (ex2_mcsrr0_re or ex2_mcsrr0_re2))) or + (mcsrr1_do(DO'range) and (DO'range => ex2_mcsrr1_re )) or + (msr_do(DO'range) and (DO'range => ex2_is_mfmsr )) or + (srr0_do(DO'range) and (DO'range => (ex2_srr0_re or ex2_srr0_re2))) or + (srr1_do(DO'range) and (DO'range => ex2_srr1_re )) or + (tcr_do(DO'range) and (DO'range => ex2_tcr_re )) or + (tsr_do(DO'range) and (DO'range => ex2_tsr_re )) or + (udec_do(DO'range) and (DO'range => ex2_udec_re )) or + (xucr1_do(DO'range) and (DO'range => ex2_xucr1_re )); +end generate; +readmux_11 : if a2mode = 1 and hvmode = 1 generate +ex3_tspr_rt_d <= + (acop_do(DO'range) and (DO'range => ex2_acop_re )) or + (ccr3_do(DO'range) and (DO'range => ex2_ccr3_re )) or + (csrr0_do(DO'range) and (DO'range => (ex2_csrr0_re or ex2_csrr0_re2))) or + (csrr1_do(DO'range) and (DO'range => ex2_csrr1_re )) or + (dbcr0_do(DO'range) and (DO'range => ex2_dbcr0_re )) or + (dbcr1_do(DO'range) and (DO'range => ex2_dbcr1_re )) or + (dbsr_do(DO'range) and (DO'range => ex2_dbsr_re )) or + (dear_do(DO'range) and (DO'range => ex2_dear_re )) or + (dec_do(DO'range) and (DO'range => ex2_dec_re )) or + (decar_do(DO'range) and (DO'range => ex2_decar_re )) or + (epcr_do(DO'range) and (DO'range => ex2_epcr_re )) or + (esr_do(DO'range) and (DO'range => ex2_esr_re )) or + (gdear_do(DO'range) and (DO'range => ex2_gdear_re )) or + (gesr_do(DO'range) and (DO'range => ex2_gesr_re )) or + (gpir_do(DO'range) and (DO'range => ex2_gpir_re )) or + (gsrr0_do(DO'range) and (DO'range => (ex2_gsrr0_re or ex2_gsrr0_re2))) or + (gsrr1_do(DO'range) and (DO'range => ex2_gsrr1_re )) or + (hacop_do(DO'range) and (DO'range => ex2_hacop_re )) or + (mcsr_do(DO'range) and (DO'range => ex2_mcsr_re )) or + (mcsrr0_do(DO'range) and (DO'range => (ex2_mcsrr0_re or ex2_mcsrr0_re2))) or + (mcsrr1_do(DO'range) and (DO'range => ex2_mcsrr1_re )) or + (msr_do(DO'range) and (DO'range => ex2_is_mfmsr )) or + (msrp_do(DO'range) and (DO'range => ex2_msrp_re )) or + (srr0_do(DO'range) and (DO'range => (ex2_srr0_re or ex2_srr0_re2))) or + (srr1_do(DO'range) and (DO'range => ex2_srr1_re )) or + (tcr_do(DO'range) and (DO'range => ex2_tcr_re )) or + (tsr_do(DO'range) and (DO'range => ex2_tsr_re )) or + (udec_do(DO'range) and (DO'range => ex2_udec_re )) or + (xucr1_do(DO'range) and (DO'range => ex2_xucr1_re )); +end generate; + +tspr_cspr_ex3_tspr_rt <= ex3_tspr_rt_q and fanout(ex3_tid_rpwr_q,regsize); + +ex2_pir_rdec <= (ex2_instr(11 to 20) = "1111001000"); +ex2_acop_rdec <= (ex2_instr(11 to 20) = "1111100000"); +ex2_ccr3_rdec <= (ex2_instr(11 to 20) = "1010111111"); +ex2_csrr0_rdec <= (ex2_instr(11 to 20) = "1101000001"); +ex2_csrr1_rdec <= (ex2_instr(11 to 20) = "1101100001"); +ex2_ctr_rdec <= (ex2_instr(11 to 20) = "0100100000"); +ex2_dbcr0_rdec <= (ex2_instr(11 to 20) = "1010001001"); +ex2_dbcr1_rdec <= (ex2_instr(11 to 20) = "1010101001"); +ex2_dbcr2_rdec <= (ex2_instr(11 to 20) = "1011001001"); +ex2_dbcr3_rdec <= (ex2_instr(11 to 20) = "1000011010"); +ex2_dbsr_rdec <= (ex2_instr(11 to 20) = "1000001001"); +ex2_dear_rdec <= (ex2_instr(11 to 20) = "1110100001"); +ex2_dec_rdec <= (ex2_instr(11 to 20) = "1011000000"); +ex2_decar_rdec <= (ex2_instr(11 to 20) = "1011000001"); +ex2_epcr_rdec <= (ex2_instr(11 to 20) = "1001101001"); +ex2_esr_rdec <= (ex2_instr(11 to 20) = "1111000001"); +ex2_gdear_rdec <= (ex2_instr(11 to 20) = "1110101011"); +ex2_gesr_rdec <= (ex2_instr(11 to 20) = "1111101011"); +ex2_gpir_rdec <= (ex2_instr(11 to 20) = "1111001011"); +ex2_gsrr0_rdec <= (ex2_instr(11 to 20) = "1101001011"); +ex2_gsrr1_rdec <= (ex2_instr(11 to 20) = "1101101011"); +ex2_hacop_rdec <= (ex2_instr(11 to 20) = "1111101010"); +ex2_iar_rdec <= (ex2_instr(11 to 20) = "1001011011"); +ex2_lr_rdec <= (ex2_instr(11 to 20) = "0100000000"); +ex2_mcsr_rdec <= (ex2_instr(11 to 20) = "1110010001"); +ex2_mcsrr0_rdec <= (ex2_instr(11 to 20) = "1101010001"); +ex2_mcsrr1_rdec <= (ex2_instr(11 to 20) = "1101110001"); +ex2_msrp_rdec <= (ex2_instr(11 to 20) = "1011101001"); +ex2_srr0_rdec <= (ex2_instr(11 to 20) = "1101000000"); +ex2_srr1_rdec <= (ex2_instr(11 to 20) = "1101100000"); +ex2_tcr_rdec <= (ex2_instr(11 to 20) = "1010001010"); +ex2_tsr_rdec <= (ex2_instr(11 to 20) = "1000001010"); +ex2_udec_rdec <= udec_en and + (ex2_instr(11 to 20) = "0011010001"); +ex2_xer_rdec <= (ex2_instr(11 to 20) = "0000100000"); +ex2_xucr1_rdec <= (ex2_instr(11 to 20) = "1001111010"); +ex2_acop_re <= ex2_acop_rdec; +ex2_ccr3_re <= ex2_ccr3_rdec; +ex2_csrr0_re <= ex2_csrr0_rdec; +ex2_csrr1_re <= ex2_csrr1_rdec; +ex2_ctr_re <= ex2_ctr_rdec; +ex2_dbcr0_re <= ex2_dbcr0_rdec; +ex2_dbcr1_re <= ex2_dbcr1_rdec; +ex2_dbcr2_re <= ex2_dbcr2_rdec; +ex2_dbcr3_re <= ex2_dbcr3_rdec; +ex2_dbsr_re <= ex2_dbsr_rdec; +ex2_dear_re <= ex2_dear_rdec and not mux_msr_gs_q(0); +ex2_dec_re <= ex2_dec_rdec; +ex2_decar_re <= ex2_decar_rdec; +ex2_epcr_re <= ex2_epcr_rdec; +ex2_esr_re <= ex2_esr_rdec and not mux_msr_gs_q(0); +ex2_gdear_re <= (ex2_gdear_rdec or (ex2_dear_rdec and mux_msr_gs_q(0))); +ex2_gesr_re <= (ex2_gesr_rdec or (ex2_esr_rdec and mux_msr_gs_q(0))); +ex2_gpir_re <= (ex2_gpir_rdec or (ex2_pir_rdec and mux_msr_gs_q(0))); +ex2_gsrr0_re <= (ex2_gsrr0_rdec or (ex2_srr0_rdec and mux_msr_gs_q(0))); +ex2_gsrr1_re <= (ex2_gsrr1_rdec or (ex2_srr1_rdec and mux_msr_gs_q(0))); +ex2_hacop_re <= ex2_hacop_rdec; +ex2_iar_re <= ex2_iar_rdec; +ex2_lr_re <= ex2_lr_rdec; +ex2_mcsr_re <= ex2_mcsr_rdec; +ex2_mcsrr0_re <= ex2_mcsrr0_rdec; +ex2_mcsrr1_re <= ex2_mcsrr1_rdec; +ex2_msrp_re <= ex2_msrp_rdec; +ex2_srr0_re <= ex2_srr0_rdec and not mux_msr_gs_q(0); +ex2_srr1_re <= ex2_srr1_rdec and not mux_msr_gs_q(0); +ex2_tcr_re <= ex2_tcr_rdec; +ex2_tsr_re <= ex2_tsr_rdec; +ex2_udec_re <= ex2_udec_rdec; +ex2_xer_re <= ex2_xer_rdec; +ex2_xucr1_re <= ex2_xucr1_rdec; + +ex2_acop_wdec <= ex2_acop_rdec; +ex2_ccr3_wdec <= ex2_ccr3_rdec; +ex2_csrr0_wdec <= ex2_csrr0_rdec; +ex2_csrr1_wdec <= ex2_csrr1_rdec; +ex2_ctr_wdec <= ex2_ctr_rdec; +ex2_dbcr0_wdec <= ex2_dbcr0_rdec; +ex2_dbcr1_wdec <= ex2_dbcr1_rdec; +ex2_dbcr2_wdec <= ex2_dbcr2_rdec; +ex2_dbcr3_wdec <= ex2_dbcr3_rdec; +ex2_dbsr_wdec <= ex2_dbsr_rdec; +ex2_dbsrwr_wdec <= (ex2_instr(11 to 20) = "1001001001"); +ex2_dear_wdec <= ex2_dear_rdec; +ex2_dec_wdec <= ex2_dec_rdec; +ex2_decar_wdec <= ex2_decar_rdec; +ex2_epcr_wdec <= ex2_epcr_rdec; +ex2_esr_wdec <= ex2_esr_rdec; +ex2_gdear_wdec <= ex2_gdear_rdec; +ex2_gesr_wdec <= ex2_gesr_rdec; +ex2_gpir_wdec <= (ex2_instr(11 to 20) = "1111001011"); +ex2_gsrr0_wdec <= ex2_gsrr0_rdec; +ex2_gsrr1_wdec <= ex2_gsrr1_rdec; +ex2_hacop_wdec <= (ex2_instr(11 to 20) = "1111101010"); +ex2_iar_wdec <= ex2_iar_rdec; +ex2_lr_wdec <= ex2_lr_rdec; +ex2_mcsr_wdec <= ex2_mcsr_rdec; +ex2_mcsrr0_wdec <= ex2_mcsrr0_rdec; +ex2_mcsrr1_wdec <= ex2_mcsrr1_rdec; +ex2_msrp_wdec <= ex2_msrp_rdec; +ex2_srr0_wdec <= ex2_srr0_rdec; +ex2_srr1_wdec <= ex2_srr1_rdec; +ex2_tcr_wdec <= ex2_tcr_rdec; +ex2_tsr_wdec <= ex2_tsr_rdec; +ex2_udec_wdec <= udec_en and + ex2_udec_rdec; +ex2_xer_wdec <= ex2_xer_rdec; +ex2_xucr1_wdec <= ex2_xucr1_rdec; +ex2_acop_we <= ex2_acop_wdec; +ex2_ccr3_we <= ex2_ccr3_wdec; +ex2_csrr0_we <= ex2_csrr0_wdec; +ex2_csrr1_we <= ex2_csrr1_wdec; +ex2_ctr_we <= ex2_ctr_wdec; +ex2_dbcr0_we <= ex2_dbcr0_wdec; +ex2_dbcr1_we <= ex2_dbcr1_wdec; +ex2_dbcr2_we <= ex2_dbcr2_wdec; +ex2_dbcr3_we <= ex2_dbcr3_wdec; +ex2_dbsr_we <= ex2_dbsr_wdec; +ex2_dbsrwr_we <= ex2_dbsrwr_wdec; +ex2_dear_we <= ex2_dear_wdec and not mux_msr_gs_q(1); +ex2_dec_we <= ex2_dec_wdec; +ex2_decar_we <= ex2_decar_wdec; +ex2_epcr_we <= ex2_epcr_wdec; +ex2_esr_we <= ex2_esr_wdec and not mux_msr_gs_q(1); +ex2_gdear_we <= (ex2_gdear_wdec or (ex2_dear_wdec and mux_msr_gs_q(1))); +ex2_gesr_we <= (ex2_gesr_wdec or (ex2_esr_wdec and mux_msr_gs_q(1))); +ex2_gpir_we <= ex2_gpir_wdec; +ex2_gsrr0_we <= (ex2_gsrr0_wdec or (ex2_srr0_wdec and mux_msr_gs_q(1))); +ex2_gsrr1_we <= (ex2_gsrr1_wdec or (ex2_srr1_wdec and mux_msr_gs_q(1))); +ex2_hacop_we <= ex2_hacop_wdec; +ex2_iar_we <= ex2_iar_wdec; +ex2_lr_we <= ex2_lr_wdec; +ex2_mcsr_we <= ex2_mcsr_wdec; +ex2_mcsrr0_we <= ex2_mcsrr0_wdec; +ex2_mcsrr1_we <= ex2_mcsrr1_wdec; +ex2_msrp_we <= ex2_msrp_wdec; +ex2_srr0_we <= ex2_srr0_wdec and not mux_msr_gs_q(1); +ex2_srr1_we <= ex2_srr1_wdec and not mux_msr_gs_q(1); +ex2_tcr_we <= ex2_tcr_wdec; +ex2_tsr_we <= ex2_tsr_wdec; +ex2_udec_we <= ex2_udec_wdec; +ex2_xer_we <= ex2_xer_wdec; +ex2_xucr1_we <= ex2_xucr1_wdec; + +ex6_acop_wdec <= (ex6_instr(11 to 20) = "1111100000"); +ex6_ccr3_wdec <= (ex6_instr(11 to 20) = "1010111111"); +ex6_csrr0_wdec <= (ex6_instr(11 to 20) = "1101000001"); +ex6_csrr1_wdec <= (ex6_instr(11 to 20) = "1101100001"); +ex6_dbcr0_wdec <= (ex6_instr(11 to 20) = "1010001001"); +ex6_dbcr1_wdec <= (ex6_instr(11 to 20) = "1010101001"); +ex6_dbsr_wdec <= (ex6_instr(11 to 20) = "1000001001"); +ex6_dbsrwr_wdec <= (ex6_instr(11 to 20) = "1001001001"); +ex6_dear_wdec <= (ex6_instr(11 to 20) = "1110100001"); +ex6_dec_wdec <= (ex6_instr(11 to 20) = "1011000000"); +ex6_decar_wdec <= (ex6_instr(11 to 20) = "1011000001"); +ex6_epcr_wdec <= (ex6_instr(11 to 20) = "1001101001"); +ex6_esr_wdec <= (ex6_instr(11 to 20) = "1111000001"); +ex6_gdear_wdec <= (ex6_instr(11 to 20) = "1110101011"); +ex6_gesr_wdec <= (ex6_instr(11 to 20) = "1111101011"); +ex6_gpir_wdec <= (ex6_instr(11 to 20) = "1111001011"); +ex6_gsrr0_wdec <= (ex6_instr(11 to 20) = "1101001011"); +ex6_gsrr1_wdec <= (ex6_instr(11 to 20) = "1101101011"); +ex6_hacop_wdec <= (ex6_instr(11 to 20) = "1111101010"); +ex6_mcsr_wdec <= (ex6_instr(11 to 20) = "1110010001"); +ex6_mcsrr0_wdec <= (ex6_instr(11 to 20) = "1101010001"); +ex6_mcsrr1_wdec <= (ex6_instr(11 to 20) = "1101110001"); +ex6_msr_wdec <= ex6_is_mtmsr; +ex6_msrp_wdec <= (ex6_instr(11 to 20) = "1011101001"); +ex6_srr0_wdec <= (ex6_instr(11 to 20) = "1101000000"); +ex6_srr1_wdec <= (ex6_instr(11 to 20) = "1101100000"); +ex6_tcr_wdec <= (ex6_instr(11 to 20) = "1010001010"); +ex6_tsr_wdec <= (ex6_instr(11 to 20) = "1000001010"); +ex6_udec_wdec <= udec_en and + (ex6_instr(11 to 20) = "0011010001"); +ex6_xucr1_wdec <= (ex6_instr(11 to 20) = "1001111010"); +ex6_acop_we <= ex6_val and ex6_is_mtspr and ex6_acop_wdec; +ex6_ccr3_we <= ex6_val and ex6_is_mtspr and ex6_ccr3_wdec; +ex6_csrr0_we <= ex6_val and ex6_is_mtspr and ex6_csrr0_wdec; +ex6_csrr1_we <= ex6_val and ex6_is_mtspr and ex6_csrr1_wdec; +ex6_dbcr0_we <= ex6_val and ex6_is_mtspr and ex6_dbcr0_wdec; +ex6_dbcr1_we <= ex6_val and ex6_is_mtspr and ex6_dbcr1_wdec; +ex6_dbsr_we <= ex6_val and ex6_is_mtspr and ex6_dbsr_wdec; +ex6_dbsrwr_we <= ex6_val and ex6_is_mtspr and ex6_dbsrwr_wdec; +ex6_dear_we <= ex6_val and ex6_is_mtspr and ex6_dear_wdec and not mux_msr_gs_q(2); +ex6_dec_we <= ex6_val and ex6_is_mtspr and ex6_dec_wdec; +ex6_decar_we <= ex6_val and ex6_is_mtspr and ex6_decar_wdec; +ex6_epcr_we <= ex6_val and ex6_is_mtspr and ex6_epcr_wdec; +ex6_esr_we <= ex6_val and ex6_is_mtspr and ex6_esr_wdec and not mux_msr_gs_q(2); +ex6_gdear_we <= ex6_val and ex6_is_mtspr and (ex6_gdear_wdec or (ex6_dear_wdec and mux_msr_gs_q(2))); +ex6_gesr_we <= ex6_val and ex6_is_mtspr and (ex6_gesr_wdec or (ex6_esr_wdec and mux_msr_gs_q(2))); +ex6_gpir_we <= ex6_val and ex6_is_mtspr and ex6_gpir_wdec; +ex6_gsrr0_we <= ex6_val and ex6_is_mtspr and (ex6_gsrr0_wdec or (ex6_srr0_wdec and mux_msr_gs_q(2))); +ex6_gsrr1_we <= ex6_val and ex6_is_mtspr and (ex6_gsrr1_wdec or (ex6_srr1_wdec and mux_msr_gs_q(2))); +ex6_hacop_we <= ex6_val and ex6_is_mtspr and ex6_hacop_wdec; +ex6_mcsr_we <= ex6_val and ex6_is_mtspr and ex6_mcsr_wdec; +ex6_mcsrr0_we <= ex6_val and ex6_is_mtspr and ex6_mcsrr0_wdec; +ex6_mcsrr1_we <= ex6_val and ex6_is_mtspr and ex6_mcsrr1_wdec; +ex6_msr_we <= ex6_val and ex6_msr_wdec; +ex6_msrp_we <= ex6_val and ex6_is_mtspr and ex6_msrp_wdec; +ex6_srr0_we <= ex6_val and ex6_is_mtspr and ex6_srr0_wdec and not mux_msr_gs_q(2); +ex6_srr1_we <= ex6_val and ex6_is_mtspr and ex6_srr1_wdec and not mux_msr_gs_q(2); +ex6_tcr_we <= ex6_val and ex6_is_mtspr and ex6_tcr_wdec; +ex6_tsr_we <= ex6_val and ex6_is_mtspr and ex6_tsr_wdec; +ex6_udec_we <= ex6_val and ex6_is_mtspr and ex6_udec_wdec; +ex6_xucr1_we <= ex6_val and ex6_is_mtspr and ex6_xucr1_wdec; + +ill_spr_00 : if a2mode = 0 and hvmode = 0 generate +tspr_cspr_illeg_mtspr_b <= + ex2_ccr3_wdec or ex2_ctr_wdec or ex2_dbcr0_wdec + or ex2_dbcr1_wdec or ex2_dbcr3_wdec or ex2_dbsr_wdec + or ex2_dear_wdec or ex2_dec_wdec or ex2_esr_wdec + or ex2_iar_wdec or ex2_lr_wdec or ex2_srr0_wdec + or ex2_srr1_wdec or ex2_xer_wdec or ex2_xucr1_wdec ; + +tspr_cspr_illeg_mfspr_b <= + ex2_ccr3_rdec or ex2_ctr_rdec or ex2_dbcr0_rdec + or ex2_dbcr1_rdec or ex2_dbcr3_rdec or ex2_dbsr_rdec + or ex2_dear_rdec or ex2_dec_rdec or ex2_esr_rdec + or ex2_iar_rdec or ex2_lr_rdec or ex2_srr0_rdec + or ex2_srr1_rdec or ex2_xer_rdec or ex2_xucr1_rdec ; + +tspr_cspr_hypv_mtspr <= + ex2_ccr3_we or ex2_dbcr0_we or ex2_dbcr1_we + or ex2_dbcr3_we or ex2_dbsr_we or ex2_dec_we + or ex2_iar_we or ex2_xucr1_we ; + +tspr_cspr_hypv_mfspr <= + ex2_ccr3_re or ex2_dbcr0_re or ex2_dbcr1_re + or ex2_dbcr3_re or ex2_dbsr_re or ex2_dec_re + or ex2_iar_re or ex2_xucr1_re ; + +end generate; +ill_spr_01 : if a2mode = 0 and hvmode = 1 generate +tspr_cspr_illeg_mtspr_b <= + ex2_ccr3_wdec or ex2_ctr_wdec or ex2_dbcr0_wdec + or ex2_dbcr1_wdec or ex2_dbcr3_wdec or ex2_dbsr_wdec + or ex2_dbsrwr_wdec or ex2_dear_wdec or ex2_dec_wdec + or ex2_epcr_wdec or ex2_esr_wdec or ex2_gdear_wdec + or ex2_gesr_wdec or ex2_gpir_wdec or ex2_gsrr0_wdec + or ex2_gsrr1_wdec or ex2_hacop_wdec or ex2_iar_wdec + or ex2_lr_wdec or ex2_msrp_wdec or ex2_srr0_wdec + or ex2_srr1_wdec or ex2_xer_wdec or ex2_xucr1_wdec ; + +tspr_cspr_illeg_mfspr_b <= + ex2_ccr3_rdec or ex2_ctr_rdec or ex2_dbcr0_rdec + or ex2_dbcr1_rdec or ex2_dbcr3_rdec or ex2_dbsr_rdec + or ex2_dear_rdec or ex2_dec_rdec or ex2_epcr_rdec + or ex2_esr_rdec or ex2_gdear_rdec or ex2_gesr_rdec + or ex2_gpir_rdec or ex2_gsrr0_rdec or ex2_gsrr1_rdec + or ex2_hacop_rdec or ex2_iar_rdec or ex2_lr_rdec + or ex2_msrp_rdec or ex2_srr0_rdec or ex2_srr1_rdec + or ex2_xer_rdec or ex2_xucr1_rdec ; + +tspr_cspr_hypv_mtspr <= + ex2_ccr3_we or ex2_dbcr0_we or ex2_dbcr1_we + or ex2_dbcr3_we or ex2_dbsr_we or ex2_dbsrwr_we + or ex2_dec_we or ex2_epcr_we or ex2_gpir_we + or ex2_hacop_we or ex2_iar_we or ex2_msrp_we + or ex2_xucr1_we ; + +tspr_cspr_hypv_mfspr <= + ex2_ccr3_re or ex2_dbcr0_re or ex2_dbcr1_re + or ex2_dbcr3_re or ex2_dbsr_re or ex2_dec_re + or ex2_epcr_re or ex2_iar_re or ex2_msrp_re + or ex2_xucr1_re ; + +end generate; +ill_spr_10 : if a2mode = 1 and hvmode = 0 generate +tspr_cspr_illeg_mtspr_b <= + ex2_acop_wdec or ex2_ccr3_wdec or ex2_csrr0_wdec + or ex2_csrr1_wdec or ex2_ctr_wdec or ex2_dbcr0_wdec + or ex2_dbcr1_wdec or ex2_dbcr2_wdec or ex2_dbcr3_wdec + or ex2_dbsr_wdec or ex2_dear_wdec or ex2_dec_wdec + or ex2_decar_wdec or ex2_esr_wdec or ex2_iar_wdec + or ex2_lr_wdec or ex2_mcsr_wdec or ex2_mcsrr0_wdec + or ex2_mcsrr1_wdec or ex2_srr0_wdec or ex2_srr1_wdec + or ex2_tcr_wdec or ex2_tsr_wdec or ex2_udec_wdec + or ex2_xer_wdec or ex2_xucr1_wdec ; + +tspr_cspr_illeg_mfspr_b <= + ex2_acop_rdec or ex2_ccr3_rdec or ex2_csrr0_rdec + or ex2_csrr1_rdec or ex2_ctr_rdec or ex2_dbcr0_rdec + or ex2_dbcr1_rdec or ex2_dbcr2_rdec or ex2_dbcr3_rdec + or ex2_dbsr_rdec or ex2_dear_rdec or ex2_dec_rdec + or ex2_decar_rdec or ex2_esr_rdec or ex2_iar_rdec + or ex2_lr_rdec or ex2_mcsr_rdec or ex2_mcsrr0_rdec + or ex2_mcsrr1_rdec or ex2_srr0_rdec or ex2_srr1_rdec + or ex2_tcr_rdec or ex2_tsr_rdec or ex2_udec_rdec + or ex2_xer_rdec or ex2_xucr1_rdec ; + +tspr_cspr_hypv_mtspr <= + ex2_ccr3_we or ex2_csrr0_we or ex2_csrr1_we + or ex2_dbcr0_we or ex2_dbcr1_we or ex2_dbcr2_we + or ex2_dbcr3_we or ex2_dbsr_we or ex2_dec_we + or ex2_decar_we or ex2_iar_we or ex2_mcsr_we + or ex2_mcsrr0_we or ex2_mcsrr1_we or ex2_tcr_we + or ex2_tsr_we or ex2_xucr1_we ; + +tspr_cspr_hypv_mfspr <= + ex2_ccr3_re or ex2_csrr0_re or ex2_csrr1_re + or ex2_dbcr0_re or ex2_dbcr1_re or ex2_dbcr2_re + or ex2_dbcr3_re or ex2_dbsr_re or ex2_dec_re + or ex2_decar_re or ex2_iar_re or ex2_mcsr_re + or ex2_mcsrr0_re or ex2_mcsrr1_re or ex2_tcr_re + or ex2_tsr_re or ex2_xucr1_re ; + +end generate; +ill_spr_11 : if a2mode = 1 and hvmode = 1 generate +tspr_cspr_illeg_mtspr_b <= + ex2_acop_wdec or ex2_ccr3_wdec or ex2_csrr0_wdec + or ex2_csrr1_wdec or ex2_ctr_wdec or ex2_dbcr0_wdec + or ex2_dbcr1_wdec or ex2_dbcr2_wdec or ex2_dbcr3_wdec + or ex2_dbsr_wdec or ex2_dbsrwr_wdec or ex2_dear_wdec + or ex2_dec_wdec or ex2_decar_wdec or ex2_epcr_wdec + or ex2_esr_wdec or ex2_gdear_wdec or ex2_gesr_wdec + or ex2_gpir_wdec or ex2_gsrr0_wdec or ex2_gsrr1_wdec + or ex2_hacop_wdec or ex2_iar_wdec or ex2_lr_wdec + or ex2_mcsr_wdec or ex2_mcsrr0_wdec or ex2_mcsrr1_wdec + or ex2_msrp_wdec or ex2_srr0_wdec or ex2_srr1_wdec + or ex2_tcr_wdec or ex2_tsr_wdec or ex2_udec_wdec + or ex2_xer_wdec or ex2_xucr1_wdec ; + +tspr_cspr_illeg_mfspr_b <= + ex2_acop_rdec or ex2_ccr3_rdec or ex2_csrr0_rdec + or ex2_csrr1_rdec or ex2_ctr_rdec or ex2_dbcr0_rdec + or ex2_dbcr1_rdec or ex2_dbcr2_rdec or ex2_dbcr3_rdec + or ex2_dbsr_rdec or ex2_dear_rdec or ex2_dec_rdec + or ex2_decar_rdec or ex2_epcr_rdec or ex2_esr_rdec + or ex2_gdear_rdec or ex2_gesr_rdec or ex2_gpir_rdec + or ex2_gsrr0_rdec or ex2_gsrr1_rdec or ex2_hacop_rdec + or ex2_iar_rdec or ex2_lr_rdec or ex2_mcsr_rdec + or ex2_mcsrr0_rdec or ex2_mcsrr1_rdec or ex2_msrp_rdec + or ex2_srr0_rdec or ex2_srr1_rdec or ex2_tcr_rdec + or ex2_tsr_rdec or ex2_udec_rdec or ex2_xer_rdec + or ex2_xucr1_rdec ; + +tspr_cspr_hypv_mtspr <= + ex2_ccr3_we or ex2_csrr0_we or ex2_csrr1_we + or ex2_dbcr0_we or ex2_dbcr1_we or ex2_dbcr2_we + or ex2_dbcr3_we or ex2_dbsr_we or ex2_dbsrwr_we + or ex2_dec_we or ex2_decar_we or ex2_epcr_we + or ex2_gpir_we or ex2_hacop_we or ex2_iar_we + or ex2_mcsr_we or ex2_mcsrr0_we or ex2_mcsrr1_we + or ex2_msrp_we or ex2_tcr_we or ex2_tsr_we + or ex2_xucr1_we ; + +tspr_cspr_hypv_mfspr <= + ex2_ccr3_re or ex2_csrr0_re or ex2_csrr1_re + or ex2_dbcr0_re or ex2_dbcr1_re or ex2_dbcr2_re + or ex2_dbcr3_re or ex2_dbsr_re or ex2_dec_re + or ex2_decar_re or ex2_epcr_re or ex2_iar_re + or ex2_mcsr_re or ex2_mcsrr0_re or ex2_mcsrr1_re + or ex2_msrp_re or ex2_tcr_re or ex2_tsr_re + or ex2_xucr1_re ; + +end generate; + +spr_acop_ct <= acop_q(32 to 63); +spr_ccr3_en_eepri <= ccr3_q(62); +spr_ccr3_si <= ccr3_q(63); +spr_dbcr0_idm <= dbcr0_q(43); +spr_dbcr0_rst <= dbcr0_q(44 to 45); +spr_dbcr0_icmp <= dbcr0_q(46); +spr_dbcr0_brt <= dbcr0_q(47); +spr_dbcr0_irpt <= dbcr0_q(48); +spr_dbcr0_trap <= dbcr0_q(49); +spr_dbcr0_iac1 <= dbcr0_q(50); +spr_dbcr0_iac2 <= dbcr0_q(51); +spr_dbcr0_iac3 <= dbcr0_q(52); +spr_dbcr0_iac4 <= dbcr0_q(53); +spr_dbcr0_dac1 <= dbcr0_q(54 to 55); +spr_dbcr0_dac2 <= dbcr0_q(56 to 57); +spr_dbcr0_ret <= dbcr0_q(58); +spr_dbcr0_dac3 <= dbcr0_q(59 to 60); +spr_dbcr0_dac4 <= dbcr0_q(61 to 62); +spr_dbcr0_ft <= dbcr0_q(63); +spr_dbcr1_iac1us <= dbcr1_q(46 to 47); +spr_dbcr1_iac1er <= dbcr1_q(48 to 49); +spr_dbcr1_iac2us <= dbcr1_q(50 to 51); +spr_dbcr1_iac2er <= dbcr1_q(52 to 53); +spr_dbcr1_iac12m <= dbcr1_q(54); +spr_dbcr1_iac3us <= dbcr1_q(55 to 56); +spr_dbcr1_iac3er <= dbcr1_q(57 to 58); +spr_dbcr1_iac4us <= dbcr1_q(59 to 60); +spr_dbcr1_iac4er <= dbcr1_q(61 to 62); +spr_dbcr1_iac34m <= dbcr1_q(63); +spr_dbsr_ide <= dbsr_q(44); +spr_epcr_extgs <= epcr_q(54); +spr_epcr_dtlbgs <= epcr_q(55); +spr_epcr_itlbgs <= epcr_q(56); +spr_epcr_dsigs <= epcr_q(57); +spr_epcr_isigs <= epcr_q(58); +spr_epcr_duvd <= epcr_q(59); +spr_epcr_icm <= epcr_q(60); +spr_epcr_gicm <= epcr_q(61); +spr_epcr_dgtmi <= epcr_q(62); +xu_mm_spr_epcr_dmiuh <= epcr_q(63); +spr_hacop_ct <= hacop_q(32 to 63); +spr_msr_cm <= msr_q(50); +spr_msr_gs <= msr_q(51); +spr_msr_ucle <= msr_q(52); +spr_msr_spv <= msr_q(53); +spr_msr_ce <= msr_q(54); +spr_msr_ee <= msr_q(55); +spr_msr_pr <= msr_q(56); +spr_msr_fp <= msr_q(57); +spr_msr_me <= msr_q(58); +spr_msr_fe0 <= msr_q(59); +spr_msr_de <= msr_q(60); +spr_msr_fe1 <= msr_q(61); +spr_msr_is <= msr_q(62); +spr_msr_ds <= msr_q(63); +spr_msrp_uclep <= msrp_q(62); +spr_tcr_wp <= tcr_q(52 to 53); +spr_tcr_wrc <= tcr_q(54 to 55); +spr_tcr_wie <= tcr_q(56); +spr_tcr_die <= tcr_q(57); +spr_tcr_fp <= tcr_q(58 to 59); +spr_tcr_fie <= tcr_q(60); +spr_tcr_are <= tcr_q(61); +spr_tcr_udie <= tcr_q(62); +spr_tcr_ud <= tcr_q(63); +spr_tsr_enw <= tsr_q(59); +spr_tsr_wis <= tsr_q(60); +spr_tsr_dis <= tsr_q(61); +spr_tsr_fis <= tsr_q(62); +spr_tsr_udis <= tsr_q(63); +spr_xucr1_ll_tb_sel <= xucr1_q(59 to 61); +spr_xucr1_ll_sel <= xucr1_q(62); +spr_xucr1_ll_en <= xucr1_q(63); + +ex6_acop_di <= ex6_spr_wd(32 to 63) ; +acop_do <= tidn(0 to 0) & + tidn(0 to 31) & + acop_q(32 to 63) ; +ex6_ccr3_di <= ex6_spr_wd(62 to 62) & + ex6_spr_wd(63 to 63) ; +ccr3_do <= tidn(0 to 0) & + tidn(0 to 31) & + tidn(32 to 61) & + ccr3_q(62 to 62) & + ccr3_q(63 to 63) ; +ex6_csrr0_di <= ex6_spr_wd(62-(eff_ifar) to 61) ; +csrr0_do <= tidn(0 to 62-(eff_ifar)) & + csrr0_q(64-(eff_ifar) to 63) & + tidn(62 to 63) ; +ex6_csrr1_di <= ex6_spr_wd(32 to 32) & + ex6_spr_wd(35 to 35) & + ex6_spr_wd(37 to 37) & + ex6_spr_wd(38 to 38) & + ex6_spr_wd(46 to 46) & + ex6_spr_wd(48 to 48) & + ex6_spr_wd(49 to 49) & + ex6_spr_wd(50 to 50) & + ex6_spr_wd(51 to 51) & + ex6_spr_wd(52 to 52) & + ex6_spr_wd(54 to 54) & + ex6_spr_wd(55 to 55) & + ex6_spr_wd(58 to 58) & + ex6_spr_wd(59 to 59) ; +csrr1_do <= tidn(0 to 0) & + tidn(0 to 31) & + csrr1_q(50 to 50) & + tidn(33 to 34) & + csrr1_q(51 to 51) & + tidn(36 to 36) & + csrr1_q(52 to 52) & + csrr1_q(53 to 53) & + tidn(39 to 45) & + csrr1_q(54 to 54) & + tidn(47 to 47) & + csrr1_q(55 to 55) & + csrr1_q(56 to 56) & + csrr1_q(57 to 57) & + csrr1_q(58 to 58) & + csrr1_q(59 to 59) & + tidn(53 to 53) & + csrr1_q(60 to 60) & + csrr1_q(61 to 61) & + tidn(56 to 57) & + csrr1_q(62 to 62) & + csrr1_q(63 to 63) & + tidn(60 to 63) ; +ex6_dbcr0_di <= ex6_spr_wd(33 to 33) & + ex6_spr_wd(34 to 35) & + ex6_spr_wd(36 to 36) & + ex6_spr_wd(37 to 37) & + ex6_spr_wd(38 to 38) & + ex6_spr_wd(39 to 39) & + ex6_spr_wd(40 to 40) & + ex6_spr_wd(41 to 41) & + ex6_spr_wd(42 to 42) & + ex6_spr_wd(43 to 43) & + ex6_spr_wd(44 to 45) & + ex6_spr_wd(46 to 47) & + ex6_spr_wd(48 to 48) & + ex6_spr_wd(59 to 60) & + ex6_spr_wd(61 to 62) & + ex6_spr_wd(63 to 63) ; +dbcr0_do <= tidn(0 to 0) & + tidn(0 to 31) & + cpl_spr_dbcr0_edm & + dbcr0_q(43 to 43) & + dbcr0_q(44 to 45) & + dbcr0_q(46 to 46) & + dbcr0_q(47 to 47) & + dbcr0_q(48 to 48) & + dbcr0_q(49 to 49) & + dbcr0_q(50 to 50) & + dbcr0_q(51 to 51) & + dbcr0_q(52 to 52) & + dbcr0_q(53 to 53) & + dbcr0_q(54 to 55) & + dbcr0_q(56 to 57) & + dbcr0_q(58 to 58) & + tidn(49 to 58) & + dbcr0_q(59 to 60) & + dbcr0_q(61 to 62) & + dbcr0_q(63 to 63) ; +ex6_dbcr1_di <= ex6_spr_wd(32 to 33) & + ex6_spr_wd(34 to 35) & + ex6_spr_wd(36 to 37) & + ex6_spr_wd(38 to 39) & + ex6_spr_wd(41 to 41) & + ex6_spr_wd(48 to 49) & + ex6_spr_wd(50 to 51) & + ex6_spr_wd(52 to 53) & + ex6_spr_wd(54 to 55) & + ex6_spr_wd(57 to 57) ; +dbcr1_do <= tidn(0 to 0) & + tidn(0 to 31) & + dbcr1_q(46 to 47) & + dbcr1_q(48 to 49) & + dbcr1_q(50 to 51) & + dbcr1_q(52 to 53) & + tidn(40 to 40) & + dbcr1_q(54 to 54) & + tidn(42 to 47) & + dbcr1_q(55 to 56) & + dbcr1_q(57 to 58) & + dbcr1_q(59 to 60) & + dbcr1_q(61 to 62) & + tidn(56 to 56) & + dbcr1_q(63 to 63) & + tidn(58 to 63) ; +ex6_dbsr_di <= ex6_spr_wd(32 to 32) & + ex6_spr_wd(33 to 33) & + ex6_spr_wd(36 to 36) & + ex6_spr_wd(37 to 37) & + ex6_spr_wd(38 to 38) & + ex6_spr_wd(39 to 39) & + ex6_spr_wd(40 to 40) & + ex6_spr_wd(41 to 41) & + ex6_spr_wd(42 to 42) & + ex6_spr_wd(43 to 43) & + ex6_spr_wd(44 to 44) & + ex6_spr_wd(45 to 45) & + ex6_spr_wd(46 to 46) & + ex6_spr_wd(47 to 47) & + ex6_spr_wd(48 to 48) & + ex6_spr_wd(59 to 59) & + ex6_spr_wd(60 to 60) & + ex6_spr_wd(61 to 61) & + ex6_spr_wd(62 to 62) & + ex6_spr_wd(63 to 63) ; +dbsr_do <= tidn(0 to 0) & + tidn(0 to 31) & + dbsr_q(44 to 44) & + dbsr_q(45 to 45) & + dbsr_mrr_q(0 to 1) & + dbsr_q(46 to 46) & + dbsr_q(47 to 47) & + dbsr_q(48 to 48) & + dbsr_q(49 to 49) & + dbsr_q(50 to 50) & + dbsr_q(51 to 51) & + dbsr_q(52 to 52) & + dbsr_q(53 to 53) & + dbsr_q(54 to 54) & + dbsr_q(55 to 55) & + dbsr_q(56 to 56) & + dbsr_q(57 to 57) & + dbsr_q(58 to 58) & + tidn(49 to 58) & + dbsr_q(59 to 59) & + dbsr_q(60 to 60) & + dbsr_q(61 to 61) & + dbsr_q(62 to 62) & + dbsr_q(63 to 63) ; +ex6_dear_di <= ex6_spr_wd(64-(regsize) to 63) ; +dear_do <= tidn(0 to 64-(regsize)) & + dear_q(64-(regsize) to 63) ; +ex6_dec_di <= ex6_spr_wd(32 to 63) ; +dec_do <= tidn(0 to 0) & + tidn(0 to 31) & + dec_q(32 to 63) ; +ex6_decar_di <= ex6_spr_wd(32 to 63) ; +decar_do <= tidn(0 to 0) & + tidn(0 to 31) & + decar_q(32 to 63) ; +ex6_epcr_di <= ex6_spr_wd(32 to 32) & + ex6_spr_wd(33 to 33) & + ex6_spr_wd(34 to 34) & + ex6_spr_wd(35 to 35) & + ex6_spr_wd(36 to 36) & + ex6_spr_wd(37 to 37) & + ex6_spr_wd(38 to 38) & + ex6_spr_wd(39 to 39) & + ex6_spr_wd(40 to 40) & + ex6_spr_wd(41 to 41) ; +epcr_do <= tidn(0 to 0) & + tidn(0 to 31) & + epcr_q(54 to 54) & + epcr_q(55 to 55) & + epcr_q(56 to 56) & + epcr_q(57 to 57) & + epcr_q(58 to 58) & + epcr_q(59 to 59) & + epcr_q(60 to 60) & + epcr_q(61 to 61) & + epcr_q(62 to 62) & + epcr_q(63 to 63) & + tidn(42 to 63) ; +ex6_esr_di <= ex6_spr_wd(36 to 36) & + ex6_spr_wd(37 to 37) & + ex6_spr_wd(38 to 38) & + ex6_spr_wd(39 to 39) & + ex6_spr_wd(40 to 40) & + ex6_spr_wd(42 to 42) & + ex6_spr_wd(43 to 43) & + ex6_spr_wd(44 to 44) & + ex6_spr_wd(45 to 45) & + ex6_spr_wd(46 to 46) & + ex6_spr_wd(47 to 47) & + ex6_spr_wd(49 to 49) & + ex6_spr_wd(53 to 53) & + ex6_spr_wd(54 to 54) & + ex6_spr_wd(55 to 55) & + ex6_spr_wd(56 to 56) & + ex6_spr_wd(57 to 57) ; +esr_do <= tidn(0 to 0) & + tidn(0 to 31) & + tidn(32 to 35) & + esr_q(47 to 47) & + esr_q(48 to 48) & + esr_q(49 to 49) & + esr_q(50 to 50) & + esr_q(51 to 51) & + tidn(41 to 41) & + esr_q(52 to 52) & + esr_q(53 to 53) & + esr_q(54 to 54) & + esr_q(55 to 55) & + esr_q(56 to 56) & + esr_q(57 to 57) & + tidn(48 to 48) & + esr_q(58 to 58) & + tidn(50 to 52) & + esr_q(59 to 59) & + esr_q(60 to 60) & + esr_q(61 to 61) & + esr_q(62 to 62) & + esr_q(63 to 63) & + tidn(58 to 63) ; +ex6_gdear_di <= ex6_spr_wd(64-(regsize) to 63) ; +gdear_do <= tidn(0 to 64-(regsize)) & + gdear_q(64-(regsize) to 63) ; +ex6_gesr_di <= ex6_spr_wd(36 to 36) & + ex6_spr_wd(37 to 37) & + ex6_spr_wd(38 to 38) & + ex6_spr_wd(39 to 39) & + ex6_spr_wd(40 to 40) & + ex6_spr_wd(42 to 42) & + ex6_spr_wd(43 to 43) & + ex6_spr_wd(44 to 44) & + ex6_spr_wd(45 to 45) & + ex6_spr_wd(46 to 46) & + ex6_spr_wd(47 to 47) & + ex6_spr_wd(49 to 49) & + ex6_spr_wd(53 to 53) & + ex6_spr_wd(54 to 54) & + ex6_spr_wd(55 to 55) & + ex6_spr_wd(56 to 56) & + ex6_spr_wd(57 to 57) ; +gesr_do <= tidn(0 to 0) & + tidn(0 to 31) & + tidn(32 to 35) & + gesr_q(47 to 47) & + gesr_q(48 to 48) & + gesr_q(49 to 49) & + gesr_q(50 to 50) & + gesr_q(51 to 51) & + tidn(41 to 41) & + gesr_q(52 to 52) & + gesr_q(53 to 53) & + gesr_q(54 to 54) & + gesr_q(55 to 55) & + gesr_q(56 to 56) & + gesr_q(57 to 57) & + tidn(48 to 48) & + gesr_q(58 to 58) & + tidn(50 to 52) & + gesr_q(59 to 59) & + gesr_q(60 to 60) & + gesr_q(61 to 61) & + gesr_q(62 to 62) & + gesr_q(63 to 63) & + tidn(58 to 63) ; +ex6_gpir_di <= ex6_spr_wd(32 to 49) & + ex6_spr_wd(50 to 63) ; +gpir_do <= tidn(0 to 0) & + tidn(0 to 31) & + gpir_q(32 to 49) & + gpir_q(50 to 63) ; +ex6_gsrr0_di <= ex6_spr_wd(62-(eff_ifar) to 61) ; +gsrr0_do <= tidn(0 to 62-(eff_ifar)) & + gsrr0_q(64-(eff_ifar) to 63) & + tidn(62 to 63) ; +ex6_gsrr1_di <= ex6_spr_wd(32 to 32) & + ex6_spr_wd(35 to 35) & + ex6_spr_wd(37 to 37) & + ex6_spr_wd(38 to 38) & + ex6_spr_wd(46 to 46) & + ex6_spr_wd(48 to 48) & + ex6_spr_wd(49 to 49) & + ex6_spr_wd(50 to 50) & + ex6_spr_wd(51 to 51) & + ex6_spr_wd(52 to 52) & + ex6_spr_wd(54 to 54) & + ex6_spr_wd(55 to 55) & + ex6_spr_wd(58 to 58) & + ex6_spr_wd(59 to 59) ; +gsrr1_do <= tidn(0 to 0) & + tidn(0 to 31) & + gsrr1_q(50 to 50) & + tidn(33 to 34) & + gsrr1_q(51 to 51) & + tidn(36 to 36) & + gsrr1_q(52 to 52) & + gsrr1_q(53 to 53) & + tidn(39 to 45) & + gsrr1_q(54 to 54) & + tidn(47 to 47) & + gsrr1_q(55 to 55) & + gsrr1_q(56 to 56) & + gsrr1_q(57 to 57) & + gsrr1_q(58 to 58) & + gsrr1_q(59 to 59) & + tidn(53 to 53) & + gsrr1_q(60 to 60) & + gsrr1_q(61 to 61) & + tidn(56 to 57) & + gsrr1_q(62 to 62) & + gsrr1_q(63 to 63) & + tidn(60 to 63) ; +ex6_hacop_di <= ex6_spr_wd(32 to 63) ; +hacop_do <= tidn(0 to 0) & + tidn(0 to 31) & + hacop_q(32 to 63) ; +ex6_mcsr_di <= ex6_spr_wd(48 to 48) & + ex6_spr_wd(49 to 49) & + ex6_spr_wd(50 to 50) & + ex6_spr_wd(51 to 51) & + ex6_spr_wd(52 to 52) & + ex6_spr_wd(53 to 53) & + ex6_spr_wd(54 to 54) & + ex6_spr_wd(55 to 55) & + ex6_spr_wd(56 to 56) & + ex6_spr_wd(57 to 57) & + ex6_spr_wd(58 to 58) & + ex6_spr_wd(59 to 59) & + ex6_spr_wd(60 to 60) & + ex6_spr_wd(61 to 61) & + ex6_spr_wd(62 to 62) ; +mcsr_do <= tidn(0 to 0) & + tidn(0 to 31) & + tidn(32 to 47) & + mcsr_q(49 to 49) & + mcsr_q(50 to 50) & + mcsr_q(51 to 51) & + mcsr_q(52 to 52) & + mcsr_q(53 to 53) & + mcsr_q(54 to 54) & + mcsr_q(55 to 55) & + mcsr_q(56 to 56) & + mcsr_q(57 to 57) & + mcsr_q(58 to 58) & + mcsr_q(59 to 59) & + mcsr_q(60 to 60) & + mcsr_q(61 to 61) & + mcsr_q(62 to 62) & + mcsr_q(63 to 63) & + tidn(63 to 63) ; +ex6_mcsrr0_di <= ex6_spr_wd(62-(eff_ifar) to 61) ; +mcsrr0_do <= tidn(0 to 62-(eff_ifar)) & + mcsrr0_q(64-(eff_ifar) to 63) & + tidn(62 to 63) ; +ex6_mcsrr1_di <= ex6_spr_wd(32 to 32) & + ex6_spr_wd(35 to 35) & + ex6_spr_wd(37 to 37) & + ex6_spr_wd(38 to 38) & + ex6_spr_wd(46 to 46) & + ex6_spr_wd(48 to 48) & + ex6_spr_wd(49 to 49) & + ex6_spr_wd(50 to 50) & + ex6_spr_wd(51 to 51) & + ex6_spr_wd(52 to 52) & + ex6_spr_wd(54 to 54) & + ex6_spr_wd(55 to 55) & + ex6_spr_wd(58 to 58) & + ex6_spr_wd(59 to 59) ; +mcsrr1_do <= tidn(0 to 0) & + tidn(0 to 31) & + mcsrr1_q(50 to 50) & + tidn(33 to 34) & + mcsrr1_q(51 to 51) & + tidn(36 to 36) & + mcsrr1_q(52 to 52) & + mcsrr1_q(53 to 53) & + tidn(39 to 45) & + mcsrr1_q(54 to 54) & + tidn(47 to 47) & + mcsrr1_q(55 to 55) & + mcsrr1_q(56 to 56) & + mcsrr1_q(57 to 57) & + mcsrr1_q(58 to 58) & + mcsrr1_q(59 to 59) & + tidn(53 to 53) & + mcsrr1_q(60 to 60) & + mcsrr1_q(61 to 61) & + tidn(56 to 57) & + mcsrr1_q(62 to 62) & + mcsrr1_q(63 to 63) & + tidn(60 to 63) ; +ex6_msr_di <= ex6_spr_wd(32 to 32) & + ex6_spr_wd(35 to 35) & + ex6_spr_wd(37 to 37) & + ex6_spr_wd(38 to 38) & + ex6_spr_wd(46 to 46) & + ex6_spr_wd(48 to 48) & + ex6_spr_wd(49 to 49) & + ex6_spr_wd(50 to 50) & + ex6_spr_wd(51 to 51) & + ex6_spr_wd(52 to 52) & + ex6_spr_wd(54 to 54) & + ex6_spr_wd(55 to 55) & + ex6_spr_wd(58 to 58) & + ex6_spr_wd(59 to 59) ; +msr_do <= tidn(0 to 0) & + tidn(0 to 31) & + msr_q(50 to 50) & + tidn(33 to 34) & + msr_q(51 to 51) & + tidn(36 to 36) & + msr_q(52 to 52) & + msr_q(53 to 53) & + tidn(39 to 45) & + msr_q(54 to 54) & + tidn(47 to 47) & + msr_q(55 to 55) & + msr_q(56 to 56) & + msr_q(57 to 57) & + msr_q(58 to 58) & + msr_q(59 to 59) & + tidn(53 to 53) & + msr_q(60 to 60) & + msr_q(61 to 61) & + tidn(56 to 57) & + msr_q(62 to 62) & + msr_q(63 to 63) & + tidn(60 to 63) ; +ex6_msrp_di <= ex6_spr_wd(37 to 37) & + ex6_spr_wd(54 to 54) ; +msrp_do <= tidn(0 to 0) & + tidn(0 to 31) & + tidn(32 to 36) & + msrp_q(62 to 62) & + tidn(38 to 53) & + msrp_q(63 to 63) & + tidn(55 to 63) ; +ex6_srr0_di <= ex6_spr_wd(62-(eff_ifar) to 61) ; +srr0_do <= tidn(0 to 62-(eff_ifar)) & + srr0_q(64-(eff_ifar) to 63) & + tidn(62 to 63) ; +ex6_srr1_di <= ex6_spr_wd(32 to 32) & + ex6_spr_wd(35 to 35) & + ex6_spr_wd(37 to 37) & + ex6_spr_wd(38 to 38) & + ex6_spr_wd(46 to 46) & + ex6_spr_wd(48 to 48) & + ex6_spr_wd(49 to 49) & + ex6_spr_wd(50 to 50) & + ex6_spr_wd(51 to 51) & + ex6_spr_wd(52 to 52) & + ex6_spr_wd(54 to 54) & + ex6_spr_wd(55 to 55) & + ex6_spr_wd(58 to 58) & + ex6_spr_wd(59 to 59) ; +srr1_do <= tidn(0 to 0) & + tidn(0 to 31) & + srr1_q(50 to 50) & + tidn(33 to 34) & + srr1_q(51 to 51) & + tidn(36 to 36) & + srr1_q(52 to 52) & + srr1_q(53 to 53) & + tidn(39 to 45) & + srr1_q(54 to 54) & + tidn(47 to 47) & + srr1_q(55 to 55) & + srr1_q(56 to 56) & + srr1_q(57 to 57) & + srr1_q(58 to 58) & + srr1_q(59 to 59) & + tidn(53 to 53) & + srr1_q(60 to 60) & + srr1_q(61 to 61) & + tidn(56 to 57) & + srr1_q(62 to 62) & + srr1_q(63 to 63) & + tidn(60 to 63) ; +ex6_tcr_di <= ex6_spr_wd(32 to 33) & + ex6_spr_wd(34 to 35) & + ex6_spr_wd(36 to 36) & + ex6_spr_wd(37 to 37) & + ex6_spr_wd(38 to 39) & + ex6_spr_wd(40 to 40) & + ex6_spr_wd(41 to 41) & + ex6_spr_wd(42 to 42) & + ex6_spr_wd(51 to 51) ; +tcr_do <= tidn(0 to 0) & + tidn(0 to 31) & + tcr_q(52 to 53) & + tcr_q(54 to 55) & + tcr_q(56 to 56) & + tcr_q(57 to 57) & + tcr_q(58 to 59) & + tcr_q(60 to 60) & + tcr_q(61 to 61) & + tcr_q(62 to 62) & + tidn(43 to 50) & + tcr_q(63 to 63) & + tidn(52 to 63) ; +ex6_tsr_di <= ex6_spr_wd(32 to 32) & + ex6_spr_wd(33 to 33) & + ex6_spr_wd(36 to 36) & + ex6_spr_wd(37 to 37) & + ex6_spr_wd(38 to 38) ; +tsr_do <= tidn(0 to 0) & + tidn(0 to 31) & + tsr_q(59 to 59) & + tsr_q(60 to 60) & + tsr_wrs_q(0 to 1) & + tsr_q(61 to 61) & + tsr_q(62 to 62) & + tsr_q(63 to 63) & + tidn(39 to 63) ; +ex6_udec_di <= ex6_spr_wd(32 to 63) ; +udec_do <= tidn(0 to 0) & + tidn(0 to 31) & + udec_q(32 to 63) ; +ex6_xucr1_di <= ex6_spr_wd(57 to 59) & + ex6_spr_wd(62 to 62) & + ex6_spr_wd(63 to 63) ; +xucr1_do <= tidn(0 to 0) & + tidn(0 to 31) & + tidn(32 to 56) & + xucr1_q(59 to 61) & + llstate(0 to 1) & + xucr1_q(62 to 62) & + xucr1_q(63 to 63) ; + +mark_unused(acop_do(0 to 64-regsize)); +mark_unused(ccr3_do(0 to 64-regsize)); +mark_unused(csrr0_do(0 to 64-regsize)); +mark_unused(csrr1_do(0 to 64-regsize)); +mark_unused(dbcr0_do(0 to 64-regsize)); +mark_unused(dbcr1_do(0 to 64-regsize)); +mark_unused(dbsr_do(0 to 64-regsize)); +mark_unused(dear_do(0 to 64-regsize)); +mark_unused(dec_do(0 to 64-regsize)); +mark_unused(decar_do(0 to 64-regsize)); +mark_unused(epcr_do(0 to 64-regsize)); +mark_unused(esr_do(0 to 64-regsize)); +mark_unused(gdear_do(0 to 64-regsize)); +mark_unused(gesr_do(0 to 64-regsize)); +mark_unused(gpir_do(0 to 64-regsize)); +mark_unused(gsrr0_do(0 to 64-regsize)); +mark_unused(gsrr1_do(0 to 64-regsize)); +mark_unused(hacop_do(0 to 64-regsize)); +mark_unused(mcsr_do(0 to 64-regsize)); +mark_unused(mcsrr0_do(0 to 64-regsize)); +mark_unused(mcsrr1_do(0 to 64-regsize)); +mark_unused(msr_do(0 to 64-regsize)); +mark_unused(msrp_do(0 to 64-regsize)); +mark_unused(srr0_do(0 to 64-regsize)); +mark_unused(srr1_do(0 to 64-regsize)); +mark_unused(tcr_do(0 to 64-regsize)); +mark_unused(tsr_do(0 to 64-regsize)); +mark_unused(udec_do(0 to 64-regsize)); +mark_unused(xucr1_do(0 to 64-regsize)); +mark_unused(ex2_ctr_re); +mark_unused(ex2_lr_re); +mark_unused(ex2_xer_re); +mark_unused(ex2_acop_we); +mark_unused(ex2_ctr_we); +mark_unused(ex2_dear_we); +mark_unused(ex2_dec_we); +mark_unused(ex2_esr_we); +mark_unused(ex2_gdear_we); +mark_unused(ex2_gesr_we); +mark_unused(ex2_gsrr0_we); +mark_unused(ex2_gsrr1_we); +mark_unused(ex2_lr_we); +mark_unused(ex2_srr0_we); +mark_unused(ex2_srr1_we); +mark_unused(ex2_udec_we); +mark_unused(ex2_xer_we); +mark_unused(ex2_rs2_q(48 to 49)); +mark_unused(cspr_tspr_ex1_instr(6 to 10)); +mark_unused(cspr_tspr_ex1_instr(31)); +mark_unused(ex6_gdear_di); +mark_unused(exx_act_data(1)); +mark_unused(exx_act_data(3 to 4)); +mark_unused(mchk_int_q); + +acop_latch_gen : if a2mode = 1 generate +acop_latch : tri_ser_rlmreg_p +generic map(width => acop_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => acop_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(acop_offset to acop_offset + acop_q'length-1), + scout => sov(acop_offset to acop_offset + acop_q'length-1), + din => acop_d, + dout => acop_q); +end generate; +acop_latch_tie : if a2mode = 0 generate + acop_q <= (others=>'0'); +end generate; +ccr3_latch : tri_ser_rlmreg_p +generic map(width => ccr3_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => ccr3_act, + forcee => ccfg_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => ccfg_sl_thold_0_b, + sg => sg_0, + scin => siv_ccfg(ccr3_offset_ccfg to ccr3_offset_ccfg + ccr3_q'length-1), + scout => sov_ccfg(ccr3_offset_ccfg to ccr3_offset_ccfg + ccr3_q'length-1), + din => ccr3_d, + dout => ccr3_q); +csrr0_latch_gen : if a2mode = 1 generate +csrr0_latch : tri_ser_rlmreg_p +generic map(width => csrr0_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => csrr0_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(csrr0_offset to csrr0_offset + csrr0_q'length-1), + scout => sov(csrr0_offset to csrr0_offset + csrr0_q'length-1), + din => csrr0_d, + dout => csrr0_q); +end generate; +csrr0_latch_tie : if a2mode = 0 generate + csrr0_q <= (others=>'0'); +end generate; +csrr1_latch_gen : if a2mode = 1 generate +csrr1_latch : tri_ser_rlmreg_p +generic map(width => csrr1_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => csrr1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(csrr1_offset to csrr1_offset + csrr1_q'length-1), + scout => sov(csrr1_offset to csrr1_offset + csrr1_q'length-1), + din => csrr1_d, + dout => csrr1_q); +end generate; +csrr1_latch_tie : if a2mode = 0 generate + csrr1_q <= (others=>'0'); +end generate; +dbcr0_latch : tri_ser_rlmreg_p +generic map(width => dbcr0_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => dbcr0_act, + forcee => dcfg_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => dcfg_sl_thold_0_b, + sg => sg_0, + scin => siv_dcfg(dbcr0_offset_dcfg to dbcr0_offset_dcfg + dbcr0_q'length-1), + scout => sov_dcfg(dbcr0_offset_dcfg to dbcr0_offset_dcfg + dbcr0_q'length-1), + din => dbcr0_d, + dout => dbcr0_q); +dbcr1_latch : tri_ser_rlmreg_p +generic map(width => dbcr1_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => dbcr1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dbcr1_offset to dbcr1_offset + dbcr1_q'length-1), + scout => sov(dbcr1_offset to dbcr1_offset + dbcr1_q'length-1), + din => dbcr1_d, + dout => dbcr1_q); +dbsr_latch : tri_ser_rlmreg_p +generic map(width => dbsr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => dbsr_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dbsr_offset to dbsr_offset + dbsr_q'length-1), + scout => sov(dbsr_offset to dbsr_offset + dbsr_q'length-1), + din => dbsr_d, + dout => dbsr_q); +dear_latch : tri_ser_rlmreg_p +generic map(width => dear_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => dear_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dear_offset to dear_offset + dear_q'length-1), + scout => sov(dear_offset to dear_offset + dear_q'length-1), + din => dear_d, + dout => dear_q); +dec_latch : tri_ser_rlmreg_p +generic map(width => dec_q'length, init => 2147483647, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => dec_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(dec_offset to dec_offset + dec_q'length-1), + scout => sov(dec_offset to dec_offset + dec_q'length-1), + din => dec_d, + dout => dec_q); +decar_latch_gen : if a2mode = 1 generate +decar_latch : tri_ser_rlmreg_p +generic map(width => decar_q'length, init => 2147483647, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => decar_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(decar_offset to decar_offset + decar_q'length-1), + scout => sov(decar_offset to decar_offset + decar_q'length-1), + din => decar_d, + dout => decar_q); +end generate; +decar_latch_tie : if a2mode = 0 generate + decar_q <= (others=>'0'); +end generate; +epcr_latch_gen : if hvmode = 1 generate +epcr_latch : tri_ser_rlmreg_p +generic map(width => epcr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => epcr_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(epcr_offset to epcr_offset + epcr_q'length-1), + scout => sov(epcr_offset to epcr_offset + epcr_q'length-1), + din => epcr_d, + dout => epcr_q); +end generate; +epcr_latch_tie : if hvmode = 0 generate + epcr_q <= (others=>'0'); +end generate; +esr_latch : tri_ser_rlmreg_p +generic map(width => esr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => esr_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(esr_offset to esr_offset + esr_q'length-1), + scout => sov(esr_offset to esr_offset + esr_q'length-1), + din => esr_d, + dout => esr_q); +gdear_latch_gen : if hvmode = 1 generate +gdear_latch : tri_ser_rlmreg_p +generic map(width => gdear_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => gdear_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(gdear_offset to gdear_offset + gdear_q'length-1), + scout => sov(gdear_offset to gdear_offset + gdear_q'length-1), + din => gdear_d, + dout => gdear_q); +end generate; +gdear_latch_tie : if hvmode = 0 generate + gdear_q <= (others=>'0'); +end generate; +gesr_latch_gen : if hvmode = 1 generate +gesr_latch : tri_ser_rlmreg_p +generic map(width => gesr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => gesr_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(gesr_offset to gesr_offset + gesr_q'length-1), + scout => sov(gesr_offset to gesr_offset + gesr_q'length-1), + din => gesr_d, + dout => gesr_q); +end generate; +gesr_latch_tie : if hvmode = 0 generate + gesr_q <= (others=>'0'); +end generate; +gpir_latch_gen : if hvmode = 1 generate +gpir_latch : tri_ser_rlmreg_p +generic map(width => gpir_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => gpir_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(gpir_offset to gpir_offset + gpir_q'length-1), + scout => sov(gpir_offset to gpir_offset + gpir_q'length-1), + din => gpir_d, + dout => gpir_q); +end generate; +gpir_latch_tie : if hvmode = 0 generate + gpir_q <= (others=>'0'); +end generate; +gsrr0_latch_gen : if hvmode = 1 generate +gsrr0_latch : tri_ser_rlmreg_p +generic map(width => gsrr0_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => gsrr0_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(gsrr0_offset to gsrr0_offset + gsrr0_q'length-1), + scout => sov(gsrr0_offset to gsrr0_offset + gsrr0_q'length-1), + din => gsrr0_d, + dout => gsrr0_q); +end generate; +gsrr0_latch_tie : if hvmode = 0 generate + gsrr0_q <= (others=>'0'); +end generate; +gsrr1_latch_gen : if hvmode = 1 generate +gsrr1_latch : tri_ser_rlmreg_p +generic map(width => gsrr1_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => gsrr1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(gsrr1_offset to gsrr1_offset + gsrr1_q'length-1), + scout => sov(gsrr1_offset to gsrr1_offset + gsrr1_q'length-1), + din => gsrr1_d, + dout => gsrr1_q); +end generate; +gsrr1_latch_tie : if hvmode = 0 generate + gsrr1_q <= (others=>'0'); +end generate; +hacop_latch_gen : if hvmode = 1 generate +hacop_latch : tri_ser_rlmreg_p +generic map(width => hacop_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => hacop_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(hacop_offset to hacop_offset + hacop_q'length-1), + scout => sov(hacop_offset to hacop_offset + hacop_q'length-1), + din => hacop_d, + dout => hacop_q); +end generate; +hacop_latch_tie : if hvmode = 0 generate + hacop_q <= (others=>'0'); +end generate; +mcsr_latch_gen : if a2mode = 1 generate +mcsr_latch : tri_ser_rlmreg_p +generic map(width => mcsr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => mcsr_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(mcsr_offset to mcsr_offset + mcsr_q'length-1), + scout => sov(mcsr_offset to mcsr_offset + mcsr_q'length-1), + din => mcsr_d, + dout => mcsr_q); +end generate; +mcsr_latch_tie : if a2mode = 0 generate + mcsr_q <= (others=>'0'); +end generate; +mcsrr0_latch_gen : if a2mode = 1 generate +mcsrr0_latch : tri_ser_rlmreg_p +generic map(width => mcsrr0_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => mcsrr0_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(mcsrr0_offset to mcsrr0_offset + mcsrr0_q'length-1), + scout => sov(mcsrr0_offset to mcsrr0_offset + mcsrr0_q'length-1), + din => mcsrr0_d, + dout => mcsrr0_q); +end generate; +mcsrr0_latch_tie : if a2mode = 0 generate + mcsrr0_q <= (others=>'0'); +end generate; +mcsrr1_latch_gen : if a2mode = 1 generate +mcsrr1_latch : tri_ser_rlmreg_p +generic map(width => mcsrr1_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => mcsrr1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(mcsrr1_offset to mcsrr1_offset + mcsrr1_q'length-1), + scout => sov(mcsrr1_offset to mcsrr1_offset + mcsrr1_q'length-1), + din => mcsrr1_d, + dout => mcsrr1_q); +end generate; +mcsrr1_latch_tie : if a2mode = 0 generate + mcsrr1_q <= (others=>'0'); +end generate; +msr_latch : tri_ser_rlmreg_p +generic map(width => msr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => msr_act, + forcee => ccfg_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => ccfg_sl_thold_0_b, + sg => sg_0, + scin => siv_ccfg(msr_offset_ccfg to msr_offset_ccfg + msr_q'length-1), + scout => sov_ccfg(msr_offset_ccfg to msr_offset_ccfg + msr_q'length-1), + din => msr_d, + dout => msr_q); +msrp_latch_gen : if hvmode = 1 generate +msrp_latch : tri_ser_rlmreg_p +generic map(width => msrp_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => msrp_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(msrp_offset to msrp_offset + msrp_q'length-1), + scout => sov(msrp_offset to msrp_offset + msrp_q'length-1), + din => msrp_d, + dout => msrp_q); +end generate; +msrp_latch_tie : if hvmode = 0 generate + msrp_q <= (others=>'0'); +end generate; +srr0_latch : tri_ser_rlmreg_p +generic map(width => srr0_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => srr0_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(srr0_offset to srr0_offset + srr0_q'length-1), + scout => sov(srr0_offset to srr0_offset + srr0_q'length-1), + din => srr0_d, + dout => srr0_q); +srr1_latch : tri_ser_rlmreg_p +generic map(width => srr1_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => srr1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(srr1_offset to srr1_offset + srr1_q'length-1), + scout => sov(srr1_offset to srr1_offset + srr1_q'length-1), + din => srr1_d, + dout => srr1_q); +tcr_latch_gen : if a2mode = 1 generate +tcr_latch : tri_ser_rlmreg_p +generic map(width => tcr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => tcr_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(tcr_offset to tcr_offset + tcr_q'length-1), + scout => sov(tcr_offset to tcr_offset + tcr_q'length-1), + din => tcr_d, + dout => tcr_q); +end generate; +tcr_latch_tie : if a2mode = 0 generate + tcr_q <= (others=>'0'); +end generate; +tsr_latch_gen : if a2mode = 1 generate +tsr_latch : tri_ser_rlmreg_p +generic map(width => tsr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => tsr_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(tsr_offset to tsr_offset + tsr_q'length-1), + scout => sov(tsr_offset to tsr_offset + tsr_q'length-1), + din => tsr_d, + dout => tsr_q); +end generate; +tsr_latch_tie : if a2mode = 0 generate + tsr_q <= (others=>'0'); +end generate; +udec_latch_gen : if a2mode = 1 generate +udec_latch : tri_ser_rlmreg_p +generic map(width => udec_q'length, init => 2147483647, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => udec_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(udec_offset to udec_offset + udec_q'length-1), + scout => sov(udec_offset to udec_offset + udec_q'length-1), + din => udec_d, + dout => udec_q); +end generate; +udec_latch_tie : if a2mode = 0 generate + udec_q <= (others=>'0'); +end generate; +xucr1_latch : tri_ser_rlmreg_p +generic map(width => xucr1_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => xucr1_act, + forcee => ccfg_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => ccfg_sl_thold_0_b, + sg => sg_0, + scin => siv_ccfg(xucr1_offset_ccfg to xucr1_offset_ccfg + xucr1_q'length-1), + scout => sov_ccfg(xucr1_offset_ccfg to xucr1_offset_ccfg + xucr1_q'length-1), + din => xucr1_d, + dout => xucr1_q); + + +exx_act_latch : tri_rlmreg_p + generic map (width => exx_act_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(exx_act_offset to exx_act_offset + exx_act_q'length-1), + scout => sov(exx_act_offset to exx_act_offset + exx_act_q'length-1), + din => exx_act_d, + dout => exx_act_q); +ex2_is_mfspr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_mfspr, + dout(0) => ex2_is_mfspr_q); +ex2_is_mtspr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_mtspr, + dout(0) => ex2_is_mtspr_q); +ex2_is_mfmsr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_mfmsr, + dout(0) => ex2_is_mfmsr_q); +ex2_instr_latch : tri_regk + generic map (width => ex2_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex2_instr_d, + dout => ex2_instr_q); +ex3_is_mtxer_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_mtxer_offset), + scout => sov(ex3_is_mtxer_offset), + din => ex3_is_mtxer_d, + dout => ex3_is_mtxer_q); +ex3_is_mfxer_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_mfxer_offset), + scout => sov(ex3_is_mfxer_offset), + din => ex3_is_mfxer_d, + dout => ex3_is_mfxer_q); +ex2_rfi_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_rfi_d, + dout(0) => ex2_rfi_q); +ex2_rfgi_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_rfgi_d, + dout(0) => ex2_rfgi_q); +ex2_rfci_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_rfci, + dout(0) => ex2_rfci_q); +ex2_rfmci_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_rfmci, + dout(0) => ex2_rfmci_q); +ex3_rfi_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_rfi_offset), + scout => sov(ex3_rfi_offset), + din => ex2_rfi_q , + dout => ex3_rfi_q); +ex3_rfgi_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_rfgi_offset), + scout => sov(ex3_rfgi_offset), + din => ex2_rfgi_q , + dout => ex3_rfgi_q); +ex3_rfci_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_rfci_offset), + scout => sov(ex3_rfci_offset), + din => ex2_rfci_q , + dout => ex3_rfci_q); +ex3_rfmci_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_rfmci_offset), + scout => sov(ex3_rfmci_offset), + din => ex2_rfmci_q , + dout => ex3_rfmci_q); +ex4_is_mfxer_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX4), + mpw1_b => mpw1_dc_b(DEX4), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_is_mfxer_q , + dout(0) => ex4_is_mfxer_q); +ex4_is_mtxer_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX4), + mpw1_b => mpw1_dc_b(DEX4), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_is_mtxer_q , + dout(0) => ex4_is_mtxer_q); +ex4_rfi_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX4), + mpw1_b => mpw1_dc_b(DEX4), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_rfi_q , + dout(0) => ex4_rfi_q); +ex4_rfgi_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX4), + mpw1_b => mpw1_dc_b(DEX4), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_rfgi_q , + dout(0) => ex4_rfgi_q); +ex4_rfci_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX4), + mpw1_b => mpw1_dc_b(DEX4), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_rfci_q , + dout(0) => ex4_rfci_q); +ex4_rfmci_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX4), + mpw1_b => mpw1_dc_b(DEX4), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_rfmci_q , + dout(0) => ex4_rfmci_q); +ex5_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX5), + mpw1_b => mpw1_dc_b(DEX5), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_val_offset), + scout => sov(ex5_val_offset), + din => ex4_val, + dout => ex5_val_q); +ex5_rfi_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX5), + mpw1_b => mpw1_dc_b(DEX5), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_rfi_offset), + scout => sov(ex5_rfi_offset), + din => ex4_rfi_q , + dout => ex5_rfi_q); +ex5_rfgi_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX5), + mpw1_b => mpw1_dc_b(DEX5), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_rfgi_offset), + scout => sov(ex5_rfgi_offset), + din => ex4_rfgi_q , + dout => ex5_rfgi_q); +ex5_rfci_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX5), + mpw1_b => mpw1_dc_b(DEX5), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_rfci_offset), + scout => sov(ex5_rfci_offset), + din => ex4_rfci_q , + dout => ex5_rfci_q); +ex5_rfmci_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX5), + mpw1_b => mpw1_dc_b(DEX5), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_rfmci_offset), + scout => sov(ex5_rfmci_offset), + din => ex4_rfmci_q , + dout => ex5_rfmci_q); +ex6_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_val_offset), + scout => sov(ex6_val_offset), + din => ex5_val, + dout => ex6_val_q); +ex6_rfi_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(5) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex5_rfi_q , + dout(0) => ex6_rfi_q); +ex6_rfgi_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(5) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex5_rfgi_q , + dout(0) => ex6_rfgi_q); +ex6_rfci_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(5) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex5_rfci_q , + dout(0) => ex6_rfci_q); +ex6_rfmci_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(5) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex5_rfmci_q , + dout(0) => ex6_rfmci_q); +ex6_wrtee_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(5) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => cspr_tspr_ex5_is_wrtee , + dout(0) => ex6_wrtee_q); +ex6_wrteei_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(5) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => cspr_tspr_ex5_is_wrteei , + dout(0) => ex6_wrteei_q); +ex6_is_mtmsr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(5) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => cspr_tspr_ex5_is_mtmsr , + dout(0) => ex6_is_mtmsr_q); +ex6_is_mtspr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(5) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => cspr_tspr_ex5_is_mtspr , + dout(0) => ex6_is_mtspr_q); +ex6_instr_latch : tri_regk + generic map (width => ex6_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(5) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => cspr_tspr_ex5_instr , + dout => ex6_instr_q); +ex6_int_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex5_int_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => cpl_spr_ex5_int , + dout(0) => ex6_int_q); +ex6_gint_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex5_int_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => cpl_spr_ex5_gint , + dout(0) => ex6_gint_q); +ex6_cint_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex5_int_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => cpl_spr_ex5_cint , + dout(0) => ex6_cint_q); +ex6_mcint_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex5_int_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => cpl_spr_ex5_mcint , + dout(0) => ex6_mcint_q); +ex6_nia_latch : tri_regk + generic map (width => ex6_nia_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex5_int_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => cpl_spr_ex5_nia , + dout => ex6_nia_q); +ex6_esr_latch : tri_regk + generic map (width => ex6_esr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => cpl_spr_ex5_esr_update , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => cpl_spr_ex5_esr , + dout => ex6_esr_q); +ex6_mcsr_latch : tri_regk + generic map (width => ex6_mcsr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex5_int_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => cpl_spr_ex5_mcsr , + dout => ex6_mcsr_q); +ex6_dbsr_latch : tri_regk + generic map (width => ex6_dbsr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => cpl_spr_ex5_dbsr_update , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => cpl_spr_ex5_dbsr , + dout => ex6_dbsr_q); +ex6_dear_save_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => cpl_spr_ex5_dear_save , + dout(0) => ex6_dear_save_q); +ex6_dear_update_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => cpl_spr_ex5_dear_update , + dout(0) => ex6_dear_update_q); +ex6_dear_update_saved_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => cpl_spr_ex5_dear_update_saved, + dout(0) => ex6_dear_update_saved_q); +ex6_dbsr_update_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => cpl_spr_ex5_dbsr_update , + dout(0) => ex6_dbsr_update_q); +ex6_esr_update_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => cpl_spr_ex5_esr_update , + dout(0) => ex6_esr_update_q); +ex6_srr0_dec_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => cpl_spr_ex5_srr0_dec , + dout(0) => ex6_srr0_dec_q); +ex6_force_gsrr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex5_int_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => cpl_spr_ex5_force_gsrr , + dout(0) => ex6_force_gsrr_q); +ex6_dbsr_ide_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex5_int_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => cpl_spr_ex5_dbsr_ide, + dout(0) => ex6_dbsr_ide_q); +ex6_spr_wd_latch : tri_regk + generic map (width => ex6_spr_wd_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act_data(5), + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex5_spr_wd , + dout => ex6_spr_wd_q); +fit_tb_tap_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(fit_tb_tap_offset), + scout => sov(fit_tb_tap_offset), + din => fit_tb_tap_d, + dout => fit_tb_tap_q); +wdog_tb_tap_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(wdog_tb_tap_offset), + scout => sov(wdog_tb_tap_offset), + din => wdog_tb_tap_d, + dout => wdog_tb_tap_q); +hang_pulse_latch : tri_rlmreg_p + generic map (width => hang_pulse_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(hang_pulse_offset to hang_pulse_offset + hang_pulse_q'length-1), + scout => sov(hang_pulse_offset to hang_pulse_offset + hang_pulse_q'length-1), + din => hang_pulse_d, + dout => hang_pulse_q); +lltap_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(lltap_offset), + scout => sov(lltap_offset), + din => lltap_d, + dout => lltap_q); +llcnt_latch : tri_rlmreg_p + generic map (width => llcnt_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(llcnt_offset to llcnt_offset + llcnt_q'length-1), + scout => sov(llcnt_offset to llcnt_offset + llcnt_q'length-1), + din => llcnt_d, + dout => llcnt_q); +msrovride_pr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(msrovride_pr_offset), + scout => sov(msrovride_pr_offset), + din => pc_xu_msrovride_pr , + dout => msrovride_pr_q); +msrovride_gs_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(msrovride_gs_offset), + scout => sov(msrovride_gs_offset), + din => pc_xu_msrovride_gs , + dout => msrovride_gs_q); +msrovride_de_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(msrovride_de_offset), + scout => sov(msrovride_de_offset), + din => pc_xu_msrovride_de, + dout => msrovride_de_q); +an_ac_ext_interrupt_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(an_ac_ext_interrupt_offset), + scout => sov(an_ac_ext_interrupt_offset), + din => an_ac_ext_interrupt , + dout => an_ac_ext_interrupt_q); +an_ac_crit_interrupt_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(an_ac_crit_interrupt_offset), + scout => sov(an_ac_crit_interrupt_offset), + din => an_ac_crit_interrupt , + dout => an_ac_crit_interrupt_q); +an_ac_perf_interrupt_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(an_ac_perf_interrupt_offset), + scout => sov(an_ac_perf_interrupt_offset), + din => an_ac_perf_interrupt , + dout => an_ac_perf_interrupt_q); +dear_tmp_latch : tri_rlmreg_p + generic map (width => dear_tmp_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex6_dear_save_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dear_tmp_offset to dear_tmp_offset + dear_tmp_q'length-1), + scout => sov(dear_tmp_offset to dear_tmp_offset + dear_tmp_q'length-1), + din => dear_tmp_d, + dout => dear_tmp_q); +mux_msr_gs_latch : tri_rlmreg_p + generic map (width => mux_msr_gs_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(mux_msr_gs_offset to mux_msr_gs_offset + mux_msr_gs_q'length-1), + scout => sov(mux_msr_gs_offset to mux_msr_gs_offset + mux_msr_gs_q'length-1), + din => mux_msr_gs_d, + dout => mux_msr_gs_q); +mux_msr_pr_latch : tri_rlmreg_p + generic map (width => mux_msr_pr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(mux_msr_pr_offset to mux_msr_pr_offset + mux_msr_pr_q'length-1), + scout => sov(mux_msr_pr_offset to mux_msr_pr_offset + mux_msr_pr_q'length-1), + din => mux_msr_pr_d, + dout => mux_msr_pr_q); +ex3_tspr_rt_latch : tri_rlmreg_p + generic map (width => ex3_tspr_rt_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act_data(2), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_tspr_rt_offset to ex3_tspr_rt_offset + ex3_tspr_rt_q'length-1), + scout => sov(ex3_tspr_rt_offset to ex3_tspr_rt_offset + ex3_tspr_rt_q'length-1), + din => ex3_tspr_rt_d, + dout => ex3_tspr_rt_q); +err_llbust_attempt_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(err_llbust_attempt_offset), + scout => sov(err_llbust_attempt_offset), + din => err_llbust_attempt_d, + dout => err_llbust_attempt_q); +err_llbust_failed_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(err_llbust_failed_offset), + scout => sov(err_llbust_failed_offset), + din => err_llbust_failed_d, + dout => err_llbust_failed_q); +inj_llbust_attempt_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(inj_llbust_attempt_offset), + scout => sov(inj_llbust_attempt_offset), + din => pc_xu_inj_llbust_attempt , + dout => inj_llbust_attempt_q); +inj_llbust_failed_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(inj_llbust_failed_offset), + scout => sov(inj_llbust_failed_offset), + din => pc_xu_inj_llbust_failed , + dout => inj_llbust_failed_q); +ex2_rs2_latch : tri_regk + generic map (width => ex2_rs2_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => fxu_spr_ex1_rs2 , + dout => ex2_rs2_q); +ex3_ct_latch : tri_rlmreg_p + generic map (width => ex3_ct_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_ct_offset to ex3_ct_offset + ex3_ct_q'length-1), + scout => sov(ex3_ct_offset to ex3_ct_offset + ex3_ct_q'length-1), + din => ex3_ct_d, + dout => ex3_ct_q); +an_ac_external_mchk_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(an_ac_external_mchk_offset), + scout => sov(an_ac_external_mchk_offset), + din => an_ac_external_mchk , + dout => an_ac_external_mchk_q); +mchk_int_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(mchk_int_offset), + scout => sov(mchk_int_offset), + din => mchk_int, + dout => mchk_int_q); +mchk_interrupt_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(mchk_interrupt_offset), + scout => sov(mchk_interrupt_offset), + din => mchk_interrupt, + dout => mchk_interrupt_q); +crit_interrupt_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(crit_interrupt_offset), + scout => sov(crit_interrupt_offset), + din => crit_interrupt, + dout => crit_interrupt_q); +wdog_interrupt_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(wdog_interrupt_offset), + scout => sov(wdog_interrupt_offset), + din => wdog_interrupt, + dout => wdog_interrupt_q); +dec_interrupt_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(dec_interrupt_offset), + scout => sov(dec_interrupt_offset), + din => dec_interrupt, + dout => dec_interrupt_q); +udec_interrupt_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(udec_interrupt_offset), + scout => sov(udec_interrupt_offset), + din => udec_interrupt, + dout => udec_interrupt_q); +perf_interrupt_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(perf_interrupt_offset), + scout => sov(perf_interrupt_offset), + din => perf_interrupt, + dout => perf_interrupt_q); +fit_interrupt_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(fit_interrupt_offset), + scout => sov(fit_interrupt_offset), + din => fit_interrupt, + dout => fit_interrupt_q); +ext_interrupt_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ext_interrupt_offset), + scout => sov(ext_interrupt_offset), + din => ext_interrupt, + dout => ext_interrupt_q); +single_instr_mode_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(single_instr_mode_offset), + scout => sov(single_instr_mode_offset), + din => single_instr_mode_d, + dout => single_instr_mode_q); +single_instr_mode_2_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(single_instr_mode_2_offset), + scout => sov(single_instr_mode_2_offset), + din => single_instr_mode_q , + dout => single_instr_mode_2_q); +machine_check_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(machine_check_offset), + scout => sov(machine_check_offset), + din => machine_check_d, + dout => machine_check_q); +raise_iss_pri_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(raise_iss_pri_offset), + scout => sov(raise_iss_pri_offset), + din => raise_iss_pri_d, + dout => raise_iss_pri_q); +raise_iss_pri_2_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(raise_iss_pri_2_offset), + scout => sov(raise_iss_pri_2_offset), + din => raise_iss_pri_q , + dout => raise_iss_pri_2_q); +epsc_egs_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(epsc_egs_offset), + scout => sov(epsc_egs_offset), + din => lsu_xu_spr_epsc_egs , + dout => epsc_egs_q); +epsc_epr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(epsc_epr_offset), + scout => sov(epsc_epr_offset), + din => lsu_xu_spr_epsc_epr , + dout => epsc_epr_q); +ex2_epid_instr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => dec_spr_ex1_epid_instr , + dout(0) => ex2_epid_instr_q); +pc_xu_inj_wdt_reset_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(pc_xu_inj_wdt_reset_offset), + scout => sov(pc_xu_inj_wdt_reset_offset), + din => pc_xu_inj_wdt_reset , + dout => pc_xu_inj_wdt_reset_q); +err_wdt_reset_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(err_wdt_reset_offset), + scout => sov(err_wdt_reset_offset), + din => err_wdt_reset_d, + dout => err_wdt_reset_q); +ex3_tid_rpwr_latch : tri_rlmreg_p + generic map (width => ex3_tid_rpwr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_tid_rpwr_offset to ex3_tid_rpwr_offset + ex3_tid_rpwr_q'length-1), + scout => sov(ex3_tid_rpwr_offset to ex3_tid_rpwr_offset + ex3_tid_rpwr_q'length-1), + din => ex3_tid_rpwr_d, + dout => ex3_tid_rpwr_q); +ram_mode_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ram_mode_offset), + scout => sov(ram_mode_offset), + din => cspr_tspr_ram_mode , + dout => ram_mode_q); +timebase_taps_latch : tri_rlmreg_p + generic map (width => timebase_taps_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(timebase_taps_offset to timebase_taps_offset + timebase_taps_q'length-1), + scout => sov(timebase_taps_offset to timebase_taps_offset + timebase_taps_q'length-1), + din => cspr_tspr_timebase_taps , + dout => timebase_taps_q); +dbsr_mrr_latch : tri_rlmreg_p + generic map (width => dbsr_mrr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => dbsr_mrr_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dbsr_mrr_offset to dbsr_mrr_offset + dbsr_mrr_q'length-1), + scout => sov(dbsr_mrr_offset to dbsr_mrr_offset + dbsr_mrr_q'length-1), + din => dbsr_mrr_d, + dout => dbsr_mrr_q); +tsr_wrs_latch : tri_rlmreg_p + generic map (width => tsr_wrs_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tsr_wrs_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(tsr_wrs_offset to tsr_wrs_offset + tsr_wrs_q'length-1), + scout => sov(tsr_wrs_offset to tsr_wrs_offset + tsr_wrs_q'length-1), + din => tsr_wrs_d, + dout => tsr_wrs_q); +iac1_en_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(iac1_en_offset), + scout => sov(iac1_en_offset), + din => iac1_en_d, + dout => iac1_en_q); +iac2_en_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(iac2_en_offset), + scout => sov(iac2_en_offset), + din => iac2_en_d, + dout => iac2_en_q); +iac3_en_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(iac3_en_offset), + scout => sov(iac3_en_offset), + din => iac3_en_d, + dout => iac3_en_q); +iac4_en_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(iac4_en_offset), + scout => sov(iac4_en_offset), + din => iac4_en_d, + dout => iac4_en_q); + + +spare_0_lcb: entity tri.tri_lcbnd(tri_lcbnd) + port map(vd => vdd, + gd => gnd, + act => tidn(0), + nclk => nclk, + forcee => func_sl_force, + thold_b => func_sl_thold_0_b, + delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), + mpw2_b => mpw2_dc_b, + sg => sg_0, + lclk => spare_0_lclk, + d1clk => spare_0_d1clk, + d2clk => spare_0_d2clk); +spare_0_latch : entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width => spare_0_q'length, expand_type => expand_type, btr => "NLI0001_X2_A12TH", init=>(spare_0_q'range=>'0')) + port map (vd => vdd, gd => gnd, + LCLK => spare_0_lclk, + D1CLK => spare_0_d1clk, + D2CLK => spare_0_d2clk, + SCANIN => siv(spare_0_offset to spare_0_offset + spare_0_q'length-1), + SCANOUT => sov(spare_0_offset to spare_0_offset + spare_0_q'length-1), + D => spare_0_d, + QB => spare_0_q); +spare_0_d <= not spare_0_q; +mark_unused(spare_0_q); + + +siv(0 to scan_right-1) <= sov(1 to scan_right-1) & scan_in; +scan_out <= sov(0); + + +ccfg_l : if sov_ccfg'length > 1 generate +siv_ccfg(0 to scan_right_ccfg-1) <= sov_ccfg(1 to scan_right_ccfg-1) & ccfg_scan_in; +ccfg_scan_out <= sov_ccfg(0); +end generate; +ccfg_s : if sov_ccfg'length <= 1 generate +ccfg_scan_out <= ccfg_scan_in; +sov_ccfg <= (others=>'0'); +siv_ccfg <= (others=>'0'); +end generate; + +dcfg_l : if sov_dcfg'length > 1 generate +siv_dcfg(0 to scan_right_dcfg-1) <= sov_dcfg(1 to scan_right_dcfg-1) & dcfg_scan_in; +dcfg_scan_out <= sov_dcfg(0); +end generate; +dcfg_s : if sov_dcfg'length <= 1 generate +dcfg_scan_out <= dcfg_scan_in; +sov_dcfg <= (others=>'0'); +siv_dcfg <= (others=>'0'); +end generate; + + + +end architecture xuq_spr_tspr; diff --git a/rel/build/ip_user/a2x_axi/a2x_axi/xgui/a2x_axi_v1_0.tcl b/rel/build/ip_user/a2x_axi/a2x_axi/xgui/a2x_axi_v1_0.tcl new file mode 100644 index 0000000..6964049 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/a2x_axi/xgui/a2x_axi_v1_0.tcl @@ -0,0 +1,130 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "C_M00_AXI_ADDR_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_M00_AXI_ARUSER_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_M00_AXI_AWUSER_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_M00_AXI_BUSER_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_M00_AXI_DATA_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_M00_AXI_ID_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_M00_AXI_RUSER_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_M00_AXI_WUSER_WIDTH" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.C_M00_AXI_ADDR_WIDTH { PARAM_VALUE.C_M00_AXI_ADDR_WIDTH } { + # Procedure called to update C_M00_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_M00_AXI_ADDR_WIDTH { PARAM_VALUE.C_M00_AXI_ADDR_WIDTH } { + # Procedure called to validate C_M00_AXI_ADDR_WIDTH + return true +} + +proc update_PARAM_VALUE.C_M00_AXI_ARUSER_WIDTH { PARAM_VALUE.C_M00_AXI_ARUSER_WIDTH } { + # Procedure called to update C_M00_AXI_ARUSER_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_M00_AXI_ARUSER_WIDTH { PARAM_VALUE.C_M00_AXI_ARUSER_WIDTH } { + # Procedure called to validate C_M00_AXI_ARUSER_WIDTH + return true +} + +proc update_PARAM_VALUE.C_M00_AXI_AWUSER_WIDTH { PARAM_VALUE.C_M00_AXI_AWUSER_WIDTH } { + # Procedure called to update C_M00_AXI_AWUSER_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_M00_AXI_AWUSER_WIDTH { PARAM_VALUE.C_M00_AXI_AWUSER_WIDTH } { + # Procedure called to validate C_M00_AXI_AWUSER_WIDTH + return true +} + +proc update_PARAM_VALUE.C_M00_AXI_BUSER_WIDTH { PARAM_VALUE.C_M00_AXI_BUSER_WIDTH } { + # Procedure called to update C_M00_AXI_BUSER_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_M00_AXI_BUSER_WIDTH { PARAM_VALUE.C_M00_AXI_BUSER_WIDTH } { + # Procedure called to validate C_M00_AXI_BUSER_WIDTH + return true +} + +proc update_PARAM_VALUE.C_M00_AXI_DATA_WIDTH { PARAM_VALUE.C_M00_AXI_DATA_WIDTH } { + # Procedure called to update C_M00_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_M00_AXI_DATA_WIDTH { PARAM_VALUE.C_M00_AXI_DATA_WIDTH } { + # Procedure called to validate C_M00_AXI_DATA_WIDTH + return true +} + +proc update_PARAM_VALUE.C_M00_AXI_ID_WIDTH { PARAM_VALUE.C_M00_AXI_ID_WIDTH } { + # Procedure called to update C_M00_AXI_ID_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_M00_AXI_ID_WIDTH { PARAM_VALUE.C_M00_AXI_ID_WIDTH } { + # Procedure called to validate C_M00_AXI_ID_WIDTH + return true +} + +proc update_PARAM_VALUE.C_M00_AXI_RUSER_WIDTH { PARAM_VALUE.C_M00_AXI_RUSER_WIDTH } { + # Procedure called to update C_M00_AXI_RUSER_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_M00_AXI_RUSER_WIDTH { PARAM_VALUE.C_M00_AXI_RUSER_WIDTH } { + # Procedure called to validate C_M00_AXI_RUSER_WIDTH + return true +} + +proc update_PARAM_VALUE.C_M00_AXI_WUSER_WIDTH { PARAM_VALUE.C_M00_AXI_WUSER_WIDTH } { + # Procedure called to update C_M00_AXI_WUSER_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_M00_AXI_WUSER_WIDTH { PARAM_VALUE.C_M00_AXI_WUSER_WIDTH } { + # Procedure called to validate C_M00_AXI_WUSER_WIDTH + return true +} + + +proc update_MODELPARAM_VALUE.C_M00_AXI_ID_WIDTH { MODELPARAM_VALUE.C_M00_AXI_ID_WIDTH PARAM_VALUE.C_M00_AXI_ID_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_M00_AXI_ID_WIDTH}] ${MODELPARAM_VALUE.C_M00_AXI_ID_WIDTH} +} + +proc update_MODELPARAM_VALUE.C_M00_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_M00_AXI_ADDR_WIDTH PARAM_VALUE.C_M00_AXI_ADDR_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_M00_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_M00_AXI_ADDR_WIDTH} +} + +proc update_MODELPARAM_VALUE.C_M00_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_M00_AXI_DATA_WIDTH PARAM_VALUE.C_M00_AXI_DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_M00_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_M00_AXI_DATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.C_M00_AXI_AWUSER_WIDTH { MODELPARAM_VALUE.C_M00_AXI_AWUSER_WIDTH PARAM_VALUE.C_M00_AXI_AWUSER_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_M00_AXI_AWUSER_WIDTH}] ${MODELPARAM_VALUE.C_M00_AXI_AWUSER_WIDTH} +} + +proc update_MODELPARAM_VALUE.C_M00_AXI_ARUSER_WIDTH { MODELPARAM_VALUE.C_M00_AXI_ARUSER_WIDTH PARAM_VALUE.C_M00_AXI_ARUSER_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_M00_AXI_ARUSER_WIDTH}] ${MODELPARAM_VALUE.C_M00_AXI_ARUSER_WIDTH} +} + +proc update_MODELPARAM_VALUE.C_M00_AXI_WUSER_WIDTH { MODELPARAM_VALUE.C_M00_AXI_WUSER_WIDTH PARAM_VALUE.C_M00_AXI_WUSER_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_M00_AXI_WUSER_WIDTH}] ${MODELPARAM_VALUE.C_M00_AXI_WUSER_WIDTH} +} + +proc update_MODELPARAM_VALUE.C_M00_AXI_RUSER_WIDTH { MODELPARAM_VALUE.C_M00_AXI_RUSER_WIDTH PARAM_VALUE.C_M00_AXI_RUSER_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_M00_AXI_RUSER_WIDTH}] ${MODELPARAM_VALUE.C_M00_AXI_RUSER_WIDTH} +} + +proc update_MODELPARAM_VALUE.C_M00_AXI_BUSER_WIDTH { MODELPARAM_VALUE.C_M00_AXI_BUSER_WIDTH PARAM_VALUE.C_M00_AXI_BUSER_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_M00_AXI_BUSER_WIDTH}] ${MODELPARAM_VALUE.C_M00_AXI_BUSER_WIDTH} +} + diff --git a/rel/build/ip_user/a2x_axi/readme.md b/rel/build/ip_user/a2x_axi/readme.md new file mode 100644 index 0000000..c8bbaf1 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/readme.md @@ -0,0 +1,8 @@ +# create IP: a2x_axi + +``` +$VIVADO -mode tcl -source tcl/create_ip_a2x_axi.tcl +rm -r ../../ip_repo/a2x_axi +cp -r a2x_axi ../../ip_repo +``` + diff --git a/rel/build/ip_user/a2x_axi/tcl b/rel/build/ip_user/a2x_axi/tcl new file mode 120000 index 0000000..f528630 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/tcl @@ -0,0 +1 @@ +../../tcl \ No newline at end of file diff --git a/rel/build/ip_user/a2x_axi/vhdl b/rel/build/ip_user/a2x_axi/vhdl new file mode 120000 index 0000000..655de1a --- /dev/null +++ b/rel/build/ip_user/a2x_axi/vhdl @@ -0,0 +1 @@ +../../../src/vhdl \ No newline at end of file diff --git a/rel/build/ip_user/a2x_axi/xdc b/rel/build/ip_user/a2x_axi/xdc new file mode 120000 index 0000000..3add899 --- /dev/null +++ b/rel/build/ip_user/a2x_axi/xdc @@ -0,0 +1 @@ +../../xdc \ No newline at end of file diff --git a/rel/build/ip_user/a2x_axi_reg/readme.md b/rel/build/ip_user/a2x_axi_reg/readme.md new file mode 100644 index 0000000..51fd26c --- /dev/null +++ b/rel/build/ip_user/a2x_axi_reg/readme.md @@ -0,0 +1,8 @@ +# create IP: a2x_axi_reg + +``` +$VIVADO -mode tcl -source tcl/create_ip_a2x_axi_reg.tcl +rm -r ../../ip_repo/a2x_axi_reg +cp -r a2x_axi_reg ../../ip_repo +``` + diff --git a/rel/build/ip_user/a2x_axi_reg/tcl b/rel/build/ip_user/a2x_axi_reg/tcl new file mode 120000 index 0000000..f528630 --- /dev/null +++ b/rel/build/ip_user/a2x_axi_reg/tcl @@ -0,0 +1 @@ +../../tcl \ No newline at end of file diff --git a/rel/build/ip_user/a2x_axi_reg/vhdl b/rel/build/ip_user/a2x_axi_reg/vhdl new file mode 120000 index 0000000..655de1a --- /dev/null +++ b/rel/build/ip_user/a2x_axi_reg/vhdl @@ -0,0 +1 @@ +../../../src/vhdl \ No newline at end of file diff --git a/rel/build/ip_user/a2x_axi_reg/xdc b/rel/build/ip_user/a2x_axi_reg/xdc new file mode 120000 index 0000000..3add899 --- /dev/null +++ b/rel/build/ip_user/a2x_axi_reg/xdc @@ -0,0 +1 @@ +../../xdc \ No newline at end of file diff --git a/rel/build/ip_user/a2x_dbug/readme.md b/rel/build/ip_user/a2x_dbug/readme.md new file mode 100644 index 0000000..7a947af --- /dev/null +++ b/rel/build/ip_user/a2x_dbug/readme.md @@ -0,0 +1,8 @@ +# create IP: a2x_dbug + +``` +$VIVADO -mode tcl -source tcl/create_ip_a2x_dbug.tcl +rm -r ../../ip_repo/a2x_dbug +cp -r a2x_dbug ../../ip_repo +``` + diff --git a/rel/build/ip_user/a2x_dbug/tcl b/rel/build/ip_user/a2x_dbug/tcl new file mode 120000 index 0000000..f528630 --- /dev/null +++ b/rel/build/ip_user/a2x_dbug/tcl @@ -0,0 +1 @@ +../../tcl \ No newline at end of file diff --git a/rel/build/ip_user/a2x_dbug/vhdl b/rel/build/ip_user/a2x_dbug/vhdl new file mode 120000 index 0000000..655de1a --- /dev/null +++ b/rel/build/ip_user/a2x_dbug/vhdl @@ -0,0 +1 @@ +../../../src/vhdl \ No newline at end of file diff --git a/rel/build/ip_user/a2x_dbug/xdc b/rel/build/ip_user/a2x_dbug/xdc new file mode 120000 index 0000000..3add899 --- /dev/null +++ b/rel/build/ip_user/a2x_dbug/xdc @@ -0,0 +1 @@ +../../xdc \ No newline at end of file diff --git a/rel/build/ip_user/a2x_reset/readme.md b/rel/build/ip_user/a2x_reset/readme.md new file mode 100644 index 0000000..4d10d60 --- /dev/null +++ b/rel/build/ip_user/a2x_reset/readme.md @@ -0,0 +1,8 @@ +# create IP: a2x_reset + +``` +$VIVADO -mode tcl -source tcl/create_ip_a2x_reset.tcl +rm -r ../../ip_repo/a2x_reset +cp -r a2x_reset ../../ip_repo +``` + diff --git a/rel/build/ip_user/a2x_reset/tcl b/rel/build/ip_user/a2x_reset/tcl new file mode 120000 index 0000000..f528630 --- /dev/null +++ b/rel/build/ip_user/a2x_reset/tcl @@ -0,0 +1 @@ +../../tcl \ No newline at end of file diff --git a/rel/build/ip_user/a2x_reset/vhdl b/rel/build/ip_user/a2x_reset/vhdl new file mode 120000 index 0000000..655de1a --- /dev/null +++ b/rel/build/ip_user/a2x_reset/vhdl @@ -0,0 +1 @@ +../../../src/vhdl \ No newline at end of file diff --git a/rel/build/ip_user/a2x_reset/xdc b/rel/build/ip_user/a2x_reset/xdc new file mode 120000 index 0000000..3add899 --- /dev/null +++ b/rel/build/ip_user/a2x_reset/xdc @@ -0,0 +1 @@ +../../xdc \ No newline at end of file diff --git a/rel/build/ip_user/reverserator_3/create_ip.tcl b/rel/build/ip_user/reverserator_3/create_ip.tcl new file mode 100644 index 0000000..6a510e8 --- /dev/null +++ b/rel/build/ip_user/reverserator_3/create_ip.tcl @@ -0,0 +1,62 @@ +# ip creator + +set project reverserator_3 ;# also top +set keep 0 ;# keep project +set xdc "" ;# set to xdc file if exists +set synth_check 1 + +proc create_ip {project {keep_project 0} {synth_check 1} {xdc ""}} { + + set vhdl_dir [file normalize ./vhdl] + set output_dir . + set project_dir ./prj + + create_project -force $project $output_dir/$project_dir -part xcvu3p-ffvc1517-2-e + + add_files -norecurse $vhdl_dir + + update_compile_order -fileset sources_1 + + set_property top $project [current_fileset] + set_property target_language VHDL [current_project] + set_property default_lib work [current_project] + set_property top $project [get_filesets sim_1] + set_property -name {xsim.compile.xvhdl.nosort} -value {false} -objects [get_filesets sim_1] + set_property -name {xsim.compile.xvlog.nosort} -value {false} -objects [get_filesets sim_1] + set_property simulator_language VHDL [current_project] + + if {$xdc != ""} { + set xdc_dir [file normalize ./xdc] + read_xdc $xdc_dir/$xdc + } + + update_compile_order -fileset sources_1 + + if {$synth_check} { + synth_design -rtl -name elab_for_sanity_check + } + + ipx::package_project -root_dir $output_dir/$project -vendor user.org -library user -taxonomy /UserIP -import_files -set_current false + ipx::unload_core $output_dir/$project/component.xml + ipx::edit_ip_in_project -upgrade true -name a2x_edit_project -directory $output_dir/$project $output_dir/$project/component.xml + update_compile_order -fileset sources_1 + set_property core_revision 2 [ipx::current_core] + ipx::update_source_project_archive -component [ipx::current_core] + ipx::create_xgui_files [ipx::current_core] + ipx::update_checksums [ipx::current_core] + ipx::save_core [ipx::current_core] + ipx::move_temp_component_back -component [ipx::current_core] + + if {$keep_project} { + close_project + puts "Project built; project dir saved: [file normalize $output_dir/$project_dir]" + } else { + close_project -delete + exec rm -rf $output_dir/$project_dir + puts "Project built; only IP files kept." + } + +} + +create_ip $project $keep $synth_check $xdc + diff --git a/rel/build/ip_user/reverserator_3/readme.md b/rel/build/ip_user/reverserator_3/readme.md new file mode 100644 index 0000000..5b0ec32 --- /dev/null +++ b/rel/build/ip_user/reverserator_3/readme.md @@ -0,0 +1,8 @@ +# create IP: reverserator_3 + +``` +$VIVADO -mode tcl -source ./create_ip.tcl +rm -r ../../ip_repo/reverserator_3 +cp -r reverserator_3 ../../ip_repo +``` + diff --git a/rel/build/ip_user/reverserator_3/vhdl/reverserator_3.vhdl b/rel/build/ip_user/reverserator_3/vhdl/reverserator_3.vhdl new file mode 100644 index 0000000..50021a4 --- /dev/null +++ b/rel/build/ip_user/reverserator_3/vhdl/reverserator_3.vhdl @@ -0,0 +1,48 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- terminate yet another rare xil bug + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity reverserator_3 is + port ( + outdoor : in std_logic_vector(0 to 2); + inndoor : out std_logic_vector(2 downto 0) + ); +end reverserator_3; + +architecture reverserator_3 of reverserator_3 is +begin + + inndoor <= outdoor; + +end reverserator_3; + diff --git a/rel/build/ip_user/reverserator_32/create_ip.tcl b/rel/build/ip_user/reverserator_32/create_ip.tcl new file mode 100644 index 0000000..4b5b86c --- /dev/null +++ b/rel/build/ip_user/reverserator_32/create_ip.tcl @@ -0,0 +1,62 @@ +# ip creator + +set project reverserator_32 ;# also top +set keep 0 ;# keep project +set xdc "" ;# set to xdc file if exists +set synth_check 1 + +proc create_ip {project {keep_project 0} {synth_check 1} {xdc ""}} { + + set vhdl_dir [file normalize ./vhdl] + set output_dir . + set project_dir ./prj + + create_project -force $project $output_dir/$project_dir -part xcvu3p-ffvc1517-2-e + + add_files -norecurse $vhdl_dir + + update_compile_order -fileset sources_1 + + set_property top $project [current_fileset] + set_property target_language VHDL [current_project] + set_property default_lib work [current_project] + set_property top $project [get_filesets sim_1] + set_property -name {xsim.compile.xvhdl.nosort} -value {false} -objects [get_filesets sim_1] + set_property -name {xsim.compile.xvlog.nosort} -value {false} -objects [get_filesets sim_1] + set_property simulator_language VHDL [current_project] + + if {$xdc != ""} { + set xdc_dir [file normalize ./xdc] + read_xdc $xdc_dir/$xdc + } + + update_compile_order -fileset sources_1 + + if {$synth_check} { + synth_design -rtl -name elab_for_sanity_check + } + + ipx::package_project -root_dir $output_dir/$project -vendor user.org -library user -taxonomy /UserIP -import_files -set_current false + ipx::unload_core $output_dir/$project/component.xml + ipx::edit_ip_in_project -upgrade true -name a2x_edit_project -directory $output_dir/$project $output_dir/$project/component.xml + update_compile_order -fileset sources_1 + set_property core_revision 2 [ipx::current_core] + ipx::update_source_project_archive -component [ipx::current_core] + ipx::create_xgui_files [ipx::current_core] + ipx::update_checksums [ipx::current_core] + ipx::save_core [ipx::current_core] + ipx::move_temp_component_back -component [ipx::current_core] + + if {$keep_project} { + close_project + puts "Project built; project dir saved: [file normalize $output_dir/$project_dir]" + } else { + close_project -delete + exec rm -rf $output_dir/$project_dir + puts "Project built; only IP files kept." + } + +} + +create_ip $project $keep $synth_check $xdc + diff --git a/rel/build/ip_user/reverserator_32/readme.md b/rel/build/ip_user/reverserator_32/readme.md new file mode 100644 index 0000000..11c073b --- /dev/null +++ b/rel/build/ip_user/reverserator_32/readme.md @@ -0,0 +1,8 @@ +# create IP: reverserator_32 + +``` +$VIVADO -mode tcl -source ./create_ip.tcl +rm -r ../../ip_repo/reverserator_32 +cp -r reverserator_32 ../../ip_repo +``` + diff --git a/rel/build/ip_user/reverserator_32/vhdl/reverserator_32.vhdl b/rel/build/ip_user/reverserator_32/vhdl/reverserator_32.vhdl new file mode 100644 index 0000000..b15470c --- /dev/null +++ b/rel/build/ip_user/reverserator_32/vhdl/reverserator_32.vhdl @@ -0,0 +1,48 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- terminate yet another rare xil bug + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity reverserator_32 is + port ( + hell : in std_logic_vector(0 to 31); + cowboys : out std_logic_vector(31 downto 0) + ); +end reverserator_32; + +architecture reverserator_32 of reverserator_32 is +begin + + cowboys <= hell; + +end reverserator_32; + diff --git a/rel/build/ip_user/reverserator_4/create_ip.tcl b/rel/build/ip_user/reverserator_4/create_ip.tcl new file mode 100644 index 0000000..c61e6cd --- /dev/null +++ b/rel/build/ip_user/reverserator_4/create_ip.tcl @@ -0,0 +1,62 @@ +# ip creator + +set project reverserator_4 ;# also top +set keep 0 ;# keep project +set xdc "" ;# set to xdc file if exists +set synth_check 1 + +proc create_ip {project {keep_project 0} {synth_check 1} {xdc ""}} { + + set vhdl_dir [file normalize ./vhdl] + set output_dir . + set project_dir ./prj + + create_project -force $project $output_dir/$project_dir -part xcvu3p-ffvc1517-2-e + + add_files -norecurse $vhdl_dir + + update_compile_order -fileset sources_1 + + set_property top $project [current_fileset] + set_property target_language VHDL [current_project] + set_property default_lib work [current_project] + set_property top $project [get_filesets sim_1] + set_property -name {xsim.compile.xvhdl.nosort} -value {false} -objects [get_filesets sim_1] + set_property -name {xsim.compile.xvlog.nosort} -value {false} -objects [get_filesets sim_1] + set_property simulator_language VHDL [current_project] + + if {$xdc != ""} { + set xdc_dir [file normalize ./xdc] + read_xdc $xdc_dir/$xdc + } + + update_compile_order -fileset sources_1 + + if {$synth_check} { + synth_design -rtl -name elab_for_sanity_check + } + + ipx::package_project -root_dir $output_dir/$project -vendor user.org -library user -taxonomy /UserIP -import_files -set_current false + ipx::unload_core $output_dir/$project/component.xml + ipx::edit_ip_in_project -upgrade true -name a2x_edit_project -directory $output_dir/$project $output_dir/$project/component.xml + update_compile_order -fileset sources_1 + set_property core_revision 2 [ipx::current_core] + ipx::update_source_project_archive -component [ipx::current_core] + ipx::create_xgui_files [ipx::current_core] + ipx::update_checksums [ipx::current_core] + ipx::save_core [ipx::current_core] + ipx::move_temp_component_back -component [ipx::current_core] + + if {$keep_project} { + close_project + puts "Project built; project dir saved: [file normalize $output_dir/$project_dir]" + } else { + close_project -delete + exec rm -rf $output_dir/$project_dir + puts "Project built; only IP files kept." + } + +} + +create_ip $project $keep $synth_check $xdc + diff --git a/rel/build/ip_user/reverserator_4/readme.md b/rel/build/ip_user/reverserator_4/readme.md new file mode 100644 index 0000000..ba5e735 --- /dev/null +++ b/rel/build/ip_user/reverserator_4/readme.md @@ -0,0 +1,8 @@ +# create IP: reverserator_4 + +``` +$VIVADO -mode tcl -source ./create_ip.tcl +rm -r ../../ip_repo/reverserator_4 +cp -r reverserator_4 ../../ip_repo +``` + diff --git a/rel/build/ip_user/reverserator_4/vhdl/reverserator_4.vhdl b/rel/build/ip_user/reverserator_4/vhdl/reverserator_4.vhdl new file mode 100644 index 0000000..8362b74 --- /dev/null +++ b/rel/build/ip_user/reverserator_4/vhdl/reverserator_4.vhdl @@ -0,0 +1,48 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- terminate yet another rare xil bug + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity reverserator_4 is + port ( + innnie : in std_logic_vector(0 to 3); + outtie : out std_logic_vector(3 downto 0) + ); +end reverserator_4; + +architecture reverserator_4 of reverserator_4 is +begin + + outtie <= innnie; + +end reverserator_4; + diff --git a/rel/build/ip_user/reverserator_64/create_ip.tcl b/rel/build/ip_user/reverserator_64/create_ip.tcl new file mode 100644 index 0000000..357da11 --- /dev/null +++ b/rel/build/ip_user/reverserator_64/create_ip.tcl @@ -0,0 +1,62 @@ +# ip creator + +set project reverserator_64 ;# also top +set keep 0 ;# keep project +set xdc "" ;# set to xdc file if exists +set synth_check 1 + +proc create_ip {project {keep_project 0} {synth_check 1} {xdc ""}} { + + set vhdl_dir [file normalize ./vhdl] + set output_dir . + set project_dir ./prj + + create_project -force $project $output_dir/$project_dir -part xcvu3p-ffvc1517-2-e + + add_files -norecurse $vhdl_dir + + update_compile_order -fileset sources_1 + + set_property top $project [current_fileset] + set_property target_language VHDL [current_project] + set_property default_lib work [current_project] + set_property top $project [get_filesets sim_1] + set_property -name {xsim.compile.xvhdl.nosort} -value {false} -objects [get_filesets sim_1] + set_property -name {xsim.compile.xvlog.nosort} -value {false} -objects [get_filesets sim_1] + set_property simulator_language VHDL [current_project] + + if {$xdc != ""} { + set xdc_dir [file normalize ./xdc] + read_xdc $xdc_dir/$xdc + } + + update_compile_order -fileset sources_1 + + if {$synth_check} { + synth_design -rtl -name elab_for_sanity_check + } + + ipx::package_project -root_dir $output_dir/$project -vendor user.org -library user -taxonomy /UserIP -import_files -set_current false + ipx::unload_core $output_dir/$project/component.xml + ipx::edit_ip_in_project -upgrade true -name a2x_edit_project -directory $output_dir/$project $output_dir/$project/component.xml + update_compile_order -fileset sources_1 + set_property core_revision 2 [ipx::current_core] + ipx::update_source_project_archive -component [ipx::current_core] + ipx::create_xgui_files [ipx::current_core] + ipx::update_checksums [ipx::current_core] + ipx::save_core [ipx::current_core] + ipx::move_temp_component_back -component [ipx::current_core] + + if {$keep_project} { + close_project + puts "Project built; project dir saved: [file normalize $output_dir/$project_dir]" + } else { + close_project -delete + exec rm -rf $output_dir/$project_dir + puts "Project built; only IP files kept." + } + +} + +create_ip $project $keep $synth_check $xdc + diff --git a/rel/build/ip_user/reverserator_64/readme.md b/rel/build/ip_user/reverserator_64/readme.md new file mode 100644 index 0000000..bfa6797 --- /dev/null +++ b/rel/build/ip_user/reverserator_64/readme.md @@ -0,0 +1,8 @@ +# create IP: reverserator_64 + +``` +$VIVADO -mode tcl -source ./create_ip.tcl +rm -r ../../ip_repo/reverserator_64 +cp -r reverserator_64 ../../ip_repo +``` + diff --git a/rel/build/ip_user/reverserator_64/vhdl/reverserator_64.vhdl b/rel/build/ip_user/reverserator_64/vhdl/reverserator_64.vhdl new file mode 100644 index 0000000..a1370f5 --- /dev/null +++ b/rel/build/ip_user/reverserator_64/vhdl/reverserator_64.vhdl @@ -0,0 +1,48 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- terminate yet another rare xil bug + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity reverserator_64 is + port ( + parkavenue : in std_logic_vector(0 to 63); + skidrowwww : out std_logic_vector(63 downto 0) + ); +end reverserator_64; + +architecture reverserator_64 of reverserator_64 is +begin + + skidrowwww <= parkavenue; + +end reverserator_64; + diff --git a/rel/build/tcl/create_ip_a2x_axi.tcl b/rel/build/tcl/create_ip_a2x_axi.tcl new file mode 100644 index 0000000..bf19fe9 --- /dev/null +++ b/rel/build/tcl/create_ip_a2x_axi.tcl @@ -0,0 +1,81 @@ +# ip creator + +set project a2x_axi ;# also top +set keep 0 ;# keep project +set xdc "" ;# set to xdc file if exists +set synth_check 1 +set vhdl2008 1 + +proc create_ip {project {keep_project 0} {synth_check 1} {xdc ""} {vhdl2008 1}} { + + set vhdl_dir [file normalize ./vhdl] + set output_dir . + set project_dir ./prj + + create_project -force $project $output_dir/$project_dir -part xcvu3p-ffvc1517-2-e + + add_files -norecurse $vhdl_dir/work + add_files -norecurse $vhdl_dir/ibm + add_files -norecurse $vhdl_dir/support + add_files -norecurse $vhdl_dir/tri + add_files -norecurse $vhdl_dir/clib + + set_property library work [get_files $vhdl_dir/work/*] + set_property library ibm [get_files $vhdl_dir/ibm/*] + set_property library support [get_files $vhdl_dir/support/*] + set_property library tri [get_files $vhdl_dir/tri/*] + set_property library clib [get_files $vhdl_dir/clib/*] + + if {$vhdl2008} { + set_property FILE_TYPE {VHDL 2008} [get_files $vhdl_dir/work/*] + set_property FILE_TYPE {VHDL 2008} [get_files $vhdl_dir/ibm/*] + set_property FILE_TYPE {VHDL 2008} [get_files $vhdl_dir/support/*] + set_property FILE_TYPE {VHDL 2008} [get_files $vhdl_dir/tri/*] + set_property FILE_TYPE {VHDL 2008} [get_files $vhdl_dir/clib/*] + } + + update_compile_order -fileset sources_1 + + set_property top $project [current_fileset] + set_property target_language VHDL [current_project] + set_property default_lib work [current_project] + set_property top $project [get_filesets sim_1] + set_property -name {xsim.compile.xvhdl.nosort} -value {false} -objects [get_filesets sim_1] + set_property -name {xsim.compile.xvlog.nosort} -value {false} -objects [get_filesets sim_1] + set_property simulator_language VHDL [current_project] + + if {$xdc != ""} { + set xdc_dir [file normalize ./xdc] + read_xdc $xdc_dir/$xdc + } + + update_compile_order -fileset sources_1 + + if {$synth_check} { + synth_design -rtl -name elab_for_sanity_check + } + + ipx::package_project -root_dir $output_dir/$project -vendor user.org -library user -taxonomy /UserIP -import_files -set_current false + ipx::unload_core $output_dir/$project/component.xml + ipx::edit_ip_in_project -upgrade true -name a2x_edit_project -directory $output_dir/$project $output_dir/$project/component.xml + update_compile_order -fileset sources_1 + set_property core_revision 2 [ipx::current_core] + ipx::update_source_project_archive -component [ipx::current_core] + ipx::create_xgui_files [ipx::current_core] + ipx::update_checksums [ipx::current_core] + ipx::save_core [ipx::current_core] + ipx::move_temp_component_back -component [ipx::current_core] + + if {$keep_project} { + close_project + puts "Project built; project dir saved: [file normalize $output_dir/$project_dir]" + } else { + close_project -delete + exec rm -rf $output_dir/$project_dir + puts "Project built; only IP files kept." + } + +} + +create_ip $project $keep $synth_check $xdc $vhdl2008 + diff --git a/rel/build/tcl/create_ip_a2x_axi_reg.tcl b/rel/build/tcl/create_ip_a2x_axi_reg.tcl new file mode 100644 index 0000000..115c3b4 --- /dev/null +++ b/rel/build/tcl/create_ip_a2x_axi_reg.tcl @@ -0,0 +1,72 @@ +# ip creator + +set project a2x_axi_reg ;# also top +set keep 0 ;# keep project +set xdc "" ;# set to xdc file if exists +set synth_check 1 + +proc create_ip {project {keep_project 0} {synth_check 1} {xdc ""}} { + + set vhdl_dir [file normalize ./vhdl] + set output_dir . + set project_dir ./prj + + create_project -force $project $output_dir/$project_dir -part xcvu3p-ffvc1517-2-e + + add_files -norecurse $vhdl_dir/work + add_files -norecurse $vhdl_dir/ibm + add_files -norecurse $vhdl_dir/support + add_files -norecurse $vhdl_dir/tri + add_files -norecurse $vhdl_dir/clib + + set_property library work [get_files $vhdl_dir/work/*] + set_property library ibm [get_files $vhdl_dir/ibm/*] + set_property library support [get_files $vhdl_dir/support/*] + set_property library tri [get_files $vhdl_dir/tri/*] + set_property library clib [get_files $vhdl_dir/clib/*] + + update_compile_order -fileset sources_1 + + set_property top $project [current_fileset] + set_property target_language VHDL [current_project] + set_property default_lib work [current_project] + set_property top $project [get_filesets sim_1] + set_property -name {xsim.compile.xvhdl.nosort} -value {false} -objects [get_filesets sim_1] + set_property -name {xsim.compile.xvlog.nosort} -value {false} -objects [get_filesets sim_1] + set_property simulator_language VHDL [current_project] + + if {$xdc != ""} { + set xdc_dir [file normalize ./xdc] + read_xdc $xdc_dir/$xdc + } + + update_compile_order -fileset sources_1 + + if {$synth_check} { + synth_design -rtl -name elab_for_sanity_check + } + + ipx::package_project -root_dir $output_dir/$project -vendor user.org -library user -taxonomy /UserIP -import_files -set_current false + ipx::unload_core $output_dir/$project/component.xml + ipx::edit_ip_in_project -upgrade true -name a2x_edit_project -directory $output_dir/$project $output_dir/$project/component.xml + update_compile_order -fileset sources_1 + set_property core_revision 2 [ipx::current_core] + ipx::update_source_project_archive -component [ipx::current_core] + ipx::create_xgui_files [ipx::current_core] + ipx::update_checksums [ipx::current_core] + ipx::save_core [ipx::current_core] + ipx::move_temp_component_back -component [ipx::current_core] + + if {$keep_project} { + close_project + puts "Project built; project dir saved: [file normalize $output_dir/$project_dir]" + } else { + close_project -delete + exec rm -rf $output_dir/$project_dir + puts "Project built; only IP files kept." + } + +} + +create_ip $project $keep $synth_check $xdc + diff --git a/rel/build/tcl/create_ip_a2x_dbug.tcl b/rel/build/tcl/create_ip_a2x_dbug.tcl new file mode 100644 index 0000000..d113d9c --- /dev/null +++ b/rel/build/tcl/create_ip_a2x_dbug.tcl @@ -0,0 +1,72 @@ +# ip creator + +set project a2x_dbug ;# also top +set keep 0 ;# keep project +set xdc "" ;# set to xdc file if exists +set synth_check 1 + +proc create_ip {project {keep_project 0} {synth_check 1} {xdc ""}} { + + set vhdl_dir [file normalize ./vhdl] + set output_dir . + set project_dir ./prj + + create_project -force $project $output_dir/$project_dir -part xcvu3p-ffvc1517-2-e + + add_files -norecurse $vhdl_dir/work + add_files -norecurse $vhdl_dir/ibm + add_files -norecurse $vhdl_dir/support + add_files -norecurse $vhdl_dir/tri + add_files -norecurse $vhdl_dir/clib + + set_property library work [get_files $vhdl_dir/work/*] + set_property library ibm [get_files $vhdl_dir/ibm/*] + set_property library support [get_files $vhdl_dir/support/*] + set_property library tri [get_files $vhdl_dir/tri/*] + set_property library clib [get_files $vhdl_dir/clib/*] + + update_compile_order -fileset sources_1 + + set_property top $project [current_fileset] + set_property target_language VHDL [current_project] + set_property default_lib work [current_project] + set_property top $project [get_filesets sim_1] + set_property -name {xsim.compile.xvhdl.nosort} -value {false} -objects [get_filesets sim_1] + set_property -name {xsim.compile.xvlog.nosort} -value {false} -objects [get_filesets sim_1] + set_property simulator_language VHDL [current_project] + + if {$xdc != ""} { + set xdc_dir [file normalize ./xdc] + read_xdc $xdc_dir/$xdc + } + + update_compile_order -fileset sources_1 + + if {$synth_check} { + synth_design -rtl -name elab_for_sanity_check + } + + ipx::package_project -root_dir $output_dir/$project -vendor user.org -library user -taxonomy /UserIP -import_files -set_current false + ipx::unload_core $output_dir/$project/component.xml + ipx::edit_ip_in_project -upgrade true -name a2x_edit_project -directory $output_dir/$project $output_dir/$project/component.xml + update_compile_order -fileset sources_1 + set_property core_revision 2 [ipx::current_core] + ipx::update_source_project_archive -component [ipx::current_core] + ipx::create_xgui_files [ipx::current_core] + ipx::update_checksums [ipx::current_core] + ipx::save_core [ipx::current_core] + ipx::move_temp_component_back -component [ipx::current_core] + + if {$keep_project} { + close_project + puts "Project built; project dir saved: [file normalize $output_dir/$project_dir]" + } else { + close_project -delete + exec rm -rf $output_dir/$project_dir + puts "Project built; only IP files kept." + } + +} + +create_ip $project $keep $synth_check $xdc + diff --git a/rel/build/tcl/create_ip_a2x_reset.tcl b/rel/build/tcl/create_ip_a2x_reset.tcl new file mode 100644 index 0000000..38062e4 --- /dev/null +++ b/rel/build/tcl/create_ip_a2x_reset.tcl @@ -0,0 +1,72 @@ +# ip creator + +set project a2x_reset ;# also top +set keep 0 ;# keep project +set xdc "" ;# set to xdc file if exists +set synth_check 1 + +proc create_ip {project {keep_project 0} {synth_check 1} {xdc ""}} { + + set vhdl_dir [file normalize ./vhdl] + set output_dir . + set project_dir ./prj + + create_project -force $project $output_dir/$project_dir -part xcvu3p-ffvc1517-2-e + + add_files -norecurse $vhdl_dir/work + add_files -norecurse $vhdl_dir/ibm + add_files -norecurse $vhdl_dir/support + add_files -norecurse $vhdl_dir/tri + add_files -norecurse $vhdl_dir/clib + + set_property library work [get_files $vhdl_dir/work/*] + set_property library ibm [get_files $vhdl_dir/ibm/*] + set_property library support [get_files $vhdl_dir/support/*] + set_property library tri [get_files $vhdl_dir/tri/*] + set_property library clib [get_files $vhdl_dir/clib/*] + + update_compile_order -fileset sources_1 + + set_property top $project [current_fileset] + set_property target_language VHDL [current_project] + set_property default_lib work [current_project] + set_property top $project [get_filesets sim_1] + set_property -name {xsim.compile.xvhdl.nosort} -value {false} -objects [get_filesets sim_1] + set_property -name {xsim.compile.xvlog.nosort} -value {false} -objects [get_filesets sim_1] + set_property simulator_language VHDL [current_project] + + if {$xdc != ""} { + set xdc_dir [file normalize ./xdc] + read_xdc $xdc_dir/$xdc + } + + update_compile_order -fileset sources_1 + + if {$synth_check} { + synth_design -rtl -name elab_for_sanity_check + } + + ipx::package_project -root_dir $output_dir/$project -vendor user.org -library user -taxonomy /UserIP -import_files -set_current false + ipx::unload_core $output_dir/$project/component.xml + ipx::edit_ip_in_project -upgrade true -name a2x_edit_project -directory $output_dir/$project $output_dir/$project/component.xml + update_compile_order -fileset sources_1 + set_property core_revision 2 [ipx::current_core] + ipx::update_source_project_archive -component [ipx::current_core] + ipx::create_xgui_files [ipx::current_core] + ipx::update_checksums [ipx::current_core] + ipx::save_core [ipx::current_core] + ipx::move_temp_component_back -component [ipx::current_core] + + if {$keep_project} { + close_project + puts "Project built; project dir saved: [file normalize $output_dir/$project_dir]" + } else { + close_project -delete + exec rm -rf $output_dir/$project_dir + puts "Project built; only IP files kept." + } + +} + +create_ip $project $keep $synth_check $xdc + diff --git a/rel/build/tcl/create_ip_a2x_scom.tcl b/rel/build/tcl/create_ip_a2x_scom.tcl new file mode 100644 index 0000000..f668f2a --- /dev/null +++ b/rel/build/tcl/create_ip_a2x_scom.tcl @@ -0,0 +1,72 @@ +# ip creator + +set project a2x_scom ;# also top +set keep 0 ;# keep project +set xdc "" ;# set to xdc file if exists +set synth_check 1 + +proc create_ip {project {keep_project 0} {synth_check 1} {xdc ""}} { + + set vhdl_dir [file normalize ./vhdl] + set output_dir . + set project_dir ./prj + + create_project -force $project $output_dir/$project_dir -part xcvu3p-ffvc1517-2-e + + add_files -norecurse $vhdl_dir/work + add_files -norecurse $vhdl_dir/ibm + add_files -norecurse $vhdl_dir/support + add_files -norecurse $vhdl_dir/tri + add_files -norecurse $vhdl_dir/clib + + set_property library work [get_files $vhdl_dir/work/*] + set_property library ibm [get_files $vhdl_dir/ibm/*] + set_property library support [get_files $vhdl_dir/support/*] + set_property library tri [get_files $vhdl_dir/tri/*] + set_property library clib [get_files $vhdl_dir/clib/*] + + update_compile_order -fileset sources_1 + + set_property top $project [current_fileset] + set_property target_language VHDL [current_project] + set_property default_lib work [current_project] + set_property top $project [get_filesets sim_1] + set_property -name {xsim.compile.xvhdl.nosort} -value {false} -objects [get_filesets sim_1] + set_property -name {xsim.compile.xvlog.nosort} -value {false} -objects [get_filesets sim_1] + set_property simulator_language VHDL [current_project] + + if {$xdc != ""} { + set xdc_dir [file normalize ./xdc] + read_xdc $xdc_dir/$xdc + } + + update_compile_order -fileset sources_1 + + if {$synth_check} { + synth_design -rtl -name elab_for_sanity_check + } + + ipx::package_project -root_dir $output_dir/$project -vendor user.org -library user -taxonomy /UserIP -import_files -set_current false + ipx::unload_core $output_dir/$project/component.xml + ipx::edit_ip_in_project -upgrade true -name a2x_edit_project -directory $output_dir/$project $output_dir/$project/component.xml + update_compile_order -fileset sources_1 + set_property core_revision 2 [ipx::current_core] + ipx::update_source_project_archive -component [ipx::current_core] + ipx::create_xgui_files [ipx::current_core] + ipx::update_checksums [ipx::current_core] + ipx::save_core [ipx::current_core] + ipx::move_temp_component_back -component [ipx::current_core] + + if {$keep_project} { + close_project + puts "Project built; project dir saved: [file normalize $output_dir/$project_dir]" + } else { + close_project -delete + exec rm -rf $output_dir/$project_dir + puts "Project built; only IP files kept." + } + +} + +create_ip $project $keep $synth_check $xdc + diff --git a/rel/build/xdc/a2x_timing.xdc b/rel/build/xdc/a2x_timing.xdc new file mode 100644 index 0000000..83e28f9 --- /dev/null +++ b/rel/build/xdc/a2x_timing.xdc @@ -0,0 +1,2 @@ +create_clock -period 10.000 -name clk [get_ports clk] +create_clock -period 5.0000 -name clk2x [get_ports clk2x] diff --git a/rel/build/xdc/main_extras.xdc b/rel/build/xdc/main_extras.xdc new file mode 100644 index 0000000..6f16541 --- /dev/null +++ b/rel/build/xdc/main_extras.xdc @@ -0,0 +1,452 @@ + +connect_debug_port u_ila_0/probe2 [get_nets [list {u_ila_0_cpl_spr_ex5_nia[247]} {u_ila_0_cpl_spr_ex5_nia[246]} {u_ila_0_cpl_spr_ex5_nia[245]} {u_ila_0_cpl_spr_ex5_nia[244]} {u_ila_0_cpl_spr_ex5_nia[243]} {u_ila_0_cpl_spr_ex5_nia[242]} {u_ila_0_cpl_spr_ex5_nia[241]} {u_ila_0_cpl_spr_ex5_nia[240]} {u_ila_0_cpl_spr_ex5_nia[239]} {u_ila_0_cpl_spr_ex5_nia[238]} {u_ila_0_cpl_spr_ex5_nia[237]} {u_ila_0_cpl_spr_ex5_nia[236]} {u_ila_0_cpl_spr_ex5_nia[235]} {u_ila_0_cpl_spr_ex5_nia[234]} {u_ila_0_cpl_spr_ex5_nia[233]} {u_ila_0_cpl_spr_ex5_nia[232]} {u_ila_0_cpl_spr_ex5_nia[231]} {u_ila_0_cpl_spr_ex5_nia[230]} {u_ila_0_cpl_spr_ex5_nia[229]} {u_ila_0_cpl_spr_ex5_nia[228]} {u_ila_0_cpl_spr_ex5_nia[227]} {u_ila_0_cpl_spr_ex5_nia[226]} {u_ila_0_cpl_spr_ex5_nia[225]} {u_ila_0_cpl_spr_ex5_nia[224]} {u_ila_0_cpl_spr_ex5_nia[223]} {u_ila_0_cpl_spr_ex5_nia[222]} {u_ila_0_cpl_spr_ex5_nia[221]} {u_ila_0_cpl_spr_ex5_nia[220]} {u_ila_0_cpl_spr_ex5_nia[219]} {u_ila_0_cpl_spr_ex5_nia[218]} {u_ila_0_cpl_spr_ex5_nia[217]} {u_ila_0_cpl_spr_ex5_nia[216]} {u_ila_0_cpl_spr_ex5_nia[215]} {u_ila_0_cpl_spr_ex5_nia[214]} {u_ila_0_cpl_spr_ex5_nia[213]} {u_ila_0_cpl_spr_ex5_nia[212]} {u_ila_0_cpl_spr_ex5_nia[211]} {u_ila_0_cpl_spr_ex5_nia[210]} {u_ila_0_cpl_spr_ex5_nia[209]} {u_ila_0_cpl_spr_ex5_nia[208]} {u_ila_0_cpl_spr_ex5_nia[207]} {u_ila_0_cpl_spr_ex5_nia[206]} {u_ila_0_cpl_spr_ex5_nia[205]} {u_ila_0_cpl_spr_ex5_nia[204]} {u_ila_0_cpl_spr_ex5_nia[203]} {u_ila_0_cpl_spr_ex5_nia[202]} {u_ila_0_cpl_spr_ex5_nia[201]} {u_ila_0_cpl_spr_ex5_nia[200]} {u_ila_0_cpl_spr_ex5_nia[199]} {u_ila_0_cpl_spr_ex5_nia[198]} {u_ila_0_cpl_spr_ex5_nia[197]} {u_ila_0_cpl_spr_ex5_nia[196]} {u_ila_0_cpl_spr_ex5_nia[195]} {u_ila_0_cpl_spr_ex5_nia[194]} {u_ila_0_cpl_spr_ex5_nia[193]} {u_ila_0_cpl_spr_ex5_nia[192]} {u_ila_0_cpl_spr_ex5_nia[191]} {u_ila_0_cpl_spr_ex5_nia[190]} {u_ila_0_cpl_spr_ex5_nia[189]} {u_ila_0_cpl_spr_ex5_nia[188]} {u_ila_0_cpl_spr_ex5_nia[187]} {u_ila_0_cpl_spr_ex5_nia[186]} {u_ila_0_cpl_spr_ex5_nia[185]} {u_ila_0_cpl_spr_ex5_nia[184]} {u_ila_0_cpl_spr_ex5_nia[183]} {u_ila_0_cpl_spr_ex5_nia[182]} {u_ila_0_cpl_spr_ex5_nia[181]} {u_ila_0_cpl_spr_ex5_nia[180]} {u_ila_0_cpl_spr_ex5_nia[179]} {u_ila_0_cpl_spr_ex5_nia[178]} {u_ila_0_cpl_spr_ex5_nia[177]} {u_ila_0_cpl_spr_ex5_nia[176]} {u_ila_0_cpl_spr_ex5_nia[175]} {u_ila_0_cpl_spr_ex5_nia[174]} {u_ila_0_cpl_spr_ex5_nia[173]} {u_ila_0_cpl_spr_ex5_nia[172]} {u_ila_0_cpl_spr_ex5_nia[171]} {u_ila_0_cpl_spr_ex5_nia[170]} {u_ila_0_cpl_spr_ex5_nia[169]} {u_ila_0_cpl_spr_ex5_nia[168]} {u_ila_0_cpl_spr_ex5_nia[167]} {u_ila_0_cpl_spr_ex5_nia[166]} {u_ila_0_cpl_spr_ex5_nia[165]} {u_ila_0_cpl_spr_ex5_nia[164]} {u_ila_0_cpl_spr_ex5_nia[163]} {u_ila_0_cpl_spr_ex5_nia[162]} {u_ila_0_cpl_spr_ex5_nia[161]} {u_ila_0_cpl_spr_ex5_nia[160]} {u_ila_0_cpl_spr_ex5_nia[159]} {u_ila_0_cpl_spr_ex5_nia[158]} {u_ila_0_cpl_spr_ex5_nia[157]} {u_ila_0_cpl_spr_ex5_nia[156]} {u_ila_0_cpl_spr_ex5_nia[155]} {u_ila_0_cpl_spr_ex5_nia[154]} {u_ila_0_cpl_spr_ex5_nia[153]} {u_ila_0_cpl_spr_ex5_nia[152]} {u_ila_0_cpl_spr_ex5_nia[151]} {u_ila_0_cpl_spr_ex5_nia[150]} {u_ila_0_cpl_spr_ex5_nia[149]} {u_ila_0_cpl_spr_ex5_nia[148]} {u_ila_0_cpl_spr_ex5_nia[147]} {u_ila_0_cpl_spr_ex5_nia[146]} {u_ila_0_cpl_spr_ex5_nia[145]} {u_ila_0_cpl_spr_ex5_nia[144]} {u_ila_0_cpl_spr_ex5_nia[143]} {u_ila_0_cpl_spr_ex5_nia[142]} {u_ila_0_cpl_spr_ex5_nia[141]} {u_ila_0_cpl_spr_ex5_nia[140]} {u_ila_0_cpl_spr_ex5_nia[139]} {u_ila_0_cpl_spr_ex5_nia[138]} {u_ila_0_cpl_spr_ex5_nia[137]} {u_ila_0_cpl_spr_ex5_nia[136]} {u_ila_0_cpl_spr_ex5_nia[135]} {u_ila_0_cpl_spr_ex5_nia[134]} {u_ila_0_cpl_spr_ex5_nia[133]} {u_ila_0_cpl_spr_ex5_nia[132]} {u_ila_0_cpl_spr_ex5_nia[131]} {u_ila_0_cpl_spr_ex5_nia[130]} {u_ila_0_cpl_spr_ex5_nia[129]} {u_ila_0_cpl_spr_ex5_nia[128]} {u_ila_0_cpl_spr_ex5_nia[127]} {u_ila_0_cpl_spr_ex5_nia[126]} {u_ila_0_cpl_spr_ex5_nia[125]} {u_ila_0_cpl_spr_ex5_nia[124]} {u_ila_0_cpl_spr_ex5_nia[123]} {u_ila_0_cpl_spr_ex5_nia[122]} {u_ila_0_cpl_spr_ex5_nia[121]} {u_ila_0_cpl_spr_ex5_nia[120]} {u_ila_0_cpl_spr_ex5_nia[119]} {u_ila_0_cpl_spr_ex5_nia[118]} {u_ila_0_cpl_spr_ex5_nia[117]} {u_ila_0_cpl_spr_ex5_nia[116]} {u_ila_0_cpl_spr_ex5_nia[115]} {u_ila_0_cpl_spr_ex5_nia[114]} {u_ila_0_cpl_spr_ex5_nia[113]} {u_ila_0_cpl_spr_ex5_nia[112]} {u_ila_0_cpl_spr_ex5_nia[111]} {u_ila_0_cpl_spr_ex5_nia[110]} {u_ila_0_cpl_spr_ex5_nia[109]} {u_ila_0_cpl_spr_ex5_nia[108]} {u_ila_0_cpl_spr_ex5_nia[107]} {u_ila_0_cpl_spr_ex5_nia[106]} {u_ila_0_cpl_spr_ex5_nia[105]} {u_ila_0_cpl_spr_ex5_nia[104]} {u_ila_0_cpl_spr_ex5_nia[103]} {u_ila_0_cpl_spr_ex5_nia[102]} {u_ila_0_cpl_spr_ex5_nia[101]} {u_ila_0_cpl_spr_ex5_nia[100]} {u_ila_0_cpl_spr_ex5_nia[99]} {u_ila_0_cpl_spr_ex5_nia[98]} {u_ila_0_cpl_spr_ex5_nia[97]} {u_ila_0_cpl_spr_ex5_nia[96]} {u_ila_0_cpl_spr_ex5_nia[95]} {u_ila_0_cpl_spr_ex5_nia[94]} {u_ila_0_cpl_spr_ex5_nia[93]} {u_ila_0_cpl_spr_ex5_nia[92]} {u_ila_0_cpl_spr_ex5_nia[91]} {u_ila_0_cpl_spr_ex5_nia[90]} {u_ila_0_cpl_spr_ex5_nia[89]} {u_ila_0_cpl_spr_ex5_nia[88]} {u_ila_0_cpl_spr_ex5_nia[87]} {u_ila_0_cpl_spr_ex5_nia[86]} {u_ila_0_cpl_spr_ex5_nia[85]} {u_ila_0_cpl_spr_ex5_nia[84]} {u_ila_0_cpl_spr_ex5_nia[83]} {u_ila_0_cpl_spr_ex5_nia[82]} {u_ila_0_cpl_spr_ex5_nia[81]} {u_ila_0_cpl_spr_ex5_nia[80]} {u_ila_0_cpl_spr_ex5_nia[79]} {u_ila_0_cpl_spr_ex5_nia[78]} {u_ila_0_cpl_spr_ex5_nia[77]} {u_ila_0_cpl_spr_ex5_nia[76]} {u_ila_0_cpl_spr_ex5_nia[75]} {u_ila_0_cpl_spr_ex5_nia[74]} {u_ila_0_cpl_spr_ex5_nia[73]} {u_ila_0_cpl_spr_ex5_nia[72]} {u_ila_0_cpl_spr_ex5_nia[71]} {u_ila_0_cpl_spr_ex5_nia[70]} {u_ila_0_cpl_spr_ex5_nia[69]} {u_ila_0_cpl_spr_ex5_nia[68]} {u_ila_0_cpl_spr_ex5_nia[67]} {u_ila_0_cpl_spr_ex5_nia[66]} {u_ila_0_cpl_spr_ex5_nia[65]} {u_ila_0_cpl_spr_ex5_nia[64]} {u_ila_0_cpl_spr_ex5_nia[63]} {u_ila_0_cpl_spr_ex5_nia[62]} {u_ila_0_cpl_spr_ex5_nia[61]} {u_ila_0_cpl_spr_ex5_nia[60]} {u_ila_0_cpl_spr_ex5_nia[59]} {u_ila_0_cpl_spr_ex5_nia[58]} {u_ila_0_cpl_spr_ex5_nia[57]} {u_ila_0_cpl_spr_ex5_nia[56]} {u_ila_0_cpl_spr_ex5_nia[55]} {u_ila_0_cpl_spr_ex5_nia[54]} {u_ila_0_cpl_spr_ex5_nia[53]} {u_ila_0_cpl_spr_ex5_nia[52]} {u_ila_0_cpl_spr_ex5_nia[51]} {u_ila_0_cpl_spr_ex5_nia[50]} {u_ila_0_cpl_spr_ex5_nia[49]} {u_ila_0_cpl_spr_ex5_nia[48]} {u_ila_0_cpl_spr_ex5_nia[47]} {u_ila_0_cpl_spr_ex5_nia[46]} {u_ila_0_cpl_spr_ex5_nia[45]} {u_ila_0_cpl_spr_ex5_nia[44]} {u_ila_0_cpl_spr_ex5_nia[43]} {u_ila_0_cpl_spr_ex5_nia[42]} {u_ila_0_cpl_spr_ex5_nia[41]} {u_ila_0_cpl_spr_ex5_nia[40]} {u_ila_0_cpl_spr_ex5_nia[39]} {u_ila_0_cpl_spr_ex5_nia[38]} {u_ila_0_cpl_spr_ex5_nia[37]} {u_ila_0_cpl_spr_ex5_nia[36]} {u_ila_0_cpl_spr_ex5_nia[35]} {u_ila_0_cpl_spr_ex5_nia[34]} {u_ila_0_cpl_spr_ex5_nia[33]} {u_ila_0_cpl_spr_ex5_nia[32]} {u_ila_0_cpl_spr_ex5_nia[31]} {u_ila_0_cpl_spr_ex5_nia[30]} {u_ila_0_cpl_spr_ex5_nia[29]} {u_ila_0_cpl_spr_ex5_nia[28]} {u_ila_0_cpl_spr_ex5_nia[27]} {u_ila_0_cpl_spr_ex5_nia[26]} {u_ila_0_cpl_spr_ex5_nia[25]} {u_ila_0_cpl_spr_ex5_nia[24]} {u_ila_0_cpl_spr_ex5_nia[23]} {u_ila_0_cpl_spr_ex5_nia[22]} {u_ila_0_cpl_spr_ex5_nia[21]} {u_ila_0_cpl_spr_ex5_nia[20]} {u_ila_0_cpl_spr_ex5_nia[19]} {u_ila_0_cpl_spr_ex5_nia[18]} {u_ila_0_cpl_spr_ex5_nia[17]} {u_ila_0_cpl_spr_ex5_nia[16]} {u_ila_0_cpl_spr_ex5_nia[15]} {u_ila_0_cpl_spr_ex5_nia[14]} {u_ila_0_cpl_spr_ex5_nia[13]} {u_ila_0_cpl_spr_ex5_nia[12]} {u_ila_0_cpl_spr_ex5_nia[11]} {u_ila_0_cpl_spr_ex5_nia[10]} {u_ila_0_cpl_spr_ex5_nia[9]} {u_ila_0_cpl_spr_ex5_nia[8]} {u_ila_0_cpl_spr_ex5_nia[7]} {u_ila_0_cpl_spr_ex5_nia[6]} {u_ila_0_cpl_spr_ex5_nia[5]} {u_ila_0_cpl_spr_ex5_nia[4]} {u_ila_0_cpl_spr_ex5_nia[3]} {u_ila_0_cpl_spr_ex5_nia[2]} {u_ila_0_cpl_spr_ex5_nia[1]} {u_ila_0_cpl_spr_ex5_nia[0]}]] +connect_debug_port u_ila_0/probe3 [get_nets [list {u_ila_0_dout[31]} {u_ila_0_dout[30]} {u_ila_0_dout[29]} {u_ila_0_dout[28]} {u_ila_0_dout[27]} {u_ila_0_dout[26]} {u_ila_0_dout[25]} {u_ila_0_dout[24]} {u_ila_0_dout[23]} {u_ila_0_dout[22]} {u_ila_0_dout[21]} {u_ila_0_dout[20]} {u_ila_0_dout[19]} {u_ila_0_dout[18]} {u_ila_0_dout[17]} {u_ila_0_dout[16]} {u_ila_0_dout[15]} {u_ila_0_dout[14]} {u_ila_0_dout[13]} {u_ila_0_dout[12]} {u_ila_0_dout[11]} {u_ila_0_dout[10]} {u_ila_0_dout[9]} {u_ila_0_dout[8]} {u_ila_0_dout[7]} {u_ila_0_dout[6]} {u_ila_0_dout[5]} {u_ila_0_dout[4]} {u_ila_0_dout[3]} {u_ila_0_dout[2]} {u_ila_0_dout[1]} {u_ila_0_dout[0]}]] +connect_debug_port u_ila_0/probe17 [get_nets [list u_ila_0_m00_axi_arready]] +connect_debug_port u_ila_0/probe18 [get_nets [list u_ila_0_m00_axi_arvalid]] +connect_debug_port u_ila_0/probe19 [get_nets [list u_ila_0_m00_axi_awready]] +connect_debug_port u_ila_0/probe20 [get_nets [list u_ila_0_m00_axi_awvalid]] +connect_debug_port u_ila_0/probe29 [get_nets [list u_ila_0_WEA]] + +connect_debug_port u_ila_0/probe2 [get_nets [list {u_ila_0_cpl_spr_ex5_nia[247]} {u_ila_0_cpl_spr_ex5_nia[246]} {u_ila_0_cpl_spr_ex5_nia[245]} {u_ila_0_cpl_spr_ex5_nia[244]} {u_ila_0_cpl_spr_ex5_nia[243]} {u_ila_0_cpl_spr_ex5_nia[242]} {u_ila_0_cpl_spr_ex5_nia[241]} {u_ila_0_cpl_spr_ex5_nia[240]} {u_ila_0_cpl_spr_ex5_nia[239]} {u_ila_0_cpl_spr_ex5_nia[238]} {u_ila_0_cpl_spr_ex5_nia[237]} {u_ila_0_cpl_spr_ex5_nia[236]} {u_ila_0_cpl_spr_ex5_nia[235]} {u_ila_0_cpl_spr_ex5_nia[234]} {u_ila_0_cpl_spr_ex5_nia[233]} {u_ila_0_cpl_spr_ex5_nia[232]} {u_ila_0_cpl_spr_ex5_nia[231]} {u_ila_0_cpl_spr_ex5_nia[230]} {u_ila_0_cpl_spr_ex5_nia[229]} {u_ila_0_cpl_spr_ex5_nia[228]} {u_ila_0_cpl_spr_ex5_nia[227]} {u_ila_0_cpl_spr_ex5_nia[226]} {u_ila_0_cpl_spr_ex5_nia[225]} {u_ila_0_cpl_spr_ex5_nia[224]} {u_ila_0_cpl_spr_ex5_nia[223]} {u_ila_0_cpl_spr_ex5_nia[222]} {u_ila_0_cpl_spr_ex5_nia[221]} {u_ila_0_cpl_spr_ex5_nia[220]} {u_ila_0_cpl_spr_ex5_nia[219]} {u_ila_0_cpl_spr_ex5_nia[218]} {u_ila_0_cpl_spr_ex5_nia[217]} {u_ila_0_cpl_spr_ex5_nia[216]} {u_ila_0_cpl_spr_ex5_nia[215]} {u_ila_0_cpl_spr_ex5_nia[214]} {u_ila_0_cpl_spr_ex5_nia[213]} {u_ila_0_cpl_spr_ex5_nia[212]} {u_ila_0_cpl_spr_ex5_nia[211]} {u_ila_0_cpl_spr_ex5_nia[210]} {u_ila_0_cpl_spr_ex5_nia[209]} {u_ila_0_cpl_spr_ex5_nia[208]} {u_ila_0_cpl_spr_ex5_nia[207]} {u_ila_0_cpl_spr_ex5_nia[206]} {u_ila_0_cpl_spr_ex5_nia[205]} {u_ila_0_cpl_spr_ex5_nia[204]} {u_ila_0_cpl_spr_ex5_nia[203]} {u_ila_0_cpl_spr_ex5_nia[202]} {u_ila_0_cpl_spr_ex5_nia[201]} {u_ila_0_cpl_spr_ex5_nia[200]} {u_ila_0_cpl_spr_ex5_nia[199]} {u_ila_0_cpl_spr_ex5_nia[198]} {u_ila_0_cpl_spr_ex5_nia[197]} {u_ila_0_cpl_spr_ex5_nia[196]} {u_ila_0_cpl_spr_ex5_nia[195]} {u_ila_0_cpl_spr_ex5_nia[194]} {u_ila_0_cpl_spr_ex5_nia[193]} {u_ila_0_cpl_spr_ex5_nia[192]} {u_ila_0_cpl_spr_ex5_nia[191]} {u_ila_0_cpl_spr_ex5_nia[190]} {u_ila_0_cpl_spr_ex5_nia[189]} {u_ila_0_cpl_spr_ex5_nia[188]} {u_ila_0_cpl_spr_ex5_nia[187]} {u_ila_0_cpl_spr_ex5_nia[186]} {u_ila_0_cpl_spr_ex5_nia[185]} {u_ila_0_cpl_spr_ex5_nia[184]} {u_ila_0_cpl_spr_ex5_nia[183]} {u_ila_0_cpl_spr_ex5_nia[182]} {u_ila_0_cpl_spr_ex5_nia[181]} {u_ila_0_cpl_spr_ex5_nia[180]} {u_ila_0_cpl_spr_ex5_nia[179]} {u_ila_0_cpl_spr_ex5_nia[178]} {u_ila_0_cpl_spr_ex5_nia[177]} {u_ila_0_cpl_spr_ex5_nia[176]} {u_ila_0_cpl_spr_ex5_nia[175]} {u_ila_0_cpl_spr_ex5_nia[174]} {u_ila_0_cpl_spr_ex5_nia[173]} {u_ila_0_cpl_spr_ex5_nia[172]} {u_ila_0_cpl_spr_ex5_nia[171]} {u_ila_0_cpl_spr_ex5_nia[170]} {u_ila_0_cpl_spr_ex5_nia[169]} {u_ila_0_cpl_spr_ex5_nia[168]} {u_ila_0_cpl_spr_ex5_nia[167]} {u_ila_0_cpl_spr_ex5_nia[166]} {u_ila_0_cpl_spr_ex5_nia[165]} {u_ila_0_cpl_spr_ex5_nia[164]} {u_ila_0_cpl_spr_ex5_nia[163]} {u_ila_0_cpl_spr_ex5_nia[162]} {u_ila_0_cpl_spr_ex5_nia[161]} {u_ila_0_cpl_spr_ex5_nia[160]} {u_ila_0_cpl_spr_ex5_nia[159]} {u_ila_0_cpl_spr_ex5_nia[158]} {u_ila_0_cpl_spr_ex5_nia[157]} {u_ila_0_cpl_spr_ex5_nia[156]} {u_ila_0_cpl_spr_ex5_nia[155]} {u_ila_0_cpl_spr_ex5_nia[154]} {u_ila_0_cpl_spr_ex5_nia[153]} {u_ila_0_cpl_spr_ex5_nia[152]} {u_ila_0_cpl_spr_ex5_nia[151]} {u_ila_0_cpl_spr_ex5_nia[150]} {u_ila_0_cpl_spr_ex5_nia[149]} {u_ila_0_cpl_spr_ex5_nia[148]} {u_ila_0_cpl_spr_ex5_nia[147]} {u_ila_0_cpl_spr_ex5_nia[146]} {u_ila_0_cpl_spr_ex5_nia[145]} {u_ila_0_cpl_spr_ex5_nia[144]} {u_ila_0_cpl_spr_ex5_nia[143]} {u_ila_0_cpl_spr_ex5_nia[142]} {u_ila_0_cpl_spr_ex5_nia[141]} {u_ila_0_cpl_spr_ex5_nia[140]} {u_ila_0_cpl_spr_ex5_nia[139]} {u_ila_0_cpl_spr_ex5_nia[138]} {u_ila_0_cpl_spr_ex5_nia[137]} {u_ila_0_cpl_spr_ex5_nia[136]} {u_ila_0_cpl_spr_ex5_nia[135]} {u_ila_0_cpl_spr_ex5_nia[134]} {u_ila_0_cpl_spr_ex5_nia[133]} {u_ila_0_cpl_spr_ex5_nia[132]} {u_ila_0_cpl_spr_ex5_nia[131]} {u_ila_0_cpl_spr_ex5_nia[130]} {u_ila_0_cpl_spr_ex5_nia[129]} {u_ila_0_cpl_spr_ex5_nia[128]} {u_ila_0_cpl_spr_ex5_nia[127]} {u_ila_0_cpl_spr_ex5_nia[126]} {u_ila_0_cpl_spr_ex5_nia[125]} {u_ila_0_cpl_spr_ex5_nia[124]} {u_ila_0_cpl_spr_ex5_nia[123]} {u_ila_0_cpl_spr_ex5_nia[122]} {u_ila_0_cpl_spr_ex5_nia[121]} {u_ila_0_cpl_spr_ex5_nia[120]} {u_ila_0_cpl_spr_ex5_nia[119]} {u_ila_0_cpl_spr_ex5_nia[118]} {u_ila_0_cpl_spr_ex5_nia[117]} {u_ila_0_cpl_spr_ex5_nia[116]} {u_ila_0_cpl_spr_ex5_nia[115]} {u_ila_0_cpl_spr_ex5_nia[114]} {u_ila_0_cpl_spr_ex5_nia[113]} {u_ila_0_cpl_spr_ex5_nia[112]} {u_ila_0_cpl_spr_ex5_nia[111]} {u_ila_0_cpl_spr_ex5_nia[110]} {u_ila_0_cpl_spr_ex5_nia[109]} {u_ila_0_cpl_spr_ex5_nia[108]} {u_ila_0_cpl_spr_ex5_nia[107]} {u_ila_0_cpl_spr_ex5_nia[106]} {u_ila_0_cpl_spr_ex5_nia[105]} {u_ila_0_cpl_spr_ex5_nia[104]} {u_ila_0_cpl_spr_ex5_nia[103]} {u_ila_0_cpl_spr_ex5_nia[102]} {u_ila_0_cpl_spr_ex5_nia[101]} {u_ila_0_cpl_spr_ex5_nia[100]} {u_ila_0_cpl_spr_ex5_nia[99]} {u_ila_0_cpl_spr_ex5_nia[98]} {u_ila_0_cpl_spr_ex5_nia[97]} {u_ila_0_cpl_spr_ex5_nia[96]} {u_ila_0_cpl_spr_ex5_nia[95]} {u_ila_0_cpl_spr_ex5_nia[94]} {u_ila_0_cpl_spr_ex5_nia[93]} {u_ila_0_cpl_spr_ex5_nia[92]} {u_ila_0_cpl_spr_ex5_nia[91]} {u_ila_0_cpl_spr_ex5_nia[90]} {u_ila_0_cpl_spr_ex5_nia[89]} {u_ila_0_cpl_spr_ex5_nia[88]} {u_ila_0_cpl_spr_ex5_nia[87]} {u_ila_0_cpl_spr_ex5_nia[86]} {u_ila_0_cpl_spr_ex5_nia[85]} {u_ila_0_cpl_spr_ex5_nia[84]} {u_ila_0_cpl_spr_ex5_nia[83]} {u_ila_0_cpl_spr_ex5_nia[82]} {u_ila_0_cpl_spr_ex5_nia[81]} {u_ila_0_cpl_spr_ex5_nia[80]} {u_ila_0_cpl_spr_ex5_nia[79]} {u_ila_0_cpl_spr_ex5_nia[78]} {u_ila_0_cpl_spr_ex5_nia[77]} {u_ila_0_cpl_spr_ex5_nia[76]} {u_ila_0_cpl_spr_ex5_nia[75]} {u_ila_0_cpl_spr_ex5_nia[74]} {u_ila_0_cpl_spr_ex5_nia[73]} {u_ila_0_cpl_spr_ex5_nia[72]} {u_ila_0_cpl_spr_ex5_nia[71]} {u_ila_0_cpl_spr_ex5_nia[70]} {u_ila_0_cpl_spr_ex5_nia[69]} {u_ila_0_cpl_spr_ex5_nia[68]} {u_ila_0_cpl_spr_ex5_nia[67]} {u_ila_0_cpl_spr_ex5_nia[66]} {u_ila_0_cpl_spr_ex5_nia[65]} {u_ila_0_cpl_spr_ex5_nia[64]} {u_ila_0_cpl_spr_ex5_nia[63]} {u_ila_0_cpl_spr_ex5_nia[62]} {u_ila_0_cpl_spr_ex5_nia[61]} {u_ila_0_cpl_spr_ex5_nia[60]} {u_ila_0_cpl_spr_ex5_nia[59]} {u_ila_0_cpl_spr_ex5_nia[58]} {u_ila_0_cpl_spr_ex5_nia[57]} {u_ila_0_cpl_spr_ex5_nia[56]} {u_ila_0_cpl_spr_ex5_nia[55]} {u_ila_0_cpl_spr_ex5_nia[54]} {u_ila_0_cpl_spr_ex5_nia[53]} {u_ila_0_cpl_spr_ex5_nia[52]} {u_ila_0_cpl_spr_ex5_nia[51]} {u_ila_0_cpl_spr_ex5_nia[50]} {u_ila_0_cpl_spr_ex5_nia[49]} {u_ila_0_cpl_spr_ex5_nia[48]} {u_ila_0_cpl_spr_ex5_nia[47]} {u_ila_0_cpl_spr_ex5_nia[46]} {u_ila_0_cpl_spr_ex5_nia[45]} {u_ila_0_cpl_spr_ex5_nia[44]} {u_ila_0_cpl_spr_ex5_nia[43]} {u_ila_0_cpl_spr_ex5_nia[42]} {u_ila_0_cpl_spr_ex5_nia[41]} {u_ila_0_cpl_spr_ex5_nia[40]} {u_ila_0_cpl_spr_ex5_nia[39]} {u_ila_0_cpl_spr_ex5_nia[38]} {u_ila_0_cpl_spr_ex5_nia[37]} {u_ila_0_cpl_spr_ex5_nia[36]} {u_ila_0_cpl_spr_ex5_nia[35]} {u_ila_0_cpl_spr_ex5_nia[34]} {u_ila_0_cpl_spr_ex5_nia[33]} {u_ila_0_cpl_spr_ex5_nia[32]} {u_ila_0_cpl_spr_ex5_nia[31]} {u_ila_0_cpl_spr_ex5_nia[30]} {u_ila_0_cpl_spr_ex5_nia[29]} {u_ila_0_cpl_spr_ex5_nia[28]} {u_ila_0_cpl_spr_ex5_nia[27]} {u_ila_0_cpl_spr_ex5_nia[26]} {u_ila_0_cpl_spr_ex5_nia[25]} {u_ila_0_cpl_spr_ex5_nia[24]} {u_ila_0_cpl_spr_ex5_nia[23]} {u_ila_0_cpl_spr_ex5_nia[22]} {u_ila_0_cpl_spr_ex5_nia[21]} {u_ila_0_cpl_spr_ex5_nia[20]} {u_ila_0_cpl_spr_ex5_nia[19]} {u_ila_0_cpl_spr_ex5_nia[18]} {u_ila_0_cpl_spr_ex5_nia[17]} {u_ila_0_cpl_spr_ex5_nia[16]} {u_ila_0_cpl_spr_ex5_nia[15]} {u_ila_0_cpl_spr_ex5_nia[14]} {u_ila_0_cpl_spr_ex5_nia[13]} {u_ila_0_cpl_spr_ex5_nia[12]} {u_ila_0_cpl_spr_ex5_nia[11]} {u_ila_0_cpl_spr_ex5_nia[10]} {u_ila_0_cpl_spr_ex5_nia[9]} {u_ila_0_cpl_spr_ex5_nia[8]} {u_ila_0_cpl_spr_ex5_nia[7]} {u_ila_0_cpl_spr_ex5_nia[6]} {u_ila_0_cpl_spr_ex5_nia[5]} {u_ila_0_cpl_spr_ex5_nia[4]} {u_ila_0_cpl_spr_ex5_nia[3]} {u_ila_0_cpl_spr_ex5_nia[2]} {u_ila_0_cpl_spr_ex5_nia[1]} {u_ila_0_cpl_spr_ex5_nia[0]}]] +connect_debug_port u_ila_0/probe3 [get_nets [list {u_ila_0_dout[31]} {u_ila_0_dout[30]} {u_ila_0_dout[29]} {u_ila_0_dout[28]} {u_ila_0_dout[27]} {u_ila_0_dout[26]} {u_ila_0_dout[25]} {u_ila_0_dout[24]} {u_ila_0_dout[23]} {u_ila_0_dout[22]} {u_ila_0_dout[21]} {u_ila_0_dout[20]} {u_ila_0_dout[19]} {u_ila_0_dout[18]} {u_ila_0_dout[17]} {u_ila_0_dout[16]} {u_ila_0_dout[15]} {u_ila_0_dout[14]} {u_ila_0_dout[13]} {u_ila_0_dout[12]} {u_ila_0_dout[11]} {u_ila_0_dout[10]} {u_ila_0_dout[9]} {u_ila_0_dout[8]} {u_ila_0_dout[7]} {u_ila_0_dout[6]} {u_ila_0_dout[5]} {u_ila_0_dout[4]} {u_ila_0_dout[3]} {u_ila_0_dout[2]} {u_ila_0_dout[1]} {u_ila_0_dout[0]}]] + +connect_debug_port u_ila_0/probe2 [get_nets [list {u_ila_0_cpl_spr_ex5_nia[247]} {u_ila_0_cpl_spr_ex5_nia[246]} {u_ila_0_cpl_spr_ex5_nia[245]} {u_ila_0_cpl_spr_ex5_nia[244]} {u_ila_0_cpl_spr_ex5_nia[243]} {u_ila_0_cpl_spr_ex5_nia[242]} {u_ila_0_cpl_spr_ex5_nia[241]} {u_ila_0_cpl_spr_ex5_nia[240]} {u_ila_0_cpl_spr_ex5_nia[239]} {u_ila_0_cpl_spr_ex5_nia[238]} {u_ila_0_cpl_spr_ex5_nia[237]} {u_ila_0_cpl_spr_ex5_nia[236]} {u_ila_0_cpl_spr_ex5_nia[235]} {u_ila_0_cpl_spr_ex5_nia[234]} {u_ila_0_cpl_spr_ex5_nia[233]} {u_ila_0_cpl_spr_ex5_nia[232]} {u_ila_0_cpl_spr_ex5_nia[231]} {u_ila_0_cpl_spr_ex5_nia[230]} {u_ila_0_cpl_spr_ex5_nia[229]} {u_ila_0_cpl_spr_ex5_nia[228]} {u_ila_0_cpl_spr_ex5_nia[227]} {u_ila_0_cpl_spr_ex5_nia[226]} {u_ila_0_cpl_spr_ex5_nia[225]} {u_ila_0_cpl_spr_ex5_nia[224]} {u_ila_0_cpl_spr_ex5_nia[223]} {u_ila_0_cpl_spr_ex5_nia[222]} {u_ila_0_cpl_spr_ex5_nia[221]} {u_ila_0_cpl_spr_ex5_nia[220]} {u_ila_0_cpl_spr_ex5_nia[219]} {u_ila_0_cpl_spr_ex5_nia[218]} {u_ila_0_cpl_spr_ex5_nia[217]} {u_ila_0_cpl_spr_ex5_nia[216]} {u_ila_0_cpl_spr_ex5_nia[215]} {u_ila_0_cpl_spr_ex5_nia[214]} {u_ila_0_cpl_spr_ex5_nia[213]} {u_ila_0_cpl_spr_ex5_nia[212]} {u_ila_0_cpl_spr_ex5_nia[211]} {u_ila_0_cpl_spr_ex5_nia[210]} {u_ila_0_cpl_spr_ex5_nia[209]} {u_ila_0_cpl_spr_ex5_nia[208]} {u_ila_0_cpl_spr_ex5_nia[207]} {u_ila_0_cpl_spr_ex5_nia[206]} {u_ila_0_cpl_spr_ex5_nia[205]} {u_ila_0_cpl_spr_ex5_nia[204]} {u_ila_0_cpl_spr_ex5_nia[203]} {u_ila_0_cpl_spr_ex5_nia[202]} {u_ila_0_cpl_spr_ex5_nia[201]} {u_ila_0_cpl_spr_ex5_nia[200]} {u_ila_0_cpl_spr_ex5_nia[199]} {u_ila_0_cpl_spr_ex5_nia[198]} {u_ila_0_cpl_spr_ex5_nia[197]} {u_ila_0_cpl_spr_ex5_nia[196]} {u_ila_0_cpl_spr_ex5_nia[195]} {u_ila_0_cpl_spr_ex5_nia[194]} {u_ila_0_cpl_spr_ex5_nia[193]} {u_ila_0_cpl_spr_ex5_nia[192]} {u_ila_0_cpl_spr_ex5_nia[191]} {u_ila_0_cpl_spr_ex5_nia[190]} {u_ila_0_cpl_spr_ex5_nia[189]} {u_ila_0_cpl_spr_ex5_nia[188]} {u_ila_0_cpl_spr_ex5_nia[187]} {u_ila_0_cpl_spr_ex5_nia[186]} {u_ila_0_cpl_spr_ex5_nia[185]} {u_ila_0_cpl_spr_ex5_nia[184]} {u_ila_0_cpl_spr_ex5_nia[183]} {u_ila_0_cpl_spr_ex5_nia[182]} {u_ila_0_cpl_spr_ex5_nia[181]} {u_ila_0_cpl_spr_ex5_nia[180]} {u_ila_0_cpl_spr_ex5_nia[179]} {u_ila_0_cpl_spr_ex5_nia[178]} {u_ila_0_cpl_spr_ex5_nia[177]} {u_ila_0_cpl_spr_ex5_nia[176]} {u_ila_0_cpl_spr_ex5_nia[175]} {u_ila_0_cpl_spr_ex5_nia[174]} {u_ila_0_cpl_spr_ex5_nia[173]} {u_ila_0_cpl_spr_ex5_nia[172]} {u_ila_0_cpl_spr_ex5_nia[171]} {u_ila_0_cpl_spr_ex5_nia[170]} {u_ila_0_cpl_spr_ex5_nia[169]} {u_ila_0_cpl_spr_ex5_nia[168]} {u_ila_0_cpl_spr_ex5_nia[167]} {u_ila_0_cpl_spr_ex5_nia[166]} {u_ila_0_cpl_spr_ex5_nia[165]} {u_ila_0_cpl_spr_ex5_nia[164]} {u_ila_0_cpl_spr_ex5_nia[163]} {u_ila_0_cpl_spr_ex5_nia[162]} {u_ila_0_cpl_spr_ex5_nia[161]} {u_ila_0_cpl_spr_ex5_nia[160]} {u_ila_0_cpl_spr_ex5_nia[159]} {u_ila_0_cpl_spr_ex5_nia[158]} {u_ila_0_cpl_spr_ex5_nia[157]} {u_ila_0_cpl_spr_ex5_nia[156]} {u_ila_0_cpl_spr_ex5_nia[155]} {u_ila_0_cpl_spr_ex5_nia[154]} {u_ila_0_cpl_spr_ex5_nia[153]} {u_ila_0_cpl_spr_ex5_nia[152]} {u_ila_0_cpl_spr_ex5_nia[151]} {u_ila_0_cpl_spr_ex5_nia[150]} {u_ila_0_cpl_spr_ex5_nia[149]} {u_ila_0_cpl_spr_ex5_nia[148]} {u_ila_0_cpl_spr_ex5_nia[147]} {u_ila_0_cpl_spr_ex5_nia[146]} {u_ila_0_cpl_spr_ex5_nia[145]} {u_ila_0_cpl_spr_ex5_nia[144]} {u_ila_0_cpl_spr_ex5_nia[143]} {u_ila_0_cpl_spr_ex5_nia[142]} {u_ila_0_cpl_spr_ex5_nia[141]} {u_ila_0_cpl_spr_ex5_nia[140]} {u_ila_0_cpl_spr_ex5_nia[139]} {u_ila_0_cpl_spr_ex5_nia[138]} {u_ila_0_cpl_spr_ex5_nia[137]} {u_ila_0_cpl_spr_ex5_nia[136]} {u_ila_0_cpl_spr_ex5_nia[135]} {u_ila_0_cpl_spr_ex5_nia[134]} {u_ila_0_cpl_spr_ex5_nia[133]} {u_ila_0_cpl_spr_ex5_nia[132]} {u_ila_0_cpl_spr_ex5_nia[131]} {u_ila_0_cpl_spr_ex5_nia[130]} {u_ila_0_cpl_spr_ex5_nia[129]} {u_ila_0_cpl_spr_ex5_nia[128]} {u_ila_0_cpl_spr_ex5_nia[127]} {u_ila_0_cpl_spr_ex5_nia[126]} {u_ila_0_cpl_spr_ex5_nia[125]} {u_ila_0_cpl_spr_ex5_nia[124]} {u_ila_0_cpl_spr_ex5_nia[123]} {u_ila_0_cpl_spr_ex5_nia[122]} {u_ila_0_cpl_spr_ex5_nia[121]} {u_ila_0_cpl_spr_ex5_nia[120]} {u_ila_0_cpl_spr_ex5_nia[119]} {u_ila_0_cpl_spr_ex5_nia[118]} {u_ila_0_cpl_spr_ex5_nia[117]} {u_ila_0_cpl_spr_ex5_nia[116]} {u_ila_0_cpl_spr_ex5_nia[115]} {u_ila_0_cpl_spr_ex5_nia[114]} {u_ila_0_cpl_spr_ex5_nia[113]} {u_ila_0_cpl_spr_ex5_nia[112]} {u_ila_0_cpl_spr_ex5_nia[111]} {u_ila_0_cpl_spr_ex5_nia[110]} {u_ila_0_cpl_spr_ex5_nia[109]} {u_ila_0_cpl_spr_ex5_nia[108]} {u_ila_0_cpl_spr_ex5_nia[107]} {u_ila_0_cpl_spr_ex5_nia[106]} {u_ila_0_cpl_spr_ex5_nia[105]} {u_ila_0_cpl_spr_ex5_nia[104]} {u_ila_0_cpl_spr_ex5_nia[103]} {u_ila_0_cpl_spr_ex5_nia[102]} {u_ila_0_cpl_spr_ex5_nia[101]} {u_ila_0_cpl_spr_ex5_nia[100]} {u_ila_0_cpl_spr_ex5_nia[99]} {u_ila_0_cpl_spr_ex5_nia[98]} {u_ila_0_cpl_spr_ex5_nia[97]} {u_ila_0_cpl_spr_ex5_nia[96]} {u_ila_0_cpl_spr_ex5_nia[95]} {u_ila_0_cpl_spr_ex5_nia[94]} {u_ila_0_cpl_spr_ex5_nia[93]} {u_ila_0_cpl_spr_ex5_nia[92]} {u_ila_0_cpl_spr_ex5_nia[91]} {u_ila_0_cpl_spr_ex5_nia[90]} {u_ila_0_cpl_spr_ex5_nia[89]} {u_ila_0_cpl_spr_ex5_nia[88]} {u_ila_0_cpl_spr_ex5_nia[87]} {u_ila_0_cpl_spr_ex5_nia[86]} {u_ila_0_cpl_spr_ex5_nia[85]} {u_ila_0_cpl_spr_ex5_nia[84]} {u_ila_0_cpl_spr_ex5_nia[83]} {u_ila_0_cpl_spr_ex5_nia[82]} {u_ila_0_cpl_spr_ex5_nia[81]} {u_ila_0_cpl_spr_ex5_nia[80]} {u_ila_0_cpl_spr_ex5_nia[79]} {u_ila_0_cpl_spr_ex5_nia[78]} {u_ila_0_cpl_spr_ex5_nia[77]} {u_ila_0_cpl_spr_ex5_nia[76]} {u_ila_0_cpl_spr_ex5_nia[75]} {u_ila_0_cpl_spr_ex5_nia[74]} {u_ila_0_cpl_spr_ex5_nia[73]} {u_ila_0_cpl_spr_ex5_nia[72]} {u_ila_0_cpl_spr_ex5_nia[71]} {u_ila_0_cpl_spr_ex5_nia[70]} {u_ila_0_cpl_spr_ex5_nia[69]} {u_ila_0_cpl_spr_ex5_nia[68]} {u_ila_0_cpl_spr_ex5_nia[67]} {u_ila_0_cpl_spr_ex5_nia[66]} {u_ila_0_cpl_spr_ex5_nia[65]} {u_ila_0_cpl_spr_ex5_nia[64]} {u_ila_0_cpl_spr_ex5_nia[63]} {u_ila_0_cpl_spr_ex5_nia[62]} {u_ila_0_cpl_spr_ex5_nia[61]} {u_ila_0_cpl_spr_ex5_nia[60]} {u_ila_0_cpl_spr_ex5_nia[59]} {u_ila_0_cpl_spr_ex5_nia[58]} {u_ila_0_cpl_spr_ex5_nia[57]} {u_ila_0_cpl_spr_ex5_nia[56]} {u_ila_0_cpl_spr_ex5_nia[55]} {u_ila_0_cpl_spr_ex5_nia[54]} {u_ila_0_cpl_spr_ex5_nia[53]} {u_ila_0_cpl_spr_ex5_nia[52]} {u_ila_0_cpl_spr_ex5_nia[51]} {u_ila_0_cpl_spr_ex5_nia[50]} {u_ila_0_cpl_spr_ex5_nia[49]} {u_ila_0_cpl_spr_ex5_nia[48]} {u_ila_0_cpl_spr_ex5_nia[47]} {u_ila_0_cpl_spr_ex5_nia[46]} {u_ila_0_cpl_spr_ex5_nia[45]} {u_ila_0_cpl_spr_ex5_nia[44]} {u_ila_0_cpl_spr_ex5_nia[43]} {u_ila_0_cpl_spr_ex5_nia[42]} {u_ila_0_cpl_spr_ex5_nia[41]} {u_ila_0_cpl_spr_ex5_nia[40]} {u_ila_0_cpl_spr_ex5_nia[39]} {u_ila_0_cpl_spr_ex5_nia[38]} {u_ila_0_cpl_spr_ex5_nia[37]} {u_ila_0_cpl_spr_ex5_nia[36]} {u_ila_0_cpl_spr_ex5_nia[35]} {u_ila_0_cpl_spr_ex5_nia[34]} {u_ila_0_cpl_spr_ex5_nia[33]} {u_ila_0_cpl_spr_ex5_nia[32]} {u_ila_0_cpl_spr_ex5_nia[31]} {u_ila_0_cpl_spr_ex5_nia[30]} {u_ila_0_cpl_spr_ex5_nia[29]} {u_ila_0_cpl_spr_ex5_nia[28]} {u_ila_0_cpl_spr_ex5_nia[27]} {u_ila_0_cpl_spr_ex5_nia[26]} {u_ila_0_cpl_spr_ex5_nia[25]} {u_ila_0_cpl_spr_ex5_nia[24]} {u_ila_0_cpl_spr_ex5_nia[23]} {u_ila_0_cpl_spr_ex5_nia[22]} {u_ila_0_cpl_spr_ex5_nia[21]} {u_ila_0_cpl_spr_ex5_nia[20]} {u_ila_0_cpl_spr_ex5_nia[19]} {u_ila_0_cpl_spr_ex5_nia[18]} {u_ila_0_cpl_spr_ex5_nia[17]} {u_ila_0_cpl_spr_ex5_nia[16]} {u_ila_0_cpl_spr_ex5_nia[15]} {u_ila_0_cpl_spr_ex5_nia[14]} {u_ila_0_cpl_spr_ex5_nia[13]} {u_ila_0_cpl_spr_ex5_nia[12]} {u_ila_0_cpl_spr_ex5_nia[11]} {u_ila_0_cpl_spr_ex5_nia[10]} {u_ila_0_cpl_spr_ex5_nia[9]} {u_ila_0_cpl_spr_ex5_nia[8]} {u_ila_0_cpl_spr_ex5_nia[7]} {u_ila_0_cpl_spr_ex5_nia[6]} {u_ila_0_cpl_spr_ex5_nia[5]} {u_ila_0_cpl_spr_ex5_nia[4]} {u_ila_0_cpl_spr_ex5_nia[3]} {u_ila_0_cpl_spr_ex5_nia[2]} {u_ila_0_cpl_spr_ex5_nia[1]} {u_ila_0_cpl_spr_ex5_nia[0]}]] +connect_debug_port u_ila_0/probe3 [get_nets [list {u_ila_0_dout[31]} {u_ila_0_dout[30]} {u_ila_0_dout[29]} {u_ila_0_dout[28]} {u_ila_0_dout[27]} {u_ila_0_dout[26]} {u_ila_0_dout[25]} {u_ila_0_dout[24]} {u_ila_0_dout[23]} {u_ila_0_dout[22]} {u_ila_0_dout[21]} {u_ila_0_dout[20]} {u_ila_0_dout[19]} {u_ila_0_dout[18]} {u_ila_0_dout[17]} {u_ila_0_dout[16]} {u_ila_0_dout[15]} {u_ila_0_dout[14]} {u_ila_0_dout[13]} {u_ila_0_dout[12]} {u_ila_0_dout[11]} {u_ila_0_dout[10]} {u_ila_0_dout[9]} {u_ila_0_dout[8]} {u_ila_0_dout[7]} {u_ila_0_dout[6]} {u_ila_0_dout[5]} {u_ila_0_dout[4]} {u_ila_0_dout[3]} {u_ila_0_dout[2]} {u_ila_0_dout[1]} {u_ila_0_dout[0]}]] + + +connect_debug_port u_ila_0/probe1 [get_nets [list {u_ila_0_cpl_spr_ex5_nia[247]} {u_ila_0_cpl_spr_ex5_nia[246]} {u_ila_0_cpl_spr_ex5_nia[245]} {u_ila_0_cpl_spr_ex5_nia[244]} {u_ila_0_cpl_spr_ex5_nia[243]} {u_ila_0_cpl_spr_ex5_nia[242]} {u_ila_0_cpl_spr_ex5_nia[241]} {u_ila_0_cpl_spr_ex5_nia[240]} {u_ila_0_cpl_spr_ex5_nia[239]} {u_ila_0_cpl_spr_ex5_nia[238]} {u_ila_0_cpl_spr_ex5_nia[237]} {u_ila_0_cpl_spr_ex5_nia[236]} {u_ila_0_cpl_spr_ex5_nia[235]} {u_ila_0_cpl_spr_ex5_nia[234]} {u_ila_0_cpl_spr_ex5_nia[233]} {u_ila_0_cpl_spr_ex5_nia[232]} {u_ila_0_cpl_spr_ex5_nia[231]} {u_ila_0_cpl_spr_ex5_nia[230]} {u_ila_0_cpl_spr_ex5_nia[229]} {u_ila_0_cpl_spr_ex5_nia[228]} {u_ila_0_cpl_spr_ex5_nia[227]} {u_ila_0_cpl_spr_ex5_nia[226]} {u_ila_0_cpl_spr_ex5_nia[225]} {u_ila_0_cpl_spr_ex5_nia[224]} {u_ila_0_cpl_spr_ex5_nia[223]} {u_ila_0_cpl_spr_ex5_nia[222]} {u_ila_0_cpl_spr_ex5_nia[221]} {u_ila_0_cpl_spr_ex5_nia[220]} {u_ila_0_cpl_spr_ex5_nia[219]} {u_ila_0_cpl_spr_ex5_nia[218]} {u_ila_0_cpl_spr_ex5_nia[217]} {u_ila_0_cpl_spr_ex5_nia[216]} {u_ila_0_cpl_spr_ex5_nia[215]} {u_ila_0_cpl_spr_ex5_nia[214]} {u_ila_0_cpl_spr_ex5_nia[213]} {u_ila_0_cpl_spr_ex5_nia[212]} {u_ila_0_cpl_spr_ex5_nia[211]} {u_ila_0_cpl_spr_ex5_nia[210]} {u_ila_0_cpl_spr_ex5_nia[209]} {u_ila_0_cpl_spr_ex5_nia[208]} {u_ila_0_cpl_spr_ex5_nia[207]} {u_ila_0_cpl_spr_ex5_nia[206]} {u_ila_0_cpl_spr_ex5_nia[205]} {u_ila_0_cpl_spr_ex5_nia[204]} {u_ila_0_cpl_spr_ex5_nia[203]} {u_ila_0_cpl_spr_ex5_nia[202]} {u_ila_0_cpl_spr_ex5_nia[201]} {u_ila_0_cpl_spr_ex5_nia[200]} {u_ila_0_cpl_spr_ex5_nia[199]} {u_ila_0_cpl_spr_ex5_nia[198]} {u_ila_0_cpl_spr_ex5_nia[197]} {u_ila_0_cpl_spr_ex5_nia[196]} {u_ila_0_cpl_spr_ex5_nia[195]} {u_ila_0_cpl_spr_ex5_nia[194]} {u_ila_0_cpl_spr_ex5_nia[193]} {u_ila_0_cpl_spr_ex5_nia[192]} {u_ila_0_cpl_spr_ex5_nia[191]} {u_ila_0_cpl_spr_ex5_nia[190]} {u_ila_0_cpl_spr_ex5_nia[189]} {u_ila_0_cpl_spr_ex5_nia[188]} {u_ila_0_cpl_spr_ex5_nia[187]} {u_ila_0_cpl_spr_ex5_nia[186]} {u_ila_0_cpl_spr_ex5_nia[185]} {u_ila_0_cpl_spr_ex5_nia[184]} {u_ila_0_cpl_spr_ex5_nia[183]} {u_ila_0_cpl_spr_ex5_nia[182]} {u_ila_0_cpl_spr_ex5_nia[181]} {u_ila_0_cpl_spr_ex5_nia[180]} {u_ila_0_cpl_spr_ex5_nia[179]} {u_ila_0_cpl_spr_ex5_nia[178]} {u_ila_0_cpl_spr_ex5_nia[177]} {u_ila_0_cpl_spr_ex5_nia[176]} {u_ila_0_cpl_spr_ex5_nia[175]} {u_ila_0_cpl_spr_ex5_nia[174]} {u_ila_0_cpl_spr_ex5_nia[173]} {u_ila_0_cpl_spr_ex5_nia[172]} {u_ila_0_cpl_spr_ex5_nia[171]} {u_ila_0_cpl_spr_ex5_nia[170]} {u_ila_0_cpl_spr_ex5_nia[169]} {u_ila_0_cpl_spr_ex5_nia[168]} {u_ila_0_cpl_spr_ex5_nia[167]} {u_ila_0_cpl_spr_ex5_nia[166]} {u_ila_0_cpl_spr_ex5_nia[165]} {u_ila_0_cpl_spr_ex5_nia[164]} {u_ila_0_cpl_spr_ex5_nia[163]} {u_ila_0_cpl_spr_ex5_nia[162]} {u_ila_0_cpl_spr_ex5_nia[161]} {u_ila_0_cpl_spr_ex5_nia[160]} {u_ila_0_cpl_spr_ex5_nia[159]} {u_ila_0_cpl_spr_ex5_nia[158]} {u_ila_0_cpl_spr_ex5_nia[157]} {u_ila_0_cpl_spr_ex5_nia[156]} {u_ila_0_cpl_spr_ex5_nia[155]} {u_ila_0_cpl_spr_ex5_nia[154]} {u_ila_0_cpl_spr_ex5_nia[153]} {u_ila_0_cpl_spr_ex5_nia[152]} {u_ila_0_cpl_spr_ex5_nia[151]} {u_ila_0_cpl_spr_ex5_nia[150]} {u_ila_0_cpl_spr_ex5_nia[149]} {u_ila_0_cpl_spr_ex5_nia[148]} {u_ila_0_cpl_spr_ex5_nia[147]} {u_ila_0_cpl_spr_ex5_nia[146]} {u_ila_0_cpl_spr_ex5_nia[145]} {u_ila_0_cpl_spr_ex5_nia[144]} {u_ila_0_cpl_spr_ex5_nia[143]} {u_ila_0_cpl_spr_ex5_nia[142]} {u_ila_0_cpl_spr_ex5_nia[141]} {u_ila_0_cpl_spr_ex5_nia[140]} {u_ila_0_cpl_spr_ex5_nia[139]} {u_ila_0_cpl_spr_ex5_nia[138]} {u_ila_0_cpl_spr_ex5_nia[137]} {u_ila_0_cpl_spr_ex5_nia[136]} {u_ila_0_cpl_spr_ex5_nia[135]} {u_ila_0_cpl_spr_ex5_nia[134]} {u_ila_0_cpl_spr_ex5_nia[133]} {u_ila_0_cpl_spr_ex5_nia[132]} {u_ila_0_cpl_spr_ex5_nia[131]} {u_ila_0_cpl_spr_ex5_nia[130]} {u_ila_0_cpl_spr_ex5_nia[129]} {u_ila_0_cpl_spr_ex5_nia[128]} {u_ila_0_cpl_spr_ex5_nia[127]} {u_ila_0_cpl_spr_ex5_nia[126]} {u_ila_0_cpl_spr_ex5_nia[125]} {u_ila_0_cpl_spr_ex5_nia[124]} {u_ila_0_cpl_spr_ex5_nia[123]} {u_ila_0_cpl_spr_ex5_nia[122]} {u_ila_0_cpl_spr_ex5_nia[121]} {u_ila_0_cpl_spr_ex5_nia[120]} {u_ila_0_cpl_spr_ex5_nia[119]} {u_ila_0_cpl_spr_ex5_nia[118]} {u_ila_0_cpl_spr_ex5_nia[117]} {u_ila_0_cpl_spr_ex5_nia[116]} {u_ila_0_cpl_spr_ex5_nia[115]} {u_ila_0_cpl_spr_ex5_nia[114]} {u_ila_0_cpl_spr_ex5_nia[113]} {u_ila_0_cpl_spr_ex5_nia[112]} {u_ila_0_cpl_spr_ex5_nia[111]} {u_ila_0_cpl_spr_ex5_nia[110]} {u_ila_0_cpl_spr_ex5_nia[109]} {u_ila_0_cpl_spr_ex5_nia[108]} {u_ila_0_cpl_spr_ex5_nia[107]} {u_ila_0_cpl_spr_ex5_nia[106]} {u_ila_0_cpl_spr_ex5_nia[105]} {u_ila_0_cpl_spr_ex5_nia[104]} {u_ila_0_cpl_spr_ex5_nia[103]} {u_ila_0_cpl_spr_ex5_nia[102]} {u_ila_0_cpl_spr_ex5_nia[101]} {u_ila_0_cpl_spr_ex5_nia[100]} {u_ila_0_cpl_spr_ex5_nia[99]} {u_ila_0_cpl_spr_ex5_nia[98]} {u_ila_0_cpl_spr_ex5_nia[97]} {u_ila_0_cpl_spr_ex5_nia[96]} {u_ila_0_cpl_spr_ex5_nia[95]} {u_ila_0_cpl_spr_ex5_nia[94]} {u_ila_0_cpl_spr_ex5_nia[93]} {u_ila_0_cpl_spr_ex5_nia[92]} {u_ila_0_cpl_spr_ex5_nia[91]} {u_ila_0_cpl_spr_ex5_nia[90]} {u_ila_0_cpl_spr_ex5_nia[89]} {u_ila_0_cpl_spr_ex5_nia[88]} {u_ila_0_cpl_spr_ex5_nia[87]} {u_ila_0_cpl_spr_ex5_nia[86]} {u_ila_0_cpl_spr_ex5_nia[85]} {u_ila_0_cpl_spr_ex5_nia[84]} {u_ila_0_cpl_spr_ex5_nia[83]} {u_ila_0_cpl_spr_ex5_nia[82]} {u_ila_0_cpl_spr_ex5_nia[81]} {u_ila_0_cpl_spr_ex5_nia[80]} {u_ila_0_cpl_spr_ex5_nia[79]} {u_ila_0_cpl_spr_ex5_nia[78]} {u_ila_0_cpl_spr_ex5_nia[77]} {u_ila_0_cpl_spr_ex5_nia[76]} {u_ila_0_cpl_spr_ex5_nia[75]} {u_ila_0_cpl_spr_ex5_nia[74]} {u_ila_0_cpl_spr_ex5_nia[73]} {u_ila_0_cpl_spr_ex5_nia[72]} {u_ila_0_cpl_spr_ex5_nia[71]} {u_ila_0_cpl_spr_ex5_nia[70]} {u_ila_0_cpl_spr_ex5_nia[69]} {u_ila_0_cpl_spr_ex5_nia[68]} {u_ila_0_cpl_spr_ex5_nia[67]} {u_ila_0_cpl_spr_ex5_nia[66]} {u_ila_0_cpl_spr_ex5_nia[65]} {u_ila_0_cpl_spr_ex5_nia[64]} {u_ila_0_cpl_spr_ex5_nia[63]} {u_ila_0_cpl_spr_ex5_nia[62]} {u_ila_0_cpl_spr_ex5_nia[61]} {u_ila_0_cpl_spr_ex5_nia[60]} {u_ila_0_cpl_spr_ex5_nia[59]} {u_ila_0_cpl_spr_ex5_nia[58]} {u_ila_0_cpl_spr_ex5_nia[57]} {u_ila_0_cpl_spr_ex5_nia[56]} {u_ila_0_cpl_spr_ex5_nia[55]} {u_ila_0_cpl_spr_ex5_nia[54]} {u_ila_0_cpl_spr_ex5_nia[53]} {u_ila_0_cpl_spr_ex5_nia[52]} {u_ila_0_cpl_spr_ex5_nia[51]} {u_ila_0_cpl_spr_ex5_nia[50]} {u_ila_0_cpl_spr_ex5_nia[49]} {u_ila_0_cpl_spr_ex5_nia[48]} {u_ila_0_cpl_spr_ex5_nia[47]} {u_ila_0_cpl_spr_ex5_nia[46]} {u_ila_0_cpl_spr_ex5_nia[45]} {u_ila_0_cpl_spr_ex5_nia[44]} {u_ila_0_cpl_spr_ex5_nia[43]} {u_ila_0_cpl_spr_ex5_nia[42]} {u_ila_0_cpl_spr_ex5_nia[41]} {u_ila_0_cpl_spr_ex5_nia[40]} {u_ila_0_cpl_spr_ex5_nia[39]} {u_ila_0_cpl_spr_ex5_nia[38]} {u_ila_0_cpl_spr_ex5_nia[37]} {u_ila_0_cpl_spr_ex5_nia[36]} {u_ila_0_cpl_spr_ex5_nia[35]} {u_ila_0_cpl_spr_ex5_nia[34]} {u_ila_0_cpl_spr_ex5_nia[33]} {u_ila_0_cpl_spr_ex5_nia[32]} {u_ila_0_cpl_spr_ex5_nia[31]} {u_ila_0_cpl_spr_ex5_nia[30]} {u_ila_0_cpl_spr_ex5_nia[29]} {u_ila_0_cpl_spr_ex5_nia[28]} {u_ila_0_cpl_spr_ex5_nia[27]} {u_ila_0_cpl_spr_ex5_nia[26]} {u_ila_0_cpl_spr_ex5_nia[25]} {u_ila_0_cpl_spr_ex5_nia[24]} {u_ila_0_cpl_spr_ex5_nia[23]} {u_ila_0_cpl_spr_ex5_nia[22]} {u_ila_0_cpl_spr_ex5_nia[21]} {u_ila_0_cpl_spr_ex5_nia[20]} {u_ila_0_cpl_spr_ex5_nia[19]} {u_ila_0_cpl_spr_ex5_nia[18]} {u_ila_0_cpl_spr_ex5_nia[17]} {u_ila_0_cpl_spr_ex5_nia[16]} {u_ila_0_cpl_spr_ex5_nia[15]} {u_ila_0_cpl_spr_ex5_nia[14]} {u_ila_0_cpl_spr_ex5_nia[13]} {u_ila_0_cpl_spr_ex5_nia[12]} {u_ila_0_cpl_spr_ex5_nia[11]} {u_ila_0_cpl_spr_ex5_nia[10]} {u_ila_0_cpl_spr_ex5_nia[9]} {u_ila_0_cpl_spr_ex5_nia[8]} {u_ila_0_cpl_spr_ex5_nia[7]} {u_ila_0_cpl_spr_ex5_nia[6]} {u_ila_0_cpl_spr_ex5_nia[5]} {u_ila_0_cpl_spr_ex5_nia[4]} {u_ila_0_cpl_spr_ex5_nia[3]} {u_ila_0_cpl_spr_ex5_nia[2]} {u_ila_0_cpl_spr_ex5_nia[1]} {u_ila_0_cpl_spr_ex5_nia[0]}]] +connect_debug_port u_ila_0/probe2 [get_nets [list {u_ila_0_dout[31]} {u_ila_0_dout[30]} {u_ila_0_dout[29]} {u_ila_0_dout[28]} {u_ila_0_dout[27]} {u_ila_0_dout[26]} {u_ila_0_dout[25]} {u_ila_0_dout[24]} {u_ila_0_dout[23]} {u_ila_0_dout[22]} {u_ila_0_dout[21]} {u_ila_0_dout[20]} {u_ila_0_dout[19]} {u_ila_0_dout[18]} {u_ila_0_dout[17]} {u_ila_0_dout[16]} {u_ila_0_dout[15]} {u_ila_0_dout[14]} {u_ila_0_dout[13]} {u_ila_0_dout[12]} {u_ila_0_dout[11]} {u_ila_0_dout[10]} {u_ila_0_dout[9]} {u_ila_0_dout[8]} {u_ila_0_dout[7]} {u_ila_0_dout[6]} {u_ila_0_dout[5]} {u_ila_0_dout[4]} {u_ila_0_dout[3]} {u_ila_0_dout[2]} {u_ila_0_dout[1]} {u_ila_0_dout[0]}]] + +set_property MARK_DEBUG true [get_nets a2x_axi_bd_i/a2x_reset_0/reset] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[13]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[17]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[3]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[25]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[23]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[21]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[19]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[15]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[1]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[5]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[8]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[9]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[41]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[39]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[37]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[35]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[33]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[31]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[29]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[47]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[45]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[43]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[59]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[61]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[63]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[27]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[49]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[51]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[53]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[55]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[57]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[11]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[12]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[0]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[24]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[22]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[20]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[18]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[16]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[14]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[2]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[4]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[6]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[7]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[10]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[40]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[38]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[36]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[34]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[32]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[30]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[28]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[26]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[54]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[56]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[50]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[52]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[48]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[46]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[44]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[42]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[62]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[58]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[60]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[31]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[3]}] +set_property MARK_DEBUG true [get_nets a2x_axi_bd_i/a2x_axi_1/m00_axi_bready] +set_property MARK_DEBUG true [get_nets a2x_axi_bd_i/a2x_axi_1/m00_axi_wlast] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[9]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[11]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[15]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[19]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[23]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[27]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[2]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[10]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[6]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[14]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[18]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[26]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[22]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[30]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[9]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_bresp[1]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[3]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[15]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[11]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[23]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[19]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[31]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[27]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[1]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[8]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[17]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[25]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[29]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[21]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[13]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[5]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[24]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[16]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[0]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[4]}] +set_property MARK_DEBUG true [get_nets a2x_axi_bd_i/a2x_axi_1/m00_axi_awready] +set_property MARK_DEBUG true [get_nets a2x_axi_bd_i/a2x_axi_1/m00_axi_wready] +set_property MARK_DEBUG true [get_nets a2x_axi_bd_i/a2x_axi_1/m00_axi_rlast] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[7]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[12]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[20]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[28]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[3]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[11]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[9]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[19]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[15]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[27]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[23]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[31]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[0]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[4]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[7]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[16]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[12]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[24]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[20]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[28]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[2]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[10]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[18]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[26]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[30]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[22]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[14]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[6]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[4]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[17]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[13]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[1]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[5]}] +set_property MARK_DEBUG true [get_nets a2x_axi_bd_i/a2x_axi_1/m00_axi_arready] +set_property MARK_DEBUG true [get_nets a2x_axi_bd_i/a2x_axi_1/m00_axi_rready] +set_property MARK_DEBUG true [get_nets a2x_axi_bd_i/a2x_axi_1/m00_axi_wvalid] +set_property MARK_DEBUG true [get_nets a2x_axi_bd_i/a2x_axi_1/m00_axi_bvalid] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[8]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[21]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[29]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[25]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[0]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[12]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[7]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[20]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[16]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[28]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[24]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[1]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[8]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[5]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[17]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[13]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[25]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[21]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[29]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[3]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[11]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[19]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[27]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[31]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[23]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[15]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[9]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[26]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[18]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[2]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[6]}] +set_property MARK_DEBUG true [get_nets a2x_axi_bd_i/a2x_axi_1/m00_axi_rvalid] +set_property MARK_DEBUG true [get_nets a2x_axi_bd_i/a2x_axi_1/m00_axi_arvalid] +set_property MARK_DEBUG true [get_nets a2x_axi_bd_i/a2x_axi_1/m00_axi_awvalid] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[14]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[10]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[22]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[30]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[5]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[1]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[13]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[8]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[21]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[17]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[29]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[25]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[2]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_bresp[0]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[10]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[6]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[18]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[14]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[26]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[22]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[30]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[0]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[4]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[12]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[20]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[28]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[24]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[16]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[7]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[0]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[1]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[2]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[3]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[4]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[5]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[6]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[7]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[8]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[9]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[10]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[11]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[12]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[13]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[14]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[15]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[16]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[17]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[18]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[19]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[20]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[21]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[22]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[23]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[24]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[25]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[26]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[27]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[28]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[29]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[30]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[31]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[19]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[3]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[0]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[26]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[27]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[24]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[25]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[22]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[23]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[20]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[21]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[18]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[16]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[17]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[14]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[15]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[12]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[30]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[31]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[28]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[29]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[13]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[1]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[2]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[4]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[5]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[6]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[7]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[8]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[9]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[10]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[11]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[19]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[3]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[0]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[26]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[27]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[24]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[25]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[22]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[23]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[20]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[21]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[18]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[16]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[17]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[14]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[15]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[12]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[30]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[31]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[28]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[29]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[13]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[1]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[2]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[4]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[5]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[6]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[7]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[8]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[9]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[10]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[11]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[21]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[18]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[19]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[20]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[22]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[23]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[24]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[25]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[26]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[27]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[28]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[29]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[30]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[31]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/ila_axi_protocol/TRIG_OUT_trig[0]}] +set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/ila_axi_protocol/TRIG_OUT_ack[0]}] +create_debug_core u_ila_0 ila +set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] +set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0] +set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0] +set_property C_DATA_DEPTH 8192 [get_debug_cores u_ila_0] +set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0] +set_property C_INPUT_PIPE_STAGES 3 [get_debug_cores u_ila_0] +set_property C_TRIGIN_EN false [get_debug_cores u_ila_0] +set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] +set_property port_width 1 [get_debug_ports u_ila_0/clk] +connect_debug_port u_ila_0/clk [get_nets [list clk]] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] +set_property port_width 248 [get_debug_ports u_ila_0/probe0] +connect_debug_port u_ila_0/probe0 [get_nets [list {u_ila_0_cpl_spr_ex5_nia[247]} {u_ila_0_cpl_spr_ex5_nia[246]} {u_ila_0_cpl_spr_ex5_nia[245]} {u_ila_0_cpl_spr_ex5_nia[244]} {u_ila_0_cpl_spr_ex5_nia[243]} {u_ila_0_cpl_spr_ex5_nia[242]} {u_ila_0_cpl_spr_ex5_nia[241]} {u_ila_0_cpl_spr_ex5_nia[240]} {u_ila_0_cpl_spr_ex5_nia[239]} {u_ila_0_cpl_spr_ex5_nia[238]} {u_ila_0_cpl_spr_ex5_nia[237]} {u_ila_0_cpl_spr_ex5_nia[236]} {u_ila_0_cpl_spr_ex5_nia[235]} {u_ila_0_cpl_spr_ex5_nia[234]} {u_ila_0_cpl_spr_ex5_nia[233]} {u_ila_0_cpl_spr_ex5_nia[232]} {u_ila_0_cpl_spr_ex5_nia[231]} {u_ila_0_cpl_spr_ex5_nia[230]} {u_ila_0_cpl_spr_ex5_nia[229]} {u_ila_0_cpl_spr_ex5_nia[228]} {u_ila_0_cpl_spr_ex5_nia[227]} {u_ila_0_cpl_spr_ex5_nia[226]} {u_ila_0_cpl_spr_ex5_nia[225]} {u_ila_0_cpl_spr_ex5_nia[224]} {u_ila_0_cpl_spr_ex5_nia[223]} {u_ila_0_cpl_spr_ex5_nia[222]} {u_ila_0_cpl_spr_ex5_nia[221]} {u_ila_0_cpl_spr_ex5_nia[220]} {u_ila_0_cpl_spr_ex5_nia[219]} {u_ila_0_cpl_spr_ex5_nia[218]} {u_ila_0_cpl_spr_ex5_nia[217]} {u_ila_0_cpl_spr_ex5_nia[216]} {u_ila_0_cpl_spr_ex5_nia[215]} {u_ila_0_cpl_spr_ex5_nia[214]} {u_ila_0_cpl_spr_ex5_nia[213]} {u_ila_0_cpl_spr_ex5_nia[212]} {u_ila_0_cpl_spr_ex5_nia[211]} {u_ila_0_cpl_spr_ex5_nia[210]} {u_ila_0_cpl_spr_ex5_nia[209]} {u_ila_0_cpl_spr_ex5_nia[208]} {u_ila_0_cpl_spr_ex5_nia[207]} {u_ila_0_cpl_spr_ex5_nia[206]} {u_ila_0_cpl_spr_ex5_nia[205]} {u_ila_0_cpl_spr_ex5_nia[204]} {u_ila_0_cpl_spr_ex5_nia[203]} {u_ila_0_cpl_spr_ex5_nia[202]} {u_ila_0_cpl_spr_ex5_nia[201]} {u_ila_0_cpl_spr_ex5_nia[200]} {u_ila_0_cpl_spr_ex5_nia[199]} {u_ila_0_cpl_spr_ex5_nia[198]} {u_ila_0_cpl_spr_ex5_nia[197]} {u_ila_0_cpl_spr_ex5_nia[196]} {u_ila_0_cpl_spr_ex5_nia[195]} {u_ila_0_cpl_spr_ex5_nia[194]} {u_ila_0_cpl_spr_ex5_nia[193]} {u_ila_0_cpl_spr_ex5_nia[192]} {u_ila_0_cpl_spr_ex5_nia[191]} {u_ila_0_cpl_spr_ex5_nia[190]} {u_ila_0_cpl_spr_ex5_nia[189]} {u_ila_0_cpl_spr_ex5_nia[188]} {u_ila_0_cpl_spr_ex5_nia[187]} {u_ila_0_cpl_spr_ex5_nia[186]} {u_ila_0_cpl_spr_ex5_nia[185]} {u_ila_0_cpl_spr_ex5_nia[184]} {u_ila_0_cpl_spr_ex5_nia[183]} {u_ila_0_cpl_spr_ex5_nia[182]} {u_ila_0_cpl_spr_ex5_nia[181]} {u_ila_0_cpl_spr_ex5_nia[180]} {u_ila_0_cpl_spr_ex5_nia[179]} {u_ila_0_cpl_spr_ex5_nia[178]} {u_ila_0_cpl_spr_ex5_nia[177]} {u_ila_0_cpl_spr_ex5_nia[176]} {u_ila_0_cpl_spr_ex5_nia[175]} {u_ila_0_cpl_spr_ex5_nia[174]} {u_ila_0_cpl_spr_ex5_nia[173]} {u_ila_0_cpl_spr_ex5_nia[172]} {u_ila_0_cpl_spr_ex5_nia[171]} {u_ila_0_cpl_spr_ex5_nia[170]} {u_ila_0_cpl_spr_ex5_nia[169]} {u_ila_0_cpl_spr_ex5_nia[168]} {u_ila_0_cpl_spr_ex5_nia[167]} {u_ila_0_cpl_spr_ex5_nia[166]} {u_ila_0_cpl_spr_ex5_nia[165]} {u_ila_0_cpl_spr_ex5_nia[164]} {u_ila_0_cpl_spr_ex5_nia[163]} {u_ila_0_cpl_spr_ex5_nia[162]} {u_ila_0_cpl_spr_ex5_nia[161]} {u_ila_0_cpl_spr_ex5_nia[160]} {u_ila_0_cpl_spr_ex5_nia[159]} {u_ila_0_cpl_spr_ex5_nia[158]} {u_ila_0_cpl_spr_ex5_nia[157]} {u_ila_0_cpl_spr_ex5_nia[156]} {u_ila_0_cpl_spr_ex5_nia[155]} {u_ila_0_cpl_spr_ex5_nia[154]} {u_ila_0_cpl_spr_ex5_nia[153]} {u_ila_0_cpl_spr_ex5_nia[152]} {u_ila_0_cpl_spr_ex5_nia[151]} {u_ila_0_cpl_spr_ex5_nia[150]} {u_ila_0_cpl_spr_ex5_nia[149]} {u_ila_0_cpl_spr_ex5_nia[148]} {u_ila_0_cpl_spr_ex5_nia[147]} {u_ila_0_cpl_spr_ex5_nia[146]} {u_ila_0_cpl_spr_ex5_nia[145]} {u_ila_0_cpl_spr_ex5_nia[144]} {u_ila_0_cpl_spr_ex5_nia[143]} {u_ila_0_cpl_spr_ex5_nia[142]} {u_ila_0_cpl_spr_ex5_nia[141]} {u_ila_0_cpl_spr_ex5_nia[140]} {u_ila_0_cpl_spr_ex5_nia[139]} {u_ila_0_cpl_spr_ex5_nia[138]} {u_ila_0_cpl_spr_ex5_nia[137]} {u_ila_0_cpl_spr_ex5_nia[136]} {u_ila_0_cpl_spr_ex5_nia[135]} {u_ila_0_cpl_spr_ex5_nia[134]} {u_ila_0_cpl_spr_ex5_nia[133]} {u_ila_0_cpl_spr_ex5_nia[132]} {u_ila_0_cpl_spr_ex5_nia[131]} {u_ila_0_cpl_spr_ex5_nia[130]} {u_ila_0_cpl_spr_ex5_nia[129]} {u_ila_0_cpl_spr_ex5_nia[128]} {u_ila_0_cpl_spr_ex5_nia[127]} {u_ila_0_cpl_spr_ex5_nia[126]} {u_ila_0_cpl_spr_ex5_nia[125]} {u_ila_0_cpl_spr_ex5_nia[124]} {u_ila_0_cpl_spr_ex5_nia[123]} {u_ila_0_cpl_spr_ex5_nia[122]} {u_ila_0_cpl_spr_ex5_nia[121]} {u_ila_0_cpl_spr_ex5_nia[120]} {u_ila_0_cpl_spr_ex5_nia[119]} {u_ila_0_cpl_spr_ex5_nia[118]} {u_ila_0_cpl_spr_ex5_nia[117]} {u_ila_0_cpl_spr_ex5_nia[116]} {u_ila_0_cpl_spr_ex5_nia[115]} {u_ila_0_cpl_spr_ex5_nia[114]} {u_ila_0_cpl_spr_ex5_nia[113]} {u_ila_0_cpl_spr_ex5_nia[112]} {u_ila_0_cpl_spr_ex5_nia[111]} {u_ila_0_cpl_spr_ex5_nia[110]} {u_ila_0_cpl_spr_ex5_nia[109]} {u_ila_0_cpl_spr_ex5_nia[108]} {u_ila_0_cpl_spr_ex5_nia[107]} {u_ila_0_cpl_spr_ex5_nia[106]} {u_ila_0_cpl_spr_ex5_nia[105]} {u_ila_0_cpl_spr_ex5_nia[104]} {u_ila_0_cpl_spr_ex5_nia[103]} {u_ila_0_cpl_spr_ex5_nia[102]} {u_ila_0_cpl_spr_ex5_nia[101]} {u_ila_0_cpl_spr_ex5_nia[100]} {u_ila_0_cpl_spr_ex5_nia[99]} {u_ila_0_cpl_spr_ex5_nia[98]} {u_ila_0_cpl_spr_ex5_nia[97]} {u_ila_0_cpl_spr_ex5_nia[96]} {u_ila_0_cpl_spr_ex5_nia[95]} {u_ila_0_cpl_spr_ex5_nia[94]} {u_ila_0_cpl_spr_ex5_nia[93]} {u_ila_0_cpl_spr_ex5_nia[92]} {u_ila_0_cpl_spr_ex5_nia[91]} {u_ila_0_cpl_spr_ex5_nia[90]} {u_ila_0_cpl_spr_ex5_nia[89]} {u_ila_0_cpl_spr_ex5_nia[88]} {u_ila_0_cpl_spr_ex5_nia[87]} {u_ila_0_cpl_spr_ex5_nia[86]} {u_ila_0_cpl_spr_ex5_nia[85]} {u_ila_0_cpl_spr_ex5_nia[84]} {u_ila_0_cpl_spr_ex5_nia[83]} {u_ila_0_cpl_spr_ex5_nia[82]} {u_ila_0_cpl_spr_ex5_nia[81]} {u_ila_0_cpl_spr_ex5_nia[80]} {u_ila_0_cpl_spr_ex5_nia[79]} {u_ila_0_cpl_spr_ex5_nia[78]} {u_ila_0_cpl_spr_ex5_nia[77]} {u_ila_0_cpl_spr_ex5_nia[76]} {u_ila_0_cpl_spr_ex5_nia[75]} {u_ila_0_cpl_spr_ex5_nia[74]} {u_ila_0_cpl_spr_ex5_nia[73]} {u_ila_0_cpl_spr_ex5_nia[72]} {u_ila_0_cpl_spr_ex5_nia[71]} {u_ila_0_cpl_spr_ex5_nia[70]} {u_ila_0_cpl_spr_ex5_nia[69]} {u_ila_0_cpl_spr_ex5_nia[68]} {u_ila_0_cpl_spr_ex5_nia[67]} {u_ila_0_cpl_spr_ex5_nia[66]} {u_ila_0_cpl_spr_ex5_nia[65]} {u_ila_0_cpl_spr_ex5_nia[64]} {u_ila_0_cpl_spr_ex5_nia[63]} {u_ila_0_cpl_spr_ex5_nia[62]} {u_ila_0_cpl_spr_ex5_nia[61]} {u_ila_0_cpl_spr_ex5_nia[60]} {u_ila_0_cpl_spr_ex5_nia[59]} {u_ila_0_cpl_spr_ex5_nia[58]} {u_ila_0_cpl_spr_ex5_nia[57]} {u_ila_0_cpl_spr_ex5_nia[56]} {u_ila_0_cpl_spr_ex5_nia[55]} {u_ila_0_cpl_spr_ex5_nia[54]} {u_ila_0_cpl_spr_ex5_nia[53]} {u_ila_0_cpl_spr_ex5_nia[52]} {u_ila_0_cpl_spr_ex5_nia[51]} {u_ila_0_cpl_spr_ex5_nia[50]} {u_ila_0_cpl_spr_ex5_nia[49]} {u_ila_0_cpl_spr_ex5_nia[48]} {u_ila_0_cpl_spr_ex5_nia[47]} {u_ila_0_cpl_spr_ex5_nia[46]} {u_ila_0_cpl_spr_ex5_nia[45]} {u_ila_0_cpl_spr_ex5_nia[44]} {u_ila_0_cpl_spr_ex5_nia[43]} {u_ila_0_cpl_spr_ex5_nia[42]} {u_ila_0_cpl_spr_ex5_nia[41]} {u_ila_0_cpl_spr_ex5_nia[40]} {u_ila_0_cpl_spr_ex5_nia[39]} {u_ila_0_cpl_spr_ex5_nia[38]} {u_ila_0_cpl_spr_ex5_nia[37]} {u_ila_0_cpl_spr_ex5_nia[36]} {u_ila_0_cpl_spr_ex5_nia[35]} {u_ila_0_cpl_spr_ex5_nia[34]} {u_ila_0_cpl_spr_ex5_nia[33]} {u_ila_0_cpl_spr_ex5_nia[32]} {u_ila_0_cpl_spr_ex5_nia[31]} {u_ila_0_cpl_spr_ex5_nia[30]} {u_ila_0_cpl_spr_ex5_nia[29]} {u_ila_0_cpl_spr_ex5_nia[28]} {u_ila_0_cpl_spr_ex5_nia[27]} {u_ila_0_cpl_spr_ex5_nia[26]} {u_ila_0_cpl_spr_ex5_nia[25]} {u_ila_0_cpl_spr_ex5_nia[24]} {u_ila_0_cpl_spr_ex5_nia[23]} {u_ila_0_cpl_spr_ex5_nia[22]} {u_ila_0_cpl_spr_ex5_nia[21]} {u_ila_0_cpl_spr_ex5_nia[20]} {u_ila_0_cpl_spr_ex5_nia[19]} {u_ila_0_cpl_spr_ex5_nia[18]} {u_ila_0_cpl_spr_ex5_nia[17]} {u_ila_0_cpl_spr_ex5_nia[16]} {u_ila_0_cpl_spr_ex5_nia[15]} {u_ila_0_cpl_spr_ex5_nia[14]} {u_ila_0_cpl_spr_ex5_nia[13]} {u_ila_0_cpl_spr_ex5_nia[12]} {u_ila_0_cpl_spr_ex5_nia[11]} {u_ila_0_cpl_spr_ex5_nia[10]} {u_ila_0_cpl_spr_ex5_nia[9]} {u_ila_0_cpl_spr_ex5_nia[8]} {u_ila_0_cpl_spr_ex5_nia[7]} {u_ila_0_cpl_spr_ex5_nia[6]} {u_ila_0_cpl_spr_ex5_nia[5]} {u_ila_0_cpl_spr_ex5_nia[4]} {u_ila_0_cpl_spr_ex5_nia[3]} {u_ila_0_cpl_spr_ex5_nia[2]} {u_ila_0_cpl_spr_ex5_nia[1]} {u_ila_0_cpl_spr_ex5_nia[0]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1] +set_property port_width 32 [get_debug_ports u_ila_0/probe1] +connect_debug_port u_ila_0/probe1 [get_nets [list {u_ila_0_dout[31]} {u_ila_0_dout[30]} {u_ila_0_dout[29]} {u_ila_0_dout[28]} {u_ila_0_dout[27]} {u_ila_0_dout[26]} {u_ila_0_dout[25]} {u_ila_0_dout[24]} {u_ila_0_dout[23]} {u_ila_0_dout[22]} {u_ila_0_dout[21]} {u_ila_0_dout[20]} {u_ila_0_dout[19]} {u_ila_0_dout[18]} {u_ila_0_dout[17]} {u_ila_0_dout[16]} {u_ila_0_dout[15]} {u_ila_0_dout[14]} {u_ila_0_dout[13]} {u_ila_0_dout[12]} {u_ila_0_dout[11]} {u_ila_0_dout[10]} {u_ila_0_dout[9]} {u_ila_0_dout[8]} {u_ila_0_dout[7]} {u_ila_0_dout[6]} {u_ila_0_dout[5]} {u_ila_0_dout[4]} {u_ila_0_dout[3]} {u_ila_0_dout[2]} {u_ila_0_dout[1]} {u_ila_0_dout[0]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2] +set_property port_width 32 [get_debug_ports u_ila_0/probe2] +connect_debug_port u_ila_0/probe2 [get_nets [list {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[0]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[1]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[2]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[3]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[4]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[5]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[6]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[7]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[8]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[9]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[10]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[11]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[12]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[13]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[14]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[15]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[16]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[17]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[18]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[19]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[20]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[21]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[22]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[23]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[24]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[25]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[26]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[27]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[28]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[29]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[30]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[31]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] +set_property port_width 32 [get_debug_ports u_ila_0/probe3] +connect_debug_port u_ila_0/probe3 [get_nets [list {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[0]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[1]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[2]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[3]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[4]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[5]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[6]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[7]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[8]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[9]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[10]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[11]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[12]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[13]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[14]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[15]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[16]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[17]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[18]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[19]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[20]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[21]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[22]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[23]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[24]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[25]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[26]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[27]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[28]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[29]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[30]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[31]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] +set_property port_width 32 [get_debug_ports u_ila_0/probe4] +connect_debug_port u_ila_0/probe4 [get_nets [list {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[0]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[1]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[2]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[3]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[4]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[5]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[6]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[7]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[8]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[9]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[10]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[11]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[12]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[13]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[14]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[15]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[16]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[17]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[18]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[19]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[20]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[21]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[22]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[23]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[24]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[25]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[26]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[27]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[28]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[29]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[30]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[31]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] +set_property port_width 32 [get_debug_ports u_ila_0/probe5] +connect_debug_port u_ila_0/probe5 [get_nets [list {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[0]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[1]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[2]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[3]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[4]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[5]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[6]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[7]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[8]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[9]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[10]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[11]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[12]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[13]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[14]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[15]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[16]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[17]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[18]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[19]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[20]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[21]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[22]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[23]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[24]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[25]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[26]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[27]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[28]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[29]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[30]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[31]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6] +set_property port_width 28 [get_debug_ports u_ila_0/probe6] +connect_debug_port u_ila_0/probe6 [get_nets [list {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[4]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[5]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[6]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[7]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[8]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[9]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[10]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[11]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[12]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[13]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[14]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[15]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[16]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[17]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[18]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[19]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[20]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[21]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[22]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[23]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[24]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[25]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[26]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[27]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[28]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[29]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[30]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[31]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7] +set_property port_width 2 [get_debug_ports u_ila_0/probe7] +connect_debug_port u_ila_0/probe7 [get_nets [list {a2x_axi_bd_i/a2x_axi_1/m00_axi_bresp[0]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_bresp[1]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8] +set_property port_width 32 [get_debug_ports u_ila_0/probe8] +connect_debug_port u_ila_0/probe8 [get_nets [list {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[0]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[1]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[2]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[3]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[4]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[5]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[6]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[7]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[8]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[9]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[10]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[11]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[12]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[13]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[14]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[15]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[16]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[17]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[18]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[19]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[20]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[21]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[22]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[23]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[24]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[25]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[26]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[27]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[28]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[29]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[30]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[31]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9] +set_property port_width 32 [get_debug_ports u_ila_0/probe9] +connect_debug_port u_ila_0/probe9 [get_nets [list {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[0]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[1]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[2]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[3]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[4]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[5]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[6]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[7]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[8]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[9]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[10]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[11]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[12]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[13]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[14]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[15]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[16]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[17]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[18]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[19]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[20]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[21]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[22]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[23]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[24]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[25]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[26]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[27]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[28]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[29]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[30]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[31]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10] +set_property port_width 1 [get_debug_ports u_ila_0/probe10] +connect_debug_port u_ila_0/probe10 [get_nets [list {a2x_axi_bd_i/ila_axi_protocol/TRIG_OUT_trig[0]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11] +set_property port_width 1 [get_debug_ports u_ila_0/probe11] +connect_debug_port u_ila_0/probe11 [get_nets [list {a2x_axi_bd_i/ila_axi_protocol/TRIG_OUT_ack[0]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12] +set_property port_width 1 [get_debug_ports u_ila_0/probe12] +connect_debug_port u_ila_0/probe12 [get_nets [list a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/lsucmd/l2cmdq/latch_store_cmd_count_i_1_n_0]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13] +set_property port_width 1 [get_debug_ports u_ila_0/probe13] +connect_debug_port u_ila_0/probe13 [get_nets [list a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/lsucmd/l2cmdq/latch_store_cmd_count_i_2_n_0]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14] +set_property port_width 1 [get_debug_ports u_ila_0/probe14] +connect_debug_port u_ila_0/probe14 [get_nets [list a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/lsucmd/l2cmdq/latch_store_cmd_count_i_3_n_0]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15] +set_property port_width 1 [get_debug_ports u_ila_0/probe15] +connect_debug_port u_ila_0/probe15 [get_nets [list a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/lsucmd/l2cmdq/latch_store_cmd_count_i_4_n_0]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16] +set_property port_width 1 [get_debug_ports u_ila_0/probe16] +connect_debug_port u_ila_0/probe16 [get_nets [list a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/lsucmd/l2cmdq/latch_store_cmd_count_i_5_n_0]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17] +set_property port_width 1 [get_debug_ports u_ila_0/probe17] +connect_debug_port u_ila_0/probe17 [get_nets [list a2x_axi_bd_i/a2x_axi_1/m00_axi_bready]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18] +set_property port_width 1 [get_debug_ports u_ila_0/probe18] +connect_debug_port u_ila_0/probe18 [get_nets [list a2x_axi_bd_i/a2x_axi_1/m00_axi_bvalid]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19] +set_property port_width 1 [get_debug_ports u_ila_0/probe19] +connect_debug_port u_ila_0/probe19 [get_nets [list a2x_axi_bd_i/a2x_axi_1/m00_axi_rlast]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20] +set_property port_width 1 [get_debug_ports u_ila_0/probe20] +connect_debug_port u_ila_0/probe20 [get_nets [list a2x_axi_bd_i/a2x_axi_1/m00_axi_rready]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21] +set_property port_width 1 [get_debug_ports u_ila_0/probe21] +connect_debug_port u_ila_0/probe21 [get_nets [list a2x_axi_bd_i/a2x_axi_1/m00_axi_rvalid]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22] +set_property port_width 1 [get_debug_ports u_ila_0/probe22] +connect_debug_port u_ila_0/probe22 [get_nets [list a2x_axi_bd_i/a2x_axi_1/m00_axi_wlast]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23] +set_property port_width 1 [get_debug_ports u_ila_0/probe23] +connect_debug_port u_ila_0/probe23 [get_nets [list a2x_axi_bd_i/a2x_axi_1/m00_axi_wready]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24] +set_property port_width 1 [get_debug_ports u_ila_0/probe24] +connect_debug_port u_ila_0/probe24 [get_nets [list a2x_axi_bd_i/a2x_axi_1/m00_axi_wvalid]] +set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub] +set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub] +set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub] +connect_debug_port dbg_hub/clk [get_nets clk] diff --git a/rel/build/xdc/main_pinout.xdc b/rel/build/xdc/main_pinout.xdc new file mode 100644 index 0000000..fa7485f --- /dev/null +++ b/rel/build/xdc/main_pinout.xdc @@ -0,0 +1,6 @@ +#set_property PACKAGE_PIN AJ28 [get_ports clk_100MHz] +#set_property IOSTANDARD LVCMOS18 [get_ports clk_100MHz] +set_property PACKAGE_PIN AP27 [get_ports clk_in1_n_0] +set_property IOSTANDARD LVDS [get_ports clk_in1_n_0] +set_property PACKAGE_PIN AP26 [get_ports clk_in1_p_0] +set_property IOSTANDARD LVDS [get_ports clk_in1_p_0] diff --git a/rel/build/xdc/main_spi.xdc b/rel/build/xdc/main_spi.xdc new file mode 100644 index 0000000..1817d9d --- /dev/null +++ b/rel/build/xdc/main_spi.xdc @@ -0,0 +1,13 @@ +## Settings to generate MSC file +# Configuration from SPI Flash as per XAPP1233 +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] +set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DIV-1 [current_design] +set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8 [current_design] +set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] +# Set CFGBVS to GND to match schematics +set_property CFGBVS GND [current_design] +# Set CONFIG_VOLTAGE to 1.8V to match schematics +set_property CONFIG_VOLTAGE 1.8 [current_design] +# Set safety trigger to power down FPGA at 125degC +set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] \ No newline at end of file diff --git a/rel/build/xdc/main_timing.xdc b/rel/build/xdc/main_timing.xdc new file mode 100644 index 0000000..3a6a02e --- /dev/null +++ b/rel/build/xdc/main_timing.xdc @@ -0,0 +1,2 @@ +set_false_path -from [get_clocks -of_objects [get_pins a2x_axi_bd_i/a2x_reset_0/U0/clk]] -to [get_clocks clk] +set_false_path -from [get_clocks -of_objects [get_pins a2x_axi_bd_i/a2x_reset_0/U0/clk]] -to [get_clocks clk2x] diff --git a/rel/fpga/init.tcl b/rel/fpga/init.tcl new file mode 100644 index 0000000..b65d646 --- /dev/null +++ b/rel/fpga/init.tcl @@ -0,0 +1,13 @@ +# init.tcl +# + +set TCL [file dirname [info script]] + +proc include {f} { + global TCL + source -notrace [file join $TCL $f] +} + +include "utils.tcl" +include "waimea.tcl" + diff --git a/rel/fpga/utils.tcl b/rel/fpga/utils.tcl new file mode 100644 index 0000000..c079981 --- /dev/null +++ b/rel/fpga/utils.tcl @@ -0,0 +1,27 @@ +# utils.tcl +# + +proc timestamp {{t ""}} { + if {$t == ""} { + set t [clock seconds] + } + return [clock format $t -format %y%m%d%H%M%S] +} + +proc datetime {{t ""}} { + if {$t == ""} { + set t [clock seconds] + } + return [clock format $t -format "%m-%d-%y %I:%M:%S %p %Z"] +} + +proc now {} { + return [clock seconds] +} + +proc vivado_year {} { + regexp -- {Vivado v(\d\d\d\d)\.*} [version] s year + return $year +} + + diff --git a/rel/fpga/waimea.tcl b/rel/fpga/waimea.tcl new file mode 100644 index 0000000..5c4fe74 --- /dev/null +++ b/rel/fpga/waimea.tcl @@ -0,0 +1,163 @@ +# board/core command interface + +#################################################################### +# system commands + +proc reset {} { + + set filter "CELL_NAME=~\"*vio_ctrl*\"" + set probe "marvio_probe_out1" + + set obj_vio [get_hw_vios -of_objects [get_hw_devices xcvu3p_0] -filter $filter] + set rst [get_hw_probes a2x_axi_bd_i/vio_0_probe_out1 -of_objects $obj_vio] + startgroup + set_property OUTPUT_VALUE 0 $rst + commit_hw_vio $rst + endgroup + startgroup + set_property OUTPUT_VALUE 1 $rst + commit_hw_vio $rst + endgroup + puts "[datetime] Reset" +} + +proc threadstop {{val F}} { + + set filter "CELL_NAME=~\"*vio_ctrl*\"" + set probe "marvio_probe_out0" + + set obj_vio [get_hw_vios -of_objects [get_hw_devices xcvu3p_0] -filter $filter] + set thread_stop [get_hw_probes a2x_axi_bd_i/$probe -of_objects $obj_vio] + set_property OUTPUT_VALUE $val $thread_stop + commit_hw_vio $thread_stop + puts "[datetime] ThreadStop=$val" +} + +#################################################################### +# ila commands + +proc ila_arm {{n 0}} { + set filter "CELL_NAME=~\"u_ila_$n\"" + set res [run_hw_ila [get_hw_ilas -of_objects [get_hw_devices xcvu3p_0] -filter $filter]] + puts "[datetime] ILA$n armed." +} + +proc ila_wait {{n 0}} { + set filter "CELL_NAME=~\"u_ila_$n\"" + puts "[datetime] ILA$n waiting..." + set res [wait_on_hw_ila [get_hw_ilas -of_objects [get_hw_devices xcvu3p_0] -filter $filter]] + display_hw_ila_data [upload_hw_ila_data [get_hw_ilas -of_objects [get_hw_devices xcvu3p_0] -filter $filter]] + puts "[datetime] ILA$n triggered." +} + +#################################################################### +# axi slave commands + +proc raxi {addr {len 8} {dev 0} {width 8}} { + + if {$dev == 0} { + set dev [get_hw_axis hw_axi_1] + } + + create_hw_axi_txn -f raxi_txn $dev -address $addr -len $len -type read + run_hw_axi -quiet raxi_txn + set res [report_hw_axi_txn -w $width raxi_txn] + return $res + +} + +proc waxi {addr data {len 8} {dev 0}} { + + if {$dev == 0} { + set dev [get_hw_axis hw_axi_1] + } + + create_hw_axi_txn -f waxi_txn $dev -address $addr -len $len -type write -data $data + run_hw_axi -quiet waxi_txn + set res [report_hw_axi_txn waxi_txn] + return $res + +} + +proc waxiq {addr data {len 8} {dev 0}} { + + set res [waxi $addr $data $len $dev] + +} + +proc testwrites {addr xfers} { + + set start [datetime] + for {set i 0} {$i < $xfers} {incr i} { + waxi $addr 00000000_11111111_22222222_33333333_44444444_55555555_66666666_77777777 + } + set end [datetime] + + puts "Finished $xfers 32B writes." + puts "Start: $start" + puts " End: $end" + +} + +proc testwrites_128B {addr xfers} { + + set start [datetime] + for {set i 0} {$i < $xfers} {incr i} { + waxi $addr { + 00000000 00000001 00000002 00000003 00000004 00000005 00000006 00000007 + 00000008 00000009 0000000A 0000000B 0000000C 0000000D 0000000E 0000000F + 00000010 00000011 00000012 00000013 00000014 00000015 00000006 00000017 + 00000018 00000019 0000001A 0000001B 0000001C 0000001D 0000000E 0000001F + } 32 + } + set end [datetime] + + puts "Finished $xfers 122B writes." + puts "Start: $start" + puts " End: $end" + +} + +proc map {lambda list} { + set res {} + foreach i $list { + lappend res [apply $lambda $i] + } + return $res +} + +proc bytereverse {x} { + set res "" + for {set i 0} {$i < [string length $x]} {incr i 2} { + set res "[string range $x $i [expr $i+1]]$res" + } + return $res +} + +proc ascii {start {len 32} {dev 0}} { + set w 128 + set res "" + set count [expr ($len-1)/$w + 1] + set ptr $start + + for {set i 0} {$i < $count} {incr i} { + + set mem [raxi $ptr [expr $w/4] $dev $w] + set ptr [format %x [expr [expr 0x$ptr] + $w]] + + # split and remove addr + set tokens [regexp -all -inline {\S+} $mem] + set tokens [lrange $tokens 1 end] + + # bytereverse and ascii + set tokens [map {x {return [bytereverse $x]}} $tokens] + set bytes [join $tokens {}] + set chars [binary format H* $bytes] + + set res "$res$chars" + + } + return $res +} + + diff --git a/rel/readme.md b/rel/readme.md new file mode 100644 index 0000000..63bb311 --- /dev/null +++ b/rel/readme.md @@ -0,0 +1,70 @@ +## Directory Structure + +``` +src/vhdl + clib (low-level components) + ibm (std_ulogic) + support (power_logic subtype) + tri (latches and arrays) + work (macros) +``` + +``` +build + a2x (project) + ip_cache (empty until project built) + ip_repo (empty until IP built/copied) + ip_user (IP macros to be built) + tcl (build scripts) + xdc (constraints) +``` + +``` +fpga + tcl +``` + +``` +doc + core user guide, etc. +``` + + +## Build Process + +### IP + +IP is created in ip_user and copied to ip_repo for use in top level bd. + +See build/ip_user/xxx/readme.md. + +Core: + +``` +a2x_axi +``` + +Simple card components: + +``` +a2x_axi_reg +a2x_dbug +a2x_reset +``` + +Help Vivado attach to VIO correctly: + +``` +reverserator_3 +reverserator_4 +reverserator_32 +reverserator_64 +``` + +### Project + +See build/a2x/readme.md. + +1. create project +2. synth/implement + diff --git a/rel/sim/unimacro/bram_tdp_macro_mock.vhdl b/rel/sim/unimacro/bram_tdp_macro_mock.vhdl new file mode 100644 index 0000000..7981623 --- /dev/null +++ b/rel/sim/unimacro/bram_tdp_macro_mock.vhdl @@ -0,0 +1,185 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity BRAM_TDP_MACRO is + generic ( + BRAM_SIZE : string; + DEVICE : string; + DOA_REG : integer; + DOB_REG : integer; + INIT_A : bit_vector; + INIT_B : bit_vector; + INIT_FILE : string; + READ_WIDTH_A : integer; + READ_WIDTH_B : integer; + SIM_COLLISION_CHECK : string; + SRVAL_A : bit_vector; + SRVAL_B : bit_vector; + WRITE_MODE_A : string; + WRITE_MODE_B : string; + WRITE_WIDTH_A : integer; + WRITE_WIDTH_B : integer; + INIT_00 : bit_vector; + INIT_01 : bit_vector; + INIT_02 : bit_vector; + INIT_03 : bit_vector; + INIT_04 : bit_vector; + INIT_05 : bit_vector; + INIT_06 : bit_vector; + INIT_07 : bit_vector; + INIT_08 : bit_vector; + INIT_09 : bit_vector; + INIT_0A : bit_vector; + INIT_0B : bit_vector; + INIT_0C : bit_vector; + INIT_0D : bit_vector; + INIT_0E : bit_vector; + INIT_0F : bit_vector; + INIT_10 : bit_vector; + INIT_11 : bit_vector; + INIT_12 : bit_vector; + INIT_13 : bit_vector; + INIT_14 : bit_vector; + INIT_15 : bit_vector; + INIT_16 : bit_vector; + INIT_17 : bit_vector; + INIT_18 : bit_vector; + INIT_19 : bit_vector; + INIT_1A : bit_vector; + INIT_1B : bit_vector; + INIT_1C : bit_vector; + INIT_1D : bit_vector; + INIT_1E : bit_vector; + INIT_1F : bit_vector; + INIT_20 : bit_vector; + INIT_21 : bit_vector; + INIT_22 : bit_vector; + INIT_23 : bit_vector; + INIT_24 : bit_vector; + INIT_25 : bit_vector; + INIT_26 : bit_vector; + INIT_27 : bit_vector; + INIT_28 : bit_vector; + INIT_29 : bit_vector; + INIT_2A : bit_vector; + INIT_2B : bit_vector; + INIT_2C : bit_vector; + INIT_2D : bit_vector; + INIT_2E : bit_vector; + INIT_2F : bit_vector; + INIT_30 : bit_vector; + INIT_31 : bit_vector; + INIT_32 : bit_vector; + INIT_33 : bit_vector; + INIT_34 : bit_vector; + INIT_35 : bit_vector; + INIT_36 : bit_vector; + INIT_37 : bit_vector; + INIT_38 : bit_vector; + INIT_39 : bit_vector; + INIT_3A : bit_vector; + INIT_3B : bit_vector; + INIT_3C : bit_vector; + INIT_3D : bit_vector; + INIT_3E : bit_vector; + INIT_3F : bit_vector; + INIT_40 : bit_vector; + INIT_41 : bit_vector; + INIT_42 : bit_vector; + INIT_43 : bit_vector; + INIT_44 : bit_vector; + INIT_45 : bit_vector; + INIT_46 : bit_vector; + INIT_47 : bit_vector; + INIT_48 : bit_vector; + INIT_49 : bit_vector; + INIT_4A : bit_vector; + INIT_4B : bit_vector; + INIT_4C : bit_vector; + INIT_4D : bit_vector; + INIT_4E : bit_vector; + INIT_4F : bit_vector; + INIT_50 : bit_vector; + INIT_51 : bit_vector; + INIT_52 : bit_vector; + INIT_53 : bit_vector; + INIT_54 : bit_vector; + INIT_55 : bit_vector; + INIT_56 : bit_vector; + INIT_57 : bit_vector; + INIT_58 : bit_vector; + INIT_59 : bit_vector; + INIT_5A : bit_vector; + INIT_5B : bit_vector; + INIT_5C : bit_vector; + INIT_5D : bit_vector; + INIT_5E : bit_vector; + INIT_5F : bit_vector; + INIT_60 : bit_vector; + INIT_61 : bit_vector; + INIT_62 : bit_vector; + INIT_63 : bit_vector; + INIT_64 : bit_vector; + INIT_65 : bit_vector; + INIT_66 : bit_vector; + INIT_67 : bit_vector; + INIT_68 : bit_vector; + INIT_69 : bit_vector; + INIT_6A : bit_vector; + INIT_6B : bit_vector; + INIT_6C : bit_vector; + INIT_6D : bit_vector; + INIT_6E : bit_vector; + INIT_6F : bit_vector; + INIT_70 : bit_vector; + INIT_71 : bit_vector; + INIT_72 : bit_vector; + INIT_73 : bit_vector; + INIT_74 : bit_vector; + INIT_75 : bit_vector; + INIT_76 : bit_vector; + INIT_77 : bit_vector; + INIT_78 : bit_vector; + INIT_79 : bit_vector; + INIT_7A : bit_vector; + INIT_7B : bit_vector; + INIT_7C : bit_vector; + INIT_7D : bit_vector; + INIT_7E : bit_vector; + INIT_7F : bit_vector; + INITP_00 : bit_vector; + INITP_01 : bit_vector; + INITP_02 : bit_vector; + INITP_03 : bit_vector; + INITP_04 : bit_vector; + INITP_05 : bit_vector; + INITP_06 : bit_vector; + INITP_07 : bit_vector; + INITP_08 : bit_vector; + INITP_09 : bit_vector; + INITP_0A : bit_vector; + INITP_0B : bit_vector; + INITP_0C : bit_vector; + INITP_0D : bit_vector; + INITP_0E : bit_vector; + INITP_0F : bit_vector + ); +port ( + DOA : out std_logic_vector; + DOB : out std_logic_vector; + ADDRA : in std_logic_vector; + ADDRB : in std_logic_vector; + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector; + DIB : in std_logic_vector; + ENA : in std_ulogic; + ENB : in std_ulogic; + REGCEA : in std_ulogic; + REGCEB : in std_ulogic; + RSTA : in std_ulogic; + RSTB : in std_ulogic; + WEA : in std_logic_vector; + WEB : in std_logic_vector + ); +end entity; diff --git a/rel/sim/unimacro/unimacro_vcomp_mock.vhdl b/rel/sim/unimacro/unimacro_vcomp_mock.vhdl new file mode 100644 index 0000000..8c60f5e --- /dev/null +++ b/rel/sim/unimacro/unimacro_vcomp_mock.vhdl @@ -0,0 +1,187 @@ +library ieee; +use ieee.std_logic_1164.all; + +package vcomponents is + component BRAM_TDP_MACRO + generic ( + BRAM_SIZE : string; + DEVICE : string; + DOA_REG : integer; + DOB_REG : integer; + INIT_A : bit_vector; + INIT_B : bit_vector; + INIT_FILE : string; + READ_WIDTH_A : integer; + READ_WIDTH_B : integer; + SIM_COLLISION_CHECK : string; + SRVAL_A : bit_vector; + SRVAL_B : bit_vector; + WRITE_MODE_A : string; + WRITE_MODE_B : string; + WRITE_WIDTH_A : integer; + WRITE_WIDTH_B : integer; + INIT_00 : bit_vector; + INIT_01 : bit_vector; + INIT_02 : bit_vector; + INIT_03 : bit_vector; + INIT_04 : bit_vector; + INIT_05 : bit_vector; + INIT_06 : bit_vector; + INIT_07 : bit_vector; + INIT_08 : bit_vector; + INIT_09 : bit_vector; + INIT_0A : bit_vector; + INIT_0B : bit_vector; + INIT_0C : bit_vector; + INIT_0D : bit_vector; + INIT_0E : bit_vector; + INIT_0F : bit_vector; + INIT_10 : bit_vector; + INIT_11 : bit_vector; + INIT_12 : bit_vector; + INIT_13 : bit_vector; + INIT_14 : bit_vector; + INIT_15 : bit_vector; + INIT_16 : bit_vector; + INIT_17 : bit_vector; + INIT_18 : bit_vector; + INIT_19 : bit_vector; + INIT_1A : bit_vector; + INIT_1B : bit_vector; + INIT_1C : bit_vector; + INIT_1D : bit_vector; + INIT_1E : bit_vector; + INIT_1F : bit_vector; + INIT_20 : bit_vector; + INIT_21 : bit_vector; + INIT_22 : bit_vector; + INIT_23 : bit_vector; + INIT_24 : bit_vector; + INIT_25 : bit_vector; + INIT_26 : bit_vector; + INIT_27 : bit_vector; + INIT_28 : bit_vector; + INIT_29 : bit_vector; + INIT_2A : bit_vector; + INIT_2B : bit_vector; + INIT_2C : bit_vector; + INIT_2D : bit_vector; + INIT_2E : bit_vector; + INIT_2F : bit_vector; + INIT_30 : bit_vector; + INIT_31 : bit_vector; + INIT_32 : bit_vector; + INIT_33 : bit_vector; + INIT_34 : bit_vector; + INIT_35 : bit_vector; + INIT_36 : bit_vector; + INIT_37 : bit_vector; + INIT_38 : bit_vector; + INIT_39 : bit_vector; + INIT_3A : bit_vector; + INIT_3B : bit_vector; + INIT_3C : bit_vector; + INIT_3D : bit_vector; + INIT_3E : bit_vector; + INIT_3F : bit_vector; + INIT_40 : bit_vector; + INIT_41 : bit_vector; + INIT_42 : bit_vector; + INIT_43 : bit_vector; + INIT_44 : bit_vector; + INIT_45 : bit_vector; + INIT_46 : bit_vector; + INIT_47 : bit_vector; + INIT_48 : bit_vector; + INIT_49 : bit_vector; + INIT_4A : bit_vector; + INIT_4B : bit_vector; + INIT_4C : bit_vector; + INIT_4D : bit_vector; + INIT_4E : bit_vector; + INIT_4F : bit_vector; + INIT_50 : bit_vector; + INIT_51 : bit_vector; + INIT_52 : bit_vector; + INIT_53 : bit_vector; + INIT_54 : bit_vector; + INIT_55 : bit_vector; + INIT_56 : bit_vector; + INIT_57 : bit_vector; + INIT_58 : bit_vector; + INIT_59 : bit_vector; + INIT_5A : bit_vector; + INIT_5B : bit_vector; + INIT_5C : bit_vector; + INIT_5D : bit_vector; + INIT_5E : bit_vector; + INIT_5F : bit_vector; + INIT_60 : bit_vector; + INIT_61 : bit_vector; + INIT_62 : bit_vector; + INIT_63 : bit_vector; + INIT_64 : bit_vector; + INIT_65 : bit_vector; + INIT_66 : bit_vector; + INIT_67 : bit_vector; + INIT_68 : bit_vector; + INIT_69 : bit_vector; + INIT_6A : bit_vector; + INIT_6B : bit_vector; + INIT_6C : bit_vector; + INIT_6D : bit_vector; + INIT_6E : bit_vector; + INIT_6F : bit_vector; + INIT_70 : bit_vector; + INIT_71 : bit_vector; + INIT_72 : bit_vector; + INIT_73 : bit_vector; + INIT_74 : bit_vector; + INIT_75 : bit_vector; + INIT_76 : bit_vector; + INIT_77 : bit_vector; + INIT_78 : bit_vector; + INIT_79 : bit_vector; + INIT_7A : bit_vector; + INIT_7B : bit_vector; + INIT_7C : bit_vector; + INIT_7D : bit_vector; + INIT_7E : bit_vector; + INIT_7F : bit_vector; + INITP_00 : bit_vector; + INITP_01 : bit_vector; + INITP_02 : bit_vector; + INITP_03 : bit_vector; + INITP_04 : bit_vector; + INITP_05 : bit_vector; + INITP_06 : bit_vector; + INITP_07 : bit_vector; + INITP_08 : bit_vector; + INITP_09 : bit_vector; + INITP_0A : bit_vector; + INITP_0B : bit_vector; + INITP_0C : bit_vector; + INITP_0D : bit_vector; + INITP_0E : bit_vector; + INITP_0F : bit_vector + ); + port ( + DOA : out std_logic_vector; + DOB : out std_logic_vector; + ADDRA : in std_logic_vector; + ADDRB : in std_logic_vector; + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector; + DIB : in std_logic_vector; + ENA : in std_ulogic; + ENB : in std_ulogic; + REGCEA : in std_ulogic; + REGCEB : in std_ulogic; + RSTA : in std_ulogic; + RSTB : in std_ulogic; + WEA : in std_logic_vector; + WEB : in std_logic_vector + ); + end component; +end package vcomponents; diff --git a/rel/src/vhdl/clib/c_debug_mux16.vhdl b/rel/src/vhdl/clib/c_debug_mux16.vhdl new file mode 100644 index 0000000..425a6d1 --- /dev/null +++ b/rel/src/vhdl/clib/c_debug_mux16.vhdl @@ -0,0 +1,164 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +--******************************************************************** +--* +--* TITLE: Debug Mux Component (16:1 Debug Groups; 4:1 Trigger Groups) +--* +--* NAME: c_debug_mux16.vhdl +--* +--******************************************************************** +-- +library ieee; use ieee.std_logic_1164.all; +library support; use support.power_logic_pkg.all; + +entity c_debug_mux16 is +generic( DBG_WIDTH : integer := 88 +); +port( + vd : inout power_logic; + gd : inout power_logic; + + select_bits : in std_ulogic_vector(0 to 15); + trace_data_in : in std_ulogic_vector(0 to DBG_WIDTH-1); + trigger_data_in : in std_ulogic_vector(0 to 11); + + dbg_group0 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group1 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group2 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group3 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group4 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group5 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group6 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group7 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group8 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group9 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group10 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group11 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group12 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group13 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group14 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group15 : in std_ulogic_vector(0 to DBG_WIDTH-1); + + trg_group0 : in std_ulogic_vector(0 to 11); + trg_group1 : in std_ulogic_vector(0 to 11); + trg_group2 : in std_ulogic_vector(0 to 11); + trg_group3 : in std_ulogic_vector(0 to 11); + + trace_data_out : out std_ulogic_vector(0 to DBG_WIDTH-1); + trigger_data_out : out std_ulogic_vector(0 to 11) +); +-- synopsys translate_off + +-- synopsys translate_on + +end c_debug_mux16; + + +architecture c_debug_mux16 of c_debug_mux16 is + +constant DBG_1FOURTH : positive := DBG_WIDTH/4; +constant DBG_2FOURTH : positive := DBG_WIDTH/2; +constant DBG_3FOURTH : positive := 3*DBG_WIDTH/4; + +signal debug_grp_selected : std_ulogic_vector(0 to DBG_WIDTH-1); +signal debug_grp_rotated : std_ulogic_vector(0 to DBG_WIDTH-1); +signal trigg_grp_selected : std_ulogic_vector(0 to 11); +signal trigg_grp_rotated : std_ulogic_vector(0 to 11); + +signal unused : std_ulogic; + +begin + + unused <= select_bits(4); + +-- Debug Mux + with select_bits(0 to 3) select debug_grp_selected <= + dbg_group0 when "0000", + dbg_group1 when "0001", + dbg_group2 when "0010", + dbg_group3 when "0011", + dbg_group4 when "0100", + dbg_group5 when "0101", + dbg_group6 when "0110", + dbg_group7 when "0111", + dbg_group8 when "1000", + dbg_group9 when "1001", + dbg_group10 when "1010", + dbg_group11 when "1011", + dbg_group12 when "1100", + dbg_group13 when "1101", + dbg_group14 when "1110", + dbg_group15 when others; + + with select_bits(5 to 6) select + debug_grp_rotated <= debug_grp_selected(DBG_1FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_1FOURTH-1) when "11", + debug_grp_selected(DBG_2FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_2FOURTH-1) when "10", + debug_grp_selected(DBG_3FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_3FOURTH-1) when "01", + debug_grp_selected(0 to DBG_WIDTH-1) when others; + + + with select_bits(7) select trace_data_out(0 to DBG_1FOURTH-1) <= + trace_data_in(0 to DBG_1FOURTH-1) when '0', + debug_grp_rotated(0 to DBG_1FOURTH-1) when others; + + with select_bits(8) select trace_data_out(DBG_1FOURTH to DBG_2FOURTH-1) <= + trace_data_in(DBG_1FOURTH to DBG_2FOURTH-1) when '0', + debug_grp_rotated(DBG_1FOURTH to DBG_2FOURTH-1) when others; + + with select_bits(9) select trace_data_out(DBG_2FOURTH to DBG_3FOURTH-1) <= + trace_data_in(DBG_2FOURTH to DBG_3FOURTH-1) when '0', + debug_grp_rotated(DBG_2FOURTH to DBG_3FOURTH-1) when others; + + with select_bits(10) select trace_data_out(DBG_3FOURTH to DBG_WIDTH-1) <= + trace_data_in(DBG_3FOURTH to DBG_WIDTH-1) when '0', + debug_grp_rotated(DBG_3FOURTH to DBG_WIDTH-1) when others; + + + +-- Trigger Mux + with select_bits(11 to 12) select trigg_grp_selected <= + trg_group0 when "00", + trg_group1 when "01", + trg_group2 when "10", + trg_group3 when others; + + with select_bits(13) select + trigg_grp_rotated <= trigg_grp_selected(6 to 11) & trigg_grp_selected(0 to 5) when '1', + trigg_grp_selected(0 to 11) when others; + + with select_bits(14) select trigger_data_out(0 to 5) <= + trigger_data_in(0 to 5) when '0', + trigg_grp_rotated(0 to 5) when others; + + with select_bits(15) select trigger_data_out(6 to 11) <= + trigger_data_in(6 to 11) when '0', + trigg_grp_rotated(6 to 11) when others; + + +end c_debug_mux16; diff --git a/rel/src/vhdl/clib/c_debug_mux32.vhdl b/rel/src/vhdl/clib/c_debug_mux32.vhdl new file mode 100644 index 0000000..8f85ee0 --- /dev/null +++ b/rel/src/vhdl/clib/c_debug_mux32.vhdl @@ -0,0 +1,194 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +--******************************************************************** +--* +--* TITLE: Debug Mux Component (32:1 Debug Groups; 4:1 Trigger Groups) +--* +--* NAME: c_debug_mux32.vhdl +--* +--******************************************************************** +-- +library ieee; use ieee.std_logic_1164.all; +library support; +use support.power_logic_pkg.all; + +entity c_debug_mux32 is +generic( DBG_WIDTH : integer := 88 +); +port( + vd : inout power_logic; + gd : inout power_logic; + + select_bits : in std_ulogic_vector(0 to 15); + trace_data_in : in std_ulogic_vector(0 to DBG_WIDTH-1); + trigger_data_in : in std_ulogic_vector(0 to 11); + + dbg_group0 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group1 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group2 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group3 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group4 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group5 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group6 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group7 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group8 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group9 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group10 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group11 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group12 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group13 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group14 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group15 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group16 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group17 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group18 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group19 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group20 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group21 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group22 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group23 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group24 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group25 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group26 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group27 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group28 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group29 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group30 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group31 : in std_ulogic_vector(0 to DBG_WIDTH-1); + + trg_group0 : in std_ulogic_vector(0 to 11); + trg_group1 : in std_ulogic_vector(0 to 11); + trg_group2 : in std_ulogic_vector(0 to 11); + trg_group3 : in std_ulogic_vector(0 to 11); + + trace_data_out : out std_ulogic_vector(0 to DBG_WIDTH-1); + trigger_data_out : out std_ulogic_vector(0 to 11) +); +-- synopsys translate_off + +-- synopsys translate_on + +end c_debug_mux32; + + +architecture c_debug_mux32 of c_debug_mux32 is + +constant DBG_1FOURTH : positive := DBG_WIDTH/4; +constant DBG_2FOURTH : positive := DBG_WIDTH/2; +constant DBG_3FOURTH : positive := 3*DBG_WIDTH/4; + +signal debug_grp_selected : std_ulogic_vector(0 to DBG_WIDTH-1); +signal debug_grp_rotated : std_ulogic_vector(0 to DBG_WIDTH-1); +signal trigg_grp_selected : std_ulogic_vector(0 to 11); +signal trigg_grp_rotated : std_ulogic_vector(0 to 11); + +begin + + +-- Debug Mux + with select_bits(0 to 4) select debug_grp_selected <= + dbg_group0 when "00000", + dbg_group1 when "00001", + dbg_group2 when "00010", + dbg_group3 when "00011", + dbg_group4 when "00100", + dbg_group5 when "00101", + dbg_group6 when "00110", + dbg_group7 when "00111", + dbg_group8 when "01000", + dbg_group9 when "01001", + dbg_group10 when "01010", + dbg_group11 when "01011", + dbg_group12 when "01100", + dbg_group13 when "01101", + dbg_group14 when "01110", + dbg_group15 when "01111", + dbg_group16 when "10000", + dbg_group17 when "10001", + dbg_group18 when "10010", + dbg_group19 when "10011", + dbg_group20 when "10100", + dbg_group21 when "10101", + dbg_group22 when "10110", + dbg_group23 when "10111", + dbg_group24 when "11000", + dbg_group25 when "11001", + dbg_group26 when "11010", + dbg_group27 when "11011", + dbg_group28 when "11100", + dbg_group29 when "11101", + dbg_group30 when "11110", + dbg_group31 when others; + + with select_bits(5 to 6) select + debug_grp_rotated <= debug_grp_selected(DBG_1FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_1FOURTH-1) when "11", + debug_grp_selected(DBG_2FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_2FOURTH-1) when "10", + debug_grp_selected(DBG_3FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_3FOURTH-1) when "01", + debug_grp_selected(0 to DBG_WIDTH-1) when others; + + + with select_bits(7) select trace_data_out(0 to DBG_1FOURTH-1) <= + trace_data_in(0 to DBG_1FOURTH-1) when '0', + debug_grp_rotated(0 to DBG_1FOURTH-1) when others; + + with select_bits(8) select trace_data_out(DBG_1FOURTH to DBG_2FOURTH-1) <= + trace_data_in(DBG_1FOURTH to DBG_2FOURTH-1) when '0', + debug_grp_rotated(DBG_1FOURTH to DBG_2FOURTH-1) when others; + + with select_bits(9) select trace_data_out(DBG_2FOURTH to DBG_3FOURTH-1) <= + trace_data_in(DBG_2FOURTH to DBG_3FOURTH-1) when '0', + debug_grp_rotated(DBG_2FOURTH to DBG_3FOURTH-1) when others; + + with select_bits(10) select trace_data_out(DBG_3FOURTH to DBG_WIDTH-1) <= + trace_data_in(DBG_3FOURTH to DBG_WIDTH-1) when '0', + debug_grp_rotated(DBG_3FOURTH to DBG_WIDTH-1) when others; + + + +-- Trigger Mux + with select_bits(11 to 12) select trigg_grp_selected <= + trg_group0 when "00", + trg_group1 when "01", + trg_group2 when "10", + trg_group3 when others; + + with select_bits(13) select + trigg_grp_rotated <= trigg_grp_selected(6 to 11) & trigg_grp_selected(0 to 5) when '1', + trigg_grp_selected(0 to 11) when others; + + with select_bits(14) select trigger_data_out(0 to 5) <= + trigger_data_in(0 to 5) when '0', + trigg_grp_rotated(0 to 5) when others; + + with select_bits(15) select trigger_data_out(6 to 11) <= + trigger_data_in(6 to 11) when '0', + trigg_grp_rotated(6 to 11) when others; + + +end c_debug_mux32; diff --git a/rel/src/vhdl/clib/c_debug_mux4.vhdl b/rel/src/vhdl/clib/c_debug_mux4.vhdl new file mode 100644 index 0000000..a819d7c --- /dev/null +++ b/rel/src/vhdl/clib/c_debug_mux4.vhdl @@ -0,0 +1,141 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +--******************************************************************** +--* +--* TITLE: Debug Mux Component (4:1 Debug Groups; 4:1 Trigger Groups) +--* +--* NAME: c_debug_mux4.vhdl +--* +--******************************************************************** +-- +library ieee; use ieee.std_logic_1164.all; +library support; +use support.power_logic_pkg.all; + +entity c_debug_mux4 is +generic( DBG_WIDTH : integer := 88 +); +port( + vd : inout power_logic; + gd : inout power_logic; + + select_bits : in std_ulogic_vector(0 to 15); + trace_data_in : in std_ulogic_vector(0 to DBG_WIDTH-1); + trigger_data_in : in std_ulogic_vector(0 to 11); + + dbg_group0 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group1 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group2 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group3 : in std_ulogic_vector(0 to DBG_WIDTH-1); + + trg_group0 : in std_ulogic_vector(0 to 11); + trg_group1 : in std_ulogic_vector(0 to 11); + trg_group2 : in std_ulogic_vector(0 to 11); + trg_group3 : in std_ulogic_vector(0 to 11); + + trace_data_out : out std_ulogic_vector(0 to DBG_WIDTH-1); + trigger_data_out : out std_ulogic_vector(0 to 11) +); +-- synopsys translate_off + +-- synopsys translate_on + +end c_debug_mux4; + + +architecture c_debug_mux4 of c_debug_mux4 is + +constant DBG_1FOURTH : positive := DBG_WIDTH/4; +constant DBG_2FOURTH : positive := DBG_WIDTH/2; +constant DBG_3FOURTH : positive := 3*DBG_WIDTH/4; + +signal debug_grp_selected : std_ulogic_vector(0 to DBG_WIDTH-1); +signal debug_grp_rotated : std_ulogic_vector(0 to DBG_WIDTH-1); +signal trigg_grp_selected : std_ulogic_vector(0 to 11); +signal trigg_grp_rotated : std_ulogic_vector(0 to 11); + +signal unused : std_ulogic; + +begin + + unused <= select_bits(2) or select_bits(3) or select_bits(4); + +-- Debug Mux + with select_bits(0 to 1) select debug_grp_selected <= + dbg_group0 when "00", + dbg_group1 when "01", + dbg_group2 when "10", + dbg_group3 when others; + + with select_bits(5 to 6) select + debug_grp_rotated <= debug_grp_selected(DBG_1FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_1FOURTH-1) when "11", + debug_grp_selected(DBG_2FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_2FOURTH-1) when "10", + debug_grp_selected(DBG_3FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_3FOURTH-1) when "01", + debug_grp_selected(0 to DBG_WIDTH-1) when others; + + + with select_bits(7) select trace_data_out(0 to DBG_1FOURTH-1) <= + trace_data_in(0 to DBG_1FOURTH-1) when '0', + debug_grp_rotated(0 to DBG_1FOURTH-1) when others; + + with select_bits(8) select trace_data_out(DBG_1FOURTH to DBG_2FOURTH-1) <= + trace_data_in(DBG_1FOURTH to DBG_2FOURTH-1) when '0', + debug_grp_rotated(DBG_1FOURTH to DBG_2FOURTH-1) when others; + + with select_bits(9) select trace_data_out(DBG_2FOURTH to DBG_3FOURTH-1) <= + trace_data_in(DBG_2FOURTH to DBG_3FOURTH-1) when '0', + debug_grp_rotated(DBG_2FOURTH to DBG_3FOURTH-1) when others; + + with select_bits(10) select trace_data_out(DBG_3FOURTH to DBG_WIDTH-1) <= + trace_data_in(DBG_3FOURTH to DBG_WIDTH-1) when '0', + debug_grp_rotated(DBG_3FOURTH to DBG_WIDTH-1) when others; + + + +-- Trigger Mux + with select_bits(11 to 12) select trigg_grp_selected <= + trg_group0 when "00", + trg_group1 when "01", + trg_group2 when "10", + trg_group3 when others; + + with select_bits(13) select + trigg_grp_rotated <= trigg_grp_selected(6 to 11) & trigg_grp_selected(0 to 5) when '1', + trigg_grp_selected(0 to 11) when others; + + with select_bits(14) select trigger_data_out(0 to 5) <= + trigger_data_in(0 to 5) when '0', + trigg_grp_rotated(0 to 5) when others; + + with select_bits(15) select trigger_data_out(6 to 11) <= + trigger_data_in(6 to 11) when '0', + trigg_grp_rotated(6 to 11) when others; + + +end c_debug_mux4; diff --git a/rel/src/vhdl/clib/c_debug_mux8.vhdl b/rel/src/vhdl/clib/c_debug_mux8.vhdl new file mode 100644 index 0000000..3fa92a1 --- /dev/null +++ b/rel/src/vhdl/clib/c_debug_mux8.vhdl @@ -0,0 +1,149 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +--******************************************************************** +--* +--* TITLE: Debug Mux Component (8:1 Debug Groups; 4:1 Trigger Groups) +--* +--* NAME: c_debug_mux8.vhdl +--* +--******************************************************************** +-- +library ieee; use ieee.std_logic_1164.all; +library support; +use support.power_logic_pkg.all; + +entity c_debug_mux8 is +generic( DBG_WIDTH : integer := 88 +); +port( + vd : inout power_logic; + gd : inout power_logic; + + select_bits : in std_ulogic_vector(0 to 15); + trace_data_in : in std_ulogic_vector(0 to DBG_WIDTH-1); + trigger_data_in : in std_ulogic_vector(0 to 11); + + dbg_group0 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group1 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group2 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group3 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group4 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group5 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group6 : in std_ulogic_vector(0 to DBG_WIDTH-1); + dbg_group7 : in std_ulogic_vector(0 to DBG_WIDTH-1); + + trg_group0 : in std_ulogic_vector(0 to 11); + trg_group1 : in std_ulogic_vector(0 to 11); + trg_group2 : in std_ulogic_vector(0 to 11); + trg_group3 : in std_ulogic_vector(0 to 11); + + trace_data_out : out std_ulogic_vector(0 to DBG_WIDTH-1); + trigger_data_out : out std_ulogic_vector(0 to 11) +); +-- synopsys translate_off + +-- synopsys translate_on + +end c_debug_mux8; + + +architecture c_debug_mux8 of c_debug_mux8 is + +constant DBG_1FOURTH : positive := DBG_WIDTH/4; +constant DBG_2FOURTH : positive := DBG_WIDTH/2; +constant DBG_3FOURTH : positive := 3*DBG_WIDTH/4; + +signal debug_grp_selected : std_ulogic_vector(0 to DBG_WIDTH-1); +signal debug_grp_rotated : std_ulogic_vector(0 to DBG_WIDTH-1); +signal trigg_grp_selected : std_ulogic_vector(0 to 11); +signal trigg_grp_rotated : std_ulogic_vector(0 to 11); + +signal unused : std_ulogic; + +begin + + unused <= select_bits(3) or select_bits(4); + +-- Debug Mux + with select_bits(0 to 2) select debug_grp_selected <= + dbg_group0 when "000", + dbg_group1 when "001", + dbg_group2 when "010", + dbg_group3 when "011", + dbg_group4 when "100", + dbg_group5 when "101", + dbg_group6 when "110", + dbg_group7 when others; + + with select_bits(5 to 6) select + debug_grp_rotated <= debug_grp_selected(DBG_1FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_1FOURTH-1) when "11", + debug_grp_selected(DBG_2FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_2FOURTH-1) when "10", + debug_grp_selected(DBG_3FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_3FOURTH-1) when "01", + debug_grp_selected(0 to DBG_WIDTH-1) when others; + + + with select_bits(7) select trace_data_out(0 to DBG_1FOURTH-1) <= + trace_data_in(0 to DBG_1FOURTH-1) when '0', + debug_grp_rotated(0 to DBG_1FOURTH-1) when others; + + with select_bits(8) select trace_data_out(DBG_1FOURTH to DBG_2FOURTH-1) <= + trace_data_in(DBG_1FOURTH to DBG_2FOURTH-1) when '0', + debug_grp_rotated(DBG_1FOURTH to DBG_2FOURTH-1) when others; + + with select_bits(9) select trace_data_out(DBG_2FOURTH to DBG_3FOURTH-1) <= + trace_data_in(DBG_2FOURTH to DBG_3FOURTH-1) when '0', + debug_grp_rotated(DBG_2FOURTH to DBG_3FOURTH-1) when others; + + with select_bits(10) select trace_data_out(DBG_3FOURTH to DBG_WIDTH-1) <= + trace_data_in(DBG_3FOURTH to DBG_WIDTH-1) when '0', + debug_grp_rotated(DBG_3FOURTH to DBG_WIDTH-1) when others; + + + +-- Trigger Mux + with select_bits(11 to 12) select trigg_grp_selected <= + trg_group0 when "00", + trg_group1 when "01", + trg_group2 when "10", + trg_group3 when others; + + with select_bits(13) select + trigg_grp_rotated <= trigg_grp_selected(6 to 11) & trigg_grp_selected(0 to 5) when '1', + trigg_grp_selected(0 to 11) when others; + + with select_bits(14) select trigger_data_out(0 to 5) <= + trigger_data_in(0 to 5) when '0', + trigg_grp_rotated(0 to 5) when others; + + with select_bits(15) select trigger_data_out(6 to 11) <= + trigger_data_in(6 to 11) when '0', + trigg_grp_rotated(6 to 11) when others; + + +end c_debug_mux8; diff --git a/rel/src/vhdl/clib/c_event_mux.vhdl b/rel/src/vhdl/clib/c_event_mux.vhdl new file mode 100644 index 0000000..ebebd01 --- /dev/null +++ b/rel/src/vhdl/clib/c_event_mux.vhdl @@ -0,0 +1,170 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +--******************************************************************** +--* +--* TITLE: Performance Event Mux Component +--* +--* NAME: c_event_mux.vhdl +--* +--******************************************************************** +-- +library ieee,support,ibm; +use ieee.std_logic_1164.all; +use ibm.std_ulogic_function_support.all; +use support.power_logic_pkg.all; + +entity c_event_mux is + generic( events_in : integer := 32; -- Valid Settings: FU=32; MMU=64; IU/XU/LSU=128 + events_out : integer := 8 ); -- Valid Settings: 8 outputs per event mux + port( + vd : inout power_logic; + gd : inout power_logic; + t0_events : in std_ulogic_vector(0 to events_in/4-1); + t1_events : in std_ulogic_vector(0 to events_in/4-1); + t2_events : in std_ulogic_vector(0 to events_in/4-1); + t3_events : in std_ulogic_vector(0 to events_in/4-1); + + -- Select bit size depends on total events: 32 events=32, 64 events=40; 128 events=48 + select_bits : in std_ulogic_vector(0 to ((events_in/64+4)*events_out)-1); + + event_bits : out std_ulogic_vector(0 to events_out-1) +); +-- synopsys translate_off + +-- synopsys translate_on + +end c_event_mux; + + +architecture c_event_mux of c_event_mux is + + -- Constants used to split select_bits into thrd_sel + inMux_sel vectors + -- Mux Size: 32 64 128 + constant INCR : natural := events_in/64+4; -- INCR: 4 5 6 + constant SIZE : natural := events_in/64+1; -- SIZE: 1 2 3 + +------ stopped here ------------------ + + -- For each output bit decode select bits to select an input mux to use. + signal inMuxDec : std_ulogic_vector(0 to events_out*events_in/4-1); + signal inMuxOut : std_ulogic_vector(0 to events_out*events_in/4-1); + + -- thrd_sel size always = 8; inMux_sel size = select_bit size - thrd_sel size + signal thrd_sel : std_ulogic_vector(0 to events_out-1); + signal inMux_sel : std_ulogic_vector(0 to ((events_in/64+3)*events_out)-1); + + +begin + -- Split the select_bits input into "thread_select" and "input mux select" vectors + -- 32: (0,4,8,12,16,20,24,28) + -- 64: (0,5,10,15,20,25,30,35) + -- 128: (0,6,12,18,24,30,36,42) + thrd_sel <= select_bits(0*INCR) & select_bits(1*INCR) & + select_bits(2*INCR) & select_bits(3*INCR) & + select_bits(4*INCR) & select_bits(5*INCR) & + select_bits(6*INCR) & select_bits(7*INCR) ; + + -- 32: (1:3,5:7,9:11,13:15,17:19,21:23,25:27,29:31) + -- 64: (1:4,6:9,11:14,16:19,21:24,26:29,31:34,36:39) + -- 128: (1:5,7:11,13:17,19:23,25:29,31:35,37:41,43:47) + inMux_sel <= select_bits(0*INCR+1 to (0+1)*INCR-1) & + select_bits(1*INCR+1 to (1+1)*INCR-1) & + select_bits(2*INCR+1 to (2+1)*INCR-1) & + select_bits(3*INCR+1 to (3+1)*INCR-1) & + select_bits(4*INCR+1 to (4+1)*INCR-1) & + select_bits(5*INCR+1 to (5+1)*INCR-1) & + select_bits(6*INCR+1 to (6+1)*INCR-1) & + select_bits(7*INCR+1 to (7+1)*INCR-1) ; + + + -- For each output bit, decode its inMux_sel bits to select the input mux it's using + decode: for X in 0 to events_out-1 generate + Mux32: if (events_in = 32) generate + inMuxDec(X*events_in/4 to X*events_in/4+7) <= decode_3to8(inMux_sel(X*3 to X*3+2)); + end generate Mux32; + + Mux64: if (events_in = 64) generate + inMuxDec(X*events_in/4 to X*events_in/4+15) <= decode_4to16(inMux_sel(X*4 to X*4+3)); + end generate Mux64; + + Mux128: if (events_in = 128) generate + inMuxDec(X*events_in/4 to X*events_in/4+31) <= decode_5to32(inMux_sel(X*5 to X*5+4)); + end generate Mux128; + end generate decode; + + + -- For each output bit, inMux and thrd_sel decodes are used to gate the selected event input + inpMuxHi: for X in 0 to events_out/2-1 generate + eventSel: for I in 0 to events_in/4-1 generate + inMuxOut(X*events_in/4 + I) <= + ((inMuxDec(X*events_in/4 + I) and not thrd_sel(X) and t0_events(I)) or + (inMuxDec(X*events_in/4 + I) and thrd_sel(X) and t1_events(I)) ); + end generate eventSel; + end generate inpMuxHi; + + inpMuxLo: for X in events_out/2 to events_out-1 generate + eventSel: for I in 0 to events_in/4-1 generate + inMuxOut(X*events_in/4 + I) <= + ((inMuxDec(X*events_in/4 + I) and not thrd_sel(X) and t2_events(I)) or + (inMuxDec(X*events_in/4 + I) and thrd_sel(X) and t3_events(I)) ); + end generate eventSel; + end generate inpMuxLo; + + + -- ORing the input mux outputs to drive each event output bit. + -- Only one selected at a time by each output bit's inMux decode value. + bitOutHi: for X in 0 to events_out/2-1 generate + Mux32: if (events_in = 32) generate + event_bits(X) <= or_reduce(inMuxOut(X*events_in/4 to X*events_in/4 + 7)); + end generate Mux32; + + Mux64: if (events_in = 64) generate + event_bits(X) <= or_reduce(inMuxOut(X*events_in/4 to X*events_in/4 + 15)); + end generate Mux64; + + Mux128: if (events_in = 128) generate + event_bits(X) <= or_reduce(inMuxOut(X*events_in/4 to X*events_in/4 + 31)); + end generate Mux128; + end generate bitOutHi; + + bitOutLo: for X in events_out/2 to events_out-1 generate + Mux32: if (events_in = 32) generate + event_bits(X) <= or_reduce(inMuxOut(X*events_in/4 to X*events_in/4 + 7)); + end generate Mux32; + + Mux64: if (events_in = 64) generate + event_bits(X) <= or_reduce(inMuxOut(X*events_in/4 to X*events_in/4 + 15)); + end generate Mux64; + + Mux128: if (events_in = 128) generate + event_bits(X) <= or_reduce(inMuxOut(X*events_in/4 to X*events_in/4 + 31)); + end generate Mux128; + end generate bitOutLo; + +end c_event_mux; diff --git a/rel/src/vhdl/clib/c_prism_bthmx.vhdl b/rel/src/vhdl/clib/c_prism_bthmx.vhdl new file mode 100644 index 0000000..123957e --- /dev/null +++ b/rel/src/vhdl/clib/c_prism_bthmx.vhdl @@ -0,0 +1,93 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee; use ieee.std_logic_1164.all ; +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; +library support; use support.power_logic_pkg.all; + +ENTITY c_prism_bthmx IS + GENERIC ( btr : string := "BTHMX_X1_A12TH" ); + PORT( + X : IN STD_ULOGIC; + SNEG : IN STD_ULOGIC; -- DO NOT FLIP THE INPUT (ADD) + SX : IN STD_ULOGIC; -- SHIFT BY 1 + SX2 : IN STD_ULOGIC; -- SHIFT BY 2 + RIGHT : IN STD_ULOGIC; -- BIT FROM THE RIGHT (LSB) + LEFT : OUT STD_ULOGIC; -- BIT FROM THE LEFT + Q : OUT STD_ULOGIC; -- FINAL OUTPUT + vd : inout power_logic; + gd : inout power_logic + ); + +-- synopsys translate_off + + + -- The following will be used by synthesis for unrolling the vector: + ATTRIBUTE PIN_BIT_INFORMATION of c_prism_bthmx : entity is + ( + 1 => (" ","X ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","SNEG ","SAME","PIN_BIT_SCALAR"), + 3 => (" ","SX ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","SX2 ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","RIGHT ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","LEFT ","SAME","PIN_BIT_SCALAR"), + 7 => (" ","Q ","SAME","PIN_BIT_SCALAR"), + 8 => (" ","VDD ","SAME","PIN_BIT_SCALAR"), + 9 => (" ","VSS ","SAME","PIN_BIT_SCALAR") + ); +-- synopsys translate_on +END c_prism_bthmx; + +ARCHITECTURE c_prism_bthmx OF c_prism_bthmx IS + + SIGNAL CENTER :STD_ULOGIC; + SIGNAL XN :STD_ULOGIC; + SIGNAL SPOS :STD_ULOGIC; + + +BEGIN + + XN <= NOT X; + + SPOS <= NOT SNEG; + + CENTER <= NOT( ( XN AND SPOS ) OR + ( X AND SNEG ) ); + + LEFT <= CENTER; -- OUTPUT + + + Q <= ( CENTER AND SX ) OR + ( RIGHT AND SX2 ) ; + + +END; diff --git a/rel/src/vhdl/clib/c_prism_csa32.vhdl b/rel/src/vhdl/clib/c_prism_csa32.vhdl new file mode 100644 index 0000000..bb4586c --- /dev/null +++ b/rel/src/vhdl/clib/c_prism_csa32.vhdl @@ -0,0 +1,78 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee; use ieee.std_logic_1164.all ; +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; +library support; use support.power_logic_pkg.all; + +ENTITY c_prism_csa32 IS + GENERIC ( btr : string := "CSA32_A2_A12TH" ); + PORT( + A : IN std_ulogic; + B : IN std_ulogic; + C : IN std_ulogic; + CAR : OUT std_ulogic; + SUM : OUT std_ulogic; + vd : inout power_logic; + gd : inout power_logic + ); + +-- synopsys translate_off + + + -- The following will be used by synthesis for unrolling the vector: + ATTRIBUTE PIN_BIT_INFORMATION of c_prism_csa32 : entity is + ( + 1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 3 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","CAR ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","SUM ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","VDD ","SAME","PIN_BIT_SCALAR"), + 7 => (" ","VSS ","SAME","PIN_BIT_SCALAR") + ); +-- synopsys translate_on +END c_prism_csa32; + +ARCHITECTURE c_prism_csa32 OF c_prism_csa32 IS + + +BEGIN + + sum <= a XOR b XOR c ; + + car <= (a AND b ) OR + (a AND c ) OR + (b AND c ); + + +END; diff --git a/rel/src/vhdl/clib/c_prism_csa42.vhdl b/rel/src/vhdl/clib/c_prism_csa42.vhdl new file mode 100644 index 0000000..0f4df10 --- /dev/null +++ b/rel/src/vhdl/clib/c_prism_csa42.vhdl @@ -0,0 +1,92 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; use ieee.std_logic_1164.all ; +library support; +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + use support.power_logic_pkg.all; + +ENTITY c_prism_csa42 IS + GENERIC ( btr : string := "CSA42_A2_A12TH" ); + PORT( + A : IN std_ulogic; + B : IN std_ulogic; + C : IN std_ulogic; + D : IN std_ulogic; + KI : IN std_ulogic; + KO : OUT std_ulogic; + CAR : OUT std_ulogic; + SUM : OUT std_ulogic; + vd : inout power_logic; + gd : inout power_logic + ); + +-- synopsys translate_off + + + -- The following will be used by synthesis for unrolling the vector: + ATTRIBUTE PIN_BIT_INFORMATION of c_prism_csa42 : entity is + ( + 1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 3 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","D ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","KI ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","KO ","SAME","PIN_BIT_SCALAR"), + 7 => (" ","CAR ","SAME","PIN_BIT_SCALAR"), + 8 => (" ","SUM ","SAME","PIN_BIT_SCALAR"), + 9 => (" ","VDD ","SAME","PIN_BIT_SCALAR"), + 10 => (" ","VSS ","SAME","PIN_BIT_SCALAR") + ); +-- synopsys translate_on +END c_prism_csa42; + +ARCHITECTURE c_prism_csa42 OF c_prism_csa42 IS + + signal s1 : std_ulogic; + +BEGIN + + s1 <= b XOR c XOR d ; + sum <= s1 XOR a XOR ki; + + car <= (s1 AND a ) OR + (s1 AND ki) OR + (a AND ki); + + ko <= (b AND c ) OR + (b AND d ) OR + (c AND d ); + + +END; diff --git a/rel/src/vhdl/clib/c_scom_addr_decode.vhdl b/rel/src/vhdl/clib/c_scom_addr_decode.vhdl new file mode 100644 index 0000000..f7cc48c --- /dev/null +++ b/rel/src/vhdl/clib/c_scom_addr_decode.vhdl @@ -0,0 +1,81 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +-- *!**************************************************************** +-- *! FILENAME : c_scom_addr_decode.vhdl +-- *! TITLE : +-- *! DESCRIPTION : Generic SCOM address decoder +-- *! +-- *!**************************************************************** + +library ieee,ibm,clib,support; +use ieee.std_logic_1164.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use support.power_logic_pkg.all; + +entity c_scom_addr_decode is + generic( satid_nobits : positive := 5 -- should not be set by user + -- Set the following 3 vectors to generate an SCOM address + -- HEX >>>>> "0000000000000000111111111111111122222222222222223333333333333333" + -- ADDR >>>>> "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + -- + -- DEC >>>>> "0000000000111111111122222222223333333333444444444455555555556666" + -- ADDR >>>>> "0123456789012345678901234567890123456789012345678901234567890123" + ; use_addr : std_ulogic_vector := "1" + ; addr_is_rdable : std_ulogic_vector := "1" + ; addr_is_wrable : std_ulogic_vector := "1" + ); + port( sc_addr : in std_ulogic_vector(0 to 11-satid_nobits-1) -- binary coded scom address + ; scaddr_dec : out std_ulogic_vector(0 to use_addr'length-1) -- one hot coded scom address; not latched + ; sc_req : in std_ulogic -- scom request + ; sc_r_nw : in std_ulogic -- read / not write bit + ; scaddr_nvld : out std_ulogic -- scom address not valid; not latched + ; sc_wr_nvld : out std_ulogic -- scom write not allowed; not latched + ; sc_rd_nvld : out std_ulogic -- scom read not allowed; not latched + ; vd : inout power_logic + ; gd : inout power_logic + ); + +end c_scom_addr_decode; + + + +architecture c_scom_addr_decode of c_scom_addr_decode is + signal address : std_ulogic_vector(0 to use_addr'length-1); +begin + decode_it : for i in 0 to use_addr'length-1 generate + address(i) <= ((sc_addr = tconv(i,sc_addr'length)) and (use_addr(i)='1')); + end generate decode_it; + + scaddr_dec <= address; + scaddr_nvld <= sc_req and not or_reduce(address); + sc_wr_nvld <= not or_reduce(address and addr_is_wrable) and sc_req and not sc_r_nw; + sc_rd_nvld <= not or_reduce(address and addr_is_rdable) and sc_req and sc_r_nw; +end c_scom_addr_decode; diff --git a/rel/src/vhdl/ibm/std_ulogic_ao_support.vhdl b/rel/src/vhdl/ibm/std_ulogic_ao_support.vhdl new file mode 100644 index 0000000..cea3409 --- /dev/null +++ b/rel/src/vhdl/ibm/std_ulogic_ao_support.vhdl @@ -0,0 +1,11616 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +--*************************************************************************** +-- Copyright 2020 International Business Machines +-- +-- Licensed under the Apache License, Version 2.0 (the “License”); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- The patent license granted to you in Section 3 of the License, as applied +-- to the “Work,” hereby includes implementations of the Work in physical form. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an “AS IS” BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- +--*************************************************************************** +library ibm,ieee ; +use ieee.std_logic_1164.all ; +use ibm.std_ulogic_support.all; + +package std_ulogic_ao_support is + -- ============================================================= + -- 2 input Port AO/OA Gates + -- ============================================================= + -- Single bit case + -- Multiple vectors logically ed bitwise + function gate_ao_2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_ao_2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_ao_2x1 : function is "VHDL-AO" ; + attribute recursive_synthesis of gate_ao_2x1 : function is true; + attribute pin_bit_information of gate_ao_2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","PASS "," "," "), + 5 => (" ","PASS "," "," "), + 6 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function ao_2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function ao_2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of ao_2x1 : function is "VHDL-AO" ; + attribute recursive_synthesis of ao_2x1 : function is true; + attribute pin_bit_information of ao_2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","PASS "," "," "), + 5 => (" ","PASS "," "," "), + 6 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_aoi_2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_aoi_2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_aoi_2x1 : function is "VHDL-AOI" ; + attribute recursive_synthesis of gate_aoi_2x1 : function is true; + attribute pin_bit_information of gate_aoi_2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","PASS "," "," "), + 5 => (" ","PASS "," "," "), + 6 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function aoi_2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function aoi_2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of aoi_2x1 : function is "VHDL-AOI" ; + attribute recursive_synthesis of aoi_2x1 : function is true; + attribute pin_bit_information of aoi_2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","PASS "," "," "), + 5 => (" ","PASS "," "," "), + 6 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oa_2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oa_2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oa_2x1 : function is "VHDL-OA" ; + attribute recursive_synthesis of gate_oa_2x1 : function is true; + attribute pin_bit_information of gate_oa_2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","PASS "," "," "), + 5 => (" ","PASS "," "," "), + 6 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oa_2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oa_2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oa_2x1 : function is "VHDL-OA" ; + attribute recursive_synthesis of oa_2x1 : function is true; + attribute pin_bit_information of oa_2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","PASS "," "," "), + 5 => (" ","PASS "," "," "), + 6 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oai_2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oai_2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oai_2x1 : function is "VHDL-OAI" ; + attribute recursive_synthesis of gate_oai_2x1 : function is true; + attribute pin_bit_information of gate_oai_2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","PASS "," "," "), + 5 => (" ","PASS "," "," "), + 6 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oai_2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oai_2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oai_2x1 : function is "VHDL-OAI" ; + attribute recursive_synthesis of oai_2x1 : function is true; + attribute pin_bit_information of oai_2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","PASS "," "," "), + 5 => (" ","PASS "," "," "), + 6 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_ao_2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_ao_2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_ao_2x2 : function is "VHDL-AO" ; + attribute recursive_synthesis of gate_ao_2x2 : function is true; + attribute pin_bit_information of gate_ao_2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function ao_2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function ao_2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of ao_2x2 : function is "VHDL-AO" ; + attribute recursive_synthesis of ao_2x2 : function is true; + attribute pin_bit_information of ao_2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_aoi_2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_aoi_2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_aoi_2x2 : function is "VHDL-AOI" ; + attribute recursive_synthesis of gate_aoi_2x2 : function is true; + attribute pin_bit_information of gate_aoi_2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function aoi_2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function aoi_2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of aoi_2x2 : function is "VHDL-AOI" ; + attribute recursive_synthesis of aoi_2x2 : function is true; + attribute pin_bit_information of aoi_2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oa_2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oa_2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oa_2x2 : function is "VHDL-OA" ; + attribute recursive_synthesis of gate_oa_2x2 : function is true; + attribute pin_bit_information of gate_oa_2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oa_2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oa_2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oa_2x2 : function is "VHDL-OA" ; + attribute recursive_synthesis of oa_2x2 : function is true; + attribute pin_bit_information of oa_2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oai_2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oai_2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oai_2x2 : function is "VHDL-OAI" ; + attribute recursive_synthesis of gate_oai_2x2 : function is true; + attribute pin_bit_information of gate_oai_2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oai_2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oai_2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oai_2x2 : function is "VHDL-OAI" ; + attribute recursive_synthesis of oai_2x2 : function is true; + attribute pin_bit_information of oai_2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + -- ============================================================= + -- 2x3 input Port AO/OA Gates + -- ============================================================= + -- Vectored primitive input functions + -- Single bit case + -- Multiple vectors logically ed bitwise + function gate_ao_2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_ao_2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_ao_2x1x1 : function is "VHDL-AO" ; + attribute recursive_synthesis of gate_ao_2x1x1 : function is true; + attribute pin_bit_information of gate_ao_2x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function ao_2x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in2a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function ao_2x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in2a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of ao_2x1x1 : function is "VHDL-AO" ; + attribute recursive_synthesis of ao_2x1x1 : function is true; + attribute pin_bit_information of ao_2x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_aoi_2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_aoi_2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_aoi_2x1x1 : function is "VHDL-AOI" ; + attribute recursive_synthesis of gate_aoi_2x1x1 : function is true; + attribute pin_bit_information of gate_aoi_2x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function aoi_2x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in2a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function aoi_2x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in2a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of aoi_2x1x1 : function is "VHDL-AOI" ; + attribute recursive_synthesis of aoi_2x1x1 : function is true; + attribute pin_bit_information of aoi_2x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oa_2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oa_2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oa_2x1x1 : function is "VHDL-OA" ; + attribute recursive_synthesis of gate_oa_2x1x1 : function is true; + attribute pin_bit_information of gate_oa_2x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oa_2x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in2a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oa_2x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in2a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oa_2x1x1 : function is "VHDL-OA" ; + attribute recursive_synthesis of oa_2x1x1 : function is true; + attribute pin_bit_information of oa_2x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oai_2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oai_2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oai_2x1x1 : function is "VHDL-OAI" ; + attribute recursive_synthesis of gate_oai_2x1x1 : function is true; + attribute pin_bit_information of gate_oai_2x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oai_2x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in2a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oai_2x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in2a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oai_2x1x1 : function is "VHDL-OAI" ; + attribute recursive_synthesis of oai_2x1x1 : function is true; + attribute pin_bit_information of oai_2x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_ao_2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_ao_2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_ao_2x2x1 : function is "VHDL-AO" ; + attribute recursive_synthesis of gate_ao_2x2x1 : function is true; + attribute pin_bit_information of gate_ao_2x2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function ao_2x2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function ao_2x2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of ao_2x2x1 : function is "VHDL-AO" ; + attribute recursive_synthesis of ao_2x2x1 : function is true; + attribute pin_bit_information of ao_2x2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_aoi_2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_aoi_2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_aoi_2x2x1 : function is "VHDL-AOI" ; + attribute recursive_synthesis of gate_aoi_2x2x1 : function is true; + attribute pin_bit_information of gate_aoi_2x2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function aoi_2x2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function aoi_2x2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of aoi_2x2x1 : function is "VHDL-AOI" ; + attribute recursive_synthesis of aoi_2x2x1 : function is true; + attribute pin_bit_information of aoi_2x2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oa_2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oa_2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oa_2x2x1 : function is "VHDL-OA" ; + attribute recursive_synthesis of gate_oa_2x2x1 : function is true; + attribute pin_bit_information of gate_oa_2x2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oa_2x2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oa_2x2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oa_2x2x1 : function is "VHDL-OA" ; + attribute recursive_synthesis of oa_2x2x1 : function is true; + attribute pin_bit_information of oa_2x2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oai_2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oai_2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oai_2x2x1 : function is "VHDL-OAI" ; + attribute recursive_synthesis of gate_oai_2x2x1 : function is true; + attribute pin_bit_information of gate_oai_2x2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oai_2x2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oai_2x2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oai_2x2x1 : function is "VHDL-OAI" ; + attribute recursive_synthesis of oai_2x2x1 : function is true; + attribute pin_bit_information of oai_2x2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_ao_2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_ao_2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_ao_2x2x2 : function is "VHDL-AO" ; + attribute recursive_synthesis of gate_ao_2x2x2 : function is true; + attribute pin_bit_information of gate_ao_2x2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function ao_2x2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function ao_2x2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of ao_2x2x2 : function is "VHDL-AO" ; + attribute recursive_synthesis of ao_2x2x2 : function is true; + attribute pin_bit_information of ao_2x2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_aoi_2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_aoi_2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_aoi_2x2x2 : function is "VHDL-AOI" ; + attribute recursive_synthesis of gate_aoi_2x2x2 : function is true; + attribute pin_bit_information of gate_aoi_2x2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function aoi_2x2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function aoi_2x2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of aoi_2x2x2 : function is "VHDL-AOI" ; + attribute recursive_synthesis of aoi_2x2x2 : function is true; + attribute pin_bit_information of aoi_2x2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oa_2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oa_2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oa_2x2x2 : function is "VHDL-OA" ; + attribute recursive_synthesis of gate_oa_2x2x2 : function is true; + attribute pin_bit_information of gate_oa_2x2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oa_2x2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oa_2x2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oa_2x2x2 : function is "VHDL-OA" ; + attribute recursive_synthesis of oa_2x2x2 : function is true; + attribute pin_bit_information of oa_2x2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oai_2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oai_2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oai_2x2x2 : function is "VHDL-OAI" ; + attribute recursive_synthesis of gate_oai_2x2x2 : function is true; + attribute pin_bit_information of gate_oai_2x2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oai_2x2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oai_2x2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oai_2x2x2 : function is "VHDL-OAI" ; + attribute recursive_synthesis of oai_2x2x2 : function is true; + attribute pin_bit_information of oai_2x2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + -- ============================================================= + -- 2x4 input Port AO/OA Gates + -- ============================================================= + -- Vectored primitive input functions + -- Single bit case + -- Multiple vectors logically ed bitwise + function gate_ao_2x1x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_ao_2x1x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_ao_2x1x1x1 : function is "VHDL-AO" ; + attribute recursive_synthesis of gate_ao_2x1x1x1 : function is true; + attribute pin_bit_information of gate_ao_2x1x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","D ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function ao_2x1x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in2a : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function ao_2x1x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of ao_2x1x1x1 : function is "VHDL-AO" ; + attribute recursive_synthesis of ao_2x1x1x1 : function is true; + attribute pin_bit_information of ao_2x1x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_aoi_2x1x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_aoi_2x1x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_aoi_2x1x1x1 : function is "VHDL-AOI" ; + attribute recursive_synthesis of gate_aoi_2x1x1x1 : function is true; + attribute pin_bit_information of gate_aoi_2x1x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","D ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function aoi_2x1x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in2a : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function aoi_2x1x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of aoi_2x1x1x1 : function is "VHDL-AOI" ; + attribute recursive_synthesis of aoi_2x1x1x1 : function is true; + attribute pin_bit_information of aoi_2x1x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oa_2x1x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oa_2x1x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oa_2x1x1x1 : function is "VHDL-OA" ; + attribute recursive_synthesis of gate_oa_2x1x1x1 : function is true; + attribute pin_bit_information of gate_oa_2x1x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","D ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oa_2x1x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in2a : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oa_2x1x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oa_2x1x1x1 : function is "VHDL-OA" ; + attribute recursive_synthesis of oa_2x1x1x1 : function is true; + attribute pin_bit_information of oa_2x1x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oai_2x1x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oai_2x1x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oai_2x1x1x1 : function is "VHDL-OAI" ; + attribute recursive_synthesis of gate_oai_2x1x1x1 : function is true; + attribute pin_bit_information of gate_oai_2x1x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","D ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oai_2x1x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in2a : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oai_2x1x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oai_2x1x1x1 : function is "VHDL-OAI" ; + attribute recursive_synthesis of oai_2x1x1x1 : function is true; + attribute pin_bit_information of oai_2x1x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_ao_2x2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_ao_2x2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_ao_2x2x1x1 : function is "VHDL-AO" ; + attribute recursive_synthesis of gate_ao_2x2x1x1 : function is true; + attribute pin_bit_information of gate_ao_2x2x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","D ","SAME","PIN_BIT_SCALAR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function ao_2x2x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function ao_2x2x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of ao_2x2x1x1 : function is "VHDL-AO" ; + attribute recursive_synthesis of ao_2x2x1x1 : function is true; + attribute pin_bit_information of ao_2x2x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_aoi_2x2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_aoi_2x2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_aoi_2x2x1x1 : function is "VHDL-AOI" ; + attribute recursive_synthesis of gate_aoi_2x2x1x1 : function is true; + attribute pin_bit_information of gate_aoi_2x2x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","D ","SAME","PIN_BIT_SCALAR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function aoi_2x2x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function aoi_2x2x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of aoi_2x2x1x1 : function is "VHDL-AOI" ; + attribute recursive_synthesis of aoi_2x2x1x1 : function is true; + attribute pin_bit_information of aoi_2x2x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oa_2x2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oa_2x2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oa_2x2x1x1 : function is "VHDL-OA" ; + attribute recursive_synthesis of gate_oa_2x2x1x1 : function is true; + attribute pin_bit_information of gate_oa_2x2x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","D ","SAME","PIN_BIT_SCALAR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oa_2x2x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oa_2x2x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oa_2x2x1x1 : function is "VHDL-OA" ; + attribute recursive_synthesis of oa_2x2x1x1 : function is true; + attribute pin_bit_information of oa_2x2x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oai_2x2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oai_2x2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oai_2x2x1x1 : function is "VHDL-OAI" ; + attribute recursive_synthesis of gate_oai_2x2x1x1 : function is true; + attribute pin_bit_information of gate_oai_2x2x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","D ","SAME","PIN_BIT_SCALAR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oai_2x2x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oai_2x2x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oai_2x2x1x1 : function is "VHDL-OAI" ; + attribute recursive_synthesis of oai_2x2x1x1 : function is true; + attribute pin_bit_information of oai_2x2x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_ao_2x2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_ao_2x2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_ao_2x2x2x1 : function is "VHDL-AO" ; + attribute recursive_synthesis of gate_ao_2x2x2x1 : function is true; + attribute pin_bit_information of gate_ao_2x2x2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","D ","SAME","PIN_BIT_SCALAR"), + 8 => (" ","PASS "," "," "), + 9 => (" ","PASS "," "," "), + 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function ao_2x2x2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function ao_2x2x2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of ao_2x2x2x1 : function is "VHDL-AO" ; + attribute recursive_synthesis of ao_2x2x2x1 : function is true; + attribute pin_bit_information of ao_2x2x2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","PASS "," "," "), + 9 => (" ","PASS "," "," "), + 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_aoi_2x2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_aoi_2x2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_aoi_2x2x2x1 : function is "VHDL-AOI" ; + attribute recursive_synthesis of gate_aoi_2x2x2x1 : function is true; + attribute pin_bit_information of gate_aoi_2x2x2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","D ","SAME","PIN_BIT_SCALAR"), + 8 => (" ","PASS "," "," "), + 9 => (" ","PASS "," "," "), + 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function aoi_2x2x2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function aoi_2x2x2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of aoi_2x2x2x1 : function is "VHDL-AOI" ; + attribute recursive_synthesis of aoi_2x2x2x1 : function is true; + attribute pin_bit_information of aoi_2x2x2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","PASS "," "," "), + 9 => (" ","PASS "," "," "), + 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oa_2x2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oa_2x2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oa_2x2x2x1 : function is "VHDL-OA" ; + attribute recursive_synthesis of gate_oa_2x2x2x1 : function is true; + attribute pin_bit_information of gate_oa_2x2x2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","D ","SAME","PIN_BIT_SCALAR"), + 8 => (" ","PASS "," "," "), + 9 => (" ","PASS "," "," "), + 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oa_2x2x2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oa_2x2x2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oa_2x2x2x1 : function is "VHDL-OA" ; + attribute recursive_synthesis of oa_2x2x2x1 : function is true; + attribute pin_bit_information of oa_2x2x2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","PASS "," "," "), + 9 => (" ","PASS "," "," "), + 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oai_2x2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oai_2x2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oai_2x2x2x1 : function is "VHDL-OAI" ; + attribute recursive_synthesis of gate_oai_2x2x2x1 : function is true; + attribute pin_bit_information of gate_oai_2x2x2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","D ","SAME","PIN_BIT_SCALAR"), + 8 => (" ","PASS "," "," "), + 9 => (" ","PASS "," "," "), + 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oai_2x2x2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oai_2x2x2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oai_2x2x2x1 : function is "VHDL-OAI" ; + attribute recursive_synthesis of oai_2x2x2x1 : function is true; + attribute pin_bit_information of oai_2x2x2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","PASS "," "," "), + 9 => (" ","PASS "," "," "), + 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_ao_2x2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_ao_2x2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_ao_2x2x2x2 : function is "VHDL-AO" ; + attribute recursive_synthesis of gate_ao_2x2x2x2 : function is true; + attribute pin_bit_information of gate_ao_2x2x2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","D ","SAME","PIN_BIT_SCALAR"), + 8 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function ao_2x2x2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic ; + in3a : std_ulogic ; + in3b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function ao_2x2x2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector ; + in3a : std_ulogic_vector ; + in3b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of ao_2x2x2x2 : function is "VHDL-AO" ; + attribute recursive_synthesis of ao_2x2x2x2 : function is true; + attribute pin_bit_information of ao_2x2x2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_aoi_2x2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_aoi_2x2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_aoi_2x2x2x2 : function is "VHDL-AOI" ; + attribute recursive_synthesis of gate_aoi_2x2x2x2 : function is true; + attribute pin_bit_information of gate_aoi_2x2x2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","D ","SAME","PIN_BIT_SCALAR"), + 8 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function aoi_2x2x2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic ; + in3a : std_ulogic ; + in3b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function aoi_2x2x2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector ; + in3a : std_ulogic_vector ; + in3b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of aoi_2x2x2x2 : function is "VHDL-AOI" ; + attribute recursive_synthesis of aoi_2x2x2x2 : function is true; + attribute pin_bit_information of aoi_2x2x2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oa_2x2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oa_2x2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oa_2x2x2x2 : function is "VHDL-OA" ; + attribute recursive_synthesis of gate_oa_2x2x2x2 : function is true; + attribute pin_bit_information of gate_oa_2x2x2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","D ","SAME","PIN_BIT_SCALAR"), + 8 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oa_2x2x2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic ; + in3a : std_ulogic ; + in3b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oa_2x2x2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector ; + in3a : std_ulogic_vector ; + in3b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oa_2x2x2x2 : function is "VHDL-OA" ; + attribute recursive_synthesis of oa_2x2x2x2 : function is true; + attribute pin_bit_information of oa_2x2x2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oai_2x2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oai_2x2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oai_2x2x2x2 : function is "VHDL-OAI" ; + attribute recursive_synthesis of gate_oai_2x2x2x2 : function is true; + attribute pin_bit_information of gate_oai_2x2x2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","D ","SAME","PIN_BIT_SCALAR"), + 8 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oai_2x2x2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic ; + in3a : std_ulogic ; + in3b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oai_2x2x2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector ; + in3a : std_ulogic_vector ; + in3b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oai_2x2x2x2 : function is "VHDL-OAI" ; + attribute recursive_synthesis of oai_2x2x2x2 : function is true; + attribute pin_bit_information of oai_2x2x2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + -- ============================================================= + -- 3 input Port AO/OA Gates + -- ============================================================= + -- Vectored primitive input functions + -- Single bit case + -- Multiple vectors logically ed bitwise + function gate_ao_3x1 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_ao_3x1 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_ao_3x1 : function is "VHDL-AO" ; + attribute recursive_synthesis of gate_ao_3x1 : function is true; + attribute pin_bit_information of gate_ao_3x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function ao_3x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function ao_3x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of ao_3x1 : function is "VHDL-AO" ; + attribute recursive_synthesis of ao_3x1 : function is true; + attribute pin_bit_information of ao_3x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_aoi_3x1 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_aoi_3x1 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_aoi_3x1 : function is "VHDL-AOI" ; + attribute recursive_synthesis of gate_aoi_3x1 : function is true; + attribute pin_bit_information of gate_aoi_3x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function aoi_3x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function aoi_3x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of aoi_3x1 : function is "VHDL-AOI" ; + attribute recursive_synthesis of aoi_3x1 : function is true; + attribute pin_bit_information of aoi_3x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oa_3x1 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oa_3x1 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oa_3x1 : function is "VHDL-OA" ; + attribute recursive_synthesis of gate_oa_3x1 : function is true; + attribute pin_bit_information of gate_oa_3x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oa_3x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oa_3x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oa_3x1 : function is "VHDL-OA" ; + attribute recursive_synthesis of oa_3x1 : function is true; + attribute pin_bit_information of oa_3x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oai_3x1 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oai_3x1 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oai_3x1 : function is "VHDL-OAI" ; + attribute recursive_synthesis of gate_oai_3x1 : function is true; + attribute pin_bit_information of gate_oai_3x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oai_3x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oai_3x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oai_3x1 : function is "VHDL-OAI" ; + attribute recursive_synthesis of oai_3x1 : function is true; + attribute pin_bit_information of oai_3x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_ao_3x2 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_ao_3x2 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_ao_3x2 : function is "VHDL-AO" ; + attribute recursive_synthesis of gate_ao_3x2 : function is true; + attribute pin_bit_information of gate_ao_3x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function ao_3x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function ao_3x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of ao_3x2 : function is "VHDL-AO" ; + attribute recursive_synthesis of ao_3x2 : function is true; + attribute pin_bit_information of ao_3x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_aoi_3x2 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_aoi_3x2 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_aoi_3x2 : function is "VHDL-AOI" ; + attribute recursive_synthesis of gate_aoi_3x2 : function is true; + attribute pin_bit_information of gate_aoi_3x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function aoi_3x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function aoi_3x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of aoi_3x2 : function is "VHDL-AOI" ; + attribute recursive_synthesis of aoi_3x2 : function is true; + attribute pin_bit_information of aoi_3x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oa_3x2 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oa_3x2 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oa_3x2 : function is "VHDL-OA" ; + attribute recursive_synthesis of gate_oa_3x2 : function is true; + attribute pin_bit_information of gate_oa_3x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oa_3x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oa_3x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oa_3x2 : function is "VHDL-OA" ; + attribute recursive_synthesis of oa_3x2 : function is true; + attribute pin_bit_information of oa_3x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oai_3x2 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oai_3x2 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oai_3x2 : function is "VHDL-OAI" ; + attribute recursive_synthesis of gate_oai_3x2 : function is true; + attribute pin_bit_information of gate_oai_3x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oai_3x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oai_3x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oai_3x2 : function is "VHDL-OAI" ; + attribute recursive_synthesis of oai_3x2 : function is true; + attribute pin_bit_information of oai_3x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_ao_3x3 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_ao_3x3 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_ao_3x3 : function is "VHDL-AO" ; + attribute recursive_synthesis of gate_ao_3x3 : function is true; + attribute pin_bit_information of gate_ao_3x3 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function ao_3x3 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function ao_3x3 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of ao_3x3 : function is "VHDL-AO" ; + attribute recursive_synthesis of ao_3x3 : function is true; + attribute pin_bit_information of ao_3x3 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_aoi_3x3 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_aoi_3x3 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_aoi_3x3 : function is "VHDL-AOI" ; + attribute recursive_synthesis of gate_aoi_3x3 : function is true; + attribute pin_bit_information of gate_aoi_3x3 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function aoi_3x3 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function aoi_3x3 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of aoi_3x3 : function is "VHDL-AOI" ; + attribute recursive_synthesis of aoi_3x3 : function is true; + attribute pin_bit_information of aoi_3x3 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oa_3x3 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oa_3x3 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oa_3x3 : function is "VHDL-OA" ; + attribute recursive_synthesis of gate_oa_3x3 : function is true; + attribute pin_bit_information of gate_oa_3x3 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oa_3x3 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oa_3x3 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oa_3x3 : function is "VHDL-OA" ; + attribute recursive_synthesis of oa_3x3 : function is true; + attribute pin_bit_information of oa_3x3 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oai_3x3 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oai_3x3 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oai_3x3 : function is "VHDL-OAI" ; + attribute recursive_synthesis of gate_oai_3x3 : function is true; + attribute pin_bit_information of gate_oai_3x3 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oai_3x3 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oai_3x3 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oai_3x3 : function is "VHDL-OAI" ; + attribute recursive_synthesis of oai_3x3 : function is true; + attribute pin_bit_information of oai_3x3 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + -- ============================================================= + -- 4 input Port AO/OA Gates + -- ============================================================= + -- Vectored primitive input functions + -- Single bit case + -- Multiple vectors logically ed bitwise + function gate_ao_4x1 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_ao_4x1 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_ao_4x1 : function is "VHDL-AO" ; + attribute recursive_synthesis of gate_ao_4x1 : function is true; + attribute pin_bit_information of gate_ao_4x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function ao_4x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function ao_4x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of ao_4x1 : function is "VHDL-AO" ; + attribute recursive_synthesis of ao_4x1 : function is true; + attribute pin_bit_information of ao_4x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_aoi_4x1 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_aoi_4x1 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_aoi_4x1 : function is "VHDL-AOI" ; + attribute recursive_synthesis of gate_aoi_4x1 : function is true; + attribute pin_bit_information of gate_aoi_4x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function aoi_4x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function aoi_4x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of aoi_4x1 : function is "VHDL-AOI" ; + attribute recursive_synthesis of aoi_4x1 : function is true; + attribute pin_bit_information of aoi_4x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oa_4x1 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oa_4x1 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oa_4x1 : function is "VHDL-OA" ; + attribute recursive_synthesis of gate_oa_4x1 : function is true; + attribute pin_bit_information of gate_oa_4x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oa_4x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oa_4x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oa_4x1 : function is "VHDL-OA" ; + attribute recursive_synthesis of oa_4x1 : function is true; + attribute pin_bit_information of oa_4x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oai_4x1 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oai_4x1 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oai_4x1 : function is "VHDL-OAI" ; + attribute recursive_synthesis of gate_oai_4x1 : function is true; + attribute pin_bit_information of gate_oai_4x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oai_4x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oai_4x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oai_4x1 : function is "VHDL-OAI" ; + attribute recursive_synthesis of oai_4x1 : function is true; + attribute pin_bit_information of oai_4x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_ao_4x2 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_ao_4x2 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_ao_4x2 : function is "VHDL-AO" ; + attribute recursive_synthesis of gate_ao_4x2 : function is true; + attribute pin_bit_information of gate_ao_4x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function ao_4x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function ao_4x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of ao_4x2 : function is "VHDL-AO" ; + attribute recursive_synthesis of ao_4x2 : function is true; + attribute pin_bit_information of ao_4x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_aoi_4x2 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_aoi_4x2 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_aoi_4x2 : function is "VHDL-AOI" ; + attribute recursive_synthesis of gate_aoi_4x2 : function is true; + attribute pin_bit_information of gate_aoi_4x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function aoi_4x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function aoi_4x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of aoi_4x2 : function is "VHDL-AOI" ; + attribute recursive_synthesis of aoi_4x2 : function is true; + attribute pin_bit_information of aoi_4x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oa_4x2 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oa_4x2 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oa_4x2 : function is "VHDL-OA" ; + attribute recursive_synthesis of gate_oa_4x2 : function is true; + attribute pin_bit_information of gate_oa_4x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oa_4x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oa_4x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oa_4x2 : function is "VHDL-OA" ; + attribute recursive_synthesis of oa_4x2 : function is true; + attribute pin_bit_information of oa_4x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oai_4x2 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oai_4x2 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oai_4x2 : function is "VHDL-OAI" ; + attribute recursive_synthesis of gate_oai_4x2 : function is true; + attribute pin_bit_information of gate_oai_4x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oai_4x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oai_4x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oai_4x2 : function is "VHDL-OAI" ; + attribute recursive_synthesis of oai_4x2 : function is true; + attribute pin_bit_information of oai_4x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_ao_4x3 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_ao_4x3 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_ao_4x3 : function is "VHDL-AO" ; + attribute recursive_synthesis of gate_ao_4x3 : function is true; + attribute pin_bit_information of gate_ao_4x3 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","PASS "," "," "), + 9 => (" ","PASS "," "," "), + 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function ao_4x3 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function ao_4x3 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of ao_4x3 : function is "VHDL-AO" ; + attribute recursive_synthesis of ao_4x3 : function is true; + attribute pin_bit_information of ao_4x3 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","PASS "," "," "), + 9 => (" ","PASS "," "," "), + 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_aoi_4x3 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_aoi_4x3 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_aoi_4x3 : function is "VHDL-AOI" ; + attribute recursive_synthesis of gate_aoi_4x3 : function is true; + attribute pin_bit_information of gate_aoi_4x3 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","PASS "," "," "), + 9 => (" ","PASS "," "," "), + 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function aoi_4x3 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function aoi_4x3 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of aoi_4x3 : function is "VHDL-AOI" ; + attribute recursive_synthesis of aoi_4x3 : function is true; + attribute pin_bit_information of aoi_4x3 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","PASS "," "," "), + 9 => (" ","PASS "," "," "), + 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oa_4x3 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oa_4x3 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oa_4x3 : function is "VHDL-OA" ; + attribute recursive_synthesis of gate_oa_4x3 : function is true; + attribute pin_bit_information of gate_oa_4x3 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","PASS "," "," "), + 9 => (" ","PASS "," "," "), + 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oa_4x3 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oa_4x3 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oa_4x3 : function is "VHDL-OA" ; + attribute recursive_synthesis of oa_4x3 : function is true; + attribute pin_bit_information of oa_4x3 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","PASS "," "," "), + 9 => (" ","PASS "," "," "), + 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oai_4x3 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oai_4x3 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oai_4x3 : function is "VHDL-OAI" ; + attribute recursive_synthesis of gate_oai_4x3 : function is true; + attribute pin_bit_information of gate_oai_4x3 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","PASS "," "," "), + 9 => (" ","PASS "," "," "), + 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oai_4x3 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oai_4x3 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oai_4x3 : function is "VHDL-OAI" ; + attribute recursive_synthesis of oai_4x3 : function is true; + attribute pin_bit_information of oai_4x3 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","PASS "," "," "), + 9 => (" ","PASS "," "," "), + 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_ao_4x4 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_ao_4x4 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_ao_4x4 : function is "VHDL-AO" ; + attribute recursive_synthesis of gate_ao_4x4 : function is true; + attribute pin_bit_information of gate_ao_4x4 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function ao_4x4 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic ; + in1d : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function ao_4x4 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector ; + in1d : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of ao_4x4 : function is "VHDL-AO" ; + attribute recursive_synthesis of ao_4x4 : function is true; + attribute pin_bit_information of ao_4x4 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_aoi_4x4 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_aoi_4x4 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_aoi_4x4 : function is "VHDL-AOI" ; + attribute recursive_synthesis of gate_aoi_4x4 : function is true; + attribute pin_bit_information of gate_aoi_4x4 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function aoi_4x4 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic ; + in1d : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function aoi_4x4 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector ; + in1d : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of aoi_4x4 : function is "VHDL-AOI" ; + attribute recursive_synthesis of aoi_4x4 : function is true; + attribute pin_bit_information of aoi_4x4 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oa_4x4 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oa_4x4 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oa_4x4 : function is "VHDL-OA" ; + attribute recursive_synthesis of gate_oa_4x4 : function is true; + attribute pin_bit_information of gate_oa_4x4 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oa_4x4 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic ; + in1d : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oa_4x4 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector ; + in1d : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oa_4x4 : function is "VHDL-OA" ; + attribute recursive_synthesis of oa_4x4 : function is true; + attribute pin_bit_information of oa_4x4 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oai_4x4 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oai_4x4 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oai_4x4 : function is "VHDL-OAI" ; + attribute recursive_synthesis of gate_oai_4x4 : function is true; + attribute pin_bit_information of gate_oai_4x4 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oai_4x4 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic ; + in1d : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oai_4x4 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector ; + in1d : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oai_4x4 : function is "VHDL-OAI" ; + attribute recursive_synthesis of oai_4x4 : function is true; + attribute pin_bit_information of oai_4x4 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + +end std_ulogic_ao_support; + +package body std_ulogic_ao_support is + -- ============================================================= + -- 2 input port ao/oa gates + -- ============================================================= + function gate_ao_2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 and in0 ) or gate1 ; + return result ; + end gate_ao_2x1 ; + + function gate_ao_2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( 0 to in0'length-1 => gate1 ) ; + return result ; + end gate_ao_2x1 ; + + function ao_2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a and in0b ) or in1a; + return result ; + end ao_2x1 ; + + function ao_2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a and in0b ) or in1a; + return result ; + end ao_2x1 ; + + function gate_aoi_2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not ( ( gate0 and in0 ) or gate1 ); + return result ; + end gate_aoi_2x1 ; + + function gate_aoi_2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not ( ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( 0 to in0'length-1 => gate1 ) ); + return result ; + end gate_aoi_2x1 ; + + function aoi_2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a and in0b ) or in1a ) ; + return result ; + end aoi_2x1 ; + + function aoi_2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a and in0b ) or in1a ) ; + return result ; + end aoi_2x1 ; + + function gate_oa_2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 or in0 ) and gate1 ; + return result ; + end gate_oa_2x1 ; + + function gate_oa_2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) or in0 ) and + ( 0 to in0'length-1 => gate1 ) ; + return result ; + end gate_oa_2x1 ; + + function oa_2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a or in0b ) and in1a ; + return result ; + end oa_2x1 ; + + function oa_2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a or in0b ) and in1a ; + return result ; + end oa_2x1 ; + + function gate_oai_2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 or in0 ) and gate1 ) ; + return result ; + end gate_oai_2x1 ; + + function gate_oai_2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not( ( ( 0 to in0'length-1 => gate0 ) or in0 ) and + ( 0 to in0'length-1 => gate1 ) ) ; + return result ; + end gate_oai_2x1 ; + + function oai_2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a or in0b ) and in1a ) ; + return result ; + end oai_2x1 ; + + function oai_2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a or in0b ) and in1a ) ; + return result ; + end oai_2x1 ; + + function gate_ao_2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( ( gate0 and in0 ) or ( gate1 and in1 ) ) ; + return result ; + end gate_ao_2x2 ; + + function gate_ao_2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( ( 0 to in1'length-1 => gate1 ) and in1 ) ; + return result ; + end gate_ao_2x2 ; + + function ao_2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ((in0a and in0b) or (in1a and in1b)); + return result ; + end ao_2x2 ; + + function ao_2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ((in0a and in0b) or (in1a and in1b)); + return result ; + end ao_2x2 ; + + function gate_aoi_2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not ((gate0 and in0) or (gate1 and in1)); + return result ; + end gate_aoi_2x2 ; + + function gate_aoi_2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not ( ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( ( 0 to in0'length-1 => gate1 ) and in1 ) ); + return result ; + end gate_aoi_2x2 ; + + function aoi_2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not ((in0a and in0b) or (in1a and in1b)); + return result ; + end aoi_2x2 ; + + function aoi_2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not ( ( in0a and in0b ) or ( in1a and in1b ) ); + return result ; + end aoi_2x2 ; + + function gate_oa_2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ((gate0 or in0) and (gate1 or in1)); + return result ; + end gate_oa_2x2 ; + + function gate_oa_2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) or in0 ) and + ( ( 0 to in1'length-1 => gate1 ) or in1 ); + return result ; + end gate_oa_2x2 ; + + function oa_2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ((in0a or in0b) and (in1a or in1b)); + return result ; + end oa_2x2 ; + + function oa_2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( ( in0a or in0b ) and ( in1a or in1b ) ); + return result ; + end oa_2x2 ; + + function gate_oai_2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not ((gate0 or in0) and (gate1 or in1)); + return result ; + end gate_oai_2x2 ; + + function gate_oai_2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not ( ( ( 0 to in0'length-1 => gate0 ) or in0 ) and + ( ( 0 to in1'length-1 => gate1 ) or in1 ) ); + return result ; + end gate_oai_2x2 ; + + function oai_2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not ((in0a or in0b) and (in1a or in1b)); + return result ; + end oai_2x2 ; + + function oai_2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not ( ( in0a or in0b ) and ( in1a or in1b ) ); + return result ; + end oai_2x2 ; + + -- ============================================================= + -- 3x2 input Port AO/OA Gates + -- ============================================================= + + function gate_ao_2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 and in0 ) or + ( gate1 ) or + ( gate2 ); + return result ; + end gate_ao_2x1x1 ; + + function gate_ao_2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( 0 to in0'length-1 => gate1 ) or + ( 0 to in0'length-1 => gate2 ) ; + return result ; + end gate_ao_2x1x1 ; + + function ao_2x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in2a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a and in0b ) or ( in1a ) or ( in2a ) ; + return result ; + end ao_2x1x1 ; + + function ao_2x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in2a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a and in0b ) or + ( in1a ) or + ( in2a ) ; + return result ; + end ao_2x1x1 ; + + function gate_aoi_2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not ( ( gate0 and in0 ) or + ( gate1 ) or + ( gate2 ) ); + return result ; + end gate_aoi_2x1x1 ; + + function gate_aoi_2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not( ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( 0 to in0'length-1 => gate1 ) or + ( 0 to in0'length-1 => gate2 ) ); + return result ; + end gate_aoi_2x1x1 ; + + function aoi_2x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in2a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not ((in0a and in0b) or (in1a) or (in2a)); + return result ; + end aoi_2x1x1 ; + + function aoi_2x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in2a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not ( ( in0a and in0b ) or + ( in1a ) or + ( in2a ) ); + return result ; + end aoi_2x1x1 ; + + function gate_oa_2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 or in0 ) and + ( gate1 ) and + ( gate2 ); + return result ; + end gate_oa_2x1x1 ; + + function gate_oa_2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) or in0 ) and + ( 0 to in0'length-1 => gate1 ) and + ( 0 to in0'length-1 => gate2 ) ; + return result ; + end gate_oa_2x1x1 ; + + function oa_2x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in2a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( ( in0a or in0b ) and ( in1a ) and ( in2a ) ); + return result ; + end oa_2x1x1 ; + + function oa_2x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in2a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector(0 to in0a'length-1); + begin + result := ( ( in0a or in0b ) and + ( in1a ) and + ( in2a ) ); + return result ; + end oa_2x1x1 ; + + function gate_oai_2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not ( ( gate0 or in0 ) and + ( gate1 ) and + ( gate2 ) ) ; + return result ; + end gate_oai_2x1x1 ; + + function gate_oai_2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not ( ( ( 0 to in0'length-1 => gate0 ) or in0 ) and + ( 0 to in0'length-1 => gate1 ) and + ( 0 to in0'length-1 => gate2 ) ) ; + return result ; + end gate_oai_2x1x1 ; + + function oai_2x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in2a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not ((in0a or in0b) and (in1a) and (in2a)); + return result ; + end oai_2x1x1 ; + + function oai_2x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in2a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not ((in0a or in0b) and + (in1a) and + (in2a)); + return result ; + end oai_2x1x1 ; + + function gate_ao_2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 and in0 ) or + ( gate1 and in1 ) or + ( gate2 ) ; + return result ; + end gate_ao_2x2x1 ; + + function gate_ao_2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( ( 0 to in1'length-1 => gate1 ) and in1 ) or + ( 0 to in0'length-1 => gate2 ) ; + return result ; + end gate_ao_2x2x1 ; + + function ao_2x2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a and in0b ) or + ( in1a and in1b ) or + ( in2a ) ; + return result ; + end ao_2x2x1 ; + + function ao_2x2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ((in0a and in0b) or + (in1a and in1b) or + (in2a)); + return result ; + end ao_2x2x1 ; + + function gate_aoi_2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 and in0 ) or + ( gate1 and in1 ) or + ( gate2 ) ) ; + return result ; + end gate_aoi_2x2x1 ; + + function gate_aoi_2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not( ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( ( 0 to in1'length-1 => gate1 ) and in1 ) or + ( 0 to in0'length-1 => gate2 ) ) ; + return result ; + end gate_aoi_2x2x1 ; + + function aoi_2x2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a and in0b ) or + ( in1a and in1b ) or + ( in2a ) ) ; + return result ; + end aoi_2x2x1 ; + + function aoi_2x2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a and in0b ) or + ( in1a and in1b ) or + ( in2a ) ) ; + return result ; + end aoi_2x2x1 ; + + function gate_oa_2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 or in0 ) and + ( gate1 or in1 ) and + ( gate2 ) ; + return result ; + end gate_oa_2x2x1 ; + + function gate_oa_2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) or in0 ) and + ( ( 0 to in1'length-1 => gate1 ) or in1 ) and + ( 0 to in0'length-1 => gate2 ) ; + return result ; + end gate_oa_2x2x1 ; + + function oa_2x2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a or in0b ) and + ( in1a or in1b ) and + ( in2a ) ; + return result ; + end oa_2x2x1 ; + + function oa_2x2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a or in0b ) and + ( in1a or in1b ) and + ( in2a ) ; + return result ; + end oa_2x2x1 ; + + function gate_oai_2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 or in0 ) and + ( gate1 or in1 ) and + ( gate2 ) ); + return result ; + end gate_oai_2x2x1 ; + + function gate_oai_2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not( ( ( 0 to in0'length-1 => gate0 ) or in0 ) and + ( ( 0 to in1'length-1 => gate1 ) or in1 ) and + ( 0 to in0'length-1 => gate2 ) ) ; + return result ; + end gate_oai_2x2x1 ; + + function oai_2x2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a or in0b ) and + ( in1a or in1b ) and + ( in2a ) ); + return result ; + end oai_2x2x1 ; + + function oai_2x2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a or in0b ) and + ( in1a or in1b ) and + ( in2a ) ); + return result ; + end oai_2x2x1 ; + + function gate_ao_2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 and in0 ) or + ( gate1 and in1 ) or + ( gate2 and in2 ) ; + return result ; + end gate_ao_2x2x2 ; + + function gate_ao_2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( ( 0 to in1'length-1 => gate1 ) and in1 ) or + ( ( 0 to in2'length-1 => gate2 ) and in2 ) ; + return result ; + end gate_ao_2x2x2 ; + + function ao_2x2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a and in0b ) or + ( in1a and in1b ) or + ( in2a and in2b ) ; + return result ; + end ao_2x2x2 ; + + function ao_2x2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a and in0b ) or + ( in1a and in1b ) or + ( in2a and in2b ) ; + return result ; + end ao_2x2x2 ; + + function gate_aoi_2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 and in0 ) or + ( gate1 and in1 ) or + ( gate2 and in2 ) ); + return result ; + end gate_aoi_2x2x2 ; + + function gate_aoi_2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not( ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( ( 0 to in1'length-1 => gate1 ) and in1 ) or + ( ( 0 to in2'length-1 => gate2 ) and in2 ) ) ; + return result ; + end gate_aoi_2x2x2 ; + + function aoi_2x2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a and in0b ) or + ( in1a and in1b ) or + ( in2a and in2b ) ); + return result ; + end aoi_2x2x2 ; + + function aoi_2x2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a and in0b ) or + ( in1a and in1b ) or + ( in2a and in2b ) ); + return result ; + end aoi_2x2x2 ; + + function gate_oa_2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 or in0 ) and + ( gate1 or in1 ) and + ( gate2 or in2 ) ; + return result ; + end gate_oa_2x2x2 ; + + function gate_oa_2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) or in0 ) and + ( ( 0 to in1'length-1 => gate1 ) or in1 ) and + ( ( 0 to in2'length-1 => gate2 ) or in2 ) ; + return result ; + end gate_oa_2x2x2 ; + + function oa_2x2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a or in0b ) and + ( in1a or in1b ) and + ( in2a or in2b ) ; + return result ; + end oa_2x2x2 ; + + function oa_2x2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a or in0b ) and + ( in1a or in1b ) and + ( in2a or in2b ) ; + return result ; + end oa_2x2x2 ; + + function gate_oai_2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 or in0 ) and + ( gate1 or in1 ) and + ( gate2 or in2 ) ) ; + return result ; + end gate_oai_2x2x2 ; + + function gate_oai_2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not( ( ( 0 to in0'length-1 => gate0 ) or in0 ) and + ( ( 0 to in1'length-1 => gate1 ) or in1 ) and + ( ( 0 to in2'length-1 => gate2 ) or in2 ) ) ; + return result ; + end gate_oai_2x2x2 ; + + function oai_2x2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a or in0b ) and + ( in1a or in1b ) and + ( in2a or in2b ) ) ; + return result ; + end oai_2x2x2 ; + + function oai_2x2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a or in0b ) and + ( in1a or in1b ) and + ( in2a or in2b ) ) ; + return result ; + end oai_2x2x2 ; + + -- ============================================================= + -- 4x2 input Port AO/OA Gates + -- ============================================================= + + function gate_ao_2x1x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 and in0 ) or + ( gate1 ) or + ( gate2 ) or + ( gate3 ) ; + return result ; + end gate_ao_2x1x1x1 ; + + function gate_ao_2x1x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( 0 to in0'length-1 => gate1 ) or + ( 0 to in0'length-1 => gate2 ) or + ( 0 to in0'length-1 => gate3 ) ; + return result ; + end gate_ao_2x1x1x1 ; + + function ao_2x1x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in2a : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a and in0b ) or + ( in1a ) or + ( in2a ) or + ( in3a ) ; + return result ; + end ao_2x1x1x1 ; + + function ao_2x1x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a and in0b ) or + ( in1a ) or + ( in2a ) or + ( in3a ) ; + return result ; + end ao_2x1x1x1 ; + + function gate_aoi_2x1x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 and in0 ) or + ( gate1 ) or + ( gate2 ) or + ( gate3 ) ) ; + return result ; + end gate_aoi_2x1x1x1 ; + + function gate_aoi_2x1x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not( ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( 0 to in0'length-1 => gate1 ) or + ( 0 to in0'length-1 => gate2 ) or + ( 0 to in0'length-1 => gate3 ) ) ; + return result ; + end gate_aoi_2x1x1x1 ; + + function aoi_2x1x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in2a : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a and in0b ) or + ( in1a ) or + ( in2a ) or + ( in3a ) ) ; + return result ; + end aoi_2x1x1x1 ; + + function aoi_2x1x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a and in0b ) or + ( in1a ) or + ( in2a ) or + ( in3a ) ) ; + return result ; + end aoi_2x1x1x1 ; + + function gate_oa_2x1x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 or in0 ) and + ( gate1 ) and + ( gate2 ) and + ( gate3 ); + return result ; + end gate_oa_2x1x1x1 ; + + function gate_oa_2x1x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) or in0 ) and + ( 0 to in0'length-1 => gate1 ) and + ( 0 to in0'length-1 => gate2 ) and + ( 0 to in0'length-1 => gate3 ); + return result ; + end gate_oa_2x1x1x1 ; + + function oa_2x1x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in2a : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a or in0b ) and + ( in1a ) and + ( in2a ) and + ( in3a ) ; + return result ; + end oa_2x1x1x1 ; + + function oa_2x1x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a or in0b ) and + ( in1a ) and + ( in2a ) and + ( in3a ) ; + return result ; + end oa_2x1x1x1 ; + + function gate_oai_2x1x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 or in0 ) and + ( gate1 ) and + ( gate2 ) and + ( gate3 ) ) ; + return result ; + end gate_oai_2x1x1x1 ; + + function gate_oai_2x1x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not( ( ( 0 to in0'length-1 => gate0 ) or in0 ) and + ( 0 to in0'length-1 => gate1 ) and + ( 0 to in0'length-1 => gate2 ) and + ( 0 to in0'length-1 => gate3 ) ) ; + return result ; + end gate_oai_2x1x1x1 ; + + function oai_2x1x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in2a : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a or in0b ) and + ( in1a ) and + ( in2a ) and + ( in3a ) ) ; + return result ; + end oai_2x1x1x1 ; + + function oai_2x1x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a or in0b ) and + ( in1a ) and + ( in2a ) and + ( in3a ) ) ; + return result ; + end oai_2x1x1x1 ; + + function gate_ao_2x2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 and in0 ) or + ( gate1 and in1 ) or + ( gate2 ) or + ( gate3 ) ; + return result ; + end gate_ao_2x2x1x1 ; + + function gate_ao_2x2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( ( 0 to in1'length-1 => gate1 ) and in1 ) or + ( 0 to in0'length-1 => gate2 ) or + ( 0 to in0'length-1 => gate3 ) ; + return result ; + end gate_ao_2x2x1x1 ; + + function ao_2x2x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a and in0b ) or + ( in1a and in1b ) or + ( in2a ) or + ( in3a ) ; + return result ; + end ao_2x2x1x1 ; + + function ao_2x2x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a and in0b ) or + ( in1a and in1b ) or + ( in2a ) or + ( in3a ) ; + return result ; + end ao_2x2x1x1 ; + + function gate_aoi_2x2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 and in0 ) or + ( gate1 and in1 ) or + ( gate2 ) or + ( gate3 ) ) ; + return result ; + end gate_aoi_2x2x1x1 ; + + function gate_aoi_2x2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not( ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( ( 0 to in1'length-1 => gate1 ) and in1 ) or + ( 0 to in0'length-1 => gate2 ) or + ( 0 to in0'length-1 => gate3 ) ) ; + return result ; + end gate_aoi_2x2x1x1 ; + + function aoi_2x2x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a and in0b ) or + ( in1a and in1b ) or + ( in2a ) or + ( in3a ) ) ; + return result ; + end aoi_2x2x1x1 ; + + function aoi_2x2x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a and in0b ) or + ( in1a and in1b ) or + ( in2a ) or + ( in3a ) ) ; + return result ; + end aoi_2x2x1x1 ; + + function gate_oa_2x2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 or in0 ) and + ( gate1 or in1 ) and + ( gate2 ) and + ( gate3 ) ; + return result ; + end gate_oa_2x2x1x1 ; + + function gate_oa_2x2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) or in0 ) and + ( ( 0 to in1'length-1 => gate1 ) or in1 ) and + ( 0 to in0'length-1 => gate2 ) and + ( 0 to in0'length-1 => gate3 ) ; + return result ; + end gate_oa_2x2x1x1 ; + + function oa_2x2x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a or in0b ) and + ( in1a or in1b ) and + ( in2a ) and + ( in3a ) ; + return result ; + end oa_2x2x1x1 ; + + function oa_2x2x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a or in0b ) and + ( in1a or in1b ) and + ( in2a ) and + ( in3a ) ; + return result ; + end oa_2x2x1x1 ; + + function gate_oai_2x2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 or in0 ) and + ( gate1 or in1 ) and + ( gate2 ) and + ( gate3 ) ) ; + return result ; + end gate_oai_2x2x1x1 ; + + function gate_oai_2x2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not( ( ( 0 to in0'length-1 => gate0 ) or in0 ) and + ( ( 0 to in1'length-1 => gate1 ) or in1 ) and + ( 0 to in0'length-1 => gate2 ) and + ( 0 to in0'length-1 => gate3 ) ) ; + return result ; + end gate_oai_2x2x1x1 ; + + function oai_2x2x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a or in0b ) and + ( in1a or in1b ) and + ( in2a ) and + ( in3a ) ) ; + return result ; + end oai_2x2x1x1 ; + + function oai_2x2x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a or in0b ) and + ( in1a or in1b ) and + ( in2a ) and + ( in3a ) ) ; + return result ; + end oai_2x2x1x1 ; + + function gate_ao_2x2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 and in0 ) or + ( gate1 and in1 ) or + ( gate2 and in2 ) or + ( gate3 ) ; + return result ; + end gate_ao_2x2x2x1 ; + + function gate_ao_2x2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( ( 0 to in1'length-1 => gate1 ) and in1 ) or + ( ( 0 to in2'length-1 => gate2 ) and in2 ) or + ( 0 to in0'length-1 => gate3 ) ; + return result ; + end gate_ao_2x2x2x1 ; + + function ao_2x2x2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a and in0b ) or + ( in1a and in1b ) or + ( in2a and in2b ) or + ( in3a ) ; + return result ; + end ao_2x2x2x1 ; + + function ao_2x2x2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a and in0b ) or + ( in1a and in1b ) or + ( in2a and in2b ) or + ( in3a ) ; + return result ; + end ao_2x2x2x1 ; + + function gate_aoi_2x2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 and in0 ) or + ( gate1 and in1 ) or + ( gate2 and in2 ) or + ( gate3 ) ); + return result ; + end gate_aoi_2x2x2x1 ; + + function gate_aoi_2x2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not( ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( ( 0 to in1'length-1 => gate1 ) and in1 ) or + ( ( 0 to in2'length-1 => gate2 ) and in2 ) or + ( 0 to in0'length-1 => gate3 ) ); + return result ; + end gate_aoi_2x2x2x1 ; + + function aoi_2x2x2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a and in0b ) or + ( in1a and in1b ) or + ( in2a and in2b ) or + ( in3a ) ) ; + return result ; + end aoi_2x2x2x1 ; + + function aoi_2x2x2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a and in0b ) or + ( in1a and in1b ) or + ( in2a and in2b ) or + ( in3a ) ) ; + return result ; + end aoi_2x2x2x1 ; + + function gate_oa_2x2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 or in0 ) and + ( gate1 or in1 ) and + ( gate2 or in2 ) and + ( gate3 ) ; + return result ; + end gate_oa_2x2x2x1 ; + + function gate_oa_2x2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) or in0 ) and + ( ( 0 to in1'length-1 => gate1 ) or in1 ) and + ( ( 0 to in2'length-1 => gate2 ) or in2 ) and + ( 0 to in0'length-1 => gate3 ) ; + return result ; + end gate_oa_2x2x2x1 ; + + function oa_2x2x2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a or in0b ) and + ( in1a or in1b ) and + ( in2a or in2b ) and + ( in3a ) ; + return result ; + end oa_2x2x2x1 ; + + function oa_2x2x2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a or in0b ) and + ( in1a or in1b ) and + ( in2a or in2b ) and + ( in3a ) ; + return result ; + end oa_2x2x2x1 ; + + function gate_oai_2x2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 or in0 ) and + ( gate1 or in1 ) and + ( gate2 or in2 ) and + ( gate3 ) ) ; + return result ; + end gate_oai_2x2x2x1 ; + + function gate_oai_2x2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not( ( ( 0 to in0'length-1 => gate0 ) or in0 ) and + ( ( 0 to in1'length-1 => gate1 ) or in1 ) and + ( ( 0 to in2'length-1 => gate2 ) or in2 ) and + ( 0 to in0'length-1 => gate3 ) ) ; + return result ; + end gate_oai_2x2x2x1 ; + + function oai_2x2x2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a or in0b ) and + ( in1a or in1b ) and + ( in2a or in2b ) and + ( in3a ) ) ; + return result ; + end oai_2x2x2x1 ; + + function oai_2x2x2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a or in0b ) and + ( in1a or in1b ) and + ( in2a or in2b ) and + ( in3a ) ) ; + return result ; + end oai_2x2x2x1 ; + + function gate_ao_2x2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 and in0 ) or + ( gate1 and in1 ) or + ( gate2 and in2 ) or + ( gate3 and in3 ) ; + return result ; + end gate_ao_2x2x2x2 ; + + function gate_ao_2x2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( ( 0 to in1'length-1 => gate1 ) and in1 ) or + ( ( 0 to in2'length-1 => gate2 ) and in2 ) or + ( ( 0 to in3'length-1 => gate3 ) and in3 ) ; + return result ; + end gate_ao_2x2x2x2 ; + + function ao_2x2x2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic ; + in3a : std_ulogic ; + in3b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a and in0b ) or + ( in1a and in1b ) or + ( in2a and in2b ) or + ( in3a and in3b ) ; + return result ; + end ao_2x2x2x2 ; + + function ao_2x2x2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector ; + in3a : std_ulogic_vector ; + in3b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a and in0b ) or + ( in1a and in1b ) or + ( in2a and in2b ) or + ( in3a and in3b ) ; + return result ; + end ao_2x2x2x2 ; + + function gate_aoi_2x2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 and in0 ) or + ( gate1 and in1 ) or + ( gate2 and in2 ) or + ( gate3 and in3 ) ) ; + return result ; + end gate_aoi_2x2x2x2 ; + + function gate_aoi_2x2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of BLOCK_DATA : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not( ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( ( 0 to in1'length-1 => gate1 ) and in1 ) or + ( ( 0 to in2'length-1 => gate2 ) and in2 ) or + ( ( 0 to in3'length-1 => gate3 ) and in3 ) ) ; + return result ; + end gate_aoi_2x2x2x2 ; + + function aoi_2x2x2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic ; + in3a : std_ulogic ; + in3b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a and in0b ) or + ( in1a and in1b ) or + ( in2a and in2b ) or + ( in3a and in3b ) ) ; + return result ; + end aoi_2x2x2x2 ; + + function aoi_2x2x2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector ; + in3a : std_ulogic_vector ; + in3b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a and in0b ) or + ( in1a and in1b ) or + ( in2a and in2b ) or + ( in3a and in3b ) ) ; + return result ; + end aoi_2x2x2x2 ; + + function gate_oa_2x2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 or in0 ) and + ( gate1 or in1 ) and + ( gate2 or in2 ) and + ( gate3 or in3 ) ; + return result ; + end gate_oa_2x2x2x2 ; + + function gate_oa_2x2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) or in0 ) and + ( ( 0 to in1'length-1 => gate1 ) or in1 ) and + ( ( 0 to in2'length-1 => gate2 ) or in2 ) and + ( ( 0 to in3'length-1 => gate3 ) or in3 ) ; + return result ; + end gate_oa_2x2x2x2 ; + + function oa_2x2x2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic ; + in3a : std_ulogic ; + in3b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a or in0b ) and + ( in1a or in1b ) and + ( in2a or in2b ) and + ( in3a or in3b ) ; + return result ; + end oa_2x2x2x2 ; + + function oa_2x2x2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector ; + in3a : std_ulogic_vector ; + in3b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a or in0b ) and + ( in1a or in1b ) and + ( in2a or in2b ) and + ( in3a or in3b ) ; + return result ; + end oa_2x2x2x2 ; + + function gate_oai_2x2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 or in0 ) and + ( gate1 or in1 ) and + ( gate2 or in2 ) and + ( gate3 or in3 ) ) ; + return result ; + end gate_oai_2x2x2x2 ; + + function gate_oai_2x2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not( ( ( 0 to in0'length-1 => gate0 ) or in0 ) and + ( ( 0 to in1'length-1 => gate1 ) or in1 ) and + ( ( 0 to in2'length-1 => gate2 ) or in2 ) and + ( ( 0 to in3'length-1 => gate3 ) or in3 ) ) ; + return result ; + end gate_oai_2x2x2x2 ; + + function oai_2x2x2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic ; + in3a : std_ulogic ; + in3b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a or in0b ) and + ( in1a or in1b ) and + ( in2a or in2b ) and + ( in3a or in3b ) ) ; + return result ; + end oai_2x2x2x2 ; + + function oai_2x2x2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector ; + in3a : std_ulogic_vector ; + in3b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a or in0b ) and + ( in1a or in1b ) and + ( in2a or in2b ) and + ( in3a or in3b ) ) ; + return result ; + end oai_2x2x2x2 ; + + -- ============================================================= + -- 3 input Port AO/OA Gates + -- ============================================================= + + function gate_ao_3x1 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 and in0a and in0b) or + ( gate1 ) ; + return result ; + end gate_ao_3x1 ; + + function gate_ao_3x1 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( ( 0 to in0a'length-1 => gate0 ) and in0a and in0b) or + ( 0 to in0a'length-1 => gate1 ) ; + return result ; + end gate_ao_3x1 ; + + function ao_3x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a and in0b and in0c ) or + ( in1a ) ; + return result ; + end ao_3x1 ; + + function ao_3x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector( 0 to in0a'length-1 ) ; + begin + result := ( in0a and in0b and in0c ) or + ( in1a ) ; + return result ; + end ao_3x1 ; + + function gate_aoi_3x1 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 and in0a and in0b) or + ( gate1 ) ) ; + return result ; + end gate_aoi_3x1 ; + + function gate_aoi_3x1 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( ( 0 to in0a'length-1 => gate0 ) and in0a and in0b) or + ( 0 to in0a'length-1 => gate1 ) ) ; + return result ; + end gate_aoi_3x1 ; + + function aoi_3x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a and in0b and in0c ) or + ( in1a ) ); + return result ; + end aoi_3x1 ; + + function aoi_3x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a and in0b and in0c ) or + ( in1a ) ); + return result ; + end aoi_3x1 ; + + function gate_oa_3x1 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 or in0a or in0b ) and + ( gate1 ) ; + return result ; + end gate_oa_3x1 ; + + function gate_oa_3x1 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( ( 0 to in0a'length-1 => gate0 ) or in0a or in0b ) and + ( 0 to in0a'length-1 => gate1 ) ; + return result ; + end gate_oa_3x1 ; + + function oa_3x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a or in0b or in0c ) and + ( in1a ) ; + return result ; + end oa_3x1 ; + + function oa_3x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a or in0b or in0c ) and + ( in1a ) ; + return result ; + end oa_3x1 ; + + function gate_oai_3x1 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 or in0a or in0b ) and + ( gate1 ) ) ; + return result ; + end gate_oai_3x1 ; + + function gate_oai_3x1 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( ( 0 to in0a'length-1 => gate0 ) or in0a or in0b ) and + ( 0 to in0a'length-1 => gate1 ) ) ; + return result ; + end gate_oai_3x1 ; + + function oai_3x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a or in0b or in0c ) and + ( in1a ) ); + return result ; + end oai_3x1 ; + + function oai_3x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a or in0b or in0c ) and + ( in1a ) ); + return result ; + end oai_3x1 ; + + function gate_ao_3x2 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 and in0a and in0b ) or + ( gate1 and in1a ) ; + return result ; + end gate_ao_3x2 ; + + function gate_ao_3x2 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( ( 0 to in0a'length-1 => gate0 ) and in0a and in0b ) or + ( ( 0 to in1a'length-1 => gate1 ) and in1a ) ; + return result ; + end gate_ao_3x2 ; + + function ao_3x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a and in0b and in0c ) or + ( in1a and in1b ) ; + return result ; + end ao_3x2 ; + + function ao_3x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a and in0b and in0c ) or + ( in1a and in1b ) ; + return result ; + end ao_3x2 ; + + function gate_aoi_3x2 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 and in0a and in0b ) or + ( gate1 and in1a ) ) ; + return result ; + end gate_aoi_3x2 ; + + function gate_aoi_3x2 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( ( 0 to in0a'length-1 => gate0 ) and in0a and in0b ) or + ( ( 0 to in1a'length-1 => gate1 ) and in1a ) ) ; + return result ; + end gate_aoi_3x2 ; + + function aoi_3x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a and in0b and in0c ) or + ( in1a and in1b ) ) ; + return result ; + end aoi_3x2 ; + + function aoi_3x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a and in0b and in0c ) or + ( in1a and in1b ) ) ; + return result ; + end aoi_3x2 ; + + function gate_oa_3x2 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 or in0a or in0b ) and + ( gate1 or in1a ) ; + return result ; + end gate_oa_3x2 ; + + function gate_oa_3x2 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( ( 0 to in0a'length-1 => gate0 ) or in0a or in0b ) and + ( ( 0 to in1a'length-1 => gate1 ) or in1a ) ; + return result ; + end gate_oa_3x2 ; + + function oa_3x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a or in0b or in0c ) and + ( in1a or in1b ) ; + return result ; + end oa_3x2 ; + + function oa_3x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a or in0b or in0c ) and + ( in1a or in1b ) ; + return result ; + end oa_3x2 ; + + function gate_oai_3x2 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 or in0a or in0b ) and + ( gate1 or in1a ) ); + return result ; + end gate_oai_3x2 ; + + function gate_oai_3x2 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( ( 0 to in0a'length-1 => gate0 ) or in0a or in0b ) and + ( ( 0 to in1a'length-1 => gate1 ) or in1a ) ); + return result ; + end gate_oai_3x2 ; + + function oai_3x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a or in0b or in0c ) and + ( in1a or in1b ) ); + return result ; + end oai_3x2 ; + + function oai_3x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a or in0b or in0c ) and + ( in1a or in1b ) ); + return result ; + end oai_3x2 ; + + function gate_ao_3x3 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 and in0a and in0b ) or + ( gate1 and in1a and in1b ) ; + return result ; + end gate_ao_3x3 ; + + function gate_ao_3x3 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( ( 0 to in0a'length-1 => gate0 ) and in0a and in0b ) or + ( ( 0 to in1a'length-1 => gate1 ) and in1a and in1b ) ; + return result ; + end gate_ao_3x3 ; + + function ao_3x3 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a and in0b and in0c ) or + ( in1a and in1b and in1c ) ; + return result ; + end ao_3x3 ; + + function ao_3x3 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a and in0b and in0c ) or + ( in1a and in1b and in1c ) ; + return result ; + end ao_3x3 ; + + function gate_aoi_3x3 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 and in0a and in0b ) or + ( gate1 and in1a and in1b ) ) ; + return result ; + end gate_aoi_3x3 ; + + function gate_aoi_3x3 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( ( 0 to in0a'length => gate0 ) and in0a and in0b ) or + ( ( 0 to in1a'length => gate1 ) and in1a and in1b ) ) ; + return result ; + end gate_aoi_3x3 ; + + function aoi_3x3 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a and in0b and in0c ) or + ( in1a and in1b and in1c ) ); + return result ; + end aoi_3x3 ; + + function aoi_3x3 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a and in0b and in0c ) or + ( in1a and in1b and in1c ) ); + return result ; + end aoi_3x3 ; + + function gate_oa_3x3 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 or in0a or in0b ) and + ( gate1 or in1a or in1b ) ; + return result ; + end gate_oa_3x3 ; + + function gate_oa_3x3 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( ( 0 to in0a'length-1 => gate0 ) or in0a or in0b ) and + ( ( 0 to in1a'length-1 => gate1 ) or in1a or in1b ) ; + return result ; + end gate_oa_3x3 ; + + function oa_3x3 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a or in0b or in0c ) and + ( in1a or in1b or in1c ) ; + return result ; + end oa_3x3 ; + + function oa_3x3 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a or in0b or in0c ) and + ( in1a or in1b or in1c ) ; + return result ; + end oa_3x3 ; + + function gate_oai_3x3 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 or in0a or in0b ) and + ( gate1 or in1a or in1b ) ) ; + return result ; + end gate_oai_3x3 ; + + function gate_oai_3x3 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( ( 0 to in0a'length-1 => gate0 ) or in0a or in0b ) and + ( ( 0 to in1a'length-1 => gate1 ) or in1a or in1b ) ) ; + return result ; + end gate_oai_3x3 ; + + function oai_3x3 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a or in0b or in0c ) and + ( in1a or in1b or in1c ) ) ; + return result ; + end oai_3x3 ; + + function oai_3x3 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a or in0b or in0c ) and + ( in1a or in1b or in1c ) ) ; + return result ; + end oai_3x3 ; + + -- ============================================================= + -- 4 input Port AO/OA Gates + -- ============================================================= + + function gate_ao_4x1 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 and in0a and in0b and in0c ) or + ( gate1 ) ; + return result ; + end gate_ao_4x1 ; + + function gate_ao_4x1 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( ( 0 to in0a'length-1 => gate0 ) and in0a and in0b and in0c ) or + ( 0 to in0a'length-1 => gate1 ) ; + return result ; + end gate_ao_4x1 ; + + function ao_4x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a and in0b and in0c and in0d ) or + ( in1a ) ; + return result ; + end ao_4x1 ; + + function ao_4x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a and in0b and in0c and in0d ) or + ( in1a ) ; + return result ; + end ao_4x1 ; + + function gate_aoi_4x1 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 and in0a and in0b and in0c ) or + ( gate1 ) ); + return result ; + end gate_aoi_4x1 ; + + function gate_aoi_4x1 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( ( 0 to in0a'length-1 => gate0 ) and in0a and in0b and in0c ) or + ( 0 to in0a'length-1 => gate1 ) ) ; + return result ; + end gate_aoi_4x1 ; + + function aoi_4x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a and in0b and in0c and in0d ) or + ( in1a ) ) ; + return result ; + end aoi_4x1 ; + + function aoi_4x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a and in0b and in0c and in0d ) or + ( in1a ) ) ; + return result ; + end aoi_4x1 ; + + function gate_oa_4x1 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 or in0a or in0b or in0c ) and + ( gate1 ) ; + return result ; + end gate_oa_4x1 ; + + function gate_oa_4x1 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( ( 0 to in0a'length-1 => gate0 ) or in0a or in0b or in0c ) and + ( 0 to in0a'length-1 => gate1 ) ; + return result ; + end gate_oa_4x1 ; + + function oa_4x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a or in0b or in0c or in0d ) and + ( in1a ) ; + return result ; + end oa_4x1 ; + + function oa_4x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a or in0b or in0c or in0d ) and + ( in1a ) ; + return result ; + end oa_4x1 ; + + function gate_oai_4x1 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 or in0a or in0b or in0c ) and + ( gate1 ) ) ; + return result ; + end gate_oai_4x1 ; + + function gate_oai_4x1 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( ( 0 to in0a'length-1 => gate0 ) or in0a or in0b or in0c ) and + ( 0 to in0a'length-1 => gate1 ) ) ; + return result ; + end gate_oai_4x1 ; + + function oai_4x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a or in0b or in0c or in0d ) and + ( in1a ) ) ; + return result ; + end oai_4x1 ; + + function oai_4x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a or in0b or in0c or in0d ) and + ( in1a ) ) ; + return result ; + end oai_4x1 ; + + function gate_ao_4x2 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 and in0a and in0b and in0c ) or + ( gate1 and in1a ) ; + return result ; + end gate_ao_4x2 ; + + function gate_ao_4x2 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( ( 0 to in0a'length-1 => gate0 ) and in0a and in0b and in0c ) or + ( ( 0 to in1a'length-1 => gate1 ) and in1a ) ; + return result ; + end gate_ao_4x2 ; + + function ao_4x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a and in0b and in0c and in0d ) or + ( in1a and in1b ) ; + return result ; + end ao_4x2 ; + + function ao_4x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a and in0b and in0c and in0d ) or + ( in1a and in1b ) ; + return result ; + end ao_4x2 ; + + function gate_aoi_4x2 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 and in0a and in0b and in0c ) or + ( gate1 and in1a ) ) ; + return result ; + end gate_aoi_4x2 ; + + function gate_aoi_4x2 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( ( 0 to in0a'length-1 => gate0 ) and in0a and in0b and in0c ) or + ( ( 0 to in1a'length-1 => gate1 ) and in1a ) ) ; + return result ; + end gate_aoi_4x2 ; + + function aoi_4x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a and in0b and in0c and in0d ) or + ( in1a and in1b ) ) ; + return result ; + end aoi_4x2 ; + + function aoi_4x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a and in0b and in0c and in0d ) or + ( in1a and in1b ) ) ; + return result ; + end aoi_4x2 ; + + function gate_oa_4x2 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 or in0a or in0b or in0c ) and + ( gate1 or in1a ) ; + return result ; + end gate_oa_4x2 ; + + function gate_oa_4x2 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( ( 0 to in0a'length-1 => gate0 ) or in0a or in0b or in0c ) and + ( ( 0 to in1a'length-1 => gate1 ) or in1a ) ; + return result ; + end gate_oa_4x2 ; + + function oa_4x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a or in0b or in0c or in0d ) and + ( in1a or in1b ) ; + return result ; + end oa_4x2 ; + + function oa_4x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a or in0b or in0c or in0d ) and + ( in1a or in1b ) ; + return result ; + end oa_4x2 ; + + function gate_oai_4x2 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 or in0a or in0b or in0c ) and + ( gate1 or in1a ) ); + return result ; + end gate_oai_4x2 ; + + function gate_oai_4x2 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( ( 0 to in0a'length-1 => gate0 ) or in0a or in0b or in0c ) and + ( ( 0 to in1a'length-1 => gate1 ) or in1a ) ); + return result ; + end gate_oai_4x2 ; + + function oai_4x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a or in0b or in0c or in0d ) and + ( in1a or in1b ) ) ; + return result ; + end oai_4x2 ; + + function oai_4x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a or in0b or in0c or in0d ) and + ( in1a or in1b ) ) ; + return result ; + end oai_4x2 ; + + function gate_ao_4x3 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 and in0a and in0b and in0c ) or + ( gate1 and in1a and in1b ) ; + return result ; + end gate_ao_4x3 ; + + function gate_ao_4x3 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( ( 0 to in0a'length-1 => gate0 ) and in0a and in0b and in0c ) or + ( ( 0 to in1a'length-1 => gate1 ) and in1a and in1b ) ; + return result ; + end gate_ao_4x3 ; + + function ao_4x3 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a and in0b and in0c and in0d ) or + ( in1a and in1b and in1c ) ; + return result ; + end ao_4x3 ; + + function ao_4x3 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a and in0b and in0c and in0d ) or + ( in1a and in1b and in1c ) ; + return result ; + end ao_4x3 ; + + function gate_aoi_4x3 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 and in0a and in0b and in0c ) or + ( gate1 and in1a and in1b ) ) ; + return result ; + end gate_aoi_4x3 ; + + function gate_aoi_4x3 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( ( 0 to in0a'length-1 => gate0 ) and in0a and in0b and in0c ) or + ( ( 0 to in1a'length-1 => gate1 ) and in1a and in1b ) ) ; + return result ; + end gate_aoi_4x3 ; + + function aoi_4x3 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a and in0b and in0c and in0d ) or + ( in1a and in1b and in1c ) ) ; + return result ; + end aoi_4x3 ; + + function aoi_4x3 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a and in0b and in0c and in0d ) or + ( in1a and in1b and in1c ) ) ; + return result ; + end aoi_4x3 ; + + function gate_oa_4x3 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 or in0a or in0b or in0c ) and + ( gate1 or in1a or in1b ) ; + return result ; + end gate_oa_4x3 ; + + function gate_oa_4x3 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( ( 0 to in0a'length-1 => gate0 ) or in0a or in0b or in0c ) and + ( ( 0 to in1a'length-1 => gate1 ) or in1a or in1b ) ; + return result ; + end gate_oa_4x3 ; + + function oa_4x3 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a or in0b or in0c or in0d ) and + ( in1a or in1b or in1c ) ; + return result ; + end oa_4x3 ; + + function oa_4x3 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a or in0b or in0c or in0d ) and + ( in1a or in1b or in1c ) ; + return result ; + end oa_4x3 ; + + function gate_oai_4x3 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 or in0a or in0b or in0c ) and + ( gate1 or in1a or in1b ) ) ; + return result ; + end gate_oai_4x3 ; + + function gate_oai_4x3 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( ( 0 to in0a'length-1 => gate0 ) or in0a or in0b or in0c ) and + ( ( 0 to in1a'length-1 => gate1 ) or in1a or in1b ) ) ; + return result ; + end gate_oai_4x3 ; + + function oai_4x3 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a or in0b or in0c or in0d ) and + ( in1a or in1b or in1c ) ) ; + return result ; + end oai_4x3 ; + + function oai_4x3 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a or in0b or in0c or in0d ) and + ( in1a or in1b or in1c ) ) ; + return result ; + end oai_4x3 ; + + function gate_ao_4x4 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 and in0a and in0b and in0c ) or + ( gate1 and in1a and in1b and in1c ) ; + return result ; + end gate_ao_4x4 ; + + function gate_ao_4x4 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( ( 0 to in0a'length-1 => gate0 ) and in0a and in0b and in0c ) or + ( ( 0 to in1a'length-1 => gate1 ) and in1a and in1b and in1c ) ; + return result ; + end gate_ao_4x4 ; + + function ao_4x4 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic ; + in1d : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a and in0b and in0c and in0d ) or + ( in1a and in1b and in1c and in1d ) ; + return result ; + end ao_4x4 ; + + function ao_4x4 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector ; + in1d : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a and in0b and in0c and in0d ) or + ( in1a and in1b and in1c and in1d ) ; + return result ; + end ao_4x4 ; + + function gate_aoi_4x4 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 and in0a and in0b and in0c ) or + ( gate1 and in1a and in1b and in1c ) ) ; + return result ; + end gate_aoi_4x4 ; + + function gate_aoi_4x4 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( ( 0 to in0a'length-1 => gate0 ) and in0a and in0b and in0c ) or + ( ( 0 to in1a'length-1 => gate1 ) and in1a and in1b and in1c ) ) ; + return result ; + end gate_aoi_4x4 ; + + function aoi_4x4 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic ; + in1d : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a and in0b and in0c and in0d ) or + ( in1a and in1b and in1c and in1d ) ) ; + return result ; + end aoi_4x4 ; + + function aoi_4x4 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector ; + in1d : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a and in0b and in0c and in0d ) or + ( in1a and in1b and in1c and in1d ) ) ; + return result ; + end aoi_4x4 ; + + function gate_oa_4x4 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 or in0a or in0b or in0c ) and + ( gate1 or in1a or in1b or in1c ) ; + return result ; + end gate_oa_4x4 ; + + function gate_oa_4x4 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( ( 0 to in0a'length-1 => gate0 ) or in0a or in0b or in0c ) and + ( ( 0 to in1a'length-1 => gate1 ) or in1a or in1b or in1c ) ; + return result ; + end gate_oa_4x4 ; + + function oa_4x4 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic ; + in1d : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a or in0b or in0c or in0d ) and + ( in1a or in1b or in1c or in1d ) ; + return result ; + end oa_4x4 ; + + function oa_4x4 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector ; + in1d : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a or in0b or in0c or in0d ) and + ( in1a or in1b or in1c or in1d ) ; + return result ; + end oa_4x4 ; + + function gate_oai_4x4 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 or in0a or in0b or in0c ) and + ( gate1 or in1a or in1b or in1c ) ) ; + return result ; + end gate_oai_4x4 ; + + function gate_oai_4x4 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( ( 0 to in0a'length-1 => gate0 ) or in0a or in0b or in0c ) and + ( ( 0 to in1a'length-1 => gate1 ) or in1a or in1b or in1c ) ) ; + return result ; + end gate_oai_4x4 ; + + function oai_4x4 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic ; + in1d : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a or in0b or in0c or in0d ) and + ( in1a or in1b or in1c or in1d ) ) ; + return result ; + end oai_4x4 ; + + function oai_4x4 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector ; + in1d : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a or in0b or in0c or in0d ) and + ( in1a or in1b or in1c or in1d ) ) ; + return result ; + end oai_4x4 ; + +end std_ulogic_ao_support; + diff --git a/rel/src/vhdl/ibm/std_ulogic_function_support.vhdl b/rel/src/vhdl/ibm/std_ulogic_function_support.vhdl new file mode 100644 index 0000000..cc7bb7f --- /dev/null +++ b/rel/src/vhdl/ibm/std_ulogic_function_support.vhdl @@ -0,0 +1,5181 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +--*************************************************************************** +-- Copyright 2020 International Business Machines +-- +-- Licensed under the Apache License, Version 2.0 (the “License”); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- The patent license granted to you in Section 3 of the License, as applied +-- to the “Work,” hereby includes implementations of the Work in physical form. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an “AS IS” BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- +--*************************************************************************** +library ibm,ieee ; +use ieee.std_logic_1164.all ; +use ibm.std_ulogic_support.all; + +package std_ulogic_function_support is + -- Subtypes used for constraining return values in package + subtype std_return_2 is std_ulogic_vector(0 to 1); + subtype std_return_4 is std_ulogic_vector(0 to 3); + subtype std_return_8 is std_ulogic_vector(0 to 7); + subtype std_return_16 is std_ulogic_vector(0 to 15); + subtype std_return_32 is std_ulogic_vector(0 to 31); + subtype std_return_64 is std_ulogic_vector(0 to 63); + -- Test Case Evaluation Attributes + -- These attributes are used to control the generation of TCE tests + -- within the VHDL code. + -- Valid on PORT, SIGNAL and LABEL . + + -- Used to turn task model generation on or off. The attribute is applied + -- to a label. If on a block it turns off generation for the whole block. + -- If on a statement it is for that statement alone. + -- The string specifies which task statement alone. + -- attribute TCE_ON of : label is "T,LTP,STP,DLTP,LST,STC,ASSRT,CMBN | ALL" ; + attribute tce_on : string; + attribute tce_off : string; + attribute tce_last : string; + attribute tce_reset : string; + attribute tce_all_off : string; + attribute tce_ignore : string; + -- The string specifies which task statement alone. + attribute tce_assertion : string; + attribute tce_combination : string; + attribute tce_seqcond : string; + + -- Global Signals + -- Synopsys translate_off + signal audit_bit_dump : std_ulogic ; + signal assertion_summary : boolean ; + signal assertion_clock : std_ulogic ; + -- Synopsys translate_on + + -- Synopsys translate_off + component assertion + generic( counted : boolean := false; + Delay : natural := 0; + Duration : natural := 0); + port( + assert_in : in std_ulogic ; + sample : in std_ulogic ; + assert_out : out std_ulogic + ); + end component; + -- Synopsys translate_on + + -- Function Declarations and Attributes + -- Gate Function + function gate + (in0 : std_ulogic_vector; + cond : std_ulogic ) + return std_ulogic_vector ; + -- Synopsys translate_off + attribute btr_name of gate : function is "AND" ; + attribute recursive_synthesis of gate : function is true ; + attribute pin_bit_information of gate : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 3 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + -- Dot Functions + function dot_and + (in0 : std_ulogic_vector ) + return std_ulogic ; + -- Synopsys translate_off + attribute btr_name of dot_and : function is "VHDL-DOTA" ; + attribute recursive_synthesis of dot_and : function is true ; + attribute pin_bit_information of dot_and : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); + -- Synopsys translate_on + + function dot_or + (in0 : std_ulogic_vector ) + return std_ulogic ; + -- synopsys translate_off + attribute btr_name of dot_or : function is "VHDL-DOTO" ; + attribute recursive_synthesis of dot_or : function is true ; + attribute pin_bit_information of dot_or : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); + -- Synopsys translate_on + + function clock_tree_dot + (in0 : std_ulogic_vector ) + return std_ulogic ; + + function clock_tree_dot + (in0 : bit_vector ) + return bit ; + -- Synopsys translate_off + attribute btr_name of clock_tree_dot : function is "VHDL-CDOT" ; + attribute recursive_synthesis of clock_tree_dot : function is true ; + attribute pin_bit_information of clock_tree_dot : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); + -- Synopsys translate_on + + -- Generic Terminator + procedure terminator + (in0 : in std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ); + + procedure terminator + (in0 : in std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ); + -- synopsys translate_off + attribute btr_name of terminator : procedure is "TERMINATOR"; + attribute recursive_synthesis of terminator : procedure is true ; + attribute pin_bit_information of terminator : procedure is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," ")); + -- Synopsys translate_on + + -- Generic Delay + function delay + (in0 : std_ulogic + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic ; + + function delay + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of delay : function is "IDENT" ; + attribute recursive_synthesis of delay : function is true ; + attribute block_data of delay : function is + "SUB_FUNC=/DELAY/LOGIC_STYLE=/DIRECT/" ; + attribute pin_bit_information of delay : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + -- Generic Buffer + function buff + (in0 : std_ulogic + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic ; + + function buff + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of buff : function is "IDENT" ; + attribute recursive_synthesis of buff : function is true ; + attribute block_data of buff : function is + "LOGIC_STYLE=/DIRECT/" ; + attribute pin_bit_information of buff : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + -- Invert single bit + function invert + (in0 : std_ulogic + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic ; + -- inverter vectored + function invert + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of invert : function is "NOT" ; + attribute recursive_synthesis of invert : function is true ; + attribute pin_bit_information of invert : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + -- Compare single bit + function compare + (in0 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic ; + -- compare multi-bit + function compare + (in0 : std_ulogic_vector; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic ; + -- synopsys translate_off + attribute btr_name of compare : function is "VHDL-COMPARE" ; + attribute recursive_synthesis of compare : function is true ; + attribute pin_bit_information of compare : function is + (1 => (" ","A0 ","INCR","PIN_BIT_SCALAR"), + 2 => (" ","M0 ","INCR","PIN_BIT_SCALAR"), + 3 => (" ","PASS "," "," "), + 4 => (" ","PASS "," "," "), + 5 => (" ","EQ ","SAME","PIN_BIT_SCALAR")); + -- Synopsys translate_on + + -- Parity Functions + -- General XOR_Tree Building Parity Function + function parity + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic ; + -- synopsys translate_off + attribute btr_name of parity : function is "XOR" ; + attribute recursive_synthesis of parity : function is true ; + attribute pin_bit_information of parity : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); + -- Synopsys translate_on + function parity_map + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic ; + + -- synopsys translate_off + attribute btr_name of parity_map : function is "XOR" ; + attribute recursive_synthesis of parity_map : function is true ; + attribute block_data of parity_map : function is + "LOGIC_STYLE=/DIRECT/" ; + attribute pin_bit_information of parity_map : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); + -- Synopsys translate_on + + -- Parity gneration/checking functions + function parity_gen_odd + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic ; + + -- synopsys translate_off + attribute btr_name of parity_gen_odd : function is "XNOR" ; + attribute recursive_synthesis of parity_gen_odd : function is true; + attribute pin_bit_information of parity_gen_odd : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); + -- Synopsys translate_on + + function parity_gen_even + (in0 : std_ulogic_vector + -- Synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- Synopsys translate_on + ) + return std_ulogic ; + -- Synopsys translate_off + attribute btr_name of parity_gen_even : function is "XOR" ; + attribute recursive_synthesis of parity_gen_even : function is true; + attribute pin_bit_information of parity_gen_even : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); + -- Synopsys translate_on + + function is_parity_odd + (in0 : std_ulogic_vector + -- Synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- Synopsys translate_on + ) + return std_ulogic ; + -- Synopsys translate_off + attribute btr_name of is_parity_odd : function is "XOR" ; + attribute recursive_synthesis of is_parity_odd : function is true; + attribute pin_bit_information of is_parity_odd : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); + -- Synopsys translate_on + + function is_parity_even + (in0 : std_ulogic_vector + -- Synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- Synopsys translate_on + ) + return std_ulogic ; + -- Synopsys translate_off + attribute btr_name of is_parity_even : function is "XNOR" ; + attribute recursive_synthesis of is_parity_even : function is true; + attribute pin_bit_information of is_parity_even : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); + -- Synopsys translate_on + + -- Full Adder + procedure full_add + (add_1 : in std_ulogic ; + add_2 : in std_ulogic ; + cryin : in std_ulogic ; + signal sum : out std_ulogic ; + signal carry : out std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ); + procedure full_add + (add_1 : in std_ulogic_vector ; + add_2 : in std_ulogic_vector ; + cryin : in std_ulogic_vector ; + signal sum : out std_ulogic_vector ; + signal carry : out std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ); + -- synopsys translate_off + attribute btr_name of full_add : procedure is "VHDL-FA"; + attribute recursive_synthesis of full_add : procedure is true ; + attribute pin_bit_information of full_add : procedure is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","CIN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","SUM ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","COUT ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," ")); + -- Synopsys translate_on + + -- Ripple Adder function + procedure ripple_adder + (add_1 : in std_ulogic_vector ; + add_2 : in std_ulogic_vector ; + signal sum : out std_ulogic_vector ; + signal carry : out std_ulogic ) ; + + procedure ripple_adder + (add_1 : in std_ulogic_vector ; + add_2 : in std_ulogic_vector ; + signal sum : out std_ulogic_vector ); + + -- Generic Tie Blocks + function tie_0 + -- synopsys translate_off + (btr : in string :="" + ;blkdata : in string :="" + ) + -- synopsys translate_on + return std_ulogic ; + -- synopsys translate_off + attribute btr_name of tie_0 : function is "VHDL-TIDN" ; + attribute recursive_synthesis of tie_0 : function is true ; + attribute block_data of tie_0 : function is + "LOGIC_STYLE=/DIRECT/" ; + attribute pin_bit_information of tie_0 : function is + (1 => (" ","PASS "," "," "), + 2 => (" ","PASS "," "," "), + 3 => (" ","ZERO ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function vector_tie_0 + (width : integer := 1 + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of vector_tie_0 : function is "VHDL-TIDN" ; + attribute recursive_synthesis of vector_tie_0 : function is true ; + attribute block_data of vector_tie_0 : function is + "LOGIC_STYLE=/DIRECT/" ; + attribute pin_bit_information of vector_tie_0 : function is + (1 => (" ","IGNR "," "," "), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","ZERO ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function tie_1 + -- synopsys translate_off + (btr : in string :="" + ;blkdata : in string :="" + ) + -- synopsys translate_on + return std_ulogic ; + -- synopsys translate_off + attribute btr_name of tie_1 : function is "VHDL-TIUP" ; + attribute recursive_synthesis of tie_1 : function is true ; + attribute block_data of tie_1 : function is + "LOGIC_STYLE=/DIRECT/" ; + attribute pin_bit_information of tie_1 : function is + (1 => (" ","PASS "," "," "), + 2 => (" ","PASS "," "," "), + 3 => (" ","ONE ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function vector_tie_1 + (width : integer := 1 + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of vector_tie_1 : function is "VHDL-TIUP" ; + attribute recursive_synthesis of vector_tie_1 : function is true ; + attribute block_data of vector_tie_1 : function is + "LOGIC_STYLE=/DIRECT/" ; + attribute pin_bit_information of vector_tie_1 : function is + (1 => (" ","IGNR "," "," "), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","ONE ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function reverse + (arg: std_ulogic_vector) + return std_ulogic_vector ; + + function and_reduce + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic ; + -- synopsys translate_off + attribute btr_name of and_reduce : function is "AND" ; + attribute recursive_synthesis of and_reduce : function is true ; + attribute pin_bit_information of and_reduce : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); + -- Synopsys translate_on + + function or_reduce + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic ; + -- synopsys translate_off + attribute btr_name of or_reduce : function is "OR" ; + attribute recursive_synthesis of or_reduce : function is true ; + attribute pin_bit_information of or_reduce : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); + -- Synopsys translate_on + + function nand_reduce + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic ; + -- synopsys translate_off + attribute btr_name of nand_reduce : function is "NAND" ; + attribute recursive_synthesis of nand_reduce : function is true ; + attribute pin_bit_information of nand_reduce : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); + -- Synopsys translate_on + + function nor_reduce + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic ; + -- synopsys translate_off + attribute btr_name of nor_reduce : function is "NOR" ; + attribute recursive_synthesis of nor_reduce : function is true ; + attribute pin_bit_information of nor_reduce : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); + -- Synopsys translate_on + + function xor_reduce + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic ; + -- synopsys translate_off + attribute btr_name of xor_reduce : function is "XOR" ; + attribute recursive_synthesis of xor_reduce : function is true ; + attribute pin_bit_information of xor_reduce : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); + -- Synopsys translate_on + + function xnor_reduce + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic ; + -- synopsys translate_off + attribute btr_name of xnor_reduce : function is "XNOR" ; + attribute recursive_synthesis of xnor_reduce : function is true ; + attribute pin_bit_information of xnor_reduce : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); + -- Synopsys translate_on + + -- Vector of gating bits gating a single vector of data bits + function gate_and + (gate : std_ulogic_vector; + in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + function gate_and + (gate : std_ulogic ; + in0 : std_ulogic + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic ; + function gate_and + (gate : std_ulogic ; + in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_and : function is "AND" ; + attribute recursive_synthesis of gate_and : function is true ; + attribute pin_bit_information of gate_and : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","PASS "," "," "), + 4 => (" ","PASS "," "," "), + 5 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function gate_or + (gate : std_ulogic_vector; + in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + function gate_or + (gate : std_ulogic ; + in0 : std_ulogic + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic ; + function gate_or + (gate : std_ulogic ; + in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_or : function is "OR" ; + attribute recursive_synthesis of gate_or : function is true ; + attribute pin_bit_information of gate_or : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","PASS "," "," "), + 4 => (" ","PASS "," "," "), + 5 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function gate_nand + (gate : std_ulogic_vector; + in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + function gate_nand + (gate : std_ulogic ; + in0 : std_ulogic + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic ; + function gate_nand + (gate : std_ulogic ; + in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_nand : function is "NAND" ; + attribute recursive_synthesis of gate_nand : function is true ; + attribute pin_bit_information of gate_nand : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","PASS "," "," "), + 4 => (" ","PASS "," "," "), + 5 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function gate_nor + (gate : std_ulogic_vector; + in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + function gate_nor + (gate : std_ulogic ; + in0 : std_ulogic + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic ; + function gate_nor + (gate : std_ulogic ; + in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_nor : function is "NOR" ; + attribute recursive_synthesis of gate_nor : function is true ; + attribute pin_bit_information of gate_nor : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","PASS "," "," "), + 4 => (" ","PASS "," "," "), + 5 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function gate_xor + (gate : std_ulogic ; + in0 : std_ulogic + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic ; + function gate_xor + (gate : std_ulogic ; + in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_xor : function is "XOR" ; + attribute recursive_synthesis of gate_xor : function is true ; + attribute pin_bit_information of gate_xor : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","PASS "," "," "), + 4 => (" ","PASS "," "," "), + 5 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function gate_xnor + (gate : std_ulogic ; + in0 : std_ulogic + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic ; + function gate_xnor + (gate : std_ulogic ; + in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_xnor : function is "XNOR" ; + attribute recursive_synthesis of gate_xnor : function is true ; + attribute pin_bit_information of gate_xnor : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","PASS "," "," "), + 4 => (" ","PASS "," "," "), + 5 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + -- Vectored primitive 2 input functions + -- Single bit case + -- Multiple vectors logically ed bitwise + function and_2 + (in0 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function and_2 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of and_2 : function is "AND" ; + attribute recursive_synthesis of and_2 : function is true ; + attribute pin_bit_information of and_2 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","PASS "," "," "), + 4 => (" ","PASS "," "," "), + 5 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function or_2 + (in0 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function or_2 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of or_2 : function is "OR" ; + attribute recursive_synthesis of or_2 : function is true ; + attribute pin_bit_information of or_2 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","PASS "," "," "), + 4 => (" ","PASS "," "," "), + 5 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function nand_2 + (in0 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function nand_2 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of nand_2 : function is "NAND" ; + attribute recursive_synthesis of nand_2 : function is true ; + attribute pin_bit_information of nand_2 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","PASS "," "," "), + 4 => (" ","PASS "," "," "), + 5 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function nor_2 + (in0 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function nor_2 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of nor_2 : function is "NOR" ; + attribute recursive_synthesis of nor_2 : function is true ; + attribute pin_bit_information of nor_2 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","PASS "," "," "), + 4 => (" ","PASS "," "," "), + 5 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function xor_2 + (in0 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function xor_2 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of xor_2 : function is "XOR" ; + attribute recursive_synthesis of xor_2 : function is true ; + attribute pin_bit_information of xor_2 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","PASS "," "," "), + 4 => (" ","PASS "," "," "), + 5 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function xnor_2 + (in0 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function xnor_2 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of xnor_2 : function is "XNOR" ; + attribute recursive_synthesis of xnor_2 : function is true ; + attribute pin_bit_information of xnor_2 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","PASS "," "," "), + 4 => (" ","PASS "," "," "), + 5 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + -- Vectored primitive 3 input functions + -- Single bit case + function and_3 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + -- multiple vectors logically ed bitwise + function and_3 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of and_3 : function is "AND" ; + attribute recursive_synthesis of and_3 : function is true ; + attribute pin_bit_information of and_3 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","PASS "," "," "), + 5 => (" ","PASS "," "," "), + 6 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function or_3 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function or_3 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of or_3 : function is "OR" ; + attribute recursive_synthesis of or_3 : function is true ; + attribute pin_bit_information of or_3 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","PASS "," "," "), + 5 => (" ","PASS "," "," "), + 6 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function nand_3 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function nand_3 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of nand_3 : function is "NAND" ; + attribute recursive_synthesis of nand_3 : function is true ; + attribute pin_bit_information of nand_3 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","PASS "," "," "), + 5 => (" ","PASS "," "," "), + 6 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function nor_3 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function nor_3 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of nor_3 : function is "NOR" ; + attribute recursive_synthesis of nor_3 : function is true ; + attribute pin_bit_information of nor_3 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","PASS "," "," "), + 5 => (" ","PASS "," "," "), + 6 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function xor_3 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function xor_3 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of xor_3 : function is "XOR" ; + attribute recursive_synthesis of xor_3 : function is true ; + attribute pin_bit_information of xor_3 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","PASS "," "," "), + 5 => (" ","PASS "," "," "), + 6 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function xnor_3 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function xnor_3 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of xnor_3 : function is "XNOR" ; + attribute recursive_synthesis of xnor_3 : function is true ; + attribute pin_bit_information of xnor_3 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","PASS "," "," "), + 5 => (" ","PASS "," "," "), + 6 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + -- Vectored primitive 4 input functions + -- Single bit case + function and_4 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function and_4 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of and_4 : function is "AND" ; + attribute recursive_synthesis of and_4 : function is true ; + attribute pin_bit_information of and_4 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function or_4 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function or_4 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of or_4 : function is "OR" ; + attribute recursive_synthesis of or_4 : function is true ; + attribute pin_bit_information of or_4 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function nand_4 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function nand_4 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of nand_4 : function is "NAND" ; + attribute recursive_synthesis of nand_4 : function is true ; + attribute pin_bit_information of nand_4 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function nor_4 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function nor_4 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of nor_4 : function is "NOR" ; + attribute recursive_synthesis of nor_4 : function is true ; + attribute pin_bit_information of nor_4 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + -- Vectored primitive 5 input functions + -- Single bit case + -- Multiple vectors logically ed bitwise + function and_5 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function and_5 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of and_5 : function is "AND" ; + attribute recursive_synthesis of and_5 : function is true ; + attribute pin_bit_information of and_5 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function or_5 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function or_5 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of or_5 : function is "OR" ; + attribute recursive_synthesis of or_5 : function is true ; + attribute pin_bit_information of or_5 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function nand_5 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function nand_5 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of nand_5 : function is "NAND" ; + attribute recursive_synthesis of nand_5 : function is true ; + attribute pin_bit_information of nand_5 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function nor_5 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function nor_5 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of nor_5 : function is "NOR" ; + attribute recursive_synthesis of nor_5 : function is true ; + attribute pin_bit_information of nor_5 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + -- Vectored primitive 6 input functions + -- Single bit case + function and_6 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function and_6 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of and_6 : function is "AND" ; + attribute recursive_synthesis of and_6 : function is true ; + attribute pin_bit_information of and_6 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function or_6 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function or_6 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of or_6 : function is "OR" ; + attribute recursive_synthesis of or_6 : function is true ; + attribute pin_bit_information of or_6 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function nand_6 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function nand_6 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of nand_6 : function is "NAND" ; + attribute recursive_synthesis of nand_6 : function is true ; + attribute pin_bit_information of nand_6 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function nor_6 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function nor_6 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of nor_6 : function is "NOR" ; + attribute recursive_synthesis of nor_6 : function is true ; + attribute pin_bit_information of nor_6 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + -- Vectored primitive 7 input functions + -- Single bit case + -- Multiple vectors logically ed bitwise + function and_7 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic ; + in6 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function and_7 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector ; + in6 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of and_7 : function is "AND" ; + attribute recursive_synthesis of and_7 : function is true ; + attribute pin_bit_information of and_7 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","PASS "," "," "), + 9 => (" ","PASS "," "," "), + 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function or_7 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic ; + in6 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function or_7 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector ; + in6 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of or_7 : function is "OR" ; + attribute recursive_synthesis of or_7 : function is true ; + attribute pin_bit_information of or_7 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","PASS "," "," "), + 9 => (" ","PASS "," "," "), + 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function nand_7 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic ; + in6 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function nand_7 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector ; + in6 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of nand_7 : function is "NAND" ; + attribute recursive_synthesis of nand_7 : function is true ; + attribute pin_bit_information of nand_7 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","PASS "," "," "), + 9 => (" ","PASS "," "," "), + 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function nor_7 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic ; + in6 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function nor_7 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector ; + in6 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of nor_7 : function is "NOR" ; + attribute recursive_synthesis of nor_7 : function is true ; + attribute pin_bit_information of nor_7 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","PASS "," "," "), + 9 => (" ","PASS "," "," "), + 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + -- Vectored primitive 8 input functions + -- Single bit case + -- Multiple vectors logically ed bitwise + function and_8 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic ; + in6 : std_ulogic ; + in7 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function and_8 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector ; + in6 : std_ulogic_vector ; + in7 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of and_8 : function is "AND" ; + attribute recursive_synthesis of and_8 : function is true ; + attribute pin_bit_information of and_8 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function or_8 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic ; + in6 : std_ulogic ; + in7 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function or_8 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector ; + in6 : std_ulogic_vector ; + in7 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of or_8 : function is "OR" ; + attribute recursive_synthesis of or_8 : function is true ; + attribute pin_bit_information of or_8 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function nand_8 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic ; + in6 : std_ulogic ; + in7 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function nand_8 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector ; + in6 : std_ulogic_vector ; + in7 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of nand_8 : function is "NAND" ; + attribute recursive_synthesis of nand_8 : function is true ; + attribute pin_bit_information of nand_8 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function nor_8 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic ; + in6 : std_ulogic ; + in7 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function nor_8 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector ; + in6 : std_ulogic_vector ; + in7 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of nor_8 : function is "NOR" ; + attribute recursive_synthesis of nor_8 : function is true ; + attribute pin_bit_information of nor_8 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function decode( code : std_ulogic_vector ) return std_ulogic_vector; + -- Synopsys translate_off + attribute functionality of decode: function is "DECODER"; + -- Synopsys translate_on + + function decode_2to4 + (code : std_ulogic_vector(0 to 1) + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_return_4 ; + -- synopsys translate_off + attribute btr_name of decode_2to4 : function is "VHDL-DECODE"; + attribute recursive_synthesis of decode_2to4 : function is true ; + attribute pin_bit_information of decode_2to4 : function is + (1 => (" ","D1 ","DECR","PIN_BIT_SCALAR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","F0 ","INCR","PIN_BIT_SCALAR")); + -- Synopsys translate_on + + function decode_3to8 + (code : std_ulogic_vector(0 to 2) + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_return_8 ; + -- synopsys translate_off + attribute btr_name of decode_3to8 : function is "VHDL-DECODE"; + attribute recursive_synthesis of decode_3to8 : function is true ; + attribute pin_bit_information of decode_3to8 : function is + (1 => (" ","D2 ","DECR","PIN_BIT_SCALAR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","F0 ","INCR","PIN_BIT_SCALAR")); + -- Synopsys translate_on + + function decode_4to16 + (code : std_ulogic_vector(0 to 3) + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_return_16 ; + -- synopsys translate_off + attribute btr_name of decode_4to16 : function is "VHDL-DECODE"; + attribute recursive_synthesis of decode_4to16 : function is true ; + attribute pin_bit_information of decode_4to16 : function is + (1 => (" ","D3 ","DECR","PIN_BIT_SCALAR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","F0 ","INCR","PIN_BIT_SCALAR")); + -- Synopsys translate_on + + function decode_5to32 + (code : std_ulogic_vector(0 to 4) + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_return_32 ; + -- synopsys translate_off + attribute btr_name of decode_5to32 : function is "VHDL-DECODE"; + attribute recursive_synthesis of decode_5to32 : function is true ; + attribute pin_bit_information of decode_5to32 : function is + (1 => (" ","D4 ","DECR","PIN_BIT_SCALAR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","F0 ","INCR","PIN_BIT_SCALAR")); + -- Synopsys translate_on + + function decode_6to64 + (code : std_ulogic_vector(0 to 5) + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_return_64 ; + -- synopsys translate_off + attribute btr_name of decode_6to64 : function is "VHDL-DECODE"; + attribute recursive_synthesis of decode_6to64 : function is true ; + attribute pin_bit_information of decode_6to64 : function is + (1 => (" ","D5 ","DECR","PIN_BIT_SCALAR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","F0 ","INCR","PIN_BIT_SCALAR")); + -- Synopsys translate_on + +end std_ulogic_function_support; + +package body std_ulogic_function_support is + -- Function Declarations and Attributes + -- Gate Function + function gate + (in0 : std_ulogic_vector; + cond : std_ulogic ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + subtype vec_length is std_ulogic_vector(0 to in0'length-1); + begin + result := in0 and vec_length'(0 to in0'length-1 => cond) ; + return result; + end gate; + + -- This function everses the range direction. + function reverse (arg: std_ulogic_vector) + return std_ulogic_vector + is + variable d, result : std_ulogic_vector(0 to arg'length-1); + begin + d := arg; + for i in 0 to d'length-1 loop + result(result'right - i) := d(i); + end loop; + return result; + end reverse; + + -- Generic Terminator + procedure terminator + (in0 : in std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- Synopsys translate_on + begin + result := in0 ; + end terminator ; + + procedure terminator + (in0 : in std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1); + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 ; + end terminator ; + + -- Generic Delay + function delay + (in0 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + -- initialize variable attribute values + result := in0; + return result; + end delay ; + + function delay + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0; + return result; + end delay ; + + function buff + (in0 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0; + return result; + end buff ; + + function buff + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0; + return result; + end buff ; + +-- inverter single bit + function invert + (in0 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not in0; + return result; + end invert ; + + -- inverter vectored + function invert + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not in0; + return result; + end invert ; + + -- Comparator + function compare + (in0 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 = in1 ; + return result; + end compare ; + +-- comparator mult-bit + function compare + (in0 : std_ulogic_vector; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 = in1 ; + return result; + end compare ; + + -- General XOR_Tree Building Parity Function + function parity + (In0 : std_ulogic_vector + -- Synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- Synopsys translate_on + ) + return Std_uLogic + is + -- Synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- Synopsys translate_on + variable result : std_ulogic; + begin + result := in0(in0'low); + for i in in0'low+1 to in0'high loop + result := in0(i) xor result ; + end loop; + return result; + end parity ; + + -- Specific Size Parity Block Map Function + function parity_map + (In0 : std_ulogic_vector + -- Synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- Synopsys translate_on + ) + return std_ulogic + is + -- Synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- Synopsys translate_on + variable result : std_ulogic; + begin + result := in0(in0'low); + for i in in0'low+1 to in0'high loop + result := in0(i) xor result ; + end loop; + return result; + end parity_map ; + +-- Parity gneration/checking functions + function parity_gen_odd + (in0 : std_ulogic_vector + -- Synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- Synopsys translate_on + ) + return std_ulogic + is + -- Synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- Synopsys translate_on + variable result : std_ulogic; + begin + result := in0(in0'low); + for i in in0'low+1 to in0'high loop + result := in0(i) xor result ; + end loop; + return not result; + end parity_gen_odd ; + + function parity_gen_even + (in0 : std_ulogic_vector + -- Synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- Synopsys translate_on + ) + return std_ulogic + is + -- Synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- Synopsys translate_on + variable result : std_ulogic; + begin + result := in0(in0'low); + for i in in0'low+1 to in0'high loop + result := in0(i) xor result ; + end loop; + return result; + end parity_gen_even ; + + function is_parity_odd + (in0 : std_ulogic_vector + -- Synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- Synopsys translate_on + ) + return std_ulogic + is + -- Synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- Synopsys translate_on + variable result : std_ulogic; + begin + result := in0(in0'low); + for i in in0'low+1 to in0'high loop + result := in0(i) xor result ; + end loop; + return result; + end is_parity_odd ; + + function is_parity_even + (in0 : std_ulogic_vector + -- Synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- Synopsys translate_on + ) + return std_ulogic + is + -- Synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- Synopsys translate_on + variable result : std_ulogic; + begin + result := in0(in0'low); + for i in in0'low+1 to in0'high loop + result := in0(i) xor result ; + end loop; + return not result; + end is_parity_even ; + + function and_reduce + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0(in0'left) ; + for i in in0'range loop + result := result and in0(i); + end loop; + result := result ; + return result; + end and_reduce ; + + function or_reduce + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0(in0'left) ; + for i in in0'range loop + result := result or in0(i); + end loop; + result := result ; + return result; + end or_reduce ; + + function nand_reduce + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0(in0'left) ; + for i in in0'range loop + result := result and in0(i); + end loop; + result := not result ; + return result; + end nand_reduce ; + + function nor_reduce + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0(in0'left) ; + for i in in0'range loop + result := result or in0(i); + end loop; + result := not result ; + return result; + end nor_reduce ; + + function xor_reduce + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := '0' ; + for i in in0'range loop + result := result xor in0(i); + end loop; + result := result ; + return result ; + end xor_reduce ; + + function xnor_reduce + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := '0' ; + for i in in0'range loop + result := result xor in0(i); + end loop; + result := not result ; + return result ; + end xnor_reduce ; + + function gate_and + (gate : std_ulogic ; + in0 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := gate and in0 ; + return result; + end gate_and; + + function gate_and + (gate : std_ulogic ; + in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + variable result : std_ulogic_vector(0 to in0'length-1); + subtype vec_length is std_ulogic_vector(0 to in0'length-1); + begin + result := in0 and vec_length'(0 to in0'length-1 => gate) ; + return result; + end gate_and; + + function gate_or + (gate : std_ulogic ; + in0 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := gate or in0 ; + return result; + end gate_or; + + function gate_or + (gate : std_ulogic ; + in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + variable result : std_ulogic_vector(0 to in0'length-1); + subtype vec_length is std_ulogic_vector(0 to in0'length-1); + begin + result := in0 or vec_length'(0 to in0'length-1 => gate) ; + return result; + end gate_or; + + function gate_nand + (gate : std_ulogic ; + in0 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := gate nand in0 ; + return result; + end gate_nand; + + function gate_nand + (gate : std_ulogic ; + in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + variable result : std_ulogic_vector(0 to in0'length-1); + subtype vec_length is std_ulogic_vector(0 to in0'length-1); + begin + result := in0 nand vec_length'( 0 to in0'length-1 => gate ); + return result; + end gate_nand; + + function gate_nor + (gate : std_ulogic ; + in0 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := gate nor in0 ; + return result; + end gate_nor; + + function gate_nor + (gate : std_ulogic ; + in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + variable result : std_ulogic_vector(0 to in0'length-1); + subtype vec_length is std_ulogic_vector(0 to in0'length-1); + begin + result := in0 nor vec_length'(0 to in0'length-1 => gate) ; + return result; + end gate_nor; + + function gate_xor + (gate : std_ulogic ; + in0 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := gate xor in0 ; + return result; + end gate_xor; + + function gate_xor + (gate : std_ulogic ; + in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + variable result : std_ulogic_vector(0 to in0'length-1); + subtype vec_length is std_ulogic_vector(0 to in0'length-1); + begin + result := in0 xor vec_length'(0 to in0'length-1 => gate) ; + return result; + end gate_xor; + + function gate_xnor + (gate : std_ulogic ; + in0 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := gate = in0 ; + return result; + end gate_xnor; + + function gate_xnor + (gate : std_ulogic ; + in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + subtype vec_length is std_ulogic_vector(0 to in0'length-1); + begin + result := not( in0 xor vec_length'(0 to in0'length-1 => gate) ) ; + return result; + end gate_xnor; + + function gate_and + (gate : std_ulogic_vector; + in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + variable result : std_ulogic_vector(0 to in0'length-1); + variable gate_int : std_ulogic ; + subtype vec_length is std_ulogic_vector(0 to in0'length-1); + begin + gate_int := gate(gate'low) ; + for i in gate'low+1 to gate'high loop + gate_int := gate_int and gate(i); + end loop; + result := in0 and vec_length'(0 to in0'length-1 => gate_int) ; + return result ; + end gate_and; + + function gate_or + (gate : std_ulogic_vector; + in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + variable result : std_ulogic_vector(0 to in0'length-1); + variable gate_int : std_ulogic ; + subtype vec_length is std_ulogic_vector(0 to in0'length-1); + begin + gate_int := gate(gate'low) ; + for i in gate'low+1 to gate'high loop + gate_int := gate_int or gate(i); + end loop; + result := in0 or vec_length'(0 to in0'length-1 => gate_int) ; + return result ; + end gate_or; + + function gate_nand + (gate : std_ulogic_vector; + in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + variable result : std_ulogic_vector(0 to in0'length-1); + variable gate_int : std_ulogic ; + subtype vec_length is std_ulogic_vector(0 to in0'length-1); + begin + gate_int := gate(gate'low) ; + for i in gate'low+1 to gate'high loop + gate_int := gate_int and gate(i); + end loop; + result := in0 and vec_length'(0 to in0'length-1 => gate_int) ; + result := not result ; + return result; + end gate_nand; + + function gate_nor + (gate : std_ulogic_vector; + in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + variable result : std_ulogic_vector(0 to in0'length-1); + variable gate_int : std_ulogic ; + subtype vec_length is std_ulogic_vector(0 to in0'length-1); + begin + gate_int := gate(gate'low) ; + for i in gate'low+1 to gate'high loop + gate_int := gate_int or gate(i); + end loop; + result := in0 or vec_length'(0 to in0'length-1 => gate_int) ; + result := not result ; + return result ; + end gate_nor; + + function xor_2 + (in0 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 xor in1 ; + return result ; + end xor_2 ; + + function xor_2 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 xor in1; + return result ; + end xor_2 ; + + function xor_3 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := (in0 xor in1 xor in2) ; + return result ; + end xor_3 ; + + function xor_3 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 xor in1 xor in2 ; + return result ; + end xor_3 ; + + function xnor_2 + (in0 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 xor in1 ) ; + return result ; + end xnor_2 ; + + function xnor_2 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 xor in1 ) ; + return result ; + end xnor_2 ; + + function xnor_3 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 xor in1 xor in2 ) ; + return result ; + end xnor_3 ; + + function xnor_3 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 xor in1 xor in2 ) ; + return result ; + end xnor_3 ; + + function and_2 + (in0 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 and in1 ; + return result ; + end and_2 ; + + function and_2 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 and in1 ; + return result ; + end and_2 ; + + function and_3 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 and in1 and in2 ; + return result ; + end and_3 ; + + function and_3 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 and in1 and in2 ; + return result ; + end and_3 ; + + function and_4 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 and in1 and in2 and in3 ; + return result ; + end and_4 ; + + function and_4 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 and in1 and in2 and in3 ; + return result ; + end and_4 ; + + function and_5 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 and in1 and in2 and in3 and in4 ; + return result ; + end and_5 ; + + function and_5 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 and in1 and in2 and in3 and in4; + return result ; + end and_5 ; + + function and_6 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 and in1 and in2 and in3 and in4 and in5 ; + return result ; + end and_6 ; + + function and_6 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 and in1 and in2 and in3 and in4 and in5 ; + return result ; + end and_6 ; + + function and_7 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic ; + in6 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 and in1 and in2 and in3 and in4 and in5 and in6 ; + return result ; + end and_7 ; + + function and_7 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector ; + in6 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 and in1 and in2 and in3 and in4 and in5 and in6 ; + return result ; + end and_7 ; + + function and_8 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic ; + in6 : std_ulogic ; + in7 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 and in1 and in2 and in3 and in4 and in5 and in6 and in7 ; + return result ; + end and_8 ; + + function and_8 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector ; + in6 : std_ulogic_vector ; + in7 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 and in1 and in2 and in3 and in4 and in5 and in6 and in7 ; + return result ; + end and_8 ; + + function or_2 + (in0 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 or in1 ; + return result ; + end or_2 ; + + function or_2 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 or in1 ; + return result ; + end or_2 ; + + function or_3 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 or in1 or in2 ; + return result ; + end or_3 ; + + function or_3 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 or in1 or in2 ; + return result ; + end or_3 ; + + function or_4 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 or in1 or in2 or in3 ; + return result ; + end or_4 ; + + function or_4 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 or in1 or in2 or in3 ; + return result ; + end or_4 ; + + function or_5 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 or in1 or in2 or in3 or in4 ; + return result ; + end or_5 ; + + function or_5 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 or in1 or in2 or in3 or in4 ; + return result ; + end or_5 ; + + function or_6 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 or in1 or in2 or in3 or in4 or in5 ; + return result ; + end or_6 ; + + function or_6 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 or in1 or in2 or in3 or in4 or in5 ; + return result ; + end or_6 ; + + function or_7 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic ; + in6 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 or in1 or in2 or in3 or in4 or in5 or in6 ; + return result ; + end or_7 ; + + function or_7 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector ; + in6 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 or in1 or in2 or in3 or in4 or in5 or in6 ; + return result ; + end or_7 ; + + function or_8 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic ; + in6 : std_ulogic ; + in7 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 or in1 or in2 or in3 or in4 or in5 or in6 or in7 ; + return result ; + end or_8 ; + + function or_8 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector ; + in6 : std_ulogic_vector ; + in7 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 or in1 or in2 or in3 or in4 or in5 or in6 or in7 ; + return result ; + end or_8 ; + + function nand_2 + (in0 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 and in1 ) ; + return result ; + end nand_2 ; + + function nand_2 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 and in1 ) ; + return result ; + end nand_2 ; + + function nand_3 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 and in1 and in2 ) ; + return result ; + end nand_3 ; + + function nand_3 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 and in1 and in2 ) ; + return result ; + end nand_3 ; + + function nand_4 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 and in1 and in2 and in3 ) ; + return result ; + end nand_4 ; + + function nand_4 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 and in1 and in2 and in3 ) ; + return result ; + end nand_4 ; + + function nand_5 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 and in1 and in2 and in3 and in4 ) ; + return result ; + end nand_5 ; + + function nand_5 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 and in1 and in2 and in3 and in4 ) ; + return result ; + end nand_5 ; + + function nand_6 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 and in1 and in2 and in3 and in4 and in5 ) ; + return result ; + end nand_6 ; + + function nand_6 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 and in1 and in2 and in3 and in4 and in5 ) ; + return result ; + end nand_6 ; + + function nand_7 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic ; + in6 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 and in1 and in2 and in3 and in4 and in5 and in6) ; + return result ; + end nand_7 ; + + function nand_7 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector ; + in6 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 and in1 and in2 and in3 and in4 and in5 and in6) ; + return result ; + end nand_7 ; + + function nand_8 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic ; + in6 : std_ulogic ; + in7 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 and in1 and in2 and in3 and in4 and in5 and in6 and in7 ) ; + return result ; + end nand_8 ; + + function nand_8 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector ; + in6 : std_ulogic_vector ; + in7 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 and in1 and in2 and in3 and in4 and in5 and in6 and in7 ) ; + return result ; + end nand_8 ; + + function nor_2 + (in0 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 or in1 ) ; + return result ; + end nor_2 ; + + function nor_2 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 or in1 ) ; + return result ; + end nor_2 ; + + function nor_3 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 or in1 or in2 ) ; + return result ; + end nor_3 ; + + function nor_3 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1) ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 or in1 or in2 ) ; + return result ; + end nor_3 ; + + function nor_4 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 or in1 or in2 or in3 ) ; + return result ; + end nor_4 ; + + function nor_4 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1) ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 or in1 or in2 or in3 ) ; + return result ; + end nor_4 ; + + function nor_5 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 or in1 or in2 or in3 or in4 ) ; + return result ; + end nor_5 ; + + function nor_5 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 or in1 or in2 or in3 or in4 ) ; + return result ; + end nor_5 ; + + function nor_6 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 or in1 or in2 or in3 or in4 or in5 ) ; + return result ; + end nor_6 ; + + function nor_6 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 or in1 or in2 or in3 or in4 or in5 ) ; + return result ; + end nor_6 ; + + function nor_7 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic ; + in6 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 or in1 or in2 or in3 or in4 or in5 or in6 ) ; + return result ; + end nor_7 ; + + function nor_7 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector ; + in6 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 or in1 or in2 or in3 or in4 or in5 or in6 ) ; + return result ; + end nor_7 ; + + function nor_8 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic ; + in6 : std_ulogic ; + in7 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 or in1 or in2 or in3 or in4 or in5 or in6 or in7 ) ; + return result ; + end nor_8 ; + + function nor_8 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector ; + in6 : std_ulogic_vector ; + in7 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 or in1 or in2 or in3 or in4 or in5 or in6 or in7 ) ; + return result ; + end nor_8 ; + + function tie_0 + -- synopsys translate_off + (btr : in string :=""; + blkdata : in string :="" + ) + -- synopsys translate_on + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := '0'; + return result; + end tie_0; + + function vector_tie_0 + (width : integer := 1 + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector(0 to width-1) ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + for i in 0 to width-1 loop + result(i) := '0'; + end loop; + return result; + end vector_tie_0; + + function tie_1 + -- synopsys translate_off + (btr : in string :="" + ;blkdata : in string :="" + ) + -- synopsys translate_on + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := '1'; + return result; + end tie_1; + + function vector_tie_1 + (width : integer := 1 + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector(0 to width-1) ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + for i in 0 to width-1 loop + result(i) := '1'; + end loop; + return result; + end vector_tie_1; + + function decode( code : std_ulogic_vector ) return std_ulogic_vector is + variable result : std_ulogic_vector(0 to (2**(code'length)-1)) := (others => '0'); + begin + result := (others => '0'); + result( tconv( code ) ) := '1'; + for i in code'low to code'high loop + if code(i) = 'U' then + result := (others => 'U'); + end if; + end loop; + for i in code'low to code'high loop + if code(i) = 'X' then + result := (others => 'X'); + end if; + end loop; + return result; + end decode; + + function decode_2to4 + (code : std_ulogic_vector(0 to 1) + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_return_4 + is + variable result : std_ulogic_vector(0 to 3) ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + case code is + when "00" => result := "1000"; + when "01" => result := "0100"; + when "10" => result := "0010"; + when "11" => result := "0001"; + when others => result := "XXXX"; + end case; + return result; + end decode_2to4; + + function decode_3to8 + (code : std_ulogic_vector(0 to 2) + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_return_8 + is + variable result : std_ulogic_vector(0 to 7) ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + case code is + when "000" => result := "10000000"; + when "001" => result := "01000000"; + when "010" => result := "00100000"; + when "011" => result := "00010000"; + when "100" => result := "00001000"; + when "101" => result := "00000100"; + when "110" => result := "00000010"; + when "111" => result := "00000001"; + when others => result := "XXXXXXXX"; + end case; + return result; + end decode_3to8; + + function decode_4to16 + (code : std_ulogic_vector(0 to 3) + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_return_16 + is + variable result : std_ulogic_vector(0 to 15) ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + case code is + when "0000" => result := "1000000000000000"; + when "0001" => result := "0100000000000000"; + when "0010" => result := "0010000000000000"; + when "0011" => result := "0001000000000000"; + when "0100" => result := "0000100000000000"; + when "0101" => result := "0000010000000000"; + when "0110" => result := "0000001000000000"; + when "0111" => result := "0000000100000000"; + when "1000" => result := "0000000010000000"; + when "1001" => result := "0000000001000000"; + when "1010" => result := "0000000000100000"; + when "1011" => result := "0000000000010000"; + when "1100" => result := "0000000000001000"; + when "1101" => result := "0000000000000100"; + when "1110" => result := "0000000000000010"; + when "1111" => result := "0000000000000001"; + when others => result := "XXXXXXXXXXXXXXXX"; + end case; + return result; + end decode_4to16; + + function decode_5to32 + (code : std_ulogic_vector(0 to 4) + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_return_32 + is + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + variable result : std_ulogic_vector(0 to 31) ; + begin + case code is + when "00000" => result := "10000000000000000000000000000000"; + when "00001" => result := "01000000000000000000000000000000"; + when "00010" => result := "00100000000000000000000000000000"; + when "00011" => result := "00010000000000000000000000000000"; + when "00100" => result := "00001000000000000000000000000000"; + when "00101" => result := "00000100000000000000000000000000"; + when "00110" => result := "00000010000000000000000000000000"; + when "00111" => result := "00000001000000000000000000000000"; + when "01000" => result := "00000000100000000000000000000000"; + when "01001" => result := "00000000010000000000000000000000"; + when "01010" => result := "00000000001000000000000000000000"; + when "01011" => result := "00000000000100000000000000000000"; + when "01100" => result := "00000000000010000000000000000000"; + when "01101" => result := "00000000000001000000000000000000"; + when "01110" => result := "00000000000000100000000000000000"; + when "01111" => result := "00000000000000010000000000000000"; + when "10000" => result := "00000000000000001000000000000000"; + when "10001" => result := "00000000000000000100000000000000"; + when "10010" => result := "00000000000000000010000000000000"; + when "10011" => result := "00000000000000000001000000000000"; + when "10100" => result := "00000000000000000000100000000000"; + when "10101" => result := "00000000000000000000010000000000"; + when "10110" => result := "00000000000000000000001000000000"; + when "10111" => result := "00000000000000000000000100000000"; + when "11000" => result := "00000000000000000000000010000000"; + when "11001" => result := "00000000000000000000000001000000"; + when "11010" => result := "00000000000000000000000000100000"; + when "11011" => result := "00000000000000000000000000010000"; + when "11100" => result := "00000000000000000000000000001000"; + when "11101" => result := "00000000000000000000000000000100"; + when "11110" => result := "00000000000000000000000000000010"; + when "11111" => result := "00000000000000000000000000000001"; + when others => result := "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; + end case; + return result; + end decode_5to32; + + function decode_6to64 + (code : std_ulogic_vector(0 to 5) + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_return_64 + is + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + variable result : std_ulogic_vector(0 to 63) ; + begin + case code is + when "000000" => result := "1000000000000000000000000000000000000000000000000000000000000000"; + when "000001" => result := "0100000000000000000000000000000000000000000000000000000000000000"; + when "000010" => result := "0010000000000000000000000000000000000000000000000000000000000000"; + when "000011" => result := "0001000000000000000000000000000000000000000000000000000000000000"; + when "000100" => result := "0000100000000000000000000000000000000000000000000000000000000000"; + when "000101" => result := "0000010000000000000000000000000000000000000000000000000000000000"; + when "000110" => result := "0000001000000000000000000000000000000000000000000000000000000000"; + when "000111" => result := "0000000100000000000000000000000000000000000000000000000000000000"; + when "001000" => result := "0000000010000000000000000000000000000000000000000000000000000000"; + when "001001" => result := "0000000001000000000000000000000000000000000000000000000000000000"; + when "001010" => result := "0000000000100000000000000000000000000000000000000000000000000000"; + when "001011" => result := "0000000000010000000000000000000000000000000000000000000000000000"; + when "001100" => result := "0000000000001000000000000000000000000000000000000000000000000000"; + when "001101" => result := "0000000000000100000000000000000000000000000000000000000000000000"; + when "001110" => result := "0000000000000010000000000000000000000000000000000000000000000000"; + when "001111" => result := "0000000000000001000000000000000000000000000000000000000000000000"; + when "010000" => result := "0000000000000000100000000000000000000000000000000000000000000000"; + when "010001" => result := "0000000000000000010000000000000000000000000000000000000000000000"; + when "010010" => result := "0000000000000000001000000000000000000000000000000000000000000000"; + when "010011" => result := "0000000000000000000100000000000000000000000000000000000000000000"; + when "010100" => result := "0000000000000000000010000000000000000000000000000000000000000000"; + when "010101" => result := "0000000000000000000001000000000000000000000000000000000000000000"; + when "010110" => result := "0000000000000000000000100000000000000000000000000000000000000000"; + when "010111" => result := "0000000000000000000000010000000000000000000000000000000000000000"; + when "011000" => result := "0000000000000000000000001000000000000000000000000000000000000000"; + when "011001" => result := "0000000000000000000000000100000000000000000000000000000000000000"; + when "011010" => result := "0000000000000000000000000010000000000000000000000000000000000000"; + when "011011" => result := "0000000000000000000000000001000000000000000000000000000000000000"; + when "011100" => result := "0000000000000000000000000000100000000000000000000000000000000000"; + when "011101" => result := "0000000000000000000000000000010000000000000000000000000000000000"; + when "011110" => result := "0000000000000000000000000000001000000000000000000000000000000000"; + when "011111" => result := "0000000000000000000000000000000100000000000000000000000000000000"; + when "100000" => result := "0000000000000000000000000000000010000000000000000000000000000000"; + when "100001" => result := "0000000000000000000000000000000001000000000000000000000000000000"; + when "100010" => result := "0000000000000000000000000000000000100000000000000000000000000000"; + when "100011" => result := "0000000000000000000000000000000000010000000000000000000000000000"; + when "100100" => result := "0000000000000000000000000000000000001000000000000000000000000000"; + when "100101" => result := "0000000000000000000000000000000000000100000000000000000000000000"; + when "100110" => result := "0000000000000000000000000000000000000010000000000000000000000000"; + when "100111" => result := "0000000000000000000000000000000000000001000000000000000000000000"; + when "101000" => result := "0000000000000000000000000000000000000000100000000000000000000000"; + when "101001" => result := "0000000000000000000000000000000000000000010000000000000000000000"; + when "101010" => result := "0000000000000000000000000000000000000000001000000000000000000000"; + when "101011" => result := "0000000000000000000000000000000000000000000100000000000000000000"; + when "101100" => result := "0000000000000000000000000000000000000000000010000000000000000000"; + when "101101" => result := "0000000000000000000000000000000000000000000001000000000000000000"; + when "101110" => result := "0000000000000000000000000000000000000000000000100000000000000000"; + when "101111" => result := "0000000000000000000000000000000000000000000000010000000000000000"; + when "110000" => result := "0000000000000000000000000000000000000000000000001000000000000000"; + when "110001" => result := "0000000000000000000000000000000000000000000000000100000000000000"; + when "110010" => result := "0000000000000000000000000000000000000000000000000010000000000000"; + when "110011" => result := "0000000000000000000000000000000000000000000000000001000000000000"; + when "110100" => result := "0000000000000000000000000000000000000000000000000000100000000000"; + when "110101" => result := "0000000000000000000000000000000000000000000000000000010000000000"; + when "110110" => result := "0000000000000000000000000000000000000000000000000000001000000000"; + when "110111" => result := "0000000000000000000000000000000000000000000000000000000100000000"; + when "111000" => result := "0000000000000000000000000000000000000000000000000000000010000000"; + when "111001" => result := "0000000000000000000000000000000000000000000000000000000001000000"; + when "111010" => result := "0000000000000000000000000000000000000000000000000000000000100000"; + when "111011" => result := "0000000000000000000000000000000000000000000000000000000000010000"; + when "111100" => result := "0000000000000000000000000000000000000000000000000000000000001000"; + when "111101" => result := "0000000000000000000000000000000000000000000000000000000000000100"; + when "111110" => result := "0000000000000000000000000000000000000000000000000000000000000010"; + when "111111" => result := "0000000000000000000000000000000000000000000000000000000000000001"; + when others => result := "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; + end case; + return result; + end decode_6to64; + +-- full adder function + procedure full_add + (add_1 : in std_ulogic ; + add_2 : in std_ulogic ; + cryin : in std_ulogic ; + signal sum : out std_ulogic ; + signal carry : out std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + is + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + sum <= add_1 xor add_2 xor cryin; + carry <= (add_1 and add_2) or + (add_1 and cryin) or + (add_2 and cryin); + end full_add; + + procedure full_add + (add_1 : in std_ulogic_vector ; + add_2 : in std_ulogic_vector ; + cryin : in std_ulogic_vector ; + signal sum : out std_ulogic_vector ; + signal carry : out std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + is + variable sum_result : std_ulogic_vector(sum'range) ; + variable carry_result : std_ulogic_vector(carry'range) ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + -- synopsys translate_off + assert (add_1'length = add_2'length) + report "Addends of Full_Add are not the same length." + severity error; + assert (add_1'length = cryin'length) and (add_2'length = cryin'length) + report "Addends of Full_Add are not the same length as the CryIn." + severity error; + -- synopsys translate_on + sum_result := add_1 xor add_2 xor cryin; + carry_result := (add_1 and add_2) or + (add_1 and cryin) or + (add_2 and cryin); + sum <= sum_result ; + carry <= carry_result ; + end full_add; + + -- Ripple adder function + procedure ripple_adder + ( add_1 : in std_ulogic_vector ; + add_2 : in std_ulogic_vector ; + signal sum : out std_ulogic_vector ; + signal carry : out std_ulogic ) + is + -- Synopsys translate_off + attribute unroll_loop : boolean; + attribute unroll_loop of ripple : label is true; + -- Synopsys translate_on + variable a : std_ulogic_vector(1 to add_1'length) ; + variable b : std_ulogic_vector(1 to add_2'length) ; + variable c : std_ulogic_vector(0 to add_1'length) ; + variable result : std_ulogic_vector(1 to add_1'length) ; + begin + a := add_1; + b := add_2; + c(c'right) := '0' ; + ripple:for i in result'right downto 1 loop + c(i-1) := ( c(i) and a(i) ) or + ( c(i) and b(i) ) or + ( a(i) and b(i) ) ; + result(i) := a(i) xor b(i) xor c(i) ; + end loop ; + sum <= result ; + carry <= c(c'left) ; + end ripple_adder ; + + procedure ripple_adder + ( add_1 : in std_ulogic_vector ; + add_2 : in std_ulogic_vector ; + signal sum : out std_ulogic_vector ) + is + -- Synopsys translate_off + attribute unroll_loop : boolean; + attribute unroll_loop of ripple : label is true; + -- Synopsys translate_on + variable a : std_ulogic_vector(1 to add_1'length) ; + variable b : std_ulogic_vector(1 to add_2'length) ; + variable c : std_ulogic_vector(1 to add_1'length) ; + variable result : std_ulogic_vector(1 to add_1'length) ; + begin + a := add_1; + b := add_2; + c(c'right) := '0' ; + ripple:for i in result'right downto 2 loop + c(i-1) := ( c(i) and a(i) ) or + ( c(i) and b(i) ) or + ( a(i) and b(i) ) ; + result(i) := a(i) xor b(i) xor c(i) ; + end loop ; + result(1) := a(1) xor b(1) xor c(1) ; + sum <= result ; + end ripple_adder ; + + -- Dot Functions + function dot_and + (in0 : std_ulogic_vector ) + return std_ulogic + is + variable result : std_ulogic ; + begin + result := '1'; + for i in in0'range loop + result := in0(i) and result ; + end loop ; + return result; + end dot_and ; + + function dot_or + (in0 : std_ulogic_vector ) + return std_ulogic + is + variable result : std_ulogic ; + begin + result := '0'; + for i in in0'range loop + result := in0(i) or result ; + end loop ; + return result; + end dot_or ; + + function clock_tree_dot + (in0 : std_ulogic_vector ) + return std_ulogic + is + variable result : std_ulogic ; + begin + result := '1'; + for i in in0'range loop + result := in0(i) and result ; + end loop ; + return result; + end clock_tree_dot ; + + function clock_tree_dot + (in0 : bit_vector ) + return bit + is + variable result : bit ; + begin + result := '1'; + for i in in0'range loop + result := in0(i) and result ; + end loop ; + return result; + end clock_tree_dot ; + +end std_ulogic_function_support; + diff --git a/rel/src/vhdl/ibm/std_ulogic_mux_support.vhdl b/rel/src/vhdl/ibm/std_ulogic_mux_support.vhdl new file mode 100644 index 0000000..430e8f6 --- /dev/null +++ b/rel/src/vhdl/ibm/std_ulogic_mux_support.vhdl @@ -0,0 +1,1544 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +--*************************************************************************** +-- Copyright 2020 International Business Machines +-- +-- Licensed under the Apache License, Version 2.0 (the “License”); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- The patent license granted to you in Section 3 of the License, as applied +-- to the “Work,” hereby includes implementations of the Work in physical form. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an “AS IS” BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- +--*************************************************************************** +library ibm,ieee ; +use ieee.std_logic_1164.all ; +use ibm.std_ulogic_support.all; + +package std_ulogic_mux_support is + + -- Multiplexor/Selector Functions + function mux_2to1 + (code : std_ulogic ; + in0 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + + function mux_2to1 + (code : std_ulogic ; + in0 : std_ulogic_vector ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of mux_2to1 : function is "VHDL-MUX" ; + attribute recursive_synthesis of mux_2to1 : function is true; + attribute pin_bit_information of mux_2to1 : function is + (1 => (" ","S0 ","DECR","PIN_BIT_SCALAR"), + 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","D1 ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","PASS "," "," "), + 5 => (" ","PASS "," "," "), + 6 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function mux_4to1 + (code : std_ulogic_vector(0 to 1) ; + in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + + function mux_4to1 + (code : std_ulogic_vector(0 to 1) ; + in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of mux_4to1 : function is "VHDL-MUX" ; + attribute recursive_synthesis of mux_4to1 : function is true; + attribute pin_bit_information of mux_4to1 : function is + (1 => (" ","S1 ","DECR","PIN_BIT_SCALAR"), + 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","D1 ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","D2 ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","D3 ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function mux_8to1 + (code : std_ulogic_vector(0 to 2) ; + in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic ; + in6 : std_ulogic ; + in7 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + + function mux_8to1 + (code : std_ulogic_vector(0 to 2) ; + in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector ; + in6 : std_ulogic_vector ; + in7 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of mux_8to1 : function is "VHDL-MUX" ; + attribute recursive_synthesis of mux_8to1 : function is true; + attribute pin_bit_information of mux_8to1 : function is + (1 => (" ","S2 ","DECR","PIN_BIT_SCALAR"), + 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","D1 ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","D2 ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","D3 ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","D4 ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","D5 ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","D6 ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","D7 ","SAME","PIN_BIT_VECTOR"), + 10 => (" ","PASS "," "," "), + 11 => (" ","PASS "," "," "), + 12 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function not_mux_2to1 + (code : std_ulogic ; + in0 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + + function not_mux_2to1 + (code : std_ulogic ; + in0 : std_ulogic_vector ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of not_mux_2to1 : function is "VHDL-MUX" ; + attribute recursive_synthesis of not_mux_2to1 : function is true; + attribute pin_bit_information of not_mux_2to1 : function is + (1 => (" ","S0 ","DECR","PIN_BIT_SCALAR"), + 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","D1 ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","PASS "," "," "), + 5 => (" ","PASS "," "," "), + 6 => (" ","INV ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function not_mux_4to1 + (code : std_ulogic_vector(0 to 1) ; + in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + + function not_mux_4to1 + (code : std_ulogic_vector(0 to 1) ; + in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of not_mux_4to1 : function is "VHDL-MUX" ; + attribute recursive_synthesis of not_mux_4to1 : function is true; + attribute pin_bit_information of not_mux_4to1 : function is + (1 => (" ","S1 ","DECR","PIN_BIT_SCALAR"), + 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","D1 ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","D2 ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","D3 ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","INV ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function not_mux_8to1 + (code : std_ulogic_vector(0 to 2) ; + in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic ; + in6 : std_ulogic ; + in7 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + + function not_mux_8to1 + (code : std_ulogic_vector(0 to 2) ; + in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector ; + in6 : std_ulogic_vector ; + in7 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of not_mux_8to1 : function is "VHDL-MUX" ; + attribute recursive_synthesis of not_mux_8to1 : function is true; + attribute pin_bit_information of not_mux_8to1 : function is + (1 => (" ","S2 ","DECR","PIN_BIT_SCALAR"), + 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","D1 ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","D2 ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","D3 ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","D4 ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","D5 ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","D6 ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","D7 ","SAME","PIN_BIT_VECTOR"), + 10 => (" ","PASS "," "," "), + 11 => (" ","PASS "," "," "), + 12 => (" ","INV ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + -- Primitive selector input functions + function select_1of2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + + function select_1of2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of select_1of2 : function is "VHDL-SELECT" ; + attribute recursive_synthesis of select_1of2 : function is true; + attribute pin_bit_information of select_1of2 : function is + (1 => (" ","S0 ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","S1 ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","D1 ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function select_1of3 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + + function select_1of3 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of select_1of3 : function is "VHDL-SELECT" ; + attribute recursive_synthesis of select_1of3 : function is true; + attribute pin_bit_information of select_1of3 : function is + (1 => (" ","S0 ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","S1 ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","D1 ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","S2 ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","D2 ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function select_1of4 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + + function select_1of4 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of select_1of4 : function is "VHDL-SELECT" ; + attribute recursive_synthesis of select_1of4 : function is true; + attribute pin_bit_information of select_1of4 : function is + (1 => (" ","S0 ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","S1 ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","D1 ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","S2 ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","D2 ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","S3 ","SAME","PIN_BIT_SCALAR"), + 8 => (" ","D3 ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function select_1of8 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic ; + in3 : std_ulogic ; + gate4 : std_ulogic ; + in4 : std_ulogic ; + gate5 : std_ulogic ; + in5 : std_ulogic ; + gate6 : std_ulogic ; + in6 : std_ulogic ; + gate7 : std_ulogic ; + in7 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + + function select_1of8 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic ; + in3 : std_ulogic_vector ; + gate4 : std_ulogic ; + in4 : std_ulogic_vector ; + gate5 : std_ulogic ; + in5 : std_ulogic_vector ; + gate6 : std_ulogic ; + in6 : std_ulogic_vector ; + gate7 : std_ulogic ; + in7 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of select_1of8 : function is "VHDL-SELECT" ; + attribute recursive_synthesis of select_1of8 : function is true; + attribute pin_bit_information of select_1of8 : function is + (1 => (" ","S0 ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","S1 ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","D1 ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","S2 ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","D2 ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","S3 ","SAME","PIN_BIT_SCALAR"), + 8 => (" ","D3 ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","S4 ","SAME","PIN_BIT_SCALAR"), + 10 => (" ","D4 ","SAME","PIN_BIT_VECTOR"), + 11 => (" ","S5 ","SAME","PIN_BIT_SCALAR"), + 12 => (" ","D5 ","SAME","PIN_BIT_VECTOR"), + 13 => (" ","S6 ","SAME","PIN_BIT_SCALAR"), + 14 => (" ","D6 ","SAME","PIN_BIT_VECTOR"), + 15 => (" ","S7 ","SAME","PIN_BIT_SCALAR"), + 16 => (" ","D7 ","SAME","PIN_BIT_VECTOR"), + 17 => (" ","PASS "," "," "), + 18 => (" ","PASS "," "," "), + 19 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function not_select_1of2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + + function not_select_1of2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of not_select_1of2 : function is "VHDL-SELECT" ; + attribute recursive_synthesis of not_select_1of2 : function is true; + attribute pin_bit_information of not_select_1of2 : function is + (1 => (" ","S0 ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","S1 ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","D1 ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","INV ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function not_select_1of3 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + + function not_select_1of3 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of not_select_1of3 : function is "VHDL-SELECT" ; + attribute recursive_synthesis of not_select_1of3 : function is true; + attribute PIN_BIT_INFORMATION of not_select_1of3 : function is + (1 => (" ","S0 ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","S1 ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","D1 ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","S2 ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","D2 ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","INV ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function not_select_1of4 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + + function not_select_1of4 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of not_select_1of4 : function is "VHDL-SELECT" ; + attribute recursive_synthesis of not_select_1of4 : function is true; + attribute pin_bit_information of not_select_1of4 : function is + (1 => (" ","S0 ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","S1 ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","D1 ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","S2 ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","D2 ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","S3 ","SAME","PIN_BIT_SCALAR"), + 8 => (" ","D3 ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","INV ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function not_select_1of8 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic ; + in3 : std_ulogic ; + gate4 : std_ulogic ; + in4 : std_ulogic ; + gate5 : std_ulogic ; + in5 : std_ulogic ; + gate6 : std_ulogic ; + in6 : std_ulogic ; + gate7 : std_ulogic ; + in7 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + + function not_select_1of8 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic ; + in3 : std_ulogic_vector ; + gate4 : std_ulogic ; + in4 : std_ulogic_vector ; + gate5 : std_ulogic ; + in5 : std_ulogic_vector ; + gate6 : std_ulogic ; + in6 : std_ulogic_vector ; + gate7 : std_ulogic ; + in7 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of not_select_1of8 : function is "VHDL-SELECT" ; + attribute recursive_synthesis of not_select_1of8 : function is true; + attribute pin_bit_information of not_select_1of8 : function is + (1 => (" ","S0 ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","S1 ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","D1 ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","S2 ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","D2 ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","S3 ","SAME","PIN_BIT_SCALAR"), + 8 => (" ","D3 ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","S4 ","SAME","PIN_BIT_SCALAR"), + 10 => (" ","D4 ","SAME","PIN_BIT_VECTOR"), + 11 => (" ","S5 ","SAME","PIN_BIT_SCALAR"), + 12 => (" ","D5 ","SAME","PIN_BIT_VECTOR"), + 13 => (" ","S6 ","SAME","PIN_BIT_SCALAR"), + 14 => (" ","D6 ","SAME","PIN_BIT_VECTOR"), + 15 => (" ","S7 ","SAME","PIN_BIT_SCALAR"), + 16 => (" ","D7 ","SAME","PIN_BIT_VECTOR"), + 17 => (" ","PASS "," "," "), + 18 => (" ","PASS "," "," "), + 19 => (" ","INV ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + +end std_ulogic_mux_support; + +package body std_ulogic_mux_support is + + -- Multiplexor/Selector Functions + function mux_2to1 + (code : std_ulogic ; + in0 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic; + begin + case code is + when '0' => result := in0; + when '1' => result := in1; + when others => result := 'X'; + end case; + return result; + end mux_2to1 ; + + function mux_2to1 + (code : std_ulogic ; + in0 : std_ulogic_vector ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + case code is + when '0' => result := in0; + when '1' => result := in1; + when others => result := (others => 'X'); + end case; + return result; + end mux_2to1 ; + + function mux_4to1 + (code : std_ulogic_vector(0 to 1) ; + in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic; + begin + case code is + when "00" => result := in0; + when "01" => result := in1; + when "10" => result := in2; + when "11" => result := in3; + when others => result := 'X'; + end case; + return result; + end mux_4to1 ; + + function mux_4to1 + (code : std_ulogic_vector(0 to 1) ; + in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + case code is + when "00" => result := in0; + when "01" => result := in1; + when "10" => result := in2; + when "11" => result := in3; + when others => result := (others => 'X'); + end case; + return result; + end mux_4to1 ; + + function mux_8to1 + (code : std_ulogic_vector(0 to 2) ; + in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic ; + in6 : std_ulogic ; + in7 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic; + begin + case code is + when "000" => result := in0; + when "001" => result := in1; + when "010" => result := in2; + when "011" => result := in3; + when "100" => result := in4; + when "101" => result := in5; + when "110" => result := in6; + when "111" => result := in7; + when others => result := 'X'; + end case; + return result; + end mux_8to1 ; + + function mux_8to1 + (code : std_ulogic_vector(0 to 2) ; + in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector ; + in6 : std_ulogic_vector ; + in7 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + case code is + when "000" => result := in0; + when "001" => result := in1; + when "010" => result := in2; + when "011" => result := in3; + when "100" => result := in4; + when "101" => result := in5; + when "110" => result := in6; + when "111" => result := in7; + when others => result := (others => 'X'); + end case; + return result; + end mux_8to1 ; + + -- Inverted Multiplexor Selector/Functions + function not_mux_2to1 + (code : std_ulogic ; + in0 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic; + begin + case code is + when '0' => result := not in0; + when '1' => result := not in1; + when others => result := 'X'; + end case; + return result; + end not_mux_2to1 ; + + function not_mux_2to1 + (code : std_ulogic ; + in0 : std_ulogic_vector ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + case code is + when '0' => result := not in0; + when '1' => result := not in1; + when others => result := (others => 'X'); + end case; + return result; + end not_mux_2to1 ; + + function not_mux_4to1 + (code : std_ulogic_vector(0 to 1) ; + in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic; + begin + case code is + when "00" => result := not in0; + when "01" => result := not in1; + when "10" => result := not in2; + when "11" => result := not in3; + when others => result := 'X'; + end case; + return result; + end not_mux_4to1 ; + + function not_mux_4to1 + (code : std_ulogic_vector(0 to 1) ; + in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + case code is + when "00" => result := not in0; + when "01" => result := not in1; + when "10" => result := not in2; + when "11" => result := not in3; + when others => result := (others => 'X'); + end case; + return result; + end not_mux_4to1 ; + + function not_mux_8to1 + (code : std_ulogic_vector(0 to 2) ; + in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic ; + in6 : std_ulogic ; + in7 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic; + begin + case code is + when "000" => result := not in0; + when "001" => result := not in1; + when "010" => result := not in2; + when "011" => result := not in3; + when "100" => result := not in4; + when "101" => result := not in5; + when "110" => result := not in6; + when "111" => result := not in7; + when others => result := 'X'; + end case; + return result; + end not_mux_8to1 ; + + function not_mux_8to1 + (code : std_ulogic_vector(0 to 2) ; + in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector ; + in6 : std_ulogic_vector ; + in7 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + case code is + when "000" => result := not in0; + when "001" => result := not in1; + when "010" => result := not in2; + when "011" => result := not in3; + when "100" => result := not in4; + when "101" => result := not in5; + when "110" => result := not in6; + when "111" => result := not in7; + when others => result := (others => 'X'); + end case; + return result; + end not_mux_8to1 ; + + -- Vectored primitive selector input functions + function select_1of2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 and in0 ) or + ( gate1 and in1 ); + return result ; + end select_1of2 ; + + function select_1of2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector(0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( ( 0 to in1'length-1 => gate1 ) and in1 ); + return result ; + end select_1of2 ; + + function select_1of3 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 and in0 ) or + ( gate1 and in1 ) or + ( gate2 and in2 ) ; + return result ; + end select_1of3 ; + + function select_1of3 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( ( 0 to in1'length-1 => gate1 ) and in1 ) or + ( ( 0 to in1'length-1 => gate2 ) and in2 ); + return result ; + end select_1of3 ; + + function select_1of4 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 and in0 ) or + ( gate1 and in1 ) or + ( gate2 and in2 ) or + ( gate3 and in3 ); + return result ; + end select_1of4 ; + + function select_1of4 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( ( 0 to in1'length-1 => gate1 ) and in1 ) or + ( ( 0 to in2'length-1 => gate2 ) and in2 ) or + ( ( 0 to in3'length-1 => gate3 ) and in3 ) ; + return result ; + end select_1of4 ; + + function select_1of8 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic ; + in3 : std_ulogic ; + gate4 : std_ulogic ; + in4 : std_ulogic ; + gate5 : std_ulogic ; + in5 : std_ulogic ; + gate6 : std_ulogic ; + in6 : std_ulogic ; + gate7 : std_ulogic ; + in7 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 and in0 ) or + ( gate1 and in1 ) or + ( gate2 and in2 ) or + ( gate3 and in3 ) or + ( gate4 and in4 ) or + ( gate5 and in5 ) or + ( gate6 and in6 ) or + ( gate7 and in7 ) ; + return result ; + end select_1of8 ; + + function select_1of8 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic ; + in3 : std_ulogic_vector ; + gate4 : std_ulogic ; + in4 : std_ulogic_vector ; + gate5 : std_ulogic ; + in5 : std_ulogic_vector ; + gate6 : std_ulogic ; + in6 : std_ulogic_vector ; + gate7 : std_ulogic ; + in7 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( ( 0 to in1'length-1 => gate1 ) and in1 ) or + ( ( 0 to in2'length-1 => gate2 ) and in2 ) or + ( ( 0 to in3'length-1 => gate3 ) and in3 ) or + ( ( 0 to in4'length-1 => gate4 ) and in4 ) or + ( ( 0 to in5'length-1 => gate5 ) and in5 ) or + ( ( 0 to in6'length-1 => gate6 ) and in6 ) or + ( ( 0 to in7'length-1 => gate7 ) and in7 ) ; + return result ; + end select_1of8 ; + + function not_select_1of2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 and in0 ) or + ( gate1 and in1 ) ) ; + return result ; + end not_select_1of2 ; + + function not_select_1of2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not( ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( ( 0 to in1'length-1 => gate1 ) and in1 ) ) ; + return result ; + end not_select_1of2 ; + + function not_select_1of3 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 and in0 ) or + ( gate1 and in1 ) or + ( gate2 and in2 ) ) ; + return result ; + end not_select_1of3 ; + + function not_select_1of3 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not( ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( ( 0 to in1'length-1 => gate1 ) and in1 ) or + ( ( 0 to in1'length-1 => gate2 ) and in2 ) ) ; + return result ; + end not_select_1of3 ; + + function not_select_1of4 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 and in0 ) or + ( gate1 and in1 ) or + ( gate2 and in2 ) or + ( gate3 and in3 ) ) ; + return result ; + end not_select_1of4 ; + + function not_select_1of4 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not( ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( ( 0 to in1'length-1 => gate1 ) and in1 ) or + ( ( 0 to in2'length-1 => gate2 ) and in2 ) or + ( ( 0 to in3'length-1 => gate3 ) and in3 ) ) ; + return result ; + end not_select_1of4 ; + + function not_select_1of8 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic ; + in3 : std_ulogic ; + gate4 : std_ulogic ; + in4 : std_ulogic ; + gate5 : std_ulogic ; + in5 : std_ulogic ; + gate6 : std_ulogic ; + in6 : std_ulogic ; + gate7 : std_ulogic ; + in7 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 and in0 ) or + ( gate1 and in1 ) or + ( gate2 and in2 ) or + ( gate3 and in3 ) or + ( gate4 and in4 ) or + ( gate5 and in5 ) or + ( gate6 and in6 ) or + ( gate7 and in7 ) ) ; + return result ; + end not_select_1of8 ; + + function not_select_1of8 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic ; + in3 : std_ulogic_vector ; + gate4 : std_ulogic ; + in4 : std_ulogic_vector ; + gate5 : std_ulogic ; + in5 : std_ulogic_vector ; + gate6 : std_ulogic ; + in6 : std_ulogic_vector ; + gate7 : std_ulogic ; + in7 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not( ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( ( 0 to in1'length-1 => gate1 ) and in1 ) or + ( ( 0 to in2'length-1 => gate2 ) and in2 ) or + ( ( 0 to in3'length-1 => gate3 ) and in3 ) or + ( ( 0 to in4'length-1 => gate4 ) and in4 ) or + ( ( 0 to in5'length-1 => gate5 ) and in5 ) or + ( ( 0 to in6'length-1 => gate6 ) and in6 ) or + ( ( 0 to in7'length-1 => gate7 ) and in7 ) ) ; + return result ; + end not_select_1of8 ; + +end std_ulogic_mux_support; diff --git a/rel/src/vhdl/ibm/std_ulogic_support.vhdl b/rel/src/vhdl/ibm/std_ulogic_support.vhdl new file mode 100644 index 0000000..63cee79 --- /dev/null +++ b/rel/src/vhdl/ibm/std_ulogic_support.vhdl @@ -0,0 +1,2706 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +--*************************************************************************** +-- Copyright 2020 International Business Machines +-- +-- Licensed under the Apache License, Version 2.0 (the “License”); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- The patent license granted to you in Section 3 of the License, as applied +-- to the “Work,” hereby includes implementations of the Work in physical form. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an “AS IS” BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- +--*************************************************************************** +library ieee, ibm ; +use ieee.std_logic_1164.all ; +use ieee.numeric_std.all ; + +package std_ulogic_support is + + attribute like_builtin: boolean; + attribute dc_allow: boolean; + attribute type_convert: boolean; + attribute recursive_synthesis: boolean; + attribute functionality: string; + attribute btr_name: string; + attribute block_data: string; + type pbi_el_t is array(0 to 3) of string; + type pbi_t is array(integer range <>) of pbi_el_t; + attribute pin_bit_information: pbi_t; + attribute dynamic_block_data: string; + + type base_t is ( bin, oct, dec, hex ); + + ------------------------------------------------------------------- + -- Overloaded Relational Operator that can return std_ulogic + ------------------------------------------------------------------- + function "=" ( l,r : integer ) return std_ulogic; + function "/=" ( l,r : integer ) return std_ulogic; + function ">" ( l,r : integer ) return std_ulogic; + function ">=" ( l,r : integer ) return std_ulogic; + function "<" ( l,r : integer ) return std_ulogic; + function "<=" ( l,r : integer ) return std_ulogic; + + function "=" ( l,r : std_ulogic ) return std_ulogic; + function "/=" ( l,r : std_ulogic ) return std_ulogic; + function ">" ( l,r : std_ulogic ) return std_ulogic; + function ">=" ( l,r : std_ulogic ) return std_ulogic; + function "<" ( l,r : std_ulogic ) return std_ulogic; + function "<=" ( l,r : std_ulogic ) return std_ulogic; + + function "=" ( l, r : std_ulogic_vector ) return std_ulogic; + function "/=" ( l, r : std_ulogic_vector ) return std_ulogic; + function ">" ( l, r : std_ulogic_vector ) return std_ulogic; + function ">=" ( l, r : std_ulogic_vector ) return std_ulogic; + function "<" ( l, r : std_ulogic_vector ) return std_ulogic; + function "<=" ( l, r : std_ulogic_vector ) return std_ulogic; +-- synopsys translate_off + attribute like_builtin of "=" :function is true; + attribute like_builtin of "/=" :function is true; + attribute like_builtin of ">" :function is true; + attribute like_builtin of ">=" :function is true; + attribute like_builtin of "<" :function is true; + attribute like_builtin of "<=" :function is true; +-- Synopsys translate_on + ------------------------------------------------------------------- + -- Relational Functions that can return Boolean + ------------------------------------------------------------------- + function eq( l,r : std_ulogic ) return boolean; + function ne( l,r : std_ulogic ) return boolean; + function gt( l,r : std_ulogic ) return boolean; + function ge( l,r : std_ulogic ) return boolean; + function lt( l,r : std_ulogic ) return boolean; + function le( l,r : std_ulogic ) return boolean; + + ------------------------------------------------------------------- + -- Relational Functions that can return std_ulogic + ------------------------------------------------------------------- + + function eq( l,r : std_ulogic ) return std_ulogic; + function ne( l,r : std_ulogic ) return std_ulogic; + function gt( l,r : std_ulogic ) return std_ulogic; + function ge( l,r : std_ulogic ) return std_ulogic; + function lt( l,r : std_ulogic ) return std_ulogic; + function le( l,r : std_ulogic ) return std_ulogic; + + ------------------------------------------------------------------- + -- Vectorized Relational Functions + ------------------------------------------------------------------- + + function eq( l,r : std_ulogic_vector ) return boolean; + function ne( l,r : std_ulogic_vector ) return boolean; + function gt( l,r : std_ulogic_vector ) return boolean; + function ge( l,r : std_ulogic_vector ) return boolean; + function lt( l,r : std_ulogic_vector ) return boolean; + function le( l,r : std_ulogic_vector ) return boolean; + + function eq( l,r : std_ulogic_vector ) return std_ulogic; + function ne( l,r : std_ulogic_vector ) return std_ulogic; + function gt( l,r : std_ulogic_vector ) return std_ulogic; + function ge( l,r : std_ulogic_vector ) return std_ulogic; + function lt( l,r : std_ulogic_vector ) return std_ulogic; + function le( l,r : std_ulogic_vector ) return std_ulogic; +-- Synopsys translate_off + attribute functionality of eq : function is "="; + attribute functionality of ne : function is "/="; + attribute functionality of gt : function is ">"; + attribute functionality of ge : function is ">="; + attribute functionality of lt : function is "<"; + attribute functionality of le : function is "<="; + + attribute dc_allow of eq : function is true; + attribute dc_allow of ne : function is true; +-- Synopsys translate_on + + ------------------------------------------------------------------- + -- Type Conversion Functions + ------------------------------------------------------------------- + + -- Boolean conversion to other types + function tconv( b : boolean ) return bit; + function tconv( b : boolean ) return std_ulogic; +-- Synopsys translate_off + function tconv( b : boolean ) return string; +-- Synopsys translate_on + + -- Bit to other types + function tconv( b : bit ) return boolean; + function tconv( b : bit ) return integer; + function tconv( b : bit ) return std_ulogic; +-- Synopsys translate_off + function tconv( b : bit ) return character; + function tconv( b : bit ) return string; +-- Synopsys translate_on + + -- Bit_vector to other types + function tconv( b : bit_vector ) return integer; + function tconv( b : bit_vector ) return std_ulogic_vector; +-- function tconv( b : bit_vector ) return std_logic_vector; +-- synopsys translate_off + function tconv( b : bit_vector ) return string; + function tconv( b : bit_vector; base : base_t ) return string; +-- synopsys translate_on + + -- Integer conversion to other types + function tconv( n : integer; w: positive ) return bit_vector ; + function tconv( n : integer; w: positive ) return std_ulogic_vector ; +-- synopsys translate_off + function tconv( n : integer; w: positive ) return string ; + function tconv( n : integer ) return string ; +-- synopsys translate_on + +-- Synopsys translate_off + -- String conversion to other types + function tconv( s : string ) return integer ; + function tconv( s : string; base : base_t ) return integer ; + function tconv( s : string ) return bit ; + function tconv( s : string ) return bit_vector ; + function tconv( s : string; base : base_t ) return bit_vector ; + function tconv( s : string ) return std_ulogic ; + function tconv( s : string ) return std_ulogic_vector ; + function tconv( s : string; base : base_t ) return std_ulogic_vector ; +-- Synopsys translate_on + + -- Std_uLogic to other types + function tconv( s : std_ulogic ) return boolean; + function tconv( s : std_ulogic ) return bit; + function tconv( s : std_ulogic ) return integer; + function tconv( s : std_ulogic ) return std_ulogic_vector; +-- synopsys translate_off + function tconv( s : std_ulogic ) return character; + function tconv( s : std_ulogic ) return string; +-- synopsys translate_on + + -- std_ulogic_vector to other types + function tconv( s : std_ulogic_vector ) return bit_vector; + function tconv( s : std_ulogic_vector ) return std_logic_vector; + function tconv( s : std_ulogic_vector ) return integer; + function tconv( s : std_ulogic_vector ) return std_ulogic; +-- synopsys translate_off + function tconv( s : std_ulogic_vector ) return string; + function tconv( s : std_ulogic_vector; base : base_t ) return string; +-- synopsys translate_on + + -- std_logic_vector to other types +-- function tconv( s : std_logic_vector ) return bit_vector; +-- function tconv( s : std_logic_vector ) return std_ulogic_vector; +-- function tconv( s : std_logic_vector ) return integer; +-- synopsys translate_off +-- function tconv( s : std_logic_vector ) return string; +-- function tconv( s : std_logic_vector; base : base_t ) return string; +-- synopsys translate_on + +-- synopsys translate_off + function hexstring( d : std_ulogic_vector ) return string ; + function octstring( d : std_ulogic_vector ) return string ; + function bitstring( d : std_ulogic_vector ) return string ; +-- synopsys translate_on + + ------------------------------------------------------------------- + -- HIS ATTRIBUTEs for Type Conversion Functions + ------------------------------------------------------------------- +-- Synopsys translate_off + attribute type_convert of tconv : function is true; + + ------------------------------------------------------------------- + -- synthesis ATTRIBUTEs for Type Conversion Functions + ------------------------------------------------------------------- + + attribute btr_name of tconv : function is "PASS"; + attribute pin_bit_information of tconv : function is + (1 => (" ","A0 ","INCR","PIN_BIT_SCALAR"), + 2 => (" ","10 ","INCR","PIN_BIT_SCALAR")); +-- Synopsys translate_on + + --============================================================================ + -- Match Functions + --============================================================================ + + function std_match (l, r: std_ulogic) return std_ulogic; + function std_match (l, r: std_ulogic_vector) return std_ulogic; + +-- Synopsys translate_off + attribute functionality of std_match : function is "="; + attribute dc_allow of std_match : function is true; +-- Synopsys translate_on +--============================================================== + -- Shift and Rotate Functions +--============================================================== + + -- Id: S.1 + function shift_left (arg: std_ulogic_vector; count: natural) return std_ulogic_vector; + -- Result subtype: std_ulogic_vector(ARG'LENGTH-1 downto 0) + -- Result: Performs a shift-left on an std_ulogic_vector vector COUNT times. + -- The vacated positions are filled with '0'. + -- The COUNT leftmost elements are lost. + + -- Id: S.2 + function shift_right (arg: std_ulogic_vector; count: natural) return std_ulogic_vector; + -- Result subtype: std_ulogic_vector(ARG'LENGTH-1 downto 0) + -- Result: Performs a shift-right on an std_ulogic_vector vector COUNT times. + -- The vacated positions are filled with '0'. + -- The COUNT rightmost elements are lost. + + -- Id: S.5 + function rotate_left (arg: std_ulogic_vector; count: natural) return std_ulogic_vector; + -- Result subtype: std_ulogic_vector(ARG'LENGTH-1 downto 0) + -- Result: Performs a rotate-left of an std_ulogic_vector vector COUNT times. + + -- Id: S.6 + function rotate_right (arg: std_ulogic_vector; count: natural) return std_ulogic_vector; + -- Result subtype: std_ulogic_vector(ARG'LENGTH-1 downto 0) + -- Result: Performs a rotate-right of an std_ulogic_vector vector COUNT times. + + -- Id: S.9 + function "sll" (arg: std_ulogic_vector; count: integer) return std_ulogic_vector; + -- Result subtype: std_ulogic_vector(ARG'LENGTH-1 downto 0) + -- Result: SHIFT_LEFT(ARG, COUNT) + + -- Id: S.11 + function "srl" (arg: std_ulogic_vector; count: integer) return std_ulogic_vector; + -- Result subtype: std_ulogic_vector(ARG'LENGTH-1 downto 0) + -- Result: SHIFT_RIGHT(ARG, COUNT) + + -- Id: S.13 + function "rol" (arg: std_ulogic_vector; count: integer) return std_ulogic_vector; + -- Result subtype: std_ulogic_vector(ARG'LENGTH-1 downto 0) + -- Result: ROTATE_LEFT(ARG, COUNT) + + -- Id: S.15 + function "ror" (arg: std_ulogic_vector; count: integer) return std_ulogic_vector; + -- Result subtype: std_ulogic_vector(ARG'LENGTH-1 downto 0) + -- Result: ROTATE_RIGHT(ARG, COUNT) + --=========================================================== + --End shift and rotate functions............................. + --=========================================================== +end std_ulogic_support ; + +package body std_ulogic_support is + + ------------------------------------------------------------------- + -- Look Up tables for operator overloading + ------------------------------------------------------------------- + -- Types used for overloaded operator lookup tables + ------------------------------------------------------------------- + +-- Synopsys synthesis_off + type std_ulogic_to_character_type is array( std_ulogic ) of character; + + constant std_ulogic_to_character : std_ulogic_to_character_type := + ( 'U','X','0','1','Z','W','L','H','-'); + + type stdlogic_2d is array ( std_ulogic, std_ulogic ) of std_ulogic; + type b_stdlogic_2d is array ( std_ulogic, std_ulogic ) of boolean; +-- Synopsys synthesis_on + ------------------------------------------------------------------- + -- Logic operation lookup tables + ------------------------------------------------------------------- +-- Synopsys synthesis_off + -- LessThan Logic Operator + + constant lt_table : stdlogic_2D := ( + -- RHS U X 0 1 Z W L H - | + -- LHS ---------------------------------------------------+--- + ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U + ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X + ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 + ( 'U', 'X', '0', '0', 'X', 'X', '0', '0', 'X' ), -- | 1 + ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z + ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W + ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L + ( 'U', 'X', '0', '0', 'X', 'X', '0', '0', 'X' ), -- | H + ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | - + others=>(others=>'-') + ); + + constant b_lt_table : b_stdlogic_2D := ( + 'U'=>( others=>false ), + 'X'=>( others=>false ), + '0'=>( '1'=>true, 'H'=>true, others=>false ), + '1'=>( others=>false ), + 'Z'=>( others=>false ), + 'W'=>( others=>false ), + 'L'=>( '1'=>true, 'H'=>true, others=>false ), + 'H'=>( others=>false ), + '-'=>( others=>false ), + others=>( others=>false ) + ); + + -- LessThanorEqual Logic Operator + + constant le_table : stdlogic_2D := ( + -- RHS U X 0 1 Z W L H - | + -- LHS ---------------------------------------------------+--- + ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U + ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X + ( 'U', 'X', '1', '1', 'X', 'X', '1', '1', 'X' ), -- | 0 + ( 'U', 'X', '0', '0', 'X', 'X', '0', '0', 'X' ), -- | 1 + ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z + ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W + ( 'U', 'X', '1', '1', 'X', 'X', '0', '1', 'X' ), -- | L + ( 'U', 'X', '0', '0', 'X', 'X', '0', '0', 'X' ), -- | H + ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | - + others=>(others=>'-') + ); + + constant b_le_table : b_stdlogic_2D := ( + -- RHS => - 0 U X 1 Z W L H + -- LHS -------------------------------------------------------------------------------------------------- + 'U'=>( others=>false ), + 'X'=>( others=>false ), + '0'=>( '0'=>true, '1'=>true, 'L'=>true, 'H'=>true, others=>false ), + '1'=>( '1'=>true, 'H'=>true, others=>false ), + 'Z'=>( others=>false ), + 'W'=>( others=>false ), + 'L'=>( '0'=>true, '1'=>true, 'L'=>true, 'H'=>true, others=>false ), + 'H'=>( '1'=>true, 'H'=>true, others=>false ), + '-'=>( others=>false ), + others=>( others=>false ) + ); + + -- GreaterThan Logic Operator + + constant gt_table : stdlogic_2D := ( + -- RHS U X 0 1 Z W L H - | + -- LHS ---------------------------------------------------+--- + ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U + ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X + ( 'U', 'X', '0', '0', 'X', 'X', '0', '0', 'X' ), -- | 0 + ( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 1 + ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z + ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W + ( 'U', 'X', '0', '0', 'X', 'X', '0', '0', 'X' ), -- | L + ( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | H + ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | - + others=>(others=>'-') + ); + + constant b_gt_table : b_stdlogic_2D := ( + -- LHS => ( RHS ) + 'U'=>( others=>false ), + 'X'=>( others=>false ), + '0'=>( others=>false ), + '1'=>( '0'=>true, 'L'=>true, others=>false ), + 'Z'=>( others=>false ), + 'W'=>( others=>false ), + 'L'=>( others=>false ), + 'H'=>( '0'=>true, 'L'=>true, others=>false ), + '-'=>( others=>false ), + others=>(others=>false)); + + -- GreaterThanorEqual Logic Operator + + constant ge_table : stdlogic_2D := ( + -- RHS U X 0 1 Z W L H - | + -- LHS ---------------------------------------------------+--- + ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U + ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X + ( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 0 + ( 'U', 'X', '1', '1', 'X', 'X', '1', '1', 'X' ), -- | 1 + ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z + ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W + ( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | L + ( 'U', 'X', '1', '1', 'X', 'X', '1', '1', 'X' ), -- | H + ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | - + others=>(others=>'-') + ); + + constant b_ge_table : b_stdlogic_2D := ( + -- RHS => - 0 U X 1 Z W L H + -- LHS -------------------------------------------------------------------------------------------------- + 'U'=>( others=>false ), + 'X'=>( others=>false ), + '0'=>( '0'=>true, 'L'=>true, others=>false ), + '1'=>( '0'=>true, '1'=>true, 'L'=>true, 'H'=>true, others=>false ), + 'Z'=>( others=>false ), + 'W'=>( others=>false ), + 'L'=>( '0'=>true, 'L'=>true, others=>false ), + 'H'=>( '0'=>true, '1'=>true, 'L'=>true, 'H'=>true, others=>false ), + '-'=>( others=>false ), + others=>( others=>false ) + ); +-- Synopsys synthesis_on + + ------------------------------------------------------------------- + -- Relational Functions returning Boolean + ------------------------------------------------------------------- + + function eq( l,r : std_ulogic ) return boolean is + begin + return std_match( l, r ); + end eq; + + function ne( l,r : std_ulogic ) return boolean is + begin + return not( std_match( l, r ) ); + end ne; + + function gt( l,r : std_ulogic ) return boolean is + variable result : boolean; + -- pragma built_in SYN_GT + begin + -- Synopsys translate_off + assert ( l /= '-' ) and ( r /= '-' ) + report "Invalid dont_care in relational function" + severity error; + result := b_gt_table( l, r ); + -- Synopsys translate_on + return result; + end gt; + + function ge( l,r : std_ulogic ) return boolean is + variable result : boolean; + -- pragma built_in SYN_GEQ + begin + -- synopsys translate_off + assert ( l /= '-' ) and ( r /= '-' ) + report "Invalid dont_care in relational function" + severity error; + result := b_ge_table( l, r ); + -- synopsys translate_on + return result; + end ge; + + function lt( l,r : std_ulogic ) return boolean is + variable result : boolean; + -- pragma built_in SYN_LT + begin + -- synopsys translate_off + assert ( l /= '-' ) and ( r /= '-' ) + report "Invalid dont_care in relational function" + severity error; + result := b_lt_table( l, r ); + -- synopsys translate_on + return result; + end lt; + + function le( l,r : std_ulogic ) return boolean is + variable result : boolean; + -- pragma built_in SYN_LEQ + begin + -- synopsys translate_off + assert ( l /= '-' ) and ( r /= '-' ) + report "Invalid dont_care in relational function" + severity error; + result := b_le_table( l, r ); + -- synopsys translate_on + return result; + end le; + + ------------------------------------------------------------------- + -- Relational Functions returning std_ulogic + ------------------------------------------------------------------- + + function eq( l,r : std_ulogic ) return std_ulogic is + begin + return std_match( l, r ); + end eq; + + function ne( l,r : std_ulogic ) return std_ulogic is + begin + return not std_match( l, r ) ; + end ne; + + function gt( l,r : std_ulogic ) return std_ulogic is + variable result : std_ulogic; + -- pragma built_in SYN_GT + begin + -- Synopsys translate_off + assert ( l /= '-' ) and ( r /= '-' ) + report "Invalid dont_care in relational function" + severity error; + result := gt_table( l, r ); + -- synopsys translate_on + return result; + end gt; + + function ge( l,r : std_ulogic ) return std_ulogic is + variable result : std_ulogic; + -- pragma built_in SYN_GEQ + begin + -- Synopsys translate_off + assert ( l /= '-' ) and ( r /= '-' ) + report "Invalid dont_care in relational function" + severity error; + result := ge_table( l, r ); + -- Synopsys translate_on + return result; + end ge; + + function lt( l,r : std_ulogic ) return std_ulogic is + variable result : std_ulogic; + -- pragma built_in SYN_LT + begin + -- Synopsys translate_off + assert ( l /= '-' ) and ( r /= '-' ) + report "Invalid dont_care in relational function" + severity error; + result := lt_table( l, r ); + -- Synopsys translate_on + return result; + end lt; + + function le( l,r : std_ulogic ) return std_ulogic is + variable result : std_ulogic; + -- pragma built_in SYN_LEQ + begin + -- Synopsys translate_off + assert ( l /= '-' ) and ( r /= '-' ) + report "Invalid dont_care in relational function" + severity error; + result := le_table( l, r ); + -- Synopsys translate_on + return result; + end le; + + -- + -- utility function get rid of most meta values + -- + function to_x01d( d : std_ulogic ) return std_ulogic is + -- pragma built_in SYN_FEED_THRU + variable result : std_ulogic; + begin + -- Synopsys translate_off + case d is + when '0' | 'L' => result := '0'; + when '1' | 'H' => result := '1'; + when '-' => result := '-'; + when others => result := 'X'; + end case; + -- Synopsys translate_on + return result; + end to_x01d; + + ------------------------------------------------------------------- + -- Vectored Relational Functions returning Boolean + ------------------------------------------------------------------- + function eq( l,r : std_ulogic_vector) return boolean is + variable result : boolean ; + begin + result := std_match(l,r); + return result; + end eq; + + --------------------------------------------------------------------- + function ne( l,r : std_ulogic_vector) return boolean is + variable result : boolean ; + begin + result := not std_match(l,r); + return result; + end ne; + + ------------------------------------------------------------------- + function gt( l,r : std_ulogic_vector) return boolean is + variable result : boolean ; + begin + result := unsigned(l) > unsigned(r); + return result; + end gt; + + ------------------------------------------------------------------- + function ge( l,r : std_ulogic_vector) return boolean is + variable result : boolean ; + begin + result := unsigned(l) >= unsigned(r); + return result; + end ge; + + ------------------------------------------------------------------- + function lt( l,r : std_ulogic_vector) return boolean is + variable result : boolean ; + begin + result := unsigned(l) < unsigned(r); + return result; + end lt; + + ------------------------------------------------------------------- + function le( l,r : std_ulogic_vector) return boolean is + variable result : boolean ; + begin + result := unsigned(l) <= unsigned(r); + return result; + end le; + + ------------------------------------------------------------------- + -- vectored relational functions returning std_ulogic + ------------------------------------------------------------------- + function eq( l,r : std_ulogic_vector) return std_ulogic is + variable result : std_ulogic ; + begin + result := std_match( l, r ) ; + --result := (l ?= r); + return result; + end eq; + --------------------------------------------------------------------- + function ne( l,r : std_ulogic_vector) return std_ulogic is + variable result :std_ulogic ; + begin + result := not std_match( l, r ) ; + --result := not (l ?= r); + return result; + end ne; + + ------------------------------------------------------------------- + function gt( l,r : std_ulogic_vector) return std_ulogic is + variable result : boolean ; + -- pragma built_in SYN_GT + begin + result := unsigned(l) > unsigned(r); + if (result = true ) then + return '1' ; + else + return '0'; + end if ; + end gt; + + ------------------------------------------------------------------- + function ge( l,r : std_ulogic_vector) return std_ulogic is + variable result : boolean ; + -- pragma built_in SYN_GEQ + begin + result := unsigned(l) >= unsigned(r); + if (result = true ) then + return '1' ; + else + return '0'; + end if ; + end ge; + + ------------------------------------------------------------------- + function lt( l,r : std_ulogic_vector) return std_ulogic is + variable result : boolean ; + -- pragma built_in SYN_LT + begin + result := unsigned(l) < unsigned(r); + if (result = true ) then + return '1' ; + else + return '0'; + end if ; + end lt; + + ------------------------------------------------------------------- + function le( l,r : std_ulogic_vector) return std_ulogic is + variable result : boolean ; + -- pragma built_in SYN_LEQ + begin + result := unsigned(l) <= unsigned(r); + if (result = true ) then + return '1' ; + else + return '0'; + end if ; + end le; + + ------------------------------------------------------------------- + -- Type Conversion Functions + ------------------------------------------------------------------- + ------------------------------------------------------------------- + -- Boolean Conversions + ------------------------------------------------------------------- + function tconv ( b : boolean ) return bit is + -- pragma built_in SYN_FEED_THRU + begin + case b is + when false => return('0'); + when true => return('1'); + end case; + end tconv ; + +-- Synopsys translate_off + function tconv ( b : boolean ) return string is + begin + case b is + when false => return("FALSE"); + when true => return("TRUE"); + end case; + end tconv ; +-- Synopsys translate_on + + function tconv ( b : boolean ) return std_ulogic is + -- pragma built_in SYN_FEED_THRU + begin + case b is + when false => return('0'); + when true => return('1'); + end case; + end tconv ; + + ------------------------------------------------------------------- + -- Bit Conversions + ------------------------------------------------------------------- + function tconv ( b : bit ) return boolean is + -- pragma built_in SYN_FEED_THRU + begin + case b is + when '0' => return(false); + when '1' => return(true); + end case; + end tconv ; + +-- Synopsys translate_off + function tconv ( b : bit ) return character is + begin + case b is + when '0' => return('0'); + when '1' => return('1'); + end case; + end tconv ; + + function tconv ( b : bit ) return string is + begin + case b is + when '0' => return("0"); + when '1' => return("1"); + end case; + end tconv ; +-- Synopsys translate_on + + function tconv ( b : bit ) return integer is + -- pragma built_in SYN_UNSIGNED_TO_INTEGER + begin + case b is + when '0' => return(0); + when '1' => return(1); + end case; + end tconv ; + + function tconv ( b : bit ) return std_ulogic is + -- pragma built_in SYN_FEED_THRU + begin + case b is + when '0' => return('0'); + when '1' => return('1'); + end case; + end tconv ; + + ------------------------------------------------------------------- + -- Bit_vector Conversions + ------------------------------------------------------------------- + function tconv ( b : bit_vector ) return integer is + variable int_result : integer ; + variable int_exp : integer ; + variable new_value : bit_vector(1 to b'length); + -- pragma built_in SYN_UNSIGNED_TO_INTEGER + begin + -- Synopsys translate_off + int_result := 0; + int_exp := 0; + new_value := b; + for i in new_value'length to 1 loop + if b(i)='1' then + int_result := int_result + (2**int_exp); + end if; + int_exp := int_exp + 1; + end loop; + -- synopsys translate_on + return int_result; + end tconv ; + +-- Synopsys translate_off + function tconv ( b : bit_vector ) return string is + alias sv : bit_vector ( 1 to b'length ) is b; + variable result : string ( 1 to b'length ); + begin + result := (others => '0'); + for i in result'range loop + case sv(i) is + when '0' => result(i) := '0'; + when '1' => result(i) := '1'; + end case; + end loop; + return result; + end tconv ; +-- Synopsys translate_on + +-- Synopsys translate_off + function tconv ( b : bit_vector; base : base_t ) return string is + alias sv : bit_vector ( 1 to b'length ) is b; + variable result : string ( 1 to b'length ); + variable start : positive; + variable extra : natural; + variable resultlength : positive; + subtype bv is bit_vector( 1 to 1 ); + subtype qv is bit_vector( 1 to 2 ); + subtype ov is bit_vector( 1 to 3 ); + subtype hv is bit_vector( 1 to 4 ); + begin + case base is + when bin => + resultlength := sv'length; + start := 1; + for i in start to resultlength loop + case sv( i ) is + when '0' => result( i ) := '0'; + when '1' => result( i ) := '1'; + end case; + end loop; + + when oct => + extra := sv'length rem ov'length; + case extra is + when 0 => + resultlength := b'length/ov'length; + start := 1; + when 1 => + resultlength := ( b'length/ov'length ) + 1; + start := 2; + case sv( 1 ) is + when '0' => result( 1 ) := '0'; + when '1' => result( 1 ) := '1'; + end case; + when 2 => + resultlength := ( b'length/ov'length ) + 1; + start := 2; + case qv'( sv( 1 to 2 ) ) is + when "00" => result( 1 ) := '0'; + when "01" => result( 1 ) := '1'; + when "10" => result( 1 ) := '2'; + when "11" => result( 1 ) := '3'; + end case; + when others => + assert false report "TCONV fatal condition" severity failure; + end case; + + for i in 0 to resultLength - start loop + case ov'( SV( (ov'length*i)+(extra+1) to (ov'length*i)+(extra+3) ) ) is + when "000" => result( i+start ) := '0'; + when "001" => result( i+start ) := '1'; + when "010" => result( i+start ) := '2'; + when "011" => result( i+start ) := '3'; + when "100" => result( i+start ) := '4'; + when "101" => result( i+start ) := '5'; + when "110" => result( i+start ) := '6'; + when "111" => result( i+start ) := '7'; + when others => result( i+start ) := '.'; + end case; + end loop; + + when hex => + extra := b'length rem hv'length; + case extra is + when 0 => + resultLength := b'length/hv'length; + start := 1; + when 1 => + resultLength := ( b'length/hv'length ) + 1; + start := 2; + case sv( 1 ) is + when '0' => result( 1 ) := '0'; + when '1' => result( 1 ) := '1'; + end case; + when 2 => + resultLength := ( b'length/hv'length ) + 1; + start := 2; + case qv'( sv( 1 to 2 ) ) is + when "00" => result( 1 ) := '0'; + when "01" => result( 1 ) := '1'; + when "10" => result( 1 ) := '2'; + when "11" => result( 1 ) := '3'; + end case; + when 3 => + resultLength := ( b'length/hv'length ) + 1; + start := 2; + case ov'( sv( 1 to 3 ) ) is + when o"0" => result( 1 ) := '0'; + when o"1" => result( 1 ) := '1'; + when o"2" => result( 1 ) := '2'; + when o"3" => result( 1 ) := '3'; + when o"4" => result( 1 ) := '4'; + when o"5" => result( 1 ) := '5'; + when o"6" => result( 1 ) := '6'; + when o"7" => result( 1 ) := '7'; + end case; + when others => + assert false report "TCONV fatal condition" severity failure; + end case; + + for i in 0 to resultLength - start loop + case hv'( SV( (hv'length*i)+(extra+1) to (hv'length*i)+(extra+4) ) ) is + when "0000" => result( i+start ) := '0'; + when "0001" => result( i+start ) := '1'; + when "0010" => result( i+start ) := '2'; + when "0011" => result( i+start ) := '3'; + when "0100" => result( i+start ) := '4'; + when "0101" => result( i+start ) := '5'; + when "0110" => result( i+start ) := '6'; + when "0111" => result( i+start ) := '7'; + when "1000" => result( i+start ) := '8'; + when "1001" => result( i+start ) := '9'; + when "1010" => result( i+start ) := 'A'; + when "1011" => result( i+start ) := 'B'; + when "1100" => result( i+start ) := 'C'; + when "1101" => result( i+start ) := 'D'; + when "1110" => result( i+start ) := 'E'; + when "1111" => result( i+start ) := 'F'; + when others => result( i+start ) := '.'; + end case; + end loop; + + when others => + assert false report "Unsupported base passed." severity warning; + + end case; + + return result( 1 to resultLength ); + end tconv ; +-- Synopsys translate_on + + function tconv ( b : bit_vector ) return std_ulogic_vector is + alias sv : bit_vector ( 1 to b'length ) is b; + variable result : std_ulogic_vector ( 1 to b'length ); + -- pragma built_in SYN_FEED_THRU + begin + for i in result'range loop + case sv(i) is + when '0' => result(i) := '0'; + when '1' => result(i) := '1'; + end case; + end loop; + return result; + end tconv ; + + --function tconv ( b : bit_vector ) return std_logic_vector is + -- alias sv : bit_vector ( 1 to b'length ) is b; + -- variable result : std_logic_vector ( 1 to b'length ); + ---- pragma built_in SYN_FEED_THRU + --begin + -- for i in result'range loop + -- case sv(i) is + -- when '0' => result(i) := '0'; + -- when '1' => result(i) := '1'; + -- end case; + -- end loop; + -- return result; + --end tconv ; + + ------------------------------------------------------------------- + -- Integer conversion to other types + ------------------------------------------------------------------- + function tconv ( n : integer;w : positive) return bit_vector is + variable result : bit_vector(w-1 downto 0) ; + variable ib : integer; + variable test : integer; + -- pragma built_in SYN_INTEGER_TO_UNSIGNED + begin + if n < 0 then + result := (others => '0'); + else + ib := n; + result := (others => '0'); + for i in result'reverse_range loop + exit when ib = 0; + test := ib rem 2; + if test = 1 then + result(i) := '1'; + else + result(i) := '0'; + end if; + ib := ib / 2; + end loop; + end if; + -- synopsys translate_off + assert n >= 0 + report "tconv: n < 0 is not permitted" + severity warning; + assert ib = 0 + report "tconv: integer overflows requested result width" + severity warning; + -- synopsys translate_on + return result; + end tconv; + + function tconv ( n : integer; w : positive) return std_ulogic_vector is + variable result : std_ulogic_vector(w-1 downto 0) ; + variable ib : integer; + variable test : integer; + -- pragma built_in SYN_INTEGER_TO_UNSIGNED + begin + if n < 0 then + result := (others => 'X'); + else + ib := n; + result := (others => '0'); + for i in result'reverse_range loop + exit when ib = 0; + test := ib rem 2; + if test = 1 then + result(i) := '1'; + else + result(i) := '0'; + end if; + ib := ib / 2; + end loop; + end if; + -- Synopsys translate_off + assert n >= 0 + report "tconv: n < 0 is not permitted" + severity warning; + assert ib = 0 + report "tconv: integer overflows requested result width" + severity warning; + -- Synopsys translate_on + return result; + end tconv; + +-- Synopsys translate_off + function tconv ( n : integer; w : positive ) return string is + subtype digit is integer range 0 to 9; + variable result : string( 1 to w ) ; + variable ib : integer; + variable msd : integer; + variable sign : character := '-'; + variable test : digit; + begin + ib := abs n; + for i in result'reverse_range loop + test := ib rem 10; + + case test is + when 0 => result(i) := '0'; + when 1 => result(i) := '1'; + when 2 => result(i) := '2'; + when 3 => result(i) := '3'; + when 4 => result(i) := '4'; + when 5 => result(i) := '5'; + when 6 => result(i) := '6'; + when 7 => result(i) := '7'; + when 8 => result(i) := '8'; + when 9 => result(i) := '9'; + end case; + + ib := ib / 10; + + exit when ib = 0; + end loop; + + if ib < 0 then + result(1) := sign; + end if; + + assert + not( ( ( ib < 0 ) and ( ( abs ib ) > ( 10**(w-1) - 1 ) ) ) or + ( ( ib >= 0 ) and ( ib > ( 10**w - 1 ) ) ) ) + report "tconv: integer overflows requested result width" + severity warning; + + return result; + end tconv; +-- Synopsys translate_on + +-- Synopsys translate_off + function tconv ( n : integer) return string is + subtype digit is integer range 0 to 9; + variable result : string( 1 to 10 ) ; + variable ib : integer; + variable msd : integer; + variable sign : character := '-'; + variable test : digit; + begin + ib := abs n ; + for i in result'reverse_range loop + test := ib rem 10; + case test is + when 0 => result(i) := '0'; + when 1 => result(i) := '1'; + when 2 => result(i) := '2'; + when 3 => result(i) := '3'; + when 4 => result(i) := '4'; + when 5 => result(i) := '5'; + when 6 => result(i) := '6'; + when 7 => result(i) := '7'; + when 8 => result(i) := '8'; + when 9 => result(i) := '9'; + end case; + ib := ib / 10; + if ib = 0 then + msd := i; + exit; + end if; + end loop; + if ib < 0 then + return sign & result(msd to 10); + else + return result(msd to 10); + end if; + end tconv; +-- Synopsys translate_on + + ------------------------------------------------------------------- + -- String conversion to other types + ------------------------------------------------------------------- +-- Synopsys translate_off + function TConv ( s : string ) return integer is + variable result : integer ; + alias si : string( s'length downto 1 ) is s; + variable invalid : boolean ; + begin + invalid := false ; + for i in si'range loop + case si( i ) is + when '0' => null; + when '1' => result := result + 10 ** ( i - 1 ) ; + when '2' => result := result + 2 * 10 ** ( i - 1 ) ; + when '3' => result := result + 3 * 10 ** ( i - 1 ) ; + when '4' => result := result + 4 * 10 ** ( i - 1 ) ; + when '5' => result := result + 5 * 10 ** ( i - 1 ) ; + when '6' => result := result + 6 * 10 ** ( i - 1 ) ; + when '7' => result := result + 7 * 10 ** ( i - 1 ) ; + when '8' => result := result + 8 * 10 ** ( i - 1 ) ; + when '9' => result := result + 9 * 10 ** ( i - 1 ) ; + when others => invalid := true; + end case; + end loop; + assert not invalid + report "String contained characters other than 0 thru 9" & + "; treating invalid characters as 0's" + severity warning; + return result; + end tconv; +-- Synopsys translate_on + +-- Synopsys translate_off + function tconv ( s : string; base : base_t ) return integer is + alias sv : string ( s'length downto 1 ) is s; + variable result : integer ; + variable invalid : boolean ; + variable vc_len : integer ; + variable validchars : string(1 to 20) := "0 thru 9 or A thru F"; + begin + invalid := false ; + case base is + when bin => + vc_len := 6; + validchars(1 to 6) := "0 or 1"; + for i in sv'range loop + case sv( i ) is + when '0' => null; + when '1' => result := result + 2 ** ( i - 1 ) ; + when others => invalid := true; + end case; + end loop; + + when oct => + vc_len := 8; + validchars(1 to 8) := "0 thru 7"; + for i in sv'range loop + case sv( i ) is + when '0' => null; + when '1' => result := result + 8 ** ( i - 1 ) ; + when '2' => result := result + 2 * 8 ** ( i - 1 ) ; + when '3' => result := result + 3 * 8 ** ( i - 1 ) ; + when '4' => result := result + 4 * 8 ** ( i - 1 ) ; + when '5' => result := result + 5 * 8 ** ( i - 1 ) ; + when '6' => result := result + 6 * 8 ** ( i - 1 ) ; + when '7' => result := result + 7 * 8 ** ( i - 1 ) ; + when others => invalid := true; + end case; + end loop; + + when dec => + vc_len := 8; + validchars(1 to 8) := "0 thru 9"; + for i in sv'range loop + case sv( i ) is + when '0' => null; + when '1' => result := result + 10 ** ( i - 1 ) ; + when '2' => result := result + 2 * 10 ** ( i - 1 ) ; + when '3' => result := result + 3 * 10 ** ( i - 1 ) ; + when '4' => result := result + 4 * 10 ** ( i - 1 ) ; + when '5' => result := result + 5 * 10 ** ( i - 1 ) ; + when '6' => result := result + 6 * 10 ** ( i - 1 ) ; + when '7' => result := result + 7 * 10 ** ( i - 1 ) ; + when '8' => result := result + 8 * 10 ** ( i - 1 ) ; + when '9' => result := result + 9 * 10 ** ( i - 1 ) ; + when others => invalid := true; + end case; + end loop; + + when hex => + for i in sv'range loop + case sv( i ) is + when '0' => null; + when '1' => result := result + 16 ** ( i - 1 ) ; + when '2' => result := result + 2 * 16 ** ( i - 1 ) ; + when '3' => result := result + 3 * 16 ** ( i - 1 ) ; + when '4' => result := result + 4 * 16 ** ( i - 1 ) ; + when '5' => result := result + 5 * 16 ** ( i - 1 ) ; + when '6' => result := result + 6 * 16 ** ( i - 1 ) ; + when '7' => result := result + 7 * 16 ** ( i - 1 ) ; + when '8' => result := result + 8 * 16 ** ( i - 1 ) ; + when '9' => result := result + 9 * 16 ** ( i - 1 ) ; + when 'A' | 'a' => result := result + 10 * 16 ** ( i - 1 ) ; + when 'B' | 'b' => result := result + 11 * 16 ** ( i - 1 ) ; + when 'C' | 'c' => result := result + 12 * 16 ** ( i - 1 ) ; + when 'D' | 'd' => result := result + 13 * 16 ** ( i - 1 ) ; + when 'E' | 'e' => result := result + 14 * 16 ** ( i - 1 ) ; + when 'F' | 'f' => result := result + 15 * 16 ** ( i - 1 ) ; + when others => invalid := true; + end case; + end loop; + + when others => + assert false report "Unsupported base passed." severity warning; + + end case; + + assert not invalid + report "String contained characters other than " & + validchars(1 to vc_len) & "; treating invalid characters as 0's" + severity warning; + + return result; + end; +-- Synopsys translate_on + +-- Synopsys translate_off + function tconv ( s : string ) return bit is + variable result : bit; + alias si : string( 1 to s'length ) is s; + variable invalid : boolean := false; + begin + assert s'length = 1 + report "String conversion to bit longer that 1 character" + severity warning; + case si(1) is + when '0' => result := '0'; + when '1' => result := '1'; + when others => + invalid := true; + result := '0'; + end case; + assert not invalid + report "String contained characters other than 0 or 1; " & + "treating invalid characters as 0's" + severity warning; + return result; + end tconv; +-- Synopsys translate_on + +-- Synopsys translate_off + function tconv ( s : string ) return bit_vector is + variable result : bit_vector( 1 to s'length ); + alias si : string( 1 to s'length ) is s; + variable invalid : boolean := false; + begin + for i in si'range loop + case si(i) is + when '0' => result( i ) := '0'; + when '1' => result( i ) := '1'; + when others => + invalid := true; + result( i ) := '0'; + end case; + end loop; + assert not invalid + report "String contained characters other than 0 or 1; " & + "treating invalid characters as 0's" + severity warning; + return result( 1 to result'length ); + end tconv; +-- Synopsys translate_on + +-- Synopsys translate_off + function tconv ( s : string; base : base_t ) return bit_vector is + variable result : bit_vector( 1 to 4*s'length ); + alias si : string( 1 to s'length ) is s; + variable invalid : boolean := false; + begin + case base is + when bin => + for i in si'range loop + case si(i) is + when '0' => result( i ) := '0'; + when '1' => result( i ) := '1'; + when others => + invalid := true; + result( i ) := '0'; + end case; + end loop; + assert not invalid + report "String contained characters other than 0 or 1; " & + "treated invalid characters as 0's" + severity warning; + return result(1 to s'length) ; + + when oct => + for i in si'range loop + case si(i) is + when '0' => result( (3*i)-2 to 3*i ) := o"0"; + when '1' => result( (3*i)-2 to 3*i ) := o"1"; + when '2' => result( (3*i)-2 to 3*i ) := o"2"; + when '3' => result( (3*i)-2 to 3*i ) := o"3"; + when '4' => result( (3*i)-2 to 3*i ) := o"4"; + when '5' => result( (3*i)-2 to 3*i ) := o"5"; + when '6' => result( (3*i)-2 to 3*i ) := o"6"; + when '7' => result( (3*i)-2 to 3*i ) := o"7"; + when others => + invalid := true; + result( (3*i)-2 to 3*i ) := o"0"; + end case; + end loop; + assert not invalid + report "String contained characters other than 0 through 7; " & + "treated invalid characters as 0's" + severity warning; + return result( 1 to 3*s'length ); + + when hex => + for i in si'range loop + case si(i) is + when '0' => result( (4*i)-3 to 4*i ) := x"0"; + when '1' => result( (4*i)-3 to 4*i ) := x"1"; + when '2' => result( (4*i)-3 to 4*i ) := x"2"; + when '3' => result( (4*i)-3 to 4*i ) := x"3"; + when '4' => result( (4*i)-3 to 4*i ) := x"4"; + when '5' => result( (4*i)-3 to 4*i ) := x"5"; + when '6' => result( (4*i)-3 to 4*i ) := x"6"; + when '7' => result( (4*i)-3 to 4*i ) := x"7"; + when '8' => result( (4*i)-3 to 4*i ) := x"8"; + when '9' => result( (4*i)-3 to 4*i ) := x"9"; + when 'A' | 'a' => result( (4*i)-3 to 4*i ) := x"A"; + when 'B' | 'b' => result( (4*i)-3 to 4*i ) := x"B"; + when 'C' | 'c' => result( (4*i)-3 to 4*i ) := x"C"; + when 'D' | 'd' => result( (4*i)-3 to 4*i ) := x"D"; + when 'E' | 'e' => result( (4*i)-3 to 4*i ) := x"E"; + when 'F' | 'f' => result( (4*i)-3 to 4*i ) := x"F"; + when others => + invalid := true; + result( (4*i)-3 to 4*i ) := x"0"; + end case; + end loop; + assert not invalid + report "String contained characters other than 0 through 9 or " & + "A through F; " & + "treated invalid characters as 0's" + severity warning; + return result( 1 to 4*s'length ); + + when others => + assert false report "Unsupported base passed." severity warning; + return result ; + + end case; + end tconv; +-- Synopsys translate_on + +-- Synopsys translate_off + function tconv ( s : string ) return std_ulogic is + variable result : std_ulogic; + alias si : string( 1 to s'length ) is s; + variable invalid : boolean := false; + begin + assert s'length = 1 + report "String conversion to bit longer that 1 character" + severity warning; + case si(1) is + when '0' => result := '0'; + when '1' => result := '1'; + when others => + invalid := true; + result := 'X'; + end case; + assert not invalid + report "String contained characters other than 0 or 1; " & + "treating invalid characters as X's" + severity warning; + return result; + end tconv; +-- Synopsys translate_on + +-- Synopsys translate_off + function tconv ( s : string ) return std_ulogic_vector is + variable result : std_ulogic_vector( 1 to s'length ); + alias si : string( 1 to s'length ) is s; + variable invalid : boolean := false; + begin + for i in si'range loop + case si(i) is + when '0' => result( i ) := '0'; + when '1' => result( i ) := '1'; + when others => + invalid := true; + result( i ) := 'X'; + end case; + end loop; + assert not invalid + report "String contained characters other than 0 or 1; " & + "treating invalid characters as X's" + severity warning; + return result( 1 to result'length ); + end tconv; +-- Synopsys translate_on + +-- Synopsys translate_off + function tconv ( s : string; base : base_t ) return std_ulogic_vector is + variable result : std_ulogic_vector( 1 to 4*s'length ); + alias si : string( 1 to s'length ) is s; + variable invalid : boolean := false; + begin + case base is + when bin => + for i in si'range loop + case si(i) is + when '0' => result( i ) := '0'; + when '1' => result( i ) := '1'; + when others => + invalid := true; + result( i ) := '0'; + end case; + end loop; + assert not invalid + report "String contained characters other than 0 or 1; " & + "treated invalid characters as 0's" + severity warning; + return result(1 to s'length) ; + + when oct => + for i in si'range loop + case si(i) is + when '0' => result( (3*i)-2 to 3*i ) := "000"; + when '1' => result( (3*i)-2 to 3*i ) := "001"; + when '2' => result( (3*i)-2 to 3*i ) := "010"; + when '3' => result( (3*i)-2 to 3*i ) := "011"; + when '4' => result( (3*i)-2 to 3*i ) := "100"; + when '5' => result( (3*i)-2 to 3*i ) := "101"; + when '6' => result( (3*i)-2 to 3*i ) := "110"; + when '7' => result( (3*i)-2 to 3*i ) := "111"; + when others => + invalid := true; + result( (3*i)-2 to 3*i ) := "XXX"; + end case; + end loop; + assert not invalid + report "String contained characters other than 0 through 7; " & + "treated invalid characters as X's" + severity warning; + return result( 1 to 3*s'length ); + + when hex => + for i in si'range loop + case si(i) is + when '0' => result( (4*i)-3 to 4*i ) := "0000"; + when '1' => result( (4*i)-3 to 4*i ) := "0001"; + when '2' => result( (4*i)-3 to 4*i ) := "0010"; + when '3' => result( (4*i)-3 to 4*i ) := "0011"; + when '4' => result( (4*i)-3 to 4*i ) := "0100"; + when '5' => result( (4*i)-3 to 4*i ) := "0101"; + when '6' => result( (4*i)-3 to 4*i ) := "0110"; + when '7' => result( (4*i)-3 to 4*i ) := "0111"; + when '8' => result( (4*i)-3 to 4*i ) := "1000"; + when '9' => result( (4*i)-3 to 4*i ) := "1001"; + when 'A' | 'a' => result( (4*i)-3 to 4*i ) := "1010"; + when 'B' | 'b' => result( (4*i)-3 to 4*i ) := "1011"; + when 'C' | 'c' => result( (4*i)-3 to 4*i ) := "1100"; + when 'D' | 'd' => result( (4*i)-3 to 4*i ) := "1101"; + when 'E' | 'e' => result( (4*i)-3 to 4*i ) := "1110"; + when 'F' | 'f' => result( (4*i)-3 to 4*i ) := "1111"; + when others => + invalid := true; + result( (4*i)-3 to 4*i ) := "XXXX"; + end case; + end loop; + assert not invalid + report "String contained characters other than 0 through 9 or " & + "A through F; " & + "treated invalid characters as X's" + severity warning; + return result( 1 to 4*s'length ); + + when others => + assert false report "Unsupported base passed." severity warning; + return result ; + + end case; + end tconv; +-- Synopsys translate_on + + ------------------------------------------------------------------- + -- Std_uLogic Conversions + ------------------------------------------------------------------- + function tconv ( s : std_ulogic ) return boolean is + -- pragma built_in SYN_FEED_THRU + begin + case s is + when '0' => return(false); + when '1' => return(true); + when 'L' => return(false); + when 'H' => return(true); + when others => return(false); + end case; + end; + + function tconv ( s : std_ulogic ) return bit is + -- pragma built_in SYN_FEED_THRU + begin + case s is + when '0' => return('0'); + when '1' => return('1'); + when 'L' => return('0'); + when 'H' => return('1'); + when others => return('0'); + end case; + end; + +-- Synopsys translate_off + function tconv ( s : std_ulogic ) return character is + begin + case s is + when '0' => return('0'); + when 'L' => return('L'); + when '1' => return('1'); + when 'H' => return('H'); + when 'U' => return('U'); + when 'W' => return('W'); + when '-' => return('-'); + when 'Z' => return('Z'); + when others => return('X'); + end case; + end; +-- Synopsys translate_on + +-- Synopsys translate_off + function tconv ( s : std_ulogic ) return string is + begin + case s is + when '0' => return("0"); + when 'L' => return("L"); + when '1' => return("1"); + when 'H' => return("H"); + when 'U' => return("U"); + when 'W' => return("W"); + when '-' => return("-"); + when 'Z' => return("Z"); + when others => return("X"); + end case; + end; +-- Synopsys translate_on + + function tconv ( s : std_ulogic ) return integer is + -- pragma built_in SYN_UNSIGNED_TO_INTEGER + begin + case s is + when '0' => return(0); + when 'L' => return(0); + when '1' => return(1); + when 'H' => return(1); + when 'U' => return(0); + when 'W' => return(0); + when '-' => return(0); + when 'Z' => return(0); + when others => return(0); + end case; + end; + + function tconv ( s : std_ulogic ) return std_ulogic_vector is + -- pragma built_in SYN_FEED_THRU + begin + case s is + when '0' => return("0"); + when 'L' => return("L"); + when '1' => return("1"); + when 'H' => return("H"); + when 'U' => return("U"); + when 'W' => return("W"); + when '-' => return("-"); + when 'Z' => return("Z"); + when others => return("X"); + end case; + end; + + ------------------------------------------------------------------- + -- std_ulogic_vector Conversions + ------------------------------------------------------------------- + function tconv ( s : std_ulogic_vector ) return bit_vector is + alias sv : std_ulogic_vector ( 1 to s'length ) is s; + variable result : bit_vector ( 1 to s'length ) ; + -- pragma built_in SYN_FEED_THRU + begin + for i in result'range loop + case sv(i) is + when '0' => result(i) := '0'; + when '1' => result(i) := '1'; + when 'L' => result(i) := '0'; + when 'H' => result(i) := '1'; + when others => result(i) := '0'; + end case; + end loop; + return result; + end; + + function tconv ( s : std_ulogic_vector ) return std_logic_vector is + alias sv : std_ulogic_vector ( 1 to s'length ) is s; + variable result : std_logic_vector ( 1 to s'length ) := (others => 'X'); + -- pragma built_in SYN_FEED_THRU + begin + for i in result'range loop + case sv(i) is + when '0' => result(i) := '0'; + when '1' => result(i) := '1'; + when 'L' => result(i) := '0'; + when 'H' => result(i) := '1'; + when 'W' => result(i) := 'W'; + when '-' => result(i) := '-'; + when 'U' => result(i) := 'U'; + when 'X' => result(i) := 'X'; + when 'Z' => result(i) := 'Z'; + end case; + end loop; + return result; + end; + + function tconv ( s : std_ulogic_vector ) return integer is + variable int_result : integer ; + variable int_exp : integer ; + variable new_value : std_ulogic_vector(1 to s'length) ; + variable invalid : boolean ; + -- pragma built_in SYN_UNSIGNED_TO_INTEGER + begin + -- Synopsys translate_off + int_result := 0; + int_exp := 0; + invalid := false ; + new_value := s ; + for i in new_value'length downto 1 loop + case new_value(i) is + when '1' => int_result := int_result + (2**int_exp); + when '0' => null; + when others => + invalid := true; + end case; + int_exp := int_exp + 1; + end loop; + assert not invalid + report "The std_ulogic_Vector input contained values " & + "other than '0' and '1'. They were treated as zeroes." + severity warning; + -- Synopsys translate_on + return int_result; + end tconv ; + +-- Synopsys translate_off + function tconv ( s : std_ulogic_vector ) return string is + alias sv : std_ulogic_vector ( 1 to s'length ) is s; + variable result : string ( 1 to s'length ) := (others => 'X'); + begin + for i in result'range loop + case sv(i) is + when '0' => result(i) := '0'; + when 'L' => result(i) := 'L'; + when '1' => result(i) := '1'; + when 'H' => result(i) := 'H'; + when 'U' => result(i) := 'U'; + when '-' => result(i) := '-'; + when 'W' => result(i) := 'W'; + when 'Z' => result(i) := 'Z'; + when others => result(i) := 'X'; + end case; + end loop; + return result; + end; +-- Synopsys translate_on + +-- Synopsys translate_off + function tconv ( s : std_ulogic_vector; base : base_t ) return string is + alias sv : std_ulogic_vector ( 1 to s'length ) is s; + variable result : string ( 1 to s'length ); + variable start : positive; + variable extra : natural; + variable resultLength : positive; + subtype bv is std_ulogic_vector( 1 to 1 ); + subtype qv is std_ulogic_vector( 1 to 2 ); + subtype ov is std_ulogic_vector( 1 to 3 ); + subtype hv is std_ulogic_vector( 1 to 4 ); + begin + case base is + when bin => + resultLength := sv'length; + start := 1; + for i in start to resultLength loop + case sv( i ) is + when '0' => result( i ) := '0'; + when '1' => result( i ) := '1'; + when 'X' => result( i ) := 'X'; + when 'L' => result( i ) := 'L'; + when 'H' => result( i ) := 'H'; + when 'W' => result( i ) := 'W'; + when '-' => result( i ) := '-'; + when 'U' => result( i ) := 'U'; + when 'Z' => result( i ) := 'Z'; + end case; + end loop; + + when oct => + extra := sv'length rem ov'length; + case extra is + when 0 => + resultLength := s'length/ov'length; + start := 1; + when 1 => + resultLength := ( s'length/ov'length ) + 1; + start := 2; + case sv( 1 ) is + when '0' => result( 1 ) := '0'; + when '1' => result( 1 ) := '1'; + when '-' => result( 1 ) := '-'; + when 'X' => result( 1 ) := 'X'; + when 'U' => result( 1 ) := 'U'; + when 'Z' => result( 1 ) := 'Z'; + when others => result( 1 ) := '.'; + end case; + when 2 => + resultLength := ( s'length/ov'length ) + 1; + start := 2; + case qv'( sv( 1 to 2 ) ) is + when "00" => result( 1 ) := '0'; + when "01" => result( 1 ) := '1'; + when "10" => result( 1 ) := '2'; + when "11" => result( 1 ) := '3'; + when "--" => result( 1 ) := '-'; + when "XX" => result( 1 ) := 'X'; + when "UU" => result( 1 ) := 'U'; + when "ZZ" => result( 1 ) := 'Z'; + when others => result( 1 ) := '.'; + end case; + when others => + assert false report "TCONV fatal condition" severity failure; + end case; + + for i in 0 to resultLength - start loop + case ov'( SV( (ov'length*i)+(extra+1) to (ov'length*i)+(extra+3) ) ) is + when "000" => result( i+start ) := '0'; + when "001" => result( i+start ) := '1'; + when "010" => result( i+start ) := '2'; + when "011" => result( i+start ) := '3'; + when "100" => result( i+start ) := '4'; + when "101" => result( i+start ) := '5'; + when "110" => result( i+start ) := '6'; + when "111" => result( i+start ) := '7'; + when "---" => result( i+start ) := '-'; + when "XXX" => result( i+start ) := 'X'; + when "UUU" => result( i+start ) := 'U'; + when "ZZZ" => result( i+start ) := 'Z'; + when others => result( i+start ) := '.'; + end case; + end loop; + + when hex => + extra := s'length rem hv'length; + case extra is + when 0 => + resultLength := s'length/hv'length; + start := 1; + when 1 => + resultLength := ( s'length/hv'length ) + 1; + start := 2; + case sv( 1 ) is + when '0' => result( 1 ) := '0'; + when '1' => result( 1 ) := '1'; + when '-' => result( 1 ) := '-'; + when 'X' => result( 1 ) := 'X'; + when 'U' => result( 1 ) := 'U'; + when 'Z' => result( 1 ) := 'Z'; + when others => result( 1 ) := '.'; + end case; + when 2 => + resultLength := ( s'length/hv'length ) + 1; + start := 2; + case qv'( sv( 1 to 2 ) ) is + when "00" => result( 1 ) := '0'; + when "01" => result( 1 ) := '1'; + when "10" => result( 1 ) := '2'; + when "11" => result( 1 ) := '3'; + when "--" => result( 1 ) := '-'; + when "XX" => result( 1 ) := 'X'; + when "UU" => result( 1 ) := 'U'; + when "ZZ" => result( 1 ) := 'Z'; + when others => result( 1 ) := '.'; + end case; + when 3 => + resultLength := ( s'length/hv'length ) + 1; + start := 2; + case ov'( sv( 1 to 3 ) ) is + when "000" => result( 1 ) := '0'; + when "001" => result( 1 ) := '1'; + when "010" => result( 1 ) := '2'; + when "011" => result( 1 ) := '3'; + when "100" => result( 1 ) := '4'; + when "101" => result( 1 ) := '5'; + when "110" => result( 1 ) := '6'; + when "111" => result( 1 ) := '7'; + when "---" => result( 1 ) := '-'; + when "XXX" => result( 1 ) := 'X'; + when "UUU" => result( 1 ) := 'U'; + when "ZZZ" => result( 1 ) := 'Z'; + when others => result( 1 ) := '.'; + end case; + when others => + assert false report "TCONV fatal condition" severity failure; + end case; + + for i in 0 to resultLength - start loop + case hv'( SV( (hv'length*i)+(extra+1) to (hv'length*i)+(extra+4) ) ) is + when "0000" => result( i+start ) := '0'; + when "0001" => result( i+start ) := '1'; + when "0010" => result( i+start ) := '2'; + when "0011" => result( i+start ) := '3'; + when "0100" => result( i+start ) := '4'; + when "0101" => result( i+start ) := '5'; + when "0110" => result( i+start ) := '6'; + when "0111" => result( i+start ) := '7'; + when "1000" => result( i+start ) := '8'; + when "1001" => result( i+start ) := '9'; + when "1010" => result( i+start ) := 'A'; + when "1011" => result( i+start ) := 'B'; + when "1100" => result( i+start ) := 'C'; + when "1101" => result( i+start ) := 'D'; + when "1110" => result( i+start ) := 'E'; + when "1111" => result( i+start ) := 'F'; + when "----" => result( i+start ) := '-'; + when "XXXX" => result( i+start ) := 'X'; + when "UUUU" => result( i+start ) := 'U'; + when "ZZZZ" => result( i+start ) := 'Z'; + when others => result( i+start ) := '.'; + end case; + end loop; + + when others => + assert false report "Unsupported base passed." severity warning; + end case; + return result( 1 to resultLength ); + end; +-- Synopsys translate_on + + function tconv ( s : std_ulogic_vector ) return std_ulogic is + alias sv : std_ulogic_vector( 1 to s'length ) is s; + variable result : std_ulogic; + -- pragma built_in SYN_FEED_THRU + begin + case sv(s'length) is + when '0' => return('0'); + when 'L' => return('L'); + when '1' => return('1'); + when 'H' => return('H'); + when 'U' => return('U'); + when 'W' => return('W'); + when '-' => return('-'); + when 'Z' => return('Z'); + when others => return('X'); + end case; + end; + + ------------------------------------------------------------------- + -- std_logic_vector Conversions + ------------------------------------------------------------------- + --function tconv ( s : std_logic_vector ) return bit_vector is + -- alias sv : std_logic_vector ( 1 to s'length ) is s; + -- variable result : bit_vector ( 1 to s'length ) := (others => '0'); + ---- pragma built_in SYN_FEED_THRU + --begin + -- for i in result'range loop + -- case sv(i) is + -- when '0' => result(i) := '0'; + -- when '1' => result(i) := '1'; + -- when 'L' => result(i) := '0'; + -- when 'H' => result(i) := '1'; + -- when others => result(i) := '0'; + -- end case; + -- end loop; + -- return result; + --end; + + --function tconv ( s : std_logic_vector ) return std_ulogic_vector is + -- alias sv : std_logic_vector ( 1 to s'length ) is s; + -- variable result : std_ulogic_vector ( 1 to s'length ) := (others => 'X'); + ---- pragma built_in SYN_FEED_THRU + --begin + -- for i in result'range loop + -- case sv(i) is + -- when '0' => result(i) := '0'; + -- when '1' => result(i) := '1'; + -- when 'L' => result(i) := '0'; + -- when 'H' => result(i) := '1'; + -- when 'W' => result(i) := 'W'; + -- when '-' => result(i) := '-'; + -- when 'U' => result(i) := 'U'; + -- when 'X' => result(i) := 'X'; + -- when 'Z' => result(i) := 'Z'; + -- end case; + -- end loop; + -- return result; + --end; + + --function tconv ( s : std_logic_vector ) return integer is + -- variable int_result : integer := 0; + -- variable int_exp : integer := 0; + -- alias new_value : std_logic_vector(1 to s'length) is s ; + -- variable invalid : boolean := false; + ---- pragma built_in SYN_UNSIGNED_TO_INTEGER + --begin + ---- Synopsys translate_off + -- for i in new_value'length downto 1 loop + -- case new_value(i) is + -- when '1' => int_result := int_result + (2**int_exp); + -- when '0' => null; + -- when others => + -- invalid := true; + -- end case; + -- int_exp := int_exp + 1; + -- end loop; + -- assert not invalid + -- report "The std_logic_Vector input contained values " & + -- "other than '0' and '1'. They were treated as zeroes." + -- severity warning; + ---- Synopsys translate_on + -- return int_result; + --end tconv ; + +-- Synopsys translate_off + --function tconv ( s : std_logic_vector ) return string is + -- alias sv : std_logic_vector ( 1 to s'length ) is s; + -- variable result : string ( 1 to s'length ) := (others => 'X'); + --begin + -- for i in result'range loop + -- case sv(i) is + -- when '0' => result(i) := '0'; + -- when 'L' => result(i) := 'L'; + -- when '1' => result(i) := '1'; + -- when 'H' => result(i) := 'H'; + -- when 'U' => result(i) := 'U'; + -- when '-' => result(i) := '-'; + -- when 'W' => result(i) := 'W'; + -- when 'Z' => result(i) := 'Z'; + -- when others => result(i) := 'X'; + -- end case; + -- end loop; + -- return result; + --end; +-- Synopsys translate_on + +-- Synopsys translate_off + --function tconv ( s : std_logic_vector; base : base_t ) return string is + -- alias sv : std_logic_vector ( 1 to s'length ) is s; + -- variable result : string ( 1 to s'length ); + -- variable start : positive; + -- variable extra : natural; + -- variable resultlength : positive; + -- subtype bv is std_logic_vector( 1 to 1 ); + -- subtype qv is std_logic_vector( 1 to 2 ); + -- subtype ov is std_logic_vector( 1 to 3 ); + -- subtype hv is std_logic_vector( 1 to 4 ); + --begin + -- case base is + -- when bin => + -- resultLength := sv'length; + -- start := 1; + -- for i in start to resultLength loop + -- case sv( i ) is + -- when '0' => result( i ) := '0'; + -- when '1' => result( i ) := '1'; + -- when 'X' => result( i ) := 'X'; + -- when 'L' => result( i ) := 'L'; + -- when 'H' => result( i ) := 'H'; + -- when 'W' => result( i ) := 'W'; + -- when '-' => result( i ) := '-'; + -- when 'U' => result( i ) := 'U'; + -- when 'Z' => result( i ) := 'Z'; + -- end case; + -- end loop; + + -- when oct => + -- extra := sv'length rem ov'length; + -- case extra is + -- when 0 => + -- resultLength := s'length/ov'length; + -- start := 1; + -- when 1 => + -- resultLength := ( s'length/ov'length ) + 1; + -- start := 2; + -- case sv( 1 ) is + -- when '0' => result( 1 ) := '0'; + -- when '1' => result( 1 ) := '1'; + -- when '-' => result( 1 ) := '-'; + -- when 'X' => result( 1 ) := 'X'; + -- when 'U' => result( 1 ) := 'U'; + -- when 'Z' => result( 1 ) := 'Z'; + -- when others => result( 1 ) := '.'; + -- end case; + -- when 2 => + -- resultLength := ( s'length/ov'length ) + 1; + -- start := 2; + -- case qv'( sv( 1 to 2 ) ) is + -- when "00" => result( 1 ) := '0'; + -- when "01" => result( 1 ) := '1'; + -- when "10" => result( 1 ) := '2'; + -- when "11" => result( 1 ) := '3'; + -- when "--" => result( 1 ) := '-'; + -- when "XX" => result( 1 ) := 'X'; + -- when "UU" => result( 1 ) := 'U'; + -- when "ZZ" => result( 1 ) := 'Z'; + -- when others => result( 1 ) := '.'; + -- end case; + -- when others => + -- assert false report "TCONV fatal condition" severity failure; + -- end case; + + -- for i in 0 to resultLength - start loop + -- case ov'( sv( (ov'length*i)+(extra+1) to (ov'length*i)+(extra+3) ) ) is + -- when "000" => result( i+start ) := '0'; + -- when "001" => result( i+start ) := '1'; + -- when "010" => result( i+start ) := '2'; + -- when "011" => result( i+start ) := '3'; + -- when "100" => result( i+start ) := '4'; + -- when "101" => result( i+start ) := '5'; + -- when "110" => result( i+start ) := '6'; + -- when "111" => result( i+start ) := '7'; + -- when "---" => result( i+start ) := '-'; + -- when "XXX" => result( i+start ) := 'X'; + -- when "UUU" => result( i+start ) := 'U'; + -- when "ZZZ" => result( i+start ) := 'Z'; + -- when others => result( i+start ) := '.'; + -- end case; + -- end loop; + + -- when hex => + -- extra := s'length rem hv'length; + -- case extra is + -- when 0 => + -- resultLength := s'length/hv'length; + -- start := 1; + -- when 1 => + -- resultLength := ( s'length/hv'length ) + 1; + -- start := 2; + -- case sv( 1 ) is + -- when '0' => result( 1 ) := '0'; + -- when '1' => result( 1 ) := '1'; + -- when '-' => result( 1 ) := '-'; + -- when 'X' => result( 1 ) := 'X'; + -- when 'U' => result( 1 ) := 'U'; + -- when 'Z' => result( 1 ) := 'Z'; + -- when others => result( 1 ) := '.'; + -- end case; + -- when 2 => + -- resultLength := ( s'length/hv'length ) + 1; + -- start := 2; + -- case qv'( sv( 1 to 2 ) ) is + -- when "00" => result( 1 ) := '0'; + -- when "01" => result( 1 ) := '1'; + -- when "10" => result( 1 ) := '2'; + -- when "11" => result( 1 ) := '3'; + -- when "--" => result( 1 ) := '-'; + -- when "XX" => result( 1 ) := 'X'; + -- when "UU" => result( 1 ) := 'U'; + -- when "ZZ" => result( 1 ) := 'Z'; + -- when others => result( 1 ) := '.'; + -- end case; + -- when 3 => + -- resultLength := ( s'length/hv'length ) + 1; + -- start := 2; + -- case ov'( sv( 1 to 3 ) ) is + -- when "000" => result( 1 ) := '0'; + -- when "001" => result( 1 ) := '1'; + -- when "010" => result( 1 ) := '2'; + -- when "011" => result( 1 ) := '3'; + -- when "100" => result( 1 ) := '4'; + -- when "101" => result( 1 ) := '5'; + -- when "110" => result( 1 ) := '6'; + -- when "111" => result( 1 ) := '7'; + -- when "---" => result( 1 ) := '-'; + -- when "XXX" => result( 1 ) := 'X'; + -- when "UUU" => result( 1 ) := 'U'; + -- when "ZZZ" => result( 1 ) := 'Z'; + -- when others => result( 1 ) := '.'; + -- end case; + -- when others => + -- assert false report "TCONV fatal condition" severity failure; + -- end case; + + -- for i in 0 to resultLength - start loop + -- case hv'( SV( (hv'length*i)+(extra+1) to (hv'length*i)+(extra+4) ) ) is + -- when "0000" => result( i+start ) := '0'; + -- when "0001" => result( i+start ) := '1'; + -- when "0010" => result( i+start ) := '2'; + -- when "0011" => result( i+start ) := '3'; + -- when "0100" => result( i+start ) := '4'; + -- when "0101" => result( i+start ) := '5'; + -- when "0110" => result( i+start ) := '6'; + -- when "0111" => result( i+start ) := '7'; + -- when "1000" => result( i+start ) := '8'; + -- when "1001" => result( i+start ) := '9'; + -- when "1010" => result( i+start ) := 'A'; + -- when "1011" => result( i+start ) := 'B'; + -- when "1100" => result( i+start ) := 'C'; + -- when "1101" => result( i+start ) := 'D'; + -- when "1110" => result( i+start ) := 'E'; + -- when "1111" => result( i+start ) := 'F'; + -- when "----" => result( i+start ) := '-'; + -- when "XXXX" => result( i+start ) := 'X'; + -- when "UUUU" => result( i+start ) := 'U'; + -- when "ZZZZ" => result( i+start ) := 'Z'; + -- when others => result( i+start ) := '.'; + -- end case; + -- end loop; + + -- when others => + -- assert false report "Unsupported base passed." severity warning; + -- end case; + -- return result( 1 to resultLength ); + --end; +-- Synopsys translate_on + +-- Synopsys translate_off + function hexstring( d : std_ulogic_vector ) return string is + variable nd : + Std_Ulogic_vector( 0 to ((d'length + (4 - (d'length mod 4))) - 1) ) := ( others => '0' ); + variable r : string(1 to (nd'length/4)); + variable hexsize : integer; + variable offset : integer; + subtype iv4 is Std_Ulogic_vector(1 to 4); + begin + + offset := d'length mod 4; + + if offset = 0 then + hexsize := d'length / 4; + nd( 0 to d'length - 1 ) := d; + else + hexsize := nd'length / 4; + nd( ( nd'left + (4 - offset) ) to nd'right ) := d; + end if; + + for i in 0 to hexsize - 1 loop + + case iv4( nd( ( i * 4 ) to ( ( i * 4 ) + 3 ) ) ) is + when "0000" => r(i + 1) := '0'; + when "0001" => r(i + 1) := '1'; + when "0010" => r(i + 1) := '2'; + when "0011" => r(i + 1) := '3'; + when "0100" => r(i + 1) := '4'; + when "0101" => r(i + 1) := '5'; + when "0110" => r(i + 1) := '6'; + when "0111" => r(i + 1) := '7'; + when "1000" => r(i + 1) := '8'; + when "1001" => r(i + 1) := '9'; + when "1010" => r(i + 1) := 'A'; + when "1011" => r(i + 1) := 'B'; + when "1100" => r(i + 1) := 'C'; + when "1101" => r(i + 1) := 'D'; + when "1110" => r(i + 1) := 'E'; + when "1111" => r(i + 1) := 'F'; + when "----" => r(i + 1) := '-'; + when "XXXX" => r(i + 1) := 'X'; + when "UUUU" => r(i + 1) := 'U'; + when "ZZZZ" => r(i + 1) := 'Z'; + when others => r(i + 1) := '.'; + end case; + + end loop; + + return r(1 to hexsize); + end hexstring; +-- Synopsys translate_on + +-- Synopsys translate_off + function octstring( d : std_ulogic_vector ) return string is + variable nd : + Std_Ulogic_vector( 0 to ((d'length + (3 - (d'length mod 3))) - 1) ) := ( others => '0' ); + variable offset : integer; + variable r : string(1 to (nd'length/3)); + variable octsize : integer; + subtype iv3 is Std_Ulogic_vector(1 to 3); + begin + + offset := d'length mod 3; + + if offset = 0 then + octsize := d'length / 3; + nd( 0 to d'length - 1 ) := d; + else + octsize := nd'length / 3; + nd( ( nd'left + (3 - offset) ) to nd'right ) := d; + end if; + + for i in 0 to octsize - 1 loop + + case iv3( nd( ( i * 3 ) to ( ( i * 3 ) + 2 ) ) ) is + when "000" => r(i + 1) := '0'; + when "001" => r(i + 1) := '1'; + when "010" => r(i + 1) := '2'; + when "011" => r(i + 1) := '3'; + when "100" => r(i + 1) := '4'; + when "101" => r(i + 1) := '5'; + when "110" => r(i + 1) := '6'; + when "111" => r(i + 1) := '7'; + when "---" => r(i + 1) := '-'; + when "XXX" => r(i + 1) := 'X'; + when "UUU" => r(i + 1) := 'U'; + when "ZZZ" => r(i + 1) := 'Z'; + when others => r(i + 1) := '.'; + end case; + + end loop; + + return r; + end octstring; +-- Synopsys translate_on + +-- Synopsys translate_off + function bitstring( d : std_ulogic_vector ) return string is + variable nd : + Std_Ulogic_vector(0 to ( d'length - 1 ) ) := ( others => '0' ); + variable r : string(1 to (nd'length)); + begin + nd := d; + for i in nd'range loop + r(i + 1) := std_ulogic_to_character( nd(i) ); + end loop; + return r; + end bitstring; +-- Synopsys translate_on + + ------------------------------------------------------------------- + -- Std_Match functions + ------------------------------------------------------------------- + constant no_warning: boolean := false; -- default to emit warnings + + -- Id: M.1a + function std_match (l, r: std_ulogic) return std_ulogic is + begin + if (l ?= r) then + return '1' ; + else + return '0' ; + end if ; + end std_match; + + -- Id: M.4b + function std_match (l, r: std_ulogic_vector) return std_ulogic is + variable result : boolean ; + begin + if (l ?= r) then + return '1' ; + else + return '0' ; + end if; + end std_match; + + ------------------------------------------------------------------- + -- Overloaded Relational Operators returning std_ulogic + ------------------------------------------------------------------- + function "=" ( l,r : integer ) return std_ulogic is + -- pragma built_in SYN_EQL + begin + if (l - r) = 0 then + return ('1'); + else + return ('0'); + end if ; + end "="; + + function "/=" ( l,r : integer ) return std_ulogic is + -- pragma built_in SYN_NEQ + begin + if (l - r) = 0 then + return ('0'); + else + return ('1'); + end if ; + end "/="; + + function ">" ( l,r : integer ) return std_ulogic is + -- pragma built_in SYN_GT + begin + if (l - r) > 0 then + return ('1'); + else + return ('0'); + end if ; + end ">"; + + function ">=" ( l,r : integer ) return std_ulogic is + -- pragma built_in SYN_GEQ + begin + if (l - r) >= 0 then + return ('1'); + else + return ('0'); + end if ; + end ">="; + + function "<" ( l,r : integer ) return std_ulogic is + -- pragma built_in SYN_LT + begin + if (r - l) > 0 then + return ('1'); + else + return ('0'); + end if ; + end "<"; + + function "<=" ( l,r : integer ) return std_ulogic is + -- pragma built_in SYN_LEQ + begin + if (r - l) >= 0 then + return ('1'); + else + return ('0'); + end if ; + end "<="; + + ------------------------------------------------------------------- + -- Overloaded Relational Operators returning STD_uLogic + ------------------------------------------------------------------- + function "=" ( l,r : std_ulogic ) return std_ulogic is + -- pragma built_in SYN_EQL + begin + return ( tconv( l = r ) ); + end "="; + + function "/=" ( l,r : std_ulogic ) return std_ulogic is + -- pragma built_in SYN_NEQ + begin + return ( tconv( l /= r ) ); + end "/="; + + function ">" ( l,r : std_ulogic ) return std_ulogic is + -- pragma built_in SYN_GT + begin + return ( tconv( l > r ) ); + end ">"; + + function ">=" ( l,r : std_ulogic ) return std_ulogic is + -- pragma built_in SYN_GEQ + begin + return ( tconv( l >= r ) ); + end ">="; + + function "<" ( l,r : std_ulogic ) return std_ulogic is + -- pragma built_in SYN_LT + begin + return ( tconv( l < r ) ); + end "<"; + + function "<=" ( l,r : std_ulogic ) return std_ulogic is + -- pragma built_in SYN_LEQ + begin + return ( tconv( l <= r ) ); + end "<="; + + ------------------------------------------------------------------- + -- Overloaded Relational Operators returning STD_uLogic + ------------------------------------------------------------------- + + function "=" ( l,r : std_ulogic_vector) return std_ulogic is + -- pragma built_in SYN_EQL + begin + -- Synopsys translate_off + if l'length /= r'length then + assert false + report "The bit lengths of the two inputs to the = " & + "operator are unequal. " + severity error; + return '0' ; + end if ; + -- Synopsys translate_on + return ( tconv( l = r ) ); + end "="; + + ------------------------------------------------------------------- + function "/=" ( l,r : std_ulogic_vector) return std_ulogic is + -- pragma built_in SYN_NEQ + begin + -- Synopsys translate_off + if l'length /= r'length then + assert false + report "The bit lengths of the two inputs to the /= " & + "operator are unequal. " + severity error; + return '0' ; + end if ; + -- Synopsys translate_on + return ( tconv( l /= r ) ); + end "/="; + + ------------------------------------------------------------------- + function ">" ( l,r : std_ulogic_vector) return std_ulogic is + -- pragma built_in SYN_GT + begin + -- Synopsys translate_off + if l'length /= r'length then + assert false + report "The bit lengths of the two inputs to the > " & + "operator are unequal. " + severity error; + return '0' ; + end if ; + -- Synopsys translate_on + return ( tconv( l > r ) ); + end ">"; + + ------------------------------------------------------------------- + function ">=" ( l,r : std_ulogic_vector) return std_ulogic is + -- pragma built_in SYN_GEQ + begin + -- Synopsys translate_off + if l'length /= r'length then + assert false + report "The bit lengths of the two inputs to the >= " & + "operator are unequal. " + severity error; + return '0' ; + end if ; + -- Synopsys translate_on + return ( tconv( l >= r ) ); + end ">="; + + ------------------------------------------------------------------- + function "<" ( l,r : std_ulogic_vector) return std_ulogic is + -- pragma built_in SYN_LT + begin + -- Synopsys translate_off + if l'length /= r'length then + assert false + report "The bit lengths of the two inputs to the < " & + "operator are unequal. " + severity error; + return '0' ; + end if ; + -- Synopsys translate_on + return ( tconv( l < r ) ); + end "<"; + + ------------------------------------------------------------------- + function "<=" ( l,r : std_ulogic_vector) return std_ulogic is + -- pragma built_in SYN_LEQ + begin + -- Synopsys translate_off + if l'length /= r'length then + assert false + report "The bit lengths of the two inputs to the <= " & + "operator are unequal. " + severity error; + return '0' ; + end if ; + -- Synopsys translate_on + return ( tconv( l <= r ) ); + end "<="; + +--============================================================== + -- Shift and Rotate Functions +--============================================================== +----------Local Subprograms - shift/rotate ops------------------- + -- Synopsys translate_off + constant NAU: std_ulogic_vector(0 downto 1) := (others => '0'); + -- Synopsys translate_on + + function xsll (arg: std_ulogic_vector; count: natural) return std_ulogic_vector + is + constant arg_l: integer := arg'length-1; + alias xarg: std_ulogic_vector(arg_l downto 0) is arg; + variable result: std_ulogic_vector(arg_l downto 0) ; + -- pragma built_in SYN_SLLU + begin + result := (others => '0'); + if count <= arg_l then + result(arg_l downto count) := xarg(arg_l-count downto 0); + end if; + return result; + end xsll; + + function xsrl (arg: std_ulogic_vector; count: natural) return std_ulogic_vector + is + constant arg_l: integer := arg'length-1; + alias xarg: std_ulogic_vector(arg_l downto 0) is arg; + variable result: std_ulogic_vector(arg_l downto 0) ; + -- pragma built_in SYN_SRLU + begin + result := (others => '0'); + if count <= arg_l then + result(arg_l-count downto 0) := xarg(arg_l downto count); + end if; + return result; + end xsrl; + + function xsra (arg: std_ulogic_vector; count: natural) return std_ulogic_vector + is + constant arg_l: integer := arg'length-1; + alias xarg: std_ulogic_vector(arg_l downto 0) is arg; + variable result: std_ulogic_vector(arg_l downto 0); + variable xcount: natural ; + -- pragma built_in SYN_SHR + begin + xcount := count; + if ((arg'length <= 1) or (xcount = 0)) then return arg; + else + if (xcount > arg_l) then xcount := arg_l; + end if; + result(arg_l-xcount downto 0) := xarg(arg_l downto xcount); + result(arg_l downto (arg_l - xcount + 1)) := (others => xarg(arg_l)); + end if; + return result; + end xsra; + + function xrol (arg: std_ulogic_vector; count: natural) return std_ulogic_vector + is + constant arg_l: integer := arg'length-1; + alias xarg: std_ulogic_vector(arg_l downto 0) is arg; + variable result: std_ulogic_vector(arg_l downto 0) ; + variable countm: integer; + -- pragma built_in SYN_ROLU + begin + result := xarg; + countm := count mod (arg_l + 1); + if countm /= 0 then + result(arg_l downto countm) := xarg(arg_l-countm downto 0); + result(countm-1 downto 0) := xarg(arg_l downto arg_l-countm+1); + end if; + return result; + end xrol; + + function xror (arg: std_ulogic_vector; count: natural) return std_ulogic_vector + is + constant arg_l: integer := arg'length-1; + alias xarg: std_ulogic_vector(arg_l downto 0) is arg; + variable result: std_ulogic_vector(arg_l downto 0) ; + variable countm: integer; + -- pragma built_in SYN_RORU + begin + countm := count mod (arg_l + 1); + result := xarg; + if countm /= 0 then + result(arg_l-countm downto 0) := xarg(arg_l downto countm); + result(arg_l downto arg_l-countm+1) := xarg(countm-1 downto 0); + end if; + return result; + end xror; + +--=================================================================== + + -- Id: S.1 + function shift_left (arg: std_ulogic_vector; count: natural) return std_ulogic_vector is + -- pragma built_in SYN_SLLU + begin + -- Synopsys translate_off + if (arg'length < 1) then return NAU; + end if; + -- Synopsys translate_on + return std_ulogic_vector( xsll( std_ulogic_vector(arg), count ) ); + end shift_left; + + -- Id: S.2 + function shift_right (arg: std_ulogic_vector; count: natural) return std_ulogic_vector is + -- pragma built_in SYN_SRLU + begin + -- Synopsys translate_off + if (arg'length < 1) then return NAU; + end if; + -- Synopsys translate_on + return std_ulogic_vector( xsrl( std_ulogic_vector(arg), count ) ); + end shift_right; + + + -- Id: S.5 + function rotate_left (arg: std_ulogic_vector; count: natural) return std_ulogic_vector is + -- pragma built_in SYN_ROLU + begin + -- Synopsys translate_off + if (arg'length < 1) then return NAU; + end if; + -- Synopsys translate_on + return std_ulogic_vector( xrol( std_ulogic_vector(arg), count ) ); + end rotate_left; + + -- Id: S.6 + function rotate_right (arg: std_ulogic_vector; count: natural) return std_ulogic_vector is + -- pragma built_in SYN_RORU + begin + -- Synopsys translate_off + if (arg'length < 1) then return NAU; + end if; + -- Synopsys translate_on + return std_ulogic_vector( xror( std_ulogic_vector(arg), count ) ); + end rotate_right; + + -- Id: S.9 + function "sll" (arg: std_ulogic_vector; count: integer) return std_ulogic_vector is + -- pragma built_in SYN_SLL + begin + if (count >= 0) then + return shift_left(arg, count); + else + return shift_right(arg, -count); + end if; + end "sll"; + + -- Id: S.11 + function "srl" (arg: std_ulogic_vector; count: integer) return std_ulogic_vector is + -- pragma built_in SYN_SRL + begin + if (count >= 0) then + return shift_right(arg, count); + else + return shift_left(arg, -count); + end if; + end "srl"; + + -- Id: S.13 + function "rol" (arg: std_ulogic_vector; count: integer) return std_ulogic_vector is + -- pragma built_in SYN_ROL + begin + if (count >= 0) then + return rotate_left(arg, count); + else + return rotate_right(arg, -count); + end if; + end "rol"; + + -- Id: S.15 + function "ror" (arg: std_ulogic_vector; count: integer) return std_ulogic_vector is + -- pragma built_in SYN_ROR + begin + if (count >= 0) then + return rotate_right(arg, count); + else + return rotate_left(arg, -count); + end if; + end "ror"; + +--============================================================== + --End Shift and Rotate Functions +--============================================================== + +end std_ulogic_support ; + diff --git a/rel/src/vhdl/ibm/std_ulogic_unsigned.vhdl b/rel/src/vhdl/ibm/std_ulogic_unsigned.vhdl new file mode 100644 index 0000000..b451b26 --- /dev/null +++ b/rel/src/vhdl/ibm/std_ulogic_unsigned.vhdl @@ -0,0 +1,374 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +--*************************************************************************** +-- Copyright 2020 International Business Machines +-- +-- Licensed under the Apache License, Version 2.0 (the “License”); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- The patent license granted to you in Section 3 of the License, as applied +-- to the “Work,” hereby includes implementations of the Work in physical form. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an “AS IS” BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- +--*************************************************************************** +library IEEE, IBM; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use IBM.std_ulogic_support.all; + +package std_ulogic_unsigned is + + function "+"(l: std_ulogic_vector; r: std_ulogic_vector) return std_ulogic_vector; + function "+"(l: std_ulogic_vector; r: integer) return std_ulogic_vector; + function "+"(l: integer; r: std_ulogic_vector) return std_ulogic_vector; + function "+"(l: std_ulogic_vector; r: std_ulogic) return std_ulogic_vector; + function "+"(l: std_ulogic; r: std_ulogic_vector) return std_ulogic_vector; + + function "-"(l: std_ulogic_vector; r: std_ulogic_vector) return std_ulogic_vector; + function "-"(l: std_ulogic_vector; r: integer) return std_ulogic_vector; + function "-"(l: integer; r: std_ulogic_vector) return std_ulogic_vector; + function "-"(l: std_ulogic_vector; r: std_ulogic) return std_ulogic_vector; + function "-"(l: std_ulogic; r: std_ulogic_vector) return std_ulogic_vector; + + function "+"(l: std_ulogic_vector) return std_ulogic_vector; + + function "*"(l: std_ulogic_vector; r: std_ulogic_vector) return std_ulogic_vector; + + function "=" ( l : natural; r : std_ulogic_vector) return boolean; + function "/="( l : natural; r : std_ulogic_vector) return boolean; + function "<" ( l : natural; r : std_ulogic_vector) return boolean; + function "<="( l : natural; r : std_ulogic_vector) return boolean; + function ">" ( l : natural; r : std_ulogic_vector) return boolean; + function ">="( l : natural; r : std_ulogic_vector) return boolean; + + function "=" ( l : std_ulogic_vector; r : natural) return boolean; + function "/="( l : std_ulogic_vector; r : natural) return boolean; + function "<" ( l : std_ulogic_vector; r : natural) return boolean; + function "<="( l : std_ulogic_vector; r : natural) return boolean; + function ">" ( l : std_ulogic_vector; r : natural) return boolean; + function ">="( l : std_ulogic_vector; r : natural) return boolean; + + function "=" ( l : natural; r : std_ulogic_vector) return std_ulogic; + function "/="( l : natural; r : std_ulogic_vector) return std_ulogic; + function "<" ( l : natural; r : std_ulogic_vector) return std_ulogic; + function "<="( l : natural; r : std_ulogic_vector) return std_ulogic; + function ">" ( l : natural; r : std_ulogic_vector) return std_ulogic; + function ">="( l : natural; r : std_ulogic_vector) return std_ulogic; + + function "=" ( l : std_ulogic_vector; r : natural) return std_ulogic; + function "/="( l : std_ulogic_vector; r : natural) return std_ulogic; + function "<" ( l : std_ulogic_vector; r : natural) return std_ulogic; + function "<="( l : std_ulogic_vector; r : natural) return std_ulogic; + function ">" ( l : std_ulogic_vector; r : natural) return std_ulogic; + function ">="( l : std_ulogic_vector; r : natural) return std_ulogic; + + function to_integer( d : std_ulogic_vector ) return natural; + -- synopsys translate_off + attribute type_convert of to_integer : function is true; + attribute btr_name of to_integer : function is "PASS"; + attribute pin_bit_information of to_integer : function is + (1 => (" ","A0 ","INCR","PIN_BIT_SCALAR"), + 2 => (" ","10 ","INCR","PIN_BIT_SCALAR")); + -- synopsys translate_on + + -- synopsys translate_off + function to_std_ulogic_vector( d : natural; w : positive ) return std_ulogic_vector; + attribute type_convert of to_std_ulogic_vector : function is true; + attribute btr_name of to_std_ulogic_vector : function is "PASS"; + attribute pin_bit_information of to_std_ulogic_vector : function is + (1 => (" ","A0 ","INCR","PIN_BIT_SCALAR"), + 2 => (" ","10 ","INCR","PIN_BIT_SCALAR")); + -- synopsys translate_on + +end std_ulogic_unsigned; + +package body std_ulogic_unsigned is + + function maximum(L, R: INTEGER) return INTEGER is + begin + if L > R then + return L; + else + return R; + end if; + end; + + function "+"(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is + constant length : INTEGER := maximum(L'length, R'length); + variable result : UNSIGNED(length-1 downto 0); + -- pragma label_applies_to plus + begin + result := UNSIGNED(L) + UNSIGNED(R); -- pragma label plus + return std_ulogic_vector(result); + end; + + function "+"(L: STD_ULOGIC_VECTOR; R: INTEGER) return STD_ULOGIC_VECTOR is + variable result : STD_ULOGIC_VECTOR (L'range); + -- pragma label_applies_to plus + begin + result := std_ulogic_vector( UNSIGNED(L) + R ); -- pragma label plus + return result ; + end; + + function "+"(L: INTEGER; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is + variable result : STD_ULOGIC_VECTOR (R'range); + -- pragma label_applies_to plus + begin + result := std_ulogic_vector( L + UNSIGNED(R) ); -- pragma label plus + return result; + end; + + function "+"(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC) return STD_ULOGIC_VECTOR is + variable result : STD_ULOGIC_VECTOR (L'range); + -- pragma label_applies_to plus + begin + if R = '1' then + result := std_ulogic_vector( UNSIGNED(L) + 1 ); + else + result := L; + end if; + return result ; + end; + + function "+"(L: STD_ULOGIC; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is + variable result : STD_ULOGIC_VECTOR (R'range); + -- pragma label_applies_to plus + begin + if L = '1' then + result := std_ulogic_vector( UNSIGNED(R) + 1 ); + else + result := R; + end if; + return result ; + end; + + function "+"(L: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is + variable result : STD_ULOGIC_VECTOR (L'range); + -- pragma label_applies_to plus + begin + result := L; + return result ; + end; + + function "-"(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is + constant length: INTEGER := maximum(L'length, R'length); + variable result : STD_ULOGIC_VECTOR (length-1 downto 0); + -- pragma label_applies_to minus + begin + result := std_ulogic_vector( UNSIGNED(L) - UNSIGNED(R) ); -- pragma label minus + return result ; + end; + + function "-"(L: STD_ULOGIC_VECTOR; R: INTEGER) return STD_ULOGIC_VECTOR is + variable result : STD_ULOGIC_VECTOR (L'range); + -- pragma label_applies_to minus + begin + result := std_ulogic_vector( UNSIGNED(L) - R ); -- pragma label minus + return result ; + end; + + function "-"(L: INTEGER; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is + variable result : STD_ULOGIC_VECTOR (R'range); + -- pragma label_applies_to minus + begin + result := std_ulogic_vector( L - UNSIGNED(R) ); -- pragma label minus + return result ; + end; + + function "-"(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC) return STD_ULOGIC_VECTOR is + variable result : STD_ULOGIC_VECTOR (L'range); + -- pragma label_applies_to minus + begin + if R = '1' then + result := std_ulogic_vector( UNSIGNED(L) - 1 ); + else + result := L; + end if; + return result ; + end; + + function "-"(L: STD_ULOGIC; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is + variable result : STD_ULOGIC_VECTOR (R'range); + -- pragma label_applies_to minus + begin + if L = '1' then + result := std_ulogic_vector( 1 - UNSIGNED(R) ); + else + result := std_ulogic_vector( 0 - UNSIGNED(R) ); + end if; + return result ; + end; + + function "*"(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is + constant length: INTEGER := maximum(L'length, R'length); + variable result : STD_ULOGIC_VECTOR ((L'length+R'length-1) downto 0); + -- pragma label_applies_to mult + begin + result := std_ulogic_vector( UNSIGNED(L) * UNSIGNED(R) ); -- pragma label mult + return result ; + end; + + function "=" ( l : natural; r : std_ulogic_vector) return boolean is + begin + return l = unsigned(r); + end "="; + + function "/="( l : natural; r : std_ulogic_vector) return boolean is + begin + return l /= unsigned(r); + end "/="; + + function "<" ( l : natural; r : std_ulogic_vector) return boolean is + begin + return l < unsigned(r); + end "<"; + + function "<="( l : natural; r : std_ulogic_vector) return boolean is + begin + return l <= unsigned(r); + end "<="; + + function ">" ( l : natural; r : std_ulogic_vector) return boolean is + begin + return l > unsigned(r); + end ">"; + + function ">="( l : natural; r : std_ulogic_vector) return boolean is + begin + return l >= unsigned(r); + end ">="; + + function "=" ( l : std_ulogic_vector; r : natural) return boolean is + begin + return unsigned(l) = r; + end "="; + + function "/="( l : std_ulogic_vector; r : natural) return boolean is + begin + return unsigned(l) /= r; + end "/="; + + function "<" ( l : std_ulogic_vector; r : natural) return boolean is + begin + return unsigned(l) < r; + end "<"; + + function "<="( l : std_ulogic_vector; r : natural) return boolean is + begin + return unsigned(l) <= r; + end "<="; + + function ">" ( l : std_ulogic_vector; r : natural) return boolean is + begin + return unsigned(l) > r; + end ">"; + + function ">="( l : std_ulogic_vector; r : natural) return boolean is + begin + return unsigned(l) >= r; + end ">="; + + function "=" ( l : natural; r : std_ulogic_vector) return std_ulogic is + begin + return tconv( l = unsigned(r) ); + end "="; + + function "/="( l : natural; r : std_ulogic_vector) return std_ulogic is + begin + return tconv( l /= unsigned(r) ); + end "/="; + + function "<" ( l : natural; r : std_ulogic_vector) return std_ulogic is + begin + return tconv( l < unsigned(r) ); + end "<"; + + function "<="( l : natural; r : std_ulogic_vector) return std_ulogic is + begin + return tconv( l <= unsigned(r) ); + end "<="; + + function ">" ( l : natural; r : std_ulogic_vector) return std_ulogic is + begin + return tconv( l > unsigned(r) ); + end ">"; + + function ">="( l : natural; r : std_ulogic_vector) return std_ulogic is + begin + return tconv( l >= unsigned(r) ); + end ">="; + + function "=" ( l : std_ulogic_vector; r : natural) return std_ulogic is + begin + return tconv( unsigned(l) = r ); + end "="; + + function "/="( l : std_ulogic_vector; r : natural) return std_ulogic is + begin + return tconv( unsigned(l) /= r ); + end "/="; + + function "<" ( l : std_ulogic_vector; r : natural) return std_ulogic is + begin + return tconv( unsigned(l) < r ); + end "<"; + + function "<="( l : std_ulogic_vector; r : natural) return std_ulogic is + begin + return tconv( unsigned(l) <= r ); + end "<="; + + function ">" ( l : std_ulogic_vector; r : natural) return std_ulogic is + begin + return tconv( unsigned(l) > r ); + end ">"; + + function ">="( l : std_ulogic_vector; r : natural) return std_ulogic is + begin + return tconv( unsigned(l) >= r ); + end ">="; + + function to_integer( d : std_ulogic_vector ) return natural is + begin + return tconv( d ); + end to_integer; + + function to_std_ulogic_vector( d : natural; w : positive ) return std_ulogic_vector is + begin + return tconv( d, w ); + end to_std_ulogic_vector; + +end std_ulogic_unsigned; diff --git a/rel/src/vhdl/support/power_logic_pkg.vhdl b/rel/src/vhdl/support/power_logic_pkg.vhdl new file mode 100644 index 0000000..eafa752 --- /dev/null +++ b/rel/src/vhdl/support/power_logic_pkg.vhdl @@ -0,0 +1,38 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee; +use ieee.std_logic_1164.all; + +package power_logic_pkg is + + subtype power_logic is std_logic; + subtype power_logic_vector is std_logic_vector; + +end package power_logic_pkg; + diff --git a/rel/src/vhdl/tri/ramb16_s18_s18.vhdl b/rel/src/vhdl/tri/ramb16_s18_s18.vhdl new file mode 100644 index 0000000..c58b13a --- /dev/null +++ b/rel/src/vhdl/tri/ramb16_s18_s18.vhdl @@ -0,0 +1,384 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; +use ieee.std_logic_1164.all; + +library ibm; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; + +library UNIMACRO; +use UNIMACRO.vcomponents.all; + +entity RAMB16_S18_S18 is + generic ( + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_A : bit_vector := X"000000000"; + INIT_B : bit_vector := X"000000000"; + SIM_COLLISION_CHECK : string := "ALL"; + SRVAL_A : bit_vector := X"000000000"; + SRVAL_B : bit_vector := X"000000000"; + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + port ( + DOA : out std_logic_vector(15 downto 0); + DOB : out std_logic_vector(15 downto 0); + DOPA : out std_logic_vector(1 downto 0); + DOPB : out std_logic_vector(1 downto 0); + ADDRA : in std_logic_vector(9 downto 0); + ADDRB : in std_logic_vector(9 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(15 downto 0); + DIB : in std_logic_vector(15 downto 0); + DIPA : in std_logic_vector(1 downto 0); + DIPB : in std_logic_vector(1 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); +end RAMB16_S18_S18; + +architecture RAMB16_S18_S18 of RAMB16_S18_S18 is + +signal DINA, DINB : std_logic_vector(17 downto 0); +signal DOUTA, DOUTB : std_logic_vector(17 downto 0); +signal SSRA_t, SSRB_t : std_logic; +signal WEA_t, WEB_t : std_logic_vector(1 downto 0); + +begin + +DINA <= DIPA & DIA; +DOPA <= DOUTA(17 downto 16); +DOA <= DOUTA(15 downto 0); + +DINB <= DIPB & DIB; +DOPB <= DOUTB(17 downto 16); +DOB <= DOUTB(15 downto 0); + +SSRA_t <= SSRA; +SSRB_t <= SSRB; +WEA_t <= WEA & WEA; +WEB_t <= WEB & WEB; + + + + + -- BRAM_TDP_MACRO: True Dual Port RAM + -- Virtex-7 + -- Xilinx HDL Language Template, version 2019.1 + + -- Note - This Unimacro model assumes the port directions to be "downto". + -- Simulation of this model with "to" in the port directions could lead to erroneous results. + + -------------------------------------------------------------------------- + -- DATA_WIDTH_A/B | BRAM_SIZE | RAM Depth | ADDRA/B Width | WEA/B Width -- + -- ===============|===========|===========|===============|=============-- + -- 19-36 | "36Kb" | 1024 | 10-bit | 4-bit -- + -- 10-18 | "36Kb" | 2048 | 11-bit | 2-bit -- + -- 10-18 | "18Kb" | 1024 | 10-bit | 2-bit -- * using + -- 5-9 | "36Kb" | 4096 | 12-bit | 1-bit -- + -- 5-9 | "18Kb" | 2048 | 11-bit | 1-bit -- + -- 3-4 | "36Kb" | 8192 | 13-bit | 1-bit -- + -- 3-4 | "18Kb" | 4096 | 12-bit | 1-bit -- + -- 2 | "36Kb" | 16384 | 14-bit | 1-bit -- + -- 2 | "18Kb" | 8192 | 13-bit | 1-bit -- + -- 1 | "36Kb" | 32768 | 15-bit | 1-bit -- + -- 1 | "18Kb" | 16384 | 14-bit | 1-bit -- + -------------------------------------------------------------------------- + + BRAM_0 : BRAM_TDP_MACRO + generic map ( + BRAM_SIZE => "18Kb", -- Target BRAM, "18Kb" or "36Kb" + DEVICE => "7SERIES", -- Target Device: "VIRTEX5", "VIRTEX6", "7SERIES", "SPARTAN6" + DOA_REG => 0, -- Optional port A output register (0 or 1) + DOB_REG => 0, -- Optional port B output register (0 or 1) + INIT_A => INIT_A, -- Initial values on A output port + INIT_B => INIT_B, -- Initial values on B output port + INIT_FILE => "NONE", + READ_WIDTH_A => 18, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb") + READ_WIDTH_B => 18, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb") + SIM_COLLISION_CHECK => "NONE", + SRVAL_A => SRVAL_A, -- Set/Reset value for A port output + SRVAL_B => SRVAL_A, -- Set/Reset value for B port output + WRITE_MODE_A => WRITE_MODE_A, -- "WRITE_FIRST", "READ_FIRST" or "NO_CHANGE" + WRITE_MODE_B => WRITE_MODE_B, -- "WRITE_FIRST", "READ_FIRST" or "NO_CHANGE" + WRITE_WIDTH_A => 18, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb") + WRITE_WIDTH_B => 18, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb") + -- The following INIT_xx declarations specify the initial contents of the RAM + INIT_00 => INIT_00, + INIT_01 => INIT_01, + INIT_02 => INIT_02, + INIT_03 => INIT_03, + INIT_04 => INIT_04, + INIT_05 => INIT_05, + INIT_06 => INIT_06, + INIT_07 => INIT_07, + INIT_08 => INIT_08, + INIT_09 => INIT_09, + INIT_0A => INIT_0A, + INIT_0B => INIT_0B, + INIT_0C => INIT_0C, + INIT_0D => INIT_0D, + INIT_0E => INIT_0E, + INIT_0F => INIT_0F, + INIT_10 => INIT_10, + INIT_11 => INIT_11, + INIT_12 => INIT_12, + INIT_13 => INIT_13, + INIT_14 => INIT_14, + INIT_15 => INIT_15, + INIT_16 => INIT_16, + INIT_17 => INIT_17, + INIT_18 => INIT_18, + INIT_19 => INIT_19, + INIT_1A => INIT_1A, + INIT_1B => INIT_1B, + INIT_1C => INIT_1C, + INIT_1D => INIT_1D, + INIT_1E => INIT_1E, + INIT_1F => INIT_1F, + INIT_20 => INIT_20, + INIT_21 => INIT_21, + INIT_22 => INIT_22, + INIT_23 => INIT_23, + INIT_24 => INIT_24, + INIT_25 => INIT_25, + INIT_26 => INIT_26, + INIT_27 => INIT_27, + INIT_28 => INIT_28, + INIT_29 => INIT_29, + INIT_2A => INIT_2A, + INIT_2B => INIT_2B, + INIT_2C => INIT_2C, + INIT_2D => INIT_2D, + INIT_2E => INIT_2E, + INIT_2F => INIT_2F, + INIT_30 => INIT_30, + INIT_31 => INIT_31, + INIT_32 => INIT_32, + INIT_33 => INIT_33, + INIT_34 => INIT_34, + INIT_35 => INIT_35, + INIT_36 => INIT_36, + INIT_37 => INIT_37, + INIT_38 => INIT_38, + INIT_39 => INIT_39, + INIT_3A => INIT_3A, + INIT_3B => INIT_3B, + INIT_3C => INIT_3C, + INIT_3D => INIT_3D, + INIT_3E => INIT_3E, + INIT_3F => INIT_3F, + + -- The next set of INIT_xx are valid when configured as 36Kb + INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", + + -- The next set of INITP_xx are for the parity bits + INITP_00 => INITP_00, + INITP_01 => INITP_01, + INITP_02 => INITP_02, + INITP_03 => INITP_03, + INITP_04 => INITP_04, + INITP_05 => INITP_05, + INITP_06 => INITP_06, + INITP_07 => INITP_07, + + -- The next set of INIT_xx are valid when configured as 36Kb + INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000" + ) + port map ( + DOA => DOUTA, -- Output port-A data, width defined by READ_WIDTH_A parameter + DOB => DOUTB, -- Output port-B data, width defined by READ_WIDTH_B parameter + ADDRA => ADDRA, -- Input port-A address, width defined by Port A depth + ADDRB => ADDRB, -- Input port-B address, width defined by Port B depth + CLKA => CLKA, -- 1-bit input port-A clock + CLKB => CLKB, -- 1-bit input port-B clock + DIA => DINA, -- Input port-A data, width defined by WRITE_WIDTH_A parameter + DIB => DINB, -- Input port-B data, width defined by WRITE_WIDTH_B parameter + ENA => ENA, -- 1-bit input port-A enable + ENB => ENB, -- 1-bit input port-B enable + REGCEA => '1', -- REGCEA, -- 1-bit input port-A output register enable + REGCEB => '1', -- REGCEB, -- 1-bit input port-B output register enable + RSTA => SSRA_t, -- 1-bit input port-A reset + RSTB => SSRB_t, -- 1-bit input port-B reset + WEA => WEA_t, -- Input port-A write enable, width defined by Port A depth + WEB => WEB_t -- Input port-B write enable, width defined by Port B depth + ); + +-- End of BRAM_TDP_MACRO_inst instantiation + + +end RAMB16_S18_S18; diff --git a/rel/src/vhdl/tri/ramb16_s36_s36.vhdl b/rel/src/vhdl/tri/ramb16_s36_s36.vhdl new file mode 100644 index 0000000..c0b06b7 --- /dev/null +++ b/rel/src/vhdl/tri/ramb16_s36_s36.vhdl @@ -0,0 +1,388 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; +use ieee.std_logic_1164.all; + +library ibm; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; + +library UNIMACRO; +use UNIMACRO.vcomponents.all; + +entity RAMB16_S36_S36 is + generic ( + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_A : bit_vector := X"000000000"; + INIT_B : bit_vector := X"000000000"; + SIM_COLLISION_CHECK : string := "ALL"; + SRVAL_A : bit_vector := X"000000000"; + SRVAL_B : bit_vector := X"000000000"; + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + port ( + DOA : out std_logic_vector(31 downto 0); + DOB : out std_logic_vector(31 downto 0); + DOPA : out std_logic_vector(3 downto 0); + DOPB : out std_logic_vector(3 downto 0); + ADDRA : in std_logic_vector(8 downto 0); + ADDRB : in std_logic_vector(8 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(31 downto 0); + DIB : in std_logic_vector(31 downto 0); + DIPA : in std_logic_vector(3 downto 0); + DIPB : in std_logic_vector(3 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); +end RAMB16_S36_S36; + +architecture RAMB16_S36_S36 of RAMB16_S36_S36 is + +signal ADDRA_10, ADDRB_10 : std_logic_vector(9 downto 0); +signal DINA, DINB : std_logic_vector(35 downto 0); +signal DOUTA, DOUTB : std_logic_vector(35 downto 0); +signal SSRA_t, SSRB_t : std_logic; +signal WEA_t, WEB_t : std_logic_vector(3 downto 0); + +begin + +ADDRA_10 <= '0' & ADDRA; +ADDRB_10 <= '0' & ADDRB; + +DINA <= DIPA & DIA; +DOPA <= DOUTA(35 downto 32); +DOA <= DOUTA(31 downto 0); + +DINB <= DIPB & DIB; +DOPB <= DOUTB(35 downto 32); +DOB <= DOUTB(31 downto 0); + +SSRA_t <= SSRA; +SSRB_t <= SSRB; +WEA_t <= WEA & WEA & WEA & WEA; +WEB_t <= WEB & WEB & WEB & WEB; + + + + + -- BRAM_TDP_MACRO: True Dual Port RAM + -- Virtex-7 + -- Xilinx HDL Language Template, version 2019.1 + + -- Note - This Unimacro model assumes the port directions to be "downto". + -- Simulation of this model with "to" in the port directions could lead to erroneous results. + + -------------------------------------------------------------------------- + -- DATA_WIDTH_A/B | BRAM_SIZE | RAM Depth | ADDRA/B Width | WEA/B Width -- + -- ===============|===========|===========|===============|=============-- + -- 19-36 | "36Kb" | 1024 | 10-bit | 4-bit -- * using + -- 10-18 | "36Kb" | 2048 | 11-bit | 2-bit -- + -- 10-18 | "18Kb" | 1024 | 10-bit | 2-bit -- + -- 5-9 | "36Kb" | 4096 | 12-bit | 1-bit -- + -- 5-9 | "18Kb" | 2048 | 11-bit | 1-bit -- + -- 3-4 | "36Kb" | 8192 | 13-bit | 1-bit -- + -- 3-4 | "18Kb" | 4096 | 12-bit | 1-bit -- + -- 2 | "36Kb" | 16384 | 14-bit | 1-bit -- + -- 2 | "18Kb" | 8192 | 13-bit | 1-bit -- + -- 1 | "36Kb" | 32768 | 15-bit | 1-bit -- + -- 1 | "18Kb" | 16384 | 14-bit | 1-bit -- + -------------------------------------------------------------------------- + + BRAM_0 : BRAM_TDP_MACRO + generic map ( + BRAM_SIZE => "36Kb", -- Target BRAM, "18Kb" or "36Kb" + DEVICE => "7SERIES", -- Target Device: "VIRTEX5", "VIRTEX6", "7SERIES", "SPARTAN6" + DOA_REG => 0, -- Optional port A output register (0 or 1) + DOB_REG => 0, -- Optional port B output register (0 or 1) + INIT_A => INIT_A, -- Initial values on A output port + INIT_B => INIT_B, -- Initial values on B output port + INIT_FILE => "NONE", + READ_WIDTH_A => 36, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb") + READ_WIDTH_B => 36, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb") + SIM_COLLISION_CHECK => "NONE", + SRVAL_A => SRVAL_A, -- Set/Reset value for A port output + SRVAL_B => SRVAL_A, -- Set/Reset value for B port output + WRITE_MODE_A => WRITE_MODE_A, -- "WRITE_FIRST", "READ_FIRST" or "NO_CHANGE" + WRITE_MODE_B => WRITE_MODE_B, -- "WRITE_FIRST", "READ_FIRST" or "NO_CHANGE" + WRITE_WIDTH_A => 36, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb") + WRITE_WIDTH_B => 36, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb") + -- The following INIT_xx declarations specify the initial contents of the RAM + INIT_00 => INIT_00, + INIT_01 => INIT_01, + INIT_02 => INIT_02, + INIT_03 => INIT_03, + INIT_04 => INIT_04, + INIT_05 => INIT_05, + INIT_06 => INIT_06, + INIT_07 => INIT_07, + INIT_08 => INIT_08, + INIT_09 => INIT_09, + INIT_0A => INIT_0A, + INIT_0B => INIT_0B, + INIT_0C => INIT_0C, + INIT_0D => INIT_0D, + INIT_0E => INIT_0E, + INIT_0F => INIT_0F, + INIT_10 => INIT_10, + INIT_11 => INIT_11, + INIT_12 => INIT_12, + INIT_13 => INIT_13, + INIT_14 => INIT_14, + INIT_15 => INIT_15, + INIT_16 => INIT_16, + INIT_17 => INIT_17, + INIT_18 => INIT_18, + INIT_19 => INIT_19, + INIT_1A => INIT_1A, + INIT_1B => INIT_1B, + INIT_1C => INIT_1C, + INIT_1D => INIT_1D, + INIT_1E => INIT_1E, + INIT_1F => INIT_1F, + INIT_20 => INIT_20, + INIT_21 => INIT_21, + INIT_22 => INIT_22, + INIT_23 => INIT_23, + INIT_24 => INIT_24, + INIT_25 => INIT_25, + INIT_26 => INIT_26, + INIT_27 => INIT_27, + INIT_28 => INIT_28, + INIT_29 => INIT_29, + INIT_2A => INIT_2A, + INIT_2B => INIT_2B, + INIT_2C => INIT_2C, + INIT_2D => INIT_2D, + INIT_2E => INIT_2E, + INIT_2F => INIT_2F, + INIT_30 => INIT_30, + INIT_31 => INIT_31, + INIT_32 => INIT_32, + INIT_33 => INIT_33, + INIT_34 => INIT_34, + INIT_35 => INIT_35, + INIT_36 => INIT_36, + INIT_37 => INIT_37, + INIT_38 => INIT_38, + INIT_39 => INIT_39, + INIT_3A => INIT_3A, + INIT_3B => INIT_3B, + INIT_3C => INIT_3C, + INIT_3D => INIT_3D, + INIT_3E => INIT_3E, + INIT_3F => INIT_3F, + + -- The next set of INIT_xx are valid when configured as 36Kb + INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", + + -- The next set of INITP_xx are for the parity bits + INITP_00 => INITP_00, + INITP_01 => INITP_01, + INITP_02 => INITP_02, + INITP_03 => INITP_03, + INITP_04 => INITP_04, + INITP_05 => INITP_05, + INITP_06 => INITP_06, + INITP_07 => INITP_07, + + -- The next set of INIT_xx are valid when configured as 36Kb + INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000" + ) + port map ( + DOA => DOUTA, -- Output port-A data, width defined by READ_WIDTH_A parameter + DOB => DOUTB, -- Output port-B data, width defined by READ_WIDTH_B parameter + ADDRA => ADDRA_10, -- Input port-A address, width defined by Port A depth + ADDRB => ADDRB_10, -- Input port-B address, width defined by Port B depth + CLKA => CLKA, -- 1-bit input port-A clock + CLKB => CLKB, -- 1-bit input port-B clock + DIA => DINA, -- Input port-A data, width defined by WRITE_WIDTH_A parameter + DIB => DINB, -- Input port-B data, width defined by WRITE_WIDTH_B parameter + ENA => ENA, -- 1-bit input port-A enable + ENB => ENB, -- 1-bit input port-B enable + REGCEA => '1', -- REGCEA, -- 1-bit input port-A output register enable + REGCEB => '1', -- REGCEB, -- 1-bit input port-B output register enable + RSTA => SSRA_t, -- 1-bit input port-A reset + RSTB => SSRB_t, -- 1-bit input port-B reset + WEA => WEA_t, -- Input port-A write enable, width defined by Port A depth + WEB => WEB_t -- Input port-B write enable, width defined by Port B depth + ); + +-- End of BRAM_TDP_MACRO_inst instantiation + + +end RAMB16_S36_S36; diff --git a/rel/src/vhdl/tri/ramb16_s9_s9.vhdl b/rel/src/vhdl/tri/ramb16_s9_s9.vhdl new file mode 100644 index 0000000..ccd6145 --- /dev/null +++ b/rel/src/vhdl/tri/ramb16_s9_s9.vhdl @@ -0,0 +1,384 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; +use ieee.std_logic_1164.all; + +library ibm; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; + +library UNIMACRO; +use UNIMACRO.vcomponents.all; + +entity RAMB16_S9_S9 is + generic ( + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_A : bit_vector := X"000000000"; + INIT_B : bit_vector := X"000000000"; + SIM_COLLISION_CHECK : string := "ALL"; + SRVAL_A : bit_vector := X"000000000"; + SRVAL_B : bit_vector := X"000000000"; + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + port ( + DOA : out std_logic_vector(7 downto 0); + DOB : out std_logic_vector(7 downto 0); + DOPA : out std_logic_vector(0 downto 0); + DOPB : out std_logic_vector(0 downto 0); + ADDRA : in std_logic_vector(10 downto 0); + ADDRB : in std_logic_vector(10 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(7 downto 0); + DIB : in std_logic_vector(7 downto 0); + DIPA : in std_logic_vector(0 downto 0); + DIPB : in std_logic_vector(0 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); +end RAMB16_S9_S9; + +architecture RAMB16_S9_S9 of RAMB16_S9_S9 is + +signal DINA, DINB : std_logic_vector(8 downto 0); +signal DOUTA, DOUTB : std_logic_vector(8 downto 0); +signal SSRA_t, SSRB_t : std_logic; +signal WEA_t, WEB_t : std_logic_vector(0 downto 0); + +begin + +DINA <= DIPA & DIA; +DOPA(0) <= DOUTA(8); +DOA <= DOUTA(7 downto 0); + +DINB <= DIPB & DIB; +DOPB(0) <= DOUTB(8); +DOB <= DOUTB(7 downto 0); + +SSRA_t <= SSRA; +SSRB_t <= SSRB; +WEA_t(0) <= WEA; +WEB_t(0) <= WEB; + + + + + -- BRAM_TDP_MACRO: True Dual Port RAM + -- Virtex-7 + -- Xilinx HDL Language Template, version 2019.1 + + -- Note - This Unimacro model assumes the port directions to be "downto". + -- Simulation of this model with "to" in the port directions could lead to erroneous results. + + -------------------------------------------------------------------------- + -- DATA_WIDTH_A/B | BRAM_SIZE | RAM Depth | ADDRA/B Width | WEA/B Width -- + -- ===============|===========|===========|===============|=============-- + -- 19-36 | "36Kb" | 1024 | 10-bit | 4-bit -- + -- 10-18 | "36Kb" | 2048 | 11-bit | 2-bit -- + -- 10-18 | "18Kb" | 1024 | 10-bit | 2-bit -- + -- 5-9 | "36Kb" | 4096 | 12-bit | 1-bit -- + -- 5-9 | "18Kb" | 2048 | 11-bit | 1-bit -- * using + -- 3-4 | "36Kb" | 8192 | 13-bit | 1-bit -- + -- 3-4 | "18Kb" | 4096 | 12-bit | 1-bit -- + -- 2 | "36Kb" | 16384 | 14-bit | 1-bit -- + -- 2 | "18Kb" | 8192 | 13-bit | 1-bit -- + -- 1 | "36Kb" | 32768 | 15-bit | 1-bit -- + -- 1 | "18Kb" | 16384 | 14-bit | 1-bit -- + -------------------------------------------------------------------------- + + BRAM_0 : BRAM_TDP_MACRO + generic map ( + BRAM_SIZE => "18Kb", -- Target BRAM, "18Kb" or "36Kb" + DEVICE => "7SERIES", -- Target Device: "VIRTEX5", "VIRTEX6", "7SERIES", "SPARTAN6" + DOA_REG => 0, -- Optional port A output register (0 or 1) + DOB_REG => 0, -- Optional port B output register (0 or 1) + INIT_A => INIT_A, -- Initial values on A output port + INIT_B => INIT_B, -- Initial values on B output port + INIT_FILE => "NONE", + READ_WIDTH_A => 9, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb") + READ_WIDTH_B => 9, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb") + SIM_COLLISION_CHECK => "NONE", + SRVAL_A => SRVAL_A, -- Set/Reset value for A port output + SRVAL_B => SRVAL_A, -- Set/Reset value for B port output + WRITE_MODE_A => WRITE_MODE_A, -- "WRITE_FIRST", "READ_FIRST" or "NO_CHANGE" + WRITE_MODE_B => WRITE_MODE_B, -- "WRITE_FIRST", "READ_FIRST" or "NO_CHANGE" + WRITE_WIDTH_A => 9, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb") + WRITE_WIDTH_B => 9, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb") + -- The following INIT_xx declarations specify the initial contents of the RAM + INIT_00 => INIT_00, + INIT_01 => INIT_01, + INIT_02 => INIT_02, + INIT_03 => INIT_03, + INIT_04 => INIT_04, + INIT_05 => INIT_05, + INIT_06 => INIT_06, + INIT_07 => INIT_07, + INIT_08 => INIT_08, + INIT_09 => INIT_09, + INIT_0A => INIT_0A, + INIT_0B => INIT_0B, + INIT_0C => INIT_0C, + INIT_0D => INIT_0D, + INIT_0E => INIT_0E, + INIT_0F => INIT_0F, + INIT_10 => INIT_10, + INIT_11 => INIT_11, + INIT_12 => INIT_12, + INIT_13 => INIT_13, + INIT_14 => INIT_14, + INIT_15 => INIT_15, + INIT_16 => INIT_16, + INIT_17 => INIT_17, + INIT_18 => INIT_18, + INIT_19 => INIT_19, + INIT_1A => INIT_1A, + INIT_1B => INIT_1B, + INIT_1C => INIT_1C, + INIT_1D => INIT_1D, + INIT_1E => INIT_1E, + INIT_1F => INIT_1F, + INIT_20 => INIT_20, + INIT_21 => INIT_21, + INIT_22 => INIT_22, + INIT_23 => INIT_23, + INIT_24 => INIT_24, + INIT_25 => INIT_25, + INIT_26 => INIT_26, + INIT_27 => INIT_27, + INIT_28 => INIT_28, + INIT_29 => INIT_29, + INIT_2A => INIT_2A, + INIT_2B => INIT_2B, + INIT_2C => INIT_2C, + INIT_2D => INIT_2D, + INIT_2E => INIT_2E, + INIT_2F => INIT_2F, + INIT_30 => INIT_30, + INIT_31 => INIT_31, + INIT_32 => INIT_32, + INIT_33 => INIT_33, + INIT_34 => INIT_34, + INIT_35 => INIT_35, + INIT_36 => INIT_36, + INIT_37 => INIT_37, + INIT_38 => INIT_38, + INIT_39 => INIT_39, + INIT_3A => INIT_3A, + INIT_3B => INIT_3B, + INIT_3C => INIT_3C, + INIT_3D => INIT_3D, + INIT_3E => INIT_3E, + INIT_3F => INIT_3F, + + -- The next set of INIT_xx are valid when configured as 36Kb + INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", + + -- The next set of INITP_xx are for the parity bits + INITP_00 => INITP_00, + INITP_01 => INITP_01, + INITP_02 => INITP_02, + INITP_03 => INITP_03, + INITP_04 => INITP_04, + INITP_05 => INITP_05, + INITP_06 => INITP_06, + INITP_07 => INITP_07, + + -- The next set of INIT_xx are valid when configured as 36Kb + INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000" + ) + port map ( + DOA => DOUTA, -- Output port-A data, width defined by READ_WIDTH_A parameter + DOB => DOUTB, -- Output port-B data, width defined by READ_WIDTH_B parameter + ADDRA => ADDRA, -- Input port-A address, width defined by Port A depth + ADDRB => ADDRB, -- Input port-B address, width defined by Port B depth + CLKA => CLKA, -- 1-bit input port-A clock + CLKB => CLKB, -- 1-bit input port-B clock + DIA => DINA, -- Input port-A data, width defined by WRITE_WIDTH_A parameter + DIB => DINB, -- Input port-B data, width defined by WRITE_WIDTH_B parameter + ENA => ENA, -- 1-bit input port-A enable + ENB => ENB, -- 1-bit input port-B enable + REGCEA => '1', -- REGCEA, -- 1-bit input port-A output register enable + REGCEB => '1', -- REGCEB, -- 1-bit input port-B output register enable + RSTA => SSRA_t, -- 1-bit input port-A reset + RSTB => SSRB_t, -- 1-bit input port-B reset + WEA => WEA_t, -- Input port-A write enable, width defined by Port A depth + WEB => WEB_t -- Input port-B write enable, width defined by Port B depth + ); + +-- End of BRAM_TDP_MACRO_inst instantiation + + +end RAMB16_S9_S9; diff --git a/rel/src/vhdl/tri/tri_128x168_1w_0.vhdl b/rel/src/vhdl/tri/tri_128x168_1w_0.vhdl new file mode 100644 index 0000000..7383b63 --- /dev/null +++ b/rel/src/vhdl/tri/tri_128x168_1w_0.vhdl @@ -0,0 +1,343 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- *!**************************************************************** +-- *! FILENAME : tri_128x168_1w_0.vhdl +-- *! DESCRIPTION : 128 Entry x 168 bit x 1 way array +-- *! +-- *!**************************************************************** + +library ieee; use ieee.std_logic_1164.all ; +library ibm; + use ibm.std_ulogic_support.all ; + use ibm.std_ulogic_function_support.all; +library support; + use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; +-- pragma translate_off +-- pragma translate_on + +entity tri_128x168_1w_0 is + generic (addressable_ports : positive := 128; -- number of addressable register in this array + addressbus_width : positive := 7; -- width of the bus to address all ports (2^addressbus_width >= addressable_ports) + port_bitwidth : positive := 168; -- bitwidth of ports + ways : positive := 1; -- number of ways + expand_type : integer := 1); -- 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) + port ( + -- POWER PINS + gnd : inout power_logic; + vdd : inout power_logic; + vcs : inout power_logic; + + -- CLOCK and CLOCKCONTROL ports + nclk : in clk_logic; + act : in std_ulogic; + ccflush_dc : in std_ulogic; + scan_dis_dc_b : in std_ulogic; + scan_diag_dc : in std_ulogic; + + abst_scan_in : in std_ulogic; + repr_scan_in : in std_ulogic; + time_scan_in : in std_ulogic; + abst_scan_out : out std_ulogic; + repr_scan_out : out std_ulogic; + time_scan_out : out std_ulogic; + + lcb_d_mode_dc : in std_ulogic; + lcb_clkoff_dc_b : in std_ulogic; + lcb_act_dis_dc : in std_ulogic; + lcb_mpw1_dc_b : in std_ulogic_vector(0 to 4); + lcb_mpw2_dc_b : in std_ulogic; + lcb_delay_lclkr_dc : in std_ulogic_vector(0 to 4); + + lcb_sg_1 : in std_ulogic; + lcb_time_sg_0 : in std_ulogic; + lcb_repr_sg_0 : in std_ulogic; + + lcb_abst_sl_thold_0 : in std_ulogic; + lcb_repr_sl_thold_0 : in std_ulogic; + lcb_time_sl_thold_0 : in std_ulogic; + lcb_ary_nsl_thold_0 : in std_ulogic; + lcb_bolt_sl_thold_0 : in std_ulogic; -- thold for any regs inside backend + + tc_lbist_ary_wrt_thru_dc : in std_ulogic; + abist_en_1 : in std_ulogic; + din_abist : in std_ulogic_vector(0 to 3); + abist_cmp_en : in std_ulogic; + abist_raw_b_dc : in std_ulogic; + data_cmp_abist : in std_ulogic_vector(0 to 3); + addr_abist : in std_ulogic_vector(0 to 6); + r_wb_abist : in std_ulogic; + + -- BOLT-ON + pc_bo_enable_2 : in std_ulogic; -- general bolt-on enable, probably DC + pc_bo_reset : in std_ulogic; -- execute sticky bit decode + pc_bo_unload : in std_ulogic; + pc_bo_repair : in std_ulogic; -- load repair reg + pc_bo_shdata : in std_ulogic; -- shift data for timing write + pc_bo_select : in std_ulogic; -- select for mask and hier writes + bo_pc_failout : out std_ulogic; -- fail/no-fix reg + bo_pc_diagloop : out std_ulogic; + tri_lcb_mpw1_dc_b : in std_ulogic; + tri_lcb_mpw2_dc_b : in std_ulogic; + tri_lcb_delay_lclkr_dc : in std_ulogic; + tri_lcb_clkoff_dc_b : in std_ulogic; + tri_lcb_act_dis_dc : in std_ulogic; + + -- PORTS + write_enable : in std_ulogic; + addr : in std_ulogic_vector (0 to addressbus_width-1); + data_in : in std_ulogic_vector (0 to port_bitwidth-1); + data_out : out std_ulogic_vector(0 to port_bitwidth-1) +); + +end entity tri_128x168_1w_0; + +architecture tri_128x168_1w_0 of tri_128x168_1w_0 is + +constant wga_base_width : integer := 168; +constant wga_width_mult : integer := (port_bitwidth*ways-1)/wga_base_width + 1; +constant ramb_base_width : integer := 36; +constant ramb_base_addr : integer := 9; +constant ramb_width_mult : integer := (port_bitwidth-1)/ramb_base_width + 1; -- # of RAMB's per way +-- added way constant below to fake out way-based generates and ranges +constant way : std_ulogic_vector(0 to 0) := "0"; + + +type RAMB_DATA_ARRAY is array (natural range <>) of std_logic_vector(0 to (ramb_base_width*ramb_width_mult - 1)); + + +begin -- tri_128x168_1w_0 + + -- synopsys translate_off + um: if expand_type = 0 generate + signal tiup : std_ulogic; + signal tidn : std_ulogic; + + signal addr_l2 : std_ulogic_vector (0 TO addressbus_width-1); + signal write_enable_d : std_ulogic; + signal write_enable_l2 : std_ulogic; + signal data_in_l2 : std_ulogic_vector(0 to port_bitwidth-1); + signal array_d : std_ulogic_vector(0 to addressable_ports*port_bitwidth*ways-1); + signal array_l2 : std_ulogic_vector(0 to addressable_ports*port_bitwidth*ways-1); + begin + tiup <= '1'; + tidn <= '0'; + + addr_latch: tri_rlmreg_p + generic map (width => addr'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act, + scin => (others => '0'), + scout => open, + din => addr, + dout => addr_l2 ); + + + write_enable_latch: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + scin => tidn, + scout => open, + din => write_enable_d, + dout => write_enable_l2 ); + + data_in_latch: tri_rlmreg_p + generic map (width => port_bitwidth, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act, + scin => (others => '0'), + scout => open, + din => data_in, + dout => data_in_l2 ); + + array_latch: tri_rlmreg_p + generic map (width => addressable_ports*port_bitwidth*ways, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + scin => (others => '0'), + scout => open, + din => array_d, + dout => array_l2 ); + + write_enable_d <= act and write_enable; + + ww: for w in 0 to ways-1 generate + begin + wy: for y in 0 to addressable_ports-1 generate + begin + wx: for x in 0 to port_bitwidth-1 generate + begin + array_d(y*port_bitwidth*ways+w*port_bitwidth+x) <= + data_in_l2(x) when (( write_enable_l2 and addr_l2 = tconv(y, addressbus_width)) = '1') + else array_l2(y*port_bitwidth*ways+w*port_bitwidth+x); + + end generate wx; + end generate wy; + end generate ww; + + data_out <= array_l2( tconv(addr_l2)*port_bitwidth*ways to tconv(addr_l2)*port_bitwidth*ways+port_bitwidth*ways-1 ); + + abst_scan_out <= abst_scan_in; + repr_scan_out <= repr_scan_in; + time_scan_out <= time_scan_in; + + bo_pc_failout <= '0'; + bo_pc_diagloop <= '0'; + + end generate um; + -- synopsys translate_on + + + a: if expand_type = 1 generate + component RAMB16_S36_S36 + -- pragma translate_off + generic( + SIM_COLLISION_CHECK : string := "none"); -- all, none, warning_only, GENERATE_X_ONLY + -- pragma translate_on + port( + DOA : out std_logic_vector(31 downto 0); + DOB : out std_logic_vector(31 downto 0); + DOPA : out std_logic_vector(3 downto 0); + DOPB : out std_logic_vector(3 downto 0); + ADDRA : in std_logic_vector(8 downto 0); + ADDRB : in std_logic_vector(8 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(31 downto 0); + DIB : in std_logic_vector(31 downto 0); + DIPA : in std_logic_vector(3 downto 0); + DIPB : in std_logic_vector(3 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic); + end component; + + -- pragma translate_off + -- pragma translate_on + + signal ramb_data_in : std_logic_vector(0 to (ramb_base_width*ramb_width_mult - 1)); + signal ramb_data_out : RAMB_DATA_ARRAY(way'range); + signal ramb_addr : std_logic_vector(0 to ramb_base_addr - 1); + + signal write : std_ulogic_vector(way'range); + signal tidn : std_ulogic; + signal unused : std_ulogic; + -- synopsys translate_off + -- synopsys translate_on + begin + + tidn <= '0'; + + add0: if (addressbus_width < ramb_base_addr) generate + begin + ramb_addr(0 to (ramb_base_addr-addressbus_width-1)) <= (others => '0'); + ramb_addr(ramb_base_addr-addressbus_width to ramb_base_addr-1) <= tconv( addr ); + end generate; + add1: if (addressbus_width >= ramb_base_addr) generate + begin + ramb_addr <= tconv( addr(addressbus_width-ramb_base_addr to addressbus_width-1) ); + end generate; + + din: for i in ramb_data_in'range generate + begin + R0: if(i < port_bitwidth) generate begin ramb_data_in(i) <= data_in(i); end generate; + R1: if(i >= port_bitwidth) generate begin ramb_data_in(i) <= '0'; end generate; + end generate; + + aw: for w in way'range generate begin + write(w) <= write_enable; + + ax: for x in 0 to (ramb_width_mult - 1) generate begin + ram: RAMB16_S36_S36 + -- pragma translate_off + generic map( + sim_collision_check => "none") + -- pragma translate_on + port map( + DOA => ramb_data_out(w)(x*ramb_base_width to x*ramb_base_width+31), + DOB => open, + DOPA => ramb_data_out(w)(x*ramb_base_width+32 to x*ramb_base_width+35), + DOPB => open, + ADDRA => ramb_addr, + ADDRB => ramb_addr, + CLKA => nclk.clk, + CLKB => tidn, + DIA => ramb_data_in(x*ramb_base_width to x*ramb_base_width+31), + DIB => ramb_data_in(x*ramb_base_width to x*ramb_base_width+31), + DIPA => ramb_data_in(x*ramb_base_width+32 to x*ramb_base_width+35), + DIPB => ramb_data_in(x*ramb_base_width+32 to x*ramb_base_width+35), + ENA => act, + ENB => tidn, + SSRA => nclk.sreset, + SSRB => tidn, + WEA => write(w), + WEB => tidn + ); + + end generate ax; + + data_out(w*port_bitwidth to ((w+1)*port_bitwidth)-1 ) <= tconv( ramb_data_out(w)(0 to port_bitwidth-1) ); + + end generate aw; + + abst_scan_out <= abst_scan_in; + repr_scan_out <= repr_scan_in; + time_scan_out <= time_scan_in; + + bo_pc_failout <= '0'; + bo_pc_diagloop <= '0'; + + unused <= or_reduce( std_ulogic_vector(ramb_data_out(0)(port_bitwidth to ramb_base_width*ramb_width_mult - 1)) + & ccflush_dc & scan_dis_dc_b & scan_diag_dc & lcb_d_mode_dc + & lcb_clkoff_dc_b & lcb_act_dis_dc & lcb_mpw1_dc_b & lcb_mpw2_dc_b + & lcb_delay_lclkr_dc & lcb_sg_1 & lcb_time_sg_0 & lcb_repr_sg_0 + & lcb_abst_sl_thold_0 & lcb_repr_sl_thold_0 & lcb_time_sl_thold_0 + & lcb_ary_nsl_thold_0 & lcb_bolt_sl_thold_0 & tc_lbist_ary_wrt_thru_dc + & abist_en_1 & din_abist & abist_cmp_en & abist_raw_b_dc & data_cmp_abist + & addr_abist & r_wb_abist & pc_bo_enable_2 & pc_bo_reset + & pc_bo_unload & pc_bo_repair & pc_bo_shdata & pc_bo_select + & tri_lcb_mpw1_dc_b & tri_lcb_mpw2_dc_b & tri_lcb_delay_lclkr_dc + & tri_lcb_clkoff_dc_b & tri_lcb_act_dis_dc ); + + end generate a; + +end tri_128x168_1w_0; diff --git a/rel/src/vhdl/tri/tri_128x16_1r1w_1.vhdl b/rel/src/vhdl/tri/tri_128x16_1r1w_1.vhdl new file mode 100644 index 0000000..4cbff46 --- /dev/null +++ b/rel/src/vhdl/tri/tri_128x16_1r1w_1.vhdl @@ -0,0 +1,463 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee; use ieee.std_logic_1164.all; +library support; + use support.power_logic_pkg.all; +library ibm; + use ibm.std_ulogic_support.all ; + use ibm.std_ulogic_function_support.all; +library tri; use tri.tri_latches_pkg.all; + +entity tri_128x16_1r1w_1 is + generic (addressable_ports : positive := 128; -- number of addressable register in this array + addressbus_width : positive := 7; -- width of the bus to address all ports (2^addressbus_width >= addressable_ports) + port_bitwidth : positive := 16; -- bitwidth of ports + ways : positive := 1; -- number of ways + expand_type : integer := 1); -- 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG), 3 = mpg latches +port ( + -- POWER PINS + vdd : INOUT power_logic; + vcs : INOUT power_logic; + gnd : INOUT power_logic; + + nclk : IN clk_logic; + + rd_act : IN std_ulogic; + wr_act : IN std_ulogic; + + -- DC TEST PINS + lcb_d_mode_dc : IN std_ulogic; + lcb_clkoff_dc_b : IN std_ulogic; + lcb_mpw1_dc_b : IN std_ulogic_vector(0 TO 4); + lcb_mpw2_dc_b : IN std_ulogic; + lcb_delay_lclkr_dc : IN std_ulogic_vector(0 TO 4); + + ccflush_dc : IN std_ulogic; + scan_dis_dc_b : IN std_ulogic; + scan_diag_dc : IN std_ulogic; + func_scan_in : IN std_ulogic; + func_scan_out : OUT std_ulogic; + + lcb_sg_0 : IN std_ulogic; + lcb_sl_thold_0_b : IN std_ulogic; + lcb_time_sl_thold_0 : IN std_ulogic; + lcb_abst_sl_thold_0 : IN std_ulogic; + lcb_ary_nsl_thold_0 : IN std_ulogic; + lcb_repr_sl_thold_0 : IN std_ulogic; + time_scan_in : IN std_ulogic; + time_scan_out : OUT std_ulogic; + abst_scan_in : IN std_ulogic; + abst_scan_out : OUT std_ulogic; + repr_scan_in : IN std_ulogic; + repr_scan_out : OUT std_ulogic; + + abist_di : IN std_ulogic_vector(0 TO 3); + abist_bw_odd : IN std_ulogic; + abist_bw_even : IN std_ulogic; + abist_wr_adr : IN std_ulogic_vector(0 TO 6); + wr_abst_act : IN std_ulogic; + abist_rd0_adr : IN std_ulogic_vector(0 TO 6); + rd0_abst_act : IN std_ulogic; + tc_lbist_ary_wrt_thru_dc : IN std_ulogic; + abist_ena_1 : IN std_ulogic; + abist_g8t_rd0_comp_ena : IN std_ulogic; + abist_raw_dc_b : IN std_ulogic; + obs0_abist_cmp : IN std_ulogic_vector(0 TO 3); + + -- BOLT-ON + lcb_bolt_sl_thold_0 : in std_ulogic; + pc_bo_enable_2 : in std_ulogic; -- general bolt-on enable + pc_bo_reset : in std_ulogic; -- reset + pc_bo_unload : in std_ulogic; -- unload sticky bits + pc_bo_repair : in std_ulogic; -- execute sticky bit decode + pc_bo_shdata : in std_ulogic; -- shift data for timing write and diag loop + pc_bo_select : in std_ulogic; -- select for mask and hier writes + bo_pc_failout : out std_ulogic; -- fail/no-fix reg + bo_pc_diagloop : out std_ulogic; + tri_lcb_mpw1_dc_b : in std_ulogic; + tri_lcb_mpw2_dc_b : in std_ulogic; + tri_lcb_delay_lclkr_dc : in std_ulogic; + tri_lcb_clkoff_dc_b : in std_ulogic; + tri_lcb_act_dis_dc : in std_ulogic; + + bw : IN std_ulogic_vector( 0 TO 15 ); + wr_adr : IN std_ulogic_vector( 0 TO 6 ); + rd_adr : IN std_ulogic_vector( 0 TO 6 ); + di : IN std_ulogic_vector( 0 TO 15 ); + do : OUT std_ulogic_vector( 0 TO 15 ) + + ); + + -- synopsys translate_off + -- synopsys translate_on + +end entity tri_128x16_1r1w_1; + +architecture tri_128x16_1r1w_1 of tri_128x16_1r1w_1 is + +begin + + -- synopsys translate_off + um: if expand_type = 0 generate + + constant rd_addr_offset : natural := 0; + constant wr_addr_offset : natural := rd_addr_offset + addressbus_width; + constant write_enable_offset : natural := wr_addr_offset + addressbus_width; + constant data_in_offset : natural := write_enable_offset + port_bitwidth; + constant data_out_offset : natural := data_in_offset + port_bitwidth; + constant array_offset : natural := data_out_offset + port_bitwidth; + constant scan_right : natural := array_offset + addressable_ports*port_bitwidth*ways - 1; + + signal tiup : std_ulogic; + signal tidn : std_ulogic; + + signal rd_addr_l2 : std_ulogic_vector (0 TO addressbus_width-1); + signal wr_addr_l2 : std_ulogic_vector (0 TO addressbus_width-1); + signal write_enable_d : std_ulogic_vector(0 to port_bitwidth-1); + signal write_enable_l2 : std_ulogic_vector(0 to port_bitwidth-1); + signal data_in_l2 : std_ulogic_vector(0 to port_bitwidth-1); + signal data_out_d : std_ulogic_vector(0 to port_bitwidth-1); + signal data_out_l2 : std_ulogic_vector(0 to port_bitwidth-1); + signal array_d : std_ulogic_vector(0 to addressable_ports*port_bitwidth*ways-1); + signal array_l2 : std_ulogic_vector(0 to addressable_ports*port_bitwidth*ways-1); + signal siv : std_ulogic_vector(0 to scan_right); + signal sov : std_ulogic_vector(0 to scan_right); + begin + tiup <= '1'; + tidn <= '0'; + + rd_addr_latch: tri_rlmreg_p + generic map (width => rd_adr'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rd_act, + scin => siv(rd_addr_offset to rd_addr_offset+rd_addr_l2'length-1), + scout => sov(rd_addr_offset to rd_addr_offset+rd_addr_l2'length-1), + din => rd_adr, + dout => rd_addr_l2 ); + + wr_addr_latch: tri_rlmreg_p + generic map (width => wr_adr'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => wr_act, + scin => siv(wr_addr_offset to wr_addr_offset+wr_addr_l2'length-1), + scout => sov(wr_addr_offset to wr_addr_offset+wr_addr_l2'length-1), + din => wr_adr, + dout => wr_addr_l2 ); + + + + write_enable_latch: tri_rlmreg_p + generic map (width => port_bitwidth, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => wr_act, + scin => siv(write_enable_offset to write_enable_offset+write_enable_l2'length-1), + scout => sov(write_enable_offset to write_enable_offset+write_enable_l2'length-1), + din => write_enable_d, + dout => write_enable_l2 ); + + data_in_latch: tri_rlmreg_p + generic map (width => port_bitwidth, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => wr_act, + scin => siv(data_in_offset to data_in_offset+data_in_l2'length-1), + scout => sov(data_in_offset to data_in_offset+data_in_l2'length-1), + din => di, + dout => data_in_l2 ); + + data_out_latch: tri_rlmreg_p + generic map (width => port_bitwidth, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => wr_act, + scin => siv(data_out_offset to data_out_offset+data_out_l2'length-1), + scout => sov(data_out_offset to data_out_offset+data_out_l2'length-1), + din => data_out_d, + dout => data_out_l2 ); + + array_latch: tri_rlmreg_p + generic map (width => addressable_ports*port_bitwidth*ways, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + scin => siv(array_offset to array_offset+array_l2'length-1), + scout => sov(array_offset to array_offset+array_l2'length-1), + din => array_d, + dout => array_l2 ); + + write_enable_d <= bw when wr_act='1' else (others => '0'); + + ww: for w in 0 to ways-1 generate + begin + wy: for y in 0 to addressable_ports-1 generate + begin + wx: for x in 0 to port_bitwidth-1 generate + begin + array_d(y*port_bitwidth*ways+w*port_bitwidth+x) <= + data_in_l2(x) when ( write_enable_l2(x)='1' and wr_addr_l2 = tconv(y, addressbus_width)) + else array_l2(y*port_bitwidth*ways+w*port_bitwidth+x); + + end generate wx; + end generate wy; + end generate ww; + + data_out_d(0) <= array_l2( tconv(rd_addr_l2)*port_bitwidth); + data_out_d(1) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+1); + data_out_d(2) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+2); + data_out_d(3) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+3); + data_out_d(4) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+4); + data_out_d(5) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+5); + data_out_d(6) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+6); + data_out_d(7) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+7); + data_out_d(8) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+8); + data_out_d(9) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+9); + data_out_d(10) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+10); + data_out_d(11) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+11); + data_out_d(12) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+12); + data_out_d(13) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+13); + data_out_d(14) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+14); + data_out_d(15) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+15); + + do(0) <= array_l2( tconv(rd_addr_l2)*port_bitwidth); + do(1) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+1); + do(2) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+2); + do(3) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+3); + do(4) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+4); + do(5) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+5); + do(6) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+6); + do(7) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+7); + do(8) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+8); + do(9) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+9); + do(10) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+10); + do(11) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+11); + do(12) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+12); + do(13) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+13); + do(14) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+14); + do(15) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+15); + + siv(0 to scan_right) <= sov(1 to scan_right) & func_scan_in; + func_scan_out <= sov(0); + + time_scan_out <= time_scan_in; + abst_scan_out <= abst_scan_in; + repr_scan_out <= repr_scan_in; + + bo_pc_failout <= '0'; + bo_pc_diagloop <= '0'; + + end generate um; + -- synopsys translate_on + + +a : if expand_type = 1 generate + +component RAMB16_S36_S36 +-- pragma translate_off + generic( + SIM_COLLISION_CHECK : string := "none"); -- all, none, warning_only, GENERATE_X_ONLY +-- pragma translate_on + port( + DOA : out std_logic_vector(31 downto 0); + DOB : out std_logic_vector(31 downto 0); + DOPA : out std_logic_vector(3 downto 0); + DOPB : out std_logic_vector(3 downto 0); + ADDRA : in std_logic_vector(8 downto 0); + ADDRB : in std_logic_vector(8 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(31 downto 0); + DIB : in std_logic_vector(31 downto 0); + DIPA : in std_logic_vector(3 downto 0); + DIPB : in std_logic_vector(3 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic); +end component; + + +signal clk,clk2x : std_ulogic; +signal b0addra, b0addrb : std_ulogic_vector(0 to 8); +signal wea, web : std_ulogic; +signal wren_a : std_ulogic; +-- Latches +signal reset_q : std_ulogic; +signal gate_fq, gate_d : std_ulogic; +signal r_data_out_1_d, r_data_out_1_fq : std_ulogic_vector(0 to 35); +signal w_data_in_0 : std_ulogic_vector(0 to 35); + +signal r_data_out_0_bram : std_logic_vector(0 to 35); +signal r_data_out_1_bram : std_logic_vector(0 to 35); + +signal toggle_d : std_ulogic; +signal toggle_q : std_ulogic; +signal toggle2x_d : std_ulogic; +signal toggle2x_q : std_ulogic; + +signal unused : std_ulogic; +-- synopsys translate_off +-- synopsys translate_on + +begin + +clk <= nclk.clk; +clk2x <= nclk.clk2x; + +rlatch: process (clk) begin + if(rising_edge(clk)) then + reset_q <= nclk.sreset; + end if; +end process; + +-- +-- NEW clk2x gate logic start +-- + +tlatch: process (nclk.clk,reset_q) +begin + if(rising_edge(nclk.clk)) then + if (reset_q = '1') then + toggle_q <= '1'; + else + toggle_q <= toggle_d; + end if; + end if; +end process; + +flatch: process (nclk.clk2x) +begin + if(rising_edge(nclk.clk2x)) then + toggle2x_q <= toggle2x_d; + gate_fq <= gate_d; + r_data_out_1_fq <= r_data_out_1_d; + end if; +end process; + +toggle_d <= not toggle_q; +toggle2x_d <= toggle_q; + +gate_d <= not(toggle_q xor toggle2x_q); + +b0addra(2 to 8) <= wr_adr; +b0addrb(2 to 8) <= rd_adr; + +-- Unused Address Bits +b0addra(0 to 1) <= "00"; +b0addrb(0 to 1) <= "00"; + + + +-- port a is a read-modify-write port +wren_a <= '1' when bw /= "0000000000000000" else '0'; +wea <= wren_a and not(gate_fq); -- write in 2nd half of nclk +web <= '0'; +w_data_in_0(0) <= di(0) when bw(0)='1' else r_data_out_0_bram(0); +w_data_in_0(1) <= di(1) when bw(1)='1' else r_data_out_0_bram(1); +w_data_in_0(2) <= di(2) when bw(2)='1' else r_data_out_0_bram(2); +w_data_in_0(3) <= di(3) when bw(3)='1' else r_data_out_0_bram(3); +w_data_in_0(4) <= di(4) when bw(4)='1' else r_data_out_0_bram(4); +w_data_in_0(5) <= di(5) when bw(5)='1' else r_data_out_0_bram(5); +w_data_in_0(6) <= di(6) when bw(6)='1' else r_data_out_0_bram(6); +w_data_in_0(7) <= di(7) when bw(7)='1' else r_data_out_0_bram(7); +w_data_in_0(8) <= di(8) when bw(8)='1' else r_data_out_0_bram(8); +w_data_in_0(9) <= di(9) when bw(9)='1' else r_data_out_0_bram(9); +w_data_in_0(10) <= di(10) when bw(10)='1' else r_data_out_0_bram(10); +w_data_in_0(11) <= di(11) when bw(11)='1' else r_data_out_0_bram(11); +w_data_in_0(12) <= di(12) when bw(12)='1' else r_data_out_0_bram(12); +w_data_in_0(13) <= di(13) when bw(13)='1' else r_data_out_0_bram(13); +w_data_in_0(14) <= di(14) when bw(14)='1' else r_data_out_0_bram(14); +w_data_in_0(15) <= di(15) when bw(15)='1' else r_data_out_0_bram(15); +w_data_in_0(16 to 35) <= (others => '0'); + +r_data_out_1_d <= std_ulogic_vector(r_data_out_1_bram); + +bram0a : ramb16_s36_s36 +-- pragma translate_off +generic map( + sim_collision_check => "none") +-- pragma translate_on +port map( + clka => clk2x, + clkb => clk2x, + ssra => reset_q, + ssrb => reset_q, + addra => std_logic_vector(b0addra), + addrb => std_logic_vector(b0addrb), + dia => std_logic_vector(w_data_in_0(0 to 31)), + dib => (others => '0'), + doa => r_data_out_0_bram(0 to 31), + dob => r_data_out_1_bram(0 to 31), + dopa => r_data_out_0_bram(32 to 35), + dopb => r_data_out_1_bram(32 to 35), + dipa => std_logic_vector(w_data_in_0(32 to 35)), + dipb => (others => '0'), + ena => '1', + enb => '1', + wea => wea, + web => web + ); + + +do <= r_data_out_1_fq(0 to 15); + +func_scan_out <= func_scan_in; +time_scan_out <= time_scan_in; +abst_scan_out <= abst_scan_in; +repr_scan_out <= repr_scan_in; + +bo_pc_failout <= '0'; +bo_pc_diagloop <= '0'; + +unused <= or_reduce( std_ulogic_vector(r_data_out_0_bram(16 to 35)) & rd_act & wr_act + & lcb_d_mode_dc & lcb_clkoff_dc_b & lcb_mpw1_dc_b & lcb_mpw2_dc_b + & lcb_delay_lclkr_dc & ccflush_dc & scan_dis_dc_b & scan_diag_dc + & lcb_sg_0 & lcb_sl_thold_0_b & lcb_time_sl_thold_0 & lcb_abst_sl_thold_0 + & lcb_ary_nsl_thold_0 & lcb_repr_sl_thold_0 & abist_di & abist_bw_odd + & abist_bw_even & abist_wr_adr & wr_abst_act & abist_rd0_adr & rd0_abst_act + & tc_lbist_ary_wrt_thru_dc & abist_ena_1 & abist_g8t_rd0_comp_ena + & abist_raw_dc_b & obs0_abist_cmp & lcb_bolt_sl_thold_0 & pc_bo_enable_2 + & pc_bo_reset & pc_bo_unload & pc_bo_repair & pc_bo_shdata & pc_bo_select + & tri_lcb_mpw1_dc_b & tri_lcb_mpw2_dc_b & tri_lcb_delay_lclkr_dc + & tri_lcb_clkoff_dc_b & tri_lcb_act_dis_dc ); + +end generate a; + + +end architecture tri_128x16_1r1w_1; diff --git a/rel/src/vhdl/tri/tri_144x78_2r2w.vhdl b/rel/src/vhdl/tri/tri_144x78_2r2w.vhdl new file mode 100644 index 0000000..bd40f2f --- /dev/null +++ b/rel/src/vhdl/tri/tri_144x78_2r2w.vhdl @@ -0,0 +1,449 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee,ibm,support,tri; +use ieee.std_logic_1164.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_support.all; +use support.power_logic_pkg.all; +use tri.tri_latches_pkg.all; + +entity tri_144x78_2r2w is +generic( + expand_type : integer := 1); +port ( + -- Clocks and Scan Cntls ----------------------------------------------------------------- + vdd :inout power_logic; + gnd :inout power_logic; + nclk :in clk_logic; + abist_en :in std_ulogic; -- when abist tested + abist_raw_dc_b :in std_ulogic; -- during abist (disables the xor in miser) + r0e_abist_comp_en :in std_ulogic; -- when abist tested + r1e_abist_comp_en :in std_ulogic; -- when abist tested + lbist_en :in std_ulogic; -- for LBIST mode + + -- LCB Signals --------------- Rd & Wr domains use same LCB controls ----------------------- + lcb_act_dis_dc :in std_ulogic; + lcb_clkoff_dc_b :in std_ulogic_vector(0 to 1); + --0 other + lcb_d_mode_dc :in std_ulogic; + --0 all other + --1 read address late + lcb_delay_lclkr_dc :in std_ulogic_vector(0 to 9); -- + -- 0: read clk lcb + -- 1: read addr lcb + -- 2: write clk E lcb + -- 3: write addr E lcb + -- 4: write clk L lcb + -- 5: write addr L lcb + -- 6: read data 0 lcb + -- 7: read data 1 lcb + -- 8: write data E lcb + -- 9: write data L lcb + lcb_fce_0 :in std_ulogic; + lcb_mpw1_dc_b :in std_ulogic_vector(1 to 9); -- + -- 0: none + -- 1: read addr lcb + -- 2: write clk E lcb + -- 3: write addr E lcb + -- 4: write clk L lcb + -- 5: write addr L lcb + -- 6: read data 0 lcb + -- 7: write data 1 lcb + -- 8: write data E lcb + -- 9: write data L lcb + lcb_mpw2_dc_b :in std_ulogic; + lcb_scan_diag_dc :in std_ulogic; + lcb_scan_dis_dc_b :in std_ulogic; + lcb_sg_0 :in std_ulogic; + lcb_time_sg_0 :in std_ulogic; + lcb_obs0_sg_0 :in std_ulogic; + lcb_obs1_sg_0 :in std_ulogic; + lcb_obs0_sl_thold_0 :in std_ulogic; + lcb_obs1_sl_thold_0 :in std_ulogic; + + lcb_abst_sl_thold_0 :in std_ulogic; + lcb_time_sl_thold_0 :in std_ulogic; + lcb_ary_nsl_thold_0 :in std_ulogic; + + -- Scan In ---------------------------------------------------------- + r_scan_in :in std_ulogic; + r_scan_out :out std_ulogic; + w_scan_in :in std_ulogic; + w_scan_out :out std_ulogic; + time_scan_in :in std_ulogic; + time_scan_out :out std_ulogic; + obs0_scan_in :in std_ulogic; + obs0_scan_out :out std_ulogic; + obs1_scan_in :in std_ulogic; + obs1_scan_out :out std_ulogic; + + -- BOLT-ON + lcb_bolt_sl_thold_0 :in std_ulogic; + pc_bo_enable_2 :in std_ulogic; -- general bolt-on enable, probably DC + pc_bo_reset :in std_ulogic; -- execute sticky bit decode + pc_bo_unload :in std_ulogic; + pc_bo_load :in std_ulogic; + pc_bo_shdata :in std_ulogic; -- shift data for timing write + pc_bo_select :in std_ulogic; -- select for mask and hier writes + bo_pc_failout :out std_ulogic; -- fail/no-fix reg + bo_pc_diagloop :out std_ulogic; + tri_lcb_mpw1_dc_b :in std_ulogic; + tri_lcb_mpw2_dc_b :in std_ulogic; + tri_lcb_delay_lclkr_dc :in std_ulogic; + tri_lcb_clkoff_dc_b :in std_ulogic; + tri_lcb_act_dis_dc :in std_ulogic; + + -- Read Port: 0 ----------------------------------------------------- + r0e_act :in std_ulogic; + r0e_en_func :in std_ulogic; + r0e_en_abist :in std_ulogic; + r0e_addr_func :in std_ulogic_vector(0 to 7); + r0e_addr_abist :in std_ulogic_vector(0 to 7); + r0e_data_out :out std_ulogic_vector(0 to 77); + r0e_byp_e :in std_ulogic; --// bypass control + r0e_byp_l :in std_ulogic; --// bypass control + r0e_byp_r :in std_ulogic; + r0e_sel_lbist :in std_ulogic; + + -- Read Port: 1 ----------------------------------------------------- + r1e_act :in std_ulogic; + r1e_en_func :in std_ulogic; + r1e_en_abist :in std_ulogic; + r1e_addr_func :in std_ulogic_vector(0 to 7); + r1e_addr_abist :in std_ulogic_vector(0 to 7); + r1e_data_out :out std_ulogic_vector(0 to 77); + r1e_byp_e :in std_ulogic; --// bypass control + r1e_byp_l :in std_ulogic; --// bypass control + r1e_byp_r :in std_ulogic; + r1e_sel_lbist :in std_ulogic; + + -- Write Port: 0 ---------------------------------------------------- EARLY + w0e_act :in std_ulogic; + w0e_en_func :in std_ulogic; + w0e_en_abist :in std_ulogic; + w0e_addr_func :in std_ulogic_vector(0 to 7); + w0e_addr_abist :in std_ulogic_vector(0 to 7); + w0e_data_func :in std_ulogic_vector(0 to 77); + w0e_data_abist :in std_ulogic_vector(0 to 3); + + w0l_act :in std_ulogic; + w0l_en_func :in std_ulogic; + w0l_en_abist :in std_ulogic; + w0l_addr_func :in std_ulogic_vector(0 to 7); + w0l_addr_abist :in std_ulogic_vector(0 to 7); + w0l_data_func :in std_ulogic_vector(0 to 77); + w0l_data_abist :in std_ulogic_vector(0 to 3) ); + + -- synopsys translate_off + -- synopsys translate_on + +end entity tri_144x78_2r2w; +architecture tri_144x78_2r2w of tri_144x78_2r2w is + +begin + +a : if expand_type = 1 generate + +component RAMB16_S36_S36 +-- pragma translate_off + generic( + SIM_COLLISION_CHECK : string := "none"); -- all, none, warning_only, GENERATE_X_ONLY +-- pragma translate_on + port( + DOA : out std_logic_vector(31 downto 0); + DOB : out std_logic_vector(31 downto 0); + DOPA : out std_logic_vector(3 downto 0); + DOPB : out std_logic_vector(3 downto 0); + ADDRA : in std_logic_vector(8 downto 0); + ADDRB : in std_logic_vector(8 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(31 downto 0); + DIB : in std_logic_vector(31 downto 0); + DIPA : in std_logic_vector(3 downto 0); + DIPB : in std_logic_vector(3 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic); +end component; + +-- pragma translate_off +-- pragma translate_on + +signal tilo : std_ulogic; +signal tihi : std_ulogic; +signal zeross : std_logic_vector(0 to 3); + +signal correct_clk : std_ulogic; +signal clk2x : std_ulogic; +signal reset : std_ulogic; +signal reset_hi : std_ulogic; +signal reset_lo : std_ulogic; +signal reset_q : std_ulogic; +signal sinit0_q : std_logic; +signal sinit1_q : std_logic; +signal flipper_d : std_ulogic; +signal flipper_q : std_ulogic; + +signal doutb0 : std_logic_vector(0 to 77); +signal doutb0_q : std_ulogic_vector(0 to 77); +signal dinfa0_par : std_logic_vector(64 to 95); +signal doutb0_par : std_logic_vector(64 to 95); +signal weaf : std_logic; +signal addra : std_logic_vector(0 to 8); +signal addrb0 : std_logic_vector(0 to 8); +signal dinfa : std_logic_vector(0 to 77); +signal dinfb : std_logic_vector(0 to 31); + +signal w0e_data_q : std_ulogic_vector(0 to 77); +signal w0l_data_q : std_ulogic_vector(0 to 77); +signal w0l_en_q : std_ulogic; +signal w0l_addr_q : std_ulogic_vector(0 to 7); +signal r1e_addr_q : std_ulogic_vector(0 to 7); + +signal r0e_byp_e_q : std_ulogic; --// bypass control +signal r0e_byp_l_q : std_ulogic; --// bypass control +signal r1e_byp_e_q : std_ulogic; --// bypass control +signal r1e_byp_l_q : std_ulogic; --// bypass control +signal r0_byp_sel : std_ulogic_vector(0 to 1); +signal r1_byp_sel : std_ulogic_vector(0 to 1); + +signal unused : std_ulogic; +-- synopsys translate_off +-- synopsys translate_on + +begin + + tilo <= '0'; + tihi <= '1'; + zeross <= (0 to 3 => '0'); + + reset <= nclk.sreset; + correct_clk <= nclk.clk; + clk2x <= nclk.clk2x; + + reset_hi <= reset; + reset_lo <= not reset_q after 1 ns ; + + + flipper_d <= not flipper_q; + + -- Slow Latches (nclk) + slatch: process (correct_clk,reset) begin + if rising_edge(correct_clk) then + if (reset = '1') then + w0l_en_q <= '0'; + r1e_addr_q <= (others => '0'); + r0e_byp_e_q <= '0'; + r0e_byp_l_q <= '0'; + r1e_byp_e_q <= '0'; + r1e_byp_l_q <= '0'; + + else + w0e_data_q <= w0e_data_func; + w0l_data_q <= w0l_data_func; + w0l_en_q <= w0l_en_func; + w0l_addr_q <= w0l_addr_func; + r1e_addr_q <= r1e_addr_func; + r0e_byp_e_q <= r0e_byp_e; + r0e_byp_l_q <= r0e_byp_l; + r1e_byp_e_q <= r1e_byp_e; + r1e_byp_l_q <= r1e_byp_l; + + end if; + end if; + end process; + + flatch: process (clk2x,reset_lo) begin + if clk2x'event and clk2x = '1' then + if (reset_lo = '0') then + flipper_q <= '0'; + + else + flipper_q <= flipper_d; + doutb0_q <= tconv(doutb0); + + end if; + end if; + end process; + + -- repower latches for resets + rlatch: process (correct_clk) begin + if(rising_edge(correct_clk)) then + reset_q <= reset_hi; + sinit0_q <= reset_hi; + sinit1_q <= reset_hi; + end if; + end process; + + + -- need to make 2 write ports + addra(0) <= '0'; + addra(1 to 8) <= (tconv((w0e_addr_func and (0 to 7 => flipper_q)) or (w0l_addr_q and (0 to 7 => not flipper_q)))) after 1 ns ; --2 write ports (A) + weaf <= (( w0e_en_func and flipper_q) or ( w0l_en_q and not flipper_q)) after 1 ns; + dinfa <= (tconv((w0e_data_func and (0 to 77 => flipper_q)) or (w0l_data_q and (0 to 77 => not flipper_q)))) after 1 ns; + + -- need to make 2 read ports + dinfb <= (others => '0'); + addrb0(0) <= '0'; + addrb0(1 to 8) <= (tconv((r0e_addr_func and (0 to 7 => flipper_q)) or (r1e_addr_q and (0 to 7 => not flipper_q)))) after 1 ns ; --2 read ports (B) + + --Bypass + r0_byp_sel <= r0e_byp_e & r0e_byp_l; + with r0_byp_sel select + r0e_data_out <= w0e_data_q when "10", + w0l_data_q when "01", + doutb0_q when others; + + r1_byp_sel <= r1e_byp_e & r1e_byp_l; + with r1_byp_sel select + r1e_data_out <= w0e_data_q when "10", + w0l_data_q when "01", + tconv(doutb0) when others; + + +U0 : RAMB16_S36_S36 +-- pragma translate_off +generic map( +-- all, none, warning_only, generate_x_only + sim_collision_check => "none") +-- pragma translate_on + port map + ( + DOA => open, + DOB => doutb0(0 to 31), + DOPA => open, + DOPB => open, + ADDRA => addra, + ADDRB => addrb0, + CLKA => clk2x, + CLKB => clk2x, + DIA => dinfa(0 to 31), + DIB => dinfb, + DIPA => zeross, + DIPB => zeross, + ENA => tihi, + ENB => tihi, + SSRA => sinit0_q, + SSRB => sinit0_q, + WEA => weaf, + WEB => tilo + ); +U1 : RAMB16_S36_S36 +-- pragma translate_off +generic map( +-- all, none, warning_only, generate_x_only + sim_collision_check => "none") +-- pragma translate_on + + port map + ( + DOA => open, + DOB => doutb0(32 to 63), + DOPA => open, + DOPB => open, + ADDRA => addra, + ADDRB => addrb0, + CLKA => clk2x, + CLKB => clk2x, + DIA => dinfa(32 to 63), + DIB => dinfb, + DIPA => zeross, + DIPB => zeross, + ENA => tihi, + ENB => tihi, + SSRA => sinit1_q, + SSRB => sinit1_q, + WEA => weaf, + WEB => tilo + ); + +doutb0(64 to 77) <= doutb0_par(64 to 77); +dinfa0_par(64 to 95) <= dinfa(64 to 77) & (78 to 95 => '0'); + +U2 : RAMB16_S36_S36 +-- pragma translate_off +generic map( +-- all, none, warning_only, generate_x_only + sim_collision_check => "none") +-- pragma translate_on + port map + ( + DOA => open, + DOB => doutb0_par(64 to 95), + DOPA => open, + DOPB => open, + ADDRA => addra, + ADDRB => addrb0, + CLKA => clk2x, + CLKB => clk2x, + DIA => dinfa0_par(64 to 95), + DIB => dinfb, + DIPA => zeross, + DIPB => zeross, + ENA => tihi, + ENB => tihi, + SSRA => sinit1_q, + SSRB => sinit1_q, + WEA => weaf, + WEB => tilo + ); + +r_scan_out <= '0'; +w_scan_out <= '0'; +time_scan_out <= '0'; +obs0_scan_out <= '0'; +obs1_scan_out <= '0'; + +bo_pc_failout <= '0'; +bo_pc_diagloop <= '0'; + +unused <= or_reduce( std_ulogic_vector(doutb0_par(78 to 95)) + & abist_en & abist_raw_dc_b & r0e_abist_comp_en & r1e_abist_comp_en + & lbist_en & lcb_act_dis_dc & lcb_clkoff_dc_b & lcb_d_mode_dc + & lcb_delay_lclkr_dc & lcb_fce_0 & lcb_mpw1_dc_b & lcb_mpw2_dc_b + & lcb_scan_diag_dc & lcb_scan_dis_dc_b & lcb_sg_0 & lcb_time_sg_0 + & lcb_obs0_sg_0 & lcb_obs1_sg_0 & lcb_obs0_sl_thold_0 & lcb_obs1_sl_thold_0 + & lcb_abst_sl_thold_0 & lcb_time_sl_thold_0 & lcb_ary_nsl_thold_0 + & r_scan_in & w_scan_in & time_scan_in & obs0_scan_in & obs1_scan_in + & r0e_act & r0e_en_func & r0e_en_abist & r0e_addr_abist & r0e_byp_r & r0e_sel_lbist + & r1e_act & r1e_en_func & r1e_en_abist & r1e_addr_abist & r1e_byp_r & r1e_sel_lbist + & w0e_act & w0e_en_abist & w0e_addr_abist & w0e_data_abist + & w0l_act & w0l_en_abist & w0l_addr_abist & w0l_data_abist + & lcb_bolt_sl_thold_0 & pc_bo_enable_2 & pc_bo_reset + & pc_bo_unload & pc_bo_load & pc_bo_shdata & pc_bo_select + & tri_lcb_mpw1_dc_b & tri_lcb_mpw2_dc_b & tri_lcb_delay_lclkr_dc + & tri_lcb_clkoff_dc_b & tri_lcb_act_dis_dc ); + +end generate; + +end architecture tri_144x78_2r2w; diff --git a/rel/src/vhdl/tri/tri_144x78_2r2w_eco.vhdl b/rel/src/vhdl/tri/tri_144x78_2r2w_eco.vhdl new file mode 100644 index 0000000..501616b --- /dev/null +++ b/rel/src/vhdl/tri/tri_144x78_2r2w_eco.vhdl @@ -0,0 +1,451 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee,ibm,support,tri; +use ieee.std_logic_1164.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_support.all; +use support.power_logic_pkg.all; +use tri.tri_latches_pkg.all; + +entity tri_144x78_2r2w_eco is +generic( + expand_type : integer := 1); +port ( + -- Clocks and Scan Cntls ----------------------------------------------------------------- + vdd :inout power_logic; + gnd :inout power_logic; + nclk :in clk_logic; + abist_en :in std_ulogic; -- when abist tested + abist_raw_dc_b :in std_ulogic; -- during abist (disables the xor in miser) + r0e_abist_comp_en :in std_ulogic; -- when abist tested + r1e_abist_comp_en :in std_ulogic; -- when abist tested + lbist_en :in std_ulogic; -- for LBIST mode + + -- LCB Signals --------------- Rd & Wr domains use same LCB controls ----------------------- + lcb_act_dis_dc :in std_ulogic; + lcb_clkoff_dc_b :in std_ulogic_vector(0 to 1); + --0 other + lcb_d_mode_dc :in std_ulogic; + --0 all other + --1 read address late + lcb_delay_lclkr_dc :in std_ulogic_vector(0 to 9); -- + -- 0: read clk lcb + -- 1: read addr lcb + -- 2: write clk E lcb + -- 3: write addr E lcb + -- 4: write clk L lcb + -- 5: write addr L lcb + -- 6: read data 0 lcb + -- 7: read data 1 lcb + -- 8: write data E lcb + -- 9: write data L lcb + lcb_fce_0 :in std_ulogic; + lcb_mpw1_dc_b :in std_ulogic_vector(1 to 9); -- + -- 0: none + -- 1: read addr lcb + -- 2: write clk E lcb + -- 3: write addr E lcb + -- 4: write clk L lcb + -- 5: write addr L lcb + -- 6: read data 0 lcb + -- 7: write data 1 lcb + -- 8: write data E lcb + -- 9: write data L lcb + lcb_mpw2_dc_b :in std_ulogic; + lcb_scan_diag_dc :in std_ulogic; + lcb_scan_dis_dc_b :in std_ulogic; + lcb_sg_0 :in std_ulogic; + lcb_time_sg_0 :in std_ulogic; + + lcb_obs0_sg_0 :in std_ulogic; + lcb_obs1_sg_0 :in std_ulogic; + lcb_obs0_sl_thold_0 :in std_ulogic; + lcb_obs1_sl_thold_0 :in std_ulogic; + + lcb_abst_sl_thold_0 :in std_ulogic; + lcb_time_sl_thold_0 :in std_ulogic; + lcb_ary_nsl_thold_0 :in std_ulogic; + + -- Scan In ---------------------------------------------------------- + r_scan_in :in std_ulogic; + r_scan_out :out std_ulogic; + w_scan_in :in std_ulogic; + w_scan_out :out std_ulogic; + time_scan_in :in std_ulogic; + time_scan_out :out std_ulogic; + obs0_scan_in :in std_ulogic; + obs0_scan_out :out std_ulogic; + obs1_scan_in :in std_ulogic; + obs1_scan_out :out std_ulogic; + + -- BOLT-ON + lcb_bolt_sl_thold_0 :in std_ulogic; + pc_bo_enable_2 :in std_ulogic; -- general bolt-on enable, probably DC + pc_bo_reset :in std_ulogic; -- execute sticky bit decode + pc_bo_unload :in std_ulogic; + pc_bo_load :in std_ulogic; + pc_bo_shdata :in std_ulogic; -- shift data for timing write + pc_bo_select :in std_ulogic; -- select for mask and hier writes + bo_pc_failout :out std_ulogic; -- fail/no-fix reg + bo_pc_diagloop :out std_ulogic; + tri_lcb_mpw1_dc_b :in std_ulogic; + tri_lcb_mpw2_dc_b :in std_ulogic; + tri_lcb_delay_lclkr_dc :in std_ulogic; + tri_lcb_clkoff_dc_b :in std_ulogic; + tri_lcb_act_dis_dc :in std_ulogic; + + -- Read Port: 0 ----------------------------------------------------- + r0e_act :in std_ulogic; + r0e_en_func :in std_ulogic; + r0e_en_abist :in std_ulogic; + r0e_addr_func :in std_ulogic_vector(0 to 7); + r0e_addr_abist :in std_ulogic_vector(0 to 7); + r0e_data_out :out std_ulogic_vector(0 to 77); + r0e_byp_e :in std_ulogic; --// bypass control + r0e_byp_l :in std_ulogic; --// bypass control + r0e_byp_r :in std_ulogic; + r0e_sel_lbist :in std_ulogic; + + -- Read Port: 1 ----------------------------------------------------- + r1e_act :in std_ulogic; + r1e_en_func :in std_ulogic; + r1e_en_abist :in std_ulogic; + r1e_addr_func :in std_ulogic_vector(0 to 7); + r1e_addr_abist :in std_ulogic_vector(0 to 7); + r1e_data_out :out std_ulogic_vector(0 to 77); + r1e_byp_e :in std_ulogic; --// bypass control + r1e_byp_l :in std_ulogic; --// bypass control + r1e_byp_r :in std_ulogic; + r1e_sel_lbist :in std_ulogic; + + -- Write Port: 0 ---------------------------------------------------- EARLY + w0e_act :in std_ulogic; + w0e_en_func :in std_ulogic; + w0e_en_abist :in std_ulogic; + w0e_addr_func :in std_ulogic_vector(0 to 7); + w0e_addr_abist :in std_ulogic_vector(0 to 7); + w0e_data_func :in std_ulogic_vector(0 to 77); + w0e_data_abist :in std_ulogic_vector(0 to 3); + + -- Write Port: 0 ---------------------------------------------------- LATE + w0l_act :in std_ulogic; + w0l_en_func :in std_ulogic; + w0l_en_abist :in std_ulogic; + w0l_addr_func :in std_ulogic_vector(0 to 7); + w0l_addr_abist :in std_ulogic_vector(0 to 7); + w0l_data_func :in std_ulogic_vector(0 to 77); + w0l_data_abist :in std_ulogic_vector(0 to 3) ); + + -- synopsys translate_off + -- synopsys translate_on + +end entity tri_144x78_2r2w_eco; +architecture tri_144x78_2r2w_eco of tri_144x78_2r2w_eco is + +begin + +a : if expand_type = 1 generate + +component RAMB16_S36_S36 +-- pragma translate_off + generic( + SIM_COLLISION_CHECK : string := "none"); -- all, none, warning_only, GENERATE_X_ONLY +-- pragma translate_on + port( + DOA : out std_logic_vector(31 downto 0); + DOB : out std_logic_vector(31 downto 0); + DOPA : out std_logic_vector(3 downto 0); + DOPB : out std_logic_vector(3 downto 0); + ADDRA : in std_logic_vector(8 downto 0); + ADDRB : in std_logic_vector(8 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(31 downto 0); + DIB : in std_logic_vector(31 downto 0); + DIPA : in std_logic_vector(3 downto 0); + DIPB : in std_logic_vector(3 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic); +end component; + +-- pragma translate_off +-- pragma translate_on + +signal tilo : std_ulogic; +signal tihi : std_ulogic; +signal zeross : std_logic_vector(0 to 3); + +signal correct_clk : std_ulogic; +signal clk2x : std_ulogic; +signal reset : std_ulogic; +signal reset_hi : std_ulogic; +signal reset_lo : std_ulogic; +signal reset_q : std_ulogic; +signal sinit0_q : std_logic; +signal sinit1_q : std_logic; +signal flipper_d : std_ulogic; +signal flipper_q : std_ulogic; + +signal doutb0 : std_logic_vector(0 to 77); +signal doutb0_q : std_ulogic_vector(0 to 77); +signal dinfa0_par : std_logic_vector(64 to 95); +signal doutb0_par : std_logic_vector(64 to 95); +signal weaf : std_logic; +signal addra : std_logic_vector(0 to 8); +signal addrb0 : std_logic_vector(0 to 8); +signal dinfa : std_logic_vector(0 to 77); +signal dinfb : std_logic_vector(0 to 31); + +signal w0e_data_q : std_ulogic_vector(0 to 77); +signal w0l_data_q : std_ulogic_vector(0 to 77); +signal w0l_en_q : std_ulogic; +signal w0l_addr_q : std_ulogic_vector(0 to 7); +signal r1e_addr_q : std_ulogic_vector(0 to 7); + +signal r0e_byp_e_q : std_ulogic; --// bypass control +signal r0e_byp_l_q : std_ulogic; --// bypass control +signal r1e_byp_e_q : std_ulogic; --// bypass control +signal r1e_byp_l_q : std_ulogic; --// bypass control +signal r0_byp_sel : std_ulogic_vector(0 to 1); +signal r1_byp_sel : std_ulogic_vector(0 to 1); + +signal unused : std_ulogic; +-- synopsys translate_off +-- synopsys translate_on + +begin + + tilo <= '0'; + tihi <= '1'; + zeross <= (0 to 3 => '0'); + + reset <= nclk.sreset; + correct_clk <= nclk.clk; + clk2x <= nclk.clk2x; + + reset_hi <= reset; + reset_lo <= not reset_q after 1 ns ; + + + flipper_d <= not flipper_q; + + -- Slow Latches (nclk) + slatch: process (correct_clk,reset) begin + if rising_edge(correct_clk) then + if (reset = '1') then + w0l_en_q <= '0'; + r1e_addr_q <= (others => '0'); + r0e_byp_e_q <= '0'; + r0e_byp_l_q <= '0'; + r1e_byp_e_q <= '0'; + r1e_byp_l_q <= '0'; + + else + w0e_data_q <= w0e_data_func; + w0l_data_q <= w0l_data_func; + w0l_en_q <= w0l_en_func; + w0l_addr_q <= w0l_addr_func; + r1e_addr_q <= r1e_addr_func; + r0e_byp_e_q <= r0e_byp_e; + r0e_byp_l_q <= r0e_byp_l; + r1e_byp_e_q <= r1e_byp_e; + r1e_byp_l_q <= r1e_byp_l; + + end if; + end if; + end process; + + flatch: process (clk2x,reset_lo) begin + if clk2x'event and clk2x = '1' then + if (reset_lo = '0') then + flipper_q <= '0'; + + else + flipper_q <= flipper_d; + doutb0_q <= tconv(doutb0); + + end if; + end if; + end process; + + -- repower latches for resets + rlatch: process (correct_clk) begin + if(rising_edge(correct_clk)) then + reset_q <= reset_hi; + sinit0_q <= reset_hi; + sinit1_q <= reset_hi; + end if; + end process; + + + -- need to make 2 write ports + addra(0) <= '0'; + addra(1 to 8) <= (tconv((w0e_addr_func and (0 to 7 => flipper_q)) or (w0l_addr_q and (0 to 7 => not flipper_q)))) after 1 ns ; --2 write ports (A) + weaf <= (( w0e_en_func and flipper_q) or ( w0l_en_q and not flipper_q)) after 1 ns; + dinfa <= (tconv((w0e_data_func and (0 to 77 => flipper_q)) or (w0l_data_q and (0 to 77 => not flipper_q)))) after 1 ns; + + -- need to make 2 read ports + dinfb <= (others => '0'); + addrb0(0) <= '0'; + addrb0(1 to 8) <= (tconv((r0e_addr_func and (0 to 7 => flipper_q)) or (r1e_addr_q and (0 to 7 => not flipper_q)))) after 1 ns ; --2 read ports (B) + + --Bypass + r0_byp_sel <= r0e_byp_e & r0e_byp_l; + with r0_byp_sel select + r0e_data_out <= w0e_data_q when "10", + w0l_data_q when "01", + doutb0_q when others; + + r1_byp_sel <= r1e_byp_e & r1e_byp_l; + with r1_byp_sel select + r1e_data_out <= w0e_data_q when "10", + w0l_data_q when "01", + tconv(doutb0) when others; + + +U0 : RAMB16_S36_S36 +-- pragma translate_off +generic map( +-- all, none, warning_only, generate_x_only + sim_collision_check => "none") +-- pragma translate_on + port map + ( + DOA => open, + DOB => doutb0(0 to 31), + DOPA => open, + DOPB => open, + ADDRA => addra, + ADDRB => addrb0, + CLKA => clk2x, + CLKB => clk2x, + DIA => dinfa(0 to 31), + DIB => dinfb, + DIPA => zeross, + DIPB => zeross, + ENA => tihi, + ENB => tihi, + SSRA => sinit0_q, + SSRB => sinit0_q, + WEA => weaf, + WEB => tilo + ); +U1 : RAMB16_S36_S36 +-- pragma translate_off +generic map( +-- all, none, warning_only, generate_x_only + sim_collision_check => "none") +-- pragma translate_on + + port map + ( + DOA => open, + DOB => doutb0(32 to 63), + DOPA => open, + DOPB => open, + ADDRA => addra, + ADDRB => addrb0, + CLKA => clk2x, + CLKB => clk2x, + DIA => dinfa(32 to 63), + DIB => dinfb, + DIPA => zeross, + DIPB => zeross, + ENA => tihi, + ENB => tihi, + SSRA => sinit1_q, + SSRB => sinit1_q, + WEA => weaf, + WEB => tilo + ); + +doutb0(64 to 77) <= doutb0_par(64 to 77); +dinfa0_par(64 to 95) <= dinfa(64 to 77) & (78 to 95 => '0'); + +U2 : RAMB16_S36_S36 +-- pragma translate_off +generic map( +-- all, none, warning_only, generate_x_only + sim_collision_check => "none") +-- pragma translate_on + port map + ( + DOA => open, + DOB => doutb0_par(64 to 95), + DOPA => open, + DOPB => open, + ADDRA => addra, + ADDRB => addrb0, + CLKA => clk2x, + CLKB => clk2x, + DIA => dinfa0_par(64 to 95), + DIB => dinfb, + DIPA => zeross, + DIPB => zeross, + ENA => tihi, + ENB => tihi, + SSRA => sinit1_q, + SSRB => sinit1_q, + WEA => weaf, + WEB => tilo + ); + +r_scan_out <= '0'; +w_scan_out <= '0'; +time_scan_out <= '0'; +obs0_scan_out <= '0'; +obs1_scan_out <= '0'; + +bo_pc_failout <= '0'; +bo_pc_diagloop <= '0'; + +unused <= or_reduce( std_ulogic_vector(doutb0_par(78 to 95)) + & abist_en & abist_raw_dc_b & r0e_abist_comp_en & r1e_abist_comp_en + & lbist_en & lcb_act_dis_dc & lcb_clkoff_dc_b & lcb_d_mode_dc + & lcb_delay_lclkr_dc & lcb_fce_0 & lcb_mpw1_dc_b & lcb_mpw2_dc_b + & lcb_scan_diag_dc & lcb_scan_dis_dc_b & lcb_sg_0 & lcb_time_sg_0 + & lcb_obs0_sg_0 & lcb_obs1_sg_0 & lcb_obs0_sl_thold_0 & lcb_obs1_sl_thold_0 + & lcb_abst_sl_thold_0 & lcb_time_sl_thold_0 & lcb_ary_nsl_thold_0 + & r_scan_in & w_scan_in & time_scan_in & obs0_scan_in & obs1_scan_in + & r0e_act & r0e_en_func & r0e_en_abist & r0e_addr_abist & r0e_byp_r & r0e_sel_lbist + & r1e_act & r1e_en_func & r1e_en_abist & r1e_addr_abist & r1e_byp_r & r1e_sel_lbist + & w0e_act & w0e_en_abist & w0e_addr_abist & w0e_data_abist + & w0l_act & w0l_en_abist & w0l_addr_abist & w0l_data_abist + & lcb_bolt_sl_thold_0 & pc_bo_enable_2 & pc_bo_reset + & pc_bo_unload & pc_bo_load & pc_bo_shdata & pc_bo_select + & tri_lcb_mpw1_dc_b & tri_lcb_mpw2_dc_b & tri_lcb_delay_lclkr_dc + & tri_lcb_clkoff_dc_b & tri_lcb_act_dis_dc ); + +end generate; + +end architecture tri_144x78_2r2w_eco; diff --git a/rel/src/vhdl/tri/tri_256x162_4w_0.vhdl b/rel/src/vhdl/tri/tri_256x162_4w_0.vhdl new file mode 100644 index 0000000..ec585f7 --- /dev/null +++ b/rel/src/vhdl/tri/tri_256x162_4w_0.vhdl @@ -0,0 +1,366 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; use ieee.std_logic_1164.all ; +library ibm; use ibm.std_ulogic_support.all ; + use ibm.std_ulogic_function_support.all; +library support; + use support.power_logic_pkg.all; +library tri; use tri.tri_latches_pkg.all; + +entity tri_256x162_4w_0 is + generic (addressable_ports : positive := 256; -- number of addressable register in this array + addressbus_width : positive := 8; -- width of the bus to address all ports (2^addressbus_width >= addressable_ports) + port_bitwidth : positive := 162; -- bitwidth of ports + ways : positive := 4; -- number of ways + expand_type : integer := 1); -- 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) + port ( + -- POWER PINS + gnd : inout power_logic; + vdd : inout power_logic; + vcs : inout power_logic; + -- CLOCK and CLOCKCONTROL ports + nclk : in clk_logic; + ccflush_dc : in std_ulogic; + lcb_clkoff_dc_b : in std_ulogic; + lcb_d_mode_dc : in std_ulogic; + lcb_act_dis_dc : in std_ulogic; + lcb_ary_nsl_thold_0 : in std_ulogic; + lcb_sg_1 : in std_ulogic; + lcb_abst_sl_thold_0 : in std_ulogic; + scan_diag_dc : in std_ulogic; + scan_dis_dc_b : in std_ulogic; + abst_scan_in : in std_ulogic_vector(0 to 1); + abst_scan_out : out std_ulogic_vector(0 to 1); + lcb_delay_lclkr_np_dc : in std_ulogic; + ctrl_lcb_delay_lclkr_np_dc : in std_ulogic; + dibw_lcb_delay_lclkr_np_dc : in std_ulogic; + ctrl_lcb_mpw1_np_dc_b : in std_ulogic; + dibw_lcb_mpw1_np_dc_b : in std_ulogic; + lcb_mpw1_pp_dc_b : in std_ulogic; + lcb_mpw1_2_pp_dc_b : in std_ulogic; + aodo_lcb_delay_lclkr_dc : in std_ulogic; + aodo_lcb_mpw1_dc_b : in std_ulogic; + aodo_lcb_mpw2_dc_b : in std_ulogic; + -- Timing Scan Chain Pins + lcb_time_sg_0 : in std_ulogic; + lcb_time_sl_thold_0 : in std_ulogic; + time_scan_in : in std_ulogic; + time_scan_out : out std_ulogic; + bitw_abist : in std_ulogic_vector(0 to 1); + -- REDUNDANCY PINS + lcb_repr_sl_thold_0 : in std_ulogic; + lcb_repr_sg_0 : in std_ulogic; + repr_scan_in : in std_ulogic; + repr_scan_out : out std_ulogic; + -- DATA I/O RELATED PINS: + tc_lbist_ary_wrt_thru_dc : in std_ulogic; + abist_en_1 : in std_ulogic; + din_abist : in std_ulogic_vector(0 to 3); + abist_cmp_en : in std_ulogic; + abist_raw_b_dc : in std_ulogic; + data_cmp_abist : in std_ulogic_vector(0 to 3); + addr_abist : in std_ulogic_vector(0 to (addressbus_width-1)); + r_wb_abist : in std_ulogic; + write_thru_en_dc : in std_ulogic; + -- BOLT-ON + lcb_bolt_sl_thold_0 : in std_ulogic; -- thold for any regs inside backend + pc_bo_enable_2 : in std_ulogic; -- general bolt-on enable, probably DC + pc_bo_reset : in std_ulogic; -- execute sticky bit decode + pc_bo_unload : in std_ulogic; + pc_bo_repair : in std_ulogic; -- load repair reg + pc_bo_shdata : in std_ulogic; -- shift data for timing write + pc_bo_select : in std_ulogic_vector(0 to 1); -- select for mask and hier writes + bo_pc_failout : out std_ulogic_vector(0 to 1); -- fail/no-fix reg + bo_pc_diagloop : out std_ulogic_vector(0 to 1); + tri_lcb_mpw1_dc_b : in std_ulogic; + tri_lcb_mpw2_dc_b : in std_ulogic; + tri_lcb_delay_lclkr_dc : in std_ulogic; + tri_lcb_clkoff_dc_b : in std_ulogic; + tri_lcb_act_dis_dc : in std_ulogic; + -- FUNCTIONAL PORTS + read_act : in std_ulogic; + write_enable : in std_ulogic; + write_way : in std_ulogic_vector (0 to (ways-1)); + addr : in std_ulogic_vector (0 to (addressbus_width-1)); + data_in : in std_ulogic_vector (0 to (port_bitwidth-1)); + data_out : out std_ulogic_vector(0 to (port_bitwidth*ways-1)) +); + + -- synopsys translate_off + + -- synopsys translate_on + +end entity tri_256x162_4w_0; + +architecture tri_256x162_4w_0 of tri_256x162_4w_0 is + +constant wga_base_width : integer := 324; +constant wga_width_mult : integer := (port_bitwidth*ways-1)/wga_base_width + 1; +constant ramb_base_width : integer := 36; +constant ramb_base_addr : integer := 9; +constant ramb_width_mult : integer := (port_bitwidth-1)/ramb_base_width + 1; + + +type RAMB_DATA_ARRAY is array (natural range <>) of std_logic_vector(0 to (ramb_base_width*ramb_width_mult - 1)); + + +begin -- tri_256x162_4w_0 + + -- synopsys translate_off + um: if expand_type = 0 generate + signal tiup : std_ulogic; + signal tidn : std_ulogic; + + signal act : std_ulogic; + signal addr_l2 : std_ulogic_vector (0 TO addressbus_width-1); + signal write_way_l2 : std_ulogic_vector (0 TO write_way'right); + signal write_enable_d : std_ulogic; + signal write_enable_l2 : std_ulogic; + signal data_in_l2 : std_ulogic_vector(0 to port_bitwidth-1); + signal array_d : std_ulogic_vector(0 to addressable_ports*port_bitwidth*ways-1); + signal array_l2 : std_ulogic_vector(0 to addressable_ports*port_bitwidth*ways-1); + begin + tiup <= '1'; + tidn <= '0'; + + act <= read_act or or_reduce(write_way); + + addr_latch: tri_rlmreg_p + generic map (width => addr'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act, + scin => (others => '0'), + scout => open, + din => addr, + dout => addr_l2 ); + + write_way_latch: tri_rlmreg_p + generic map (width => write_way'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act, + scin => (others => '0'), + scout => open, + din => write_way, + dout => write_way_l2 ); + + write_enable_latch: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + scin => tidn, + scout => open, + din => write_enable_d, + dout => write_enable_l2 ); + + data_in_latch: tri_rlmreg_p + generic map (width => port_bitwidth, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act, + scin => (others => '0'), + scout => open, + din => data_in, + dout => data_in_l2 ); + + array_latch: tri_rlmreg_p + generic map (width => addressable_ports*port_bitwidth*ways, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + scin => (others => '0'), + scout => open, + din => array_d, + dout => array_l2 ); + + write_enable_d <= act and write_enable; + + ww: for w in 0 to ways-1 generate + begin + wy: for y in 0 to addressable_ports-1 generate + begin + wx: for x in 0 to port_bitwidth-1 generate + begin + array_d(y*port_bitwidth*ways+w*port_bitwidth+x) <= + data_in_l2(x) when (( write_enable_l2 and addr_l2 = tconv(y, addressbus_width) and + write_way_l2(w)) = '1') + else array_l2(y*port_bitwidth*ways+w*port_bitwidth+x); + + end generate wx; + end generate wy; + end generate ww; + + data_out <= array_l2( tconv(addr_l2)*port_bitwidth*ways to tconv(addr_l2)*port_bitwidth*ways+port_bitwidth*ways-1 ); + + abst_scan_out <= "00"; + time_scan_out <= '0'; + repr_scan_out <= '0'; + + bo_pc_failout <= "00"; + bo_pc_diagloop <= "00"; + + end generate um; + -- synopsys translate_on + + + a: if expand_type = 1 generate + component RAMB16_S36_S36 + -- pragma translate_off + generic( + SIM_COLLISION_CHECK : string := "none"); -- all, none, warning_only, GENERATE_X_ONLY + -- pragma translate_on + port( + DOA : out std_logic_vector(31 downto 0); + DOB : out std_logic_vector(31 downto 0); + DOPA : out std_logic_vector(3 downto 0); + DOPB : out std_logic_vector(3 downto 0); + ADDRA : in std_logic_vector(8 downto 0); + ADDRB : in std_logic_vector(8 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(31 downto 0); + DIB : in std_logic_vector(31 downto 0); + DIPA : in std_logic_vector(3 downto 0); + DIPB : in std_logic_vector(3 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic); + end component; + + -- pragma translate_off + -- pragma translate_on + + signal ramb_data_in : std_logic_vector(0 to (ramb_base_width*ramb_width_mult - 1)); + signal ramb_data_out : RAMB_DATA_ARRAY(0 to ways-1); + signal ramb_addr : std_logic_vector(0 to ramb_base_addr - 1); + + signal act : std_ulogic_vector(0 to ways-1); + signal write : std_ulogic_vector(0 to ways-1); + signal tidn : std_ulogic; + signal unused : std_ulogic; + -- synopsys translate_off + -- synopsys translate_on + begin + + tidn <= '0'; + + add0: if (addressbus_width < ramb_base_addr) generate + begin + ramb_addr(0 to (ramb_base_addr-addressbus_width-1)) <= (others => '0'); + ramb_addr(ramb_base_addr-addressbus_width to ramb_base_addr-1) <= tconv( addr ); + end generate; + add1: if (addressbus_width >= ramb_base_addr) generate + begin + ramb_addr <= tconv( addr(addressbus_width-ramb_base_addr to addressbus_width-1) ); + end generate; + + din: for i in ramb_data_in'range generate + begin + R0: if(i < port_bitwidth) generate begin ramb_data_in(i) <= data_in(i); end generate; + R1: if(i >= port_bitwidth) generate begin ramb_data_in(i) <= '0'; end generate; + end generate; + + aw: for w in 0 to ways-1 generate begin + act(w) <= read_act or write_way(w); + write(w) <= write_enable and write_way(w); + + ax: for x in 0 to (ramb_width_mult - 1) generate begin + arr: RAMB16_S36_S36 + -- pragma translate_off + generic map( + -- all, none, warning_only, generate_x_only + sim_collision_check => "none") + -- pragma translate_on + port map( + DOA => ramb_data_out(w)(x*ramb_base_width to x*ramb_base_width+31), + DOB => open, + DOPA => ramb_data_out(w)(x*ramb_base_width+32 to x*ramb_base_width+35), + DOPB => open, + ADDRA => ramb_addr, + ADDRB => ramb_addr, + CLKA => nclk.clk, + CLKB => tidn, + DIA => ramb_data_in(x*ramb_base_width to x*ramb_base_width+31), + DIB => ramb_data_in(x*ramb_base_width to x*ramb_base_width+31), + DIPA => ramb_data_in(x*ramb_base_width+32 to x*ramb_base_width+35), + DIPB => ramb_data_in(x*ramb_base_width+32 to x*ramb_base_width+35), + ENA => act(w), + ENB => tidn, + SSRA => nclk.sreset, + SSRB => tidn, + WEA => write(w), + WEB => tidn + ); + + end generate ax; + + data_out(w*port_bitwidth to ((w+1)*port_bitwidth)-1 ) <= tconv( ramb_data_out(w)(0 to port_bitwidth-1) ); + + end generate aw; + + abst_scan_out <= "00"; + time_scan_out <= '0'; + repr_scan_out <= '0'; + + bo_pc_failout <= "00"; + bo_pc_diagloop <= "00"; + + unused <= or_reduce( std_ulogic_vector(ramb_data_out(0)(port_bitwidth to ramb_base_width*ramb_width_mult - 1)) + & std_ulogic_vector(ramb_data_out(1)(port_bitwidth to ramb_base_width*ramb_width_mult - 1)) + & std_ulogic_vector(ramb_data_out(2)(port_bitwidth to ramb_base_width*ramb_width_mult - 1)) + & std_ulogic_vector(ramb_data_out(3)(port_bitwidth to ramb_base_width*ramb_width_mult - 1)) + & ccflush_dc & lcb_clkoff_dc_b & lcb_d_mode_dc & lcb_act_dis_dc + & scan_dis_dc_b & scan_diag_dc & bitw_abist + & lcb_sg_1 & lcb_time_sg_0 & lcb_repr_sg_0 + & lcb_abst_sl_thold_0 & lcb_repr_sl_thold_0 + & lcb_time_sl_thold_0 & lcb_ary_nsl_thold_0 & tc_lbist_ary_wrt_thru_dc + & abist_en_1 & din_abist & abist_cmp_en & abist_raw_b_dc & data_cmp_abist + & addr_abist & r_wb_abist & write_thru_en_dc & abst_scan_in & time_scan_in & repr_scan_in + & lcb_delay_lclkr_np_dc & ctrl_lcb_delay_lclkr_np_dc & dibw_lcb_delay_lclkr_np_dc + & ctrl_lcb_mpw1_np_dc_b & dibw_lcb_mpw1_np_dc_b & lcb_mpw1_pp_dc_b & lcb_mpw1_2_pp_dc_b + & aodo_lcb_delay_lclkr_dc & aodo_lcb_mpw1_dc_b & aodo_lcb_mpw2_dc_b + & lcb_bolt_sl_thold_0 & pc_bo_enable_2 & pc_bo_reset + & pc_bo_unload & pc_bo_repair & pc_bo_shdata & pc_bo_select + & tri_lcb_mpw1_dc_b & tri_lcb_mpw2_dc_b & tri_lcb_delay_lclkr_dc + & tri_lcb_clkoff_dc_b & tri_lcb_act_dis_dc ); + + end generate a; + +end tri_256x162_4w_0; diff --git a/rel/src/vhdl/tri/tri_32x35_8w_1r1w.vhdl b/rel/src/vhdl/tri/tri_32x35_8w_1r1w.vhdl new file mode 100644 index 0000000..422805a --- /dev/null +++ b/rel/src/vhdl/tri/tri_32x35_8w_1r1w.vhdl @@ -0,0 +1,594 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; use ieee.std_logic_1164.all ; +library ibm; use ibm.std_ulogic_support.all ; + use ibm.std_ulogic_function_support.all; +library support; use support.power_logic_pkg.all; +library tri; use tri.tri_latches_pkg.all; + +-- pragma translate_off +-- pragma translate_on + +entity tri_32x35_8w_1r1w is + generic (addressable_ports : positive := 32; -- number of addressable register in this array + addressbus_width : positive := 5; -- width of the bus to address all ports (2^addressbus_width >= addressable_ports) + port_bitwidth : positive := 35; -- bitwidth of ports + ways : positive := 8; -- number of ways + expand_type : integer := 1); -- 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) + port ( + -- POWER PINS + gnd : inout power_logic; + vdd : inout power_logic; + vcs : inout power_logic; + -- CLOCK and CLOCKCONTROL ports + nclk : in clk_logic; + rd0_act : in std_ulogic; + sg_0 : in std_ulogic; + abst_slp_sl_thold_0 : in std_ulogic; + ary_slp_nsl_thold_0 : in std_ulogic; + time_sl_thold_0 : in std_ulogic; + repr_sl_thold_0 : in std_ulogic; + clkoff_dc_b : in std_ulogic; + ccflush_dc : in std_ulogic; + scan_dis_dc_b : in std_ulogic; + scan_diag_dc : in std_ulogic; + d_mode_dc : in std_ulogic; + mpw1_dc_b : in std_ulogic_vector(0 to 4); + mpw2_dc_b : in std_ulogic; + delay_lclkr_dc : in std_ulogic_vector(0 to 4); + -- ABIST + wr_abst_act : in std_ulogic; + rd0_abst_act : in std_ulogic; + abist_di : in std_ulogic_vector(0 to 3); + abist_bw_odd : in std_ulogic; + abist_bw_even : in std_ulogic; + abist_wr_adr : in std_ulogic_vector(0 to 4); + abist_rd0_adr : in std_ulogic_vector(0 to 4); + tc_lbist_ary_wrt_thru_dc : in std_ulogic; + abist_ena_1 : in std_ulogic; + abist_g8t_rd0_comp_ena : in std_ulogic; + abist_raw_dc_b : in std_ulogic; + obs0_abist_cmp : in std_ulogic_vector(0 to 3); + -- Scan + abst_scan_in : in std_ulogic; + time_scan_in : in std_ulogic; + repr_scan_in : in std_ulogic; + abst_scan_out : out std_ulogic; + time_scan_out : out std_ulogic; + repr_scan_out : out std_ulogic; + -- BOLT-ON + lcb_bolt_sl_thold_0 : in std_ulogic; + pc_bo_enable_2 : in std_ulogic; -- general bolt-on enable + pc_bo_reset : in std_ulogic; -- reset + pc_bo_unload : in std_ulogic; -- unload sticky bits + pc_bo_repair : in std_ulogic; -- execute sticky bit decode + pc_bo_shdata : in std_ulogic; -- shift data for timing write and diag loop + pc_bo_select : in std_ulogic_vector(0 to 3); -- select for mask and hier writes + bo_pc_failout : out std_ulogic_vector(0 to 3); -- fail/no-fix reg + bo_pc_diagloop : out std_ulogic_vector(0 to 3); + tri_lcb_mpw1_dc_b : in std_ulogic; + tri_lcb_mpw2_dc_b : in std_ulogic; + tri_lcb_delay_lclkr_dc : in std_ulogic; + tri_lcb_clkoff_dc_b : in std_ulogic; + tri_lcb_act_dis_dc : in std_ulogic; + -- Write Ports + write_enable : in std_ulogic_vector (0 to ((port_bitwidth*ways-1)/(port_bitwidth*2))); + way : in std_ulogic_vector (0 to (ways-1)); + addr_wr : in std_ulogic_vector (0 to (addressbus_width-1)); + data_in : in std_ulogic_vector (0 to (port_bitwidth-1)); + -- Read Ports + addr_rd_01 : in std_ulogic_vector (0 to (addressbus_width-1)); + addr_rd_23 : in std_ulogic_vector (0 to (addressbus_width-1)); + addr_rd_45 : in std_ulogic_vector (0 to (addressbus_width-1)); + addr_rd_67 : in std_ulogic_vector (0 to (addressbus_width-1)); + data_out : out std_ulogic_vector(0 to (port_bitwidth*ways-1)) +); + + -- synopsys translate_off + + -- synopsys translate_on + +end entity tri_32x35_8w_1r1w; + +architecture tri_32x35_8w_1r1w of tri_32x35_8w_1r1w is + +constant wga_base_width : integer := 70; +constant wga_base_addr : integer := 5; +constant wga_width_mult : integer := (port_bitwidth*ways-1)/wga_base_width + 1; +constant ramb_base_width : integer := 36; +constant ramb_base_addr : integer := 9; +constant ramb_width_mult : integer := (port_bitwidth-1)/ramb_base_width + 1; + + + + +begin -- tri_32x35_8w_1r1w + + -- synopsys translate_off + um: if expand_type = 0 generate + signal tiup : std_ulogic; + signal tidn : std_ulogic; + + signal addr_rd_l2 : std_ulogic_vector (0 TO addressbus_width-1); + signal addr_wr_l2 : std_ulogic_vector (0 TO addressbus_width-1); + signal way_l2 : std_ulogic_vector (0 TO way'right); + signal write_enable_d : std_ulogic_vector(0 to wga_width_mult-1); + signal write_enable_l2 : std_ulogic_vector(0 to wga_width_mult-1); + signal data_in_l2 : std_ulogic_vector(0 to port_bitwidth-1); + signal array_d : std_ulogic_vector(0 to addressable_ports*port_bitwidth*ways-1); + signal array_l2 : std_ulogic_vector(0 to addressable_ports*port_bitwidth*ways-1); + signal act : std_ulogic; + begin + tiup <= '1'; + tidn <= '0'; + + act <= or_reduce(write_enable) or rd0_act; + + addr_rd_latch: tri_rlmreg_p + generic map (width => addr_rd_01'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => act, + scin => (others => '0'), + scout => open, + din => addr_rd_01, + dout => addr_rd_l2 ); + + addr_wr_latch: tri_rlmreg_p + generic map (width => addr_wr'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => act, + scin => (others => '0'), + scout => open, + din => addr_wr, + dout => addr_wr_l2 ); + + way_latch: tri_rlmreg_p + generic map (width => way'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => act, + scin => (others => '0'), + scout => open, + din => way, + dout => way_l2 ); + + write_enable_latch: tri_rlmreg_p + generic map (width => wga_width_mult, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => act, + scin => (others => '0'), + scout => open, + din => write_enable_d, + dout => write_enable_l2 ); + + data_in_latch: tri_rlmreg_p + generic map (width => port_bitwidth, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => act, + scin => (others => '0'), + scout => open, + din => data_in, + dout => data_in_l2 ); + + array_latch: tri_rlmreg_p + generic map (width => addressable_ports*port_bitwidth*ways, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => tiup, + scin => (others => '0'), + scout => open, + din => array_d, + dout => array_l2 ); + + write_enable_d <= write_enable; + + ww: for w in 0 to ways-1 generate + begin + wy: for y in 0 to addressable_ports-1 generate + begin + wx: for x in 0 to port_bitwidth-1 generate + begin + array_d(y*port_bitwidth*ways+w*port_bitwidth+x) <= + data_in_l2(x) when (( or_reduce(write_enable_l2) and addr_wr_l2 = tconv(y, addressbus_width) and + way_l2(w)) = '1') + else array_l2(y*port_bitwidth*ways+w*port_bitwidth+x); + + end generate wx; + end generate wy; + end generate ww; + + data_out <= array_l2( tconv(addr_rd_l2)*port_bitwidth*ways to tconv(addr_rd_l2)*port_bitwidth*ways+port_bitwidth*ways-1 ); + + abst_scan_out <= tidn; + time_scan_out <= tidn; + repr_scan_out <= tidn; + + bo_pc_failout <= "0000"; + bo_pc_diagloop <= "0000"; + end generate um; + -- synopsys translate_on + + a: if expand_type = 1 generate + component RAMB16_S36_S36 + -- pragma translate_off + generic( + SIM_COLLISION_CHECK : string := "none"); -- all, none, warning_only, GENERATE_X_ONLY + -- pragma translate_on + port( + DOA : out std_logic_vector(31 downto 0); + DOB : out std_logic_vector(31 downto 0); + DOPA : out std_logic_vector(3 downto 0); + DOPB : out std_logic_vector(3 downto 0); + ADDRA : in std_logic_vector(8 downto 0); + ADDRB : in std_logic_vector(8 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(31 downto 0); + DIB : in std_logic_vector(31 downto 0); + DIPA : in std_logic_vector(3 downto 0); + DIPB : in std_logic_vector(3 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic); + end component; + + -- pragma translate_off + -- pragma translate_on + + signal array_wr_data : std_logic_vector(0 to port_bitwidth - 1); + signal ramb_data_in : std_logic_vector(0 to 35); + signal ramb_data_outA : std_logic_vector(0 to 35); + signal ramb_data_outB : std_logic_vector(0 to 35); + signal ramb_data_outC : std_logic_vector(0 to 35); + signal ramb_data_outD : std_logic_vector(0 to 35); + signal ramb_data_outE : std_logic_vector(0 to 35); + signal ramb_data_outF : std_logic_vector(0 to 35); + signal ramb_data_outG : std_logic_vector(0 to 35); + signal ramb_data_outH : std_logic_vector(0 to 35); + signal ramb_addr_wr : std_logic_vector(0 to ramb_base_addr - 1); + signal ramb_addr_rd : std_logic_vector(0 to ramb_base_addr - 1); + signal data_outA : std_ulogic_vector(0 to 35); + signal data_outB : std_ulogic_vector(0 to 35); + signal data_outC : std_ulogic_vector(0 to 35); + signal data_outD : std_ulogic_vector(0 to 35); + signal data_outE : std_ulogic_vector(0 to 35); + signal data_outF : std_ulogic_vector(0 to 35); + signal data_outG : std_ulogic_vector(0 to 35); + signal data_outH : std_ulogic_vector(0 to 35); + + signal rd_addr : std_ulogic_vector(0 to ramb_base_addr - 1); + signal wr_addr : std_ulogic_vector(0 to ramb_base_addr - 1); + signal write_enable_wA : std_ulogic; + signal write_enable_wB : std_ulogic; + signal write_enable_wC : std_ulogic; + signal write_enable_wD : std_ulogic; + signal write_enable_wE : std_ulogic; + signal write_enable_wF : std_ulogic; + signal write_enable_wG : std_ulogic; + signal write_enable_wH : std_ulogic; + signal tidn : std_logic_vector(0 to 35); + signal act : std_ulogic; + signal wen : std_ulogic; + signal unused : std_ulogic; + -- synopsys translate_off + -- synopsys translate_on + begin + + tidn <= (others=>'0'); + + wen <= or_reduce(write_enable); + act <= rd0_act or wen; + + -- Data Generate + array_wr_data <= tconv(data_in); + addr_calc : for t in 0 to 35 generate begin + R0 : if(t < 35 - (port_bitwidth-1)) generate begin ramb_data_in(t) <= '0'; end generate; + R1 : if(t >= 35 - (port_bitwidth-1)) generate begin ramb_data_in(t) <= array_wr_data(t-(35-(port_bitwidth-1))); end generate; + end generate addr_calc; + + write_enable_wA <= wen and way(0); + write_enable_wB <= wen and way(1); + write_enable_wC <= wen and way(2); + write_enable_wD <= wen and way(3); + write_enable_wE <= wen and way(4); + write_enable_wF <= wen and way(5); + write_enable_wG <= wen and way(6); + write_enable_wH <= wen and way(7); + + -- Read/Write Port Address Generate + rambAddrCalc : for t in 0 to ramb_base_addr-1 generate begin + R0 : if(t < ramb_base_addr-addressbus_width) generate begin + rd_addr(t) <= '0'; + wr_addr(t) <= '0'; + end generate; + R1 : if(t >= ramb_base_addr-addressbus_width) generate begin + rd_addr(t) <= addr_rd_01(t-(ramb_base_addr-addressbus_width)); + wr_addr(t) <= addr_wr(t-(ramb_base_addr-addressbus_width)); + end generate; + end generate rambAddrCalc; + + ramb_addr_wr <= tconv(wr_addr); + ramb_addr_rd <= tconv(rd_addr); + + data_outA <= tconv(ramb_data_outA); + data_outB <= tconv(ramb_data_outB); + data_outC <= tconv(ramb_data_outC); + data_outD <= tconv(ramb_data_outD); + data_outE <= tconv(ramb_data_outE); + data_outF <= tconv(ramb_data_outF); + data_outG <= tconv(ramb_data_outG); + data_outH <= tconv(ramb_data_outH); + + data_out <= data_outA((35-(port_bitwidth-1)) to 35) & data_outB((35-(port_bitwidth-1)) to 35) & + data_outC((35-(port_bitwidth-1)) to 35) & data_outD((35-(port_bitwidth-1)) to 35) & + data_outE((35-(port_bitwidth-1)) to 35) & data_outF((35-(port_bitwidth-1)) to 35) & + data_outG((35-(port_bitwidth-1)) to 35) & data_outH((35-(port_bitwidth-1)) to 35); + + arr0_A: RAMB16_S36_S36 + -- pragma translate_off + generic map( + -- all, none, warning_only, generate_x_only + sim_collision_check => "none") + -- pragma translate_on + port map( + DOA => ramb_data_outA(0 to 31), + DOB => open, + DOPA => ramb_data_outA(32 to 35), + DOPB => open, + ADDRA => ramb_addr_rd, + ADDRB => ramb_addr_wr, + CLKA => nclk.clk, + CLKB => nclk.clk, + DIA => tidn(0 to 31), + DIB => ramb_data_in(0 to 31), + DIPA => tidn(32 to 35), + DIPB => ramb_data_in(32 to 35), + ENA => act, + ENB => act, + SSRA => nclk.sreset, + SSRB => nclk.sreset, + WEA => tidn(0), + WEB => write_enable_wA + ); + + arr1_B: RAMB16_S36_S36 + -- pragma translate_off + generic map( + -- all, none, warning_only, generate_x_only + sim_collision_check => "none") + -- pragma translate_on + port map( + DOA => ramb_data_outB(0 to 31), + DOB => open, + DOPA => ramb_data_outB(32 to 35), + DOPB => open, + ADDRA => ramb_addr_rd, + ADDRB => ramb_addr_wr, + CLKA => nclk.clk, + CLKB => nclk.clk, + DIA => tidn(0 to 31), + DIB => ramb_data_in(0 to 31), + DIPA => tidn(32 to 35), + DIPB => ramb_data_in(32 to 35), + ENA => act, + ENB => act, + SSRA => nclk.sreset, + SSRB => nclk.sreset, + WEA => tidn(0), + WEB => write_enable_wB + ); + + arr2_C: RAMB16_S36_S36 + -- pragma translate_off + generic map( + -- all, none, warning_only, generate_x_only + sim_collision_check => "none") + -- pragma translate_on + port map( + DOA => ramb_data_outC(0 to 31), + DOB => open, + DOPA => ramb_data_outC(32 to 35), + DOPB => open, + ADDRA => ramb_addr_rd, + ADDRB => ramb_addr_wr, + CLKA => nclk.clk, + CLKB => nclk.clk, + DIA => tidn(0 to 31), + DIB => ramb_data_in(0 to 31), + DIPA => tidn(32 to 35), + DIPB => ramb_data_in(32 to 35), + ENA => act, + ENB => act, + SSRA => nclk.sreset, + SSRB => nclk.sreset, + WEA => tidn(0), + WEB => write_enable_wC + ); + + arr3_D: RAMB16_S36_S36 + -- pragma translate_off + generic map( + -- all, none, warning_only, generate_x_only + sim_collision_check => "none") + -- pragma translate_on + port map( + DOA => ramb_data_outD(0 to 31), + DOB => open, + DOPA => ramb_data_outD(32 to 35), + DOPB => open, + ADDRA => ramb_addr_rd, + ADDRB => ramb_addr_wr, + CLKA => nclk.clk, + CLKB => nclk.clk, + DIA => tidn(0 to 31), + DIB => ramb_data_in(0 to 31), + DIPA => tidn(32 to 35), + DIPB => ramb_data_in(32 to 35), + ENA => act, + ENB => act, + SSRA => nclk.sreset, + SSRB => nclk.sreset, + WEA => tidn(0), + WEB => write_enable_wD + ); + + arr4_E: RAMB16_S36_S36 + -- pragma translate_off + generic map( + -- all, none, warning_only, generate_x_only + sim_collision_check => "none") + -- pragma translate_on + port map( + DOA => ramb_data_outE(0 to 31), + DOB => open, + DOPA => ramb_data_outE(32 to 35), + DOPB => open, + ADDRA => ramb_addr_rd, + ADDRB => ramb_addr_wr, + CLKA => nclk.clk, + CLKB => nclk.clk, + DIA => tidn(0 to 31), + DIB => ramb_data_in(0 to 31), + DIPA => tidn(32 to 35), + DIPB => ramb_data_in(32 to 35), + ENA => act, + ENB => act, + SSRA => nclk.sreset, + SSRB => nclk.sreset, + WEA => tidn(0), + WEB => write_enable_wE + ); + + arr5_F: RAMB16_S36_S36 + -- pragma translate_off + generic map( + -- all, none, warning_only, generate_x_only + sim_collision_check => "none") + -- pragma translate_on + port map( + DOA => ramb_data_outF(0 to 31), + DOB => open, + DOPA => ramb_data_outF(32 to 35), + DOPB => open, + ADDRA => ramb_addr_rd, + ADDRB => ramb_addr_wr, + CLKA => nclk.clk, + CLKB => nclk.clk, + DIA => tidn(0 to 31), + DIB => ramb_data_in(0 to 31), + DIPA => tidn(32 to 35), + DIPB => ramb_data_in(32 to 35), + ENA => act, + ENB => act, + SSRA => nclk.sreset, + SSRB => nclk.sreset, + WEA => tidn(0), + WEB => write_enable_wF + ); + + arr6_G: RAMB16_S36_S36 + -- pragma translate_off + generic map( + -- all, none, warning_only, generate_x_only + sim_collision_check => "none") + -- pragma translate_on + port map( + DOA => ramb_data_outG(0 to 31), + DOB => open, + DOPA => ramb_data_outG(32 to 35), + DOPB => open, + ADDRA => ramb_addr_rd, + ADDRB => ramb_addr_wr, + CLKA => nclk.clk, + CLKB => nclk.clk, + DIA => tidn(0 to 31), + DIB => ramb_data_in(0 to 31), + DIPA => tidn(32 to 35), + DIPB => ramb_data_in(32 to 35), + ENA => act, + ENB => act, + SSRA => nclk.sreset, + SSRB => nclk.sreset, + WEA => tidn(0), + WEB => write_enable_wG + ); + + arr7_H: RAMB16_S36_S36 + -- pragma translate_off + generic map( + -- all, none, warning_only, generate_x_only + sim_collision_check => "none") + -- pragma translate_on + port map( + DOA => ramb_data_outH(0 to 31), + DOB => open, + DOPA => ramb_data_outH(32 to 35), + DOPB => open, + ADDRA => ramb_addr_rd, + ADDRB => ramb_addr_wr, + CLKA => nclk.clk, + CLKB => nclk.clk, + DIA => tidn(0 to 31), + DIB => ramb_data_in(0 to 31), + DIPA => tidn(32 to 35), + DIPB => ramb_data_in(32 to 35), + ENA => act, + ENB => act, + SSRA => nclk.sreset, + SSRB => nclk.sreset, + WEA => tidn(0), + WEB => write_enable_wH + ); + + abst_scan_out <= tidn(0); + time_scan_out <= tidn(0); + repr_scan_out <= tidn(0); + + bo_pc_failout <= "0000"; + bo_pc_diagloop <= "0000"; + + unused <= or_reduce( data_outA(0) & data_outB(0) & data_outC(0) & data_outD(0) + & data_outE(0) & data_outF(0) & data_outG(0) & data_outH(0) + & sg_0 & abst_slp_sl_thold_0 & ary_slp_nsl_thold_0 + & time_sl_thold_0 & repr_sl_thold_0 & clkoff_dc_b & ccflush_dc + & scan_dis_dc_b & scan_diag_dc & d_mode_dc & mpw1_dc_b & mpw2_dc_b + & delay_lclkr_dc & wr_abst_act & rd0_abst_act & abist_di + & abist_bw_odd & abist_bw_even & abist_wr_adr & abist_rd0_adr + & tc_lbist_ary_wrt_thru_dc & abist_ena_1 & abist_g8t_rd0_comp_ena + & abist_raw_dc_b & obs0_abist_cmp & abst_scan_in & time_scan_in + & repr_scan_in & addr_rd_23 & addr_rd_45 & addr_rd_67 + & lcb_bolt_sl_thold_0 & pc_bo_enable_2 & pc_bo_reset + & pc_bo_unload & pc_bo_repair & pc_bo_shdata & pc_bo_select + & tri_lcb_mpw1_dc_b & tri_lcb_mpw2_dc_b & tri_lcb_delay_lclkr_dc + & tri_lcb_clkoff_dc_b & tri_lcb_act_dis_dc ); + end generate a; + +end tri_32x35_8w_1r1w; diff --git a/rel/src/vhdl/tri/tri_512x288_9.vhdl b/rel/src/vhdl/tri/tri_512x288_9.vhdl new file mode 100644 index 0000000..4cba5a2 --- /dev/null +++ b/rel/src/vhdl/tri/tri_512x288_9.vhdl @@ -0,0 +1,784 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; use ieee.std_logic_1164.all ; +library ibm; use ibm.std_ulogic_support.all ; + use ibm.std_ulogic_function_support.all; +library support; use support.power_logic_pkg.all; +library tri; use tri.tri_latches_pkg.all; + +entity tri_512x288_9 is + generic (addressable_ports : positive := 512; -- number of addressable register in this array + addressbus_width : positive := 6; -- width of the bus to address all ports (2^addressbus_width >= addressable_ports) + port_bitwidth : positive := 288; -- bitwidth of ports (per way) + bit_write_type : positive := 9; -- gives the number of bits that shares one write-enable; must divide evenly into array + ways : positive := 1; -- number of ways + expand_type : integer := 1); -- 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) + port ( + -- POWER PINS + gnd : inout power_logic; + vdd : inout power_logic; + vcs : inout power_logic; + -- CLOCK and CLOCKCONTROL ports + nclk : in clk_logic; + act : in std_ulogic; + sg_0 : in std_ulogic; + sg_1 : in std_ulogic; + ary_nsl_thold_0 : in std_ulogic; + abst_sl_thold_0 : in std_ulogic; + time_sl_thold_0 : in std_ulogic; + repr_sl_thold_0 : in std_ulogic; + clkoff_dc_b : in std_ulogic; + ccflush_dc : in std_ulogic; + scan_dis_dc_b : in std_ulogic; + scan_diag_dc : in std_ulogic; + d_mode_dc : in std_ulogic; + act_dis_dc : in std_ulogic; + lcb_delay_lclkr_np_dc : in std_ulogic; + ctrl_lcb_delay_lclkr_np_dc : in std_ulogic; + dibw_lcb_delay_lclkr_np_dc : in std_ulogic; + ctrl_lcb_mpw1_np_dc_b : in std_ulogic; + dibw_lcb_mpw1_np_dc_b : in std_ulogic; + lcb_mpw1_pp_dc_b : in std_ulogic; + lcb_mpw1_2_pp_dc_b : in std_ulogic; + aodo_lcb_delay_lclkr_dc : in std_ulogic; + aodo_lcb_mpw1_dc_b : in std_ulogic; + aodo_lcb_mpw2_dc_b : in std_ulogic; + -- ABIST + bitw_abist : in std_ulogic_vector(0 to 1); + tc_lbist_ary_wrt_thru_dc : in std_ulogic; + abist_en_1 : in std_ulogic; + din_abist : in std_ulogic_vector(0 to 3); + abist_cmp_en : in std_ulogic; + abist_raw_b_dc : in std_ulogic; + data_cmp_abist : in std_ulogic_vector(0 to 3); + addr_abist : in std_ulogic_vector(0 to 8); + r_wb_abist : in std_ulogic; + -- Scan + abst_scan_in : in std_ulogic_vector(0 to 1); + time_scan_in : in std_ulogic; + repr_scan_in : in std_ulogic; + abst_scan_out : out std_ulogic_vector(0 to 1); + time_scan_out : out std_ulogic; + repr_scan_out : out std_ulogic; + -- BOLT-ON + lcb_bolt_sl_thold_0 : in std_ulogic; -- thold for any regs inside backend + pc_bo_enable_2 : in std_ulogic; -- general bolt-on enable, probably DC + pc_bo_reset : in std_ulogic; -- execute sticky bit decode + pc_bo_unload : in std_ulogic; + pc_bo_repair : in std_ulogic; -- load repair reg + pc_bo_shdata : in std_ulogic; -- shift data for timing write + pc_bo_select : in std_ulogic_vector(0 to 1); -- select for mask and hier writes + bo_pc_failout : out std_ulogic_vector(0 to 1); -- fail/no-fix reg + bo_pc_diagloop : out std_ulogic_vector(0 to 1); + tri_lcb_mpw1_dc_b : in std_ulogic; + tri_lcb_mpw2_dc_b : in std_ulogic; + tri_lcb_delay_lclkr_dc : in std_ulogic; + tri_lcb_clkoff_dc_b : in std_ulogic; + tri_lcb_act_dis_dc : in std_ulogic; + -- FUNCTIONAL PORTS + write_enable : in std_ulogic; + bw : in std_ulogic_vector (0 to (port_bitwidth-1)); + arr_up_addr : in std_ulogic_vector (0 to 2); + addr : in std_ulogic_vector (0 to (addressbus_width-1)); + data_in : in std_ulogic_vector (0 to (port_bitwidth-1)); + data_out : out std_ulogic_vector(0 to (port_bitwidth*ways-1)) +); + + -- synopsys translate_off + + -- synopsys translate_on + +end entity tri_512x288_9; + +architecture tri_512x288_9 of tri_512x288_9 is + + + + +constant ramb_base_addr : integer := 11; + +begin -- tri_512x288_9 + + -- synopsys translate_off + um: if expand_type = 0 generate + signal tiup : std_ulogic; + signal tidn : std_ulogic; + + signal addr_l2 : std_ulogic_vector(0 TO addressbus_width-1); + signal bw_l2 : std_ulogic_vector(0 TO bw'right); + signal write_enable_d : std_ulogic; + signal write_enable_l2 : std_ulogic; + signal data_in_l2 : std_ulogic_vector(0 to port_bitwidth-1); + signal array_d : std_ulogic_vector(0 to addressable_ports*port_bitwidth*ways-1); + signal array_l2 : std_ulogic_vector(0 to addressable_ports*port_bitwidth*ways-1); + begin + tiup <= '1'; + tidn <= '0'; + + addr_latch: tri_rlmreg_p + generic map (width => addr'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act, + scin => (others => '0'), + scout => open, + din => addr, + dout => addr_l2 ); + + bw_latch: tri_rlmreg_p + generic map (width => bw'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act, + scin => (others => '0'), + scout => open, + din => bw, + dout => bw_l2 ); + + write_enable_latch: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + scin => tidn, + scout => open, + din => write_enable_d, + dout => write_enable_l2 ); + + data_in_latch: tri_rlmreg_p + generic map (width => port_bitwidth, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act, + scin => (others => '0'), + scout => open, + din => data_in, + dout => data_in_l2 ); + + array_latch: tri_rlmreg_p + generic map (width => addressable_ports*port_bitwidth*ways, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + scin => (others => '0'), + scout => open, + din => array_d, + dout => array_l2 ); + + write_enable_d <= act and write_enable; + + ww: for w in 0 to ways-1 generate + begin + wy: for y in 0 to addressable_ports-1 generate + begin + wx: for x in 0 to port_bitwidth-1 generate + begin + array_d(y*port_bitwidth*ways+w*port_bitwidth+x) <= + data_in_l2(x) when (( write_enable_l2 and addr_l2 = tconv(y, addressbus_width) and bw_l2(x/bit_write_type) ) = '1') + else array_l2(y*port_bitwidth*ways+w*port_bitwidth+x); + + end generate wx; + end generate wy; + end generate ww; + + data_out <= array_l2( tconv(addr_l2)*port_bitwidth*ways to tconv(addr_l2)*port_bitwidth*ways+port_bitwidth*ways-1 ); + + abst_scan_out <= (others=>'0'); + time_scan_out <= tidn; + repr_scan_out <= tidn; + + bo_pc_failout <= (others=>'0'); + bo_pc_diagloop <= (others=>'0'); + end generate um; + -- synopsys translate_on + + a: if expand_type = 1 generate + component RAMB16_S9_S9 + -- pragma translate_off + generic + ( + SIM_COLLISION_CHECK : string := "none"); -- all, none, warning_only, GENERATE_X_ONLY + -- pragma translate_on + port + ( + DOA : out std_logic_vector(7 downto 0); + DOB : out std_logic_vector(7 downto 0); + DOPA : out std_logic_vector(0 downto 0); + DOPB : out std_logic_vector(0 downto 0); + ADDRA : in std_logic_vector(10 downto 0); + ADDRB : in std_logic_vector(10 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(7 downto 0); + DIB : in std_logic_vector(7 downto 0); + DIPA : in std_logic_vector(0 downto 0); + DIPB : in std_logic_vector(0 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); + end component; + + -- pragma translate_off + -- pragma translate_on + + constant addresswidth : integer := addressbus_width+3+1; + signal arr_data_in : std_logic_vector(0 to 287); + signal ramb_data_in : std_logic_vector(0 to 255); + signal ramb_parity_in : std_logic_vector(0 to 31); + signal ramb_uh_addr : std_ulogic_vector(0 to 10); + signal ramb_lh_addr : std_ulogic_vector(0 to 10); + signal uh_addr : std_ulogic_vector(0 to addresswidth-1); + signal lh_addr : std_ulogic_vector(0 to addresswidth-1); + signal ramb_data_out : std_logic_vector(0 to 255); + signal ramb_parity_out : std_logic_vector(0 to 31); + + signal tidn : std_ulogic; + signal wrt_en_wAH : std_ulogic_vector(0 to 31); + signal bitWrt : std_ulogic_vector(0 to 31); + signal rdDataOut : std_ulogic_vector(0 to 255); + signal rdParityOut : std_ulogic_vector(0 to 31); + + signal unused : std_ulogic; + -- synopsys translate_off + -- synopsys translate_on + begin + + tidn <= '0'; + + arr_data_in <= tconv(data_in); + + dWFixUp : for t in 0 to 31 generate begin + ramb_data_in((8*t) to (8*t)+7) <= arr_data_in(t+0) & arr_data_in(t+32) & arr_data_in(t+64) & arr_data_in(t+96) & + arr_data_in(t+144) & arr_data_in(t+176) & arr_data_in(t+208) & arr_data_in(t+240); + ramb_parity_in(t) <= arr_data_in(t+128+(128*(t/16))); + bitWrt(t) <= bw(t); + end generate dWFixUp; + + wrtEn_gen : for t in 0 to 31 generate begin + wrt_en_wAH(t) <= write_enable and bitWrt(t); + end generate wrtEn_gen; + + -- Read/Write Port Address Generate + uh_addr <= arr_up_addr & addr & '0'; + lh_addr <= arr_up_addr & addr & '1'; + + rambAddrCalc : for t in 0 to ramb_base_addr-1 generate begin + R0 : if(t < ramb_base_addr-addresswidth) generate begin + ramb_uh_addr(t) <= '0'; + ramb_lh_addr(t) <= '0'; + end generate; + R1 : if(t >= ramb_base_addr-addresswidth) generate begin + ramb_uh_addr(t) <= uh_addr(t-(ramb_base_addr-addresswidth)); + ramb_lh_addr(t) <= lh_addr(t-(ramb_base_addr-addresswidth)); + end generate; + end generate rambAddrCalc; + + dRFixUp : for t in 0 to 31 generate begin + data_out(t+0) <= rdDataOut((t*8)+0); + data_out(t+32) <= rdDataOut((t*8)+1); + data_out(t+64) <= rdDataOut((t*8)+2); + data_out(t+96) <= rdDataOut((t*8)+3); + data_out(t+144) <= rdDataOut((t*8)+4); + data_out(t+176) <= rdDataOut((t*8)+5); + data_out(t+208) <= rdDataOut((t*8)+6); + data_out(t+240) <= rdDataOut((t*8)+7); + data_out(t+128+(128*(t/16))) <= rdParityOut(t); + end generate dRFixUp; + + rdDataOut <= tconv(ramb_data_out); + rdParityOut <= tconv(ramb_parity_out); + + arr0: RAMB16_S9_S9 + -- pragma translate_off + generic map( + -- all, none, warning_only, generate_x_only + sim_collision_check => "none") + -- pragma translate_on + port map( + DOA => ramb_data_out(0 to 7), + DOB => ramb_data_out(128 to 135), + DOPA => ramb_parity_out(0 to 0), + DOPB => ramb_parity_out(16 to 16), + ADDRA => tconv(ramb_uh_addr), + ADDRB => tconv(ramb_lh_addr), + CLKA => nclk.clk, + CLKB => nclk.clk, + DIA => ramb_data_in(0 to 7), + DIB => ramb_data_in(128 to 135), + DIPA => ramb_parity_in(0 to 0), + DIPB => ramb_parity_in(16 to 16), + ENA => act, + ENB => act, + SSRA => nclk.sreset, + SSRB => nclk.sreset, + WEA => wrt_en_wAH(0), + WEB => wrt_en_wAH(16) + ); + + arr1: RAMB16_S9_S9 + -- pragma translate_off + generic map( + -- all, none, warning_only, generate_x_only + sim_collision_check => "none") + -- pragma translate_on + port map( + DOA => ramb_data_out(8 to 15), + DOB => ramb_data_out(136 to 143), + DOPA => ramb_parity_out(1 to 1), + DOPB => ramb_parity_out(17 to 17), + ADDRA => tconv(ramb_uh_addr), + ADDRB => tconv(ramb_lh_addr), + CLKA => nclk.clk, + CLKB => nclk.clk, + DIA => ramb_data_in(8 to 15), + DIB => ramb_data_in(136 to 143), + DIPA => ramb_parity_in(1 to 1), + DIPB => ramb_parity_in(17 to 17), + ENA => act, + ENB => act, + SSRA => nclk.sreset, + SSRB => nclk.sreset, + WEA => wrt_en_wAH(1), + WEB => wrt_en_wAH(17) + ); + + arr2: RAMB16_S9_S9 + -- pragma translate_off + generic map( + -- all, none, warning_only, generate_x_only + sim_collision_check => "none") + -- pragma translate_on + port map( + DOA => ramb_data_out(16 to 23), + DOB => ramb_data_out(144 to 151), + DOPA => ramb_parity_out(2 to 2), + DOPB => ramb_parity_out(18 to 18), + ADDRA => tconv(ramb_uh_addr), + ADDRB => tconv(ramb_lh_addr), + CLKA => nclk.clk, + CLKB => nclk.clk, + DIA => ramb_data_in(16 to 23), + DIB => ramb_data_in(144 to 151), + DIPA => ramb_parity_in(2 to 2), + DIPB => ramb_parity_in(18 to 18), + ENA => act, + ENB => act, + SSRA => nclk.sreset, + SSRB => nclk.sreset, + WEA => wrt_en_wAH(2), + WEB => wrt_en_wAH(18) + ); + + arr3: RAMB16_S9_S9 + -- pragma translate_off + generic map( + -- all, none, warning_only, generate_x_only + sim_collision_check => "none") + -- pragma translate_on + port map( + DOA => ramb_data_out(24 to 31), + DOB => ramb_data_out(152 to 159), + DOPA => ramb_parity_out(3 to 3), + DOPB => ramb_parity_out(19 to 19), + ADDRA => tconv(ramb_uh_addr), + ADDRB => tconv(ramb_lh_addr), + CLKA => nclk.clk, + CLKB => nclk.clk, + DIA => ramb_data_in(24 to 31), + DIB => ramb_data_in(152 to 159), + DIPA => ramb_parity_in(3 to 3), + DIPB => ramb_parity_in(19 to 19), + ENA => act, + ENB => act, + SSRA => nclk.sreset, + SSRB => nclk.sreset, + WEA => wrt_en_wAH(3), + WEB => wrt_en_wAH(19) + ); + + arr4: RAMB16_S9_S9 + -- pragma translate_off + generic map( + -- all, none, warning_only, generate_x_only + sim_collision_check => "none") + -- pragma translate_on + port map( + DOA => ramb_data_out(32 to 39), + DOB => ramb_data_out(160 to 167), + DOPA => ramb_parity_out(4 to 4), + DOPB => ramb_parity_out(20 to 20), + ADDRA => tconv(ramb_uh_addr), + ADDRB => tconv(ramb_lh_addr), + CLKA => nclk.clk, + CLKB => nclk.clk, + DIA => ramb_data_in(32 to 39), + DIB => ramb_data_in(160 to 167), + DIPA => ramb_parity_in(4 to 4), + DIPB => ramb_parity_in(20 to 20), + ENA => act, + ENB => act, + SSRA => nclk.sreset, + SSRB => nclk.sreset, + WEA => wrt_en_wAH(4), + WEB => wrt_en_wAH(20) + ); + + arr5: RAMB16_S9_S9 + -- pragma translate_off + generic map( + -- all, none, warning_only, generate_x_only + sim_collision_check => "none") + -- pragma translate_on + port map( + DOA => ramb_data_out(40 to 47), + DOB => ramb_data_out(168 to 175), + DOPA => ramb_parity_out(5 to 5), + DOPB => ramb_parity_out(21 to 21), + ADDRA => tconv(ramb_uh_addr), + ADDRB => tconv(ramb_lh_addr), + CLKA => nclk.clk, + CLKB => nclk.clk, + DIA => ramb_data_in(40 to 47), + DIB => ramb_data_in(168 to 175), + DIPA => ramb_parity_in(5 to 5), + DIPB => ramb_parity_in(21 to 21), + ENA => act, + ENB => act, + SSRA => nclk.sreset, + SSRB => nclk.sreset, + WEA => wrt_en_wAH(5), + WEB => wrt_en_wAH(21) + ); + + arr6: RAMB16_S9_S9 + -- pragma translate_off + generic map( + -- all, none, warning_only, generate_x_only + sim_collision_check => "none") + -- pragma translate_on + port map( + DOA => ramb_data_out(48 to 55), + DOB => ramb_data_out(176 to 183), + DOPA => ramb_parity_out(6 to 6), + DOPB => ramb_parity_out(22 to 22), + ADDRA => tconv(ramb_uh_addr), + ADDRB => tconv(ramb_lh_addr), + CLKA => nclk.clk, + CLKB => nclk.clk, + DIA => ramb_data_in(48 to 55), + DIB => ramb_data_in(176 to 183), + DIPA => ramb_parity_in(6 to 6), + DIPB => ramb_parity_in(22 to 22), + ENA => act, + ENB => act, + SSRA => nclk.sreset, + SSRB => nclk.sreset, + WEA => wrt_en_wAH(6), + WEB => wrt_en_wAH(22) + ); + + arr7: RAMB16_S9_S9 + -- pragma translate_off + generic map( + -- all, none, warning_only, generate_x_only + sim_collision_check => "none") + -- pragma translate_on + port map( + DOA => ramb_data_out(56 to 63), + DOB => ramb_data_out(184 to 191), + DOPA => ramb_parity_out(7 to 7), + DOPB => ramb_parity_out(23 to 23), + ADDRA => tconv(ramb_uh_addr), + ADDRB => tconv(ramb_lh_addr), + CLKA => nclk.clk, + CLKB => nclk.clk, + DIA => ramb_data_in(56 to 63), + DIB => ramb_data_in(184 to 191), + DIPA => ramb_parity_in(7 to 7), + DIPB => ramb_parity_in(23 to 23), + ENA => act, + ENB => act, + SSRA => nclk.sreset, + SSRB => nclk.sreset, + WEA => wrt_en_wAH(7), + WEB => wrt_en_wAH(23) + ); + + arr8: RAMB16_S9_S9 + -- pragma translate_off + generic map( + -- all, none, warning_only, generate_x_only + sim_collision_check => "none") + -- pragma translate_on + port map( + DOA => ramb_data_out(64 to 71), + DOB => ramb_data_out(192 to 199), + DOPA => ramb_parity_out(8 to 8), + DOPB => ramb_parity_out(24 to 24), + ADDRA => tconv(ramb_uh_addr), + ADDRB => tconv(ramb_lh_addr), + CLKA => nclk.clk, + CLKB => nclk.clk, + DIA => ramb_data_in(64 to 71), + DIB => ramb_data_in(192 to 199), + DIPA => ramb_parity_in(8 to 8), + DIPB => ramb_parity_in(24 to 24), + ENA => act, + ENB => act, + SSRA => nclk.sreset, + SSRB => nclk.sreset, + WEA => wrt_en_wAH(8), + WEB => wrt_en_wAH(24) + ); + + arr9: RAMB16_S9_S9 + -- pragma translate_off + generic map( + -- all, none, warning_only, generate_x_only + sim_collision_check => "none") + -- pragma translate_on + port map( + DOA => ramb_data_out(72 to 79), + DOB => ramb_data_out(200 to 207), + DOPA => ramb_parity_out(9 to 9), + DOPB => ramb_parity_out(25 to 25), + ADDRA => tconv(ramb_uh_addr), + ADDRB => tconv(ramb_lh_addr), + CLKA => nclk.clk, + CLKB => nclk.clk, + DIA => ramb_data_in(72 to 79), + DIB => ramb_data_in(200 to 207), + DIPA => ramb_parity_in(9 to 9), + DIPB => ramb_parity_in(25 to 25), + ENA => act, + ENB => act, + SSRA => nclk.sreset, + SSRB => nclk.sreset, + WEA => wrt_en_wAH(9), + WEB => wrt_en_wAH(25) + ); + + arrA: RAMB16_S9_S9 + -- pragma translate_off + generic map( + -- all, none, warning_only, generate_x_only + sim_collision_check => "none") + -- pragma translate_on + port map( + DOA => ramb_data_out(80 to 87), + DOB => ramb_data_out(208 to 215), + DOPA => ramb_parity_out(10 to 10), + DOPB => ramb_parity_out(26 to 26), + ADDRA => tconv(ramb_uh_addr), + ADDRB => tconv(ramb_lh_addr), + CLKA => nclk.clk, + CLKB => nclk.clk, + DIA => ramb_data_in(80 to 87), + DIB => ramb_data_in(208 to 215), + DIPA => ramb_parity_in(10 to 10), + DIPB => ramb_parity_in(26 to 26), + ENA => act, + ENB => act, + SSRA => nclk.sreset, + SSRB => nclk.sreset, + WEA => wrt_en_wAH(10), + WEB => wrt_en_wAH(26) + ); + + arrB: RAMB16_S9_S9 + -- pragma translate_off + generic map( + -- all, none, warning_only, generate_x_only + sim_collision_check => "none") + -- pragma translate_on + port map( + DOA => ramb_data_out(88 to 95), + DOB => ramb_data_out(216 to 223), + DOPA => ramb_parity_out(11 to 11), + DOPB => ramb_parity_out(27 to 27), + ADDRA => tconv(ramb_uh_addr), + ADDRB => tconv(ramb_lh_addr), + CLKA => nclk.clk, + CLKB => nclk.clk, + DIA => ramb_data_in(88 to 95), + DIB => ramb_data_in(216 to 223), + DIPA => ramb_parity_in(11 to 11), + DIPB => ramb_parity_in(27 to 27), + ENA => act, + ENB => act, + SSRA => nclk.sreset, + SSRB => nclk.sreset, + WEA => wrt_en_wAH(11), + WEB => wrt_en_wAH(27) + ); + + arrC: RAMB16_S9_S9 + -- pragma translate_off + generic map( + -- all, none, warning_only, generate_x_only + sim_collision_check => "none") + -- pragma translate_on + port map( + DOA => ramb_data_out(96 to 103), + DOB => ramb_data_out(224 to 231), + DOPA => ramb_parity_out(12 to 12), + DOPB => ramb_parity_out(28 to 28), + ADDRA => tconv(ramb_uh_addr), + ADDRB => tconv(ramb_lh_addr), + CLKA => nclk.clk, + CLKB => nclk.clk, + DIA => ramb_data_in(96 to 103), + DIB => ramb_data_in(224 to 231), + DIPA => ramb_parity_in(12 to 12), + DIPB => ramb_parity_in(28 to 28), + ENA => act, + ENB => act, + SSRA => nclk.sreset, + SSRB => nclk.sreset, + WEA => wrt_en_wAH(12), + WEB => wrt_en_wAH(28) + ); + + arrD: RAMB16_S9_S9 + -- pragma translate_off + generic map( + -- all, none, warning_only, generate_x_only + sim_collision_check => "none") + -- pragma translate_on + port map( + DOA => ramb_data_out(104 to 111), + DOB => ramb_data_out(232 to 239), + DOPA => ramb_parity_out(13 to 13), + DOPB => ramb_parity_out(29 to 29), + ADDRA => tconv(ramb_uh_addr), + ADDRB => tconv(ramb_lh_addr), + CLKA => nclk.clk, + CLKB => nclk.clk, + DIA => ramb_data_in(104 to 111), + DIB => ramb_data_in(232 to 239), + DIPA => ramb_parity_in(13 to 13), + DIPB => ramb_parity_in(29 to 29), + ENA => act, + ENB => act, + SSRA => nclk.sreset, + SSRB => nclk.sreset, + WEA => wrt_en_wAH(13), + WEB => wrt_en_wAH(29) + ); + + arrE: RAMB16_S9_S9 + -- pragma translate_off + generic map( + -- all, none, warning_only, generate_x_only + sim_collision_check => "none") + -- pragma translate_on + port map( + DOA => ramb_data_out(112 to 119), + DOB => ramb_data_out(240 to 247), + DOPA => ramb_parity_out(14 to 14), + DOPB => ramb_parity_out(30 to 30), + ADDRA => tconv(ramb_uh_addr), + ADDRB => tconv(ramb_lh_addr), + CLKA => nclk.clk, + CLKB => nclk.clk, + DIA => ramb_data_in(112 to 119), + DIB => ramb_data_in(240 to 247), + DIPA => ramb_parity_in(14 to 14), + DIPB => ramb_parity_in(30 to 30), + ENA => act, + ENB => act, + SSRA => nclk.sreset, + SSRB => nclk.sreset, + WEA => wrt_en_wAH(14), + WEB => wrt_en_wAH(30) + ); + + arrF: RAMB16_S9_S9 + -- pragma translate_off + generic map( + -- all, none, warning_only, generate_x_only + sim_collision_check => "none") + -- pragma translate_on + port map( + DOA => ramb_data_out(120 to 127), + DOB => ramb_data_out(248 to 255), + DOPA => ramb_parity_out(15 to 15), + DOPB => ramb_parity_out(31 to 31), + ADDRA => tconv(ramb_uh_addr), + ADDRB => tconv(ramb_lh_addr), + CLKA => nclk.clk, + CLKB => nclk.clk, + DIA => ramb_data_in(120 to 127), + DIB => ramb_data_in(248 to 255), + DIPA => ramb_parity_in(15 to 15), + DIPB => ramb_parity_in(31 to 31), + ENA => act, + ENB => act, + SSRA => nclk.sreset, + SSRB => nclk.sreset, + WEA => wrt_en_wAH(15), + WEB => wrt_en_wAH(31) + ); + + abst_scan_out <= (others=>'0'); + time_scan_out <= tidn; + repr_scan_out <= tidn; + + bo_pc_failout <= (others=>'0'); + bo_pc_diagloop <= (others=>'0'); + + unused <= or_reduce( bw(32 to port_bitwidth-1) + & clkoff_dc_b & ccflush_dc & scan_dis_dc_b & scan_diag_dc & d_mode_dc & act_dis_dc + & bitw_abist & sg_0 & sg_1 + & abst_sl_thold_0 & repr_sl_thold_0 + & time_sl_thold_0 & ary_nsl_thold_0 & tc_lbist_ary_wrt_thru_dc + & abist_en_1 & din_abist & abist_cmp_en & abist_raw_b_dc & data_cmp_abist + & addr_abist & r_wb_abist & abst_scan_in & time_scan_in & repr_scan_in + & lcb_delay_lclkr_np_dc & ctrl_lcb_delay_lclkr_np_dc & dibw_lcb_delay_lclkr_np_dc + & ctrl_lcb_mpw1_np_dc_b & dibw_lcb_mpw1_np_dc_b & lcb_mpw1_pp_dc_b & lcb_mpw1_2_pp_dc_b + & aodo_lcb_delay_lclkr_dc & aodo_lcb_mpw1_dc_b & aodo_lcb_mpw2_dc_b + & lcb_bolt_sl_thold_0 & pc_bo_enable_2 & pc_bo_reset + & pc_bo_unload & pc_bo_repair & pc_bo_shdata & pc_bo_select + & tri_lcb_mpw1_dc_b & tri_lcb_mpw2_dc_b & tri_lcb_delay_lclkr_dc + & tri_lcb_clkoff_dc_b & tri_lcb_act_dis_dc ); + + end generate a; + + +end tri_512x288_9; diff --git a/rel/src/vhdl/tri/tri_64x36_4w_1r1w.vhdl b/rel/src/vhdl/tri/tri_64x36_4w_1r1w.vhdl new file mode 100644 index 0000000..06d2bdd --- /dev/null +++ b/rel/src/vhdl/tri/tri_64x36_4w_1r1w.vhdl @@ -0,0 +1,364 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; use ieee.std_logic_1164.all ; +library ibm; use ibm.std_ulogic_support.all ; + use ibm.std_ulogic_function_support.all; +library support; + use support.power_logic_pkg.all; +library tri; use tri.tri_latches_pkg.all; +-- pragma translate_off +-- pragma translate_on + +entity tri_64x36_4w_1r1w is + generic (addressable_ports : positive := 64; -- number of addressable register in this array + addressbus_width : positive := 6; -- width of the bus to address all ports (2^addressbus_width >= addressable_ports) + port_bitwidth : positive := 36; -- bitwidth of ports + ways : positive := 4; -- number of ways + expand_type : integer := 1); -- 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) + port ( + -- POWER PINS + gnd : inout power_logic; + vdd : inout power_logic; + vcs : inout power_logic; + -- CLOCK and CLOCKCONTROL ports + nclk : in clk_logic; + rd_act : in std_ulogic; + wr_act : in std_ulogic; + sg_0 : in std_ulogic; + abst_sl_thold_0 : in std_ulogic; + ary_nsl_thold_0 : in std_ulogic; + time_sl_thold_0 : in std_ulogic; + repr_sl_thold_0 : in std_ulogic; + clkoff_dc_b : in std_ulogic; + ccflush_dc : in std_ulogic; + scan_dis_dc_b : in std_ulogic; + scan_diag_dc : in std_ulogic; + d_mode_dc : in std_ulogic; + mpw1_dc_b : in std_ulogic_vector(0 to 4); + mpw2_dc_b : in std_ulogic; + delay_lclkr_dc : in std_ulogic_vector(0 to 4); + -- ABIST + wr_abst_act : in std_ulogic; + rd0_abst_act : in std_ulogic; + abist_di : in std_ulogic_vector(0 to 3); + abist_bw_odd : in std_ulogic; + abist_bw_even : in std_ulogic; + abist_wr_adr : in std_ulogic_vector(0 to 5); + abist_rd0_adr : in std_ulogic_vector(0 to 5); + tc_lbist_ary_wrt_thru_dc : in std_ulogic; + abist_ena_1 : in std_ulogic; + abist_g8t_rd0_comp_ena : in std_ulogic; + abist_raw_dc_b : in std_ulogic; + obs0_abist_cmp : in std_ulogic_vector(0 to 3); + -- Scan + abst_scan_in : in std_ulogic_vector(0 to 1); + time_scan_in : in std_ulogic; + repr_scan_in : in std_ulogic; + abst_scan_out : out std_ulogic_vector(0 to 1); + time_scan_out : out std_ulogic; + repr_scan_out : out std_ulogic; + -- BOLT-ON + lcb_bolt_sl_thold_0 : in std_ulogic; + pc_bo_enable_2 : in std_ulogic; -- general bolt-on enable + pc_bo_reset : in std_ulogic; -- reset + pc_bo_unload : in std_ulogic; -- unload sticky bits + pc_bo_repair : in std_ulogic; -- execute sticky bit decode + pc_bo_shdata : in std_ulogic; -- shift data for timing write and diag loop + pc_bo_select : in std_ulogic_vector(0 to 1); -- select for mask and hier writes + bo_pc_failout : out std_ulogic_vector(0 to 1); -- fail/no-fix reg + bo_pc_diagloop : out std_ulogic_vector(0 to 1); + tri_lcb_mpw1_dc_b : in std_ulogic; + tri_lcb_mpw2_dc_b : in std_ulogic; + tri_lcb_delay_lclkr_dc : in std_ulogic; + tri_lcb_clkoff_dc_b : in std_ulogic; + tri_lcb_act_dis_dc : in std_ulogic; + -- Write Ports + wr_way : in std_ulogic_vector (0 to (ways-1)); + wr_addr : in std_ulogic_vector (0 to (addressbus_width-1)); + data_in : in std_ulogic_vector (0 to (port_bitwidth*ways-1)); + -- Read Ports + rd_addr : in std_ulogic_vector(0 to (addressbus_width-1)); + data_out : out std_ulogic_vector(0 to (port_bitwidth*ways-1)) +); + + -- synopsys translate_off + + -- synopsys translate_on + +end entity tri_64x36_4w_1r1w; + +architecture tri_64x36_4w_1r1w of tri_64x36_4w_1r1w is + +constant wga_base_width : integer := 72; +constant wga_width_mult : integer := (port_bitwidth*ways-1)/wga_base_width + 1; +constant ramb_base_width : integer := 36; +constant ramb_base_addr : integer := 9; +constant ramb_width_mult : integer := (port_bitwidth-1)/ramb_base_width + 1; + + +type RAMB_DATA_ARRAY is array (natural range <>) of std_logic_vector(0 to (ramb_base_width*ramb_width_mult - 1)); + + +begin -- tri_64x36_4w_1r1w + + -- synopsys translate_off + um: if expand_type = 0 generate + signal tiup : std_ulogic; + signal tidn : std_ulogic; + + signal wr_addr_l2 : std_ulogic_vector (0 TO addressbus_width-1); + signal rd_addr_l2 : std_ulogic_vector (0 TO addressbus_width-1); + signal way_l2 : std_ulogic_vector (0 TO wr_way'right); + signal write_enable_l2 : std_ulogic; + signal data_in_l2 : std_ulogic_vector(0 to port_bitwidth*ways-1); + signal array_d : std_ulogic_vector(0 to addressable_ports*port_bitwidth*ways-1); + signal array_l2 : std_ulogic_vector(0 to addressable_ports*port_bitwidth*ways-1); + begin + tiup <= '1'; + tidn <= '0'; + + wr_addr_latch: tri_rlmreg_p + generic map (width => wr_addr'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => wr_act, + scin => (others => '0'), + scout => open, + din => wr_addr, + dout => wr_addr_l2 ); + + rd_addr_latch: tri_rlmreg_p + generic map (width => rd_addr'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rd_act, + scin => (others => '0'), + scout => open, + din => rd_addr, + dout => rd_addr_l2 ); + + way_latch: tri_rlmreg_p + generic map (width => wr_way'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => wr_act, + scin => (others => '0'), + scout => open, + din => wr_way, + dout => way_l2 ); + + write_enable_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + scin => tidn, + scout => open, + din => wr_act, + dout => write_enable_l2 ); + + data_in_latch: tri_rlmreg_p + generic map (width => port_bitwidth*ways, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => wr_act, + scin => (others => '0'), + scout => open, + din => data_in, + dout => data_in_l2 ); + + array_latch: tri_rlmreg_p + generic map (width => addressable_ports*port_bitwidth*ways, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + scin => (others => '0'), + scout => open, + din => array_d, + dout => array_l2 ); + + ww: for w in 0 to ways-1 generate + begin + wy: for y in 0 to addressable_ports-1 generate + begin + wx: for x in 0 to port_bitwidth-1 generate + begin + array_d(y*port_bitwidth*ways+w*port_bitwidth+x) <= + data_in_l2(w*port_bitwidth+x) when (( write_enable_l2 and wr_addr_l2 = tconv(y, addressbus_width) and + way_l2(w)) = '1') + else array_l2(y*port_bitwidth*ways+w*port_bitwidth+x); + + end generate wx; + end generate wy; + end generate ww; + + data_out <= array_l2( tconv(rd_addr_l2)*port_bitwidth*ways to tconv(rd_addr_l2)*port_bitwidth*ways+port_bitwidth*ways-1 ); + + abst_scan_out <= tidn & tidn; + time_scan_out <= tidn; + repr_scan_out <= tidn; + + bo_pc_failout <= tidn & tidn; + bo_pc_diagloop <= tidn & tidn; + end generate um; + -- synopsys translate_on + + + a: if expand_type = 1 generate + component RAMB16_S36_S36 + -- pragma translate_off + generic + ( + SIM_COLLISION_CHECK : string := "none"); -- all, none, warning_only, GENERATE_X_ONLY + -- pragma translate_on + port + ( + DOA : out std_logic_vector(31 downto 0); + DOB : out std_logic_vector(31 downto 0); + DOPA : out std_logic_vector(3 downto 0); + DOPB : out std_logic_vector(3 downto 0); + ADDRA : in std_logic_vector(8 downto 0); + ADDRB : in std_logic_vector(8 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(31 downto 0); + DIB : in std_logic_vector(31 downto 0); + DIPA : in std_logic_vector(3 downto 0); + DIPB : in std_logic_vector(3 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); + end component; + + -- pragma translate_off + -- pragma translate_on + + signal ramb_data_in : RAMB_DATA_ARRAY(wr_way'range); + signal ramb_data_out : RAMB_DATA_ARRAY(wr_way'range); + signal ramb_rd_addr : std_logic_vector(0 to ramb_base_addr - 1); + signal ramb_wr_addr : std_logic_vector(0 to ramb_base_addr - 1); + + signal tidn : std_ulogic; + signal unused : std_ulogic; + -- synopsys translate_off + -- synopsys translate_on + begin + + tidn <= '0'; + + add0: if (addressbus_width < ramb_base_addr) generate + begin + ramb_rd_addr(0 to (ramb_base_addr-addressbus_width-1)) <= (others => '0'); + ramb_rd_addr(ramb_base_addr-addressbus_width to ramb_base_addr-1) <= tconv( rd_addr ); + + ramb_wr_addr(0 to (ramb_base_addr-addressbus_width-1)) <= (others => '0'); + ramb_wr_addr(ramb_base_addr-addressbus_width to ramb_base_addr-1) <= tconv( wr_addr ); + end generate; + add1: if (addressbus_width >= ramb_base_addr) generate + begin + ramb_rd_addr <= tconv( rd_addr(addressbus_width-ramb_base_addr to addressbus_width-1) ); + ramb_wr_addr <= tconv( wr_addr(addressbus_width-ramb_base_addr to addressbus_width-1) ); + end generate; + + dw: for w in wr_way'range generate begin + din: for i in 0 to (ramb_base_width*ramb_width_mult - 1) generate + begin + R0: if(i < port_bitwidth) generate begin ramb_data_in(w)(i) <= data_in(w*port_bitwidth+i); end generate; + R1: if(i >= port_bitwidth) generate begin ramb_data_in(w)(i) <= '0'; end generate; + end generate din; + end generate dw; + + aw: for w in wr_way'range generate begin + ax: for x in 0 to (ramb_width_mult - 1) generate begin + arr: RAMB16_S36_S36 + -- pragma translate_off + generic map( + -- all, none, warning_only, generate_x_only + sim_collision_check => "none") + -- pragma translate_on + port map( + DOA => ramb_data_out(w)(x*ramb_base_width to x*ramb_base_width+31), + DOB => open, + DOPA => ramb_data_out(w)(x*ramb_base_width+32 to x*ramb_base_width+35), + DOPB => open, + ADDRA => ramb_rd_addr, + ADDRB => ramb_wr_addr, + CLKA => nclk.clk, + CLKB => nclk.clk, + DIA => ramb_data_in(w)(x*ramb_base_width to x*ramb_base_width+31), + DIB => ramb_data_in(w)(x*ramb_base_width to x*ramb_base_width+31), + DIPA => ramb_data_in(w)(x*ramb_base_width+32 to x*ramb_base_width+35), + DIPB => ramb_data_in(w)(x*ramb_base_width+32 to x*ramb_base_width+35), + ENA => rd_act, + ENB => wr_act, + SSRA => nclk.sreset, + SSRB => nclk.sreset, + WEA => tidn, + WEB => wr_way(w) + ); + + end generate ax; + + data_out(w*port_bitwidth to ((w+1)*port_bitwidth)-1 ) <= tconv( ramb_data_out(w)(0 to port_bitwidth-1) ); + + end generate aw; + + abst_scan_out <= tidn & tidn; + time_scan_out <= tidn; + repr_scan_out <= tidn; + + bo_pc_failout <= tidn & tidn; + bo_pc_diagloop <= tidn & tidn; + + unused <= or_reduce( sg_0 & abst_sl_thold_0 & ary_nsl_thold_0 + & time_sl_thold_0 & repr_sl_thold_0 & clkoff_dc_b & ccflush_dc + & scan_dis_dc_b & scan_diag_dc & d_mode_dc & mpw1_dc_b & mpw2_dc_b + & delay_lclkr_dc & wr_abst_act & rd0_abst_act & abist_di + & abist_bw_odd & abist_bw_even & abist_wr_adr & abist_rd0_adr + & tc_lbist_ary_wrt_thru_dc & abist_ena_1 & abist_g8t_rd0_comp_ena + & abist_raw_dc_b & obs0_abist_cmp & abst_scan_in & time_scan_in + & repr_scan_in & lcb_bolt_sl_thold_0 & pc_bo_enable_2 & pc_bo_reset + & pc_bo_unload & pc_bo_repair & pc_bo_shdata & pc_bo_select + & tri_lcb_mpw1_dc_b & tri_lcb_mpw2_dc_b & tri_lcb_delay_lclkr_dc + & tri_lcb_clkoff_dc_b & tri_lcb_act_dis_dc ); + end generate a; + + +end tri_64x36_4w_1r1w; diff --git a/rel/src/vhdl/tri/tri_64x42_4w_1r1w.vhdl b/rel/src/vhdl/tri/tri_64x42_4w_1r1w.vhdl new file mode 100644 index 0000000..6973ba9 --- /dev/null +++ b/rel/src/vhdl/tri/tri_64x42_4w_1r1w.vhdl @@ -0,0 +1,390 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee,ibm,support,tri; +use ieee.std_logic_1164.all; +use ibm.std_ulogic_function_support.all; +use support.power_logic_pkg.all; +use tri.tri_latches_pkg.all; +-- pragma translate_off +-- pragma translate_on + +entity tri_64x42_4w_1r1w is +generic( + expand_type : integer := 1); +port ( + -- Power + vdd : INOUT power_logic; + vcs : INOUT power_logic; + gnd : INOUT power_logic; + + -- Clock Pervasive + nclk : in clk_logic; + sg_0 : in std_ulogic; + abst_sl_thold_0 : in std_ulogic; + ary_nsl_thold_0 : in std_ulogic; + time_sl_thold_0 : in std_ulogic; + repr_sl_thold_0 : in std_ulogic; + + -- Reads + rd0_act : in std_ulogic; + rd0_adr : in std_ulogic_vector(0 to 5); + do0 : out std_ulogic_vector(0 to 167); + + -- Writes + wr_way : in std_ulogic_vector (0 to 3); + wr_act : in std_ulogic; + wr_adr : in std_ulogic_vector(0 to 5); + di : in std_ulogic_vector(0 to 167); + + -- Scan + abst_scan_in : in std_ulogic; + abst_scan_out : out std_ulogic; + time_scan_in : in std_ulogic; + time_scan_out : out std_ulogic; + repr_scan_in : in std_ulogic; + repr_scan_out : out std_ulogic; + + -- Misc Pervasive + scan_dis_dc_b : in std_ulogic; + scan_diag_dc : in std_ulogic; + ccflush_dc : in std_ulogic; + ary0_clkoff_dc_b : in std_ulogic; + ary0_d_mode_dc : in std_ulogic; + ary0_mpw1_dc_b : in std_ulogic_vector(0 to 4); + ary0_mpw2_dc_b : in std_ulogic; + ary0_delay_lclkr_dc : in std_ulogic_vector(0 to 4); + ary1_clkoff_dc_b : in std_ulogic; + ary1_d_mode_dc : in std_ulogic; + ary1_mpw1_dc_b : in std_ulogic_vector(0 to 4); + ary1_mpw2_dc_b : in std_ulogic; + ary1_delay_lclkr_dc : in std_ulogic_vector(0 to 4); + + -- BOLT-ON + lcb_bolt_sl_thold_0 : in std_ulogic; + pc_bo_enable_2 : in std_ulogic; -- general bolt-on enable + pc_bo_reset : in std_ulogic; -- reset + pc_bo_unload : in std_ulogic; -- unload sticky bits + pc_bo_repair : in std_ulogic; -- execute sticky bit decode + pc_bo_shdata : in std_ulogic; -- shift data for timing write and diag loop + pc_bo_select : in std_ulogic_vector(0 to 1); -- select for mask and hier writes + bo_pc_failout : out std_ulogic_vector(0 to 1); -- fail/no-fix reg + bo_pc_diagloop : out std_ulogic_vector(0 to 1); + tri_lcb_mpw1_dc_b : in std_ulogic; + tri_lcb_mpw2_dc_b : in std_ulogic; + tri_lcb_delay_lclkr_dc : in std_ulogic; + tri_lcb_clkoff_dc_b : in std_ulogic; + tri_lcb_act_dis_dc : in std_ulogic; + + -- ABIST + abist_di : in std_ulogic_vector(0 to 3); + abist_bw_odd : in std_ulogic; + abist_bw_even : in std_ulogic; + abist_wr_adr : in std_ulogic_vector(0 to 5); + wr_abst_act : in std_ulogic; + abist_rd0_adr : in std_ulogic_vector(0 to 5); + rd0_abst_act : in std_ulogic; + tc_lbist_ary_wrt_thru_dc : in std_ulogic; + abist_ena_1 : in std_ulogic; + abist_g8t_rd0_comp_ena : in std_ulogic; + abist_raw_dc_b : in std_ulogic; + obs0_abist_cmp : in std_ulogic_vector(0 to 3) + ); + +-- synopsys translate_off +-- synopsys translate_on + + +end entity tri_64x42_4w_1r1w; +architecture tri_64x42_4w_1r1w of tri_64x42_4w_1r1w is + +begin + +a : if expand_type = 1 generate + +component RAMB16_S36_S36 +-- pragma translate_off +generic( + SIM_COLLISION_CHECK : string := "none"); -- all, none, warning_only, GENERATE_X_ONLY +-- pragma translate_on +port( + DOA : out std_logic_vector(31 downto 0); + DOB : out std_logic_vector(31 downto 0); + DOPA : out std_logic_vector(3 downto 0); + DOPB : out std_logic_vector(3 downto 0); + ADDRA : in std_logic_vector(8 downto 0); + ADDRB : in std_logic_vector(8 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(31 downto 0); + DIB : in std_logic_vector(31 downto 0); + DIPA : in std_logic_vector(3 downto 0); + DIPB : in std_logic_vector(3 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic); +end component; + +-- pragma translate_off +-- pragma translate_on + +signal clk, clk2x : std_ulogic; +signal addra, addrb : std_ulogic_vector(0 to 8); +signal wea0, wea1, wea2, wea3 : std_ulogic; +signal web0, web1, web2, web3 : std_ulogic; +signal bdo0, bdo1, bdo2, bdo3 : std_logic_vector(0 to 71); +signal bdi0, bdi1, bdi2, bdi3 : std_ulogic_vector(0 to 71); +signal sreset : std_ulogic; +signal tidn : std_ulogic_vector(36 to 65); +-- Latches +signal reset_q : std_ulogic; +signal gate_fq, gate_d : std_ulogic; +signal bdo_d, bdo_fq : std_ulogic_vector(0 to 167); + +signal toggle_d : std_ulogic; +signal toggle_q : std_ulogic; +signal toggle2x_d : std_ulogic; +signal toggle2x_q : std_ulogic; + +signal unused : std_ulogic; +-- synopsys translate_off +-- synopsys translate_on + +begin + +tidn <= (others=>'0'); +clk <= nclk.clk; +clk2x <= nclk.clk2x; +sreset<= nclk.sreset; + +rlatch: process (clk) begin + if(rising_edge(clk)) then + reset_q <= sreset after 10 ps; + end if; +end process; + + +tlatch: process (nclk.clk,reset_q) +begin + if(rising_edge(nclk.clk)) then + if (reset_q = '1') then + toggle_q <= '1'; + else + toggle_q <= toggle_d; + end if; + end if; +end process; + +flatch: process (nclk.clk2x) +begin + if(rising_edge(nclk.clk2x)) then + toggle2x_q <= toggle2x_d; + gate_fq <= gate_d; + bdo_fq <= bdo_d; + end if; +end process; + +toggle_d <= not toggle_q; +toggle2x_d <= toggle_q; + +gate_d <= not(toggle_q xor toggle2x_q); + + + + + + + + bdi0 <= di(0 to 35) & tidn(36 to 65) & di(36 to 41); + bdi1 <= di(42 to 77) & tidn(36 to 65) & di(78 to 83); + bdi2 <= di(84 to 119) & tidn(36 to 65) & di(120 to 125); + bdi3 <= di(126 to 161) & tidn(36 to 65) & di(162 to 167); + +bdo_d(0 to 41) <= std_ulogic_vector(bdo0(0 to 35) & bdo0(66 to 71)); +bdo_d(42 to 83) <= std_ulogic_vector(bdo1(0 to 35) & bdo1(66 to 71)); +bdo_d(84 to 125) <= std_ulogic_vector(bdo2(0 to 35) & bdo2(66 to 71)); +bdo_d(126 to 167) <= std_ulogic_vector(bdo3(0 to 35) & bdo3(66 to 71)); + +do0 <= bdo_fq; + +wea0 <= (wr_act and gate_fq and wr_way(0)) after 10 ps; +web0 <= (wr_act and gate_fq and wr_way(0)) after 10 ps; +wea1 <= (wr_act and gate_fq and wr_way(1)) after 10 ps; +web1 <= (wr_act and gate_fq and wr_way(1)) after 10 ps; +wea2 <= (wr_act and gate_fq and wr_way(2)) after 10 ps; +web2 <= (wr_act and gate_fq and wr_way(2)) after 10 ps; +wea3 <= (wr_act and gate_fq and wr_way(3)) after 10 ps; +web3 <= (wr_act and gate_fq and wr_way(3)) after 10 ps; + +with gate_fq select + addra <= ("00" & wr_adr & '0') after 10 ps when '1', + ("00" & rd0_adr & '0') after 10 ps when others; + +with gate_fq select + addrb <= ("00" & wr_adr & '1') after 10 ps when '1', + ("00" & rd0_adr & '1') after 10 ps when others; + +bram0a : ramb16_s36_s36 +-- pragma translate_off +generic map( +-- all, none, warning_only, generate_x_only + sim_collision_check => "none") +-- pragma translate_on +port map( + clka => clk2x, + clkb => clk2x, + ssra => sreset, + ssrb => sreset, + addra => std_logic_vector(addra), + addrb => std_logic_vector(addrb), + dia => std_logic_vector(bdi0(00 to 31)), + dipa => std_logic_vector(bdi0(32 to 35)), + dib => std_logic_vector(bdi0(36 to 67)), + dipb => std_logic_vector(bdi0(68 to 71)), + doa => bdo0(00 to 31), + dopa => bdo0(32 to 35), + dob => bdo0(36 to 67), + dopb => bdo0(68 to 71), + ena => '1', + enb => '1', + wea => wea0, + web => web0 + ); + +bram0b : ramb16_s36_s36 +-- pragma translate_off +generic map( +-- all, none, warning_only, generate_x_only + sim_collision_check => "none") +-- pragma translate_on +port map( + clka => clk2x, + clkb => clk2x, + ssra => sreset, + ssrb => sreset, + addra => std_logic_vector(addra), + addrb => std_logic_vector(addrb), + dia => std_logic_vector(bdi1(00 to 31)), + dipa => std_logic_vector(bdi1(32 to 35)), + dib => std_logic_vector(bdi1(36 to 67)), + dipb => std_logic_vector(bdi1(68 to 71)), + doa => bdo1(00 to 31), + dopa => bdo1(32 to 35), + dob => bdo1(36 to 67), + dopb => bdo1(68 to 71), + ena => '1', + enb => '1', + wea => wea1, + web => web1 + ); + +bram0c : ramb16_s36_s36 +-- pragma translate_off +generic map( +-- all, none, warning_only, generate_x_only + sim_collision_check => "none") +-- pragma translate_on +port map( + clka => clk2x, + clkb => clk2x, + ssra => sreset, + ssrb => sreset, + addra => std_logic_vector(addra), + addrb => std_logic_vector(addrb), + dia => std_logic_vector(bdi2(00 to 31)), + dipa => std_logic_vector(bdi2(32 to 35)), + dib => std_logic_vector(bdi2(36 to 67)), + dipb => std_logic_vector(bdi2(68 to 71)), + doa => bdo2(00 to 31), + dopa => bdo2(32 to 35), + dob => bdo2(36 to 67), + dopb => bdo2(68 to 71), + ena => '1', + enb => '1', + wea => wea2, + web => web2 + ); + + +bram0d : ramb16_s36_s36 +-- pragma translate_off +generic map( +-- all, none, warning_only, generate_x_only + sim_collision_check => "none") +-- pragma translate_on +port map( + clka => clk2x, + clkb => clk2x, + ssra => sreset, + ssrb => sreset, + addra => std_logic_vector(addra), + addrb => std_logic_vector(addrb), + dia => std_logic_vector(bdi3(00 to 31)), + dipa => std_logic_vector(bdi3(32 to 35)), + dib => std_logic_vector(bdi3(36 to 67)), + dipb => std_logic_vector(bdi3(68 to 71)), + doa => bdo3(00 to 31), + dopa => bdo3(32 to 35), + dob => bdo3(36 to 67), + dopb => bdo3(68 to 71), + ena => '1', + enb => '1', + wea => wea3, + web => web3 + ); + + +abst_scan_out <= abst_scan_in; +time_scan_out <= time_scan_in; +repr_scan_out <= repr_scan_in; + +bo_pc_failout <= "00"; +bo_pc_diagloop <= "00"; + +unused <= or_reduce( sg_0 & abst_sl_thold_0 & ary_nsl_thold_0 & time_sl_thold_0 & repr_sl_thold_0 + & ary0_clkoff_dc_b & ary0_d_mode_dc & ary0_mpw1_dc_b & ary0_mpw2_dc_b + & ary0_delay_lclkr_dc & ccflush_dc & scan_dis_dc_b & scan_diag_dc + & ary1_clkoff_dc_b & ary1_d_mode_dc & ary1_mpw1_dc_b & ary1_mpw2_dc_b + & ary1_delay_lclkr_dc & abist_di + & abist_bw_odd & abist_bw_even & abist_wr_adr & abist_rd0_adr + & wr_abst_act & rd0_abst_act + & tc_lbist_ary_wrt_thru_dc & abist_ena_1 & abist_g8t_rd0_comp_ena + & abist_raw_dc_b & obs0_abist_cmp & rd0_act + & std_ulogic_vector( bdo0(36 to 65) ) & std_ulogic_vector( bdo1(36 to 65) ) + & std_ulogic_vector( bdo2(36 to 65) ) & std_ulogic_vector( bdo3(36 to 65) ) + & lcb_bolt_sl_thold_0 & pc_bo_enable_2 & pc_bo_reset + & pc_bo_unload & pc_bo_repair & pc_bo_shdata & pc_bo_select + & tri_lcb_mpw1_dc_b & tri_lcb_mpw2_dc_b & tri_lcb_delay_lclkr_dc + & tri_lcb_clkoff_dc_b & tri_lcb_act_dis_dc ); + +end generate; + +end architecture tri_64x42_4w_1r1w; diff --git a/rel/src/vhdl/tri/tri_64x72_1r1w.vhdl b/rel/src/vhdl/tri/tri_64x72_1r1w.vhdl new file mode 100644 index 0000000..43fa2f2 --- /dev/null +++ b/rel/src/vhdl/tri/tri_64x72_1r1w.vhdl @@ -0,0 +1,291 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee,ibm,support,tri; +use ieee.std_logic_1164.all; +use ibm.std_ulogic_function_support.all; +use support.power_logic_pkg.all; +use tri.tri_latches_pkg.all; +-- pragma translate_off +-- pragma translate_on + +entity tri_64x72_1r1w is +generic( + expand_type : integer := 1; + regsize : integer := 64); +port ( + -- Power + vdd : INOUT power_logic; + vcs : INOUT power_logic; + gnd : INOUT power_logic; + + -- Clock Pervasive + nclk : in clk_logic; + sg_0 : in std_ulogic; + abst_sl_thold_0 : in std_ulogic; + ary_nsl_thold_0 : in std_ulogic; + time_sl_thold_0 : in std_ulogic; + repr_sl_thold_0 : in std_ulogic; + + -- Reads + rd0_act : in std_ulogic; + rd0_adr : in std_ulogic_vector(0 to 5); + do0 : out std_ulogic_vector(64-regsize to 72-(64/regsize)); + + -- Writes + wr_act : in std_ulogic; + wr_adr : in std_ulogic_vector(0 to 5); + di : in std_ulogic_vector(64-regsize to 72-(64/regsize)); + + -- Scan + abst_scan_in : in std_ulogic; + abst_scan_out : out std_ulogic; + time_scan_in : in std_ulogic; + time_scan_out : out std_ulogic; + repr_scan_in : in std_ulogic; + repr_scan_out : out std_ulogic; + + -- Misc Pervasive + scan_dis_dc_b : in std_ulogic; + scan_diag_dc : in std_ulogic; + ccflush_dc : in std_ulogic; + clkoff_dc_b : in std_ulogic; + d_mode_dc : in std_ulogic; + mpw1_dc_b : in std_ulogic_vector(0 to 4); + mpw2_dc_b : in std_ulogic; + delay_lclkr_dc : in std_ulogic_vector(0 to 4); + + -- BOLT-ON + lcb_bolt_sl_thold_0 : in std_ulogic; + pc_bo_enable_2 : in std_ulogic; -- general bolt-on enable + pc_bo_reset : in std_ulogic; -- reset + pc_bo_unload : in std_ulogic; -- unload sticky bits + pc_bo_repair : in std_ulogic; -- execute sticky bit decode + pc_bo_shdata : in std_ulogic; -- shift data for timing write and diag loop + pc_bo_select : in std_ulogic; -- select for mask and hier writes + bo_pc_failout : out std_ulogic; -- fail/no-fix reg + bo_pc_diagloop : out std_ulogic; + tri_lcb_mpw1_dc_b : in std_ulogic; + tri_lcb_mpw2_dc_b : in std_ulogic; + tri_lcb_delay_lclkr_dc : in std_ulogic; + tri_lcb_clkoff_dc_b : in std_ulogic; + tri_lcb_act_dis_dc : in std_ulogic; + + -- ABIST + abist_di : in std_ulogic_vector(0 to 3); + abist_bw_odd : in std_ulogic; + abist_bw_even : in std_ulogic; + abist_wr_adr : in std_ulogic_vector(0 to 5); + wr_abst_act : in std_ulogic; + abist_rd0_adr : in std_ulogic_vector(0 to 5); + rd0_abst_act : in std_ulogic; + tc_lbist_ary_wrt_thru_dc : in std_ulogic; + abist_ena_1 : in std_ulogic; + abist_g8t_rd0_comp_ena : in std_ulogic; + abist_raw_dc_b : in std_ulogic; + obs0_abist_cmp : in std_ulogic_vector(0 to 3) + ); + +-- synopsys translate_off +-- synopsys translate_on + + +end entity tri_64x72_1r1w; +architecture tri_64x72_1r1w of tri_64x72_1r1w is + +begin + +a : if expand_type = 1 generate + +component RAMB16_S36_S36 +-- pragma translate_off +generic( + SIM_COLLISION_CHECK : string := "none"); -- all, none, warning_only, GENERATE_X_ONLY +-- pragma translate_on +port( + DOA : out std_logic_vector(31 downto 0); + DOB : out std_logic_vector(31 downto 0); + DOPA : out std_logic_vector(3 downto 0); + DOPB : out std_logic_vector(3 downto 0); + ADDRA : in std_logic_vector(8 downto 0); + ADDRB : in std_logic_vector(8 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(31 downto 0); + DIB : in std_logic_vector(31 downto 0); + DIPA : in std_logic_vector(3 downto 0); + DIPB : in std_logic_vector(3 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic); +end component; + +-- pragma translate_off +-- pragma translate_on + +signal clk, clk2x : std_ulogic; +signal addra, addrb : std_ulogic_vector(0 to 8); +signal wea, web : std_ulogic; +signal bdo : std_logic_vector(0 to 71); +signal bdi : std_ulogic_vector(0 to 71); +signal sreset : std_ulogic; +signal tidn : std_ulogic_vector(0 to 71); +-- Latches +signal reset_q : std_ulogic; +signal gate_fq, gate_d : std_ulogic; +signal bdo_d, bdo_fq : std_ulogic_vector(64-regsize to 72-(64/regsize)); + +signal toggle_d : std_ulogic; +signal toggle_q : std_ulogic; +signal toggle2x_d : std_ulogic; +signal toggle2x_q : std_ulogic; + +signal unused : std_ulogic; +-- synopsys translate_off +-- synopsys translate_on + +begin + +tidn <= (others=>'0'); +clk <= nclk.clk; +clk2x <= nclk.clk2x; +sreset<= nclk.sreset; + +rlatch: process (clk) begin + if(rising_edge(clk)) then + reset_q <= sreset after 10 ps; + end if; +end process; + + +tlatch: process (nclk.clk,reset_q) +begin + if(rising_edge(nclk.clk)) then + if (reset_q = '1') then + toggle_q <= '1'; + else + toggle_q <= toggle_d; + end if; + end if; +end process; + +flatch: process (nclk.clk2x) +begin + if(rising_edge(nclk.clk2x)) then + toggle2x_q <= toggle2x_d; + gate_fq <= gate_d; + bdo_fq <= bdo_d; + end if; +end process; + +toggle_d <= not toggle_q; +toggle2x_d <= toggle_q; + +gate_d <= not(toggle_q xor toggle2x_q); + + + + + + +in32 : if regsize = 32 generate + bdi <= tidn(0 to 31) & di(32 to 63) & di(64 to 70) & tidn(71); +end generate; +in64 : if regsize = 64 generate + bdi <= di(0 to 71); +end generate; + +bdo_d <= std_ulogic_vector(bdo(64-regsize to 72-(64/regsize))); +do0 <= bdo_fq; + +wea <= (wr_act and gate_fq) after 10 ps; +web <= (wr_act and gate_fq) after 10 ps; + +with gate_fq select + addra <= ("00" & wr_adr & '0') after 10 ps when '1', + ("00" & rd0_adr & '0') after 10 ps when others; + +with gate_fq select + addrb <= ("00" & wr_adr & '1') after 10 ps when '1', + ("00" & rd0_adr & '1') after 10 ps when others; + +bram0a : ramb16_s36_s36 +-- pragma translate_off +generic map( +-- all, none, warning_only, generate_x_only + sim_collision_check => "none") +-- pragma translate_on +port map( + clka => clk2x, + clkb => clk2x, + ssra => sreset, + ssrb => sreset, + addra => std_logic_vector(addra), + addrb => std_logic_vector(addrb), + dia => std_logic_vector(bdi(00 to 31)), + dib => std_logic_vector(bdi(32 to 63)), + dipa => std_logic_vector(bdi(64 to 67)), + dipb => std_logic_vector(bdi(68 to 71)), + doa => bdo(00 to 31), + dob => bdo(32 to 63), + dopa => bdo(64 to 67), + dopb => bdo(68 to 71), + ena => '1', + enb => '1', + wea => wea, + web => web + ); + + +abst_scan_out <= abst_scan_in; +time_scan_out <= time_scan_in; +repr_scan_out <= repr_scan_in; + +bo_pc_failout <= '0'; +bo_pc_diagloop <= '0'; + +unused <= or_reduce( sg_0 & abst_sl_thold_0 & ary_nsl_thold_0 & time_sl_thold_0 & repr_sl_thold_0 + & scan_dis_dc_b & scan_diag_dc & ccflush_dc + & clkoff_dc_b & d_mode_dc & mpw1_dc_b & mpw2_dc_b + & delay_lclkr_dc & abist_di + & abist_bw_odd & abist_bw_even & abist_wr_adr & abist_rd0_adr + & wr_abst_act & rd0_abst_act + & tc_lbist_ary_wrt_thru_dc & abist_ena_1 & abist_g8t_rd0_comp_ena + & abist_raw_dc_b & obs0_abist_cmp & rd0_act & tidn + & lcb_bolt_sl_thold_0 & pc_bo_enable_2 & pc_bo_reset + & pc_bo_unload & pc_bo_repair & pc_bo_shdata & pc_bo_select + & tri_lcb_mpw1_dc_b & tri_lcb_mpw2_dc_b & tri_lcb_delay_lclkr_dc + & tri_lcb_clkoff_dc_b & tri_lcb_act_dis_dc ); + + +end generate; + +end architecture tri_64x72_1r1w; diff --git a/rel/src/vhdl/tri/tri_aoi22_nlats.vhdl b/rel/src/vhdl/tri/tri_aoi22_nlats.vhdl new file mode 100644 index 0000000..911f5c7 --- /dev/null +++ b/rel/src/vhdl/tri/tri_aoi22_nlats.vhdl @@ -0,0 +1,126 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- *!**************************************************************** +-- *! FILENAME : tri_aoi22_nlats.vhdl +-- *! DESCRIPTION : n-bit scannable m/s latch, for bit stacking, with aoi22 gate in front +-- *! +-- *!**************************************************************** + +library ieee; use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library support; + use support.power_logic_pkg.all; +library tri; use tri.tri_latches_pkg.all; +-- pragma translate_off +-- pragma translate_on + +entity tri_aoi22_nlats is + + generic ( + offset : natural range 0 to 65535 := 0; + width : positive range 1 to 65536 := 1 ; + init : std_ulogic_vector := "0" ; + synthclonedlatch : string := "" ; + btr : string := "NLL0001_X2_A12TH" ; + needs_sreset : integer := 1 ; -- for inferred latches + expand_type : integer := 1 ); -- 1 = non-ibm, 2 = ibm (MPG) + port ( + vd : inout power_logic; + gd : inout power_logic; + LCLK : in clk_logic; + D1CLK : in std_ulogic; + D2CLK : in std_ulogic; + SCANIN : in std_ulogic_vector(offset to offset+width-1); + SCANOUT : out std_ulogic_vector(offset to offset+width-1); + A1 : in std_ulogic_vector(offset to offset+width-1); + A2 : in std_ulogic_vector(offset to offset+width-1); + B1 : in std_ulogic_vector(offset to offset+width-1); + B2 : in std_ulogic_vector(offset to offset+width-1); + QB : out std_ulogic_vector(offset to offset+width-1) + ); + + -- synopsys translate_off + + -- synopsys translate_on + +end entity tri_aoi22_nlats; + +architecture tri_aoi22_nlats of tri_aoi22_nlats is + +begin + + a: if expand_type = 1 generate + constant init_v : std_ulogic_vector(0 to (init'length + width-1)):=init & (0 to width-1=>'0'); + constant zeros : std_ulogic_vector(0 to width-1) := (0 to width-1 => '0'); + + signal sreset : std_ulogic; + signal int_din : std_ulogic_vector(0 to width-1); + signal int_dout : std_ulogic_vector(0 to width-1) := init_v(0 to width-1); + signal vact, vact_b : std_ulogic_vector(0 to width-1); + signal vsreset, vsreset_b : std_ulogic_vector(0 to width-1); + signal vthold, vthold_b : std_ulogic_vector(0 to width-1); + signal din : std_ulogic_vector(0 to width-1); + signal unused : std_ulogic_vector(0 to width-1); + -- synopsys translate_off + -- synopsys translate_on + begin + rst: if needs_sreset = 1 generate + sreset <= LCLK.sreset; + end generate rst; + no_rst: if needs_sreset /=1 generate + sreset <= '0'; + end generate no_rst; + + vsreset <= (0 to width-1 => sreset); + vsreset_b <= (0 to width-1 => not sreset); + din <= (A1 and A2) or (B1 and B2) ; -- Output is inverted, so just AND-OR here + int_din <= (vsreset_b and din) or + (vsreset and init_v(0 to width-1)); + + vact <= (0 to width-1 => D1CLK); + vact_b <= (0 to width-1 => not D1CLK); + + vthold_b <= (0 to width-1 => D2CLK); + vthold <= (0 to width-1 => not D2CLK); + + l: process (LCLK, vact, int_din, vact_b, int_dout, vsreset, vsreset_b, vthold_b, vthold) + begin + if rising_edge(LCLK.clk) then + int_dout <= (((vact and vthold_b) or vsreset) and int_din) or + (((vact_b or vthold) and vsreset_b) and int_dout); + end if; + end process l; + QB <= not int_dout; + SCANOUT <= zeros; + + unused <= SCANIN; + end generate a; + +end tri_aoi22_nlats; diff --git a/rel/src/vhdl/tri/tri_aoi22_nlats_wlcb.vhdl b/rel/src/vhdl/tri/tri_aoi22_nlats_wlcb.vhdl new file mode 100644 index 0000000..61c5de0 --- /dev/null +++ b/rel/src/vhdl/tri/tri_aoi22_nlats_wlcb.vhdl @@ -0,0 +1,138 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- *!**************************************************************** +-- *! FILENAME : tri_aoi22_nlats_wlcb.vhdl +-- *! DESCRIPTION : Multi-bit aoi22-latch, LCB included +-- *! +-- *!**************************************************************** + +library ieee; use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library support; + use support.power_logic_pkg.all; +library tri; use tri.tri_latches_pkg.all; +-- pragma translate_off +-- pragma translate_on + +entity tri_aoi22_nlats_wlcb is + + generic ( + width : integer := 4; + offset : integer range 0 to 65535 := 0 ; --starting bit + init : integer := 0; -- will be converted to the least signficant + -- 31 bits of init_v + ibuf : boolean := false; --inverted latch IOs, if set to true. + dualscan : string := ""; -- if "S", marks data ports as scan for Moebius + needs_sreset: integer := 1 ; -- for inferred latches + expand_type : integer := 1 ; -- 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) + synthclonedlatch : string := "" ; + btr : string := "NLL0001_X2_A12TH" ); + + port ( + vd : inout power_logic; + gd : inout power_logic; + nclk : in clk_logic; + act : in std_ulogic := '1'; -- 1: functional, 0: no clock + forcee : in std_ulogic := '0'; -- 1: force LCB active + thold_b : in std_ulogic := '1'; -- 1: functional, 0: no clock + d_mode : in std_ulogic := '0'; -- 1: disable pulse mode, 0: pulse mode + sg : in std_ulogic := '0'; -- 0: functional, 1: scan + delay_lclkr : in std_ulogic := '0'; -- 0: functional + mpw1_b : in std_ulogic := '1'; -- pulse width control bit + mpw2_b : in std_ulogic := '1'; -- pulse width control bit + scin : in std_ulogic_vector(offset to offset+width-1); -- scan in + scout : out std_ulogic_vector(offset to offset+width-1); + A1 : in std_ulogic_vector(offset to offset+width-1); + A2 : in std_ulogic_vector(offset to offset+width-1); + B1 : in std_ulogic_vector(offset to offset+width-1); + B2 : in std_ulogic_vector(offset to offset+width-1); + QB : out std_ulogic_vector(offset to offset+width-1)); + + -- synopsys translate_off + + -- synopsys translate_on + +end entity tri_aoi22_nlats_wlcb; + +architecture tri_aoi22_nlats_wlcb of tri_aoi22_nlats_wlcb is + + constant init_v : std_ulogic_vector(0 to width-1) := std_ulogic_vector( to_unsigned( init, width ) ); + constant zeros : std_ulogic_vector(0 to width-1) := (0 to width-1 => '0'); + +begin + + a: if expand_type = 1 generate + signal sreset : std_ulogic; + signal int_din, din : std_ulogic_vector(0 to width-1); + signal int_dout : std_ulogic_vector(0 to width-1) := init_v; + signal vact, vact_b : std_ulogic_vector(0 to width-1); + signal vsreset, vsreset_b : std_ulogic_vector(0 to width-1); + signal vthold, vthold_b : std_ulogic_vector(0 to width-1); + signal unused : std_ulogic_vector(0 to width); + -- synopsys translate_off + -- synopsys translate_on + begin + rst: if needs_sreset = 1 generate + sreset <= nclk.sreset; + end generate rst; + no_rst: if needs_sreset /=1 generate + sreset <= '0'; + end generate no_rst; + + vsreset <= (0 to width-1 => sreset); + vsreset_b <= (0 to width-1 => not sreset); + + din <= (A1 and A2) or (B1 and B2) ; -- Output is inverted, so just AND-OR here + int_din <= (vsreset_b and din) or + (vsreset and init_v); + + vact <= (0 to width-1 => (act or forcee)); + vact_b <= (0 to width-1 => not (act or forcee)); + + vthold_b <= (0 to width-1 => thold_b); + vthold <= (0 to width-1 => not thold_b); + + l: process (nclk, vact, int_din, vact_b, int_dout, vsreset, vsreset_b, vthold_b, vthold) + begin + if rising_edge(nclk.clk) then + int_dout <= (((vact and vthold_b) or vsreset) and int_din) or + (((vact_b or vthold) and vsreset_b) and int_dout); + end if; + end process l; + + QB <= not int_dout; + + scout <= zeros; + + unused(0) <= d_mode or sg or delay_lclkr or mpw1_b or mpw2_b; + unused(1 to width) <= scin; + end generate a; + +end tri_aoi22_nlats_wlcb; diff --git a/rel/src/vhdl/tri/tri_bht.vhdl b/rel/src/vhdl/tri/tri_bht.vhdl new file mode 100644 index 0000000..4cbd121 --- /dev/null +++ b/rel/src/vhdl/tri/tri_bht.vhdl @@ -0,0 +1,524 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + + +library ieee; +use ieee.std_logic_1164.all; + +library ibm; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; + +library support; +use support.power_logic_pkg.all; + +library tri; +use tri.tri_latches_pkg.all; + + +entity tri_bht is +generic(expand_type : integer := 1 ); -- 0 = ibm umbra, 1 = xilinx, 2 = ibm mpg +port( + -- power pins + gnd : inout power_logic; + vdd : inout power_logic; + vcs : inout power_logic; + + -- clock and clockcontrol ports + nclk : in clk_logic; + pc_iu_func_sl_thold_2 : in std_ulogic; + pc_iu_sg_2 : in std_ulogic; + pc_iu_time_sl_thold_2 : in std_ulogic; + pc_iu_abst_sl_thold_2 : in std_ulogic; + pc_iu_ary_nsl_thold_2 : in std_ulogic; + pc_iu_repr_sl_thold_2 : in std_ulogic; + pc_iu_bolt_sl_thold_2 : in std_ulogic; + tc_ac_ccflush_dc : in std_ulogic; + tc_ac_scan_dis_dc_b : in std_ulogic; + clkoff_b : in std_ulogic; + scan_diag_dc : in std_ulogic; + act_dis : in std_ulogic; + d_mode : in std_ulogic; + delay_lclkr : in std_ulogic; + mpw1_b : in std_ulogic; + mpw2_b : in std_ulogic; + g8t_clkoff_b : in std_ulogic; + g8t_d_mode : in std_ulogic; + g8t_delay_lclkr : in std_ulogic_vector(0 to 4); + g8t_mpw1_b : in std_ulogic_vector(0 to 4); + g8t_mpw2_b : in std_ulogic; + func_scan_in : in std_ulogic; + time_scan_in : in std_ulogic; + abst_scan_in : in std_ulogic; + repr_scan_in : in std_ulogic; + func_scan_out : out std_ulogic; + time_scan_out : out std_ulogic; + abst_scan_out : out std_ulogic; + repr_scan_out : out std_ulogic; + + pc_iu_abist_di_0 : in std_ulogic_vector(0 to 3); + pc_iu_abist_g8t_bw_1 : in std_ulogic; + pc_iu_abist_g8t_bw_0 : in std_ulogic; + pc_iu_abist_waddr_0 : in std_ulogic_vector(3 to 9); + pc_iu_abist_g8t_wenb : in std_ulogic; + pc_iu_abist_raddr_0 : in std_ulogic_vector(3 to 9); + pc_iu_abist_g8t1p_renb_0 : in std_ulogic; + an_ac_lbist_ary_wrt_thru_dc: in std_ulogic; + pc_iu_abist_ena_dc : in std_ulogic; + pc_iu_abist_wl128_comp_ena : in std_ulogic; + pc_iu_abist_raw_dc_b : in std_ulogic; + pc_iu_abist_g8t_dcomp : in std_ulogic_vector(0 to 3); + + -- BOLT-ON + pc_iu_bo_enable_2 : in std_ulogic; -- general bolt-on enable + pc_iu_bo_reset : in std_ulogic; -- reset + pc_iu_bo_unload : in std_ulogic; -- unload sticky bits + pc_iu_bo_repair : in std_ulogic; -- execute sticky bit decode + pc_iu_bo_shdata : in std_ulogic; -- shift data for timing write and diag loop + pc_iu_bo_select : in std_ulogic; -- select for mask and hier writes + iu_pc_bo_fail : out std_ulogic; -- fail/no-fix reg + iu_pc_bo_diagout : out std_ulogic; + + -- ports + r_act : in std_ulogic; + w_act : in std_ulogic_vector(0 to 3); + r_addr : in std_ulogic_vector(0 to 7); + w_addr : in std_ulogic_vector(0 to 7); + data_in : in std_ulogic_vector(0 to 1); + data_out0 : out std_ulogic_vector(0 to 1); + data_out1 : out std_ulogic_vector(0 to 1); + data_out2 : out std_ulogic_vector(0 to 1); + data_out3 : out std_ulogic_vector(0 to 1) + +); + +-- pragma translate_off + + +-- pragma translate_on + +end tri_bht; +architecture tri_bht of tri_bht is + +---------------------------- +-- constants +---------------------------- + +constant data_in_offset : natural := 0; +constant w_act_offset : natural := data_in_offset + 2; +constant r_act_offset : natural := w_act_offset + 4; +constant w_addr_offset : natural := r_act_offset + 1; +constant r_addr_offset : natural := w_addr_offset + 8; +constant data_out_offset : natural := r_addr_offset + 8; +constant array_offset : natural := data_out_offset + 8; +constant scan_right : natural := array_offset + 1 - 1; + +constant INIT_MASK : std_ulogic_vector(0 to 1) := "10"; + +---------------------------- +-- signals +---------------------------- + +signal pc_iu_func_sl_thold_1 : std_ulogic; +signal pc_iu_func_sl_thold_0 : std_ulogic; +signal pc_iu_func_sl_thold_0_b : std_ulogic; +signal pc_iu_time_sl_thold_1 : std_ulogic; +signal pc_iu_time_sl_thold_0 : std_ulogic; +signal pc_iu_ary_nsl_thold_1 : std_ulogic; +signal pc_iu_ary_nsl_thold_0 : std_ulogic; +signal pc_iu_abst_sl_thold_1 : std_ulogic; +signal pc_iu_abst_sl_thold_0 : std_ulogic; +signal pc_iu_repr_sl_thold_1 : std_ulogic; +signal pc_iu_repr_sl_thold_0 : std_ulogic; +signal pc_iu_bolt_sl_thold_1 : std_ulogic; +signal pc_iu_bolt_sl_thold_0 : std_ulogic; +signal pc_iu_sg_1 : std_ulogic; +signal pc_iu_sg_0 : std_ulogic; +signal forcee : std_ulogic; + +signal siv : std_ulogic_vector(0 to scan_right); +signal sov : std_ulogic_vector(0 to scan_right); + +signal tiup : std_ulogic; + +signal data_out_d : std_ulogic_vector(0 to 7); +signal data_out_q : std_ulogic_vector(0 to 7); + +signal ary_w_en : std_ulogic; +signal ary_w_addr : std_ulogic_vector(0 to 6); +signal ary_w_sel : std_ulogic_vector(0 to 15); +signal ary_w_data : std_ulogic_vector(0 to 15); + +signal ary_r_en : std_ulogic; +signal ary_r_addr : std_ulogic_vector(0 to 6); +signal ary_r_data : std_ulogic_vector(0 to 15); + +signal data_out : std_ulogic_vector(0 to 7); +signal write_thru : std_ulogic_vector(0 to 3); + +signal data_in_d : std_ulogic_vector(0 to 1); +signal data_in_q : std_ulogic_vector(0 to 1); +signal w_act_d : std_ulogic_vector(0 to 3); +signal w_act_q : std_ulogic_vector(0 to 3); +signal r_act_d : std_ulogic; +signal r_act_q : std_ulogic; +signal w_addr_d : std_ulogic_vector(0 to 7); +signal w_addr_q : std_ulogic_vector(0 to 7); +signal r_addr_d : std_ulogic_vector(0 to 7); +signal r_addr_q : std_ulogic_vector(0 to 7); + + +begin + + +tiup <= '1'; + + +data_out0(0 to 1) <= data_out_q(0 to 1); +data_out1(0 to 1) <= data_out_q(2 to 3); +data_out2(0 to 1) <= data_out_q(4 to 5); +data_out3(0 to 1) <= data_out_q(6 to 7); + + +ary_w_en <= or_reduce(w_act(0 to 3)) and not ((w_addr(1 to 7) = r_addr(1 to 7)) and r_act = '1'); + +ary_w_addr(0 to 6) <= w_addr(1 to 7); + +ary_w_sel(0) <= w_act(0) and w_addr(0) = '0'; +ary_w_sel(1) <= w_act(0) and w_addr(0) = '0'; +ary_w_sel(2) <= w_act(1) and w_addr(0) = '0'; +ary_w_sel(3) <= w_act(1) and w_addr(0) = '0'; +ary_w_sel(4) <= w_act(2) and w_addr(0) = '0'; +ary_w_sel(5) <= w_act(2) and w_addr(0) = '0'; +ary_w_sel(6) <= w_act(3) and w_addr(0) = '0'; +ary_w_sel(7) <= w_act(3) and w_addr(0) = '0'; +ary_w_sel(8) <= w_act(0) and w_addr(0) = '1'; +ary_w_sel(9) <= w_act(0) and w_addr(0) = '1'; +ary_w_sel(10) <= w_act(1) and w_addr(0) = '1'; +ary_w_sel(11) <= w_act(1) and w_addr(0) = '1'; +ary_w_sel(12) <= w_act(2) and w_addr(0) = '1'; +ary_w_sel(13) <= w_act(2) and w_addr(0) = '1'; +ary_w_sel(14) <= w_act(3) and w_addr(0) = '1'; +ary_w_sel(15) <= w_act(3) and w_addr(0) = '1'; + +ary_w_data(0 to 15) <= (data_in(0 to 1) xor INIT_MASK(0 to 1)) & + (data_in(0 to 1) xor INIT_MASK(0 to 1)) & + (data_in(0 to 1) xor INIT_MASK(0 to 1)) & + (data_in(0 to 1) xor INIT_MASK(0 to 1)) & + (data_in(0 to 1) xor INIT_MASK(0 to 1)) & + (data_in(0 to 1) xor INIT_MASK(0 to 1)) & + (data_in(0 to 1) xor INIT_MASK(0 to 1)) & + (data_in(0 to 1) xor INIT_MASK(0 to 1)) ; + +ary_r_en <= r_act; + +ary_r_addr(0 to 6) <= r_addr(1 to 7); + +data_out(0 to 7) <= gate(ary_r_data(0 to 7) xor (INIT_MASK(0 to 1) & INIT_MASK(0 to 1) & INIT_MASK(0 to 1) & INIT_MASK(0 to 1)), r_addr_q(0) = '0') or + gate(ary_r_data(8 to 15) xor (INIT_MASK(0 to 1) & INIT_MASK(0 to 1) & INIT_MASK(0 to 1) & INIT_MASK(0 to 1)), r_addr_q(0) = '1') ; + +--write through support + +data_in_d(0 to 1) <= data_in(0 to 1); +w_act_d(0 to 3) <= w_act(0 to 3); +r_act_d <= r_act; +w_addr_d(0 to 7) <= w_addr(0 to 7); +r_addr_d(0 to 7) <= r_addr(0 to 7); + +write_thru(0 to 3) <= w_act_q(0 to 3) when (w_addr_q(0 to 7) = r_addr_q(0 to 7)) and r_act_q = '1' else "0000"; + +data_out_d(0 to 1) <= data_in_q(0 to 1) when write_thru(0) = '1' else + data_out(0 to 1); +data_out_d(2 to 3) <= data_in_q(0 to 1) when write_thru(1) = '1' else + data_out(2 to 3); +data_out_d(4 to 5) <= data_in_q(0 to 1) when write_thru(2) = '1' else + data_out(4 to 5); +data_out_d(6 to 7) <= data_in_q(0 to 1) when write_thru(3) = '1' else + data_out(6 to 7); + +------------------------------------------------- +-- array +------------------------------------------------- + +bht0: entity tri.tri_128x16_1r1w_1 + generic map ( expand_type => expand_type ) + port map( + gnd => gnd, + vdd => vdd, + vcs => vcs, + nclk => nclk, + + rd_act => ary_r_en, + wr_act => ary_w_en, + + lcb_d_mode_dc => g8t_d_mode, + lcb_clkoff_dc_b => g8t_clkoff_b, + lcb_mpw1_dc_b => g8t_mpw1_b, + lcb_mpw2_dc_b => g8t_mpw2_b, + lcb_delay_lclkr_dc => g8t_delay_lclkr, + ccflush_dc => tc_ac_ccflush_dc, + scan_dis_dc_b => tc_ac_scan_dis_dc_b, + scan_diag_dc => scan_diag_dc, + func_scan_in => siv(array_offset), + func_scan_out => sov(array_offset), + + lcb_sg_0 => pc_iu_sg_0, + lcb_sl_thold_0_b => pc_iu_func_sl_thold_0_b, + lcb_time_sl_thold_0 => pc_iu_time_sl_thold_0, + lcb_abst_sl_thold_0 => pc_iu_abst_sl_thold_0, + lcb_ary_nsl_thold_0 => pc_iu_ary_nsl_thold_0, + lcb_repr_sl_thold_0 => pc_iu_repr_sl_thold_0, + time_scan_in => time_scan_in, + time_scan_out => time_scan_out, + abst_scan_in => abst_scan_in, + abst_scan_out => abst_scan_out, + repr_scan_in => repr_scan_in, + repr_scan_out => repr_scan_out, + + abist_di => pc_iu_abist_di_0, + abist_bw_odd => pc_iu_abist_g8t_bw_1, + abist_bw_even => pc_iu_abist_g8t_bw_0, + abist_wr_adr => pc_iu_abist_waddr_0, + wr_abst_act => pc_iu_abist_g8t_wenb, + abist_rd0_adr => pc_iu_abist_raddr_0, + rd0_abst_act => pc_iu_abist_g8t1p_renb_0, + tc_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc, + abist_ena_1 => pc_iu_abist_ena_dc, + abist_g8t_rd0_comp_ena => pc_iu_abist_wl128_comp_ena, + abist_raw_dc_b => pc_iu_abist_raw_dc_b, + obs0_abist_cmp => pc_iu_abist_g8t_dcomp, + + lcb_bolt_sl_thold_0 => pc_iu_bolt_sl_thold_0, + pc_bo_enable_2 => pc_iu_bo_enable_2, + pc_bo_reset => pc_iu_bo_reset, + pc_bo_unload => pc_iu_bo_unload, + pc_bo_repair => pc_iu_bo_repair, + pc_bo_shdata => pc_iu_bo_shdata, + pc_bo_select => pc_iu_bo_select, + bo_pc_failout => iu_pc_bo_fail, + bo_pc_diagloop => iu_pc_bo_diagout, + + tri_lcb_mpw1_dc_b => mpw1_b, + tri_lcb_mpw2_dc_b => mpw2_b, + tri_lcb_delay_lclkr_dc => delay_lclkr, + tri_lcb_clkoff_dc_b => clkoff_b, + tri_lcb_act_dis_dc => act_dis, + + bw => ary_w_sel, + wr_adr => ary_w_addr, + rd_adr => ary_r_addr, + di => ary_w_data, + do => ary_r_data +); + + + +------------------------------------------------- +-- latches +------------------------------------------------- + +data_in_reg: tri_rlmreg_p +generic map (width => data_in_q'length, init => 0, expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(data_in_offset to data_in_offset + data_in_q'length-1), + scout => sov(data_in_offset to data_in_offset + data_in_q'length-1), + din => data_in_d, + dout => data_in_q); + +w_act_reg: tri_rlmreg_p +generic map (width => w_act_q'length, init => 0, expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(w_act_offset to w_act_offset + w_act_q'length-1), + scout => sov(w_act_offset to w_act_offset + w_act_q'length-1), + din => w_act_d, + dout => w_act_q); + +r_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(r_act_offset), + scout => sov(r_act_offset), + din => r_act_d, + dout => r_act_q); + +w_addr_reg: tri_rlmreg_p +generic map (width => w_addr_q'length, init => 0, expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(w_addr_offset to w_addr_offset + w_addr_q'length-1), + scout => sov(w_addr_offset to w_addr_offset + w_addr_q'length-1), + din => w_addr_d, + dout => w_addr_q); + +r_addr_reg: tri_rlmreg_p +generic map (width => r_addr_q'length, init => 0, expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(r_addr_offset to r_addr_offset + r_addr_q'length-1), + scout => sov(r_addr_offset to r_addr_offset + r_addr_q'length-1), + din => r_addr_d, + dout => r_addr_q); + + +data_out_reg: tri_rlmreg_p +generic map (width => data_out_q'length, init => 0, expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(data_out_offset to data_out_offset + data_out_q'length-1), + scout => sov(data_out_offset to data_out_offset + data_out_q'length-1), + din => data_out_d, + dout => data_out_q); + + +------------------------------------------------- +-- pervasive +------------------------------------------------- + +perv_2to1_reg: tri_plat + generic map (width => 7, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_iu_func_sl_thold_2, + din(1) => pc_iu_sg_2, + din(2) => pc_iu_time_sl_thold_2, + din(3) => pc_iu_abst_sl_thold_2, + din(4) => pc_iu_ary_nsl_thold_2, + din(5) => pc_iu_repr_sl_thold_2, + din(6) => pc_iu_bolt_sl_thold_2, + q(0) => pc_iu_func_sl_thold_1, + q(1) => pc_iu_sg_1, + q(2) => pc_iu_time_sl_thold_1, + q(3) => pc_iu_abst_sl_thold_1, + q(4) => pc_iu_ary_nsl_thold_1, + q(5) => pc_iu_repr_sl_thold_1, + q(6) => pc_iu_bolt_sl_thold_1 +); + +perv_1to0_reg: tri_plat + generic map (width => 7, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_iu_func_sl_thold_1, + din(1) => pc_iu_sg_1, + din(2) => pc_iu_time_sl_thold_1, + din(3) => pc_iu_abst_sl_thold_1, + din(4) => pc_iu_ary_nsl_thold_1, + din(5) => pc_iu_repr_sl_thold_1, + din(6) => pc_iu_bolt_sl_thold_1, + q(0) => pc_iu_func_sl_thold_0, + q(1) => pc_iu_sg_0, + q(2) => pc_iu_time_sl_thold_0, + q(3) => pc_iu_abst_sl_thold_0, + q(4) => pc_iu_ary_nsl_thold_0, + q(5) => pc_iu_repr_sl_thold_0, + q(6) => pc_iu_bolt_sl_thold_0 +); + +perv_lcbor: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_b, + thold => pc_iu_func_sl_thold_0, + sg => pc_iu_sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => pc_iu_func_sl_thold_0_b); + + +------------------------------------------------- +-- scan +------------------------------------------------- + +siv(0 to scan_right) <= func_scan_in & sov(0 to scan_right-1); +func_scan_out <= sov(scan_right); + + +end tri_bht; diff --git a/rel/src/vhdl/tri/tri_boltreg_p.vhdl b/rel/src/vhdl/tri/tri_boltreg_p.vhdl new file mode 100644 index 0000000..5019f32 --- /dev/null +++ b/rel/src/vhdl/tri/tri_boltreg_p.vhdl @@ -0,0 +1,193 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- *!**************************************************************** +-- *! FILENAME : tri_boltreg_p.vhdl +-- *! DESCRIPTION : Multi-bit latch, LCB included +-- *! Same as tri_rlmreg_p, but different name for lcb +-- *! for relaxed timing +-- *! +-- *!**************************************************************** + +library ieee; use ieee.std_logic_1164.all; + use ieee.numeric_std.all; +library support; + use support.power_logic_pkg.all; +library tri; use tri.tri_latches_pkg.all; + +entity tri_boltreg_p is + + generic ( + width : integer := 4; + offset : integer range 0 to 65535 := 0 ; --starting bit + init : integer := 0; -- will be converted to the least signficant + -- 31 bits of init_v + ibuf : boolean := false; --inverted latch IOs, if set to true. + dualscan : string := ""; -- if "S", marks data ports as scan for Moebius + needs_sreset: integer := 1 ; -- for inferred latches + expand_type : integer := 1 );-- 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) + + port ( + vd : inout power_logic; + gd : inout power_logic; + nclk : in clk_logic; + act : in std_ulogic := '1'; -- 1: functional, 0: no clock + forcee : in std_ulogic := '0'; -- 1: force LCB active + thold_b : in std_ulogic := '1'; -- 1: functional, 0: no clock + d_mode : in std_ulogic := '0'; -- 1: disable pulse mode, 0: pulse mode + sg : in std_ulogic := '0'; -- 0: functional, 1: scan + delay_lclkr : in std_ulogic := '0'; -- 0: functional + mpw1_b : in std_ulogic := '1'; -- pulse width control bit + mpw2_b : in std_ulogic := '1'; -- pulse width control bit + scin : in std_ulogic_vector(offset to offset+width-1); -- scan in + din : in std_ulogic_vector(offset to offset+width-1); -- data in + scout : out std_ulogic_vector(offset to offset+width-1); + dout : out std_ulogic_vector(offset to offset+width-1) ); + +end entity tri_boltreg_p; + +architecture tri_boltreg_p of tri_boltreg_p is + + constant init_v : std_ulogic_vector(0 to width-1) := std_ulogic_vector( to_unsigned( init, width ) ); + constant zeros : std_ulogic_vector(0 to width-1) := (0 to width-1 => '0'); + +begin -- tri_boltreg_p + + -- synopsys translate_off + um: if expand_type = 0 generate + component c_rlmreg_p + generic ( width : positive := 4 ; --bit width value + init : std_ulogic_vector := "0"; --latch initialization + dualscan : string := "" -- if "S", marks data ports as scan for Moebius + ); + port ( + nclk : in std_ulogic; -- chip global clock signal + act : in std_ulogic; -- 1: functional, 0: no clock + thold_b : in std_ulogic; -- 1: functional, 0: stop the clock. + sg : in std_ulogic; -- 0: functional, 1: scan + scin : in std_ulogic_vector(0 to width-1); -- scan in + din : in std_ulogic_vector(0 to width-1); -- data in + dout : out std_ulogic_vector(0 to width-1); -- data out + scout : out std_ulogic_vector(0 to width-1) -- scan out + ); + end component; + signal scanin_inv : std_ulogic_vector(0 to width-1); + signal scanout_inv : std_ulogic_vector(0 to width-1); + signal act_or_force : std_ulogic; + signal din_buf : std_ulogic_vector(0 to width-1); + signal dout_buf : std_ulogic_vector(0 to width-1); + begin + act_or_force <= act or forcee; + + cib: --insert inverters at latch IO if ibuf=true + if ibuf = true generate + din_buf <= not din; + dout <= not dout_buf; + end generate cib; + cnib: -- no inverters at latch IO if ibuf=false (default) + if ibuf = false generate + din_buf <= din; + dout <= dout_buf; + end generate cnib; + + l:c_rlmreg_p + generic map (width => width, init => init_v, dualscan => dualscan) + port map ( + nclk => nclk.clk, + act => act_or_force, + thold_b => thold_b, + sg => sg, + scin => scanin_inv, + din => din_buf, + scout => scanout_inv, + dout => dout_buf); + + scanin_inv <= scin xor init_v; + scout <= scanout_inv xor init_v; + end generate um; + -- synopsys translate_on + + a: if expand_type = 1 generate + signal sreset : std_ulogic; + signal int_din : std_ulogic_vector(0 to width-1); + signal int_dout : std_ulogic_vector(0 to width-1) := init_v; + signal vact, vact_b : std_ulogic_vector(0 to width-1); + signal vsreset, vsreset_b : std_ulogic_vector(0 to width-1); + signal vthold, vthold_b : std_ulogic_vector(0 to width-1); + signal unused : std_ulogic_vector(0 to width); + -- synopsys translate_off + -- synopsys translate_on + begin + rst: if needs_sreset = 1 generate + sreset <= nclk.sreset; + end generate rst; + no_rst: if needs_sreset /=1 generate + sreset <= '0'; + end generate no_rst; + + vsreset <= (0 to width-1 => sreset); + vsreset_b <= (0 to width-1 => not sreset); + + cib: if ibuf = true generate + int_din <= (vsreset_b and not din) or + (vsreset and init_v); + end generate cib; + cnib: if ibuf = false generate + int_din <= (vsreset_b and din) or + (vsreset and init_v); + end generate cnib; + + vact <= (0 to width-1 => (act or forcee)); + vact_b <= (0 to width-1 => not (act or forcee)); + + vthold_b <= (0 to width-1 => thold_b); + vthold <= (0 to width-1 => not thold_b); + + l: process (nclk, vact, int_din, vact_b, int_dout, vsreset, vsreset_b, vthold_b, vthold) + begin + if rising_edge(nclk.clk) then + int_dout <= (((vact and vthold_b) or vsreset) and int_din) or + (((vact_b or vthold) and vsreset_b) and int_dout); + end if; + end process l; + + cob: if ibuf = true generate + dout <= not int_dout; + end generate cob; + + cnob: if ibuf = false generate + dout <= int_dout; + end generate cnob; + + scout <= zeros; + + unused(0) <= d_mode or sg or delay_lclkr or mpw1_b or mpw2_b; + unused(1 to width) <= scin; + end generate a; + +end tri_boltreg_p; diff --git a/rel/src/vhdl/tri/tri_caa_prism_abist.vhdl b/rel/src/vhdl/tri/tri_caa_prism_abist.vhdl new file mode 100644 index 0000000..74945e2 --- /dev/null +++ b/rel/src/vhdl/tri/tri_caa_prism_abist.vhdl @@ -0,0 +1,150 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- +-- Description: A2 Core ABIST Engine +-- +library ieee, ibm; +use ieee.std_logic_1164.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +library support; +USE support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + + +entity tri_caa_prism_abist is +generic(expand_type : integer := 1 ); -- 0=ibm (Umbra), 1=non-ibm, 2=ibm (CDP) +Port (vdd : INOUT power_logic; + gnd : INOUT power_logic; + nclk : In clk_logic; + scan_dis_dc_b : In std_ulogic; + lcb_clkoff_dc_b : In std_ulogic; + lcb_mpw1_dc_b : In std_ulogic; + lcb_mpw2_dc_b : In std_ulogic; + lcb_delay_lclkr_dc : In std_ulogic; + lcb_delay_lclkr_np_dc : In std_ulogic; + lcb_act_dis_dc : In std_ulogic; + lcb_d_mode_dc : In std_ulogic; + gptr_thold : In std_ulogic; + gptr_scan_in : In std_ulogic; + gptr_scan_out : Out std_ulogic; + abist_thold : In std_ulogic; + abist_sg : In std_ulogic; + abist_scan_in : In std_ulogic; + abist_scan_out : Out std_ulogic; + -- LBIST + ABIST Engine Controls + abist_done_in_dc : In std_ulogic; + abist_done_out_dc : Out std_ulogic; + abist_mode_dc : In std_ulogic; + abist_start_test : In std_ulogic; + lbist_mode_dc : In std_ulogic; + lbist_ac_mode_dc : In std_ulogic; + -- ABIST Outputs + abist_waddr_0 : Out std_ulogic_vector(0 to 9); + abist_waddr_1 : Out std_ulogic_vector(0 to 9); + abist_grf_wenb_0 : Out std_ulogic; + abist_grf_wenb_1 : Out std_ulogic; + abist_raddr_0 : Out std_ulogic_vector(0 to 9); + abist_raddr_1 : Out std_ulogic_vector(0 to 9); + abist_grf_renb_0 : Out std_ulogic; + abist_grf_renb_1 : Out std_ulogic; + abist_g8t_wenb : Out std_ulogic; + abist_g8t1p_renb_0 : Out std_ulogic; + abist_g6t_r_wb : Out std_ulogic; + abist_di_g6t_2r : Out std_ulogic_vector(0 to 3); + abist_di_0 : Out std_ulogic_vector(0 to 3); + abist_di_1 : Out std_ulogic_vector(0 to 3); + abist_dcomp : Out std_ulogic_vector(0 to 3); + abist_dcomp_g6t_2r : Out std_ulogic_vector(0 to 3); + abist_bw_0 : Out std_ulogic; + abist_bw_1 : Out std_ulogic; + abist_wl32_g8t_comp_ena : Out std_ulogic; + abist_wl64_g8t_comp_ena : Out std_ulogic; + abist_wl128_g8t_comp_ena : Out std_ulogic; + abist_wl144_comp_ena : Out std_ulogic; + abist_wl256_comp_ena : Out std_ulogic; + abist_wl512_comp_ena : Out std_ulogic; + abist_ena_dc : Out std_ulogic; + abist_raw_dc_b : Out std_ulogic +); + +-- synopsys translate_off + + + + +-- synopsys translate_on +end entity tri_caa_prism_abist; + +architecture tri_caa_prism_abist of tri_caa_prism_abist is + +signal unused : std_ulogic; +-- synopsys translate_off +-- synopsys translate_on + +begin + + gptr_scan_out <= '0'; + abist_scan_out <= '0'; + abist_done_out_dc <= '0'; + abist_waddr_0 <= "0000000000"; + abist_waddr_1 <= "0000000000"; + abist_grf_wenb_0 <= '0'; + abist_grf_wenb_1 <= '0'; + abist_raddr_0 <= "0000000000"; + abist_raddr_1 <= "0000000000"; + abist_grf_renb_0 <= '0'; + abist_grf_renb_1 <= '0'; + abist_g8t_wenb <= '0'; + abist_g8t1p_renb_0 <= '0'; + abist_g6t_r_wb <= '0'; + abist_di_g6t_2r <= "0000"; + abist_di_0 <= "0000"; + abist_di_1 <= "0000"; + abist_dcomp <= "0000"; + abist_dcomp_g6t_2r <= "0000"; + abist_bw_0 <= '0'; + abist_bw_1 <= '0'; + abist_wl32_g8t_comp_ena <= '0'; + abist_wl64_g8t_comp_ena <= '0'; + abist_wl128_g8t_comp_ena <= '0'; + abist_wl144_comp_ena <= '0'; + abist_wl256_comp_ena <= '0'; + abist_wl512_comp_ena <= '0'; + abist_ena_dc <= '0'; + abist_raw_dc_b <= '0'; + + unused <= or_reduce(scan_dis_dc_b & lcb_clkoff_dc_b & lcb_mpw1_dc_b & lcb_mpw2_dc_b & + lcb_delay_lclkr_dc & lcb_delay_lclkr_np_dc & lcb_act_dis_dc & lcb_d_mode_dc & + gptr_thold & gptr_scan_in & abist_thold & abist_sg & abist_scan_in & + abist_done_in_dc & abist_mode_dc & abist_start_test & + lbist_mode_dc & lbist_ac_mode_dc ); + +end tri_caa_prism_abist; diff --git a/rel/src/vhdl/tri/tri_cam_16x143_1r1w1c.vhdl b/rel/src/vhdl/tri/tri_cam_16x143_1r1w1c.vhdl new file mode 100644 index 0000000..f8f6af7 --- /dev/null +++ b/rel/src/vhdl/tri/tri_cam_16x143_1r1w1c.vhdl @@ -0,0 +1,2838 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +--******************************************************************** +--* TITLE: I-ERAT CAM Tri-Library Model +--* NAME: tri_cam_16x143_1r1w1c + +library ieee; +use ieee.std_logic_1164.all; +library ibm; +use ibm.std_ulogic_unsigned.all; +use ibm.std_ulogic_function_support.all; +library support; +use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; +-- pragma translate_off +-- pragma translate_on +entity tri_cam_16x143_1r1w1c is + + generic (cam_data_width : natural := 84; + array_data_width : natural := 68; + rpn_width : natural := 30; + num_entry : natural := 16; + num_entry_log2 : natural := 4; + expand_type : integer := 1); + port( + gnd : inout power_logic; + vdd : inout power_logic; + vcs : inout power_logic; + + nclk : in clk_logic; + tc_ccflush_dc : in std_ulogic; + tc_scan_dis_dc_b : in std_ulogic; + tc_scan_diag_dc : in std_ulogic; + tc_lbist_en_dc : in std_ulogic; + an_ac_atpg_en_dc : in std_ulogic; + + lcb_d_mode_dc : in std_ulogic; + lcb_clkoff_dc_b : in std_ulogic; + lcb_act_dis_dc : in std_ulogic; + lcb_mpw1_dc_b : in std_ulogic_vector(0 to 3); + lcb_mpw2_dc_b : in std_ulogic; + lcb_delay_lclkr_dc : in std_ulogic_vector(0 to 3); + + pc_sg_2 : in std_ulogic; + pc_func_slp_sl_thold_2 : in std_ulogic; + pc_func_slp_nsl_thold_2 : in std_ulogic; + pc_regf_slp_sl_thold_2 : in std_ulogic; + pc_time_sl_thold_2 : in std_ulogic; + pc_fce_2 : in std_ulogic; + + func_scan_in : in std_ulogic; + func_scan_out : out std_ulogic; + regfile_scan_in : in std_ulogic_vector(0 TO 4); + regfile_scan_out : out std_ulogic_vector(0 TO 4); + time_scan_in : in std_ulogic; + time_scan_out : out std_ulogic; + + + rd_val : in std_ulogic; + rd_val_late : in std_ulogic; + rw_entry : in std_ulogic_vector(0 to num_entry_log2-1); + + wr_array_data : in std_ulogic_vector(0 to array_data_width-1); + wr_cam_data : in std_ulogic_vector(0 to cam_data_width-1); + wr_array_val : in std_ulogic_vector(0 to 1); + wr_cam_val : in std_ulogic_vector(0 to 1); + wr_val_early : in std_ulogic; + + comp_request : in std_ulogic; + comp_addr : in std_ulogic_vector(0 to 51); + addr_enable : in std_ulogic_vector(0 to 1); + comp_pgsize : in std_ulogic_vector(0 to 2); + pgsize_enable : in std_ulogic; + comp_class : in std_ulogic_vector(0 to 1); + class_enable : in std_ulogic_vector(0 to 2); + comp_extclass : in std_ulogic_vector(0 to 1); + extclass_enable : in std_ulogic_vector(0 to 1); + comp_state : in std_ulogic_vector(0 to 1); + state_enable : in std_ulogic_vector(0 to 1); + comp_thdid : in std_ulogic_vector(0 to 3); + thdid_enable : in std_ulogic_vector(0 to 1); + comp_pid : in std_ulogic_vector(0 to 7); + pid_enable : in std_ulogic; + comp_invalidate : in std_ulogic; + flash_invalidate : in std_ulogic; + + array_cmp_data : out std_ulogic_vector(0 to array_data_width-1); + rd_array_data : out std_ulogic_vector(0 to array_data_width-1); + + cam_cmp_data : out std_ulogic_vector(0 to cam_data_width-1); + cam_hit : out std_ulogic; + cam_hit_entry : out std_ulogic_vector(0 to num_entry_log2-1); + entry_match : out std_ulogic_vector(0 to num_entry-1); + entry_valid : out std_ulogic_vector(0 to num_entry-1); + rd_cam_data : out std_ulogic_vector(0 to cam_data_width-1); + + +bypass_mux_enab_np1 : in std_ulogic; +bypass_attr_np1 : in std_ulogic_vector(0 to 20); +attr_np2 : out std_ulogic_vector(0 to 20); +rpn_np2 : out std_ulogic_vector(22 to 51) + + ); +-- synopsys translate_off +-- synopsys translate_on +end entity tri_cam_16x143_1r1w1c; +architecture tri_cam_16x143_1r1w1c of tri_cam_16x143_1r1w1c is +component tri_cam_16x143_1r1w1c_matchline + generic (have_xbit : integer := 1; + num_pgsizes : integer := 5; + have_cmpmask : integer := 1; + cmpmask_width : integer := 4); +port( + addr_in : in std_ulogic_vector(0 to 51); + addr_enable : in std_ulogic_vector(0 to 1); + comp_pgsize : in std_ulogic_vector(0 to 2); + pgsize_enable : in std_ulogic; + entry_size : in std_ulogic_vector(0 to 2); + entry_cmpmask : in std_ulogic_vector(0 to cmpmask_width-1); + entry_xbit : in std_ulogic; + entry_xbitmask : in std_ulogic_vector(0 to cmpmask_width-1); + entry_epn : in std_ulogic_vector(0 to 51); + comp_class : in std_ulogic_vector(0 to 1); + entry_class : in std_ulogic_vector(0 to 1); + class_enable : in std_ulogic_vector(0 to 2); + comp_extclass : in std_ulogic_vector(0 to 1); + entry_extclass : in std_ulogic_vector(0 to 1); + extclass_enable : in std_ulogic_vector(0 to 1); + comp_state : in std_ulogic_vector(0 to 1); + entry_hv : in std_ulogic; + entry_ds : in std_ulogic; + state_enable : in std_ulogic_vector(0 to 1); + entry_thdid : in std_ulogic_vector(0 to 3); + comp_thdid : in std_ulogic_vector(0 to 3); + thdid_enable : in std_ulogic_vector(0 to 1); + entry_pid : in std_ulogic_vector(0 to 7); + comp_pid : in std_ulogic_vector(0 to 7); + pid_enable : in std_ulogic; + entry_v : in std_ulogic; + comp_invalidate : in std_ulogic; + + match : out std_ulogic +); +end component; +begin +a : if expand_type = 1 generate +component RAMB16_S9_S9 +-- pragma translate_off + generic + ( + SIM_COLLISION_CHECK : string := "none"); +-- pragma translate_on + port + ( + DOA : out std_logic_vector(7 downto 0); + DOB : out std_logic_vector(7 downto 0); + DOPA : out std_logic_vector(0 downto 0); + DOPB : out std_logic_vector(0 downto 0); + ADDRA : in std_logic_vector(10 downto 0); + ADDRB : in std_logic_vector(10 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(7 downto 0); + DIB : in std_logic_vector(7 downto 0); + DIPA : in std_logic_vector(0 downto 0); + DIPB : in std_logic_vector(0 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); +end component; +component RAMB16_S18_S18 +-- pragma translate_off + generic( + SIM_COLLISION_CHECK : string := "none"); +-- pragma translate_on + port( + DOA : out std_logic_vector(15 downto 0); + DOB : out std_logic_vector(15 downto 0); + DOPA : out std_logic_vector(1 downto 0); + DOPB : out std_logic_vector(1 downto 0); + + ADDRA : in std_logic_vector(9 downto 0); + ADDRB : in std_logic_vector(9 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(15 downto 0); + DIB : in std_logic_vector(15 downto 0); + DIPA : in std_logic_vector(1 downto 0); + DIPB : in std_logic_vector(1 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic); + end component; +component RAMB16_S36_S36 +-- pragma translate_off + generic( + SIM_COLLISION_CHECK : string := "none"); +-- pragma translate_on + port( + DOA : out std_logic_vector(31 downto 0); + DOB : out std_logic_vector(31 downto 0); + DOPA : out std_logic_vector(3 downto 0); + DOPB : out std_logic_vector(3 downto 0); + ADDRA : in std_logic_vector(8 downto 0); + ADDRB : in std_logic_vector(8 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(31 downto 0); + DIB : in std_logic_vector(31 downto 0); + DIPA : in std_logic_vector(3 downto 0); + DIPB : in std_logic_vector(3 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic); + end component; +-- pragma translate_off +-- pragma translate_on +signal clk,clk2x : std_ulogic; +signal bram0_addra, bram0_addrb : std_ulogic_vector(0 to 8); +signal bram1_addra, bram1_addrb : std_ulogic_vector(0 to 10); +signal bram2_addra, bram2_addrb : std_ulogic_vector(0 to 9); +signal bram0_wea, bram1_wea, bram2_wea : std_ulogic; +signal array_cmp_data_bram : std_ulogic_vector(0 to 55); +signal array_cmp_data_bramp : std_ulogic_vector(66 to 72); +-- Latches +signal sreset_q : std_ulogic; +signal gate_fq, gate_d : std_ulogic; +signal comp_addr_np1_d, comp_addr_np1_q : std_ulogic_vector(52-rpn_width to 51); +signal rpn_np2_d,rpn_np2_q : std_ulogic_vector(52-rpn_width to 51); +signal attr_np2_d,attr_np2_q : std_ulogic_vector(0 to 20); +-- CAM entry signals +signal entry0_epn_d, entry0_epn_q : std_ulogic_vector(0 to 51); +signal entry0_xbit_d, entry0_xbit_q : std_ulogic; +signal entry0_size_d, entry0_size_q : std_ulogic_vector(0 to 2); +signal entry0_v_d, entry0_v_q : std_ulogic; +signal entry0_thdid_d, entry0_thdid_q : std_ulogic_vector(0 to 3); +signal entry0_class_d, entry0_class_q : std_ulogic_vector(0 to 1); +signal entry0_extclass_d, entry0_extclass_q : std_ulogic_vector(0 to 1); +signal entry0_hv_d, entry0_hv_q : std_ulogic; +signal entry0_ds_d, entry0_ds_q : std_ulogic; +signal entry0_pid_d, entry0_pid_q : std_ulogic_vector(0 to 7); +signal entry0_cmpmask_d, entry0_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry0_parity_d, entry0_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry0_sel : std_ulogic_vector(0 to 1); +signal entry0_inval : std_ulogic; +signal entry0_v_muxsel : std_ulogic_vector(0 to 1); +signal entry0_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry0_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry1_epn_d, entry1_epn_q : std_ulogic_vector(0 to 51); +signal entry1_xbit_d, entry1_xbit_q : std_ulogic; +signal entry1_size_d, entry1_size_q : std_ulogic_vector(0 to 2); +signal entry1_v_d, entry1_v_q : std_ulogic; +signal entry1_thdid_d, entry1_thdid_q : std_ulogic_vector(0 to 3); +signal entry1_class_d, entry1_class_q : std_ulogic_vector(0 to 1); +signal entry1_extclass_d, entry1_extclass_q : std_ulogic_vector(0 to 1); +signal entry1_hv_d, entry1_hv_q : std_ulogic; +signal entry1_ds_d, entry1_ds_q : std_ulogic; +signal entry1_pid_d, entry1_pid_q : std_ulogic_vector(0 to 7); +signal entry1_cmpmask_d, entry1_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry1_parity_d, entry1_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry1_sel : std_ulogic_vector(0 to 1); +signal entry1_inval : std_ulogic; +signal entry1_v_muxsel : std_ulogic_vector(0 to 1); +signal entry1_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry1_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry2_epn_d, entry2_epn_q : std_ulogic_vector(0 to 51); +signal entry2_xbit_d, entry2_xbit_q : std_ulogic; +signal entry2_size_d, entry2_size_q : std_ulogic_vector(0 to 2); +signal entry2_v_d, entry2_v_q : std_ulogic; +signal entry2_thdid_d, entry2_thdid_q : std_ulogic_vector(0 to 3); +signal entry2_class_d, entry2_class_q : std_ulogic_vector(0 to 1); +signal entry2_extclass_d, entry2_extclass_q : std_ulogic_vector(0 to 1); +signal entry2_hv_d, entry2_hv_q : std_ulogic; +signal entry2_ds_d, entry2_ds_q : std_ulogic; +signal entry2_pid_d, entry2_pid_q : std_ulogic_vector(0 to 7); +signal entry2_cmpmask_d, entry2_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry2_parity_d, entry2_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry2_sel : std_ulogic_vector(0 to 1); +signal entry2_inval : std_ulogic; +signal entry2_v_muxsel : std_ulogic_vector(0 to 1); +signal entry2_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry2_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry3_epn_d, entry3_epn_q : std_ulogic_vector(0 to 51); +signal entry3_xbit_d, entry3_xbit_q : std_ulogic; +signal entry3_size_d, entry3_size_q : std_ulogic_vector(0 to 2); +signal entry3_v_d, entry3_v_q : std_ulogic; +signal entry3_thdid_d, entry3_thdid_q : std_ulogic_vector(0 to 3); +signal entry3_class_d, entry3_class_q : std_ulogic_vector(0 to 1); +signal entry3_extclass_d, entry3_extclass_q : std_ulogic_vector(0 to 1); +signal entry3_hv_d, entry3_hv_q : std_ulogic; +signal entry3_ds_d, entry3_ds_q : std_ulogic; +signal entry3_pid_d, entry3_pid_q : std_ulogic_vector(0 to 7); +signal entry3_cmpmask_d, entry3_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry3_parity_d, entry3_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry3_sel : std_ulogic_vector(0 to 1); +signal entry3_inval : std_ulogic; +signal entry3_v_muxsel : std_ulogic_vector(0 to 1); +signal entry3_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry3_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry4_epn_d, entry4_epn_q : std_ulogic_vector(0 to 51); +signal entry4_xbit_d, entry4_xbit_q : std_ulogic; +signal entry4_size_d, entry4_size_q : std_ulogic_vector(0 to 2); +signal entry4_v_d, entry4_v_q : std_ulogic; +signal entry4_thdid_d, entry4_thdid_q : std_ulogic_vector(0 to 3); +signal entry4_class_d, entry4_class_q : std_ulogic_vector(0 to 1); +signal entry4_extclass_d, entry4_extclass_q : std_ulogic_vector(0 to 1); +signal entry4_hv_d, entry4_hv_q : std_ulogic; +signal entry4_ds_d, entry4_ds_q : std_ulogic; +signal entry4_pid_d, entry4_pid_q : std_ulogic_vector(0 to 7); +signal entry4_cmpmask_d, entry4_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry4_parity_d, entry4_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry4_sel : std_ulogic_vector(0 to 1); +signal entry4_inval : std_ulogic; +signal entry4_v_muxsel : std_ulogic_vector(0 to 1); +signal entry4_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry4_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry5_epn_d, entry5_epn_q : std_ulogic_vector(0 to 51); +signal entry5_xbit_d, entry5_xbit_q : std_ulogic; +signal entry5_size_d, entry5_size_q : std_ulogic_vector(0 to 2); +signal entry5_v_d, entry5_v_q : std_ulogic; +signal entry5_thdid_d, entry5_thdid_q : std_ulogic_vector(0 to 3); +signal entry5_class_d, entry5_class_q : std_ulogic_vector(0 to 1); +signal entry5_extclass_d, entry5_extclass_q : std_ulogic_vector(0 to 1); +signal entry5_hv_d, entry5_hv_q : std_ulogic; +signal entry5_ds_d, entry5_ds_q : std_ulogic; +signal entry5_pid_d, entry5_pid_q : std_ulogic_vector(0 to 7); +signal entry5_cmpmask_d, entry5_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry5_parity_d, entry5_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry5_sel : std_ulogic_vector(0 to 1); +signal entry5_inval : std_ulogic; +signal entry5_v_muxsel : std_ulogic_vector(0 to 1); +signal entry5_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry5_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry6_epn_d, entry6_epn_q : std_ulogic_vector(0 to 51); +signal entry6_xbit_d, entry6_xbit_q : std_ulogic; +signal entry6_size_d, entry6_size_q : std_ulogic_vector(0 to 2); +signal entry6_v_d, entry6_v_q : std_ulogic; +signal entry6_thdid_d, entry6_thdid_q : std_ulogic_vector(0 to 3); +signal entry6_class_d, entry6_class_q : std_ulogic_vector(0 to 1); +signal entry6_extclass_d, entry6_extclass_q : std_ulogic_vector(0 to 1); +signal entry6_hv_d, entry6_hv_q : std_ulogic; +signal entry6_ds_d, entry6_ds_q : std_ulogic; +signal entry6_pid_d, entry6_pid_q : std_ulogic_vector(0 to 7); +signal entry6_cmpmask_d, entry6_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry6_parity_d, entry6_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry6_sel : std_ulogic_vector(0 to 1); +signal entry6_inval : std_ulogic; +signal entry6_v_muxsel : std_ulogic_vector(0 to 1); +signal entry6_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry6_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry7_epn_d, entry7_epn_q : std_ulogic_vector(0 to 51); +signal entry7_xbit_d, entry7_xbit_q : std_ulogic; +signal entry7_size_d, entry7_size_q : std_ulogic_vector(0 to 2); +signal entry7_v_d, entry7_v_q : std_ulogic; +signal entry7_thdid_d, entry7_thdid_q : std_ulogic_vector(0 to 3); +signal entry7_class_d, entry7_class_q : std_ulogic_vector(0 to 1); +signal entry7_extclass_d, entry7_extclass_q : std_ulogic_vector(0 to 1); +signal entry7_hv_d, entry7_hv_q : std_ulogic; +signal entry7_ds_d, entry7_ds_q : std_ulogic; +signal entry7_pid_d, entry7_pid_q : std_ulogic_vector(0 to 7); +signal entry7_cmpmask_d, entry7_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry7_parity_d, entry7_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry7_sel : std_ulogic_vector(0 to 1); +signal entry7_inval : std_ulogic; +signal entry7_v_muxsel : std_ulogic_vector(0 to 1); +signal entry7_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry7_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry8_epn_d, entry8_epn_q : std_ulogic_vector(0 to 51); +signal entry8_xbit_d, entry8_xbit_q : std_ulogic; +signal entry8_size_d, entry8_size_q : std_ulogic_vector(0 to 2); +signal entry8_v_d, entry8_v_q : std_ulogic; +signal entry8_thdid_d, entry8_thdid_q : std_ulogic_vector(0 to 3); +signal entry8_class_d, entry8_class_q : std_ulogic_vector(0 to 1); +signal entry8_extclass_d, entry8_extclass_q : std_ulogic_vector(0 to 1); +signal entry8_hv_d, entry8_hv_q : std_ulogic; +signal entry8_ds_d, entry8_ds_q : std_ulogic; +signal entry8_pid_d, entry8_pid_q : std_ulogic_vector(0 to 7); +signal entry8_cmpmask_d, entry8_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry8_parity_d, entry8_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry8_sel : std_ulogic_vector(0 to 1); +signal entry8_inval : std_ulogic; +signal entry8_v_muxsel : std_ulogic_vector(0 to 1); +signal entry8_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry8_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry9_epn_d, entry9_epn_q : std_ulogic_vector(0 to 51); +signal entry9_xbit_d, entry9_xbit_q : std_ulogic; +signal entry9_size_d, entry9_size_q : std_ulogic_vector(0 to 2); +signal entry9_v_d, entry9_v_q : std_ulogic; +signal entry9_thdid_d, entry9_thdid_q : std_ulogic_vector(0 to 3); +signal entry9_class_d, entry9_class_q : std_ulogic_vector(0 to 1); +signal entry9_extclass_d, entry9_extclass_q : std_ulogic_vector(0 to 1); +signal entry9_hv_d, entry9_hv_q : std_ulogic; +signal entry9_ds_d, entry9_ds_q : std_ulogic; +signal entry9_pid_d, entry9_pid_q : std_ulogic_vector(0 to 7); +signal entry9_cmpmask_d, entry9_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry9_parity_d, entry9_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry9_sel : std_ulogic_vector(0 to 1); +signal entry9_inval : std_ulogic; +signal entry9_v_muxsel : std_ulogic_vector(0 to 1); +signal entry9_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry9_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry10_epn_d, entry10_epn_q : std_ulogic_vector(0 to 51); +signal entry10_xbit_d, entry10_xbit_q : std_ulogic; +signal entry10_size_d, entry10_size_q : std_ulogic_vector(0 to 2); +signal entry10_v_d, entry10_v_q : std_ulogic; +signal entry10_thdid_d, entry10_thdid_q : std_ulogic_vector(0 to 3); +signal entry10_class_d, entry10_class_q : std_ulogic_vector(0 to 1); +signal entry10_extclass_d, entry10_extclass_q : std_ulogic_vector(0 to 1); +signal entry10_hv_d, entry10_hv_q : std_ulogic; +signal entry10_ds_d, entry10_ds_q : std_ulogic; +signal entry10_pid_d, entry10_pid_q : std_ulogic_vector(0 to 7); +signal entry10_cmpmask_d, entry10_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry10_parity_d, entry10_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry10_sel : std_ulogic_vector(0 to 1); +signal entry10_inval : std_ulogic; +signal entry10_v_muxsel : std_ulogic_vector(0 to 1); +signal entry10_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry10_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry11_epn_d, entry11_epn_q : std_ulogic_vector(0 to 51); +signal entry11_xbit_d, entry11_xbit_q : std_ulogic; +signal entry11_size_d, entry11_size_q : std_ulogic_vector(0 to 2); +signal entry11_v_d, entry11_v_q : std_ulogic; +signal entry11_thdid_d, entry11_thdid_q : std_ulogic_vector(0 to 3); +signal entry11_class_d, entry11_class_q : std_ulogic_vector(0 to 1); +signal entry11_extclass_d, entry11_extclass_q : std_ulogic_vector(0 to 1); +signal entry11_hv_d, entry11_hv_q : std_ulogic; +signal entry11_ds_d, entry11_ds_q : std_ulogic; +signal entry11_pid_d, entry11_pid_q : std_ulogic_vector(0 to 7); +signal entry11_cmpmask_d, entry11_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry11_parity_d, entry11_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry11_sel : std_ulogic_vector(0 to 1); +signal entry11_inval : std_ulogic; +signal entry11_v_muxsel : std_ulogic_vector(0 to 1); +signal entry11_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry11_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry12_epn_d, entry12_epn_q : std_ulogic_vector(0 to 51); +signal entry12_xbit_d, entry12_xbit_q : std_ulogic; +signal entry12_size_d, entry12_size_q : std_ulogic_vector(0 to 2); +signal entry12_v_d, entry12_v_q : std_ulogic; +signal entry12_thdid_d, entry12_thdid_q : std_ulogic_vector(0 to 3); +signal entry12_class_d, entry12_class_q : std_ulogic_vector(0 to 1); +signal entry12_extclass_d, entry12_extclass_q : std_ulogic_vector(0 to 1); +signal entry12_hv_d, entry12_hv_q : std_ulogic; +signal entry12_ds_d, entry12_ds_q : std_ulogic; +signal entry12_pid_d, entry12_pid_q : std_ulogic_vector(0 to 7); +signal entry12_cmpmask_d, entry12_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry12_parity_d, entry12_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry12_sel : std_ulogic_vector(0 to 1); +signal entry12_inval : std_ulogic; +signal entry12_v_muxsel : std_ulogic_vector(0 to 1); +signal entry12_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry12_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry13_epn_d, entry13_epn_q : std_ulogic_vector(0 to 51); +signal entry13_xbit_d, entry13_xbit_q : std_ulogic; +signal entry13_size_d, entry13_size_q : std_ulogic_vector(0 to 2); +signal entry13_v_d, entry13_v_q : std_ulogic; +signal entry13_thdid_d, entry13_thdid_q : std_ulogic_vector(0 to 3); +signal entry13_class_d, entry13_class_q : std_ulogic_vector(0 to 1); +signal entry13_extclass_d, entry13_extclass_q : std_ulogic_vector(0 to 1); +signal entry13_hv_d, entry13_hv_q : std_ulogic; +signal entry13_ds_d, entry13_ds_q : std_ulogic; +signal entry13_pid_d, entry13_pid_q : std_ulogic_vector(0 to 7); +signal entry13_cmpmask_d, entry13_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry13_parity_d, entry13_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry13_sel : std_ulogic_vector(0 to 1); +signal entry13_inval : std_ulogic; +signal entry13_v_muxsel : std_ulogic_vector(0 to 1); +signal entry13_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry13_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry14_epn_d, entry14_epn_q : std_ulogic_vector(0 to 51); +signal entry14_xbit_d, entry14_xbit_q : std_ulogic; +signal entry14_size_d, entry14_size_q : std_ulogic_vector(0 to 2); +signal entry14_v_d, entry14_v_q : std_ulogic; +signal entry14_thdid_d, entry14_thdid_q : std_ulogic_vector(0 to 3); +signal entry14_class_d, entry14_class_q : std_ulogic_vector(0 to 1); +signal entry14_extclass_d, entry14_extclass_q : std_ulogic_vector(0 to 1); +signal entry14_hv_d, entry14_hv_q : std_ulogic; +signal entry14_ds_d, entry14_ds_q : std_ulogic; +signal entry14_pid_d, entry14_pid_q : std_ulogic_vector(0 to 7); +signal entry14_cmpmask_d, entry14_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry14_parity_d, entry14_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry14_sel : std_ulogic_vector(0 to 1); +signal entry14_inval : std_ulogic; +signal entry14_v_muxsel : std_ulogic_vector(0 to 1); +signal entry14_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry14_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry15_epn_d, entry15_epn_q : std_ulogic_vector(0 to 51); +signal entry15_xbit_d, entry15_xbit_q : std_ulogic; +signal entry15_size_d, entry15_size_q : std_ulogic_vector(0 to 2); +signal entry15_v_d, entry15_v_q : std_ulogic; +signal entry15_thdid_d, entry15_thdid_q : std_ulogic_vector(0 to 3); +signal entry15_class_d, entry15_class_q : std_ulogic_vector(0 to 1); +signal entry15_extclass_d, entry15_extclass_q : std_ulogic_vector(0 to 1); +signal entry15_hv_d, entry15_hv_q : std_ulogic; +signal entry15_ds_d, entry15_ds_q : std_ulogic; +signal entry15_pid_d, entry15_pid_q : std_ulogic_vector(0 to 7); +signal entry15_cmpmask_d, entry15_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry15_parity_d, entry15_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry15_sel : std_ulogic_vector(0 to 1); +signal entry15_inval : std_ulogic; +signal entry15_v_muxsel : std_ulogic_vector(0 to 1); +signal entry15_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry15_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal cam_cmp_data_muxsel : std_ulogic_vector(0 to 4); +signal rd_cam_data_muxsel : std_ulogic_vector(0 to 4); +signal cam_cmp_data_np1 : std_ulogic_vector(0 to cam_data_width-1); +signal array_cmp_data_np1 : std_ulogic_vector(0 to array_data_width-1); +signal wr_array_data_bram : std_ulogic_vector(0 to 72); +signal rd_array_data_d_std : std_logic_vector(0 to 72); +signal array_cmp_data_bram_std : std_logic_vector(0 to 55); +signal array_cmp_data_bramp_std : std_logic_vector(66 to 72); +-- latch signals +signal rd_array_data_d : std_ulogic_vector(0 to array_data_width-1); +signal rd_array_data_q : std_ulogic_vector(0 to array_data_width-1); +signal cam_cmp_data_d : std_ulogic_vector(0 to cam_data_width-1); +signal cam_cmp_data_q : std_ulogic_vector(0 to cam_data_width-1); +signal cam_cmp_parity_d : std_ulogic_vector(0 to 9); +signal cam_cmp_parity_q : std_ulogic_vector(0 to 9); +signal rd_cam_data_d : std_ulogic_vector(0 to cam_data_width-1); +signal rd_cam_data_q : std_ulogic_vector(0 to cam_data_width-1); +signal entry_match_d : std_ulogic_vector(0 to num_entry-1); +signal entry_match_q : std_ulogic_vector(0 to num_entry-1); +signal match_vec : std_ulogic_vector(0 to num_entry-1); +signal cam_hit_entry_d : std_ulogic_vector(0 to num_entry_log2-1); +signal cam_hit_entry_q : std_ulogic_vector(0 to num_entry_log2-1); +signal cam_hit_d : std_ulogic; +signal cam_hit_q : std_ulogic; +signal toggle_d : std_ulogic; +signal toggle_q : std_ulogic; +signal toggle2x_d : std_ulogic; +signal toggle2x_q : std_ulogic; +begin + +clk <= not nclk.clk; +clk2x <= nclk.clk2x; +rlatch: process (clk) +begin +if(rising_edge(clk)) then +sreset_q <= nclk.sreset; +end if; +end process; +tlatch: process (nclk.clk,sreset_q) +begin +if(rising_edge(nclk.clk)) then +if (sreset_q = '1') then +toggle_q <= '1'; +else +toggle_q <= toggle_d; +end if; +end if; +end process; +flatch: process (nclk.clk2x) +begin +if(rising_edge(nclk.clk2x)) then +toggle2x_q <= toggle2x_d; +gate_fq <= gate_d; +end if; +end process; +toggle_d <= not toggle_q; +toggle2x_d <= toggle_q; +gate_d <= toggle_q xor toggle2x_q; +slatch: process (nclk,sreset_q) +begin +if(rising_edge(nclk.clk)) then +if (sreset_q = '1') then +cam_cmp_data_q <= (others => '0'); +cam_cmp_parity_q <= (others => '0'); +rd_cam_data_q <= (others => '0'); +rd_array_data_q <= (others => '0'); +entry_match_q <= (others => '0'); +cam_hit_entry_q <= (others => '0'); +cam_hit_q <= '0'; +comp_addr_np1_q <= (others => '0'); +rpn_np2_q <= (others => '0'); +attr_np2_q <= (others => '0'); +entry0_size_q <= (others => '0'); +entry0_xbit_q <= '0'; +entry0_epn_q <= (others => '0'); +entry0_class_q <= (others => '0'); +entry0_extclass_q <= (others => '0'); +entry0_hv_q <= '0'; +entry0_ds_q <= '0'; +entry0_thdid_q <= (others => '0'); +entry0_pid_q <= (others => '0'); +entry0_v_q <= '0'; +entry0_parity_q <= (others => '0'); +entry0_cmpmask_q <= (others => '0'); +entry1_size_q <= (others => '0'); +entry1_xbit_q <= '0'; +entry1_epn_q <= (others => '0'); +entry1_class_q <= (others => '0'); +entry1_extclass_q <= (others => '0'); +entry1_hv_q <= '0'; +entry1_ds_q <= '0'; +entry1_thdid_q <= (others => '0'); +entry1_pid_q <= (others => '0'); +entry1_v_q <= '0'; +entry1_parity_q <= (others => '0'); +entry1_cmpmask_q <= (others => '0'); +entry2_size_q <= (others => '0'); +entry2_xbit_q <= '0'; +entry2_epn_q <= (others => '0'); +entry2_class_q <= (others => '0'); +entry2_extclass_q <= (others => '0'); +entry2_hv_q <= '0'; +entry2_ds_q <= '0'; +entry2_thdid_q <= (others => '0'); +entry2_pid_q <= (others => '0'); +entry2_v_q <= '0'; +entry2_parity_q <= (others => '0'); +entry2_cmpmask_q <= (others => '0'); +entry3_size_q <= (others => '0'); +entry3_xbit_q <= '0'; +entry3_epn_q <= (others => '0'); +entry3_class_q <= (others => '0'); +entry3_extclass_q <= (others => '0'); +entry3_hv_q <= '0'; +entry3_ds_q <= '0'; +entry3_thdid_q <= (others => '0'); +entry3_pid_q <= (others => '0'); +entry3_v_q <= '0'; +entry3_parity_q <= (others => '0'); +entry3_cmpmask_q <= (others => '0'); +entry4_size_q <= (others => '0'); +entry4_xbit_q <= '0'; +entry4_epn_q <= (others => '0'); +entry4_class_q <= (others => '0'); +entry4_extclass_q <= (others => '0'); +entry4_hv_q <= '0'; +entry4_ds_q <= '0'; +entry4_thdid_q <= (others => '0'); +entry4_pid_q <= (others => '0'); +entry4_v_q <= '0'; +entry4_parity_q <= (others => '0'); +entry4_cmpmask_q <= (others => '0'); +entry5_size_q <= (others => '0'); +entry5_xbit_q <= '0'; +entry5_epn_q <= (others => '0'); +entry5_class_q <= (others => '0'); +entry5_extclass_q <= (others => '0'); +entry5_hv_q <= '0'; +entry5_ds_q <= '0'; +entry5_thdid_q <= (others => '0'); +entry5_pid_q <= (others => '0'); +entry5_v_q <= '0'; +entry5_parity_q <= (others => '0'); +entry5_cmpmask_q <= (others => '0'); +entry6_size_q <= (others => '0'); +entry6_xbit_q <= '0'; +entry6_epn_q <= (others => '0'); +entry6_class_q <= (others => '0'); +entry6_extclass_q <= (others => '0'); +entry6_hv_q <= '0'; +entry6_ds_q <= '0'; +entry6_thdid_q <= (others => '0'); +entry6_pid_q <= (others => '0'); +entry6_v_q <= '0'; +entry6_parity_q <= (others => '0'); +entry6_cmpmask_q <= (others => '0'); +entry7_size_q <= (others => '0'); +entry7_xbit_q <= '0'; +entry7_epn_q <= (others => '0'); +entry7_class_q <= (others => '0'); +entry7_extclass_q <= (others => '0'); +entry7_hv_q <= '0'; +entry7_ds_q <= '0'; +entry7_thdid_q <= (others => '0'); +entry7_pid_q <= (others => '0'); +entry7_v_q <= '0'; +entry7_parity_q <= (others => '0'); +entry7_cmpmask_q <= (others => '0'); +entry8_size_q <= (others => '0'); +entry8_xbit_q <= '0'; +entry8_epn_q <= (others => '0'); +entry8_class_q <= (others => '0'); +entry8_extclass_q <= (others => '0'); +entry8_hv_q <= '0'; +entry8_ds_q <= '0'; +entry8_thdid_q <= (others => '0'); +entry8_pid_q <= (others => '0'); +entry8_v_q <= '0'; +entry8_parity_q <= (others => '0'); +entry8_cmpmask_q <= (others => '0'); +entry9_size_q <= (others => '0'); +entry9_xbit_q <= '0'; +entry9_epn_q <= (others => '0'); +entry9_class_q <= (others => '0'); +entry9_extclass_q <= (others => '0'); +entry9_hv_q <= '0'; +entry9_ds_q <= '0'; +entry9_thdid_q <= (others => '0'); +entry9_pid_q <= (others => '0'); +entry9_v_q <= '0'; +entry9_parity_q <= (others => '0'); +entry9_cmpmask_q <= (others => '0'); +entry10_size_q <= (others => '0'); +entry10_xbit_q <= '0'; +entry10_epn_q <= (others => '0'); +entry10_class_q <= (others => '0'); +entry10_extclass_q <= (others => '0'); +entry10_hv_q <= '0'; +entry10_ds_q <= '0'; +entry10_thdid_q <= (others => '0'); +entry10_pid_q <= (others => '0'); +entry10_v_q <= '0'; +entry10_parity_q <= (others => '0'); +entry10_cmpmask_q <= (others => '0'); +entry11_size_q <= (others => '0'); +entry11_xbit_q <= '0'; +entry11_epn_q <= (others => '0'); +entry11_class_q <= (others => '0'); +entry11_extclass_q <= (others => '0'); +entry11_hv_q <= '0'; +entry11_ds_q <= '0'; +entry11_thdid_q <= (others => '0'); +entry11_pid_q <= (others => '0'); +entry11_v_q <= '0'; +entry11_parity_q <= (others => '0'); +entry11_cmpmask_q <= (others => '0'); +entry12_size_q <= (others => '0'); +entry12_xbit_q <= '0'; +entry12_epn_q <= (others => '0'); +entry12_class_q <= (others => '0'); +entry12_extclass_q <= (others => '0'); +entry12_hv_q <= '0'; +entry12_ds_q <= '0'; +entry12_thdid_q <= (others => '0'); +entry12_pid_q <= (others => '0'); +entry12_v_q <= '0'; +entry12_parity_q <= (others => '0'); +entry12_cmpmask_q <= (others => '0'); +entry13_size_q <= (others => '0'); +entry13_xbit_q <= '0'; +entry13_epn_q <= (others => '0'); +entry13_class_q <= (others => '0'); +entry13_extclass_q <= (others => '0'); +entry13_hv_q <= '0'; +entry13_ds_q <= '0'; +entry13_thdid_q <= (others => '0'); +entry13_pid_q <= (others => '0'); +entry13_v_q <= '0'; +entry13_parity_q <= (others => '0'); +entry13_cmpmask_q <= (others => '0'); +entry14_size_q <= (others => '0'); +entry14_xbit_q <= '0'; +entry14_epn_q <= (others => '0'); +entry14_class_q <= (others => '0'); +entry14_extclass_q <= (others => '0'); +entry14_hv_q <= '0'; +entry14_ds_q <= '0'; +entry14_thdid_q <= (others => '0'); +entry14_pid_q <= (others => '0'); +entry14_v_q <= '0'; +entry14_parity_q <= (others => '0'); +entry14_cmpmask_q <= (others => '0'); +entry15_size_q <= (others => '0'); +entry15_xbit_q <= '0'; +entry15_epn_q <= (others => '0'); +entry15_class_q <= (others => '0'); +entry15_extclass_q <= (others => '0'); +entry15_hv_q <= '0'; +entry15_ds_q <= '0'; +entry15_thdid_q <= (others => '0'); +entry15_pid_q <= (others => '0'); +entry15_v_q <= '0'; +entry15_parity_q <= (others => '0'); +entry15_cmpmask_q <= (others => '0'); +else +cam_cmp_data_q <= cam_cmp_data_d; +rd_cam_data_q <= rd_cam_data_d; +rd_array_data_q <= rd_array_data_d; +entry_match_q <= entry_match_d; +cam_hit_entry_q <= cam_hit_entry_d; +cam_hit_q <= cam_hit_d; +cam_cmp_parity_q <= cam_cmp_parity_d; +comp_addr_np1_q <= comp_addr_np1_d; +rpn_np2_q <= rpn_np2_d; +attr_np2_q <= attr_np2_d; +entry0_size_q <= entry0_size_d; +entry0_xbit_q <= entry0_xbit_d; +entry0_epn_q <= entry0_epn_d; +entry0_class_q <= entry0_class_d; +entry0_extclass_q <= entry0_extclass_d; +entry0_hv_q <= entry0_hv_d; +entry0_ds_q <= entry0_ds_d; +entry0_thdid_q <= entry0_thdid_d; +entry0_pid_q <= entry0_pid_d; +entry0_v_q <= entry0_v_d; +entry0_parity_q <= entry0_parity_d; +entry0_cmpmask_q <= entry0_cmpmask_d; +entry1_size_q <= entry1_size_d; +entry1_xbit_q <= entry1_xbit_d; +entry1_epn_q <= entry1_epn_d; +entry1_class_q <= entry1_class_d; +entry1_extclass_q <= entry1_extclass_d; +entry1_hv_q <= entry1_hv_d; +entry1_ds_q <= entry1_ds_d; +entry1_thdid_q <= entry1_thdid_d; +entry1_pid_q <= entry1_pid_d; +entry1_v_q <= entry1_v_d; +entry1_parity_q <= entry1_parity_d; +entry1_cmpmask_q <= entry1_cmpmask_d; +entry2_size_q <= entry2_size_d; +entry2_xbit_q <= entry2_xbit_d; +entry2_epn_q <= entry2_epn_d; +entry2_class_q <= entry2_class_d; +entry2_extclass_q <= entry2_extclass_d; +entry2_hv_q <= entry2_hv_d; +entry2_ds_q <= entry2_ds_d; +entry2_thdid_q <= entry2_thdid_d; +entry2_pid_q <= entry2_pid_d; +entry2_v_q <= entry2_v_d; +entry2_parity_q <= entry2_parity_d; +entry2_cmpmask_q <= entry2_cmpmask_d; +entry3_size_q <= entry3_size_d; +entry3_xbit_q <= entry3_xbit_d; +entry3_epn_q <= entry3_epn_d; +entry3_class_q <= entry3_class_d; +entry3_extclass_q <= entry3_extclass_d; +entry3_hv_q <= entry3_hv_d; +entry3_ds_q <= entry3_ds_d; +entry3_thdid_q <= entry3_thdid_d; +entry3_pid_q <= entry3_pid_d; +entry3_v_q <= entry3_v_d; +entry3_parity_q <= entry3_parity_d; +entry3_cmpmask_q <= entry3_cmpmask_d; +entry4_size_q <= entry4_size_d; +entry4_xbit_q <= entry4_xbit_d; +entry4_epn_q <= entry4_epn_d; +entry4_class_q <= entry4_class_d; +entry4_extclass_q <= entry4_extclass_d; +entry4_hv_q <= entry4_hv_d; +entry4_ds_q <= entry4_ds_d; +entry4_thdid_q <= entry4_thdid_d; +entry4_pid_q <= entry4_pid_d; +entry4_v_q <= entry4_v_d; +entry4_parity_q <= entry4_parity_d; +entry4_cmpmask_q <= entry4_cmpmask_d; +entry5_size_q <= entry5_size_d; +entry5_xbit_q <= entry5_xbit_d; +entry5_epn_q <= entry5_epn_d; +entry5_class_q <= entry5_class_d; +entry5_extclass_q <= entry5_extclass_d; +entry5_hv_q <= entry5_hv_d; +entry5_ds_q <= entry5_ds_d; +entry5_thdid_q <= entry5_thdid_d; +entry5_pid_q <= entry5_pid_d; +entry5_v_q <= entry5_v_d; +entry5_parity_q <= entry5_parity_d; +entry5_cmpmask_q <= entry5_cmpmask_d; +entry6_size_q <= entry6_size_d; +entry6_xbit_q <= entry6_xbit_d; +entry6_epn_q <= entry6_epn_d; +entry6_class_q <= entry6_class_d; +entry6_extclass_q <= entry6_extclass_d; +entry6_hv_q <= entry6_hv_d; +entry6_ds_q <= entry6_ds_d; +entry6_thdid_q <= entry6_thdid_d; +entry6_pid_q <= entry6_pid_d; +entry6_v_q <= entry6_v_d; +entry6_parity_q <= entry6_parity_d; +entry6_cmpmask_q <= entry6_cmpmask_d; +entry7_size_q <= entry7_size_d; +entry7_xbit_q <= entry7_xbit_d; +entry7_epn_q <= entry7_epn_d; +entry7_class_q <= entry7_class_d; +entry7_extclass_q <= entry7_extclass_d; +entry7_hv_q <= entry7_hv_d; +entry7_ds_q <= entry7_ds_d; +entry7_thdid_q <= entry7_thdid_d; +entry7_pid_q <= entry7_pid_d; +entry7_v_q <= entry7_v_d; +entry7_parity_q <= entry7_parity_d; +entry7_cmpmask_q <= entry7_cmpmask_d; +entry8_size_q <= entry8_size_d; +entry8_xbit_q <= entry8_xbit_d; +entry8_epn_q <= entry8_epn_d; +entry8_class_q <= entry8_class_d; +entry8_extclass_q <= entry8_extclass_d; +entry8_hv_q <= entry8_hv_d; +entry8_ds_q <= entry8_ds_d; +entry8_thdid_q <= entry8_thdid_d; +entry8_pid_q <= entry8_pid_d; +entry8_v_q <= entry8_v_d; +entry8_parity_q <= entry8_parity_d; +entry8_cmpmask_q <= entry8_cmpmask_d; +entry9_size_q <= entry9_size_d; +entry9_xbit_q <= entry9_xbit_d; +entry9_epn_q <= entry9_epn_d; +entry9_class_q <= entry9_class_d; +entry9_extclass_q <= entry9_extclass_d; +entry9_hv_q <= entry9_hv_d; +entry9_ds_q <= entry9_ds_d; +entry9_thdid_q <= entry9_thdid_d; +entry9_pid_q <= entry9_pid_d; +entry9_v_q <= entry9_v_d; +entry9_parity_q <= entry9_parity_d; +entry9_cmpmask_q <= entry9_cmpmask_d; +entry10_size_q <= entry10_size_d; +entry10_xbit_q <= entry10_xbit_d; +entry10_epn_q <= entry10_epn_d; +entry10_class_q <= entry10_class_d; +entry10_extclass_q <= entry10_extclass_d; +entry10_hv_q <= entry10_hv_d; +entry10_ds_q <= entry10_ds_d; +entry10_thdid_q <= entry10_thdid_d; +entry10_pid_q <= entry10_pid_d; +entry10_v_q <= entry10_v_d; +entry10_parity_q <= entry10_parity_d; +entry10_cmpmask_q <= entry10_cmpmask_d; +entry11_size_q <= entry11_size_d; +entry11_xbit_q <= entry11_xbit_d; +entry11_epn_q <= entry11_epn_d; +entry11_class_q <= entry11_class_d; +entry11_extclass_q <= entry11_extclass_d; +entry11_hv_q <= entry11_hv_d; +entry11_ds_q <= entry11_ds_d; +entry11_thdid_q <= entry11_thdid_d; +entry11_pid_q <= entry11_pid_d; +entry11_v_q <= entry11_v_d; +entry11_parity_q <= entry11_parity_d; +entry11_cmpmask_q <= entry11_cmpmask_d; +entry12_size_q <= entry12_size_d; +entry12_xbit_q <= entry12_xbit_d; +entry12_epn_q <= entry12_epn_d; +entry12_class_q <= entry12_class_d; +entry12_extclass_q <= entry12_extclass_d; +entry12_hv_q <= entry12_hv_d; +entry12_ds_q <= entry12_ds_d; +entry12_thdid_q <= entry12_thdid_d; +entry12_pid_q <= entry12_pid_d; +entry12_v_q <= entry12_v_d; +entry12_parity_q <= entry12_parity_d; +entry12_cmpmask_q <= entry12_cmpmask_d; +entry13_size_q <= entry13_size_d; +entry13_xbit_q <= entry13_xbit_d; +entry13_epn_q <= entry13_epn_d; +entry13_class_q <= entry13_class_d; +entry13_extclass_q <= entry13_extclass_d; +entry13_hv_q <= entry13_hv_d; +entry13_ds_q <= entry13_ds_d; +entry13_thdid_q <= entry13_thdid_d; +entry13_pid_q <= entry13_pid_d; +entry13_v_q <= entry13_v_d; +entry13_parity_q <= entry13_parity_d; +entry13_cmpmask_q <= entry13_cmpmask_d; +entry14_size_q <= entry14_size_d; +entry14_xbit_q <= entry14_xbit_d; +entry14_epn_q <= entry14_epn_d; +entry14_class_q <= entry14_class_d; +entry14_extclass_q <= entry14_extclass_d; +entry14_hv_q <= entry14_hv_d; +entry14_ds_q <= entry14_ds_d; +entry14_thdid_q <= entry14_thdid_d; +entry14_pid_q <= entry14_pid_d; +entry14_v_q <= entry14_v_d; +entry14_parity_q <= entry14_parity_d; +entry14_cmpmask_q <= entry14_cmpmask_d; +entry15_size_q <= entry15_size_d; +entry15_xbit_q <= entry15_xbit_d; +entry15_epn_q <= entry15_epn_d; +entry15_class_q <= entry15_class_d; +entry15_extclass_q <= entry15_extclass_d; +entry15_hv_q <= entry15_hv_d; +entry15_ds_q <= entry15_ds_d; +entry15_thdid_q <= entry15_thdid_d; +entry15_pid_q <= entry15_pid_d; +entry15_v_q <= entry15_v_d; +entry15_parity_q <= entry15_parity_d; +entry15_cmpmask_q <= entry15_cmpmask_d; +end if; +end if; +end process; +----------------------------------------------------------------------- +-- latch input logic +----------------------------------------------------------------------- +comp_addr_np1_d <= comp_addr(52-rpn_width to 51); +cam_hit_d <= '1' when (match_vec /= "0000000000000000" and comp_request='1') else '0'; +cam_hit_entry_d <= "0001" when match_vec(0 to 1)="01" else + "0010" when match_vec(0 to 2)="001" else + "0011" when match_vec(0 to 3)="0001" else + "0100" when match_vec(0 to 4)="00001" else + "0101" when match_vec(0 to 5)="000001" else + "0110" when match_vec(0 to 6)="0000001" else + "0111" when match_vec(0 to 7)="00000001" else + "1000" when match_vec(0 to 8)="000000001" else + "1001" when match_vec(0 to 9)="0000000001" else + "1010" when match_vec(0 to 10)="00000000001" else + "1011" when match_vec(0 to 11)="000000000001" else + "1100" when match_vec(0 to 12)="0000000000001" else + "1101" when match_vec(0 to 13)="00000000000001" else + "1110" when match_vec(0 to 14)="000000000000001" else + "1111" when match_vec(0 to 15)="0000000000000001" else + "0000"; +entry_match_d <= match_vec when (comp_request='1') else (others => '0'); +wr_entry0_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="0000")) else '0'; +wr_entry0_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="0000")) else '0'; +with wr_entry0_sel(0) select + entry0_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry0_epn_q(0 to 31) when others; +with wr_entry0_sel(0) select + entry0_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry0_epn_q(32 to 51) when others; +with wr_entry0_sel(0) select + entry0_xbit_d <= wr_cam_data(52) when '1', + entry0_xbit_q when others; +with wr_entry0_sel(0) select + entry0_size_d <= wr_cam_data(53 to 55) when '1', + entry0_size_q(0 to 2) when others; +with wr_entry0_sel(0) select + entry0_class_d <= wr_cam_data(61 to 62) when '1', + entry0_class_q(0 to 1) when others; +with wr_entry0_sel(1) select + entry0_extclass_d <= wr_cam_data(63 to 64) when '1', + entry0_extclass_q(0 to 1) when others; +with wr_entry0_sel(1) select + entry0_hv_d <= wr_cam_data(65) when '1', + entry0_hv_q when others; +with wr_entry0_sel(1) select + entry0_ds_d <= wr_cam_data(66) when '1', + entry0_ds_q when others; +with wr_entry0_sel(1) select + entry0_pid_d <= wr_cam_data(67 to 74) when '1', + entry0_pid_q(0 to 7) when others; +with wr_entry0_sel(0) select + entry0_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry0_cmpmask_q when others; +-- the cam parity bits.. some wr_array_data bits contain parity for cam +with wr_entry0_sel(0) select + entry0_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry0_parity_q(0 to 3) when others; +with wr_entry0_sel(0) select + entry0_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry0_parity_q(4 to 6) when others; +with wr_entry0_sel(0) select + entry0_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry0_parity_q(7) when others; +with wr_entry0_sel(1) select + entry0_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry0_parity_q(8) when others; +with wr_entry0_sel(1) select + entry0_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry0_parity_q(9) when others; +wr_entry1_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="0001")) else '0'; +wr_entry1_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="0001")) else '0'; +with wr_entry1_sel(0) select + entry1_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry1_epn_q(0 to 31) when others; +with wr_entry1_sel(0) select + entry1_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry1_epn_q(32 to 51) when others; +with wr_entry1_sel(0) select + entry1_xbit_d <= wr_cam_data(52) when '1', + entry1_xbit_q when others; +with wr_entry1_sel(0) select + entry1_size_d <= wr_cam_data(53 to 55) when '1', + entry1_size_q(0 to 2) when others; +with wr_entry1_sel(0) select + entry1_class_d <= wr_cam_data(61 to 62) when '1', + entry1_class_q(0 to 1) when others; +with wr_entry1_sel(1) select + entry1_extclass_d <= wr_cam_data(63 to 64) when '1', + entry1_extclass_q(0 to 1) when others; +with wr_entry1_sel(1) select + entry1_hv_d <= wr_cam_data(65) when '1', + entry1_hv_q when others; +with wr_entry1_sel(1) select + entry1_ds_d <= wr_cam_data(66) when '1', + entry1_ds_q when others; +with wr_entry1_sel(1) select + entry1_pid_d <= wr_cam_data(67 to 74) when '1', + entry1_pid_q(0 to 7) when others; +with wr_entry1_sel(0) select + entry1_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry1_cmpmask_q when others; +-- the cam parity bits.. some wr_array_data bits contain parity for cam +with wr_entry1_sel(0) select + entry1_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry1_parity_q(0 to 3) when others; +with wr_entry1_sel(0) select + entry1_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry1_parity_q(4 to 6) when others; +with wr_entry1_sel(0) select + entry1_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry1_parity_q(7) when others; +with wr_entry1_sel(1) select + entry1_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry1_parity_q(8) when others; +with wr_entry1_sel(1) select + entry1_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry1_parity_q(9) when others; +wr_entry2_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="0010")) else '0'; +wr_entry2_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="0010")) else '0'; +with wr_entry2_sel(0) select + entry2_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry2_epn_q(0 to 31) when others; +with wr_entry2_sel(0) select + entry2_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry2_epn_q(32 to 51) when others; +with wr_entry2_sel(0) select + entry2_xbit_d <= wr_cam_data(52) when '1', + entry2_xbit_q when others; +with wr_entry2_sel(0) select + entry2_size_d <= wr_cam_data(53 to 55) when '1', + entry2_size_q(0 to 2) when others; +with wr_entry2_sel(0) select + entry2_class_d <= wr_cam_data(61 to 62) when '1', + entry2_class_q(0 to 1) when others; +with wr_entry2_sel(1) select + entry2_extclass_d <= wr_cam_data(63 to 64) when '1', + entry2_extclass_q(0 to 1) when others; +with wr_entry2_sel(1) select + entry2_hv_d <= wr_cam_data(65) when '1', + entry2_hv_q when others; +with wr_entry2_sel(1) select + entry2_ds_d <= wr_cam_data(66) when '1', + entry2_ds_q when others; +with wr_entry2_sel(1) select + entry2_pid_d <= wr_cam_data(67 to 74) when '1', + entry2_pid_q(0 to 7) when others; +with wr_entry2_sel(0) select + entry2_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry2_cmpmask_q when others; +-- the cam parity bits.. some wr_array_data bits contain parity for cam +with wr_entry2_sel(0) select + entry2_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry2_parity_q(0 to 3) when others; +with wr_entry2_sel(0) select + entry2_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry2_parity_q(4 to 6) when others; +with wr_entry2_sel(0) select + entry2_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry2_parity_q(7) when others; +with wr_entry2_sel(1) select + entry2_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry2_parity_q(8) when others; +with wr_entry2_sel(1) select + entry2_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry2_parity_q(9) when others; +wr_entry3_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="0011")) else '0'; +wr_entry3_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="0011")) else '0'; +with wr_entry3_sel(0) select + entry3_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry3_epn_q(0 to 31) when others; +with wr_entry3_sel(0) select + entry3_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry3_epn_q(32 to 51) when others; +with wr_entry3_sel(0) select + entry3_xbit_d <= wr_cam_data(52) when '1', + entry3_xbit_q when others; +with wr_entry3_sel(0) select + entry3_size_d <= wr_cam_data(53 to 55) when '1', + entry3_size_q(0 to 2) when others; +with wr_entry3_sel(0) select + entry3_class_d <= wr_cam_data(61 to 62) when '1', + entry3_class_q(0 to 1) when others; +with wr_entry3_sel(1) select + entry3_extclass_d <= wr_cam_data(63 to 64) when '1', + entry3_extclass_q(0 to 1) when others; +with wr_entry3_sel(1) select + entry3_hv_d <= wr_cam_data(65) when '1', + entry3_hv_q when others; +with wr_entry3_sel(1) select + entry3_ds_d <= wr_cam_data(66) when '1', + entry3_ds_q when others; +with wr_entry3_sel(1) select + entry3_pid_d <= wr_cam_data(67 to 74) when '1', + entry3_pid_q(0 to 7) when others; +with wr_entry3_sel(0) select + entry3_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry3_cmpmask_q when others; +-- the cam parity bits.. some wr_array_data bits contain parity for cam +with wr_entry3_sel(0) select + entry3_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry3_parity_q(0 to 3) when others; +with wr_entry3_sel(0) select + entry3_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry3_parity_q(4 to 6) when others; +with wr_entry3_sel(0) select + entry3_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry3_parity_q(7) when others; +with wr_entry3_sel(1) select + entry3_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry3_parity_q(8) when others; +with wr_entry3_sel(1) select + entry3_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry3_parity_q(9) when others; +wr_entry4_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="0100")) else '0'; +wr_entry4_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="0100")) else '0'; +with wr_entry4_sel(0) select + entry4_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry4_epn_q(0 to 31) when others; +with wr_entry4_sel(0) select + entry4_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry4_epn_q(32 to 51) when others; +with wr_entry4_sel(0) select + entry4_xbit_d <= wr_cam_data(52) when '1', + entry4_xbit_q when others; +with wr_entry4_sel(0) select + entry4_size_d <= wr_cam_data(53 to 55) when '1', + entry4_size_q(0 to 2) when others; +with wr_entry4_sel(0) select + entry4_class_d <= wr_cam_data(61 to 62) when '1', + entry4_class_q(0 to 1) when others; +with wr_entry4_sel(1) select + entry4_extclass_d <= wr_cam_data(63 to 64) when '1', + entry4_extclass_q(0 to 1) when others; +with wr_entry4_sel(1) select + entry4_hv_d <= wr_cam_data(65) when '1', + entry4_hv_q when others; +with wr_entry4_sel(1) select + entry4_ds_d <= wr_cam_data(66) when '1', + entry4_ds_q when others; +with wr_entry4_sel(1) select + entry4_pid_d <= wr_cam_data(67 to 74) when '1', + entry4_pid_q(0 to 7) when others; +with wr_entry4_sel(0) select + entry4_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry4_cmpmask_q when others; +-- the cam parity bits.. some wr_array_data bits contain parity for cam +with wr_entry4_sel(0) select + entry4_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry4_parity_q(0 to 3) when others; +with wr_entry4_sel(0) select + entry4_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry4_parity_q(4 to 6) when others; +with wr_entry4_sel(0) select + entry4_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry4_parity_q(7) when others; +with wr_entry4_sel(1) select + entry4_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry4_parity_q(8) when others; +with wr_entry4_sel(1) select + entry4_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry4_parity_q(9) when others; +wr_entry5_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="0101")) else '0'; +wr_entry5_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="0101")) else '0'; +with wr_entry5_sel(0) select + entry5_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry5_epn_q(0 to 31) when others; +with wr_entry5_sel(0) select + entry5_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry5_epn_q(32 to 51) when others; +with wr_entry5_sel(0) select + entry5_xbit_d <= wr_cam_data(52) when '1', + entry5_xbit_q when others; +with wr_entry5_sel(0) select + entry5_size_d <= wr_cam_data(53 to 55) when '1', + entry5_size_q(0 to 2) when others; +with wr_entry5_sel(0) select + entry5_class_d <= wr_cam_data(61 to 62) when '1', + entry5_class_q(0 to 1) when others; +with wr_entry5_sel(1) select + entry5_extclass_d <= wr_cam_data(63 to 64) when '1', + entry5_extclass_q(0 to 1) when others; +with wr_entry5_sel(1) select + entry5_hv_d <= wr_cam_data(65) when '1', + entry5_hv_q when others; +with wr_entry5_sel(1) select + entry5_ds_d <= wr_cam_data(66) when '1', + entry5_ds_q when others; +with wr_entry5_sel(1) select + entry5_pid_d <= wr_cam_data(67 to 74) when '1', + entry5_pid_q(0 to 7) when others; +with wr_entry5_sel(0) select + entry5_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry5_cmpmask_q when others; +-- the cam parity bits.. some wr_array_data bits contain parity for cam +with wr_entry5_sel(0) select + entry5_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry5_parity_q(0 to 3) when others; +with wr_entry5_sel(0) select + entry5_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry5_parity_q(4 to 6) when others; +with wr_entry5_sel(0) select + entry5_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry5_parity_q(7) when others; +with wr_entry5_sel(1) select + entry5_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry5_parity_q(8) when others; +with wr_entry5_sel(1) select + entry5_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry5_parity_q(9) when others; +wr_entry6_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="0110")) else '0'; +wr_entry6_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="0110")) else '0'; +with wr_entry6_sel(0) select + entry6_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry6_epn_q(0 to 31) when others; +with wr_entry6_sel(0) select + entry6_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry6_epn_q(32 to 51) when others; +with wr_entry6_sel(0) select + entry6_xbit_d <= wr_cam_data(52) when '1', + entry6_xbit_q when others; +with wr_entry6_sel(0) select + entry6_size_d <= wr_cam_data(53 to 55) when '1', + entry6_size_q(0 to 2) when others; +with wr_entry6_sel(0) select + entry6_class_d <= wr_cam_data(61 to 62) when '1', + entry6_class_q(0 to 1) when others; +with wr_entry6_sel(1) select + entry6_extclass_d <= wr_cam_data(63 to 64) when '1', + entry6_extclass_q(0 to 1) when others; +with wr_entry6_sel(1) select + entry6_hv_d <= wr_cam_data(65) when '1', + entry6_hv_q when others; +with wr_entry6_sel(1) select + entry6_ds_d <= wr_cam_data(66) when '1', + entry6_ds_q when others; +with wr_entry6_sel(1) select + entry6_pid_d <= wr_cam_data(67 to 74) when '1', + entry6_pid_q(0 to 7) when others; +with wr_entry6_sel(0) select + entry6_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry6_cmpmask_q when others; +-- the cam parity bits.. some wr_array_data bits contain parity for cam +with wr_entry6_sel(0) select + entry6_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry6_parity_q(0 to 3) when others; +with wr_entry6_sel(0) select + entry6_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry6_parity_q(4 to 6) when others; +with wr_entry6_sel(0) select + entry6_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry6_parity_q(7) when others; +with wr_entry6_sel(1) select + entry6_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry6_parity_q(8) when others; +with wr_entry6_sel(1) select + entry6_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry6_parity_q(9) when others; +wr_entry7_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="0111")) else '0'; +wr_entry7_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="0111")) else '0'; +with wr_entry7_sel(0) select + entry7_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry7_epn_q(0 to 31) when others; +with wr_entry7_sel(0) select + entry7_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry7_epn_q(32 to 51) when others; +with wr_entry7_sel(0) select + entry7_xbit_d <= wr_cam_data(52) when '1', + entry7_xbit_q when others; +with wr_entry7_sel(0) select + entry7_size_d <= wr_cam_data(53 to 55) when '1', + entry7_size_q(0 to 2) when others; +with wr_entry7_sel(0) select + entry7_class_d <= wr_cam_data(61 to 62) when '1', + entry7_class_q(0 to 1) when others; +with wr_entry7_sel(1) select + entry7_extclass_d <= wr_cam_data(63 to 64) when '1', + entry7_extclass_q(0 to 1) when others; +with wr_entry7_sel(1) select + entry7_hv_d <= wr_cam_data(65) when '1', + entry7_hv_q when others; +with wr_entry7_sel(1) select + entry7_ds_d <= wr_cam_data(66) when '1', + entry7_ds_q when others; +with wr_entry7_sel(1) select + entry7_pid_d <= wr_cam_data(67 to 74) when '1', + entry7_pid_q(0 to 7) when others; +with wr_entry7_sel(0) select + entry7_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry7_cmpmask_q when others; +-- the cam parity bits.. some wr_array_data bits contain parity for cam +with wr_entry7_sel(0) select + entry7_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry7_parity_q(0 to 3) when others; +with wr_entry7_sel(0) select + entry7_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry7_parity_q(4 to 6) when others; +with wr_entry7_sel(0) select + entry7_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry7_parity_q(7) when others; +with wr_entry7_sel(1) select + entry7_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry7_parity_q(8) when others; +with wr_entry7_sel(1) select + entry7_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry7_parity_q(9) when others; +wr_entry8_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="1000")) else '0'; +wr_entry8_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="1000")) else '0'; +with wr_entry8_sel(0) select + entry8_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry8_epn_q(0 to 31) when others; +with wr_entry8_sel(0) select + entry8_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry8_epn_q(32 to 51) when others; +with wr_entry8_sel(0) select + entry8_xbit_d <= wr_cam_data(52) when '1', + entry8_xbit_q when others; +with wr_entry8_sel(0) select + entry8_size_d <= wr_cam_data(53 to 55) when '1', + entry8_size_q(0 to 2) when others; +with wr_entry8_sel(0) select + entry8_class_d <= wr_cam_data(61 to 62) when '1', + entry8_class_q(0 to 1) when others; +with wr_entry8_sel(1) select + entry8_extclass_d <= wr_cam_data(63 to 64) when '1', + entry8_extclass_q(0 to 1) when others; +with wr_entry8_sel(1) select + entry8_hv_d <= wr_cam_data(65) when '1', + entry8_hv_q when others; +with wr_entry8_sel(1) select + entry8_ds_d <= wr_cam_data(66) when '1', + entry8_ds_q when others; +with wr_entry8_sel(1) select + entry8_pid_d <= wr_cam_data(67 to 74) when '1', + entry8_pid_q(0 to 7) when others; +with wr_entry8_sel(0) select + entry8_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry8_cmpmask_q when others; +-- the cam parity bits.. some wr_array_data bits contain parity for cam +with wr_entry8_sel(0) select + entry8_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry8_parity_q(0 to 3) when others; +with wr_entry8_sel(0) select + entry8_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry8_parity_q(4 to 6) when others; +with wr_entry8_sel(0) select + entry8_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry8_parity_q(7) when others; +with wr_entry8_sel(1) select + entry8_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry8_parity_q(8) when others; +with wr_entry8_sel(1) select + entry8_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry8_parity_q(9) when others; +wr_entry9_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="1001")) else '0'; +wr_entry9_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="1001")) else '0'; +with wr_entry9_sel(0) select + entry9_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry9_epn_q(0 to 31) when others; +with wr_entry9_sel(0) select + entry9_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry9_epn_q(32 to 51) when others; +with wr_entry9_sel(0) select + entry9_xbit_d <= wr_cam_data(52) when '1', + entry9_xbit_q when others; +with wr_entry9_sel(0) select + entry9_size_d <= wr_cam_data(53 to 55) when '1', + entry9_size_q(0 to 2) when others; +with wr_entry9_sel(0) select + entry9_class_d <= wr_cam_data(61 to 62) when '1', + entry9_class_q(0 to 1) when others; +with wr_entry9_sel(1) select + entry9_extclass_d <= wr_cam_data(63 to 64) when '1', + entry9_extclass_q(0 to 1) when others; +with wr_entry9_sel(1) select + entry9_hv_d <= wr_cam_data(65) when '1', + entry9_hv_q when others; +with wr_entry9_sel(1) select + entry9_ds_d <= wr_cam_data(66) when '1', + entry9_ds_q when others; +with wr_entry9_sel(1) select + entry9_pid_d <= wr_cam_data(67 to 74) when '1', + entry9_pid_q(0 to 7) when others; +with wr_entry9_sel(0) select + entry9_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry9_cmpmask_q when others; +-- the cam parity bits.. some wr_array_data bits contain parity for cam +with wr_entry9_sel(0) select + entry9_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry9_parity_q(0 to 3) when others; +with wr_entry9_sel(0) select + entry9_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry9_parity_q(4 to 6) when others; +with wr_entry9_sel(0) select + entry9_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry9_parity_q(7) when others; +with wr_entry9_sel(1) select + entry9_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry9_parity_q(8) when others; +with wr_entry9_sel(1) select + entry9_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry9_parity_q(9) when others; +wr_entry10_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="1010")) else '0'; +wr_entry10_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="1010")) else '0'; +with wr_entry10_sel(0) select + entry10_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry10_epn_q(0 to 31) when others; +with wr_entry10_sel(0) select + entry10_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry10_epn_q(32 to 51) when others; +with wr_entry10_sel(0) select + entry10_xbit_d <= wr_cam_data(52) when '1', + entry10_xbit_q when others; +with wr_entry10_sel(0) select + entry10_size_d <= wr_cam_data(53 to 55) when '1', + entry10_size_q(0 to 2) when others; +with wr_entry10_sel(0) select + entry10_class_d <= wr_cam_data(61 to 62) when '1', + entry10_class_q(0 to 1) when others; +with wr_entry10_sel(1) select + entry10_extclass_d <= wr_cam_data(63 to 64) when '1', + entry10_extclass_q(0 to 1) when others; +with wr_entry10_sel(1) select + entry10_hv_d <= wr_cam_data(65) when '1', + entry10_hv_q when others; +with wr_entry10_sel(1) select + entry10_ds_d <= wr_cam_data(66) when '1', + entry10_ds_q when others; +with wr_entry10_sel(1) select + entry10_pid_d <= wr_cam_data(67 to 74) when '1', + entry10_pid_q(0 to 7) when others; +with wr_entry10_sel(0) select + entry10_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry10_cmpmask_q when others; +-- the cam parity bits.. some wr_array_data bits contain parity for cam +with wr_entry10_sel(0) select + entry10_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry10_parity_q(0 to 3) when others; +with wr_entry10_sel(0) select + entry10_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry10_parity_q(4 to 6) when others; +with wr_entry10_sel(0) select + entry10_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry10_parity_q(7) when others; +with wr_entry10_sel(1) select + entry10_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry10_parity_q(8) when others; +with wr_entry10_sel(1) select + entry10_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry10_parity_q(9) when others; +wr_entry11_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="1011")) else '0'; +wr_entry11_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="1011")) else '0'; +with wr_entry11_sel(0) select + entry11_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry11_epn_q(0 to 31) when others; +with wr_entry11_sel(0) select + entry11_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry11_epn_q(32 to 51) when others; +with wr_entry11_sel(0) select + entry11_xbit_d <= wr_cam_data(52) when '1', + entry11_xbit_q when others; +with wr_entry11_sel(0) select + entry11_size_d <= wr_cam_data(53 to 55) when '1', + entry11_size_q(0 to 2) when others; +with wr_entry11_sel(0) select + entry11_class_d <= wr_cam_data(61 to 62) when '1', + entry11_class_q(0 to 1) when others; +with wr_entry11_sel(1) select + entry11_extclass_d <= wr_cam_data(63 to 64) when '1', + entry11_extclass_q(0 to 1) when others; +with wr_entry11_sel(1) select + entry11_hv_d <= wr_cam_data(65) when '1', + entry11_hv_q when others; +with wr_entry11_sel(1) select + entry11_ds_d <= wr_cam_data(66) when '1', + entry11_ds_q when others; +with wr_entry11_sel(1) select + entry11_pid_d <= wr_cam_data(67 to 74) when '1', + entry11_pid_q(0 to 7) when others; +with wr_entry11_sel(0) select + entry11_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry11_cmpmask_q when others; +-- the cam parity bits.. some wr_array_data bits contain parity for cam +with wr_entry11_sel(0) select + entry11_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry11_parity_q(0 to 3) when others; +with wr_entry11_sel(0) select + entry11_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry11_parity_q(4 to 6) when others; +with wr_entry11_sel(0) select + entry11_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry11_parity_q(7) when others; +with wr_entry11_sel(1) select + entry11_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry11_parity_q(8) when others; +with wr_entry11_sel(1) select + entry11_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry11_parity_q(9) when others; +wr_entry12_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="1100")) else '0'; +wr_entry12_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="1100")) else '0'; +with wr_entry12_sel(0) select + entry12_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry12_epn_q(0 to 31) when others; +with wr_entry12_sel(0) select + entry12_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry12_epn_q(32 to 51) when others; +with wr_entry12_sel(0) select + entry12_xbit_d <= wr_cam_data(52) when '1', + entry12_xbit_q when others; +with wr_entry12_sel(0) select + entry12_size_d <= wr_cam_data(53 to 55) when '1', + entry12_size_q(0 to 2) when others; +with wr_entry12_sel(0) select + entry12_class_d <= wr_cam_data(61 to 62) when '1', + entry12_class_q(0 to 1) when others; +with wr_entry12_sel(1) select + entry12_extclass_d <= wr_cam_data(63 to 64) when '1', + entry12_extclass_q(0 to 1) when others; +with wr_entry12_sel(1) select + entry12_hv_d <= wr_cam_data(65) when '1', + entry12_hv_q when others; +with wr_entry12_sel(1) select + entry12_ds_d <= wr_cam_data(66) when '1', + entry12_ds_q when others; +with wr_entry12_sel(1) select + entry12_pid_d <= wr_cam_data(67 to 74) when '1', + entry12_pid_q(0 to 7) when others; +with wr_entry12_sel(0) select + entry12_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry12_cmpmask_q when others; +-- the cam parity bits.. some wr_array_data bits contain parity for cam +with wr_entry12_sel(0) select + entry12_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry12_parity_q(0 to 3) when others; +with wr_entry12_sel(0) select + entry12_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry12_parity_q(4 to 6) when others; +with wr_entry12_sel(0) select + entry12_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry12_parity_q(7) when others; +with wr_entry12_sel(1) select + entry12_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry12_parity_q(8) when others; +with wr_entry12_sel(1) select + entry12_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry12_parity_q(9) when others; +wr_entry13_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="1101")) else '0'; +wr_entry13_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="1101")) else '0'; +with wr_entry13_sel(0) select + entry13_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry13_epn_q(0 to 31) when others; +with wr_entry13_sel(0) select + entry13_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry13_epn_q(32 to 51) when others; +with wr_entry13_sel(0) select + entry13_xbit_d <= wr_cam_data(52) when '1', + entry13_xbit_q when others; +with wr_entry13_sel(0) select + entry13_size_d <= wr_cam_data(53 to 55) when '1', + entry13_size_q(0 to 2) when others; +with wr_entry13_sel(0) select + entry13_class_d <= wr_cam_data(61 to 62) when '1', + entry13_class_q(0 to 1) when others; +with wr_entry13_sel(1) select + entry13_extclass_d <= wr_cam_data(63 to 64) when '1', + entry13_extclass_q(0 to 1) when others; +with wr_entry13_sel(1) select + entry13_hv_d <= wr_cam_data(65) when '1', + entry13_hv_q when others; +with wr_entry13_sel(1) select + entry13_ds_d <= wr_cam_data(66) when '1', + entry13_ds_q when others; +with wr_entry13_sel(1) select + entry13_pid_d <= wr_cam_data(67 to 74) when '1', + entry13_pid_q(0 to 7) when others; +with wr_entry13_sel(0) select + entry13_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry13_cmpmask_q when others; +-- the cam parity bits.. some wr_array_data bits contain parity for cam +with wr_entry13_sel(0) select + entry13_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry13_parity_q(0 to 3) when others; +with wr_entry13_sel(0) select + entry13_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry13_parity_q(4 to 6) when others; +with wr_entry13_sel(0) select + entry13_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry13_parity_q(7) when others; +with wr_entry13_sel(1) select + entry13_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry13_parity_q(8) when others; +with wr_entry13_sel(1) select + entry13_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry13_parity_q(9) when others; +wr_entry14_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="1110")) else '0'; +wr_entry14_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="1110")) else '0'; +with wr_entry14_sel(0) select + entry14_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry14_epn_q(0 to 31) when others; +with wr_entry14_sel(0) select + entry14_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry14_epn_q(32 to 51) when others; +with wr_entry14_sel(0) select + entry14_xbit_d <= wr_cam_data(52) when '1', + entry14_xbit_q when others; +with wr_entry14_sel(0) select + entry14_size_d <= wr_cam_data(53 to 55) when '1', + entry14_size_q(0 to 2) when others; +with wr_entry14_sel(0) select + entry14_class_d <= wr_cam_data(61 to 62) when '1', + entry14_class_q(0 to 1) when others; +with wr_entry14_sel(1) select + entry14_extclass_d <= wr_cam_data(63 to 64) when '1', + entry14_extclass_q(0 to 1) when others; +with wr_entry14_sel(1) select + entry14_hv_d <= wr_cam_data(65) when '1', + entry14_hv_q when others; +with wr_entry14_sel(1) select + entry14_ds_d <= wr_cam_data(66) when '1', + entry14_ds_q when others; +with wr_entry14_sel(1) select + entry14_pid_d <= wr_cam_data(67 to 74) when '1', + entry14_pid_q(0 to 7) when others; +with wr_entry14_sel(0) select + entry14_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry14_cmpmask_q when others; +-- the cam parity bits.. some wr_array_data bits contain parity for cam +with wr_entry14_sel(0) select + entry14_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry14_parity_q(0 to 3) when others; +with wr_entry14_sel(0) select + entry14_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry14_parity_q(4 to 6) when others; +with wr_entry14_sel(0) select + entry14_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry14_parity_q(7) when others; +with wr_entry14_sel(1) select + entry14_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry14_parity_q(8) when others; +with wr_entry14_sel(1) select + entry14_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry14_parity_q(9) when others; +wr_entry15_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="1111")) else '0'; +wr_entry15_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="1111")) else '0'; +with wr_entry15_sel(0) select + entry15_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry15_epn_q(0 to 31) when others; +with wr_entry15_sel(0) select + entry15_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry15_epn_q(32 to 51) when others; +with wr_entry15_sel(0) select + entry15_xbit_d <= wr_cam_data(52) when '1', + entry15_xbit_q when others; +with wr_entry15_sel(0) select + entry15_size_d <= wr_cam_data(53 to 55) when '1', + entry15_size_q(0 to 2) when others; +with wr_entry15_sel(0) select + entry15_class_d <= wr_cam_data(61 to 62) when '1', + entry15_class_q(0 to 1) when others; +with wr_entry15_sel(1) select + entry15_extclass_d <= wr_cam_data(63 to 64) when '1', + entry15_extclass_q(0 to 1) when others; +with wr_entry15_sel(1) select + entry15_hv_d <= wr_cam_data(65) when '1', + entry15_hv_q when others; +with wr_entry15_sel(1) select + entry15_ds_d <= wr_cam_data(66) when '1', + entry15_ds_q when others; +with wr_entry15_sel(1) select + entry15_pid_d <= wr_cam_data(67 to 74) when '1', + entry15_pid_q(0 to 7) when others; +with wr_entry15_sel(0) select + entry15_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry15_cmpmask_q when others; +-- the cam parity bits.. some wr_array_data bits contain parity for cam +with wr_entry15_sel(0) select + entry15_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry15_parity_q(0 to 3) when others; +with wr_entry15_sel(0) select + entry15_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry15_parity_q(4 to 6) when others; +with wr_entry15_sel(0) select + entry15_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry15_parity_q(7) when others; +with wr_entry15_sel(1) select + entry15_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry15_parity_q(8) when others; +with wr_entry15_sel(1) select + entry15_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry15_parity_q(9) when others; +-- entry valid and thdid next state logic +entry0_inval <= (comp_invalidate and match_vec(0)) or flash_invalidate; +entry0_v_muxsel(0 to 1) <= (entry0_inval & wr_entry0_sel(0)); +with entry0_v_muxsel(0 to 1) select + entry0_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry0_v_q when others; +with wr_entry0_sel(0) select + entry0_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry0_thdid_q(0 to 3) when others; +entry1_inval <= (comp_invalidate and match_vec(1)) or flash_invalidate; +entry1_v_muxsel(0 to 1) <= (entry1_inval & wr_entry1_sel(0)); +with entry1_v_muxsel(0 to 1) select + entry1_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry1_v_q when others; +with wr_entry1_sel(0) select + entry1_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry1_thdid_q(0 to 3) when others; +entry2_inval <= (comp_invalidate and match_vec(2)) or flash_invalidate; +entry2_v_muxsel(0 to 1) <= (entry2_inval & wr_entry2_sel(0)); +with entry2_v_muxsel(0 to 1) select + entry2_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry2_v_q when others; +with wr_entry2_sel(0) select + entry2_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry2_thdid_q(0 to 3) when others; +entry3_inval <= (comp_invalidate and match_vec(3)) or flash_invalidate; +entry3_v_muxsel(0 to 1) <= (entry3_inval & wr_entry3_sel(0)); +with entry3_v_muxsel(0 to 1) select + entry3_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry3_v_q when others; +with wr_entry3_sel(0) select + entry3_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry3_thdid_q(0 to 3) when others; +entry4_inval <= (comp_invalidate and match_vec(4)) or flash_invalidate; +entry4_v_muxsel(0 to 1) <= (entry4_inval & wr_entry4_sel(0)); +with entry4_v_muxsel(0 to 1) select + entry4_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry4_v_q when others; +with wr_entry4_sel(0) select + entry4_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry4_thdid_q(0 to 3) when others; +entry5_inval <= (comp_invalidate and match_vec(5)) or flash_invalidate; +entry5_v_muxsel(0 to 1) <= (entry5_inval & wr_entry5_sel(0)); +with entry5_v_muxsel(0 to 1) select + entry5_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry5_v_q when others; +with wr_entry5_sel(0) select + entry5_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry5_thdid_q(0 to 3) when others; +entry6_inval <= (comp_invalidate and match_vec(6)) or flash_invalidate; +entry6_v_muxsel(0 to 1) <= (entry6_inval & wr_entry6_sel(0)); +with entry6_v_muxsel(0 to 1) select + entry6_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry6_v_q when others; +with wr_entry6_sel(0) select + entry6_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry6_thdid_q(0 to 3) when others; +entry7_inval <= (comp_invalidate and match_vec(7)) or flash_invalidate; +entry7_v_muxsel(0 to 1) <= (entry7_inval & wr_entry7_sel(0)); +with entry7_v_muxsel(0 to 1) select + entry7_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry7_v_q when others; +with wr_entry7_sel(0) select + entry7_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry7_thdid_q(0 to 3) when others; +entry8_inval <= (comp_invalidate and match_vec(8)) or flash_invalidate; +entry8_v_muxsel(0 to 1) <= (entry8_inval & wr_entry8_sel(0)); +with entry8_v_muxsel(0 to 1) select + entry8_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry8_v_q when others; +with wr_entry8_sel(0) select + entry8_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry8_thdid_q(0 to 3) when others; +entry9_inval <= (comp_invalidate and match_vec(9)) or flash_invalidate; +entry9_v_muxsel(0 to 1) <= (entry9_inval & wr_entry9_sel(0)); +with entry9_v_muxsel(0 to 1) select + entry9_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry9_v_q when others; +with wr_entry9_sel(0) select + entry9_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry9_thdid_q(0 to 3) when others; +entry10_inval <= (comp_invalidate and match_vec(10)) or flash_invalidate; +entry10_v_muxsel(0 to 1) <= (entry10_inval & wr_entry10_sel(0)); +with entry10_v_muxsel(0 to 1) select + entry10_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry10_v_q when others; +with wr_entry10_sel(0) select + entry10_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry10_thdid_q(0 to 3) when others; +entry11_inval <= (comp_invalidate and match_vec(11)) or flash_invalidate; +entry11_v_muxsel(0 to 1) <= (entry11_inval & wr_entry11_sel(0)); +with entry11_v_muxsel(0 to 1) select + entry11_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry11_v_q when others; +with wr_entry11_sel(0) select + entry11_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry11_thdid_q(0 to 3) when others; +entry12_inval <= (comp_invalidate and match_vec(12)) or flash_invalidate; +entry12_v_muxsel(0 to 1) <= (entry12_inval & wr_entry12_sel(0)); +with entry12_v_muxsel(0 to 1) select + entry12_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry12_v_q when others; +with wr_entry12_sel(0) select + entry12_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry12_thdid_q(0 to 3) when others; +entry13_inval <= (comp_invalidate and match_vec(13)) or flash_invalidate; +entry13_v_muxsel(0 to 1) <= (entry13_inval & wr_entry13_sel(0)); +with entry13_v_muxsel(0 to 1) select + entry13_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry13_v_q when others; +with wr_entry13_sel(0) select + entry13_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry13_thdid_q(0 to 3) when others; +entry14_inval <= (comp_invalidate and match_vec(14)) or flash_invalidate; +entry14_v_muxsel(0 to 1) <= (entry14_inval & wr_entry14_sel(0)); +with entry14_v_muxsel(0 to 1) select + entry14_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry14_v_q when others; +with wr_entry14_sel(0) select + entry14_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry14_thdid_q(0 to 3) when others; +entry15_inval <= (comp_invalidate and match_vec(15)) or flash_invalidate; +entry15_v_muxsel(0 to 1) <= (entry15_inval & wr_entry15_sel(0)); +with entry15_v_muxsel(0 to 1) select + entry15_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry15_v_q when others; +with wr_entry15_sel(0) select + entry15_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry15_thdid_q(0 to 3) when others; +-- CAM compare data out mux +entry0_cam_vec <= entry0_epn_q & entry0_xbit_q & entry0_size_q & entry0_v_q & entry0_thdid_q & + entry0_class_q & entry0_extclass_q & entry0_hv_q & entry0_ds_q & entry0_pid_q & entry0_cmpmask_q; +entry1_cam_vec <= entry1_epn_q & entry1_xbit_q & entry1_size_q & entry1_v_q & entry1_thdid_q & + entry1_class_q & entry1_extclass_q & entry1_hv_q & entry1_ds_q & entry1_pid_q & entry1_cmpmask_q; +entry2_cam_vec <= entry2_epn_q & entry2_xbit_q & entry2_size_q & entry2_v_q & entry2_thdid_q & + entry2_class_q & entry2_extclass_q & entry2_hv_q & entry2_ds_q & entry2_pid_q & entry2_cmpmask_q; +entry3_cam_vec <= entry3_epn_q & entry3_xbit_q & entry3_size_q & entry3_v_q & entry3_thdid_q & + entry3_class_q & entry3_extclass_q & entry3_hv_q & entry3_ds_q & entry3_pid_q & entry3_cmpmask_q; +entry4_cam_vec <= entry4_epn_q & entry4_xbit_q & entry4_size_q & entry4_v_q & entry4_thdid_q & + entry4_class_q & entry4_extclass_q & entry4_hv_q & entry4_ds_q & entry4_pid_q & entry4_cmpmask_q; +entry5_cam_vec <= entry5_epn_q & entry5_xbit_q & entry5_size_q & entry5_v_q & entry5_thdid_q & + entry5_class_q & entry5_extclass_q & entry5_hv_q & entry5_ds_q & entry5_pid_q & entry5_cmpmask_q; +entry6_cam_vec <= entry6_epn_q & entry6_xbit_q & entry6_size_q & entry6_v_q & entry6_thdid_q & + entry6_class_q & entry6_extclass_q & entry6_hv_q & entry6_ds_q & entry6_pid_q & entry6_cmpmask_q; +entry7_cam_vec <= entry7_epn_q & entry7_xbit_q & entry7_size_q & entry7_v_q & entry7_thdid_q & + entry7_class_q & entry7_extclass_q & entry7_hv_q & entry7_ds_q & entry7_pid_q & entry7_cmpmask_q; +entry8_cam_vec <= entry8_epn_q & entry8_xbit_q & entry8_size_q & entry8_v_q & entry8_thdid_q & + entry8_class_q & entry8_extclass_q & entry8_hv_q & entry8_ds_q & entry8_pid_q & entry8_cmpmask_q; +entry9_cam_vec <= entry9_epn_q & entry9_xbit_q & entry9_size_q & entry9_v_q & entry9_thdid_q & + entry9_class_q & entry9_extclass_q & entry9_hv_q & entry9_ds_q & entry9_pid_q & entry9_cmpmask_q; +entry10_cam_vec <= entry10_epn_q & entry10_xbit_q & entry10_size_q & entry10_v_q & entry10_thdid_q & + entry10_class_q & entry10_extclass_q & entry10_hv_q & entry10_ds_q & entry10_pid_q & entry10_cmpmask_q; +entry11_cam_vec <= entry11_epn_q & entry11_xbit_q & entry11_size_q & entry11_v_q & entry11_thdid_q & + entry11_class_q & entry11_extclass_q & entry11_hv_q & entry11_ds_q & entry11_pid_q & entry11_cmpmask_q; +entry12_cam_vec <= entry12_epn_q & entry12_xbit_q & entry12_size_q & entry12_v_q & entry12_thdid_q & + entry12_class_q & entry12_extclass_q & entry12_hv_q & entry12_ds_q & entry12_pid_q & entry12_cmpmask_q; +entry13_cam_vec <= entry13_epn_q & entry13_xbit_q & entry13_size_q & entry13_v_q & entry13_thdid_q & + entry13_class_q & entry13_extclass_q & entry13_hv_q & entry13_ds_q & entry13_pid_q & entry13_cmpmask_q; +entry14_cam_vec <= entry14_epn_q & entry14_xbit_q & entry14_size_q & entry14_v_q & entry14_thdid_q & + entry14_class_q & entry14_extclass_q & entry14_hv_q & entry14_ds_q & entry14_pid_q & entry14_cmpmask_q; +entry15_cam_vec <= entry15_epn_q & entry15_xbit_q & entry15_size_q & entry15_v_q & entry15_thdid_q & + entry15_class_q & entry15_extclass_q & entry15_hv_q & entry15_ds_q & entry15_pid_q & entry15_cmpmask_q; +cam_cmp_data_muxsel <= not(comp_request) & cam_hit_entry_d; +with cam_cmp_data_muxsel select + cam_cmp_data_d <= entry0_cam_vec when "00000", + entry1_cam_vec when "00001", + entry2_cam_vec when "00010", + entry3_cam_vec when "00011", + entry4_cam_vec when "00100", + entry5_cam_vec when "00101", + entry6_cam_vec when "00110", + entry7_cam_vec when "00111", + entry8_cam_vec when "01000", + entry9_cam_vec when "01001", + entry10_cam_vec when "01010", + entry11_cam_vec when "01011", + entry12_cam_vec when "01100", + entry13_cam_vec when "01101", + entry14_cam_vec when "01110", + entry15_cam_vec when "01111", + cam_cmp_data_q when others; +cam_cmp_data_np1 <= cam_cmp_data_q; +-- CAM read data out mux +rd_cam_data_muxsel <= not(rd_val) & rw_entry; +with rd_cam_data_muxsel select + rd_cam_data_d <= entry0_cam_vec when "00000", + entry1_cam_vec when "00001", + entry2_cam_vec when "00010", + entry3_cam_vec when "00011", + entry4_cam_vec when "00100", + entry5_cam_vec when "00101", + entry6_cam_vec when "00110", + entry7_cam_vec when "00111", + entry8_cam_vec when "01000", + entry9_cam_vec when "01001", + entry10_cam_vec when "01010", + entry11_cam_vec when "01011", + entry12_cam_vec when "01100", + entry13_cam_vec when "01101", + entry14_cam_vec when "01110", + entry15_cam_vec when "01111", + rd_cam_data_q when others; +-- CAM compare parity out mux +with cam_cmp_data_muxsel select + cam_cmp_parity_d <= entry0_parity_q when "00000", + entry1_parity_q when "00001", + entry2_parity_q when "00010", + entry3_parity_q when "00011", + entry4_parity_q when "00100", + entry5_parity_q when "00101", + entry6_parity_q when "00110", + entry7_parity_q when "00111", + entry8_parity_q when "01000", + entry9_parity_q when "01001", + entry10_parity_q when "01010", + entry11_parity_q when "01011", + entry12_parity_q when "01100", + entry13_parity_q when "01101", + entry14_parity_q when "01110", + entry15_parity_q when "01111", + cam_cmp_parity_q when others; +array_cmp_data_np1(0 to 50) <= array_cmp_data_bram(2 to 31) & array_cmp_data_bram(34 to 39) & array_cmp_data_bram(41 to 55); +array_cmp_data_np1(51 to 60) <= cam_cmp_parity_q; +array_cmp_data_np1(61 to 67) <= array_cmp_data_bramp(66 to 72); +array_cmp_data <= array_cmp_data_np1; +with rd_cam_data_muxsel select + rd_array_data_d(51 to 60) <= entry0_parity_q when "00000", + entry1_parity_q when "00001", + entry2_parity_q when "00010", + entry3_parity_q when "00011", + entry4_parity_q when "00100", + entry5_parity_q when "00101", + entry6_parity_q when "00110", + entry7_parity_q when "00111", + entry8_parity_q when "01000", + entry9_parity_q when "01001", + entry10_parity_q when "01010", + entry11_parity_q when "01011", + entry12_parity_q when "01100", + entry13_parity_q when "01101", + entry14_parity_q when "01110", + entry15_parity_q when "01111", + rd_array_data_q(51 to 60) when others; +rpn_np2_d(22 to 33) <= ( comp_addr_np1_q(22 to 33) and (22 to 33 => bypass_mux_enab_np1 ) ) or + ( array_cmp_data_np1(0 to 11) and (0 to 11 => not(bypass_mux_enab_np1)) ); +rpn_np2_d(34 to 39) <= ( comp_addr_np1_q(34 to 39) and (34 to 39 => (not(cam_cmp_data_np1(75)) or bypass_mux_enab_np1)) ) or + ( array_cmp_data_np1(12 to 17) and (12 to 17 => (cam_cmp_data_np1(75) and not bypass_mux_enab_np1)) ); +rpn_np2_d(40 to 43) <= ( comp_addr_np1_q(40 to 43) and (40 to 43 => (not(cam_cmp_data_np1(76)) or bypass_mux_enab_np1)) ) or + ( array_cmp_data_np1(18 to 21) and (18 to 21 => (cam_cmp_data_np1(76) and not bypass_mux_enab_np1)) ); +rpn_np2_d(44 to 47) <= ( comp_addr_np1_q(44 to 47) and (44 to 47 => (not(cam_cmp_data_np1(77)) or bypass_mux_enab_np1)) ) or + ( array_cmp_data_np1(22 to 25) and (22 to 25 => (cam_cmp_data_np1(77) and not bypass_mux_enab_np1)) ); +rpn_np2_d(48 to 51) <= ( comp_addr_np1_q(48 to 51) and (48 to 51 => (not(cam_cmp_data_np1(78)) or bypass_mux_enab_np1)) ) or + ( array_cmp_data_np1(26 to 29) and (26 to 29 => (cam_cmp_data_np1(78) and not bypass_mux_enab_np1)) ); +attr_np2_d(0 to 20) <= ( bypass_attr_np1(0 to 20) and (0 to 20 => bypass_mux_enab_np1) ) or + ( array_cmp_data_np1(30 to 50) and (30 to 50 => not bypass_mux_enab_np1) ); +rpn_np2(22 to 51) <= rpn_np2_q(22 to 51); +attr_np2(0 to 20) <= attr_np2_q(0 to 20); +----------------------------------------------------------------------- +-- matchline component instantiations +----------------------------------------------------------------------- +matchline_comb0 : tri_cam_16x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry0_size_q, + entry_cmpmask => entry0_cmpmask_q(0 to 3), + entry_xbit => entry0_xbit_q, + entry_xbitmask => entry0_cmpmask_q(4 to 7), + entry_epn => entry0_epn_q, + comp_class => comp_class, + entry_class => entry0_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry0_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry0_hv_q, + entry_ds => entry0_ds_q, + state_enable => state_enable, + entry_thdid => entry0_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry0_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry0_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(0) + ); +matchline_comb1 : tri_cam_16x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry1_size_q, + entry_cmpmask => entry1_cmpmask_q(0 to 3), + entry_xbit => entry1_xbit_q, + entry_xbitmask => entry1_cmpmask_q(4 to 7), + entry_epn => entry1_epn_q, + comp_class => comp_class, + entry_class => entry1_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry1_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry1_hv_q, + entry_ds => entry1_ds_q, + state_enable => state_enable, + entry_thdid => entry1_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry1_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry1_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(1) + ); +matchline_comb2 : tri_cam_16x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry2_size_q, + entry_cmpmask => entry2_cmpmask_q(0 to 3), + entry_xbit => entry2_xbit_q, + entry_xbitmask => entry2_cmpmask_q(4 to 7), + entry_epn => entry2_epn_q, + comp_class => comp_class, + entry_class => entry2_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry2_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry2_hv_q, + entry_ds => entry2_ds_q, + state_enable => state_enable, + entry_thdid => entry2_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry2_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry2_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(2) + ); +matchline_comb3 : tri_cam_16x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry3_size_q, + entry_cmpmask => entry3_cmpmask_q(0 to 3), + entry_xbit => entry3_xbit_q, + entry_xbitmask => entry3_cmpmask_q(4 to 7), + entry_epn => entry3_epn_q, + comp_class => comp_class, + entry_class => entry3_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry3_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry3_hv_q, + entry_ds => entry3_ds_q, + state_enable => state_enable, + entry_thdid => entry3_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry3_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry3_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(3) + ); +matchline_comb4 : tri_cam_16x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry4_size_q, + entry_cmpmask => entry4_cmpmask_q(0 to 3), + entry_xbit => entry4_xbit_q, + entry_xbitmask => entry4_cmpmask_q(4 to 7), + entry_epn => entry4_epn_q, + comp_class => comp_class, + entry_class => entry4_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry4_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry4_hv_q, + entry_ds => entry4_ds_q, + state_enable => state_enable, + entry_thdid => entry4_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry4_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry4_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(4) + ); +matchline_comb5 : tri_cam_16x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry5_size_q, + entry_cmpmask => entry5_cmpmask_q(0 to 3), + entry_xbit => entry5_xbit_q, + entry_xbitmask => entry5_cmpmask_q(4 to 7), + entry_epn => entry5_epn_q, + comp_class => comp_class, + entry_class => entry5_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry5_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry5_hv_q, + entry_ds => entry5_ds_q, + state_enable => state_enable, + entry_thdid => entry5_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry5_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry5_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(5) + ); +matchline_comb6 : tri_cam_16x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry6_size_q, + entry_cmpmask => entry6_cmpmask_q(0 to 3), + entry_xbit => entry6_xbit_q, + entry_xbitmask => entry6_cmpmask_q(4 to 7), + entry_epn => entry6_epn_q, + comp_class => comp_class, + entry_class => entry6_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry6_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry6_hv_q, + entry_ds => entry6_ds_q, + state_enable => state_enable, + entry_thdid => entry6_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry6_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry6_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(6) + ); +matchline_comb7 : tri_cam_16x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry7_size_q, + entry_cmpmask => entry7_cmpmask_q(0 to 3), + entry_xbit => entry7_xbit_q, + entry_xbitmask => entry7_cmpmask_q(4 to 7), + entry_epn => entry7_epn_q, + comp_class => comp_class, + entry_class => entry7_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry7_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry7_hv_q, + entry_ds => entry7_ds_q, + state_enable => state_enable, + entry_thdid => entry7_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry7_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry7_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(7) + ); +matchline_comb8 : tri_cam_16x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry8_size_q, + entry_cmpmask => entry8_cmpmask_q(0 to 3), + entry_xbit => entry8_xbit_q, + entry_xbitmask => entry8_cmpmask_q(4 to 7), + entry_epn => entry8_epn_q, + comp_class => comp_class, + entry_class => entry8_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry8_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry8_hv_q, + entry_ds => entry8_ds_q, + state_enable => state_enable, + entry_thdid => entry8_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry8_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry8_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(8) + ); +matchline_comb9 : tri_cam_16x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry9_size_q, + entry_cmpmask => entry9_cmpmask_q(0 to 3), + entry_xbit => entry9_xbit_q, + entry_xbitmask => entry9_cmpmask_q(4 to 7), + entry_epn => entry9_epn_q, + comp_class => comp_class, + entry_class => entry9_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry9_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry9_hv_q, + entry_ds => entry9_ds_q, + state_enable => state_enable, + entry_thdid => entry9_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry9_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry9_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(9) + ); +matchline_comb10 : tri_cam_16x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry10_size_q, + entry_cmpmask => entry10_cmpmask_q(0 to 3), + entry_xbit => entry10_xbit_q, + entry_xbitmask => entry10_cmpmask_q(4 to 7), + entry_epn => entry10_epn_q, + comp_class => comp_class, + entry_class => entry10_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry10_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry10_hv_q, + entry_ds => entry10_ds_q, + state_enable => state_enable, + entry_thdid => entry10_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry10_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry10_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(10) + ); +matchline_comb11 : tri_cam_16x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry11_size_q, + entry_cmpmask => entry11_cmpmask_q(0 to 3), + entry_xbit => entry11_xbit_q, + entry_xbitmask => entry11_cmpmask_q(4 to 7), + entry_epn => entry11_epn_q, + comp_class => comp_class, + entry_class => entry11_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry11_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry11_hv_q, + entry_ds => entry11_ds_q, + state_enable => state_enable, + entry_thdid => entry11_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry11_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry11_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(11) + ); +matchline_comb12 : tri_cam_16x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry12_size_q, + entry_cmpmask => entry12_cmpmask_q(0 to 3), + entry_xbit => entry12_xbit_q, + entry_xbitmask => entry12_cmpmask_q(4 to 7), + entry_epn => entry12_epn_q, + comp_class => comp_class, + entry_class => entry12_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry12_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry12_hv_q, + entry_ds => entry12_ds_q, + state_enable => state_enable, + entry_thdid => entry12_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry12_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry12_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(12) + ); +matchline_comb13 : tri_cam_16x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry13_size_q, + entry_cmpmask => entry13_cmpmask_q(0 to 3), + entry_xbit => entry13_xbit_q, + entry_xbitmask => entry13_cmpmask_q(4 to 7), + entry_epn => entry13_epn_q, + comp_class => comp_class, + entry_class => entry13_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry13_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry13_hv_q, + entry_ds => entry13_ds_q, + state_enable => state_enable, + entry_thdid => entry13_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry13_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry13_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(13) + ); +matchline_comb14 : tri_cam_16x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry14_size_q, + entry_cmpmask => entry14_cmpmask_q(0 to 3), + entry_xbit => entry14_xbit_q, + entry_xbitmask => entry14_cmpmask_q(4 to 7), + entry_epn => entry14_epn_q, + comp_class => comp_class, + entry_class => entry14_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry14_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry14_hv_q, + entry_ds => entry14_ds_q, + state_enable => state_enable, + entry_thdid => entry14_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry14_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry14_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(14) + ); +matchline_comb15 : tri_cam_16x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry15_size_q, + entry_cmpmask => entry15_cmpmask_q(0 to 3), + entry_xbit => entry15_xbit_q, + entry_xbitmask => entry15_cmpmask_q(4 to 7), + entry_epn => entry15_epn_q, + comp_class => comp_class, + entry_class => entry15_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry15_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry15_hv_q, + entry_ds => entry15_ds_q, + state_enable => state_enable, + entry_thdid => entry15_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry15_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry15_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(15) + ); +----------------------------------------------------------------------- +-- BRAM signal assignments +----------------------------------------------------------------------- +bram0_wea <= wr_array_val(0) and gate_fq; +bram1_wea <= wr_array_val(1) and gate_fq; +bram2_wea <= wr_array_val(1) and gate_fq; +bram0_addra(9-num_entry_log2 to 8) <= rw_entry(0 to num_entry_log2-1); +bram1_addra(11-num_entry_log2 to 10) <= rw_entry(0 to num_entry_log2-1); +bram2_addra(10-num_entry_log2 to 9) <= rw_entry(0 to num_entry_log2-1); +bram0_addrb(9-num_entry_log2 to 8) <= cam_hit_entry_q; +bram1_addrb(11-num_entry_log2 to 10) <= cam_hit_entry_q; +bram2_addrb(10-num_entry_log2 to 9) <= cam_hit_entry_q; +-- Unused Address Bits +bram0_addra(0 to 8-num_entry_log2) <= (others => '0'); +bram0_addrb(0 to 8-num_entry_log2) <= (others => '0'); +bram1_addra(0 to 10-num_entry_log2) <= (others => '0'); +bram1_addrb(0 to 10-num_entry_log2) <= (others => '0'); +bram2_addra(0 to 9-num_entry_log2) <= (others => '0'); +bram2_addrb(0 to 9-num_entry_log2) <= (others => '0'); +-- This ram houses the RPN(20:51) bits, wr_array_data_bram(0:31) +-- uses wr_array_val(0), parity is wr_array_data_bram(66:69) +bram0 : ramb16_s36_s36 + +-- pragma translate_off +generic map( + +-- all, none, warning_only, generate_x_only +sim_collision_check => "none") + +-- pragma translate_on +port map( + clka => clk2x, + clkb => clk2x, + ssra => sreset_q, + ssrb => sreset_q, + addra => std_logic_vector(bram0_addra), + addrb => std_logic_vector(bram0_addrb), + dia => std_logic_vector(wr_array_data_bram(0 to 31)), + dib => (others => '0'), + doa => rd_array_data_d_std(0 to 31), + dob => array_cmp_data_bram_std(0 to 31), + dopa => rd_array_data_d_std(66 to 69), + dopb => array_cmp_data_bramp_std(66 to 69), + dipa => std_logic_vector(wr_array_data_bram(66 to 69)), + dipb => (others => '0'), + ena => '1', + enb => '1', + wea => bram0_wea, + web => '0' + ); +-- This ram houses the RPN(18:19),R,C,4xResv bits, wr_array_data_bram(32:39) +-- uses wr_array_val(1), parity is wr_array_data_bram(70) +bram1 : ramb16_s9_s9 + +-- pragma translate_off +generic map( + +-- all, none, warning_only, generate_x_only +sim_collision_check => "none") + +-- pragma translate_on +port map( + clka => clk2x, + clkb => clk2x, + ssra => sreset_q, + ssrb => sreset_q, + addra => std_logic_vector(bram1_addra), + addrb => std_logic_vector(bram1_addrb), + dia => std_logic_vector(wr_array_data_bram(32 to 39)), + dib => (others => '0'), + doa => rd_array_data_d_std(32 to 39), + dob => array_cmp_data_bram_std(32 to 39), + dopa => rd_array_data_d_std(70 to 70), + dopb => array_cmp_data_bramp_std(70 to 70), + dipa => std_logic_vector(wr_array_data_bram(70 to 70)), + dipb => (others => '0'), + ena => '1', + enb => '1', + wea => bram1_wea, + web => '0' + ); +-- This ram houses the 1xResv,U0-U3,WIMGE,UX,UW,UR,SX,SW,SR bits, wr_array_data_bram(40:55) +-- uses wr_array_val(1), parity is wr_array_data_bram(71:72) +bram2 : ramb16_s18_s18 + +-- pragma translate_off +generic map( + +-- all, none, warning_only, generate_x_only +sim_collision_check => "none") + +-- pragma translate_on +port map( + clka => clk2x, + clkb => clk2x, + ssra => sreset_q, + ssrb => sreset_q, + addra => std_logic_vector(bram2_addra), + addrb => std_logic_vector(bram2_addrb), + dia => std_logic_vector(wr_array_data_bram(40 to 55)), + dib => (others => '0'), + doa => rd_array_data_d_std(40 to 55), + dob => array_cmp_data_bram_std(40 to 55), + dopa => rd_array_data_d_std(71 to 72), + dopb => array_cmp_data_bramp_std(71 to 72), + dipa => std_logic_vector(wr_array_data_bram(71 to 72)), + dipb => (others => '0'), + ena => '1', + enb => '1', + wea => bram2_wea, + web => '0' + ); +-- array write data swizzle -> convert 68-bit data to 73-bit bram data +-- 32x143 version, 42b RA +-- wr_array_data +-- 0:29 - RPN +-- 30:31 - R,C +-- 32:35 - ResvAttr +-- 36:39 - U0-U3 +-- 40:44 - WIMGE +-- 45:47 - UX,UW,UR +-- 48:50 - SX,SW,SR +-- 51:60 - CAM parity +-- 61:67 - Array parity +-- RTX layout in A2_AvpEratHelper.C +-- ram0(0:31): 00 & RPN(0:29) +-- ram1(0:7) : 00 & R,C,ResvAttr(0:3) +-- ram2(0:15): '0' & U(0:3),WIMGE,UX,UW,UR,SX,SW,SR +wr_array_data_bram(0 to 72) <= "00" & wr_array_data(0 to 29) & + "00" & wr_array_data(30 to 35) & + '0' & wr_array_data(36 to 50) & + wr_array_data(51 to 60) & wr_array_data(61 to 67); +rd_array_data_d_std(56 to 65) <= (others => '0'); +rd_array_data_d(0 to 29) <= std_ulogic_vector(rd_array_data_d_std(2 to 31)); +rd_array_data_d(30 to 35) <= std_ulogic_vector(rd_array_data_d_std(34 to 39)); +rd_array_data_d(36 to 50) <= std_ulogic_vector(rd_array_data_d_std(41 to 55)); +rd_array_data_d(61 to 67) <= std_ulogic_vector(rd_array_data_d_std(66 to 72)); +array_cmp_data_bram <= std_ulogic_vector(array_cmp_data_bram_std); +array_cmp_data_bramp <= std_ulogic_vector(array_cmp_data_bramp_std); +----------------------------------------------------------------------- +-- entity output assignments +----------------------------------------------------------------------- +rd_array_data <= rd_array_data_q; +cam_cmp_data <= cam_cmp_data_q; +rd_cam_data <= rd_cam_data_q; +entry_valid(0) <= entry0_v_q; +entry_valid(1) <= entry1_v_q; +entry_valid(2) <= entry2_v_q; +entry_valid(3) <= entry3_v_q; +entry_valid(4) <= entry4_v_q; +entry_valid(5) <= entry5_v_q; +entry_valid(6) <= entry6_v_q; +entry_valid(7) <= entry7_v_q; +entry_valid(8) <= entry8_v_q; +entry_valid(9) <= entry9_v_q; +entry_valid(10) <= entry10_v_q; +entry_valid(11) <= entry11_v_q; +entry_valid(12) <= entry12_v_q; +entry_valid(13) <= entry13_v_q; +entry_valid(14) <= entry14_v_q; +entry_valid(15) <= entry15_v_q; +entry_match <= entry_match_q; +cam_hit_entry <= cam_hit_entry_q; +cam_hit <= cam_hit_q; +func_scan_out <= func_scan_in; +regfile_scan_out <= regfile_scan_in; +time_scan_out <= time_scan_in; +end generate; +end tri_cam_16x143_1r1w1c; diff --git a/rel/src/vhdl/tri/tri_cam_16x143_1r1w1c_matchline.vhdl b/rel/src/vhdl/tri/tri_cam_16x143_1r1w1c_matchline.vhdl new file mode 100644 index 0000000..bad8ab6 --- /dev/null +++ b/rel/src/vhdl/tri/tri_cam_16x143_1r1w1c_matchline.vhdl @@ -0,0 +1,457 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +--******************************************************************** +--* +--* TITLE: I-ERAT CAM Match Line Logic for Functional Model +--* +--* NAME: tri_cam_16x143_1r1w1c_matchline +--* + +library ieee; +use ieee.std_logic_1164.all ; +library ibm; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; + +------------------------------------------------------------------------ +-- Entity +------------------------------------------------------------------------ + +entity tri_cam_16x143_1r1w1c_matchline is + generic (have_xbit : integer := 1; + num_pgsizes : integer := 5; + have_cmpmask : integer := 1; + cmpmask_width : integer := 4); + +port( -- @{default:nclk}@ + addr_in : in std_ulogic_vector(0 to 51); + addr_enable : in std_ulogic_vector(0 to 1); + comp_pgsize : in std_ulogic_vector(0 to 2); + pgsize_enable : in std_ulogic; + entry_size : in std_ulogic_vector(0 to 2); + entry_cmpmask : in std_ulogic_vector(0 to cmpmask_width-1); + entry_xbit : in std_ulogic; + entry_xbitmask : in std_ulogic_vector(0 to cmpmask_width-1); + entry_epn : in std_ulogic_vector(0 to 51); + comp_class : in std_ulogic_vector(0 to 1); + entry_class : in std_ulogic_vector(0 to 1); + class_enable : in std_ulogic_vector(0 to 2); + comp_extclass : in std_ulogic_vector(0 to 1); + entry_extclass : in std_ulogic_vector(0 to 1); + extclass_enable : in std_ulogic_vector(0 to 1); + comp_state : in std_ulogic_vector(0 to 1); + entry_hv : in std_ulogic; + entry_ds : in std_ulogic; + state_enable : in std_ulogic_vector(0 to 1); + entry_thdid : in std_ulogic_vector(0 to 3); + comp_thdid : in std_ulogic_vector(0 to 3); + thdid_enable : in std_ulogic_vector(0 to 1); + entry_pid : in std_ulogic_vector(0 to 7); + comp_pid : in std_ulogic_vector(0 to 7); + pid_enable : in std_ulogic; + entry_v : in std_ulogic; + comp_invalidate : in std_ulogic; + + match : out std_ulogic +); + + -- synopsys translate_off + -- synopsys translate_on + +end tri_cam_16x143_1r1w1c_matchline; + +architecture tri_cam_16x143_1r1w1c_matchline of tri_cam_16x143_1r1w1c_matchline is + + +------------------------------------------------------------------------ +-- Signals +------------------------------------------------------------------------ + + signal entry_epn_b : std_ulogic_vector(34 to 51); + signal function_50_51 : std_ulogic; + signal function_48_51 : std_ulogic; + signal function_46_51 : std_ulogic; + signal function_44_51 : std_ulogic; + signal function_40_51 : std_ulogic; + signal function_36_51 : std_ulogic; + signal function_34_51 : std_ulogic; + signal pgsize_eq_16K : std_ulogic; + signal pgsize_eq_64K : std_ulogic; + signal pgsize_eq_256K : std_ulogic; + signal pgsize_eq_1M : std_ulogic; + signal pgsize_eq_16M : std_ulogic; + signal pgsize_eq_256M : std_ulogic; + signal pgsize_eq_1G : std_ulogic; + signal pgsize_gte_16K : std_ulogic; + signal pgsize_gte_64K : std_ulogic; + signal pgsize_gte_256K : std_ulogic; + signal pgsize_gte_1M : std_ulogic; + signal pgsize_gte_16M : std_ulogic; + signal pgsize_gte_256M : std_ulogic; + signal pgsize_gte_1G : std_ulogic; + signal comp_or_34_35 : std_ulogic; + signal comp_or_34_39 : std_ulogic; + signal comp_or_36_39 : std_ulogic; + signal comp_or_40_43 : std_ulogic; + signal comp_or_44_45 : std_ulogic; + signal comp_or_44_47 : std_ulogic; + signal comp_or_46_47 : std_ulogic; + signal comp_or_48_49 : std_ulogic; + signal comp_or_48_51 : std_ulogic; + signal comp_or_50_51 : std_ulogic; + signal match_line : std_ulogic_vector(0 to 72); + signal pgsize_match : std_ulogic; + signal addr_match : std_ulogic; + signal class_match : std_ulogic; + signal extclass_match : std_ulogic; + signal state_match : std_ulogic; + signal thdid_match : std_ulogic; + signal pid_match : std_ulogic; + +begin + + match_line(0 to 72) <= not((entry_epn(0 to 51) & entry_size(0 to 2) & entry_class(0 to 1) & entry_extclass(0 to 1) & entry_hv & entry_ds & entry_pid(0 to 7) & entry_thdid(0 to 3)) xor + (addr_in(0 to 51) & comp_pgsize(0 to 2) & comp_class(0 to 1) & comp_extclass(0 to 1) & comp_state(0 to 1) & comp_pid(0 to 7) & comp_thdid(0 to 3)) + ); + +numpgsz8 : if num_pgsizes = 8 generate + + entry_epn_b(34 to 51) <= not(entry_epn(34 to 51)); + + +gen_nocmpmask80 : if have_cmpmask = 0 generate + pgsize_eq_1G <= ( entry_size(0) and entry_size(1) and entry_size(2) ); + pgsize_eq_256M <= ( entry_size(0) and entry_size(1) and not(entry_size(2))); + pgsize_eq_16M <= ( entry_size(0) and not(entry_size(1)) and entry_size(2) ); + pgsize_eq_1M <= ( entry_size(0) and not(entry_size(1)) and not(entry_size(2))); + pgsize_eq_256K <= (not(entry_size(0)) and entry_size(1) and entry_size(2) ); + pgsize_eq_64K <= (not(entry_size(0)) and entry_size(1) and not(entry_size(2))); + pgsize_eq_16K <= (not(entry_size(0)) and not(entry_size(1)) and entry_size(2) ); + + pgsize_gte_1G <= ( entry_size(0) and entry_size(1) and entry_size(2) ); + pgsize_gte_256M <= ( entry_size(0) and entry_size(1) and not(entry_size(2))) or + pgsize_gte_1G; + pgsize_gte_16M <= ( entry_size(0) and not(entry_size(1)) and entry_size(2) ) or + pgsize_gte_256M; + pgsize_gte_1M <= ( entry_size(0) and not(entry_size(1)) and not(entry_size(2))) or + pgsize_gte_16M; + pgsize_gte_256K <= (not(entry_size(0)) and entry_size(1) and entry_size(2) ) or + pgsize_gte_1M; + pgsize_gte_64K <= (not(entry_size(0)) and entry_size(1) and not(entry_size(2))) or + pgsize_gte_256K; + pgsize_gte_16K <= (not(entry_size(0)) and not(entry_size(1)) and entry_size(2) ) or + pgsize_gte_64K; + +end generate gen_nocmpmask80; + +gen_cmpmask80 : if have_cmpmask = 1 generate +-- size entry_cmpmask: 0123456 +-- 1GB 0000000 +-- 256MB 1000000 +-- 16MB 1100000 +-- 1MB 1110000 +-- 256KB 1111000 +-- 64KB 1111100 +-- 16KB 1111110 +-- 4KB 1111111 + pgsize_gte_1G <= not entry_cmpmask(0); + pgsize_gte_256M <= not entry_cmpmask(1); + pgsize_gte_16M <= not entry_cmpmask(2); + pgsize_gte_1M <= not entry_cmpmask(3); + pgsize_gte_256K <= not entry_cmpmask(4); + pgsize_gte_64K <= not entry_cmpmask(5); + pgsize_gte_16K <= not entry_cmpmask(6); + +-- size entry_xbitmask: 0123456 +-- 1GB 1000000 +-- 256MB 0100000 +-- 16MB 0010000 +-- 1MB 0001000 +-- 256KB 0000100 +-- 64KB 0000010 +-- 16KB 0000001 +-- 4KB 0000000 + pgsize_eq_1G <= entry_xbitmask(0); + pgsize_eq_256M <= entry_xbitmask(1); + pgsize_eq_16M <= entry_xbitmask(2); + pgsize_eq_1M <= entry_xbitmask(3); + pgsize_eq_256K <= entry_xbitmask(4); + pgsize_eq_64K <= entry_xbitmask(5); + pgsize_eq_16K <= entry_xbitmask(6); +end generate gen_cmpmask80; + +gen_noxbit80 : if have_xbit = 0 generate + function_34_51 <= '0'; + function_36_51 <= '0'; + function_40_51 <= '0'; + function_44_51 <= '0'; + function_46_51 <= '0'; + function_48_51 <= '0'; + function_50_51 <= '0'; +end generate gen_noxbit80; + +gen_xbit80 : if have_xbit /= 0 generate + function_34_51 <= not(entry_xbit) or + not(pgsize_eq_1G) or + or_reduce(entry_epn_b(34 to 51) and addr_in(34 to 51)); + function_36_51 <= not(entry_xbit) or + not(pgsize_eq_256M) or + or_reduce(entry_epn_b(36 to 51) and addr_in(36 to 51)); + function_40_51 <= not(entry_xbit) or + not(pgsize_eq_16M) or + or_reduce(entry_epn_b(40 to 51) and addr_in(40 to 51)); + function_44_51 <= not(entry_xbit) or + not(pgsize_eq_1M) or + or_reduce(entry_epn_b(44 to 51) and addr_in(44 to 51)); + function_46_51 <= not(entry_xbit) or + not(pgsize_eq_256K) or + or_reduce(entry_epn_b(46 to 51) and addr_in(46 to 51)); + function_48_51 <= not(entry_xbit) or + not(pgsize_eq_64K) or + or_reduce(entry_epn_b(48 to 51) and addr_in(48 to 51)); + function_50_51 <= not(entry_xbit) or + not(pgsize_eq_16K) or + or_reduce(entry_epn_b(50 to 51) and addr_in(50 to 51)); +end generate gen_xbit80; + + + + comp_or_50_51 <= and_reduce(match_line(50 to 51)) or pgsize_gte_16K; + comp_or_48_49 <= and_reduce(match_line(48 to 49)) or pgsize_gte_64K; + comp_or_46_47 <= and_reduce(match_line(46 to 47)) or pgsize_gte_256K; + comp_or_44_45 <= and_reduce(match_line(44 to 45)) or pgsize_gte_1M; + comp_or_40_43 <= and_reduce(match_line(40 to 43)) or pgsize_gte_16M; + comp_or_36_39 <= and_reduce(match_line(36 to 39)) or pgsize_gte_256M; + comp_or_34_35 <= and_reduce(match_line(34 to 35)) or pgsize_gte_1G; + +gen_noxbit81 : if have_xbit = 0 generate + addr_match <= (comp_or_34_35 and -- Ignore functions based on page size + comp_or_36_39 and + comp_or_40_43 and + comp_or_44_45 and + comp_or_46_47 and + comp_or_48_49 and + comp_or_50_51 and + and_reduce(match_line(31 to 33)) and -- Regular compare largest page size + (and_reduce(match_line(0 to 30)) or not(addr_enable(1)))) or -- ignored part of epn + not(addr_enable(0)); -- Include address as part of compare, + -- should never ignore for regular compare/read. + -- Could ignore for compare/invalidate +end generate gen_noxbit81; + +gen_xbit81 : if have_xbit /= 0 generate + addr_match <= (function_50_51 and -- Exclusion functions + function_48_51 and + function_46_51 and + function_44_51 and + function_40_51 and + function_36_51 and + function_34_51 and + comp_or_34_35 and -- Ignore functions based on page size + comp_or_36_39 and + comp_or_40_43 and + comp_or_44_45 and + comp_or_46_47 and + comp_or_48_49 and + comp_or_50_51 and + and_reduce(match_line(31 to 33)) and -- Regular compare largest page size + (and_reduce(match_line(0 to 30)) or not(addr_enable(1)))) or -- ignored part of epn + not(addr_enable(0)); -- Include address as part of compare, + -- should never ignore for regular compare/read. + -- Could ignore for compare/invalidate +end generate gen_xbit81; + +end generate numpgsz8; -- numpgsz8: num_pgsizes = 8 + + +numpgsz5 : if num_pgsizes = 5 generate + + -- tie off unused signals + function_50_51 <= '0'; + function_46_51 <= '0'; + function_36_51 <= '0'; + pgsize_eq_16K <= '0'; + pgsize_eq_256K <= '0'; + pgsize_eq_256M <= '0'; + pgsize_gte_16K <= '0'; + pgsize_gte_256K <= '0'; + pgsize_gte_256M <= '0'; + comp_or_34_35 <= '0'; + comp_or_36_39 <= '0'; + comp_or_44_45 <= '0'; + comp_or_46_47 <= '0'; + comp_or_48_49 <= '0'; + comp_or_50_51 <= '0'; + + entry_epn_b(34 to 51) <= not(entry_epn(34 to 51)); + + +gen_nocmpmask50 : if have_cmpmask = 0 generate + -- 110 + pgsize_eq_1G <= ( entry_size(0) and entry_size(1) and not(entry_size(2)) ); + -- 111 + pgsize_eq_16M <= ( entry_size(0) and entry_size(1) and entry_size(2) ); + -- 101 + pgsize_eq_1M <= ( entry_size(0) and not(entry_size(1)) and entry_size(2)); + -- 011 + pgsize_eq_64K <= (not(entry_size(0)) and entry_size(1) and entry_size(2)); + + + pgsize_gte_1G <= ( entry_size(0) and entry_size(1) and not(entry_size(2)) ); + + pgsize_gte_16M <= ( entry_size(0) and entry_size(1) and entry_size(2) ) or + pgsize_gte_1G; + pgsize_gte_1M <= ( entry_size(0) and not(entry_size(1)) and entry_size(2)) or + pgsize_gte_16M; + pgsize_gte_64K <= (not(entry_size(0)) and entry_size(1) and entry_size(2)) or + pgsize_gte_1M; +end generate gen_nocmpmask50; + +gen_cmpmask50 : if have_cmpmask = 1 generate +-- size entry_cmpmask: 0123 +-- 1GB 0000 +-- 16MB 1000 +-- 1MB 1100 +-- 64KB 1110 +-- 4KB 1111 + pgsize_gte_1G <= not entry_cmpmask(0); + pgsize_gte_16M <= not entry_cmpmask(1); + pgsize_gte_1M <= not entry_cmpmask(2); + pgsize_gte_64K <= not entry_cmpmask(3); + +-- size entry_xbitmask: 0123 +-- 1GB 1000 +-- 16MB 0100 +-- 1MB 0010 +-- 64KB 0001 +-- 4KB 0000 + pgsize_eq_1G <= entry_xbitmask(0); + pgsize_eq_16M <= entry_xbitmask(1); + pgsize_eq_1M <= entry_xbitmask(2); + pgsize_eq_64K <= entry_xbitmask(3); +end generate gen_cmpmask50; + +gen_noxbit50 : if have_xbit = 0 generate + function_34_51 <= '0'; + function_40_51 <= '0'; + function_44_51 <= '0'; + function_48_51 <= '0'; +end generate gen_noxbit50; + +gen_xbit50 : if have_xbit /= 0 generate + -- 1G + function_34_51 <= not(entry_xbit) or + not(pgsize_eq_1G) or + or_reduce(entry_epn_b(34 to 51) and addr_in(34 to 51)); + -- 16M + function_40_51 <= not(entry_xbit) or + not(pgsize_eq_16M) or + or_reduce(entry_epn_b(40 to 51) and addr_in(40 to 51)); + -- 1M + function_44_51 <= not(entry_xbit) or + not(pgsize_eq_1M) or + or_reduce(entry_epn_b(44 to 51) and addr_in(44 to 51)); + -- 64K + function_48_51 <= not(entry_xbit) or + not(pgsize_eq_64K) or + or_reduce(entry_epn_b(48 to 51) and addr_in(48 to 51)); +end generate gen_xbit50; + + comp_or_48_51 <= and_reduce(match_line(48 to 51)) or pgsize_gte_64K; + comp_or_44_47 <= and_reduce(match_line(44 to 47)) or pgsize_gte_1M; + comp_or_40_43 <= and_reduce(match_line(40 to 43)) or pgsize_gte_16M; + comp_or_34_39 <= and_reduce(match_line(34 to 39)) or pgsize_gte_1G; + +gen_noxbit51 : if have_xbit = 0 generate + addr_match <= (comp_or_34_39 and -- Ignore functions based on page size + comp_or_40_43 and + comp_or_44_47 and + comp_or_48_51 and + and_reduce(match_line(31 to 33)) and -- Regular compare largest page size + (and_reduce(match_line(0 to 30)) or not(addr_enable(1)))) or -- ignored part of epn + not(addr_enable(0)); -- Include address as part of compare, + -- should never ignore for regular compare/read. + -- Could ignore for compare/invalidate +end generate gen_noxbit51; + +gen_xbit51 : if have_xbit /= 0 generate + addr_match <= (function_48_51 and + function_44_51 and + function_40_51 and + function_34_51 and + comp_or_34_39 and -- Ignore functions based on page size + comp_or_40_43 and + comp_or_44_47 and + comp_or_48_51 and + and_reduce(match_line(31 to 33)) and -- Regular compare largest page size + (and_reduce(match_line(0 to 30)) or not(addr_enable(1)))) or -- ignored part of epn + not(addr_enable(0)); -- Include address as part of compare, + -- should never ignore for regular compare/read. + -- Could ignore for compare/invalidate +end generate gen_xbit51; + +end generate numpgsz5; -- numpgsz5: num_pgsizes = 5 + + + pgsize_match <= and_reduce(match_line(52 to 54)) or + not(pgsize_enable); + + class_match <= (match_line(55) or not(class_enable(0))) and + (match_line(56) or not(class_enable(1))) and + (and_reduce(match_line(55 to 56)) or not(class_enable(2)) or + (not(entry_extclass(1)) and not comp_invalidate)); -- pid_nz bit + + extclass_match <= (match_line(57) or not(extclass_enable(0))) and -- iprot bit + (match_line(58) or not(extclass_enable(1))); -- pid_nz bit + + state_match <= (match_line(59) or + not(state_enable(0))) and + (match_line(60) or + not(state_enable(1))); + + thdid_match <= (or_reduce(entry_thdid(0 to 3) and comp_thdid(0 to 3)) or not(thdid_enable(0))) and + (and_reduce(match_line(69 to 72)) or not(thdid_enable(1)) or + (not(entry_extclass(1)) and not comp_invalidate)); -- pid_nz bit + + pid_match <= and_reduce(match_line(61 to 68)) or + -- entry_pid=0 ignores pid match for compares, + -- but not for invalidates. + (not(entry_extclass(1)) and not comp_invalidate) or -- pid_nz bit + not(pid_enable); + + match <= addr_match and -- Address compare + pgsize_match and -- Size compare + class_match and -- Class compare + extclass_match and -- ExtClass compare + state_match and -- State compare + thdid_match and -- ThdID compare + pid_match and -- PID compare + entry_v; -- Valid + +end tri_cam_16x143_1r1w1c_matchline; diff --git a/rel/src/vhdl/tri/tri_cam_32x143_1r1w1c.vhdl b/rel/src/vhdl/tri/tri_cam_32x143_1r1w1c.vhdl new file mode 100644 index 0000000..2d9b922 --- /dev/null +++ b/rel/src/vhdl/tri/tri_cam_32x143_1r1w1c.vhdl @@ -0,0 +1,5128 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +--******************************************************************** +--* TITLE: I-ERAT CAM Tri-Library Model +--* NAME: tri_cam_32x143_1r1w1c + +library ieee; +use ieee.std_logic_1164.all; +library ibm; +use ibm.std_ulogic_unsigned.all; +use ibm.std_ulogic_function_support.all; +library support; +use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; +-- pragma translate_off +-- pragma translate_on +entity tri_cam_32x143_1r1w1c is + + generic (cam_data_width : natural := 84; + array_data_width : natural := 68; + rpn_width : natural := 30; + num_entry : natural := 32; + num_entry_log2 : natural := 5; + expand_type : integer := 1); + port( + gnd : inout power_logic; + vdd : inout power_logic; + vcs : inout power_logic; + + nclk : in clk_logic; + tc_ccflush_dc : in std_ulogic; + tc_scan_dis_dc_b : in std_ulogic; + tc_scan_diag_dc : in std_ulogic; + tc_lbist_en_dc : in std_ulogic; + an_ac_atpg_en_dc : in std_ulogic; + + lcb_d_mode_dc : in std_ulogic; + lcb_clkoff_dc_b : in std_ulogic; + lcb_act_dis_dc : in std_ulogic; + lcb_mpw1_dc_b : in std_ulogic_vector(0 to 3); + lcb_mpw2_dc_b : in std_ulogic; + lcb_delay_lclkr_dc : in std_ulogic_vector(0 to 3); + + pc_sg_2 : in std_ulogic; + pc_func_slp_sl_thold_2 : in std_ulogic; + pc_func_slp_nsl_thold_2 : in std_ulogic; + pc_regf_slp_sl_thold_2 : in std_ulogic; + pc_time_sl_thold_2 : in std_ulogic; + pc_fce_2 : in std_ulogic; + + func_scan_in : in std_ulogic; + func_scan_out : out std_ulogic; + regfile_scan_in : in std_ulogic_vector(0 TO 6); + regfile_scan_out : out std_ulogic_vector(0 TO 6); + time_scan_in : in std_ulogic; + time_scan_out : out std_ulogic; + + + rd_val : in std_ulogic; + rd_val_late : in std_ulogic; + rw_entry : in std_ulogic_vector(0 to num_entry_log2-1); + + wr_array_data : in std_ulogic_vector(0 to array_data_width-1); + wr_cam_data : in std_ulogic_vector(0 to cam_data_width-1); + wr_array_val : in std_ulogic_vector(0 to 1); + wr_cam_val : in std_ulogic_vector(0 to 1); + wr_val_early : in std_ulogic; + + comp_request : in std_ulogic; + comp_addr : in std_ulogic_vector(0 to 51); + addr_enable : in std_ulogic_vector(0 to 1); + comp_pgsize : in std_ulogic_vector(0 to 2); + pgsize_enable : in std_ulogic; + comp_class : in std_ulogic_vector(0 to 1); + class_enable : in std_ulogic_vector(0 to 2); + comp_extclass : in std_ulogic_vector(0 to 1); + extclass_enable : in std_ulogic_vector(0 to 1); + comp_state : in std_ulogic_vector(0 to 1); + state_enable : in std_ulogic_vector(0 to 1); + comp_thdid : in std_ulogic_vector(0 to 3); + thdid_enable : in std_ulogic_vector(0 to 1); + comp_pid : in std_ulogic_vector(0 to 7); + pid_enable : in std_ulogic; + comp_invalidate : in std_ulogic; + flash_invalidate : in std_ulogic; + + array_cmp_data : out std_ulogic_vector(0 to array_data_width-1); + rd_array_data : out std_ulogic_vector(0 to array_data_width-1); + + cam_cmp_data : out std_ulogic_vector(0 to cam_data_width-1); + cam_hit : out std_ulogic; + cam_hit_entry : out std_ulogic_vector(0 to num_entry_log2-1); + entry_match : out std_ulogic_vector(0 to num_entry-1); + entry_valid : out std_ulogic_vector(0 to num_entry-1); + rd_cam_data : out std_ulogic_vector(0 to cam_data_width-1); + + +----- new ports for IO plus ----------------------- +bypass_mux_enab_np1 : in std_ulogic; +bypass_attr_np1 : in std_ulogic_vector(0 to 20); +attr_np2 : out std_ulogic_vector(0 to 20); +rpn_np2 : out std_ulogic_vector(22 to 51) + + ); +-- synopsys translate_off +-- synopsys translate_on +end entity tri_cam_32x143_1r1w1c; +architecture tri_cam_32x143_1r1w1c of tri_cam_32x143_1r1w1c is +component tri_cam_32x143_1r1w1c_matchline + generic (have_xbit : integer := 1; + num_pgsizes : integer := 5; + have_cmpmask : integer := 1; + cmpmask_width : integer := 4); +port( + addr_in : in std_ulogic_vector(0 to 51); + addr_enable : in std_ulogic_vector(0 to 1); + comp_pgsize : in std_ulogic_vector(0 to 2); + pgsize_enable : in std_ulogic; + entry_size : in std_ulogic_vector(0 to 2); + entry_cmpmask : in std_ulogic_vector(0 to cmpmask_width-1); + entry_xbit : in std_ulogic; + entry_xbitmask : in std_ulogic_vector(0 to cmpmask_width-1); + entry_epn : in std_ulogic_vector(0 to 51); + comp_class : in std_ulogic_vector(0 to 1); + entry_class : in std_ulogic_vector(0 to 1); + class_enable : in std_ulogic_vector(0 to 2); + comp_extclass : in std_ulogic_vector(0 to 1); + entry_extclass : in std_ulogic_vector(0 to 1); + extclass_enable : in std_ulogic_vector(0 to 1); + comp_state : in std_ulogic_vector(0 to 1); + entry_hv : in std_ulogic; + entry_ds : in std_ulogic; + state_enable : in std_ulogic_vector(0 to 1); + entry_thdid : in std_ulogic_vector(0 to 3); + comp_thdid : in std_ulogic_vector(0 to 3); + thdid_enable : in std_ulogic_vector(0 to 1); + entry_pid : in std_ulogic_vector(0 to 7); + comp_pid : in std_ulogic_vector(0 to 7); + pid_enable : in std_ulogic; + entry_v : in std_ulogic; + comp_invalidate : in std_ulogic; + + match : out std_ulogic +); +end component; +begin +a : if expand_type = 1 generate +component RAMB16_S9_S9 +-- pragma translate_off + generic + ( + SIM_COLLISION_CHECK : string := "none"); +-- pragma translate_on + port + ( + DOA : out std_logic_vector(7 downto 0); + DOB : out std_logic_vector(7 downto 0); + DOPA : out std_logic_vector(0 downto 0); + DOPB : out std_logic_vector(0 downto 0); + ADDRA : in std_logic_vector(10 downto 0); + ADDRB : in std_logic_vector(10 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(7 downto 0); + DIB : in std_logic_vector(7 downto 0); + DIPA : in std_logic_vector(0 downto 0); + DIPB : in std_logic_vector(0 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); +end component; +component RAMB16_S18_S18 +-- pragma translate_off + generic( + SIM_COLLISION_CHECK : string := "none"); +-- pragma translate_on + port( + DOA : out std_logic_vector(15 downto 0); + DOB : out std_logic_vector(15 downto 0); + DOPA : out std_logic_vector(1 downto 0); + DOPB : out std_logic_vector(1 downto 0); + + ADDRA : in std_logic_vector(9 downto 0); + ADDRB : in std_logic_vector(9 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(15 downto 0); + DIB : in std_logic_vector(15 downto 0); + DIPA : in std_logic_vector(1 downto 0); + DIPB : in std_logic_vector(1 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic); + end component; +component RAMB16_S36_S36 +-- pragma translate_off + generic( + SIM_COLLISION_CHECK : string := "none"); +-- pragma translate_on + port( + DOA : out std_logic_vector(31 downto 0); + DOB : out std_logic_vector(31 downto 0); + DOPA : out std_logic_vector(3 downto 0); + DOPB : out std_logic_vector(3 downto 0); + ADDRA : in std_logic_vector(8 downto 0); + ADDRB : in std_logic_vector(8 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(31 downto 0); + DIB : in std_logic_vector(31 downto 0); + DIPA : in std_logic_vector(3 downto 0); + DIPB : in std_logic_vector(3 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic); + end component; +-- pragma translate_off +-- pragma translate_on +signal clk,clk2x : std_ulogic; +signal bram0_addra, bram0_addrb : std_ulogic_vector(0 to 8); +signal bram1_addra, bram1_addrb : std_ulogic_vector(0 to 10); +signal bram2_addra, bram2_addrb : std_ulogic_vector(0 to 9); +signal bram0_wea, bram1_wea, bram2_wea : std_ulogic; +signal array_cmp_data_bram : std_ulogic_vector(0 to 55); +signal array_cmp_data_bramp : std_ulogic_vector(66 to 72); +-- Latches +signal sreset_q : std_ulogic; +signal gate_fq, gate_d : std_ulogic; +signal comp_addr_np1_d, comp_addr_np1_q : std_ulogic_vector(52-rpn_width to 51); +signal rpn_np2_d,rpn_np2_q : std_ulogic_vector(52-rpn_width to 51); +signal attr_np2_d,attr_np2_q : std_ulogic_vector(0 to 20); +-- CAM entry signals +signal entry0_epn_d, entry0_epn_q : std_ulogic_vector(0 to 51); +signal entry0_xbit_d, entry0_xbit_q : std_ulogic; +signal entry0_size_d, entry0_size_q : std_ulogic_vector(0 to 2); +signal entry0_v_d, entry0_v_q : std_ulogic; +signal entry0_thdid_d, entry0_thdid_q : std_ulogic_vector(0 to 3); +signal entry0_class_d, entry0_class_q : std_ulogic_vector(0 to 1); +signal entry0_extclass_d, entry0_extclass_q : std_ulogic_vector(0 to 1); +signal entry0_hv_d, entry0_hv_q : std_ulogic; +signal entry0_ds_d, entry0_ds_q : std_ulogic; +signal entry0_pid_d, entry0_pid_q : std_ulogic_vector(0 to 7); +signal entry0_cmpmask_d, entry0_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry0_parity_d, entry0_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry0_sel : std_ulogic_vector(0 to 1); +signal entry0_inval : std_ulogic; +signal entry0_v_muxsel : std_ulogic_vector(0 to 1); +signal entry0_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry0_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry1_epn_d, entry1_epn_q : std_ulogic_vector(0 to 51); +signal entry1_xbit_d, entry1_xbit_q : std_ulogic; +signal entry1_size_d, entry1_size_q : std_ulogic_vector(0 to 2); +signal entry1_v_d, entry1_v_q : std_ulogic; +signal entry1_thdid_d, entry1_thdid_q : std_ulogic_vector(0 to 3); +signal entry1_class_d, entry1_class_q : std_ulogic_vector(0 to 1); +signal entry1_extclass_d, entry1_extclass_q : std_ulogic_vector(0 to 1); +signal entry1_hv_d, entry1_hv_q : std_ulogic; +signal entry1_ds_d, entry1_ds_q : std_ulogic; +signal entry1_pid_d, entry1_pid_q : std_ulogic_vector(0 to 7); +signal entry1_cmpmask_d, entry1_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry1_parity_d, entry1_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry1_sel : std_ulogic_vector(0 to 1); +signal entry1_inval : std_ulogic; +signal entry1_v_muxsel : std_ulogic_vector(0 to 1); +signal entry1_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry1_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry2_epn_d, entry2_epn_q : std_ulogic_vector(0 to 51); +signal entry2_xbit_d, entry2_xbit_q : std_ulogic; +signal entry2_size_d, entry2_size_q : std_ulogic_vector(0 to 2); +signal entry2_v_d, entry2_v_q : std_ulogic; +signal entry2_thdid_d, entry2_thdid_q : std_ulogic_vector(0 to 3); +signal entry2_class_d, entry2_class_q : std_ulogic_vector(0 to 1); +signal entry2_extclass_d, entry2_extclass_q : std_ulogic_vector(0 to 1); +signal entry2_hv_d, entry2_hv_q : std_ulogic; +signal entry2_ds_d, entry2_ds_q : std_ulogic; +signal entry2_pid_d, entry2_pid_q : std_ulogic_vector(0 to 7); +signal entry2_cmpmask_d, entry2_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry2_parity_d, entry2_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry2_sel : std_ulogic_vector(0 to 1); +signal entry2_inval : std_ulogic; +signal entry2_v_muxsel : std_ulogic_vector(0 to 1); +signal entry2_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry2_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry3_epn_d, entry3_epn_q : std_ulogic_vector(0 to 51); +signal entry3_xbit_d, entry3_xbit_q : std_ulogic; +signal entry3_size_d, entry3_size_q : std_ulogic_vector(0 to 2); +signal entry3_v_d, entry3_v_q : std_ulogic; +signal entry3_thdid_d, entry3_thdid_q : std_ulogic_vector(0 to 3); +signal entry3_class_d, entry3_class_q : std_ulogic_vector(0 to 1); +signal entry3_extclass_d, entry3_extclass_q : std_ulogic_vector(0 to 1); +signal entry3_hv_d, entry3_hv_q : std_ulogic; +signal entry3_ds_d, entry3_ds_q : std_ulogic; +signal entry3_pid_d, entry3_pid_q : std_ulogic_vector(0 to 7); +signal entry3_cmpmask_d, entry3_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry3_parity_d, entry3_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry3_sel : std_ulogic_vector(0 to 1); +signal entry3_inval : std_ulogic; +signal entry3_v_muxsel : std_ulogic_vector(0 to 1); +signal entry3_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry3_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry4_epn_d, entry4_epn_q : std_ulogic_vector(0 to 51); +signal entry4_xbit_d, entry4_xbit_q : std_ulogic; +signal entry4_size_d, entry4_size_q : std_ulogic_vector(0 to 2); +signal entry4_v_d, entry4_v_q : std_ulogic; +signal entry4_thdid_d, entry4_thdid_q : std_ulogic_vector(0 to 3); +signal entry4_class_d, entry4_class_q : std_ulogic_vector(0 to 1); +signal entry4_extclass_d, entry4_extclass_q : std_ulogic_vector(0 to 1); +signal entry4_hv_d, entry4_hv_q : std_ulogic; +signal entry4_ds_d, entry4_ds_q : std_ulogic; +signal entry4_pid_d, entry4_pid_q : std_ulogic_vector(0 to 7); +signal entry4_cmpmask_d, entry4_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry4_parity_d, entry4_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry4_sel : std_ulogic_vector(0 to 1); +signal entry4_inval : std_ulogic; +signal entry4_v_muxsel : std_ulogic_vector(0 to 1); +signal entry4_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry4_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry5_epn_d, entry5_epn_q : std_ulogic_vector(0 to 51); +signal entry5_xbit_d, entry5_xbit_q : std_ulogic; +signal entry5_size_d, entry5_size_q : std_ulogic_vector(0 to 2); +signal entry5_v_d, entry5_v_q : std_ulogic; +signal entry5_thdid_d, entry5_thdid_q : std_ulogic_vector(0 to 3); +signal entry5_class_d, entry5_class_q : std_ulogic_vector(0 to 1); +signal entry5_extclass_d, entry5_extclass_q : std_ulogic_vector(0 to 1); +signal entry5_hv_d, entry5_hv_q : std_ulogic; +signal entry5_ds_d, entry5_ds_q : std_ulogic; +signal entry5_pid_d, entry5_pid_q : std_ulogic_vector(0 to 7); +signal entry5_cmpmask_d, entry5_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry5_parity_d, entry5_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry5_sel : std_ulogic_vector(0 to 1); +signal entry5_inval : std_ulogic; +signal entry5_v_muxsel : std_ulogic_vector(0 to 1); +signal entry5_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry5_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry6_epn_d, entry6_epn_q : std_ulogic_vector(0 to 51); +signal entry6_xbit_d, entry6_xbit_q : std_ulogic; +signal entry6_size_d, entry6_size_q : std_ulogic_vector(0 to 2); +signal entry6_v_d, entry6_v_q : std_ulogic; +signal entry6_thdid_d, entry6_thdid_q : std_ulogic_vector(0 to 3); +signal entry6_class_d, entry6_class_q : std_ulogic_vector(0 to 1); +signal entry6_extclass_d, entry6_extclass_q : std_ulogic_vector(0 to 1); +signal entry6_hv_d, entry6_hv_q : std_ulogic; +signal entry6_ds_d, entry6_ds_q : std_ulogic; +signal entry6_pid_d, entry6_pid_q : std_ulogic_vector(0 to 7); +signal entry6_cmpmask_d, entry6_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry6_parity_d, entry6_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry6_sel : std_ulogic_vector(0 to 1); +signal entry6_inval : std_ulogic; +signal entry6_v_muxsel : std_ulogic_vector(0 to 1); +signal entry6_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry6_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry7_epn_d, entry7_epn_q : std_ulogic_vector(0 to 51); +signal entry7_xbit_d, entry7_xbit_q : std_ulogic; +signal entry7_size_d, entry7_size_q : std_ulogic_vector(0 to 2); +signal entry7_v_d, entry7_v_q : std_ulogic; +signal entry7_thdid_d, entry7_thdid_q : std_ulogic_vector(0 to 3); +signal entry7_class_d, entry7_class_q : std_ulogic_vector(0 to 1); +signal entry7_extclass_d, entry7_extclass_q : std_ulogic_vector(0 to 1); +signal entry7_hv_d, entry7_hv_q : std_ulogic; +signal entry7_ds_d, entry7_ds_q : std_ulogic; +signal entry7_pid_d, entry7_pid_q : std_ulogic_vector(0 to 7); +signal entry7_cmpmask_d, entry7_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry7_parity_d, entry7_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry7_sel : std_ulogic_vector(0 to 1); +signal entry7_inval : std_ulogic; +signal entry7_v_muxsel : std_ulogic_vector(0 to 1); +signal entry7_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry7_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry8_epn_d, entry8_epn_q : std_ulogic_vector(0 to 51); +signal entry8_xbit_d, entry8_xbit_q : std_ulogic; +signal entry8_size_d, entry8_size_q : std_ulogic_vector(0 to 2); +signal entry8_v_d, entry8_v_q : std_ulogic; +signal entry8_thdid_d, entry8_thdid_q : std_ulogic_vector(0 to 3); +signal entry8_class_d, entry8_class_q : std_ulogic_vector(0 to 1); +signal entry8_extclass_d, entry8_extclass_q : std_ulogic_vector(0 to 1); +signal entry8_hv_d, entry8_hv_q : std_ulogic; +signal entry8_ds_d, entry8_ds_q : std_ulogic; +signal entry8_pid_d, entry8_pid_q : std_ulogic_vector(0 to 7); +signal entry8_cmpmask_d, entry8_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry8_parity_d, entry8_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry8_sel : std_ulogic_vector(0 to 1); +signal entry8_inval : std_ulogic; +signal entry8_v_muxsel : std_ulogic_vector(0 to 1); +signal entry8_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry8_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry9_epn_d, entry9_epn_q : std_ulogic_vector(0 to 51); +signal entry9_xbit_d, entry9_xbit_q : std_ulogic; +signal entry9_size_d, entry9_size_q : std_ulogic_vector(0 to 2); +signal entry9_v_d, entry9_v_q : std_ulogic; +signal entry9_thdid_d, entry9_thdid_q : std_ulogic_vector(0 to 3); +signal entry9_class_d, entry9_class_q : std_ulogic_vector(0 to 1); +signal entry9_extclass_d, entry9_extclass_q : std_ulogic_vector(0 to 1); +signal entry9_hv_d, entry9_hv_q : std_ulogic; +signal entry9_ds_d, entry9_ds_q : std_ulogic; +signal entry9_pid_d, entry9_pid_q : std_ulogic_vector(0 to 7); +signal entry9_cmpmask_d, entry9_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry9_parity_d, entry9_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry9_sel : std_ulogic_vector(0 to 1); +signal entry9_inval : std_ulogic; +signal entry9_v_muxsel : std_ulogic_vector(0 to 1); +signal entry9_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry9_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry10_epn_d, entry10_epn_q : std_ulogic_vector(0 to 51); +signal entry10_xbit_d, entry10_xbit_q : std_ulogic; +signal entry10_size_d, entry10_size_q : std_ulogic_vector(0 to 2); +signal entry10_v_d, entry10_v_q : std_ulogic; +signal entry10_thdid_d, entry10_thdid_q : std_ulogic_vector(0 to 3); +signal entry10_class_d, entry10_class_q : std_ulogic_vector(0 to 1); +signal entry10_extclass_d, entry10_extclass_q : std_ulogic_vector(0 to 1); +signal entry10_hv_d, entry10_hv_q : std_ulogic; +signal entry10_ds_d, entry10_ds_q : std_ulogic; +signal entry10_pid_d, entry10_pid_q : std_ulogic_vector(0 to 7); +signal entry10_cmpmask_d, entry10_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry10_parity_d, entry10_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry10_sel : std_ulogic_vector(0 to 1); +signal entry10_inval : std_ulogic; +signal entry10_v_muxsel : std_ulogic_vector(0 to 1); +signal entry10_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry10_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry11_epn_d, entry11_epn_q : std_ulogic_vector(0 to 51); +signal entry11_xbit_d, entry11_xbit_q : std_ulogic; +signal entry11_size_d, entry11_size_q : std_ulogic_vector(0 to 2); +signal entry11_v_d, entry11_v_q : std_ulogic; +signal entry11_thdid_d, entry11_thdid_q : std_ulogic_vector(0 to 3); +signal entry11_class_d, entry11_class_q : std_ulogic_vector(0 to 1); +signal entry11_extclass_d, entry11_extclass_q : std_ulogic_vector(0 to 1); +signal entry11_hv_d, entry11_hv_q : std_ulogic; +signal entry11_ds_d, entry11_ds_q : std_ulogic; +signal entry11_pid_d, entry11_pid_q : std_ulogic_vector(0 to 7); +signal entry11_cmpmask_d, entry11_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry11_parity_d, entry11_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry11_sel : std_ulogic_vector(0 to 1); +signal entry11_inval : std_ulogic; +signal entry11_v_muxsel : std_ulogic_vector(0 to 1); +signal entry11_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry11_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry12_epn_d, entry12_epn_q : std_ulogic_vector(0 to 51); +signal entry12_xbit_d, entry12_xbit_q : std_ulogic; +signal entry12_size_d, entry12_size_q : std_ulogic_vector(0 to 2); +signal entry12_v_d, entry12_v_q : std_ulogic; +signal entry12_thdid_d, entry12_thdid_q : std_ulogic_vector(0 to 3); +signal entry12_class_d, entry12_class_q : std_ulogic_vector(0 to 1); +signal entry12_extclass_d, entry12_extclass_q : std_ulogic_vector(0 to 1); +signal entry12_hv_d, entry12_hv_q : std_ulogic; +signal entry12_ds_d, entry12_ds_q : std_ulogic; +signal entry12_pid_d, entry12_pid_q : std_ulogic_vector(0 to 7); +signal entry12_cmpmask_d, entry12_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry12_parity_d, entry12_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry12_sel : std_ulogic_vector(0 to 1); +signal entry12_inval : std_ulogic; +signal entry12_v_muxsel : std_ulogic_vector(0 to 1); +signal entry12_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry12_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry13_epn_d, entry13_epn_q : std_ulogic_vector(0 to 51); +signal entry13_xbit_d, entry13_xbit_q : std_ulogic; +signal entry13_size_d, entry13_size_q : std_ulogic_vector(0 to 2); +signal entry13_v_d, entry13_v_q : std_ulogic; +signal entry13_thdid_d, entry13_thdid_q : std_ulogic_vector(0 to 3); +signal entry13_class_d, entry13_class_q : std_ulogic_vector(0 to 1); +signal entry13_extclass_d, entry13_extclass_q : std_ulogic_vector(0 to 1); +signal entry13_hv_d, entry13_hv_q : std_ulogic; +signal entry13_ds_d, entry13_ds_q : std_ulogic; +signal entry13_pid_d, entry13_pid_q : std_ulogic_vector(0 to 7); +signal entry13_cmpmask_d, entry13_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry13_parity_d, entry13_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry13_sel : std_ulogic_vector(0 to 1); +signal entry13_inval : std_ulogic; +signal entry13_v_muxsel : std_ulogic_vector(0 to 1); +signal entry13_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry13_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry14_epn_d, entry14_epn_q : std_ulogic_vector(0 to 51); +signal entry14_xbit_d, entry14_xbit_q : std_ulogic; +signal entry14_size_d, entry14_size_q : std_ulogic_vector(0 to 2); +signal entry14_v_d, entry14_v_q : std_ulogic; +signal entry14_thdid_d, entry14_thdid_q : std_ulogic_vector(0 to 3); +signal entry14_class_d, entry14_class_q : std_ulogic_vector(0 to 1); +signal entry14_extclass_d, entry14_extclass_q : std_ulogic_vector(0 to 1); +signal entry14_hv_d, entry14_hv_q : std_ulogic; +signal entry14_ds_d, entry14_ds_q : std_ulogic; +signal entry14_pid_d, entry14_pid_q : std_ulogic_vector(0 to 7); +signal entry14_cmpmask_d, entry14_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry14_parity_d, entry14_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry14_sel : std_ulogic_vector(0 to 1); +signal entry14_inval : std_ulogic; +signal entry14_v_muxsel : std_ulogic_vector(0 to 1); +signal entry14_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry14_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry15_epn_d, entry15_epn_q : std_ulogic_vector(0 to 51); +signal entry15_xbit_d, entry15_xbit_q : std_ulogic; +signal entry15_size_d, entry15_size_q : std_ulogic_vector(0 to 2); +signal entry15_v_d, entry15_v_q : std_ulogic; +signal entry15_thdid_d, entry15_thdid_q : std_ulogic_vector(0 to 3); +signal entry15_class_d, entry15_class_q : std_ulogic_vector(0 to 1); +signal entry15_extclass_d, entry15_extclass_q : std_ulogic_vector(0 to 1); +signal entry15_hv_d, entry15_hv_q : std_ulogic; +signal entry15_ds_d, entry15_ds_q : std_ulogic; +signal entry15_pid_d, entry15_pid_q : std_ulogic_vector(0 to 7); +signal entry15_cmpmask_d, entry15_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry15_parity_d, entry15_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry15_sel : std_ulogic_vector(0 to 1); +signal entry15_inval : std_ulogic; +signal entry15_v_muxsel : std_ulogic_vector(0 to 1); +signal entry15_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry15_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry16_epn_d, entry16_epn_q : std_ulogic_vector(0 to 51); +signal entry16_xbit_d, entry16_xbit_q : std_ulogic; +signal entry16_size_d, entry16_size_q : std_ulogic_vector(0 to 2); +signal entry16_v_d, entry16_v_q : std_ulogic; +signal entry16_thdid_d, entry16_thdid_q : std_ulogic_vector(0 to 3); +signal entry16_class_d, entry16_class_q : std_ulogic_vector(0 to 1); +signal entry16_extclass_d, entry16_extclass_q : std_ulogic_vector(0 to 1); +signal entry16_hv_d, entry16_hv_q : std_ulogic; +signal entry16_ds_d, entry16_ds_q : std_ulogic; +signal entry16_pid_d, entry16_pid_q : std_ulogic_vector(0 to 7); +signal entry16_cmpmask_d, entry16_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry16_parity_d, entry16_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry16_sel : std_ulogic_vector(0 to 1); +signal entry16_inval : std_ulogic; +signal entry16_v_muxsel : std_ulogic_vector(0 to 1); +signal entry16_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry16_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry17_epn_d, entry17_epn_q : std_ulogic_vector(0 to 51); +signal entry17_xbit_d, entry17_xbit_q : std_ulogic; +signal entry17_size_d, entry17_size_q : std_ulogic_vector(0 to 2); +signal entry17_v_d, entry17_v_q : std_ulogic; +signal entry17_thdid_d, entry17_thdid_q : std_ulogic_vector(0 to 3); +signal entry17_class_d, entry17_class_q : std_ulogic_vector(0 to 1); +signal entry17_extclass_d, entry17_extclass_q : std_ulogic_vector(0 to 1); +signal entry17_hv_d, entry17_hv_q : std_ulogic; +signal entry17_ds_d, entry17_ds_q : std_ulogic; +signal entry17_pid_d, entry17_pid_q : std_ulogic_vector(0 to 7); +signal entry17_cmpmask_d, entry17_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry17_parity_d, entry17_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry17_sel : std_ulogic_vector(0 to 1); +signal entry17_inval : std_ulogic; +signal entry17_v_muxsel : std_ulogic_vector(0 to 1); +signal entry17_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry17_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry18_epn_d, entry18_epn_q : std_ulogic_vector(0 to 51); +signal entry18_xbit_d, entry18_xbit_q : std_ulogic; +signal entry18_size_d, entry18_size_q : std_ulogic_vector(0 to 2); +signal entry18_v_d, entry18_v_q : std_ulogic; +signal entry18_thdid_d, entry18_thdid_q : std_ulogic_vector(0 to 3); +signal entry18_class_d, entry18_class_q : std_ulogic_vector(0 to 1); +signal entry18_extclass_d, entry18_extclass_q : std_ulogic_vector(0 to 1); +signal entry18_hv_d, entry18_hv_q : std_ulogic; +signal entry18_ds_d, entry18_ds_q : std_ulogic; +signal entry18_pid_d, entry18_pid_q : std_ulogic_vector(0 to 7); +signal entry18_cmpmask_d, entry18_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry18_parity_d, entry18_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry18_sel : std_ulogic_vector(0 to 1); +signal entry18_inval : std_ulogic; +signal entry18_v_muxsel : std_ulogic_vector(0 to 1); +signal entry18_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry18_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry19_epn_d, entry19_epn_q : std_ulogic_vector(0 to 51); +signal entry19_xbit_d, entry19_xbit_q : std_ulogic; +signal entry19_size_d, entry19_size_q : std_ulogic_vector(0 to 2); +signal entry19_v_d, entry19_v_q : std_ulogic; +signal entry19_thdid_d, entry19_thdid_q : std_ulogic_vector(0 to 3); +signal entry19_class_d, entry19_class_q : std_ulogic_vector(0 to 1); +signal entry19_extclass_d, entry19_extclass_q : std_ulogic_vector(0 to 1); +signal entry19_hv_d, entry19_hv_q : std_ulogic; +signal entry19_ds_d, entry19_ds_q : std_ulogic; +signal entry19_pid_d, entry19_pid_q : std_ulogic_vector(0 to 7); +signal entry19_cmpmask_d, entry19_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry19_parity_d, entry19_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry19_sel : std_ulogic_vector(0 to 1); +signal entry19_inval : std_ulogic; +signal entry19_v_muxsel : std_ulogic_vector(0 to 1); +signal entry19_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry19_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry20_epn_d, entry20_epn_q : std_ulogic_vector(0 to 51); +signal entry20_xbit_d, entry20_xbit_q : std_ulogic; +signal entry20_size_d, entry20_size_q : std_ulogic_vector(0 to 2); +signal entry20_v_d, entry20_v_q : std_ulogic; +signal entry20_thdid_d, entry20_thdid_q : std_ulogic_vector(0 to 3); +signal entry20_class_d, entry20_class_q : std_ulogic_vector(0 to 1); +signal entry20_extclass_d, entry20_extclass_q : std_ulogic_vector(0 to 1); +signal entry20_hv_d, entry20_hv_q : std_ulogic; +signal entry20_ds_d, entry20_ds_q : std_ulogic; +signal entry20_pid_d, entry20_pid_q : std_ulogic_vector(0 to 7); +signal entry20_cmpmask_d, entry20_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry20_parity_d, entry20_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry20_sel : std_ulogic_vector(0 to 1); +signal entry20_inval : std_ulogic; +signal entry20_v_muxsel : std_ulogic_vector(0 to 1); +signal entry20_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry20_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry21_epn_d, entry21_epn_q : std_ulogic_vector(0 to 51); +signal entry21_xbit_d, entry21_xbit_q : std_ulogic; +signal entry21_size_d, entry21_size_q : std_ulogic_vector(0 to 2); +signal entry21_v_d, entry21_v_q : std_ulogic; +signal entry21_thdid_d, entry21_thdid_q : std_ulogic_vector(0 to 3); +signal entry21_class_d, entry21_class_q : std_ulogic_vector(0 to 1); +signal entry21_extclass_d, entry21_extclass_q : std_ulogic_vector(0 to 1); +signal entry21_hv_d, entry21_hv_q : std_ulogic; +signal entry21_ds_d, entry21_ds_q : std_ulogic; +signal entry21_pid_d, entry21_pid_q : std_ulogic_vector(0 to 7); +signal entry21_cmpmask_d, entry21_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry21_parity_d, entry21_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry21_sel : std_ulogic_vector(0 to 1); +signal entry21_inval : std_ulogic; +signal entry21_v_muxsel : std_ulogic_vector(0 to 1); +signal entry21_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry21_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry22_epn_d, entry22_epn_q : std_ulogic_vector(0 to 51); +signal entry22_xbit_d, entry22_xbit_q : std_ulogic; +signal entry22_size_d, entry22_size_q : std_ulogic_vector(0 to 2); +signal entry22_v_d, entry22_v_q : std_ulogic; +signal entry22_thdid_d, entry22_thdid_q : std_ulogic_vector(0 to 3); +signal entry22_class_d, entry22_class_q : std_ulogic_vector(0 to 1); +signal entry22_extclass_d, entry22_extclass_q : std_ulogic_vector(0 to 1); +signal entry22_hv_d, entry22_hv_q : std_ulogic; +signal entry22_ds_d, entry22_ds_q : std_ulogic; +signal entry22_pid_d, entry22_pid_q : std_ulogic_vector(0 to 7); +signal entry22_cmpmask_d, entry22_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry22_parity_d, entry22_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry22_sel : std_ulogic_vector(0 to 1); +signal entry22_inval : std_ulogic; +signal entry22_v_muxsel : std_ulogic_vector(0 to 1); +signal entry22_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry22_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry23_epn_d, entry23_epn_q : std_ulogic_vector(0 to 51); +signal entry23_xbit_d, entry23_xbit_q : std_ulogic; +signal entry23_size_d, entry23_size_q : std_ulogic_vector(0 to 2); +signal entry23_v_d, entry23_v_q : std_ulogic; +signal entry23_thdid_d, entry23_thdid_q : std_ulogic_vector(0 to 3); +signal entry23_class_d, entry23_class_q : std_ulogic_vector(0 to 1); +signal entry23_extclass_d, entry23_extclass_q : std_ulogic_vector(0 to 1); +signal entry23_hv_d, entry23_hv_q : std_ulogic; +signal entry23_ds_d, entry23_ds_q : std_ulogic; +signal entry23_pid_d, entry23_pid_q : std_ulogic_vector(0 to 7); +signal entry23_cmpmask_d, entry23_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry23_parity_d, entry23_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry23_sel : std_ulogic_vector(0 to 1); +signal entry23_inval : std_ulogic; +signal entry23_v_muxsel : std_ulogic_vector(0 to 1); +signal entry23_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry23_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry24_epn_d, entry24_epn_q : std_ulogic_vector(0 to 51); +signal entry24_xbit_d, entry24_xbit_q : std_ulogic; +signal entry24_size_d, entry24_size_q : std_ulogic_vector(0 to 2); +signal entry24_v_d, entry24_v_q : std_ulogic; +signal entry24_thdid_d, entry24_thdid_q : std_ulogic_vector(0 to 3); +signal entry24_class_d, entry24_class_q : std_ulogic_vector(0 to 1); +signal entry24_extclass_d, entry24_extclass_q : std_ulogic_vector(0 to 1); +signal entry24_hv_d, entry24_hv_q : std_ulogic; +signal entry24_ds_d, entry24_ds_q : std_ulogic; +signal entry24_pid_d, entry24_pid_q : std_ulogic_vector(0 to 7); +signal entry24_cmpmask_d, entry24_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry24_parity_d, entry24_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry24_sel : std_ulogic_vector(0 to 1); +signal entry24_inval : std_ulogic; +signal entry24_v_muxsel : std_ulogic_vector(0 to 1); +signal entry24_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry24_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry25_epn_d, entry25_epn_q : std_ulogic_vector(0 to 51); +signal entry25_xbit_d, entry25_xbit_q : std_ulogic; +signal entry25_size_d, entry25_size_q : std_ulogic_vector(0 to 2); +signal entry25_v_d, entry25_v_q : std_ulogic; +signal entry25_thdid_d, entry25_thdid_q : std_ulogic_vector(0 to 3); +signal entry25_class_d, entry25_class_q : std_ulogic_vector(0 to 1); +signal entry25_extclass_d, entry25_extclass_q : std_ulogic_vector(0 to 1); +signal entry25_hv_d, entry25_hv_q : std_ulogic; +signal entry25_ds_d, entry25_ds_q : std_ulogic; +signal entry25_pid_d, entry25_pid_q : std_ulogic_vector(0 to 7); +signal entry25_cmpmask_d, entry25_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry25_parity_d, entry25_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry25_sel : std_ulogic_vector(0 to 1); +signal entry25_inval : std_ulogic; +signal entry25_v_muxsel : std_ulogic_vector(0 to 1); +signal entry25_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry25_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry26_epn_d, entry26_epn_q : std_ulogic_vector(0 to 51); +signal entry26_xbit_d, entry26_xbit_q : std_ulogic; +signal entry26_size_d, entry26_size_q : std_ulogic_vector(0 to 2); +signal entry26_v_d, entry26_v_q : std_ulogic; +signal entry26_thdid_d, entry26_thdid_q : std_ulogic_vector(0 to 3); +signal entry26_class_d, entry26_class_q : std_ulogic_vector(0 to 1); +signal entry26_extclass_d, entry26_extclass_q : std_ulogic_vector(0 to 1); +signal entry26_hv_d, entry26_hv_q : std_ulogic; +signal entry26_ds_d, entry26_ds_q : std_ulogic; +signal entry26_pid_d, entry26_pid_q : std_ulogic_vector(0 to 7); +signal entry26_cmpmask_d, entry26_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry26_parity_d, entry26_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry26_sel : std_ulogic_vector(0 to 1); +signal entry26_inval : std_ulogic; +signal entry26_v_muxsel : std_ulogic_vector(0 to 1); +signal entry26_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry26_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry27_epn_d, entry27_epn_q : std_ulogic_vector(0 to 51); +signal entry27_xbit_d, entry27_xbit_q : std_ulogic; +signal entry27_size_d, entry27_size_q : std_ulogic_vector(0 to 2); +signal entry27_v_d, entry27_v_q : std_ulogic; +signal entry27_thdid_d, entry27_thdid_q : std_ulogic_vector(0 to 3); +signal entry27_class_d, entry27_class_q : std_ulogic_vector(0 to 1); +signal entry27_extclass_d, entry27_extclass_q : std_ulogic_vector(0 to 1); +signal entry27_hv_d, entry27_hv_q : std_ulogic; +signal entry27_ds_d, entry27_ds_q : std_ulogic; +signal entry27_pid_d, entry27_pid_q : std_ulogic_vector(0 to 7); +signal entry27_cmpmask_d, entry27_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry27_parity_d, entry27_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry27_sel : std_ulogic_vector(0 to 1); +signal entry27_inval : std_ulogic; +signal entry27_v_muxsel : std_ulogic_vector(0 to 1); +signal entry27_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry27_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry28_epn_d, entry28_epn_q : std_ulogic_vector(0 to 51); +signal entry28_xbit_d, entry28_xbit_q : std_ulogic; +signal entry28_size_d, entry28_size_q : std_ulogic_vector(0 to 2); +signal entry28_v_d, entry28_v_q : std_ulogic; +signal entry28_thdid_d, entry28_thdid_q : std_ulogic_vector(0 to 3); +signal entry28_class_d, entry28_class_q : std_ulogic_vector(0 to 1); +signal entry28_extclass_d, entry28_extclass_q : std_ulogic_vector(0 to 1); +signal entry28_hv_d, entry28_hv_q : std_ulogic; +signal entry28_ds_d, entry28_ds_q : std_ulogic; +signal entry28_pid_d, entry28_pid_q : std_ulogic_vector(0 to 7); +signal entry28_cmpmask_d, entry28_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry28_parity_d, entry28_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry28_sel : std_ulogic_vector(0 to 1); +signal entry28_inval : std_ulogic; +signal entry28_v_muxsel : std_ulogic_vector(0 to 1); +signal entry28_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry28_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry29_epn_d, entry29_epn_q : std_ulogic_vector(0 to 51); +signal entry29_xbit_d, entry29_xbit_q : std_ulogic; +signal entry29_size_d, entry29_size_q : std_ulogic_vector(0 to 2); +signal entry29_v_d, entry29_v_q : std_ulogic; +signal entry29_thdid_d, entry29_thdid_q : std_ulogic_vector(0 to 3); +signal entry29_class_d, entry29_class_q : std_ulogic_vector(0 to 1); +signal entry29_extclass_d, entry29_extclass_q : std_ulogic_vector(0 to 1); +signal entry29_hv_d, entry29_hv_q : std_ulogic; +signal entry29_ds_d, entry29_ds_q : std_ulogic; +signal entry29_pid_d, entry29_pid_q : std_ulogic_vector(0 to 7); +signal entry29_cmpmask_d, entry29_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry29_parity_d, entry29_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry29_sel : std_ulogic_vector(0 to 1); +signal entry29_inval : std_ulogic; +signal entry29_v_muxsel : std_ulogic_vector(0 to 1); +signal entry29_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry29_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry30_epn_d, entry30_epn_q : std_ulogic_vector(0 to 51); +signal entry30_xbit_d, entry30_xbit_q : std_ulogic; +signal entry30_size_d, entry30_size_q : std_ulogic_vector(0 to 2); +signal entry30_v_d, entry30_v_q : std_ulogic; +signal entry30_thdid_d, entry30_thdid_q : std_ulogic_vector(0 to 3); +signal entry30_class_d, entry30_class_q : std_ulogic_vector(0 to 1); +signal entry30_extclass_d, entry30_extclass_q : std_ulogic_vector(0 to 1); +signal entry30_hv_d, entry30_hv_q : std_ulogic; +signal entry30_ds_d, entry30_ds_q : std_ulogic; +signal entry30_pid_d, entry30_pid_q : std_ulogic_vector(0 to 7); +signal entry30_cmpmask_d, entry30_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry30_parity_d, entry30_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry30_sel : std_ulogic_vector(0 to 1); +signal entry30_inval : std_ulogic; +signal entry30_v_muxsel : std_ulogic_vector(0 to 1); +signal entry30_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry30_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal entry31_epn_d, entry31_epn_q : std_ulogic_vector(0 to 51); +signal entry31_xbit_d, entry31_xbit_q : std_ulogic; +signal entry31_size_d, entry31_size_q : std_ulogic_vector(0 to 2); +signal entry31_v_d, entry31_v_q : std_ulogic; +signal entry31_thdid_d, entry31_thdid_q : std_ulogic_vector(0 to 3); +signal entry31_class_d, entry31_class_q : std_ulogic_vector(0 to 1); +signal entry31_extclass_d, entry31_extclass_q : std_ulogic_vector(0 to 1); +signal entry31_hv_d, entry31_hv_q : std_ulogic; +signal entry31_ds_d, entry31_ds_q : std_ulogic; +signal entry31_pid_d, entry31_pid_q : std_ulogic_vector(0 to 7); +signal entry31_cmpmask_d, entry31_cmpmask_q : std_ulogic_vector(0 to 8); +signal entry31_parity_d, entry31_parity_q : std_ulogic_vector(0 to 9); +signal wr_entry31_sel : std_ulogic_vector(0 to 1); +signal entry31_inval : std_ulogic; +signal entry31_v_muxsel : std_ulogic_vector(0 to 1); +signal entry31_cam_vec : std_ulogic_vector(0 to cam_data_width-1); +signal entry31_array_vec : std_ulogic_vector(0 to array_data_width-1); +signal cam_cmp_data_muxsel : std_ulogic_vector(0 to 5); +signal rd_cam_data_muxsel : std_ulogic_vector(0 to 5); +signal cam_cmp_data_np1 : std_ulogic_vector(0 to cam_data_width-1); +signal array_cmp_data_np1 : std_ulogic_vector(0 to array_data_width-1); +signal wr_array_data_bram : std_ulogic_vector(0 to 72); +signal rd_array_data_d_std : std_logic_vector(0 to 72); +signal array_cmp_data_bram_std : std_logic_vector(0 to 55); +signal array_cmp_data_bramp_std : std_logic_vector(66 to 72); +-- latch signals +signal rd_array_data_d : std_ulogic_vector(0 to array_data_width-1); +signal rd_array_data_q : std_ulogic_vector(0 to array_data_width-1); +signal cam_cmp_data_d : std_ulogic_vector(0 to cam_data_width-1); +signal cam_cmp_data_q : std_ulogic_vector(0 to cam_data_width-1); +signal cam_cmp_parity_d : std_ulogic_vector(0 to 9); +signal cam_cmp_parity_q : std_ulogic_vector(0 to 9); +signal rd_cam_data_d : std_ulogic_vector(0 to cam_data_width-1); +signal rd_cam_data_q : std_ulogic_vector(0 to cam_data_width-1); +signal entry_match_d : std_ulogic_vector(0 to num_entry-1); +signal entry_match_q : std_ulogic_vector(0 to num_entry-1); +signal match_vec : std_ulogic_vector(0 to num_entry-1); +signal cam_hit_entry_d : std_ulogic_vector(0 to num_entry_log2-1); +signal cam_hit_entry_q : std_ulogic_vector(0 to num_entry_log2-1); +signal cam_hit_d : std_ulogic; +signal cam_hit_q : std_ulogic; +signal toggle_d : std_ulogic; +signal toggle_q : std_ulogic; +signal toggle2x_d : std_ulogic; +signal toggle2x_q : std_ulogic; +begin + +clk <= not nclk.clk; +clk2x <= nclk.clk2x; +rlatch: process (clk) +begin +if(rising_edge(clk)) then +sreset_q <= nclk.sreset; +end if; +end process; +tlatch: process (nclk.clk,sreset_q) +begin +if(rising_edge(nclk.clk)) then +if (sreset_q = '1') then +toggle_q <= '1'; +else +toggle_q <= toggle_d; +end if; +end if; +end process; +flatch: process (nclk.clk2x) +begin +if(rising_edge(nclk.clk2x)) then +toggle2x_q <= toggle2x_d; +gate_fq <= gate_d; +end if; +end process; +toggle_d <= not toggle_q; +toggle2x_d <= toggle_q; +gate_d <= toggle_q xor toggle2x_q; +slatch: process (nclk,sreset_q) +begin +if(rising_edge(nclk.clk)) then +if (sreset_q = '1') then +cam_cmp_data_q <= (others => '0'); +cam_cmp_parity_q <= (others => '0'); +rd_cam_data_q <= (others => '0'); +rd_array_data_q <= (others => '0'); +entry_match_q <= (others => '0'); +cam_hit_entry_q <= (others => '0'); +cam_hit_q <= '0'; +comp_addr_np1_q <= (others => '0'); +rpn_np2_q <= (others => '0'); +attr_np2_q <= (others => '0'); +entry0_size_q <= (others => '0'); +entry0_xbit_q <= '0'; +entry0_epn_q <= (others => '0'); +entry0_class_q <= (others => '0'); +entry0_extclass_q <= (others => '0'); +entry0_hv_q <= '0'; +entry0_ds_q <= '0'; +entry0_thdid_q <= (others => '0'); +entry0_pid_q <= (others => '0'); +entry0_v_q <= '0'; +entry0_parity_q <= (others => '0'); +entry0_cmpmask_q <= (others => '0'); +entry1_size_q <= (others => '0'); +entry1_xbit_q <= '0'; +entry1_epn_q <= (others => '0'); +entry1_class_q <= (others => '0'); +entry1_extclass_q <= (others => '0'); +entry1_hv_q <= '0'; +entry1_ds_q <= '0'; +entry1_thdid_q <= (others => '0'); +entry1_pid_q <= (others => '0'); +entry1_v_q <= '0'; +entry1_parity_q <= (others => '0'); +entry1_cmpmask_q <= (others => '0'); +entry2_size_q <= (others => '0'); +entry2_xbit_q <= '0'; +entry2_epn_q <= (others => '0'); +entry2_class_q <= (others => '0'); +entry2_extclass_q <= (others => '0'); +entry2_hv_q <= '0'; +entry2_ds_q <= '0'; +entry2_thdid_q <= (others => '0'); +entry2_pid_q <= (others => '0'); +entry2_v_q <= '0'; +entry2_parity_q <= (others => '0'); +entry2_cmpmask_q <= (others => '0'); +entry3_size_q <= (others => '0'); +entry3_xbit_q <= '0'; +entry3_epn_q <= (others => '0'); +entry3_class_q <= (others => '0'); +entry3_extclass_q <= (others => '0'); +entry3_hv_q <= '0'; +entry3_ds_q <= '0'; +entry3_thdid_q <= (others => '0'); +entry3_pid_q <= (others => '0'); +entry3_v_q <= '0'; +entry3_parity_q <= (others => '0'); +entry3_cmpmask_q <= (others => '0'); +entry4_size_q <= (others => '0'); +entry4_xbit_q <= '0'; +entry4_epn_q <= (others => '0'); +entry4_class_q <= (others => '0'); +entry4_extclass_q <= (others => '0'); +entry4_hv_q <= '0'; +entry4_ds_q <= '0'; +entry4_thdid_q <= (others => '0'); +entry4_pid_q <= (others => '0'); +entry4_v_q <= '0'; +entry4_parity_q <= (others => '0'); +entry4_cmpmask_q <= (others => '0'); +entry5_size_q <= (others => '0'); +entry5_xbit_q <= '0'; +entry5_epn_q <= (others => '0'); +entry5_class_q <= (others => '0'); +entry5_extclass_q <= (others => '0'); +entry5_hv_q <= '0'; +entry5_ds_q <= '0'; +entry5_thdid_q <= (others => '0'); +entry5_pid_q <= (others => '0'); +entry5_v_q <= '0'; +entry5_parity_q <= (others => '0'); +entry5_cmpmask_q <= (others => '0'); +entry6_size_q <= (others => '0'); +entry6_xbit_q <= '0'; +entry6_epn_q <= (others => '0'); +entry6_class_q <= (others => '0'); +entry6_extclass_q <= (others => '0'); +entry6_hv_q <= '0'; +entry6_ds_q <= '0'; +entry6_thdid_q <= (others => '0'); +entry6_pid_q <= (others => '0'); +entry6_v_q <= '0'; +entry6_parity_q <= (others => '0'); +entry6_cmpmask_q <= (others => '0'); +entry7_size_q <= (others => '0'); +entry7_xbit_q <= '0'; +entry7_epn_q <= (others => '0'); +entry7_class_q <= (others => '0'); +entry7_extclass_q <= (others => '0'); +entry7_hv_q <= '0'; +entry7_ds_q <= '0'; +entry7_thdid_q <= (others => '0'); +entry7_pid_q <= (others => '0'); +entry7_v_q <= '0'; +entry7_parity_q <= (others => '0'); +entry7_cmpmask_q <= (others => '0'); +entry8_size_q <= (others => '0'); +entry8_xbit_q <= '0'; +entry8_epn_q <= (others => '0'); +entry8_class_q <= (others => '0'); +entry8_extclass_q <= (others => '0'); +entry8_hv_q <= '0'; +entry8_ds_q <= '0'; +entry8_thdid_q <= (others => '0'); +entry8_pid_q <= (others => '0'); +entry8_v_q <= '0'; +entry8_parity_q <= (others => '0'); +entry8_cmpmask_q <= (others => '0'); +entry9_size_q <= (others => '0'); +entry9_xbit_q <= '0'; +entry9_epn_q <= (others => '0'); +entry9_class_q <= (others => '0'); +entry9_extclass_q <= (others => '0'); +entry9_hv_q <= '0'; +entry9_ds_q <= '0'; +entry9_thdid_q <= (others => '0'); +entry9_pid_q <= (others => '0'); +entry9_v_q <= '0'; +entry9_parity_q <= (others => '0'); +entry9_cmpmask_q <= (others => '0'); +entry10_size_q <= (others => '0'); +entry10_xbit_q <= '0'; +entry10_epn_q <= (others => '0'); +entry10_class_q <= (others => '0'); +entry10_extclass_q <= (others => '0'); +entry10_hv_q <= '0'; +entry10_ds_q <= '0'; +entry10_thdid_q <= (others => '0'); +entry10_pid_q <= (others => '0'); +entry10_v_q <= '0'; +entry10_parity_q <= (others => '0'); +entry10_cmpmask_q <= (others => '0'); +entry11_size_q <= (others => '0'); +entry11_xbit_q <= '0'; +entry11_epn_q <= (others => '0'); +entry11_class_q <= (others => '0'); +entry11_extclass_q <= (others => '0'); +entry11_hv_q <= '0'; +entry11_ds_q <= '0'; +entry11_thdid_q <= (others => '0'); +entry11_pid_q <= (others => '0'); +entry11_v_q <= '0'; +entry11_parity_q <= (others => '0'); +entry11_cmpmask_q <= (others => '0'); +entry12_size_q <= (others => '0'); +entry12_xbit_q <= '0'; +entry12_epn_q <= (others => '0'); +entry12_class_q <= (others => '0'); +entry12_extclass_q <= (others => '0'); +entry12_hv_q <= '0'; +entry12_ds_q <= '0'; +entry12_thdid_q <= (others => '0'); +entry12_pid_q <= (others => '0'); +entry12_v_q <= '0'; +entry12_parity_q <= (others => '0'); +entry12_cmpmask_q <= (others => '0'); +entry13_size_q <= (others => '0'); +entry13_xbit_q <= '0'; +entry13_epn_q <= (others => '0'); +entry13_class_q <= (others => '0'); +entry13_extclass_q <= (others => '0'); +entry13_hv_q <= '0'; +entry13_ds_q <= '0'; +entry13_thdid_q <= (others => '0'); +entry13_pid_q <= (others => '0'); +entry13_v_q <= '0'; +entry13_parity_q <= (others => '0'); +entry13_cmpmask_q <= (others => '0'); +entry14_size_q <= (others => '0'); +entry14_xbit_q <= '0'; +entry14_epn_q <= (others => '0'); +entry14_class_q <= (others => '0'); +entry14_extclass_q <= (others => '0'); +entry14_hv_q <= '0'; +entry14_ds_q <= '0'; +entry14_thdid_q <= (others => '0'); +entry14_pid_q <= (others => '0'); +entry14_v_q <= '0'; +entry14_parity_q <= (others => '0'); +entry14_cmpmask_q <= (others => '0'); +entry15_size_q <= (others => '0'); +entry15_xbit_q <= '0'; +entry15_epn_q <= (others => '0'); +entry15_class_q <= (others => '0'); +entry15_extclass_q <= (others => '0'); +entry15_hv_q <= '0'; +entry15_ds_q <= '0'; +entry15_thdid_q <= (others => '0'); +entry15_pid_q <= (others => '0'); +entry15_v_q <= '0'; +entry15_parity_q <= (others => '0'); +entry15_cmpmask_q <= (others => '0'); +entry16_size_q <= (others => '0'); +entry16_xbit_q <= '0'; +entry16_epn_q <= (others => '0'); +entry16_class_q <= (others => '0'); +entry16_extclass_q <= (others => '0'); +entry16_hv_q <= '0'; +entry16_ds_q <= '0'; +entry16_thdid_q <= (others => '0'); +entry16_pid_q <= (others => '0'); +entry16_v_q <= '0'; +entry16_parity_q <= (others => '0'); +entry16_cmpmask_q <= (others => '0'); +entry17_size_q <= (others => '0'); +entry17_xbit_q <= '0'; +entry17_epn_q <= (others => '0'); +entry17_class_q <= (others => '0'); +entry17_extclass_q <= (others => '0'); +entry17_hv_q <= '0'; +entry17_ds_q <= '0'; +entry17_thdid_q <= (others => '0'); +entry17_pid_q <= (others => '0'); +entry17_v_q <= '0'; +entry17_parity_q <= (others => '0'); +entry17_cmpmask_q <= (others => '0'); +entry18_size_q <= (others => '0'); +entry18_xbit_q <= '0'; +entry18_epn_q <= (others => '0'); +entry18_class_q <= (others => '0'); +entry18_extclass_q <= (others => '0'); +entry18_hv_q <= '0'; +entry18_ds_q <= '0'; +entry18_thdid_q <= (others => '0'); +entry18_pid_q <= (others => '0'); +entry18_v_q <= '0'; +entry18_parity_q <= (others => '0'); +entry18_cmpmask_q <= (others => '0'); +entry19_size_q <= (others => '0'); +entry19_xbit_q <= '0'; +entry19_epn_q <= (others => '0'); +entry19_class_q <= (others => '0'); +entry19_extclass_q <= (others => '0'); +entry19_hv_q <= '0'; +entry19_ds_q <= '0'; +entry19_thdid_q <= (others => '0'); +entry19_pid_q <= (others => '0'); +entry19_v_q <= '0'; +entry19_parity_q <= (others => '0'); +entry19_cmpmask_q <= (others => '0'); +entry20_size_q <= (others => '0'); +entry20_xbit_q <= '0'; +entry20_epn_q <= (others => '0'); +entry20_class_q <= (others => '0'); +entry20_extclass_q <= (others => '0'); +entry20_hv_q <= '0'; +entry20_ds_q <= '0'; +entry20_thdid_q <= (others => '0'); +entry20_pid_q <= (others => '0'); +entry20_v_q <= '0'; +entry20_parity_q <= (others => '0'); +entry20_cmpmask_q <= (others => '0'); +entry21_size_q <= (others => '0'); +entry21_xbit_q <= '0'; +entry21_epn_q <= (others => '0'); +entry21_class_q <= (others => '0'); +entry21_extclass_q <= (others => '0'); +entry21_hv_q <= '0'; +entry21_ds_q <= '0'; +entry21_thdid_q <= (others => '0'); +entry21_pid_q <= (others => '0'); +entry21_v_q <= '0'; +entry21_parity_q <= (others => '0'); +entry21_cmpmask_q <= (others => '0'); +entry22_size_q <= (others => '0'); +entry22_xbit_q <= '0'; +entry22_epn_q <= (others => '0'); +entry22_class_q <= (others => '0'); +entry22_extclass_q <= (others => '0'); +entry22_hv_q <= '0'; +entry22_ds_q <= '0'; +entry22_thdid_q <= (others => '0'); +entry22_pid_q <= (others => '0'); +entry22_v_q <= '0'; +entry22_parity_q <= (others => '0'); +entry22_cmpmask_q <= (others => '0'); +entry23_size_q <= (others => '0'); +entry23_xbit_q <= '0'; +entry23_epn_q <= (others => '0'); +entry23_class_q <= (others => '0'); +entry23_extclass_q <= (others => '0'); +entry23_hv_q <= '0'; +entry23_ds_q <= '0'; +entry23_thdid_q <= (others => '0'); +entry23_pid_q <= (others => '0'); +entry23_v_q <= '0'; +entry23_parity_q <= (others => '0'); +entry23_cmpmask_q <= (others => '0'); +entry24_size_q <= (others => '0'); +entry24_xbit_q <= '0'; +entry24_epn_q <= (others => '0'); +entry24_class_q <= (others => '0'); +entry24_extclass_q <= (others => '0'); +entry24_hv_q <= '0'; +entry24_ds_q <= '0'; +entry24_thdid_q <= (others => '0'); +entry24_pid_q <= (others => '0'); +entry24_v_q <= '0'; +entry24_parity_q <= (others => '0'); +entry24_cmpmask_q <= (others => '0'); +entry25_size_q <= (others => '0'); +entry25_xbit_q <= '0'; +entry25_epn_q <= (others => '0'); +entry25_class_q <= (others => '0'); +entry25_extclass_q <= (others => '0'); +entry25_hv_q <= '0'; +entry25_ds_q <= '0'; +entry25_thdid_q <= (others => '0'); +entry25_pid_q <= (others => '0'); +entry25_v_q <= '0'; +entry25_parity_q <= (others => '0'); +entry25_cmpmask_q <= (others => '0'); +entry26_size_q <= (others => '0'); +entry26_xbit_q <= '0'; +entry26_epn_q <= (others => '0'); +entry26_class_q <= (others => '0'); +entry26_extclass_q <= (others => '0'); +entry26_hv_q <= '0'; +entry26_ds_q <= '0'; +entry26_thdid_q <= (others => '0'); +entry26_pid_q <= (others => '0'); +entry26_v_q <= '0'; +entry26_parity_q <= (others => '0'); +entry26_cmpmask_q <= (others => '0'); +entry27_size_q <= (others => '0'); +entry27_xbit_q <= '0'; +entry27_epn_q <= (others => '0'); +entry27_class_q <= (others => '0'); +entry27_extclass_q <= (others => '0'); +entry27_hv_q <= '0'; +entry27_ds_q <= '0'; +entry27_thdid_q <= (others => '0'); +entry27_pid_q <= (others => '0'); +entry27_v_q <= '0'; +entry27_parity_q <= (others => '0'); +entry27_cmpmask_q <= (others => '0'); +entry28_size_q <= (others => '0'); +entry28_xbit_q <= '0'; +entry28_epn_q <= (others => '0'); +entry28_class_q <= (others => '0'); +entry28_extclass_q <= (others => '0'); +entry28_hv_q <= '0'; +entry28_ds_q <= '0'; +entry28_thdid_q <= (others => '0'); +entry28_pid_q <= (others => '0'); +entry28_v_q <= '0'; +entry28_parity_q <= (others => '0'); +entry28_cmpmask_q <= (others => '0'); +entry29_size_q <= (others => '0'); +entry29_xbit_q <= '0'; +entry29_epn_q <= (others => '0'); +entry29_class_q <= (others => '0'); +entry29_extclass_q <= (others => '0'); +entry29_hv_q <= '0'; +entry29_ds_q <= '0'; +entry29_thdid_q <= (others => '0'); +entry29_pid_q <= (others => '0'); +entry29_v_q <= '0'; +entry29_parity_q <= (others => '0'); +entry29_cmpmask_q <= (others => '0'); +entry30_size_q <= (others => '0'); +entry30_xbit_q <= '0'; +entry30_epn_q <= (others => '0'); +entry30_class_q <= (others => '0'); +entry30_extclass_q <= (others => '0'); +entry30_hv_q <= '0'; +entry30_ds_q <= '0'; +entry30_thdid_q <= (others => '0'); +entry30_pid_q <= (others => '0'); +entry30_v_q <= '0'; +entry30_parity_q <= (others => '0'); +entry30_cmpmask_q <= (others => '0'); +entry31_size_q <= (others => '0'); +entry31_xbit_q <= '0'; +entry31_epn_q <= (others => '0'); +entry31_class_q <= (others => '0'); +entry31_extclass_q <= (others => '0'); +entry31_hv_q <= '0'; +entry31_ds_q <= '0'; +entry31_thdid_q <= (others => '0'); +entry31_pid_q <= (others => '0'); +entry31_v_q <= '0'; +entry31_parity_q <= (others => '0'); +entry31_cmpmask_q <= (others => '0'); +else +cam_cmp_data_q <= cam_cmp_data_d; +rd_cam_data_q <= rd_cam_data_d; +rd_array_data_q <= rd_array_data_d; +entry_match_q <= entry_match_d; +cam_hit_entry_q <= cam_hit_entry_d; +cam_hit_q <= cam_hit_d; +cam_cmp_parity_q <= cam_cmp_parity_d; +comp_addr_np1_q <= comp_addr_np1_d; +rpn_np2_q <= rpn_np2_d; +attr_np2_q <= attr_np2_d; +entry0_size_q <= entry0_size_d; +entry0_xbit_q <= entry0_xbit_d; +entry0_epn_q <= entry0_epn_d; +entry0_class_q <= entry0_class_d; +entry0_extclass_q <= entry0_extclass_d; +entry0_hv_q <= entry0_hv_d; +entry0_ds_q <= entry0_ds_d; +entry0_thdid_q <= entry0_thdid_d; +entry0_pid_q <= entry0_pid_d; +entry0_v_q <= entry0_v_d; +entry0_parity_q <= entry0_parity_d; +entry0_cmpmask_q <= entry0_cmpmask_d; +entry1_size_q <= entry1_size_d; +entry1_xbit_q <= entry1_xbit_d; +entry1_epn_q <= entry1_epn_d; +entry1_class_q <= entry1_class_d; +entry1_extclass_q <= entry1_extclass_d; +entry1_hv_q <= entry1_hv_d; +entry1_ds_q <= entry1_ds_d; +entry1_thdid_q <= entry1_thdid_d; +entry1_pid_q <= entry1_pid_d; +entry1_v_q <= entry1_v_d; +entry1_parity_q <= entry1_parity_d; +entry1_cmpmask_q <= entry1_cmpmask_d; +entry2_size_q <= entry2_size_d; +entry2_xbit_q <= entry2_xbit_d; +entry2_epn_q <= entry2_epn_d; +entry2_class_q <= entry2_class_d; +entry2_extclass_q <= entry2_extclass_d; +entry2_hv_q <= entry2_hv_d; +entry2_ds_q <= entry2_ds_d; +entry2_thdid_q <= entry2_thdid_d; +entry2_pid_q <= entry2_pid_d; +entry2_v_q <= entry2_v_d; +entry2_parity_q <= entry2_parity_d; +entry2_cmpmask_q <= entry2_cmpmask_d; +entry3_size_q <= entry3_size_d; +entry3_xbit_q <= entry3_xbit_d; +entry3_epn_q <= entry3_epn_d; +entry3_class_q <= entry3_class_d; +entry3_extclass_q <= entry3_extclass_d; +entry3_hv_q <= entry3_hv_d; +entry3_ds_q <= entry3_ds_d; +entry3_thdid_q <= entry3_thdid_d; +entry3_pid_q <= entry3_pid_d; +entry3_v_q <= entry3_v_d; +entry3_parity_q <= entry3_parity_d; +entry3_cmpmask_q <= entry3_cmpmask_d; +entry4_size_q <= entry4_size_d; +entry4_xbit_q <= entry4_xbit_d; +entry4_epn_q <= entry4_epn_d; +entry4_class_q <= entry4_class_d; +entry4_extclass_q <= entry4_extclass_d; +entry4_hv_q <= entry4_hv_d; +entry4_ds_q <= entry4_ds_d; +entry4_thdid_q <= entry4_thdid_d; +entry4_pid_q <= entry4_pid_d; +entry4_v_q <= entry4_v_d; +entry4_parity_q <= entry4_parity_d; +entry4_cmpmask_q <= entry4_cmpmask_d; +entry5_size_q <= entry5_size_d; +entry5_xbit_q <= entry5_xbit_d; +entry5_epn_q <= entry5_epn_d; +entry5_class_q <= entry5_class_d; +entry5_extclass_q <= entry5_extclass_d; +entry5_hv_q <= entry5_hv_d; +entry5_ds_q <= entry5_ds_d; +entry5_thdid_q <= entry5_thdid_d; +entry5_pid_q <= entry5_pid_d; +entry5_v_q <= entry5_v_d; +entry5_parity_q <= entry5_parity_d; +entry5_cmpmask_q <= entry5_cmpmask_d; +entry6_size_q <= entry6_size_d; +entry6_xbit_q <= entry6_xbit_d; +entry6_epn_q <= entry6_epn_d; +entry6_class_q <= entry6_class_d; +entry6_extclass_q <= entry6_extclass_d; +entry6_hv_q <= entry6_hv_d; +entry6_ds_q <= entry6_ds_d; +entry6_thdid_q <= entry6_thdid_d; +entry6_pid_q <= entry6_pid_d; +entry6_v_q <= entry6_v_d; +entry6_parity_q <= entry6_parity_d; +entry6_cmpmask_q <= entry6_cmpmask_d; +entry7_size_q <= entry7_size_d; +entry7_xbit_q <= entry7_xbit_d; +entry7_epn_q <= entry7_epn_d; +entry7_class_q <= entry7_class_d; +entry7_extclass_q <= entry7_extclass_d; +entry7_hv_q <= entry7_hv_d; +entry7_ds_q <= entry7_ds_d; +entry7_thdid_q <= entry7_thdid_d; +entry7_pid_q <= entry7_pid_d; +entry7_v_q <= entry7_v_d; +entry7_parity_q <= entry7_parity_d; +entry7_cmpmask_q <= entry7_cmpmask_d; +entry8_size_q <= entry8_size_d; +entry8_xbit_q <= entry8_xbit_d; +entry8_epn_q <= entry8_epn_d; +entry8_class_q <= entry8_class_d; +entry8_extclass_q <= entry8_extclass_d; +entry8_hv_q <= entry8_hv_d; +entry8_ds_q <= entry8_ds_d; +entry8_thdid_q <= entry8_thdid_d; +entry8_pid_q <= entry8_pid_d; +entry8_v_q <= entry8_v_d; +entry8_parity_q <= entry8_parity_d; +entry8_cmpmask_q <= entry8_cmpmask_d; +entry9_size_q <= entry9_size_d; +entry9_xbit_q <= entry9_xbit_d; +entry9_epn_q <= entry9_epn_d; +entry9_class_q <= entry9_class_d; +entry9_extclass_q <= entry9_extclass_d; +entry9_hv_q <= entry9_hv_d; +entry9_ds_q <= entry9_ds_d; +entry9_thdid_q <= entry9_thdid_d; +entry9_pid_q <= entry9_pid_d; +entry9_v_q <= entry9_v_d; +entry9_parity_q <= entry9_parity_d; +entry9_cmpmask_q <= entry9_cmpmask_d; +entry10_size_q <= entry10_size_d; +entry10_xbit_q <= entry10_xbit_d; +entry10_epn_q <= entry10_epn_d; +entry10_class_q <= entry10_class_d; +entry10_extclass_q <= entry10_extclass_d; +entry10_hv_q <= entry10_hv_d; +entry10_ds_q <= entry10_ds_d; +entry10_thdid_q <= entry10_thdid_d; +entry10_pid_q <= entry10_pid_d; +entry10_v_q <= entry10_v_d; +entry10_parity_q <= entry10_parity_d; +entry10_cmpmask_q <= entry10_cmpmask_d; +entry11_size_q <= entry11_size_d; +entry11_xbit_q <= entry11_xbit_d; +entry11_epn_q <= entry11_epn_d; +entry11_class_q <= entry11_class_d; +entry11_extclass_q <= entry11_extclass_d; +entry11_hv_q <= entry11_hv_d; +entry11_ds_q <= entry11_ds_d; +entry11_thdid_q <= entry11_thdid_d; +entry11_pid_q <= entry11_pid_d; +entry11_v_q <= entry11_v_d; +entry11_parity_q <= entry11_parity_d; +entry11_cmpmask_q <= entry11_cmpmask_d; +entry12_size_q <= entry12_size_d; +entry12_xbit_q <= entry12_xbit_d; +entry12_epn_q <= entry12_epn_d; +entry12_class_q <= entry12_class_d; +entry12_extclass_q <= entry12_extclass_d; +entry12_hv_q <= entry12_hv_d; +entry12_ds_q <= entry12_ds_d; +entry12_thdid_q <= entry12_thdid_d; +entry12_pid_q <= entry12_pid_d; +entry12_v_q <= entry12_v_d; +entry12_parity_q <= entry12_parity_d; +entry12_cmpmask_q <= entry12_cmpmask_d; +entry13_size_q <= entry13_size_d; +entry13_xbit_q <= entry13_xbit_d; +entry13_epn_q <= entry13_epn_d; +entry13_class_q <= entry13_class_d; +entry13_extclass_q <= entry13_extclass_d; +entry13_hv_q <= entry13_hv_d; +entry13_ds_q <= entry13_ds_d; +entry13_thdid_q <= entry13_thdid_d; +entry13_pid_q <= entry13_pid_d; +entry13_v_q <= entry13_v_d; +entry13_parity_q <= entry13_parity_d; +entry13_cmpmask_q <= entry13_cmpmask_d; +entry14_size_q <= entry14_size_d; +entry14_xbit_q <= entry14_xbit_d; +entry14_epn_q <= entry14_epn_d; +entry14_class_q <= entry14_class_d; +entry14_extclass_q <= entry14_extclass_d; +entry14_hv_q <= entry14_hv_d; +entry14_ds_q <= entry14_ds_d; +entry14_thdid_q <= entry14_thdid_d; +entry14_pid_q <= entry14_pid_d; +entry14_v_q <= entry14_v_d; +entry14_parity_q <= entry14_parity_d; +entry14_cmpmask_q <= entry14_cmpmask_d; +entry15_size_q <= entry15_size_d; +entry15_xbit_q <= entry15_xbit_d; +entry15_epn_q <= entry15_epn_d; +entry15_class_q <= entry15_class_d; +entry15_extclass_q <= entry15_extclass_d; +entry15_hv_q <= entry15_hv_d; +entry15_ds_q <= entry15_ds_d; +entry15_thdid_q <= entry15_thdid_d; +entry15_pid_q <= entry15_pid_d; +entry15_v_q <= entry15_v_d; +entry15_parity_q <= entry15_parity_d; +entry15_cmpmask_q <= entry15_cmpmask_d; +entry16_size_q <= entry16_size_d; +entry16_xbit_q <= entry16_xbit_d; +entry16_epn_q <= entry16_epn_d; +entry16_class_q <= entry16_class_d; +entry16_extclass_q <= entry16_extclass_d; +entry16_hv_q <= entry16_hv_d; +entry16_ds_q <= entry16_ds_d; +entry16_thdid_q <= entry16_thdid_d; +entry16_pid_q <= entry16_pid_d; +entry16_v_q <= entry16_v_d; +entry16_parity_q <= entry16_parity_d; +entry16_cmpmask_q <= entry16_cmpmask_d; +entry17_size_q <= entry17_size_d; +entry17_xbit_q <= entry17_xbit_d; +entry17_epn_q <= entry17_epn_d; +entry17_class_q <= entry17_class_d; +entry17_extclass_q <= entry17_extclass_d; +entry17_hv_q <= entry17_hv_d; +entry17_ds_q <= entry17_ds_d; +entry17_thdid_q <= entry17_thdid_d; +entry17_pid_q <= entry17_pid_d; +entry17_v_q <= entry17_v_d; +entry17_parity_q <= entry17_parity_d; +entry17_cmpmask_q <= entry17_cmpmask_d; +entry18_size_q <= entry18_size_d; +entry18_xbit_q <= entry18_xbit_d; +entry18_epn_q <= entry18_epn_d; +entry18_class_q <= entry18_class_d; +entry18_extclass_q <= entry18_extclass_d; +entry18_hv_q <= entry18_hv_d; +entry18_ds_q <= entry18_ds_d; +entry18_thdid_q <= entry18_thdid_d; +entry18_pid_q <= entry18_pid_d; +entry18_v_q <= entry18_v_d; +entry18_parity_q <= entry18_parity_d; +entry18_cmpmask_q <= entry18_cmpmask_d; +entry19_size_q <= entry19_size_d; +entry19_xbit_q <= entry19_xbit_d; +entry19_epn_q <= entry19_epn_d; +entry19_class_q <= entry19_class_d; +entry19_extclass_q <= entry19_extclass_d; +entry19_hv_q <= entry19_hv_d; +entry19_ds_q <= entry19_ds_d; +entry19_thdid_q <= entry19_thdid_d; +entry19_pid_q <= entry19_pid_d; +entry19_v_q <= entry19_v_d; +entry19_parity_q <= entry19_parity_d; +entry19_cmpmask_q <= entry19_cmpmask_d; +entry20_size_q <= entry20_size_d; +entry20_xbit_q <= entry20_xbit_d; +entry20_epn_q <= entry20_epn_d; +entry20_class_q <= entry20_class_d; +entry20_extclass_q <= entry20_extclass_d; +entry20_hv_q <= entry20_hv_d; +entry20_ds_q <= entry20_ds_d; +entry20_thdid_q <= entry20_thdid_d; +entry20_pid_q <= entry20_pid_d; +entry20_v_q <= entry20_v_d; +entry20_parity_q <= entry20_parity_d; +entry20_cmpmask_q <= entry20_cmpmask_d; +entry21_size_q <= entry21_size_d; +entry21_xbit_q <= entry21_xbit_d; +entry21_epn_q <= entry21_epn_d; +entry21_class_q <= entry21_class_d; +entry21_extclass_q <= entry21_extclass_d; +entry21_hv_q <= entry21_hv_d; +entry21_ds_q <= entry21_ds_d; +entry21_thdid_q <= entry21_thdid_d; +entry21_pid_q <= entry21_pid_d; +entry21_v_q <= entry21_v_d; +entry21_parity_q <= entry21_parity_d; +entry21_cmpmask_q <= entry21_cmpmask_d; +entry22_size_q <= entry22_size_d; +entry22_xbit_q <= entry22_xbit_d; +entry22_epn_q <= entry22_epn_d; +entry22_class_q <= entry22_class_d; +entry22_extclass_q <= entry22_extclass_d; +entry22_hv_q <= entry22_hv_d; +entry22_ds_q <= entry22_ds_d; +entry22_thdid_q <= entry22_thdid_d; +entry22_pid_q <= entry22_pid_d; +entry22_v_q <= entry22_v_d; +entry22_parity_q <= entry22_parity_d; +entry22_cmpmask_q <= entry22_cmpmask_d; +entry23_size_q <= entry23_size_d; +entry23_xbit_q <= entry23_xbit_d; +entry23_epn_q <= entry23_epn_d; +entry23_class_q <= entry23_class_d; +entry23_extclass_q <= entry23_extclass_d; +entry23_hv_q <= entry23_hv_d; +entry23_ds_q <= entry23_ds_d; +entry23_thdid_q <= entry23_thdid_d; +entry23_pid_q <= entry23_pid_d; +entry23_v_q <= entry23_v_d; +entry23_parity_q <= entry23_parity_d; +entry23_cmpmask_q <= entry23_cmpmask_d; +entry24_size_q <= entry24_size_d; +entry24_xbit_q <= entry24_xbit_d; +entry24_epn_q <= entry24_epn_d; +entry24_class_q <= entry24_class_d; +entry24_extclass_q <= entry24_extclass_d; +entry24_hv_q <= entry24_hv_d; +entry24_ds_q <= entry24_ds_d; +entry24_thdid_q <= entry24_thdid_d; +entry24_pid_q <= entry24_pid_d; +entry24_v_q <= entry24_v_d; +entry24_parity_q <= entry24_parity_d; +entry24_cmpmask_q <= entry24_cmpmask_d; +entry25_size_q <= entry25_size_d; +entry25_xbit_q <= entry25_xbit_d; +entry25_epn_q <= entry25_epn_d; +entry25_class_q <= entry25_class_d; +entry25_extclass_q <= entry25_extclass_d; +entry25_hv_q <= entry25_hv_d; +entry25_ds_q <= entry25_ds_d; +entry25_thdid_q <= entry25_thdid_d; +entry25_pid_q <= entry25_pid_d; +entry25_v_q <= entry25_v_d; +entry25_parity_q <= entry25_parity_d; +entry25_cmpmask_q <= entry25_cmpmask_d; +entry26_size_q <= entry26_size_d; +entry26_xbit_q <= entry26_xbit_d; +entry26_epn_q <= entry26_epn_d; +entry26_class_q <= entry26_class_d; +entry26_extclass_q <= entry26_extclass_d; +entry26_hv_q <= entry26_hv_d; +entry26_ds_q <= entry26_ds_d; +entry26_thdid_q <= entry26_thdid_d; +entry26_pid_q <= entry26_pid_d; +entry26_v_q <= entry26_v_d; +entry26_parity_q <= entry26_parity_d; +entry26_cmpmask_q <= entry26_cmpmask_d; +entry27_size_q <= entry27_size_d; +entry27_xbit_q <= entry27_xbit_d; +entry27_epn_q <= entry27_epn_d; +entry27_class_q <= entry27_class_d; +entry27_extclass_q <= entry27_extclass_d; +entry27_hv_q <= entry27_hv_d; +entry27_ds_q <= entry27_ds_d; +entry27_thdid_q <= entry27_thdid_d; +entry27_pid_q <= entry27_pid_d; +entry27_v_q <= entry27_v_d; +entry27_parity_q <= entry27_parity_d; +entry27_cmpmask_q <= entry27_cmpmask_d; +entry28_size_q <= entry28_size_d; +entry28_xbit_q <= entry28_xbit_d; +entry28_epn_q <= entry28_epn_d; +entry28_class_q <= entry28_class_d; +entry28_extclass_q <= entry28_extclass_d; +entry28_hv_q <= entry28_hv_d; +entry28_ds_q <= entry28_ds_d; +entry28_thdid_q <= entry28_thdid_d; +entry28_pid_q <= entry28_pid_d; +entry28_v_q <= entry28_v_d; +entry28_parity_q <= entry28_parity_d; +entry28_cmpmask_q <= entry28_cmpmask_d; +entry29_size_q <= entry29_size_d; +entry29_xbit_q <= entry29_xbit_d; +entry29_epn_q <= entry29_epn_d; +entry29_class_q <= entry29_class_d; +entry29_extclass_q <= entry29_extclass_d; +entry29_hv_q <= entry29_hv_d; +entry29_ds_q <= entry29_ds_d; +entry29_thdid_q <= entry29_thdid_d; +entry29_pid_q <= entry29_pid_d; +entry29_v_q <= entry29_v_d; +entry29_parity_q <= entry29_parity_d; +entry29_cmpmask_q <= entry29_cmpmask_d; +entry30_size_q <= entry30_size_d; +entry30_xbit_q <= entry30_xbit_d; +entry30_epn_q <= entry30_epn_d; +entry30_class_q <= entry30_class_d; +entry30_extclass_q <= entry30_extclass_d; +entry30_hv_q <= entry30_hv_d; +entry30_ds_q <= entry30_ds_d; +entry30_thdid_q <= entry30_thdid_d; +entry30_pid_q <= entry30_pid_d; +entry30_v_q <= entry30_v_d; +entry30_parity_q <= entry30_parity_d; +entry30_cmpmask_q <= entry30_cmpmask_d; +entry31_size_q <= entry31_size_d; +entry31_xbit_q <= entry31_xbit_d; +entry31_epn_q <= entry31_epn_d; +entry31_class_q <= entry31_class_d; +entry31_extclass_q <= entry31_extclass_d; +entry31_hv_q <= entry31_hv_d; +entry31_ds_q <= entry31_ds_d; +entry31_thdid_q <= entry31_thdid_d; +entry31_pid_q <= entry31_pid_d; +entry31_v_q <= entry31_v_d; +entry31_parity_q <= entry31_parity_d; +entry31_cmpmask_q <= entry31_cmpmask_d; +end if; +end if; +end process; +----------------------------------------------------------------------- +-- latch input logic +----------------------------------------------------------------------- +comp_addr_np1_d <= comp_addr(52-rpn_width to 51); +cam_hit_d <= '1' when (match_vec /= "00000000000000000000000000000000" and comp_request='1') else '0'; +cam_hit_entry_d <= "00001" when match_vec(0 to 1)="01" else + "00010" when match_vec(0 to 2)="001" else + "00011" when match_vec(0 to 3)="0001" else + "00100" when match_vec(0 to 4)="00001" else + "00101" when match_vec(0 to 5)="000001" else + "00110" when match_vec(0 to 6)="0000001" else + "00111" when match_vec(0 to 7)="00000001" else + "01000" when match_vec(0 to 8)="000000001" else + "01001" when match_vec(0 to 9)="0000000001" else + "01010" when match_vec(0 to 10)="00000000001" else + "01011" when match_vec(0 to 11)="000000000001" else + "01100" when match_vec(0 to 12)="0000000000001" else + "01101" when match_vec(0 to 13)="00000000000001" else + "01110" when match_vec(0 to 14)="000000000000001" else + "01111" when match_vec(0 to 15)="0000000000000001" else + "10000" when match_vec(0 to 16)="00000000000000001" else + "10001" when match_vec(0 to 17)="000000000000000001" else + "10010" when match_vec(0 to 18)="0000000000000000001" else + "10011" when match_vec(0 to 19)="00000000000000000001" else + "10100" when match_vec(0 to 20)="000000000000000000001" else + "10101" when match_vec(0 to 21)="0000000000000000000001" else + "10110" when match_vec(0 to 22)="00000000000000000000001" else + "10111" when match_vec(0 to 23)="000000000000000000000001" else + "11000" when match_vec(0 to 24)="0000000000000000000000001" else + "11001" when match_vec(0 to 25)="00000000000000000000000001" else + "11010" when match_vec(0 to 26)="000000000000000000000000001" else + "11011" when match_vec(0 to 27)="0000000000000000000000000001" else + "11100" when match_vec(0 to 28)="00000000000000000000000000001" else + "11101" when match_vec(0 to 29)="000000000000000000000000000001" else + "11110" when match_vec(0 to 30)="0000000000000000000000000000001" else + "11111" when match_vec(0 to 31)="00000000000000000000000000000001" else + "00000"; +entry_match_d <= match_vec when (comp_request='1') else (others => '0'); +wr_entry0_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="00000")) else '0'; +wr_entry0_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="00000")) else '0'; +with wr_entry0_sel(0) select + entry0_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry0_epn_q(0 to 31) when others; +with wr_entry0_sel(0) select + entry0_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry0_epn_q(32 to 51) when others; +with wr_entry0_sel(0) select + entry0_xbit_d <= wr_cam_data(52) when '1', + entry0_xbit_q when others; +with wr_entry0_sel(0) select + entry0_size_d <= wr_cam_data(53 to 55) when '1', + entry0_size_q(0 to 2) when others; +with wr_entry0_sel(0) select + entry0_class_d <= wr_cam_data(61 to 62) when '1', + entry0_class_q(0 to 1) when others; +with wr_entry0_sel(1) select + entry0_extclass_d <= wr_cam_data(63 to 64) when '1', + entry0_extclass_q(0 to 1) when others; +with wr_entry0_sel(1) select + entry0_hv_d <= wr_cam_data(65) when '1', + entry0_hv_q when others; +with wr_entry0_sel(1) select + entry0_ds_d <= wr_cam_data(66) when '1', + entry0_ds_q when others; +with wr_entry0_sel(1) select + entry0_pid_d <= wr_cam_data(67 to 74) when '1', + entry0_pid_q(0 to 7) when others; +with wr_entry0_sel(0) select + entry0_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry0_cmpmask_q when others; +-- the cam parity bits.. some wr_array_data bits contain parity for cam +with wr_entry0_sel(0) select + entry0_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry0_parity_q(0 to 3) when others; +with wr_entry0_sel(0) select + entry0_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry0_parity_q(4 to 6) when others; +with wr_entry0_sel(0) select + entry0_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry0_parity_q(7) when others; +with wr_entry0_sel(1) select + entry0_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry0_parity_q(8) when others; +with wr_entry0_sel(1) select + entry0_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry0_parity_q(9) when others; +wr_entry1_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="00001")) else '0'; +wr_entry1_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="00001")) else '0'; +with wr_entry1_sel(0) select + entry1_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry1_epn_q(0 to 31) when others; +with wr_entry1_sel(0) select + entry1_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry1_epn_q(32 to 51) when others; +with wr_entry1_sel(0) select + entry1_xbit_d <= wr_cam_data(52) when '1', + entry1_xbit_q when others; +with wr_entry1_sel(0) select + entry1_size_d <= wr_cam_data(53 to 55) when '1', + entry1_size_q(0 to 2) when others; +with wr_entry1_sel(0) select + entry1_class_d <= wr_cam_data(61 to 62) when '1', + entry1_class_q(0 to 1) when others; +with wr_entry1_sel(1) select + entry1_extclass_d <= wr_cam_data(63 to 64) when '1', + entry1_extclass_q(0 to 1) when others; +with wr_entry1_sel(1) select + entry1_hv_d <= wr_cam_data(65) when '1', + entry1_hv_q when others; +with wr_entry1_sel(1) select + entry1_ds_d <= wr_cam_data(66) when '1', + entry1_ds_q when others; +with wr_entry1_sel(1) select + entry1_pid_d <= wr_cam_data(67 to 74) when '1', + entry1_pid_q(0 to 7) when others; +with wr_entry1_sel(0) select + entry1_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry1_cmpmask_q when others; +-- the cam parity bits.. some wr_array_data bits contain parity for cam +with wr_entry1_sel(0) select + entry1_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry1_parity_q(0 to 3) when others; +with wr_entry1_sel(0) select + entry1_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry1_parity_q(4 to 6) when others; +with wr_entry1_sel(0) select + entry1_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry1_parity_q(7) when others; +with wr_entry1_sel(1) select + entry1_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry1_parity_q(8) when others; +with wr_entry1_sel(1) select + entry1_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry1_parity_q(9) when others; +wr_entry2_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="00010")) else '0'; +wr_entry2_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="00010")) else '0'; +with wr_entry2_sel(0) select + entry2_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry2_epn_q(0 to 31) when others; +with wr_entry2_sel(0) select + entry2_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry2_epn_q(32 to 51) when others; +with wr_entry2_sel(0) select + entry2_xbit_d <= wr_cam_data(52) when '1', + entry2_xbit_q when others; +with wr_entry2_sel(0) select + entry2_size_d <= wr_cam_data(53 to 55) when '1', + entry2_size_q(0 to 2) when others; +with wr_entry2_sel(0) select + entry2_class_d <= wr_cam_data(61 to 62) when '1', + entry2_class_q(0 to 1) when others; +with wr_entry2_sel(1) select + entry2_extclass_d <= wr_cam_data(63 to 64) when '1', + entry2_extclass_q(0 to 1) when others; +with wr_entry2_sel(1) select + entry2_hv_d <= wr_cam_data(65) when '1', + entry2_hv_q when others; +with wr_entry2_sel(1) select + entry2_ds_d <= wr_cam_data(66) when '1', + entry2_ds_q when others; +with wr_entry2_sel(1) select + entry2_pid_d <= wr_cam_data(67 to 74) when '1', + entry2_pid_q(0 to 7) when others; +with wr_entry2_sel(0) select + entry2_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry2_cmpmask_q when others; +-- the cam parity bits.. some wr_array_data bits contain parity for cam +with wr_entry2_sel(0) select + entry2_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry2_parity_q(0 to 3) when others; +with wr_entry2_sel(0) select + entry2_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry2_parity_q(4 to 6) when others; +with wr_entry2_sel(0) select + entry2_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry2_parity_q(7) when others; +with wr_entry2_sel(1) select + entry2_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry2_parity_q(8) when others; +with wr_entry2_sel(1) select + entry2_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry2_parity_q(9) when others; +wr_entry3_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="00011")) else '0'; +wr_entry3_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="00011")) else '0'; +with wr_entry3_sel(0) select + entry3_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry3_epn_q(0 to 31) when others; +with wr_entry3_sel(0) select + entry3_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry3_epn_q(32 to 51) when others; +with wr_entry3_sel(0) select + entry3_xbit_d <= wr_cam_data(52) when '1', + entry3_xbit_q when others; +with wr_entry3_sel(0) select + entry3_size_d <= wr_cam_data(53 to 55) when '1', + entry3_size_q(0 to 2) when others; +with wr_entry3_sel(0) select + entry3_class_d <= wr_cam_data(61 to 62) when '1', + entry3_class_q(0 to 1) when others; +with wr_entry3_sel(1) select + entry3_extclass_d <= wr_cam_data(63 to 64) when '1', + entry3_extclass_q(0 to 1) when others; +with wr_entry3_sel(1) select + entry3_hv_d <= wr_cam_data(65) when '1', + entry3_hv_q when others; +with wr_entry3_sel(1) select + entry3_ds_d <= wr_cam_data(66) when '1', + entry3_ds_q when others; +with wr_entry3_sel(1) select + entry3_pid_d <= wr_cam_data(67 to 74) when '1', + entry3_pid_q(0 to 7) when others; +with wr_entry3_sel(0) select + entry3_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry3_cmpmask_q when others; +-- the cam parity bits.. some wr_array_data bits contain parity for cam +with wr_entry3_sel(0) select + entry3_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry3_parity_q(0 to 3) when others; +with wr_entry3_sel(0) select + entry3_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry3_parity_q(4 to 6) when others; +with wr_entry3_sel(0) select + entry3_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry3_parity_q(7) when others; +with wr_entry3_sel(1) select + entry3_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry3_parity_q(8) when others; +with wr_entry3_sel(1) select + entry3_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry3_parity_q(9) when others; +wr_entry4_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="00100")) else '0'; +wr_entry4_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="00100")) else '0'; +with wr_entry4_sel(0) select + entry4_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry4_epn_q(0 to 31) when others; +with wr_entry4_sel(0) select + entry4_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry4_epn_q(32 to 51) when others; +with wr_entry4_sel(0) select + entry4_xbit_d <= wr_cam_data(52) when '1', + entry4_xbit_q when others; +with wr_entry4_sel(0) select + entry4_size_d <= wr_cam_data(53 to 55) when '1', + entry4_size_q(0 to 2) when others; +with wr_entry4_sel(0) select + entry4_class_d <= wr_cam_data(61 to 62) when '1', + entry4_class_q(0 to 1) when others; +with wr_entry4_sel(1) select + entry4_extclass_d <= wr_cam_data(63 to 64) when '1', + entry4_extclass_q(0 to 1) when others; +with wr_entry4_sel(1) select + entry4_hv_d <= wr_cam_data(65) when '1', + entry4_hv_q when others; +with wr_entry4_sel(1) select + entry4_ds_d <= wr_cam_data(66) when '1', + entry4_ds_q when others; +with wr_entry4_sel(1) select + entry4_pid_d <= wr_cam_data(67 to 74) when '1', + entry4_pid_q(0 to 7) when others; +with wr_entry4_sel(0) select + entry4_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry4_cmpmask_q when others; +-- the cam parity bits.. some wr_array_data bits contain parity for cam +with wr_entry4_sel(0) select + entry4_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry4_parity_q(0 to 3) when others; +with wr_entry4_sel(0) select + entry4_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry4_parity_q(4 to 6) when others; +with wr_entry4_sel(0) select + entry4_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry4_parity_q(7) when others; +with wr_entry4_sel(1) select + entry4_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry4_parity_q(8) when others; +with wr_entry4_sel(1) select + entry4_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry4_parity_q(9) when others; +wr_entry5_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="00101")) else '0'; +wr_entry5_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="00101")) else '0'; +with wr_entry5_sel(0) select + entry5_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry5_epn_q(0 to 31) when others; +with wr_entry5_sel(0) select + entry5_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry5_epn_q(32 to 51) when others; +with wr_entry5_sel(0) select + entry5_xbit_d <= wr_cam_data(52) when '1', + entry5_xbit_q when others; +with wr_entry5_sel(0) select + entry5_size_d <= wr_cam_data(53 to 55) when '1', + entry5_size_q(0 to 2) when others; +with wr_entry5_sel(0) select + entry5_class_d <= wr_cam_data(61 to 62) when '1', + entry5_class_q(0 to 1) when others; +with wr_entry5_sel(1) select + entry5_extclass_d <= wr_cam_data(63 to 64) when '1', + entry5_extclass_q(0 to 1) when others; +with wr_entry5_sel(1) select + entry5_hv_d <= wr_cam_data(65) when '1', + entry5_hv_q when others; +with wr_entry5_sel(1) select + entry5_ds_d <= wr_cam_data(66) when '1', + entry5_ds_q when others; +with wr_entry5_sel(1) select + entry5_pid_d <= wr_cam_data(67 to 74) when '1', + entry5_pid_q(0 to 7) when others; +with wr_entry5_sel(0) select + entry5_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry5_cmpmask_q when others; +-- the cam parity bits.. some wr_array_data bits contain parity for cam +with wr_entry5_sel(0) select + entry5_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry5_parity_q(0 to 3) when others; +with wr_entry5_sel(0) select + entry5_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry5_parity_q(4 to 6) when others; +with wr_entry5_sel(0) select + entry5_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry5_parity_q(7) when others; +with wr_entry5_sel(1) select + entry5_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry5_parity_q(8) when others; +with wr_entry5_sel(1) select + entry5_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry5_parity_q(9) when others; +wr_entry6_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="00110")) else '0'; +wr_entry6_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="00110")) else '0'; +with wr_entry6_sel(0) select + entry6_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry6_epn_q(0 to 31) when others; +with wr_entry6_sel(0) select + entry6_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry6_epn_q(32 to 51) when others; +with wr_entry6_sel(0) select + entry6_xbit_d <= wr_cam_data(52) when '1', + entry6_xbit_q when others; +with wr_entry6_sel(0) select + entry6_size_d <= wr_cam_data(53 to 55) when '1', + entry6_size_q(0 to 2) when others; +with wr_entry6_sel(0) select + entry6_class_d <= wr_cam_data(61 to 62) when '1', + entry6_class_q(0 to 1) when others; +with wr_entry6_sel(1) select + entry6_extclass_d <= wr_cam_data(63 to 64) when '1', + entry6_extclass_q(0 to 1) when others; +with wr_entry6_sel(1) select + entry6_hv_d <= wr_cam_data(65) when '1', + entry6_hv_q when others; +with wr_entry6_sel(1) select + entry6_ds_d <= wr_cam_data(66) when '1', + entry6_ds_q when others; +with wr_entry6_sel(1) select + entry6_pid_d <= wr_cam_data(67 to 74) when '1', + entry6_pid_q(0 to 7) when others; +with wr_entry6_sel(0) select + entry6_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry6_cmpmask_q when others; +-- the cam parity bits.. some wr_array_data bits contain parity for cam +with wr_entry6_sel(0) select + entry6_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry6_parity_q(0 to 3) when others; +with wr_entry6_sel(0) select + entry6_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry6_parity_q(4 to 6) when others; +with wr_entry6_sel(0) select + entry6_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry6_parity_q(7) when others; +with wr_entry6_sel(1) select + entry6_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry6_parity_q(8) when others; +with wr_entry6_sel(1) select + entry6_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry6_parity_q(9) when others; +wr_entry7_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="00111")) else '0'; +wr_entry7_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="00111")) else '0'; +with wr_entry7_sel(0) select + entry7_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry7_epn_q(0 to 31) when others; +with wr_entry7_sel(0) select + entry7_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry7_epn_q(32 to 51) when others; +with wr_entry7_sel(0) select + entry7_xbit_d <= wr_cam_data(52) when '1', + entry7_xbit_q when others; +with wr_entry7_sel(0) select + entry7_size_d <= wr_cam_data(53 to 55) when '1', + entry7_size_q(0 to 2) when others; +with wr_entry7_sel(0) select + entry7_class_d <= wr_cam_data(61 to 62) when '1', + entry7_class_q(0 to 1) when others; +with wr_entry7_sel(1) select + entry7_extclass_d <= wr_cam_data(63 to 64) when '1', + entry7_extclass_q(0 to 1) when others; +with wr_entry7_sel(1) select + entry7_hv_d <= wr_cam_data(65) when '1', + entry7_hv_q when others; +with wr_entry7_sel(1) select + entry7_ds_d <= wr_cam_data(66) when '1', + entry7_ds_q when others; +with wr_entry7_sel(1) select + entry7_pid_d <= wr_cam_data(67 to 74) when '1', + entry7_pid_q(0 to 7) when others; +with wr_entry7_sel(0) select + entry7_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry7_cmpmask_q when others; +-- the cam parity bits.. some wr_array_data bits contain parity for cam +with wr_entry7_sel(0) select + entry7_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry7_parity_q(0 to 3) when others; +with wr_entry7_sel(0) select + entry7_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry7_parity_q(4 to 6) when others; +with wr_entry7_sel(0) select + entry7_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry7_parity_q(7) when others; +with wr_entry7_sel(1) select + entry7_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry7_parity_q(8) when others; +with wr_entry7_sel(1) select + entry7_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry7_parity_q(9) when others; +wr_entry8_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="01000")) else '0'; +wr_entry8_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="01000")) else '0'; +with wr_entry8_sel(0) select + entry8_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry8_epn_q(0 to 31) when others; +with wr_entry8_sel(0) select + entry8_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry8_epn_q(32 to 51) when others; +with wr_entry8_sel(0) select + entry8_xbit_d <= wr_cam_data(52) when '1', + entry8_xbit_q when others; +with wr_entry8_sel(0) select + entry8_size_d <= wr_cam_data(53 to 55) when '1', + entry8_size_q(0 to 2) when others; +with wr_entry8_sel(0) select + entry8_class_d <= wr_cam_data(61 to 62) when '1', + entry8_class_q(0 to 1) when others; +with wr_entry8_sel(1) select + entry8_extclass_d <= wr_cam_data(63 to 64) when '1', + entry8_extclass_q(0 to 1) when others; +with wr_entry8_sel(1) select + entry8_hv_d <= wr_cam_data(65) when '1', + entry8_hv_q when others; +with wr_entry8_sel(1) select + entry8_ds_d <= wr_cam_data(66) when '1', + entry8_ds_q when others; +with wr_entry8_sel(1) select + entry8_pid_d <= wr_cam_data(67 to 74) when '1', + entry8_pid_q(0 to 7) when others; +with wr_entry8_sel(0) select + entry8_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry8_cmpmask_q when others; +-- the cam parity bits.. some wr_array_data bits contain parity for cam +with wr_entry8_sel(0) select + entry8_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry8_parity_q(0 to 3) when others; +with wr_entry8_sel(0) select + entry8_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry8_parity_q(4 to 6) when others; +with wr_entry8_sel(0) select + entry8_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry8_parity_q(7) when others; +with wr_entry8_sel(1) select + entry8_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry8_parity_q(8) when others; +with wr_entry8_sel(1) select + entry8_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry8_parity_q(9) when others; +wr_entry9_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="01001")) else '0'; +wr_entry9_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="01001")) else '0'; +with wr_entry9_sel(0) select + entry9_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry9_epn_q(0 to 31) when others; +with wr_entry9_sel(0) select + entry9_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry9_epn_q(32 to 51) when others; +with wr_entry9_sel(0) select + entry9_xbit_d <= wr_cam_data(52) when '1', + entry9_xbit_q when others; +with wr_entry9_sel(0) select + entry9_size_d <= wr_cam_data(53 to 55) when '1', + entry9_size_q(0 to 2) when others; +with wr_entry9_sel(0) select + entry9_class_d <= wr_cam_data(61 to 62) when '1', + entry9_class_q(0 to 1) when others; +with wr_entry9_sel(1) select + entry9_extclass_d <= wr_cam_data(63 to 64) when '1', + entry9_extclass_q(0 to 1) when others; +with wr_entry9_sel(1) select + entry9_hv_d <= wr_cam_data(65) when '1', + entry9_hv_q when others; +with wr_entry9_sel(1) select + entry9_ds_d <= wr_cam_data(66) when '1', + entry9_ds_q when others; +with wr_entry9_sel(1) select + entry9_pid_d <= wr_cam_data(67 to 74) when '1', + entry9_pid_q(0 to 7) when others; +with wr_entry9_sel(0) select + entry9_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry9_cmpmask_q when others; +-- the cam parity bits.. some wr_array_data bits contain parity for cam +with wr_entry9_sel(0) select + entry9_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry9_parity_q(0 to 3) when others; +with wr_entry9_sel(0) select + entry9_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry9_parity_q(4 to 6) when others; +with wr_entry9_sel(0) select + entry9_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry9_parity_q(7) when others; +with wr_entry9_sel(1) select + entry9_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry9_parity_q(8) when others; +with wr_entry9_sel(1) select + entry9_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry9_parity_q(9) when others; +wr_entry10_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="01010")) else '0'; +wr_entry10_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="01010")) else '0'; +with wr_entry10_sel(0) select + entry10_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry10_epn_q(0 to 31) when others; +with wr_entry10_sel(0) select + entry10_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry10_epn_q(32 to 51) when others; +with wr_entry10_sel(0) select + entry10_xbit_d <= wr_cam_data(52) when '1', + entry10_xbit_q when others; +with wr_entry10_sel(0) select + entry10_size_d <= wr_cam_data(53 to 55) when '1', + entry10_size_q(0 to 2) when others; +with wr_entry10_sel(0) select + entry10_class_d <= wr_cam_data(61 to 62) when '1', + entry10_class_q(0 to 1) when others; +with wr_entry10_sel(1) select + entry10_extclass_d <= wr_cam_data(63 to 64) when '1', + entry10_extclass_q(0 to 1) when others; +with wr_entry10_sel(1) select + entry10_hv_d <= wr_cam_data(65) when '1', + entry10_hv_q when others; +with wr_entry10_sel(1) select + entry10_ds_d <= wr_cam_data(66) when '1', + entry10_ds_q when others; +with wr_entry10_sel(1) select + entry10_pid_d <= wr_cam_data(67 to 74) when '1', + entry10_pid_q(0 to 7) when others; +with wr_entry10_sel(0) select + entry10_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry10_cmpmask_q when others; +-- the cam parity bits.. some wr_array_data bits contain parity for cam +with wr_entry10_sel(0) select + entry10_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry10_parity_q(0 to 3) when others; +with wr_entry10_sel(0) select + entry10_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry10_parity_q(4 to 6) when others; +with wr_entry10_sel(0) select + entry10_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry10_parity_q(7) when others; +with wr_entry10_sel(1) select + entry10_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry10_parity_q(8) when others; +with wr_entry10_sel(1) select + entry10_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry10_parity_q(9) when others; +wr_entry11_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="01011")) else '0'; +wr_entry11_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="01011")) else '0'; +with wr_entry11_sel(0) select + entry11_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry11_epn_q(0 to 31) when others; +with wr_entry11_sel(0) select + entry11_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry11_epn_q(32 to 51) when others; +with wr_entry11_sel(0) select + entry11_xbit_d <= wr_cam_data(52) when '1', + entry11_xbit_q when others; +with wr_entry11_sel(0) select + entry11_size_d <= wr_cam_data(53 to 55) when '1', + entry11_size_q(0 to 2) when others; +with wr_entry11_sel(0) select + entry11_class_d <= wr_cam_data(61 to 62) when '1', + entry11_class_q(0 to 1) when others; +with wr_entry11_sel(1) select + entry11_extclass_d <= wr_cam_data(63 to 64) when '1', + entry11_extclass_q(0 to 1) when others; +with wr_entry11_sel(1) select + entry11_hv_d <= wr_cam_data(65) when '1', + entry11_hv_q when others; +with wr_entry11_sel(1) select + entry11_ds_d <= wr_cam_data(66) when '1', + entry11_ds_q when others; +with wr_entry11_sel(1) select + entry11_pid_d <= wr_cam_data(67 to 74) when '1', + entry11_pid_q(0 to 7) when others; +with wr_entry11_sel(0) select + entry11_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry11_cmpmask_q when others; +-- the cam parity bits.. some wr_array_data bits contain parity for cam +with wr_entry11_sel(0) select + entry11_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry11_parity_q(0 to 3) when others; +with wr_entry11_sel(0) select + entry11_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry11_parity_q(4 to 6) when others; +with wr_entry11_sel(0) select + entry11_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry11_parity_q(7) when others; +with wr_entry11_sel(1) select + entry11_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry11_parity_q(8) when others; +with wr_entry11_sel(1) select + entry11_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry11_parity_q(9) when others; +wr_entry12_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="01100")) else '0'; +wr_entry12_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="01100")) else '0'; +with wr_entry12_sel(0) select + entry12_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry12_epn_q(0 to 31) when others; +with wr_entry12_sel(0) select + entry12_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry12_epn_q(32 to 51) when others; +with wr_entry12_sel(0) select + entry12_xbit_d <= wr_cam_data(52) when '1', + entry12_xbit_q when others; +with wr_entry12_sel(0) select + entry12_size_d <= wr_cam_data(53 to 55) when '1', + entry12_size_q(0 to 2) when others; +with wr_entry12_sel(0) select + entry12_class_d <= wr_cam_data(61 to 62) when '1', + entry12_class_q(0 to 1) when others; +with wr_entry12_sel(1) select + entry12_extclass_d <= wr_cam_data(63 to 64) when '1', + entry12_extclass_q(0 to 1) when others; +with wr_entry12_sel(1) select + entry12_hv_d <= wr_cam_data(65) when '1', + entry12_hv_q when others; +with wr_entry12_sel(1) select + entry12_ds_d <= wr_cam_data(66) when '1', + entry12_ds_q when others; +with wr_entry12_sel(1) select + entry12_pid_d <= wr_cam_data(67 to 74) when '1', + entry12_pid_q(0 to 7) when others; +with wr_entry12_sel(0) select + entry12_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry12_cmpmask_q when others; +-- the cam parity bits.. some wr_array_data bits contain parity for cam +with wr_entry12_sel(0) select + entry12_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry12_parity_q(0 to 3) when others; +with wr_entry12_sel(0) select + entry12_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry12_parity_q(4 to 6) when others; +with wr_entry12_sel(0) select + entry12_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry12_parity_q(7) when others; +with wr_entry12_sel(1) select + entry12_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry12_parity_q(8) when others; +with wr_entry12_sel(1) select + entry12_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry12_parity_q(9) when others; +wr_entry13_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="01101")) else '0'; +wr_entry13_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="01101")) else '0'; +with wr_entry13_sel(0) select + entry13_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry13_epn_q(0 to 31) when others; +with wr_entry13_sel(0) select + entry13_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry13_epn_q(32 to 51) when others; +with wr_entry13_sel(0) select + entry13_xbit_d <= wr_cam_data(52) when '1', + entry13_xbit_q when others; +with wr_entry13_sel(0) select + entry13_size_d <= wr_cam_data(53 to 55) when '1', + entry13_size_q(0 to 2) when others; +with wr_entry13_sel(0) select + entry13_class_d <= wr_cam_data(61 to 62) when '1', + entry13_class_q(0 to 1) when others; +with wr_entry13_sel(1) select + entry13_extclass_d <= wr_cam_data(63 to 64) when '1', + entry13_extclass_q(0 to 1) when others; +with wr_entry13_sel(1) select + entry13_hv_d <= wr_cam_data(65) when '1', + entry13_hv_q when others; +with wr_entry13_sel(1) select + entry13_ds_d <= wr_cam_data(66) when '1', + entry13_ds_q when others; +with wr_entry13_sel(1) select + entry13_pid_d <= wr_cam_data(67 to 74) when '1', + entry13_pid_q(0 to 7) when others; +with wr_entry13_sel(0) select + entry13_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry13_cmpmask_q when others; +-- the cam parity bits.. some wr_array_data bits contain parity for cam +with wr_entry13_sel(0) select + entry13_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry13_parity_q(0 to 3) when others; +with wr_entry13_sel(0) select + entry13_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry13_parity_q(4 to 6) when others; +with wr_entry13_sel(0) select + entry13_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry13_parity_q(7) when others; +with wr_entry13_sel(1) select + entry13_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry13_parity_q(8) when others; +with wr_entry13_sel(1) select + entry13_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry13_parity_q(9) when others; +wr_entry14_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="01110")) else '0'; +wr_entry14_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="01110")) else '0'; +with wr_entry14_sel(0) select + entry14_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry14_epn_q(0 to 31) when others; +with wr_entry14_sel(0) select + entry14_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry14_epn_q(32 to 51) when others; +with wr_entry14_sel(0) select + entry14_xbit_d <= wr_cam_data(52) when '1', + entry14_xbit_q when others; +with wr_entry14_sel(0) select + entry14_size_d <= wr_cam_data(53 to 55) when '1', + entry14_size_q(0 to 2) when others; +with wr_entry14_sel(0) select + entry14_class_d <= wr_cam_data(61 to 62) when '1', + entry14_class_q(0 to 1) when others; +with wr_entry14_sel(1) select + entry14_extclass_d <= wr_cam_data(63 to 64) when '1', + entry14_extclass_q(0 to 1) when others; +with wr_entry14_sel(1) select + entry14_hv_d <= wr_cam_data(65) when '1', + entry14_hv_q when others; +with wr_entry14_sel(1) select + entry14_ds_d <= wr_cam_data(66) when '1', + entry14_ds_q when others; +with wr_entry14_sel(1) select + entry14_pid_d <= wr_cam_data(67 to 74) when '1', + entry14_pid_q(0 to 7) when others; +with wr_entry14_sel(0) select + entry14_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry14_cmpmask_q when others; +-- the cam parity bits.. some wr_array_data bits contain parity for cam +with wr_entry14_sel(0) select + entry14_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry14_parity_q(0 to 3) when others; +with wr_entry14_sel(0) select + entry14_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry14_parity_q(4 to 6) when others; +with wr_entry14_sel(0) select + entry14_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry14_parity_q(7) when others; +with wr_entry14_sel(1) select + entry14_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry14_parity_q(8) when others; +with wr_entry14_sel(1) select + entry14_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry14_parity_q(9) when others; +wr_entry15_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="01111")) else '0'; +wr_entry15_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="01111")) else '0'; +with wr_entry15_sel(0) select + entry15_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry15_epn_q(0 to 31) when others; +with wr_entry15_sel(0) select + entry15_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry15_epn_q(32 to 51) when others; +with wr_entry15_sel(0) select + entry15_xbit_d <= wr_cam_data(52) when '1', + entry15_xbit_q when others; +with wr_entry15_sel(0) select + entry15_size_d <= wr_cam_data(53 to 55) when '1', + entry15_size_q(0 to 2) when others; +with wr_entry15_sel(0) select + entry15_class_d <= wr_cam_data(61 to 62) when '1', + entry15_class_q(0 to 1) when others; +with wr_entry15_sel(1) select + entry15_extclass_d <= wr_cam_data(63 to 64) when '1', + entry15_extclass_q(0 to 1) when others; +with wr_entry15_sel(1) select + entry15_hv_d <= wr_cam_data(65) when '1', + entry15_hv_q when others; +with wr_entry15_sel(1) select + entry15_ds_d <= wr_cam_data(66) when '1', + entry15_ds_q when others; +with wr_entry15_sel(1) select + entry15_pid_d <= wr_cam_data(67 to 74) when '1', + entry15_pid_q(0 to 7) when others; +with wr_entry15_sel(0) select + entry15_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry15_cmpmask_q when others; +-- the cam parity bits.. some wr_array_data bits contain parity for cam +with wr_entry15_sel(0) select + entry15_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry15_parity_q(0 to 3) when others; +with wr_entry15_sel(0) select + entry15_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry15_parity_q(4 to 6) when others; +with wr_entry15_sel(0) select + entry15_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry15_parity_q(7) when others; +with wr_entry15_sel(1) select + entry15_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry15_parity_q(8) when others; +with wr_entry15_sel(1) select + entry15_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry15_parity_q(9) when others; +wr_entry16_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="10000")) else '0'; +wr_entry16_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="10000")) else '0'; +with wr_entry16_sel(0) select + entry16_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry16_epn_q(0 to 31) when others; +with wr_entry16_sel(0) select + entry16_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry16_epn_q(32 to 51) when others; +with wr_entry16_sel(0) select + entry16_xbit_d <= wr_cam_data(52) when '1', + entry16_xbit_q when others; +with wr_entry16_sel(0) select + entry16_size_d <= wr_cam_data(53 to 55) when '1', + entry16_size_q(0 to 2) when others; +with wr_entry16_sel(0) select + entry16_class_d <= wr_cam_data(61 to 62) when '1', + entry16_class_q(0 to 1) when others; +with wr_entry16_sel(1) select + entry16_extclass_d <= wr_cam_data(63 to 64) when '1', + entry16_extclass_q(0 to 1) when others; +with wr_entry16_sel(1) select + entry16_hv_d <= wr_cam_data(65) when '1', + entry16_hv_q when others; +with wr_entry16_sel(1) select + entry16_ds_d <= wr_cam_data(66) when '1', + entry16_ds_q when others; +with wr_entry16_sel(1) select + entry16_pid_d <= wr_cam_data(67 to 74) when '1', + entry16_pid_q(0 to 7) when others; +with wr_entry16_sel(0) select + entry16_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry16_cmpmask_q when others; +-- the cam parity bits.. some wr_array_data bits contain parity for cam +with wr_entry16_sel(0) select + entry16_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry16_parity_q(0 to 3) when others; +with wr_entry16_sel(0) select + entry16_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry16_parity_q(4 to 6) when others; +with wr_entry16_sel(0) select + entry16_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry16_parity_q(7) when others; +with wr_entry16_sel(1) select + entry16_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry16_parity_q(8) when others; +with wr_entry16_sel(1) select + entry16_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry16_parity_q(9) when others; +wr_entry17_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="10001")) else '0'; +wr_entry17_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="10001")) else '0'; +with wr_entry17_sel(0) select + entry17_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry17_epn_q(0 to 31) when others; +with wr_entry17_sel(0) select + entry17_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry17_epn_q(32 to 51) when others; +with wr_entry17_sel(0) select + entry17_xbit_d <= wr_cam_data(52) when '1', + entry17_xbit_q when others; +with wr_entry17_sel(0) select + entry17_size_d <= wr_cam_data(53 to 55) when '1', + entry17_size_q(0 to 2) when others; +with wr_entry17_sel(0) select + entry17_class_d <= wr_cam_data(61 to 62) when '1', + entry17_class_q(0 to 1) when others; +with wr_entry17_sel(1) select + entry17_extclass_d <= wr_cam_data(63 to 64) when '1', + entry17_extclass_q(0 to 1) when others; +with wr_entry17_sel(1) select + entry17_hv_d <= wr_cam_data(65) when '1', + entry17_hv_q when others; +with wr_entry17_sel(1) select + entry17_ds_d <= wr_cam_data(66) when '1', + entry17_ds_q when others; +with wr_entry17_sel(1) select + entry17_pid_d <= wr_cam_data(67 to 74) when '1', + entry17_pid_q(0 to 7) when others; +with wr_entry17_sel(0) select + entry17_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry17_cmpmask_q when others; +-- the cam parity bits.. some wr_array_data bits contain parity for cam +with wr_entry17_sel(0) select + entry17_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry17_parity_q(0 to 3) when others; +with wr_entry17_sel(0) select + entry17_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry17_parity_q(4 to 6) when others; +with wr_entry17_sel(0) select + entry17_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry17_parity_q(7) when others; +with wr_entry17_sel(1) select + entry17_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry17_parity_q(8) when others; +with wr_entry17_sel(1) select + entry17_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry17_parity_q(9) when others; +wr_entry18_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="10010")) else '0'; +wr_entry18_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="10010")) else '0'; +with wr_entry18_sel(0) select + entry18_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry18_epn_q(0 to 31) when others; +with wr_entry18_sel(0) select + entry18_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry18_epn_q(32 to 51) when others; +with wr_entry18_sel(0) select + entry18_xbit_d <= wr_cam_data(52) when '1', + entry18_xbit_q when others; +with wr_entry18_sel(0) select + entry18_size_d <= wr_cam_data(53 to 55) when '1', + entry18_size_q(0 to 2) when others; +with wr_entry18_sel(0) select + entry18_class_d <= wr_cam_data(61 to 62) when '1', + entry18_class_q(0 to 1) when others; +with wr_entry18_sel(1) select + entry18_extclass_d <= wr_cam_data(63 to 64) when '1', + entry18_extclass_q(0 to 1) when others; +with wr_entry18_sel(1) select + entry18_hv_d <= wr_cam_data(65) when '1', + entry18_hv_q when others; +with wr_entry18_sel(1) select + entry18_ds_d <= wr_cam_data(66) when '1', + entry18_ds_q when others; +with wr_entry18_sel(1) select + entry18_pid_d <= wr_cam_data(67 to 74) when '1', + entry18_pid_q(0 to 7) when others; +with wr_entry18_sel(0) select + entry18_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry18_cmpmask_q when others; +-- the cam parity bits.. some wr_array_data bits contain parity for cam +with wr_entry18_sel(0) select + entry18_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry18_parity_q(0 to 3) when others; +with wr_entry18_sel(0) select + entry18_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry18_parity_q(4 to 6) when others; +with wr_entry18_sel(0) select + entry18_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry18_parity_q(7) when others; +with wr_entry18_sel(1) select + entry18_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry18_parity_q(8) when others; +with wr_entry18_sel(1) select + entry18_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry18_parity_q(9) when others; +wr_entry19_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="10011")) else '0'; +wr_entry19_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="10011")) else '0'; +with wr_entry19_sel(0) select + entry19_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry19_epn_q(0 to 31) when others; +with wr_entry19_sel(0) select + entry19_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry19_epn_q(32 to 51) when others; +with wr_entry19_sel(0) select + entry19_xbit_d <= wr_cam_data(52) when '1', + entry19_xbit_q when others; +with wr_entry19_sel(0) select + entry19_size_d <= wr_cam_data(53 to 55) when '1', + entry19_size_q(0 to 2) when others; +with wr_entry19_sel(0) select + entry19_class_d <= wr_cam_data(61 to 62) when '1', + entry19_class_q(0 to 1) when others; +with wr_entry19_sel(1) select + entry19_extclass_d <= wr_cam_data(63 to 64) when '1', + entry19_extclass_q(0 to 1) when others; +with wr_entry19_sel(1) select + entry19_hv_d <= wr_cam_data(65) when '1', + entry19_hv_q when others; +with wr_entry19_sel(1) select + entry19_ds_d <= wr_cam_data(66) when '1', + entry19_ds_q when others; +with wr_entry19_sel(1) select + entry19_pid_d <= wr_cam_data(67 to 74) when '1', + entry19_pid_q(0 to 7) when others; +with wr_entry19_sel(0) select + entry19_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry19_cmpmask_q when others; +-- the cam parity bits.. some wr_array_data bits contain parity for cam +with wr_entry19_sel(0) select + entry19_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry19_parity_q(0 to 3) when others; +with wr_entry19_sel(0) select + entry19_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry19_parity_q(4 to 6) when others; +with wr_entry19_sel(0) select + entry19_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry19_parity_q(7) when others; +with wr_entry19_sel(1) select + entry19_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry19_parity_q(8) when others; +with wr_entry19_sel(1) select + entry19_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry19_parity_q(9) when others; +wr_entry20_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="10100")) else '0'; +wr_entry20_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="10100")) else '0'; +with wr_entry20_sel(0) select + entry20_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry20_epn_q(0 to 31) when others; +with wr_entry20_sel(0) select + entry20_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry20_epn_q(32 to 51) when others; +with wr_entry20_sel(0) select + entry20_xbit_d <= wr_cam_data(52) when '1', + entry20_xbit_q when others; +with wr_entry20_sel(0) select + entry20_size_d <= wr_cam_data(53 to 55) when '1', + entry20_size_q(0 to 2) when others; +with wr_entry20_sel(0) select + entry20_class_d <= wr_cam_data(61 to 62) when '1', + entry20_class_q(0 to 1) when others; +with wr_entry20_sel(1) select + entry20_extclass_d <= wr_cam_data(63 to 64) when '1', + entry20_extclass_q(0 to 1) when others; +with wr_entry20_sel(1) select + entry20_hv_d <= wr_cam_data(65) when '1', + entry20_hv_q when others; +with wr_entry20_sel(1) select + entry20_ds_d <= wr_cam_data(66) when '1', + entry20_ds_q when others; +with wr_entry20_sel(1) select + entry20_pid_d <= wr_cam_data(67 to 74) when '1', + entry20_pid_q(0 to 7) when others; +with wr_entry20_sel(0) select + entry20_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry20_cmpmask_q when others; +-- the cam parity bits.. some wr_array_data bits contain parity for cam +with wr_entry20_sel(0) select + entry20_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry20_parity_q(0 to 3) when others; +with wr_entry20_sel(0) select + entry20_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry20_parity_q(4 to 6) when others; +with wr_entry20_sel(0) select + entry20_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry20_parity_q(7) when others; +with wr_entry20_sel(1) select + entry20_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry20_parity_q(8) when others; +with wr_entry20_sel(1) select + entry20_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry20_parity_q(9) when others; +wr_entry21_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="10101")) else '0'; +wr_entry21_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="10101")) else '0'; +with wr_entry21_sel(0) select + entry21_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry21_epn_q(0 to 31) when others; +with wr_entry21_sel(0) select + entry21_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry21_epn_q(32 to 51) when others; +with wr_entry21_sel(0) select + entry21_xbit_d <= wr_cam_data(52) when '1', + entry21_xbit_q when others; +with wr_entry21_sel(0) select + entry21_size_d <= wr_cam_data(53 to 55) when '1', + entry21_size_q(0 to 2) when others; +with wr_entry21_sel(0) select + entry21_class_d <= wr_cam_data(61 to 62) when '1', + entry21_class_q(0 to 1) when others; +with wr_entry21_sel(1) select + entry21_extclass_d <= wr_cam_data(63 to 64) when '1', + entry21_extclass_q(0 to 1) when others; +with wr_entry21_sel(1) select + entry21_hv_d <= wr_cam_data(65) when '1', + entry21_hv_q when others; +with wr_entry21_sel(1) select + entry21_ds_d <= wr_cam_data(66) when '1', + entry21_ds_q when others; +with wr_entry21_sel(1) select + entry21_pid_d <= wr_cam_data(67 to 74) when '1', + entry21_pid_q(0 to 7) when others; +with wr_entry21_sel(0) select + entry21_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry21_cmpmask_q when others; +-- the cam parity bits.. some wr_array_data bits contain parity for cam +with wr_entry21_sel(0) select + entry21_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry21_parity_q(0 to 3) when others; +with wr_entry21_sel(0) select + entry21_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry21_parity_q(4 to 6) when others; +with wr_entry21_sel(0) select + entry21_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry21_parity_q(7) when others; +with wr_entry21_sel(1) select + entry21_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry21_parity_q(8) when others; +with wr_entry21_sel(1) select + entry21_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry21_parity_q(9) when others; +wr_entry22_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="10110")) else '0'; +wr_entry22_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="10110")) else '0'; +with wr_entry22_sel(0) select + entry22_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry22_epn_q(0 to 31) when others; +with wr_entry22_sel(0) select + entry22_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry22_epn_q(32 to 51) when others; +with wr_entry22_sel(0) select + entry22_xbit_d <= wr_cam_data(52) when '1', + entry22_xbit_q when others; +with wr_entry22_sel(0) select + entry22_size_d <= wr_cam_data(53 to 55) when '1', + entry22_size_q(0 to 2) when others; +with wr_entry22_sel(0) select + entry22_class_d <= wr_cam_data(61 to 62) when '1', + entry22_class_q(0 to 1) when others; +with wr_entry22_sel(1) select + entry22_extclass_d <= wr_cam_data(63 to 64) when '1', + entry22_extclass_q(0 to 1) when others; +with wr_entry22_sel(1) select + entry22_hv_d <= wr_cam_data(65) when '1', + entry22_hv_q when others; +with wr_entry22_sel(1) select + entry22_ds_d <= wr_cam_data(66) when '1', + entry22_ds_q when others; +with wr_entry22_sel(1) select + entry22_pid_d <= wr_cam_data(67 to 74) when '1', + entry22_pid_q(0 to 7) when others; +with wr_entry22_sel(0) select + entry22_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry22_cmpmask_q when others; +-- the cam parity bits.. some wr_array_data bits contain parity for cam +with wr_entry22_sel(0) select + entry22_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry22_parity_q(0 to 3) when others; +with wr_entry22_sel(0) select + entry22_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry22_parity_q(4 to 6) when others; +with wr_entry22_sel(0) select + entry22_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry22_parity_q(7) when others; +with wr_entry22_sel(1) select + entry22_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry22_parity_q(8) when others; +with wr_entry22_sel(1) select + entry22_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry22_parity_q(9) when others; +wr_entry23_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="10111")) else '0'; +wr_entry23_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="10111")) else '0'; +with wr_entry23_sel(0) select + entry23_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry23_epn_q(0 to 31) when others; +with wr_entry23_sel(0) select + entry23_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry23_epn_q(32 to 51) when others; +with wr_entry23_sel(0) select + entry23_xbit_d <= wr_cam_data(52) when '1', + entry23_xbit_q when others; +with wr_entry23_sel(0) select + entry23_size_d <= wr_cam_data(53 to 55) when '1', + entry23_size_q(0 to 2) when others; +with wr_entry23_sel(0) select + entry23_class_d <= wr_cam_data(61 to 62) when '1', + entry23_class_q(0 to 1) when others; +with wr_entry23_sel(1) select + entry23_extclass_d <= wr_cam_data(63 to 64) when '1', + entry23_extclass_q(0 to 1) when others; +with wr_entry23_sel(1) select + entry23_hv_d <= wr_cam_data(65) when '1', + entry23_hv_q when others; +with wr_entry23_sel(1) select + entry23_ds_d <= wr_cam_data(66) when '1', + entry23_ds_q when others; +with wr_entry23_sel(1) select + entry23_pid_d <= wr_cam_data(67 to 74) when '1', + entry23_pid_q(0 to 7) when others; +with wr_entry23_sel(0) select + entry23_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry23_cmpmask_q when others; +-- the cam parity bits.. some wr_array_data bits contain parity for cam +with wr_entry23_sel(0) select + entry23_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry23_parity_q(0 to 3) when others; +with wr_entry23_sel(0) select + entry23_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry23_parity_q(4 to 6) when others; +with wr_entry23_sel(0) select + entry23_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry23_parity_q(7) when others; +with wr_entry23_sel(1) select + entry23_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry23_parity_q(8) when others; +with wr_entry23_sel(1) select + entry23_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry23_parity_q(9) when others; +wr_entry24_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="11000")) else '0'; +wr_entry24_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="11000")) else '0'; +with wr_entry24_sel(0) select + entry24_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry24_epn_q(0 to 31) when others; +with wr_entry24_sel(0) select + entry24_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry24_epn_q(32 to 51) when others; +with wr_entry24_sel(0) select + entry24_xbit_d <= wr_cam_data(52) when '1', + entry24_xbit_q when others; +with wr_entry24_sel(0) select + entry24_size_d <= wr_cam_data(53 to 55) when '1', + entry24_size_q(0 to 2) when others; +with wr_entry24_sel(0) select + entry24_class_d <= wr_cam_data(61 to 62) when '1', + entry24_class_q(0 to 1) when others; +with wr_entry24_sel(1) select + entry24_extclass_d <= wr_cam_data(63 to 64) when '1', + entry24_extclass_q(0 to 1) when others; +with wr_entry24_sel(1) select + entry24_hv_d <= wr_cam_data(65) when '1', + entry24_hv_q when others; +with wr_entry24_sel(1) select + entry24_ds_d <= wr_cam_data(66) when '1', + entry24_ds_q when others; +with wr_entry24_sel(1) select + entry24_pid_d <= wr_cam_data(67 to 74) when '1', + entry24_pid_q(0 to 7) when others; +with wr_entry24_sel(0) select + entry24_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry24_cmpmask_q when others; +-- the cam parity bits.. some wr_array_data bits contain parity for cam +with wr_entry24_sel(0) select + entry24_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry24_parity_q(0 to 3) when others; +with wr_entry24_sel(0) select + entry24_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry24_parity_q(4 to 6) when others; +with wr_entry24_sel(0) select + entry24_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry24_parity_q(7) when others; +with wr_entry24_sel(1) select + entry24_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry24_parity_q(8) when others; +with wr_entry24_sel(1) select + entry24_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry24_parity_q(9) when others; +wr_entry25_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="11001")) else '0'; +wr_entry25_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="11001")) else '0'; +with wr_entry25_sel(0) select + entry25_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry25_epn_q(0 to 31) when others; +with wr_entry25_sel(0) select + entry25_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry25_epn_q(32 to 51) when others; +with wr_entry25_sel(0) select + entry25_xbit_d <= wr_cam_data(52) when '1', + entry25_xbit_q when others; +with wr_entry25_sel(0) select + entry25_size_d <= wr_cam_data(53 to 55) when '1', + entry25_size_q(0 to 2) when others; +with wr_entry25_sel(0) select + entry25_class_d <= wr_cam_data(61 to 62) when '1', + entry25_class_q(0 to 1) when others; +with wr_entry25_sel(1) select + entry25_extclass_d <= wr_cam_data(63 to 64) when '1', + entry25_extclass_q(0 to 1) when others; +with wr_entry25_sel(1) select + entry25_hv_d <= wr_cam_data(65) when '1', + entry25_hv_q when others; +with wr_entry25_sel(1) select + entry25_ds_d <= wr_cam_data(66) when '1', + entry25_ds_q when others; +with wr_entry25_sel(1) select + entry25_pid_d <= wr_cam_data(67 to 74) when '1', + entry25_pid_q(0 to 7) when others; +with wr_entry25_sel(0) select + entry25_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry25_cmpmask_q when others; +-- the cam parity bits.. some wr_array_data bits contain parity for cam +with wr_entry25_sel(0) select + entry25_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry25_parity_q(0 to 3) when others; +with wr_entry25_sel(0) select + entry25_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry25_parity_q(4 to 6) when others; +with wr_entry25_sel(0) select + entry25_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry25_parity_q(7) when others; +with wr_entry25_sel(1) select + entry25_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry25_parity_q(8) when others; +with wr_entry25_sel(1) select + entry25_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry25_parity_q(9) when others; +wr_entry26_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="11010")) else '0'; +wr_entry26_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="11010")) else '0'; +with wr_entry26_sel(0) select + entry26_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry26_epn_q(0 to 31) when others; +with wr_entry26_sel(0) select + entry26_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry26_epn_q(32 to 51) when others; +with wr_entry26_sel(0) select + entry26_xbit_d <= wr_cam_data(52) when '1', + entry26_xbit_q when others; +with wr_entry26_sel(0) select + entry26_size_d <= wr_cam_data(53 to 55) when '1', + entry26_size_q(0 to 2) when others; +with wr_entry26_sel(0) select + entry26_class_d <= wr_cam_data(61 to 62) when '1', + entry26_class_q(0 to 1) when others; +with wr_entry26_sel(1) select + entry26_extclass_d <= wr_cam_data(63 to 64) when '1', + entry26_extclass_q(0 to 1) when others; +with wr_entry26_sel(1) select + entry26_hv_d <= wr_cam_data(65) when '1', + entry26_hv_q when others; +with wr_entry26_sel(1) select + entry26_ds_d <= wr_cam_data(66) when '1', + entry26_ds_q when others; +with wr_entry26_sel(1) select + entry26_pid_d <= wr_cam_data(67 to 74) when '1', + entry26_pid_q(0 to 7) when others; +with wr_entry26_sel(0) select + entry26_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry26_cmpmask_q when others; +-- the cam parity bits.. some wr_array_data bits contain parity for cam +with wr_entry26_sel(0) select + entry26_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry26_parity_q(0 to 3) when others; +with wr_entry26_sel(0) select + entry26_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry26_parity_q(4 to 6) when others; +with wr_entry26_sel(0) select + entry26_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry26_parity_q(7) when others; +with wr_entry26_sel(1) select + entry26_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry26_parity_q(8) when others; +with wr_entry26_sel(1) select + entry26_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry26_parity_q(9) when others; +wr_entry27_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="11011")) else '0'; +wr_entry27_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="11011")) else '0'; +with wr_entry27_sel(0) select + entry27_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry27_epn_q(0 to 31) when others; +with wr_entry27_sel(0) select + entry27_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry27_epn_q(32 to 51) when others; +with wr_entry27_sel(0) select + entry27_xbit_d <= wr_cam_data(52) when '1', + entry27_xbit_q when others; +with wr_entry27_sel(0) select + entry27_size_d <= wr_cam_data(53 to 55) when '1', + entry27_size_q(0 to 2) when others; +with wr_entry27_sel(0) select + entry27_class_d <= wr_cam_data(61 to 62) when '1', + entry27_class_q(0 to 1) when others; +with wr_entry27_sel(1) select + entry27_extclass_d <= wr_cam_data(63 to 64) when '1', + entry27_extclass_q(0 to 1) when others; +with wr_entry27_sel(1) select + entry27_hv_d <= wr_cam_data(65) when '1', + entry27_hv_q when others; +with wr_entry27_sel(1) select + entry27_ds_d <= wr_cam_data(66) when '1', + entry27_ds_q when others; +with wr_entry27_sel(1) select + entry27_pid_d <= wr_cam_data(67 to 74) when '1', + entry27_pid_q(0 to 7) when others; +with wr_entry27_sel(0) select + entry27_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry27_cmpmask_q when others; +-- the cam parity bits.. some wr_array_data bits contain parity for cam +with wr_entry27_sel(0) select + entry27_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry27_parity_q(0 to 3) when others; +with wr_entry27_sel(0) select + entry27_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry27_parity_q(4 to 6) when others; +with wr_entry27_sel(0) select + entry27_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry27_parity_q(7) when others; +with wr_entry27_sel(1) select + entry27_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry27_parity_q(8) when others; +with wr_entry27_sel(1) select + entry27_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry27_parity_q(9) when others; +wr_entry28_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="11100")) else '0'; +wr_entry28_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="11100")) else '0'; +with wr_entry28_sel(0) select + entry28_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry28_epn_q(0 to 31) when others; +with wr_entry28_sel(0) select + entry28_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry28_epn_q(32 to 51) when others; +with wr_entry28_sel(0) select + entry28_xbit_d <= wr_cam_data(52) when '1', + entry28_xbit_q when others; +with wr_entry28_sel(0) select + entry28_size_d <= wr_cam_data(53 to 55) when '1', + entry28_size_q(0 to 2) when others; +with wr_entry28_sel(0) select + entry28_class_d <= wr_cam_data(61 to 62) when '1', + entry28_class_q(0 to 1) when others; +with wr_entry28_sel(1) select + entry28_extclass_d <= wr_cam_data(63 to 64) when '1', + entry28_extclass_q(0 to 1) when others; +with wr_entry28_sel(1) select + entry28_hv_d <= wr_cam_data(65) when '1', + entry28_hv_q when others; +with wr_entry28_sel(1) select + entry28_ds_d <= wr_cam_data(66) when '1', + entry28_ds_q when others; +with wr_entry28_sel(1) select + entry28_pid_d <= wr_cam_data(67 to 74) when '1', + entry28_pid_q(0 to 7) when others; +with wr_entry28_sel(0) select + entry28_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry28_cmpmask_q when others; +-- the cam parity bits.. some wr_array_data bits contain parity for cam +with wr_entry28_sel(0) select + entry28_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry28_parity_q(0 to 3) when others; +with wr_entry28_sel(0) select + entry28_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry28_parity_q(4 to 6) when others; +with wr_entry28_sel(0) select + entry28_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry28_parity_q(7) when others; +with wr_entry28_sel(1) select + entry28_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry28_parity_q(8) when others; +with wr_entry28_sel(1) select + entry28_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry28_parity_q(9) when others; +wr_entry29_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="11101")) else '0'; +wr_entry29_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="11101")) else '0'; +with wr_entry29_sel(0) select + entry29_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry29_epn_q(0 to 31) when others; +with wr_entry29_sel(0) select + entry29_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry29_epn_q(32 to 51) when others; +with wr_entry29_sel(0) select + entry29_xbit_d <= wr_cam_data(52) when '1', + entry29_xbit_q when others; +with wr_entry29_sel(0) select + entry29_size_d <= wr_cam_data(53 to 55) when '1', + entry29_size_q(0 to 2) when others; +with wr_entry29_sel(0) select + entry29_class_d <= wr_cam_data(61 to 62) when '1', + entry29_class_q(0 to 1) when others; +with wr_entry29_sel(1) select + entry29_extclass_d <= wr_cam_data(63 to 64) when '1', + entry29_extclass_q(0 to 1) when others; +with wr_entry29_sel(1) select + entry29_hv_d <= wr_cam_data(65) when '1', + entry29_hv_q when others; +with wr_entry29_sel(1) select + entry29_ds_d <= wr_cam_data(66) when '1', + entry29_ds_q when others; +with wr_entry29_sel(1) select + entry29_pid_d <= wr_cam_data(67 to 74) when '1', + entry29_pid_q(0 to 7) when others; +with wr_entry29_sel(0) select + entry29_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry29_cmpmask_q when others; +-- the cam parity bits.. some wr_array_data bits contain parity for cam +with wr_entry29_sel(0) select + entry29_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry29_parity_q(0 to 3) when others; +with wr_entry29_sel(0) select + entry29_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry29_parity_q(4 to 6) when others; +with wr_entry29_sel(0) select + entry29_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry29_parity_q(7) when others; +with wr_entry29_sel(1) select + entry29_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry29_parity_q(8) when others; +with wr_entry29_sel(1) select + entry29_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry29_parity_q(9) when others; +wr_entry30_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="11110")) else '0'; +wr_entry30_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="11110")) else '0'; +with wr_entry30_sel(0) select + entry30_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry30_epn_q(0 to 31) when others; +with wr_entry30_sel(0) select + entry30_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry30_epn_q(32 to 51) when others; +with wr_entry30_sel(0) select + entry30_xbit_d <= wr_cam_data(52) when '1', + entry30_xbit_q when others; +with wr_entry30_sel(0) select + entry30_size_d <= wr_cam_data(53 to 55) when '1', + entry30_size_q(0 to 2) when others; +with wr_entry30_sel(0) select + entry30_class_d <= wr_cam_data(61 to 62) when '1', + entry30_class_q(0 to 1) when others; +with wr_entry30_sel(1) select + entry30_extclass_d <= wr_cam_data(63 to 64) when '1', + entry30_extclass_q(0 to 1) when others; +with wr_entry30_sel(1) select + entry30_hv_d <= wr_cam_data(65) when '1', + entry30_hv_q when others; +with wr_entry30_sel(1) select + entry30_ds_d <= wr_cam_data(66) when '1', + entry30_ds_q when others; +with wr_entry30_sel(1) select + entry30_pid_d <= wr_cam_data(67 to 74) when '1', + entry30_pid_q(0 to 7) when others; +with wr_entry30_sel(0) select + entry30_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry30_cmpmask_q when others; +-- the cam parity bits.. some wr_array_data bits contain parity for cam +with wr_entry30_sel(0) select + entry30_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry30_parity_q(0 to 3) when others; +with wr_entry30_sel(0) select + entry30_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry30_parity_q(4 to 6) when others; +with wr_entry30_sel(0) select + entry30_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry30_parity_q(7) when others; +with wr_entry30_sel(1) select + entry30_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry30_parity_q(8) when others; +with wr_entry30_sel(1) select + entry30_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry30_parity_q(9) when others; +wr_entry31_sel(0) <= '1' when ((wr_cam_val(0)='1') and (rw_entry="11111")) else '0'; +wr_entry31_sel(1) <= '1' when ((wr_cam_val(1)='1') and (rw_entry="11111")) else '0'; +with wr_entry31_sel(0) select + entry31_epn_d(0 to 31) <= wr_cam_data(0 to 31) when '1', + entry31_epn_q(0 to 31) when others; +with wr_entry31_sel(0) select + entry31_epn_d(32 to 51) <= wr_cam_data(32 to 51) when '1', + entry31_epn_q(32 to 51) when others; +with wr_entry31_sel(0) select + entry31_xbit_d <= wr_cam_data(52) when '1', + entry31_xbit_q when others; +with wr_entry31_sel(0) select + entry31_size_d <= wr_cam_data(53 to 55) when '1', + entry31_size_q(0 to 2) when others; +with wr_entry31_sel(0) select + entry31_class_d <= wr_cam_data(61 to 62) when '1', + entry31_class_q(0 to 1) when others; +with wr_entry31_sel(1) select + entry31_extclass_d <= wr_cam_data(63 to 64) when '1', + entry31_extclass_q(0 to 1) when others; +with wr_entry31_sel(1) select + entry31_hv_d <= wr_cam_data(65) when '1', + entry31_hv_q when others; +with wr_entry31_sel(1) select + entry31_ds_d <= wr_cam_data(66) when '1', + entry31_ds_q when others; +with wr_entry31_sel(1) select + entry31_pid_d <= wr_cam_data(67 to 74) when '1', + entry31_pid_q(0 to 7) when others; +with wr_entry31_sel(0) select + entry31_cmpmask_d <= wr_cam_data(75 to 83) when '1', + entry31_cmpmask_q when others; +-- the cam parity bits.. some wr_array_data bits contain parity for cam +with wr_entry31_sel(0) select + entry31_parity_d(0 to 3) <= wr_array_data(rpn_width+21 to rpn_width+24) when '1', + entry31_parity_q(0 to 3) when others; +with wr_entry31_sel(0) select + entry31_parity_d(4 to 6) <= wr_array_data(rpn_width+25 to rpn_width+27) when '1', + entry31_parity_q(4 to 6) when others; +with wr_entry31_sel(0) select + entry31_parity_d(7) <= wr_array_data(rpn_width+28) when '1', + entry31_parity_q(7) when others; +with wr_entry31_sel(1) select + entry31_parity_d(8) <= wr_array_data(rpn_width+29) when '1', + entry31_parity_q(8) when others; +with wr_entry31_sel(1) select + entry31_parity_d(9) <= wr_array_data(rpn_width+30) when '1', + entry31_parity_q(9) when others; +-- entry valid and thdid next state logic +entry0_inval <= (comp_invalidate and match_vec(0)) or flash_invalidate; +entry0_v_muxsel(0 to 1) <= (entry0_inval & wr_entry0_sel(0)); +with entry0_v_muxsel(0 to 1) select + entry0_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry0_v_q when others; +with wr_entry0_sel(0) select + entry0_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry0_thdid_q(0 to 3) when others; +entry1_inval <= (comp_invalidate and match_vec(1)) or flash_invalidate; +entry1_v_muxsel(0 to 1) <= (entry1_inval & wr_entry1_sel(0)); +with entry1_v_muxsel(0 to 1) select + entry1_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry1_v_q when others; +with wr_entry1_sel(0) select + entry1_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry1_thdid_q(0 to 3) when others; +entry2_inval <= (comp_invalidate and match_vec(2)) or flash_invalidate; +entry2_v_muxsel(0 to 1) <= (entry2_inval & wr_entry2_sel(0)); +with entry2_v_muxsel(0 to 1) select + entry2_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry2_v_q when others; +with wr_entry2_sel(0) select + entry2_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry2_thdid_q(0 to 3) when others; +entry3_inval <= (comp_invalidate and match_vec(3)) or flash_invalidate; +entry3_v_muxsel(0 to 1) <= (entry3_inval & wr_entry3_sel(0)); +with entry3_v_muxsel(0 to 1) select + entry3_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry3_v_q when others; +with wr_entry3_sel(0) select + entry3_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry3_thdid_q(0 to 3) when others; +entry4_inval <= (comp_invalidate and match_vec(4)) or flash_invalidate; +entry4_v_muxsel(0 to 1) <= (entry4_inval & wr_entry4_sel(0)); +with entry4_v_muxsel(0 to 1) select + entry4_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry4_v_q when others; +with wr_entry4_sel(0) select + entry4_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry4_thdid_q(0 to 3) when others; +entry5_inval <= (comp_invalidate and match_vec(5)) or flash_invalidate; +entry5_v_muxsel(0 to 1) <= (entry5_inval & wr_entry5_sel(0)); +with entry5_v_muxsel(0 to 1) select + entry5_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry5_v_q when others; +with wr_entry5_sel(0) select + entry5_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry5_thdid_q(0 to 3) when others; +entry6_inval <= (comp_invalidate and match_vec(6)) or flash_invalidate; +entry6_v_muxsel(0 to 1) <= (entry6_inval & wr_entry6_sel(0)); +with entry6_v_muxsel(0 to 1) select + entry6_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry6_v_q when others; +with wr_entry6_sel(0) select + entry6_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry6_thdid_q(0 to 3) when others; +entry7_inval <= (comp_invalidate and match_vec(7)) or flash_invalidate; +entry7_v_muxsel(0 to 1) <= (entry7_inval & wr_entry7_sel(0)); +with entry7_v_muxsel(0 to 1) select + entry7_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry7_v_q when others; +with wr_entry7_sel(0) select + entry7_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry7_thdid_q(0 to 3) when others; +entry8_inval <= (comp_invalidate and match_vec(8)) or flash_invalidate; +entry8_v_muxsel(0 to 1) <= (entry8_inval & wr_entry8_sel(0)); +with entry8_v_muxsel(0 to 1) select + entry8_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry8_v_q when others; +with wr_entry8_sel(0) select + entry8_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry8_thdid_q(0 to 3) when others; +entry9_inval <= (comp_invalidate and match_vec(9)) or flash_invalidate; +entry9_v_muxsel(0 to 1) <= (entry9_inval & wr_entry9_sel(0)); +with entry9_v_muxsel(0 to 1) select + entry9_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry9_v_q when others; +with wr_entry9_sel(0) select + entry9_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry9_thdid_q(0 to 3) when others; +entry10_inval <= (comp_invalidate and match_vec(10)) or flash_invalidate; +entry10_v_muxsel(0 to 1) <= (entry10_inval & wr_entry10_sel(0)); +with entry10_v_muxsel(0 to 1) select + entry10_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry10_v_q when others; +with wr_entry10_sel(0) select + entry10_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry10_thdid_q(0 to 3) when others; +entry11_inval <= (comp_invalidate and match_vec(11)) or flash_invalidate; +entry11_v_muxsel(0 to 1) <= (entry11_inval & wr_entry11_sel(0)); +with entry11_v_muxsel(0 to 1) select + entry11_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry11_v_q when others; +with wr_entry11_sel(0) select + entry11_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry11_thdid_q(0 to 3) when others; +entry12_inval <= (comp_invalidate and match_vec(12)) or flash_invalidate; +entry12_v_muxsel(0 to 1) <= (entry12_inval & wr_entry12_sel(0)); +with entry12_v_muxsel(0 to 1) select + entry12_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry12_v_q when others; +with wr_entry12_sel(0) select + entry12_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry12_thdid_q(0 to 3) when others; +entry13_inval <= (comp_invalidate and match_vec(13)) or flash_invalidate; +entry13_v_muxsel(0 to 1) <= (entry13_inval & wr_entry13_sel(0)); +with entry13_v_muxsel(0 to 1) select + entry13_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry13_v_q when others; +with wr_entry13_sel(0) select + entry13_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry13_thdid_q(0 to 3) when others; +entry14_inval <= (comp_invalidate and match_vec(14)) or flash_invalidate; +entry14_v_muxsel(0 to 1) <= (entry14_inval & wr_entry14_sel(0)); +with entry14_v_muxsel(0 to 1) select + entry14_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry14_v_q when others; +with wr_entry14_sel(0) select + entry14_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry14_thdid_q(0 to 3) when others; +entry15_inval <= (comp_invalidate and match_vec(15)) or flash_invalidate; +entry15_v_muxsel(0 to 1) <= (entry15_inval & wr_entry15_sel(0)); +with entry15_v_muxsel(0 to 1) select + entry15_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry15_v_q when others; +with wr_entry15_sel(0) select + entry15_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry15_thdid_q(0 to 3) when others; +entry16_inval <= (comp_invalidate and match_vec(16)) or flash_invalidate; +entry16_v_muxsel(0 to 1) <= (entry16_inval & wr_entry16_sel(0)); +with entry16_v_muxsel(0 to 1) select + entry16_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry16_v_q when others; +with wr_entry16_sel(0) select + entry16_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry16_thdid_q(0 to 3) when others; +entry17_inval <= (comp_invalidate and match_vec(17)) or flash_invalidate; +entry17_v_muxsel(0 to 1) <= (entry17_inval & wr_entry17_sel(0)); +with entry17_v_muxsel(0 to 1) select + entry17_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry17_v_q when others; +with wr_entry17_sel(0) select + entry17_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry17_thdid_q(0 to 3) when others; +entry18_inval <= (comp_invalidate and match_vec(18)) or flash_invalidate; +entry18_v_muxsel(0 to 1) <= (entry18_inval & wr_entry18_sel(0)); +with entry18_v_muxsel(0 to 1) select + entry18_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry18_v_q when others; +with wr_entry18_sel(0) select + entry18_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry18_thdid_q(0 to 3) when others; +entry19_inval <= (comp_invalidate and match_vec(19)) or flash_invalidate; +entry19_v_muxsel(0 to 1) <= (entry19_inval & wr_entry19_sel(0)); +with entry19_v_muxsel(0 to 1) select + entry19_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry19_v_q when others; +with wr_entry19_sel(0) select + entry19_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry19_thdid_q(0 to 3) when others; +entry20_inval <= (comp_invalidate and match_vec(20)) or flash_invalidate; +entry20_v_muxsel(0 to 1) <= (entry20_inval & wr_entry20_sel(0)); +with entry20_v_muxsel(0 to 1) select + entry20_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry20_v_q when others; +with wr_entry20_sel(0) select + entry20_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry20_thdid_q(0 to 3) when others; +entry21_inval <= (comp_invalidate and match_vec(21)) or flash_invalidate; +entry21_v_muxsel(0 to 1) <= (entry21_inval & wr_entry21_sel(0)); +with entry21_v_muxsel(0 to 1) select + entry21_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry21_v_q when others; +with wr_entry21_sel(0) select + entry21_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry21_thdid_q(0 to 3) when others; +entry22_inval <= (comp_invalidate and match_vec(22)) or flash_invalidate; +entry22_v_muxsel(0 to 1) <= (entry22_inval & wr_entry22_sel(0)); +with entry22_v_muxsel(0 to 1) select + entry22_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry22_v_q when others; +with wr_entry22_sel(0) select + entry22_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry22_thdid_q(0 to 3) when others; +entry23_inval <= (comp_invalidate and match_vec(23)) or flash_invalidate; +entry23_v_muxsel(0 to 1) <= (entry23_inval & wr_entry23_sel(0)); +with entry23_v_muxsel(0 to 1) select + entry23_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry23_v_q when others; +with wr_entry23_sel(0) select + entry23_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry23_thdid_q(0 to 3) when others; +entry24_inval <= (comp_invalidate and match_vec(24)) or flash_invalidate; +entry24_v_muxsel(0 to 1) <= (entry24_inval & wr_entry24_sel(0)); +with entry24_v_muxsel(0 to 1) select + entry24_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry24_v_q when others; +with wr_entry24_sel(0) select + entry24_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry24_thdid_q(0 to 3) when others; +entry25_inval <= (comp_invalidate and match_vec(25)) or flash_invalidate; +entry25_v_muxsel(0 to 1) <= (entry25_inval & wr_entry25_sel(0)); +with entry25_v_muxsel(0 to 1) select + entry25_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry25_v_q when others; +with wr_entry25_sel(0) select + entry25_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry25_thdid_q(0 to 3) when others; +entry26_inval <= (comp_invalidate and match_vec(26)) or flash_invalidate; +entry26_v_muxsel(0 to 1) <= (entry26_inval & wr_entry26_sel(0)); +with entry26_v_muxsel(0 to 1) select + entry26_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry26_v_q when others; +with wr_entry26_sel(0) select + entry26_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry26_thdid_q(0 to 3) when others; +entry27_inval <= (comp_invalidate and match_vec(27)) or flash_invalidate; +entry27_v_muxsel(0 to 1) <= (entry27_inval & wr_entry27_sel(0)); +with entry27_v_muxsel(0 to 1) select + entry27_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry27_v_q when others; +with wr_entry27_sel(0) select + entry27_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry27_thdid_q(0 to 3) when others; +entry28_inval <= (comp_invalidate and match_vec(28)) or flash_invalidate; +entry28_v_muxsel(0 to 1) <= (entry28_inval & wr_entry28_sel(0)); +with entry28_v_muxsel(0 to 1) select + entry28_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry28_v_q when others; +with wr_entry28_sel(0) select + entry28_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry28_thdid_q(0 to 3) when others; +entry29_inval <= (comp_invalidate and match_vec(29)) or flash_invalidate; +entry29_v_muxsel(0 to 1) <= (entry29_inval & wr_entry29_sel(0)); +with entry29_v_muxsel(0 to 1) select + entry29_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry29_v_q when others; +with wr_entry29_sel(0) select + entry29_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry29_thdid_q(0 to 3) when others; +entry30_inval <= (comp_invalidate and match_vec(30)) or flash_invalidate; +entry30_v_muxsel(0 to 1) <= (entry30_inval & wr_entry30_sel(0)); +with entry30_v_muxsel(0 to 1) select + entry30_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry30_v_q when others; +with wr_entry30_sel(0) select + entry30_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry30_thdid_q(0 to 3) when others; +entry31_inval <= (comp_invalidate and match_vec(31)) or flash_invalidate; +entry31_v_muxsel(0 to 1) <= (entry31_inval & wr_entry31_sel(0)); +with entry31_v_muxsel(0 to 1) select + entry31_v_d <= '0' when "10", + '0' when "11", + wr_cam_data(56) when "01", + entry31_v_q when others; +with wr_entry31_sel(0) select + entry31_thdid_d(0 to 3) <= wr_cam_data(57 to 60) when '1', + entry31_thdid_q(0 to 3) when others; +-- CAM compare data out mux +entry0_cam_vec <= entry0_epn_q & entry0_xbit_q & entry0_size_q & entry0_v_q & entry0_thdid_q & + entry0_class_q & entry0_extclass_q & entry0_hv_q & entry0_ds_q & entry0_pid_q & entry0_cmpmask_q; +entry1_cam_vec <= entry1_epn_q & entry1_xbit_q & entry1_size_q & entry1_v_q & entry1_thdid_q & + entry1_class_q & entry1_extclass_q & entry1_hv_q & entry1_ds_q & entry1_pid_q & entry1_cmpmask_q; +entry2_cam_vec <= entry2_epn_q & entry2_xbit_q & entry2_size_q & entry2_v_q & entry2_thdid_q & + entry2_class_q & entry2_extclass_q & entry2_hv_q & entry2_ds_q & entry2_pid_q & entry2_cmpmask_q; +entry3_cam_vec <= entry3_epn_q & entry3_xbit_q & entry3_size_q & entry3_v_q & entry3_thdid_q & + entry3_class_q & entry3_extclass_q & entry3_hv_q & entry3_ds_q & entry3_pid_q & entry3_cmpmask_q; +entry4_cam_vec <= entry4_epn_q & entry4_xbit_q & entry4_size_q & entry4_v_q & entry4_thdid_q & + entry4_class_q & entry4_extclass_q & entry4_hv_q & entry4_ds_q & entry4_pid_q & entry4_cmpmask_q; +entry5_cam_vec <= entry5_epn_q & entry5_xbit_q & entry5_size_q & entry5_v_q & entry5_thdid_q & + entry5_class_q & entry5_extclass_q & entry5_hv_q & entry5_ds_q & entry5_pid_q & entry5_cmpmask_q; +entry6_cam_vec <= entry6_epn_q & entry6_xbit_q & entry6_size_q & entry6_v_q & entry6_thdid_q & + entry6_class_q & entry6_extclass_q & entry6_hv_q & entry6_ds_q & entry6_pid_q & entry6_cmpmask_q; +entry7_cam_vec <= entry7_epn_q & entry7_xbit_q & entry7_size_q & entry7_v_q & entry7_thdid_q & + entry7_class_q & entry7_extclass_q & entry7_hv_q & entry7_ds_q & entry7_pid_q & entry7_cmpmask_q; +entry8_cam_vec <= entry8_epn_q & entry8_xbit_q & entry8_size_q & entry8_v_q & entry8_thdid_q & + entry8_class_q & entry8_extclass_q & entry8_hv_q & entry8_ds_q & entry8_pid_q & entry8_cmpmask_q; +entry9_cam_vec <= entry9_epn_q & entry9_xbit_q & entry9_size_q & entry9_v_q & entry9_thdid_q & + entry9_class_q & entry9_extclass_q & entry9_hv_q & entry9_ds_q & entry9_pid_q & entry9_cmpmask_q; +entry10_cam_vec <= entry10_epn_q & entry10_xbit_q & entry10_size_q & entry10_v_q & entry10_thdid_q & + entry10_class_q & entry10_extclass_q & entry10_hv_q & entry10_ds_q & entry10_pid_q & entry10_cmpmask_q; +entry11_cam_vec <= entry11_epn_q & entry11_xbit_q & entry11_size_q & entry11_v_q & entry11_thdid_q & + entry11_class_q & entry11_extclass_q & entry11_hv_q & entry11_ds_q & entry11_pid_q & entry11_cmpmask_q; +entry12_cam_vec <= entry12_epn_q & entry12_xbit_q & entry12_size_q & entry12_v_q & entry12_thdid_q & + entry12_class_q & entry12_extclass_q & entry12_hv_q & entry12_ds_q & entry12_pid_q & entry12_cmpmask_q; +entry13_cam_vec <= entry13_epn_q & entry13_xbit_q & entry13_size_q & entry13_v_q & entry13_thdid_q & + entry13_class_q & entry13_extclass_q & entry13_hv_q & entry13_ds_q & entry13_pid_q & entry13_cmpmask_q; +entry14_cam_vec <= entry14_epn_q & entry14_xbit_q & entry14_size_q & entry14_v_q & entry14_thdid_q & + entry14_class_q & entry14_extclass_q & entry14_hv_q & entry14_ds_q & entry14_pid_q & entry14_cmpmask_q; +entry15_cam_vec <= entry15_epn_q & entry15_xbit_q & entry15_size_q & entry15_v_q & entry15_thdid_q & + entry15_class_q & entry15_extclass_q & entry15_hv_q & entry15_ds_q & entry15_pid_q & entry15_cmpmask_q; +entry16_cam_vec <= entry16_epn_q & entry16_xbit_q & entry16_size_q & entry16_v_q & entry16_thdid_q & + entry16_class_q & entry16_extclass_q & entry16_hv_q & entry16_ds_q & entry16_pid_q & entry16_cmpmask_q; +entry17_cam_vec <= entry17_epn_q & entry17_xbit_q & entry17_size_q & entry17_v_q & entry17_thdid_q & + entry17_class_q & entry17_extclass_q & entry17_hv_q & entry17_ds_q & entry17_pid_q & entry17_cmpmask_q; +entry18_cam_vec <= entry18_epn_q & entry18_xbit_q & entry18_size_q & entry18_v_q & entry18_thdid_q & + entry18_class_q & entry18_extclass_q & entry18_hv_q & entry18_ds_q & entry18_pid_q & entry18_cmpmask_q; +entry19_cam_vec <= entry19_epn_q & entry19_xbit_q & entry19_size_q & entry19_v_q & entry19_thdid_q & + entry19_class_q & entry19_extclass_q & entry19_hv_q & entry19_ds_q & entry19_pid_q & entry19_cmpmask_q; +entry20_cam_vec <= entry20_epn_q & entry20_xbit_q & entry20_size_q & entry20_v_q & entry20_thdid_q & + entry20_class_q & entry20_extclass_q & entry20_hv_q & entry20_ds_q & entry20_pid_q & entry20_cmpmask_q; +entry21_cam_vec <= entry21_epn_q & entry21_xbit_q & entry21_size_q & entry21_v_q & entry21_thdid_q & + entry21_class_q & entry21_extclass_q & entry21_hv_q & entry21_ds_q & entry21_pid_q & entry21_cmpmask_q; +entry22_cam_vec <= entry22_epn_q & entry22_xbit_q & entry22_size_q & entry22_v_q & entry22_thdid_q & + entry22_class_q & entry22_extclass_q & entry22_hv_q & entry22_ds_q & entry22_pid_q & entry22_cmpmask_q; +entry23_cam_vec <= entry23_epn_q & entry23_xbit_q & entry23_size_q & entry23_v_q & entry23_thdid_q & + entry23_class_q & entry23_extclass_q & entry23_hv_q & entry23_ds_q & entry23_pid_q & entry23_cmpmask_q; +entry24_cam_vec <= entry24_epn_q & entry24_xbit_q & entry24_size_q & entry24_v_q & entry24_thdid_q & + entry24_class_q & entry24_extclass_q & entry24_hv_q & entry24_ds_q & entry24_pid_q & entry24_cmpmask_q; +entry25_cam_vec <= entry25_epn_q & entry25_xbit_q & entry25_size_q & entry25_v_q & entry25_thdid_q & + entry25_class_q & entry25_extclass_q & entry25_hv_q & entry25_ds_q & entry25_pid_q & entry25_cmpmask_q; +entry26_cam_vec <= entry26_epn_q & entry26_xbit_q & entry26_size_q & entry26_v_q & entry26_thdid_q & + entry26_class_q & entry26_extclass_q & entry26_hv_q & entry26_ds_q & entry26_pid_q & entry26_cmpmask_q; +entry27_cam_vec <= entry27_epn_q & entry27_xbit_q & entry27_size_q & entry27_v_q & entry27_thdid_q & + entry27_class_q & entry27_extclass_q & entry27_hv_q & entry27_ds_q & entry27_pid_q & entry27_cmpmask_q; +entry28_cam_vec <= entry28_epn_q & entry28_xbit_q & entry28_size_q & entry28_v_q & entry28_thdid_q & + entry28_class_q & entry28_extclass_q & entry28_hv_q & entry28_ds_q & entry28_pid_q & entry28_cmpmask_q; +entry29_cam_vec <= entry29_epn_q & entry29_xbit_q & entry29_size_q & entry29_v_q & entry29_thdid_q & + entry29_class_q & entry29_extclass_q & entry29_hv_q & entry29_ds_q & entry29_pid_q & entry29_cmpmask_q; +entry30_cam_vec <= entry30_epn_q & entry30_xbit_q & entry30_size_q & entry30_v_q & entry30_thdid_q & + entry30_class_q & entry30_extclass_q & entry30_hv_q & entry30_ds_q & entry30_pid_q & entry30_cmpmask_q; +entry31_cam_vec <= entry31_epn_q & entry31_xbit_q & entry31_size_q & entry31_v_q & entry31_thdid_q & + entry31_class_q & entry31_extclass_q & entry31_hv_q & entry31_ds_q & entry31_pid_q & entry31_cmpmask_q; +cam_cmp_data_muxsel <= not(comp_request) & cam_hit_entry_d; +with cam_cmp_data_muxsel select + cam_cmp_data_d <= entry0_cam_vec when "000000", + entry1_cam_vec when "000001", + entry2_cam_vec when "000010", + entry3_cam_vec when "000011", + entry4_cam_vec when "000100", + entry5_cam_vec when "000101", + entry6_cam_vec when "000110", + entry7_cam_vec when "000111", + entry8_cam_vec when "001000", + entry9_cam_vec when "001001", + entry10_cam_vec when "001010", + entry11_cam_vec when "001011", + entry12_cam_vec when "001100", + entry13_cam_vec when "001101", + entry14_cam_vec when "001110", + entry15_cam_vec when "001111", + entry16_cam_vec when "010000", + entry17_cam_vec when "010001", + entry18_cam_vec when "010010", + entry19_cam_vec when "010011", + entry20_cam_vec when "010100", + entry21_cam_vec when "010101", + entry22_cam_vec when "010110", + entry23_cam_vec when "010111", + entry24_cam_vec when "011000", + entry25_cam_vec when "011001", + entry26_cam_vec when "011010", + entry27_cam_vec when "011011", + entry28_cam_vec when "011100", + entry29_cam_vec when "011101", + entry30_cam_vec when "011110", + entry31_cam_vec when "011111", + cam_cmp_data_q when others; +cam_cmp_data_np1 <= cam_cmp_data_q; +-- CAM read data out mux +rd_cam_data_muxsel <= not(rd_val) & rw_entry; +with rd_cam_data_muxsel select + rd_cam_data_d <= entry0_cam_vec when "000000", + entry1_cam_vec when "000001", + entry2_cam_vec when "000010", + entry3_cam_vec when "000011", + entry4_cam_vec when "000100", + entry5_cam_vec when "000101", + entry6_cam_vec when "000110", + entry7_cam_vec when "000111", + entry8_cam_vec when "001000", + entry9_cam_vec when "001001", + entry10_cam_vec when "001010", + entry11_cam_vec when "001011", + entry12_cam_vec when "001100", + entry13_cam_vec when "001101", + entry14_cam_vec when "001110", + entry15_cam_vec when "001111", + entry16_cam_vec when "010000", + entry17_cam_vec when "010001", + entry18_cam_vec when "010010", + entry19_cam_vec when "010011", + entry20_cam_vec when "010100", + entry21_cam_vec when "010101", + entry22_cam_vec when "010110", + entry23_cam_vec when "010111", + entry24_cam_vec when "011000", + entry25_cam_vec when "011001", + entry26_cam_vec when "011010", + entry27_cam_vec when "011011", + entry28_cam_vec when "011100", + entry29_cam_vec when "011101", + entry30_cam_vec when "011110", + entry31_cam_vec when "011111", + rd_cam_data_q when others; +-- CAM compare parity out mux +with cam_cmp_data_muxsel select + cam_cmp_parity_d <= entry0_parity_q when "000000", + entry1_parity_q when "000001", + entry2_parity_q when "000010", + entry3_parity_q when "000011", + entry4_parity_q when "000100", + entry5_parity_q when "000101", + entry6_parity_q when "000110", + entry7_parity_q when "000111", + entry8_parity_q when "001000", + entry9_parity_q when "001001", + entry10_parity_q when "001010", + entry11_parity_q when "001011", + entry12_parity_q when "001100", + entry13_parity_q when "001101", + entry14_parity_q when "001110", + entry15_parity_q when "001111", + entry16_parity_q when "010000", + entry17_parity_q when "010001", + entry18_parity_q when "010010", + entry19_parity_q when "010011", + entry20_parity_q when "010100", + entry21_parity_q when "010101", + entry22_parity_q when "010110", + entry23_parity_q when "010111", + entry24_parity_q when "011000", + entry25_parity_q when "011001", + entry26_parity_q when "011010", + entry27_parity_q when "011011", + entry28_parity_q when "011100", + entry29_parity_q when "011101", + entry30_parity_q when "011110", + entry31_parity_q when "011111", + cam_cmp_parity_q when others; +array_cmp_data_np1(0 to 50) <= array_cmp_data_bram(2 to 31) & array_cmp_data_bram(34 to 39) & array_cmp_data_bram(41 to 55); +array_cmp_data_np1(51 to 60) <= cam_cmp_parity_q; +array_cmp_data_np1(61 to 67) <= array_cmp_data_bramp(66 to 72); +array_cmp_data <= array_cmp_data_np1; +-- CAM read parity out mux +with rd_cam_data_muxsel select + rd_array_data_d(51 to 60) <= entry0_parity_q when "000000", + entry1_parity_q when "000001", + entry2_parity_q when "000010", + entry3_parity_q when "000011", + entry4_parity_q when "000100", + entry5_parity_q when "000101", + entry6_parity_q when "000110", + entry7_parity_q when "000111", + entry8_parity_q when "001000", + entry9_parity_q when "001001", + entry10_parity_q when "001010", + entry11_parity_q when "001011", + entry12_parity_q when "001100", + entry13_parity_q when "001101", + entry14_parity_q when "001110", + entry15_parity_q when "001111", + entry16_parity_q when "010000", + entry17_parity_q when "010001", + entry18_parity_q when "010010", + entry19_parity_q when "010011", + entry20_parity_q when "010100", + entry21_parity_q when "010101", + entry22_parity_q when "010110", + entry23_parity_q when "010111", + entry24_parity_q when "011000", + entry25_parity_q when "011001", + entry26_parity_q when "011010", + entry27_parity_q when "011011", + entry28_parity_q when "011100", + entry29_parity_q when "011101", + entry30_parity_q when "011110", + entry31_parity_q when "011111", + rd_array_data_q(51 to 60) when others; +rpn_np2_d(22 to 33) <= ( comp_addr_np1_q(22 to 33) and (22 to 33 => bypass_mux_enab_np1 ) ) or + ( array_cmp_data_np1(0 to 11) and (0 to 11 => not(bypass_mux_enab_np1)) ); +rpn_np2_d(34 to 39) <= ( comp_addr_np1_q(34 to 39) and (34 to 39 => (not(cam_cmp_data_np1(75)) or bypass_mux_enab_np1)) ) or + ( array_cmp_data_np1(12 to 17) and (12 to 17 => (cam_cmp_data_np1(75) and not bypass_mux_enab_np1)) ); +rpn_np2_d(40 to 43) <= ( comp_addr_np1_q(40 to 43) and (40 to 43 => (not(cam_cmp_data_np1(76)) or bypass_mux_enab_np1)) ) or + ( array_cmp_data_np1(18 to 21) and (18 to 21 => (cam_cmp_data_np1(76) and not bypass_mux_enab_np1)) ); +rpn_np2_d(44 to 47) <= ( comp_addr_np1_q(44 to 47) and (44 to 47 => (not(cam_cmp_data_np1(77)) or bypass_mux_enab_np1)) ) or + ( array_cmp_data_np1(22 to 25) and (22 to 25 => (cam_cmp_data_np1(77) and not bypass_mux_enab_np1)) ); +rpn_np2_d(48 to 51) <= ( comp_addr_np1_q(48 to 51) and (48 to 51 => (not(cam_cmp_data_np1(78)) or bypass_mux_enab_np1)) ) or + ( array_cmp_data_np1(26 to 29) and (26 to 29 => (cam_cmp_data_np1(78) and not bypass_mux_enab_np1)) ); +attr_np2_d(0 to 20) <= ( bypass_attr_np1(0 to 20) and (0 to 20 => bypass_mux_enab_np1) ) or + ( array_cmp_data_np1(30 to 50) and (30 to 50 => not bypass_mux_enab_np1) ); +rpn_np2(22 to 51) <= rpn_np2_q(22 to 51); +attr_np2(0 to 20) <= attr_np2_q(0 to 20); +----------------------------------------------------------------------- +-- matchline component instantiations +----------------------------------------------------------------------- +matchline_comb0 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry0_size_q, + entry_cmpmask => entry0_cmpmask_q(0 to 3), + entry_xbit => entry0_xbit_q, + entry_xbitmask => entry0_cmpmask_q(4 to 7), + entry_epn => entry0_epn_q, + comp_class => comp_class, + entry_class => entry0_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry0_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry0_hv_q, + entry_ds => entry0_ds_q, + state_enable => state_enable, + entry_thdid => entry0_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry0_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry0_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(0) + ); +matchline_comb1 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry1_size_q, + entry_cmpmask => entry1_cmpmask_q(0 to 3), + entry_xbit => entry1_xbit_q, + entry_xbitmask => entry1_cmpmask_q(4 to 7), + entry_epn => entry1_epn_q, + comp_class => comp_class, + entry_class => entry1_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry1_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry1_hv_q, + entry_ds => entry1_ds_q, + state_enable => state_enable, + entry_thdid => entry1_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry1_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry1_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(1) + ); +matchline_comb2 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry2_size_q, + entry_cmpmask => entry2_cmpmask_q(0 to 3), + entry_xbit => entry2_xbit_q, + entry_xbitmask => entry2_cmpmask_q(4 to 7), + entry_epn => entry2_epn_q, + comp_class => comp_class, + entry_class => entry2_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry2_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry2_hv_q, + entry_ds => entry2_ds_q, + state_enable => state_enable, + entry_thdid => entry2_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry2_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry2_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(2) + ); +matchline_comb3 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry3_size_q, + entry_cmpmask => entry3_cmpmask_q(0 to 3), + entry_xbit => entry3_xbit_q, + entry_xbitmask => entry3_cmpmask_q(4 to 7), + entry_epn => entry3_epn_q, + comp_class => comp_class, + entry_class => entry3_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry3_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry3_hv_q, + entry_ds => entry3_ds_q, + state_enable => state_enable, + entry_thdid => entry3_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry3_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry3_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(3) + ); +matchline_comb4 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry4_size_q, + entry_cmpmask => entry4_cmpmask_q(0 to 3), + entry_xbit => entry4_xbit_q, + entry_xbitmask => entry4_cmpmask_q(4 to 7), + entry_epn => entry4_epn_q, + comp_class => comp_class, + entry_class => entry4_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry4_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry4_hv_q, + entry_ds => entry4_ds_q, + state_enable => state_enable, + entry_thdid => entry4_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry4_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry4_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(4) + ); +matchline_comb5 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry5_size_q, + entry_cmpmask => entry5_cmpmask_q(0 to 3), + entry_xbit => entry5_xbit_q, + entry_xbitmask => entry5_cmpmask_q(4 to 7), + entry_epn => entry5_epn_q, + comp_class => comp_class, + entry_class => entry5_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry5_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry5_hv_q, + entry_ds => entry5_ds_q, + state_enable => state_enable, + entry_thdid => entry5_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry5_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry5_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(5) + ); +matchline_comb6 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry6_size_q, + entry_cmpmask => entry6_cmpmask_q(0 to 3), + entry_xbit => entry6_xbit_q, + entry_xbitmask => entry6_cmpmask_q(4 to 7), + entry_epn => entry6_epn_q, + comp_class => comp_class, + entry_class => entry6_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry6_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry6_hv_q, + entry_ds => entry6_ds_q, + state_enable => state_enable, + entry_thdid => entry6_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry6_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry6_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(6) + ); +matchline_comb7 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry7_size_q, + entry_cmpmask => entry7_cmpmask_q(0 to 3), + entry_xbit => entry7_xbit_q, + entry_xbitmask => entry7_cmpmask_q(4 to 7), + entry_epn => entry7_epn_q, + comp_class => comp_class, + entry_class => entry7_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry7_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry7_hv_q, + entry_ds => entry7_ds_q, + state_enable => state_enable, + entry_thdid => entry7_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry7_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry7_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(7) + ); +matchline_comb8 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry8_size_q, + entry_cmpmask => entry8_cmpmask_q(0 to 3), + entry_xbit => entry8_xbit_q, + entry_xbitmask => entry8_cmpmask_q(4 to 7), + entry_epn => entry8_epn_q, + comp_class => comp_class, + entry_class => entry8_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry8_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry8_hv_q, + entry_ds => entry8_ds_q, + state_enable => state_enable, + entry_thdid => entry8_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry8_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry8_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(8) + ); +matchline_comb9 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry9_size_q, + entry_cmpmask => entry9_cmpmask_q(0 to 3), + entry_xbit => entry9_xbit_q, + entry_xbitmask => entry9_cmpmask_q(4 to 7), + entry_epn => entry9_epn_q, + comp_class => comp_class, + entry_class => entry9_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry9_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry9_hv_q, + entry_ds => entry9_ds_q, + state_enable => state_enable, + entry_thdid => entry9_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry9_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry9_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(9) + ); +matchline_comb10 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry10_size_q, + entry_cmpmask => entry10_cmpmask_q(0 to 3), + entry_xbit => entry10_xbit_q, + entry_xbitmask => entry10_cmpmask_q(4 to 7), + entry_epn => entry10_epn_q, + comp_class => comp_class, + entry_class => entry10_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry10_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry10_hv_q, + entry_ds => entry10_ds_q, + state_enable => state_enable, + entry_thdid => entry10_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry10_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry10_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(10) + ); +matchline_comb11 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry11_size_q, + entry_cmpmask => entry11_cmpmask_q(0 to 3), + entry_xbit => entry11_xbit_q, + entry_xbitmask => entry11_cmpmask_q(4 to 7), + entry_epn => entry11_epn_q, + comp_class => comp_class, + entry_class => entry11_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry11_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry11_hv_q, + entry_ds => entry11_ds_q, + state_enable => state_enable, + entry_thdid => entry11_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry11_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry11_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(11) + ); +matchline_comb12 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry12_size_q, + entry_cmpmask => entry12_cmpmask_q(0 to 3), + entry_xbit => entry12_xbit_q, + entry_xbitmask => entry12_cmpmask_q(4 to 7), + entry_epn => entry12_epn_q, + comp_class => comp_class, + entry_class => entry12_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry12_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry12_hv_q, + entry_ds => entry12_ds_q, + state_enable => state_enable, + entry_thdid => entry12_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry12_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry12_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(12) + ); +matchline_comb13 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry13_size_q, + entry_cmpmask => entry13_cmpmask_q(0 to 3), + entry_xbit => entry13_xbit_q, + entry_xbitmask => entry13_cmpmask_q(4 to 7), + entry_epn => entry13_epn_q, + comp_class => comp_class, + entry_class => entry13_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry13_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry13_hv_q, + entry_ds => entry13_ds_q, + state_enable => state_enable, + entry_thdid => entry13_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry13_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry13_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(13) + ); +matchline_comb14 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry14_size_q, + entry_cmpmask => entry14_cmpmask_q(0 to 3), + entry_xbit => entry14_xbit_q, + entry_xbitmask => entry14_cmpmask_q(4 to 7), + entry_epn => entry14_epn_q, + comp_class => comp_class, + entry_class => entry14_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry14_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry14_hv_q, + entry_ds => entry14_ds_q, + state_enable => state_enable, + entry_thdid => entry14_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry14_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry14_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(14) + ); +matchline_comb15 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry15_size_q, + entry_cmpmask => entry15_cmpmask_q(0 to 3), + entry_xbit => entry15_xbit_q, + entry_xbitmask => entry15_cmpmask_q(4 to 7), + entry_epn => entry15_epn_q, + comp_class => comp_class, + entry_class => entry15_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry15_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry15_hv_q, + entry_ds => entry15_ds_q, + state_enable => state_enable, + entry_thdid => entry15_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry15_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry15_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(15) + ); +matchline_comb16 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry16_size_q, + entry_cmpmask => entry16_cmpmask_q(0 to 3), + entry_xbit => entry16_xbit_q, + entry_xbitmask => entry16_cmpmask_q(4 to 7), + entry_epn => entry16_epn_q, + comp_class => comp_class, + entry_class => entry16_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry16_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry16_hv_q, + entry_ds => entry16_ds_q, + state_enable => state_enable, + entry_thdid => entry16_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry16_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry16_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(16) + ); +matchline_comb17 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry17_size_q, + entry_cmpmask => entry17_cmpmask_q(0 to 3), + entry_xbit => entry17_xbit_q, + entry_xbitmask => entry17_cmpmask_q(4 to 7), + entry_epn => entry17_epn_q, + comp_class => comp_class, + entry_class => entry17_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry17_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry17_hv_q, + entry_ds => entry17_ds_q, + state_enable => state_enable, + entry_thdid => entry17_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry17_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry17_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(17) + ); +matchline_comb18 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry18_size_q, + entry_cmpmask => entry18_cmpmask_q(0 to 3), + entry_xbit => entry18_xbit_q, + entry_xbitmask => entry18_cmpmask_q(4 to 7), + entry_epn => entry18_epn_q, + comp_class => comp_class, + entry_class => entry18_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry18_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry18_hv_q, + entry_ds => entry18_ds_q, + state_enable => state_enable, + entry_thdid => entry18_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry18_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry18_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(18) + ); +matchline_comb19 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry19_size_q, + entry_cmpmask => entry19_cmpmask_q(0 to 3), + entry_xbit => entry19_xbit_q, + entry_xbitmask => entry19_cmpmask_q(4 to 7), + entry_epn => entry19_epn_q, + comp_class => comp_class, + entry_class => entry19_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry19_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry19_hv_q, + entry_ds => entry19_ds_q, + state_enable => state_enable, + entry_thdid => entry19_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry19_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry19_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(19) + ); +matchline_comb20 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry20_size_q, + entry_cmpmask => entry20_cmpmask_q(0 to 3), + entry_xbit => entry20_xbit_q, + entry_xbitmask => entry20_cmpmask_q(4 to 7), + entry_epn => entry20_epn_q, + comp_class => comp_class, + entry_class => entry20_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry20_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry20_hv_q, + entry_ds => entry20_ds_q, + state_enable => state_enable, + entry_thdid => entry20_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry20_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry20_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(20) + ); +matchline_comb21 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry21_size_q, + entry_cmpmask => entry21_cmpmask_q(0 to 3), + entry_xbit => entry21_xbit_q, + entry_xbitmask => entry21_cmpmask_q(4 to 7), + entry_epn => entry21_epn_q, + comp_class => comp_class, + entry_class => entry21_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry21_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry21_hv_q, + entry_ds => entry21_ds_q, + state_enable => state_enable, + entry_thdid => entry21_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry21_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry21_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(21) + ); +matchline_comb22 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry22_size_q, + entry_cmpmask => entry22_cmpmask_q(0 to 3), + entry_xbit => entry22_xbit_q, + entry_xbitmask => entry22_cmpmask_q(4 to 7), + entry_epn => entry22_epn_q, + comp_class => comp_class, + entry_class => entry22_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry22_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry22_hv_q, + entry_ds => entry22_ds_q, + state_enable => state_enable, + entry_thdid => entry22_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry22_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry22_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(22) + ); +matchline_comb23 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry23_size_q, + entry_cmpmask => entry23_cmpmask_q(0 to 3), + entry_xbit => entry23_xbit_q, + entry_xbitmask => entry23_cmpmask_q(4 to 7), + entry_epn => entry23_epn_q, + comp_class => comp_class, + entry_class => entry23_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry23_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry23_hv_q, + entry_ds => entry23_ds_q, + state_enable => state_enable, + entry_thdid => entry23_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry23_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry23_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(23) + ); +matchline_comb24 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry24_size_q, + entry_cmpmask => entry24_cmpmask_q(0 to 3), + entry_xbit => entry24_xbit_q, + entry_xbitmask => entry24_cmpmask_q(4 to 7), + entry_epn => entry24_epn_q, + comp_class => comp_class, + entry_class => entry24_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry24_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry24_hv_q, + entry_ds => entry24_ds_q, + state_enable => state_enable, + entry_thdid => entry24_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry24_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry24_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(24) + ); +matchline_comb25 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry25_size_q, + entry_cmpmask => entry25_cmpmask_q(0 to 3), + entry_xbit => entry25_xbit_q, + entry_xbitmask => entry25_cmpmask_q(4 to 7), + entry_epn => entry25_epn_q, + comp_class => comp_class, + entry_class => entry25_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry25_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry25_hv_q, + entry_ds => entry25_ds_q, + state_enable => state_enable, + entry_thdid => entry25_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry25_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry25_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(25) + ); +matchline_comb26 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry26_size_q, + entry_cmpmask => entry26_cmpmask_q(0 to 3), + entry_xbit => entry26_xbit_q, + entry_xbitmask => entry26_cmpmask_q(4 to 7), + entry_epn => entry26_epn_q, + comp_class => comp_class, + entry_class => entry26_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry26_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry26_hv_q, + entry_ds => entry26_ds_q, + state_enable => state_enable, + entry_thdid => entry26_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry26_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry26_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(26) + ); +matchline_comb27 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry27_size_q, + entry_cmpmask => entry27_cmpmask_q(0 to 3), + entry_xbit => entry27_xbit_q, + entry_xbitmask => entry27_cmpmask_q(4 to 7), + entry_epn => entry27_epn_q, + comp_class => comp_class, + entry_class => entry27_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry27_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry27_hv_q, + entry_ds => entry27_ds_q, + state_enable => state_enable, + entry_thdid => entry27_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry27_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry27_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(27) + ); +matchline_comb28 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry28_size_q, + entry_cmpmask => entry28_cmpmask_q(0 to 3), + entry_xbit => entry28_xbit_q, + entry_xbitmask => entry28_cmpmask_q(4 to 7), + entry_epn => entry28_epn_q, + comp_class => comp_class, + entry_class => entry28_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry28_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry28_hv_q, + entry_ds => entry28_ds_q, + state_enable => state_enable, + entry_thdid => entry28_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry28_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry28_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(28) + ); +matchline_comb29 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry29_size_q, + entry_cmpmask => entry29_cmpmask_q(0 to 3), + entry_xbit => entry29_xbit_q, + entry_xbitmask => entry29_cmpmask_q(4 to 7), + entry_epn => entry29_epn_q, + comp_class => comp_class, + entry_class => entry29_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry29_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry29_hv_q, + entry_ds => entry29_ds_q, + state_enable => state_enable, + entry_thdid => entry29_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry29_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry29_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(29) + ); +matchline_comb30 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry30_size_q, + entry_cmpmask => entry30_cmpmask_q(0 to 3), + entry_xbit => entry30_xbit_q, + entry_xbitmask => entry30_cmpmask_q(4 to 7), + entry_epn => entry30_epn_q, + comp_class => comp_class, + entry_class => entry30_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry30_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry30_hv_q, + entry_ds => entry30_ds_q, + state_enable => state_enable, + entry_thdid => entry30_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry30_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry30_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(30) + ); +matchline_comb31 : tri_cam_32x143_1r1w1c_matchline + generic map (have_xbit => 1, + num_pgsizes => 5, + have_cmpmask => 1, + cmpmask_width => 4) + port map ( + addr_in => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + entry_size => entry31_size_q, + entry_cmpmask => entry31_cmpmask_q(0 to 3), + entry_xbit => entry31_xbit_q, + entry_xbitmask => entry31_cmpmask_q(4 to 7), + entry_epn => entry31_epn_q, + comp_class => comp_class, + entry_class => entry31_class_q, + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => entry31_extclass_q, + extclass_enable => extclass_enable, + comp_state => comp_state, + entry_hv => entry31_hv_q, + entry_ds => entry31_ds_q, + state_enable => state_enable, + entry_thdid => entry31_thdid_q, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + entry_pid => entry31_pid_q, + comp_pid => comp_pid, + pid_enable => pid_enable, + entry_v => entry31_v_q, + comp_invalidate => comp_invalidate, + + match => match_vec(31) + ); +----------------------------------------------------------------------- +-- BRAM signal assignments +----------------------------------------------------------------------- +bram0_wea <= wr_array_val(0) and gate_fq; +bram1_wea <= wr_array_val(1) and gate_fq; +bram2_wea <= wr_array_val(1) and gate_fq; +bram0_addra(9-num_entry_log2 to 8) <= rw_entry(0 to num_entry_log2-1); +bram1_addra(11-num_entry_log2 to 10) <= rw_entry(0 to num_entry_log2-1); +bram2_addra(10-num_entry_log2 to 9) <= rw_entry(0 to num_entry_log2-1); +bram0_addrb(9-num_entry_log2 to 8) <= cam_hit_entry_q; +bram1_addrb(11-num_entry_log2 to 10) <= cam_hit_entry_q; +bram2_addrb(10-num_entry_log2 to 9) <= cam_hit_entry_q; +-- Unused Address Bits +bram0_addra(0 to 8-num_entry_log2) <= (others => '0'); +bram0_addrb(0 to 8-num_entry_log2) <= (others => '0'); +bram1_addra(0 to 10-num_entry_log2) <= (others => '0'); +bram1_addrb(0 to 10-num_entry_log2) <= (others => '0'); +bram2_addra(0 to 9-num_entry_log2) <= (others => '0'); +bram2_addrb(0 to 9-num_entry_log2) <= (others => '0'); +-- This ram houses the RPN(20:51) bits, wr_array_data_bram(0:31) +-- uses wr_array_val(0), parity is wr_array_data_bram(66:69) +bram0 : ramb16_s36_s36 + +-- pragma translate_off +generic map( + +-- all, none, warning_only, generate_x_only +sim_collision_check => "none") + +-- pragma translate_on +port map( + clka => clk2x, + clkb => clk2x, + ssra => sreset_q, + ssrb => sreset_q, + addra => std_logic_vector(bram0_addra), + addrb => std_logic_vector(bram0_addrb), + dia => std_logic_vector(wr_array_data_bram(0 to 31)), + dib => (others => '0'), + doa => rd_array_data_d_std(0 to 31), + dob => array_cmp_data_bram_std(0 to 31), + dopa => rd_array_data_d_std(66 to 69), + dopb => array_cmp_data_bramp_std(66 to 69), + dipa => std_logic_vector(wr_array_data_bram(66 to 69)), + dipb => (others => '0'), + ena => '1', + enb => '1', + wea => bram0_wea, + web => '0' + ); +-- This ram houses the RPN(18:19),R,C,4xResv bits, wr_array_data_bram(32:39) +-- uses wr_array_val(1), parity is wr_array_data_bram(70) +bram1 : ramb16_s9_s9 + +-- pragma translate_off +generic map( + +-- all, none, warning_only, generate_x_only +sim_collision_check => "none") + +-- pragma translate_on +port map( + clka => clk2x, + clkb => clk2x, + ssra => sreset_q, + ssrb => sreset_q, + addra => std_logic_vector(bram1_addra), + addrb => std_logic_vector(bram1_addrb), + dia => std_logic_vector(wr_array_data_bram(32 to 39)), + dib => (others => '0'), + doa => rd_array_data_d_std(32 to 39), + dob => array_cmp_data_bram_std(32 to 39), + dopa => rd_array_data_d_std(70 to 70), + dopb => array_cmp_data_bramp_std(70 to 70), + dipa => std_logic_vector(wr_array_data_bram(70 to 70)), + dipb => (others => '0'), + ena => '1', + enb => '1', + wea => bram1_wea, + web => '0' + ); +-- This ram houses the 1xResv,U0-U3,WIMGE,UX,UW,UR,SX,SW,SR bits, wr_array_data_bram(40:55) +-- uses wr_array_val(2), parity is wr_array_data_bram(71:72) +bram2 : ramb16_s18_s18 + +-- pragma translate_off +generic map( + +-- all, none, warning_only, generate_x_only +sim_collision_check => "none") + +-- pragma translate_on +port map( + clka => clk2x, + clkb => clk2x, + ssra => sreset_q, + ssrb => sreset_q, + addra => std_logic_vector(bram2_addra), + addrb => std_logic_vector(bram2_addrb), + dia => std_logic_vector(wr_array_data_bram(40 to 55)), + dib => (others => '0'), + doa => rd_array_data_d_std(40 to 55), + dob => array_cmp_data_bram_std(40 to 55), + dopa => rd_array_data_d_std(71 to 72), + dopb => array_cmp_data_bramp_std(71 to 72), + dipa => std_logic_vector(wr_array_data_bram(71 to 72)), + dipb => (others => '0'), + ena => '1', + enb => '1', + wea => bram2_wea, + web => '0' + ); +-- array write data swizzle -> convert 68-bit data to 73-bit bram data +-- 32x143 version, 42b RA +-- wr_array_data +-- 0:29 - RPN +-- 30:31 - R,C +-- 32:35 - ResvAttr +-- 36:39 - U0-U3 +-- 40:44 - WIMGE +-- 45:47 - UX,UW,UR +-- 48:50 - SX,SW,SR +-- 51:60 - CAM parity +-- 61:67 - Array parity +-- RTX layout in A2_AvpEratHelper.C +-- ram0(0:31): 00 & RPN(0:29) +-- ram1(0:7) : 00 & R,C,ResvAttr(0:3) +-- ram2(0:15): '0' & U(0:3),WIMGE,UX,UW,UR,SX,SW,SR +wr_array_data_bram(0 to 72) <= "00" & wr_array_data(0 to 29) & + "00" & wr_array_data(30 to 35) & + '0' & wr_array_data(36 to 50) & + wr_array_data(51 to 60) & wr_array_data(61 to 67); +rd_array_data_d_std(56 to 65) <= (others => '0'); +rd_array_data_d(0 to 29) <= std_ulogic_vector(rd_array_data_d_std(2 to 31)); +rd_array_data_d(30 to 35) <= std_ulogic_vector(rd_array_data_d_std(34 to 39)); +rd_array_data_d(36 to 50) <= std_ulogic_vector(rd_array_data_d_std(41 to 55)); +rd_array_data_d(61 to 67) <= std_ulogic_vector(rd_array_data_d_std(66 to 72)); +array_cmp_data_bram <= std_ulogic_vector(array_cmp_data_bram_std); +array_cmp_data_bramp <= std_ulogic_vector(array_cmp_data_bramp_std); +----------------------------------------------------------------------- +-- entity output assignments +----------------------------------------------------------------------- +rd_array_data <= rd_array_data_q; +cam_cmp_data <= cam_cmp_data_q; +rd_cam_data <= rd_cam_data_q; +entry_valid(0) <= entry0_v_q; +entry_valid(1) <= entry1_v_q; +entry_valid(2) <= entry2_v_q; +entry_valid(3) <= entry3_v_q; +entry_valid(4) <= entry4_v_q; +entry_valid(5) <= entry5_v_q; +entry_valid(6) <= entry6_v_q; +entry_valid(7) <= entry7_v_q; +entry_valid(8) <= entry8_v_q; +entry_valid(9) <= entry9_v_q; +entry_valid(10) <= entry10_v_q; +entry_valid(11) <= entry11_v_q; +entry_valid(12) <= entry12_v_q; +entry_valid(13) <= entry13_v_q; +entry_valid(14) <= entry14_v_q; +entry_valid(15) <= entry15_v_q; +entry_valid(16) <= entry16_v_q; +entry_valid(17) <= entry17_v_q; +entry_valid(18) <= entry18_v_q; +entry_valid(19) <= entry19_v_q; +entry_valid(20) <= entry20_v_q; +entry_valid(21) <= entry21_v_q; +entry_valid(22) <= entry22_v_q; +entry_valid(23) <= entry23_v_q; +entry_valid(24) <= entry24_v_q; +entry_valid(25) <= entry25_v_q; +entry_valid(26) <= entry26_v_q; +entry_valid(27) <= entry27_v_q; +entry_valid(28) <= entry28_v_q; +entry_valid(29) <= entry29_v_q; +entry_valid(30) <= entry30_v_q; +entry_valid(31) <= entry31_v_q; +entry_match <= entry_match_q; +cam_hit_entry <= cam_hit_entry_q; +cam_hit <= cam_hit_q; +func_scan_out <= func_scan_in; +regfile_scan_out <= regfile_scan_in; +time_scan_out <= time_scan_in; +end generate; +end tri_cam_32x143_1r1w1c; diff --git a/rel/src/vhdl/tri/tri_cam_32x143_1r1w1c_matchline.vhdl b/rel/src/vhdl/tri/tri_cam_32x143_1r1w1c_matchline.vhdl new file mode 100644 index 0000000..bed00f8 --- /dev/null +++ b/rel/src/vhdl/tri/tri_cam_32x143_1r1w1c_matchline.vhdl @@ -0,0 +1,459 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +--******************************************************************** +--* +--* TITLE: D-ERAT CAM Match Line Logic for Functional Model +--* +--* NAME: tri_cam_32x143_1r1w1c_matchline +--* + +library ieee; +use ieee.std_logic_1164.all ; +library ibm; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; + +------------------------------------------------------------------------ +-- Entity +------------------------------------------------------------------------ + +entity tri_cam_32x143_1r1w1c_matchline is + generic (have_xbit : integer := 1; + num_pgsizes : integer := 5; + have_cmpmask : integer := 1; + cmpmask_width : integer := 4); + +port( -- @{default:nclk}@ + addr_in : in std_ulogic_vector(0 to 51); + addr_enable : in std_ulogic_vector(0 to 1); + comp_pgsize : in std_ulogic_vector(0 to 2); + pgsize_enable : in std_ulogic; + entry_size : in std_ulogic_vector(0 to 2); + entry_cmpmask : in std_ulogic_vector(0 to cmpmask_width-1); + entry_xbit : in std_ulogic; + entry_xbitmask : in std_ulogic_vector(0 to cmpmask_width-1); + entry_epn : in std_ulogic_vector(0 to 51); + comp_class : in std_ulogic_vector(0 to 1); + entry_class : in std_ulogic_vector(0 to 1); + class_enable : in std_ulogic_vector(0 to 2); + comp_extclass : in std_ulogic_vector(0 to 1); + entry_extclass : in std_ulogic_vector(0 to 1); + extclass_enable : in std_ulogic_vector(0 to 1); + comp_state : in std_ulogic_vector(0 to 1); + entry_hv : in std_ulogic; + entry_ds : in std_ulogic; + state_enable : in std_ulogic_vector(0 to 1); + entry_thdid : in std_ulogic_vector(0 to 3); + comp_thdid : in std_ulogic_vector(0 to 3); + thdid_enable : in std_ulogic_vector(0 to 1); + entry_pid : in std_ulogic_vector(0 to 7); + comp_pid : in std_ulogic_vector(0 to 7); + pid_enable : in std_ulogic; + entry_v : in std_ulogic; + comp_invalidate : in std_ulogic; + + match : out std_ulogic +); + + -- synopsys translate_off + -- synopsys translate_on + +end tri_cam_32x143_1r1w1c_matchline; + +architecture tri_cam_32x143_1r1w1c_matchline of tri_cam_32x143_1r1w1c_matchline is + + +------------------------------------------------------------------------ +-- Signals +------------------------------------------------------------------------ + + signal entry_epn_b : std_ulogic_vector(34 to 51); + signal function_50_51 : std_ulogic; + signal function_48_51 : std_ulogic; + signal function_46_51 : std_ulogic; + signal function_44_51 : std_ulogic; + signal function_40_51 : std_ulogic; + signal function_36_51 : std_ulogic; + signal function_34_51 : std_ulogic; + signal pgsize_eq_16K : std_ulogic; + signal pgsize_eq_64K : std_ulogic; + signal pgsize_eq_256K : std_ulogic; + signal pgsize_eq_1M : std_ulogic; + signal pgsize_eq_16M : std_ulogic; + signal pgsize_eq_256M : std_ulogic; + signal pgsize_eq_1G : std_ulogic; + signal pgsize_gte_16K : std_ulogic; + signal pgsize_gte_64K : std_ulogic; + signal pgsize_gte_256K : std_ulogic; + signal pgsize_gte_1M : std_ulogic; + signal pgsize_gte_16M : std_ulogic; + signal pgsize_gte_256M : std_ulogic; + signal pgsize_gte_1G : std_ulogic; + signal comp_or_34_35 : std_ulogic; + signal comp_or_34_39 : std_ulogic; + signal comp_or_36_39 : std_ulogic; + signal comp_or_40_43 : std_ulogic; + signal comp_or_44_45 : std_ulogic; + signal comp_or_44_47 : std_ulogic; + signal comp_or_46_47 : std_ulogic; + signal comp_or_48_49 : std_ulogic; + signal comp_or_48_51 : std_ulogic; + signal comp_or_50_51 : std_ulogic; + signal match_line : std_ulogic_vector(0 to 72); + signal pgsize_match : std_ulogic; + signal addr_match : std_ulogic; + signal class_match : std_ulogic; + signal extclass_match : std_ulogic; + signal state_match : std_ulogic; + signal thdid_match : std_ulogic; + signal pid_match : std_ulogic; + +begin + + match_line(0 to 72) <= not((entry_epn(0 to 51) & entry_size(0 to 2) & entry_class(0 to 1) & entry_extclass(0 to 1) & entry_hv & entry_ds & entry_pid(0 to 7) & entry_thdid(0 to 3)) xor + (addr_in(0 to 51) & comp_pgsize(0 to 2) & comp_class(0 to 1) & comp_extclass(0 to 1) & comp_state(0 to 1) & comp_pid(0 to 7) & comp_thdid(0 to 3)) + ); + +numpgsz8 : if num_pgsizes = 8 generate + + entry_epn_b(34 to 51) <= not(entry_epn(34 to 51)); + + +gen_nocmpmask80 : if have_cmpmask = 0 generate + pgsize_eq_1G <= ( entry_size(0) and entry_size(1) and entry_size(2) ); + pgsize_eq_256M <= ( entry_size(0) and entry_size(1) and not(entry_size(2))); + pgsize_eq_16M <= ( entry_size(0) and not(entry_size(1)) and entry_size(2) ); + pgsize_eq_1M <= ( entry_size(0) and not(entry_size(1)) and not(entry_size(2))); + pgsize_eq_256K <= (not(entry_size(0)) and entry_size(1) and entry_size(2) ); + pgsize_eq_64K <= (not(entry_size(0)) and entry_size(1) and not(entry_size(2))); + pgsize_eq_16K <= (not(entry_size(0)) and not(entry_size(1)) and entry_size(2) ); + + pgsize_gte_1G <= ( entry_size(0) and entry_size(1) and entry_size(2) ); + pgsize_gte_256M <= ( entry_size(0) and entry_size(1) and not(entry_size(2))) or + pgsize_gte_1G; + pgsize_gte_16M <= ( entry_size(0) and not(entry_size(1)) and entry_size(2) ) or + pgsize_gte_256M; + pgsize_gte_1M <= ( entry_size(0) and not(entry_size(1)) and not(entry_size(2))) or + pgsize_gte_16M; + pgsize_gte_256K <= (not(entry_size(0)) and entry_size(1) and entry_size(2) ) or + pgsize_gte_1M; + pgsize_gte_64K <= (not(entry_size(0)) and entry_size(1) and not(entry_size(2))) or + pgsize_gte_256K; + pgsize_gte_16K <= (not(entry_size(0)) and not(entry_size(1)) and entry_size(2) ) or + pgsize_gte_64K; + + +end generate gen_nocmpmask80; + +gen_cmpmask80 : if have_cmpmask = 1 generate +-- size entry_cmpmask: 0123456 +-- 1GB 0000000 +-- 256MB 1000000 +-- 16MB 1100000 +-- 1MB 1110000 +-- 256KB 1111000 +-- 64KB 1111100 +-- 16KB 1111110 +-- 4KB 1111111 + pgsize_gte_1G <= not entry_cmpmask(0); + pgsize_gte_256M <= not entry_cmpmask(1); + pgsize_gte_16M <= not entry_cmpmask(2); + pgsize_gte_1M <= not entry_cmpmask(3); + pgsize_gte_256K <= not entry_cmpmask(4); + pgsize_gte_64K <= not entry_cmpmask(5); + pgsize_gte_16K <= not entry_cmpmask(6); + +-- size entry_xbitmask: 0123456 +-- 1GB 1000000 +-- 256MB 0100000 +-- 16MB 0010000 +-- 1MB 0001000 +-- 256KB 0000100 +-- 64KB 0000010 +-- 16KB 0000001 +-- 4KB 0000000 + pgsize_eq_1G <= entry_xbitmask(0); + pgsize_eq_256M <= entry_xbitmask(1); + pgsize_eq_16M <= entry_xbitmask(2); + pgsize_eq_1M <= entry_xbitmask(3); + pgsize_eq_256K <= entry_xbitmask(4); + pgsize_eq_64K <= entry_xbitmask(5); + pgsize_eq_16K <= entry_xbitmask(6); +end generate gen_cmpmask80; + +gen_noxbit80 : if have_xbit = 0 generate + function_34_51 <= '0'; + function_36_51 <= '0'; + function_40_51 <= '0'; + function_44_51 <= '0'; + function_46_51 <= '0'; + function_48_51 <= '0'; + function_50_51 <= '0'; +end generate gen_noxbit80; + +gen_xbit80 : if have_xbit /= 0 generate + function_34_51 <= not(entry_xbit) or + not(pgsize_eq_1G) or + or_reduce(entry_epn_b(34 to 51) and addr_in(34 to 51)); + function_36_51 <= not(entry_xbit) or + not(pgsize_eq_256M) or + or_reduce(entry_epn_b(36 to 51) and addr_in(36 to 51)); + function_40_51 <= not(entry_xbit) or + not(pgsize_eq_16M) or + or_reduce(entry_epn_b(40 to 51) and addr_in(40 to 51)); + function_44_51 <= not(entry_xbit) or + not(pgsize_eq_1M) or + or_reduce(entry_epn_b(44 to 51) and addr_in(44 to 51)); + function_46_51 <= not(entry_xbit) or + not(pgsize_eq_256K) or + or_reduce(entry_epn_b(46 to 51) and addr_in(46 to 51)); + function_48_51 <= not(entry_xbit) or + not(pgsize_eq_64K) or + or_reduce(entry_epn_b(48 to 51) and addr_in(48 to 51)); + function_50_51 <= not(entry_xbit) or + not(pgsize_eq_16K) or + or_reduce(entry_epn_b(50 to 51) and addr_in(50 to 51)); +end generate gen_xbit80; + + + comp_or_50_51 <= and_reduce(match_line(50 to 51)) or pgsize_gte_16K; + comp_or_48_49 <= and_reduce(match_line(48 to 49)) or pgsize_gte_64K; + comp_or_46_47 <= and_reduce(match_line(46 to 47)) or pgsize_gte_256K; + comp_or_44_45 <= and_reduce(match_line(44 to 45)) or pgsize_gte_1M; + comp_or_40_43 <= and_reduce(match_line(40 to 43)) or pgsize_gte_16M; + comp_or_36_39 <= and_reduce(match_line(36 to 39)) or pgsize_gte_256M; + comp_or_34_35 <= and_reduce(match_line(34 to 35)) or pgsize_gte_1G; + +gen_noxbit81 : if have_xbit = 0 generate + addr_match <= (comp_or_34_35 and -- Ignore functions based on page size + comp_or_36_39 and + comp_or_40_43 and + comp_or_44_45 and + comp_or_46_47 and + comp_or_48_49 and + comp_or_50_51 and + and_reduce(match_line(31 to 33)) and -- Regular compare largest page size + (and_reduce(match_line(0 to 30)) or not(addr_enable(1)))) or -- ignored part of epn + not(addr_enable(0)); -- Include address as part of compare, + -- should never ignore for regular compare/read. + -- Could ignore for compare/invalidate +end generate gen_noxbit81; + +gen_xbit81 : if have_xbit /= 0 generate + addr_match <= (function_50_51 and -- Exclusion functions + function_48_51 and + function_46_51 and + function_44_51 and + function_40_51 and + function_36_51 and + function_34_51 and + comp_or_34_35 and -- Ignore functions based on page size + comp_or_36_39 and + comp_or_40_43 and + comp_or_44_45 and + comp_or_46_47 and + comp_or_48_49 and + comp_or_50_51 and + and_reduce(match_line(31 to 33)) and -- Regular compare largest page size + (and_reduce(match_line(0 to 30)) or not(addr_enable(1)))) or -- ignored part of epn + not(addr_enable(0)); -- Include address as part of compare, + -- should never ignore for regular compare/read. + -- Could ignore for compare/invalidate +end generate gen_xbit81; + +end generate numpgsz8; -- numpgsz8: num_pgsizes = 8 + + +numpgsz5 : if num_pgsizes = 5 generate + + -- tie off unused signals + function_50_51 <= '0'; + function_46_51 <= '0'; + function_36_51 <= '0'; + pgsize_eq_16K <= '0'; + pgsize_eq_256K <= '0'; + pgsize_eq_256M <= '0'; + pgsize_gte_16K <= '0'; + pgsize_gte_256K <= '0'; + pgsize_gte_256M <= '0'; + comp_or_34_35 <= '0'; + comp_or_36_39 <= '0'; + comp_or_44_45 <= '0'; + comp_or_46_47 <= '0'; + comp_or_48_49 <= '0'; + comp_or_50_51 <= '0'; + + entry_epn_b(34 to 51) <= not(entry_epn(34 to 51)); + + +gen_nocmpmask50 : if have_cmpmask = 0 generate + -- 110 + pgsize_eq_1G <= ( entry_size(0) and entry_size(1) and not(entry_size(2)) ); + -- 111 + pgsize_eq_16M <= ( entry_size(0) and entry_size(1) and entry_size(2) ); + -- 101 + pgsize_eq_1M <= ( entry_size(0) and not(entry_size(1)) and entry_size(2)); + -- 011 + pgsize_eq_64K <= (not(entry_size(0)) and entry_size(1) and entry_size(2)); + + + pgsize_gte_1G <= ( entry_size(0) and entry_size(1) and not(entry_size(2)) ); + + pgsize_gte_16M <= ( entry_size(0) and entry_size(1) and entry_size(2) ) or + pgsize_gte_1G; + pgsize_gte_1M <= ( entry_size(0) and not(entry_size(1)) and entry_size(2)) or + pgsize_gte_16M; + pgsize_gte_64K <= (not(entry_size(0)) and entry_size(1) and entry_size(2)) or + pgsize_gte_1M; + +end generate gen_nocmpmask50; + +gen_cmpmask50 : if have_cmpmask = 1 generate +-- size entry_cmpmask: 0123 +-- 1GB 0000 +-- 16MB 1000 +-- 1MB 1100 +-- 64KB 1110 +-- 4KB 1111 + pgsize_gte_1G <= not entry_cmpmask(0); + pgsize_gte_16M <= not entry_cmpmask(1); + pgsize_gte_1M <= not entry_cmpmask(2); + pgsize_gte_64K <= not entry_cmpmask(3); + +-- size entry_xbitmask: 0123 +-- 1GB 1000 +-- 16MB 0100 +-- 1MB 0010 +-- 64KB 0001 +-- 4KB 0000 + pgsize_eq_1G <= entry_xbitmask(0); + pgsize_eq_16M <= entry_xbitmask(1); + pgsize_eq_1M <= entry_xbitmask(2); + pgsize_eq_64K <= entry_xbitmask(3); +end generate gen_cmpmask50; + +gen_noxbit50 : if have_xbit = 0 generate + function_34_51 <= '0'; + function_40_51 <= '0'; + function_44_51 <= '0'; + function_48_51 <= '0'; +end generate gen_noxbit50; + +gen_xbit50 : if have_xbit /= 0 generate + -- 1G + function_34_51 <= not(entry_xbit) or + not(pgsize_eq_1G) or + or_reduce(entry_epn_b(34 to 51) and addr_in(34 to 51)); + -- 16M + function_40_51 <= not(entry_xbit) or + not(pgsize_eq_16M) or + or_reduce(entry_epn_b(40 to 51) and addr_in(40 to 51)); + -- 1M + function_44_51 <= not(entry_xbit) or + not(pgsize_eq_1M) or + or_reduce(entry_epn_b(44 to 51) and addr_in(44 to 51)); + -- 64K + function_48_51 <= not(entry_xbit) or + not(pgsize_eq_64K) or + or_reduce(entry_epn_b(48 to 51) and addr_in(48 to 51)); +end generate gen_xbit50; + + comp_or_48_51 <= and_reduce(match_line(48 to 51)) or pgsize_gte_64K; + comp_or_44_47 <= and_reduce(match_line(44 to 47)) or pgsize_gte_1M; + comp_or_40_43 <= and_reduce(match_line(40 to 43)) or pgsize_gte_16M; + comp_or_34_39 <= and_reduce(match_line(34 to 39)) or pgsize_gte_1G; + +gen_noxbit51 : if have_xbit = 0 generate + addr_match <= (comp_or_34_39 and -- Ignore functions based on page size + comp_or_40_43 and + comp_or_44_47 and + comp_or_48_51 and + and_reduce(match_line(31 to 33)) and -- Regular compare largest page size + (and_reduce(match_line(0 to 30)) or not(addr_enable(1)))) or -- ignored part of epn + not(addr_enable(0)); -- Include address as part of compare, + -- should never ignore for regular compare/read. + -- Could ignore for compare/invalidate +end generate gen_noxbit51; + +gen_xbit51 : if have_xbit /= 0 generate + addr_match <= (function_48_51 and + function_44_51 and + function_40_51 and + function_34_51 and + comp_or_34_39 and -- Ignore functions based on page size + comp_or_40_43 and + comp_or_44_47 and + comp_or_48_51 and + and_reduce(match_line(31 to 33)) and -- Regular compare largest page size + (and_reduce(match_line(0 to 30)) or not(addr_enable(1)))) or -- ignored part of epn + not(addr_enable(0)); -- Include address as part of compare, + -- should never ignore for regular compare/read. + -- Could ignore for compare/invalidate +end generate gen_xbit51; + +end generate numpgsz5; -- numpgsz5: num_pgsizes = 5 + + + pgsize_match <= and_reduce(match_line(52 to 54)) or + not(pgsize_enable); + + class_match <= (match_line(55) or not(class_enable(0))) and + (match_line(56) or not(class_enable(1))) and + (and_reduce(match_line(55 to 56)) or not(class_enable(2)) or + (not(entry_extclass(1)) and not comp_invalidate)); -- pid_nz bit + + extclass_match <= (match_line(57) or not(extclass_enable(0))) and -- iprot bit + (match_line(58) or not(extclass_enable(1))); -- pid_nz bit + + state_match <= (match_line(59) or + not(state_enable(0))) and + (match_line(60) or + not(state_enable(1))); + + thdid_match <= (or_reduce(entry_thdid(0 to 3) and comp_thdid(0 to 3)) or not(thdid_enable(0))) and + (and_reduce(match_line(69 to 72)) or not(thdid_enable(1)) or + (not(entry_extclass(1)) and not comp_invalidate)); -- pid_nz bit + + pid_match <= and_reduce(match_line(61 to 68)) or + -- entry_pid=0 ignores pid match for compares, + -- but not for invalidates. + (not(entry_extclass(1)) and not comp_invalidate) or -- pid_nz bit + not(pid_enable); + + match <= addr_match and -- Address compare + pgsize_match and -- Size compare + class_match and -- Class compare + extclass_match and -- ExtClass compare + state_match and -- State compare + thdid_match and -- ThdID compare + pid_match and -- PID compare + entry_v; -- Valid + + +end tri_cam_32x143_1r1w1c_matchline; diff --git a/rel/src/vhdl/tri/tri_cam_parerr_mac.vhdl b/rel/src/vhdl/tri/tri_cam_parerr_mac.vhdl new file mode 100644 index 0000000..f75ae93 --- /dev/null +++ b/rel/src/vhdl/tri/tri_cam_parerr_mac.vhdl @@ -0,0 +1,186 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +--******************************************************************** +--* TITLE: ERAT CAM Parity Error Macro Tri-Library Model +--* NAME: tri_cam_parerr_mac +library ieee; +use ieee.std_logic_1164.all; +library ibm; +use ibm.std_ulogic_unsigned.all; +use ibm.std_ulogic_function_support.all; +library support; +use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity tri_cam_parerr_mac is + generic (expand_type : integer := 1); + port( + + np1_cam_cmp_data :in std_ulogic_vector(0 to 83); + np1_array_cmp_data :in std_ulogic_vector(0 to 67); + + np2_cam_cmp_data :out std_ulogic_vector(0 to 83); + np2_array_cmp_data :out std_ulogic_vector(0 to 67); + np2_cmp_data_parerr_epn :out std_ulogic; + np2_cmp_data_parerr_rpn :out std_ulogic; + + -- Pervasive + gnd :inout power_logic; + vdd :inout power_logic; + nclk :in clk_logic; + act :in std_ulogic; + lcb_act_dis_dc :in std_ulogic; + lcb_delay_lclkr_dc :in std_ulogic; + lcb_clkoff_dc_b_0 :in std_ulogic; + lcb_mpw1_dc_b :in std_ulogic; + lcb_mpw2_dc_b :in std_ulogic; + lcb_sg_0 :in std_ulogic; + lcb_func_sl_thold_0 :in std_ulogic; + func_scan_in :in std_ulogic; + func_scan_out :out std_ulogic + ); +-- synopsys translate_off +-- synopsys translate_on +end entity tri_cam_parerr_mac; + +architecture tri_cam_parerr_mac of tri_cam_parerr_mac is + +begin + + um: if expand_type = 0 generate + signal np2_cam_cmp_data_q :std_ulogic_vector(0 to np1_cam_cmp_data'length-1); + signal np2_array_cmp_data_q :std_ulogic_vector(0 to np1_array_cmp_data'length-1); + signal np2_cmp_data_calc_par :std_ulogic_vector(50 to 67); + + begin + np1_cam_cmp_data_latch: tri_rlmreg_p + generic map (width => np1_cam_cmp_data'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => act, + scin => (others => '0'), + scout => open, + din => np1_cam_cmp_data, + dout => np2_cam_cmp_data_q); + + np1_array_cmp_data_latch: tri_rlmreg_p + generic map (width => np1_array_cmp_data'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => act, + scin => (others => '0'), + scout => open, + din => np1_array_cmp_data, + dout => np2_array_cmp_data_q); + + -- Parity Calculation + np2_cmp_data_calc_par(50) <= xor_reduce(np2_cam_cmp_data_q(75 to 82)); + np2_cmp_data_calc_par(51) <= xor_reduce(np2_cam_cmp_data_q(0 to 7)); + np2_cmp_data_calc_par(52) <= xor_reduce(np2_cam_cmp_data_q(8 to 15)); + np2_cmp_data_calc_par(53) <= xor_reduce(np2_cam_cmp_data_q(16 to 23)); + np2_cmp_data_calc_par(54) <= xor_reduce(np2_cam_cmp_data_q(24 to 31)); + np2_cmp_data_calc_par(55) <= xor_reduce(np2_cam_cmp_data_q(32 to 39)); + np2_cmp_data_calc_par(56) <= xor_reduce(np2_cam_cmp_data_q(40 to 47)); + np2_cmp_data_calc_par(57) <= xor_reduce(np2_cam_cmp_data_q(48 to 55)); + np2_cmp_data_calc_par(58) <= xor_reduce(np2_cam_cmp_data_q(57 to 62)); + np2_cmp_data_calc_par(59) <= xor_reduce(np2_cam_cmp_data_q(63 to 66)); + np2_cmp_data_calc_par(60) <= xor_reduce(np2_cam_cmp_data_q(67 to 74)); + np2_cmp_data_calc_par(61) <= xor_reduce(np2_array_cmp_data_q(0 to 5)); + np2_cmp_data_calc_par(62) <= xor_reduce(np2_array_cmp_data_q(6 to 13)); + np2_cmp_data_calc_par(63) <= xor_reduce(np2_array_cmp_data_q(14 to 21)); + np2_cmp_data_calc_par(64) <= xor_reduce(np2_array_cmp_data_q(22 to 29)); + np2_cmp_data_calc_par(65) <= xor_reduce(np2_array_cmp_data_q(30 to 37)); + np2_cmp_data_calc_par(66) <= xor_reduce(np2_array_cmp_data_q(38 to 44)); + np2_cmp_data_calc_par(67) <= xor_reduce(np2_array_cmp_data_q(45 to 50)); + + -- Outputs + np2_cmp_data_parerr_epn <= or_reduce(np2_cmp_data_calc_par(50 to 60) xor (np2_cam_cmp_data_q(83) & np2_array_cmp_data_q(51 to 60))); + np2_cmp_data_parerr_rpn <= or_reduce(np2_cmp_data_calc_par(61 to 67) xor np2_array_cmp_data_q(61 to 67)); + np2_cam_cmp_data <= np2_cam_cmp_data_q; + np2_array_cmp_data <= np2_array_cmp_data_q; + end generate um; + + a: if expand_type = 1 generate + signal np2_cam_cmp_data_q :std_ulogic_vector(0 to np1_cam_cmp_data'length-1); + signal np2_array_cmp_data_q :std_ulogic_vector(0 to np1_array_cmp_data'length-1); + signal np2_cmp_data_calc_par :std_ulogic_vector(50 to 67); + signal clk :std_ulogic; + signal sreset_q :std_ulogic; + begin + clk <= not nclk.clk; + rlatch: process (clk) + begin + if(rising_edge(clk)) then + sreset_q <= nclk.sreset; + end if; + end process; + + slatch: process (nclk,sreset_q) + begin + if(rising_edge(nclk.clk)) then + if (sreset_q = '1') then + np2_cam_cmp_data_q <= (others=>'0'); + np2_array_cmp_data_q <= (others=>'0'); + else + np2_cam_cmp_data_q <= np1_cam_cmp_data; + np2_array_cmp_data_q <= np1_array_cmp_data; + end if; + end if; + end process; + + -- Parity Calculation + np2_cmp_data_calc_par(50) <= xor_reduce(np2_cam_cmp_data_q(75 to 82)); + np2_cmp_data_calc_par(51) <= xor_reduce(np2_cam_cmp_data_q(0 to 7)); + np2_cmp_data_calc_par(52) <= xor_reduce(np2_cam_cmp_data_q(8 to 15)); + np2_cmp_data_calc_par(53) <= xor_reduce(np2_cam_cmp_data_q(16 to 23)); + np2_cmp_data_calc_par(54) <= xor_reduce(np2_cam_cmp_data_q(24 to 31)); + np2_cmp_data_calc_par(55) <= xor_reduce(np2_cam_cmp_data_q(32 to 39)); + np2_cmp_data_calc_par(56) <= xor_reduce(np2_cam_cmp_data_q(40 to 47)); + np2_cmp_data_calc_par(57) <= xor_reduce(np2_cam_cmp_data_q(48 to 55)); + np2_cmp_data_calc_par(58) <= xor_reduce(np2_cam_cmp_data_q(57 to 62)); + np2_cmp_data_calc_par(59) <= xor_reduce(np2_cam_cmp_data_q(63 to 66)); + np2_cmp_data_calc_par(60) <= xor_reduce(np2_cam_cmp_data_q(67 to 74)); + np2_cmp_data_calc_par(61) <= xor_reduce(np2_array_cmp_data_q(0 to 5)); + np2_cmp_data_calc_par(62) <= xor_reduce(np2_array_cmp_data_q(6 to 13)); + np2_cmp_data_calc_par(63) <= xor_reduce(np2_array_cmp_data_q(14 to 21)); + np2_cmp_data_calc_par(64) <= xor_reduce(np2_array_cmp_data_q(22 to 29)); + np2_cmp_data_calc_par(65) <= xor_reduce(np2_array_cmp_data_q(30 to 37)); + np2_cmp_data_calc_par(66) <= xor_reduce(np2_array_cmp_data_q(38 to 44)); + np2_cmp_data_calc_par(67) <= xor_reduce(np2_array_cmp_data_q(45 to 50)); + + -- Outputs + np2_cmp_data_parerr_epn <= or_reduce(np2_cmp_data_calc_par(50 to 60) xor (np2_cam_cmp_data_q(83) & np2_array_cmp_data_q(51 to 60))); + np2_cmp_data_parerr_rpn <= or_reduce(np2_cmp_data_calc_par(61 to 67) xor np2_array_cmp_data_q(61 to 67)); + np2_cam_cmp_data <= np2_cam_cmp_data_q; + np2_array_cmp_data <= np2_array_cmp_data_q; + + -- Scan Chains + func_scan_out <= func_scan_in; + end generate a; + +end tri_cam_parerr_mac; diff --git a/rel/src/vhdl/tri/tri_direct_err_rpt.vhdl b/rel/src/vhdl/tri/tri_direct_err_rpt.vhdl new file mode 100644 index 0000000..2958c33 --- /dev/null +++ b/rel/src/vhdl/tri/tri_direct_err_rpt.vhdl @@ -0,0 +1,70 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- *!**************************************************************** +-- *! FILENAME : tri_direct_err_rpt.vhdl +-- *! DESCRIPTION : Error Reporting Component +-- *! +-- *!**************************************************************** + +library ieee; use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library support; use support.power_logic_pkg.all; +library tri; use tri.tri_latches_pkg.all; +-- pragma translate_off +-- pragma translate_on + +entity tri_direct_err_rpt is + + generic ( + width : positive := 1 ; -- use to bundle error reporting checkers of the same exact type + expand_type : integer := 1 ); -- 1 = non-ibm, 2 = ibm (MPG) + port ( + vd : inout power_logic; + gd : inout power_logic; + + err_in : in std_ulogic_vector(0 to width-1); + err_out : out std_ulogic_vector(0 to width-1) + ); + -- synopsys translate_off + + -- synopsys translate_on + +end tri_direct_err_rpt; + +architecture tri_direct_err_rpt of tri_direct_err_rpt is + +begin -- tri_direct_err_rpt + + a: if expand_type /= 2 generate + begin + err_out <= err_in; + end generate a; + +end tri_direct_err_rpt; diff --git a/rel/src/vhdl/tri/tri_err_rpt.vhdl b/rel/src/vhdl/tri/tri_err_rpt.vhdl new file mode 100644 index 0000000..d190544 --- /dev/null +++ b/rel/src/vhdl/tri/tri_err_rpt.vhdl @@ -0,0 +1,143 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- *!**************************************************************** +-- *! FILENAME : tri_err_rpt.vhdl +-- *! DESCRIPTION : Error Reporting Component +-- *! +-- *!**************************************************************** + +library ieee; use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library support; + use support.power_logic_pkg.all; +library tri; use tri.tri_latches_pkg.all; +-- pragma translate_off +-- pragma translate_on + +entity tri_err_rpt is + + generic ( + width : positive := 1; -- number of errors of the same type + mask_reset_value : std_ulogic_vector := "0";-- use to set default/flush value for mask bits + inline : boolean := false; -- make hold latch be inline; err_out is sticky -- default to shadow + share_mask : boolean := false; -- PERMISSION NEEDED for true + -- used for width >1 to reduce area of mask (common error disable) + use_nlats : boolean := false; -- only necessary in standby area to be able to reset to init value + needs_sreset : integer := 1 ; -- for inferred latches + expand_type : integer := 1 ); -- 1 = non-ibm, 2 = ibm (MPG) + + port ( + vd : inout power_logic; + gd : inout power_logic; + err_d1clk : in std_ulogic; -- caution: if lcb uses powersavings, errors must always get reported + err_d2clk : in std_ulogic; + err_lclk : in clk_logic; + -- error scan chain (func or mode) + err_scan_in : in std_ulogic_vector(0 to width-1); + err_scan_out : out std_ulogic_vector(0 to width-1); + -- clock gateable mode clocks + mode_dclk : in std_ulogic; + mode_lclk : in clk_logic; + -- mode scan chain + mode_scan_in : in std_ulogic_vector(0 to width-1); + mode_scan_out : out std_ulogic_vector(0 to width-1); + + err_in : in std_ulogic_vector(0 to width-1); + err_out : out std_ulogic_vector(0 to width-1); + + hold_out : out std_ulogic_vector(0 to width-1); -- sticky error hold latch for trap usage + mask_out : out std_ulogic_vector(0 to width-1) + ); + -- synopsys translate_off + + -- synopsys translate_on + +end tri_err_rpt; + +architecture tri_err_rpt of tri_err_rpt is + +begin -- tri_err_rpt + + a: if expand_type /= 2 generate + constant mask_initv : std_ulogic_vector(0 to (mask_reset_value'length + width-1)):=mask_reset_value & (0 to width-1=>'0'); + signal hold_in : std_ulogic_vector(0 to width-1); + signal hold_lt : std_ulogic_vector(0 to width-1); + signal mask_lt : std_ulogic_vector(0 to width-1); + signal unused : std_ulogic_vector(0 to width); + -- synopsys translate_off + -- synopsys translate_on + begin + -- hold latches + hold_in <= err_in or hold_lt; + + hold: entity tri.tri_nlat_scan + generic map( width => width, + needs_sreset => needs_sreset, + expand_type => expand_type ) + port map + ( vd => vd, + gd => gd, + d1clk => err_d1clk, + d2clk => err_d2clk, + lclk => err_lclk, + scan_in => err_scan_in(0 to width-1), + scan_out => err_scan_out(0 to width-1), + din => hold_in, + q => hold_lt, + q_b => open + ); + + -- mask + m: if (share_mask = false) generate + mask_lt <= mask_initv(0 to width-1); + end generate m; + sm: if (share_mask = true) generate + mask_lt <= (others => mask_initv(0)); + end generate sm; + + mode_scan_out <= (others => '0'); + + -- assign outputs + hold_out <= hold_lt; + mask_out <= mask_lt; + + inline_hold: if (inline = true) generate + err_out <= hold_lt and not mask_lt; + end generate inline_hold; + + side_hold: if (inline = false) generate + err_out <= err_in and not mask_lt; + end generate side_hold; + + unused(0) <= mode_dclk; + unused(1 to width) <= mode_scan_in; + end generate a; + +end tri_err_rpt; diff --git a/rel/src/vhdl/tri/tri_inv_nlats.vhdl b/rel/src/vhdl/tri/tri_inv_nlats.vhdl new file mode 100644 index 0000000..aa501bc --- /dev/null +++ b/rel/src/vhdl/tri/tri_inv_nlats.vhdl @@ -0,0 +1,122 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- *!**************************************************************** +-- *! FILENAME : tri_inv_nlats.vhdl +-- *! DESCRIPTION : n-bit scannable m/s latch, for bit stacking, with inv gate in front +-- *! +-- *!**************************************************************** + +library ieee; use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library support; + use support.power_logic_pkg.all; +library tri; use tri.tri_latches_pkg.all; + +entity tri_inv_nlats is + + generic ( + offset : natural range 0 to 65535 := 0; + width : positive range 1 to 65536 := 1 ; + init : std_ulogic_vector := "0" ; + synthclonedlatch : string := "" ; + btr : string := "NLI0001_X1_A12TH" ; + needs_sreset : integer := 1 ; -- for inferred latches + expand_type : integer := 1 ); -- 1 = non-ibm, 2 = ibm (MPG) + port ( + vd : inout power_logic; + gd : inout power_logic; + LCLK : in clk_logic; + D1CLK : in std_ulogic; + D2CLK : in std_ulogic; + SCANIN : in std_ulogic_vector(offset to offset+width-1); + SCANOUT : out std_ulogic_vector(offset to offset+width-1); + D : in std_ulogic_vector(offset to offset+width-1); + QB : out std_ulogic_vector(offset to offset+width-1) + ); + +end entity tri_inv_nlats; + +architecture tri_inv_nlats of tri_inv_nlats is + +begin + + a: if expand_type = 1 generate + constant init_v : std_ulogic_vector(0 to (init'length + width-1)):=init & (0 to width-1=>'0'); + constant zeros : std_ulogic_vector(0 to width-1) := (0 to width-1 => '0'); + + signal sreset : std_ulogic; + signal int_din : std_ulogic_vector(0 to width-1); + signal int_dout : std_ulogic_vector(0 to width-1) := init_v(0 to width-1); + signal vact, vact_b : std_ulogic_vector(0 to width-1); + signal vsreset, vsreset_b : std_ulogic_vector(0 to width-1); + signal vthold, vthold_b : std_ulogic_vector(0 to width-1); + signal din : std_ulogic_vector(0 to width-1); + signal unused : std_ulogic_vector(0 to width-1); + -- synopsys translate_off + -- synopsys translate_on + begin + rst: if needs_sreset = 1 generate + sreset <= LCLK.sreset; + end generate rst; + no_rst: if needs_sreset /=1 generate + sreset <= '0'; + end generate no_rst; + + vsreset <= (0 to width-1 => sreset); + vsreset_b <= (0 to width-1 => not sreset); + din <= D ; -- Output is inverted, so don't invert here + int_din <= (vsreset_b and din) or + (vsreset and init_v(0 to width-1)); + + vact <= (0 to width-1 => D1CLK); + vact_b <= (0 to width-1 => not D1CLK); + + vthold_b <= (0 to width-1 => D2CLK); + vthold <= (0 to width-1 => not D2CLK); + + l: process (LCLK, vact, int_din, vact_b, int_dout, vsreset, vsreset_b, vthold_b, vthold) + begin + if rising_edge(LCLK.clk) then + int_dout <= (((vact and vthold_b) or vsreset) and int_din) or + (((vact_b or vthold) and vsreset_b) and int_dout); + end if; + end process l; + QB <= not int_dout; + SCANOUT <= zeros; + + unused <= SCANIN; + end generate a; + + + --===================================================== + --== non inverting latch with inv gate in front + --===================================================== + +end tri_inv_nlats; diff --git a/rel/src/vhdl/tri/tri_inv_nlats_wlcb.vhdl b/rel/src/vhdl/tri/tri_inv_nlats_wlcb.vhdl new file mode 100644 index 0000000..866752b --- /dev/null +++ b/rel/src/vhdl/tri/tri_inv_nlats_wlcb.vhdl @@ -0,0 +1,133 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- *!**************************************************************** +-- *! FILENAME : tri_inv_nlats_wlcb.vhdl +-- *! DESCRIPTION : Multi-bit aoi22-latch, LCB included +-- *! +-- *!**************************************************************** + +library ieee; use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library support; + use support.power_logic_pkg.all; +library tri; use tri.tri_latches_pkg.all; + +entity tri_inv_nlats_wlcb is + + generic ( + width : integer := 4; + offset : integer range 0 to 65535 := 0 ; --starting bit + init : integer := 0; -- will be converted to the least signficant + -- 31 bits of init_v + ibuf : boolean := false; --inverted latch IOs, if set to true. + dualscan : string := ""; -- if "S", marks data ports as scan for Moebius + needs_sreset: integer := 1 ; -- for inferred latches + expand_type : integer := 1 ; -- 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) + synthclonedlatch : string := "" ; + btr : string := "NLI0001_X2_A12TH" ); + + port ( + vd : inout power_logic; + gd : inout power_logic; + nclk : in clk_logic; + act : in std_ulogic := '1'; -- 1: functional, 0: no clock + forcee : in std_ulogic := '0'; -- 1: force LCB active + thold_b : in std_ulogic := '1'; -- 1: functional, 0: no clock + d_mode : in std_ulogic := '0'; -- 1: disable pulse mode, 0: pulse mode + sg : in std_ulogic := '0'; -- 0: functional, 1: scan + delay_lclkr : in std_ulogic := '0'; -- 0: functional + mpw1_b : in std_ulogic := '1'; -- pulse width control bit + mpw2_b : in std_ulogic := '1'; -- pulse width control bit + scin : in std_ulogic_vector(offset to offset+width-1); -- scan in + scout : out std_ulogic_vector(offset to offset+width-1); + D : in std_ulogic_vector(offset to offset+width-1); + QB : out std_ulogic_vector(offset to offset+width-1)); + + -- synopsys translate_off + + -- synopsys translate_on + +end entity tri_inv_nlats_wlcb; + +architecture tri_inv_nlats_wlcb of tri_inv_nlats_wlcb is + + constant init_v : std_ulogic_vector(0 to width-1) := std_ulogic_vector( to_unsigned( init, width ) ); + constant zeros : std_ulogic_vector(0 to width-1) := (0 to width-1 => '0'); + +begin + + a: if expand_type = 1 generate + signal sreset : std_ulogic; + signal int_din, din : std_ulogic_vector(0 to width-1); + signal int_dout : std_ulogic_vector(0 to width-1) := init_v; + signal vact, vact_b : std_ulogic_vector(0 to width-1); + signal vsreset, vsreset_b : std_ulogic_vector(0 to width-1); + signal vthold, vthold_b : std_ulogic_vector(0 to width-1); + signal unused : std_ulogic_vector(0 to width); + -- synopsys translate_off + -- synopsys translate_on + begin + rst: if needs_sreset = 1 generate + sreset <= nclk.sreset; + end generate rst; + no_rst: if needs_sreset /=1 generate + sreset <= '0'; + end generate no_rst; + + vsreset <= (0 to width-1 => sreset); + vsreset_b <= (0 to width-1 => not sreset); + + din <= D; + int_din <= (vsreset_b and din) or + (vsreset and init_v); + + vact <= (0 to width-1 => (act or forcee)); + vact_b <= (0 to width-1 => not (act or forcee)); + + vthold_b <= (0 to width-1 => thold_b); + vthold <= (0 to width-1 => not thold_b); + + l: process (nclk, vact, int_din, vact_b, int_dout, vsreset, vsreset_b, vthold_b, vthold) + begin + if rising_edge(nclk.clk) then + int_dout <= (((vact and vthold_b) or vsreset) and int_din) or + (((vact_b or vthold) and vsreset_b) and int_dout); + end if; + end process l; + + QB <= not int_dout; + + scout <= zeros; + + unused(0) <= d_mode or sg or delay_lclkr or mpw1_b or mpw2_b; + unused(1 to width) <= scin; + end generate a; + +end tri_inv_nlats_wlcb; diff --git a/rel/src/vhdl/tri/tri_latches_pkg.vhdl b/rel/src/vhdl/tri/tri_latches_pkg.vhdl new file mode 100644 index 0000000..39163eb --- /dev/null +++ b/rel/src/vhdl/tri/tri_latches_pkg.vhdl @@ -0,0 +1,519 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +LIBRARY ieee; USE ieee.std_logic_1164.all; +LIBRARY support; USE support.power_logic_pkg.all; + +PACKAGE tri_latches_pkg IS + + type clk_logic is record + clk : std_ulogic; + sreset : std_ulogic; + clk2x : std_ulogic; + clk4x : std_ulogic; + end record; + + type clk_logic_vector is array ( NATURAL range <> ) of clk_logic; + + + component tri_cw_nlat + generic ( + bhc:string:=""; + ub:string:=""; + offset : natural range 0 to 65535 := 0; + width : positive range 1 to 65536 := 1 ; + init : std_ulogic_vector := "0"; + needs_sreset : integer := 1 ; -- for inferred latches + expand_type : integer := 1 ); -- 1 = non-ibm, 2 = ibm (MPG) + port ( + vd : inout power_logic; + gd : inout power_logic; + d_b : in std_ulogic_vector(0 to width-1); + scan_in : in std_ulogic_vector(0 to width-1); + d1clk : in std_ulogic; + d2clk : in std_ulogic; + lclk : in clk_logic; + q_b : out std_ulogic_vector(0 to width-1); + scan_out : out std_ulogic_vector(0 to width-1) + ); + end component; + + component tri_direct_err_rpt + generic ( + width : positive := 1 ; -- use to bundle error reporting checkers of the same exact type + expand_type : integer := 1 ); -- 1 = non-ibm, 2 = ibm (MPG) + port ( + vd : inout power_logic; + gd : inout power_logic; + + err_in : in std_ulogic_vector(0 to width-1); + err_out : out std_ulogic_vector(0 to width-1) + ); + end component; + + component tri_err_rpt + generic ( + width : positive := 1; -- number of errors of the same type + mask_reset_value : std_ulogic_vector := "0";-- use to set default/flush value for mask bits + inline : boolean := false; -- make hold latch be inline; err_out is sticky -- default to shadow + reset_hold : boolean := false; -- make Hold latch use reset input + needs_sreset : integer := 1 ; -- for inferred latches + expand_type : integer := 1 ); -- 1 = non-ibm, 2 = ibm (MPG) + port ( + vd : inout power_logic; + gd : inout power_logic; + err_d1clk : in std_ulogic; -- caution: if lcb uses powersavings, errors must always get reported + err_d2clk : in std_ulogic; + err_lclk : in clk_logic; + -- error scan chain (func or mode) + err_scan_in : in std_ulogic_vector(0 to width-1); + err_scan_out : out std_ulogic_vector(0 to width-1); + -- clock gateable mode clocks + mode_dclk : in std_ulogic; + mode_lclk : in clk_logic; + -- mode scan chain + mode_scan_in : in std_ulogic_vector(0 to width-1); + mode_scan_out : out std_ulogic_vector(0 to width-1); + + err_in : in std_ulogic_vector(0 to width-1); + err_out : out std_ulogic_vector(0 to width-1); + + hold_out : out std_ulogic_vector(0 to width-1); -- sticky error hold latch for trap usage + mask_out : out std_ulogic_vector(0 to width-1) + ); + end component; + + component tri_klat + generic ( + width : positive range 1 to 65536 := 1 ; + offset : natural range 0 to 65535 := 0; + init : std_ulogic_vector := "0" ; + synthclonedlatch : string := "" ; + needs_sreset : integer := 1 ; -- for inferred latches + expand_type : integer := 1 ); -- 1 = non-ibm, 2 = ibm (MPG) + port ( + vd : inout power_logic; + gd : inout power_logic; + dclk : in std_ulogic; + lclk : in clk_logic; + din : in std_ulogic_vector(offset to offset+width-1); + q : out std_ulogic_vector(offset to offset+width-1); + q_b : out std_ulogic_vector(offset to offset+width-1) + ); + end component; + + component tri_lcbcntl_array_mac + generic ( expand_type : integer := 1 ); -- 1 = non-ibm, 2 = ibm (MPG) + port ( + vdd : inout power_logic; + gnd : inout power_logic; + sg : in std_ulogic; + nclk : in clk_logic; + scan_in : in std_ulogic; + scan_diag_dc : in std_ulogic; + thold : in std_ulogic; + clkoff_dc_b : out std_ulogic; + delay_lclkr_dc : out std_ulogic_vector(0 to 4); + act_dis_dc : out std_ulogic; + d_mode_dc : out std_ulogic; + mpw1_dc_b : out std_ulogic_vector(0 to 4); + mpw2_dc_b : out std_ulogic; + scan_out : out std_ulogic + ); + end component; + + component tri_lcbcntl_mac + generic ( expand_type : integer := 1 ); -- 1 = non-ibm, 2 = ibm (MPG) + port ( + vdd : inout power_logic; + gnd : inout power_logic; + sg : in std_ulogic; + nclk : in clk_logic; + scan_in : in std_ulogic; + scan_diag_dc : in std_ulogic; + thold : in std_ulogic; + clkoff_dc_b : out std_ulogic; + delay_lclkr_dc : out std_ulogic_vector(0 to 4); + act_dis_dc : out std_ulogic; + d_mode_dc : out std_ulogic; + mpw1_dc_b : out std_ulogic_vector(0 to 4); + mpw2_dc_b : out std_ulogic; + scan_out : out std_ulogic + ); + end component; + + component tri_lcbkd + generic ( expand_type : integer := 1 ); -- 1 = non-ibm, 2 = ibm (MPG) + port ( + vd : inout power_logic; + gd : inout power_logic; + act : in std_ulogic; + delay_lclkr : in std_ulogic; + mpw1_b : in std_ulogic; + mpw2_b : in std_ulogic; + nclk : in clk_logic; + forcee : in std_ulogic; + thold_b : in std_ulogic; + dclk : out std_ulogic; + lclk : out clk_logic + ); + end component; + + component tri_lcbnd + generic ( expand_type : integer := 1 ); -- 1 = non-ibm, 2 = ibm (MPG) + port ( + vd : inout power_logic; + gd : inout power_logic; + act : in std_ulogic; + delay_lclkr : in std_ulogic; + mpw1_b : in std_ulogic; + mpw2_b : in std_ulogic; + nclk : in clk_logic; + forcee : in std_ulogic; + sg : in std_ulogic; + thold_b : in std_ulogic; + d1clk : out std_ulogic; + d2clk : out std_ulogic; + lclk : out clk_logic + ); + end component; + + component tri_lcbor + generic ( expand_type : integer := 1 ); -- 1 = non-ibm, 2 = ibm (MPG) + port ( + clkoff_b : in std_ulogic; + thold : in std_ulogic; + sg : in std_ulogic; + act_dis : in std_ulogic; + forcee : out std_ulogic; + thold_b : out std_ulogic + ); + end component; + + component tri_lcbs + generic ( expand_type : integer := 1 ); -- 1 = non-ibm, 2 = ibm (MPG) + port ( + vd : inout power_logic; + gd : inout power_logic; + delay_lclkr : in std_ulogic; + nclk : in clk_logic; + forcee : in std_ulogic; + thold_b : in std_ulogic; + dclk : out std_ulogic; + lclk : out clk_logic + ); + end component; + + component tri_nlat + generic ( + offset : natural range 0 to 65535 := 0; + reset_inverts_scan : boolean := true; + width : positive range 1 to 65536 := 1 ; + init : std_ulogic_vector := "0" ; + synthclonedlatch : string := "" ; + needs_sreset : integer := 1 ; -- for inferred latches + expand_type : integer := 1 ); -- 1 = non-ibm, 2 = ibm (MPG) + port ( + vd : inout power_logic; + gd : inout power_logic; + d1clk : in std_ulogic; + d2clk : in std_ulogic; + lclk : in clk_logic; + scan_in : in std_ulogic; + din : in std_ulogic_vector(offset to offset+width-1); + q : out std_ulogic_vector(offset to offset+width-1); + q_b : out std_ulogic_vector(offset to offset+width-1); + scan_out : out std_ulogic + ); + end component; + + component tri_nlat_scan + generic ( + offset : natural range 0 to 65535 := 0; + width : positive range 1 to 65536 := 1 ; + init : std_ulogic_vector := "0" ; + reset_inverts_scan : boolean := true; + synthclonedlatch : string := "" ; + needs_sreset : integer := 1 ; -- for inferred latches + expand_type : integer := 1 ); -- 1 = non-ibm, 2 = ibm (MPG) + port ( + vd : inout power_logic; + gd : inout power_logic; + d1clk : in std_ulogic; + d2clk : in std_ulogic; + lclk : in clk_logic; + din : in std_ulogic_vector(offset to offset+width-1); + scan_in : in std_ulogic_vector(offset to offset+width-1); + q : out std_ulogic_vector(offset to offset+width-1); + q_b : out std_ulogic_vector(offset to offset+width-1); + scan_out : out std_ulogic_vector(offset to offset+width-1) + ); + end component; + + component tri_plat + generic ( + width : positive range 1 to 65536 := 1 ; + offset : natural range 0 to 65535 := 0 ; + init : integer := 0; -- will be converted to the least signficant 31 bits of init_v + synthclonedlatch : string := "" ; + flushlat : boolean := true ; + expand_type : integer := 1 ); -- 1 = non-ibm, 2 = ibm (MPG) + port ( + vd : inout power_logic; + gd : inout power_logic; + nclk : in clk_logic; + flush : in std_ulogic; + din : in std_ulogic_vector(offset to offset+width-1); + q : out std_ulogic_vector(offset to offset+width-1) ); + end component; + + component tri_regk + generic ( + width : integer := 4; + offset : integer range 0 to 65535 := 0 ; --starting bit + init : integer := 0; -- will be converted to the least signficant + -- 31 bits of init_v + synthclonedlatch : string := ""; + needs_sreset : integer := 1 ; -- for inferred latches + expand_type : integer := 1 );-- 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) + port ( + vd : inout power_logic; + gd : inout power_logic; + nclk : in clk_logic; + act : in std_ulogic := '1'; -- 1: functional, 0: no clock + forcee : in std_ulogic := '0'; -- 1: force LCB active + thold_b : in std_ulogic := '1'; -- 1: functional, 0: no clock + d_mode : in std_ulogic := '0'; -- 1: disable pulse mode, 0: pulse mode + delay_lclkr : in std_ulogic := '0'; -- 0: functional + mpw1_b : in std_ulogic := '1'; -- pulse width control bit + mpw2_b : in std_ulogic := '1'; -- pulse width control bit + din : in std_ulogic_vector(offset to offset+width-1); -- data in + dout : out std_ulogic_vector(offset to offset+width-1) ); + end component; + + component tri_regs + generic ( + width : integer := 4; + offset : integer range 0 to 65535 := 0 ; --starting bit + init : integer := 0; -- will be converted to the least signficant + -- 31 bits of init_v + ibuf : boolean := false; --inverted latch IOs, if set to true. + dualscan : string := ""; -- if "S", marks data ports as scan for Moebius + needs_sreset : integer := 1 ; -- for inferred latches + expand_type : integer := 1 );-- 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) + port ( + vd : inout power_logic; + gd : inout power_logic; + nclk : in clk_logic; + forcee : in std_ulogic := '0'; -- 1: force LCB active + thold_b : in std_ulogic := '1'; -- 1: functional, 0: no clock + delay_lclkr : in std_ulogic := '0'; -- 0: functional + scin : in std_ulogic_vector(offset to offset+width-1); -- scan in + scout : out std_ulogic_vector(offset to offset+width-1); + dout : out std_ulogic_vector(offset to offset+width-1) ); + end component; + + component tri_rlmlatch_p + generic ( + init : integer := 0; -- will be converted to the least signficant + -- 31 bits of init_v + ibuf : boolean := false; --inverted latch IOs, if set to true. + dualscan : string := ""; -- if "S", marks data ports as scan for Moebius + needs_sreset: integer := 1 ; -- for inferred latches + expand_type : integer := 1 );-- 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) + port ( + vd : inout power_logic; + gd : inout power_logic; + nclk : in clk_logic; + act : in std_ulogic := '1'; -- 1: functional, 0: no clock + forcee : in std_ulogic := '0'; -- 1: force LCB active + thold_b : in std_ulogic := '1'; -- 1: functional, 0: no clock + d_mode : in std_ulogic := '0'; -- 1: disable pulse mode, 0: pulse mode + sg : in std_ulogic := '0'; -- 0: functional, 1: scan + delay_lclkr : in std_ulogic := '0'; -- 0: functional + mpw1_b : in std_ulogic := '1'; -- pulse width control bit + mpw2_b : in std_ulogic := '1'; -- pulse width control bit + scin : in std_ulogic := '0'; -- scan in + din : in std_ulogic; -- data in + scout : out std_ulogic; -- scan out + dout : out std_ulogic); -- data out + end component; + + component tri_rlmreg_p + generic ( + width : integer := 4; + offset : integer range 0 to 65535 := 0 ; --starting bit + init : integer := 0; -- will be converted to the least signficant + -- 31 bits of init_v + ibuf : boolean := false; --inverted latch IOs, if set to true. + dualscan : string := ""; -- if "S", marks data ports as scan for Moebius + needs_sreset: integer := 1 ; -- for inferred latches + expand_type : integer := 1 );-- 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) + port ( + vd : inout power_logic; + gd : inout power_logic; + nclk : in clk_logic; + act : in std_ulogic := '1'; -- 1: functional, 0: no clock + forcee : in std_ulogic := '0'; -- 1: force LCB active + thold_b : in std_ulogic := '1'; -- 1: functional, 0: no clock + d_mode : in std_ulogic := '0'; -- 1: disable pulse mode, 0: pulse mode + sg : in std_ulogic := '0'; -- 0: functional, 1: scan + delay_lclkr : in std_ulogic := '0'; -- 0: functional + mpw1_b : in std_ulogic := '1'; -- pulse width control bit + mpw2_b : in std_ulogic := '1'; -- pulse width control bit + scin : in std_ulogic_vector(offset to offset+width-1); -- scan in + din : in std_ulogic_vector(offset to offset+width-1); -- data in + scout : out std_ulogic_vector(offset to offset+width-1); + dout : out std_ulogic_vector(offset to offset+width-1) ); + end component; + + component tri_slat + generic ( + width : positive range 1 to 65536 := 1; + offset : natural range 0 to 65535 := 0; + init : std_ulogic_vector := "0"; + synthclonedlatch : string := ""; + reset_inverts_scan : boolean := true; + expand_type : integer := 1); -- 1 - other (FPGA), 2 - MPG + port ( + vd : inout power_logic; + gd : inout power_logic; + dclk : in std_ulogic; + lclk : in clk_logic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + q : out std_ulogic_vector(offset to offset+width-1); + q_b : out std_ulogic_vector(offset to offset+width-1)); + end component; + + component tri_slat_lbist + generic ( + width : positive range 1 to 65536 := 1; + offset : natural range 0 to 65535 := 0; + init : std_ulogic_vector := "0"; + synthclonedlatch : string := ""; + reset_inverts_scan : boolean := true; + expand_type : integer := 1); -- 1 - other (FPGA), 2 - MPG + port ( + vd : inout power_logic; + gd : inout power_logic; + dclk : in std_ulogic; + lclk : in clk_logic; + tc_xx_lbist_ac_mode_dc : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + q : out std_ulogic_vector(offset to offset+width-1); + q_b : out std_ulogic_vector(offset to offset+width-1)); + end component; + + component tri_slat_scan + generic ( + width : positive range 1 to 65536 := 1 ; + offset : natural range 0 to 65535 := 0; + init : std_ulogic_vector := "0" ; + synthclonedlatch : string := "" ; + btr : string := "c_slat_scan" ; + reset_inverts_scan : boolean := true; + expand_type : integer := 1 ); -- 1 = non-ibm, 2 = ibm (MPG) + port ( + vd : inout power_logic; + gd : inout power_logic; + dclk : in std_ulogic; + lclk : in clk_logic; + scan_in : in std_ulogic_vector(offset to offset+width-1); + scan_out : out std_ulogic_vector(offset to offset+width-1); + q : out std_ulogic_vector(offset to offset+width-1); + q_b : out std_ulogic_vector(offset to offset+width-1) + ); + end component; + + component tri_ser_rlmreg_p + generic ( + width : positive range 1 to 65536 := 1 ; + offset : natural range 0 to 65535 := 0 ; + init : integer := 0; + ibuf : boolean := false; + dualscan : string := ""; + needs_sreset : integer := 1 ; + expand_type : integer := 1 ); + port ( + vd : inout power_logic; + gd : inout power_logic; + nclk : in clk_logic; + act : in std_ulogic := '1'; + forcee : in std_ulogic := '0'; + thold_b : in std_ulogic := '1'; + d_mode : in std_ulogic := '0'; + sg : in std_ulogic := '0'; + delay_lclkr : in std_ulogic := '0'; + mpw1_b : in std_ulogic := '1'; + mpw2_b : in std_ulogic := '1'; + scin : in std_ulogic_vector(offset to offset+width-1); + din : in std_ulogic_vector(offset to offset+width-1); + scout : out std_ulogic_vector(offset to offset+width-1); + dout : out std_ulogic_vector(offset to offset+width-1)); + end component; + + component tri_aoi22_nlats_wlcb + generic ( + width : integer := 4; + offset : integer range 0 to 65535 := 0 ; --starting bit + init : integer := 0; -- will be converted to the least signficant + -- 31 bits of init_v + ibuf : boolean := false; --inverted latch IOs, if set to true. + dualscan : string := ""; -- if "S", marks data ports as scan for Moebius + needs_sreset : integer := 1 ; -- for inferred latches + expand_type : integer := 1 ; -- 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) + synthclonedlatch : string := "" ; + btr : string := "NLL0001_X2_A12TH" ); + port ( + vd : inout power_logic; + gd : inout power_logic; + nclk : in clk_logic; + act : in std_ulogic := '1'; -- 1: functional, 0: no clock + forcee : in std_ulogic := '0'; -- 1: force LCB active + thold_b : in std_ulogic := '1'; -- 1: functional, 0: no clock + d_mode : in std_ulogic := '0'; -- 1: disable pulse mode, 0: pulse mode + sg : in std_ulogic := '0'; -- 0: functional, 1: scan + delay_lclkr : in std_ulogic := '0'; -- 0: functional + mpw1_b : in std_ulogic := '1'; -- pulse width control bit + mpw2_b : in std_ulogic := '1'; -- pulse width control bit + scin : in std_ulogic_vector(offset to offset+width-1); -- scan in + scout : out std_ulogic_vector(offset to offset+width-1); + A1 : in std_ulogic_vector(offset to offset+width-1); + A2 : in std_ulogic_vector(offset to offset+width-1); + B1 : in std_ulogic_vector(offset to offset+width-1); + B2 : in std_ulogic_vector(offset to offset+width-1); + QB : out std_ulogic_vector(offset to offset+width-1)); + end component; + +end tri_latches_pkg; + +package body tri_latches_pkg is + +end tri_latches_pkg; diff --git a/rel/src/vhdl/tri/tri_lcbcntl_array_mac.vhdl b/rel/src/vhdl/tri/tri_lcbcntl_array_mac.vhdl new file mode 100644 index 0000000..577c4c2 --- /dev/null +++ b/rel/src/vhdl/tri/tri_lcbcntl_array_mac.vhdl @@ -0,0 +1,89 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- *!**************************************************************** +-- *! FILENAME : tri_lcbcntl_array_mac.vhdl +-- *! DESCRIPTION : Used to generate control signals for LCBs +-- *!**************************************************************** + +library ieee; use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library support; + use support.power_logic_pkg.all; +library tri; use tri.tri_latches_pkg.all; +-- pragma translate_off +-- pragma translate_on + +entity tri_lcbcntl_array_mac is + + generic ( expand_type : integer := 1 ); -- 1 = non-ibm, 2 = ibm (MPG) + + port ( + vdd : inout power_logic; + gnd : inout power_logic; + sg : in std_ulogic; + nclk : in clk_logic; + scan_in : in std_ulogic; + scan_diag_dc : in std_ulogic; + thold : in std_ulogic; + clkoff_dc_b : out std_ulogic; + delay_lclkr_dc : out std_ulogic_vector(0 to 4); + act_dis_dc : out std_ulogic; + d_mode_dc : out std_ulogic; + mpw1_dc_b : out std_ulogic_vector(0 to 4); + mpw2_dc_b : out std_ulogic; + scan_out : out std_ulogic + ); + + -- synopsys translate_off + + -- synopsys translate_on + +end entity tri_lcbcntl_array_mac; + +architecture tri_lcbcntl_array_mac of tri_lcbcntl_array_mac is + + signal unused : std_ulogic; + -- synopsys translate_off + -- synopsys translate_on + +begin + + a: if expand_type = 1 generate + clkoff_dc_b <= '1'; + delay_lclkr_dc <= "00000"; + act_dis_dc <= '0'; + d_mode_dc <= '0'; + mpw1_dc_b <= "11111"; + mpw2_dc_b <= '1'; + scan_out <= '0'; + unused <= sg or scan_in or scan_diag_dc or thold; + end generate a; + +end tri_lcbcntl_array_mac; diff --git a/rel/src/vhdl/tri/tri_lcbcntl_mac.vhdl b/rel/src/vhdl/tri/tri_lcbcntl_mac.vhdl new file mode 100644 index 0000000..f2ccc4f --- /dev/null +++ b/rel/src/vhdl/tri/tri_lcbcntl_mac.vhdl @@ -0,0 +1,89 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- *!**************************************************************** +-- *! FILENAME : tri_lcbcntl_mac.vhdl +-- *! DESCRIPTION : Used to generate control signals for LCBs +-- *!**************************************************************** + +library ieee; use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library support; + use support.power_logic_pkg.all; +library tri; use tri.tri_latches_pkg.all; +-- pragma translate_off +-- pragma translate_on + +entity tri_lcbcntl_mac is + + generic ( expand_type : integer := 1 ); -- 1 = non-ibm, 2 = ibm (MPG) + + port ( + vdd : inout power_logic; + gnd : inout power_logic; + sg : in std_ulogic; + nclk : in clk_logic; + scan_in : in std_ulogic; + scan_diag_dc : in std_ulogic; + thold : in std_ulogic; + clkoff_dc_b : out std_ulogic; + delay_lclkr_dc : out std_ulogic_vector(0 to 4); + act_dis_dc : out std_ulogic; + d_mode_dc : out std_ulogic; + mpw1_dc_b : out std_ulogic_vector(0 to 4); + mpw2_dc_b : out std_ulogic; + scan_out : out std_ulogic + ); + + -- synopsys translate_off + + -- synopsys translate_on + +end entity tri_lcbcntl_mac; + +architecture tri_lcbcntl_mac of tri_lcbcntl_mac is + + signal unused : std_ulogic; + -- synopsys translate_off + -- synopsys translate_on + +begin + + a: if expand_type = 1 generate + clkoff_dc_b <= '1'; + delay_lclkr_dc <= "00000"; + act_dis_dc <= '0'; + d_mode_dc <= '0'; + mpw1_dc_b <= "11111"; + mpw2_dc_b <= '1'; + scan_out <= '0'; + unused <= sg or scan_in or scan_diag_dc or thold; + end generate a; + +end tri_lcbcntl_mac; diff --git a/rel/src/vhdl/tri/tri_lcbnd.vhdl b/rel/src/vhdl/tri/tri_lcbnd.vhdl new file mode 100644 index 0000000..2711935 --- /dev/null +++ b/rel/src/vhdl/tri/tri_lcbnd.vhdl @@ -0,0 +1,88 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- *!**************************************************************** +-- *! FILENAME : tri_lcbnd.vhdl +-- *! DESCRIPTION : Wrapper for nlat LCB - will not run in pulsed mode +-- *!**************************************************************** + +library ieee; use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library support; + use support.power_logic_pkg.all; +library tri; use tri.tri_latches_pkg.all; +-- pragma translate_off +-- pragma translate_on + +entity tri_lcbnd is + + generic ( expand_type : integer := 1 ); -- 1 = non-ibm, 2 = ibm (MPG) + + port ( + vd : inout power_logic; + gd : inout power_logic; + act : in std_ulogic; + delay_lclkr : in std_ulogic; + mpw1_b : in std_ulogic; + mpw2_b : in std_ulogic; + nclk : in clk_logic; + forcee : in std_ulogic; + sg : in std_ulogic; + thold_b : in std_ulogic; + d1clk : out std_ulogic; + d2clk : out std_ulogic; + lclk : out clk_logic + ); + + -- synopsys translate_off + + -- synopsys translate_on + +end entity tri_lcbnd; + +architecture tri_lcbnd of tri_lcbnd is + +begin + + a: if expand_type = 1 generate + signal gate_b : std_ulogic; + signal unused : std_ulogic; + -- synopsys translate_off + -- synopsys translate_on + begin + gate_b <= forcee or act; + + d1clk <= gate_b; + d2clk <= thold_b; + lclk <= nclk; + + unused <= delay_lclkr or mpw1_b or mpw2_b or sg; + end generate a; + +end tri_lcbnd; diff --git a/rel/src/vhdl/tri/tri_lcbor.vhdl b/rel/src/vhdl/tri/tri_lcbor.vhdl new file mode 100644 index 0000000..c9f67bf --- /dev/null +++ b/rel/src/vhdl/tri/tri_lcbor.vhdl @@ -0,0 +1,67 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- *!**************************************************************** +-- *! FILENAME : tri_lcbor.vhdl +-- *! DESCRIPTION : Used to generate LCB controls +-- *!**************************************************************** + +library ieee; use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library support; + use support.power_logic_pkg.all; + +entity tri_lcbor is + + generic ( expand_type : integer := 1 ); -- 1 = non-ibm, 2 = ibm (MPG) + + port ( + clkoff_b : in std_ulogic; + thold : in std_ulogic; + sg : in std_ulogic; + act_dis : in std_ulogic; + forcee : out std_ulogic; + thold_b : out std_ulogic + ); + +end entity tri_lcbor; + +architecture tri_lcbor of tri_lcbor is + + signal unused : std_ulogic; + +begin + + a: if expand_type = 1 generate + forcee <= '0'; + thold_b <= not thold; + unused <= clkoff_b or sg or act_dis; + end generate a; + +end tri_lcbor; diff --git a/rel/src/vhdl/tri/tri_lcbs.vhdl b/rel/src/vhdl/tri/tri_lcbs.vhdl new file mode 100644 index 0000000..19f4511 --- /dev/null +++ b/rel/src/vhdl/tri/tri_lcbs.vhdl @@ -0,0 +1,71 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- *!**************************************************************** +-- *! FILENAME : tri_lcbs.vhdl +-- *! DESCRIPTION : Wrapper for slat LCB +-- *!**************************************************************** + +library ieee; use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library support; + use support.power_logic_pkg.all; +library tri; use tri.tri_latches_pkg.all; + +entity tri_lcbs is + + generic ( expand_type : integer := 1 ); -- 1 = non-ibm, 2 = ibm (MPG) + + port ( + vd : inout power_logic; + gd : inout power_logic; + delay_lclkr : in std_ulogic; + nclk : in clk_logic; + forcee : in std_ulogic; + thold_b : in std_ulogic; + dclk : out std_ulogic; + lclk : out clk_logic + ); + +end entity tri_lcbs; + +architecture tri_lcbs of tri_lcbs is + +begin + + a: if expand_type = 1 generate + signal unused : std_ulogic; + begin + -- No scan chain in this methodology + dclk <= thold_b; + lclk <= nclk; + unused <= delay_lclkr or forcee; + end generate a; + +end tri_lcbs; diff --git a/rel/src/vhdl/tri/tri_nand2_nlats.vhdl b/rel/src/vhdl/tri/tri_nand2_nlats.vhdl new file mode 100644 index 0000000..9016cd8 --- /dev/null +++ b/rel/src/vhdl/tri/tri_nand2_nlats.vhdl @@ -0,0 +1,122 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- *!**************************************************************** +-- *! FILENAME : tri_nand2_nlats.vhdl +-- *! DESCRIPTION : n-bit scannable m/s latch, for bit stacking, with nand2 gate in front +-- *!**************************************************************** + +library ieee; use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library support; + use support.power_logic_pkg.all; +library tri; use tri.tri_latches_pkg.all; + +entity tri_nand2_nlats is + + generic ( + offset : natural range 0 to 65535 := 0; + width : positive range 1 to 65536 := 1 ; + init : std_ulogic_vector := "0" ; + synthclonedlatch : string := "" ; + btr : string := "NLA0001_X1_A12TH" ; + needs_sreset : integer := 1 ; -- for inferred latches + expand_type : integer := 1 ); -- 1 = non-ibm, 2 = ibm (MPG) + port ( + vd : inout power_logic; + gd : inout power_logic; + LCLK : in clk_logic; + D1CLK : in std_ulogic; + D2CLK : in std_ulogic; + SCANIN : in std_ulogic_vector(offset to offset+width-1); + SCANOUT : out std_ulogic_vector(offset to offset+width-1); + A1 : in std_ulogic_vector(offset to offset+width-1); + A2 : in std_ulogic_vector(offset to offset+width-1); + QB : out std_ulogic_vector(offset to offset+width-1) + ); + +end entity tri_nand2_nlats; + +architecture tri_nand2_nlats of tri_nand2_nlats is + +begin + + a: if expand_type = 1 generate + constant init_v : std_ulogic_vector(0 to (init'length + width-1)):=init & (0 to width-1=>'0'); + constant zeros : std_ulogic_vector(0 to width-1) := (0 to width-1 => '0'); + + signal sreset : std_ulogic; + signal int_din : std_ulogic_vector(0 to width-1); + signal int_dout : std_ulogic_vector(0 to width-1) := init_v(0 to width-1); + signal vact, vact_b : std_ulogic_vector(0 to width-1); + signal vsreset, vsreset_b : std_ulogic_vector(0 to width-1); + signal vthold, vthold_b : std_ulogic_vector(0 to width-1); + signal din : std_ulogic_vector(0 to width-1); + signal unused : std_ulogic_vector(0 to width-1); + -- synopsys translate_off + -- synopsys translate_on + begin + rst: if needs_sreset = 1 generate + sreset <= LCLK.sreset; + end generate rst; + no_rst: if needs_sreset /=1 generate + sreset <= '0'; + end generate no_rst; + + vsreset <= (0 to width-1 => sreset); + vsreset_b <= (0 to width-1 => not sreset); + din <= A1 and A2; -- Output is inverted, so just AND2 here + int_din <= (vsreset_b and din) or + (vsreset and init_v(0 to width-1)); + + vact <= (0 to width-1 => D1CLK); + vact_b <= (0 to width-1 => not D1CLK); + + vthold_b <= (0 to width-1 => D2CLK); + vthold <= (0 to width-1 => not D2CLK); + + l: process (LCLK, vact, int_din, vact_b, int_dout, vsreset, vsreset_b, vthold_b, vthold) + begin + if rising_edge(LCLK.clk) then + int_dout <= (((vact and vthold_b) or vsreset) and int_din) or + (((vact_b or vthold) and vsreset_b) and int_dout); + end if; + end process l; + QB <= not int_dout; + SCANOUT <= zeros; + + unused <= SCANIN; + end generate a; + + + --===================================================== + --== non inverting latch with nand2 gate in front + --===================================================== + +end tri_nand2_nlats; diff --git a/rel/src/vhdl/tri/tri_nlat.vhdl b/rel/src/vhdl/tri/tri_nlat.vhdl new file mode 100644 index 0000000..cc2c9e6 --- /dev/null +++ b/rel/src/vhdl/tri/tri_nlat.vhdl @@ -0,0 +1,115 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- *!**************************************************************** +-- *! FILENAME : tri_nlat.vhdl +-- *! DESCRIPTION : Basic n-bit latch w/ internal scan +-- *!**************************************************************** + +library ieee; use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library support; + use support.power_logic_pkg.all; +library tri; use tri.tri_latches_pkg.all; + +entity tri_nlat is + + generic ( + offset : natural range 0 to 65535 := 0; + reset_inverts_scan : boolean := true; + width : positive range 1 to 65536 := 1 ; + init : std_ulogic_vector := "0" ; + synthclonedlatch : string := "" ; + needs_sreset : integer := 1 ; -- for inferred latches + expand_type : integer := 1 ); -- 1 = non-ibm, 2 = ibm (MPG) + port ( + vd : inout power_logic; + gd : inout power_logic; + d1clk : in std_ulogic; + d2clk : in std_ulogic; + lclk : in clk_logic; + scan_in : in std_ulogic; + din : in std_ulogic_vector(offset to offset+width-1); + q : out std_ulogic_vector(offset to offset+width-1); + q_b : out std_ulogic_vector(offset to offset+width-1); + scan_out : out std_ulogic + ); + +end entity tri_nlat; + +architecture tri_nlat of tri_nlat is + +begin + + a: if expand_type = 1 generate + constant init_v : std_ulogic_vector(0 to (init'length + width-1)):=init & (0 to width-1=>'0'); + constant zeros : std_ulogic_vector(0 to width-1) := (0 to width-1 => '0'); + + signal sreset : std_ulogic; + signal int_din : std_ulogic_vector(0 to width-1); + signal int_dout : std_ulogic_vector(0 to width-1) := init_v(0 to width-1); + signal vact, vact_b : std_ulogic_vector(0 to width-1); + signal vsreset, vsreset_b : std_ulogic_vector(0 to width-1); + signal vthold, vthold_b : std_ulogic_vector(0 to width-1); + signal unused : std_ulogic; + -- synopsys translate_off + -- synopsys translate_on + begin + rst: if needs_sreset = 1 generate + sreset <= lclk.sreset; + end generate rst; + no_rst: if needs_sreset /=1 generate + sreset <= '0'; + end generate no_rst; + + vsreset <= (0 to width-1 => sreset); + vsreset_b <= (0 to width-1 => not sreset); + int_din <= (vsreset_b and din) or + (vsreset and init_v(0 to width-1)); + + vact <= (0 to width-1 => d1clk); + vact_b <= (0 to width-1 => not d1clk); + + vthold_b <= (0 to width-1 => d2clk); + vthold <= (0 to width-1 => not d2clk); + + l: process (lclk, vact, int_din, vact_b, int_dout, vsreset, vsreset_b, vthold_b, vthold) + begin + if rising_edge(lclk.clk) then + int_dout <= (((vact and vthold_b) or vsreset) and int_din) or + (((vact_b or vthold) and vsreset_b) and int_dout); + end if; + end process l; + q <= int_dout; + q_b <= not int_dout; + scan_out <= zeros(0); + unused <= scan_in; + end generate a; + +end tri_nlat; diff --git a/rel/src/vhdl/tri/tri_nlat_scan.vhdl b/rel/src/vhdl/tri/tri_nlat_scan.vhdl new file mode 100644 index 0000000..ee8f2c4 --- /dev/null +++ b/rel/src/vhdl/tri/tri_nlat_scan.vhdl @@ -0,0 +1,120 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- *!**************************************************************** +-- *! FILENAME : tri_nlat_scan.vhdl +-- *! DESCRIPTION : Basic n-bit latch +-- *!**************************************************************** + +library ieee; use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library support; + use support.power_logic_pkg.all; +library tri; use tri.tri_latches_pkg.all; +-- pragma translate_off +-- pragma translate_on + +entity tri_nlat_scan is + + generic ( offset : natural range 0 to 65535 := 0; + width : positive range 1 to 65536 := 1 ; + init : std_ulogic_vector := "0" ; + reset_inverts_scan : boolean := true; + synthclonedlatch : string := "" ; + needs_sreset : integer := 1 ; -- for inferred latches + expand_type : integer := 1 ); -- 1 = non-ibm, 2 = ibm (MPG) + port ( + vd : inout power_logic; + gd : inout power_logic; + d1clk : in std_ulogic; + d2clk : in std_ulogic; + lclk : in clk_logic; + din : in std_ulogic_vector(offset to offset+width-1); + scan_in : in std_ulogic_vector(offset to offset+width-1); + q : out std_ulogic_vector(offset to offset+width-1); + q_b : out std_ulogic_vector(offset to offset+width-1); + scan_out : out std_ulogic_vector(offset to offset+width-1) + ); + + -- synopsys translate_off + + -- synopsys translate_on + +end entity tri_nlat_scan; + +architecture tri_nlat_scan of tri_nlat_scan is + +begin + + a: if expand_type = 1 generate + constant init_v : std_ulogic_vector(0 to (init'length + width-1)):=init & (0 to width-1=>'0'); + constant zeros : std_ulogic_vector(0 to width-1) := (0 to width-1 => '0'); + + signal sreset : std_ulogic; + signal int_din : std_ulogic_vector(0 to width-1); + signal int_dout : std_ulogic_vector(0 to width-1) := init_v(0 to width-1); + signal vact, vact_b : std_ulogic_vector(0 to width-1); + signal vsreset, vsreset_b : std_ulogic_vector(0 to width-1); + signal vthold, vthold_b : std_ulogic_vector(0 to width-1); + signal unused : std_ulogic_vector(0 to width-1); + -- synopsys translate_off + -- synopsys translate_on + begin + rst: if needs_sreset = 1 generate + sreset <= lclk.sreset; + end generate rst; + no_rst: if needs_sreset /=1 generate + sreset <= '0'; + end generate no_rst; + + vsreset <= (0 to width-1 => sreset); + vsreset_b <= (0 to width-1 => not sreset); + int_din <= (vsreset_b and din) or + (vsreset and init_v(0 to width-1)); + + vact <= (0 to width-1 => d1clk); + vact_b <= (0 to width-1 => not d1clk); + + vthold_b <= (0 to width-1 => d2clk); + vthold <= (0 to width-1 => not d2clk); + + l: process (lclk, vact, int_din, vact_b, int_dout, vsreset, vsreset_b, vthold_b, vthold) + begin + if rising_edge(lclk.clk) then + int_dout <= (((vact and vthold_b) or vsreset) and int_din) or + (((vact_b or vthold) and vsreset_b) and int_dout); + end if; + end process l; + q <= int_dout; + q_b <= not int_dout; + scan_out <= zeros; + unused <= scan_in; + end generate a; + +end tri_nlat_scan; diff --git a/rel/src/vhdl/tri/tri_nor2_nlats.vhdl b/rel/src/vhdl/tri/tri_nor2_nlats.vhdl new file mode 100644 index 0000000..d87ffa0 --- /dev/null +++ b/rel/src/vhdl/tri/tri_nor2_nlats.vhdl @@ -0,0 +1,127 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- *!**************************************************************** +-- *! FILENAME : tri_nor2_nlats.vhdl +-- *! DESCRIPTION : n-bit scannable m/s latch, for bit stacking, with nor2 gate in front +-- *!**************************************************************** + +library ieee; use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library support; + use support.power_logic_pkg.all; +library tri; use tri.tri_latches_pkg.all; +-- pragma translate_off +-- pragma translate_on + +entity tri_nor2_nlats is + + generic ( + offset : natural range 0 to 65535 := 0; + width : positive range 1 to 65536 := 1 ; + init : std_ulogic_vector := "0" ; + synthclonedlatch : string := "" ; + btr : string := "NLO0001_X1_A12TH" ; + needs_sreset : integer := 1 ; -- for inferred latches + expand_type : integer := 1 ); -- 1 = non-ibm, 2 = ibm (MPG) + port ( + vd : inout power_logic; + gd : inout power_logic; + LCLK : in clk_logic; + D1CLK : in std_ulogic; + D2CLK : in std_ulogic; + SCANIN : in std_ulogic_vector(offset to offset+width-1); + SCANOUT : out std_ulogic_vector(offset to offset+width-1); + A1 : in std_ulogic_vector(offset to offset+width-1); + A2 : in std_ulogic_vector(offset to offset+width-1); + QB : out std_ulogic_vector(offset to offset+width-1) + ); + + -- synopsys translate_off + + -- synopsys translate_on + +end entity tri_nor2_nlats; + +architecture tri_nor2_nlats of tri_nor2_nlats is + +begin + + a: if expand_type = 1 generate + constant init_v : std_ulogic_vector(0 to (init'length + width-1)):=init & (0 to width-1=>'0'); + constant zeros : std_ulogic_vector(0 to width-1) := (0 to width-1 => '0'); + + signal sreset : std_ulogic; + signal int_din : std_ulogic_vector(0 to width-1); + signal int_dout : std_ulogic_vector(0 to width-1) := init_v(0 to width-1); + signal vact, vact_b : std_ulogic_vector(0 to width-1); + signal vsreset, vsreset_b : std_ulogic_vector(0 to width-1); + signal vthold, vthold_b : std_ulogic_vector(0 to width-1); + signal din : std_ulogic_vector(0 to width-1); + signal unused : std_ulogic_vector(0 to width-1); + -- synopsys translate_off + -- synopsys translate_on + begin + rst: if needs_sreset = 1 generate + sreset <= LCLK.sreset; + end generate rst; + no_rst: if needs_sreset /=1 generate + sreset <= '0'; + end generate no_rst; + + vsreset <= (0 to width-1 => sreset); + vsreset_b <= (0 to width-1 => not sreset); + din <= A1 or A2 ; -- Output is inverted, so just OR2 here + int_din <= (vsreset_b and din) or + (vsreset and init_v(0 to width-1)); + + vact <= (0 to width-1 => D1CLK); + vact_b <= (0 to width-1 => not D1CLK); + + vthold_b <= (0 to width-1 => D2CLK); + vthold <= (0 to width-1 => not D2CLK); + + l: process (LCLK, vact, int_din, vact_b, int_dout, vsreset, vsreset_b, vthold_b, vthold) + begin + if rising_edge(LCLK.clk) then + int_dout <= (((vact and vthold_b) or vsreset) and int_din) or + (((vact_b or vthold) and vsreset_b) and int_dout); + end if; + end process l; + QB <= not int_dout; + SCANOUT <= zeros; + + unused <= SCANIN; + end generate a; + + --===================================================== + --== non inverting latch with nor2 gate in front + --===================================================== + +end tri_nor2_nlats; diff --git a/rel/src/vhdl/tri/tri_oai22_nlats.vhdl b/rel/src/vhdl/tri/tri_oai22_nlats.vhdl new file mode 100644 index 0000000..a201e32 --- /dev/null +++ b/rel/src/vhdl/tri/tri_oai22_nlats.vhdl @@ -0,0 +1,128 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- *!**************************************************************** +-- *! FILENAME : tri_oai22_nlats.vhdl +-- *! DESCRIPTION : n-bit scannable m/s latch, for bit stacking, with oai22 gate in front +-- *!**************************************************************** + +library ieee; use ieee.std_logic_1164.all; + use ieee.numeric_std.all; +library support; + use support.power_logic_pkg.all; +library tri; use tri.tri_latches_pkg.all; +-- pragma translate_off +-- pragma translate_on + +entity tri_oai22_nlats is + + generic ( + offset : natural range 0 to 65535 := 0; + width : positive range 1 to 65536 := 1 ; + init : std_ulogic_vector := "0" ; + synthclonedlatch : string := "" ; + btr : string := "NLM0001_X1_A12TH" ; + needs_sreset : integer := 1 ; -- for inferred latches + expand_type : integer := 1 ); -- 1 = non-ibm, 2 = ibm (MPG) + port ( + vd : inout power_logic; + gd : inout power_logic; + LCLK : in clk_logic; + D1CLK : in std_ulogic; + D2CLK : in std_ulogic; + SCANIN : in std_ulogic_vector(offset to offset+width-1); + SCANOUT : out std_ulogic_vector(offset to offset+width-1); + A1 : in std_ulogic_vector(offset to offset+width-1); + A2 : in std_ulogic_vector(offset to offset+width-1); + B1 : in std_ulogic_vector(offset to offset+width-1); + B2 : in std_ulogic_vector(offset to offset+width-1); + QB : out std_ulogic_vector(offset to offset+width-1) + ); + + -- synopsys translate_off + + -- synopsys translate_on + +end entity tri_oai22_nlats; + +architecture tri_oai22_nlats of tri_oai22_nlats is + +begin + + a: if expand_type = 1 generate + constant init_v : std_ulogic_vector(0 to (init'length + width-1)):=init & (0 to width-1=>'0'); + constant zeros : std_ulogic_vector(0 to width-1) := (0 to width-1 => '0'); + + signal sreset : std_ulogic; + signal int_din : std_ulogic_vector(0 to width-1); + signal int_dout : std_ulogic_vector(0 to width-1) := init_v(0 to width-1); + signal vact, vact_b : std_ulogic_vector(0 to width-1); + signal vsreset, vsreset_b : std_ulogic_vector(0 to width-1); + signal vthold, vthold_b : std_ulogic_vector(0 to width-1); + signal din : std_ulogic_vector(0 to width-1); + signal unused : std_ulogic_vector(0 to width-1); + -- synopsys translate_off + -- synopsys translate_on + begin + rst: if needs_sreset = 1 generate + sreset <= LCLK.sreset; + end generate rst; + no_rst: if needs_sreset /=1 generate + sreset <= '0'; + end generate no_rst; + + vsreset <= (0 to width-1 => sreset); + vsreset_b <= (0 to width-1 => not sreset); + din <= (A1 or A2) and (B1 or B2) ; -- Output is inverted, so just OR-AND here + int_din <= (vsreset_b and din) or + (vsreset and init_v(0 to width-1)); + + vact <= (0 to width-1 => D1CLK); + vact_b <= (0 to width-1 => not D1CLK); + + vthold_b <= (0 to width-1 => D2CLK); + vthold <= (0 to width-1 => not D2CLK); + + l: process (LCLK, vact, int_din, vact_b, int_dout, vsreset, vsreset_b, vthold_b, vthold) + begin + if rising_edge(LCLK.clk) then + int_dout <= (((vact and vthold_b) or vsreset) and int_din) or + (((vact_b or vthold) and vsreset_b) and int_dout); + end if; + end process l; + QB <= not int_dout; + SCANOUT <= zeros; + + unused <= SCANIN; + end generate a; + + --===================================================== + --== non inverting latch with oai22 gate in front + --===================================================== + +end tri_oai22_nlats; diff --git a/rel/src/vhdl/tri/tri_plat.vhdl b/rel/src/vhdl/tri/tri_plat.vhdl new file mode 100644 index 0000000..78da763 --- /dev/null +++ b/rel/src/vhdl/tri/tri_plat.vhdl @@ -0,0 +1,102 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- *!**************************************************************** +-- *! FILENAME : tri_plat.vhdl +-- *! DESCRIPTION : Non-scannable pipeline latch +-- *!**************************************************************** + +library ieee; use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library support; + use support.power_logic_pkg.all; +library tri; use tri.tri_latches_pkg.all; +-- pragma translate_off +-- pragma translate_on + +entity tri_plat is + + generic ( + width : positive range 1 to 65536 := 1 ; + offset : natural range 0 to 65535 := 0 ; + init : integer := 0; -- will be converted to the least signficant 31 bits of init_v + synthclonedlatch : string := "" ; + flushlat : boolean := true ; + expand_type : integer := 1 ); -- 1 = non-ibm, 2 = ibm (MPG) + + port ( + vd : inout power_logic; + gd : inout power_logic; + nclk : in clk_logic; + flush : in std_ulogic; + din : in std_ulogic_vector(offset to offset+width-1); + q : out std_ulogic_vector(offset to offset+width-1) ); + + -- synopsys translate_off + + -- synopsys translate_on + +end entity tri_plat; + +architecture tri_plat of tri_plat is + + constant init_v : std_ulogic_vector(0 to width-1) := std_ulogic_vector( to_unsigned( init, width ) ); + +begin -- tri_plat + + a: if expand_type /= 2 generate + signal int_din : std_ulogic_vector(0 to width-1); + signal int_dout : std_ulogic_vector(0 to width-1) := init_v; + signal vsreset, vsreset_b : std_ulogic_vector(0 to width-1); + begin + + vsreset <= (0 to width-1 => nclk.sreset); + vsreset_b <= (0 to width-1 => not nclk.sreset); + + int_din <= (vsreset_b and din) or + (vsreset and init_v); + + l: process (nclk, int_din, flush, din) + begin + + if rising_edge(nclk.clk) then + int_dout <= int_din; + end if; + + if (flush = '1') then + int_dout <= din; + end if; + + end process l; + + q <= int_dout; + + end generate a; + +end tri_plat; diff --git a/rel/src/vhdl/tri/tri_psro_soft.vhdl b/rel/src/vhdl/tri/tri_psro_soft.vhdl new file mode 100644 index 0000000..4c3507d --- /dev/null +++ b/rel/src/vhdl/tri/tri_psro_soft.vhdl @@ -0,0 +1,56 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee; +use ieee.std_logic_1164.all ; +library ibm; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +library support; +use support.power_logic_pkg.all; + + +entity tri_psro_soft is + port ( + vdd : inout power_logic; -- Local Voltage Grid + gnd : inout power_logic; -- Local Gnd + psro_enable : in std_ulogic_vector(0 to 2); -- From pervasive + psro_ringsig : out std_ulogic -- These need to be triple buffered + ); + +-- synopsys translate_off +-- synopsys translate_on +end tri_psro_soft; + + +architecture tri_psro_soft of tri_psro_soft is +begin + + psro_ringsig <= or_reduce(psro_enable(0 to 2)); + +end tri_psro_soft; diff --git a/rel/src/vhdl/tri/tri_regk.vhdl b/rel/src/vhdl/tri/tri_regk.vhdl new file mode 100644 index 0000000..071128c --- /dev/null +++ b/rel/src/vhdl/tri/tri_regk.vhdl @@ -0,0 +1,120 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- *!**************************************************************** +-- *! FILENAME : tri_regk.vhdl +-- *! DESCRIPTION : Multi-bit non-scannable latch, LCB included +-- *!**************************************************************** + +library ieee; use ieee.std_logic_1164.all; + use ieee.numeric_std.all; +library support; + use support.power_logic_pkg.all; +library tri; use tri.tri_latches_pkg.all; +-- pragma translate_off +-- pragma translate_on + +entity tri_regk is + generic ( + width : integer := 4; + offset : integer range 0 to 65535 := 0 ; --starting bit + init : integer := 0; -- will be converted to the least signficant + -- 31 bits of init_v + synthclonedlatch : string := ""; + needs_sreset : integer := 1 ; -- for inferred latches + expand_type : integer := 1 ); -- 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) + + port ( + vd : inout power_logic; + gd : inout power_logic; + nclk : in clk_logic; + act : in std_ulogic := '1'; -- 1: functional, 0: no clock + forcee : in std_ulogic := '0'; -- 1: force LCB active + thold_b : in std_ulogic := '1'; -- 1: functional, 0: no clock + d_mode : in std_ulogic := '0'; -- 1: disable pulse mode, 0: pulse mode + delay_lclkr : in std_ulogic := '0'; -- 0: functional + mpw1_b : in std_ulogic := '1'; -- pulse width control bit + mpw2_b : in std_ulogic := '1'; -- pulse width control bit + din : in std_ulogic_vector(offset to offset+width-1); -- data in + dout : out std_ulogic_vector(offset to offset+width-1) ); + + -- synopsys translate_off + + -- synopsys translate_on + +end entity tri_regk; + +architecture tri_regk of tri_regk is + + constant init_v : std_ulogic_vector(0 to width-1) := std_ulogic_vector( to_unsigned( init, width ) ); + constant zeros : std_ulogic_vector(0 to width-1) := (0 to width-1 => '0'); + +begin -- tri_regk + + a: if expand_type = 1 generate + signal sreset : std_ulogic; + signal int_din : std_ulogic_vector(0 to width-1); + signal int_dout : std_ulogic_vector(0 to width-1) := init_v; + signal vact, vact_b : std_ulogic_vector(0 to width-1); + signal vsreset, vsreset_b : std_ulogic_vector(0 to width-1); + signal vthold, vthold_b : std_ulogic_vector(0 to width-1); + signal unused : std_ulogic; + -- synopsys translate_off + -- synopsys translate_on + begin + rst: if needs_sreset = 1 generate + sreset <= nclk.sreset; + end generate rst; + no_rst: if needs_sreset /=1 generate + sreset <= '0'; + end generate no_rst; + + vsreset <= (0 to width-1 => sreset); + vsreset_b <= (0 to width-1 => not sreset); + int_din <= (vsreset_b and din) or + (vsreset and init_v); + + vact <= (0 to width-1 => (act or forcee)); + vact_b <= (0 to width-1 => not (act or forcee)); + + vthold_b <= (0 to width-1 => thold_b); + vthold <= (0 to width-1 => not thold_b); + + l: process (nclk, vact, int_din, vact_b, int_dout, vsreset, vsreset_b, vthold_b, vthold) + begin + if rising_edge(nclk.clk) then + int_dout <= (((vact and vthold_b) or vsreset) and int_din) or + (((vact_b or vthold) and vsreset_b) and int_dout); + end if; + end process l; + dout <= int_dout; + + unused <= d_mode or delay_lclkr or mpw1_b or mpw2_b; + end generate a; + +end tri_regk; diff --git a/rel/src/vhdl/tri/tri_regs.vhdl b/rel/src/vhdl/tri/tri_regs.vhdl new file mode 100644 index 0000000..ed69b59 --- /dev/null +++ b/rel/src/vhdl/tri/tri_regs.vhdl @@ -0,0 +1,131 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- *!**************************************************************** +-- *! FILENAME : tri_regs.vhdl +-- *! DESCRIPTION : Multi-bit scan-only latch, LCB included +-- *!**************************************************************** + +library ieee; use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library support; + use support.power_logic_pkg.all; +library tri; use tri.tri_latches_pkg.all; +-- pragma translate_off +-- pragma translate_on + +entity tri_regs is + + generic ( + width : integer := 4; + offset : integer range 0 to 65535 := 0 ; --starting bit + init : integer := 0; -- will be converted to the least signficant + -- 31 bits of init_v + ibuf : boolean := false; --inverted latch IOs, if set to true. + dualscan : string := ""; -- if "S", marks data ports as scan for Moebius + needs_sreset: integer := 1 ; -- for inferred latches + expand_type : integer := 1 );-- 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) + + port ( + vd : inout power_logic; + gd : inout power_logic; + nclk : in clk_logic; + forcee : in std_ulogic := '0'; -- 1: force LCB active + thold_b : in std_ulogic := '1'; -- 1: functional, 0: no clock + delay_lclkr : in std_ulogic := '0'; -- 0: functional + scin : in std_ulogic_vector(offset to offset+width-1); -- scan in + scout : out std_ulogic_vector(offset to offset+width-1); + dout : out std_ulogic_vector(offset to offset+width-1) ); + + -- synopsys translate_off + + -- synopsys translate_on + +end entity tri_regs; + +architecture tri_regs of tri_regs is + + constant init_v : std_ulogic_vector(0 to width-1) := std_ulogic_vector( to_unsigned( init, width ) ); + constant zeros : std_ulogic_vector(0 to width-1) := (0 to width-1 => '0'); + +begin -- tri_regs + + a: if expand_type = 1 generate + signal sreset : std_ulogic; + signal int_din : std_ulogic_vector(0 to width-1); + signal int_dout : std_ulogic_vector(0 to width-1) := init_v; + signal vact, vact_b : std_ulogic_vector(0 to width-1); + signal vsreset, vsreset_b : std_ulogic_vector(0 to width-1); + signal vthold, vthold_b : std_ulogic_vector(0 to width-1); + signal unused : std_ulogic_vector(0 to width); + -- synopsys translate_off + -- synopsys translate_on + begin + rst: if needs_sreset = 1 generate + sreset <= nclk.sreset; + end generate rst; + no_rst: if needs_sreset /=1 generate + sreset <= '0'; + end generate no_rst; + + vsreset <= (0 to width-1 => sreset); + vsreset_b <= (0 to width-1 => not sreset); + + int_din <= (vsreset_b and int_dout) or + (vsreset and init_v); + + vact <= (0 to width-1 => forcee); + vact_b <= (0 to width-1 => not forcee); + + vthold_b <= (0 to width-1 => thold_b); + vthold <= (0 to width-1 => not thold_b); + + l: process (nclk, vact, int_din, vact_b, int_dout, vsreset, vsreset_b, vthold_b, vthold) + begin + if rising_edge(nclk.clk) then + int_dout <= (((vact and vthold_b) or vsreset) and int_din) or + (((vact_b or vthold) and vsreset_b) and int_dout); + end if; + end process l; + + cob: if ibuf = true generate + dout <= not int_dout; + end generate cob; + + cnob: if ibuf = false generate + dout <= int_dout; + end generate cnob; + + scout <= zeros; + + unused(0) <= delay_lclkr; + unused(1 to width) <= scin; + end generate a; + +end tri_regs; diff --git a/rel/src/vhdl/tri/tri_rlmlatch_p.vhdl b/rel/src/vhdl/tri/tri_rlmlatch_p.vhdl new file mode 100644 index 0000000..7ce45ab --- /dev/null +++ b/rel/src/vhdl/tri/tri_rlmlatch_p.vhdl @@ -0,0 +1,184 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- *!**************************************************************** +-- *! FILENAME : tri_rlmlatch_p.vhdl +-- *! DESCRIPTION : 1-bit latch, LCB included +-- *!**************************************************************** + +library ieee; use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library support; + use support.power_logic_pkg.all; +library tri; use tri.tri_latches_pkg.all; +-- pragma translate_off +-- pragma translate_on + +entity tri_rlmlatch_p is + + generic ( + init : integer := 0; -- will be converted to the least signficant + -- 31 bits of init_v + ibuf : boolean := false; --inverted latch IOs, if set to true. + dualscan : string := ""; -- if "S", marks data ports as scan for Moebius + needs_sreset: integer := 1 ; -- for inferred latches + expand_type : integer := 1 );-- 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) + + port ( + vd : inout power_logic; + gd : inout power_logic; + nclk : in clk_logic; + act : in std_ulogic := '1'; -- 1: functional, 0: no clock + forcee : in std_ulogic := '0'; -- 1: force LCB active + thold_b : in std_ulogic := '1'; -- 1: functional, 0: no clock + d_mode : in std_ulogic := '0'; -- 1: disable pulse mode, 0: pulse mode + sg : in std_ulogic := '0'; -- 0: functional, 1: scan + delay_lclkr : in std_ulogic := '0'; -- 0: functional + mpw1_b : in std_ulogic := '1'; -- pulse width control bit + mpw2_b : in std_ulogic := '1'; -- pulse width control bit + scin : in std_ulogic := '0'; -- scan in + din : in std_ulogic; -- data in + scout : out std_ulogic; -- scan out + dout : out std_ulogic); -- data out + + -- synopsys translate_off + + -- synopsys translate_on + +end entity tri_rlmlatch_p; + +architecture tri_rlmlatch_p of tri_rlmlatch_p is + + constant width : integer := 1; + constant offset : natural := 0; + constant init_v : std_ulogic_vector(0 to width-1) := std_ulogic_vector( to_unsigned( init, width ) ); + constant zeros : std_ulogic_vector(0 to width-1) := (0 to width-1 => '0'); + +begin -- tri_rlmlatch_p + + -- synopsys translate_off + um: if expand_type = 0 generate + component c_rlmreg_p + generic ( width : positive := 4 ; --bit width value + init : std_ulogic_vector := "0"; --latch initialization + dualscan : string := "" -- if "S", marks data ports as scan for Moebius + ); + port ( + nclk : in std_ulogic; -- chip global clock signal + act : in std_ulogic; -- 1: functional, 0: no clock + thold_b : in std_ulogic; -- 1: functional, 0: stop the clock. + sg : in std_ulogic; -- 0: functional, 1: scan + scin : in std_ulogic_vector(0 to width-1); -- scan in + din : in std_ulogic_vector(0 to width-1); -- data in + dout : out std_ulogic_vector(0 to width-1); -- data out + scout : out std_ulogic_vector(0 to width-1) -- scan out + ); + end component; + signal scanin_inv : std_ulogic; + signal scanout_inv : std_ulogic; + signal act_or_force : std_ulogic; + signal din_buf : std_ulogic; + signal dout_buf : std_ulogic; + begin + act_or_force <= act or forcee; + + cib: --insert inverters at latch IO if ibuf=true + if ibuf = true generate + din_buf <= not din; + dout <= not dout_buf; + end generate cib; + cnib: -- no inverters at latch IO if ibuf=false (default) + if ibuf = false generate + din_buf <= din; + dout <= dout_buf; + end generate cnib; + + l:c_rlmreg_p + generic map (width => width, init => init_v, dualscan => dualscan) + port map ( + nclk => nclk.clk, + act => act_or_force, + thold_b => thold_b, + sg => sg, + scin(0) => scanin_inv, + din(0) => din_buf, + scout(0) => scanout_inv, + dout(0) => dout_buf); + + scanin_inv <= scin xor init_v(0); + scout <= scanout_inv xor init_v(0); + end generate um; + -- synopsys translate_on + + a: if expand_type = 1 generate + signal sreset : std_ulogic; + signal int_din : std_ulogic; + signal int_dout : std_ulogic := init_v(0); + signal unused : std_ulogic; + -- synopsys translate_off + -- synopsys translate_on + begin + rst: if needs_sreset = 1 generate + sreset <= nclk.sreset; + end generate rst; + no_rst: if needs_sreset /=1 generate + sreset <= '0'; + end generate no_rst; + + cib: if ibuf = true generate + int_din <= (not sreset and not din) or + (sreset and init_v(0)); + end generate cib; + cnib: if ibuf = false generate + int_din <= (not sreset and din) or + (sreset and init_v(0)); + end generate cnib; + + l: process (nclk, act, forcee, int_din, int_dout, sreset, thold_b) + begin + if rising_edge(nclk.clk) then + int_dout <= ( (((act or forcee) and thold_b) or sreset ) and int_din ) or + ( ((not act and not forcee) or not thold_b) and not sreset and int_dout); + end if; + end process l; + + cob: if ibuf = true generate + dout <= not int_dout; + end generate cob; + + cnob: if ibuf = false generate + dout <= int_dout; + end generate cnob; + + scout <= zeros(0); + + unused <= d_mode or sg or delay_lclkr or mpw1_b or mpw2_b or scin; + end generate a; + +end tri_rlmlatch_p; diff --git a/rel/src/vhdl/tri/tri_rlmreg_p.vhdl b/rel/src/vhdl/tri/tri_rlmreg_p.vhdl new file mode 100644 index 0000000..a16240f --- /dev/null +++ b/rel/src/vhdl/tri/tri_rlmreg_p.vhdl @@ -0,0 +1,195 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- *!**************************************************************** +-- *! FILENAME : tri_rlmreg_p.vhdl +-- *! DESCRIPTION : Multi-bit latch, LCB included +-- *!**************************************************************** + +library ieee; use ieee.std_logic_1164.all; + use ieee.numeric_std.all; +library support; use support.power_logic_pkg.all; +library tri; use tri.tri_latches_pkg.all; +-- pragma translate_off +-- pragma translate_on + +entity tri_rlmreg_p is + + generic ( + width : integer := 4; + offset : integer range 0 to 65535 := 0 ; --starting bit + init : integer := 0; -- will be converted to the least signficant + -- 31 bits of init_v + ibuf : boolean := false; --inverted latch IOs, if set to true. + dualscan : string := ""; -- if "S", marks data ports as scan for Moebius + needs_sreset: integer := 1 ; -- for inferred latches + expand_type : integer := 1 );-- 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) + + port ( + vd : inout power_logic; + gd : inout power_logic; + nclk : in clk_logic; + act : in std_ulogic := '1'; -- 1: functional, 0: no clock + forcee : in std_ulogic := '0'; -- 1: force LCB active + thold_b : in std_ulogic := '1'; -- 1: functional, 0: no clock + d_mode : in std_ulogic := '0'; -- 1: disable pulse mode, 0: pulse mode + sg : in std_ulogic := '0'; -- 0: functional, 1: scan + delay_lclkr : in std_ulogic := '0'; -- 0: functional + mpw1_b : in std_ulogic := '1'; -- pulse width control bit + mpw2_b : in std_ulogic := '1'; -- pulse width control bit + scin : in std_ulogic_vector(offset to offset+width-1); -- scan in + din : in std_ulogic_vector(offset to offset+width-1); -- data in + scout : out std_ulogic_vector(offset to offset+width-1); + dout : out std_ulogic_vector(offset to offset+width-1) ); + + -- synopsys translate_off + + -- synopsys translate_on + +end entity tri_rlmreg_p; + +architecture tri_rlmreg_p of tri_rlmreg_p is + + constant init_v : std_ulogic_vector(0 to width-1) := std_ulogic_vector( to_unsigned( init, width ) ); + constant zeros : std_ulogic_vector(0 to width-1) := (0 to width-1 => '0'); + +begin -- tri_rlmreg_p + + -- synopsys translate_off + um: if expand_type = 0 generate + component c_rlmreg_p + generic ( width : positive := 4 ; --bit width value + init : std_ulogic_vector := "0"; --latch initialization + dualscan : string := "" -- if "S", marks data ports as scan for Moebius + ); + port ( + nclk : in std_ulogic; -- chip global clock signal + act : in std_ulogic; -- 1: functional, 0: no clock + thold_b : in std_ulogic; -- 1: functional, 0: stop the clock. + sg : in std_ulogic; -- 0: functional, 1: scan + scin : in std_ulogic_vector(0 to width-1); -- scan in + din : in std_ulogic_vector(0 to width-1); -- data in + dout : out std_ulogic_vector(0 to width-1); -- data out + scout : out std_ulogic_vector(0 to width-1) -- scan out + ); + end component; + signal scanin_inv : std_ulogic_vector(0 to width-1); + signal scanout_inv : std_ulogic_vector(0 to width-1); + signal act_or_force : std_ulogic; + signal din_buf : std_ulogic_vector(0 to width-1); + signal dout_buf : std_ulogic_vector(0 to width-1); + begin + act_or_force <= act or forcee; + + cib: --insert inverters at latch IO if ibuf=true + if ibuf = true generate + din_buf <= not din; + dout <= not dout_buf; + end generate cib; + cnib: -- no inverters at latch IO if ibuf=false (default) + if ibuf = false generate + din_buf <= din; + dout <= dout_buf; + end generate cnib; + + l:c_rlmreg_p + generic map (width => width, init => init_v, dualscan => dualscan) + port map ( + nclk => nclk.clk, + act => act_or_force, + thold_b => thold_b, + sg => sg, + scin => scanin_inv, + din => din_buf, + scout => scanout_inv, + dout => dout_buf); + + scanin_inv <= scin xor init_v; + scout <= scanout_inv xor init_v; + end generate um; + -- synopsys translate_on + + a: if expand_type = 1 generate + signal sreset : std_ulogic; + signal int_din : std_ulogic_vector(0 to width-1); + signal int_dout : std_ulogic_vector(0 to width-1) := init_v; + signal vact, vact_b : std_ulogic_vector(0 to width-1); + signal vsreset, vsreset_b : std_ulogic_vector(0 to width-1); + signal vthold, vthold_b : std_ulogic_vector(0 to width-1); + signal unused : std_ulogic_vector(0 to width); + -- synopsys translate_off + -- synopsys translate_on + begin + rst: if needs_sreset = 1 generate + sreset <= nclk.sreset; + end generate rst; + no_rst: if needs_sreset /=1 generate + sreset <= '0'; + end generate no_rst; + + vsreset <= (0 to width-1 => sreset); + vsreset_b <= (0 to width-1 => not sreset); + + cib: if ibuf = true generate + int_din <= (vsreset_b and not din) or + (vsreset and init_v); + end generate cib; + cnib: if ibuf = false generate + int_din <= (vsreset_b and din) or + (vsreset and init_v); + end generate cnib; + + vact <= (0 to width-1 => (act or forcee)); + vact_b <= (0 to width-1 => not (act or forcee)); + + vthold_b <= (0 to width-1 => thold_b); + vthold <= (0 to width-1 => not thold_b); + + l: process (nclk, vact, int_din, vact_b, int_dout, vsreset, vsreset_b, vthold_b, vthold) + begin + if rising_edge(nclk.clk) then + int_dout <= (((vact and vthold_b) or vsreset) and int_din) or + (((vact_b or vthold) and vsreset_b) and int_dout); + end if; + end process l; + + cob: if ibuf = true generate + dout <= not int_dout; + end generate cob; + + cnob: if ibuf = false generate + dout <= int_dout; + end generate cnob; + + scout <= zeros; + + unused(0) <= d_mode or sg or delay_lclkr or mpw1_b or mpw2_b; + unused(1 to width) <= scin; + end generate a; + +end tri_rlmreg_p; diff --git a/rel/src/vhdl/tri/tri_ser_rlmreg_p.vhdl b/rel/src/vhdl/tri/tri_ser_rlmreg_p.vhdl new file mode 100644 index 0000000..9748c7f --- /dev/null +++ b/rel/src/vhdl/tri/tri_ser_rlmreg_p.vhdl @@ -0,0 +1,100 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee,support,tri; +use ieee.std_logic_1164.all; +use support.power_logic_pkg.all; +use tri.tri_latches_pkg.all; + +entity tri_ser_rlmreg_p is +generic ( + width : positive range 1 to 65536 := 1 ; + offset : natural range 0 to 65535 := 0 ; + init : integer := 0; + ibuf : boolean := false; + dualscan : string := ""; + needs_sreset : integer := 1 ; + expand_type : integer := 1 ); +port ( + vd : inout power_logic; + gd : inout power_logic; + nclk : in clk_logic; + act : in std_ulogic := '1'; + forcee : in std_ulogic := '0'; + thold_b : in std_ulogic := '1'; + d_mode : in std_ulogic := '0'; + sg : in std_ulogic := '0'; + delay_lclkr : in std_ulogic := '0'; + mpw1_b : in std_ulogic := '1'; + mpw2_b : in std_ulogic := '1'; + scin : in std_ulogic_vector(offset to offset+width-1); + din : in std_ulogic_vector(offset to offset+width-1); + scout : out std_ulogic_vector(offset to offset+width-1); + dout : out std_ulogic_vector(offset to offset+width-1)); + + -- synopsys translate_off + -- synopsys translate_on + +end entity tri_ser_rlmreg_p; + +architecture tri_ser_rlmreg_p of tri_ser_rlmreg_p is + +signal dout_b, act_buf, act_buf_b, dout_buf : std_ulogic_vector(offset to offset+width-1); + +begin + +act_buf <= (others=>act); +act_buf_b <= (others=>not(act)); +dout_buf <= not dout_b; +dout <= dout_buf; + +tri_ser_rlmreg_p : entity tri.tri_aoi22_nlats_wlcb(tri_aoi22_nlats_wlcb) + generic map ( + width => width, + offset => offset, + init => init, + ibuf => ibuf, + dualscan=> dualscan, + expand_type => expand_type, + needs_sreset => needs_sreset) + port map (nclk => nclk, vd => vd, gd => gd, + act => act, + forcee => forcee, + d_mode => d_mode, delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, mpw2_b => mpw2_b, + thold_b => thold_b, + sg => sg, + scin => scin, + scout => scout, + A1 => din, + A2 => act_buf, + B1 => dout_buf, + B2 => act_buf_b, + QB => dout_b); + +end tri_ser_rlmreg_p; diff --git a/rel/src/vhdl/tri/tri_serial_scom2.vhdl b/rel/src/vhdl/tri/tri_serial_scom2.vhdl new file mode 100644 index 0000000..018e6f8 --- /dev/null +++ b/rel/src/vhdl/tri/tri_serial_scom2.vhdl @@ -0,0 +1,1065 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- *!**************************************************************** +-- *! FILENAME : tri_serial_scom2.vhdl +-- *! DESCRIPTION : SCOM Satellite +-- *! Only supports 1:1 ratio +-- *!**************************************************************** + +library ieee; use ieee.std_logic_1164.all; + use ieee.numeric_std.all; +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_unsigned.all; +library support; + use support.power_logic_pkg.all; +library tri; use tri.tri_latches_pkg.all; + +entity tri_serial_scom2 is + + generic ( + width : positive := 64; -- 64 is the maximum allowed + internal_addr_decode: boolean := false; + use_addr : std_ulogic_vector := "1000000000000000000000000000000000000000000000000000000000000000"; + addr_is_rdable : std_ulogic_vector := "1000000000000000000000000000000000000000000000000000000000000000"; + addr_is_wrable : std_ulogic_vector := "1000000000000000000000000000000000000000000000000000000000000000"; + pipeline_addr_v : std_ulogic_vector := "0000000000000000000000000000000000000000000000000000000000000000"; + pipeline_paritychk : boolean := false; -- pipeline parcheck for timing + satid_nobits : positive := 4; -- should not be set by user + regid_nobits : positive := 6; + ringid_nobits : positive := 3; + expand_type : integer := 1 ); -- 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) + + port ( + -- clock, scan and misc interfaces + nclk : in clk_logic; + vd : inout power_logic; + gd : inout power_logic; + scom_func_thold : in std_ulogic; + sg : in std_ulogic; + act_dis_dc : in std_ulogic; + clkoff_dc_b : in std_ulogic; + mpw1_dc_b : in std_ulogic; + mpw2_dc_b : in std_ulogic; + d_mode_dc : in std_ulogic; + delay_lclkr_dc : in std_ulogic; + + --! scan chain should evaluate to 0:176 for WIDTH=64 and 6 regid_nobits (=64 SCOM addresses) + --! scan chain vector is longer than number of latches being used + --! scan chain should evaluate to 0:176 for WIDTH=64 and 6 regid_nobits (=64 SCOM addresses) + --! scan chain vector is longer than number of latches being used + --! due to vhdl generics formulation and shortings + func_scan_in : in std_ulogic_vector(0 to + (((width+15)/16)*16)+2*(((((width+15)/16)*16)-1)/16+1)+(2**regid_nobits)+40 ); + -- | | + -- data_shifter + -- | par_nobits | + func_scan_out : out std_ulogic_vector(0 to + (((width+15)/16)*16)+2*(((((width+15)/16)*16)-1)/16+1)+(2**regid_nobits)+40 ); + + + -- for mask slat inside of c_err_rpt + dcfg_scan_dclk : in std_ulogic; + dcfg_scan_lclk : in clk_logic; + + --! for nlats inside of c_err_rpt + dcfg_d1clk : in std_ulogic; -- needed for one bit only, always or scom_local_act clocked dcfg + dcfg_d2clk : in std_ulogic; -- needed for one bit only, always or scom_local_act clocked dcfg + dcfg_lclk : in clk_logic; -- needed for one bit only, always or scom_local_act clocked dcfg + + -- contains mask slat and hold nlat of c_err_rpt + dcfg_scan_in : in std_ulogic_vector(0 to 1); + dcfg_scan_out : out std_ulogic_vector(0 to 1); + + -- denotes SCOM sat active if set to '1', can be used for local clock gating + scom_local_act : out std_ulogic; + + ----------------------------------------------------------------------- + -- SCOM Interface + ----------------------------------------------------------------------- + -- SCOM satellite ID tied to a specific pattern + sat_id : in std_ulogic_vector(0 to satid_nobits-1); + + -- SCOM Data Channel input (carry both address and data) + scom_dch_in : in std_ulogic; + + -- SCOM Control Channel input + scom_cch_in : in std_ulogic; + + -- SCOM Data Channel output + scom_dch_out : out std_ulogic; + + -- SCOM Control Channel output + scom_cch_out : out std_ulogic; + + ----------------------------------------------------------------------- + -- Interface between SCOM satellite and internal macro logic + ----------------------------------------------------------------------- + -- denotes a request if asserted to '1', level + sc_req : out std_ulogic; + + -- acknowledge a pending request with sc_ack_info+sc_rdata+sc_rparity + -- being valid + sc_ack : in std_ulogic; + + -- acknowledge information + -- 0: '1' if access violation, otherwise '0' + -- 1: '1' if register address invalid + sc_ack_info : in std_ulogic_vector(0 to 1); + + -- '1' if read access, '0' write access + sc_r_nw : out std_ulogic; + + -- Register address, default 6 bits for up to 64 register addresses + sc_addr : out std_ulogic_vector(0 to regid_nobits-1); + + -- one-hot address, valid only if INTERNAL_ADDR_DECODE=TRUE, else zeros + addr_v : out std_ulogic_vector(0 to use_addr'high); + + -- Read data delivered by macro logic as response to a read request + sc_rdata : in std_ulogic_vector(0 to width-1); + + -- Write data delivered from SCOM satellite for a write request + sc_wdata : out std_ulogic_vector(0 to width-1); + + -- Write data parity bit over sc_wdata, optional usage + sc_wparity : out std_ulogic; + + ----------------------------------------------------------------------- + -- parity error of fsm state vector, wire to next local fir + scom_err : out std_ulogic; + + -- reset fsm (optional), tie to '0' if unused + fsm_reset : in std_ulogic + + ); + -- synopsys translate_off + + -- synopsys translate_on + +end tri_serial_scom2; + +architecture tri_serial_scom2 of tri_serial_scom2 is + +begin -- tri_serial_scom2 + + a: if expand_type /= 2 generate + constant state_width : positive := 5 ; + constant i_width : positive := (((width+15)/16)*16); -- width adjusted to 16-bit boundary + constant par_nobits : positive := (i_width-1)/16+1; + constant reg_nobits : positive := regid_nobits; -- 6 + constant satid_regid_nobits : positive := satid_nobits + regid_nobits; -- 4 + 6 = 10 + constant rw_bit_index : positive := satid_regid_nobits + 1; -- 11 + constant parbit_index : positive := rw_bit_index + 1; -- 12 + constant head_width : positive := parbit_index + 1; + constant head_init : std_ulogic_vector( 0 to head_width-1) := "0000000000000"; + + --0123Parity + constant idle : std_ulogic_vector(0 to state_width-1) := "00000"; -- 0 = x00 + constant rec_head : std_ulogic_vector(0 to state_width-1) := "00011"; -- 1 = x03 + constant check_before : std_ulogic_vector(0 to state_width-1) := "00101"; -- 2 = x05 + constant rec_wdata : std_ulogic_vector(0 to state_width-1) := "00110"; -- 3 = x06 + constant rec_wpar : std_ulogic_vector(0 to state_width-1) := "01001"; -- 4 = x09 + constant exe_cmd : std_ulogic_vector(0 to state_width-1) := "01010"; -- 5 = x0A + constant filler0 : std_ulogic_vector(0 to state_width-1) := "01100"; -- 6 = x0C + constant filler1 : std_ulogic_vector(0 to state_width-1) := "01111"; -- 7 = x0F + constant gen_ulinfo : std_ulogic_vector(0 to state_width-1) := "10001"; -- 8 = x11 + constant send_ulinfo : std_ulogic_vector(0 to state_width-1) := "10010"; -- 9 = x12 + constant send_rdata : std_ulogic_vector(0 to state_width-1) := "10100"; -- 10 = x14 + constant send_0 : std_ulogic_vector(0 to state_width-1) := "10111"; -- 11 = x17 + constant send_1 : std_ulogic_vector(0 to state_width-1) := "11000"; -- 12 = x18 + constant check_wpar : std_ulogic_vector(0 to state_width-1) := "11011"; -- 13 = x1B + -- 14 = x1D + constant not_selected : std_ulogic_vector(0 to state_width-1) := "11110"; -- 15 = x1E + + constant eof_wdata : positive := parbit_index-1+64; -- here max width, it is 64 + constant eof_wpar : positive := eof_wdata + 4; + + constant eof_wdata_n : positive := parbit_index-1+ i_width; + constant eof_wpar_m : positive := eof_wdata + par_nobits; + + + signal is_idle : std_ulogic; + signal is_rec_head : std_ulogic; + signal is_check_before: std_ulogic; + signal is_rec_wdata : std_ulogic; + signal is_rec_wpar : std_ulogic; + signal is_exe_cmd : std_ulogic; + signal is_gen_ulinfo : std_ulogic; + signal is_send_ulinfo : std_ulogic; + signal is_send_rdata : std_ulogic; + signal is_send_0 : std_ulogic; + signal is_send_1 : std_ulogic; + signal is_filler_0 : std_ulogic; + signal is_filler_1 : std_ulogic; + + signal next_state, state_in, state_lt : std_ulogic_vector(0 to state_width-1); + + signal dch_lt : std_ulogic; + signal cch_in, cch_lt : std_ulogic_vector(0 to 1); + + signal reset : std_ulogic; + signal got_head, gor_eofwdata, got_eofwpar, sent_rdata, got_ulhead, do_send_par + ,cntgtheadpluswidth, cntgteofwdataplusparity : std_ulogic; + signal p0_err, any_ack_error, match : std_ulogic; + signal p0_err_in, p0_err_lt : std_ulogic; + signal do_write, do_read : std_ulogic; + signal enable_cnt : std_ulogic; + signal cnt_in, cnt_lt : std_ulogic_vector(0 to 6); + signal head_in, head_lt : std_ulogic_vector(0 to head_width-1); + signal tail_in, tail_lt : std_ulogic_vector(0 to 4); + signal sc_ack_info_in, sc_ack_info_lt : std_ulogic_vector(0 to 1); + signal head_mux : std_ulogic; + + signal data_shifter_in, data_shifter_lt : std_ulogic_vector(0 to i_width-1); + signal data_shifter_lt_tmp : std_ulogic_vector(0 to 63); + + signal datapar_shifter_in, datapar_shifter_lt : std_ulogic_vector(0 to par_nobits-1); + signal data_mux, par_mux : std_ulogic; + signal dch_out_internal_in, dch_out_internal_lt : std_ulogic; + signal parity_satid_regaddr_in : std_ulogic; + signal parity_satid_regaddr_lt : std_ulogic; + signal func_force : std_ulogic; + signal func_thold_b, d1clk, d2clk : std_ulogic; + signal lclk : clk_logic; + signal local_act, local_act_int : std_ulogic; + signal scom_err_in, scom_err_lt : std_ulogic; + signal scom_local_act_in, scom_local_act_lt : std_ulogic; + + signal wpar_err : std_ulogic; + signal wpar_err_in, wpar_err_lt : std_ulogic; + signal par_data_in, par_data_lt : std_ulogic_vector(0 to par_nobits-1); + signal sc_rparity : std_ulogic_vector(0 to par_nobits-1); + + signal read_valid, write_valid : std_ulogic; + signal dec_addr_in, dec_addr_q : std_ulogic_vector(use_addr'range); + signal addr_nvld : std_ulogic; + signal write_nvld, read_nvld : std_ulogic; + signal state_par_error : std_ulogic; + signal sat_id_net : std_ulogic_vector(0 to satid_nobits-1); + + signal unused : std_ulogic_vector(0 to 1); + + -- signal renaming and mapping to make it visible internally for debug + signal scom_cch_in_int : std_ulogic; + signal scom_dch_in_int : std_ulogic; + signal scom_cch_input_in, scom_cch_input_lt : std_ulogic; + signal scom_dch_input_in, scom_dch_input_lt : std_ulogic; + + + signal func_scan_temp : std_ulogic; + signal func_scan_temp_1 : std_ulogic; + signal func_scan_temp_2 : std_ulogic; + signal func_scan_temp_3 : std_ulogic; + signal func_scan_temp_4 : std_ulogic; + + signal spare_latch1_in, spare_latch1_lt : std_ulogic; + signal spare_latch2_in, spare_latch2_lt : std_ulogic; + + signal unused_signals : std_ulogic; + + + + begin + assert (or_reduce(use_addr)='1') + report "pcb if component must use at least one address, generic use_addr is all zeroes" + severity error; + + assert (use_addr'length<=2**reg_nobits) + report "use_addr is larger than 2^reg_nobits" + severity error; + + + assert (i_width > 0) + report "has to be in the range of 1..64" + severity error; + + assert (i_width < 65) + report "has to be in the range of 1..64" + severity error; + + + + lcbor_func: entity tri.tri_lcbor(tri_lcbor) + generic map ( expand_type => expand_type ) + port map ( + clkoff_b => clkoff_dc_b, + thold => scom_func_thold, + sg => sg, + act_dis => act_dis_dc, + forcee => func_force, + thold_b => func_thold_b ); + + + lcb_func: entity tri.tri_lcbnd(tri_lcbnd) + generic map ( expand_type => expand_type ) + port map ( + vd => vd, + gd => gd, + act => local_act_int, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + nclk => nclk, + forcee => func_force, + sg => sg, + thold_b => func_thold_b, + ---------------------------- + d1clk => d1clk, + d2clk => d2clk, + lclk => lclk + ); + +------------------------------------------------------------------------------- + parity_err : entity tri.tri_err_rpt(tri_err_rpt) + generic map ( + width => 1 -- use to bundle error reporting checkers of the same exact type + , inline => false -- make hold latch be inline + , mask_reset_value=> "0" -- do not report address and data parity errors by default + -- since already reported to PCB through error reply + , needs_sreset => 1 + , expand_type => expand_type ) + port map ( vd => vd, + gd => gd, + err_d1clk => dcfg_d1clk, + err_d2clk => dcfg_d2clk, + err_lclk => dcfg_lclk, + err_scan_in => dcfg_scan_in (0 to 0), + err_scan_out => dcfg_scan_out(0 to 0), + mode_dclk => dcfg_scan_dclk, + mode_lclk => dcfg_scan_lclk, + mode_scan_in => dcfg_scan_in (1 to 1), + mode_scan_out => dcfg_scan_out(1 to 1), + + err_in (0) => state_par_error, + err_out(0) => scom_err_in + ); + + scom_err <= scom_err_lt; -- drive this output with a latch + +------------------------------------------------------------------------------- + +-- fill spares of scan vector + func_scan_out(state_width + i_width + 2*par_nobits+head_width+22+(2**regid_nobits) to func_scan_out'high) <= + func_scan_in(state_width + i_width + 2*par_nobits+head_width+22+(2**regid_nobits) to func_scan_out'high) ; + +------------------------------------------------------------------------------- + + sat_id_net <= sat_id; + -- input lathes on cch and dch: + scom_cch_input_in <= scom_cch_in; + scom_cch_in_int <= scom_cch_input_lt; + scom_dch_input_in <= scom_dch_in; + scom_dch_in_int <= scom_dch_input_lt; + + + + cch_in <= scom_cch_in_int & cch_lt(0); + + reset <= (cch_lt(0) and not scom_cch_in_int) -- with falling edge of scom_cch_in / scom_cch_in_int + or fsm_reset -- or with fsm_reset + or scom_err_lt; + + local_act <= or_reduce(scom_cch_input_in & cch_lt); -- active with scom_cch_in and as long as cch_lt + + local_act_int <= local_act or scom_local_act_lt; + + scom_local_act_in <= local_act; -- drive this output with a latch + scom_local_act <= scom_local_act_lt; + + scom_cch_out <= cch_lt(0); + + dch_out_internal_in <= head_lt(0) when is_send_ulinfo='1' else + '0' when is_send_0 ='1' else + '1' when is_send_1 ='1' else + data_shifter_lt(0) when (is_send_rdata and not do_send_par)='1' else + datapar_shifter_lt(0) when (is_send_rdata and do_send_par)='1' else + dch_lt; + + scom_dch_out <= dch_out_internal_lt; + +-- copy the internal signals to ports + sc_req <= is_exe_cmd; + sc_addr <= head_lt(satid_nobits+1 to satid_regid_nobits); + sc_r_nw <= head_lt(rw_bit_index); + +-- copy the result of the deserializer to the output, take care of the fact that data shifter is multiple of 16 and not all is used as output + copy2sc_wdata: if width<64 generate + copy2sc_wdata_loop_1: for i in 0 to width-1 generate + sc_wdata(i) <= data_shifter_lt(i); + end generate copy2sc_wdata_loop_1; + + + end generate copy2sc_wdata; + + copy2sc_wdata_all: if width=64 generate + sc_wdata <= data_shifter_lt; + end generate copy2sc_wdata_all; + + + sc_wparity <= xor_reduce(datapar_shifter_lt); + +------------------------------------------------------------------------------- + -- FSM: serial => parallel => serial state machine + -- + fsm_transition: process (state_lt, got_head, gor_eofwdata, got_eofwpar, + got_ulhead, sent_rdata, p0_err, any_ack_error, + match, do_write, do_read, + cch_lt(0), dch_lt, sc_ack, wpar_err, read_nvld) + + begin + next_state <= state_lt; + case state_lt is + when idle => if dch_lt='1' then + next_state <= rec_head; + end if; + + when rec_head => if (got_head)='1' then + next_state <= check_before; + end if; + + when check_before => if match='0' then + next_state <= not_selected; + elsif ( (read_nvld or p0_err) and do_read)='1' then + next_state <= filler0; + elsif (not p0_err and not read_nvld and do_read)='1' then + next_state <= exe_cmd; + else + next_state <= rec_wdata; + end if; + + when rec_wdata => if gor_eofwdata='1' then + next_state <= rec_wpar; + end if; + + when rec_wpar => if (got_eofwpar and not p0_err)='1' then + next_state <= check_wpar; + elsif (got_eofwpar and p0_err)='1' then + next_state <= filler0; + end if; + + when check_wpar => if wpar_err='0' then + next_state <= exe_cmd; + else + next_state <= filler1; + end if; + + when exe_cmd => if sc_ack='1' then + next_state <= filler1; + end if; + + when filler0 => next_state <= filler1; + + when filler1 => next_state <= gen_ulinfo; + + when gen_ulinfo => next_state <= send_ulinfo; + + when send_ulinfo => if (got_ulhead and (do_write or (do_read and any_ack_error)))='1' then + next_state <= send_0; + elsif (got_ulhead and do_read)='1' then + next_state <= send_rdata; + end if; + + when send_rdata => if sent_rdata='1' then + next_state <= send_0; + end if; + + when send_0 => next_state <= send_1; + + when send_1 => next_state <= idle; + + when not_selected => if cch_lt(0)='0' then + next_state <= idle; + end if; + + when others => next_state <= idle; + + end case; + + end process fsm_transition; + + state_in <= state_lt when local_act='0' else + idle when reset='1' else + next_state; + + state_par_error <= xor_reduce(state_lt); + +------------------------------------------------------------------------------- + is_idle <= (state_lt=idle); + is_rec_head <= (state_lt=rec_head); + is_check_before <= (state_lt=check_before); + is_rec_wdata <= (state_lt=rec_wdata); + is_rec_wpar <= (state_lt=rec_wpar); + is_exe_cmd <= (state_lt=exe_cmd); + is_gen_ulinfo <= (state_lt=gen_ulinfo); + is_send_ulinfo <= (state_lt=send_ulinfo); + is_send_rdata <= (state_lt=send_rdata); + is_send_0 <= (state_lt=send_0); + is_send_1 <= (state_lt=send_1); + is_filler_0 <= (state_lt=filler0); + is_filler_1 <= (state_lt=filler1); + +------------------------------------------------------------------------------- + enable_cnt <= is_rec_head + or is_check_before + or is_rec_wdata + or is_rec_wpar + or is_send_ulinfo + or is_send_rdata + or is_send_0 + or is_send_1 + ; + cnt_in <= (others=>'0') when ((is_idle or is_gen_ulinfo) = '1') else + cnt_lt + "0000001" when (enable_cnt = '1') else + cnt_lt; + + got_head <= (cnt_lt = (1+satid_nobits+regid_nobits)); + + got_ulhead <= (cnt_lt = (1+satid_nobits+regid_nobits+4)); + + gor_eofwdata <= (cnt_lt = eof_wdata); + got_eofwpar <= (cnt_lt = eof_wpar); + + sent_rdata <= (cnt_lt=tconv(83,7)); + + cntgtheadpluswidth <= (cnt_lt > eof_wdata_n); + cntgteofwdataplusparity <= (cnt_lt > eof_wpar_m); + + do_send_par <= (cnt_lt > 79); -- 78 bits = 15 ulhead + 64 data + +------------------------------------------------------------------------------- + -- shift downlink command (for this or any subsequent satellite) or uplink response (from previous satellite) + head_in(head_width-2 to head_width-1) <= head_lt(head_width-1) & dch_lt when (is_rec_head or (is_idle and dch_lt))='1' else + head_lt(head_width-2 to head_width-1); + + head_in(0 to satid_regid_nobits) <= head_lt(1 to satid_regid_nobits) & head_mux when (is_rec_head or is_send_ulinfo)='1' else + head_lt(0 to satid_regid_nobits); + + head_mux <= head_lt(rw_bit_index) when is_rec_head='1' else + tail_lt(0); + + + -- calculate parity P0 of uplink frame + tail_in(4) <= xor_reduce ( parity_satid_regaddr_lt & tail_lt(0) & (wpar_err and do_write) & sc_ack_info_lt(0 to 1)) + when is_gen_ulinfo='1'and (internal_addr_decode=false) else + xor_reduce ( parity_satid_regaddr_lt & tail_lt(0) & (wpar_err and do_write) & (write_nvld or read_nvld) & addr_nvld ) + when is_gen_ulinfo='1'and (internal_addr_decode=true) + else tail_lt(4); + + + + -- copy sampled ack_info coming from logic + tail_in(2 to 3) <= sc_ack_info_lt(0 to 1) when is_gen_ulinfo='1' and internal_addr_decode=false else + (write_nvld or read_nvld) & addr_nvld when is_gen_ulinfo='1' and internal_addr_decode=true else + tail_lt(3 to 4) when is_send_ulinfo='1' else -- shift out + tail_lt(2 to 3); + + + + -- Write Data Parity error + tail_in(1) <= (wpar_err and do_write) when is_gen_ulinfo='1' else -- parity error on write operation + tail_lt(2) when is_send_ulinfo='1' else -- shift out + tail_lt(1); + + -- parity check of of downlink P0 yields error + tail_in(0) <= not p0_err when is_check_before='1' else -- set to '1' if a downlink parity error is detected by satellite, otherwise '0' + tail_lt(1) when is_send_ulinfo='1' else -- shift out + tail_lt(0); + + -- sample and hold ack_info, one spare bit + sc_ack_info_in <= sc_ack_info when (is_exe_cmd and sc_ack)='1' else + "00" when is_idle='1' else + sc_ack_info_lt; + +------------------------------------------------------------------------------- + + do_write <= not do_read; + do_read <= head_lt(rw_bit_index); + match <= (head_lt(1 to satid_nobits)=sat_id_net); + + -- if downlink parity error then set p0_err + p0_err_in <= '0' when (is_idle = '1') else + p0_err_lt xor head_in(parbit_index) when (is_rec_head = '1') else + p0_err_lt ; + p0_err <= p0_err_lt; + -- p0_err <= gate_and(is_check_before, xor_reduce (head_lt(1 to parbit_index))); + ------------------------------------------------------------------------- + parity_satid_regaddr_in <= xor_reduce (sat_id_net & head_lt(satid_nobits+1 to satid_regid_nobits)); + + any_ack_error <= or_reduce(sc_ack_info_lt); + +------------------------------------------------------------------------------- + + data_mux <= dch_lt when (is_check_before or is_rec_wdata)='1' else + '0'; + + data_shifter_in_1: if (width = i_width) generate + data_shifter_in <= data_shifter_lt(1 to i_width-1) & data_mux when (is_check_before or + (is_rec_wdata and not cntgtheadpluswidth) or + is_send_rdata)='1' else + (sc_rdata(0 to width-1)) when (is_exe_cmd and sc_ack and do_read)='1' else + data_shifter_lt; + end generate data_shifter_in_1; + + data_shifter_in_2: if (width < i_width) generate + data_shifter_in <= data_shifter_lt(1 to i_width-1) & data_mux when (is_check_before or + (is_rec_wdata and not cntgtheadpluswidth) or + is_send_rdata)='1' else + (sc_rdata(0 to width-1) & (width to i_width-1 =>'0')) when (is_exe_cmd and sc_ack and do_read)='1' else + data_shifter_lt; + end generate data_shifter_in_2; +------------------------------------------------------------------------------- + -- parity handling + par_mux <= dch_lt when (is_rec_wpar)='1' else + '0'; + + -- receiving parity: shift when receiving write data parity + -- sending parity of read data: shift when sending read data parity + -- latch generated parity of read data when read data is accepted + datapar_shifter_in <= datapar_shifter_lt(1 to par_nobits-1) & par_mux when ((is_rec_wpar and not cntgteofwdataplusparity)or + (is_send_rdata and do_send_par))='1' else + sc_rparity when (is_filler_1 ='1') else -- 1.33 + datapar_shifter_lt; + + + data_shifter_move_1: if (width = i_width) generate + data_shifter_lt_tmp (0 to width-1) <= data_shifter_lt; + data_shifter_padding_1: if width < 64 generate + data_shifter_lt_tmp(width to 63) <= (others=>'0'); + end generate data_shifter_padding_1; + end generate data_shifter_move_1; + + data_shifter_move_2: if (width < i_width) generate + data_shifter_lt_tmp(0 to width-1) <= data_shifter_lt(0 to width-1); + data_shifter_lt_tmp(width to i_width-1) <= data_shifter_lt(width to i_width-1); + data_shifter_padding_1: if i_width < 64 generate + data_shifter_lt_tmp(i_width to 63) <= (others=>'0'); + end generate data_shifter_padding_1; + end generate data_shifter_move_2; +------------------------------------------------------------------------------- + + wdata_par_check: for i in 0 to par_nobits-1 generate + par_data_in(i) <= xor_reduce(data_shifter_lt_tmp(16*i to 16*(i+1)-1)); + end generate wdata_par_check; + + wdata_par_check_pipe: if pipeline_paritychk=true generate + state: entity tri.tri_nlat_scan(tri_nlat_scan) + generic map( width => par_nobits, + needs_sreset => 1, + expand_type => expand_type ) + port map + ( d1clk => d1clk + , vd => vd + , gd => gd + , lclk => lclk + , d2clk => d2clk + , scan_in => func_scan_in (state_width+i_width+par_nobits+head_width+22 to state_width+i_width+2*par_nobits+head_width+21) + , scan_out => func_scan_out(state_width+i_width+par_nobits+head_width+22 to state_width+i_width+2*par_nobits+head_width+21) + , din => par_data_in + , q => par_data_lt + ); + end generate wdata_par_check_pipe; + + wdata_par_check_nopipe: if pipeline_paritychk=false generate + par_data_lt <= par_data_in; + func_scan_out(state_width+i_width+par_nobits+head_width+22 to state_width+i_width+2*par_nobits+head_width+21) + <= func_scan_in (state_width+i_width+par_nobits+head_width+22 to state_width+i_width+2*par_nobits+head_width+21); + + end generate wdata_par_check_nopipe; + + wpar_err_in <= or_reduce(par_data_in xor datapar_shifter_in); + wpar_err <= wpar_err_lt; + +------------------------------------------------------------------------------- + rdata_parity_gen: for i in 0 to par_nobits-1 generate + sc_rparity(i) <= xor_reduce(data_shifter_lt_tmp(16*i to 16*(i+1)-1)); + end generate rdata_parity_gen; +------------------------------------------------------------------------------- + ------------------------------------------------------------------- + -- address decoding section + -- Generate onehot Address (binary to one-hot) + ------------------------------------------------------------------- + + internal_addr_decoding: if internal_addr_decode=true generate + -------------------------------------------------------------------------- + foralladdresses : for i in use_addr'range generate + ------------------------------------------------------------------------ + addr_bit_set : if (use_addr(i) = '1') generate + dec_addr_in(i) <= (head_lt(satid_nobits+1 to satid_regid_nobits) = tconv(i, reg_nobits)); + + -- generate latch to hold addr_v only if required + latch_for_onehot : if pipeline_addr_v(i) = '1' generate + dec_addr : entity tri.tri_nlat(tri_nlat) + generic map( width => 1, + needs_sreset => 1, + expand_type => expand_type) + port map ( d1clk => d1clk, + vd => vd, + gd => gd, + d2clk => d2clk, + lclk => lclk, + scan_in => func_scan_in(state_width+i_width+2*par_nobits+head_width+22 +i), + din(0) => dec_addr_in(i), + q(0) => dec_addr_q(i), + scan_out => func_scan_out(state_width+i_width+2*par_nobits+head_width+22 +i) ); + end generate latch_for_onehot; + + -- otherwise no latch + no_latch_for_onehot : if pipeline_addr_v(i) = '0' generate + func_scan_out(state_width+i_width+2*par_nobits+head_width+22 +i) <= func_scan_in(state_width+i_width+2*par_nobits+head_width+22 +i); + dec_addr_q(i) <= dec_addr_in(i); + end generate no_latch_for_onehot; + + end generate addr_bit_set; + ------------------------------------------------------------------------ + addr_bit_notset : if (use_addr(i) /= '1') generate -- do not generate hardware for unused addresses + func_scan_out(state_width+i_width+2*par_nobits+head_width+22+i) <= func_scan_in(state_width+i_width+2*par_nobits+head_width+22 +i); + dec_addr_in(i) <= '0'; + dec_addr_q(i) <= dec_addr_in(i); + end generate addr_bit_notset; + end generate foralladdresses; + -------------------------------------------------------------------------- + -- check writable and/or readable, 1.45: dec_addr_q changed to dec_addr_in + read_valid <= or_reduce(dec_addr_in and addr_is_rdable); + write_valid <= or_reduce(dec_addr_in and addr_is_wrable); + addr_nvld <= not or_reduce(dec_addr_in); + write_nvld <= (not write_valid and not addr_nvld) and do_write; + read_nvld <= (not read_valid and not addr_nvld) and do_read; + + unused <= "00"; + end generate internal_addr_decoding; + + + external_addr_decoding: if internal_addr_decode=false generate + foralladdresses : for i in use_addr'range generate + func_scan_out(state_width+i_width+2*par_nobits+head_width+22+i) <= func_scan_in(state_width+i_width+2*par_nobits+head_width+22 +i); + dec_addr_in(i) <= '0'; + dec_addr_q(i) <= dec_addr_in(i); + end generate foralladdresses; + read_valid <= '1';-- suppressing wrong error generation + write_valid<= '1';-- suppressing wrong error generation + addr_nvld <= '0'; + write_nvld <= '0'; + read_nvld <= '0'; + + unused <= write_valid & read_valid; + end generate external_addr_decoding; + + + + short_unused_addr_range: for i in use_addr'high+1 to 63 generate + func_scan_out(state_width+i_width+2*par_nobits+head_width+22+i) <= func_scan_in(state_width+i_width+2*par_nobits+head_width+22+i); + end generate short_unused_addr_range; + + addr_v <= dec_addr_q(0 to use_addr'high); + +------------------------------------------------------------------------------- + + state: entity tri.tri_nlat_scan(tri_nlat_scan) + generic map( width => state_width, init => idle, needs_sreset => 1, expand_type => expand_type ) + port map + ( d1clk => d1clk + , vd => vd + , gd => gd + , lclk => lclk + , d2clk => d2clk + , scan_in => func_scan_in (0 to state_width-1) + , scan_out => func_scan_out(0 to state_width-1) + , din => state_in + , q => state_lt + ); + + counter: entity tri.tri_nlat_scan(tri_nlat_scan) + generic map( width => 7, init => "0000000", needs_sreset => 1, expand_type => expand_type ) + port map + ( d1clk => d1clk + , vd => vd + , gd => gd + , lclk => lclk + , d2clk => d2clk + , scan_in => func_scan_in (state_width to state_width+6) + , scan_out => func_scan_out(state_width to state_width+6) + , din => cnt_in + , q => cnt_lt + ); + + data_shifter: entity tri.tri_nlat_scan(tri_nlat_scan) + generic map( width => i_width, needs_sreset => 1, expand_type => expand_type ) + port map + ( d1clk => d1clk + , vd => vd + , gd => gd + , lclk => lclk + , d2clk => d2clk + , scan_in => func_scan_in (state_width+7 to state_width+i_width+6) + , scan_out => func_scan_out(state_width+7 to state_width+i_width+6) + , din => data_shifter_in + , q => data_shifter_lt + ); + + datapar_shifter: entity tri.tri_nlat_scan(tri_nlat_scan) + generic map( width => par_nobits, needs_sreset => 1, expand_type => expand_type ) + port map + ( d1clk => d1clk + , vd => vd + , gd => gd + , lclk => lclk + , d2clk => d2clk + , scan_in => func_scan_in (state_width+i_width+7 to state_width+i_width+par_nobits+6) + , scan_out => func_scan_out(state_width+i_width+7 to state_width+i_width+par_nobits+6) + , din => datapar_shifter_in + , q => datapar_shifter_lt + ); + + head_lat: entity tri.tri_nlat_scan(tri_nlat_scan) + generic map( width => head_width, init => head_init, needs_sreset => 1, expand_type => expand_type ) + port map + ( d1clk => d1clk + , vd => vd + , gd => gd + , lclk => lclk + , d2clk => d2clk + , scan_in => func_scan_in (state_width+i_width+par_nobits+7 to state_width+i_width+par_nobits+head_width+6) + , scan_out => func_scan_out(state_width+i_width+par_nobits+7 to state_width+i_width+par_nobits+head_width+6) + , din => head_in + , q => head_lt + ); + + tail_lat: entity tri.tri_nlat_scan(tri_nlat_scan) + generic map( width => 5, init => "00000", needs_sreset => 1, expand_type => expand_type ) + port map + ( d1clk => d1clk, + vd => vd, + gd => gd, + lclk => lclk, + d2clk => d2clk, + scan_in => func_scan_in (state_width+i_width+par_nobits+head_width+7 to state_width+i_width+par_nobits+head_width+11), + scan_out => func_scan_out(state_width+i_width+par_nobits+head_width+7 to state_width+i_width+par_nobits+head_width+11), + din => tail_in, + q => tail_lt + ); + + dch_inlatch: entity tri.tri_nlat(tri_nlat) + generic map( width => 1, needs_sreset => 1, expand_type => expand_type ) + port map + ( d1clk => d1clk + , vd => vd + , gd => gd + , lclk => lclk + , d2clk => d2clk + , scan_in => func_scan_in (state_width+i_width+par_nobits+head_width+12) + , scan_out => func_scan_out(state_width+i_width+par_nobits+head_width+12) + , din(0) => scom_dch_in_int + , q(0) => dch_lt + ); + + + ack_info: entity tri.tri_nlat_scan(tri_nlat_scan) + generic map( width => 2, needs_sreset => 1, expand_type => expand_type ) + port map + ( d1clk => d1clk + , vd => vd + , gd => gd + , lclk => lclk + , d2clk => d2clk + , scan_in => func_scan_in (state_width+i_width+par_nobits+head_width+13 to state_width+i_width+par_nobits+head_width+14) + , scan_out => func_scan_out(state_width+i_width+par_nobits+head_width+13 to state_width+i_width+par_nobits+head_width+14) + , din => sc_ack_info_in + , q => sc_ack_info_lt + ); + + dch_outlatch: entity tri.tri_nlat(tri_nlat) + generic map( width => 1, needs_sreset => 1, expand_type => expand_type ) + port map + ( d1clk => d1clk + , vd => vd + , gd => gd + , lclk => lclk + , d2clk => d2clk + , scan_in => func_scan_in (state_width+i_width+par_nobits+head_width+15) + , scan_out => func_scan_out(state_width+i_width+par_nobits+head_width+15) + , din(0) => dch_out_internal_in + , q(0) => dch_out_internal_lt + ); + + cch_latches: entity tri.tri_nlat_scan(tri_nlat_scan) + generic map( width => 2, needs_sreset => 1, expand_type => expand_type ) + port map + ( d1clk => d1clk + , vd => vd + , gd => gd + , lclk => lclk + , d2clk => d2clk + , scan_in => func_scan_in (state_width+i_width+par_nobits+head_width+16 to state_width+i_width+par_nobits+head_width+17) + , scan_out => func_scan_out(state_width+i_width+par_nobits+head_width+16 to state_width+i_width+par_nobits+head_width+17) + , din => cch_in + , q => cch_lt + ); + + scom_err_latch: entity tri.tri_nlat(tri_nlat) + generic map( width => 1, needs_sreset => 1, expand_type => expand_type ) + port map + ( d1clk => d1clk + , vd => vd + , gd => gd + , lclk => lclk + , d2clk => d2clk + , scan_in => func_scan_in (state_width+i_width+par_nobits+head_width+18) + , scan_out => func_scan_out(state_width+i_width+par_nobits+head_width+18) + , din(0) => scom_err_in + , q(0) => scom_err_lt + ); + + scom_local_act_latch: entity tri.tri_nlat(tri_nlat) + generic map( width => 1, needs_sreset => 1, expand_type => expand_type ) + port map + ( d1clk => d1clk + , vd => vd + , gd => gd + , lclk => lclk + , d2clk => d2clk + , scan_in => func_scan_in (state_width+i_width+par_nobits+head_width+19) + , scan_out => func_scan_out(state_width+i_width+par_nobits+head_width+19) + , din(0) => scom_local_act_in + , q(0) => scom_local_act_lt + ); + + spare_latch1: entity tri.tri_nlat(tri_nlat) + generic map( width => 1, needs_sreset => 1, expand_type => expand_type ) + port map + ( d1clk => d1clk + , vd => vd + , gd => gd + , lclk => lclk + , d2clk => d2clk + , scan_in => func_scan_in (state_width+i_width+par_nobits+head_width+20) + , scan_out => func_scan_out(state_width+i_width+par_nobits+head_width+20) + , din(0) => spare_latch1_in + , q(0) => spare_latch1_lt + ); + + spare_latch2: entity tri.tri_nlat(tri_nlat) + generic map( width => 1, needs_sreset => 1, expand_type => expand_type ) + port map + ( d1clk => d1clk + , vd => vd + , gd => gd + , lclk => lclk + , d2clk => d2clk + , scan_in => func_scan_in(state_width+i_width+par_nobits+head_width+21) + , scan_out => func_scan_temp + , din(0) => spare_latch2_in + , q(0) => spare_latch2_lt + ); + + scom_cch_input_latch: entity tri.tri_nlat(tri_nlat) + generic map( width => 1, needs_sreset => 1, expand_type => expand_type ) + port map + ( d1clk => d1clk + , vd => vd + , gd => gd + , lclk => lclk + , d2clk => d2clk + , scan_in => func_scan_temp + , scan_out => func_scan_temp_1 + , din(0) => scom_cch_input_in + , q(0) => scom_cch_input_lt + ); + + scom_dch_input_latch: entity tri.tri_nlat(tri_nlat) + generic map( width => 1, needs_sreset => 1, expand_type => expand_type ) + port map + ( d1clk => d1clk + , vd => vd + , gd => gd + , lclk => lclk + , d2clk => d2clk + , scan_in => func_scan_temp_1 + , scan_out => func_scan_temp_2 + , din(0) => scom_dch_input_in + , q(0) => scom_dch_input_lt + ); + + parity_reg1: entity tri.tri_nlat(tri_nlat) + generic map( width => 1, needs_sreset => 1, expand_type => expand_type ) + port map + ( d1clk => d1clk + , vd => vd + , gd => gd + , lclk => lclk + , d2clk => d2clk + , scan_in => func_scan_temp_2 + , scan_out => func_scan_temp_3 + , din(0) => parity_satid_regaddr_in + , q(0) => parity_satid_regaddr_lt + ); + + p0_err_latch: entity tri.tri_nlat(tri_nlat) + generic map( width => 1, needs_sreset => 1, expand_type => expand_type ) + port map + ( d1clk => d1clk + , vd => vd + , gd => gd + , lclk => lclk + , d2clk => d2clk + , scan_in => func_scan_temp_3 + , scan_out => func_scan_temp_4 + , din(0) => p0_err_in + , q(0) => p0_err_lt + ); + + wpar_err_latch: entity tri.tri_nlat(tri_nlat) + generic map( width => 1, needs_sreset => 1, expand_type => expand_type ) + port map + ( d1clk => d1clk + , vd => vd + , gd => gd + , lclk => lclk + , d2clk => d2clk + , scan_in => func_scan_temp_4 + , scan_out => func_scan_out(state_width+i_width+par_nobits+head_width+21) + , din(0) => wpar_err_in + , q(0) => wpar_err_lt + ); + +------------------------------------------------------------------------------- + unused_signals <= or_reduce ( is_filler_0 & is_filler_1 + & spare_latch1_lt + & spare_latch2_lt + & par_data_lt + & d_mode_dc ) ; + + spare_latch1_in <= '0'; + spare_latch2_in <= '0'; + + + end generate a; + +end tri_serial_scom2; diff --git a/rel/src/vhdl/tri/tri_slat_scan.vhdl b/rel/src/vhdl/tri/tri_slat_scan.vhdl new file mode 100644 index 0000000..5e28494 --- /dev/null +++ b/rel/src/vhdl/tri/tri_slat_scan.vhdl @@ -0,0 +1,83 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- *!**************************************************************** +-- *! FILENAME : tri_slat_scan.vhdl +-- *! DESCRIPTION : n-bit scan-only latch without scan_connect +-- *!**************************************************************** + +library ieee; use ieee.std_logic_1164.all; + use ieee.numeric_std.all; +library support; use support.power_logic_pkg.all; +library tri; use tri.tri_latches_pkg.all; + +entity tri_slat_scan is + + generic ( width : positive range 1 to 65536 := 1 ; + offset : natural range 0 to 65535 := 0; + init : std_ulogic_vector := "0" ; + synthclonedlatch : string := "" ; + btr : string := "c_slat_scan" ; + reset_inverts_scan : boolean := true; + expand_type : integer := 1 ); -- 1 = non-ibm, 2 = ibm (MPG) + port ( + vd : inout power_logic; + gd : inout power_logic; + dclk : in std_ulogic; + lclk : in clk_logic; + scan_in : in std_ulogic_vector(offset to offset+width-1); + scan_out : out std_ulogic_vector(offset to offset+width-1); + q : out std_ulogic_vector(offset to offset+width-1); + q_b : out std_ulogic_vector(offset to offset+width-1) + ); + + -- synopsys translate_off + + -- synopsys translate_on + +end entity tri_slat_scan; + +architecture tri_slat_scan of tri_slat_scan is + +begin + + a: if expand_type = 1 generate + constant zeros : std_ulogic_vector(0 to width-1) := (0 to width-1 => '0'); + constant initv : std_ulogic_vector(0 to (init'length + width-1)):=init & (0 to width-1=>'0'); + signal unused : std_ulogic_vector(0 to width); + -- synopsys translate_off + -- synopsys translate_on + begin + scan_out <= zeros; + q <= initv(0 to width-1); + q_b <= not initv(0 to width-1); + unused(0) <= dclk; + unused(1 to width) <= scan_in; + end generate a; + +end tri_slat_scan; diff --git a/rel/src/vhdl/work/a2l2_axi.vhdl b/rel/src/vhdl/work/a2l2_axi.vhdl new file mode 100644 index 0000000..f9c12a7 --- /dev/null +++ b/rel/src/vhdl/work/a2l2_axi.vhdl @@ -0,0 +1,1844 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- ttypes handled: +-- 00 ifetch +-- 01 ifetch pre (may not occur?) +-- 08 load +-- 09 larx +-- 20 store +-- 29 stcx +-- 2A lwsync +-- 2B hwsync +-- 3A tlbsync (lwsync version) +-- 3F dcbi + +-- 08 larx +-- OB larx w/hint + +-- ttypes not handled: +-- 02 mmu_read (is it diff from load?) +-- 04 icbt +-- 05 dcbtst +-- 07 dcbt +-- 0D dcbtst +-- 0F dcbtls +-- 14 icbtls +-- 15 dcbtstls +--- 17 dcbtls +-- 21 dcbz +-- 22 ditc +-- 24 icblc +-- 25 dcblc +-- 26 icswx +-- 27 icswx. +-- 2C mtspr_trace +-- 2D msgsnd +-- 2E ici +-- 2F dci +-- 32 mbar +-- 33 ptesync +-- 34 l1_load_hit +-- 35 dcbst +-- 36 dcbf +-- 37 dcbf +-- 3C tlbivax +-- 3D tlbi +-- 3E icbi +-- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.all; +use work.a2x_pkg.all; + +entity a2l2_axi is + generic ( + threads : integer := 4; + xu_real_data_add : integer := 42; + st_data_32b_mode : integer := 1; -- proc data/be size + ac_st_data_32b_mode : integer := 1; + stores_32B : boolean := false; -- does proc gen 32B stores + lpid_width : integer := 8; + ld_queue_size : integer := c_ld_queue_size; + st_queue_size : integer := c_st_queue_size; + rld_spacing : std_logic_vector := "1111"; -- debug: space b2b reloads + C_m00_AXI_ID_WIDTH : integer := 4; + C_m00_AXI_ADDR_WIDTH : integer := 32; + C_m00_AXI_DATA_WIDTH : integer := 32; + C_m00_AXI_AWUSER_WIDTH : integer := 4; + C_m00_AXI_ARUSER_WIDTH : integer := 4; + C_m00_AXI_WUSER_WIDTH : integer := 4; + C_m00_AXI_RUSER_WIDTH : integer := 4; + C_m00_AXI_BUSER_WIDTH : integer := 4 + ); + port ( + clk : in std_logic; + reset_n : in std_logic; + err : out std_logic_vector(0 to 3); + + ac_an_req_pwr_token : in std_logic; + ac_an_req : in std_logic; + ac_an_req_endian : in std_logic; + ac_an_req_ld_core_tag : in std_logic_vector(0 to 4); + ac_an_req_ld_xfr_len : in std_logic_vector(0 to 2); + ac_an_req_ra : in std_logic_vector(64-xu_real_data_add to 63); + ac_an_req_thread : in std_logic_vector(0 to 2); + ac_an_req_ttype : in std_logic_vector(0 to 5); + ac_an_req_user_defined : in std_logic_vector(0 to 3); + ac_an_req_wimg_g : in std_logic; + ac_an_req_wimg_i : in std_logic; + ac_an_req_wimg_m : in std_logic; + ac_an_req_wimg_w : in std_logic; + + ac_an_st_data_pwr_token : in std_logic; + ac_an_st_byte_enbl : in std_logic_vector(0 to 15+(st_data_32b_mode*16)); + ac_an_st_data : in std_logic_vector(0 to 127+(st_data_32b_mode*128)); + + an_ac_reld_data_coming : out std_logic; + an_ac_reld_core_tag : out std_logic_vector(0 to 4); + an_ac_reld_data : out std_logic_vector(0 to 127); + an_ac_reld_data_vld : out std_logic; + an_ac_reld_ecc_err : out std_logic; + an_ac_reld_ecc_err_ue : out std_logic; + an_ac_reld_qw : out std_logic_vector(57 to 59); + an_ac_reld_crit_qw : out std_logic; + an_ac_reld_l1_dump : out std_logic; + + an_ac_req_ld_pop : out std_logic; + an_ac_req_st_pop : out std_logic; + an_ac_req_st_gather : out std_logic; + an_ac_req_st_pop_thrd : out std_logic_vector(0 to 2); + an_ac_reservation_vld : out std_logic_vector(0 to threads-1); + an_ac_stcx_complete : out std_logic_vector(0 to 3); + an_ac_stcx_pass : out std_logic_vector(0 to 3); + an_ac_sync_ack : out std_logic_vector(0 to 3); + + m00_axi_awid : out std_logic_vector(C_M00_AXI_ID_WIDTH-1 downto 0); + m00_axi_awaddr : out std_logic_vector(C_M00_AXI_ADDR_WIDTH-1 downto 0); + m00_axi_awlen : out std_logic_vector(7 downto 0); + m00_axi_awsize : out std_logic_vector(2 downto 0); + m00_axi_awburst : out std_logic_vector(1 downto 0); + m00_axi_awlock : out std_logic; + m00_axi_awcache : out std_logic_vector(3 downto 0); + m00_axi_awprot : out std_logic_vector(2 downto 0); + m00_axi_awqos : out std_logic_vector(3 downto 0); + m00_axi_awuser : out std_logic_vector(C_M00_AXI_AWUSER_WIDTH-1 downto 0); + m00_axi_awvalid : out std_logic; + m00_axi_awready : in std_logic; + m00_axi_wdata : out std_logic_vector(C_M00_AXI_DATA_WIDTH-1 downto 0); + m00_axi_wstrb : out std_logic_vector(C_M00_AXI_DATA_WIDTH/8-1 downto 0); + m00_axi_wlast : out std_logic; + m00_axi_wuser : out std_logic_vector(C_M00_AXI_WUSER_WIDTH-1 downto 0); + m00_axi_wvalid : out std_logic; + m00_axi_wready : in std_logic; + m00_axi_bid : in std_logic_vector(C_M00_AXI_ID_WIDTH-1 downto 0); + m00_axi_bresp : in std_logic_vector(1 downto 0); + m00_axi_buser : in std_logic_vector(C_M00_AXI_BUSER_WIDTH-1 downto 0); + m00_axi_bvalid : in std_logic; + m00_axi_bready : out std_logic; + m00_axi_arid : out std_logic_vector(C_M00_AXI_ID_WIDTH-1 downto 0); + m00_axi_araddr : out std_logic_vector(C_M00_AXI_ADDR_WIDTH-1 downto 0); + m00_axi_arlen : out std_logic_vector(7 downto 0); + m00_axi_arsize : out std_logic_vector(2 downto 0); + m00_axi_arburst : out std_logic_vector(1 downto 0); + m00_axi_arlock : out std_logic; + m00_axi_arcache : out std_logic_vector(3 downto 0); + m00_axi_arprot : out std_logic_vector(2 downto 0); + m00_axi_arqos : out std_logic_vector(3 downto 0); + m00_axi_aruser : out std_logic_vector(C_M00_AXI_ARUSER_WIDTH-1 downto 0); + m00_axi_arvalid : out std_logic; + m00_axi_arready : in std_logic; + m00_axi_rid : in std_logic_vector(C_M00_AXI_ID_WIDTH-1 downto 0); + m00_axi_rdata : in std_logic_vector(C_M00_AXI_DATA_WIDTH-1 downto 0); + m00_axi_rresp : in std_logic_vector(1 downto 0); + m00_axi_rlast : in std_logic; + m00_axi_ruser : in std_logic_vector(C_M00_AXI_RUSER_WIDTH-1 downto 0); + m00_axi_rvalid : in std_logic; + m00_axi_rready : out std_logic + ); +end a2l2_axi; + +architecture a2l2_axi of a2l2_axi is + +signal reload_d: A2L2RELOAD; +signal reload_q: A2L2RELOAD; + +signal rld_seq_d : std_logic_vector(0 to 4); +signal rld_seq_q : std_logic_vector(0 to 4); +signal rld_dseq_d : std_logic_vector(0 to 3); +signal rld_dseq_q : std_logic_vector(0 to 3); + +signal req_pwr_d: std_logic; +signal req_pwr_q: std_logic; +signal store_pwr_d: std_logic; +signal store_pwr_q: std_logic; + +signal load_queue_d: LOADQUEUE; +signal load_queue_q: LOADQUEUE; +signal ldq_head_d: std_logic_vector(0 to clog2(ld_queue_size)-1); +signal ldq_head_q: std_logic_vector(0 to clog2(ld_queue_size)-1); +signal ldq_send_d: std_logic_vector(0 to clog2(ld_queue_size)-1); +signal ldq_send_q: std_logic_vector(0 to clog2(ld_queue_size)-1); +signal ldq_data_d: std_logic_vector(0 to clog2(ld_queue_size)-1); +signal ldq_data_q: std_logic_vector(0 to clog2(ld_queue_size)-1); +signal ldq_tail_d: std_logic_vector(0 to clog2(ld_queue_size)-1); +signal ldq_tail_q: std_logic_vector(0 to clog2(ld_queue_size)-1); +signal ldq_count_d: std_logic_vector(0 to clog2(ld_queue_size)); +signal ldq_count_q: std_logic_vector(0 to clog2(ld_queue_size)); +signal load_dep_d: LOADQUEUEDEP; +signal load_dep_q: LOADQUEUEDEP; +signal rld_head : A2L2REQUEST; + +signal load_data_ready_d, load_data_ready_q : std_logic; +signal load_data_queue_d : LOADDATAQUEUE; +signal load_data_queue_q : LOADDATAQUEUE; + +signal rdataq_head_d : std_logic_vector(0 to clog2(ld_queue_size*16)-1); +signal rdataq_head_q : std_logic_vector(0 to clog2(ld_queue_size*16)-1); +signal rdataq_tail_d : std_logic_vector(0 to clog2(ld_queue_size*16)-1); +signal rdataq_tail_q : std_logic_vector(0 to clog2(ld_queue_size*16)-1); + +signal store_queue_d : STOREQUEUE; +signal store_queue_q : STOREQUEUE; +signal store_data_queue_d : STOREDATAQUEUE; +signal store_data_queue_q : STOREDATAQUEUE; +signal store_rsp_ready_d, store_rsp_ready_q : std_logic; +signal stq_head_d: std_logic_vector(0 to clog2(st_queue_size)-1); +signal stq_head_q: std_logic_vector(0 to clog2(st_queue_size)-1); +signal stq_send_d: std_logic_vector(0 to clog2(st_queue_size)-1); +signal stq_send_q: std_logic_vector(0 to clog2(st_queue_size)-1); +signal stq_data_d: std_logic_vector(0 to clog2(st_queue_size)-1); +signal stq_data_q: std_logic_vector(0 to clog2(st_queue_size)-1); +signal stq_tail_d: std_logic_vector(0 to clog2(st_queue_size)-1); +signal stq_tail_q: std_logic_vector(0 to clog2(st_queue_size)-1); +signal stq_count_d: std_logic_vector(0 to clog2(st_queue_size)); +signal stq_count_q: std_logic_vector(0 to clog2(st_queue_size)); +signal st_data_xfer_d: std_logic_vector(0 to 2); +signal st_data_xfer_q: std_logic_vector(0 to 2); +signal store_pop_pending_d: std_logic_vector(0 to clog2(st_queue_size)-1); +signal store_pop_pending_q: std_logic_vector(0 to clog2(st_queue_size)-1); +signal store_dep_d: STOREQUEUEDEP; +signal store_dep_q: STOREQUEUEDEP; + +signal resv_d: RESVARRAY; +signal resv_q: RESVARRAY; + +signal req_p1_d: A2L2REQUEST; +signal req_p1_q: A2L2REQUEST; +signal ld_p1_entry_d: std_logic_vector(0 to clog2(ld_queue_size)); +signal ld_p1_entry_q: std_logic_vector(0 to clog2(ld_queue_size)); +signal st_p1_entry_d: std_logic_vector(0 to clog2(st_queue_size)); +signal st_p1_entry_q: std_logic_vector(0 to clog2(st_queue_size)); +signal status_d: A2L2STATUS; +signal status_q: A2L2STATUS; +signal err_d, err_q: std_logic_vector(0 to 3); +signal rld_spacing_d, rld_spacing_q: std_logic_vector(0 to 3); +signal rld_spacing_cnt_d, rld_spacing_cnt_q: std_logic_vector(0 to 3); + +signal axi_load_ready : std_logic; +signal axi_load_valid : std_logic; +signal axi_load_id : std_logic_vector(C_M00_AXI_ID_WIDTH-1 downto 0); +signal axi_load_ra : std_logic_vector(C_M00_AXI_ADDR_WIDTH-1 downto 0); +signal axi_load_ra_hi : std_logic_vector(C_M00_AXI_ADDR_WIDTH-1 downto 6); +signal axi_load_ra_lo : std_logic_vector(5 downto 0); +signal axi_load_len : std_logic_vector(6 downto 0); +signal axi_load_mod : std_logic_vector(11 downto 0); + +signal axi_load_data_ready : std_logic; +signal axi_load_data_valid : std_logic; +signal axi_load_data_id : std_logic_vector(C_M00_AXI_ID_WIDTH-1 downto 0); +signal axi_load_data_resp : std_logic_vector(1 downto 0); +signal axi_load_data_last : std_logic; +signal axi_load_data : std_logic_vector(C_M00_AXI_DATA_WIDTH-1 downto 0); + +signal axi_store_valid : std_logic; +signal axi_store_id : std_logic_vector(C_M00_AXI_ID_WIDTH-1 downto 0); +signal axi_store_ra : std_logic_vector(C_M00_AXI_ADDR_WIDTH-1 downto 0); +signal axi_store_len : std_logic_vector(6 downto 0); +signal axi_store_mod : std_logic_vector(11 downto 0); + +signal axi_store_data_ready : std_logic; +signal axi_store_data_valid : std_logic; +signal axi_store_data : std_logic_vector(C_M00_AXI_DATA_WIDTH-1 downto 0); +signal axi_store_data_be : std_logic_vector(C_M00_AXI_DATA_WIDTH/8-1 downto 0); + +signal axi_store_rsp_ready : std_logic; +signal axi_store_rsp_valid : std_logic; +signal axi_store_rsp_id : std_logic_vector(C_M00_AXI_ID_WIDTH-1 downto 0); +signal axi_store_rsp_resp : std_logic_vector(1 downto 0); +signal store_complete : std_logic; + +signal store_data_in : std_logic_vector(0 to 127); +signal store_be_in : std_logic_vector(0 to 15); + +signal req_in: A2L2REQUEST; +signal req_clr : A2L2REQUEST; +signal ld_req: A2L2REQUEST; +signal req_in_load : std_logic; +signal load_len : std_logic_vector(6 downto 0); +signal ldq_oflow : std_logic; +signal ldq_uflow : std_logic; +signal ldq_count_sel: std_logic_vector(0 to 1); +signal axi_load_taken : std_logic; +signal load_queue_clr : A2L2REQUEST; +signal load_queue_fb : LOADQUEUE; +signal load_complete : std_logic; +signal ldq_valid_rst : std_logic_vector(0 to ld_queue_size-1); +signal ldq_sent_set : std_logic_vector(0 to ld_queue_size-1); +signal ldq_data_set : std_logic_vector(0 to ld_queue_size-1); +signal ldq_data_rst : std_logic_vector(0 to ld_queue_size-1); +signal rdataq_write_sel : std_logic_vector(0 to ld_queue_size*16-1); +signal rdataq_head_inc : std_logic_vector(0 to clog2(ld_queue_size*16)-1); +signal rld_single : std_logic; +signal rld_ready : std_logic; +signal rld_data_ready : std_logic; +signal rld_tag : std_logic_vector(0 to 4); +signal rld_len : std_logic_vector(0 to 2); +signal rld_ra_lo : std_logic_vector(0 to 3); +signal rdataq_head_sel : std_logic_vector(0 to 1); +signal rld_complete : std_logic; +signal rld_crit_qw : std_logic_vector(0 to 1); +signal rld_data_0 : std_logic_vector(0 to 31); +signal rld_data_1 : std_logic_vector(0 to 31); +signal rld_data_2 : std_logic_vector(0 to 31); +signal rld_data_3 : std_logic_vector(0 to 31); +signal rld_data_4 : std_logic_vector(0 to 31); +signal rld_data_5 : std_logic_vector(0 to 31); +signal rld_data_6 : std_logic_vector(0 to 31); +signal rld_data_7 : std_logic_vector(0 to 31); +signal rld_data_8 : std_logic_vector(0 to 31); +signal rld_data_9 : std_logic_vector(0 to 31); +signal rld_data_10 : std_logic_vector(0 to 31); +signal rld_data_11 : std_logic_vector(0 to 31); +signal rld_data_12 : std_logic_vector(0 to 31); +signal rld_data_13 : std_logic_vector(0 to 31); +signal rld_data_14 : std_logic_vector(0 to 31); +signal rld_data_15 : std_logic_vector(0 to 31); +signal rld_data_0_alg : std_logic_vector(0 to 31); +signal rld_data_1_alg : std_logic_vector(0 to 31); +signal rld_data_2_alg : std_logic_vector(0 to 31); +signal rld_data_3_alg : std_logic_vector(0 to 31); +signal rld_data_1_alg_single : std_logic_vector(0 to 31); +signal rld_data_2_alg_single : std_logic_vector(0 to 31); +signal rld_data_3_alg_single : std_logic_vector(0 to 31); +signal rld_data_1_use_0 : std_logic; +signal rld_data_2_use_0 : std_logic; +signal rld_data_3_use_0 : std_logic; +signal rld_data_3_use_1 : std_logic; +signal rld_data_qw0 : std_logic_vector(0 to 127); +signal rld_data_qw1 : std_logic_vector(0 to 127); +signal rld_data_qw2 : std_logic_vector(0 to 127); +signal rld_data_qw3 : std_logic_vector(0 to 127); +signal set_rld_spacing_cnt : std_logic; +signal rst_rld_spacing_cnt : std_logic; +signal rld_spacing_stall : std_logic; +signal rld_seq_err : std_logic; +signal rld_dseq_err : std_logic; +signal rld_data_valid : std_logic; +signal start_rld_data : std_logic; +signal rld_data_qw : std_logic_vector(0 to 1); +signal st_req_send : A2L2REQUEST; +signal st_req_data : A2L2REQUEST; +signal req_in_store: std_logic; +signal store_queue_clr : A2L2REQUEST; +signal store_queue_fb : STOREQUEUE; +signal store_data_queue_clr : A2L2STOREDATA; +signal st_data : A2L2STOREDATA; +signal stq_count_sel: std_logic_vector(0 to 1); +signal axi_store_ready : std_logic; +signal axi_store_taken : std_logic; +signal store_taken : std_logic; +signal store_advance : std_logic; +signal axi_store_data_taken : std_logic; +signal axi_store_data_last : std_logic; +signal stq_valid_rst : std_logic_vector(0 to st_queue_size-1); +signal stq_sent_set : std_logic_vector(0 to st_queue_size-1); +signal stq_data_rst : std_logic_vector(0 to st_queue_size-1); +signal st_data_last_xfer : std_logic; +signal st_data_xfer_hold : std_logic; +signal st_data_xfer_inc : std_logic; +signal st_data_xfer_done : std_logic; +signal stq_oflow : std_logic; +signal stq_uflow : std_logic; +signal req_in_spec: std_logic; +signal req_p1_addr_hit_lhs : std_logic_vector(0 to st_queue_size-1); +signal req_p1_sync_lhs : std_logic_vector(0 to st_queue_size-1); +signal req_p1_any_lhs: std_logic_vector(0 to st_queue_size-1); +signal req_p1_addr_hit_shl: std_logic_vector(0 to ld_queue_size-1); +signal req_p1_sync_shl: std_logic_vector(0 to ld_queue_size-1); +signal req_p1_any_shl: std_logic_vector(0 to ld_queue_size-1); +signal ld_req_stall: std_logic; +signal st_req_stall: std_logic; +signal load_queue_set_dep : std_logic_vector(0 to ld_queue_size-1); +signal load_queue_rst_dep : std_logic_vector(0 to ld_queue_size-1); +signal store_queue_set_dep : std_logic_vector(0 to st_queue_size-1); +signal store_queue_rst_dep : std_logic_vector(0 to st_queue_size-1); +signal lhs_ordered : std_logic_vector(0 to st_queue_size-1); +signal lhs_ordered_youngest : std_logic_vector(0 to st_queue_size-1); +signal lhs_youngest : std_logic_vector(0 to st_queue_size-1); +signal lhs_entry : std_logic_vector(0 to 1+clog2(st_queue_size)-1); +signal shl_ordered : std_logic_vector(0 to ld_queue_size-1); +signal shl_ordered_youngest : std_logic_vector(0 to ld_queue_size-1); +signal shl_youngest : std_logic_vector(0 to ld_queue_size-1); +signal shl_entry : std_logic_vector(0 to 1+clog2(ld_queue_size)-1); +signal reload_clr : A2L2RELOAD; +signal resv_clr : A2L2RESV; +signal status_clr : A2L2STATUS; +signal req_ra_line : std_logic_vector(64-xu_real_data_add to 59); +signal larx_t : std_logic_vector(0 to 3); +signal stcx_t : std_logic_vector(0 to 3); +signal store_t : std_logic_vector(0 to 3); +signal stcx_store_t : std_logic_vector(0 to 3); +signal resv_ra_hit : std_logic_vector(0 to 3); +signal resv_set : std_logic_vector(0 to 3); +signal resv_rst : std_logic_vector(0 to 3); +signal store_spec_valid : std_logic; +signal lwsync_complete : std_logic; +signal hwsync_complete : std_logic; +signal store_spec_complete : std_logic; +signal hwsync_valid : std_logic; +signal lwsync_valid : std_logic; +signal store_pop_delayed : std_logic; +signal store_rsp_complete : std_logic; +signal store_pop_pending_sel : std_logic_vector(0 to 2); +signal ld_dep: std_logic_vector(0 to clog2(st_queue_size)); +signal st_dep: std_logic_vector(0 to clog2(ld_queue_size)); + +begin + +req_clr <= (valid => '0', sent => '0', data => '0', dseq => (others => '0'), endian => '0', tag => (others => '0'), len => (others => '0'), + ra => (others => '0'), thread => (others => '0'), ditc => '0', spec => '0', ttype => (others => '0'), user => (others => '0'), wimg => (others => '0'), hwsync => '0'); +load_queue_clr <= req_clr; +reload_clr <= (valid => '0', coming => '0', tag => (others => '0'), data => (others => '0'), qw => (others => '0'), crit => '0', dump => '0', ee => '0', ue => '0'); +store_queue_clr <= req_clr; +store_data_queue_clr <= (data => (others => '0'), be => (others => '0')); +status_clr <= (ld_pop => '0', st_pop => '0', st_pop_thrd => (others => '0'), gather => '0', res_valid => (others => '0'), stcx_complete => (others => '0'), + stcx_pass => (others => '0'), sync_ack => (others => '0')); +resv_clr <= (valid => '0', ra => (others => '0')); + +FF: process(clk) begin + +if rising_edge(clk) then + + if reset_n = '0' then + + req_pwr_q <= '0'; + req_p1_q <= req_clr; + ld_p1_entry_q <= (others => '0'); + st_p1_entry_q <= (others => '0'); + rld_seq_q <= (others => '1'); + rld_dseq_q <= (others => '1'); + ldq_count_q <= (others => '0'); + ldq_head_q <= (others => '0'); + ldq_send_q <= (others => '0'); + ldq_data_q <= (others => '0'); + ldq_tail_q <= (others => '0'); + for i in 0 to ld_queue_size*16-1 loop + load_data_queue_q(i) <= (others => '0'); + end loop; + rdataq_head_q <= (others => '0'); + rdataq_tail_q <= (others => '0'); + reload_q <= reload_clr; + rld_spacing_q <= rld_spacing; + rld_spacing_cnt_q <= (others => '0'); + store_pwr_q <= '0'; + for i in 0 to ld_queue_size-1 loop + load_queue_q(i) <= load_queue_clr; + load_dep_q(i) <= (others => '0'); + end loop; + for i in 0 to st_queue_size-1 loop + store_queue_q(i) <= store_queue_clr; + store_data_queue_q(i) <= store_data_queue_clr; + store_dep_q(i) <= (others => '0'); + end loop; + stq_count_q <= (others => '0'); + stq_head_q <= (others => '0'); + stq_send_q <= (others => '0'); + stq_data_q <= (others => '0'); + stq_tail_q <= (others => '0'); + st_data_xfer_q <= (others => '0'); + store_pop_pending_q <= (others => '0'); + status_q <= status_clr; + for i in 0 to 3 loop + resv_q(i) <= resv_clr; + end loop; + load_data_ready_q <= '0'; + store_rsp_ready_q <= '0'; + err_q <= (others => '0'); + + else + + req_pwr_q <= req_pwr_d; + req_p1_q <= req_p1_d; + ld_p1_entry_q <= ld_p1_entry_d; + st_p1_entry_q <= st_p1_entry_d; + rld_seq_q <= rld_seq_d; + rld_dseq_q <= rld_dseq_d; + ldq_count_q <= ldq_count_d; + ldq_head_q <= ldq_head_d; + ldq_send_q <= ldq_send_d; + ldq_data_q <= ldq_data_d; + ldq_tail_q <= ldq_tail_d; + for i in 0 to ld_queue_size*16-1 loop + load_data_queue_q(i) <= load_data_queue_d(i); + end loop; + rdataq_head_q <= rdataq_head_d; + rdataq_tail_q <= rdataq_tail_d; + reload_q <= reload_d; + rld_spacing_q <= rld_spacing_d; + rld_spacing_cnt_q <= rld_spacing_cnt_d; + store_pwr_q <= store_pwr_d; + for i in 0 to ld_queue_size-1 loop + load_queue_q(i) <= load_queue_d(i); + load_dep_q(i) <= load_dep_d(i); + end loop; + for i in 0 to st_queue_size-1 loop + store_queue_q(i) <= store_queue_d(i); + store_data_queue_q(i) <= store_data_queue_d(i); + store_dep_q(i) <= store_dep_d(i); + end loop; + stq_count_q <= stq_count_d; + stq_head_q <= stq_head_d; + stq_send_q <= stq_send_d; + stq_data_q <= stq_data_d; + stq_tail_q <= stq_tail_d; + st_data_xfer_q <= st_data_xfer_d; + store_pop_pending_q <= store_pop_pending_d; + status_q <= status_d; + for i in 0 to 3 loop + resv_q(i) <= resv_d(i); + end loop; + load_data_ready_q <= load_data_ready_d; + store_rsp_ready_q <= store_rsp_ready_d; + err_q <= err_d; + + end if; + +end if; + +end process FF; + +------------------------------------------------------------------------------------------------------------ +-- Init +-- credits are initially set in core + +------------------------------------------------------------------------------------------------------------ +-- Process request +-- + +req_pwr_d <= ac_an_req_pwr_token; + +req_in.valid <= ac_an_req and req_pwr_q; +req_in.sent <= '0'; +req_in.data <= '0'; +req_in.endian <= ac_an_req_endian; +req_in.tag <= ac_an_req_ld_core_tag; +req_in.len <= ac_an_req_ld_xfr_len; +req_in.ra <= ac_an_req_ra; +req_in.thread <= ac_an_req_thread(0 to 1); +req_in.ditc <= ac_an_req_thread(2); +req_in.spec <= req_in_spec; +req_in.ttype <= ac_an_req_ttype; +req_in.user <= ac_an_req_user_defined; +req_in.wimg <= ac_an_req_wimg_w & ac_an_req_wimg_i & ac_an_req_wimg_m & ac_an_req_wimg_g; +req_in.hwsync <= req_in.spec; + +--tbl ReqDcd +-- +--n req_in.valid req_in_load +--n | req_in.ttype |req_in_store +--n | | req_in.thread ||req_in_spec +--n | | | ||| +--n | | | ||| larx_t +--n | | | ||| | stcx_t +--n | | | ||| | | store_t +--n | | | ||| | | | +--n | | | ||| | | | +--n | | | ||| | | | +--b | 012345 01 ||| 0123 0123 0123 +--t i iiiiii ii ooo oooo oooo oooo +--*------------------------------------------------------------------------------------------------------------------- +--s 0 ------ -- 000 0000 0000 0000 +--* Loads ------------------------------------------------------------------------------------------------------------ +--s 1 000000 -- 100 0000 0000 0000 * ifetch +--s 1 000001 -- 100 0000 0000 0000 * ifetch pre +--s 1 001000 -- 100 0000 0000 0000 * load +--* Stores ----------------------------------------------------------------------------------------------------------- +--s 1 100000 00 010 0000 0000 1000 * store +--s 1 100000 01 010 0000 0000 0100 * store +--s 1 100000 10 010 0000 0000 0010 * store +--s 1 100000 11 010 0000 0000 0001 * store +--* Larx/Stcx -------------------------------------------------------------------------------------------------------- +--s 1 001001 00 100 1000 0000 0000 * larx +--s 1 001001 01 100 0100 0000 0000 * larx +--s 1 001001 10 100 0010 0000 0000 * larx +--s 1 001001 11 100 0001 0000 0000 * larx +--* 1 001011 00 000 1000 0000 0000 * larx hint +--* 1 001011 01 000 0100 0000 0000 * larx hint +--* 1 001011 10 000 0010 0000 0000 * larx hint +--* 1 001011 11 000 0001 0000 0000 * larx hint +--s 1 101001 00 010 0000 1000 0000 * stcx +--s 1 101001 01 010 0000 0100 0000 * stcx +--s 1 101001 10 010 0000 0010 0000 * stcx +--s 1 101001 11 010 0000 0001 0000 * stcx +--* Specials --------------------------------------------------------------------------------------------------------- +--s 1 101010 -- 011 0000 0000 0000 * lwsync +--s 1 101011 -- 011 0000 0000 0000 * hwsync +--s 1 111010 -- 011 0000 0000 0000 * tlbsync +--s 1 111111 -- 011 0000 0000 0000 * dcbi +--*------------------------------------------------------------------------------------------------------------------- +-- +--tbl ReqDcd + +------------------------------------------------------------------------------------------------------------ +-- Load Request +-- +-- push load to load queue +-- head: oldest +-- send: next to send +-- data: next to receive data +-- tail: next to write + +with req_in_load select + ldq_tail_d <= inc(ldq_tail_q) when '1', + ldq_tail_q when others; + +-- feedback +gen_load_queue_fb: for i in 0 to ld_queue_size-1 generate + + load_queue_fb(i).valid <= load_queue_q(i).valid and not ldq_valid_rst(i); + load_queue_fb(i).sent <= (load_queue_q(i).sent or ldq_sent_set(i)) and not ldq_valid_rst(i); + load_queue_fb(i).data <= (load_queue_q(i).data or ldq_data_set(i)) and not ldq_data_rst(i); + load_queue_fb(i).dseq <= "000"; -- might use if interleaving data returns + load_queue_fb(i).endian <= load_queue_q(i).endian; + load_queue_fb(i).tag <= load_queue_q(i).tag; + load_queue_fb(i).len <= load_queue_q(i).len; + load_queue_fb(i).ra <= load_queue_q(i).ra; + load_queue_fb(i).thread <= load_queue_q(i).thread; + load_queue_fb(i).ditc <= load_queue_q(i).ditc; + load_queue_fb(i).spec <= load_queue_q(i).spec; + load_queue_fb(i).ttype <= load_queue_q(i).ttype; + load_queue_fb(i).user <= load_queue_q(i).user; + load_queue_fb(i).wimg <= load_queue_q(i).wimg; + load_queue_fb(i).hwsync <= load_queue_q(i).hwsync; + + load_dep_d(i) <= gate_and(load_queue_set_dep(i), lhs_entry) or + gate_and(not load_queue_set_dep(i) and not load_queue_rst_dep(i), load_dep_q(i)); +end generate; + +gen_load_queue: for i in 0 to ld_queue_size-1 generate + + load_queue_d(i) <= req_in when b(req_in_load and eq(ldq_tail_q, i)) else load_queue_fb(i); + +end generate; + +axi_load_id <= "0000"; + +ld_req <= mux_queue(load_queue_q, ldq_send_q); +ld_dep <= mux_queue(load_dep_q, ldq_send_q); + +-- send next available load to axi if ready and no stall +axi_load_valid <= ld_req.valid and not ld_req.sent and not ld_req_stall; + +-- i=0 is always 64B; i=1 uses len +axi_load_ra_hi <= ld_req.ra(64-C_M00_AXI_ADDR_WIDTH to 57); +with ld_req.wimg(1) select + axi_load_ra_lo <= "000000" when '0', + ld_req.ra(58 to 63) when others; +axi_load_ra <= axi_load_ra_hi & axi_load_ra_lo; + +axi_load_mod <= "000000000000"; + +with ld_req.len select + load_len <= "0000001" when "001", + "0000010" when "010", + "0000100" when "100", + "0001000" when "101", + "0010000" when "110", + "0100000" when others; + +with ld_req.wimg(1) select + axi_load_len <= load_len when '1', + "1000000" when others; + +axi_load_taken <= axi_load_valid and axi_load_ready; + +-- sent: set when req accepted by axi +gen_ldq_sent: for i in 0 to ld_queue_size-1 generate + ldq_sent_set(i) <= axi_load_taken and eq(ldq_send_q, i); +end generate; + +with axi_load_taken select + ldq_send_d <= inc(ldq_send_q) when '1', + ldq_send_q when others; + +-- data: set when last xfer received from axi +gen_load_data_set: for i in 0 to ld_queue_size-1 generate + ldq_data_set(i) <= axi_load_data_last and eq(ldq_data_q, i); +end generate; + +with axi_load_data_last select + ldq_data_d <= inc(ldq_data_q) when '1', + ldq_data_q when others; + +with load_complete select + ldq_head_d <= inc(ldq_head_q) when '1', + ldq_head_q when others; + +ldq_count_sel <= req_in_load & load_complete; +with ldq_count_sel select + ldq_count_d <= inc(ldq_count_q) when "10", + dec(ldq_count_q) when "01", + ldq_count_q when others; + +ldq_oflow <= eq(ldq_count_q, ld_queue_size) and eq(ldq_count_sel, "10"); +ldq_uflow <= eq(ldq_count_q, 0) and eq(ldq_count_sel, "01"); + +------------------------------------------------------------------------------------------------------------ +-- Load Data Receive +-- +-- head: next to send +-- tail: next to write + +load_data_ready_d <= '1'; +axi_load_data_ready <= load_data_ready_q; + +with axi_load_data_valid select + rdataq_tail_d <= inc(rdataq_tail_q) when '1', + rdataq_tail_q when others; + + +-- axi_load_data_resp: check + +gen_load_load_data_queue: for i in 0 to ld_queue_size*16-1 generate + rdataq_write_sel(i) <= axi_load_data_valid and eq(rdataq_tail_q, i); + with rdataq_write_sel(i) select + load_data_queue_d(i) <= axi_load_data(7 downto 0) & axi_load_data(15 downto 8) & axi_load_data(23 downto 16) & axi_load_data(31 downto 24) when '1', + load_data_queue_q(i) when others; +end generate; + +------------------------------------------------------------------------------------------------------------ +-- Load Data Send +-- +-- each 16B xfer uses top 4 entries, swizzled for LE/BE if necessary +-- a2l2 supports 2 main modes of return: alternating or consecutive; it also allows variable gaps between pairs of xfers for 64B +-- crit qw can be returned first; only certain qw ordering is allowed (pairs must be consecutive): +-- 0-1-2-3, 0-1-3-2 +-- 1-0-2-3, 1-0-3-2 +-- 2-3-0-1, 2-3-1-0 +-- 3-2-0-1, 3-2-1-0 +-- gaps can be filled with other xfers +-- +-- use 'consecutive' mode and crit first +-- ra(58:59) selects first rdataq to send; then use 0-1-2-3, 1-0-2-3, 2-3-0-1, 3-2-0-1 patterns + +rld_head <= mux_queue(load_queue_q, ldq_head_q); +rld_data_valid <= rld_head.valid and rld_head.data; +rld_tag <= rld_head.tag; +rld_single <= rld_head.wimg(1); +rld_crit_qw <= rld_head.ra(58 to 59); +rld_len <= rld_head.len; +rld_ra_lo <= rld_head.ra(60 to 63); + + +reload_d.tag <= rld_tag; +reload_d.ue <= '0'; +reload_d.ee <= '0'; +reload_d.dump <= '0'; + +-- debug +-- insert cycles between reld data -> next reld coming +rld_spacing_d <= rld_spacing_q; +rst_rld_spacing_cnt <= eq(rld_spacing_q, rld_spacing_cnt_q); +set_rld_spacing_cnt <= rld_complete and ne(rld_spacing_q, 0); +rld_spacing_cnt_d <= gate_and(rst_rld_spacing_cnt, "0000") or + gate_and(set_rld_spacing_cnt, "0001") or + gate_and(not rst_rld_spacing_cnt and not set_rld_spacing_cnt, inc(rld_spacing_cnt_q)); +rld_spacing_stall <= ne(rld_spacing_cnt_q, 0); + +rld_ready <= rld_data_valid and not rld_spacing_stall; -- entry ready; fastpath doesn't work without peeking at next entry for crit_qw,single for seq (or axi_load_data_last) + +-- data: reset in d-1 +gen_load_data_rst: for i in 0 to ld_queue_size-1 generate + ldq_data_rst(i) <= start_rld_data and eq(ldq_head_q, i); +end generate; + +--tbl RldSeq +-- +--n rld_seq_q rld_seq_d +--n | | +--n | rld_ready | reload_d.coming +--n | | rld_crit_qw | |reload_d.valid +--n | | | rld_single | ||reload_d.qw +--n | | | | | ||| reload_d.crit +--n | | | | | ||| | start_rld_data +--n | | | | | ||| | | +--n | | | | | ||| | | rld_seq_err +--b | | | | | ||55| | | +--b 01234 | 01 | 01234 ||89| | | +--t iiiii i ii i ooooo ooooo o o +--*------------------------------------------------------------------------------------------------------------------- +--*-- Idle ----------------------------------------------------------------------------------------------------------- +--s 11111 0 -- - 11111 00000 0 0 +--s 11111 1 00 0 10000 10000 0 0 +--s 11111 1 01 0 10010 10000 0 0 +--s 11111 1 10 0 10100 10000 0 0 +--s 11111 1 11 0 10110 10000 0 0 +--s 11111 1 00 1 00001 10000 0 0 +--s 11111 1 01 1 00010 10000 0 0 +--s 11111 1 10 1 00011 10000 0 0 +--s 11111 1 11 1 00100 10000 0 0 +--*-- Single a 00 ------------------------------------------------------------------------------------------------------- +--s 00001 - -- - 00110 01001 0 0 * d-3 +--*-- Single a 01 ------------------------------------------------------------------------------------------------------- +--s 00010 - -- - 00110 01011 0 0 * d-3 +--*-- Single a 10 ------------------------------------------------------------------------------------------------------- +--s 00011 - -- - 00110 01101 0 0 * d-3 +--*-- Single a 11 ------------------------------------------------------------------------------------------------------- +--s 00100 - -- - 00110 01111 0 0 * d-3 +--*-- Single b ------------------------------------------------------------------------------------------------------- +--s 00110 - -- - 00111 00000 0 0 * d-2 +--*-- Single c ------------------------------------------------------------------------------------------------------- +--s 00111 - -- - 11111 00000 1 0 * d-1 +--*-- Crit 0a -------------------------------------------------------------------------------------------------------- +--s 10000 - -- - 10001 01001 0 0 * d-3 +--*-- Crit 0b -------------------------------------------------------------------------------------------------------- +--s 10001 - -- - 11010 11010 0 0 * d-2 +--*-- Crit 1a -------------------------------------------------------------------------------------------------------- +--s 10010 - -- - 10011 01011 0 0 * d-3 +--*-- Crit 1b -------------------------------------------------------------------------------------------------------- +--s 10011 - -- - 11010 11000 0 0 * d-2 +--*-- Crit 2a -------------------------------------------------------------------------------------------------------- +--s 10100 - -- - 10101 01101 0 0 * d-3 +--*-- Crit 2b -------------------------------------------------------------------------------------------------------- +--s 10101 - -- - 11000 11110 0 0 * d-2 +--*-- Crit 3a -------------------------------------------------------------------------------------------------------- +--s 10110 - -- - 10111 01111 0 0 * d-3 +--*-- Crit 3b -------------------------------------------------------------------------------------------------------- +--s 10111 - -- - 11000 11100 0 0 * d-2 +--*-- 2nd 01a -------------------------------------------------------------------------------------------------------- +--s 11000 - -- - 11001 01000 1 0 * d-1 +--*-- 2nd 01b -------------------------------------------------------------------------------------------------------- +--s 11001 - -- - 11111 01010 0 0 * d+0 +--*-- 2nd 23a -------------------------------------------------------------------------------------------------------- +--s 11010 - -- - 11011 01100 1 0 * d-1 +--*-- 2nd 23b -------------------------------------------------------------------------------------------------------- +--s 11011 - -- - 11111 01110 0 0 * d+0 +--*-- ERROR ---------------------------------------------------------------------------------------------------------- +--s 00000 - -- - 00000 00000 0 1 +--s 00101 - -- - 00101 00000 0 1 +--s 11100 - -- - 11100 00000 0 1 +--s 11101 - -- - 11101 00000 0 1 +--s 11110 - -- - 11110 00000 0 1 +--*------------------------------------------------------------------------------------------------------------------- +--tbl RldSeq + +--tbl RldDataSeq +-- +--n rld_dseq_q rld_dseq_d +--n | | +--n | start_rld_data | rld_data_qw +--n | | rld_crit_qw | | rld_complete +--n | | | rld_single | | | +--n | | | | | | | +--n | | | | | | | +--n | | | | | | | +--n | | | | | | | +--n | | | | | | | rld_dseq_err +--b 0123 | 01 | 0123 01 | | +--t iiii i ii i oooo oo o o +--*------------------------------------------------------------------------------------------------------------------- +--*-- Idle ----------------------------------------------------------------------------------------------------------- +--s 1111 0 -- - 1111 00 0 0 * zzz..zzz.... +--s 1111 1 00 0 0001 00 0 0 * 0-1-2-3 +--s 1111 1 01 0 0010 01 0 0 * 1-0-2-3 +--s 1111 1 10 0 0011 10 0 0 * 2-3-0-1 +--s 1111 1 11 0 0100 11 0 0 * 3-2-0-1 +--s 1111 1 -- 1 1111 00 1 0 * single xfer +--*-- 2nd 01 --------------------------------------------------------------------------------------------------------- +--s 0001 - -- - 1011 01 0 0 * d+0 +--*-- 2nd 10 --------------------------------------------------------------------------------------------------------- +--s 0010 - -- - 1011 00 0 0 * d+0 +--*-- 2nd 23 --------------------------------------------------------------------------------------------------------- +--s 0011 - -- - 1001 11 0 0 * d+0 +--*-- 2nd 32 --------------------------------------------------------------------------------------------------------- +--s 0100 - -- - 1001 10 0 0 * d+0 +--*-- 3rd 01 --------------------------------------------------------------------------------------------------------- +--s 1001 - -- - 1010 00 0 0 * d+1 +--*-- 4th 01 --------------------------------------------------------------------------------------------------------- +--s 1010 - -- - 1111 01 1 0 * d+2 +--*-- 3rd 23 --------------------------------------------------------------------------------------------------------- +--s 1011 - -- - 1100 10 0 0 * d+1 +--*-- 4th 23 --------------------------------------------------------------------------------------------------------- +--s 1100 - -- - 1111 11 1 0 * d+2 +--*-- ERROR ---------------------------------------------------------------------------------------------------------- +--s 0000 - -- - 0000 00 0 1 +--s 0101 - -- - 0101 00 0 1 +--s 0110 - -- - 0110 00 0 1 +--s 0111 - -- - 0111 00 0 1 +--s 1000 - -- - 1000 00 0 1 +--s 1101 - -- - 1101 00 0 1 +--s 1110 - -- - 1110 00 0 1 +--*------------------------------------------------------------------------------------------------------------------- +--tbl RldDataSeq + +load_complete <= rld_complete; + +gen_ldq_valid_rst: for i in 0 to ld_queue_size-1 generate + ldq_valid_rst(i) <= load_complete and eq(ldq_head_q, i); +end generate; + +status_d.ld_pop <= load_complete; + +-- send reload +an_ac_reld_data_coming <= reload_q.coming; +an_ac_reld_data_vld <= reload_q.valid; +an_ac_reld_core_tag <= reload_q.tag; +an_ac_reld_qw <= reload_q.qw; +an_ac_reld_crit_qw <= reload_q.crit; +an_ac_reld_ecc_err <= reload_q.ee; +an_ac_reld_ecc_err_ue <= reload_q.ue; +an_ac_reld_l1_dump <= reload_q.dump; +an_ac_reld_data <= reload_q.data; + +-- misc outputs +an_ac_req_ld_pop <= status_q.ld_pop; +an_ac_req_st_pop <= status_q.st_pop; +an_ac_req_st_pop_thrd <= status_q.st_pop_thrd; +an_ac_req_st_gather <= status_q.gather; +an_ac_reservation_vld <= status_q.res_valid; +an_ac_stcx_complete <= status_q.stcx_complete; +an_ac_stcx_pass <= status_q.stcx_pass; +an_ac_sync_ack <= status_q.sync_ack; + +rdataq_head_sel <= rld_complete & rld_single; + +with rld_len select + rdataq_head_inc <= inc(rdataq_head_q, 1) when "001", + inc(rdataq_head_q, 1) when "010", + inc(rdataq_head_q, 1) when "100", + inc(rdataq_head_q, 2) when "101", + inc(rdataq_head_q, 4) when others; + +with rdataq_head_sel select + rdataq_head_d <= rdataq_head_inc when "11", + inc(rdataq_head_q, 16) when "10", + rdataq_head_q when others; + +--rld_data_0/1 need to be shifted in position for 1,2,4,8 byte reads +--it has to be in the right position within 16B +-- len=1,2,4 are 4B axi reads +-- len=5 is 8B axi read +rld_data_0 <= mux_queue(load_data_queue_q, rdataq_head_q); +rld_data_1 <= mux_queue(load_data_queue_q, inc(rdataq_head_q, 1)); +rld_data_2 <= mux_queue(load_data_queue_q, inc(rdataq_head_q, 2)); +rld_data_3 <= mux_queue(load_data_queue_q, inc(rdataq_head_q, 3)); + +-- data0 always aligned +rld_data_0_alg <= rld_data_0; + +-- align to data1 if: +-- len=1 and lo=4/5/6/7 +-- len=2 and lo=4/6 +-- len=4 and lo=4 +rld_data_1_use_0 <= b(((rld_len = "001") or (rld_len = "010") or (rld_len = "100")) and + (rld_ra_lo(1) = '1')); + +with rld_data_1_use_0 select + rld_data_1_alg_single <= rld_data_0 when '1', + rld_data_1 when others; + +with rld_single select + rld_data_1_alg <= rld_data_1_alg_single when '1', + rld_data_1 when others; + +-- align to data2 if: +-- len=1 and lo=8/9/A/B +-- len=2 and lo=8/A +-- len=4 and lo=8 +-- len=8 and lo=8 + +rld_data_2_use_0 <= b(((rld_len = "001") or (rld_len = "010") or (rld_len = "100") or (rld_len = "101")) and + (rld_ra_lo(0) = '1')); + +with rld_data_2_use_0 select + rld_data_2_alg_single <= rld_data_0 when '1', + rld_data_2 when others; + +with rld_single select + rld_data_2_alg <= rld_data_2_alg_single when '1', + rld_data_2 when others; + +-- align to data3 if: +-- len=1 and lo=C/D/E/F +-- len=2 and lo=C/E +-- len=4 and lo=C +-- len=8 and lo=8 + +rld_data_3_use_0 <= b(((rld_len = "001") or (rld_len = "010") or (rld_len = "100")) and + (rld_ra_lo(0) = '1')); + +rld_data_3_use_1 <= b((rld_len = "101") and (rld_ra_lo(0) = '1')); + +rld_data_3_alg_single <= gate_and(rld_data_3_use_0, rld_data_0) or + gate_and(rld_data_3_use_1, rld_data_1) or + gate_and(not rld_data_3_use_0 and not rld_data_3_use_1, rld_data_3); + +with rld_single select + rld_data_3_alg <= rld_data_3_alg_single when '1', + rld_data_3 when others; + +rld_data_4 <= mux_queue(load_data_queue_q, inc(rdataq_head_q, 4)); +rld_data_5 <= mux_queue(load_data_queue_q, inc(rdataq_head_q, 5)); +rld_data_6 <= mux_queue(load_data_queue_q, inc(rdataq_head_q, 6)); +rld_data_7 <= mux_queue(load_data_queue_q, inc(rdataq_head_q, 7)); +rld_data_8 <= mux_queue(load_data_queue_q, inc(rdataq_head_q, 8)); +rld_data_9 <= mux_queue(load_data_queue_q, inc(rdataq_head_q, 9)); +rld_data_10 <= mux_queue(load_data_queue_q, inc(rdataq_head_q, 10)); +rld_data_11 <= mux_queue(load_data_queue_q, inc(rdataq_head_q, 11)); +rld_data_12 <= mux_queue(load_data_queue_q, inc(rdataq_head_q, 12)); +rld_data_13 <= mux_queue(load_data_queue_q, inc(rdataq_head_q, 13)); +rld_data_14 <= mux_queue(load_data_queue_q, inc(rdataq_head_q, 14)); +rld_data_15 <= mux_queue(load_data_queue_q, inc(rdataq_head_q, 15)); + +rld_data_qw0 <= rld_data_0_alg & rld_data_1_alg & rld_data_2_alg & rld_data_3_alg; +rld_data_qw1 <= rld_data_4 & rld_data_5 & rld_data_6 & rld_data_7; +rld_data_qw2 <= rld_data_8 & rld_data_9 & rld_data_10 & rld_data_11; +rld_data_qw3 <= rld_data_12 & rld_data_13 & rld_data_14 & rld_data_15; + +with rld_data_qw select + reload_d.data <= rld_data_qw0 when "00", + rld_data_qw1 when "01", + rld_data_qw2 when "10", + rld_data_qw3 when others; + +------------------------------------------------------------------------------------------------------------ +-- Store Request +-- +-- push store to store queue +-- head: oldest +-- send: next to send +-- data: next to send data +-- tail: next to write +-- +-- special stores are not sent to axi directly + +store_pwr_d <= ac_an_st_data_pwr_token; + +with req_in_store select + stq_tail_d <= inc(stq_tail_q) when '1', + stq_tail_q when others; + +-- feedback +gen_store_queue_fb: for i in 0 to st_queue_size-1 generate + + store_queue_fb(i).valid <= store_queue_q(i).valid and not stq_valid_rst(i); + store_queue_fb(i).sent <= store_queue_q(i).sent or stq_sent_set(i); + store_queue_fb(i).data <= (store_queue_q(i).data or stq_sent_set(i)) and not stq_data_rst(i); + store_queue_fb(i).dseq <= "000"; + store_queue_fb(i).endian <= store_queue_q(i).endian; + store_queue_fb(i).tag <= store_queue_q(i).tag; + store_queue_fb(i).len <= store_queue_q(i).len; + store_queue_fb(i).ra <= store_queue_q(i).ra; + store_queue_fb(i).thread <= store_queue_q(i).thread; + store_queue_fb(i).ditc <= store_queue_q(i).ditc; + store_queue_fb(i).spec <= store_queue_q(i).spec; + store_queue_fb(i).ttype <= store_queue_q(i).ttype; + store_queue_fb(i).user <= store_queue_q(i).user; + store_queue_fb(i).wimg <= store_queue_q(i).wimg; + store_queue_fb(i).hwsync <= store_queue_q(i).hwsync; + + store_dep_d(i) <= gate_and(store_queue_set_dep(i), shl_entry) or + gate_and(not store_queue_set_dep(i) and not store_queue_rst_dep(i), store_dep_q(i)); + +end generate; + +-- store queue +gen_store_queue: for i in 0 to st_queue_size-1 generate + + store_queue_d(i) <= req_in when b(req_in_store and eq(stq_tail_q, i)) else store_queue_fb(i); + +end generate; + +axi_store_id <= "0000"; -- could use this to allow d/i fetch/prefetch reordering + +st_req_send <= mux_queue(store_queue_q, stq_send_q); +st_dep <= mux_queue(store_dep_q, stq_send_q); + +-- send next available store to axi if ready and no stall +axi_store_valid <= st_req_send.valid and not st_req_send.spec and not st_req_send.sent and not st_req_stall; +axi_store_mod <= "000000000000"; + +-- all 16B stores for now +axi_store_ra <= st_req_send.ra(64-C_M00_AXI_ADDR_WIDTH to 59) & "0000"; + +-- assume even if using 32B interface, all stores are 16B or less +-- so can mux lo/hi data/be +-- it appears the mux'ing is not necessary; the data is dup'd hi/lo (so far at least); +-- BUT, the BE need to be looked at across all bits (need to mux based on bit 59) + +gen_store_len_16B: if st_data_32b_mode = 0 generate + store_data_in <= ac_an_st_data; + store_be_in <= ac_an_st_byte_enbl; +end generate; +gen_store_len_32B: if st_data_32b_mode = 1 generate +-- a2 only gens 16B stores unless it has bgq fpu +-- but need to still pick data/BE from proper bytes + with req_in.ra(59) select + store_data_in <= ac_an_st_data(128 to 255) when '1', + ac_an_st_data(0 to 127) when others; + with req_in.ra(59) select + store_be_in <= ac_an_st_byte_enbl(16 to 31) when '1', + ac_an_st_byte_enbl(0 to 15) when others; +end generate; + +-- special store handling +-- +-- syncs: +-- go through valid-send-data stages, then autocomplete +-- hwsync: +-- dep vs ldq (wait for older loads) +-- stall self until head (wait for older stores) +-- hold send pointer until complete (no younger store will be sent) +-- +-- dcbi: +-- like normal lwsync + +store_spec_valid <= st_req_send.valid and st_req_send.spec; + +hwsync_valid <= store_spec_valid and st_req_send.hwsync; + +lwsync_valid <= store_spec_valid and + (eq(st_req_send.ttype, LWSYNC) or + eq(st_req_send.ttype, MBAR) or + eq(st_req_send.ttype, TLBSYNC) or + eq(st_req_send.ttype, DCBI)); + +axi_store_taken <= axi_store_valid and axi_store_ready; +-- store to axi, or spec +store_taken <= axi_store_taken or (store_spec_valid and not st_req_stall); + +gen_stq_sent: for i in 0 to st_queue_size-1 generate + stq_sent_set(i) <= store_taken and eq(stq_send_q, i); +end generate; + +store_advance <= (store_taken and not hwsync_valid) or hwsync_complete; + +-- inc to next entry +with store_advance select + stq_send_d <= inc(stq_send_q) when '1', + stq_send_q when others; + +------------------------------------------------------------------------------------------------------------ +-- Store Data +-- +-- add modes so that aw+w or aw+w+b must be completed before next aw + +gen_store_data_queue: for i in 0 to st_queue_size-1 generate + store_data_queue_d(i) <= (data => store_data_in, be => store_be_in) when b(req_in_store and eq(stq_tail_q, i)) else store_data_queue_q(i); +end generate; + +st_req_data <= mux_queue(store_queue_q, stq_data_q); +st_data <= mux_queue(store_data_queue_q, stq_data_q); + +-- send next available store data to axi if ready +axi_store_data_valid <= st_req_data.valid and st_req_data.data and not st_req_data.spec; + +axi_store_data_taken <= axi_store_data_valid and axi_store_data_ready; + +st_data_xfer_inc <= axi_store_data_taken and not st_data_last_xfer; +st_data_xfer_done <= axi_store_data_taken and st_data_last_xfer; +st_data_xfer_hold <= not st_data_xfer_inc and not st_data_xfer_done; + +st_data_xfer_d <= gate_and(st_data_xfer_inc, inc(st_data_xfer_q)) or + gate_and(st_data_xfer_done, "000") or + gate_and(st_data_xfer_hold, st_data_xfer_q); + +-- this can be done smarter if BE are examined; transfer 4/8/16 based on hi/lo be +gen_store_data_16B: if not stores_32B generate + +axi_store_len <= "0010000"; +st_data_last_xfer <= eq(st_data_xfer_q, "011"); + +with st_data_xfer_q select + axi_store_data <= st_data.data(24 to 31) & st_data.data(16 to 23) & st_data.data(8 to 15) & st_data.data(0 to 7) when "000", + st_data.data(56 to 63) & st_data.data(48 to 55) & st_data.data(40 to 47) & st_data.data(32 to 39) when "001", + st_data.data(88 to 95) & st_data.data(80 to 87) & st_data.data(72 to 79) & st_data.data(64 to 71) when "010", + st_data.data(120 to 127) & st_data.data(112 to 119) & st_data.data(104 to 111) & st_data.data(96 to 103) when others; + +with st_data_xfer_q select + axi_store_data_be <= st_data.be( 3) & st_data.be( 2) & st_data.be( 1) & st_data.be( 0) when "000", + st_data.be( 7) & st_data.be( 6) & st_data.be( 5) & st_data.be( 4) when "001", + st_data.be(11) & st_data.be(10) & st_data.be( 9) & st_data.be( 8) when "010", + st_data.be(15) & st_data.be(14) & st_data.be(13) & st_data.be(12) when others; +end generate; + +gen_store_data_32B: if stores_32B generate + +axi_store_len <= "0100000"; +st_data_last_xfer <= eq(st_data_xfer_q, "111"); + +with st_data_xfer_q select + axi_store_data <= st_data.data(24 to 31) & st_data.data(16 to 23) & st_data.data(8 to 15) & st_data.data(0 to 7) when "000", + st_data.data(56 to 63) & st_data.data(48 to 55) & st_data.data(40 to 47) & st_data.data(32 to 39) when "001", + st_data.data(87 to 95) & st_data.data(80 to 87) & st_data.data(72 to 79) & st_data.data(64 to 71) when "010", + st_data.data(120 to 127) & st_data.data(112 to 119) & st_data.data(104 to 111) & st_data.data(96 to 103) when "011", + st_data.data(152 to 159) & st_data.data(144 to 151) & st_data.data(136 to 143) & st_data.data(128 to 135) when "100", + st_data.data(184 to 191) & st_data.data(176 to 183) & st_data.data(168 to 175) & st_data.data(160 to 167) when "101", + st_data.data(216 to 223) & st_data.data(208 to 215) & st_data.data(200 to 207) & st_data.data(192 to 199) when "110", + st_data.data(248 to 255) & st_data.data(240 to 247) & st_data.data(232 to 239) & st_data.data(224 to 231) when others; + +with st_data_xfer_q select + axi_store_data_be <= st_data.be( 3) & st_data.be( 2) & st_data.be( 1) & st_data.be( 0) when "000", + st_data.be( 7) & st_data.be( 6) & st_data.be( 5) & st_data.be( 4) when "001", + st_data.be(11) & st_data.be(10) & st_data.be( 9) & st_data.be( 8) when "010", + st_data.be(15) & st_data.be(14) & st_data.be(13) & st_data.be(12) when "011", + st_data.be(19) & st_data.be(18) & st_data.be(17) & st_data.be(16) when "100", + st_data.be(23) & st_data.be(22) & st_data.be(21) & st_data.be(20) when "101", + st_data.be(27) & st_data.be(26) & st_data.be(25) & st_data.be(24) when "110", + st_data.be(31) & st_data.be(30) & st_data.be(29) & st_data.be(28) when others; +end generate; + +axi_store_data_last <= st_data_last_xfer; + +with st_data_xfer_done or store_spec_complete select + stq_data_d <= inc(stq_data_q) when '1', + stq_data_q when others; + +gen_store_data_rst: for i in 0 to st_queue_size-1 generate + stq_data_rst(i) <= st_data_xfer_done and eq(stq_data_q, i); +end generate; + +------------------------------------------------------------------------------------------------------------ +-- Store Resp + +-- could use for throttling +store_rsp_ready_d <= '1'; +axi_store_rsp_ready <= store_rsp_ready_q; + +-- special ops, auto-resp +lwsync_complete <= st_req_data.valid and st_req_data.data and st_req_data.spec and not st_req_data.hwsync; +hwsync_complete <= st_req_data.valid and st_req_data.data and st_req_data.spec and st_req_data.hwsync and not st_req_stall; +store_spec_complete <= lwsync_complete or hwsync_complete; + +-- check resp, pop stq entry, return credit +-- spec complete can occur concurrently with normal responses, so need to send delayed when necessary +store_rsp_complete <= (axi_store_rsp_valid and eq(axi_store_rsp_resp, "00")); +store_complete <= store_rsp_complete or store_spec_complete; + +store_pop_delayed <= or_reduce(store_pop_pending_q); +store_pop_pending_sel <= store_rsp_complete & store_spec_complete & store_pop_delayed; +with store_pop_pending_sel select + store_pop_pending_d <= dec(store_pop_pending_q) when "001", + inc(store_pop_pending_q) when "110", + inc(store_pop_pending_q) when "111", + store_pop_pending_q when others; + +status_d.st_pop <= store_complete or store_pop_delayed; +status_d.st_pop_thrd <= "000"; -- ditc only +status_d.gather <= '0'; -- if store was merged into existing stq entry, use this to return credit + +with store_complete select + stq_head_d <= inc(stq_head_q) when '1', + stq_head_q when others; + +stq_count_sel <= req_in_store & store_complete; +with stq_count_sel select + stq_count_d <= inc(stq_count_q) when "10", + dec(stq_count_q) when "01", + stq_count_q when others; + +gen_stq_valid_rst: for i in 0 to st_queue_size-1 generate + stq_valid_rst(i) <= store_complete and eq(stq_head_q, i); +end generate; + +stq_oflow <= eq(stq_count_q, st_queue_size) and req_in_store; +stq_uflow <= eq(stq_count_q, 0) and store_complete; + +------------------------------------------------------------------------------------------------------------ +-- +-- Specials + +-- larx/stcx +-- larx bypasses L1 cache (i.e. data is not used if it hits in the L1) +-- if larx hits L1, then core invalidates line automatically, therefore, the L2 does NOT need to send back-invalidate for larx +-- larx address is specifed to the 64B cache line. The reservation granule is the 64-Byte cacheline. +-- core will not send any newer instructions following larx from the same thread to L2 until larx is completed +-- L2 tracks one reservation per thread +-- reservation is set before core receives reload data +-- reservation_vld signal (used for fast wake-up from wait state) must be visible at the A2 before lwarx data is returned + +stcx_store_t(0) <= stcx_t(0) or store_t(0); +stcx_store_t(1) <= stcx_t(1) or store_t(1); +stcx_store_t(2) <= stcx_t(2) or store_t(2); +stcx_store_t(3) <= stcx_t(3) or store_t(3); + +req_ra_line <= req_in.ra(64-xu_real_data_add to 59); +resv_ra_hit(0) <= eq(req_ra_line, resv_q(0).ra); +resv_ra_hit(1) <= eq(req_ra_line, resv_q(1).ra); +resv_ra_hit(2) <= eq(req_ra_line, resv_q(2).ra); +resv_ra_hit(3) <= eq(req_ra_line, resv_q(3).ra); + +resv_set(0) <= larx_t(0); +resv_set(1) <= larx_t(1); +resv_set(2) <= larx_t(2); +resv_set(3) <= larx_t(3); + +resv_rst(0) <= resv_ra_hit(0) and (stcx_store_t(0) or stcx_store_t(1) or stcx_store_t(2) or stcx_store_t(3)); +resv_rst(1) <= resv_ra_hit(1) and (stcx_store_t(0) or stcx_store_t(1) or stcx_store_t(2) or stcx_store_t(3)); +resv_rst(2) <= resv_ra_hit(2) and (stcx_store_t(0) or stcx_store_t(1) or stcx_store_t(2) or stcx_store_t(3)); +resv_rst(3) <= resv_ra_hit(3) and (stcx_store_t(0) or stcx_store_t(1) or stcx_store_t(2) or stcx_store_t(3)); + +resv_d(0).valid <= (resv_q(0).valid or resv_set(0)) and not resv_rst(0); +resv_d(1).valid <= (resv_q(1).valid or resv_set(1)) and not resv_rst(1); +resv_d(2).valid <= (resv_q(2).valid or resv_set(2)) and not resv_rst(2); +resv_d(3).valid <= (resv_q(3).valid or resv_set(3)) and not resv_rst(3); + +with resv_set(0) select + resv_d(0).ra <= req_ra_line when '1', + resv_q(0).ra when others; + +with resv_set(1) select + resv_d(1).ra <= req_ra_line when '1', + resv_q(1).ra when others; + +with resv_set(2) select + resv_d(2).ra <= req_ra_line when '1', + resv_q(2).ra when others; + +with resv_set(3) select + resv_d(3).ra <= req_ra_line when '1', + resv_q(3).ra when others; + +status_d.res_valid(0) <= resv_q(0).valid; +status_d.res_valid(1) <= resv_q(1).valid; +status_d.res_valid(2) <= resv_q(2).valid; +status_d.res_valid(3) <= resv_q(3).valid; + +status_d.stcx_complete(0) <= stcx_t(0); +status_d.stcx_complete(1) <= stcx_t(1); +status_d.stcx_complete(2) <= stcx_t(2); +status_d.stcx_complete(3) <= stcx_t(3); + +status_d.stcx_pass(0) <= stcx_t(0) and resv_q(0).valid and resv_ra_hit(0); +status_d.stcx_pass(1) <= stcx_t(1) and resv_q(1).valid and resv_ra_hit(1); +status_d.stcx_pass(2) <= stcx_t(2) and resv_q(2).valid and resv_ra_hit(2); +status_d.stcx_pass(3) <= stcx_t(3) and resv_q(3).valid and resv_ra_hit(3); + +-- sync ack + +status_d.sync_ack(0) <= hwsync_complete and eq(st_req_data.ttype, HWSYNC) and eq(st_req_data.thread, "00"); +status_d.sync_ack(1) <= hwsync_complete and eq(st_req_data.ttype, HWSYNC) and eq(st_req_data.thread, "01"); +status_d.sync_ack(2) <= hwsync_complete and eq(st_req_data.ttype, HWSYNC) and eq(st_req_data.thread, "10"); +status_d.sync_ack(3) <= hwsync_complete and eq(st_req_data.ttype, HWSYNC) and eq(st_req_data.thread, "11"); + +------------------------------------------------------------------------------------------------------------ +-- Load/Store Ordering/Barriers + +req_p1_d <= req_in; + +-- save entry loaded, for setting dependency +ld_p1_entry_d <= req_in_load & ldq_tail_q; +st_p1_entry_d <= req_in_store & stq_tail_q; + +-- ld hit st +gen_dep_addr_cmp_l: for i in 0 to st_queue_size-1 generate + +req_p1_addr_hit_lhs(i) <= ld_p1_entry_q(0) and -- ld req + address_check(req_p1_q, store_queue_q(i)) and -- stq hit + (not stq_valid_rst(i)); -- stq not completing + +req_p1_sync_lhs(i) <= ld_p1_entry_q(0) and -- ld req + store_queue_q(i).valid and -- entry valid + store_queue_q(i).hwsync and -- hwsync + (not stq_valid_rst(i)); -- stq not completing + +req_p1_any_lhs(i) <= req_p1_addr_hit_lhs(i) or req_p1_sync_lhs(i); + +end generate; + +-- rotate to order +lhs_ordered <= rotl(req_p1_any_lhs, stq_head_q); + +-- pick youngest +lhs_ordered_youngest <= right_one(lhs_ordered); + +-- rotate back to entry +lhs_youngest <= rotr(lhs_ordered_youngest, stq_head_q); + +-- encode +lhs_entry <= gate_and(or_reduce(lhs_youngest), '1' & enc(lhs_youngest)); + +-- st hit ld +gen_dep_addr_cmp_s: for i in 0 to ld_queue_size-1 generate + +req_p1_addr_hit_shl(i) <= st_p1_entry_q(0) and -- st req + not req_p1_q.spec and -- not special op + address_check(req_p1_q, load_queue_q(i)) and -- ldq hit + (not ldq_valid_rst(i)); -- ldq not completing + +req_p1_sync_shl(i) <= st_p1_entry_q(0) and -- st req + load_queue_q(i).valid and -- entry valid + req_p1_q.hwsync and -- hwsync + (not ldq_valid_rst(i)); -- ldq not completing + +req_p1_any_shl(i) <= req_p1_addr_hit_shl(i) or req_p1_sync_shl(i); + +end generate; + +-- rotate to order +shl_ordered <= rotl(req_p1_any_shl, ldq_head_q); + +-- pick youngest +shl_ordered_youngest <= right_one(shl_ordered); + +-- rotate back to entry +shl_youngest <= rotr(shl_ordered_youngest, ldq_head_q); + +-- encode +shl_entry <= gate_and(or_reduce(shl_youngest), '1' & enc(shl_youngest)); + +-- addr_hit/barrier ops: +-- 1. block current cycle valid if req_p1 is head this cycle +-- 2. set dep of req_p1 in queue to youngest hit of other queue +-- 3. block head to axi if entry.dep set +-- 4. reset entry.dep(s) when corresponding entry completes + +ld_req_stall <= lhs_entry(0) or ld_dep(0); +st_req_stall <= shl_entry(0) or st_dep(0) or + (st_req_data.hwsync and not eq(stq_send_q, stq_head_q)); -- hwsync waits until it is head + +-- set: reqp1 cycle +gen_ldq_set_dep: for i in 0 to ld_queue_size-1 generate +load_queue_set_dep(i) <= ld_p1_entry_q(0) and eq(ld_p1_entry_q(1 to clog2(ld_queue_size)), i) and lhs_entry(0); +end generate; + +gen_stq_set_dep: for i in 0 to st_queue_size-1 generate +store_queue_set_dep(i) <= st_p1_entry_q(0) and eq(st_p1_entry_q(1 to clog2(st_queue_size)), i) and shl_entry(0); +end generate; + +-- rst: comp cycle +gen_ldq_rst_dep: for i in 0 to ld_queue_size-1 generate +load_queue_rst_dep(i) <= store_complete and load_dep_q(i)(0) and eq(load_dep_q(i)(1 to clog2(st_queue_size)), stq_head_q); +end generate; + +gen_stq_rst_dep: for i in 0 to st_queue_size-1 generate +store_queue_rst_dep(i) <= load_complete and store_dep_q(i)(0) and eq(store_dep_q(i)(1 to clog2(ld_queue_size)), ldq_head_q); +end generate; + +-------------------------------------------------------------------------------------- +-- AXI Interface + +-- read req + +axi_load_ready <= m00_axi_arready; +m00_axi_arvalid <= axi_load_valid; +m00_axi_arid <= axi_load_id; +m00_axi_araddr <= axi_load_ra; + +with axi_load_len select + m00_axi_arlen <= x"00" when "0000001", -- 1B + x"00" when "0000010", -- 2B + x"00" when "0000100", -- 4B + x"01" when "0001000", -- 8B + x"03" when "0010000", -- 16B + x"07" when "0100000", -- 32B + x"0F" when "1000000", -- 64B + x"00" when others; + +m00_axi_arsize <= "010"; +m00_axi_arburst <= "01"; + +-- axi_read_mod stuff +m00_axi_arlock <= '0'; +m00_axi_arcache <= "0011"; +m00_axi_arprot <= "000"; +m00_axi_arqos <= x"0"; +m00_axi_aruser <= (others => '1'); + +-- read resp + +m00_axi_rready <= axi_load_data_ready; +axi_load_data_valid <= m00_axi_rvalid; +axi_load_data_id <= m00_axi_rid; +axi_load_data <= m00_axi_rdata; +axi_load_data_resp <= m00_axi_rresp; +axi_load_data_last <= m00_axi_rlast; + +-- store req + +axi_store_ready <= m00_axi_awready; +m00_axi_awvalid <= axi_store_valid; +m00_axi_awid <= axi_store_id; +m00_axi_awaddr <= axi_store_ra; + +with axi_store_len select + m00_axi_awlen <= x"03" when "0010000", -- 16B + x"07" when "0100000", -- 32B + x"00" when others; + +m00_axi_awsize <= "010"; +m00_axi_awburst <= "01"; + +-- mod stuff +m00_axi_awlock <= '0'; +m00_axi_awcache <= "0010"; +m00_axi_awprot <= "000"; +m00_axi_awqos <= x"0"; +m00_axi_awuser <= (others => '1'); + +-- store data + +axi_store_data_ready <= m00_axi_wready; +m00_axi_wvalid <= axi_store_data_valid; +m00_axi_wdata <= axi_store_data; +m00_axi_wstrb <= axi_store_data_be; +m00_axi_wlast <= axi_store_data_last; +m00_axi_wuser <= (others => '0'); + +-- store resp + +m00_axi_bready <= axi_store_rsp_ready; +axi_store_rsp_valid <= m00_axi_bvalid; +axi_store_rsp_id <= m00_axi_bid; +axi_store_rsp_resp <= m00_axi_bresp; + +------------------------------------------------------------------------------------------------------------ +-- Misc + +err_d(0) <= ldq_uflow; +err_d(1) <= ldq_oflow; +err_d(2) <= stq_uflow; +err_d(3) <= stq_oflow; + +err <= err_q; + +------------------------------------------------------------------------------------------------------------ +-- move along. + +--vtable ReqDcd +req_in_load <= + (req_in.valid and not req_in.ttype(0) and not req_in.ttype(1) and not req_in.ttype(2) and not req_in.ttype(3) and not req_in.ttype(4) and not req_in.ttype(5)) or + (req_in.valid and not req_in.ttype(0) and not req_in.ttype(1) and not req_in.ttype(2) and not req_in.ttype(3) and not req_in.ttype(4) and req_in.ttype(5)) or + (req_in.valid and not req_in.ttype(0) and not req_in.ttype(1) and req_in.ttype(2) and not req_in.ttype(3) and not req_in.ttype(4) and not req_in.ttype(5)) or + (req_in.valid and not req_in.ttype(0) and not req_in.ttype(1) and req_in.ttype(2) and not req_in.ttype(3) and not req_in.ttype(4) and req_in.ttype(5) and not req_in.thread(0) and not req_in.thread(1)) or + (req_in.valid and not req_in.ttype(0) and not req_in.ttype(1) and req_in.ttype(2) and not req_in.ttype(3) and not req_in.ttype(4) and req_in.ttype(5) and not req_in.thread(0) and req_in.thread(1)) or + (req_in.valid and not req_in.ttype(0) and not req_in.ttype(1) and req_in.ttype(2) and not req_in.ttype(3) and not req_in.ttype(4) and req_in.ttype(5) and req_in.thread(0) and not req_in.thread(1)) or + (req_in.valid and not req_in.ttype(0) and not req_in.ttype(1) and req_in.ttype(2) and not req_in.ttype(3) and not req_in.ttype(4) and req_in.ttype(5) and req_in.thread(0) and req_in.thread(1)); +req_in_store <= + (req_in.valid and req_in.ttype(0) and not req_in.ttype(1) and not req_in.ttype(2) and not req_in.ttype(3) and not req_in.ttype(4) and not req_in.ttype(5) and not req_in.thread(0) and not req_in.thread(1)) or + (req_in.valid and req_in.ttype(0) and not req_in.ttype(1) and not req_in.ttype(2) and not req_in.ttype(3) and not req_in.ttype(4) and not req_in.ttype(5) and not req_in.thread(0) and req_in.thread(1)) or + (req_in.valid and req_in.ttype(0) and not req_in.ttype(1) and not req_in.ttype(2) and not req_in.ttype(3) and not req_in.ttype(4) and not req_in.ttype(5) and req_in.thread(0) and not req_in.thread(1)) or + (req_in.valid and req_in.ttype(0) and not req_in.ttype(1) and not req_in.ttype(2) and not req_in.ttype(3) and not req_in.ttype(4) and not req_in.ttype(5) and req_in.thread(0) and req_in.thread(1)) or + (req_in.valid and req_in.ttype(0) and not req_in.ttype(1) and req_in.ttype(2) and not req_in.ttype(3) and not req_in.ttype(4) and req_in.ttype(5) and not req_in.thread(0) and not req_in.thread(1)) or + (req_in.valid and req_in.ttype(0) and not req_in.ttype(1) and req_in.ttype(2) and not req_in.ttype(3) and not req_in.ttype(4) and req_in.ttype(5) and not req_in.thread(0) and req_in.thread(1)) or + (req_in.valid and req_in.ttype(0) and not req_in.ttype(1) and req_in.ttype(2) and not req_in.ttype(3) and not req_in.ttype(4) and req_in.ttype(5) and req_in.thread(0) and not req_in.thread(1)) or + (req_in.valid and req_in.ttype(0) and not req_in.ttype(1) and req_in.ttype(2) and not req_in.ttype(3) and not req_in.ttype(4) and req_in.ttype(5) and req_in.thread(0) and req_in.thread(1)) or + (req_in.valid and req_in.ttype(0) and not req_in.ttype(1) and req_in.ttype(2) and not req_in.ttype(3) and req_in.ttype(4) and not req_in.ttype(5)) or + (req_in.valid and req_in.ttype(0) and not req_in.ttype(1) and req_in.ttype(2) and not req_in.ttype(3) and req_in.ttype(4) and req_in.ttype(5)) or + (req_in.valid and req_in.ttype(0) and req_in.ttype(1) and req_in.ttype(2) and not req_in.ttype(3) and req_in.ttype(4) and not req_in.ttype(5)) or + (req_in.valid and req_in.ttype(0) and req_in.ttype(1) and req_in.ttype(2) and req_in.ttype(3) and req_in.ttype(4) and req_in.ttype(5)); +req_in_spec <= + (req_in.valid and req_in.ttype(0) and not req_in.ttype(1) and req_in.ttype(2) and not req_in.ttype(3) and req_in.ttype(4) and not req_in.ttype(5)) or + (req_in.valid and req_in.ttype(0) and not req_in.ttype(1) and req_in.ttype(2) and not req_in.ttype(3) and req_in.ttype(4) and req_in.ttype(5)) or + (req_in.valid and req_in.ttype(0) and req_in.ttype(1) and req_in.ttype(2) and not req_in.ttype(3) and req_in.ttype(4) and not req_in.ttype(5)) or + (req_in.valid and req_in.ttype(0) and req_in.ttype(1) and req_in.ttype(2) and req_in.ttype(3) and req_in.ttype(4) and req_in.ttype(5)); +larx_t(0) <= + (req_in.valid and not req_in.ttype(0) and not req_in.ttype(1) and req_in.ttype(2) and not req_in.ttype(3) and not req_in.ttype(4) and req_in.ttype(5) and not req_in.thread(0) and not req_in.thread(1)); +larx_t(1) <= + (req_in.valid and not req_in.ttype(0) and not req_in.ttype(1) and req_in.ttype(2) and not req_in.ttype(3) and not req_in.ttype(4) and req_in.ttype(5) and not req_in.thread(0) and req_in.thread(1)); +larx_t(2) <= + (req_in.valid and not req_in.ttype(0) and not req_in.ttype(1) and req_in.ttype(2) and not req_in.ttype(3) and not req_in.ttype(4) and req_in.ttype(5) and req_in.thread(0) and not req_in.thread(1)); +larx_t(3) <= + (req_in.valid and not req_in.ttype(0) and not req_in.ttype(1) and req_in.ttype(2) and not req_in.ttype(3) and not req_in.ttype(4) and req_in.ttype(5) and req_in.thread(0) and req_in.thread(1)); +stcx_t(0) <= + (req_in.valid and req_in.ttype(0) and not req_in.ttype(1) and req_in.ttype(2) and not req_in.ttype(3) and not req_in.ttype(4) and req_in.ttype(5) and not req_in.thread(0) and not req_in.thread(1)); +stcx_t(1) <= + (req_in.valid and req_in.ttype(0) and not req_in.ttype(1) and req_in.ttype(2) and not req_in.ttype(3) and not req_in.ttype(4) and req_in.ttype(5) and not req_in.thread(0) and req_in.thread(1)); +stcx_t(2) <= + (req_in.valid and req_in.ttype(0) and not req_in.ttype(1) and req_in.ttype(2) and not req_in.ttype(3) and not req_in.ttype(4) and req_in.ttype(5) and req_in.thread(0) and not req_in.thread(1)); +stcx_t(3) <= + (req_in.valid and req_in.ttype(0) and not req_in.ttype(1) and req_in.ttype(2) and not req_in.ttype(3) and not req_in.ttype(4) and req_in.ttype(5) and req_in.thread(0) and req_in.thread(1)); +store_t(0) <= + (req_in.valid and req_in.ttype(0) and not req_in.ttype(1) and not req_in.ttype(2) and not req_in.ttype(3) and not req_in.ttype(4) and not req_in.ttype(5) and not req_in.thread(0) and not req_in.thread(1)); +store_t(1) <= + (req_in.valid and req_in.ttype(0) and not req_in.ttype(1) and not req_in.ttype(2) and not req_in.ttype(3) and not req_in.ttype(4) and not req_in.ttype(5) and not req_in.thread(0) and req_in.thread(1)); +store_t(2) <= + (req_in.valid and req_in.ttype(0) and not req_in.ttype(1) and not req_in.ttype(2) and not req_in.ttype(3) and not req_in.ttype(4) and not req_in.ttype(5) and req_in.thread(0) and not req_in.thread(1)); +store_t(3) <= + (req_in.valid and req_in.ttype(0) and not req_in.ttype(1) and not req_in.ttype(2) and not req_in.ttype(3) and not req_in.ttype(4) and not req_in.ttype(5) and req_in.thread(0) and req_in.thread(1)); +--vtable ReqDcd + +--vtable RldSeq +rld_seq_d(0) <= + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4) and not rld_ready) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4) and rld_ready and not rld_crit_qw(0) and not rld_crit_qw(1) and not rld_single) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4) and rld_ready and not rld_crit_qw(0) and rld_crit_qw(1) and not rld_single) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4) and rld_ready and rld_crit_qw(0) and not rld_crit_qw(1) and not rld_single) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4) and rld_ready and rld_crit_qw(0) and rld_crit_qw(1) and not rld_single) or + (not rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and not rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and not rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and not rld_seq_q(2) and not rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and not rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and not rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)); +rld_seq_d(1) <= + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4) and not rld_ready) or + (not rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and not rld_seq_q(2) and not rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and not rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and not rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)); +rld_seq_d(2) <= + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4) and not rld_ready) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4) and rld_ready and rld_crit_qw(0) and not rld_crit_qw(1) and not rld_single) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4) and rld_ready and rld_crit_qw(0) and rld_crit_qw(1) and not rld_single) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4) and rld_ready and rld_crit_qw(0) and rld_crit_qw(1) and rld_single) or + (not rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)) or + (not rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)) or + (not rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4)) or + (not rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and not rld_seq_q(3) and not rld_seq_q(4)) or + (not rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)) or + (not rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and not rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and not rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4)) or + (not rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and not rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)); +rld_seq_d(3) <= + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4) and not rld_ready) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4) and rld_ready and not rld_crit_qw(0) and rld_crit_qw(1) and not rld_single) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4) and rld_ready and rld_crit_qw(0) and rld_crit_qw(1) and not rld_single) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4) and rld_ready and not rld_crit_qw(0) and rld_crit_qw(1) and rld_single) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4) and rld_ready and rld_crit_qw(0) and not rld_crit_qw(1) and rld_single) or + (not rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)) or + (not rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)) or + (not rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4)) or + (not rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and not rld_seq_q(3) and not rld_seq_q(4)) or + (not rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)) or + (not rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and not rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)); +rld_seq_d(4) <= + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4) and not rld_ready) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4) and rld_ready and not rld_crit_qw(0) and not rld_crit_qw(1) and rld_single) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4) and rld_ready and rld_crit_qw(0) and not rld_crit_qw(1) and rld_single) or + (not rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)) or + (not rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and not rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and not rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and not rld_seq_q(2) and not rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and not rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4)) or + (not rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)); +reload_d.coming <= + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4) and rld_ready and not rld_crit_qw(0) and not rld_crit_qw(1) and not rld_single) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4) and rld_ready and not rld_crit_qw(0) and rld_crit_qw(1) and not rld_single) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4) and rld_ready and rld_crit_qw(0) and not rld_crit_qw(1) and not rld_single) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4) and rld_ready and rld_crit_qw(0) and rld_crit_qw(1) and not rld_single) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4) and rld_ready and not rld_crit_qw(0) and not rld_crit_qw(1) and rld_single) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4) and rld_ready and not rld_crit_qw(0) and rld_crit_qw(1) and rld_single) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4) and rld_ready and rld_crit_qw(0) and not rld_crit_qw(1) and rld_single) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4) and rld_ready and rld_crit_qw(0) and rld_crit_qw(1) and rld_single) or + (rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4)); +reload_d.valid <= + (not rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)) or + (not rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)) or + (not rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4)) or + (not rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and not rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and not rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and not rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and not rld_seq_q(2) and not rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and not rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4)); +reload_d.qw(58) <= + (not rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4)) or + (not rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and not rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and not rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4)); +reload_d.qw(59) <= + (not rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)) or + (not rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and not rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and not rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4)); +reload_d.crit <= + (not rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)) or + (not rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)) or + (not rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4)) or + (not rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and not rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and not rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and not rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)); +start_rld_data <= + (not rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and not rld_seq_q(2) and not rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and not rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)); +rld_seq_err <= + (not rld_seq_q(0) and not rld_seq_q(1) and not rld_seq_q(2) and not rld_seq_q(3) and not rld_seq_q(4)) or + (not rld_seq_q(0) and not rld_seq_q(1) and rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and not rld_seq_q(3) and not rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)) or + (rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4)); +--vtable RldSeq + +--vtable RldDataSeq +rld_dseq_d(0) <= + (rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and rld_dseq_q(3) and not start_rld_data) or + (rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and rld_dseq_q(3) and start_rld_data and rld_single) or + (not rld_dseq_q(0) and not rld_dseq_q(1) and not rld_dseq_q(2) and rld_dseq_q(3)) or + (not rld_dseq_q(0) and not rld_dseq_q(1) and rld_dseq_q(2) and not rld_dseq_q(3)) or + (not rld_dseq_q(0) and not rld_dseq_q(1) and rld_dseq_q(2) and rld_dseq_q(3)) or + (not rld_dseq_q(0) and rld_dseq_q(1) and not rld_dseq_q(2) and not rld_dseq_q(3)) or + (rld_dseq_q(0) and not rld_dseq_q(1) and not rld_dseq_q(2) and rld_dseq_q(3)) or + (rld_dseq_q(0) and not rld_dseq_q(1) and rld_dseq_q(2) and not rld_dseq_q(3)) or + (rld_dseq_q(0) and not rld_dseq_q(1) and rld_dseq_q(2) and rld_dseq_q(3)) or + (rld_dseq_q(0) and rld_dseq_q(1) and not rld_dseq_q(2) and not rld_dseq_q(3)) or + (rld_dseq_q(0) and not rld_dseq_q(1) and not rld_dseq_q(2) and not rld_dseq_q(3)) or + (rld_dseq_q(0) and rld_dseq_q(1) and not rld_dseq_q(2) and rld_dseq_q(3)) or + (rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and not rld_dseq_q(3)); +rld_dseq_d(1) <= + (rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and rld_dseq_q(3) and not start_rld_data) or + (rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and rld_dseq_q(3) and start_rld_data and rld_crit_qw(0) and rld_crit_qw(1) and not rld_single) or + (rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and rld_dseq_q(3) and start_rld_data and rld_single) or + (rld_dseq_q(0) and not rld_dseq_q(1) and rld_dseq_q(2) and not rld_dseq_q(3)) or + (rld_dseq_q(0) and not rld_dseq_q(1) and rld_dseq_q(2) and rld_dseq_q(3)) or + (rld_dseq_q(0) and rld_dseq_q(1) and not rld_dseq_q(2) and not rld_dseq_q(3)) or + (not rld_dseq_q(0) and rld_dseq_q(1) and not rld_dseq_q(2) and rld_dseq_q(3)) or + (not rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and not rld_dseq_q(3)) or + (not rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and rld_dseq_q(3)) or + (rld_dseq_q(0) and rld_dseq_q(1) and not rld_dseq_q(2) and rld_dseq_q(3)) or + (rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and not rld_dseq_q(3)); +rld_dseq_d(2) <= + (rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and rld_dseq_q(3) and not start_rld_data) or + (rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and rld_dseq_q(3) and start_rld_data and not rld_crit_qw(0) and rld_crit_qw(1) and not rld_single) or + (rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and rld_dseq_q(3) and start_rld_data and rld_crit_qw(0) and not rld_crit_qw(1) and not rld_single) or + (rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and rld_dseq_q(3) and start_rld_data and rld_single) or + (not rld_dseq_q(0) and not rld_dseq_q(1) and not rld_dseq_q(2) and rld_dseq_q(3)) or + (not rld_dseq_q(0) and not rld_dseq_q(1) and rld_dseq_q(2) and not rld_dseq_q(3)) or + (rld_dseq_q(0) and not rld_dseq_q(1) and not rld_dseq_q(2) and rld_dseq_q(3)) or + (rld_dseq_q(0) and not rld_dseq_q(1) and rld_dseq_q(2) and not rld_dseq_q(3)) or + (rld_dseq_q(0) and rld_dseq_q(1) and not rld_dseq_q(2) and not rld_dseq_q(3)) or + (not rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and not rld_dseq_q(3)) or + (not rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and rld_dseq_q(3)) or + (rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and not rld_dseq_q(3)); +rld_dseq_d(3) <= + (rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and rld_dseq_q(3) and not start_rld_data) or + (rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and rld_dseq_q(3) and start_rld_data and not rld_crit_qw(0) and not rld_crit_qw(1) and not rld_single) or + (rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and rld_dseq_q(3) and start_rld_data and rld_crit_qw(0) and not rld_crit_qw(1) and not rld_single) or + (rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and rld_dseq_q(3) and start_rld_data and rld_single) or + (not rld_dseq_q(0) and not rld_dseq_q(1) and not rld_dseq_q(2) and rld_dseq_q(3)) or + (not rld_dseq_q(0) and not rld_dseq_q(1) and rld_dseq_q(2) and not rld_dseq_q(3)) or + (not rld_dseq_q(0) and not rld_dseq_q(1) and rld_dseq_q(2) and rld_dseq_q(3)) or + (not rld_dseq_q(0) and rld_dseq_q(1) and not rld_dseq_q(2) and not rld_dseq_q(3)) or + (rld_dseq_q(0) and not rld_dseq_q(1) and rld_dseq_q(2) and not rld_dseq_q(3)) or + (rld_dseq_q(0) and rld_dseq_q(1) and not rld_dseq_q(2) and not rld_dseq_q(3)) or + (not rld_dseq_q(0) and rld_dseq_q(1) and not rld_dseq_q(2) and rld_dseq_q(3)) or + (not rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and rld_dseq_q(3)) or + (rld_dseq_q(0) and rld_dseq_q(1) and not rld_dseq_q(2) and rld_dseq_q(3)); +rld_data_qw(0) <= + (rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and rld_dseq_q(3) and start_rld_data and rld_crit_qw(0) and not rld_crit_qw(1) and not rld_single) or + (rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and rld_dseq_q(3) and start_rld_data and rld_crit_qw(0) and rld_crit_qw(1) and not rld_single) or + (not rld_dseq_q(0) and not rld_dseq_q(1) and rld_dseq_q(2) and rld_dseq_q(3)) or + (not rld_dseq_q(0) and rld_dseq_q(1) and not rld_dseq_q(2) and not rld_dseq_q(3)) or + (rld_dseq_q(0) and not rld_dseq_q(1) and rld_dseq_q(2) and rld_dseq_q(3)) or + (rld_dseq_q(0) and rld_dseq_q(1) and not rld_dseq_q(2) and not rld_dseq_q(3)); +rld_data_qw(1) <= + (rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and rld_dseq_q(3) and start_rld_data and not rld_crit_qw(0) and rld_crit_qw(1) and not rld_single) or + (rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and rld_dseq_q(3) and start_rld_data and rld_crit_qw(0) and rld_crit_qw(1) and not rld_single) or + (not rld_dseq_q(0) and not rld_dseq_q(1) and not rld_dseq_q(2) and rld_dseq_q(3)) or + (not rld_dseq_q(0) and not rld_dseq_q(1) and rld_dseq_q(2) and rld_dseq_q(3)) or + (rld_dseq_q(0) and not rld_dseq_q(1) and rld_dseq_q(2) and not rld_dseq_q(3)) or + (rld_dseq_q(0) and rld_dseq_q(1) and not rld_dseq_q(2) and not rld_dseq_q(3)); +rld_complete <= + (rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and rld_dseq_q(3) and start_rld_data and rld_single) or + (rld_dseq_q(0) and not rld_dseq_q(1) and rld_dseq_q(2) and not rld_dseq_q(3)) or + (rld_dseq_q(0) and rld_dseq_q(1) and not rld_dseq_q(2) and not rld_dseq_q(3)); +rld_dseq_err <= + (not rld_dseq_q(0) and not rld_dseq_q(1) and not rld_dseq_q(2) and not rld_dseq_q(3)) or + (not rld_dseq_q(0) and rld_dseq_q(1) and not rld_dseq_q(2) and rld_dseq_q(3)) or + (not rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and not rld_dseq_q(3)) or + (not rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and rld_dseq_q(3)) or + (rld_dseq_q(0) and not rld_dseq_q(1) and not rld_dseq_q(2) and not rld_dseq_q(3)) or + (rld_dseq_q(0) and rld_dseq_q(1) and not rld_dseq_q(2) and rld_dseq_q(3)) or + (rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and not rld_dseq_q(3)); +--vtable RldDataSeq + + +end a2l2_axi; diff --git a/rel/src/vhdl/work/a2x_axi.vhdl b/rel/src/vhdl/work/a2x_axi.vhdl new file mode 100644 index 0000000..022e42f --- /dev/null +++ b/rel/src/vhdl/work/a2x_axi.vhdl @@ -0,0 +1,664 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- a2i core plus a2l2_axi +-- use this for the core-level wrapper + +library ieee; use ieee.std_logic_1164.all; +library ibm; +library work; use work.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; +library support; + use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity a2x_axi is + generic ( + C_M00_AXI_ID_WIDTH : integer := 4; + C_M00_AXI_ADDR_WIDTH : integer := 32; + C_M00_AXI_DATA_WIDTH : integer := 32; + C_M00_AXI_AWUSER_WIDTH : integer := 4; + C_M00_AXI_ARUSER_WIDTH : integer := 4; + C_M00_AXI_WUSER_WIDTH : integer := 4; + C_M00_AXI_RUSER_WIDTH : integer := 4; + C_M00_AXI_BUSER_WIDTH : integer := 4 + ); + port ( + + clk : in std_logic; + clk2x : in std_logic; + reset_n : in std_logic; -- active low + thold : in std_logic; -- normally 0 + + core_id : in std_logic_vector(0 to 7); -- for multicore + thread_stop : in std_logic_vector(0 to 3); -- control + thread_running : out std_logic_vector(0 to 3); -- status + + ext_mchk : in std_logic_vector(0 to 3); -- machine check + ext_checkstop : in std_logic; -- checkstop + debug_stop : in std_logic; -- thread stop + mchk : out std_logic_vector(0 to 3); -- machine check + recov_err : out std_logic_vector(0 to 2); -- recoverable + checkstop : out std_logic_vector(0 to 2); -- checkstop + a2l2_axi_err : out std_logic_vector(0 to 3); -- + + crit_interrupt : in std_logic_vector(0 to 3); -- critical + ext_interrupt : in std_logic_vector(0 to 3); -- external + perf_interrupt : in std_logic_vector(0 to 3); -- performance + + tb_update_enable : in std_logic; -- normally 1 + tb_update_pulse : in std_logic; -- tb clock if xucr0[tcs]=1 (must be <1/2 proc clk; tb pulse is 2x this clock) + + scom_sat_id : in std_logic_vector(0 to 3); -- could split into acq and axi + scom_dch_in : in std_logic; + scom_cch_in : in std_logic; + scom_dch_out : out std_logic; + scom_cch_out : out std_logic; + + flh2l2_gate : in std_logic; + hang_pulse : in std_logic_vector(0 to 3); + + m00_axi_awid : out std_logic_vector(C_M00_AXI_ID_WIDTH-1 downto 0); + m00_axi_awaddr : out std_logic_vector(C_M00_AXI_ADDR_WIDTH-1 downto 0); + m00_axi_awlen : out std_logic_vector(7 downto 0); + m00_axi_awsize : out std_logic_vector(2 downto 0); + m00_axi_awburst : out std_logic_vector(1 downto 0); + m00_axi_awlock : out std_logic; + m00_axi_awcache : out std_logic_vector(3 downto 0); + m00_axi_awprot : out std_logic_vector(2 downto 0); + m00_axi_awqos : out std_logic_vector(3 downto 0); + m00_axi_awuser : out std_logic_vector(C_M00_AXI_AWUSER_WIDTH-1 downto 0); + m00_axi_awvalid : out std_logic; + m00_axi_awready : in std_logic; + m00_axi_wdata : out std_logic_vector(C_M00_AXI_DATA_WIDTH-1 downto 0); + m00_axi_wstrb : out std_logic_vector(C_M00_AXI_DATA_WIDTH/8-1 downto 0); + m00_axi_wlast : out std_logic; + m00_axi_wuser : out std_logic_vector(C_M00_AXI_WUSER_WIDTH-1 downto 0); + m00_axi_wvalid : out std_logic; + m00_axi_wready : in std_logic; + m00_axi_bid : in std_logic_vector(C_M00_AXI_ID_WIDTH-1 downto 0); + m00_axi_bresp : in std_logic_vector(1 downto 0); + m00_axi_buser : in std_logic_vector(C_M00_AXI_BUSER_WIDTH-1 downto 0); + m00_axi_bvalid : in std_logic; + m00_axi_bready : out std_logic; + m00_axi_arid : out std_logic_vector(C_M00_AXI_ID_WIDTH-1 downto 0); + m00_axi_araddr : out std_logic_vector(C_M00_AXI_ADDR_WIDTH-1 downto 0); + m00_axi_arlen : out std_logic_vector(7 downto 0); + m00_axi_arsize : out std_logic_vector(2 downto 0); + m00_axi_arburst : out std_logic_vector(1 downto 0); + m00_axi_arlock : out std_logic; + m00_axi_arcache : out std_logic_vector(3 downto 0); + m00_axi_arprot : out std_logic_vector(2 downto 0); + m00_axi_arqos : out std_logic_vector(3 downto 0); + m00_axi_aruser : out std_logic_vector(C_M00_AXI_ARUSER_WIDTH-1 downto 0); + m00_axi_arvalid : out std_logic; + m00_axi_arready : in std_logic; + m00_axi_rid : in std_logic_vector(C_M00_AXI_ID_WIDTH-1 downto 0); + m00_axi_rdata : in std_logic_vector(C_M00_AXI_DATA_WIDTH-1 downto 0); + m00_axi_rresp : in std_logic_vector(1 downto 0); + m00_axi_rlast : in std_logic; + m00_axi_ruser : in std_logic_vector(C_M00_AXI_RUSER_WIDTH-1 downto 0); + m00_axi_rvalid : in std_logic; + m00_axi_rready : out std_logic + + ); +end a2x_axi; + +architecture a2x_axi of a2x_axi is + + -- Common + constant expand_type : integer := 1; + constant threads : integer := 4; + -- XU + constant xu_real_data_add : integer := 42; + constant st_data_32b_mode : integer := 1; + constant ac_st_data_32b_mode : integer := 1; + -- MM + constant error_width : integer := 3; + constant expand_tlb_type : integer := 2; + constant extclass_width : integer := 2; + constant inv_seq_width : integer := 4; + constant lpid_width : integer := 8; + constant pid_width : integer := 14; + constant ra_entry_width : integer := 12; + constant real_addr_width : integer := 42; + +signal a2_nclk : clk_logic; + +signal an_ac_sg_7 : std_logic; +signal an_ac_back_inv : std_logic; +signal an_ac_back_inv_addr : std_logic_vector(22 to 63); +signal an_ac_back_inv_lbit : std_logic; +signal an_ac_back_inv_gs : std_logic; +signal an_ac_back_inv_ind : std_logic; +signal an_ac_back_inv_local : std_logic; +signal an_ac_back_inv_lpar_id : std_logic_vector(0 to 7); +signal an_ac_back_inv_target : std_logic_vector(0 to 4); +signal an_ac_dcr_act : std_logic; +signal an_ac_dcr_val : std_logic; +signal an_ac_dcr_read : std_logic; +signal an_ac_dcr_etid : std_logic_vector(0 to 1); +signal an_ac_dcr_data : std_logic_vector(0 to 63); +signal an_ac_dcr_done : std_logic; +signal an_ac_flh2l2_gate : std_logic; +signal an_ac_reld_core_tag : std_logic_vector(0 to 4); +signal an_ac_reld_data : std_logic_vector(0 to 127); +signal an_ac_reld_data_vld : std_logic; +signal an_ac_reld_ecc_err : std_logic; +signal an_ac_reld_ecc_err_ue : std_logic; +signal an_ac_reld_qw : std_logic_vector(57 to 59); +signal an_ac_reld_data_coming : std_logic; +signal an_ac_reld_ditc : std_logic; +signal an_ac_reld_crit_qw : std_logic; +signal an_ac_reld_l1_dump : std_logic; + +signal an_ac_req_ld_pop : std_logic; +signal an_ac_req_st_gather : std_logic; +signal an_ac_req_st_pop : std_logic; +signal an_ac_req_st_pop_thrd : std_logic_vector(0 to 2); + +signal an_ac_stcx_complete : std_logic_vector(0 to 3); +signal an_ac_stcx_pass : std_logic_vector(0 to 3); +signal an_ac_sync_ack : std_logic_vector(0 to 3); +signal an_ac_user_defined : std_logic_vector(0 to 3); +signal an_ac_reservation_vld : std_logic_vector(0 to 3); + +signal an_ac_icbi_ack : std_ulogic; +signal an_ac_icbi_ack_thread : std_ulogic_vector(0 to 1); +signal an_ac_sleep_en : std_ulogic_vector(0 to 3); +signal ac_an_back_inv_reject : std_ulogic; +signal ac_an_box_empty : std_ulogic_vector(0 to 3); +signal ac_an_lpar_id : std_ulogic_vector(0 to 7); +signal ac_an_power_managed : std_ulogic; +signal ac_an_req : std_ulogic; +signal ac_an_req_endian : std_ulogic; +signal ac_an_req_ld_core_tag : std_ulogic_vector(0 to 4); +signal ac_an_req_ld_xfr_len : std_ulogic_vector(0 to 2); +signal ac_an_req_pwr_token : std_ulogic; +signal ac_an_req_ra : std_ulogic_vector(22 to 63); +signal ac_an_req_spare_ctrl_a0 : std_ulogic_vector(0 to 3); +signal ac_an_req_thread : std_ulogic_vector(0 to 2); +signal ac_an_req_ttype : std_ulogic_vector(0 to 5); +signal ac_an_req_user_defined : std_ulogic_vector(0 to 3); +signal ac_an_req_wimg_g : std_ulogic; +signal ac_an_req_wimg_i : std_ulogic; +signal ac_an_req_wimg_m : std_ulogic; +signal ac_an_req_wimg_w : std_ulogic; +signal ac_an_reld_ditc_pop : std_ulogic_vector(0 to 3); +signal ac_an_rvwinkle_mode : std_ulogic; +signal ac_an_st_byte_enbl : std_ulogic_vector(0 to 31); +signal ac_an_st_data : std_ulogic_vector(0 to 255); +signal ac_an_st_data_pwr_token : std_ulogic; +signal ac_an_fu_bypass_events : std_ulogic_vector(0 to 7); +signal ac_an_iu_bypass_events : std_ulogic_vector(0 to 7); +signal ac_an_mm_bypass_events : std_ulogic_vector(0 to 7); +signal an_ac_debug_stop : std_ulogic; +signal ac_an_psro_ringsig : std_ulogic; +signal an_ac_psro_enable_dc : std_ulogic_vector(0 to 2); +signal an_ac_req_spare_ctrl_a1 : std_ulogic_vector(0 to 3); +signal alt_disp : std_ulogic; +signal d_mode : std_ulogic; +signal delay_lclkr : std_ulogic; +signal mpw1_b : std_ulogic; +signal mpw2_b : std_ulogic; +signal scdis_b : std_ulogic; + +signal an_ac_abist_mode_dc : std_ulogic; +signal an_ac_abist_start_test : std_ulogic; +signal an_ac_abst_scan_in : std_ulogic_vector(0 to 9); +signal an_ac_atpg_en_dc : std_ulogic; +signal an_ac_bcfg_scan_in : std_ulogic_vector(0 to 4); +signal an_ac_lbist_ary_wrt_thru_dc : std_ulogic; +signal an_ac_ccenable_dc : std_ulogic; +signal an_ac_ccflush_dc : std_ulogic; +signal an_ac_reset_1_complete : std_ulogic; +signal an_ac_reset_2_complete : std_ulogic; +signal an_ac_reset_3_complete : std_ulogic; +signal an_ac_reset_wd_complete : std_ulogic; +signal an_ac_dcfg_scan_in : std_ulogic_vector(0 to 2); +signal an_ac_fce_7 : std_ulogic; +signal an_ac_func_scan_in : std_ulogic_vector(0 to 63); +signal an_ac_gptr_scan_in : std_ulogic; +signal an_ac_hang_pulse : std_ulogic_vector(0 to 3); +signal an_ac_lbist_en_dc : std_ulogic; +signal an_ac_lbist_ac_mode_dc : std_ulogic; +signal an_ac_lbist_ip_dc : std_ulogic; +signal an_ac_malf_alert : std_ulogic; +signal an_ac_gsd_test_enable_dc : std_ulogic; +signal an_ac_gsd_test_acmode_dc : std_ulogic; +signal an_ac_repr_scan_in : std_ulogic; +signal an_ac_scan_diag_dc : std_ulogic; +signal an_ac_scan_dis_dc_b : std_ulogic; +signal an_ac_scan_type_dc : std_ulogic_vector(0 to 8); +signal an_ac_scom_sat_id : std_ulogic_vector(0 to 3); +signal an_ac_checkstop : std_ulogic; +signal an_ac_machine_check : std_ulogic_vector(0 to 3); +signal an_ac_tb_update_enable : std_ulogic; +signal an_ac_tb_update_pulse : std_ulogic; +signal an_ac_time_scan_in : std_ulogic; +signal an_ac_regf_scan_in : std_ulogic_vector(0 to 11); + +signal ac_an_debug_bus : std_ulogic_vector(0 to 87); +signal ac_an_event_bus : std_ulogic_vector(0 to 7); +signal ac_an_trace_triggers : std_ulogic_vector(0 to 11); +signal ac_an_abist_done_dc : std_ulogic; +signal ac_an_abst_scan_out : std_ulogic_vector(0 to 9); +signal ac_an_bcfg_scan_out : std_ulogic_vector(0 to 4); +signal ac_an_dcfg_scan_out : std_ulogic_vector(0 to 2); +signal ac_an_debug_trigger : std_ulogic_vector(0 to 3); +signal ac_an_func_scan_out : std_ulogic_vector(0 to 63); +signal ac_an_gptr_scan_out : std_ulogic; +signal ac_an_repr_scan_out : std_ulogic; +signal ac_an_time_scan_out : std_ulogic; +signal ac_an_special_attn : std_ulogic_vector(0 to 3); +signal ac_an_checkstop : std_ulogic_vector(0 to 2); +signal ac_an_dcr_act : std_ulogic; +signal ac_an_dcr_val : std_ulogic; +signal ac_an_dcr_read : std_ulogic; +signal ac_an_dcr_user : std_ulogic; +signal ac_an_dcr_etid : std_ulogic_vector(0 to 1); +signal ac_an_dcr_addr : std_ulogic_vector(11 to 20); +signal ac_an_dcr_data : std_ulogic_vector(0 to 63); + +signal ac_an_machine_check : std_ulogic_vector(0 to 3); +signal ac_an_pm_thread_running : std_ulogic_vector(0 to 3); +signal ac_an_recov_err : std_ulogic_vector(0 to 2); +signal ac_an_local_checkstop : std_ulogic_vector(0 to 2); +signal an_ac_external_mchk : std_ulogic_vector(0 to 3); + +signal gnd : power_logic; +signal vcs : power_logic; +signal vdd : power_logic; +signal vio : power_logic; + +signal node_scom_dch_in : std_ulogic; +signal node_scom_cch_in : std_ulogic; +signal node_scom_dch_out : std_ulogic; +signal node_scom_cch_out : std_ulogic; + +signal an_ac_camfence_en_dc : std_ulogic; + +signal tidn : std_ulogic; +signal tiup : std_ulogic; + +begin + +tidn <= '0'; +tiup <= '1'; + +a2_nclk.clk <= clk; +a2_nclk.clk2x <= clk2x; +a2_nclk.clk4x <= '0'; +a2_nclk.sreset <= not reset_n; + +alt_disp <= tidn; +d_mode <= tiup; +delay_lclkr <= tidn; +mpw1_b <= tidn; +mpw2_b <= tidn; +scdis_b <= tidn; +an_ac_ccenable_dc <= tiup; +an_ac_scan_type_dc <= tiup & tiup & tiup & tiup & tiup & tiup & tiup & tiup & tiup; + +-- most/all of this can be removed from all logic for fpga +an_ac_func_scan_in <= (others => '0'); +an_ac_regf_scan_in <= (others => '0'); +an_ac_bcfg_scan_in <= (others => '0'); +an_ac_dcfg_scan_in <= (others => '0'); +an_ac_abst_scan_in <= (others => '0'); +an_ac_gptr_scan_in <= '0'; +an_ac_repr_scan_in <= '0'; +an_ac_time_scan_in <= '0'; +an_ac_atpg_en_dc <= '0'; +an_ac_scan_dis_dc_b <= '1'; +an_ac_camfence_en_dc <= '0'; +an_ac_abist_start_test <= '0'; +an_ac_abist_mode_dc <= '0'; +an_ac_lbist_en_dc <= '0'; +an_ac_lbist_ac_mode_dc <= '0'; +an_ac_lbist_ip_dc <= '0'; +an_ac_fce_7 <= '0'; +an_ac_sg_7 <= '0'; +an_ac_gsd_test_acmode_dc <= '0'; +an_ac_lbist_ary_wrt_thru_dc <= '0'; +an_ac_gsd_test_enable_dc <= '0'; +an_ac_scan_diag_dc <= '0'; +an_ac_psro_enable_dc <= (others => '0'); +an_ac_ccflush_dc <= '0'; + +-- misc +an_ac_flh2l2_gate <= flh2l2_gate; +an_ac_external_mchk <= ext_mchk; +an_ac_checkstop <= ext_checkstop; +an_ac_debug_stop <= debug_stop; +an_ac_hang_pulse <= hang_pulse; +thread_running <= ac_an_pm_thread_running; +-- errors +mchk <= ac_an_machine_check; +recov_err <= ac_an_recov_err; +checkstop <= ac_an_local_checkstop; +-- scom +an_ac_scom_sat_id <= scom_sat_id; +node_scom_dch_in <= scom_dch_in; +node_scom_cch_in <= scom_cch_in; +scom_dch_out <= node_scom_dch_out; +scom_cch_out <= node_scom_cch_out; + +-- smp and other a2l2_axi stuff +an_ac_user_defined <= (others => '0'); +an_ac_req_spare_ctrl_a1 <= (others => '0'); + +an_ac_icbi_ack <= '0'; +an_ac_icbi_ack_thread <= (others => '0'); + +an_ac_back_inv <= '0'; +an_ac_back_inv_gs <= '0'; +an_ac_back_inv_local <= '0'; +an_ac_back_inv_lbit <= '0'; +an_ac_back_inv_ind <= '0'; +an_ac_back_inv_addr <= (others => '0'); +an_ac_back_inv_lpar_id <= (others => '0'); +an_ac_back_inv_target <= (others => '0'); + +an_ac_reld_ditc <= '0'; + +an_ac_dcr_act <= '0'; +an_ac_dcr_val <= '0'; +an_ac_dcr_read <= '0'; +an_ac_dcr_etid <= (others => '0'); +an_ac_dcr_data <= (others => '0'); +an_ac_dcr_done <= '0'; + +an_ac_reset_1_complete <= '0'; +an_ac_reset_2_complete <= '0'; +an_ac_reset_3_complete <= '0'; +an_ac_reset_wd_complete <= '0'; + +an_ac_sleep_en <= (others => '0'); +an_ac_malf_alert <= '0'; + +acq: entity work.acq_soft(acq_soft) + generic map( + error_width => error_width, + expand_type => expand_type, + expand_tlb_type => expand_tlb_type, + extclass_width => extclass_width, + inv_seq_width => inv_seq_width, + lpid_width => lpid_width, + pid_width => pid_width, + ra_entry_width => ra_entry_width, + real_addr_width => real_addr_width, + threads => threads, + + xu_real_data_add => xu_real_data_add, + st_data_32b_mode => st_data_32b_mode, + ac_st_data_32b_mode => ac_st_data_32b_mode + ) + port map ( + an_ac_back_inv => an_ac_back_inv, + an_ac_back_inv_addr => an_ac_back_inv_addr, + an_ac_back_inv_lbit => an_ac_back_inv_lbit, + an_ac_back_inv_gs => an_ac_back_inv_gs, + an_ac_back_inv_ind => an_ac_back_inv_ind, + an_ac_back_inv_local => an_ac_back_inv_local, + an_ac_back_inv_lpar_id => an_ac_back_inv_lpar_id, + an_ac_back_inv_target => an_ac_back_inv_target, + an_ac_crit_interrupt => crit_interrupt, + an_ac_dcr_act => an_ac_dcr_act, + an_ac_dcr_val => an_ac_dcr_val, + an_ac_dcr_read => an_ac_dcr_read, + an_ac_dcr_etid => an_ac_dcr_etid, + an_ac_dcr_data => an_ac_dcr_data, + an_ac_dcr_done => an_ac_dcr_done, + an_ac_ext_interrupt => ext_interrupt, + an_ac_flh2l2_gate => an_ac_flh2l2_gate, + an_ac_reld_core_tag => an_ac_reld_core_tag, + an_ac_reld_data => an_ac_reld_data, + an_ac_reld_data_vld => an_ac_reld_data_vld, + an_ac_reld_ecc_err => an_ac_reld_ecc_err, + an_ac_reld_ecc_err_ue => an_ac_reld_ecc_err_ue, + an_ac_reld_qw => an_ac_reld_qw, + an_ac_reld_data_coming => an_ac_reld_data_coming, + an_ac_reld_ditc => an_ac_reld_ditc, + an_ac_reld_crit_qw => an_ac_reld_crit_qw, + an_ac_reld_l1_dump => an_ac_reld_l1_dump, + an_ac_regf_scan_in => an_ac_regf_scan_in, + an_ac_req_ld_pop => an_ac_req_ld_pop, + an_ac_req_spare_ctrl_a1 => an_ac_req_spare_ctrl_a1, + an_ac_req_st_gather => an_ac_req_st_gather, + an_ac_req_st_pop => an_ac_req_st_pop, + an_ac_req_st_pop_thrd => an_ac_req_st_pop_thrd, + an_ac_reservation_vld => an_ac_reservation_vld, + an_ac_sleep_en => an_ac_sleep_en, + an_ac_stcx_complete => an_ac_stcx_complete, + an_ac_stcx_pass => an_ac_stcx_pass, + an_ac_sync_ack => an_ac_sync_ack, + an_ac_icbi_ack => an_ac_icbi_ack, + an_ac_icbi_ack_thread => an_ac_icbi_ack_thread, + a2_nclk => a2_nclk, + an_ac_abist_mode_dc => an_ac_abist_mode_dc, + an_ac_abist_start_test => an_ac_abist_start_test, + an_ac_abst_scan_in => an_ac_abst_scan_in, + an_ac_rtim_sl_thold_7 => thold, + an_ac_ary_nsl_thold_7 => thold, + an_ac_func_nsl_thold_7 => thold, + an_ac_func_sl_thold_7 => thold, + an_ac_atpg_en_dc => an_ac_atpg_en_dc, + an_ac_bcfg_scan_in => an_ac_bcfg_scan_in, + an_ac_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc, + an_ac_ccenable_dc => an_ac_ccenable_dc, + an_ac_ccflush_dc => an_ac_ccflush_dc, + an_ac_coreid => core_id, + an_ac_lbist_ip_dc => an_ac_lbist_ip_dc, + an_ac_malf_alert => an_ac_malf_alert, + an_ac_reset_1_complete => an_ac_reset_1_complete, + an_ac_reset_2_complete => an_ac_reset_2_complete, + an_ac_reset_3_complete => an_ac_reset_3_complete, + an_ac_reset_wd_complete => an_ac_reset_wd_complete, + an_ac_dcfg_scan_in => an_ac_dcfg_scan_in, + an_ac_debug_stop => an_ac_debug_stop, + an_ac_external_mchk => an_ac_external_mchk, + an_ac_fce_7 => an_ac_fce_7, + an_ac_func_scan_in => an_ac_func_scan_in, + an_ac_gptr_scan_in => an_ac_gptr_scan_in, + an_ac_gsd_test_acmode_dc => an_ac_gsd_test_acmode_dc, + an_ac_gsd_test_enable_dc => an_ac_gsd_test_enable_dc, + an_ac_hang_pulse => an_ac_hang_pulse, + an_ac_lbist_en_dc => an_ac_lbist_en_dc, + an_ac_lbist_ac_mode_dc => an_ac_lbist_ac_mode_dc, + an_ac_perf_interrupt => perf_interrupt, + an_ac_pm_thread_stop => thread_stop, + an_ac_psro_enable_dc => an_ac_psro_enable_dc, + an_ac_repr_scan_in => an_ac_repr_scan_in, + an_ac_scan_diag_dc => an_ac_scan_diag_dc, + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b, + an_ac_scan_type_dc => an_ac_scan_type_dc, + an_ac_scom_cch => node_scom_cch_in, + an_ac_scom_dch => node_scom_dch_in, + an_ac_scom_sat_id => an_ac_scom_sat_id, + an_ac_sg_7 => an_ac_sg_7, + an_ac_checkstop => an_ac_checkstop, + an_ac_tb_update_enable => tb_update_enable, + an_ac_tb_update_pulse => tb_update_pulse, + an_ac_time_scan_in => an_ac_time_scan_in, + ac_an_back_inv_reject => ac_an_back_inv_reject, + ac_an_box_empty => ac_an_box_empty, + ac_an_lpar_id => ac_an_lpar_id, + ac_an_machine_check => ac_an_machine_check, + ac_an_power_managed => ac_an_power_managed, + ac_an_req => ac_an_req, + ac_an_req_endian => ac_an_req_endian, + ac_an_req_ld_core_tag => ac_an_req_ld_core_tag, + ac_an_req_ld_xfr_len => ac_an_req_ld_xfr_len, + ac_an_req_pwr_token => ac_an_req_pwr_token, + ac_an_req_ra => ac_an_req_ra, + ac_an_req_spare_ctrl_a0 => ac_an_req_spare_ctrl_a0, + ac_an_req_thread => ac_an_req_thread, + ac_an_req_ttype => ac_an_req_ttype, + ac_an_req_user_defined => ac_an_req_user_defined, + ac_an_req_wimg_g => ac_an_req_wimg_g, + ac_an_req_wimg_i => ac_an_req_wimg_i, + ac_an_req_wimg_m => ac_an_req_wimg_m, + ac_an_req_wimg_w => ac_an_req_wimg_w, + ac_an_reld_ditc_pop => ac_an_reld_ditc_pop, + ac_an_rvwinkle_mode => ac_an_rvwinkle_mode, + ac_an_st_byte_enbl => ac_an_st_byte_enbl, + ac_an_st_data => ac_an_st_data, + ac_an_st_data_pwr_token => ac_an_st_data_pwr_token, + ac_an_fu_bypass_events => ac_an_fu_bypass_events, + ac_an_iu_bypass_events => ac_an_iu_bypass_events, + ac_an_mm_bypass_events => ac_an_mm_bypass_events, + ac_an_debug_bus => ac_an_debug_bus, + ac_an_event_bus => ac_an_event_bus, + ac_an_trace_triggers => ac_an_trace_triggers, + ac_an_abist_done_dc => ac_an_abist_done_dc, + ac_an_abst_scan_out => ac_an_abst_scan_out, + ac_an_bcfg_scan_out => ac_an_bcfg_scan_out, + ac_an_dcfg_scan_out => ac_an_dcfg_scan_out, + ac_an_debug_trigger => ac_an_debug_trigger, + ac_an_func_scan_out => ac_an_func_scan_out, + ac_an_gptr_scan_out => ac_an_gptr_scan_out, + ac_an_pm_thread_running => ac_an_pm_thread_running, + ac_an_psro_ringsig => ac_an_psro_ringsig, + ac_an_recov_err => ac_an_recov_err, + ac_an_repr_scan_out => ac_an_repr_scan_out, + ac_an_scom_cch => node_scom_cch_out, + ac_an_scom_dch => node_scom_dch_out, + ac_an_time_scan_out => ac_an_time_scan_out, + ac_an_special_attn => ac_an_special_attn, + ac_an_checkstop => ac_an_checkstop, + ac_an_local_checkstop => ac_an_local_checkstop, + ac_an_dcr_act => ac_an_dcr_act, + ac_an_dcr_val => ac_an_dcr_val, + ac_an_dcr_read => ac_an_dcr_read, + ac_an_dcr_user => ac_an_dcr_user, + ac_an_dcr_etid => ac_an_dcr_etid, + ac_an_dcr_addr => ac_an_dcr_addr, + ac_an_dcr_data => ac_an_dcr_data, + an_ac_camfence_en_dc => an_ac_camfence_en_dc, + + gnd => gnd, + vcs => vcs, + vdd => vdd + ); + +a2l2_axi: entity work.a2l2_axi(a2l2_axi) +generic map( + C_M00_AXI_ID_WIDTH => C_M00_AXI_ID_WIDTH, + C_M00_AXI_ADDR_WIDTH => C_M00_AXI_ADDR_WIDTH, + C_M00_AXI_DATA_WIDTH => C_M00_AXI_DATA_WIDTH, + C_M00_AXI_AWUSER_WIDTH => C_M00_AXI_AWUSER_WIDTH, + C_M00_AXI_ARUSER_WIDTH => C_M00_AXI_ARUSER_WIDTH, + C_M00_AXI_WUSER_WIDTH => C_M00_AXI_WUSER_WIDTH, + C_M00_AXI_RUSER_WIDTH => C_M00_AXI_RUSER_WIDTH, + C_M00_AXI_BUSER_WIDTH => C_M00_AXI_BUSER_WIDTH + ) +port map( + clk => clk, + reset_n => reset_n, + err => a2l2_axi_err, + ac_an_req => ac_an_req, + ac_an_req_endian => ac_an_req_endian, + ac_an_req_ld_core_tag => ac_an_req_ld_core_tag, + ac_an_req_ld_xfr_len => ac_an_req_ld_xfr_len, + ac_an_req_pwr_token => ac_an_req_pwr_token, + ac_an_req_ra => ac_an_req_ra, + ac_an_req_thread => ac_an_req_thread, + ac_an_req_ttype => ac_an_req_ttype, + ac_an_req_user_defined => ac_an_req_user_defined, + ac_an_req_wimg_g => ac_an_req_wimg_g, + ac_an_req_wimg_i => ac_an_req_wimg_i, + ac_an_req_wimg_m => ac_an_req_wimg_m, + ac_an_req_wimg_w => ac_an_req_wimg_w, + ac_an_st_byte_enbl => ac_an_st_byte_enbl, + ac_an_st_data => ac_an_st_data, + ac_an_st_data_pwr_token => ac_an_st_data_pwr_token, + an_ac_reld_core_tag => an_ac_reld_core_tag, + an_ac_reld_data => an_ac_reld_data, + an_ac_reld_data_vld => an_ac_reld_data_vld, + an_ac_reld_ecc_err => an_ac_reld_ecc_err, + an_ac_reld_ecc_err_ue => an_ac_reld_ecc_err_ue, + an_ac_reld_qw => an_ac_reld_qw, + an_ac_reld_data_coming => an_ac_reld_data_coming, + an_ac_reld_crit_qw => an_ac_reld_crit_qw, + an_ac_reld_l1_dump => an_ac_reld_l1_dump, + an_ac_req_ld_pop => an_ac_req_ld_pop, + an_ac_req_st_pop => an_ac_req_st_pop, + an_ac_req_st_gather => an_ac_req_st_gather, + an_ac_req_st_pop_thrd => an_ac_req_st_pop_thrd, + an_ac_reservation_vld => an_ac_reservation_vld, + an_ac_stcx_complete => an_ac_stcx_complete, + an_ac_stcx_pass => an_ac_stcx_pass, + an_ac_sync_ack => an_ac_sync_ack, + m00_axi_awid => m00_axi_awid, + m00_axi_awaddr => m00_axi_awaddr, + m00_axi_awlen => m00_axi_awlen, + m00_axi_awsize => m00_axi_awsize, + m00_axi_awburst => m00_axi_awburst, + m00_axi_awlock => m00_axi_awlock, + m00_axi_awcache => m00_axi_awcache, + m00_axi_awprot => m00_axi_awprot, + m00_axi_awqos => m00_axi_awqos, + m00_axi_awuser => m00_axi_awuser, + m00_axi_awvalid => m00_axi_awvalid, + m00_axi_awready => m00_axi_awready, + m00_axi_wdata => m00_axi_wdata, + m00_axi_wstrb => m00_axi_wstrb, + m00_axi_wlast => m00_axi_wlast, + m00_axi_wuser => m00_axi_wuser, + m00_axi_wvalid => m00_axi_wvalid, + m00_axi_wready => m00_axi_wready, + m00_axi_bid => m00_axi_bid, + m00_axi_bresp => m00_axi_bresp, + m00_axi_buser => m00_axi_buser, + m00_axi_bvalid => m00_axi_bvalid, + m00_axi_bready => m00_axi_bready, + m00_axi_arid => m00_axi_arid, + m00_axi_araddr => m00_axi_araddr, + m00_axi_arlen => m00_axi_arlen, + m00_axi_arsize => m00_axi_arsize, + m00_axi_arburst => m00_axi_arburst, + m00_axi_arlock => m00_axi_arlock, + m00_axi_arcache => m00_axi_arcache, + m00_axi_arprot => m00_axi_arprot, + m00_axi_arqos => m00_axi_arqos, + m00_axi_aruser => m00_axi_aruser, + m00_axi_arvalid => m00_axi_arvalid, + m00_axi_arready => m00_axi_arready, + m00_axi_rid => m00_axi_rid, + m00_axi_rdata => m00_axi_rdata, + m00_axi_rresp => m00_axi_rresp, + m00_axi_rlast => m00_axi_rlast, + m00_axi_ruser => m00_axi_ruser, + m00_axi_rvalid => m00_axi_rvalid, + m00_axi_rready => m00_axi_rready + ); + +end a2x_axi; diff --git a/rel/src/vhdl/work/a2x_axi_intr.vhdl b/rel/src/vhdl/work/a2x_axi_intr.vhdl new file mode 100644 index 0000000..e77bc67 --- /dev/null +++ b/rel/src/vhdl/work/a2x_axi_intr.vhdl @@ -0,0 +1,631 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity a2x_axi_intr is + generic ( + + C_S_AXI_DATA_WIDTH : integer := 32; + C_S_AXI_ADDR_WIDTH : integer := 5; + C_NUM_OF_INTR : integer := 1; + C_INTR_SENSITIVITY : std_logic_vector := x"FFFFFFFF"; + C_INTR_ACTIVE_STATE : std_logic_vector := x"FFFFFFFF"; + C_IRQ_SENSITIVITY : integer := 1; + C_IRQ_ACTIVE_STATE : integer := 1 + ); + port ( + + + S_AXI_ACLK : in std_logic; + S_AXI_ARESETN : in std_logic; + S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + S_AXI_AWPROT : in std_logic_vector(2 downto 0); + S_AXI_AWVALID : in std_logic; + S_AXI_AWREADY : out std_logic; + S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); + S_AXI_WVALID : in std_logic; + S_AXI_WREADY : out std_logic; + S_AXI_BRESP : out std_logic_vector(1 downto 0); + S_AXI_BVALID : out std_logic; + S_AXI_BREADY : in std_logic; + S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + S_AXI_ARPROT : in std_logic_vector(2 downto 0); + S_AXI_ARVALID : in std_logic; + S_AXI_ARREADY : out std_logic; + S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + S_AXI_RRESP : out std_logic_vector(1 downto 0); + S_AXI_RVALID : out std_logic; + S_AXI_RREADY : in std_logic; + irq : out std_logic + ); +end a2x_axi_intr; + +architecture arch_imp of a2x_axi_intr is + + signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + signal axi_awready : std_logic; + signal axi_wready : std_logic; + signal axi_bresp : std_logic_vector(1 downto 0); + signal axi_bvalid : std_logic; + signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + signal axi_arready : std_logic; + signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal axi_rresp : std_logic_vector(1 downto 0); + signal axi_rvalid : std_logic; + signal reg_global_intr_en :std_logic_vector(0 downto 0); + signal reg_intr_en :std_logic_vector(C_NUM_OF_INTR-1 downto 0); + signal reg_intr_sts :std_logic_vector(C_NUM_OF_INTR-1 downto 0); + signal reg_intr_ack :std_logic_vector(C_NUM_OF_INTR-1 downto 0); + signal reg_intr_pending :std_logic_vector(C_NUM_OF_INTR-1 downto 0); + + signal intr :std_logic_vector(C_NUM_OF_INTR-1 downto 0); + signal det_intr :std_logic_vector(C_NUM_OF_INTR-1 downto 0); + + signal intr_reg_rden :std_logic; + signal intr_reg_wren :std_logic; + signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal intr_counter :std_logic_vector(3 downto 0); + + signal intr_all : std_logic; + signal intr_ack_all : std_logic; + signal s_irq : std_logic; + signal intr_all_ff : std_logic; + signal intr_ack_all_ff: std_logic; + signal aw_en : std_logic; + + + function or_reduction (vec : in std_logic_vector) return std_logic is + variable res_v : std_logic := '0'; + begin + for i in vec'range loop + res_v := res_v or vec(i); + end loop; + return res_v; + end function; +begin + + S_AXI_AWREADY <= axi_awready; + S_AXI_WREADY <= axi_wready; + S_AXI_BRESP <= axi_bresp; + S_AXI_BVALID <= axi_bvalid; + S_AXI_ARREADY <= axi_arready; + S_AXI_RDATA <= axi_rdata; + S_AXI_RRESP <= axi_rresp; + S_AXI_RVALID <= axi_rvalid; + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_awready <= '0'; + aw_en <= '1'; + else + if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then + axi_awready <= '1'; + aw_en <= '0'; + elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then + aw_en <= '1'; + axi_awready <= '0'; + else + axi_awready <= '0'; + end if; + end if; + end if; + end process; + + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_awaddr <= (others => '0'); + else + if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then + axi_awaddr <= S_AXI_AWADDR; + end if; + end if; + end if; + end process; + + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_wready <= '0'; + else + if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1' and aw_en = '1') then + axi_wready <= '1'; + else + axi_wready <= '0'; + end if; + end if; + end if; + end process; + + intr_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ; + + gen_intr_reg : for i in 0 to (C_NUM_OF_INTR - 1) generate + begin + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + reg_global_intr_en <= (others => '0'); + else + if (intr_reg_wren = '1' and axi_awaddr(4 downto 2) = "000") then + reg_global_intr_en(0) <= S_AXI_WDATA(0); + end if; + end if; + end if; + end process; + + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + reg_intr_en(i) <= '0'; + else + if (intr_reg_wren = '1' and axi_awaddr(4 downto 2) = "001") then + reg_intr_en(i) <= S_AXI_WDATA(i); + end if; + end if; + end if; + end process; + + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if (S_AXI_ARESETN = '0' or reg_intr_ack(i) = '1') then + reg_intr_sts(i) <= '0'; + else + reg_intr_sts(i) <= det_intr(i); + end if; + end if; + end process; + + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if (S_AXI_ARESETN = '0' or reg_intr_ack(i) = '1') then + reg_intr_ack(i) <= '0'; + else + if (intr_reg_wren = '1' and axi_awaddr(4 downto 2) = "011") then + reg_intr_ack(i) <= S_AXI_WDATA(i); + end if; + end if; + end if; + end process; + + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if (S_AXI_ARESETN = '0' or reg_intr_ack(i) = '1') then + reg_intr_pending(i) <= '0'; + else + reg_intr_pending(i) <= reg_intr_sts(i) and reg_intr_en(i); + end if; + end if; + end process; + + + end generate gen_intr_reg; + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_bvalid <= '0'; + axi_bresp <= "00"; + else + if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then + axi_bvalid <= '1'; + axi_bresp <= "00"; + elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then + axi_bvalid <= '0'; + end if; + end if; + end if; + end process; + + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_arready <= '0'; + axi_araddr <= (others => '1'); + else + if (axi_arready = '0' and S_AXI_ARVALID = '1') then + axi_arready <= '1'; + axi_araddr <= S_AXI_ARADDR; + else + axi_arready <= '0'; + end if; + end if; + end if; + end process; + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_rvalid <= '0'; + axi_rresp <= "00"; + else + if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then + axi_rvalid <= '1'; + axi_rresp <= "00"; + elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then + axi_rvalid <= '0'; + end if; + end if; + end if; + end process; + + intr_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ; + + RDATA_INTR_NUM_32: if (C_NUM_OF_INTR=32) generate + begin + + process (reg_global_intr_en, reg_intr_en, reg_intr_sts, reg_intr_ack, reg_intr_pending, axi_araddr, S_AXI_ARESETN, intr_reg_rden) + variable loc_addr :std_logic_vector(2 downto 0); + begin + if S_AXI_ARESETN = '0' then + reg_data_out <= (others => '0'); + else + loc_addr := axi_araddr(4 downto 2); + case loc_addr is + when "000" => + reg_data_out <= x"0000000" & "000" & reg_global_intr_en(0); + when "001" => + reg_data_out <= reg_intr_en; + when "010" => + reg_data_out <= reg_intr_sts; + when "011" => + reg_data_out <= reg_intr_ack; + when "100" => + reg_data_out <= reg_intr_pending; + when others => + reg_data_out <= (others => '0'); + end case; + end if; + end process; + + end generate RDATA_INTR_NUM_32; + + RDATA_INTR_NUM_LESS_32: if (C_NUM_OF_INTR/=32) generate + begin + + process (reg_global_intr_en, reg_intr_en, reg_intr_sts, reg_intr_ack, reg_intr_pending, axi_araddr, S_AXI_ARESETN, intr_reg_rden) + variable loc_addr :std_logic_vector(2 downto 0); + variable zero : std_logic_vector (C_S_AXI_DATA_WIDTH-C_NUM_OF_INTR-1 downto 0); + begin + if S_AXI_ARESETN = '0' then + reg_data_out <= (others => '0'); + zero := (others=>'0'); + else + zero := (others=>'0'); + loc_addr := axi_araddr(4 downto 2); + case loc_addr is + when "000" => + reg_data_out <= x"0000000" & "000" & reg_global_intr_en(0); + when "001" => + reg_data_out <= zero & reg_intr_en; + when "010" => + reg_data_out <= zero & reg_intr_sts; + when "011" => + reg_data_out <= zero & reg_intr_ack; + when "100" => + reg_data_out <= zero & reg_intr_pending; + when others => + reg_data_out <= (others => '0'); + end case; + end if; + end process; + + end generate RDATA_INTR_NUM_LESS_32; + process( S_AXI_ACLK ) is + begin + if (rising_edge (S_AXI_ACLK)) then + if ( S_AXI_ARESETN = '0' ) then + axi_rdata <= (others => '0'); + else + if (intr_reg_rden = '1') then + axi_rdata <= reg_data_out; + end if; + end if; + end if; + end process; + + + process( S_AXI_ACLK ) is + begin + if (rising_edge (S_AXI_ACLK)) then + if ( S_AXI_ARESETN = '0') then + intr_counter <= (others => '1'); + elsif (intr_counter /= x"0") then + intr_counter <= std_logic_vector (unsigned(intr_counter) - 1); + end if; + end if; + end process; + + + process( S_AXI_ACLK ) is + begin + if (rising_edge (S_AXI_ACLK)) then + if ( S_AXI_ARESETN = '0') then + intr <= (others => '0'); + else + if (intr_counter = x"a") then + intr <= (others => '1'); + else + intr <= (others => '0'); + end if; + end if; + end if; + end process; + + process (S_AXI_ACLK) + variable temp : std_logic; + begin + if (rising_edge (S_AXI_ACLK)) then + if( S_AXI_ARESETN = '0' or intr_ack_all_ff = '1') then + intr_all <= '0'; + else + intr_all <= or_reduction(reg_intr_pending); + end if; + end if; + end process; + + process (S_AXI_ACLK) + variable temp : std_logic; + begin + if (rising_edge (S_AXI_ACLK)) then + if( S_AXI_ARESETN = '0' or intr_ack_all_ff = '1') then + intr_ack_all <= '0'; + else + intr_ack_all <= or_reduction(reg_intr_ack); + end if; + end if; + end process; + + process( S_AXI_ACLK ) is + begin + if (rising_edge (S_AXI_ACLK)) then + if ( S_AXI_ARESETN = '0') then + intr_all_ff <= '0'; + intr_ack_all_ff <= '0'; + else + intr_all_ff <= intr_all; + intr_ack_all_ff <= intr_ack_all; + end if; + end if; + end process; + + + gen_intr_detection : for i in 0 to (C_NUM_OF_INTR - 1) generate + signal s_irq_lvl: std_logic; + begin + gen_intr_level_detect: if (C_INTR_SENSITIVITY(i) = '1') generate + begin + gen_intr_active_high_detect: if (C_INTR_ACTIVE_STATE(i) = '1') generate + begin + + process( S_AXI_ACLK ) is + begin + if (rising_edge (S_AXI_ACLK)) then + if ( S_AXI_ARESETN = '0' or reg_intr_ack(i) = '1') then + det_intr(i) <= '0'; + else + if (intr(i) = '1') then + det_intr(i) <= '1'; + end if; + end if; + end if; + end process; + end generate gen_intr_active_high_detect; + + gen_intr_active_low_detect: if (C_INTR_ACTIVE_STATE(i) = '0') generate + process( S_AXI_ACLK ) is + begin + if (rising_edge (S_AXI_ACLK)) then + if ( S_AXI_ARESETN = '0' or reg_intr_ack(i) = '1') then + det_intr(i) <= '0'; + else + if (intr(i) = '0') then + det_intr(i) <= '1'; + end if; + end if; + end if; + end process; + end generate gen_intr_active_low_detect; + + end generate gen_intr_level_detect; + + + gen_intr_edge_detect: if (C_INTR_SENSITIVITY(i) = '0') generate + signal intr_edge : std_logic_vector (C_NUM_OF_INTR-1 downto 0); + signal intr_ff : std_logic_vector (C_NUM_OF_INTR-1 downto 0); + signal intr_ff2 : std_logic_vector (C_NUM_OF_INTR-1 downto 0); + begin + gen_intr_rising_edge_detect: if (C_INTR_ACTIVE_STATE(i) = '1') generate + begin + process( S_AXI_ACLK ) is + begin + if (rising_edge (S_AXI_ACLK)) then + if ( S_AXI_ARESETN = '0' or reg_intr_ack(i) = '1') then + intr_ff(i) <= '0'; + intr_ff2(i) <= '0'; + else + intr_ff(i) <= intr(i); + intr_ff2(i) <= intr_ff(i); + end if; + end if; + end process; + + intr_edge(i) <= intr_ff(i) and (not intr_ff2(i)); + + process( S_AXI_ACLK ) is + begin + if (rising_edge (S_AXI_ACLK)) then + if ( S_AXI_ARESETN = '0' or reg_intr_ack(i) = '1') then + det_intr(i) <= '0'; + elsif (intr_edge(i) = '1') then + det_intr(i) <= '1'; + end if; + end if; + end process; + + end generate gen_intr_rising_edge_detect; + + gen_intr_falling_edge_detect: if (C_INTR_ACTIVE_STATE(i) = '0') generate + begin + process( S_AXI_ACLK ) is + begin + if (rising_edge (S_AXI_ACLK)) then + if ( S_AXI_ARESETN = '0' or reg_intr_ack(i) = '1') then + intr_ff(i) <= '0'; + intr_ff2(i) <= '0'; + else + intr_ff(i) <= intr(i); + intr_ff2(i) <= intr_ff(i); + end if; + end if; + end process; + + intr_edge(i) <= intr_ff2(i) and (not intr_ff(i)); + + process( S_AXI_ACLK ) is + begin + if (rising_edge (S_AXI_ACLK)) then + if ( S_AXI_ARESETN = '0' or reg_intr_ack(i) = '1') then + det_intr(i) <= '0'; + elsif (intr_edge(i) = '1') then + det_intr(i) <= '1'; + end if; + end if; + end process; + end generate gen_intr_falling_edge_detect; + + end generate gen_intr_edge_detect; + + + gen_irq_level: if (C_IRQ_SENSITIVITY = 1) generate + begin + irq_level_high: if (C_IRQ_ACTIVE_STATE = 1) generate + begin + process( S_AXI_ACLK ) is + begin + if (rising_edge (S_AXI_ACLK)) then + if ( S_AXI_ARESETN = '0' or intr_ack_all = '1') then + s_irq_lvl <= '0'; + elsif (intr_all = '1' and reg_global_intr_en(0) = '1') then + s_irq_lvl <= '1'; + end if; + end if; + end process; + + s_irq <= s_irq_lvl; + end generate irq_level_high; + + + irq_level_low: if (C_IRQ_ACTIVE_STATE = 0) generate + process( S_AXI_ACLK ) is + begin + if (rising_edge (S_AXI_ACLK)) then + if ( S_AXI_ARESETN = '0' or intr_ack_all = '1') then + s_irq_lvl <= '1'; + elsif (intr_all = '1' and reg_global_intr_en(0) = '1') then + s_irq_lvl <= '0'; + end if; + end if; + end process; + + s_irq <= s_irq_lvl; + end generate irq_level_low; + + end generate gen_irq_level; + + + gen_irq_edge: if (C_IRQ_SENSITIVITY = 0) generate + + signal s_irq_lvl_ff:std_logic; + begin + irq_rising_edge: if (C_IRQ_ACTIVE_STATE = 1) generate + begin + process( S_AXI_ACLK ) is + begin + if (rising_edge (S_AXI_ACLK)) then + if ( S_AXI_ARESETN = '0' or intr_ack_all = '1') then + s_irq_lvl <= '0'; + s_irq_lvl_ff <= '0'; + elsif (intr_all = '1' and reg_global_intr_en(0) = '1') then + s_irq_lvl <= '1'; + s_irq_lvl_ff <= s_irq_lvl; + end if; + end if; + end process; + + s_irq <= s_irq_lvl and (not s_irq_lvl_ff); + end generate irq_rising_edge; + + irq_falling_edge: if (C_IRQ_ACTIVE_STATE = 0) generate + begin + process( S_AXI_ACLK ) is + begin + if (rising_edge (S_AXI_ACLK)) then + if ( S_AXI_ARESETN = '0' or intr_ack_all = '1') then + s_irq_lvl <= '1'; + s_irq_lvl_ff <= '1'; + elsif (intr_all = '1' and reg_global_intr_en(0) = '1') then + s_irq_lvl <= '0'; + s_irq_lvl_ff <= s_irq_lvl; + end if; + end if; + end process; + + s_irq <= not (s_irq_lvl_ff and (not s_irq_lvl)); + end generate irq_falling_edge; + + end generate gen_irq_edge; + + irq <= s_irq; + end generate gen_intr_detection; + + + +end arch_imp; diff --git a/rel/src/vhdl/work/a2x_axi_reg.vhdl b/rel/src/vhdl/work/a2x_axi_reg.vhdl new file mode 100644 index 0000000..3122ae6 --- /dev/null +++ b/rel/src/vhdl/work/a2x_axi_reg.vhdl @@ -0,0 +1,381 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity a2x_axi_reg is + generic ( + + + + C_S00_AXI_DATA_WIDTH : integer := 32; + C_S00_AXI_ADDR_WIDTH : integer := 6; + + C_S_AXI_INTR_DATA_WIDTH : integer := 32; + C_S_AXI_INTR_ADDR_WIDTH : integer := 5; + C_NUM_OF_INTR : integer := 1; + C_INTR_SENSITIVITY : std_logic_vector := x"FFFFFFFF"; + C_INTR_ACTIVE_STATE : std_logic_vector := x"FFFFFFFF"; + C_IRQ_SENSITIVITY : integer := 1; + C_IRQ_ACTIVE_STATE : integer := 1 + ); + port ( + + reg_cmd_00 : in std_logic_vector(1 downto 0); + reg_cmd_01 : in std_logic_vector(1 downto 0); + reg_cmd_02 : in std_logic_vector(1 downto 0); + reg_cmd_03 : in std_logic_vector(1 downto 0); + reg_cmd_04 : in std_logic_vector(1 downto 0); + reg_cmd_05 : in std_logic_vector(1 downto 0); + reg_cmd_06 : in std_logic_vector(1 downto 0); + reg_cmd_07 : in std_logic_vector(1 downto 0); + reg_cmd_08 : in std_logic_vector(1 downto 0); + reg_cmd_09 : in std_logic_vector(1 downto 0); + reg_cmd_0A : in std_logic_vector(1 downto 0); + reg_cmd_0B : in std_logic_vector(1 downto 0); + reg_cmd_0C : in std_logic_vector(1 downto 0); + reg_cmd_0D : in std_logic_vector(1 downto 0); + reg_cmd_0E : in std_logic_vector(1 downto 0); + reg_cmd_0F : in std_logic_vector(1 downto 0); + reg_in_00 : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); + reg_in_01 : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); + reg_in_02 : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); + reg_in_03 : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); + reg_in_04 : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); + reg_in_05 : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); + reg_in_06 : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); + reg_in_07 : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); + reg_in_08 : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); + reg_in_09 : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); + reg_in_0A : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); + reg_in_0B : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); + reg_in_0C : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); + reg_in_0D : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); + reg_in_0E : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); + reg_in_0F : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); + reg_out_00 : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); + reg_out_01 : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); + reg_out_02 : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); + reg_out_03 : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); + reg_out_04 : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); + reg_out_05 : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); + reg_out_06 : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); + reg_out_07 : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); + reg_out_08 : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); + reg_out_09 : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); + reg_out_0A : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); + reg_out_0B : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); + reg_out_0C : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); + reg_out_0D : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); + reg_out_0E : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); + reg_out_0F : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); + + + + s00_axi_aclk : in std_logic; + s00_axi_aresetn : in std_logic; + s00_axi_awaddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0); + s00_axi_awprot : in std_logic_vector(2 downto 0); + s00_axi_awvalid : in std_logic; + s00_axi_awready : out std_logic; + s00_axi_wdata : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); + s00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0); + s00_axi_wvalid : in std_logic; + s00_axi_wready : out std_logic; + s00_axi_bresp : out std_logic_vector(1 downto 0); + s00_axi_bvalid : out std_logic; + s00_axi_bready : in std_logic; + s00_axi_araddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0); + s00_axi_arprot : in std_logic_vector(2 downto 0); + s00_axi_arvalid : in std_logic; + s00_axi_arready : out std_logic; + s00_axi_rdata : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); + s00_axi_rresp : out std_logic_vector(1 downto 0); + s00_axi_rvalid : out std_logic; + s00_axi_rready : in std_logic; + + s_axi_intr_aclk : in std_logic; + s_axi_intr_aresetn : in std_logic; + s_axi_intr_awaddr : in std_logic_vector(C_S_AXI_INTR_ADDR_WIDTH-1 downto 0); + s_axi_intr_awprot : in std_logic_vector(2 downto 0); + s_axi_intr_awvalid : in std_logic; + s_axi_intr_awready : out std_logic; + s_axi_intr_wdata : in std_logic_vector(C_S_AXI_INTR_DATA_WIDTH-1 downto 0); + s_axi_intr_wstrb : in std_logic_vector((C_S_AXI_INTR_DATA_WIDTH/8)-1 downto 0); + s_axi_intr_wvalid : in std_logic; + s_axi_intr_wready : out std_logic; + s_axi_intr_bresp : out std_logic_vector(1 downto 0); + s_axi_intr_bvalid : out std_logic; + s_axi_intr_bready : in std_logic; + s_axi_intr_araddr : in std_logic_vector(C_S_AXI_INTR_ADDR_WIDTH-1 downto 0); + s_axi_intr_arprot : in std_logic_vector(2 downto 0); + s_axi_intr_arvalid : in std_logic; + s_axi_intr_arready : out std_logic; + s_axi_intr_rdata : out std_logic_vector(C_S_AXI_INTR_DATA_WIDTH-1 downto 0); + s_axi_intr_rresp : out std_logic_vector(1 downto 0); + s_axi_intr_rvalid : out std_logic; + s_axi_intr_rready : in std_logic; + irq : out std_logic + ); +end a2x_axi_reg; + +architecture a2x_axi_reg of a2x_axi_reg is + + component a2x_axi_reg_S00 is + generic ( + C_S_AXI_DATA_WIDTH : integer := 32; + C_S_AXI_ADDR_WIDTH : integer := 6 + ); + port ( + reg_cmd_00 : in std_logic_vector(1 downto 0); + reg_cmd_01 : in std_logic_vector(1 downto 0); + reg_cmd_02 : in std_logic_vector(1 downto 0); + reg_cmd_03 : in std_logic_vector(1 downto 0); + reg_cmd_04 : in std_logic_vector(1 downto 0); + reg_cmd_05 : in std_logic_vector(1 downto 0); + reg_cmd_06 : in std_logic_vector(1 downto 0); + reg_cmd_07 : in std_logic_vector(1 downto 0); + reg_cmd_08 : in std_logic_vector(1 downto 0); + reg_cmd_09 : in std_logic_vector(1 downto 0); + reg_cmd_0A : in std_logic_vector(1 downto 0); + reg_cmd_0B : in std_logic_vector(1 downto 0); + reg_cmd_0C : in std_logic_vector(1 downto 0); + reg_cmd_0D : in std_logic_vector(1 downto 0); + reg_cmd_0E : in std_logic_vector(1 downto 0); + reg_cmd_0F : in std_logic_vector(1 downto 0); + reg_in_00 : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_in_01 : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_in_02 : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_in_03 : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_in_04 : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_in_05 : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_in_06 : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_in_07 : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_in_08 : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_in_09 : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_in_0A : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_in_0B : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_in_0C : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_in_0D : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_in_0E : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_in_0F : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_out_00 : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_out_01 : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_out_02 : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_out_03 : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_out_04 : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_out_05 : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_out_06 : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_out_07 : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_out_08 : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_out_09 : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_out_0A : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_out_0B : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_out_0C : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_out_0D : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_out_0E : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_out_0F : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + S_AXI_ACLK : in std_logic; + S_AXI_ARESETN : in std_logic; + S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + S_AXI_AWPROT : in std_logic_vector(2 downto 0); + S_AXI_AWVALID : in std_logic; + S_AXI_AWREADY : out std_logic; + S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); + S_AXI_WVALID : in std_logic; + S_AXI_WREADY : out std_logic; + S_AXI_BRESP : out std_logic_vector(1 downto 0); + S_AXI_BVALID : out std_logic; + S_AXI_BREADY : in std_logic; + S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + S_AXI_ARPROT : in std_logic_vector(2 downto 0); + S_AXI_ARVALID : in std_logic; + S_AXI_ARREADY : out std_logic; + S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + S_AXI_RRESP : out std_logic_vector(1 downto 0); + S_AXI_RVALID : out std_logic; + S_AXI_RREADY : in std_logic + ); + end component a2x_axi_reg_S00; + + component a2x_axi_intr is + generic ( + C_S_AXI_DATA_WIDTH : integer := 32; + C_S_AXI_ADDR_WIDTH : integer := 5; + C_NUM_OF_INTR : integer := 1; + C_INTR_SENSITIVITY : std_logic_vector := x"FFFFFFFF"; + C_INTR_ACTIVE_STATE : std_logic_vector := x"FFFFFFFF"; + C_IRQ_SENSITIVITY : integer := 1; + C_IRQ_ACTIVE_STATE : integer := 1 + ); + port ( + S_AXI_ACLK : in std_logic; + S_AXI_ARESETN : in std_logic; + S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + S_AXI_AWPROT : in std_logic_vector(2 downto 0); + S_AXI_AWVALID : in std_logic; + S_AXI_AWREADY : out std_logic; + S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); + S_AXI_WVALID : in std_logic; + S_AXI_WREADY : out std_logic; + S_AXI_BRESP : out std_logic_vector(1 downto 0); + S_AXI_BVALID : out std_logic; + S_AXI_BREADY : in std_logic; + S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + S_AXI_ARPROT : in std_logic_vector(2 downto 0); + S_AXI_ARVALID : in std_logic; + S_AXI_ARREADY : out std_logic; + S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + S_AXI_RRESP : out std_logic_vector(1 downto 0); + S_AXI_RVALID : out std_logic; + S_AXI_RREADY : in std_logic; + irq : out std_logic + ); + end component a2x_axi_intr; + +begin + +a2x_axi_reg_S00_inst : a2x_axi_reg_S00 + generic map ( + C_S_AXI_DATA_WIDTH => C_S00_AXI_DATA_WIDTH, + C_S_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH + ) + port map ( + reg_cmd_00 => reg_cmd_00, + reg_cmd_01 => reg_cmd_01, + reg_cmd_02 => reg_cmd_02, + reg_cmd_03 => reg_cmd_03, + reg_cmd_04 => reg_cmd_04, + reg_cmd_05 => reg_cmd_05, + reg_cmd_06 => reg_cmd_06, + reg_cmd_07 => reg_cmd_07, + reg_cmd_08 => reg_cmd_08, + reg_cmd_09 => reg_cmd_09, + reg_cmd_0A => reg_cmd_0A, + reg_cmd_0B => reg_cmd_0B, + reg_cmd_0C => reg_cmd_0C, + reg_cmd_0D => reg_cmd_0D, + reg_cmd_0E => reg_cmd_0E, + reg_cmd_0F => reg_cmd_0F, + reg_in_00 => reg_in_00, + reg_in_01 => reg_in_01, + reg_in_02 => reg_in_02, + reg_in_03 => reg_in_03, + reg_in_04 => reg_in_04, + reg_in_05 => reg_in_05, + reg_in_06 => reg_in_06, + reg_in_07 => reg_in_07, + reg_in_08 => reg_in_08, + reg_in_09 => reg_in_09, + reg_in_0A => reg_in_0A, + reg_in_0B => reg_in_0B, + reg_in_0C => reg_in_0C, + reg_in_0D => reg_in_0D, + reg_in_0E => reg_in_0E, + reg_in_0F => reg_in_0F, + reg_out_00 => reg_out_00, + reg_out_01 => reg_out_01, + reg_out_02 => reg_out_02, + reg_out_03 => reg_out_03, + reg_out_04 => reg_out_04, + reg_out_05 => reg_out_05, + reg_out_06 => reg_out_06, + reg_out_07 => reg_out_07, + reg_out_08 => reg_out_08, + reg_out_09 => reg_out_09, + reg_out_0A => reg_out_0A, + reg_out_0B => reg_out_0B, + reg_out_0C => reg_out_0C, + reg_out_0D => reg_out_0D, + reg_out_0E => reg_out_0E, + reg_out_0F => reg_out_0F, + S_AXI_ACLK => s00_axi_aclk, + S_AXI_ARESETN => s00_axi_aresetn, + S_AXI_AWADDR => s00_axi_awaddr, + S_AXI_AWPROT => s00_axi_awprot, + S_AXI_AWVALID => s00_axi_awvalid, + S_AXI_AWREADY => s00_axi_awready, + S_AXI_WDATA => s00_axi_wdata, + S_AXI_WSTRB => s00_axi_wstrb, + S_AXI_WVALID => s00_axi_wvalid, + S_AXI_WREADY => s00_axi_wready, + S_AXI_BRESP => s00_axi_bresp, + S_AXI_BVALID => s00_axi_bvalid, + S_AXI_BREADY => s00_axi_bready, + S_AXI_ARADDR => s00_axi_araddr, + S_AXI_ARPROT => s00_axi_arprot, + S_AXI_ARVALID => s00_axi_arvalid, + S_AXI_ARREADY => s00_axi_arready, + S_AXI_RDATA => s00_axi_rdata, + S_AXI_RRESP => s00_axi_rresp, + S_AXI_RVALID => s00_axi_rvalid, + S_AXI_RREADY => s00_axi_rready + ); + +a2x_axi_intr_inst : a2x_axi_intr + generic map ( + C_S_AXI_DATA_WIDTH => C_S_AXI_INTR_DATA_WIDTH, + C_S_AXI_ADDR_WIDTH => C_S_AXI_INTR_ADDR_WIDTH, + C_NUM_OF_INTR => C_NUM_OF_INTR, + C_INTR_SENSITIVITY => C_INTR_SENSITIVITY, + C_INTR_ACTIVE_STATE => C_INTR_ACTIVE_STATE, + C_IRQ_SENSITIVITY => C_IRQ_SENSITIVITY, + C_IRQ_ACTIVE_STATE => C_IRQ_ACTIVE_STATE + ) + port map ( + S_AXI_ACLK => s_axi_intr_aclk, + S_AXI_ARESETN => s_axi_intr_aresetn, + S_AXI_AWADDR => s_axi_intr_awaddr, + S_AXI_AWPROT => s_axi_intr_awprot, + S_AXI_AWVALID => s_axi_intr_awvalid, + S_AXI_AWREADY => s_axi_intr_awready, + S_AXI_WDATA => s_axi_intr_wdata, + S_AXI_WSTRB => s_axi_intr_wstrb, + S_AXI_WVALID => s_axi_intr_wvalid, + S_AXI_WREADY => s_axi_intr_wready, + S_AXI_BRESP => s_axi_intr_bresp, + S_AXI_BVALID => s_axi_intr_bvalid, + S_AXI_BREADY => s_axi_intr_bready, + S_AXI_ARADDR => s_axi_intr_araddr, + S_AXI_ARPROT => s_axi_intr_arprot, + S_AXI_ARVALID => s_axi_intr_arvalid, + S_AXI_ARREADY => s_axi_intr_arready, + S_AXI_RDATA => s_axi_intr_rdata, + S_AXI_RRESP => s_axi_intr_rresp, + S_AXI_RVALID => s_axi_intr_rvalid, + S_AXI_RREADY => s_axi_intr_rready, + irq => irq + ); + + + +end a2x_axi_reg; diff --git a/rel/src/vhdl/work/a2x_axi_reg_S00.vhdl b/rel/src/vhdl/work/a2x_axi_reg_S00.vhdl new file mode 100644 index 0000000..bec0a04 --- /dev/null +++ b/rel/src/vhdl/work/a2x_axi_reg_S00.vhdl @@ -0,0 +1,573 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity a2x_axi_reg_S00 is + generic ( + + + C_S_AXI_DATA_WIDTH : integer := 32; + C_S_AXI_ADDR_WIDTH : integer := 6 + ); + port ( + + reg_cmd_00 : in std_logic_vector(1 downto 0); + reg_cmd_01 : in std_logic_vector(1 downto 0); + reg_cmd_02 : in std_logic_vector(1 downto 0); + reg_cmd_03 : in std_logic_vector(1 downto 0); + reg_cmd_04 : in std_logic_vector(1 downto 0); + reg_cmd_05 : in std_logic_vector(1 downto 0); + reg_cmd_06 : in std_logic_vector(1 downto 0); + reg_cmd_07 : in std_logic_vector(1 downto 0); + reg_cmd_08 : in std_logic_vector(1 downto 0); + reg_cmd_09 : in std_logic_vector(1 downto 0); + reg_cmd_0A : in std_logic_vector(1 downto 0); + reg_cmd_0B : in std_logic_vector(1 downto 0); + reg_cmd_0C : in std_logic_vector(1 downto 0); + reg_cmd_0D : in std_logic_vector(1 downto 0); + reg_cmd_0E : in std_logic_vector(1 downto 0); + reg_cmd_0F : in std_logic_vector(1 downto 0); + reg_in_00 : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_in_01 : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_in_02 : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_in_03 : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_in_04 : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_in_05 : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_in_06 : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_in_07 : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_in_08 : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_in_09 : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_in_0A : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_in_0B : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_in_0C : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_in_0D : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_in_0E : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_in_0F : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_out_00 : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_out_01 : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_out_02 : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_out_03 : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_out_04 : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_out_05 : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_out_06 : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_out_07 : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_out_08 : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_out_09 : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_out_0A : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_out_0B : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_out_0C : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_out_0D : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_out_0E : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + reg_out_0F : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + + + S_AXI_ACLK : in std_logic; + S_AXI_ARESETN : in std_logic; + S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + S_AXI_AWPROT : in std_logic_vector(2 downto 0); + S_AXI_AWVALID : in std_logic; + S_AXI_AWREADY : out std_logic; + S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); + S_AXI_WVALID : in std_logic; + S_AXI_WREADY : out std_logic; + S_AXI_BRESP : out std_logic_vector(1 downto 0); + S_AXI_BVALID : out std_logic; + S_AXI_BREADY : in std_logic; + S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + S_AXI_ARPROT : in std_logic_vector(2 downto 0); + S_AXI_ARVALID : in std_logic; + S_AXI_ARREADY : out std_logic; + S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + S_AXI_RRESP : out std_logic_vector(1 downto 0); + S_AXI_RVALID : out std_logic; + S_AXI_RREADY : in std_logic + ); +end a2x_axi_reg_S00; + +architecture arch_imp of a2x_axi_reg_S00 is + + signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + signal axi_awready : std_logic; + signal axi_wready : std_logic; + signal axi_bresp : std_logic_vector(1 downto 0); + signal axi_bvalid : std_logic; + signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + signal axi_arready : std_logic; + signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal axi_rresp : std_logic_vector(1 downto 0); + signal axi_rvalid : std_logic; + + constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1; + constant OPT_MEM_ADDR_BITS : integer := 3; + signal slv_reg0, slv_reg0_d :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg1, slv_reg1_d :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg2, slv_reg2_d :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg3, slv_reg3_d :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg4, slv_reg4_d :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg5, slv_reg5_d :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg6, slv_reg6_d :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg7, slv_reg7_d :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg8, slv_reg8_d :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg9, slv_reg9_d :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg10, slv_reg10_d :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg11, slv_reg11_d :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg12, slv_reg12_d :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg13, slv_reg13_d :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg14, slv_reg14_d :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg15, slv_reg15_d :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg_rden : std_logic; + signal slv_reg_wren : std_logic; + signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal byte_index : integer; + signal aw_en : std_logic; + +begin + + S_AXI_AWREADY <= axi_awready; + S_AXI_WREADY <= axi_wready; + S_AXI_BRESP <= axi_bresp; + S_AXI_BVALID <= axi_bvalid; + S_AXI_ARREADY <= axi_arready; + S_AXI_RDATA <= axi_rdata; + S_AXI_RRESP <= axi_rresp; + S_AXI_RVALID <= axi_rvalid; + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_awready <= '0'; + aw_en <= '1'; + else + if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then + axi_awready <= '1'; + aw_en <= '0'; + elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then + aw_en <= '1'; + axi_awready <= '0'; + else + axi_awready <= '0'; + end if; + end if; + end if; + end process; + + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_awaddr <= (others => '0'); + else + if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then + axi_awaddr <= S_AXI_AWADDR; + end if; + end if; + end if; + end process; + + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_wready <= '0'; + else + if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1' and aw_en = '1') then + axi_wready <= '1'; + else + axi_wready <= '0'; + end if; + end if; + end if; + end process; + + slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ; + + process (S_AXI_ACLK) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + slv_reg0 <= (others => '0'); + slv_reg1 <= (others => '0'); + slv_reg2 <= (others => '0'); + slv_reg3 <= (others => '0'); + slv_reg4 <= (others => '0'); + slv_reg5 <= (others => '0'); + slv_reg6 <= (others => '0'); + slv_reg7 <= (others => '0'); + slv_reg8 <= (others => '0'); + slv_reg9 <= (others => '0'); + slv_reg10 <= (others => '0'); + slv_reg11 <= (others => '0'); + slv_reg12 <= (others => '0'); + slv_reg13 <= (others => '0'); + slv_reg14 <= (others => '0'); + slv_reg15 <= (others => '0'); + else + loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + if (slv_reg_wren = '1') then + case loc_addr is + when b"0000" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0001" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0010" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0011" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0100" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0101" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0110" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + slv_reg6(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0111" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + slv_reg7(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1000" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + slv_reg8(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1001" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + slv_reg9(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1010" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + slv_reg10(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1011" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + slv_reg11(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1100" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + slv_reg12(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1101" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + slv_reg13(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1110" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + slv_reg14(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1111" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + slv_reg15(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when others => + slv_reg0 <= slv_reg0_d; + slv_reg1 <= slv_reg1_d; + slv_reg2 <= slv_reg2_d; + slv_reg3 <= slv_reg3_d; + slv_reg4 <= slv_reg4_d; + slv_reg5 <= slv_reg5_d; + slv_reg6 <= slv_reg6_d; + slv_reg7 <= slv_reg7_d; + slv_reg8 <= slv_reg8_d; + slv_reg9 <= slv_reg9_d; + slv_reg10 <= slv_reg10_d; + slv_reg11 <= slv_reg11_d; + slv_reg12 <= slv_reg12_d; + slv_reg13 <= slv_reg13_d; + slv_reg14 <= slv_reg14_d; + slv_reg15 <= slv_reg15_d; + end case; + end if; + end if; + end if; + end process; + + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_bvalid <= '0'; + axi_bresp <= "00"; + else + if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then + axi_bvalid <= '1'; + axi_bresp <= "00"; + elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then + axi_bvalid <= '0'; + end if; + end if; + end if; + end process; + + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_arready <= '0'; + axi_araddr <= (others => '1'); + else + if (axi_arready = '0' and S_AXI_ARVALID = '1') then + axi_arready <= '1'; + axi_araddr <= S_AXI_ARADDR; + else + axi_arready <= '0'; + end if; + end if; + end if; + end process; + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_rvalid <= '0'; + axi_rresp <= "00"; + else + if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then + axi_rvalid <= '1'; + axi_rresp <= "00"; + elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then + axi_rvalid <= '0'; + end if; + end if; + end if; + end process; + + slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ; + + process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, axi_araddr, S_AXI_ARESETN, slv_reg_rden) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + case loc_addr is + when b"0000" => + reg_data_out <= slv_reg0; + when b"0001" => + reg_data_out <= slv_reg1; + when b"0010" => + reg_data_out <= slv_reg2; + when b"0011" => + reg_data_out <= slv_reg3; + when b"0100" => + reg_data_out <= slv_reg4; + when b"0101" => + reg_data_out <= slv_reg5; + when b"0110" => + reg_data_out <= slv_reg6; + when b"0111" => + reg_data_out <= slv_reg7; + when b"1000" => + reg_data_out <= slv_reg8; + when b"1001" => + reg_data_out <= slv_reg9; + when b"1010" => + reg_data_out <= slv_reg10; + when b"1011" => + reg_data_out <= slv_reg11; + when b"1100" => + reg_data_out <= slv_reg12; + when b"1101" => + reg_data_out <= slv_reg13; + when b"1110" => + reg_data_out <= slv_reg14; + when b"1111" => + case slv_reg15 is + when x"00000000" => reg_data_out <= x"02000048"; + when others => reg_data_out <= x"00000000"; + end case; + when others => + reg_data_out <= (others => '0'); + end case; + end process; + + process( S_AXI_ACLK ) is + begin + if (rising_edge (S_AXI_ACLK)) then + if ( S_AXI_ARESETN = '0' ) then + axi_rdata <= (others => '0'); + else + if (slv_reg_rden = '1') then + axi_rdata <= reg_data_out; + end if; + end if; + end if; + end process; + + + + with reg_cmd_00 select + slv_reg0_d <= slv_reg0 when "00", + slv_reg0 or reg_in_00 when "01", + slv_reg0 and not reg_in_00 when "10", + reg_in_00 when others; + + with reg_cmd_01 select + slv_reg1_d <= slv_reg1 when "00", + slv_reg1 or reg_in_01 when "01", + slv_reg1 and not reg_in_01 when "10", + reg_in_01 when others; + + with reg_cmd_02 select + slv_reg2_d <= slv_reg2 when "00", + slv_reg2 or reg_in_02 when "01", + slv_reg2 and not reg_in_02 when "10", + reg_in_02 when others; + + with reg_cmd_03 select + slv_reg3_d <= slv_reg3 when "00", + slv_reg3 or reg_in_03 when "01", + slv_reg3 and not reg_in_03 when "10", + reg_in_03 when others; + + with reg_cmd_04 select + slv_reg4_d <= slv_reg4 when "00", + slv_reg4 or reg_in_04 when "01", + slv_reg4 and not reg_in_04 when "10", + reg_in_04 when others; + + with reg_cmd_05 select + slv_reg5_d <= slv_reg5 when "00", + slv_reg5 or reg_in_05 when "01", + slv_reg5 and not reg_in_05 when "10", + reg_in_05 when others; + + with reg_cmd_06 select + slv_reg6_d <= slv_reg6 when "00", + slv_reg6 or reg_in_06 when "01", + slv_reg6 and not reg_in_06 when "10", + reg_in_06 when others; + + with reg_cmd_07 select + slv_reg7_d <= slv_reg7 when "00", + slv_reg7 or reg_in_07 when "01", + slv_reg7 and not reg_in_07 when "10", + reg_in_07 when others; + + with reg_cmd_08 select + slv_reg8_d <= slv_reg8 when "00", + slv_reg8 or reg_in_08 when "01", + slv_reg8 and not reg_in_08 when "10", + reg_in_08 when others; + + with reg_cmd_09 select + slv_reg9_d <= slv_reg9 when "00", + slv_reg9 or reg_in_09 when "01", + slv_reg9 and not reg_in_09 when "10", + reg_in_09 when others; + + with reg_cmd_0A select + slv_reg10_d <= slv_reg10 when "00", + slv_reg10 or reg_in_0A when "01", + slv_reg10 and not reg_in_0A when "10", + reg_in_0A when others; + + with reg_cmd_0B select + slv_reg11_d <= slv_reg11 when "00", + slv_reg11 or reg_in_0B when "01", + slv_reg11 and not reg_in_0B when "10", + reg_in_0B when others; + + with reg_cmd_0C select + slv_reg12_d <= slv_reg12 when "00", + slv_reg12 or reg_in_0C when "01", + slv_reg12 and not reg_in_0C when "10", + reg_in_0C when others; + + with reg_cmd_0D select + slv_reg13_d <= slv_reg13 when "00", + slv_reg13 or reg_in_0D when "01", + slv_reg13 and not reg_in_0D when "10", + reg_in_0D when others; + + with reg_cmd_0E select + slv_reg14_d <= slv_reg14 when "00", + slv_reg14 or reg_in_0E when "01", + slv_reg14 and not reg_in_0E when "10", + reg_in_0E when others; + + with reg_cmd_0F select + slv_reg15_d <= slv_reg15 when "00", + slv_reg15 or reg_in_0F when "01", + slv_reg15 and not reg_in_0F when "10", + reg_in_0F when others; + + + +end arch_imp; diff --git a/rel/src/vhdl/work/a2x_dbug.vhdl b/rel/src/vhdl/work/a2x_dbug.vhdl new file mode 100644 index 0000000..e3e036e --- /dev/null +++ b/rel/src/vhdl/work/a2x_dbug.vhdl @@ -0,0 +1,158 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- a2x dbug junk +-- +-- 1. passthru threadstop and modify with trig if enabled +-- 2. enable trigger ack +-- 3. counter for stuff +-- 4. scom +-- +-- others: debug stop + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.all; +use work.a2x_pkg.all; + +entity a2x_dbug is + port ( + clk : in std_logic; + reset_n : in std_logic; + + threadstop_in : in std_logic_vector(0 to 3); + + trigger_in : in std_logic; + trigger_threadstop : in std_logic_vector(0 to 3); + trigger_ack_enable : in std_logic; + + trigger_out : out std_logic; + trigger_ack_out : out std_logic; + threadstop_out : out std_logic_vector(0 to 3); + + req_valid : in std_logic; + req_id : in std_logic_vector(0 to 3); + req_addr : in std_logic_vector(0 to 5); + req_rw : in std_logic; + req_wr_data : in std_logic_vector(0 to 63); + + rsp_valid : out std_logic; + rsp_data : out std_logic_vector(0 to 63); + + dch_in : in std_logic; + cch_in : in std_logic; + dch_out : out std_logic; + cch_out : out std_logic; + + err : out std_logic + ); + +end a2x_dbug; + +architecture a2x_dbug of a2x_dbug is + +-- FFs +signal counter_d, counter_q : std_logic_vector(0 to 39); +signal trigger_ack_d, trigger_ack_q : std_logic; + +begin + +FF: process(clk) begin + +if rising_edge(clk) then + + if reset_n = '0' then + + counter_q <= (others => '0'); + trigger_ack_q <= '0'; + + else + + counter_q <= counter_d; + trigger_ack_q <= trigger_ack_d; + + end if; + +end if; + +end process FF; + + + +------------------------------------------------------------------------------------------------------------ +-- counter +------------------------------------------------------------------------------------------------------------ + +counter_d <= inc(counter_q); + +------------------------------------------------------------------------------------------------------------ +-- threadstop +------------------------------------------------------------------------------------------------------------ + +threadstop_out <= threadstop_in or gate_and(trigger_in, trigger_threadstop); + +------------------------------------------------------------------------------------------------------------ +-- ILA +------------------------------------------------------------------------------------------------------------ + +trigger_out <= trigger_in; + +-- acks until it goes away; or could do a pulse +trigger_ack_d <= trigger_ack_enable and trigger_in; +trigger_ack_out <= trigger_ack_q; + +------------------------------------------------------------------------------------------------------------ +-- SCOM +------------------------------------------------------------------------------------------------------------ + +scom: entity work.a2x_scom(a2x_scom) + port map ( + clk => clk, + reset_n => reset_n, + + req_valid => req_valid, + req_id => req_id, + req_addr => req_addr, + req_rw => req_rw, + req_wr_data => req_wr_data, + + rsp_valid => rsp_valid, + rsp_data => rsp_data, + + dch_in => dch_in, + cch_in => cch_in, + dch_out => dch_out, + cch_out => cch_out, + + err => err + ); + +end a2x_dbug; diff --git a/rel/src/vhdl/work/a2x_pkg.vhdl b/rel/src/vhdl/work/a2x_pkg.vhdl new file mode 100644 index 0000000..ba19240 --- /dev/null +++ b/rel/src/vhdl/work/a2x_pkg.vhdl @@ -0,0 +1,544 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +package a2x_pkg is + +attribute dont_touch : string; + +constant c_ld_queue_size : integer := 4; +constant c_ld_queue_bits : integer := 2; +constant c_st_queue_size : integer := 16; +constant c_st_queue_bits : integer := 4; +constant c_max_pointer : integer := 2; + +-- A2L2 ttypes +constant IFETCH : std_logic_vector(0 to 5) := "000000"; +constant IFETCHPRE : std_logic_vector(0 to 5) := "000001"; +constant LOAD : std_logic_vector(0 to 5) := "001000"; +constant STORE : std_logic_vector(0 to 5) := "100000"; + +constant LARX : std_logic_vector(0 to 5) := "001001"; +constant LARXHINT : std_logic_vector(0 to 5) := "001011"; +constant STCX : std_logic_vector(0 to 5) := "101011"; + +constant LWSYNC : std_logic_vector(0 to 5) := "101010"; +constant HWSYNC : std_logic_vector(0 to 5) := "101011"; +constant MBAR : std_logic_vector(0 to 5) := "110010"; +constant TLBSYNC : std_logic_vector(0 to 5) := "111010"; + +constant DCBI : std_logic_vector(0 to 5) := "111111"; + + +function or_reduce(slv: in std_logic_vector) return std_logic; +function and_reduce(slv: in std_logic_vector) return std_logic; +function inc(a: in std_logic_vector) return std_logic_vector; +function inc(a: in std_logic_vector; b: in integer) return std_logic_vector; +function dec(a: in std_logic_vector) return std_logic_vector; +function eq(a: in std_logic_vector; b: in integer) return boolean; +function eq(a: in std_logic_vector; b: in integer) return std_logic; +function eq(a: in std_logic_vector; b: in std_logic_vector) return boolean; +function eq(a: in std_logic_vector; b: in std_logic_vector) return std_logic; +function ne(a: in std_logic_vector; b: in integer) return boolean; +function ne(a: in std_logic_vector; b: in integer) return std_logic; +function ne(a: in std_logic_vector; b: in std_logic_vector) return boolean; +function ne(a: in std_logic_vector; b: in std_logic_vector) return std_logic; +function gt(a: in std_logic_vector; b: in integer) return boolean; +function gt(a: in std_logic_vector; b: in std_logic_vector) return boolean; +function gt(a: in std_logic_vector; b: in std_logic_vector) return std_logic; +function nz(a: in std_logic_vector) return boolean; +function nz(a: in std_logic_vector) return std_logic; +function b(a: in boolean) return std_logic; +function b(a: in std_logic) return boolean; + +function clog2(n : in integer) return integer; +function conv_integer(a: in std_logic_vector) return integer; +function max(a: in integer; b: in integer) return integer; + +function right_one(a: in std_logic_vector) return std_logic_vector; +function gate_and(a: in std_logic; b: in std_logic_vector) return std_logic_vector; +function rotl(a: in std_logic_vector; b: in integer) return std_logic_vector; +function rotl(a: in std_logic_vector; b: in std_logic_vector) return std_logic_vector; +function rotr(a: in std_logic_vector; b: in integer) return std_logic_vector; +function rotr(a: in std_logic_vector; b: in std_logic_vector) return std_logic_vector; +function enc(a: in std_logic_vector) return std_logic_vector; +function enc(a: in std_logic_vector; b: in integer) return std_logic_vector; + +subtype RADDR is std_logic_vector(64-42 to 63); +subtype LINEADDR is std_logic_vector(64-42 to 59); + +type A2L2REQUEST is record + valid : std_logic; + sent : std_logic; + data : std_logic; + dseq : std_logic_vector(0 to 2); + endian : std_logic; + tag : std_logic_vector(0 to 4); + len : std_logic_vector(0 to 2); + ra : RADDR; + thread : std_logic_vector(0 to 1); + spec : std_logic; + ditc : std_logic; + ttype : std_logic_vector(0 to 5); + user : std_logic_vector(0 to 3); + wimg : std_logic_vector(0 to 3); + hwsync : std_logic; +end record; + +type A2L2STOREDATA is record + data : std_logic_vector(0 to 127); + be : std_logic_vector(0 to 15); +end record; + +type A2L2RELOAD is record + coming : std_logic; + valid : std_logic; + tag : std_logic_vector(0 to 4); + data : std_logic_vector(0 to 127); + ee : std_logic; + ue : std_logic; + qw : std_logic_vector(57 to 59); + crit : std_logic; + dump : std_logic; +end record; + +type A2L2STATUS is record + ld_pop : std_logic; + st_pop : std_logic; + st_pop_thrd : std_logic_vector(0 to 2); + gather : std_logic; + res_valid : std_logic_vector(0 to 3); + stcx_complete : std_logic_vector(0 to 3); + stcx_pass : std_logic_vector(0 to 3); + sync_ack : std_logic_vector(0 to 3); +end record; + +type A2L2RESV is record + valid : std_logic; + ra : LINEADDR; +end record; + +type LOADQUEUE is array(0 to c_ld_queue_size-1) of A2L2REQUEST; +type LOADDATAQUEUE is array(0 to 63) of std_logic_vector(0 to 31); +type LOADQUEUEDEP is array(0 to c_ld_queue_size-1) of std_logic_vector(0 to c_st_queue_bits); -- 0: valid +type STOREQUEUE is array(0 to c_st_queue_size-1) of A2L2REQUEST; +type STOREDATAQUEUE is array(0 to c_st_queue_size-1) of A2L2STOREDATA; +type STOREQUEUEDEP is array(0 to c_st_queue_size-1) of std_logic_vector(0 to c_ld_queue_bits); -- 0: valid +type RESVARRAY is array(0 to 3) of A2L2RESV; + +function address_check(a: in A2L2REQUEST; b: in A2L2REQUEST) return std_logic; + +function mux_queue(a: in LOADQUEUE; b: in std_logic_vector) return A2L2REQUEST; +function mux_queue(a: in LOADDATAQUEUE; b: in integer) return std_logic_vector; +function mux_queue(a: in LOADDATAQUEUE; b: in std_logic_vector) return std_logic_vector; +function mux_queue(a: in LOADQUEUEDEP; b: in std_logic_vector) return std_logic_vector; +function mux_queue(a: in STOREQUEUE; b: in std_logic_vector) return A2L2REQUEST; +function mux_queue(a: in STOREDATAQUEUE; b: in std_logic_vector) return A2L2STOREDATA; +function mux_queue(a: in STOREQUEUEDEP; b: in std_logic_vector) return std_logic_vector; + +end a2x_pkg; + +package body a2x_pkg is + +---------------------------------------------------------------------- +-- Functions + +function or_reduce(slv: in std_logic_vector) return std_logic is + variable res: std_logic := '0'; +begin + for i in slv'range loop + res := res or slv(i); + end loop; + return res; +end function; + +function and_reduce(slv: in std_logic_vector) return std_logic is + variable res: std_logic := '1'; +begin + for i in slv'range loop + res := res and slv(i); + end loop; + return res; +end function; + +function inc(a: in std_logic_vector) return std_logic_vector is + variable res: std_logic_vector(0 to a'length-1); +begin + res := std_logic_vector(unsigned(a) + 1); + return res; +end function; + +function inc(a: in std_logic_vector; b: in integer) return std_logic_vector is + variable res: std_logic_vector(0 to a'length-1); +begin + res := std_logic_vector(unsigned(a) + b); + return res; +end function; + +function dec(a: in std_logic_vector) return std_logic_vector is + variable res: std_logic_vector(0 to a'length-1); +begin + res := std_logic_vector(unsigned(a) - 1); + return res; +end function; + +function eq(a: in std_logic_vector; b: in integer) return boolean is + variable res: boolean; +begin + res := unsigned(a) = b; + return res; +end function; + +function eq(a: in std_logic_vector; b: in integer) return std_logic is + variable res: std_logic; +begin + if unsigned(a) = b then + res := '1'; + else + res := '0'; + end if; + return res; +end function; + +function eq(a: in std_logic_vector; b: in std_logic_vector) return boolean is + variable res: boolean; +begin + res := unsigned(a) = unsigned(b); + return res; +end function; + +function eq(a: in std_logic_vector; b: in std_logic_vector) return std_logic is + variable res: std_logic; +begin + if unsigned(a) = unsigned(b) then + res := '1'; + else + res := '0'; + end if; + return res; +end function; + +function ne(a: in std_logic_vector; b: in integer) return boolean is + variable res: boolean; +begin + res := unsigned(a) /= b; + return res; +end function; + +function ne(a: in std_logic_vector; b: in integer) return std_logic is + variable res: std_logic; +begin + if unsigned(a) /= b then + res := '1'; + else + res := '0'; + end if; + return res; +end function; + +function ne(a: in std_logic_vector; b: in std_logic_vector) return boolean is + variable res: boolean; +begin + res := unsigned(a) /= unsigned(b); + return res; +end function; + +function ne(a: in std_logic_vector; b: in std_logic_vector) return std_logic is + variable res: std_logic; +begin + if unsigned(a) /= unsigned(b) then + res := '1'; + else + res := '0'; + end if; + return res; +end function; + +function gt(a: in std_logic_vector; b: in integer) return boolean is + variable res: boolean; +begin + res := unsigned(a) > b; + return res; +end function; + +function gt(a: in std_logic_vector; b: in std_logic_vector) return boolean is + variable res: boolean; +begin + res := unsigned(a) > unsigned(b); + return res; +end function; + +function gt(a: in std_logic_vector; b: in std_logic_vector) return std_logic is + variable res: std_logic; +begin + if unsigned(a) > unsigned(b) then + res := '1'; + else + res := '0'; + end if; + return res; +end function; + +function nz(a: in std_logic_vector) return boolean is + variable res: boolean; +begin + res := unsigned(a) /= 0; + return res; +end function; + +function nz(a: in std_logic_vector) return std_logic is + variable res: std_logic; +begin + if unsigned(a) /= 0 then + res := '1'; + else + res := '0'; + end if; + return res; +end function; + +function b(a: in boolean) return std_logic is + variable res: std_logic; +begin + if a then + res := '1'; + else + res := '0'; + end if; + return res; +end function; + +function b(a: in std_logic) return boolean is + variable res: boolean; +begin + if a = '1' then + res := true; + else + res := false; + end if; + return res; +end function; + +function right_one(a: in std_logic_vector) return std_logic_vector is + variable res : std_logic_vector(0 to a'length - 1); +begin + for i in a'length - 1 downto 0 loop + if a(i) = '1' then + res(i) := '1'; + exit; + end if; + end loop; + return res; +end function; + +function rotl(a: in std_logic_vector; b: in integer) return std_logic_vector is + variable res : std_logic_vector(0 to a'length - 1); +begin + res := a(b to a'length - 1) & a(0 to b - 1); + return res; +end function; + +function rotl(a: in std_logic_vector; b: in std_logic_vector) return std_logic_vector is + variable res : std_logic_vector(0 to a'length - 1) := a; + variable c : integer := conv_integer(b); + variable i : integer; +begin + for i in 0 to a'length - 1 loop + if (i + c < a'length) then + res(i) := a(i + c); + else + res(i) := a(i + c - a'length); + end if; + end loop; + return res; +end function; + +function rotr(a: in std_logic_vector; b: in integer) return std_logic_vector is + variable res: std_logic_vector(0 to a'length - 1); +begin + res := a(a'length - b to a'length - 1) & a(0 to a'length - b - 1); + return res; +end function; + +function rotr(a: in std_logic_vector; b: in std_logic_vector) return std_logic_vector is + variable res: std_logic_vector(0 to a'length - 1); + variable c : integer := conv_integer(b); +begin + for i in 0 to a'length - 1 loop + if (a'length - c + i < a'length) then + res(i) := a(a'length - c + i); + else + res(i) := a(-c + i); + end if; + end loop; + return res; +end function; + +function gate_and(a: in std_logic; b: in std_logic_vector) return std_logic_vector is + variable res: std_logic_vector(0 to b'length-1); +begin + if a = '1' then + res := b; + else + res := (others => '0'); + end if; + return res; +end function; + +function enc(a: in std_logic_vector) return std_logic_vector is + variable res: std_logic_vector(0 to clog2(a'length)-1) := (others => '0'); +begin + for i in 0 to a'length - 1 loop + if (a(i) = '1') then + res := std_logic_vector(to_unsigned(i, res'length)); + exit; + end if; + end loop; + return res; +end function; + +function enc(a: in std_logic_vector; b: in integer) return std_logic_vector is + variable res: std_logic_vector(0 to b-1) := (others => '0'); +begin + for i in 0 to a'length - 1 loop + if (a(i) = '1') then + res := std_logic_vector(to_unsigned(i, res'length)); + exit; + end if; + end loop; + return res; +end function; + +function conv_integer(a: in std_logic_vector) return integer is + variable res: integer; +begin + res := to_integer(unsigned(a)); + return res; +end function; + +function max(a: in integer; b: in integer) return integer is + variable res : integer; +begin + if (a > b) then + res := a; + else + res := b; + end if; + return res; +end function; + +function mux_queue(a: in LOADQUEUE; b: in std_logic_vector) return A2L2REQUEST is + variable res: A2L2REQUEST; +begin + res := a(conv_integer(b)); + return res; +end function; + +function mux_queue(a: in LOADDATAQUEUE; b: in std_logic_vector) return std_logic_vector is + variable res: std_logic_vector(0 to a(0)'length-1); +begin + res := a(conv_integer(b)); + return res; +end function; + +function mux_queue(a: in LOADDATAQUEUE; b: in integer) return std_logic_vector is + variable res: std_logic_vector(0 to a(0)'length-1); +begin + res := a(b); + return res; +end function; + +function mux_queue(a: in LOADQUEUEDEP; b: in std_logic_vector) return std_logic_vector is + variable res: std_logic_vector(0 to a(0)'length-1); +begin + res := a(conv_integer(b)); + return res; +end function; + + +function mux_queue(a: in STOREQUEUE; b: in std_logic_vector) return A2L2REQUEST is + variable res: A2L2REQUEST; +begin + res := a(conv_integer(b)); + return res; +end function; + +function mux_queue(a: in STOREDATAQUEUE; b: in std_logic_vector) return A2L2STOREDATA is + variable res: A2L2STOREDATA; +begin + res := a(conv_integer(b)); + return res; +end function; + +function mux_queue(a: in STOREQUEUEDEP; b: in std_logic_vector) return std_logic_vector is + variable res: std_logic_vector(0 to a(0)'length-1); +begin + res := a(conv_integer(b)); + return res; +end function; + +-- compare requests to determine if they overlap +function address_check(a: in A2L2REQUEST; b: in A2L2REQUEST) return std_logic is + variable res: std_logic := '0'; + variable a_start, a_end, b_start, b_end : unsigned(0 to a.ra'length-1); +begin + a_start := unsigned(a.ra); + a_end := unsigned(a.ra) + 64; + b_start := unsigned(b.ra); + b_end := unsigned(b.ra) + 64; + if ((a.valid = '1') and (a.spec = '0') and (b.valid = '1') and (b.spec = '0')) then + if ((a_start >= b_start) and (a_start <= b_end)) then + res := '1'; + elsif ((a_end >= b_start) and (a_end <= b_end)) then + res := '1'; + end if; + end if; + return res; +end function; + +function clog2(n : in integer) return integer is + variable i : integer; + variable j : integer := n - 1; + variable res : integer := 1; +begin + for i in 0 to 31 loop + if (j > 1) then + j := j / 2; + res := res + 1; + else + exit; + end if; + end loop; + return res; +end; + +end a2x_pkg; + diff --git a/rel/src/vhdl/work/a2x_reset.vhdl b/rel/src/vhdl/work/a2x_reset.vhdl new file mode 100644 index 0000000..93c6cd5 --- /dev/null +++ b/rel/src/vhdl/work/a2x_reset.vhdl @@ -0,0 +1,92 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee; +use ieee.std_logic_1164.ALL; +use ieee.numeric_std.all; + +-- both resets are negative-active! + +entity a2x_reset is + port ( + clk : in std_logic; + reset_in : in std_logic; + reset : out std_logic + ); +end a2x_reset; + +architecture a2x_reset of a2x_reset is + constant reset_period : integer := 32; + signal reset_in_q : std_logic := '0'; + signal reset_q : std_logic := '0'; + signal counter_q : std_logic_vector(0 to 31) := x"00000000"; + +function inc(a: in std_logic_vector) return std_logic_vector is + variable res: std_logic_vector(0 to a'length-1); +begin + res := std_logic_vector(unsigned(a) + 1); + return res; +end function; +function eq(a: in std_logic_vector; b: in integer) return boolean is + variable res: boolean; +begin + res := unsigned(a) = b; + return res; +end function; +function leq(a: in std_logic_vector; b: in integer) return boolean is + variable res: boolean; +begin + res := unsigned(a) <= b; + return res; +end function; + +begin + + FF: process (clk) begin + + if (rising_edge(clk)) then + + reset_in_q <= reset_in; + + if (reset_in_q = '1' and reset_in = '0') then -- edge-trigger hi->lo + counter_q <= (others => '0'); + elsif (leq(counter_q, reset_period)) then -- reset period + counter_q <= inc(counter_q); + reset_q <= '0'; + else -- normal + counter_q <= counter_q; + reset_q <= '1'; + end if; + + end if; + + end process; + + reset <= reset_q; + +end architecture a2x_reset; diff --git a/rel/src/vhdl/work/a2x_scom.vhdl b/rel/src/vhdl/work/a2x_scom.vhdl new file mode 100644 index 0000000..e5a9972 --- /dev/null +++ b/rel/src/vhdl/work/a2x_scom.vhdl @@ -0,0 +1,215 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- a2x par/ser scom master +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.all; +use work.a2x_pkg.all; + +entity a2x_scom is + port ( + clk : in std_logic; + reset_n : in std_logic; + + req_valid : in std_logic; + req_id : in std_logic_vector(0 to 3); + req_addr : in std_logic_vector(0 to 5); + req_rw : in std_logic; + req_wr_data : in std_logic_vector(0 to 63); + + rsp_valid : out std_logic; + rsp_data : out std_logic_vector(0 to 63); + + dch_in : in std_logic; + cch_in : in std_logic; + dch_out : out std_logic; + cch_out : out std_logic; + + err : out std_logic + ); +end a2x_scom; + +architecture a2x_scom of a2x_scom is + + +-- FFs + +signal scom_seq_d, scom_seq_q : std_logic_vector(0 to 3); + +signal req_v_d, req_v_q : std_logic; +signal req_sat_d, req_sat_q : std_logic_vector(0 to 3); +signal req_addr_d, req_addr_q : std_logic_vector(0 to 5); +signal req_rw_d, req_rw_q : std_logic; +signal req_wr_data_d, req_wr_data_q : std_logic_vector(0 to 63); + +signal rsp_v_d, rsp_v_q : std_logic; +signal rsp_data_d, rsp_data_q : std_logic; + +signal cch_in_d, cch_in_q : std_logic_vector(0 to 1); +signal cch_out_d, cch_out_q : std_logic; +signal dch_in_d, dch_in_q : std_logic; +signal dch_out_d, dch_out_q : std_logic; +signal scom_err_d, scom_err_q : std_logic; + +-- misc +signal cch_start : std_logic; +signal cch_end : std_logic; +signal scom_reset : std_logic; +signal scom_seq_err : std_logic; + +begin + + +FF: process(clk) begin + +if rising_edge(clk) then + + if reset_n = '0' then + + cch_in_q <= (others => '0'); + cch_out_q <= '0'; + dch_in_q <= '0'; + dch_out_q <= '0'; + scom_seq_q <= (others => '1'); + req_v_q <= '0'; + req_sat_q <= (others => '0'); + req_addr_q <= (others => '0'); + req_rw_q <= '0'; + req_wr_data_q <= (others => '0'); + rsp_v_q <= '0'; + scom_err_q <= '0'; + + else + + cch_in_q <= cch_in_d; + cch_out_q <= cch_out_d; + dch_in_q <= dch_in_d; + dch_out_q <= dch_out_d; + scom_seq_q <= scom_seq_d; + req_v_q <= req_v_d; + req_sat_q <= req_sat_d; + req_addr_q <= req_addr_d; + req_rw_q <= req_rw_d; + req_wr_data_q <= req_wr_data_d; + rsp_v_q <= rsp_v_q; + scom_err_q <= scom_err_d; + + end if; + +end if; + +end process FF; + + +------------------------------------------------------------------------------------------------------------ +-- SCOM +------------------------------------------------------------------------------------------------------------ + +-- request +req_v_d <= req_valid; +req_sat_d <= req_id; +req_addr_d <= req_addr; +req_rw_d <= (req_rw and req_valid) or (req_rw_q and not req_valid); +req_wr_data_d <= req_wr_data; + +-- send command; when header is received back, look for data/rsp + + + +--tbl ScomSeq +-- +--n scom_seq_q scom_seq +--n | scom_reset | load_serializer +--n | |req_v_q | |check_deserializer +--n | || header_sent | || scom_seq_err +--n | || |header_rcvd | || | +--n | || ||header_ok | || | +--n | || ||| req_read | || | +--n | || ||| |req_write_done | || | +--n | || ||| || | || | +--b 0123 || ||| || 0123 || | +--t iiii ii iii ii oooo oo o +--*------------------------------------------------------------------------------------------------------------------- +--* Idle ------------------------------------------------------------------------------------------------------------- +--s 1111 1- --- -- 1111 00 0 * +--s 1111 00 --- -- 1111 00 0 * +--s 1111 01 --- -- 0001 10 0 * +--* Start Send ------------------------------------------------------------------------------------------------------- +--s 0001 1- --- -- 1111 01 0 * +--s 0001 0- 0-- -- 0001 01 0 * +--s 0001 0- 1-- -- 0010 01 0 * +--* Receive Header---------------------------------------------------------------------------------------------------- +--s 0010 1- --- -- 1111 01 0 * +--s 0010 0- -0- -- 0010 01 0 * +--s 0010 0- -1- 1- 0011 01 0 * +--s 0010 0- -1- 00 1000 01 0 * +--* Receive Read Data ------------------------------------------------------------------------------------------------ +--s 0011 1- --- -- 1111 00 0 * +--* Send Write Data -------------------------------------------------------------------------------------------------- +--s 1000 1- --- -- 1111 00 0 * +--* Receive Write Response ------------------------------------------------------------------------------------------- +--s 1001 1- --- -- 1111 00 0 * +--* Error ------------------------------------------------------------------------------------------------------------ +--s 0000 -- --- -- 0000 00 1 * +--*------------------------------------------------------------------------------------------------------------------- +-- +--tbl ScomSeq + + +-- serial interfaces +-- +-- 0. receive parallel request +-- 1. load serializer, initiate send +-- 2. deserializer compares until command matched +-- 3. deserializer processes response +-- read data/ack +-- write ack +-- 4. return result to parallel out + + +cch_out_d <= cch_in; +cch_out <= cch_out_q; + +dch_out_d <= dch_in; +dch_out <= dch_out_q; + +err <= '0'; + + +------------------------------------------------------------------------------------------------------------ + + + + +end a2x_scom; diff --git a/rel/src/vhdl/work/acq_soft.vhdl b/rel/src/vhdl/work/acq_soft.vhdl new file mode 100644 index 0000000..b2e6614 --- /dev/null +++ b/rel/src/vhdl/work/acq_soft.vhdl @@ -0,0 +1,4674 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- *!**************************************************************** +-- *! FILENAME : acq_soft.vhdl +-- *! DESCRIPTION : ACQ top level entity/architecture +-- *! +-- *!**************************************************************** +-- +-- |------------------------------------------------------------16-------------| +-- | a2_simwrap.vhdl - verification ! | +-- | ! | +-- | |---------------------------------------------------------16----------! | +-- | | acq.vhdl (new version) ac_an_st_data bus ! | | +-- | | bytes ! | | +-- ! | | | | +-- | | |------------------------------------------------------16-------| | | +-- | | | ACQ_CORE.vhdl - acsii library ! | | | +-- | | | ! | | | +-- | | | ! | | | +-- | | | |---------------------------------------------------16----| | | | +-- | | | | acq_soft.vhdl (original acq.vhdl) ! | | | | +-- | | | | | | | | | +-- | | | | |------| |------| |------| |-------| |---32-| | | | | +-- | | | | | FU | | IU | | PU | | MMU | | XU | | | | | +-- | | | | |------| |------| |------| |-------| |------| | | | | +-- | | | | | | | | +-- | | | |---------------------------------------------------------| | | | +-- | | | | | | +-- | | |---------------------------------------------------------------| | | +-- | | | | +-- | |---------------------------------------------------------------------! | +-- | | +-- |---------------------------------------------------------------------------| +-- +-- Pass-thru signal name convention, UU is unit ID +-- signalName_oUU output ac_an_st_data_omm +-- signalName_iUU input ac_an_st_data_imm +-- +library ieee; use ieee.std_logic_1164.all; +library ibm; +library work; use work.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; +library support; + use support.power_logic_pkg.all; + use work.iuq_pkg.all; +library tri; + use tri.tri_latches_pkg.all; +use work.xuq_pkg.all; + +ENTITY acq_soft IS + GENERIC(xu_eff_ifar : integer := 62; + expand_type : integer := 2; + regmode : integer := 6; + hvmode : integer := 1; + a2mode : integer := 1; + bcfg_epn_0to15 : integer := 0; + bcfg_epn_16to31 : integer := 0; + bcfg_epn_32to47 : integer := (2**16)-1; + bcfg_epn_48to51 : integer := (2**4)-1; + bcfg_rpn_22to31 : integer := (2**10)-1; + bcfg_rpn_32to47 : integer := (2**16)-1; + bcfg_rpn_48to51 : integer := (2**4)-1; + fpr_addr_width : integer := 5; + lmq_entries : integer := 8; + threads : integer := 4; + ucode_mode : integer := 1; + uc_ifar : integer := 21; + data_out_width : integer := 64; + debug_event_width : integer := 16; + debug_trace_width : integer := 88; + epn_width : integer := 52; + eptr_width : integer := 4; + erat_ary_data_width : integer := 73; + erat_cam_data_width : integer := 75; + erat_rel_data_width : integer := 132; + error_width : integer := 3; + expand_tlb_type : integer := 2; + extclass_width : integer := 2; + inv_seq_width : integer := 6; + lpid_width : integer := 8; + lru_width : integer := 16; + mmucr0_width : integer := 20; + mmucr1_width : integer := 32; + mmucr2_width : integer := 32; + mmucr3_width : integer := 15; + pid_width : integer := 14; + pid_width_erat : integer := 8; + por_seq_width : integer := 3; + ra_entry_width : integer := 12; + real_addr_width : integer := 42; + req_epn_width : integer := 52; + rpn_width : integer := 30; + rs_data_width : integer := 64; + rs_is_width : integer := 9; + spr_addr_width : integer := 10; + spr_ctl_width : integer := 3; + spr_data_width : integer := 64; + spr_etid_width : integer := 2; + spr_xucr0_init_mod : integer := 0; + state_width : integer := 4; + thdid_width : integer := 4; + tlb_addr_width : natural := 7; + tlb_num_entry : natural := 512; + tlb_num_entry_log2 : natural := 9; + tlb_seq_width : integer := 6; + tlb_tag_width : natural := 110; + tlb_way_width : natural := 168; + tlb_ways : natural := 4; + tlb_word_width : natural := 84; + tlbsel_width : integer := 2; + ttype_width : integer := 4; + vpn_width : integer := 61; + watermark_width : integer := 4; + ws_width : integer := 2; + dc_size : natural := 14; -- 16K D$ --> 14 32K D$ --> 15 + include_boxes : integer := 1; + l_endian_m : integer := 1; + load_credits : integer := 4; + xu_real_data_add : integer := 42; + st_data_32b_mode : integer := 1; + ac_st_data_32b_mode : integer := 0; + store_credits : integer := 20 + ); + PORT ( + an_ac_back_inv : in std_ulogic; + an_ac_back_inv_addr : in std_ulogic_vector(64-xu_real_data_add to 63); + an_ac_back_inv_lbit : in std_ulogic; + an_ac_back_inv_gs : in std_ulogic; + an_ac_back_inv_ind : in std_ulogic; + an_ac_back_inv_local : in std_ulogic; + an_ac_back_inv_lpar_id : in std_ulogic_vector(0 to lpid_width-1); + an_ac_back_inv_target : in std_ulogic_vector(0 to 4); + an_ac_dcr_act : in std_ulogic; + an_ac_dcr_val : in std_ulogic; + an_ac_dcr_read : in std_ulogic; + an_ac_dcr_etid : in std_ulogic_vector(0 to 1); + an_ac_dcr_data : in std_ulogic_vector(64-(2**regmode) to 63); + an_ac_dcr_done : in std_ulogic; + an_ac_crit_interrupt : in std_ulogic_vector(0 to threads-1); + an_ac_ext_interrupt : in std_ulogic_vector(0 to threads-1); + an_ac_camfence_en_dc : in std_ulogic; + an_ac_flh2l2_gate : in std_ulogic; -- Gate L1 Hit forwarding SPR config bit + an_ac_icbi_ack : in std_ulogic; + an_ac_icbi_ack_thread : in std_ulogic_vector(0 to 1); + an_ac_reld_core_tag : in std_ulogic_vector(0 to 4); + an_ac_reld_data : in std_ulogic_vector(0 to 127); + an_ac_reld_data_vld : in std_ulogic; + an_ac_reld_ecc_err : in std_ulogic; + an_ac_reld_ecc_err_ue : in std_ulogic; + an_ac_reld_qw : in std_ulogic_vector(57 to 59); + an_ac_reld_data_coming : in std_ulogic; + an_ac_reld_ditc : in std_ulogic; + an_ac_reld_crit_qw : in std_ulogic; + an_ac_reld_l1_dump : in std_ulogic; + an_ac_req_ld_pop : in std_ulogic; + an_ac_req_spare_ctrl_a1 : in std_ulogic_vector(0 to 3); + an_ac_req_st_gather : in std_ulogic; + an_ac_req_st_pop : in std_ulogic; + an_ac_req_st_pop_thrd : in std_ulogic_vector(0 to 2); + an_ac_reservation_vld : in std_ulogic_vector(0 to threads-1); + an_ac_sleep_en : in std_ulogic_vector(0 to threads-1); + an_ac_stcx_complete : in std_ulogic_vector(0 to 3); + an_ac_stcx_pass : in std_ulogic_vector(0 to 3); + an_ac_sync_ack : in std_ulogic_vector(0 to 3); + a2_nclk : in clk_logic; + an_ac_abist_mode_dc : in std_ulogic; + an_ac_abist_start_test : in std_ulogic; + an_ac_abst_scan_in : in std_ulogic_vector(0 to 9); + an_ac_ary_nsl_thold_7 : in std_ulogic; + an_ac_atpg_en_dc : in std_ulogic; + an_ac_bcfg_scan_in : in std_ulogic_vector(0 to 4); + an_ac_lbist_ary_wrt_thru_dc : in std_ulogic; + an_ac_ccenable_dc : in std_ulogic; + an_ac_ccflush_dc : in std_ulogic; + an_ac_coreid : in std_ulogic_vector(0 to 7); + an_ac_reset_1_complete : in std_ulogic; + an_ac_reset_2_complete : in std_ulogic; + an_ac_reset_3_complete : in std_ulogic; + an_ac_reset_wd_complete : in std_ulogic; + an_ac_dcfg_scan_in : in std_ulogic_vector(0 to 2); + an_ac_debug_stop : in std_ulogic; + an_ac_external_mchk : in std_ulogic_vector(0 to 3); + an_ac_fce_7 : in std_ulogic; + an_ac_func_nsl_thold_7 : in std_ulogic; + an_ac_func_scan_in : in std_ulogic_vector(0 to 63); + an_ac_func_sl_thold_7 : in std_ulogic; + an_ac_gsd_test_enable_dc : in std_ulogic; + an_ac_gsd_test_acmode_dc : in std_ulogic; + an_ac_gptr_scan_in : in std_ulogic; + an_ac_hang_pulse : in std_ulogic_vector(0 to threads-1); + an_ac_lbist_en_dc : in std_ulogic; + an_ac_lbist_ac_mode_dc : in std_ulogic; + an_ac_lbist_ip_dc : in std_ulogic; + an_ac_malf_alert : in std_ulogic; + an_ac_perf_interrupt : in std_ulogic_vector(0 to threads-1); + an_ac_pm_thread_stop : in std_ulogic_vector(0 to 3); + an_ac_psro_enable_dc : in std_ulogic_vector(0 to 2); + an_ac_regf_scan_in : in std_ulogic_vector(0 to 11); + an_ac_repr_scan_in : in std_ulogic; + an_ac_rtim_sl_thold_7 : in std_ulogic; + an_ac_scan_diag_dc : in std_ulogic; + an_ac_scan_dis_dc_b : in std_ulogic; + an_ac_scan_type_dc : in std_ulogic_vector(0 to 8); + an_ac_scom_cch : in std_ulogic; + an_ac_scom_dch : in std_ulogic; + an_ac_scom_sat_id : in std_ulogic_vector(0 to 3); + an_ac_sg_7 : in std_ulogic; + an_ac_checkstop : in std_ulogic; + an_ac_tb_update_enable : in std_ulogic; + an_ac_tb_update_pulse : in std_ulogic; + an_ac_time_scan_in : in std_ulogic; + ac_an_back_inv_reject : out std_ulogic; + ac_an_box_empty : out std_ulogic_vector(0 to 3); + ac_an_reld_ditc_pop : out std_ulogic_vector(0 to 3); -- return credit from inbox (per thread) + ac_an_lpar_id : out std_ulogic_vector(0 to lpid_width-1); + ac_an_machine_check : out std_ulogic_vector(0 to threads-1); + ac_an_power_managed : out std_ulogic; + ac_an_req : out std_ulogic; + ac_an_req_endian : out std_ulogic; + ac_an_req_ld_core_tag : out std_ulogic_vector(0 to 4); + ac_an_req_ld_xfr_len : out std_ulogic_vector(0 to 2); + ac_an_req_pwr_token : out std_ulogic; + ac_an_req_ra : out std_ulogic_vector(64-xu_real_data_add to 63); + ac_an_req_spare_ctrl_a0 : out std_ulogic_vector(0 to 3); + ac_an_req_thread : out std_ulogic_vector(0 to 2); + ac_an_req_ttype : out std_ulogic_vector(0 to 5); + ac_an_req_user_defined : out std_ulogic_vector(0 to 3); + ac_an_req_wimg_g : out std_ulogic; + ac_an_req_wimg_i : out std_ulogic; + ac_an_req_wimg_m : out std_ulogic; + ac_an_req_wimg_w : out std_ulogic; + ac_an_rvwinkle_mode : out std_ulogic; + ac_an_st_byte_enbl : out std_ulogic_vector(0 to 15+(st_data_32b_mode*16)); + ac_an_st_data : out std_ulogic_vector(0 to 127+(st_data_32b_mode*128)); + ac_an_st_data_pwr_token : out std_ulogic; + ac_an_fu_bypass_events : out std_ulogic_vector(0 to 7); + ac_an_iu_bypass_events : out std_ulogic_vector(0 to 7); + ac_an_mm_bypass_events : out std_ulogic_vector(0 to 7); + ac_an_lsu_bypass_events : out std_ulogic_vector(0 to 7); + ac_an_debug_bus : out std_ulogic_vector(0 to 87); + ac_an_event_bus : out std_ulogic_vector(0 to 7); + ac_an_trace_triggers : out std_ulogic_vector(0 to 11); + ac_an_abist_done_dc : out std_ulogic; + ac_an_abst_scan_out : out std_ulogic_vector(0 to 9); + ac_an_bcfg_scan_out : out std_ulogic_vector(0 to 4); + ac_an_dcfg_scan_out : out std_ulogic_vector(0 to 2); + ac_an_debug_trigger : out std_ulogic_vector(0 to threads-1); + ac_an_func_scan_out : out std_ulogic_vector(0 to 63); + ac_an_gptr_scan_out : out std_ulogic; + ac_an_pm_thread_running : out std_ulogic_vector(0 to 3); + ac_an_psro_ringsig : out std_ulogic; + ac_an_recov_err : out std_ulogic_vector(0 to 2); + ac_an_regf_scan_out : out std_ulogic_vector(0 to 11); + ac_an_repr_scan_out : out std_ulogic; + ac_an_reset_1_request : out std_ulogic; + ac_an_reset_2_request : out std_ulogic; + ac_an_reset_3_request : out std_ulogic; + ac_an_reset_wd_request : out std_ulogic; + ac_an_scom_cch : out std_ulogic; + ac_an_scom_dch : out std_ulogic; + ac_an_time_scan_out : out std_ulogic; + ac_an_special_attn : out std_ulogic_vector(0 to 3); + ac_an_checkstop : out std_ulogic_vector(0 to 2); + ac_an_local_checkstop : out std_ulogic_vector(0 to 2); + ac_an_trace_error : out std_ulogic; + ac_an_dcr_act : out std_ulogic; + ac_an_dcr_val : out std_ulogic; + ac_an_dcr_read : out std_ulogic; + ac_an_dcr_user : out std_ulogic; + ac_an_dcr_etid : out std_ulogic_vector(0 to 1); + ac_an_dcr_addr : out std_ulogic_vector(11 to 20); + ac_an_dcr_data : out std_ulogic_vector(64-(2**regmode) to 63); + gnd : inout power_logic; + vcs : inout power_logic; + vdd : inout power_logic + ); + -- synopsys translate_off + -- synopsys translate_on +END acq_soft; + +ARCHITECTURE acq_soft OF acq_soft IS + + +signal a2_nclk_copy : clk_logic; +signal bx_pc_err_inbox_ue : std_ulogic; +signal bx_pc_err_outbox_ue : std_ulogic; +signal fu_iu_uc_special : std_ulogic_vector(0 to 3); +signal fu_pc_err_regfile_parity : std_ulogic_vector(0 to 3); +signal fu_pc_err_regfile_ue : std_ulogic_vector(0 to 3); +signal fu_pc_event_data : std_ulogic_vector(0 to 7); +signal fu_pc_ram_data : std_ulogic_vector(0 to 63); +signal fu_pc_ram_done : std_ulogic; +signal fu_xu_ex2_async_block : std_ulogic_vector(0 to 3); +signal fu_xu_ex1_ifar : std_ulogic_vector(62-xu_eff_ifar to 61); +signal fu_xu_ex2_ifar_val : std_ulogic_vector(0 to 3); +signal fu_xu_ex2_ifar_issued : std_ulogic_vector(0 to 3); +signal fu_xu_ex2_store_data : std_ulogic_vector(0 to 63); +signal fu_xu_ex2_store_data_val : std_ulogic; +signal fu_xu_ex3_ap_int_req : std_ulogic_vector(0 to 3); +signal fu_xu_ex3_flush2ucode : std_ulogic_vector(0 to 3); +signal fu_xu_ex2_instr_match : std_ulogic_vector(0 to 3); +signal fu_xu_ex2_instr_type : std_ulogic_vector(0 to 11); +signal fu_xu_ex2_is_ucode : std_ulogic_vector(0 to 3); +signal fu_xu_ex3_n_flush : std_ulogic_vector(0 to 3); +signal fu_xu_ex3_np1_flush : std_ulogic_vector(0 to 3); +signal fu_xu_ex3_regfile_err_det : std_ulogic_vector(0 to 3); +signal fu_xu_ex3_trap : std_ulogic_vector(0 to 3); +signal fu_xu_ex4_cr : std_ulogic_vector(0 to 3); +signal fu_xu_ex4_cr_bf : std_ulogic_vector(0 to 2); +signal fu_xu_ex4_cr_noflush : std_ulogic_vector(0 to 3); +signal fu_xu_ex4_cr_val : std_ulogic_vector(0 to 3); +signal fu_xu_regfile_seq_end : std_ulogic; +signal fu_xu_rf1_act : std_ulogic_vector(0 to 3); +signal fu_bx_slowspr_addr : std_ulogic_vector(0 to 9); +signal fu_bx_slowspr_data : std_ulogic_vector(64-(2**regmode) to 63); +signal fu_bx_slowspr_done : std_ulogic; +signal fu_bx_slowspr_etid : std_ulogic_vector(0 to 1); +signal fu_bx_slowspr_rw : std_ulogic; +signal fu_bx_slowspr_val : std_ulogic; +signal bx_xu_slowspr_addr : std_ulogic_vector(0 to 9); +signal bx_xu_slowspr_data : std_ulogic_vector(64-(2**regmode) to 63); +signal bx_xu_slowspr_done : std_ulogic; +signal bx_xu_slowspr_etid : std_ulogic_vector(0 to 1); +signal bx_xu_slowspr_rw : std_ulogic; +signal bx_xu_slowspr_val : std_ulogic; +signal bx_xu_quiesce : std_ulogic_vector(0 to 3); +signal iu_fu_ex2_n_flush : std_ulogic_vector(0 to 3); +signal iu_fu_is2_tid_decode : std_ulogic_vector(0 to 3); +signal iu_fu_rf0_bypsel : std_ulogic_vector(0 to 5); +signal iu_fu_rf0_fra : std_ulogic_vector(0 to 6); +signal iu_fu_rf0_fra_v : std_ulogic; +signal iu_fu_rf0_frb : std_ulogic_vector(0 to 6); +signal iu_fu_rf0_frb_v : std_ulogic; +signal iu_fu_rf0_frc : std_ulogic_vector(0 to 6); +signal iu_fu_rf0_frc_v : std_ulogic; +signal iu_fu_rf0_frt : std_ulogic_vector(0 to 6); +signal iu_fu_rf0_ifar : eff_ifar; +signal iu_fu_rf0_instr : std_ulogic_vector(0 to 31); +signal iu_fu_rf0_instr_match : std_ulogic; +signal iu_fu_rf0_instr_v : std_ulogic; +signal iu_fu_rf0_is_ucode : std_ulogic; +signal iu_fu_rf0_ucfmul : std_ulogic; +signal iu_fu_rf0_ldst_val : std_ulogic; +signal iu_fu_rf0_ldst_tid : std_ulogic_vector(0 to 1); +signal iu_fu_rf0_ldst_tag : std_ulogic_vector(0 to 8); +signal iu_fu_rf0_str_val : std_ulogic; +signal iu_fu_rf0_tid : std_ulogic_vector(0 to 1); +signal iu_mm_ierat_epn : std_ulogic_vector(0 to 51); +signal iu_mm_ierat_flush : std_ulogic_vector(0 to 3); +signal iu_mm_ierat_mmucr0 : std_ulogic_vector(0 to 17); +signal iu_mm_ierat_mmucr0_we : std_ulogic_vector(0 to 3); +signal iu_mm_ierat_mmucr1 : std_ulogic_vector(0 to 3); +signal iu_mm_ierat_mmucr1_we : std_ulogic; +signal iu_mm_ierat_req : std_ulogic; +signal iu_mm_ierat_snoop_ack : std_ulogic; +signal iu_mm_ierat_thdid : std_ulogic_vector(0 to 3); +signal iu_mm_ierat_tid : std_ulogic_vector(0 to 13); +signal iu_mm_ierat_state : std_ulogic_vector(0 to 3); +signal iu_mm_lmq_empty : std_ulogic; +signal iu_pc_err_icache_parity : std_ulogic; +signal iu_pc_err_icachedir_multihit : std_ulogic; +signal iu_pc_err_icachedir_parity : std_ulogic; +signal iu_pc_err_ucode_illegal : std_ulogic_vector(0 to 3); +signal iu_pc_event_data : std_ulogic_vector(0 to 7); +signal iu_pc_slowspr_addr : std_ulogic_vector(0 to 9); +signal iu_pc_slowspr_data : std_ulogic_vector(64-(2**regmode) to 63); +signal iu_pc_slowspr_done : std_ulogic; +signal iu_pc_slowspr_etid : std_ulogic_vector(0 to 1); +signal iu_pc_slowspr_rw : std_ulogic; +signal iu_pc_slowspr_val : std_ulogic; +signal iu_xu_ex4_tlb_data : std_ulogic_vector(64-(2**regmode) to 63); +signal iu_xu_ierat_ex2_flush_req : std_ulogic_vector(0 to threads-1); +signal iu_xu_ierat_ex3_par_err : std_ulogic_vector(0 to threads-1); +signal iu_xu_ierat_ex4_par_err : std_ulogic_vector(0 to threads-1); +signal iu_xu_is2_axu_instr_type : std_ulogic_vector(0 to 2); +signal iu_xu_is2_axu_ld_or_st : std_ulogic; +signal iu_xu_is2_axu_ldst_extpid : std_ulogic; +signal iu_xu_is2_axu_ldst_forcealign : std_ulogic; +signal iu_xu_is2_axu_ldst_forceexcept : std_ulogic; +signal iu_xu_is2_axu_ldst_indexed : std_ulogic; +signal iu_xu_is2_axu_ldst_size : std_ulogic_vector(0 to 5); +signal iu_xu_is2_axu_ldst_tag : std_ulogic_vector(0 to 8); +signal iu_xu_is2_axu_ldst_update : std_ulogic; +signal iu_xu_is2_axu_mffgpr : std_ulogic; +signal iu_xu_is2_axu_mftgpr : std_ulogic; +signal iu_xu_is2_axu_movedp : std_ulogic; +signal iu_xu_is2_axu_store : std_ulogic; +signal iu_xu_is2_error : std_ulogic_vector(0 to 2); +signal iu_xu_is2_gshare : std_ulogic_vector(0 to 3); +signal iu_xu_is2_ifar : eff_ifar; +signal iu_xu_is2_instr : std_ulogic_vector(0 to 31); +signal iu_xu_is2_is_ucode : std_ulogic; +signal iu_xu_is2_match : std_ulogic; +signal iu_xu_is2_pred_taken_cnt : std_ulogic_vector(0 to 1); +signal iu_xu_is2_pred_update : std_ulogic; +signal iu_xu_is2_s1 : std_ulogic_vector(0 to 5); +signal iu_xu_is2_s1_vld : std_ulogic; +signal iu_xu_is2_s2 : std_ulogic_vector(0 to 5); +signal iu_xu_is2_s2_vld : std_ulogic; +signal iu_xu_is2_s3 : std_ulogic_vector(0 to 5); +signal iu_xu_is2_s3_vld : std_ulogic; +signal iu_xu_is2_ta : std_ulogic_vector(0 to 5); +signal iu_xu_is2_ta_vld : std_ulogic; +signal iu_xu_is2_tid : std_ulogic_vector(0 to 3); +signal iu_xu_is2_ucode_vld : std_ulogic; +signal iu_xu_is2_vld : std_ulogic; +signal iu_xu_quiesce : std_ulogic_vector(0 to threads-1); +signal iu_xu_ra : std_ulogic_vector(real_ifar'left to 59); +signal iu_xu_request : std_ulogic; +signal iu_xu_thread : std_ulogic_vector(0 to 3); +signal iu_xu_userdef : std_ulogic_vector(0 to 3); +signal iu_xu_wimge : std_ulogic_vector(0 to 4); +signal mm_iu_ierat_mmucr0_0 : std_ulogic_vector(0 to 19); +signal mm_iu_ierat_mmucr0_1 : std_ulogic_vector(0 to 19); +signal mm_iu_ierat_mmucr0_2 : std_ulogic_vector(0 to 19); +signal mm_iu_ierat_mmucr0_3 : std_ulogic_vector(0 to 19); +signal mm_iu_ierat_mmucr1 : std_ulogic_vector(0 to 8); +signal mm_iu_ierat_pid0 : std_ulogic_vector(0 to 13); +signal mm_iu_ierat_pid1 : std_ulogic_vector(0 to 13); +signal mm_iu_ierat_pid2 : std_ulogic_vector(0 to 13); +signal mm_iu_ierat_pid3 : std_ulogic_vector(0 to 13); +signal mm_iu_ierat_rel_data : std_ulogic_vector(0 to 131); +signal mm_iu_ierat_rel_val : std_ulogic_vector(0 to 4); +signal mm_iu_ierat_snoop_attr : std_ulogic_vector(0 to 25); +signal mm_iu_ierat_snoop_coming : std_ulogic; +signal mm_iu_ierat_snoop_val : std_ulogic; +signal mm_iu_ierat_snoop_vpn : std_ulogic_vector(52-epn_width to 51); +signal mm_iu_slowspr_addr : std_ulogic_vector(0 to 9); +signal mm_iu_slowspr_data : std_ulogic_vector(64-spr_data_width to 63); +signal mm_iu_slowspr_done : std_ulogic; +signal mm_iu_slowspr_etid : std_ulogic_vector(0 to 1); +signal mm_iu_slowspr_rw : std_ulogic; +signal mm_iu_slowspr_val : std_ulogic; +signal xu_pc_err_mcsr_summary : std_ulogic_vector(0 to threads-1); +signal xu_pc_err_ierat_parity : std_ulogic; +signal xu_pc_err_derat_parity : std_ulogic; +signal xu_pc_err_tlb_parity : std_ulogic; +signal xu_pc_err_tlb_lru_parity : std_ulogic; +signal xu_pc_err_ierat_multihit : std_ulogic; +signal xu_pc_err_derat_multihit : std_ulogic; +signal xu_pc_err_tlb_multihit : std_ulogic; +signal xu_pc_err_ext_mchk : std_ulogic; +signal xu_pc_err_local_snoop_reject : std_ulogic; +signal mm_xu_derat_mmucr0_0 : std_ulogic_vector(0 to 19); +signal mm_xu_derat_mmucr0_1 : std_ulogic_vector(0 to 19); +signal mm_xu_derat_mmucr0_2 : std_ulogic_vector(0 to 19); +signal mm_xu_derat_mmucr0_3 : std_ulogic_vector(0 to 19); +signal mm_xu_derat_mmucr1 : std_ulogic_vector(0 to 9); +signal mm_xu_derat_pid0 : std_ulogic_vector(0 to 13); +signal mm_xu_derat_pid1 : std_ulogic_vector(0 to 13); +signal mm_xu_derat_pid2 : std_ulogic_vector(0 to 13); +signal mm_xu_derat_pid3 : std_ulogic_vector(0 to 13); +signal mm_xu_derat_rel_data : std_ulogic_vector(0 to 131); +signal mm_xu_derat_rel_val : std_ulogic_vector(0 to 4); +signal mm_xu_derat_snoop_attr : std_ulogic_vector(0 to 25); +signal mm_xu_derat_snoop_coming : std_ulogic; +signal mm_xu_derat_snoop_val : std_ulogic; +signal mm_xu_derat_snoop_vpn : std_ulogic_vector(52-epn_width to 51); +signal mm_iu_barrier_done : std_ulogic_vector(0 to 3); +signal mm_xu_eratmiss_done : std_ulogic_vector(0 to 3); +signal mm_xu_esr_pt : std_ulogic_vector(0 to 3); +signal mm_xu_esr_data : std_ulogic_vector(0 to 3); +signal mm_xu_esr_epid : std_ulogic_vector(0 to 3); +signal mm_xu_esr_st : std_ulogic_vector(0 to 3); +signal mm_xu_ex3_flush_req : std_ulogic_vector(0 to 3); +signal xu_mm_rf1_is_tlbsxr : std_ulogic; +signal mm_xu_hold_done : std_ulogic_vector(0 to 3); +signal mm_xu_hold_req : std_ulogic_vector(0 to 3); +signal mm_xu_hv_priv : std_ulogic_vector(0 to threads-1); +signal mm_xu_illeg_instr : std_ulogic_vector(0 to threads-1); +signal mm_xu_lru_par_err : std_ulogic_vector(0 to 3); +signal mm_xu_lrat_miss : std_ulogic_vector(0 to 3); +signal mm_xu_local_snoop_reject : std_ulogic_vector(0 to thdid_width-1); +signal mm_xu_lsu_addr : std_ulogic_vector(64-real_addr_width to 63); +signal mm_xu_lsu_lpid : std_ulogic_vector(0 to 7); +signal mm_xu_lsu_lpidr : std_ulogic_vector(0 to 7); +signal mm_xu_lsu_gs : std_ulogic; +signal mm_xu_lsu_ind : std_ulogic; +signal mm_xu_lsu_lbit : std_ulogic; +signal mm_xu_lsu_req : std_ulogic_vector(0 to 3); +signal mm_xu_lsu_ttype : std_ulogic_vector(0 to 1); +signal mm_xu_lsu_u : std_ulogic_vector(0 to 3); +signal mm_xu_lsu_wimge : std_ulogic_vector(0 to 4); +signal mm_xu_pt_fault : std_ulogic_vector(0 to 3); +signal mm_xu_quiesce : std_ulogic_vector(0 to threads-1); +signal mm_xu_tlb_inelig : std_ulogic_vector(0 to 3); +signal mm_xu_tlb_miss : std_ulogic_vector(0 to 3); +signal mm_xu_tlb_multihit_err : std_ulogic_vector(0 to 3); +signal mm_xu_tlb_par_err : std_ulogic_vector(0 to 3); +signal mm_xu_cr0_eq : std_ulogic_vector(0 to 3); +signal mm_xu_cr0_eq_valid : std_ulogic_vector(0 to 3); +signal pc_bx_inj_inbox_ecc : std_ulogic; +signal pc_bx_inj_outbox_ecc : std_ulogic; +signal pc_fu_abst_sl_thold_3 : std_ulogic; +signal pc_fu_abst_slp_sl_thold_3 : std_ulogic; +signal pc_fu_ary_nsl_thold_3 : std_ulogic; +signal pc_fu_ary_slp_nsl_thold_3 : std_ulogic; +signal pc_fu_cfg_sl_thold_3 : std_ulogic; +signal pc_fu_cfg_slp_sl_thold_3 : std_ulogic; +signal pc_bx_debug_mux1_ctrls : std_ulogic_vector(0 to 15); +signal pc_fu_debug_mux1_ctrls : std_ulogic_vector(0 to 15); +signal pc_fu_fce_3 : std_ulogic; +signal pc_fu_func_nsl_thold_3 : std_ulogic; +signal pc_fu_func_sl_thold_3 : std_ulogic_vector(0 to 1); +signal pc_fu_func_slp_nsl_thold_3 : std_ulogic; +signal pc_fu_func_slp_sl_thold_3 : std_ulogic_vector(0 to 1); +signal pc_fu_gptr_sl_thold_3 : std_ulogic; +signal pc_fu_ram_mode : std_ulogic; +signal pc_fu_ram_thread : std_ulogic_vector(0 to 1); +signal pc_fu_repr_sl_thold_3 : std_ulogic; +signal pc_fu_sg_3 : std_ulogic_vector(0 to 1); +signal pc_fu_slowspr_addr : std_ulogic_vector(0 to 9); +signal pc_fu_slowspr_data : std_ulogic_vector(64-(2**regmode) to 63); +signal pc_fu_slowspr_done : std_ulogic; +signal pc_fu_slowspr_etid : std_ulogic_vector(0 to 1); +signal pc_fu_slowspr_rw : std_ulogic; +signal pc_fu_slowspr_val : std_ulogic; +signal pc_bx_trace_bus_enable : std_ulogic; +signal pc_fu_time_sl_thold_3 : std_ulogic; +signal pc_fu_trace_bus_enable : std_ulogic; +signal pc_iu_gptr_sl_thold_4 : std_ulogic; +signal pc_iu_time_sl_thold_4 : std_ulogic; +signal pc_iu_repr_sl_thold_4 : std_ulogic; +signal pc_iu_abst_sl_thold_4 : std_ulogic; +signal pc_iu_abst_slp_sl_thold_4 : std_ulogic; +signal pc_iu_bolt_sl_thold_4 : std_ulogic; +signal pc_iu_regf_slp_sl_thold_4 : std_ulogic; +signal pc_iu_func_sl_thold_4 : std_ulogic; +signal pc_iu_func_slp_sl_thold_4 : std_ulogic; +signal pc_iu_cfg_sl_thold_4 : std_ulogic; +signal pc_iu_cfg_slp_sl_thold_4 : std_ulogic; +signal pc_iu_func_nsl_thold_4 : std_ulogic; +signal pc_iu_func_slp_nsl_thold_4 : std_ulogic; +signal pc_iu_ary_nsl_thold_4 : std_ulogic; +signal pc_iu_ary_slp_nsl_thold_4 : std_ulogic; +signal pc_iu_sg_4 : std_ulogic; +signal pc_iu_fce_4 : std_ulogic; +signal pc_iu_debug_mux1_ctrls : std_ulogic_vector(0 to 15); +signal pc_iu_debug_mux2_ctrls : std_ulogic_vector(0 to 15); +signal pc_iu_init_reset : std_ulogic; +signal pc_iu_inj_icache_parity : std_ulogic; +signal pc_iu_inj_icachedir_parity : std_ulogic; +signal pc_iu_inj_icachedir_multihit : std_ulogic; +signal pc_iu_ram_force_cmplt : std_ulogic; +signal pc_iu_ram_instr : std_ulogic_vector(0 to 31); +signal pc_iu_ram_instr_ext : std_ulogic_vector(0 to 3); +signal pc_iu_ram_mode : std_ulogic; +signal pc_iu_ram_thread : std_ulogic_vector(0 to 1); +signal pc_iu_trace_bus_enable : std_ulogic; +signal pc_xu_abst_sl_thold_3 : std_ulogic; +signal pc_xu_abst_slp_sl_thold_3 : std_ulogic; +signal pc_xu_regf_sl_thold_3 : std_ulogic; +signal pc_xu_regf_slp_sl_thold_3 : std_ulogic; +signal pc_xu_ary_nsl_thold_3 : std_ulogic; +signal pc_xu_ary_slp_nsl_thold_3 : std_ulogic; +signal pc_xu_cache_par_err_event : std_ulogic; +signal pc_xu_cfg_sl_thold_3 : std_ulogic; +signal pc_xu_cfg_slp_sl_thold_3 : std_ulogic; +signal pc_xu_dbg_action : std_ulogic_vector(0 to 11); +signal pc_xu_decrem_dis_on_stop : std_ulogic; +signal spr_pvr_version_dc : std_ulogic_vector(8 to 15); +signal spr_pvr_revision_dc : std_ulogic_vector(12 to 15); +signal xu_pc_spr_ccr0_we : std_ulogic_vector(0 to 3); +signal xu_pc_spr_ccr0_pme : std_ulogic_vector(0 to 1); +signal pc_xu_debug_mux1_ctrls : std_ulogic_vector(0 to 15); +signal pc_xu_debug_mux2_ctrls : std_ulogic_vector(0 to 15); +signal pc_xu_debug_mux3_ctrls : std_ulogic_vector(0 to 15); +signal pc_xu_debug_mux4_ctrls : std_ulogic_vector(0 to 15); +signal pc_xu_extirpts_dis_on_stop : std_ulogic; +signal pc_xu_fce_3 : std_ulogic_vector(0 to 1); +signal pc_xu_force_ude : std_ulogic_vector(0 to 3); +signal pc_xu_func_nsl_thold_3 : std_ulogic; +signal pc_xu_func_sl_thold_3 : std_ulogic_vector(0 to 4); +signal pc_xu_func_slp_nsl_thold_3 : std_ulogic; +signal pc_xu_func_slp_sl_thold_3 : std_ulogic_vector(0 to 4); +signal pc_xu_gptr_sl_thold_3 : std_ulogic; +signal pc_xu_init_reset : std_ulogic; +signal pc_xu_inj_dcache_parity : std_ulogic; +signal pc_xu_inj_dcachedir_parity : std_ulogic; +signal pc_xu_inj_llbust_attempt : std_ulogic_vector(0 to 3); +signal pc_xu_inj_llbust_failed : std_ulogic_vector(0 to 3); +signal pc_xu_inj_sprg_ecc : std_ulogic_vector(0 to 3); +signal pc_xu_inj_regfile_parity : std_ulogic_vector(0 to 3); +signal pc_xu_inj_wdt_reset : std_ulogic_vector(0 to 3); +signal pc_xu_inj_dcachedir_multihit : std_ulogic; +signal pc_xu_msrovride_enab : std_ulogic; +signal pc_xu_msrovride_pr : std_ulogic; +signal pc_xu_msrovride_gs : std_ulogic; +signal pc_xu_ram_mode : std_ulogic; +signal pc_xu_ram_thread : std_ulogic_vector(0 to 1); +signal pc_xu_ram_execute : std_ulogic; +signal pc_xu_repr_sl_thold_3 : std_ulogic; +signal pc_xu_reset_1_complete : std_ulogic; +signal pc_xu_reset_2_complete : std_ulogic; +signal pc_xu_reset_3_complete : std_ulogic; +signal pc_xu_reset_wd_complete : std_ulogic; +signal pc_xu_sg_3 : std_ulogic_vector(0 to 4); +signal pc_xu_step : std_ulogic_vector(0 to 3); +signal pc_xu_stop : std_ulogic_vector(0 to 3); +signal pc_xu_timebase_dis_on_stop : std_ulogic; +signal pc_xu_time_sl_thold_3 : std_ulogic; +signal pc_xu_trace_bus_enable : std_ulogic; +signal xu_n_is2_flush : std_ulogic_vector(0 to threads-1); +signal xu_n_rf0_flush : std_ulogic_vector(0 to threads-1); +signal xu_n_rf1_flush : std_ulogic_vector(0 to threads-1); +signal xu_n_ex1_flush : std_ulogic_vector(0 to threads-1); +signal xu_n_ex2_flush : std_ulogic_vector(0 to threads-1); +signal xu_n_ex3_flush : std_ulogic_vector(0 to threads-1); +signal xu_n_ex4_flush : std_ulogic_vector(0 to threads-1); +signal xu_n_ex5_flush : std_ulogic_vector(0 to threads-1); +signal xu_s_rf1_flush : std_ulogic_vector(0 to threads-1); +signal xu_s_ex1_flush : std_ulogic_vector(0 to threads-1); +signal xu_s_ex2_flush : std_ulogic_vector(0 to threads-1); +signal xu_s_ex3_flush : std_ulogic_vector(0 to threads-1); +signal xu_s_ex4_flush : std_ulogic_vector(0 to threads-1); +signal xu_s_ex5_flush : std_ulogic_vector(0 to threads-1); +signal xu_wu_rf1_flush : std_ulogic_vector(0 to threads-1); +signal xu_wu_ex1_flush : std_ulogic_vector(0 to threads-1); +signal xu_wu_ex2_flush : std_ulogic_vector(0 to threads-1); +signal xu_wu_ex3_flush : std_ulogic_vector(0 to threads-1); +signal xu_wu_ex4_flush : std_ulogic_vector(0 to threads-1); +signal xu_wu_ex5_flush : std_ulogic_vector(0 to threads-1); +signal xu_wl_rf1_flush : std_ulogic_vector(0 to threads-1); +signal xu_wl_ex1_flush : std_ulogic_vector(0 to threads-1); +signal xu_wl_ex2_flush : std_ulogic_vector(0 to threads-1); +signal xu_wl_ex3_flush : std_ulogic_vector(0 to threads-1); +signal xu_wl_ex4_flush : std_ulogic_vector(0 to threads-1); +signal xu_wl_ex5_flush : std_ulogic_vector(0 to threads-1); +signal xu_fu_ccr2_ap : std_ulogic_vector(0 to threads-1); +signal xu_fu_ex3_eff_addr : std_ulogic_vector(59 to 63); +signal xu_fu_ex6_load_data : std_ulogic_vector(0 to 255); +signal xu_fu_ex5_load_le : std_ulogic; +signal xu_fu_ex5_load_tag : std_ulogic_vector(0 to 8); +signal xu_fu_ex5_load_val : std_ulogic_vector(0 to threads-1); +signal xu_fu_ex5_reload_val : std_ulogic; +signal xu_fu_msr_fp : std_ulogic_vector(0 to 3); +signal xu_fu_msr_pr : std_ulogic_vector(0 to 3); +signal xu_fu_msr_gs : std_ulogic_vector(0 to 3); +signal xu_fu_msr_spv : std_ulogic_vector(0 to threads-1); +signal xu_fu_regfile_seq_beg : std_ulogic; +signal xu_iu_complete_qentry : std_ulogic_vector(0 to lmq_entries-1); +signal xu_iu_complete_target_type : std_ulogic_vector(0 to 1); +signal xu_iu_complete_tid : std_ulogic_vector(0 to 3); +signal xu_iu_ex1_ra_entry : std_ulogic_vector(8 to 11); +signal xu_iu_ex1_rb : std_ulogic_vector(64-(2**regmode) to 51); +signal xu_iu_ex1_rs_is : std_ulogic_vector(0 to 8); +signal xu_iu_ex5_bclr : std_ulogic; +signal xu_iu_ex5_bh : std_ulogic_vector(0 to 1); +signal xu_iu_ex5_br_hist : std_ulogic_vector(0 to 1); +signal xu_iu_ex5_br_taken : std_ulogic; +signal xu_iu_ex5_br_update : std_ulogic; +signal xu_iu_ex5_getNIA : std_ulogic; +signal xu_iu_ex5_gshare : std_ulogic_vector(0 to 3); +signal xu_iu_ex5_ifar : std_ulogic_vector(62-xu_eff_ifar to 61); +signal xu_iu_ex5_lk : std_ulogic; +signal xu_iu_ex5_ppc_cpl : std_ulogic_vector(0 to 3); +signal xu_iu_ex4_loadmiss_qentry : std_ulogic_vector(0 to lmq_entries-1); +signal xu_iu_ex4_loadmiss_target : std_ulogic_vector(0 to 8); +signal xu_iu_ex4_loadmiss_target_type: std_ulogic_vector(0 to 1); +signal xu_iu_ex4_loadmiss_tid : std_ulogic_vector(0 to 3); +signal xu_iu_ex4_rs_data : std_ulogic_vector(64-(2**regmode) to 63); +signal xu_iu_ex5_tid : std_ulogic_vector(0 to threads-1); +signal xu_iu_ex5_val : std_ulogic; +signal xu_iu_ex5_loadmiss_qentry : std_ulogic_vector(0 to lmq_entries-1); +signal xu_iu_ex5_loadmiss_target : std_ulogic_vector(0 to 8); +signal xu_iu_ex5_loadmiss_target_type: std_ulogic_vector(0 to 1); +signal xu_iu_ex5_loadmiss_tid : std_ulogic_vector(0 to 3); +signal xu_iu_ex6_icbi_val : std_ulogic_vector(0 to threads-1); +signal xu_iu_ex6_icbi_addr : std_ulogic_vector(64-xu_real_data_add to 57); +signal xu_iu_ex6_pri : std_ulogic_vector(0 to 2); +signal xu_iu_ex6_pri_val : std_ulogic_vector(0 to 3); +signal xu_iu_flush_2ucode : std_ulogic_vector(0 to 3); +signal xu_iu_flush_2ucode_type : std_ulogic_vector(0 to 3); +signal xu_iu_hid_mmu_mode : std_ulogic; +signal xu_iu_xucr0_rel : std_ulogic; +signal xu_iu_ici : std_ulogic; +signal xu_iu_iu0_flush_ifar0 : std_ulogic_vector(62-xu_eff_ifar to 61); +signal xu_iu_iu0_flush_ifar1 : std_ulogic_vector(62-xu_eff_ifar to 61); +signal xu_iu_iu0_flush_ifar2 : std_ulogic_vector(62-xu_eff_ifar to 61); +signal xu_iu_iu0_flush_ifar3 : std_ulogic_vector(62-xu_eff_ifar to 61); +signal xu_iu_larx_done_tid : std_ulogic_vector(0 to 3); +signal xu_iu_membar_tid : std_ulogic_vector(0 to 3); +signal xu_iu_msr_cm : std_ulogic_vector(0 to threads-1); +signal xu_iu_msr_gs : std_ulogic_vector(0 to 3); +signal xu_iu_msr_hv : std_ulogic_vector(0 to threads-1); +signal xu_iu_msr_is : std_ulogic_vector(0 to threads-1); +signal xu_iu_msr_pr : std_ulogic_vector(0 to threads-1); +signal xu_iu_multdiv_done : std_ulogic_vector(0 to threads-1); +signal xu_iu_need_hole : std_ulogic; +signal xu_iu_raise_iss_pri : std_ulogic_vector(0 to 3); +signal xu_iu_ram_issue : std_ulogic_vector(0 to threads-1); +signal xu_iu_ex1_is_csync : std_ulogic; +signal xu_iu_ex1_is_isync : std_ulogic; +signal xu_iu_rf1_is_eratilx : std_ulogic; +signal xu_iu_rf1_is_eratre : std_ulogic; +signal xu_iu_rf1_is_eratsx : std_ulogic; +signal xu_iu_rf1_is_eratwe : std_ulogic; +signal xu_iu_rf1_val : std_ulogic_vector(0 to 3); +signal xu_iu_rf1_ws : std_ulogic_vector(0 to 1); +signal xu_iu_rf1_t : std_ulogic_vector(0 to 2); +signal xu_iu_run_thread : std_ulogic_vector(0 to 3); +signal xu_iu_set_barr_tid : std_ulogic_vector(0 to 3); +signal xu_iu_single_instr_mode : std_ulogic_vector(0 to threads-1); +signal xu_iu_slowspr_done : std_ulogic_vector(0 to 3); +signal xu_iu_spr_ccr2_en_dcr : std_ulogic; +signal xu_iu_spr_ccr2_ifratsc : std_ulogic_vector(0 to 8); +signal xu_iu_spr_ccr2_ifrat : std_ulogic; +signal xu_bx_ccr2_en_ditc : std_ulogic; +signal xu_iu_spr_xer0 : std_ulogic_vector(57 to 63); +signal xu_iu_spr_xer1 : std_ulogic_vector(57 to 63); +signal xu_iu_spr_xer2 : std_ulogic_vector(57 to 63); +signal xu_iu_spr_xer3 : std_ulogic_vector(57 to 63); +signal xu_iu_uc_flush_ifar0 : std_ulogic_vector(62-uc_ifar to 61); +signal xu_iu_uc_flush_ifar1 : std_ulogic_vector(62-uc_ifar to 61); +signal xu_iu_uc_flush_ifar2 : std_ulogic_vector(62-uc_ifar to 61); +signal xu_iu_uc_flush_ifar3 : std_ulogic_vector(62-uc_ifar to 61); +signal xu_iu_ucode_restart : std_ulogic_vector(0 to 3); +signal xu_mm_derat_epn : std_ulogic_vector(64-rs_data_width to 51); +signal xu_mm_derat_lpid : std_ulogic_vector(0 to lpid_width-1); +signal xu_mm_derat_mmucr0 : std_ulogic_vector(0 to 17); +signal xu_mm_derat_mmucr0_we : std_ulogic_vector(0 to 3); +signal xu_mm_derat_mmucr1 : std_ulogic_vector(0 to 4); +signal xu_mm_derat_mmucr1_we : std_ulogic; +signal xu_mm_derat_req : std_ulogic; +signal xu_mm_derat_snoop_ack : std_ulogic; +signal xu_mm_derat_thdid : std_ulogic_vector(0 to 3); +signal xu_mm_derat_tid : std_ulogic_vector(0 to pid_width-1); +signal xu_mm_derat_ttype : std_ulogic_vector(0 to 1); +signal xu_mm_derat_state : std_ulogic_vector(0 to 3); +signal xu_mm_ex2_eff_addr : std_ulogic_vector(64-rs_data_width to 63); +signal xu_mm_ex1_rs_is : std_ulogic_vector(0 to 8); +signal xu_mm_ex4_flush : std_ulogic_vector(0 to thdid_width-1); +signal xu_mm_ex5_flush : std_ulogic_vector(0 to thdid_width-1); +signal xu_mm_ex5_perf_dtlb : std_ulogic_vector(0 to thdid_width-1); +signal xu_mm_ex5_perf_itlb : std_ulogic_vector(0 to thdid_width-1); +signal xu_mm_hid_mmu_mode : std_ulogic; +signal xu_mm_hold_ack : std_ulogic_vector(0 to thdid_width-1); +signal xu_mm_ierat_flush : std_ulogic_vector(0 to threads-1); +signal xu_mm_ierat_miss : std_ulogic_vector(0 to threads-1); +signal xu_mm_lmq_stq_empty : std_ulogic; +signal xu_mm_lsu_token : std_ulogic; +signal xu_mm_msr_cm : std_ulogic_vector(0 to threads-1); +signal xu_mm_msr_ds : std_ulogic_vector(0 to threads-1); +signal xu_mm_msr_gs : std_ulogic_vector(0 to threads-1); +signal xu_mm_msr_is : std_ulogic_vector(0 to threads-1); +signal xu_mm_msr_pr : std_ulogic_vector(0 to threads-1); +signal xu_mm_ex1_is_csync : std_ulogic; +signal xu_mm_ex1_is_isync : std_ulogic; +signal xu_mm_rf1_is_eratilx : std_ulogic; +signal xu_mm_rf1_is_erativax : std_ulogic; +signal xu_mm_rf1_is_tlbilx : std_ulogic; +signal xu_mm_rf1_is_tlbivax : std_ulogic; +signal xu_mm_rf1_is_tlbre : std_ulogic; +signal xu_mm_rf1_is_tlbsx : std_ulogic; +signal xu_mm_rf1_is_tlbsrx : std_ulogic; +signal xu_mm_rf1_is_tlbwe : std_ulogic; +signal xu_mm_rf1_val : std_ulogic_vector(0 to 3); +signal xu_mm_rf1_t : std_ulogic_vector(0 to 2); +signal xu_mm_slowspr_addr : std_ulogic_vector(0 to 9); +signal xu_mm_slowspr_data : std_ulogic_vector(64-(2**regmode) to 63); +signal xu_mm_slowspr_done : std_ulogic; +signal xu_mm_slowspr_etid : std_ulogic_vector(0 to 1); +signal xu_mm_slowspr_rw : std_ulogic; +signal xu_mm_slowspr_val : std_ulogic; +signal xu_mm_spr_epcr_dgtmi : std_ulogic_vector(0 to threads-1); +signal xu_mm_spr_epcr_dmiuh : std_ulogic_vector(0 to thdid_width-1); +signal xu_pc_err_attention_instr : std_ulogic_vector(0 to 3); +signal xu_pc_err_dcache_parity : std_ulogic; +signal xu_pc_err_dcachedir_parity : std_ulogic; +signal xu_pc_err_dcachedir_multihit : std_ulogic; +signal xu_pc_err_debug_event : std_ulogic_vector(0 to 3); +signal xu_pc_err_ditc_overrun : std_ulogic; +signal bx_pc_err_inbox_ecc : std_ulogic; +signal xu_pc_err_invld_reld : std_ulogic; +signal bx_pc_err_outbox_ecc : std_ulogic; +signal xu_pc_err_l2intrf_ecc : std_ulogic; +signal xu_pc_err_l2intrf_ue : std_ulogic; +signal xu_pc_err_l2credit_overrun : std_ulogic; +signal xu_pc_err_llbust_attempt : std_ulogic_vector(0 to 3); +signal xu_pc_err_llbust_failed : std_ulogic_vector(0 to 3); +signal xu_pc_err_nia_miscmpr : std_ulogic_vector(0 to 3); +signal xu_pc_err_regfile_parity : std_ulogic_vector(0 to 3); +signal xu_pc_err_regfile_ue : std_ulogic_vector(0 to 3); +signal xu_pc_err_sprg_ecc : std_ulogic_vector(0 to 3); +signal xu_pc_err_sprg_ue : std_ulogic_vector(0 to 3); +signal xu_pc_err_wdt_reset : std_ulogic_vector(0 to 3); +signal xu_pc_event_data : std_ulogic_vector(0 to 7); +signal xu_pc_lsu_event_data : std_ulogic_vector(0 to 7); +signal xu_pc_ram_data : std_ulogic_vector(64-(2**regmode) to 63); +signal xu_pc_ram_done : std_ulogic; +signal xu_pc_ram_interrupt : std_ulogic; +signal xu_pc_running : std_ulogic_vector(0 to 3); +signal xu_pc_step_done : std_ulogic_vector(0 to threads-1); +signal xu_pc_stop_dbg_event : std_ulogic_vector(0 to 3); +signal pc_fu_ccflush_dc : std_ulogic; +signal pc_iu_ccflush_dc : std_ulogic; +signal pc_xu_ccflush_dc : std_ulogic; +signal pc_bx_ccflush_dc : std_ulogic; +signal pc_fu_event_count_mode : std_ulogic_vector(0 to 2); +signal pc_iu_event_count_mode : std_ulogic_vector(0 to 2); +signal pc_xu_event_count_mode : std_ulogic_vector(0 to 2); +signal pc_fu_inj_regfile_parity : std_ulogic_vector(0 to 3); +signal pc_fu_instr_trace_mode : std_ulogic; +signal pc_fu_instr_trace_tid : std_ulogic_vector(0 to 1); +signal pc_xu_instr_trace_mode : std_ulogic; +signal pc_xu_instr_trace_tid : std_ulogic_vector(0 to 1); +signal pc_xu_ram_flush_thread : std_ulogic; +signal pc_bx_abist_di_0 : std_ulogic_vector(0 to 3); +signal pc_bx_abist_ena_dc : std_ulogic; +signal pc_bx_abist_g8t1p_renb_0 : std_ulogic; +signal pc_bx_abist_g8t_bw_0 : std_ulogic; +signal pc_bx_abist_g8t_bw_1 : std_ulogic; +signal pc_bx_abist_g8t_dcomp : std_ulogic_vector(0 to 3); +signal pc_bx_abist_g8t_wenb : std_ulogic; +signal pc_bx_abist_raddr_0 : std_ulogic_vector(0 to 9); +signal pc_bx_abist_raw_dc_b : std_ulogic; +signal pc_bx_abist_waddr_0 : std_ulogic_vector(0 to 9); +signal pc_bx_abist_wl64_comp_ena : std_ulogic; +signal pc_fu_abist_di_0 : std_ulogic_vector(0 to 3); +signal pc_fu_abist_di_1 : std_ulogic_vector(0 to 3); +signal pc_fu_abist_ena_dc : std_ulogic; +signal pc_fu_abist_grf_renb_0 : std_ulogic; +signal pc_fu_abist_grf_renb_1 : std_ulogic; +signal pc_fu_abist_grf_wenb_0 : std_ulogic; +signal pc_fu_abist_grf_wenb_1 : std_ulogic; +signal pc_fu_abist_raddr_0 : std_ulogic_vector(0 to 9); +signal pc_fu_abist_raddr_1 : std_ulogic_vector(0 to 9); +signal pc_fu_abist_raw_dc_b : std_ulogic; +signal pc_fu_abist_waddr_0 : std_ulogic_vector(0 to 9); +signal pc_fu_abist_waddr_1 : std_ulogic_vector(0 to 9); +signal pc_fu_abist_wl144_comp_ena : std_ulogic; +signal pc_iu_abist_dcomp_g6t_2r : std_ulogic_vector(0 to 3); +signal pc_iu_abist_di_0 : std_ulogic_vector(0 to 3); +signal pc_iu_abist_di_g6t_2r : std_ulogic_vector(0 to 3); +signal pc_iu_abist_ena_dc : std_ulogic; +signal pc_iu_abist_g6t_bw : std_ulogic_vector(0 to 1); +signal pc_iu_abist_g6t_r_wb : std_ulogic; +signal pc_iu_abist_g8t1p_renb_0 : std_ulogic; +signal pc_iu_abist_g8t_bw_0 : std_ulogic; +signal pc_iu_abist_g8t_bw_1 : std_ulogic; +signal pc_iu_abist_g8t_dcomp : std_ulogic_vector(0 to 3); +signal pc_iu_abist_g8t_wenb : std_ulogic; +signal pc_iu_abist_raddr_0 : std_ulogic_vector(0 to 9); +signal pc_iu_abist_raw_dc_b : std_ulogic; +signal pc_iu_abist_waddr_0 : std_ulogic_vector(0 to 9); +signal pc_iu_abist_wl128_comp_ena : std_ulogic; +signal pc_iu_abist_wl256_comp_ena : std_ulogic; +signal pc_iu_abist_wl64_comp_ena : std_ulogic; +signal pc_xu_abist_dcomp_g6t_2r : std_ulogic_vector(0 to 3); +signal pc_xu_abist_di_0 : std_ulogic_vector(0 to 3); +signal pc_xu_abist_di_1 : std_ulogic_vector(0 to 3); +signal pc_xu_abist_di_g6t_2r : std_ulogic_vector(0 to 3); +signal pc_xu_abist_ena_dc : std_ulogic; +signal pc_xu_abist_g6t_bw : std_ulogic_vector(0 to 1); +signal pc_xu_abist_g6t_r_wb : std_ulogic; +signal pc_xu_abist_g8t1p_renb_0 : std_ulogic; +signal pc_xu_abist_g8t_bw_0 : std_ulogic; +signal pc_xu_abist_g8t_bw_1 : std_ulogic; +signal pc_xu_abist_g8t_dcomp : std_ulogic_vector(0 to 3); +signal pc_xu_abist_g8t_wenb : std_ulogic; +signal pc_xu_abist_grf_renb_0 : std_ulogic; +signal pc_xu_abist_grf_renb_1 : std_ulogic; +signal pc_xu_abist_grf_wenb_0 : std_ulogic; +signal pc_xu_abist_grf_wenb_1 : std_ulogic; +signal pc_xu_abist_raddr_0 : std_ulogic_vector(0 to 9); +signal pc_xu_abist_raddr_1 : std_ulogic_vector(0 to 9); +signal pc_xu_abist_raw_dc_b : std_ulogic; +signal pc_xu_abist_waddr_0 : std_ulogic_vector(0 to 9); +signal pc_xu_abist_waddr_1 : std_ulogic_vector(0 to 9); +signal pc_xu_abist_wl144_comp_ena : std_ulogic; +signal pc_xu_abist_wl32_comp_ena : std_ulogic; +signal pc_xu_abist_wl512_comp_ena : std_ulogic; +signal xu_bx_ex1_mtdp_val : std_ulogic; -- command from mtdp is valid +signal xu_bx_ex1_mfdp_val : std_ulogic; -- command from mtdp is valid +signal xu_bx_ex1_ipc_thrd : std_ulogic_vector(0 to 1); -- Thread ID +signal xu_bx_ex2_ipc_ba : std_ulogic_vector(0 to 4); -- offset into the active 64B buffer +signal xu_bx_ex2_ipc_sz : std_ulogic_vector(0 to 1); -- size of data (00=4B, 10=16B) +signal xu_bx_ex4_256st_data : std_ulogic_vector(128 to 255); +signal bx_xu_ex4_mtdp_cr_status : std_ulogic; -- status (pas/fail) of the mtdp (sets CR) +signal bx_xu_ex4_mfdp_cr_status : std_ulogic; -- status (pas/fail) of the mfdp (sets CR) +signal bx_xu_ex5_dp_data : std_ulogic_vector(0 to 127); +signal bx_lsu_ob_pwr_tok : std_ulogic; +signal bx_lsu_ob_req_val : std_ulogic; +signal bx_lsu_ob_ditc_val : std_ulogic; +signal bx_lsu_ob_thrd : std_ulogic_vector(0 to 1); +signal bx_lsu_ob_qw : std_ulogic_vector(58 to 59); +signal bx_lsu_ob_dest : std_ulogic_vector(0 to 14); +signal bx_lsu_ob_data : std_ulogic_vector(0 to 127); +signal bx_lsu_ob_addr : std_ulogic_vector(64-xu_real_data_add to 57); +signal lsu_bx_cmd_avail : std_ulogic; +signal lsu_bx_cmd_sent : std_ulogic; +signal lsu_bx_cmd_stall : std_ulogic; +signal lsu_reld_data_vld : std_ulogic; -- reload data is coming in 2 cycles +signal bx_ib_empty_int : std_ulogic_vector(0 to 3); +signal ac_an_reld_ditc_pop_int : std_ulogic_vector(0 to 3); +signal lsu_reld_core_tag : std_ulogic_vector(3 to 4); -- reload data destinatoin tag (thread) +signal lsu_reld_ditc : std_ulogic; -- reload data is for ditc (inbox) +signal lsu_reld_ecc_err : std_ulogic; -- reload data has ecc error +signal lsu_reld_qw : std_ulogic_vector(58 to 59); -- reload data +signal lsu_reld_data : std_ulogic_vector(0 to 127); -- reload data +signal lsu_req_st_pop : std_ulogic; -- decrement outbox credit count +signal lsu_req_st_pop_thrd : std_ulogic_vector(0 to 2); -- decrement outbox credit count +signal pc_bx_func_sl_thold_3 : std_ulogic; +signal pc_bx_func_slp_sl_thold_3 : std_ulogic; +signal pc_bx_gptr_sl_thold_3 : std_ulogic; +signal pc_bx_time_sl_thold_3 : std_ulogic; +signal pc_bx_repr_sl_thold_3 : std_ulogic; +signal pc_bx_abst_sl_thold_3 : std_ulogic; +signal pc_bx_ary_nsl_thold_3 : std_ulogic; +signal pc_bx_ary_slp_nsl_thold_3 : std_ulogic; +signal pc_bx_sg_3 : std_ulogic; +signal rp_pc_rtim_sl_thold_6 : std_ulogic; +signal rp_pc_func_sl_thold_6 : std_ulogic; +signal rp_pc_func_nsl_thold_6 : std_ulogic; +signal rp_pc_ary_nsl_thold_6 : std_ulogic; +signal rp_pc_sg_6 : std_ulogic; +signal rp_pc_fce_6 : std_ulogic; +signal debug_start_tiedowns : std_ulogic_vector(0 to 87); +signal trigger_start_tiedowns : std_ulogic_vector(0 to 11); +signal bx_fu_debug_data : std_ulogic_vector(0 to 87); +signal bx_fu_trigger_data : std_ulogic_vector(0 to 11); +signal fu_pc_debug_data : std_ulogic_vector(0 to 87); +signal fu_pc_trigger_data : std_ulogic_vector(0 to 11); +signal pc_iu_debug_data : std_ulogic_vector(0 to 87); +signal pc_iu_trigger_data : std_ulogic_vector(0 to 11); +signal iu_xu_debug_data : std_ulogic_vector(0 to 87); +signal iu_xu_trigger_data : std_ulogic_vector(0 to 11); +signal xu_mm_debug_data : std_ulogic_vector(0 to 87); +signal xu_mm_trigger_data : std_ulogic_vector(0 to 11); +signal iu_pc_gptr_scan_out : std_ulogic; +signal pc_fu_gptr_scan_out : std_ulogic; +signal fu_bx_gptr_scan_out : std_ulogic; +signal bx_xu_gptr_scan_out : std_ulogic; +signal xu_mm_gptr_scan_out : std_ulogic; +signal iu_fu_time_scan_out : std_ulogic; +signal fu_bx_time_scan_out : std_ulogic; +signal bx_xu_time_scan_out : std_ulogic; +signal xu_mm_time_scan_out : std_ulogic; +signal iu_fu_repr_scan_out : std_ulogic; +signal fu_bx_repr_scan_out : std_ulogic; +signal bx_xu_repr_scan_out : std_ulogic; +signal xu_mm_repr_scan_out : std_ulogic; +signal mm_iu_ccfg_scan_out : std_ulogic; +signal iu_pc_ccfg_scan_out : std_ulogic; +signal xu_fu_ccfg_scan_out : std_ulogic; +signal iu_fu_bcfg_scan_out : std_ulogic; +signal mm_rp_bcfg_scan_out : std_ulogic; +signal rp_pc_bcfg_scan_out_q : std_ulogic; +signal mm_rp_dcfg_scan_out : std_ulogic; +signal rp_pc_dcfg_scan_out_q : std_ulogic; +signal iu_fu_dcfg_scan_out : std_ulogic; +signal pc_rp_abst_scan_out : std_ulogic; +signal rp_pc_func_scan_in_q : std_ulogic_vector(0 to 1); +signal pc_rp_func_scan_out : std_ulogic_vector(0 to 1); +signal rp_fu_abst_scan_in_q : std_ulogic; +signal fu_rp_abst_scan_out : std_ulogic; +signal fu_rp_ccfg_scan_out : std_ulogic; +signal fu_rp_bcfg_scan_out : std_ulogic; +signal fu_rp_dcfg_scan_out : std_ulogic; +signal rp_fu_func_scan_in_q : std_ulogic_vector(0 to 3); +signal fu_rp_func_scan_out : std_ulogic_vector(0 to 3); +signal rp_bx_abst_scan_in_q : std_ulogic; +signal bx_rp_abst_scan_out : std_ulogic; +signal rp_bx_func_scan_in_q : std_ulogic_vector(0 to 1); +signal rp_fu_bx_abst_scan_in : std_ulogic; +signal bx_fu_rp_abst_scan_out : std_ulogic; +signal rp_fu_bx_func_scan_in : std_ulogic_vector(0 to 1); +signal bx_fu_rp_func_scan_out : std_ulogic_vector(0 to 1); +signal bx_rp_func_scan_out : std_ulogic_vector(0 to 1); +signal pc_rp_bcfg_scan_out : std_ulogic; +signal pc_rp_ccfg_scan_out : std_ulogic; +signal pc_rp_dcfg_scan_out : std_ulogic; +signal iu_pc_abst_scan_out : std_ulogic; +signal rp_pc_scom_dch_q : std_ulogic; +signal rp_pc_scom_cch_q : std_ulogic; +signal rp_pc_checkstop_q : std_ulogic; +signal rp_pc_debug_stop_q : std_ulogic; +signal rp_pc_pm_thread_stop_q : std_ulogic_vector(0 to 3); +signal rp_pc_reset_1_complete_q : std_ulogic; +signal rp_pc_reset_2_complete_q : std_ulogic; +signal rp_pc_reset_3_complete_q : std_ulogic; +signal rp_pc_reset_wd_complete_q : std_ulogic; +signal rp_pc_abist_start_test_q : std_ulogic; +signal pc_rp_scom_dch : std_ulogic; +signal pc_rp_scom_cch : std_ulogic; +signal pc_rp_special_attn : std_ulogic_vector(0 to 3); +signal pc_rp_checkstop : std_ulogic_vector(0 to 2); +signal pc_rp_trace_error : std_ulogic; +signal pc_rp_local_checkstop : std_ulogic_vector(0 to 2); +signal pc_rp_recov_err : std_ulogic_vector(0 to 2); +signal pc_rp_event_bus : std_ulogic_vector(0 to 7); +signal pc_rp_fu_bypass_events : std_ulogic_vector(0 to 7); +signal pc_rp_iu_bypass_events : std_ulogic_vector(0 to 7); +signal pc_rp_mm_bypass_events : std_ulogic_vector(0 to 7); +signal pc_rp_lsu_bypass_events : std_ulogic_vector(0 to 7); +signal pc_rp_pm_thread_running : std_ulogic_vector(0 to 3); +signal pc_rp_power_managed : std_ulogic; +signal pc_rp_rvwinkle_mode : std_ulogic; +signal pc_fu_event_mux_ctrls : std_ulogic_vector(0 to 31); +signal pc_iu_event_mux_ctrls : std_ulogic_vector(0 to 47); +signal pc_xu_event_mux_ctrls : std_ulogic_vector(0 to 47); +signal pc_xu_lsu_event_mux_ctrls : std_ulogic_vector(0 to 47); +signal pc_fu_event_bus_enable : std_ulogic; +signal pc_iu_event_bus_enable : std_ulogic; +signal pc_xu_event_bus_enable : std_ulogic; +signal pc_rp_event_bus_enable : std_ulogic; +signal rp_mm_event_bus_enable_q : std_ulogic; +signal ac_an_debug_bus_int : std_ulogic_vector(0 to 87); +signal ac_rp_trace_to_perfcntr : std_ulogic_vector(0 to 7); +signal rp_pc_trace_to_perfcntr_q : std_ulogic_vector(0 to 7); +signal ac_an_power_managed_int : std_ulogic; +signal xu_iu_reld_core_tag : std_ulogic_vector(0 to 4); +signal xu_iu_reld_core_tag_clone : std_ulogic_vector(1 to 4); +signal xu_iu_reld_data : std_ulogic_vector(0 to 127); +signal xu_iu_reld_data_coming_clone : std_ulogic; +signal xu_iu_reld_data_vld : std_ulogic; +signal xu_iu_reld_data_vld_clone : std_ulogic; +signal xu_iu_reld_ecc_err : std_ulogic; +signal xu_iu_reld_ditc_clone : std_ulogic; +signal xu_iu_reld_ecc_err_ue : std_ulogic; +signal xu_iu_reld_qw : std_ulogic_vector(57 to 59); +signal xu_iu_stcx_complete : std_ulogic_vector(0 to 3); +signal xu_st_byte_enbl : std_ulogic_vector(0 to 15+(st_data_32b_mode*16)); +signal xu_st_data : std_ulogic_vector(0 to 127+(st_data_32b_mode*128)); +-- Start Bolt-On ABIST Signals +signal an_ac_bo_enable : std_ulogic; +signal an_ac_bo_go : std_ulogic; +signal an_ac_bo_cntlclk : std_ulogic; +signal an_ac_bo_ccflush : std_ulogic; +signal an_ac_bo_reset : std_ulogic; +signal an_ac_bo_data : std_ulogic; +signal an_ac_bo_shcntl : std_ulogic; +signal an_ac_bo_shdata : std_ulogic; +signal an_ac_bo_exe : std_ulogic; +signal an_ac_bo_sysrepair : std_ulogic; +signal an_ac_bo_donein : std_ulogic; +signal an_ac_bo_sdin : std_ulogic; +signal an_ac_bo_waitin : std_ulogic; +signal an_ac_bo_failin : std_ulogic; +signal an_ac_bo_fcshdata : std_ulogic; +signal an_ac_bo_fcreset : std_ulogic; +signal ac_an_bo_doneout : std_ulogic; +signal ac_an_bo_sdout : std_ulogic; +signal ac_an_bo_diagloopout : std_ulogic; +signal ac_an_bo_waitout : std_ulogic; +signal ac_an_bo_failout : std_ulogic; +signal pc_bx_bolt_sl_thold_3 : std_ulogic; +signal pc_fu_bolt_sl_thold_3 : std_ulogic; +signal pc_xu_bolt_sl_thold_3 : std_ulogic; +signal pc_bx_bo_enable_3 : std_ulogic; +signal pc_bx_bo_unload : std_ulogic; +signal pc_bx_bo_repair : std_ulogic; +signal pc_bx_bo_reset : std_ulogic; +signal pc_bx_bo_shdata : std_ulogic; +signal pc_bx_bo_select : std_ulogic_vector(0 to 3); +signal bx_pc_bo_fail : std_ulogic_vector(0 to 3); +signal bx_pc_bo_diagout : std_ulogic_vector(0 to 3); +signal pc_fu_bo_enable_3 : std_ulogic; +signal pc_fu_bo_unload : std_ulogic; +signal pc_fu_bo_load : std_ulogic; +signal pc_fu_bo_reset : std_ulogic; +signal pc_fu_bo_shdata : std_ulogic; +signal pc_fu_bo_select : std_ulogic_vector(0 to 1); +signal fu_pc_bo_fail : std_ulogic_vector(0 to 1); +signal fu_pc_bo_diagout : std_ulogic_vector(0 to 1); +signal pc_iu_bo_enable_4 : std_ulogic; +signal pc_iu_bo_unload : std_ulogic; +signal pc_iu_bo_repair : std_ulogic; +signal pc_iu_bo_reset : std_ulogic; +signal pc_iu_bo_shdata : std_ulogic; +signal pc_iu_bo_select : std_ulogic_vector(0 to 4); +signal iu_pc_bo_fail : std_ulogic_vector(0 to 4); +signal iu_pc_bo_diagout : std_ulogic_vector(0 to 4); +signal pc_xu_bo_enable_3 : std_ulogic; +signal pc_xu_bo_unload : std_ulogic; +signal pc_xu_bo_load : std_ulogic; +signal pc_xu_bo_repair : std_ulogic; +signal pc_xu_bo_reset : std_ulogic; +signal pc_xu_bo_shdata : std_ulogic; +signal pc_xu_bo_select : std_ulogic_vector(0 to 8); +signal xu_pc_bo_fail : std_ulogic_vector(0 to 8); +signal xu_pc_bo_diagout : std_ulogic_vector(0 to 8); +-- End Bolt-On ABIST Signals + +-- iu pass thru outputs +signal an_ac_abist_mode_dc_oiu : std_ulogic; +signal an_ac_ccflush_dc_oiu : std_ulogic; +signal an_ac_gsd_test_enable_dc_oiu : std_ulogic; +signal an_ac_gsd_test_acmode_dc_oiu : std_ulogic; +signal an_ac_lbist_ip_dc_oiu : std_ulogic; +signal an_ac_lbist_ac_mode_dc_oiu : std_ulogic; +signal an_ac_malf_alert_oiu : std_ulogic; +signal an_ac_psro_enable_dc_oiu : std_ulogic_vector(0 to 2); +signal an_ac_scan_type_dc_oiu : std_ulogic_vector(0 to 8); +signal an_ac_scom_sat_id_oiu : std_ulogic_vector(0 to 3); +signal an_ac_back_inv_oiu : std_ulogic; +signal an_ac_back_inv_addr_oiu : std_ulogic_vector(64-xu_real_data_add to 63); +signal an_ac_back_inv_target_bit1_oiu : std_ulogic; +signal an_ac_back_inv_target_bit3_oiu : std_ulogic; +signal an_ac_back_inv_target_bit4_oiu : std_ulogic; +signal an_ac_atpg_en_dc_oiu : std_ulogic; +signal an_ac_lbist_ary_wrt_thru_dc_oiu : std_ulogic; +signal an_ac_lbist_en_dc_oiu : std_ulogic; +signal an_ac_scan_diag_dc_oiu : std_ulogic; +signal an_ac_scan_dis_dc_b_oiu : std_ulogic; +-- _omm suffix means output from mmu +signal an_ac_back_inv_omm : std_ulogic; +signal an_ac_back_inv_addr_omm : std_ulogic_vector(64-real_addr_width to 63); +signal an_ac_back_inv_target_omm_iua : std_ulogic_vector(0 to 1); +signal an_ac_back_inv_target_omm_iub : std_ulogic_vector(3 to 4); +signal an_ac_reld_core_tag_omm : std_ulogic_vector(0 to 4); +signal an_ac_reld_data_omm : std_ulogic_vector(0 to 127); +signal an_ac_reld_data_vld_omm : std_ulogic; +signal an_ac_reld_ecc_err_omm : std_ulogic; +signal an_ac_reld_ecc_err_ue_omm : std_ulogic; +signal an_ac_reld_qw_omm : std_ulogic_vector(57 to 59); +signal an_ac_reld_ditc_omm : std_ulogic; +signal an_ac_reld_crit_qw_omm : std_ulogic; +signal an_ac_reld_data_coming_omm : std_ulogic; +signal an_ac_reld_l1_dump_omm : std_ulogic; +signal an_ac_camfence_en_dc_omm : std_ulogic; +signal an_ac_stcx_complete_omm : std_ulogic_vector(0 to 3); +signal an_ac_abist_mode_dc_omm : std_ulogic; +signal an_ac_abist_start_test_omm : std_ulogic; +signal an_ac_abst_scan_in_omm_iu : std_ulogic_vector(0 to 4); +signal an_ac_abst_scan_in_omm_xu : std_ulogic_vector(7 to 9); +signal an_ac_atpg_en_dc_omm : std_ulogic; +signal an_ac_bcfg_scan_in_omm_bit1 : std_ulogic; +signal an_ac_bcfg_scan_in_omm_bit3 : std_ulogic; +signal an_ac_bcfg_scan_in_omm_bit4 : std_ulogic; +signal an_ac_lbist_ary_wrt_thru_dc_omm : std_ulogic; +signal an_ac_ccflush_dc_omm : std_ulogic; +signal an_ac_reset_1_complete_omm : std_ulogic; +signal an_ac_reset_2_complete_omm : std_ulogic; +signal an_ac_reset_3_complete_omm : std_ulogic; +signal an_ac_reset_wd_complete_omm : std_ulogic; +signal an_ac_dcfg_scan_in_omm : std_ulogic_vector(1 to 2); +signal an_ac_debug_stop_omm : std_ulogic; +signal an_ac_func_scan_in_omm_iua : std_ulogic_vector(0 to 21); +signal an_ac_func_scan_in_omm_iub : std_ulogic_vector(60 to 63); +signal an_ac_func_scan_in_omm_xu : std_ulogic_vector(31 to 58); +signal an_ac_lbist_en_dc_omm : std_ulogic; +signal an_ac_pm_thread_stop_omm : std_ulogic_vector(0 to 3); +signal an_ac_regf_scan_in_omm : std_ulogic_vector(0 to 11); +signal an_ac_scan_diag_dc_omm : std_ulogic; +signal an_ac_scan_dis_dc_b_omm : std_ulogic; +signal an_ac_scom_cch_omm : std_ulogic; +signal an_ac_scom_dch_omm : std_ulogic; +signal an_ac_checkstop_omm : std_ulogic; +-- _imm prefix means input to mmu +signal ac_an_abst_scan_out_imm_iu : std_ulogic_vector(0 to 4); +signal ac_an_abst_scan_out_imm_xu : std_ulogic_vector(7 to 9); +signal ac_an_bcfg_scan_out_imm : std_ulogic_vector(0 to 4); +signal ac_an_dcfg_scan_out_imm : std_ulogic_vector(0 to 2); +signal ac_an_func_scan_out_imm_iua : std_ulogic_vector(0 to 21); +signal ac_an_func_scan_out_imm_iub : std_ulogic_vector(60 to 63); +signal ac_an_func_scan_out_imm_xu : std_ulogic_vector(31 to 58); +signal ac_an_reld_ditc_pop_imm : std_ulogic_vector(0 to 3); +signal ac_an_power_managed_imm : std_ulogic; +signal ac_an_rvwinkle_mode_imm : std_ulogic; +signal ac_an_fu_bypass_events_imm : std_ulogic_vector(0 to 7); +signal ac_an_iu_bypass_events_imm : std_ulogic_vector(0 to 7); +signal ac_an_mm_bypass_events_imm : std_ulogic_vector(0 to 7); +signal ac_an_lsu_bypass_events_imm : std_ulogic_vector(0 to 7); +signal ac_an_event_bus_imm : std_ulogic_vector(0 to 7); +signal ac_an_pm_thread_running_imm : std_ulogic_vector(0 to 3); +signal ac_an_recov_err_imm : std_ulogic_vector(0 to 2); +signal ac_an_regf_scan_out_imm : std_ulogic_vector(0 to 11); +signal ac_an_scom_cch_imm : std_ulogic; +signal ac_an_scom_dch_imm : std_ulogic; +signal ac_an_special_attn_imm : std_ulogic_vector(0 to 3); +signal ac_an_checkstop_imm : std_ulogic_vector(0 to 2); +signal ac_an_local_checkstop_imm : std_ulogic_vector(0 to 2); +signal ac_an_trace_error_imm : std_ulogic; + +signal bx_pc_err_inbox_ue_ofu : std_ulogic; +signal bx_pc_err_outbox_ue_ofu : std_ulogic; +signal bx_pc_err_inbox_ecc_ofu : std_ulogic; +signal bx_pc_err_outbox_ecc_ofu : std_ulogic; +signal pc_bx_bolt_sl_thold_3_ofu : std_ulogic; +signal pc_bx_bo_enable_3_ofu : std_ulogic; +signal pc_bx_bo_unload_ofu : std_ulogic; +signal pc_bx_bo_repair_ofu : std_ulogic; +signal pc_bx_bo_reset_ofu : std_ulogic; +signal pc_bx_bo_shdata_ofu : std_ulogic; +signal pc_bx_bo_select_ofu : std_ulogic_vector(0 to 3); +signal bx_pc_bo_fail_ofu : std_ulogic_vector(0 to 3); +signal bx_pc_bo_diagout_ofu : std_ulogic_vector(0 to 3); +signal pc_bx_abist_di_0_ofu : std_ulogic_vector(0 to 3); +signal pc_bx_abist_ena_dc_ofu : std_ulogic; +signal pc_bx_abist_g8t1p_renb_0_ofu : std_ulogic; +signal pc_bx_abist_g8t_bw_0_ofu : std_ulogic; +signal pc_bx_abist_g8t_bw_1_ofu : std_ulogic; +signal pc_bx_abist_g8t_dcomp_ofu : std_ulogic_vector(0 to 3); +signal pc_bx_abist_g8t_wenb_ofu : std_ulogic; +signal pc_bx_abist_raddr_0_ofu : std_ulogic_vector(4 to 9); +signal pc_bx_abist_raw_dc_b_ofu : std_ulogic; +signal pc_bx_abist_waddr_0_ofu : std_ulogic_vector(4 to 9); +signal pc_bx_abist_wl64_comp_ena_ofu : std_ulogic; +signal pc_bx_trace_bus_enable_ofu : std_ulogic; +signal pc_bx_debug_mux1_ctrls_ofu : std_ulogic_vector(0 to 15); +signal pc_bx_inj_inbox_ecc_ofu : std_ulogic; +signal pc_bx_inj_outbox_ecc_ofu : std_ulogic; +signal pc_bx_ccflush_dc_ofu : std_ulogic; +signal pc_bx_sg_3_ofu : std_ulogic; +signal pc_bx_func_sl_thold_3_ofu : std_ulogic; +signal pc_bx_func_slp_sl_thold_3_ofu : std_ulogic; +signal pc_bx_gptr_sl_thold_3_ofu : std_ulogic; +signal pc_bx_time_sl_thold_3_ofu : std_ulogic; +signal pc_bx_repr_sl_thold_3_ofu : std_ulogic; +signal pc_bx_abst_sl_thold_3_ofu : std_ulogic; +signal pc_bx_ary_nsl_thold_3_ofu : std_ulogic; +signal pc_bx_ary_slp_nsl_thold_3_ofu : std_ulogic; + +signal xu_pc_err_mcsr_summary_ofu : std_ulogic_vector(0 to 3); +signal xu_pc_err_ierat_parity_ofu : std_ulogic; +signal xu_pc_err_derat_parity_ofu : std_ulogic; +signal xu_pc_err_tlb_parity_ofu : std_ulogic; +signal xu_pc_err_tlb_lru_parity_ofu : std_ulogic; +signal xu_pc_err_ierat_multihit_ofu : std_ulogic; +signal xu_pc_err_derat_multihit_ofu : std_ulogic; +signal xu_pc_err_tlb_multihit_ofu : std_ulogic; +signal xu_pc_err_ext_mchk_ofu : std_ulogic; +signal xu_pc_err_ditc_overrun_ofu : std_ulogic; +signal xu_pc_err_local_snoop_reject_ofu : std_ulogic; +signal xu_pc_err_attention_instr_ofu : std_ulogic_vector(0 to 3); +signal xu_pc_err_dcache_parity_ofu : std_ulogic; +signal xu_pc_err_dcachedir_parity_ofu : std_ulogic; +signal xu_pc_err_dcachedir_multihit_ofu : std_ulogic; +signal xu_pc_err_debug_event_ofu : std_ulogic_vector(0 to 3); +signal xu_pc_err_invld_reld_ofu : std_ulogic; +signal xu_pc_err_l2intrf_ecc_ofu : std_ulogic; +signal xu_pc_err_l2intrf_ue_ofu : std_ulogic; +signal xu_pc_err_l2credit_overrun_ofu : std_ulogic; +signal xu_pc_err_llbust_attempt_ofu : std_ulogic_vector(0 to 3); +signal xu_pc_err_llbust_failed_ofu : std_ulogic_vector(0 to 3); +signal xu_pc_err_nia_miscmpr_ofu : std_ulogic_vector(0 to 3); +signal xu_pc_err_regfile_parity_ofu : std_ulogic_vector(0 to 3); +signal xu_pc_err_regfile_ue_ofu : std_ulogic_vector(0 to 3); +signal xu_pc_err_sprg_ecc_ofu : std_ulogic_vector(0 to 3); +signal xu_pc_err_sprg_ue_ofu : std_ulogic_vector(0 to 3); +signal xu_pc_err_wdt_reset_ofu : std_ulogic_vector(0 to 3); +signal xu_pc_event_data_ofu : std_ulogic_vector(0 to 7); +signal xu_pc_ram_data_ofu : std_ulogic_vector(64-(2**regmode) to 63); +signal xu_pc_ram_done_ofu : std_ulogic; +signal xu_pc_ram_interrupt_ofu : std_ulogic; +signal xu_pc_running_ofu : std_ulogic_vector(0 to 3); +signal xu_pc_spr_ccr0_pme_ofu : std_ulogic_vector(0 to 1); +signal xu_pc_spr_ccr0_we_ofu : std_ulogic_vector(0 to 3); +signal xu_pc_step_done_ofu : std_ulogic_vector(0 to 3); +signal xu_pc_stop_dbg_event_ofu : std_ulogic_vector(0 to 3); +signal pc_xu_bolt_sl_thold_3_ofu : std_ulogic; +signal pc_xu_bo_enable_3_ofu : std_ulogic; +signal pc_xu_bo_unload_ofu : std_ulogic; +signal pc_xu_bo_load_ofu : std_ulogic; +signal pc_xu_bo_repair_ofu : std_ulogic; +signal pc_xu_bo_reset_ofu : std_ulogic; +signal pc_xu_bo_shdata_ofu : std_ulogic; +signal pc_xu_bo_select_ofu : std_ulogic_vector(0 to 8); +signal xu_pc_bo_fail_ofu : std_ulogic_vector(0 to 8); +signal xu_pc_bo_diagout_ofu : std_ulogic_vector(0 to 8); +signal pc_xu_abist_dcomp_g6t_2r_ofu : std_ulogic_vector(0 to 3); +signal pc_xu_abist_di_0_ofu : std_ulogic_vector(0 to 3); +signal pc_xu_abist_di_1_ofu : std_ulogic_vector(0 to 3); +signal pc_xu_abist_di_g6t_2r_ofu : std_ulogic_vector(0 to 3); +signal pc_xu_abist_ena_dc_ofu : std_ulogic; +signal pc_xu_abist_g6t_bw_ofu : std_ulogic_vector(0 to 1); +signal pc_xu_abist_g6t_r_wb_ofu : std_ulogic; +signal pc_xu_abist_g8t1p_renb_0_ofu : std_ulogic; +signal pc_xu_abist_g8t_bw_0_ofu : std_ulogic; +signal pc_xu_abist_g8t_bw_1_ofu : std_ulogic; +signal pc_xu_abist_g8t_dcomp_ofu : std_ulogic_vector(0 to 3); +signal pc_xu_abist_g8t_wenb_ofu : std_ulogic; +signal pc_xu_abist_grf_renb_0_ofu : std_ulogic; +signal pc_xu_abist_grf_renb_1_ofu : std_ulogic; +signal pc_xu_abist_grf_wenb_0_ofu : std_ulogic; +signal pc_xu_abist_grf_wenb_1_ofu : std_ulogic; +signal pc_xu_abist_raddr_0_ofu : std_ulogic_vector(0 to 9); +signal pc_xu_abist_raddr_1_ofu : std_ulogic_vector(0 to 9); +signal pc_xu_abist_raw_dc_b_ofu : std_ulogic; +signal pc_xu_abist_waddr_0_ofu : std_ulogic_vector(0 to 9); +signal pc_xu_abist_waddr_1_ofu : std_ulogic_vector(0 to 9); +signal pc_xu_abist_wl144_comp_ena_ofu : std_ulogic; +signal pc_xu_abist_wl32_comp_ena_ofu : std_ulogic; +signal pc_xu_abist_wl512_comp_ena_ofu : std_ulogic; +signal pc_xu_event_mux_ctrls_ofu : std_ulogic_vector(0 to 47); +signal pc_xu_lsu_event_mux_ctrls_ofu : std_ulogic_vector(0 to 47); +signal pc_xu_event_bus_enable_ofu : std_ulogic; +signal pc_xu_abst_sl_thold_3_ofu : std_ulogic; +signal pc_xu_abst_slp_sl_thold_3_ofu : std_ulogic; +signal pc_xu_regf_sl_thold_3_ofu : std_ulogic; +signal pc_xu_regf_slp_sl_thold_3_ofu : std_ulogic; +signal pc_xu_ary_nsl_thold_3_ofu : std_ulogic; +signal pc_xu_ary_slp_nsl_thold_3_ofu : std_ulogic; +signal pc_xu_cache_par_err_event_ofu : std_ulogic; +signal pc_xu_ccflush_dc_ofu : std_ulogic; +signal pc_xu_cfg_sl_thold_3_ofu : std_ulogic; +signal pc_xu_cfg_slp_sl_thold_3_ofu : std_ulogic; +signal pc_xu_dbg_action_ofu : std_ulogic_vector(0 to 11); +signal pc_xu_debug_mux1_ctrls_ofu : std_ulogic_vector(0 to 15); +signal pc_xu_debug_mux2_ctrls_ofu : std_ulogic_vector(0 to 15); +signal pc_xu_debug_mux3_ctrls_ofu : std_ulogic_vector(0 to 15); +signal pc_xu_debug_mux4_ctrls_ofu : std_ulogic_vector(0 to 15); +signal pc_xu_decrem_dis_on_stop_ofu : std_ulogic; +signal pc_xu_event_count_mode_ofu : std_ulogic_vector(0 to 2); +signal pc_xu_extirpts_dis_on_stop_ofu : std_ulogic; +signal pc_xu_fce_3_ofu : std_ulogic_vector(0 to 1); +signal pc_xu_force_ude_ofu : std_ulogic_vector(0 to 3); +signal pc_xu_func_nsl_thold_3_ofu : std_ulogic; +signal pc_xu_func_sl_thold_3_ofu : std_ulogic_vector(0 to 4); +signal pc_xu_func_slp_nsl_thold_3_ofu : std_ulogic; +signal pc_xu_func_slp_sl_thold_3_ofu : std_ulogic_vector(0 to 4); +signal pc_xu_gptr_sl_thold_3_ofu : std_ulogic; +signal pc_xu_init_reset_ofu : std_ulogic; +signal pc_xu_inj_dcache_parity_ofu : std_ulogic; +signal pc_xu_inj_dcachedir_parity_ofu : std_ulogic; +signal pc_xu_inj_llbust_attempt_ofu : std_ulogic_vector(0 to 3); +signal pc_xu_inj_llbust_failed_ofu : std_ulogic_vector(0 to 3); +signal pc_xu_inj_sprg_ecc_ofu : std_ulogic_vector(0 to 3); +signal pc_xu_inj_regfile_parity_ofu : std_ulogic_vector(0 to 3); +signal pc_xu_inj_wdt_reset_ofu : std_ulogic_vector(0 to 3); +signal pc_xu_inj_dcachedir_multihit_ofu : std_ulogic; +signal pc_xu_instr_trace_mode_ofu : std_ulogic; +signal pc_xu_instr_trace_tid_ofu : std_ulogic_vector(0 to 1); +signal pc_xu_msrovride_enab_ofu : std_ulogic; +signal pc_xu_msrovride_gs_ofu : std_ulogic; +signal pc_xu_msrovride_pr_ofu : std_ulogic; +signal pc_xu_ram_execute_ofu : std_ulogic; +signal pc_xu_ram_flush_thread_ofu : std_ulogic; +signal pc_xu_ram_mode_ofu : std_ulogic; +signal pc_xu_ram_thread_ofu : std_ulogic_vector(0 to 1); +signal pc_xu_repr_sl_thold_3_ofu : std_ulogic; +signal pc_xu_reset_1_cmplt_ofu : std_ulogic; +signal pc_xu_reset_2_cmplt_ofu : std_ulogic; +signal pc_xu_reset_3_cmplt_ofu : std_ulogic; +signal pc_xu_reset_wd_cmplt_ofu : std_ulogic; +signal pc_xu_sg_3_ofu : std_ulogic_vector(0 to 4); +signal pc_xu_step_ofu : std_ulogic_vector(0 to 3); +signal pc_xu_stop_ofu : std_ulogic_vector(0 to 3); +signal pc_xu_time_sl_thold_3_ofu : std_ulogic; +signal pc_xu_timebase_dis_on_stop_ofu : std_ulogic; +signal pc_xu_trace_bus_enable_ofu : std_ulogic; + +signal an_ac_crit_interrupt_omm : std_ulogic_vector(0 to thdid_width-1); +signal an_ac_ext_interrupt_omm : std_ulogic_vector(0 to thdid_width-1); +signal an_ac_flh2l2_gate_omm : std_ulogic; +signal an_ac_icbi_ack_omm : std_ulogic; +signal an_ac_icbi_ack_thread_omm : std_ulogic_vector(0 to 1); +signal an_ac_req_ld_pop_omm : std_ulogic; +signal an_ac_req_spare_ctrl_a1_omm : std_ulogic_vector(0 to 3); +signal an_ac_req_st_gather_omm : std_ulogic; +signal an_ac_req_st_pop_omm : std_ulogic; +signal an_ac_req_st_pop_thrd_omm : std_ulogic_vector(0 to 2); +signal an_ac_reservation_vld_omm : std_ulogic_vector(0 to thdid_width-1); +signal an_ac_sleep_en_omm : std_ulogic_vector(0 to thdid_width-1); +signal an_ac_stcx_pass_omm : std_ulogic_vector(0 to 3); +signal an_ac_sync_ack_omm : std_ulogic_vector(0 to 3); +signal an_ac_ary_nsl_thold_7_omm : std_ulogic; +signal an_ac_coreid_omm : std_ulogic_vector(0 to 7); +signal an_ac_external_mchk_omm : std_ulogic_vector(0 to 3); +signal an_ac_fce_7_omm : std_ulogic; +signal an_ac_func_nsl_thold_7_omm : std_ulogic; +signal an_ac_func_sl_thold_7_omm : std_ulogic; +signal an_ac_gsd_test_enable_dc_omm : std_ulogic; +signal an_ac_gsd_test_acmode_dc_omm : std_ulogic; +signal an_ac_gptr_scan_in_omm : std_ulogic; +signal an_ac_hang_pulse_omm : std_ulogic_vector(0 to thdid_width-1); +signal an_ac_lbist_ac_mode_dc_omm : std_ulogic; +signal an_ac_lbist_ip_dc_omm : std_ulogic; +signal an_ac_malf_alert_omm : std_ulogic; +signal an_ac_perf_interrupt_omm : std_ulogic_vector(0 to thdid_width-1); +signal an_ac_psro_enable_dc_omm : std_ulogic_vector(0 to 2); +signal an_ac_repr_scan_in_omm : std_ulogic; +signal an_ac_rtim_sl_thold_7_omm : std_ulogic; +signal an_ac_scan_type_dc_omm : std_ulogic_vector(0 to 8); +signal an_ac_scom_sat_id_omm : std_ulogic_vector(0 to 3); +signal an_ac_sg_7_omm : std_ulogic; +signal an_ac_tb_update_enable_omm : std_ulogic; +signal an_ac_tb_update_pulse_omm : std_ulogic; +signal an_ac_time_scan_in_omm : std_ulogic; + +signal ac_an_box_empty_imm : std_ulogic_vector(0 to 3); +signal ac_an_machine_check_imm : std_ulogic_vector(0 to thdid_width-1); +signal ac_an_req_imm : std_ulogic; +signal ac_an_req_endian_imm : std_ulogic; +signal ac_an_req_ld_core_tag_imm : std_ulogic_vector(0 to 4); +signal ac_an_req_ld_xfr_len_imm : std_ulogic_vector(0 to 2); +signal ac_an_req_pwr_token_imm : std_ulogic; +signal ac_an_req_ra_imm : std_ulogic_vector(64-real_addr_width to 63); +signal ac_an_req_spare_ctrl_a0_imm : std_ulogic_vector(0 to 3); +signal ac_an_req_thread_imm : std_ulogic_vector(0 to 2); +signal ac_an_req_ttype_imm : std_ulogic_vector(0 to 5); +signal ac_an_req_user_defined_imm : std_ulogic_vector(0 to 3); +signal ac_an_req_wimg_g_imm : std_ulogic; +signal ac_an_req_wimg_i_imm : std_ulogic; +signal ac_an_req_wimg_m_imm : std_ulogic; +signal ac_an_req_wimg_w_imm : std_ulogic; +signal ac_an_st_byte_enbl_imm : std_ulogic_vector(0 to 31); +signal ac_an_st_byte_enbl_omm : std_ulogic_vector(16 to 31); +signal ac_an_st_data_imm : std_ulogic_vector(0 to 255); +signal ac_an_st_data_omm : std_ulogic_vector(128 to 255); +signal ac_an_st_data_pwr_token_imm : std_ulogic; +signal ac_an_debug_trigger_imm : std_ulogic_vector(0 to thdid_width-1); +signal ac_an_reset_1_request_imm : std_ulogic; +signal ac_an_reset_2_request_imm : std_ulogic; +signal ac_an_reset_3_request_imm : std_ulogic; +signal ac_an_reset_wd_request_imm : std_ulogic; +signal an_ac_scan_diag_dc_opc : std_ulogic; +signal an_ac_scan_dis_dc_b_opc : std_ulogic; +signal an_ac_scan_dis_dc_b_ofu : std_ulogic; +signal an_ac_scan_diag_dc_ofu : std_ulogic; + +signal ac_an_abist_done_dc_iiu : std_ulogic; +signal ac_an_psro_ringsig_iiu : std_ulogic; +signal an_ac_ccenable_dc_iiu : std_ulogic; +signal mm_pc_bo_fail_iiu : std_ulogic_vector(0 to 4); +signal mm_pc_bo_diagout_iiu : std_ulogic_vector(0 to 4); +signal mm_pc_event_data_iiu : std_ulogic_vector(0 to 7); + +signal ac_an_abist_done_dc_oiu : std_ulogic; +signal ac_an_psro_ringsig_oiu : std_ulogic; +signal an_ac_ccenable_dc_oiu : std_ulogic; +signal mm_pc_bo_fail_oiu : std_ulogic_vector(0 to 4); +signal mm_pc_bo_diagout_oiu : std_ulogic_vector(0 to 4); +signal mm_pc_event_data_oiu : std_ulogic_vector(0 to 7); + +signal pc_mm_abist_dcomp_g6t_2r_iiu : std_ulogic_vector(0 to 3); +signal pc_mm_abist_di_g6t_2r_iiu : std_ulogic_vector(0 to 3); +signal pc_mm_abist_di_0_iiu : std_ulogic_vector(0 to 3); +signal pc_mm_abist_ena_dc_iiu : std_ulogic; +signal pc_mm_abist_g6t_r_wb_iiu : std_ulogic; +signal pc_mm_abist_g8t_bw_0_iiu : std_ulogic; +signal pc_mm_abist_g8t_bw_1_iiu : std_ulogic; +signal pc_mm_abist_g8t_dcomp_iiu : std_ulogic_vector(0 to 3); +signal pc_mm_abist_g8t_wenb_iiu : std_ulogic; +signal pc_mm_abist_g8t1p_renb_0_iiu : std_ulogic; +signal pc_mm_abist_raddr_0_iiu : std_ulogic_vector(0 to 9); +signal pc_mm_abist_raw_dc_b_iiu : std_ulogic; +signal pc_mm_abist_waddr_0_iiu : std_ulogic_vector(0 to 9); +signal pc_mm_abist_wl128_comp_ena_iiu : std_ulogic; +signal pc_mm_bo_enable_4_iiu : std_ulogic; +signal pc_mm_bo_repair_iiu : std_ulogic; +signal pc_mm_bo_reset_iiu : std_ulogic; +signal pc_mm_bo_select_iiu : std_ulogic_vector(0 to 4); +signal pc_mm_bo_shdata_iiu : std_ulogic; +signal pc_mm_bo_unload_iiu : std_ulogic; +signal pc_mm_ccflush_dc_iiu : std_ulogic; +signal pc_mm_debug_mux1_ctrls_iiu : std_ulogic_vector(0 to 15); +signal pc_mm_event_count_mode_iiu : std_ulogic_vector(0 to 2); +signal pc_mm_event_mux_ctrls_iiu : std_ulogic_vector(0 to 39); +signal pc_mm_trace_bus_enable_iiu : std_ulogic; +signal pc_mm_abist_dcomp_g6t_2r_oiu : std_ulogic_vector(0 to 3); +signal pc_mm_abist_di_g6t_2r_oiu : std_ulogic_vector(0 to 3); +signal pc_mm_abist_di_0_oiu : std_ulogic_vector(0 to 3); +signal pc_mm_abist_ena_dc_oiu : std_ulogic; +signal pc_mm_abist_g6t_r_wb_oiu : std_ulogic; +signal pc_mm_abist_g8t_bw_0_oiu : std_ulogic; +signal pc_mm_abist_g8t_bw_1_oiu : std_ulogic; +signal pc_mm_abist_g8t_dcomp_oiu : std_ulogic_vector(0 to 3); +signal pc_mm_abist_g8t_wenb_oiu : std_ulogic; +signal pc_mm_abist_g8t1p_renb_0_oiu : std_ulogic; +signal pc_mm_abist_raddr_0_oiu : std_ulogic_vector(0 to 9); +signal pc_mm_abist_raw_dc_b_oiu : std_ulogic; +signal pc_mm_abist_waddr_0_oiu : std_ulogic_vector(0 to 9); +signal pc_mm_abist_wl128_comp_ena_oiu : std_ulogic; +signal pc_mm_abst_sl_thold_3_oiu : std_ulogic; +signal pc_mm_abst_slp_sl_thold_3_oiu : std_ulogic; +signal pc_mm_ary_nsl_thold_3_oiu : std_ulogic; +signal pc_mm_ary_slp_nsl_thold_3_oiu : std_ulogic; +signal pc_mm_bo_enable_3_oiu : std_ulogic; +signal pc_mm_bo_repair_oiu : std_ulogic; +signal pc_mm_bo_reset_oiu : std_ulogic; +signal pc_mm_bo_select_oiu : std_ulogic_vector(0 to 4); +signal pc_mm_bo_shdata_oiu : std_ulogic; +signal pc_mm_bo_unload_oiu : std_ulogic; +signal pc_mm_bolt_sl_thold_3_oiu : std_ulogic; +signal pc_mm_ccflush_dc_oiu : std_ulogic; +signal pc_mm_cfg_sl_thold_3_oiu : std_ulogic; +signal pc_mm_cfg_slp_sl_thold_3_oiu : std_ulogic; +signal pc_mm_debug_mux1_ctrls_oiu : std_ulogic_vector(0 to 15); +signal pc_mm_event_count_mode_oiu : std_ulogic_vector(0 to 2); +signal pc_mm_event_mux_ctrls_oiu : std_ulogic_vector(0 to 39); +signal pc_mm_fce_3_oiu : std_ulogic; +signal pc_mm_func_nsl_thold_3_oiu : std_ulogic; +signal pc_mm_func_sl_thold_3_oiu : std_ulogic_vector(0 to 1); +signal pc_mm_func_slp_nsl_thold_3_oiu : std_ulogic; +signal pc_mm_func_slp_sl_thold_3_oiu : std_ulogic_vector(0 to 1); +signal pc_mm_gptr_sl_thold_3_oiu : std_ulogic; +signal pc_mm_repr_sl_thold_3_oiu : std_ulogic; +signal pc_mm_sg_3_oiu : std_ulogic_vector(0 to 1); +signal pc_mm_time_sl_thold_3_oiu : std_ulogic; +signal pc_mm_trace_bus_enable_oiu : std_ulogic; +signal xu_ex2_flush_ofu : std_ulogic_vector(0 to 3); +signal xu_ex3_flush_ofu : std_ulogic_vector(0 to 3); +signal xu_ex4_flush_ofu : std_ulogic_vector(0 to 3); +signal xu_ex5_flush_ofu : std_ulogic_vector(0 to 3); +signal an_ac_lbist_ary_wrt_thru_dc_ofu : std_ulogic; +signal xu_pc_lsu_event_data_ofu : std_ulogic_vector(0 to 7); +signal xu_pc_err_mchk_disabled : std_ulogic; +signal xu_pc_err_mchk_disabled_ofu : std_ulogic; +signal xu_iu_l_flush : std_ulogic_vector(0 to 3); +signal xu_iu_u_flush : std_ulogic_vector(0 to 3); +signal debug_bus_out_int : std_ulogic_vector(0 to 7); +signal an_ac_grffence_en_dc_oiu : std_ulogic; +signal xu_fu_lbist_ary_wrt_thru_dc : std_ulogic; +signal pc_xu_msrovride_de : std_ulogic; + +signal bg_an_ac_func_scan_sn : std_ulogic_vector(60 to 69); +signal bg_an_ac_abst_scan_sn : std_ulogic_vector(10 to 11); +signal bg_an_ac_func_scan_sn_q : std_ulogic_vector(60 to 69); +signal bg_an_ac_abst_scan_sn_q : std_ulogic_vector(10 to 11); + +signal bg_ac_an_func_scan_ns : std_ulogic_vector(60 to 69); +signal bg_ac_an_abst_scan_ns : std_ulogic_vector(10 to 11); +signal bg_ac_an_func_scan_ns_q : std_ulogic_vector(60 to 69); +signal bg_ac_an_abst_scan_ns_q : std_ulogic_vector(10 to 11); + +signal bg_pc_l1p_abist_di_0 : std_ulogic_vector(0 to 3); +signal bg_pc_l1p_abist_g8t1p_renb_0 : std_ulogic; +signal bg_pc_l1p_abist_g8t_bw_0 : std_ulogic; +signal bg_pc_l1p_abist_g8t_bw_1 : std_ulogic; +signal bg_pc_l1p_abist_g8t_dcomp : std_ulogic_vector(0 to 3); +signal bg_pc_l1p_abist_g8t_wenb : std_ulogic; +signal bg_pc_l1p_abist_raddr_0 : std_ulogic_vector(0 to 9); +signal bg_pc_l1p_abist_waddr_0 : std_ulogic_vector(0 to 9); +signal bg_pc_l1p_abist_wl128_comp_ena : std_ulogic; +signal bg_pc_l1p_abist_wl32_comp_ena : std_ulogic; +signal bg_pc_l1p_abist_di_0_q : std_ulogic_vector(0 to 3); +signal bg_pc_l1p_abist_g8t1p_renb_0_q : std_ulogic; +signal bg_pc_l1p_abist_g8t_bw_0_q : std_ulogic; +signal bg_pc_l1p_abist_g8t_bw_1_q : std_ulogic; +signal bg_pc_l1p_abist_g8t_dcomp_q : std_ulogic_vector(0 to 3); +signal bg_pc_l1p_abist_g8t_wenb_q : std_ulogic; +signal bg_pc_l1p_abist_raddr_0_q : std_ulogic_vector(0 to 9); +signal bg_pc_l1p_abist_waddr_0_q : std_ulogic_vector(0 to 9); +signal bg_pc_l1p_abist_wl128_comp_ena_q : std_ulogic; +signal bg_pc_l1p_abist_wl32_comp_ena_q : std_ulogic; + +signal bg_pc_l1p_gptr_sl_thold_3 : std_ulogic; +signal bg_pc_l1p_time_sl_thold_3 : std_ulogic; +signal bg_pc_l1p_repr_sl_thold_3 : std_ulogic; +signal bg_pc_l1p_abst_sl_thold_3 : std_ulogic; +signal bg_pc_l1p_func_sl_thold_3 : std_ulogic_vector(0 to 1); +signal bg_pc_l1p_func_slp_sl_thold_3 : std_ulogic; +signal bg_pc_l1p_bolt_sl_thold_3 : std_ulogic; +signal bg_pc_l1p_ary_nsl_thold_3 : std_ulogic; +signal bg_pc_l1p_sg_3 : std_ulogic_vector(0 to 1); +signal bg_pc_l1p_fce_3 : std_ulogic; +signal bg_pc_l1p_bo_enable_3 : std_ulogic; +signal bg_pc_l1p_gptr_sl_thold_2 : std_ulogic; +signal bg_pc_l1p_time_sl_thold_2 : std_ulogic; +signal bg_pc_l1p_repr_sl_thold_2 : std_ulogic; +signal bg_pc_l1p_abst_sl_thold_2 : std_ulogic; +signal bg_pc_l1p_func_sl_thold_2 : std_ulogic_vector(0 to 1); +signal bg_pc_l1p_func_slp_sl_thold_2 : std_ulogic; +signal bg_pc_l1p_bolt_sl_thold_2 : std_ulogic; +signal bg_pc_l1p_ary_nsl_thold_2 : std_ulogic; +signal bg_pc_l1p_sg_2 : std_ulogic_vector(0 to 1); +signal bg_pc_l1p_fce_2 : std_ulogic; +signal bg_pc_l1p_bo_enable_2 : std_ulogic; + +signal bg_pc_bo_unload_iiu : std_ulogic; +signal bg_pc_bo_load_iiu : std_ulogic; +signal bg_pc_bo_repair_iiu : std_ulogic; +signal bg_pc_bo_reset_iiu : std_ulogic; +signal bg_pc_bo_shdata_iiu : std_ulogic; +signal bg_pc_bo_select_iiu : std_ulogic_vector(0 to 10); +signal bg_pc_l1p_ccflush_dc_iiu : std_ulogic; +signal bg_pc_l1p_abist_ena_dc_iiu : std_ulogic; +signal bg_pc_l1p_abist_raw_dc_b_iiu : std_ulogic; + +signal bg_pc_bo_unload_oiu : std_ulogic; +signal bg_pc_bo_load_oiu : std_ulogic; +signal bg_pc_bo_repair_oiu : std_ulogic; +signal bg_pc_bo_reset_oiu : std_ulogic; +signal bg_pc_bo_shdata_oiu : std_ulogic; +signal bg_pc_bo_select_oiu : std_ulogic_vector(0 to 10); +signal bg_pc_l1p_ccflush_dc_oiu : std_ulogic; +signal bg_pc_l1p_abist_ena_dc_oiu : std_ulogic; +signal bg_pc_l1p_abist_raw_dc_b_oiu : std_ulogic; + +signal bg_pc_bo_fail_oiu : std_ulogic_vector(0 to 10); +signal bg_pc_bo_diagout_oiu : std_ulogic_vector(0 to 10); + +-- MMU +signal bg_pc_l1p_gptr_sl_thold_2_imm : std_ulogic; +signal bg_pc_l1p_time_sl_thold_2_imm : std_ulogic; +signal bg_pc_l1p_repr_sl_thold_2_imm : std_ulogic; +signal bg_pc_l1p_abst_sl_thold_2_imm : std_ulogic; +signal bg_pc_l1p_func_sl_thold_2_imm : std_ulogic_vector(0 to 1); +signal bg_pc_l1p_func_slp_sl_thold_2_imm : std_ulogic; +signal bg_pc_l1p_bolt_sl_thold_2_imm : std_ulogic; +signal bg_pc_l1p_ary_nsl_thold_2_imm : std_ulogic; +signal bg_pc_l1p_sg_2_imm : std_ulogic_vector(0 to 1); +signal bg_pc_l1p_fce_2_imm : std_ulogic; +signal bg_pc_l1p_bo_enable_2_imm : std_ulogic; +signal bg_pc_bo_unload : std_ulogic; +signal bg_pc_bo_load : std_ulogic; +signal bg_pc_bo_repair : std_ulogic; +signal bg_pc_bo_reset : std_ulogic; +signal bg_pc_bo_shdata : std_ulogic; +signal bg_pc_bo_select : std_ulogic_vector(0 to 10); +signal bg_pc_l1p_ccflush_dc : std_ulogic; +signal bg_pc_l1p_abist_ena_dc : std_ulogic; +signal bg_pc_l1p_abist_raw_dc_b : std_ulogic; +signal bg_an_ac_func_scan_sn_omm : std_ulogic_vector(60 to 69); +signal bg_an_ac_abst_scan_sn_omm : std_ulogic_vector(10 to 11); +signal bg_pc_bo_fail : std_ulogic_vector(0 to 10); +signal bg_pc_bo_diagout : std_ulogic_vector(0 to 10); +signal bg_pc_bo_fail_omm : std_ulogic_vector(0 to 10); +signal bg_pc_bo_diagout_omm : std_ulogic_vector(0 to 10); + +signal xu_fu_lbist_en_dc : std_ulogic; +signal xu_iu_xucr4_mmu_mchk : std_ulogic; +signal xu_mm_xucr4_mmu_mchk : std_ulogic; + +-- synopsys translate_off + + +-- synopsys translate_on + + +BEGIN + + +debug_start_tiedowns <= (0 to 87 => '0'); +trigger_start_tiedowns <= (0 to 11 => '0'); + +ac_rp_trace_to_perfcntr <= debug_bus_out_int; +ac_an_debug_bus <= ac_an_debug_bus_int; + +ac_an_power_managed_imm <= ac_an_power_managed_int; + +a2_nclk_copy <= a2_nclk; + + +an_ac_bo_enable <= '0'; +an_ac_bo_go <= '0'; +an_ac_bo_cntlclk <= '0'; +an_ac_bo_ccflush <= '1'; +an_ac_bo_reset <= '0'; +an_ac_bo_data <= '0'; +an_ac_bo_shcntl <= '0'; +an_ac_bo_shdata <= '0'; +an_ac_bo_exe <= '0'; +an_ac_bo_sysrepair <= '0'; +an_ac_bo_donein <= '0'; +an_ac_bo_sdin <= '0'; +an_ac_bo_waitin <= '0'; +an_ac_bo_failin <= '0'; +an_ac_bo_fcshdata <= '0'; +an_ac_bo_fcreset <= '0'; + + bg_an_ac_func_scan_sn <= "0000000000"; -- in std_ulogic_vector(60 to 69); + bg_an_ac_abst_scan_sn <= "00"; -- in std_ulogic_vector(10 to 11); + bg_pc_l1p_gptr_sl_thold_3 <= '0'; + bg_pc_l1p_time_sl_thold_3 <= '0'; + bg_pc_l1p_repr_sl_thold_3 <= '0'; + bg_pc_l1p_abst_sl_thold_3 <= '0'; + bg_pc_l1p_func_sl_thold_3 <= "00"; -- in std_ulogic_vector(0 to 1); + bg_pc_l1p_func_slp_sl_thold_3 <= '0'; + bg_pc_l1p_bolt_sl_thold_3 <= '0'; + bg_pc_l1p_ary_nsl_thold_3 <= '0'; + bg_pc_l1p_sg_3 <= "00"; -- in std_ulogic_vector(0 to 1); + bg_pc_l1p_fce_3 <= '0'; + bg_pc_l1p_bo_enable_3 <= '0'; + bg_pc_bo_unload_iiu <= '0'; + bg_pc_bo_load_iiu <= '0'; + bg_pc_bo_repair_iiu <= '0'; + bg_pc_bo_reset_iiu <= '0'; + bg_pc_bo_shdata_iiu <= '0'; + bg_pc_bo_select_iiu <= "00000000000"; -- in std_ulogic_vector(0 to 10); + bg_pc_l1p_ccflush_dc_iiu <= '0'; + bg_pc_l1p_abist_ena_dc_iiu <= '0'; + bg_pc_l1p_abist_raw_dc_b_iiu <= '0'; + bg_pc_bo_fail <= "00000000000"; -- in std_ulogic_vector(0 to 10); + bg_pc_bo_diagout <= "00000000000"; -- in std_ulogic_vector(0 to 10); + + +spr_pvr_version_dc <= "01001000"; +spr_pvr_revision_dc <= "0010"; + + +a_fuq: entity work.fuq + generic map(expand_type => expand_type, eff_ifar => xu_eff_ifar, regmode => regmode) + port map ( + an_ac_abist_mode_dc => an_ac_abist_mode_dc_oiu, + an_ac_lbist_ary_wrt_thru_dc => xu_fu_lbist_ary_wrt_thru_dc, + an_ac_lbist_en_dc => xu_fu_lbist_en_dc, + pc_fu_ccflush_dc => pc_fu_ccflush_dc, + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b_opc, + an_ac_scan_diag_dc => an_ac_scan_diag_dc_opc, + abst_scan_in => rp_fu_abst_scan_in_q, + bcfg_scan_in => iu_fu_bcfg_scan_out, + ccfg_scan_in => xu_fu_ccfg_scan_out, + dcfg_scan_in => iu_fu_dcfg_scan_out, + func_scan_in => rp_fu_func_scan_in_q(0 to 3), + gptr_scan_in => pc_fu_gptr_scan_out, + repr_scan_in => iu_fu_repr_scan_out, + time_scan_in => iu_fu_time_scan_out, + --BX scan staging + bx_fu_rp_abst_scan_out => bx_fu_rp_abst_scan_out, + bx_rp_abst_scan_out => bx_rp_abst_scan_out, + rp_bx_abst_scan_in => rp_bx_abst_scan_in_q, + rp_fu_bx_abst_scan_in => rp_fu_bx_abst_scan_in, + rp_bx_func_scan_in => rp_bx_func_scan_in_q, + rp_fu_bx_func_scan_in => rp_fu_bx_func_scan_in, + bx_fu_rp_func_scan_out => bx_fu_rp_func_scan_out, + bx_rp_func_scan_out => bx_rp_func_scan_out, + debug_data_in => bx_fu_debug_data, + trace_triggers_in => bx_fu_trigger_data, + iu_fu_ex2_n_flush => iu_fu_ex2_n_flush, + iu_fu_is2_tid_decode => iu_fu_is2_tid_decode, + iu_fu_rf0_bypsel => iu_fu_rf0_bypsel, + iu_fu_rf0_fra => iu_fu_rf0_fra, + iu_fu_rf0_fra_v => iu_fu_rf0_fra_v, + iu_fu_rf0_frb => iu_fu_rf0_frb, + iu_fu_rf0_frb_v => iu_fu_rf0_frb_v, + iu_fu_rf0_frc => iu_fu_rf0_frc, + iu_fu_rf0_frc_v => iu_fu_rf0_frc_v, + iu_fu_rf0_frt => iu_fu_rf0_frt, + iu_fu_rf0_ifar => iu_fu_rf0_ifar, + iu_fu_rf0_instr => iu_fu_rf0_instr, + iu_fu_rf0_instr_match => iu_fu_rf0_instr_match, + iu_fu_rf0_instr_v => iu_fu_rf0_instr_v, + iu_fu_rf0_is_ucode => iu_fu_rf0_is_ucode, + iu_fu_rf0_ucfmul => iu_fu_rf0_ucfmul, + iu_fu_rf0_ldst_val => iu_fu_rf0_ldst_val, + iu_fu_rf0_ldst_tid => iu_fu_rf0_ldst_tid, + iu_fu_rf0_ldst_tag => iu_fu_rf0_ldst_tag, + iu_fu_rf0_str_val => iu_fu_rf0_str_val, + iu_fu_rf0_tid => iu_fu_rf0_tid, + nclk => a2_nclk, + pc_fu_abist_di_0 => pc_fu_abist_di_0(0 to 3), + pc_fu_abist_di_1 => pc_fu_abist_di_1(0 to 3), + pc_fu_abist_ena_dc => pc_fu_abist_ena_dc, + pc_fu_abist_grf_renb_0 => pc_fu_abist_grf_renb_0, + pc_fu_abist_grf_renb_1 => pc_fu_abist_grf_renb_1, + pc_fu_abist_grf_wenb_0 => pc_fu_abist_grf_wenb_0, + pc_fu_abist_grf_wenb_1 => pc_fu_abist_grf_wenb_1, + pc_fu_abist_raddr_0 => pc_fu_abist_raddr_0(0 to 9), + pc_fu_abist_raddr_1 => pc_fu_abist_raddr_1(0 to 9), + pc_fu_abist_raw_dc_b => pc_fu_abist_raw_dc_b, + pc_fu_abist_waddr_0 => pc_fu_abist_waddr_0(0 to 9), + pc_fu_abist_waddr_1 => pc_fu_abist_waddr_1(0 to 9), + pc_fu_abist_wl144_comp_ena => pc_fu_abist_wl144_comp_ena, + pc_fu_abst_sl_thold_3 => pc_fu_abst_sl_thold_3, + pc_fu_abst_slp_sl_thold_3 => pc_fu_abst_slp_sl_thold_3, + pc_fu_ary_nsl_thold_3 => pc_fu_ary_nsl_thold_3, + pc_fu_ary_slp_nsl_thold_3 => pc_fu_ary_slp_nsl_thold_3, + pc_fu_bolt_sl_thold_3 => pc_fu_bolt_sl_thold_3, + pc_fu_bo_enable_3 => pc_fu_bo_enable_3, + pc_fu_bo_unload => pc_fu_bo_unload, + pc_fu_bo_load => pc_fu_bo_load, + pc_fu_bo_reset => pc_fu_bo_reset, + pc_fu_bo_shdata => pc_fu_bo_shdata, + pc_fu_bo_select => pc_fu_bo_select, + pc_fu_cfg_sl_thold_3 => pc_fu_cfg_sl_thold_3, + pc_fu_cfg_slp_sl_thold_3 => pc_fu_cfg_slp_sl_thold_3, + pc_fu_debug_mux_ctrls => pc_fu_debug_mux1_ctrls, + pc_fu_event_mux_ctrls => pc_fu_event_mux_ctrls, + pc_fu_event_count_mode => pc_fu_event_count_mode, + pc_fu_fce_3 => pc_fu_fce_3, + pc_fu_func_nsl_thold_3 => pc_fu_func_nsl_thold_3, + pc_fu_func_sl_thold_3 => pc_fu_func_sl_thold_3, + pc_fu_func_slp_nsl_thold_3 => pc_fu_func_slp_nsl_thold_3, + pc_fu_func_slp_sl_thold_3 => pc_fu_func_slp_sl_thold_3, + pc_fu_gptr_sl_thold_3 => pc_fu_gptr_sl_thold_3, + pc_fu_inj_regfile_parity => pc_fu_inj_regfile_parity, + pc_fu_instr_trace_mode => pc_fu_instr_trace_mode, + pc_fu_instr_trace_tid => pc_fu_instr_trace_tid, + pc_fu_ram_mode => pc_fu_ram_mode, + pc_fu_ram_thread => pc_fu_ram_thread, + pc_fu_repr_sl_thold_3 => pc_fu_repr_sl_thold_3, + pc_fu_sg_3 => pc_fu_sg_3, + slowspr_addr_in => pc_fu_slowspr_addr, + slowspr_data_in => pc_fu_slowspr_data, + slowspr_done_in => pc_fu_slowspr_done, + slowspr_etid_in => pc_fu_slowspr_etid, + slowspr_rw_in => pc_fu_slowspr_rw, + slowspr_val_in => pc_fu_slowspr_val, + pc_fu_time_sl_thold_3 => pc_fu_time_sl_thold_3, + pc_fu_trace_bus_enable => pc_fu_trace_bus_enable, + pc_fu_event_bus_enable => pc_fu_event_bus_enable, + xu_ex1_flush => xu_n_ex1_flush, + xu_ex2_flush => xu_n_ex2_flush, + xu_ex3_flush => xu_n_ex3_flush, + xu_ex4_flush => xu_n_ex4_flush, + xu_ex5_flush => xu_n_ex5_flush, + xu_fu_ex3_eff_addr => xu_fu_ex3_eff_addr, + xu_fu_ex6_load_data => xu_fu_ex6_load_data(192 to 255), + xu_fu_ex5_load_le => xu_fu_ex5_load_le, + xu_fu_ex5_load_tag => xu_fu_ex5_load_tag, + xu_fu_ex5_load_val => xu_fu_ex5_load_val, + xu_fu_ex5_reload_val => xu_fu_ex5_reload_val, + xu_fu_msr_fp => xu_fu_msr_fp, + xu_fu_msr_pr => xu_fu_msr_pr, + xu_fu_msr_gs => xu_fu_msr_gs, + xu_fu_regfile_seq_beg => xu_fu_regfile_seq_beg, + xu_is2_flush => xu_n_is2_flush, + xu_rf0_flush => xu_n_rf0_flush, + xu_rf1_flush => xu_n_rf1_flush, + abst_scan_out => fu_rp_abst_scan_out, + bcfg_scan_out => fu_rp_bcfg_scan_out, + ccfg_scan_out => fu_rp_ccfg_scan_out, + dcfg_scan_out => fu_rp_dcfg_scan_out, + func_scan_out => fu_rp_func_scan_out(0 to 3), + gptr_scan_out => fu_bx_gptr_scan_out, + repr_scan_out => fu_bx_repr_scan_out, + time_scan_out => fu_bx_time_scan_out, + debug_data_out => fu_pc_debug_data, + trace_triggers_out => fu_pc_trigger_data, + fu_iu_uc_special => fu_iu_uc_special, + fu_pc_bo_fail => fu_pc_bo_fail, + fu_pc_bo_diagout => fu_pc_bo_diagout, + fu_pc_err_regfile_parity => fu_pc_err_regfile_parity, + fu_pc_err_regfile_ue => fu_pc_err_regfile_ue, + fu_pc_event_data => fu_pc_event_data, + fu_pc_ram_data => fu_pc_ram_data, + fu_pc_ram_done => fu_pc_ram_done, + fu_xu_ex1_ifar => fu_xu_ex1_ifar, + fu_xu_ex2_async_block => fu_xu_ex2_async_block, + fu_xu_ex2_ifar_val => fu_xu_ex2_ifar_val, + fu_xu_ex2_ifar_issued => fu_xu_ex2_ifar_issued, + fu_xu_ex2_store_data => fu_xu_ex2_store_data, + fu_xu_ex2_store_data_val => fu_xu_ex2_store_data_val, + fu_xu_ex3_flush2ucode => fu_xu_ex3_flush2ucode, + fu_xu_ex2_instr_match => fu_xu_ex2_instr_match, + fu_xu_ex2_instr_type => fu_xu_ex2_instr_type, + fu_xu_ex2_is_ucode => fu_xu_ex2_is_ucode, + fu_xu_ex3_ap_int_req => fu_xu_ex3_ap_int_req, + fu_xu_ex3_n_flush => fu_xu_ex3_n_flush, + fu_xu_ex3_np1_flush => fu_xu_ex3_np1_flush, + fu_xu_ex3_regfile_err_det => fu_xu_ex3_regfile_err_det, + fu_xu_ex3_trap => fu_xu_ex3_trap, + fu_xu_ex4_cr => fu_xu_ex4_cr, + fu_xu_ex4_cr_bf => fu_xu_ex4_cr_bf, + fu_xu_ex4_cr_noflush => fu_xu_ex4_cr_noflush, + fu_xu_ex4_cr_val => fu_xu_ex4_cr_val, + fu_xu_regfile_seq_end => fu_xu_regfile_seq_end, + fu_xu_rf1_act => fu_xu_rf1_act, + slowspr_addr_out => fu_bx_slowspr_addr, + slowspr_data_out => fu_bx_slowspr_data, + slowspr_done_out => fu_bx_slowspr_done, + slowspr_etid_out => fu_bx_slowspr_etid, + slowspr_rw_out => fu_bx_slowspr_rw, + slowspr_val_out => fu_bx_slowspr_val, + + -- Passthru signals for DD2, FU inputs + bx_pc_err_inbox_ue_ifu => bx_pc_err_inbox_ue, + bx_pc_err_outbox_ue_ifu => bx_pc_err_outbox_ue, + bx_pc_err_inbox_ecc_ifu => bx_pc_err_inbox_ecc, + bx_pc_err_outbox_ecc_ifu => bx_pc_err_outbox_ecc, + pc_bx_bolt_sl_thold_3_ifu => pc_bx_bolt_sl_thold_3, + pc_bx_bo_enable_3_ifu => pc_bx_bo_enable_3, + pc_bx_bo_unload_ifu => pc_bx_bo_unload, + pc_bx_bo_repair_ifu => pc_bx_bo_repair, + pc_bx_bo_reset_ifu => pc_bx_bo_reset, + pc_bx_bo_shdata_ifu => pc_bx_bo_shdata, + pc_bx_bo_select_ifu => pc_bx_bo_select, + bx_pc_bo_fail_ifu => bx_pc_bo_fail, + bx_pc_bo_diagout_ifu => bx_pc_bo_diagout, + pc_bx_abist_di_0_ifu => pc_bx_abist_di_0, + pc_bx_abist_ena_dc_ifu => pc_bx_abist_ena_dc, + pc_bx_abist_g8t1p_renb_0_ifu => pc_bx_abist_g8t1p_renb_0, + pc_bx_abist_g8t_bw_0_ifu => pc_bx_abist_g8t_bw_0, + pc_bx_abist_g8t_bw_1_ifu => pc_bx_abist_g8t_bw_1, + pc_bx_abist_g8t_dcomp_ifu => pc_bx_abist_g8t_dcomp, + pc_bx_abist_g8t_wenb_ifu => pc_bx_abist_g8t_wenb, + pc_bx_abist_raddr_0_ifu => pc_bx_abist_raddr_0(4 to 9), + pc_bx_abist_raw_dc_b_ifu => pc_bx_abist_raw_dc_b, + pc_bx_abist_waddr_0_ifu => pc_bx_abist_waddr_0(4 to 9), + pc_bx_abist_wl64_comp_ena_ifu => pc_bx_abist_wl64_comp_ena, + pc_bx_trace_bus_enable_ifu => pc_bx_trace_bus_enable, + pc_bx_debug_mux1_ctrls_ifu => pc_bx_debug_mux1_ctrls, + pc_bx_inj_inbox_ecc_ifu => pc_bx_inj_inbox_ecc, + pc_bx_inj_outbox_ecc_ifu => pc_bx_inj_outbox_ecc, + pc_bx_ccflush_dc_ifu => pc_bx_ccflush_dc, + pc_bx_sg_3_ifu => pc_bx_sg_3, + pc_bx_func_sl_thold_3_ifu => pc_bx_func_sl_thold_3, + pc_bx_func_slp_sl_thold_3_ifu => pc_bx_func_slp_sl_thold_3, + pc_bx_gptr_sl_thold_3_ifu => pc_bx_gptr_sl_thold_3, + pc_bx_time_sl_thold_3_ifu => pc_bx_time_sl_thold_3, + pc_bx_repr_sl_thold_3_ifu => pc_bx_repr_sl_thold_3, + pc_bx_abst_sl_thold_3_ifu => pc_bx_abst_sl_thold_3, + pc_bx_ary_nsl_thold_3_ifu => pc_bx_ary_nsl_thold_3, + pc_bx_ary_slp_nsl_thold_3_ifu => pc_bx_ary_slp_nsl_thold_3, + + xu_pc_err_mcsr_summary_ifu => xu_pc_err_mcsr_summary, + xu_pc_err_ierat_parity_ifu => xu_pc_err_ierat_parity, + xu_pc_err_derat_parity_ifu => xu_pc_err_derat_parity, + xu_pc_err_tlb_parity_ifu => xu_pc_err_tlb_parity, + xu_pc_err_tlb_lru_parity_ifu => xu_pc_err_tlb_lru_parity, + xu_pc_err_ierat_multihit_ifu => xu_pc_err_ierat_multihit, + xu_pc_err_derat_multihit_ifu => xu_pc_err_derat_multihit, + xu_pc_err_tlb_multihit_ifu => xu_pc_err_tlb_multihit, + xu_pc_err_ext_mchk_ifu => xu_pc_err_ext_mchk, + xu_pc_err_ditc_overrun_ifu => xu_pc_err_ditc_overrun, + xu_pc_err_local_snoop_reject_ifu => xu_pc_err_local_snoop_reject, + xu_pc_err_attention_instr_ifu => xu_pc_err_attention_instr, + xu_pc_err_dcache_parity_ifu => xu_pc_err_dcache_parity, + xu_pc_err_dcachedir_parity_ifu => xu_pc_err_dcachedir_parity, + xu_pc_err_dcachedir_multihit_ifu => xu_pc_err_dcachedir_multihit, + xu_pc_err_debug_event_ifu => xu_pc_err_debug_event, + xu_pc_err_invld_reld_ifu => xu_pc_err_invld_reld, + xu_pc_err_l2intrf_ecc_ifu => xu_pc_err_l2intrf_ecc, + xu_pc_err_l2intrf_ue_ifu => xu_pc_err_l2intrf_ue, + xu_pc_err_l2credit_overrun_ifu => xu_pc_err_l2credit_overrun, + xu_pc_err_llbust_attempt_ifu => xu_pc_err_llbust_attempt, + xu_pc_err_llbust_failed_ifu => xu_pc_err_llbust_failed, + xu_pc_err_nia_miscmpr_ifu => xu_pc_err_nia_miscmpr, + xu_pc_err_regfile_parity_ifu => xu_pc_err_regfile_parity, + xu_pc_err_regfile_ue_ifu => xu_pc_err_regfile_ue, + xu_pc_err_sprg_ecc_ifu => xu_pc_err_sprg_ecc, + xu_pc_err_sprg_ue_ifu => xu_pc_err_sprg_ue, + xu_pc_err_wdt_reset_ifu => xu_pc_err_wdt_reset, + xu_pc_event_data_ifu => xu_pc_event_data, + xu_pc_ram_data_ifu => xu_pc_ram_data, + xu_pc_ram_done_ifu => xu_pc_ram_done, + xu_pc_ram_interrupt_ifu => xu_pc_ram_interrupt, + xu_pc_running_ifu => xu_pc_running, + xu_pc_spr_ccr0_pme_ifu => xu_pc_spr_ccr0_pme, + xu_pc_spr_ccr0_we_ifu => xu_pc_spr_ccr0_we, + xu_pc_step_done_ifu => xu_pc_step_done, + xu_pc_stop_dbg_event_ifu => xu_pc_stop_dbg_event, + pc_xu_bolt_sl_thold_3_ifu => pc_xu_bolt_sl_thold_3, + pc_xu_bo_enable_3_ifu => pc_xu_bo_enable_3, + pc_xu_bo_unload_ifu => pc_xu_bo_unload, + pc_xu_bo_load_ifu => pc_xu_bo_load, + pc_xu_bo_repair_ifu => pc_xu_bo_repair, + pc_xu_bo_reset_ifu => pc_xu_bo_reset, + pc_xu_bo_shdata_ifu => pc_xu_bo_shdata, + pc_xu_bo_select_ifu => pc_xu_bo_select, + xu_pc_bo_fail_ifu => xu_pc_bo_fail, + xu_pc_bo_diagout_ifu => xu_pc_bo_diagout, + pc_xu_abist_dcomp_g6t_2r_ifu => pc_xu_abist_dcomp_g6t_2r, + pc_xu_abist_di_0_ifu => pc_xu_abist_di_0, + pc_xu_abist_di_1_ifu => pc_xu_abist_di_1, + pc_xu_abist_di_g6t_2r_ifu => pc_xu_abist_di_g6t_2r, + pc_xu_abist_ena_dc_ifu => pc_xu_abist_ena_dc, + pc_xu_abist_g6t_bw_ifu => pc_xu_abist_g6t_bw, + pc_xu_abist_g6t_r_wb_ifu => pc_xu_abist_g6t_r_wb, + pc_xu_abist_g8t1p_renb_0_ifu => pc_xu_abist_g8t1p_renb_0, + pc_xu_abist_g8t_bw_0_ifu => pc_xu_abist_g8t_bw_0, + pc_xu_abist_g8t_bw_1_ifu => pc_xu_abist_g8t_bw_1, + pc_xu_abist_g8t_dcomp_ifu => pc_xu_abist_g8t_dcomp, + pc_xu_abist_g8t_wenb_ifu => pc_xu_abist_g8t_wenb, + pc_xu_abist_grf_renb_0_ifu => pc_xu_abist_grf_renb_0, + pc_xu_abist_grf_renb_1_ifu => pc_xu_abist_grf_renb_1, + pc_xu_abist_grf_wenb_0_ifu => pc_xu_abist_grf_wenb_0, + pc_xu_abist_grf_wenb_1_ifu => pc_xu_abist_grf_wenb_1, + pc_xu_abist_raddr_0_ifu => pc_xu_abist_raddr_0, + pc_xu_abist_raddr_1_ifu => pc_xu_abist_raddr_1, + pc_xu_abist_raw_dc_b_ifu => pc_xu_abist_raw_dc_b, + pc_xu_abist_waddr_0_ifu => pc_xu_abist_waddr_0, + pc_xu_abist_waddr_1_ifu => pc_xu_abist_waddr_1, + pc_xu_abist_wl144_comp_ena_ifu => pc_xu_abist_wl144_comp_ena, + pc_xu_abist_wl32_comp_ena_ifu => pc_xu_abist_wl32_comp_ena, + pc_xu_abist_wl512_comp_ena_ifu => pc_xu_abist_wl512_comp_ena, + pc_xu_event_mux_ctrls_ifu => pc_xu_event_mux_ctrls, + pc_xu_lsu_event_mux_ctrls_ifu => pc_xu_lsu_event_mux_ctrls, + pc_xu_event_bus_enable_ifu => pc_xu_event_bus_enable, + pc_xu_abst_sl_thold_3_ifu => pc_xu_abst_sl_thold_3, + pc_xu_abst_slp_sl_thold_3_ifu => pc_xu_abst_slp_sl_thold_3, + pc_xu_regf_sl_thold_3_ifu => pc_xu_regf_sl_thold_3, + pc_xu_regf_slp_sl_thold_3_ifu => pc_xu_regf_slp_sl_thold_3, + pc_xu_ary_nsl_thold_3_ifu => pc_xu_ary_nsl_thold_3, + pc_xu_ary_slp_nsl_thold_3_ifu => pc_xu_ary_slp_nsl_thold_3, + pc_xu_cache_par_err_event_ifu => pc_xu_cache_par_err_event, + pc_xu_ccflush_dc_ifu => pc_xu_ccflush_dc, + pc_xu_cfg_sl_thold_3_ifu => pc_xu_cfg_sl_thold_3, + pc_xu_cfg_slp_sl_thold_3_ifu => pc_xu_cfg_slp_sl_thold_3, + pc_xu_dbg_action_ifu => pc_xu_dbg_action, + pc_xu_debug_mux1_ctrls_ifu => pc_xu_debug_mux1_ctrls, + pc_xu_debug_mux2_ctrls_ifu => pc_xu_debug_mux2_ctrls, + pc_xu_debug_mux3_ctrls_ifu => pc_xu_debug_mux3_ctrls, + pc_xu_debug_mux4_ctrls_ifu => pc_xu_debug_mux4_ctrls, + pc_xu_decrem_dis_on_stop_ifu => pc_xu_decrem_dis_on_stop, + pc_xu_event_count_mode_ifu => pc_xu_event_count_mode, + pc_xu_extirpts_dis_on_stop_ifu => pc_xu_extirpts_dis_on_stop, + pc_xu_fce_3_ifu => pc_xu_fce_3, + pc_xu_force_ude_ifu => pc_xu_force_ude, + pc_xu_func_nsl_thold_3_ifu => pc_xu_func_nsl_thold_3, + pc_xu_func_sl_thold_3_ifu => pc_xu_func_sl_thold_3, + pc_xu_func_slp_nsl_thold_3_ifu => pc_xu_func_slp_nsl_thold_3, + pc_xu_func_slp_sl_thold_3_ifu => pc_xu_func_slp_sl_thold_3, + pc_xu_gptr_sl_thold_3_ifu => pc_xu_gptr_sl_thold_3, + pc_xu_init_reset_ifu => pc_xu_init_reset, + pc_xu_inj_dcache_parity_ifu => pc_xu_inj_dcache_parity, + pc_xu_inj_dcachedir_parity_ifu => pc_xu_inj_dcachedir_parity, + pc_xu_inj_llbust_attempt_ifu => pc_xu_inj_llbust_attempt, + pc_xu_inj_llbust_failed_ifu => pc_xu_inj_llbust_failed, + pc_xu_inj_sprg_ecc_ifu => pc_xu_inj_sprg_ecc, + pc_xu_inj_regfile_parity_ifu => pc_xu_inj_regfile_parity, + pc_xu_inj_wdt_reset_ifu => pc_xu_inj_wdt_reset, + pc_xu_inj_dcachedir_multihit_ifu => pc_xu_inj_dcachedir_multihit, + pc_xu_instr_trace_mode_ifu => pc_xu_instr_trace_mode, + pc_xu_instr_trace_tid_ifu => pc_xu_instr_trace_tid, + pc_xu_msrovride_enab_ifu => pc_xu_msrovride_enab, + pc_xu_msrovride_gs_ifu => pc_xu_msrovride_gs, + pc_xu_msrovride_pr_ifu => pc_xu_msrovride_pr, + pc_xu_ram_execute_ifu => pc_xu_ram_execute, + pc_xu_ram_flush_thread_ifu => pc_xu_ram_flush_thread, + pc_xu_ram_mode_ifu => pc_xu_ram_mode, + pc_xu_ram_thread_ifu => pc_xu_ram_thread, + pc_xu_repr_sl_thold_3_ifu => pc_xu_repr_sl_thold_3, + pc_xu_reset_1_cmplt_ifu => pc_xu_reset_1_complete, + pc_xu_reset_2_cmplt_ifu => pc_xu_reset_2_complete, + pc_xu_reset_3_cmplt_ifu => pc_xu_reset_3_complete, + pc_xu_reset_wd_cmplt_ifu => pc_xu_reset_wd_complete, + pc_xu_sg_3_ifu => pc_xu_sg_3, + pc_xu_step_ifu => pc_xu_step, + pc_xu_stop_ifu => pc_xu_stop, + pc_xu_time_sl_thold_3_ifu => pc_xu_time_sl_thold_3, + pc_xu_timebase_dis_on_stop_ifu => pc_xu_timebase_dis_on_stop, + pc_xu_trace_bus_enable_ifu => pc_xu_trace_bus_enable, + + bx_pc_err_inbox_ue_ofu => bx_pc_err_inbox_ue_ofu , + bx_pc_err_outbox_ue_ofu => bx_pc_err_outbox_ue_ofu, + bx_pc_err_inbox_ecc_ofu => bx_pc_err_inbox_ecc_ofu, + bx_pc_err_outbox_ecc_ofu => bx_pc_err_outbox_ecc_ofu, + pc_bx_bolt_sl_thold_3_ofu => pc_bx_bolt_sl_thold_3_ofu, + pc_bx_bo_enable_3_ofu => pc_bx_bo_enable_3_ofu , + pc_bx_bo_unload_ofu => pc_bx_bo_unload_ofu , + pc_bx_bo_repair_ofu => pc_bx_bo_repair_ofu , + pc_bx_bo_reset_ofu => pc_bx_bo_reset_ofu , + pc_bx_bo_shdata_ofu => pc_bx_bo_shdata_ofu , + pc_bx_bo_select_ofu => pc_bx_bo_select_ofu , + bx_pc_bo_fail_ofu => bx_pc_bo_fail_ofu , + bx_pc_bo_diagout_ofu => bx_pc_bo_diagout_ofu , + pc_bx_abist_di_0_ofu => pc_bx_abist_di_0_ofu , + pc_bx_abist_ena_dc_ofu => pc_bx_abist_ena_dc_ofu , + pc_bx_abist_g8t1p_renb_0_ofu => pc_bx_abist_g8t1p_renb_0_ofu, + pc_bx_abist_g8t_bw_0_ofu => pc_bx_abist_g8t_bw_0_ofu, + pc_bx_abist_g8t_bw_1_ofu => pc_bx_abist_g8t_bw_1_ofu, + pc_bx_abist_g8t_dcomp_ofu => pc_bx_abist_g8t_dcomp_ofu, + pc_bx_abist_g8t_wenb_ofu => pc_bx_abist_g8t_wenb_ofu, + pc_bx_abist_raddr_0_ofu => pc_bx_abist_raddr_0_ofu, + pc_bx_abist_raw_dc_b_ofu => pc_bx_abist_raw_dc_b_ofu, + pc_bx_abist_waddr_0_ofu => pc_bx_abist_waddr_0_ofu, + pc_bx_abist_wl64_comp_ena_ofu => pc_bx_abist_wl64_comp_ena_ofu, + pc_bx_trace_bus_enable_ofu => pc_bx_trace_bus_enable_ofu, + pc_bx_debug_mux1_ctrls_ofu => pc_bx_debug_mux1_ctrls_ofu, + pc_bx_inj_inbox_ecc_ofu => pc_bx_inj_inbox_ecc_ofu, + pc_bx_inj_outbox_ecc_ofu => pc_bx_inj_outbox_ecc_ofu, + pc_bx_ccflush_dc_ofu => pc_bx_ccflush_dc_ofu , + pc_bx_sg_3_ofu => pc_bx_sg_3_ofu , + pc_bx_func_sl_thold_3_ofu => pc_bx_func_sl_thold_3_ofu, + pc_bx_func_slp_sl_thold_3_ofu => pc_bx_func_slp_sl_thold_3_ofu, + pc_bx_gptr_sl_thold_3_ofu => pc_bx_gptr_sl_thold_3_ofu, + pc_bx_time_sl_thold_3_ofu => pc_bx_time_sl_thold_3_ofu, + pc_bx_repr_sl_thold_3_ofu => pc_bx_repr_sl_thold_3_ofu, + pc_bx_abst_sl_thold_3_ofu => pc_bx_abst_sl_thold_3_ofu, + pc_bx_ary_nsl_thold_3_ofu => pc_bx_ary_nsl_thold_3_ofu, + pc_bx_ary_slp_nsl_thold_3_ofu => pc_bx_ary_slp_nsl_thold_3_ofu, + + xu_pc_err_mcsr_summary_ofu => xu_pc_err_mcsr_summary_ofu , + xu_pc_err_ierat_parity_ofu => xu_pc_err_ierat_parity_ofu , + xu_pc_err_derat_parity_ofu => xu_pc_err_derat_parity_ofu , + xu_pc_err_tlb_parity_ofu => xu_pc_err_tlb_parity_ofu , + xu_pc_err_tlb_lru_parity_ofu => xu_pc_err_tlb_lru_parity_ofu , + xu_pc_err_ierat_multihit_ofu => xu_pc_err_ierat_multihit_ofu , + xu_pc_err_derat_multihit_ofu => xu_pc_err_derat_multihit_ofu , + xu_pc_err_tlb_multihit_ofu => xu_pc_err_tlb_multihit_ofu , + xu_pc_err_ext_mchk_ofu => xu_pc_err_ext_mchk_ofu , + xu_pc_err_ditc_overrun_ofu => xu_pc_err_ditc_overrun_ofu , + xu_pc_err_local_snoop_reject_ofu => xu_pc_err_local_snoop_reject_ofu , + xu_pc_err_attention_instr_ofu => xu_pc_err_attention_instr_ofu , + xu_pc_err_dcache_parity_ofu => xu_pc_err_dcache_parity_ofu , + xu_pc_err_dcachedir_parity_ofu => xu_pc_err_dcachedir_parity_ofu , + xu_pc_err_dcachedir_multihit_ofu => xu_pc_err_dcachedir_multihit_ofu , + xu_pc_err_debug_event_ofu => xu_pc_err_debug_event_ofu , + xu_pc_err_invld_reld_ofu => xu_pc_err_invld_reld_ofu , + xu_pc_err_l2intrf_ecc_ofu => xu_pc_err_l2intrf_ecc_ofu , + xu_pc_err_l2intrf_ue_ofu => xu_pc_err_l2intrf_ue_ofu , + xu_pc_err_l2credit_overrun_ofu => xu_pc_err_l2credit_overrun_ofu , + xu_pc_err_llbust_attempt_ofu => xu_pc_err_llbust_attempt_ofu , + xu_pc_err_llbust_failed_ofu => xu_pc_err_llbust_failed_ofu , + xu_pc_err_nia_miscmpr_ofu => xu_pc_err_nia_miscmpr_ofu , + xu_pc_err_regfile_parity_ofu => xu_pc_err_regfile_parity_ofu , + xu_pc_err_regfile_ue_ofu => xu_pc_err_regfile_ue_ofu , + xu_pc_err_sprg_ecc_ofu => xu_pc_err_sprg_ecc_ofu , + xu_pc_err_sprg_ue_ofu => xu_pc_err_sprg_ue_ofu , + xu_pc_err_wdt_reset_ofu => xu_pc_err_wdt_reset_ofu , + xu_pc_event_data_ofu => xu_pc_event_data_ofu , + xu_pc_ram_data_ofu => xu_pc_ram_data_ofu , + xu_pc_ram_done_ofu => xu_pc_ram_done_ofu , + xu_pc_ram_interrupt_ofu => xu_pc_ram_interrupt_ofu , + xu_pc_running_ofu => xu_pc_running_ofu , + xu_pc_spr_ccr0_pme_ofu => xu_pc_spr_ccr0_pme_ofu , + xu_pc_spr_ccr0_we_ofu => xu_pc_spr_ccr0_we_ofu , + xu_pc_step_done_ofu => xu_pc_step_done_ofu , + xu_pc_stop_dbg_event_ofu => xu_pc_stop_dbg_event_ofu , + pc_xu_bolt_sl_thold_3_ofu => pc_xu_bolt_sl_thold_3_ofu , + pc_xu_bo_enable_3_ofu => pc_xu_bo_enable_3_ofu , + pc_xu_bo_unload_ofu => pc_xu_bo_unload_ofu , + pc_xu_bo_load_ofu => pc_xu_bo_load_ofu , + pc_xu_bo_repair_ofu => pc_xu_bo_repair_ofu , + pc_xu_bo_reset_ofu => pc_xu_bo_reset_ofu , + pc_xu_bo_shdata_ofu => pc_xu_bo_shdata_ofu , + pc_xu_bo_select_ofu => pc_xu_bo_select_ofu , + xu_pc_bo_fail_ofu => xu_pc_bo_fail_ofu , + xu_pc_bo_diagout_ofu => xu_pc_bo_diagout_ofu , + pc_xu_abist_dcomp_g6t_2r_ofu => pc_xu_abist_dcomp_g6t_2r_ofu , + pc_xu_abist_di_0_ofu => pc_xu_abist_di_0_ofu , + pc_xu_abist_di_1_ofu => pc_xu_abist_di_1_ofu , + pc_xu_abist_di_g6t_2r_ofu => pc_xu_abist_di_g6t_2r_ofu , + pc_xu_abist_ena_dc_ofu => pc_xu_abist_ena_dc_ofu , + pc_xu_abist_g6t_bw_ofu => pc_xu_abist_g6t_bw_ofu , + pc_xu_abist_g6t_r_wb_ofu => pc_xu_abist_g6t_r_wb_ofu , + pc_xu_abist_g8t1p_renb_0_ofu => pc_xu_abist_g8t1p_renb_0_ofu , + pc_xu_abist_g8t_bw_0_ofu => pc_xu_abist_g8t_bw_0_ofu , + pc_xu_abist_g8t_bw_1_ofu => pc_xu_abist_g8t_bw_1_ofu , + pc_xu_abist_g8t_dcomp_ofu => pc_xu_abist_g8t_dcomp_ofu , + pc_xu_abist_g8t_wenb_ofu => pc_xu_abist_g8t_wenb_ofu , + pc_xu_abist_grf_renb_0_ofu => pc_xu_abist_grf_renb_0_ofu , + pc_xu_abist_grf_renb_1_ofu => pc_xu_abist_grf_renb_1_ofu , + pc_xu_abist_grf_wenb_0_ofu => pc_xu_abist_grf_wenb_0_ofu , + pc_xu_abist_grf_wenb_1_ofu => pc_xu_abist_grf_wenb_1_ofu , + pc_xu_abist_raddr_0_ofu => pc_xu_abist_raddr_0_ofu , + pc_xu_abist_raddr_1_ofu => pc_xu_abist_raddr_1_ofu , + pc_xu_abist_raw_dc_b_ofu => pc_xu_abist_raw_dc_b_ofu , + pc_xu_abist_waddr_0_ofu => pc_xu_abist_waddr_0_ofu , + pc_xu_abist_waddr_1_ofu => pc_xu_abist_waddr_1_ofu , + pc_xu_abist_wl144_comp_ena_ofu => pc_xu_abist_wl144_comp_ena_ofu , + pc_xu_abist_wl32_comp_ena_ofu => pc_xu_abist_wl32_comp_ena_ofu , + pc_xu_abist_wl512_comp_ena_ofu => pc_xu_abist_wl512_comp_ena_ofu , + pc_xu_event_mux_ctrls_ofu => pc_xu_event_mux_ctrls_ofu , + pc_xu_lsu_event_mux_ctrls_ofu => pc_xu_lsu_event_mux_ctrls_ofu , + pc_xu_event_bus_enable_ofu => pc_xu_event_bus_enable_ofu , + pc_xu_abst_sl_thold_3_ofu => pc_xu_abst_sl_thold_3_ofu , + pc_xu_abst_slp_sl_thold_3_ofu => pc_xu_abst_slp_sl_thold_3_ofu , + pc_xu_regf_sl_thold_3_ofu => pc_xu_regf_sl_thold_3_ofu , + pc_xu_regf_slp_sl_thold_3_ofu => pc_xu_regf_slp_sl_thold_3_ofu , + pc_xu_ary_nsl_thold_3_ofu => pc_xu_ary_nsl_thold_3_ofu , + pc_xu_ary_slp_nsl_thold_3_ofu => pc_xu_ary_slp_nsl_thold_3_ofu , + pc_xu_cache_par_err_event_ofu => pc_xu_cache_par_err_event_ofu , + pc_xu_ccflush_dc_ofu => pc_xu_ccflush_dc_ofu , + pc_xu_cfg_sl_thold_3_ofu => pc_xu_cfg_sl_thold_3_ofu , + pc_xu_cfg_slp_sl_thold_3_ofu => pc_xu_cfg_slp_sl_thold_3_ofu , + pc_xu_dbg_action_ofu => pc_xu_dbg_action_ofu , + pc_xu_debug_mux1_ctrls_ofu => pc_xu_debug_mux1_ctrls_ofu , + pc_xu_debug_mux2_ctrls_ofu => pc_xu_debug_mux2_ctrls_ofu , + pc_xu_debug_mux3_ctrls_ofu => pc_xu_debug_mux3_ctrls_ofu , + pc_xu_debug_mux4_ctrls_ofu => pc_xu_debug_mux4_ctrls_ofu , + pc_xu_decrem_dis_on_stop_ofu => pc_xu_decrem_dis_on_stop_ofu , + pc_xu_event_count_mode_ofu => pc_xu_event_count_mode_ofu , + pc_xu_extirpts_dis_on_stop_ofu => pc_xu_extirpts_dis_on_stop_ofu , + pc_xu_fce_3_ofu => pc_xu_fce_3_ofu , + pc_xu_force_ude_ofu => pc_xu_force_ude_ofu , + pc_xu_func_nsl_thold_3_ofu => pc_xu_func_nsl_thold_3_ofu , + pc_xu_func_sl_thold_3_ofu => pc_xu_func_sl_thold_3_ofu , + pc_xu_func_slp_nsl_thold_3_ofu => pc_xu_func_slp_nsl_thold_3_ofu , + pc_xu_func_slp_sl_thold_3_ofu => pc_xu_func_slp_sl_thold_3_ofu , + pc_xu_gptr_sl_thold_3_ofu => pc_xu_gptr_sl_thold_3_ofu , + pc_xu_init_reset_ofu => pc_xu_init_reset_ofu , + pc_xu_inj_dcache_parity_ofu => pc_xu_inj_dcache_parity_ofu , + pc_xu_inj_dcachedir_parity_ofu => pc_xu_inj_dcachedir_parity_ofu , + pc_xu_inj_llbust_attempt_ofu => pc_xu_inj_llbust_attempt_ofu , + pc_xu_inj_llbust_failed_ofu => pc_xu_inj_llbust_failed_ofu , + pc_xu_inj_sprg_ecc_ofu => pc_xu_inj_sprg_ecc_ofu , + pc_xu_inj_regfile_parity_ofu => pc_xu_inj_regfile_parity_ofu , + pc_xu_inj_wdt_reset_ofu => pc_xu_inj_wdt_reset_ofu , + pc_xu_inj_dcachedir_multihit_ofu => pc_xu_inj_dcachedir_multihit_ofu, + pc_xu_instr_trace_mode_ofu => pc_xu_instr_trace_mode_ofu , + pc_xu_instr_trace_tid_ofu => pc_xu_instr_trace_tid_ofu , + pc_xu_msrovride_enab_ofu => pc_xu_msrovride_enab_ofu , + pc_xu_msrovride_gs_ofu => pc_xu_msrovride_gs_ofu , + pc_xu_msrovride_pr_ofu => pc_xu_msrovride_pr_ofu , + pc_xu_ram_execute_ofu => pc_xu_ram_execute_ofu , + pc_xu_ram_flush_thread_ofu => pc_xu_ram_flush_thread_ofu , + pc_xu_ram_mode_ofu => pc_xu_ram_mode_ofu , + pc_xu_ram_thread_ofu => pc_xu_ram_thread_ofu , + pc_xu_repr_sl_thold_3_ofu => pc_xu_repr_sl_thold_3_ofu , + pc_xu_reset_1_cmplt_ofu => pc_xu_reset_1_cmplt_ofu , + pc_xu_reset_2_cmplt_ofu => pc_xu_reset_2_cmplt_ofu , + pc_xu_reset_3_cmplt_ofu => pc_xu_reset_3_cmplt_ofu , + pc_xu_reset_wd_cmplt_ofu => pc_xu_reset_wd_cmplt_ofu , + pc_xu_sg_3_ofu => pc_xu_sg_3_ofu , + pc_xu_step_ofu => pc_xu_step_ofu , + pc_xu_stop_ofu => pc_xu_stop_ofu , + pc_xu_time_sl_thold_3_ofu => pc_xu_time_sl_thold_3_ofu , + pc_xu_timebase_dis_on_stop_ofu => pc_xu_timebase_dis_on_stop_ofu , + pc_xu_trace_bus_enable_ofu => pc_xu_trace_bus_enable_ofu , + an_ac_scan_dis_dc_b_ofu => an_ac_scan_dis_dc_b_ofu, + an_ac_scan_diag_dc_ofu => an_ac_scan_diag_dc_ofu, + + xu_ex2_flush_ofu => xu_ex2_flush_ofu, + xu_ex3_flush_ofu => xu_ex3_flush_ofu, + xu_ex4_flush_ofu => xu_ex4_flush_ofu, + xu_ex5_flush_ofu => xu_ex5_flush_ofu, + an_ac_lbist_ary_wrt_thru_dc_ofu => an_ac_lbist_ary_wrt_thru_dc_ofu, + + xu_pc_err_mchk_disabled_ifu => xu_pc_err_mchk_disabled, + xu_pc_lsu_event_data_ifu => xu_pc_lsu_event_data, + xu_pc_err_mchk_disabled_ofu => xu_pc_err_mchk_disabled_ofu, + xu_pc_lsu_event_data_ofu => xu_pc_lsu_event_data_ofu, + + gnd => gnd, + vdd => vdd + ); -- end component a_fuq + +a_iuq: entity work.iuq + generic map(expand_type => expand_type, + bcfg_epn_0to15 => bcfg_epn_0to15, + bcfg_epn_16to31 => bcfg_epn_16to31, + bcfg_epn_32to47 => bcfg_epn_32to47, + bcfg_epn_48to51 => bcfg_epn_48to51, + bcfg_rpn_22to31 => bcfg_rpn_22to31, + bcfg_rpn_32to47 => bcfg_rpn_32to47, + bcfg_rpn_48to51 => bcfg_rpn_48to51, + fpr_addr_width => fpr_addr_width, + lmq_entries => lmq_entries, + regmode => regmode, + threads => threads, + ucode_mode => ucode_mode) + port map ( + abst_scan_in => an_ac_abst_scan_in_omm_iu(0 to 2), + bcfg_scan_in => an_ac_bcfg_scan_in_omm_bit3, + ccfg_scan_in => mm_iu_ccfg_scan_out, + dcfg_scan_in => an_ac_dcfg_scan_in_omm(1), + func_scan_in => an_ac_func_scan_in_omm_iua(6 to 19), + gptr_scan_in => an_ac_gptr_scan_in_omm, + repr_scan_in => an_ac_repr_scan_in_omm, + time_scan_in => an_ac_time_scan_in_omm, + regf_scan_in => an_ac_regf_scan_in_omm(0 to 4), + debug_data_in => pc_iu_debug_data, + trace_triggers_in => pc_iu_trigger_data, + an_ac_back_inv => an_ac_back_inv_omm, + an_ac_back_inv_addr => an_ac_back_inv_addr_omm(real_ifar'left to 63), + an_ac_back_inv_target_iiu_a => an_ac_back_inv_target_omm_iua, + an_ac_back_inv_target_iiu_b => an_ac_back_inv_target_omm_iub, + an_ac_grffence_en_dc => an_ac_camfence_en_dc_omm, + an_ac_icbi_ack => an_ac_icbi_ack_omm, + an_ac_icbi_ack_thread => an_ac_icbi_ack_thread_omm, + an_ac_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc_omm, + an_ac_reld_core_tag => xu_iu_reld_core_tag, + an_ac_reld_data => xu_iu_reld_data, + an_ac_reld_data_vld => xu_iu_reld_data_vld, + an_ac_reld_data_coming_clone => xu_iu_reld_data_coming_clone, + an_ac_reld_ditc_clone => xu_iu_reld_ditc_clone, + an_ac_reld_ecc_err => xu_iu_reld_ecc_err, + an_ac_reld_ecc_err_ue => xu_iu_reld_ecc_err_ue, + an_ac_reld_qw => xu_iu_reld_qw, + an_ac_reld_data_vld_clone => xu_iu_reld_data_vld_clone, + an_ac_reld_core_tag_clone => xu_iu_reld_core_tag_clone, + an_ac_scan_diag_dc => an_ac_scan_diag_dc_omm, + an_ac_stcx_complete => xu_iu_stcx_complete, + an_ac_sync_ack => an_ac_sync_ack_omm, + fu_iu_uc_special => fu_iu_uc_special, + mm_iu_ierat_mmucr0_0 => mm_iu_ierat_mmucr0_0, + mm_iu_ierat_mmucr0_1 => mm_iu_ierat_mmucr0_1, + mm_iu_ierat_mmucr0_2 => mm_iu_ierat_mmucr0_2, + mm_iu_ierat_mmucr0_3 => mm_iu_ierat_mmucr0_3, + mm_iu_ierat_mmucr1 => mm_iu_ierat_mmucr1, + mm_iu_ierat_pid0 => mm_iu_ierat_pid0, + mm_iu_ierat_pid1 => mm_iu_ierat_pid1, + mm_iu_ierat_pid2 => mm_iu_ierat_pid2, + mm_iu_ierat_pid3 => mm_iu_ierat_pid3, + mm_iu_ierat_rel_data => mm_iu_ierat_rel_data, + mm_iu_ierat_rel_val => mm_iu_ierat_rel_val, + mm_iu_ierat_snoop_attr => mm_iu_ierat_snoop_attr, + mm_iu_ierat_snoop_coming => mm_iu_ierat_snoop_coming, + mm_iu_ierat_snoop_val => mm_iu_ierat_snoop_val, + mm_iu_ierat_snoop_vpn => mm_iu_ierat_snoop_vpn, + slowspr_addr_in => mm_iu_slowspr_addr, + slowspr_data_in => mm_iu_slowspr_data, + slowspr_done_in => mm_iu_slowspr_done, + slowspr_etid_in => mm_iu_slowspr_etid, + slowspr_rw_in => mm_iu_slowspr_rw, + slowspr_val_in => mm_iu_slowspr_val, + nclk => a2_nclk, + pc_iu_abist_dcomp_g6t_2r => pc_iu_abist_dcomp_g6t_2r(0 to 3), + pc_iu_abist_di_0 => pc_iu_abist_di_0(0 to 3), + pc_iu_abist_di_g6t_2r => pc_iu_abist_di_g6t_2r(0 to 3), + pc_iu_abist_ena_dc => pc_iu_abist_ena_dc, + pc_iu_abist_g6t_bw => pc_iu_abist_g6t_bw(0 to 1), + pc_iu_abist_g6t_r_wb => pc_iu_abist_g6t_r_wb, + pc_iu_abist_g8t1p_renb_0 => pc_iu_abist_g8t1p_renb_0, + pc_iu_abist_g8t_bw_0 => pc_iu_abist_g8t_bw_0, + pc_iu_abist_g8t_bw_1 => pc_iu_abist_g8t_bw_1, + pc_iu_abist_g8t_dcomp => pc_iu_abist_g8t_dcomp(0 to 3), + pc_iu_abist_g8t_wenb => pc_iu_abist_g8t_wenb, + pc_iu_abist_raddr_0 => pc_iu_abist_raddr_0(0 to 9), + pc_iu_abist_raw_dc_b => pc_iu_abist_raw_dc_b, + pc_iu_abist_waddr_0 => pc_iu_abist_waddr_0(0 to 9), + pc_iu_abist_wl128_comp_ena => pc_iu_abist_wl128_comp_ena, + pc_iu_abist_wl256_comp_ena => pc_iu_abist_wl256_comp_ena, + pc_iu_abist_wl64_comp_ena => pc_iu_abist_wl64_comp_ena, + pc_iu_bo_enable_4 => pc_iu_bo_enable_4, + pc_iu_bo_reset => pc_iu_bo_reset, + pc_iu_bo_unload => pc_iu_bo_unload, + pc_iu_bo_repair => pc_iu_bo_repair, + pc_iu_bo_shdata => pc_iu_bo_shdata, + pc_iu_bo_select => pc_iu_bo_select, + pc_iu_debug_mux1_ctrls => pc_iu_debug_mux1_ctrls, + pc_iu_debug_mux2_ctrls => pc_iu_debug_mux2_ctrls, + pc_iu_event_bus_enable => pc_iu_event_bus_enable, + pc_iu_event_count_mode => pc_iu_event_count_mode, + pc_iu_event_mux_ctrls => pc_iu_event_mux_ctrls, + pc_iu_gptr_sl_thold_4 => pc_iu_gptr_sl_thold_4, + pc_iu_time_sl_thold_4 => pc_iu_time_sl_thold_4, + pc_iu_repr_sl_thold_4 => pc_iu_repr_sl_thold_4, + pc_iu_abst_sl_thold_4 => pc_iu_abst_sl_thold_4, + pc_iu_abst_slp_sl_thold_4 => pc_iu_abst_slp_sl_thold_4, + pc_iu_bolt_sl_thold_4 => pc_iu_bolt_sl_thold_4, + pc_iu_regf_slp_sl_thold_4 => pc_iu_regf_slp_sl_thold_4, + pc_iu_func_sl_thold_4 => pc_iu_func_sl_thold_4, + pc_iu_func_slp_sl_thold_4 => pc_iu_func_slp_sl_thold_4, + pc_iu_cfg_sl_thold_4 => pc_iu_cfg_sl_thold_4, + pc_iu_cfg_slp_sl_thold_4 => pc_iu_cfg_slp_sl_thold_4, + pc_iu_func_nsl_thold_4 => pc_iu_func_nsl_thold_4, + pc_iu_func_slp_nsl_thold_4 => pc_iu_func_slp_nsl_thold_4, + pc_iu_ary_nsl_thold_4 => pc_iu_ary_nsl_thold_4, + pc_iu_ary_slp_nsl_thold_4 => pc_iu_ary_slp_nsl_thold_4, + pc_iu_sg_4 => pc_iu_sg_4, + pc_iu_fce_4 => pc_iu_fce_4, + pc_iu_init_reset => pc_iu_init_reset, + pc_iu_inj_icache_parity => pc_iu_inj_icache_parity, + pc_iu_inj_icachedir_multihit => pc_iu_inj_icachedir_multihit, + pc_iu_inj_icachedir_parity => pc_iu_inj_icachedir_parity, + pc_iu_ram_force_cmplt => pc_iu_ram_force_cmplt, + pc_iu_ram_instr => pc_iu_ram_instr, + pc_iu_ram_instr_ext => pc_iu_ram_instr_ext, + pc_iu_ram_mode => pc_iu_ram_mode, + pc_iu_ram_thread => pc_iu_ram_thread, + pc_iu_trace_bus_enable => pc_iu_trace_bus_enable, + tc_ac_ccflush_dc => pc_iu_ccflush_dc, + an_ac_lbist_en_dc => an_ac_lbist_en_dc_omm, + an_ac_atpg_en_dc => an_ac_atpg_en_dc_omm, + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b_omm, + xu_iu_complete_qentry => xu_iu_complete_qentry, + xu_iu_complete_target_type => xu_iu_complete_target_type, + xu_iu_complete_tid => xu_iu_complete_tid, + xu_iu_ex1_ra_entry => xu_iu_ex1_ra_entry, + xu_iu_ex1_rb => xu_iu_ex1_rb, + xu_iu_ex1_rs_is => xu_iu_ex1_rs_is, + xu_iu_ex5_bclr => xu_iu_ex5_bclr, + xu_iu_ex5_bh => xu_iu_ex5_bh, + xu_iu_ex5_br_hist => xu_iu_ex5_br_hist, + xu_iu_ex5_br_taken => xu_iu_ex5_br_taken, + xu_iu_ex5_br_update => xu_iu_ex5_br_update, + xu_iu_ex5_getNIA => xu_iu_ex5_getNIA, + xu_iu_ex5_gshare => xu_iu_ex5_gshare, + xu_iu_ex5_ifar => xu_iu_ex5_ifar, + xu_iu_ex5_lk => xu_iu_ex5_lk, + xu_iu_ex5_ppc_cpl => xu_iu_ex5_ppc_cpl, + xu_iu_ex4_loadmiss_qentry => xu_iu_ex4_loadmiss_qentry, + xu_iu_ex4_loadmiss_target => xu_iu_ex4_loadmiss_target, + xu_iu_ex4_loadmiss_target_type=> xu_iu_ex4_loadmiss_target_type, + xu_iu_ex4_loadmiss_tid => xu_iu_ex4_loadmiss_tid, + xu_iu_ex4_rs_data => xu_iu_ex4_rs_data, + xu_iu_ex5_tid => xu_iu_ex5_tid, + xu_iu_ex5_val => xu_iu_ex5_val, + xu_iu_ex5_loadmiss_qentry => xu_iu_ex5_loadmiss_qentry, + xu_iu_ex5_loadmiss_target => xu_iu_ex5_loadmiss_target, + xu_iu_ex5_loadmiss_target_type=> xu_iu_ex5_loadmiss_target_type, + xu_iu_ex5_loadmiss_tid => xu_iu_ex5_loadmiss_tid, + xu_iu_ex6_icbi_val => xu_iu_ex6_icbi_val, + xu_iu_ex6_icbi_addr => xu_iu_ex6_icbi_addr, + xu_iu_ex6_pri => xu_iu_ex6_pri, + xu_iu_ex6_pri_val => xu_iu_ex6_pri_val, + xu_iu_flush_2ucode => xu_iu_flush_2ucode, + xu_iu_flush_2ucode_type => xu_iu_flush_2ucode_type, + xu_iu_hid_mmu_mode => xu_iu_hid_mmu_mode, + xu_iu_xucr0_rel => xu_iu_xucr0_rel, + xu_iu_ici => xu_iu_ici, + xu_iu_iu0_flush_ifar0 => xu_iu_iu0_flush_ifar0, + xu_iu_iu0_flush_ifar1 => xu_iu_iu0_flush_ifar1, + xu_iu_iu0_flush_ifar2 => xu_iu_iu0_flush_ifar2, + xu_iu_iu0_flush_ifar3 => xu_iu_iu0_flush_ifar3, + xu_iu_larx_done_tid => xu_iu_larx_done_tid, + xu_iu_membar_tid => xu_iu_membar_tid, + xu_iu_msr_cm => xu_iu_msr_cm, + xu_iu_msr_gs => xu_iu_msr_gs, + xu_iu_msr_hv => xu_iu_msr_hv, + xu_iu_msr_is => xu_iu_msr_is, + xu_iu_msr_pr => xu_iu_msr_pr, + xu_iu_multdiv_done => xu_iu_multdiv_done, + xu_iu_need_hole => xu_iu_need_hole, + xu_iu_raise_iss_pri => xu_iu_raise_iss_pri, + xu_iu_ram_issue => xu_iu_ram_issue, + xu_iu_ex1_is_csync => xu_iu_ex1_is_csync, + xu_iu_ex1_is_isync => xu_iu_ex1_is_isync, + xu_iu_rf1_is_eratilx => xu_iu_rf1_is_eratilx, + xu_iu_rf1_is_eratre => xu_iu_rf1_is_eratre, + xu_iu_rf1_is_eratsx => xu_iu_rf1_is_eratsx, + xu_iu_rf1_is_eratwe => xu_iu_rf1_is_eratwe, + xu_iu_rf1_val => xu_iu_rf1_val, + xu_iu_rf1_ws => xu_iu_rf1_ws, + xu_iu_rf1_t => xu_iu_rf1_t, + xu_iu_run_thread => xu_iu_run_thread, + xu_iu_set_barr_tid => xu_iu_set_barr_tid, + xu_iu_single_instr_mode => xu_iu_single_instr_mode, + xu_iu_slowspr_done => xu_iu_slowspr_done, + xu_iu_spr_ccr2_en_dcr => xu_iu_spr_ccr2_en_dcr, + xu_iu_spr_ccr2_ifratsc => xu_iu_spr_ccr2_ifratsc, + xu_iu_spr_ccr2_ifrat => xu_iu_spr_ccr2_ifrat, + xu_iu_spr_xer0 => xu_iu_spr_xer0, + xu_iu_spr_xer1 => xu_iu_spr_xer1, + xu_iu_spr_xer2 => xu_iu_spr_xer2, + xu_iu_spr_xer3 => xu_iu_spr_xer3, + xu_iu_uc_flush_ifar0 => xu_iu_uc_flush_ifar0, + xu_iu_uc_flush_ifar1 => xu_iu_uc_flush_ifar1, + xu_iu_uc_flush_ifar2 => xu_iu_uc_flush_ifar2, + xu_iu_uc_flush_ifar3 => xu_iu_uc_flush_ifar3, + xu_iu_ucode_restart => xu_iu_ucode_restart, + abst_scan_out(0 to 1) => ac_an_abst_scan_out_imm_iu(0 to 1), + abst_scan_out(2) => iu_pc_abst_scan_out, + bcfg_scan_out => iu_fu_bcfg_scan_out, + ccfg_scan_out => iu_pc_ccfg_scan_out, + dcfg_scan_out => iu_fu_dcfg_scan_out, + func_scan_out => ac_an_func_scan_out_imm_iua(6 to 19), + gptr_scan_out => iu_pc_gptr_scan_out, + repr_scan_out => iu_fu_repr_scan_out, + time_scan_out => iu_fu_time_scan_out, + regf_scan_out => ac_an_regf_scan_out_imm(0 to 4), + debug_data_out => iu_xu_debug_data, + trace_triggers_out => iu_xu_trigger_data, + iu_fu_ex2_n_flush => iu_fu_ex2_n_flush, + iu_fu_is2_tid_decode => iu_fu_is2_tid_decode, + iu_fu_rf0_bypsel => iu_fu_rf0_bypsel, + iu_fu_rf0_fra => iu_fu_rf0_fra, + iu_fu_rf0_fra_v => iu_fu_rf0_fra_v, + iu_fu_rf0_frb => iu_fu_rf0_frb, + iu_fu_rf0_frb_v => iu_fu_rf0_frb_v, + iu_fu_rf0_frc => iu_fu_rf0_frc, + iu_fu_rf0_frc_v => iu_fu_rf0_frc_v, + iu_fu_rf0_frt => iu_fu_rf0_frt, + iu_fu_rf0_ifar => iu_fu_rf0_ifar, + iu_fu_rf0_instr => iu_fu_rf0_instr, + iu_fu_rf0_instr_match => iu_fu_rf0_instr_match, + iu_fu_rf0_instr_v => iu_fu_rf0_instr_v, + iu_fu_rf0_is_ucode => iu_fu_rf0_is_ucode, + iu_fu_rf0_ucfmul => iu_fu_rf0_ucfmul, + iu_fu_rf0_ldst_val => iu_fu_rf0_ldst_val, + iu_fu_rf0_ldst_tid => iu_fu_rf0_ldst_tid, + iu_fu_rf0_ldst_tag => iu_fu_rf0_ldst_tag, + iu_fu_rf0_str_val => iu_fu_rf0_str_val, + iu_fu_rf0_tid => iu_fu_rf0_tid, + iu_mm_ierat_epn => iu_mm_ierat_epn, + iu_mm_ierat_flush => iu_mm_ierat_flush, + iu_mm_ierat_mmucr0 => iu_mm_ierat_mmucr0, + iu_mm_ierat_mmucr0_we => iu_mm_ierat_mmucr0_we, + iu_mm_ierat_mmucr1 => iu_mm_ierat_mmucr1, + iu_mm_ierat_mmucr1_we => iu_mm_ierat_mmucr1_we, + iu_mm_ierat_req => iu_mm_ierat_req, + iu_mm_ierat_snoop_ack => iu_mm_ierat_snoop_ack, + iu_mm_ierat_thdid => iu_mm_ierat_thdid, + iu_mm_ierat_tid => iu_mm_ierat_tid, + iu_mm_ierat_state => iu_mm_ierat_state, + iu_mm_lmq_empty => iu_mm_lmq_empty, + mm_iu_barrier_done => mm_iu_barrier_done, + iu_pc_bo_fail => iu_pc_bo_fail, + iu_pc_bo_diagout => iu_pc_bo_diagout, + iu_pc_err_icache_parity => iu_pc_err_icache_parity, + iu_pc_err_icachedir_multihit => iu_pc_err_icachedir_multihit, + iu_pc_err_icachedir_parity => iu_pc_err_icachedir_parity, + iu_pc_err_ucode_illegal => iu_pc_err_ucode_illegal, + iu_pc_event_data => iu_pc_event_data, + slowspr_addr_out => iu_pc_slowspr_addr, + slowspr_data_out => iu_pc_slowspr_data, + slowspr_done_out => iu_pc_slowspr_done, + slowspr_etid_out => iu_pc_slowspr_etid, + slowspr_rw_out => iu_pc_slowspr_rw, + slowspr_val_out => iu_pc_slowspr_val, + iu_xu_ex4_tlb_data => iu_xu_ex4_tlb_data, + iu_xu_ierat_ex2_flush_req => iu_xu_ierat_ex2_flush_req, + iu_xu_ierat_ex3_par_err => iu_xu_ierat_ex3_par_err, + iu_xu_ierat_ex4_par_err => iu_xu_ierat_ex4_par_err, + iu_xu_is2_axu_instr_type => iu_xu_is2_axu_instr_type, + iu_xu_is2_axu_ld_or_st => iu_xu_is2_axu_ld_or_st, + iu_xu_is2_axu_ldst_extpid => iu_xu_is2_axu_ldst_extpid, + iu_xu_is2_axu_ldst_forcealign => iu_xu_is2_axu_ldst_forcealign, + iu_xu_is2_axu_ldst_forceexcept => iu_xu_is2_axu_ldst_forceexcept, + iu_xu_is2_axu_ldst_indexed => iu_xu_is2_axu_ldst_indexed, + iu_xu_is2_axu_ldst_size => iu_xu_is2_axu_ldst_size, + iu_xu_is2_axu_ldst_tag => iu_xu_is2_axu_ldst_tag, + iu_xu_is2_axu_ldst_update => iu_xu_is2_axu_ldst_update, + iu_xu_is2_axu_mffgpr => iu_xu_is2_axu_mffgpr, + iu_xu_is2_axu_mftgpr => iu_xu_is2_axu_mftgpr, + iu_xu_is2_axu_movedp => iu_xu_is2_axu_movedp, + iu_xu_is2_axu_store => iu_xu_is2_axu_store, + iu_xu_is2_error => iu_xu_is2_error, + iu_xu_is2_gshare => iu_xu_is2_gshare, + iu_xu_is2_ifar => iu_xu_is2_ifar, + iu_xu_is2_instr => iu_xu_is2_instr, + iu_xu_is2_is_ucode => iu_xu_is2_is_ucode, + iu_xu_is2_match => iu_xu_is2_match, + iu_xu_is2_pred_taken_cnt => iu_xu_is2_pred_taken_cnt, + iu_xu_is2_pred_update => iu_xu_is2_pred_update, + iu_xu_is2_s1 => iu_xu_is2_s1, + iu_xu_is2_s1_vld => iu_xu_is2_s1_vld, + iu_xu_is2_s2 => iu_xu_is2_s2, + iu_xu_is2_s2_vld => iu_xu_is2_s2_vld, + iu_xu_is2_s3 => iu_xu_is2_s3, + iu_xu_is2_s3_vld => iu_xu_is2_s3_vld, + iu_xu_is2_ta => iu_xu_is2_ta, + iu_xu_is2_ta_vld => iu_xu_is2_ta_vld, + iu_xu_is2_tid => iu_xu_is2_tid, + iu_xu_is2_ucode_vld => iu_xu_is2_ucode_vld, + iu_xu_is2_vld => iu_xu_is2_vld, + iu_xu_quiesce => iu_xu_quiesce, + iu_xu_ra => iu_xu_ra, + iu_xu_request => iu_xu_request, + iu_xu_thread => iu_xu_thread, + iu_xu_userdef => iu_xu_userdef, + iu_xu_wimge => iu_xu_wimge, + + rtim_sl_thold_7 => an_ac_rtim_sl_thold_7_omm, + func_sl_thold_7 => an_ac_func_sl_thold_7_omm, + func_nsl_thold_7 => an_ac_func_nsl_thold_7_omm, + ary_nsl_thold_7 => an_ac_ary_nsl_thold_7_omm, + sg_7 => an_ac_sg_7_omm, + fce_7 => an_ac_fce_7_omm, + rtim_sl_thold_6 => rp_pc_rtim_sl_thold_6, + func_sl_thold_6 => rp_pc_func_sl_thold_6, + func_nsl_thold_6 => rp_pc_func_nsl_thold_6, + ary_nsl_thold_6 => rp_pc_ary_nsl_thold_6, + sg_6 => rp_pc_sg_6, + fce_6 => rp_pc_fce_6, + an_ac_scom_dch => an_ac_scom_dch_omm, + an_ac_scom_cch => an_ac_scom_cch_omm, + an_ac_checkstop => an_ac_checkstop_omm, + an_ac_debug_stop => an_ac_debug_stop_omm, + an_ac_pm_thread_stop => an_ac_pm_thread_stop_omm, + an_ac_reset_1_complete => an_ac_reset_1_complete_omm, + an_ac_reset_2_complete => an_ac_reset_2_complete_omm, + an_ac_reset_3_complete => an_ac_reset_3_complete_omm, + an_ac_reset_wd_complete => an_ac_reset_wd_complete_omm, + an_ac_abist_start_test => an_ac_abist_start_test_omm, + ac_rp_trace_to_perfcntr => ac_rp_trace_to_perfcntr, + rp_pc_scom_dch_q => rp_pc_scom_dch_q, + rp_pc_scom_cch_q => rp_pc_scom_cch_q, + rp_pc_checkstop_q => rp_pc_checkstop_q, + rp_pc_debug_stop_q => rp_pc_debug_stop_q, + rp_pc_pm_thread_stop_q => rp_pc_pm_thread_stop_q, + rp_pc_reset_1_complete_q => rp_pc_reset_1_complete_q, + rp_pc_reset_2_complete_q => rp_pc_reset_2_complete_q, + rp_pc_reset_3_complete_q => rp_pc_reset_3_complete_q, + rp_pc_reset_wd_complete_q => rp_pc_reset_wd_complete_q, + rp_pc_abist_start_test_q => rp_pc_abist_start_test_q, + rp_pc_trace_to_perfcntr_q => rp_pc_trace_to_perfcntr_q, + pc_rp_scom_dch => pc_rp_scom_dch, + pc_rp_scom_cch => pc_rp_scom_cch, + pc_rp_special_attn => pc_rp_special_attn, + pc_rp_checkstop => pc_rp_checkstop, + pc_rp_local_checkstop => pc_rp_local_checkstop, + pc_rp_recov_err => pc_rp_recov_err, + pc_rp_trace_error => pc_rp_trace_error, + pc_rp_event_bus_enable => pc_rp_event_bus_enable, + pc_rp_event_bus => pc_rp_event_bus, + pc_rp_fu_bypass_events => pc_rp_fu_bypass_events, + pc_rp_iu_bypass_events => pc_rp_iu_bypass_events, + pc_rp_mm_bypass_events => pc_rp_mm_bypass_events, + pc_rp_lsu_bypass_events => pc_rp_lsu_bypass_events, + pc_rp_pm_thread_running => pc_rp_pm_thread_running, + pc_rp_power_managed => pc_rp_power_managed, + pc_rp_rvwinkle_mode => pc_rp_rvwinkle_mode, + ac_an_scom_dch_q => ac_an_scom_dch_imm, + ac_an_scom_cch_q => ac_an_scom_cch_imm, + ac_an_special_attn_q => ac_an_special_attn_imm, + ac_an_checkstop_q => ac_an_checkstop_imm, + ac_an_local_checkstop_q => ac_an_local_checkstop_imm, + ac_an_recov_err_q => ac_an_recov_err_imm, + ac_an_trace_error_q => ac_an_trace_error_imm, + rp_mm_event_bus_enable_q => rp_mm_event_bus_enable_q, + ac_an_event_bus_q => ac_an_event_bus_imm, + ac_an_fu_bypass_events_q => ac_an_fu_bypass_events_imm, + ac_an_iu_bypass_events_q => ac_an_iu_bypass_events_imm, + ac_an_mm_bypass_events_q => ac_an_mm_bypass_events_imm, + ac_an_lsu_bypass_events_q => ac_an_lsu_bypass_events_imm, + ac_an_pm_thread_running_q => ac_an_pm_thread_running_imm, + ac_an_power_managed_q => ac_an_power_managed_int, + ac_an_rvwinkle_mode_q => ac_an_rvwinkle_mode_imm, + + pc_func_scan_in => an_ac_func_scan_in_omm_iua(0 to 1), + pc_func_scan_in_q => rp_pc_func_scan_in_q(0 to 1), + pc_func_scan_out => pc_rp_func_scan_out(1), + pc_func_scan_out_q => ac_an_func_scan_out_imm_iua(1), + pc_bcfg_scan_in => mm_rp_bcfg_scan_out, + pc_bcfg_scan_in_q => rp_pc_bcfg_scan_out_q, + pc_dcfg_scan_in => mm_rp_dcfg_scan_out, + pc_dcfg_scan_in_q => rp_pc_dcfg_scan_out_q, + pc_bcfg_scan_out => pc_rp_bcfg_scan_out, + pc_bcfg_scan_out_q => ac_an_bcfg_scan_out_imm(2), + pc_ccfg_scan_out => pc_rp_ccfg_scan_out, + pc_ccfg_scan_out_q => ac_an_bcfg_scan_out_imm(0), + pc_dcfg_scan_out => pc_rp_dcfg_scan_out, + pc_dcfg_scan_out_q => ac_an_dcfg_scan_out_imm(0), + fu_abst_scan_in => an_ac_abst_scan_in_omm_iu(3), + fu_abst_scan_in_q => rp_fu_abst_scan_in_q, + fu_abst_scan_out => fu_rp_abst_scan_out, + fu_abst_scan_out_q => ac_an_abst_scan_out_imm_iu(3), + fu_bcfg_scan_out => fu_rp_bcfg_scan_out, + fu_bcfg_scan_out_q => ac_an_bcfg_scan_out_imm(3), + fu_ccfg_scan_out => fu_rp_ccfg_scan_out, + fu_ccfg_scan_out_q => ac_an_bcfg_scan_out_imm(1), + fu_dcfg_scan_out => fu_rp_dcfg_scan_out, + fu_dcfg_scan_out_q => ac_an_dcfg_scan_out_imm(1), + fu_func_scan_in => an_ac_func_scan_in_omm_iua(2 to 5), + fu_func_scan_in_q => rp_fu_func_scan_in_q(0 to 3), + fu_func_scan_out => fu_rp_func_scan_out(0 to 3), + fu_func_scan_out_q => ac_an_func_scan_out_imm_iua(2 to 5), + bx_abst_scan_in => an_ac_abst_scan_in_omm_iu(4), + bx_abst_scan_in_q => rp_bx_abst_scan_in_q, + bx_abst_scan_out => bx_rp_abst_scan_out, + bx_abst_scan_out_q => ac_an_abst_scan_out_imm_iu(4), + bx_func_scan_in => an_ac_func_scan_in_omm_iua(20 to 21), + bx_func_scan_in_q => rp_bx_func_scan_in_q(0 to 1), + bx_func_scan_out => bx_rp_func_scan_out(0 to 1), + bx_func_scan_out_q => ac_an_func_scan_out_imm_iua(20 to 21), + spare_func_scan_in => an_ac_func_scan_in_omm_iub(60 to 63), + spare_func_scan_out_q => ac_an_func_scan_out_imm_iub(60 to 63), + rp_abst_scan_in => pc_rp_abst_scan_out, -- uses and stages pcq scan chain + rp_func_scan_in => pc_rp_func_scan_out(0), -- uses and stages pcq scan chain + rp_abst_scan_out => ac_an_abst_scan_out_imm_iu(2), -- uses and stages pcq scan chain + rp_func_scan_out => ac_an_func_scan_out_imm_iua(0), -- uses and stages pcq scan chain + + -- pass thru signals + an_ac_abist_mode_dc_iiu => an_ac_abist_mode_dc_omm, + an_ac_ccflush_dc_iiu => an_ac_ccflush_dc_omm, + an_ac_gsd_test_enable_dc_iiu => an_ac_gsd_test_enable_dc_omm, + an_ac_gsd_test_acmode_dc_iiu => an_ac_gsd_test_acmode_dc_omm, + an_ac_lbist_ip_dc_iiu => an_ac_lbist_ip_dc_omm, + an_ac_lbist_ac_mode_dc_iiu => an_ac_lbist_ac_mode_dc_omm, + an_ac_malf_alert_iiu => an_ac_malf_alert_omm, + an_ac_psro_enable_dc_iiu => an_ac_psro_enable_dc_omm, + an_ac_scan_type_dc_iiu => an_ac_scan_type_dc_omm, + an_ac_scom_sat_id_iiu => an_ac_scom_sat_id_omm, + + an_ac_abist_mode_dc_oiu => an_ac_abist_mode_dc_oiu, + an_ac_ccflush_dc_oiu => an_ac_ccflush_dc_oiu, + an_ac_gsd_test_enable_dc_oiu => an_ac_gsd_test_enable_dc_oiu, + an_ac_gsd_test_acmode_dc_oiu => an_ac_gsd_test_acmode_dc_oiu, + an_ac_lbist_ip_dc_oiu => an_ac_lbist_ip_dc_oiu, + an_ac_lbist_ac_mode_dc_oiu => an_ac_lbist_ac_mode_dc_oiu, + an_ac_malf_alert_oiu => an_ac_malf_alert_oiu, + an_ac_psro_enable_dc_oiu => an_ac_psro_enable_dc_oiu, + an_ac_scan_type_dc_oiu => an_ac_scan_type_dc_oiu, + an_ac_scom_sat_id_oiu => an_ac_scom_sat_id_oiu, + + an_ac_back_inv_oiu => an_ac_back_inv_oiu, + an_ac_back_inv_addr_oiu => an_ac_back_inv_addr_oiu, + an_ac_back_inv_target_bit1_oiu => an_ac_back_inv_target_bit1_oiu, + an_ac_back_inv_target_bit3_oiu => an_ac_back_inv_target_bit3_oiu, + an_ac_back_inv_target_bit4_oiu => an_ac_back_inv_target_bit4_oiu, + an_ac_atpg_en_dc_oiu => an_ac_atpg_en_dc_oiu, + an_ac_lbist_ary_wrt_thru_dc_oiu => an_ac_lbist_ary_wrt_thru_dc_oiu, + an_ac_lbist_en_dc_oiu => an_ac_lbist_en_dc_oiu, + an_ac_scan_diag_dc_oiu => an_ac_scan_diag_dc_oiu, + an_ac_scan_dis_dc_b_oiu => an_ac_scan_dis_dc_b_oiu, + + + + ac_an_abist_done_dc_iiu => ac_an_abist_done_dc_iiu, + ac_an_psro_ringsig_iiu => ac_an_psro_ringsig_iiu, + an_ac_ccenable_dc_iiu => an_ac_ccenable_dc_iiu, + mm_pc_bo_fail_iiu => mm_pc_bo_fail_iiu, + mm_pc_bo_diagout_iiu => mm_pc_bo_diagout_iiu, + mm_pc_event_data_iiu => mm_pc_event_data_iiu, + + ac_an_abist_done_dc_oiu => ac_an_abist_done_dc_oiu, + ac_an_psro_ringsig_oiu => ac_an_psro_ringsig_oiu, + an_ac_ccenable_dc_oiu => an_ac_ccenable_dc_oiu, + mm_pc_bo_fail_oiu => mm_pc_bo_fail_oiu, + mm_pc_bo_diagout_oiu => mm_pc_bo_diagout_oiu, + mm_pc_event_data_oiu => mm_pc_event_data_oiu, + + pc_mm_abist_dcomp_g6t_2r_iiu => pc_mm_abist_dcomp_g6t_2r_iiu, + pc_mm_abist_di_g6t_2r_iiu => pc_mm_abist_di_g6t_2r_iiu, + pc_mm_abist_di_0_iiu => pc_mm_abist_di_0_iiu, + pc_mm_abist_ena_dc_iiu => pc_mm_abist_ena_dc_iiu, + pc_mm_abist_g6t_r_wb_iiu => pc_mm_abist_g6t_r_wb_iiu, + pc_mm_abist_g8t_bw_0_iiu => pc_mm_abist_g8t_bw_0_iiu, + pc_mm_abist_g8t_bw_1_iiu => pc_mm_abist_g8t_bw_1_iiu, + pc_mm_abist_g8t_dcomp_iiu => pc_mm_abist_g8t_dcomp_iiu, + pc_mm_abist_g8t_wenb_iiu => pc_mm_abist_g8t_wenb_iiu, + pc_mm_abist_g8t1p_renb_0_iiu => pc_mm_abist_g8t1p_renb_0_iiu, + pc_mm_abist_raddr_0_iiu => pc_mm_abist_raddr_0_iiu, + pc_mm_abist_raw_dc_b_iiu => pc_mm_abist_raw_dc_b_iiu, + pc_mm_abist_waddr_0_iiu => pc_mm_abist_waddr_0_iiu, + pc_mm_abist_wl128_comp_ena_iiu => pc_mm_abist_wl128_comp_ena_iiu, + pc_mm_bo_enable_4_iiu => pc_mm_bo_enable_4_iiu, + pc_mm_bo_repair_iiu => pc_mm_bo_repair_iiu, + pc_mm_bo_reset_iiu => pc_mm_bo_reset_iiu, + pc_mm_bo_select_iiu => pc_mm_bo_select_iiu, + pc_mm_bo_shdata_iiu => pc_mm_bo_shdata_iiu, + pc_mm_bo_unload_iiu => pc_mm_bo_unload_iiu, + pc_mm_ccflush_dc_iiu => pc_mm_ccflush_dc_iiu, + pc_mm_debug_mux1_ctrls_iiu => pc_mm_debug_mux1_ctrls_iiu, + pc_mm_event_count_mode_iiu => pc_mm_event_count_mode_iiu, + pc_mm_event_mux_ctrls_iiu => pc_mm_event_mux_ctrls_iiu, + pc_mm_trace_bus_enable_iiu => pc_mm_trace_bus_enable_iiu, + pc_mm_abist_dcomp_g6t_2r_oiu => pc_mm_abist_dcomp_g6t_2r_oiu, + pc_mm_abist_di_g6t_2r_oiu => pc_mm_abist_di_g6t_2r_oiu, + pc_mm_abist_di_0_oiu => pc_mm_abist_di_0_oiu, + pc_mm_abist_ena_dc_oiu => pc_mm_abist_ena_dc_oiu, + pc_mm_abist_g6t_r_wb_oiu => pc_mm_abist_g6t_r_wb_oiu, + pc_mm_abist_g8t_bw_0_oiu => pc_mm_abist_g8t_bw_0_oiu, + pc_mm_abist_g8t_bw_1_oiu => pc_mm_abist_g8t_bw_1_oiu, + pc_mm_abist_g8t_dcomp_oiu => pc_mm_abist_g8t_dcomp_oiu, + pc_mm_abist_g8t_wenb_oiu => pc_mm_abist_g8t_wenb_oiu, + pc_mm_abist_g8t1p_renb_0_oiu => pc_mm_abist_g8t1p_renb_0_oiu, + pc_mm_abist_raddr_0_oiu => pc_mm_abist_raddr_0_oiu, + pc_mm_abist_raw_dc_b_oiu => pc_mm_abist_raw_dc_b_oiu, + pc_mm_abist_waddr_0_oiu => pc_mm_abist_waddr_0_oiu, + pc_mm_abist_wl128_comp_ena_oiu => pc_mm_abist_wl128_comp_ena_oiu, + pc_mm_abst_sl_thold_3_oiu => pc_mm_abst_sl_thold_3_oiu, + pc_mm_abst_slp_sl_thold_3_oiu => pc_mm_abst_slp_sl_thold_3_oiu, + pc_mm_ary_nsl_thold_3_oiu => pc_mm_ary_nsl_thold_3_oiu, + pc_mm_ary_slp_nsl_thold_3_oiu => pc_mm_ary_slp_nsl_thold_3_oiu, + pc_mm_bo_enable_3_oiu => pc_mm_bo_enable_3_oiu, + pc_mm_bo_repair_oiu => pc_mm_bo_repair_oiu, + pc_mm_bo_reset_oiu => pc_mm_bo_reset_oiu, + pc_mm_bo_select_oiu => pc_mm_bo_select_oiu, + pc_mm_bo_shdata_oiu => pc_mm_bo_shdata_oiu, + pc_mm_bo_unload_oiu => pc_mm_bo_unload_oiu, + pc_mm_bolt_sl_thold_3_oiu => pc_mm_bolt_sl_thold_3_oiu, + pc_mm_ccflush_dc_oiu => pc_mm_ccflush_dc_oiu, + pc_mm_cfg_sl_thold_3_oiu => pc_mm_cfg_sl_thold_3_oiu, + pc_mm_cfg_slp_sl_thold_3_oiu => pc_mm_cfg_slp_sl_thold_3_oiu, + pc_mm_debug_mux1_ctrls_oiu => pc_mm_debug_mux1_ctrls_oiu, + pc_mm_event_count_mode_oiu => pc_mm_event_count_mode_oiu, + pc_mm_event_mux_ctrls_oiu => pc_mm_event_mux_ctrls_oiu, + pc_mm_fce_3_oiu => pc_mm_fce_3_oiu, + pc_mm_func_nsl_thold_3_oiu => pc_mm_func_nsl_thold_3_oiu, + pc_mm_func_sl_thold_3_oiu => pc_mm_func_sl_thold_3_oiu, + pc_mm_func_slp_nsl_thold_3_oiu => pc_mm_func_slp_nsl_thold_3_oiu, + pc_mm_func_slp_sl_thold_3_oiu => pc_mm_func_slp_sl_thold_3_oiu, + pc_mm_gptr_sl_thold_3_oiu => pc_mm_gptr_sl_thold_3_oiu, + pc_mm_repr_sl_thold_3_oiu => pc_mm_repr_sl_thold_3_oiu, + pc_mm_sg_3_oiu => pc_mm_sg_3_oiu, + pc_mm_time_sl_thold_3_oiu => pc_mm_time_sl_thold_3_oiu, + pc_mm_trace_bus_enable_oiu => pc_mm_trace_bus_enable_oiu, + + xu_wu_rf1_flush => xu_wu_rf1_flush, + xu_wu_ex1_flush => xu_wu_ex1_flush, + xu_wu_ex2_flush => xu_wu_ex2_flush, + xu_wu_ex3_flush => xu_wu_ex3_flush, + xu_wu_ex4_flush => xu_wu_ex4_flush, + xu_wu_ex5_flush => xu_wu_ex5_flush, + xu_wl_rf1_flush => xu_wl_rf1_flush, + xu_wl_ex1_flush => xu_wl_ex1_flush, + xu_wl_ex2_flush => xu_wl_ex2_flush, + xu_wl_ex3_flush => xu_wl_ex3_flush, + xu_wl_ex4_flush => xu_wl_ex4_flush, + xu_wl_ex5_flush => xu_wl_ex5_flush, + xu_iu_l_flush => xu_iu_l_flush, + xu_iu_u_flush => xu_iu_u_flush, + + an_ac_grffence_en_dc_oiu => an_ac_grffence_en_dc_oiu, + + bg_an_ac_func_scan_sn => bg_an_ac_func_scan_sn_omm, + bg_an_ac_abst_scan_sn => bg_an_ac_abst_scan_sn_omm, + bg_an_ac_func_scan_sn_q => bg_an_ac_func_scan_sn_q, + bg_an_ac_abst_scan_sn_q => bg_an_ac_abst_scan_sn_q, + + bg_ac_an_func_scan_ns => "0000000000", + bg_ac_an_abst_scan_ns => "00", + bg_ac_an_func_scan_ns_q => bg_ac_an_func_scan_ns_q, + bg_ac_an_abst_scan_ns_q => bg_ac_an_abst_scan_ns_q, + + bg_pc_l1p_abist_di_0 => "0000", + bg_pc_l1p_abist_g8t1p_renb_0 => '0', + bg_pc_l1p_abist_g8t_bw_0 => '0', + bg_pc_l1p_abist_g8t_bw_1 => '0', + bg_pc_l1p_abist_g8t_dcomp => "0000", + bg_pc_l1p_abist_g8t_wenb => '0', + bg_pc_l1p_abist_raddr_0 => "0000000000", + bg_pc_l1p_abist_waddr_0 => "0000000000", + bg_pc_l1p_abist_wl128_comp_ena => '0', + bg_pc_l1p_abist_wl32_comp_ena => '0', + bg_pc_l1p_abist_di_0_q => bg_pc_l1p_abist_di_0_q, + bg_pc_l1p_abist_g8t1p_renb_0_q => bg_pc_l1p_abist_g8t1p_renb_0_q, + bg_pc_l1p_abist_g8t_bw_0_q => bg_pc_l1p_abist_g8t_bw_0_q, + bg_pc_l1p_abist_g8t_bw_1_q => bg_pc_l1p_abist_g8t_bw_1_q, + bg_pc_l1p_abist_g8t_dcomp_q => bg_pc_l1p_abist_g8t_dcomp_q, + bg_pc_l1p_abist_g8t_wenb_q => bg_pc_l1p_abist_g8t_wenb_q, + bg_pc_l1p_abist_raddr_0_q => bg_pc_l1p_abist_raddr_0_q, + bg_pc_l1p_abist_waddr_0_q => bg_pc_l1p_abist_waddr_0_q, + bg_pc_l1p_abist_wl128_comp_ena_q => bg_pc_l1p_abist_wl128_comp_ena_q, + bg_pc_l1p_abist_wl32_comp_ena_q => bg_pc_l1p_abist_wl32_comp_ena_q, + + bg_pc_l1p_gptr_sl_thold_3 => bg_pc_l1p_gptr_sl_thold_3, + bg_pc_l1p_time_sl_thold_3 => bg_pc_l1p_time_sl_thold_3, + bg_pc_l1p_repr_sl_thold_3 => bg_pc_l1p_repr_sl_thold_3, + bg_pc_l1p_abst_sl_thold_3 => bg_pc_l1p_abst_sl_thold_3, + bg_pc_l1p_func_sl_thold_3 => bg_pc_l1p_func_sl_thold_3, + bg_pc_l1p_func_slp_sl_thold_3 => bg_pc_l1p_func_slp_sl_thold_3, + bg_pc_l1p_bolt_sl_thold_3 => bg_pc_l1p_bolt_sl_thold_3, + bg_pc_l1p_ary_nsl_thold_3 => bg_pc_l1p_ary_nsl_thold_3, + bg_pc_l1p_sg_3 => bg_pc_l1p_sg_3, + bg_pc_l1p_fce_3 => bg_pc_l1p_fce_3, + bg_pc_l1p_bo_enable_3 => bg_pc_l1p_bo_enable_3, + bg_pc_l1p_gptr_sl_thold_2 => bg_pc_l1p_gptr_sl_thold_2_imm, + bg_pc_l1p_time_sl_thold_2 => bg_pc_l1p_time_sl_thold_2_imm, + bg_pc_l1p_repr_sl_thold_2 => bg_pc_l1p_repr_sl_thold_2_imm, + bg_pc_l1p_abst_sl_thold_2 => bg_pc_l1p_abst_sl_thold_2_imm, + bg_pc_l1p_func_sl_thold_2 => bg_pc_l1p_func_sl_thold_2_imm, + bg_pc_l1p_func_slp_sl_thold_2 => bg_pc_l1p_func_slp_sl_thold_2_imm, + bg_pc_l1p_bolt_sl_thold_2 => bg_pc_l1p_bolt_sl_thold_2_imm, + bg_pc_l1p_ary_nsl_thold_2 => bg_pc_l1p_ary_nsl_thold_2_imm, + bg_pc_l1p_sg_2 => bg_pc_l1p_sg_2_imm, + bg_pc_l1p_fce_2 => bg_pc_l1p_fce_2_imm, + bg_pc_l1p_bo_enable_2 => bg_pc_l1p_bo_enable_2_imm, + + bg_pc_bo_unload_iiu => bg_pc_bo_unload_iiu, + bg_pc_bo_load_iiu => bg_pc_bo_load_iiu, + bg_pc_bo_repair_iiu => bg_pc_bo_repair_iiu, + bg_pc_bo_reset_iiu => bg_pc_bo_reset_iiu, + bg_pc_bo_shdata_iiu => bg_pc_bo_shdata_iiu, + bg_pc_bo_select_iiu => bg_pc_bo_select_iiu, + bg_pc_l1p_ccflush_dc_iiu => bg_pc_l1p_ccflush_dc_iiu, + bg_pc_l1p_abist_ena_dc_iiu => bg_pc_l1p_abist_ena_dc_iiu, + bg_pc_l1p_abist_raw_dc_b_iiu => bg_pc_l1p_abist_raw_dc_b_iiu, + + bg_pc_bo_unload_oiu => bg_pc_bo_unload_oiu, + bg_pc_bo_load_oiu => bg_pc_bo_load_oiu, + bg_pc_bo_repair_oiu => bg_pc_bo_repair_oiu, + bg_pc_bo_reset_oiu => bg_pc_bo_reset_oiu, + bg_pc_bo_shdata_oiu => bg_pc_bo_shdata_oiu, + bg_pc_bo_select_oiu => bg_pc_bo_select_oiu, + bg_pc_l1p_ccflush_dc_oiu => bg_pc_l1p_ccflush_dc_oiu, + bg_pc_l1p_abist_ena_dc_oiu => bg_pc_l1p_abist_ena_dc_oiu, + bg_pc_l1p_abist_raw_dc_b_oiu => bg_pc_l1p_abist_raw_dc_b_oiu, + + bg_pc_bo_fail_iiu => bg_pc_bo_fail_omm, + bg_pc_bo_diagout_iiu => bg_pc_bo_diagout_omm, + bg_pc_bo_fail_oiu => bg_pc_bo_fail_oiu, + bg_pc_bo_diagout_oiu => bg_pc_bo_diagout_oiu, + + xu_iu_xucr4_mmu_mchk => xu_iu_xucr4_mmu_mchk, + + gnd => gnd, + vcs => vcs, + vdd => vdd + ); -- end component a_iuq + +a_xuq: entity work.xuq + generic map(a2mode => a2mode, + bcfg_epn_0to15 => bcfg_epn_0to15, + bcfg_epn_16to31 => bcfg_epn_16to31, + bcfg_epn_32to47 => bcfg_epn_32to47, + bcfg_epn_48to51 => bcfg_epn_48to51, + bcfg_rpn_22to31 => bcfg_rpn_22to31, + bcfg_rpn_32to47 => bcfg_rpn_32to47, + bcfg_rpn_48to51 => bcfg_rpn_48to51, + eff_ifar => xu_eff_ifar, + expand_type => expand_type, + l_endian_m => l_endian_m, + lmq_entries => lmq_entries, + real_data_add => xu_real_data_add, + regmode => regmode, + hvmode => hvmode, + st_data_32b_mode => st_data_32b_mode, + threads => threads, + load_credits => load_credits, + store_credits => store_credits, + spr_xucr0_init_mod => spr_xucr0_init_mod, + dc_size => dc_size ) + port map ( + abst_scan_in => an_ac_abst_scan_in_omm_xu(7 to 9), + bcfg_scan_in => an_ac_bcfg_scan_in_omm_bit4, + ccfg_scan_in => an_ac_bcfg_scan_in_omm_bit1, + dcfg_scan_in => an_ac_dcfg_scan_in_omm(2), + func_scan_in => an_ac_func_scan_in_omm_xu(31 to 58), + gptr_scan_in => bx_xu_gptr_scan_out, + repr_scan_in => bx_xu_repr_scan_out, + time_scan_in => bx_xu_time_scan_out, + an_ac_atpg_en_dc => an_ac_atpg_en_dc_oiu, + an_ac_back_inv => an_ac_back_inv_oiu, + an_ac_back_inv_addr => an_ac_back_inv_addr_oiu(64-xu_real_data_add to 63), + an_ac_back_inv_target_bit1 => an_ac_back_inv_target_bit1_oiu, + an_ac_back_inv_target_bit3 => an_ac_back_inv_target_bit3_oiu, + an_ac_back_inv_target_bit4 => an_ac_back_inv_target_bit4_oiu, + an_ac_crit_interrupt => an_ac_crit_interrupt_omm, + an_ac_ext_interrupt => an_ac_ext_interrupt_omm, + an_ac_flh2l2_gate => an_ac_flh2l2_gate_omm, + an_ac_grffence_en_dc => an_ac_grffence_en_dc_oiu, + an_ac_lbist_en_dc => an_ac_lbist_en_dc_oiu, + an_ac_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc_oiu, + an_ac_perf_interrupt => an_ac_perf_interrupt_omm, + an_ac_reld_core_tag => an_ac_reld_core_tag_omm(0 to 4), + an_ac_reld_data => an_ac_reld_data_omm, + an_ac_reld_data_vld => an_ac_reld_data_vld_omm, + an_ac_reld_ecc_err => an_ac_reld_ecc_err_omm, + an_ac_reld_ecc_err_ue => an_ac_reld_ecc_err_ue_omm, + an_ac_reld_qw => an_ac_reld_qw_omm, + an_ac_reld_data_coming => an_ac_reld_data_coming_omm, + an_ac_reld_ditc => an_ac_reld_ditc_omm, + an_ac_reld_crit_qw => an_ac_reld_crit_qw_omm, + an_ac_req_ld_pop => an_ac_req_ld_pop_omm, + an_ac_req_spare_ctrl_a1 => an_ac_req_spare_ctrl_a1_omm, + an_ac_req_st_gather => an_ac_req_st_gather_omm, + an_ac_req_st_pop => an_ac_req_st_pop_omm, + an_ac_reservation_vld => an_ac_reservation_vld_omm, + an_ac_sleep_en => an_ac_sleep_en_omm, + an_ac_stcx_complete => an_ac_stcx_complete_omm, + an_ac_stcx_pass => an_ac_stcx_pass_omm, + xu_iu_stcx_complete => xu_iu_stcx_complete, + lsu_reld_data_vld => lsu_reld_data_vld, + lsu_reld_core_tag => lsu_reld_core_tag, + lsu_reld_qw => lsu_reld_qw , + lsu_reld_ditc => lsu_reld_ditc, + lsu_reld_ecc_err => lsu_reld_ecc_err, + lsu_reld_data => lsu_reld_data, + lsu_req_st_pop => lsu_req_st_pop, + lsu_req_st_pop_thrd => lsu_req_st_pop_thrd, + fu_xu_ex1_ifar0 => fu_xu_ex1_ifar, + fu_xu_ex1_ifar1 => fu_xu_ex1_ifar, + fu_xu_ex1_ifar2 => fu_xu_ex1_ifar, + fu_xu_ex1_ifar3 => fu_xu_ex1_ifar, + fu_xu_ex2_async_block => fu_xu_ex2_async_block, + fu_xu_ex2_ifar_val => fu_xu_ex2_ifar_val, + fu_xu_ex2_ifar_issued => fu_xu_ex2_ifar_issued, + fu_xu_ex2_store_data(0 to 63) => fu_xu_ex2_store_data, + fu_xu_ex2_store_data(64 to 127) => fu_xu_ex2_store_data, + fu_xu_ex2_store_data(128 to 191) => fu_xu_ex2_store_data, + fu_xu_ex2_store_data(192 to 255) => fu_xu_ex2_store_data, + fu_xu_ex2_store_data_val => fu_xu_ex2_store_data_val, + fu_xu_ex3_flush2ucode => fu_xu_ex3_flush2ucode, + fu_xu_ex2_instr_match => fu_xu_ex2_instr_match, + fu_xu_ex2_instr_type => fu_xu_ex2_instr_type, + fu_xu_ex2_is_ucode => fu_xu_ex2_is_ucode, + fu_xu_ex3_ap_int_req => fu_xu_ex3_ap_int_req, + fu_xu_ex3_n_flush => fu_xu_ex3_n_flush, + fu_xu_ex3_np1_flush => fu_xu_ex3_np1_flush, + fu_xu_ex3_regfile_err_det => fu_xu_ex3_regfile_err_det, + fu_xu_ex3_trap => fu_xu_ex3_trap, + fu_xu_ex4_cr0 => fu_xu_ex4_cr, + fu_xu_ex4_cr0_bf => fu_xu_ex4_cr_bf, + fu_xu_ex4_cr1 => fu_xu_ex4_cr, + fu_xu_ex4_cr1_bf => fu_xu_ex4_cr_bf, + fu_xu_ex4_cr2 => fu_xu_ex4_cr, + fu_xu_ex4_cr2_bf => fu_xu_ex4_cr_bf, + fu_xu_ex4_cr3 => fu_xu_ex4_cr, + fu_xu_ex4_cr3_bf => fu_xu_ex4_cr_bf, + fu_xu_ex4_cr_noflush => fu_xu_ex4_cr_noflush, + fu_xu_ex4_cr_val => fu_xu_ex4_cr_val, + fu_xu_regfile_seq_end => fu_xu_regfile_seq_end, + fu_xu_rf1_act => fu_xu_rf1_act, + regf_scan_in => an_ac_regf_scan_in_omm(5 to 11), + slowspr_addr_in => bx_xu_slowspr_addr, + slowspr_data_in => bx_xu_slowspr_data, + slowspr_done_in => bx_xu_slowspr_done, + slowspr_etid_in => bx_xu_slowspr_etid, + slowspr_rw_in => bx_xu_slowspr_rw, + slowspr_val_in => bx_xu_slowspr_val, + spr_pvr_version_dc => spr_pvr_version_dc, + spr_pvr_revision_dc => spr_pvr_revision_dc, + debug_data_in => iu_xu_debug_data, + trigger_data_in => iu_xu_trigger_data, + iu_xu_ex4_tlb_data => iu_xu_ex4_tlb_data, + iu_xu_ierat_ex2_flush_req => iu_xu_ierat_ex2_flush_req, + iu_xu_ierat_ex3_par_err => iu_xu_ierat_ex3_par_err, + iu_xu_ierat_ex4_par_err => iu_xu_ierat_ex4_par_err, + iu_xu_is2_axu_instr_type => iu_xu_is2_axu_instr_type, + iu_xu_is2_axu_ld_or_st => iu_xu_is2_axu_ld_or_st, + iu_xu_is2_axu_ldst_extpid => iu_xu_is2_axu_ldst_extpid, + iu_xu_is2_axu_ldst_forcealign => iu_xu_is2_axu_ldst_forcealign, + iu_xu_is2_axu_ldst_forceexcept => iu_xu_is2_axu_ldst_forceexcept, + iu_xu_is2_axu_ldst_indexed => iu_xu_is2_axu_ldst_indexed, + iu_xu_is2_axu_ldst_size => iu_xu_is2_axu_ldst_size, + iu_xu_is2_axu_ldst_tag => iu_xu_is2_axu_ldst_tag, + iu_xu_is2_axu_ldst_update => iu_xu_is2_axu_ldst_update, + iu_xu_is2_axu_mffgpr => iu_xu_is2_axu_mffgpr, + iu_xu_is2_axu_mftgpr => iu_xu_is2_axu_mftgpr, + iu_xu_is2_axu_store => iu_xu_is2_axu_store, + iu_xu_is2_axu_movedp => iu_xu_is2_axu_movedp, + iu_xu_is2_error => iu_xu_is2_error, + iu_xu_is2_gshare => iu_xu_is2_gshare, + iu_xu_is2_ifar => iu_xu_is2_ifar, + iu_xu_is2_instr => iu_xu_is2_instr, + iu_xu_is2_is_ucode => iu_xu_is2_is_ucode, + iu_xu_is2_match => iu_xu_is2_match, + iu_xu_is2_pred_taken_cnt => iu_xu_is2_pred_taken_cnt, + iu_xu_is2_pred_update => iu_xu_is2_pred_update, + iu_xu_is2_s1 => iu_xu_is2_s1, + iu_xu_is2_s1_vld => iu_xu_is2_s1_vld, + iu_xu_is2_s2 => iu_xu_is2_s2, + iu_xu_is2_s2_vld => iu_xu_is2_s2_vld, + iu_xu_is2_s3 => iu_xu_is2_s3, + iu_xu_is2_s3_vld => iu_xu_is2_s3_vld, + iu_xu_is2_ta => iu_xu_is2_ta, + iu_xu_is2_ta_vld => iu_xu_is2_ta_vld, + iu_xu_is2_tid => iu_xu_is2_tid, + iu_xu_is2_ucode_vld => iu_xu_is2_ucode_vld, + iu_xu_is2_vld => iu_xu_is2_vld, + iu_xu_quiesce => iu_xu_quiesce, + iu_xu_ra => iu_xu_ra, + iu_xu_request => iu_xu_request, + iu_xu_thread => iu_xu_thread, + iu_xu_userdef => iu_xu_userdef, + iu_xu_wimge => iu_xu_wimge, + mm_xu_derat_mmucr0_0 => mm_xu_derat_mmucr0_0, + mm_xu_derat_mmucr0_1 => mm_xu_derat_mmucr0_1, + mm_xu_derat_mmucr0_2 => mm_xu_derat_mmucr0_2, + mm_xu_derat_mmucr0_3 => mm_xu_derat_mmucr0_3, + mm_xu_derat_mmucr1 => mm_xu_derat_mmucr1, + mm_xu_derat_pid0 => mm_xu_derat_pid0, + mm_xu_derat_pid1 => mm_xu_derat_pid1, + mm_xu_derat_pid2 => mm_xu_derat_pid2, + mm_xu_derat_pid3 => mm_xu_derat_pid3, + mm_xu_derat_rel_data => mm_xu_derat_rel_data, + mm_xu_derat_rel_val => mm_xu_derat_rel_val, + mm_xu_derat_snoop_attr => mm_xu_derat_snoop_attr, + mm_xu_derat_snoop_val => mm_xu_derat_snoop_val, + mm_xu_derat_snoop_coming => mm_xu_derat_snoop_coming, + mm_xu_derat_snoop_vpn => mm_xu_derat_snoop_vpn, + mm_xu_eratmiss_done => mm_xu_eratmiss_done, + mm_xu_esr_pt => mm_xu_esr_pt, + mm_xu_esr_data => mm_xu_esr_data, + mm_xu_esr_epid => mm_xu_esr_epid, + mm_xu_esr_st => mm_xu_esr_st, + mm_xu_ex3_flush_req => mm_xu_ex3_flush_req, + xu_mm_rf1_is_tlbsxr => xu_mm_rf1_is_tlbsxr, + mm_xu_hold_done => mm_xu_hold_done, + mm_xu_hold_req => mm_xu_hold_req, + mm_xu_hv_priv => mm_xu_hv_priv, + mm_xu_illeg_instr => mm_xu_illeg_instr, + mm_xu_local_snoop_reject => mm_xu_local_snoop_reject, + mm_xu_lrat_miss => mm_xu_lrat_miss, + mm_xu_lsu_addr => mm_xu_lsu_addr, + mm_xu_lsu_lpid => mm_xu_lsu_lpid, + mm_xu_lsu_lpidr => mm_xu_lsu_lpidr, + mm_xu_lsu_gs => mm_xu_lsu_gs, + mm_xu_lsu_ind => mm_xu_lsu_ind, + mm_xu_lsu_lbit => mm_xu_lsu_lbit, + mm_xu_lsu_req => mm_xu_lsu_req, + mm_xu_lsu_ttype => mm_xu_lsu_ttype, + mm_xu_lsu_u => mm_xu_lsu_u, + mm_xu_lsu_wimge => mm_xu_lsu_wimge, + mm_xu_pt_fault => mm_xu_pt_fault, + mm_xu_quiesce => mm_xu_quiesce, + mm_xu_tlb_inelig => mm_xu_tlb_inelig, + mm_xu_tlb_miss => mm_xu_tlb_miss, + mm_xu_tlb_multihit_err => mm_xu_tlb_multihit_err, + mm_xu_tlb_par_err => mm_xu_tlb_par_err, + mm_xu_lru_par_err => mm_xu_lru_par_err, + mm_xu_cr0_eq_valid => mm_xu_cr0_eq_valid, + mm_xu_cr0_eq => mm_xu_cr0_eq, + nclk => a2_nclk, + pc_xu_abst_sl_thold_3 => pc_xu_abst_sl_thold_3_ofu, + pc_xu_abst_slp_sl_thold_3 => pc_xu_abst_slp_sl_thold_3_ofu, + pc_xu_regf_sl_thold_3 => pc_xu_regf_sl_thold_3_ofu, + pc_xu_regf_slp_sl_thold_3 => pc_xu_regf_slp_sl_thold_3_ofu, + pc_xu_ary_nsl_thold_3 => pc_xu_ary_nsl_thold_3_ofu, + pc_xu_ary_slp_nsl_thold_3 => pc_xu_ary_slp_nsl_thold_3_ofu, + pc_xu_bolt_sl_thold_3 => pc_xu_bolt_sl_thold_3_ofu, + pc_xu_bo_enable_3 => pc_xu_bo_enable_3_ofu, + pc_xu_bo_load => pc_xu_bo_load_ofu, + pc_xu_bo_unload => pc_xu_bo_unload_ofu, + pc_xu_bo_repair => pc_xu_bo_repair_ofu, + pc_xu_bo_reset => pc_xu_bo_reset_ofu, + pc_xu_bo_shdata => pc_xu_bo_shdata_ofu, + pc_xu_bo_select => pc_xu_bo_select_ofu, + pc_xu_cache_par_err_event => pc_xu_cache_par_err_event_ofu, + pc_xu_ccflush_dc => pc_xu_ccflush_dc_ofu, + pc_xu_cfg_sl_thold_3 => pc_xu_cfg_sl_thold_3_ofu, + pc_xu_cfg_slp_sl_thold_3 => pc_xu_cfg_slp_sl_thold_3_ofu, + pc_xu_dbg_action => pc_xu_dbg_action_ofu, + pc_xu_debug_mux1_ctrls => pc_xu_debug_mux1_ctrls_ofu, + pc_xu_debug_mux2_ctrls => pc_xu_debug_mux2_ctrls_ofu, + pc_xu_debug_mux3_ctrls => pc_xu_debug_mux3_ctrls_ofu, + pc_xu_debug_mux4_ctrls => pc_xu_debug_mux4_ctrls_ofu, + pc_xu_decrem_dis_on_stop => pc_xu_decrem_dis_on_stop_ofu, + xu_pc_spr_ccr0_we => xu_pc_spr_ccr0_we, + xu_pc_spr_ccr0_pme => xu_pc_spr_ccr0_pme, + pc_xu_event_bus_enable => pc_xu_event_bus_enable_ofu, + pc_xu_event_count_mode => pc_xu_event_count_mode_ofu, + pc_xu_event_mux_ctrls => pc_xu_event_mux_ctrls_ofu, + pc_xu_extirpts_dis_on_stop => pc_xu_extirpts_dis_on_stop_ofu, + pc_xu_fce_3 => pc_xu_fce_3_ofu, + pc_xu_force_ude => pc_xu_force_ude_ofu, + pc_xu_func_nsl_thold_3 => pc_xu_func_nsl_thold_3_ofu, + pc_xu_func_sl_thold_3 => pc_xu_func_sl_thold_3_ofu, + pc_xu_func_slp_nsl_thold_3 => pc_xu_func_slp_nsl_thold_3_ofu, + pc_xu_func_slp_sl_thold_3 => pc_xu_func_slp_sl_thold_3_ofu, + pc_xu_gptr_sl_thold_3 => pc_xu_gptr_sl_thold_3_ofu, + pc_xu_init_reset => pc_xu_init_reset_ofu, + pc_xu_inj_dcachedir_multihit => pc_xu_inj_dcachedir_multihit_ofu, + pc_xu_instr_trace_mode => pc_xu_instr_trace_mode_ofu, + pc_xu_instr_trace_tid => pc_xu_instr_trace_tid_ofu, + pc_xu_lsu_event_mux_ctrls => pc_xu_lsu_event_mux_ctrls_ofu, + pc_xu_msrovride_de => pc_xu_msrovride_de, + pc_xu_msrovride_enab => pc_xu_msrovride_enab_ofu, + pc_xu_msrovride_pr => pc_xu_msrovride_pr_ofu, + pc_xu_msrovride_gs => pc_xu_msrovride_gs_ofu, + pc_xu_ram_execute => pc_xu_ram_execute_ofu, + pc_xu_ram_flush_thread => pc_xu_ram_flush_thread_ofu, + pc_xu_ram_mode => pc_xu_ram_mode_ofu, + pc_xu_ram_thread => pc_xu_ram_thread_ofu, + pc_xu_repr_sl_thold_3 => pc_xu_repr_sl_thold_3_ofu, + pc_xu_reset_1_complete => pc_xu_reset_1_cmplt_ofu, + pc_xu_reset_2_complete => pc_xu_reset_2_cmplt_ofu, + pc_xu_reset_3_complete => pc_xu_reset_3_cmplt_ofu, + pc_xu_reset_wd_complete => pc_xu_reset_wd_cmplt_ofu, + pc_xu_sg_3 => pc_xu_sg_3_ofu, + pc_xu_step => pc_xu_step_ofu, + pc_xu_stop => pc_xu_stop_ofu, + pc_xu_timebase_dis_on_stop => pc_xu_timebase_dis_on_stop_ofu, + pc_xu_time_sl_thold_3 => pc_xu_time_sl_thold_3_ofu, + pc_xu_trace_bus_enable => pc_xu_trace_bus_enable_ofu, + pc_xu_inj_dcache_parity => pc_xu_inj_dcache_parity_ofu, + pc_xu_inj_dcachedir_parity => pc_xu_inj_dcachedir_parity_ofu, + pc_xu_inj_llbust_attempt => pc_xu_inj_llbust_attempt_ofu, + pc_xu_inj_llbust_failed => pc_xu_inj_llbust_failed_ofu, + pc_xu_inj_sprg_ecc => pc_xu_inj_sprg_ecc_ofu, + pc_xu_inj_regfile_parity => pc_xu_inj_regfile_parity_ofu, + pc_xu_inj_wdt_reset => pc_xu_inj_wdt_reset_ofu, + pc_xu_abist_dcomp_g6t_2r => pc_xu_abist_dcomp_g6t_2r_ofu(0 to 3), + pc_xu_abist_di_0 => pc_xu_abist_di_0_ofu(0 to 3), + pc_xu_abist_di_1 => pc_xu_abist_di_1_ofu(0 to 3), + pc_xu_abist_di_g6t_2r => pc_xu_abist_di_g6t_2r_ofu(0 to 3), + pc_xu_abist_ena_dc => pc_xu_abist_ena_dc_ofu, + pc_xu_abist_g6t_bw => pc_xu_abist_g6t_bw_ofu(0 to 1), + pc_xu_abist_g6t_r_wb => pc_xu_abist_g6t_r_wb_ofu, + pc_xu_abist_g8t1p_renb_0 => pc_xu_abist_g8t1p_renb_0_ofu, + pc_xu_abist_g8t_bw_0 => pc_xu_abist_g8t_bw_0_ofu, + pc_xu_abist_g8t_bw_1 => pc_xu_abist_g8t_bw_1_ofu, + pc_xu_abist_g8t_dcomp => pc_xu_abist_g8t_dcomp_ofu(0 to 3), + pc_xu_abist_g8t_wenb => pc_xu_abist_g8t_wenb_ofu, + pc_xu_abist_grf_renb_0 => pc_xu_abist_grf_renb_0_ofu, + pc_xu_abist_grf_renb_1 => pc_xu_abist_grf_renb_1_ofu, + pc_xu_abist_grf_wenb_0 => pc_xu_abist_grf_wenb_0_ofu, + pc_xu_abist_grf_wenb_1 => pc_xu_abist_grf_wenb_1_ofu, + pc_xu_abist_raddr_0 => pc_xu_abist_raddr_0_ofu(0 to 9), + pc_xu_abist_raddr_1 => pc_xu_abist_raddr_1_ofu(0 to 9), + pc_xu_abist_raw_dc_b => pc_xu_abist_raw_dc_b_ofu, + pc_xu_abist_waddr_0 => pc_xu_abist_waddr_0_ofu(0 to 9), + pc_xu_abist_waddr_1 => pc_xu_abist_waddr_1_ofu(0 to 9), + pc_xu_abist_wl144_comp_ena => pc_xu_abist_wl144_comp_ena_ofu, + pc_xu_abist_wl32_comp_ena => pc_xu_abist_wl32_comp_ena_ofu, + pc_xu_abist_wl512_comp_ena => pc_xu_abist_wl512_comp_ena_ofu, + an_ac_coreid => an_ac_coreid_omm, + an_ac_external_mchk => an_ac_external_mchk_omm, + an_ac_hang_pulse => an_ac_hang_pulse_omm, + an_ac_scan_diag_dc => an_ac_scan_diag_dc_oiu, + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b_oiu, + an_ac_tb_update_enable => an_ac_tb_update_enable_omm, + an_ac_tb_update_pulse => an_ac_tb_update_pulse_omm, + an_ac_reld_l1_dump => an_ac_reld_l1_dump_omm, + ac_tc_machine_check => ac_an_machine_check_imm, + ac_an_req => ac_an_req_imm, + ac_an_req_endian => ac_an_req_endian_imm, + ac_an_req_ld_core_tag => ac_an_req_ld_core_tag_imm, + ac_an_req_ld_xfr_len => ac_an_req_ld_xfr_len_imm, + ac_an_req_pwr_token => ac_an_req_pwr_token_imm, + ac_an_req_ra => ac_an_req_ra_imm, + ac_an_req_spare_ctrl_a0 => ac_an_req_spare_ctrl_a0_imm, + ac_an_req_thread => ac_an_req_thread_imm, + ac_an_req_ttype => ac_an_req_ttype_imm, + ac_an_req_user_defined => ac_an_req_user_defined_imm, + ac_an_req_wimg_g => ac_an_req_wimg_g_imm, + ac_an_req_wimg_i => ac_an_req_wimg_i_imm, + ac_an_req_wimg_m => ac_an_req_wimg_m_imm, + ac_an_req_wimg_w => ac_an_req_wimg_w_imm, + ac_an_st_byte_enbl => xu_st_byte_enbl, + ac_an_st_data => xu_st_data, + ac_an_st_data_pwr_token => ac_an_st_data_pwr_token_imm, + an_ac_req_st_pop_thrd => an_ac_req_st_pop_thrd_omm, + ac_tc_debug_trigger => ac_an_debug_trigger_imm, + ac_tc_reset_1_request => ac_an_reset_1_request_imm, + ac_tc_reset_2_request => ac_an_reset_2_request_imm, + ac_tc_reset_3_request => ac_an_reset_3_request_imm, + ac_tc_reset_wd_request => ac_an_reset_wd_request_imm, + abst_scan_out => ac_an_abst_scan_out_imm_xu(7 to 9), + bcfg_scan_out => ac_an_bcfg_scan_out_imm(4), + ccfg_scan_out => xu_fu_ccfg_scan_out, + dcfg_scan_out => ac_an_dcfg_scan_out_imm(2), + func_scan_out => ac_an_func_scan_out_imm_xu(31 to 58), + gptr_scan_out => xu_mm_gptr_scan_out, + repr_scan_out => xu_mm_repr_scan_out, + time_scan_out => xu_mm_time_scan_out, + regf_scan_out => ac_an_regf_scan_out_imm(5 to 11), + xu_n_is2_flush => xu_n_is2_flush, + xu_n_rf0_flush => xu_n_rf0_flush, + xu_n_rf1_flush => xu_n_rf1_flush, + xu_n_ex1_flush => xu_n_ex1_flush, + xu_n_ex2_flush => xu_n_ex2_flush, + xu_n_ex3_flush => xu_n_ex3_flush, + xu_n_ex4_flush => xu_n_ex4_flush, + xu_n_ex5_flush => xu_n_ex5_flush, + xu_s_rf1_flush => xu_s_rf1_flush, + xu_s_ex1_flush => xu_s_ex1_flush, + xu_s_ex2_flush => xu_s_ex2_flush, + xu_s_ex3_flush => xu_s_ex3_flush, + xu_s_ex4_flush => xu_s_ex4_flush, + xu_s_ex5_flush => xu_s_ex5_flush, + xu_wu_rf1_flush => xu_wu_rf1_flush, + xu_wu_ex1_flush => xu_wu_ex1_flush, + xu_wu_ex2_flush => xu_wu_ex2_flush, + xu_wu_ex3_flush => xu_wu_ex3_flush, + xu_wu_ex4_flush => xu_wu_ex4_flush, + xu_wu_ex5_flush => xu_wu_ex5_flush, + xu_wl_rf1_flush => xu_wl_rf1_flush, + xu_wl_ex1_flush => xu_wl_ex1_flush, + xu_wl_ex2_flush => xu_wl_ex2_flush, + xu_wl_ex3_flush => xu_wl_ex3_flush, + xu_wl_ex4_flush => xu_wl_ex4_flush, + xu_wl_ex5_flush => xu_wl_ex5_flush, + xu_fu_ccr2_ap => xu_fu_ccr2_ap, + xu_fu_ex3_eff_addr => xu_fu_ex3_eff_addr, + xu_fu_ex6_load_data => xu_fu_ex6_load_data, + xu_fu_ex5_load_le => xu_fu_ex5_load_le, + xu_fu_ex5_load_tag => xu_fu_ex5_load_tag, + xu_fu_ex5_load_val => xu_fu_ex5_load_val, + xu_fu_ex5_reload_val => xu_fu_ex5_reload_val, + xu_fu_msr_fp => xu_fu_msr_fp, + xu_fu_msr_pr => xu_fu_msr_pr, + xu_fu_msr_gs => xu_fu_msr_gs, + xu_fu_msr_spv => xu_fu_msr_spv, + xu_fu_regfile_seq_beg => xu_fu_regfile_seq_beg, + xu_iu_complete_qentry => xu_iu_complete_qentry, + xu_iu_complete_target_type => xu_iu_complete_target_type, + xu_iu_complete_tid => xu_iu_complete_tid, + xu_iu_ex1_ra_entry => xu_iu_ex1_ra_entry, + xu_iu_ex1_rb => xu_iu_ex1_rb, + xu_iu_ex1_rs_is => xu_iu_ex1_rs_is, + xu_iu_ex5_bclr => xu_iu_ex5_bclr, + xu_iu_ex5_bh => xu_iu_ex5_bh, + xu_iu_ex5_br_hist => xu_iu_ex5_br_hist, + xu_iu_ex5_br_taken => xu_iu_ex5_br_taken, + xu_iu_ex5_br_update => xu_iu_ex5_br_update, + xu_iu_ex5_getNIA => xu_iu_ex5_getNIA, + xu_iu_ex5_gshare => xu_iu_ex5_gshare, + xu_iu_ex5_ifar => xu_iu_ex5_ifar, + xu_iu_ex5_lk => xu_iu_ex5_lk, + xu_iu_ex5_ppc_cpl => xu_iu_ex5_ppc_cpl, + xu_iu_ex4_loadmiss_qentry => xu_iu_ex4_loadmiss_qentry, + xu_iu_ex4_loadmiss_target => xu_iu_ex4_loadmiss_target, + xu_iu_ex4_loadmiss_target_type=> xu_iu_ex4_loadmiss_target_type, + xu_iu_ex4_loadmiss_tid => xu_iu_ex4_loadmiss_tid, + xu_iu_ex4_rs_data => xu_iu_ex4_rs_data, + xu_iu_ex5_tid => xu_iu_ex5_tid, + xu_iu_ex5_val => xu_iu_ex5_val, + xu_iu_ex5_loadmiss_qentry => xu_iu_ex5_loadmiss_qentry, + xu_iu_ex5_loadmiss_target => xu_iu_ex5_loadmiss_target, + xu_iu_ex5_loadmiss_target_type=> xu_iu_ex5_loadmiss_target_type, + xu_iu_ex5_loadmiss_tid => xu_iu_ex5_loadmiss_tid, + xu_iu_ex6_icbi_val => xu_iu_ex6_icbi_val, + xu_iu_ex6_icbi_addr => xu_iu_ex6_icbi_addr, + xu_iu_ex6_pri => xu_iu_ex6_pri, + xu_iu_ex6_pri_val => xu_iu_ex6_pri_val, + xu_iu_flush_2ucode => xu_iu_flush_2ucode, + xu_iu_flush_2ucode_type => xu_iu_flush_2ucode_type, + xu_iu_hid_mmu_mode => xu_iu_hid_mmu_mode, + xu_iu_xucr0_rel => xu_iu_xucr0_rel, + xu_iu_ici => xu_iu_ici, + xu_iu_iu0_flush_ifar0 => xu_iu_iu0_flush_ifar0, + xu_iu_iu0_flush_ifar1 => xu_iu_iu0_flush_ifar1, + xu_iu_iu0_flush_ifar2 => xu_iu_iu0_flush_ifar2, + xu_iu_iu0_flush_ifar3 => xu_iu_iu0_flush_ifar3, + xu_iu_larx_done_tid => xu_iu_larx_done_tid, + xu_iu_set_barr_tid => xu_iu_set_barr_tid, + xu_iu_membar_tid => xu_iu_membar_tid, + xu_iu_msr_cm => xu_iu_msr_cm, + xu_iu_msr_hv => xu_iu_msr_hv, + xu_iu_msr_is => xu_iu_msr_is, + xu_iu_msr_pr => xu_iu_msr_pr, + xu_iu_multdiv_done => xu_iu_multdiv_done, + xu_iu_need_hole => xu_iu_need_hole, + xu_iu_raise_iss_pri => xu_iu_raise_iss_pri, + xu_iu_ram_issue => xu_iu_ram_issue, + xu_iu_ex1_is_csync => xu_iu_ex1_is_csync, + xu_iu_ex1_is_isync => xu_iu_ex1_is_isync, + xu_iu_rf1_is_eratilx => xu_iu_rf1_is_eratilx, + xu_iu_rf1_is_eratre => xu_iu_rf1_is_eratre, + xu_iu_rf1_is_eratsx => xu_iu_rf1_is_eratsx, + xu_iu_rf1_is_eratwe => xu_iu_rf1_is_eratwe, + xu_iu_rf1_val => xu_iu_rf1_val, + xu_iu_rf1_ws => xu_iu_rf1_ws, + xu_iu_rf1_t => xu_iu_rf1_t, + xu_iu_run_thread => xu_iu_run_thread, + xu_iu_single_instr_mode => xu_iu_single_instr_mode, + xu_iu_slowspr_done => xu_iu_slowspr_done, + xu_iu_spr_ccr2_en_dcr => xu_iu_spr_ccr2_en_dcr, + xu_iu_spr_ccr2_ifratsc => xu_iu_spr_ccr2_ifratsc, + xu_iu_spr_ccr2_ifrat => xu_iu_spr_ccr2_ifrat, + xu_bx_ccr2_en_ditc => xu_bx_ccr2_en_ditc, + xu_iu_spr_xer0 => xu_iu_spr_xer0, + xu_iu_spr_xer1 => xu_iu_spr_xer1, + xu_iu_spr_xer2 => xu_iu_spr_xer2, + xu_iu_spr_xer3 => xu_iu_spr_xer3, + xu_iu_uc_flush_ifar0 => xu_iu_uc_flush_ifar0, + xu_iu_uc_flush_ifar1 => xu_iu_uc_flush_ifar1, + xu_iu_uc_flush_ifar2 => xu_iu_uc_flush_ifar2, + xu_iu_uc_flush_ifar3 => xu_iu_uc_flush_ifar3, + xu_iu_ucode_restart => xu_iu_ucode_restart, + xu_mm_derat_epn => xu_mm_derat_epn, + xu_mm_derat_lpid => xu_mm_derat_lpid, + xu_mm_derat_mmucr0 => xu_mm_derat_mmucr0, + xu_mm_derat_mmucr0_we => xu_mm_derat_mmucr0_we, + xu_mm_derat_mmucr1 => xu_mm_derat_mmucr1, + xu_mm_derat_mmucr1_we => xu_mm_derat_mmucr1_we, + xu_mm_derat_req => xu_mm_derat_req, + xu_mm_derat_snoop_ack => xu_mm_derat_snoop_ack, + xu_mm_derat_state => xu_mm_derat_state, + xu_mm_derat_thdid => xu_mm_derat_thdid, + xu_mm_derat_tid => xu_mm_derat_tid, + xu_mm_derat_ttype => xu_mm_derat_ttype, + xu_mm_ex2_eff_addr => xu_mm_ex2_eff_addr, + xu_mm_ex1_rs_is => xu_mm_ex1_rs_is, + xu_mm_ex4_flush => xu_mm_ex4_flush, + xu_mm_ex5_flush => xu_mm_ex5_flush, + xu_mm_ex5_perf_dtlb => xu_mm_ex5_perf_dtlb, + xu_mm_ex5_perf_itlb => xu_mm_ex5_perf_itlb, + xu_mm_hid_mmu_mode => xu_mm_hid_mmu_mode, + xu_mm_hold_ack => xu_mm_hold_ack, + xu_mm_ierat_flush => xu_mm_ierat_flush, + xu_mm_ierat_miss => xu_mm_ierat_miss, + xu_mm_lmq_stq_empty => xu_mm_lmq_stq_empty, + xu_mm_lsu_token => xu_mm_lsu_token, + xu_mm_msr_cm => xu_mm_msr_cm, + xu_mm_msr_ds => xu_mm_msr_ds, + xu_mm_msr_gs => xu_mm_msr_gs, + xu_iu_msr_gs => xu_iu_msr_gs, + xu_mm_msr_is => xu_mm_msr_is, + xu_mm_msr_pr => xu_mm_msr_pr, + xu_mm_ex1_is_csync => xu_mm_ex1_is_csync, + xu_mm_ex1_is_isync => xu_mm_ex1_is_isync, + xu_mm_rf1_is_eratilx => xu_mm_rf1_is_eratilx, + xu_mm_rf1_is_erativax => xu_mm_rf1_is_erativax, + xu_mm_rf1_is_tlbilx => xu_mm_rf1_is_tlbilx, + xu_mm_rf1_is_tlbivax => xu_mm_rf1_is_tlbivax, + xu_mm_rf1_is_tlbre => xu_mm_rf1_is_tlbre, + xu_mm_rf1_is_tlbsx => xu_mm_rf1_is_tlbsx, + xu_mm_rf1_is_tlbsrx => xu_mm_rf1_is_tlbsrx, + xu_mm_rf1_is_tlbwe => xu_mm_rf1_is_tlbwe, + xu_mm_rf1_val => xu_mm_rf1_val, + xu_mm_rf1_t => xu_mm_rf1_t, + xu_mm_spr_epcr_dgtmi => xu_mm_spr_epcr_dgtmi, + xu_mm_spr_epcr_dmiuh => xu_mm_spr_epcr_dmiuh, + slowspr_addr_out => xu_mm_slowspr_addr, + slowspr_data_out => xu_mm_slowspr_data, + slowspr_done_out => xu_mm_slowspr_done, + slowspr_etid_out => xu_mm_slowspr_etid, + slowspr_rw_out => xu_mm_slowspr_rw, + slowspr_val_out => xu_mm_slowspr_val, + debug_data_out => xu_mm_debug_data, + trigger_data_out => xu_mm_trigger_data, + xu_pc_bo_fail => xu_pc_bo_fail, + xu_pc_bo_diagout => xu_pc_bo_diagout, + xu_pc_err_attention_instr => xu_pc_err_attention_instr, + xu_pc_err_dcache_parity => xu_pc_err_dcache_parity, + xu_pc_err_dcachedir_multihit => xu_pc_err_dcachedir_multihit, + xu_pc_err_dcachedir_parity => xu_pc_err_dcachedir_parity, + xu_pc_err_debug_event => xu_pc_err_debug_event, + xu_pc_err_mcsr_summary => xu_pc_err_mcsr_summary, + xu_pc_err_ierat_parity => xu_pc_err_ierat_parity, + xu_pc_err_derat_parity => xu_pc_err_derat_parity, + xu_pc_err_ditc_overrun => xu_pc_err_ditc_overrun, + xu_pc_err_tlb_parity => xu_pc_err_tlb_parity, + xu_pc_err_tlb_lru_parity => xu_pc_err_tlb_lru_parity, + xu_pc_err_ierat_multihit => xu_pc_err_ierat_multihit, + xu_pc_err_derat_multihit => xu_pc_err_derat_multihit, + xu_pc_err_tlb_multihit => xu_pc_err_tlb_multihit, + xu_pc_err_ext_mchk => xu_pc_err_ext_mchk, + xu_pc_err_local_snoop_reject => xu_pc_err_local_snoop_reject, + xu_pc_err_l2intrf_ecc => xu_pc_err_l2intrf_ecc, + xu_pc_err_l2intrf_ue => xu_pc_err_l2intrf_ue, + xu_pc_err_llbust_attempt => xu_pc_err_llbust_attempt, + xu_pc_err_llbust_failed => xu_pc_err_llbust_failed, + xu_pc_err_nia_miscmpr => xu_pc_err_nia_miscmpr, + xu_pc_err_regfile_parity => xu_pc_err_regfile_parity, + xu_pc_err_regfile_ue => xu_pc_err_regfile_ue, + xu_pc_err_sprg_ecc => xu_pc_err_sprg_ecc, + xu_pc_err_sprg_ue => xu_pc_err_sprg_ue, + xu_pc_err_wdt_reset => xu_pc_err_wdt_reset, + xu_pc_err_invld_reld => xu_pc_err_invld_reld, + xu_pc_err_l2credit_overrun => xu_pc_err_l2credit_overrun, + xu_pc_lsu_event_data => xu_pc_lsu_event_data, + xu_pc_event_data => xu_pc_event_data, + xu_pc_ram_data => xu_pc_ram_data, + xu_pc_ram_done => xu_pc_ram_done, + xu_pc_ram_interrupt => xu_pc_ram_interrupt, + xu_pc_running => xu_pc_running, + xu_pc_step_done => xu_pc_step_done, + xu_pc_stop_dbg_event => xu_pc_stop_dbg_event, + xu_bx_ex1_mtdp_val => xu_bx_ex1_mtdp_val , + xu_bx_ex1_mfdp_val => xu_bx_ex1_mfdp_val , + xu_bx_ex1_ipc_thrd => xu_bx_ex1_ipc_thrd , + xu_bx_ex2_ipc_ba => xu_bx_ex2_ipc_ba , + xu_bx_ex2_ipc_sz => xu_bx_ex2_ipc_sz , + xu_bx_ex4_256st_data => xu_bx_ex4_256st_data(128 to 255) , + xu_iu_reld_core_tag => xu_iu_reld_core_tag, + xu_iu_reld_core_tag_clone => xu_iu_reld_core_tag_clone, + xu_iu_reld_data => xu_iu_reld_data, + xu_iu_reld_data_coming_clone => xu_iu_reld_data_coming_clone, + xu_iu_reld_data_vld => xu_iu_reld_data_vld, + xu_iu_reld_data_vld_clone => xu_iu_reld_data_vld_clone, + xu_iu_reld_ditc_clone => xu_iu_reld_ditc_clone, + xu_iu_reld_ecc_err => xu_iu_reld_ecc_err, + xu_iu_reld_ecc_err_ue => xu_iu_reld_ecc_err_ue, + xu_iu_reld_qw => xu_iu_reld_qw, + + bx_xu_ex4_mtdp_cr_status => bx_xu_ex4_mtdp_cr_status , + bx_xu_ex4_mfdp_cr_status => bx_xu_ex4_mfdp_cr_status , + bx_xu_ex5_dp_data => bx_xu_ex5_dp_data , + bx_xu_quiesce => bx_xu_quiesce, + + -- outputs to network or l2 from outbox + bx_lsu_ob_pwr_tok => bx_lsu_ob_pwr_tok , + bx_lsu_ob_req_val => bx_lsu_ob_req_val , + bx_lsu_ob_ditc_val => bx_lsu_ob_ditc_val, + bx_lsu_ob_thrd => bx_lsu_ob_thrd , + bx_lsu_ob_qw => bx_lsu_ob_qw , + bx_lsu_ob_dest => bx_lsu_ob_dest , + bx_lsu_ob_data => bx_lsu_ob_data , + bx_lsu_ob_addr => bx_lsu_ob_addr , + -- inputs from lsu + lsu_bx_cmd_avail => lsu_bx_cmd_avail , + lsu_bx_cmd_sent => lsu_bx_cmd_sent , + lsu_bx_cmd_stall => lsu_bx_cmd_stall , + + + + ac_an_reld_ditc_pop_int => ac_an_reld_ditc_pop_int, + ac_an_reld_ditc_pop_q => ac_an_reld_ditc_pop_imm, + bx_ib_empty_int => bx_ib_empty_int, + bx_ib_empty_q => ac_an_box_empty_imm, + xu_iu_l_flush => xu_iu_l_flush, + xu_iu_u_flush => xu_iu_u_flush, + xu_pc_err_mchk_disabled => xu_pc_err_mchk_disabled, + xu_fu_lbist_ary_wrt_thru_dc => xu_fu_lbist_ary_wrt_thru_dc, + xu_fu_lbist_en_dc => xu_fu_lbist_en_dc, + xu_iu_xucr4_mmu_mchk => xu_iu_xucr4_mmu_mchk, + xu_mm_xucr4_mmu_mchk => xu_mm_xucr4_mmu_mchk, + + gnd => gnd, + vcs => vcs, + vdd => vdd + ); -- end component a_xuq + + ac_an_st_byte_enbl_imm <= xu_st_byte_enbl; + ac_an_st_data_imm <= xu_st_data; + + + + + + +a_mmq: entity work.mmq + generic map(data_out_width => data_out_width, + debug_event_width => debug_event_width, + debug_trace_width => debug_trace_width, + epn_width => epn_width, + eptr_width => eptr_width, + erat_ary_data_width => erat_ary_data_width, + erat_cam_data_width => erat_cam_data_width, + erat_rel_data_width => erat_rel_data_width, + error_width => error_width, + expand_tlb_type => expand_tlb_type, + expand_type => expand_type, + extclass_width => extclass_width, + inv_seq_width => inv_seq_width, + lpid_width => lpid_width, + lru_width => lru_width, + mmucr0_width => mmucr0_width, + mmucr1_width => mmucr1_width, + mmucr2_width => mmucr2_width, + mmucr3_width => mmucr3_width, + pid_width => pid_width, + por_seq_width => por_seq_width, + ra_entry_width => ra_entry_width, + real_addr_width => real_addr_width, + req_epn_width => req_epn_width, + rpn_width => rpn_width, + rs_data_width => rs_data_width, + rs_is_width => rs_is_width, + spr_addr_width => spr_addr_width, + spr_ctl_width => spr_ctl_width, + spr_data_width => spr_data_width, + spr_etid_width => spr_etid_width, + state_width => state_width, + thdid_width => thdid_width, + tlb_addr_width => tlb_addr_width, + tlb_num_entry => tlb_num_entry, + tlb_num_entry_log2 => tlb_num_entry_log2, + tlb_seq_width => tlb_seq_width, + tlb_tag_width => tlb_tag_width, + tlb_way_width => tlb_way_width, + tlb_ways => tlb_ways, + tlb_word_width => tlb_word_width, + tlbsel_width => tlbsel_width, + ttype_width => ttype_width, + vpn_width => vpn_width, + watermark_width => watermark_width, + ws_width => ws_width) + port map ( + an_ac_abst_scan_in => an_ac_abst_scan_in(0 to 9), + an_ac_bcfg_scan_in => an_ac_bcfg_scan_in(0 to 4), + an_ac_dcfg_scan_in => an_ac_dcfg_scan_in(0 to 2), + an_ac_func_scan_in => an_ac_func_scan_in(0 to 63), + gptr_scan_in => xu_mm_gptr_scan_out, + repr_scan_in => xu_mm_repr_scan_out, + time_scan_in => xu_mm_time_scan_out, + an_ac_back_inv => an_ac_back_inv, + an_ac_back_inv_addr => an_ac_back_inv_addr, + an_ac_back_inv_lbit => an_ac_back_inv_lbit, + an_ac_back_inv_gs => an_ac_back_inv_gs, + an_ac_back_inv_ind => an_ac_back_inv_ind, + an_ac_back_inv_local => an_ac_back_inv_local, + an_ac_back_inv_lpar_id => an_ac_back_inv_lpar_id, + an_ac_back_inv_target => an_ac_back_inv_target, + an_ac_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc, + an_ac_reld_core_tag => an_ac_reld_core_tag, + an_ac_reld_data => an_ac_reld_data, + an_ac_reld_data_vld => an_ac_reld_data_vld, + an_ac_reld_ecc_err => an_ac_reld_ecc_err, + an_ac_reld_ecc_err_ue => an_ac_reld_ecc_err_ue, + an_ac_reld_qw => an_ac_reld_qw(57 to 59), + an_ac_reld_ditc => an_ac_reld_ditc, + an_ac_reld_crit_qw => an_ac_reld_crit_qw, + iu_mm_ierat_epn => iu_mm_ierat_epn, + iu_mm_ierat_flush => iu_mm_ierat_flush, + iu_mm_ierat_mmucr0 => iu_mm_ierat_mmucr0, + iu_mm_ierat_mmucr0_we => iu_mm_ierat_mmucr0_we, + iu_mm_ierat_mmucr1 => iu_mm_ierat_mmucr1, + iu_mm_ierat_mmucr1_we => iu_mm_ierat_mmucr1_we, + iu_mm_ierat_req => iu_mm_ierat_req, + iu_mm_ierat_snoop_ack => iu_mm_ierat_snoop_ack, + iu_mm_ierat_thdid => iu_mm_ierat_thdid, + iu_mm_ierat_tid => iu_mm_ierat_tid, + iu_mm_ierat_state => iu_mm_ierat_state, + iu_mm_lmq_empty => iu_mm_lmq_empty, + nclk => a2_nclk, + pc_mm_abist_dcomp_g6t_2r => pc_mm_abist_dcomp_g6t_2r_oiu, + pc_mm_abist_di_0 => pc_mm_abist_di_0_oiu, + pc_mm_abist_di_g6t_2r => pc_mm_abist_di_g6t_2r_oiu, + pc_mm_abist_ena_dc => pc_mm_abist_ena_dc_oiu, + pc_mm_abist_g6t_r_wb => pc_mm_abist_g6t_r_wb_oiu, + pc_mm_abist_g8t1p_renb_0 => pc_mm_abist_g8t1p_renb_0_oiu, + pc_mm_abist_g8t_bw_0 => pc_mm_abist_g8t_bw_0_oiu, + pc_mm_abist_g8t_bw_1 => pc_mm_abist_g8t_bw_1_oiu, + pc_mm_abist_g8t_dcomp => pc_mm_abist_g8t_dcomp_oiu, + pc_mm_abist_g8t_wenb => pc_mm_abist_g8t_wenb_oiu, + pc_mm_abist_raddr_0 => pc_mm_abist_raddr_0_oiu, + pc_mm_abist_raw_dc_b => pc_mm_abist_raw_dc_b_oiu, + pc_mm_abist_waddr_0 => pc_mm_abist_waddr_0_oiu, + pc_mm_abist_wl128_comp_ena => pc_mm_abist_wl128_comp_ena_oiu, + pc_mm_abst_sl_thold_3 => pc_mm_abst_sl_thold_3_oiu, + pc_mm_abst_slp_sl_thold_3 => pc_mm_abst_slp_sl_thold_3_oiu, + pc_mm_ary_nsl_thold_3 => pc_mm_ary_nsl_thold_3_oiu, + pc_mm_ary_slp_nsl_thold_3 => pc_mm_ary_slp_nsl_thold_3_oiu, + pc_mm_bolt_sl_thold_3 => pc_mm_bolt_sl_thold_3_oiu, + pc_mm_bo_enable_3 => pc_mm_bo_enable_3_oiu, + pc_mm_bo_reset => pc_mm_bo_reset_oiu, + pc_mm_bo_unload => pc_mm_bo_unload_oiu, + pc_mm_bo_repair => pc_mm_bo_repair_oiu, + pc_mm_bo_shdata => pc_mm_bo_shdata_oiu, + pc_mm_bo_select => pc_mm_bo_select_oiu, + pc_mm_cfg_sl_thold_3 => pc_mm_cfg_sl_thold_3_oiu, + pc_mm_cfg_slp_sl_thold_3 => pc_mm_cfg_slp_sl_thold_3_oiu, + pc_mm_debug_mux1_ctrls => pc_mm_debug_mux1_ctrls_oiu, + pc_mm_event_count_mode => pc_mm_event_count_mode_oiu, + pc_mm_event_mux_ctrls => pc_mm_event_mux_ctrls_oiu, + pc_mm_fce_3 => pc_mm_fce_3_oiu, + pc_mm_func_nsl_thold_3 => pc_mm_func_nsl_thold_3_oiu, + pc_mm_func_sl_thold_3 => pc_mm_func_sl_thold_3_oiu, + pc_mm_func_slp_nsl_thold_3 => pc_mm_func_slp_nsl_thold_3_oiu, + pc_mm_func_slp_sl_thold_3 => pc_mm_func_slp_sl_thold_3_oiu, + pc_mm_gptr_sl_thold_3 => pc_mm_gptr_sl_thold_3_oiu, + pc_mm_repr_sl_thold_3 => pc_mm_repr_sl_thold_3_oiu, + pc_mm_sg_3 => pc_mm_sg_3_oiu, + pc_mm_time_sl_thold_3 => pc_mm_time_sl_thold_3_oiu, + pc_mm_trace_bus_enable => pc_mm_trace_bus_enable_oiu, + rp_mm_event_bus_enable_q => rp_mm_event_bus_enable_q, + tc_ac_ccflush_dc => pc_mm_ccflush_dc_oiu, + tc_ac_lbist_en_dc => an_ac_lbist_en_dc, + tc_ac_scan_diag_dc => an_ac_scan_diag_dc, + tc_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b, + debug_bus_in => xu_mm_debug_data, + trace_triggers_in => xu_mm_trigger_data, + xu_ex1_flush => xu_s_ex1_flush, + xu_ex2_flush => xu_s_ex2_flush, + xu_ex3_flush => xu_s_ex3_flush, + xu_ex4_flush => xu_s_ex4_flush, + xu_ex5_flush => xu_s_ex5_flush, + mm_xu_cr0_eq => mm_xu_cr0_eq, + mm_xu_cr0_eq_valid => mm_xu_cr0_eq_valid, + xu_mm_derat_epn => xu_mm_derat_epn, + xu_mm_derat_lpid => xu_mm_derat_lpid, + xu_mm_derat_mmucr0 => xu_mm_derat_mmucr0, + xu_mm_derat_mmucr0_we => xu_mm_derat_mmucr0_we, + xu_mm_derat_mmucr1 => xu_mm_derat_mmucr1, + xu_mm_derat_mmucr1_we => xu_mm_derat_mmucr1_we, + xu_mm_derat_req => xu_mm_derat_req, + xu_mm_derat_snoop_ack => xu_mm_derat_snoop_ack, + xu_mm_derat_state => xu_mm_derat_state, + xu_mm_derat_thdid => xu_mm_derat_thdid, + xu_mm_derat_tid => xu_mm_derat_tid, + xu_mm_derat_ttype => xu_mm_derat_ttype, + xu_mm_ex2_eff_addr => xu_mm_ex2_eff_addr, + xu_mm_ex1_rs_is => xu_mm_ex1_rs_is, + xu_mm_ex4_flush => xu_mm_ex4_flush, + xu_mm_ex5_flush => xu_mm_ex5_flush, + xu_mm_ex5_perf_dtlb => xu_mm_ex5_perf_dtlb, + xu_mm_ex5_perf_itlb => xu_mm_ex5_perf_itlb, + xu_mm_hid_mmu_mode => xu_mm_hid_mmu_mode, + xu_mm_hold_ack => xu_mm_hold_ack, + xu_mm_ierat_flush => xu_mm_ierat_flush, + xu_mm_ierat_miss => xu_mm_ierat_miss, + xu_mm_lmq_stq_empty => xu_mm_lmq_stq_empty, + xu_mm_lsu_token => xu_mm_lsu_token, + xu_mm_msr_cm => xu_mm_msr_cm, + xu_mm_msr_ds => xu_mm_msr_ds, + xu_mm_msr_gs => xu_mm_msr_gs, + xu_mm_msr_is => xu_mm_msr_is, + xu_mm_msr_pr => xu_mm_msr_pr, + xu_mm_ex1_is_csync => xu_mm_ex1_is_csync, + xu_mm_ex1_is_isync => xu_mm_ex1_is_isync, + xu_mm_rf1_is_eratilx => xu_mm_rf1_is_eratilx, + xu_mm_rf1_is_erativax => xu_mm_rf1_is_erativax, + xu_mm_rf1_is_tlbilx => xu_mm_rf1_is_tlbilx, + xu_mm_rf1_is_tlbivax => xu_mm_rf1_is_tlbivax, + xu_mm_rf1_is_tlbre => xu_mm_rf1_is_tlbre, + xu_mm_rf1_is_tlbsx => xu_mm_rf1_is_tlbsx, + xu_mm_rf1_is_tlbsxr => xu_mm_rf1_is_tlbsxr, + xu_mm_rf1_is_tlbsrx => xu_mm_rf1_is_tlbsrx, + xu_mm_rf1_is_tlbwe => xu_mm_rf1_is_tlbwe, + xu_mm_rf1_val => xu_mm_rf1_val, + xu_mm_rf1_t => xu_mm_rf1_t, + xu_mm_spr_epcr_dgtmi => xu_mm_spr_epcr_dgtmi, + xu_mm_spr_epcr_dmiuh => xu_mm_spr_epcr_dmiuh, + slowspr_addr_in => xu_mm_slowspr_addr, + slowspr_data_in => xu_mm_slowspr_data, + slowspr_done_in => xu_mm_slowspr_done, + slowspr_etid_in => xu_mm_slowspr_etid, + slowspr_rw_in => xu_mm_slowspr_rw, + slowspr_val_in => xu_mm_slowspr_val, + xu_rf1_flush => xu_s_rf1_flush, + bcfg_scan_out => mm_rp_bcfg_scan_out, + ccfg_scan_out => mm_iu_ccfg_scan_out, + dcfg_scan_out => mm_rp_dcfg_scan_out, + ac_an_gptr_scan_out => ac_an_gptr_scan_out, + ac_an_repr_scan_out => ac_an_repr_scan_out, + ac_an_time_scan_out => ac_an_time_scan_out, + ac_an_back_inv_reject => ac_an_back_inv_reject, + ac_an_lpar_id => ac_an_lpar_id, + mm_iu_barrier_done => mm_iu_barrier_done, + mm_iu_ierat_mmucr0_0 => mm_iu_ierat_mmucr0_0, + mm_iu_ierat_mmucr0_1 => mm_iu_ierat_mmucr0_1, + mm_iu_ierat_mmucr0_2 => mm_iu_ierat_mmucr0_2, + mm_iu_ierat_mmucr0_3 => mm_iu_ierat_mmucr0_3, + mm_iu_ierat_mmucr1 => mm_iu_ierat_mmucr1, + mm_iu_ierat_pid0 => mm_iu_ierat_pid0, + mm_iu_ierat_pid1 => mm_iu_ierat_pid1, + mm_iu_ierat_pid2 => mm_iu_ierat_pid2, + mm_iu_ierat_pid3 => mm_iu_ierat_pid3, + mm_iu_ierat_rel_data => mm_iu_ierat_rel_data, + mm_iu_ierat_rel_val => mm_iu_ierat_rel_val, + mm_iu_ierat_snoop_attr => mm_iu_ierat_snoop_attr, + mm_iu_ierat_snoop_coming => mm_iu_ierat_snoop_coming, + mm_iu_ierat_snoop_val => mm_iu_ierat_snoop_val, + mm_iu_ierat_snoop_vpn => mm_iu_ierat_snoop_vpn, + slowspr_addr_out => mm_iu_slowspr_addr, + slowspr_data_out => mm_iu_slowspr_data, + slowspr_done_out => mm_iu_slowspr_done, + slowspr_etid_out => mm_iu_slowspr_etid, + slowspr_rw_out => mm_iu_slowspr_rw, + slowspr_val_out => mm_iu_slowspr_val, + debug_bus_out => ac_an_debug_bus_int, + trace_triggers_out => ac_an_trace_triggers, + mm_pc_bo_diagout => mm_pc_bo_diagout_iiu, + mm_pc_bo_fail => mm_pc_bo_fail_iiu, + mm_pc_event_data => mm_pc_event_data_iiu, + mm_xu_derat_mmucr0_0 => mm_xu_derat_mmucr0_0, + mm_xu_derat_mmucr0_1 => mm_xu_derat_mmucr0_1, + mm_xu_derat_mmucr0_2 => mm_xu_derat_mmucr0_2, + mm_xu_derat_mmucr0_3 => mm_xu_derat_mmucr0_3, + mm_xu_derat_mmucr1 => mm_xu_derat_mmucr1, + mm_xu_derat_pid0 => mm_xu_derat_pid0, + mm_xu_derat_pid1 => mm_xu_derat_pid1, + mm_xu_derat_pid2 => mm_xu_derat_pid2, + mm_xu_derat_pid3 => mm_xu_derat_pid3, + mm_xu_derat_rel_data => mm_xu_derat_rel_data, + mm_xu_derat_rel_val => mm_xu_derat_rel_val, + mm_xu_derat_snoop_attr => mm_xu_derat_snoop_attr, + mm_xu_derat_snoop_coming => mm_xu_derat_snoop_coming, + mm_xu_derat_snoop_val => mm_xu_derat_snoop_val, + mm_xu_derat_snoop_vpn => mm_xu_derat_snoop_vpn, + mm_xu_eratmiss_done => mm_xu_eratmiss_done, + mm_xu_esr_pt => mm_xu_esr_pt, + mm_xu_esr_data => mm_xu_esr_data, + mm_xu_esr_epid => mm_xu_esr_epid, + mm_xu_esr_st => mm_xu_esr_st, + mm_xu_ex3_flush_req => mm_xu_ex3_flush_req, + mm_xu_hold_done => mm_xu_hold_done, + mm_xu_hold_req => mm_xu_hold_req, + mm_xu_hv_priv => mm_xu_hv_priv, + mm_xu_illeg_instr => mm_xu_illeg_instr, + mm_xu_local_snoop_reject => mm_xu_local_snoop_reject, + mm_xu_lrat_miss => mm_xu_lrat_miss, + mm_xu_lsu_addr => mm_xu_lsu_addr, + mm_xu_lsu_lpid => mm_xu_lsu_lpid, + mm_xu_lsu_lpidr => mm_xu_lsu_lpidr, + mm_xu_lsu_gs => mm_xu_lsu_gs, + mm_xu_lsu_ind => mm_xu_lsu_ind, + mm_xu_lsu_lbit => mm_xu_lsu_lbit, + mm_xu_lsu_req => mm_xu_lsu_req, + mm_xu_lsu_ttype => mm_xu_lsu_ttype, + mm_xu_lsu_u => mm_xu_lsu_u, + mm_xu_lsu_wimge => mm_xu_lsu_wimge, + mm_xu_pt_fault => mm_xu_pt_fault, + mm_xu_quiesce => mm_xu_quiesce, + mm_xu_tlb_inelig => mm_xu_tlb_inelig, + mm_xu_tlb_miss => mm_xu_tlb_miss, + mm_xu_tlb_multihit_err => mm_xu_tlb_multihit_err, + mm_xu_tlb_par_err => mm_xu_tlb_par_err, + mm_xu_lru_par_err => mm_xu_lru_par_err, + + an_ac_reld_data_coming => an_ac_reld_data_coming, + an_ac_reld_l1_dump => an_ac_reld_l1_dump, + an_ac_grffence_en_dc => an_ac_camfence_en_dc, + an_ac_stcx_complete => an_ac_stcx_complete, + an_ac_abist_mode_dc => an_ac_abist_mode_dc, + an_ac_abist_start_test => an_ac_abist_start_test, + an_ac_atpg_en_dc => an_ac_atpg_en_dc, + an_ac_ccflush_dc => an_ac_ccflush_dc, + an_ac_reset_1_complete => an_ac_reset_1_complete, + an_ac_reset_2_complete => an_ac_reset_2_complete, + an_ac_reset_3_complete => an_ac_reset_3_complete, + an_ac_reset_wd_complete => an_ac_reset_wd_complete, + an_ac_debug_stop => an_ac_debug_stop, + an_ac_lbist_en_dc => an_ac_lbist_en_dc, + an_ac_pm_thread_stop => an_ac_pm_thread_stop, + an_ac_regf_scan_in => an_ac_regf_scan_in, + an_ac_scan_diag_dc => an_ac_scan_diag_dc, + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b, + an_ac_scom_cch => an_ac_scom_cch, + an_ac_scom_dch => an_ac_scom_dch, + an_ac_checkstop => an_ac_checkstop, +-- _omm suffix means output from mmu + an_ac_back_inv_omm => an_ac_back_inv_omm, + an_ac_back_inv_addr_omm => an_ac_back_inv_addr_omm, + an_ac_back_inv_target_omm_iua => an_ac_back_inv_target_omm_iua, + an_ac_back_inv_target_omm_iub => an_ac_back_inv_target_omm_iub, + an_ac_reld_core_tag_omm => an_ac_reld_core_tag_omm, + an_ac_reld_data_omm => an_ac_reld_data_omm, + an_ac_reld_data_vld_omm => an_ac_reld_data_vld_omm, + an_ac_reld_ecc_err_omm => an_ac_reld_ecc_err_omm, + an_ac_reld_ecc_err_ue_omm => an_ac_reld_ecc_err_ue_omm, + an_ac_reld_qw_omm => an_ac_reld_qw_omm, + an_ac_reld_ditc_omm => an_ac_reld_ditc_omm, + an_ac_reld_crit_qw_omm => an_ac_reld_crit_qw_omm, + an_ac_reld_data_coming_omm => an_ac_reld_data_coming_omm, + an_ac_reld_l1_dump_omm => an_ac_reld_l1_dump_omm, + an_ac_grffence_en_dc_omm => an_ac_camfence_en_dc_omm, + an_ac_stcx_complete_omm => an_ac_stcx_complete_omm, + an_ac_abist_mode_dc_omm => an_ac_abist_mode_dc_omm, + an_ac_abist_start_test_omm => an_ac_abist_start_test_omm, + an_ac_abst_scan_in_omm_iu => an_ac_abst_scan_in_omm_iu, + an_ac_abst_scan_in_omm_xu => an_ac_abst_scan_in_omm_xu, + an_ac_atpg_en_dc_omm => an_ac_atpg_en_dc_omm, + an_ac_bcfg_scan_in_omm_bit1 => an_ac_bcfg_scan_in_omm_bit1, + an_ac_bcfg_scan_in_omm_bit3 => an_ac_bcfg_scan_in_omm_bit3, + an_ac_bcfg_scan_in_omm_bit4 => an_ac_bcfg_scan_in_omm_bit4, + an_ac_lbist_ary_wrt_thru_dc_omm => an_ac_lbist_ary_wrt_thru_dc_omm, + an_ac_ccflush_dc_omm => an_ac_ccflush_dc_omm, + an_ac_reset_1_complete_omm => an_ac_reset_1_complete_omm, + an_ac_reset_2_complete_omm => an_ac_reset_2_complete_omm, + an_ac_reset_3_complete_omm => an_ac_reset_3_complete_omm, + an_ac_reset_wd_complete_omm => an_ac_reset_wd_complete_omm, + an_ac_dcfg_scan_in_omm => an_ac_dcfg_scan_in_omm, + an_ac_debug_stop_omm => an_ac_debug_stop_omm, + an_ac_func_scan_in_omm_iua => an_ac_func_scan_in_omm_iua, + an_ac_func_scan_in_omm_iub => an_ac_func_scan_in_omm_iub, + an_ac_func_scan_in_omm_xu => an_ac_func_scan_in_omm_xu, + an_ac_lbist_en_dc_omm => an_ac_lbist_en_dc_omm, + an_ac_pm_thread_stop_omm => an_ac_pm_thread_stop_omm, + an_ac_regf_scan_in_omm => an_ac_regf_scan_in_omm, + an_ac_scan_diag_dc_omm => an_ac_scan_diag_dc_omm, + an_ac_scan_dis_dc_b_omm => an_ac_scan_dis_dc_b_omm, + an_ac_scom_cch_omm => an_ac_scom_cch_omm, + an_ac_scom_dch_omm => an_ac_scom_dch_omm, + an_ac_checkstop_omm => an_ac_checkstop_omm, +-- _imm prefix means input to mmu + ac_an_abst_scan_out_imm_iu => ac_an_abst_scan_out_imm_iu, + ac_an_abst_scan_out_imm_xu => ac_an_abst_scan_out_imm_xu, + ac_an_bcfg_scan_out_imm => ac_an_bcfg_scan_out_imm, + ac_an_dcfg_scan_out_imm => ac_an_dcfg_scan_out_imm, + ac_an_func_scan_out_imm_iua => ac_an_func_scan_out_imm_iua, + ac_an_func_scan_out_imm_iub => ac_an_func_scan_out_imm_iub, + ac_an_func_scan_out_imm_xu => ac_an_func_scan_out_imm_xu, + ac_an_reld_ditc_pop_imm => ac_an_reld_ditc_pop_imm, + ac_an_power_managed_imm => ac_an_power_managed_imm, + ac_an_rvwinkle_mode_imm => ac_an_rvwinkle_mode_imm, + ac_an_fu_bypass_events_imm => ac_an_fu_bypass_events_imm, + ac_an_iu_bypass_events_imm => ac_an_iu_bypass_events_imm, + ac_an_mm_bypass_events_imm => ac_an_mm_bypass_events_imm, + ac_an_lsu_bypass_events_imm => ac_an_lsu_bypass_events_imm, + ac_an_event_bus_imm => ac_an_event_bus_imm, + ac_an_pm_thread_running_imm => ac_an_pm_thread_running_imm, + ac_an_recov_err_imm => ac_an_recov_err_imm, + ac_an_regf_scan_out_imm => ac_an_regf_scan_out_imm, + ac_an_scom_cch_imm => ac_an_scom_cch_imm, + ac_an_scom_dch_imm => ac_an_scom_dch_imm, + ac_an_special_attn_imm => ac_an_special_attn_imm, + ac_an_checkstop_imm => ac_an_checkstop_imm, + ac_an_local_checkstop_imm => ac_an_local_checkstop_imm, + ac_an_trace_error_imm => ac_an_trace_error_imm, + ac_an_abst_scan_out => ac_an_abst_scan_out, + ac_an_bcfg_scan_out => ac_an_bcfg_scan_out, + ac_an_dcfg_scan_out => ac_an_dcfg_scan_out, + ac_an_func_scan_out => ac_an_func_scan_out, + ac_an_reld_ditc_pop => ac_an_reld_ditc_pop, + ac_an_power_managed => ac_an_power_managed, + ac_an_rvwinkle_mode => ac_an_rvwinkle_mode, + ac_an_fu_bypass_events => ac_an_fu_bypass_events, + ac_an_iu_bypass_events => ac_an_iu_bypass_events, + ac_an_mm_bypass_events => ac_an_mm_bypass_events, + ac_an_lsu_bypass_events => ac_an_lsu_bypass_events, + ac_an_event_bus => ac_an_event_bus, + ac_an_pm_thread_running => ac_an_pm_thread_running, + ac_an_recov_err => ac_an_recov_err, + ac_an_regf_scan_out => ac_an_regf_scan_out, + ac_an_scom_cch => ac_an_scom_cch, + ac_an_scom_dch => ac_an_scom_dch, + ac_an_special_attn => ac_an_special_attn, + ac_an_checkstop => ac_an_checkstop, + ac_an_local_checkstop => ac_an_local_checkstop, + ac_an_trace_error => ac_an_trace_error, + an_ac_dcr_act => an_ac_dcr_act, + an_ac_dcr_val => an_ac_dcr_val, + an_ac_dcr_read => an_ac_dcr_read, + an_ac_dcr_etid => an_ac_dcr_etid, + an_ac_dcr_data => an_ac_dcr_data, + an_ac_dcr_done => an_ac_dcr_done, + an_ac_crit_interrupt => an_ac_crit_interrupt, + an_ac_ext_interrupt => an_ac_ext_interrupt, + an_ac_flh2l2_gate => an_ac_flh2l2_gate, + an_ac_icbi_ack => an_ac_icbi_ack, + an_ac_icbi_ack_thread => an_ac_icbi_ack_thread, + an_ac_req_ld_pop => an_ac_req_ld_pop, + an_ac_req_spare_ctrl_a1 => an_ac_req_spare_ctrl_a1, + an_ac_req_st_gather => an_ac_req_st_gather, + an_ac_req_st_pop => an_ac_req_st_pop, + an_ac_req_st_pop_thrd => an_ac_req_st_pop_thrd, + an_ac_reservation_vld => an_ac_reservation_vld, + an_ac_sleep_en => an_ac_sleep_en, + an_ac_stcx_pass => an_ac_stcx_pass, + an_ac_sync_ack => an_ac_sync_ack, + an_ac_ary_nsl_thold_7 => an_ac_ary_nsl_thold_7, + an_ac_ccenable_dc => an_ac_ccenable_dc, + an_ac_coreid => an_ac_coreid, + an_ac_external_mchk => an_ac_external_mchk, + an_ac_fce_7 => an_ac_fce_7, + an_ac_func_nsl_thold_7 => an_ac_func_nsl_thold_7, + an_ac_func_sl_thold_7 => an_ac_func_sl_thold_7, + an_ac_gsd_test_enable_dc => an_ac_gsd_test_enable_dc, + an_ac_gsd_test_acmode_dc => an_ac_gsd_test_acmode_dc, + an_ac_gptr_scan_in => an_ac_gptr_scan_in, + an_ac_hang_pulse => an_ac_hang_pulse, + an_ac_lbist_ac_mode_dc => an_ac_lbist_ac_mode_dc, + an_ac_lbist_ip_dc => an_ac_lbist_ip_dc, + an_ac_malf_alert => an_ac_malf_alert, + an_ac_perf_interrupt => an_ac_perf_interrupt, + an_ac_psro_enable_dc => an_ac_psro_enable_dc, + an_ac_repr_scan_in => an_ac_repr_scan_in, + an_ac_rtim_sl_thold_7 => an_ac_rtim_sl_thold_7, + an_ac_scan_type_dc => an_ac_scan_type_dc, + an_ac_scom_sat_id => an_ac_scom_sat_id, + an_ac_sg_7 => an_ac_sg_7, + an_ac_tb_update_enable => an_ac_tb_update_enable, + an_ac_tb_update_pulse => an_ac_tb_update_pulse, + an_ac_time_scan_in => an_ac_time_scan_in, + an_ac_crit_interrupt_omm => an_ac_crit_interrupt_omm, + an_ac_ext_interrupt_omm => an_ac_ext_interrupt_omm, + an_ac_flh2l2_gate_omm => an_ac_flh2l2_gate_omm, + an_ac_icbi_ack_omm => an_ac_icbi_ack_omm, + an_ac_icbi_ack_thread_omm => an_ac_icbi_ack_thread_omm, + an_ac_req_ld_pop_omm => an_ac_req_ld_pop_omm, + an_ac_req_spare_ctrl_a1_omm => an_ac_req_spare_ctrl_a1_omm, + an_ac_req_st_gather_omm => an_ac_req_st_gather_omm, + an_ac_req_st_pop_omm => an_ac_req_st_pop_omm, + an_ac_req_st_pop_thrd_omm => an_ac_req_st_pop_thrd_omm, + an_ac_reservation_vld_omm => an_ac_reservation_vld_omm, + an_ac_sleep_en_omm => an_ac_sleep_en_omm, + an_ac_stcx_pass_omm => an_ac_stcx_pass_omm, + an_ac_sync_ack_omm => an_ac_sync_ack_omm, + an_ac_ary_nsl_thold_7_omm => an_ac_ary_nsl_thold_7_omm, + an_ac_ccenable_dc_omm => an_ac_ccenable_dc_iiu, + an_ac_coreid_omm => an_ac_coreid_omm, + an_ac_external_mchk_omm => an_ac_external_mchk_omm, + an_ac_fce_7_omm => an_ac_fce_7_omm, + an_ac_func_nsl_thold_7_omm => an_ac_func_nsl_thold_7_omm, + an_ac_func_sl_thold_7_omm => an_ac_func_sl_thold_7_omm, + an_ac_gsd_test_enable_dc_omm => an_ac_gsd_test_enable_dc_omm, + an_ac_gsd_test_acmode_dc_omm => an_ac_gsd_test_acmode_dc_omm, + an_ac_gptr_scan_in_omm => an_ac_gptr_scan_in_omm, + an_ac_hang_pulse_omm => an_ac_hang_pulse_omm, + an_ac_lbist_ac_mode_dc_omm => an_ac_lbist_ac_mode_dc_omm, + an_ac_lbist_ip_dc_omm => an_ac_lbist_ip_dc_omm, + an_ac_malf_alert_omm => an_ac_malf_alert_omm, + an_ac_perf_interrupt_omm => an_ac_perf_interrupt_omm, + an_ac_psro_enable_dc_omm => an_ac_psro_enable_dc_omm, + an_ac_repr_scan_in_omm => an_ac_repr_scan_in_omm, + an_ac_rtim_sl_thold_7_omm => an_ac_rtim_sl_thold_7_omm, + an_ac_scan_type_dc_omm => an_ac_scan_type_dc_omm, + an_ac_scom_sat_id_omm => an_ac_scom_sat_id_omm, + an_ac_sg_7_omm => an_ac_sg_7_omm, + an_ac_tb_update_enable_omm => an_ac_tb_update_enable_omm, + an_ac_tb_update_pulse_omm => an_ac_tb_update_pulse_omm, + an_ac_time_scan_in_omm => an_ac_time_scan_in_omm, + + ac_an_box_empty_imm => ac_an_box_empty_imm, + ac_an_machine_check_imm => ac_an_machine_check_imm, + ac_an_req_imm => ac_an_req_imm, + ac_an_req_endian_imm => ac_an_req_endian_imm, + ac_an_req_ld_core_tag_imm => ac_an_req_ld_core_tag_imm, + ac_an_req_ld_xfr_len_imm => ac_an_req_ld_xfr_len_imm, + ac_an_req_pwr_token_imm => ac_an_req_pwr_token_imm, + ac_an_req_ra_imm => ac_an_req_ra_imm, + ac_an_req_spare_ctrl_a0_imm => ac_an_req_spare_ctrl_a0_imm, + ac_an_req_thread_imm => ac_an_req_thread_imm, + ac_an_req_ttype_imm => ac_an_req_ttype_imm, + ac_an_req_user_defined_imm => ac_an_req_user_defined_imm, + ac_an_req_wimg_g_imm => ac_an_req_wimg_g_imm, + ac_an_req_wimg_i_imm => ac_an_req_wimg_i_imm, + ac_an_req_wimg_m_imm => ac_an_req_wimg_m_imm, + ac_an_req_wimg_w_imm => ac_an_req_wimg_w_imm, + ac_an_st_byte_enbl_imm => ac_an_st_byte_enbl_imm, + ac_an_st_data_imm => ac_an_st_data_imm, + ac_an_st_data_pwr_token_imm => ac_an_st_data_pwr_token_imm, + ac_an_abist_done_dc_imm => ac_an_abist_done_dc_oiu, + ac_an_debug_trigger_imm => ac_an_debug_trigger_imm, + ac_an_psro_ringsig_imm => ac_an_psro_ringsig_oiu, + ac_an_reset_1_request_imm => ac_an_reset_1_request_imm, + ac_an_reset_2_request_imm => ac_an_reset_2_request_imm, + ac_an_reset_3_request_imm => ac_an_reset_3_request_imm, + ac_an_reset_wd_request_imm => ac_an_reset_wd_request_imm, + + ac_an_box_empty => ac_an_box_empty, + ac_an_machine_check => ac_an_machine_check, + ac_an_req => ac_an_req, + ac_an_req_endian => ac_an_req_endian, + ac_an_req_ld_core_tag => ac_an_req_ld_core_tag, + ac_an_req_ld_xfr_len => ac_an_req_ld_xfr_len, + ac_an_req_pwr_token => ac_an_req_pwr_token, + ac_an_req_ra => ac_an_req_ra, + ac_an_req_spare_ctrl_a0 => ac_an_req_spare_ctrl_a0, + ac_an_req_thread => ac_an_req_thread, + ac_an_req_ttype => ac_an_req_ttype, + ac_an_req_user_defined => ac_an_req_user_defined, + ac_an_req_wimg_g => ac_an_req_wimg_g, + ac_an_req_wimg_i => ac_an_req_wimg_i, + ac_an_req_wimg_m => ac_an_req_wimg_m, + ac_an_req_wimg_w => ac_an_req_wimg_w, + ac_an_st_byte_enbl => ac_an_st_byte_enbl, + ac_an_st_data => ac_an_st_data, + ac_an_st_data_pwr_token => ac_an_st_data_pwr_token, + ac_an_abist_done_dc => ac_an_abist_done_dc, + ac_an_debug_trigger => ac_an_debug_trigger, + ac_an_psro_ringsig => ac_an_psro_ringsig, + ac_an_reset_1_request => ac_an_reset_1_request, + ac_an_reset_2_request => ac_an_reset_2_request, + ac_an_reset_3_request => ac_an_reset_3_request, + ac_an_reset_wd_request => ac_an_reset_wd_request, + ac_an_dcr_act => ac_an_dcr_act, + ac_an_dcr_val => ac_an_dcr_val, + ac_an_dcr_read => ac_an_dcr_read, + ac_an_dcr_user => ac_an_dcr_user, + ac_an_dcr_etid => ac_an_dcr_etid, + ac_an_dcr_addr => ac_an_dcr_addr, + ac_an_dcr_data => ac_an_dcr_data, + + debug_bus_out_int => debug_bus_out_int, + + bg_ac_an_func_scan_ns_imm => bg_ac_an_func_scan_ns_q, + bg_ac_an_abst_scan_ns_imm => bg_ac_an_abst_scan_ns_q, + bg_ac_an_func_scan_ns => bg_ac_an_func_scan_ns, + bg_ac_an_abst_scan_ns => bg_ac_an_abst_scan_ns, + bg_pc_l1p_abist_di_0_imm => bg_pc_l1p_abist_di_0_q, + bg_pc_l1p_abist_g8t1p_renb_0_imm => bg_pc_l1p_abist_g8t1p_renb_0_q, + bg_pc_l1p_abist_g8t_bw_0_imm => bg_pc_l1p_abist_g8t_bw_0_q, + bg_pc_l1p_abist_g8t_bw_1_imm => bg_pc_l1p_abist_g8t_bw_1_q, + bg_pc_l1p_abist_g8t_dcomp_imm => bg_pc_l1p_abist_g8t_dcomp_q, + bg_pc_l1p_abist_g8t_wenb_imm => bg_pc_l1p_abist_g8t_wenb_q, + bg_pc_l1p_abist_raddr_0_imm => bg_pc_l1p_abist_raddr_0_q, + bg_pc_l1p_abist_waddr_0_imm => bg_pc_l1p_abist_waddr_0_q, + bg_pc_l1p_abist_wl128_comp_ena_imm => bg_pc_l1p_abist_wl128_comp_ena_q, + bg_pc_l1p_abist_wl32_comp_ena_imm => bg_pc_l1p_abist_wl32_comp_ena_q, + bg_pc_l1p_abist_di_0 => bg_pc_l1p_abist_di_0, + bg_pc_l1p_abist_g8t1p_renb_0 => bg_pc_l1p_abist_g8t1p_renb_0, + bg_pc_l1p_abist_g8t_bw_0 => bg_pc_l1p_abist_g8t_bw_0, + bg_pc_l1p_abist_g8t_bw_1 => bg_pc_l1p_abist_g8t_bw_1, + bg_pc_l1p_abist_g8t_dcomp => bg_pc_l1p_abist_g8t_dcomp, + bg_pc_l1p_abist_g8t_wenb => bg_pc_l1p_abist_g8t_wenb, + bg_pc_l1p_abist_raddr_0 => bg_pc_l1p_abist_raddr_0, + bg_pc_l1p_abist_waddr_0 => bg_pc_l1p_abist_waddr_0, + bg_pc_l1p_abist_wl128_comp_ena => bg_pc_l1p_abist_wl128_comp_ena, + bg_pc_l1p_abist_wl32_comp_ena => bg_pc_l1p_abist_wl32_comp_ena, + bg_pc_l1p_gptr_sl_thold_2_imm => bg_pc_l1p_gptr_sl_thold_2_imm, + bg_pc_l1p_time_sl_thold_2_imm => bg_pc_l1p_time_sl_thold_2_imm, + bg_pc_l1p_repr_sl_thold_2_imm => bg_pc_l1p_repr_sl_thold_2_imm, + bg_pc_l1p_abst_sl_thold_2_imm => bg_pc_l1p_abst_sl_thold_2_imm, + bg_pc_l1p_func_sl_thold_2_imm => bg_pc_l1p_func_sl_thold_2_imm, + bg_pc_l1p_func_slp_sl_thold_2_imm => bg_pc_l1p_func_slp_sl_thold_2_imm, + bg_pc_l1p_bolt_sl_thold_2_imm => bg_pc_l1p_bolt_sl_thold_2_imm, + bg_pc_l1p_ary_nsl_thold_2_imm => bg_pc_l1p_ary_nsl_thold_2_imm, + bg_pc_l1p_sg_2_imm => bg_pc_l1p_sg_2_imm, + bg_pc_l1p_fce_2_imm => bg_pc_l1p_fce_2_imm, + bg_pc_l1p_bo_enable_2_imm => bg_pc_l1p_bo_enable_2_imm, + bg_pc_l1p_gptr_sl_thold_2 => bg_pc_l1p_gptr_sl_thold_2, + bg_pc_l1p_time_sl_thold_2 => bg_pc_l1p_time_sl_thold_2, + bg_pc_l1p_repr_sl_thold_2 => bg_pc_l1p_repr_sl_thold_2, + bg_pc_l1p_abst_sl_thold_2 => bg_pc_l1p_abst_sl_thold_2, + bg_pc_l1p_func_sl_thold_2 => bg_pc_l1p_func_sl_thold_2, + bg_pc_l1p_func_slp_sl_thold_2 => bg_pc_l1p_func_slp_sl_thold_2, + bg_pc_l1p_bolt_sl_thold_2 => bg_pc_l1p_bolt_sl_thold_2, + bg_pc_l1p_ary_nsl_thold_2 => bg_pc_l1p_ary_nsl_thold_2, + bg_pc_l1p_sg_2 => bg_pc_l1p_sg_2, + bg_pc_l1p_fce_2 => bg_pc_l1p_fce_2, + bg_pc_l1p_bo_enable_2 => bg_pc_l1p_bo_enable_2, + bg_pc_bo_unload_imm => bg_pc_bo_unload_oiu, + bg_pc_bo_load_imm => bg_pc_bo_load_oiu, + bg_pc_bo_repair_imm => bg_pc_bo_repair_oiu, + bg_pc_bo_reset_imm => bg_pc_bo_reset_oiu, + bg_pc_bo_shdata_imm => bg_pc_bo_shdata_oiu, + bg_pc_bo_select_imm => bg_pc_bo_select_oiu, + bg_pc_l1p_ccflush_dc_imm => bg_pc_l1p_ccflush_dc_oiu, + bg_pc_l1p_abist_ena_dc_imm => bg_pc_l1p_abist_ena_dc_oiu, + bg_pc_l1p_abist_raw_dc_b_imm => bg_pc_l1p_abist_raw_dc_b_oiu, + bg_pc_bo_unload => bg_pc_bo_unload, + bg_pc_bo_load => bg_pc_bo_load, + bg_pc_bo_repair => bg_pc_bo_repair, + bg_pc_bo_reset => bg_pc_bo_reset, + bg_pc_bo_shdata => bg_pc_bo_shdata, + bg_pc_bo_select => bg_pc_bo_select, + bg_pc_l1p_ccflush_dc => bg_pc_l1p_ccflush_dc, + bg_pc_l1p_abist_ena_dc => bg_pc_l1p_abist_ena_dc, + bg_pc_l1p_abist_raw_dc_b => bg_pc_l1p_abist_raw_dc_b, + bg_an_ac_func_scan_sn => bg_an_ac_func_scan_sn, + bg_an_ac_abst_scan_sn => bg_an_ac_abst_scan_sn, + bg_an_ac_func_scan_sn_omm => bg_an_ac_func_scan_sn_omm, + bg_an_ac_abst_scan_sn_omm => bg_an_ac_abst_scan_sn_omm, + bg_pc_bo_fail => bg_pc_bo_fail, + bg_pc_bo_diagout => bg_pc_bo_diagout, + bg_pc_bo_fail_omm => bg_pc_bo_fail_omm, + bg_pc_bo_diagout_omm => bg_pc_bo_diagout_omm, + xu_mm_xucr4_mmu_mchk => xu_mm_xucr4_mmu_mchk, + + gnd => gnd, + vcs => vcs, + vdd => vdd + ); -- end component a_mmq + +a_pcq: entity work.pcq + generic map(expand_type => expand_type, regmode => regmode) + port map ( + abst_scan_in => iu_pc_abst_scan_out, + bcfg_scan_in => rp_pc_bcfg_scan_out_q, + ccfg_scan_in => iu_pc_ccfg_scan_out, + dcfg_scan_in => rp_pc_dcfg_scan_out_q, + func_scan_in => rp_pc_func_scan_in_q(0 to 1), + gptr_scan_in => iu_pc_gptr_scan_out, + bx_pc_err_inbox_ue => bx_pc_err_inbox_ue_ofu, + bx_pc_err_outbox_ue => bx_pc_err_outbox_ue_ofu, + fu_pc_event_data => fu_pc_event_data, + fu_pc_ram_data => fu_pc_ram_data, + fu_pc_ram_done => fu_pc_ram_done, + iu_pc_err_icache_parity => iu_pc_err_icache_parity, + iu_pc_err_icachedir_multihit => iu_pc_err_icachedir_multihit, + iu_pc_err_icachedir_parity => iu_pc_err_icachedir_parity, + fu_pc_err_regfile_parity => fu_pc_err_regfile_parity, + fu_pc_err_regfile_ue => fu_pc_err_regfile_ue, + iu_pc_err_ucode_illegal => iu_pc_err_ucode_illegal, + iu_pc_event_data => iu_pc_event_data, + slowspr_addr_in => iu_pc_slowspr_addr, + slowspr_data_in => iu_pc_slowspr_data, + slowspr_done_in => iu_pc_slowspr_done, + slowspr_etid_in => iu_pc_slowspr_etid, + slowspr_rw_in => iu_pc_slowspr_rw, + slowspr_val_in => iu_pc_slowspr_val, + xu_pc_err_mcsr_summary => xu_pc_err_mcsr_summary_ofu, + xu_pc_err_ierat_parity => xu_pc_err_ierat_parity_ofu, + xu_pc_err_derat_parity => xu_pc_err_derat_parity_ofu, + xu_pc_err_tlb_parity => xu_pc_err_tlb_parity_ofu, + xu_pc_err_tlb_lru_parity => xu_pc_err_tlb_lru_parity_ofu, + xu_pc_err_ierat_multihit => xu_pc_err_ierat_multihit_ofu, + xu_pc_err_derat_multihit => xu_pc_err_derat_multihit_ofu, + xu_pc_err_tlb_multihit => xu_pc_err_tlb_multihit_ofu, + xu_pc_err_ext_mchk => xu_pc_err_ext_mchk_ofu, + xu_pc_err_ditc_overrun => xu_pc_err_ditc_overrun_ofu, + xu_pc_err_local_snoop_reject => xu_pc_err_local_snoop_reject_ofu, + mm_pc_event_data => mm_pc_event_data_oiu, + nclk => a2_nclk, + an_ac_rtim_sl_thold_6 => rp_pc_rtim_sl_thold_6, + an_ac_func_sl_thold_6 => rp_pc_func_sl_thold_6, + an_ac_func_nsl_thold_6 => rp_pc_func_nsl_thold_6, + an_ac_ary_nsl_thold_6 => rp_pc_ary_nsl_thold_6, + an_ac_sg_6 => rp_pc_sg_6, + an_ac_fce_6 => rp_pc_fce_6, + an_ac_abist_start_test => rp_pc_abist_start_test_q, + an_ac_ccenable_dc => an_ac_ccenable_dc_oiu, + an_ac_ccflush_dc => an_ac_ccflush_dc_oiu, + an_ac_debug_stop => rp_pc_debug_stop_q, + an_ac_gsd_test_enable_dc => an_ac_gsd_test_enable_dc_oiu, + an_ac_gsd_test_acmode_dc => an_ac_gsd_test_acmode_dc_oiu, + an_ac_lbist_en_dc => an_ac_lbist_en_dc_oiu, + an_ac_lbist_ip_dc => an_ac_lbist_ip_dc_oiu, + an_ac_lbist_ac_mode_dc => an_ac_lbist_ac_mode_dc_oiu, + an_ac_abist_mode_dc => an_ac_abist_mode_dc_oiu, + an_ac_malf_alert => an_ac_malf_alert_oiu, + an_ac_pm_thread_stop => rp_pc_pm_thread_stop_q, + an_ac_psro_enable_dc => an_ac_psro_enable_dc_oiu, + an_ac_reset_1_complete => rp_pc_reset_1_complete_q, + an_ac_reset_2_complete => rp_pc_reset_2_complete_q, + an_ac_reset_3_complete => rp_pc_reset_3_complete_q, + an_ac_reset_wd_complete => rp_pc_reset_wd_complete_q, + an_ac_scan_diag_dc => an_ac_scan_diag_dc_oiu, + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b_oiu, + an_ac_scan_type_dc => an_ac_scan_type_dc_oiu, + an_ac_scom_cch => rp_pc_scom_cch_q, + an_ac_scom_dch => rp_pc_scom_dch_q, + an_ac_scom_sat_id => an_ac_scom_sat_id_oiu, + an_ac_checkstop => rp_pc_checkstop_q, + debug_bus_in => fu_pc_debug_data, + trace_triggers_in => fu_pc_trigger_data, + xu_pc_err_attention_instr => xu_pc_err_attention_instr_ofu, + xu_pc_err_dcache_parity => xu_pc_err_dcache_parity_ofu, + xu_pc_err_dcachedir_parity => xu_pc_err_dcachedir_parity_ofu, + xu_pc_err_dcachedir_multihit => xu_pc_err_dcachedir_multihit_ofu, + xu_pc_err_debug_event => xu_pc_err_debug_event_ofu, + bx_pc_err_inbox_ecc => bx_pc_err_inbox_ecc_ofu, + xu_pc_err_invld_reld => xu_pc_err_invld_reld_ofu, + xu_pc_err_l2intrf_ecc => xu_pc_err_l2intrf_ecc_ofu, + xu_pc_err_l2intrf_ue => xu_pc_err_l2intrf_ue_ofu, + xu_pc_err_l2credit_overrun => xu_pc_err_l2credit_overrun_ofu, + xu_pc_err_llbust_attempt => xu_pc_err_llbust_attempt_ofu, + xu_pc_err_llbust_failed => xu_pc_err_llbust_failed_ofu, + xu_pc_err_nia_miscmpr => xu_pc_err_nia_miscmpr_ofu, + bx_pc_err_outbox_ecc => bx_pc_err_outbox_ecc_ofu, + xu_pc_err_regfile_parity => xu_pc_err_regfile_parity_ofu, + xu_pc_err_regfile_ue => xu_pc_err_regfile_ue_ofu, + xu_pc_err_sprg_ecc => xu_pc_err_sprg_ecc_ofu, + xu_pc_err_sprg_ue => xu_pc_err_sprg_ue_ofu, + xu_pc_err_wdt_reset => xu_pc_err_wdt_reset_ofu, + xu_pc_event_data => xu_pc_event_data_ofu, + lsu_pc_event_data => xu_pc_lsu_event_data_ofu, + ac_pc_trace_to_perfcntr => rp_pc_trace_to_perfcntr_q, + xu_pc_ram_data => xu_pc_ram_data_ofu, + xu_pc_ram_done => xu_pc_ram_done_ofu, + xu_pc_ram_interrupt => xu_pc_ram_interrupt_ofu, + xu_pc_running => xu_pc_running_ofu, + xu_pc_spr_ccr0_pme => xu_pc_spr_ccr0_pme_ofu, + xu_pc_spr_ccr0_we => xu_pc_spr_ccr0_we_ofu, + xu_pc_step_done => xu_pc_step_done_ofu, + xu_pc_stop_dbg_event => xu_pc_stop_dbg_event_ofu, +-- Start Bolt-On ABIST Interface + an_ac_bo_enable => an_ac_bo_enable, + an_ac_bo_go => an_ac_bo_go, + an_ac_bo_cntlclk => an_ac_bo_cntlclk, + an_ac_bo_ccflush => an_ac_bo_ccflush, + an_ac_bo_reset => an_ac_bo_reset, + an_ac_bo_data => an_ac_bo_data, + an_ac_bo_shcntl => an_ac_bo_shcntl, + an_ac_bo_shdata => an_ac_bo_shdata, + an_ac_bo_exe => an_ac_bo_exe, + an_ac_bo_sysrepair => an_ac_bo_sysrepair, + an_ac_bo_donein => an_ac_bo_donein, + an_ac_bo_sdin => an_ac_bo_sdin, + an_ac_bo_waitin => an_ac_bo_waitin, + an_ac_bo_failin => an_ac_bo_failin, + an_ac_bo_fcshdata => an_ac_bo_fcshdata, + an_ac_bo_fcreset => an_ac_bo_fcreset, + ac_an_bo_doneout => ac_an_bo_doneout, + ac_an_bo_sdout => ac_an_bo_sdout, + ac_an_bo_diagloopout => ac_an_bo_diagloopout, + ac_an_bo_waitout => ac_an_bo_waitout, + ac_an_bo_failout => ac_an_bo_failout, + pc_bx_bolt_sl_thold_3 => pc_bx_bolt_sl_thold_3, + pc_fu_bolt_sl_thold_3 => pc_fu_bolt_sl_thold_3, + pc_xu_bolt_sl_thold_3 => pc_xu_bolt_sl_thold_3, + pc_bx_bo_enable_3 => pc_bx_bo_enable_3, + pc_bx_bo_unload => pc_bx_bo_unload, + pc_bx_bo_repair => pc_bx_bo_repair, + pc_bx_bo_reset => pc_bx_bo_reset, + pc_bx_bo_shdata => pc_bx_bo_shdata, + pc_bx_bo_select => pc_bx_bo_select, + bx_pc_bo_fail => bx_pc_bo_fail_ofu, + bx_pc_bo_diagout => bx_pc_bo_diagout_ofu, + pc_fu_bo_enable_3 => pc_fu_bo_enable_3, + pc_fu_bo_unload => pc_fu_bo_unload, + pc_fu_bo_load => pc_fu_bo_load, + pc_fu_bo_reset => pc_fu_bo_reset, + pc_fu_bo_shdata => pc_fu_bo_shdata, + pc_fu_bo_select => pc_fu_bo_select, + fu_pc_bo_fail => fu_pc_bo_fail, + fu_pc_bo_diagout => fu_pc_bo_diagout, + pc_iu_bo_enable_4 => pc_iu_bo_enable_4, + pc_iu_bo_unload => pc_iu_bo_unload, + pc_iu_bo_repair => pc_iu_bo_repair, + pc_iu_bo_reset => pc_iu_bo_reset, + pc_iu_bo_shdata => pc_iu_bo_shdata, + pc_iu_bo_select => pc_iu_bo_select, + iu_pc_bo_fail => iu_pc_bo_fail, + iu_pc_bo_diagout => iu_pc_bo_diagout, + pc_mm_bo_enable_4 => pc_mm_bo_enable_4_iiu, + pc_mm_bo_unload => pc_mm_bo_unload_iiu, + pc_mm_bo_repair => pc_mm_bo_repair_iiu, + pc_mm_bo_reset => pc_mm_bo_reset_iiu, + pc_mm_bo_shdata => pc_mm_bo_shdata_iiu, + pc_mm_bo_select => pc_mm_bo_select_iiu, + mm_pc_bo_fail => mm_pc_bo_fail_oiu, + mm_pc_bo_diagout => mm_pc_bo_diagout_oiu, + pc_xu_bo_enable_3 => pc_xu_bo_enable_3, + pc_xu_bo_unload => pc_xu_bo_unload, + pc_xu_bo_load => pc_xu_bo_load, + pc_xu_bo_repair => pc_xu_bo_repair, + pc_xu_bo_reset => pc_xu_bo_reset, + pc_xu_bo_shdata => pc_xu_bo_shdata, + pc_xu_bo_select => pc_xu_bo_select, + xu_pc_bo_fail => xu_pc_bo_fail_ofu, + xu_pc_bo_diagout => xu_pc_bo_diagout_ofu, +-- End Bolt-On ABIST Interface PCQ + ac_an_power_managed => pc_rp_power_managed, + ac_an_rvwinkle_mode => pc_rp_rvwinkle_mode, + ac_an_fu_bypass_events => pc_rp_fu_bypass_events, + ac_an_iu_bypass_events => pc_rp_iu_bypass_events, + ac_an_mm_bypass_events => pc_rp_mm_bypass_events, + ac_an_lsu_bypass_events => pc_rp_lsu_bypass_events, + ac_an_event_bus => pc_rp_event_bus, + ac_an_abist_done_dc => ac_an_abist_done_dc_iiu, + ac_an_local_checkstop => pc_rp_local_checkstop, + ac_an_pm_thread_running => pc_rp_pm_thread_running, + ac_an_psro_ringsig => ac_an_psro_ringsig_iiu, + ac_an_recov_err => pc_rp_recov_err, + ac_an_scom_cch => pc_rp_scom_cch, + ac_an_scom_dch => pc_rp_scom_dch, + ac_an_special_attn => pc_rp_special_attn, + ac_an_checkstop => pc_rp_checkstop, + ac_an_trace_error => pc_rp_trace_error, + debug_bus_out => pc_iu_debug_data, + trace_triggers_out => pc_iu_trigger_data, + abst_scan_out => pc_rp_abst_scan_out, + bcfg_scan_out => pc_rp_bcfg_scan_out, + ccfg_scan_out => pc_rp_ccfg_scan_out, + dcfg_scan_out => pc_rp_dcfg_scan_out, + func_scan_out => pc_rp_func_scan_out(0 to 1), + gptr_scan_out => pc_fu_gptr_scan_out, + pc_bx_abist_di_0 => pc_bx_abist_di_0(0 to 3), + pc_bx_abist_ena_dc => pc_bx_abist_ena_dc, + pc_bx_abist_g8t1p_renb_0 => pc_bx_abist_g8t1p_renb_0, + pc_bx_abist_g8t_bw_0 => pc_bx_abist_g8t_bw_0, + pc_bx_abist_g8t_bw_1 => pc_bx_abist_g8t_bw_1, + pc_bx_abist_g8t_dcomp => pc_bx_abist_g8t_dcomp(0 to 3), + pc_bx_abist_g8t_wenb => pc_bx_abist_g8t_wenb, + pc_bx_abist_raddr_0 => pc_bx_abist_raddr_0(0 to 9), + pc_bx_abist_raw_dc_b => pc_bx_abist_raw_dc_b, + pc_bx_abist_waddr_0 => pc_bx_abist_waddr_0(0 to 9), + pc_bx_abist_wl64_g8t_comp_ena => pc_bx_abist_wl64_comp_ena, + pc_fu_abist_di_0 => pc_fu_abist_di_0(0 to 3), + pc_fu_abist_di_1 => pc_fu_abist_di_1(0 to 3), + pc_fu_abist_ena_dc => pc_fu_abist_ena_dc, + pc_fu_abist_grf_renb_0 => pc_fu_abist_grf_renb_0, + pc_fu_abist_grf_renb_1 => pc_fu_abist_grf_renb_1, + pc_fu_abist_grf_wenb_0 => pc_fu_abist_grf_wenb_0, + pc_fu_abist_grf_wenb_1 => pc_fu_abist_grf_wenb_1, + pc_fu_abist_raddr_0 => pc_fu_abist_raddr_0(0 to 9), + pc_fu_abist_raddr_1 => pc_fu_abist_raddr_1(0 to 9), + pc_fu_abist_raw_dc_b => pc_fu_abist_raw_dc_b, + pc_fu_abist_waddr_0 => pc_fu_abist_waddr_0(0 to 9), + pc_fu_abist_waddr_1 => pc_fu_abist_waddr_1(0 to 9), + pc_fu_abist_wl144_comp_ena => pc_fu_abist_wl144_comp_ena, + pc_iu_abist_dcomp_g6t_2r => pc_iu_abist_dcomp_g6t_2r(0 to 3), + pc_iu_abist_di_0 => pc_iu_abist_di_0(0 to 3), + pc_iu_abist_di_g6t_2r => pc_iu_abist_di_g6t_2r(0 to 3), + pc_iu_abist_ena_dc => pc_iu_abist_ena_dc, + pc_iu_abist_g6t_bw => pc_iu_abist_g6t_bw(0 to 1), + pc_iu_abist_g6t_r_wb => pc_iu_abist_g6t_r_wb, + pc_iu_abist_g8t1p_renb_0 => pc_iu_abist_g8t1p_renb_0, + pc_iu_abist_g8t_bw_0 => pc_iu_abist_g8t_bw_0, + pc_iu_abist_g8t_bw_1 => pc_iu_abist_g8t_bw_1, + pc_iu_abist_g8t_dcomp => pc_iu_abist_g8t_dcomp(0 to 3), + pc_iu_abist_g8t_wenb => pc_iu_abist_g8t_wenb, + pc_iu_abist_raddr_0 => pc_iu_abist_raddr_0(0 to 9), + pc_iu_abist_raw_dc_b => pc_iu_abist_raw_dc_b, + pc_iu_abist_waddr_0 => pc_iu_abist_waddr_0(0 to 9), + pc_iu_abist_wl128_g8t_comp_ena => pc_iu_abist_wl128_comp_ena, + pc_iu_abist_wl256_comp_ena => pc_iu_abist_wl256_comp_ena, + pc_iu_abist_wl64_g8t_comp_ena => pc_iu_abist_wl64_comp_ena, + pc_mm_abist_dcomp_g6t_2r => pc_mm_abist_dcomp_g6t_2r_iiu(0 to 3), + pc_mm_abist_di_0 => pc_mm_abist_di_0_iiu(0 to 3), + pc_mm_abist_di_g6t_2r => pc_mm_abist_di_g6t_2r_iiu(0 to 3), + pc_mm_abist_ena_dc => pc_mm_abist_ena_dc_iiu, + pc_mm_abist_g6t_r_wb => pc_mm_abist_g6t_r_wb_iiu, + pc_mm_abist_g8t1p_renb_0 => pc_mm_abist_g8t1p_renb_0_iiu, + pc_mm_abist_g8t_bw_0 => pc_mm_abist_g8t_bw_0_iiu, + pc_mm_abist_g8t_bw_1 => pc_mm_abist_g8t_bw_1_iiu, + pc_mm_abist_g8t_dcomp => pc_mm_abist_g8t_dcomp_iiu(0 to 3), + pc_mm_abist_g8t_wenb => pc_mm_abist_g8t_wenb_iiu, + pc_mm_abist_raddr_0 => pc_mm_abist_raddr_0_iiu(0 to 9), + pc_mm_abist_raw_dc_b => pc_mm_abist_raw_dc_b_iiu, + pc_mm_abist_waddr_0 => pc_mm_abist_waddr_0_iiu(0 to 9), + pc_mm_abist_wl128_g8t_comp_ena => pc_mm_abist_wl128_comp_ena_iiu, + pc_xu_abist_dcomp_g6t_2r => pc_xu_abist_dcomp_g6t_2r(0 to 3), + pc_xu_abist_di_0 => pc_xu_abist_di_0(0 to 3), + pc_xu_abist_di_1 => pc_xu_abist_di_1(0 to 3), + pc_xu_abist_di_g6t_2r => pc_xu_abist_di_g6t_2r(0 to 3), + pc_xu_abist_ena_dc => pc_xu_abist_ena_dc, + pc_xu_abist_g6t_bw => pc_xu_abist_g6t_bw(0 to 1), + pc_xu_abist_g6t_r_wb => pc_xu_abist_g6t_r_wb, + pc_xu_abist_g8t1p_renb_0 => pc_xu_abist_g8t1p_renb_0, + pc_xu_abist_g8t_bw_0 => pc_xu_abist_g8t_bw_0, + pc_xu_abist_g8t_bw_1 => pc_xu_abist_g8t_bw_1, + pc_xu_abist_g8t_dcomp => pc_xu_abist_g8t_dcomp(0 to 3), + pc_xu_abist_g8t_wenb => pc_xu_abist_g8t_wenb, + pc_xu_abist_grf_renb_0 => pc_xu_abist_grf_renb_0, + pc_xu_abist_grf_renb_1 => pc_xu_abist_grf_renb_1, + pc_xu_abist_grf_wenb_0 => pc_xu_abist_grf_wenb_0, + pc_xu_abist_grf_wenb_1 => pc_xu_abist_grf_wenb_1, + pc_xu_abist_raddr_0 => pc_xu_abist_raddr_0(0 to 9), + pc_xu_abist_raddr_1 => pc_xu_abist_raddr_1(0 to 9), + pc_xu_abist_raw_dc_b => pc_xu_abist_raw_dc_b, + pc_xu_abist_waddr_0 => pc_xu_abist_waddr_0(0 to 9), + pc_xu_abist_waddr_1 => pc_xu_abist_waddr_1(0 to 9), + pc_xu_abist_wl144_comp_ena => pc_xu_abist_wl144_comp_ena, + pc_xu_abist_wl32_g8t_comp_ena => pc_xu_abist_wl32_comp_ena, + pc_xu_abist_wl512_comp_ena => pc_xu_abist_wl512_comp_ena, + pc_bx_trace_bus_enable => pc_bx_trace_bus_enable, + pc_bx_debug_mux1_ctrls => pc_bx_debug_mux1_ctrls, + pc_bx_inj_inbox_ecc => pc_bx_inj_inbox_ecc, + pc_bx_inj_outbox_ecc => pc_bx_inj_outbox_ecc, + pc_fu_abst_sl_thold_3 => pc_fu_abst_sl_thold_3, + pc_fu_abst_slp_sl_thold_3 => pc_fu_abst_slp_sl_thold_3, + pc_fu_ary_nsl_thold_3 => pc_fu_ary_nsl_thold_3, + pc_fu_ary_slp_nsl_thold_3 => pc_fu_ary_slp_nsl_thold_3, + pc_fu_ccflush_dc => pc_fu_ccflush_dc, + pc_fu_cfg_sl_thold_3 => pc_fu_cfg_sl_thold_3, + pc_fu_cfg_slp_sl_thold_3 => pc_fu_cfg_slp_sl_thold_3, + pc_fu_debug_mux1_ctrls => pc_fu_debug_mux1_ctrls, + pc_fu_event_count_mode => pc_fu_event_count_mode, + pc_fu_event_mux_ctrls => pc_fu_event_mux_ctrls, + pc_iu_event_mux_ctrls => pc_iu_event_mux_ctrls, + pc_mm_event_mux_ctrls => pc_mm_event_mux_ctrls_iiu, + pc_xu_event_mux_ctrls => pc_xu_event_mux_ctrls, + pc_xu_lsu_event_mux_ctrls => pc_xu_lsu_event_mux_ctrls, + pc_fu_event_bus_enable => pc_fu_event_bus_enable, + pc_iu_event_bus_enable => pc_iu_event_bus_enable, + pc_rp_event_bus_enable => pc_rp_event_bus_enable, + pc_xu_event_bus_enable => pc_xu_event_bus_enable, + pc_fu_fce_3 => pc_fu_fce_3, + pc_fu_func_nsl_thold_3 => pc_fu_func_nsl_thold_3, + pc_fu_func_sl_thold_3 => pc_fu_func_sl_thold_3, + pc_fu_func_slp_nsl_thold_3 => pc_fu_func_slp_nsl_thold_3, + pc_fu_func_slp_sl_thold_3 => pc_fu_func_slp_sl_thold_3, + pc_fu_gptr_sl_thold_3 => pc_fu_gptr_sl_thold_3, + pc_fu_inj_regfile_parity => pc_fu_inj_regfile_parity, + pc_fu_instr_trace_mode => pc_fu_instr_trace_mode, + pc_fu_instr_trace_tid => pc_fu_instr_trace_tid, + pc_fu_ram_mode => pc_fu_ram_mode, + pc_fu_ram_thread => pc_fu_ram_thread, + pc_fu_repr_sl_thold_3 => pc_fu_repr_sl_thold_3, + pc_fu_sg_3 => pc_fu_sg_3, + slowspr_addr_out => pc_fu_slowspr_addr, + slowspr_data_out => pc_fu_slowspr_data, + slowspr_done_out => pc_fu_slowspr_done, + slowspr_etid_out => pc_fu_slowspr_etid, + slowspr_rw_out => pc_fu_slowspr_rw, + slowspr_val_out => pc_fu_slowspr_val, + pc_fu_time_sl_thold_3 => pc_fu_time_sl_thold_3, + pc_fu_trace_bus_enable => pc_fu_trace_bus_enable, + pc_iu_ccflush_dc => pc_iu_ccflush_dc, + pc_iu_gptr_sl_thold_4 => pc_iu_gptr_sl_thold_4, + pc_iu_time_sl_thold_4 => pc_iu_time_sl_thold_4, + pc_iu_repr_sl_thold_4 => pc_iu_repr_sl_thold_4, + pc_iu_abst_sl_thold_4 => pc_iu_abst_sl_thold_4, + pc_iu_abst_slp_sl_thold_4 => pc_iu_abst_slp_sl_thold_4, + pc_iu_bolt_sl_thold_4 => pc_iu_bolt_sl_thold_4, + pc_iu_regf_slp_sl_thold_4 => pc_iu_regf_slp_sl_thold_4, + pc_iu_func_sl_thold_4 => pc_iu_func_sl_thold_4, + pc_iu_func_slp_sl_thold_4 => pc_iu_func_slp_sl_thold_4, + pc_iu_cfg_sl_thold_4 => pc_iu_cfg_sl_thold_4, + pc_iu_cfg_slp_sl_thold_4 => pc_iu_cfg_slp_sl_thold_4, + pc_iu_func_nsl_thold_4 => pc_iu_func_nsl_thold_4, + pc_iu_func_slp_nsl_thold_4 => pc_iu_func_slp_nsl_thold_4, + pc_iu_ary_nsl_thold_4 => pc_iu_ary_nsl_thold_4, + pc_iu_ary_slp_nsl_thold_4 => pc_iu_ary_slp_nsl_thold_4, + pc_iu_sg_4 => pc_iu_sg_4, + pc_iu_fce_4 => pc_iu_fce_4, + pc_iu_debug_mux1_ctrls => pc_iu_debug_mux1_ctrls, + pc_iu_debug_mux2_ctrls => pc_iu_debug_mux2_ctrls, + pc_iu_event_count_mode => pc_iu_event_count_mode, + pc_iu_init_reset => pc_iu_init_reset, + pc_iu_inj_icache_parity => pc_iu_inj_icache_parity, + pc_iu_inj_icachedir_parity => pc_iu_inj_icachedir_parity, + pc_iu_inj_icachedir_multihit => pc_iu_inj_icachedir_multihit, + pc_iu_ram_force_cmplt => pc_iu_ram_force_cmplt, + pc_iu_ram_instr => pc_iu_ram_instr, + pc_iu_ram_instr_ext => pc_iu_ram_instr_ext, + pc_iu_ram_mode => pc_iu_ram_mode, + pc_iu_ram_thread => pc_iu_ram_thread, + pc_iu_trace_bus_enable => pc_iu_trace_bus_enable, + pc_mm_ccflush_dc => pc_mm_ccflush_dc_iiu, + pc_mm_debug_mux1_ctrls => pc_mm_debug_mux1_ctrls_iiu, + pc_mm_event_count_mode => pc_mm_event_count_mode_iiu, + pc_mm_trace_bus_enable => pc_mm_trace_bus_enable_iiu, + pc_xu_abst_sl_thold_3 => pc_xu_abst_sl_thold_3, + pc_xu_abst_slp_sl_thold_3 => pc_xu_abst_slp_sl_thold_3, + pc_xu_regf_sl_thold_3 => pc_xu_regf_sl_thold_3, + pc_xu_regf_slp_sl_thold_3 => pc_xu_regf_slp_sl_thold_3, + pc_xu_ary_nsl_thold_3 => pc_xu_ary_nsl_thold_3, + pc_xu_ary_slp_nsl_thold_3 => pc_xu_ary_slp_nsl_thold_3, + pc_xu_cache_par_err_event => pc_xu_cache_par_err_event, + pc_xu_ccflush_dc => pc_xu_ccflush_dc, + pc_xu_cfg_sl_thold_3 => pc_xu_cfg_sl_thold_3, + pc_xu_cfg_slp_sl_thold_3 => pc_xu_cfg_slp_sl_thold_3, + pc_xu_dbg_action => pc_xu_dbg_action, + pc_xu_debug_mux1_ctrls => pc_xu_debug_mux1_ctrls, + pc_xu_debug_mux2_ctrls => pc_xu_debug_mux2_ctrls, + pc_xu_debug_mux3_ctrls => pc_xu_debug_mux3_ctrls, + pc_xu_debug_mux4_ctrls => pc_xu_debug_mux4_ctrls, + pc_xu_decrem_dis_on_stop => pc_xu_decrem_dis_on_stop, + pc_xu_event_count_mode => pc_xu_event_count_mode, + pc_xu_extirpts_dis_on_stop => pc_xu_extirpts_dis_on_stop, + pc_xu_fce_3 => pc_xu_fce_3, + pc_xu_force_ude => pc_xu_force_ude, + pc_xu_func_nsl_thold_3 => pc_xu_func_nsl_thold_3, + pc_xu_func_sl_thold_3 => pc_xu_func_sl_thold_3, + pc_xu_func_slp_nsl_thold_3 => pc_xu_func_slp_nsl_thold_3, + pc_xu_func_slp_sl_thold_3 => pc_xu_func_slp_sl_thold_3, + pc_xu_gptr_sl_thold_3 => pc_xu_gptr_sl_thold_3, + pc_xu_init_reset => pc_xu_init_reset, + pc_xu_inj_dcache_parity => pc_xu_inj_dcache_parity, + pc_xu_inj_dcachedir_parity => pc_xu_inj_dcachedir_parity, + pc_xu_inj_llbust_attempt => pc_xu_inj_llbust_attempt, + pc_xu_inj_llbust_failed => pc_xu_inj_llbust_failed, + pc_xu_inj_sprg_ecc => pc_xu_inj_sprg_ecc, + pc_xu_inj_regfile_parity => pc_xu_inj_regfile_parity, + pc_xu_inj_wdt_reset => pc_xu_inj_wdt_reset, + pc_xu_inj_dcachedir_multihit => pc_xu_inj_dcachedir_multihit, + pc_xu_instr_trace_mode => pc_xu_instr_trace_mode, + pc_xu_instr_trace_tid => pc_xu_instr_trace_tid, + pc_xu_msrovride_de => pc_xu_msrovride_de, + pc_xu_msrovride_enab => pc_xu_msrovride_enab, + pc_xu_msrovride_gs => pc_xu_msrovride_gs, + pc_xu_msrovride_pr => pc_xu_msrovride_pr, + pc_xu_ram_execute => pc_xu_ram_execute, + pc_xu_ram_flush_thread => pc_xu_ram_flush_thread, + pc_xu_ram_mode => pc_xu_ram_mode, + pc_xu_ram_thread => pc_xu_ram_thread, + pc_xu_repr_sl_thold_3 => pc_xu_repr_sl_thold_3, + pc_xu_reset_1_cmplt => pc_xu_reset_1_complete, + pc_xu_reset_2_cmplt => pc_xu_reset_2_complete, + pc_xu_reset_3_cmplt => pc_xu_reset_3_complete, + pc_xu_reset_wd_cmplt => pc_xu_reset_wd_complete, + pc_xu_sg_3 => pc_xu_sg_3, + pc_xu_step => pc_xu_step, + pc_xu_stop => pc_xu_stop, + pc_xu_time_sl_thold_3 => pc_xu_time_sl_thold_3, + pc_xu_timebase_dis_on_stop => pc_xu_timebase_dis_on_stop, + pc_xu_trace_bus_enable => pc_xu_trace_bus_enable, + pc_bx_ccflush_dc => pc_bx_ccflush_dc, + pc_bx_sg_3 => pc_bx_sg_3, + pc_bx_func_sl_thold_3 => pc_bx_func_sl_thold_3, + pc_bx_func_slp_sl_thold_3 => pc_bx_func_slp_sl_thold_3, + pc_bx_gptr_sl_thold_3 => pc_bx_gptr_sl_thold_3, + pc_bx_time_sl_thold_3 => pc_bx_time_sl_thold_3, + pc_bx_repr_sl_thold_3 => pc_bx_repr_sl_thold_3, + pc_bx_abst_sl_thold_3 => pc_bx_abst_sl_thold_3, + pc_bx_ary_nsl_thold_3 => pc_bx_ary_nsl_thold_3, + pc_bx_ary_slp_nsl_thold_3 => pc_bx_ary_slp_nsl_thold_3, + + an_ac_scan_diag_dc_opc => an_ac_scan_diag_dc_opc, + an_ac_scan_dis_dc_b_opc => an_ac_scan_dis_dc_b_opc, + + xu_pc_err_mchk_disabled => xu_pc_err_mchk_disabled_ofu, + + gnd => gnd, + vdd => vdd + ); -- end component a_pcq + + +bx: if include_boxes=1 generate begin + a_bxq: entity work.bxq + generic map(expand_type => expand_type, + real_data_add => xu_real_data_add, + regmode => regmode) + PORT map( + -- input command and data from mtdp instruction + xu_bx_ccr2_en_ditc => xu_bx_ccr2_en_ditc, + xu_ex2_flush => xu_ex2_flush_ofu, + xu_ex3_flush => xu_ex3_flush_ofu, + xu_ex4_flush => xu_ex4_flush_ofu, + xu_ex5_flush => xu_ex5_flush_ofu, + xu_bx_ex1_mtdp_val => xu_bx_ex1_mtdp_val, + xu_bx_ex1_mfdp_val => xu_bx_ex1_mfdp_val, + xu_bx_ex1_ipc_thrd => xu_bx_ex1_ipc_thrd, + xu_bx_ex2_ipc_ba => xu_bx_ex2_ipc_ba, + xu_bx_ex2_ipc_sz => xu_bx_ex2_ipc_sz, + xu_bx_ex4_256st_data => xu_bx_ex4_256st_data(128 to 255) , + + bx_xu_ex4_mtdp_cr_status => bx_xu_ex4_mtdp_cr_status , + bx_xu_ex4_mfdp_cr_status => bx_xu_ex4_mfdp_cr_status , + bx_xu_ex5_dp_data => bx_xu_ex5_dp_data , + + -- outputs to network or l2 from outbox + bx_lsu_ob_pwr_tok => bx_lsu_ob_pwr_tok, + bx_lsu_ob_req_val => bx_lsu_ob_req_val, + bx_lsu_ob_ditc_val => bx_lsu_ob_ditc_val, + bx_lsu_ob_thrd => bx_lsu_ob_thrd, + bx_lsu_ob_qw => bx_lsu_ob_qw, + bx_lsu_ob_dest => bx_lsu_ob_dest, + bx_lsu_ob_data => bx_lsu_ob_data, + bx_lsu_ob_addr => bx_lsu_ob_addr, + + ac_an_reld_ditc_pop => ac_an_reld_ditc_pop_int, + + bx_ib_empty => bx_ib_empty_int, + bx_xu_quiesce => bx_xu_quiesce, + + -- inputs from lsu + lsu_bx_cmd_avail => lsu_bx_cmd_avail, + lsu_bx_cmd_sent => lsu_bx_cmd_sent, + lsu_bx_cmd_stall => lsu_bx_cmd_stall, + + -- inputs from network or l2 going to inbox + lsu_reld_data_vld => lsu_reld_data_vld, + lsu_reld_core_tag => lsu_reld_core_tag(3 to 4), + lsu_reld_qw => lsu_reld_qw, + lsu_reld_ditc => lsu_reld_ditc, + lsu_reld_ecc_err => lsu_reld_ecc_err, + lsu_reld_data => lsu_reld_data, + + an_ac_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc_ofu, + + lsu_req_st_pop => lsu_req_st_pop , + lsu_req_st_pop_thrd => lsu_req_st_pop_thrd , + + slowspr_addr_in => fu_bx_slowspr_addr, + slowspr_data_in => fu_bx_slowspr_data, + slowspr_done_in => fu_bx_slowspr_done, + slowspr_etid_in => fu_bx_slowspr_etid, + slowspr_rw_in => fu_bx_slowspr_rw, + slowspr_val_in => fu_bx_slowspr_val, + slowspr_addr_out => bx_xu_slowspr_addr, + slowspr_data_out => bx_xu_slowspr_data, + slowspr_done_out => bx_xu_slowspr_done, + slowspr_etid_out => bx_xu_slowspr_etid, + slowspr_rw_out => bx_xu_slowspr_rw, + slowspr_val_out => bx_xu_slowspr_val, + + bx_pc_bo_fail => bx_pc_bo_fail, + bx_pc_bo_diagout => bx_pc_bo_diagout, + bx_pc_err_inbox_ecc => bx_pc_err_inbox_ecc, + bx_pc_err_outbox_ecc => bx_pc_err_outbox_ecc, + bx_pc_err_inbox_ue => bx_pc_err_inbox_ue, + bx_pc_err_outbox_ue => bx_pc_err_outbox_ue, + pc_bx_inj_inbox_ecc => pc_bx_inj_inbox_ecc_ofu, + pc_bx_inj_outbox_ecc => pc_bx_inj_outbox_ecc_ofu, + + -- debug connections + pc_bx_trace_bus_enable => pc_bx_trace_bus_enable_ofu, + pc_bx_debug_mux1_ctrls => pc_bx_debug_mux1_ctrls_ofu, + trigger_data_in => trigger_start_tiedowns, + debug_data_in => debug_start_tiedowns, + debug_data_out => bx_fu_debug_data, + trigger_data_out => bx_fu_trigger_data, + + vdd => vdd, + gnd => gnd, + vcs => vcs, + nclk => a2_nclk, + + pc_bx_abist_di_0 => pc_bx_abist_di_0_ofu, + pc_bx_abist_ena_dc => pc_bx_abist_ena_dc_ofu, + pc_bx_abist_g8t1p_renb_0 => pc_bx_abist_g8t1p_renb_0_ofu, + pc_bx_abist_g8t_bw_0 => pc_bx_abist_g8t_bw_0_ofu, + pc_bx_abist_g8t_bw_1 => pc_bx_abist_g8t_bw_1_ofu, + pc_bx_abist_g8t_dcomp => pc_bx_abist_g8t_dcomp_ofu, + pc_bx_abist_g8t_wenb => pc_bx_abist_g8t_wenb_ofu, + pc_bx_abist_raddr_0 => pc_bx_abist_raddr_0_ofu(4 to 9), + pc_bx_abist_raw_dc_b => pc_bx_abist_raw_dc_b_ofu, + pc_bx_abist_waddr_0 => pc_bx_abist_waddr_0_ofu(4 to 9), + pc_bx_abist_wl64_comp_ena => pc_bx_abist_wl64_comp_ena_ofu, + pc_bx_bolt_sl_thold_3 => pc_bx_bolt_sl_thold_3_ofu, + pc_bx_bo_enable_3 => pc_bx_bo_enable_3_ofu, + pc_bx_bo_unload => pc_bx_bo_unload_ofu, + pc_bx_bo_repair => pc_bx_bo_repair_ofu, + pc_bx_bo_reset => pc_bx_bo_reset_ofu, + pc_bx_bo_shdata => pc_bx_bo_shdata_ofu, + pc_bx_bo_select => pc_bx_bo_select_ofu, + pc_bx_ccflush_dc => pc_bx_ccflush_dc_ofu, + pc_bx_sg_3 => pc_bx_sg_3_ofu, + pc_bx_func_sl_thold_3 => pc_bx_func_sl_thold_3_ofu, + pc_bx_func_slp_sl_thold_3 => pc_bx_func_slp_sl_thold_3_ofu, + pc_bx_gptr_sl_thold_3 => pc_bx_gptr_sl_thold_3_ofu, + pc_bx_abst_sl_thold_3 => pc_bx_abst_sl_thold_3_ofu, + pc_bx_time_sl_thold_3 => pc_bx_time_sl_thold_3_ofu, + pc_bx_ary_nsl_thold_3 => pc_bx_ary_nsl_thold_3_ofu, + pc_bx_ary_slp_nsl_thold_3 => pc_bx_ary_slp_nsl_thold_3_ofu, + pc_bx_repr_sl_thold_3 => pc_bx_repr_sl_thold_3_ofu, + an_ac_scan_diag_dc => an_ac_scan_diag_dc_ofu, + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b_ofu, + time_scan_in => fu_bx_time_scan_out, + repr_scan_in => fu_bx_repr_scan_out, + abst_scan_in => rp_fu_bx_abst_scan_in, + time_scan_out => bx_xu_time_scan_out, + repr_scan_out => bx_xu_repr_scan_out, + abst_scan_out => bx_fu_rp_abst_scan_out, + gptr_scan_in => fu_bx_gptr_scan_out, + gptr_scan_out => bx_xu_gptr_scan_out, + func_scan_in => rp_fu_bx_func_scan_in, + func_scan_out => bx_fu_rp_func_scan_out + ); -- end component a_bxq +end generate; + + +nobx: if include_boxes=0 generate begin + bx_xu_ex5_dp_data <= (others=>'0'); + bx_xu_ex4_mtdp_cr_status <= '0'; + bx_xu_ex4_mfdp_cr_status <= '0'; + bx_lsu_ob_pwr_tok <= '0'; + bx_lsu_ob_req_val <= '0'; + bx_lsu_ob_ditc_val <= '0'; + bx_lsu_ob_thrd <= (others=>'0'); + bx_lsu_ob_qw <= (others=>'0'); + bx_lsu_ob_dest <= (others=>'0'); + bx_lsu_ob_data <= (others=>'0'); + bx_lsu_ob_addr <= (others=>'0'); + ac_an_reld_ditc_pop_int <= (others=>'0'); + bx_ib_empty_int <= (others=>'1'); + bx_xu_quiesce <= (others=>'1'); + bx_xu_slowspr_addr <= fu_bx_slowspr_addr; + bx_xu_slowspr_data <= fu_bx_slowspr_data; + bx_xu_slowspr_done <= fu_bx_slowspr_done; + bx_xu_slowspr_etid <= fu_bx_slowspr_etid; + bx_xu_slowspr_rw <= fu_bx_slowspr_rw; + bx_xu_slowspr_val <= fu_bx_slowspr_val; + bx_pc_err_inbox_ecc <= '0'; + bx_pc_err_outbox_ecc <= '0'; + bx_pc_err_inbox_ue <= '0'; + bx_pc_err_outbox_ue <= '0'; + bx_fu_debug_data <= debug_start_tiedowns; + bx_fu_trigger_data <= trigger_start_tiedowns; + bx_xu_time_scan_out <= fu_bx_time_scan_out; + bx_xu_repr_scan_out <= fu_bx_repr_scan_out; + bx_rp_abst_scan_out <= rp_bx_abst_scan_in_q; + fu_bx_gptr_scan_out <= fu_bx_gptr_scan_out; + bx_rp_func_scan_out <= rp_bx_func_scan_in_q; +end generate; + + +END acq_soft; diff --git a/rel/src/vhdl/work/bxq.vhdl b/rel/src/vhdl/work/bxq.vhdl new file mode 100644 index 0000000..e883e13 --- /dev/null +++ b/rel/src/vhdl/work/bxq.vhdl @@ -0,0 +1,7120 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XU Inbox/Outbox logic for message passing between processors +-- + +LIBRARY ieee; USE ieee.std_logic_1164.all ; + USE ieee.numeric_std.all; +LIBRARY ibm; + USE ibm.std_ulogic_support.all ; + USE ibm.std_ulogic_function_support.all; + USE ibm.std_ulogic_unsigned.all; +LIBRARY tri; USE tri.tri_latches_pkg.all; +LIBRARY support; + USE support.power_logic_pkg.all; +LIBRARY clib; + + +ENTITY bxq IS + generic(expand_type : integer := 2; -- 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) + regmode : integer := 6; -- 5 = 32bit mode, 6 = 64bit mode + real_data_add : integer := 42 ); -- 42 bit real address + PORT ( + xu_bx_ccr2_en_ditc :in std_ulogic; + xu_ex2_flush :in std_ulogic_vector(0 to 3); + xu_ex3_flush :in std_ulogic_vector(0 to 3); + xu_ex4_flush :in std_ulogic_vector(0 to 3); + xu_ex5_flush :in std_ulogic_vector(0 to 3); + xu_bx_ex1_mtdp_val :in std_ulogic; -- command from mtdp is valid + xu_bx_ex1_mfdp_val :in std_ulogic; -- command from mtdp is valid + xu_bx_ex1_ipc_thrd :in std_ulogic_vector(0 to 1); -- Thread ID + xu_bx_ex2_ipc_ba :in std_ulogic_vector(0 to 4); -- offset into the active 64B buffer + xu_bx_ex2_ipc_sz :in std_ulogic_vector(0 to 1); -- size of data (00=4B, 10=16B) + xu_bx_ex4_256st_data :in std_ulogic_vector(0 to 127); -- 16B of data to put into outbox buffer + + bx_xu_ex4_mtdp_cr_status :out std_ulogic; -- status (pas/fail) of the mtdp (sets CR) + bx_xu_ex4_mfdp_cr_status :out std_ulogic; -- status (pas/fail) of the mfdp (sets CR) + bx_xu_ex5_dp_data :out std_ulogic_vector(0 to 127); -- 16B of data from the inbox buffer + + -- outputs to network or l2 from outbox + bx_lsu_ob_pwr_tok :out std_ulogic; + bx_lsu_ob_req_val :out std_ulogic; -- message buffer data is ready to send + bx_lsu_ob_ditc_val :out std_ulogic; -- send dtic command + bx_lsu_ob_thrd :out std_ulogic_vector(0 to 1); -- source thread + bx_lsu_ob_qw :out std_ulogic_vector(58 to 59); -- quadword data pointer + bx_lsu_ob_dest :out std_ulogic_vector(0 to 14); -- destination for the packet + bx_lsu_ob_data :out std_ulogic_vector(0 to 127); -- 16B of data from the outbox + bx_lsu_ob_addr :out std_ulogic_vector(64-real_data_add to 57); -- address for boxes message + + ac_an_reld_ditc_pop :out std_ulogic_vector(0 to 3); -- return credit from inbox (per thread) + + bx_ib_empty :out std_ulogic_vector(0 to 3); -- inbox is empty + bx_xu_quiesce :out std_ulogic_vector(0 to 3); -- inbox and outbox are empty + + -- inputs from lsu + lsu_bx_cmd_avail :in std_ulogic; + lsu_bx_cmd_sent :in std_ulogic; + lsu_bx_cmd_stall :in std_ulogic; + + -- inputs from network or l2 going to inbox + + lsu_reld_data_vld :in std_ulogic; -- reload data is coming in 2 cycles + lsu_reld_core_tag :in std_ulogic_vector(3 to 4); -- reload data destinatoin tag (thread) + lsu_reld_qw :in std_ulogic_vector(58 to 59); -- reload data quadword pointer + lsu_reld_ditc :in std_ulogic; -- reload data is for ditc (inbox) + lsu_reld_data :in std_ulogic_vector(0 to 127); -- reload data + lsu_reld_ecc_err :in std_ulogic; -- reload data has ecc error + + lsu_req_st_pop :in std_ulogic; -- decrement outbox credit count + lsu_req_st_pop_thrd :in std_ulogic_vector(0 to 2); -- decrement outbox credit count + + -- Slow SPR Bus + slowspr_val_in :in std_ulogic; + slowspr_rw_in :in std_ulogic; + slowspr_etid_in :in std_ulogic_vector(0 to 1); + slowspr_addr_in :in std_ulogic_vector(0 to 9); + slowspr_data_in :in std_ulogic_vector(64-(2**REGMODE) to 63); + slowspr_done_in :in std_ulogic; + slowspr_val_out :out std_ulogic; + slowspr_rw_out :out std_ulogic; + slowspr_etid_out :out std_ulogic_vector(0 to 1); + slowspr_addr_out :out std_ulogic_vector(0 to 9); + slowspr_data_out :out std_ulogic_vector(64-(2**REGMODE) to 63); + slowspr_done_out :out std_ulogic; + + bx_pc_err_inbox_ecc :out std_ulogic; + bx_pc_err_outbox_ecc :out std_ulogic; + bx_pc_err_inbox_ue :out std_ulogic; + bx_pc_err_outbox_ue :out std_ulogic; + pc_bx_inj_inbox_ecc :in std_ulogic; + pc_bx_inj_outbox_ecc :in std_ulogic; + + -- debug connections + pc_bx_trace_bus_enable : in std_ulogic; + pc_bx_debug_mux1_ctrls : in std_ulogic_vector(0 to 15); + trigger_data_in : in std_ulogic_vector(0 to 11); + debug_data_in : in std_ulogic_vector(0 to 87); + trigger_data_out : out std_ulogic_vector(0 to 11); + debug_data_out : out std_ulogic_vector(0 to 87); + + +-- power + vdd : inout power_logic; + gnd : inout power_logic; + vcs : inout power_logic; + + pc_bx_abist_di_0 :in std_ulogic_vector(0 to 3); + pc_bx_abist_g8t_bw_1 :in std_ulogic; + pc_bx_abist_g8t_bw_0 :in std_ulogic; + pc_bx_abist_waddr_0 :in std_ulogic_vector(4 to 9); + pc_bx_abist_g8t_wenb :in std_ulogic; + pc_bx_abist_raddr_0 :in std_ulogic_vector(4 to 9); + pc_bx_abist_g8t1p_renb_0 :in std_ulogic; + an_ac_lbist_ary_wrt_thru_dc :in std_ulogic; + pc_bx_abist_ena_dc :in std_ulogic; + pc_bx_abist_wl64_comp_ena :in std_ulogic; + pc_bx_abist_raw_dc_b :in std_ulogic; + pc_bx_abist_g8t_dcomp :in std_ulogic_vector(0 to 3); + + nclk :in clk_logic; + pc_bx_ccflush_dc : in std_ulogic; + pc_bx_sg_3 : in std_ulogic; + pc_bx_func_sl_thold_3 : in std_ulogic; + pc_bx_func_slp_sl_thold_3 : in std_ulogic; + pc_bx_gptr_sl_thold_3 : in std_ulogic; + pc_bx_abst_sl_thold_3 : in std_ulogic; + pc_bx_time_sl_thold_3 : in std_ulogic; + pc_bx_ary_nsl_thold_3 : in std_ulogic; + pc_bx_ary_slp_nsl_thold_3 : in std_ulogic; + pc_bx_repr_sl_thold_3 : in std_ulogic; + pc_bx_bolt_sl_thold_3 : in std_ulogic; + an_ac_scan_diag_dc : in std_ulogic; + an_ac_scan_dis_dc_b : in std_ulogic; + + pc_bx_bo_enable_3 : in std_ulogic; + pc_bx_bo_unload : in std_ulogic; + pc_bx_bo_repair : in std_ulogic; + pc_bx_bo_reset : in std_ulogic; + pc_bx_bo_shdata : in std_ulogic; + pc_bx_bo_select : in std_ulogic_vector(0 to 3); + bx_pc_bo_fail : out std_ulogic_vector(0 to 3); + bx_pc_bo_diagout : out std_ulogic_vector(0 to 3); + + + time_scan_in : in std_ulogic; + repr_scan_in : in std_ulogic; + abst_scan_in : in std_ulogic; + time_scan_out : out std_ulogic; + repr_scan_out : out std_ulogic; + abst_scan_out : out std_ulogic; + gptr_scan_in : in std_ulogic; + gptr_scan_out : out std_ulogic; + func_scan_in :in std_ulogic_vector(0 to 1); + func_scan_out :out std_ulogic_vector(0 to 1) + ); + + + + + + +END ; + +ARCHITECTURE bxq OF bxq IS + +signal ex4_mtdp_val_gated :std_ulogic; + +signal ob0_wrt_entry_ptr_d :std_ulogic_vector(0 to 1); -- outbox thread 0 write buffer entry pointer +signal ob0_wrt_entry_ptr_q :std_ulogic_vector(0 to 1); +signal ob0_set_val :std_ulogic; +signal ob1_wrt_entry_ptr_d :std_ulogic_vector(0 to 1); -- outbox thread 1 write buffer entry pointer +signal ob1_wrt_entry_ptr_q :std_ulogic_vector(0 to 1); +signal ob1_set_val :std_ulogic; +signal ob2_wrt_entry_ptr_d :std_ulogic_vector(0 to 1); -- outbox thread 2 write buffer entry pointer +signal ob2_wrt_entry_ptr_q :std_ulogic_vector(0 to 1); +signal ob2_set_val :std_ulogic; +signal ob3_wrt_entry_ptr_d :std_ulogic_vector(0 to 1); -- outbox thread 3 write buffer entry pointer +signal ob3_wrt_entry_ptr_q :std_ulogic_vector(0 to 1); +signal ob3_set_val :std_ulogic; + +signal ob_status_reg_newdata :std_ulogic_vector(0 to 17); -- data to be written into message buffer complete and status registers +signal ob0_buf0_status_d :std_ulogic_vector(0 to 17); -- outbox thread 0 buffer 0 message buffer complete register +signal ob0_buf1_status_d :std_ulogic_vector(0 to 17); -- outbox thread 0 buffer 1 message buffer complete register +signal ob0_buf2_status_d :std_ulogic_vector(0 to 17); -- outbox thread 0 buffer 2 message buffer complete register +signal ob0_buf3_status_d :std_ulogic_vector(0 to 17); -- outbox thread 0 buffer 3 message buffer complete register +signal ob1_buf0_status_d :std_ulogic_vector(0 to 17); -- outbox thread 1 buffer 0 message buffer complete register +signal ob1_buf1_status_d :std_ulogic_vector(0 to 17); -- outbox thread 1 buffer 1 message buffer complete register +signal ob1_buf2_status_d :std_ulogic_vector(0 to 17); -- outbox thread 1 buffer 2 message buffer complete register +signal ob1_buf3_status_d :std_ulogic_vector(0 to 17); -- outbox thread 1 buffer 3 message buffer complete register +signal ob2_buf0_status_d :std_ulogic_vector(0 to 17); -- outbox thread 2 buffer 0 message buffer complete register +signal ob2_buf1_status_d :std_ulogic_vector(0 to 17); -- outbox thread 2 buffer 1 message buffer complete register +signal ob2_buf2_status_d :std_ulogic_vector(0 to 17); -- outbox thread 2 buffer 2 message buffer complete register +signal ob2_buf3_status_d :std_ulogic_vector(0 to 17); -- outbox thread 2 buffer 3 message buffer complete register +signal ob3_buf0_status_d :std_ulogic_vector(0 to 17); -- outbox thread 3 buffer 0 message buffer complete register +signal ob3_buf1_status_d :std_ulogic_vector(0 to 17); -- outbox thread 3 buffer 1 message buffer complete register +signal ob3_buf2_status_d :std_ulogic_vector(0 to 17); -- outbox thread 3 buffer 2 message buffer complete register +signal ob3_buf3_status_d :std_ulogic_vector(0 to 17); -- outbox thread 3 buffer 3 message buffer complete register +signal ob0_buf0_status_q :std_ulogic_vector(0 to 17); -- outbox thread 0 buffer 0 message buffer complete register +signal ob0_buf1_status_q :std_ulogic_vector(0 to 17); -- outbox thread 0 buffer 1 message buffer complete register +signal ob0_buf2_status_q :std_ulogic_vector(0 to 17); -- outbox thread 0 buffer 2 message buffer complete register +signal ob0_buf3_status_q :std_ulogic_vector(0 to 17); -- outbox thread 0 buffer 3 message buffer complete register +signal ob1_buf0_status_q :std_ulogic_vector(0 to 17); -- outbox thread 1 buffer 0 message buffer complete register +signal ob1_buf1_status_q :std_ulogic_vector(0 to 17); -- outbox thread 1 buffer 1 message buffer complete register +signal ob1_buf2_status_q :std_ulogic_vector(0 to 17); -- outbox thread 1 buffer 2 message buffer complete register +signal ob1_buf3_status_q :std_ulogic_vector(0 to 17); -- outbox thread 1 buffer 3 message buffer complete register +signal ob2_buf0_status_q :std_ulogic_vector(0 to 17); -- outbox thread 2 buffer 0 message buffer complete register +signal ob2_buf1_status_q :std_ulogic_vector(0 to 17); -- outbox thread 2 buffer 1 message buffer complete register +signal ob2_buf2_status_q :std_ulogic_vector(0 to 17); -- outbox thread 2 buffer 2 message buffer complete register +signal ob2_buf3_status_q :std_ulogic_vector(0 to 17); -- outbox thread 2 buffer 3 message buffer complete register +signal ob3_buf0_status_q :std_ulogic_vector(0 to 17); -- outbox thread 3 buffer 0 message buffer complete register +signal ob3_buf1_status_q :std_ulogic_vector(0 to 17); -- outbox thread 3 buffer 1 message buffer complete register +signal ob3_buf2_status_q :std_ulogic_vector(0 to 17); -- outbox thread 3 buffer 2 message buffer complete register +signal ob3_buf3_status_q :std_ulogic_vector(0 to 17); -- outbox thread 3 buffer 3 message buffer complete register +signal wrt_ob0_buf0_status :std_ulogic; +signal wrt_ob0_buf1_status :std_ulogic; +signal wrt_ob0_buf2_status :std_ulogic; +signal wrt_ob0_buf3_status :std_ulogic; +signal wrt_ob1_buf0_status :std_ulogic; +signal wrt_ob1_buf1_status :std_ulogic; +signal wrt_ob1_buf2_status :std_ulogic; +signal wrt_ob1_buf3_status :std_ulogic; +signal wrt_ob2_buf0_status :std_ulogic; +signal wrt_ob2_buf1_status :std_ulogic; +signal wrt_ob2_buf2_status :std_ulogic; +signal wrt_ob2_buf3_status :std_ulogic; +signal wrt_ob3_buf0_status :std_ulogic; +signal wrt_ob3_buf1_status :std_ulogic; +signal wrt_ob3_buf2_status :std_ulogic; +signal wrt_ob3_buf3_status :std_ulogic; +signal ex4_wrt_ob_status :std_ulogic_vector(0 to 15); +signal ex5_wrt_ob_status_q :std_ulogic_vector(0 to 15); +signal ex5_wrt_ob_status_gated :std_ulogic_vector(0 to 15); +signal ex6_wrt_ob_status_q :std_ulogic_vector(0 to 15); +signal ex5_ob0_buf0_flushed :std_ulogic; +signal ex5_ob0_buf1_flushed :std_ulogic; +signal ex5_ob0_buf2_flushed :std_ulogic; +signal ex5_ob0_buf3_flushed :std_ulogic; +signal ex5_ob1_buf0_flushed :std_ulogic; +signal ex5_ob1_buf1_flushed :std_ulogic; +signal ex5_ob1_buf2_flushed :std_ulogic; +signal ex5_ob1_buf3_flushed :std_ulogic; +signal ex5_ob2_buf0_flushed :std_ulogic; +signal ex5_ob2_buf1_flushed :std_ulogic; +signal ex5_ob2_buf2_flushed :std_ulogic; +signal ex5_ob2_buf3_flushed :std_ulogic; +signal ex5_ob3_buf0_flushed :std_ulogic; +signal ex5_ob3_buf1_flushed :std_ulogic; +signal ex5_ob3_buf2_flushed :std_ulogic; +signal ex5_ob3_buf3_flushed :std_ulogic; +signal ex5_ob0_flushed :std_ulogic; +signal ex5_ob1_flushed :std_ulogic; +signal ex5_ob2_flushed :std_ulogic; +signal ex5_ob3_flushed :std_ulogic; +signal ex6_ob0_buf0_flushed :std_ulogic; +signal ex6_ob0_buf1_flushed :std_ulogic; +signal ex6_ob0_buf2_flushed :std_ulogic; +signal ex6_ob0_buf3_flushed :std_ulogic; +signal ex6_ob1_buf0_flushed :std_ulogic; +signal ex6_ob1_buf1_flushed :std_ulogic; +signal ex6_ob1_buf2_flushed :std_ulogic; +signal ex6_ob1_buf3_flushed :std_ulogic; +signal ex6_ob2_buf0_flushed :std_ulogic; +signal ex6_ob2_buf1_flushed :std_ulogic; +signal ex6_ob2_buf2_flushed :std_ulogic; +signal ex6_ob2_buf3_flushed :std_ulogic; +signal ex6_ob3_buf0_flushed :std_ulogic; +signal ex6_ob3_buf1_flushed :std_ulogic; +signal ex6_ob3_buf2_flushed :std_ulogic; +signal ex6_ob3_buf3_flushed :std_ulogic; +signal ex6_ob0_flushed :std_ulogic; +signal ex6_ob1_flushed :std_ulogic; +signal ex6_ob2_flushed :std_ulogic; +signal ex6_ob3_flushed :std_ulogic; +signal ob0_buf0_status_val :std_ulogic; +signal ob0_buf1_status_val :std_ulogic; +signal ob0_buf2_status_val :std_ulogic; +signal ob0_buf3_status_val :std_ulogic; +signal ob1_buf0_status_val :std_ulogic; +signal ob1_buf1_status_val :std_ulogic; +signal ob1_buf2_status_val :std_ulogic; +signal ob1_buf3_status_val :std_ulogic; +signal ob2_buf0_status_val :std_ulogic; +signal ob2_buf1_status_val :std_ulogic; +signal ob2_buf2_status_val :std_ulogic; +signal ob2_buf3_status_val :std_ulogic; +signal ob3_buf0_status_val :std_ulogic; +signal ob3_buf1_status_val :std_ulogic; +signal ob3_buf2_status_val :std_ulogic; +signal ob3_buf3_status_val :std_ulogic; + +signal ob_rd_data :std_ulogic_vector(0 to 127); +signal ob_rd_data1_l2 :std_ulogic_vector(0 to 127); +signal ob_rd_data_cor :std_ulogic_vector(0 to 127); +signal ob_rd_data_cor_l2 :std_ulogic_vector(0 to 127); +signal ob_rd_data_ecc0 :std_ulogic_vector(0 to 6); +signal ob_rd_data_ecc1 :std_ulogic_vector(0 to 6); +signal ob_rd_data_ecc2 :std_ulogic_vector(0 to 6); +signal ob_rd_data_ecc3 :std_ulogic_vector(0 to 6); +signal ob_rd_data_ecc0_l2 :std_ulogic_vector(0 to 6); +signal ob_rd_data_ecc1_l2 :std_ulogic_vector(0 to 6); +signal ob_rd_data_ecc2_l2 :std_ulogic_vector(0 to 6); +signal ob_rd_data_ecc3_l2 :std_ulogic_vector(0 to 6); +signal ob_rd_data_nsyn0 :std_ulogic_vector(0 to 6); +signal ob_rd_data_nsyn1 :std_ulogic_vector(0 to 6); +signal ob_rd_data_nsyn2 :std_ulogic_vector(0 to 6); +signal ob_rd_data_nsyn3 :std_ulogic_vector(0 to 6); +signal ob_ary_sbe :std_ulogic_vector(0 to 3); +signal ob_ary_sbe_q :std_ulogic_vector(0 to 3); +signal ob_ary_sbe_or :std_ulogic; +signal ob_ary_ue :std_ulogic_vector(0 to 3); +signal ob_ary_ue_q :std_ulogic_vector(0 to 3); +signal ob_ary_ue_or :std_ulogic; +signal ob_datain_ecc0 :std_ulogic_vector(0 to 6); +signal ob_datain_ecc1 :std_ulogic_vector(0 to 6); +signal ob_datain_ecc2 :std_ulogic_vector(0 to 6); +signal ob_datain_ecc3 :std_ulogic_vector(0 to 6); +signal ob_wrt_entry_ptr :std_ulogic_vector(0 to 1); +signal ob_wrt_addr :std_ulogic_vector(0 to 5); +signal ob_ary_wrt_addr_l2 :std_ulogic_vector(0 to 5); +signal ob_ary_rd_addr :std_ulogic_vector(0 to 5); +signal ob_buf_status_val :std_ulogic; +signal ex3_ob_buf_status_val :std_ulogic; +signal ob_wen :std_ulogic_vector(0 to 3); +signal ob_ary_wen_l2 :std_ulogic_vector(0 to 3); +signal ob_ary_wrt_data_l2 :std_ulogic_vector(0 to 127); + +signal ob0_rd_entry_ptr_d :std_ulogic_vector(0 to 1); +signal ob0_rd_entry_ptr_q :std_ulogic_vector(0 to 1); +signal ob1_rd_entry_ptr_d :std_ulogic_vector(0 to 1); +signal ob1_rd_entry_ptr_q :std_ulogic_vector(0 to 1); +signal ob2_rd_entry_ptr_d :std_ulogic_vector(0 to 1); +signal ob2_rd_entry_ptr_q :std_ulogic_vector(0 to 1); +signal ob3_rd_entry_ptr_d :std_ulogic_vector(0 to 1); +signal ob3_rd_entry_ptr_q :std_ulogic_vector(0 to 1); + +signal ob_to_node_status_reg :std_ulogic_vector(1 to 17); +signal ob0_to_nd_status_reg :std_ulogic_vector(0 to 17); +signal ob1_to_nd_status_reg :std_ulogic_vector(0 to 17); +signal ob2_to_nd_status_reg :std_ulogic_vector(0 to 17); +signal ob3_to_nd_status_reg :std_ulogic_vector(0 to 17); + +signal ob_to_node_sel_d :std_ulogic_vector(0 to 3); +signal ob_to_node_sel_q :std_ulogic_vector(0 to 3); +signal ob_to_node_sel_sav_d :std_ulogic_vector(0 to 3); +signal ob_to_node_sel_sav_q :std_ulogic_vector(0 to 3); +signal ob_to_nd_val_t0 :std_ulogic; +signal ob_to_nd_val_t1 :std_ulogic; +signal ob_to_nd_val_t2 :std_ulogic; +signal ob_to_nd_val_t3 :std_ulogic; +signal ob_to_nd_status_reg_vals :std_ulogic_vector(0 to 3); + +signal send_ob_idle :std_ulogic; +signal send_ob_data1 :std_ulogic; +signal send_ob_data2 :std_ulogic; +signal send_ob_data3 :std_ulogic; +signal send_ob_data4 :std_ulogic; +signal send_ob_ditc :std_ulogic; +signal send_ob_wait :std_ulogic; +signal send_ob_nxt_idle :std_ulogic; +signal send_ob_nxt_data1 :std_ulogic; +signal send_ob_nxt_data2 :std_ulogic; +signal send_ob_nxt_data3 :std_ulogic; +signal send_ob_nxt_data4 :std_ulogic; +signal send_ob_nxt_ditc :std_ulogic; +signal send_ob_nxt_wait :std_ulogic; +signal ob_to_nd_done_d :std_ulogic; +signal send_ob_nxt_state :std_ulogic_vector(0 to 6); +signal send_ob_state_q :std_ulogic_vector(0 to 6); + +signal ob0_buf_done :std_ulogic; +signal ob1_buf_done :std_ulogic; +signal ob2_buf_done :std_ulogic; +signal ob3_buf_done :std_ulogic; +signal ob0_buf0_done :std_ulogic; +signal ob0_buf1_done :std_ulogic; +signal ob0_buf2_done :std_ulogic; +signal ob0_buf3_done :std_ulogic; +signal ob1_buf0_done :std_ulogic; +signal ob1_buf1_done :std_ulogic; +signal ob1_buf2_done :std_ulogic; +signal ob1_buf3_done :std_ulogic; +signal ob2_buf0_done :std_ulogic; +signal ob2_buf1_done :std_ulogic; +signal ob2_buf2_done :std_ulogic; +signal ob2_buf3_done :std_ulogic; +signal ob3_buf0_done :std_ulogic; +signal ob3_buf1_done :std_ulogic; +signal ob3_buf2_done :std_ulogic; +signal ob3_buf3_done :std_ulogic; + +signal ob_to_node_selected_thrd :std_ulogic_vector(0 to 1); +signal ob_to_node_selected_rd_ptr :std_ulogic_vector(0 to 1); +signal ob_to_node_data_ptr :std_ulogic_vector(0 to 1); +signal send_ob_seq_ptr :std_ulogic_vector(0 to 1); + +signal dly_ob_cmd_val_q :std_ulogic_vector(0 to 1); +signal dly_ob_cmd_val_d :std_ulogic_vector(0 to 1); +signal bx_lsu_ob_req_val_d :std_ulogic; +signal bx_lsu_ob_req_val_int :std_ulogic; +signal send_ob_data_val :std_ulogic; +signal send_ob_ditc_val :std_ulogic; +signal dly_ob_ditc_val_q :std_ulogic_vector(0 to 1); +signal dly_ob_ditc_val_d :std_ulogic_vector(0 to 1); +signal dly_ob_qw :std_ulogic_vector(58 to 59); +signal dly1_ob_qw :std_ulogic_vector(58 to 59); +signal ob_addr_d :std_ulogic_vector(64-real_data_add to 57); + +signal lat_st_pop :std_ulogic; +signal lat_st_pop_thrd :std_ulogic_vector(0 to 2); +signal ob_pop :std_ulogic_vector(0 to 3); +signal ob_cmd_count_incr_t0 :std_ulogic_vector(0 to 1); +signal ob_cmd_count_decr_t0 :std_ulogic_vector(0 to 1); +signal ob_cmd_count_t0_d :std_ulogic_vector(0 to 1); +signal ob_cmd_count_t0_q :std_ulogic_vector(0 to 1); +signal ob_credit_t0 :std_ulogic; +signal ob_cmd_count_incr_t1 :std_ulogic_vector(0 to 1); +signal ob_cmd_count_decr_t1 :std_ulogic_vector(0 to 1); +signal ob_cmd_count_t1_d :std_ulogic_vector(0 to 1); +signal ob_cmd_count_t1_q :std_ulogic_vector(0 to 1); +signal ob_credit_t1 :std_ulogic; +signal ob_cmd_count_incr_t2 :std_ulogic_vector(0 to 1); +signal ob_cmd_count_decr_t2 :std_ulogic_vector(0 to 1); +signal ob_cmd_count_t2_d :std_ulogic_vector(0 to 1); +signal ob_cmd_count_t2_q :std_ulogic_vector(0 to 1); +signal ob_credit_t2 :std_ulogic; +signal ob_cmd_count_incr_t3 :std_ulogic_vector(0 to 1); +signal ob_cmd_count_decr_t3 :std_ulogic_vector(0 to 1); +signal ob_cmd_count_t3_d :std_ulogic_vector(0 to 1); +signal ob_cmd_count_t3_q :std_ulogic_vector(0 to 1); +signal ob_credit_t3 :std_ulogic; +signal ob_to_nd_ready :std_ulogic; +signal ob_lsu_complete :std_ulogic; +signal lsu_cmd_avail_q :std_ulogic; +signal lsu_cmd_sent_q :std_ulogic; +signal lsu_cmd_stall_q :std_ulogic; +signal ob_cmd_sent_count_d :std_ulogic_vector(0 to 2); +signal ob_cmd_sent_count_q :std_ulogic_vector(0 to 2); + +signal wrt_ib0_buf0_status :std_ulogic; +signal wrt_ib0_buf1_status :std_ulogic; +signal wrt_ib0_buf2_status :std_ulogic; +signal wrt_ib0_buf3_status :std_ulogic; +signal wrt_ib1_buf0_status :std_ulogic; +signal wrt_ib1_buf1_status :std_ulogic; +signal wrt_ib1_buf2_status :std_ulogic; +signal wrt_ib1_buf3_status :std_ulogic; +signal wrt_ib2_buf0_status :std_ulogic; +signal wrt_ib2_buf1_status :std_ulogic; +signal wrt_ib2_buf2_status :std_ulogic; +signal wrt_ib2_buf3_status :std_ulogic; +signal wrt_ib3_buf0_status :std_ulogic; +signal wrt_ib3_buf1_status :std_ulogic; +signal wrt_ib3_buf2_status :std_ulogic; +signal wrt_ib3_buf3_status :std_ulogic; +signal ib0_incr_ptr :std_ulogic; +signal ib1_incr_ptr :std_ulogic; +signal ib2_incr_ptr :std_ulogic; +signal ib3_incr_ptr :std_ulogic; +signal ib0_decr_ptr :std_ulogic; +signal ib1_decr_ptr :std_ulogic; +signal ib2_decr_ptr :std_ulogic; +signal ib3_decr_ptr :std_ulogic; +signal ib0_decr_ptr_by2 :std_ulogic; +signal ib1_decr_ptr_by2 :std_ulogic; +signal ib2_decr_ptr_by2 :std_ulogic; +signal ib3_decr_ptr_by2 :std_ulogic; +signal ib0_decr_ptr_by3 :std_ulogic; +signal ib1_decr_ptr_by3 :std_ulogic; +signal ib2_decr_ptr_by3 :std_ulogic; +signal ib3_decr_ptr_by3 :std_ulogic; +signal ex4_wrt_ib_status :std_ulogic_vector(0 to 15); +signal ex5_wrt_ib_status_q :std_ulogic_vector(0 to 15); +signal ex5_wrt_ib_status_gated :std_ulogic_vector(0 to 15); +signal ex6_wrt_ib_status_q :std_ulogic_vector(0 to 15); +signal ex5_ib0_buf0_flushed :std_ulogic; +signal ex5_ib0_buf1_flushed :std_ulogic; +signal ex5_ib0_buf2_flushed :std_ulogic; +signal ex5_ib0_buf3_flushed :std_ulogic; +signal ex5_ib1_buf0_flushed :std_ulogic; +signal ex5_ib1_buf1_flushed :std_ulogic; +signal ex5_ib1_buf2_flushed :std_ulogic; +signal ex5_ib1_buf3_flushed :std_ulogic; +signal ex5_ib2_buf0_flushed :std_ulogic; +signal ex5_ib2_buf1_flushed :std_ulogic; +signal ex5_ib2_buf2_flushed :std_ulogic; +signal ex5_ib2_buf3_flushed :std_ulogic; +signal ex5_ib3_buf0_flushed :std_ulogic; +signal ex5_ib3_buf1_flushed :std_ulogic; +signal ex5_ib3_buf2_flushed :std_ulogic; +signal ex5_ib3_buf3_flushed :std_ulogic; +signal ex4_ib0_flushed :std_ulogic; +signal ex4_ib1_flushed :std_ulogic; +signal ex4_ib2_flushed :std_ulogic; +signal ex4_ib3_flushed :std_ulogic; +signal ex5_ib0_flushed :std_ulogic; +signal ex5_ib1_flushed :std_ulogic; +signal ex5_ib2_flushed :std_ulogic; +signal ex5_ib3_flushed :std_ulogic; +signal ex6_ib0_buf0_flushed :std_ulogic; +signal ex6_ib0_buf1_flushed :std_ulogic; +signal ex6_ib0_buf2_flushed :std_ulogic; +signal ex6_ib0_buf3_flushed :std_ulogic; +signal ex6_ib1_buf0_flushed :std_ulogic; +signal ex6_ib1_buf1_flushed :std_ulogic; +signal ex6_ib1_buf2_flushed :std_ulogic; +signal ex6_ib1_buf3_flushed :std_ulogic; +signal ex6_ib2_buf0_flushed :std_ulogic; +signal ex6_ib2_buf1_flushed :std_ulogic; +signal ex6_ib2_buf2_flushed :std_ulogic; +signal ex6_ib2_buf3_flushed :std_ulogic; +signal ex6_ib3_buf0_flushed :std_ulogic; +signal ex6_ib3_buf1_flushed :std_ulogic; +signal ex6_ib3_buf2_flushed :std_ulogic; +signal ex6_ib3_buf3_flushed :std_ulogic; +signal ex6_ib0_flushed :std_ulogic; +signal ex6_ib1_flushed :std_ulogic; +signal ex6_ib2_flushed :std_ulogic; +signal ex6_ib3_flushed :std_ulogic; +signal ib_t0_pop_d :std_ulogic; +signal ib_t1_pop_d :std_ulogic; +signal ib_t2_pop_d :std_ulogic; +signal ib_t3_pop_d :std_ulogic; + +signal ib0_buf0_val_d :std_ulogic; -- outbox thread 0 buffer 0 val register +signal ib0_buf1_val_d :std_ulogic; -- outbox thread 0 buffer 1 val register +signal ib0_buf2_val_d :std_ulogic; -- outbox thread 0 buffer 2 val register +signal ib0_buf3_val_d :std_ulogic; -- outbox thread 0 buffer 3 val register +signal ib1_buf0_val_d :std_ulogic; -- outbox thread 1 buffer 0 val register +signal ib1_buf1_val_d :std_ulogic; -- outbox thread 1 buffer 1 val register +signal ib1_buf2_val_d :std_ulogic; -- outbox thread 1 buffer 2 val register +signal ib1_buf3_val_d :std_ulogic; -- outbox thread 1 buffer 3 val register +signal ib2_buf0_val_d :std_ulogic; -- outbox thread 2 buffer 0 val register +signal ib2_buf1_val_d :std_ulogic; -- outbox thread 2 buffer 1 val register +signal ib2_buf2_val_d :std_ulogic; -- outbox thread 2 buffer 2 val register +signal ib2_buf3_val_d :std_ulogic; -- outbox thread 2 buffer 3 val register +signal ib3_buf0_val_d :std_ulogic; -- outbox thread 3 buffer 0 val register +signal ib3_buf1_val_d :std_ulogic; -- outbox thread 3 buffer 1 val register +signal ib3_buf2_val_d :std_ulogic; -- outbox thread 3 buffer 2 val register +signal ib3_buf3_val_d :std_ulogic; -- outbox thread 3 buffer 3 val register +signal ib0_buf0_val_q :std_ulogic; -- outbox thread 0 buffer 0 val register +signal ib0_buf1_val_q :std_ulogic; -- outbox thread 0 buffer 1 val register +signal ib0_buf2_val_q :std_ulogic; -- outbox thread 0 buffer 2 val register +signal ib0_buf3_val_q :std_ulogic; -- outbox thread 0 buffer 3 val register +signal ib1_buf0_val_q :std_ulogic; -- outbox thread 1 buffer 0 val register +signal ib1_buf1_val_q :std_ulogic; -- outbox thread 1 buffer 1 val register +signal ib1_buf2_val_q :std_ulogic; -- outbox thread 1 buffer 2 val register +signal ib1_buf3_val_q :std_ulogic; -- outbox thread 1 buffer 3 val register +signal ib2_buf0_val_q :std_ulogic; -- outbox thread 2 buffer 0 val register +signal ib2_buf1_val_q :std_ulogic; -- outbox thread 2 buffer 1 val register +signal ib2_buf2_val_q :std_ulogic; -- outbox thread 2 buffer 2 val register +signal ib2_buf3_val_q :std_ulogic; -- outbox thread 2 buffer 3 val register +signal ib3_buf0_val_q :std_ulogic; -- outbox thread 3 buffer 0 val register +signal ib3_buf1_val_q :std_ulogic; -- outbox thread 3 buffer 1 val register +signal ib3_buf2_val_q :std_ulogic; -- outbox thread 3 buffer 2 val register +signal ib3_buf3_val_q :std_ulogic; -- outbox thread 3 buffer 3 val register +signal ib0_rd_val_reg :std_ulogic; +signal ib1_rd_val_reg :std_ulogic; +signal ib2_rd_val_reg :std_ulogic; +signal ib3_rd_val_reg :std_ulogic; +signal ex4_ib_rd_status_reg :std_ulogic; +signal ex4_ib_val_save :std_ulogic; +signal ex5_ib_val_save_q :std_ulogic; +signal ex6_ib_val_save_q :std_ulogic; +signal ib_empty_d :std_ulogic_vector(0 to 3); +signal quiesce_d :std_ulogic_vector(0 to 3); + +signal ex3_data_w0_sel :std_ulogic_vector(0 to 3); +signal ex3_data_w1_sel :std_ulogic_vector(0 to 3); +signal ex3_data_w2_sel :std_ulogic_vector(0 to 3); +signal ex3_data_w3_sel :std_ulogic_vector(0 to 3); +signal ex3_data_sel_status :std_ulogic; +signal ex3_inbox_data :std_ulogic_vector(0 to 127); +signal ex4_inbox_data :std_ulogic_vector(0 to 127); +signal ex5_inbox_data_cor :std_ulogic_vector(0 to 127); + +signal ib0_buf0_set_val :std_ulogic; +signal ib0_buf1_set_val :std_ulogic; +signal ib0_buf2_set_val :std_ulogic; +signal ib0_buf3_set_val :std_ulogic; +signal ib1_buf0_set_val :std_ulogic; +signal ib1_buf1_set_val :std_ulogic; +signal ib1_buf2_set_val :std_ulogic; +signal ib1_buf3_set_val :std_ulogic; +signal ib2_buf0_set_val :std_ulogic; +signal ib2_buf1_set_val :std_ulogic; +signal ib2_buf2_set_val :std_ulogic; +signal ib2_buf3_set_val :std_ulogic; +signal ib3_buf0_set_val :std_ulogic; +signal ib3_buf1_set_val :std_ulogic; +signal ib3_buf2_set_val :std_ulogic; +signal ib3_buf3_set_val :std_ulogic; +signal ib0_buf0_reset_val :std_ulogic; +signal ib0_buf1_reset_val :std_ulogic; +signal ib0_buf2_reset_val :std_ulogic; +signal ib0_buf3_reset_val :std_ulogic; +signal ib1_buf0_reset_val :std_ulogic; +signal ib1_buf1_reset_val :std_ulogic; +signal ib1_buf2_reset_val :std_ulogic; +signal ib1_buf3_reset_val :std_ulogic; +signal ib2_buf0_reset_val :std_ulogic; +signal ib2_buf1_reset_val :std_ulogic; +signal ib2_buf2_reset_val :std_ulogic; +signal ib2_buf3_reset_val :std_ulogic; +signal ib3_buf0_reset_val :std_ulogic; +signal ib3_buf1_reset_val :std_ulogic; +signal ib3_buf2_reset_val :std_ulogic; +signal ib3_buf3_reset_val :std_ulogic; + +signal ib0_rd_entry_ptr_d :std_ulogic_vector(0 to 1); +signal ib1_rd_entry_ptr_d :std_ulogic_vector(0 to 1); +signal ib2_rd_entry_ptr_d :std_ulogic_vector(0 to 1); +signal ib3_rd_entry_ptr_d :std_ulogic_vector(0 to 1); +signal ib0_rd_entry_ptr_q :std_ulogic_vector(0 to 1); +signal ib1_rd_entry_ptr_q :std_ulogic_vector(0 to 1); +signal ib2_rd_entry_ptr_q :std_ulogic_vector(0 to 1); +signal ib3_rd_entry_ptr_q :std_ulogic_vector(0 to 1); +signal ib0_rd_entry_ptr_dly_q :std_ulogic_vector(0 to 1); +signal ib1_rd_entry_ptr_dly_q :std_ulogic_vector(0 to 1); +signal ib2_rd_entry_ptr_dly_q :std_ulogic_vector(0 to 1); +signal ib3_rd_entry_ptr_dly_q :std_ulogic_vector(0 to 1); + signal ib_rd_entry_ptr :std_ulogic_vector(0 to 1); + +signal ib_ary_rd_addr :std_ulogic_vector(0 to 5); +signal ib_wen :std_ulogic; +signal ib_ary_wen :std_ulogic_vector(0 to 3); +signal ib_ary_wrt_addr :std_ulogic_vector(0 to 5); +signal ib_rd_data :std_ulogic_vector(0 to 127); +signal ib_rd_data_cor :std_ulogic_vector(0 to 127); +signal ib_rd_data_ecc0 :std_ulogic_vector(0 to 6); +signal ib_rd_data_ecc1 :std_ulogic_vector(0 to 6); +signal ib_rd_data_ecc2 :std_ulogic_vector(0 to 6); +signal ib_rd_data_ecc3 :std_ulogic_vector(0 to 6); +signal ex3_ib_data_ecc0 :std_ulogic_vector(0 to 6); +signal ex3_ib_data_ecc1 :std_ulogic_vector(0 to 6); +signal ex3_ib_data_ecc2 :std_ulogic_vector(0 to 6); +signal ex3_ib_data_ecc3 :std_ulogic_vector(0 to 6); +signal ex4_ib_data_ecc0 :std_ulogic_vector(0 to 6); +signal ex4_ib_data_ecc1 :std_ulogic_vector(0 to 6); +signal ex4_ib_data_ecc2 :std_ulogic_vector(0 to 6); +signal ex4_ib_data_ecc3 :std_ulogic_vector(0 to 6); +signal ib_rd_data_nsyn0 :std_ulogic_vector(0 to 6); +signal ib_rd_data_nsyn1 :std_ulogic_vector(0 to 6); +signal ib_rd_data_nsyn2 :std_ulogic_vector(0 to 6); +signal ib_rd_data_nsyn3 :std_ulogic_vector(0 to 6); +signal ib_datain_ecc0 :std_ulogic_vector(0 to 6); +signal ib_datain_ecc1 :std_ulogic_vector(0 to 6); +signal ib_datain_ecc2 :std_ulogic_vector(0 to 6); +signal ib_datain_ecc3 :std_ulogic_vector(0 to 6); +signal ex4_ib_ecc_val :std_ulogic; +signal ex5_ib_ecc_val :std_ulogic; +signal ib_ary_ue_or :std_ulogic; +signal ib_ary_ue :std_ulogic_vector(0 to 3); +signal ib_ary_ue_q :std_ulogic_vector(0 to 3); +signal ib_ary_sbe_or :std_ulogic; +signal ib_ary_sbe :std_ulogic_vector(0 to 3); +signal ib_ary_sbe_q :std_ulogic_vector(0 to 3); +signal ob_abst_scan_out :std_ulogic; +signal ib_abst_scan_out :std_ulogic; +signal ob_time_scan_out :std_ulogic; +signal ib_time_scan_out :std_ulogic; +signal ob_repr_scan_out :std_ulogic; + +signal lat_reld_data_val :std_ulogic; +signal lat_reld_ditc :std_ulogic; +signal lat_reld_ecc_err :std_ulogic; +signal reld_data_val_dminus2 :std_ulogic; +signal reld_data_val_dminus1 :std_ulogic; +signal reld_data_val :std_ulogic; +signal reld_data_val_dplus1 :std_ulogic; +signal lat_reld_core_tag :std_ulogic_vector(3 to 4); +signal reld_core_tag_dminus1 :std_ulogic_vector(3 to 4); +signal reld_core_tag :std_ulogic_vector(3 to 4); +signal reld_core_tag_dplus1 :std_ulogic_vector(3 to 4); +signal lat_reld_qw :std_ulogic_vector(58 to 59); +signal reld_qw_dminus1 :std_ulogic_vector(58 to 59); +signal reld_qw :std_ulogic_vector(58 to 59); +signal lat_reld_data :std_ulogic_vector(0 to 127); + +signal ib0_wrt_entry_ptr_d :std_ulogic_vector(0 to 1); +signal ib1_wrt_entry_ptr_d :std_ulogic_vector(0 to 1); +signal ib2_wrt_entry_ptr_d :std_ulogic_vector(0 to 1); +signal ib3_wrt_entry_ptr_d :std_ulogic_vector(0 to 1); +signal ib0_wrt_entry_ptr_q :std_ulogic_vector(0 to 1); +signal ib1_wrt_entry_ptr_q :std_ulogic_vector(0 to 1); +signal ib2_wrt_entry_ptr_q :std_ulogic_vector(0 to 1); +signal ib3_wrt_entry_ptr_q :std_ulogic_vector(0 to 1); +signal ib0_wrt_entry_ptr :std_ulogic_vector(0 to 1); +signal ib1_wrt_entry_ptr :std_ulogic_vector(0 to 1); +signal ib2_wrt_entry_ptr :std_ulogic_vector(0 to 1); +signal ib3_wrt_entry_ptr :std_ulogic_vector(0 to 1); +signal ib0_wrt_entry_ptr_minus1 :std_ulogic_vector(0 to 1); +signal ib1_wrt_entry_ptr_minus1 :std_ulogic_vector(0 to 1); +signal ib2_wrt_entry_ptr_minus1 :std_ulogic_vector(0 to 1); +signal ib3_wrt_entry_ptr_minus1 :std_ulogic_vector(0 to 1); +signal dec_ib0_wrt_entry_ptr :std_ulogic; +signal dec_ib1_wrt_entry_ptr :std_ulogic; +signal dec_ib2_wrt_entry_ptr :std_ulogic; +signal dec_ib3_wrt_entry_ptr :std_ulogic; +signal ib0_wrt_data_ctr_d :std_ulogic_vector(0 to 1); +signal ib1_wrt_data_ctr_d :std_ulogic_vector(0 to 1); +signal ib2_wrt_data_ctr_d :std_ulogic_vector(0 to 1); +signal ib3_wrt_data_ctr_d :std_ulogic_vector(0 to 1); +signal ib0_wrt_data_ctr_q :std_ulogic_vector(0 to 1); +signal ib1_wrt_data_ctr_q :std_ulogic_vector(0 to 1); +signal ib2_wrt_data_ctr_q :std_ulogic_vector(0 to 1); +signal ib3_wrt_data_ctr_q :std_ulogic_vector(0 to 1); + + +signal ib_wrt_thrd :std_ulogic_vector(0 to 1); +signal ib_wrt_entry_pointer :std_ulogic_vector(0 to 1); + +signal ib0_set_val :std_ulogic; +signal ib1_set_val :std_ulogic; +signal ib2_set_val :std_ulogic; +signal ib3_set_val :std_ulogic; +signal ib0_set_val_q :std_ulogic; +signal ib1_set_val_q :std_ulogic; +signal ib2_set_val_q :std_ulogic; +signal ib3_set_val_q :std_ulogic; +signal ib0_ecc_err_d :std_ulogic; +signal ib1_ecc_err_d :std_ulogic; +signal ib2_ecc_err_d :std_ulogic; +signal ib3_ecc_err_d :std_ulogic; +signal ib0_ecc_err_q :std_ulogic; +signal ib1_ecc_err_q :std_ulogic; +signal ib2_ecc_err_q :std_ulogic; +signal ib3_ecc_err_q :std_ulogic; + +signal inbox_ecc_err_q :std_ulogic; +signal inbox_ue_q :std_ulogic; +signal outbox_ecc_err_q :std_ulogic; +signal outbox_ue_q :std_ulogic; + +signal ob0_buf0_clr :std_ulogic; +signal ob0_buf1_clr :std_ulogic; +signal ob0_buf2_clr :std_ulogic; +signal ob0_buf3_clr :std_ulogic; +signal ob1_buf0_clr :std_ulogic; +signal ob1_buf1_clr :std_ulogic; +signal ob1_buf2_clr :std_ulogic; +signal ob1_buf3_clr :std_ulogic; +signal ob2_buf0_clr :std_ulogic; +signal ob2_buf1_clr :std_ulogic; +signal ob2_buf2_clr :std_ulogic; +signal ob2_buf3_clr :std_ulogic; +signal ob3_buf0_clr :std_ulogic; +signal ob3_buf1_clr :std_ulogic; +signal ob3_buf2_clr :std_ulogic; +signal ob3_buf3_clr :std_ulogic; +signal ob0_buf0_status_avail :std_ulogic; +signal ob0_buf1_status_avail :std_ulogic; +signal ob0_buf2_status_avail :std_ulogic; +signal ob0_buf3_status_avail :std_ulogic; +signal ob1_buf0_status_avail :std_ulogic; +signal ob1_buf1_status_avail :std_ulogic; +signal ob1_buf2_status_avail :std_ulogic; +signal ob1_buf3_status_avail :std_ulogic; +signal ob2_buf0_status_avail :std_ulogic; +signal ob2_buf1_status_avail :std_ulogic; +signal ob2_buf2_status_avail :std_ulogic; +signal ob2_buf3_status_avail :std_ulogic; +signal ob3_buf0_status_avail :std_ulogic; +signal ob3_buf1_status_avail :std_ulogic; +signal ob3_buf2_status_avail :std_ulogic; +signal ob3_buf3_status_avail :std_ulogic; +signal ob_buf_status_avail_d :std_ulogic_vector(0 to 15); +signal ob_buf_status_avail_q :std_ulogic_vector(0 to 15); + +signal my_ccr2_en_ditc_q :std_ulogic; +signal my_ex3_flush :std_ulogic; +signal my_ex3_flush_q :std_ulogic_vector(0 to 3); +signal my_ex4_flush_q :std_ulogic_vector(0 to 3); +signal my_ex5_flush_q :std_ulogic_vector(0 to 3); +signal my_ex6_flush_q :std_ulogic_vector(0 to 3); +signal my_ex4_stg_flush :std_ulogic; +signal my_ex5_stg_flush :std_ulogic; +signal my_ex6_stg_flush :std_ulogic; +signal ex2_mfdp_val_q :std_ulogic; -- command from mtdp is valid +signal ex3_mfdp_val_q :std_ulogic; -- command from mtdp is valid +signal ex4_mfdp_val_q :std_ulogic; -- command from mtdp is valid +signal ex5_mfdp_val_q :std_ulogic; -- command from mtdp is valid +signal ex6_mfdp_val_q :std_ulogic; -- command from mtdp is valid +signal ex3_mtdp_val :std_ulogic; -- command from mtdp is valid +signal ex2_mtdp_val_q :std_ulogic; -- command from mtdp is valid +signal ex3_mtdp_val_q :std_ulogic; -- command from mtdp is valid +signal ex2_ipc_thrd_q :std_ulogic_vector(0 to 1); -- Thread ID +signal ex3_ipc_thrd_q :std_ulogic_vector(0 to 1); -- Thread ID +signal ex3_ipc_ba_q :std_ulogic_vector(0 to 4); -- offset into the active 64B buffer +signal ex3_ipc_sz_q :std_ulogic_vector(0 to 1); -- size of data (00=4B, 10=16B) +signal ex4_mtdp_val_q :std_ulogic; -- command from mtdp is valid +signal ex5_mtdp_val_q :std_ulogic; -- command from mtdp is valid +signal ex6_mtdp_val_q :std_ulogic; -- command from mtdp is valid +signal ex7_mtdp_val_q :std_ulogic; -- command from mtdp is valid +signal ex4_ipc_thrd_q :std_ulogic_vector(0 to 1); -- Thread ID +signal ex5_ipc_thrd_q :std_ulogic_vector(0 to 1); -- Thread ID +signal ex6_ipc_thrd_q :std_ulogic_vector(0 to 1); -- Thread ID +signal ex4_ipc_ba_q :std_ulogic_vector(0 to 4); -- offset into the active 64B buffer +signal ex4_ipc_sz_q :std_ulogic_vector(0 to 1); -- size of data (00=4B, 10=16B) +--signal ex4_256st_data_q :std_ulogic_vector(0 to 127); -- 16B of data to put into outbox buffer +--signal ex4_256st_data_par_q :std_ulogic_vector(0 to 15); -- parity accross the st_data +signal ex3_mtdp_cr_status :std_ulogic; +signal ex4_mtdp_cr_status :std_ulogic; +signal ex3_mfdp_cr_status :std_ulogic; +signal ex4_mfdp_cr_status_i :std_ulogic; + +signal ditc_addr_sel :std_ulogic; +signal ditc_addr_wen :std_ulogic; +signal ditc_addr_t0_wen :std_ulogic; +signal ditc_addr_t1_wen :std_ulogic; +signal ditc_addr_t2_wen :std_ulogic; +signal ditc_addr_t3_wen :std_ulogic; +signal ditc_addr_t0_d :std_ulogic_vector(64-real_data_add to 57); +signal ditc_addr_t1_d :std_ulogic_vector(64-real_data_add to 57); +signal ditc_addr_t2_d :std_ulogic_vector(64-real_data_add to 57); +signal ditc_addr_t3_d :std_ulogic_vector(64-real_data_add to 57); +signal ditc_addr_t0_q :std_ulogic_vector(64-real_data_add to 57); +signal ditc_addr_t1_q :std_ulogic_vector(64-real_data_add to 57); +signal ditc_addr_t2_q :std_ulogic_vector(64-real_data_add to 57); +signal ditc_addr_t3_q :std_ulogic_vector(64-real_data_add to 57); +signal ditc_addr_reg :std_ulogic_vector(64-(2**REGMODE) to 63); +signal ditc_addr_rd_val :std_ulogic; +signal xu_slowspr_data_d :std_ulogic_vector(64-(2**REGMODE) to 63); +signal xu_slowspr_done_d :std_ulogic; +signal xu_slowspr_val_d :std_ulogic; +signal xu_slowspr_rw_d :std_ulogic; +signal xu_slowspr_etid_d :std_ulogic_vector(0 to 1); +signal xu_slowspr_addr_d :std_ulogic_vector(0 to 9); +signal bx_slowspr_val_q :std_ulogic; +signal bx_slowspr_rw_q :std_ulogic; +signal bx_slowspr_etid_q :std_ulogic_vector(0 to 1); +signal bx_slowspr_addr_q :std_ulogic_vector(0 to 9); +signal bx_slowspr_data_q :std_ulogic_vector(64-(2**REGMODE) to 63); +signal bx_slowspr_done_q :std_ulogic; + +signal ob_rd_logic_act :std_ulogic; +signal ob_rd_logic_act_d :std_ulogic; +signal ob_rd_logic_act_q :std_ulogic; +signal mtdp_ex3_to_7_val :std_ulogic; +signal ib_buf_val_act :std_ulogic; +signal dp_op_val :std_ulogic; + +signal abist_di_0 :std_ulogic_vector(0 to 3); +signal abist_g8t_bw_1 :std_ulogic; +signal abist_g8t_bw_0 :std_ulogic; +signal abist_waddr_0 :std_ulogic_vector(4 to 9); +signal abist_g8t_wenb :std_ulogic; +signal abist_raddr_0 :std_ulogic_vector(4 to 9); +signal abist_g8t1p_renb_0 :std_ulogic; +signal abist_wl64_comp_ena :std_ulogic; +signal abist_g8t_dcomp :std_ulogic_vector(0 to 3); + +signal dbg_group0_d :std_ulogic_vector(0 to 17); +signal dbg_group0_q :std_ulogic_vector(0 to 17); +signal dbg_group0 :std_ulogic_vector(0 to 87); +signal dbg_group1 :std_ulogic_vector(0 to 87); +signal dbg_group2 :std_ulogic_vector(0 to 87); +signal dbg_group3 :std_ulogic_vector(0 to 87); +signal trg_group0 :std_ulogic_vector(0 to 11); +signal trg_group1 :std_ulogic_vector(0 to 11); +signal trg_group2 :std_ulogic_vector(0 to 11); +signal trg_group3 :std_ulogic_vector(0 to 11); +signal debug_mux1_ctrls_q :std_ulogic_vector(0 to 15); +signal debug_mux_out_d :std_ulogic_vector(0 to 87); +signal trigger_mux_out_d :std_ulogic_vector(0 to 11); +signal trace_bus_enable_q :std_ulogic; +signal spare0_l2 :std_ulogic_vector(0 to 7); +signal spare1_l2 :std_ulogic_vector(0 to 3); + +signal sg_2 :std_ulogic; +signal func_sl_thold_2 :std_ulogic; +signal func_slp_sl_thold_2 :std_ulogic; +signal abst_sl_thold_2 :std_ulogic; +signal time_sl_thold_2 :std_ulogic; +signal ary_nsl_thold_2 :std_ulogic; +signal ary_slp_nsl_thold_2 :std_ulogic; +signal gptr_sl_thold_2 :std_ulogic; +signal repr_sl_thold_2 :std_ulogic; +signal bolt_sl_thold_2 :std_ulogic; +signal bolt_enable_2 :std_ulogic; +signal func_sl_thold_1 :std_ulogic; +signal func_slp_sl_thold_1 :std_ulogic; +signal abst_sl_thold_1 :std_ulogic; +signal time_sl_thold_1 :std_ulogic; +signal ary_nsl_thold_1 :std_ulogic; +signal ary_slp_nsl_thold_1 :std_ulogic; +signal gptr_sl_thold_1 :std_ulogic; +signal repr_sl_thold_1 :std_ulogic; +signal bolt_sl_thold_1 :std_ulogic; +signal func_sl_thold_0 :std_ulogic; +signal func_slp_sl_thold_0 :std_ulogic; +signal ary_nsl_thold_0 :std_ulogic; +signal ary_slp_nsl_thold_0 :std_ulogic; +signal abst_sl_thold_0 :std_ulogic; +signal time_sl_thold_0 :std_ulogic; +signal repr_sl_thold_0 :std_ulogic; +signal gptr_sl_thold_0 :std_ulogic; +signal bolt_sl_thold_0 :std_ulogic; +signal slat_force :std_ulogic; +signal time_slat_thold_b :std_ulogic; +signal time_slat_d2clk :std_ulogic; +signal time_slat_lclk :clk_logic; +signal time_scan_out_stg :std_ulogic; +signal repr_slat_thold_b :std_ulogic; +signal repr_slat_d2clk :std_ulogic; +signal repr_slat_lclk :clk_logic; + +signal clkoff_dc_b :std_ulogic; +signal d_mode_dc :std_ulogic; +signal delay_lclkr_dc :std_ulogic; +signal delay_lclkr_dc_v :std_ulogic_vector(0 to 4); +signal mpw1_dc_b :std_ulogic; +signal mpw1_dc_b_v :std_ulogic_vector(0 to 4); +signal mpw2_dc_b :std_ulogic; +signal ary0_clkoff_dc_b :std_ulogic; +signal ary0_d_mode_dc :std_ulogic; +signal ary0_delay_lclkr_dc_v :std_ulogic_vector(0 to 4); +signal ary0_mpw1_dc_b_v :std_ulogic_vector(0 to 4); +signal ary0_mpw2_dc_b :std_ulogic; +signal ary1_clkoff_dc_b :std_ulogic; +signal ary1_d_mode_dc :std_ulogic; +signal ary1_delay_lclkr_dc_v :std_ulogic_vector(0 to 4); +signal ary1_mpw1_dc_b_v :std_ulogic_vector(0 to 4); +signal ary1_mpw2_dc_b :std_ulogic; +signal int1_gptr_scan_out :std_ulogic; +signal int0_gptr_scan_out :std_ulogic; +signal int_repr_scan_out :std_ulogic; +signal repr_scan_out_q :std_ulogic; +signal repr_scan_in_q :std_ulogic; +signal int_gptr_scan_out :std_ulogic; +signal time_scan_in_q :std_ulogic; + +signal ob_err_inj_q :std_ulogic; +signal ib_err_inj_q :std_ulogic; +signal ob_ary_wrt_data_0 :std_ulogic; +signal lat_reld_data_0 :std_ulogic; + +signal sg_1 : std_ulogic; +signal sg_0 : std_ulogic; +signal func_sl_force : std_ulogic; +signal func_sl_thold_0_b : std_ulogic; +signal func_slp_sl_force : std_ulogic; +signal func_slp_sl_thold_0_b : std_ulogic; +signal abst_sl_force : std_ulogic; +signal abst_sl_thold_0_b : std_ulogic; + +signal tidn : std_ulogic; +signal unused :std_ulogic_vector(0 to 23); + +constant my_ex3_flush_offset : natural := 0; +constant my_ex4_flush_offset : natural :=my_ex3_flush_offset + my_ex3_flush_q'length; +constant my_ex5_flush_offset : natural :=my_ex4_flush_offset + my_ex4_flush_q'length; +constant my_ex6_flush_offset : natural :=my_ex5_flush_offset + my_ex5_flush_q'length; +constant my_ccr2_en_ditc_offset : natural :=my_ex6_flush_offset + my_ex6_flush_q'length; +constant ex2_mtdp_val_offset : natural :=my_ccr2_en_ditc_offset + 1; +constant ex3_mtdp_val_offset : natural :=ex2_mtdp_val_offset + 1; +constant ex4_mtdp_val_offset : natural :=ex3_mtdp_val_offset + 1; +constant ex5_mtdp_val_offset : natural :=ex4_mtdp_val_offset + 1; +constant ex6_mtdp_val_offset : natural :=ex5_mtdp_val_offset + 1; +constant ex7_mtdp_val_offset : natural :=ex6_mtdp_val_offset + 1; +constant ex2_mfdp_val_offset : natural :=ex7_mtdp_val_offset + 1; +constant ex3_mfdp_val_offset : natural :=ex2_mfdp_val_offset + 1; +constant ex4_mfdp_val_offset : natural :=ex3_mfdp_val_offset + 1; +constant ex5_mfdp_val_offset : natural :=ex4_mfdp_val_offset + 1; +constant ex6_mfdp_val_offset : natural :=ex5_mfdp_val_offset + 1; +constant ex2_ipc_thrd_offset : natural :=ex6_mfdp_val_offset + 1; +constant ex3_ipc_thrd_offset : natural :=ex2_ipc_thrd_offset + ex2_ipc_thrd_q'length; +constant ex3_ipc_ba_offset : natural :=ex3_ipc_thrd_offset + ex3_ipc_thrd_q'length; +constant ex3_ipc_sz_offset : natural :=ex3_ipc_ba_offset + ex3_ipc_ba_q'length; +constant bx_slowspr_val_offset : natural :=ex3_ipc_sz_offset + ex3_ipc_sz_q'length; +constant bx_slowspr_rw_offset : natural :=bx_slowspr_val_offset + 1; +constant bx_slowspr_etid_offset : natural :=bx_slowspr_rw_offset + 1; +constant bx_slowspr_addr_offset : natural :=bx_slowspr_etid_offset + bx_slowspr_etid_q'length; +constant bx_slowspr_data_offset : natural :=bx_slowspr_addr_offset + bx_slowspr_addr_q'length; +constant bx_slowspr_done_offset : natural :=bx_slowspr_data_offset + bx_slowspr_data_q'length; +constant xu_slowspr_val_offset : natural :=bx_slowspr_done_offset + 1; +constant xu_slowspr_rw_offset : natural :=xu_slowspr_val_offset + 1; +constant xu_slowspr_etid_offset : natural :=xu_slowspr_rw_offset + 1; +constant xu_slowspr_addr_offset : natural :=xu_slowspr_etid_offset + xu_slowspr_etid_d'length; +constant xu_slowspr_data_offset : natural :=xu_slowspr_addr_offset + xu_slowspr_addr_d'length; +constant xu_slowspr_done_offset : natural :=xu_slowspr_data_offset + xu_slowspr_data_d'length; +constant ditc_addr_t0_offset : natural :=xu_slowspr_done_offset + 1; +constant ditc_addr_t1_offset : natural :=ditc_addr_t0_offset + ditc_addr_t0_d'length; +constant ditc_addr_t2_offset : natural :=ditc_addr_t1_offset + ditc_addr_t1_d'length; +constant ditc_addr_t3_offset : natural :=ditc_addr_t2_offset + ditc_addr_t2_d'length; +constant ob0_wrt_entry_ptr_offset : natural :=ditc_addr_t3_offset + ditc_addr_t3_d'length; +constant ob1_wrt_entry_ptr_offset : natural :=ob0_wrt_entry_ptr_offset + ob0_wrt_entry_ptr_q'length; +constant ob2_wrt_entry_ptr_offset : natural :=ob1_wrt_entry_ptr_offset + ob1_wrt_entry_ptr_q'length; +constant ob3_wrt_entry_ptr_offset : natural :=ob2_wrt_entry_ptr_offset + ob2_wrt_entry_ptr_q'length; +constant ob_rd_logic_act_offset : natural :=ob3_wrt_entry_ptr_offset + ob3_wrt_entry_ptr_q'length; +constant ex5_wrt_ob_status_offset : natural :=ob_rd_logic_act_offset + 1; +constant ex6_wrt_ob_status_offset : natural :=ex5_wrt_ob_status_offset + ex5_wrt_ob_status_q'length; +constant ob0_buf0_status_offset : natural :=ex6_wrt_ob_status_offset + ex6_wrt_ob_status_q'length; +constant ob0_buf1_status_offset : natural :=ob0_buf0_status_offset + ob0_buf0_status_q'length; +constant ob0_buf2_status_offset : natural :=ob0_buf1_status_offset + ob0_buf1_status_q'length; +constant ob0_buf3_status_offset : natural :=ob0_buf2_status_offset + ob0_buf2_status_q'length; +constant ob1_buf0_status_offset : natural :=ob0_buf3_status_offset + ob0_buf3_status_q'length; +constant ob1_buf1_status_offset : natural :=ob1_buf0_status_offset + ob1_buf0_status_q'length; +constant ob1_buf2_status_offset : natural :=ob1_buf1_status_offset + ob1_buf1_status_q'length; +constant ob1_buf3_status_offset : natural :=ob1_buf2_status_offset + ob1_buf2_status_q'length; +constant ob2_buf0_status_offset : natural :=ob1_buf3_status_offset + ob1_buf3_status_q'length; +constant ob2_buf1_status_offset : natural :=ob2_buf0_status_offset + ob2_buf0_status_q'length; +constant ob2_buf2_status_offset : natural :=ob2_buf1_status_offset + ob2_buf1_status_q'length; +constant ob2_buf3_status_offset : natural :=ob2_buf2_status_offset + ob2_buf2_status_q'length; +constant ob3_buf0_status_offset : natural :=ob2_buf3_status_offset + ob2_buf3_status_q'length; +constant ob3_buf1_status_offset : natural :=ob3_buf0_status_offset + ob3_buf0_status_q'length; +constant ob3_buf2_status_offset : natural :=ob3_buf1_status_offset + ob3_buf1_status_q'length; +constant ob3_buf3_status_offset : natural :=ob3_buf2_status_offset + ob3_buf2_status_q'length; +constant spare0_offset : natural :=ob3_buf3_status_offset + ob3_buf3_status_q'length; +constant ob_buf_status_avail_offset : natural :=spare0_offset + spare0_l2'length; +constant ex4_mtdp_cr_status_offset : natural :=ob_buf_status_avail_offset + ob_buf_status_avail_q'length; +constant ob_wrt_data_offset : natural :=ex4_mtdp_cr_status_offset + 1; +constant ob_ary_wen_offset : natural :=ob_wrt_data_offset + ob_ary_wrt_data_l2'length; +constant ob_ary_wrt_addr_offset : natural :=ob_ary_wen_offset + ob_ary_wen_l2'length; +constant ob_err_inj_offset : natural :=ob_ary_wrt_addr_offset + ob_ary_wrt_addr_l2'length; +constant ob_rd_data1_offset : natural :=ob_err_inj_offset + 1; + + +constant ob_rd_data_ecc0_offset : natural :=ob_rd_data1_offset + ob_rd_data1_l2'length; +constant ob_rd_data_ecc1_offset : natural :=ob_rd_data_ecc0_offset + ob_rd_data_ecc0'length; +constant ob_rd_data_ecc2_offset : natural :=ob_rd_data_ecc1_offset + ob_rd_data_ecc1'length; +constant ob_rd_data_ecc3_offset : natural :=ob_rd_data_ecc2_offset + ob_rd_data_ecc2'length; + + +constant ob_ary_sbe_offset : natural :=ob_rd_data_ecc3_offset + ob_rd_data_ecc3'length; +constant ob_ary_ue_offset : natural :=ob_ary_sbe_offset + ob_ary_sbe_q'length; +constant ob_rd_data_cor_offset : natural :=ob_ary_ue_offset + ob_ary_ue_q'length; +constant outbox_ecc_err_offset : natural :=ob_rd_data_cor_offset + ob_rd_data_cor'length; +constant outbox_ue_offset : natural :=outbox_ecc_err_offset + 1; +constant ob0_rd_entry_ptr_offset : natural :=outbox_ue_offset + 1; +constant ob1_rd_entry_ptr_offset : natural :=ob0_rd_entry_ptr_offset + ob0_rd_entry_ptr_q'length; +constant ob2_rd_entry_ptr_offset : natural :=ob1_rd_entry_ptr_offset + ob1_rd_entry_ptr_q'length; +constant ob3_rd_entry_ptr_offset : natural :=ob2_rd_entry_ptr_offset + ob2_rd_entry_ptr_q'length; +constant ob_to_node_sel_offset : natural :=ob3_rd_entry_ptr_offset + ob3_rd_entry_ptr_q'length; + +constant scan_right0 : natural :=ob_to_node_sel_offset + ob_to_node_sel_q'length; + +constant ob_to_node_sel_sav_offset : natural :=ob_to_node_sel_offset + ob_to_node_sel_q'length; +constant lsu_cmd_avail_offset : natural :=ob_to_node_sel_sav_offset + ob_to_node_sel_sav_q'length; +constant lsu_cmd_sent_offset : natural :=lsu_cmd_avail_offset + 1; +constant lsu_cmd_stall_offset : natural :=lsu_cmd_sent_offset + 1; +constant ob_cmd_sent_count_offset : natural :=lsu_cmd_stall_offset + 1; +constant send_ob_state_offset : natural :=ob_cmd_sent_count_offset + ob_cmd_sent_count_q'length; +constant spare1_offset : natural :=send_ob_state_offset + send_ob_state_q'length; +constant dly_ob_cmd_val_offset : natural :=spare1_offset + spare1_l2'length; +constant bxlsu_ob_req_val_offset : natural :=dly_ob_cmd_val_offset + dly_ob_cmd_val_q'length; +constant dly_ob_ditc_val_offset : natural :=bxlsu_ob_req_val_offset + 1; +constant bxlsu_ob_ditc_val_offset : natural :=dly_ob_ditc_val_offset + dly_ob_ditc_val_q'length; +constant dly_ob_qw_offset : natural :=bxlsu_ob_ditc_val_offset + 1; +constant dly1_ob_qw_offset : natural :=dly_ob_qw_offset + dly_ob_qw'length; +constant bxlsu_ob_qw_offset : natural :=dly1_ob_qw_offset + dly1_ob_qw'length; +constant bxlsu_ob_thrd_offset : natural :=bxlsu_ob_qw_offset + bx_lsu_ob_qw'length; +constant bxlsu_ob_addr_offset : natural :=bxlsu_ob_thrd_offset + bx_lsu_ob_thrd'length; +constant bxlsu_ob_dest_offset : natural :=bxlsu_ob_addr_offset + bx_lsu_ob_addr'length; +constant st_pop_offset : natural :=bxlsu_ob_dest_offset + bx_lsu_ob_dest'length; +constant st_pop_thrd_offset : natural :=st_pop_offset + 1; +constant ob_cmd_count_t0_offset : natural :=st_pop_thrd_offset + lat_st_pop_thrd'length; +constant ob_cmd_count_t1_offset : natural :=ob_cmd_count_t0_offset + ob_cmd_count_t0_q'length; +constant ob_cmd_count_t2_offset : natural :=ob_cmd_count_t1_offset + ob_cmd_count_t1_q'length; +constant ob_cmd_count_t3_offset : natural :=ob_cmd_count_t2_offset + ob_cmd_count_t2_q'length; +constant ex5_wrt_ib_status_offset : natural :=ob_cmd_count_t3_offset + ob_cmd_count_t3_q'length; +constant ex6_wrt_ib_status_offset : natural :=ex5_wrt_ib_status_offset + ex5_wrt_ib_status_q'length; +constant ipc_ib_t0_pop_offset : natural :=ex6_wrt_ib_status_offset + ex6_wrt_ib_status_q'length; +constant ipc_ib_t1_pop_offset : natural :=ipc_ib_t0_pop_offset + 1; +constant ipc_ib_t2_pop_offset : natural :=ipc_ib_t1_pop_offset + 1; +constant ipc_ib_t3_pop_offset : natural :=ipc_ib_t2_pop_offset + 1; +constant ib0_buf0_val_offset : natural :=ipc_ib_t3_pop_offset + 1; +constant ib0_buf1_val_offset : natural :=ib0_buf0_val_offset + 1; +constant ib0_buf2_val_offset : natural :=ib0_buf1_val_offset + 1; +constant ib0_buf3_val_offset : natural :=ib0_buf2_val_offset + 1; +constant ib1_buf0_val_offset : natural :=ib0_buf3_val_offset + 1; +constant ib1_buf1_val_offset : natural :=ib1_buf0_val_offset + 1; +constant ib1_buf2_val_offset : natural :=ib1_buf1_val_offset + 1; +constant ib1_buf3_val_offset : natural :=ib1_buf2_val_offset + 1; +constant ib2_buf0_val_offset : natural :=ib1_buf3_val_offset + 1; +constant ib2_buf1_val_offset : natural :=ib2_buf0_val_offset + 1; +constant ib2_buf2_val_offset : natural :=ib2_buf1_val_offset + 1; +constant ib2_buf3_val_offset : natural :=ib2_buf2_val_offset + 1; +constant ib3_buf0_val_offset : natural :=ib2_buf3_val_offset + 1; +constant ib3_buf1_val_offset : natural :=ib3_buf0_val_offset + 1; +constant ib3_buf2_val_offset : natural :=ib3_buf1_val_offset + 1; +constant ib3_buf3_val_offset : natural :=ib3_buf2_val_offset + 1; +constant ex5_ib_val_save_offset : natural :=ib3_buf3_val_offset + 1; +constant ex6_ib_val_save_offset : natural :=ex5_ib_val_save_offset + 1; +constant ib_empty_offset : natural :=ex6_ib_val_save_offset + 1; +constant quiesce_offset : natural :=ib_empty_offset + ib_empty_d'length; +constant ib0_rd_entry_ptr_offset : natural :=quiesce_offset + quiesce_d'length; +constant ib1_rd_entry_ptr_offset : natural :=ib0_rd_entry_ptr_offset + ib0_rd_entry_ptr_q'length; +constant ib2_rd_entry_ptr_offset : natural :=ib1_rd_entry_ptr_offset + ib1_rd_entry_ptr_q'length; +constant ib3_rd_entry_ptr_offset : natural :=ib2_rd_entry_ptr_offset + ib2_rd_entry_ptr_q'length; +constant ib0_rd_entry_ptr_dly_offset : natural :=ib3_rd_entry_ptr_offset + ib3_rd_entry_ptr_q'length; +constant ib1_rd_entry_ptr_dly_offset : natural :=ib0_rd_entry_ptr_dly_offset + ib0_rd_entry_ptr_dly_q'length; +constant ib2_rd_entry_ptr_dly_offset : natural :=ib1_rd_entry_ptr_dly_offset + ib1_rd_entry_ptr_dly_q'length; +constant ib3_rd_entry_ptr_dly_offset : natural :=ib2_rd_entry_ptr_dly_offset + ib2_rd_entry_ptr_dly_q'length; + + +constant ib_err_inj_offset : natural :=ib3_rd_entry_ptr_dly_offset + ib3_rd_entry_ptr_dly_q'length; +constant ex5_inbox_data_cor_offset : natural :=ib_err_inj_offset + 1; +constant ib_ary_sbe_offset : natural :=ex5_inbox_data_cor_offset + ex5_inbox_data_cor'length; +constant ib_ary_ue_offset : natural :=ib_ary_sbe_offset + ib_ary_sbe_q'length; +constant inbox_ecc_err_offset : natural :=ib_ary_ue_offset + ib_ary_ue_q'length; +constant inbox_ue_offset : natural :=inbox_ecc_err_offset + 1; +constant ex4_ipc_thrd_offset : natural :=inbox_ue_offset + 1; +constant ex5_ipc_thrd_offset : natural :=ex4_ipc_thrd_offset + ex4_ipc_thrd_q'length; +constant ex6_ipc_thrd_offset : natural :=ex5_ipc_thrd_offset + ex5_ipc_thrd_q'length; +constant ex4_ipc_ba_offset : natural :=ex6_ipc_thrd_offset + ex6_ipc_thrd_q'length; +constant ex4_ipc_sz_offset : natural :=ex4_ipc_ba_offset + ex4_ipc_ba_q'length; +constant ex4_dp_data_offset : natural :=ex4_ipc_sz_offset + ex4_ipc_sz_q'length; +constant ex4_ib_data_ecc0_offset : natural :=ex4_dp_data_offset + ex4_inbox_data'length; +constant ex4_ib_data_ecc1_offset : natural :=ex4_ib_data_ecc0_offset + ex4_ib_data_ecc0'length; +constant ex4_ib_data_ecc2_offset : natural :=ex4_ib_data_ecc1_offset + ex4_ib_data_ecc1'length; +constant ex4_ib_data_ecc3_offset : natural :=ex4_ib_data_ecc2_offset + ex4_ib_data_ecc2'length; +constant ex4_mfdp_cr_status_offset : natural :=ex4_ib_data_ecc3_offset + ex4_ib_data_ecc3'length; +constant ex5_ib_ecc_val_offset : natural :=ex4_mfdp_cr_status_offset + 1; +constant reld_data_val_offset : natural :=ex5_ib_ecc_val_offset + 1; +constant reld_data_val_dplus1_offset : natural :=reld_data_val_offset + 1; +constant reld_ditc_offset : natural :=reld_data_val_dplus1_offset + 1; +constant reld_ecc_err_offset : natural :=reld_ditc_offset + 1; +constant reld_data_val_dminus2_offset : natural :=reld_ecc_err_offset + 1; +constant reld_data_val_dminus1_offset : natural :=reld_data_val_dminus2_offset + 1; +constant reld_core_tag_dminus2_offset : natural :=reld_data_val_dminus1_offset + 1; +constant reld_core_tag_dminus1_offset : natural :=reld_core_tag_dminus2_offset + lat_reld_core_tag'length; +constant reld_core_tag_offset : natural :=reld_core_tag_dminus1_offset + reld_core_tag_dminus1'length; +constant reld_core_tag_dplus1_offset : natural :=reld_core_tag_offset + reld_core_tag'length; +constant reld_qw_dminus2_offset : natural :=reld_core_tag_dplus1_offset + reld_core_tag_dplus1'length; +constant reld_qw_dminus1_offset : natural :=reld_qw_dminus2_offset + lat_reld_qw'length; +constant reld_qw_offset : natural :=reld_qw_dminus1_offset + reld_qw_dminus1'length; +constant reld_data_offset : natural :=reld_qw_offset + reld_qw'length; +constant ib0_wrt_entry_ptr_offset : natural :=reld_data_offset + lat_reld_data'length; +constant ib1_wrt_entry_ptr_offset : natural :=ib0_wrt_entry_ptr_offset + ib0_wrt_entry_ptr_q'length; +constant ib2_wrt_entry_ptr_offset : natural :=ib1_wrt_entry_ptr_offset + ib1_wrt_entry_ptr_q'length; +constant ib3_wrt_entry_ptr_offset : natural :=ib2_wrt_entry_ptr_offset + ib2_wrt_entry_ptr_q'length; +constant ib0_wrt_data_ctr_offset : natural :=ib3_wrt_entry_ptr_offset + ib3_wrt_entry_ptr_q'length; +constant ib1_wrt_data_ctr_offset : natural :=ib0_wrt_data_ctr_offset + ib0_wrt_data_ctr_q'length; +constant ib2_wrt_data_ctr_offset : natural :=ib1_wrt_data_ctr_offset + ib1_wrt_data_ctr_q'length; +constant ib3_wrt_data_ctr_offset : natural :=ib2_wrt_data_ctr_offset + ib2_wrt_data_ctr_q'length; +constant ib0_ecc_err_offset : natural :=ib3_wrt_data_ctr_offset + ib3_wrt_data_ctr_q'length; +constant ib1_ecc_err_offset : natural :=ib0_ecc_err_offset + 1; +constant ib2_ecc_err_offset : natural :=ib1_ecc_err_offset + 1; +constant ib3_ecc_err_offset : natural :=ib2_ecc_err_offset + 1; +constant ib0_set_val_offset : natural :=ib3_ecc_err_offset + 1; +constant ib1_set_val_offset : natural :=ib0_set_val_offset + 1; +constant ib2_set_val_offset : natural :=ib1_set_val_offset + 1; +constant ib3_set_val_offset : natural :=ib2_set_val_offset + 1; +constant debug_dbg_group0_offset : natural :=ib3_set_val_offset + 1; +constant trace_bus_enable_offset : natural :=debug_dbg_group0_offset + dbg_group0_q'length; +constant debug_mux_ctrls_offset : natural :=trace_bus_enable_offset + 1; +constant debug_mux_out_offset : natural :=debug_mux_ctrls_offset + debug_mux1_ctrls_q'length; +constant trigger_mux_out_offset : natural :=debug_mux_out_offset + debug_mux_out_d'length; + +constant scan_right1 : natural :=trigger_mux_out_offset + trigger_mux_out_d'length; + +signal siv : std_ulogic_vector(0 to scan_right1-1); +signal sov : std_ulogic_vector(0 to scan_right1-1); +signal ab_reg_si : std_ulogic_vector(0 to 24); +signal ab_reg_so : std_ulogic_vector(0 to 24); + +signal unused_signals : std_ulogic; + +begin + + +tidn <= '0'; + +unused_signals <= or_reduce(unused & delay_lclkr_dc_v(1 to 4) & mpw1_dc_b_v(1 to 4)); + +dp_op_val <= mtdp_ex3_to_7_val or ex3_mfdp_val_q or ex4_mfdp_val_q or ex5_mfdp_val_q or ex6_mfdp_val_q; + +--********************************************************************************************** +-- Latch XU interface signals +--********************************************************************************************** + +latch_my_ex3_flush : tri_rlmreg_p + generic map (width => my_ex3_flush_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(my_ex3_flush_offset to my_ex3_flush_offset + my_ex3_flush_q'length-1), + scout => sov(my_ex3_flush_offset to my_ex3_flush_offset + my_ex3_flush_q'length-1), + din => xu_ex2_flush, + dout => my_ex3_flush_q ); + +my_ex3_flush <= (my_ex3_flush_q(0) and ex3_ipc_thrd_q="00") or + (my_ex3_flush_q(1) and ex3_ipc_thrd_q="01") or + (my_ex3_flush_q(2) and ex3_ipc_thrd_q="10") or + (my_ex3_flush_q(3) and ex3_ipc_thrd_q="11"); + +latch_my_ex4_flush : tri_rlmreg_p + generic map (width => my_ex4_flush_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dp_op_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(my_ex4_flush_offset to my_ex4_flush_offset + my_ex4_flush_q'length-1), + scout => sov(my_ex4_flush_offset to my_ex4_flush_offset + my_ex4_flush_q'length-1), + din => xu_ex3_flush, + dout => my_ex4_flush_q ); + +my_ex4_stg_flush <= (my_ex4_flush_q(0) and (ex4_ipc_thrd_q(0 to 1)="00")) or + (my_ex4_flush_q(1) and (ex4_ipc_thrd_q(0 to 1)="01")) or + (my_ex4_flush_q(2) and (ex4_ipc_thrd_q(0 to 1)="10")) or + (my_ex4_flush_q(3) and (ex4_ipc_thrd_q(0 to 1)="11")); + +latch_my_ex5_flush : tri_rlmreg_p + generic map (width => my_ex4_flush_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dp_op_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(my_ex5_flush_offset to my_ex5_flush_offset + my_ex5_flush_q'length-1), + scout => sov(my_ex5_flush_offset to my_ex5_flush_offset + my_ex5_flush_q'length-1), + din => xu_ex4_flush, + dout => my_ex5_flush_q ); + +my_ex5_stg_flush <= (my_ex5_flush_q(0) and (ex5_ipc_thrd_q(0 to 1)="00")) or + (my_ex5_flush_q(1) and (ex5_ipc_thrd_q(0 to 1)="01")) or + (my_ex5_flush_q(2) and (ex5_ipc_thrd_q(0 to 1)="10")) or + (my_ex5_flush_q(3) and (ex5_ipc_thrd_q(0 to 1)="11")); + +latch_my_ex6_flush : tri_rlmreg_p + generic map (width => my_ex4_flush_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dp_op_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(my_ex6_flush_offset to my_ex6_flush_offset + my_ex6_flush_q'length-1), + scout => sov(my_ex6_flush_offset to my_ex6_flush_offset + my_ex6_flush_q'length-1), + din => xu_ex5_flush, + dout => my_ex6_flush_q ); + +my_ex6_stg_flush <= (my_ex6_flush_q(0) and (ex6_ipc_thrd_q(0 to 1)="00")) or + (my_ex6_flush_q(1) and (ex6_ipc_thrd_q(0 to 1)="01")) or + (my_ex6_flush_q(2) and (ex6_ipc_thrd_q(0 to 1)="10")) or + (my_ex6_flush_q(3) and (ex6_ipc_thrd_q(0 to 1)="11")); + +latch_my_ccr2_en_ditc : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(my_ccr2_en_ditc_offset to my_ccr2_en_ditc_offset), + scout => sov(my_ccr2_en_ditc_offset to my_ccr2_en_ditc_offset), + din(0) => xu_bx_ccr2_en_ditc, + dout(0) => my_ccr2_en_ditc_q ); + +latch_ex2_mtdp_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex2_mtdp_val_offset to ex2_mtdp_val_offset), + scout => sov(ex2_mtdp_val_offset to ex2_mtdp_val_offset), + din(0) => xu_bx_ex1_mtdp_val, + dout(0) => ex2_mtdp_val_q ); + +latch_ex3_mtdp_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex3_mtdp_val_offset to ex3_mtdp_val_offset), + scout => sov(ex3_mtdp_val_offset to ex3_mtdp_val_offset), + din(0) => ex2_mtdp_val_q, + dout(0) => ex3_mtdp_val_q ); + +ex3_mtdp_val <= ex3_mtdp_val_q and not my_ex3_flush and my_ccr2_en_ditc_q; + +latch_ex4_mtdp_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => mtdp_ex3_to_7_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_mtdp_val_offset to ex4_mtdp_val_offset), + scout => sov(ex4_mtdp_val_offset to ex4_mtdp_val_offset), + din(0) => ex3_mtdp_val, + dout(0) => ex4_mtdp_val_q ); +latch_ex5_mtdp_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => mtdp_ex3_to_7_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex5_mtdp_val_offset to ex5_mtdp_val_offset), + scout => sov(ex5_mtdp_val_offset to ex5_mtdp_val_offset), + din(0) => ex4_mtdp_val_q, + dout(0) => ex5_mtdp_val_q ); +latch_ex6_mtdp_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => mtdp_ex3_to_7_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex6_mtdp_val_offset to ex6_mtdp_val_offset), + scout => sov(ex6_mtdp_val_offset to ex6_mtdp_val_offset), + din(0) => ex5_mtdp_val_q, + dout(0) => ex6_mtdp_val_q ); +latch_ex7_mtdp_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => mtdp_ex3_to_7_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex7_mtdp_val_offset to ex7_mtdp_val_offset), + scout => sov(ex7_mtdp_val_offset to ex7_mtdp_val_offset), + din(0) => ex6_mtdp_val_q, + dout(0) => ex7_mtdp_val_q ); + +mtdp_ex3_to_7_val <= ex3_mtdp_val_q or ex4_mtdp_val_q or ex5_mtdp_val_q or ex6_mtdp_val_q or ex7_mtdp_val_q; + +latch_ex2_mfdp_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex2_mfdp_val_offset to ex2_mfdp_val_offset), + scout => sov(ex2_mfdp_val_offset to ex2_mfdp_val_offset), + din(0) => xu_bx_ex1_mfdp_val, + dout(0) => ex2_mfdp_val_q ); +latch_ex3_mfdp_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex3_mfdp_val_offset to ex3_mfdp_val_offset), + scout => sov(ex3_mfdp_val_offset to ex3_mfdp_val_offset), + din(0) => ex2_mfdp_val_q, + dout(0) => ex3_mfdp_val_q ); +latch_ex4_mfdp_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dp_op_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_mfdp_val_offset to ex4_mfdp_val_offset), + scout => sov(ex4_mfdp_val_offset to ex4_mfdp_val_offset), + din(0) => ex3_mfdp_val_q, + dout(0) => ex4_mfdp_val_q ); +latch_ex5_mfdp_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dp_op_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex5_mfdp_val_offset to ex5_mfdp_val_offset), + scout => sov(ex5_mfdp_val_offset to ex5_mfdp_val_offset), + din(0) => ex4_mfdp_val_q, + dout(0) => ex5_mfdp_val_q ); +latch_ex6_mfdp_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dp_op_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex6_mfdp_val_offset to ex6_mfdp_val_offset), + scout => sov(ex6_mfdp_val_offset to ex6_mfdp_val_offset), + din(0) => ex5_mfdp_val_q, + dout(0) => ex6_mfdp_val_q ); +latch_ex2_ipc_thrd : tri_rlmreg_p + generic map (width => ex2_ipc_thrd_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex2_ipc_thrd_offset to ex2_ipc_thrd_offset + ex2_ipc_thrd_q'length-1), + scout => sov(ex2_ipc_thrd_offset to ex2_ipc_thrd_offset + ex2_ipc_thrd_q'length-1), + din => xu_bx_ex1_ipc_thrd(0 to 1), + dout => ex2_ipc_thrd_q(0 to 1) ); +latch_ex3_ipc_thrd : tri_rlmreg_p + generic map (width => ex3_ipc_thrd_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex3_ipc_thrd_offset to ex3_ipc_thrd_offset + ex3_ipc_thrd_q'length-1), + scout => sov(ex3_ipc_thrd_offset to ex3_ipc_thrd_offset + ex3_ipc_thrd_q'length-1), + din => ex2_ipc_thrd_q(0 to 1), + dout => ex3_ipc_thrd_q(0 to 1) ); +latch_ex3_ipc_ba : tri_rlmreg_p + generic map (width => ex3_ipc_ba_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex3_ipc_ba_offset to ex3_ipc_ba_offset + ex3_ipc_ba_q'length-1), + scout => sov(ex3_ipc_ba_offset to ex3_ipc_ba_offset + ex3_ipc_ba_q'length-1), + din => xu_bx_ex2_ipc_ba(0 to 4), + dout => ex3_ipc_ba_q(0 to 4) ); +latch_ex3_ipc_sz : tri_rlmreg_p + generic map (width => ex3_ipc_sz_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex3_ipc_sz_offset to ex3_ipc_sz_offset + ex3_ipc_sz_q'length-1), + scout => sov(ex3_ipc_sz_offset to ex3_ipc_sz_offset + ex3_ipc_sz_q'length-1), + din => xu_bx_ex2_ipc_sz(0 to 1), + dout => ex3_ipc_sz_q(0 to 1) ); + +-- XXXXXXXXXXXXXXXXXX +-- Slow SPR's +-- XXXXXXXXXXXXXXXXXX + +ditc_addr_sel <= (bx_slowspr_addr_q = "11" & x"DF"); + +ditc_addr_wen <= bx_slowspr_val_q and ditc_addr_sel and not bx_slowspr_rw_q; + +-- SLOWSPR Writes + +-- Thread 0 SlowSPR Register +ditc_addr_t0_wen <= ditc_addr_wen and (bx_slowspr_etid_q = "00"); + +ditc_addr_t0_d <= bx_slowspr_data_q(64-real_data_add to 57) when ditc_addr_t0_wen='1' else + ditc_addr_t0_q; + +-- Thread 1 SlowSPR Register +ditc_addr_t1_wen <= ditc_addr_wen and (bx_slowspr_etid_q = "01"); + +ditc_addr_t1_d <= bx_slowspr_data_q(64-real_data_add to 57) when ditc_addr_t1_wen='1' else + ditc_addr_t1_q; + +-- Thread 2 SlowSPR Register +ditc_addr_t2_wen <= ditc_addr_wen and (bx_slowspr_etid_q = "10"); + +ditc_addr_t2_d <= bx_slowspr_data_q(64-real_data_add to 57) when ditc_addr_t2_wen='1' else + ditc_addr_t2_q; + +-- Thread 3 SlowSPR Register +ditc_addr_t3_wen <= ditc_addr_wen and (bx_slowspr_etid_q = "11"); + +ditc_addr_t3_d <= bx_slowspr_data_q(64-real_data_add to 57) when ditc_addr_t3_wen='1' else + ditc_addr_t3_q; + + +-- SLOWSPR Read +-- Thread Register Selection +with bx_slowspr_etid_q select + ditc_addr_reg(64-real_data_add to 57) <= ditc_addr_t0_q when "00", + ditc_addr_t1_q when "01", + ditc_addr_t2_q when "10", + ditc_addr_t3_q when others; + +ditc_addr_reg(64-(2**REGMODE) to 64-real_data_add-1) <= (others=>'0'); +ditc_addr_reg(58 to 63) <= (others=>'0'); + +-- SlowSPR Selection +ditc_addr_rd_val <= bx_slowspr_val_q and ditc_addr_sel and bx_slowspr_rw_q; + +xu_slowspr_data_d <= ditc_addr_reg when ditc_addr_rd_val='1' else + bx_slowspr_data_q; + +-- Operation Complete +xu_slowspr_done_d <= (bx_slowspr_val_q and ditc_addr_sel) or bx_slowspr_done_q; + + +xu_slowspr_val_d <= bx_slowspr_val_q; +xu_slowspr_rw_d <= bx_slowspr_rw_q; +xu_slowspr_etid_d <= bx_slowspr_etid_q; +xu_slowspr_addr_d <= bx_slowspr_addr_q; + +latch_bx_slowspr_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(bx_slowspr_val_offset to bx_slowspr_val_offset), + scout => sov(bx_slowspr_val_offset to bx_slowspr_val_offset), + din(0) => slowspr_val_in, + dout(0) => bx_slowspr_val_q ); + +latch_bx_slowspr_rw : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => slowspr_val_in, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(bx_slowspr_rw_offset to bx_slowspr_rw_offset), + scout => sov(bx_slowspr_rw_offset to bx_slowspr_rw_offset), + din(0) => slowspr_rw_in, + dout(0) => bx_slowspr_rw_q ); + +latch_bx_slowspr_etid : tri_rlmreg_p + generic map (width => bx_slowspr_etid_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => slowspr_val_in, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(bx_slowspr_etid_offset to bx_slowspr_etid_offset + bx_slowspr_etid_q'length-1), + scout => sov(bx_slowspr_etid_offset to bx_slowspr_etid_offset + bx_slowspr_etid_q'length-1), + din => slowspr_etid_in, + dout => bx_slowspr_etid_q ); + +latch_bx_slowspr_addr : tri_rlmreg_p + generic map (width => bx_slowspr_addr_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => slowspr_val_in, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(bx_slowspr_addr_offset to bx_slowspr_addr_offset + bx_slowspr_addr_q'length-1), + scout => sov(bx_slowspr_addr_offset to bx_slowspr_addr_offset + bx_slowspr_addr_q'length-1), + din => slowspr_addr_in, + dout => bx_slowspr_addr_q ); + +latch_bx_slowspr_data : tri_rlmreg_p + generic map (width => bx_slowspr_data_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => slowspr_val_in, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(bx_slowspr_data_offset to bx_slowspr_data_offset + bx_slowspr_data_q'length-1), + scout => sov(bx_slowspr_data_offset to bx_slowspr_data_offset + bx_slowspr_data_q'length-1), + din => slowspr_data_in, + dout => bx_slowspr_data_q ); + +latch_bx_slowspr_done : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => slowspr_val_in, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(bx_slowspr_done_offset to bx_slowspr_done_offset), + scout => sov(bx_slowspr_done_offset to bx_slowspr_done_offset), + din(0) => slowspr_done_in, + dout(0) => bx_slowspr_done_q ); + +latch_xu_slowspr_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(xu_slowspr_val_offset to xu_slowspr_val_offset), + scout => sov(xu_slowspr_val_offset to xu_slowspr_val_offset), + din(0) => xu_slowspr_val_d, + dout(0) => slowspr_val_out ); + + +latch_xu_slowspr_rw : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => bx_slowspr_val_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(xu_slowspr_rw_offset to xu_slowspr_rw_offset), + scout => sov(xu_slowspr_rw_offset to xu_slowspr_rw_offset), + din(0) => xu_slowspr_rw_d, + dout(0) => slowspr_rw_out ); + +latch_xu_slowspr_etid : tri_rlmreg_p + generic map (width => xu_slowspr_etid_d'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => bx_slowspr_val_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(xu_slowspr_etid_offset to xu_slowspr_etid_offset + xu_slowspr_etid_d'length-1), + scout => sov(xu_slowspr_etid_offset to xu_slowspr_etid_offset + xu_slowspr_etid_d'length-1), + din => xu_slowspr_etid_d, + dout => slowspr_etid_out ); + +latch_xu_slowspr_addr : tri_rlmreg_p + generic map (width => xu_slowspr_addr_d'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => bx_slowspr_val_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(xu_slowspr_addr_offset to xu_slowspr_addr_offset + xu_slowspr_addr_d'length-1), + scout => sov(xu_slowspr_addr_offset to xu_slowspr_addr_offset + xu_slowspr_addr_d'length-1), + din => xu_slowspr_addr_d, + dout => slowspr_addr_out ); + +latch_xu_slowspr_data : tri_rlmreg_p + generic map (width => xu_slowspr_data_d'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => bx_slowspr_val_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(xu_slowspr_data_offset to xu_slowspr_data_offset + xu_slowspr_data_d'length-1), + scout => sov(xu_slowspr_data_offset to xu_slowspr_data_offset + xu_slowspr_data_d'length-1), + din => xu_slowspr_data_d, + dout => slowspr_data_out ); + +latch_xu_slowspr_done : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => bx_slowspr_val_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(xu_slowspr_done_offset to xu_slowspr_done_offset), + scout => sov(xu_slowspr_done_offset to xu_slowspr_done_offset), + din(0) => xu_slowspr_done_d, + dout(0) => slowspr_done_out ); + +latch_ditc_addr_t0 : tri_rlmreg_p + generic map (width => ditc_addr_t0_d'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ditc_addr_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ditc_addr_t0_offset to ditc_addr_t0_offset + ditc_addr_t0_d'length-1), + scout => sov(ditc_addr_t0_offset to ditc_addr_t0_offset + ditc_addr_t0_d'length-1), + din => ditc_addr_t0_d, + dout => ditc_addr_t0_q ); + +latch_ditc_addr_t1 : tri_rlmreg_p + generic map (width => ditc_addr_t1_d'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ditc_addr_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ditc_addr_t1_offset to ditc_addr_t1_offset + ditc_addr_t1_d'length-1), + scout => sov(ditc_addr_t1_offset to ditc_addr_t1_offset + ditc_addr_t1_d'length-1), + din => ditc_addr_t1_d, + dout => ditc_addr_t1_q ); + +latch_ditc_addr_t2 : tri_rlmreg_p + generic map (width => ditc_addr_t2_d'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ditc_addr_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ditc_addr_t2_offset to ditc_addr_t2_offset + ditc_addr_t2_d'length-1), + scout => sov(ditc_addr_t2_offset to ditc_addr_t2_offset + ditc_addr_t2_d'length-1), + din => ditc_addr_t2_d, + dout => ditc_addr_t2_q ); + +latch_ditc_addr_t3 : tri_rlmreg_p + generic map (width => ditc_addr_t3_d'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ditc_addr_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ditc_addr_t3_offset to ditc_addr_t3_offset + ditc_addr_t3_d'length-1), + scout => sov(ditc_addr_t3_offset to ditc_addr_t3_offset + ditc_addr_t3_d'length-1), + din => ditc_addr_t3_d, + dout => ditc_addr_t3_q ); + +-- ******************************************************************************************** +-- +-- OUTBOX +-- +-- ******************************************************************************************** + +ex4_mtdp_val_gated <= ex4_mtdp_val_q and not my_ex4_stg_flush; + + +--********************************************************************************************** +-- increment outbox buffer write pointer when message buffer complete reg is written valid +-- there is one buffer pointer per thread +--********************************************************************************************** + +ob0_wrt_entry_ptr_d <= std_ulogic_vector(unsigned(ob0_wrt_entry_ptr_q) + 1) when ob0_set_val='1' else + std_ulogic_vector(unsigned(ob0_wrt_entry_ptr_q) - 1) when (ex5_ob0_flushed xor ex6_ob0_flushed)='1' else + std_ulogic_vector(unsigned(ob0_wrt_entry_ptr_q) - 2) when (ex5_ob0_flushed and ex6_ob0_flushed)='1' else + ob0_wrt_entry_ptr_q(0 to 1); + +ob1_wrt_entry_ptr_d <= std_ulogic_vector(unsigned(ob1_wrt_entry_ptr_q) + 1) when ob1_set_val='1' else + std_ulogic_vector(unsigned(ob1_wrt_entry_ptr_q) - 1) when (ex5_ob1_flushed xor ex6_ob1_flushed)='1' else + std_ulogic_vector(unsigned(ob1_wrt_entry_ptr_q) - 2) when (ex5_ob1_flushed and ex6_ob1_flushed)='1' else + ob1_wrt_entry_ptr_q(0 to 1); + +ob2_wrt_entry_ptr_d <= std_ulogic_vector(unsigned(ob2_wrt_entry_ptr_q) + 1) when ob2_set_val='1' else + std_ulogic_vector(unsigned(ob2_wrt_entry_ptr_q) - 1) when (ex5_ob2_flushed xor ex6_ob2_flushed)='1' else + std_ulogic_vector(unsigned(ob2_wrt_entry_ptr_q) - 2) when (ex5_ob2_flushed and ex6_ob2_flushed)='1' else + ob2_wrt_entry_ptr_q(0 to 1); + +ob3_wrt_entry_ptr_d <= std_ulogic_vector(unsigned(ob3_wrt_entry_ptr_q) + 1) when ob3_set_val='1' else + std_ulogic_vector(unsigned(ob3_wrt_entry_ptr_q) - 1) when (ex5_ob3_flushed xor ex6_ob3_flushed)='1' else + std_ulogic_vector(unsigned(ob3_wrt_entry_ptr_q) - 2) when (ex5_ob3_flushed and ex6_ob3_flushed)='1' else + ob3_wrt_entry_ptr_q(0 to 1); + +--********************************************************************************************************** +-- Dealing with flushed ops: +-- +-- In order to deal with flushed ops up until ex5, these pointers will be pipeline staged until ex5. +-- If the op is flushed in ex5, the new pointer will be loaded from the staged ex5 pointer. +-- An additional bit for each message buffer complete reg will get set in ex5 if the op is not flushed. +-- Before the buffer is eligible to be sent to node, both the valid and committed bits must be set (could +-- probably just look at the committed bit which will not be set unless the valid is on). If the +-- committed bit is not set in ex5 because of a flush, then the messge buffer complete reg should be +-- cleared. +-- Probably have to stage the thread ID until ex5 too so that I know which buffer to use in ex5. +--********************************************************************************************************** + + +latch_ob0_wrt_entry_ptr : tri_rlmreg_p + generic map (width => ob0_wrt_entry_ptr_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => mtdp_ex3_to_7_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob0_wrt_entry_ptr_offset to ob0_wrt_entry_ptr_offset + ob0_wrt_entry_ptr_q'length-1), + scout => sov(ob0_wrt_entry_ptr_offset to ob0_wrt_entry_ptr_offset + ob0_wrt_entry_ptr_q'length-1), + din => ob0_wrt_entry_ptr_d(0 to 1), + dout => ob0_wrt_entry_ptr_q(0 to 1) ); + +latch_ob1_wrt_entry_ptr : tri_rlmreg_p + generic map (width => ob1_wrt_entry_ptr_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => mtdp_ex3_to_7_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob1_wrt_entry_ptr_offset to ob1_wrt_entry_ptr_offset + ob1_wrt_entry_ptr_q'length-1), + scout => sov(ob1_wrt_entry_ptr_offset to ob1_wrt_entry_ptr_offset + ob1_wrt_entry_ptr_q'length-1), + din => ob1_wrt_entry_ptr_d(0 to 1), + dout => ob1_wrt_entry_ptr_q(0 to 1) ); + +latch_ob2_wrt_entry_ptr : tri_rlmreg_p + generic map (width => ob2_wrt_entry_ptr_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => mtdp_ex3_to_7_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob2_wrt_entry_ptr_offset to ob2_wrt_entry_ptr_offset + ob2_wrt_entry_ptr_q'length-1), + scout => sov(ob2_wrt_entry_ptr_offset to ob2_wrt_entry_ptr_offset + ob2_wrt_entry_ptr_q'length-1), + din => ob2_wrt_entry_ptr_d(0 to 1), + dout => ob2_wrt_entry_ptr_q(0 to 1) ); + +latch_ob3_wrt_entry_ptr : tri_rlmreg_p + generic map (width => ob3_wrt_entry_ptr_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => mtdp_ex3_to_7_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob3_wrt_entry_ptr_offset to ob3_wrt_entry_ptr_offset + ob3_wrt_entry_ptr_q'length-1), + scout => sov(ob3_wrt_entry_ptr_offset to ob3_wrt_entry_ptr_offset + ob3_wrt_entry_ptr_q'length-1), + din => ob3_wrt_entry_ptr_d(0 to 1), + dout => ob3_wrt_entry_ptr_q(0 to 1) ); + +--**************************************************************************** +-- write to the data port message buffer complete register when BA = 10001 +-- since ba(3:4)=01 the rotator will put the data on word 1 +--**************************************************************************** + +ob_status_reg_newdata(0 to 17) <= xu_bx_ex4_256st_data(32) & -- valid bit + xu_bx_ex4_256st_data(33 to 34) & -- length + xu_bx_ex4_256st_data(49 to 55) & -- dest node + xu_bx_ex4_256st_data(56 to 63); -- dest thread + +wrt_ob0_buf0_status <= not ob0_buf0_status_avail and ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "00") and (ex4_ipc_ba_q = "10001") and (ob0_wrt_entry_ptr_q = "00"); +wrt_ob0_buf1_status <= not ob0_buf1_status_avail and ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "00") and (ex4_ipc_ba_q = "10001") and (ob0_wrt_entry_ptr_q = "01"); +wrt_ob0_buf2_status <= not ob0_buf2_status_avail and ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "00") and (ex4_ipc_ba_q = "10001") and (ob0_wrt_entry_ptr_q = "10"); +wrt_ob0_buf3_status <= not ob0_buf3_status_avail and ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "00") and (ex4_ipc_ba_q = "10001") and (ob0_wrt_entry_ptr_q = "11"); +wrt_ob1_buf0_status <= not ob1_buf0_status_avail and ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "01") and (ex4_ipc_ba_q = "10001") and (ob1_wrt_entry_ptr_q = "00"); +wrt_ob1_buf1_status <= not ob1_buf1_status_avail and ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "01") and (ex4_ipc_ba_q = "10001") and (ob1_wrt_entry_ptr_q = "01"); +wrt_ob1_buf2_status <= not ob1_buf2_status_avail and ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "01") and (ex4_ipc_ba_q = "10001") and (ob1_wrt_entry_ptr_q = "10"); +wrt_ob1_buf3_status <= not ob1_buf3_status_avail and ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "01") and (ex4_ipc_ba_q = "10001") and (ob1_wrt_entry_ptr_q = "11"); +wrt_ob2_buf0_status <= not ob2_buf0_status_avail and ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "10") and (ex4_ipc_ba_q = "10001") and (ob2_wrt_entry_ptr_q = "00"); +wrt_ob2_buf1_status <= not ob2_buf1_status_avail and ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "10") and (ex4_ipc_ba_q = "10001") and (ob2_wrt_entry_ptr_q = "01"); +wrt_ob2_buf2_status <= not ob2_buf2_status_avail and ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "10") and (ex4_ipc_ba_q = "10001") and (ob2_wrt_entry_ptr_q = "10"); +wrt_ob2_buf3_status <= not ob2_buf3_status_avail and ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "10") and (ex4_ipc_ba_q = "10001") and (ob2_wrt_entry_ptr_q = "11"); +wrt_ob3_buf0_status <= not ob3_buf0_status_avail and ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "11") and (ex4_ipc_ba_q = "10001") and (ob3_wrt_entry_ptr_q = "00"); +wrt_ob3_buf1_status <= not ob3_buf1_status_avail and ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "11") and (ex4_ipc_ba_q = "10001") and (ob3_wrt_entry_ptr_q = "01"); +wrt_ob3_buf2_status <= not ob3_buf2_status_avail and ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "11") and (ex4_ipc_ba_q = "10001") and (ob3_wrt_entry_ptr_q = "10"); +wrt_ob3_buf3_status <= not ob3_buf3_status_avail and ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "11") and (ex4_ipc_ba_q = "10001") and (ob3_wrt_entry_ptr_q = "11"); + +ob0_set_val <= wrt_ob0_buf0_status or wrt_ob0_buf1_status or wrt_ob0_buf2_status or wrt_ob0_buf3_status; +ob1_set_val <= wrt_ob1_buf0_status or wrt_ob1_buf1_status or wrt_ob1_buf2_status or wrt_ob1_buf3_status; +ob2_set_val <= wrt_ob2_buf0_status or wrt_ob2_buf1_status or wrt_ob2_buf2_status or wrt_ob2_buf3_status; +ob3_set_val <= wrt_ob3_buf0_status or wrt_ob3_buf1_status or wrt_ob3_buf2_status or wrt_ob3_buf3_status; + +-- remember which status reg written last cycle + +ex4_wrt_ob_status(0 to 15) <= wrt_ob0_buf0_status & wrt_ob0_buf1_status & wrt_ob0_buf2_status & wrt_ob0_buf3_status & + wrt_ob1_buf0_status & wrt_ob1_buf1_status & wrt_ob1_buf2_status & wrt_ob1_buf3_status & + wrt_ob2_buf0_status & wrt_ob2_buf1_status & wrt_ob2_buf2_status & wrt_ob2_buf3_status & + wrt_ob3_buf0_status & wrt_ob3_buf1_status & wrt_ob3_buf2_status & wrt_ob3_buf3_status; + +ob_rd_logic_act_d <= ex4_mtdp_val_q or + ob0_buf0_status_q(0) or ob0_buf1_status_q(0) or ob0_buf2_status_q(0) or ob0_buf3_status_q(0) or + ob1_buf0_status_q(0) or ob1_buf1_status_q(0) or ob1_buf2_status_q(0) or ob1_buf3_status_q(0) or + ob2_buf0_status_q(0) or ob2_buf1_status_q(0) or ob2_buf2_status_q(0) or ob2_buf3_status_q(0) or + ob3_buf0_status_q(0) or ob3_buf1_status_q(0) or ob3_buf2_status_q(0) or ob3_buf3_status_q(0); + +latch_ob_rd_logic_act : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_rd_logic_act_offset to ob_rd_logic_act_offset), + scout => sov(ob_rd_logic_act_offset to ob_rd_logic_act_offset), + din(0) => ob_rd_logic_act_d, + dout(0) => ob_rd_logic_act_q ); + +ob_rd_logic_act <= ob_rd_logic_act_q or ex4_mtdp_val_q or ex5_mtdp_val_q or ex6_mtdp_val_q; + +latch_ex5_wrt_ob_status : tri_rlmreg_p + generic map (width => ex5_wrt_ob_status_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex5_wrt_ob_status_offset to ex5_wrt_ob_status_offset + ex5_wrt_ob_status_q'length-1), + scout => sov(ex5_wrt_ob_status_offset to ex5_wrt_ob_status_offset + ex5_wrt_ob_status_q'length-1), + din => ex4_wrt_ob_status(0 to 15), + dout => ex5_wrt_ob_status_q(0 to 15) ); + +ex5_wrt_ob_status_gated(0 to 15) <= gate_and(not my_ex5_stg_flush, ex5_wrt_ob_status_q(0 to 15)); + +latch_ex6_wrt_ob_status : tri_rlmreg_p + generic map (width => ex6_wrt_ob_status_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex6_wrt_ob_status_offset to ex6_wrt_ob_status_offset + ex6_wrt_ob_status_q'length-1), + scout => sov(ex6_wrt_ob_status_offset to ex6_wrt_ob_status_offset + ex6_wrt_ob_status_q'length-1), + din => ex5_wrt_ob_status_gated(0 to 15), + dout => ex6_wrt_ob_status_q(0 to 15) ); + +ex5_ob0_buf0_flushed <= ex5_wrt_ob_status_q(0) and my_ex5_stg_flush; +ex5_ob0_buf1_flushed <= ex5_wrt_ob_status_q(1) and my_ex5_stg_flush; +ex5_ob0_buf2_flushed <= ex5_wrt_ob_status_q(2) and my_ex5_stg_flush; +ex5_ob0_buf3_flushed <= ex5_wrt_ob_status_q(3) and my_ex5_stg_flush; +ex5_ob1_buf0_flushed <= ex5_wrt_ob_status_q(4) and my_ex5_stg_flush; +ex5_ob1_buf1_flushed <= ex5_wrt_ob_status_q(5) and my_ex5_stg_flush; +ex5_ob1_buf2_flushed <= ex5_wrt_ob_status_q(6) and my_ex5_stg_flush; +ex5_ob1_buf3_flushed <= ex5_wrt_ob_status_q(7) and my_ex5_stg_flush; +ex5_ob2_buf0_flushed <= ex5_wrt_ob_status_q(8) and my_ex5_stg_flush; +ex5_ob2_buf1_flushed <= ex5_wrt_ob_status_q(9) and my_ex5_stg_flush; +ex5_ob2_buf2_flushed <= ex5_wrt_ob_status_q(10) and my_ex5_stg_flush; +ex5_ob2_buf3_flushed <= ex5_wrt_ob_status_q(11) and my_ex5_stg_flush; +ex5_ob3_buf0_flushed <= ex5_wrt_ob_status_q(12) and my_ex5_stg_flush; +ex5_ob3_buf1_flushed <= ex5_wrt_ob_status_q(13) and my_ex5_stg_flush; +ex5_ob3_buf2_flushed <= ex5_wrt_ob_status_q(14) and my_ex5_stg_flush; +ex5_ob3_buf3_flushed <= ex5_wrt_ob_status_q(15) and my_ex5_stg_flush; + +ex5_ob0_flushed <= ex5_ob0_buf0_flushed or ex5_ob0_buf1_flushed or ex5_ob0_buf2_flushed or ex5_ob0_buf3_flushed; +ex5_ob1_flushed <= ex5_ob1_buf0_flushed or ex5_ob1_buf1_flushed or ex5_ob1_buf2_flushed or ex5_ob1_buf3_flushed; +ex5_ob2_flushed <= ex5_ob2_buf0_flushed or ex5_ob2_buf1_flushed or ex5_ob2_buf2_flushed or ex5_ob2_buf3_flushed; +ex5_ob3_flushed <= ex5_ob3_buf0_flushed or ex5_ob3_buf1_flushed or ex5_ob3_buf2_flushed or ex5_ob3_buf3_flushed; + +ex6_ob0_buf0_flushed <= ex6_wrt_ob_status_q(0) and my_ex6_stg_flush; +ex6_ob0_buf1_flushed <= ex6_wrt_ob_status_q(1) and my_ex6_stg_flush; +ex6_ob0_buf2_flushed <= ex6_wrt_ob_status_q(2) and my_ex6_stg_flush; +ex6_ob0_buf3_flushed <= ex6_wrt_ob_status_q(3) and my_ex6_stg_flush; +ex6_ob1_buf0_flushed <= ex6_wrt_ob_status_q(4) and my_ex6_stg_flush; +ex6_ob1_buf1_flushed <= ex6_wrt_ob_status_q(5) and my_ex6_stg_flush; +ex6_ob1_buf2_flushed <= ex6_wrt_ob_status_q(6) and my_ex6_stg_flush; +ex6_ob1_buf3_flushed <= ex6_wrt_ob_status_q(7) and my_ex6_stg_flush; +ex6_ob2_buf0_flushed <= ex6_wrt_ob_status_q(8) and my_ex6_stg_flush; +ex6_ob2_buf1_flushed <= ex6_wrt_ob_status_q(9) and my_ex6_stg_flush; +ex6_ob2_buf2_flushed <= ex6_wrt_ob_status_q(10) and my_ex6_stg_flush; +ex6_ob2_buf3_flushed <= ex6_wrt_ob_status_q(11) and my_ex6_stg_flush; +ex6_ob3_buf0_flushed <= ex6_wrt_ob_status_q(12) and my_ex6_stg_flush; +ex6_ob3_buf1_flushed <= ex6_wrt_ob_status_q(13) and my_ex6_stg_flush; +ex6_ob3_buf2_flushed <= ex6_wrt_ob_status_q(14) and my_ex6_stg_flush; +ex6_ob3_buf3_flushed <= ex6_wrt_ob_status_q(15) and my_ex6_stg_flush; + +ex6_ob0_flushed <= ex6_ob0_buf0_flushed or ex6_ob0_buf1_flushed or ex6_ob0_buf2_flushed or ex6_ob0_buf3_flushed; +ex6_ob1_flushed <= ex6_ob1_buf0_flushed or ex6_ob1_buf1_flushed or ex6_ob1_buf2_flushed or ex6_ob1_buf3_flushed; +ex6_ob2_flushed <= ex6_ob2_buf0_flushed or ex6_ob2_buf1_flushed or ex6_ob2_buf2_flushed or ex6_ob2_buf3_flushed; +ex6_ob3_flushed <= ex6_ob3_buf0_flushed or ex6_ob3_buf1_flushed or ex6_ob3_buf2_flushed or ex6_ob3_buf3_flushed; + +ob0_buf0_clr <= ob0_buf0_done or ex5_ob0_buf0_flushed or ex6_ob0_buf0_flushed; + +ob0_buf0_status_avail <= ob0_buf0_status_q(0) and not ex5_ob0_buf0_flushed and not ex6_ob0_buf0_flushed; + +ob0_buf0_status_d(0 to 17) <= ob_status_reg_newdata(0 to 17) when wrt_ob0_buf0_status='1' else + (others => '0') when ob0_buf0_clr='1' else + ob0_buf0_status_q(0 to 17); + +ob0_buf1_clr <= ob0_buf1_done or ex5_ob0_buf1_flushed or ex6_ob0_buf1_flushed; + +ob0_buf1_status_avail <= ob0_buf1_status_q(0) and not ex5_ob0_buf1_flushed and not ex6_ob0_buf1_flushed; + +ob0_buf1_status_d(0 to 17) <= ob_status_reg_newdata(0 to 17) when wrt_ob0_buf1_status='1' else + (others => '0') when ob0_buf1_clr='1' else + ob0_buf1_status_q(0 to 17); + +ob0_buf2_clr <= ob0_buf2_done or ex5_ob0_buf2_flushed or ex6_ob0_buf2_flushed; + +ob0_buf2_status_avail <= ob0_buf2_status_q(0) and not ex5_ob0_buf2_flushed and not ex6_ob0_buf2_flushed; + +ob0_buf2_status_d(0 to 17) <= ob_status_reg_newdata(0 to 17) when wrt_ob0_buf2_status='1' else + (others => '0') when ob0_buf2_clr='1' else + ob0_buf2_status_q(0 to 17); + +ob0_buf3_clr <= ob0_buf3_done or ex5_ob0_buf3_flushed or ex6_ob0_buf3_flushed; + +ob0_buf3_status_avail <= ob0_buf3_status_q(0) and not ex5_ob0_buf3_flushed and not ex6_ob0_buf3_flushed; + +ob0_buf3_status_d(0 to 17) <= ob_status_reg_newdata(0 to 17) when wrt_ob0_buf3_status='1' else + (others => '0') when ob0_buf3_clr='1' else + ob0_buf3_status_q(0 to 17); + +ob1_buf0_clr <= ob1_buf0_done or ex5_ob1_buf0_flushed or ex6_ob1_buf0_flushed; + +ob1_buf0_status_avail <= ob1_buf0_status_q(0) and not ex5_ob1_buf0_flushed and not ex6_ob1_buf0_flushed; + +ob1_buf0_status_d(0 to 17) <= ob_status_reg_newdata(0 to 17) when wrt_ob1_buf0_status='1' else + (others => '0') when ob1_buf0_clr='1' else + ob1_buf0_status_q(0 to 17); + +ob1_buf1_clr <= ob1_buf1_done or ex5_ob1_buf1_flushed or ex6_ob1_buf1_flushed; + +ob1_buf1_status_avail <= ob1_buf1_status_q(0) and not ex5_ob1_buf1_flushed and not ex6_ob1_buf1_flushed; + +ob1_buf1_status_d(0 to 17) <= ob_status_reg_newdata(0 to 17) when wrt_ob1_buf1_status='1' else + (others => '0') when ob1_buf1_clr='1' else + ob1_buf1_status_q(0 to 17); + +ob1_buf2_clr <= ob1_buf2_done or ex5_ob1_buf2_flushed or ex6_ob1_buf2_flushed; + +ob1_buf2_status_avail <= ob1_buf2_status_q(0) and not ex5_ob1_buf2_flushed and not ex6_ob1_buf2_flushed; + +ob1_buf2_status_d(0 to 17) <= ob_status_reg_newdata(0 to 17) when wrt_ob1_buf2_status='1' else + (others => '0') when ob1_buf2_clr='1' else + ob1_buf2_status_q(0 to 17); + +ob1_buf3_clr <= ob1_buf3_done or ex5_ob1_buf3_flushed or ex6_ob1_buf3_flushed; + +ob1_buf3_status_avail <= ob1_buf3_status_q(0) and not ex5_ob1_buf3_flushed and not ex6_ob1_buf3_flushed; + +ob1_buf3_status_d(0 to 17) <= ob_status_reg_newdata(0 to 17) when wrt_ob1_buf3_status='1' else + (others => '0') when ob1_buf3_clr='1' else + ob1_buf3_status_q(0 to 17); + +ob2_buf0_clr <= ob2_buf0_done or ex5_ob2_buf0_flushed or ex6_ob2_buf0_flushed; + +ob2_buf0_status_avail <= ob2_buf0_status_q(0) and not ex5_ob2_buf0_flushed and not ex6_ob2_buf0_flushed; + +ob2_buf0_status_d(0 to 17) <= ob_status_reg_newdata(0 to 17) when wrt_ob2_buf0_status='1' else + (others => '0') when ob2_buf0_clr='1' else + ob2_buf0_status_q(0 to 17); + +ob2_buf1_clr <= ob2_buf1_done or ex5_ob2_buf1_flushed or ex6_ob2_buf1_flushed; + +ob2_buf1_status_avail <= ob2_buf1_status_q(0) and not ex5_ob2_buf1_flushed and not ex6_ob2_buf1_flushed; + +ob2_buf1_status_d(0 to 17) <= ob_status_reg_newdata(0 to 17) when wrt_ob2_buf1_status='1' else + (others => '0') when ob2_buf1_clr='1' else + ob2_buf1_status_q(0 to 17); + +ob2_buf2_clr <= ob2_buf2_done or ex5_ob2_buf2_flushed or ex6_ob2_buf2_flushed; + +ob2_buf2_status_avail <= ob2_buf2_status_q(0) and not ex5_ob2_buf2_flushed and not ex6_ob2_buf2_flushed; + +ob2_buf2_status_d(0 to 17) <= ob_status_reg_newdata(0 to 17) when wrt_ob2_buf2_status='1' else + (others => '0') when ob2_buf2_clr='1' else + ob2_buf2_status_q(0 to 17); + +ob2_buf3_clr <= ob2_buf3_done or ex5_ob2_buf3_flushed or ex6_ob2_buf3_flushed; + +ob2_buf3_status_avail <= ob2_buf3_status_q(0) and not ex5_ob2_buf3_flushed and not ex6_ob2_buf3_flushed; + +ob2_buf3_status_d(0 to 17) <= ob_status_reg_newdata(0 to 17) when wrt_ob2_buf3_status='1' else + (others => '0') when ob2_buf3_clr='1' else + ob2_buf3_status_q(0 to 17); + +ob3_buf0_clr <= ob3_buf0_done or ex5_ob3_buf0_flushed or ex6_ob3_buf0_flushed; + +ob3_buf0_status_avail <= ob3_buf0_status_q(0) and not ex5_ob3_buf0_flushed and not ex6_ob3_buf0_flushed; + +ob3_buf0_status_d(0 to 17) <= ob_status_reg_newdata(0 to 17) when wrt_ob3_buf0_status='1' else + (others => '0') when ob3_buf0_clr='1' else + ob3_buf0_status_q(0 to 17); + +ob3_buf1_clr <= ob3_buf1_done or ex5_ob3_buf1_flushed or ex6_ob3_buf1_flushed; + +ob3_buf1_status_avail <= ob3_buf1_status_q(0) and not ex5_ob3_buf1_flushed and not ex6_ob3_buf1_flushed; + +ob3_buf1_status_d(0 to 17) <= ob_status_reg_newdata(0 to 17) when wrt_ob3_buf1_status='1' else + (others => '0') when ob3_buf1_clr='1' else + ob3_buf1_status_q(0 to 17); + +ob3_buf2_clr <= ob3_buf2_done or ex5_ob3_buf2_flushed or ex6_ob3_buf2_flushed; + +ob3_buf2_status_avail <= ob3_buf2_status_q(0) and not ex5_ob3_buf2_flushed and not ex6_ob3_buf2_flushed; + +ob3_buf2_status_d(0 to 17) <= ob_status_reg_newdata(0 to 17) when wrt_ob3_buf2_status='1' else + (others => '0') when ob3_buf2_clr='1' else + ob3_buf2_status_q(0 to 17); + +ob3_buf3_clr <= ob3_buf3_done or ex5_ob3_buf3_flushed or ex6_ob3_buf3_flushed; + +ob3_buf3_status_avail <= ob3_buf3_status_q(0) and not ex5_ob3_buf3_flushed and not ex6_ob3_buf3_flushed; + +ob3_buf3_status_d(0 to 17) <= ob_status_reg_newdata(0 to 17) when wrt_ob3_buf3_status='1' else + (others => '0') when ob3_buf3_clr='1' else + ob3_buf3_status_q(0 to 17); + +latch_ob0_buf0_status : tri_rlmreg_p + generic map (width => ob0_buf0_status_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob0_buf0_status_offset to ob0_buf0_status_offset + ob0_buf0_status_q'length-1), + scout => sov(ob0_buf0_status_offset to ob0_buf0_status_offset + ob0_buf0_status_q'length-1), + din => ob0_buf0_status_d, + dout => ob0_buf0_status_q ); + + +latch_ob0_buf1_status : tri_rlmreg_p + generic map (width => ob0_buf1_status_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob0_buf1_status_offset to ob0_buf1_status_offset + ob0_buf1_status_q'length-1), + scout => sov(ob0_buf1_status_offset to ob0_buf1_status_offset + ob0_buf1_status_q'length-1), + din => ob0_buf1_status_d, + dout => ob0_buf1_status_q ); + +latch_ob0_buf2_status : tri_rlmreg_p + generic map (width => ob0_buf2_status_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob0_buf2_status_offset to ob0_buf2_status_offset + ob0_buf2_status_q'length-1), + scout => sov(ob0_buf2_status_offset to ob0_buf2_status_offset + ob0_buf2_status_q'length-1), + din => ob0_buf2_status_d, + dout => ob0_buf2_status_q ); + +latch_ob0_buf3_status : tri_rlmreg_p + generic map (width => ob0_buf3_status_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob0_buf3_status_offset to ob0_buf3_status_offset + ob0_buf3_status_q'length-1), + scout => sov(ob0_buf3_status_offset to ob0_buf3_status_offset + ob0_buf3_status_q'length-1), + din => ob0_buf3_status_d, + dout => ob0_buf3_status_q ); + +latch_ob1_buf0_status : tri_rlmreg_p + generic map (width => ob1_buf0_status_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob1_buf0_status_offset to ob1_buf0_status_offset + ob1_buf0_status_q'length-1), + scout => sov(ob1_buf0_status_offset to ob1_buf0_status_offset + ob1_buf0_status_q'length-1), + din => ob1_buf0_status_d, + dout => ob1_buf0_status_q ); + + +latch_ob1_buf1_status : tri_rlmreg_p + generic map (width => ob1_buf1_status_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob1_buf1_status_offset to ob1_buf1_status_offset + ob1_buf1_status_q'length-1), + scout => sov(ob1_buf1_status_offset to ob1_buf1_status_offset + ob1_buf1_status_q'length-1), + din => ob1_buf1_status_d, + dout => ob1_buf1_status_q ); + +latch_ob1_buf2_status : tri_rlmreg_p + generic map (width => ob1_buf2_status_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob1_buf2_status_offset to ob1_buf2_status_offset + ob1_buf2_status_q'length-1), + scout => sov(ob1_buf2_status_offset to ob1_buf2_status_offset + ob1_buf2_status_q'length-1), + din => ob1_buf2_status_d, + dout => ob1_buf2_status_q ); + +latch_ob1_buf3_status : tri_rlmreg_p + generic map (width => ob1_buf3_status_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob1_buf3_status_offset to ob1_buf3_status_offset + ob1_buf3_status_q'length-1), + scout => sov(ob1_buf3_status_offset to ob1_buf3_status_offset + ob1_buf3_status_q'length-1), + din => ob1_buf3_status_d, + dout => ob1_buf3_status_q ); + +latch_ob2_buf0_status : tri_rlmreg_p + generic map (width => ob2_buf0_status_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob2_buf0_status_offset to ob2_buf0_status_offset + ob2_buf0_status_q'length-1), + scout => sov(ob2_buf0_status_offset to ob2_buf0_status_offset + ob2_buf0_status_q'length-1), + din => ob2_buf0_status_d, + dout => ob2_buf0_status_q ); + + +latch_ob2_buf1_status : tri_rlmreg_p + generic map (width => ob2_buf1_status_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob2_buf1_status_offset to ob2_buf1_status_offset + ob2_buf1_status_q'length-1), + scout => sov(ob2_buf1_status_offset to ob2_buf1_status_offset + ob2_buf1_status_q'length-1), + din => ob2_buf1_status_d, + dout => ob2_buf1_status_q ); + +latch_ob2_buf2_status : tri_rlmreg_p + generic map (width => ob2_buf2_status_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob2_buf2_status_offset to ob2_buf2_status_offset + ob2_buf2_status_q'length-1), + scout => sov(ob2_buf2_status_offset to ob2_buf2_status_offset + ob2_buf2_status_q'length-1), + din => ob2_buf2_status_d, + dout => ob2_buf2_status_q ); + +latch_ob2_buf3_status : tri_rlmreg_p + generic map (width => ob2_buf3_status_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob2_buf3_status_offset to ob2_buf3_status_offset + ob2_buf3_status_q'length-1), + scout => sov(ob2_buf3_status_offset to ob2_buf3_status_offset + ob2_buf3_status_q'length-1), + din => ob2_buf3_status_d, + dout => ob2_buf3_status_q ); + +latch_ob3_buf0_status : tri_rlmreg_p + generic map (width => ob3_buf0_status_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob3_buf0_status_offset to ob3_buf0_status_offset + ob3_buf0_status_q'length-1), + scout => sov(ob3_buf0_status_offset to ob3_buf0_status_offset + ob3_buf0_status_q'length-1), + din => ob3_buf0_status_d, + dout => ob3_buf0_status_q ); + + +latch_ob3_buf1_status : tri_rlmreg_p + generic map (width => ob3_buf1_status_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob3_buf1_status_offset to ob3_buf1_status_offset + ob3_buf1_status_q'length-1), + scout => sov(ob3_buf1_status_offset to ob3_buf1_status_offset + ob3_buf1_status_q'length-1), + din => ob3_buf1_status_d, + dout => ob3_buf1_status_q ); + +latch_ob3_buf2_status : tri_rlmreg_p + generic map (width => ob3_buf2_status_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob3_buf2_status_offset to ob3_buf2_status_offset + ob3_buf2_status_q'length-1), + scout => sov(ob3_buf2_status_offset to ob3_buf2_status_offset + ob3_buf2_status_q'length-1), + din => ob3_buf2_status_d, + dout => ob3_buf2_status_q ); + +latch_ob3_buf3_status : tri_rlmreg_p + generic map (width => ob3_buf3_status_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob3_buf3_status_offset to ob3_buf3_status_offset + ob3_buf3_status_q'length-1), + scout => sov(ob3_buf3_status_offset to ob3_buf3_status_offset + ob3_buf3_status_q'length-1), + din => ob3_buf3_status_d, + dout => ob3_buf3_status_q ); + +ob_buf_status_avail_d <= ob0_buf0_status_avail & ob0_buf1_status_avail & ob0_buf2_status_avail & ob0_buf3_status_avail & + ob1_buf0_status_avail & ob1_buf1_status_avail & ob1_buf2_status_avail & ob1_buf3_status_avail & + ob2_buf0_status_avail & ob2_buf1_status_avail & ob2_buf2_status_avail & ob2_buf3_status_avail & + ob3_buf0_status_avail & ob3_buf1_status_avail & ob3_buf2_status_avail & ob3_buf3_status_avail; + +latch_ob_buf_status_avail : tri_rlmreg_p + generic map (width => ob_buf_status_avail_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_buf_status_avail_offset to ob_buf_status_avail_offset + ob_buf_status_avail_q'length-1), + scout => sov(ob_buf_status_avail_offset to ob_buf_status_avail_offset + ob_buf_status_avail_q'length-1), + din => ob_buf_status_avail_d, + dout => ob_buf_status_avail_q ); + +ob0_buf0_status_val <= ob_buf_status_avail_q(0) and not ex6_ob0_buf0_flushed; -- buffer ready to go out to node if not flushed +ob0_buf1_status_val <= ob_buf_status_avail_q(1) and not ex6_ob0_buf1_flushed; +ob0_buf2_status_val <= ob_buf_status_avail_q(2) and not ex6_ob0_buf2_flushed; +ob0_buf3_status_val <= ob_buf_status_avail_q(3) and not ex6_ob0_buf3_flushed; +ob1_buf0_status_val <= ob_buf_status_avail_q(4) and not ex6_ob1_buf0_flushed; +ob1_buf1_status_val <= ob_buf_status_avail_q(5) and not ex6_ob1_buf1_flushed; +ob1_buf2_status_val <= ob_buf_status_avail_q(6) and not ex6_ob1_buf2_flushed; +ob1_buf3_status_val <= ob_buf_status_avail_q(7) and not ex6_ob1_buf3_flushed; +ob2_buf0_status_val <= ob_buf_status_avail_q(8) and not ex6_ob2_buf0_flushed; +ob2_buf1_status_val <= ob_buf_status_avail_q(9) and not ex6_ob2_buf1_flushed; +ob2_buf2_status_val <= ob_buf_status_avail_q(10) and not ex6_ob2_buf2_flushed; +ob2_buf3_status_val <= ob_buf_status_avail_q(11) and not ex6_ob2_buf3_flushed; +ob3_buf0_status_val <= ob_buf_status_avail_q(12) and not ex6_ob3_buf0_flushed; +ob3_buf1_status_val <= ob_buf_status_avail_q(13) and not ex6_ob3_buf1_flushed; +ob3_buf2_status_val <= ob_buf_status_avail_q(14) and not ex6_ob3_buf2_flushed; +ob3_buf3_status_val <= ob_buf_status_avail_q(15) and not ex6_ob3_buf3_flushed; + + +--**************************************************************************** +-- outbox array write address +--**************************************************************************** + +with ex4_ipc_thrd_q(0 to 1) select + ob_wrt_entry_ptr(0 to 1) <= ob0_wrt_entry_ptr_q(0 to 1) when "00", + ob1_wrt_entry_ptr_q(0 to 1) when "01", + ob2_wrt_entry_ptr_q(0 to 1) when "10", + ob3_wrt_entry_ptr_q(0 to 1) when others; + +ob_wrt_addr(0 to 5) <= ex4_ipc_thrd_q(0 to 1) & ob_wrt_entry_ptr(0 to 1) & ex4_ipc_ba_q(1 to 2); + +--**************************************************************************** +-- outbox array write enable +--**************************************************************************** +ob_buf_status_val <= (ob0_buf0_status_avail and (ex4_ipc_thrd_q="00") and ob0_wrt_entry_ptr_q="00") or + (ob0_buf1_status_avail and (ex4_ipc_thrd_q="00") and ob0_wrt_entry_ptr_q="01") or + (ob0_buf2_status_avail and (ex4_ipc_thrd_q="00") and ob0_wrt_entry_ptr_q="10") or + (ob0_buf3_status_avail and (ex4_ipc_thrd_q="00") and ob0_wrt_entry_ptr_q="11") or + (ob1_buf0_status_avail and (ex4_ipc_thrd_q="01") and ob1_wrt_entry_ptr_q="00") or + (ob1_buf1_status_avail and (ex4_ipc_thrd_q="01") and ob1_wrt_entry_ptr_q="01") or + (ob1_buf2_status_avail and (ex4_ipc_thrd_q="01") and ob1_wrt_entry_ptr_q="10") or + (ob1_buf3_status_avail and (ex4_ipc_thrd_q="01") and ob1_wrt_entry_ptr_q="11") or + (ob2_buf0_status_avail and (ex4_ipc_thrd_q="10") and ob2_wrt_entry_ptr_q="00") or + (ob2_buf1_status_avail and (ex4_ipc_thrd_q="10") and ob2_wrt_entry_ptr_q="01") or + (ob2_buf2_status_avail and (ex4_ipc_thrd_q="10") and ob2_wrt_entry_ptr_q="10") or + (ob2_buf3_status_avail and (ex4_ipc_thrd_q="10") and ob2_wrt_entry_ptr_q="11") or + (ob3_buf0_status_avail and (ex4_ipc_thrd_q="11") and ob3_wrt_entry_ptr_q="00") or + (ob3_buf1_status_avail and (ex4_ipc_thrd_q="11") and ob3_wrt_entry_ptr_q="01") or + (ob3_buf2_status_avail and (ex4_ipc_thrd_q="11") and ob3_wrt_entry_ptr_q="10") or + (ob3_buf3_status_avail and (ex4_ipc_thrd_q="11") and ob3_wrt_entry_ptr_q="11"); + +ob_wen(0) <= ex4_mtdp_val_gated and not ob_buf_status_val and ex4_ipc_ba_q(0)='0' and + ( (ex4_ipc_ba_q(3 to 4)="00") or (ex4_ipc_sz_q="10") or + (ex4_ipc_ba_q(3 to 4)="11" and ex4_ipc_sz_q="01") ); +ob_wen(1) <= ex4_mtdp_val_gated and not ob_buf_status_val and ex4_ipc_ba_q(0)='0' and + ( (ex4_ipc_ba_q(3 to 4)="01") or (ex4_ipc_sz_q="10") or + (ex4_ipc_ba_q(3 to 4)="00" and ex4_ipc_sz_q="01") ); +ob_wen(2) <= ex4_mtdp_val_gated and not ob_buf_status_val and ex4_ipc_ba_q(0)='0' and + ( (ex4_ipc_ba_q(3 to 4)="10") or (ex4_ipc_sz_q="10") or + (ex4_ipc_ba_q(3 to 4)="01" and ex4_ipc_sz_q="01") ); +ob_wen(3) <= ex4_mtdp_val_gated and not ob_buf_status_val and ex4_ipc_ba_q(0)='0' and + ( (ex4_ipc_ba_q(3 to 4)="11") or (ex4_ipc_sz_q="10") or + (ex4_ipc_ba_q(3 to 4)="10" and ex4_ipc_sz_q="01") ); + + +--**************************************************************************** +-- determine pass/fail CR status of mtdp +--**************************************************************************** + +ex3_ob_buf_status_val <= (ob0_buf0_status_avail and (ex3_ipc_thrd_q="00") and ob0_wrt_entry_ptr_d="00") or + (ob0_buf1_status_avail and (ex3_ipc_thrd_q="00") and ob0_wrt_entry_ptr_d="01") or + (ob0_buf2_status_avail and (ex3_ipc_thrd_q="00") and ob0_wrt_entry_ptr_d="10") or + (ob0_buf3_status_avail and (ex3_ipc_thrd_q="00") and ob0_wrt_entry_ptr_d="11") or + (ob1_buf0_status_avail and (ex3_ipc_thrd_q="01") and ob1_wrt_entry_ptr_d="00") or + (ob1_buf1_status_avail and (ex3_ipc_thrd_q="01") and ob1_wrt_entry_ptr_d="01") or + (ob1_buf2_status_avail and (ex3_ipc_thrd_q="01") and ob1_wrt_entry_ptr_d="10") or + (ob1_buf3_status_avail and (ex3_ipc_thrd_q="01") and ob1_wrt_entry_ptr_d="11") or + (ob2_buf0_status_avail and (ex3_ipc_thrd_q="10") and ob2_wrt_entry_ptr_d="00") or + (ob2_buf1_status_avail and (ex3_ipc_thrd_q="10") and ob2_wrt_entry_ptr_d="01") or + (ob2_buf2_status_avail and (ex3_ipc_thrd_q="10") and ob2_wrt_entry_ptr_d="10") or + (ob2_buf3_status_avail and (ex3_ipc_thrd_q="10") and ob2_wrt_entry_ptr_d="11") or + (ob3_buf0_status_avail and (ex3_ipc_thrd_q="11") and ob3_wrt_entry_ptr_d="00") or + (ob3_buf1_status_avail and (ex3_ipc_thrd_q="11") and ob3_wrt_entry_ptr_d="01") or + (ob3_buf2_status_avail and (ex3_ipc_thrd_q="11") and ob3_wrt_entry_ptr_d="10") or + (ob3_buf3_status_avail and (ex3_ipc_thrd_q="11") and ob3_wrt_entry_ptr_d="11"); + + +ex3_mtdp_cr_status <= ex3_mtdp_val and (not ex3_ob_buf_status_val or (ex3_ipc_ba_q = "10000")); -- 1=mtdp passed, 0=mtdp failed + +latch_ex4_mtdp_cr_status : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => mtdp_ex3_to_7_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_mtdp_cr_status_offset to ex4_mtdp_cr_status_offset), + scout => sov(ex4_mtdp_cr_status_offset to ex4_mtdp_cr_status_offset), + din(0) => ex3_mtdp_cr_status, + dout(0) => ex4_mtdp_cr_status ); + +bx_xu_ex4_mtdp_cr_status <= ex4_mtdp_cr_status; + + +-- latch data for ecc gen before writing array +latch_ob_wrt_data : tri_rlmreg_p + generic map (width => ob_ary_wrt_data_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ex4_mtdp_val_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_wrt_data_offset to ob_wrt_data_offset + ob_ary_wrt_data_l2'length-1), + scout => sov(ob_wrt_data_offset to ob_wrt_data_offset + ob_ary_wrt_data_l2'length-1), + din => xu_bx_ex4_256st_data, + dout => ob_ary_wrt_data_l2 ); + +latch_ob_ary_wen : tri_rlmreg_p + generic map (width => ob_ary_wen_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => mtdp_ex3_to_7_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_ary_wen_offset to ob_ary_wen_offset + ob_ary_wen_l2'length-1), + scout => sov(ob_ary_wen_offset to ob_ary_wen_offset + ob_ary_wen_l2'length-1), + din => ob_wen, + dout => ob_ary_wen_l2 ); + +latch_ob_ary_wrt_addr : tri_rlmreg_p + generic map (width => ob_ary_wrt_addr_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ex4_mtdp_val_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_ary_wrt_addr_offset to ob_ary_wrt_addr_offset + ob_ary_wrt_addr_l2'length-1), + scout => sov(ob_ary_wrt_addr_offset to ob_ary_wrt_addr_offset + ob_ary_wrt_addr_l2'length-1), + din => ob_wrt_addr, + dout => ob_ary_wrt_addr_l2 ); + +-- setting check bits to 1s causes the ecc bits to be inverted which will cause the downstream +-- ecccgen to produce an inverted syn which is what eccchk wants. +ob_di_eccgen0: entity work.xuq_eccgen(xuq_eccgen) + generic map ( regsize => 32 ) + port map(din(0 to 31) => ob_ary_wrt_data_l2(0 to 31), + din(32 to 38) => "1111111", + syn => ob_datain_ecc0 ); + +ob_di_eccgen1: entity work.xuq_eccgen(xuq_eccgen) + generic map ( regsize => 32 ) + port map(din(0 to 31) => ob_ary_wrt_data_l2(32 to 63), + din(32 to 38) => "1111111", + syn => ob_datain_ecc1 ); + +ob_di_eccgen2: entity work.xuq_eccgen(xuq_eccgen) + generic map ( regsize => 32 ) + port map(din(0 to 31) => ob_ary_wrt_data_l2(64 to 95), + din(32 to 38) => "1111111", + syn => ob_datain_ecc2 ); + +ob_di_eccgen3: entity work.xuq_eccgen(xuq_eccgen) + generic map ( regsize => 32 ) + port map(din(0 to 31) => ob_ary_wrt_data_l2(96 to 127), + din(32 to 38) => "1111111", + syn => ob_datain_ecc3 ); + + +--**************************************************************************** +-- outbox error inject +--**************************************************************************** + +latch_ob_err_inj : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_err_inj_offset to ob_err_inj_offset), + scout => sov(ob_err_inj_offset to ob_err_inj_offset), + din(0) => pc_bx_inj_outbox_ecc, + dout(0) => ob_err_inj_q ); + +ob_ary_wrt_data_0 <= ob_ary_wrt_data_l2(0) xor ob_err_inj_q; + +--**************************************************************************** +-- outbox array +--**************************************************************************** + +ob_array: entity tri.tri_64x42_4w_1r1w(tri_64x42_4w_1r1w) + generic map ( expand_type => expand_type ) + port map( +-- functional ports + wr_way => ob_ary_wen_l2(0 to 3), + wr_adr => ob_ary_wrt_addr_l2(0 to 5), + + di(0) => ob_ary_wrt_data_0, + di(1 to 31) => ob_ary_wrt_data_l2(1 to 31), + di(32 to 38) => ob_datain_ecc0(0 to 6), + di(39 to 41) => "000", + + di(42 to 73) => ob_ary_wrt_data_l2(32 to 63), + di(74 to 80) => ob_datain_ecc1(0 to 6), + di(81 to 83) => "000", + + di(84 to 115) => ob_ary_wrt_data_l2(64 to 95), + di(116 to 122) => ob_datain_ecc2(0 to 6), + di(123 to 125) => "000", + + di(126 to 157) => ob_ary_wrt_data_l2(96 to 127), + di(158 to 164) => ob_datain_ecc3(0 to 6), + di(165 to 167) => "000", + + rd0_adr => ob_ary_rd_addr(0 to 5), + + do0(0 to 31) => ob_rd_data(0 to 31), + do0(32 to 38) => ob_rd_data_ecc0(0 to 6), + do0(39 to 41) => unused(0 to 2), + + do0(42 to 73) => ob_rd_data(32 to 63), + do0(74 to 80) => ob_rd_data_ecc1(0 to 6), + do0(81 to 83) => unused(3 to 5), + + do0(84 to 115) => ob_rd_data(64 to 95), + do0(116 to 122) => ob_rd_data_ecc2(0 to 6), + do0(123 to 125) => unused(6 to 8), + + do0(126 to 157) => ob_rd_data(96 to 127), + do0(158 to 164) => ob_rd_data_ecc3(0 to 6), + do0(165 to 167) => unused(9 to 11), + + -- ABIST + abist_di => abist_di_0, + abist_bw_odd => abist_g8t_bw_1, + abist_bw_even => abist_g8t_bw_0, + abist_wr_adr => abist_waddr_0(4 to 9), + wr_abst_act => abist_g8t_wenb, + abist_rd0_adr => abist_raddr_0(4 to 9), + rd0_abst_act => abist_g8t1p_renb_0, + tc_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc, + abist_ena_1 => pc_bx_abist_ena_dc, + abist_g8t_rd0_comp_ena => abist_wl64_comp_ena, + abist_raw_dc_b => pc_bx_abist_raw_dc_b, + obs0_abist_cmp => abist_g8t_dcomp, + + -- BOLT-ON + lcb_bolt_sl_thold_0 => bolt_sl_thold_0, + pc_bo_enable_2 => bolt_enable_2, + pc_bo_reset => pc_bx_bo_reset, + pc_bo_unload => pc_bx_bo_unload, + pc_bo_repair => pc_bx_bo_repair, + pc_bo_shdata => pc_bx_bo_shdata, + pc_bo_select => pc_bx_bo_select(0 to 1), + bo_pc_failout => bx_pc_bo_fail(0 to 1), + bo_pc_diagloop => bx_pc_bo_diagout(0 to 1), + tri_lcb_mpw1_dc_b => mpw1_dc_b, + tri_lcb_mpw2_dc_b => mpw2_dc_b, + tri_lcb_delay_lclkr_dc => delay_lclkr_dc, + tri_lcb_clkoff_dc_b => clkoff_dc_b, + tri_lcb_act_dis_dc => tidn, + +-- pervasive ports + gnd => gnd, + vdd => vdd, + vcs => vcs, + nclk => nclk, + rd0_act => ob_rd_logic_act, + wr_act => ex5_mtdp_val_q, + sg_0 => sg_0, + abst_sl_thold_0 => abst_sl_thold_0, + ary_nsl_thold_0 => ary_nsl_thold_0, + time_sl_thold_0 => time_sl_thold_0, + repr_sl_thold_0 => repr_sl_thold_0, + scan_dis_dc_b => an_ac_scan_dis_dc_b, + scan_diag_dc => an_ac_scan_diag_dc, + ccflush_dc => pc_bx_ccflush_dc, + + ary0_clkoff_dc_b => ary0_clkoff_dc_b, + ary0_d_mode_dc => ary0_d_mode_dc, + ary0_mpw1_dc_b => ary0_mpw1_dc_b_v, + ary0_mpw2_dc_b => ary0_mpw2_dc_b, + ary0_delay_lclkr_dc => ary0_delay_lclkr_dc_v, + + ary1_clkoff_dc_b => ary1_clkoff_dc_b, + ary1_d_mode_dc => ary1_d_mode_dc, + ary1_mpw1_dc_b => ary1_mpw1_dc_b_v, + ary1_mpw2_dc_b => ary1_mpw2_dc_b, + ary1_delay_lclkr_dc => ary1_delay_lclkr_dc_v, + + abst_scan_in => abst_scan_in, + time_scan_in => time_scan_in_q, + repr_scan_in => repr_scan_in_q, + abst_scan_out => ob_abst_scan_out, + time_scan_out => ob_time_scan_out, + repr_scan_out => ob_repr_scan_out +); + + +--**************************************************************************** +-- Latch output of array +--**************************************************************************** + +latch_ob_rd_data1 : tri_rlmreg_p + generic map (width => ob_rd_data1_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_rd_data1_offset to ob_rd_data1_offset + ob_rd_data1_l2'length-1), + scout => sov(ob_rd_data1_offset to ob_rd_data1_offset + ob_rd_data1_l2'length-1), + din => ob_rd_data(0 to 127), + dout => ob_rd_data1_l2 ); + +latch_ob_rd_data_ecc0 : tri_rlmreg_p + generic map (width => ob_rd_data_ecc0'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_rd_data_ecc0_offset to ob_rd_data_ecc0_offset + ob_rd_data_ecc0'length-1), + scout => sov(ob_rd_data_ecc0_offset to ob_rd_data_ecc0_offset + ob_rd_data_ecc0'length-1), + din => ob_rd_data_ecc0(0 to 6), + dout => ob_rd_data_ecc0_l2 ); + +latch_ob_rd_data_ecc1 : tri_rlmreg_p + generic map (width => ob_rd_data_ecc1'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_rd_data_ecc1_offset to ob_rd_data_ecc1_offset + ob_rd_data_ecc1'length-1), + scout => sov(ob_rd_data_ecc1_offset to ob_rd_data_ecc1_offset + ob_rd_data_ecc1'length-1), + din => ob_rd_data_ecc1(0 to 6), + dout => ob_rd_data_ecc1_l2 ); + +latch_ob_rd_data_ecc2 : tri_rlmreg_p + generic map (width => ob_rd_data_ecc2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_rd_data_ecc2_offset to ob_rd_data_ecc2_offset + ob_rd_data_ecc2'length-1), + scout => sov(ob_rd_data_ecc2_offset to ob_rd_data_ecc2_offset + ob_rd_data_ecc2'length-1), + din => ob_rd_data_ecc2(0 to 6), + dout => ob_rd_data_ecc2_l2 ); + +latch_ob_rd_data_ecc3 : tri_rlmreg_p + generic map (width => ob_rd_data_ecc3'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_rd_data_ecc3_offset to ob_rd_data_ecc3_offset + ob_rd_data_ecc3'length-1), + scout => sov(ob_rd_data_ecc3_offset to ob_rd_data_ecc3_offset + ob_rd_data_ecc3'length-1), + din => ob_rd_data_ecc3(0 to 6), + dout => ob_rd_data_ecc3_l2 ); + +--**************************************************************************** +-- Check OB data for ECC error +--**************************************************************************** + + + +ob_do_eccgen0: entity work.xuq_eccgen(xuq_eccgen) + generic map ( regsize => 32 ) + port map(din(0 to 31) => ob_rd_data1_l2(0 to 31), + din(32 to 38) => ob_rd_data_ecc0_l2, + syn => ob_rd_data_nsyn0 ); + +ob_do_eccgen1: entity work.xuq_eccgen(xuq_eccgen) + generic map ( regsize => 32 ) + port map(din(0 to 31) => ob_rd_data1_l2(32 to 63), + din(32 to 38) => ob_rd_data_ecc1_l2, + syn => ob_rd_data_nsyn1 ); + +ob_do_eccgen2: entity work.xuq_eccgen(xuq_eccgen) + generic map ( regsize => 32 ) + port map(din(0 to 31) => ob_rd_data1_l2(64 to 95), + din(32 to 38) => ob_rd_data_ecc2_l2, + syn => ob_rd_data_nsyn2 ); + +ob_do_eccgen3: entity work.xuq_eccgen(xuq_eccgen) + generic map ( regsize => 32 ) + port map(din(0 to 31) => ob_rd_data1_l2(96 to 127), + din(32 to 38) => ob_rd_data_ecc3_l2, + syn => ob_rd_data_nsyn3 ); + +ob_di_eccchk0: entity work.xuq_eccchk(xuq_eccchk) + generic map ( regsize => 32 ) + port map(din => ob_rd_data1_l2(0 to 31), + EnCorr => '1', + NSyn => ob_rd_data_nsyn0, + Corrd => ob_rd_data_cor(0 to 31), + sbe => ob_ary_sbe(0), + ue => ob_ary_ue(0) ); + + +ob_di_eccchk1: entity work.xuq_eccchk(xuq_eccchk) + generic map ( regsize => 32 ) + port map(din => ob_rd_data1_l2(32 to 63), + EnCorr => '1', + NSyn => ob_rd_data_nsyn1, + Corrd => ob_rd_data_cor(32 to 63), + sbe => ob_ary_sbe(1), + ue => ob_ary_ue(1) ); + +ob_di_eccchk2: entity work.xuq_eccchk(xuq_eccchk) + generic map ( regsize => 32 ) + port map(din => ob_rd_data1_l2(64 to 95), + EnCorr => '1', + NSyn => ob_rd_data_nsyn2, + Corrd => ob_rd_data_cor(64 to 95), + sbe => ob_ary_sbe(2), + ue => ob_ary_ue(2) ); + +ob_di_eccchk3: entity work.xuq_eccchk(xuq_eccchk) + generic map ( regsize => 32 ) + port map(din => ob_rd_data1_l2(96 to 127), + EnCorr => '1', + NSyn => ob_rd_data_nsyn3, + Corrd => ob_rd_data_cor(96 to 127), + sbe => ob_ary_sbe(3), + ue => ob_ary_ue(3) ); + +latch_ob_ary_sbe : tri_rlmreg_p + generic map (width => ob_ary_sbe_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_ary_sbe_offset to ob_ary_sbe_offset + ob_ary_sbe_q'length-1), + scout => sov(ob_ary_sbe_offset to ob_ary_sbe_offset + ob_ary_sbe_q'length-1), + din => ob_ary_sbe(0 to 3), + dout => ob_ary_sbe_q(0 to 3) ); + +latch_ob_ary_ue : tri_rlmreg_p + generic map (width => ob_ary_ue_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_ary_ue_offset to ob_ary_ue_offset + ob_ary_ue_q'length-1), + scout => sov(ob_ary_ue_offset to ob_ary_ue_offset + ob_ary_ue_q'length-1), + din => ob_ary_ue(0 to 3), + dout => ob_ary_ue_q(0 to 3) ); + +ob_ary_sbe_or <= (ob_ary_sbe_q(0) or ob_ary_sbe_q(1) or ob_ary_sbe_q(2) or ob_ary_sbe_q(3)) and bx_lsu_ob_req_val_int; + +ob_ary_ue_or <= (ob_ary_ue_q(0) or ob_ary_ue_q(1) or ob_ary_ue_q(2) or ob_ary_ue_q(3)) and bx_lsu_ob_req_val_int; + + + + +latch_ob_rd_data_cor : tri_rlmreg_p + generic map (width => ob_rd_data_cor'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_rd_data_cor_offset to ob_rd_data_cor_offset + ob_rd_data_cor'length-1), + scout => sov(ob_rd_data_cor_offset to ob_rd_data_cor_offset + ob_rd_data_cor'length-1), + din => ob_rd_data_cor(0 to 127), + dout => ob_rd_data_cor_l2 ); + +-- latch parity error and send to pervasive + + +latch_outbox_ecc_err : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(outbox_ecc_err_offset to outbox_ecc_err_offset), + scout => sov(outbox_ecc_err_offset to outbox_ecc_err_offset), + din(0) => ob_ary_sbe_or, + dout(0) => outbox_ecc_err_q ); + +latch_outbox_ue : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(outbox_ue_offset to outbox_ue_offset), + scout => sov(outbox_ue_offset to outbox_ue_offset), + din(0) => ob_ary_ue_or, + dout(0) => outbox_ue_q ); + + outbox_err_rpt : entity tri.tri_direct_err_rpt + generic map + ( width => 2 + , expand_type => expand_type + ) + port map + ( vd => vdd + , gd => gnd + , err_in(0) => outbox_ecc_err_q + , err_in(1) => outbox_ue_q + , err_out(0) => bx_pc_err_outbox_ecc + , err_out(1) => bx_pc_err_outbox_ue + ); + +--**************************************************************************** +-- increment outbox buffer read pointer when message buffer complete reg valid is reset +-- there is one buffer pointer per thread +--**************************************************************************** + +ob0_rd_entry_ptr_d <= std_ulogic_vector(unsigned(ob0_rd_entry_ptr_q) + 1) when ob0_buf_done='1' else + ob0_rd_entry_ptr_q(0 to 1); + +ob1_rd_entry_ptr_d <= std_ulogic_vector(unsigned(ob1_rd_entry_ptr_q) + 1) when ob1_buf_done='1' else + ob1_rd_entry_ptr_q(0 to 1); + +ob2_rd_entry_ptr_d <= std_ulogic_vector(unsigned(ob2_rd_entry_ptr_q) + 1) when ob2_buf_done='1' else + ob2_rd_entry_ptr_q(0 to 1); + +ob3_rd_entry_ptr_d <= std_ulogic_vector(unsigned(ob3_rd_entry_ptr_q) + 1) when ob3_buf_done='1' else + ob3_rd_entry_ptr_q(0 to 1); + +latch_ob0_rd_entry_ptr : tri_rlmreg_p + generic map (width => ob0_rd_entry_ptr_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob0_rd_entry_ptr_offset to ob0_rd_entry_ptr_offset + ob0_rd_entry_ptr_q'length-1), + scout => sov(ob0_rd_entry_ptr_offset to ob0_rd_entry_ptr_offset + ob0_rd_entry_ptr_q'length-1), + din => ob0_rd_entry_ptr_d(0 to 1), + dout => ob0_rd_entry_ptr_q(0 to 1) ); + +latch_ob1_rd_entry_ptr : tri_rlmreg_p + generic map (width => ob1_rd_entry_ptr_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob1_rd_entry_ptr_offset to ob1_rd_entry_ptr_offset + ob1_rd_entry_ptr_q'length-1), + scout => sov(ob1_rd_entry_ptr_offset to ob1_rd_entry_ptr_offset + ob1_rd_entry_ptr_q'length-1), + din => ob1_rd_entry_ptr_d(0 to 1), + dout => ob1_rd_entry_ptr_q(0 to 1) ); + +latch_ob2_rd_entry_ptr : tri_rlmreg_p + generic map (width => ob2_rd_entry_ptr_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob2_rd_entry_ptr_offset to ob2_rd_entry_ptr_offset + ob2_rd_entry_ptr_q'length-1), + scout => sov(ob2_rd_entry_ptr_offset to ob2_rd_entry_ptr_offset + ob2_rd_entry_ptr_q'length-1), + din => ob2_rd_entry_ptr_d(0 to 1), + dout => ob2_rd_entry_ptr_q(0 to 1) ); + +latch_ob3_rd_entry_ptr : tri_rlmreg_p + generic map (width => ob3_rd_entry_ptr_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob3_rd_entry_ptr_offset to ob3_rd_entry_ptr_offset + ob3_rd_entry_ptr_q'length-1), + scout => sov(ob3_rd_entry_ptr_offset to ob3_rd_entry_ptr_offset + ob3_rd_entry_ptr_q'length-1), + din => ob3_rd_entry_ptr_d(0 to 1), + dout => ob3_rd_entry_ptr_q(0 to 1) ); + +--**************************************************************************** +-- use read pointer to select message buffer complete reg for each thread +--**************************************************************************** + +with ob0_rd_entry_ptr_q(0 to 1) select + ob0_to_nd_status_reg <= ob0_buf0_status_val & ob0_buf0_status_q(1 to 17) when "00", + ob0_buf1_status_val & ob0_buf1_status_q(1 to 17) when "01", + ob0_buf2_status_val & ob0_buf2_status_q(1 to 17) when "10", + ob0_buf3_status_val & ob0_buf3_status_q(1 to 17) when others; + +with ob1_rd_entry_ptr_q(0 to 1) select + ob1_to_nd_status_reg <= ob1_buf0_status_val & ob1_buf0_status_q(1 to 17) when "00", + ob1_buf1_status_val & ob1_buf1_status_q(1 to 17) when "01", + ob1_buf2_status_val & ob1_buf2_status_q(1 to 17) when "10", + ob1_buf3_status_val & ob1_buf3_status_q(1 to 17) when others; + +with ob2_rd_entry_ptr_q(0 to 1) select + ob2_to_nd_status_reg <= ob2_buf0_status_val & ob2_buf0_status_q(1 to 17) when "00", + ob2_buf1_status_val & ob2_buf1_status_q(1 to 17) when "01", + ob2_buf2_status_val & ob2_buf2_status_q(1 to 17) when "10", + ob2_buf3_status_val & ob2_buf3_status_q(1 to 17) when others; + +with ob3_rd_entry_ptr_q(0 to 1) select + ob3_to_nd_status_reg <= ob3_buf0_status_val & ob3_buf0_status_q(1 to 17) when "00", + ob3_buf1_status_val & ob3_buf1_status_q(1 to 17) when "01", + ob3_buf2_status_val & ob3_buf2_status_q(1 to 17) when "10", + ob3_buf3_status_val & ob3_buf3_status_q(1 to 17) when others; + +--**************************************************************************** +-- Determine which thread gets selected to send to node +-- +-- This logic is best described with this table macro +-- the AND OR equations from the table are written below +--**************************************************************************** + +-- +-- ?TABLE ob_to_node_sel LISTING(final) OPTIMIZE PARMS(ON-SET,OFF-SET); +-- *INPUTS*=================================================*OUTPUTS*=====================* +-- | | | +-- | ob0_to_nd_status_reg | ob_to_node_sel_d | +-- | | ob1_to_nd_status_reg | | | +-- | | | ob2_to_nd_status_reg | | | +-- | | | | ob3_to_nd_status_reg | | | +-- | | | | | ob_to_node_sel_q | | ob_to_nd_val | +-- | | | | | | send_ob_idle | | | | +-- | | | | | | | | | | | +-- | 0 0 0 0 0123 | | 0123 | | +-- *TYPE*===================================================+=============================+ +-- | . . . . .... . | .... . | +-- *OPTIMIZE*---------------------------------------------->| AAAA B | +-- *TERMS*==================================================+=============================+ +-- | 0 0 0 0 0001 - | 0001 0 | +-- | 0 0 0 0 0010 - | 0010 0 | +-- | 0 0 0 0 0100 - | 0100 0 | +-- | 0 0 0 0 1000 - | 1000 0 | +-- | - - - - 0001 0 | 0001 0 | +-- | - - - - 0010 0 | 0010 0 | +-- | - - - - 0100 0 | 0100 0 | +-- | - - - - 1000 0 | 1000 0 | +-- *========================================================+=============================+ +-- | 1 - - - 0001 1 | 1000 1 | +-- | 0 1 - - 0001 1 | 0100 1 | +-- | 0 0 1 - 0001 1 | 0010 1 | +-- | 0 0 0 1 0001 1 | 0001 1 | +-- *========================================================+=============================+ +-- | - 1 - - 1000 1 | 0100 1 | +-- | - 0 1 - 1000 1 | 0010 1 | +-- | - 0 0 1 1000 1 | 0001 1 | +-- | 1 0 0 0 1000 1 | 1000 1 | +-- *========================================================+=============================+ +-- | - - 1 - 0100 1 | 0010 1 | +-- | - - 0 1 0100 1 | 0001 1 | +-- | 1 - 0 0 0100 1 | 1000 1 | +-- | 0 1 0 0 0100 1 | 0100 1 | +-- *========================================================+=============================+ +-- | - - - 1 0010 1 | 0001 1 | +-- | 1 - - 0 0010 1 | 1000 1 | +-- | 0 1 - 0 0010 1 | 0100 1 | +-- | 0 0 1 0 0010 1 | 0010 1 | +-- *END*====================================================+=============================+ +-- ?TABLE END ob_to_node_sel ; + +ob_to_nd_status_reg_vals(0 to 3) <= ob0_to_nd_status_reg(0) & + ob1_to_nd_status_reg(0) & + ob2_to_nd_status_reg(0) & + ob3_to_nd_status_reg(0); + + +ob_to_node_sel_d(0) <= (ob_to_nd_status_reg_vals(0) and ob_to_node_sel_q(3)) or + (ob_to_nd_status_reg_vals(0) and ob_to_node_sel_q(2) and ob_to_nd_status_reg_vals(3)='0' ) or + (ob_to_nd_status_reg_vals(0) and ob_to_node_sel_q(1) and ob_to_nd_status_reg_vals(2 to 3)="00" ) or + (ob_to_nd_status_reg_vals(0) and ob_to_node_sel_q(0) and ob_to_nd_status_reg_vals(1 to 3)="000" ) or + (ob_to_node_sel_q(0) and ob_to_nd_status_reg_vals(0 to 3)="0000" ); + +ob_to_node_sel_d(1) <= (ob_to_nd_status_reg_vals(1) and ob_to_node_sel_q(0)) or + (ob_to_nd_status_reg_vals(1) and ob_to_node_sel_q(3) and ob_to_nd_status_reg_vals(0)='0' ) or + (ob_to_nd_status_reg_vals(1) and ob_to_node_sel_q(2) and ob_to_nd_status_reg_vals(3)='0' and ob_to_nd_status_reg_vals(0)='0' ) or + (ob_to_nd_status_reg_vals(1) and ob_to_node_sel_q(1) and ob_to_nd_status_reg_vals(2 to 3)="00" and ob_to_nd_status_reg_vals(0)='0' ) or + (ob_to_node_sel_q(1) and ob_to_nd_status_reg_vals(0 to 3)="0000" ); + +ob_to_node_sel_d(2) <= (ob_to_nd_status_reg_vals(2) and ob_to_node_sel_q(1)) or + (ob_to_nd_status_reg_vals(2) and ob_to_node_sel_q(0) and ob_to_nd_status_reg_vals(1)='0' ) or + (ob_to_nd_status_reg_vals(2) and ob_to_node_sel_q(3) and ob_to_nd_status_reg_vals(0 to 1)="00" ) or + (ob_to_nd_status_reg_vals(2) and ob_to_node_sel_q(2) and ob_to_nd_status_reg_vals(3)='0' and ob_to_nd_status_reg_vals(0 to 1)="00" ) or + (ob_to_node_sel_q(2) and ob_to_nd_status_reg_vals(0 to 3)="0000" ); + +ob_to_node_sel_d(3) <= (ob_to_nd_status_reg_vals(3) and ob_to_node_sel_q(2)) or + (ob_to_nd_status_reg_vals(3) and ob_to_node_sel_q(1) and ob_to_nd_status_reg_vals(2)='0' ) or + (ob_to_nd_status_reg_vals(3) and ob_to_node_sel_q(0) and ob_to_nd_status_reg_vals(1 to 2)="00" ) or + (ob_to_nd_status_reg_vals(3) and ob_to_node_sel_q(3) and ob_to_nd_status_reg_vals(0 to 2)="000" ) or + (ob_to_node_sel_q(3) and ob_to_nd_status_reg_vals(0 to 3)="0000" ); + + +-- latch the outbox to node select + +latch_ob_to_node_sel : tri_rlmreg_p + generic map (width => ob_to_node_sel_q'length, init => 1, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_to_node_sel_offset to ob_to_node_sel_offset + ob_to_node_sel_q'length-1), + scout => sov(ob_to_node_sel_offset to ob_to_node_sel_offset + ob_to_node_sel_q'length-1), + din => ob_to_node_sel_d(0 to 3), + dout => ob_to_node_sel_q(0 to 3) ); + +ob_to_node_sel_sav_d(0 to 3) <= ob_to_node_sel_q(0 to 3) when send_ob_idle='1' else + ob_to_node_sel_sav_q(0 to 3); + +latch_ob_to_node_sel_sav : tri_rlmreg_p + generic map (width => ob_to_node_sel_sav_q'length, init => 1, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_to_node_sel_sav_offset to ob_to_node_sel_sav_offset + ob_to_node_sel_sav_q'length-1), + scout => sov(ob_to_node_sel_sav_offset to ob_to_node_sel_sav_offset + ob_to_node_sel_sav_q'length-1), + din => ob_to_node_sel_sav_d(0 to 3), + dout => ob_to_node_sel_sav_q(0 to 3) ); + +ob_to_node_status_reg(1 to 17) <= gate_and( ob_to_node_sel_sav_q(0), ob0_to_nd_status_reg(1 to 17) ) or + gate_and( ob_to_node_sel_sav_q(1), ob1_to_nd_status_reg(1 to 17) ) or + gate_and( ob_to_node_sel_sav_q(2), ob2_to_nd_status_reg(1 to 17) ) or + gate_and( ob_to_node_sel_sav_q(3), ob3_to_nd_status_reg(1 to 17) ); + + +ob_to_nd_val_t0 <= send_ob_idle and ob0_to_nd_status_reg(0) and ob_to_node_sel_q(0); +ob_to_nd_val_t1 <= send_ob_idle and ob1_to_nd_status_reg(0) and ob_to_node_sel_q(1); +ob_to_nd_val_t2 <= send_ob_idle and ob2_to_nd_status_reg(0) and ob_to_node_sel_q(2); +ob_to_nd_val_t3 <= send_ob_idle and ob3_to_nd_status_reg(0) and ob_to_node_sel_q(3); + + +-- delay the ipc outbox command 1 cycle so that it lines up with the data +--latch_ipc_ob_cmd : tri_rlmreg_p +-- generic map (width => ipc_ob_cmd_q'length, init => 0, expand_type => expand_type) +-- port map (nclk => nclk, +-- act => '1', +-- forcee => func_sl_force, +-- d_mode => d_mode_dc, +-- delay_lclkr => delay_lclkr_dc, +-- mpw1_b => mpw1_dc_b, +-- mpw2_b => mpw2_dc_b, +-- thold_b => func_sl_thold_0_b, +-- sg => sg_0, +-- vd => vdd, +-- gd => gnd, +-- sreset => func_sl_thold_0_b, +-- scin => siv(ipc_ob_cmd_offset to ipc_ob_cmd_offset + ipc_ob_cmd_q'length-1), +-- scout => sov(ipc_ob_cmd_offset to ipc_ob_cmd_offset + ipc_ob_cmd_q'length-1), +-- din => ob_to_node_status_reg(0 to 18), +-- dout => ipc_ob_cmd_q(0 to 18) ); + +--**************************************************************************** +-- LSU interface +--**************************************************************************** + +latch_lsu_cmd_avail : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(lsu_cmd_avail_offset to lsu_cmd_avail_offset), + scout => sov(lsu_cmd_avail_offset to lsu_cmd_avail_offset), + din(0) => lsu_bx_cmd_avail, + dout(0) => lsu_cmd_avail_q ); + +latch_lsu_cmd_sent : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(lsu_cmd_sent_offset to lsu_cmd_sent_offset), + scout => sov(lsu_cmd_sent_offset to lsu_cmd_sent_offset), + din(0) => lsu_bx_cmd_sent, + dout(0) => lsu_cmd_sent_q ); + +latch_lsu_cmd_stall : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(lsu_cmd_stall_offset to lsu_cmd_stall_offset), + scout => sov(lsu_cmd_stall_offset to lsu_cmd_stall_offset), + din(0) => lsu_bx_cmd_stall, + dout(0) => lsu_cmd_stall_q ); + + +--**************************************************************************** +-- outbox data transfer stall counter: Counts OB commands that have been +-- sent from the LSU and keeps track of which one needs to be resent when +-- the LSU stalls. +-- +-- 000 -> no transfers sent from LSU, resend the 2nd data beat on a stall +-- 001 -> count the 1st transfer sent from LSU, resend the 3rd data beat on a stall +-- 010 -> count the 2nd transfer sent from LSU, resend the 4rd data beat on a stall +-- 011 -> count the 3rd transfer sent from LSU, resend the DITC on a stall +-- 100 -> count the 4th transfer sent from LSU, LSU already has DITC - don't need to resend +-- 101 -> count the DITC transfer sent from LSU, OB message is done +--**************************************************************************** + +ob_cmd_sent_count_d(0 to 2) <= "000" when ob_to_nd_done_d = '1' else + std_ulogic_vector(unsigned(ob_cmd_sent_count_q) + 1) when lsu_cmd_sent_q = '1' else + ob_cmd_sent_count_q(0 to 2); + + +latch_ob_cmd_sent_count : tri_rlmreg_p + generic map (width => ob_cmd_sent_count_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_cmd_sent_count_offset to ob_cmd_sent_count_offset + ob_cmd_sent_count_q'length-1), + scout => sov(ob_cmd_sent_count_offset to ob_cmd_sent_count_offset + ob_cmd_sent_count_q'length-1), + din => ob_cmd_sent_count_d(0 to 2), + dout => ob_cmd_sent_count_q(0 to 2) ); + +--**************************************************************************** +-- State machine for sending packet from outbox to node +--**************************************************************************** + +ob_to_nd_ready <= ((ob_to_nd_val_t0 and ob_credit_t0) or + (ob_to_nd_val_t1 and ob_credit_t1) or + (ob_to_nd_val_t2 and ob_credit_t2) or + (ob_to_nd_val_t3 and ob_credit_t3)) and lsu_cmd_avail_q; + +ob_lsu_complete <= (((ob_cmd_sent_count_q = "100") and (ob_to_node_status_reg(1 to 2) = "11")) or -- len is 64B + ((ob_cmd_sent_count_q = "011") and (ob_to_node_status_reg(1 to 2) = "10")) or -- len is 48B + ((ob_cmd_sent_count_q = "010") and (ob_to_node_status_reg(1 to 2) = "01")) or -- len is 32B + ((ob_cmd_sent_count_q = "001") and (ob_to_node_status_reg(1 to 2) = "00"))) and lsu_cmd_sent_q; + +send_ob_idle <= send_ob_state_q(6); +send_ob_data1 <= send_ob_state_q(0); +send_ob_data2 <= send_ob_state_q(1); +send_ob_data3 <= send_ob_state_q(2); +send_ob_data4 <= send_ob_state_q(3); +send_ob_ditc <= send_ob_state_q(4); +send_ob_wait <= send_ob_state_q(5); + +send_ob_state_mach: process(send_ob_idle, send_ob_data1, send_ob_data2, send_ob_data3, send_ob_data4, send_ob_ditc, send_ob_wait, ob_to_nd_ready, ob_to_node_status_reg(1 to 2), lsu_cmd_stall_q, ob_cmd_sent_count_q, ob_lsu_complete, ob_ary_ue_or) begin + + send_ob_nxt_idle <= '0'; + send_ob_nxt_data1 <= '0'; + send_ob_nxt_data2 <= '0'; + send_ob_nxt_data3 <= '0'; + send_ob_nxt_data4 <= '0'; + send_ob_nxt_ditc <= '0'; + send_ob_nxt_wait <= '0'; + ob_to_nd_done_d <= '0'; + + if send_ob_idle = '1' then + if ob_to_nd_ready = '1' then + send_ob_nxt_data1 <= '1'; + else + send_ob_nxt_idle <= '1'; + end if; + end if; + + if send_ob_data1 = '1' then + if ob_ary_ue_or = '1' then + send_ob_nxt_idle <= '1'; + ob_to_nd_done_d <= '1'; + elsif ob_to_node_status_reg(1 to 2) = "00" then -- length of transfer is 16B + send_ob_nxt_ditc <= '1'; + else + send_ob_nxt_data2 <= '1'; + end if; + end if; + + if send_ob_data2 = '1' then + if ob_ary_ue_or = '1' then + send_ob_nxt_idle <= '1'; + ob_to_nd_done_d <= '1'; + elsif lsu_cmd_stall_q = '0' then + if ob_to_node_status_reg(1 to 2) = "01" then -- length of transfer is 32B + send_ob_nxt_ditc <= '1'; + else + send_ob_nxt_data3 <= '1'; + end if; + else -- stall = 1 + send_ob_nxt_data2 <= '1'; + end if; + end if; + + if send_ob_data3 = '1' then + if ob_ary_ue_or = '1' then + send_ob_nxt_idle <= '1'; + ob_to_nd_done_d <= '1'; + elsif lsu_cmd_stall_q = '0' then + if ob_to_node_status_reg(1 to 2) = "10" then -- length of transfer is 48B + send_ob_nxt_ditc <= '1'; + else + send_ob_nxt_data4 <= '1'; + end if; + else -- stall = 1 + send_ob_nxt_data3 <= '1'; + end if; + end if; + + if send_ob_data4 = '1' then + if ob_ary_ue_or = '1' then + send_ob_nxt_idle <= '1'; + ob_to_nd_done_d <= '1'; + elsif lsu_cmd_stall_q = '0' then + send_ob_nxt_ditc <= '1'; + else -- stall = 1 + send_ob_nxt_data4 <= '1'; + end if; + end if; + + if send_ob_ditc = '1' then + if ob_ary_ue_or = '1' then + send_ob_nxt_idle <= '1'; + ob_to_nd_done_d <= '1'; + elsif lsu_cmd_stall_q = '0' then + send_ob_nxt_wait <= '1'; + else -- stall = 1 + send_ob_nxt_ditc <= '1'; + end if; + end if; + + if send_ob_wait = '1' then + if ob_ary_ue_or = '1' then + send_ob_nxt_idle <= '1'; + ob_to_nd_done_d <= '1'; + elsif lsu_cmd_stall_q = '0' then + if (ob_lsu_complete = '1') then + send_ob_nxt_idle <= '1'; + ob_to_nd_done_d <= '1'; + else + send_ob_nxt_wait <= '1'; + end if; + else -- stall = 1 + if ob_cmd_sent_count_q = "000" then + send_ob_nxt_data2 <= '1'; + elsif ob_cmd_sent_count_q = "001" then + send_ob_nxt_data3 <= '1'; + elsif ob_cmd_sent_count_q = "010" then + send_ob_nxt_data4 <= '1'; + elsif ob_cmd_sent_count_q = "011" then + send_ob_nxt_ditc <= '1'; + else -- count = 100 + send_ob_nxt_wait <= '1'; + end if; + end if; + end if; + +end process; + +send_ob_nxt_state(6) <= send_ob_nxt_idle; +send_ob_nxt_state(0) <= send_ob_nxt_data1; +send_ob_nxt_state(1) <= send_ob_nxt_data2; +send_ob_nxt_state(2) <= send_ob_nxt_data3; +send_ob_nxt_state(3) <= send_ob_nxt_data4; +send_ob_nxt_state(4) <= send_ob_nxt_ditc; +send_ob_nxt_state(5) <= send_ob_nxt_wait; + +latch_send_ob_state : tri_rlmreg_p + generic map (width => send_ob_state_q'length, init => 1, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(send_ob_state_offset to send_ob_state_offset + send_ob_state_q'length-1), + scout => sov(send_ob_state_offset to send_ob_state_offset + send_ob_state_q'length-1), + din => send_ob_nxt_state, + dout => send_ob_state_q ); + + + + +ob0_buf_done <= ob_to_nd_done_d and ob_to_node_sel_sav_q(0); +ob1_buf_done <= ob_to_nd_done_d and ob_to_node_sel_sav_q(1); +ob2_buf_done <= ob_to_nd_done_d and ob_to_node_sel_sav_q(2); +ob3_buf_done <= ob_to_nd_done_d and ob_to_node_sel_sav_q(3); + +ob0_buf0_done <= ob_to_nd_done_d and ob_to_node_sel_sav_q(0) and ob0_rd_entry_ptr_q(0 to 1)="00"; +ob0_buf1_done <= ob_to_nd_done_d and ob_to_node_sel_sav_q(0) and ob0_rd_entry_ptr_q(0 to 1)="01"; +ob0_buf2_done <= ob_to_nd_done_d and ob_to_node_sel_sav_q(0) and ob0_rd_entry_ptr_q(0 to 1)="10"; +ob0_buf3_done <= ob_to_nd_done_d and ob_to_node_sel_sav_q(0) and ob0_rd_entry_ptr_q(0 to 1)="11"; +ob1_buf0_done <= ob_to_nd_done_d and ob_to_node_sel_sav_q(1) and ob1_rd_entry_ptr_q(0 to 1)="00"; +ob1_buf1_done <= ob_to_nd_done_d and ob_to_node_sel_sav_q(1) and ob1_rd_entry_ptr_q(0 to 1)="01"; +ob1_buf2_done <= ob_to_nd_done_d and ob_to_node_sel_sav_q(1) and ob1_rd_entry_ptr_q(0 to 1)="10"; +ob1_buf3_done <= ob_to_nd_done_d and ob_to_node_sel_sav_q(1) and ob1_rd_entry_ptr_q(0 to 1)="11"; +ob2_buf0_done <= ob_to_nd_done_d and ob_to_node_sel_sav_q(2) and ob2_rd_entry_ptr_q(0 to 1)="00"; +ob2_buf1_done <= ob_to_nd_done_d and ob_to_node_sel_sav_q(2) and ob2_rd_entry_ptr_q(0 to 1)="01"; +ob2_buf2_done <= ob_to_nd_done_d and ob_to_node_sel_sav_q(2) and ob2_rd_entry_ptr_q(0 to 1)="10"; +ob2_buf3_done <= ob_to_nd_done_d and ob_to_node_sel_sav_q(2) and ob2_rd_entry_ptr_q(0 to 1)="11"; +ob3_buf0_done <= ob_to_nd_done_d and ob_to_node_sel_sav_q(3) and ob3_rd_entry_ptr_q(0 to 1)="00"; +ob3_buf1_done <= ob_to_nd_done_d and ob_to_node_sel_sav_q(3) and ob3_rd_entry_ptr_q(0 to 1)="01"; +ob3_buf2_done <= ob_to_nd_done_d and ob_to_node_sel_sav_q(3) and ob3_rd_entry_ptr_q(0 to 1)="10"; +ob3_buf3_done <= ob_to_nd_done_d and ob_to_node_sel_sav_q(3) and ob3_rd_entry_ptr_q(0 to 1)="11"; + + +--**************************************************************************** +-- determine outbox array read pointer +--**************************************************************************** + +ob_to_node_selected_thrd(0) <= ob_to_node_sel_sav_q(2) or ob_to_node_sel_sav_q(3); +ob_to_node_selected_thrd(1) <= ob_to_node_sel_sav_q(1) or ob_to_node_sel_sav_q(3); + +ob_to_node_selected_rd_ptr(0 to 1) <= gate_and(ob_to_node_sel_sav_q(0) , ob0_rd_entry_ptr_q(0 to 1) ) or + gate_and(ob_to_node_sel_sav_q(1) , ob1_rd_entry_ptr_q(0 to 1) ) or + gate_and(ob_to_node_sel_sav_q(2) , ob2_rd_entry_ptr_q(0 to 1) ) or + gate_and(ob_to_node_sel_sav_q(3) , ob3_rd_entry_ptr_q(0 to 1) ); + +send_ob_seq_ptr(0) <= send_ob_data3 or send_ob_data4; +send_ob_seq_ptr(1) <= send_ob_data2 or send_ob_data4; + +ob_to_node_data_ptr(0 to 1) <= send_ob_seq_ptr(0 to 1) when lsu_cmd_stall_q = '0' else -- send data pointed to by state machine + "01" when ob_cmd_sent_count_q = "000" else -- resend 2nd data beat + "10" when ob_cmd_sent_count_q = "001" else -- resend 3rd data beat + "11"; -- when ob_cmd_sent_count_q = "010" else -- resend 4th data beat + +ob_ary_rd_addr(0 to 5) <= ob_to_node_selected_thrd & ob_to_node_selected_rd_ptr & ob_to_node_data_ptr; + + +--**************************************************************************** +-- send command to the lsu +--**************************************************************************** + +send_ob_data_val <= ((send_ob_data1 or send_ob_data2 or send_ob_data3 or send_ob_data4) and not lsu_cmd_stall_q); + +dly_ob_cmd_val_d(0) <= send_ob_data_val and not ob_ary_ue_or; +dly_ob_cmd_val_d(1) <= dly_ob_cmd_val_q(0) and not ob_ary_ue_or; + +latch_dly_ob_cmd_val : tri_rlmreg_p + generic map (width => dly_ob_cmd_val_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(dly_ob_cmd_val_offset to dly_ob_cmd_val_offset + dly_ob_cmd_val_q'length-1), + scout => sov(dly_ob_cmd_val_offset to dly_ob_cmd_val_offset + dly_ob_cmd_val_q'length-1), + din => dly_ob_cmd_val_d(0 to 1), + dout => dly_ob_cmd_val_q(0 to 1) ); + +bx_lsu_ob_pwr_tok <= dly_ob_cmd_val_q(1) or dly_ob_ditc_val_q(1); + +bx_lsu_ob_req_val_d <= dly_ob_cmd_val_q(1) and not ob_ary_ue_or; + +latch_bxlsu_ob_req_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(bxlsu_ob_req_val_offset to bxlsu_ob_req_val_offset), + scout => sov(bxlsu_ob_req_val_offset to bxlsu_ob_req_val_offset), + din(0) => bx_lsu_ob_req_val_d, + dout(0) => bx_lsu_ob_req_val_int ); + +bx_lsu_ob_req_val <= bx_lsu_ob_req_val_int; + +send_ob_ditc_val <= (send_ob_ditc and not lsu_cmd_stall_q); + +dly_ob_ditc_val_d(0) <= send_ob_ditc_val and not ob_ary_ue_or; +dly_ob_ditc_val_d(1) <= dly_ob_ditc_val_q(0) and not ob_ary_ue_or; + +latch_dly_ob_ditc_val : tri_rlmreg_p + generic map (width => dly_ob_ditc_val_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(dly_ob_ditc_val_offset to dly_ob_ditc_val_offset + dly_ob_ditc_val_q'length-1), + scout => sov(dly_ob_ditc_val_offset to dly_ob_ditc_val_offset + dly_ob_ditc_val_q'length-1), + din => dly_ob_ditc_val_d(0 to 1), + dout => dly_ob_ditc_val_q(0 to 1) ); + +latch_bxlsu_ob_ditc_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(bxlsu_ob_ditc_val_offset to bxlsu_ob_ditc_val_offset), + scout => sov(bxlsu_ob_ditc_val_offset to bxlsu_ob_ditc_val_offset), + din(0) => dly_ob_ditc_val_q(1), + dout(0) => bx_lsu_ob_ditc_val ); + +latch_dly_ob_qw : tri_rlmreg_p + generic map (width => dly_ob_qw'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(dly_ob_qw_offset to dly_ob_qw_offset + dly_ob_qw'length-1), + scout => sov(dly_ob_qw_offset to dly_ob_qw_offset + dly_ob_qw'length-1), + din => ob_to_node_data_ptr(0 to 1), + dout => dly_ob_qw ); + +latch_dly1_ob_qw : tri_rlmreg_p + generic map (width => dly1_ob_qw'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(dly1_ob_qw_offset to dly1_ob_qw_offset + dly1_ob_qw'length-1), + scout => sov(dly1_ob_qw_offset to dly1_ob_qw_offset + dly1_ob_qw'length-1), + din => dly_ob_qw, + dout => dly1_ob_qw ); + + +latch_bxlsu_ob_qw : tri_rlmreg_p + generic map (width => bx_lsu_ob_qw'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(bxlsu_ob_qw_offset to bxlsu_ob_qw_offset + bx_lsu_ob_qw'length-1), + scout => sov(bxlsu_ob_qw_offset to bxlsu_ob_qw_offset + bx_lsu_ob_qw'length-1), + din => dly1_ob_qw, + dout => bx_lsu_ob_qw ); + + +latch_bxlsu_ob_thrd : tri_rlmreg_p + generic map (width => bx_lsu_ob_thrd'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(bxlsu_ob_thrd_offset to bxlsu_ob_thrd_offset + bx_lsu_ob_thrd'length-1), + scout => sov(bxlsu_ob_thrd_offset to bxlsu_ob_thrd_offset + bx_lsu_ob_thrd'length-1), + din => ob_to_node_selected_thrd(0 to 1), + dout => bx_lsu_ob_thrd ); + +with ob_to_node_selected_thrd(0 to 1) select + ob_addr_d <= ditc_addr_t0_q when "00", + ditc_addr_t1_q when "01", + ditc_addr_t2_q when "10", + ditc_addr_t3_q when others; + +latch_bxlsu_ob_addr : tri_rlmreg_p + generic map (width => bx_lsu_ob_addr'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(bxlsu_ob_addr_offset to bxlsu_ob_addr_offset + bx_lsu_ob_addr'length-1), + scout => sov(bxlsu_ob_addr_offset to bxlsu_ob_addr_offset + bx_lsu_ob_addr'length-1), + din => ob_addr_d, + dout => bx_lsu_ob_addr ); + + +latch_bxlsu_ob_dest : tri_rlmreg_p + generic map (width => bx_lsu_ob_dest'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_rd_logic_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(bxlsu_ob_dest_offset to bxlsu_ob_dest_offset + bx_lsu_ob_dest'length-1), + scout => sov(bxlsu_ob_dest_offset to bxlsu_ob_dest_offset + bx_lsu_ob_dest'length-1), + din => ob_to_node_status_reg(3 to 17), + dout => bx_lsu_ob_dest ); + + +bx_lsu_ob_data <= ob_rd_data_cor_l2; + +--**************************************************************************** +-- nd interface credit counter for outbox +--**************************************************************************** + +-- latch the pop signal from the node interface + +latch_st_pop : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(st_pop_offset to st_pop_offset), + scout => sov(st_pop_offset to st_pop_offset), + din(0) => lsu_req_st_pop, + dout(0) => lat_st_pop ); + +latch_st_pop_thrd : tri_rlmreg_p + generic map (width => lat_st_pop_thrd'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(st_pop_thrd_offset to st_pop_thrd_offset + lat_st_pop_thrd'length-1), + scout => sov(st_pop_thrd_offset to st_pop_thrd_offset + lat_st_pop_thrd'length-1), + din => lsu_req_st_pop_thrd(0 to 2), + dout => lat_st_pop_thrd(0 to 2) ); + +ob_cmd_count_incr_t0(0 to 1) <= std_ulogic_vector(unsigned(ob_cmd_count_t0_q) + 1); +ob_cmd_count_decr_t0(0 to 1) <= std_ulogic_vector(unsigned(ob_cmd_count_t0_q) - 1); + +ob_cmd_count_incr_t1(0 to 1) <= std_ulogic_vector(unsigned(ob_cmd_count_t1_q) + 1); +ob_cmd_count_decr_t1(0 to 1) <= std_ulogic_vector(unsigned(ob_cmd_count_t1_q) - 1); + +ob_cmd_count_incr_t2(0 to 1) <= std_ulogic_vector(unsigned(ob_cmd_count_t2_q) + 1); +ob_cmd_count_decr_t2(0 to 1) <= std_ulogic_vector(unsigned(ob_cmd_count_t2_q) - 1); + +ob_cmd_count_incr_t3(0 to 1) <= std_ulogic_vector(unsigned(ob_cmd_count_t3_q) + 1); +ob_cmd_count_decr_t3(0 to 1) <= std_ulogic_vector(unsigned(ob_cmd_count_t3_q) - 1); + +ob_pop(0) <= lat_st_pop and lat_st_pop_thrd(2) and lat_st_pop_thrd(0 to 1)="00"; +ob_pop(1) <= lat_st_pop and lat_st_pop_thrd(2) and lat_st_pop_thrd(0 to 1)="01"; +ob_pop(2) <= lat_st_pop and lat_st_pop_thrd(2) and lat_st_pop_thrd(0 to 1)="10"; +ob_pop(3) <= lat_st_pop and lat_st_pop_thrd(2) and lat_st_pop_thrd(0 to 1)="11"; + +ob_cmd_count_t0_d(0 to 1) <= ob_cmd_count_incr_t0(0 to 1) when ( (ob_to_nd_val_t0 and ob_credit_t0 and lsu_cmd_avail_q) and not ob_pop(0)) = '1' else + ob_cmd_count_decr_t0(0 to 1) when (not (ob_to_nd_val_t0 and ob_credit_t0 and lsu_cmd_avail_q) and ob_pop(0)) = '1' else + ob_cmd_count_t0_q; + +ob_cmd_count_t1_d(0 to 1) <= ob_cmd_count_incr_t1(0 to 1) when ( (ob_to_nd_val_t1 and ob_credit_t1 and lsu_cmd_avail_q) and not ob_pop(1)) = '1' else + ob_cmd_count_decr_t1(0 to 1) when (not (ob_to_nd_val_t1 and ob_credit_t1 and lsu_cmd_avail_q) and ob_pop(1)) = '1' else + ob_cmd_count_t1_q; + +ob_cmd_count_t2_d(0 to 1) <= ob_cmd_count_incr_t2(0 to 1) when ( (ob_to_nd_val_t2 and ob_credit_t2 and lsu_cmd_avail_q) and not ob_pop(2)) = '1' else + ob_cmd_count_decr_t2(0 to 1) when (not (ob_to_nd_val_t2 and ob_credit_t2 and lsu_cmd_avail_q) and ob_pop(2)) = '1' else + ob_cmd_count_t2_q; + +ob_cmd_count_t3_d(0 to 1) <= ob_cmd_count_incr_t3(0 to 1) when ( (ob_to_nd_val_t3 and ob_credit_t3 and lsu_cmd_avail_q) and not ob_pop(3)) = '1' else + ob_cmd_count_decr_t3(0 to 1) when (not (ob_to_nd_val_t3 and ob_credit_t3 and lsu_cmd_avail_q) and ob_pop(3)) = '1' else + ob_cmd_count_t3_q; + +latch_ob_cmd_count_t0 : tri_rlmreg_p + generic map (width => ob_cmd_count_t0_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_cmd_count_t0_offset to ob_cmd_count_t0_offset + ob_cmd_count_t0_q'length-1), + scout => sov(ob_cmd_count_t0_offset to ob_cmd_count_t0_offset + ob_cmd_count_t0_q'length-1), + din => ob_cmd_count_t0_d(0 to 1), + dout => ob_cmd_count_t0_q(0 to 1) ); + +latch_ob_cmd_count_t1 : tri_rlmreg_p + generic map (width => ob_cmd_count_t1_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_cmd_count_t1_offset to ob_cmd_count_t1_offset + ob_cmd_count_t1_q'length-1), + scout => sov(ob_cmd_count_t1_offset to ob_cmd_count_t1_offset + ob_cmd_count_t1_q'length-1), + din => ob_cmd_count_t1_d(0 to 1), + dout => ob_cmd_count_t1_q(0 to 1) ); + +latch_ob_cmd_count_t2 : tri_rlmreg_p + generic map (width => ob_cmd_count_t2_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_cmd_count_t2_offset to ob_cmd_count_t2_offset + ob_cmd_count_t2_q'length-1), + scout => sov(ob_cmd_count_t2_offset to ob_cmd_count_t2_offset + ob_cmd_count_t2_q'length-1), + din => ob_cmd_count_t2_d(0 to 1), + dout => ob_cmd_count_t2_q(0 to 1) ); + +latch_ob_cmd_count_t3 : tri_rlmreg_p + generic map (width => ob_cmd_count_t3_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_cmd_count_t3_offset to ob_cmd_count_t3_offset + ob_cmd_count_t3_q'length-1), + scout => sov(ob_cmd_count_t3_offset to ob_cmd_count_t3_offset + ob_cmd_count_t3_q'length-1), + din => ob_cmd_count_t3_d(0 to 1), + dout => ob_cmd_count_t3_q(0 to 1) ); + +ob_credit_t0 <= not ob_cmd_count_t0_q(0); -- when cmd count gets to 2, there are no credits left +ob_credit_t1 <= not ob_cmd_count_t1_q(0); -- when cmd count gets to 2, there are no credits left +ob_credit_t2 <= not ob_cmd_count_t2_q(0); -- when cmd count gets to 2, there are no credits left +ob_credit_t3 <= not ob_cmd_count_t3_q(0); -- when cmd count gets to 2, there are no credits left + + +-- ******************************************************************************************** +-- +-- INBOX +-- +-- ******************************************************************************************** + +--**************************************************************************** +-- write to the input data port status register when BA = 10000 +-- since ba(3:4)=00 the rotator will put the data on word 0 +--**************************************************************************** + +wrt_ib0_buf0_status <= ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "00") and (ex4_ipc_ba_q = "10000") and (ib0_rd_entry_ptr_dly_q = "00"); +wrt_ib0_buf1_status <= ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "00") and (ex4_ipc_ba_q = "10000") and (ib0_rd_entry_ptr_dly_q = "01"); +wrt_ib0_buf2_status <= ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "00") and (ex4_ipc_ba_q = "10000") and (ib0_rd_entry_ptr_dly_q = "10"); +wrt_ib0_buf3_status <= ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "00") and (ex4_ipc_ba_q = "10000") and (ib0_rd_entry_ptr_dly_q = "11"); +wrt_ib1_buf0_status <= ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "01") and (ex4_ipc_ba_q = "10000") and (ib1_rd_entry_ptr_dly_q = "00"); +wrt_ib1_buf1_status <= ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "01") and (ex4_ipc_ba_q = "10000") and (ib1_rd_entry_ptr_dly_q = "01"); +wrt_ib1_buf2_status <= ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "01") and (ex4_ipc_ba_q = "10000") and (ib1_rd_entry_ptr_dly_q = "10"); +wrt_ib1_buf3_status <= ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "01") and (ex4_ipc_ba_q = "10000") and (ib1_rd_entry_ptr_dly_q = "11"); +wrt_ib2_buf0_status <= ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "10") and (ex4_ipc_ba_q = "10000") and (ib2_rd_entry_ptr_dly_q = "00"); +wrt_ib2_buf1_status <= ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "10") and (ex4_ipc_ba_q = "10000") and (ib2_rd_entry_ptr_dly_q = "01"); +wrt_ib2_buf2_status <= ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "10") and (ex4_ipc_ba_q = "10000") and (ib2_rd_entry_ptr_dly_q = "10"); +wrt_ib2_buf3_status <= ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "10") and (ex4_ipc_ba_q = "10000") and (ib2_rd_entry_ptr_dly_q = "11"); +wrt_ib3_buf0_status <= ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "11") and (ex4_ipc_ba_q = "10000") and (ib3_rd_entry_ptr_dly_q = "00"); +wrt_ib3_buf1_status <= ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "11") and (ex4_ipc_ba_q = "10000") and (ib3_rd_entry_ptr_dly_q = "01"); +wrt_ib3_buf2_status <= ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "11") and (ex4_ipc_ba_q = "10000") and (ib3_rd_entry_ptr_dly_q = "10"); +wrt_ib3_buf3_status <= ex4_mtdp_val_gated and (ex4_ipc_thrd_q = "11") and (ex4_ipc_ba_q = "10000") and (ib3_rd_entry_ptr_dly_q = "11"); + +ib0_incr_ptr <= ex3_mtdp_val and (ex3_ipc_thrd_q = "00") and (ex3_ipc_ba_q = "10000"); -- used to update entry ptr +ib1_incr_ptr <= ex3_mtdp_val and (ex3_ipc_thrd_q = "01") and (ex3_ipc_ba_q = "10000"); +ib2_incr_ptr <= ex3_mtdp_val and (ex3_ipc_thrd_q = "10") and (ex3_ipc_ba_q = "10000"); +ib3_incr_ptr <= ex3_mtdp_val and (ex3_ipc_thrd_q = "11") and (ex3_ipc_ba_q = "10000"); + +-- remember which status reg written last cycle + +ex4_wrt_ib_status(0 to 15) <= wrt_ib0_buf0_status & wrt_ib0_buf1_status & wrt_ib0_buf2_status & wrt_ib0_buf3_status & + wrt_ib1_buf0_status & wrt_ib1_buf1_status & wrt_ib1_buf2_status & wrt_ib1_buf3_status & + wrt_ib2_buf0_status & wrt_ib2_buf1_status & wrt_ib2_buf2_status & wrt_ib2_buf3_status & + wrt_ib3_buf0_status & wrt_ib3_buf1_status & wrt_ib3_buf2_status & wrt_ib3_buf3_status; + +ex4_ib0_flushed <= ex4_mtdp_val_q and (ex4_ipc_thrd_q = "00") and (ex4_ipc_ba_q = "10000") and my_ex4_stg_flush; +ex4_ib1_flushed <= ex4_mtdp_val_q and (ex4_ipc_thrd_q = "01") and (ex4_ipc_ba_q = "10000") and my_ex4_stg_flush; +ex4_ib2_flushed <= ex4_mtdp_val_q and (ex4_ipc_thrd_q = "10") and (ex4_ipc_ba_q = "10000") and my_ex4_stg_flush; +ex4_ib3_flushed <= ex4_mtdp_val_q and (ex4_ipc_thrd_q = "11") and (ex4_ipc_ba_q = "10000") and my_ex4_stg_flush; + +latch_ex5_wrt_ib_status : tri_rlmreg_p + generic map (width => ex5_wrt_ib_status_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => mtdp_ex3_to_7_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex5_wrt_ib_status_offset to ex5_wrt_ib_status_offset + ex5_wrt_ib_status_q'length-1), + scout => sov(ex5_wrt_ib_status_offset to ex5_wrt_ib_status_offset + ex5_wrt_ib_status_q'length-1), + din => ex4_wrt_ib_status(0 to 15), + dout => ex5_wrt_ib_status_q(0 to 15) ); + +ex5_wrt_ib_status_gated(0 to 15) <= gate_and(not my_ex5_stg_flush, ex5_wrt_ib_status_q(0 to 15)); + +latch_ex6_wrt_ib_status : tri_rlmreg_p + generic map (width => ex6_wrt_ib_status_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => mtdp_ex3_to_7_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex6_wrt_ib_status_offset to ex6_wrt_ib_status_offset + ex6_wrt_ib_status_q'length-1), + scout => sov(ex6_wrt_ib_status_offset to ex6_wrt_ib_status_offset + ex6_wrt_ib_status_q'length-1), + din => ex5_wrt_ib_status_gated(0 to 15), + dout => ex6_wrt_ib_status_q(0 to 15) ); + +ex5_ib0_buf0_flushed <= ex5_wrt_ib_status_q(0) and my_ex5_stg_flush; +ex5_ib0_buf1_flushed <= ex5_wrt_ib_status_q(1) and my_ex5_stg_flush; +ex5_ib0_buf2_flushed <= ex5_wrt_ib_status_q(2) and my_ex5_stg_flush; +ex5_ib0_buf3_flushed <= ex5_wrt_ib_status_q(3) and my_ex5_stg_flush; +ex5_ib1_buf0_flushed <= ex5_wrt_ib_status_q(4) and my_ex5_stg_flush; +ex5_ib1_buf1_flushed <= ex5_wrt_ib_status_q(5) and my_ex5_stg_flush; +ex5_ib1_buf2_flushed <= ex5_wrt_ib_status_q(6) and my_ex5_stg_flush; +ex5_ib1_buf3_flushed <= ex5_wrt_ib_status_q(7) and my_ex5_stg_flush; +ex5_ib2_buf0_flushed <= ex5_wrt_ib_status_q(8) and my_ex5_stg_flush; +ex5_ib2_buf1_flushed <= ex5_wrt_ib_status_q(9) and my_ex5_stg_flush; +ex5_ib2_buf2_flushed <= ex5_wrt_ib_status_q(10) and my_ex5_stg_flush; +ex5_ib2_buf3_flushed <= ex5_wrt_ib_status_q(11) and my_ex5_stg_flush; +ex5_ib3_buf0_flushed <= ex5_wrt_ib_status_q(12) and my_ex5_stg_flush; +ex5_ib3_buf1_flushed <= ex5_wrt_ib_status_q(13) and my_ex5_stg_flush; +ex5_ib3_buf2_flushed <= ex5_wrt_ib_status_q(14) and my_ex5_stg_flush; +ex5_ib3_buf3_flushed <= ex5_wrt_ib_status_q(15) and my_ex5_stg_flush; + +ex5_ib0_flushed <= ex5_ib0_buf0_flushed or ex5_ib0_buf1_flushed or ex5_ib0_buf2_flushed or ex5_ib0_buf3_flushed; +ex5_ib1_flushed <= ex5_ib1_buf0_flushed or ex5_ib1_buf1_flushed or ex5_ib1_buf2_flushed or ex5_ib1_buf3_flushed; +ex5_ib2_flushed <= ex5_ib2_buf0_flushed or ex5_ib2_buf1_flushed or ex5_ib2_buf2_flushed or ex5_ib2_buf3_flushed; +ex5_ib3_flushed <= ex5_ib3_buf0_flushed or ex5_ib3_buf1_flushed or ex5_ib3_buf2_flushed or ex5_ib3_buf3_flushed; + +ex6_ib0_buf0_flushed <= ex6_wrt_ib_status_q(0) and my_ex6_stg_flush; +ex6_ib0_buf1_flushed <= ex6_wrt_ib_status_q(1) and my_ex6_stg_flush; +ex6_ib0_buf2_flushed <= ex6_wrt_ib_status_q(2) and my_ex6_stg_flush; +ex6_ib0_buf3_flushed <= ex6_wrt_ib_status_q(3) and my_ex6_stg_flush; +ex6_ib1_buf0_flushed <= ex6_wrt_ib_status_q(4) and my_ex6_stg_flush; +ex6_ib1_buf1_flushed <= ex6_wrt_ib_status_q(5) and my_ex6_stg_flush; +ex6_ib1_buf2_flushed <= ex6_wrt_ib_status_q(6) and my_ex6_stg_flush; +ex6_ib1_buf3_flushed <= ex6_wrt_ib_status_q(7) and my_ex6_stg_flush; +ex6_ib2_buf0_flushed <= ex6_wrt_ib_status_q(8) and my_ex6_stg_flush; +ex6_ib2_buf1_flushed <= ex6_wrt_ib_status_q(9) and my_ex6_stg_flush; +ex6_ib2_buf2_flushed <= ex6_wrt_ib_status_q(10) and my_ex6_stg_flush; +ex6_ib2_buf3_flushed <= ex6_wrt_ib_status_q(11) and my_ex6_stg_flush; +ex6_ib3_buf0_flushed <= ex6_wrt_ib_status_q(12) and my_ex6_stg_flush; +ex6_ib3_buf1_flushed <= ex6_wrt_ib_status_q(13) and my_ex6_stg_flush; +ex6_ib3_buf2_flushed <= ex6_wrt_ib_status_q(14) and my_ex6_stg_flush; +ex6_ib3_buf3_flushed <= ex6_wrt_ib_status_q(15) and my_ex6_stg_flush; + +ex6_ib0_flushed <= ex6_ib0_buf0_flushed or ex6_ib0_buf1_flushed or ex6_ib0_buf2_flushed or ex6_ib0_buf3_flushed; +ex6_ib1_flushed <= ex6_ib1_buf0_flushed or ex6_ib1_buf1_flushed or ex6_ib1_buf2_flushed or ex6_ib1_buf3_flushed; +ex6_ib2_flushed <= ex6_ib2_buf0_flushed or ex6_ib2_buf1_flushed or ex6_ib2_buf2_flushed or ex6_ib2_buf3_flushed; +ex6_ib3_flushed <= ex6_ib3_buf0_flushed or ex6_ib3_buf1_flushed or ex6_ib3_buf2_flushed or ex6_ib3_buf3_flushed; + + +-- ************************************************************************** +-- return credit to node/L2 for the IPC inbox (one credit counter per thread) +-- when inbox status register is written to invalid +-- ************************************************************************** +ib_t0_pop_d <= (ex6_wrt_ib_status_q(0) or ex6_wrt_ib_status_q(1) or ex6_wrt_ib_status_q(2) or ex6_wrt_ib_status_q(3)) and + not my_ex6_stg_flush; + +ib_t1_pop_d <= (ex6_wrt_ib_status_q(4) or ex6_wrt_ib_status_q(5) or ex6_wrt_ib_status_q(6) or ex6_wrt_ib_status_q(7)) and + not my_ex6_stg_flush; + +ib_t2_pop_d <= (ex6_wrt_ib_status_q(8) or ex6_wrt_ib_status_q(9) or ex6_wrt_ib_status_q(10) or ex6_wrt_ib_status_q(11)) and + not my_ex6_stg_flush; + +ib_t3_pop_d <= (ex6_wrt_ib_status_q(12) or ex6_wrt_ib_status_q(13) or ex6_wrt_ib_status_q(14) or ex6_wrt_ib_status_q(15)) and + not my_ex6_stg_flush; + +latch_ipc_ib_t0_pop : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => mtdp_ex3_to_7_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ipc_ib_t0_pop_offset to ipc_ib_t0_pop_offset), + scout => sov(ipc_ib_t0_pop_offset to ipc_ib_t0_pop_offset), + din(0) => ib_t0_pop_d, + dout(0) => ac_an_reld_ditc_pop(0) ); + +latch_ipc_ib_t1_pop : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => mtdp_ex3_to_7_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ipc_ib_t1_pop_offset to ipc_ib_t1_pop_offset), + scout => sov(ipc_ib_t1_pop_offset to ipc_ib_t1_pop_offset), + din(0) => ib_t1_pop_d, + dout(0) => ac_an_reld_ditc_pop(1) ); + +latch_ipc_ib_t2_pop : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => mtdp_ex3_to_7_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ipc_ib_t2_pop_offset to ipc_ib_t2_pop_offset), + scout => sov(ipc_ib_t2_pop_offset to ipc_ib_t2_pop_offset), + din(0) => ib_t2_pop_d, + dout(0) => ac_an_reld_ditc_pop(2) ); + +latch_ipc_ib_t3_pop : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => mtdp_ex3_to_7_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ipc_ib_t3_pop_offset to ipc_ib_t3_pop_offset), + scout => sov(ipc_ib_t3_pop_offset to ipc_ib_t3_pop_offset), + din(0) => ib_t3_pop_d, + dout(0) => ac_an_reld_ditc_pop(3) ); + + + + +ib0_buf0_val_d <= '0' when wrt_ib0_buf0_status='1' else + ex5_ib_val_save_q when ex5_ib0_buf0_flushed='1' else + ex6_ib_val_save_q when ex6_ib0_buf0_flushed='1' else + '1' when ib0_buf0_set_val='1' else + '0' when ib0_buf0_reset_val='1' else + ib0_buf0_val_q; + +ib0_buf1_val_d <= '0' when wrt_ib0_buf1_status='1' else + ex5_ib_val_save_q when ex5_ib0_buf1_flushed='1' else + ex6_ib_val_save_q when ex6_ib0_buf1_flushed='1' else + '1' when ib0_buf1_set_val='1' else + '0' when ib0_buf1_reset_val='1' else + ib0_buf1_val_q; + +ib0_buf2_val_d <= '0' when wrt_ib0_buf2_status='1' else + ex5_ib_val_save_q when ex5_ib0_buf2_flushed='1' else + ex6_ib_val_save_q when ex6_ib0_buf2_flushed='1' else + '1' when ib0_buf2_set_val='1' else + '0' when ib0_buf2_reset_val='1' else + ib0_buf2_val_q; + +ib0_buf3_val_d <= '0' when wrt_ib0_buf3_status='1' else + ex5_ib_val_save_q when ex5_ib0_buf3_flushed='1' else + ex6_ib_val_save_q when ex6_ib0_buf3_flushed='1' else + '1' when ib0_buf3_set_val='1' else + '0' when ib0_buf3_reset_val='1' else + ib0_buf3_val_q; + +ib1_buf0_val_d <= '0' when wrt_ib1_buf0_status='1' else + ex5_ib_val_save_q when ex5_ib1_buf0_flushed='1' else + ex6_ib_val_save_q when ex6_ib1_buf0_flushed='1' else + '1' when ib1_buf0_set_val='1' else + '0' when ib1_buf0_reset_val='1' else + ib1_buf0_val_q; + +ib1_buf1_val_d <= '0' when wrt_ib1_buf1_status='1' else + ex5_ib_val_save_q when ex5_ib1_buf1_flushed='1' else + ex6_ib_val_save_q when ex6_ib1_buf1_flushed='1' else + '1' when ib1_buf1_set_val='1' else + '0' when ib1_buf1_reset_val='1' else + ib1_buf1_val_q; + +ib1_buf2_val_d <= '0' when wrt_ib1_buf2_status='1' else + ex5_ib_val_save_q when ex5_ib1_buf2_flushed='1' else + ex6_ib_val_save_q when ex6_ib1_buf2_flushed='1' else + '1' when ib1_buf2_set_val='1' else + '0' when ib1_buf2_reset_val='1' else + ib1_buf2_val_q; + +ib1_buf3_val_d <= '0' when wrt_ib1_buf3_status='1' else + ex5_ib_val_save_q when ex5_ib1_buf3_flushed='1' else + ex6_ib_val_save_q when ex6_ib1_buf3_flushed='1' else + '1' when ib1_buf3_set_val='1' else + '0' when ib1_buf3_reset_val='1' else + ib1_buf3_val_q; + +ib2_buf0_val_d <= '0' when wrt_ib2_buf0_status='1' else + ex5_ib_val_save_q when ex5_ib2_buf0_flushed='1' else + ex6_ib_val_save_q when ex6_ib2_buf0_flushed='1' else + '1' when ib2_buf0_set_val='1' else + '0' when ib2_buf0_reset_val='1' else + ib2_buf0_val_q; + +ib2_buf1_val_d <= '0' when wrt_ib2_buf1_status='1' else + ex5_ib_val_save_q when ex5_ib2_buf1_flushed='1' else + ex6_ib_val_save_q when ex6_ib2_buf1_flushed='1' else + '1' when ib2_buf1_set_val='1' else + '0' when ib2_buf1_reset_val='1' else + ib2_buf1_val_q; + +ib2_buf2_val_d <= '0' when wrt_ib2_buf2_status='1' else + ex5_ib_val_save_q when ex5_ib2_buf2_flushed='1' else + ex6_ib_val_save_q when ex6_ib2_buf2_flushed='1' else + '1' when ib2_buf2_set_val='1' else + '0' when ib2_buf2_reset_val='1' else + ib2_buf2_val_q; + +ib2_buf3_val_d <= '0' when wrt_ib2_buf3_status='1' else + ex5_ib_val_save_q when ex5_ib2_buf3_flushed='1' else + ex6_ib_val_save_q when ex6_ib2_buf3_flushed='1' else + '1' when ib2_buf3_set_val='1' else + '0' when ib2_buf3_reset_val='1' else + ib2_buf3_val_q; + +ib3_buf0_val_d <= '0' when wrt_ib3_buf0_status='1' else + ex5_ib_val_save_q when ex5_ib3_buf0_flushed='1' else + ex6_ib_val_save_q when ex6_ib3_buf0_flushed='1' else + '1' when ib3_buf0_set_val='1' else + '0' when ib3_buf0_reset_val='1' else + ib3_buf0_val_q; + +ib3_buf1_val_d <= '0' when wrt_ib3_buf1_status='1' else + ex5_ib_val_save_q when ex5_ib3_buf1_flushed='1' else + ex6_ib_val_save_q when ex6_ib3_buf1_flushed='1' else + '1' when ib3_buf1_set_val='1' else + '0' when ib3_buf1_reset_val='1' else + ib3_buf1_val_q; + +ib3_buf2_val_d <= '0' when wrt_ib3_buf2_status='1' else + ex5_ib_val_save_q when ex5_ib3_buf2_flushed='1' else + ex6_ib_val_save_q when ex6_ib3_buf2_flushed='1' else + '1' when ib3_buf2_set_val='1' else + '0' when ib3_buf2_reset_val='1' else + ib3_buf2_val_q; + +ib3_buf3_val_d <= '0' when wrt_ib3_buf3_status='1' else + ex5_ib_val_save_q when ex5_ib3_buf3_flushed='1' else + ex6_ib_val_save_q when ex6_ib3_buf3_flushed='1' else + '1' when ib3_buf3_set_val='1' else + '0' when ib3_buf3_reset_val='1' else + ib3_buf3_val_q; + +ex4_ib_val_save <= gate_and(wrt_ib0_buf0_status, ib0_buf0_val_q) or + gate_and(wrt_ib0_buf1_status, ib0_buf1_val_q) or + gate_and(wrt_ib0_buf2_status, ib0_buf2_val_q) or + gate_and(wrt_ib0_buf3_status, ib0_buf3_val_q) or + gate_and(wrt_ib1_buf0_status, ib1_buf0_val_q) or + gate_and(wrt_ib1_buf1_status, ib1_buf1_val_q) or + gate_and(wrt_ib1_buf2_status, ib1_buf2_val_q) or + gate_and(wrt_ib1_buf3_status, ib1_buf3_val_q) or + gate_and(wrt_ib2_buf0_status, ib2_buf0_val_q) or + gate_and(wrt_ib2_buf1_status, ib2_buf1_val_q) or + gate_and(wrt_ib2_buf2_status, ib2_buf2_val_q) or + gate_and(wrt_ib2_buf3_status, ib2_buf3_val_q) or + gate_and(wrt_ib3_buf0_status, ib3_buf0_val_q) or + gate_and(wrt_ib3_buf1_status, ib3_buf1_val_q) or + gate_and(wrt_ib3_buf2_status, ib3_buf2_val_q) or + gate_and(wrt_ib3_buf3_status, ib3_buf3_val_q); + + +ib_buf_val_act <= reld_data_val or mtdp_ex3_to_7_val; + +latch_ib0_buf0_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ib_buf_val_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib0_buf0_val_offset to ib0_buf0_val_offset), + scout => sov(ib0_buf0_val_offset to ib0_buf0_val_offset), + din(0) => ib0_buf0_val_d, + dout(0) => ib0_buf0_val_q ); + + +latch_ib0_buf1_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ib_buf_val_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib0_buf1_val_offset to ib0_buf1_val_offset), + scout => sov(ib0_buf1_val_offset to ib0_buf1_val_offset), + din(0) => ib0_buf1_val_d, + dout(0) => ib0_buf1_val_q ); + +latch_ib0_buf2_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ib_buf_val_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib0_buf2_val_offset to ib0_buf2_val_offset), + scout => sov(ib0_buf2_val_offset to ib0_buf2_val_offset), + din(0) => ib0_buf2_val_d, + dout(0) => ib0_buf2_val_q ); + +latch_ib0_buf3_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ib_buf_val_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib0_buf3_val_offset to ib0_buf3_val_offset), + scout => sov(ib0_buf3_val_offset to ib0_buf3_val_offset), + din(0) => ib0_buf3_val_d, + dout(0) => ib0_buf3_val_q ); + +latch_ib1_buf0_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ib_buf_val_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib1_buf0_val_offset to ib1_buf0_val_offset), + scout => sov(ib1_buf0_val_offset to ib1_buf0_val_offset), + din(0) => ib1_buf0_val_d, + dout(0) => ib1_buf0_val_q ); + + +latch_ib1_buf1_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ib_buf_val_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib1_buf1_val_offset to ib1_buf1_val_offset), + scout => sov(ib1_buf1_val_offset to ib1_buf1_val_offset), + din(0) => ib1_buf1_val_d, + dout(0) => ib1_buf1_val_q ); + +latch_ib1_buf2_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ib_buf_val_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib1_buf2_val_offset to ib1_buf2_val_offset), + scout => sov(ib1_buf2_val_offset to ib1_buf2_val_offset), + din(0) => ib1_buf2_val_d, + dout(0) => ib1_buf2_val_q ); + +latch_ib1_buf3_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ib_buf_val_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib1_buf3_val_offset to ib1_buf3_val_offset), + scout => sov(ib1_buf3_val_offset to ib1_buf3_val_offset), + din(0) => ib1_buf3_val_d, + dout(0) => ib1_buf3_val_q ); + +latch_ib2_buf0_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ib_buf_val_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib2_buf0_val_offset to ib2_buf0_val_offset), + scout => sov(ib2_buf0_val_offset to ib2_buf0_val_offset), + din(0) => ib2_buf0_val_d, + dout(0) => ib2_buf0_val_q ); + + +latch_ib2_buf1_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ib_buf_val_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib2_buf1_val_offset to ib2_buf1_val_offset), + scout => sov(ib2_buf1_val_offset to ib2_buf1_val_offset), + din(0) => ib2_buf1_val_d, + dout(0) => ib2_buf1_val_q ); + +latch_ib2_buf2_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ib_buf_val_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib2_buf2_val_offset to ib2_buf2_val_offset), + scout => sov(ib2_buf2_val_offset to ib2_buf2_val_offset), + din(0) => ib2_buf2_val_d, + dout(0) => ib2_buf2_val_q ); + +latch_ib2_buf3_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ib_buf_val_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib2_buf3_val_offset to ib2_buf3_val_offset), + scout => sov(ib2_buf3_val_offset to ib2_buf3_val_offset), + din(0) => ib2_buf3_val_d, + dout(0) => ib2_buf3_val_q ); + +latch_ib3_buf0_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ib_buf_val_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib3_buf0_val_offset to ib3_buf0_val_offset), + scout => sov(ib3_buf0_val_offset to ib3_buf0_val_offset), + din(0) => ib3_buf0_val_d, + dout(0) => ib3_buf0_val_q ); + + +latch_ib3_buf1_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ib_buf_val_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib3_buf1_val_offset to ib3_buf1_val_offset), + scout => sov(ib3_buf1_val_offset to ib3_buf1_val_offset), + din(0) => ib3_buf1_val_d, + dout(0) => ib3_buf1_val_q ); + +latch_ib3_buf2_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ib_buf_val_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib3_buf2_val_offset to ib3_buf2_val_offset), + scout => sov(ib3_buf2_val_offset to ib3_buf2_val_offset), + din(0) => ib3_buf2_val_d, + dout(0) => ib3_buf2_val_q ); + +latch_ib3_buf3_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ib_buf_val_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib3_buf3_val_offset to ib3_buf3_val_offset), + scout => sov(ib3_buf3_val_offset to ib3_buf3_val_offset), + din(0) => ib3_buf3_val_d, + dout(0) => ib3_buf3_val_q ); + +latch_ex5_ib_val_save : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => mtdp_ex3_to_7_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex5_ib_val_save_offset to ex5_ib_val_save_offset), + scout => sov(ex5_ib_val_save_offset to ex5_ib_val_save_offset), + din(0) => ex4_ib_val_save, + dout(0) => ex5_ib_val_save_q ); + +latch_ex6_ib_val_save : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => mtdp_ex3_to_7_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex6_ib_val_save_offset to ex6_ib_val_save_offset), + scout => sov(ex6_ib_val_save_offset to ex6_ib_val_save_offset), + din(0) => ex5_ib_val_save_q, + dout(0) => ex6_ib_val_save_q ); + + +ib_empty_d(0) <= not (ib0_buf0_val_q or ib0_buf1_val_q or ib0_buf2_val_q or ib0_buf3_val_q); +ib_empty_d(1) <= not (ib1_buf0_val_q or ib1_buf1_val_q or ib1_buf2_val_q or ib1_buf3_val_q); +ib_empty_d(2) <= not (ib2_buf0_val_q or ib2_buf1_val_q or ib2_buf2_val_q or ib2_buf3_val_q); +ib_empty_d(3) <= not (ib3_buf0_val_q or ib3_buf1_val_q or ib3_buf2_val_q or ib3_buf3_val_q); + +quiesce_d(0) <= ib_empty_d(0) and not (ob0_buf0_status_q(0) or ob0_buf1_status_q(0) or ob0_buf2_status_q(0) or ob0_buf3_status_q(0)); +quiesce_d(1) <= ib_empty_d(1) and not (ob1_buf0_status_q(0) or ob1_buf1_status_q(0) or ob1_buf2_status_q(0) or ob1_buf3_status_q(0)); +quiesce_d(2) <= ib_empty_d(2) and not (ob2_buf0_status_q(0) or ob2_buf1_status_q(0) or ob2_buf2_status_q(0) or ob2_buf3_status_q(0)); +quiesce_d(3) <= ib_empty_d(3) and not (ob3_buf0_status_q(0) or ob3_buf1_status_q(0) or ob3_buf2_status_q(0) or ob3_buf3_status_q(0)); + +latch_ib_empty : tri_rlmreg_p + generic map (width => ib_empty_d'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib_empty_offset to ib_empty_offset + ib_empty_d'length-1), + scout => sov(ib_empty_offset to ib_empty_offset + ib_empty_d'length-1), + din => ib_empty_d(0 to 3), + dout => bx_ib_empty(0 to 3) ); + +latch_quiesce : tri_rlmreg_p + generic map (width => quiesce_d'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(quiesce_offset to quiesce_offset + quiesce_d'length-1), + scout => sov(quiesce_offset to quiesce_offset + quiesce_d'length-1), + din => quiesce_d(0 to 3), + dout => bx_xu_quiesce(0 to 3) ); + + + +--********************************************************************************************** +-- increment inbox buffer read pointer when the status register is written in-valid +-- there is one buffer pointer per thread +-- the entry pointer gets updated in ex3 even though the status reg is written in ex4 +-- this allows the logic to use the latched version of the entry pointer +--********************************************************************************************** + +ib0_decr_ptr <= (ex4_ib0_flushed & ex5_ib0_flushed & ex6_ib0_flushed = "100") or + (ex4_ib0_flushed & ex5_ib0_flushed & ex6_ib0_flushed = "010") or + (ex4_ib0_flushed & ex5_ib0_flushed & ex6_ib0_flushed = "001"); + +ib0_decr_ptr_by2 <= (ex4_ib0_flushed & ex5_ib0_flushed & ex6_ib0_flushed = "110") or + (ex4_ib0_flushed & ex5_ib0_flushed & ex6_ib0_flushed = "101") or + (ex4_ib0_flushed & ex5_ib0_flushed & ex6_ib0_flushed = "011"); + +ib0_decr_ptr_by3 <= ex4_ib0_flushed & ex5_ib0_flushed & ex6_ib0_flushed = "111"; + +ib0_rd_entry_ptr_d <= std_ulogic_vector(unsigned(ib0_rd_entry_ptr_q) + 1) when ib0_incr_ptr='1' else + std_ulogic_vector(unsigned(ib0_rd_entry_ptr_q) - 1) when ib0_decr_ptr='1' else + std_ulogic_vector(unsigned(ib0_rd_entry_ptr_q) - 2) when ib0_decr_ptr_by2='1' else + std_ulogic_vector(unsigned(ib0_rd_entry_ptr_q) - 3) when ib0_decr_ptr_by3='1' else + ib0_rd_entry_ptr_q(0 to 1); + +ib1_decr_ptr <= (ex4_ib1_flushed & ex5_ib1_flushed & ex6_ib1_flushed = "100") or + (ex4_ib1_flushed & ex5_ib1_flushed & ex6_ib1_flushed = "010") or + (ex4_ib1_flushed & ex5_ib1_flushed & ex6_ib1_flushed = "001"); + +ib1_decr_ptr_by2 <= (ex4_ib1_flushed & ex5_ib1_flushed & ex6_ib1_flushed = "110") or + (ex4_ib1_flushed & ex5_ib1_flushed & ex6_ib1_flushed = "101") or + (ex4_ib1_flushed & ex5_ib1_flushed & ex6_ib1_flushed = "011"); + +ib1_decr_ptr_by3 <= ex4_ib1_flushed & ex5_ib1_flushed & ex6_ib1_flushed = "111"; + +ib1_rd_entry_ptr_d <= std_ulogic_vector(unsigned(ib1_rd_entry_ptr_q) + 1) when ib1_incr_ptr='1' else + std_ulogic_vector(unsigned(ib1_rd_entry_ptr_q) - 1) when ib1_decr_ptr='1' else + std_ulogic_vector(unsigned(ib1_rd_entry_ptr_q) - 2) when ib1_decr_ptr_by2='1' else + std_ulogic_vector(unsigned(ib1_rd_entry_ptr_q) - 3) when ib1_decr_ptr_by3='1' else + ib1_rd_entry_ptr_q(0 to 1); + +ib2_decr_ptr <= (ex4_ib2_flushed & ex5_ib2_flushed & ex6_ib2_flushed = "100") or + (ex4_ib2_flushed & ex5_ib2_flushed & ex6_ib2_flushed = "010") or + (ex4_ib2_flushed & ex5_ib2_flushed & ex6_ib2_flushed = "001"); + +ib2_decr_ptr_by2 <= (ex4_ib2_flushed & ex5_ib2_flushed & ex6_ib2_flushed = "110") or + (ex4_ib2_flushed & ex5_ib2_flushed & ex6_ib2_flushed = "101") or + (ex4_ib2_flushed & ex5_ib2_flushed & ex6_ib2_flushed = "011"); + +ib2_decr_ptr_by3 <= ex4_ib2_flushed & ex5_ib2_flushed & ex6_ib2_flushed = "111"; + +ib2_rd_entry_ptr_d <= std_ulogic_vector(unsigned(ib2_rd_entry_ptr_q) + 1) when ib2_incr_ptr='1' else + std_ulogic_vector(unsigned(ib2_rd_entry_ptr_q) - 1) when ib2_decr_ptr='1' else + std_ulogic_vector(unsigned(ib2_rd_entry_ptr_q) - 2) when ib2_decr_ptr_by2='1' else + std_ulogic_vector(unsigned(ib2_rd_entry_ptr_q) - 3) when ib2_decr_ptr_by3='1' else + ib2_rd_entry_ptr_q(0 to 1); + +ib3_decr_ptr <= (ex4_ib3_flushed & ex5_ib3_flushed & ex6_ib3_flushed = "100") or + (ex4_ib3_flushed & ex5_ib3_flushed & ex6_ib3_flushed = "010") or + (ex4_ib3_flushed & ex5_ib3_flushed & ex6_ib3_flushed = "001"); + +ib3_decr_ptr_by2 <= (ex4_ib3_flushed & ex5_ib3_flushed & ex6_ib3_flushed = "110") or + (ex4_ib3_flushed & ex5_ib3_flushed & ex6_ib3_flushed = "101") or + (ex4_ib3_flushed & ex5_ib3_flushed & ex6_ib3_flushed = "011"); + +ib3_decr_ptr_by3 <= ex4_ib3_flushed & ex5_ib3_flushed & ex6_ib3_flushed = "111"; + +ib3_rd_entry_ptr_d <= std_ulogic_vector(unsigned(ib3_rd_entry_ptr_q) + 1) when ib3_incr_ptr='1' else + std_ulogic_vector(unsigned(ib3_rd_entry_ptr_q) - 1) when ib3_decr_ptr='1' else + std_ulogic_vector(unsigned(ib3_rd_entry_ptr_q) - 2) when ib3_decr_ptr_by2='1' else + std_ulogic_vector(unsigned(ib3_rd_entry_ptr_q) - 3) when ib3_decr_ptr_by3='1' else + ib3_rd_entry_ptr_q(0 to 1); + +latch_ib0_rd_entry_ptr : tri_rlmreg_p + generic map (width => ib0_rd_entry_ptr_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => mtdp_ex3_to_7_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib0_rd_entry_ptr_offset to ib0_rd_entry_ptr_offset + ib0_rd_entry_ptr_q'length-1), + scout => sov(ib0_rd_entry_ptr_offset to ib0_rd_entry_ptr_offset + ib0_rd_entry_ptr_q'length-1), + din => ib0_rd_entry_ptr_d(0 to 1), + dout => ib0_rd_entry_ptr_q(0 to 1) ); + +latch_ib1_rd_entry_ptr : tri_rlmreg_p + generic map (width => ib1_rd_entry_ptr_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => mtdp_ex3_to_7_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib1_rd_entry_ptr_offset to ib1_rd_entry_ptr_offset + ib1_rd_entry_ptr_q'length-1), + scout => sov(ib1_rd_entry_ptr_offset to ib1_rd_entry_ptr_offset + ib1_rd_entry_ptr_q'length-1), + din => ib1_rd_entry_ptr_d(0 to 1), + dout => ib1_rd_entry_ptr_q(0 to 1) ); + +latch_ib2_rd_entry_ptr : tri_rlmreg_p + generic map (width => ib2_rd_entry_ptr_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => mtdp_ex3_to_7_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib2_rd_entry_ptr_offset to ib2_rd_entry_ptr_offset + ib2_rd_entry_ptr_q'length-1), + scout => sov(ib2_rd_entry_ptr_offset to ib2_rd_entry_ptr_offset + ib2_rd_entry_ptr_q'length-1), + din => ib2_rd_entry_ptr_d(0 to 1), + dout => ib2_rd_entry_ptr_q(0 to 1) ); + +latch_ib3_rd_entry_ptr : tri_rlmreg_p + generic map (width => ib3_rd_entry_ptr_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => mtdp_ex3_to_7_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib3_rd_entry_ptr_offset to ib3_rd_entry_ptr_offset + ib3_rd_entry_ptr_q'length-1), + scout => sov(ib3_rd_entry_ptr_offset to ib3_rd_entry_ptr_offset + ib3_rd_entry_ptr_q'length-1), + din => ib3_rd_entry_ptr_d(0 to 1), + dout => ib3_rd_entry_ptr_q(0 to 1) ); + +latch_ib0_rd_entry_ptr_dly : tri_rlmreg_p + generic map (width => ib0_rd_entry_ptr_dly_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => mtdp_ex3_to_7_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib0_rd_entry_ptr_dly_offset to ib0_rd_entry_ptr_dly_offset + ib0_rd_entry_ptr_dly_q'length-1), + scout => sov(ib0_rd_entry_ptr_dly_offset to ib0_rd_entry_ptr_dly_offset + ib0_rd_entry_ptr_dly_q'length-1), + din => ib0_rd_entry_ptr_q(0 to 1), + dout => ib0_rd_entry_ptr_dly_q(0 to 1) ); + +latch_ib1_rd_entry_ptr_dly : tri_rlmreg_p + generic map (width => ib1_rd_entry_ptr_dly_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => mtdp_ex3_to_7_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib1_rd_entry_ptr_dly_offset to ib1_rd_entry_ptr_dly_offset + ib1_rd_entry_ptr_dly_q'length-1), + scout => sov(ib1_rd_entry_ptr_dly_offset to ib1_rd_entry_ptr_dly_offset + ib1_rd_entry_ptr_dly_q'length-1), + din => ib1_rd_entry_ptr_q(0 to 1), + dout => ib1_rd_entry_ptr_dly_q(0 to 1) ); + +latch_ib2_rd_entry_ptr_dly : tri_rlmreg_p + generic map (width => ib2_rd_entry_ptr_dly_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => mtdp_ex3_to_7_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib2_rd_entry_ptr_dly_offset to ib2_rd_entry_ptr_dly_offset + ib2_rd_entry_ptr_dly_q'length-1), + scout => sov(ib2_rd_entry_ptr_dly_offset to ib2_rd_entry_ptr_dly_offset + ib2_rd_entry_ptr_dly_q'length-1), + din => ib2_rd_entry_ptr_q(0 to 1), + dout => ib2_rd_entry_ptr_dly_q(0 to 1) ); + +latch_ib3_rd_entry_ptr_dly : tri_rlmreg_p + generic map (width => ib3_rd_entry_ptr_dly_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => mtdp_ex3_to_7_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib3_rd_entry_ptr_dly_offset to ib3_rd_entry_ptr_dly_offset + ib3_rd_entry_ptr_dly_q'length-1), + scout => sov(ib3_rd_entry_ptr_dly_offset to ib3_rd_entry_ptr_dly_offset + ib3_rd_entry_ptr_dly_q'length-1), + din => ib3_rd_entry_ptr_q(0 to 1), + dout => ib3_rd_entry_ptr_dly_q(0 to 1) ); + +--********************************************************************************************** +-- use thread id to select one of the inbox read pointers to use in the inbox array read address +--********************************************************************************************** + +with ex2_ipc_thrd_q(0 to 1) select + ib_rd_entry_ptr(0 to 1) <= ib0_rd_entry_ptr_d(0 to 1) when "00", + ib1_rd_entry_ptr_d(0 to 1) when "01", + ib2_rd_entry_ptr_d(0 to 1) when "10", + ib3_rd_entry_ptr_d(0 to 1) when others; + +ib_ary_rd_addr(0 to 5) <= ex2_ipc_thrd_q(0 to 1) & ib_rd_entry_ptr(0 to 1) & xu_bx_ex2_ipc_ba(1 to 2); + + +--**************************************************************************** +-- inbox error inject +--**************************************************************************** + +latch_ib_err_inj : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib_err_inj_offset to ib_err_inj_offset), + scout => sov(ib_err_inj_offset to ib_err_inj_offset), + din(0) => pc_bx_inj_inbox_ecc, + dout(0) => ib_err_inj_q ); + +lat_reld_data_0 <= lat_reld_data(0) xor ib_err_inj_q; + +--**************************************************************************** +-- inbox array +--**************************************************************************** + +ib_array: entity tri.tri_64x42_4w_1r1w(tri_64x42_4w_1r1w) + generic map ( expand_type => expand_type ) + port map( +-- functional ports + wr_way => ib_ary_wen(0 to 3), + wr_adr => ib_ary_wrt_addr(0 to 5), + + di(0) => lat_reld_data_0, + di(1 to 31) => lat_reld_data(1 to 31), + di(32 to 38) => ib_datain_ecc0(0 to 6), + di(39 to 41) => "000", + + di(42 to 73) => lat_reld_data(32 to 63), + di(74 to 80) => ib_datain_ecc1(0 to 6), + di(81 to 83) => "000", + + di(84 to 115) => lat_reld_data(64 to 95), + di(116 to 122) => ib_datain_ecc2(0 to 6), + di(123 to 125) => "000", + + di(126 to 157) => lat_reld_data(96 to 127), + di(158 to 164) => ib_datain_ecc3(0 to 6), + di(165 to 167) => "000", + + rd0_adr => ib_ary_rd_addr(0 to 5), + + do0(0 to 31) => ib_rd_data(0 to 31), + do0(32 to 38) => ib_rd_data_ecc0(0 to 6), + do0(39 to 41) => unused(12 to 14), + + do0(42 to 73) => ib_rd_data(32 to 63), + do0(74 to 80) => ib_rd_data_ecc1(0 to 6), + do0(81 to 83) => unused(15 to 17), + + do0(84 to 115) => ib_rd_data(64 to 95), + do0(116 to 122) => ib_rd_data_ecc2(0 to 6), + do0(123 to 125) => unused(18 to 20), + + do0(126 to 157) => ib_rd_data(96 to 127), + do0(158 to 164) => ib_rd_data_ecc3(0 to 6), + do0(165 to 167) => unused(21 to 23), + + -- ABIST + abist_di => abist_di_0, + abist_bw_odd => abist_g8t_bw_1, + abist_bw_even => abist_g8t_bw_0, + abist_wr_adr => abist_waddr_0(4 to 9), + wr_abst_act => abist_g8t_wenb, + abist_rd0_adr => abist_raddr_0(4 to 9), + rd0_abst_act => abist_g8t1p_renb_0, + tc_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc, + abist_ena_1 => pc_bx_abist_ena_dc, + abist_g8t_rd0_comp_ena => abist_wl64_comp_ena, + abist_raw_dc_b => pc_bx_abist_raw_dc_b, + obs0_abist_cmp => abist_g8t_dcomp, + + -- BOLT-ON + lcb_bolt_sl_thold_0 => bolt_sl_thold_0, + pc_bo_enable_2 => bolt_enable_2, + pc_bo_reset => pc_bx_bo_reset, + pc_bo_unload => pc_bx_bo_unload, + pc_bo_repair => pc_bx_bo_repair, + pc_bo_shdata => pc_bx_bo_shdata, + pc_bo_select => pc_bx_bo_select(2 to 3), + bo_pc_failout => bx_pc_bo_fail(2 to 3), + bo_pc_diagloop => bx_pc_bo_diagout(2 to 3), + tri_lcb_mpw1_dc_b => mpw1_dc_b, + tri_lcb_mpw2_dc_b => mpw2_dc_b, + tri_lcb_delay_lclkr_dc => delay_lclkr_dc, + tri_lcb_clkoff_dc_b => clkoff_dc_b, + tri_lcb_act_dis_dc => tidn, + +-- pervasive ports + gnd => gnd, + vdd => vdd, + vcs => vcs, + nclk => nclk, + rd0_act => ex2_mfdp_val_q, + wr_act => reld_data_val, + sg_0 => sg_0, + abst_sl_thold_0 => abst_sl_thold_0, + ary_nsl_thold_0 => ary_slp_nsl_thold_0, + time_sl_thold_0 => time_sl_thold_0, + repr_sl_thold_0 => repr_sl_thold_0, + scan_dis_dc_b => an_ac_scan_dis_dc_b, + scan_diag_dc => an_ac_scan_diag_dc, + ccflush_dc => pc_bx_ccflush_dc, + + ary0_clkoff_dc_b => ary0_clkoff_dc_b, + ary0_d_mode_dc => ary0_d_mode_dc, + ary0_mpw1_dc_b => ary0_mpw1_dc_b_v, + ary0_mpw2_dc_b => ary0_mpw2_dc_b, + ary0_delay_lclkr_dc => ary0_delay_lclkr_dc_v, + + ary1_clkoff_dc_b => ary1_clkoff_dc_b, + ary1_d_mode_dc => ary1_d_mode_dc, + ary1_mpw1_dc_b => ary1_mpw1_dc_b_v, + ary1_mpw2_dc_b => ary1_mpw2_dc_b, + ary1_delay_lclkr_dc => ary1_delay_lclkr_dc_v, + + abst_scan_in => ob_abst_scan_out, + time_scan_in => ob_time_scan_out, + repr_scan_in => ob_repr_scan_out, + abst_scan_out => ib_abst_scan_out, + time_scan_out => ib_time_scan_out, + repr_scan_out => int_repr_scan_out +); + + + + +ib_do_eccgen0: entity work.xuq_eccgen(xuq_eccgen) + generic map ( regsize => 32 ) + port map(din(0 to 31) => ex4_inbox_data(0 to 31), + din(32 to 38) => ex4_ib_data_ecc0, + syn => ib_rd_data_nsyn0 ); + +ib_do_eccgen1: entity work.xuq_eccgen(xuq_eccgen) + generic map ( regsize => 32 ) + port map(din(0 to 31) => ex4_inbox_data(32 to 63), + din(32 to 38) => ex4_ib_data_ecc1, + syn => ib_rd_data_nsyn1 ); + +ib_do_eccgen2: entity work.xuq_eccgen(xuq_eccgen) + generic map ( regsize => 32 ) + port map(din(0 to 31) => ex4_inbox_data(64 to 95), + din(32 to 38) => ex4_ib_data_ecc2, + syn => ib_rd_data_nsyn2 ); + +ib_do_eccgen3: entity work.xuq_eccgen(xuq_eccgen) + generic map ( regsize => 32 ) + port map(din(0 to 31) => ex4_inbox_data(96 to 127), + din(32 to 38) => ex4_ib_data_ecc3, + syn => ib_rd_data_nsyn3 ); + + +ib_di_eccchk0: entity work.xuq_eccchk(xuq_eccchk) + generic map ( regsize => 32 ) + port map(din => ex4_inbox_data(0 to 31), + EnCorr => '1', + NSyn => ib_rd_data_nsyn0, + Corrd => ib_rd_data_cor(0 to 31), + sbe => ib_ary_sbe(0), + ue => ib_ary_ue(0) ); + +ib_di_eccchk1: entity work.xuq_eccchk(xuq_eccchk) + generic map ( regsize => 32 ) + port map(din => ex4_inbox_data(32 to 63), + EnCorr => '1', + NSyn => ib_rd_data_nsyn1, + Corrd => ib_rd_data_cor(32 to 63), + sbe => ib_ary_sbe(1), + ue => ib_ary_ue(1) ); + +ib_di_eccchk2: entity work.xuq_eccchk(xuq_eccchk) + generic map ( regsize => 32 ) + port map(din => ex4_inbox_data(64 to 95), + EnCorr => '1', + NSyn => ib_rd_data_nsyn2, + Corrd => ib_rd_data_cor(64 to 95), + sbe => ib_ary_sbe(2), + ue => ib_ary_ue(2) ); + +ib_di_eccchk3: entity work.xuq_eccchk(xuq_eccchk) + generic map ( regsize => 32 ) + port map(din => ex4_inbox_data(96 to 127), + EnCorr => '1', + NSyn => ib_rd_data_nsyn3, + Corrd => ib_rd_data_cor(96 to 127), + sbe => ib_ary_sbe(3), + ue => ib_ary_ue(3) ); + +latch_ex5_inbox_data_cor : tri_rlmreg_p + generic map (width => ex5_inbox_data_cor'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ex4_mfdp_val_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex5_inbox_data_cor_offset to ex5_inbox_data_cor_offset + ex5_inbox_data_cor'length-1), + scout => sov(ex5_inbox_data_cor_offset to ex5_inbox_data_cor_offset + ex5_inbox_data_cor'length-1), + din => ib_rd_data_cor(0 to 127), + dout => ex5_inbox_data_cor(0 to 127) ); + +latch_ib_ary_sbe : tri_rlmreg_p + generic map (width => ib_ary_sbe_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ex4_mfdp_val_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib_ary_sbe_offset to ib_ary_sbe_offset + ib_ary_sbe_q'length-1), + scout => sov(ib_ary_sbe_offset to ib_ary_sbe_offset + ib_ary_sbe_q'length-1), + din => ib_ary_sbe(0 to 3), + dout => ib_ary_sbe_q(0 to 3) ); + +latch_ib_ary_ue : tri_rlmreg_p + generic map (width => ib_ary_ue_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ex4_mfdp_val_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib_ary_ue_offset to ib_ary_ue_offset + ib_ary_ue_q'length-1), + scout => sov(ib_ary_ue_offset to ib_ary_ue_offset + ib_ary_ue_q'length-1), + din => ib_ary_ue(0 to 3), + dout => ib_ary_ue_q(0 to 3) ); + +ib_ary_sbe_or <= (ib_ary_sbe_q(0) or ib_ary_sbe_q(1) or ib_ary_sbe_q(2) or ib_ary_sbe_q(3)) and ex5_ib_ecc_val; + +ib_ary_ue_or <= (ib_ary_ue_q(0) or ib_ary_ue_q(1) or ib_ary_ue_q(2) or ib_ary_ue_q(3)) and ex5_ib_ecc_val; + +-- latch read address(0:1) (thread select bits) to use for parity error detection + + +latch_inbox_ecc_err : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dp_op_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(inbox_ecc_err_offset to inbox_ecc_err_offset), + scout => sov(inbox_ecc_err_offset to inbox_ecc_err_offset), + din(0) => ib_ary_sbe_or, + dout(0) => inbox_ecc_err_q ); + +latch_inbox_ue : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dp_op_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(inbox_ue_offset to inbox_ue_offset), + scout => sov(inbox_ue_offset to inbox_ue_offset), + din(0) => ib_ary_ue_or, + dout(0) => inbox_ue_q ); + + inbox_err_rpt : entity tri.tri_direct_err_rpt + generic map + ( width => 2 + , expand_type => expand_type + ) + port map + ( vd => vdd + , gd => gnd + , err_in(0) => inbox_ecc_err_q + , err_in(1) => inbox_ue_q + , err_out(0) => bx_pc_err_inbox_ecc + , err_out(1) => bx_pc_err_inbox_ue + ); + +--**************************************************************************** +-- use read pointer to select status register for each thread +--**************************************************************************** + +with ib0_rd_entry_ptr_q(0 to 1) select + ib0_rd_val_reg <= (ib0_buf0_val_q and not ib0_buf0_reset_val) when "00", + (ib0_buf1_val_q and not ib0_buf1_reset_val) when "01", + (ib0_buf2_val_q and not ib0_buf2_reset_val) when "10", + (ib0_buf3_val_q and not ib0_buf3_reset_val) when others; + +with ib1_rd_entry_ptr_q(0 to 1) select + ib1_rd_val_reg <= (ib1_buf0_val_q and not ib1_buf0_reset_val) when "00", + (ib1_buf1_val_q and not ib1_buf1_reset_val) when "01", + (ib1_buf2_val_q and not ib1_buf2_reset_val) when "10", + (ib1_buf3_val_q and not ib1_buf3_reset_val) when others; + +with ib2_rd_entry_ptr_q(0 to 1) select + ib2_rd_val_reg <= (ib2_buf0_val_q and not ib2_buf0_reset_val) when "00", + (ib2_buf1_val_q and not ib2_buf1_reset_val) when "01", + (ib2_buf2_val_q and not ib2_buf2_reset_val) when "10", + (ib2_buf3_val_q and not ib2_buf3_reset_val) when others; + +with ib3_rd_entry_ptr_q(0 to 1) select + ib3_rd_val_reg <= (ib3_buf0_val_q and not ib3_buf0_reset_val) when "00", + (ib3_buf1_val_q and not ib3_buf1_reset_val) when "01", + (ib3_buf2_val_q and not ib3_buf2_reset_val) when "10", + (ib3_buf3_val_q and not ib3_buf3_reset_val) when others; + + +--**************************************************************************** +-- stage thread and ba to ex4 for mfdp status reg mux controls +--**************************************************************************** + + +latch_ex4_ipc_thrd : tri_rlmreg_p + generic map (width => ex4_ipc_thrd_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dp_op_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_ipc_thrd_offset to ex4_ipc_thrd_offset + ex4_ipc_thrd_q'length-1), + scout => sov(ex4_ipc_thrd_offset to ex4_ipc_thrd_offset + ex4_ipc_thrd_q'length-1), + din => ex3_ipc_thrd_q(0 to 1), + dout => ex4_ipc_thrd_q(0 to 1) ); + +latch_ex5_ipc_thrd : tri_rlmreg_p + generic map (width => ex5_ipc_thrd_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dp_op_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex5_ipc_thrd_offset to ex5_ipc_thrd_offset + ex5_ipc_thrd_q'length-1), + scout => sov(ex5_ipc_thrd_offset to ex5_ipc_thrd_offset + ex5_ipc_thrd_q'length-1), + din => ex4_ipc_thrd_q(0 to 1), + dout => ex5_ipc_thrd_q(0 to 1) ); + +latch_ex6_ipc_thrd : tri_rlmreg_p + generic map (width => ex6_ipc_thrd_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dp_op_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex6_ipc_thrd_offset to ex6_ipc_thrd_offset + ex6_ipc_thrd_q'length-1), + scout => sov(ex6_ipc_thrd_offset to ex6_ipc_thrd_offset + ex6_ipc_thrd_q'length-1), + din => ex5_ipc_thrd_q(0 to 1), + dout => ex6_ipc_thrd_q(0 to 1) ); + +latch_ex4_ipc_ba : tri_rlmreg_p + generic map (width => ex4_ipc_ba_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dp_op_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_ipc_ba_offset to ex4_ipc_ba_offset + ex4_ipc_ba_q'length-1), + scout => sov(ex4_ipc_ba_offset to ex4_ipc_ba_offset + ex4_ipc_ba_q'length-1), + din => ex3_ipc_ba_q(0 to 4), + dout => ex4_ipc_ba_q(0 to 4) ); + +latch_ex4_ipc_sz : tri_rlmreg_p + generic map (width => ex4_ipc_sz_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dp_op_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_ipc_sz_offset to ex4_ipc_sz_offset + ex4_ipc_sz_q'length-1), + scout => sov(ex4_ipc_sz_offset to ex4_ipc_sz_offset + ex4_ipc_sz_q'length-1), + din => ex3_ipc_sz_q(0 to 1), + dout => ex4_ipc_sz_q(0 to 1) ); + +--**************************************************************************** +-- use thread id to select which threads status reg to return +--**************************************************************************** + +with ex4_ipc_thrd_q(0 to 1) select + ex4_ib_rd_status_reg <= ib0_rd_val_reg when "00", + ib1_rd_val_reg when "01", + ib2_rd_val_reg when "10", + ib3_rd_val_reg when others; + + +--**************************************************************************** +-- return data to the processor on a mfdp op +--**************************************************************************** +ex3_data_w0_sel(0) <= (ex3_ipc_sz_q="00" and ex3_ipc_ba_q(3 to 4)="00" and ex3_ipc_ba_q(0)='0') or ex3_ipc_sz_q="10" or + (ex3_ipc_sz_q="01" and ex3_ipc_ba_q(3)='0'); +ex3_data_w0_sel(1) <= ex3_ipc_sz_q="00" and ex3_ipc_ba_q(3 to 4)="01"; +ex3_data_w0_sel(2) <= (ex3_ipc_sz_q="00" and ex3_ipc_ba_q(3 to 4)="10") or + (ex3_ipc_sz_q="01" and ex3_ipc_ba_q(3)='1'); +ex3_data_w0_sel(3) <= ex3_ipc_sz_q="00" and ex3_ipc_ba_q(3 to 4)="11"; +ex3_data_sel_status <= ex3_ipc_ba_q = "10000"; + +ex3_inbox_data(0 to 31) <= gate_and(ex3_data_w0_sel(0), ib_rd_data(0 to 31)) or + gate_and(ex3_data_w0_sel(1), ib_rd_data(32 to 63)) or + gate_and(ex3_data_w0_sel(2), ib_rd_data(64 to 95)) or + gate_and(ex3_data_w0_sel(3), ib_rd_data(96 to 127)) or + gate_and(ex3_data_sel_status, x"0000000" & "000" & ex4_ib_rd_status_reg); + +ex3_ib_data_ecc0(0 to 6)<= gate_and(ex3_data_w0_sel(0), ib_rd_data_ecc0(0 to 6)) or + gate_and(ex3_data_w0_sel(1), ib_rd_data_ecc1(0 to 6)) or + gate_and(ex3_data_w0_sel(2), ib_rd_data_ecc2(0 to 6)) or + gate_and(ex3_data_w0_sel(3), ib_rd_data_ecc3(0 to 6)); + +ex3_data_w1_sel(0) <= ex3_ipc_sz_q="00" and ex3_ipc_ba_q(3 to 4)="00" and ex3_ipc_ba_q(0)='0'; +ex3_data_w1_sel(1) <= (ex3_ipc_sz_q="00" and ex3_ipc_ba_q(3 to 4)="01") or ex3_ipc_sz_q="10" or + (ex3_ipc_sz_q="01" and ex3_ipc_ba_q(3)='0'); +ex3_data_w1_sel(2) <= ex3_ipc_sz_q="00" and ex3_ipc_ba_q(3 to 4)="10"; +ex3_data_w1_sel(3) <= (ex3_ipc_sz_q="00" and ex3_ipc_ba_q(3 to 4)="11") or + (ex3_ipc_sz_q="01" and ex3_ipc_ba_q(3)='1'); + +ex3_inbox_data(32 to 63) <= gate_and(ex3_data_w1_sel(0), ib_rd_data(0 to 31)) or + gate_and(ex3_data_w1_sel(1), ib_rd_data(32 to 63)) or + gate_and(ex3_data_w1_sel(2), ib_rd_data(64 to 95)) or + gate_and(ex3_data_w1_sel(3), ib_rd_data(96 to 127)) or + gate_and(ex3_data_sel_status, x"0000000" & "000" & ex4_ib_rd_status_reg); + +ex3_ib_data_ecc1(0 to 6)<= gate_and(ex3_data_w1_sel(0), ib_rd_data_ecc0(0 to 6)) or + gate_and(ex3_data_w1_sel(1), ib_rd_data_ecc1(0 to 6)) or + gate_and(ex3_data_w1_sel(2), ib_rd_data_ecc2(0 to 6)) or + gate_and(ex3_data_w1_sel(3), ib_rd_data_ecc3(0 to 6)); + +ex3_data_w2_sel(0) <= (ex3_ipc_sz_q="00" and ex3_ipc_ba_q(3 to 4)="00" and ex3_ipc_ba_q(0)='0') or + (ex3_ipc_sz_q="01" and ex3_ipc_ba_q(3)='0'); +ex3_data_w2_sel(1) <= ex3_ipc_sz_q="00" and ex3_ipc_ba_q(3 to 4)="01"; +ex3_data_w2_sel(2) <= (ex3_ipc_sz_q="00" and ex3_ipc_ba_q(3 to 4)="10") or ex3_ipc_sz_q="10" or + (ex3_ipc_sz_q="01" and ex3_ipc_ba_q(3)='1'); +ex3_data_w2_sel(3) <= ex3_ipc_sz_q="00" and ex3_ipc_ba_q(3 to 4)="11"; + +ex3_inbox_data(64 to 95) <= gate_and(ex3_data_w2_sel(0), ib_rd_data(0 to 31)) or + gate_and(ex3_data_w2_sel(1), ib_rd_data(32 to 63)) or + gate_and(ex3_data_w2_sel(2), ib_rd_data(64 to 95)) or + gate_and(ex3_data_w2_sel(3), ib_rd_data(96 to 127)) or + gate_and(ex3_data_sel_status, x"0000000" & "000" & ex4_ib_rd_status_reg); + +ex3_ib_data_ecc2(0 to 6)<= gate_and(ex3_data_w2_sel(0), ib_rd_data_ecc0(0 to 6)) or + gate_and(ex3_data_w2_sel(1), ib_rd_data_ecc1(0 to 6)) or + gate_and(ex3_data_w2_sel(2), ib_rd_data_ecc2(0 to 6)) or + gate_and(ex3_data_w2_sel(3), ib_rd_data_ecc3(0 to 6)); + +ex3_data_w3_sel(0) <= ex3_ipc_sz_q="00" and ex3_ipc_ba_q(3 to 4)="00" and ex3_ipc_ba_q(0)='0'; +ex3_data_w3_sel(1) <= (ex3_ipc_sz_q="00" and ex3_ipc_ba_q(3 to 4)="01") or + (ex3_ipc_sz_q="01" and ex3_ipc_ba_q(3)='0'); +ex3_data_w3_sel(2) <= ex3_ipc_sz_q="00" and ex3_ipc_ba_q(3 to 4)="10"; +ex3_data_w3_sel(3) <= (ex3_ipc_sz_q="00" and ex3_ipc_ba_q(3 to 4)="11") or ex3_ipc_sz_q="10" or + (ex3_ipc_sz_q="01" and ex3_ipc_ba_q(3)='1'); + +ex3_inbox_data(96 to 127) <= gate_and(ex3_data_w3_sel(0), ib_rd_data(0 to 31)) or + gate_and(ex3_data_w3_sel(1), ib_rd_data(32 to 63)) or + gate_and(ex3_data_w3_sel(2), ib_rd_data(64 to 95)) or + gate_and(ex3_data_w3_sel(3), ib_rd_data(96 to 127)) or + gate_and(ex3_data_sel_status, x"0000000" & "000" & ex4_ib_rd_status_reg); + +ex3_ib_data_ecc3(0 to 6)<= gate_and(ex3_data_w3_sel(0), ib_rd_data_ecc0(0 to 6)) or + gate_and(ex3_data_w3_sel(1), ib_rd_data_ecc1(0 to 6)) or + gate_and(ex3_data_w3_sel(2), ib_rd_data_ecc2(0 to 6)) or + gate_and(ex3_data_w3_sel(3), ib_rd_data_ecc3(0 to 6)); + +-- latch data before returning it to xu + +latch_ex4_dp_data : tri_rlmreg_p + generic map (width => ex4_inbox_data'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ex3_mfdp_val_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_dp_data_offset to ex4_dp_data_offset + ex4_inbox_data'length-1), + scout => sov(ex4_dp_data_offset to ex4_dp_data_offset + ex4_inbox_data'length-1), + din => ex3_inbox_data(0 to 127), + dout => ex4_inbox_data(0 to 127) ); + + +latch_ex4_ib_data_ecc0 : tri_rlmreg_p + generic map (width => ex4_ib_data_ecc0'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ex3_mfdp_val_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_ib_data_ecc0_offset to ex4_ib_data_ecc0_offset + ex4_ib_data_ecc0'length-1), + scout => sov(ex4_ib_data_ecc0_offset to ex4_ib_data_ecc0_offset + ex4_ib_data_ecc0'length-1), + din => ex3_ib_data_ecc0(0 to 6), + dout => ex4_ib_data_ecc0(0 to 6) ); + +latch_ex4_ib_data_ecc1 : tri_rlmreg_p + generic map (width => ex4_ib_data_ecc1'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ex3_mfdp_val_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_ib_data_ecc1_offset to ex4_ib_data_ecc1_offset + ex4_ib_data_ecc1'length-1), + scout => sov(ex4_ib_data_ecc1_offset to ex4_ib_data_ecc1_offset + ex4_ib_data_ecc1'length-1), + din => ex3_ib_data_ecc1(0 to 6), + dout => ex4_ib_data_ecc1(0 to 6) ); + +latch_ex4_ib_data_ecc2 : tri_rlmreg_p + generic map (width => ex4_ib_data_ecc2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ex3_mfdp_val_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_ib_data_ecc2_offset to ex4_ib_data_ecc2_offset + ex4_ib_data_ecc2'length-1), + scout => sov(ex4_ib_data_ecc2_offset to ex4_ib_data_ecc2_offset + ex4_ib_data_ecc2'length-1), + din => ex3_ib_data_ecc2(0 to 6), + dout => ex4_ib_data_ecc2(0 to 6) ); + +latch_ex4_ib_data_ecc3 : tri_rlmreg_p + generic map (width => ex4_ib_data_ecc3'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ex3_mfdp_val_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_ib_data_ecc3_offset to ex4_ib_data_ecc3_offset + ex4_ib_data_ecc3'length-1), + scout => sov(ex4_ib_data_ecc3_offset to ex4_ib_data_ecc3_offset + ex4_ib_data_ecc3'length-1), + din => ex3_ib_data_ecc3(0 to 6), + dout => ex4_ib_data_ecc3(0 to 6) ); + +bx_xu_ex5_dp_data(0 to 127) <= ex5_inbox_data_cor(0 to 127); + +ex3_mfdp_cr_status <= ex3_mfdp_val_q and ( (ib0_rd_val_reg and ex3_ipc_thrd_q="00") or -- 1=mfdp pass, 0=mfdp fail + (ib1_rd_val_reg and ex3_ipc_thrd_q="01") or + (ib2_rd_val_reg and ex3_ipc_thrd_q="10") or + (ib3_rd_val_reg and ex3_ipc_thrd_q="11")); + +latch_ex4_mfdp_cr_status : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dp_op_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_mfdp_cr_status_offset to ex4_mfdp_cr_status_offset), + scout => sov(ex4_mfdp_cr_status_offset to ex4_mfdp_cr_status_offset), + din(0) => ex3_mfdp_cr_status, + dout(0) => ex4_mfdp_cr_status_i ); + +bx_xu_ex4_mfdp_cr_status <= ex4_mfdp_cr_status_i; + + +ex4_ib_ecc_val <= ex4_mfdp_cr_status_i and not ex4_ipc_ba_q(0); -- mfdp valid and not status reg (data from array) + +latch_ex5_ib_ecc_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dp_op_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex5_ib_ecc_val_offset to ex5_ib_ecc_val_offset), + scout => sov(ex5_ib_ecc_val_offset to ex5_ib_ecc_val_offset), + din(0) => ex4_ib_ecc_val, + dout(0) => ex5_ib_ecc_val ); + + +--********************************************************************************************** +-- latch the inputs from the node/L2 +--********************************************************************************************** + +latch_reld_data_val_dminus2 : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(reld_data_val_dminus2_offset to reld_data_val_dminus2_offset), + scout => sov(reld_data_val_dminus2_offset to reld_data_val_dminus2_offset), + din(0) => lsu_reld_data_vld, + dout(0) => lat_reld_data_val ); + +latch_reld_ditc : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(reld_ditc_offset to reld_ditc_offset), + scout => sov(reld_ditc_offset to reld_ditc_offset), + din(0) => lsu_reld_ditc, + dout(0) => lat_reld_ditc ); + +latch_reld_ecc_err : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(reld_ecc_err_offset to reld_ecc_err_offset), + scout => sov(reld_ecc_err_offset to reld_ecc_err_offset), + din(0) => lsu_reld_ecc_err, + dout(0) => lat_reld_ecc_err ); + +reld_data_val_dminus2 <= lat_reld_data_val and lat_reld_ditc; + +latch_reld_data_val_dminus1 : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(reld_data_val_dminus1_offset to reld_data_val_dminus1_offset), + scout => sov(reld_data_val_dminus1_offset to reld_data_val_dminus1_offset), + din(0) => reld_data_val_dminus2, + dout(0) => reld_data_val_dminus1 ); + +latch_reld_data_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(reld_data_val_offset to reld_data_val_offset), + scout => sov(reld_data_val_offset to reld_data_val_offset), + din(0) => reld_data_val_dminus1, + dout(0) => reld_data_val ); + +latch_reld_data_val_dplus1 : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(reld_data_val_dplus1_offset to reld_data_val_dplus1_offset), + scout => sov(reld_data_val_dplus1_offset to reld_data_val_dplus1_offset), + din(0) => reld_data_val, + dout(0) => reld_data_val_dplus1 ); + +latch_reld_core_tag_dminus2 : tri_rlmreg_p + generic map (width => lat_reld_core_tag'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(reld_core_tag_dminus2_offset to reld_core_tag_dminus2_offset + lat_reld_core_tag'length-1), + scout => sov(reld_core_tag_dminus2_offset to reld_core_tag_dminus2_offset + lat_reld_core_tag'length-1), + din => lsu_reld_core_tag, + dout => lat_reld_core_tag ); + +latch_reld_core_tag_dminus1 : tri_rlmreg_p + generic map (width => reld_core_tag_dminus1'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(reld_core_tag_dminus1_offset to reld_core_tag_dminus1_offset + reld_core_tag_dminus1'length-1), + scout => sov(reld_core_tag_dminus1_offset to reld_core_tag_dminus1_offset + reld_core_tag_dminus1'length-1), + din => lat_reld_core_tag, + dout => reld_core_tag_dminus1 ); + +latch_reld_core_tag : tri_rlmreg_p + generic map (width => reld_core_tag'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(reld_core_tag_offset to reld_core_tag_offset + reld_core_tag'length-1), + scout => sov(reld_core_tag_offset to reld_core_tag_offset + reld_core_tag'length-1), + din => reld_core_tag_dminus1, + dout => reld_core_tag ); + +latch_reld_core_tag_dplus1 : tri_rlmreg_p + generic map (width => reld_core_tag_dplus1'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(reld_core_tag_dplus1_offset to reld_core_tag_dplus1_offset + reld_core_tag_dplus1'length-1), + scout => sov(reld_core_tag_dplus1_offset to reld_core_tag_dplus1_offset + reld_core_tag_dplus1'length-1), + din => reld_core_tag, + dout => reld_core_tag_dplus1 ); + +latch_reld_qw_dminus2 : tri_rlmreg_p + generic map (width => lat_reld_qw'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(reld_qw_dminus2_offset to reld_qw_dminus2_offset + lat_reld_qw'length-1), + scout => sov(reld_qw_dminus2_offset to reld_qw_dminus2_offset + lat_reld_qw'length-1), + din => lsu_reld_qw, + dout => lat_reld_qw ); + +latch_reld_qw_dminus1 : tri_rlmreg_p + generic map (width => reld_qw_dminus1'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(reld_qw_dminus1_offset to reld_qw_dminus1_offset + reld_qw_dminus1'length-1), + scout => sov(reld_qw_dminus1_offset to reld_qw_dminus1_offset + reld_qw_dminus1'length-1), + din => lat_reld_qw, + dout => reld_qw_dminus1 ); + +latch_reld_qw : tri_rlmreg_p + generic map (width => reld_qw'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(reld_qw_offset to reld_qw_offset + reld_qw'length-1), + scout => sov(reld_qw_offset to reld_qw_offset + reld_qw'length-1), + din => reld_qw_dminus1, + dout => reld_qw ); + +latch_reld_data : tri_rlmreg_p + generic map (width => lat_reld_data'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => reld_data_val_dminus1, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(reld_data_offset to reld_data_offset + lat_reld_data'length-1), + scout => sov(reld_data_offset to reld_data_offset + lat_reld_data'length-1), + din => lsu_reld_data, + dout => lat_reld_data ); + +--**************************************************************************** +-- Generate ECC for IB array write data +--**************************************************************************** + + +ib_di_eccgen0: entity work.xuq_eccgen(xuq_eccgen) + generic map ( regsize => 32 ) + port map(din(0 to 31) => lat_reld_data(0 to 31), + din(32 to 38) => "1111111", + syn => ib_datain_ecc0 ); + +ib_di_eccgen1: entity work.xuq_eccgen(xuq_eccgen) + generic map ( regsize => 32 ) + port map(din(0 to 31) => lat_reld_data(32 to 63), + din(32 to 38) => "1111111", + syn => ib_datain_ecc1 ); + +ib_di_eccgen2: entity work.xuq_eccgen(xuq_eccgen) + generic map ( regsize => 32 ) + port map(din(0 to 31) => lat_reld_data(64 to 95), + din(32 to 38) => "1111111", + syn => ib_datain_ecc2 ); + +ib_di_eccgen3: entity work.xuq_eccgen(xuq_eccgen) + generic map ( regsize => 32 ) + port map(din(0 to 31) => lat_reld_data(96 to 127), + din(32 to 38) => "1111111", + syn => ib_datain_ecc3 ); + +--********************************************************************************************** +-- increment inbox buffer write pointer when the status register is written valid from nd_to_ib +-- there is one buffer pointer per thread +--********************************************************************************************** + +ib0_wrt_entry_ptr_minus1 <= std_ulogic_vector(unsigned(ib0_wrt_entry_ptr_q) - 1); +ib1_wrt_entry_ptr_minus1 <= std_ulogic_vector(unsigned(ib1_wrt_entry_ptr_q) - 1); +ib2_wrt_entry_ptr_minus1 <= std_ulogic_vector(unsigned(ib2_wrt_entry_ptr_q) - 1); +ib3_wrt_entry_ptr_minus1 <= std_ulogic_vector(unsigned(ib3_wrt_entry_ptr_q) - 1); + +dec_ib0_wrt_entry_ptr <= ib0_set_val_q and lat_reld_ecc_err; +dec_ib1_wrt_entry_ptr <= ib1_set_val_q and lat_reld_ecc_err; +dec_ib2_wrt_entry_ptr <= ib2_set_val_q and lat_reld_ecc_err; +dec_ib3_wrt_entry_ptr <= ib3_set_val_q and lat_reld_ecc_err; + +ib0_wrt_entry_ptr_d <= std_ulogic_vector(unsigned(ib0_wrt_entry_ptr_q) + 1) when ib0_set_val='1' else + std_ulogic_vector(unsigned(ib0_wrt_entry_ptr_q) - 1) when dec_ib0_wrt_entry_ptr='1' else + ib0_wrt_entry_ptr_q(0 to 1); + +ib1_wrt_entry_ptr_d <= std_ulogic_vector(unsigned(ib1_wrt_entry_ptr_q) + 1) when ib1_set_val='1' else + std_ulogic_vector(unsigned(ib1_wrt_entry_ptr_q) - 1) when dec_ib1_wrt_entry_ptr='1' else + ib1_wrt_entry_ptr_q(0 to 1); + +ib2_wrt_entry_ptr_d <= std_ulogic_vector(unsigned(ib2_wrt_entry_ptr_q) + 1) when ib2_set_val='1' else + std_ulogic_vector(unsigned(ib2_wrt_entry_ptr_q) - 1) when dec_ib2_wrt_entry_ptr='1' else + ib2_wrt_entry_ptr_q(0 to 1); + +ib3_wrt_entry_ptr_d <= std_ulogic_vector(unsigned(ib3_wrt_entry_ptr_q) + 1) when ib3_set_val='1' else + std_ulogic_vector(unsigned(ib3_wrt_entry_ptr_q) - 1) when dec_ib3_wrt_entry_ptr='1' else + ib3_wrt_entry_ptr_q(0 to 1); + + +latch_ib0_wrt_entry_ptr : tri_rlmreg_p + generic map (width => ib0_wrt_entry_ptr_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => reld_data_val, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib0_wrt_entry_ptr_offset to ib0_wrt_entry_ptr_offset + ib0_wrt_entry_ptr_q'length-1), + scout => sov(ib0_wrt_entry_ptr_offset to ib0_wrt_entry_ptr_offset + ib0_wrt_entry_ptr_q'length-1), + din => ib0_wrt_entry_ptr_d(0 to 1), + dout => ib0_wrt_entry_ptr_q(0 to 1) ); + +latch_ib1_wrt_entry_ptr : tri_rlmreg_p + generic map (width => ib1_wrt_entry_ptr_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => reld_data_val, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib1_wrt_entry_ptr_offset to ib1_wrt_entry_ptr_offset + ib1_wrt_entry_ptr_q'length-1), + scout => sov(ib1_wrt_entry_ptr_offset to ib1_wrt_entry_ptr_offset + ib1_wrt_entry_ptr_q'length-1), + din => ib1_wrt_entry_ptr_d(0 to 1), + dout => ib1_wrt_entry_ptr_q(0 to 1) ); + +latch_ib2_wrt_entry_ptr : tri_rlmreg_p + generic map (width => ib2_wrt_entry_ptr_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => reld_data_val, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib2_wrt_entry_ptr_offset to ib2_wrt_entry_ptr_offset + ib2_wrt_entry_ptr_q'length-1), + scout => sov(ib2_wrt_entry_ptr_offset to ib2_wrt_entry_ptr_offset + ib2_wrt_entry_ptr_q'length-1), + din => ib2_wrt_entry_ptr_d(0 to 1), + dout => ib2_wrt_entry_ptr_q(0 to 1) ); + +latch_ib3_wrt_entry_ptr : tri_rlmreg_p + generic map (width => ib3_wrt_entry_ptr_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => reld_data_val, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib3_wrt_entry_ptr_offset to ib3_wrt_entry_ptr_offset + ib3_wrt_entry_ptr_q'length-1), + scout => sov(ib3_wrt_entry_ptr_offset to ib3_wrt_entry_ptr_offset + ib3_wrt_entry_ptr_q'length-1), + din => ib3_wrt_entry_ptr_d(0 to 1), + dout => ib3_wrt_entry_ptr_q(0 to 1) ); + +ib0_wrt_entry_ptr <= ib0_wrt_entry_ptr_q when dec_ib0_wrt_entry_ptr='0' else + ib0_wrt_entry_ptr_minus1; + +ib1_wrt_entry_ptr <= ib1_wrt_entry_ptr_q when dec_ib1_wrt_entry_ptr='0' else + ib1_wrt_entry_ptr_minus1; + +ib2_wrt_entry_ptr <= ib2_wrt_entry_ptr_q when dec_ib2_wrt_entry_ptr='0' else + ib2_wrt_entry_ptr_minus1; + +ib3_wrt_entry_ptr <= ib3_wrt_entry_ptr_q when dec_ib3_wrt_entry_ptr='0' else + ib3_wrt_entry_ptr_minus1; + +--**************************************************************************** +-- Count data beats for each thread's inbox +--**************************************************************************** + +ib0_wrt_data_ctr_d(0 to 1) <= std_ulogic_vector(unsigned(ib0_wrt_data_ctr_q) + 1) when (reld_data_val_dminus1='1' and reld_core_tag_dminus1="00") else + ib0_wrt_data_ctr_q; + +ib1_wrt_data_ctr_d(0 to 1) <= std_ulogic_vector(unsigned(ib1_wrt_data_ctr_q) + 1) when (reld_data_val_dminus1='1' and reld_core_tag_dminus1="01") else + ib1_wrt_data_ctr_q; + +ib2_wrt_data_ctr_d(0 to 1) <= std_ulogic_vector(unsigned(ib2_wrt_data_ctr_q) + 1) when (reld_data_val_dminus1='1' and reld_core_tag_dminus1="10") else + ib2_wrt_data_ctr_q; + +ib3_wrt_data_ctr_d(0 to 1) <= std_ulogic_vector(unsigned(ib3_wrt_data_ctr_q) + 1) when (reld_data_val_dminus1='1' and reld_core_tag_dminus1="11") else + ib3_wrt_data_ctr_q; + +latch_ib0_wrt_data_ctr : tri_rlmreg_p + generic map (width => ib0_wrt_data_ctr_q'length, init => 3, expand_type => expand_type) + port map (nclk => nclk, + act => reld_data_val_dminus1, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib0_wrt_data_ctr_offset to ib0_wrt_data_ctr_offset + ib0_wrt_data_ctr_q'length-1), + scout => sov(ib0_wrt_data_ctr_offset to ib0_wrt_data_ctr_offset + ib0_wrt_data_ctr_q'length-1), + din => ib0_wrt_data_ctr_d(0 to 1), + dout => ib0_wrt_data_ctr_q(0 to 1)); + +latch_ib1_wrt_data_ctr : tri_rlmreg_p + generic map (width => ib1_wrt_data_ctr_q'length, init => 3, expand_type => expand_type) + port map (nclk => nclk, + act => reld_data_val_dminus1, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib1_wrt_data_ctr_offset to ib1_wrt_data_ctr_offset + ib1_wrt_data_ctr_q'length-1), + scout => sov(ib1_wrt_data_ctr_offset to ib1_wrt_data_ctr_offset + ib1_wrt_data_ctr_q'length-1), + din => ib1_wrt_data_ctr_d(0 to 1), + dout => ib1_wrt_data_ctr_q(0 to 1)); + +latch_ib2_wrt_data_ctr : tri_rlmreg_p + generic map (width => ib2_wrt_data_ctr_q'length, init => 3, expand_type => expand_type) + port map (nclk => nclk, + act => reld_data_val_dminus1, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib2_wrt_data_ctr_offset to ib2_wrt_data_ctr_offset + ib2_wrt_data_ctr_q'length-1), + scout => sov(ib2_wrt_data_ctr_offset to ib2_wrt_data_ctr_offset + ib2_wrt_data_ctr_q'length-1), + din => ib2_wrt_data_ctr_d(0 to 1), + dout => ib2_wrt_data_ctr_q(0 to 1)); + +latch_ib3_wrt_data_ctr : tri_rlmreg_p + generic map (width => ib3_wrt_data_ctr_q'length, init => 3, expand_type => expand_type) + port map (nclk => nclk, + act => reld_data_val_dminus1, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib3_wrt_data_ctr_offset to ib3_wrt_data_ctr_offset + ib3_wrt_data_ctr_q'length-1), + scout => sov(ib3_wrt_data_ctr_offset to ib3_wrt_data_ctr_offset + ib3_wrt_data_ctr_q'length-1), + din => ib3_wrt_data_ctr_d(0 to 1), + dout => ib3_wrt_data_ctr_q(0 to 1)); + + +-- select thread id for node to inbox command +ib_wrt_thrd(0 to 1) <= reld_core_tag(3 to 4); + +-- use thread to select write pointer +with ib_wrt_thrd select + ib_wrt_entry_pointer <= ib0_wrt_entry_ptr when "00", + ib1_wrt_entry_ptr when "01", + ib2_wrt_entry_ptr when "10", + ib3_wrt_entry_ptr when others; + + +-- assemble inbox array write address +ib_ary_wrt_addr(0 to 5) <= ib_wrt_thrd & ib_wrt_entry_pointer & reld_qw(58 to 59); + +ib_wen <= reld_data_val; +ib_ary_wen <= (others => ib_wen); + + +ib0_ecc_err_d <= (reld_data_val_dplus1 and lat_reld_ecc_err and not(ib0_wrt_data_ctr_q="11") and not ib0_set_val_q and reld_core_tag_dplus1="00") or + (ib0_ecc_err_q and not (ib0_wrt_data_ctr_q="11")); + +ib1_ecc_err_d <= (reld_data_val_dplus1 and lat_reld_ecc_err and not(ib1_wrt_data_ctr_q="11") and not ib1_set_val_q and reld_core_tag_dplus1="01") or + (ib1_ecc_err_q and not (ib1_wrt_data_ctr_q="11")); + +ib2_ecc_err_d <= (reld_data_val_dplus1 and lat_reld_ecc_err and not(ib2_wrt_data_ctr_q="11") and not ib2_set_val_q and reld_core_tag_dplus1="10") or + (ib2_ecc_err_q and not (ib2_wrt_data_ctr_q="11")); + +ib3_ecc_err_d <= (reld_data_val_dplus1 and lat_reld_ecc_err and not(ib3_wrt_data_ctr_q="11") and not ib3_set_val_q and reld_core_tag_dplus1="11") or + (ib3_ecc_err_q and not (ib3_wrt_data_ctr_q="11")); + +latch_ib0_ecc_err : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib0_ecc_err_offset to ib0_ecc_err_offset), + scout => sov(ib0_ecc_err_offset to ib0_ecc_err_offset), + din(0) => ib0_ecc_err_d, + dout(0) => ib0_ecc_err_q ); + +latch_ib1_ecc_err : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib1_ecc_err_offset to ib1_ecc_err_offset), + scout => sov(ib1_ecc_err_offset to ib1_ecc_err_offset), + din(0) => ib1_ecc_err_d, + dout(0) => ib1_ecc_err_q ); + +latch_ib2_ecc_err : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib2_ecc_err_offset to ib2_ecc_err_offset), + scout => sov(ib2_ecc_err_offset to ib2_ecc_err_offset), + din(0) => ib2_ecc_err_d, + dout(0) => ib2_ecc_err_q ); + +latch_ib3_ecc_err : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib3_ecc_err_offset to ib3_ecc_err_offset), + scout => sov(ib3_ecc_err_offset to ib3_ecc_err_offset), + din(0) => ib3_ecc_err_d, + dout(0) => ib3_ecc_err_q ); + +-- detemine which threads and buffers to set valid +ib0_set_val <= ib0_wrt_data_ctr_q="11" and reld_data_val and ib_wrt_thrd="00" and not (ib0_ecc_err_q or (reld_data_val_dplus1 and lat_reld_ecc_err and reld_core_tag_dplus1="00")); +ib1_set_val <= ib1_wrt_data_ctr_q="11" and reld_data_val and ib_wrt_thrd="01" and not (ib1_ecc_err_q or (reld_data_val_dplus1 and lat_reld_ecc_err and reld_core_tag_dplus1="01")); +ib2_set_val <= ib2_wrt_data_ctr_q="11" and reld_data_val and ib_wrt_thrd="10" and not (ib2_ecc_err_q or (reld_data_val_dplus1 and lat_reld_ecc_err and reld_core_tag_dplus1="10")); +ib3_set_val <= ib3_wrt_data_ctr_q="11" and reld_data_val and ib_wrt_thrd="11" and not (ib3_ecc_err_q or (reld_data_val_dplus1 and lat_reld_ecc_err and reld_core_tag_dplus1="11")); + + +ib0_buf0_set_val <= ib0_set_val and ib0_wrt_entry_ptr_q="00"; +ib0_buf1_set_val <= ib0_set_val and ib0_wrt_entry_ptr_q="01"; +ib0_buf2_set_val <= ib0_set_val and ib0_wrt_entry_ptr_q="10"; +ib0_buf3_set_val <= ib0_set_val and ib0_wrt_entry_ptr_q="11"; +ib1_buf0_set_val <= ib1_set_val and ib1_wrt_entry_ptr_q="00"; +ib1_buf1_set_val <= ib1_set_val and ib1_wrt_entry_ptr_q="01"; +ib1_buf2_set_val <= ib1_set_val and ib1_wrt_entry_ptr_q="10"; +ib1_buf3_set_val <= ib1_set_val and ib1_wrt_entry_ptr_q="11"; +ib2_buf0_set_val <= ib2_set_val and ib2_wrt_entry_ptr_q="00"; +ib2_buf1_set_val <= ib2_set_val and ib2_wrt_entry_ptr_q="01"; +ib2_buf2_set_val <= ib2_set_val and ib2_wrt_entry_ptr_q="10"; +ib2_buf3_set_val <= ib2_set_val and ib2_wrt_entry_ptr_q="11"; +ib3_buf0_set_val <= ib3_set_val and ib3_wrt_entry_ptr_q="00"; +ib3_buf1_set_val <= ib3_set_val and ib3_wrt_entry_ptr_q="01"; +ib3_buf2_set_val <= ib3_set_val and ib3_wrt_entry_ptr_q="10"; +ib3_buf3_set_val <= ib3_set_val and ib3_wrt_entry_ptr_q="11"; + +ib0_buf0_reset_val <= ib0_set_val_q and lat_reld_ecc_err and ib0_wrt_entry_ptr="00"; +ib0_buf1_reset_val <= ib0_set_val_q and lat_reld_ecc_err and ib0_wrt_entry_ptr="01"; +ib0_buf2_reset_val <= ib0_set_val_q and lat_reld_ecc_err and ib0_wrt_entry_ptr="10"; +ib0_buf3_reset_val <= ib0_set_val_q and lat_reld_ecc_err and ib0_wrt_entry_ptr="11"; +ib1_buf0_reset_val <= ib1_set_val_q and lat_reld_ecc_err and ib1_wrt_entry_ptr="00"; +ib1_buf1_reset_val <= ib1_set_val_q and lat_reld_ecc_err and ib1_wrt_entry_ptr="01"; +ib1_buf2_reset_val <= ib1_set_val_q and lat_reld_ecc_err and ib1_wrt_entry_ptr="10"; +ib1_buf3_reset_val <= ib1_set_val_q and lat_reld_ecc_err and ib1_wrt_entry_ptr="11"; +ib2_buf0_reset_val <= ib2_set_val_q and lat_reld_ecc_err and ib2_wrt_entry_ptr="00"; +ib2_buf1_reset_val <= ib2_set_val_q and lat_reld_ecc_err and ib2_wrt_entry_ptr="01"; +ib2_buf2_reset_val <= ib2_set_val_q and lat_reld_ecc_err and ib2_wrt_entry_ptr="10"; +ib2_buf3_reset_val <= ib2_set_val_q and lat_reld_ecc_err and ib2_wrt_entry_ptr="11"; +ib3_buf0_reset_val <= ib3_set_val_q and lat_reld_ecc_err and ib3_wrt_entry_ptr="00"; +ib3_buf1_reset_val <= ib3_set_val_q and lat_reld_ecc_err and ib3_wrt_entry_ptr="01"; +ib3_buf2_reset_val <= ib3_set_val_q and lat_reld_ecc_err and ib3_wrt_entry_ptr="10"; +ib3_buf3_reset_val <= ib3_set_val_q and lat_reld_ecc_err and ib3_wrt_entry_ptr="11"; + +latch_ib0_set_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib0_set_val_offset to ib0_set_val_offset), + scout => sov(ib0_set_val_offset to ib0_set_val_offset), + din(0) => ib0_set_val, + dout(0) => ib0_set_val_q ); + +latch_ib1_set_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib1_set_val_offset to ib1_set_val_offset), + scout => sov(ib1_set_val_offset to ib1_set_val_offset), + din(0) => ib1_set_val, + dout(0) => ib1_set_val_q ); + +latch_ib2_set_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib2_set_val_offset to ib2_set_val_offset), + scout => sov(ib2_set_val_offset to ib2_set_val_offset), + din(0) => ib2_set_val, + dout(0) => ib2_set_val_q ); + +latch_ib3_set_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ib3_set_val_offset to ib3_set_val_offset), + scout => sov(ib3_set_val_offset to ib3_set_val_offset), + din(0) => ib3_set_val, + dout(0) => ib3_set_val_q ); + +------------------------------------------------- +-- Debug +------------------------------------------------- + +dbg_group0_d <= ob_status_reg_newdata; + +dbg_group0 <= my_ex3_flush & + my_ex4_stg_flush & + my_ex5_stg_flush & + my_ex6_stg_flush & + my_ccr2_en_ditc_q & + ex4_mtdp_val_q & + ex4_ipc_thrd_q & + ex4_ipc_ba_q & + ex4_ipc_sz_q & + ob0_wrt_entry_ptr_q & + ob1_wrt_entry_ptr_q & + ob2_wrt_entry_ptr_q & + ob3_wrt_entry_ptr_q & + dbg_group0_q & + ob0_buf0_status_q(0) & + ob0_buf1_status_q(0) & + ob0_buf2_status_q(0) & + ob0_buf3_status_q(0) & + ob1_buf0_status_q(0) & + ob1_buf1_status_q(0) & + ob1_buf2_status_q(0) & + ob1_buf3_status_q(0) & + ob2_buf0_status_q(0) & + ob2_buf1_status_q(0) & + ob2_buf2_status_q(0) & + ob2_buf3_status_q(0) & + ob3_buf0_status_q(0) & + ob3_buf1_status_q(0) & + ob3_buf2_status_q(0) & + ob3_buf3_status_q(0) & + ob_wen & + ex4_mtdp_cr_status & + outbox_ecc_err_q & + outbox_ue_q & + ob0_rd_entry_ptr_q & + ob1_rd_entry_ptr_q & + ob2_rd_entry_ptr_q & + ob3_rd_entry_ptr_q & + ob_to_node_data_ptr & + ob_to_node_sel_q & + ob_to_node_sel_sav_q & -- 8 + bx_slowspr_val_q & + ditc_addr_sel & + bx_slowspr_rw_q & + bx_slowspr_etid_q & + ob_err_inj_q ; + +dbg_group1 <= ob_to_node_status_reg & + ob_to_nd_val_t0 & + ob_to_nd_val_t1 & + ob_to_nd_val_t2 & + ob_to_nd_val_t3 & + lsu_cmd_avail_q & + lsu_cmd_sent_q & + lsu_cmd_stall_q & + ob_cmd_sent_count_q & + ob_cmd_count_t0_q & + ob_cmd_count_t1_q & + ob_cmd_count_t2_q & + ob_cmd_count_t3_q & + send_ob_state_q & + dly_ob_cmd_val_q(1) & + dly_ob_ditc_val_q(1) & + dly1_ob_qw & + ob_to_node_selected_thrd(0 to 1) & + ob_addr_d & + lat_st_pop & + lat_st_pop_thrd(0 to 2); + +dbg_group2 <= my_ex3_flush & + my_ex4_stg_flush & + my_ex5_stg_flush & + my_ex6_stg_flush & + my_ccr2_en_ditc_q & + ex4_mfdp_val_q & + ex4_mtdp_val_q & + ex4_ipc_thrd_q & + ex4_ipc_ba_q & + ex4_ipc_sz_q & + ib0_rd_entry_ptr_q & + ib1_rd_entry_ptr_q & + ib2_rd_entry_ptr_q & + ib3_rd_entry_ptr_q & + ib_t0_pop_d & + ib_t1_pop_d & + ib_t2_pop_d & + ib_t3_pop_d & + ib0_buf0_val_q & + ib0_buf1_val_q & + ib0_buf2_val_q & + ib0_buf3_val_q & + ib1_buf0_val_q & + ib1_buf1_val_q & + ib1_buf2_val_q & + ib1_buf3_val_q & + ib2_buf0_val_q & + ib2_buf1_val_q & + ib2_buf2_val_q & + ib2_buf3_val_q & + ib3_buf0_val_q & + ib3_buf1_val_q & + ib3_buf2_val_q & + ib3_buf3_val_q & + ex5_ib_val_save_q & + ex6_ib_val_save_q & + inbox_ecc_err_q & + inbox_ue_q & + ex4_ib_rd_status_reg & + ex4_mfdp_cr_status_i & + lat_reld_data_val & + lat_reld_ditc & + lat_reld_core_tag & + lat_reld_qw & + ib0_wrt_entry_ptr_q & + ib1_wrt_entry_ptr_q & + ib2_wrt_entry_ptr_q & + ib3_wrt_entry_ptr_q & + ib0_wrt_data_ctr_q & + ib1_wrt_data_ctr_q & + ib2_wrt_data_ctr_q & + ib3_wrt_data_ctr_q & + lat_reld_data(24 to 31) & + ex5_inbox_data_cor(24 to 31); + +dbg_group3 <= lat_reld_data(56 to 63) & + lat_reld_data(88 to 95) & + ex5_inbox_data_cor(56 to 63) & + ex5_inbox_data_cor(88 to 95) & + ex5_inbox_data_cor(120 to 127) & + ob_ary_wrt_data_l2(24 to 31) & + ob_ary_wrt_data_l2(56 to 63) & + ob_ary_wrt_data_l2(88 to 95) & + ob_rd_data_cor_l2(24 to 31) & + ob_rd_data_cor_l2(56 to 63) & + ob_rd_data_cor_l2(120 to 127); + +trg_group0 <= ex4_mtdp_val_q & + ex4_mfdp_val_q & + my_ex4_stg_flush & + my_ex5_stg_flush & + my_ex6_stg_flush & + ob_to_nd_ready & + dly_ob_cmd_val_q(1) & + dly_ob_ditc_val_q(1) & + ob_credit_t0 & + ob_credit_t1 & + ob_credit_t2 & + ob_credit_t3; + +trg_group1 <= ex5_ob0_flushed & + ex5_ob1_flushed & + ex5_ob2_flushed & + ex5_ob3_flushed & + ex6_ob0_flushed & + ex6_ob1_flushed & + ex6_ob2_flushed & + ex6_ob3_flushed & + ex4_mtdp_cr_status & + ob_lsu_complete & + outbox_ecc_err_q & + outbox_ue_q ; + +trg_group2 <= ex4_ipc_thrd_q & + ex4_ipc_ba_q & + ex4_ib0_flushed & + ex4_ib1_flushed & + ex4_ib2_flushed & + ex4_ib3_flushed & + ex4_mfdp_cr_status_i; + +trg_group3 <= ex5_ib0_flushed & + ex5_ib1_flushed & + ex5_ib2_flushed & + ex5_ib3_flushed & + ex6_ib0_flushed & + ex6_ib1_flushed & + ex6_ib2_flushed & + ex6_ib3_flushed & + lat_reld_data_val & + lat_reld_ditc & + lat_reld_core_tag ; + +-- latch one set of debug input signals to represent that latches that may be needed when the real signals are used +latch_debug_dbg_group0 : tri_rlmreg_p + generic map (width => dbg_group0_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => trace_bus_enable_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(debug_dbg_group0_offset to debug_dbg_group0_offset + dbg_group0_q'length-1), + scout => sov(debug_dbg_group0_offset to debug_dbg_group0_offset + dbg_group0_q'length-1), + din => dbg_group0_d, + dout => dbg_group0_q); + + +latch_trace_bus_enable : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(trace_bus_enable_offset to trace_bus_enable_offset), + scout => sov(trace_bus_enable_offset to trace_bus_enable_offset), + din(0) => pc_bx_trace_bus_enable, + dout(0) => trace_bus_enable_q ); + +latch_debug_mux_ctrls : tri_rlmreg_p + generic map (width => debug_mux1_ctrls_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => trace_bus_enable_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(debug_mux_ctrls_offset to debug_mux_ctrls_offset + debug_mux1_ctrls_q'length-1), + scout => sov(debug_mux_ctrls_offset to debug_mux_ctrls_offset + debug_mux1_ctrls_q'length-1), + din => pc_bx_debug_mux1_ctrls(0 to 15), + dout => debug_mux1_ctrls_q(0 to 15)); + +debug_mux : entity clib.c_debug_mux4(c_debug_mux4) + port map ( + vd => vdd, + gd => gnd, + select_bits => debug_mux1_ctrls_q, + trace_data_in => debug_data_in, + trigger_data_in => trigger_data_in, + + dbg_group0 => dbg_group0, + dbg_group1 => dbg_group1, + dbg_group2 => dbg_group2, + dbg_group3 => dbg_group3, + + trg_group0 => trg_group0, + trg_group1 => trg_group1, + trg_group2 => trg_group2, + trg_group3 => trg_group3, + + trace_data_out => debug_mux_out_d, + trigger_data_out => trigger_mux_out_d + ); + + +latch_debug_mux_out : tri_rlmreg_p + generic map (width => debug_mux_out_d'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => trace_bus_enable_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(debug_mux_out_offset to debug_mux_out_offset + debug_mux_out_d'length-1), + scout => sov(debug_mux_out_offset to debug_mux_out_offset + debug_mux_out_d'length-1), + din => debug_mux_out_d(0 to 87), + dout => debug_data_out(0 to 87)); + + +latch_trigger_mux_out : tri_rlmreg_p + generic map (width => trigger_mux_out_d'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => trace_bus_enable_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(trigger_mux_out_offset to trigger_mux_out_offset + trigger_mux_out_d'length-1), + scout => sov(trigger_mux_out_offset to trigger_mux_out_offset + trigger_mux_out_d'length-1), + din => trigger_mux_out_d(0 to 11), + dout => trigger_data_out(0 to 11)); + +------------------------------------------------- +-- Pervasive +------------------------------------------------- + +perv_3to2_reg: tri_plat + generic map (width => 11, expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_bx_ccflush_dc, + din(0) => pc_bx_func_sl_thold_3, + din(1) => pc_bx_gptr_sl_thold_3, + din(2) => pc_bx_sg_3, + din(3) => pc_bx_abst_sl_thold_3, + din(4) => pc_bx_time_sl_thold_3, + din(5) => pc_bx_ary_nsl_thold_3, + din(6) => pc_bx_repr_sl_thold_3, + din(7) => pc_bx_func_slp_sl_thold_3, + din(8) => pc_bx_ary_slp_nsl_thold_3, + din(9) => pc_bx_bolt_sl_thold_3, + din(10) => pc_bx_bo_enable_3, + q(0) => func_sl_thold_2, + q(1) => gptr_sl_thold_2, + q(2) => sg_2, + q(3) => abst_sl_thold_2, + q(4) => time_sl_thold_2, + q(5) => ary_nsl_thold_2, + q(6) => repr_sl_thold_2, + q(7) => func_slp_sl_thold_2, + q(8) => ary_slp_nsl_thold_2, + q(9) => bolt_sl_thold_2, + q(10) => bolt_enable_2); + + +perv_2to1_reg: tri_plat + generic map (width => 10, expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_bx_ccflush_dc, + din(0) => func_sl_thold_2, + din(1) => gptr_sl_thold_2, + din(2) => sg_2, + din(3) => abst_sl_thold_2, + din(4) => time_sl_thold_2, + din(5) => ary_nsl_thold_2, + din(6) => repr_sl_thold_2, + din(7) => func_slp_sl_thold_2, + din(8) => ary_slp_nsl_thold_2, + din(9) => bolt_sl_thold_2, + q(0) => func_sl_thold_1, + q(1) => gptr_sl_thold_1, + q(2) => sg_1, + q(3) => abst_sl_thold_1, + q(4) => time_sl_thold_1, + q(5) => ary_nsl_thold_1, + q(6) => repr_sl_thold_1, + q(7) => func_slp_sl_thold_1, + q(8) => ary_slp_nsl_thold_1, + q(9) => bolt_sl_thold_1); + +perv_1to0_reg: tri_plat + generic map (width => 10, expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_bx_ccflush_dc, + din(0) => func_sl_thold_1, + din(1) => gptr_sl_thold_1, + din(2) => sg_1, + din(3) => abst_sl_thold_1, + din(4) => time_sl_thold_1, + din(5) => ary_nsl_thold_1, + din(6) => repr_sl_thold_1, + din(7) => func_slp_sl_thold_1, + din(8) => ary_slp_nsl_thold_1, + din(9) => bolt_sl_thold_1, + q(0) => func_sl_thold_0, + q(1) => gptr_sl_thold_0, + q(2) => sg_0, + q(3) => abst_sl_thold_0, + q(4) => time_sl_thold_0, + q(5) => ary_nsl_thold_0, + q(6) => repr_sl_thold_0, + q(7) => func_slp_sl_thold_0, + q(8) => ary_slp_nsl_thold_0, + q(9) => bolt_sl_thold_0); + +perv_lcbor_func_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_dc_b, + thold => func_sl_thold_0, + sg => sg_0, + act_dis => tidn, + forcee => func_sl_force, + thold_b => func_sl_thold_0_b); + +perv_lcbor_func_slp_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_dc_b, + thold => func_slp_sl_thold_0, + sg => sg_0, + act_dis => tidn, + forcee => func_slp_sl_force, + thold_b => func_slp_sl_thold_0_b); + +ab_lcbor_func_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_dc_b, + thold => abst_sl_thold_0, + sg => sg_0, + act_dis => tidn, + forcee => abst_sl_force, + thold_b => abst_sl_thold_0_b); + +perv_lcbctrl_0: tri_lcbcntl_mac + generic map (expand_type => expand_type) +port map ( + vdd => vdd, + gnd => gnd, + sg => sg_0, + nclk => nclk, + scan_in => gptr_scan_in, + scan_diag_dc => an_ac_scan_diag_dc, + thold => gptr_sl_thold_0, + clkoff_dc_b => clkoff_dc_b, + delay_lclkr_dc => delay_lclkr_dc_v(0 to 4), + act_dis_dc => open, + d_mode_dc => d_mode_dc, + mpw1_dc_b => mpw1_dc_b_v(0 to 4), + mpw2_dc_b => mpw2_dc_b, + scan_out => int_gptr_scan_out); + +delay_lclkr_dc <= delay_lclkr_dc_v(0); +mpw1_dc_b <= mpw1_dc_b_v(0); + +perv_lcbctrl_ary_0: tri_lcbcntl_array_mac + generic map (expand_type => expand_type) +port map ( + vdd => vdd, + gnd => gnd, + sg => sg_0, + nclk => nclk, + scan_in => int_gptr_scan_out, + scan_diag_dc => an_ac_scan_diag_dc, + thold => gptr_sl_thold_0, + clkoff_dc_b => ary0_clkoff_dc_b, + delay_lclkr_dc => ary0_delay_lclkr_dc_v(0 to 4), + act_dis_dc => open, + d_mode_dc => ary0_d_mode_dc, + mpw1_dc_b => ary0_mpw1_dc_b_v(0 to 4), + mpw2_dc_b => ary0_mpw2_dc_b, + scan_out => int0_gptr_scan_out); + +perv_lcbctrl_ary_1: tri_lcbcntl_array_mac + generic map (expand_type => expand_type) +port map ( + vdd => vdd, + gnd => gnd, + sg => sg_0, + nclk => nclk, + scan_in => int0_gptr_scan_out, + scan_diag_dc => an_ac_scan_diag_dc, + thold => gptr_sl_thold_0, + clkoff_dc_b => ary1_clkoff_dc_b, + delay_lclkr_dc => ary1_delay_lclkr_dc_v(0 to 4), + act_dis_dc => open, + d_mode_dc => ary1_d_mode_dc, + mpw1_dc_b => ary1_mpw1_dc_b_v(0 to 4), + mpw2_dc_b => ary1_mpw2_dc_b, + scan_out => int1_gptr_scan_out); + +gptr_scan_out <= int1_gptr_scan_out and an_ac_scan_dis_dc_b; + +-- LCBs for scan only staging latches +slat_force <= sg_0; +time_slat_thold_b <= NOT time_sl_thold_0; + +perv_lcbs_time: tri_lcbs + generic map (expand_type => expand_type ) + port map ( + vd => vdd, + gd => gnd, + delay_lclkr => delay_lclkr_dc, + nclk => nclk, + forcee => slat_force, + thold_b => time_slat_thold_b, + dclk => time_slat_d2clk, + lclk => time_slat_lclk ); + +perv_time_stg: tri_slat_scan + generic map (width => 2, init => "00", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => time_slat_d2clk, + lclk => time_slat_lclk, + scan_in(0) => time_scan_in, + scan_in(1) => ib_time_scan_out, + scan_out(0) => time_scan_in_q, + scan_out(1) => time_scan_out_stg ); + +time_scan_out <= time_scan_out_stg and an_ac_scan_dis_dc_b; + +repr_slat_thold_b <= NOT repr_sl_thold_0; + +perv_lcbs_repr: tri_lcbs + generic map (expand_type => expand_type ) + port map ( + vd => vdd, + gd => gnd, + delay_lclkr => delay_lclkr_dc, + nclk => nclk, + forcee => slat_force, + thold_b => repr_slat_thold_b, + dclk => repr_slat_d2clk, + lclk => repr_slat_lclk ); + +perv_repr_stg: tri_slat_scan + generic map (width => 2, init => "00", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => repr_slat_d2clk, + lclk => repr_slat_lclk, + scan_in(0) => repr_scan_in, + scan_in(1) => int_repr_scan_out, + scan_out(0) => repr_scan_in_q, + scan_out(1) => repr_scan_out_q ); + +repr_scan_out <= repr_scan_out_q and an_ac_scan_dis_dc_b; + +-- ABIST timing latches +ab_reg: tri_rlmreg_p generic map (init => 0, expand_type => expand_type, width => 25, needs_sreset => 0) +port map (nclk => nclk, + act => pc_bx_abist_ena_dc, + forcee => abst_sl_force, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => abst_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => ab_reg_si(0 to 24), + scout => ab_reg_so(0 to 24), + din ( 0 to 3) => pc_bx_abist_di_0(0 to 3) , + din ( 4) => pc_bx_abist_g8t_bw_1 , + din ( 5) => pc_bx_abist_g8t_bw_0 , + din ( 6 to 11) => pc_bx_abist_waddr_0(4 to 9) , + din ( 12) => pc_bx_abist_g8t_wenb , + din (13 to 18) => pc_bx_abist_raddr_0(4 to 9), + din ( 19) => pc_bx_abist_g8t1p_renb_0, + din ( 20) => pc_bx_abist_wl64_comp_ena, + din (21 to 24) => pc_bx_abist_g8t_dcomp(0 to 3) , + dout( 0 to 3) => abist_di_0(0 to 3) , + dout( 4) => abist_g8t_bw_1 , + dout( 5) => abist_g8t_bw_0 , + dout( 6 to 11) => abist_waddr_0(4 to 9) , + dout( 12) => abist_g8t_wenb , + dout(13 to 18) => abist_raddr_0(4 to 9), + dout( 19) => abist_g8t1p_renb_0, + dout( 20) => abist_wl64_comp_ena, + dout(21 to 24) => abist_g8t_dcomp(0 to 3) ); + + +-- ********************************************************************************* +-- Spare latches + +latch_spare0 : tri_rlmreg_p + generic map (width => spare0_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(spare0_offset to spare0_offset + spare0_l2'length-1), + scout => sov(spare0_offset to spare0_offset + spare0_l2'length-1), + din => spare0_l2(0 to 7), + dout => spare0_l2(0 to 7) ); + +latch_spare1 : tri_rlmreg_p + generic map (width => spare1_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(spare1_offset to spare1_offset + spare1_l2'length-1), + scout => sov(spare1_offset to spare1_offset + spare1_l2'length-1), + din => spare1_l2, + dout => spare1_l2 ); + + +-- scan in and scan out connections +siv(0 to scan_right0-1) <= sov(1 to scan_right0-1) & func_scan_in(0); +func_scan_out(0) <= sov(0) and an_ac_scan_dis_dc_b; + +siv(scan_right0 to siv'right) <= sov(scan_right0+1 to siv'right) & func_scan_in(1); +func_scan_out(1) <= sov(scan_right0) and an_ac_scan_dis_dc_b; + +ab_reg_si(0 to 24) <= ab_reg_so(1 to 24) & ib_abst_scan_out; +abst_scan_out <= ab_reg_so(0) and an_ac_scan_dis_dc_b; + +end bxq; diff --git a/rel/src/vhdl/work/fuq.vhdl b/rel/src/vhdl/work/fuq.vhdl new file mode 100644 index 0000000..521e731 --- /dev/null +++ b/rel/src/vhdl/work/fuq.vhdl @@ -0,0 +1,1691 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +--***************************************************************************** +--* +--* TITLE: fuq +--* +--* NAME: fuq.vhdl +--* +--* DESC: Top level Double Precision Floating Point Unit +--* +--***************************************************************************** + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + +entity fuq is +generic( + expand_type : integer := 2 ; -- 0 - ibm tech, 1 - other, 2 - MPG); + eff_ifar : integer := 62; + regmode : integer := 6); --32 or 64 bit mode +port( + + pc_fu_ccflush_dc : in std_ulogic; + an_ac_scan_dis_dc_b : in std_ulogic; + an_ac_scan_diag_dc : in std_ulogic; + + pc_fu_gptr_sl_thold_3 : in std_ulogic; + pc_fu_time_sl_thold_3 : in std_ulogic; + pc_fu_repr_sl_thold_3 : in std_ulogic; + pc_fu_abst_sl_thold_3 : in std_ulogic; + pc_fu_abst_slp_sl_thold_3 : in std_ulogic; + pc_fu_func_sl_thold_3 : in std_ulogic_vector(0 to 1); + pc_fu_func_slp_sl_thold_3 : in std_ulogic_vector(0 to 1); + pc_fu_cfg_sl_thold_3 : in std_ulogic; + pc_fu_cfg_slp_sl_thold_3 : in std_ulogic; + pc_fu_func_nsl_thold_3 : in std_ulogic; + pc_fu_func_slp_nsl_thold_3 : in std_ulogic; + pc_fu_ary_nsl_thold_3 : in std_ulogic; + pc_fu_ary_slp_nsl_thold_3 : in std_ulogic; + pc_fu_sg_3 : in std_ulogic_vector(0 to 1); + pc_fu_fce_3 : in std_ulogic; + an_ac_lbist_en_dc : in std_ulogic; + an_ac_abist_mode_dc : in std_ulogic; + an_ac_lbist_ary_wrt_thru_dc : in std_ulogic; + + pc_fu_bolt_sl_thold_3 : in std_ulogic; + pc_fu_bo_enable_3 : in std_ulogic; + pc_fu_bo_unload : in std_ulogic; + pc_fu_bo_load : in std_ulogic; + pc_fu_bo_reset : in std_ulogic; + pc_fu_bo_shdata : in std_ulogic; + pc_fu_bo_select : in std_ulogic_vector(0 to 1); + fu_pc_bo_fail : out std_ulogic_vector(0 to 1); + fu_pc_bo_diagout : out std_ulogic_vector(0 to 1); + + nclk : in clk_logic; + vdd : inout power_logic; + gnd : inout power_logic; + + -- Scan + gptr_scan_in : in std_ulogic; --tc_ac_gptr_scan_in(2) + time_scan_in : in std_ulogic; --tc_ac_time_scan_in(2) + repr_scan_in : in std_ulogic; --tc_ac_repr_scan_in(2) + abst_scan_in : in std_ulogic; --tc_ac_abst_scan_in(4) + func_scan_in : in std_ulogic_vector(0 to 3); --tc_ac_func_scan_in(24:27) + ccfg_scan_in : in std_ulogic; --tc_ac_bcfg_scan_in(1) + bcfg_scan_in : in std_ulogic; --tc_ac_bcfg_scan_in(2) + dcfg_scan_in : in std_ulogic; --tc_ac_dcfg_scan_in(2) + + gptr_scan_out : out std_ulogic; + time_scan_out : out std_ulogic; + repr_scan_out : out std_ulogic; + abst_scan_out : out std_ulogic; + func_scan_out : out std_ulogic_vector(0 to 3); + ccfg_scan_out : out std_ulogic; + bcfg_scan_out : out std_ulogic; + dcfg_scan_out : out std_ulogic; + + -- Staging for BX scans for timing + + bx_fu_rp_abst_scan_out : in std_ulogic; + bx_rp_abst_scan_out : out std_ulogic; + + rp_bx_abst_scan_in : in std_ulogic; + rp_fu_bx_abst_scan_in : out std_ulogic; + + rp_bx_func_scan_in : in std_ulogic_vector(0 to 1); + rp_fu_bx_func_scan_in : out std_ulogic_vector(0 to 1); + + bx_fu_rp_func_scan_out : in std_ulogic_vector(0 to 1); + bx_rp_func_scan_out : out std_ulogic_vector(0 to 1); + + bx_pc_err_inbox_ue_ifu : in std_ulogic; + bx_pc_err_outbox_ue_ifu : in std_ulogic; + bx_pc_err_inbox_ecc_ifu : in std_ulogic; + bx_pc_err_outbox_ecc_ifu : in std_ulogic; + pc_bx_bolt_sl_thold_3_ifu : in std_ulogic; + pc_bx_bo_enable_3_ifu : in std_ulogic; + pc_bx_bo_unload_ifu : in std_ulogic; + pc_bx_bo_repair_ifu : in std_ulogic; + pc_bx_bo_reset_ifu : in std_ulogic; + pc_bx_bo_shdata_ifu : in std_ulogic; + pc_bx_bo_select_ifu : in std_ulogic_vector(0 to 3); + bx_pc_bo_fail_ifu : in std_ulogic_vector(0 to 3); + bx_pc_bo_diagout_ifu : in std_ulogic_vector(0 to 3); + pc_bx_abist_di_0_ifu : in std_ulogic_vector(0 to 3); + pc_bx_abist_ena_dc_ifu : in std_ulogic; + pc_bx_abist_g8t1p_renb_0_ifu : in std_ulogic; + pc_bx_abist_g8t_bw_0_ifu : in std_ulogic; + pc_bx_abist_g8t_bw_1_ifu : in std_ulogic; + pc_bx_abist_g8t_dcomp_ifu : in std_ulogic_vector(0 to 3); + pc_bx_abist_g8t_wenb_ifu : in std_ulogic; + pc_bx_abist_raddr_0_ifu : in std_ulogic_vector(4 to 9); + pc_bx_abist_raw_dc_b_ifu : in std_ulogic; + pc_bx_abist_waddr_0_ifu : in std_ulogic_vector(4 to 9); + pc_bx_abist_wl64_comp_ena_ifu : in std_ulogic; + pc_bx_trace_bus_enable_ifu : in std_ulogic; + pc_bx_debug_mux1_ctrls_ifu : in std_ulogic_vector(0 to 15); + pc_bx_inj_inbox_ecc_ifu : in std_ulogic; + pc_bx_inj_outbox_ecc_ifu : in std_ulogic; + pc_bx_ccflush_dc_ifu : in std_ulogic; + pc_bx_sg_3_ifu : in std_ulogic; + pc_bx_func_sl_thold_3_ifu : in std_ulogic; + pc_bx_func_slp_sl_thold_3_ifu : in std_ulogic; + pc_bx_gptr_sl_thold_3_ifu : in std_ulogic; + pc_bx_time_sl_thold_3_ifu : in std_ulogic; + pc_bx_repr_sl_thold_3_ifu : in std_ulogic; + pc_bx_abst_sl_thold_3_ifu : in std_ulogic; + pc_bx_ary_nsl_thold_3_ifu : in std_ulogic; + pc_bx_ary_slp_nsl_thold_3_ifu : in std_ulogic; + + xu_pc_err_mcsr_summary_ifu : in std_ulogic_vector(0 to 3); + xu_pc_err_ierat_parity_ifu : in std_ulogic; + xu_pc_err_derat_parity_ifu : in std_ulogic; + xu_pc_err_tlb_parity_ifu : in std_ulogic; + xu_pc_err_tlb_lru_parity_ifu : in std_ulogic; + xu_pc_err_ierat_multihit_ifu : in std_ulogic; + xu_pc_err_derat_multihit_ifu : in std_ulogic; + xu_pc_err_tlb_multihit_ifu : in std_ulogic; + xu_pc_err_ext_mchk_ifu : in std_ulogic; + xu_pc_err_mchk_disabled_ifu : in std_ulogic; + xu_pc_err_ditc_overrun_ifu : in std_ulogic; + xu_pc_err_local_snoop_reject_ifu : in std_ulogic; + xu_pc_err_attention_instr_ifu : in std_ulogic_vector(0 to 3); + xu_pc_err_dcache_parity_ifu : in std_ulogic; + xu_pc_err_dcachedir_parity_ifu : in std_ulogic; + xu_pc_err_dcachedir_multihit_ifu : in std_ulogic; + xu_pc_err_debug_event_ifu : in std_ulogic_vector(0 to 3); + xu_pc_err_invld_reld_ifu : in std_ulogic; + xu_pc_err_l2intrf_ecc_ifu : in std_ulogic; + xu_pc_err_l2intrf_ue_ifu : in std_ulogic; + xu_pc_err_l2credit_overrun_ifu : in std_ulogic; + xu_pc_err_llbust_attempt_ifu : in std_ulogic_vector(0 to 3); + xu_pc_err_llbust_failed_ifu : in std_ulogic_vector(0 to 3); + xu_pc_err_nia_miscmpr_ifu : in std_ulogic_vector(0 to 3); + xu_pc_err_regfile_parity_ifu : in std_ulogic_vector(0 to 3); + xu_pc_err_regfile_ue_ifu : in std_ulogic_vector(0 to 3); + xu_pc_err_sprg_ecc_ifu : in std_ulogic_vector(0 to 3); + xu_pc_err_sprg_ue_ifu : in std_ulogic_vector(0 to 3); + xu_pc_err_wdt_reset_ifu : in std_ulogic_vector(0 to 3); + xu_pc_event_data_ifu : in std_ulogic_vector(0 to 7); + xu_pc_ram_data_ifu : in std_ulogic_vector(64-(2**regmode) to 63); + xu_pc_ram_done_ifu : in std_ulogic; + xu_pc_ram_interrupt_ifu : in std_ulogic; + xu_pc_running_ifu : in std_ulogic_vector(0 to 3); + xu_pc_spr_ccr0_pme_ifu : in std_ulogic_vector(0 to 1); + xu_pc_spr_ccr0_we_ifu : in std_ulogic_vector(0 to 3); + xu_pc_step_done_ifu : in std_ulogic_vector(0 to 3); + xu_pc_stop_dbg_event_ifu : in std_ulogic_vector(0 to 3); + xu_pc_lsu_event_data_ifu : in std_ulogic_vector(0 to 7); + pc_xu_bolt_sl_thold_3_ifu : in std_ulogic; + pc_xu_bo_enable_3_ifu : in std_ulogic; + pc_xu_bo_unload_ifu : in std_ulogic; + pc_xu_bo_load_ifu : in std_ulogic; + pc_xu_bo_repair_ifu : in std_ulogic; + pc_xu_bo_reset_ifu : in std_ulogic; + pc_xu_bo_shdata_ifu : in std_ulogic; + pc_xu_bo_select_ifu : in std_ulogic_vector(0 to 8); + xu_pc_bo_fail_ifu : in std_ulogic_vector(0 to 8); + xu_pc_bo_diagout_ifu : in std_ulogic_vector(0 to 8); + pc_xu_abist_dcomp_g6t_2r_ifu : in std_ulogic_vector(0 to 3); + pc_xu_abist_di_0_ifu : in std_ulogic_vector(0 to 3); + pc_xu_abist_di_1_ifu : in std_ulogic_vector(0 to 3); + pc_xu_abist_di_g6t_2r_ifu : in std_ulogic_vector(0 to 3); + pc_xu_abist_ena_dc_ifu : in std_ulogic; + pc_xu_abist_g6t_bw_ifu : in std_ulogic_vector(0 to 1); + pc_xu_abist_g6t_r_wb_ifu : in std_ulogic; + pc_xu_abist_g8t1p_renb_0_ifu : in std_ulogic; + pc_xu_abist_g8t_bw_0_ifu : in std_ulogic; + pc_xu_abist_g8t_bw_1_ifu : in std_ulogic; + pc_xu_abist_g8t_dcomp_ifu : in std_ulogic_vector(0 to 3); + pc_xu_abist_g8t_wenb_ifu : in std_ulogic; + pc_xu_abist_grf_renb_0_ifu : in std_ulogic; + pc_xu_abist_grf_renb_1_ifu : in std_ulogic; + pc_xu_abist_grf_wenb_0_ifu : in std_ulogic; + pc_xu_abist_grf_wenb_1_ifu : in std_ulogic; + pc_xu_abist_raddr_0_ifu : in std_ulogic_vector(0 to 9); + pc_xu_abist_raddr_1_ifu : in std_ulogic_vector(0 to 9); + pc_xu_abist_raw_dc_b_ifu : in std_ulogic; + pc_xu_abist_waddr_0_ifu : in std_ulogic_vector(0 to 9); + pc_xu_abist_waddr_1_ifu : in std_ulogic_vector(0 to 9); + pc_xu_abist_wl144_comp_ena_ifu : in std_ulogic; + pc_xu_abist_wl32_comp_ena_ifu : in std_ulogic; + pc_xu_abist_wl512_comp_ena_ifu : in std_ulogic; + pc_xu_event_mux_ctrls_ifu : in std_ulogic_vector(0 to 47); + pc_xu_lsu_event_mux_ctrls_ifu : in std_ulogic_vector(0 to 47); + pc_xu_event_bus_enable_ifu : in std_ulogic; + pc_xu_abst_sl_thold_3_ifu : in std_ulogic; + pc_xu_abst_slp_sl_thold_3_ifu : in std_ulogic; + pc_xu_regf_sl_thold_3_ifu : in std_ulogic; + pc_xu_regf_slp_sl_thold_3_ifu : in std_ulogic; + pc_xu_ary_nsl_thold_3_ifu : in std_ulogic; + pc_xu_ary_slp_nsl_thold_3_ifu : in std_ulogic; + pc_xu_cache_par_err_event_ifu : in std_ulogic; + pc_xu_ccflush_dc_ifu : in std_ulogic; + pc_xu_cfg_sl_thold_3_ifu : in std_ulogic; + pc_xu_cfg_slp_sl_thold_3_ifu : in std_ulogic; + pc_xu_dbg_action_ifu : in std_ulogic_vector(0 to 11); + pc_xu_debug_mux1_ctrls_ifu : in std_ulogic_vector(0 to 15); + pc_xu_debug_mux2_ctrls_ifu : in std_ulogic_vector(0 to 15); + pc_xu_debug_mux3_ctrls_ifu : in std_ulogic_vector(0 to 15); + pc_xu_debug_mux4_ctrls_ifu : in std_ulogic_vector(0 to 15); + pc_xu_decrem_dis_on_stop_ifu : in std_ulogic; + pc_xu_event_count_mode_ifu : in std_ulogic_vector(0 to 2); + pc_xu_extirpts_dis_on_stop_ifu : in std_ulogic; + pc_xu_fce_3_ifu : in std_ulogic_vector(0 to 1); + pc_xu_force_ude_ifu : in std_ulogic_vector(0 to 3); + pc_xu_func_nsl_thold_3_ifu : in std_ulogic; + pc_xu_func_sl_thold_3_ifu : in std_ulogic_vector(0 to 4); + pc_xu_func_slp_nsl_thold_3_ifu : in std_ulogic; + pc_xu_func_slp_sl_thold_3_ifu : in std_ulogic_vector(0 to 4); + pc_xu_gptr_sl_thold_3_ifu : in std_ulogic; + pc_xu_init_reset_ifu : in std_ulogic; + pc_xu_inj_dcache_parity_ifu : in std_ulogic; + pc_xu_inj_dcachedir_parity_ifu : in std_ulogic; + pc_xu_inj_llbust_attempt_ifu : in std_ulogic_vector(0 to 3); + pc_xu_inj_llbust_failed_ifu : in std_ulogic_vector(0 to 3); + pc_xu_inj_sprg_ecc_ifu : in std_ulogic_vector(0 to 3); + pc_xu_inj_regfile_parity_ifu : in std_ulogic_vector(0 to 3); + pc_xu_inj_wdt_reset_ifu : in std_ulogic_vector(0 to 3); + pc_xu_inj_dcachedir_multihit_ifu : in std_ulogic; + pc_xu_instr_trace_mode_ifu : in std_ulogic; + pc_xu_instr_trace_tid_ifu : in std_ulogic_vector(0 to 1); + pc_xu_msrovride_enab_ifu : in std_ulogic; + pc_xu_msrovride_gs_ifu : in std_ulogic; + pc_xu_msrovride_pr_ifu : in std_ulogic; + pc_xu_ram_execute_ifu : in std_ulogic; + pc_xu_ram_flush_thread_ifu : in std_ulogic; + pc_xu_ram_mode_ifu : in std_ulogic; + pc_xu_ram_thread_ifu : in std_ulogic_vector(0 to 1); + pc_xu_repr_sl_thold_3_ifu : in std_ulogic; + pc_xu_reset_1_cmplt_ifu : in std_ulogic; + pc_xu_reset_2_cmplt_ifu : in std_ulogic; + pc_xu_reset_3_cmplt_ifu : in std_ulogic; + pc_xu_reset_wd_cmplt_ifu : in std_ulogic; + pc_xu_sg_3_ifu : in std_ulogic_vector(0 to 4); + pc_xu_step_ifu : in std_ulogic_vector(0 to 3); + pc_xu_stop_ifu : in std_ulogic_vector(0 to 3); + pc_xu_time_sl_thold_3_ifu : in std_ulogic; + pc_xu_timebase_dis_on_stop_ifu : in std_ulogic; + pc_xu_trace_bus_enable_ifu : in std_ulogic; + + bx_pc_err_inbox_ue_ofu : out std_ulogic; + bx_pc_err_outbox_ue_ofu : out std_ulogic; + bx_pc_err_inbox_ecc_ofu : out std_ulogic; + bx_pc_err_outbox_ecc_ofu : out std_ulogic; + pc_bx_bolt_sl_thold_3_ofu : out std_ulogic; + pc_bx_bo_enable_3_ofu : out std_ulogic; + pc_bx_bo_unload_ofu : out std_ulogic; + pc_bx_bo_repair_ofu : out std_ulogic; + pc_bx_bo_reset_ofu : out std_ulogic; + pc_bx_bo_shdata_ofu : out std_ulogic; + pc_bx_bo_select_ofu : out std_ulogic_vector(0 to 3); + bx_pc_bo_fail_ofu : out std_ulogic_vector(0 to 3); + bx_pc_bo_diagout_ofu : out std_ulogic_vector(0 to 3); + pc_bx_abist_di_0_ofu : out std_ulogic_vector(0 to 3); + pc_bx_abist_ena_dc_ofu : out std_ulogic; + pc_bx_abist_g8t1p_renb_0_ofu : out std_ulogic; + pc_bx_abist_g8t_bw_0_ofu : out std_ulogic; + pc_bx_abist_g8t_bw_1_ofu : out std_ulogic; + pc_bx_abist_g8t_dcomp_ofu : out std_ulogic_vector(0 to 3); + pc_bx_abist_g8t_wenb_ofu : out std_ulogic; + pc_bx_abist_raddr_0_ofu : out std_ulogic_vector(4 to 9); + pc_bx_abist_raw_dc_b_ofu : out std_ulogic; + pc_bx_abist_waddr_0_ofu : out std_ulogic_vector(4 to 9); + pc_bx_abist_wl64_comp_ena_ofu : out std_ulogic; + pc_bx_trace_bus_enable_ofu : out std_ulogic; + pc_bx_debug_mux1_ctrls_ofu : out std_ulogic_vector(0 to 15); + pc_bx_inj_inbox_ecc_ofu : out std_ulogic; + pc_bx_inj_outbox_ecc_ofu : out std_ulogic; + pc_bx_ccflush_dc_ofu : out std_ulogic; + pc_bx_sg_3_ofu : out std_ulogic; + pc_bx_func_sl_thold_3_ofu : out std_ulogic; + pc_bx_func_slp_sl_thold_3_ofu : out std_ulogic; + pc_bx_gptr_sl_thold_3_ofu : out std_ulogic; + pc_bx_time_sl_thold_3_ofu : out std_ulogic; + pc_bx_repr_sl_thold_3_ofu : out std_ulogic; + pc_bx_abst_sl_thold_3_ofu : out std_ulogic; + pc_bx_ary_nsl_thold_3_ofu : out std_ulogic; + pc_bx_ary_slp_nsl_thold_3_ofu : out std_ulogic; + + xu_pc_err_mcsr_summary_ofu : out std_ulogic_vector(0 to 3); + xu_pc_err_ierat_parity_ofu : out std_ulogic; + xu_pc_err_derat_parity_ofu : out std_ulogic; + xu_pc_err_tlb_parity_ofu : out std_ulogic; + xu_pc_err_tlb_lru_parity_ofu : out std_ulogic; + xu_pc_err_ierat_multihit_ofu : out std_ulogic; + xu_pc_err_derat_multihit_ofu : out std_ulogic; + xu_pc_err_tlb_multihit_ofu : out std_ulogic; + xu_pc_err_ext_mchk_ofu : out std_ulogic; + xu_pc_err_mchk_disabled_ofu : out std_ulogic; + xu_pc_err_ditc_overrun_ofu : out std_ulogic; + xu_pc_err_local_snoop_reject_ofu : out std_ulogic; + xu_pc_err_attention_instr_ofu : out std_ulogic_vector(0 to 3); + xu_pc_err_dcache_parity_ofu : out std_ulogic; + xu_pc_err_dcachedir_parity_ofu : out std_ulogic; + xu_pc_err_dcachedir_multihit_ofu : out std_ulogic; + xu_pc_err_debug_event_ofu : out std_ulogic_vector(0 to 3); + xu_pc_err_invld_reld_ofu : out std_ulogic; + xu_pc_err_l2intrf_ecc_ofu : out std_ulogic; + xu_pc_err_l2intrf_ue_ofu : out std_ulogic; + xu_pc_err_l2credit_overrun_ofu : out std_ulogic; + xu_pc_err_llbust_attempt_ofu : out std_ulogic_vector(0 to 3); + xu_pc_err_llbust_failed_ofu : out std_ulogic_vector(0 to 3); + xu_pc_err_nia_miscmpr_ofu : out std_ulogic_vector(0 to 3); + xu_pc_err_regfile_parity_ofu : out std_ulogic_vector(0 to 3); + xu_pc_err_regfile_ue_ofu : out std_ulogic_vector(0 to 3); + xu_pc_err_sprg_ecc_ofu : out std_ulogic_vector(0 to 3); + xu_pc_err_sprg_ue_ofu : out std_ulogic_vector(0 to 3); + xu_pc_err_wdt_reset_ofu : out std_ulogic_vector(0 to 3); + xu_pc_event_data_ofu : out std_ulogic_vector(0 to 7); + xu_pc_ram_data_ofu : out std_ulogic_vector(64-(2**regmode) to 63); + xu_pc_ram_done_ofu : out std_ulogic; + xu_pc_ram_interrupt_ofu : out std_ulogic; + xu_pc_running_ofu : out std_ulogic_vector(0 to 3); + xu_pc_spr_ccr0_pme_ofu : out std_ulogic_vector(0 to 1); + xu_pc_spr_ccr0_we_ofu : out std_ulogic_vector(0 to 3); + xu_pc_step_done_ofu : out std_ulogic_vector(0 to 3); + xu_pc_stop_dbg_event_ofu : out std_ulogic_vector(0 to 3); + xu_pc_lsu_event_data_ofu : out std_ulogic_vector(0 to 7); + pc_xu_bolt_sl_thold_3_ofu : out std_ulogic; + pc_xu_bo_enable_3_ofu : out std_ulogic; + pc_xu_bo_unload_ofu : out std_ulogic; + pc_xu_bo_load_ofu : out std_ulogic; + pc_xu_bo_repair_ofu : out std_ulogic; + pc_xu_bo_reset_ofu : out std_ulogic; + pc_xu_bo_shdata_ofu : out std_ulogic; + pc_xu_bo_select_ofu : out std_ulogic_vector(0 to 8); + xu_pc_bo_fail_ofu : out std_ulogic_vector(0 to 8); + xu_pc_bo_diagout_ofu : out std_ulogic_vector(0 to 8); + pc_xu_abist_dcomp_g6t_2r_ofu : out std_ulogic_vector(0 to 3); + pc_xu_abist_di_0_ofu : out std_ulogic_vector(0 to 3); + pc_xu_abist_di_1_ofu : out std_ulogic_vector(0 to 3); + pc_xu_abist_di_g6t_2r_ofu : out std_ulogic_vector(0 to 3); + pc_xu_abist_ena_dc_ofu : out std_ulogic; + pc_xu_abist_g6t_bw_ofu : out std_ulogic_vector(0 to 1); + pc_xu_abist_g6t_r_wb_ofu : out std_ulogic; + pc_xu_abist_g8t1p_renb_0_ofu : out std_ulogic; + pc_xu_abist_g8t_bw_0_ofu : out std_ulogic; + pc_xu_abist_g8t_bw_1_ofu : out std_ulogic; + pc_xu_abist_g8t_dcomp_ofu : out std_ulogic_vector(0 to 3); + pc_xu_abist_g8t_wenb_ofu : out std_ulogic; + pc_xu_abist_grf_renb_0_ofu : out std_ulogic; + pc_xu_abist_grf_renb_1_ofu : out std_ulogic; + pc_xu_abist_grf_wenb_0_ofu : out std_ulogic; + pc_xu_abist_grf_wenb_1_ofu : out std_ulogic; + pc_xu_abist_raddr_0_ofu : out std_ulogic_vector(0 to 9); + pc_xu_abist_raddr_1_ofu : out std_ulogic_vector(0 to 9); + pc_xu_abist_raw_dc_b_ofu : out std_ulogic; + pc_xu_abist_waddr_0_ofu : out std_ulogic_vector(0 to 9); + pc_xu_abist_waddr_1_ofu : out std_ulogic_vector(0 to 9); + pc_xu_abist_wl144_comp_ena_ofu : out std_ulogic; + pc_xu_abist_wl32_comp_ena_ofu : out std_ulogic; + pc_xu_abist_wl512_comp_ena_ofu : out std_ulogic; + pc_xu_event_mux_ctrls_ofu : out std_ulogic_vector(0 to 47); + pc_xu_lsu_event_mux_ctrls_ofu : out std_ulogic_vector(0 to 47); + pc_xu_event_bus_enable_ofu : out std_ulogic; + pc_xu_abst_sl_thold_3_ofu : out std_ulogic; + pc_xu_abst_slp_sl_thold_3_ofu : out std_ulogic; + pc_xu_regf_sl_thold_3_ofu : out std_ulogic; + pc_xu_regf_slp_sl_thold_3_ofu : out std_ulogic; + pc_xu_ary_nsl_thold_3_ofu : out std_ulogic; + pc_xu_ary_slp_nsl_thold_3_ofu : out std_ulogic; + pc_xu_cache_par_err_event_ofu : out std_ulogic; + pc_xu_ccflush_dc_ofu : out std_ulogic; + pc_xu_cfg_sl_thold_3_ofu : out std_ulogic; + pc_xu_cfg_slp_sl_thold_3_ofu : out std_ulogic; + pc_xu_dbg_action_ofu : out std_ulogic_vector(0 to 11); + pc_xu_debug_mux1_ctrls_ofu : out std_ulogic_vector(0 to 15); + pc_xu_debug_mux2_ctrls_ofu : out std_ulogic_vector(0 to 15); + pc_xu_debug_mux3_ctrls_ofu : out std_ulogic_vector(0 to 15); + pc_xu_debug_mux4_ctrls_ofu : out std_ulogic_vector(0 to 15); + pc_xu_decrem_dis_on_stop_ofu : out std_ulogic; + pc_xu_event_count_mode_ofu : out std_ulogic_vector(0 to 2); + pc_xu_extirpts_dis_on_stop_ofu : out std_ulogic; + pc_xu_fce_3_ofu : out std_ulogic_vector(0 to 1); + pc_xu_force_ude_ofu : out std_ulogic_vector(0 to 3); + pc_xu_func_nsl_thold_3_ofu : out std_ulogic; + pc_xu_func_sl_thold_3_ofu : out std_ulogic_vector(0 to 4); + pc_xu_func_slp_nsl_thold_3_ofu : out std_ulogic; + pc_xu_func_slp_sl_thold_3_ofu : out std_ulogic_vector(0 to 4); + pc_xu_gptr_sl_thold_3_ofu : out std_ulogic; + pc_xu_init_reset_ofu : out std_ulogic; + pc_xu_inj_dcache_parity_ofu : out std_ulogic; + pc_xu_inj_dcachedir_parity_ofu : out std_ulogic; + pc_xu_inj_llbust_attempt_ofu : out std_ulogic_vector(0 to 3); + pc_xu_inj_llbust_failed_ofu : out std_ulogic_vector(0 to 3); + pc_xu_inj_sprg_ecc_ofu : out std_ulogic_vector(0 to 3); + pc_xu_inj_regfile_parity_ofu : out std_ulogic_vector(0 to 3); + pc_xu_inj_wdt_reset_ofu : out std_ulogic_vector(0 to 3); + pc_xu_inj_dcachedir_multihit_ofu : out std_ulogic; + pc_xu_instr_trace_mode_ofu : out std_ulogic; + pc_xu_instr_trace_tid_ofu : out std_ulogic_vector(0 to 1); + pc_xu_msrovride_enab_ofu : out std_ulogic; + pc_xu_msrovride_gs_ofu : out std_ulogic; + pc_xu_msrovride_pr_ofu : out std_ulogic; + pc_xu_ram_execute_ofu : out std_ulogic; + pc_xu_ram_flush_thread_ofu : out std_ulogic; + pc_xu_ram_mode_ofu : out std_ulogic; + pc_xu_ram_thread_ofu : out std_ulogic_vector(0 to 1); + pc_xu_repr_sl_thold_3_ofu : out std_ulogic; + pc_xu_reset_1_cmplt_ofu : out std_ulogic; + pc_xu_reset_2_cmplt_ofu : out std_ulogic; + pc_xu_reset_3_cmplt_ofu : out std_ulogic; + pc_xu_reset_wd_cmplt_ofu : out std_ulogic; + pc_xu_sg_3_ofu : out std_ulogic_vector(0 to 4); + pc_xu_step_ofu : out std_ulogic_vector(0 to 3); + pc_xu_stop_ofu : out std_ulogic_vector(0 to 3); + pc_xu_time_sl_thold_3_ofu : out std_ulogic; + pc_xu_timebase_dis_on_stop_ofu : out std_ulogic; + pc_xu_trace_bus_enable_ofu : out std_ulogic; + an_ac_scan_dis_dc_b_ofu : out std_ulogic; + an_ac_scan_diag_dc_ofu : out std_ulogic; + xu_ex2_flush_ofu : out std_ulogic_vector(0 to 3); + xu_ex3_flush_ofu : out std_ulogic_vector(0 to 3); + xu_ex4_flush_ofu : out std_ulogic_vector(0 to 3); + xu_ex5_flush_ofu : out std_ulogic_vector(0 to 3); + an_ac_lbist_ary_wrt_thru_dc_ofu : out std_ulogic; + + -- Interface to IU + iu_fu_rf0_instr_v : in std_ulogic; + iu_fu_rf0_instr : in std_ulogic_vector(0 to 31); + iu_fu_rf0_fra_v : in std_ulogic; + iu_fu_rf0_frb_v : in std_ulogic; + iu_fu_rf0_frc_v : in std_ulogic; + iu_fu_rf0_tid : in std_ulogic_vector(0 to 1); + iu_fu_rf0_fra : in std_ulogic_vector(0 to 6); + iu_fu_rf0_frb : in std_ulogic_vector(0 to 6); + iu_fu_rf0_frc : in std_ulogic_vector(0 to 6); + iu_fu_rf0_frt : in std_ulogic_vector(0 to 6); + iu_fu_rf0_ifar : in std_ulogic_vector(62-eff_ifar to 61); + iu_fu_rf0_str_val : in std_ulogic; + iu_fu_rf0_ldst_val : in std_ulogic; + iu_fu_rf0_ldst_tid : in std_ulogic_vector(0 to 1); + iu_fu_rf0_ldst_tag : in std_ulogic_vector(0 to 8); + iu_fu_rf0_bypsel : in std_ulogic_vector(0 to 5); + iu_fu_rf0_instr_match : in std_ulogic; + iu_fu_rf0_is_ucode : in std_ulogic; + iu_fu_rf0_ucfmul : in std_ulogic; + iu_fu_is2_tid_decode : in std_ulogic_vector(0 to 3); + iu_fu_ex2_n_flush : in std_ulogic_vector(0 to 3); + -- flush signals + xu_is2_flush : in std_ulogic_vector(0 to 3); + xu_rf0_flush : in std_ulogic_vector(0 to 3); + xu_rf1_flush : in std_ulogic_vector(0 to 3); + xu_ex1_flush : in std_ulogic_vector(0 to 3); + xu_ex2_flush : in std_ulogic_vector(0 to 3); + xu_ex3_flush : in std_ulogic_vector(0 to 3); + xu_ex4_flush : in std_ulogic_vector(0 to 3); + xu_ex5_flush : in std_ulogic_vector(0 to 3); + -- Completion + xu_fu_ex3_eff_addr : in std_ulogic_vector(59 to 63); + fu_xu_ex2_ifar_val : out std_ulogic_vector(0 to 3); + fu_xu_ex2_ifar_issued : out std_ulogic_vector(0 to 3); + fu_xu_ex1_ifar : out std_ulogic_vector(62-eff_ifar to 61); + fu_xu_ex3_n_flush : out std_ulogic_vector(0 to 3); + fu_xu_ex3_np1_flush : out std_ulogic_vector(0 to 3); + fu_xu_ex3_flush2ucode : out std_ulogic_vector(0 to 3); + fu_xu_ex2_instr_type : out std_ulogic_vector(0 to 11); + fu_xu_ex2_instr_match : out std_ulogic_vector(0 to 3); + fu_xu_ex2_is_ucode : out std_ulogic_vector(0 to 3); + fu_xu_ex3_trap : out std_ulogic_vector(0 to 3); + fu_xu_ex3_ap_int_req : out std_ulogic_vector(0 to 3); + -- Slow SPR Bus, PC + slowspr_val_in : in std_ulogic; + slowspr_rw_in : in std_ulogic; + slowspr_etid_in : in std_ulogic_vector(0 to 1); + slowspr_addr_in : in std_ulogic_vector(0 to 9); + slowspr_data_in : in std_ulogic_vector(64-(2**regmode) to 63); + slowspr_done_in : in std_ulogic; + slowspr_val_out : out std_ulogic; + slowspr_rw_out : out std_ulogic; + slowspr_etid_out : out std_ulogic_vector(0 to 1); + slowspr_addr_out : out std_ulogic_vector(0 to 9); + slowspr_data_out : out std_ulogic_vector(64-(2**regmode) to 63); + slowspr_done_out : out std_ulogic; + pc_fu_ram_mode : in std_ulogic; + pc_fu_ram_thread : in std_ulogic_vector(0 to 1); + fu_pc_ram_done : out std_ulogic; + fu_pc_ram_data : out std_ulogic_vector(0 to 63); + pc_fu_trace_bus_enable : in std_ulogic; + pc_fu_event_bus_enable : in std_ulogic; + pc_fu_instr_trace_mode : in std_ulogic; + pc_fu_instr_trace_tid : in std_ulogic_vector(0 to 1); + pc_fu_debug_mux_ctrls : in std_ulogic_vector(0 to 15); + pc_fu_event_count_mode : in std_ulogic_vector(0 to 2); + pc_fu_event_mux_ctrls : in std_ulogic_vector(0 to 31); + debug_data_in : in std_ulogic_vector(0 to 87); + debug_data_out : out std_ulogic_vector(0 to 87); + trace_triggers_in : in std_ulogic_vector(0 to 11); + trace_triggers_out : out std_ulogic_vector(0 to 11); + fu_pc_event_data : out std_ulogic_vector(0 to 7); + pc_fu_abist_di_0 : in std_ulogic_vector(0 to 3); + pc_fu_abist_di_1 : in std_ulogic_vector(0 to 3); + pc_fu_abist_ena_dc : in std_ulogic; + pc_fu_abist_grf_renb_0 : in std_ulogic; + pc_fu_abist_grf_renb_1 : in std_ulogic; + pc_fu_abist_grf_wenb_0 : in std_ulogic; + pc_fu_abist_grf_wenb_1 : in std_ulogic; + pc_fu_abist_raddr_0 : in std_ulogic_vector(0 to 9); + pc_fu_abist_raddr_1 : in std_ulogic_vector(0 to 9); + pc_fu_abist_raw_dc_b : in std_ulogic; + pc_fu_abist_waddr_0 : in std_ulogic_vector(0 to 9); + pc_fu_abist_waddr_1 : in std_ulogic_vector(0 to 9); + pc_fu_abist_wl144_comp_ena : in std_ulogic; + fu_pc_err_regfile_parity : out std_ulogic_vector(0 to 3); + fu_pc_err_regfile_ue : out std_ulogic_vector(0 to 3); + pc_fu_inj_regfile_parity : in std_ulogic_vector(0 to 3); + fu_xu_ex3_regfile_err_det : out std_ulogic_vector(0 to 3); + xu_fu_regfile_seq_beg : in std_ulogic; + fu_xu_regfile_seq_end : out std_ulogic; + + -- Load/Store + fu_xu_ex2_store_data : out std_ulogic_vector(0 to 63); + fu_xu_ex2_store_data_val : out std_ulogic; + xu_fu_ex5_load_val : in std_ulogic_vector(0 to 3); + xu_fu_ex5_load_tag : in std_ulogic_vector(0 to 8); + xu_fu_ex5_load_le : in std_ulogic; + xu_fu_ex5_reload_val : in std_ulogic; + xu_fu_ex6_load_data : in std_ulogic_vector(192 to 255); + -- Interface to XU + fu_xu_rf1_act : out std_ulogic_vector(0 to 3); + fu_xu_ex2_async_block : out std_ulogic_vector(0 to 3); + xu_fu_msr_fp : in std_ulogic_vector(0 to 3); + xu_fu_msr_pr : in std_ulogic_vector(0 to 3); + xu_fu_msr_gs : in std_ulogic_vector(0 to 3); + fu_iu_uc_special : out std_ulogic_vector(0 to 3); + fu_xu_ex4_cr_val : out std_ulogic_vector(0 to 3); + fu_xu_ex4_cr_noflush : out std_ulogic_vector(0 to 3); + fu_xu_ex4_cr_bf : out std_ulogic_vector(0 to 2); + fu_xu_ex4_cr : out std_ulogic_vector(0 to 3) +); + -- synopsys translate_off + -- synopsys translate_on + +end fuq; + +architecture fuq of fuq is + + + + +-- ####################### SIGNALS ####################### -- + +signal f_dcd_msr_fp_act : std_ulogic; + +signal f_dcd_ex6_frt_addr : std_ulogic_vector(0 to 5); +signal f_dcd_ex6_frt_tid : std_ulogic_vector(0 to 1); +signal f_dcd_ex6_frt_wen : std_ulogic; +signal f_dcd_ex5_frt_tid : std_ulogic_vector(0 to 1); + + +signal f_dcd_rf1_mad_act : std_ulogic; +signal f_dcd_rf1_sto_act : std_ulogic; +signal f_dcd_ex6_cancel : std_ulogic; +signal f_dcd_rf1_bypsel_a_res0 : std_ulogic; +signal f_dcd_rf1_bypsel_a_load0 : std_ulogic; +signal f_dcd_rf1_bypsel_b_res0 : std_ulogic; +signal f_dcd_rf1_bypsel_b_load0 : std_ulogic; +signal f_dcd_rf1_bypsel_c_res0 : std_ulogic; +signal f_dcd_rf1_bypsel_c_load0 : std_ulogic; +signal f_dcd_rf1_bypsel_a_res1 : std_ulogic; +signal f_dcd_rf1_bypsel_a_load1 : std_ulogic; +signal f_dcd_rf1_bypsel_b_res1 : std_ulogic; +signal f_dcd_rf1_bypsel_b_load1 : std_ulogic; +signal f_dcd_rf1_bypsel_c_res1 : std_ulogic; +signal f_dcd_rf1_bypsel_c_load1 : std_ulogic; +signal f_dcd_rf0_bypsel_a_res1 : std_ulogic; +signal f_dcd_rf0_bypsel_a_load1 : std_ulogic; +signal f_dcd_rf0_bypsel_b_res1 : std_ulogic; +signal f_dcd_rf0_bypsel_b_load1 : std_ulogic; +signal f_dcd_rf0_bypsel_c_res1 : std_ulogic; +signal f_dcd_rf0_bypsel_c_load1 : std_ulogic; +signal f_dcd_rf0_bypsel_s_res1 : std_ulogic; +signal f_dcd_rf0_bypsel_s_load1 : std_ulogic; + +signal f_fpr_ex7_load_sign : std_ulogic; +signal f_fpr_ex7_load_expo : std_ulogic_vector(3 to 13); +signal f_fpr_ex7_load_frac : std_ulogic_vector(0 to 52); +signal f_fpr_ex7_load_addr : std_ulogic_vector(0 to 7); +signal f_fpr_ex7_load_v : std_ulogic; +signal f_fpr_rf1_a_sign : std_ulogic; +signal f_fpr_rf1_a_expo : std_ulogic_vector(1 to 13) ; +signal f_fpr_rf1_a_frac : std_ulogic_vector(0 to 52) ; +signal f_fpr_rf1_c_sign : std_ulogic; +signal f_fpr_rf1_c_expo : std_ulogic_vector(1 to 13) ; +signal f_fpr_rf1_c_frac : std_ulogic_vector(0 to 52) ; +signal f_fpr_rf1_b_sign : std_ulogic; +signal f_fpr_rf1_b_expo : std_ulogic_vector(1 to 13) ; +signal f_fpr_rf1_b_frac : std_ulogic_vector(0 to 52) ; +signal f_fpr_ex7_frt_sign : std_ulogic; +signal f_fpr_ex7_frt_expo : std_ulogic_vector(1 to 13); +signal f_fpr_ex7_frt_frac : std_ulogic_vector(0 to 52); +signal f_fpr_ex8_load_sign : std_ulogic; +signal f_fpr_ex8_load_expo : std_ulogic_vector(3 to 13); +signal f_fpr_ex8_load_frac : std_ulogic_vector(0 to 52); +signal f_dcd_rf1_aop_valid : std_ulogic; +signal f_dcd_rf1_cop_valid : std_ulogic; +signal f_dcd_rf1_bop_valid : std_ulogic; +signal f_dcd_rf1_sp : std_ulogic; -- off for frsp +signal f_dcd_rf1_emin_dp : std_ulogic; -- prenorm_dp +signal f_dcd_rf1_emin_sp : std_ulogic; -- prenorm_sp, frsp +signal f_dcd_rf1_force_pass_b : std_ulogic; -- fmr,fnabbs,fabs,fneg,mtfsf +signal f_dcd_rf1_fsel_b : std_ulogic; -- fsel +signal f_dcd_rf1_from_integer_b : std_ulogic; -- fcfid (signed integer) +signal f_dcd_rf1_to_integer_b : std_ulogic; -- fcti* (signed integer 32/64) +signal f_dcd_rf1_rnd_to_int_b : std_ulogic; -- fri* +signal f_dcd_rf1_math_b : std_ulogic; -- fmul,fmad,fmsub,fadd,fsub,fnmsub,fnmadd +signal f_dcd_rf1_est_recip_b : std_ulogic; -- fres +signal f_dcd_rf1_est_rsqrt_b : std_ulogic; -- frsqrte +signal f_dcd_rf1_move_b : std_ulogic; -- fmr,fneg,fabs,fnabs +signal f_dcd_rf1_prenorm_b : std_ulogic; -- prenorm ?? need +signal f_dcd_rf1_frsp_b : std_ulogic; -- round-to-sgle-precision ?? need +signal f_dcd_rf1_compare_b : std_ulogic; -- fcomp* +signal f_dcd_rf1_ordered_b : std_ulogic; -- fcompo +signal f_dcd_rf1_div_beg : std_ulogic; -- save NAN and other special +signal f_dcd_rf1_sqrt_beg : std_ulogic; -- +signal f_dcd_rf1_force_excp_dis : std_ulogic; -- +signal f_dcd_rf1_nj_deni : std_ulogic; -- force output den to zero +signal f_dcd_rf1_nj_deno : std_ulogic; -- force output den to zero +signal f_dcd_rf1_sp_conv_b : std_ulogic; -- for sp/dp convert +signal f_dcd_rf1_word_b : std_ulogic; -- fctiw* +signal f_dcd_rf1_uns_b : std_ulogic; -- for converts unsigned +signal f_dcd_rf1_sub_op_b : std_ulogic; -- fsub, fnmsub, fmsub +signal f_dcd_rf1_op_rnd_v_b : std_ulogic; -- roundg mode = nearest +signal f_dcd_rf1_op_rnd_b : std_ulogic_vector(0 to 1); -- roundg mode = positive infinity +signal f_dcd_rf1_inv_sign_b : std_ulogic; -- fnmsub fnmadd +signal f_dcd_rf1_sign_ctl_b : std_ulogic_vector(0 to 1); -- 0:fmr/fneg 1:fneg/fnabs +signal f_dcd_rf1_sgncpy_b : std_ulogic; -- for sgncpy instruction : +signal f_dcd_rf1_fpscr_bit_data_b : std_ulogic_vector(0 to 3); --data to write to nibble (other than mtfsf) +signal f_dcd_rf1_fpscr_bit_mask_b : std_ulogic_vector(0 to 3); --enable update of bit with the nibble +signal f_dcd_rf1_fpscr_nib_mask_b : std_ulogic_vector(0 to 8); --enable update of this nibble +signal f_dcd_rf1_mv_to_scr_b : std_ulogic; --mcrfs,mtfsf,mtfsfi,mtfsb0,mtfsb1 +signal f_dcd_rf1_mv_from_scr_b : std_ulogic; --mffs +signal f_dcd_rf1_mtfsbx_b : std_ulogic; --fpscr set bit, reset bit +signal f_dcd_rf1_mcrfs_b : std_ulogic; --move fpscr field to cr and reset exceptions +signal f_dcd_rf1_mtfsf_b : std_ulogic; --move fpr data to fpscr +signal f_dcd_rf1_mtfsfi_b : std_ulogic; --move immediate data to fpscr +signal f_scr_ex7_cr_fld : std_ulogic_vector (0 to 3) ; +signal f_add_ex4_fpcc_iu : std_ulogic_vector (0 to 3) ; +signal f_rnd_ex6_res_expo : std_ulogic_vector (1 to 13) ; +signal f_rnd_ex6_res_frac : std_ulogic_vector (0 to 52) ; +signal f_rnd_ex6_res_sign : std_ulogic ; +signal f_dcd_rf1_thread_b : std_ulogic_vector(0 to 3) ; +signal f_dcd_rf1_sto_dp : std_ulogic ; +signal f_dcd_rf1_sto_sp : std_ulogic ; +signal f_dcd_rf1_sto_wd : std_ulogic ; +signal f_dcd_rf1_log2e_b : std_ulogic ; +signal f_dcd_rf1_pow2e_b : std_ulogic ; +signal f_dcd_rf1_ftdiv : std_ulogic ; +signal f_dcd_rf1_ftsqrt : std_ulogic ; +signal f_ex2_b_den_flush : std_ulogic ; +signal f_scr_ex7_fx_thread0 : std_ulogic_vector (0 to 3) ; +signal f_scr_ex7_fx_thread1 : std_ulogic_vector (0 to 3) ; +signal f_scr_ex7_fx_thread2 : std_ulogic_vector (0 to 3) ; +signal f_scr_ex7_fx_thread3 : std_ulogic_vector (0 to 3) ; +signal f_dcd_rf0_tid : std_ulogic_vector(0 to 1) ; +signal f_dcd_rf0_fra : std_ulogic_vector(0 to 5); +signal f_dcd_rf0_frb : std_ulogic_vector(0 to 5); +signal f_dcd_rf0_frc : std_ulogic_vector(0 to 5); +signal f_dcd_rf1_uc_ft_pos : std_ulogic; +signal f_dcd_rf1_uc_ft_neg : std_ulogic; +signal f_dcd_rf1_uc_fa_pos : std_ulogic; +signal f_dcd_rf1_uc_fc_pos : std_ulogic; +signal f_dcd_rf1_uc_fb_pos : std_ulogic; +signal f_dcd_rf1_uc_fc_hulp : std_ulogic; +signal f_dcd_rf1_uc_fc_0_5 : std_ulogic; +signal f_dcd_rf1_uc_fc_1_0 : std_ulogic; +signal f_dcd_rf1_uc_fc_1_minus : std_ulogic; +signal f_dcd_rf1_uc_fb_1_0 : std_ulogic; +signal f_dcd_rf1_uc_fb_0_75 : std_ulogic; +signal f_dcd_rf1_uc_fb_0_5 : std_ulogic; +signal f_dcd_ex2_uc_inc_lsb : std_ulogic; +signal f_dcd_ex2_uc_gs_v : std_ulogic; +signal f_dcd_ex2_uc_gs : std_ulogic_vector(0 to 1); +signal f_dcd_perr_sm_running : std_ulogic; +signal f_dcd_ex1_perr_force_c : std_ulogic; +signal f_dcd_ex1_perr_fsel_ovrd : std_ulogic; + +signal f_pic_ex5_fpr_wr_dis_b : std_ulogic ; +signal f_fpr_rf1_s_sign : std_ulogic ; +signal f_fpr_rf1_s_expo : std_ulogic_vector(1 to 11) ; +signal f_fpr_rf1_s_frac : std_ulogic_vector(0 to 52) ; + +signal f_mad_si : std_ulogic_vector(0 to 17) ; +signal f_mad_so : std_ulogic_vector(0 to 17) ; +signal f_dcd_si : std_ulogic; +signal f_dcd_so : std_ulogic; +signal f_fpr_si : std_ulogic; +signal f_fpr_so : std_ulogic; +signal f_sto_si : std_ulogic; +signal f_sto_so : std_ulogic; +signal gptr_scan_io : std_ulogic; + +signal time_sl_thold_1 : std_ulogic; +signal abst_sl_thold_1 : std_ulogic; +signal func_sl_thold_1 : std_ulogic_vector(0 to 1); +signal ary_nsl_thold_1 : std_ulogic; +signal cfg_sl_thold_1 : std_ulogic; +signal func_slp_sl_thold_1 : std_ulogic; +signal gptr_sl_thold_0 : std_ulogic; + +signal fce_1 : std_ulogic; +signal sg_1 : std_ulogic_vector(0 to 1); +signal clkoff_dc_b : std_ulogic; +signal act_dis : std_ulogic; +signal delay_lclkr_dc : std_ulogic_vector(0 to 9); +signal mpw1_dc_b : std_ulogic_vector(0 to 9); +signal mpw2_dc_b : std_ulogic_vector(0 to 1); + +signal fpu_enable : std_ulogic; --dc_act + +signal f_mad_ex6_uc_sign :std_ulogic; +signal f_mad_ex6_uc_zero :std_ulogic; +signal f_mad_ex3_uc_special :std_ulogic; +signal f_mad_ex3_uc_vxsqrt :std_ulogic; +signal f_mad_ex3_uc_vxsnan :std_ulogic; +signal f_mad_ex3_uc_zx :std_ulogic; +signal f_mad_ex3_uc_vxidi :std_ulogic; +signal f_mad_ex3_uc_vxzdz :std_ulogic; +signal f_mad_ex3_uc_res_sign :std_ulogic; +signal f_mad_ex3_uc_round_mode :std_ulogic_vector(0 to 1); + signal f_dcd_rf1_uc_mid :std_ulogic; + signal f_dcd_rf1_uc_end :std_ulogic; + signal f_dcd_rf1_uc_special :std_ulogic; + signal f_dcd_ex2_uc_vxsnan :std_ulogic; + signal f_dcd_ex2_uc_zx :std_ulogic; + signal f_dcd_ex2_uc_vxidi :std_ulogic; + signal f_dcd_ex2_uc_vxzdz :std_ulogic; + signal f_dcd_ex2_uc_vxsqrt :std_ulogic; + signal f_fpr_ex1_a_par :std_ulogic_vector(0 to 7); + signal f_fpr_ex1_b_par :std_ulogic_vector(0 to 7); + signal f_fpr_ex1_c_par :std_ulogic_vector(0 to 7); + signal f_fpr_ex1_s_par :std_ulogic_vector(0 to 7); + signal f_fpr_ex1_s_expo_extra :std_Ulogic; + signal f_sto_ex2_s_parity_check :std_ulogic; + signal f_mad_ex2_a_parity_check :std_ulogic; + signal f_mad_ex2_c_parity_check :std_ulogic; + signal f_mad_ex2_b_parity_check :std_ulogic; + + signal f_dcd_ex5_flush_int : std_ulogic_vector(0 to 3); + signal scan_dis_dc_b :std_ulogic; + signal scan_diag_dc :std_ulogic; + + signal spare_unused : std_ulogic_vector(0 to 5); + +---------------------------------------------------------------- +begin + + + + + + + scan_dis_dc_b <= an_ac_scan_dis_dc_b; + scan_diag_dc <= an_ac_scan_diag_dc; +------------------------------------------------------------------------ +-- Floating Point Pervasive staging, lcbctrl's + + prv: entity work.fuq_perv(fuq_perv) + generic map( + expand_type => expand_type) + port map( + vdd => vdd , + gnd => gnd , + nclk => nclk , + pc_fu_sg_3 => pc_fu_sg_3 , + pc_fu_abst_sl_thold_3 => pc_fu_abst_sl_thold_3 , + pc_fu_func_sl_thold_3 => pc_fu_func_sl_thold_3 , + pc_fu_func_slp_sl_thold_3 => pc_fu_func_slp_sl_thold_3 , + pc_fu_gptr_sl_thold_3 => pc_fu_gptr_sl_thold_3 , + pc_fu_time_sl_thold_3 => pc_fu_time_sl_thold_3 , + pc_fu_ary_nsl_thold_3 => pc_fu_ary_nsl_thold_3 , + pc_fu_cfg_sl_thold_3 => pc_fu_cfg_sl_thold_3 , + pc_fu_repr_sl_thold_3 => pc_fu_repr_sl_thold_3 , + pc_fu_fce_3 => pc_fu_fce_3 , + tc_ac_ccflush_dc => pc_fu_ccflush_dc , + tc_ac_scan_diag_dc => scan_diag_dc , + abst_sl_thold_1 => abst_sl_thold_1 , + func_sl_thold_1 => func_sl_thold_1 , + time_sl_thold_1 => time_sl_thold_1 , + ary_nsl_thold_1 => ary_nsl_thold_1 , + cfg_sl_thold_1 => cfg_sl_thold_1 , + func_slp_sl_thold_1 => func_slp_sl_thold_1 , + gptr_sl_thold_0 => gptr_sl_thold_0 , + fce_1 => fce_1 , + sg_1 => sg_1 , + clkoff_dc_b => clkoff_dc_b , + act_dis => act_dis , + delay_lclkr_dc => delay_lclkr_dc , + mpw1_dc_b => mpw1_dc_b , + mpw2_dc_b => mpw2_dc_b , + repr_scan_in => repr_scan_in , + repr_scan_out => repr_scan_out , + gptr_scan_in => gptr_scan_in , + gptr_scan_out => gptr_scan_io ); + +------------------------------------------------------------------------ +-- Floating Point Register, RF1 + + fpr: entity work.fuq_fpr(fuq_fpr) + generic map( + expand_type => expand_type) + port map( + nclk => nclk , + clkoff_b => clkoff_dc_b , + act_dis => act_dis , + flush => pc_fu_ccflush_dc , + delay_lclkra(0 to 1) => delay_lclkr_dc(0 to 1) , + delay_lclkrb(6 to 7) => delay_lclkr_dc(6 to 7) , + mpw1_ba(0 to 1) => mpw1_dc_b(0 to 1) , + mpw1_bb(6 to 7) => mpw1_dc_b(6 to 7) , + mpw2_b => mpw2_dc_b , + sg_1 => sg_1(1) , + abst_sl_thold_1 => abst_sl_thold_1 , + time_sl_thold_1 => time_sl_thold_1 , + ary_nsl_thold_1 => ary_nsl_thold_1 , + gptr_sl_thold_0 => gptr_sl_thold_0 , + fce_1 => fce_1 , + thold_1 => func_sl_thold_1(1) , + scan_dis_dc_b => scan_dis_dc_b , + scan_diag_dc => scan_diag_dc , + lbist_en_dc => an_ac_lbist_en_dc , + an_ac_abist_mode_dc => an_ac_abist_mode_dc , + an_ac_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc , + f_dcd_msr_fp_act => f_dcd_msr_fp_act , + + bx_fu_rp_abst_scan_out => bx_fu_rp_abst_scan_out , + bx_rp_abst_scan_out => bx_rp_abst_scan_out , + rp_bx_abst_scan_in => rp_bx_abst_scan_in , + rp_fu_bx_abst_scan_in => rp_fu_bx_abst_scan_in , + rp_bx_func_scan_in => rp_bx_func_scan_in , + rp_fu_bx_func_scan_in => rp_fu_bx_func_scan_in , + bx_fu_rp_func_scan_out => bx_fu_rp_func_scan_out , + bx_rp_func_scan_out => bx_rp_func_scan_out , + + pc_fu_bolt_sl_thold_3 => pc_fu_bolt_sl_thold_3 , + pc_fu_bo_enable_3 => pc_fu_bo_enable_3 , + pc_fu_bo_unload => pc_fu_bo_unload , + pc_fu_bo_load => pc_fu_bo_load , + pc_fu_bo_reset => pc_fu_bo_reset , + pc_fu_bo_shdata => pc_fu_bo_shdata , + pc_fu_bo_select => pc_fu_bo_select , + fu_pc_bo_fail => fu_pc_bo_fail , + fu_pc_bo_diagout => fu_pc_bo_diagout , + + iu_fu_rf0_fra_v => iu_fu_rf0_fra_v , + iu_fu_rf0_frb_v => iu_fu_rf0_frb_v , + iu_fu_rf0_frc_v => iu_fu_rf0_frc_v , + iu_fu_rf0_str_v => iu_fu_rf0_str_val , + f_dcd_perr_sm_running => f_dcd_perr_sm_running , + + f_fpr_si => f_fpr_si , + f_fpr_so => f_fpr_so , + f_fpr_ab_si => abst_scan_in , + f_fpr_ab_so => abst_scan_out , + time_scan_in => time_scan_in , + time_scan_out => time_scan_out , + gptr_scan_in => gptr_scan_io , + gptr_scan_out => gptr_scan_out , + vdd => vdd , + gnd => gnd , + pc_fu_abist_di_0 => pc_fu_abist_di_0 , + pc_fu_abist_di_1 => pc_fu_abist_di_1 , + pc_fu_abist_ena_dc => pc_fu_abist_ena_dc , + pc_fu_abist_grf_renb_0 => pc_fu_abist_grf_renb_0 , + pc_fu_abist_grf_renb_1 => pc_fu_abist_grf_renb_1 , + pc_fu_abist_grf_wenb_0 => pc_fu_abist_grf_wenb_0 , + pc_fu_abist_grf_wenb_1 => pc_fu_abist_grf_wenb_1 , + pc_fu_abist_raddr_0 => pc_fu_abist_raddr_0 , + pc_fu_abist_raddr_1 => pc_fu_abist_raddr_1 , + pc_fu_abist_raw_dc_b => pc_fu_abist_raw_dc_b , + pc_fu_abist_waddr_0 => pc_fu_abist_waddr_0 , + pc_fu_abist_waddr_1 => pc_fu_abist_waddr_1 , + pc_fu_abist_wl144_comp_ena => pc_fu_abist_wl144_comp_ena , + pc_fu_inj_regfile_parity => pc_fu_inj_regfile_parity , + ------------------------------------------------ + f_dcd_rf0_tid => f_dcd_rf0_tid , + f_dcd_rf0_fra => f_dcd_rf0_fra , --uc_hook + --f_dcd_rf0_fra_slow(4) => f_dcd_rf0_fra_slow(4) ,--i--fpr-- --uc_hook + f_dcd_rf0_frb => f_dcd_rf0_frb , + f_dcd_rf0_frc => f_dcd_rf0_frc , + iu_fu_rf0_ldst_tid => iu_fu_rf0_ldst_tid , + iu_fu_rf0_ldst_tag => iu_fu_rf0_ldst_tag , + f_dcd_rf0_bypsel_a_res1 => f_dcd_rf0_bypsel_a_res1 , + f_dcd_rf0_bypsel_a_load1 => f_dcd_rf0_bypsel_a_load1 , + f_dcd_rf0_bypsel_b_res1 => f_dcd_rf0_bypsel_b_res1 , + f_dcd_rf0_bypsel_b_load1 => f_dcd_rf0_bypsel_b_load1 , + f_dcd_rf0_bypsel_c_res1 => f_dcd_rf0_bypsel_c_res1 , + f_dcd_rf0_bypsel_c_load1 => f_dcd_rf0_bypsel_c_load1 , + f_dcd_rf0_bypsel_s_res1 => f_dcd_rf0_bypsel_s_res1 , + f_dcd_rf0_bypsel_s_load1 => f_dcd_rf0_bypsel_s_load1 , + ------------------------------------------------ + f_dcd_ex6_frt_addr => f_dcd_ex6_frt_addr , + f_dcd_ex5_frt_tid => f_dcd_ex5_frt_tid , + f_dcd_ex6_frt_tid => f_dcd_ex6_frt_tid , + f_dcd_ex6_frt_wen => f_dcd_ex6_frt_wen , + f_rnd_ex6_res_expo => f_rnd_ex6_res_expo , + f_rnd_ex6_res_frac => f_rnd_ex6_res_frac , + f_rnd_ex6_res_sign => f_rnd_ex6_res_sign , + ------------------------------------------------ + f_dcd_ex5_flush_int => f_dcd_ex5_flush_int , + xu_fu_ex5_load_tag => xu_fu_ex5_load_tag , + xu_fu_ex5_load_val => xu_fu_ex5_load_val , + xu_fu_ex6_load_data => xu_fu_ex6_load_data , + ------------------------------------------------ + f_fpr_ex7_load_addr => f_fpr_ex7_load_addr , + f_fpr_ex7_load_v => f_fpr_ex7_load_v , + f_fpr_ex7_load_sign => f_fpr_ex7_load_sign , + f_fpr_ex7_load_expo => f_fpr_ex7_load_expo , + f_fpr_ex7_load_frac => f_fpr_ex7_load_frac , + f_fpr_rf1_s_sign => f_fpr_rf1_s_sign , + f_fpr_rf1_s_expo => f_fpr_rf1_s_expo , + f_fpr_rf1_s_frac => f_fpr_rf1_s_frac , + f_fpr_rf1_a_sign => f_fpr_rf1_a_sign , + f_fpr_rf1_a_expo => f_fpr_rf1_a_expo , + f_fpr_rf1_a_frac => f_fpr_rf1_a_frac , + f_fpr_rf1_c_sign => f_fpr_rf1_c_sign , + f_fpr_rf1_c_expo => f_fpr_rf1_c_expo , + f_fpr_rf1_c_frac => f_fpr_rf1_c_frac , + f_fpr_rf1_b_sign => f_fpr_rf1_b_sign , + f_fpr_rf1_b_expo => f_fpr_rf1_b_expo , + f_fpr_rf1_b_frac => f_fpr_rf1_b_frac , + f_fpr_ex1_s_expo_extra => f_fpr_ex1_s_expo_extra , + f_fpr_ex1_s_par => f_fpr_ex1_s_par , + f_fpr_ex1_a_par => f_fpr_ex1_a_par , + f_fpr_ex1_b_par => f_fpr_ex1_b_par , + f_fpr_ex1_c_par => f_fpr_ex1_c_par ); + + +------------------------------------------------------------------------ +-- Store + + sto: entity work.fuq_sto(fuq_sto) + generic map( + expand_type => expand_type) + port map( + vdd => vdd , + gnd => gnd , + clkoff_b => clkoff_dc_b , + act_dis => act_dis , + flush => pc_fu_ccflush_dc , + delay_lclkr => delay_lclkr_dc(1 to 2) , + mpw1_b => mpw1_dc_b(1 to 2) , + mpw2_b => mpw2_dc_b(0 to 0) , + sg_1 => sg_1(1) , + thold_1 => func_sl_thold_1(1) , + fpu_enable => fpu_enable , + nclk => nclk , + f_sto_si => f_sto_si , + f_sto_so => f_sto_so , + f_dcd_rf1_sto_act => f_dcd_rf1_sto_act , + + f_fpr_ex1_s_expo_extra => f_fpr_ex1_s_expo_extra , + f_fpr_ex1_s_par => f_fpr_ex1_s_par , + f_sto_ex2_s_parity_check => f_sto_ex2_s_parity_check , + ------------------------------------------------ + f_dcd_rf1_sto_dp => f_dcd_rf1_sto_dp , + f_dcd_rf1_sto_sp => f_dcd_rf1_sto_sp , + f_dcd_rf1_sto_wd => f_dcd_rf1_sto_wd , + f_byp_rf1_s_sign => f_fpr_rf1_s_sign , + f_byp_rf1_s_expo => f_fpr_rf1_s_expo , + f_byp_rf1_s_frac => f_fpr_rf1_s_frac , + f_sto_ex2_sto_data => fu_xu_ex2_store_data ); + ------------------------------------------------ + + + +------------------------------------------------------------------------ +-- Main Pipe + + + fpu_enable <= f_dcd_msr_fp_act; + + f_dcd_rf1_bypsel_a_res1 <= '0' ; + f_dcd_rf1_bypsel_a_load1 <= '0' ; + f_dcd_rf1_bypsel_b_res1 <= '0' ; + f_dcd_rf1_bypsel_b_load1 <= '0' ; + f_dcd_rf1_bypsel_c_res1 <= '0' ; + f_dcd_rf1_bypsel_c_load1 <= '0' ; + f_fpr_ex8_load_sign <= '0'; + f_fpr_ex8_load_expo(3 to 13) <= (others => '0'); + f_fpr_ex8_load_frac(0 to 52) <= (others => '0'); + + f_fpr_ex7_frt_sign <= '0' ; + f_fpr_ex7_frt_expo(1 to 13) <= (others => '0'); + f_fpr_ex7_frt_frac(0 to 52) <= (others => '0'); + + + mad: entity work.fuq_mad(fuq_mad) + generic map( + expand_type => expand_type) + port map( + f_dcd_ex6_cancel => f_dcd_ex6_cancel , + f_dcd_rf1_bypsel_a_res0 => f_dcd_rf1_bypsel_a_res0 , + f_dcd_rf1_bypsel_a_res1 => f_dcd_rf1_bypsel_a_res1 , + f_dcd_rf1_bypsel_a_load0 => f_dcd_rf1_bypsel_a_load0 , + f_dcd_rf1_bypsel_a_load1 => f_dcd_rf1_bypsel_a_load1 , + f_dcd_rf1_bypsel_b_res0 => f_dcd_rf1_bypsel_b_res0 , + f_dcd_rf1_bypsel_b_res1 => f_dcd_rf1_bypsel_b_res1 , + f_dcd_rf1_bypsel_b_load0 => f_dcd_rf1_bypsel_b_load0 , + f_dcd_rf1_bypsel_b_load1 => f_dcd_rf1_bypsel_b_load1 , + f_dcd_rf1_bypsel_c_res0 => f_dcd_rf1_bypsel_c_res0 , + f_dcd_rf1_bypsel_c_res1 => f_dcd_rf1_bypsel_c_res1 , + f_dcd_rf1_bypsel_c_load0 => f_dcd_rf1_bypsel_c_load0 , + f_dcd_rf1_bypsel_c_load1 => f_dcd_rf1_bypsel_c_load1 , + f_dcd_rf1_force_excp_dis => f_dcd_rf1_force_excp_dis , + f_fpr_ex7_frt_sign => f_fpr_ex7_frt_sign , + f_fpr_ex7_frt_expo(1 to 13) => f_fpr_ex7_frt_expo(1 to 13) , + f_fpr_ex7_frt_frac(0 to 52) => f_fpr_ex7_frt_frac(0 to 52) , + f_fpr_ex7_load_sign => f_fpr_ex8_load_sign , + f_fpr_ex7_load_expo(3 to 13) => f_fpr_ex8_load_expo(3 to 13) , + f_fpr_ex7_load_frac(0 to 52) => f_fpr_ex8_load_frac(0 to 52) , + ------------------------------------------------ + ------------------------------------------------ + f_fpr_ex6_load_sign => f_fpr_ex7_load_sign , + f_fpr_ex6_load_expo => f_fpr_ex7_load_expo , + f_fpr_ex6_load_frac => f_fpr_ex7_load_frac , + f_fpr_rf1_a_sign => f_fpr_rf1_a_sign , + f_fpr_rf1_a_expo => f_fpr_rf1_a_expo , + f_fpr_rf1_a_frac => f_fpr_rf1_a_frac , + f_fpr_rf1_c_sign => f_fpr_rf1_c_sign , + f_fpr_rf1_c_expo => f_fpr_rf1_c_expo , + f_fpr_rf1_c_frac => f_fpr_rf1_c_frac , + f_fpr_rf1_b_sign => f_fpr_rf1_b_sign , + f_fpr_rf1_b_expo => f_fpr_rf1_b_expo , + f_fpr_rf1_b_frac => f_fpr_rf1_b_frac , + ------------------------------------------------ + f_dcd_rf1_aop_valid => f_dcd_rf1_aop_valid , + f_dcd_rf1_cop_valid => f_dcd_rf1_cop_valid , + f_dcd_rf1_bop_valid => f_dcd_rf1_bop_valid , + f_dcd_rf1_sp => f_dcd_rf1_sp , + f_dcd_rf1_emin_dp => f_dcd_rf1_emin_dp , + f_dcd_rf1_emin_sp => f_dcd_rf1_emin_sp , + f_dcd_rf1_force_pass_b => f_dcd_rf1_force_pass_b , + f_dcd_rf1_fsel_b => f_dcd_rf1_fsel_b , + f_dcd_rf1_from_integer_b => f_dcd_rf1_from_integer_b , + f_dcd_rf1_to_integer_b => f_dcd_rf1_to_integer_b , + f_dcd_rf1_rnd_to_int_b => f_dcd_rf1_rnd_to_int_b , + f_dcd_rf1_math_b => f_dcd_rf1_math_b , + f_dcd_rf1_est_recip_b => f_dcd_rf1_est_recip_b , + f_dcd_rf1_est_rsqrt_b => f_dcd_rf1_est_rsqrt_b , + f_dcd_rf1_move_b => f_dcd_rf1_move_b , + f_dcd_rf1_prenorm_b => f_dcd_rf1_prenorm_b , + f_dcd_rf1_frsp_b => f_dcd_rf1_frsp_b , + f_dcd_rf1_compare_b => f_dcd_rf1_compare_b , + f_dcd_rf1_ordered_b => f_dcd_rf1_ordered_b , + f_dcd_rf1_nj_deni => f_dcd_rf1_nj_deni , + f_dcd_rf1_nj_deno => f_dcd_rf1_nj_deno , + f_dcd_rf1_sp_conv_b => f_dcd_rf1_sp_conv_b , + f_dcd_rf1_word_b => f_dcd_rf1_word_b , + f_dcd_rf1_uns_b => f_dcd_rf1_uns_b , + f_dcd_rf1_sub_op_b => f_dcd_rf1_sub_op_b , + f_dcd_rf1_op_rnd_v_b => f_dcd_rf1_op_rnd_v_b , + f_dcd_rf1_op_rnd_b => f_dcd_rf1_op_rnd_b , + f_dcd_rf1_inv_sign_b => f_dcd_rf1_inv_sign_b , + f_dcd_rf1_sign_ctl_b => f_dcd_rf1_sign_ctl_b , + f_dcd_rf1_sgncpy_b => f_dcd_rf1_sgncpy_b , + f_dcd_rf1_fpscr_bit_data_b => f_dcd_rf1_fpscr_bit_data_b , + f_dcd_rf1_fpscr_bit_mask_b => f_dcd_rf1_fpscr_bit_mask_b , + f_dcd_rf1_fpscr_nib_mask_b => f_dcd_rf1_fpscr_nib_mask_b , + f_dcd_rf1_mv_to_scr_b => f_dcd_rf1_mv_to_scr_b , + f_dcd_rf1_mv_from_scr_b => f_dcd_rf1_mv_from_scr_b , + f_dcd_rf1_mtfsbx_b => f_dcd_rf1_mtfsbx_b , + f_dcd_rf1_mcrfs_b => f_dcd_rf1_mcrfs_b , + f_dcd_rf1_mtfsf_b => f_dcd_rf1_mtfsf_b , + f_dcd_rf1_mtfsfi_b => f_dcd_rf1_mtfsfi_b , + f_dcd_rf1_log2e_b => f_dcd_rf1_log2e_b , + f_dcd_rf1_pow2e_b => f_dcd_rf1_pow2e_b , + f_dcd_rf1_ftdiv => f_dcd_rf1_ftdiv , + f_dcd_rf1_ftsqrt => f_dcd_rf1_ftsqrt , + f_dcd_ex1_perr_force_c => f_dcd_ex1_perr_force_c , + f_dcd_ex1_perr_fsel_ovrd => f_dcd_ex1_perr_fsel_ovrd , + f_add_ex4_fpcc_iu => f_add_ex4_fpcc_iu , + f_pic_ex5_fpr_wr_dis_b => f_pic_ex5_fpr_wr_dis_b , + f_scr_ex7_cr_fld => f_scr_ex7_cr_fld , + f_rnd_ex6_res_expo => f_rnd_ex6_res_expo , + f_rnd_ex6_res_frac => f_rnd_ex6_res_frac , + f_rnd_ex6_res_sign => f_rnd_ex6_res_sign , + f_ex2_b_den_flush => f_ex2_b_den_flush , + f_scr_ex7_fx_thread0 => f_scr_ex7_fx_thread0 , + f_scr_ex7_fx_thread1 => f_scr_ex7_fx_thread1 , + f_scr_ex7_fx_thread2 => f_scr_ex7_fx_thread2 , + f_scr_ex7_fx_thread3 => f_scr_ex7_fx_thread3 , + + ------------------------------------------------ + f_dcd_rf1_uc_ft_pos => f_dcd_rf1_uc_ft_pos , + f_dcd_rf1_uc_ft_neg => f_dcd_rf1_uc_ft_neg , + f_dcd_rf1_uc_fa_pos => f_dcd_rf1_uc_fa_pos , + f_dcd_rf1_uc_fc_pos => f_dcd_rf1_uc_fc_pos , + f_dcd_rf1_uc_fb_pos => f_dcd_rf1_uc_fb_pos , + f_dcd_rf1_uc_fc_hulp => f_dcd_rf1_uc_fc_hulp , + f_dcd_rf1_uc_fc_0_5 => f_dcd_rf1_uc_fc_0_5 , + f_dcd_rf1_uc_fc_1_0 => f_dcd_rf1_uc_fc_1_0 , + f_dcd_rf1_uc_fc_1_minus => f_dcd_rf1_uc_fc_1_minus , + f_dcd_rf1_uc_fb_1_0 => f_dcd_rf1_uc_fb_1_0 , + f_dcd_rf1_uc_fb_0_75 => f_dcd_rf1_uc_fb_0_75 , + f_dcd_rf1_uc_fb_0_5 => f_dcd_rf1_uc_fb_0_5 , + f_dcd_ex2_uc_inc_lsb => f_dcd_ex2_uc_inc_lsb , + f_dcd_ex2_uc_gs_v => f_dcd_ex2_uc_gs_v , + f_dcd_ex2_uc_gs => f_dcd_ex2_uc_gs , + f_dcd_rf1_div_beg => f_dcd_rf1_div_beg , + f_dcd_rf1_sqrt_beg => f_dcd_rf1_sqrt_beg , + f_dcd_rf1_uc_mid => f_dcd_rf1_uc_mid , + f_dcd_rf1_uc_end => f_dcd_rf1_uc_end , + f_dcd_rf1_uc_special => f_dcd_rf1_uc_special , + f_dcd_ex2_uc_vxsnan => f_dcd_ex2_uc_vxsnan , + f_dcd_ex2_uc_zx => f_dcd_ex2_uc_zx , + f_dcd_ex2_uc_vxidi => f_dcd_ex2_uc_vxidi , + f_dcd_ex2_uc_vxzdz => f_dcd_ex2_uc_vxzdz , + f_dcd_ex2_uc_vxsqrt => f_dcd_ex2_uc_vxsqrt , + f_mad_ex6_uc_sign => f_mad_ex6_uc_sign , + f_mad_ex6_uc_zero => f_mad_ex6_uc_zero , + f_mad_ex3_uc_special => f_mad_ex3_uc_special , + ------------------------------------------------------------------ + f_mad_ex3_uc_vxsnan => f_mad_ex3_uc_vxsnan , + f_mad_ex3_uc_zx => f_mad_ex3_uc_zx , + f_mad_ex3_uc_vxsqrt => f_mad_ex3_uc_vxsqrt , + f_mad_ex3_uc_vxidi => f_mad_ex3_uc_vxidi , + f_mad_ex3_uc_vxzdz => f_mad_ex3_uc_vxzdz , + f_mad_ex3_uc_res_sign => f_mad_ex3_uc_res_sign , + f_mad_ex3_uc_round_mode(0 to 1) => f_mad_ex3_uc_round_mode(0 to 1) , + ------------------------------------------- + f_fpr_ex1_a_par => f_fpr_ex1_a_par , + f_fpr_ex1_b_par => f_fpr_ex1_b_par , + f_fpr_ex1_c_par => f_fpr_ex1_c_par , + f_mad_ex2_a_parity_check => f_mad_ex2_a_parity_check , + f_mad_ex2_c_parity_check => f_mad_ex2_c_parity_check , + f_mad_ex2_b_parity_check => f_mad_ex2_b_parity_check , + + ------------------------------------------------ + rf1_thread_b => f_dcd_rf1_thread_b , + ------------------------------------------------ + vdd => vdd , + gnd => gnd , + scan_in => f_mad_si(0 to 17) , + scan_out => f_mad_so(0 to 17) , + clkoff_b => clkoff_dc_b , + act_dis => act_dis , + flush => pc_fu_ccflush_dc , + delay_lclkr => delay_lclkr_dc(1 to 7) , + mpw1_b => mpw1_dc_b(1 to 7) , + mpw2_b => mpw2_dc_b , + sg_1 => sg_1(0) , + thold_1 => func_sl_thold_1(0) , + fpu_enable => fpu_enable , + f_dcd_rf1_act => f_dcd_rf1_mad_act , + nclk => nclk ); + + ------------------------------------------------ + + + +------------------------------------------------------------------------ +-- Control and Decode + + dcd: entity work.fuq_dcd(fuq_dcd) + generic map( + expand_type => expand_type , + eff_ifar => eff_ifar , + regmode => regmode ) + port map( + nclk => nclk , + clkoff_b => clkoff_dc_b , + act_dis => act_dis , + flush => pc_fu_ccflush_dc , + delay_lclkr => delay_lclkr_dc , + mpw1_b => mpw1_dc_b , + mpw2_b => mpw2_dc_b , + sg_1 => sg_1(1) , + thold_1 => func_sl_thold_1(1) , + cfg_sl_thold_1 => cfg_sl_thold_1 , + func_slp_sl_thold_1 => func_slp_sl_thold_1 , + f_dcd_si => f_dcd_si , + f_dcd_so => f_dcd_so , + dcfg_scan_in => dcfg_scan_in , + dcfg_scan_out => dcfg_scan_out , + bcfg_scan_in => bcfg_scan_in , + bcfg_scan_out => bcfg_scan_out , + ccfg_scan_in => ccfg_scan_in , + ccfg_scan_out => ccfg_scan_out , + vdd => vdd , + gnd => gnd , + f_dcd_msr_fp_act => f_dcd_msr_fp_act , + fu_xu_rf1_act => fu_xu_rf1_act , + fu_xu_ex2_async_block => fu_xu_ex2_async_block , + ------------------------------------------------ + iu_fu_rf0_instr_v => iu_fu_rf0_instr_v , + iu_fu_rf0_instr => iu_fu_rf0_instr , + iu_fu_rf0_fra_v => iu_fu_rf0_fra_v , + iu_fu_rf0_frb_v => iu_fu_rf0_frb_v , + iu_fu_rf0_frc_v => iu_fu_rf0_frc_v , + iu_fu_rf0_fra => iu_fu_rf0_fra , + iu_fu_rf0_frb => iu_fu_rf0_frb , + iu_fu_rf0_frc => iu_fu_rf0_frc , + iu_fu_rf0_tid => iu_fu_rf0_tid , + iu_fu_rf0_frt => iu_fu_rf0_frt , + iu_fu_rf0_ifar => iu_fu_rf0_ifar , + iu_fu_rf0_str_val => iu_fu_rf0_str_val , + iu_fu_rf0_ldst_val => iu_fu_rf0_ldst_val , + iu_fu_rf0_ldst_tid => iu_fu_rf0_ldst_tid , + iu_fu_rf0_ldst_tag => iu_fu_rf0_ldst_tag , + iu_fu_rf0_bypsel => iu_fu_rf0_bypsel , + iu_fu_rf0_instr_match => iu_fu_rf0_instr_match , + iu_fu_rf0_is_ucode => iu_fu_rf0_is_ucode , + iu_fu_rf0_ucfmul => iu_fu_rf0_ucfmul , + iu_fu_is2_tid_decode => iu_fu_is2_tid_decode , + iu_fu_ex2_n_flush => iu_fu_ex2_n_flush , + f_fpr_ex7_load_addr => f_fpr_ex7_load_addr , + f_fpr_ex7_load_v => f_fpr_ex7_load_v , + ------------------------------------------------ + xu_is2_flush => xu_is2_flush , + xu_rf0_flush => xu_rf0_flush , + xu_rf1_flush => xu_rf1_flush , + xu_ex1_flush => xu_ex1_flush , + xu_ex2_flush => xu_ex2_flush , + xu_ex3_flush => xu_ex3_flush , + xu_ex4_flush => xu_ex4_flush , + xu_ex5_flush => xu_ex5_flush , + f_dcd_ex5_flush_int => f_dcd_ex5_flush_int , + xu_fu_ex5_reload_val => xu_fu_ex5_reload_val , + xu_fu_ex5_load_val => xu_fu_ex5_load_val , + f_ex2_b_den_flush => f_ex2_b_den_flush , + f_scr_ex7_fx_thread0 => f_scr_ex7_fx_thread0 , + f_scr_ex7_fx_thread1 => f_scr_ex7_fx_thread1 , + f_scr_ex7_fx_thread2 => f_scr_ex7_fx_thread2 , + f_scr_ex7_fx_thread3 => f_scr_ex7_fx_thread3 , + ------------------------------------------------ + f_dcd_ex1_perr_force_c => f_dcd_ex1_perr_force_c , + f_dcd_ex1_perr_fsel_ovrd => f_dcd_ex1_perr_fsel_ovrd , + f_dcd_perr_sm_running => f_dcd_perr_sm_running , + f_add_ex4_fpcc_iu => f_add_ex4_fpcc_iu , + f_pic_ex5_fpr_wr_dis_b => f_pic_ex5_fpr_wr_dis_b , + f_scr_ex7_cr_fld => f_scr_ex7_cr_fld , + f_dcd_rf1_aop_valid => f_dcd_rf1_aop_valid , + f_dcd_rf1_cop_valid => f_dcd_rf1_cop_valid , + f_dcd_rf1_bop_valid => f_dcd_rf1_bop_valid , + f_dcd_rf1_sp => f_dcd_rf1_sp , + f_dcd_rf1_emin_dp => f_dcd_rf1_emin_dp , + f_dcd_rf1_emin_sp => f_dcd_rf1_emin_sp , + f_dcd_rf1_force_pass_b => f_dcd_rf1_force_pass_b , + f_dcd_rf1_fsel_b => f_dcd_rf1_fsel_b , + f_dcd_rf1_from_integer_b => f_dcd_rf1_from_integer_b , + f_dcd_rf1_to_integer_b => f_dcd_rf1_to_integer_b , + f_dcd_rf1_rnd_to_int_b => f_dcd_rf1_rnd_to_int_b , + f_dcd_rf1_math_b => f_dcd_rf1_math_b , + f_dcd_rf1_est_recip_b => f_dcd_rf1_est_recip_b , + f_dcd_rf1_est_rsqrt_b => f_dcd_rf1_est_rsqrt_b , + f_dcd_rf1_move_b => f_dcd_rf1_move_b , + f_dcd_rf1_prenorm_b => f_dcd_rf1_prenorm_b , + f_dcd_rf1_frsp_b => f_dcd_rf1_frsp_b , + f_dcd_rf1_compare_b => f_dcd_rf1_compare_b , + f_dcd_rf1_ordered_b => f_dcd_rf1_ordered_b , + f_dcd_rf1_force_excp_dis => f_dcd_rf1_force_excp_dis , + f_dcd_rf1_nj_deni => f_dcd_rf1_nj_deni , + f_dcd_rf1_nj_deno => f_dcd_rf1_nj_deno , + f_dcd_rf1_sp_conv_b => f_dcd_rf1_sp_conv_b , + f_dcd_rf1_uns_b => f_dcd_rf1_uns_b , + f_dcd_rf1_word_b => f_dcd_rf1_word_b , + f_dcd_rf1_sub_op_b => f_dcd_rf1_sub_op_b , + f_dcd_rf1_op_rnd_v_b => f_dcd_rf1_op_rnd_v_b , + f_dcd_rf1_op_rnd_b => f_dcd_rf1_op_rnd_b , + f_dcd_rf1_inv_sign_b => f_dcd_rf1_inv_sign_b , + f_dcd_rf1_sign_ctl_b => f_dcd_rf1_sign_ctl_b , + f_dcd_rf1_sgncpy_b => f_dcd_rf1_sgncpy_b , + f_dcd_rf1_fpscr_bit_data_b => f_dcd_rf1_fpscr_bit_data_b , + f_dcd_rf1_fpscr_bit_mask_b => f_dcd_rf1_fpscr_bit_mask_b , + f_dcd_rf1_fpscr_nib_mask_b => f_dcd_rf1_fpscr_nib_mask_b , + f_dcd_rf1_mv_to_scr_b => f_dcd_rf1_mv_to_scr_b , + f_dcd_rf1_mv_from_scr_b => f_dcd_rf1_mv_from_scr_b , + f_dcd_rf1_mtfsbx_b => f_dcd_rf1_mtfsbx_b , + f_dcd_rf1_mcrfs_b => f_dcd_rf1_mcrfs_b , + f_dcd_rf1_mtfsf_b => f_dcd_rf1_mtfsf_b , + f_dcd_rf1_mtfsfi_b => f_dcd_rf1_mtfsfi_b , + f_dcd_rf1_thread_b => f_dcd_rf1_thread_b , + f_dcd_rf1_sto_dp => f_dcd_rf1_sto_dp , + f_dcd_rf1_sto_sp => f_dcd_rf1_sto_sp , + f_dcd_rf1_sto_wd => f_dcd_rf1_sto_wd , + f_dcd_rf1_log2e_b => f_dcd_rf1_log2e_b , + f_dcd_rf1_pow2e_b => f_dcd_rf1_pow2e_b , + f_dcd_rf1_ftdiv => f_dcd_rf1_ftdiv , + f_dcd_rf1_ftsqrt => f_dcd_rf1_ftsqrt , + f_dcd_ex6_cancel => f_dcd_ex6_cancel , + f_dcd_rf1_mad_act => f_dcd_rf1_mad_act , + f_dcd_rf1_sto_act => f_dcd_rf1_sto_act , + f_dcd_rf1_bypsel_a_res0 => f_dcd_rf1_bypsel_a_res0 , + f_dcd_rf1_bypsel_a_load0 => f_dcd_rf1_bypsel_a_load0 , + f_dcd_rf1_bypsel_b_res0 => f_dcd_rf1_bypsel_b_res0 , + f_dcd_rf1_bypsel_b_load0 => f_dcd_rf1_bypsel_b_load0 , + f_dcd_rf1_bypsel_c_res0 => f_dcd_rf1_bypsel_c_res0 , + f_dcd_rf1_bypsel_c_load0 => f_dcd_rf1_bypsel_c_load0 , + f_dcd_rf0_bypsel_a_res1 => f_dcd_rf0_bypsel_a_res1 , + f_dcd_rf0_bypsel_a_load1 => f_dcd_rf0_bypsel_a_load1 , + f_dcd_rf0_bypsel_b_res1 => f_dcd_rf0_bypsel_b_res1 , + f_dcd_rf0_bypsel_b_load1 => f_dcd_rf0_bypsel_b_load1 , + f_dcd_rf0_bypsel_c_res1 => f_dcd_rf0_bypsel_c_res1 , + f_dcd_rf0_bypsel_c_load1 => f_dcd_rf0_bypsel_c_load1 , + f_dcd_rf0_bypsel_s_res1 => f_dcd_rf0_bypsel_s_res1 , + f_dcd_rf0_bypsel_s_load1 => f_dcd_rf0_bypsel_s_load1 , + ------------------------------------------------ + f_dcd_rf0_tid => f_dcd_rf0_tid , + f_dcd_rf0_fra => f_dcd_rf0_fra , + f_dcd_rf0_frb => f_dcd_rf0_frb , + f_dcd_rf0_frc => f_dcd_rf0_frc , + f_dcd_rf1_div_beg => f_dcd_rf1_div_beg , + f_dcd_rf1_sqrt_beg => f_dcd_rf1_sqrt_beg , + f_dcd_rf1_uc_ft_pos => f_dcd_rf1_uc_ft_pos , + f_dcd_rf1_uc_ft_neg => f_dcd_rf1_uc_ft_neg , + f_dcd_rf1_uc_fa_pos => f_dcd_rf1_uc_fa_pos , + f_dcd_rf1_uc_fc_pos => f_dcd_rf1_uc_fc_pos , + f_dcd_rf1_uc_fb_pos => f_dcd_rf1_uc_fb_pos , + f_dcd_rf1_uc_fc_hulp => f_dcd_rf1_uc_fc_hulp , + f_dcd_rf1_uc_fc_0_5 => f_dcd_rf1_uc_fc_0_5 , + f_dcd_rf1_uc_fc_1_0 => f_dcd_rf1_uc_fc_1_0 , + f_dcd_rf1_uc_fc_1_minus => f_dcd_rf1_uc_fc_1_minus , + f_dcd_rf1_uc_fb_1_0 => f_dcd_rf1_uc_fb_1_0 , + f_dcd_rf1_uc_fb_0_75 => f_dcd_rf1_uc_fb_0_75 , + f_dcd_rf1_uc_fb_0_5 => f_dcd_rf1_uc_fb_0_5 , + f_dcd_ex2_uc_inc_lsb => f_dcd_ex2_uc_inc_lsb , + f_dcd_rf1_uc_mid => f_dcd_rf1_uc_mid , + f_dcd_rf1_uc_end => f_dcd_rf1_uc_end , + fu_iu_uc_special => fu_iu_uc_special , + f_dcd_rf1_uc_special => f_dcd_rf1_uc_special , + f_dcd_ex2_uc_gs_v => f_dcd_ex2_uc_gs_v , + f_dcd_ex2_uc_gs => f_dcd_ex2_uc_gs , + f_dcd_ex2_uc_vxsnan => f_dcd_ex2_uc_vxsnan , + f_dcd_ex2_uc_zx => f_dcd_ex2_uc_zx , + f_dcd_ex2_uc_vxidi => f_dcd_ex2_uc_vxidi , + f_dcd_ex2_uc_vxzdz => f_dcd_ex2_uc_vxzdz , + f_dcd_ex2_uc_vxsqrt => f_dcd_ex2_uc_vxsqrt , + f_mad_ex6_uc_sign => f_mad_ex6_uc_sign , + f_mad_ex6_uc_zero => f_mad_ex6_uc_zero , + f_mad_ex3_uc_special => f_mad_ex3_uc_special , + f_mad_ex3_uc_vxsnan => f_mad_ex3_uc_vxsnan , + f_mad_ex3_uc_zx => f_mad_ex3_uc_zx , + f_mad_ex3_uc_vxidi => f_mad_ex3_uc_vxidi , + f_mad_ex3_uc_vxzdz => f_mad_ex3_uc_vxzdz , + f_mad_ex3_uc_vxsqrt => f_mad_ex3_uc_vxsqrt , + f_mad_ex3_uc_res_sign => f_mad_ex3_uc_res_sign , + f_mad_ex3_uc_round_mode => f_mad_ex3_uc_round_mode , + ------------------------------------------------ + slowspr_val_in => slowspr_val_in , + slowspr_rw_in => slowspr_rw_in , + slowspr_etid_in => slowspr_etid_in , + slowspr_addr_in => slowspr_addr_in , + slowspr_data_in => slowspr_data_in , + slowspr_done_in => slowspr_done_in , + slowspr_val_out => slowspr_val_out , + slowspr_rw_out => slowspr_rw_out , + slowspr_etid_out => slowspr_etid_out , + slowspr_addr_out => slowspr_addr_out , + slowspr_data_out => slowspr_data_out , + slowspr_done_out => slowspr_done_out , + pc_fu_trace_bus_enable => pc_fu_trace_bus_enable , + pc_fu_event_bus_enable => pc_fu_event_bus_enable , + pc_fu_debug_mux_ctrls => pc_fu_debug_mux_ctrls , + pc_fu_event_count_mode => pc_fu_event_count_mode , + pc_fu_event_mux_ctrls => pc_fu_event_mux_ctrls , + debug_data_in => debug_data_in , + debug_data_out => debug_data_out , + trace_triggers_in => trace_triggers_in , + trace_triggers_out => trace_triggers_out , + fu_pc_event_data => fu_pc_event_data , + + xu_fu_msr_fp => xu_fu_msr_fp , + xu_fu_msr_pr => xu_fu_msr_pr , + xu_fu_msr_gs => xu_fu_msr_gs , + pc_fu_instr_trace_mode => pc_fu_instr_trace_mode , + pc_fu_instr_trace_tid => pc_fu_instr_trace_tid , + + ------------------------------------------------ + f_rnd_ex6_res_expo => f_rnd_ex6_res_expo , + f_rnd_ex6_res_frac => f_rnd_ex6_res_frac , + f_rnd_ex6_res_sign => f_rnd_ex6_res_sign , + pc_fu_ram_mode => pc_fu_ram_mode , + pc_fu_ram_thread => pc_fu_ram_thread , + fu_pc_ram_done => fu_pc_ram_done , + fu_pc_ram_data => fu_pc_ram_data , + f_sto_ex2_s_parity_check => f_sto_ex2_s_parity_check , + f_mad_ex2_a_parity_check => f_mad_ex2_a_parity_check , + f_mad_ex2_b_parity_check => f_mad_ex2_b_parity_check , + f_mad_ex2_c_parity_check => f_mad_ex2_c_parity_check , + fu_pc_err_regfile_parity => fu_pc_err_regfile_parity , + fu_pc_err_regfile_ue => fu_pc_err_regfile_ue , + fu_xu_ex3_regfile_err_det => fu_xu_ex3_regfile_err_det , + xu_fu_regfile_seq_beg => xu_fu_regfile_seq_beg , + fu_xu_regfile_seq_end => fu_xu_regfile_seq_end , + ------------------------------------------------ + f_dcd_ex6_frt_addr => f_dcd_ex6_frt_addr , + f_dcd_ex5_frt_tid => f_dcd_ex5_frt_tid , + f_dcd_ex6_frt_tid => f_dcd_ex6_frt_tid , + f_dcd_ex6_frt_wen => f_dcd_ex6_frt_wen , + fu_xu_ex2_store_data_val => fu_xu_ex2_store_data_val , + fu_xu_ex4_cr => fu_xu_ex4_cr , + fu_xu_ex4_cr_val => fu_xu_ex4_cr_val , + fu_xu_ex4_cr_bf => fu_xu_ex4_cr_bf , + fu_xu_ex4_cr_noflush => fu_xu_ex4_cr_noflush , + ------------------------------------------------ + xu_fu_ex3_eff_addr => xu_fu_ex3_eff_addr , + fu_xu_ex3_n_flush => fu_xu_ex3_n_flush , + fu_xu_ex3_np1_flush => fu_xu_ex3_np1_flush , + fu_xu_ex3_ap_int_req => fu_xu_ex3_ap_int_req , + fu_xu_ex3_flush2ucode => fu_xu_ex3_flush2ucode , + fu_xu_ex2_instr_type => fu_xu_ex2_instr_type , + fu_xu_ex2_instr_match => fu_xu_ex2_instr_match , + fu_xu_ex2_is_ucode => fu_xu_ex2_is_ucode , + fu_xu_ex3_trap => fu_xu_ex3_trap , + fu_xu_ex2_ifar_val => fu_xu_ex2_ifar_val , + fu_xu_ex2_ifar_issued => fu_xu_ex2_ifar_issued , + fu_xu_ex1_ifar => fu_xu_ex1_ifar ); + + +------------------------------------------------------------------------ +-- Unused + + spare_unused(0) <= pc_fu_abst_slp_sl_thold_3; + spare_unused(1) <= pc_fu_cfg_slp_sl_thold_3; + spare_unused(2) <= pc_fu_func_nsl_thold_3; + spare_unused(3) <= pc_fu_func_slp_nsl_thold_3; + spare_unused(4) <= pc_fu_ary_slp_nsl_thold_3; + spare_unused(5) <= xu_fu_ex5_load_le; + +------------------------------------------------------------------------ +-- Scan Chains + + f_fpr_si <= func_scan_in(0); + f_sto_si <= f_fpr_so; + f_dcd_si <= f_sto_so; + func_scan_out(0) <= scan_dis_dc_b and f_dcd_so; + + + f_mad_si(0) <= func_scan_in(1); + f_mad_si(1) <= f_mad_so(0); + f_mad_si(2) <= f_mad_so(1); + f_mad_si(3) <= f_mad_so(2); + f_mad_si(4) <= f_mad_so(3); + f_mad_si(5) <= f_mad_so(4); + func_scan_out(1) <= scan_dis_dc_b and f_mad_so(5); + + f_mad_si(6) <= func_scan_in(2); + f_mad_si(7) <= f_mad_so(6); + f_mad_si(8) <= f_mad_so(7); + f_mad_si(9) <= f_mad_so(8); + f_mad_si(10) <= f_mad_so(9); + f_mad_si(11) <= f_mad_so(10); + func_scan_out(2) <= scan_dis_dc_b and f_mad_so(11); + + f_mad_si(12) <= func_scan_in(3); + f_mad_si(13) <= f_mad_so(12); + f_mad_si(14) <= f_mad_so(13); + f_mad_si(15) <= f_mad_so(14); + f_mad_si(16) <= f_mad_so(15); + f_mad_si(17) <= f_mad_so(16); + func_scan_out(3) <= scan_dis_dc_b and f_mad_so(17); + + + bx_pc_err_inbox_ue_ofu <= bx_pc_err_inbox_ue_ifu ; + bx_pc_err_outbox_ue_ofu <= bx_pc_err_outbox_ue_ifu ; + bx_pc_err_inbox_ecc_ofu <= bx_pc_err_inbox_ecc_ifu ; + bx_pc_err_outbox_ecc_ofu <= bx_pc_err_outbox_ecc_ifu ; + pc_bx_bolt_sl_thold_3_ofu <= pc_bx_bolt_sl_thold_3_ifu ; + pc_bx_bo_enable_3_ofu <= pc_bx_bo_enable_3_ifu ; + pc_bx_bo_unload_ofu <= pc_bx_bo_unload_ifu ; + pc_bx_bo_repair_ofu <= pc_bx_bo_repair_ifu ; + pc_bx_bo_reset_ofu <= pc_bx_bo_reset_ifu ; + pc_bx_bo_shdata_ofu <= pc_bx_bo_shdata_ifu ; + pc_bx_bo_select_ofu <= pc_bx_bo_select_ifu ; + bx_pc_bo_fail_ofu <= bx_pc_bo_fail_ifu ; + bx_pc_bo_diagout_ofu <= bx_pc_bo_diagout_ifu ; + pc_bx_abist_di_0_ofu <= pc_bx_abist_di_0_ifu ; + pc_bx_abist_ena_dc_ofu <= pc_bx_abist_ena_dc_ifu ; + pc_bx_abist_g8t1p_renb_0_ofu <= pc_bx_abist_g8t1p_renb_0_ifu ; + pc_bx_abist_g8t_bw_0_ofu <= pc_bx_abist_g8t_bw_0_ifu ; + pc_bx_abist_g8t_bw_1_ofu <= pc_bx_abist_g8t_bw_1_ifu ; + pc_bx_abist_g8t_dcomp_ofu <= pc_bx_abist_g8t_dcomp_ifu ; + pc_bx_abist_g8t_wenb_ofu <= pc_bx_abist_g8t_wenb_ifu ; + pc_bx_abist_raddr_0_ofu <= pc_bx_abist_raddr_0_ifu ; + pc_bx_abist_raw_dc_b_ofu <= pc_bx_abist_raw_dc_b_ifu ; + pc_bx_abist_waddr_0_ofu <= pc_bx_abist_waddr_0_ifu ; + pc_bx_abist_wl64_comp_ena_ofu <= pc_bx_abist_wl64_comp_ena_ifu ; + pc_bx_trace_bus_enable_ofu <= pc_bx_trace_bus_enable_ifu ; + pc_bx_debug_mux1_ctrls_ofu <= pc_bx_debug_mux1_ctrls_ifu ; + pc_bx_inj_inbox_ecc_ofu <= pc_bx_inj_inbox_ecc_ifu ; + pc_bx_inj_outbox_ecc_ofu <= pc_bx_inj_outbox_ecc_ifu ; + pc_bx_ccflush_dc_ofu <= pc_bx_ccflush_dc_ifu ; + pc_bx_sg_3_ofu <= pc_bx_sg_3_ifu ; + pc_bx_func_sl_thold_3_ofu <= pc_bx_func_sl_thold_3_ifu ; + pc_bx_func_slp_sl_thold_3_ofu <= pc_bx_func_slp_sl_thold_3_ifu ; + pc_bx_gptr_sl_thold_3_ofu <= pc_bx_gptr_sl_thold_3_ifu ; + pc_bx_time_sl_thold_3_ofu <= pc_bx_time_sl_thold_3_ifu ; + pc_bx_repr_sl_thold_3_ofu <= pc_bx_repr_sl_thold_3_ifu ; + pc_bx_abst_sl_thold_3_ofu <= pc_bx_abst_sl_thold_3_ifu ; + pc_bx_ary_nsl_thold_3_ofu <= pc_bx_ary_nsl_thold_3_ifu ; + pc_bx_ary_slp_nsl_thold_3_ofu <= pc_bx_ary_slp_nsl_thold_3_ifu ; + + xu_pc_err_mcsr_summary_ofu <= xu_pc_err_mcsr_summary_ifu ; + xu_pc_err_ierat_parity_ofu <= xu_pc_err_ierat_parity_ifu ; + xu_pc_err_derat_parity_ofu <= xu_pc_err_derat_parity_ifu ; + xu_pc_err_tlb_parity_ofu <= xu_pc_err_tlb_parity_ifu ; + xu_pc_err_tlb_lru_parity_ofu <= xu_pc_err_tlb_lru_parity_ifu ; + xu_pc_err_ierat_multihit_ofu <= xu_pc_err_ierat_multihit_ifu ; + xu_pc_err_derat_multihit_ofu <= xu_pc_err_derat_multihit_ifu ; + xu_pc_err_tlb_multihit_ofu <= xu_pc_err_tlb_multihit_ifu ; + xu_pc_err_ext_mchk_ofu <= xu_pc_err_ext_mchk_ifu ; + xu_pc_err_mchk_disabled_ofu <= xu_pc_err_mchk_disabled_ifu ; + xu_pc_err_ditc_overrun_ofu <= xu_pc_err_ditc_overrun_ifu ; + xu_pc_err_local_snoop_reject_ofu <= xu_pc_err_local_snoop_reject_ifu ; + xu_pc_err_attention_instr_ofu <= xu_pc_err_attention_instr_ifu ; + xu_pc_err_dcache_parity_ofu <= xu_pc_err_dcache_parity_ifu ; + xu_pc_err_dcachedir_parity_ofu <= xu_pc_err_dcachedir_parity_ifu ; + xu_pc_err_dcachedir_multihit_ofu <= xu_pc_err_dcachedir_multihit_ifu ; + xu_pc_err_debug_event_ofu <= xu_pc_err_debug_event_ifu ; + xu_pc_err_invld_reld_ofu <= xu_pc_err_invld_reld_ifu ; + xu_pc_err_l2intrf_ecc_ofu <= xu_pc_err_l2intrf_ecc_ifu ; + xu_pc_err_l2intrf_ue_ofu <= xu_pc_err_l2intrf_ue_ifu ; + xu_pc_err_l2credit_overrun_ofu <= xu_pc_err_l2credit_overrun_ifu ; + xu_pc_err_llbust_attempt_ofu <= xu_pc_err_llbust_attempt_ifu ; + xu_pc_err_llbust_failed_ofu <= xu_pc_err_llbust_failed_ifu ; + xu_pc_err_nia_miscmpr_ofu <= xu_pc_err_nia_miscmpr_ifu ; + xu_pc_err_regfile_parity_ofu <= xu_pc_err_regfile_parity_ifu ; + xu_pc_err_regfile_ue_ofu <= xu_pc_err_regfile_ue_ifu ; + xu_pc_err_sprg_ecc_ofu <= xu_pc_err_sprg_ecc_ifu ; + xu_pc_err_sprg_ue_ofu <= xu_pc_err_sprg_ue_ifu ; + xu_pc_err_wdt_reset_ofu <= xu_pc_err_wdt_reset_ifu ; + xu_pc_event_data_ofu <= xu_pc_event_data_ifu ; + xu_pc_ram_data_ofu <= xu_pc_ram_data_ifu ; + xu_pc_ram_done_ofu <= xu_pc_ram_done_ifu ; + xu_pc_ram_interrupt_ofu <= xu_pc_ram_interrupt_ifu ; + xu_pc_running_ofu <= xu_pc_running_ifu ; + xu_pc_spr_ccr0_pme_ofu <= xu_pc_spr_ccr0_pme_ifu ; + xu_pc_spr_ccr0_we_ofu <= xu_pc_spr_ccr0_we_ifu ; + xu_pc_step_done_ofu <= xu_pc_step_done_ifu ; + xu_pc_stop_dbg_event_ofu <= xu_pc_stop_dbg_event_ifu ; + xu_pc_lsu_event_data_ofu <= xu_pc_lsu_event_data_ifu ; + pc_xu_bolt_sl_thold_3_ofu <= pc_xu_bolt_sl_thold_3_ifu ; + pc_xu_bo_enable_3_ofu <= pc_xu_bo_enable_3_ifu ; + pc_xu_bo_unload_ofu <= pc_xu_bo_unload_ifu ; + pc_xu_bo_load_ofu <= pc_xu_bo_load_ifu ; + pc_xu_bo_repair_ofu <= pc_xu_bo_repair_ifu ; + pc_xu_bo_reset_ofu <= pc_xu_bo_reset_ifu ; + pc_xu_bo_shdata_ofu <= pc_xu_bo_shdata_ifu ; + pc_xu_bo_select_ofu <= pc_xu_bo_select_ifu ; + xu_pc_bo_fail_ofu <= xu_pc_bo_fail_ifu ; + xu_pc_bo_diagout_ofu <= xu_pc_bo_diagout_ifu ; + pc_xu_abist_dcomp_g6t_2r_ofu <= pc_xu_abist_dcomp_g6t_2r_ifu ; + pc_xu_abist_di_0_ofu <= pc_xu_abist_di_0_ifu ; + pc_xu_abist_di_1_ofu <= pc_xu_abist_di_1_ifu ; + pc_xu_abist_di_g6t_2r_ofu <= pc_xu_abist_di_g6t_2r_ifu ; + pc_xu_abist_ena_dc_ofu <= pc_xu_abist_ena_dc_ifu ; + pc_xu_abist_g6t_bw_ofu <= pc_xu_abist_g6t_bw_ifu ; + pc_xu_abist_g6t_r_wb_ofu <= pc_xu_abist_g6t_r_wb_ifu ; + pc_xu_abist_g8t1p_renb_0_ofu <= pc_xu_abist_g8t1p_renb_0_ifu ; + pc_xu_abist_g8t_bw_0_ofu <= pc_xu_abist_g8t_bw_0_ifu ; + pc_xu_abist_g8t_bw_1_ofu <= pc_xu_abist_g8t_bw_1_ifu ; + pc_xu_abist_g8t_dcomp_ofu <= pc_xu_abist_g8t_dcomp_ifu ; + pc_xu_abist_g8t_wenb_ofu <= pc_xu_abist_g8t_wenb_ifu ; + pc_xu_abist_grf_renb_0_ofu <= pc_xu_abist_grf_renb_0_ifu ; + pc_xu_abist_grf_renb_1_ofu <= pc_xu_abist_grf_renb_1_ifu ; + pc_xu_abist_grf_wenb_0_ofu <= pc_xu_abist_grf_wenb_0_ifu ; + pc_xu_abist_grf_wenb_1_ofu <= pc_xu_abist_grf_wenb_1_ifu ; + pc_xu_abist_raddr_0_ofu <= pc_xu_abist_raddr_0_ifu ; + pc_xu_abist_raddr_1_ofu <= pc_xu_abist_raddr_1_ifu ; + pc_xu_abist_raw_dc_b_ofu <= pc_xu_abist_raw_dc_b_ifu ; + pc_xu_abist_waddr_0_ofu <= pc_xu_abist_waddr_0_ifu ; + pc_xu_abist_waddr_1_ofu <= pc_xu_abist_waddr_1_ifu ; + pc_xu_abist_wl144_comp_ena_ofu <= pc_xu_abist_wl144_comp_ena_ifu ; + pc_xu_abist_wl32_comp_ena_ofu <= pc_xu_abist_wl32_comp_ena_ifu ; + pc_xu_abist_wl512_comp_ena_ofu <= pc_xu_abist_wl512_comp_ena_ifu ; + pc_xu_event_mux_ctrls_ofu <= pc_xu_event_mux_ctrls_ifu ; + pc_xu_lsu_event_mux_ctrls_ofu <= pc_xu_lsu_event_mux_ctrls_ifu ; + pc_xu_event_bus_enable_ofu <= pc_xu_event_bus_enable_ifu ; + pc_xu_abst_sl_thold_3_ofu <= pc_xu_abst_sl_thold_3_ifu ; + pc_xu_abst_slp_sl_thold_3_ofu <= pc_xu_abst_slp_sl_thold_3_ifu ; + pc_xu_regf_sl_thold_3_ofu <= pc_xu_regf_sl_thold_3_ifu ; + pc_xu_regf_slp_sl_thold_3_ofu <= pc_xu_regf_slp_sl_thold_3_ifu ; + pc_xu_ary_nsl_thold_3_ofu <= pc_xu_ary_nsl_thold_3_ifu ; + pc_xu_ary_slp_nsl_thold_3_ofu <= pc_xu_ary_slp_nsl_thold_3_ifu ; + pc_xu_cache_par_err_event_ofu <= pc_xu_cache_par_err_event_ifu ; + pc_xu_ccflush_dc_ofu <= pc_xu_ccflush_dc_ifu ; + pc_xu_cfg_sl_thold_3_ofu <= pc_xu_cfg_sl_thold_3_ifu ; + pc_xu_cfg_slp_sl_thold_3_ofu <= pc_xu_cfg_slp_sl_thold_3_ifu ; + pc_xu_dbg_action_ofu <= pc_xu_dbg_action_ifu ; + pc_xu_debug_mux1_ctrls_ofu <= pc_xu_debug_mux1_ctrls_ifu ; + pc_xu_debug_mux2_ctrls_ofu <= pc_xu_debug_mux2_ctrls_ifu ; + pc_xu_debug_mux3_ctrls_ofu <= pc_xu_debug_mux3_ctrls_ifu ; + pc_xu_debug_mux4_ctrls_ofu <= pc_xu_debug_mux4_ctrls_ifu ; + pc_xu_decrem_dis_on_stop_ofu <= pc_xu_decrem_dis_on_stop_ifu ; + pc_xu_event_count_mode_ofu <= pc_xu_event_count_mode_ifu ; + pc_xu_extirpts_dis_on_stop_ofu <= pc_xu_extirpts_dis_on_stop_ifu ; + pc_xu_fce_3_ofu <= pc_xu_fce_3_ifu ; + pc_xu_force_ude_ofu <= pc_xu_force_ude_ifu ; + pc_xu_func_nsl_thold_3_ofu <= pc_xu_func_nsl_thold_3_ifu ; + pc_xu_func_sl_thold_3_ofu <= pc_xu_func_sl_thold_3_ifu ; + pc_xu_func_slp_nsl_thold_3_ofu <= pc_xu_func_slp_nsl_thold_3_ifu ; + pc_xu_func_slp_sl_thold_3_ofu <= pc_xu_func_slp_sl_thold_3_ifu ; + pc_xu_gptr_sl_thold_3_ofu <= pc_xu_gptr_sl_thold_3_ifu ; + pc_xu_init_reset_ofu <= pc_xu_init_reset_ifu ; + pc_xu_inj_dcache_parity_ofu <= pc_xu_inj_dcache_parity_ifu ; + pc_xu_inj_dcachedir_parity_ofu <= pc_xu_inj_dcachedir_parity_ifu ; + pc_xu_inj_llbust_attempt_ofu <= pc_xu_inj_llbust_attempt_ifu ; + pc_xu_inj_llbust_failed_ofu <= pc_xu_inj_llbust_failed_ifu ; + pc_xu_inj_sprg_ecc_ofu <= pc_xu_inj_sprg_ecc_ifu ; + pc_xu_inj_regfile_parity_ofu <= pc_xu_inj_regfile_parity_ifu ; + pc_xu_inj_wdt_reset_ofu <= pc_xu_inj_wdt_reset_ifu ; + pc_xu_inj_dcachedir_multihit_ofu <= pc_xu_inj_dcachedir_multihit_ifu ; + pc_xu_instr_trace_mode_ofu <= pc_xu_instr_trace_mode_ifu ; + pc_xu_instr_trace_tid_ofu <= pc_xu_instr_trace_tid_ifu ; + pc_xu_msrovride_enab_ofu <= pc_xu_msrovride_enab_ifu ; + pc_xu_msrovride_gs_ofu <= pc_xu_msrovride_gs_ifu ; + pc_xu_msrovride_pr_ofu <= pc_xu_msrovride_pr_ifu ; + pc_xu_ram_execute_ofu <= pc_xu_ram_execute_ifu ; + pc_xu_ram_flush_thread_ofu <= pc_xu_ram_flush_thread_ifu ; + pc_xu_ram_mode_ofu <= pc_xu_ram_mode_ifu ; + pc_xu_ram_thread_ofu <= pc_xu_ram_thread_ifu ; + pc_xu_repr_sl_thold_3_ofu <= pc_xu_repr_sl_thold_3_ifu ; + pc_xu_reset_1_cmplt_ofu <= pc_xu_reset_1_cmplt_ifu ; + pc_xu_reset_2_cmplt_ofu <= pc_xu_reset_2_cmplt_ifu ; + pc_xu_reset_3_cmplt_ofu <= pc_xu_reset_3_cmplt_ifu ; + pc_xu_reset_wd_cmplt_ofu <= pc_xu_reset_wd_cmplt_ifu ; + pc_xu_sg_3_ofu <= pc_xu_sg_3_ifu ; + pc_xu_step_ofu <= pc_xu_step_ifu ; + pc_xu_stop_ofu <= pc_xu_stop_ifu ; + pc_xu_time_sl_thold_3_ofu <= pc_xu_time_sl_thold_3_ifu ; + pc_xu_timebase_dis_on_stop_ofu <= pc_xu_timebase_dis_on_stop_ifu ; + pc_xu_trace_bus_enable_ofu <= pc_xu_trace_bus_enable_ifu ; + + an_ac_scan_dis_dc_b_ofu <= scan_dis_dc_b ; + an_ac_scan_diag_dc_ofu <= scan_diag_dc ; + + xu_ex2_flush_ofu <= xu_ex2_flush ; + xu_ex3_flush_ofu <= xu_ex3_flush ; + xu_ex4_flush_ofu <= xu_ex4_flush ; + xu_ex5_flush_ofu <= xu_ex5_flush ; + an_ac_lbist_ary_wrt_thru_dc_ofu <= an_ac_lbist_ary_wrt_thru_dc ; + + +end architecture fuq; diff --git a/rel/src/vhdl/work/fuq_add.vhdl b/rel/src/vhdl/work/fuq_add.vhdl new file mode 100644 index 0000000..567026c --- /dev/null +++ b/rel/src/vhdl/work/fuq_add.vhdl @@ -0,0 +1,630 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + +entity fuq_add is +generic( expand_type : integer := 2 ); -- 0 - ibm tech, 1 - other ); +port( + + vdd :inout power_logic; + gnd :inout power_logic; + clkoff_b :in std_ulogic; -- tiup + act_dis :in std_ulogic; -- ??tidn?? + flush :in std_ulogic; -- ??tidn?? + delay_lclkr :in std_ulogic_vector(3 to 4); -- tidn, + mpw1_b :in std_ulogic_vector(3 to 4); -- tidn, + mpw2_b :in std_ulogic_vector(0 to 0); -- tidn, + sg_1 :in std_ulogic; + thold_1 :in std_ulogic; + fpu_enable :in std_ulogic; --dc_act + nclk :in clk_logic; + + f_add_si :in std_ulogic; --perv + f_add_so :out std_ulogic; --perv + ex1_act_b :in std_ulogic; --act + + f_sa3_ex3_s :in std_ulogic_vector(0 to 162); -- data + f_sa3_ex3_c :in std_ulogic_vector(53 to 161); -- data + + -- f_alg_ex2_sel_byp :in std_ulogic; -- all eac selects off + f_alg_ex3_frc_sel_p1 :in std_ulogic; -- rounding converts + f_alg_ex3_sticky :in std_ulogic; -- part of eac control + f_alg_ex2_effsub_eac_b :in std_ulogic; -- already shut off for algByp + f_alg_ex2_prod_z :in std_ulogic; + + f_pic_ex3_is_gt :in std_ulogic; -- compare + f_pic_ex3_is_lt :in std_ulogic; -- compare + f_pic_ex3_is_eq :in std_ulogic; -- compare + f_pic_ex3_is_nan :in std_ulogic; -- compare + f_pic_ex3_cmp_sgnpos :in std_ulogic; -- compare + f_pic_ex3_cmp_sgnneg :in std_ulogic; -- compare + + f_add_ex4_res :out std_ulogic_vector(0 to 162); -- RESULT + f_add_ex4_flag_nan :out std_ulogic; -- compare for fpscr + f_add_ex4_flag_gt :out std_ulogic; -- compare for fpscr + f_add_ex4_flag_lt :out std_ulogic; -- compare for fpscr + f_add_ex4_flag_eq :out std_ulogic; -- compare for fpscr + f_add_ex4_fpcc_iu :out std_ulogic_vector(0 to 3); -- compare for iu + f_add_ex4_sign_carry :out std_ulogic; -- select sign from product/addend + f_add_ex4_to_int_ovf_wd :out std_ulogic_vector(0 to 1); -- raw data + f_add_ex4_to_int_ovf_dw :out std_ulogic_vector(0 to 1); -- raw data + f_add_ex4_sticky :out std_ulogic -- for nrm + +); + + +end fuq_add; -- ENTITY + +architecture fuq_add of fuq_add is + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + +--//################################# +--//# sigdef : non-functional +--//################################# + + signal thold_0_b, thold_0 :std_ulogic; + signal sg_0, forcee :std_ulogic; + + signal ex1_act :std_ulogic; + signal ex2_act :std_ulogic; + signal ex3_act :std_ulogic; + + signal act_si :std_ulogic_vector(0 to 8); + signal act_so :std_ulogic_vector(0 to 8); + signal ex4_res_so :std_ulogic_vector(0 to 162); + signal ex4_res_si :std_ulogic_vector(0 to 162); + signal ex4_cmp_so :std_ulogic_vector(0 to 9); + signal ex4_cmp_si :std_ulogic_vector(0 to 9); + + signal spare_unused :std_ulogic_vector(0 to 3); + +--//################################# +--//# sigdef : functional +--//################################# + + signal ex3_s :std_ulogic_vector( 0 to 162); + signal ex3_c :std_ulogic_vector(53 to 161); + + signal ex3_flag_nan :std_ulogic; + signal ex3_flag_gt :std_ulogic; + signal ex3_flag_lt :std_ulogic; + signal ex3_flag_eq :std_ulogic; + signal ex3_sign_carry :std_ulogic; + + signal ex3_inc_all1 :std_ulogic; + signal ex3_inc_byt_c_glb :std_ulogic_vector(1 to 6); + signal ex3_inc_byt_c_glb_b :std_ulogic_vector(1 to 6); + signal ex3_inc_p1 :std_ulogic_vector(0 to 52); + signal ex3_inc_p0 :std_ulogic_vector(0 to 52); + + signal ex3_s_p0 :std_ulogic_vector(53 to 162); + signal ex3_s_p1 :std_ulogic_vector(53 to 162); + signal ex3_res :std_ulogic_vector(0 to 162); + + signal ex2_effsub :std_ulogic; + signal ex3_effsub :std_ulogic; + + signal ex2_effadd_npz :std_ulogic; + signal ex2_effsub_npz :std_ulogic; + signal ex3_effsub_npz :std_ulogic; + signal ex3_effadd_npz :std_ulogic; + signal ex3_flip_inc_p0 :std_ulogic; + signal ex3_flip_inc_p1 :std_ulogic; + signal ex3_inc_sel_p0 :std_ulogic; + signal ex3_inc_sel_p1 :std_ulogic; + + signal ex4_res, ex4_res_b , ex4_res_l2_b :std_ulogic_vector(0 to 162) ; + signal ex4_flag_nan_b :std_ulogic; + signal ex4_flag_gt_b :std_ulogic; + signal ex4_flag_lt_b :std_ulogic; + signal ex4_flag_eq_b :std_ulogic; + signal ex4_fpcc_iu_b :std_ulogic_vector(0 to 3) ; + signal ex4_sign_carry_b :std_ulogic; + signal ex4_sticky_b :std_ulogic; + + signal ex3_g16 :std_ulogic_vector(0 to 6); + signal ex3_t16 :std_ulogic_vector(0 to 6); + signal ex3_g128, ex3_t128, ex3_g128_b, ex3_t128_b :std_ulogic_vector(1 to 6); + signal ex3_inc_byt_c_b :std_ulogic_vector(0 to 6); + signal ex3_eac_sel_p0n, ex3_eac_sel_p0, ex3_eac_sel_p1 : std_ulogic_vector(0 to 6); + signal ex3_flag_nan_cp1, ex3_flag_gt_cp1, ex3_flag_lt_cp1, ex3_flag_eq_cp1 :std_ulogic; + signal add_ex4_d1clk , add_ex4_d2clk :std_ulogic ; + signal add_ex4_lclk :clk_logic ; + + signal ex3_s_p0n, ex3_res_p0n_b, ex3_res_p0_b, ex3_res_p1_b :std_ulogic_vector(53 to 162); + signal ex3_inc_p0_x, ex3_inc_p1_x, ex3_incx_p0_b, ex3_incx_p1_b :std_ulogic_vector(0 to 52); + signal ex3_sel_a1, ex3_sel_a2, ex3_sel_a3 :std_ulogic_vector(53 to 162); + + + + +begin + +--//################################################################ +--//# pervasive +--//################################################################ + + thold_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => thold_1, -- ?? need an lcb_or after this + q(0) => thold_0 ); + + sg_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => sg_1 , + q(0) => sg_0 ); + + lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map ( + clkoff_b => clkoff_b, + thold => thold_0, + sg => sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => thold_0_b ); + +--//################################################################ +--//# act +--//################################################################ + + ex1_act <= not ex1_act_b ; + ex2_effsub <= not f_alg_ex2_effsub_eac_b ; + ex2_effsub_npz <= not f_alg_ex2_effsub_eac_b and not f_alg_ex2_prod_z; + ex2_effadd_npz <= f_alg_ex2_effsub_eac_b and not f_alg_ex2_prod_z; + + act_lat: tri_rlmreg_p generic map (width=> 9, expand_type => expand_type, needs_sreset => 0) port map ( + forcee => forcee,--i-- tidn, + --d_mode => d_mode ,--i-- tiup, + delay_lclkr => delay_lclkr(3) ,--i-- tidn, + mpw1_b => mpw1_b(3) ,--i-- tidn, + mpw2_b => mpw2_b(0) ,--i-- tidn, + nclk => nclk, + act => fpu_enable, + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scout => act_so , + scin => act_si , + ------------------- + din(0) => spare_unused(0), + din(1) => spare_unused(1), + din(2) => ex1_act, + din(3) => ex2_act, + din(4) => ex2_effsub , + din(5) => ex2_effsub_npz, + din(6) => ex2_effadd_npz, + din(7) => spare_unused(2), + din(8) => spare_unused(3), + ------------------- + dout(0) => spare_unused(0), + dout(1) => spare_unused(1), + dout(2) => ex2_act, + dout(3) => ex3_act, + dout(4) => ex3_effsub , + dout(5) => ex3_effsub_npz, + dout(6) => ex3_effadd_npz, + dout(7) => spare_unused(2) , + dout(8) => spare_unused(3) ); + + add_ex4_lcb : tri_lcbnd generic map (expand_type => expand_type) port map( + delay_lclkr => delay_lclkr(4) ,-- tidn ,--in + -- --d_mode => d_mode ,-- tiup ,--in + mpw1_b => mpw1_b(4) ,-- tidn ,--in + mpw2_b => mpw2_b(0) ,-- tidn ,--in + forcee => forcee,-- tidn ,--in + nclk => nclk ,--in + vd => vdd ,--inout + gd => gnd ,--inout + act => ex3_act ,--in + sg => sg_0 ,--in + thold_b => thold_0_b ,--in + d1clk => add_ex4_d1clk ,--out + d2clk => add_ex4_d2clk ,--out + lclk => add_ex4_lclk );--out + + +--//################################################################ +--//# ex3 logic +--//################################################################ + + ex3_s(0 to 162) <= f_sa3_ex3_s(0 to 162); + ex3_c(53 to 161) <= f_sa3_ex3_c(53 to 161); + + --ex3 incrementer----------------------------------------- + + --ex3 incr (global carry)--------------------------------- + + all1: entity work.fuq_add_all1(fuq_add_all1) port map( + ex3_inc_byt_c_b(0 to 6) => ex3_inc_byt_c_b(0 to 6) ,--i-- + ex3_inc_byt_c_glb(1 to 6) => ex3_inc_byt_c_glb(1 to 6) ,--o-- + ex3_inc_byt_c_glb_b(1 to 6) => ex3_inc_byt_c_glb_b(1 to 6) ,--o-- + ex3_inc_all1 => ex3_inc_all1 );--o-- + + --ex3 incr (byte sections) ------------------------------------------------- + + inc8_6: entity work.fuq_loc8inc_lsb(fuq_loc8inc_lsb) port map( + co_b => ex3_inc_byt_c_b(6) ,--o-- + x => ex3_s ( 48 to 52) ,--i-- + s0 => ex3_inc_p0( 48 to 52) ,--o-- + s1 => ex3_inc_p1( 48 to 52) );--o-- + + inc8_5: entity work.fuq_loc8inc(fuq_loc8inc) port map( + ci => ex3_inc_byt_c_glb(6) ,--i-- + ci_b => ex3_inc_byt_c_glb_b(6) ,--i-- + co_b => ex3_inc_byt_c_b(5) ,--o-- + x => ex3_s ( 40 to 47) ,--i-- + s0 => ex3_inc_p0( 40 to 47) ,--o-- + s1 => ex3_inc_p1( 40 to 47) );--o-- + + inc8_4: entity work.fuq_loc8inc(fuq_loc8inc) port map( + ci => ex3_inc_byt_c_glb(5) ,--i-- + ci_b => ex3_inc_byt_c_glb_b(5) ,--i-- + co_b => ex3_inc_byt_c_b(4) ,--o-- + x => ex3_s ( 32 to 39) ,--i-- + s0 => ex3_inc_p0( 32 to 39) ,--o-- + s1 => ex3_inc_p1( 32 to 39) );--o-- + + inc8_3: entity work.fuq_loc8inc(fuq_loc8inc) port map( + ci => ex3_inc_byt_c_glb(4) ,--i-- + ci_b => ex3_inc_byt_c_glb_b(4) ,--i-- + co_b => ex3_inc_byt_c_b(3) ,--o-- + x => ex3_s ( 24 to 31) ,--i-- + s0 => ex3_inc_p0( 24 to 31) ,--o-- + s1 => ex3_inc_p1( 24 to 31) );--o-- + + inc8_2: entity work.fuq_loc8inc(fuq_loc8inc) port map( + ci => ex3_inc_byt_c_glb(3) ,--i-- + ci_b => ex3_inc_byt_c_glb_b(3) ,--i-- + co_b => ex3_inc_byt_c_b(2) ,--o-- + x => ex3_s ( 16 to 23) ,--i-- + s0 => ex3_inc_p0( 16 to 23) ,--o-- + s1 => ex3_inc_p1( 16 to 23) );--o-- + + inc8_1: entity work.fuq_loc8inc(fuq_loc8inc) port map( + ci => ex3_inc_byt_c_glb(2) ,--i-- + ci_b => ex3_inc_byt_c_glb_b(2) ,--i-- + co_b => ex3_inc_byt_c_b(1) ,--o-- + x => ex3_s ( 8 to 15) ,--i-- + s0 => ex3_inc_p0( 8 to 15) ,--o-- + s1 => ex3_inc_p1( 8 to 15) );--o-- + + inc8_0: entity work.fuq_loc8inc(fuq_loc8inc) port map( + ci => ex3_inc_byt_c_glb(1) ,--i-- + ci_b => ex3_inc_byt_c_glb_b(1) ,--i-- + co_b => ex3_inc_byt_c_b(0) ,--o-- + x => ex3_s ( 0 to 7) ,--i-- + s0 => ex3_inc_p0( 0 to 7) ,--o-- + s1 => ex3_inc_p1( 0 to 7) );--o-- + + + + --ex3 adder----------------------------------------------- + + -- sum[53] is the raw aligner bit + -- car[53] includes the bogous bit + -- position 53 also includes a "1" to push out the bogous bit + -- + -- [0:52] needs "111...111" to push out the bogous bit + -- but the first co of [53] is supressed instead + -- + -- ex3_53 => s53, c53, "1", ci : 2nd co : s53 * c53 * ci + + + -- sums + -- [0] 053:068 + -- [1] 069:084 + -- [2] 085:100 + -- [3] 101:116 + -- [4] 117:132 + -- [5] 133:148 + -- [6] 149:164 <162,"1","1"> + + hc16_0: entity work.fuq_hc16pp_msb(fuq_hc16pp_msb) port map( + x => ex3_s( 53 to 68) ,--i-- + y => ex3_c( 53 to 68) ,--i-- + ci0 => ex3_g128(1) ,--i-- + ci0_b => ex3_g128_b(1) ,--i-- + ci1 => ex3_t128(1) ,--i-- + ci1_b => ex3_t128_b(1) ,--i-- + s0 => ex3_s_p0( 53 to 68) ,--o-- + s1 => ex3_s_p1( 53 to 68) ,--o-- + g16 => ex3_g16(0) ,--o-- + t16 => ex3_t16(0) );--o-- + + hc16_1: entity work.fuq_hc16pp(fuq_hc16pp) port map( + x => ex3_s( 69 to 84) ,--i-- + y => ex3_c( 69 to 84) ,--i-- + ci0 => ex3_g128(2) ,--i-- + ci0_b => ex3_g128_b(2) ,--i-- + ci1 => ex3_t128(2) ,--i-- + ci1_b => ex3_t128_b(2) ,--i-- + s0 => ex3_s_p0( 69 to 84) ,--o-- + s1 => ex3_s_p1( 69 to 84) ,--o-- + g16 => ex3_g16(1) ,--o-- + t16 => ex3_t16(1) );--o-- + + hc16_2: entity work.fuq_hc16pp(fuq_hc16pp) port map( + x => ex3_s( 85 to 100) ,--i-- + y => ex3_c( 85 to 100) ,--i-- + ci0 => ex3_g128(3) ,--i-- + ci0_b => ex3_g128_b(3) ,--i-- + ci1 => ex3_t128(3) ,--i-- + ci1_b => ex3_t128_b(3) ,--i-- + s0 => ex3_s_p0( 85 to 100) ,--o-- + s1 => ex3_s_p1( 85 to 100) ,--o-- + g16 => ex3_g16(2) ,--o-- + t16 => ex3_t16(2) );--o-- + + hc16_3: entity work.fuq_hc16pp(fuq_hc16pp) port map( + x => ex3_s(101 to 116) ,--i-- + y => ex3_c(101 to 116) ,--i-- + ci0 => ex3_g128(4) ,--i-- + ci0_b => ex3_g128_b(4) ,--i-- + ci1 => ex3_t128(4) ,--i-- + ci1_b => ex3_t128_b(4) ,--i-- + s0 => ex3_s_p0(101 to 116) ,--o-- + s1 => ex3_s_p1(101 to 116) ,--o-- + g16 => ex3_g16(3) ,--o-- + t16 => ex3_t16(3) );--o-- + + hc16_4: entity work.fuq_hc16pp(fuq_hc16pp) port map( + x => ex3_s(117 to 132) ,--i-- + y => ex3_c(117 to 132) ,--i-- + ci0 => ex3_g128(5) ,--i-- + ci0_b => ex3_g128_b(5) ,--i-- + ci1 => ex3_t128(5) ,--i-- + ci1_b => ex3_t128_b(5) ,--i-- + s0 => ex3_s_p0(117 to 132) ,--o-- + s1 => ex3_s_p1(117 to 132) ,--o-- + g16 => ex3_g16(4) ,--o-- + t16 => ex3_t16(4) );--o-- + + hc16_5: entity work.fuq_hc16pp(fuq_hc16pp) port map( + x => ex3_s(133 to 148) ,--i-- + y => ex3_c(133 to 148) ,--i-- + ci0 => ex3_g128(6) ,--i-- + ci0_b => ex3_g128_b(6) ,--i-- + ci1 => ex3_t128(6) ,--i-- + ci1_b => ex3_t128_b(6) ,--i-- + s0 => ex3_s_p0(133 to 148) ,--o-- + s1 => ex3_s_p1(133 to 148) ,--o-- + g16 => ex3_g16(5) ,--o-- + t16 => ex3_t16(5) );--o-- + + hc16_6: entity work.fuq_hc16pp_lsb(fuq_hc16pp_lsb) port map( + x(0 to 13) => ex3_s(149 to 162) ,--i-- + y(0 to 12) => ex3_c(149 to 161) ,--i-- + s0 => ex3_s_p0(149 to 162) ,--o-- + s1 => ex3_s_p1(149 to 162) ,--o-- + g16 => ex3_g16(6) ,--o-- + t16 => ex3_t16(6) );--o-- + + + + -------------------------------------------------- + -- EACMUX: incrementer bits + -------------------------------------------------- + + u_incmx_p0x: ex3_inc_p0_x(0 to 52) <= ex3_inc_p0(0 to 52) xor (0 to 52=> ex3_flip_inc_p0); + u_incmx_p1x: ex3_inc_p1_x(0 to 52) <= ex3_inc_p1(0 to 52) xor (0 to 52=> ex3_flip_inc_p1); + + u_incmx_p0: ex3_incx_p0_b(0 to 52) <= not( (0 to 52=> ex3_inc_sel_p0) and ex3_inc_p0_x(0 to 52) ); + u_incmx_p1: ex3_incx_p1_b(0 to 52) <= not( (0 to 52=> ex3_inc_sel_p1) and ex3_inc_p1_x(0 to 52) ); + u_incmx: ex3_res (0 to 52) <= not( ex3_incx_p0_b(0 to 52) and ex3_incx_p1_b(0 to 52) ); + + -------------------------------------------------- + -- EACMUX: adder bits + -------------------------------------------------- + + ex3_sel_a1(53 to 68) <= (53 to 68 => ex3_eac_sel_p0n(0) ); --rename + ex3_sel_a1(69 to 84) <= (69 to 84 => ex3_eac_sel_p0n(1) ); --rename + ex3_sel_a1(85 to 100) <= (85 to 100 => ex3_eac_sel_p0n(2) ); --rename + ex3_sel_a1(101 to 116) <= (101 to 116 => ex3_eac_sel_p0n(3) ); --rename + ex3_sel_a1(117 to 132) <= (117 to 132 => ex3_eac_sel_p0n(4) ); --rename + ex3_sel_a1(133 to 148) <= (133 to 148 => ex3_eac_sel_p0n(5) ); --rename + ex3_sel_a1(149 to 162) <= (149 to 162 => ex3_eac_sel_p0n(6) ); --rename + + ex3_sel_a2(53 to 68) <= (53 to 68 => ex3_eac_sel_p0(0) ); --rename + ex3_sel_a2(69 to 84) <= (69 to 84 => ex3_eac_sel_p0(1) ); --rename + ex3_sel_a2(85 to 100) <= (85 to 100 => ex3_eac_sel_p0(2) ); --rename + ex3_sel_a2(101 to 116) <= (101 to 116 => ex3_eac_sel_p0(3) ); --rename + ex3_sel_a2(117 to 132) <= (117 to 132 => ex3_eac_sel_p0(4) ); --rename + ex3_sel_a2(133 to 148) <= (133 to 148 => ex3_eac_sel_p0(5) ); --rename + ex3_sel_a2(149 to 162) <= (149 to 162 => ex3_eac_sel_p0(6) ); --rename + + ex3_sel_a3(53 to 68) <= (53 to 68 => ex3_eac_sel_p1(0) ); --rename + ex3_sel_a3(69 to 84) <= (69 to 84 => ex3_eac_sel_p1(1) ); --rename + ex3_sel_a3(85 to 100) <= (85 to 100 => ex3_eac_sel_p1(2) ); --rename + ex3_sel_a3(101 to 116) <= (101 to 116 => ex3_eac_sel_p1(3) ); --rename + ex3_sel_a3(117 to 132) <= (117 to 132 => ex3_eac_sel_p1(4) ); --rename + ex3_sel_a3(133 to 148) <= (133 to 148 => ex3_eac_sel_p1(5) ); --rename + ex3_sel_a3(149 to 162) <= (149 to 162 => ex3_eac_sel_p1(6) ); --rename + + u_eacmx_i: ex3_s_p0n (53 to 162) <= not( ex3_s_p0(53 to 162) ); + u_eacmx_a1: ex3_res_p0n_b(53 to 162) <= not( ex3_sel_a1(53 to 162) and ex3_s_p0n(53 to 162) ); + u_eacmx_a2: ex3_res_p0_b (53 to 162) <= not( ex3_sel_a2(53 to 162) and ex3_s_p0(53 to 162) ); + u_eacmx_a3: ex3_res_p1_b (53 to 162) <= not( ex3_sel_a3(53 to 162) and ex3_s_p1(53 to 162) ); + u_eacmx: ex3_res (53 to 162) <= not( ex3_res_p0n_b(53 to 162) and ex3_res_p0_b(53 to 162) and ex3_res_p1_b(53 to 162) ); + + +--=################################################################################## +--=# global carry chain, eac_selects, compare, sign_carry +--=################################################################################## + + glbc: entity work.fuq_add_glbc(fuq_add_glbc) port map( + ex3_g16(0 to 6) => ex3_g16(0 to 6) ,--i-- + ex3_t16(0 to 6) => ex3_t16(0 to 6) ,--i-- + ex3_inc_all1 => ex3_inc_all1 ,--i-- + ex3_effsub => ex3_effsub ,--i-- + ex3_effsub_npz => ex3_effsub_npz ,--i-- + ex3_effadd_npz => ex3_effadd_npz ,--i-- + f_alg_ex3_frc_sel_p1 => f_alg_ex3_frc_sel_p1 ,--i-- + f_alg_ex3_sticky => f_alg_ex3_sticky ,--i-- + f_pic_ex3_is_nan => f_pic_ex3_is_nan ,--i-- + f_pic_ex3_is_gt => f_pic_ex3_is_gt ,--i-- + f_pic_ex3_is_lt => f_pic_ex3_is_lt ,--i-- + f_pic_ex3_is_eq => f_pic_ex3_is_eq ,--i-- + f_pic_ex3_cmp_sgnpos => f_pic_ex3_cmp_sgnpos ,--i-- + f_pic_ex3_cmp_sgnneg => f_pic_ex3_cmp_sgnneg ,--i-- + ex3_g128(1 to 6) => ex3_g128(1 to 6) ,--o-- + ex3_g128_b(1 to 6) => ex3_g128_b(1 to 6) ,--o-- + ex3_t128(1 to 6) => ex3_t128(1 to 6) ,--o-- + ex3_t128_b(1 to 6) => ex3_t128_b(1 to 6) ,--o-- + ex3_flip_inc_p0 => ex3_flip_inc_p0 ,--o-- + ex3_flip_inc_p1 => ex3_flip_inc_p1 ,--o-- + ex3_inc_sel_p0 => ex3_inc_sel_p0 ,--o-- + ex3_inc_sel_p1 => ex3_inc_sel_p1 ,--o-- + ex3_eac_sel_p0n(0 to 6) => ex3_eac_sel_p0n ,--o-- + ex3_eac_sel_p0 (0 to 6) => ex3_eac_sel_p0 ,--o-- + ex3_eac_sel_p1 (0 to 6) => ex3_eac_sel_p1 ,--o-- + ex3_sign_carry => ex3_sign_carry ,--o-- + ex3_flag_nan_cp1 => ex3_flag_nan_cp1 ,--o-- duplicate lat driven by unique gate + ex3_flag_gt_cp1 => ex3_flag_gt_cp1 ,--o-- duplicate lat driven by unique gate + ex3_flag_lt_cp1 => ex3_flag_lt_cp1 ,--o-- duplicate lat driven by unique gate + ex3_flag_eq_cp1 => ex3_flag_eq_cp1 ,--o-- duplicate lat driven by unique gate + ex3_flag_nan => ex3_flag_nan ,--o-- + ex3_flag_gt => ex3_flag_gt ,--o-- + ex3_flag_lt => ex3_flag_lt ,--o-- + ex3_flag_eq => ex3_flag_eq );--o-- + + + +--//################################################################ +--//# ex4 latches +--//################################################################ + + ex4_res_hi_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 53, btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd ,--inout + gd => gnd ,--inout + LCLK => add_ex4_lclk ,-- lclk.clk + D1CLK => add_ex4_d1clk , + D2CLK => add_ex4_d2clk , + SCANIN => ex4_res_si(0 to 52) , + SCANOUT => ex4_res_so(0 to 52) , + D => ex3_res(0 to 52) , + QB => ex4_res_l2_b(0 to 52) ); --LAT + + + ex4_res_lo_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 110, btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd ,--inout + gd => gnd ,--inout + LCLK => add_ex4_lclk ,-- lclk.clk + D1CLK => add_ex4_d1clk , + D2CLK => add_ex4_d2clk , + SCANIN => ex4_res_si(53 to 162) , + SCANOUT => ex4_res_so(53 to 162) , + D => ex3_res(53 to 162) , + QB => ex4_res_l2_b(53 to 162) ); --LAT + + ex4_res (0 to 162) <= not ex4_res_l2_b(0 to 162) ; +a_oinv: ex4_res_b(0 to 162) <= not ex4_res (0 to 162); +a_obuf: f_add_ex4_res (0 to 162) <= not ex4_res_b(0 to 162) ; -- output + + ex4_cmp_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 10, btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd ,--inout + gd => gnd ,--inout + LCLK => add_ex4_lclk ,-- lclk.clk + D1CLK => add_ex4_d1clk , + D2CLK => add_ex4_d2clk , + SCANIN => ex4_cmp_si , + SCANOUT => ex4_cmp_so , + D( 0) => ex3_flag_lt , + D( 1) => ex3_flag_lt_cp1 , + D( 2) => ex3_flag_gt , + D( 3) => ex3_flag_gt_cp1 , + D( 4) => ex3_flag_eq , + D( 5) => ex3_flag_eq_cp1 , + D( 6) => ex3_flag_nan , + D( 7) => ex3_flag_nan_cp1 , + D( 8) => ex3_sign_carry , + D( 9) => f_alg_ex3_sticky , + ------------------- + QB( 0) => ex4_flag_lt_b , --LAT + QB( 1) => ex4_fpcc_iu_b(0) , --LAT + QB( 2) => ex4_flag_gt_b , --LAT + QB( 3) => ex4_fpcc_iu_b(1) , --LAT + QB( 4) => ex4_flag_eq_b , --LAT + QB( 5) => ex4_fpcc_iu_b(2) , --LAT + QB( 6) => ex4_flag_nan_b , --LAT + QB( 7) => ex4_fpcc_iu_b(3) , --LAT + QB( 8) => ex4_sign_carry_b , --LAT + QB( 9) => ex4_sticky_b ); --LAT + + + f_add_ex4_flag_nan <= not ex4_flag_nan_b ;--output + f_add_ex4_flag_gt <= not ex4_flag_gt_b ;--output + f_add_ex4_flag_lt <= not ex4_flag_lt_b ;--output + f_add_ex4_flag_eq <= not ex4_flag_eq_b ;--output + f_add_ex4_fpcc_iu(0 to 3) <= not ex4_fpcc_iu_b(0 to 3) ;--output + f_add_ex4_sign_carry <= not ex4_sign_carry_b ;--output + f_add_ex4_sticky <= not ex4_sticky_b ;--output + + + f_add_ex4_to_int_ovf_wd(0) <= ex4_res(130) ; + f_add_ex4_to_int_ovf_wd(1) <= ex4_res(131) ; + f_add_ex4_to_int_ovf_dw(0) <= ex4_res(98) ; + f_add_ex4_to_int_ovf_dw(1) <= ex4_res(99) ; + +--//################################################################ +--//# ex4 logic +--//################################################################ + + + +--//################################################################ +--//# scan string +--//################################################################ + + act_si (0 to 8) <= act_so (1 to 8) & f_add_si ; + ex4_res_si (0 to 162) <= ex4_res_so (1 to 162) & act_so(0); + ex4_cmp_si (0 to 9) <= ex4_cmp_so (1 to 9) & ex4_res_so(0); + f_add_so <= ex4_cmp_so (0) ; + +end; -- fuq_add ARCHITECTURE diff --git a/rel/src/vhdl/work/fuq_add_all1.vhdl b/rel/src/vhdl/work/fuq_add_all1.vhdl new file mode 100644 index 0000000..e84f65b --- /dev/null +++ b/rel/src/vhdl/work/fuq_add_all1.vhdl @@ -0,0 +1,117 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; use ieee.std_logic_1164.all ; +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + +entity fuq_add_all1 is port( + ex3_inc_byt_c_b :in std_ulogic_vector(0 to 6); -- from each byte section + ex3_inc_byt_c_glb :out std_ulogic_vector(1 to 6); + ex3_inc_byt_c_glb_b :out std_ulogic_vector(1 to 6); + ex3_inc_all1 :out std_ulogic + ); + + + +END fuq_add_all1; + + +ARCHITECTURE fuq_add_all1 OF fuq_add_all1 IS + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal ex3_inc_byt_g1 :std_ulogic_vector(0 to 6); + signal ex3_inc_byt_g2_b :std_ulogic_vector(0 to 6); + signal ex3_inc_byt_g4 :std_ulogic_vector(0 to 6); + signal ex3_inc_byt_g8_b :std_ulogic_vector(0 to 6); + signal ex3_inc_byt_g_glb_int :std_ulogic_vector(1 to 6); + + + +BEGIN + + ii: ex3_inc_byt_g1(0 to 6) <= not ex3_inc_byt_c_b(0 to 6);--expect some wire distance between latches + -- drive to a common location + + g26: ex3_inc_byt_g2_b(6) <= not( ex3_inc_byt_g1(6) ); + g25: ex3_inc_byt_g2_b(5) <= not( ex3_inc_byt_g1(5) and ex3_inc_byt_g1(6) ); + g24: ex3_inc_byt_g2_b(4) <= not( ex3_inc_byt_g1(4) and ex3_inc_byt_g1(5) ); + g23: ex3_inc_byt_g2_b(3) <= not( ex3_inc_byt_g1(3) and ex3_inc_byt_g1(4) ); + g22: ex3_inc_byt_g2_b(2) <= not( ex3_inc_byt_g1(2) and ex3_inc_byt_g1(3) ); + g21: ex3_inc_byt_g2_b(1) <= not( ex3_inc_byt_g1(1) and ex3_inc_byt_g1(2) ); + g20: ex3_inc_byt_g2_b(0) <= not( ex3_inc_byt_g1(0) and ex3_inc_byt_g1(1) ); + + g46: ex3_inc_byt_g4(6) <= not( ex3_inc_byt_g2_b(6) ); + g45: ex3_inc_byt_g4(5) <= not( ex3_inc_byt_g2_b(5) ); + g44: ex3_inc_byt_g4(4) <= not( ex3_inc_byt_g2_b(4) or ex3_inc_byt_g2_b(6) ); + g43: ex3_inc_byt_g4(3) <= not( ex3_inc_byt_g2_b(3) or ex3_inc_byt_g2_b(5) ); + g42: ex3_inc_byt_g4(2) <= not( ex3_inc_byt_g2_b(2) or ex3_inc_byt_g2_b(4) ); + g41: ex3_inc_byt_g4(1) <= not( ex3_inc_byt_g2_b(1) or ex3_inc_byt_g2_b(3) ); + g40: ex3_inc_byt_g4(0) <= not( ex3_inc_byt_g2_b(0) or ex3_inc_byt_g2_b(2) ); + + g86: ex3_inc_byt_g8_b(6) <= not( ex3_inc_byt_g4(6) ); + g85: ex3_inc_byt_g8_b(5) <= not( ex3_inc_byt_g4(5) ); + g84: ex3_inc_byt_g8_b(4) <= not( ex3_inc_byt_g4(4) ); + g83: ex3_inc_byt_g8_b(3) <= not( ex3_inc_byt_g4(3) ); + g82: ex3_inc_byt_g8_b(2) <= not( ex3_inc_byt_g4(2) and ex3_inc_byt_g4(6) ); + g81: ex3_inc_byt_g8_b(1) <= not( ex3_inc_byt_g4(1) and ex3_inc_byt_g4(5) ); + g80: ex3_inc_byt_g8_b(0) <= not( ex3_inc_byt_g4(0) and ex3_inc_byt_g4(4) ); + + all1: ex3_inc_all1 <= not ex3_inc_byt_g8_b(0); + iop1: ex3_inc_byt_c_glb(1) <= not ex3_inc_byt_g8_b(1); -- drive back from common + iop2: ex3_inc_byt_c_glb(2) <= not ex3_inc_byt_g8_b(2); -- drive back from common + iop3: ex3_inc_byt_c_glb(3) <= not ex3_inc_byt_g8_b(3); -- drive back from common + iop4: ex3_inc_byt_c_glb(4) <= not ex3_inc_byt_g8_b(4); -- drive back from common + iop5: ex3_inc_byt_c_glb(5) <= not ex3_inc_byt_g8_b(5); -- drive back from common + iop6: ex3_inc_byt_c_glb(6) <= not ex3_inc_byt_g8_b(6); -- drive back from common + + ionn1: ex3_inc_byt_g_glb_int(1) <= not ex3_inc_byt_g8_b(1); + ionn2: ex3_inc_byt_g_glb_int(2) <= not ex3_inc_byt_g8_b(2); + ionn3: ex3_inc_byt_g_glb_int(3) <= not ex3_inc_byt_g8_b(3); + ionn4: ex3_inc_byt_g_glb_int(4) <= not ex3_inc_byt_g8_b(4); + ionn5: ex3_inc_byt_g_glb_int(5) <= not ex3_inc_byt_g8_b(5); + ionn6: ex3_inc_byt_g_glb_int(6) <= not ex3_inc_byt_g8_b(6); + + ion1: ex3_inc_byt_c_glb_b(1) <= not ex3_inc_byt_g_glb_int(1) ; -- drive back from common + ion2: ex3_inc_byt_c_glb_b(2) <= not ex3_inc_byt_g_glb_int(2) ; -- drive back from common + ion3: ex3_inc_byt_c_glb_b(3) <= not ex3_inc_byt_g_glb_int(3) ; -- drive back from common + ion4: ex3_inc_byt_c_glb_b(4) <= not ex3_inc_byt_g_glb_int(4) ; -- drive back from common + ion5: ex3_inc_byt_c_glb_b(5) <= not ex3_inc_byt_g_glb_int(5) ; -- drive back from common + ion6: ex3_inc_byt_c_glb_b(6) <= not ex3_inc_byt_g_glb_int(6) ; -- drive back from common + + + +END; -- ARCH fuq_add_all1 diff --git a/rel/src/vhdl/work/fuq_add_glbc.vhdl b/rel/src/vhdl/work/fuq_add_glbc.vhdl new file mode 100644 index 0000000..cd7d831 --- /dev/null +++ b/rel/src/vhdl/work/fuq_add_glbc.vhdl @@ -0,0 +1,632 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; use ieee.std_logic_1164.all ; +library ibm; + + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + +entity fuq_add_glbc is port( + ex3_g16 :in std_ulogic_vector(0 to 6); -- from each byte section + ex3_t16 :in std_ulogic_vector(0 to 6); -- from each byte section + + ex3_inc_all1 :in std_ulogic; + ex3_effsub :in std_ulogic; + ex3_effsub_npz :in std_ulogic; + ex3_effadd_npz :in std_ulogic; + f_alg_ex3_frc_sel_p1 :in std_ulogic; + f_alg_ex3_sticky :in std_ulogic; + f_pic_ex3_is_nan :in std_ulogic; + f_pic_ex3_is_gt :in std_ulogic; + f_pic_ex3_is_lt :in std_ulogic; + f_pic_ex3_is_eq :in std_ulogic; + f_pic_ex3_cmp_sgnpos :in std_ulogic; + f_pic_ex3_cmp_sgnneg :in std_ulogic; + -------------------- + ex3_g128 :out std_ulogic_vector(1 to 6); -- to each byte section + ex3_g128_b :out std_ulogic_vector(1 to 6); -- to each byte section + ex3_t128 :out std_ulogic_vector(1 to 6); -- to each byte section + ex3_t128_b :out std_ulogic_vector(1 to 6); -- to each byte section + -------------------- + ex3_flip_inc_p0 :out std_ulogic; + ex3_flip_inc_p1 :out std_ulogic; + ex3_inc_sel_p0 :out std_ulogic; + ex3_inc_sel_p1 :out std_ulogic; + ex3_eac_sel_p0n :out std_ulogic_vector(0 to 6); + ex3_eac_sel_p0 :out std_ulogic_vector(0 to 6); + ex3_eac_sel_p1 :out std_ulogic_vector(0 to 6); + + ex3_sign_carry :out std_ulogic; + ex3_flag_nan_cp1 :out std_ulogic; + ex3_flag_gt_cp1 :out std_ulogic; + ex3_flag_lt_cp1 :out std_ulogic; + ex3_flag_eq_cp1 :out std_ulogic; + ex3_flag_nan :out std_ulogic; + ex3_flag_gt :out std_ulogic; + ex3_flag_lt :out std_ulogic; + ex3_flag_eq :out std_ulogic + ); + + + +END fuq_add_glbc; + + +ARCHITECTURE fuq_add_glbc OF fuq_add_glbc IS + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + + signal cp0_g32_01_b, cp0_g32_23_b, cp0_g32_45_b, cp0_g32_66_b :std_ulogic; + signal cp0_t32_01_b , cp0_t32_23_b, cp0_t32_45_b, cp0_t32_66_b :std_ulogic; + signal cp0_g64_03, cp0_g64_46, cp0_t64_03, cp0_t64_46 :std_ulogic; + signal cp0_g128_06_b, cp0_t128_06_b :std_ulogic; + signal cp0_all1_b, cp0_all1_p, cp0_co_p0, cp0_co_p1 :std_ulogic; + signal cp0_flip_inc_p1_b, ex3_inc_sel_p0_b, ex3_sign_carry_b :std_ulogic; + signal ex3_my_gt_b, ex3_my_lt , ex3_my_eq_b :std_ulogic; + signal ex3_my_gt , ex3_my_eq :std_ulogic; + signal ex3_gt_pos_b , ex3_gt_neg_b , ex3_lt_pos_b , ex3_lt_neg_b , ex3_eq_eq_b :std_ulogic; + signal ex3_is_gt_b, ex3_is_lt_b, ex3_is_eq_b, ex3_sgn_eq :std_ulogic; + + signal cp7_g32_00_b , cp7_g32_12_b , cp7_g32_34_b , cp7_g32_56_b :std_ulogic; + signal cp7_t32_00_b , cp7_t32_12_b , cp7_t32_34_b :std_ulogic; + signal cp7_g64_02 , cp7_g64_36 , cp7_t64_02 :std_ulogic; + signal cp7_g128_06_b :std_ulogic; + signal cp7_all1_b , cp7_all1_p , cp7_co_p0 :std_ulogic; + signal cp7_sel_p0n_x_b , cp7_sel_p0n_y_b :std_ulogic; + signal cp7_sel_p0_b , cp7_sel_p1_b :std_ulogic; + signal cp7_sub_sticky , cp7_sub_stickyn :std_ulogic; + signal cp7_add_frcp1_b , cp7_add_frcp0_b :std_ulogic; + + signal cp6_g32_00_b , cp6_g32_12_b , cp6_g32_34_b , cp6_g32_56_b :std_ulogic; + signal cp6_t32_00_b , cp6_t32_12_b , cp6_t32_34_b :std_ulogic; + signal cp6_g64_02 , cp6_g64_36 , cp6_t64_02 :std_ulogic; + signal cp6_g128_06_b :std_ulogic; + signal cp6_all1_b , cp6_all1_p , cp6_co_p0 :std_ulogic; + signal cp6_sel_p0n_x_b , cp6_sel_p0n_y_b :std_ulogic; + signal cp6_sel_p0_b , cp6_sel_p1_b :std_ulogic; + signal cp6_sub_sticky , cp6_sub_stickyn :std_ulogic; + signal cp6_add_frcp1_b , cp6_add_frcp0_b :std_ulogic; + + signal cp5_g32_00_b , cp5_g32_12_b , cp5_g32_34_b , cp5_g32_56_b :std_ulogic; + signal cp5_t32_00_b , cp5_t32_12_b , cp5_t32_34_b , cp5_t32_56_b :std_ulogic; + signal cp5_g64_02 , cp5_g64_36 , cp5_t64_02 :std_ulogic; + signal cp5_g128_06_b :std_ulogic; + signal cp5_all1_b , cp5_all1_p , cp5_co_p0 :std_ulogic; + signal cp5_sel_p0n_x_b , cp5_sel_p0n_y_b :std_ulogic; + signal cp5_sel_p0_b , cp5_sel_p1_b :std_ulogic; + signal cp5_sub_sticky , cp5_sub_stickyn :std_ulogic; + signal cp5_add_frcp1_b , cp5_add_frcp0_b :std_ulogic; + + + + signal cp4_g32_01_b, cp4_g32_23_b, cp4_g32_45_b, cp4_g32_66_b :std_ulogic; + signal cp4_t32_01_b , cp4_t32_23_b, cp4_t32_45_b, cp4_t32_66_b :std_ulogic; + signal cp4_g64_03, cp4_g64_46, cp4_t64_03, cp4_t64_46 :std_ulogic; + signal cp4_g128_06_b :std_ulogic; + signal cp4_all1_b , cp4_all1_p , cp4_co_p0 :std_ulogic; + signal cp4_sel_p0n_x_b , cp4_sel_p0n_y_b :std_ulogic; + signal cp4_sel_p0_b , cp4_sel_p1_b :std_ulogic; + signal cp4_sub_sticky , cp4_sub_stickyn :std_ulogic; + signal cp4_add_frcp1_b , cp4_add_frcp0_b :std_ulogic; + + + signal cp3_g32_00_b , cp3_g32_12_b , cp3_g32_34_b , cp3_g32_56_b :std_ulogic; + signal cp3_t32_00_b , cp3_t32_12_b , cp3_t32_34_b , cp3_t32_56_b :std_ulogic; + signal cp3_g64_02 , cp3_g64_36 , cp3_t64_02 , cp3_t64_36 :std_ulogic; + signal cp3_g128_06_b :std_ulogic; + signal cp3_all1_b , cp3_all1_p , cp3_co_p0 :std_ulogic; + signal cp3_sel_p0n_x_b , cp3_sel_p0n_y_b :std_ulogic; + signal cp3_sel_p0_b , cp3_sel_p1_b :std_ulogic; + signal cp3_sub_sticky , cp3_sub_stickyn :std_ulogic; + signal cp3_add_frcp1_b , cp3_add_frcp0_b :std_ulogic; + + signal cp2_g32_01_b, cp2_g32_23_b, cp2_g32_45_b, cp2_g32_66_b :std_ulogic; + signal cp2_t32_01_b , cp2_t32_23_b, cp2_t32_45_b, cp2_t32_66_b :std_ulogic; + signal cp2_g64_03, cp2_g64_46, cp2_t64_03, cp2_t64_46 :std_ulogic; + signal cp2_g128_06_b :std_ulogic; + signal cp2_all1_b , cp2_all1_p , cp2_co_p0 :std_ulogic; + signal cp2_sel_p0n_x_b , cp2_sel_p0n_y_b :std_ulogic; + signal cp2_sel_p0_b , cp2_sel_p1_b :std_ulogic; + signal cp2_sub_sticky , cp2_sub_stickyn :std_ulogic; + signal cp2_add_frcp1_b , cp2_add_frcp0_b :std_ulogic; + + signal cp1_g32_01_b, cp1_g32_23_b, cp1_g32_45_b, cp1_g32_66_b :std_ulogic; + signal cp1_t32_01_b , cp1_t32_23_b, cp1_t32_45_b, cp1_t32_66_b :std_ulogic; + signal cp1_g64_03, cp1_g64_46, cp1_t64_03, cp1_t64_46 :std_ulogic; + signal cp1_g128_06_b :std_ulogic; + signal cp1_all1_b , cp1_all1_p , cp1_co_p0 :std_ulogic; + signal cp1_sel_p0n_x_b , cp1_sel_p0n_y_b :std_ulogic; + signal cp1_sel_p0_b , cp1_sel_p1_b :std_ulogic; + signal cp1_sub_sticky , cp1_sub_stickyn :std_ulogic; + signal cp1_add_frcp1_b , cp1_add_frcp0_b :std_ulogic; + +signal cp1_g32_11_b, cp1_t32_11_b, cp1_g64_13, cp1_t64_13, cp1_g128_16_b, cp1_t128_16_b :std_ulogic; --EXTRA +signal cp2_g64_23, cp2_t64_23, cp2_g128_26_b, cp2_t128_26_b :std_ulogic; +signal cp3_g128_36_b, cp3_t128_36_b :std_ulogic; +signal cp4_g128_46_b, cp4_t128_46_b :std_ulogic; +signal cp5_g64_56, cp5_t64_56, cp5_g128_56_b, cp5_t128_56_b :std_ulogic; +signal cp6_g32_66_b, cp6_t32_66_b :std_ulogic; + +signal cp1_g128_16, cp1_t128_16 :std_ulogic; --DRIVER +signal cp2_g128_26, cp2_t128_26 :std_ulogic; +signal cp3_g128_36, cp3_t128_36 :std_ulogic; +signal cp4_g128_46, cp4_t128_46 :std_ulogic; +signal cp5_g128_56, cp5_t128_56 :std_ulogic; +signal cp6_g128_66, cp6_t128_66 :std_ulogic; + + + + + +BEGIN + +--=######################################### +--= global carry chain +--=######################################### + -- try to put all long wire from BYT to global + -- parallel copies should allow for smaller aoi/oai blocks + +--=######################################### +--= CMP COPY +--=######################################### + + +ucp0_g32_01: cp0_g32_01_b <= not( ex3_g16(0) or ( ex3_t16(0) and ex3_g16(1) ) ); --cw_aoi21 +ucp0_g32_23: cp0_g32_23_b <= not( ex3_g16(2) or ( ex3_t16(2) and ex3_g16(3) ) ); --cw_aoi21 +ucp0_g32_45: cp0_g32_45_b <= not( ex3_g16(4) or ( ex3_t16(4) and ex3_g16(5) ) ); --cw_aoi21 +ucp0_g32_66: cp0_g32_66_b <= not( ex3_g16(6) ); --cw_invert --done + +ucp0_t32_01: cp0_t32_01_b <= not( ex3_t16(0) and ex3_t16(1) ); --cw_nand2 +ucp0_t32_23: cp0_t32_23_b <= not( ex3_t16(2) and ex3_t16(3) ); --cw_nand2 +ucp0_t32_45: cp0_t32_45_b <= not( ex3_t16(4) and ex3_t16(5) ); --cw_nand2 +ucp0_t32_66: cp0_t32_66_b <= not( ex3_t16(6) ); --cw_invert + +ucp0_g64_03: cp0_g64_03 <= not( cp0_g32_01_b and (cp0_t32_01_b or cp0_g32_23_b) ); --cw_oai21 +ucp0_g64_46: cp0_g64_46 <= not( cp0_g32_45_b and (cp0_t32_45_b or cp0_g32_66_b) ); --cw_oai21 + +ucp0_t64_03: cp0_t64_03 <= not( cp0_t32_01_b or cp0_t32_23_b ); --cw_nor2 +ucp0_t64_46: cp0_t64_46 <= not( cp0_g32_45_b and (cp0_t32_45_b or cp0_t32_66_b) ); --cw_oai21 + +ucp0_g128_06: cp0_g128_06_b <= not( cp0_g64_03 or ( cp0_t64_03 and cp0_g64_46 ) ); --cw_aoi21 +ucp0_t128_06: cp0_t128_06_b <= not( cp0_g64_03 or ( cp0_t64_03 and cp0_t64_46 ) ); --cw_aoi21 + +ucp0_all1n: cp0_all1_b <= not ex3_inc_all1 ;--cw_invert +ucp0_all1p: cp0_all1_p <= not cp0_all1_b ;--cw_invert +ucp0_co_p0: cp0_co_p0 <= not( cp0_g128_06_b ) ;--cw_invert +ucp0_co_p1: cp0_co_p1 <= not( cp0_t128_06_b ) ;--cw_invert + + + ---------------- incr eac selects -------------------- + + ex3_flip_inc_p0 <= ex3_effsub; --NOT MAPPED --output-- +ucp0_f1in: cp0_flip_inc_p1_b <= not( ex3_effsub and cp0_all1_b ); --cw_nand2 +ucp0_f1i: ex3_flip_inc_p1 <= not( cp0_flip_inc_p1_b ); --cw_invert --output-- + +ucp0_s1i: ex3_inc_sel_p1 <= not cp0_g128_06_b ; --cw_invert --OUTPUT-- +ucp0_s0in: ex3_inc_sel_p0_b <= not cp0_g128_06_b ; --cw_invert +ucp0_s0i: ex3_inc_sel_p0 <= not ex3_inc_sel_p0_b; --cw_invert --OUTPUT-- + + ---------------- sign selects -------------------- + +ucp0_sgn0: ex3_sign_carry_b <= not( ex3_effsub and cp0_all1_p and cp0_co_p0 );--cw_nand3 +ucp0_sgn1: ex3_sign_carry <= not( ex3_sign_carry_b ); --cw_invert --OUTPUT-- + + ----------------- compares --------------------------- + +ucp0_my_gtn: ex3_my_gt_b <= not( cp0_co_p0 and cp0_all1_p );--cw_nand2 +ucp0_my_lt: ex3_my_lt <= not( cp0_co_p1 and cp0_all1_p );--cw_nand2 +ucp0_my_eqb: ex3_my_eq_b <= not( cp0_co_p1 and cp0_all1_p and cp0_g128_06_b );--cw_nand3 + +ucp0_my_gt: ex3_my_gt <= not ex3_my_gt_b ; --cw_invert +ucp0_my_eq: ex3_my_eq <= not ex3_my_eq_b ; --cw_invert + +ucp0_gt_pos: ex3_gt_pos_b <= not( ex3_my_gt and f_pic_ex3_cmp_sgnpos);--cw_nand2 +ucp0_gt_neg: ex3_gt_neg_b <= not( ex3_my_lt and f_pic_ex3_cmp_sgnneg);--cw_nand2 +ucp0_lt_pos: ex3_lt_pos_b <= not( ex3_my_lt and f_pic_ex3_cmp_sgnpos);--cw_nand2 +ucp0_lt_neg: ex3_lt_neg_b <= not( ex3_my_gt and f_pic_ex3_cmp_sgnneg);--cw_nand2 +ucp0_eq_eq: ex3_eq_eq_b <= not( ex3_my_eq and ex3_sgn_eq );--cw_nand3 + +ucp0_flg_gt: ex3_flag_gt <= not( ex3_gt_pos_b and ex3_gt_neg_b and ex3_is_gt_b );--cw_nand3 --output-- +ucp0_flg_gt1: ex3_flag_gt_cp1 <= not( ex3_gt_pos_b and ex3_gt_neg_b and ex3_is_gt_b );--cw_nand3 --output-- +ucp0_flg_lt: ex3_flag_lt <= not( ex3_lt_pos_b and ex3_lt_neg_b and ex3_is_lt_b );--cw_nand3 --output-- +ucp0_flg_lt1: ex3_flag_lt_cp1 <= not( ex3_lt_pos_b and ex3_lt_neg_b and ex3_is_lt_b );--cw_nand3 --output-- +ucp0_flg_eq: ex3_flag_eq <= not( ex3_eq_eq_b and ex3_is_eq_b );--cw_nand2 --output-- +ucp0_flg_eq1: ex3_flag_eq_cp1 <= not( ex3_eq_eq_b and ex3_is_eq_b );--cw_nand2 --output-- + + ex3_flag_nan <= f_pic_ex3_is_nan; --NOT MAPPED --output-- + ex3_flag_nan_cp1 <= f_pic_ex3_is_nan; --NOT MAPPED --output-- + + ex3_is_gt_b <= not( f_pic_ex3_is_gt );--NOT MAPPED + ex3_is_lt_b <= not( f_pic_ex3_is_lt );--NOT MAPPED + ex3_is_eq_b <= not( f_pic_ex3_is_eq );--NOT MAPPED + ex3_sgn_eq <= f_pic_ex3_cmp_sgnpos or f_pic_ex3_cmp_sgnneg ; --NOT MAPPED + + +--=######################################### +--= BYT_0 MSB COPY +--=######################################### + +ucp1_g32_11: cp1_g32_11_b <= not( ex3_g16(1) ); --cw_aoi21 --EXTRA +ucp1_g32_01: cp1_g32_01_b <= not( ex3_g16(0) or ( ex3_t16(0) and ex3_g16(1) ) ); --cw_aoi21 +ucp1_g32_23: cp1_g32_23_b <= not( ex3_g16(2) or ( ex3_t16(2) and ex3_g16(3) ) ); --cw_aoi21 +ucp1_g32_45: cp1_g32_45_b <= not( ex3_g16(4) or ( ex3_t16(4) and ex3_g16(5) ) ); --cw_aoi21 +ucp1_g32_66: cp1_g32_66_b <= not( ex3_g16(6) ); --cw_invert --done + +ucp1_t32_11: cp1_t32_11_b <= not( ex3_t16(1) ); --cw_invert --EXTRA +ucp1_t32_01: cp1_t32_01_b <= not( ex3_t16(0) and ex3_t16(1) ); --cw_nand2 +ucp1_t32_23: cp1_t32_23_b <= not( ex3_t16(2) and ex3_t16(3) ); --cw_nand2 +ucp1_t32_45: cp1_t32_45_b <= not( ex3_t16(4) and ex3_t16(5) ); --cw_nand2 +ucp1_t32_66: cp1_t32_66_b <= not( ex3_t16(6) ); --cw_invert + +ucp1_g64_03: cp1_g64_03 <= not( cp1_g32_01_b and (cp1_t32_01_b or cp1_g32_23_b) ); --cw_oai21 +ucp1_g64_13: cp1_g64_13 <= not( cp1_g32_11_b and (cp1_t32_11_b or cp1_g32_23_b) ); --cw_oai21 --EXTRA +ucp1_g64_46: cp1_g64_46 <= not( cp1_g32_45_b and (cp1_t32_45_b or cp1_g32_66_b) ); --cw_oai21 + +ucp1_t64_03: cp1_t64_03 <= not( cp1_t32_01_b or cp1_t32_23_b ); --cw_nor2 +ucp1_t64_13: cp1_t64_13 <= not( cp1_t32_11_b or cp1_t32_23_b ); --cw_nor2 --EXTRA +ucp1_t64_46: cp1_t64_46 <= not( cp1_g32_45_b and (cp1_t32_45_b or cp1_t32_66_b) ); --cw_oai21 + +ucp1_g128_06: cp1_g128_06_b <= not( cp1_g64_03 or ( cp1_t64_03 and cp1_g64_46 ) ); --cw_aoi21 +ucp1_g128_16: cp1_g128_16_b <= not( cp1_g64_13 or ( cp1_t64_13 and cp1_g64_46 ) ); --cw_aoi21 --EXTRA +ucp1_t128_16: cp1_t128_16_b <= not( cp1_g64_13 or ( cp1_t64_13 and cp1_t64_46 ) ); --cw_aoi21 --EXTRA + + +ucp1_cog: ex3_g128(1) <= not( cp1_g128_16_b);--cw_invert --OUTPUT-- +ucp1_cogx: cp1_g128_16 <= not( cp1_g128_16_b);--cw_invert +ucp1_cogb: ex3_g128_b(1) <= not( cp1_g128_16 );--cw_invert --OUTPUT-- +ucp1_cot: ex3_t128(1) <= not( cp1_t128_16_b);--cw_invert --OUTPUT-- +ucp1_cotx: cp1_t128_16 <= not( cp1_t128_16_b);--cw_invert +ucp1_cotb: ex3_t128_b(1) <= not( cp1_t128_16 );--cw_invert --OUTPUT-- + +ucp1_all1n: cp1_all1_b <= not ex3_inc_all1 ;--cw_invert +ucp1_all1p: cp1_all1_p <= not cp1_all1_b ;--cw_invert +ucp1_co_p0: cp1_co_p0 <= not( cp1_g128_06_b ) ;--cw_invert + +ucp1_espnx: cp1_sel_p0n_x_b <= not( cp1_all1_b and ex3_effsub_npz);--cw_nand2 +ucp1_espny: cp1_sel_p0n_y_b <= not( cp1_g128_06_b and ex3_effsub_npz);--cw_nand2 +ucp1_selp0: cp1_sel_p0_b <= not( cp1_co_p0 and cp1_all1_p and cp1_sub_sticky );--cw_nand3 +ucp1_selp1: cp1_sel_p1_b <= not( cp1_co_p0 and cp1_all1_p and cp1_sub_stickyn );--cw_nand3 + +ucp1_espn: ex3_eac_sel_p0n(0) <= not( cp1_sel_p0n_x_b and cp1_sel_p0n_y_b);--cw_nand2 --OUTPUT-- +ucp1_esp0: ex3_eac_sel_p0(0) <= not( cp1_sel_p0_b and cp1_add_frcp0_b);--cw_nand2 --OUTPUT-- +ucp1_esp1: ex3_eac_sel_p1(0) <= not( cp1_sel_p1_b and cp1_add_frcp1_b);--cw_nand2 --OUTPUT-- + + cp1_sub_sticky <= ex3_effsub_npz and f_alg_ex3_sticky ;--NOT MAPPED + cp1_sub_stickyn <= ex3_effsub_npz and not f_alg_ex3_sticky ;--NOT MAPPED + cp1_add_frcp1_b <= not( ex3_effadd_npz and f_alg_ex3_frc_sel_p1 );--NOT MAPPED + cp1_add_frcp0_b <= not( ex3_effadd_npz and not f_alg_ex3_frc_sel_p1 );--NOT MAPPED + + +--=######################################### +--= BYT_1 MSB COPY +--=######################################### + +ucp2_g32_01: cp2_g32_01_b <= not( ex3_g16(0) or ( ex3_t16(0) and ex3_g16(1) ) ); --cw_aoi21 +ucp2_g32_23: cp2_g32_23_b <= not( ex3_g16(2) or ( ex3_t16(2) and ex3_g16(3) ) ); --cw_aoi21 +ucp2_g32_45: cp2_g32_45_b <= not( ex3_g16(4) or ( ex3_t16(4) and ex3_g16(5) ) ); --cw_aoi21 +ucp2_g32_66: cp2_g32_66_b <= not( ex3_g16(6) ); --cw_invert --done + +ucp2_t32_01: cp2_t32_01_b <= not( ex3_t16(0) and ex3_t16(1) ); --cw_nand2 +ucp2_t32_23: cp2_t32_23_b <= not( ex3_t16(2) and ex3_t16(3) ); --cw_nand2 +ucp2_t32_45: cp2_t32_45_b <= not( ex3_t16(4) and ex3_t16(5) ); --cw_nand2 +ucp2_t32_66: cp2_t32_66_b <= not( ex3_t16(6) ); --cw_invert + +ucp2_g64_23: cp2_g64_23 <= not( cp2_g32_23_b ); --cw_invert --EXTRA +ucp2_g64_03: cp2_g64_03 <= not( cp2_g32_01_b and (cp2_t32_01_b or cp2_g32_23_b) ); --cw_oai21 +ucp2_g64_46: cp2_g64_46 <= not( cp2_g32_45_b and (cp2_t32_45_b or cp2_g32_66_b) ); --cw_oai21 + +ucp2_t64_23: cp2_t64_23 <= not( cp2_t32_23_b ); --cw_invert --EXTRA +ucp2_t64_03: cp2_t64_03 <= not( cp2_t32_01_b or cp2_t32_23_b ); --cw_nor2 +ucp2_t64_46: cp2_t64_46 <= not( cp2_g32_45_b and (cp2_t32_45_b or cp2_t32_66_b) ); --cw_oai21 + +ucp2_g128_06: cp2_g128_06_b <= not( cp2_g64_03 or ( cp2_t64_03 and cp2_g64_46 ) ); --cw_aoi21 +ucp2_g128_26: cp2_g128_26_b <= not( cp2_g64_23 or ( cp2_t64_23 and cp2_g64_46 ) ); --cw_aoi21 --EXTRA +ucp2_t128_26: cp2_t128_26_b <= not( cp2_g64_23 or ( cp2_t64_23 and cp2_t64_46 ) ); --cw_aoi21 --EXTRA + + +ucp2_cog: ex3_g128(2) <= not( cp2_g128_26_b);--cw_invert --OUTPUT-- +ucp2_cogx: cp2_g128_26 <= not( cp2_g128_26_b);--cw_invert +ucp2_cogb: ex3_g128_b(2) <= not( cp2_g128_26 );--cw_invert --OUTPUT-- +ucp2_cot: ex3_t128(2) <= not( cp2_t128_26_b);--cw_invert --OUTPUT-- +ucp2_cotx: cp2_t128_26 <= not( cp2_t128_26_b);--cw_invert +ucp2_cotb: ex3_t128_b(2) <= not( cp2_t128_26 );--cw_invert --OUTPUT-- + + +ucp2_all1n: cp2_all1_b <= not ex3_inc_all1 ;--cw_invert +ucp2_all1p: cp2_all1_p <= not cp2_all1_b ;--cw_invert +ucp2_co_p0: cp2_co_p0 <= not( cp2_g128_06_b ) ;--cw_invert + +ucp2_espnx: cp2_sel_p0n_x_b <= not( cp2_all1_b and ex3_effsub_npz);--cw_nand2 +ucp2_espny: cp2_sel_p0n_y_b <= not( cp2_g128_06_b and ex3_effsub_npz);--cw_nand2 +ucp2_selp0: cp2_sel_p0_b <= not( cp2_co_p0 and cp2_all1_p and cp2_sub_sticky );--cw_nand3 +ucp2_selp1: cp2_sel_p1_b <= not( cp2_co_p0 and cp2_all1_p and cp2_sub_stickyn );--cw_nand3 + +ucp2_espn: ex3_eac_sel_p0n(1) <= not( cp2_sel_p0n_x_b and cp2_sel_p0n_y_b);--cw_nand2 --OUTPUT-- +ucp2_esp0: ex3_eac_sel_p0(1) <= not( cp2_sel_p0_b and cp2_add_frcp0_b);--cw_nand2 --OUTPUT-- +ucp2_esp1: ex3_eac_sel_p1(1) <= not( cp2_sel_p1_b and cp2_add_frcp1_b);--cw_nand2 --OUTPUT-- + + cp2_sub_sticky <= ex3_effsub_npz and f_alg_ex3_sticky ;--NOT MAPPED + cp2_sub_stickyn <= ex3_effsub_npz and not f_alg_ex3_sticky ;--NOT MAPPED + cp2_add_frcp1_b <= not( ex3_effadd_npz and f_alg_ex3_frc_sel_p1 );--NOT MAPPED + cp2_add_frcp0_b <= not( ex3_effadd_npz and not f_alg_ex3_frc_sel_p1 );--NOT MAPPED + + +--=######################################### +--= BYT_2 MSB COPY +--=######################################### + +ucp3_g32_00: cp3_g32_00_b <= not( ex3_g16(0) ) ; --cw_invert +ucp3_g32_12: cp3_g32_12_b <= not( ex3_g16(1) or ( ex3_t16(1) and ex3_g16(2) ) ); --cw_aoi21 +ucp3_g32_34: cp3_g32_34_b <= not( ex3_g16(3) or ( ex3_t16(3) and ex3_g16(4) ) ); --cw_aoi21 +ucp3_g32_56: cp3_g32_56_b <= not( ex3_g16(5) or ( ex3_t16(5) and ex3_g16(6) ) ); --cw_aoi21 + +ucp3_t32_00: cp3_t32_00_b <= not( ex3_t16(0) ); --cw_invert +ucp3_t32_12: cp3_t32_12_b <= not( ex3_t16(1) and ex3_t16(2) ); --cw_nand2 +ucp3_t32_34: cp3_t32_34_b <= not( ex3_t16(3) and ex3_t16(4) ); --cw_nand2 +ucp3_t32_56: cp3_t32_56_b <= not( ex3_g16(5) or ( ex3_t16(5) and ex3_t16(6) ) ); --cw_aoi21 + +ucp3_g64_02: cp3_g64_02 <= not( cp3_g32_00_b and (cp3_t32_00_b or cp3_g32_12_b) ); --cw_oai21 +ucp3_g64_36: cp3_g64_36 <= not( cp3_g32_34_b and (cp3_t32_34_b or cp3_g32_56_b) ); --cw_oai21 + +ucp3_t64_02: cp3_t64_02 <= not( cp3_t32_00_b or cp3_t32_12_b ); --cw_nor2 +ucp3_t64_36: cp3_t64_36 <= not( cp3_g32_34_b and (cp3_t32_34_b or cp3_t32_56_b) ); --cw_oai21 + +ucp3_g128_06: cp3_g128_06_b <= not( cp3_g64_02 or ( cp3_t64_02 and cp3_g64_36 ) ); --cw_aoi21 +ucp3_g128_36: cp3_g128_36_b <= not( cp3_g64_36 ); --cw_invert --EXTRA +ucp3_t128_36: cp3_t128_36_b <= not( cp3_t64_36 ); --cw_invert --EXTRA + + +ucp3_cog: ex3_g128(3) <= not( cp3_g128_36_b);--cw_invert --OUTPUT-- +ucp3_cogx: cp3_g128_36 <= not( cp3_g128_36_b);--cw_invert +ucp3_cogb: ex3_g128_b(3) <= not( cp3_g128_36 );--cw_invert --OUTPUT-- +ucp3_cot: ex3_t128(3) <= not( cp3_t128_36_b);--cw_invert --OUTPUT-- +ucp3_cotx: cp3_t128_36 <= not( cp3_t128_36_b);--cw_invert +ucp3_cotb: ex3_t128_b(3) <= not( cp3_t128_36 );--cw_invert --OUTPUT-- + + +ucp3_all1n: cp3_all1_b <= not ex3_inc_all1 ;--cw_invert +ucp3_all1p: cp3_all1_p <= not cp3_all1_b ;--cw_invert +ucp3_co_p0: cp3_co_p0 <= not( cp3_g128_06_b ) ;--cw_invert + +ucp3_espnx: cp3_sel_p0n_x_b <= not( cp3_all1_b and ex3_effsub_npz);--cw_nand2 +ucp3_espny: cp3_sel_p0n_y_b <= not( cp3_g128_06_b and ex3_effsub_npz);--cw_nand2 +ucp3_selp0: cp3_sel_p0_b <= not( cp3_co_p0 and cp3_all1_p and cp3_sub_sticky );--cw_nand3 +ucp3_selp1: cp3_sel_p1_b <= not( cp3_co_p0 and cp3_all1_p and cp3_sub_stickyn );--cw_nand3 + +ucp3_espn: ex3_eac_sel_p0n(2) <= not( cp3_sel_p0n_x_b and cp3_sel_p0n_y_b);--cw_nand2 --OUTPUT-- +ucp3_esp0: ex3_eac_sel_p0(2) <= not( cp3_sel_p0_b and cp3_add_frcp0_b);--cw_nand2 --OUTPUT-- +ucp3_esp1: ex3_eac_sel_p1(2) <= not( cp3_sel_p1_b and cp3_add_frcp1_b);--cw_nand2 --OUTPUT-- + + cp3_sub_sticky <= ex3_effsub_npz and f_alg_ex3_sticky ;--NOT MAPPED + cp3_sub_stickyn <= ex3_effsub_npz and not f_alg_ex3_sticky ;--NOT MAPPED + cp3_add_frcp1_b <= not( ex3_effadd_npz and f_alg_ex3_frc_sel_p1 );--NOT MAPPED + cp3_add_frcp0_b <= not( ex3_effadd_npz and not f_alg_ex3_frc_sel_p1 );--NOT MAPPED + + + +--=######################################### +--= BYT_3 MSB COPY +--=######################################### + +ucp4_g32_01: cp4_g32_01_b <= not( ex3_g16(0) or ( ex3_t16(0) and ex3_g16(1) ) ); --cw_aoi21 +ucp4_g32_23: cp4_g32_23_b <= not( ex3_g16(2) or ( ex3_t16(2) and ex3_g16(3) ) ); --cw_aoi21 +ucp4_g32_45: cp4_g32_45_b <= not( ex3_g16(4) or ( ex3_t16(4) and ex3_g16(5) ) ); --cw_aoi21 +ucp4_g32_66: cp4_g32_66_b <= not( ex3_g16(6) ); --cw_invert --done + +ucp4_t32_01: cp4_t32_01_b <= not( ex3_t16(0) and ex3_t16(1) ); --cw_nand2 +ucp4_t32_23: cp4_t32_23_b <= not( ex3_t16(2) and ex3_t16(3) ); --cw_nand2 +ucp4_t32_45: cp4_t32_45_b <= not( ex3_t16(4) and ex3_t16(5) ); --cw_nand2 +ucp4_t32_66: cp4_t32_66_b <= not( ex3_t16(6) ); --cw_invert + +ucp4_g64_03: cp4_g64_03 <= not( cp4_g32_01_b and (cp4_t32_01_b or cp4_g32_23_b) ); --cw_oai21 +ucp4_g64_46: cp4_g64_46 <= not( cp4_g32_45_b and (cp4_t32_45_b or cp4_g32_66_b) ); --cw_oai21 + +ucp4_t64_03: cp4_t64_03 <= not( cp4_t32_01_b or cp4_t32_23_b ); --cw_nor2 +ucp4_t64_46: cp4_t64_46 <= not( cp4_g32_45_b and (cp4_t32_45_b or cp4_t32_66_b) ); --cw_oai21 + +ucp4_g128_06: cp4_g128_06_b <= not( cp4_g64_03 or ( cp4_t64_03 and cp4_g64_46 ) ); --cw_aoi21 +ucp4_g128_46: cp4_g128_46_b <= not( cp4_g64_46 ); --cw_invert --EXTRA +ucp4_t128_46: cp4_t128_46_b <= not( cp4_t64_46 ); --cw_invert --EXTRA + +ucp4_cog: ex3_g128(4) <= not( cp4_g128_46_b);--cw_invert --OUTPUT-- +ucp4_cogx: cp4_g128_46 <= not( cp4_g128_46_b);--cw_invert +ucp4_cogb: ex3_g128_b(4) <= not( cp4_g128_46 );--cw_invert --OUTPUT-- +ucp4_cot: ex3_t128(4) <= not( cp4_t128_46_b);--cw_invert --OUTPUT-- +ucp4_cotx: cp4_t128_46 <= not( cp4_t128_46_b);--cw_invert +ucp4_cotb: ex3_t128_b(4) <= not( cp4_t128_46 );--cw_invert --OUTPUT-- + +ucp4_all1n: cp4_all1_b <= not ex3_inc_all1 ;--cw_invert +ucp4_all1p: cp4_all1_p <= not cp4_all1_b ;--cw_invert +ucp4_co_p0: cp4_co_p0 <= not( cp4_g128_06_b ) ;--cw_invert + +ucp4_espnx: cp4_sel_p0n_x_b <= not( cp4_all1_b and ex3_effsub_npz);--cw_nand2 +ucp4_espny: cp4_sel_p0n_y_b <= not( cp4_g128_06_b and ex3_effsub_npz);--cw_nand2 +ucp4_selp0: cp4_sel_p0_b <= not( cp4_co_p0 and cp4_all1_p and cp4_sub_sticky );--cw_nand3 +ucp4_selp1: cp4_sel_p1_b <= not( cp4_co_p0 and cp4_all1_p and cp4_sub_stickyn );--cw_nand3 + +ucp4_espn: ex3_eac_sel_p0n(3) <= not( cp4_sel_p0n_x_b and cp4_sel_p0n_y_b);--cw_nand2 --OUTPUT-- +ucp4_esp0: ex3_eac_sel_p0(3) <= not( cp4_sel_p0_b and cp4_add_frcp0_b);--cw_nand2 --OUTPUT-- +ucp4_esp1: ex3_eac_sel_p1(3) <= not( cp4_sel_p1_b and cp4_add_frcp1_b);--cw_nand2 --OUTPUT-- + + cp4_sub_sticky <= ex3_effsub_npz and f_alg_ex3_sticky ;--NOT MAPPED + cp4_sub_stickyn <= ex3_effsub_npz and not f_alg_ex3_sticky ;--NOT MAPPED + cp4_add_frcp1_b <= not( ex3_effadd_npz and f_alg_ex3_frc_sel_p1 );--NOT MAPPED + cp4_add_frcp0_b <= not( ex3_effadd_npz and not f_alg_ex3_frc_sel_p1 );--NOT MAPPED + + +--=######################################### +--= BYT_4 +--=######################################### + +ucp5_g32_00: cp5_g32_00_b <= not( ex3_g16(0) ); --cw_invert +ucp5_g32_12: cp5_g32_12_b <= not( ex3_g16(1) or ( ex3_t16(1) and ex3_g16(2) ) ); --cw_aoi21 +ucp5_g32_34: cp5_g32_34_b <= not( ex3_g16(3) or ( ex3_t16(3) and ex3_g16(4) ) ); --cw_aoi21 +ucp5_g32_56: cp5_g32_56_b <= not( ex3_g16(5) or ( ex3_t16(5) and ex3_g16(6) ) ); --cw_aoi21 + +ucp5_t32_00: cp5_t32_00_b <= not( ex3_t16(0) ); --cw_invert +ucp5_t32_12: cp5_t32_12_b <= not( ex3_t16(1) and ex3_t16(2) ); --cw_nand2 +ucp5_t32_34: cp5_t32_34_b <= not( ex3_t16(3) and ex3_t16(4) ); --cw_nand2 +ucp5_t32_56: cp5_t32_56_b <= not( ex3_g16(5) or ( ex3_t16(5) and ex3_t16(6) ) ); --cw_aoi21 + + +ucp5_g64_02: cp5_g64_02 <= not( cp5_g32_00_b and (cp5_t32_00_b or cp5_g32_12_b) ); --cw_oai21 +ucp5_g64_36: cp5_g64_36 <= not( cp5_g32_34_b and (cp5_t32_34_b or cp5_g32_56_b) ); --cw_oai21 +ucp5_g64_56: cp5_g64_56 <= not( cp5_g32_56_b ); --cw_invert --EXTRA + +ucp5_t64_02: cp5_t64_02 <= not( cp5_t32_00_b or cp5_t32_12_b ); --cw_nor2 +ucp5_t64_56: cp5_t64_56 <= not( cp5_t32_56_b ); --cw_invert --EXTRA + +ucp5_g128_06: cp5_g128_06_b <= not( cp5_g64_02 or ( cp5_t64_02 and cp5_g64_36 ) ); --cw_aoi21 +ucp5_g128_56: cp5_g128_56_b <= not( cp5_g64_56 ); --cw_invert --EXTRA +ucp5_t128_56: cp5_t128_56_b <= not( cp5_t64_56 ); --cw_invert --EXTRA + + +ucp5_cog: ex3_g128(5) <= not( cp5_g128_56_b);--cw_invert --OUTPUT-- +ucp5_cogx: cp5_g128_56 <= not( cp5_g128_56_b);--cw_invert +ucp5_cogb: ex3_g128_b(5) <= not( cp5_g128_56 );--cw_invert --OUTPUT-- +ucp5_cot: ex3_t128(5) <= not( cp5_t128_56_b);--cw_invert --OUTPUT-- +ucp5_cotx: cp5_t128_56 <= not( cp5_t128_56_b);--cw_invert +ucp5_cotb: ex3_t128_b(5) <= not( cp5_t128_56 );--cw_invert --OUTPUT-- + +ucp5_all1n: cp5_all1_b <= not ex3_inc_all1 ;--cw_invert +ucp5_all1p: cp5_all1_p <= not cp5_all1_b ;--cw_invert +ucp5_co_p0: cp5_co_p0 <= not( cp5_g128_06_b ) ;--cw_invert + +ucp5_espnx: cp5_sel_p0n_x_b <= not( cp5_all1_b and ex3_effsub_npz);--cw_nand2 +ucp5_espny: cp5_sel_p0n_y_b <= not( cp5_g128_06_b and ex3_effsub_npz);--cw_nand2 +ucp5_selp0: cp5_sel_p0_b <= not( cp5_co_p0 and cp5_all1_p and cp5_sub_sticky );--cw_nand3 +ucp5_selp1: cp5_sel_p1_b <= not( cp5_co_p0 and cp5_all1_p and cp5_sub_stickyn );--cw_nand3 + +ucp5_espn: ex3_eac_sel_p0n(4) <= not( cp5_sel_p0n_x_b and cp5_sel_p0n_y_b);--cw_nand2 --OUTPUT-- +ucp5_esp0: ex3_eac_sel_p0(4) <= not( cp5_sel_p0_b and cp5_add_frcp0_b);--cw_nand2 --OUTPUT-- +ucp5_esp1: ex3_eac_sel_p1(4) <= not( cp5_sel_p1_b and cp5_add_frcp1_b);--cw_nand2 --OUTPUT-- + + cp5_sub_sticky <= ex3_effsub_npz and f_alg_ex3_sticky ;--NOT MAPPED + cp5_sub_stickyn <= ex3_effsub_npz and not f_alg_ex3_sticky ;--NOT MAPPED + cp5_add_frcp1_b <= not( ex3_effadd_npz and f_alg_ex3_frc_sel_p1 );--NOT MAPPED + cp5_add_frcp0_b <= not( ex3_effadd_npz and not f_alg_ex3_frc_sel_p1 );--NOT MAPPED + + +--=######################################### +--= BYT_5 +--=######################################### + +ucp6_g32_00: cp6_g32_00_b <= not( ex3_g16(0) ); --cw_invert +ucp6_g32_12: cp6_g32_12_b <= not( ex3_g16(1) or ( ex3_t16(1) and ex3_g16(2) ) ); --cw_aoi21 +ucp6_g32_34: cp6_g32_34_b <= not( ex3_g16(3) or ( ex3_t16(3) and ex3_g16(4) ) ); --cw_aoi21 +ucp6_g32_56: cp6_g32_56_b <= not( ex3_g16(5) or ( ex3_t16(5) and ex3_g16(6) ) ); --cw_aoi21 +ucp6_g32_66: cp6_g32_66_b <= not( ex3_g16(6) ); --cw_invert EXTRA + +ucp6_t32_00: cp6_t32_00_b <= not( ex3_t16(0) ); --cw_invert +ucp6_t32_12: cp6_t32_12_b <= not( ex3_t16(1) and ex3_t16(2) ); --cw_nand2 +ucp6_t32_34: cp6_t32_34_b <= not( ex3_t16(3) and ex3_t16(4) ); --cw_nand2 +ucp6_t32_66: cp6_t32_66_b <= not( ex3_t16(6) ); --cw_invert EXTRA + +ucp6_g64_02: cp6_g64_02 <= not( cp6_g32_00_b and (cp6_t32_00_b or cp6_g32_12_b) ); --cw_oai21 +ucp6_g64_36: cp6_g64_36 <= not( cp6_g32_34_b and (cp6_t32_34_b or cp6_g32_56_b) ); --cw_oai21 + +ucp6_t64_02: cp6_t64_02 <= not( cp6_t32_00_b or cp6_t32_12_b ); --cw_nor2 + +ucp6_g128_06: cp6_g128_06_b <= not( cp6_g64_02 or ( cp6_t64_02 and cp6_g64_36 ) ); --cw_aoi21 + + +ucp6_cog: ex3_g128(6) <= not( cp6_g32_66_b );--cw_invert --OUTPUT-- +ucp6_cogx: cp6_g128_66 <= not( cp6_g32_66_b );--cw_invert +ucp6_cogb: ex3_g128_b(6) <= not( cp6_g128_66 );--cw_invert --OUTPUT-- +ucp6_cot: ex3_t128(6) <= not( cp6_t32_66_b );--cw_invert --OUTPUT-- +ucp6_cotx: cp6_t128_66 <= not( cp6_t32_66_b );--cw_invert +ucp6_cotb: ex3_t128_b(6) <= not( cp6_t128_66 );--cw_invert --OUTPUT-- + + +ucp6_all1n: cp6_all1_b <= not ex3_inc_all1 ;--cw_invert +ucp6_all1p: cp6_all1_p <= not cp6_all1_b ;--cw_invert +ucp6_co_p0: cp6_co_p0 <= not( cp6_g128_06_b ) ;--cw_invert + +ucp6_espnx: cp6_sel_p0n_x_b <= not( cp6_all1_b and ex3_effsub_npz);--cw_nand2 +ucp6_espny: cp6_sel_p0n_y_b <= not( cp6_g128_06_b and ex3_effsub_npz);--cw_nand2 +ucp6_selp0: cp6_sel_p0_b <= not( cp6_co_p0 and cp6_all1_p and cp6_sub_sticky );--cw_nand3 +ucp6_selp1: cp6_sel_p1_b <= not( cp6_co_p0 and cp6_all1_p and cp6_sub_stickyn );--cw_nand3 + +ucp6_espn: ex3_eac_sel_p0n(5) <= not( cp6_sel_p0n_x_b and cp6_sel_p0n_y_b);--cw_nand2 --OUTPUT-- +ucp6_esp0: ex3_eac_sel_p0(5) <= not( cp6_sel_p0_b and cp6_add_frcp0_b);--cw_nand2 --OUTPUT-- +ucp6_esp1: ex3_eac_sel_p1(5) <= not( cp6_sel_p1_b and cp6_add_frcp1_b);--cw_nand2 --OUTPUT-- + + cp6_sub_sticky <= ex3_effsub_npz and f_alg_ex3_sticky ;--NOT MAPPED + cp6_sub_stickyn <= ex3_effsub_npz and not f_alg_ex3_sticky ;--NOT MAPPED + cp6_add_frcp1_b <= not( ex3_effadd_npz and f_alg_ex3_frc_sel_p1 );--NOT MAPPED + cp6_add_frcp0_b <= not( ex3_effadd_npz and not f_alg_ex3_frc_sel_p1 );--NOT MAPPED + + +--=######################################### +--= BYT_6 LSB COPY +--=######################################### + +ucp7_g32_00: cp7_g32_00_b <= not( ex3_g16(0) ) ; --cw_invert +ucp7_g32_12: cp7_g32_12_b <= not( ex3_g16(1) or ( ex3_t16(1) and ex3_g16(2) ) ); --cw_aoi21 +ucp7_g32_34: cp7_g32_34_b <= not( ex3_g16(3) or ( ex3_t16(3) and ex3_g16(4) ) ); --cw_aoi21 +ucp7_g32_56: cp7_g32_56_b <= not( ex3_g16(5) or ( ex3_t16(5) and ex3_g16(6) ) ); --cw_aoi21 + +ucp7_t32_00: cp7_t32_00_b <= not( ex3_t16(0) ); --cw_invert +ucp7_t32_12: cp7_t32_12_b <= not( ex3_t16(1) and ex3_t16(2) ); --cw_nand2 +ucp7_t32_34: cp7_t32_34_b <= not( ex3_t16(3) and ex3_t16(4) ); --cw_nand2 + + +ucp7_g64_02: cp7_g64_02 <= not( cp7_g32_00_b and (cp7_t32_00_b or cp7_g32_12_b) ); --cw_oai21 +ucp7_g64_36: cp7_g64_36 <= not( cp7_g32_34_b and (cp7_t32_34_b or cp7_g32_56_b) ); --cw_oai21 + +ucp7_t64_02: cp7_t64_02 <= not( cp7_t32_00_b or cp7_t32_12_b ); --cw_nor2 + +ucp7_g128_06: cp7_g128_06_b <= not( cp7_g64_02 or ( cp7_t64_02 and cp7_g64_36 ) ); --cw_aoi21 + +ucp7_all1n: cp7_all1_b <= not ex3_inc_all1 ;--cw_invert +ucp7_all1p: cp7_all1_p <= not cp7_all1_b ;--cw_invert +ucp7_co_p0: cp7_co_p0 <= not( cp7_g128_06_b ) ;--cw_invert + +ucp7_espnx: cp7_sel_p0n_x_b <= not( cp7_all1_b and ex3_effsub_npz);--cw_nand2 +ucp7_espny: cp7_sel_p0n_y_b <= not( cp7_g128_06_b and ex3_effsub_npz);--cw_nand2 +ucp7_selp0: cp7_sel_p0_b <= not( cp7_co_p0 and cp7_all1_p and cp7_sub_sticky );--cw_nand3 +ucp7_selp1: cp7_sel_p1_b <= not( cp7_co_p0 and cp7_all1_p and cp7_sub_stickyn );--cw_nand3 + +ucp7_espn: ex3_eac_sel_p0n(6) <= not( cp7_sel_p0n_x_b and cp7_sel_p0n_y_b);--cw_nand2 --OUTPUT-- +ucp7_esp0: ex3_eac_sel_p0(6) <= not( cp7_sel_p0_b and cp7_add_frcp0_b);--cw_nand2 --OUTPUT-- +ucp7_esp1: ex3_eac_sel_p1(6) <= not( cp7_sel_p1_b and cp7_add_frcp1_b);--cw_nand2 --OUTPUT-- + + cp7_sub_sticky <= ex3_effsub_npz and f_alg_ex3_sticky ;--NOT MAPPED + cp7_sub_stickyn <= ex3_effsub_npz and not f_alg_ex3_sticky ;--NOT MAPPED + cp7_add_frcp1_b <= not( ex3_effadd_npz and f_alg_ex3_frc_sel_p1 );--NOT MAPPED + cp7_add_frcp0_b <= not( ex3_effadd_npz and not f_alg_ex3_frc_sel_p1 );--NOT MAPPED + +END; -- ARCH fuq_add_glbc diff --git a/rel/src/vhdl/work/fuq_alg.vhdl b/rel/src/vhdl/work/fuq_alg.vhdl new file mode 100644 index 0000000..d00db73 --- /dev/null +++ b/rel/src/vhdl/work/fuq_alg.vhdl @@ -0,0 +1,1060 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + + +entity fuq_alg is +generic( expand_type : integer := 2 ); -- 0 - ibm tech, 1 - other ); +port( + + vdd :inout power_logic; + gnd :inout power_logic; + clkoff_b :in std_ulogic; -- tiup + act_dis :in std_ulogic; -- ??tidn?? + flush :in std_ulogic; -- ??tidn?? + delay_lclkr :in std_ulogic_vector(1 to 3); -- tidn, + mpw1_b :in std_ulogic_vector(1 to 3); -- tidn, + mpw2_b :in std_ulogic_vector(0 to 0); -- tidn, + sg_1 :in std_ulogic; + thold_1 :in std_ulogic; + fpu_enable :in std_ulogic; --dc_act + nclk :in clk_logic; + + + f_alg_si :in std_ulogic; --perv + f_alg_so :out std_ulogic; --perv + rf1_act :in std_ulogic; --act + ex1_act :in std_ulogic; --act + + f_byp_alg_ex1_b_expo :in std_ulogic_vector(1 to 13); + f_byp_alg_ex1_a_expo :in std_ulogic_vector(1 to 13); + f_byp_alg_ex1_c_expo :in std_ulogic_vector(1 to 13); + f_byp_alg_ex1_b_frac :in std_ulogic_vector(0 to 52); + f_byp_alg_ex1_b_sign :in std_ulogic; + + f_fmt_ex1_prod_zero :in std_ulogic; -- valid and Zero (Madd/Mul) + f_fmt_ex1_b_zero :in std_ulogic; -- valid and zero (could be denorm, so zero out B) + f_fmt_ex1_pass_sel :in std_ulogic; + f_fmt_ex2_pass_frac :in std_ulogic_vector(0 to 52); + + f_dcd_rf1_sp :in std_ulogic; + f_dcd_rf1_from_integer_b :in std_ulogic; -- K, spec, round + f_dcd_rf1_to_integer_b :in std_ulogic; -- K, spec, round + f_dcd_rf1_word_b :in std_ulogic; + f_dcd_rf1_uns_b :in std_ulogic; + + f_pic_ex1_rnd_to_int :in std_ulogic; + f_pic_ex1_frsp_ue1 :in std_ulogic; -- K, spec, round + f_pic_ex1_effsub_raw :in std_ulogic; -- + f_pic_ex1_sh_unf_ig_b :in std_ulogic; -- fcfid + f_pic_ex1_sh_unf_do :in std_ulogic; -- (do not know why want this) + f_pic_ex1_sh_ovf_ig_b :in std_ulogic; -- fcfid + f_pic_ex1_sh_ovf_do :in std_ulogic; -- fsel, fpscr, fmr, + f_pic_ex2_rnd_nr :in std_ulogic; -- + f_pic_ex2_rnd_inf_ok :in std_ulogic; -- pi/pos, ni/neg + + f_alg_ex1_sign_frmw :out std_ulogic; -- sign bit for from_integer_word_signed + f_alg_ex2_byp_nonflip :out std_ulogic; + f_alg_ex2_res :out std_ulogic_vector(0 to 162); --sad3/add + f_alg_ex2_sel_byp :out std_ulogic; -- all eac selects off + f_alg_ex2_effsub_eac_b :out std_ulogic; -- includes cancelations + f_alg_ex2_prod_z :out std_ulogic; + f_alg_ex2_sh_unf :out std_ulogic; -- f_pic + f_alg_ex2_sh_ovf :out std_ulogic; -- f_pic + f_alg_ex3_frc_sel_p1 :out std_ulogic; -- rounding converts + f_alg_ex3_sticky :out std_ulogic; -- part of eac control + f_alg_ex3_int_fr :out std_ulogic; -- f_pic + f_alg_ex3_int_fi :out std_ulogic -- f_pic +); + + +end fuq_alg; -- ENTITY + +architecture fuq_alg of fuq_alg is + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal thold_0_b, thold_0, forcee :std_ulogic; + signal sg_0 :std_ulogic; + signal ex2_act :std_ulogic; + signal spare_unused :std_ulogic_vector(0 to 3); + ---------------------------------------- + signal act_so :std_ulogic_vector(0 to 4);--SCAN + signal act_si :std_ulogic_vector(0 to 4);--SCAN + signal ex1_ctl_so :std_ulogic_vector(0 to 4);--SCAN + signal ex1_ctl_si :std_ulogic_vector(0 to 4);--SCAN + signal ex2_shd_so, ex2_shd_si :std_ulogic_vector(0 to 67);--SCAN + signal ex2_shc_so, ex2_shc_si :std_ulogic_vector(0 to 24);--SCAN + signal ex2_ctl_so :std_ulogic_vector(0 to 14);--SCAN + signal ex2_ctl_si :std_ulogic_vector(0 to 14);--SCAN + signal ex3_ctl_so :std_ulogic_vector(0 to 10);--SCAN + signal ex3_ctl_si :std_ulogic_vector(0 to 10);--SCAN + ---------------------------------------- + signal ex1_from_integer :std_ulogic; + signal ex2_from_integer :std_ulogic; + signal ex1_to_integer :std_ulogic; + signal ex1_sel_special, ex1_sel_special_b, ex2_sel_special_b :std_ulogic; + signal ex1_sh_ovf :std_ulogic; + signal ex1_sh_unf_x , ex2_sh_unf_x :std_ulogic; + signal ex1_sel_byp_nonflip :std_ulogic; + signal ex1_sel_byp_nonflip_lze :std_ulogic; + signal ex1_from_integer_neg :std_ulogic; + signal ex1_integer_op :std_ulogic; + signal ex1_to_integer_neg :std_ulogic; + signal ex1_negate :std_ulogic; + signal ex1_effsub_alg :std_ulogic; + signal ex2_sh_unf :std_ulogic; + signal ex2_sel_byp :std_ulogic; + signal ex2_effsub_alg :std_ulogic; + signal ex2_prd_sel_pos_hi :std_ulogic; + signal ex2_prd_sel_neg_hi :std_ulogic; + signal ex2_prd_sel_pos_lo :std_ulogic; + signal ex2_prd_sel_neg_lo :std_ulogic; + signal ex2_prd_sel_pos_lohi :std_ulogic; + signal ex2_prd_sel_neg_lohi :std_ulogic; + signal ex2_byp_sel_pos :std_ulogic; + signal ex2_byp_sel_neg :std_ulogic; + signal ex2_byp_sel_byp_pos :std_ulogic; + signal ex2_byp_sel_byp_neg :std_ulogic; + signal ex2_b_sign :std_ulogic; + signal ex2_to_integer :std_ulogic; + signal ex1_sh_lvl2 :std_ulogic_vector(0 to 67) ; + signal ex2_sh_lvl2, ex2_sh_lvl2_b :std_ulogic_vector(0 to 67) ; + signal ex2_bsha :std_ulogic_vector(6 to 9) ; + signal ex2_sticky_en16_x :std_ulogic_vector(0 to 4) ; + signal ex2_xthrm_6_ns_b :std_ulogic; + signal ex2_xthrm_7_ns_b :std_ulogic; + signal ex2_xthrm_8_b :std_ulogic; + signal ex2_xthrm_8a9_b :std_ulogic; + signal ex2_xthrm_8o9_b :std_ulogic; + signal ex2_xthrm7o8a9 :std_ulogic; + signal ex2_xthrm7o8 :std_ulogic; + signal ex2_xthrm7o8o9 :std_ulogic; + signal ex2_xthrm7a8a9 :std_ulogic; + signal ex2_xthrm_6_ns :std_ulogic; + signal ex2_ge176_b :std_ulogic; + signal ex2_ge160_b :std_ulogic; + signal ex2_ge144_b :std_ulogic; + signal ex2_ge128_b :std_ulogic; + signal ex2_ge112_b :std_ulogic; + signal ex1_bsha_6, ex1_bsha_7, ex1_bsha_8, ex1_bsha_9 :std_ulogic; + signal ex2_bsha_pos :std_ulogic; + signal ex2_sh_lvl3 :std_ulogic_vector(0 to 162) ; + signal ex2_sticky_or16 :std_ulogic_vector(0 to 4) ; + signal ex1_b_zero :std_ulogic ; + signal ex2_b_zero, ex2_b_zero_b :std_ulogic ; + + signal ex1_dp :std_ulogic; + + signal ex2_byp_nonflip_lze :std_ulogic; +signal ex2_sel_byp_nonflip :std_ulogic; +signal ex2_prod_zero :std_ulogic; +signal ex2_sh_ovf_en, ex2_sh_unf_en, ex2_sh_unf_do :std_ulogic; +signal ex2_sh_ovf :std_ulogic; +signal ex2_integer_op :std_ulogic; +signal ex2_negate :std_ulogic; +signal ex2_unf_bz :std_ulogic; +signal ex2_all1_x :std_ulogic; +signal ex2_ovf_pz :std_ulogic; +signal ex2_all1_y :std_ulogic; + signal ex2_sel_special :std_ulogic; + signal rf1_from_integer , rf1_to_integer , rf1_dp :std_ulogic; + signal rf1_uns, rf1_word, ex1_uns, ex1_word :std_ulogic; + signal ex1_word_from, ex2_word_from :std_ulogic; + signal ex2_rnd_to_int :std_ulogic; + signal ex1_sign_from :std_ulogic; + signal ex1_b_frac :std_ulogic_vector(0 to 52); + signal ex1_b_expo :std_ulogic_vector(1 to 13); + signal ex1_b_sign :std_ulogic; + signal ex1_bsha_neg, ex2_bsha_neg : std_ulogic ; + + + signal ex1_lvl1_shdcd000_b :std_ulogic; + signal ex1_lvl1_shdcd001_b :std_ulogic; + signal ex1_lvl1_shdcd002_b :std_ulogic; + signal ex1_lvl1_shdcd003_b :std_ulogic; + signal ex1_lvl2_shdcd000 :std_ulogic; + signal ex1_lvl2_shdcd004 :std_ulogic; + signal ex1_lvl2_shdcd008 :std_ulogic; + signal ex1_lvl2_shdcd012 :std_ulogic; + signal ex1_lvl3_shdcd000 :std_ulogic; + signal ex1_lvl3_shdcd016 :std_ulogic; + signal ex1_lvl3_shdcd032 :std_ulogic; + signal ex1_lvl3_shdcd048 :std_ulogic; + signal ex1_lvl3_shdcd064 :std_ulogic; + signal ex1_lvl3_shdcd080 :std_ulogic; + signal ex1_lvl3_shdcd096 :std_ulogic; + signal ex1_lvl3_shdcd112 :std_ulogic; + signal ex1_lvl3_shdcd128 :std_ulogic; + signal ex1_lvl3_shdcd144 :std_ulogic; + signal ex1_lvl3_shdcd160 :std_ulogic; + signal ex1_lvl3_shdcd176 :std_ulogic; + signal ex1_lvl3_shdcd192 :std_ulogic;-- -64 + signal ex1_lvl3_shdcd208 :std_ulogic;-- -48 + signal ex1_lvl3_shdcd224 :std_ulogic;-- -32 + signal ex1_lvl3_shdcd240 :std_ulogic;-- -16 + + signal ex2_lvl3_shdcd000 :std_ulogic; + signal ex2_lvl3_shdcd016 :std_ulogic; + signal ex2_lvl3_shdcd032 :std_ulogic; + signal ex2_lvl3_shdcd048 :std_ulogic; + signal ex2_lvl3_shdcd064 :std_ulogic; + signal ex2_lvl3_shdcd080 :std_ulogic; + signal ex2_lvl3_shdcd096 :std_ulogic; + signal ex2_lvl3_shdcd112 :std_ulogic; + signal ex2_lvl3_shdcd128 :std_ulogic; + signal ex2_lvl3_shdcd144 :std_ulogic; + signal ex2_lvl3_shdcd160 :std_ulogic; + signal ex2_lvl3_shdcd176 :std_ulogic; + signal ex2_lvl3_shdcd192 :std_ulogic; + signal ex2_lvl3_shdcd208 :std_ulogic; + signal ex2_lvl3_shdcd224 :std_ulogic; + signal ex2_lvl3_shdcd240 :std_ulogic; + + signal ex3_int_fr_nr1_b, ex3_int_fr_nr2_b, ex3_int_fr_ok_b :std_ulogic; + signal ex3_int_fr :std_ulogic; + signal ex3_sel_p1_0_b, ex3_sel_p1_1_b :std_ulogic; + signal ex3_sticky_math :std_ulogic; + signal ex3_sticky_toint :std_ulogic; + signal ex3_sticky_toint_nr :std_ulogic; + signal ex3_sticky_toint_ok :std_ulogic; + signal ex3_frmneg_o_toneg :std_ulogic; + signal ex3_frmneg_o_topos :std_ulogic; + signal ex3_lsb_toint_nr :std_ulogic; + signal ex3_g_math :std_ulogic; + signal ex3_g_toint :std_ulogic; + signal ex3_g_toint_nr :std_ulogic; + signal ex3_g_toint_ok :std_ulogic; + signal ex2_frmneg :std_ulogic; + signal ex2_toneg :std_ulogic; + signal ex2_topos :std_ulogic; + signal ex2_frmneg_o_toneg :std_ulogic; + signal ex2_frmneg_o_topos :std_ulogic; + signal ex2_toint_gate_x :std_ulogic; + signal ex2_toint_gate_g :std_ulogic; + signal ex2_toint_gt_nr_x :std_ulogic; + signal ex2_toint_gt_nr_g :std_ulogic; + signal ex2_toint_gt_ok_x :std_ulogic; + signal ex2_toint_gt_ok_g :std_ulogic; + signal ex2_math_gate_x :std_ulogic; + signal ex2_math_gate_g :std_ulogic; + signal ex2_sticky_eac_x :std_ulogic; + signal ex2_sticky_math :std_ulogic; + signal ex2_sticky_toint :std_ulogic; + signal ex2_sticky_toint_nr :std_ulogic; + signal ex2_sticky_toint_ok :std_ulogic; + signal ex2_lsb_toint_nr :std_ulogic; + signal ex2_g_math :std_ulogic; + signal ex2_g_toint :std_ulogic; + signal ex2_g_toint_nr :std_ulogic; + signal ex2_g_toint_ok :std_ulogic; + signal ex2_sh16_162, ex2_sh16_163 :std_ulogic; + signal alg_ex2_d1clk, alg_ex2_d2clk :std_ulogic; + + signal alg_ex2_lclk :clk_logic; + + signal ex2_bsha_b :std_ulogic_vector(6 to 9); + signal ex2_bsha_neg_b :std_ulogic; + signal ex2_sh_ovf_b :std_ulogic; + signal ex2_sh_unf_x_b :std_ulogic; + signal ex2_lvl3_shdcd000_b :std_ulogic; + signal ex2_lvl3_shdcd016_b :std_ulogic; + signal ex2_lvl3_shdcd032_b :std_ulogic; + signal ex2_lvl3_shdcd048_b :std_ulogic; + signal ex2_lvl3_shdcd064_b :std_ulogic; + signal ex2_lvl3_shdcd080_b :std_ulogic; + signal ex2_lvl3_shdcd096_b :std_ulogic; + signal ex2_lvl3_shdcd112_b :std_ulogic; + signal ex2_lvl3_shdcd128_b :std_ulogic; + signal ex2_lvl3_shdcd144_b :std_ulogic; + signal ex2_lvl3_shdcd160_b :std_ulogic; + signal ex2_lvl3_shdcd176_b :std_ulogic; + signal ex2_lvl3_shdcd192_b :std_ulogic; + signal ex2_lvl3_shdcd208_b :std_ulogic; + signal ex2_lvl3_shdcd224_b :std_ulogic; + signal ex2_lvl3_shdcd240_b :std_ulogic; + signal ex2_b_zero_l2_b :std_ulogic; + signal ex2_prod_zero_b :std_ulogic; + signal ex2_byp_nonflip_lze_b :std_ulogic; + signal ex2_sel_byp_nonflip_b :std_ulogic; + signal ex2_sh_unf_do_b :std_ulogic; + signal ex2_sh_unf_en_b :std_ulogic; + signal ex2_sh_ovf_en_b :std_ulogic; + signal ex2_effsub_alg_b :std_ulogic; + signal ex2_negate_b :std_ulogic; + signal ex2_b_sign_b :std_ulogic; + signal ex2_to_integer_b :std_ulogic; + signal ex2_from_integer_b :std_ulogic; + signal ex2_rnd_to_int_b :std_ulogic; + signal ex2_integer_op_b :std_ulogic; + signal ex2_word_from_b :std_ulogic; + + signal unused :std_ulogic; + +--==############################################################## +--# map block attributes +--==############################################################## + +begin + + unused <= ex1_b_expo(1) or ex1_b_expo(2) or + ex1_dp or --latch output + ex2_lvl3_shdcd176 ;-- latch output + + ex1_b_frac(0 to 52) <= f_byp_alg_ex1_b_frac(0 to 52); --RENAME + ex1_b_sign <= f_byp_alg_ex1_b_sign ; --RENAME + ex1_b_expo(1 to 13) <= f_byp_alg_ex1_b_expo(1 to 13); --RENAME + +--==############################################################## +--# pervasive +--==############################################################## + + thold_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => thold_1, -- ?? need an lcb_or after this + q(0) => thold_0 ); + + sg_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => sg_1 , + q(0) => sg_0 ); + + + lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map ( + clkoff_b => clkoff_b, + thold => thold_0, + sg => sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => thold_0_b ); + + + +--==############################################################## +--# act +--==############################################################## + + + act_lat: tri_rlmreg_p generic map (width=> 5, expand_type => expand_type, needs_sreset => 0) port map ( + vd => vdd, + gd => gnd, + forcee => forcee,--i-- tidn, + --d_mode => d_mode ,--i-- tiup, + delay_lclkr => delay_lclkr(2) ,--i-- tidn, + mpw1_b => mpw1_b(2) ,--i-- tidn, + mpw2_b => mpw2_b(0) ,--i-- tidn, + nclk => nclk, + act => fpu_enable, + thold_b => thold_0_b, + sg => sg_0, + scout => act_so , + scin => act_si , + ------------------- + din(0) => spare_unused(0), + din(1) => spare_unused(1), + din(2) => ex1_act, + din(3) => spare_unused(2), + din(4) => spare_unused(3), + ------------------- + dout(0) => spare_unused(0), + dout(1) => spare_unused(1), + dout(2) => ex2_act, + dout(3) => spare_unused(2) , + dout(4) => spare_unused(3) ); + + + alg_ex2_lcb : tri_lcbnd generic map (expand_type => expand_type) port map( + delay_lclkr => delay_lclkr(2) ,-- tidn ,--in + mpw1_b => mpw1_b(2) ,-- tidn ,--in + mpw2_b => mpw2_b(0) ,-- tidn ,--in + forcee => forcee,-- tidn ,--in + nclk => nclk ,--in + vd => vdd ,--inout + gd => gnd ,--inout + act => ex1_act ,--in + sg => sg_0 ,--in + thold_b => thold_0_b ,--in + d1clk => alg_ex2_d1clk ,--out + d2clk => alg_ex2_d2clk ,--out + lclk => alg_ex2_lclk );--out + + + + +--==############################################################## +--# rf1 logic +--==############################################################## + + --#------------------------------------------------------------- + --# shift amount calculation :start with exponent difference + --#------------------------------------------------------------- + + + +--==############################################################## +--# ex1 latches (from rf1 logic) +--==############################################################## + + + + rf1_from_integer <= not f_dcd_rf1_from_integer_b ; + rf1_to_integer <= not f_dcd_rf1_to_integer_b ; + rf1_dp <= not f_dcd_rf1_sp ; + rf1_word <= not f_dcd_rf1_word_b ; + rf1_uns <= not f_dcd_rf1_uns_b ; + + + ex1_ctl_lat: tri_rlmreg_p generic map (width=> 5, expand_type => expand_type, needs_sreset => 0) port map ( + forcee => forcee,--tidn, + --d_mode => d_mode ,--tiup, + delay_lclkr => delay_lclkr(1) ,--tidn, + mpw1_b => mpw1_b(1) ,--tidn, + mpw2_b => mpw2_b(0) ,--tidn, + vd => vdd , + gd => gnd , + nclk => nclk , + thold_b => thold_0_b , + sg => sg_0 , + act => rf1_act , + scout => ex1_ctl_so , + scin => ex1_ctl_si , + ----------------- + din(0) => rf1_from_integer , + din(1) => rf1_to_integer , + din(2) => rf1_dp , + din(3) => rf1_word , + din(4) => rf1_uns , + ----------------- + dout(0) => ex1_from_integer , + dout(1) => ex1_to_integer , + dout(2) => ex1_dp , + dout(3) => ex1_word , + dout(4) => ex1_uns ); + + + +--==############################################################## +--# ex1 logic +--==############################################################## + + sha: entity work.fuq_alg_add(fuq_alg_add) generic map (expand_type => expand_type) port map( + vdd => vdd, + gnd => gnd, + f_byp_alg_ex1_b_expo(1 to 13) => f_byp_alg_ex1_b_expo ,--i-- + f_byp_alg_ex1_a_expo(1 to 13) => f_byp_alg_ex1_a_expo ,--i-- + f_byp_alg_ex1_c_expo(1 to 13) => f_byp_alg_ex1_c_expo ,--i-- + -- ex1_sel_special => ex1_sel_special ,--i-- + ex1_sel_special_b => ex1_sel_special_b ,--i-- + ex1_bsha_6_o => ex1_bsha_6 ,--o-- + ex1_bsha_7_o => ex1_bsha_7 ,--o-- + ex1_bsha_8_o => ex1_bsha_8 ,--o-- + ex1_bsha_9_o => ex1_bsha_9 ,--o-- + ex1_bsha_neg_o => ex1_bsha_neg ,--o-- + ex1_sh_ovf => ex1_sh_ovf ,--o-- + ex1_sh_unf_x => ex1_sh_unf_x ,--o-- + ex1_lvl1_shdcd000_b => ex1_lvl1_shdcd000_b ,--o-- + ex1_lvl1_shdcd001_b => ex1_lvl1_shdcd001_b ,--o-- + ex1_lvl1_shdcd002_b => ex1_lvl1_shdcd002_b ,--o-- + ex1_lvl1_shdcd003_b => ex1_lvl1_shdcd003_b ,--o-- + ex1_lvl2_shdcd000 => ex1_lvl2_shdcd000 ,--o-- + ex1_lvl2_shdcd004 => ex1_lvl2_shdcd004 ,--o-- + ex1_lvl2_shdcd008 => ex1_lvl2_shdcd008 ,--o-- + ex1_lvl2_shdcd012 => ex1_lvl2_shdcd012 ,--o-- + ex1_lvl3_shdcd000 => ex1_lvl3_shdcd000 ,--o-- + ex1_lvl3_shdcd016 => ex1_lvl3_shdcd016 ,--o-- + ex1_lvl3_shdcd032 => ex1_lvl3_shdcd032 ,--o-- + ex1_lvl3_shdcd048 => ex1_lvl3_shdcd048 ,--o-- + ex1_lvl3_shdcd064 => ex1_lvl3_shdcd064 ,--o-- + ex1_lvl3_shdcd080 => ex1_lvl3_shdcd080 ,--o-- + ex1_lvl3_shdcd096 => ex1_lvl3_shdcd096 ,--o-- + ex1_lvl3_shdcd112 => ex1_lvl3_shdcd112 ,--o-- + ex1_lvl3_shdcd128 => ex1_lvl3_shdcd128 ,--o-- + ex1_lvl3_shdcd144 => ex1_lvl3_shdcd144 ,--o-- + ex1_lvl3_shdcd160 => ex1_lvl3_shdcd160 ,--o-- + ex1_lvl3_shdcd176 => ex1_lvl3_shdcd176 ,--o-- + ex1_lvl3_shdcd192 => ex1_lvl3_shdcd192 ,--o-- + ex1_lvl3_shdcd208 => ex1_lvl3_shdcd208 ,--o-- + ex1_lvl3_shdcd224 => ex1_lvl3_shdcd224 ,--o-- + ex1_lvl3_shdcd240 => ex1_lvl3_shdcd240 );--o-- + + ex1_sel_special <= ex1_from_integer ; + ex1_sel_special_b <= not ex1_from_integer ; + + + --#------------------------------------------------- + --# determine bypass selects, operand flip + --#------------------------------------------------- + +--//---------------------------------- +--// ex1 +--//---------------------------------- + + ex1_sel_byp_nonflip_lze <= + ( f_fmt_ex1_pass_sel ) or -- nan pass + ( f_pic_ex1_sh_ovf_do ) ; -- fsel, fpscr, fmr, + + ex1_sel_byp_nonflip <= + ( f_pic_ex1_frsp_ue1 ) or -- <<<< move all this stuff to ex2 + ( f_fmt_ex1_pass_sel ) or -- nan pass + ( f_pic_ex1_sh_ovf_do ) ; -- fsel, fpscr, fmr, + + ex1_integer_op <= ex1_from_integer or (ex1_to_integer and not f_pic_ex1_rnd_to_int); + + -- the negate for from_integer should only catch the last 64 bits (because it is not sign extended) + + f_alg_ex1_sign_frmw <= ex1_b_frac(21) ; -- output (for sign logic) + + ex1_sign_from <= + (ex1_from_integer and ex1_word and ex1_b_frac(21) ) or -- 32 from left 52 - 31 = 21 + (ex1_from_integer and not ex1_word and ex1_b_sign ); + + ex1_from_integer_neg <= ex1_from_integer and ex1_sign_from and not ex1_uns; + + ex1_word_from <= ex1_word and ex1_from_integer ; + + ex1_to_integer_neg <= ex1_to_integer and ex1_b_sign and not f_pic_ex1_rnd_to_int; + + ex1_negate <= f_pic_ex1_effsub_raw or -- subtract op + ex1_from_integer_neg or + ex1_to_integer_neg ; + + ex1_effsub_alg <= f_pic_ex1_effsub_raw and not f_fmt_ex1_pass_sel; + + ex1_b_zero <= f_fmt_ex1_b_zero; + + + + + -- for sh_unf/b_zero effadd: alg_res = 00...00 (turn off all selects) + -- for sh_unf/b_zero effsub: alg_res = 11...11 (turn on pos/neg selects) + -- + -- 0:52 53:54 55:98 99:163 + -- to_int 0 0 0 ssssss + -- from_int 0 0 0 ssssss + -- bypass{nan,fmr} d 0 ? ?????? + -- sh_ov + -- sh_unf + -- effadd + -- effsub + + --#--------------------------------------------------------------- + --# first 2 levels of shifting (1) 0/1/2/3 (2) 0/4/8/12 + --#--------------------------------------------------------------- + + sh4: entity work.fuq_alg_sh4(fuq_alg_sh4) generic map (expand_type => expand_type) port map( + ex1_lvl1_shdcd000_b => ex1_lvl1_shdcd000_b ,--i-- + ex1_lvl1_shdcd001_b => ex1_lvl1_shdcd001_b ,--i-- + ex1_lvl1_shdcd002_b => ex1_lvl1_shdcd002_b ,--i-- + ex1_lvl1_shdcd003_b => ex1_lvl1_shdcd003_b ,--i-- + ex1_lvl2_shdcd000 => ex1_lvl2_shdcd000 ,--i-- + ex1_lvl2_shdcd004 => ex1_lvl2_shdcd004 ,--i-- + ex1_lvl2_shdcd008 => ex1_lvl2_shdcd008 ,--i-- + ex1_lvl2_shdcd012 => ex1_lvl2_shdcd012 ,--i-- + ex1_sel_special => ex1_sel_special ,--i-- + ex1_b_sign => ex1_b_sign ,--i-- + ex1_b_expo(3 to 13) => ex1_b_expo(3 to 13) ,--i-- + ex1_b_frac(0 to 52) => ex1_b_frac(0 to 52) ,--i-- + ex1_sh_lvl2(0 to 67) => ex1_sh_lvl2(0 to 67) );--o-- + +--==############################################################## +--# ex2 latches (from ex1 logic) +--==############################################################## + + ex2_shd_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 68, btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd ,--inout + gd => gnd ,--inout + LCLK => alg_ex2_lclk ,-- lclk.clk + D1CLK => alg_ex2_d1clk , + D2CLK => alg_ex2_d2clk , + SCANIN => ex2_shd_si , + SCANOUT => ex2_shd_so , + D => ex1_sh_lvl2 (0 to 67) , + QB => ex2_sh_lvl2_b(0 to 67) ); + + ex2_sh_lvl2(0 to 67) <= not ex2_sh_lvl2_b(0 to 67) ; + + + ex2_shc_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 25, btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd ,--inout + gd => gnd ,--inout + LCLK => alg_ex2_lclk ,-- lclk.clk + D1CLK => alg_ex2_d1clk , + D2CLK => alg_ex2_d2clk , + SCANIN => ex2_shc_si , + SCANOUT => ex2_shc_so , + ------------------- + D(0) => ex1_bsha_neg , + D(1) => ex1_sh_ovf , + D(2) => ex1_sh_unf_x , + D(3) => ex1_sel_special , + D(4) => ex1_sel_special_b, + D(5) => ex1_bsha_6 , + D(6) => ex1_bsha_7 , + D(7) => ex1_bsha_8 , + D(8) => ex1_bsha_9 , + D(9) => ex1_lvl3_shdcd000 , + D(10) => ex1_lvl3_shdcd016 , + D(11) => ex1_lvl3_shdcd032 , + D(12) => ex1_lvl3_shdcd048 , + D(13) => ex1_lvl3_shdcd064 , + D(14) => ex1_lvl3_shdcd080 , + D(15) => ex1_lvl3_shdcd096 , + D(16) => ex1_lvl3_shdcd112 , + D(17) => ex1_lvl3_shdcd128 , + D(18) => ex1_lvl3_shdcd144 , + D(19) => ex1_lvl3_shdcd160 , + D(20) => ex1_lvl3_shdcd176 , + D(21) => ex1_lvl3_shdcd192 , + D(22) => ex1_lvl3_shdcd208 , + D(23) => ex1_lvl3_shdcd224 , + D(24) => ex1_lvl3_shdcd240 , + ---------------------- + QB(0) => ex2_bsha_neg_b , + QB(1) => ex2_sh_ovf_b , + QB(2) => ex2_sh_unf_x_b , + QB(3) => ex2_sel_special_b , + QB(4) => ex2_sel_special , + QB(5) => ex2_bsha_b(6) , + QB(6) => ex2_bsha_b(7) , + QB(7) => ex2_bsha_b(8) , + QB(8) => ex2_bsha_b(9) , + QB(9) => ex2_lvl3_shdcd000_b , + QB(10) => ex2_lvl3_shdcd016_b , + QB(11) => ex2_lvl3_shdcd032_b , + QB(12) => ex2_lvl3_shdcd048_b , + QB(13) => ex2_lvl3_shdcd064_b , + QB(14) => ex2_lvl3_shdcd080_b , + QB(15) => ex2_lvl3_shdcd096_b , + QB(16) => ex2_lvl3_shdcd112_b , + QB(17) => ex2_lvl3_shdcd128_b , + QB(18) => ex2_lvl3_shdcd144_b , + QB(19) => ex2_lvl3_shdcd160_b , + QB(20) => ex2_lvl3_shdcd176_b , + QB(21) => ex2_lvl3_shdcd192_b , + QB(22) => ex2_lvl3_shdcd208_b , + QB(23) => ex2_lvl3_shdcd224_b , + QB(24) => ex2_lvl3_shdcd240_b ); + + + ex2_bsha_neg <= not ex2_bsha_neg_b ; + ex2_sh_ovf <= not ex2_sh_ovf_b ; + ex2_sh_unf_x <= not ex2_sh_unf_x_b ; + ex2_bsha(6) <= not ex2_bsha_b(6) ; + ex2_bsha(7) <= not ex2_bsha_b(7) ; + ex2_bsha(8) <= not ex2_bsha_b(8) ; + ex2_bsha(9) <= not ex2_bsha_b(9) ; + ex2_lvl3_shdcd000 <= not ex2_lvl3_shdcd000_b ; + ex2_lvl3_shdcd016 <= not ex2_lvl3_shdcd016_b ; + ex2_lvl3_shdcd032 <= not ex2_lvl3_shdcd032_b ; + ex2_lvl3_shdcd048 <= not ex2_lvl3_shdcd048_b ; + ex2_lvl3_shdcd064 <= not ex2_lvl3_shdcd064_b ; + ex2_lvl3_shdcd080 <= not ex2_lvl3_shdcd080_b ; + ex2_lvl3_shdcd096 <= not ex2_lvl3_shdcd096_b ; + ex2_lvl3_shdcd112 <= not ex2_lvl3_shdcd112_b ; + ex2_lvl3_shdcd128 <= not ex2_lvl3_shdcd128_b ; + ex2_lvl3_shdcd144 <= not ex2_lvl3_shdcd144_b ; + ex2_lvl3_shdcd160 <= not ex2_lvl3_shdcd160_b ; + ex2_lvl3_shdcd176 <= not ex2_lvl3_shdcd176_b ; + ex2_lvl3_shdcd192 <= not ex2_lvl3_shdcd192_b ; + ex2_lvl3_shdcd208 <= not ex2_lvl3_shdcd208_b ; + ex2_lvl3_shdcd224 <= not ex2_lvl3_shdcd224_b ; + ex2_lvl3_shdcd240 <= not ex2_lvl3_shdcd240_b ; + + + + + ex2_ctl_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 15, btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd ,--inout + gd => gnd ,--inout + LCLK => alg_ex2_lclk ,-- lclk.clk + D1CLK => alg_ex2_d1clk , + D2CLK => alg_ex2_d2clk , + SCANIN => ex2_ctl_si , + SCANOUT => ex2_ctl_so , + ------------------- + D(0) => ex1_b_zero , + D(1) => f_fmt_ex1_prod_zero , + D(2) => ex1_sel_byp_nonflip_lze , + D(3) => ex1_sel_byp_nonflip , + D(4) => f_pic_ex1_sh_unf_do , + D(5) => f_pic_ex1_sh_unf_ig_b , + D(6) => f_pic_ex1_sh_ovf_ig_b , + D(7) => ex1_effsub_alg , + D(8) => ex1_negate , + D(9) => ex1_b_sign , + D(10) => ex1_to_integer , + D(11) => ex1_from_integer , + D(12) => f_pic_ex1_rnd_to_int , + D(13) => ex1_integer_op , + D(14) => ex1_word_from , + ------------------- + QB(0) => ex2_b_zero_l2_b , + QB(1) => ex2_prod_zero_b , + QB(2) => ex2_byp_nonflip_lze_b , + QB(3) => ex2_sel_byp_nonflip_b , + QB(4) => ex2_sh_unf_do_b , + QB(5) => ex2_sh_unf_en_b , + QB(6) => ex2_sh_ovf_en_b , + QB(7) => ex2_effsub_alg_b , + QB(8) => ex2_negate_b , + QB(9) => ex2_b_sign_b , + QB(10) => ex2_to_integer_b , + QB(11) => ex2_from_integer_b , + QB(12) => ex2_rnd_to_int_b , + QB(13) => ex2_integer_op_b , + QB(14) => ex2_word_from_b ); + + + ex2_b_zero <= not ex2_b_zero_l2_b ; + ex2_prod_zero <= not ex2_prod_zero_b ; + ex2_byp_nonflip_lze <= not ex2_byp_nonflip_lze_b ; + ex2_sel_byp_nonflip <= not ex2_sel_byp_nonflip_b ; + ex2_sh_unf_do <= not ex2_sh_unf_do_b ; + ex2_sh_unf_en <= not ex2_sh_unf_en_b ; + ex2_sh_ovf_en <= not ex2_sh_ovf_en_b ; + ex2_effsub_alg <= not ex2_effsub_alg_b ; + ex2_negate <= not ex2_negate_b ; + ex2_b_sign <= not ex2_b_sign_b ; + ex2_to_integer <= not ex2_to_integer_b ; + ex2_from_integer <= not ex2_from_integer_b ; + ex2_rnd_to_int <= not ex2_rnd_to_int_b ; + ex2_integer_op <= not ex2_integer_op_b ; + ex2_word_from <= not ex2_word_from_b ; + + + + + --$$ sticky enable for 16 bit groups ------------------------ + --$$ + --$$ ex1_sticky_en16_x(0) <= + --$$ (ex1_lvl3_shdcd176 ) or -- == 176 + --$$ (ex1_bsha( 6) and ex1_bsha( 7) ) or -- >= 176 + --$$ (ex1_bsha( 6) and ex1_bsha( 8) and ex1_bsha( 9) ) ; -- >= 176 + --$$ ex1_sticky_en16_x(1) <= ex1_sticky_en16_x(0) or ex1_lvl3_shdcd160_x ; + --$$ ex1_sticky_en16_x(2) <= ex1_sticky_en16_x(1) or ex1_lvl3_shdcd144_x ; + --$$ ex1_sticky_en16_x(3) <= ex1_sticky_en16_x(2) or ex1_lvl3_shdcd128_x ; + --$$ ex1_sticky_en16_x(4) <= ex1_sticky_en16_x(3) or ex1_lvl3_shdcd112_x ; + + -------------------------------- + -- Sticky Bit Thermometer + -------------------------------- + -- bhsa(6789) + -- 176 1011 GE_176: 6 * (7 | (8*9) ) + -- 160 1010 GE_160: 6 * (7 | (8) ) + -- 144 1001 GE_144 6 * (7 | (8|9) ) + -- 128 1000 GE_128: 6 + -- 112 0111 GE_112: 6 | (7 * (8*9) ) + + ex2_xthrm_6_ns_b <= not( ex2_bsha(6) and ex2_sel_special_b ); + ex2_xthrm_7_ns_b <= not( ex2_bsha(7) and ex2_sel_special_b ); + ex2_xthrm_8_b <= not( ex2_bsha(8) ); + ex2_xthrm_8a9_b <= not( ex2_bsha(8) and ex2_bsha(9) ); + ex2_xthrm_8o9_b <= not( ex2_bsha(8) or ex2_bsha(9) ); + + ex2_xthrm7o8a9 <= not( ex2_xthrm_7_ns_b and ex2_xthrm_8a9_b ); + ex2_xthrm7o8 <= not( ex2_xthrm_7_ns_b and ex2_xthrm_8_b ); + ex2_xthrm7o8o9 <= not( ex2_xthrm_7_ns_b and ex2_xthrm_8o9_b ); + ex2_xthrm7a8a9 <= not( ex2_xthrm_7_ns_b or ex2_xthrm_8a9_b ); + ex2_xthrm_6_ns <= not( ex2_xthrm_6_ns_b ); + + ex2_ge176_b <= not( ex2_xthrm_6_ns and ex2_xthrm7o8a9 ); + ex2_ge160_b <= not( ex2_xthrm_6_ns and ex2_xthrm7o8 ); + ex2_ge144_b <= not( ex2_xthrm_6_ns and ex2_xthrm7o8o9 ); + ex2_ge128_b <= not( ex2_xthrm_6_ns ); + ex2_ge112_b <= not( ex2_xthrm_6_ns or ex2_xthrm7a8a9 ); + + ex2_sticky_en16_x(0) <= not ex2_ge176_b ; + ex2_sticky_en16_x(1) <= not ex2_ge160_b ; + ex2_sticky_en16_x(2) <= not ex2_ge144_b ; + ex2_sticky_en16_x(3) <= not ex2_ge128_b ; + ex2_sticky_en16_x(4) <= not ex2_ge112_b ; + + + + + + + ex2_b_zero_b <= not ex2_b_zero ; + + + f_alg_ex2_byp_nonflip <= ex2_byp_nonflip_lze ; + f_alg_ex2_sel_byp <= ex2_sel_byp ;--output-- all eac selects off + f_alg_ex2_effsub_eac_b <= not ex2_effsub_alg ;--output-- includes cancelations + f_alg_ex2_prod_z <= ex2_prod_zero ;--output + f_alg_ex2_sh_unf <= ex2_sh_unf ;--output--f_pic-- + f_alg_ex2_sh_ovf <= ex2_ovf_pz ;--output--f_pic-- + + + + +--==############################################################## +--# ex2 logic +--==############################################################## + + --#------------------------------------------------- + --# start sticky (passed 163 ... passed 162 for math, but need guard for fcti rounding) + --#------------------------------------------------- + + or16: entity work.fuq_alg_or16(fuq_alg_or16) generic map (expand_type => expand_type) port map ( + ex2_sh_lvl2(0 to 67) => ex2_sh_lvl2(0 to 67) ,--i-- + ex2_sticky_or16(0 to 4) => ex2_sticky_or16(0 to 4) );--o-- + + --#------------------------------------------------- + --# finish shifting + --#------------------------------------------------- + -- this looks more like a 53:1 mux than a shifter to shrink it, and lower load on selects + -- real implementation should be nand/nand/nor ... ?? integrate nor into latch ?? + + sh16: entity work.fuq_alg_sh16(fuq_alg_sh16) generic map (expand_type => expand_type) port map ( + ex2_lvl3_shdcd000 => ex2_lvl3_shdcd000 ,--i-- + ex2_lvl3_shdcd016 => ex2_lvl3_shdcd016 ,--i-- + ex2_lvl3_shdcd032 => ex2_lvl3_shdcd032 ,--i-- + ex2_lvl3_shdcd048 => ex2_lvl3_shdcd048 ,--i-- + ex2_lvl3_shdcd064 => ex2_lvl3_shdcd064 ,--i-- + ex2_lvl3_shdcd080 => ex2_lvl3_shdcd080 ,--i-- + ex2_lvl3_shdcd096 => ex2_lvl3_shdcd096 ,--i-- + ex2_lvl3_shdcd112 => ex2_lvl3_shdcd112 ,--i-- + ex2_lvl3_shdcd128 => ex2_lvl3_shdcd128 ,--i-- + ex2_lvl3_shdcd144 => ex2_lvl3_shdcd144 ,--i-- + ex2_lvl3_shdcd160 => ex2_lvl3_shdcd160 ,--i-- + ex2_lvl3_shdcd192 => ex2_lvl3_shdcd192 ,--i-- + ex2_lvl3_shdcd208 => ex2_lvl3_shdcd208 ,--i-- + ex2_lvl3_shdcd224 => ex2_lvl3_shdcd224 ,--i-- + ex2_lvl3_shdcd240 => ex2_lvl3_shdcd240 ,--i-- + ex2_sel_special => ex2_sel_special ,--i-- + ex2_sh_lvl2(0 to 67) => ex2_sh_lvl2(0 to 67) ,--i-- [0:63] is also data for from integer + ex2_sh16_162 => ex2_sh16_162 ,--o-- + ex2_sh16_163 => ex2_sh16_163 ,--o-- + ex2_sh_lvl3(0 to 162) => ex2_sh_lvl3(0 to 162) );--o-- + + + --==--------------------------------------------- + --== finish bypass controls + --==---------------------------------------------- + + ex2_ovf_pz <= ex2_prod_zero or (ex2_sh_ovf and ex2_sh_ovf_en and not ex2_b_zero); + ex2_sel_byp <= ex2_sel_byp_nonflip or ex2_ovf_pz ; + ex2_all1_y <= ex2_negate and ex2_ovf_pz ; + ex2_all1_x <= ex2_negate and ex2_unf_bz ; + ex2_sh_unf <= ex2_sh_unf_do or ( ex2_sh_unf_en and ex2_sh_unf_x and not ex2_prod_zero); + ex2_unf_bz <= ex2_b_zero or ex2_sh_unf ; + + + + + ex2_byp_sel_byp_pos <= + ( ex2_sel_byp_nonflip ) or + ( ex2_ovf_pz and not ex2_integer_op and not ex2_negate and not ex2_unf_bz ) or + ( ex2_ovf_pz and not ex2_integer_op and ex2_all1_x ); + + ex2_byp_sel_byp_neg <= not ex2_sel_byp_nonflip and + ex2_ovf_pz and not ex2_integer_op and ex2_negate ; + + ex2_byp_sel_pos <= + ( not ex2_sel_byp and not ex2_integer_op and not ex2_negate and not ex2_unf_bz ) or + ( not ex2_sel_byp and not ex2_integer_op and ex2_all1_x ); + ex2_byp_sel_neg <= + ( not ex2_sel_byp and not ex2_integer_op and ex2_negate ); + + + ex2_prd_sel_pos_hi <= ex2_prd_sel_pos_lo and not ex2_integer_op ; + ex2_prd_sel_neg_hi <= ex2_prd_sel_neg_lo and not ex2_integer_op ; + + ex2_prd_sel_pos_lohi <= ex2_prd_sel_pos_lo and not ex2_word_from ; + ex2_prd_sel_neg_lohi <= ex2_prd_sel_neg_lo and not ex2_word_from ; + + + ex2_prd_sel_pos_lo <= + ( not ex2_sel_byp_nonflip and not ex2_ovf_pz and not ex2_unf_bz and not ex2_negate ) or + ( not ex2_sel_byp_nonflip and ex2_all1_x ) or + ( not ex2_sel_byp_nonflip and ex2_all1_y ) ; + ex2_prd_sel_neg_lo <= + ( not ex2_sel_byp_nonflip and ex2_negate ) ; + + + --#------------------------------------------------- + --# bypass mux & operand flip + --#------------------------------------------------- + --# integer operation positions + --# 32 32 + --# 99:130 131:162 + + bymx: entity work.fuq_alg_bypmux(fuq_alg_bypmux) generic map (expand_type => expand_type) port map ( + ex2_byp_sel_byp_neg => ex2_byp_sel_byp_neg ,--i-- + ex2_byp_sel_byp_pos => ex2_byp_sel_byp_pos ,--i-- + ex2_byp_sel_neg => ex2_byp_sel_neg ,--i-- + ex2_byp_sel_pos => ex2_byp_sel_pos ,--i-- + ex2_prd_sel_neg_hi => ex2_prd_sel_neg_hi ,--i-- + ex2_prd_sel_neg_lo => ex2_prd_sel_neg_lo ,--i-- + ex2_prd_sel_neg_lohi => ex2_prd_sel_neg_lohi ,--i-- + ex2_prd_sel_pos_hi => ex2_prd_sel_pos_hi ,--i-- + ex2_prd_sel_pos_lo => ex2_prd_sel_pos_lo ,--i-- + ex2_prd_sel_pos_lohi => ex2_prd_sel_pos_lohi ,--i-- + ex2_sh_lvl3(0 to 162) => ex2_sh_lvl3(0 to 162) ,--i-- + f_fmt_ex2_pass_frac(0 to 52) => f_fmt_ex2_pass_frac(0 to 52) ,--i-- + f_alg_ex2_res(0 to 162) => f_alg_ex2_res(0 to 162) );--o-- + + + --#------------------------------------------------- + --# finish sticky + --#------------------------------------------------- + + ex2_frmneg <= ex2_from_integer and ex2_negate; --need +1 as part of negate + ex2_toneg <= (ex2_to_integer and not ex2_rnd_to_int and ex2_b_sign) ; --reverse rounding for toint/neg + ex2_topos <= (ex2_to_integer and not ex2_rnd_to_int and not ex2_b_sign) or ex2_rnd_to_int; + ex2_frmneg_o_toneg <= ex2_frmneg or ex2_toneg; + ex2_frmneg_o_topos <= ex2_frmneg or ex2_topos; + + ex2_math_gate_x <= not ex2_sel_byp_nonflip and ex2_b_zero_b and not ex2_ovf_pz ; + ex2_toint_gate_x <= ex2_to_integer and ex2_b_zero_b ; + ex2_toint_gt_nr_x <= ex2_to_integer and ex2_b_zero_b and f_pic_ex2_rnd_nr ; + ex2_toint_gt_ok_x <= ex2_to_integer and ex2_b_zero_b and f_pic_ex2_rnd_inf_ok ; + + ex2_math_gate_g <= not ex2_sel_byp_nonflip and not ex2_ovf_pz and ex2_b_zero_b and (ex2_prd_sel_pos_lo or ex2_prd_sel_neg_lo); + ex2_toint_gate_g <= ex2_to_integer and not ex2_ovf_pz and not ex2_sh_unf and ex2_b_zero_b; + ex2_toint_gt_nr_g <= ex2_to_integer and not ex2_ovf_pz and not ex2_sh_unf and ex2_b_zero_b and f_pic_ex2_rnd_nr ; + ex2_toint_gt_ok_g <= ex2_to_integer and not ex2_ovf_pz and not ex2_sh_unf and ex2_b_zero_b and f_pic_ex2_rnd_inf_ok ; + + ex2_bsha_pos <= not ex2_bsha_neg ; + + ex2_sticky_eac_x <= -- shift underflow enables all sticky + ( (ex2_sh_unf or ex2_sticky_en16_x(0)) and ex2_sticky_or16(0) and ex2_bsha_pos ) or + ( (ex2_sh_unf or ex2_sticky_en16_x(1)) and ex2_sticky_or16(1) and ex2_bsha_pos ) or + ( (ex2_sh_unf or ex2_sticky_en16_x(2)) and ex2_sticky_or16(2) and ex2_bsha_pos ) or + ( (ex2_sh_unf or ex2_sticky_en16_x(3)) and ex2_sticky_or16(3) and ex2_bsha_pos ) or + ( (ex2_sh_unf or ex2_sticky_en16_x(4)) and ex2_sticky_or16(4) and ex2_bsha_pos ) ; + + + ex2_sticky_math <= ex2_sticky_eac_x and ex2_math_gate_x ; + ex2_sticky_toint <= ex2_sticky_eac_x and ex2_toint_gate_x; + ex2_sticky_toint_nr <= ex2_sticky_eac_x and ex2_toint_gt_nr_x; + ex2_sticky_toint_ok <= ex2_sticky_eac_x and ex2_toint_gt_ok_x ; + + -- round-to-int goes up if guard is ON (this fakes it out) + ex2_lsb_toint_nr <= (ex2_sh16_162 or ex2_rnd_to_int) and ex2_toint_gt_nr_g ; + + ex2_g_math <= ex2_sh16_163 and ex2_math_gate_g ; + ex2_g_toint <= ex2_sh16_163 and ex2_toint_gate_g; + ex2_g_toint_nr <= ex2_sh16_163 and ex2_toint_gt_nr_g ; + ex2_g_toint_ok <= ex2_sh16_163 and ex2_toint_gt_ok_g ; + + + +--==############################################################## +--# ex3 latches (from ex2 logic) +--==############################################################## + + + ex3_ctl_lat: tri_rlmreg_p generic map (width=> 11, expand_type => expand_type, needs_sreset => 0) port map ( + forcee => forcee,--tidn, + delay_lclkr => delay_lclkr(3) ,--tidn, + mpw1_b => mpw1_b(3) ,--tidn, + mpw2_b => mpw2_b(0) ,--tidn, + vd => vdd , + gd => gnd , + nclk => nclk , + thold_b => thold_0_b , + sg => sg_0 , + act => ex2_act , + scout => ex3_ctl_so , + scin => ex3_ctl_si , + ----------------- + din(0) => ex2_sticky_math , + din(1) => ex2_sticky_toint , + din(2) => ex2_sticky_toint_nr , + din(3) => ex2_sticky_toint_ok , + din(4) => ex2_frmneg_o_toneg , + din(5) => ex2_frmneg_o_topos , + din(6) => ex2_lsb_toint_nr , + din(7) => ex2_g_math , + din(8) => ex2_g_toint , + din(9) => ex2_g_toint_nr , + din(10) => ex2_g_toint_ok , + ---------------- + dout(0) => ex3_sticky_math , + dout(1) => ex3_sticky_toint , + dout(2) => ex3_sticky_toint_nr , + dout(3) => ex3_sticky_toint_ok , + dout(4) => ex3_frmneg_o_toneg , + dout(5) => ex3_frmneg_o_topos , + dout(6) => ex3_lsb_toint_nr , + dout(7) => ex3_g_math , + dout(8) => ex3_g_toint , + dout(9) => ex3_g_toint_nr , + dout(10) => ex3_g_toint_ok ); + +--==############################################################## +--== ex3 logic +--==############################################################## + + f_alg_ex3_sticky <= ex3_sticky_math or ex3_g_math ;--output-- + f_alg_ex3_int_fi <= ex3_sticky_toint or ex3_g_toint ;--outpt-- + + ex3_int_fr_nr1_b <= not( ex3_g_toint_nr and ex3_sticky_toint_nr ); + ex3_int_fr_nr2_b <= not( ex3_g_toint_nr and ex3_lsb_toint_nr ); + ex3_int_fr_ok_b <= not( ex3_g_toint_ok or ex3_sticky_toint_ok ); + ex3_int_fr <= not( ex3_int_fr_nr1_b and ex3_int_fr_nr2_b and ex3_int_fr_ok_b ); + f_alg_ex3_int_fr <= ex3_int_fr ;--output-- f_pic + + ex3_sel_p1_0_b <= not( not ex3_int_fr and ex3_frmneg_o_toneg); + ex3_sel_p1_1_b <= not( ex3_int_fr and ex3_frmneg_o_topos); + f_alg_ex3_frc_sel_p1 <= not(ex3_sel_p1_0_b and ex3_sel_p1_1_b ) ;--output-- rounding converts + + +--==############################################################## +--# scan string +--==############################################################## + + ex1_ctl_si (0 to 4) <= ex1_ctl_so (1 to 4) & f_alg_si ;--SCAN + ex2_shd_si (0 to 67) <= ex2_shd_so (1 to 67) & ex1_ctl_so (0) ;--SCAN + ex2_shc_si (0 to 24) <= ex2_shc_so (1 to 24) & ex2_shd_so (0) ;--SCAN + ex2_ctl_si (0 to 14) <= ex2_ctl_so (1 to 14) & ex2_shc_so (0) ;--SCAN + ex3_ctl_si (0 to 10) <= ex3_ctl_so (1 to 10) & ex2_ctl_so (0) ;--SCAN + act_si (0 to 4) <= act_so (1 to 4) & ex3_ctl_so (0) ;--SCAN + f_alg_so <= act_so (0) ;--SCAN + + +end; -- fuq_alg ARCHITECTURE diff --git a/rel/src/vhdl/work/fuq_alg_add.vhdl b/rel/src/vhdl/work/fuq_alg_add.vhdl new file mode 100644 index 0000000..7478788 --- /dev/null +++ b/rel/src/vhdl/work/fuq_alg_add.vhdl @@ -0,0 +1,706 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + library clib ; + +entity fuq_alg_add is +generic( expand_type : integer := 2 ); -- 0 - ibm tech, 1 - other ); +port( + + vdd : inout power_logic; + gnd : inout power_logic; + + f_byp_alg_ex1_b_expo :in std_ulogic_vector(1 to 13); + f_byp_alg_ex1_a_expo :in std_ulogic_vector(1 to 13); + f_byp_alg_ex1_c_expo :in std_ulogic_vector(1 to 13); + + ex1_sel_special_b :in std_ulogic ; + + ex1_bsha_6_o :out std_ulogic ; + ex1_bsha_7_o :out std_ulogic ; + ex1_bsha_8_o :out std_ulogic ; + ex1_bsha_9_o :out std_ulogic ; + + ex1_bsha_neg_o :out std_ulogic ; + ex1_sh_ovf :out std_ulogic ; + ex1_sh_unf_x :out std_ulogic ; + + + ex1_lvl1_shdcd000_b :out std_ulogic ; + ex1_lvl1_shdcd001_b :out std_ulogic ; + ex1_lvl1_shdcd002_b :out std_ulogic ; + ex1_lvl1_shdcd003_b :out std_ulogic ; + + ex1_lvl2_shdcd000 :out std_ulogic ; + ex1_lvl2_shdcd004 :out std_ulogic ; + ex1_lvl2_shdcd008 :out std_ulogic ; + ex1_lvl2_shdcd012 :out std_ulogic ; + + ex1_lvl3_shdcd000 :out std_ulogic ;-- 0000 +000 + ex1_lvl3_shdcd016 :out std_ulogic ;-- 0001 +016 + ex1_lvl3_shdcd032 :out std_ulogic ;-- 0010 +032 + ex1_lvl3_shdcd048 :out std_ulogic ;-- 0011 +048 + ex1_lvl3_shdcd064 :out std_ulogic ;-- 0100 +064 + ex1_lvl3_shdcd080 :out std_ulogic ;-- 0101 +080 + ex1_lvl3_shdcd096 :out std_ulogic ;-- 0110 +096 + ex1_lvl3_shdcd112 :out std_ulogic ;-- 0111 +112 + ex1_lvl3_shdcd128 :out std_ulogic ;-- 1000 +128 + ex1_lvl3_shdcd144 :out std_ulogic ;-- 1001 +144 + ex1_lvl3_shdcd160 :out std_ulogic ;-- 1010 +160 + ex1_lvl3_shdcd176 :out std_ulogic ;-- 1011 + ex1_lvl3_shdcd192 :out std_ulogic ;-- 1100 -064 + ex1_lvl3_shdcd208 :out std_ulogic ;-- 1101 -048 + ex1_lvl3_shdcd224 :out std_ulogic ;-- 1110 -032 + ex1_lvl3_shdcd240 :out std_ulogic -- 1111 -016 +); ------------------------------------------------------------------- + + + +end fuq_alg_add; + +architecture fuq_alg_add of fuq_alg_add is + + constant tiup :std_ulogic := '1'; + constant tidn :std_ulogic := '0'; + signal ex1_bsha_sim_c :std_ulogic_vector(2 to 14); + signal ex1_bsha_sim_p :std_ulogic_vector(1 to 13); + signal ex1_bsha_sim_g :std_ulogic_vector(2 to 13); + signal ex1_bsha_sim :std_ulogic_vector(1 to 13); + + signal ex1_b_expo_b :std_ulogic_vector(1 to 13); + signal ex1_a_expo_b :std_ulogic_vector(2 to 13); + signal ex1_c_expo_b :std_ulogic_vector(2 to 13); + signal ex1_bsha_neg :std_ulogic; + signal ex1_sh_ovf_b :std_ulogic; + signal ex1_alg_sx :std_ulogic_vector(1 to 13) ; + signal ex1_alg_cx :std_ulogic_vector(0 to 12) ; + signal ex1_alg_add_p :std_ulogic_vector(1 to 12) ; + signal ex1_alg_add_g_b :std_ulogic_vector(2 to 12) ; + signal ex1_alg_add_t_b :std_ulogic_vector(2 to 11) ; + + signal ex1_bsha_6_b :std_ulogic; + signal ex1_bsha_7_b :std_ulogic; + signal ex1_bsha_8_b :std_ulogic; + signal ex1_bsha_9_b :std_ulogic; + signal ex1_67_dcd00_b :std_ulogic; + signal ex1_67_dcd01_b :std_ulogic; + signal ex1_67_dcd10_b :std_ulogic; + signal ex1_67_dcd11_b :std_ulogic; + signal ex1_89_dcd00_b :std_ulogic; + signal ex1_89_dcd01_b :std_ulogic; + signal ex1_89_dcd10_b :std_ulogic; + signal ex1_89_dcd11_b :std_ulogic; + + signal ex1_lv2_0pg0_b :std_ulogic; + signal ex1_lv2_0pg1_b :std_ulogic; + signal ex1_lv2_0pk0_b :std_ulogic; + signal ex1_lv2_0pk1_b :std_ulogic; + signal ex1_lv2_0pp0_b :std_ulogic; + signal ex1_lv2_0pp1_b :std_ulogic; + signal ex1_lv2_1pg0_b :std_ulogic; + signal ex1_lv2_1pg1_b :std_ulogic; + signal ex1_lv2_1pk0_b :std_ulogic; + signal ex1_lv2_1pk1_b :std_ulogic; + signal ex1_lv2_1pp0_b :std_ulogic; + signal ex1_lv2_1pp1_b :std_ulogic; + signal ex1_lv2_shdcd000 :std_ulogic; + signal ex1_lv2_shdcd004 :std_ulogic; + signal ex1_lv2_shdcd008 :std_ulogic; + signal ex1_lv2_shdcd012 :std_ulogic; + signal ex1_lvl2_shdcd000_b :std_ulogic; + signal ex1_lvl2_shdcd004_b :std_ulogic; + signal ex1_lvl2_shdcd008_b :std_ulogic; + signal ex1_lvl2_shdcd012_b :std_ulogic; + + signal ex1_alg_add_c_b :std_ulogic_vector(7 to 10); + signal ex1_g02_12 :std_ulogic; + signal ex1_g02_12_b :std_ulogic; + signal ex1_bsha_13_b :std_ulogic; + signal ex1_bsha_13 :std_ulogic; + signal ex1_bsha_12_b :std_ulogic; + signal ex1_bsha_12 :std_ulogic; + signal ex1_lv2_ci11n_en_b :std_ulogic; + signal ex1_lv2_ci11p_en_b :std_ulogic; + signal ex1_lv2_ci11n_en :std_ulogic; + signal ex1_lv2_ci11p_en :std_ulogic; + signal ex1_g02_10 :std_ulogic; + signal ex1_t02_10 :std_ulogic; + signal ex1_g04_10_b :std_ulogic; + signal ex1_lv2_g11_x :std_ulogic; + signal ex1_lv2_g11_b :std_ulogic; + signal ex1_lv2_g11 :std_ulogic; + signal ex1_lv2_k11_b :std_ulogic; + signal ex1_lv2_k11 :std_ulogic; + signal ex1_lv2_p11_b :std_ulogic; + signal ex1_lv2_p11 :std_ulogic; + signal ex1_lv2_p10_b :std_ulogic; + signal ex1_lv2_p10 :std_ulogic; + signal ex1_g04_10 :std_ulogic; + signal ex1_g02_6 :std_ulogic; + signal ex1_g02_7 :std_ulogic; + signal ex1_g02_8 :std_ulogic; + signal ex1_g02_9 :std_ulogic; + signal ex1_t02_6 :std_ulogic; + signal ex1_t02_7 :std_ulogic; + signal ex1_t02_8 :std_ulogic; + signal ex1_t02_9 :std_ulogic; + signal ex1_g04_6_b :std_ulogic; + signal ex1_g04_7_b :std_ulogic; + signal ex1_g04_8_b :std_ulogic; + signal ex1_g04_9_b :std_ulogic; + signal ex1_t04_6_b :std_ulogic; + signal ex1_t04_7_b :std_ulogic; + signal ex1_t04_8_b :std_ulogic; + signal ex1_t04_9_b :std_ulogic; + signal ex1_g08_6 :std_ulogic; + signal ex1_g04_7 :std_ulogic; + signal ex1_g04_8 :std_ulogic; + signal ex1_g04_9 :std_ulogic; + signal ex1_t04_7 :std_ulogic; + signal ex1_t04_8 :std_ulogic; + signal ex1_t04_9 :std_ulogic; + signal ex1_bsha_6 :std_ulogic; + signal ex1_bsha_7 :std_ulogic; + signal ex1_bsha_8 :std_ulogic; + signal ex1_bsha_9 :std_ulogic; + signal ex1_g02_4 :std_ulogic; + signal ex1_g02_2 :std_ulogic; + signal ex1_t02_4 :std_ulogic; + signal ex1_t02_2 :std_ulogic; + signal ex1_g04_2_b :std_ulogic; + signal ex1_t04_2_b :std_ulogic; + signal ex1_ones_2t3_b :std_ulogic; + signal ex1_ones_4t5_b :std_ulogic; + signal ex1_ones_2t5 :std_ulogic; + signal ex1_ones_2t5_b :std_ulogic; + signal ex1_zero_2_b :std_ulogic; + signal ex1_zero_3_b :std_ulogic; + signal ex1_zero_4_b :std_ulogic; + signal ex1_zero_5 :std_ulogic; + signal ex1_zero_5_b :std_ulogic; + signal ex1_zero_2t3 :std_ulogic; + signal ex1_zero_4t5 :std_ulogic; + signal ex1_zero_2t5_b :std_ulogic; + signal pos_if_pco6 :std_ulogic; + signal pos_if_nco6 :std_ulogic; + signal pos_if_pco6_b :std_ulogic; + signal pos_if_nco6_b :std_ulogic; + signal unf_if_nco6_b :std_ulogic; + signal unf_if_pco6_b :std_ulogic; + signal ex1_g08_6_b :std_ulogic; + signal ex1_bsha_pos :std_ulogic; + signal ex1_bsha_6_i :std_ulogic; + signal ex1_bsha_7_i :std_ulogic; + signal ex1_bsha_8_i :std_ulogic; + signal ex1_bsha_9_i :std_ulogic; + signal ex1_ack_s :std_ulogic_vector(1 to 13); + signal ex1_ack_c :std_ulogic_vector(1 to 12); + + + + +begin + + ------------------------------------------------------- + -- FOR simulation only : will not generate any logic + ------------------------------------------------------- + + + ex1_bsha_sim_p(1 to 12) <= ex1_alg_sx(1 to 12) xor ex1_alg_cx(1 to 12); + ex1_bsha_sim_p( 13) <= ex1_alg_sx( 13) ; + ex1_bsha_sim_g(2 to 12) <= ex1_alg_sx(2 to 12) and ex1_alg_cx(2 to 12); + ex1_bsha_sim_g(13) <= tidn; + ex1_bsha_sim (1 to 13) <= ex1_bsha_sim_p(1 to 13) xor ex1_bsha_sim_c(2 to 14); + + ex1_bsha_sim_c(14) <= tidn; + ex1_bsha_sim_c(13) <= ex1_bsha_sim_g(13) or (ex1_bsha_sim_p(13) and ex1_bsha_sim_c(14) ); + ex1_bsha_sim_c(12) <= ex1_bsha_sim_g(12) or (ex1_bsha_sim_p(12) and ex1_bsha_sim_c(13) ); + ex1_bsha_sim_c(11) <= ex1_bsha_sim_g(11) or (ex1_bsha_sim_p(11) and ex1_bsha_sim_c(12) ); + ex1_bsha_sim_c(10) <= ex1_bsha_sim_g(10) or (ex1_bsha_sim_p(10) and ex1_bsha_sim_c(11) ); + ex1_bsha_sim_c( 9) <= ex1_bsha_sim_g( 9) or (ex1_bsha_sim_p( 9) and ex1_bsha_sim_c(10) ); + ex1_bsha_sim_c( 8) <= ex1_bsha_sim_g( 8) or (ex1_bsha_sim_p( 8) and ex1_bsha_sim_c( 9) ); + ex1_bsha_sim_c( 7) <= ex1_bsha_sim_g( 7) or (ex1_bsha_sim_p( 7) and ex1_bsha_sim_c( 8) ); + ex1_bsha_sim_c( 6) <= ex1_bsha_sim_g( 6) or (ex1_bsha_sim_p( 6) and ex1_bsha_sim_c( 7) ); + ex1_bsha_sim_c( 5) <= ex1_bsha_sim_g( 5) or (ex1_bsha_sim_p( 5) and ex1_bsha_sim_c( 6) ); + ex1_bsha_sim_c( 4) <= ex1_bsha_sim_g( 4) or (ex1_bsha_sim_p( 4) and ex1_bsha_sim_c( 5) ); + ex1_bsha_sim_c( 3) <= ex1_bsha_sim_g( 3) or (ex1_bsha_sim_p( 3) and ex1_bsha_sim_c( 4) ); + ex1_bsha_sim_c( 2) <= ex1_bsha_sim_g( 2) or (ex1_bsha_sim_p( 2) and ex1_bsha_sim_c( 3) ); + + +--==############################################################## +--# ex1 logic +--==############################################################## + -- for MADD operations SHA = (Ea+Ec+!Eb) + 1 -bias + 56 + -- (Ea+Ec+!Eb) + 57 +!bias + 1 + -- (Ea+Ec+!Eb) + 58 +!bias + -- 0_0011_1111_1111 bias = 1023 + -- 1_1100_0000_0000 !bias + -- 11_1010 58 + -- ----------------------- + -- 1_1100_0011_1010 ( !bias + 58 ) + -- + -- leading bit [1] is a sign bit, but the compressor creates bit 0. + -- 13 bits should be enough to hold the entire result, therefore throw away bit 0. + + + a32_inv: ex1_a_expo_b(2 to 13) <= not f_byp_alg_ex1_a_expo(2 to 13); + c32_inv: ex1_c_expo_b(2 to 13) <= not f_byp_alg_ex1_c_expo(2 to 13); + b32_inv: ex1_b_expo_b(1 to 13) <= not f_byp_alg_ex1_b_expo(1 to 13); + +sx01: ex1_ack_s( 1) <= not( f_byp_alg_ex1_a_expo( 1) xor f_byp_alg_ex1_c_expo( 1) ); --K[ 1]==1 +sx02: ex1_ack_s( 2) <= not( f_byp_alg_ex1_a_expo( 2) xor f_byp_alg_ex1_c_expo( 2) ); --K[ 2]==1 +sx03: ex1_ack_s( 3) <= not( f_byp_alg_ex1_a_expo( 3) xor f_byp_alg_ex1_c_expo( 3) ); --K[ 3]==1 +sx04: ex1_ack_s( 4) <= ( f_byp_alg_ex1_a_expo( 4) xor f_byp_alg_ex1_c_expo( 4) ); --K[ 4]==0 +sx05: ex1_ack_s( 5) <= ( f_byp_alg_ex1_a_expo( 5) xor f_byp_alg_ex1_c_expo( 5) ); --K[ 5]==0 +sx06: ex1_ack_s( 6) <= ( f_byp_alg_ex1_a_expo( 6) xor f_byp_alg_ex1_c_expo( 6) ); --K[ 6]==0 +sx07: ex1_ack_s( 7) <= ( f_byp_alg_ex1_a_expo( 7) xor f_byp_alg_ex1_c_expo( 7) ); --K[ 7]==0 +sx08: ex1_ack_s( 8) <= not( f_byp_alg_ex1_a_expo( 8) xor f_byp_alg_ex1_c_expo( 8) ); --K[ 8]==1 +sx09: ex1_ack_s( 9) <= not( f_byp_alg_ex1_a_expo( 9) xor f_byp_alg_ex1_c_expo( 9) ); --K[ 9]==1 1 +sx10: ex1_ack_s(10) <= not( f_byp_alg_ex1_a_expo(10) xor f_byp_alg_ex1_c_expo(10) ); --K[10]==1 1 +sx11: ex1_ack_s(11) <= ( f_byp_alg_ex1_a_expo(11) xor f_byp_alg_ex1_c_expo(11) ); --K[11]==0 +sx12: ex1_ack_s(12) <= not( f_byp_alg_ex1_a_expo(12) xor f_byp_alg_ex1_c_expo(12) ); --K[12]==1 +sx13: ex1_ack_s(13) <= ( f_byp_alg_ex1_a_expo(13) xor f_byp_alg_ex1_c_expo(13) ); --K[13]==0 + + + +-- cx00: ex1_ack_c( 0) <= not( ex1_a_expo_b( 1) and ex1_c_expo_b( 1) ); --K[ 1]==1 +or + cx01: ex1_ack_c( 1) <= not( ex1_a_expo_b( 2) and ex1_c_expo_b( 2) ); --K[ 2]==1 +or + cx02: ex1_ack_c( 2) <= not( ex1_a_expo_b( 3) and ex1_c_expo_b( 3) ); --K[ 3]==1 +or + cx03: ex1_ack_c( 3) <= not( ex1_a_expo_b( 4) or ex1_c_expo_b( 4) ); --K[ 4]==0 +and + cx04: ex1_ack_c( 4) <= not( ex1_a_expo_b( 5) or ex1_c_expo_b( 5) ); --K[ 5]==0 +and + cx05: ex1_ack_c( 5) <= not( ex1_a_expo_b( 6) or ex1_c_expo_b( 6) ); --K[ 6]==0 +and + cx06: ex1_ack_c( 6) <= not( ex1_a_expo_b( 7) or ex1_c_expo_b( 7) ); --K[ 7]==0 +and + cx07: ex1_ack_c( 7) <= not( ex1_a_expo_b( 8) and ex1_c_expo_b( 8) ); --K[ 8]==1 +or + cx08: ex1_ack_c( 8) <= not( ex1_a_expo_b( 9) and ex1_c_expo_b( 9) ); --K[ 9]==1 +or + cx09: ex1_ack_c( 9) <= not( ex1_a_expo_b(10) and ex1_c_expo_b(10) ); --K[10]==1 +or + cx10: ex1_ack_c(10) <= not( ex1_a_expo_b(11) or ex1_c_expo_b(11) ); --K[11]==0 +and + cx11: ex1_ack_c(11) <= not( ex1_a_expo_b(12) and ex1_c_expo_b(12) ); --K[12]==1 +or + cx12: ex1_ack_c(12) <= not( ex1_a_expo_b(13) or ex1_c_expo_b(13) ); --K[13]==0 + + + + + + +sha32_01: entity clib.c_prism_csa32 port map( -- fuq_csa32s_h2 MLT32_X1_A12TH + vd => vdd, + gd => gnd, + a => ex1_b_expo_b(1) ,--i-- + b => ex1_ack_s(1) ,--i-- + c => ex1_ack_c(1) ,--i-- + sum => ex1_alg_sx(1) ,--o-- + car => ex1_alg_cx(0) );--o-- +sha32_02: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex1_b_expo_b(2) ,--i-- + b => ex1_ack_s(2) ,--i-- + c => ex1_ack_c(2) ,--i-- + sum => ex1_alg_sx(2) ,--o-- + car => ex1_alg_cx(1) );--o-- +sha32_03: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex1_b_expo_b(3) ,--i-- + b => ex1_ack_s(3) ,--i-- + c => ex1_ack_c(3) ,--i-- + sum => ex1_alg_sx(3) ,--o-- + car => ex1_alg_cx(2) );--o-- +sha32_04: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex1_b_expo_b(4) ,--i-- + b => ex1_ack_s(4) ,--i-- + c => ex1_ack_c(4) ,--i-- + sum => ex1_alg_sx(4) ,--o-- + car => ex1_alg_cx(3) );--o-- +sha32_05: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex1_b_expo_b(5) ,--i-- + b => ex1_ack_s(5) ,--i-- + c => ex1_ack_c(5) ,--i-- + sum => ex1_alg_sx(5) ,--o-- + car => ex1_alg_cx(4) );--o-- +sha32_06: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex1_b_expo_b(6) ,--i-- + b => ex1_ack_s(6) ,--i-- + c => ex1_ack_c(6) ,--i-- + sum => ex1_alg_sx(6) ,--o-- + car => ex1_alg_cx(5) );--o-- +sha32_07: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex1_b_expo_b(7) ,--i-- + b => ex1_ack_s(7) ,--i-- + c => ex1_ack_c(7) ,--i-- + sum => ex1_alg_sx(7) ,--o-- + car => ex1_alg_cx(6) );--o-- +sha32_08: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex1_b_expo_b(8) ,--i-- + b => ex1_ack_s(8) ,--i-- + c => ex1_ack_c(8) ,--i-- + sum => ex1_alg_sx(8) ,--o-- + car => ex1_alg_cx(7) );--o-- +sha32_09: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex1_b_expo_b(9) ,--i-- + b => ex1_ack_s(9) ,--i-- + c => ex1_ack_c(9) ,--i-- + sum => ex1_alg_sx(9) ,--o-- + car => ex1_alg_cx(8) );--o-- +sha32_10: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex1_b_expo_b(10) ,--i-- + b => ex1_ack_s(10) ,--i-- + c => ex1_ack_c(10) ,--i-- + sum => ex1_alg_sx(10) ,--o-- + car => ex1_alg_cx(9) );--o-- +sha32_11: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex1_b_expo_b(11) ,--i-- + b => ex1_ack_s(11) ,--i-- + c => ex1_ack_c(11) ,--i-- + sum => ex1_alg_sx(11) ,--o-- + car => ex1_alg_cx(10) );--o-- +sha32_12: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex1_b_expo_b(12) ,--i-- + b => ex1_ack_s(12) ,--i-- + c => ex1_ack_c(12) ,--i-- + sum => ex1_alg_sx(12) ,--o-- + car => ex1_alg_cx(11) );--o-- +sha32_13: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex1_b_expo_b(13) ,--i-- + b => ex1_ack_s(13) ,--i-- + c => tidn ,--i-- + sum => ex1_alg_sx(13) ,--o-- + car => ex1_alg_cx(12) );--o-- + + + -- now finish the add (for sha==0 means shift 0) + +p1_01: ex1_alg_add_p( 1) <= ex1_alg_sx( 1) xor ex1_alg_cx( 1); +p1_02: ex1_alg_add_p( 2) <= ex1_alg_sx( 2) xor ex1_alg_cx( 2); +p1_03: ex1_alg_add_p( 3) <= ex1_alg_sx( 3) xor ex1_alg_cx( 3); +p1_04: ex1_alg_add_p( 4) <= ex1_alg_sx( 4) xor ex1_alg_cx( 4); +p1_05: ex1_alg_add_p( 5) <= ex1_alg_sx( 5) xor ex1_alg_cx( 5); +p1_06: ex1_alg_add_p( 6) <= ex1_alg_sx( 6) xor ex1_alg_cx( 6); +p1_07: ex1_alg_add_p( 7) <= ex1_alg_sx( 7) xor ex1_alg_cx( 7); +p1_08: ex1_alg_add_p( 8) <= ex1_alg_sx( 8) xor ex1_alg_cx( 8); +p1_09: ex1_alg_add_p( 9) <= ex1_alg_sx( 9) xor ex1_alg_cx( 9); +p1_10: ex1_alg_add_p(10) <= ex1_alg_sx(10) xor ex1_alg_cx(10); +p1_11: ex1_alg_add_p(11) <= ex1_alg_sx(11) xor ex1_alg_cx(11); +p1_12: ex1_alg_add_p(12) <= ex1_alg_sx(12) xor ex1_alg_cx(12); + + +g1_02: ex1_alg_add_g_b( 2) <= not( ex1_alg_sx( 2) and ex1_alg_cx( 2) ); +g1_03: ex1_alg_add_g_b( 3) <= not( ex1_alg_sx( 3) and ex1_alg_cx( 3) ); +g1_04: ex1_alg_add_g_b( 4) <= not( ex1_alg_sx( 4) and ex1_alg_cx( 4) ); +g1_05: ex1_alg_add_g_b( 5) <= not( ex1_alg_sx( 5) and ex1_alg_cx( 5) ); +g1_06: ex1_alg_add_g_b( 6) <= not( ex1_alg_sx( 6) and ex1_alg_cx( 6) ); +g1_07: ex1_alg_add_g_b( 7) <= not( ex1_alg_sx( 7) and ex1_alg_cx( 7) ); +g1_08: ex1_alg_add_g_b( 8) <= not( ex1_alg_sx( 8) and ex1_alg_cx( 8) ); +g1_09: ex1_alg_add_g_b( 9) <= not( ex1_alg_sx( 9) and ex1_alg_cx( 9) ); +g1_10: ex1_alg_add_g_b(10) <= not( ex1_alg_sx(10) and ex1_alg_cx(10) ); +g1_11: ex1_alg_add_g_b(11) <= not( ex1_alg_sx(11) and ex1_alg_cx(11) ); +g1_12: ex1_alg_add_g_b(12) <= not( ex1_alg_sx(12) and ex1_alg_cx(12) ); + +t1_02: ex1_alg_add_t_b( 2) <= not( ex1_alg_sx( 2) or ex1_alg_cx( 2) ); +t1_03: ex1_alg_add_t_b( 3) <= not( ex1_alg_sx( 3) or ex1_alg_cx( 3) ); +t1_04: ex1_alg_add_t_b( 4) <= not( ex1_alg_sx( 4) or ex1_alg_cx( 4) ); +t1_05: ex1_alg_add_t_b( 5) <= not( ex1_alg_sx( 5) or ex1_alg_cx( 5) ); +t1_06: ex1_alg_add_t_b( 6) <= not( ex1_alg_sx( 6) or ex1_alg_cx( 6) ); +t1_07: ex1_alg_add_t_b( 7) <= not( ex1_alg_sx( 7) or ex1_alg_cx( 7) ); +t1_08: ex1_alg_add_t_b( 8) <= not( ex1_alg_sx( 8) or ex1_alg_cx( 8) ); +t1_09: ex1_alg_add_t_b( 9) <= not( ex1_alg_sx( 9) or ex1_alg_cx( 9) ); +t1_10: ex1_alg_add_t_b(10) <= not( ex1_alg_sx(10) or ex1_alg_cx(10) ); +t1_11: ex1_alg_add_t_b(11) <= not( ex1_alg_sx(11) or ex1_alg_cx(11) ); + + ----------------------------------------------------------------------- + -- 12:13 are a decode group (12,13) are known before adder starts ) + ----------------------------------------------------------------------- + +g2_12: ex1_g02_12 <= not ex1_alg_add_g_b(12); -- main carry chain +g2_12b: ex1_g02_12_b <= not ex1_g02_12 ; -- main carry chain + +res_13b: ex1_bsha_13_b <= not ex1_alg_sx(13); -- direct from compressor +res_13: ex1_bsha_13 <= not ex1_bsha_13_b ; -- to decoder 0/1/2/3 +res_12b: ex1_bsha_12_b <= not ex1_alg_add_p(12); +res_12: ex1_bsha_12 <= not ex1_bsha_12_b ; -- to decoder 0/1/2/3 + +ci11nb: ex1_lv2_ci11n_en_b <= not( ex1_sel_special_b and ex1_g02_12_b ); +ci11pb: ex1_lv2_ci11p_en_b <= not( ex1_sel_special_b and ex1_g02_12 ); +ci11n: ex1_lv2_ci11n_en <= not( ex1_lv2_ci11n_en_b ); -- to decoder 0/4/8/12 +ci11p: ex1_lv2_ci11p_en <= not( ex1_lv2_ci11p_en_b ); -- to decoder 0/4/8/12 + + ----------------------------------------------------------------------- + -- 10:11 are a decode group, do not compute adder result (send signal direct to decode) + ----------------------------------------------------------------------- + +g2_10: ex1_g02_10 <= not( ex1_alg_add_g_b(10) and (ex1_alg_add_t_b(10) or ex1_alg_add_g_b(11)) );--main carry chain +t2_10: ex1_t02_10 <= not( ex1_alg_add_t_b(10) or ex1_alg_add_t_b(11) );--main carry chain +g4_10: ex1_g04_10_b <= not( ex1_g02_10 or (ex1_t02_10 and ex1_g02_12 ) );--main carry chain + +g11x: ex1_lv2_g11_x <= not( ex1_alg_add_g_b(11) ); +g11b: ex1_lv2_g11_b <= not( ex1_lv2_g11_x ); +g11: ex1_lv2_g11 <= not( ex1_lv2_g11_b ); -- to decoder 0/4/8/12 +k11x: ex1_lv2_k11_b <= not( ex1_alg_add_t_b(11) ); +k11: ex1_lv2_k11 <= not( ex1_lv2_k11_b ); -- to decoder 0/4/8/12 +p11b: ex1_lv2_p11_b <= not( ex1_alg_add_p(11) ); +p11: ex1_lv2_p11 <= not( ex1_lv2_p11_b ); -- to decoder 0/4/8/12 +p10b: ex1_lv2_p10_b <= not( ex1_alg_add_p(10) ); -- to decoder 0/4/8/12 +p10: ex1_lv2_p10 <= not( ex1_lv2_p10_b ); -- to decoder 0/4/8/12 + + ----------------------------------------------------------------------- + -- 6:9 are a decode group, not used until next cycle: (get add result then decode) + ------------------------------------------------------------------------ + +g4x_10: ex1_g04_10 <= not ex1_g04_10_b ; -- use this buffered of version to finish the local carry chain + +g2_06: ex1_g02_6 <= not( ex1_alg_add_g_b(6) and (ex1_alg_add_t_b(6) or ex1_alg_add_g_b(7)) ); +g2_07: ex1_g02_7 <= not( ex1_alg_add_g_b(7) and (ex1_alg_add_t_b(7) or ex1_alg_add_g_b(8)) ); +g2_08: ex1_g02_8 <= not( ex1_alg_add_g_b(8) and (ex1_alg_add_t_b(8) or ex1_alg_add_g_b(9)) ); +g2_09: ex1_g02_9 <= not( ex1_alg_add_g_b(9) ); +t2_06: ex1_t02_6 <= not( ex1_alg_add_t_b(6) or ex1_alg_add_t_b(7) ); +t2_07: ex1_t02_7 <= not( ex1_alg_add_t_b(7) or ex1_alg_add_t_b(8) ); +t2_08: ex1_t02_8 <= not( ex1_alg_add_t_b(8) or ex1_alg_add_t_b(9) ); +t2_09: ex1_t02_9 <= not( ex1_alg_add_t_b(9) ); + +g4_06b: ex1_g04_6_b <= not( ex1_g02_6 or (ex1_t02_6 and ex1_g02_8 ) ); +g4_07b: ex1_g04_7_b <= not( ex1_g02_7 or (ex1_t02_7 and ex1_g02_9 ) ); +g4_08b: ex1_g04_8_b <= not( ex1_g02_8 ); +g4_09b: ex1_g04_9_b <= not( ex1_g02_9 ); +t4_06b: ex1_t04_6_b <= not( ex1_t02_6 and ex1_t02_8 ); +t4_07b: ex1_t04_7_b <= not( ex1_t02_7 and ex1_t02_9 ); +t4_08b: ex1_t04_8_b <= not( ex1_t02_8 ); +t4_09b: ex1_t04_9_b <= not( ex1_t02_9 ); + +g8_06: ex1_g08_6 <= not( ex1_g04_6_b and (ex1_t04_6_b or ex1_g04_10_b ) );--main carry chain +g4_07: ex1_g04_7 <= not( ex1_g04_7_b ); +g4_08: ex1_g04_8 <= not( ex1_g04_8_b ); +g4_09: ex1_g04_9 <= not( ex1_g04_9_b ); +t4_07: ex1_t04_7 <= not( ex1_t04_7_b ); +t4_08: ex1_t04_8 <= not( ex1_t04_8_b ); +t4_09: ex1_t04_9 <= not( ex1_t04_9_b ); + +c07: ex1_alg_add_c_b(7) <= not( ex1_g04_7 or (ex1_t04_7 and ex1_g04_10) ); +c08: ex1_alg_add_c_b(8) <= not( ex1_g04_8 or (ex1_t04_8 and ex1_g04_10) ); +c09: ex1_alg_add_c_b(9) <= not( ex1_g04_9 or (ex1_t04_9 and ex1_g04_10) ); +c10: ex1_alg_add_c_b(10) <= not( ex1_g04_10 ); + +res_6: ex1_bsha_6 <= not( ex1_alg_add_p(6) xor ex1_alg_add_c_b(7) );--to multiple of 16 decoder +res_7: ex1_bsha_7 <= not( ex1_alg_add_p(7) xor ex1_alg_add_c_b(8) );--to multiple of 16 decoder +res_8: ex1_bsha_8 <= not( ex1_alg_add_p(8) xor ex1_alg_add_c_b(9) );--to multiple of 16 decoder +res_9: ex1_bsha_9 <= not( ex1_alg_add_p(9) xor ex1_alg_add_c_b(10) );--to multiple of 16 decoder + + +res_6i: ex1_bsha_6_i <= not ex1_bsha_6 ; +res_7i: ex1_bsha_7_i <= not ex1_bsha_7 ; +res_8i: ex1_bsha_8_i <= not ex1_bsha_8 ; +res_9i: ex1_bsha_9_i <= not ex1_bsha_9 ; + +res_6o: ex1_bsha_6_o <= not ex1_bsha_6_i ; +res_7o: ex1_bsha_7_o <= not ex1_bsha_7_i ; +res_8o: ex1_bsha_8_o <= not ex1_bsha_8_i ; +res_9o: ex1_bsha_9_o <= not ex1_bsha_9_i ; + + ------------------------------------------------------------------------- + -- Just need to know if 2/3/4/5 != 0000 for unf, produce that signal directly + ------------------------------------------------------------------------- + +g2_02: ex1_g02_2 <= not( ex1_alg_add_g_b(2) and (ex1_alg_add_t_b(2) or ex1_alg_add_g_b(3)) ); --for carry select +g2_04: ex1_g02_4 <= not( ex1_alg_add_g_b(4) and (ex1_alg_add_t_b(4) or ex1_alg_add_g_b(5)) ); --for carry select + +t2_02: ex1_t02_2 <= not( (ex1_alg_add_t_b(2) or ex1_alg_add_t_b(3)) ); --for carry select +t2_04: ex1_t02_4 <= not( ex1_alg_add_g_b(4) and (ex1_alg_add_t_b(4) or ex1_alg_add_t_b(5)) ); --for carry select + +g4_02: ex1_g04_2_b <= not( ex1_g02_2 or (ex1_t02_2 and ex1_g02_4 ) ); --for carry select +t4_02: ex1_t04_2_b <= not( ex1_g02_2 or (ex1_t02_2 and ex1_t02_4 ) ); --for carry select + + +ones23: ex1_ones_2t3_b <= not( ex1_alg_add_p(2) and ex1_alg_add_p(3) );-- for unf calculation +ones45: ex1_ones_4t5_b <= not( ex1_alg_add_p(4) and ex1_alg_add_p(5) );-- for unf calculation +ones25: ex1_ones_2t5 <= not( ex1_ones_2t3_b or ex1_ones_4t5_b );-- for unf calculation +ones25_b: ex1_ones_2t5_b <= not( ex1_ones_2t5 ); + +z2b: ex1_zero_2_b <= not( ex1_alg_add_p(2) xor ex1_alg_add_t_b(3) );-- for unf calc +z3b: ex1_zero_3_b <= not( ex1_alg_add_p(3) xor ex1_alg_add_t_b(4) );-- for unf calc +z4b: ex1_zero_4_b <= not( ex1_alg_add_p(4) xor ex1_alg_add_t_b(5) );-- for unf calc +z5: ex1_zero_5 <= not( ex1_alg_add_p(5) );-- for unf calc +z5b: ex1_zero_5_b <= not( ex1_zero_5 );-- for unf calc +z23: ex1_zero_2t3 <= not( ex1_zero_2_b or ex1_zero_3_b );-- for unf calc +z45: ex1_zero_4t5 <= not( ex1_zero_4_b or ex1_zero_5_b );-- for unf calc +z25b: ex1_zero_2t5_b <= not( ex1_zero_2t3 and ex1_zero_4t5 );-- for unf calc + + ---------------------------------------------------------------------------- + -- [1] is really the sign bit .. needed to indicate ovf/underflow + ------------------------------------------------- + -- finish shift underflow + -- if sha > 162 all the bits should become sticky and the aligner output should be zero + -- from 163:255 the shifter does this, so just need to detect the upper bits + +pco6: pos_if_pco6 <= ( ex1_alg_add_p(1) xor ex1_t04_2_b ); +nco6: pos_if_nco6 <= ( ex1_alg_add_p(1) xor ex1_g04_2_b ); +pco6b: pos_if_pco6_b <= not pos_if_pco6 ; +nco6b: pos_if_nco6_b <= not pos_if_nco6 ; + +unifnc: unf_if_nco6_b <= not( pos_if_nco6 and ex1_zero_2t5_b ); +unifpc: unf_if_pco6_b <= not( pos_if_pco6 and ex1_ones_2t5_b ); + +g8_06b: ex1_g08_6_b <= not ex1_g08_6 ; +shap: ex1_bsha_pos <= not( (pos_if_pco6_b and ex1_g08_6) or (pos_if_nco6_b and ex1_g08_6_b) );-- same as neg +shovb: ex1_sh_ovf_b <= not( (pos_if_pco6_b and ex1_g08_6) or (pos_if_nco6_b and ex1_g08_6_b) );-- same as neg +shun: ex1_sh_unf_x <= not( (unf_if_pco6_b and ex1_g08_6) or (unf_if_nco6_b and ex1_g08_6_b) ); +shan: ex1_bsha_neg <= not( ex1_bsha_pos ); +shan2: ex1_bsha_neg_o <= not( ex1_bsha_pos ); +shov: ex1_sh_ovf <= not( ex1_sh_ovf_b ); + + + --==------------------------------------------------------------------------------- + --== decode for first level shifter (0/1/2/3) + --==------------------------------------------------------------------------------- + +d1_0: ex1_lvl1_shdcd000_b <= not( ex1_bsha_12_b and ex1_bsha_13_b ); +d1_1: ex1_lvl1_shdcd001_b <= not( ex1_bsha_12_b and ex1_bsha_13 ); +d1_2: ex1_lvl1_shdcd002_b <= not( ex1_bsha_12 and ex1_bsha_13_b ); +d1_3: ex1_lvl1_shdcd003_b <= not( ex1_bsha_12 and ex1_bsha_13 ); + + --==------------------------------------------------------------------------------- + --== decode for second level shifter (0/4/8/12) + --==------------------------------------------------------------------------------- + -- ex1_lvl2_shdcd000 <= not ex1_bsha(10) and not ex1_bsha(11) ; + -- ex1_lvl2_shdcd004 <= not ex1_bsha(10) and ex1_bsha(11) ; + -- ex1_lvl2_shdcd008 <= ex1_bsha(10) and not ex1_bsha(11) ; + -- ex1_lvl2_shdcd012 <= ex1_bsha(10) and ex1_bsha(11) ; + ---------------------------------------------------------------------- + -- p10 (11) ci11 DCD p10 (11) ci11 DCD + -- !p k 0 00 !p k 0 00 + -- !P p 0 01 p g 0 00 + -- !p g 0 10 P p 1 00 + -- + -- p k 0 10 !P p 0 01 + -- P p 0 11 !p k 1 01 + -- p g 0 00 p g 1 01 + -- + -- !p k 1 01 !p g 0 10 + -- !P p 1 10 p k 0 10 + -- !p g 1 11 !P p 1 10 + -- + -- p k 1 11 P p 0 11 + -- P p 1 00 !p g 1 11 + -- p g 1 01 p k 1 11 + +d2_0pg0: ex1_lv2_0pg0_b <= not( ex1_lv2_p10_b and ex1_lv2_g11 and ex1_lv2_ci11n_en ); +d2_0pg1: ex1_lv2_0pg1_b <= not( ex1_lv2_p10_b and ex1_lv2_g11 and ex1_lv2_ci11p_en ); +d2_0pk0: ex1_lv2_0pk0_b <= not( ex1_lv2_p10_b and ex1_lv2_k11 and ex1_lv2_ci11n_en ); +d2_0pk1: ex1_lv2_0pk1_b <= not( ex1_lv2_p10_b and ex1_lv2_k11 and ex1_lv2_ci11p_en ); +d2_0pp0: ex1_lv2_0pp0_b <= not( ex1_lv2_p10_b and ex1_lv2_p11 and ex1_lv2_ci11n_en ); +d2_0pp1: ex1_lv2_0pp1_b <= not( ex1_lv2_p10_b and ex1_lv2_p11 and ex1_lv2_ci11p_en ); +d2_1pg0: ex1_lv2_1pg0_b <= not( ex1_lv2_p10 and ex1_lv2_g11 and ex1_lv2_ci11n_en ); +d2_1pg1: ex1_lv2_1pg1_b <= not( ex1_lv2_p10 and ex1_lv2_g11 and ex1_lv2_ci11p_en ); +d2_1pk0: ex1_lv2_1pk0_b <= not( ex1_lv2_p10 and ex1_lv2_k11 and ex1_lv2_ci11n_en ); +d2_1pk1: ex1_lv2_1pk1_b <= not( ex1_lv2_p10 and ex1_lv2_k11 and ex1_lv2_ci11p_en ); +d2_1pp0: ex1_lv2_1pp0_b <= not( ex1_lv2_p10 and ex1_lv2_p11 and ex1_lv2_ci11n_en ); +d2_1pp1: ex1_lv2_1pp1_b <= not( ex1_lv2_p10 and ex1_lv2_p11 and ex1_lv2_ci11p_en ); + +d2_0: ex1_lv2_shdcd000 <= not( ex1_lv2_0pk0_b and ex1_lv2_1pg0_b and ex1_lv2_1pp1_b ); +d2_1: ex1_lv2_shdcd004 <= not( ex1_lv2_0pp0_b and ex1_lv2_0pk1_b and ex1_lv2_1pg1_b ); +d2_2: ex1_lv2_shdcd008 <= not( ex1_lv2_0pg0_b and ex1_lv2_1pk0_b and ex1_lv2_0pp1_b ); +d2_3: ex1_lv2_shdcd012 <= not( ex1_lv2_1pp0_b and ex1_lv2_0pg1_b and ex1_lv2_1pk1_b ); + +i2_0: ex1_lvl2_shdcd000_b <= not ex1_lv2_shdcd000; +i2_1: ex1_lvl2_shdcd004_b <= not ex1_lv2_shdcd004; +i2_2: ex1_lvl2_shdcd008_b <= not ex1_lv2_shdcd008; +i2_3: ex1_lvl2_shdcd012_b <= not ex1_lv2_shdcd012; + +ii2_0: ex1_lvl2_shdcd000 <= not ex1_lvl2_shdcd000_b; +ii2_1: ex1_lvl2_shdcd004 <= not ex1_lvl2_shdcd004_b; +ii2_2: ex1_lvl2_shdcd008 <= not ex1_lvl2_shdcd008_b; +ii2_3: ex1_lvl2_shdcd012 <= not ex1_lvl2_shdcd012_b; + + + + --==-------------------------------------------- + --== decode to control ex2 shifting + --==-------------------------------------------- + +i3_6: ex1_bsha_6_b <= not ex1_bsha_6 ; +i3_7: ex1_bsha_7_b <= not ex1_bsha_7 ; +i3_8: ex1_bsha_8_b <= not ex1_bsha_8 ; +i3_9: ex1_bsha_9_b <= not ex1_bsha_9 ; + +d67_0: ex1_67_dcd00_b <= not( ex1_bsha_6_b and ex1_bsha_7_b ); +d67_1: ex1_67_dcd01_b <= not( ex1_bsha_6_b and ex1_bsha_7 ); +d67_2: ex1_67_dcd10_b <= not( ex1_bsha_6 and ex1_bsha_7_b ); +d67_3: ex1_67_dcd11_b <= not( ex1_bsha_6 and ex1_bsha_7 and ex1_bsha_neg ); + +d89_0: ex1_89_dcd00_b <= not( ex1_bsha_8_b and ex1_bsha_9_b and ex1_sel_special_b ); +d89_1: ex1_89_dcd01_b <= not( ex1_bsha_8_b and ex1_bsha_9 and ex1_sel_special_b ); +d89_2: ex1_89_dcd10_b <= not( ex1_bsha_8 and ex1_bsha_9_b and ex1_sel_special_b ); +d89_3: ex1_89_dcd11_b <= not( ex1_bsha_8 and ex1_bsha_9 and ex1_sel_special_b ); + +d3_00: ex1_lvl3_shdcd000 <= not( ex1_67_dcd00_b or ex1_89_dcd00_b );-- 0000 +000 +d3_01: ex1_lvl3_shdcd016 <= not( ex1_67_dcd00_b or ex1_89_dcd01_b );-- 0001 +016 +d3_02: ex1_lvl3_shdcd032 <= not( ex1_67_dcd00_b or ex1_89_dcd10_b );-- 0010 +032 +d3_03: ex1_lvl3_shdcd048 <= not( ex1_67_dcd00_b or ex1_89_dcd11_b );-- 0011 +048 +d3_04: ex1_lvl3_shdcd064 <= not( ex1_67_dcd01_b or ex1_89_dcd00_b );-- 0100 +064 +d3_05: ex1_lvl3_shdcd080 <= not( ex1_67_dcd01_b or ex1_89_dcd01_b );-- 0101 +080 +d3_06: ex1_lvl3_shdcd096 <= not( ex1_67_dcd01_b or ex1_89_dcd10_b );-- 0110 +096 +d3_07: ex1_lvl3_shdcd112 <= not( ex1_67_dcd01_b or ex1_89_dcd11_b );-- 0111 +112 +d3_08: ex1_lvl3_shdcd128 <= not( ex1_67_dcd10_b or ex1_89_dcd00_b );-- 1000 +128 +d3_09: ex1_lvl3_shdcd144 <= not( ex1_67_dcd10_b or ex1_89_dcd01_b );-- 1001 +144 +d3_10: ex1_lvl3_shdcd160 <= not( ex1_67_dcd10_b or ex1_89_dcd10_b );-- 1010 +160 +d3_11: ex1_lvl3_shdcd176 <= not( ex1_67_dcd10_b or ex1_89_dcd11_b );-- 1011 +d3_12: ex1_lvl3_shdcd192 <= not( ex1_67_dcd11_b or ex1_89_dcd00_b );-- 1100 -064 +d3_13: ex1_lvl3_shdcd208 <= not( ex1_67_dcd11_b or ex1_89_dcd01_b );-- 1101 -048 +d3_14: ex1_lvl3_shdcd224 <= not( ex1_67_dcd11_b or ex1_89_dcd10_b );-- 1110 -032 +d3_15: ex1_lvl3_shdcd240 <= not( ex1_67_dcd11_b or ex1_89_dcd11_b );-- 1111 -016 + + +end; -- fuq_alg_add ARCHITECTURE diff --git a/rel/src/vhdl/work/fuq_alg_bypmux.vhdl b/rel/src/vhdl/work/fuq_alg_bypmux.vhdl new file mode 100644 index 0000000..095882f --- /dev/null +++ b/rel/src/vhdl/work/fuq_alg_bypmux.vhdl @@ -0,0 +1,113 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + + +entity fuq_alg_bypmux is +generic( expand_type : integer := 2 ); -- 0 - ibm tech, 1 - other ); +port( + ----------- BYPASS CONTROLS ----------------- + ex2_byp_sel_byp_neg :in std_ulogic; + ex2_byp_sel_byp_pos :in std_ulogic; + ex2_byp_sel_neg :in std_ulogic; + ex2_byp_sel_pos :in std_ulogic; + ex2_prd_sel_neg_hi :in std_ulogic; + ex2_prd_sel_neg_lo :in std_ulogic; + ex2_prd_sel_neg_lohi :in std_ulogic; + ex2_prd_sel_pos_hi :in std_ulogic; + ex2_prd_sel_pos_lo :in std_ulogic; + ex2_prd_sel_pos_lohi :in std_ulogic; + + ----------- BYPASS DATA ----------------- + ex2_sh_lvl3 :in std_ulogic_vector(0 to 162); + f_fmt_ex2_pass_frac :in std_ulogic_vector(0 to 52); + + ---------- BYPASS OUTPUT --------------- + f_alg_ex2_res :out std_ulogic_vector(0 to 162) +); + + + +end fuq_alg_bypmux; -- ENTITY + +architecture fuq_alg_bypmux of fuq_alg_bypmux is + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal m0_b, m1_b :std_ulogic_vector(0 to 162); + signal ex2_sh_lvl3_b :std_ulogic_vector(0 to 162); + signal f_fmt_ex2_pass_frac_b :std_ulogic_vector(0 to 52); + + +begin + + + + +i0: ex2_sh_lvl3_b(0 to 162) <= not( ex2_sh_lvl3(0 to 162) ); +i1: f_fmt_ex2_pass_frac_b(0 to 52) <= not( f_fmt_ex2_pass_frac(0 to 52) ); + +---------------------------------------------------------------- + +m0_000: m0_b(0 to 52) <= not( ( (0 to 52=> ex2_byp_sel_pos) and ex2_sh_lvl3 (0 to 52) ) or + ( (0 to 52=> ex2_byp_sel_neg) and ex2_sh_lvl3_b (0 to 52) ) ); + +m1_000: m1_b(0 to 52) <= not( ( (0 to 52=> ex2_byp_sel_byp_pos) and f_fmt_ex2_pass_frac (0 to 52) ) or + ( (0 to 52=> ex2_byp_sel_byp_neg) and f_fmt_ex2_pass_frac_b(0 to 52) ) ); +----------------------------------------------------------------- + +m0_053: m0_b(53 to 98) <= not( (53 to 98=> ex2_prd_sel_pos_hi) and ex2_sh_lvl3 (53 to 98) ); +m1_053: m1_b(53 to 98) <= not( (53 to 98=> ex2_prd_sel_neg_hi) and ex2_sh_lvl3_b(53 to 98) ); + +----------------------------------------------------------------- + +m0_099: m0_b(99 to 130) <= not( (99 to 130=> ex2_prd_sel_pos_lohi) and ex2_sh_lvl3 (99 to 130) ); +m1_099: m1_b(99 to 130) <= not( (99 to 130=> ex2_prd_sel_neg_lohi) and ex2_sh_lvl3_b(99 to 130) ); + +----------------------------------------------------------------- + +m0_131: m0_b(131 to 162) <= not( (131 to 162=> ex2_prd_sel_pos_lo) and ex2_sh_lvl3 (131 to 162) ); +m1_131: m1_b(131 to 162) <= not( (131 to 162=> ex2_prd_sel_neg_lo) and ex2_sh_lvl3_b(131 to 162) ); + +----------------------------------------------------------------- + +mx: f_alg_ex2_res(0 to 162) <= not( m0_b(0 to 162) and m1_b(0 to 162 ) ); + +end; -- fuq_alg_bypmux ARCHITECTURE diff --git a/rel/src/vhdl/work/fuq_alg_or16.vhdl b/rel/src/vhdl/work/fuq_alg_or16.vhdl new file mode 100644 index 0000000..1c9e0ed --- /dev/null +++ b/rel/src/vhdl/work/fuq_alg_or16.vhdl @@ -0,0 +1,185 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + +entity fuq_alg_or16 is +generic( expand_type : integer := 2 ); -- 0 - ibm tech, 1 - other ); +port( + ex2_sh_lvl2 :in std_ulogic_vector(0 to 67) ; + ex2_sticky_or16 :out std_ulogic_vector(0 to 4) +); + + + +end fuq_alg_or16; -- ENTITY + +architecture fuq_alg_or16 of fuq_alg_or16 is + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + signal ex2_g1o2_b :std_ulogic_vector(0 to 7); + signal ex2_g2o2_b :std_ulogic_vector(0 to 7); + signal ex2_g3o2_b :std_ulogic_vector(0 to 7); + signal ex2_g4o2_b :std_ulogic_vector(0 to 7); + signal ex2_g1o4 :std_ulogic_vector(0 to 3); + signal ex2_g2o4 :std_ulogic_vector(0 to 3); + signal ex2_g3o4 :std_ulogic_vector(0 to 3); + signal ex2_g4o4 :std_ulogic_vector(0 to 3); + signal ex2_g0o8_b :std_ulogic_vector(0 to 1); + signal ex2_g1o8_b :std_ulogic_vector(0 to 1); + signal ex2_g2o8_b :std_ulogic_vector(0 to 1); + signal ex2_g3o8_b :std_ulogic_vector(0 to 1); + signal ex2_g4o8_b :std_ulogic_vector(0 to 1); + signal ex2_o16, ex2_o16_b :std_ulogic_vector(0 to 4); + + + + +begin + +------------------------------------------------------------ +-- UnMapped origianl equations +------------------------------------------------------------ +-- ex2_sticky_or16(4) <= OR( ex2_sh_lvl2[52:67] ); +-- ex2_sticky_or16(3) <= OR( ex2_sh_lvl2[36:51] ); +-- ex2_sticky_or16(2) <= OR( ex2_sh_lvl2[20:35] ); +-- ex2_sticky_or16(1) <= OR( ex2_sh_lvl2[ 4:19] ); +-- ex2_sticky_or16(0) <= OR( ex2_sh_lvl2[ 0: 3] ); +----------------------------------------------------------- + + +g1o2_0: ex2_g1o2_b(0) <= not( ex2_sh_lvl2( 4) or ex2_sh_lvl2( 5) ); +g1o2_1: ex2_g1o2_b(1) <= not( ex2_sh_lvl2( 6) or ex2_sh_lvl2( 7) ); +g1o2_2: ex2_g1o2_b(2) <= not( ex2_sh_lvl2( 8) or ex2_sh_lvl2( 9) ); +g1o2_3: ex2_g1o2_b(3) <= not( ex2_sh_lvl2(10) or ex2_sh_lvl2(11) ); +g1o2_4: ex2_g1o2_b(4) <= not( ex2_sh_lvl2(12) or ex2_sh_lvl2(13) ); +g1o2_5: ex2_g1o2_b(5) <= not( ex2_sh_lvl2(14) or ex2_sh_lvl2(15) ); +g1o2_6: ex2_g1o2_b(6) <= not( ex2_sh_lvl2(16) or ex2_sh_lvl2(17) ); +g1o2_7: ex2_g1o2_b(7) <= not( ex2_sh_lvl2(18) or ex2_sh_lvl2(19) ); + +g2o2_0: ex2_g2o2_b(0) <= not( ex2_sh_lvl2(20) or ex2_sh_lvl2(21) ); +g2o2_1: ex2_g2o2_b(1) <= not( ex2_sh_lvl2(22) or ex2_sh_lvl2(23) ); +g2o2_2: ex2_g2o2_b(2) <= not( ex2_sh_lvl2(24) or ex2_sh_lvl2(25) ); +g2o2_3: ex2_g2o2_b(3) <= not( ex2_sh_lvl2(26) or ex2_sh_lvl2(27) ); +g2o2_4: ex2_g2o2_b(4) <= not( ex2_sh_lvl2(28) or ex2_sh_lvl2(29) ); +g2o2_5: ex2_g2o2_b(5) <= not( ex2_sh_lvl2(30) or ex2_sh_lvl2(31) ); +g2o2_6: ex2_g2o2_b(6) <= not( ex2_sh_lvl2(32) or ex2_sh_lvl2(33) ); +g2o2_7: ex2_g2o2_b(7) <= not( ex2_sh_lvl2(34) or ex2_sh_lvl2(35) ); + +g3o2_0: ex2_g3o2_b(0) <= not( ex2_sh_lvl2(36) or ex2_sh_lvl2(37) ); +g3o2_1: ex2_g3o2_b(1) <= not( ex2_sh_lvl2(38) or ex2_sh_lvl2(39) ); +g3o2_2: ex2_g3o2_b(2) <= not( ex2_sh_lvl2(40) or ex2_sh_lvl2(41) ); +g3o2_3: ex2_g3o2_b(3) <= not( ex2_sh_lvl2(42) or ex2_sh_lvl2(43) ); +g3o2_4: ex2_g3o2_b(4) <= not( ex2_sh_lvl2(44) or ex2_sh_lvl2(45) ); +g3o2_5: ex2_g3o2_b(5) <= not( ex2_sh_lvl2(46) or ex2_sh_lvl2(47) ); +g3o2_6: ex2_g3o2_b(6) <= not( ex2_sh_lvl2(48) or ex2_sh_lvl2(49) ); +g3o2_7: ex2_g3o2_b(7) <= not( ex2_sh_lvl2(50) or ex2_sh_lvl2(51) ); + +g4o2_0: ex2_g4o2_b(0) <= not( ex2_sh_lvl2(52) or ex2_sh_lvl2(53) ); +g4o2_1: ex2_g4o2_b(1) <= not( ex2_sh_lvl2(54) or ex2_sh_lvl2(55) ); +g4o2_2: ex2_g4o2_b(2) <= not( ex2_sh_lvl2(56) or ex2_sh_lvl2(57) ); +g4o2_3: ex2_g4o2_b(3) <= not( ex2_sh_lvl2(58) or ex2_sh_lvl2(59) ); +g4o2_4: ex2_g4o2_b(4) <= not( ex2_sh_lvl2(60) or ex2_sh_lvl2(61) ); +g4o2_5: ex2_g4o2_b(5) <= not( ex2_sh_lvl2(62) or ex2_sh_lvl2(63) ); +g4o2_6: ex2_g4o2_b(6) <= not( ex2_sh_lvl2(64) or ex2_sh_lvl2(65) ); +g4o2_7: ex2_g4o2_b(7) <= not( ex2_sh_lvl2(66) or ex2_sh_lvl2(67) ); + +-------------------------------------------- + +g1o4_0: ex2_g1o4(0) <= not(ex2_g1o2_b(0) and ex2_g1o2_b(1) ); +g1o4_1: ex2_g1o4(1) <= not(ex2_g1o2_b(2) and ex2_g1o2_b(3) ); +g1o4_2: ex2_g1o4(2) <= not(ex2_g1o2_b(4) and ex2_g1o2_b(5) ); +g1o4_3: ex2_g1o4(3) <= not(ex2_g1o2_b(6) and ex2_g1o2_b(7) ); + +g2o4_0: ex2_g2o4(0) <= not(ex2_g2o2_b(0) and ex2_g2o2_b(1) ); +g2o4_1: ex2_g2o4(1) <= not(ex2_g2o2_b(2) and ex2_g2o2_b(3) ); +g2o4_2: ex2_g2o4(2) <= not(ex2_g2o2_b(4) and ex2_g2o2_b(5) ); +g2o4_3: ex2_g2o4(3) <= not(ex2_g2o2_b(6) and ex2_g2o2_b(7) ); + +g3o4_0: ex2_g3o4(0) <= not(ex2_g3o2_b(0) and ex2_g3o2_b(1) ); +g3o4_1: ex2_g3o4(1) <= not(ex2_g3o2_b(2) and ex2_g3o2_b(3) ); +g3o4_2: ex2_g3o4(2) <= not(ex2_g3o2_b(4) and ex2_g3o2_b(5) ); +g3o4_3: ex2_g3o4(3) <= not(ex2_g3o2_b(6) and ex2_g3o2_b(7) ); + +g4o4_0: ex2_g4o4(0) <= not(ex2_g4o2_b(0) and ex2_g4o2_b(1) ); +g4o4_1: ex2_g4o4(1) <= not(ex2_g4o2_b(2) and ex2_g4o2_b(3) ); +g4o4_2: ex2_g4o4(2) <= not(ex2_g4o2_b(4) and ex2_g4o2_b(5) ); +g4o4_3: ex2_g4o4(3) <= not(ex2_g4o2_b(6) and ex2_g4o2_b(7) ); + +----------------------------------------------- + +g0o8_0: ex2_g0o8_b(0) <= not( ex2_sh_lvl2( 0) or ex2_sh_lvl2( 1) ); +g0o8_1: ex2_g0o8_b(1) <= not( ex2_sh_lvl2( 2) or ex2_sh_lvl2( 3) ); + +g1o8_0: ex2_g1o8_b(0) <= not( ex2_g1o4(0) or ex2_g1o4(1) ); +g1o8_1: ex2_g1o8_b(1) <= not( ex2_g1o4(2) or ex2_g1o4(3) ); + +g2o8_0: ex2_g2o8_b(0) <= not( ex2_g2o4(0) or ex2_g2o4(1) ); +g2o8_1: ex2_g2o8_b(1) <= not( ex2_g2o4(2) or ex2_g2o4(3) ); + +g3o8_0: ex2_g3o8_b(0) <= not( ex2_g3o4(0) or ex2_g3o4(1) ); +g3o8_1: ex2_g3o8_b(1) <= not( ex2_g3o4(2) or ex2_g3o4(3) ); + +g4o8_0: ex2_g4o8_b(0) <= not( ex2_g4o4(0) or ex2_g4o4(1) ); +g4o8_1: ex2_g4o8_b(1) <= not( ex2_g4o4(2) or ex2_g4o4(3) ); + +-------------------------------------------------- + +g0o16: ex2_o16(0) <= not(ex2_g0o8_b(0) and ex2_g0o8_b(1) ); +g1o16: ex2_o16(1) <= not(ex2_g1o8_b(0) and ex2_g1o8_b(1) ); +g2o16: ex2_o16(2) <= not(ex2_g2o8_b(0) and ex2_g2o8_b(1) ); +g3o16: ex2_o16(3) <= not(ex2_g3o8_b(0) and ex2_g3o8_b(1) ); +g4o16: ex2_o16(4) <= not(ex2_g4o8_b(0) and ex2_g4o8_b(1) ); + +-------------------------------------------------- + +g0o16i: ex2_o16_b(0) <= not( ex2_o16(0) ); +g1o16i: ex2_o16_b(1) <= not( ex2_o16(1) ); +g2o16i: ex2_o16_b(2) <= not( ex2_o16(2) ); +g3o16i: ex2_o16_b(3) <= not( ex2_o16(3) ); +g4o16i: ex2_o16_b(4) <= not( ex2_o16(4) ); + +-------------------------------------------------- + +g0o16ii: ex2_sticky_or16(0) <= not( ex2_o16_b(0) ); +g1o16ii: ex2_sticky_or16(1) <= not( ex2_o16_b(1) ); +g2o16ii: ex2_sticky_or16(2) <= not( ex2_o16_b(2) ); +g3o16ii: ex2_sticky_or16(3) <= not( ex2_o16_b(3) ); +g4o16ii: ex2_sticky_or16(4) <= not( ex2_o16_b(4) ); + +end; -- fuq_alg_or16 ARCHITECTURE diff --git a/rel/src/vhdl/work/fuq_alg_sh16.vhdl b/rel/src/vhdl/work/fuq_alg_sh16.vhdl new file mode 100644 index 0000000..f7a1dc5 --- /dev/null +++ b/rel/src/vhdl/work/fuq_alg_sh16.vhdl @@ -0,0 +1,972 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + + +entity fuq_alg_sh16 is +generic( expand_type : integer := 2 ); -- 0 - ibm tech, 1 - other ); +port( + ----------- SHIFT CONTROLS ----------------- + ex2_lvl3_shdcd000 :in std_ulogic; + ex2_lvl3_shdcd016 :in std_ulogic; + ex2_lvl3_shdcd032 :in std_ulogic; + ex2_lvl3_shdcd048 :in std_ulogic; + ex2_lvl3_shdcd064 :in std_ulogic; + ex2_lvl3_shdcd080 :in std_ulogic; + ex2_lvl3_shdcd096 :in std_ulogic; + ex2_lvl3_shdcd112 :in std_ulogic; + ex2_lvl3_shdcd128 :in std_ulogic; + ex2_lvl3_shdcd144 :in std_ulogic; + ex2_lvl3_shdcd160 :in std_ulogic; + ex2_lvl3_shdcd192 :in std_ulogic; + ex2_lvl3_shdcd208 :in std_ulogic; + ex2_lvl3_shdcd224 :in std_ulogic; + ex2_lvl3_shdcd240 :in std_ulogic; + ex2_sel_special :in std_ulogic; + + ----------- SHIFT DATA ----------------- + ex2_sh_lvl2 :in std_ulogic_vector(0 to 67) ; + + ---------- SHIFT OUTPUT --------------- + ex2_sh16_162 :out std_ulogic ; + ex2_sh16_163 :out std_ulogic ; + ex2_sh_lvl3 :out std_ulogic_vector(0 to 162) +); + + + +end fuq_alg_sh16; -- ENTITY + +architecture fuq_alg_sh16 of fuq_alg_sh16 is + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal ex2_sh16_r1_b, ex2_sh16_r2_b, ex2_sh16_r3_b : std_ulogic_vector(0 to 162); + signal ex2_special :std_ulogic_vector(99 to 162); + + + signal cpx_spc_b :std_ulogic; + signal cpx_000_b :std_ulogic; + signal cpx_016_b :std_ulogic; + signal cpx_032_b :std_ulogic; + signal cpx_048_b :std_ulogic; + signal cpx_064_b :std_ulogic; + signal cpx_080_b :std_ulogic; + signal cpx_096_b :std_ulogic; + signal cpx_112_b :std_ulogic; + signal cpx_128_b :std_ulogic; + signal cpx_144_b :std_ulogic; + signal cpx_160_b :std_ulogic; + signal cpx_192_b :std_ulogic; + signal cpx_208_b :std_ulogic; + signal cpx_224_b :std_ulogic; + signal cpx_240_b :std_ulogic; + signal cp1_spc :std_ulogic; + signal cp1_000 :std_ulogic; + signal cp1_016 :std_ulogic; + signal cp1_032 :std_ulogic; + signal cp1_048 :std_ulogic; + signal cp1_064 :std_ulogic; + signal cp1_080 :std_ulogic; + signal cp1_096 :std_ulogic; + signal cp1_112 :std_ulogic; + signal cp1_128 :std_ulogic; + signal cp1_144 :std_ulogic; + signal cp1_160 :std_ulogic; + signal cp1_192 :std_ulogic; + signal cp1_208 :std_ulogic; + signal cp1_224 :std_ulogic; + signal cp1_240 :std_ulogic; + signal cp2_spc :std_ulogic; + signal cp2_000 :std_ulogic; + signal cp2_016 :std_ulogic; + signal cp2_032 :std_ulogic; + signal cp2_048 :std_ulogic; + signal cp2_064 :std_ulogic; + signal cp2_080 :std_ulogic; + signal cp2_096 :std_ulogic; + signal cp2_112 :std_ulogic; + signal cp2_128 :std_ulogic; + signal cp2_144 :std_ulogic; + signal cp2_208 :std_ulogic; + signal cp2_224 :std_ulogic; + signal cp2_240 :std_ulogic; + signal cp3_spc :std_ulogic; + signal cp3_000 :std_ulogic; + signal cp3_016 :std_ulogic; + signal cp3_032 :std_ulogic; + signal cp3_048 :std_ulogic; + signal cp3_064 :std_ulogic; + signal cp3_080 :std_ulogic; + signal cp3_096 :std_ulogic; + signal cp3_112 :std_ulogic; + signal cp3_128 :std_ulogic; + signal cp3_224 :std_ulogic; + signal cp3_240 :std_ulogic; + signal cp4_spc :std_ulogic; + signal cp4_000 :std_ulogic; + signal cp4_016 :std_ulogic; + signal cp4_032 :std_ulogic; + signal cp4_048 :std_ulogic; + signal cp4_064 :std_ulogic; + signal cp4_080 :std_ulogic; + signal cp4_096 :std_ulogic; + signal cp4_112 :std_ulogic; + signal cp4_240 :std_ulogic; + signal cp5_spc :std_ulogic; + signal cp5_000 :std_ulogic; + signal cp5_016 :std_ulogic; + signal cp5_032 :std_ulogic; + signal cp5_048 :std_ulogic; + signal cp5_064 :std_ulogic; + signal cp5_080 :std_ulogic; + signal cp5_096 :std_ulogic; +signal ex2_sh16_r1_162_b, ex2_sh16_r2_162_b, ex2_sh16_r3_162_b :std_ulogic; +signal ex2_sh16_r1_163_b, ex2_sh16_r2_163_b, ex2_sh16_r3_163_b :std_ulogic; + + + + + +begin + + ex2_special(99 to 162) <= ex2_sh_lvl2(0 to 63); + + + + + +cxspcb: cpx_spc_b <= not ex2_sel_special ; +cx000b: cpx_000_b <= not ex2_lvl3_shdcd000 ; +cx016b: cpx_016_b <= not ex2_lvl3_shdcd016 ; +cx032b: cpx_032_b <= not ex2_lvl3_shdcd032 ; +cx048b: cpx_048_b <= not ex2_lvl3_shdcd048 ; +cx064b: cpx_064_b <= not ex2_lvl3_shdcd064 ; +cx080b: cpx_080_b <= not ex2_lvl3_shdcd080 ; +cx096b: cpx_096_b <= not ex2_lvl3_shdcd096 ; +cx112b: cpx_112_b <= not ex2_lvl3_shdcd112 ; +cx128b: cpx_128_b <= not ex2_lvl3_shdcd128 ; +cx144b: cpx_144_b <= not ex2_lvl3_shdcd144 ; +cx160b: cpx_160_b <= not ex2_lvl3_shdcd160 ; +cx192b: cpx_192_b <= not ex2_lvl3_shdcd192 ; +cx208b: cpx_208_b <= not ex2_lvl3_shdcd208 ; +cx224b: cpx_224_b <= not ex2_lvl3_shdcd224 ; +cx240b: cpx_240_b <= not ex2_lvl3_shdcd240 ; + + +c1_spc: cp1_spc <= not cpx_spc_b ; +c1_000: cp1_000 <= not cpx_000_b ; +c1_016: cp1_016 <= not cpx_016_b ; +c1_032: cp1_032 <= not cpx_032_b ; +c1_048: cp1_048 <= not cpx_048_b ; +c1_064: cp1_064 <= not cpx_064_b ; +c1_080: cp1_080 <= not cpx_080_b ; +c1_096: cp1_096 <= not cpx_096_b ; +c1_112: cp1_112 <= not cpx_112_b ; +c1_128: cp1_128 <= not cpx_128_b ; +c1_144: cp1_144 <= not cpx_144_b ; +c1_160: cp1_160 <= not cpx_160_b ; +c1_192: cp1_192 <= not cpx_192_b ; +c1_208: cp1_208 <= not cpx_208_b ; +c1_224: cp1_224 <= not cpx_224_b ; +c1_240: cp1_240 <= not cpx_240_b ; + +c2_spc: cp2_spc <= not cpx_spc_b ; +c2_000: cp2_000 <= not cpx_000_b ; +c2_016: cp2_016 <= not cpx_016_b ; +c2_032: cp2_032 <= not cpx_032_b ; +c2_048: cp2_048 <= not cpx_048_b ; +c2_064: cp2_064 <= not cpx_064_b ; +c2_080: cp2_080 <= not cpx_080_b ; +c2_096: cp2_096 <= not cpx_096_b ; +c2_112: cp2_112 <= not cpx_112_b ; +c2_128: cp2_128 <= not cpx_128_b ; +c2_144: cp2_144 <= not cpx_144_b ; +c2_208: cp2_208 <= not cpx_208_b ; +c2_224: cp2_224 <= not cpx_224_b ; +c2_240: cp2_240 <= not cpx_240_b ; + +c3_spc: cp3_spc <= not cpx_spc_b ; +c3_000: cp3_000 <= not cpx_000_b ; +c3_016: cp3_016 <= not cpx_016_b ; +c3_032: cp3_032 <= not cpx_032_b ; +c3_048: cp3_048 <= not cpx_048_b ; +c3_064: cp3_064 <= not cpx_064_b ; +c3_080: cp3_080 <= not cpx_080_b ; +c3_096: cp3_096 <= not cpx_096_b ; +c3_112: cp3_112 <= not cpx_112_b ; +c3_128: cp3_128 <= not cpx_128_b ; +c3_224: cp3_224 <= not cpx_224_b ; +c3_240: cp3_240 <= not cpx_240_b ; + +c4_spc: cp4_spc <= not cpx_spc_b ; +c4_000: cp4_000 <= not cpx_000_b ; +c4_016: cp4_016 <= not cpx_016_b ; +c4_032: cp4_032 <= not cpx_032_b ; +c4_048: cp4_048 <= not cpx_048_b ; +c4_064: cp4_064 <= not cpx_064_b ; +c4_080: cp4_080 <= not cpx_080_b ; +c4_096: cp4_096 <= not cpx_096_b ; +c4_112: cp4_112 <= not cpx_112_b ; +c4_240: cp4_240 <= not cpx_240_b ; + +c5_spc: cp5_spc <= not cpx_spc_b ; +c5_000: cp5_000 <= not cpx_000_b ; +c5_016: cp5_016 <= not cpx_016_b ; +c5_032: cp5_032 <= not cpx_032_b ; +c5_048: cp5_048 <= not cpx_048_b ; +c5_064: cp5_064 <= not cpx_064_b ; +c5_080: cp5_080 <= not cpx_080_b ; +c5_096: cp5_096 <= not cpx_096_b ; + + + + +--------------------------------------------------------------------- + +r1_000: ex2_sh16_r1_b(0) <= not( (cp1_192 and ex2_sh_lvl2(64) ) or (cp1_208 and ex2_sh_lvl2(48) ) ); +r1_001: ex2_sh16_r1_b(1) <= not( (cp1_192 and ex2_sh_lvl2(65) ) or (cp1_208 and ex2_sh_lvl2(49) ) ); +r1_002: ex2_sh16_r1_b(2) <= not( (cp1_192 and ex2_sh_lvl2(66) ) or (cp1_208 and ex2_sh_lvl2(50) ) ); +r1_003: ex2_sh16_r1_b(3) <= not( (cp1_192 and ex2_sh_lvl2(67) ) or (cp1_208 and ex2_sh_lvl2(51) ) ); +r1_004: ex2_sh16_r1_b(4) <= not( cp1_208 and ex2_sh_lvl2(52) ); +r1_005: ex2_sh16_r1_b(5) <= not( cp1_208 and ex2_sh_lvl2(53) ); +r1_006: ex2_sh16_r1_b(6) <= not( cp1_208 and ex2_sh_lvl2(54) ); +r1_007: ex2_sh16_r1_b(7) <= not( cp1_208 and ex2_sh_lvl2(55) ); +r1_008: ex2_sh16_r1_b(8) <= not( cp1_208 and ex2_sh_lvl2(56) ); +r1_009: ex2_sh16_r1_b(9) <= not( cp1_208 and ex2_sh_lvl2(57) ); +r1_010: ex2_sh16_r1_b(10) <= not( cp1_208 and ex2_sh_lvl2(58) ); +r1_011: ex2_sh16_r1_b(11) <= not( cp1_208 and ex2_sh_lvl2(59) ); +r1_012: ex2_sh16_r1_b(12) <= not( cp1_208 and ex2_sh_lvl2(60) ); +r1_013: ex2_sh16_r1_b(13) <= not( cp1_208 and ex2_sh_lvl2(61) ); +r1_014: ex2_sh16_r1_b(14) <= not( cp1_208 and ex2_sh_lvl2(62) ); +r1_015: ex2_sh16_r1_b(15) <= not( cp1_208 and ex2_sh_lvl2(63) ); + +r1_016: ex2_sh16_r1_b(16) <= not( (cp2_208 and ex2_sh_lvl2(64) ) or (cp2_224 and ex2_sh_lvl2(48) ) ); +r1_017: ex2_sh16_r1_b(17) <= not( (cp2_208 and ex2_sh_lvl2(65) ) or (cp2_224 and ex2_sh_lvl2(49) ) ); +r1_018: ex2_sh16_r1_b(18) <= not( (cp2_208 and ex2_sh_lvl2(66) ) or (cp2_224 and ex2_sh_lvl2(50) ) ); +r1_019: ex2_sh16_r1_b(19) <= not( (cp2_208 and ex2_sh_lvl2(67) ) or (cp2_224 and ex2_sh_lvl2(51) ) ); +r1_020: ex2_sh16_r1_b(20) <= not( cp2_224 and ex2_sh_lvl2(52) ); +r1_021: ex2_sh16_r1_b(21) <= not( cp2_224 and ex2_sh_lvl2(53) ); +r1_022: ex2_sh16_r1_b(22) <= not( cp2_224 and ex2_sh_lvl2(54) ); +r1_023: ex2_sh16_r1_b(23) <= not( cp2_224 and ex2_sh_lvl2(55) ); +r1_024: ex2_sh16_r1_b(24) <= not( cp2_224 and ex2_sh_lvl2(56) ); +r1_025: ex2_sh16_r1_b(25) <= not( cp2_224 and ex2_sh_lvl2(57) ); +r1_026: ex2_sh16_r1_b(26) <= not( cp2_224 and ex2_sh_lvl2(58) ); +r1_027: ex2_sh16_r1_b(27) <= not( cp2_224 and ex2_sh_lvl2(59) ); +r1_028: ex2_sh16_r1_b(28) <= not( cp2_224 and ex2_sh_lvl2(60) ); +r1_029: ex2_sh16_r1_b(29) <= not( cp2_224 and ex2_sh_lvl2(61) ); +r1_030: ex2_sh16_r1_b(30) <= not( cp2_224 and ex2_sh_lvl2(62) ); +r1_031: ex2_sh16_r1_b(31) <= not( cp2_224 and ex2_sh_lvl2(63) ); + +r1_032: ex2_sh16_r1_b(32) <= not( (cp3_224 and ex2_sh_lvl2(64) ) or (cp3_240 and ex2_sh_lvl2(48) ) ); +r1_033: ex2_sh16_r1_b(33) <= not( (cp3_224 and ex2_sh_lvl2(65) ) or (cp3_240 and ex2_sh_lvl2(49) ) ); +r1_034: ex2_sh16_r1_b(34) <= not( (cp3_224 and ex2_sh_lvl2(66) ) or (cp3_240 and ex2_sh_lvl2(50) ) ); +r1_035: ex2_sh16_r1_b(35) <= not( (cp3_224 and ex2_sh_lvl2(67) ) or (cp3_240 and ex2_sh_lvl2(51) ) ); +r1_036: ex2_sh16_r1_b(36) <= not( cp3_240 and ex2_sh_lvl2(52) ); +r1_037: ex2_sh16_r1_b(37) <= not( cp3_240 and ex2_sh_lvl2(53) ); +r1_038: ex2_sh16_r1_b(38) <= not( cp3_240 and ex2_sh_lvl2(54) ); +r1_039: ex2_sh16_r1_b(39) <= not( cp3_240 and ex2_sh_lvl2(55) ); +r1_040: ex2_sh16_r1_b(40) <= not( cp3_240 and ex2_sh_lvl2(56) ); +r1_041: ex2_sh16_r1_b(41) <= not( cp3_240 and ex2_sh_lvl2(57) ); +r1_042: ex2_sh16_r1_b(42) <= not( cp3_240 and ex2_sh_lvl2(58) ); +r1_043: ex2_sh16_r1_b(43) <= not( cp3_240 and ex2_sh_lvl2(59) ); +r1_044: ex2_sh16_r1_b(44) <= not( cp3_240 and ex2_sh_lvl2(60) ); +r1_045: ex2_sh16_r1_b(45) <= not( cp3_240 and ex2_sh_lvl2(61) ); +r1_046: ex2_sh16_r1_b(46) <= not( cp3_240 and ex2_sh_lvl2(62) ); +r1_047: ex2_sh16_r1_b(47) <= not( cp3_240 and ex2_sh_lvl2(63) ); + +r1_048: ex2_sh16_r1_b(48) <= not( (cp4_240 and ex2_sh_lvl2(64) ) or (cp4_000 and ex2_sh_lvl2(48) ) ); +r1_049: ex2_sh16_r1_b(49) <= not( (cp4_240 and ex2_sh_lvl2(65) ) or (cp4_000 and ex2_sh_lvl2(49) ) ); +r1_050: ex2_sh16_r1_b(50) <= not( (cp4_240 and ex2_sh_lvl2(66) ) or (cp4_000 and ex2_sh_lvl2(50) ) ); +r1_051: ex2_sh16_r1_b(51) <= not( (cp4_240 and ex2_sh_lvl2(67) ) or (cp4_000 and ex2_sh_lvl2(51) ) ); +r1_052: ex2_sh16_r1_b(52) <= not( cp4_000 and ex2_sh_lvl2(52) ); +r1_053: ex2_sh16_r1_b(53) <= not( cp4_000 and ex2_sh_lvl2(53) ); +r1_054: ex2_sh16_r1_b(54) <= not( cp4_000 and ex2_sh_lvl2(54) ); +r1_055: ex2_sh16_r1_b(55) <= not( cp4_000 and ex2_sh_lvl2(55) ); +r1_056: ex2_sh16_r1_b(56) <= not( cp4_000 and ex2_sh_lvl2(56) ); +r1_057: ex2_sh16_r1_b(57) <= not( cp4_000 and ex2_sh_lvl2(57) ); +r1_058: ex2_sh16_r1_b(58) <= not( cp4_000 and ex2_sh_lvl2(58) ); +r1_059: ex2_sh16_r1_b(59) <= not( cp4_000 and ex2_sh_lvl2(59) ); +r1_060: ex2_sh16_r1_b(60) <= not( cp4_000 and ex2_sh_lvl2(60) ); +r1_061: ex2_sh16_r1_b(61) <= not( cp4_000 and ex2_sh_lvl2(61) ); +r1_062: ex2_sh16_r1_b(62) <= not( cp4_000 and ex2_sh_lvl2(62) ); +r1_063: ex2_sh16_r1_b(63) <= not( cp4_000 and ex2_sh_lvl2(63) ); + +r1_064: ex2_sh16_r1_b(64) <= not( (cp5_000 and ex2_sh_lvl2(64) ) or (cp4_016 and ex2_sh_lvl2(48) ) ); +r1_065: ex2_sh16_r1_b(65) <= not( (cp5_000 and ex2_sh_lvl2(65) ) or (cp4_016 and ex2_sh_lvl2(49) ) ); +r1_066: ex2_sh16_r1_b(66) <= not( (cp5_000 and ex2_sh_lvl2(66) ) or (cp4_016 and ex2_sh_lvl2(50) ) ); +r1_067: ex2_sh16_r1_b(67) <= not( (cp5_000 and ex2_sh_lvl2(67) ) or (cp4_016 and ex2_sh_lvl2(51) ) ); +r1_068: ex2_sh16_r1_b(68) <= not( cp4_016 and ex2_sh_lvl2(52) ); +r1_069: ex2_sh16_r1_b(69) <= not( cp4_016 and ex2_sh_lvl2(53) ); +r1_070: ex2_sh16_r1_b(70) <= not( cp4_016 and ex2_sh_lvl2(54) ); +r1_071: ex2_sh16_r1_b(71) <= not( cp4_016 and ex2_sh_lvl2(55) ); +r1_072: ex2_sh16_r1_b(72) <= not( cp4_016 and ex2_sh_lvl2(56) ); +r1_073: ex2_sh16_r1_b(73) <= not( cp4_016 and ex2_sh_lvl2(57) ); +r1_074: ex2_sh16_r1_b(74) <= not( cp4_016 and ex2_sh_lvl2(58) ); +r1_075: ex2_sh16_r1_b(75) <= not( cp4_016 and ex2_sh_lvl2(59) ); +r1_076: ex2_sh16_r1_b(76) <= not( cp4_016 and ex2_sh_lvl2(60) ); +r1_077: ex2_sh16_r1_b(77) <= not( cp4_016 and ex2_sh_lvl2(61) ); +r1_078: ex2_sh16_r1_b(78) <= not( cp4_016 and ex2_sh_lvl2(62) ); +r1_079: ex2_sh16_r1_b(79) <= not( cp4_016 and ex2_sh_lvl2(63) ); + +r1_080: ex2_sh16_r1_b(80) <= not( (cp5_016 and ex2_sh_lvl2(64) ) or (cp4_032 and ex2_sh_lvl2(48) ) ); +r1_081: ex2_sh16_r1_b(81) <= not( (cp5_016 and ex2_sh_lvl2(65) ) or (cp4_032 and ex2_sh_lvl2(49) ) ); +r1_082: ex2_sh16_r1_b(82) <= not( (cp5_016 and ex2_sh_lvl2(66) ) or (cp4_032 and ex2_sh_lvl2(50) ) ); +r1_083: ex2_sh16_r1_b(83) <= not( (cp5_016 and ex2_sh_lvl2(67) ) or (cp4_032 and ex2_sh_lvl2(51) ) ); +r1_084: ex2_sh16_r1_b(84) <= not( cp4_032 and ex2_sh_lvl2(52) ); +r1_085: ex2_sh16_r1_b(85) <= not( cp4_032 and ex2_sh_lvl2(53) ); +r1_086: ex2_sh16_r1_b(86) <= not( cp4_032 and ex2_sh_lvl2(54) ); +r1_087: ex2_sh16_r1_b(87) <= not( cp4_032 and ex2_sh_lvl2(55) ); +r1_088: ex2_sh16_r1_b(88) <= not( cp4_032 and ex2_sh_lvl2(56) ); +r1_089: ex2_sh16_r1_b(89) <= not( cp4_032 and ex2_sh_lvl2(57) ); +r1_090: ex2_sh16_r1_b(90) <= not( cp4_032 and ex2_sh_lvl2(58) ); +r1_091: ex2_sh16_r1_b(91) <= not( cp4_032 and ex2_sh_lvl2(59) ); +r1_092: ex2_sh16_r1_b(92) <= not( cp4_032 and ex2_sh_lvl2(60) ); +r1_093: ex2_sh16_r1_b(93) <= not( cp4_032 and ex2_sh_lvl2(61) ); +r1_094: ex2_sh16_r1_b(94) <= not( cp4_032 and ex2_sh_lvl2(62) ); +r1_095: ex2_sh16_r1_b(95) <= not( cp4_032 and ex2_sh_lvl2(63) ); + +r1_096: ex2_sh16_r1_b(96) <= not( (cp5_032 and ex2_sh_lvl2(64) ) or (cp4_048 and ex2_sh_lvl2(48) ) ); +r1_097: ex2_sh16_r1_b(97) <= not( (cp5_032 and ex2_sh_lvl2(65) ) or (cp4_048 and ex2_sh_lvl2(49) ) ); +r1_098: ex2_sh16_r1_b(98) <= not( (cp5_032 and ex2_sh_lvl2(66) ) or (cp4_048 and ex2_sh_lvl2(50) ) ); +r1_099: ex2_sh16_r1_b(99) <= not( (cp5_032 and ex2_sh_lvl2(67) ) or (cp4_048 and ex2_sh_lvl2(51) ) ); +r1_100: ex2_sh16_r1_b(100) <= not( cp4_048 and ex2_sh_lvl2(52) ); +r1_101: ex2_sh16_r1_b(101) <= not( cp4_048 and ex2_sh_lvl2(53) ); +r1_102: ex2_sh16_r1_b(102) <= not( cp4_048 and ex2_sh_lvl2(54) ); +r1_103: ex2_sh16_r1_b(103) <= not( cp4_048 and ex2_sh_lvl2(55) ); +r1_104: ex2_sh16_r1_b(104) <= not( cp4_048 and ex2_sh_lvl2(56) ); +r1_105: ex2_sh16_r1_b(105) <= not( cp4_048 and ex2_sh_lvl2(57) ); +r1_106: ex2_sh16_r1_b(106) <= not( cp4_048 and ex2_sh_lvl2(58) ); +r1_107: ex2_sh16_r1_b(107) <= not( cp4_048 and ex2_sh_lvl2(59) ); +r1_108: ex2_sh16_r1_b(108) <= not( cp4_048 and ex2_sh_lvl2(60) ); +r1_109: ex2_sh16_r1_b(109) <= not( cp4_048 and ex2_sh_lvl2(61) ); +r1_110: ex2_sh16_r1_b(110) <= not( cp4_048 and ex2_sh_lvl2(62) ); +r1_111: ex2_sh16_r1_b(111) <= not( cp4_048 and ex2_sh_lvl2(63) ); + +r1_112: ex2_sh16_r1_b(112) <= not( (cp5_048 and ex2_sh_lvl2(64) ) or (cp4_064 and ex2_sh_lvl2(48) ) ); +r1_113: ex2_sh16_r1_b(113) <= not( (cp5_048 and ex2_sh_lvl2(65) ) or (cp4_064 and ex2_sh_lvl2(49) ) ); +r1_114: ex2_sh16_r1_b(114) <= not( (cp5_048 and ex2_sh_lvl2(66) ) or (cp4_064 and ex2_sh_lvl2(50) ) ); +r1_115: ex2_sh16_r1_b(115) <= not( (cp5_048 and ex2_sh_lvl2(67) ) or (cp4_064 and ex2_sh_lvl2(51) ) ); +r1_116: ex2_sh16_r1_b(116) <= not( cp4_064 and ex2_sh_lvl2(52) ); +r1_117: ex2_sh16_r1_b(117) <= not( cp4_064 and ex2_sh_lvl2(53) ); +r1_118: ex2_sh16_r1_b(118) <= not( cp4_064 and ex2_sh_lvl2(54) ); +r1_119: ex2_sh16_r1_b(119) <= not( cp4_064 and ex2_sh_lvl2(55) ); +r1_120: ex2_sh16_r1_b(120) <= not( cp4_064 and ex2_sh_lvl2(56) ); +r1_121: ex2_sh16_r1_b(121) <= not( cp4_064 and ex2_sh_lvl2(57) ); +r1_122: ex2_sh16_r1_b(122) <= not( cp4_064 and ex2_sh_lvl2(58) ); +r1_123: ex2_sh16_r1_b(123) <= not( cp4_064 and ex2_sh_lvl2(59) ); +r1_124: ex2_sh16_r1_b(124) <= not( cp4_064 and ex2_sh_lvl2(60) ); +r1_125: ex2_sh16_r1_b(125) <= not( cp4_064 and ex2_sh_lvl2(61) ); +r1_126: ex2_sh16_r1_b(126) <= not( cp4_064 and ex2_sh_lvl2(62) ); +r1_127: ex2_sh16_r1_b(127) <= not( cp4_064 and ex2_sh_lvl2(63) ); + +r1_128: ex2_sh16_r1_b(128) <= not( (cp5_064 and ex2_sh_lvl2(64) ) or (cp4_080 and ex2_sh_lvl2(48) ) ); +r1_129: ex2_sh16_r1_b(129) <= not( (cp5_064 and ex2_sh_lvl2(65) ) or (cp4_080 and ex2_sh_lvl2(49) ) ); +r1_130: ex2_sh16_r1_b(130) <= not( (cp5_064 and ex2_sh_lvl2(66) ) or (cp4_080 and ex2_sh_lvl2(50) ) ); +r1_131: ex2_sh16_r1_b(131) <= not( (cp5_064 and ex2_sh_lvl2(67) ) or (cp4_080 and ex2_sh_lvl2(51) ) ); +r1_132: ex2_sh16_r1_b(132) <= not( cp4_080 and ex2_sh_lvl2(52) ); +r1_133: ex2_sh16_r1_b(133) <= not( cp4_080 and ex2_sh_lvl2(53) ); +r1_134: ex2_sh16_r1_b(134) <= not( cp4_080 and ex2_sh_lvl2(54) ); +r1_135: ex2_sh16_r1_b(135) <= not( cp4_080 and ex2_sh_lvl2(55) ); +r1_136: ex2_sh16_r1_b(136) <= not( cp4_080 and ex2_sh_lvl2(56) ); +r1_137: ex2_sh16_r1_b(137) <= not( cp4_080 and ex2_sh_lvl2(57) ); +r1_138: ex2_sh16_r1_b(138) <= not( cp4_080 and ex2_sh_lvl2(58) ); +r1_139: ex2_sh16_r1_b(139) <= not( cp4_080 and ex2_sh_lvl2(59) ); +r1_140: ex2_sh16_r1_b(140) <= not( cp4_080 and ex2_sh_lvl2(60) ); +r1_141: ex2_sh16_r1_b(141) <= not( cp4_080 and ex2_sh_lvl2(61) ); +r1_142: ex2_sh16_r1_b(142) <= not( cp4_080 and ex2_sh_lvl2(62) ); +r1_143: ex2_sh16_r1_b(143) <= not( cp4_080 and ex2_sh_lvl2(63) ); + +r1_144: ex2_sh16_r1_b(144) <= not( (cp5_080 and ex2_sh_lvl2(64) ) or (cp4_096 and ex2_sh_lvl2(48) ) ); +r1_145: ex2_sh16_r1_b(145) <= not( (cp5_080 and ex2_sh_lvl2(65) ) or (cp4_096 and ex2_sh_lvl2(49) ) ); +r1_146: ex2_sh16_r1_b(146) <= not( (cp5_080 and ex2_sh_lvl2(66) ) or (cp4_096 and ex2_sh_lvl2(50) ) ); +r1_147: ex2_sh16_r1_b(147) <= not( (cp5_080 and ex2_sh_lvl2(67) ) or (cp4_096 and ex2_sh_lvl2(51) ) ); +r1_148: ex2_sh16_r1_b(148) <= not( cp4_096 and ex2_sh_lvl2(52) ); +r1_149: ex2_sh16_r1_b(149) <= not( cp4_096 and ex2_sh_lvl2(53) ); +r1_150: ex2_sh16_r1_b(150) <= not( cp4_096 and ex2_sh_lvl2(54) ); +r1_151: ex2_sh16_r1_b(151) <= not( cp4_096 and ex2_sh_lvl2(55) ); +r1_152: ex2_sh16_r1_b(152) <= not( cp4_096 and ex2_sh_lvl2(56) ); +r1_153: ex2_sh16_r1_b(153) <= not( cp4_096 and ex2_sh_lvl2(57) ); +r1_154: ex2_sh16_r1_b(154) <= not( cp4_096 and ex2_sh_lvl2(58) ); +r1_155: ex2_sh16_r1_b(155) <= not( cp4_096 and ex2_sh_lvl2(59) ); +r1_156: ex2_sh16_r1_b(156) <= not( cp4_096 and ex2_sh_lvl2(60) ); +r1_157: ex2_sh16_r1_b(157) <= not( cp4_096 and ex2_sh_lvl2(61) ); +r1_158: ex2_sh16_r1_b(158) <= not( cp4_096 and ex2_sh_lvl2(62) ); +r1_159: ex2_sh16_r1_b(159) <= not( cp4_096 and ex2_sh_lvl2(63) ); + +r1_160: ex2_sh16_r1_b(160) <= not( (cp5_096 and ex2_sh_lvl2(64) ) or (cp4_112 and ex2_sh_lvl2(48) ) ); +r1_161: ex2_sh16_r1_b(161) <= not( (cp5_096 and ex2_sh_lvl2(65) ) or (cp4_112 and ex2_sh_lvl2(49) ) ); +r1_162: ex2_sh16_r1_b(162) <= not( (cp5_096 and ex2_sh_lvl2(66) ) or (cp4_112 and ex2_sh_lvl2(50) ) ); + +r2_000: ex2_sh16_r2_b(0) <= not( (cp1_224 and ex2_sh_lvl2(32) ) or (cp1_240 and ex2_sh_lvl2(16) ) ); +r2_001: ex2_sh16_r2_b(1) <= not( (cp1_224 and ex2_sh_lvl2(33) ) or (cp1_240 and ex2_sh_lvl2(17) ) ); +r2_002: ex2_sh16_r2_b(2) <= not( (cp1_224 and ex2_sh_lvl2(34) ) or (cp1_240 and ex2_sh_lvl2(18) ) ); +r2_003: ex2_sh16_r2_b(3) <= not( (cp1_224 and ex2_sh_lvl2(35) ) or (cp1_240 and ex2_sh_lvl2(19) ) ); +r2_004: ex2_sh16_r2_b(4) <= not( (cp1_224 and ex2_sh_lvl2(36) ) or (cp1_240 and ex2_sh_lvl2(20) ) ); +r2_005: ex2_sh16_r2_b(5) <= not( (cp1_224 and ex2_sh_lvl2(37) ) or (cp1_240 and ex2_sh_lvl2(21) ) ); +r2_006: ex2_sh16_r2_b(6) <= not( (cp1_224 and ex2_sh_lvl2(38) ) or (cp1_240 and ex2_sh_lvl2(22) ) ); +r2_007: ex2_sh16_r2_b(7) <= not( (cp1_224 and ex2_sh_lvl2(39) ) or (cp1_240 and ex2_sh_lvl2(23) ) ); +r2_008: ex2_sh16_r2_b(8) <= not( (cp1_224 and ex2_sh_lvl2(40) ) or (cp1_240 and ex2_sh_lvl2(24) ) ); +r2_009: ex2_sh16_r2_b(9) <= not( (cp1_224 and ex2_sh_lvl2(41) ) or (cp1_240 and ex2_sh_lvl2(25) ) ); +r2_010: ex2_sh16_r2_b(10) <= not( (cp1_224 and ex2_sh_lvl2(42) ) or (cp1_240 and ex2_sh_lvl2(26) ) ); +r2_011: ex2_sh16_r2_b(11) <= not( (cp1_224 and ex2_sh_lvl2(43) ) or (cp1_240 and ex2_sh_lvl2(27) ) ); +r2_012: ex2_sh16_r2_b(12) <= not( (cp1_224 and ex2_sh_lvl2(44) ) or (cp1_240 and ex2_sh_lvl2(28) ) ); +r2_013: ex2_sh16_r2_b(13) <= not( (cp1_224 and ex2_sh_lvl2(45) ) or (cp1_240 and ex2_sh_lvl2(29) ) ); +r2_014: ex2_sh16_r2_b(14) <= not( (cp1_224 and ex2_sh_lvl2(46) ) or (cp1_240 and ex2_sh_lvl2(30) ) ); +r2_015: ex2_sh16_r2_b(15) <= not( (cp1_224 and ex2_sh_lvl2(47) ) or (cp1_240 and ex2_sh_lvl2(31) ) ); + +r2_016: ex2_sh16_r2_b(16) <= not( (cp2_240 and ex2_sh_lvl2(32) ) or (cp2_000 and ex2_sh_lvl2(16) ) ); +r2_017: ex2_sh16_r2_b(17) <= not( (cp2_240 and ex2_sh_lvl2(33) ) or (cp2_000 and ex2_sh_lvl2(17) ) ); +r2_018: ex2_sh16_r2_b(18) <= not( (cp2_240 and ex2_sh_lvl2(34) ) or (cp2_000 and ex2_sh_lvl2(18) ) ); +r2_019: ex2_sh16_r2_b(19) <= not( (cp2_240 and ex2_sh_lvl2(35) ) or (cp2_000 and ex2_sh_lvl2(19) ) ); +r2_020: ex2_sh16_r2_b(20) <= not( (cp2_240 and ex2_sh_lvl2(36) ) or (cp2_000 and ex2_sh_lvl2(20) ) ); +r2_021: ex2_sh16_r2_b(21) <= not( (cp2_240 and ex2_sh_lvl2(37) ) or (cp2_000 and ex2_sh_lvl2(21) ) ); +r2_022: ex2_sh16_r2_b(22) <= not( (cp2_240 and ex2_sh_lvl2(38) ) or (cp2_000 and ex2_sh_lvl2(22) ) ); +r2_023: ex2_sh16_r2_b(23) <= not( (cp2_240 and ex2_sh_lvl2(39) ) or (cp2_000 and ex2_sh_lvl2(23) ) ); +r2_024: ex2_sh16_r2_b(24) <= not( (cp2_240 and ex2_sh_lvl2(40) ) or (cp2_000 and ex2_sh_lvl2(24) ) ); +r2_025: ex2_sh16_r2_b(25) <= not( (cp2_240 and ex2_sh_lvl2(41) ) or (cp2_000 and ex2_sh_lvl2(25) ) ); +r2_026: ex2_sh16_r2_b(26) <= not( (cp2_240 and ex2_sh_lvl2(42) ) or (cp2_000 and ex2_sh_lvl2(26) ) ); +r2_027: ex2_sh16_r2_b(27) <= not( (cp2_240 and ex2_sh_lvl2(43) ) or (cp2_000 and ex2_sh_lvl2(27) ) ); +r2_028: ex2_sh16_r2_b(28) <= not( (cp2_240 and ex2_sh_lvl2(44) ) or (cp2_000 and ex2_sh_lvl2(28) ) ); +r2_029: ex2_sh16_r2_b(29) <= not( (cp2_240 and ex2_sh_lvl2(45) ) or (cp2_000 and ex2_sh_lvl2(29) ) ); +r2_030: ex2_sh16_r2_b(30) <= not( (cp2_240 and ex2_sh_lvl2(46) ) or (cp2_000 and ex2_sh_lvl2(30) ) ); +r2_031: ex2_sh16_r2_b(31) <= not( (cp2_240 and ex2_sh_lvl2(47) ) or (cp2_000 and ex2_sh_lvl2(31) ) ); + +r2_032: ex2_sh16_r2_b(32) <= not( (cp3_000 and ex2_sh_lvl2(32) ) or (cp2_016 and ex2_sh_lvl2(16) ) ); +r2_033: ex2_sh16_r2_b(33) <= not( (cp3_000 and ex2_sh_lvl2(33) ) or (cp2_016 and ex2_sh_lvl2(17) ) ); +r2_034: ex2_sh16_r2_b(34) <= not( (cp3_000 and ex2_sh_lvl2(34) ) or (cp2_016 and ex2_sh_lvl2(18) ) ); +r2_035: ex2_sh16_r2_b(35) <= not( (cp3_000 and ex2_sh_lvl2(35) ) or (cp2_016 and ex2_sh_lvl2(19) ) ); +r2_036: ex2_sh16_r2_b(36) <= not( (cp3_000 and ex2_sh_lvl2(36) ) or (cp2_016 and ex2_sh_lvl2(20) ) ); +r2_037: ex2_sh16_r2_b(37) <= not( (cp3_000 and ex2_sh_lvl2(37) ) or (cp2_016 and ex2_sh_lvl2(21) ) ); +r2_038: ex2_sh16_r2_b(38) <= not( (cp3_000 and ex2_sh_lvl2(38) ) or (cp2_016 and ex2_sh_lvl2(22) ) ); +r2_039: ex2_sh16_r2_b(39) <= not( (cp3_000 and ex2_sh_lvl2(39) ) or (cp2_016 and ex2_sh_lvl2(23) ) ); +r2_040: ex2_sh16_r2_b(40) <= not( (cp3_000 and ex2_sh_lvl2(40) ) or (cp2_016 and ex2_sh_lvl2(24) ) ); +r2_041: ex2_sh16_r2_b(41) <= not( (cp3_000 and ex2_sh_lvl2(41) ) or (cp2_016 and ex2_sh_lvl2(25) ) ); +r2_042: ex2_sh16_r2_b(42) <= not( (cp3_000 and ex2_sh_lvl2(42) ) or (cp2_016 and ex2_sh_lvl2(26) ) ); +r2_043: ex2_sh16_r2_b(43) <= not( (cp3_000 and ex2_sh_lvl2(43) ) or (cp2_016 and ex2_sh_lvl2(27) ) ); +r2_044: ex2_sh16_r2_b(44) <= not( (cp3_000 and ex2_sh_lvl2(44) ) or (cp2_016 and ex2_sh_lvl2(28) ) ); +r2_045: ex2_sh16_r2_b(45) <= not( (cp3_000 and ex2_sh_lvl2(45) ) or (cp2_016 and ex2_sh_lvl2(29) ) ); +r2_046: ex2_sh16_r2_b(46) <= not( (cp3_000 and ex2_sh_lvl2(46) ) or (cp2_016 and ex2_sh_lvl2(30) ) ); +r2_047: ex2_sh16_r2_b(47) <= not( (cp3_000 and ex2_sh_lvl2(47) ) or (cp2_016 and ex2_sh_lvl2(31) ) ); + +r2_048: ex2_sh16_r2_b(48) <= not( (cp3_016 and ex2_sh_lvl2(32) ) or (cp2_032 and ex2_sh_lvl2(16) ) ); +r2_049: ex2_sh16_r2_b(49) <= not( (cp3_016 and ex2_sh_lvl2(33) ) or (cp2_032 and ex2_sh_lvl2(17) ) ); +r2_050: ex2_sh16_r2_b(50) <= not( (cp3_016 and ex2_sh_lvl2(34) ) or (cp2_032 and ex2_sh_lvl2(18) ) ); +r2_051: ex2_sh16_r2_b(51) <= not( (cp3_016 and ex2_sh_lvl2(35) ) or (cp2_032 and ex2_sh_lvl2(19) ) ); +r2_052: ex2_sh16_r2_b(52) <= not( (cp3_016 and ex2_sh_lvl2(36) ) or (cp2_032 and ex2_sh_lvl2(20) ) ); +r2_053: ex2_sh16_r2_b(53) <= not( (cp3_016 and ex2_sh_lvl2(37) ) or (cp2_032 and ex2_sh_lvl2(21) ) ); +r2_054: ex2_sh16_r2_b(54) <= not( (cp3_016 and ex2_sh_lvl2(38) ) or (cp2_032 and ex2_sh_lvl2(22) ) ); +r2_055: ex2_sh16_r2_b(55) <= not( (cp3_016 and ex2_sh_lvl2(39) ) or (cp2_032 and ex2_sh_lvl2(23) ) ); +r2_056: ex2_sh16_r2_b(56) <= not( (cp3_016 and ex2_sh_lvl2(40) ) or (cp2_032 and ex2_sh_lvl2(24) ) ); +r2_057: ex2_sh16_r2_b(57) <= not( (cp3_016 and ex2_sh_lvl2(41) ) or (cp2_032 and ex2_sh_lvl2(25) ) ); +r2_058: ex2_sh16_r2_b(58) <= not( (cp3_016 and ex2_sh_lvl2(42) ) or (cp2_032 and ex2_sh_lvl2(26) ) ); +r2_059: ex2_sh16_r2_b(59) <= not( (cp3_016 and ex2_sh_lvl2(43) ) or (cp2_032 and ex2_sh_lvl2(27) ) ); +r2_060: ex2_sh16_r2_b(60) <= not( (cp3_016 and ex2_sh_lvl2(44) ) or (cp2_032 and ex2_sh_lvl2(28) ) ); +r2_061: ex2_sh16_r2_b(61) <= not( (cp3_016 and ex2_sh_lvl2(45) ) or (cp2_032 and ex2_sh_lvl2(29) ) ); +r2_062: ex2_sh16_r2_b(62) <= not( (cp3_016 and ex2_sh_lvl2(46) ) or (cp2_032 and ex2_sh_lvl2(30) ) ); +r2_063: ex2_sh16_r2_b(63) <= not( (cp3_016 and ex2_sh_lvl2(47) ) or (cp2_032 and ex2_sh_lvl2(31) ) ); + +r2_064: ex2_sh16_r2_b(64) <= not( (cp3_032 and ex2_sh_lvl2(32) ) or (cp2_048 and ex2_sh_lvl2(16) ) ); +r2_065: ex2_sh16_r2_b(65) <= not( (cp3_032 and ex2_sh_lvl2(33) ) or (cp2_048 and ex2_sh_lvl2(17) ) ); +r2_066: ex2_sh16_r2_b(66) <= not( (cp3_032 and ex2_sh_lvl2(34) ) or (cp2_048 and ex2_sh_lvl2(18) ) ); +r2_067: ex2_sh16_r2_b(67) <= not( (cp3_032 and ex2_sh_lvl2(35) ) or (cp2_048 and ex2_sh_lvl2(19) ) ); +r2_068: ex2_sh16_r2_b(68) <= not( (cp3_032 and ex2_sh_lvl2(36) ) or (cp2_048 and ex2_sh_lvl2(20) ) ); +r2_069: ex2_sh16_r2_b(69) <= not( (cp3_032 and ex2_sh_lvl2(37) ) or (cp2_048 and ex2_sh_lvl2(21) ) ); +r2_070: ex2_sh16_r2_b(70) <= not( (cp3_032 and ex2_sh_lvl2(38) ) or (cp2_048 and ex2_sh_lvl2(22) ) ); +r2_071: ex2_sh16_r2_b(71) <= not( (cp3_032 and ex2_sh_lvl2(39) ) or (cp2_048 and ex2_sh_lvl2(23) ) ); +r2_072: ex2_sh16_r2_b(72) <= not( (cp3_032 and ex2_sh_lvl2(40) ) or (cp2_048 and ex2_sh_lvl2(24) ) ); +r2_073: ex2_sh16_r2_b(73) <= not( (cp3_032 and ex2_sh_lvl2(41) ) or (cp2_048 and ex2_sh_lvl2(25) ) ); +r2_074: ex2_sh16_r2_b(74) <= not( (cp3_032 and ex2_sh_lvl2(42) ) or (cp2_048 and ex2_sh_lvl2(26) ) ); +r2_075: ex2_sh16_r2_b(75) <= not( (cp3_032 and ex2_sh_lvl2(43) ) or (cp2_048 and ex2_sh_lvl2(27) ) ); +r2_076: ex2_sh16_r2_b(76) <= not( (cp3_032 and ex2_sh_lvl2(44) ) or (cp2_048 and ex2_sh_lvl2(28) ) ); +r2_077: ex2_sh16_r2_b(77) <= not( (cp3_032 and ex2_sh_lvl2(45) ) or (cp2_048 and ex2_sh_lvl2(29) ) ); +r2_078: ex2_sh16_r2_b(78) <= not( (cp3_032 and ex2_sh_lvl2(46) ) or (cp2_048 and ex2_sh_lvl2(30) ) ); +r2_079: ex2_sh16_r2_b(79) <= not( (cp3_032 and ex2_sh_lvl2(47) ) or (cp2_048 and ex2_sh_lvl2(31) ) ); + +r2_080: ex2_sh16_r2_b(80) <= not( (cp3_048 and ex2_sh_lvl2(32) ) or (cp2_064 and ex2_sh_lvl2(16) ) ); +r2_081: ex2_sh16_r2_b(81) <= not( (cp3_048 and ex2_sh_lvl2(33) ) or (cp2_064 and ex2_sh_lvl2(17) ) ); +r2_082: ex2_sh16_r2_b(82) <= not( (cp3_048 and ex2_sh_lvl2(34) ) or (cp2_064 and ex2_sh_lvl2(18) ) ); +r2_083: ex2_sh16_r2_b(83) <= not( (cp3_048 and ex2_sh_lvl2(35) ) or (cp2_064 and ex2_sh_lvl2(19) ) ); +r2_084: ex2_sh16_r2_b(84) <= not( (cp3_048 and ex2_sh_lvl2(36) ) or (cp2_064 and ex2_sh_lvl2(20) ) ); +r2_085: ex2_sh16_r2_b(85) <= not( (cp3_048 and ex2_sh_lvl2(37) ) or (cp2_064 and ex2_sh_lvl2(21) ) ); +r2_086: ex2_sh16_r2_b(86) <= not( (cp3_048 and ex2_sh_lvl2(38) ) or (cp2_064 and ex2_sh_lvl2(22) ) ); +r2_087: ex2_sh16_r2_b(87) <= not( (cp3_048 and ex2_sh_lvl2(39) ) or (cp2_064 and ex2_sh_lvl2(23) ) ); +r2_088: ex2_sh16_r2_b(88) <= not( (cp3_048 and ex2_sh_lvl2(40) ) or (cp2_064 and ex2_sh_lvl2(24) ) ); +r2_089: ex2_sh16_r2_b(89) <= not( (cp3_048 and ex2_sh_lvl2(41) ) or (cp2_064 and ex2_sh_lvl2(25) ) ); +r2_090: ex2_sh16_r2_b(90) <= not( (cp3_048 and ex2_sh_lvl2(42) ) or (cp2_064 and ex2_sh_lvl2(26) ) ); +r2_091: ex2_sh16_r2_b(91) <= not( (cp3_048 and ex2_sh_lvl2(43) ) or (cp2_064 and ex2_sh_lvl2(27) ) ); +r2_092: ex2_sh16_r2_b(92) <= not( (cp3_048 and ex2_sh_lvl2(44) ) or (cp2_064 and ex2_sh_lvl2(28) ) ); +r2_093: ex2_sh16_r2_b(93) <= not( (cp3_048 and ex2_sh_lvl2(45) ) or (cp2_064 and ex2_sh_lvl2(29) ) ); +r2_094: ex2_sh16_r2_b(94) <= not( (cp3_048 and ex2_sh_lvl2(46) ) or (cp2_064 and ex2_sh_lvl2(30) ) ); +r2_095: ex2_sh16_r2_b(95) <= not( (cp3_048 and ex2_sh_lvl2(47) ) or (cp2_064 and ex2_sh_lvl2(31) ) ); + +r2_096: ex2_sh16_r2_b(96) <= not( (cp3_064 and ex2_sh_lvl2(32) ) or (cp2_080 and ex2_sh_lvl2(16) ) ); +r2_097: ex2_sh16_r2_b(97) <= not( (cp3_064 and ex2_sh_lvl2(33) ) or (cp2_080 and ex2_sh_lvl2(17) ) ); +r2_098: ex2_sh16_r2_b(98) <= not( (cp3_064 and ex2_sh_lvl2(34) ) or (cp2_080 and ex2_sh_lvl2(18) ) ); +r2_099: ex2_sh16_r2_b(99) <= not( (cp3_064 and ex2_sh_lvl2(35) ) or (cp2_080 and ex2_sh_lvl2(19) ) ); +r2_100: ex2_sh16_r2_b(100) <= not( (cp3_064 and ex2_sh_lvl2(36) ) or (cp2_080 and ex2_sh_lvl2(20) ) ); +r2_101: ex2_sh16_r2_b(101) <= not( (cp3_064 and ex2_sh_lvl2(37) ) or (cp2_080 and ex2_sh_lvl2(21) ) ); +r2_102: ex2_sh16_r2_b(102) <= not( (cp3_064 and ex2_sh_lvl2(38) ) or (cp2_080 and ex2_sh_lvl2(22) ) ); +r2_103: ex2_sh16_r2_b(103) <= not( (cp3_064 and ex2_sh_lvl2(39) ) or (cp2_080 and ex2_sh_lvl2(23) ) ); +r2_104: ex2_sh16_r2_b(104) <= not( (cp3_064 and ex2_sh_lvl2(40) ) or (cp2_080 and ex2_sh_lvl2(24) ) ); +r2_105: ex2_sh16_r2_b(105) <= not( (cp3_064 and ex2_sh_lvl2(41) ) or (cp2_080 and ex2_sh_lvl2(25) ) ); +r2_106: ex2_sh16_r2_b(106) <= not( (cp3_064 and ex2_sh_lvl2(42) ) or (cp2_080 and ex2_sh_lvl2(26) ) ); +r2_107: ex2_sh16_r2_b(107) <= not( (cp3_064 and ex2_sh_lvl2(43) ) or (cp2_080 and ex2_sh_lvl2(27) ) ); +r2_108: ex2_sh16_r2_b(108) <= not( (cp3_064 and ex2_sh_lvl2(44) ) or (cp2_080 and ex2_sh_lvl2(28) ) ); +r2_109: ex2_sh16_r2_b(109) <= not( (cp3_064 and ex2_sh_lvl2(45) ) or (cp2_080 and ex2_sh_lvl2(29) ) ); +r2_110: ex2_sh16_r2_b(110) <= not( (cp3_064 and ex2_sh_lvl2(46) ) or (cp2_080 and ex2_sh_lvl2(30) ) ); +r2_111: ex2_sh16_r2_b(111) <= not( (cp3_064 and ex2_sh_lvl2(47) ) or (cp2_080 and ex2_sh_lvl2(31) ) ); + +r2_112: ex2_sh16_r2_b(112) <= not( (cp3_080 and ex2_sh_lvl2(32) ) or (cp2_096 and ex2_sh_lvl2(16) ) ); +r2_113: ex2_sh16_r2_b(113) <= not( (cp3_080 and ex2_sh_lvl2(33) ) or (cp2_096 and ex2_sh_lvl2(17) ) ); +r2_114: ex2_sh16_r2_b(114) <= not( (cp3_080 and ex2_sh_lvl2(34) ) or (cp2_096 and ex2_sh_lvl2(18) ) ); +r2_115: ex2_sh16_r2_b(115) <= not( (cp3_080 and ex2_sh_lvl2(35) ) or (cp2_096 and ex2_sh_lvl2(19) ) ); +r2_116: ex2_sh16_r2_b(116) <= not( (cp3_080 and ex2_sh_lvl2(36) ) or (cp2_096 and ex2_sh_lvl2(20) ) ); +r2_117: ex2_sh16_r2_b(117) <= not( (cp3_080 and ex2_sh_lvl2(37) ) or (cp2_096 and ex2_sh_lvl2(21) ) ); +r2_118: ex2_sh16_r2_b(118) <= not( (cp3_080 and ex2_sh_lvl2(38) ) or (cp2_096 and ex2_sh_lvl2(22) ) ); +r2_119: ex2_sh16_r2_b(119) <= not( (cp3_080 and ex2_sh_lvl2(39) ) or (cp2_096 and ex2_sh_lvl2(23) ) ); +r2_120: ex2_sh16_r2_b(120) <= not( (cp3_080 and ex2_sh_lvl2(40) ) or (cp2_096 and ex2_sh_lvl2(24) ) ); +r2_121: ex2_sh16_r2_b(121) <= not( (cp3_080 and ex2_sh_lvl2(41) ) or (cp2_096 and ex2_sh_lvl2(25) ) ); +r2_122: ex2_sh16_r2_b(122) <= not( (cp3_080 and ex2_sh_lvl2(42) ) or (cp2_096 and ex2_sh_lvl2(26) ) ); +r2_123: ex2_sh16_r2_b(123) <= not( (cp3_080 and ex2_sh_lvl2(43) ) or (cp2_096 and ex2_sh_lvl2(27) ) ); +r2_124: ex2_sh16_r2_b(124) <= not( (cp3_080 and ex2_sh_lvl2(44) ) or (cp2_096 and ex2_sh_lvl2(28) ) ); +r2_125: ex2_sh16_r2_b(125) <= not( (cp3_080 and ex2_sh_lvl2(45) ) or (cp2_096 and ex2_sh_lvl2(29) ) ); +r2_126: ex2_sh16_r2_b(126) <= not( (cp3_080 and ex2_sh_lvl2(46) ) or (cp2_096 and ex2_sh_lvl2(30) ) ); +r2_127: ex2_sh16_r2_b(127) <= not( (cp3_080 and ex2_sh_lvl2(47) ) or (cp2_096 and ex2_sh_lvl2(31) ) ); + +r2_128: ex2_sh16_r2_b(128) <= not( (cp3_096 and ex2_sh_lvl2(32) ) or (cp2_112 and ex2_sh_lvl2(16) ) ); +r2_129: ex2_sh16_r2_b(129) <= not( (cp3_096 and ex2_sh_lvl2(33) ) or (cp2_112 and ex2_sh_lvl2(17) ) ); +r2_130: ex2_sh16_r2_b(130) <= not( (cp3_096 and ex2_sh_lvl2(34) ) or (cp2_112 and ex2_sh_lvl2(18) ) ); +r2_131: ex2_sh16_r2_b(131) <= not( (cp3_096 and ex2_sh_lvl2(35) ) or (cp2_112 and ex2_sh_lvl2(19) ) ); +r2_132: ex2_sh16_r2_b(132) <= not( (cp3_096 and ex2_sh_lvl2(36) ) or (cp2_112 and ex2_sh_lvl2(20) ) ); +r2_133: ex2_sh16_r2_b(133) <= not( (cp3_096 and ex2_sh_lvl2(37) ) or (cp2_112 and ex2_sh_lvl2(21) ) ); +r2_134: ex2_sh16_r2_b(134) <= not( (cp3_096 and ex2_sh_lvl2(38) ) or (cp2_112 and ex2_sh_lvl2(22) ) ); +r2_135: ex2_sh16_r2_b(135) <= not( (cp3_096 and ex2_sh_lvl2(39) ) or (cp2_112 and ex2_sh_lvl2(23) ) ); +r2_136: ex2_sh16_r2_b(136) <= not( (cp3_096 and ex2_sh_lvl2(40) ) or (cp2_112 and ex2_sh_lvl2(24) ) ); +r2_137: ex2_sh16_r2_b(137) <= not( (cp3_096 and ex2_sh_lvl2(41) ) or (cp2_112 and ex2_sh_lvl2(25) ) ); +r2_138: ex2_sh16_r2_b(138) <= not( (cp3_096 and ex2_sh_lvl2(42) ) or (cp2_112 and ex2_sh_lvl2(26) ) ); +r2_139: ex2_sh16_r2_b(139) <= not( (cp3_096 and ex2_sh_lvl2(43) ) or (cp2_112 and ex2_sh_lvl2(27) ) ); +r2_140: ex2_sh16_r2_b(140) <= not( (cp3_096 and ex2_sh_lvl2(44) ) or (cp2_112 and ex2_sh_lvl2(28) ) ); +r2_141: ex2_sh16_r2_b(141) <= not( (cp3_096 and ex2_sh_lvl2(45) ) or (cp2_112 and ex2_sh_lvl2(29) ) ); +r2_142: ex2_sh16_r2_b(142) <= not( (cp3_096 and ex2_sh_lvl2(46) ) or (cp2_112 and ex2_sh_lvl2(30) ) ); +r2_143: ex2_sh16_r2_b(143) <= not( (cp3_096 and ex2_sh_lvl2(47) ) or (cp2_112 and ex2_sh_lvl2(31) ) ); + +r2_144: ex2_sh16_r2_b(144) <= not( (cp3_112 and ex2_sh_lvl2(32) ) or (cp2_128 and ex2_sh_lvl2(16) ) ); +r2_145: ex2_sh16_r2_b(145) <= not( (cp3_112 and ex2_sh_lvl2(33) ) or (cp2_128 and ex2_sh_lvl2(17) ) ); +r2_146: ex2_sh16_r2_b(146) <= not( (cp3_112 and ex2_sh_lvl2(34) ) or (cp2_128 and ex2_sh_lvl2(18) ) ); +r2_147: ex2_sh16_r2_b(147) <= not( (cp3_112 and ex2_sh_lvl2(35) ) or (cp2_128 and ex2_sh_lvl2(19) ) ); +r2_148: ex2_sh16_r2_b(148) <= not( (cp3_112 and ex2_sh_lvl2(36) ) or (cp2_128 and ex2_sh_lvl2(20) ) ); +r2_149: ex2_sh16_r2_b(149) <= not( (cp3_112 and ex2_sh_lvl2(37) ) or (cp2_128 and ex2_sh_lvl2(21) ) ); +r2_150: ex2_sh16_r2_b(150) <= not( (cp3_112 and ex2_sh_lvl2(38) ) or (cp2_128 and ex2_sh_lvl2(22) ) ); +r2_151: ex2_sh16_r2_b(151) <= not( (cp3_112 and ex2_sh_lvl2(39) ) or (cp2_128 and ex2_sh_lvl2(23) ) ); +r2_152: ex2_sh16_r2_b(152) <= not( (cp3_112 and ex2_sh_lvl2(40) ) or (cp2_128 and ex2_sh_lvl2(24) ) ); +r2_153: ex2_sh16_r2_b(153) <= not( (cp3_112 and ex2_sh_lvl2(41) ) or (cp2_128 and ex2_sh_lvl2(25) ) ); +r2_154: ex2_sh16_r2_b(154) <= not( (cp3_112 and ex2_sh_lvl2(42) ) or (cp2_128 and ex2_sh_lvl2(26) ) ); +r2_155: ex2_sh16_r2_b(155) <= not( (cp3_112 and ex2_sh_lvl2(43) ) or (cp2_128 and ex2_sh_lvl2(27) ) ); +r2_156: ex2_sh16_r2_b(156) <= not( (cp3_112 and ex2_sh_lvl2(44) ) or (cp2_128 and ex2_sh_lvl2(28) ) ); +r2_157: ex2_sh16_r2_b(157) <= not( (cp3_112 and ex2_sh_lvl2(45) ) or (cp2_128 and ex2_sh_lvl2(29) ) ); +r2_158: ex2_sh16_r2_b(158) <= not( (cp3_112 and ex2_sh_lvl2(46) ) or (cp2_128 and ex2_sh_lvl2(30) ) ); +r2_159: ex2_sh16_r2_b(159) <= not( (cp3_112 and ex2_sh_lvl2(47) ) or (cp2_128 and ex2_sh_lvl2(31) ) ); + +r2_160: ex2_sh16_r2_b(160) <= not( (cp3_128 and ex2_sh_lvl2(32) ) or (cp2_144 and ex2_sh_lvl2(16) ) ); +r2_161: ex2_sh16_r2_b(161) <= not( (cp3_128 and ex2_sh_lvl2(33) ) or (cp2_144 and ex2_sh_lvl2(17) ) ); +r2_162: ex2_sh16_r2_b(162) <= not( (cp3_128 and ex2_sh_lvl2(34) ) or (cp2_144 and ex2_sh_lvl2(18) ) ); + +r3_000: ex2_sh16_r3_b(0) <= not( cp1_000 and ex2_sh_lvl2(0) ); +r3_001: ex2_sh16_r3_b(1) <= not( cp1_000 and ex2_sh_lvl2(1) ); +r3_002: ex2_sh16_r3_b(2) <= not( cp1_000 and ex2_sh_lvl2(2) ); +r3_003: ex2_sh16_r3_b(3) <= not( cp1_000 and ex2_sh_lvl2(3) ); +r3_004: ex2_sh16_r3_b(4) <= not( cp1_000 and ex2_sh_lvl2(4) ); +r3_005: ex2_sh16_r3_b(5) <= not( cp1_000 and ex2_sh_lvl2(5) ); +r3_006: ex2_sh16_r3_b(6) <= not( cp1_000 and ex2_sh_lvl2(6) ); +r3_007: ex2_sh16_r3_b(7) <= not( cp1_000 and ex2_sh_lvl2(7) ); +r3_008: ex2_sh16_r3_b(8) <= not( cp1_000 and ex2_sh_lvl2(8) ); +r3_009: ex2_sh16_r3_b(9) <= not( cp1_000 and ex2_sh_lvl2(9) ); +r3_010: ex2_sh16_r3_b(10) <= not( cp1_000 and ex2_sh_lvl2(10) ); +r3_011: ex2_sh16_r3_b(11) <= not( cp1_000 and ex2_sh_lvl2(11) ); +r3_012: ex2_sh16_r3_b(12) <= not( cp1_000 and ex2_sh_lvl2(12) ); +r3_013: ex2_sh16_r3_b(13) <= not( cp1_000 and ex2_sh_lvl2(13) ); +r3_014: ex2_sh16_r3_b(14) <= not( cp1_000 and ex2_sh_lvl2(14) ); +r3_015: ex2_sh16_r3_b(15) <= not( cp1_000 and ex2_sh_lvl2(15) ); + +r3_016: ex2_sh16_r3_b(16) <= not( cp1_016 and ex2_sh_lvl2(0) ); +r3_017: ex2_sh16_r3_b(17) <= not( cp1_016 and ex2_sh_lvl2(1) ); +r3_018: ex2_sh16_r3_b(18) <= not( cp1_016 and ex2_sh_lvl2(2) ); +r3_019: ex2_sh16_r3_b(19) <= not( cp1_016 and ex2_sh_lvl2(3) ); +r3_020: ex2_sh16_r3_b(20) <= not( cp1_016 and ex2_sh_lvl2(4) ); +r3_021: ex2_sh16_r3_b(21) <= not( cp1_016 and ex2_sh_lvl2(5) ); +r3_022: ex2_sh16_r3_b(22) <= not( cp1_016 and ex2_sh_lvl2(6) ); +r3_023: ex2_sh16_r3_b(23) <= not( cp1_016 and ex2_sh_lvl2(7) ); +r3_024: ex2_sh16_r3_b(24) <= not( cp1_016 and ex2_sh_lvl2(8) ); +r3_025: ex2_sh16_r3_b(25) <= not( cp1_016 and ex2_sh_lvl2(9) ); +r3_026: ex2_sh16_r3_b(26) <= not( cp1_016 and ex2_sh_lvl2(10) ); +r3_027: ex2_sh16_r3_b(27) <= not( cp1_016 and ex2_sh_lvl2(11) ); +r3_028: ex2_sh16_r3_b(28) <= not( cp1_016 and ex2_sh_lvl2(12) ); +r3_029: ex2_sh16_r3_b(29) <= not( cp1_016 and ex2_sh_lvl2(13) ); +r3_030: ex2_sh16_r3_b(30) <= not( cp1_016 and ex2_sh_lvl2(14) ); +r3_031: ex2_sh16_r3_b(31) <= not( cp1_016 and ex2_sh_lvl2(15) ); + +r3_032: ex2_sh16_r3_b(32) <= not( cp1_032 and ex2_sh_lvl2(0) ); +r3_033: ex2_sh16_r3_b(33) <= not( cp1_032 and ex2_sh_lvl2(1) ); +r3_034: ex2_sh16_r3_b(34) <= not( cp1_032 and ex2_sh_lvl2(2) ); +r3_035: ex2_sh16_r3_b(35) <= not( cp1_032 and ex2_sh_lvl2(3) ); +r3_036: ex2_sh16_r3_b(36) <= not( cp1_032 and ex2_sh_lvl2(4) ); +r3_037: ex2_sh16_r3_b(37) <= not( cp1_032 and ex2_sh_lvl2(5) ); +r3_038: ex2_sh16_r3_b(38) <= not( cp1_032 and ex2_sh_lvl2(6) ); +r3_039: ex2_sh16_r3_b(39) <= not( cp1_032 and ex2_sh_lvl2(7) ); +r3_040: ex2_sh16_r3_b(40) <= not( cp1_032 and ex2_sh_lvl2(8) ); +r3_041: ex2_sh16_r3_b(41) <= not( cp1_032 and ex2_sh_lvl2(9) ); +r3_042: ex2_sh16_r3_b(42) <= not( cp1_032 and ex2_sh_lvl2(10) ); +r3_043: ex2_sh16_r3_b(43) <= not( cp1_032 and ex2_sh_lvl2(11) ); +r3_044: ex2_sh16_r3_b(44) <= not( cp1_032 and ex2_sh_lvl2(12) ); +r3_045: ex2_sh16_r3_b(45) <= not( cp1_032 and ex2_sh_lvl2(13) ); +r3_046: ex2_sh16_r3_b(46) <= not( cp1_032 and ex2_sh_lvl2(14) ); +r3_047: ex2_sh16_r3_b(47) <= not( cp1_032 and ex2_sh_lvl2(15) ); + +r3_048: ex2_sh16_r3_b(48) <= not( cp1_048 and ex2_sh_lvl2(0) ); +r3_049: ex2_sh16_r3_b(49) <= not( cp1_048 and ex2_sh_lvl2(1) ); +r3_050: ex2_sh16_r3_b(50) <= not( cp1_048 and ex2_sh_lvl2(2) ); +r3_051: ex2_sh16_r3_b(51) <= not( cp1_048 and ex2_sh_lvl2(3) ); +r3_052: ex2_sh16_r3_b(52) <= not( cp1_048 and ex2_sh_lvl2(4) ); +r3_053: ex2_sh16_r3_b(53) <= not( cp1_048 and ex2_sh_lvl2(5) ); +r3_054: ex2_sh16_r3_b(54) <= not( cp1_048 and ex2_sh_lvl2(6) ); +r3_055: ex2_sh16_r3_b(55) <= not( cp1_048 and ex2_sh_lvl2(7) ); +r3_056: ex2_sh16_r3_b(56) <= not( cp1_048 and ex2_sh_lvl2(8) ); +r3_057: ex2_sh16_r3_b(57) <= not( cp1_048 and ex2_sh_lvl2(9) ); +r3_058: ex2_sh16_r3_b(58) <= not( cp1_048 and ex2_sh_lvl2(10) ); +r3_059: ex2_sh16_r3_b(59) <= not( cp1_048 and ex2_sh_lvl2(11) ); +r3_060: ex2_sh16_r3_b(60) <= not( cp1_048 and ex2_sh_lvl2(12) ); +r3_061: ex2_sh16_r3_b(61) <= not( cp1_048 and ex2_sh_lvl2(13) ); +r3_062: ex2_sh16_r3_b(62) <= not( cp1_048 and ex2_sh_lvl2(14) ); +r3_063: ex2_sh16_r3_b(63) <= not( cp1_048 and ex2_sh_lvl2(15) ); + +r3_064: ex2_sh16_r3_b(64) <= not( cp1_064 and ex2_sh_lvl2(0) ); +r3_065: ex2_sh16_r3_b(65) <= not( cp1_064 and ex2_sh_lvl2(1) ); +r3_066: ex2_sh16_r3_b(66) <= not( cp1_064 and ex2_sh_lvl2(2) ); +r3_067: ex2_sh16_r3_b(67) <= not( cp1_064 and ex2_sh_lvl2(3) ); +r3_068: ex2_sh16_r3_b(68) <= not( cp1_064 and ex2_sh_lvl2(4) ); +r3_069: ex2_sh16_r3_b(69) <= not( cp1_064 and ex2_sh_lvl2(5) ); +r3_070: ex2_sh16_r3_b(70) <= not( cp1_064 and ex2_sh_lvl2(6) ); +r3_071: ex2_sh16_r3_b(71) <= not( cp1_064 and ex2_sh_lvl2(7) ); +r3_072: ex2_sh16_r3_b(72) <= not( cp1_064 and ex2_sh_lvl2(8) ); +r3_073: ex2_sh16_r3_b(73) <= not( cp1_064 and ex2_sh_lvl2(9) ); +r3_074: ex2_sh16_r3_b(74) <= not( cp1_064 and ex2_sh_lvl2(10) ); +r3_075: ex2_sh16_r3_b(75) <= not( cp1_064 and ex2_sh_lvl2(11) ); +r3_076: ex2_sh16_r3_b(76) <= not( cp1_064 and ex2_sh_lvl2(12) ); +r3_077: ex2_sh16_r3_b(77) <= not( cp1_064 and ex2_sh_lvl2(13) ); +r3_078: ex2_sh16_r3_b(78) <= not( cp1_064 and ex2_sh_lvl2(14) ); +r3_079: ex2_sh16_r3_b(79) <= not( cp1_064 and ex2_sh_lvl2(15) ); + +r3_080: ex2_sh16_r3_b(80) <= not( cp1_080 and ex2_sh_lvl2(0) ); +r3_081: ex2_sh16_r3_b(81) <= not( cp1_080 and ex2_sh_lvl2(1) ); +r3_082: ex2_sh16_r3_b(82) <= not( cp1_080 and ex2_sh_lvl2(2) ); +r3_083: ex2_sh16_r3_b(83) <= not( cp1_080 and ex2_sh_lvl2(3) ); +r3_084: ex2_sh16_r3_b(84) <= not( cp1_080 and ex2_sh_lvl2(4) ); +r3_085: ex2_sh16_r3_b(85) <= not( cp1_080 and ex2_sh_lvl2(5) ); +r3_086: ex2_sh16_r3_b(86) <= not( cp1_080 and ex2_sh_lvl2(6) ); +r3_087: ex2_sh16_r3_b(87) <= not( cp1_080 and ex2_sh_lvl2(7) ); +r3_088: ex2_sh16_r3_b(88) <= not( cp1_080 and ex2_sh_lvl2(8) ); +r3_089: ex2_sh16_r3_b(89) <= not( cp1_080 and ex2_sh_lvl2(9) ); +r3_090: ex2_sh16_r3_b(90) <= not( cp1_080 and ex2_sh_lvl2(10) ); +r3_091: ex2_sh16_r3_b(91) <= not( cp1_080 and ex2_sh_lvl2(11) ); +r3_092: ex2_sh16_r3_b(92) <= not( cp1_080 and ex2_sh_lvl2(12) ); +r3_093: ex2_sh16_r3_b(93) <= not( cp1_080 and ex2_sh_lvl2(13) ); +r3_094: ex2_sh16_r3_b(94) <= not( cp1_080 and ex2_sh_lvl2(14) ); +r3_095: ex2_sh16_r3_b(95) <= not( cp1_080 and ex2_sh_lvl2(15) ); + +r3_096: ex2_sh16_r3_b(96) <= not( cp1_096 and ex2_sh_lvl2(0) ) ; +r3_097: ex2_sh16_r3_b(97) <= not( cp1_096 and ex2_sh_lvl2(1) ) ; +r3_098: ex2_sh16_r3_b(98) <= not( cp1_096 and ex2_sh_lvl2(2) ) ; +r3_099: ex2_sh16_r3_b(99) <= not( (cp1_096 and ex2_sh_lvl2(3) ) or (cp1_spc and ex2_special(99) ) ); +r3_100: ex2_sh16_r3_b(100) <= not( (cp1_096 and ex2_sh_lvl2(4) ) or (cp1_spc and ex2_special(100) ) ); +r3_101: ex2_sh16_r3_b(101) <= not( (cp1_096 and ex2_sh_lvl2(5) ) or (cp1_spc and ex2_special(101) ) ); +r3_102: ex2_sh16_r3_b(102) <= not( (cp1_096 and ex2_sh_lvl2(6) ) or (cp1_spc and ex2_special(102) ) ); +r3_103: ex2_sh16_r3_b(103) <= not( (cp1_096 and ex2_sh_lvl2(7) ) or (cp1_spc and ex2_special(103) ) ); +r3_104: ex2_sh16_r3_b(104) <= not( (cp1_096 and ex2_sh_lvl2(8) ) or (cp1_spc and ex2_special(104) ) ); +r3_105: ex2_sh16_r3_b(105) <= not( (cp1_096 and ex2_sh_lvl2(9) ) or (cp1_spc and ex2_special(105) ) ); +r3_106: ex2_sh16_r3_b(106) <= not( (cp1_096 and ex2_sh_lvl2(10) ) or (cp1_spc and ex2_special(106) ) ); +r3_107: ex2_sh16_r3_b(107) <= not( (cp1_096 and ex2_sh_lvl2(11) ) or (cp1_spc and ex2_special(107) ) ); +r3_108: ex2_sh16_r3_b(108) <= not( (cp1_096 and ex2_sh_lvl2(12) ) or (cp1_spc and ex2_special(108) ) ); +r3_109: ex2_sh16_r3_b(109) <= not( (cp1_096 and ex2_sh_lvl2(13) ) or (cp1_spc and ex2_special(109) ) ); +r3_110: ex2_sh16_r3_b(110) <= not( (cp1_096 and ex2_sh_lvl2(14) ) or (cp1_spc and ex2_special(110) ) ); +r3_111: ex2_sh16_r3_b(111) <= not( (cp1_096 and ex2_sh_lvl2(15) ) or (cp1_spc and ex2_special(111) ) ); + +r3_112: ex2_sh16_r3_b(112) <= not( (cp1_112 and ex2_sh_lvl2(0) ) or (cp2_spc and ex2_special(112) ) ); +r3_113: ex2_sh16_r3_b(113) <= not( (cp1_112 and ex2_sh_lvl2(1) ) or (cp2_spc and ex2_special(113) ) ); +r3_114: ex2_sh16_r3_b(114) <= not( (cp1_112 and ex2_sh_lvl2(2) ) or (cp2_spc and ex2_special(114) ) ); +r3_115: ex2_sh16_r3_b(115) <= not( (cp1_112 and ex2_sh_lvl2(3) ) or (cp2_spc and ex2_special(115) ) ); +r3_116: ex2_sh16_r3_b(116) <= not( (cp1_112 and ex2_sh_lvl2(4) ) or (cp2_spc and ex2_special(116) ) ); +r3_117: ex2_sh16_r3_b(117) <= not( (cp1_112 and ex2_sh_lvl2(5) ) or (cp2_spc and ex2_special(117) ) ); +r3_118: ex2_sh16_r3_b(118) <= not( (cp1_112 and ex2_sh_lvl2(6) ) or (cp2_spc and ex2_special(118) ) ); +r3_119: ex2_sh16_r3_b(119) <= not( (cp1_112 and ex2_sh_lvl2(7) ) or (cp2_spc and ex2_special(119) ) ); +r3_120: ex2_sh16_r3_b(120) <= not( (cp1_112 and ex2_sh_lvl2(8) ) or (cp2_spc and ex2_special(120) ) ); +r3_121: ex2_sh16_r3_b(121) <= not( (cp1_112 and ex2_sh_lvl2(9) ) or (cp2_spc and ex2_special(121) ) ); +r3_122: ex2_sh16_r3_b(122) <= not( (cp1_112 and ex2_sh_lvl2(10) ) or (cp2_spc and ex2_special(122) ) ); +r3_123: ex2_sh16_r3_b(123) <= not( (cp1_112 and ex2_sh_lvl2(11) ) or (cp2_spc and ex2_special(123) ) ); +r3_124: ex2_sh16_r3_b(124) <= not( (cp1_112 and ex2_sh_lvl2(12) ) or (cp2_spc and ex2_special(124) ) ); +r3_125: ex2_sh16_r3_b(125) <= not( (cp1_112 and ex2_sh_lvl2(13) ) or (cp2_spc and ex2_special(125) ) ); +r3_126: ex2_sh16_r3_b(126) <= not( (cp1_112 and ex2_sh_lvl2(14) ) or (cp2_spc and ex2_special(126) ) ); +r3_127: ex2_sh16_r3_b(127) <= not( (cp1_112 and ex2_sh_lvl2(15) ) or (cp2_spc and ex2_special(127) ) ); + +r3_128: ex2_sh16_r3_b(128) <= not( (cp1_128 and ex2_sh_lvl2(0) ) or (cp3_spc and ex2_special(128) ) ); +r3_129: ex2_sh16_r3_b(129) <= not( (cp1_128 and ex2_sh_lvl2(1) ) or (cp3_spc and ex2_special(129) ) ); +r3_130: ex2_sh16_r3_b(130) <= not( (cp1_128 and ex2_sh_lvl2(2) ) or (cp3_spc and ex2_special(130) ) ); +r3_131: ex2_sh16_r3_b(131) <= not( (cp1_128 and ex2_sh_lvl2(3) ) or (cp3_spc and ex2_special(131) ) ); +r3_132: ex2_sh16_r3_b(132) <= not( (cp1_128 and ex2_sh_lvl2(4) ) or (cp3_spc and ex2_special(132) ) ); +r3_133: ex2_sh16_r3_b(133) <= not( (cp1_128 and ex2_sh_lvl2(5) ) or (cp3_spc and ex2_special(133) ) ); +r3_134: ex2_sh16_r3_b(134) <= not( (cp1_128 and ex2_sh_lvl2(6) ) or (cp3_spc and ex2_special(134) ) ); +r3_135: ex2_sh16_r3_b(135) <= not( (cp1_128 and ex2_sh_lvl2(7) ) or (cp3_spc and ex2_special(135) ) ); +r3_136: ex2_sh16_r3_b(136) <= not( (cp1_128 and ex2_sh_lvl2(8) ) or (cp3_spc and ex2_special(136) ) ); +r3_137: ex2_sh16_r3_b(137) <= not( (cp1_128 and ex2_sh_lvl2(9) ) or (cp3_spc and ex2_special(137) ) ); +r3_138: ex2_sh16_r3_b(138) <= not( (cp1_128 and ex2_sh_lvl2(10) ) or (cp3_spc and ex2_special(138) ) ); +r3_139: ex2_sh16_r3_b(139) <= not( (cp1_128 and ex2_sh_lvl2(11) ) or (cp3_spc and ex2_special(139) ) ); +r3_140: ex2_sh16_r3_b(140) <= not( (cp1_128 and ex2_sh_lvl2(12) ) or (cp3_spc and ex2_special(140) ) ); +r3_141: ex2_sh16_r3_b(141) <= not( (cp1_128 and ex2_sh_lvl2(13) ) or (cp3_spc and ex2_special(141) ) ); +r3_142: ex2_sh16_r3_b(142) <= not( (cp1_128 and ex2_sh_lvl2(14) ) or (cp3_spc and ex2_special(142) ) ); +r3_143: ex2_sh16_r3_b(143) <= not( (cp1_128 and ex2_sh_lvl2(15) ) or (cp3_spc and ex2_special(143) ) ); + +r3_144: ex2_sh16_r3_b(144) <= not( (cp1_144 and ex2_sh_lvl2(0) ) or (cp4_spc and ex2_special(144) ) ); +r3_145: ex2_sh16_r3_b(145) <= not( (cp1_144 and ex2_sh_lvl2(1) ) or (cp4_spc and ex2_special(145) ) ); +r3_146: ex2_sh16_r3_b(146) <= not( (cp1_144 and ex2_sh_lvl2(2) ) or (cp4_spc and ex2_special(146) ) ); +r3_147: ex2_sh16_r3_b(147) <= not( (cp1_144 and ex2_sh_lvl2(3) ) or (cp4_spc and ex2_special(147) ) ); +r3_148: ex2_sh16_r3_b(148) <= not( (cp1_144 and ex2_sh_lvl2(4) ) or (cp4_spc and ex2_special(148) ) ); +r3_149: ex2_sh16_r3_b(149) <= not( (cp1_144 and ex2_sh_lvl2(5) ) or (cp4_spc and ex2_special(149) ) ); +r3_150: ex2_sh16_r3_b(150) <= not( (cp1_144 and ex2_sh_lvl2(6) ) or (cp4_spc and ex2_special(150) ) ); +r3_151: ex2_sh16_r3_b(151) <= not( (cp1_144 and ex2_sh_lvl2(7) ) or (cp4_spc and ex2_special(151) ) ); +r3_152: ex2_sh16_r3_b(152) <= not( (cp1_144 and ex2_sh_lvl2(8) ) or (cp4_spc and ex2_special(152) ) ); +r3_153: ex2_sh16_r3_b(153) <= not( (cp1_144 and ex2_sh_lvl2(9) ) or (cp4_spc and ex2_special(153) ) ); +r3_154: ex2_sh16_r3_b(154) <= not( (cp1_144 and ex2_sh_lvl2(10) ) or (cp4_spc and ex2_special(154) ) ); +r3_155: ex2_sh16_r3_b(155) <= not( (cp1_144 and ex2_sh_lvl2(11) ) or (cp4_spc and ex2_special(155) ) ); +r3_156: ex2_sh16_r3_b(156) <= not( (cp1_144 and ex2_sh_lvl2(12) ) or (cp4_spc and ex2_special(156) ) ); +r3_157: ex2_sh16_r3_b(157) <= not( (cp1_144 and ex2_sh_lvl2(13) ) or (cp4_spc and ex2_special(157) ) ); +r3_158: ex2_sh16_r3_b(158) <= not( (cp1_144 and ex2_sh_lvl2(14) ) or (cp4_spc and ex2_special(158) ) ); +r3_159: ex2_sh16_r3_b(159) <= not( (cp1_144 and ex2_sh_lvl2(15) ) or (cp4_spc and ex2_special(159) ) ); + +r3_160: ex2_sh16_r3_b(160) <= not( (cp1_160 and ex2_sh_lvl2(0) ) or (cp5_spc and ex2_special(160) ) ); +r3_161: ex2_sh16_r3_b(161) <= not( (cp1_160 and ex2_sh_lvl2(1) ) or (cp5_spc and ex2_special(161) ) ); +r3_162: ex2_sh16_r3_b(162) <= not( (cp1_160 and ex2_sh_lvl2(2) ) or (cp5_spc and ex2_special(162) ) ); + + +o_000: ex2_sh_lvl3(0) <= not( ex2_sh16_r1_b(0) and ex2_sh16_r2_b(0) and ex2_sh16_r3_b(0) ); +o_001: ex2_sh_lvl3(1) <= not( ex2_sh16_r1_b(1) and ex2_sh16_r2_b(1) and ex2_sh16_r3_b(1) ); +o_002: ex2_sh_lvl3(2) <= not( ex2_sh16_r1_b(2) and ex2_sh16_r2_b(2) and ex2_sh16_r3_b(2) ); +o_003: ex2_sh_lvl3(3) <= not( ex2_sh16_r1_b(3) and ex2_sh16_r2_b(3) and ex2_sh16_r3_b(3) ); +o_004: ex2_sh_lvl3(4) <= not( ex2_sh16_r1_b(4) and ex2_sh16_r2_b(4) and ex2_sh16_r3_b(4) ); +o_005: ex2_sh_lvl3(5) <= not( ex2_sh16_r1_b(5) and ex2_sh16_r2_b(5) and ex2_sh16_r3_b(5) ); +o_006: ex2_sh_lvl3(6) <= not( ex2_sh16_r1_b(6) and ex2_sh16_r2_b(6) and ex2_sh16_r3_b(6) ); +o_007: ex2_sh_lvl3(7) <= not( ex2_sh16_r1_b(7) and ex2_sh16_r2_b(7) and ex2_sh16_r3_b(7) ); +o_008: ex2_sh_lvl3(8) <= not( ex2_sh16_r1_b(8) and ex2_sh16_r2_b(8) and ex2_sh16_r3_b(8) ); +o_009: ex2_sh_lvl3(9) <= not( ex2_sh16_r1_b(9) and ex2_sh16_r2_b(9) and ex2_sh16_r3_b(9) ); +o_010: ex2_sh_lvl3(10) <= not( ex2_sh16_r1_b(10) and ex2_sh16_r2_b(10) and ex2_sh16_r3_b(10) ); +o_011: ex2_sh_lvl3(11) <= not( ex2_sh16_r1_b(11) and ex2_sh16_r2_b(11) and ex2_sh16_r3_b(11) ); +o_012: ex2_sh_lvl3(12) <= not( ex2_sh16_r1_b(12) and ex2_sh16_r2_b(12) and ex2_sh16_r3_b(12) ); +o_013: ex2_sh_lvl3(13) <= not( ex2_sh16_r1_b(13) and ex2_sh16_r2_b(13) and ex2_sh16_r3_b(13) ); +o_014: ex2_sh_lvl3(14) <= not( ex2_sh16_r1_b(14) and ex2_sh16_r2_b(14) and ex2_sh16_r3_b(14) ); +o_015: ex2_sh_lvl3(15) <= not( ex2_sh16_r1_b(15) and ex2_sh16_r2_b(15) and ex2_sh16_r3_b(15) ); +o_016: ex2_sh_lvl3(16) <= not( ex2_sh16_r1_b(16) and ex2_sh16_r2_b(16) and ex2_sh16_r3_b(16) ); +o_017: ex2_sh_lvl3(17) <= not( ex2_sh16_r1_b(17) and ex2_sh16_r2_b(17) and ex2_sh16_r3_b(17) ); +o_018: ex2_sh_lvl3(18) <= not( ex2_sh16_r1_b(18) and ex2_sh16_r2_b(18) and ex2_sh16_r3_b(18) ); +o_019: ex2_sh_lvl3(19) <= not( ex2_sh16_r1_b(19) and ex2_sh16_r2_b(19) and ex2_sh16_r3_b(19) ); +o_020: ex2_sh_lvl3(20) <= not( ex2_sh16_r1_b(20) and ex2_sh16_r2_b(20) and ex2_sh16_r3_b(20) ); +o_021: ex2_sh_lvl3(21) <= not( ex2_sh16_r1_b(21) and ex2_sh16_r2_b(21) and ex2_sh16_r3_b(21) ); +o_022: ex2_sh_lvl3(22) <= not( ex2_sh16_r1_b(22) and ex2_sh16_r2_b(22) and ex2_sh16_r3_b(22) ); +o_023: ex2_sh_lvl3(23) <= not( ex2_sh16_r1_b(23) and ex2_sh16_r2_b(23) and ex2_sh16_r3_b(23) ); +o_024: ex2_sh_lvl3(24) <= not( ex2_sh16_r1_b(24) and ex2_sh16_r2_b(24) and ex2_sh16_r3_b(24) ); +o_025: ex2_sh_lvl3(25) <= not( ex2_sh16_r1_b(25) and ex2_sh16_r2_b(25) and ex2_sh16_r3_b(25) ); +o_026: ex2_sh_lvl3(26) <= not( ex2_sh16_r1_b(26) and ex2_sh16_r2_b(26) and ex2_sh16_r3_b(26) ); +o_027: ex2_sh_lvl3(27) <= not( ex2_sh16_r1_b(27) and ex2_sh16_r2_b(27) and ex2_sh16_r3_b(27) ); +o_028: ex2_sh_lvl3(28) <= not( ex2_sh16_r1_b(28) and ex2_sh16_r2_b(28) and ex2_sh16_r3_b(28) ); +o_029: ex2_sh_lvl3(29) <= not( ex2_sh16_r1_b(29) and ex2_sh16_r2_b(29) and ex2_sh16_r3_b(29) ); +o_030: ex2_sh_lvl3(30) <= not( ex2_sh16_r1_b(30) and ex2_sh16_r2_b(30) and ex2_sh16_r3_b(30) ); +o_031: ex2_sh_lvl3(31) <= not( ex2_sh16_r1_b(31) and ex2_sh16_r2_b(31) and ex2_sh16_r3_b(31) ); +o_032: ex2_sh_lvl3(32) <= not( ex2_sh16_r1_b(32) and ex2_sh16_r2_b(32) and ex2_sh16_r3_b(32) ); +o_033: ex2_sh_lvl3(33) <= not( ex2_sh16_r1_b(33) and ex2_sh16_r2_b(33) and ex2_sh16_r3_b(33) ); +o_034: ex2_sh_lvl3(34) <= not( ex2_sh16_r1_b(34) and ex2_sh16_r2_b(34) and ex2_sh16_r3_b(34) ); +o_035: ex2_sh_lvl3(35) <= not( ex2_sh16_r1_b(35) and ex2_sh16_r2_b(35) and ex2_sh16_r3_b(35) ); +o_036: ex2_sh_lvl3(36) <= not( ex2_sh16_r1_b(36) and ex2_sh16_r2_b(36) and ex2_sh16_r3_b(36) ); +o_037: ex2_sh_lvl3(37) <= not( ex2_sh16_r1_b(37) and ex2_sh16_r2_b(37) and ex2_sh16_r3_b(37) ); +o_038: ex2_sh_lvl3(38) <= not( ex2_sh16_r1_b(38) and ex2_sh16_r2_b(38) and ex2_sh16_r3_b(38) ); +o_039: ex2_sh_lvl3(39) <= not( ex2_sh16_r1_b(39) and ex2_sh16_r2_b(39) and ex2_sh16_r3_b(39) ); +o_040: ex2_sh_lvl3(40) <= not( ex2_sh16_r1_b(40) and ex2_sh16_r2_b(40) and ex2_sh16_r3_b(40) ); +o_041: ex2_sh_lvl3(41) <= not( ex2_sh16_r1_b(41) and ex2_sh16_r2_b(41) and ex2_sh16_r3_b(41) ); +o_042: ex2_sh_lvl3(42) <= not( ex2_sh16_r1_b(42) and ex2_sh16_r2_b(42) and ex2_sh16_r3_b(42) ); +o_043: ex2_sh_lvl3(43) <= not( ex2_sh16_r1_b(43) and ex2_sh16_r2_b(43) and ex2_sh16_r3_b(43) ); +o_044: ex2_sh_lvl3(44) <= not( ex2_sh16_r1_b(44) and ex2_sh16_r2_b(44) and ex2_sh16_r3_b(44) ); +o_045: ex2_sh_lvl3(45) <= not( ex2_sh16_r1_b(45) and ex2_sh16_r2_b(45) and ex2_sh16_r3_b(45) ); +o_046: ex2_sh_lvl3(46) <= not( ex2_sh16_r1_b(46) and ex2_sh16_r2_b(46) and ex2_sh16_r3_b(46) ); +o_047: ex2_sh_lvl3(47) <= not( ex2_sh16_r1_b(47) and ex2_sh16_r2_b(47) and ex2_sh16_r3_b(47) ); +o_048: ex2_sh_lvl3(48) <= not( ex2_sh16_r1_b(48) and ex2_sh16_r2_b(48) and ex2_sh16_r3_b(48) ); +o_049: ex2_sh_lvl3(49) <= not( ex2_sh16_r1_b(49) and ex2_sh16_r2_b(49) and ex2_sh16_r3_b(49) ); +o_050: ex2_sh_lvl3(50) <= not( ex2_sh16_r1_b(50) and ex2_sh16_r2_b(50) and ex2_sh16_r3_b(50) ); +o_051: ex2_sh_lvl3(51) <= not( ex2_sh16_r1_b(51) and ex2_sh16_r2_b(51) and ex2_sh16_r3_b(51) ); +o_052: ex2_sh_lvl3(52) <= not( ex2_sh16_r1_b(52) and ex2_sh16_r2_b(52) and ex2_sh16_r3_b(52) ); +o_053: ex2_sh_lvl3(53) <= not( ex2_sh16_r1_b(53) and ex2_sh16_r2_b(53) and ex2_sh16_r3_b(53) ); +o_054: ex2_sh_lvl3(54) <= not( ex2_sh16_r1_b(54) and ex2_sh16_r2_b(54) and ex2_sh16_r3_b(54) ); +o_055: ex2_sh_lvl3(55) <= not( ex2_sh16_r1_b(55) and ex2_sh16_r2_b(55) and ex2_sh16_r3_b(55) ); +o_056: ex2_sh_lvl3(56) <= not( ex2_sh16_r1_b(56) and ex2_sh16_r2_b(56) and ex2_sh16_r3_b(56) ); +o_057: ex2_sh_lvl3(57) <= not( ex2_sh16_r1_b(57) and ex2_sh16_r2_b(57) and ex2_sh16_r3_b(57) ); +o_058: ex2_sh_lvl3(58) <= not( ex2_sh16_r1_b(58) and ex2_sh16_r2_b(58) and ex2_sh16_r3_b(58) ); +o_059: ex2_sh_lvl3(59) <= not( ex2_sh16_r1_b(59) and ex2_sh16_r2_b(59) and ex2_sh16_r3_b(59) ); +o_060: ex2_sh_lvl3(60) <= not( ex2_sh16_r1_b(60) and ex2_sh16_r2_b(60) and ex2_sh16_r3_b(60) ); +o_061: ex2_sh_lvl3(61) <= not( ex2_sh16_r1_b(61) and ex2_sh16_r2_b(61) and ex2_sh16_r3_b(61) ); +o_062: ex2_sh_lvl3(62) <= not( ex2_sh16_r1_b(62) and ex2_sh16_r2_b(62) and ex2_sh16_r3_b(62) ); +o_063: ex2_sh_lvl3(63) <= not( ex2_sh16_r1_b(63) and ex2_sh16_r2_b(63) and ex2_sh16_r3_b(63) ); +o_064: ex2_sh_lvl3(64) <= not( ex2_sh16_r1_b(64) and ex2_sh16_r2_b(64) and ex2_sh16_r3_b(64) ); +o_065: ex2_sh_lvl3(65) <= not( ex2_sh16_r1_b(65) and ex2_sh16_r2_b(65) and ex2_sh16_r3_b(65) ); +o_066: ex2_sh_lvl3(66) <= not( ex2_sh16_r1_b(66) and ex2_sh16_r2_b(66) and ex2_sh16_r3_b(66) ); +o_067: ex2_sh_lvl3(67) <= not( ex2_sh16_r1_b(67) and ex2_sh16_r2_b(67) and ex2_sh16_r3_b(67) ); +o_068: ex2_sh_lvl3(68) <= not( ex2_sh16_r1_b(68) and ex2_sh16_r2_b(68) and ex2_sh16_r3_b(68) ); +o_069: ex2_sh_lvl3(69) <= not( ex2_sh16_r1_b(69) and ex2_sh16_r2_b(69) and ex2_sh16_r3_b(69) ); +o_070: ex2_sh_lvl3(70) <= not( ex2_sh16_r1_b(70) and ex2_sh16_r2_b(70) and ex2_sh16_r3_b(70) ); +o_071: ex2_sh_lvl3(71) <= not( ex2_sh16_r1_b(71) and ex2_sh16_r2_b(71) and ex2_sh16_r3_b(71) ); +o_072: ex2_sh_lvl3(72) <= not( ex2_sh16_r1_b(72) and ex2_sh16_r2_b(72) and ex2_sh16_r3_b(72) ); +o_073: ex2_sh_lvl3(73) <= not( ex2_sh16_r1_b(73) and ex2_sh16_r2_b(73) and ex2_sh16_r3_b(73) ); +o_074: ex2_sh_lvl3(74) <= not( ex2_sh16_r1_b(74) and ex2_sh16_r2_b(74) and ex2_sh16_r3_b(74) ); +o_075: ex2_sh_lvl3(75) <= not( ex2_sh16_r1_b(75) and ex2_sh16_r2_b(75) and ex2_sh16_r3_b(75) ); +o_076: ex2_sh_lvl3(76) <= not( ex2_sh16_r1_b(76) and ex2_sh16_r2_b(76) and ex2_sh16_r3_b(76) ); +o_077: ex2_sh_lvl3(77) <= not( ex2_sh16_r1_b(77) and ex2_sh16_r2_b(77) and ex2_sh16_r3_b(77) ); +o_078: ex2_sh_lvl3(78) <= not( ex2_sh16_r1_b(78) and ex2_sh16_r2_b(78) and ex2_sh16_r3_b(78) ); +o_079: ex2_sh_lvl3(79) <= not( ex2_sh16_r1_b(79) and ex2_sh16_r2_b(79) and ex2_sh16_r3_b(79) ); +o_080: ex2_sh_lvl3(80) <= not( ex2_sh16_r1_b(80) and ex2_sh16_r2_b(80) and ex2_sh16_r3_b(80) ); +o_081: ex2_sh_lvl3(81) <= not( ex2_sh16_r1_b(81) and ex2_sh16_r2_b(81) and ex2_sh16_r3_b(81) ); +o_082: ex2_sh_lvl3(82) <= not( ex2_sh16_r1_b(82) and ex2_sh16_r2_b(82) and ex2_sh16_r3_b(82) ); +o_083: ex2_sh_lvl3(83) <= not( ex2_sh16_r1_b(83) and ex2_sh16_r2_b(83) and ex2_sh16_r3_b(83) ); +o_084: ex2_sh_lvl3(84) <= not( ex2_sh16_r1_b(84) and ex2_sh16_r2_b(84) and ex2_sh16_r3_b(84) ); +o_085: ex2_sh_lvl3(85) <= not( ex2_sh16_r1_b(85) and ex2_sh16_r2_b(85) and ex2_sh16_r3_b(85) ); +o_086: ex2_sh_lvl3(86) <= not( ex2_sh16_r1_b(86) and ex2_sh16_r2_b(86) and ex2_sh16_r3_b(86) ); +o_087: ex2_sh_lvl3(87) <= not( ex2_sh16_r1_b(87) and ex2_sh16_r2_b(87) and ex2_sh16_r3_b(87) ); +o_088: ex2_sh_lvl3(88) <= not( ex2_sh16_r1_b(88) and ex2_sh16_r2_b(88) and ex2_sh16_r3_b(88) ); +o_089: ex2_sh_lvl3(89) <= not( ex2_sh16_r1_b(89) and ex2_sh16_r2_b(89) and ex2_sh16_r3_b(89) ); +o_090: ex2_sh_lvl3(90) <= not( ex2_sh16_r1_b(90) and ex2_sh16_r2_b(90) and ex2_sh16_r3_b(90) ); +o_091: ex2_sh_lvl3(91) <= not( ex2_sh16_r1_b(91) and ex2_sh16_r2_b(91) and ex2_sh16_r3_b(91) ); +o_092: ex2_sh_lvl3(92) <= not( ex2_sh16_r1_b(92) and ex2_sh16_r2_b(92) and ex2_sh16_r3_b(92) ); +o_093: ex2_sh_lvl3(93) <= not( ex2_sh16_r1_b(93) and ex2_sh16_r2_b(93) and ex2_sh16_r3_b(93) ); +o_094: ex2_sh_lvl3(94) <= not( ex2_sh16_r1_b(94) and ex2_sh16_r2_b(94) and ex2_sh16_r3_b(94) ); +o_095: ex2_sh_lvl3(95) <= not( ex2_sh16_r1_b(95) and ex2_sh16_r2_b(95) and ex2_sh16_r3_b(95) ); +o_096: ex2_sh_lvl3(96) <= not( ex2_sh16_r1_b(96) and ex2_sh16_r2_b(96) and ex2_sh16_r3_b(96) ); +o_097: ex2_sh_lvl3(97) <= not( ex2_sh16_r1_b(97) and ex2_sh16_r2_b(97) and ex2_sh16_r3_b(97) ); +o_098: ex2_sh_lvl3(98) <= not( ex2_sh16_r1_b(98) and ex2_sh16_r2_b(98) and ex2_sh16_r3_b(98) ); +o_099: ex2_sh_lvl3(99) <= not( ex2_sh16_r1_b(99) and ex2_sh16_r2_b(99) and ex2_sh16_r3_b(99) ); +o_100: ex2_sh_lvl3(100) <= not( ex2_sh16_r1_b(100) and ex2_sh16_r2_b(100) and ex2_sh16_r3_b(100) ); +o_101: ex2_sh_lvl3(101) <= not( ex2_sh16_r1_b(101) and ex2_sh16_r2_b(101) and ex2_sh16_r3_b(101) ); +o_102: ex2_sh_lvl3(102) <= not( ex2_sh16_r1_b(102) and ex2_sh16_r2_b(102) and ex2_sh16_r3_b(102) ); +o_103: ex2_sh_lvl3(103) <= not( ex2_sh16_r1_b(103) and ex2_sh16_r2_b(103) and ex2_sh16_r3_b(103) ); +o_104: ex2_sh_lvl3(104) <= not( ex2_sh16_r1_b(104) and ex2_sh16_r2_b(104) and ex2_sh16_r3_b(104) ); +o_105: ex2_sh_lvl3(105) <= not( ex2_sh16_r1_b(105) and ex2_sh16_r2_b(105) and ex2_sh16_r3_b(105) ); +o_106: ex2_sh_lvl3(106) <= not( ex2_sh16_r1_b(106) and ex2_sh16_r2_b(106) and ex2_sh16_r3_b(106) ); +o_107: ex2_sh_lvl3(107) <= not( ex2_sh16_r1_b(107) and ex2_sh16_r2_b(107) and ex2_sh16_r3_b(107) ); +o_108: ex2_sh_lvl3(108) <= not( ex2_sh16_r1_b(108) and ex2_sh16_r2_b(108) and ex2_sh16_r3_b(108) ); +o_109: ex2_sh_lvl3(109) <= not( ex2_sh16_r1_b(109) and ex2_sh16_r2_b(109) and ex2_sh16_r3_b(109) ); +o_110: ex2_sh_lvl3(110) <= not( ex2_sh16_r1_b(110) and ex2_sh16_r2_b(110) and ex2_sh16_r3_b(110) ); +o_111: ex2_sh_lvl3(111) <= not( ex2_sh16_r1_b(111) and ex2_sh16_r2_b(111) and ex2_sh16_r3_b(111) ); +o_112: ex2_sh_lvl3(112) <= not( ex2_sh16_r1_b(112) and ex2_sh16_r2_b(112) and ex2_sh16_r3_b(112) ); +o_113: ex2_sh_lvl3(113) <= not( ex2_sh16_r1_b(113) and ex2_sh16_r2_b(113) and ex2_sh16_r3_b(113) ); +o_114: ex2_sh_lvl3(114) <= not( ex2_sh16_r1_b(114) and ex2_sh16_r2_b(114) and ex2_sh16_r3_b(114) ); +o_115: ex2_sh_lvl3(115) <= not( ex2_sh16_r1_b(115) and ex2_sh16_r2_b(115) and ex2_sh16_r3_b(115) ); +o_116: ex2_sh_lvl3(116) <= not( ex2_sh16_r1_b(116) and ex2_sh16_r2_b(116) and ex2_sh16_r3_b(116) ); +o_117: ex2_sh_lvl3(117) <= not( ex2_sh16_r1_b(117) and ex2_sh16_r2_b(117) and ex2_sh16_r3_b(117) ); +o_118: ex2_sh_lvl3(118) <= not( ex2_sh16_r1_b(118) and ex2_sh16_r2_b(118) and ex2_sh16_r3_b(118) ); +o_119: ex2_sh_lvl3(119) <= not( ex2_sh16_r1_b(119) and ex2_sh16_r2_b(119) and ex2_sh16_r3_b(119) ); +o_120: ex2_sh_lvl3(120) <= not( ex2_sh16_r1_b(120) and ex2_sh16_r2_b(120) and ex2_sh16_r3_b(120) ); +o_121: ex2_sh_lvl3(121) <= not( ex2_sh16_r1_b(121) and ex2_sh16_r2_b(121) and ex2_sh16_r3_b(121) ); +o_122: ex2_sh_lvl3(122) <= not( ex2_sh16_r1_b(122) and ex2_sh16_r2_b(122) and ex2_sh16_r3_b(122) ); +o_123: ex2_sh_lvl3(123) <= not( ex2_sh16_r1_b(123) and ex2_sh16_r2_b(123) and ex2_sh16_r3_b(123) ); +o_124: ex2_sh_lvl3(124) <= not( ex2_sh16_r1_b(124) and ex2_sh16_r2_b(124) and ex2_sh16_r3_b(124) ); +o_125: ex2_sh_lvl3(125) <= not( ex2_sh16_r1_b(125) and ex2_sh16_r2_b(125) and ex2_sh16_r3_b(125) ); +o_126: ex2_sh_lvl3(126) <= not( ex2_sh16_r1_b(126) and ex2_sh16_r2_b(126) and ex2_sh16_r3_b(126) ); +o_127: ex2_sh_lvl3(127) <= not( ex2_sh16_r1_b(127) and ex2_sh16_r2_b(127) and ex2_sh16_r3_b(127) ); +o_128: ex2_sh_lvl3(128) <= not( ex2_sh16_r1_b(128) and ex2_sh16_r2_b(128) and ex2_sh16_r3_b(128) ); +o_129: ex2_sh_lvl3(129) <= not( ex2_sh16_r1_b(129) and ex2_sh16_r2_b(129) and ex2_sh16_r3_b(129) ); +o_130: ex2_sh_lvl3(130) <= not( ex2_sh16_r1_b(130) and ex2_sh16_r2_b(130) and ex2_sh16_r3_b(130) ); +o_131: ex2_sh_lvl3(131) <= not( ex2_sh16_r1_b(131) and ex2_sh16_r2_b(131) and ex2_sh16_r3_b(131) ); +o_132: ex2_sh_lvl3(132) <= not( ex2_sh16_r1_b(132) and ex2_sh16_r2_b(132) and ex2_sh16_r3_b(132) ); +o_133: ex2_sh_lvl3(133) <= not( ex2_sh16_r1_b(133) and ex2_sh16_r2_b(133) and ex2_sh16_r3_b(133) ); +o_134: ex2_sh_lvl3(134) <= not( ex2_sh16_r1_b(134) and ex2_sh16_r2_b(134) and ex2_sh16_r3_b(134) ); +o_135: ex2_sh_lvl3(135) <= not( ex2_sh16_r1_b(135) and ex2_sh16_r2_b(135) and ex2_sh16_r3_b(135) ); +o_136: ex2_sh_lvl3(136) <= not( ex2_sh16_r1_b(136) and ex2_sh16_r2_b(136) and ex2_sh16_r3_b(136) ); +o_137: ex2_sh_lvl3(137) <= not( ex2_sh16_r1_b(137) and ex2_sh16_r2_b(137) and ex2_sh16_r3_b(137) ); +o_138: ex2_sh_lvl3(138) <= not( ex2_sh16_r1_b(138) and ex2_sh16_r2_b(138) and ex2_sh16_r3_b(138) ); +o_139: ex2_sh_lvl3(139) <= not( ex2_sh16_r1_b(139) and ex2_sh16_r2_b(139) and ex2_sh16_r3_b(139) ); +o_140: ex2_sh_lvl3(140) <= not( ex2_sh16_r1_b(140) and ex2_sh16_r2_b(140) and ex2_sh16_r3_b(140) ); +o_141: ex2_sh_lvl3(141) <= not( ex2_sh16_r1_b(141) and ex2_sh16_r2_b(141) and ex2_sh16_r3_b(141) ); +o_142: ex2_sh_lvl3(142) <= not( ex2_sh16_r1_b(142) and ex2_sh16_r2_b(142) and ex2_sh16_r3_b(142) ); +o_143: ex2_sh_lvl3(143) <= not( ex2_sh16_r1_b(143) and ex2_sh16_r2_b(143) and ex2_sh16_r3_b(143) ); +o_144: ex2_sh_lvl3(144) <= not( ex2_sh16_r1_b(144) and ex2_sh16_r2_b(144) and ex2_sh16_r3_b(144) ); +o_145: ex2_sh_lvl3(145) <= not( ex2_sh16_r1_b(145) and ex2_sh16_r2_b(145) and ex2_sh16_r3_b(145) ); +o_146: ex2_sh_lvl3(146) <= not( ex2_sh16_r1_b(146) and ex2_sh16_r2_b(146) and ex2_sh16_r3_b(146) ); +o_147: ex2_sh_lvl3(147) <= not( ex2_sh16_r1_b(147) and ex2_sh16_r2_b(147) and ex2_sh16_r3_b(147) ); +o_148: ex2_sh_lvl3(148) <= not( ex2_sh16_r1_b(148) and ex2_sh16_r2_b(148) and ex2_sh16_r3_b(148) ); +o_149: ex2_sh_lvl3(149) <= not( ex2_sh16_r1_b(149) and ex2_sh16_r2_b(149) and ex2_sh16_r3_b(149) ); +o_150: ex2_sh_lvl3(150) <= not( ex2_sh16_r1_b(150) and ex2_sh16_r2_b(150) and ex2_sh16_r3_b(150) ); +o_151: ex2_sh_lvl3(151) <= not( ex2_sh16_r1_b(151) and ex2_sh16_r2_b(151) and ex2_sh16_r3_b(151) ); +o_152: ex2_sh_lvl3(152) <= not( ex2_sh16_r1_b(152) and ex2_sh16_r2_b(152) and ex2_sh16_r3_b(152) ); +o_153: ex2_sh_lvl3(153) <= not( ex2_sh16_r1_b(153) and ex2_sh16_r2_b(153) and ex2_sh16_r3_b(153) ); +o_154: ex2_sh_lvl3(154) <= not( ex2_sh16_r1_b(154) and ex2_sh16_r2_b(154) and ex2_sh16_r3_b(154) ); +o_155: ex2_sh_lvl3(155) <= not( ex2_sh16_r1_b(155) and ex2_sh16_r2_b(155) and ex2_sh16_r3_b(155) ); +o_156: ex2_sh_lvl3(156) <= not( ex2_sh16_r1_b(156) and ex2_sh16_r2_b(156) and ex2_sh16_r3_b(156) ); +o_157: ex2_sh_lvl3(157) <= not( ex2_sh16_r1_b(157) and ex2_sh16_r2_b(157) and ex2_sh16_r3_b(157) ); +o_158: ex2_sh_lvl3(158) <= not( ex2_sh16_r1_b(158) and ex2_sh16_r2_b(158) and ex2_sh16_r3_b(158) ); +o_159: ex2_sh_lvl3(159) <= not( ex2_sh16_r1_b(159) and ex2_sh16_r2_b(159) and ex2_sh16_r3_b(159) ); +o_160: ex2_sh_lvl3(160) <= not( ex2_sh16_r1_b(160) and ex2_sh16_r2_b(160) and ex2_sh16_r3_b(160) ); +o_161: ex2_sh_lvl3(161) <= not( ex2_sh16_r1_b(161) and ex2_sh16_r2_b(161) and ex2_sh16_r3_b(161) ); +o_162: ex2_sh_lvl3(162) <= not( ex2_sh16_r1_b(162) and ex2_sh16_r2_b(162) and ex2_sh16_r3_b(162) ); + + + +---------------------------------------- +-- replicated logic for sticky bit +---------------------------------------- + + +rr3_162: ex2_sh16_r3_162_b <= not( (ex2_lvl3_shdcd160 and ex2_sh_lvl2(2) ) or (ex2_sel_special and ex2_special(162) ) ); +rr3_163: ex2_sh16_r3_163_b <= not( ex2_lvl3_shdcd160 and ex2_sh_lvl2(3) ); + +rr2_162: ex2_sh16_r2_162_b <= not( (ex2_lvl3_shdcd128 and ex2_sh_lvl2(34) ) or (ex2_lvl3_shdcd144 and ex2_sh_lvl2(18) ) ); +rr2_163: ex2_sh16_r2_163_b <= not( (ex2_lvl3_shdcd128 and ex2_sh_lvl2(35) ) or (ex2_lvl3_shdcd144 and ex2_sh_lvl2(19) ) ); + +rr1_162: ex2_sh16_r1_162_b <= not( (ex2_lvl3_shdcd096 and ex2_sh_lvl2(66) ) or (ex2_lvl3_shdcd112 and ex2_sh_lvl2(50) ) ); +rr1_163: ex2_sh16_r1_163_b <= not( (ex2_lvl3_shdcd096 and ex2_sh_lvl2(67) ) or (ex2_lvl3_shdcd112 and ex2_sh_lvl2(51) ) ); + +ro_162: ex2_sh16_162 <= not( ex2_sh16_r1_162_b and ex2_sh16_r2_162_b and ex2_sh16_r3_162_b ); +ro_163: ex2_sh16_163 <= not( ex2_sh16_r1_163_b and ex2_sh16_r2_163_b and ex2_sh16_r3_163_b ); + + + +end; -- fuq_alg_sh16 ARCHITECTURE diff --git a/rel/src/vhdl/work/fuq_alg_sh4.vhdl b/rel/src/vhdl/work/fuq_alg_sh4.vhdl new file mode 100644 index 0000000..5edc7ae --- /dev/null +++ b/rel/src/vhdl/work/fuq_alg_sh4.vhdl @@ -0,0 +1,707 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + + +entity fuq_alg_sh4 is +generic( expand_type : integer := 2 ); -- 0 - ibm tech, 1 - other ); +port( + ----------- SHIFT CONTROLS ----------------- + ex1_lvl1_shdcd000_b :in std_ulogic; + ex1_lvl1_shdcd001_b :in std_ulogic; + ex1_lvl1_shdcd002_b :in std_ulogic; + ex1_lvl1_shdcd003_b :in std_ulogic; + ex1_lvl2_shdcd000 :in std_ulogic; + ex1_lvl2_shdcd004 :in std_ulogic; + ex1_lvl2_shdcd008 :in std_ulogic; + ex1_lvl2_shdcd012 :in std_ulogic; + ex1_sel_special :in std_ulogic; + + ----------- SHIFT DATA ----------------- + ex1_b_sign :in std_ulogic; + ex1_b_expo :in std_ulogic_vector(3 to 13) ; + ex1_b_frac :in std_ulogic_vector(0 to 52) ; + + ---------- SHIFT OUTPUT --------------- + ex1_sh_lvl2 :out std_ulogic_vector(0 to 67) +); + + + +end fuq_alg_sh4; -- ENTITY + +architecture fuq_alg_sh4 of fuq_alg_sh4 is + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal ex1_special_fcfid :std_ulogic_vector(0 to 63); + signal ex1_sh_lv1 :std_ulogic_vector(0 to 55); + signal ex1_sh_lv1x_b :std_ulogic_vector(0 to 53); + signal ex1_sh_lv1y_b :std_ulogic_vector(2 to 55); + signal ex1_sh_lv2x_b :std_ulogic_vector(0 to 59); + signal ex1_sh_lv2y_b :std_ulogic_vector(8 to 67); + signal ex1_sh_lv2z_b :std_ulogic_vector(0 to 63); + + signal sh1v2dcd0_cp1 :std_ulogic; + signal sh1v3dcd0_cp1_b :std_ulogic; + signal sh1v3dcd0_cp2_b :std_ulogic; + signal sh1v4dcd0_cp1 :std_ulogic; + signal sh1v4dcd0_cp2 :std_ulogic; + signal sh1v4dcd0_cp3 :std_ulogic; + signal sh1v4dcd0_cp4 :std_ulogic; + signal sh1v2dcd1_cp1 :std_ulogic; + signal sh1v3dcd1_cp1_b :std_ulogic; + signal sh1v3dcd1_cp2_b :std_ulogic; + signal sh1v4dcd1_cp1 :std_ulogic; + signal sh1v4dcd1_cp2 :std_ulogic; + signal sh1v4dcd1_cp3 :std_ulogic; + signal sh1v4dcd1_cp4 :std_ulogic; + signal sh1v2dcd2_cp1 :std_ulogic; + signal sh1v3dcd2_cp1_b :std_ulogic; + signal sh1v3dcd2_cp2_b :std_ulogic; + signal sh1v4dcd2_cp1 :std_ulogic; + signal sh1v4dcd2_cp2 :std_ulogic; + signal sh1v4dcd2_cp3 :std_ulogic; + signal sh1v4dcd2_cp4 :std_ulogic; + signal sh1v2dcd3_cp1 :std_ulogic; + signal sh1v3dcd3_cp1_b :std_ulogic; + signal sh1v3dcd3_cp2_b :std_ulogic; + signal sh1v4dcd3_cp1 :std_ulogic; + signal sh1v4dcd3_cp2 :std_ulogic; + signal sh1v4dcd3_cp3 :std_ulogic; + signal sh1v4dcd3_cp4 :std_ulogic; + signal sh2v1dcd00_cp1_b :std_ulogic; + signal sh2v2dcd00_cp1 :std_ulogic; + signal sh2v3dcd00_cp1_b :std_ulogic; + signal sh2v3dcd00_cp2_b :std_ulogic; + signal sh2v4dcd00_cp1 :std_ulogic; + signal sh2v4dcd00_cp2 :std_ulogic; + signal sh2v4dcd00_cp3 :std_ulogic; + signal sh2v4dcd00_cp4 :std_ulogic; + signal sh2v1dcd04_cp1_b :std_ulogic; + signal sh2v2dcd04_cp1 :std_ulogic; + signal sh2v3dcd04_cp1_b :std_ulogic; + signal sh2v3dcd04_cp2_b :std_ulogic; + signal sh2v4dcd04_cp1 :std_ulogic; + signal sh2v4dcd04_cp2 :std_ulogic; + signal sh2v4dcd04_cp3 :std_ulogic; + signal sh2v4dcd04_cp4 :std_ulogic; + signal sh2v1dcd08_cp1_b :std_ulogic; + signal sh2v2dcd08_cp1 :std_ulogic; + signal sh2v3dcd08_cp1_b :std_ulogic; + signal sh2v3dcd08_cp2_b :std_ulogic; + signal sh2v4dcd08_cp1 :std_ulogic; + signal sh2v4dcd08_cp2 :std_ulogic; + signal sh2v4dcd08_cp3 :std_ulogic; + signal sh2v4dcd08_cp4 :std_ulogic; + signal sh2v1dcd12_cp1_b :std_ulogic; + signal sh2v2dcd12_cp1 :std_ulogic; + signal sh2v3dcd12_cp1_b :std_ulogic; + signal sh2v3dcd12_cp2_b :std_ulogic; + signal sh2v4dcd12_cp1 :std_ulogic; + signal sh2v4dcd12_cp2 :std_ulogic; + signal sh2v4dcd12_cp3 :std_ulogic; + signal sh2v4dcd12_cp4 :std_ulogic; + signal sh2v1dcdpp_cp1_b :std_ulogic; + signal sh2v2dcdpp_cp1 :std_ulogic; + signal sh2v3dcdpp_cp1_b :std_ulogic; + signal sh2v3dcdpp_cp2_b :std_ulogic; + signal sh2v4dcdpp_cp1 :std_ulogic; + signal sh2v4dcdpp_cp2 :std_ulogic; + signal sh2v4dcdpp_cp3 :std_ulogic; + signal sh2v4dcdpp_cp4 :std_ulogic; + + + + + + + + + +begin + + --#------------------------------------------------- + --# adjust B for fcfid specials + --#------------------------------------------------- + -- if implicit bit is off: exponent should be 0 instead of x001, x381 (1/897) + -- frac(0) is the implicit bit. + -- 0_0000_0000_0001 1 + -- 0_0011_1000_0001 897 + + ex1_special_fcfid(0) <= ex1_b_sign ; -- fcfid integer + ex1_special_fcfid(1) <= ex1_b_expo( 3) ; + ex1_special_fcfid(2) <= ex1_b_expo( 4) and ex1_b_frac(0) ; + ex1_special_fcfid(3) <= ex1_b_expo( 5) and ex1_b_frac(0) ; + ex1_special_fcfid(4) <= ex1_b_expo( 6) and ex1_b_frac(0) ; + ex1_special_fcfid(5) <= ex1_b_expo( 7) ; + ex1_special_fcfid(6) <= ex1_b_expo( 8) ; + ex1_special_fcfid(7) <= ex1_b_expo( 9) ; + ex1_special_fcfid(8) <= ex1_b_expo(10) ; + ex1_special_fcfid(9) <= ex1_b_expo(11) ; + ex1_special_fcfid(10) <= ex1_b_expo(12) ; + ex1_special_fcfid(11) <= ex1_b_expo(13) and ex1_b_frac(0) ; + ex1_special_fcfid(12 to 63) <= ex1_b_frac(1 to 52); -- fcfid integer + + +--#--------------------------------------- +--# repower the selects for sh 0/1/2/3 +--#--------------------------------------- + + s1v2d0c1: sh1v2dcd0_cp1 <= not ex1_lvl1_shdcd000_b; + s1v3d0c1: sh1v3dcd0_cp1_b <= not sh1v2dcd0_cp1 ; + s1v3d0c2: sh1v3dcd0_cp2_b <= not sh1v2dcd0_cp1 ; + s1v4d0c1: sh1v4dcd0_cp1 <= not sh1v3dcd0_cp1_b; --drive 0:13 + s1v4d0c2: sh1v4dcd0_cp2 <= not sh1v3dcd0_cp1_b; --drive 14:27 + s1v4d0c3: sh1v4dcd0_cp3 <= not sh1v3dcd0_cp2_b; --drive 28:41 + s1v4d0c4: sh1v4dcd0_cp4 <= not sh1v3dcd0_cp2_b; --drive 42:55 + + s1v2d1c1: sh1v2dcd1_cp1 <= not ex1_lvl1_shdcd001_b; + s1v3d1c1: sh1v3dcd1_cp1_b <= not sh1v2dcd1_cp1 ; + s1v3d1c2: sh1v3dcd1_cp2_b <= not sh1v2dcd1_cp1 ; + s1v4d1c1: sh1v4dcd1_cp1 <= not sh1v3dcd1_cp1_b; --drive 0:13 + s1v4d1c2: sh1v4dcd1_cp2 <= not sh1v3dcd1_cp1_b; --drive 14:27 + s1v4d1c3: sh1v4dcd1_cp3 <= not sh1v3dcd1_cp2_b; --drive 28:41 + s1v4d1c4: sh1v4dcd1_cp4 <= not sh1v3dcd1_cp2_b; --drive 42:55 + + s1v2d2c1: sh1v2dcd2_cp1 <= not ex1_lvl1_shdcd002_b; + s1v3d2c1: sh1v3dcd2_cp1_b <= not sh1v2dcd2_cp1 ; + s1v3d2c2: sh1v3dcd2_cp2_b <= not sh1v2dcd2_cp1 ; + s1v4d2c1: sh1v4dcd2_cp1 <= not sh1v3dcd2_cp1_b; --drive 0:13 + s1v4d2c2: sh1v4dcd2_cp2 <= not sh1v3dcd2_cp1_b; --drive 14:27 + s1v4d2c3: sh1v4dcd2_cp3 <= not sh1v3dcd2_cp2_b; --drive 28:41 + s1v4d2c4: sh1v4dcd2_cp4 <= not sh1v3dcd2_cp2_b; --drive 42:55 + + s1v2d3c1: sh1v2dcd3_cp1 <= not ex1_lvl1_shdcd003_b; + s1v3d3c1: sh1v3dcd3_cp1_b <= not sh1v2dcd3_cp1 ; + s1v3d3c2: sh1v3dcd3_cp2_b <= not sh1v2dcd3_cp1 ; + s1v4d3c1: sh1v4dcd3_cp1 <= not sh1v3dcd3_cp1_b; --drive 0:13 + s1v4d3c2: sh1v4dcd3_cp2 <= not sh1v3dcd3_cp1_b; --drive 14:27 + s1v4d3c3: sh1v4dcd3_cp3 <= not sh1v3dcd3_cp2_b; --drive 28:41 + s1v4d3c4: sh1v4dcd3_cp4 <= not sh1v3dcd3_cp2_b; --drive 42:55 + +--#--------------------------------------- +--# repower the selects for sh 0/4/8/12 +--#--------------------------------------- + + s2v1d00c1: sh2v1dcd00_cp1_b <= not ex1_lvl2_shdcd000; + s2v2d00c1: sh2v2dcd00_cp1 <= not sh2v1dcd00_cp1_b ; + s2v3d00c1: sh2v3dcd00_cp1_b <= not sh2v2dcd00_cp1 ; + s2v3d00c2: sh2v3dcd00_cp2_b <= not sh2v2dcd00_cp1 ; + s2v4d00c1: sh2v4dcd00_cp1 <= not sh2v3dcd00_cp1_b; --drive 0:16 + s2v4d00c2: sh2v4dcd00_cp2 <= not sh2v3dcd00_cp1_b; --drive 17:33 + s2v4d00c3: sh2v4dcd00_cp3 <= not sh2v3dcd00_cp2_b; --drive 34:50 + s2v4d00c4: sh2v4dcd00_cp4 <= not sh2v3dcd00_cp2_b; --drive 57:67 + + s2v1d04c1: sh2v1dcd04_cp1_b <= not ex1_lvl2_shdcd004; + s2v2d04c1: sh2v2dcd04_cp1 <= not sh2v1dcd04_cp1_b ; + s2v3d04c1: sh2v3dcd04_cp1_b <= not sh2v2dcd04_cp1 ; + s2v3d04c2: sh2v3dcd04_cp2_b <= not sh2v2dcd04_cp1 ; + s2v4d04c1: sh2v4dcd04_cp1 <= not sh2v3dcd04_cp1_b; --drive 0:16 + s2v4d04c2: sh2v4dcd04_cp2 <= not sh2v3dcd04_cp1_b; --drive 17:33 + s2v4d04c3: sh2v4dcd04_cp3 <= not sh2v3dcd04_cp2_b; --drive 34:50 + s2v4d04c4: sh2v4dcd04_cp4 <= not sh2v3dcd04_cp2_b; --drive 57:67 + + s2v1d08c1: sh2v1dcd08_cp1_b <= not ex1_lvl2_shdcd008; + s2v2d08c1: sh2v2dcd08_cp1 <= not sh2v1dcd08_cp1_b ; + s2v3d08c1: sh2v3dcd08_cp1_b <= not sh2v2dcd08_cp1 ; + s2v3d08c2: sh2v3dcd08_cp2_b <= not sh2v2dcd08_cp1 ; + s2v4d08c1: sh2v4dcd08_cp1 <= not sh2v3dcd08_cp1_b; --drive 0:16 + s2v4d08c2: sh2v4dcd08_cp2 <= not sh2v3dcd08_cp1_b; --drive 17:33 + s2v4d08c3: sh2v4dcd08_cp3 <= not sh2v3dcd08_cp2_b; --drive 34:50 + s2v4d08c4: sh2v4dcd08_cp4 <= not sh2v3dcd08_cp2_b; --drive 57:67 + + s2v1d12c1: sh2v1dcd12_cp1_b <= not ex1_lvl2_shdcd012; + s2v2d12c1: sh2v2dcd12_cp1 <= not sh2v1dcd12_cp1_b ; + s2v3d12c1: sh2v3dcd12_cp1_b <= not sh2v2dcd12_cp1 ; + s2v3d12c2: sh2v3dcd12_cp2_b <= not sh2v2dcd12_cp1 ; + s2v4d12c1: sh2v4dcd12_cp1 <= not sh2v3dcd12_cp1_b; --drive 0:16 + s2v4d12c2: sh2v4dcd12_cp2 <= not sh2v3dcd12_cp1_b; --drive 17:33 + s2v4d12c3: sh2v4dcd12_cp3 <= not sh2v3dcd12_cp2_b; --drive 34:50 + s2v4d12c4: sh2v4dcd12_cp4 <= not sh2v3dcd12_cp2_b; --drive 57:67 + + s2v1dppc1: sh2v1dcdpp_cp1_b <= not ex1_sel_special ; + s2v2dppc1: sh2v2dcdpp_cp1 <= not sh2v1dcdpp_cp1_b ; + s2v3dppc1: sh2v3dcdpp_cp1_b <= not sh2v2dcdpp_cp1 ; + s2v3dppc2: sh2v3dcdpp_cp2_b <= not sh2v2dcdpp_cp1 ; + s2v4dppc1: sh2v4dcdpp_cp1 <= not sh2v3dcdpp_cp1_b; --drive 0:16 + s2v4dppc2: sh2v4dcdpp_cp2 <= not sh2v3dcdpp_cp1_b; --drive 17:33 + s2v4dppc3: sh2v4dcdpp_cp3 <= not sh2v3dcdpp_cp2_b; --drive 34:50 + s2v4dppc4: sh2v4dcdpp_cp4 <= not sh2v3dcdpp_cp2_b; --drive 57:67 + +--------------------------------------- + + + lv1x_00: ex1_sh_lv1x_b(0) <= not( sh1v4dcd0_cp1 and ex1_b_frac(0) ) ; + lv1x_01: ex1_sh_lv1x_b(1) <= not( (sh1v4dcd0_cp1 and ex1_b_frac(1) ) or (sh1v4dcd1_cp1 and ex1_b_frac(0) ) ); + lv1x_02: ex1_sh_lv1x_b(2) <= not( (sh1v4dcd0_cp1 and ex1_b_frac(2) ) or (sh1v4dcd1_cp1 and ex1_b_frac(1) ) ); + lv1x_03: ex1_sh_lv1x_b(3) <= not( (sh1v4dcd0_cp1 and ex1_b_frac(3) ) or (sh1v4dcd1_cp1 and ex1_b_frac(2) ) ); + lv1x_04: ex1_sh_lv1x_b(4) <= not( (sh1v4dcd0_cp1 and ex1_b_frac(4) ) or (sh1v4dcd1_cp1 and ex1_b_frac(3) ) ); + lv1x_05: ex1_sh_lv1x_b(5) <= not( (sh1v4dcd0_cp1 and ex1_b_frac(5) ) or (sh1v4dcd1_cp1 and ex1_b_frac(4) ) ); + lv1x_06: ex1_sh_lv1x_b(6) <= not( (sh1v4dcd0_cp1 and ex1_b_frac(6) ) or (sh1v4dcd1_cp1 and ex1_b_frac(5) ) ); + lv1x_07: ex1_sh_lv1x_b(7) <= not( (sh1v4dcd0_cp1 and ex1_b_frac(7) ) or (sh1v4dcd1_cp1 and ex1_b_frac(6) ) ); + lv1x_08: ex1_sh_lv1x_b(8) <= not( (sh1v4dcd0_cp1 and ex1_b_frac(8) ) or (sh1v4dcd1_cp1 and ex1_b_frac(7) ) ); + lv1x_09: ex1_sh_lv1x_b(9) <= not( (sh1v4dcd0_cp1 and ex1_b_frac(9) ) or (sh1v4dcd1_cp1 and ex1_b_frac(8) ) ); + lv1x_10: ex1_sh_lv1x_b(10) <= not( (sh1v4dcd0_cp1 and ex1_b_frac(10) ) or (sh1v4dcd1_cp1 and ex1_b_frac(9) ) ); + lv1x_11: ex1_sh_lv1x_b(11) <= not( (sh1v4dcd0_cp1 and ex1_b_frac(11) ) or (sh1v4dcd1_cp1 and ex1_b_frac(10) ) ); + lv1x_12: ex1_sh_lv1x_b(12) <= not( (sh1v4dcd0_cp1 and ex1_b_frac(12) ) or (sh1v4dcd1_cp1 and ex1_b_frac(11) ) ); + lv1x_13: ex1_sh_lv1x_b(13) <= not( (sh1v4dcd0_cp1 and ex1_b_frac(13) ) or (sh1v4dcd1_cp1 and ex1_b_frac(12) ) ); + lv1x_14: ex1_sh_lv1x_b(14) <= not( (sh1v4dcd0_cp2 and ex1_b_frac(14) ) or (sh1v4dcd1_cp2 and ex1_b_frac(13) ) ); + lv1x_15: ex1_sh_lv1x_b(15) <= not( (sh1v4dcd0_cp2 and ex1_b_frac(15) ) or (sh1v4dcd1_cp2 and ex1_b_frac(14) ) ); + lv1x_16: ex1_sh_lv1x_b(16) <= not( (sh1v4dcd0_cp2 and ex1_b_frac(16) ) or (sh1v4dcd1_cp2 and ex1_b_frac(15) ) ); + lv1x_17: ex1_sh_lv1x_b(17) <= not( (sh1v4dcd0_cp2 and ex1_b_frac(17) ) or (sh1v4dcd1_cp2 and ex1_b_frac(16) ) ); + lv1x_18: ex1_sh_lv1x_b(18) <= not( (sh1v4dcd0_cp2 and ex1_b_frac(18) ) or (sh1v4dcd1_cp2 and ex1_b_frac(17) ) ); + lv1x_19: ex1_sh_lv1x_b(19) <= not( (sh1v4dcd0_cp2 and ex1_b_frac(19) ) or (sh1v4dcd1_cp2 and ex1_b_frac(18) ) ); + lv1x_20: ex1_sh_lv1x_b(20) <= not( (sh1v4dcd0_cp2 and ex1_b_frac(20) ) or (sh1v4dcd1_cp2 and ex1_b_frac(19) ) ); + lv1x_21: ex1_sh_lv1x_b(21) <= not( (sh1v4dcd0_cp2 and ex1_b_frac(21) ) or (sh1v4dcd1_cp2 and ex1_b_frac(20) ) ); + lv1x_22: ex1_sh_lv1x_b(22) <= not( (sh1v4dcd0_cp2 and ex1_b_frac(22) ) or (sh1v4dcd1_cp2 and ex1_b_frac(21) ) ); + lv1x_23: ex1_sh_lv1x_b(23) <= not( (sh1v4dcd0_cp2 and ex1_b_frac(23) ) or (sh1v4dcd1_cp2 and ex1_b_frac(22) ) ); + lv1x_24: ex1_sh_lv1x_b(24) <= not( (sh1v4dcd0_cp2 and ex1_b_frac(24) ) or (sh1v4dcd1_cp2 and ex1_b_frac(23) ) ); + lv1x_25: ex1_sh_lv1x_b(25) <= not( (sh1v4dcd0_cp2 and ex1_b_frac(25) ) or (sh1v4dcd1_cp2 and ex1_b_frac(24) ) ); + lv1x_26: ex1_sh_lv1x_b(26) <= not( (sh1v4dcd0_cp2 and ex1_b_frac(26) ) or (sh1v4dcd1_cp2 and ex1_b_frac(25) ) ); + lv1x_27: ex1_sh_lv1x_b(27) <= not( (sh1v4dcd0_cp2 and ex1_b_frac(27) ) or (sh1v4dcd1_cp2 and ex1_b_frac(26) ) ); + lv1x_28: ex1_sh_lv1x_b(28) <= not( (sh1v4dcd0_cp3 and ex1_b_frac(28) ) or (sh1v4dcd1_cp3 and ex1_b_frac(27) ) ); + lv1x_29: ex1_sh_lv1x_b(29) <= not( (sh1v4dcd0_cp3 and ex1_b_frac(29) ) or (sh1v4dcd1_cp3 and ex1_b_frac(28) ) ); + lv1x_30: ex1_sh_lv1x_b(30) <= not( (sh1v4dcd0_cp3 and ex1_b_frac(30) ) or (sh1v4dcd1_cp3 and ex1_b_frac(29) ) ); + lv1x_31: ex1_sh_lv1x_b(31) <= not( (sh1v4dcd0_cp3 and ex1_b_frac(31) ) or (sh1v4dcd1_cp3 and ex1_b_frac(30) ) ); + lv1x_32: ex1_sh_lv1x_b(32) <= not( (sh1v4dcd0_cp3 and ex1_b_frac(32) ) or (sh1v4dcd1_cp3 and ex1_b_frac(31) ) ); + lv1x_33: ex1_sh_lv1x_b(33) <= not( (sh1v4dcd0_cp3 and ex1_b_frac(33) ) or (sh1v4dcd1_cp3 and ex1_b_frac(32) ) ); + lv1x_34: ex1_sh_lv1x_b(34) <= not( (sh1v4dcd0_cp3 and ex1_b_frac(34) ) or (sh1v4dcd1_cp3 and ex1_b_frac(33) ) ); + lv1x_35: ex1_sh_lv1x_b(35) <= not( (sh1v4dcd0_cp3 and ex1_b_frac(35) ) or (sh1v4dcd1_cp3 and ex1_b_frac(34) ) ); + lv1x_36: ex1_sh_lv1x_b(36) <= not( (sh1v4dcd0_cp3 and ex1_b_frac(36) ) or (sh1v4dcd1_cp3 and ex1_b_frac(35) ) ); + lv1x_37: ex1_sh_lv1x_b(37) <= not( (sh1v4dcd0_cp3 and ex1_b_frac(37) ) or (sh1v4dcd1_cp3 and ex1_b_frac(36) ) ); + lv1x_38: ex1_sh_lv1x_b(38) <= not( (sh1v4dcd0_cp3 and ex1_b_frac(38) ) or (sh1v4dcd1_cp3 and ex1_b_frac(37) ) ); + lv1x_39: ex1_sh_lv1x_b(39) <= not( (sh1v4dcd0_cp3 and ex1_b_frac(39) ) or (sh1v4dcd1_cp3 and ex1_b_frac(38) ) ); + lv1x_40: ex1_sh_lv1x_b(40) <= not( (sh1v4dcd0_cp3 and ex1_b_frac(40) ) or (sh1v4dcd1_cp3 and ex1_b_frac(39) ) ); + lv1x_41: ex1_sh_lv1x_b(41) <= not( (sh1v4dcd0_cp3 and ex1_b_frac(41) ) or (sh1v4dcd1_cp3 and ex1_b_frac(40) ) ); + lv1x_42: ex1_sh_lv1x_b(42) <= not( (sh1v4dcd0_cp4 and ex1_b_frac(42) ) or (sh1v4dcd1_cp4 and ex1_b_frac(41) ) ); + lv1x_43: ex1_sh_lv1x_b(43) <= not( (sh1v4dcd0_cp4 and ex1_b_frac(43) ) or (sh1v4dcd1_cp4 and ex1_b_frac(42) ) ); + lv1x_44: ex1_sh_lv1x_b(44) <= not( (sh1v4dcd0_cp4 and ex1_b_frac(44) ) or (sh1v4dcd1_cp4 and ex1_b_frac(43) ) ); + lv1x_45: ex1_sh_lv1x_b(45) <= not( (sh1v4dcd0_cp4 and ex1_b_frac(45) ) or (sh1v4dcd1_cp4 and ex1_b_frac(44) ) ); + lv1x_46: ex1_sh_lv1x_b(46) <= not( (sh1v4dcd0_cp4 and ex1_b_frac(46) ) or (sh1v4dcd1_cp4 and ex1_b_frac(45) ) ); + lv1x_47: ex1_sh_lv1x_b(47) <= not( (sh1v4dcd0_cp4 and ex1_b_frac(47) ) or (sh1v4dcd1_cp4 and ex1_b_frac(46) ) ); + lv1x_48: ex1_sh_lv1x_b(48) <= not( (sh1v4dcd0_cp4 and ex1_b_frac(48) ) or (sh1v4dcd1_cp4 and ex1_b_frac(47) ) ); + lv1x_49: ex1_sh_lv1x_b(49) <= not( (sh1v4dcd0_cp4 and ex1_b_frac(49) ) or (sh1v4dcd1_cp4 and ex1_b_frac(48) ) ); + lv1x_50: ex1_sh_lv1x_b(50) <= not( (sh1v4dcd0_cp4 and ex1_b_frac(50) ) or (sh1v4dcd1_cp4 and ex1_b_frac(49) ) ); + lv1x_51: ex1_sh_lv1x_b(51) <= not( (sh1v4dcd0_cp4 and ex1_b_frac(51) ) or (sh1v4dcd1_cp4 and ex1_b_frac(50) ) ); + lv1x_52: ex1_sh_lv1x_b(52) <= not( (sh1v4dcd0_cp4 and ex1_b_frac(52) ) or (sh1v4dcd1_cp4 and ex1_b_frac(51) ) ); + lv1x_53: ex1_sh_lv1x_b(53) <= not( sh1v4dcd1_cp4 and ex1_b_frac(52) ); + + + + lv1y_02: ex1_sh_lv1y_b(2) <= not( sh1v4dcd2_cp1 and ex1_b_frac(0) ) ; + lv1y_03: ex1_sh_lv1y_b(3) <= not( (sh1v4dcd2_cp1 and ex1_b_frac(1) ) or (sh1v4dcd3_cp1 and ex1_b_frac(0) ) ); + lv1y_04: ex1_sh_lv1y_b(4) <= not( (sh1v4dcd2_cp1 and ex1_b_frac(2) ) or (sh1v4dcd3_cp1 and ex1_b_frac(1) ) ); + lv1y_05: ex1_sh_lv1y_b(5) <= not( (sh1v4dcd2_cp1 and ex1_b_frac(3) ) or (sh1v4dcd3_cp1 and ex1_b_frac(2) ) ); + lv1y_06: ex1_sh_lv1y_b(6) <= not( (sh1v4dcd2_cp1 and ex1_b_frac(4) ) or (sh1v4dcd3_cp1 and ex1_b_frac(3) ) ); + lv1y_07: ex1_sh_lv1y_b(7) <= not( (sh1v4dcd2_cp1 and ex1_b_frac(5) ) or (sh1v4dcd3_cp1 and ex1_b_frac(4) ) ); + lv1y_08: ex1_sh_lv1y_b(8) <= not( (sh1v4dcd2_cp1 and ex1_b_frac(6) ) or (sh1v4dcd3_cp1 and ex1_b_frac(5) ) ); + lv1y_09: ex1_sh_lv1y_b(9) <= not( (sh1v4dcd2_cp1 and ex1_b_frac(7) ) or (sh1v4dcd3_cp1 and ex1_b_frac(6) ) ); + lv1y_10: ex1_sh_lv1y_b(10) <= not( (sh1v4dcd2_cp1 and ex1_b_frac(8) ) or (sh1v4dcd3_cp1 and ex1_b_frac(7) ) ); + lv1y_11: ex1_sh_lv1y_b(11) <= not( (sh1v4dcd2_cp1 and ex1_b_frac(9) ) or (sh1v4dcd3_cp1 and ex1_b_frac(8) ) ); + lv1y_12: ex1_sh_lv1y_b(12) <= not( (sh1v4dcd2_cp1 and ex1_b_frac(10) ) or (sh1v4dcd3_cp1 and ex1_b_frac(9) ) ); + lv1y_13: ex1_sh_lv1y_b(13) <= not( (sh1v4dcd2_cp1 and ex1_b_frac(11) ) or (sh1v4dcd3_cp1 and ex1_b_frac(10) ) ); + lv1y_14: ex1_sh_lv1y_b(14) <= not( (sh1v4dcd2_cp2 and ex1_b_frac(12) ) or (sh1v4dcd3_cp2 and ex1_b_frac(11) ) ); + lv1y_15: ex1_sh_lv1y_b(15) <= not( (sh1v4dcd2_cp2 and ex1_b_frac(13) ) or (sh1v4dcd3_cp2 and ex1_b_frac(12) ) ); + lv1y_16: ex1_sh_lv1y_b(16) <= not( (sh1v4dcd2_cp2 and ex1_b_frac(14) ) or (sh1v4dcd3_cp2 and ex1_b_frac(13) ) ); + lv1y_17: ex1_sh_lv1y_b(17) <= not( (sh1v4dcd2_cp2 and ex1_b_frac(15) ) or (sh1v4dcd3_cp2 and ex1_b_frac(14) ) ); + lv1y_18: ex1_sh_lv1y_b(18) <= not( (sh1v4dcd2_cp2 and ex1_b_frac(16) ) or (sh1v4dcd3_cp2 and ex1_b_frac(15) ) ); + lv1y_19: ex1_sh_lv1y_b(19) <= not( (sh1v4dcd2_cp2 and ex1_b_frac(17) ) or (sh1v4dcd3_cp2 and ex1_b_frac(16) ) ); + lv1y_20: ex1_sh_lv1y_b(20) <= not( (sh1v4dcd2_cp2 and ex1_b_frac(18) ) or (sh1v4dcd3_cp2 and ex1_b_frac(17) ) ); + lv1y_21: ex1_sh_lv1y_b(21) <= not( (sh1v4dcd2_cp2 and ex1_b_frac(19) ) or (sh1v4dcd3_cp2 and ex1_b_frac(18) ) ); + lv1y_22: ex1_sh_lv1y_b(22) <= not( (sh1v4dcd2_cp2 and ex1_b_frac(20) ) or (sh1v4dcd3_cp2 and ex1_b_frac(19) ) ); + lv1y_23: ex1_sh_lv1y_b(23) <= not( (sh1v4dcd2_cp2 and ex1_b_frac(21) ) or (sh1v4dcd3_cp2 and ex1_b_frac(20) ) ); + lv1y_24: ex1_sh_lv1y_b(24) <= not( (sh1v4dcd2_cp2 and ex1_b_frac(22) ) or (sh1v4dcd3_cp2 and ex1_b_frac(21) ) ); + lv1y_25: ex1_sh_lv1y_b(25) <= not( (sh1v4dcd2_cp2 and ex1_b_frac(23) ) or (sh1v4dcd3_cp2 and ex1_b_frac(22) ) ); + lv1y_26: ex1_sh_lv1y_b(26) <= not( (sh1v4dcd2_cp2 and ex1_b_frac(24) ) or (sh1v4dcd3_cp2 and ex1_b_frac(23) ) ); + lv1y_27: ex1_sh_lv1y_b(27) <= not( (sh1v4dcd2_cp2 and ex1_b_frac(25) ) or (sh1v4dcd3_cp2 and ex1_b_frac(24) ) ); + lv1y_28: ex1_sh_lv1y_b(28) <= not( (sh1v4dcd2_cp3 and ex1_b_frac(26) ) or (sh1v4dcd3_cp3 and ex1_b_frac(25) ) ); + lv1y_29: ex1_sh_lv1y_b(29) <= not( (sh1v4dcd2_cp3 and ex1_b_frac(27) ) or (sh1v4dcd3_cp3 and ex1_b_frac(26) ) ); + lv1y_30: ex1_sh_lv1y_b(30) <= not( (sh1v4dcd2_cp3 and ex1_b_frac(28) ) or (sh1v4dcd3_cp3 and ex1_b_frac(27) ) ); + lv1y_31: ex1_sh_lv1y_b(31) <= not( (sh1v4dcd2_cp3 and ex1_b_frac(29) ) or (sh1v4dcd3_cp3 and ex1_b_frac(28) ) ); + lv1y_32: ex1_sh_lv1y_b(32) <= not( (sh1v4dcd2_cp3 and ex1_b_frac(30) ) or (sh1v4dcd3_cp3 and ex1_b_frac(29) ) ); + lv1y_33: ex1_sh_lv1y_b(33) <= not( (sh1v4dcd2_cp3 and ex1_b_frac(31) ) or (sh1v4dcd3_cp3 and ex1_b_frac(30) ) ); + lv1y_34: ex1_sh_lv1y_b(34) <= not( (sh1v4dcd2_cp3 and ex1_b_frac(32) ) or (sh1v4dcd3_cp3 and ex1_b_frac(31) ) ); + lv1y_35: ex1_sh_lv1y_b(35) <= not( (sh1v4dcd2_cp3 and ex1_b_frac(33) ) or (sh1v4dcd3_cp3 and ex1_b_frac(32) ) ); + lv1y_36: ex1_sh_lv1y_b(36) <= not( (sh1v4dcd2_cp3 and ex1_b_frac(34) ) or (sh1v4dcd3_cp3 and ex1_b_frac(33) ) ); + lv1y_37: ex1_sh_lv1y_b(37) <= not( (sh1v4dcd2_cp3 and ex1_b_frac(35) ) or (sh1v4dcd3_cp3 and ex1_b_frac(34) ) ); + lv1y_38: ex1_sh_lv1y_b(38) <= not( (sh1v4dcd2_cp3 and ex1_b_frac(36) ) or (sh1v4dcd3_cp3 and ex1_b_frac(35) ) ); + lv1y_39: ex1_sh_lv1y_b(39) <= not( (sh1v4dcd2_cp3 and ex1_b_frac(37) ) or (sh1v4dcd3_cp3 and ex1_b_frac(36) ) ); + lv1y_40: ex1_sh_lv1y_b(40) <= not( (sh1v4dcd2_cp3 and ex1_b_frac(38) ) or (sh1v4dcd3_cp3 and ex1_b_frac(37) ) ); + lv1y_41: ex1_sh_lv1y_b(41) <= not( (sh1v4dcd2_cp4 and ex1_b_frac(39) ) or (sh1v4dcd3_cp4 and ex1_b_frac(38) ) ); + lv1y_42: ex1_sh_lv1y_b(42) <= not( (sh1v4dcd2_cp4 and ex1_b_frac(40) ) or (sh1v4dcd3_cp4 and ex1_b_frac(39) ) ); + lv1y_43: ex1_sh_lv1y_b(43) <= not( (sh1v4dcd2_cp4 and ex1_b_frac(41) ) or (sh1v4dcd3_cp4 and ex1_b_frac(40) ) ); + lv1y_44: ex1_sh_lv1y_b(44) <= not( (sh1v4dcd2_cp4 and ex1_b_frac(42) ) or (sh1v4dcd3_cp4 and ex1_b_frac(41) ) ); + lv1y_45: ex1_sh_lv1y_b(45) <= not( (sh1v4dcd2_cp4 and ex1_b_frac(43) ) or (sh1v4dcd3_cp4 and ex1_b_frac(42) ) ); + lv1y_46: ex1_sh_lv1y_b(46) <= not( (sh1v4dcd2_cp4 and ex1_b_frac(44) ) or (sh1v4dcd3_cp4 and ex1_b_frac(43) ) ); + lv1y_47: ex1_sh_lv1y_b(47) <= not( (sh1v4dcd2_cp4 and ex1_b_frac(45) ) or (sh1v4dcd3_cp4 and ex1_b_frac(44) ) ); + lv1y_48: ex1_sh_lv1y_b(48) <= not( (sh1v4dcd2_cp4 and ex1_b_frac(46) ) or (sh1v4dcd3_cp4 and ex1_b_frac(45) ) ); + lv1y_49: ex1_sh_lv1y_b(49) <= not( (sh1v4dcd2_cp4 and ex1_b_frac(47) ) or (sh1v4dcd3_cp4 and ex1_b_frac(46) ) ); + lv1y_50: ex1_sh_lv1y_b(50) <= not( (sh1v4dcd2_cp4 and ex1_b_frac(48) ) or (sh1v4dcd3_cp4 and ex1_b_frac(47) ) ); + lv1y_51: ex1_sh_lv1y_b(51) <= not( (sh1v4dcd2_cp4 and ex1_b_frac(49) ) or (sh1v4dcd3_cp4 and ex1_b_frac(48) ) ); + lv1y_52: ex1_sh_lv1y_b(52) <= not( (sh1v4dcd2_cp4 and ex1_b_frac(50) ) or (sh1v4dcd3_cp4 and ex1_b_frac(49) ) ); + lv1y_53: ex1_sh_lv1y_b(53) <= not( (sh1v4dcd2_cp4 and ex1_b_frac(51) ) or (sh1v4dcd3_cp4 and ex1_b_frac(50) ) ); + lv1y_54: ex1_sh_lv1y_b(54) <= not( (sh1v4dcd2_cp4 and ex1_b_frac(52) ) or (sh1v4dcd3_cp4 and ex1_b_frac(51) ) ); + lv1y_55: ex1_sh_lv1y_b(55) <= not( sh1v4dcd3_cp4 and ex1_b_frac(52) ); + + lv1_00: ex1_sh_lv1(0) <= not( ex1_sh_lv1x_b(0) ); + lv1_01: ex1_sh_lv1(1) <= not( ex1_sh_lv1x_b(1) ); + lv1_02: ex1_sh_lv1(2) <= not( ex1_sh_lv1x_b(2) and ex1_sh_lv1y_b(2) ); + lv1_03: ex1_sh_lv1(3) <= not( ex1_sh_lv1x_b(3) and ex1_sh_lv1y_b(3) ); + lv1_04: ex1_sh_lv1(4) <= not( ex1_sh_lv1x_b(4) and ex1_sh_lv1y_b(4) ); + lv1_05: ex1_sh_lv1(5) <= not( ex1_sh_lv1x_b(5) and ex1_sh_lv1y_b(5) ); + lv1_06: ex1_sh_lv1(6) <= not( ex1_sh_lv1x_b(6) and ex1_sh_lv1y_b(6) ); + lv1_07: ex1_sh_lv1(7) <= not( ex1_sh_lv1x_b(7) and ex1_sh_lv1y_b(7) ); + lv1_08: ex1_sh_lv1(8) <= not( ex1_sh_lv1x_b(8) and ex1_sh_lv1y_b(8) ); + lv1_09: ex1_sh_lv1(9) <= not( ex1_sh_lv1x_b(9) and ex1_sh_lv1y_b(9) ); + lv1_10: ex1_sh_lv1(10) <= not( ex1_sh_lv1x_b(10) and ex1_sh_lv1y_b(10) ); + lv1_11: ex1_sh_lv1(11) <= not( ex1_sh_lv1x_b(11) and ex1_sh_lv1y_b(11) ); + lv1_12: ex1_sh_lv1(12) <= not( ex1_sh_lv1x_b(12) and ex1_sh_lv1y_b(12) ); + lv1_13: ex1_sh_lv1(13) <= not( ex1_sh_lv1x_b(13) and ex1_sh_lv1y_b(13) ); + lv1_14: ex1_sh_lv1(14) <= not( ex1_sh_lv1x_b(14) and ex1_sh_lv1y_b(14) ); + lv1_15: ex1_sh_lv1(15) <= not( ex1_sh_lv1x_b(15) and ex1_sh_lv1y_b(15) ); + lv1_16: ex1_sh_lv1(16) <= not( ex1_sh_lv1x_b(16) and ex1_sh_lv1y_b(16) ); + lv1_17: ex1_sh_lv1(17) <= not( ex1_sh_lv1x_b(17) and ex1_sh_lv1y_b(17) ); + lv1_18: ex1_sh_lv1(18) <= not( ex1_sh_lv1x_b(18) and ex1_sh_lv1y_b(18) ); + lv1_19: ex1_sh_lv1(19) <= not( ex1_sh_lv1x_b(19) and ex1_sh_lv1y_b(19) ); + lv1_20: ex1_sh_lv1(20) <= not( ex1_sh_lv1x_b(20) and ex1_sh_lv1y_b(20) ); + lv1_21: ex1_sh_lv1(21) <= not( ex1_sh_lv1x_b(21) and ex1_sh_lv1y_b(21) ); + lv1_22: ex1_sh_lv1(22) <= not( ex1_sh_lv1x_b(22) and ex1_sh_lv1y_b(22) ); + lv1_23: ex1_sh_lv1(23) <= not( ex1_sh_lv1x_b(23) and ex1_sh_lv1y_b(23) ); + lv1_24: ex1_sh_lv1(24) <= not( ex1_sh_lv1x_b(24) and ex1_sh_lv1y_b(24) ); + lv1_25: ex1_sh_lv1(25) <= not( ex1_sh_lv1x_b(25) and ex1_sh_lv1y_b(25) ); + lv1_26: ex1_sh_lv1(26) <= not( ex1_sh_lv1x_b(26) and ex1_sh_lv1y_b(26) ); + lv1_27: ex1_sh_lv1(27) <= not( ex1_sh_lv1x_b(27) and ex1_sh_lv1y_b(27) ); + lv1_28: ex1_sh_lv1(28) <= not( ex1_sh_lv1x_b(28) and ex1_sh_lv1y_b(28) ); + lv1_29: ex1_sh_lv1(29) <= not( ex1_sh_lv1x_b(29) and ex1_sh_lv1y_b(29) ); + lv1_30: ex1_sh_lv1(30) <= not( ex1_sh_lv1x_b(30) and ex1_sh_lv1y_b(30) ); + lv1_31: ex1_sh_lv1(31) <= not( ex1_sh_lv1x_b(31) and ex1_sh_lv1y_b(31) ); + lv1_32: ex1_sh_lv1(32) <= not( ex1_sh_lv1x_b(32) and ex1_sh_lv1y_b(32) ); + lv1_33: ex1_sh_lv1(33) <= not( ex1_sh_lv1x_b(33) and ex1_sh_lv1y_b(33) ); + lv1_34: ex1_sh_lv1(34) <= not( ex1_sh_lv1x_b(34) and ex1_sh_lv1y_b(34) ); + lv1_35: ex1_sh_lv1(35) <= not( ex1_sh_lv1x_b(35) and ex1_sh_lv1y_b(35) ); + lv1_36: ex1_sh_lv1(36) <= not( ex1_sh_lv1x_b(36) and ex1_sh_lv1y_b(36) ); + lv1_37: ex1_sh_lv1(37) <= not( ex1_sh_lv1x_b(37) and ex1_sh_lv1y_b(37) ); + lv1_38: ex1_sh_lv1(38) <= not( ex1_sh_lv1x_b(38) and ex1_sh_lv1y_b(38) ); + lv1_39: ex1_sh_lv1(39) <= not( ex1_sh_lv1x_b(39) and ex1_sh_lv1y_b(39) ); + lv1_40: ex1_sh_lv1(40) <= not( ex1_sh_lv1x_b(40) and ex1_sh_lv1y_b(40) ); + lv1_41: ex1_sh_lv1(41) <= not( ex1_sh_lv1x_b(41) and ex1_sh_lv1y_b(41) ); + lv1_42: ex1_sh_lv1(42) <= not( ex1_sh_lv1x_b(42) and ex1_sh_lv1y_b(42) ); + lv1_43: ex1_sh_lv1(43) <= not( ex1_sh_lv1x_b(43) and ex1_sh_lv1y_b(43) ); + lv1_44: ex1_sh_lv1(44) <= not( ex1_sh_lv1x_b(44) and ex1_sh_lv1y_b(44) ); + lv1_45: ex1_sh_lv1(45) <= not( ex1_sh_lv1x_b(45) and ex1_sh_lv1y_b(45) ); + lv1_46: ex1_sh_lv1(46) <= not( ex1_sh_lv1x_b(46) and ex1_sh_lv1y_b(46) ); + lv1_47: ex1_sh_lv1(47) <= not( ex1_sh_lv1x_b(47) and ex1_sh_lv1y_b(47) ); + lv1_48: ex1_sh_lv1(48) <= not( ex1_sh_lv1x_b(48) and ex1_sh_lv1y_b(48) ); + lv1_49: ex1_sh_lv1(49) <= not( ex1_sh_lv1x_b(49) and ex1_sh_lv1y_b(49) ); + lv1_50: ex1_sh_lv1(50) <= not( ex1_sh_lv1x_b(50) and ex1_sh_lv1y_b(50) ); + lv1_51: ex1_sh_lv1(51) <= not( ex1_sh_lv1x_b(51) and ex1_sh_lv1y_b(51) ); + lv1_52: ex1_sh_lv1(52) <= not( ex1_sh_lv1x_b(52) and ex1_sh_lv1y_b(52) ); + lv1_53: ex1_sh_lv1(53) <= not( ex1_sh_lv1x_b(53) and ex1_sh_lv1y_b(53) ); + lv1_54: ex1_sh_lv1(54) <= not( ex1_sh_lv1y_b(54) ); + lv1_55: ex1_sh_lv1(55) <= not( ex1_sh_lv1y_b(55) ); + +---------------------------------------------------------------------------------------------- + + + lv2x_00: ex1_sh_lv2x_b(0) <= not( sh2v4dcd00_cp1 and ex1_sh_lv1(0) ); + lv2x_01: ex1_sh_lv2x_b(1) <= not( sh2v4dcd00_cp1 and ex1_sh_lv1(1) ); + lv2x_02: ex1_sh_lv2x_b(2) <= not( sh2v4dcd00_cp1 and ex1_sh_lv1(2) ); + lv2x_03: ex1_sh_lv2x_b(3) <= not( sh2v4dcd00_cp1 and ex1_sh_lv1(3) ); + lv2x_04: ex1_sh_lv2x_b(4) <= not( (sh2v4dcd00_cp1 and ex1_sh_lv1(4) ) or (sh2v4dcd04_cp1 and ex1_sh_lv1(0) ) ); + lv2x_05: ex1_sh_lv2x_b(5) <= not( (sh2v4dcd00_cp1 and ex1_sh_lv1(5) ) or (sh2v4dcd04_cp1 and ex1_sh_lv1(1) ) ); + lv2x_06: ex1_sh_lv2x_b(6) <= not( (sh2v4dcd00_cp1 and ex1_sh_lv1(6) ) or (sh2v4dcd04_cp1 and ex1_sh_lv1(2) ) ); + lv2x_07: ex1_sh_lv2x_b(7) <= not( (sh2v4dcd00_cp1 and ex1_sh_lv1(7) ) or (sh2v4dcd04_cp1 and ex1_sh_lv1(3) ) ); + lv2x_08: ex1_sh_lv2x_b(8) <= not( (sh2v4dcd00_cp1 and ex1_sh_lv1(8) ) or (sh2v4dcd04_cp1 and ex1_sh_lv1(4) ) ); + lv2x_09: ex1_sh_lv2x_b(9) <= not( (sh2v4dcd00_cp1 and ex1_sh_lv1(9) ) or (sh2v4dcd04_cp1 and ex1_sh_lv1(5) ) ); + lv2x_10: ex1_sh_lv2x_b(10) <= not( (sh2v4dcd00_cp1 and ex1_sh_lv1(10) ) or (sh2v4dcd04_cp1 and ex1_sh_lv1(6) ) ); + lv2x_11: ex1_sh_lv2x_b(11) <= not( (sh2v4dcd00_cp1 and ex1_sh_lv1(11) ) or (sh2v4dcd04_cp1 and ex1_sh_lv1(7) ) ); + lv2x_12: ex1_sh_lv2x_b(12) <= not( (sh2v4dcd00_cp1 and ex1_sh_lv1(12) ) or (sh2v4dcd04_cp1 and ex1_sh_lv1(8) ) ); + lv2x_13: ex1_sh_lv2x_b(13) <= not( (sh2v4dcd00_cp1 and ex1_sh_lv1(13) ) or (sh2v4dcd04_cp1 and ex1_sh_lv1(9) ) ); + lv2x_14: ex1_sh_lv2x_b(14) <= not( (sh2v4dcd00_cp1 and ex1_sh_lv1(14) ) or (sh2v4dcd04_cp1 and ex1_sh_lv1(10) ) ); + lv2x_15: ex1_sh_lv2x_b(15) <= not( (sh2v4dcd00_cp2 and ex1_sh_lv1(15) ) or (sh2v4dcd04_cp2 and ex1_sh_lv1(11) ) ); + lv2x_16: ex1_sh_lv2x_b(16) <= not( (sh2v4dcd00_cp2 and ex1_sh_lv1(16) ) or (sh2v4dcd04_cp2 and ex1_sh_lv1(12) ) ); + lv2x_17: ex1_sh_lv2x_b(17) <= not( (sh2v4dcd00_cp2 and ex1_sh_lv1(17) ) or (sh2v4dcd04_cp2 and ex1_sh_lv1(13) ) ); + lv2x_18: ex1_sh_lv2x_b(18) <= not( (sh2v4dcd00_cp2 and ex1_sh_lv1(18) ) or (sh2v4dcd04_cp2 and ex1_sh_lv1(14) ) ); + lv2x_19: ex1_sh_lv2x_b(19) <= not( (sh2v4dcd00_cp2 and ex1_sh_lv1(19) ) or (sh2v4dcd04_cp2 and ex1_sh_lv1(15) ) ); + lv2x_20: ex1_sh_lv2x_b(20) <= not( (sh2v4dcd00_cp2 and ex1_sh_lv1(20) ) or (sh2v4dcd04_cp2 and ex1_sh_lv1(16) ) ); + lv2x_21: ex1_sh_lv2x_b(21) <= not( (sh2v4dcd00_cp2 and ex1_sh_lv1(21) ) or (sh2v4dcd04_cp2 and ex1_sh_lv1(17) ) ); + lv2x_22: ex1_sh_lv2x_b(22) <= not( (sh2v4dcd00_cp2 and ex1_sh_lv1(22) ) or (sh2v4dcd04_cp2 and ex1_sh_lv1(18) ) ); + lv2x_23: ex1_sh_lv2x_b(23) <= not( (sh2v4dcd00_cp2 and ex1_sh_lv1(23) ) or (sh2v4dcd04_cp2 and ex1_sh_lv1(19) ) ); + lv2x_24: ex1_sh_lv2x_b(24) <= not( (sh2v4dcd00_cp2 and ex1_sh_lv1(24) ) or (sh2v4dcd04_cp2 and ex1_sh_lv1(20) ) ); + lv2x_25: ex1_sh_lv2x_b(25) <= not( (sh2v4dcd00_cp2 and ex1_sh_lv1(25) ) or (sh2v4dcd04_cp2 and ex1_sh_lv1(21) ) ); + lv2x_26: ex1_sh_lv2x_b(26) <= not( (sh2v4dcd00_cp2 and ex1_sh_lv1(26) ) or (sh2v4dcd04_cp2 and ex1_sh_lv1(22) ) ); + lv2x_27: ex1_sh_lv2x_b(27) <= not( (sh2v4dcd00_cp2 and ex1_sh_lv1(27) ) or (sh2v4dcd04_cp2 and ex1_sh_lv1(23) ) ); + lv2x_28: ex1_sh_lv2x_b(28) <= not( (sh2v4dcd00_cp2 and ex1_sh_lv1(28) ) or (sh2v4dcd04_cp2 and ex1_sh_lv1(24) ) ); + lv2x_29: ex1_sh_lv2x_b(29) <= not( (sh2v4dcd00_cp2 and ex1_sh_lv1(29) ) or (sh2v4dcd04_cp2 and ex1_sh_lv1(25) ) ); + lv2x_30: ex1_sh_lv2x_b(30) <= not( (sh2v4dcd00_cp3 and ex1_sh_lv1(30) ) or (sh2v4dcd04_cp3 and ex1_sh_lv1(26) ) ); + lv2x_31: ex1_sh_lv2x_b(31) <= not( (sh2v4dcd00_cp3 and ex1_sh_lv1(31) ) or (sh2v4dcd04_cp3 and ex1_sh_lv1(27) ) ); + lv2x_32: ex1_sh_lv2x_b(32) <= not( (sh2v4dcd00_cp3 and ex1_sh_lv1(32) ) or (sh2v4dcd04_cp3 and ex1_sh_lv1(28) ) ); + lv2x_33: ex1_sh_lv2x_b(33) <= not( (sh2v4dcd00_cp3 and ex1_sh_lv1(33) ) or (sh2v4dcd04_cp3 and ex1_sh_lv1(29) ) ); + lv2x_34: ex1_sh_lv2x_b(34) <= not( (sh2v4dcd00_cp3 and ex1_sh_lv1(34) ) or (sh2v4dcd04_cp3 and ex1_sh_lv1(30) ) ); + lv2x_35: ex1_sh_lv2x_b(35) <= not( (sh2v4dcd00_cp3 and ex1_sh_lv1(35) ) or (sh2v4dcd04_cp3 and ex1_sh_lv1(31) ) ); + lv2x_36: ex1_sh_lv2x_b(36) <= not( (sh2v4dcd00_cp3 and ex1_sh_lv1(36) ) or (sh2v4dcd04_cp3 and ex1_sh_lv1(32) ) ); + lv2x_37: ex1_sh_lv2x_b(37) <= not( (sh2v4dcd00_cp3 and ex1_sh_lv1(37) ) or (sh2v4dcd04_cp3 and ex1_sh_lv1(33) ) ); + lv2x_38: ex1_sh_lv2x_b(38) <= not( (sh2v4dcd00_cp3 and ex1_sh_lv1(38) ) or (sh2v4dcd04_cp3 and ex1_sh_lv1(34) ) ); + lv2x_39: ex1_sh_lv2x_b(39) <= not( (sh2v4dcd00_cp3 and ex1_sh_lv1(39) ) or (sh2v4dcd04_cp3 and ex1_sh_lv1(35) ) ); + lv2x_40: ex1_sh_lv2x_b(40) <= not( (sh2v4dcd00_cp3 and ex1_sh_lv1(40) ) or (sh2v4dcd04_cp3 and ex1_sh_lv1(36) ) ); + lv2x_41: ex1_sh_lv2x_b(41) <= not( (sh2v4dcd00_cp3 and ex1_sh_lv1(41) ) or (sh2v4dcd04_cp3 and ex1_sh_lv1(37) ) ); + lv2x_42: ex1_sh_lv2x_b(42) <= not( (sh2v4dcd00_cp3 and ex1_sh_lv1(42) ) or (sh2v4dcd04_cp3 and ex1_sh_lv1(38) ) ); + lv2x_43: ex1_sh_lv2x_b(43) <= not( (sh2v4dcd00_cp3 and ex1_sh_lv1(43) ) or (sh2v4dcd04_cp3 and ex1_sh_lv1(39) ) ); + lv2x_44: ex1_sh_lv2x_b(44) <= not( (sh2v4dcd00_cp3 and ex1_sh_lv1(44) ) or (sh2v4dcd04_cp3 and ex1_sh_lv1(40) ) ); + lv2x_45: ex1_sh_lv2x_b(45) <= not( (sh2v4dcd00_cp4 and ex1_sh_lv1(45) ) or (sh2v4dcd04_cp4 and ex1_sh_lv1(41) ) ); + lv2x_46: ex1_sh_lv2x_b(46) <= not( (sh2v4dcd00_cp4 and ex1_sh_lv1(46) ) or (sh2v4dcd04_cp4 and ex1_sh_lv1(42) ) ); + lv2x_47: ex1_sh_lv2x_b(47) <= not( (sh2v4dcd00_cp4 and ex1_sh_lv1(47) ) or (sh2v4dcd04_cp4 and ex1_sh_lv1(43) ) ); + lv2x_48: ex1_sh_lv2x_b(48) <= not( (sh2v4dcd00_cp4 and ex1_sh_lv1(48) ) or (sh2v4dcd04_cp4 and ex1_sh_lv1(44) ) ); + lv2x_49: ex1_sh_lv2x_b(49) <= not( (sh2v4dcd00_cp4 and ex1_sh_lv1(49) ) or (sh2v4dcd04_cp4 and ex1_sh_lv1(45) ) ); + lv2x_50: ex1_sh_lv2x_b(50) <= not( (sh2v4dcd00_cp4 and ex1_sh_lv1(50) ) or (sh2v4dcd04_cp4 and ex1_sh_lv1(46) ) ); + lv2x_51: ex1_sh_lv2x_b(51) <= not( (sh2v4dcd00_cp4 and ex1_sh_lv1(51) ) or (sh2v4dcd04_cp4 and ex1_sh_lv1(47) ) ); + lv2x_52: ex1_sh_lv2x_b(52) <= not( (sh2v4dcd00_cp4 and ex1_sh_lv1(52) ) or (sh2v4dcd04_cp4 and ex1_sh_lv1(48) ) ); + lv2x_53: ex1_sh_lv2x_b(53) <= not( (sh2v4dcd00_cp4 and ex1_sh_lv1(53) ) or (sh2v4dcd04_cp4 and ex1_sh_lv1(49) ) ); + lv2x_54: ex1_sh_lv2x_b(54) <= not( (sh2v4dcd00_cp4 and ex1_sh_lv1(54) ) or (sh2v4dcd04_cp4 and ex1_sh_lv1(50) ) ); + lv2x_55: ex1_sh_lv2x_b(55) <= not( (sh2v4dcd00_cp4 and ex1_sh_lv1(55) ) or (sh2v4dcd04_cp4 and ex1_sh_lv1(51) ) ); + lv2x_56: ex1_sh_lv2x_b(56) <= not( sh2v4dcd04_cp4 and ex1_sh_lv1(52) ); + lv2x_57: ex1_sh_lv2x_b(57) <= not( sh2v4dcd04_cp4 and ex1_sh_lv1(53) ); + lv2x_58: ex1_sh_lv2x_b(58) <= not( sh2v4dcd04_cp4 and ex1_sh_lv1(54) ); + lv2x_59: ex1_sh_lv2x_b(59) <= not( sh2v4dcd04_cp4 and ex1_sh_lv1(55) ); + + + + lv2y_08: ex1_sh_lv2y_b(8) <= not( sh2v4dcd08_cp1 and ex1_sh_lv1(0) ); + lv2y_09: ex1_sh_lv2y_b(9) <= not( sh2v4dcd08_cp1 and ex1_sh_lv1(1) ); + lv2y_10: ex1_sh_lv2y_b(10) <= not( sh2v4dcd08_cp1 and ex1_sh_lv1(2) ); + lv2y_11: ex1_sh_lv2y_b(11) <= not( sh2v4dcd08_cp1 and ex1_sh_lv1(3) ); + lv2y_12: ex1_sh_lv2y_b(12) <= not( (sh2v4dcd08_cp1 and ex1_sh_lv1(4) ) or (sh2v4dcd12_cp1 and ex1_sh_lv1(0) ) ); + lv2y_13: ex1_sh_lv2y_b(13) <= not( (sh2v4dcd08_cp1 and ex1_sh_lv1(5) ) or (sh2v4dcd12_cp1 and ex1_sh_lv1(1) ) ); + lv2y_14: ex1_sh_lv2y_b(14) <= not( (sh2v4dcd08_cp1 and ex1_sh_lv1(6) ) or (sh2v4dcd12_cp1 and ex1_sh_lv1(2) ) ); + lv2y_15: ex1_sh_lv2y_b(15) <= not( (sh2v4dcd08_cp1 and ex1_sh_lv1(7) ) or (sh2v4dcd12_cp1 and ex1_sh_lv1(3) ) ); + lv2y_16: ex1_sh_lv2y_b(16) <= not( (sh2v4dcd08_cp1 and ex1_sh_lv1(8) ) or (sh2v4dcd12_cp1 and ex1_sh_lv1(4) ) ); + lv2y_17: ex1_sh_lv2y_b(17) <= not( (sh2v4dcd08_cp1 and ex1_sh_lv1(9) ) or (sh2v4dcd12_cp1 and ex1_sh_lv1(5) ) ); + lv2y_18: ex1_sh_lv2y_b(18) <= not( (sh2v4dcd08_cp1 and ex1_sh_lv1(10) ) or (sh2v4dcd12_cp1 and ex1_sh_lv1(6) ) ); + lv2y_19: ex1_sh_lv2y_b(19) <= not( (sh2v4dcd08_cp1 and ex1_sh_lv1(11) ) or (sh2v4dcd12_cp1 and ex1_sh_lv1(7) ) ); + lv2y_20: ex1_sh_lv2y_b(20) <= not( (sh2v4dcd08_cp1 and ex1_sh_lv1(12) ) or (sh2v4dcd12_cp1 and ex1_sh_lv1(8) ) ); + lv2y_21: ex1_sh_lv2y_b(21) <= not( (sh2v4dcd08_cp1 and ex1_sh_lv1(13) ) or (sh2v4dcd12_cp1 and ex1_sh_lv1(9) ) ); + lv2y_22: ex1_sh_lv2y_b(22) <= not( (sh2v4dcd08_cp2 and ex1_sh_lv1(14) ) or (sh2v4dcd12_cp2 and ex1_sh_lv1(10) ) ); + lv2y_23: ex1_sh_lv2y_b(23) <= not( (sh2v4dcd08_cp2 and ex1_sh_lv1(15) ) or (sh2v4dcd12_cp2 and ex1_sh_lv1(11) ) ); + lv2y_24: ex1_sh_lv2y_b(24) <= not( (sh2v4dcd08_cp2 and ex1_sh_lv1(16) ) or (sh2v4dcd12_cp2 and ex1_sh_lv1(12) ) ); + lv2y_25: ex1_sh_lv2y_b(25) <= not( (sh2v4dcd08_cp2 and ex1_sh_lv1(17) ) or (sh2v4dcd12_cp2 and ex1_sh_lv1(13) ) ); + lv2y_26: ex1_sh_lv2y_b(26) <= not( (sh2v4dcd08_cp2 and ex1_sh_lv1(18) ) or (sh2v4dcd12_cp2 and ex1_sh_lv1(14) ) ); + lv2y_27: ex1_sh_lv2y_b(27) <= not( (sh2v4dcd08_cp2 and ex1_sh_lv1(19) ) or (sh2v4dcd12_cp2 and ex1_sh_lv1(15) ) ); + lv2y_28: ex1_sh_lv2y_b(28) <= not( (sh2v4dcd08_cp2 and ex1_sh_lv1(20) ) or (sh2v4dcd12_cp2 and ex1_sh_lv1(16) ) ); + lv2y_29: ex1_sh_lv2y_b(29) <= not( (sh2v4dcd08_cp2 and ex1_sh_lv1(21) ) or (sh2v4dcd12_cp2 and ex1_sh_lv1(17) ) ); + lv2y_30: ex1_sh_lv2y_b(30) <= not( (sh2v4dcd08_cp2 and ex1_sh_lv1(22) ) or (sh2v4dcd12_cp2 and ex1_sh_lv1(18) ) ); + lv2y_31: ex1_sh_lv2y_b(31) <= not( (sh2v4dcd08_cp2 and ex1_sh_lv1(23) ) or (sh2v4dcd12_cp2 and ex1_sh_lv1(19) ) ); + lv2y_32: ex1_sh_lv2y_b(32) <= not( (sh2v4dcd08_cp2 and ex1_sh_lv1(24) ) or (sh2v4dcd12_cp2 and ex1_sh_lv1(20) ) ); + lv2y_33: ex1_sh_lv2y_b(33) <= not( (sh2v4dcd08_cp2 and ex1_sh_lv1(25) ) or (sh2v4dcd12_cp2 and ex1_sh_lv1(21) ) ); + lv2y_34: ex1_sh_lv2y_b(34) <= not( (sh2v4dcd08_cp2 and ex1_sh_lv1(26) ) or (sh2v4dcd12_cp2 and ex1_sh_lv1(22) ) ); + lv2y_35: ex1_sh_lv2y_b(35) <= not( (sh2v4dcd08_cp2 and ex1_sh_lv1(27) ) or (sh2v4dcd12_cp2 and ex1_sh_lv1(23) ) ); + lv2y_36: ex1_sh_lv2y_b(36) <= not( (sh2v4dcd08_cp2 and ex1_sh_lv1(28) ) or (sh2v4dcd12_cp2 and ex1_sh_lv1(24) ) ); + lv2y_37: ex1_sh_lv2y_b(37) <= not( (sh2v4dcd08_cp3 and ex1_sh_lv1(29) ) or (sh2v4dcd12_cp3 and ex1_sh_lv1(25) ) ); + lv2y_38: ex1_sh_lv2y_b(38) <= not( (sh2v4dcd08_cp3 and ex1_sh_lv1(30) ) or (sh2v4dcd12_cp3 and ex1_sh_lv1(26) ) ); + lv2y_39: ex1_sh_lv2y_b(39) <= not( (sh2v4dcd08_cp3 and ex1_sh_lv1(31) ) or (sh2v4dcd12_cp3 and ex1_sh_lv1(27) ) ); + lv2y_40: ex1_sh_lv2y_b(40) <= not( (sh2v4dcd08_cp3 and ex1_sh_lv1(32) ) or (sh2v4dcd12_cp3 and ex1_sh_lv1(28) ) ); + lv2y_41: ex1_sh_lv2y_b(41) <= not( (sh2v4dcd08_cp3 and ex1_sh_lv1(33) ) or (sh2v4dcd12_cp3 and ex1_sh_lv1(29) ) ); + lv2y_42: ex1_sh_lv2y_b(42) <= not( (sh2v4dcd08_cp3 and ex1_sh_lv1(34) ) or (sh2v4dcd12_cp3 and ex1_sh_lv1(30) ) ); + lv2y_43: ex1_sh_lv2y_b(43) <= not( (sh2v4dcd08_cp3 and ex1_sh_lv1(35) ) or (sh2v4dcd12_cp3 and ex1_sh_lv1(31) ) ); + lv2y_44: ex1_sh_lv2y_b(44) <= not( (sh2v4dcd08_cp3 and ex1_sh_lv1(36) ) or (sh2v4dcd12_cp3 and ex1_sh_lv1(32) ) ); + lv2y_45: ex1_sh_lv2y_b(45) <= not( (sh2v4dcd08_cp3 and ex1_sh_lv1(37) ) or (sh2v4dcd12_cp3 and ex1_sh_lv1(33) ) ); + lv2y_46: ex1_sh_lv2y_b(46) <= not( (sh2v4dcd08_cp3 and ex1_sh_lv1(38) ) or (sh2v4dcd12_cp3 and ex1_sh_lv1(34) ) ); + lv2y_47: ex1_sh_lv2y_b(47) <= not( (sh2v4dcd08_cp3 and ex1_sh_lv1(39) ) or (sh2v4dcd12_cp3 and ex1_sh_lv1(35) ) ); + lv2y_48: ex1_sh_lv2y_b(48) <= not( (sh2v4dcd08_cp3 and ex1_sh_lv1(40) ) or (sh2v4dcd12_cp3 and ex1_sh_lv1(36) ) ); + lv2y_49: ex1_sh_lv2y_b(49) <= not( (sh2v4dcd08_cp3 and ex1_sh_lv1(41) ) or (sh2v4dcd12_cp3 and ex1_sh_lv1(37) ) ); + lv2y_50: ex1_sh_lv2y_b(50) <= not( (sh2v4dcd08_cp3 and ex1_sh_lv1(42) ) or (sh2v4dcd12_cp3 and ex1_sh_lv1(38) ) ); + lv2y_51: ex1_sh_lv2y_b(51) <= not( (sh2v4dcd08_cp3 and ex1_sh_lv1(43) ) or (sh2v4dcd12_cp3 and ex1_sh_lv1(39) ) ); + lv2y_52: ex1_sh_lv2y_b(52) <= not( (sh2v4dcd08_cp4 and ex1_sh_lv1(44) ) or (sh2v4dcd12_cp4 and ex1_sh_lv1(40) ) ); + lv2y_53: ex1_sh_lv2y_b(53) <= not( (sh2v4dcd08_cp4 and ex1_sh_lv1(45) ) or (sh2v4dcd12_cp4 and ex1_sh_lv1(41) ) ); + lv2y_54: ex1_sh_lv2y_b(54) <= not( (sh2v4dcd08_cp4 and ex1_sh_lv1(46) ) or (sh2v4dcd12_cp4 and ex1_sh_lv1(42) ) ); + lv2y_55: ex1_sh_lv2y_b(55) <= not( (sh2v4dcd08_cp4 and ex1_sh_lv1(47) ) or (sh2v4dcd12_cp4 and ex1_sh_lv1(43) ) ); + lv2y_56: ex1_sh_lv2y_b(56) <= not( (sh2v4dcd08_cp4 and ex1_sh_lv1(48) ) or (sh2v4dcd12_cp4 and ex1_sh_lv1(44) ) ); + lv2y_57: ex1_sh_lv2y_b(57) <= not( (sh2v4dcd08_cp4 and ex1_sh_lv1(49) ) or (sh2v4dcd12_cp4 and ex1_sh_lv1(45) ) ); + lv2y_58: ex1_sh_lv2y_b(58) <= not( (sh2v4dcd08_cp4 and ex1_sh_lv1(50) ) or (sh2v4dcd12_cp4 and ex1_sh_lv1(46) ) ); + lv2y_59: ex1_sh_lv2y_b(59) <= not( (sh2v4dcd08_cp4 and ex1_sh_lv1(51) ) or (sh2v4dcd12_cp4 and ex1_sh_lv1(47) ) ); + lv2y_60: ex1_sh_lv2y_b(60) <= not( (sh2v4dcd08_cp4 and ex1_sh_lv1(52) ) or (sh2v4dcd12_cp4 and ex1_sh_lv1(48) ) ); + lv2y_61: ex1_sh_lv2y_b(61) <= not( (sh2v4dcd08_cp4 and ex1_sh_lv1(53) ) or (sh2v4dcd12_cp4 and ex1_sh_lv1(49) ) ); + lv2y_62: ex1_sh_lv2y_b(62) <= not( (sh2v4dcd08_cp4 and ex1_sh_lv1(54) ) or (sh2v4dcd12_cp4 and ex1_sh_lv1(50) ) ); + lv2y_63: ex1_sh_lv2y_b(63) <= not( (sh2v4dcd08_cp4 and ex1_sh_lv1(55) ) or (sh2v4dcd12_cp4 and ex1_sh_lv1(51) ) ); + lv2y_64: ex1_sh_lv2y_b(64) <= not( sh2v4dcd12_cp4 and ex1_sh_lv1(52) ); + lv2y_65: ex1_sh_lv2y_b(65) <= not( sh2v4dcd12_cp4 and ex1_sh_lv1(53) ); + lv2y_66: ex1_sh_lv2y_b(66) <= not( sh2v4dcd12_cp4 and ex1_sh_lv1(54) ); + lv2y_67: ex1_sh_lv2y_b(67) <= not( sh2v4dcd12_cp4 and ex1_sh_lv1(55) ); + + + lv2z_00: ex1_sh_lv2z_b( 0) <= not( sh2v4dcdpp_cp1 and ex1_special_fcfid( 0) ); + lv2z_01: ex1_sh_lv2z_b( 1) <= not( sh2v4dcdpp_cp1 and ex1_special_fcfid( 1) ); + lv2z_02: ex1_sh_lv2z_b( 2) <= not( sh2v4dcdpp_cp1 and ex1_special_fcfid( 2) ); + lv2z_03: ex1_sh_lv2z_b( 3) <= not( sh2v4dcdpp_cp1 and ex1_special_fcfid( 3) ); + lv2z_04: ex1_sh_lv2z_b( 4) <= not( sh2v4dcdpp_cp1 and ex1_special_fcfid( 4) ); + lv2z_05: ex1_sh_lv2z_b( 5) <= not( sh2v4dcdpp_cp1 and ex1_special_fcfid( 5) ); + lv2z_06: ex1_sh_lv2z_b( 6) <= not( sh2v4dcdpp_cp1 and ex1_special_fcfid( 6) ); + lv2z_07: ex1_sh_lv2z_b( 7) <= not( sh2v4dcdpp_cp1 and ex1_special_fcfid( 7) ); + lv2z_08: ex1_sh_lv2z_b( 8) <= not( sh2v4dcdpp_cp1 and ex1_special_fcfid( 8) ); + lv2z_09: ex1_sh_lv2z_b( 9) <= not( sh2v4dcdpp_cp1 and ex1_special_fcfid( 9) ); + lv2z_10: ex1_sh_lv2z_b(10) <= not( sh2v4dcdpp_cp1 and ex1_special_fcfid(10) ); + lv2z_11: ex1_sh_lv2z_b(11) <= not( sh2v4dcdpp_cp1 and ex1_special_fcfid(11) ); + lv2z_12: ex1_sh_lv2z_b(12) <= not( sh2v4dcdpp_cp1 and ex1_special_fcfid(12) ); + lv2z_13: ex1_sh_lv2z_b(13) <= not( sh2v4dcdpp_cp1 and ex1_special_fcfid(13) ); + lv2z_14: ex1_sh_lv2z_b(14) <= not( sh2v4dcdpp_cp1 and ex1_special_fcfid(14) ); + lv2z_15: ex1_sh_lv2z_b(15) <= not( sh2v4dcdpp_cp1 and ex1_special_fcfid(15) ); + lv2z_16: ex1_sh_lv2z_b(16) <= not( sh2v4dcdpp_cp2 and ex1_special_fcfid(16) ); + lv2z_17: ex1_sh_lv2z_b(17) <= not( sh2v4dcdpp_cp2 and ex1_special_fcfid(17) ); + lv2z_18: ex1_sh_lv2z_b(18) <= not( sh2v4dcdpp_cp2 and ex1_special_fcfid(18) ); + lv2z_19: ex1_sh_lv2z_b(19) <= not( sh2v4dcdpp_cp2 and ex1_special_fcfid(19) ); + lv2z_20: ex1_sh_lv2z_b(20) <= not( sh2v4dcdpp_cp2 and ex1_special_fcfid(20) ); + lv2z_21: ex1_sh_lv2z_b(21) <= not( sh2v4dcdpp_cp2 and ex1_special_fcfid(21) ); + lv2z_22: ex1_sh_lv2z_b(22) <= not( sh2v4dcdpp_cp2 and ex1_special_fcfid(22) ); + lv2z_23: ex1_sh_lv2z_b(23) <= not( sh2v4dcdpp_cp2 and ex1_special_fcfid(23) ); + lv2z_24: ex1_sh_lv2z_b(24) <= not( sh2v4dcdpp_cp2 and ex1_special_fcfid(24) ); + lv2z_25: ex1_sh_lv2z_b(25) <= not( sh2v4dcdpp_cp2 and ex1_special_fcfid(25) ); + lv2z_26: ex1_sh_lv2z_b(26) <= not( sh2v4dcdpp_cp2 and ex1_special_fcfid(26) ); + lv2z_27: ex1_sh_lv2z_b(27) <= not( sh2v4dcdpp_cp2 and ex1_special_fcfid(27) ); + lv2z_28: ex1_sh_lv2z_b(28) <= not( sh2v4dcdpp_cp2 and ex1_special_fcfid(28) ); + lv2z_29: ex1_sh_lv2z_b(29) <= not( sh2v4dcdpp_cp2 and ex1_special_fcfid(29) ); + lv2z_30: ex1_sh_lv2z_b(30) <= not( sh2v4dcdpp_cp2 and ex1_special_fcfid(30) ); + lv2z_31: ex1_sh_lv2z_b(31) <= not( sh2v4dcdpp_cp2 and ex1_special_fcfid(31) ); + lv2z_32: ex1_sh_lv2z_b(32) <= not( sh2v4dcdpp_cp3 and ex1_special_fcfid(32) ); + lv2z_33: ex1_sh_lv2z_b(33) <= not( sh2v4dcdpp_cp3 and ex1_special_fcfid(33) ); + lv2z_34: ex1_sh_lv2z_b(34) <= not( sh2v4dcdpp_cp3 and ex1_special_fcfid(34) ); + lv2z_35: ex1_sh_lv2z_b(35) <= not( sh2v4dcdpp_cp3 and ex1_special_fcfid(35) ); + lv2z_36: ex1_sh_lv2z_b(36) <= not( sh2v4dcdpp_cp3 and ex1_special_fcfid(36) ); + lv2z_37: ex1_sh_lv2z_b(37) <= not( sh2v4dcdpp_cp3 and ex1_special_fcfid(37) ); + lv2z_38: ex1_sh_lv2z_b(38) <= not( sh2v4dcdpp_cp3 and ex1_special_fcfid(38) ); + lv2z_39: ex1_sh_lv2z_b(39) <= not( sh2v4dcdpp_cp3 and ex1_special_fcfid(39) ); + lv2z_40: ex1_sh_lv2z_b(40) <= not( sh2v4dcdpp_cp3 and ex1_special_fcfid(40) ); + lv2z_41: ex1_sh_lv2z_b(41) <= not( sh2v4dcdpp_cp3 and ex1_special_fcfid(41) ); + lv2z_42: ex1_sh_lv2z_b(42) <= not( sh2v4dcdpp_cp3 and ex1_special_fcfid(42) ); + lv2z_43: ex1_sh_lv2z_b(43) <= not( sh2v4dcdpp_cp3 and ex1_special_fcfid(43) ); + lv2z_44: ex1_sh_lv2z_b(44) <= not( sh2v4dcdpp_cp3 and ex1_special_fcfid(44) ); + lv2z_45: ex1_sh_lv2z_b(45) <= not( sh2v4dcdpp_cp3 and ex1_special_fcfid(45) ); + lv2z_46: ex1_sh_lv2z_b(46) <= not( sh2v4dcdpp_cp3 and ex1_special_fcfid(46) ); + lv2z_47: ex1_sh_lv2z_b(47) <= not( sh2v4dcdpp_cp3 and ex1_special_fcfid(47) ); + lv2z_48: ex1_sh_lv2z_b(48) <= not( sh2v4dcdpp_cp4 and ex1_special_fcfid(48) ); + lv2z_49: ex1_sh_lv2z_b(49) <= not( sh2v4dcdpp_cp4 and ex1_special_fcfid(49) ); + lv2z_50: ex1_sh_lv2z_b(50) <= not( sh2v4dcdpp_cp4 and ex1_special_fcfid(50) ); + lv2z_51: ex1_sh_lv2z_b(51) <= not( sh2v4dcdpp_cp4 and ex1_special_fcfid(51) ); + lv2z_52: ex1_sh_lv2z_b(52) <= not( sh2v4dcdpp_cp4 and ex1_special_fcfid(52) ); + lv2z_53: ex1_sh_lv2z_b(53) <= not( sh2v4dcdpp_cp4 and ex1_special_fcfid(53) ); + lv2z_54: ex1_sh_lv2z_b(54) <= not( sh2v4dcdpp_cp4 and ex1_special_fcfid(54) ); + lv2z_55: ex1_sh_lv2z_b(55) <= not( sh2v4dcdpp_cp4 and ex1_special_fcfid(55) ); + lv2z_56: ex1_sh_lv2z_b(56) <= not( sh2v4dcdpp_cp4 and ex1_special_fcfid(56) ); + lv2z_57: ex1_sh_lv2z_b(57) <= not( sh2v4dcdpp_cp4 and ex1_special_fcfid(57) ); + lv2z_58: ex1_sh_lv2z_b(58) <= not( sh2v4dcdpp_cp4 and ex1_special_fcfid(58) ); + lv2z_59: ex1_sh_lv2z_b(59) <= not( sh2v4dcdpp_cp4 and ex1_special_fcfid(59) ); + lv2z_60: ex1_sh_lv2z_b(60) <= not( sh2v4dcdpp_cp4 and ex1_special_fcfid(60) ); + lv2z_61: ex1_sh_lv2z_b(61) <= not( sh2v4dcdpp_cp4 and ex1_special_fcfid(61) ); + lv2z_62: ex1_sh_lv2z_b(62) <= not( sh2v4dcdpp_cp4 and ex1_special_fcfid(62) ); + lv2z_63: ex1_sh_lv2z_b(63) <= not( sh2v4dcdpp_cp4 and ex1_special_fcfid(63) ); + + + + lv2_00: ex1_sh_lvl2(00) <= not( ex1_sh_lv2x_b(00) and ex1_sh_lv2z_b(00) ) ; + lv2_01: ex1_sh_lvl2(01) <= not( ex1_sh_lv2x_b(01) and ex1_sh_lv2z_b(01) ) ; + lv2_02: ex1_sh_lvl2(02) <= not( ex1_sh_lv2x_b(02) and ex1_sh_lv2z_b(02) ) ; + lv2_03: ex1_sh_lvl2(03) <= not( ex1_sh_lv2x_b(03) and ex1_sh_lv2z_b(03) ) ; + lv2_04: ex1_sh_lvl2(04) <= not( ex1_sh_lv2x_b(04) and ex1_sh_lv2z_b(04) ) ; + lv2_05: ex1_sh_lvl2(05) <= not( ex1_sh_lv2x_b(05) and ex1_sh_lv2z_b(05) ) ; + lv2_06: ex1_sh_lvl2(06) <= not( ex1_sh_lv2x_b(06) and ex1_sh_lv2z_b(06) ) ; + lv2_07: ex1_sh_lvl2(07) <= not( ex1_sh_lv2x_b(07) and ex1_sh_lv2z_b(07) ) ; + lv2_08: ex1_sh_lvl2(08) <= not( ex1_sh_lv2x_b(08) and ex1_sh_lv2y_b(08) and ex1_sh_lv2z_b(08) ) ; + lv2_09: ex1_sh_lvl2(09) <= not( ex1_sh_lv2x_b(09) and ex1_sh_lv2y_b(09) and ex1_sh_lv2z_b(09) ) ; + lv2_10: ex1_sh_lvl2(10) <= not( ex1_sh_lv2x_b(10) and ex1_sh_lv2y_b(10) and ex1_sh_lv2z_b(10) ) ; + lv2_11: ex1_sh_lvl2(11) <= not( ex1_sh_lv2x_b(11) and ex1_sh_lv2y_b(11) and ex1_sh_lv2z_b(11) ) ; + lv2_12: ex1_sh_lvl2(12) <= not( ex1_sh_lv2x_b(12) and ex1_sh_lv2y_b(12) and ex1_sh_lv2z_b(12) ) ; + lv2_13: ex1_sh_lvl2(13) <= not( ex1_sh_lv2x_b(13) and ex1_sh_lv2y_b(13) and ex1_sh_lv2z_b(13) ) ; + lv2_14: ex1_sh_lvl2(14) <= not( ex1_sh_lv2x_b(14) and ex1_sh_lv2y_b(14) and ex1_sh_lv2z_b(14) ) ; + lv2_15: ex1_sh_lvl2(15) <= not( ex1_sh_lv2x_b(15) and ex1_sh_lv2y_b(15) and ex1_sh_lv2z_b(15) ) ; + lv2_16: ex1_sh_lvl2(16) <= not( ex1_sh_lv2x_b(16) and ex1_sh_lv2y_b(16) and ex1_sh_lv2z_b(16) ) ; + lv2_17: ex1_sh_lvl2(17) <= not( ex1_sh_lv2x_b(17) and ex1_sh_lv2y_b(17) and ex1_sh_lv2z_b(17) ) ; + lv2_18: ex1_sh_lvl2(18) <= not( ex1_sh_lv2x_b(18) and ex1_sh_lv2y_b(18) and ex1_sh_lv2z_b(18) ) ; + lv2_19: ex1_sh_lvl2(19) <= not( ex1_sh_lv2x_b(19) and ex1_sh_lv2y_b(19) and ex1_sh_lv2z_b(19) ) ; + lv2_20: ex1_sh_lvl2(20) <= not( ex1_sh_lv2x_b(20) and ex1_sh_lv2y_b(20) and ex1_sh_lv2z_b(20) ) ; + lv2_21: ex1_sh_lvl2(21) <= not( ex1_sh_lv2x_b(21) and ex1_sh_lv2y_b(21) and ex1_sh_lv2z_b(21) ) ; + lv2_22: ex1_sh_lvl2(22) <= not( ex1_sh_lv2x_b(22) and ex1_sh_lv2y_b(22) and ex1_sh_lv2z_b(22) ) ; + lv2_23: ex1_sh_lvl2(23) <= not( ex1_sh_lv2x_b(23) and ex1_sh_lv2y_b(23) and ex1_sh_lv2z_b(23) ) ; + lv2_24: ex1_sh_lvl2(24) <= not( ex1_sh_lv2x_b(24) and ex1_sh_lv2y_b(24) and ex1_sh_lv2z_b(24) ) ; + lv2_25: ex1_sh_lvl2(25) <= not( ex1_sh_lv2x_b(25) and ex1_sh_lv2y_b(25) and ex1_sh_lv2z_b(25) ) ; + lv2_26: ex1_sh_lvl2(26) <= not( ex1_sh_lv2x_b(26) and ex1_sh_lv2y_b(26) and ex1_sh_lv2z_b(26) ) ; + lv2_27: ex1_sh_lvl2(27) <= not( ex1_sh_lv2x_b(27) and ex1_sh_lv2y_b(27) and ex1_sh_lv2z_b(27) ) ; + lv2_28: ex1_sh_lvl2(28) <= not( ex1_sh_lv2x_b(28) and ex1_sh_lv2y_b(28) and ex1_sh_lv2z_b(28) ) ; + lv2_29: ex1_sh_lvl2(29) <= not( ex1_sh_lv2x_b(29) and ex1_sh_lv2y_b(29) and ex1_sh_lv2z_b(29) ) ; + lv2_30: ex1_sh_lvl2(30) <= not( ex1_sh_lv2x_b(30) and ex1_sh_lv2y_b(30) and ex1_sh_lv2z_b(30) ) ; + lv2_31: ex1_sh_lvl2(31) <= not( ex1_sh_lv2x_b(31) and ex1_sh_lv2y_b(31) and ex1_sh_lv2z_b(31) ) ; + lv2_32: ex1_sh_lvl2(32) <= not( ex1_sh_lv2x_b(32) and ex1_sh_lv2y_b(32) and ex1_sh_lv2z_b(32) ) ; + lv2_33: ex1_sh_lvl2(33) <= not( ex1_sh_lv2x_b(33) and ex1_sh_lv2y_b(33) and ex1_sh_lv2z_b(33) ) ; + lv2_34: ex1_sh_lvl2(34) <= not( ex1_sh_lv2x_b(34) and ex1_sh_lv2y_b(34) and ex1_sh_lv2z_b(34) ) ; + lv2_35: ex1_sh_lvl2(35) <= not( ex1_sh_lv2x_b(35) and ex1_sh_lv2y_b(35) and ex1_sh_lv2z_b(35) ) ; + lv2_36: ex1_sh_lvl2(36) <= not( ex1_sh_lv2x_b(36) and ex1_sh_lv2y_b(36) and ex1_sh_lv2z_b(36) ) ; + lv2_37: ex1_sh_lvl2(37) <= not( ex1_sh_lv2x_b(37) and ex1_sh_lv2y_b(37) and ex1_sh_lv2z_b(37) ) ; + lv2_38: ex1_sh_lvl2(38) <= not( ex1_sh_lv2x_b(38) and ex1_sh_lv2y_b(38) and ex1_sh_lv2z_b(38) ) ; + lv2_39: ex1_sh_lvl2(39) <= not( ex1_sh_lv2x_b(39) and ex1_sh_lv2y_b(39) and ex1_sh_lv2z_b(39) ) ; + lv2_40: ex1_sh_lvl2(40) <= not( ex1_sh_lv2x_b(40) and ex1_sh_lv2y_b(40) and ex1_sh_lv2z_b(40) ) ; + lv2_41: ex1_sh_lvl2(41) <= not( ex1_sh_lv2x_b(41) and ex1_sh_lv2y_b(41) and ex1_sh_lv2z_b(41) ) ; + lv2_42: ex1_sh_lvl2(42) <= not( ex1_sh_lv2x_b(42) and ex1_sh_lv2y_b(42) and ex1_sh_lv2z_b(42) ) ; + lv2_43: ex1_sh_lvl2(43) <= not( ex1_sh_lv2x_b(43) and ex1_sh_lv2y_b(43) and ex1_sh_lv2z_b(43) ) ; + lv2_44: ex1_sh_lvl2(44) <= not( ex1_sh_lv2x_b(44) and ex1_sh_lv2y_b(44) and ex1_sh_lv2z_b(44) ) ; + lv2_45: ex1_sh_lvl2(45) <= not( ex1_sh_lv2x_b(45) and ex1_sh_lv2y_b(45) and ex1_sh_lv2z_b(45) ) ; + lv2_46: ex1_sh_lvl2(46) <= not( ex1_sh_lv2x_b(46) and ex1_sh_lv2y_b(46) and ex1_sh_lv2z_b(46) ) ; + lv2_47: ex1_sh_lvl2(47) <= not( ex1_sh_lv2x_b(47) and ex1_sh_lv2y_b(47) and ex1_sh_lv2z_b(47) ) ; + lv2_48: ex1_sh_lvl2(48) <= not( ex1_sh_lv2x_b(48) and ex1_sh_lv2y_b(48) and ex1_sh_lv2z_b(48) ) ; + lv2_49: ex1_sh_lvl2(49) <= not( ex1_sh_lv2x_b(49) and ex1_sh_lv2y_b(49) and ex1_sh_lv2z_b(49) ) ; + lv2_50: ex1_sh_lvl2(50) <= not( ex1_sh_lv2x_b(50) and ex1_sh_lv2y_b(50) and ex1_sh_lv2z_b(50) ) ; + lv2_51: ex1_sh_lvl2(51) <= not( ex1_sh_lv2x_b(51) and ex1_sh_lv2y_b(51) and ex1_sh_lv2z_b(51) ) ; + lv2_52: ex1_sh_lvl2(52) <= not( ex1_sh_lv2x_b(52) and ex1_sh_lv2y_b(52) and ex1_sh_lv2z_b(52) ) ; + lv2_53: ex1_sh_lvl2(53) <= not( ex1_sh_lv2x_b(53) and ex1_sh_lv2y_b(53) and ex1_sh_lv2z_b(53) ) ; + lv2_54: ex1_sh_lvl2(54) <= not( ex1_sh_lv2x_b(54) and ex1_sh_lv2y_b(54) and ex1_sh_lv2z_b(54) ) ; + lv2_55: ex1_sh_lvl2(55) <= not( ex1_sh_lv2x_b(55) and ex1_sh_lv2y_b(55) and ex1_sh_lv2z_b(55) ) ; + lv2_56: ex1_sh_lvl2(56) <= not( ex1_sh_lv2x_b(56) and ex1_sh_lv2y_b(56) and ex1_sh_lv2z_b(56) ) ; + lv2_57: ex1_sh_lvl2(57) <= not( ex1_sh_lv2x_b(57) and ex1_sh_lv2y_b(57) and ex1_sh_lv2z_b(57) ) ; + lv2_58: ex1_sh_lvl2(58) <= not( ex1_sh_lv2x_b(58) and ex1_sh_lv2y_b(58) and ex1_sh_lv2z_b(58) ) ; + lv2_59: ex1_sh_lvl2(59) <= not( ex1_sh_lv2x_b(59) and ex1_sh_lv2y_b(59) and ex1_sh_lv2z_b(59) ) ; + lv2_60: ex1_sh_lvl2(60) <= not( ex1_sh_lv2y_b(60) and ex1_sh_lv2z_b(60) ) ; + lv2_61: ex1_sh_lvl2(61) <= not( ex1_sh_lv2y_b(61) and ex1_sh_lv2z_b(61) ) ; + lv2_62: ex1_sh_lvl2(62) <= not( ex1_sh_lv2y_b(62) and ex1_sh_lv2z_b(62) ) ; + lv2_63: ex1_sh_lvl2(63) <= not( ex1_sh_lv2y_b(63) and ex1_sh_lv2z_b(63) ) ; + lv2_64: ex1_sh_lvl2(64) <= not( ex1_sh_lv2y_b(64) ) ; + lv2_65: ex1_sh_lvl2(65) <= not( ex1_sh_lv2y_b(65) ) ; + lv2_66: ex1_sh_lvl2(66) <= not( ex1_sh_lv2y_b(66) ) ; + lv2_67: ex1_sh_lvl2(67) <= not( ex1_sh_lv2y_b(67) ) ; + + + +end; -- fuq_alg_sh4 ARCHITECTURE diff --git a/rel/src/vhdl/work/fuq_byp.vhdl b/rel/src/vhdl/work/fuq_byp.vhdl new file mode 100644 index 0000000..ff5b7f0 --- /dev/null +++ b/rel/src/vhdl/work/fuq_byp.vhdl @@ -0,0 +1,1833 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Synopsys translate, Issues resolved: NONE + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + +ENTITY fuq_byp IS +generic( expand_type : integer := 2 ); -- 0 - ibm tech, 1 - other ); +PORT( + vdd :inout power_logic; + gnd :inout power_logic; + clkoff_b :in std_ulogic; -- tiup + act_dis :in std_ulogic; -- ??tidn?? + flush :in std_ulogic; -- ??tidn?? + delay_lclkr :in std_ulogic; -- tidn, + mpw1_b :in std_ulogic; -- tidn, + mpw2_b :in std_ulogic; -- tidn, + sg_1 :in std_ulogic; + thold_1 :in std_ulogic; + fpu_enable :in std_ulogic; --dc_act + nclk :in clk_logic; + + f_byp_si :in std_ulogic; --perv + f_byp_so :out std_ulogic; --perv + rf1_act :in std_ulogic; --act + + f_dcd_rf1_bypsel_a_res0 :in std_ulogic; + f_dcd_rf1_bypsel_a_res1 :in std_ulogic; + f_dcd_rf1_bypsel_a_load0 :in std_ulogic; + f_dcd_rf1_bypsel_a_load1 :in std_ulogic; + f_dcd_rf1_bypsel_b_res0 :in std_ulogic; + f_dcd_rf1_bypsel_b_res1 :in std_ulogic; + f_dcd_rf1_bypsel_b_load0 :in std_ulogic; + f_dcd_rf1_bypsel_b_load1 :in std_ulogic; + f_dcd_rf1_bypsel_c_res0 :in std_ulogic; + f_dcd_rf1_bypsel_c_res1 :in std_ulogic; + f_dcd_rf1_bypsel_c_load0 :in std_ulogic; + f_dcd_rf1_bypsel_c_load1 :in std_ulogic; + + + f_rnd_ex6_res_sign :in std_ulogic; + f_rnd_ex6_res_expo :in std_ulogic_vector(1 to 13); + f_rnd_ex6_res_frac :in std_ulogic_vector(0 to 52); + f_dcd_rf1_uc_fc_hulp :in std_ulogic ; + + f_dcd_rf1_div_beg :in std_ulogic; + f_dcd_rf1_uc_fa_pos :in std_ulogic; + f_dcd_rf1_uc_fc_pos :in std_ulogic; + f_dcd_rf1_uc_fb_pos :in std_ulogic; + f_dcd_rf1_uc_fc_0_5 :in std_ulogic; + f_dcd_rf1_uc_fc_1_0 :in std_ulogic; + f_dcd_rf1_uc_fc_1_minus :in std_ulogic; + f_dcd_rf1_uc_fb_1_0 :in std_ulogic; + f_dcd_rf1_uc_fb_0_75 :in std_ulogic; + f_dcd_rf1_uc_fb_0_5 :in std_ulogic; + + + f_fpr_ex7_frt_sign :in std_ulogic ; + f_fpr_ex7_frt_expo :in std_ulogic_vector (1 to 13); + f_fpr_ex7_frt_frac :in std_ulogic_vector (0 to 52); + f_fpr_ex7_load_sign :in std_ulogic ; + f_fpr_ex7_load_expo :in std_ulogic_vector (3 to 13); + f_fpr_ex7_load_frac :in std_ulogic_vector (0 to 52); + + f_fpr_ex6_load_sign :in std_ulogic; + f_fpr_ex6_load_expo :in std_ulogic_vector(3 to 13); + f_fpr_ex6_load_frac :in std_ulogic_vector(0 to 52); + + f_fpr_rf1_a_sign :in std_ulogic; + f_fpr_rf1_a_expo :in std_ulogic_vector(1 to 13); + f_fpr_rf1_a_frac :in std_ulogic_vector(0 to 52); --[0] is implicit bit + + f_fpr_rf1_c_sign :in std_ulogic; + f_fpr_rf1_c_expo :in std_ulogic_vector(1 to 13); + f_fpr_rf1_c_frac :in std_ulogic_vector(0 to 52); --[0] is implicit bit + + f_fpr_rf1_b_sign :in std_ulogic; + f_fpr_rf1_b_expo :in std_ulogic_vector(1 to 13); + f_fpr_rf1_b_frac :in std_ulogic_vector(0 to 52); --[0] is implicit bit + + f_dcd_rf1_aop_valid :in std_ulogic; + f_dcd_rf1_cop_valid :in std_ulogic; + f_dcd_rf1_bop_valid :in std_ulogic; + f_dcd_rf1_sp :in std_ulogic; + f_dcd_rf1_to_integer_b :in std_ulogic; + f_dcd_rf1_emin_dp :in std_ulogic; + f_dcd_rf1_emin_sp :in std_ulogic; + + f_byp_fmt_ex1_a_expo :out std_ulogic_vector(1 to 13); + f_byp_fmt_ex1_c_expo :out std_ulogic_vector(1 to 13); + f_byp_fmt_ex1_b_expo :out std_ulogic_vector(1 to 13); + f_byp_eie_ex1_a_expo :out std_ulogic_vector(1 to 13); + f_byp_eie_ex1_c_expo :out std_ulogic_vector(1 to 13); + f_byp_eie_ex1_b_expo :out std_ulogic_vector(1 to 13); + f_byp_alg_ex1_a_expo :out std_ulogic_vector(1 to 13); + f_byp_alg_ex1_c_expo :out std_ulogic_vector(1 to 13); + f_byp_alg_ex1_b_expo :out std_ulogic_vector(1 to 13); + + f_byp_fmt_ex1_a_sign :out std_ulogic; + f_byp_fmt_ex1_c_sign :out std_ulogic; + f_byp_fmt_ex1_b_sign :out std_ulogic; + f_byp_pic_ex1_a_sign :out std_ulogic; + f_byp_pic_ex1_c_sign :out std_ulogic; + f_byp_pic_ex1_b_sign :out std_ulogic; + f_byp_alg_ex1_b_sign :out std_ulogic; + + f_byp_fmt_ex1_a_frac :out std_ulogic_vector(0 to 52); + f_byp_fmt_ex1_c_frac :out std_ulogic_vector(0 to 52); + f_byp_fmt_ex1_b_frac :out std_ulogic_vector(0 to 52); + f_byp_alg_ex1_b_frac :out std_ulogic_vector(0 to 52); + f_byp_mul_ex1_a_frac :out std_ulogic_vector(0 to 52) ;--mul + f_byp_mul_ex1_a_frac_17 :out std_ulogic ;--mul + f_byp_mul_ex1_a_frac_35 :out std_ulogic ;--mul + f_byp_mul_ex1_c_frac :out std_ulogic_vector(0 to 53) --mul + + +); + +-- synopsys translate_off +-- synopsys translate_on + + +end fuq_byp; -- ENTITY + +architecture fuq_byp of fuq_byp is + + constant tiup :std_ulogic := '1'; + constant tidn :std_ulogic := '0'; + constant k_emin_dp :std_ulogic_vector(1 to 13) := "0000000000001"; + constant k_emin_sp :std_ulogic_vector(1 to 13) := "0001110000001"; + constant k_toint :std_ulogic_vector(1 to 13) := "0010001101001"; + constant expo_zero :std_ulogic_vector(1 to 13) := "0000000000001"; + constant expo_bias :std_ulogic_vector(1 to 13) := "0001111111111"; + constant expo_bias_m1 :std_ulogic_vector(1 to 13) := "0001111111110"; + ---------------------------------- + -- 57-bias is done after Ea+Ec-Eb + ---------------------------------- + -- bias + 162 - 56 + -- bias + 106 1023+106 = 1129 + -- + -- 0_0011_1111_1111 + -- 110 1010 106 = + ------------------------------- + -- 0 0100 0110 1001 + ------------------------------- + + signal rf1_c_k_expo :std_ulogic_vector(1 to 13); + signal rf1_b_k_expo :std_ulogic_vector(1 to 13); + signal rf1_a_k_expo :std_ulogic_vector(1 to 13); + signal rf1_a_k_frac :std_ulogic_vector(0 to 52); + signal rf1_c_k_frac :std_ulogic_vector(0 to 52); + signal rf1_b_k_frac :std_ulogic_vector(0 to 52); + + signal rf1_a_expo_prebyp :std_ulogic_vector(1 to 13); + signal rf1_c_expo_prebyp :std_ulogic_vector(1 to 13); + signal rf1_b_expo_prebyp :std_ulogic_vector(1 to 13); + signal rf1_a_frac_prebyp :std_ulogic_vector(0 to 52); + signal rf1_c_frac_prebyp :std_ulogic_vector(0 to 52); + signal rf1_b_frac_prebyp :std_ulogic_vector(0 to 52); + signal rf1_a_sign_prebyp :std_ulogic; + signal rf1_c_sign_prebyp :std_ulogic; + signal rf1_b_sign_prebyp :std_ulogic; + + + signal rf1_a_sign_pre1_b :std_ulogic; + signal rf1_a_sign_pre2_b :std_ulogic; + signal rf1_a_sign_pre :std_ulogic; + signal rf1_c_sign_pre1_b :std_ulogic; + signal rf1_c_sign_pre2_b :std_ulogic; + signal rf1_c_sign_pre :std_ulogic; + signal rf1_b_sign_pre1_b :std_ulogic; + signal rf1_b_sign_pre2_b :std_ulogic; + signal rf1_b_sign_pre :std_ulogic; + + signal aop_valid_sign , cop_valid_sign , bop_valid_sign :std_ulogic; + signal aop_valid_plus , cop_valid_plus , bop_valid_plus :std_ulogic; + + + signal spare_unused :std_ulogic_vector(0 to 3); + signal unused :std_ulogic; + signal thold_0, forcee, thold_0_b, sg_0 :std_ulogic ; + + + signal ex1_b_frac_si , ex1_b_frac_so :std_ulogic_vector(0 to 52); + signal ex1_frac_a_fmt_si , ex1_frac_a_fmt_so :std_ulogic_vector(0 to 52); + signal ex1_frac_c_fmt_si , ex1_frac_c_fmt_so :std_ulogic_vector(0 to 52); + signal ex1_frac_b_fmt_si , ex1_frac_b_fmt_so :std_ulogic_vector(0 to 52); + signal frac_mul_c_si , frac_mul_c_so :std_ulogic_vector(0 to 53); + signal frac_mul_a_si , frac_mul_a_so :std_ulogic_vector(0 to 54); + + signal ex1_expo_a_eie_si, ex1_expo_a_eie_so :std_ulogic_vector(0 to 13); + signal ex1_expo_b_eie_si, ex1_expo_b_eie_so :std_ulogic_vector(0 to 13); + signal ex1_expo_c_eie_si, ex1_expo_c_eie_so :std_ulogic_vector(0 to 13); + signal ex1_expo_a_fmt_si, ex1_expo_a_fmt_so :std_ulogic_vector(0 to 13); + signal ex1_expo_b_fmt_si, ex1_expo_b_fmt_so :std_ulogic_vector(0 to 13); + signal ex1_expo_c_fmt_si, ex1_expo_c_fmt_so :std_ulogic_vector(0 to 13); + signal ex1_expo_b_alg_si, ex1_expo_b_alg_so :std_ulogic_vector(0 to 13); + signal ex1_expo_a_alg_si, ex1_expo_a_alg_so :std_ulogic_vector(0 to 12); + signal ex1_expo_c_alg_si, ex1_expo_c_alg_so :std_ulogic_vector(0 to 12); + + signal act_si, act_so :std_ulogic_vector(0 to 3); + + + signal sel_a_no_byp_s :std_ulogic; + signal sel_c_no_byp_s :std_ulogic; + signal sel_b_no_byp_s :std_ulogic; + signal sel_a_res0_s :std_ulogic; + signal sel_a_res1_s :std_ulogic; + signal sel_a_load0_s :std_ulogic; + signal sel_a_load1_s :std_ulogic; + signal sel_c_res0_s :std_ulogic; + signal sel_c_res1_s :std_ulogic; + signal sel_c_load0_s :std_ulogic; + signal sel_c_load1_s :std_ulogic; + signal sel_b_res0_s :std_ulogic; + signal sel_b_res1_s :std_ulogic; + signal sel_b_load0_s :std_ulogic; + signal sel_b_load1_s :std_ulogic; + + signal sel_a_no_byp :std_ulogic; + signal sel_c_no_byp :std_ulogic; + signal sel_b_no_byp :std_ulogic; + + + signal sel_a_imm :std_ulogic; + signal sel_a_res0 :std_ulogic; + signal sel_a_res1 :std_ulogic; + signal sel_a_load0 :std_ulogic; + signal sel_a_load1 :std_ulogic; + signal sel_c_imm :std_ulogic; + signal sel_c_res0 :std_ulogic; + signal sel_c_res1 :std_ulogic; + signal sel_c_load0 :std_ulogic; + signal sel_c_load1 :std_ulogic; + signal sel_b_imm :std_ulogic; + signal sel_b_res0 :std_ulogic; + signal sel_b_res1 :std_ulogic; + signal sel_b_load0 :std_ulogic; + signal sel_b_load1 :std_ulogic; + + + signal ex6_load_expo :std_ulogic_vector(1 to 13); + + signal rf1_b_frac_alg_b, ex1_b_frac_alg_b :std_ulogic_vector(0 to 52); + signal rf1_a_frac_fmt_b, ex1_a_frac_fmt_b :std_ulogic_vector(0 to 52); + signal rf1_c_frac_fmt_b, ex1_c_frac_fmt_b :std_ulogic_vector(0 to 52); + signal rf1_b_frac_fmt_b, ex1_b_frac_fmt_b :std_ulogic_vector(0 to 52); + signal ex1_a_frac_mul_17_b, ex1_a_frac_mul_35_b :std_ulogic; + signal ex1_a_frac_mul_b :std_ulogic_vector(0 to 52); + signal ex1_c_frac_mul_b :std_ulogic_vector(0 to 53); + signal rf1_a_frac_mul_17_b, rf1_a_frac_mul_35_b :std_ulogic; + signal rf1_a_frac_mul_b :std_ulogic_vector(0 to 52); + signal rf1_c_frac_mul_b :std_ulogic_vector(0 to 53); + signal rf1_b_sign_alg_b, ex1_b_sign_alg_b :std_ulogic ; + signal rf1_b_expo_alg_b, ex1_b_expo_alg_b :std_ulogic_vector(1 to 13); + signal rf1_c_expo_alg_b, ex1_c_expo_alg_b :std_ulogic_vector(1 to 13); + signal rf1_a_expo_alg_b, ex1_a_expo_alg_b :std_ulogic_vector(1 to 13); + signal rf1_a_sign_fmt_b, ex1_a_sign_fmt_b :std_ulogic ; + signal rf1_a_expo_fmt_b, ex1_a_expo_fmt_b :std_ulogic_vector(1 to 13) ; + signal rf1_c_sign_fmt_b, ex1_c_sign_fmt_b :std_ulogic ; + signal rf1_c_expo_fmt_b, ex1_c_expo_fmt_b :std_ulogic_vector(1 to 13) ; + signal rf1_b_sign_fmt_b, ex1_b_sign_fmt_b :std_ulogic ; + signal rf1_b_expo_fmt_b, ex1_b_expo_fmt_b :std_ulogic_vector(1 to 13) ; + signal rf1_a_sign_pic_b, ex1_a_sign_pic_b :std_ulogic ; + signal rf1_a_expo_eie_b, ex1_a_expo_eie_b :std_ulogic_vector(1 to 13) ; + signal rf1_c_sign_pic_b, ex1_c_sign_pic_b :std_ulogic ; + signal rf1_c_expo_eie_b, ex1_c_expo_eie_b :std_ulogic_vector(1 to 13) ; + signal rf1_b_sign_pic_b, ex1_b_sign_pic_b :std_ulogic ; + signal rf1_b_expo_eie_b, ex1_b_expo_eie_b :std_ulogic_vector(1 to 13) ; + signal cop_uc_imm , bop_uc_imm :std_ulogic; + + signal rf1_a_sign_fpr :std_ulogic; + signal rf1_c_sign_fpr :std_ulogic; + signal rf1_b_sign_fpr :std_ulogic; + signal rf1_a_expo_fpr :std_ulogic_vector(1 to 13); + signal rf1_c_expo_fpr :std_ulogic_vector(1 to 13); + signal rf1_b_expo_fpr :std_ulogic_vector(1 to 13); + signal rf1_a_frac_fpr :std_ulogic_vector(0 to 52); + signal rf1_c_frac_fpr :std_ulogic_vector(0 to 52); + signal rf1_b_frac_fpr :std_ulogic_vector(0 to 52); + + signal ex6_sign_res_ear :std_ulogic; + signal ex6_sign_res_dly :std_ulogic; + signal ex6_sign_lod_ear :std_ulogic; + signal ex6_sign_lod_dly :std_ulogic; + signal ex6_expo_res_ear :std_ulogic_vector(1 to 13); + signal ex6_expo_res_dly :std_ulogic_vector(1 to 13); + signal ex6_expo_lod_ear :std_ulogic_vector(1 to 13); + signal ex6_expo_lod_dly :std_ulogic_vector(1 to 13); + signal ex6_frac_res_ear :std_ulogic_vector(0 to 52); + signal ex6_frac_res_dly :std_ulogic_vector(0 to 52); + signal ex6_frac_lod_ear :std_ulogic_vector(0 to 52); + signal ex6_frac_lod_dly :std_ulogic_vector(0 to 52); + signal rf1_a_expo_pre1_b :std_ulogic_vector(1 to 13); + signal rf1_c_expo_pre1_b :std_ulogic_vector(1 to 13); + signal rf1_b_expo_pre1_b :std_ulogic_vector(1 to 13); + signal rf1_a_expo_pre2_b :std_ulogic_vector(1 to 13); + signal rf1_c_expo_pre2_b :std_ulogic_vector(1 to 13); + signal rf1_b_expo_pre2_b :std_ulogic_vector(1 to 13); + signal rf1_a_expo_pre3_b :std_ulogic_vector(1 to 13); + signal rf1_c_expo_pre3_b :std_ulogic_vector(1 to 13); + signal rf1_b_expo_pre3_b :std_ulogic_vector(1 to 13); + signal rf1_a_expo_pre :std_ulogic_vector(1 to 13); + signal rf1_c_expo_pre :std_ulogic_vector(1 to 13); + signal rf1_b_expo_pre :std_ulogic_vector(1 to 13); + signal rf1_a_frac_pre :std_ulogic_vector(0 to 52); + signal rf1_c_frac_pre :std_ulogic_vector(0 to 52); + signal rf1_b_frac_pre :std_ulogic_vector(0 to 52); + signal rf1_a_frac_pre1_b :std_ulogic_vector(0 to 52); + signal rf1_a_frac_pre2_b :std_ulogic_vector(0 to 52); + signal rf1_c_frac_pre1_b :std_ulogic_vector(0 to 52); + signal rf1_c_frac_pre2_b :std_ulogic_vector(0 to 52); + signal rf1_c_frac_pre3_b :std_ulogic_vector(0 to 52); + signal rf1_b_frac_pre1_b :std_ulogic_vector(0 to 52); + signal rf1_b_frac_pre2_b :std_ulogic_vector(0 to 52); + signal rf1_b_frac_pre3_b :std_ulogic_vector(0 to 1); + + signal byp_ex1_d1clk, byp_ex1_d2clk :std_ulogic; + signal byp_ex1_lclk : clk_logic; + signal rf1_c_frac_pre3_hulp_b ,rf1_hulp_sp , rf1_c_frac_pre_hulp , rf1_c_frac_prebyp_hulp :std_ulogic ; + + signal temp_rf1_c_frac_mul :std_ulogic_vector(0 to 53); + signal temp_rf1_a_frac_mul :std_ulogic_vector(0 to 52); + signal temp_rf1_a_frac_mul_17 :std_ulogic; + signal temp_rf1_a_frac_mul_35 :std_ulogic; + +-- synopsys translate_off + + + + + + + + +-- synopsys translate_on + + signal ex1_b_frac_alg :std_ulogic_vector(0 to 52); + signal ex1_b_frac_fmt :std_ulogic_vector(0 to 52); + signal ex1_a_frac_fmt :std_ulogic_vector(0 to 52); + signal ex1_c_frac_fmt :std_ulogic_vector(0 to 52); + signal ex1_b_sign_alg :std_ulogic ; + signal ex1_b_sign_fmt :std_ulogic ; + signal ex1_a_sign_fmt :std_ulogic ; + signal ex1_c_sign_fmt :std_ulogic ; + signal ex1_b_sign_pic :std_ulogic ; + signal ex1_a_sign_pic :std_ulogic ; + signal ex1_c_sign_pic :std_ulogic ; + signal ex1_b_expo_alg :std_ulogic_vector(1 to 13) ; + signal ex1_a_expo_alg :std_ulogic_vector(1 to 13) ; + signal ex1_c_expo_alg :std_ulogic_vector(1 to 13) ; + signal ex1_b_expo_fmt :std_ulogic_vector(1 to 13) ; + signal ex1_a_expo_fmt :std_ulogic_vector(1 to 13) ; + signal ex1_c_expo_fmt :std_ulogic_vector(1 to 13) ; + signal ex1_b_expo_eie :std_ulogic_vector(1 to 13) ; + signal ex1_a_expo_eie :std_ulogic_vector(1 to 13) ; + signal ex1_c_expo_eie :std_ulogic_vector(1 to 13) ; + + + + +begin + + unused <= rf1_a_expo_pre3_b(1) or rf1_a_expo_pre3_b(2) or + rf1_c_expo_pre3_b(1) or rf1_c_expo_pre3_b(2) or rf1_c_expo_pre3_b(3) or + rf1_b_expo_pre3_b(1) or rf1_b_expo_pre3_b(2) or rf1_b_expo_pre3_b(3) or + rf1_a_k_expo(1) or rf1_a_k_expo(2) or + or_reduce( rf1_c_k_expo(1 to 12) ) or + or_reduce( rf1_b_k_expo(1 to 3) ) or + or_reduce( rf1_a_k_frac(0 to 52) ) or + or_reduce( rf1_b_k_frac(2 to 52) ) ; + + +--#=############################################################## +--# pervasive +--#=############################################################## + + + thold_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => thold_1, + q(0) => thold_0 ); + + sg_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => sg_1 , + q(0) => sg_0 ); + + + lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map ( + clkoff_b => clkoff_b, + thold => thold_0, + sg => sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => thold_0_b ); + + + +--#=############################################################## +--# act +--#=############################################################## + + + act_lat: tri_rlmreg_p generic map (width=> 4, expand_type => expand_type, needs_sreset => 0 ) port map ( + delay_lclkr => delay_lclkr ,-- tidn ,--in + mpw1_b => mpw1_b ,-- tidn ,--in + mpw2_b => mpw2_b ,-- tidn ,--in + forcee => forcee,-- tidn ,--in + + vd => vdd, + gd => gnd, + nclk => nclk, + act => fpu_enable, + thold_b => thold_0_b, + sg => sg_0, + scout => act_so , + scin => act_si , + ------------------- + din(0) => spare_unused(0), + din(1) => spare_unused(1), + din(2) => spare_unused(2), + din(3) => spare_unused(3), + ------------------- + dout(0) => spare_unused(0), + dout(1) => spare_unused(1), + dout(2) => spare_unused(2) , + dout(3) => spare_unused(3) ); + + + byp_ex1_lcb : tri_lcbnd generic map (expand_type => expand_type) port map( + delay_lclkr => delay_lclkr ,-- tidn ,--in + mpw1_b => mpw1_b ,-- tidn ,--in + mpw2_b => mpw2_b ,-- tidn ,--in + forcee => forcee,-- tidn ,--in + nclk => nclk ,--in + vd => vdd ,--inout + gd => gnd ,--inout + act => rf1_act ,--in + sg => sg_0 ,--in + thold_b => thold_0_b ,--in + d1clk => byp_ex1_d1clk ,--out + d2clk => byp_ex1_d2clk ,--out + lclk => byp_ex1_lclk );--out + + + + +--================================================= +-- Constants for the immediate data +--================================================= + + rf1_a_k_expo(1 to 2) <= tidn & tidn ; + rf1_a_k_expo(3 to 13) <= + ( (3 to 13=> not f_dcd_rf1_to_integer_b) and k_toint (3 to 13) ) or + ( (3 to 13=> f_dcd_rf1_emin_dp ) and k_emin_dp(3 to 13) ) or + ( (3 to 13=> f_dcd_rf1_emin_sp ) and k_emin_sp(3 to 13) ) ; + + + rf1_c_k_expo(1 to 3) <= tidn & tidn & tidn ; + rf1_c_k_expo(4 to 12) <= (4 to 12 => tiup); + rf1_c_k_expo(13) <= + ( not cop_uc_imm and expo_bias(13) ) or -- non divide + ( f_dcd_rf1_uc_fc_1_0 and expo_bias(13) ) or -- div/sqrt + ( f_dcd_rf1_uc_fc_0_5 and expo_bias_m1(13) ) or -- div/sqrt + ( f_dcd_rf1_uc_fc_1_minus and expo_bias_m1(13) ) ; -- div/sqrt + + rf1_b_k_expo(1 to 3) <= tidn & tidn & tidn ; + rf1_b_k_expo(4 to 13) <= + ( (4 to 13=> not bop_uc_imm ) and expo_zero(4 to 13) ) or -- non divide + ( (4 to 13=> f_dcd_rf1_uc_fb_1_0 ) and expo_bias(4 to 13) ) or -- div/sqrt + ( (4 to 13=> f_dcd_rf1_uc_fb_0_5 ) and expo_bias_m1(4 to 13) ) or -- div/sqrt + ( (4 to 13=> f_dcd_rf1_uc_fb_0_75) and expo_bias_m1(4 to 13) ) ; -- div/sqrt + + + rf1_a_k_frac(0 to 52) <= tidn & (1 to 52 => tidn); + + -- c is invalid for divide , a is valid ... but want multiplier output to be zero for divide first step (prenorm) + rf1_c_k_frac(0) <= not f_dcd_rf1_div_beg ; -- tiup ; + rf1_c_k_frac(1 to 52) <= (1 to 52 => f_dcd_rf1_uc_fc_1_minus); + + rf1_b_k_frac(0) <= bop_uc_imm ; + rf1_b_k_frac(1) <= f_dcd_rf1_uc_fb_0_75 ; + rf1_b_k_frac(2 to 52) <= (2 to 52 => tidn); + + + --===================================================================== + -- selects for operand bypass muxes (also known as: data forwarding ) + --===================================================================== + + + -- forcing invalid causes selection of immediate data + + cop_uc_imm <= f_dcd_rf1_uc_fc_0_5 or f_dcd_rf1_uc_fc_1_0 or f_dcd_rf1_uc_fc_1_minus ; + bop_uc_imm <= f_dcd_rf1_uc_fb_0_5 or f_dcd_rf1_uc_fb_1_0 or f_dcd_rf1_uc_fb_0_75 ; + + + aop_valid_sign <= (f_dcd_rf1_aop_valid and not f_dcd_rf1_uc_fa_pos) ; + cop_valid_sign <= (f_dcd_rf1_cop_valid and not f_dcd_rf1_uc_fc_pos and not cop_uc_imm) ; + bop_valid_sign <= (f_dcd_rf1_bop_valid and not f_dcd_rf1_uc_fb_pos and not bop_uc_imm) ; + + aop_valid_plus <= (f_dcd_rf1_aop_valid ); + cop_valid_plus <= (f_dcd_rf1_cop_valid and not cop_uc_imm); + bop_valid_plus <= (f_dcd_rf1_bop_valid and not bop_uc_imm); + + sel_a_no_byp_s <= not( f_dcd_rf1_bypsel_a_res0 or f_dcd_rf1_bypsel_a_res1 or f_dcd_rf1_bypsel_a_load0 or f_dcd_rf1_bypsel_a_load1 or not aop_valid_sign); + sel_c_no_byp_s <= not( f_dcd_rf1_bypsel_c_res0 or f_dcd_rf1_bypsel_c_res1 or f_dcd_rf1_bypsel_c_load0 or f_dcd_rf1_bypsel_c_load1 or not cop_valid_sign); + sel_b_no_byp_s <= not( f_dcd_rf1_bypsel_b_res0 or f_dcd_rf1_bypsel_b_res1 or f_dcd_rf1_bypsel_b_load0 or f_dcd_rf1_bypsel_b_load1 or not bop_valid_sign); + + sel_a_no_byp <= not( f_dcd_rf1_bypsel_a_res0 or f_dcd_rf1_bypsel_a_res1 or f_dcd_rf1_bypsel_a_load0 or f_dcd_rf1_bypsel_a_load1 or not aop_valid_plus); + sel_c_no_byp <= not( f_dcd_rf1_bypsel_c_res0 or f_dcd_rf1_bypsel_c_res1 or f_dcd_rf1_bypsel_c_load0 or f_dcd_rf1_bypsel_c_load1 or not cop_valid_plus); + sel_b_no_byp <= not( f_dcd_rf1_bypsel_b_res0 or f_dcd_rf1_bypsel_b_res1 or f_dcd_rf1_bypsel_b_load0 or f_dcd_rf1_bypsel_b_load1 or not bop_valid_plus); + + + sel_a_res0_s <= aop_valid_sign and f_dcd_rf1_bypsel_a_res0 ; + sel_a_res1_s <= aop_valid_sign and f_dcd_rf1_bypsel_a_res1 ; + sel_a_load0_s <= aop_valid_sign and f_dcd_rf1_bypsel_a_load0 ; + sel_a_load1_s <= aop_valid_sign and f_dcd_rf1_bypsel_a_load1 ; + + sel_c_res0_s <= cop_valid_sign and f_dcd_rf1_bypsel_c_res0 ; + sel_c_res1_s <= cop_valid_sign and f_dcd_rf1_bypsel_c_res1 ; + sel_c_load0_s <= cop_valid_sign and f_dcd_rf1_bypsel_c_load0 ; + sel_c_load1_s <= cop_valid_sign and f_dcd_rf1_bypsel_c_load1 ; + + sel_b_res0_s <= bop_valid_sign and f_dcd_rf1_bypsel_b_res0 ; + sel_b_res1_s <= bop_valid_sign and f_dcd_rf1_bypsel_b_res1 ; + sel_b_load0_s <= bop_valid_sign and f_dcd_rf1_bypsel_b_load0 ; + sel_b_load1_s <= bop_valid_sign and f_dcd_rf1_bypsel_b_load1 ; + + sel_a_imm <= not aop_valid_plus ; + sel_a_res0 <= aop_valid_plus and f_dcd_rf1_bypsel_a_res0 ; + sel_a_res1 <= aop_valid_plus and f_dcd_rf1_bypsel_a_res1 ; + sel_a_load0 <= aop_valid_plus and f_dcd_rf1_bypsel_a_load0 ; + sel_a_load1 <= aop_valid_plus and f_dcd_rf1_bypsel_a_load1 ; + + sel_c_imm <= not cop_valid_plus ; + sel_c_res0 <= cop_valid_plus and f_dcd_rf1_bypsel_c_res0 ; + sel_c_res1 <= cop_valid_plus and f_dcd_rf1_bypsel_c_res1 ; + sel_c_load0 <= cop_valid_plus and f_dcd_rf1_bypsel_c_load0 ; + sel_c_load1 <= cop_valid_plus and f_dcd_rf1_bypsel_c_load1 ; + + sel_b_imm <= not bop_valid_plus ; + sel_b_res0 <= bop_valid_plus and f_dcd_rf1_bypsel_b_res0 ; + sel_b_res1 <= bop_valid_plus and f_dcd_rf1_bypsel_b_res1 ; + sel_b_load0 <= bop_valid_plus and f_dcd_rf1_bypsel_b_load0 ; + sel_b_load1 <= bop_valid_plus and f_dcd_rf1_bypsel_b_load1 ; + + + -------------------------- + -- sign bit data forwarding + -------------------------- + + ex6_sign_res_ear <= f_rnd_ex6_res_sign; + ex6_sign_res_dly <= f_fpr_ex7_frt_sign; + ex6_sign_lod_ear <= f_fpr_ex6_load_sign; + ex6_sign_lod_dly <= f_fpr_ex7_load_sign; + +fwd_a_sign_pre1: rf1_a_sign_pre1_b <= not( ( sel_a_res0_s and ex6_sign_res_ear ) or ( sel_a_res1_s and ex6_sign_res_dly ) ); +fwd_a_sign_pre2: rf1_a_sign_pre2_b <= not( ( sel_a_load0_s and ex6_sign_lod_ear ) or ( sel_a_load1_s and ex6_sign_lod_dly ) ); +fwd_a_sign_pre: rf1_a_sign_pre <= not( rf1_a_sign_pre1_b and rf1_a_sign_pre2_b ); + +fwd_c_sign_pre1: rf1_c_sign_pre1_b <= not( ( sel_c_res0_s and ex6_sign_res_ear ) or ( sel_c_res1_s and ex6_sign_res_dly ) ); +fwd_c_sign_pre2: rf1_c_sign_pre2_b <= not( ( sel_c_load0_s and ex6_sign_lod_ear ) or ( sel_c_load1_s and ex6_sign_lod_dly ) ); +fwd_c_sign_pre: rf1_c_sign_pre <= not( rf1_c_sign_pre1_b and rf1_c_sign_pre2_b ); + +fwd_b_sign_pre1: rf1_b_sign_pre1_b <= not( ( sel_b_res0_s and ex6_sign_res_ear ) or ( sel_b_res1_s and ex6_sign_res_dly ) ); +fwd_b_sign_pre2: rf1_b_sign_pre2_b <= not( ( sel_b_load0_s and ex6_sign_lod_ear ) or ( sel_b_load1_s and ex6_sign_lod_dly ) ); +fwd_b_sign_pre: rf1_b_sign_pre <= not( rf1_b_sign_pre1_b and rf1_b_sign_pre2_b ); + + rf1_a_sign_prebyp <= rf1_a_sign_pre ; -- may need to manually rebuffer + rf1_c_sign_prebyp <= rf1_c_sign_pre ; -- may need to manually rebuffer + rf1_b_sign_prebyp <= rf1_b_sign_pre ; -- may need to manually rebuffer + + -------------------------- + -- exponent data forwarding + -------------------------- + + ex6_load_expo(1 to 13) <= tidn & tidn & f_fpr_ex6_load_expo(3 to 13) ; + ex6_expo_res_ear(1 to 13) <= f_rnd_ex6_res_expo(1 to 13); + ex6_expo_res_dly(1 to 13) <= f_fpr_ex7_frt_expo(1 to 13); + ex6_expo_lod_ear(1 to 13) <= ex6_load_expo(1 to 13); + ex6_expo_lod_dly(1 to 13) <= tidn & tidn & f_fpr_ex7_load_expo(3 to 13) ; + + +fwd_a_expo_pre1_01: rf1_a_expo_pre1_b( 1) <= not( ( sel_a_res0 and ex6_expo_res_ear( 1) ) or ( sel_a_res1 and ex6_expo_res_dly( 1) ) ); +fwd_a_expo_pre1_02: rf1_a_expo_pre1_b( 2) <= not( ( sel_a_res0 and ex6_expo_res_ear( 2) ) or ( sel_a_res1 and ex6_expo_res_dly( 2) ) ); +fwd_a_expo_pre1_03: rf1_a_expo_pre1_b( 3) <= not( ( sel_a_res0 and ex6_expo_res_ear( 3) ) or ( sel_a_res1 and ex6_expo_res_dly( 3) ) ); +fwd_a_expo_pre1_04: rf1_a_expo_pre1_b( 4) <= not( ( sel_a_res0 and ex6_expo_res_ear( 4) ) or ( sel_a_res1 and ex6_expo_res_dly( 4) ) ); +fwd_a_expo_pre1_05: rf1_a_expo_pre1_b( 5) <= not( ( sel_a_res0 and ex6_expo_res_ear( 5) ) or ( sel_a_res1 and ex6_expo_res_dly( 5) ) ); +fwd_a_expo_pre1_06: rf1_a_expo_pre1_b( 6) <= not( ( sel_a_res0 and ex6_expo_res_ear( 6) ) or ( sel_a_res1 and ex6_expo_res_dly( 6) ) ); +fwd_a_expo_pre1_07: rf1_a_expo_pre1_b( 7) <= not( ( sel_a_res0 and ex6_expo_res_ear( 7) ) or ( sel_a_res1 and ex6_expo_res_dly( 7) ) ); +fwd_a_expo_pre1_08: rf1_a_expo_pre1_b( 8) <= not( ( sel_a_res0 and ex6_expo_res_ear( 8) ) or ( sel_a_res1 and ex6_expo_res_dly( 8) ) ); +fwd_a_expo_pre1_09: rf1_a_expo_pre1_b( 9) <= not( ( sel_a_res0 and ex6_expo_res_ear( 9) ) or ( sel_a_res1 and ex6_expo_res_dly( 9) ) ); +fwd_a_expo_pre1_10: rf1_a_expo_pre1_b(10) <= not( ( sel_a_res0 and ex6_expo_res_ear(10) ) or ( sel_a_res1 and ex6_expo_res_dly(10) ) ); +fwd_a_expo_pre1_11: rf1_a_expo_pre1_b(11) <= not( ( sel_a_res0 and ex6_expo_res_ear(11) ) or ( sel_a_res1 and ex6_expo_res_dly(11) ) ); +fwd_a_expo_pre1_12: rf1_a_expo_pre1_b(12) <= not( ( sel_a_res0 and ex6_expo_res_ear(12) ) or ( sel_a_res1 and ex6_expo_res_dly(12) ) ); +fwd_a_expo_pre1_13: rf1_a_expo_pre1_b(13) <= not( ( sel_a_res0 and ex6_expo_res_ear(13) ) or ( sel_a_res1 and ex6_expo_res_dly(13) ) ); + +fwd_c_expo_pre1_01: rf1_c_expo_pre1_b( 1) <= not( ( sel_c_res0 and ex6_expo_res_ear( 1) ) or ( sel_c_res1 and ex6_expo_res_dly( 1) ) ); +fwd_c_expo_pre1_02: rf1_c_expo_pre1_b( 2) <= not( ( sel_c_res0 and ex6_expo_res_ear( 2) ) or ( sel_c_res1 and ex6_expo_res_dly( 2) ) ); +fwd_c_expo_pre1_03: rf1_c_expo_pre1_b( 3) <= not( ( sel_c_res0 and ex6_expo_res_ear( 3) ) or ( sel_c_res1 and ex6_expo_res_dly( 3) ) ); +fwd_c_expo_pre1_04: rf1_c_expo_pre1_b( 4) <= not( ( sel_c_res0 and ex6_expo_res_ear( 4) ) or ( sel_c_res1 and ex6_expo_res_dly( 4) ) ); +fwd_c_expo_pre1_05: rf1_c_expo_pre1_b( 5) <= not( ( sel_c_res0 and ex6_expo_res_ear( 5) ) or ( sel_c_res1 and ex6_expo_res_dly( 5) ) ); +fwd_c_expo_pre1_06: rf1_c_expo_pre1_b( 6) <= not( ( sel_c_res0 and ex6_expo_res_ear( 6) ) or ( sel_c_res1 and ex6_expo_res_dly( 6) ) ); +fwd_c_expo_pre1_07: rf1_c_expo_pre1_b( 7) <= not( ( sel_c_res0 and ex6_expo_res_ear( 7) ) or ( sel_c_res1 and ex6_expo_res_dly( 7) ) ); +fwd_c_expo_pre1_08: rf1_c_expo_pre1_b( 8) <= not( ( sel_c_res0 and ex6_expo_res_ear( 8) ) or ( sel_c_res1 and ex6_expo_res_dly( 8) ) ); +fwd_c_expo_pre1_09: rf1_c_expo_pre1_b( 9) <= not( ( sel_c_res0 and ex6_expo_res_ear( 9) ) or ( sel_c_res1 and ex6_expo_res_dly( 9) ) ); +fwd_c_expo_pre1_10: rf1_c_expo_pre1_b(10) <= not( ( sel_c_res0 and ex6_expo_res_ear(10) ) or ( sel_c_res1 and ex6_expo_res_dly(10) ) ); +fwd_c_expo_pre1_11: rf1_c_expo_pre1_b(11) <= not( ( sel_c_res0 and ex6_expo_res_ear(11) ) or ( sel_c_res1 and ex6_expo_res_dly(11) ) ); +fwd_c_expo_pre1_12: rf1_c_expo_pre1_b(12) <= not( ( sel_c_res0 and ex6_expo_res_ear(12) ) or ( sel_c_res1 and ex6_expo_res_dly(12) ) ); +fwd_c_expo_pre1_13: rf1_c_expo_pre1_b(13) <= not( ( sel_c_res0 and ex6_expo_res_ear(13) ) or ( sel_c_res1 and ex6_expo_res_dly(13) ) ); + +fwd_b_expo_pre1_01: rf1_b_expo_pre1_b( 1) <= not( ( sel_b_res0 and ex6_expo_res_ear( 1) ) or ( sel_b_res1 and ex6_expo_res_dly( 1) ) ); +fwd_b_expo_pre1_02: rf1_b_expo_pre1_b( 2) <= not( ( sel_b_res0 and ex6_expo_res_ear( 2) ) or ( sel_b_res1 and ex6_expo_res_dly( 2) ) ); +fwd_b_expo_pre1_03: rf1_b_expo_pre1_b( 3) <= not( ( sel_b_res0 and ex6_expo_res_ear( 3) ) or ( sel_b_res1 and ex6_expo_res_dly( 3) ) ); +fwd_b_expo_pre1_04: rf1_b_expo_pre1_b( 4) <= not( ( sel_b_res0 and ex6_expo_res_ear( 4) ) or ( sel_b_res1 and ex6_expo_res_dly( 4) ) ); +fwd_b_expo_pre1_05: rf1_b_expo_pre1_b( 5) <= not( ( sel_b_res0 and ex6_expo_res_ear( 5) ) or ( sel_b_res1 and ex6_expo_res_dly( 5) ) ); +fwd_b_expo_pre1_06: rf1_b_expo_pre1_b( 6) <= not( ( sel_b_res0 and ex6_expo_res_ear( 6) ) or ( sel_b_res1 and ex6_expo_res_dly( 6) ) ); +fwd_b_expo_pre1_07: rf1_b_expo_pre1_b( 7) <= not( ( sel_b_res0 and ex6_expo_res_ear( 7) ) or ( sel_b_res1 and ex6_expo_res_dly( 7) ) ); +fwd_b_expo_pre1_08: rf1_b_expo_pre1_b( 8) <= not( ( sel_b_res0 and ex6_expo_res_ear( 8) ) or ( sel_b_res1 and ex6_expo_res_dly( 8) ) ); +fwd_b_expo_pre1_09: rf1_b_expo_pre1_b( 9) <= not( ( sel_b_res0 and ex6_expo_res_ear( 9) ) or ( sel_b_res1 and ex6_expo_res_dly( 9) ) ); +fwd_b_expo_pre1_10: rf1_b_expo_pre1_b(10) <= not( ( sel_b_res0 and ex6_expo_res_ear(10) ) or ( sel_b_res1 and ex6_expo_res_dly(10) ) ); +fwd_b_expo_pre1_11: rf1_b_expo_pre1_b(11) <= not( ( sel_b_res0 and ex6_expo_res_ear(11) ) or ( sel_b_res1 and ex6_expo_res_dly(11) ) ); +fwd_b_expo_pre1_12: rf1_b_expo_pre1_b(12) <= not( ( sel_b_res0 and ex6_expo_res_ear(12) ) or ( sel_b_res1 and ex6_expo_res_dly(12) ) ); +fwd_b_expo_pre1_13: rf1_b_expo_pre1_b(13) <= not( ( sel_b_res0 and ex6_expo_res_ear(13) ) or ( sel_b_res1 and ex6_expo_res_dly(13) ) ); + + +fwd_a_expo_pre2_01: rf1_a_expo_pre2_b( 1) <= not( (sel_a_load0 and ex6_expo_lod_ear( 1) ) or (sel_a_load1 and ex6_expo_lod_dly( 1) ) ); +fwd_a_expo_pre2_02: rf1_a_expo_pre2_b( 2) <= not( (sel_a_load0 and ex6_expo_lod_ear( 2) ) or (sel_a_load1 and ex6_expo_lod_dly( 2) ) ); +fwd_a_expo_pre2_03: rf1_a_expo_pre2_b( 3) <= not( (sel_a_load0 and ex6_expo_lod_ear( 3) ) or (sel_a_load1 and ex6_expo_lod_dly( 3) ) ); +fwd_a_expo_pre2_04: rf1_a_expo_pre2_b( 4) <= not( (sel_a_load0 and ex6_expo_lod_ear( 4) ) or (sel_a_load1 and ex6_expo_lod_dly( 4) ) ); +fwd_a_expo_pre2_05: rf1_a_expo_pre2_b( 5) <= not( (sel_a_load0 and ex6_expo_lod_ear( 5) ) or (sel_a_load1 and ex6_expo_lod_dly( 5) ) ); +fwd_a_expo_pre2_06: rf1_a_expo_pre2_b( 6) <= not( (sel_a_load0 and ex6_expo_lod_ear( 6) ) or (sel_a_load1 and ex6_expo_lod_dly( 6) ) ); +fwd_a_expo_pre2_07: rf1_a_expo_pre2_b( 7) <= not( (sel_a_load0 and ex6_expo_lod_ear( 7) ) or (sel_a_load1 and ex6_expo_lod_dly( 7) ) ); +fwd_a_expo_pre2_08: rf1_a_expo_pre2_b( 8) <= not( (sel_a_load0 and ex6_expo_lod_ear( 8) ) or (sel_a_load1 and ex6_expo_lod_dly( 8) ) ); +fwd_a_expo_pre2_09: rf1_a_expo_pre2_b( 9) <= not( (sel_a_load0 and ex6_expo_lod_ear( 9) ) or (sel_a_load1 and ex6_expo_lod_dly( 9) ) ); +fwd_a_expo_pre2_10: rf1_a_expo_pre2_b(10) <= not( (sel_a_load0 and ex6_expo_lod_ear(10) ) or (sel_a_load1 and ex6_expo_lod_dly(10) ) ); +fwd_a_expo_pre2_11: rf1_a_expo_pre2_b(11) <= not( (sel_a_load0 and ex6_expo_lod_ear(11) ) or (sel_a_load1 and ex6_expo_lod_dly(11) ) ); +fwd_a_expo_pre2_12: rf1_a_expo_pre2_b(12) <= not( (sel_a_load0 and ex6_expo_lod_ear(12) ) or (sel_a_load1 and ex6_expo_lod_dly(12) ) ); +fwd_a_expo_pre2_13: rf1_a_expo_pre2_b(13) <= not( (sel_a_load0 and ex6_expo_lod_ear(13) ) or (sel_a_load1 and ex6_expo_lod_dly(13) ) ); + +fwd_c_expo_pre2_01: rf1_c_expo_pre2_b( 1) <= not( (sel_c_load0 and ex6_expo_lod_ear( 1) ) or (sel_c_load1 and ex6_expo_lod_dly( 1) ) ); +fwd_c_expo_pre2_02: rf1_c_expo_pre2_b( 2) <= not( (sel_c_load0 and ex6_expo_lod_ear( 2) ) or (sel_c_load1 and ex6_expo_lod_dly( 2) ) ); +fwd_c_expo_pre2_03: rf1_c_expo_pre2_b( 3) <= not( (sel_c_load0 and ex6_expo_lod_ear( 3) ) or (sel_c_load1 and ex6_expo_lod_dly( 3) ) ); +fwd_c_expo_pre2_04: rf1_c_expo_pre2_b( 4) <= not( (sel_c_load0 and ex6_expo_lod_ear( 4) ) or (sel_c_load1 and ex6_expo_lod_dly( 4) ) ); +fwd_c_expo_pre2_05: rf1_c_expo_pre2_b( 5) <= not( (sel_c_load0 and ex6_expo_lod_ear( 5) ) or (sel_c_load1 and ex6_expo_lod_dly( 5) ) ); +fwd_c_expo_pre2_06: rf1_c_expo_pre2_b( 6) <= not( (sel_c_load0 and ex6_expo_lod_ear( 6) ) or (sel_c_load1 and ex6_expo_lod_dly( 6) ) ); +fwd_c_expo_pre2_07: rf1_c_expo_pre2_b( 7) <= not( (sel_c_load0 and ex6_expo_lod_ear( 7) ) or (sel_c_load1 and ex6_expo_lod_dly( 7) ) ); +fwd_c_expo_pre2_08: rf1_c_expo_pre2_b( 8) <= not( (sel_c_load0 and ex6_expo_lod_ear( 8) ) or (sel_c_load1 and ex6_expo_lod_dly( 8) ) ); +fwd_c_expo_pre2_09: rf1_c_expo_pre2_b( 9) <= not( (sel_c_load0 and ex6_expo_lod_ear( 9) ) or (sel_c_load1 and ex6_expo_lod_dly( 9) ) ); +fwd_c_expo_pre2_10: rf1_c_expo_pre2_b(10) <= not( (sel_c_load0 and ex6_expo_lod_ear(10) ) or (sel_c_load1 and ex6_expo_lod_dly(10) ) ); +fwd_c_expo_pre2_11: rf1_c_expo_pre2_b(11) <= not( (sel_c_load0 and ex6_expo_lod_ear(11) ) or (sel_c_load1 and ex6_expo_lod_dly(11) ) ); +fwd_c_expo_pre2_12: rf1_c_expo_pre2_b(12) <= not( (sel_c_load0 and ex6_expo_lod_ear(12) ) or (sel_c_load1 and ex6_expo_lod_dly(12) ) ); +fwd_c_expo_pre2_13: rf1_c_expo_pre2_b(13) <= not( (sel_c_load0 and ex6_expo_lod_ear(13) ) or (sel_c_load1 and ex6_expo_lod_dly(13) ) ); + +fwd_b_expo_pre2_01: rf1_b_expo_pre2_b( 1) <= not( (sel_b_load0 and ex6_expo_lod_ear( 1) ) or (sel_b_load1 and ex6_expo_lod_dly( 1) ) ); +fwd_b_expo_pre2_02: rf1_b_expo_pre2_b( 2) <= not( (sel_b_load0 and ex6_expo_lod_ear( 2) ) or (sel_b_load1 and ex6_expo_lod_dly( 2) ) ); +fwd_b_expo_pre2_03: rf1_b_expo_pre2_b( 3) <= not( (sel_b_load0 and ex6_expo_lod_ear( 3) ) or (sel_b_load1 and ex6_expo_lod_dly( 3) ) ); +fwd_b_expo_pre2_04: rf1_b_expo_pre2_b( 4) <= not( (sel_b_load0 and ex6_expo_lod_ear( 4) ) or (sel_b_load1 and ex6_expo_lod_dly( 4) ) ); +fwd_b_expo_pre2_05: rf1_b_expo_pre2_b( 5) <= not( (sel_b_load0 and ex6_expo_lod_ear( 5) ) or (sel_b_load1 and ex6_expo_lod_dly( 5) ) ); +fwd_b_expo_pre2_06: rf1_b_expo_pre2_b( 6) <= not( (sel_b_load0 and ex6_expo_lod_ear( 6) ) or (sel_b_load1 and ex6_expo_lod_dly( 6) ) ); +fwd_b_expo_pre2_07: rf1_b_expo_pre2_b( 7) <= not( (sel_b_load0 and ex6_expo_lod_ear( 7) ) or (sel_b_load1 and ex6_expo_lod_dly( 7) ) ); +fwd_b_expo_pre2_08: rf1_b_expo_pre2_b( 8) <= not( (sel_b_load0 and ex6_expo_lod_ear( 8) ) or (sel_b_load1 and ex6_expo_lod_dly( 8) ) ); +fwd_b_expo_pre2_09: rf1_b_expo_pre2_b( 9) <= not( (sel_b_load0 and ex6_expo_lod_ear( 9) ) or (sel_b_load1 and ex6_expo_lod_dly( 9) ) ); +fwd_b_expo_pre2_10: rf1_b_expo_pre2_b(10) <= not( (sel_b_load0 and ex6_expo_lod_ear(10) ) or (sel_b_load1 and ex6_expo_lod_dly(10) ) ); +fwd_b_expo_pre2_11: rf1_b_expo_pre2_b(11) <= not( (sel_b_load0 and ex6_expo_lod_ear(11) ) or (sel_b_load1 and ex6_expo_lod_dly(11) ) ); +fwd_b_expo_pre2_12: rf1_b_expo_pre2_b(12) <= not( (sel_b_load0 and ex6_expo_lod_ear(12) ) or (sel_b_load1 and ex6_expo_lod_dly(12) ) ); +fwd_b_expo_pre2_13: rf1_b_expo_pre2_b(13) <= not( (sel_b_load0 and ex6_expo_lod_ear(13) ) or (sel_b_load1 and ex6_expo_lod_dly(13) ) ); + + + + +fwd_a_expo_pre3_01: rf1_a_expo_pre3_b( 1) <= not( tidn ); +fwd_a_expo_pre3_02: rf1_a_expo_pre3_b( 2) <= not( tidn ); +fwd_a_expo_pre3_03: rf1_a_expo_pre3_b( 3) <= not( sel_a_imm and rf1_a_k_expo( 3) ); +fwd_a_expo_pre3_04: rf1_a_expo_pre3_b( 4) <= not( sel_a_imm and rf1_a_k_expo( 4) ); +fwd_a_expo_pre3_05: rf1_a_expo_pre3_b( 5) <= not( sel_a_imm and rf1_a_k_expo( 5) ); +fwd_a_expo_pre3_06: rf1_a_expo_pre3_b( 6) <= not( sel_a_imm and rf1_a_k_expo( 6) ); +fwd_a_expo_pre3_07: rf1_a_expo_pre3_b( 7) <= not( sel_a_imm and rf1_a_k_expo( 7) ); +fwd_a_expo_pre3_08: rf1_a_expo_pre3_b( 8) <= not( sel_a_imm and rf1_a_k_expo( 8) ); +fwd_a_expo_pre3_09: rf1_a_expo_pre3_b( 9) <= not( sel_a_imm and rf1_a_k_expo( 9) ); +fwd_a_expo_pre3_10: rf1_a_expo_pre3_b(10) <= not( sel_a_imm and rf1_a_k_expo(10) ); +fwd_a_expo_pre3_11: rf1_a_expo_pre3_b(11) <= not( sel_a_imm and rf1_a_k_expo(11) ); +fwd_a_expo_pre3_12: rf1_a_expo_pre3_b(12) <= not( sel_a_imm and rf1_a_k_expo(12) ); +fwd_a_expo_pre3_13: rf1_a_expo_pre3_b(13) <= not( sel_a_imm and rf1_a_k_expo(13) ); + +fwd_c_expo_pre3_01: rf1_c_expo_pre3_b( 1) <= not( tidn ); +fwd_c_expo_pre3_02: rf1_c_expo_pre3_b( 2) <= not( tidn ); +fwd_c_expo_pre3_03: rf1_c_expo_pre3_b( 3) <= not( tidn ); +fwd_c_expo_pre3_04: rf1_c_expo_pre3_b( 4) <= not( sel_c_imm ); +fwd_c_expo_pre3_05: rf1_c_expo_pre3_b( 5) <= not( sel_c_imm ); +fwd_c_expo_pre3_06: rf1_c_expo_pre3_b( 6) <= not( sel_c_imm ); +fwd_c_expo_pre3_07: rf1_c_expo_pre3_b( 7) <= not( sel_c_imm ); +fwd_c_expo_pre3_08: rf1_c_expo_pre3_b( 8) <= not( sel_c_imm ); +fwd_c_expo_pre3_09: rf1_c_expo_pre3_b( 9) <= not( sel_c_imm ); +fwd_c_expo_pre3_10: rf1_c_expo_pre3_b(10) <= not( sel_c_imm ); +fwd_c_expo_pre3_11: rf1_c_expo_pre3_b(11) <= not( sel_c_imm ); +fwd_c_expo_pre3_12: rf1_c_expo_pre3_b(12) <= not( sel_c_imm ); +fwd_c_expo_pre3_13: rf1_c_expo_pre3_b(13) <= not( sel_c_imm and rf1_c_k_expo(13) ); + +fwd_b_expo_pre3_01: rf1_b_expo_pre3_b( 1) <= not( tidn ); +fwd_b_expo_pre3_02: rf1_b_expo_pre3_b( 2) <= not( tidn ); +fwd_b_expo_pre3_03: rf1_b_expo_pre3_b( 3) <= not( tidn ); +fwd_b_expo_pre3_04: rf1_b_expo_pre3_b( 4) <= not( sel_b_imm and rf1_b_k_expo( 4) ); +fwd_b_expo_pre3_05: rf1_b_expo_pre3_b( 5) <= not( sel_b_imm and rf1_b_k_expo( 5) ); +fwd_b_expo_pre3_06: rf1_b_expo_pre3_b( 6) <= not( sel_b_imm and rf1_b_k_expo( 6) ); +fwd_b_expo_pre3_07: rf1_b_expo_pre3_b( 7) <= not( sel_b_imm and rf1_b_k_expo( 7) ); +fwd_b_expo_pre3_08: rf1_b_expo_pre3_b( 8) <= not( sel_b_imm and rf1_b_k_expo( 8) ); +fwd_b_expo_pre3_09: rf1_b_expo_pre3_b( 9) <= not( sel_b_imm and rf1_b_k_expo( 9) ); +fwd_b_expo_pre3_10: rf1_b_expo_pre3_b(10) <= not( sel_b_imm and rf1_b_k_expo(10) ); +fwd_b_expo_pre3_11: rf1_b_expo_pre3_b(11) <= not( sel_b_imm and rf1_b_k_expo(11) ); +fwd_b_expo_pre3_12: rf1_b_expo_pre3_b(12) <= not( sel_b_imm and rf1_b_k_expo(12) ); +fwd_b_expo_pre3_13: rf1_b_expo_pre3_b(13) <= not( sel_b_imm and rf1_b_k_expo(13) ); + + +fwd_a_expo_pre_01: rf1_a_expo_pre( 1) <= not( rf1_a_expo_pre1_b( 1) and rf1_a_expo_pre2_b( 1) ); +fwd_a_expo_pre_02: rf1_a_expo_pre( 2) <= not( rf1_a_expo_pre1_b( 2) and rf1_a_expo_pre2_b( 2) ); +fwd_a_expo_pre_03: rf1_a_expo_pre( 3) <= not( rf1_a_expo_pre1_b( 3) and rf1_a_expo_pre2_b( 3) and rf1_a_expo_pre3_b( 3) ); +fwd_a_expo_pre_04: rf1_a_expo_pre( 4) <= not( rf1_a_expo_pre1_b( 4) and rf1_a_expo_pre2_b( 4) and rf1_a_expo_pre3_b( 4) ); +fwd_a_expo_pre_05: rf1_a_expo_pre( 5) <= not( rf1_a_expo_pre1_b( 5) and rf1_a_expo_pre2_b( 5) and rf1_a_expo_pre3_b( 5) ); +fwd_a_expo_pre_06: rf1_a_expo_pre( 6) <= not( rf1_a_expo_pre1_b( 6) and rf1_a_expo_pre2_b( 6) and rf1_a_expo_pre3_b( 6) ); +fwd_a_expo_pre_07: rf1_a_expo_pre( 7) <= not( rf1_a_expo_pre1_b( 7) and rf1_a_expo_pre2_b( 7) and rf1_a_expo_pre3_b( 7) ); +fwd_a_expo_pre_08: rf1_a_expo_pre( 8) <= not( rf1_a_expo_pre1_b( 8) and rf1_a_expo_pre2_b( 8) and rf1_a_expo_pre3_b( 8) ); +fwd_a_expo_pre_09: rf1_a_expo_pre( 9) <= not( rf1_a_expo_pre1_b( 9) and rf1_a_expo_pre2_b( 9) and rf1_a_expo_pre3_b( 9) ); +fwd_a_expo_pre_10: rf1_a_expo_pre(10) <= not( rf1_a_expo_pre1_b(10) and rf1_a_expo_pre2_b(10) and rf1_a_expo_pre3_b(10) ); +fwd_a_expo_pre_11: rf1_a_expo_pre(11) <= not( rf1_a_expo_pre1_b(11) and rf1_a_expo_pre2_b(11) and rf1_a_expo_pre3_b(11) ); +fwd_a_expo_pre_12: rf1_a_expo_pre(12) <= not( rf1_a_expo_pre1_b(12) and rf1_a_expo_pre2_b(12) and rf1_a_expo_pre3_b(12) ); +fwd_a_expo_pre_13: rf1_a_expo_pre(13) <= not( rf1_a_expo_pre1_b(13) and rf1_a_expo_pre2_b(13) and rf1_a_expo_pre3_b(13) ); + +fwd_c_expo_pre_01: rf1_c_expo_pre( 1) <= not( rf1_c_expo_pre1_b( 1) and rf1_c_expo_pre2_b( 1) ); +fwd_c_expo_pre_02: rf1_c_expo_pre( 2) <= not( rf1_c_expo_pre1_b( 2) and rf1_c_expo_pre2_b( 2) ); +fwd_c_expo_pre_03: rf1_c_expo_pre( 3) <= not( rf1_c_expo_pre1_b( 3) and rf1_c_expo_pre2_b( 3) ); +fwd_c_expo_pre_04: rf1_c_expo_pre( 4) <= not( rf1_c_expo_pre1_b( 4) and rf1_c_expo_pre2_b( 4) and rf1_c_expo_pre3_b( 4) ); +fwd_c_expo_pre_05: rf1_c_expo_pre( 5) <= not( rf1_c_expo_pre1_b( 5) and rf1_c_expo_pre2_b( 5) and rf1_c_expo_pre3_b( 5) ); +fwd_c_expo_pre_06: rf1_c_expo_pre( 6) <= not( rf1_c_expo_pre1_b( 6) and rf1_c_expo_pre2_b( 6) and rf1_c_expo_pre3_b( 6) ); +fwd_c_expo_pre_07: rf1_c_expo_pre( 7) <= not( rf1_c_expo_pre1_b( 7) and rf1_c_expo_pre2_b( 7) and rf1_c_expo_pre3_b( 7) ); +fwd_c_expo_pre_08: rf1_c_expo_pre( 8) <= not( rf1_c_expo_pre1_b( 8) and rf1_c_expo_pre2_b( 8) and rf1_c_expo_pre3_b( 8) ); +fwd_c_expo_pre_09: rf1_c_expo_pre( 9) <= not( rf1_c_expo_pre1_b( 9) and rf1_c_expo_pre2_b( 9) and rf1_c_expo_pre3_b( 9) ); +fwd_c_expo_pre_10: rf1_c_expo_pre(10) <= not( rf1_c_expo_pre1_b(10) and rf1_c_expo_pre2_b(10) and rf1_c_expo_pre3_b(10) ); +fwd_c_expo_pre_11: rf1_c_expo_pre(11) <= not( rf1_c_expo_pre1_b(11) and rf1_c_expo_pre2_b(11) and rf1_c_expo_pre3_b(11) ); +fwd_c_expo_pre_12: rf1_c_expo_pre(12) <= not( rf1_c_expo_pre1_b(12) and rf1_c_expo_pre2_b(12) and rf1_c_expo_pre3_b(12) ); +fwd_c_expo_pre_13: rf1_c_expo_pre(13) <= not( rf1_c_expo_pre1_b(13) and rf1_c_expo_pre2_b(13) and rf1_c_expo_pre3_b(13) ); + +fwd_b_expo_pre_01: rf1_b_expo_pre( 1) <= not( rf1_b_expo_pre1_b( 1) and rf1_b_expo_pre2_b( 1) ); +fwd_b_expo_pre_02: rf1_b_expo_pre( 2) <= not( rf1_b_expo_pre1_b( 2) and rf1_b_expo_pre2_b( 2) ); +fwd_b_expo_pre_03: rf1_b_expo_pre( 3) <= not( rf1_b_expo_pre1_b( 3) and rf1_b_expo_pre2_b( 3) ); +fwd_b_expo_pre_04: rf1_b_expo_pre( 4) <= not( rf1_b_expo_pre1_b( 4) and rf1_b_expo_pre2_b( 4) and rf1_b_expo_pre3_b( 4) ); +fwd_b_expo_pre_05: rf1_b_expo_pre( 5) <= not( rf1_b_expo_pre1_b( 5) and rf1_b_expo_pre2_b( 5) and rf1_b_expo_pre3_b( 5) ); +fwd_b_expo_pre_06: rf1_b_expo_pre( 6) <= not( rf1_b_expo_pre1_b( 6) and rf1_b_expo_pre2_b( 6) and rf1_b_expo_pre3_b( 6) ); +fwd_b_expo_pre_07: rf1_b_expo_pre( 7) <= not( rf1_b_expo_pre1_b( 7) and rf1_b_expo_pre2_b( 7) and rf1_b_expo_pre3_b( 7) ); +fwd_b_expo_pre_08: rf1_b_expo_pre( 8) <= not( rf1_b_expo_pre1_b( 8) and rf1_b_expo_pre2_b( 8) and rf1_b_expo_pre3_b( 8) ); +fwd_b_expo_pre_09: rf1_b_expo_pre( 9) <= not( rf1_b_expo_pre1_b( 9) and rf1_b_expo_pre2_b( 9) and rf1_b_expo_pre3_b( 9) ); +fwd_b_expo_pre_10: rf1_b_expo_pre(10) <= not( rf1_b_expo_pre1_b(10) and rf1_b_expo_pre2_b(10) and rf1_b_expo_pre3_b(10) ); +fwd_b_expo_pre_11: rf1_b_expo_pre(11) <= not( rf1_b_expo_pre1_b(11) and rf1_b_expo_pre2_b(11) and rf1_b_expo_pre3_b(11) ); +fwd_b_expo_pre_12: rf1_b_expo_pre(12) <= not( rf1_b_expo_pre1_b(12) and rf1_b_expo_pre2_b(12) and rf1_b_expo_pre3_b(12) ); +fwd_b_expo_pre_13: rf1_b_expo_pre(13) <= not( rf1_b_expo_pre1_b(13) and rf1_b_expo_pre2_b(13) and rf1_b_expo_pre3_b(13) ); + + + rf1_a_expo_prebyp(1 to 13) <= rf1_a_expo_pre(1 to 13); -- may need to manually repower + rf1_c_expo_prebyp(1 to 13) <= rf1_c_expo_pre(1 to 13); -- may need to manually repower + rf1_b_expo_prebyp(1 to 13) <= rf1_b_expo_pre(1 to 13); -- may need to manually repower + + -------------------------- + -- fraction + -------------------------- + + ex6_frac_res_ear(0 to 52) <= f_rnd_ex6_res_frac(0 to 52); + ex6_frac_res_dly(0 to 52) <= f_fpr_ex7_frt_frac(0 to 52); + ex6_frac_lod_ear(0 to 52) <= f_fpr_ex6_load_frac(0 to 52); + ex6_frac_lod_dly(0 to 52) <= f_fpr_ex7_load_frac(0 to 52); + + + + + +fwd_c_frac_pre3_00: rf1_c_frac_pre3_b( 0) <= not( sel_c_imm and rf1_c_k_frac( 0) ); +fwd_c_frac_pre3_01: rf1_c_frac_pre3_b( 1) <= not( sel_c_imm and rf1_c_k_frac( 1) ); +fwd_c_frac_pre3_02: rf1_c_frac_pre3_b( 2) <= not( sel_c_imm and rf1_c_k_frac( 2) ); +fwd_c_frac_pre3_03: rf1_c_frac_pre3_b( 3) <= not( sel_c_imm and rf1_c_k_frac( 3) ); +fwd_c_frac_pre3_04: rf1_c_frac_pre3_b( 4) <= not( sel_c_imm and rf1_c_k_frac( 4) ); +fwd_c_frac_pre3_05: rf1_c_frac_pre3_b( 5) <= not( sel_c_imm and rf1_c_k_frac( 5) ); +fwd_c_frac_pre3_06: rf1_c_frac_pre3_b( 6) <= not( sel_c_imm and rf1_c_k_frac( 6) ); +fwd_c_frac_pre3_07: rf1_c_frac_pre3_b( 7) <= not( sel_c_imm and rf1_c_k_frac( 7) ); +fwd_c_frac_pre3_08: rf1_c_frac_pre3_b( 8) <= not( sel_c_imm and rf1_c_k_frac( 8) ); +fwd_c_frac_pre3_09: rf1_c_frac_pre3_b( 9) <= not( sel_c_imm and rf1_c_k_frac( 9) ); +fwd_c_frac_pre3_10: rf1_c_frac_pre3_b(10) <= not( sel_c_imm and rf1_c_k_frac(10) ); +fwd_c_frac_pre3_11: rf1_c_frac_pre3_b(11) <= not( sel_c_imm and rf1_c_k_frac(11) ); +fwd_c_frac_pre3_12: rf1_c_frac_pre3_b(12) <= not( sel_c_imm and rf1_c_k_frac(12) ); +fwd_c_frac_pre3_13: rf1_c_frac_pre3_b(13) <= not( sel_c_imm and rf1_c_k_frac(13) ); +fwd_c_frac_pre3_14: rf1_c_frac_pre3_b(14) <= not( sel_c_imm and rf1_c_k_frac(14) ); +fwd_c_frac_pre3_15: rf1_c_frac_pre3_b(15) <= not( sel_c_imm and rf1_c_k_frac(15) ); +fwd_c_frac_pre3_16: rf1_c_frac_pre3_b(16) <= not( sel_c_imm and rf1_c_k_frac(16) ); +fwd_c_frac_pre3_17: rf1_c_frac_pre3_b(17) <= not( sel_c_imm and rf1_c_k_frac(17) ); +fwd_c_frac_pre3_18: rf1_c_frac_pre3_b(18) <= not( sel_c_imm and rf1_c_k_frac(18) ); +fwd_c_frac_pre3_19: rf1_c_frac_pre3_b(19) <= not( sel_c_imm and rf1_c_k_frac(19) ); +fwd_c_frac_pre3_20: rf1_c_frac_pre3_b(20) <= not( sel_c_imm and rf1_c_k_frac(20) ); +fwd_c_frac_pre3_21: rf1_c_frac_pre3_b(21) <= not( sel_c_imm and rf1_c_k_frac(21) ); +fwd_c_frac_pre3_22: rf1_c_frac_pre3_b(22) <= not( sel_c_imm and rf1_c_k_frac(22) ); +fwd_c_frac_pre3_23: rf1_c_frac_pre3_b(23) <= not( sel_c_imm and rf1_c_k_frac(23) ); +fwd_c_frac_pre3_24: rf1_c_frac_pre3_b(24) <= not( sel_c_imm and rf1_c_k_frac(24) ); +fwd_c_frac_pre3_25: rf1_c_frac_pre3_b(25) <= not( sel_c_imm and rf1_c_k_frac(25) ); +fwd_c_frac_pre3_26: rf1_c_frac_pre3_b(26) <= not( sel_c_imm and rf1_c_k_frac(26) ); +fwd_c_frac_pre3_27: rf1_c_frac_pre3_b(27) <= not( sel_c_imm and rf1_c_k_frac(27) ); +fwd_c_frac_pre3_28: rf1_c_frac_pre3_b(28) <= not( sel_c_imm and rf1_c_k_frac(28) ); +fwd_c_frac_pre3_29: rf1_c_frac_pre3_b(29) <= not( sel_c_imm and rf1_c_k_frac(29) ); +fwd_c_frac_pre3_30: rf1_c_frac_pre3_b(30) <= not( sel_c_imm and rf1_c_k_frac(30) ); +fwd_c_frac_pre3_31: rf1_c_frac_pre3_b(31) <= not( sel_c_imm and rf1_c_k_frac(31) ); +fwd_c_frac_pre3_32: rf1_c_frac_pre3_b(32) <= not( sel_c_imm and rf1_c_k_frac(32) ); +fwd_c_frac_pre3_33: rf1_c_frac_pre3_b(33) <= not( sel_c_imm and rf1_c_k_frac(33) ); +fwd_c_frac_pre3_34: rf1_c_frac_pre3_b(34) <= not( sel_c_imm and rf1_c_k_frac(34) ); +fwd_c_frac_pre3_35: rf1_c_frac_pre3_b(35) <= not( sel_c_imm and rf1_c_k_frac(35) ); +fwd_c_frac_pre3_36: rf1_c_frac_pre3_b(36) <= not( sel_c_imm and rf1_c_k_frac(36) ); +fwd_c_frac_pre3_37: rf1_c_frac_pre3_b(37) <= not( sel_c_imm and rf1_c_k_frac(37) ); +fwd_c_frac_pre3_38: rf1_c_frac_pre3_b(38) <= not( sel_c_imm and rf1_c_k_frac(38) ); +fwd_c_frac_pre3_39: rf1_c_frac_pre3_b(39) <= not( sel_c_imm and rf1_c_k_frac(39) ); +fwd_c_frac_pre3_40: rf1_c_frac_pre3_b(40) <= not( sel_c_imm and rf1_c_k_frac(40) ); +fwd_c_frac_pre3_41: rf1_c_frac_pre3_b(41) <= not( sel_c_imm and rf1_c_k_frac(41) ); +fwd_c_frac_pre3_42: rf1_c_frac_pre3_b(42) <= not( sel_c_imm and rf1_c_k_frac(42) ); +fwd_c_frac_pre3_43: rf1_c_frac_pre3_b(43) <= not( sel_c_imm and rf1_c_k_frac(43) ); +fwd_c_frac_pre3_44: rf1_c_frac_pre3_b(44) <= not( sel_c_imm and rf1_c_k_frac(44) ); +fwd_c_frac_pre3_45: rf1_c_frac_pre3_b(45) <= not( sel_c_imm and rf1_c_k_frac(45) ); +fwd_c_frac_pre3_46: rf1_c_frac_pre3_b(46) <= not( sel_c_imm and rf1_c_k_frac(46) ); +fwd_c_frac_pre3_47: rf1_c_frac_pre3_b(47) <= not( sel_c_imm and rf1_c_k_frac(47) ); +fwd_c_frac_pre3_48: rf1_c_frac_pre3_b(48) <= not( sel_c_imm and rf1_c_k_frac(48) ); +fwd_c_frac_pre3_49: rf1_c_frac_pre3_b(49) <= not( sel_c_imm and rf1_c_k_frac(49) ); +fwd_c_frac_pre3_50: rf1_c_frac_pre3_b(50) <= not( sel_c_imm and rf1_c_k_frac(50) ); +fwd_c_frac_pre3_51: rf1_c_frac_pre3_b(51) <= not( sel_c_imm and rf1_c_k_frac(51) ); +fwd_c_frac_pre3_52: rf1_c_frac_pre3_b(52) <= not( sel_c_imm and rf1_c_k_frac(52) ); + +fwd_c_frac_pre3_24h: rf1_c_frac_pre3_hulp_b <= not( (sel_c_imm and rf1_c_k_frac(24)) or rf1_hulp_sp ); + +rf1_hulp_sp <= f_dcd_rf1_sp and f_dcd_rf1_uc_fc_hulp ; + + +fwd_b_frac_pre3_00: rf1_b_frac_pre3_b( 0) <= not( sel_b_imm and rf1_b_k_frac( 0) ); +fwd_b_frac_pre3_01: rf1_b_frac_pre3_b( 1) <= not( sel_b_imm and rf1_b_k_frac( 1) ); + + + +fwd_a_frac_pre1_00: rf1_a_frac_pre1_b( 0) <= not( (sel_a_res0 and ex6_frac_res_ear( 0) ) or (sel_a_res1 and ex6_frac_res_dly( 0) ) ); +fwd_a_frac_pre1_01: rf1_a_frac_pre1_b( 1) <= not( (sel_a_res0 and ex6_frac_res_ear( 1) ) or (sel_a_res1 and ex6_frac_res_dly( 1) ) ); +fwd_a_frac_pre1_02: rf1_a_frac_pre1_b( 2) <= not( (sel_a_res0 and ex6_frac_res_ear( 2) ) or (sel_a_res1 and ex6_frac_res_dly( 2) ) ); +fwd_a_frac_pre1_03: rf1_a_frac_pre1_b( 3) <= not( (sel_a_res0 and ex6_frac_res_ear( 3) ) or (sel_a_res1 and ex6_frac_res_dly( 3) ) ); +fwd_a_frac_pre1_04: rf1_a_frac_pre1_b( 4) <= not( (sel_a_res0 and ex6_frac_res_ear( 4) ) or (sel_a_res1 and ex6_frac_res_dly( 4) ) ); +fwd_a_frac_pre1_05: rf1_a_frac_pre1_b( 5) <= not( (sel_a_res0 and ex6_frac_res_ear( 5) ) or (sel_a_res1 and ex6_frac_res_dly( 5) ) ); +fwd_a_frac_pre1_06: rf1_a_frac_pre1_b( 6) <= not( (sel_a_res0 and ex6_frac_res_ear( 6) ) or (sel_a_res1 and ex6_frac_res_dly( 6) ) ); +fwd_a_frac_pre1_07: rf1_a_frac_pre1_b( 7) <= not( (sel_a_res0 and ex6_frac_res_ear( 7) ) or (sel_a_res1 and ex6_frac_res_dly( 7) ) ); +fwd_a_frac_pre1_08: rf1_a_frac_pre1_b( 8) <= not( (sel_a_res0 and ex6_frac_res_ear( 8) ) or (sel_a_res1 and ex6_frac_res_dly( 8) ) ); +fwd_a_frac_pre1_09: rf1_a_frac_pre1_b( 9) <= not( (sel_a_res0 and ex6_frac_res_ear( 9) ) or (sel_a_res1 and ex6_frac_res_dly( 9) ) ); +fwd_a_frac_pre1_10: rf1_a_frac_pre1_b(10) <= not( (sel_a_res0 and ex6_frac_res_ear(10) ) or (sel_a_res1 and ex6_frac_res_dly(10) ) ); +fwd_a_frac_pre1_11: rf1_a_frac_pre1_b(11) <= not( (sel_a_res0 and ex6_frac_res_ear(11) ) or (sel_a_res1 and ex6_frac_res_dly(11) ) ); +fwd_a_frac_pre1_12: rf1_a_frac_pre1_b(12) <= not( (sel_a_res0 and ex6_frac_res_ear(12) ) or (sel_a_res1 and ex6_frac_res_dly(12) ) ); +fwd_a_frac_pre1_13: rf1_a_frac_pre1_b(13) <= not( (sel_a_res0 and ex6_frac_res_ear(13) ) or (sel_a_res1 and ex6_frac_res_dly(13) ) ); +fwd_a_frac_pre1_14: rf1_a_frac_pre1_b(14) <= not( (sel_a_res0 and ex6_frac_res_ear(14) ) or (sel_a_res1 and ex6_frac_res_dly(14) ) ); +fwd_a_frac_pre1_15: rf1_a_frac_pre1_b(15) <= not( (sel_a_res0 and ex6_frac_res_ear(15) ) or (sel_a_res1 and ex6_frac_res_dly(15) ) ); +fwd_a_frac_pre1_16: rf1_a_frac_pre1_b(16) <= not( (sel_a_res0 and ex6_frac_res_ear(16) ) or (sel_a_res1 and ex6_frac_res_dly(16) ) ); +fwd_a_frac_pre1_17: rf1_a_frac_pre1_b(17) <= not( (sel_a_res0 and ex6_frac_res_ear(17) ) or (sel_a_res1 and ex6_frac_res_dly(17) ) ); +fwd_a_frac_pre1_18: rf1_a_frac_pre1_b(18) <= not( (sel_a_res0 and ex6_frac_res_ear(18) ) or (sel_a_res1 and ex6_frac_res_dly(18) ) ); +fwd_a_frac_pre1_19: rf1_a_frac_pre1_b(19) <= not( (sel_a_res0 and ex6_frac_res_ear(19) ) or (sel_a_res1 and ex6_frac_res_dly(19) ) ); +fwd_a_frac_pre1_20: rf1_a_frac_pre1_b(20) <= not( (sel_a_res0 and ex6_frac_res_ear(20) ) or (sel_a_res1 and ex6_frac_res_dly(20) ) ); +fwd_a_frac_pre1_21: rf1_a_frac_pre1_b(21) <= not( (sel_a_res0 and ex6_frac_res_ear(21) ) or (sel_a_res1 and ex6_frac_res_dly(21) ) ); +fwd_a_frac_pre1_22: rf1_a_frac_pre1_b(22) <= not( (sel_a_res0 and ex6_frac_res_ear(22) ) or (sel_a_res1 and ex6_frac_res_dly(22) ) ); +fwd_a_frac_pre1_23: rf1_a_frac_pre1_b(23) <= not( (sel_a_res0 and ex6_frac_res_ear(23) ) or (sel_a_res1 and ex6_frac_res_dly(23) ) ); +fwd_a_frac_pre1_24: rf1_a_frac_pre1_b(24) <= not( (sel_a_res0 and ex6_frac_res_ear(24) ) or (sel_a_res1 and ex6_frac_res_dly(24) ) ); +fwd_a_frac_pre1_25: rf1_a_frac_pre1_b(25) <= not( (sel_a_res0 and ex6_frac_res_ear(25) ) or (sel_a_res1 and ex6_frac_res_dly(25) ) ); +fwd_a_frac_pre1_26: rf1_a_frac_pre1_b(26) <= not( (sel_a_res0 and ex6_frac_res_ear(26) ) or (sel_a_res1 and ex6_frac_res_dly(26) ) ); +fwd_a_frac_pre1_27: rf1_a_frac_pre1_b(27) <= not( (sel_a_res0 and ex6_frac_res_ear(27) ) or (sel_a_res1 and ex6_frac_res_dly(27) ) ); +fwd_a_frac_pre1_28: rf1_a_frac_pre1_b(28) <= not( (sel_a_res0 and ex6_frac_res_ear(28) ) or (sel_a_res1 and ex6_frac_res_dly(28) ) ); +fwd_a_frac_pre1_29: rf1_a_frac_pre1_b(29) <= not( (sel_a_res0 and ex6_frac_res_ear(29) ) or (sel_a_res1 and ex6_frac_res_dly(29) ) ); +fwd_a_frac_pre1_30: rf1_a_frac_pre1_b(30) <= not( (sel_a_res0 and ex6_frac_res_ear(30) ) or (sel_a_res1 and ex6_frac_res_dly(30) ) ); +fwd_a_frac_pre1_31: rf1_a_frac_pre1_b(31) <= not( (sel_a_res0 and ex6_frac_res_ear(31) ) or (sel_a_res1 and ex6_frac_res_dly(31) ) ); +fwd_a_frac_pre1_32: rf1_a_frac_pre1_b(32) <= not( (sel_a_res0 and ex6_frac_res_ear(32) ) or (sel_a_res1 and ex6_frac_res_dly(32) ) ); +fwd_a_frac_pre1_33: rf1_a_frac_pre1_b(33) <= not( (sel_a_res0 and ex6_frac_res_ear(33) ) or (sel_a_res1 and ex6_frac_res_dly(33) ) ); +fwd_a_frac_pre1_34: rf1_a_frac_pre1_b(34) <= not( (sel_a_res0 and ex6_frac_res_ear(34) ) or (sel_a_res1 and ex6_frac_res_dly(34) ) ); +fwd_a_frac_pre1_35: rf1_a_frac_pre1_b(35) <= not( (sel_a_res0 and ex6_frac_res_ear(35) ) or (sel_a_res1 and ex6_frac_res_dly(35) ) ); +fwd_a_frac_pre1_36: rf1_a_frac_pre1_b(36) <= not( (sel_a_res0 and ex6_frac_res_ear(36) ) or (sel_a_res1 and ex6_frac_res_dly(36) ) ); +fwd_a_frac_pre1_37: rf1_a_frac_pre1_b(37) <= not( (sel_a_res0 and ex6_frac_res_ear(37) ) or (sel_a_res1 and ex6_frac_res_dly(37) ) ); +fwd_a_frac_pre1_38: rf1_a_frac_pre1_b(38) <= not( (sel_a_res0 and ex6_frac_res_ear(38) ) or (sel_a_res1 and ex6_frac_res_dly(38) ) ); +fwd_a_frac_pre1_39: rf1_a_frac_pre1_b(39) <= not( (sel_a_res0 and ex6_frac_res_ear(39) ) or (sel_a_res1 and ex6_frac_res_dly(39) ) ); +fwd_a_frac_pre1_40: rf1_a_frac_pre1_b(40) <= not( (sel_a_res0 and ex6_frac_res_ear(40) ) or (sel_a_res1 and ex6_frac_res_dly(40) ) ); +fwd_a_frac_pre1_41: rf1_a_frac_pre1_b(41) <= not( (sel_a_res0 and ex6_frac_res_ear(41) ) or (sel_a_res1 and ex6_frac_res_dly(41) ) ); +fwd_a_frac_pre1_42: rf1_a_frac_pre1_b(42) <= not( (sel_a_res0 and ex6_frac_res_ear(42) ) or (sel_a_res1 and ex6_frac_res_dly(42) ) ); +fwd_a_frac_pre1_43: rf1_a_frac_pre1_b(43) <= not( (sel_a_res0 and ex6_frac_res_ear(43) ) or (sel_a_res1 and ex6_frac_res_dly(43) ) ); +fwd_a_frac_pre1_44: rf1_a_frac_pre1_b(44) <= not( (sel_a_res0 and ex6_frac_res_ear(44) ) or (sel_a_res1 and ex6_frac_res_dly(44) ) ); +fwd_a_frac_pre1_45: rf1_a_frac_pre1_b(45) <= not( (sel_a_res0 and ex6_frac_res_ear(45) ) or (sel_a_res1 and ex6_frac_res_dly(45) ) ); +fwd_a_frac_pre1_46: rf1_a_frac_pre1_b(46) <= not( (sel_a_res0 and ex6_frac_res_ear(46) ) or (sel_a_res1 and ex6_frac_res_dly(46) ) ); +fwd_a_frac_pre1_47: rf1_a_frac_pre1_b(47) <= not( (sel_a_res0 and ex6_frac_res_ear(47) ) or (sel_a_res1 and ex6_frac_res_dly(47) ) ); +fwd_a_frac_pre1_48: rf1_a_frac_pre1_b(48) <= not( (sel_a_res0 and ex6_frac_res_ear(48) ) or (sel_a_res1 and ex6_frac_res_dly(48) ) ); +fwd_a_frac_pre1_49: rf1_a_frac_pre1_b(49) <= not( (sel_a_res0 and ex6_frac_res_ear(49) ) or (sel_a_res1 and ex6_frac_res_dly(49) ) ); +fwd_a_frac_pre1_50: rf1_a_frac_pre1_b(50) <= not( (sel_a_res0 and ex6_frac_res_ear(50) ) or (sel_a_res1 and ex6_frac_res_dly(50) ) ); +fwd_a_frac_pre1_51: rf1_a_frac_pre1_b(51) <= not( (sel_a_res0 and ex6_frac_res_ear(51) ) or (sel_a_res1 and ex6_frac_res_dly(51) ) ); +fwd_a_frac_pre1_52: rf1_a_frac_pre1_b(52) <= not( (sel_a_res0 and ex6_frac_res_ear(52) ) or (sel_a_res1 and ex6_frac_res_dly(52) ) ); + + +fwd_c_frac_pre1_00: rf1_c_frac_pre1_b( 0) <= not( (sel_c_res0 and ex6_frac_res_ear( 0) ) or (sel_c_res1 and ex6_frac_res_dly( 0) ) ); +fwd_c_frac_pre1_01: rf1_c_frac_pre1_b( 1) <= not( (sel_c_res0 and ex6_frac_res_ear( 1) ) or (sel_c_res1 and ex6_frac_res_dly( 1) ) ); +fwd_c_frac_pre1_02: rf1_c_frac_pre1_b( 2) <= not( (sel_c_res0 and ex6_frac_res_ear( 2) ) or (sel_c_res1 and ex6_frac_res_dly( 2) ) ); +fwd_c_frac_pre1_03: rf1_c_frac_pre1_b( 3) <= not( (sel_c_res0 and ex6_frac_res_ear( 3) ) or (sel_c_res1 and ex6_frac_res_dly( 3) ) ); +fwd_c_frac_pre1_04: rf1_c_frac_pre1_b( 4) <= not( (sel_c_res0 and ex6_frac_res_ear( 4) ) or (sel_c_res1 and ex6_frac_res_dly( 4) ) ); +fwd_c_frac_pre1_05: rf1_c_frac_pre1_b( 5) <= not( (sel_c_res0 and ex6_frac_res_ear( 5) ) or (sel_c_res1 and ex6_frac_res_dly( 5) ) ); +fwd_c_frac_pre1_06: rf1_c_frac_pre1_b( 6) <= not( (sel_c_res0 and ex6_frac_res_ear( 6) ) or (sel_c_res1 and ex6_frac_res_dly( 6) ) ); +fwd_c_frac_pre1_07: rf1_c_frac_pre1_b( 7) <= not( (sel_c_res0 and ex6_frac_res_ear( 7) ) or (sel_c_res1 and ex6_frac_res_dly( 7) ) ); +fwd_c_frac_pre1_08: rf1_c_frac_pre1_b( 8) <= not( (sel_c_res0 and ex6_frac_res_ear( 8) ) or (sel_c_res1 and ex6_frac_res_dly( 8) ) ); +fwd_c_frac_pre1_09: rf1_c_frac_pre1_b( 9) <= not( (sel_c_res0 and ex6_frac_res_ear( 9) ) or (sel_c_res1 and ex6_frac_res_dly( 9) ) ); +fwd_c_frac_pre1_10: rf1_c_frac_pre1_b(10) <= not( (sel_c_res0 and ex6_frac_res_ear(10) ) or (sel_c_res1 and ex6_frac_res_dly(10) ) ); +fwd_c_frac_pre1_11: rf1_c_frac_pre1_b(11) <= not( (sel_c_res0 and ex6_frac_res_ear(11) ) or (sel_c_res1 and ex6_frac_res_dly(11) ) ); +fwd_c_frac_pre1_12: rf1_c_frac_pre1_b(12) <= not( (sel_c_res0 and ex6_frac_res_ear(12) ) or (sel_c_res1 and ex6_frac_res_dly(12) ) ); +fwd_c_frac_pre1_13: rf1_c_frac_pre1_b(13) <= not( (sel_c_res0 and ex6_frac_res_ear(13) ) or (sel_c_res1 and ex6_frac_res_dly(13) ) ); +fwd_c_frac_pre1_14: rf1_c_frac_pre1_b(14) <= not( (sel_c_res0 and ex6_frac_res_ear(14) ) or (sel_c_res1 and ex6_frac_res_dly(14) ) ); +fwd_c_frac_pre1_15: rf1_c_frac_pre1_b(15) <= not( (sel_c_res0 and ex6_frac_res_ear(15) ) or (sel_c_res1 and ex6_frac_res_dly(15) ) ); +fwd_c_frac_pre1_16: rf1_c_frac_pre1_b(16) <= not( (sel_c_res0 and ex6_frac_res_ear(16) ) or (sel_c_res1 and ex6_frac_res_dly(16) ) ); +fwd_c_frac_pre1_17: rf1_c_frac_pre1_b(17) <= not( (sel_c_res0 and ex6_frac_res_ear(17) ) or (sel_c_res1 and ex6_frac_res_dly(17) ) ); +fwd_c_frac_pre1_18: rf1_c_frac_pre1_b(18) <= not( (sel_c_res0 and ex6_frac_res_ear(18) ) or (sel_c_res1 and ex6_frac_res_dly(18) ) ); +fwd_c_frac_pre1_19: rf1_c_frac_pre1_b(19) <= not( (sel_c_res0 and ex6_frac_res_ear(19) ) or (sel_c_res1 and ex6_frac_res_dly(19) ) ); +fwd_c_frac_pre1_20: rf1_c_frac_pre1_b(20) <= not( (sel_c_res0 and ex6_frac_res_ear(20) ) or (sel_c_res1 and ex6_frac_res_dly(20) ) ); +fwd_c_frac_pre1_21: rf1_c_frac_pre1_b(21) <= not( (sel_c_res0 and ex6_frac_res_ear(21) ) or (sel_c_res1 and ex6_frac_res_dly(21) ) ); +fwd_c_frac_pre1_22: rf1_c_frac_pre1_b(22) <= not( (sel_c_res0 and ex6_frac_res_ear(22) ) or (sel_c_res1 and ex6_frac_res_dly(22) ) ); +fwd_c_frac_pre1_23: rf1_c_frac_pre1_b(23) <= not( (sel_c_res0 and ex6_frac_res_ear(23) ) or (sel_c_res1 and ex6_frac_res_dly(23) ) ); +fwd_c_frac_pre1_24: rf1_c_frac_pre1_b(24) <= not( (sel_c_res0 and ex6_frac_res_ear(24) ) or (sel_c_res1 and ex6_frac_res_dly(24) ) ); +fwd_c_frac_pre1_25: rf1_c_frac_pre1_b(25) <= not( (sel_c_res0 and ex6_frac_res_ear(25) ) or (sel_c_res1 and ex6_frac_res_dly(25) ) ); +fwd_c_frac_pre1_26: rf1_c_frac_pre1_b(26) <= not( (sel_c_res0 and ex6_frac_res_ear(26) ) or (sel_c_res1 and ex6_frac_res_dly(26) ) ); +fwd_c_frac_pre1_27: rf1_c_frac_pre1_b(27) <= not( (sel_c_res0 and ex6_frac_res_ear(27) ) or (sel_c_res1 and ex6_frac_res_dly(27) ) ); +fwd_c_frac_pre1_28: rf1_c_frac_pre1_b(28) <= not( (sel_c_res0 and ex6_frac_res_ear(28) ) or (sel_c_res1 and ex6_frac_res_dly(28) ) ); +fwd_c_frac_pre1_29: rf1_c_frac_pre1_b(29) <= not( (sel_c_res0 and ex6_frac_res_ear(29) ) or (sel_c_res1 and ex6_frac_res_dly(29) ) ); +fwd_c_frac_pre1_30: rf1_c_frac_pre1_b(30) <= not( (sel_c_res0 and ex6_frac_res_ear(30) ) or (sel_c_res1 and ex6_frac_res_dly(30) ) ); +fwd_c_frac_pre1_31: rf1_c_frac_pre1_b(31) <= not( (sel_c_res0 and ex6_frac_res_ear(31) ) or (sel_c_res1 and ex6_frac_res_dly(31) ) ); +fwd_c_frac_pre1_32: rf1_c_frac_pre1_b(32) <= not( (sel_c_res0 and ex6_frac_res_ear(32) ) or (sel_c_res1 and ex6_frac_res_dly(32) ) ); +fwd_c_frac_pre1_33: rf1_c_frac_pre1_b(33) <= not( (sel_c_res0 and ex6_frac_res_ear(33) ) or (sel_c_res1 and ex6_frac_res_dly(33) ) ); +fwd_c_frac_pre1_34: rf1_c_frac_pre1_b(34) <= not( (sel_c_res0 and ex6_frac_res_ear(34) ) or (sel_c_res1 and ex6_frac_res_dly(34) ) ); +fwd_c_frac_pre1_35: rf1_c_frac_pre1_b(35) <= not( (sel_c_res0 and ex6_frac_res_ear(35) ) or (sel_c_res1 and ex6_frac_res_dly(35) ) ); +fwd_c_frac_pre1_36: rf1_c_frac_pre1_b(36) <= not( (sel_c_res0 and ex6_frac_res_ear(36) ) or (sel_c_res1 and ex6_frac_res_dly(36) ) ); +fwd_c_frac_pre1_37: rf1_c_frac_pre1_b(37) <= not( (sel_c_res0 and ex6_frac_res_ear(37) ) or (sel_c_res1 and ex6_frac_res_dly(37) ) ); +fwd_c_frac_pre1_38: rf1_c_frac_pre1_b(38) <= not( (sel_c_res0 and ex6_frac_res_ear(38) ) or (sel_c_res1 and ex6_frac_res_dly(38) ) ); +fwd_c_frac_pre1_39: rf1_c_frac_pre1_b(39) <= not( (sel_c_res0 and ex6_frac_res_ear(39) ) or (sel_c_res1 and ex6_frac_res_dly(39) ) ); +fwd_c_frac_pre1_40: rf1_c_frac_pre1_b(40) <= not( (sel_c_res0 and ex6_frac_res_ear(40) ) or (sel_c_res1 and ex6_frac_res_dly(40) ) ); +fwd_c_frac_pre1_41: rf1_c_frac_pre1_b(41) <= not( (sel_c_res0 and ex6_frac_res_ear(41) ) or (sel_c_res1 and ex6_frac_res_dly(41) ) ); +fwd_c_frac_pre1_42: rf1_c_frac_pre1_b(42) <= not( (sel_c_res0 and ex6_frac_res_ear(42) ) or (sel_c_res1 and ex6_frac_res_dly(42) ) ); +fwd_c_frac_pre1_43: rf1_c_frac_pre1_b(43) <= not( (sel_c_res0 and ex6_frac_res_ear(43) ) or (sel_c_res1 and ex6_frac_res_dly(43) ) ); +fwd_c_frac_pre1_44: rf1_c_frac_pre1_b(44) <= not( (sel_c_res0 and ex6_frac_res_ear(44) ) or (sel_c_res1 and ex6_frac_res_dly(44) ) ); +fwd_c_frac_pre1_45: rf1_c_frac_pre1_b(45) <= not( (sel_c_res0 and ex6_frac_res_ear(45) ) or (sel_c_res1 and ex6_frac_res_dly(45) ) ); +fwd_c_frac_pre1_46: rf1_c_frac_pre1_b(46) <= not( (sel_c_res0 and ex6_frac_res_ear(46) ) or (sel_c_res1 and ex6_frac_res_dly(46) ) ); +fwd_c_frac_pre1_47: rf1_c_frac_pre1_b(47) <= not( (sel_c_res0 and ex6_frac_res_ear(47) ) or (sel_c_res1 and ex6_frac_res_dly(47) ) ); +fwd_c_frac_pre1_48: rf1_c_frac_pre1_b(48) <= not( (sel_c_res0 and ex6_frac_res_ear(48) ) or (sel_c_res1 and ex6_frac_res_dly(48) ) ); +fwd_c_frac_pre1_49: rf1_c_frac_pre1_b(49) <= not( (sel_c_res0 and ex6_frac_res_ear(49) ) or (sel_c_res1 and ex6_frac_res_dly(49) ) ); +fwd_c_frac_pre1_50: rf1_c_frac_pre1_b(50) <= not( (sel_c_res0 and ex6_frac_res_ear(50) ) or (sel_c_res1 and ex6_frac_res_dly(50) ) ); +fwd_c_frac_pre1_51: rf1_c_frac_pre1_b(51) <= not( (sel_c_res0 and ex6_frac_res_ear(51) ) or (sel_c_res1 and ex6_frac_res_dly(51) ) ); +fwd_c_frac_pre1_52: rf1_c_frac_pre1_b(52) <= not( (sel_c_res0 and ex6_frac_res_ear(52) ) or (sel_c_res1 and ex6_frac_res_dly(52) ) ); + + +fwd_b_frac_pre1_00: rf1_b_frac_pre1_b( 0) <= not( (sel_b_res0 and ex6_frac_res_ear( 0) ) or (sel_b_res1 and ex6_frac_res_dly( 0) ) ); +fwd_b_frac_pre1_01: rf1_b_frac_pre1_b( 1) <= not( (sel_b_res0 and ex6_frac_res_ear( 1) ) or (sel_b_res1 and ex6_frac_res_dly( 1) ) ); +fwd_b_frac_pre1_02: rf1_b_frac_pre1_b( 2) <= not( (sel_b_res0 and ex6_frac_res_ear( 2) ) or (sel_b_res1 and ex6_frac_res_dly( 2) ) ); +fwd_b_frac_pre1_03: rf1_b_frac_pre1_b( 3) <= not( (sel_b_res0 and ex6_frac_res_ear( 3) ) or (sel_b_res1 and ex6_frac_res_dly( 3) ) ); +fwd_b_frac_pre1_04: rf1_b_frac_pre1_b( 4) <= not( (sel_b_res0 and ex6_frac_res_ear( 4) ) or (sel_b_res1 and ex6_frac_res_dly( 4) ) ); +fwd_b_frac_pre1_05: rf1_b_frac_pre1_b( 5) <= not( (sel_b_res0 and ex6_frac_res_ear( 5) ) or (sel_b_res1 and ex6_frac_res_dly( 5) ) ); +fwd_b_frac_pre1_06: rf1_b_frac_pre1_b( 6) <= not( (sel_b_res0 and ex6_frac_res_ear( 6) ) or (sel_b_res1 and ex6_frac_res_dly( 6) ) ); +fwd_b_frac_pre1_07: rf1_b_frac_pre1_b( 7) <= not( (sel_b_res0 and ex6_frac_res_ear( 7) ) or (sel_b_res1 and ex6_frac_res_dly( 7) ) ); +fwd_b_frac_pre1_08: rf1_b_frac_pre1_b( 8) <= not( (sel_b_res0 and ex6_frac_res_ear( 8) ) or (sel_b_res1 and ex6_frac_res_dly( 8) ) ); +fwd_b_frac_pre1_09: rf1_b_frac_pre1_b( 9) <= not( (sel_b_res0 and ex6_frac_res_ear( 9) ) or (sel_b_res1 and ex6_frac_res_dly( 9) ) ); +fwd_b_frac_pre1_10: rf1_b_frac_pre1_b(10) <= not( (sel_b_res0 and ex6_frac_res_ear(10) ) or (sel_b_res1 and ex6_frac_res_dly(10) ) ); +fwd_b_frac_pre1_11: rf1_b_frac_pre1_b(11) <= not( (sel_b_res0 and ex6_frac_res_ear(11) ) or (sel_b_res1 and ex6_frac_res_dly(11) ) ); +fwd_b_frac_pre1_12: rf1_b_frac_pre1_b(12) <= not( (sel_b_res0 and ex6_frac_res_ear(12) ) or (sel_b_res1 and ex6_frac_res_dly(12) ) ); +fwd_b_frac_pre1_13: rf1_b_frac_pre1_b(13) <= not( (sel_b_res0 and ex6_frac_res_ear(13) ) or (sel_b_res1 and ex6_frac_res_dly(13) ) ); +fwd_b_frac_pre1_14: rf1_b_frac_pre1_b(14) <= not( (sel_b_res0 and ex6_frac_res_ear(14) ) or (sel_b_res1 and ex6_frac_res_dly(14) ) ); +fwd_b_frac_pre1_15: rf1_b_frac_pre1_b(15) <= not( (sel_b_res0 and ex6_frac_res_ear(15) ) or (sel_b_res1 and ex6_frac_res_dly(15) ) ); +fwd_b_frac_pre1_16: rf1_b_frac_pre1_b(16) <= not( (sel_b_res0 and ex6_frac_res_ear(16) ) or (sel_b_res1 and ex6_frac_res_dly(16) ) ); +fwd_b_frac_pre1_17: rf1_b_frac_pre1_b(17) <= not( (sel_b_res0 and ex6_frac_res_ear(17) ) or (sel_b_res1 and ex6_frac_res_dly(17) ) ); +fwd_b_frac_pre1_18: rf1_b_frac_pre1_b(18) <= not( (sel_b_res0 and ex6_frac_res_ear(18) ) or (sel_b_res1 and ex6_frac_res_dly(18) ) ); +fwd_b_frac_pre1_19: rf1_b_frac_pre1_b(19) <= not( (sel_b_res0 and ex6_frac_res_ear(19) ) or (sel_b_res1 and ex6_frac_res_dly(19) ) ); +fwd_b_frac_pre1_20: rf1_b_frac_pre1_b(20) <= not( (sel_b_res0 and ex6_frac_res_ear(20) ) or (sel_b_res1 and ex6_frac_res_dly(20) ) ); +fwd_b_frac_pre1_21: rf1_b_frac_pre1_b(21) <= not( (sel_b_res0 and ex6_frac_res_ear(21) ) or (sel_b_res1 and ex6_frac_res_dly(21) ) ); +fwd_b_frac_pre1_22: rf1_b_frac_pre1_b(22) <= not( (sel_b_res0 and ex6_frac_res_ear(22) ) or (sel_b_res1 and ex6_frac_res_dly(22) ) ); +fwd_b_frac_pre1_23: rf1_b_frac_pre1_b(23) <= not( (sel_b_res0 and ex6_frac_res_ear(23) ) or (sel_b_res1 and ex6_frac_res_dly(23) ) ); +fwd_b_frac_pre1_24: rf1_b_frac_pre1_b(24) <= not( (sel_b_res0 and ex6_frac_res_ear(24) ) or (sel_b_res1 and ex6_frac_res_dly(24) ) ); +fwd_b_frac_pre1_25: rf1_b_frac_pre1_b(25) <= not( (sel_b_res0 and ex6_frac_res_ear(25) ) or (sel_b_res1 and ex6_frac_res_dly(25) ) ); +fwd_b_frac_pre1_26: rf1_b_frac_pre1_b(26) <= not( (sel_b_res0 and ex6_frac_res_ear(26) ) or (sel_b_res1 and ex6_frac_res_dly(26) ) ); +fwd_b_frac_pre1_27: rf1_b_frac_pre1_b(27) <= not( (sel_b_res0 and ex6_frac_res_ear(27) ) or (sel_b_res1 and ex6_frac_res_dly(27) ) ); +fwd_b_frac_pre1_28: rf1_b_frac_pre1_b(28) <= not( (sel_b_res0 and ex6_frac_res_ear(28) ) or (sel_b_res1 and ex6_frac_res_dly(28) ) ); +fwd_b_frac_pre1_29: rf1_b_frac_pre1_b(29) <= not( (sel_b_res0 and ex6_frac_res_ear(29) ) or (sel_b_res1 and ex6_frac_res_dly(29) ) ); +fwd_b_frac_pre1_30: rf1_b_frac_pre1_b(30) <= not( (sel_b_res0 and ex6_frac_res_ear(30) ) or (sel_b_res1 and ex6_frac_res_dly(30) ) ); +fwd_b_frac_pre1_31: rf1_b_frac_pre1_b(31) <= not( (sel_b_res0 and ex6_frac_res_ear(31) ) or (sel_b_res1 and ex6_frac_res_dly(31) ) ); +fwd_b_frac_pre1_32: rf1_b_frac_pre1_b(32) <= not( (sel_b_res0 and ex6_frac_res_ear(32) ) or (sel_b_res1 and ex6_frac_res_dly(32) ) ); +fwd_b_frac_pre1_33: rf1_b_frac_pre1_b(33) <= not( (sel_b_res0 and ex6_frac_res_ear(33) ) or (sel_b_res1 and ex6_frac_res_dly(33) ) ); +fwd_b_frac_pre1_34: rf1_b_frac_pre1_b(34) <= not( (sel_b_res0 and ex6_frac_res_ear(34) ) or (sel_b_res1 and ex6_frac_res_dly(34) ) ); +fwd_b_frac_pre1_35: rf1_b_frac_pre1_b(35) <= not( (sel_b_res0 and ex6_frac_res_ear(35) ) or (sel_b_res1 and ex6_frac_res_dly(35) ) ); +fwd_b_frac_pre1_36: rf1_b_frac_pre1_b(36) <= not( (sel_b_res0 and ex6_frac_res_ear(36) ) or (sel_b_res1 and ex6_frac_res_dly(36) ) ); +fwd_b_frac_pre1_37: rf1_b_frac_pre1_b(37) <= not( (sel_b_res0 and ex6_frac_res_ear(37) ) or (sel_b_res1 and ex6_frac_res_dly(37) ) ); +fwd_b_frac_pre1_38: rf1_b_frac_pre1_b(38) <= not( (sel_b_res0 and ex6_frac_res_ear(38) ) or (sel_b_res1 and ex6_frac_res_dly(38) ) ); +fwd_b_frac_pre1_39: rf1_b_frac_pre1_b(39) <= not( (sel_b_res0 and ex6_frac_res_ear(39) ) or (sel_b_res1 and ex6_frac_res_dly(39) ) ); +fwd_b_frac_pre1_40: rf1_b_frac_pre1_b(40) <= not( (sel_b_res0 and ex6_frac_res_ear(40) ) or (sel_b_res1 and ex6_frac_res_dly(40) ) ); +fwd_b_frac_pre1_41: rf1_b_frac_pre1_b(41) <= not( (sel_b_res0 and ex6_frac_res_ear(41) ) or (sel_b_res1 and ex6_frac_res_dly(41) ) ); +fwd_b_frac_pre1_42: rf1_b_frac_pre1_b(42) <= not( (sel_b_res0 and ex6_frac_res_ear(42) ) or (sel_b_res1 and ex6_frac_res_dly(42) ) ); +fwd_b_frac_pre1_43: rf1_b_frac_pre1_b(43) <= not( (sel_b_res0 and ex6_frac_res_ear(43) ) or (sel_b_res1 and ex6_frac_res_dly(43) ) ); +fwd_b_frac_pre1_44: rf1_b_frac_pre1_b(44) <= not( (sel_b_res0 and ex6_frac_res_ear(44) ) or (sel_b_res1 and ex6_frac_res_dly(44) ) ); +fwd_b_frac_pre1_45: rf1_b_frac_pre1_b(45) <= not( (sel_b_res0 and ex6_frac_res_ear(45) ) or (sel_b_res1 and ex6_frac_res_dly(45) ) ); +fwd_b_frac_pre1_46: rf1_b_frac_pre1_b(46) <= not( (sel_b_res0 and ex6_frac_res_ear(46) ) or (sel_b_res1 and ex6_frac_res_dly(46) ) ); +fwd_b_frac_pre1_47: rf1_b_frac_pre1_b(47) <= not( (sel_b_res0 and ex6_frac_res_ear(47) ) or (sel_b_res1 and ex6_frac_res_dly(47) ) ); +fwd_b_frac_pre1_48: rf1_b_frac_pre1_b(48) <= not( (sel_b_res0 and ex6_frac_res_ear(48) ) or (sel_b_res1 and ex6_frac_res_dly(48) ) ); +fwd_b_frac_pre1_49: rf1_b_frac_pre1_b(49) <= not( (sel_b_res0 and ex6_frac_res_ear(49) ) or (sel_b_res1 and ex6_frac_res_dly(49) ) ); +fwd_b_frac_pre1_50: rf1_b_frac_pre1_b(50) <= not( (sel_b_res0 and ex6_frac_res_ear(50) ) or (sel_b_res1 and ex6_frac_res_dly(50) ) ); +fwd_b_frac_pre1_51: rf1_b_frac_pre1_b(51) <= not( (sel_b_res0 and ex6_frac_res_ear(51) ) or (sel_b_res1 and ex6_frac_res_dly(51) ) ); +fwd_b_frac_pre1_52: rf1_b_frac_pre1_b(52) <= not( (sel_b_res0 and ex6_frac_res_ear(52) ) or (sel_b_res1 and ex6_frac_res_dly(52) ) ); + + + + + +fwd_a_frac_pre2_00: rf1_a_frac_pre2_b( 0) <= not( (sel_a_load0 and ex6_frac_lod_ear( 0) ) or (sel_a_load1 and ex6_frac_lod_dly( 0) ) ); +fwd_a_frac_pre2_01: rf1_a_frac_pre2_b( 1) <= not( (sel_a_load0 and ex6_frac_lod_ear( 1) ) or (sel_a_load1 and ex6_frac_lod_dly( 1) ) ); +fwd_a_frac_pre2_02: rf1_a_frac_pre2_b( 2) <= not( (sel_a_load0 and ex6_frac_lod_ear( 2) ) or (sel_a_load1 and ex6_frac_lod_dly( 2) ) ); +fwd_a_frac_pre2_03: rf1_a_frac_pre2_b( 3) <= not( (sel_a_load0 and ex6_frac_lod_ear( 3) ) or (sel_a_load1 and ex6_frac_lod_dly( 3) ) ); +fwd_a_frac_pre2_04: rf1_a_frac_pre2_b( 4) <= not( (sel_a_load0 and ex6_frac_lod_ear( 4) ) or (sel_a_load1 and ex6_frac_lod_dly( 4) ) ); +fwd_a_frac_pre2_05: rf1_a_frac_pre2_b( 5) <= not( (sel_a_load0 and ex6_frac_lod_ear( 5) ) or (sel_a_load1 and ex6_frac_lod_dly( 5) ) ); +fwd_a_frac_pre2_06: rf1_a_frac_pre2_b( 6) <= not( (sel_a_load0 and ex6_frac_lod_ear( 6) ) or (sel_a_load1 and ex6_frac_lod_dly( 6) ) ); +fwd_a_frac_pre2_07: rf1_a_frac_pre2_b( 7) <= not( (sel_a_load0 and ex6_frac_lod_ear( 7) ) or (sel_a_load1 and ex6_frac_lod_dly( 7) ) ); +fwd_a_frac_pre2_08: rf1_a_frac_pre2_b( 8) <= not( (sel_a_load0 and ex6_frac_lod_ear( 8) ) or (sel_a_load1 and ex6_frac_lod_dly( 8) ) ); +fwd_a_frac_pre2_09: rf1_a_frac_pre2_b( 9) <= not( (sel_a_load0 and ex6_frac_lod_ear( 9) ) or (sel_a_load1 and ex6_frac_lod_dly( 9) ) ); +fwd_a_frac_pre2_10: rf1_a_frac_pre2_b(10) <= not( (sel_a_load0 and ex6_frac_lod_ear(10) ) or (sel_a_load1 and ex6_frac_lod_dly(10) ) ); +fwd_a_frac_pre2_11: rf1_a_frac_pre2_b(11) <= not( (sel_a_load0 and ex6_frac_lod_ear(11) ) or (sel_a_load1 and ex6_frac_lod_dly(11) ) ); +fwd_a_frac_pre2_12: rf1_a_frac_pre2_b(12) <= not( (sel_a_load0 and ex6_frac_lod_ear(12) ) or (sel_a_load1 and ex6_frac_lod_dly(12) ) ); +fwd_a_frac_pre2_13: rf1_a_frac_pre2_b(13) <= not( (sel_a_load0 and ex6_frac_lod_ear(13) ) or (sel_a_load1 and ex6_frac_lod_dly(13) ) ); +fwd_a_frac_pre2_14: rf1_a_frac_pre2_b(14) <= not( (sel_a_load0 and ex6_frac_lod_ear(14) ) or (sel_a_load1 and ex6_frac_lod_dly(14) ) ); +fwd_a_frac_pre2_15: rf1_a_frac_pre2_b(15) <= not( (sel_a_load0 and ex6_frac_lod_ear(15) ) or (sel_a_load1 and ex6_frac_lod_dly(15) ) ); +fwd_a_frac_pre2_16: rf1_a_frac_pre2_b(16) <= not( (sel_a_load0 and ex6_frac_lod_ear(16) ) or (sel_a_load1 and ex6_frac_lod_dly(16) ) ); +fwd_a_frac_pre2_17: rf1_a_frac_pre2_b(17) <= not( (sel_a_load0 and ex6_frac_lod_ear(17) ) or (sel_a_load1 and ex6_frac_lod_dly(17) ) ); +fwd_a_frac_pre2_18: rf1_a_frac_pre2_b(18) <= not( (sel_a_load0 and ex6_frac_lod_ear(18) ) or (sel_a_load1 and ex6_frac_lod_dly(18) ) ); +fwd_a_frac_pre2_19: rf1_a_frac_pre2_b(19) <= not( (sel_a_load0 and ex6_frac_lod_ear(19) ) or (sel_a_load1 and ex6_frac_lod_dly(19) ) ); +fwd_a_frac_pre2_20: rf1_a_frac_pre2_b(20) <= not( (sel_a_load0 and ex6_frac_lod_ear(20) ) or (sel_a_load1 and ex6_frac_lod_dly(20) ) ); +fwd_a_frac_pre2_21: rf1_a_frac_pre2_b(21) <= not( (sel_a_load0 and ex6_frac_lod_ear(21) ) or (sel_a_load1 and ex6_frac_lod_dly(21) ) ); +fwd_a_frac_pre2_22: rf1_a_frac_pre2_b(22) <= not( (sel_a_load0 and ex6_frac_lod_ear(22) ) or (sel_a_load1 and ex6_frac_lod_dly(22) ) ); +fwd_a_frac_pre2_23: rf1_a_frac_pre2_b(23) <= not( (sel_a_load0 and ex6_frac_lod_ear(23) ) or (sel_a_load1 and ex6_frac_lod_dly(23) ) ); +fwd_a_frac_pre2_24: rf1_a_frac_pre2_b(24) <= not( (sel_a_load0 and ex6_frac_lod_ear(24) ) or (sel_a_load1 and ex6_frac_lod_dly(24) ) ); +fwd_a_frac_pre2_25: rf1_a_frac_pre2_b(25) <= not( (sel_a_load0 and ex6_frac_lod_ear(25) ) or (sel_a_load1 and ex6_frac_lod_dly(25) ) ); +fwd_a_frac_pre2_26: rf1_a_frac_pre2_b(26) <= not( (sel_a_load0 and ex6_frac_lod_ear(26) ) or (sel_a_load1 and ex6_frac_lod_dly(26) ) ); +fwd_a_frac_pre2_27: rf1_a_frac_pre2_b(27) <= not( (sel_a_load0 and ex6_frac_lod_ear(27) ) or (sel_a_load1 and ex6_frac_lod_dly(27) ) ); +fwd_a_frac_pre2_28: rf1_a_frac_pre2_b(28) <= not( (sel_a_load0 and ex6_frac_lod_ear(28) ) or (sel_a_load1 and ex6_frac_lod_dly(28) ) ); +fwd_a_frac_pre2_29: rf1_a_frac_pre2_b(29) <= not( (sel_a_load0 and ex6_frac_lod_ear(29) ) or (sel_a_load1 and ex6_frac_lod_dly(29) ) ); +fwd_a_frac_pre2_30: rf1_a_frac_pre2_b(30) <= not( (sel_a_load0 and ex6_frac_lod_ear(30) ) or (sel_a_load1 and ex6_frac_lod_dly(30) ) ); +fwd_a_frac_pre2_31: rf1_a_frac_pre2_b(31) <= not( (sel_a_load0 and ex6_frac_lod_ear(31) ) or (sel_a_load1 and ex6_frac_lod_dly(31) ) ); +fwd_a_frac_pre2_32: rf1_a_frac_pre2_b(32) <= not( (sel_a_load0 and ex6_frac_lod_ear(32) ) or (sel_a_load1 and ex6_frac_lod_dly(32) ) ); +fwd_a_frac_pre2_33: rf1_a_frac_pre2_b(33) <= not( (sel_a_load0 and ex6_frac_lod_ear(33) ) or (sel_a_load1 and ex6_frac_lod_dly(33) ) ); +fwd_a_frac_pre2_34: rf1_a_frac_pre2_b(34) <= not( (sel_a_load0 and ex6_frac_lod_ear(34) ) or (sel_a_load1 and ex6_frac_lod_dly(34) ) ); +fwd_a_frac_pre2_35: rf1_a_frac_pre2_b(35) <= not( (sel_a_load0 and ex6_frac_lod_ear(35) ) or (sel_a_load1 and ex6_frac_lod_dly(35) ) ); +fwd_a_frac_pre2_36: rf1_a_frac_pre2_b(36) <= not( (sel_a_load0 and ex6_frac_lod_ear(36) ) or (sel_a_load1 and ex6_frac_lod_dly(36) ) ); +fwd_a_frac_pre2_37: rf1_a_frac_pre2_b(37) <= not( (sel_a_load0 and ex6_frac_lod_ear(37) ) or (sel_a_load1 and ex6_frac_lod_dly(37) ) ); +fwd_a_frac_pre2_38: rf1_a_frac_pre2_b(38) <= not( (sel_a_load0 and ex6_frac_lod_ear(38) ) or (sel_a_load1 and ex6_frac_lod_dly(38) ) ); +fwd_a_frac_pre2_39: rf1_a_frac_pre2_b(39) <= not( (sel_a_load0 and ex6_frac_lod_ear(39) ) or (sel_a_load1 and ex6_frac_lod_dly(39) ) ); +fwd_a_frac_pre2_40: rf1_a_frac_pre2_b(40) <= not( (sel_a_load0 and ex6_frac_lod_ear(40) ) or (sel_a_load1 and ex6_frac_lod_dly(40) ) ); +fwd_a_frac_pre2_41: rf1_a_frac_pre2_b(41) <= not( (sel_a_load0 and ex6_frac_lod_ear(41) ) or (sel_a_load1 and ex6_frac_lod_dly(41) ) ); +fwd_a_frac_pre2_42: rf1_a_frac_pre2_b(42) <= not( (sel_a_load0 and ex6_frac_lod_ear(42) ) or (sel_a_load1 and ex6_frac_lod_dly(42) ) ); +fwd_a_frac_pre2_43: rf1_a_frac_pre2_b(43) <= not( (sel_a_load0 and ex6_frac_lod_ear(43) ) or (sel_a_load1 and ex6_frac_lod_dly(43) ) ); +fwd_a_frac_pre2_44: rf1_a_frac_pre2_b(44) <= not( (sel_a_load0 and ex6_frac_lod_ear(44) ) or (sel_a_load1 and ex6_frac_lod_dly(44) ) ); +fwd_a_frac_pre2_45: rf1_a_frac_pre2_b(45) <= not( (sel_a_load0 and ex6_frac_lod_ear(45) ) or (sel_a_load1 and ex6_frac_lod_dly(45) ) ); +fwd_a_frac_pre2_46: rf1_a_frac_pre2_b(46) <= not( (sel_a_load0 and ex6_frac_lod_ear(46) ) or (sel_a_load1 and ex6_frac_lod_dly(46) ) ); +fwd_a_frac_pre2_47: rf1_a_frac_pre2_b(47) <= not( (sel_a_load0 and ex6_frac_lod_ear(47) ) or (sel_a_load1 and ex6_frac_lod_dly(47) ) ); +fwd_a_frac_pre2_48: rf1_a_frac_pre2_b(48) <= not( (sel_a_load0 and ex6_frac_lod_ear(48) ) or (sel_a_load1 and ex6_frac_lod_dly(48) ) ); +fwd_a_frac_pre2_49: rf1_a_frac_pre2_b(49) <= not( (sel_a_load0 and ex6_frac_lod_ear(49) ) or (sel_a_load1 and ex6_frac_lod_dly(49) ) ); +fwd_a_frac_pre2_50: rf1_a_frac_pre2_b(50) <= not( (sel_a_load0 and ex6_frac_lod_ear(50) ) or (sel_a_load1 and ex6_frac_lod_dly(50) ) ); +fwd_a_frac_pre2_51: rf1_a_frac_pre2_b(51) <= not( (sel_a_load0 and ex6_frac_lod_ear(51) ) or (sel_a_load1 and ex6_frac_lod_dly(51) ) ); +fwd_a_frac_pre2_52: rf1_a_frac_pre2_b(52) <= not( (sel_a_load0 and ex6_frac_lod_ear(52) ) or (sel_a_load1 and ex6_frac_lod_dly(52) ) ); + +fwd_c_frac_pre2_00: rf1_c_frac_pre2_b( 0) <= not( (sel_c_load0 and ex6_frac_lod_ear( 0) ) or (sel_c_load1 and ex6_frac_lod_dly( 0) ) ); +fwd_c_frac_pre2_01: rf1_c_frac_pre2_b( 1) <= not( (sel_c_load0 and ex6_frac_lod_ear( 1) ) or (sel_c_load1 and ex6_frac_lod_dly( 1) ) ); +fwd_c_frac_pre2_02: rf1_c_frac_pre2_b( 2) <= not( (sel_c_load0 and ex6_frac_lod_ear( 2) ) or (sel_c_load1 and ex6_frac_lod_dly( 2) ) ); +fwd_c_frac_pre2_03: rf1_c_frac_pre2_b( 3) <= not( (sel_c_load0 and ex6_frac_lod_ear( 3) ) or (sel_c_load1 and ex6_frac_lod_dly( 3) ) ); +fwd_c_frac_pre2_04: rf1_c_frac_pre2_b( 4) <= not( (sel_c_load0 and ex6_frac_lod_ear( 4) ) or (sel_c_load1 and ex6_frac_lod_dly( 4) ) ); +fwd_c_frac_pre2_05: rf1_c_frac_pre2_b( 5) <= not( (sel_c_load0 and ex6_frac_lod_ear( 5) ) or (sel_c_load1 and ex6_frac_lod_dly( 5) ) ); +fwd_c_frac_pre2_06: rf1_c_frac_pre2_b( 6) <= not( (sel_c_load0 and ex6_frac_lod_ear( 6) ) or (sel_c_load1 and ex6_frac_lod_dly( 6) ) ); +fwd_c_frac_pre2_07: rf1_c_frac_pre2_b( 7) <= not( (sel_c_load0 and ex6_frac_lod_ear( 7) ) or (sel_c_load1 and ex6_frac_lod_dly( 7) ) ); +fwd_c_frac_pre2_08: rf1_c_frac_pre2_b( 8) <= not( (sel_c_load0 and ex6_frac_lod_ear( 8) ) or (sel_c_load1 and ex6_frac_lod_dly( 8) ) ); +fwd_c_frac_pre2_09: rf1_c_frac_pre2_b( 9) <= not( (sel_c_load0 and ex6_frac_lod_ear( 9) ) or (sel_c_load1 and ex6_frac_lod_dly( 9) ) ); +fwd_c_frac_pre2_10: rf1_c_frac_pre2_b(10) <= not( (sel_c_load0 and ex6_frac_lod_ear(10) ) or (sel_c_load1 and ex6_frac_lod_dly(10) ) ); +fwd_c_frac_pre2_11: rf1_c_frac_pre2_b(11) <= not( (sel_c_load0 and ex6_frac_lod_ear(11) ) or (sel_c_load1 and ex6_frac_lod_dly(11) ) ); +fwd_c_frac_pre2_12: rf1_c_frac_pre2_b(12) <= not( (sel_c_load0 and ex6_frac_lod_ear(12) ) or (sel_c_load1 and ex6_frac_lod_dly(12) ) ); +fwd_c_frac_pre2_13: rf1_c_frac_pre2_b(13) <= not( (sel_c_load0 and ex6_frac_lod_ear(13) ) or (sel_c_load1 and ex6_frac_lod_dly(13) ) ); +fwd_c_frac_pre2_14: rf1_c_frac_pre2_b(14) <= not( (sel_c_load0 and ex6_frac_lod_ear(14) ) or (sel_c_load1 and ex6_frac_lod_dly(14) ) ); +fwd_c_frac_pre2_15: rf1_c_frac_pre2_b(15) <= not( (sel_c_load0 and ex6_frac_lod_ear(15) ) or (sel_c_load1 and ex6_frac_lod_dly(15) ) ); +fwd_c_frac_pre2_16: rf1_c_frac_pre2_b(16) <= not( (sel_c_load0 and ex6_frac_lod_ear(16) ) or (sel_c_load1 and ex6_frac_lod_dly(16) ) ); +fwd_c_frac_pre2_17: rf1_c_frac_pre2_b(17) <= not( (sel_c_load0 and ex6_frac_lod_ear(17) ) or (sel_c_load1 and ex6_frac_lod_dly(17) ) ); +fwd_c_frac_pre2_18: rf1_c_frac_pre2_b(18) <= not( (sel_c_load0 and ex6_frac_lod_ear(18) ) or (sel_c_load1 and ex6_frac_lod_dly(18) ) ); +fwd_c_frac_pre2_19: rf1_c_frac_pre2_b(19) <= not( (sel_c_load0 and ex6_frac_lod_ear(19) ) or (sel_c_load1 and ex6_frac_lod_dly(19) ) ); +fwd_c_frac_pre2_20: rf1_c_frac_pre2_b(20) <= not( (sel_c_load0 and ex6_frac_lod_ear(20) ) or (sel_c_load1 and ex6_frac_lod_dly(20) ) ); +fwd_c_frac_pre2_21: rf1_c_frac_pre2_b(21) <= not( (sel_c_load0 and ex6_frac_lod_ear(21) ) or (sel_c_load1 and ex6_frac_lod_dly(21) ) ); +fwd_c_frac_pre2_22: rf1_c_frac_pre2_b(22) <= not( (sel_c_load0 and ex6_frac_lod_ear(22) ) or (sel_c_load1 and ex6_frac_lod_dly(22) ) ); +fwd_c_frac_pre2_23: rf1_c_frac_pre2_b(23) <= not( (sel_c_load0 and ex6_frac_lod_ear(23) ) or (sel_c_load1 and ex6_frac_lod_dly(23) ) ); +fwd_c_frac_pre2_24: rf1_c_frac_pre2_b(24) <= not( (sel_c_load0 and ex6_frac_lod_ear(24) ) or (sel_c_load1 and ex6_frac_lod_dly(24) ) ); +fwd_c_frac_pre2_25: rf1_c_frac_pre2_b(25) <= not( (sel_c_load0 and ex6_frac_lod_ear(25) ) or (sel_c_load1 and ex6_frac_lod_dly(25) ) ); +fwd_c_frac_pre2_26: rf1_c_frac_pre2_b(26) <= not( (sel_c_load0 and ex6_frac_lod_ear(26) ) or (sel_c_load1 and ex6_frac_lod_dly(26) ) ); +fwd_c_frac_pre2_27: rf1_c_frac_pre2_b(27) <= not( (sel_c_load0 and ex6_frac_lod_ear(27) ) or (sel_c_load1 and ex6_frac_lod_dly(27) ) ); +fwd_c_frac_pre2_28: rf1_c_frac_pre2_b(28) <= not( (sel_c_load0 and ex6_frac_lod_ear(28) ) or (sel_c_load1 and ex6_frac_lod_dly(28) ) ); +fwd_c_frac_pre2_29: rf1_c_frac_pre2_b(29) <= not( (sel_c_load0 and ex6_frac_lod_ear(29) ) or (sel_c_load1 and ex6_frac_lod_dly(29) ) ); +fwd_c_frac_pre2_30: rf1_c_frac_pre2_b(30) <= not( (sel_c_load0 and ex6_frac_lod_ear(30) ) or (sel_c_load1 and ex6_frac_lod_dly(30) ) ); +fwd_c_frac_pre2_31: rf1_c_frac_pre2_b(31) <= not( (sel_c_load0 and ex6_frac_lod_ear(31) ) or (sel_c_load1 and ex6_frac_lod_dly(31) ) ); +fwd_c_frac_pre2_32: rf1_c_frac_pre2_b(32) <= not( (sel_c_load0 and ex6_frac_lod_ear(32) ) or (sel_c_load1 and ex6_frac_lod_dly(32) ) ); +fwd_c_frac_pre2_33: rf1_c_frac_pre2_b(33) <= not( (sel_c_load0 and ex6_frac_lod_ear(33) ) or (sel_c_load1 and ex6_frac_lod_dly(33) ) ); +fwd_c_frac_pre2_34: rf1_c_frac_pre2_b(34) <= not( (sel_c_load0 and ex6_frac_lod_ear(34) ) or (sel_c_load1 and ex6_frac_lod_dly(34) ) ); +fwd_c_frac_pre2_35: rf1_c_frac_pre2_b(35) <= not( (sel_c_load0 and ex6_frac_lod_ear(35) ) or (sel_c_load1 and ex6_frac_lod_dly(35) ) ); +fwd_c_frac_pre2_36: rf1_c_frac_pre2_b(36) <= not( (sel_c_load0 and ex6_frac_lod_ear(36) ) or (sel_c_load1 and ex6_frac_lod_dly(36) ) ); +fwd_c_frac_pre2_37: rf1_c_frac_pre2_b(37) <= not( (sel_c_load0 and ex6_frac_lod_ear(37) ) or (sel_c_load1 and ex6_frac_lod_dly(37) ) ); +fwd_c_frac_pre2_38: rf1_c_frac_pre2_b(38) <= not( (sel_c_load0 and ex6_frac_lod_ear(38) ) or (sel_c_load1 and ex6_frac_lod_dly(38) ) ); +fwd_c_frac_pre2_39: rf1_c_frac_pre2_b(39) <= not( (sel_c_load0 and ex6_frac_lod_ear(39) ) or (sel_c_load1 and ex6_frac_lod_dly(39) ) ); +fwd_c_frac_pre2_40: rf1_c_frac_pre2_b(40) <= not( (sel_c_load0 and ex6_frac_lod_ear(40) ) or (sel_c_load1 and ex6_frac_lod_dly(40) ) ); +fwd_c_frac_pre2_41: rf1_c_frac_pre2_b(41) <= not( (sel_c_load0 and ex6_frac_lod_ear(41) ) or (sel_c_load1 and ex6_frac_lod_dly(41) ) ); +fwd_c_frac_pre2_42: rf1_c_frac_pre2_b(42) <= not( (sel_c_load0 and ex6_frac_lod_ear(42) ) or (sel_c_load1 and ex6_frac_lod_dly(42) ) ); +fwd_c_frac_pre2_43: rf1_c_frac_pre2_b(43) <= not( (sel_c_load0 and ex6_frac_lod_ear(43) ) or (sel_c_load1 and ex6_frac_lod_dly(43) ) ); +fwd_c_frac_pre2_44: rf1_c_frac_pre2_b(44) <= not( (sel_c_load0 and ex6_frac_lod_ear(44) ) or (sel_c_load1 and ex6_frac_lod_dly(44) ) ); +fwd_c_frac_pre2_45: rf1_c_frac_pre2_b(45) <= not( (sel_c_load0 and ex6_frac_lod_ear(45) ) or (sel_c_load1 and ex6_frac_lod_dly(45) ) ); +fwd_c_frac_pre2_46: rf1_c_frac_pre2_b(46) <= not( (sel_c_load0 and ex6_frac_lod_ear(46) ) or (sel_c_load1 and ex6_frac_lod_dly(46) ) ); +fwd_c_frac_pre2_47: rf1_c_frac_pre2_b(47) <= not( (sel_c_load0 and ex6_frac_lod_ear(47) ) or (sel_c_load1 and ex6_frac_lod_dly(47) ) ); +fwd_c_frac_pre2_48: rf1_c_frac_pre2_b(48) <= not( (sel_c_load0 and ex6_frac_lod_ear(48) ) or (sel_c_load1 and ex6_frac_lod_dly(48) ) ); +fwd_c_frac_pre2_49: rf1_c_frac_pre2_b(49) <= not( (sel_c_load0 and ex6_frac_lod_ear(49) ) or (sel_c_load1 and ex6_frac_lod_dly(49) ) ); +fwd_c_frac_pre2_50: rf1_c_frac_pre2_b(50) <= not( (sel_c_load0 and ex6_frac_lod_ear(50) ) or (sel_c_load1 and ex6_frac_lod_dly(50) ) ); +fwd_c_frac_pre2_51: rf1_c_frac_pre2_b(51) <= not( (sel_c_load0 and ex6_frac_lod_ear(51) ) or (sel_c_load1 and ex6_frac_lod_dly(51) ) ); +fwd_c_frac_pre2_52: rf1_c_frac_pre2_b(52) <= not( (sel_c_load0 and ex6_frac_lod_ear(52) ) or (sel_c_load1 and ex6_frac_lod_dly(52) ) ); + +fwd_b_frac_pre2_00: rf1_b_frac_pre2_b( 0) <= not( (sel_b_load0 and ex6_frac_lod_ear( 0) ) or (sel_b_load1 and ex6_frac_lod_dly( 0) ) ); +fwd_b_frac_pre2_01: rf1_b_frac_pre2_b( 1) <= not( (sel_b_load0 and ex6_frac_lod_ear( 1) ) or (sel_b_load1 and ex6_frac_lod_dly( 1) ) ); +fwd_b_frac_pre2_02: rf1_b_frac_pre2_b( 2) <= not( (sel_b_load0 and ex6_frac_lod_ear( 2) ) or (sel_b_load1 and ex6_frac_lod_dly( 2) ) ); +fwd_b_frac_pre2_03: rf1_b_frac_pre2_b( 3) <= not( (sel_b_load0 and ex6_frac_lod_ear( 3) ) or (sel_b_load1 and ex6_frac_lod_dly( 3) ) ); +fwd_b_frac_pre2_04: rf1_b_frac_pre2_b( 4) <= not( (sel_b_load0 and ex6_frac_lod_ear( 4) ) or (sel_b_load1 and ex6_frac_lod_dly( 4) ) ); +fwd_b_frac_pre2_05: rf1_b_frac_pre2_b( 5) <= not( (sel_b_load0 and ex6_frac_lod_ear( 5) ) or (sel_b_load1 and ex6_frac_lod_dly( 5) ) ); +fwd_b_frac_pre2_06: rf1_b_frac_pre2_b( 6) <= not( (sel_b_load0 and ex6_frac_lod_ear( 6) ) or (sel_b_load1 and ex6_frac_lod_dly( 6) ) ); +fwd_b_frac_pre2_07: rf1_b_frac_pre2_b( 7) <= not( (sel_b_load0 and ex6_frac_lod_ear( 7) ) or (sel_b_load1 and ex6_frac_lod_dly( 7) ) ); +fwd_b_frac_pre2_08: rf1_b_frac_pre2_b( 8) <= not( (sel_b_load0 and ex6_frac_lod_ear( 8) ) or (sel_b_load1 and ex6_frac_lod_dly( 8) ) ); +fwd_b_frac_pre2_09: rf1_b_frac_pre2_b( 9) <= not( (sel_b_load0 and ex6_frac_lod_ear( 9) ) or (sel_b_load1 and ex6_frac_lod_dly( 9) ) ); +fwd_b_frac_pre2_10: rf1_b_frac_pre2_b(10) <= not( (sel_b_load0 and ex6_frac_lod_ear(10) ) or (sel_b_load1 and ex6_frac_lod_dly(10) ) ); +fwd_b_frac_pre2_11: rf1_b_frac_pre2_b(11) <= not( (sel_b_load0 and ex6_frac_lod_ear(11) ) or (sel_b_load1 and ex6_frac_lod_dly(11) ) ); +fwd_b_frac_pre2_12: rf1_b_frac_pre2_b(12) <= not( (sel_b_load0 and ex6_frac_lod_ear(12) ) or (sel_b_load1 and ex6_frac_lod_dly(12) ) ); +fwd_b_frac_pre2_13: rf1_b_frac_pre2_b(13) <= not( (sel_b_load0 and ex6_frac_lod_ear(13) ) or (sel_b_load1 and ex6_frac_lod_dly(13) ) ); +fwd_b_frac_pre2_14: rf1_b_frac_pre2_b(14) <= not( (sel_b_load0 and ex6_frac_lod_ear(14) ) or (sel_b_load1 and ex6_frac_lod_dly(14) ) ); +fwd_b_frac_pre2_15: rf1_b_frac_pre2_b(15) <= not( (sel_b_load0 and ex6_frac_lod_ear(15) ) or (sel_b_load1 and ex6_frac_lod_dly(15) ) ); +fwd_b_frac_pre2_16: rf1_b_frac_pre2_b(16) <= not( (sel_b_load0 and ex6_frac_lod_ear(16) ) or (sel_b_load1 and ex6_frac_lod_dly(16) ) ); +fwd_b_frac_pre2_17: rf1_b_frac_pre2_b(17) <= not( (sel_b_load0 and ex6_frac_lod_ear(17) ) or (sel_b_load1 and ex6_frac_lod_dly(17) ) ); +fwd_b_frac_pre2_18: rf1_b_frac_pre2_b(18) <= not( (sel_b_load0 and ex6_frac_lod_ear(18) ) or (sel_b_load1 and ex6_frac_lod_dly(18) ) ); +fwd_b_frac_pre2_19: rf1_b_frac_pre2_b(19) <= not( (sel_b_load0 and ex6_frac_lod_ear(19) ) or (sel_b_load1 and ex6_frac_lod_dly(19) ) ); +fwd_b_frac_pre2_20: rf1_b_frac_pre2_b(20) <= not( (sel_b_load0 and ex6_frac_lod_ear(20) ) or (sel_b_load1 and ex6_frac_lod_dly(20) ) ); +fwd_b_frac_pre2_21: rf1_b_frac_pre2_b(21) <= not( (sel_b_load0 and ex6_frac_lod_ear(21) ) or (sel_b_load1 and ex6_frac_lod_dly(21) ) ); +fwd_b_frac_pre2_22: rf1_b_frac_pre2_b(22) <= not( (sel_b_load0 and ex6_frac_lod_ear(22) ) or (sel_b_load1 and ex6_frac_lod_dly(22) ) ); +fwd_b_frac_pre2_23: rf1_b_frac_pre2_b(23) <= not( (sel_b_load0 and ex6_frac_lod_ear(23) ) or (sel_b_load1 and ex6_frac_lod_dly(23) ) ); +fwd_b_frac_pre2_24: rf1_b_frac_pre2_b(24) <= not( (sel_b_load0 and ex6_frac_lod_ear(24) ) or (sel_b_load1 and ex6_frac_lod_dly(24) ) ); +fwd_b_frac_pre2_25: rf1_b_frac_pre2_b(25) <= not( (sel_b_load0 and ex6_frac_lod_ear(25) ) or (sel_b_load1 and ex6_frac_lod_dly(25) ) ); +fwd_b_frac_pre2_26: rf1_b_frac_pre2_b(26) <= not( (sel_b_load0 and ex6_frac_lod_ear(26) ) or (sel_b_load1 and ex6_frac_lod_dly(26) ) ); +fwd_b_frac_pre2_27: rf1_b_frac_pre2_b(27) <= not( (sel_b_load0 and ex6_frac_lod_ear(27) ) or (sel_b_load1 and ex6_frac_lod_dly(27) ) ); +fwd_b_frac_pre2_28: rf1_b_frac_pre2_b(28) <= not( (sel_b_load0 and ex6_frac_lod_ear(28) ) or (sel_b_load1 and ex6_frac_lod_dly(28) ) ); +fwd_b_frac_pre2_29: rf1_b_frac_pre2_b(29) <= not( (sel_b_load0 and ex6_frac_lod_ear(29) ) or (sel_b_load1 and ex6_frac_lod_dly(29) ) ); +fwd_b_frac_pre2_30: rf1_b_frac_pre2_b(30) <= not( (sel_b_load0 and ex6_frac_lod_ear(30) ) or (sel_b_load1 and ex6_frac_lod_dly(30) ) ); +fwd_b_frac_pre2_31: rf1_b_frac_pre2_b(31) <= not( (sel_b_load0 and ex6_frac_lod_ear(31) ) or (sel_b_load1 and ex6_frac_lod_dly(31) ) ); +fwd_b_frac_pre2_32: rf1_b_frac_pre2_b(32) <= not( (sel_b_load0 and ex6_frac_lod_ear(32) ) or (sel_b_load1 and ex6_frac_lod_dly(32) ) ); +fwd_b_frac_pre2_33: rf1_b_frac_pre2_b(33) <= not( (sel_b_load0 and ex6_frac_lod_ear(33) ) or (sel_b_load1 and ex6_frac_lod_dly(33) ) ); +fwd_b_frac_pre2_34: rf1_b_frac_pre2_b(34) <= not( (sel_b_load0 and ex6_frac_lod_ear(34) ) or (sel_b_load1 and ex6_frac_lod_dly(34) ) ); +fwd_b_frac_pre2_35: rf1_b_frac_pre2_b(35) <= not( (sel_b_load0 and ex6_frac_lod_ear(35) ) or (sel_b_load1 and ex6_frac_lod_dly(35) ) ); +fwd_b_frac_pre2_36: rf1_b_frac_pre2_b(36) <= not( (sel_b_load0 and ex6_frac_lod_ear(36) ) or (sel_b_load1 and ex6_frac_lod_dly(36) ) ); +fwd_b_frac_pre2_37: rf1_b_frac_pre2_b(37) <= not( (sel_b_load0 and ex6_frac_lod_ear(37) ) or (sel_b_load1 and ex6_frac_lod_dly(37) ) ); +fwd_b_frac_pre2_38: rf1_b_frac_pre2_b(38) <= not( (sel_b_load0 and ex6_frac_lod_ear(38) ) or (sel_b_load1 and ex6_frac_lod_dly(38) ) ); +fwd_b_frac_pre2_39: rf1_b_frac_pre2_b(39) <= not( (sel_b_load0 and ex6_frac_lod_ear(39) ) or (sel_b_load1 and ex6_frac_lod_dly(39) ) ); +fwd_b_frac_pre2_40: rf1_b_frac_pre2_b(40) <= not( (sel_b_load0 and ex6_frac_lod_ear(40) ) or (sel_b_load1 and ex6_frac_lod_dly(40) ) ); +fwd_b_frac_pre2_41: rf1_b_frac_pre2_b(41) <= not( (sel_b_load0 and ex6_frac_lod_ear(41) ) or (sel_b_load1 and ex6_frac_lod_dly(41) ) ); +fwd_b_frac_pre2_42: rf1_b_frac_pre2_b(42) <= not( (sel_b_load0 and ex6_frac_lod_ear(42) ) or (sel_b_load1 and ex6_frac_lod_dly(42) ) ); +fwd_b_frac_pre2_43: rf1_b_frac_pre2_b(43) <= not( (sel_b_load0 and ex6_frac_lod_ear(43) ) or (sel_b_load1 and ex6_frac_lod_dly(43) ) ); +fwd_b_frac_pre2_44: rf1_b_frac_pre2_b(44) <= not( (sel_b_load0 and ex6_frac_lod_ear(44) ) or (sel_b_load1 and ex6_frac_lod_dly(44) ) ); +fwd_b_frac_pre2_45: rf1_b_frac_pre2_b(45) <= not( (sel_b_load0 and ex6_frac_lod_ear(45) ) or (sel_b_load1 and ex6_frac_lod_dly(45) ) ); +fwd_b_frac_pre2_46: rf1_b_frac_pre2_b(46) <= not( (sel_b_load0 and ex6_frac_lod_ear(46) ) or (sel_b_load1 and ex6_frac_lod_dly(46) ) ); +fwd_b_frac_pre2_47: rf1_b_frac_pre2_b(47) <= not( (sel_b_load0 and ex6_frac_lod_ear(47) ) or (sel_b_load1 and ex6_frac_lod_dly(47) ) ); +fwd_b_frac_pre2_48: rf1_b_frac_pre2_b(48) <= not( (sel_b_load0 and ex6_frac_lod_ear(48) ) or (sel_b_load1 and ex6_frac_lod_dly(48) ) ); +fwd_b_frac_pre2_49: rf1_b_frac_pre2_b(49) <= not( (sel_b_load0 and ex6_frac_lod_ear(49) ) or (sel_b_load1 and ex6_frac_lod_dly(49) ) ); +fwd_b_frac_pre2_50: rf1_b_frac_pre2_b(50) <= not( (sel_b_load0 and ex6_frac_lod_ear(50) ) or (sel_b_load1 and ex6_frac_lod_dly(50) ) ); +fwd_b_frac_pre2_51: rf1_b_frac_pre2_b(51) <= not( (sel_b_load0 and ex6_frac_lod_ear(51) ) or (sel_b_load1 and ex6_frac_lod_dly(51) ) ); +fwd_b_frac_pre2_52: rf1_b_frac_pre2_b(52) <= not( (sel_b_load0 and ex6_frac_lod_ear(52) ) or (sel_b_load1 and ex6_frac_lod_dly(52) ) ); + + +fwd_a_frac_pre_00: rf1_a_frac_pre( 0) <= not( rf1_a_frac_pre1_b( 0) and rf1_a_frac_pre2_b( 0) ); +fwd_a_frac_pre_01: rf1_a_frac_pre( 1) <= not( rf1_a_frac_pre1_b( 1) and rf1_a_frac_pre2_b( 1) ); +fwd_a_frac_pre_02: rf1_a_frac_pre( 2) <= not( rf1_a_frac_pre1_b( 2) and rf1_a_frac_pre2_b( 2) ); +fwd_a_frac_pre_03: rf1_a_frac_pre( 3) <= not( rf1_a_frac_pre1_b( 3) and rf1_a_frac_pre2_b( 3) ); +fwd_a_frac_pre_04: rf1_a_frac_pre( 4) <= not( rf1_a_frac_pre1_b( 4) and rf1_a_frac_pre2_b( 4) ); +fwd_a_frac_pre_05: rf1_a_frac_pre( 5) <= not( rf1_a_frac_pre1_b( 5) and rf1_a_frac_pre2_b( 5) ); +fwd_a_frac_pre_06: rf1_a_frac_pre( 6) <= not( rf1_a_frac_pre1_b( 6) and rf1_a_frac_pre2_b( 6) ); +fwd_a_frac_pre_07: rf1_a_frac_pre( 7) <= not( rf1_a_frac_pre1_b( 7) and rf1_a_frac_pre2_b( 7) ); +fwd_a_frac_pre_08: rf1_a_frac_pre( 8) <= not( rf1_a_frac_pre1_b( 8) and rf1_a_frac_pre2_b( 8) ); +fwd_a_frac_pre_09: rf1_a_frac_pre( 9) <= not( rf1_a_frac_pre1_b( 9) and rf1_a_frac_pre2_b( 9) ); +fwd_a_frac_pre_10: rf1_a_frac_pre(10) <= not( rf1_a_frac_pre1_b(10) and rf1_a_frac_pre2_b(10) ); +fwd_a_frac_pre_11: rf1_a_frac_pre(11) <= not( rf1_a_frac_pre1_b(11) and rf1_a_frac_pre2_b(11) ); +fwd_a_frac_pre_12: rf1_a_frac_pre(12) <= not( rf1_a_frac_pre1_b(12) and rf1_a_frac_pre2_b(12) ); +fwd_a_frac_pre_13: rf1_a_frac_pre(13) <= not( rf1_a_frac_pre1_b(13) and rf1_a_frac_pre2_b(13) ); +fwd_a_frac_pre_14: rf1_a_frac_pre(14) <= not( rf1_a_frac_pre1_b(14) and rf1_a_frac_pre2_b(14) ); +fwd_a_frac_pre_15: rf1_a_frac_pre(15) <= not( rf1_a_frac_pre1_b(15) and rf1_a_frac_pre2_b(15) ); +fwd_a_frac_pre_16: rf1_a_frac_pre(16) <= not( rf1_a_frac_pre1_b(16) and rf1_a_frac_pre2_b(16) ); +fwd_a_frac_pre_17: rf1_a_frac_pre(17) <= not( rf1_a_frac_pre1_b(17) and rf1_a_frac_pre2_b(17) ); +fwd_a_frac_pre_18: rf1_a_frac_pre(18) <= not( rf1_a_frac_pre1_b(18) and rf1_a_frac_pre2_b(18) ); +fwd_a_frac_pre_19: rf1_a_frac_pre(19) <= not( rf1_a_frac_pre1_b(19) and rf1_a_frac_pre2_b(19) ); +fwd_a_frac_pre_20: rf1_a_frac_pre(20) <= not( rf1_a_frac_pre1_b(20) and rf1_a_frac_pre2_b(20) ); +fwd_a_frac_pre_21: rf1_a_frac_pre(21) <= not( rf1_a_frac_pre1_b(21) and rf1_a_frac_pre2_b(21) ); +fwd_a_frac_pre_22: rf1_a_frac_pre(22) <= not( rf1_a_frac_pre1_b(22) and rf1_a_frac_pre2_b(22) ); +fwd_a_frac_pre_23: rf1_a_frac_pre(23) <= not( rf1_a_frac_pre1_b(23) and rf1_a_frac_pre2_b(23) ); +fwd_a_frac_pre_24: rf1_a_frac_pre(24) <= not( rf1_a_frac_pre1_b(24) and rf1_a_frac_pre2_b(24) ); +fwd_a_frac_pre_25: rf1_a_frac_pre(25) <= not( rf1_a_frac_pre1_b(25) and rf1_a_frac_pre2_b(25) ); +fwd_a_frac_pre_26: rf1_a_frac_pre(26) <= not( rf1_a_frac_pre1_b(26) and rf1_a_frac_pre2_b(26) ); +fwd_a_frac_pre_27: rf1_a_frac_pre(27) <= not( rf1_a_frac_pre1_b(27) and rf1_a_frac_pre2_b(27) ); +fwd_a_frac_pre_28: rf1_a_frac_pre(28) <= not( rf1_a_frac_pre1_b(28) and rf1_a_frac_pre2_b(28) ); +fwd_a_frac_pre_29: rf1_a_frac_pre(29) <= not( rf1_a_frac_pre1_b(29) and rf1_a_frac_pre2_b(29) ); +fwd_a_frac_pre_30: rf1_a_frac_pre(30) <= not( rf1_a_frac_pre1_b(30) and rf1_a_frac_pre2_b(30) ); +fwd_a_frac_pre_31: rf1_a_frac_pre(31) <= not( rf1_a_frac_pre1_b(31) and rf1_a_frac_pre2_b(31) ); +fwd_a_frac_pre_32: rf1_a_frac_pre(32) <= not( rf1_a_frac_pre1_b(32) and rf1_a_frac_pre2_b(32) ); +fwd_a_frac_pre_33: rf1_a_frac_pre(33) <= not( rf1_a_frac_pre1_b(33) and rf1_a_frac_pre2_b(33) ); +fwd_a_frac_pre_34: rf1_a_frac_pre(34) <= not( rf1_a_frac_pre1_b(34) and rf1_a_frac_pre2_b(34) ); +fwd_a_frac_pre_35: rf1_a_frac_pre(35) <= not( rf1_a_frac_pre1_b(35) and rf1_a_frac_pre2_b(35) ); +fwd_a_frac_pre_36: rf1_a_frac_pre(36) <= not( rf1_a_frac_pre1_b(36) and rf1_a_frac_pre2_b(36) ); +fwd_a_frac_pre_37: rf1_a_frac_pre(37) <= not( rf1_a_frac_pre1_b(37) and rf1_a_frac_pre2_b(37) ); +fwd_a_frac_pre_38: rf1_a_frac_pre(38) <= not( rf1_a_frac_pre1_b(38) and rf1_a_frac_pre2_b(38) ); +fwd_a_frac_pre_39: rf1_a_frac_pre(39) <= not( rf1_a_frac_pre1_b(39) and rf1_a_frac_pre2_b(39) ); +fwd_a_frac_pre_40: rf1_a_frac_pre(40) <= not( rf1_a_frac_pre1_b(40) and rf1_a_frac_pre2_b(40) ); +fwd_a_frac_pre_41: rf1_a_frac_pre(41) <= not( rf1_a_frac_pre1_b(41) and rf1_a_frac_pre2_b(41) ); +fwd_a_frac_pre_42: rf1_a_frac_pre(42) <= not( rf1_a_frac_pre1_b(42) and rf1_a_frac_pre2_b(42) ); +fwd_a_frac_pre_43: rf1_a_frac_pre(43) <= not( rf1_a_frac_pre1_b(43) and rf1_a_frac_pre2_b(43) ); +fwd_a_frac_pre_44: rf1_a_frac_pre(44) <= not( rf1_a_frac_pre1_b(44) and rf1_a_frac_pre2_b(44) ); +fwd_a_frac_pre_45: rf1_a_frac_pre(45) <= not( rf1_a_frac_pre1_b(45) and rf1_a_frac_pre2_b(45) ); +fwd_a_frac_pre_46: rf1_a_frac_pre(46) <= not( rf1_a_frac_pre1_b(46) and rf1_a_frac_pre2_b(46) ); +fwd_a_frac_pre_47: rf1_a_frac_pre(47) <= not( rf1_a_frac_pre1_b(47) and rf1_a_frac_pre2_b(47) ); +fwd_a_frac_pre_48: rf1_a_frac_pre(48) <= not( rf1_a_frac_pre1_b(48) and rf1_a_frac_pre2_b(48) ); +fwd_a_frac_pre_49: rf1_a_frac_pre(49) <= not( rf1_a_frac_pre1_b(49) and rf1_a_frac_pre2_b(49) ); +fwd_a_frac_pre_50: rf1_a_frac_pre(50) <= not( rf1_a_frac_pre1_b(50) and rf1_a_frac_pre2_b(50) ); +fwd_a_frac_pre_51: rf1_a_frac_pre(51) <= not( rf1_a_frac_pre1_b(51) and rf1_a_frac_pre2_b(51) ); +fwd_a_frac_pre_52: rf1_a_frac_pre(52) <= not( rf1_a_frac_pre1_b(52) and rf1_a_frac_pre2_b(52) ); + +fwd_c_frac_pre_00: rf1_c_frac_pre( 0) <= not( rf1_c_frac_pre1_b( 0) and rf1_c_frac_pre2_b( 0) and rf1_c_frac_pre3_b( 0) ); +fwd_c_frac_pre_01: rf1_c_frac_pre( 1) <= not( rf1_c_frac_pre1_b( 1) and rf1_c_frac_pre2_b( 1) and rf1_c_frac_pre3_b( 1) ); +fwd_c_frac_pre_02: rf1_c_frac_pre( 2) <= not( rf1_c_frac_pre1_b( 2) and rf1_c_frac_pre2_b( 2) and rf1_c_frac_pre3_b( 2) ); +fwd_c_frac_pre_03: rf1_c_frac_pre( 3) <= not( rf1_c_frac_pre1_b( 3) and rf1_c_frac_pre2_b( 3) and rf1_c_frac_pre3_b( 3) ); +fwd_c_frac_pre_04: rf1_c_frac_pre( 4) <= not( rf1_c_frac_pre1_b( 4) and rf1_c_frac_pre2_b( 4) and rf1_c_frac_pre3_b( 4) ); +fwd_c_frac_pre_05: rf1_c_frac_pre( 5) <= not( rf1_c_frac_pre1_b( 5) and rf1_c_frac_pre2_b( 5) and rf1_c_frac_pre3_b( 5) ); +fwd_c_frac_pre_06: rf1_c_frac_pre( 6) <= not( rf1_c_frac_pre1_b( 6) and rf1_c_frac_pre2_b( 6) and rf1_c_frac_pre3_b( 6) ); +fwd_c_frac_pre_07: rf1_c_frac_pre( 7) <= not( rf1_c_frac_pre1_b( 7) and rf1_c_frac_pre2_b( 7) and rf1_c_frac_pre3_b( 7) ); +fwd_c_frac_pre_08: rf1_c_frac_pre( 8) <= not( rf1_c_frac_pre1_b( 8) and rf1_c_frac_pre2_b( 8) and rf1_c_frac_pre3_b( 8) ); +fwd_c_frac_pre_09: rf1_c_frac_pre( 9) <= not( rf1_c_frac_pre1_b( 9) and rf1_c_frac_pre2_b( 9) and rf1_c_frac_pre3_b( 9) ); +fwd_c_frac_pre_10: rf1_c_frac_pre(10) <= not( rf1_c_frac_pre1_b(10) and rf1_c_frac_pre2_b(10) and rf1_c_frac_pre3_b(10) ); +fwd_c_frac_pre_11: rf1_c_frac_pre(11) <= not( rf1_c_frac_pre1_b(11) and rf1_c_frac_pre2_b(11) and rf1_c_frac_pre3_b(11) ); +fwd_c_frac_pre_12: rf1_c_frac_pre(12) <= not( rf1_c_frac_pre1_b(12) and rf1_c_frac_pre2_b(12) and rf1_c_frac_pre3_b(12) ); +fwd_c_frac_pre_13: rf1_c_frac_pre(13) <= not( rf1_c_frac_pre1_b(13) and rf1_c_frac_pre2_b(13) and rf1_c_frac_pre3_b(13) ); +fwd_c_frac_pre_14: rf1_c_frac_pre(14) <= not( rf1_c_frac_pre1_b(14) and rf1_c_frac_pre2_b(14) and rf1_c_frac_pre3_b(14) ); +fwd_c_frac_pre_15: rf1_c_frac_pre(15) <= not( rf1_c_frac_pre1_b(15) and rf1_c_frac_pre2_b(15) and rf1_c_frac_pre3_b(15) ); +fwd_c_frac_pre_16: rf1_c_frac_pre(16) <= not( rf1_c_frac_pre1_b(16) and rf1_c_frac_pre2_b(16) and rf1_c_frac_pre3_b(16) ); +fwd_c_frac_pre_17: rf1_c_frac_pre(17) <= not( rf1_c_frac_pre1_b(17) and rf1_c_frac_pre2_b(17) and rf1_c_frac_pre3_b(17) ); +fwd_c_frac_pre_18: rf1_c_frac_pre(18) <= not( rf1_c_frac_pre1_b(18) and rf1_c_frac_pre2_b(18) and rf1_c_frac_pre3_b(18) ); +fwd_c_frac_pre_19: rf1_c_frac_pre(19) <= not( rf1_c_frac_pre1_b(19) and rf1_c_frac_pre2_b(19) and rf1_c_frac_pre3_b(19) ); +fwd_c_frac_pre_20: rf1_c_frac_pre(20) <= not( rf1_c_frac_pre1_b(20) and rf1_c_frac_pre2_b(20) and rf1_c_frac_pre3_b(20) ); +fwd_c_frac_pre_21: rf1_c_frac_pre(21) <= not( rf1_c_frac_pre1_b(21) and rf1_c_frac_pre2_b(21) and rf1_c_frac_pre3_b(21) ); +fwd_c_frac_pre_22: rf1_c_frac_pre(22) <= not( rf1_c_frac_pre1_b(22) and rf1_c_frac_pre2_b(22) and rf1_c_frac_pre3_b(22) ); +fwd_c_frac_pre_23: rf1_c_frac_pre(23) <= not( rf1_c_frac_pre1_b(23) and rf1_c_frac_pre2_b(23) and rf1_c_frac_pre3_b(23) ); +fwd_c_frac_pre_24: rf1_c_frac_pre(24) <= not( rf1_c_frac_pre1_b(24) and rf1_c_frac_pre2_b(24) and rf1_c_frac_pre3_b(24) ); +fwd_c_frac_pre_25: rf1_c_frac_pre(25) <= not( rf1_c_frac_pre1_b(25) and rf1_c_frac_pre2_b(25) and rf1_c_frac_pre3_b(25) ); +fwd_c_frac_pre_26: rf1_c_frac_pre(26) <= not( rf1_c_frac_pre1_b(26) and rf1_c_frac_pre2_b(26) and rf1_c_frac_pre3_b(26) ); +fwd_c_frac_pre_27: rf1_c_frac_pre(27) <= not( rf1_c_frac_pre1_b(27) and rf1_c_frac_pre2_b(27) and rf1_c_frac_pre3_b(27) ); +fwd_c_frac_pre_28: rf1_c_frac_pre(28) <= not( rf1_c_frac_pre1_b(28) and rf1_c_frac_pre2_b(28) and rf1_c_frac_pre3_b(28) ); +fwd_c_frac_pre_29: rf1_c_frac_pre(29) <= not( rf1_c_frac_pre1_b(29) and rf1_c_frac_pre2_b(29) and rf1_c_frac_pre3_b(29) ); +fwd_c_frac_pre_30: rf1_c_frac_pre(30) <= not( rf1_c_frac_pre1_b(30) and rf1_c_frac_pre2_b(30) and rf1_c_frac_pre3_b(30) ); +fwd_c_frac_pre_31: rf1_c_frac_pre(31) <= not( rf1_c_frac_pre1_b(31) and rf1_c_frac_pre2_b(31) and rf1_c_frac_pre3_b(31) ); +fwd_c_frac_pre_32: rf1_c_frac_pre(32) <= not( rf1_c_frac_pre1_b(32) and rf1_c_frac_pre2_b(32) and rf1_c_frac_pre3_b(32) ); +fwd_c_frac_pre_33: rf1_c_frac_pre(33) <= not( rf1_c_frac_pre1_b(33) and rf1_c_frac_pre2_b(33) and rf1_c_frac_pre3_b(33) ); +fwd_c_frac_pre_34: rf1_c_frac_pre(34) <= not( rf1_c_frac_pre1_b(34) and rf1_c_frac_pre2_b(34) and rf1_c_frac_pre3_b(34) ); +fwd_c_frac_pre_35: rf1_c_frac_pre(35) <= not( rf1_c_frac_pre1_b(35) and rf1_c_frac_pre2_b(35) and rf1_c_frac_pre3_b(35) ); +fwd_c_frac_pre_36: rf1_c_frac_pre(36) <= not( rf1_c_frac_pre1_b(36) and rf1_c_frac_pre2_b(36) and rf1_c_frac_pre3_b(36) ); +fwd_c_frac_pre_37: rf1_c_frac_pre(37) <= not( rf1_c_frac_pre1_b(37) and rf1_c_frac_pre2_b(37) and rf1_c_frac_pre3_b(37) ); +fwd_c_frac_pre_38: rf1_c_frac_pre(38) <= not( rf1_c_frac_pre1_b(38) and rf1_c_frac_pre2_b(38) and rf1_c_frac_pre3_b(38) ); +fwd_c_frac_pre_39: rf1_c_frac_pre(39) <= not( rf1_c_frac_pre1_b(39) and rf1_c_frac_pre2_b(39) and rf1_c_frac_pre3_b(39) ); +fwd_c_frac_pre_40: rf1_c_frac_pre(40) <= not( rf1_c_frac_pre1_b(40) and rf1_c_frac_pre2_b(40) and rf1_c_frac_pre3_b(40) ); +fwd_c_frac_pre_41: rf1_c_frac_pre(41) <= not( rf1_c_frac_pre1_b(41) and rf1_c_frac_pre2_b(41) and rf1_c_frac_pre3_b(41) ); +fwd_c_frac_pre_42: rf1_c_frac_pre(42) <= not( rf1_c_frac_pre1_b(42) and rf1_c_frac_pre2_b(42) and rf1_c_frac_pre3_b(42) ); +fwd_c_frac_pre_43: rf1_c_frac_pre(43) <= not( rf1_c_frac_pre1_b(43) and rf1_c_frac_pre2_b(43) and rf1_c_frac_pre3_b(43) ); +fwd_c_frac_pre_44: rf1_c_frac_pre(44) <= not( rf1_c_frac_pre1_b(44) and rf1_c_frac_pre2_b(44) and rf1_c_frac_pre3_b(44) ); +fwd_c_frac_pre_45: rf1_c_frac_pre(45) <= not( rf1_c_frac_pre1_b(45) and rf1_c_frac_pre2_b(45) and rf1_c_frac_pre3_b(45) ); +fwd_c_frac_pre_46: rf1_c_frac_pre(46) <= not( rf1_c_frac_pre1_b(46) and rf1_c_frac_pre2_b(46) and rf1_c_frac_pre3_b(46) ); +fwd_c_frac_pre_47: rf1_c_frac_pre(47) <= not( rf1_c_frac_pre1_b(47) and rf1_c_frac_pre2_b(47) and rf1_c_frac_pre3_b(47) ); +fwd_c_frac_pre_48: rf1_c_frac_pre(48) <= not( rf1_c_frac_pre1_b(48) and rf1_c_frac_pre2_b(48) and rf1_c_frac_pre3_b(48) ); +fwd_c_frac_pre_49: rf1_c_frac_pre(49) <= not( rf1_c_frac_pre1_b(49) and rf1_c_frac_pre2_b(49) and rf1_c_frac_pre3_b(49) ); +fwd_c_frac_pre_50: rf1_c_frac_pre(50) <= not( rf1_c_frac_pre1_b(50) and rf1_c_frac_pre2_b(50) and rf1_c_frac_pre3_b(50) ); +fwd_c_frac_pre_51: rf1_c_frac_pre(51) <= not( rf1_c_frac_pre1_b(51) and rf1_c_frac_pre2_b(51) and rf1_c_frac_pre3_b(51) ); +fwd_c_frac_pre_52: rf1_c_frac_pre(52) <= not( rf1_c_frac_pre1_b(52) and rf1_c_frac_pre2_b(52) and rf1_c_frac_pre3_b(52) ); + +fwd_c_frac_pre_24h: rf1_c_frac_pre_hulp <= not( rf1_c_frac_pre1_b(24) and rf1_c_frac_pre2_b(24) and rf1_c_frac_pre3_hulp_b ); + + +fwd_b_frac_pre_00: rf1_b_frac_pre( 0) <= not( rf1_b_frac_pre1_b( 0) and rf1_b_frac_pre2_b( 0) and rf1_b_frac_pre3_b( 0) ); +fwd_b_frac_pre_01: rf1_b_frac_pre( 1) <= not( rf1_b_frac_pre1_b( 1) and rf1_b_frac_pre2_b( 1) and rf1_b_frac_pre3_b( 1) ); +fwd_b_frac_pre_02: rf1_b_frac_pre( 2) <= not( rf1_b_frac_pre1_b( 2) and rf1_b_frac_pre2_b( 2) ); +fwd_b_frac_pre_03: rf1_b_frac_pre( 3) <= not( rf1_b_frac_pre1_b( 3) and rf1_b_frac_pre2_b( 3) ); +fwd_b_frac_pre_04: rf1_b_frac_pre( 4) <= not( rf1_b_frac_pre1_b( 4) and rf1_b_frac_pre2_b( 4) ); +fwd_b_frac_pre_05: rf1_b_frac_pre( 5) <= not( rf1_b_frac_pre1_b( 5) and rf1_b_frac_pre2_b( 5) ); +fwd_b_frac_pre_06: rf1_b_frac_pre( 6) <= not( rf1_b_frac_pre1_b( 6) and rf1_b_frac_pre2_b( 6) ); +fwd_b_frac_pre_07: rf1_b_frac_pre( 7) <= not( rf1_b_frac_pre1_b( 7) and rf1_b_frac_pre2_b( 7) ); +fwd_b_frac_pre_08: rf1_b_frac_pre( 8) <= not( rf1_b_frac_pre1_b( 8) and rf1_b_frac_pre2_b( 8) ); +fwd_b_frac_pre_09: rf1_b_frac_pre( 9) <= not( rf1_b_frac_pre1_b( 9) and rf1_b_frac_pre2_b( 9) ); +fwd_b_frac_pre_10: rf1_b_frac_pre(10) <= not( rf1_b_frac_pre1_b(10) and rf1_b_frac_pre2_b(10) ); +fwd_b_frac_pre_11: rf1_b_frac_pre(11) <= not( rf1_b_frac_pre1_b(11) and rf1_b_frac_pre2_b(11) ); +fwd_b_frac_pre_12: rf1_b_frac_pre(12) <= not( rf1_b_frac_pre1_b(12) and rf1_b_frac_pre2_b(12) ); +fwd_b_frac_pre_13: rf1_b_frac_pre(13) <= not( rf1_b_frac_pre1_b(13) and rf1_b_frac_pre2_b(13) ); +fwd_b_frac_pre_14: rf1_b_frac_pre(14) <= not( rf1_b_frac_pre1_b(14) and rf1_b_frac_pre2_b(14) ); +fwd_b_frac_pre_15: rf1_b_frac_pre(15) <= not( rf1_b_frac_pre1_b(15) and rf1_b_frac_pre2_b(15) ); +fwd_b_frac_pre_16: rf1_b_frac_pre(16) <= not( rf1_b_frac_pre1_b(16) and rf1_b_frac_pre2_b(16) ); +fwd_b_frac_pre_17: rf1_b_frac_pre(17) <= not( rf1_b_frac_pre1_b(17) and rf1_b_frac_pre2_b(17) ); +fwd_b_frac_pre_18: rf1_b_frac_pre(18) <= not( rf1_b_frac_pre1_b(18) and rf1_b_frac_pre2_b(18) ); +fwd_b_frac_pre_19: rf1_b_frac_pre(19) <= not( rf1_b_frac_pre1_b(19) and rf1_b_frac_pre2_b(19) ); +fwd_b_frac_pre_20: rf1_b_frac_pre(20) <= not( rf1_b_frac_pre1_b(20) and rf1_b_frac_pre2_b(20) ); +fwd_b_frac_pre_21: rf1_b_frac_pre(21) <= not( rf1_b_frac_pre1_b(21) and rf1_b_frac_pre2_b(21) ); +fwd_b_frac_pre_22: rf1_b_frac_pre(22) <= not( rf1_b_frac_pre1_b(22) and rf1_b_frac_pre2_b(22) ); +fwd_b_frac_pre_23: rf1_b_frac_pre(23) <= not( rf1_b_frac_pre1_b(23) and rf1_b_frac_pre2_b(23) ); +fwd_b_frac_pre_24: rf1_b_frac_pre(24) <= not( rf1_b_frac_pre1_b(24) and rf1_b_frac_pre2_b(24) ); +fwd_b_frac_pre_25: rf1_b_frac_pre(25) <= not( rf1_b_frac_pre1_b(25) and rf1_b_frac_pre2_b(25) ); +fwd_b_frac_pre_26: rf1_b_frac_pre(26) <= not( rf1_b_frac_pre1_b(26) and rf1_b_frac_pre2_b(26) ); +fwd_b_frac_pre_27: rf1_b_frac_pre(27) <= not( rf1_b_frac_pre1_b(27) and rf1_b_frac_pre2_b(27) ); +fwd_b_frac_pre_28: rf1_b_frac_pre(28) <= not( rf1_b_frac_pre1_b(28) and rf1_b_frac_pre2_b(28) ); +fwd_b_frac_pre_29: rf1_b_frac_pre(29) <= not( rf1_b_frac_pre1_b(29) and rf1_b_frac_pre2_b(29) ); +fwd_b_frac_pre_30: rf1_b_frac_pre(30) <= not( rf1_b_frac_pre1_b(30) and rf1_b_frac_pre2_b(30) ); +fwd_b_frac_pre_31: rf1_b_frac_pre(31) <= not( rf1_b_frac_pre1_b(31) and rf1_b_frac_pre2_b(31) ); +fwd_b_frac_pre_32: rf1_b_frac_pre(32) <= not( rf1_b_frac_pre1_b(32) and rf1_b_frac_pre2_b(32) ); +fwd_b_frac_pre_33: rf1_b_frac_pre(33) <= not( rf1_b_frac_pre1_b(33) and rf1_b_frac_pre2_b(33) ); +fwd_b_frac_pre_34: rf1_b_frac_pre(34) <= not( rf1_b_frac_pre1_b(34) and rf1_b_frac_pre2_b(34) ); +fwd_b_frac_pre_35: rf1_b_frac_pre(35) <= not( rf1_b_frac_pre1_b(35) and rf1_b_frac_pre2_b(35) ); +fwd_b_frac_pre_36: rf1_b_frac_pre(36) <= not( rf1_b_frac_pre1_b(36) and rf1_b_frac_pre2_b(36) ); +fwd_b_frac_pre_37: rf1_b_frac_pre(37) <= not( rf1_b_frac_pre1_b(37) and rf1_b_frac_pre2_b(37) ); +fwd_b_frac_pre_38: rf1_b_frac_pre(38) <= not( rf1_b_frac_pre1_b(38) and rf1_b_frac_pre2_b(38) ); +fwd_b_frac_pre_39: rf1_b_frac_pre(39) <= not( rf1_b_frac_pre1_b(39) and rf1_b_frac_pre2_b(39) ); +fwd_b_frac_pre_40: rf1_b_frac_pre(40) <= not( rf1_b_frac_pre1_b(40) and rf1_b_frac_pre2_b(40) ); +fwd_b_frac_pre_41: rf1_b_frac_pre(41) <= not( rf1_b_frac_pre1_b(41) and rf1_b_frac_pre2_b(41) ); +fwd_b_frac_pre_42: rf1_b_frac_pre(42) <= not( rf1_b_frac_pre1_b(42) and rf1_b_frac_pre2_b(42) ); +fwd_b_frac_pre_43: rf1_b_frac_pre(43) <= not( rf1_b_frac_pre1_b(43) and rf1_b_frac_pre2_b(43) ); +fwd_b_frac_pre_44: rf1_b_frac_pre(44) <= not( rf1_b_frac_pre1_b(44) and rf1_b_frac_pre2_b(44) ); +fwd_b_frac_pre_45: rf1_b_frac_pre(45) <= not( rf1_b_frac_pre1_b(45) and rf1_b_frac_pre2_b(45) ); +fwd_b_frac_pre_46: rf1_b_frac_pre(46) <= not( rf1_b_frac_pre1_b(46) and rf1_b_frac_pre2_b(46) ); +fwd_b_frac_pre_47: rf1_b_frac_pre(47) <= not( rf1_b_frac_pre1_b(47) and rf1_b_frac_pre2_b(47) ); +fwd_b_frac_pre_48: rf1_b_frac_pre(48) <= not( rf1_b_frac_pre1_b(48) and rf1_b_frac_pre2_b(48) ); +fwd_b_frac_pre_49: rf1_b_frac_pre(49) <= not( rf1_b_frac_pre1_b(49) and rf1_b_frac_pre2_b(49) ); +fwd_b_frac_pre_50: rf1_b_frac_pre(50) <= not( rf1_b_frac_pre1_b(50) and rf1_b_frac_pre2_b(50) ); +fwd_b_frac_pre_51: rf1_b_frac_pre(51) <= not( rf1_b_frac_pre1_b(51) and rf1_b_frac_pre2_b(51) ); +fwd_b_frac_pre_52: rf1_b_frac_pre(52) <= not( rf1_b_frac_pre1_b(52) and rf1_b_frac_pre2_b(52) ); + + + + rf1_a_frac_prebyp(0 to 52) <= rf1_a_frac_pre(0 to 52);-- may need to manually repower + rf1_c_frac_prebyp(0 to 52) <= rf1_c_frac_pre(0 to 52); + rf1_b_frac_prebyp(0 to 52) <= rf1_b_frac_pre(0 to 52); + rf1_c_frac_prebyp_hulp <= rf1_c_frac_pre_hulp ; + + rf1_a_sign_fpr <= f_fpr_rf1_a_sign ; -- later on we may map in some inverters + rf1_c_sign_fpr <= f_fpr_rf1_c_sign ; + rf1_b_sign_fpr <= f_fpr_rf1_b_sign ; + rf1_a_expo_fpr(1 to 13) <= f_fpr_rf1_a_expo(1 to 13) ; + rf1_c_expo_fpr(1 to 13) <= f_fpr_rf1_c_expo(1 to 13) ; + rf1_b_expo_fpr(1 to 13) <= f_fpr_rf1_b_expo(1 to 13) ; + rf1_a_frac_fpr(0 to 52) <= f_fpr_rf1_a_frac(0 to 52) ; + rf1_c_frac_fpr(0 to 52) <= f_fpr_rf1_c_frac(0 to 52) ; + rf1_b_frac_fpr(0 to 52) <= f_fpr_rf1_b_frac(0 to 52) ; + +----------------------------------------------------------------------------------------- +-- for the last level, need a seperate copy for each latch for the pass gate rules +-- (fpr is the late path ... so the mux is hierarchical to speed up that path) +----------------------------------------------------------------------------------------- + +fwd_a_sign_fmt: rf1_a_sign_fmt_b <= not( ( sel_a_no_byp_s and rf1_a_sign_fpr ) or rf1_a_sign_prebyp ); +fwd_a_sign_pic: rf1_a_sign_pic_b <= not( ( sel_a_no_byp_s and rf1_a_sign_fpr ) or rf1_a_sign_prebyp ); +fwd_c_sign_fmt: rf1_c_sign_fmt_b <= not( ( sel_c_no_byp_s and rf1_c_sign_fpr ) or rf1_c_sign_prebyp ); +fwd_c_sign_pic: rf1_c_sign_pic_b <= not( ( sel_c_no_byp_s and rf1_c_sign_fpr ) or rf1_c_sign_prebyp ); +fwd_b_sign_fmt: rf1_b_sign_fmt_b <= not( ( sel_b_no_byp_s and rf1_b_sign_fpr ) or rf1_b_sign_prebyp ); +fwd_b_sign_pic: rf1_b_sign_pic_b <= not( ( sel_b_no_byp_s and rf1_b_sign_fpr ) or rf1_b_sign_prebyp ); +fwd_b_sign_alg: rf1_b_sign_alg_b <= not( ( sel_b_no_byp_s and rf1_b_sign_fpr ) or rf1_b_sign_prebyp ); + +fwd_a_expo_fmt: rf1_a_expo_fmt_b(1 to 13) <= not( ( (1 to 13 => sel_a_no_byp) and rf1_a_expo_fpr(1 to 13) ) or rf1_a_expo_prebyp(1 to 13) ); +fwd_a_expo_eie: rf1_a_expo_eie_b(1 to 13) <= not( ( (1 to 13 => sel_a_no_byp) and rf1_a_expo_fpr(1 to 13) ) or rf1_a_expo_prebyp(1 to 13) ); +fwd_a_expo_alg: rf1_a_expo_alg_b(1 to 13) <= not( ( (1 to 13 => sel_a_no_byp) and rf1_a_expo_fpr(1 to 13) ) or rf1_a_expo_prebyp(1 to 13) ); +fwd_c_expo_fmt: rf1_c_expo_fmt_b(1 to 13) <= not( ( (1 to 13 => sel_c_no_byp) and rf1_c_expo_fpr(1 to 13) ) or rf1_c_expo_prebyp(1 to 13) ); +fwd_c_expo_eie: rf1_c_expo_eie_b(1 to 13) <= not( ( (1 to 13 => sel_c_no_byp) and rf1_c_expo_fpr(1 to 13) ) or rf1_c_expo_prebyp(1 to 13) ); +fwd_c_expo_alg: rf1_c_expo_alg_b(1 to 13) <= not( ( (1 to 13 => sel_c_no_byp) and rf1_c_expo_fpr(1 to 13) ) or rf1_c_expo_prebyp(1 to 13) ); +fwd_b_expo_fmt: rf1_b_expo_fmt_b(1 to 13) <= not( ( (1 to 13 => sel_b_no_byp) and rf1_b_expo_fpr(1 to 13) ) or rf1_b_expo_prebyp(1 to 13) ); +fwd_b_expo_eie: rf1_b_expo_eie_b(1 to 13) <= not( ( (1 to 13 => sel_b_no_byp) and rf1_b_expo_fpr(1 to 13) ) or rf1_b_expo_prebyp(1 to 13) ); +fwd_b_expo_alg: rf1_b_expo_alg_b(1 to 13) <= not( ( (1 to 13 => sel_b_no_byp) and rf1_b_expo_fpr(1 to 13) ) or rf1_b_expo_prebyp(1 to 13) ); + +fwd_a_frac_fmt_00: rf1_a_frac_fmt_b(0 to 23) <= not( ( (0 to 23 => sel_a_no_byp) AND rf1_a_frac_fpr(0 to 23) ) or rf1_a_frac_prebyp(0 to 23) ); +fwd_a_frac_mul_00: rf1_a_frac_mul_b(0 to 23) <= not( ( (0 to 23 => sel_a_no_byp) AND rf1_a_frac_fpr(0 to 23) ) or rf1_a_frac_prebyp(0 to 23) ); +fwd_a_frac_mul_17: rf1_a_frac_mul_17_b <= not( ( sel_a_no_byp AND rf1_a_frac_fpr(17) ) or rf1_a_frac_prebyp(17) ); +fwd_a_frac_fmt_24: rf1_a_frac_fmt_b(24 to 52) <= not( ( (24 to 52 => sel_a_no_byp) AND rf1_a_frac_fpr(24 to 52) ) or rf1_a_frac_prebyp(24 to 52) ); +fwd_a_frac_mul_24: rf1_a_frac_mul_b(24 to 52) <= not( ( (24 to 52 => sel_a_no_byp) AND rf1_a_frac_fpr(24 to 52) ) or rf1_a_frac_prebyp(24 to 52) ); +fwd_a_frac_mul_35: rf1_a_frac_mul_35_b <= not( ( sel_a_no_byp AND rf1_a_frac_fpr(35) ) or rf1_a_frac_prebyp(35) ); + +fwd_c_frac_fmt_00: rf1_c_frac_fmt_b(0 to 23) <= not( ( (0 to 23 => sel_c_no_byp) AND rf1_c_frac_fpr(0 to 23) ) or rf1_c_frac_prebyp(0 to 23) ); +fwd_c_frac_mul_00: rf1_c_frac_mul_b(0 to 23) <= not( ( (0 to 23 => sel_c_no_byp) AND rf1_c_frac_fpr(0 to 23) ) or rf1_c_frac_prebyp(0 to 23) ); + +fwd_c_frac_fmt_24: rf1_c_frac_fmt_b(24) <= not( ( sel_c_no_byp AND rf1_c_frac_fpr(24) ) or rf1_c_frac_prebyp(24) ); +fwd_c_frac_mul_24: rf1_c_frac_mul_b(24) <= not( ( sel_c_no_byp AND rf1_c_frac_fpr(24) ) or rf1_c_frac_prebyp_hulp ); + +fwd_c_frac_fmt_25: rf1_c_frac_fmt_b(25 to 52) <= not( ( (25 to 52 => sel_c_no_byp) AND rf1_c_frac_fpr(25 to 52) ) or rf1_c_frac_prebyp(25 to 52) ); +fwd_c_frac_mul_25: rf1_c_frac_mul_b(25 to 52) <= not( ( (25 to 52 => sel_c_no_byp) AND rf1_c_frac_fpr(25 to 52) ) or rf1_c_frac_prebyp(25 to 52) ); + rf1_c_frac_mul_b(53) <= not( f_dcd_rf1_uc_fc_hulp and not f_dcd_rf1_sp ); + +fwd_b_frac_fmt_00: rf1_b_frac_fmt_b(0 to 23) <= not( ( (0 to 23 => sel_b_no_byp) AND rf1_b_frac_fpr(0 to 23) ) or rf1_b_frac_prebyp(0 to 23) ); +fwd_b_frac_alg_00: rf1_b_frac_alg_b(0 to 23) <= not( ( (0 to 23 => sel_b_no_byp) AND rf1_b_frac_fpr(0 to 23) ) or rf1_b_frac_prebyp(0 to 23) ); +fwd_b_frac_fmt_24: rf1_b_frac_fmt_b(24 to 52) <= not( ( (24 to 52 => sel_b_no_byp) AND rf1_b_frac_fpr(24 to 52) ) or rf1_b_frac_prebyp(24 to 52) ); +fwd_b_frac_alg_24: rf1_b_frac_alg_b(24 to 52) <= not( ( (24 to 52 => sel_b_no_byp) AND rf1_b_frac_fpr(24 to 52) ) or rf1_b_frac_prebyp(24 to 52) ); + + + +--==================================================================== +--== ex1 operand latches +--==================================================================== + + ------------------ FRACTION --------------------------------------- + + + + + + ex1_frac_b_alg_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 53, btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd ,--inout + gd => gnd ,--inout + LCLK => byp_ex1_lclk ,--in --lclk.clk + D1CLK => byp_ex1_d1clk ,--in + D2CLK => byp_ex1_d2clk ,--in + SCANIN => ex1_b_frac_si ,--in + SCANOUT => ex1_b_frac_so ,--in + D => rf1_b_frac_alg_b(0 to 52) ,--in + QB => ex1_b_frac_alg (0 to 52) );--out + + ex1_frac_a_fmt_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 53, btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd ,--inout + gd => gnd ,--inout + LCLK => byp_ex1_lclk ,--in --lclk.clk + D1CLK => byp_ex1_d1clk ,--in + D2CLK => byp_ex1_d2clk ,--in + SCANIN => ex1_frac_a_fmt_si ,--in + SCANOUT => ex1_frac_a_fmt_so ,--in + D(0 to 52) => rf1_a_frac_fmt_b(0 to 52) , + QB(0 to 52) => ex1_a_frac_fmt (0 to 52) ); + + ex1_frac_c_fmt_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 53, btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd ,--inout + gd => gnd ,--inout + LCLK => byp_ex1_lclk ,--in --lclk.clk + D1CLK => byp_ex1_d1clk ,--in + D2CLK => byp_ex1_d2clk ,--in + SCANIN => ex1_frac_c_fmt_si ,--in + SCANOUT => ex1_frac_c_fmt_so ,--in + D(0 to 52) => rf1_c_frac_fmt_b(0 to 52) , + QB(0 to 52) => ex1_c_frac_fmt (0 to 52) ); + + ex1_frac_b_fmt_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 53, btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd ,--inout + gd => gnd ,--inout + LCLK => byp_ex1_lclk ,--in --lclk.clk + D1CLK => byp_ex1_d1clk ,--in + D2CLK => byp_ex1_d2clk ,--in + SCANIN => ex1_frac_b_fmt_si ,--in + SCANOUT => ex1_frac_b_fmt_so ,--in + D(0 to 52) => rf1_b_frac_fmt_b(0 to 52) , + QB(0 to 52) => ex1_b_frac_fmt (0 to 52) ); + + + u_qi_bfa: ex1_b_frac_alg_b(0 to 52) <= not ex1_b_frac_alg(0 to 52) ; + u_qi_bff: ex1_b_frac_fmt_b(0 to 52) <= not ex1_b_frac_fmt(0 to 52) ; + u_qi_cff: ex1_c_frac_fmt_b(0 to 52) <= not ex1_c_frac_fmt(0 to 52) ; + u_qi_aff: ex1_a_frac_fmt_b(0 to 52) <= not ex1_a_frac_fmt(0 to 52) ; + + u_di_cfm: temp_rf1_c_frac_mul(0 to 53) <= not rf1_c_frac_mul_b(0 to 53) ; + u_di_afm: temp_rf1_a_frac_mul(0 to 52) <= not rf1_a_frac_mul_b(0 to 52) ; + u_di_afm_17: temp_rf1_a_frac_mul_17 <= not rf1_a_frac_mul_17_b ; + u_di_afm_35: temp_rf1_a_frac_mul_35 <= not rf1_a_frac_mul_35_b ; + + + ex1_frac_c_mul_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 54, btr => "NLI0001_X4_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd ,--inout + gd => gnd ,--inout + LCLK => byp_ex1_lclk ,--in --lclk.clk + D1CLK => byp_ex1_d1clk ,--in + D2CLK => byp_ex1_d2clk ,--in + SCANIN => frac_mul_c_si ,--in + SCANOUT => frac_mul_c_so ,--in + D(0 to 52) => temp_rf1_c_frac_mul(0 to 52) ,--in + D(53) => temp_rf1_c_frac_mul(53) ,--in -- f_dcd_rf1_uc_fc_hulp, + QB => ex1_c_frac_mul_b(0 to 53) );--out + + ex1_frac_a_mul_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 55, btr => "NLI0001_X4_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd ,--inout + gd => gnd ,--inout + LCLK => byp_ex1_lclk ,--in --lclk.clk + D1CLK => byp_ex1_d1clk ,--in + D2CLK => byp_ex1_d2clk ,--in + SCANIN => frac_mul_a_si ,--in + SCANOUT => frac_mul_a_so ,--in + D( 0) => temp_rf1_a_frac_mul(0) , + D( 1) => temp_rf1_a_frac_mul(17) , + D( 2) => temp_rf1_a_frac_mul(35) , + D( 3) => temp_rf1_a_frac_mul(1) , + D( 4) => temp_rf1_a_frac_mul(18) , + D( 5) => temp_rf1_a_frac_mul(36) , + D( 6) => temp_rf1_a_frac_mul(2) , + D( 7) => temp_rf1_a_frac_mul(19) , + D( 8) => temp_rf1_a_frac_mul(37) , + D( 9) => temp_rf1_a_frac_mul(3) , + D(10) => temp_rf1_a_frac_mul(20) , + D(11) => temp_rf1_a_frac_mul(38) , + D(12) => temp_rf1_a_frac_mul(4) , + D(13) => temp_rf1_a_frac_mul(21) , + D(14) => temp_rf1_a_frac_mul(39) , + D(15) => temp_rf1_a_frac_mul(5) , + D(16) => temp_rf1_a_frac_mul(22) , + D(17) => temp_rf1_a_frac_mul(40) , + D(18) => temp_rf1_a_frac_mul(6) , + D(19) => temp_rf1_a_frac_mul(23) , + D(20) => temp_rf1_a_frac_mul(41) , + D(21) => temp_rf1_a_frac_mul(7) , + D(22) => temp_rf1_a_frac_mul(24) , + D(23) => temp_rf1_a_frac_mul(42) , + D(24) => temp_rf1_a_frac_mul(8) , + D(25) => temp_rf1_a_frac_mul(25) , + D(26) => temp_rf1_a_frac_mul(43) , + D(27) => temp_rf1_a_frac_mul(9) , + D(28) => temp_rf1_a_frac_mul(26) , + D(29) => temp_rf1_a_frac_mul(44) , + D(30) => temp_rf1_a_frac_mul(10) , + D(31) => temp_rf1_a_frac_mul(27) , + D(32) => temp_rf1_a_frac_mul(45) , + D(33) => temp_rf1_a_frac_mul(11) , + D(34) => temp_rf1_a_frac_mul(28) , + D(35) => temp_rf1_a_frac_mul(46) , + D(36) => temp_rf1_a_frac_mul(12) , + D(37) => temp_rf1_a_frac_mul(29) , + D(38) => temp_rf1_a_frac_mul(47) , + D(39) => temp_rf1_a_frac_mul(13) , + D(40) => temp_rf1_a_frac_mul(30) , + D(41) => temp_rf1_a_frac_mul(48) , + D(42) => temp_rf1_a_frac_mul(14) , + D(43) => temp_rf1_a_frac_mul(31) , + D(44) => temp_rf1_a_frac_mul(49) , + D(45) => temp_rf1_a_frac_mul(15) , + D(46) => temp_rf1_a_frac_mul(32) , + D(47) => temp_rf1_a_frac_mul(50) , + D(48) => temp_rf1_a_frac_mul(16) , + D(49) => temp_rf1_a_frac_mul(33) , + D(50) => temp_rf1_a_frac_mul(51) , + D(51) => temp_rf1_a_frac_mul_17 , -- copy of 17 for bit stacking + D(52) => temp_rf1_a_frac_mul(34) , + D(53) => temp_rf1_a_frac_mul(52) , + D(54) => temp_rf1_a_frac_mul_35 , -- copy of 35 for bit stacking + ------------------------------------------ + QB( 0) => ex1_a_frac_mul_b(0) , + QB( 1) => ex1_a_frac_mul_b(17) , -- real copy of bit 17 + QB( 2) => ex1_a_frac_mul_b(35) , -- real copy of bit 35 + QB( 3) => ex1_a_frac_mul_b(1) , + QB( 4) => ex1_a_frac_mul_b(18) , + QB( 5) => ex1_a_frac_mul_b(36) , + QB( 6) => ex1_a_frac_mul_b(2) , + QB( 7) => ex1_a_frac_mul_b(19) , + QB( 8) => ex1_a_frac_mul_b(37) , + QB( 9) => ex1_a_frac_mul_b(3) , + QB(10) => ex1_a_frac_mul_b(20) , + QB(11) => ex1_a_frac_mul_b(38) , + QB(12) => ex1_a_frac_mul_b(4) , + QB(13) => ex1_a_frac_mul_b(21) , + QB(14) => ex1_a_frac_mul_b(39) , + QB(15) => ex1_a_frac_mul_b(5) , + QB(16) => ex1_a_frac_mul_b(22) , + QB(17) => ex1_a_frac_mul_b(40) , + QB(18) => ex1_a_frac_mul_b(6) , + QB(19) => ex1_a_frac_mul_b(23) , + QB(20) => ex1_a_frac_mul_b(41) , + QB(21) => ex1_a_frac_mul_b(7) , + QB(22) => ex1_a_frac_mul_b(24) , + QB(23) => ex1_a_frac_mul_b(42) , + QB(24) => ex1_a_frac_mul_b(8) , + QB(25) => ex1_a_frac_mul_b(25) , + QB(26) => ex1_a_frac_mul_b(43) , + QB(27) => ex1_a_frac_mul_b(9) , + QB(28) => ex1_a_frac_mul_b(26) , + QB(29) => ex1_a_frac_mul_b(44) , + QB(30) => ex1_a_frac_mul_b(10) , + QB(31) => ex1_a_frac_mul_b(27) , + QB(32) => ex1_a_frac_mul_b(45) , + QB(33) => ex1_a_frac_mul_b(11) , + QB(34) => ex1_a_frac_mul_b(28) , + QB(35) => ex1_a_frac_mul_b(46) , + QB(36) => ex1_a_frac_mul_b(12) , + QB(37) => ex1_a_frac_mul_b(29) , + QB(38) => ex1_a_frac_mul_b(47) , + QB(39) => ex1_a_frac_mul_b(13) , + QB(40) => ex1_a_frac_mul_b(30) , + QB(41) => ex1_a_frac_mul_b(48) , + QB(42) => ex1_a_frac_mul_b(14) , + QB(43) => ex1_a_frac_mul_b(31) , + QB(44) => ex1_a_frac_mul_b(49) , + QB(45) => ex1_a_frac_mul_b(15) , + QB(46) => ex1_a_frac_mul_b(32) , + QB(47) => ex1_a_frac_mul_b(50) , + QB(48) => ex1_a_frac_mul_b(16) , + QB(49) => ex1_a_frac_mul_b(33) , + QB(50) => ex1_a_frac_mul_b(51) , + QB(51) => ex1_a_frac_mul_17_b , -- copy of 17 for bit stacking + QB(52) => ex1_a_frac_mul_b(34) , + QB(53) => ex1_a_frac_mul_b(52) , + QB(54) => ex1_a_frac_mul_35_b ); -- copy of 35 for bit stacking + + + bfa_oinv: f_byp_alg_ex1_b_frac(0 to 52) <= not ex1_b_frac_alg_b(0 to 52) ; + f_byp_fmt_ex1_a_frac(0 to 52) <= not ex1_a_frac_fmt_b(0 to 52); + f_byp_fmt_ex1_c_frac(0 to 52) <= not ex1_c_frac_fmt_b(0 to 52); + f_byp_fmt_ex1_b_frac(0 to 52) <= not ex1_b_frac_fmt_b(0 to 52); + afm_oinv: f_byp_mul_ex1_a_frac(0 to 52) <= not ex1_a_frac_mul_b(0 to 52); + afm_oinv_17: f_byp_mul_ex1_a_frac_17 <= not ex1_a_frac_mul_17_b ; + afm_oinv_35: f_byp_mul_ex1_a_frac_35 <= not ex1_a_frac_mul_35_b ; + cfm_oinv: f_byp_mul_ex1_c_frac(0 to 53) <= not ex1_c_frac_mul_b(0 to 53) ; + + + ------------------ EXPONENT SIGN ---------------------------------- + + ex1_expo_b_alg_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 14, btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd ,--inout + gd => gnd ,--inout + LCLK => byp_ex1_lclk ,--in --lclk.clk + D1CLK => byp_ex1_d1clk ,--in + D2CLK => byp_ex1_d2clk ,--in + SCANIN => ex1_expo_b_alg_si ,--in + SCANOUT => ex1_expo_b_alg_so ,--in + D(0) => rf1_b_sign_alg_b , + D(1 to 13) => rf1_b_expo_alg_b(1 to 13) , + QB(0) => ex1_b_sign_alg , + QB(1 to 13) => ex1_b_expo_alg (1 to 13) ); + + ex1_expo_c_alg_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 13, btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd ,--inout + gd => gnd ,--inout + LCLK => byp_ex1_lclk ,--in --lclk.clk + D1CLK => byp_ex1_d1clk ,--in + D2CLK => byp_ex1_d2clk ,--in + SCANIN => ex1_expo_c_alg_si ,--in + SCANOUT => ex1_expo_c_alg_so ,--in + D => rf1_c_expo_alg_b(1 to 13) , + QB => ex1_c_expo_alg (1 to 13) ); + + ex1_expo_a_alg_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 13, btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd ,--inout + gd => gnd ,--inout + LCLK => byp_ex1_lclk ,--in --lclk.clk + D1CLK => byp_ex1_d1clk ,--in + D2CLK => byp_ex1_d2clk ,--in + SCANIN => ex1_expo_a_alg_si ,--in + SCANOUT => ex1_expo_a_alg_so ,--in + D => rf1_a_expo_alg_b(1 to 13) , + QB => ex1_a_expo_alg (1 to 13) ); + + + ex1_expo_b_fmt_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 14, btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd ,--inout + gd => gnd ,--inout + LCLK => byp_ex1_lclk ,--in --lclk.clk + D1CLK => byp_ex1_d1clk ,--in + D2CLK => byp_ex1_d2clk ,--in + SCANIN => ex1_expo_b_fmt_si ,--in + SCANOUT => ex1_expo_b_fmt_so ,--in + D(0) => rf1_b_sign_fmt_b , + D(1 to 13) => rf1_b_expo_fmt_b(1 to 13) , + QB(0) => ex1_b_sign_fmt , + QB(1 to 13) => ex1_b_expo_fmt (1 to 13) ); + + ex1_expo_a_fmt_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 14, btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd ,--inout + gd => gnd ,--inout + LCLK => byp_ex1_lclk ,--in --lclk.clk + D1CLK => byp_ex1_d1clk ,--in + D2CLK => byp_ex1_d2clk ,--in + SCANIN => ex1_expo_a_fmt_si ,--in + SCANOUT => ex1_expo_a_fmt_so ,--in + D(0) => rf1_a_sign_fmt_b , + D(1 to 13) => rf1_a_expo_fmt_b(1 to 13) , + QB(0) => ex1_a_sign_fmt , + QB(1 to 13) => ex1_a_expo_fmt (1 to 13) ); + + ex1_expo_c_fmt_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 14, btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd ,--inout + gd => gnd ,--inout + LCLK => byp_ex1_lclk ,--in --lclk.clk + D1CLK => byp_ex1_d1clk ,--in + D2CLK => byp_ex1_d2clk ,--in + SCANIN => ex1_expo_c_fmt_si ,--in + SCANOUT => ex1_expo_c_fmt_so ,--in + D(0) => rf1_c_sign_fmt_b , + D(1 to 13) => rf1_c_expo_fmt_b(1 to 13) , + QB(0) => ex1_c_sign_fmt , + QB(1 to 13) => ex1_c_expo_fmt (1 to 13) ); + + ex1_expo_b_eie_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 14, btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd ,--inout + gd => gnd ,--inout + LCLK => byp_ex1_lclk ,--in --lclk.clk + D1CLK => byp_ex1_d1clk ,--in + D2CLK => byp_ex1_d2clk ,--in + SCANIN => ex1_expo_b_eie_si ,--in + SCANOUT => ex1_expo_b_eie_so ,--in + D(0) => rf1_b_sign_pic_b , + D(1 to 13) => rf1_b_expo_eie_b(1 to 13) , + QB(0) => ex1_b_sign_pic , + QB(1 to 13) => ex1_b_expo_eie (1 to 13) ); + + ex1_expo_a_eie_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 14, btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd ,--inout + gd => gnd ,--inout + LCLK => byp_ex1_lclk ,--in --lclk.clk + D1CLK => byp_ex1_d1clk ,--in + D2CLK => byp_ex1_d2clk ,--in + SCANIN => ex1_expo_a_eie_si ,--in + SCANOUT => ex1_expo_a_eie_so ,--in + D(0) => rf1_a_sign_pic_b , + D(1 to 13) => rf1_a_expo_eie_b(1 to 13) , + QB(0) => ex1_a_sign_pic , + QB(1 to 13) => ex1_a_expo_eie (1 to 13) ); + + ex1_expo_c_eie_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 14, btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd ,--inout + gd => gnd ,--inout + LCLK => byp_ex1_lclk ,--in --lclk.clk + D1CLK => byp_ex1_d1clk ,--in + D2CLK => byp_ex1_d2clk ,--in + SCANIN => ex1_expo_c_eie_si ,--in + SCANOUT => ex1_expo_c_eie_so ,--in + D(0) => rf1_c_sign_pic_b , + D(1 to 13) => rf1_c_expo_eie_b(1 to 13) , + QB(0) => ex1_c_sign_pic , + QB(1 to 13) => ex1_c_expo_eie (1 to 13) ); + + + + + + ex1_b_sign_alg_b <= not ex1_b_sign_alg ; + ex1_b_sign_fmt_b <= not ex1_b_sign_fmt ; + ex1_a_sign_fmt_b <= not ex1_a_sign_fmt ; + ex1_c_sign_fmt_b <= not ex1_c_sign_fmt ; + ex1_b_sign_pic_b <= not ex1_b_sign_pic ; + ex1_a_sign_pic_b <= not ex1_a_sign_pic ; + ex1_c_sign_pic_b <= not ex1_c_sign_pic ; + + ex1_b_expo_alg_b(1 to 13) <= not ex1_b_expo_alg(1 to 13); + ex1_c_expo_alg_b(1 to 13) <= not ex1_c_expo_alg(1 to 13); + ex1_a_expo_alg_b(1 to 13) <= not ex1_a_expo_alg(1 to 13); + ex1_b_expo_fmt_b(1 to 13) <= not ex1_b_expo_fmt(1 to 13); + ex1_c_expo_fmt_b(1 to 13) <= not ex1_c_expo_fmt(1 to 13); + ex1_a_expo_fmt_b(1 to 13) <= not ex1_a_expo_fmt(1 to 13); + ex1_b_expo_eie_b(1 to 13) <= not ex1_b_expo_eie(1 to 13); + ex1_c_expo_eie_b(1 to 13) <= not ex1_c_expo_eie(1 to 13); + ex1_a_expo_eie_b(1 to 13) <= not ex1_a_expo_eie(1 to 13); + + + f_byp_alg_ex1_b_sign <= not ex1_b_sign_alg_b; + f_byp_alg_ex1_b_expo(1 to 13) <= not ex1_b_expo_alg_b(1 to 13); + f_byp_alg_ex1_c_expo(1 to 13) <= not ex1_c_expo_alg_b(1 to 13); + f_byp_alg_ex1_a_expo(1 to 13) <= not ex1_a_expo_alg_b(1 to 13); + + f_byp_fmt_ex1_a_sign <= not ex1_a_sign_fmt_b ; + f_byp_fmt_ex1_a_expo(1 to 13) <= not ex1_a_expo_fmt_b(1 to 13) ; + f_byp_fmt_ex1_c_sign <= not ex1_c_sign_fmt_b ; + f_byp_fmt_ex1_c_expo(1 to 13) <= not ex1_c_expo_fmt_b(1 to 13) ; + f_byp_fmt_ex1_b_sign <= not ex1_b_sign_fmt_b ; + f_byp_fmt_ex1_b_expo(1 to 13) <= not ex1_b_expo_fmt_b(1 to 13) ; + + f_byp_pic_ex1_a_sign <= not ex1_a_sign_pic_b ; + f_byp_eie_ex1_a_expo(1 to 13) <= not ex1_a_expo_eie_b(1 to 13) ; + f_byp_pic_ex1_c_sign <= not ex1_c_sign_pic_b ; + f_byp_eie_ex1_c_expo(1 to 13) <= not ex1_c_expo_eie_b(1 to 13) ; + f_byp_pic_ex1_b_sign <= not ex1_b_sign_pic_b ; + f_byp_eie_ex1_b_expo(1 to 13) <= not ex1_b_expo_eie_b(1 to 13) ; + + + +--==================================================================== +--== scan chain +--==================================================================== + + act_si(0 to 3) <= act_so(1 to 3) & f_byp_si ; + ex1_b_frac_si(0 to 52) <= ex1_b_frac_so(1 to 52) & act_so(0) ; + ex1_frac_a_fmt_si(0 to 52) <= ex1_frac_a_fmt_so(1 to 52) & ex1_b_frac_so(0) ; + ex1_frac_c_fmt_si(0 to 52) <= ex1_frac_c_fmt_so(1 to 52) & ex1_frac_a_fmt_so(0) ; + ex1_frac_b_fmt_si(0 to 52) <= ex1_frac_b_fmt_so(1 to 52) & ex1_frac_c_fmt_so(0) ; + frac_mul_c_si(0 to 53) <= frac_mul_c_so(1 to 53) & ex1_frac_b_fmt_so(0) ; + frac_mul_a_si(0 to 54) <= frac_mul_a_so(1 to 54) & frac_mul_c_so(0) ; + ex1_expo_a_eie_si(0 to 13) <= ex1_expo_a_eie_so(1 to 13) & frac_mul_a_so(0) ; + ex1_expo_c_eie_si(0 to 13) <= ex1_expo_c_eie_so(1 to 13) & ex1_expo_a_eie_so(0); + ex1_expo_b_eie_si(0 to 13) <= ex1_expo_b_eie_so(1 to 13) & ex1_expo_c_eie_so(0); + ex1_expo_a_fmt_si(0 to 13) <= ex1_expo_a_fmt_so(1 to 13) & ex1_expo_b_eie_so(0); + ex1_expo_c_fmt_si(0 to 13) <= ex1_expo_c_fmt_so(1 to 13) & ex1_expo_a_fmt_so(0); + ex1_expo_b_fmt_si(0 to 13) <= ex1_expo_b_fmt_so(1 to 13) & ex1_expo_c_fmt_so(0); + ex1_expo_b_alg_si(0 to 13) <= ex1_expo_b_alg_so(1 to 13) & ex1_expo_b_fmt_so(0); + ex1_expo_a_alg_si(0 to 12) <= ex1_expo_a_alg_so(1 to 12) & ex1_expo_b_alg_so(0); + ex1_expo_c_alg_si(0 to 12) <= ex1_expo_c_alg_so(1 to 12) & ex1_expo_a_alg_so(0); + f_byp_so <= ex1_expo_c_alg_so(0) ; + + + +end; -- fuq_byp ARCHITECTURE diff --git a/rel/src/vhdl/work/fuq_cr2.vhdl b/rel/src/vhdl/work/fuq_cr2.vhdl new file mode 100644 index 0000000..e0a00bb --- /dev/null +++ b/rel/src/vhdl/work/fuq_cr2.vhdl @@ -0,0 +1,821 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + +-- FPSCR BIT DEFINITIONS +-- -------------- control +-- [24] ve +-- [25] oe +-- [26] ue +-- [27] ze +-- [28] xe +-- [29] non-ieee +-- [30:31] rnd_mode 00:nr 01:zr 02:pi 03:ni +-- +-- the rnd_mode must be read in ex2 of the using op +-- the rnd_mode is set in ex3 of the sending op (to_integer only) +-- there must be a 2 cycle bubble after update op +-- +-- set 1 2 3 +-- read x x 1 2 + + + +entity fuq_cr2 is +generic( expand_type : integer := 2 ); -- 0 - ibm tech, 1 - other ); +port( + + vdd :inout power_logic; + gnd :inout power_logic; + clkoff_b :in std_ulogic; -- tiup + act_dis :in std_ulogic; -- ??tidn?? + flush :in std_ulogic; -- ??tidn?? + delay_lclkr :in std_ulogic_vector(1 to 7); -- tidn, + mpw1_b :in std_ulogic_vector(1 to 7); -- tidn, + mpw2_b :in std_ulogic_vector(0 to 1); -- tidn, + sg_1 :in std_ulogic; + thold_1 :in std_ulogic; + fpu_enable :in std_ulogic; --dc_act + nclk :in clk_logic; + + + f_cr2_si :in std_ulogic ;-- perv + f_cr2_so :out std_ulogic ;-- perv + rf1_act :in std_ulogic ;-- HELP + ex1_act :in std_ulogic ;-- act writes + rf1_thread_b :in std_ulogic_vector(0 to 3) ;-- thread write + f_dcd_ex6_cancel :in std_ulogic ;-- + + f_fmt_ex1_bop_byt :in std_ulogic_vector(45 to 52); --for mtfsf to shadow reg + f_dcd_rf1_fpscr_bit_data_b :in std_ulogic_vector(0 to 3); --data to write to nibble (other than mtfsf) + f_dcd_rf1_fpscr_bit_mask_b :in std_ulogic_vector(0 to 3); --enable update of bit within the nibble + f_dcd_rf1_fpscr_nib_mask_b :in std_ulogic_vector(0 to 8); --enable update of this nibble + f_dcd_rf1_mtfsbx_b :in std_ulogic; --fpscr set bit, reset bit + f_dcd_rf1_mcrfs_b :in std_ulogic; --move fpscr field to cr and reset exceptions + f_dcd_rf1_mtfsf_b :in std_ulogic; --move fpr data to fpscr + f_dcd_rf1_mtfsfi_b :in std_ulogic; --move immediate data to fpscr + + f_cr2_ex3_thread_b :out std_ulogic_vector(0 to 3) ;--scr + f_cr2_ex3_fpscr_bit_data_b :out std_ulogic_vector(0 to 3); --data to write to nibble (other than mtfsf) + f_cr2_ex3_fpscr_bit_mask_b :out std_ulogic_vector(0 to 3); --enable update of bit within the nibble + f_cr2_ex3_fpscr_nib_mask_b :out std_ulogic_vector(0 to 8); --enable update of this nibble + f_cr2_ex3_mtfsbx_b :out std_ulogic; --fpscr set bit, reset bit + f_cr2_ex3_mcrfs_b :out std_ulogic; --move fpscr field to cr and reset exceptions + f_cr2_ex3_mtfsf_b :out std_ulogic; --move fpr data to fpscr + f_cr2_ex3_mtfsfi_b :out std_ulogic; --move immediate data to fpscr + + f_cr2_ex5_fpscr_rd_dat :out std_ulogic_vector(24 to 31); --scr + f_cr2_ex6_fpscr_rd_dat :out std_ulogic_vector(24 to 31); --scr + f_cr2_ex1_fpscr_shadow :out std_ulogic_vector(0 to 7) --fpic + + +); -- end ports + + + +end fuq_cr2; -- ENTITY + + +architecture fuq_cr2 of fuq_cr2 is + + constant tiup :std_ulogic := '1'; + constant tidn :std_ulogic := '0'; + + signal sg_0 :std_ulogic ; + signal thold_0_b , thold_0, forcee :std_ulogic ; + signal ex6_th0_act :std_ulogic ; + signal ex6_th1_act :std_ulogic ; + signal ex6_th2_act :std_ulogic ; + signal ex6_th3_act :std_ulogic ; + signal ex2_act :std_ulogic ; + signal ex3_act :std_ulogic ; + signal ex4_act, ex5_act, ex6_act :std_ulogic ; + signal ex4_mv_to_op :std_ulogic ; + signal ex5_mv_to_op :std_ulogic ; + signal ex6_mv_to_op :std_ulogic ; + + signal ex1_thread :std_ulogic_vector(0 to 3) ; + signal ex2_thread :std_ulogic_vector(0 to 3) ; + signal ex3_thread :std_ulogic_vector(0 to 3) ; + signal ex4_thread :std_ulogic_vector(0 to 3) ; + signal ex5_thread :std_ulogic_vector(0 to 3) ; + signal ex6_thread :std_ulogic_vector(0 to 3) ; + signal act_spare_unused :std_ulogic_vector(0 to 2) ; + ------------------- + signal act_so , act_si :std_ulogic_vector(0 to 6) ;--SCAN + signal ex1_ctl_so , ex1_ctl_si :std_ulogic_vector(0 to 33) ;--SCAN + signal ex2_ctl_so , ex2_ctl_si :std_ulogic_vector(0 to 24) ;--SCAN + signal ex3_ctl_so , ex3_ctl_si :std_ulogic_vector(0 to 24) ;--SCAN + signal ex4_ctl_so , ex4_ctl_si :std_ulogic_vector(0 to 4) ;--SCAN + signal ex5_ctl_so , ex5_ctl_si :std_ulogic_vector(0 to 4) ;--SCAN + signal ex6_ctl_so , ex6_ctl_si :std_ulogic_vector(0 to 4) ;--SCAN + signal shadow0_so , shadow0_si :std_ulogic_vector(0 to 7) ;--SCAN + signal shadow1_so , shadow1_si :std_ulogic_vector(0 to 7) ;--SCAN + signal shadow2_so , shadow2_si :std_ulogic_vector(0 to 7) ;--SCAN + signal shadow3_so , shadow3_si :std_ulogic_vector(0 to 7) ;--SCAN + signal shadow_byp2_so , shadow_byp2_si :std_ulogic_vector(0 to 7) ;--SCAN + signal shadow_byp3_so , shadow_byp3_si :std_ulogic_vector(0 to 7) ;--SCAN + signal shadow_byp4_so , shadow_byp4_si :std_ulogic_vector(0 to 7) ;--SCAN + signal shadow_byp5_so , shadow_byp5_si :std_ulogic_vector(0 to 7) ;--SCAN + signal shadow_byp6_so , shadow_byp6_si :std_ulogic_vector(0 to 7) ;--SCAN + ------------------- + signal shadow0 :std_ulogic_vector(0 to 7) ; + signal shadow1 :std_ulogic_vector(0 to 7) ; + signal shadow2 :std_ulogic_vector(0 to 7) ; + signal shadow3 :std_ulogic_vector(0 to 7) ; + signal shadow_byp2 :std_ulogic_vector(0 to 7) ; + signal shadow_byp3 :std_ulogic_vector(0 to 7) ; + signal shadow_byp4 :std_ulogic_vector(0 to 7) ; + signal shadow_byp5 :std_ulogic_vector(0 to 7) ; + signal shadow_byp6 :std_ulogic_vector(0 to 7) ; + signal shadow_byp2_din :std_ulogic_vector(0 to 7) ; + + signal ex1_bit_sel :std_ulogic_vector(0 to 7) ; + signal ex1_fpscr_bit_data :std_ulogic_vector(0 to 3); + signal ex1_fpscr_bit_mask :std_ulogic_vector(0 to 3); + signal ex1_fpscr_nib_mask :std_ulogic_vector(0 to 8); + signal ex1_mtfsbx :std_ulogic; + signal ex1_mcrfs :std_ulogic; + signal ex1_mtfsf :std_ulogic; + signal ex1_mtfsfi :std_ulogic; + signal ex2_fpscr_bit_data :std_ulogic_vector(0 to 3); + signal ex2_fpscr_bit_mask :std_ulogic_vector(0 to 3); + signal ex2_fpscr_nib_mask :std_ulogic_vector(0 to 8); + signal ex2_mtfsbx :std_ulogic; + signal ex2_mcrfs :std_ulogic; + signal ex2_mtfsf :std_ulogic; + signal ex2_mtfsfi :std_ulogic; + + signal ex3_fpscr_bit_data :std_ulogic_vector(0 to 3); + signal ex3_fpscr_bit_mask :std_ulogic_vector(0 to 3); + signal ex3_fpscr_nib_mask :std_ulogic_vector(0 to 8); + signal ex3_mtfsbx :std_ulogic; + signal ex3_mcrfs :std_ulogic; + signal ex3_mtfsf :std_ulogic; + signal ex3_mtfsfi :std_ulogic; + signal ex1_mv_to_op :std_ulogic; + signal ex2_mv_to_op :std_ulogic; + signal ex3_mv_to_op :std_ulogic; + signal ex1_fpscr_data :std_ulogic_vector(0 to 7); + signal rf1_thread :std_ulogic_vector(0 to 3); + signal rf1_rd_sel_0 , ex1_rd_sel_0 :std_ulogic; + signal rf1_rd_sel_1 , ex1_rd_sel_1 :std_ulogic; + signal rf1_rd_sel_2 , ex1_rd_sel_2 :std_ulogic; + signal rf1_rd_sel_3 , ex1_rd_sel_3 :std_ulogic; + signal rf1_rd_sel_byp2, ex1_rd_sel_byp2 :std_ulogic; + signal rf1_rd_sel_byp3, ex1_rd_sel_byp3 :std_ulogic; + signal rf1_rd_sel_byp4, ex1_rd_sel_byp4 :std_ulogic; + signal rf1_rd_sel_byp5, ex1_rd_sel_byp5 :std_ulogic; + signal rf1_rd_sel_byp6, ex1_rd_sel_byp6 :std_ulogic; + + signal rf1_rd_sel_byp2_pri :std_ulogic; + signal rf1_rd_sel_byp3_pri :std_ulogic; + signal rf1_rd_sel_byp4_pri :std_ulogic; + signal rf1_rd_sel_byp5_pri :std_ulogic; + signal rf1_rd_sel_byp6_pri :std_ulogic; + + signal ex1_fpscr_shadow_mux :std_ulogic_vector(0 to 7); + signal rf1_thread_match_1 :std_ulogic; + signal rf1_thread_match_2 :std_ulogic; + signal rf1_thread_match_3 :std_ulogic; + signal rf1_thread_match_4 :std_ulogic; + signal rf1_thread_match_5 :std_ulogic; + signal rf1_fpscr_bit_data :std_ulogic_vector(0 to 3) ; + signal rf1_fpscr_bit_mask :std_ulogic_vector(0 to 3) ; + signal rf1_fpscr_nib_mask :std_ulogic_vector(0 to 8) ; + signal rf1_mtfsbx :std_ulogic ; + signal rf1_mcrfs :std_ulogic ; + signal rf1_mtfsf :std_ulogic ; + signal rf1_mtfsfi :std_ulogic ; + signal ex6_cancel :std_ulogic; + signal ex6_fpscr_rd_dat_no_byp :std_ulogic_vector(24 to 31); + + +begin + + +--//############################################ +--//# pervasive +--//############################################ + + thold_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => thold_1, + q(0) => thold_0 ); + + sg_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => sg_1 , + q(0) => sg_0 ); + + + lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map ( + clkoff_b => clkoff_b, + thold => thold_0, + sg => sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => thold_0_b ); + + +--//############################################ +--//# ACT LATCHES +--//############################################ + + + act_lat: tri_rlmreg_p generic map (width=> 7, expand_type => expand_type, needs_sreset => 0) port map ( + forcee => forcee,-- tidn, + delay_lclkr => delay_lclkr(6) ,-- tidn, + mpw1_b => mpw1_b(6) ,-- tidn, + mpw2_b => mpw2_b(1) ,-- tidn, + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => fpu_enable, + scout => act_so , + scin => act_si , + ----------------- + din(0) => act_spare_unused(0), + din(1) => act_spare_unused(1), + din(2) => ex1_act, + din(3) => ex2_act, + din(4) => ex3_act, + din(5) => ex4_act, + din(6) => ex5_act, + ------------------- + dout(0) => act_spare_unused(0), + dout(1) => act_spare_unused(1), + dout(2) => ex2_act, + dout(3) => ex3_act, + dout(4) => ex4_act, + dout(5) => ex5_act , + dout(6) => ex6_act ); + + + act_spare_unused(2) <= rf1_act; + +--//############################################# +--//## ex1 latches +--//############################################# + + rf1_thread(0 to 3) <= not rf1_thread_b(0 to 3) ; + rf1_fpscr_bit_data(0 to 3) <= not f_dcd_rf1_fpscr_bit_data_b(0 to 3); + rf1_fpscr_bit_mask(0 to 3) <= not f_dcd_rf1_fpscr_bit_mask_b(0 to 3); + rf1_fpscr_nib_mask(0 to 8) <= not f_dcd_rf1_fpscr_nib_mask_b(0 to 8); + rf1_mtfsbx <= not f_dcd_rf1_mtfsbx_b ; + rf1_mcrfs <= not f_dcd_rf1_mcrfs_b ; + rf1_mtfsf <= not f_dcd_rf1_mtfsf_b ; + rf1_mtfsfi <= not f_dcd_rf1_mtfsfi_b ; + + + ex1_ctl_lat: tri_rlmreg_p generic map (width=> 34, expand_type => expand_type) port map ( + forcee => forcee,-- tidn, + delay_lclkr => delay_lclkr(1) ,-- tidn, + mpw1_b => mpw1_b(1) ,-- tidn, + mpw2_b => mpw2_b(0) ,-- tidn, + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => fpu_enable, + scout => ex1_ctl_so , + scin => ex1_ctl_si , + ------------------- + din(0 to 3) => rf1_thread(0 to 3) , + din(4 to 7) => rf1_fpscr_bit_data(0 to 3), + din(8 to 11) => rf1_fpscr_bit_mask(0 to 3), + din(12 to 20) => rf1_fpscr_nib_mask(0 to 8), + din(21) => rf1_mtfsbx , + din(22) => rf1_mcrfs , + din(23) => rf1_mtfsf , + din(24) => rf1_mtfsfi , + din(25) => rf1_rd_sel_0 , + din(26) => rf1_rd_sel_1 , + din(27) => rf1_rd_sel_2 , + din(28) => rf1_rd_sel_3 , + din(29) => rf1_rd_sel_byp2_pri , + din(30) => rf1_rd_sel_byp3_pri , + din(31) => rf1_rd_sel_byp4_pri , + din(32) => rf1_rd_sel_byp5_pri , + din(33) => rf1_rd_sel_byp6_pri , + ------------------- + dout(0 to 3) => ex1_thread(0 to 3) , + dout(4 to 7) => ex1_fpscr_bit_data(0 to 3), + dout(8 to 11) => ex1_fpscr_bit_mask(0 to 3), + dout(12 to 20) => ex1_fpscr_nib_mask(0 to 8), + dout(21) => ex1_mtfsbx , + dout(22) => ex1_mcrfs , + dout(23) => ex1_mtfsf , + dout(24) => ex1_mtfsfi , + dout(25) => ex1_rd_sel_0 , + dout(26) => ex1_rd_sel_1 , + dout(27) => ex1_rd_sel_2 , + dout(28) => ex1_rd_sel_3 , + dout(29) => ex1_rd_sel_byp2 , + dout(30) => ex1_rd_sel_byp3 , + dout(31) => ex1_rd_sel_byp4 , + dout(32) => ex1_rd_sel_byp5 , + dout(33) => ex1_rd_sel_byp6 ); + + +--//############################################# +--//## ex2 latches +--//############################################# + + ex2_ctl_lat: tri_rlmreg_p generic map (width=> 25, expand_type => expand_type) port map ( + forcee => forcee,-- tidn, + delay_lclkr => delay_lclkr(2) ,-- tidn, + mpw1_b => mpw1_b(2) ,-- tidn, + mpw2_b => mpw2_b(0) ,-- tidn, + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => fpu_enable, + scout => ex2_ctl_so , + scin => ex2_ctl_si , + ------------------- + din(0 to 3) => ex1_thread(0 to 3) , + din(4 to 7) => ex1_fpscr_bit_data(0 to 3) , + din(8 to 11) => ex1_fpscr_bit_mask(0 to 3) , + din(12 to 20) => ex1_fpscr_nib_mask(0 to 8) , + din(21) => ex1_mtfsbx , + din(22) => ex1_mcrfs , + din(23) => ex1_mtfsf , + din(24) => ex1_mtfsfi , + ------------------- + dout(0 to 3) => ex2_thread(0 to 3) , + dout(4 to 7) => ex2_fpscr_bit_data(0 to 3) , + dout(8 to 11) => ex2_fpscr_bit_mask(0 to 3) , + dout(12 to 20) => ex2_fpscr_nib_mask(0 to 8) , + dout(21) => ex2_mtfsbx , + dout(22) => ex2_mcrfs , + dout(23) => ex2_mtfsf , + dout(24) => ex2_mtfsfi ); + + +--//############################################# +--//## ex3 latches +--//############################################# + + ex3_ctl_lat: tri_rlmreg_p generic map (width=> 25, expand_type => expand_type) port map ( + forcee => forcee,-- tidn, + delay_lclkr => delay_lclkr(3) ,-- tidn, + mpw1_b => mpw1_b(3) ,-- tidn, + mpw2_b => mpw2_b(0) ,-- tidn, + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => fpu_enable, + scout => ex3_ctl_so , + scin => ex3_ctl_si , + ------------------- + din(0 to 3) => ex2_thread(0 to 3) , + din(4 to 7) => ex2_fpscr_bit_data(0 to 3) , + din(8 to 11) => ex2_fpscr_bit_mask(0 to 3) , + din(12 to 20) => ex2_fpscr_nib_mask(0 to 8) , + din(21) => ex2_mtfsbx , + din(22) => ex2_mcrfs , + din(23) => ex2_mtfsf , + din(24) => ex2_mtfsfi , + ------------------- + dout(0 to 3) => ex3_thread(0 to 3) , + dout(4 to 7) => ex3_fpscr_bit_data(0 to 3) , + dout(8 to 11) => ex3_fpscr_bit_mask(0 to 3) , + dout(12 to 20) => ex3_fpscr_nib_mask(0 to 8) , + dout(21) => ex3_mtfsbx , + dout(22) => ex3_mcrfs , + dout(23) => ex3_mtfsf , + dout(24) => ex3_mtfsfi ); + + f_cr2_ex3_thread_b(0 to 3) <= not ex3_thread(0 to 3) ;--output-- + f_cr2_ex3_fpscr_bit_data_b(0 to 3) <= not ex3_fpscr_bit_data(0 to 3);--output-- + f_cr2_ex3_fpscr_bit_mask_b(0 to 3) <= not ex3_fpscr_bit_mask(0 to 3);--output-- + f_cr2_ex3_fpscr_nib_mask_b(0 to 8) <= not ex3_fpscr_nib_mask(0 to 8);--output-- + f_cr2_ex3_mtfsbx_b <= not ex3_mtfsbx ;--output-- + f_cr2_ex3_mcrfs_b <= not ex3_mcrfs ;--output-- + f_cr2_ex3_mtfsf_b <= not ex3_mtfsf ;--output-- + f_cr2_ex3_mtfsfi_b <= not ex3_mtfsfi ;--output-- + + + + ex4_ctl_lat: tri_rlmreg_p generic map (width=> 5, expand_type => expand_type) port map ( + forcee => forcee,-- tidn, + delay_lclkr => delay_lclkr(4) ,-- tidn, + mpw1_b => mpw1_b(4) ,-- tidn, + mpw2_b => mpw2_b(0) ,-- tidn, + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => fpu_enable, + scout => ex4_ctl_so , + scin => ex4_ctl_si , + ------------------- + din(0 to 3) => ex3_thread(0 to 3) , + din(4) => ex3_mv_to_op , + ------------------- + dout(0 to 3) => ex4_thread(0 to 3) , + dout(4) => ex4_mv_to_op ); + + + ex5_ctl_lat: tri_rlmreg_p generic map (width=> 5, expand_type => expand_type) port map ( + forcee => forcee,-- tidn, + delay_lclkr => delay_lclkr(5) ,-- tidn, + mpw1_b => mpw1_b(5) ,-- tidn, + mpw2_b => mpw2_b(1) ,-- tidn, + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => fpu_enable, + scout => ex5_ctl_so , + scin => ex5_ctl_si , + ------------------- + din(0 to 3) => ex4_thread(0 to 3) , + din(4) => ex4_mv_to_op, + ------------------- + dout(0 to 3) => ex5_thread(0 to 3) , + dout(4) => ex5_mv_to_op ); + + ex6_ctl_lat: tri_rlmreg_p generic map (width=> 5, expand_type => expand_type) port map ( + forcee => forcee,-- tidn, + delay_lclkr => delay_lclkr(6) ,-- tidn, + mpw1_b => mpw1_b(6) ,-- tidn, + mpw2_b => mpw2_b(1) ,-- tidn, + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => fpu_enable, + scout => ex6_ctl_so , + scin => ex6_ctl_si , + ------------------- + din(0 to 3) => ex5_thread(0 to 3) , + din(4) => ex5_mv_to_op , + dout(0 to 3) => ex6_thread(0 to 3) , + dout(4) => ex6_mv_to_op ); + +ex6_cancel <= f_dcd_ex6_cancel; + +--//############################################## +--//# read mux for mffs instruction +--//############################################## + +f_cr2_ex5_fpscr_rd_dat(24 to 31) <= -- output to rounder + ( (24 to 31 => ex5_thread(0)) and shadow0(0 to 7) ) or + ( (24 to 31 => ex5_thread(1)) and shadow1(0 to 7) ) or + ( (24 to 31 => ex5_thread(2)) and shadow2(0 to 7) ) or + ( (24 to 31 => ex5_thread(3)) and shadow3(0 to 7) ) ; + + +ex6_fpscr_rd_dat_no_byp(24 to 31) <= + ( (24 to 31 => ex6_thread(0)) and shadow0(0 to 7) ) or + ( (24 to 31 => ex6_thread(1)) and shadow1(0 to 7) ) or + ( (24 to 31 => ex6_thread(2)) and shadow2(0 to 7) ) or + ( (24 to 31 => ex6_thread(3)) and shadow3(0 to 7) ) ; + +f_cr2_ex6_fpscr_rd_dat(24 to 31) <= + ( (24 to 31 => ex6_mv_to_op) and shadow_byp6(0 to 7) ) or + ( (24 to 31 => not ex6_mv_to_op) and ex6_fpscr_rd_dat_no_byp(24 to 31) ) ; + + + +--//############################################## +--//# fpscr write data / merge +--//############################################## + + ex1_bit_sel(0 to 3) <= ex1_fpscr_bit_mask(0 to 3) and (0 to 3 => ex1_mv_to_op and ex1_fpscr_nib_mask(6) ); + ex1_bit_sel(4 to 7) <= ex1_fpscr_bit_mask(0 to 3) and (0 to 3 => ex1_mv_to_op and ex1_fpscr_nib_mask(7) ); + + ex1_fpscr_data(0 to 3) <= + ( f_fmt_ex1_bop_byt(45 to 48) and (0 to 3=> ex1_mtfsf) ) or + ( ex1_fpscr_bit_data(0 to 3) and not (0 to 3=> ex1_mtfsf) ) ; + ex1_fpscr_data(4 to 7) <= + ( f_fmt_ex1_bop_byt(49 to 52) and (0 to 3=> ex1_mtfsf) ) or + ( ex1_fpscr_bit_data(0 to 3) and not (0 to 3=> ex1_mtfsf) ) ; + + shadow_byp2_din(0 to 7) <= -- may not update all the bits + (ex1_fpscr_shadow_mux(0 to 7) and not ex1_bit_sel(0 to 7) ) or + (ex1_fpscr_data(0 to 7) and ex1_bit_sel(0 to 7) ) ; + +--//############################################## +--//# read mux select generation (for pipeline control bits) +--//############################################## + + + ex1_mv_to_op <= ex1_mtfsbx or ex1_mtfsf or ex1_mtfsfi ; + ex2_mv_to_op <= ex2_mtfsbx or ex2_mtfsf or ex2_mtfsfi ; + ex3_mv_to_op <= ex3_mtfsbx or ex3_mtfsf or ex3_mtfsfi ; + + + rf1_thread_match_1 <= + ( rf1_thread(0) and ex1_thread(0) ) or + ( rf1_thread(1) and ex1_thread(1) ) or + ( rf1_thread(2) and ex1_thread(2) ) or + ( rf1_thread(3) and ex1_thread(3) ) ; + + rf1_thread_match_2 <= + ( rf1_thread(0) and ex2_thread(0) ) or + ( rf1_thread(1) and ex2_thread(1) ) or + ( rf1_thread(2) and ex2_thread(2) ) or + ( rf1_thread(3) and ex2_thread(3) ) ; + + rf1_thread_match_3 <= + ( rf1_thread(0) and ex3_thread(0) ) or + ( rf1_thread(1) and ex3_thread(1) ) or + ( rf1_thread(2) and ex3_thread(2) ) or + ( rf1_thread(3) and ex3_thread(3) ) ; + + rf1_thread_match_4 <= + ( rf1_thread(0) and ex4_thread(0) ) or + ( rf1_thread(1) and ex4_thread(1) ) or + ( rf1_thread(2) and ex4_thread(2) ) or + ( rf1_thread(3) and ex4_thread(3) ) ; + + rf1_thread_match_5 <= + ( rf1_thread(0) and ex5_thread(0) ) or + ( rf1_thread(1) and ex5_thread(1) ) or + ( rf1_thread(2) and ex5_thread(2) ) or + ( rf1_thread(3) and ex5_thread(3) ) ; + + rf1_rd_sel_byp2 <= rf1_thread_match_1 and ex1_mv_to_op ; + rf1_rd_sel_byp3 <= rf1_thread_match_2 and ex2_mv_to_op ; + rf1_rd_sel_byp4 <= rf1_thread_match_3 and ex3_mv_to_op ; + rf1_rd_sel_byp5 <= rf1_thread_match_4 and ex4_mv_to_op ; + rf1_rd_sel_byp6 <= rf1_thread_match_5 and ex5_mv_to_op ; + + rf1_rd_sel_0 <= rf1_thread(0) and not rf1_rd_sel_byp2 and not rf1_rd_sel_byp3 and not rf1_rd_sel_byp4 and not rf1_rd_sel_byp5 and not rf1_rd_sel_byp6 ; + rf1_rd_sel_1 <= rf1_thread(1) and not rf1_rd_sel_byp2 and not rf1_rd_sel_byp3 and not rf1_rd_sel_byp4 and not rf1_rd_sel_byp5 and not rf1_rd_sel_byp6 ; + rf1_rd_sel_2 <= rf1_thread(2) and not rf1_rd_sel_byp2 and not rf1_rd_sel_byp3 and not rf1_rd_sel_byp4 and not rf1_rd_sel_byp5 and not rf1_rd_sel_byp6 ; + rf1_rd_sel_3 <= rf1_thread(3) and not rf1_rd_sel_byp2 and not rf1_rd_sel_byp3 and not rf1_rd_sel_byp4 and not rf1_rd_sel_byp5 and not rf1_rd_sel_byp6 ; + + + rf1_rd_sel_byp2_pri <= rf1_rd_sel_byp2; + rf1_rd_sel_byp3_pri <= not rf1_rd_sel_byp2 and rf1_rd_sel_byp3; + rf1_rd_sel_byp4_pri <= not rf1_rd_sel_byp2 and not rf1_rd_sel_byp3 and rf1_rd_sel_byp4; + rf1_rd_sel_byp5_pri <= not rf1_rd_sel_byp2 and not rf1_rd_sel_byp3 and not rf1_rd_sel_byp4 and rf1_rd_sel_byp5; + rf1_rd_sel_byp6_pri <= not rf1_rd_sel_byp2 and not rf1_rd_sel_byp3 and not rf1_rd_sel_byp4 and not rf1_rd_sel_byp5 and rf1_rd_sel_byp6 ; + + +--//############################################## +--//# read mux for pipeline control bits +--//############################################## + + ex1_fpscr_shadow_mux(0 to 7) <= + ( (0 to 7 => ex1_rd_sel_0) and shadow0 (0 to 7) ) or + ( (0 to 7 => ex1_rd_sel_1) and shadow1 (0 to 7) ) or + ( (0 to 7 => ex1_rd_sel_2) and shadow2 (0 to 7) ) or + ( (0 to 7 => ex1_rd_sel_3) and shadow3 (0 to 7) ) or + ( (0 to 7 => ex1_rd_sel_byp2) and shadow_byp2(0 to 7) ) or + ( (0 to 7 => ex1_rd_sel_byp3) and shadow_byp3(0 to 7) ) or + ( (0 to 7 => ex1_rd_sel_byp4) and shadow_byp4(0 to 7) ) or + ( (0 to 7 => ex1_rd_sel_byp5) and shadow_byp5(0 to 7) ) or + ( (0 to 7 => ex1_rd_sel_byp6) and shadow_byp6(0 to 7) ) ; + + f_cr2_ex1_fpscr_shadow(0 to 7) <= ex1_fpscr_shadow_mux(0 to 7); + + +--//############################################## +--//# latches +--//############################################## + + shadow_byp2_lat: tri_rlmreg_p generic map (width=> 8, expand_type => expand_type) port map ( + forcee => forcee,-- tidn, + delay_lclkr => delay_lclkr(2) ,-- tidn, + mpw1_b => mpw1_b(2) ,-- tidn, + mpw2_b => mpw2_b(0) ,-- tidn, + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => ex1_act, + scout => shadow_byp2_so , + scin => shadow_byp2_si , + ------------------ + din => shadow_byp2_din(0 to 7), + dout => shadow_byp2 (0 to 7) );--LAT-- + + shadow_byp3_lat: tri_rlmreg_p generic map (width=> 8, expand_type => expand_type) port map ( + forcee => forcee,-- tidn, + delay_lclkr => delay_lclkr(3) ,-- tidn, + mpw1_b => mpw1_b(3) ,-- tidn, + mpw2_b => mpw2_b(0) ,-- tidn, + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => ex2_act, + scout => shadow_byp3_so , + scin => shadow_byp3_si , + ------------------- + din => shadow_byp2(0 to 7), + dout => shadow_byp3(0 to 7) );--LAT-- + + shadow_byp4_lat: tri_rlmreg_p generic map (width=> 8, expand_type => expand_type) port map ( + forcee => forcee,-- tidn, + delay_lclkr => delay_lclkr(4) ,-- tidn, + mpw1_b => mpw1_b(4) ,-- tidn, + mpw2_b => mpw2_b(0) ,-- tidn, + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => ex3_act, + scout => shadow_byp4_so , + scin => shadow_byp4_si , + ------------------- + din => shadow_byp3(0 to 7), + dout => shadow_byp4(0 to 7) );--LAT-- + + shadow_byp5_lat: tri_rlmreg_p generic map (width=> 8, expand_type => expand_type) port map ( + forcee => forcee,-- tidn, + delay_lclkr => delay_lclkr(5) ,-- tidn, + mpw1_b => mpw1_b(5) ,-- tidn, + mpw2_b => mpw2_b(1) ,-- tidn, + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => ex4_act, + scout => shadow_byp5_so , + scin => shadow_byp5_si , + ------------------- + din => shadow_byp4(0 to 7), + dout => shadow_byp5(0 to 7) );--LAT-- + + shadow_byp6_lat: tri_rlmreg_p generic map (width=> 8, expand_type => expand_type) port map ( + forcee => forcee,-- tidn, + delay_lclkr => delay_lclkr(6) ,-- tidn, + mpw1_b => mpw1_b(6) ,-- tidn, + mpw2_b => mpw2_b(1) ,-- tidn, + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => ex5_act, + scout => shadow_byp6_so , + scin => shadow_byp6_si , + din => shadow_byp5(0 to 7), + dout => shadow_byp6(0 to 7) ); + + ex6_th0_act <= ex6_act and ex6_thread(0) and not ex6_cancel and ex6_mv_to_op ; + ex6_th1_act <= ex6_act and ex6_thread(1) and not ex6_cancel and ex6_mv_to_op ; + ex6_th2_act <= ex6_act and ex6_thread(2) and not ex6_cancel and ex6_mv_to_op ; + ex6_th3_act <= ex6_act and ex6_thread(3) and not ex6_cancel and ex6_mv_to_op ; + + + + shadow0_lat: tri_rlmreg_p generic map (width=> 8, expand_type => expand_type) port map ( + forcee => forcee,-- tidn, + delay_lclkr => delay_lclkr(7) ,-- tidn, + mpw1_b => mpw1_b(7) ,-- tidn, + mpw2_b => mpw2_b(1) ,-- tidn, + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => ex6_th0_act, + scout => shadow0_so , + scin => shadow0_si , + ------------------- + din => shadow_byp6(0 to 7), + dout => shadow0(0 to 7) );--LAT-- + + shadow1_lat: tri_rlmreg_p generic map (width=> 8, expand_type => expand_type) port map ( + forcee => forcee,-- tidn, + delay_lclkr => delay_lclkr(7) ,-- tidn, + mpw1_b => mpw1_b(7) ,-- tidn, + mpw2_b => mpw2_b(1) ,-- tidn, + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => ex6_th1_act, + scout => shadow1_so , + scin => shadow1_si , + ------------------- + din => shadow_byp6(0 to 7), + dout => shadow1(0 to 7) );--LAT-- + + shadow2_lat: tri_rlmreg_p generic map (width=> 8, expand_type => expand_type) port map ( + forcee => forcee,-- tidn, + delay_lclkr => delay_lclkr(7) ,-- tidn, + mpw1_b => mpw1_b(7) ,-- tidn, + mpw2_b => mpw2_b(1) ,-- tidn, + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => ex6_th2_act, + scout => shadow2_so , + scin => shadow2_si , + ------------------- + din => shadow_byp6(0 to 7), + dout => shadow2(0 to 7) );--LAT-- + + shadow3_lat: tri_rlmreg_p generic map (width=> 8, expand_type => expand_type) port map ( + forcee => forcee,-- tidn, + delay_lclkr => delay_lclkr(7) ,-- tidn, + mpw1_b => mpw1_b(7) ,-- tidn, + mpw2_b => mpw2_b(1) ,-- tidn, + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => ex6_th3_act, + scout => shadow3_so , + scin => shadow3_si , + ------------------- + din => shadow_byp6(0 to 7), + dout => shadow3(0 to 7) );--LAT-- + + + +--//############################################ +--//# scan +--//############################################ + + + ex1_ctl_si (0 to 33) <= ex1_ctl_so (1 to 33) & f_cr2_si ; + ex2_ctl_si (0 to 24) <= ex2_ctl_so (1 to 24) & ex1_ctl_so (0); + ex3_ctl_si (0 to 24) <= ex3_ctl_so (1 to 24) & ex2_ctl_so (0); + ex4_ctl_si (0 to 4) <= ex4_ctl_so (1 to 4) & ex3_ctl_so (0); + ex5_ctl_si (0 to 4) <= ex5_ctl_so (1 to 4) & ex4_ctl_so (0); + ex6_ctl_si (0 to 4) <= ex6_ctl_so (1 to 4) & ex5_ctl_so (0); + shadow0_si (0 to 7) <= shadow0_so (1 to 7) & ex6_ctl_so (0); + shadow1_si (0 to 7) <= shadow1_so (1 to 7) & shadow0_so (0); + shadow2_si (0 to 7) <= shadow2_so (1 to 7) & shadow1_so (0); + shadow3_si (0 to 7) <= shadow3_so (1 to 7) & shadow2_so (0); + shadow_byp2_si (0 to 7) <= shadow_byp2_so (1 to 7) & shadow3_so (0); + shadow_byp3_si (0 to 7) <= shadow_byp3_so (1 to 7) & shadow_byp2_so (0); + shadow_byp4_si (0 to 7) <= shadow_byp4_so (1 to 7) & shadow_byp3_so (0); + shadow_byp5_si (0 to 7) <= shadow_byp5_so (1 to 7) & shadow_byp4_so (0); + shadow_byp6_si (0 to 7) <= shadow_byp6_so (1 to 7) & shadow_byp5_so (0); + act_si (0 to 6) <= act_so (1 to 6) & shadow_byp6_so (0); + f_cr2_so <= act_so (0) ; + + + +end; -- fuq_cr2 ARCHITECTURE diff --git a/rel/src/vhdl/work/fuq_csa22_h2.vhdl b/rel/src/vhdl/work/fuq_csa22_h2.vhdl new file mode 100644 index 0000000..ef269e9 --- /dev/null +++ b/rel/src/vhdl/work/fuq_csa22_h2.vhdl @@ -0,0 +1,58 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee; use ieee.std_logic_1164.all ; +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + +ENTITY fuq_csa22_h2 IS + PORT( + a : IN std_ulogic; + b : IN std_ulogic; + car : OUT std_ulogic; + sum : OUT std_ulogic + ); +END fuq_csa22_h2; + +ARCHITECTURE fuq_csa22_h2 OF fuq_csa22_h2 IS + + signal car_b, sum_b : std_ulogic; + + + +BEGIN + + u_22nandc: car_b <= not( a and b ); + u_22nands: sum_b <= not( car_b and (a or b) ); -- this is equiv to an xnor + u_22invc: car <= not car_b; + u_22invs: sum <= not sum_b ; + +END; diff --git a/rel/src/vhdl/work/fuq_dcd.vhdl b/rel/src/vhdl/work/fuq_dcd.vhdl new file mode 100644 index 0000000..027a531 --- /dev/null +++ b/rel/src/vhdl/work/fuq_dcd.vhdl @@ -0,0 +1,2866 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library IEEE,ibm,clib; +use IEEE.STD_LOGIC_1164.all; + +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_support.all; +library support; +use support.power_logic_pkg.all; + + +library tri; use tri.tri_latches_pkg.all; + +entity fuq_dcd is +generic( + expand_type : integer := 2 ; -- 0 - ibm tech, 1 - other ); + eff_ifar : integer := 62; + regmode : integer := 6); --32 or 64 bit mode +port( + nclk : in clk_logic; + clkoff_b : in std_ulogic; -- tiup + act_dis : in std_ulogic; -- ??tidn?? + flush : in std_ulogic; -- ??tidn?? + delay_lclkr : in std_ulogic_vector(0 to 9); -- tidn, + mpw1_b : in std_ulogic_vector(0 to 9); -- tidn, + mpw2_b : in std_ulogic_vector(0 to 1); -- tidn, + thold_1 : in std_ulogic; + cfg_sl_thold_1 : in std_ulogic; + func_slp_sl_thold_1 : in std_ulogic; + + sg_1 : in std_ulogic; + f_dcd_si : in std_ulogic; + f_dcd_so : out std_ulogic; + dcfg_scan_in : in std_ulogic; + dcfg_scan_out : out std_ulogic; + bcfg_scan_in : in std_ulogic; + bcfg_scan_out : out std_ulogic; + ccfg_scan_in : in std_ulogic; + ccfg_scan_out : out std_ulogic; + vdd : inout power_logic; + gnd : inout power_logic; + f_dcd_msr_fp_act : out std_ulogic; + fu_xu_rf1_act : out std_ulogic_vector(0 to 3); + + -- Interface to IU + iu_fu_rf0_instr_v : in std_ulogic; + iu_fu_rf0_instr : in std_ulogic_vector(0 to 31); + iu_fu_rf0_fra_v : in std_ulogic; + iu_fu_rf0_frb_v : in std_ulogic; + iu_fu_rf0_frc_v : in std_ulogic; + iu_fu_rf0_tid : in std_ulogic_vector(0 to 1); + iu_fu_rf0_fra : in std_ulogic_vector(0 to 6); + iu_fu_rf0_frb : in std_ulogic_vector(0 to 6); + iu_fu_rf0_frc : in std_ulogic_vector(0 to 6); + iu_fu_rf0_frt : in std_ulogic_vector(0 to 6); + iu_fu_rf0_ifar : in std_ulogic_vector(62-eff_ifar to 61); + iu_fu_rf0_str_val : in std_ulogic; + iu_fu_rf0_ldst_val : in std_ulogic; + iu_fu_rf0_ldst_tid : in std_ulogic_vector(0 to 1); + iu_fu_rf0_ldst_tag : in std_ulogic_vector(0 to 8); + iu_fu_rf0_bypsel : in std_ulogic_vector(0 to 5); + iu_fu_rf0_instr_match : in std_ulogic; + iu_fu_rf0_is_ucode : in std_ulogic; + iu_fu_rf0_ucfmul : in std_ulogic; + iu_fu_is2_tid_decode : in std_ulogic_vector(0 to 3); + iu_fu_ex2_n_flush : in std_ulogic_vector(0 to 3); + + f_fpr_ex7_load_addr : in std_ulogic_vector(0 to 7); + f_fpr_ex7_load_v : in std_ulogic; + -- flush signals + xu_is2_flush : in std_ulogic_vector(0 to 3); + xu_rf0_flush : in std_ulogic_vector(0 to 3); + xu_rf1_flush : in std_ulogic_vector(0 to 3); + xu_ex1_flush : in std_ulogic_vector(0 to 3); + xu_ex2_flush : in std_ulogic_vector(0 to 3); + xu_ex3_flush : in std_ulogic_vector(0 to 3); + xu_ex4_flush : in std_ulogic_vector(0 to 3); + xu_ex5_flush : in std_ulogic_vector(0 to 3); + f_dcd_ex5_flush_int : out std_ulogic_vector(0 to 3); + xu_fu_ex5_reload_val : in std_ulogic; + xu_fu_ex5_load_val : in std_ulogic_vector(0 to 3); + + f_dcd_perr_sm_running : out std_ulogic; + + -- Interface to mad + f_scr_ex7_cr_fld : in std_ulogic_vector (0 to 3) ;--o-- + f_add_ex4_fpcc_iu : in std_ulogic_vector (0 to 3) ;--o-- + f_pic_ex5_fpr_wr_dis_b : in std_ulogic ;--o-- + f_dcd_rf1_aop_valid : out std_ulogic; + f_dcd_rf1_cop_valid : out std_ulogic; + f_dcd_rf1_bop_valid : out std_ulogic; + f_dcd_rf1_sp : out std_ulogic; -- off for frsp + f_dcd_rf1_emin_dp : out std_ulogic; -- prenorm_dp + f_dcd_rf1_emin_sp : out std_ulogic; -- prenorm_sp, frsp + f_dcd_rf1_force_pass_b : out std_ulogic; -- fmr,fnabbs,fabs,fneg,mtfsf + + f_dcd_rf1_fsel_b : out std_ulogic; -- fsel + f_dcd_rf1_from_integer_b : out std_ulogic; -- fcfid (signed integer) + f_dcd_rf1_to_integer_b : out std_ulogic; -- fcti* (signed integer 32/64) + f_dcd_rf1_rnd_to_int_b : out std_ulogic; -- fri* + f_dcd_rf1_math_b : out std_ulogic; -- fmul,fmad,fmsub,fadd,fsub,fnmsub,fnmadd + f_dcd_rf1_est_recip_b : out std_ulogic; -- fres + f_dcd_rf1_est_rsqrt_b : out std_ulogic; -- frsqrte + f_dcd_rf1_move_b : out std_ulogic; -- fmr,fneg,fabs,fnabs + f_dcd_rf1_prenorm_b : out std_ulogic; -- prenorm ?? need + f_dcd_rf1_frsp_b : out std_ulogic; -- round-to-single-precision ?? need + f_dcd_rf1_compare_b : out std_ulogic; -- fcomp* + f_dcd_rf1_ordered_b : out std_ulogic; -- fcompo + + f_dcd_rf1_force_excp_dis : out std_ulogic; -- force all exceptions disabled + f_dcd_rf1_nj_deni : out std_ulogic; -- force input den to zero + f_dcd_rf1_nj_deno : out std_ulogic; -- force output den to zero + f_dcd_rf1_sp_conv_b : out std_ulogic; -- for sp/dp convert + f_dcd_rf1_uns_b : out std_ulogic; -- for converts unsigned + + f_dcd_rf1_word_b : out std_ulogic; -- fctiw* + f_dcd_rf1_sub_op_b : out std_ulogic; -- fsub, fnmsub, fmsub + f_dcd_rf1_op_rnd_v_b : out std_ulogic; -- rounding mode = nearest + f_dcd_rf1_op_rnd_b : out std_ulogic_vector(0 to 1); -- rounding mode = positive infinity + f_dcd_rf1_inv_sign_b : out std_ulogic; -- fnmsub fnmadd + f_dcd_rf1_sign_ctl_b : out std_ulogic_vector(0 to 1); -- 0:fmr/fnabs 1:fneg/fnabs + f_dcd_rf1_sgncpy_b : out std_ulogic; -- for sgncpy instruction : + -- BValid=1 Avalid=0 move=1 sgncpy=1 + -- sgnctl=fabs=00 <11 for _b> + -- force pass, rnd_v=0, ovf_unf_dis, + + f_dcd_rf1_fpscr_bit_data_b : out std_ulogic_vector(0 to 3); --data to write to nibble (other than mtfsf) + f_dcd_rf1_fpscr_bit_mask_b : out std_ulogic_vector(0 to 3); --enable update of bit within the nibble + f_dcd_rf1_fpscr_nib_mask_b : out std_ulogic_vector(0 to 8); --enable update of this nibble + -- [8] = 0 except + -- if (mtfsi AND w=1 AND bf=000 ) <= 0000_0000_1 + -- if (mtfsf AND L==1) <= 1111_1111_1 + -- if (mtfsf AND L=0 and w=1 and flm=xxxx_xxxx_1) <= 0000_0000_1 + -- if (mtfsf AND L=0 and w=1 and flm=xxxx_xxxx_0) <= 0000_0000_0 + -- if (mtfsf AND L=0 and w=0 and flm=xxxx_xxxx_1) <= dddd_dddd_0 + f_dcd_rf1_mv_to_scr_b : out std_ulogic; --mcrfs,mtfsf,mtfsfi,mtfsb0,mtfsb1 + f_dcd_rf1_mv_from_scr_b : out std_ulogic; --mffs + f_dcd_rf1_mtfsbx_b : out std_ulogic; --fpscr set bit, reset bit + f_dcd_rf1_mcrfs_b : out std_ulogic; --move fpscr field to cr and reset exceptions + f_dcd_rf1_mtfsf_b : out std_ulogic; --move fpr data to fpscr + f_dcd_rf1_mtfsfi_b : out std_ulogic; --move immediate data to fpscr + f_dcd_rf1_thread_b : out std_ulogic_vector(0 to 3); + f_dcd_rf1_sto_dp : out std_ulogic ; + f_dcd_rf1_sto_sp : out std_ulogic ; + f_dcd_rf1_sto_wd : out std_ulogic ; + f_dcd_rf1_log2e_b : out std_ulogic ; + f_dcd_rf1_pow2e_b : out std_ulogic ; + f_dcd_rf1_ftdiv : out std_ulogic ; + f_dcd_rf1_ftsqrt : out std_ulogic ; + f_dcd_rf1_mad_act : out std_ulogic ; + f_dcd_rf1_sto_act : out std_ulogic ; + f_dcd_ex6_cancel : out std_ulogic ; + f_dcd_rf1_bypsel_a_res0 : out std_ulogic; + f_dcd_rf1_bypsel_a_load0 : out std_ulogic; + f_dcd_rf1_bypsel_b_res0 : out std_ulogic; + f_dcd_rf1_bypsel_b_load0 : out std_ulogic; + f_dcd_rf1_bypsel_c_res0 : out std_ulogic; + f_dcd_rf1_bypsel_c_load0 : out std_ulogic; + f_dcd_rf0_bypsel_a_res1 : out std_ulogic; + f_dcd_rf0_bypsel_b_res1 : out std_ulogic; + f_dcd_rf0_bypsel_c_res1 : out std_ulogic; + f_dcd_rf0_bypsel_s_res1 : out std_ulogic; + f_dcd_rf0_bypsel_a_load1 : out std_ulogic; + f_dcd_rf0_bypsel_b_load1 : out std_ulogic; + f_dcd_rf0_bypsel_c_load1 : out std_ulogic; + f_dcd_rf0_bypsel_s_load1 : out std_ulogic; + f_dcd_ex1_perr_force_c : out std_ulogic; + f_dcd_ex1_perr_fsel_ovrd : out std_ulogic; + + -- Slow SPR Bus + slowspr_val_in : in std_ulogic; + slowspr_rw_in : in std_ulogic; + slowspr_etid_in : in std_ulogic_vector(0 to 1); + slowspr_addr_in : in std_ulogic_vector(0 to 9); + slowspr_data_in : in std_ulogic_vector(64-(2**regmode) to 63); + slowspr_done_in : in std_ulogic; + slowspr_val_out : out std_ulogic; + slowspr_rw_out : out std_ulogic; + slowspr_etid_out : out std_ulogic_vector(0 to 1); + slowspr_addr_out : out std_ulogic_vector(0 to 9); + slowspr_data_out : out std_ulogic_vector(64-(2**regmode) to 63); + slowspr_done_out : out std_ulogic; + -- DBG + pc_fu_trace_bus_enable : in std_ulogic; + pc_fu_event_bus_enable : in std_ulogic; + pc_fu_debug_mux_ctrls : in std_ulogic_vector(0 to 15); + pc_fu_event_count_mode : in std_ulogic_vector(0 to 2); + pc_fu_event_mux_ctrls : in std_ulogic_vector(0 to 31); + debug_data_in : in std_ulogic_vector(0 to 87); + debug_data_out : out std_ulogic_vector(0 to 87); + trace_triggers_in : in std_ulogic_vector(0 to 11); + trace_triggers_out : out std_ulogic_vector(0 to 11); + fu_pc_event_data : out std_ulogic_vector(0 to 7); + -- RAM + f_rnd_ex6_res_expo : in std_ulogic_vector (1 to 13); + f_rnd_ex6_res_frac : in std_ulogic_vector (0 to 52); + f_rnd_ex6_res_sign : in std_ulogic ; + pc_fu_ram_mode : in std_ulogic; + pc_fu_ram_thread : in std_ulogic_vector(0 to 1); + fu_pc_ram_done : out std_ulogic; + fu_pc_ram_data : out std_ulogic_vector(0 to 63); + -- Parity + f_sto_ex2_s_parity_check : in std_ulogic; + f_mad_ex2_a_parity_check : in std_ulogic; + f_mad_ex2_b_parity_check : in std_ulogic; + f_mad_ex2_c_parity_check : in std_ulogic; + fu_pc_err_regfile_parity : out std_ulogic_vector(0 to 3); + fu_pc_err_regfile_ue : out std_ulogic_vector(0 to 3); + fu_xu_ex3_regfile_err_det : out std_ulogic_vector(0 to 3); + xu_fu_regfile_seq_beg : in std_ulogic; + fu_xu_regfile_seq_end : out std_ulogic; + fu_xu_ex2_async_block : out std_ulogic_vector(0 to 3); + + xu_fu_msr_fp : in std_ulogic_vector(0 to 3); + xu_fu_msr_pr : in std_ulogic_vector(0 to 3); + xu_fu_msr_gs : in std_ulogic_vector(0 to 3); + pc_fu_instr_trace_mode : in std_ulogic; + pc_fu_instr_trace_tid : in std_ulogic_vector(0 to 1); + + ------------------------------------------------ + f_dcd_ex6_frt_addr : out std_ulogic_vector(0 to 5); + f_dcd_ex6_frt_tid : out std_ulogic_vector(0 to 1); + f_dcd_ex5_frt_tid : out std_ulogic_vector(0 to 1); + f_dcd_ex6_frt_wen : out std_ulogic; + fu_xu_ex2_store_data_val : out std_ulogic; + fu_xu_ex4_cr : out std_ulogic_vector(0 to 3); + fu_xu_ex4_cr_val : out std_ulogic_vector(0 to 3); + fu_xu_ex4_cr_bf : out std_ulogic_vector(0 to 2); + fu_xu_ex4_cr_noflush : out std_ulogic_vector(0 to 3); + ------------------------------------------------ + f_scr_ex7_fx_thread0 : in std_ulogic_vector(0 to 3); + f_scr_ex7_fx_thread1 : in std_ulogic_vector(0 to 3); + f_scr_ex7_fx_thread2 : in std_ulogic_vector(0 to 3); + f_scr_ex7_fx_thread3 : in std_ulogic_vector(0 to 3); + f_dcd_rf0_tid : out std_ulogic_vector(0 to 1); + f_dcd_rf0_fra : out std_ulogic_vector(0 to 5); + f_dcd_rf0_frb : out std_ulogic_vector(0 to 5); + f_dcd_rf0_frc : out std_ulogic_vector(0 to 5); + f_dcd_rf1_div_beg : out std_ulogic; -- save NAN and other special + f_dcd_rf1_sqrt_beg : out std_ulogic; -- + f_dcd_rf1_uc_ft_pos : out std_ulogic; + f_dcd_rf1_uc_ft_neg : out std_ulogic; + f_dcd_rf1_uc_fa_pos : out std_ulogic; + f_dcd_rf1_uc_fc_pos : out std_ulogic; + f_dcd_rf1_uc_fb_pos : out std_ulogic; + f_dcd_rf1_uc_fc_hulp : out std_ulogic; + f_dcd_rf1_uc_fc_0_5 : out std_ulogic; + f_dcd_rf1_uc_fc_1_0 : out std_ulogic; + f_dcd_rf1_uc_fc_1_minus : out std_ulogic; + f_dcd_rf1_uc_fb_1_0 : out std_ulogic; + f_dcd_rf1_uc_fb_0_75 : out std_ulogic; + f_dcd_rf1_uc_fb_0_5 : out std_ulogic; + f_dcd_ex2_uc_inc_lsb : out std_ulogic; + f_dcd_rf1_uc_mid : out std_ulogic; + f_dcd_rf1_uc_end : out std_ulogic; + fu_iu_uc_special : out std_ulogic_vector(0 to 3); + f_dcd_rf1_uc_special : out std_ulogic; + f_dcd_ex2_uc_gs_v : out std_ulogic; + f_dcd_ex2_uc_gs : out std_ulogic_vector(0 to 1); + f_dcd_ex2_uc_vxsnan : out std_ulogic; + f_dcd_ex2_uc_zx : out std_ulogic; + f_dcd_ex2_uc_vxidi : out std_ulogic; + f_dcd_ex2_uc_vxzdz : out std_ulogic; + f_dcd_ex2_uc_vxsqrt : out std_ulogic; + f_mad_ex6_uc_sign : in std_ulogic; + f_mad_ex6_uc_zero : in std_ulogic; + f_mad_ex3_uc_special : in std_ulogic; + f_mad_ex3_uc_vxsnan : in std_ulogic; + f_mad_ex3_uc_zx : in std_ulogic; + f_mad_ex3_uc_vxidi : in std_ulogic; + f_mad_ex3_uc_vxzdz : in std_ulogic; + f_mad_ex3_uc_vxsqrt : in std_ulogic; + f_mad_ex3_uc_res_sign : in std_ulogic; + f_mad_ex3_uc_round_mode : in std_ulogic_vector(0 to 1); + + ------------------------------------------------ + f_ex2_b_den_flush : in std_ulogic; + xu_fu_ex3_eff_addr : in std_ulogic_vector(59 to 63); + fu_xu_ex3_n_flush : out std_ulogic_vector(0 to 3); + fu_xu_ex3_np1_flush : out std_ulogic_vector(0 to 3); + fu_xu_ex3_ap_int_req : out std_ulogic_vector(0 to 3); + fu_xu_ex3_flush2ucode : out std_ulogic_vector(0 to 3); + fu_xu_ex2_instr_type : out std_ulogic_vector(0 to 11); + fu_xu_ex2_instr_match : out std_ulogic_vector(0 to 3); + fu_xu_ex2_is_ucode : out std_ulogic_vector(0 to 3); + fu_xu_ex3_trap : out std_ulogic_vector(0 to 3); + fu_xu_ex2_ifar_val : out std_ulogic_vector(0 to 3); + fu_xu_ex2_ifar_issued : out std_ulogic_vector(0 to 3); + fu_xu_ex1_ifar : out std_ulogic_vector(62-eff_ifar to 61) + ------------------------------------------------ +); + -- synopsys translate_off + + -- synopsys translate_on + +end fuq_dcd; + +architecture fuq_dcd of fuq_dcd is + +-- ###################### CONSTANTS ###################### -- + + + +-- ####################### SIGNALS ####################### -- +signal tilo : std_ulogic; +signal tihi : std_ulogic; +signal tilo_out : std_ulogic; +signal tihi_out : std_ulogic; + +signal thold_0 : std_ulogic; +signal thold_0_b : std_ulogic; +signal sg_0 : std_ulogic; +signal forcee : std_ulogic; +signal cfg_sl_thold_0 : std_ulogic; +signal cfg_sl_thold_0_b : std_ulogic; +signal cfg_sl_force : std_ulogic; +signal func_slp_sl_thold_0 : std_ulogic; +signal func_slp_sl_force : std_ulogic; +signal func_slp_sl_thold_0_b : std_ulogic; + +signal rf0_str_v : std_ulogic; +signal rf0_ldst_valid : std_ulogic_vector(0 to 3); +signal rf0_str_tag : std_ulogic_vector(0 to 1); +signal rf0_instr_valid : std_ulogic_vector(0 to 3); +signal rf0_instr_fra : std_ulogic_vector(0 to 5); +signal rf0_instr_frb : std_ulogic_vector(0 to 5); +signal rf0_instr_frc : std_ulogic_vector(0 to 5); +signal rf0_instr_frs : std_ulogic_vector(0 to 5); +signal rf0_instr_frt : std_ulogic_vector(0 to 5); +signal rf0_instr_tid_1hot : std_ulogic_vector(0 to 3); +signal thread_id_rf0 : std_ulogic_vector(0 to 3); +signal rf0_thread_so, rf0_thread_si :std_ulogic_vector(0 to 3); +signal rf0_tid : std_ulogic_vector(0 to 1); +signal rf0_bypsel : std_ulogic_vector(0 to 5); +signal rf0_bypsel_a_res0 : std_ulogic; +signal rf0_bypsel_b_res0 : std_ulogic; +signal rf0_bypsel_c_res0 : std_ulogic; +signal rf0_bypsel_a_load0 : std_ulogic; +signal rf0_bypsel_b_load0 : std_ulogic; +signal rf0_bypsel_c_load0 : std_ulogic; +signal rf0_bypsel_a_res1 : std_ulogic; +signal rf0_bypsel_b_res1 : std_ulogic; +signal rf0_bypsel_s_res1 : std_ulogic; +signal rf0_bypsel_c_res1 : std_ulogic; +signal rf0_bypsel_a_load1 : std_ulogic; +signal rf0_bypsel_b_load1 : std_ulogic; +signal rf0_bypsel_c_load1 : std_ulogic; +signal rf0_bypsel_s_load1 : std_ulogic; +signal rf0_instr_match : std_ulogic; +signal rf0_is_ucode : std_ulogic; +signal rf0_frs_byp : std_ulogic; + +signal xu_ex5_flush_int : std_ulogic_vector(0 to 3); + +signal ex5_reload_val_b : std_ulogic_vector(0 to 3); + +signal rf1_v : std_ulogic; +signal rf1_axu_v : std_ulogic; +signal rf1_instr_v : std_ulogic_vector(0 to 3); +signal rf1_tid : std_ulogic_vector(0 to 1); +signal rf1_instr_valid : std_ulogic_vector(0 to 3); +signal rf1_instr : std_ulogic_vector(0 to 31); +signal rf1_instr_fra_v : std_ulogic; +signal rf1_instr_frb_v : std_ulogic; +signal rf1_instr_frc_v : std_ulogic; +signal rf1_instr_frt : std_ulogic_vector(0 to 5); +signal rf1_instr_fra : std_ulogic_vector(0 to 5); +signal rf1_instr_frb : std_ulogic_vector(0 to 5); +signal rf1_instr_frc : std_ulogic_vector(0 to 5); +signal rf1_instr_frs : std_ulogic_vector(0 to 5); +signal rf1_instr_ifar : std_ulogic_vector(62-eff_ifar to 61); +signal rf1_str_v : std_ulogic; +signal rf1_ldst_v : std_ulogic_vector(0 to 3); +signal rf1_ldst_valid : std_ulogic_vector(0 to 3); +signal rf1_str_tag : std_ulogic_vector(0 to 1); +signal rf1_bypsel_a_res0 : std_ulogic; +signal rf1_bypsel_b_res0 : std_ulogic; +signal rf1_bypsel_c_res0 : std_ulogic; +signal rf1_bypsel_a_load0 : std_ulogic; +signal rf1_bypsel_b_load0 : std_ulogic; +signal rf1_bypsel_c_load0 : std_ulogic; +signal rf1_bypsel_a_res1 : std_ulogic; +signal rf1_bypsel_b_res1 : std_ulogic; +signal rf1_bypsel_c_res1 : std_ulogic; +signal rf1_bypsel_a_load1 : std_ulogic; +signal rf1_bypsel_b_load1 : std_ulogic; +signal rf1_bypsel_c_load1 : std_ulogic; +signal rf1_frs_byp : std_ulogic; + +signal rf1_primary : std_ulogic_vector(0 to 5); +signal rf1_sec_xform : std_ulogic_vector(0 to 9); +signal rf1_sec_aform : std_ulogic_vector(0 to 4); +signal rf1_dp : std_ulogic; +signal rf1_sp : std_ulogic; +signal rf1_dporsp : std_ulogic; +signal rf1_fcfid : std_ulogic; +signal rf1_fcfidu : std_ulogic; +signal rf1_fcfids : std_ulogic; +signal rf1_fcfidus : std_ulogic; +signal rf1_fcfiwu : std_ulogic; +signal rf1_fcfiwus : std_ulogic; +signal rf1_fctid : std_ulogic; +signal rf1_fctidu : std_ulogic; +signal rf1_fctidz : std_ulogic; +signal rf1_fctiduz : std_ulogic; +signal rf1_frim : std_ulogic; +signal rf1_frin : std_ulogic; +signal rf1_frip : std_ulogic; +signal rf1_friz : std_ulogic; +signal rf1_frsp : std_ulogic; +signal rf1_fmr : std_ulogic; +signal rf1_fneg : std_ulogic; +signal rf1_fabs : std_ulogic; +signal rf1_fnabs : std_ulogic; +signal rf1_fsel : std_ulogic; +signal rf1_frsqrte : std_ulogic; +signal rf1_fres : std_ulogic; +signal rf1_fctiw : std_ulogic; +signal rf1_fctiwu : std_ulogic; +signal rf1_fctiwz : std_ulogic; +signal rf1_fctiwuz : std_ulogic; +signal rf1_fcmpu : std_ulogic; +signal rf1_fcmpo : std_ulogic; +signal rf1_fcpsgn : std_ulogic; +signal rf1_fadd : std_ulogic; +signal rf1_fsub : std_ulogic; +signal rf1_fmul : std_ulogic; +signal rf1_fmadd : std_ulogic; +signal rf1_fmsub : std_ulogic; +signal rf1_fnmadd : std_ulogic; +signal rf1_fnmsub : std_ulogic; +signal rf1_mffs : std_ulogic; +signal rf1_mcrfs : std_ulogic; +signal rf1_mtfsfi : std_ulogic; +signal rf1_mtfsf : std_ulogic; +signal rf1_mtfsb0 : std_ulogic; +signal rf1_mtfsb1 : std_ulogic; +signal rf1_cr_val : std_ulogic; +signal ex1_cr_val_din : std_ulogic; +signal rf1_record : std_ulogic; +signal rf1_moves : std_ulogic; +signal rf1_to_ints : std_ulogic; +signal rf1_from_ints : std_ulogic; +signal rf1_fpscr_moves : std_ulogic; +signal rf1_mtfsb_bt : std_ulogic_vector(0 to 3); +signal rf1_mtfs_bf : std_ulogic_vector(0 to 7); +signal rf1_mcrfs_bfa : std_ulogic_vector(0 to 7); +signal rf1_mtfsf_nib : std_ulogic_vector(0 to 7); +signal rf1_mtfsf_l : std_ulogic; +signal rf1_mtfsf_w : std_ulogic; +signal rf1_fpscr_bit_data : std_ulogic_vector(0 to 3); +signal rf1_fpscr_bit_mask : std_ulogic_vector(0 to 3); +signal rf1_fpscr_nib_mask : std_ulogic_vector(0 to 8); +signal rf1_loge : std_ulogic; +signal rf1_expte : std_ulogic; +signal rf1_ftdiv : std_ulogic; +signal rf1_ftsqrt : std_ulogic; +signal rf1_rnd0 : std_ulogic; +signal rf1_rnd1 : std_ulogic; +signal rf1_kill_wen : std_ulogic; +signal rf1_instr_match : std_ulogic; +signal rf1_is_ucode : std_ulogic; +signal rf1_prenorm : std_ulogic; +signal rf1_div_beg : std_ulogic; +signal rf1_sqrt_beg : std_ulogic; +signal rf1_divsqrt_beg : std_ulogic; +signal rf1_fra_v : std_ulogic; +signal rf1_frb_v : std_ulogic; +signal rf1_frc_v : std_ulogic; +signal rf1_byp_a : std_ulogic; +signal rf1_byp_b : std_ulogic; +signal rf1_byp_c : std_ulogic; +signal rf1_uc_end : std_ulogic; +signal f_dcd_rf1_uc_fa_dis_par : std_ulogic; +signal f_dcd_rf1_uc_fb_dis_par : std_ulogic; +signal f_dcd_rf1_uc_fc_dis_par : std_ulogic; + +signal ex1_v : std_ulogic; +signal ex1_axu_v : std_ulogic; +signal ex1_instr_v : std_ulogic_vector(0 to 3); +signal ex1_instr_valid : std_ulogic_vector(0 to 3); +signal ex1_instr_frt : std_ulogic_vector(0 to 5); +signal ex1_str_v : std_ulogic; +signal ex1_str_valid : std_ulogic; +signal ex1_ldst_v : std_ulogic_vector(0 to 3); +signal ex1_ldst_valid : std_ulogic_vector(0 to 3); +signal ex1_instr_ifar : std_ulogic_vector(62-eff_ifar to 61); +signal ex1_cr_val : std_ulogic; +signal ex1_record : std_ulogic; +signal ex1_kill_wen : std_ulogic; +signal ex1_mcrfs : std_ulogic; +signal ex1_instr_match : std_ulogic; +signal ex1_is_ucode : std_ulogic; +signal ex1_divsqrt_beg : std_ulogic; +signal ex1_ifar_val : std_ulogic_vector(0 to 3); +signal ex1_fra_v : std_ulogic; +signal ex1_frb_v : std_ulogic; +signal ex1_frc_v : std_ulogic; +signal ex1_fra_valid : std_ulogic; +signal ex1_frb_valid : std_ulogic; +signal ex1_frc_valid : std_ulogic; +signal ex1_frs_byp : std_ulogic; +signal ex1_async_block : std_ulogic_vector(0 to 3); + +signal ex2_axu_v : std_ulogic; +signal ex2_instr_v : std_ulogic_vector(0 to 3); +signal ex2_instr_valid : std_ulogic_vector(0 to 3); +signal ex2_instr_frt : std_ulogic_vector(0 to 5); +signal ex2_cr_val : std_ulogic; +signal ex2_record : std_ulogic; +signal ex2_kill_wen : std_ulogic; +signal ex2_mcrfs : std_ulogic; +signal ex2_instr_match : std_ulogic; +signal ex2_is_ucode : std_ulogic; +signal ex2_ifar_val : std_ulogic_vector(0 to 3); +signal ex2_iu_n_flush : std_ulogic_vector(0 to 3); +signal ex2_fra_v : std_ulogic; +signal ex2_frb_v : std_ulogic; +signal ex2_frc_v : std_ulogic; +signal ex2_sto_perr : std_ulogic_vector(0 to 3); +signal ex2_abc_perr : std_ulogic_vector(0 to 3); +signal ex2_fpr_perr : std_ulogic_vector(0 to 3); +signal ex2_ldst_v : std_ulogic_vector(0 to 3); +signal ex2_str_v : std_ulogic; +signal ex2_fu_or_ldst_v : std_ulogic_vector(0 to 3); +signal ex2_n_flush : std_ulogic_vector(0 to 3); +signal ex2_flush2ucode : std_ulogic_vector(0 to 3); +signal ex2_frs_byp : std_ulogic; +signal ex2_async_block : std_ulogic_vector(0 to 3); + +signal ex3_instr_v : std_ulogic_vector(0 to 3); +signal ex3_instr_valid : std_ulogic_vector(0 to 3); +signal ex3_instr_frt : std_ulogic_vector(0 to 5); +signal ex3_cr_val : std_ulogic; +signal ex3_record : std_ulogic; +signal ex3_b_den_flush : std_ulogic; +signal ex4_b_den_flush_din : std_ulogic; +signal ex3_kill_wen : std_ulogic; +signal ex3_mcrfs : std_ulogic; +signal ex3_instr_match : std_ulogic; +signal ex3_is_ucode : std_ulogic; +signal ex3_n_flush : std_ulogic_vector(0 to 3); +signal ex3_flush2ucode : std_ulogic_vector(0 to 3); + +signal ex4_instr_v : std_ulogic_vector(0 to 3); +signal ex4_instr_valid : std_ulogic_vector(0 to 3); +signal ex4_instr_tid : std_ulogic_vector(0 to 1); +signal ex4_instr_frt : std_ulogic_vector(0 to 5); +signal ex5_instr_frt_din : std_ulogic_vector(0 to 5); +signal ex4_cr_val, ex4_cr_val_cp, ex4_cr_val_cp_b : std_ulogic; +signal ex4_fpcc_x_b, ex7_cr_fld_x_b :std_ulogic_vector(0 to 3); +signal ex4_record : std_ulogic; +signal ex4_kill_wen : std_ulogic; +signal ex4_mcrfs : std_ulogic; +signal ex4_is_ucode : std_ulogic; +signal ex4_b_den_flush : std_ulogic; +signal ex4_uc_special : std_ulogic; + +signal ex5_instr_valid_din : std_ulogic_vector(0 to 3); +signal ex5_instr_v : std_ulogic_vector(0 to 3); +signal ex5_instr_valid : std_ulogic_vector(0 to 3); +signal ex5_instr_bypval : std_ulogic_vector(0 to 3); +signal ex5_instr_tid : std_ulogic_vector(0 to 1); +signal ex5_instr_frt : std_ulogic_vector(0 to 5); +signal ex5_record_din : std_ulogic; +signal ex5_mcrfs_din : std_ulogic; +signal ex5_record : std_ulogic; +signal ex5_mcrfs : std_ulogic; +signal ex5_is_ucode : std_ulogic; +signal ex5_instr_flush : std_ulogic; +signal ex5_cr_val_din : std_ulogic; +signal ex5_cr_val : std_ulogic; +signal ex5_kill_wen_din : std_ulogic; +signal ex5_kill_wen : std_ulogic; +signal ex6_instr_valid_din : std_ulogic_vector(0 to 3); + +signal ex6_instr_v : std_ulogic_vector(0 to 3); +signal ex6_instr_valid : std_ulogic; +signal ex6_instr_tid : std_ulogic_vector(0 to 1); +signal ex6_instr_frt : std_ulogic_vector(0 to 5); +signal ex6_record : std_ulogic; +signal ex6_record_v : std_ulogic_vector(0 to 3); +signal ex6_bf : std_ulogic_vector(0 to 2); +signal ex6_mcrfs : std_ulogic; +signal ex6_is_ucode : std_ulogic; +signal ex6_is_fixperr : std_ulogic; +signal ex6_record_din : std_ulogic; +signal ex6_mcrfs_din : std_ulogic; +signal ex6_cr_val_din : std_ulogic; +signal ex6_cr_val : std_ulogic; +signal ex6_kill_wen : std_ulogic; +signal ex6_kill_wen_din : std_ulogic; + +signal ex7_record_v : std_ulogic_vector(0 to 3); +signal ex7_bf : std_ulogic_vector(0 to 2); + +signal rf1_uc_op_rnd_v : std_ulogic; +signal rf1_uc_op_rnd : std_ulogic_vector(0 to 1); + +signal ex1_instr_frs : std_ulogic_vector(0 to 5); +signal ex1_instr_fra : std_ulogic_vector(0 to 5); +signal ex1_instr_frb : std_ulogic_vector(0 to 5); +signal ex1_instr_frc : std_ulogic_vector(0 to 5); +signal ex1_perr_si, ex1_perr_so : std_ulogic_vector(0 to 23); +signal ex2_instr_frs : std_ulogic_vector(0 to 5); +signal ex2_instr_fra : std_ulogic_vector(0 to 5); +signal ex2_instr_frb : std_ulogic_vector(0 to 5); +signal ex2_instr_frc : std_ulogic_vector(0 to 5); +signal ex2_perr_si, ex2_perr_so : std_ulogic_vector(0 to 23); +signal ex2_f0a_perr : std_ulogic; +signal ex2_f0c_perr : std_ulogic; +signal ex2_f1b_perr : std_ulogic; +signal ex2_f1s_perr : std_ulogic; +signal perr_sm_ns : std_ulogic_vector(0 to 2); +signal perr_sm_si, perr_sm_so : std_ulogic_vector(0 to 2); +signal perr_sm_din : std_ulogic_vector(0 to 2); +signal perr_sm_l2 : std_ulogic_vector(0 to 2); +signal perr_ctl_si, perr_ctl_so : std_ulogic_vector(0 to 24); +signal perr_addr_din : std_ulogic_vector(0 to 5); +signal perr_addr_l2 : std_ulogic_vector(0 to 5); +signal perr_tid_din : std_ulogic_vector(0 to 3); +signal perr_tid_l2 : std_ulogic_vector(0 to 3); +signal perr_tid_enc : std_ulogic_vector(0 to 1); +signal new_perr_sm_instr_v : std_ulogic; +signal rf0_perr_sm_instr_v : std_ulogic; +signal rf0_perr_sm_instr_v_b : std_ulogic; +signal rf0_frc_perr_x_b : std_ulogic_vector(0 to 5); +signal rf0_frc_iu_x_b : std_ulogic_vector(0 to 5); +signal rf0_frb_perr_x_b : std_ulogic_vector(0 to 5); +signal rf0_frb_iu_x_b : std_ulogic_vector(0 to 5); +signal rf0_tid_perr_x_b : std_ulogic_vector(0 to 1); +signal rf0_tid_iu_x_b : std_ulogic_vector(0 to 1); +signal rf1_perr_sm_instr_v : std_ulogic; +signal ex1_perr_sm_instr_v : std_ulogic; +signal ex2_perr_sm_instr_v : std_ulogic; +signal ex3_perr_sm_instr_v : std_ulogic; +signal ex4_perr_sm_instr_v : std_ulogic; +signal ex5_perr_sm_instr_v : std_ulogic; +signal perr_move_f0_to_f1 : std_ulogic; +signal perr_move_f1_to_f0 : std_ulogic; +signal perr_move_f0_to_f1_l2 : std_ulogic; +signal perr_move_f1_to_f0_l2 : std_ulogic; +signal rf0_perr_move_f0_to_f1 : std_ulogic; +signal rf0_perr_move_f1_to_f0 : std_ulogic; +signal rf0_perr_force_c : std_ulogic; +signal rf1_perr_force_c : std_ulogic; +signal ex1_perr_force_c : std_ulogic; +signal regfile_seq_beg : std_ulogic; +signal regfile_seq_end : std_ulogic; +signal ex2_regfile_err_det : std_ulogic; +signal ex3_regfile_err_det : std_ulogic_vector(0 to 3); +signal rf0_regfile_ue : std_ulogic; +signal rf0_regfile_ce : std_ulogic; +signal rf1_regfile_ue : std_ulogic; +signal rf1_regfile_ce : std_ulogic; +signal ex4_eff_addr : std_ulogic_vector(59 to 63); +signal err_regfile_parity : std_ulogic_vector(0 to 3); +signal err_regfile_ue : std_ulogic_vector(0 to 3); + +signal slowspr_in_val : std_ulogic; +signal slowspr_in_rw : std_ulogic; +signal slowspr_in_etid : std_ulogic_vector(0 to 1); +signal slowspr_in_addr : std_ulogic_vector(0 to 9); +signal slowspr_in_data : std_ulogic_vector(64-(2**regmode) to 63); +signal slowspr_in_done : std_ulogic; +signal slowspr_out_val : std_ulogic; +signal slowspr_out_rw : std_ulogic; +signal slowspr_out_etid : std_ulogic_vector(0 to 1); +signal slowspr_out_addr : std_ulogic_vector(0 to 9); +signal slowspr_out_data : std_ulogic_vector(64-(2**regmode) to 63); +signal slowspr_out_done : std_ulogic; +signal axucr0_dec : std_ulogic; +signal axucr0_rd : std_ulogic; +signal axucr0_wr : std_ulogic; +signal axucr0_din : std_ulogic_vector(61 to 63); +signal axucr0_q : std_ulogic_vector(61 to 63); +signal debug_data_d : std_ulogic_vector(0 to 87); +signal debug_data_q : std_ulogic_vector(0 to 87); +signal debug_trig_d : std_ulogic_vector(0 to 11); +signal debug_trig_q : std_ulogic_vector(0 to 11); +signal debug_mux_ctrls_q : std_ulogic_vector(0 to 15); +signal debug_mux_ctrls_muxed : std_ulogic_vector(0 to 15); + +signal trace_data_in : std_ulogic_vector(0 to 87); +signal trigger_data_in : std_ulogic_vector(0 to 11); +signal dbg_group0 : std_ulogic_vector(0 to 87); +signal dbg_group1 : std_ulogic_vector(0 to 87); +signal dbg_group2 : std_ulogic_vector(0 to 87); +signal dbg_group3 : std_ulogic_vector(0 to 87); +signal trg_group0 : std_ulogic_vector(0 to 11); +signal trg_group1 : std_ulogic_vector(0 to 11); +signal trg_group2 : std_ulogic_vector(0 to 11); +signal trg_group3 : std_ulogic_vector(0 to 11); +signal trigger_data_out : std_ulogic_vector(0 to 11); +signal trace_data_out : std_ulogic_vector(0 to 87); +signal uc_hooks_debug : std_ulogic_vector(0 to 55); + +signal t0_events : std_ulogic_vector(0 to 7); +signal t1_events : std_ulogic_vector(0 to 7); +signal t2_events : std_ulogic_vector(0 to 7); +signal t3_events : std_ulogic_vector(0 to 7); +signal t0_events_in : std_ulogic_vector(0 to 7); +signal t1_events_in : std_ulogic_vector(0 to 7); +signal t2_events_in : std_ulogic_vector(0 to 7); +signal t3_events_in : std_ulogic_vector(0 to 7); +signal evnt_axu_instr_cmt : std_ulogic_vector(0 to 3); +signal evnt_axu_cr_cmt : std_ulogic_vector(0 to 3); +signal evnt_axu_idle : std_ulogic_vector(0 to 3); +signal evnt_div_sqrt_ip : std_ulogic_vector(0 to 3); +signal evnt_denrm_flush : std_ulogic_vector(0 to 3); +signal evnt_uc_instr_cmt : std_ulogic_vector(0 to 3); +signal event_data_d : std_ulogic_vector(0 to 7); +signal event_data_q : std_ulogic_vector(0 to 7); +signal evnt_fpu_fex : std_ulogic_vector(0 to 3); +signal evnt_fpu_fx : std_ulogic_vector(0 to 3); +signal event_en_d : std_ulogic_vector(0 to 3); +signal event_en_q : std_ulogic_vector(0 to 3); +signal event_count_mode_q : std_ulogic_vector(0 to 2); +signal msr_pr_q : std_ulogic_vector(0 to 3); +signal msr_gs_q : std_ulogic_vector(0 to 3); +signal instr_trace_mode_q : std_ulogic; +signal instr_trace_tid_q : std_ulogic_vector(0 to 1); + +signal rf1_instr_iss : std_ulogic_vector(0 to 3); +signal ex1_instr_iss : std_ulogic_vector(0 to 3); +signal ex2_instr_iss : std_ulogic_vector(0 to 3); + +signal ex6_ram_sign : std_ulogic; +signal ex6_ram_frac : std_ulogic_vector(0 to 52); +signal ex6_ram_expo : std_ulogic_vector(3 to 13); +signal ex6_ram_done : std_ulogic; +signal ex7_ram_done : std_ulogic; +signal ex7_ram_sign : std_ulogic; +signal ex7_ram_frac : std_ulogic_vector(0 to 52); +signal ex7_ram_expo : std_ulogic_vector(3 to 13); +signal ex7_ram_data : std_ulogic_vector(0 to 63); + +signal rf1_iu_si, rf1_iu_so : std_ulogic_vector(0 to 14); +signal rf1_frt_si, rf1_frt_so : std_ulogic_vector(0 to 31); +signal uc_hooks_rc_rf0 : std_ulogic; +signal dbg0_act : std_ulogic; +signal event_act : std_ulogic; + +signal SPARE_L2 : std_ulogic_vector(0 to 23); + +signal act_lat_si, act_lat_so : std_ulogic_vector(0 to 2); +signal rf1_ifr_si, rf1_ifr_so : std_ulogic_vector(62-eff_ifar to 61); +signal rf1_instl_si, rf1_instl_so : std_ulogic_vector(0 to 31); +signal rf1_byp_si, rf1_byp_so : std_ulogic_vector(0 to 11); +signal ex1_ctl_si, ex1_ctl_so : std_ulogic_vector(0 to 7); +signal ex1_frt_si, ex1_frt_so : std_ulogic_vector(0 to 17); +signal ex1_ifar_si, ex1_ifar_so : std_ulogic_vector(62-eff_ifar to 61); +signal ex2_ctl_si, ex2_ctl_so : std_ulogic_vector(0 to 15); +signal ex2_ctlng_si, ex2_ctlng_so : std_ulogic_vector(0 to 16); +signal ex3_ctlng_si, ex3_ctlng_so : std_ulogic_vector(0 to 15); +signal ex3_ctl_si, ex3_ctl_so : std_ulogic_vector(0 to 12); +signal ex4_ctl_si, ex4_ctl_so : std_ulogic_vector(0 to 15); +signal ex5_ctl_si, ex5_ctl_so : std_ulogic_vector(0 to 14); +signal ex6_ctl_si, ex6_ctl_so : std_ulogic_vector(0 to 15); +signal ex7_ctl_si, ex7_ctl_so : std_ulogic_vector(0 to 6); +signal spr_ctl_si, spr_ctl_so : std_ulogic_vector(0 to 14); +signal spr_data_si, spr_data_so : std_ulogic_vector(64-(2**regmode) to 63); +signal ram_data_si, ram_data_so : std_ulogic_vector(0 to 64); +signal ram_datav_si, ram_datav_so : std_ulogic_vector(0 to 0); +signal perf_data_si, perf_data_so : std_ulogic_vector(0 to 38); +signal dbg0_data_si, dbg0_data_so : std_ulogic_vector(0 to 115); +signal dbg1_data_si, dbg1_data_so : std_ulogic_vector(0 to 4); +signal spare_si, spare_so : std_ulogic_vector(0 to 23); +signal f_ucode_si, f_ucode_so : std_ulogic; +signal axucr0_lat_si, axucr0_lat_so : std_ulogic_vector(0 to 2); + +signal cfg_slat_d2clk : std_ulogic; +signal cfg_slat_lclk : clk_logic; + + +signal ex2_store_valid , ex2_stdv_si, ex2_stdv_so : std_ulogic; +signal msr_fp : std_ulogic; +signal msr_fp_raw : std_ulogic; +signal msr_fp_act : std_ulogic; + +signal perr_sm_running : std_ulogic; + +signal spare_unused : std_ulogic_vector(0 to 10); + + + + + signal ex5_iflush_int_b, ex5_iflush_b :std_ulogic_vector(0 to 3); + signal ex5_iflush_01, ex5_iflush_23, ex5_instr_flush_b :std_ulogic; + + + +---------------------------------------------------------------- +begin + + + tilo <= '0'; + tihi <= '1'; + fu_buf_up: tihi_out <= tihi; + fu_buf_dn: tilo_out <= tilo; + +------------------------------------------------------------------------ +-- Pervasive + + thold_reg_0: tri_plat generic map (expand_type => expand_type, width => 3) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => thold_1, + din(1) => cfg_sl_thold_1, + din(2) => func_slp_sl_thold_1, + q(0) => thold_0, + q(1) => cfg_sl_thold_0, + q(2) => func_slp_sl_thold_0 ); + + sg_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => sg_1 , + q(0) => sg_0 ); + + + lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map ( + clkoff_b => clkoff_b, + thold => thold_0, + sg => sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => thold_0_b ); + + cfg_sl_lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map ( + clkoff_b => clkoff_b, + thold => cfg_sl_thold_0, + sg => sg_0, + act_dis => act_dis, + forcee => cfg_sl_force, + thold_b => cfg_sl_thold_0_b ); + + func_slp_sl_lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map ( + clkoff_b => clkoff_b, + thold => func_slp_sl_thold_0, + sg => sg_0, + act_dis => act_dis, + forcee => func_slp_sl_force, + thold_b => func_slp_sl_thold_0_b ); + +------------------------------------------------------------------------ +-- Act Latches + + msr_fp <= or_reduce(xu_fu_msr_fp(0 to 3)); + + act_lat: tri_rlmreg_p generic map (init => 0, expand_type => expand_type, width => 3) port map ( + nclk => nclk, + act => tihi, + forcee => forcee, + delay_lclkr => delay_lclkr(9), + mpw1_b => mpw1_b(9), + mpw2_b => mpw2_b(1), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => act_lat_si(0 to 2), + scout => act_lat_so(0 to 2), + din(0) => pc_fu_trace_bus_enable, + din(1) => pc_fu_event_bus_enable, + din(2) => msr_fp, + dout(0) => dbg0_act , + dout(1) => event_act , + dout(2) => msr_fp_raw); + + msr_fp_act <= msr_fp_raw or not axucr0_q(63); + + f_dcd_msr_fp_act <= msr_fp_act; + +------------------------------------------------------------------------ +-- RF0 + + + rf0_str_tag(0 to 1) <= iu_fu_rf0_ldst_tag(0 to 1); + + rf0_ldst_valid(0) <= iu_fu_rf0_ldst_val and not xu_rf0_flush(0) and iu_fu_rf0_ldst_tid(0 to 1) = "00"; + rf0_ldst_valid(1) <= iu_fu_rf0_ldst_val and not xu_rf0_flush(1) and iu_fu_rf0_ldst_tid(0 to 1) = "01"; + rf0_ldst_valid(2) <= iu_fu_rf0_ldst_val and not xu_rf0_flush(2) and iu_fu_rf0_ldst_tid(0 to 1) = "10"; + rf0_ldst_valid(3) <= iu_fu_rf0_ldst_val and not xu_rf0_flush(3) and iu_fu_rf0_ldst_tid(0 to 1) = "11"; + + rf0_str_v <= iu_fu_rf0_str_val; + + rf0_instr_match <= iu_fu_rf0_instr_match; + rf0_is_ucode <= iu_fu_rf0_is_ucode; + + rf0_tid(0 to 1) <= iu_fu_rf0_tid(0 to 1); + rf0_instr_tid_1hot(0) <= (rf0_tid(0 to 1) = "00") and iu_fu_rf0_instr_v; + rf0_instr_tid_1hot(1) <= (rf0_tid(0 to 1) = "01") and iu_fu_rf0_instr_v; + rf0_instr_tid_1hot(2) <= (rf0_tid(0 to 1) = "10") and iu_fu_rf0_instr_v; + rf0_instr_tid_1hot(3) <= (rf0_tid(0 to 1) = "11") and iu_fu_rf0_instr_v; + + rf0_instr_valid(0 to 3) <= rf0_instr_tid_1hot(0 to 3) and not xu_rf0_flush(0 to 3); + + rf0_thread_lat: tri_rlmreg_p generic map (init => 0, expand_type => expand_type, width => 4) port map ( + nclk => nclk, + act => msr_fp_act, + forcee => forcee, + delay_lclkr => delay_lclkr(8), + mpw1_b => mpw1_b(8), + mpw2_b => mpw2_b(1), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => rf0_thread_si(0 to 3), + scout => rf0_thread_so(0 to 3), + din(0 to 3) => iu_fu_is2_tid_decode(0 to 3), + dout(0 to 3) => thread_id_rf0(0 to 3) ) ; + + + rf0_instr_frt(0 to 5) <= iu_fu_rf0_frt(1 to 6); -- bit0 unused + rf0_instr_fra(0 to 5) <= iu_fu_rf0_fra(1 to 6); -- bit0 unused + rf0_instr_frb(0 to 5) <= iu_fu_rf0_frb(1 to 6); -- bit0 unused + rf0_instr_frc(0 to 5) <= iu_fu_rf0_frc(1 to 6); -- bit0 unused + rf0_instr_frs(0 to 5) <= iu_fu_rf0_ldst_tag(3 to 8); + + ------------------------------------------------------------------------ + -- Bypass Writethru Detect + + -- 000000 <= FPR lev0 + -- 100000 <= EX6 load bypass into A lev1 + -- 010000 <= EX6 load bypass into c lev1 + -- 001000 <= EX6 load bypass into B lev1 + -- 000100 <= EX6 bypass into A lev1 + -- 000010 <= EX6 bypass into c lev1 + -- 000001 <= EX6 bypass into B lev1 + + rf0_bypsel(0 to 5) <= iu_fu_rf0_bypsel(0 to 5); + + rf0_bypsel_a_res0 <= rf0_bypsel(3) and or_reduce(ex5_instr_bypval(0 to 3)); + rf0_bypsel_c_res0 <= rf0_bypsel(4) and or_reduce(ex5_instr_bypval(0 to 3)); + rf0_bypsel_b_res0 <= rf0_bypsel(5) and or_reduce(ex5_instr_bypval(0 to 3)); + + rf0_bypsel_a_res1 <= (ex6_instr_tid(0 to 1) & ex6_instr_frt(0 to 5)) = (rf0_tid(0 to 1) & rf0_instr_fra(0 to 5)) and + (ex6_instr_valid and not ex6_kill_wen) and iu_fu_rf0_fra_v and not rf0_bypsel_a_res0 and not rf0_bypsel_a_load0; + rf0_bypsel_c_res1 <= (ex6_instr_tid(0 to 1) & ex6_instr_frt(0 to 5)) = (rf0_tid(0 to 1) & rf0_instr_frc(0 to 5)) and + (ex6_instr_valid and not ex6_kill_wen) and iu_fu_rf0_frc_v and not rf0_bypsel_c_res0 and not rf0_bypsel_c_load0; + rf0_bypsel_b_res1 <= (ex6_instr_tid(0 to 1) & ex6_instr_frt(0 to 5)) = (rf0_tid(0 to 1) & rf0_instr_frb(0 to 5)) and + (ex6_instr_valid and not ex6_kill_wen) and iu_fu_rf0_frb_v and not rf0_bypsel_b_res0 and not rf0_bypsel_b_load0; + + rf0_bypsel_s_res1 <= (ex6_instr_tid(0 to 1) & ex6_instr_frt(0 to 5)) = (iu_fu_rf0_ldst_tid(0 to 1) & rf0_instr_frs(0 to 5)) and + (ex6_instr_valid and not ex6_kill_wen) and rf0_str_v; + + rf0_bypsel_a_load0 <= rf0_bypsel(0); + rf0_bypsel_c_load0 <= rf0_bypsel(1); + rf0_bypsel_b_load0 <= rf0_bypsel(2); + + rf0_bypsel_a_load1 <= (f_fpr_ex7_load_addr(0 to 7) ) = (rf0_tid(0 to 1) & rf0_instr_fra(0 to 5)) and f_fpr_ex7_load_v and iu_fu_rf0_fra_v and not rf0_bypsel_a_load0 and not rf0_bypsel_a_res0; + rf0_bypsel_c_load1 <= (f_fpr_ex7_load_addr(0 to 7) ) = (rf0_tid(0 to 1) & rf0_instr_frc(0 to 5)) and f_fpr_ex7_load_v and iu_fu_rf0_frc_v and not rf0_bypsel_c_load0 and not rf0_bypsel_c_res0; + rf0_bypsel_b_load1 <= (f_fpr_ex7_load_addr(0 to 7) ) = (rf0_tid(0 to 1) & rf0_instr_frb(0 to 5)) and f_fpr_ex7_load_v and iu_fu_rf0_frb_v and not rf0_bypsel_b_load0 and not rf0_bypsel_b_res0; + rf0_bypsel_s_load1 <= (f_fpr_ex7_load_addr(0 to 7) ) = (iu_fu_rf0_ldst_tid(0 to 1) & rf0_instr_frs(0 to 5)) and f_fpr_ex7_load_v and rf0_str_v; + + f_dcd_rf0_bypsel_a_res1 <= rf0_bypsel_a_res1; + f_dcd_rf0_bypsel_b_res1 <= rf0_bypsel_b_res1; + f_dcd_rf0_bypsel_c_res1 <= rf0_bypsel_c_res1; + f_dcd_rf0_bypsel_a_load1 <= rf0_bypsel_a_load1; + f_dcd_rf0_bypsel_b_load1 <= rf0_bypsel_b_load1; + f_dcd_rf0_bypsel_c_load1 <= rf0_bypsel_c_load1; + + f_dcd_rf0_bypsel_s_res1 <= rf0_bypsel_s_res1; + f_dcd_rf0_bypsel_s_load1 <= rf0_bypsel_s_load1; + + rf0_frs_byp <= rf0_bypsel_s_res1 or rf0_bypsel_s_load1; + +------------------------------------------------------------------------ +-- RF1 + + -- Latches + rf1_iu: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 15) + port map (nclk => nclk, + act => tihi, + forcee => forcee, + delay_lclkr => delay_lclkr(0), + mpw1_b => mpw1_b(0), + mpw2_b => mpw2_b(0), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => rf1_iu_si(0 to 14), + scout => rf1_iu_so(0 to 14), + --------------------------------------------- + din(0) => iu_fu_rf0_fra_v, + din(1) => iu_fu_rf0_frb_v, + din(2) => iu_fu_rf0_frc_v, + din(3 to 6) => rf0_instr_valid(0 to 3), + din(7 to 10) => rf0_ldst_valid(0 to 3), + din(11 to 12) => rf0_str_tag(0 to 1), + din(13) => rf0_str_v, + din(14) => rf0_frs_byp, + --------------------------------------------- + dout(0) => rf1_instr_fra_v, + dout(1) => rf1_instr_frb_v, + dout(2) => rf1_instr_frc_v, + dout(3 to 6) => rf1_instr_v(0 to 3), + dout(7 to 10) => rf1_ldst_v(0 to 3), + dout(11 to 12) => rf1_str_tag(0 to 1), + dout(13) => rf1_str_v, + dout(14) => rf1_frs_byp + --------------------------------------------- + ); + rf1_frt: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 32) + port map (nclk => nclk, + act => msr_fp_act, + forcee => forcee, + delay_lclkr => delay_lclkr(0), + mpw1_b => mpw1_b(0), + mpw2_b => mpw2_b(0), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => rf1_frt_si(0 to 31), + scout => rf1_frt_so(0 to 31), + din( 0 to 5) => rf0_instr_frt(0 to 5) , + din( 6 to 11) => rf0_instr_fra(0 to 5) , + din(12 to 17) => rf0_instr_frb(0 to 5) , + din(18 to 23) => rf0_instr_frc(0 to 5) , + din(24 to 29) => rf0_instr_frs(0 to 5) , + din(30) => rf0_instr_match , + din(31) => rf0_is_ucode , + --------------------------------------------- + dout( 0 to 5) => rf1_instr_frt(0 to 5) , + dout( 6 to 11) => rf1_instr_fra(0 to 5) , + dout(12 to 17) => rf1_instr_frb(0 to 5) , + dout(18 to 23) => rf1_instr_frc(0 to 5) , + dout(24 to 29) => rf1_instr_frs(0 to 5) , + dout(30) => rf1_instr_match , + dout(31) => rf1_is_ucode + --------------------------------------------- + ); + rf1_ifr: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => eff_ifar) + port map (nclk => nclk, + act => tihi, + forcee => forcee, + delay_lclkr => delay_lclkr(0), + mpw1_b => mpw1_b(0), + mpw2_b => mpw2_b(0), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => rf1_ifr_si, + scout => rf1_ifr_so, + din => iu_fu_rf0_ifar, + dout => rf1_instr_ifar ); + rf1_instl: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 32) + port map (nclk => nclk, + act => msr_fp_act, + forcee => forcee, + delay_lclkr => delay_lclkr(0), + mpw1_b => mpw1_b(0), + mpw2_b => mpw2_b(0), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => rf1_instl_si(0 to 31), + scout => rf1_instl_so(0 to 31), + din(0 to 30) => iu_fu_rf0_instr(0 to 30), + din(31) => uc_hooks_rc_rf0, -- uc_hooks sometimes alters rc bit (iu_fu_rf0_instr(31) + dout => rf1_instr(0 to 31) ); + rf1_byp: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 12) + port map (nclk => nclk, + act => msr_fp_act, + forcee => forcee, + delay_lclkr => delay_lclkr(0), + mpw1_b => mpw1_b(0), + mpw2_b => mpw2_b(0), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => rf1_byp_si(0 to 11), + scout => rf1_byp_so(0 to 11), + din(0) => rf0_bypsel_a_res0, + din(1) => rf0_bypsel_c_res0, + din(2) => rf0_bypsel_b_res0, + din(3) => rf0_bypsel_a_res1, + din(4) => rf0_bypsel_c_res1, + din(5) => rf0_bypsel_b_res1, + din(6) => rf0_bypsel_a_load0, + din(7) => rf0_bypsel_c_load0, + din(8) => rf0_bypsel_b_load0, + din(9) => rf0_bypsel_a_load1, + din(10) => rf0_bypsel_c_load1, + din(11) => rf0_bypsel_b_load1, + --------------------------------------------- + dout(0) => rf1_bypsel_a_res0, + dout(1) => rf1_bypsel_c_res0, + dout(2) => rf1_bypsel_b_res0, + dout(3) => rf1_bypsel_a_res1, + dout(4) => rf1_bypsel_c_res1, + dout(5) => rf1_bypsel_b_res1, + dout(6) => rf1_bypsel_a_load0, + dout(7) => rf1_bypsel_c_load0, + dout(8) => rf1_bypsel_b_load0, + dout(9) => rf1_bypsel_a_load1, + dout(10) => rf1_bypsel_c_load1, + dout(11) => rf1_bypsel_b_load1 + --------------------------------------------- + ); + + -- Flushes + rf1_instr_valid(0 to 3) <= rf1_instr_v(0 to 3) and not xu_rf1_flush(0 to 3); + rf1_ldst_valid(0 to 3) <= rf1_ldst_v(0 to 3) and not xu_rf1_flush(0 to 3); + + fu_xu_rf1_act(0 to 3) <= rf1_instr_v(0 to 3); + + rf1_tid(0) <= rf1_instr_v(2) or rf1_instr_v(3); + rf1_tid(1) <= rf1_instr_v(1) or rf1_instr_v(3); + + --------------------------------------------------------------------- + -- Decode IOP + + rf1_primary(0 to 5) <= rf1_instr(0 to 5); + rf1_sec_xform(0 to 9) <= rf1_instr(21 to 30); + rf1_sec_aform(0 to 4) <= rf1_instr(26 to 30); + rf1_v <= rf1_instr_v(0) or rf1_instr_v(1) or rf1_instr_v(2) or rf1_instr_v(3); + rf1_axu_v <= rf1_v or rf1_ldst_v(0) or rf1_ldst_v(1) or rf1_ldst_v(2) or rf1_ldst_v(3) or rf1_perr_sm_instr_v; + rf1_dp <= (rf1_primary(0 to 5) = "111111") and rf1_v and not rf1_perr_sm_instr_v; + rf1_sp <= (rf1_primary(0 to 5) = "111011") and rf1_v and not rf1_perr_sm_instr_v; + rf1_dporsp <= rf1_dp or rf1_sp; + + rf1_fabs <= rf1_dp and (rf1_sec_xform(0 to 9) = "0100001000"); + rf1_fadd <= rf1_dporsp and (rf1_sec_aform(0 to 4) = "10101"); + rf1_fcfid <= rf1_dp and (rf1_sec_xform(0 to 9) = "1101001110"); + rf1_fcfidu <= rf1_dp and (rf1_sec_xform(0 to 9) = "1111001110"); + rf1_fcfids <= rf1_sp and (rf1_sec_xform(0 to 9) = "1101001110"); + rf1_fcfidus <= rf1_sp and (rf1_sec_xform(0 to 9) = "1111001110"); + rf1_fcfiwu <= rf1_dp and (rf1_sec_xform(0 to 9) = "0011001110"); + rf1_fcfiwus <= rf1_sp and (rf1_sec_xform(0 to 9) = "0011001110"); + rf1_fcmpo <= rf1_dp and (rf1_sec_xform(0 to 9) = "0000100000"); + rf1_fcmpu <= rf1_dp and (rf1_sec_xform(0 to 9) = "0000000000"); + rf1_fcpsgn <= rf1_dp and (rf1_sec_xform(0 to 9) = "0000001000"); + rf1_fctid <= rf1_dp and (rf1_sec_xform(0 to 9) = "1100101110"); + rf1_fctidu <= rf1_dp and (rf1_sec_xform(0 to 9) = "1110101110"); + rf1_fctidz <= rf1_dp and (rf1_sec_xform(0 to 9) = "1100101111"); + rf1_fctiduz <= rf1_dp and (rf1_sec_xform(0 to 9) = "1110101111"); + rf1_fctiw <= rf1_dp and (rf1_sec_xform(0 to 9) = "0000001110"); + rf1_fctiwu <= rf1_dp and (rf1_sec_xform(0 to 9) = "0010001110"); + rf1_fctiwz <= rf1_dp and (rf1_sec_xform(0 to 9) = "0000001111"); + rf1_fctiwuz <= rf1_dp and (rf1_sec_xform(0 to 9) = "0010001111"); + rf1_fmadd <= rf1_dporsp and (rf1_sec_aform(0 to 4) = "11101"); + rf1_fmr <= rf1_dp and (rf1_sec_xform(0 to 9) = "0001001000"); + rf1_fmsub <= rf1_dporsp and (rf1_sec_aform(0 to 4) = "11100"); + rf1_fmul <= rf1_dporsp and ((rf1_sec_aform(0 to 4) = "11001") or + (rf1_sec_aform(0 to 4) = "10001")); --This is for the last divide op + rf1_fnabs <= rf1_dp and (rf1_sec_xform(0 to 9) = "0010001000"); + rf1_fneg <= rf1_dp and (rf1_sec_xform(0 to 9) = "0000101000"); + rf1_fnmadd <= rf1_dporsp and (rf1_sec_aform(0 to 4) = "11111"); + rf1_fnmsub <= rf1_dporsp and (rf1_sec_aform(0 to 4) = "11110"); + rf1_fres <= rf1_dporsp and (rf1_sec_aform(0 to 4) = "11000"); + rf1_frim <= rf1_dp and (rf1_sec_xform(0 to 9) = "0111101000"); + rf1_frin <= rf1_dp and (rf1_sec_xform(0 to 9) = "0110001000"); + rf1_frip <= rf1_dp and (rf1_sec_xform(0 to 9) = "0111001000"); + rf1_friz <= rf1_dp and (rf1_sec_xform(0 to 9) = "0110101000"); + rf1_frsp <= rf1_dp and (rf1_sec_xform(0 to 9) = "0000001100"); + rf1_frsqrte <= rf1_dporsp and (rf1_sec_aform(0 to 4) = "11010"); + rf1_fsel <= (rf1_dp and (rf1_sec_aform(0 to 4) = "10111")) + or (not perr_sm_l2(0)); --perr state machine, don't update the fpscr, only move. + + rf1_fsub <= rf1_dporsp and (rf1_sec_aform(0 to 4) = "10100"); + rf1_mcrfs <= rf1_dp and (rf1_sec_xform(0 to 9) = "0001000000"); + rf1_mffs <= rf1_dp and (rf1_sec_xform(0 to 9) = "1001000111"); + rf1_mtfsb0 <= rf1_dp and (rf1_sec_xform(0 to 9) = "0001000110"); + rf1_mtfsb1 <= rf1_dp and (rf1_sec_xform(0 to 9) = "0000100110"); + rf1_mtfsf <= rf1_dp and (rf1_sec_xform(0 to 9) = "1011000111"); + rf1_mtfsfi <= rf1_dp and (rf1_sec_xform(0 to 9) = "0010000110"); + rf1_loge <= rf1_dporsp and (rf1_sec_xform(0 to 9) = "0011100101"); + rf1_expte <= rf1_dporsp and (rf1_sec_xform(0 to 9) = "0011000101"); + rf1_prenorm <= rf1_dporsp and (rf1_sec_xform(5 to 9) = "10000"); + + rf1_ftdiv <= rf1_dp and (rf1_sec_xform(0 to 9) = "0010000000"); + rf1_ftsqrt <= rf1_dp and (rf1_sec_xform(0 to 9) = "0010100000"); + + rf1_cr_val <= rf1_fcmpu or rf1_fcmpo; + rf1_record <= (rf1_dporsp and rf1_instr(31)) and not rf1_cr_val and not rf1_mcrfs + and not rf1_ftdiv and not rf1_ftsqrt; + + rf1_moves <= rf1_fmr or rf1_fabs or rf1_fnabs or rf1_fneg or rf1_fcpsgn ; + + rf1_to_ints <= rf1_fctid or rf1_fctidu or rf1_fctidz or rf1_fctiduz or + rf1_fctiw or rf1_fctiwu or rf1_fctiwz or rf1_fctiwuz; + rf1_from_ints <= rf1_fcfid or rf1_fcfidu or rf1_fcfids or rf1_fcfidus or + rf1_fcfiwu or rf1_fcfiwus; + rf1_fpscr_moves <= rf1_mtfsb0 or rf1_mtfsb1 or rf1_mtfsf or rf1_mtfsfi or rf1_mcrfs; + + rf1_kill_wen <= rf1_cr_val or rf1_fpscr_moves or rf1_ftdiv or rf1_ftsqrt; + + + -- rf1_instr_imm defs + -- mcrfs bf(0:2) - cr field + -- bfa(0:2) - nib_mask one-hot + -- mtfsfi bf(0:2) - fpscr field + -- U(0:3) - imm U is placed into fpscr field bf + -- mtfsf FLM(0:7) - nib mask, frb placed into fpscr + -- mtfsb0 BT(0:4) - bit BT of fpscr is set to 0 + -- mtfsb1 BT(0:4) - bit BT of fpscr is set to 1 + -- + rf1_mtfsb_bt(0) <= not rf1_instr(9) and not rf1_instr(10); --00 + rf1_mtfsb_bt(1) <= not rf1_instr(9) and rf1_instr(10); --01 + rf1_mtfsb_bt(2) <= rf1_instr(9) and not rf1_instr(10); --10 + rf1_mtfsb_bt(3) <= rf1_instr(9) and rf1_instr(10); --11 + + rf1_mtfs_bf(0) <= not rf1_instr(6) and not rf1_instr(7) and not rf1_instr(8); --000 + rf1_mtfs_bf(1) <= not rf1_instr(6) and not rf1_instr(7) and rf1_instr(8); --001 + rf1_mtfs_bf(2) <= not rf1_instr(6) and rf1_instr(7) and not rf1_instr(8); --010 + rf1_mtfs_bf(3) <= not rf1_instr(6) and rf1_instr(7) and rf1_instr(8); --011 + rf1_mtfs_bf(4) <= rf1_instr(6) and not rf1_instr(7) and not rf1_instr(8); --100 + rf1_mtfs_bf(5) <= rf1_instr(6) and not rf1_instr(7) and rf1_instr(8); --101 + rf1_mtfs_bf(6) <= rf1_instr(6) and rf1_instr(7) and not rf1_instr(8); --110 + rf1_mtfs_bf(7) <= rf1_instr(6) and rf1_instr(7) and rf1_instr(8); --111 + + rf1_mcrfs_bfa(0) <= not rf1_instr(11) and not rf1_instr(12) and not rf1_instr(13); --000 + rf1_mcrfs_bfa(1) <= not rf1_instr(11) and not rf1_instr(12) and rf1_instr(13); --001 + rf1_mcrfs_bfa(2) <= not rf1_instr(11) and rf1_instr(12) and not rf1_instr(13); --010 + rf1_mcrfs_bfa(3) <= not rf1_instr(11) and rf1_instr(12) and rf1_instr(13); --011 + rf1_mcrfs_bfa(4) <= rf1_instr(11) and not rf1_instr(12) and not rf1_instr(13); --100 + rf1_mcrfs_bfa(5) <= rf1_instr(11) and not rf1_instr(12) and rf1_instr(13); --101 + rf1_mcrfs_bfa(6) <= rf1_instr(11) and rf1_instr(12) and not rf1_instr(13); --110 + rf1_mcrfs_bfa(7) <= rf1_instr(11) and rf1_instr(12) and rf1_instr(13); --111 + + rf1_mtfsf_l <= rf1_instr(6); + rf1_mtfsf_w <= rf1_instr(15); + + + rf1_fpscr_bit_data(0 to 3) <= (rf1_instr(16 to 19) or (0 to 3 => rf1_mtfsb1)) and not + (0 to 3 => rf1_mtfsb0 or rf1_mtfsf or rf1_mcrfs); + + rf1_fpscr_bit_mask(0 to 3) <= rf1_mtfsb_bt(0 to 3) or + (0 to 3 => rf1_mtfsfi or rf1_mtfsf or rf1_mcrfs); + + rf1_fpscr_nib_mask(0 to 7) <= (rf1_mtfs_bf (0 to 7) and (0 to 7 => rf1_mtfsb1 or rf1_mtfsb0) ) or + (rf1_mtfs_bf (0 to 7) and (0 to 7 => rf1_mtfsfi and not rf1_mtfsf_w)) or + (rf1_mtfsf_nib(0 to 7) and (0 to 7 => rf1_mtfsf) ) or + (rf1_mcrfs_bfa(0 to 7) and (0 to 7 => rf1_mcrfs) ); + + + + rf1_mtfsf_nib(0 to 7) <= (rf1_instr(7 to 14) or (7 to 14 => rf1_mtfsf_l)) and not (0 to 7 => not rf1_mtfsf_l and rf1_mtfsf_w); + + rf1_fpscr_nib_mask(8) <= (rf1_mtfsfi and rf1_mtfsf_w and rf1_mtfs_bf(7)) or + (rf1_mtfsf and rf1_mtfsf_l ) or + (rf1_mtfsf and not rf1_mtfsf_l and rf1_mtfsf_w and rf1_instr(14)); + + f_dcd_rf1_fpscr_bit_data_b(0 to 3) <= not rf1_fpscr_bit_data(0 to 3); + f_dcd_rf1_fpscr_bit_mask_b(0 to 3) <= not rf1_fpscr_bit_mask(0 to 3); + f_dcd_rf1_fpscr_nib_mask_b(0 to 8) <= not rf1_fpscr_nib_mask(0 to 8); + + --------------------------------------------------------------------- + -- Outputs to Mad + + f_dcd_rf1_aop_valid <= rf1_instr_fra_v; + f_dcd_rf1_cop_valid <= rf1_instr_frc_v or + (not perr_sm_l2(0) and rf1_perr_sm_instr_v); --Reading out parity + f_dcd_rf1_bop_valid <= rf1_instr_frb_v or + (not perr_sm_l2(0) and rf1_perr_sm_instr_v); --Reading out parity + + f_dcd_rf1_sp <= rf1_sp and not (rf1_fcfids or rf1_fcfiwus or rf1_fcfidus); + f_dcd_rf1_emin_dp <= tilo; + f_dcd_rf1_emin_sp <= rf1_frsp; + f_dcd_rf1_force_pass_b <= not (rf1_fmr or rf1_fabs or rf1_fnabs or rf1_fneg or rf1_mtfsf or rf1_fcpsgn); + f_dcd_rf1_fsel_b <= not rf1_fsel; + f_dcd_rf1_from_integer_b <= not rf1_from_ints; + f_dcd_rf1_to_integer_b <= not (rf1_to_ints or rf1_frim or rf1_frin or rf1_frip or rf1_friz); + f_dcd_rf1_rnd_to_int_b <= not (rf1_frim or rf1_frin or rf1_frip or rf1_friz); + f_dcd_rf1_math_b <= not (rf1_fmul or rf1_fmadd or rf1_fmsub or rf1_fadd or rf1_fsub or rf1_fnmsub or rf1_fnmadd); + f_dcd_rf1_est_recip_b <= not rf1_fres; + f_dcd_rf1_est_rsqrt_b <= not rf1_frsqrte; + f_dcd_rf1_move_b <= not (rf1_moves); + f_dcd_rf1_prenorm_b <= not (rf1_prenorm); + f_dcd_rf1_frsp_b <= not rf1_frsp; + f_dcd_rf1_compare_b <= not rf1_cr_val; + f_dcd_rf1_ordered_b <= not rf1_fcmpo; + f_dcd_rf1_sp_conv_b <= not (rf1_fcfids or rf1_fcfidus or rf1_fcfiwus); + f_dcd_rf1_uns_b <= not (rf1_fcfidu or rf1_fcfidus or rf1_fcfiwu or rf1_fcfiwus or + rf1_fctidu or rf1_fctiduz or rf1_fctiwu or rf1_fctiwuz); + f_dcd_rf1_word_b <= not (rf1_fctiw or rf1_fctiwu or rf1_fctiwz or rf1_fctiwuz or + rf1_fcfiwu or rf1_fcfiwus); + f_dcd_rf1_sub_op_b <= not (rf1_fsub or rf1_fmsub or rf1_fnmsub or rf1_cr_val); + f_dcd_rf1_inv_sign_b <= not (rf1_fnmadd or rf1_fnmsub); + f_dcd_rf1_sign_ctl_b(0) <= not (rf1_fmr or rf1_fnabs); + f_dcd_rf1_sign_ctl_b(1) <= not (rf1_fneg or rf1_fnabs); + f_dcd_rf1_sgncpy_b <= not rf1_fcpsgn; + f_dcd_rf1_mv_to_scr_b <= not (rf1_mcrfs or rf1_mtfsf or rf1_mtfsfi or rf1_mtfsb0 or rf1_mtfsb1); + f_dcd_rf1_mv_from_scr_b <= not rf1_mffs; + f_dcd_rf1_mtfsbx_b <= not (rf1_mtfsb0 or rf1_mtfsb1); + f_dcd_rf1_mcrfs_b <= not rf1_mcrfs; + f_dcd_rf1_mtfsf_b <= not rf1_mtfsf; + f_dcd_rf1_mtfsfi_b <= not rf1_mtfsfi; + + f_dcd_rf1_mad_act <= rf1_v or rf1_perr_sm_instr_v; + + f_dcd_rf1_sto_act <= (rf1_ldst_v(0) or rf1_ldst_v(1) or rf1_ldst_v(2) or rf1_ldst_v(3)) and rf1_str_v; + + -- Force rounding mode. + -- 00 - round to nearest + -- 01 - round toward zero + -- 10 - round toward +Inf + -- 11 - round toward -Inf + rf1_rnd0 <= ((rf1_frim or rf1_frip) and not rf1_uc_op_rnd_v) or + (rf1_uc_op_rnd(0) and rf1_uc_op_rnd_v); + + rf1_rnd1 <= ((rf1_fctidz or rf1_fctiwz or rf1_fctiduz or rf1_fctiwuz or rf1_friz or rf1_frim) and not rf1_uc_op_rnd_v) or + (rf1_uc_op_rnd(1) and rf1_uc_op_rnd_v); + + + f_dcd_rf1_op_rnd_v_b <= not (rf1_fctidz or rf1_fctiwz or rf1_fctiduz or rf1_fctiwuz or + rf1_frim or rf1_frin or rf1_frip or rf1_friz or rf1_uc_op_rnd_v); + f_dcd_rf1_op_rnd_b(0 to 1) <= not (rf1_rnd0 & rf1_rnd1); + + f_dcd_rf1_thread_b(0 to 3) <= not rf1_instr_v(0 to 3); + + -- store_tag[0:1] + -- 00 store DP + -- 10 store SP + -- 11 store SP Word + f_dcd_rf1_sto_dp <= not rf1_str_tag(0); + f_dcd_rf1_sto_sp <= rf1_str_tag(0) and not rf1_str_tag(1); + f_dcd_rf1_sto_wd <= rf1_str_tag(0) and rf1_str_tag(1); + + f_dcd_rf1_log2e_b <= not rf1_loge; + f_dcd_rf1_pow2e_b <= not rf1_expte; + + f_dcd_rf1_ftdiv <= rf1_ftdiv; + f_dcd_rf1_ftsqrt <= rf1_ftsqrt; + + + -- Writethru Case, RF0 = EX6 + f_dcd_rf1_bypsel_a_res0 <= rf1_bypsel_a_res0 ; + f_dcd_rf1_bypsel_a_load0 <= rf1_bypsel_a_load0 ; + f_dcd_rf1_bypsel_b_res0 <= rf1_bypsel_b_res0 ; + f_dcd_rf1_bypsel_b_load0 <= rf1_bypsel_b_load0 ; + f_dcd_rf1_bypsel_c_res0 <= rf1_bypsel_c_res0 ; + f_dcd_rf1_bypsel_c_load0 <= rf1_bypsel_c_load0 ; + + + -- operand valids for parity checking + rf1_byp_a <= rf1_bypsel_a_res0 or rf1_bypsel_a_res1 or rf1_bypsel_a_load0 or rf1_bypsel_a_load1; + rf1_byp_b <= rf1_bypsel_b_res0 or rf1_bypsel_b_res1 or rf1_bypsel_b_load0 or rf1_bypsel_b_load1; + rf1_byp_c <= rf1_bypsel_c_res0 or rf1_bypsel_c_res1 or rf1_bypsel_c_load0 or rf1_bypsel_c_load1; + rf1_fra_v <= rf1_instr_fra_v and not rf1_byp_a and not f_dcd_rf1_uc_fa_dis_par; + rf1_frb_v <= rf1_instr_frb_v and not rf1_byp_b and not f_dcd_rf1_uc_fb_dis_par; + rf1_frc_v <= rf1_instr_frc_v and not rf1_byp_c and not f_dcd_rf1_uc_fc_dis_par and not rf1_uc_end; -- last sqrt mutiplies a const + +------------------------------------------------------------------------ +-- EX1 + + ex1_cr_val_din <= rf1_cr_val or rf1_ftdiv or rf1_ftsqrt; + + -- Latches + ex1_ctl: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 8) + port map (nclk => nclk, + act => tihi, + forcee => forcee, + delay_lclkr => delay_lclkr(1), + mpw1_b => mpw1_b(1), + mpw2_b => mpw2_b(0), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => ex1_ctl_si(0 to 7), + scout => ex1_ctl_so(0 to 7), + --------------------------------------------- + din(0 to 3) => rf1_instr_valid(0 to 3), + din(4 to 7) => rf1_ldst_valid(0 to 3), + --------------------------------------------- + dout(0 to 3) => ex1_instr_v(0 to 3), + dout(4 to 7) => ex1_ldst_v(0 to 3) + --------------------------------------------- + ); + + ex1_frt: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 18) + port map (nclk => nclk, + act => rf1_axu_v, + forcee => forcee, + delay_lclkr => delay_lclkr(1), + mpw1_b => mpw1_b(1), + mpw2_b => mpw2_b(0), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => ex1_frt_si(0 to 17), + scout => ex1_frt_so(0 to 17), + --------------------------------------------- + din(0 to 5) => rf1_instr_frt(0 to 5), + din( 6) => ex1_cr_val_din, + din( 7) => rf1_record, + din( 8) => rf1_kill_wen, + din( 9) => rf1_mcrfs, + din(10) => rf1_instr_match, + din(11) => rf1_is_ucode, + din(12) => rf1_divsqrt_beg, + din(13) => rf1_fra_v, + din(14) => rf1_frb_v, + din(15) => rf1_frc_v, + din(16) => rf1_str_v, + din(17) => rf1_frs_byp, + --------------------------------------------- + dout(0 to 5) => ex1_instr_frt(0 to 5), + dout(6) => ex1_cr_val, + dout(7) => ex1_record, + dout(8) => ex1_kill_wen, + dout(9) => ex1_mcrfs, + dout(10) => ex1_instr_match, + dout(11) => ex1_is_ucode, + dout(12) => ex1_divsqrt_beg, + dout(13) => ex1_fra_v, + dout(14) => ex1_frb_v, + dout(15) => ex1_frc_v, + dout(16) => ex1_str_v, + dout(17) => ex1_frs_byp + --------------------------------------------- + ); + ex1_ifar: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => eff_ifar) + port map (nclk => nclk, + act => rf1_v, + forcee => forcee, + delay_lclkr => delay_lclkr(1), + mpw1_b => mpw1_b(1), + mpw2_b => mpw2_b(0), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => ex1_ifar_si, + scout => ex1_ifar_so, + --------------------------------------------- + din => rf1_instr_ifar, + --------------------------------------------- + dout => ex1_instr_ifar + --------------------------------------------- + ); + + ex1_perr: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 24) + port map (nclk => nclk, + act => rf1_axu_v, + forcee => forcee, + delay_lclkr => delay_lclkr(1), + mpw1_b => mpw1_b(1), + mpw2_b => mpw2_b(0), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => ex1_perr_si(0 to 23), + scout => ex1_perr_so(0 to 23), + din( 0 to 5) => rf1_instr_frs(0 to 5) , + din( 6 to 11) => rf1_instr_fra(0 to 5) , + din(12 to 17) => rf1_instr_frb(0 to 5) , + din(18 to 23) => rf1_instr_frc(0 to 5) , + --------------------------------------------- + dout( 0 to 5) => ex1_instr_frs(0 to 5) , + dout( 6 to 11) => ex1_instr_fra(0 to 5) , + dout(12 to 17) => ex1_instr_frb(0 to 5) , + dout(18 to 23) => ex1_instr_frc(0 to 5) + --------------------------------------------- + ); + + -- Flushes + ex1_instr_valid(0 to 3) <= ex1_instr_v(0 to 3) and not xu_ex1_flush(0 to 3); + ex1_v <= ex1_instr_v(0) or ex1_instr_v(1) or ex1_instr_v(2) or ex1_instr_v(3); + ex1_axu_v <= ex1_v or ex1_ldst_v(0) or ex1_ldst_v(1) or ex1_ldst_v(2) or ex1_ldst_v(3); + + -- Loads/Stores + ex1_ldst_valid <= ex1_ldst_v(0 to 3) and not xu_ex1_flush(0 to 3); + + ex1_str_valid <= ex1_str_v and or_reduce(ex1_ldst_valid(0 to 3)); + ex1_fra_valid <= ex1_fra_v and or_reduce(ex1_instr_valid(0 to 3)); + ex1_frb_valid <= ex1_frb_v and or_reduce(ex1_instr_valid(0 to 3)); + ex1_frc_valid <= ex1_frc_v and or_reduce(ex1_instr_valid(0 to 3)); + + -- Completion to XU + ex1_ifar_val(0 to 3) <= ex1_instr_valid(0 to 3) and not (0 to 3 => ex1_divsqrt_beg); + + fu_xu_ex1_ifar <= ex1_instr_ifar; + + + -- Since we send out fex (fp enabled exception) in EX7, there is a chance that an async int + -- can occur after it completed, but before completion knows about the fex. In this case, + -- we need to block async interupts for the window between them. + + -- The window is actally EX4-EX6, we slide it up a few cycles so XU can latch it, and use + -- it in EX3. XU only uses this block when FE0/FE1 are asserted (FP exceptions enabled) + ex1_async_block(0 to 3) <= ex1_instr_v(0 to 3) or -- for safety + ex2_instr_v(0 to 3) or -- EX4 + ex3_instr_v(0 to 3) or -- EX5 + ex4_instr_v(0 to 3) or -- EX6 + ex5_instr_v(0 to 3) ; -- for safety + +------------------------------------------------------------------------ +-- EX2 + + -- Latches + ex2_ctlng_lat: tri_rlmreg_p generic map (init => 0, expand_type => expand_type, width => 17) port map ( + nclk => nclk, + act => tihi, + forcee => forcee, + delay_lclkr => delay_lclkr(2), + mpw1_b => mpw1_b(2), + mpw2_b => mpw2_b(0), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => ex2_ctlng_si(0 to 16), + scout => ex2_ctlng_so(0 to 16), + --------------------------------------------- + din( 0 to 3) => ex1_instr_valid(0 to 3), + din( 4 to 7) => ex1_ifar_val(0 to 3), + din( 8 to 11) => ex1_ldst_valid(0 to 3), + din(12 to 15) => ex1_async_block(0 to 3), + din(16) => ex1_str_valid, + --------------------------------------------- + dout( 0 to 3) => ex2_instr_v(0 to 3), + dout( 4 to 7) => ex2_ifar_val(0 to 3), + dout( 8 to 11) => ex2_ldst_v(0 to 3), + dout(12 to 15) => ex2_async_block(0 to 3), + dout(16) => ex2_str_v + --------------------------------------------- + ); + + ex2_ctl_lat: tri_rlmreg_p generic map (init => 0, expand_type => expand_type, width => 16) port map ( + nclk => nclk, + act => ex1_axu_v, + forcee => forcee, + delay_lclkr => delay_lclkr(2), + mpw1_b => mpw1_b(2), + mpw2_b => mpw2_b(0), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => ex2_ctl_si(0 to 15), + scout => ex2_ctl_so(0 to 15), + --------------------------------------------- + din(0 to 5) => ex1_instr_frt(0 to 5), + din(6) => ex1_cr_val, + din(7) => ex1_record, + din(8) => ex1_kill_wen, + din(9) => ex1_mcrfs, + din(10) => ex1_instr_match, + din(11) => ex1_is_ucode, + din(12) => ex1_fra_valid, + din(13) => ex1_frb_valid, + din(14) => ex1_frc_valid, + din(15) => ex1_frs_byp, + --------------------------------------------- + dout(0 to 5) => ex2_instr_frt(0 to 5), + dout(6) => ex2_cr_val, + dout(7) => ex2_record, + dout(8) => ex2_kill_wen, + dout(9) => ex2_mcrfs, + dout(10) => ex2_instr_match, + dout(11) => ex2_is_ucode, + dout(12) => ex2_fra_v, + dout(13) => ex2_frb_v, + dout(14) => ex2_frc_v, + dout(15) => ex2_frs_byp + --------------------------------------------- + ); + + + ex2_stdv_lat: tri_rlmreg_p generic map (init => 0, expand_type => expand_type, width => 1) port map ( + nclk => nclk, + act => tihi, + forcee => forcee, + delay_lclkr => delay_lclkr(2), + mpw1_b => mpw1_b(2), + mpw2_b => mpw2_b(0), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin(0) => ex2_stdv_si, + scout(0) => ex2_stdv_so, + --------------------------------------------- + din(0) => ex1_str_valid, + dout(0) => ex2_store_valid ); + + + + ex2_perr: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 24) + port map (nclk => nclk, + act => ex1_axu_v, + forcee => forcee, + delay_lclkr => delay_lclkr(2), + mpw1_b => mpw1_b(2), + mpw2_b => mpw2_b(0), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => ex2_perr_si(0 to 23), + scout => ex2_perr_so(0 to 23), + din( 0 to 5) => ex1_instr_frs(0 to 5) , + din( 6 to 11) => ex1_instr_fra(0 to 5) , + din(12 to 17) => ex1_instr_frb(0 to 5) , + din(18 to 23) => ex1_instr_frc(0 to 5) , + --------------------------------------------- + dout( 0 to 5) => ex2_instr_frs(0 to 5) , + dout( 6 to 11) => ex2_instr_fra(0 to 5) , + dout(12 to 17) => ex2_instr_frb(0 to 5) , + dout(18 to 23) => ex2_instr_frc(0 to 5) + --------------------------------------------- + ); + + + -- Parity Checking + ex2_sto_perr(0 to 3) <= (0 to 3 => f_sto_ex2_s_parity_check and ex2_str_v and not ex2_frs_byp) and ex2_ldst_v(0 to 3); + + ex2_abc_perr(0 to 3) <= (0 to 3 => (f_mad_ex2_a_parity_check and ex2_fra_v) or + (f_mad_ex2_b_parity_check and ex2_frb_v) or + (f_mad_ex2_c_parity_check and ex2_frc_v) ) and ex2_instr_v(0 to 3); + + ex2_fpr_perr(0 to 3) <= (ex2_sto_perr(0 to 3) or ex2_abc_perr(0 to 3)) and not xu_ex2_flush(0 to 3) and (0 to 3 => msr_fp_act); + + ex2_regfile_err_det <= or_reduce((ex2_sto_perr(0 to 3) or ex2_abc_perr(0 to 3)) and not xu_ex2_flush(0 to 3)) and msr_fp_act; + + ex2_f0a_perr <= f_mad_ex2_a_parity_check and ex2_fra_v ; + ex2_f0c_perr <= f_mad_ex2_c_parity_check and (ex2_frc_v or (perr_sm_l2(1) and ex2_perr_sm_instr_v) ); + ex2_f1b_perr <= f_mad_ex2_b_parity_check and (ex2_frb_v or (perr_sm_l2(1) and ex2_perr_sm_instr_v) ); + ex2_f1s_perr <= f_sto_ex2_s_parity_check and ex2_str_v ; + + -- Flushes + ex2_instr_valid(0 to 3) <= ex2_instr_v(0 to 3) and not xu_ex2_flush(0 to 3); + + -- Outputs + fu_xu_ex2_store_data_val <= ex2_store_valid; + + -- Outputs + fu_xu_ex2_ifar_val(0 to 3) <= ex2_ifar_val(0 to 3); + fu_xu_ex2_ifar_issued(0 to 3) <= ex2_instr_iss(0 to 3); + + fu_xu_ex2_instr_type(0 to 11) <= tilo_out & tilo_out & tihi_out & + tilo_out & tilo_out & tihi_out & + tilo_out & tilo_out & tihi_out & + tilo_out & tilo_out & tihi_out ; + + fu_xu_ex2_instr_match(0 to 3) <= (0 to 3 => ex2_instr_match); + fu_xu_ex2_is_ucode(0 to 3) <= (0 to 3 => ex2_is_ucode); + + fu_xu_ex2_async_block(0 to 3) <= ex2_async_block(0 to 3); + + -- The n flush for next cycle + -- The N flush can come from either an FU instruction, or a load in the XU pipe + ex2_fu_or_ldst_v(0 to 3) <= (ex2_instr_v(0 to 3) or ex2_ldst_v(0 to 3)) and not xu_ex2_flush(0 to 3); + + ex2_iu_n_flush(0 to 3) <= iu_fu_ex2_n_flush(0 to 3) and ex2_fu_or_ldst_v(0 to 3); + + ex2_n_flush(0 to 3) <= (ex2_instr_valid(0 to 3) and (0 to 3 => f_ex2_b_den_flush)) or + ex2_iu_n_flush(0 to 3) ; + + ex2_axu_v <= or_reduce(ex2_instr_v(0 to 3) or ex2_ldst_v(0 to 3)); + + -- flush2ucode + ex2_flush2ucode(0 to 3) <= ex2_instr_v(0 to 3) and (0 to 3 => f_ex2_b_den_flush) and not ex2_iu_n_flush(0 to 3) and not xu_ex2_flush(0 to 3); + + +------------------------------------------------------------------------ +-- EX3 + + -- Latches + ex3_ctlng: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 16) + port map (nclk => nclk, + act => tihi, + forcee => forcee, + delay_lclkr => delay_lclkr(3), + mpw1_b => mpw1_b(3), + mpw2_b => mpw2_b(0), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => ex3_ctlng_si(0 to 15), + scout => ex3_ctlng_so(0 to 15), + --------------------------------------------- + din( 0 to 3) => ex2_instr_valid(0 to 3), + din( 4 to 7) => ex2_n_flush(0 to 3), + din( 8 to 11) => ex2_flush2ucode(0 to 3), + din(12 to 15) => ex2_fpr_perr(0 to 3), + --------------------------------------------- + dout( 0 to 3) => ex3_instr_v(0 to 3), + dout( 4 to 7) => ex3_n_flush(0 to 3), + dout( 8 to 11) => ex3_flush2ucode(0 to 3), + dout(12 to 15) => ex3_regfile_err_det(0 to 3) + --------------------------------------------- + ); + + ex3_ctl: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 13) + port map (nclk => nclk, + act => ex2_axu_v, + forcee => forcee, + delay_lclkr => delay_lclkr(3), + mpw1_b => mpw1_b(3), + mpw2_b => mpw2_b(0), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => ex3_ctl_si(0 to 12), + scout => ex3_ctl_so(0 to 12), + --------------------------------------------- + din(0 to 5) => ex2_instr_frt(0 to 5), + din(6) => ex2_cr_val, + din(7) => ex2_record, + din(8) => f_ex2_b_den_flush, + din(9) => ex2_kill_wen, + din(10) => ex2_mcrfs, + din(11) => ex2_instr_match, + din(12) => ex2_is_ucode, + --------------------------------------------- + dout(0 to 5) => ex3_instr_frt(0 to 5), + dout(6) => ex3_cr_val, + dout(7) => ex3_record, + dout(8) => ex3_b_den_flush, + dout(9) => ex3_kill_wen, + dout(10) => ex3_mcrfs, + dout(11) => ex3_instr_match, + dout(12) => ex3_is_ucode + --------------------------------------------- + ); + + + -- Flushes + ex3_instr_valid(0 to 3) <= ex3_instr_v(0 to 3) and not xu_ex3_flush(0 to 3) and (0 to 3 => msr_fp_act); + + + -- Outputs + + fu_xu_ex3_n_flush(0 to 3) <= ex3_n_flush(0 to 3) ; + + + fu_xu_ex3_np1_flush(0 to 3) <= tilo_out & tilo_out & tilo_out & tilo_out; + fu_xu_ex3_ap_int_req(0 to 3) <= tilo_out & tilo_out & tilo_out & tilo_out; + + fu_xu_ex3_flush2ucode(0 to 3) <= ex3_flush2ucode; + + + fu_xu_ex3_trap(0 to 3) <= (f_scr_ex7_fx_thread0(1) & f_scr_ex7_fx_thread1(1) & + f_scr_ex7_fx_thread2(1) & f_scr_ex7_fx_thread3(1) ) ; + + fu_xu_ex3_regfile_err_det(0 to 3) <= ex3_regfile_err_det(0 to 3); + +------------------------------------------------------------------------ +-- EX4 + + -- Latches + ex4_ctl_lat: tri_rlmreg_p generic map (init => 0, expand_type => expand_type, width => 16) port map ( + nclk => nclk, + act => tihi, + forcee => forcee, + delay_lclkr => delay_lclkr(4), + mpw1_b => mpw1_b(4), + mpw2_b => mpw2_b(0), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => ex4_ctl_si, + scout => ex4_ctl_so, + --------------------------------------------- + din(0 to 3) => ex3_instr_valid(0 to 3), + din(4 to 9) => ex3_instr_frt(0 to 5), + din(10) => ex3_cr_val, + din(11) => ex3_cr_val, + din(12) => ex3_record, + din(13) => ex3_kill_wen, + din(14) => ex3_mcrfs, + din(15) => ex3_is_ucode, + --------------------------------------------- + dout(0 to 3) => ex4_instr_v(0 to 3), + dout(4 to 9) => ex4_instr_frt(0 to 5), + dout(10) => ex4_cr_val, + dout(11) => ex4_cr_val_cp, + dout(12) => ex4_record, + dout(13) => ex4_kill_wen, + dout(14) => ex4_mcrfs, + dout(15) => ex4_is_ucode + --------------------------------------------- + ); + + + + ex4_cr_val_cp_b <= not( ex4_cr_val_cp) ; + + u_cr_o1: ex7_cr_fld_x_b(0 to 3) <= not( f_scr_ex7_cr_fld (0 to 3) and (0 to 3 => ex4_cr_val_cp_b) ); + u_cr_o2: ex4_fpcc_x_b(0 to 3) <= not( f_add_ex4_fpcc_iu(0 to 3) and (0 to 3 => ex4_cr_val_cp) ); + u_cr_o: fu_xu_ex4_cr(0 to 3) <= not( ex4_fpcc_x_b(0 to 3) and ex7_cr_fld_x_b(0 to 3) ); + + + + + -- Flushes + ex4_instr_valid(0 to 3) <= ex4_instr_v(0 to 3) and not xu_ex4_flush(0 to 3); + + fu_xu_ex4_cr_val <= (ex4_instr_v (0 to 3) and (0 to 3 => ex4_cr_val)) or + ex7_record_v(0 to 3); + + fu_xu_ex4_cr_bf(0 to 2) <= (ex4_instr_frt(1 to 3) and (0 to 2 => ex4_cr_val)) or + (ex7_bf(0 to 2) and not (0 to 2 => ex4_cr_val)) ; + + fu_xu_ex4_cr_noflush(0 to 3) <= ex7_record_v(0 to 3); + + + + -- This creates ex4_cr_val, make sure it wasn't flushed + ex5_record_din <= ex4_record and or_reduce(ex4_instr_valid(0 to 3)); + ex5_mcrfs_din <= ex4_mcrfs and or_reduce(ex4_instr_valid(0 to 3)); + ex5_cr_val_din <= ex4_cr_val and or_reduce(ex4_instr_valid(0 to 3)); + + ex4_instr_tid(0) <= ex4_instr_v(2) or ex4_instr_v(3); + ex4_instr_tid(1) <= ex4_instr_v(1) or ex4_instr_v(3); + + ex5_kill_wen_din <= ex4_kill_wen or (ex4_uc_special and ex4_is_ucode); + + + ex5_instr_valid_din(0) <= ex4_instr_valid(0); + ex5_instr_valid_din(1) <= ex4_instr_valid(1); + ex5_instr_valid_din(2) <= ex4_instr_valid(2); + ex5_instr_valid_din(3) <= ex4_instr_valid(3); + + ex5_instr_frt_din(0 to 5) <= (ex4_instr_frt(0 to 5) and not (0 to 5 => perr_sm_l2(2))) or + (perr_addr_l2 (0 to 5) and (0 to 5 => perr_sm_l2(2))) ; + +------------------------------------------------------------------------ +-- EX5 + + -- Latches + ex5_ctl: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 15) + port map (nclk => nclk, + act => tihi, + forcee => forcee, + delay_lclkr => delay_lclkr(5), + mpw1_b => mpw1_b(5), + mpw2_b => mpw2_b(1), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => ex5_ctl_si(0 to 14), + scout => ex5_ctl_so(0 to 14), + --------------------------------------------- + din(0 to 3) => ex5_instr_valid_din(0 to 3), + din(4 to 9) => ex5_instr_frt_din(0 to 5), + din(10) => ex5_record_din, + din(11) => ex5_mcrfs_din, + din(12) => ex4_is_ucode, + din(13) => ex5_cr_val_din, + din(14) => ex5_kill_wen_din, + --------------------------------------------- + dout(0 to 3) => ex5_instr_v(0 to 3), + dout(4 to 9) => ex5_instr_frt(0 to 5), + dout(10) => ex5_record, + dout(11) => ex5_mcrfs, + dout(12) => ex5_is_ucode, + dout(13) => ex5_cr_val, + dout(14) => ex5_kill_wen + --------------------------------------------- + ); + + ex5_instr_tid(0) <= ex5_instr_v(2) or ex5_instr_v(3); + ex5_instr_tid(1) <= ex5_instr_v(1) or ex5_instr_v(3); + + + + +-- this should really just be moved to fuq_fpr: +ex5_reload_val_b(0) <= not (xu_fu_ex5_load_val(0) and xu_fu_ex5_reload_val); +ex5_reload_val_b(1) <= not (xu_fu_ex5_load_val(1) and xu_fu_ex5_reload_val); +ex5_reload_val_b(2) <= not (xu_fu_ex5_load_val(2) and xu_fu_ex5_reload_val); +ex5_reload_val_b(3) <= not (xu_fu_ex5_load_val(3) and xu_fu_ex5_reload_val); + + + u5_iflsh_int0b: ex5_iflush_int_b(0) <= not( xu_ex5_flush(0) and ex5_reload_val_b(0) );--small + u5_iflsh_int1b: ex5_iflush_int_b(1) <= not( xu_ex5_flush(1) and ex5_reload_val_b(1) );--small + u5_iflsh_int2b: ex5_iflush_int_b(2) <= not( xu_ex5_flush(2) and ex5_reload_val_b(2) );--small + u5_iflsh_int3b: ex5_iflush_int_b(3) <= not( xu_ex5_flush(3) and ex5_reload_val_b(3) );--small + + u5_iflsh_int0: xu_ex5_flush_int(0) <= not( ex5_iflush_int_b(0) ); + u5_iflsh_int1: xu_ex5_flush_int(1) <= not( ex5_iflush_int_b(1) ); + u5_iflsh_int2: xu_ex5_flush_int(2) <= not( ex5_iflush_int_b(2) ); + u5_iflsh_int3: xu_ex5_flush_int(3) <= not( ex5_iflush_int_b(3) ); + +f_dcd_ex5_flush_int <= xu_ex5_flush_int(0 to 3) ; + + + u5_iflsh0: ex5_iflush_b(0) <= not( xu_ex5_flush(0) and ex5_instr_v(0) );--big + u5_iflsh1: ex5_iflush_b(1) <= not( xu_ex5_flush(1) and ex5_instr_v(1) );--big + u5_iflsh2: ex5_iflush_b(2) <= not( xu_ex5_flush(2) and ex5_instr_v(2) );--big + u5_iflsh3: ex5_iflush_b(3) <= not( xu_ex5_flush(3) and ex5_instr_v(3) );--big + + u5_iflsh_01: ex5_iflush_01 <= not( ex5_iflush_b(0) and ex5_iflush_b(1) ); + u5_iflsh_23: ex5_iflush_23 <= not( ex5_iflush_b(2) and ex5_iflush_b(3) ); + + u5_iflsh_b: ex5_instr_flush_b <= not( ex5_iflush_01 or ex5_iflush_23 ) ; + + u5_iflsh: ex5_instr_flush <= not ex5_instr_flush_b ;--small + + + + + + ex5_instr_valid(0) <= ex5_instr_v(0) and not xu_ex5_flush(0); + ex5_instr_valid(1) <= ex5_instr_v(1) and not xu_ex5_flush(1); + ex5_instr_valid(2) <= ex5_instr_v(2) and not xu_ex5_flush(2); + ex5_instr_valid(3) <= ex5_instr_v(3) and not xu_ex5_flush(3); + + -- Mux in the Parity Error Sequencer valid + ex6_instr_valid_din(0) <= ex5_instr_valid(0) or (perr_sm_l2(2) and ex5_perr_sm_instr_v and perr_tid_enc(0 to 1)="00"); + ex6_instr_valid_din(1) <= ex5_instr_valid(1) or (perr_sm_l2(2) and ex5_perr_sm_instr_v and perr_tid_enc(0 to 1)="01"); + ex6_instr_valid_din(2) <= ex5_instr_valid(2) or (perr_sm_l2(2) and ex5_perr_sm_instr_v and perr_tid_enc(0 to 1)="10"); + ex6_instr_valid_din(3) <= ex5_instr_valid(3) or (perr_sm_l2(2) and ex5_perr_sm_instr_v and perr_tid_enc(0 to 1)="11"); + + ex6_kill_wen_din <= (ex5_kill_wen or not f_pic_ex5_fpr_wr_dis_b) and not (perr_sm_l2(2) and ex5_perr_sm_instr_v); + + + --Make a copy without the flush for bypass + ex5_instr_bypval(0) <= ex5_instr_v(0) and f_pic_ex5_fpr_wr_dis_b and not ex5_kill_wen; + ex5_instr_bypval(1) <= ex5_instr_v(1) and f_pic_ex5_fpr_wr_dis_b and not ex5_kill_wen; + ex5_instr_bypval(2) <= ex5_instr_v(2) and f_pic_ex5_fpr_wr_dis_b and not ex5_kill_wen; + ex5_instr_bypval(3) <= ex5_instr_v(3) and f_pic_ex5_fpr_wr_dis_b and not ex5_kill_wen; + + + f_dcd_ex5_frt_tid(0 to 1) <= ex5_instr_tid(0 to 1); + + -- Don't update CR during certain exceptions + ex6_mcrfs_din <= ex5_mcrfs and not ex5_instr_flush; + ex6_cr_val_din <= ex5_cr_val and not ex5_instr_flush; + + -- Ouputs + +------------------------------------------------------------------------ +-- EX6 + + -- Latches + ex6_ctl: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 16) + port map (nclk => nclk, + act => tihi, + forcee => forcee, + delay_lclkr => delay_lclkr(6), + mpw1_b => mpw1_b(6), + mpw2_b => mpw2_b(1), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => ex6_ctl_si(0 to 15), + scout => ex6_ctl_so(0 to 15), + --------------------------------------------- + din(0 to 3) => ex6_instr_valid_din(0 to 3), + din(4 to 9) => ex5_instr_frt(0 to 5), + din(10) => ex6_record_din, + din(11) => ex6_mcrfs_din, + din(12) => ex5_is_ucode, + din(13) => ex6_cr_val_din, + din(14) => ex6_kill_wen_din, + din(15) => ex5_perr_sm_instr_v, + --------------------------------------------- + dout(0 to 3) => ex6_instr_v(0 to 3), + dout(4 to 9) => ex6_instr_frt(0 to 5), + dout(10) => ex6_record, + dout(11) => ex6_mcrfs, + dout(12) => ex6_is_ucode, + dout(13) => ex6_cr_val, + dout(14) => ex6_kill_wen, + dout(15) => ex6_is_fixperr + --------------------------------------------- + ); + + ex6_instr_tid(0) <= ex6_instr_v(2) or ex6_instr_v(3); + ex6_instr_tid(1) <= ex6_instr_v(1) or ex6_instr_v(3); + + -- Flushes - no flushes in EX6 + ex6_instr_valid <= or_reduce(ex6_instr_v(0 to 3)) ; + + -- Outputs EX6 + f_dcd_ex6_frt_addr(0 to 5) <= ex6_instr_frt(0 to 5); + f_dcd_ex6_frt_tid(0 to 1) <= ex6_instr_tid(0 to 1); + f_dcd_ex6_frt_wen <= ex6_instr_valid and not ex6_kill_wen; + + f_dcd_ex6_cancel <= not ex6_instr_valid; + + -- Records + ex6_record_v(0) <= ex6_instr_v(0) and (ex6_record or ex6_mcrfs); + ex6_record_v(1) <= ex6_instr_v(1) and (ex6_record or ex6_mcrfs); + ex6_record_v(2) <= ex6_instr_v(2) and (ex6_record or ex6_mcrfs); + ex6_record_v(3) <= ex6_instr_v(3) and (ex6_record or ex6_mcrfs); + + + ex6_bf(0 to 2) <= (ex6_instr_frt(1 to 3) and (1 to 3 => ex6_mcrfs)) or + ( "001" and not (1 to 3 => ex6_mcrfs)); + +------------------------------------------------------------------------ +-- EX7 FPSCR, Record Forms + + + -- Latches + ex7_ctl: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 7) + port map (nclk => nclk, + act => tihi, + forcee => forcee, + delay_lclkr => delay_lclkr(7), + mpw1_b => mpw1_b(7), + mpw2_b => mpw2_b(1), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => ex7_ctl_si(0 to 6), + scout => ex7_ctl_so(0 to 6), + --------------------------------------------- + din(0 to 3) => ex6_record_v(0 to 3), + din(4 to 6) => ex6_bf(0 to 2), + --------------------------------------------- + dout(0 to 3) => ex7_record_v(0 to 3), + dout(4 to 6) => ex7_bf(0 to 2) + --------------------------------------------- + ); + +------------------------------------------------------------------------ +-- Parity State Machine + + perr_sm: tri_rlmreg_p + generic map (init => 4, expand_type => expand_type, width => 3) + port map (nclk => nclk, + act => tihi, + forcee => forcee, + delay_lclkr => delay_lclkr(9), + mpw1_b => mpw1_b(9), + mpw2_b => mpw2_b(1), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => perr_sm_si(0 to 2), + scout => perr_sm_so(0 to 2), + din( 0 to 2) => perr_sm_din(0 to 2) , + --------------------------------------------- + dout( 0 to 2) => perr_sm_l2(0 to 2) + --------------------------------------------- + ); + perr_ctl: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 25) + port map (nclk => nclk, + act => msr_fp_act, + forcee => forcee, + delay_lclkr => delay_lclkr(9), + mpw1_b => mpw1_b(9), + mpw2_b => mpw2_b(1), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => perr_ctl_si(0 to 24), + scout => perr_ctl_so(0 to 24), + din( 0 to 5) => perr_addr_din(0 to 5), + din( 6 to 9) => perr_tid_din(0 to 3), + din(10) => perr_move_f0_to_f1, + din(11) => perr_move_f1_to_f0, + din(12) => rf0_perr_force_c, + din(13) => rf1_perr_force_c, + din(14) => new_perr_sm_instr_v, + din(15) => rf0_perr_sm_instr_v, + din(16) => rf1_perr_sm_instr_v, + din(17) => ex1_perr_sm_instr_v, + din(18) => ex2_perr_sm_instr_v, + din(19) => ex3_perr_sm_instr_v, + din(20) => ex4_perr_sm_instr_v, + din(21) => xu_fu_regfile_seq_beg, + din(22) => regfile_seq_end, + din(23) => rf0_regfile_ue, + din(24) => rf0_regfile_ce, + --------------------------------------------- + dout( 0 to 5) => perr_addr_l2(0 to 5) , + dout( 6 to 9) => perr_tid_l2(0 to 3), + dout(10) => perr_move_f0_to_f1_l2, + dout(11) => perr_move_f1_to_f0_l2, + dout(12) => rf1_perr_force_c, + dout(13) => ex1_perr_force_c, + dout(14) => rf0_perr_sm_instr_v, + dout(15) => rf1_perr_sm_instr_v, + dout(16) => ex1_perr_sm_instr_v, + dout(17) => ex2_perr_sm_instr_v, + dout(18) => ex3_perr_sm_instr_v, + dout(19) => ex4_perr_sm_instr_v, + dout(20) => ex5_perr_sm_instr_v, + dout(21) => regfile_seq_beg, + dout(22) => fu_xu_regfile_seq_end, + dout(23) => rf1_regfile_ue, + dout(24) => rf1_regfile_ce + --------------------------------------------- + ); + + rf0_perr_sm_instr_v_b <= not rf0_perr_sm_instr_v; + + perr_tid_enc(0) <= perr_tid_l2(2) or perr_tid_l2(3); + perr_tid_enc(1) <= perr_tid_l2(1) or perr_tid_l2(3); + +-- State 0 = 100 = Default, no parity error +-- State 1 = 010 = Parity error detected. Flush System, and read out both entries +-- State 2 = 001 = Move good to bad, or UE + + perr_sm_running <= not perr_sm_l2(0); + f_dcd_perr_sm_running <= perr_sm_running; + +-- Goto State0 at the end of the sequence. That's either after a UE, or writeback is done + perr_sm_ns(0) <= (perr_sm_l2(2) and rf0_regfile_ue) or (perr_sm_l2(2) and ex5_perr_sm_instr_v); + regfile_seq_end <= perr_sm_ns(0) ; + +-- Goto State1 when a parity error is detected. + perr_sm_ns(1) <= perr_sm_l2(0) and regfile_seq_beg; + +-- Goto State2 when both sets of data have been read out + perr_sm_ns(2) <= perr_sm_l2(1) and ex5_perr_sm_instr_v; + + -- set move decision. Both means Uncorrectable Error + perr_move_f0_to_f1 <= ex2_f1b_perr when (perr_sm_l2(1) and ex2_perr_sm_instr_v) = '1' else + perr_move_f0_to_f1_l2 ; + perr_move_f1_to_f0 <= ex2_f0c_perr when (perr_sm_l2(1) and ex2_perr_sm_instr_v) = '1' else + perr_move_f1_to_f0_l2 ; + + + rf0_perr_move_f0_to_f1 <= perr_move_f0_to_f1_l2 and (perr_sm_l2(2) and rf0_perr_sm_instr_v); + rf0_perr_move_f1_to_f0 <= perr_move_f1_to_f0_l2 and (perr_sm_l2(2) and rf0_perr_sm_instr_v); + + rf0_perr_force_c <= rf0_perr_move_f0_to_f1 and not rf0_perr_move_f1_to_f0; + + f_dcd_ex1_perr_force_c <= ex1_perr_force_c; + f_dcd_ex1_perr_fsel_ovrd <= ex1_perr_sm_instr_v and perr_sm_l2(2); + + perr_sm_din(0 to 2) <= ("100" and (0 to 2 => perr_sm_ns(0))) or + ("010" and (0 to 2 => perr_sm_ns(1))) or + ("001" and (0 to 2 => perr_sm_ns(2))) or + (perr_sm_l2 and (0 to 2 => not (or_reduce(perr_sm_ns(0 to 2))))); + + -- Send a dummy instruction down the pipe for reading or writing the regfiles + new_perr_sm_instr_v <= perr_sm_ns(1) or perr_sm_ns(2); + + + -- Save the offending address and tid on any parity error and hold. + perr_addr_din(0 to 5) <= ex2_instr_fra(0 to 5) when (ex2_f0a_perr and ex2_regfile_err_det and perr_sm_l2(0)) = '1' else + ex2_instr_frb(0 to 5) when (ex2_f1b_perr and ex2_regfile_err_det and perr_sm_l2(0)) = '1' else + ex2_instr_frc(0 to 5) when (ex2_f0c_perr and ex2_regfile_err_det and perr_sm_l2(0)) = '1' else + ex2_instr_frs(0 to 5) when (ex2_f1s_perr and ex2_regfile_err_det and perr_sm_l2(0)) = '1' else + perr_addr_l2(0 to 5); + + + perr_tid_din(0 to 3) <= (ex2_fpr_perr(0 to 3) and (0 to 3 => ex2_regfile_err_det and perr_sm_l2(0))) or + (perr_tid_l2(0 to 3) and not (0 to 3 => ex2_regfile_err_det and perr_sm_l2(0))); + + --Mux into the FPR address + u_pc_o1: rf0_frc_perr_x_b(0 to 5) <= not( perr_addr_l2 (0 to 5) and (0 to 5 => rf0_perr_sm_instr_v ) ); + u_pc_o2: rf0_frc_iu_x_b(0 to 5) <= not( rf0_instr_frc (0 to 5) and (0 to 5 => rf0_perr_sm_instr_v_b) ); + u_pc_o: f_dcd_rf0_frc(0 to 5) <= not( rf0_frc_perr_x_b(0 to 5) and rf0_frc_iu_x_b(0 to 5) ); + + u_pb_o1: rf0_frb_perr_x_b(0 to 5) <= not( perr_addr_l2 (0 to 5) and (0 to 5 => rf0_perr_sm_instr_v ) ); + u_pb_o2: rf0_frb_iu_x_b(0 to 5) <= not( rf0_instr_frb (0 to 5) and (0 to 5 => rf0_perr_sm_instr_v_b) ); + u_pb_o: f_dcd_rf0_frb(0 to 5) <= not( rf0_frb_perr_x_b(0 to 5) and rf0_frb_iu_x_b(0 to 5) ); + + u_pt_o1: rf0_tid_perr_x_b(0 to 1) <= not( perr_tid_enc (0 to 1) and (0 to 1 => rf0_perr_sm_instr_v ) ); + u_pt_o2: rf0_tid_iu_x_b(0 to 1) <= not( rf0_tid (0 to 1) and (0 to 1 => rf0_perr_sm_instr_v_b) ); + u_pt_o: f_dcd_rf0_tid(0 to 1) <= not( rf0_tid_perr_x_b(0 to 1) and rf0_tid_iu_x_b(0 to 1) ); + + -- Determine if we have a ue or ce to report to PC + -- state prefixes are for the recirc, not relevant to PC + rf0_regfile_ce <= (rf0_perr_move_f0_to_f1 or rf0_perr_move_f1_to_f0) and not (rf0_perr_move_f0_to_f1 and rf0_perr_move_f1_to_f0); + rf0_regfile_ue <= rf0_perr_move_f0_to_f1 and rf0_perr_move_f1_to_f0; + + err_regfile_parity(0 to 3) <= perr_tid_l2(0 to 3) and (0 to 3 => rf1_regfile_ce); + err_regfile_ue(0 to 3) <= perr_tid_l2(0 to 3) and (0 to 3 => rf1_regfile_ue); + + + fu_err_rpt : entity tri.tri_direct_err_rpt(tri_direct_err_rpt) + generic map (width => 8, expand_type => expand_type) + port map (vd => vdd, gd => gnd, + err_in(0) => err_regfile_parity(0), + err_in(1) => err_regfile_parity(1), + err_in(2) => err_regfile_parity(2), + err_in(3) => err_regfile_parity(3), + err_in(4) => err_regfile_ue(0), + err_in(5) => err_regfile_ue(1), + err_in(6) => err_regfile_ue(2), + err_in(7) => err_regfile_ue(3), + err_out(0) => fu_pc_err_regfile_parity(0), + err_out(1) => fu_pc_err_regfile_parity(1), + err_out(2) => fu_pc_err_regfile_parity(2), + err_out(3) => fu_pc_err_regfile_parity(3), + err_out(4) => fu_pc_err_regfile_ue(0), + err_out(5) => fu_pc_err_regfile_ue(1), + err_out(6) => fu_pc_err_regfile_ue(2), + err_out(7) => fu_pc_err_regfile_ue(3) ); + + +------------------------------------------------------------------------ +-- Microcode Hooks for Divide and Square Root + + + ucode_hooks : entity work.fuq_dcd_uc_hooks + generic map(expand_type => expand_type) + port map( + nclk => nclk, + thold_0_b => thold_0_b, + sg_0 => sg_0, + f_ucode_si => f_ucode_si, + forcee => forcee, + delay_lclkr => delay_lclkr(9), + mpw1_b => mpw1_b(9), + mpw2_b => mpw2_b(1), + vdd => vdd, + gnd => gnd, + msr_fp_act => msr_fp_act, + perr_sm_running => perr_sm_running, + --------------------------------------------------------------- + iu_fu_rf0_instr_v => iu_fu_rf0_instr_v, + iu_fu_rf0_instr => iu_fu_rf0_instr, + ucode_mode_rf0 => iu_fu_rf0_is_ucode, + iu_fu_rf0_ucfmul => iu_fu_rf0_ucfmul, + f_mad_ex3_uc_round_mode => f_mad_ex3_uc_round_mode, + rf0_instr_fra => rf0_instr_fra, + f_dcd_rf0_fra => f_dcd_rf0_fra, + iu_fu_rf0_ifar => iu_fu_rf0_ifar(58 to 61), + thread_id_rf0 => thread_id_rf0, + xu_rf0_flush => xu_rf0_flush, + xu_rf1_flush => xu_rf1_flush, + xu_ex1_flush => xu_ex1_flush, + xu_ex2_flush => xu_ex2_flush, + xu_ex3_flush => xu_ex3_flush, + xu_ex4_flush => xu_ex4_flush, + xu_ex5_flush => xu_ex5_flush, + f_mad_ex3_uc_res_sign => f_mad_ex3_uc_res_sign, + f_mad_ex6_uc_sign => f_mad_ex6_uc_sign, + f_mad_ex6_uc_zero => f_mad_ex6_uc_zero, + f_mad_ex3_uc_special => f_mad_ex3_uc_special, + f_mad_ex3_uc_vxsnan => f_mad_ex3_uc_vxsnan, + f_mad_ex3_uc_zx => f_mad_ex3_uc_zx, + f_mad_ex3_uc_vxidi => f_mad_ex3_uc_vxidi, + f_mad_ex3_uc_vxzdz => f_mad_ex3_uc_vxzdz, + f_mad_ex3_uc_vxsqrt => f_mad_ex3_uc_vxsqrt, + f_dcd_rf1_div_beg => rf1_div_beg, + f_dcd_rf1_sqrt_beg => rf1_sqrt_beg, + f_dcd_rf1_uc_mid => f_dcd_rf1_uc_mid, + f_dcd_rf1_uc_end => rf1_uc_end, + ex4_uc_special => ex4_uc_special, + f_dcd_rf1_uc_special => f_dcd_rf1_uc_special, + f_dcd_rf1_uc_ft_pos => f_dcd_rf1_uc_ft_pos, + f_dcd_rf1_uc_ft_neg => f_dcd_rf1_uc_ft_neg, + f_dcd_rf1_uc_fa_pos => f_dcd_rf1_uc_fa_pos, + f_dcd_rf1_uc_fc_pos => f_dcd_rf1_uc_fc_pos, + f_dcd_rf1_uc_fb_pos => f_dcd_rf1_uc_fb_pos, + f_dcd_rf1_uc_fc_hulp => f_dcd_rf1_uc_fc_hulp, + f_dcd_rf1_uc_fc_0_5 => f_dcd_rf1_uc_fc_0_5, + f_dcd_rf1_uc_fc_1_0 => f_dcd_rf1_uc_fc_1_0, + f_dcd_rf1_uc_fc_1_minus => f_dcd_rf1_uc_fc_1_minus, + f_dcd_rf1_uc_fb_1_0 => f_dcd_rf1_uc_fb_1_0, + f_dcd_rf1_uc_fb_0_75 => f_dcd_rf1_uc_fb_0_75, + f_dcd_rf1_uc_fb_0_5 => f_dcd_rf1_uc_fb_0_5 , + f_dcd_rf1_uc_fa_dis_par => f_dcd_rf1_uc_fa_dis_par, + f_dcd_rf1_uc_fb_dis_par => f_dcd_rf1_uc_fb_dis_par, + f_dcd_rf1_uc_fc_dis_par => f_dcd_rf1_uc_fc_dis_par, + uc_op_rnd_v_rf1 => rf1_uc_op_rnd_v, + uc_op_rnd_rf1 => rf1_uc_op_rnd, + f_dcd_ex2_uc_inc_lsb => f_dcd_ex2_uc_inc_lsb, + f_dcd_ex2_uc_gs_v => f_dcd_ex2_uc_gs_v , + f_dcd_ex2_uc_gs => f_dcd_ex2_uc_gs , + f_dcd_ex2_uc_vxsnan => f_dcd_ex2_uc_vxsnan, + f_dcd_ex2_uc_zx => f_dcd_ex2_uc_zx , + f_dcd_ex2_uc_vxidi => f_dcd_ex2_uc_vxidi , + f_dcd_ex2_uc_vxzdz => f_dcd_ex2_uc_vxzdz , + f_dcd_ex2_uc_vxsqrt => f_dcd_ex2_uc_vxsqrt , + uc_hooks_rc_rf0 => uc_hooks_rc_rf0, + evnt_div_sqrt_ip => evnt_div_sqrt_ip, + uc_hooks_debug => uc_hooks_debug, + --------------------------------------------------------------- + f_ucode_so => f_ucode_so + ); + + rf1_divsqrt_beg <= rf1_div_beg or rf1_sqrt_beg; + + -- Buffer outputs + f_dcd_rf1_div_beg <= rf1_div_beg; + f_dcd_rf1_sqrt_beg <= rf1_sqrt_beg; + f_dcd_rf1_uc_end <= rf1_uc_end; + + fu_iu_uc_special(0 to 3) <= (0 to 3 => tilo); + +------------------------------------------------------------------------ +-- Slow SPR Bus + + -- Latches + spr_ctl: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 15) + port map (nclk => nclk, + act => tihi, + forcee => forcee, + delay_lclkr => delay_lclkr(9), + mpw1_b => mpw1_b(9), + mpw2_b => mpw2_b(1), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => spr_ctl_si(0 to 14), + scout => spr_ctl_so(0 to 14), + --------------------------------------------- + din(0) => slowspr_in_val, + din(1) => slowspr_in_rw, + din(2 to 3) => slowspr_in_etid(0 to 1), + din(4 to 13) => slowspr_in_addr(0 to 9), + din(14) => slowspr_in_done, + --------------------------------------------- + dout(0) => slowspr_out_val, + dout(1) => slowspr_out_rw, + dout(2 to 3) => slowspr_out_etid(0 to 1), + dout(4 to 13) => slowspr_out_addr(0 to 9), + dout(14) => slowspr_out_done + --------------------------------------------- + ); + spr_data: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 2**regmode) + port map (nclk => nclk, + act => tihi, + forcee => forcee, + delay_lclkr => delay_lclkr(9), + mpw1_b => mpw1_b(9), + mpw2_b => mpw2_b(1), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => spr_data_si(64-(2**regmode) to 63), + scout => spr_data_so(64-(2**regmode) to 63), + --------------------------------------------- + din => slowspr_in_data, + --------------------------------------------- + dout => slowspr_out_data + --------------------------------------------- + ); + + axucr0_lat: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 3) + port map (nclk => nclk, + act => tihi, + forcee => cfg_sl_force, + delay_lclkr => delay_lclkr(9), + mpw1_b => mpw1_b(9), + mpw2_b => mpw2_b(1), + thold_b => cfg_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => axucr0_lat_si(0 to 2), + scout => axucr0_lat_so(0 to 2), + --------------------------------------------- + din(0 to 2) => axucr0_din(61 to 63), + --------------------------------------------- + dout(0 to 2) => axucr0_q(61 to 63) + --------------------------------------------- + ); + lcbs_cfg: tri_lcbs + generic map (expand_type => expand_type ) + port map ( + vd => vdd, + gd => gnd, + delay_lclkr => delay_lclkr(9), + nclk => nclk, + forcee => cfg_sl_force, + thold_b => cfg_sl_thold_0_b, + dclk => cfg_slat_d2clk, + lclk => cfg_slat_lclk ); + + -- Staging latches for scan_in/out signals on config rings + cfg_stg: tri_slat_scan + generic map (width => 2, init => "00", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => cfg_slat_d2clk, + lclk => cfg_slat_lclk, + scan_in(0) => ccfg_scan_in, + scan_in(1) => bcfg_scan_in, + scan_out(0) => ccfg_scan_out, + scan_out(1) => bcfg_scan_out ); + + + f_dcd_rf1_force_excp_dis <= axucr0_q(61); + f_dcd_rf1_nj_deni <= axucr0_q(62); + f_dcd_rf1_nj_deno <= axucr0_q(63); + + slowspr_in_val <= slowspr_val_in ; + slowspr_in_rw <= slowspr_rw_in ; + slowspr_in_etid <= slowspr_etid_in ; + slowspr_in_addr <= slowspr_addr_in ; + slowspr_in_data <= slowspr_data_in ; + slowspr_in_done <= slowspr_done_in ; + + -- AXUCR0 is SPR 976 + axucr0_dec <= slowspr_out_addr(0 to 9) = "1111010000"; + axucr0_rd <= slowspr_out_val and axucr0_dec and slowspr_out_rw; + axucr0_wr <= slowspr_out_val and axucr0_dec and not slowspr_out_rw; + + axucr0_din(61 to 63) <= (slowspr_out_data(61 to 63) and (61 to 63 => axucr0_wr)) or + (axucr0_q(61 to 63) and not (61 to 63 => axucr0_wr)); + + slowspr_data_out(64-(2**regmode) to 60) <= slowspr_out_data(64-(2**regmode) to 60); + + slowspr_data_out(61 to 63) <= (axucr0_q(61 to 63) and (61 to 63 => axucr0_rd)) or + (slowspr_out_data(61 to 63) and not (61 to 63 => axucr0_rd)); + + slowspr_val_out <= slowspr_out_val ; + slowspr_rw_out <= slowspr_out_rw ; + slowspr_etid_out <= slowspr_out_etid ; + slowspr_addr_out <= slowspr_out_addr ; + slowspr_done_out <= slowspr_out_done or axucr0_rd or axucr0_wr ; + +------------------------------------------------------------------------ +-- RAM + + + ex6_ram_sign <= f_rnd_ex6_res_sign; + ex6_ram_frac(0 to 52) <= f_rnd_ex6_res_frac(0 to 52); + ex6_ram_expo(3 to 13) <= f_rnd_ex6_res_expo(3 to 13); + + -- Better be the only instr in the pipe for that thread. Bugspray event fail if not + ex6_ram_done <= pc_fu_ram_mode and ex6_instr_valid and (pc_fu_ram_thread(0 to 1) = ex6_instr_tid(0 to 1)) + and not ex6_is_ucode -- Only report the end of the ucode seq + and not ex6_is_fixperr; + + ex7_ram_lat: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 65) + port map (nclk => nclk, + act => ex6_instr_valid, + forcee => forcee, + delay_lclkr => delay_lclkr(9), + mpw1_b => mpw1_b(9), + mpw2_b => mpw2_b(1), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => ram_data_si(0 to 64), + scout => ram_data_so(0 to 64), + --------------------------------------------- + din(0) => ex6_ram_sign, + din(1 to 11) => ex6_ram_expo(3 to 13), + din(12 to 64) => ex6_ram_frac(0 to 52), + --------------------------------------------- + dout(0) => ex7_ram_sign, + dout(1 to 11) => ex7_ram_expo(3 to 13), + dout(12 to 64) => ex7_ram_frac(0 to 52) + --------------------------------------------- + ); + ex7_ramv_lat: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 1) + port map (nclk => nclk, + act => tihi, + forcee => forcee, + delay_lclkr => delay_lclkr(9), + mpw1_b => mpw1_b(9), + mpw2_b => mpw2_b(1), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin(0) => ram_datav_si(0), + scout(0) => ram_datav_so(0), + --------------------------------------------- + din(0) => ex6_ram_done, + --------------------------------------------- + dout(0) => ex7_ram_done + ); + + ex7_ram_data( 0) <= ex7_ram_sign; + ex7_ram_data( 1 to 11) <= ex7_ram_expo(3 to 13) and (3 to 13 => ex7_ram_frac(0)); + ex7_ram_data(12 to 63) <= ex7_ram_frac(1 to 52); + + fu_pc_ram_done <= ex7_ram_done; + fu_pc_ram_data(0 to 63) <= ex7_ram_data(0 to 63); + +------------------------------------------------------------------------ +-- Event Bus + + -- Perf events + evnt_axu_instr_cmt(0) <= ex6_instr_valid and (ex6_instr_tid(0 to 1) = "00") and not ex6_is_ucode and not ex6_is_fixperr; + evnt_axu_instr_cmt(1) <= ex6_instr_valid and (ex6_instr_tid(0 to 1) = "01") and not ex6_is_ucode and not ex6_is_fixperr; + evnt_axu_instr_cmt(2) <= ex6_instr_valid and (ex6_instr_tid(0 to 1) = "10") and not ex6_is_ucode and not ex6_is_fixperr; + evnt_axu_instr_cmt(3) <= ex6_instr_valid and (ex6_instr_tid(0 to 1) = "11") and not ex6_is_ucode and not ex6_is_fixperr; + + evnt_axu_cr_cmt(0) <= ex6_instr_valid and (ex6_instr_tid(0 to 1) = "00") and (ex6_cr_val or ex6_record or ex6_mcrfs); + evnt_axu_cr_cmt(1) <= ex6_instr_valid and (ex6_instr_tid(0 to 1) = "01") and (ex6_cr_val or ex6_record or ex6_mcrfs); + evnt_axu_cr_cmt(2) <= ex6_instr_valid and (ex6_instr_tid(0 to 1) = "10") and (ex6_cr_val or ex6_record or ex6_mcrfs); + evnt_axu_cr_cmt(3) <= ex6_instr_valid and (ex6_instr_tid(0 to 1) = "11") and (ex6_cr_val or ex6_record or ex6_mcrfs); + + evnt_axu_idle(0) <= (ex6_instr_tid(0 to 1) = "00") and not (ex6_instr_valid or ex6_cr_val or ex6_record or ex6_mcrfs); --includes ucode + evnt_axu_idle(1) <= (ex6_instr_tid(0 to 1) = "01") and not (ex6_instr_valid or ex6_cr_val or ex6_record or ex6_mcrfs); --includes ucode + evnt_axu_idle(2) <= (ex6_instr_tid(0 to 1) = "10") and not (ex6_instr_valid or ex6_cr_val or ex6_record or ex6_mcrfs); --includes ucode + evnt_axu_idle(3) <= (ex6_instr_tid(0 to 1) = "11") and not (ex6_instr_valid or ex6_cr_val or ex6_record or ex6_mcrfs); --includes ucode + + evnt_denrm_flush(0) <= (ex4_instr_tid(0 to 1) = "00") and ex4_b_den_flush; + evnt_denrm_flush(1) <= (ex4_instr_tid(0 to 1) = "01") and ex4_b_den_flush; + evnt_denrm_flush(2) <= (ex4_instr_tid(0 to 1) = "10") and ex4_b_den_flush; + evnt_denrm_flush(3) <= (ex4_instr_tid(0 to 1) = "11") and ex4_b_den_flush; + + evnt_uc_instr_cmt(0) <= ex6_instr_valid and (ex6_instr_tid(0 to 1) = "00") and ex6_is_ucode; + evnt_uc_instr_cmt(1) <= ex6_instr_valid and (ex6_instr_tid(0 to 1) = "01") and ex6_is_ucode; + evnt_uc_instr_cmt(2) <= ex6_instr_valid and (ex6_instr_tid(0 to 1) = "10") and ex6_is_ucode; + evnt_uc_instr_cmt(3) <= ex6_instr_valid and (ex6_instr_tid(0 to 1) = "11") and ex6_is_ucode; + + evnt_fpu_fx(0 to 3) <= f_scr_ex7_fx_thread0(0) & f_scr_ex7_fx_thread1(0) & f_scr_ex7_fx_thread2(0) & f_scr_ex7_fx_thread3(0) ; + evnt_fpu_fex(0 to 3) <= f_scr_ex7_fx_thread0(1) & f_scr_ex7_fx_thread1(1) & f_scr_ex7_fx_thread2(1) & f_scr_ex7_fx_thread3(1) ; + + t0_events_in(0 to 7) <= evnt_axu_instr_cmt(0) & evnt_axu_cr_cmt(0) & evnt_axu_idle(0) & evnt_div_sqrt_ip(0) & + evnt_denrm_flush(0) & evnt_uc_instr_cmt(0) & evnt_fpu_fx(0) & evnt_fpu_fex(0); + t1_events_in(0 to 7) <= evnt_axu_instr_cmt(1) & evnt_axu_cr_cmt(1) & evnt_axu_idle(1) & evnt_div_sqrt_ip(1) & + evnt_denrm_flush(1) & evnt_uc_instr_cmt(1) & evnt_fpu_fx(1) & evnt_fpu_fex(1); + t2_events_in(0 to 7) <= evnt_axu_instr_cmt(2) & evnt_axu_cr_cmt(2) & evnt_axu_idle(2) & evnt_div_sqrt_ip(2) & + evnt_denrm_flush(2) & evnt_uc_instr_cmt(2) & evnt_fpu_fx(2) & evnt_fpu_fex(2); + t3_events_in(0 to 7) <= evnt_axu_instr_cmt(3) & evnt_axu_cr_cmt(3) & evnt_axu_idle(3) & evnt_div_sqrt_ip(3) & + evnt_denrm_flush(3) & evnt_uc_instr_cmt(3) & evnt_fpu_fx(3) & evnt_fpu_fex(3); + + event_en_d <= ( msr_pr_q and (0 to 3=> event_count_mode_q(0))) or -- User + (not msr_pr_q and msr_gs_q and (0 to 3=> event_count_mode_q(1))) or -- Guest Supervisor + (not msr_pr_q and not msr_gs_q and (0 to 3=> event_count_mode_q(2))); -- Hypervisor + + t0_events <= t0_events_in and (0 to 7 =>event_en_q(0)); + t1_events <= t1_events_in and (0 to 7 =>event_en_q(1)); + t2_events <= t2_events_in and (0 to 7 =>event_en_q(2)); + t3_events <= t3_events_in and (0 to 7 =>event_en_q(3)); + + + event_mux: entity clib.c_event_mux + generic map ( events_in => 32 ) + port map( + vd => vdd , + gd => gnd , + t0_events => t0_events, + t1_events => t1_events, + t2_events => t2_events, + t3_events => t3_events, + + select_bits => pc_fu_event_mux_ctrls, + event_bits => event_data_d + ); + + perf_data: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 39) + port map (nclk => nclk, + act => event_act, + forcee => func_slp_sl_force, + delay_lclkr => delay_lclkr(9), + mpw1_b => mpw1_b(9), + mpw2_b => mpw2_b(1), + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => perf_data_si(0 to 38), + scout => perf_data_so(0 to 38), + --------------------------------------------- + din( 0 to 7) => event_data_d(0 to 7), + din( 8 to 11) => event_en_d(0 to 3), + din(12) => ex4_b_den_flush_din, + din(13 to 15) => pc_fu_event_count_mode(0 to 2), + din(16 to 19) => xu_fu_msr_pr(0 to 3), + din(20 to 23) => xu_fu_msr_gs(0 to 3), + din(24) => pc_fu_instr_trace_mode, + din(25 to 26) => pc_fu_instr_trace_tid(0 to 1), + din(27 to 30) => rf0_instr_tid_1hot(0 to 3), + din(31 to 34) => rf1_instr_iss(0 to 3), + din(35 to 38) => ex1_instr_iss(0 to 3), + + --------------------------------------------- + dout( 0 to 7) => event_data_q(0 to 7), + dout( 8 to 11) => event_en_q(0 to 3), + dout(12) => ex4_b_den_flush, + dout(13 to 15) => event_count_mode_q(0 to 2), + dout(16 to 19) => msr_pr_q(0 to 3), + dout(20 to 23) => msr_gs_q(0 to 3), + dout(24) => instr_trace_mode_q, + dout(25 to 26) => instr_trace_tid_q(0 to 1), + dout(27 to 30) => rf1_instr_iss(0 to 3), + dout(31 to 34) => ex1_instr_iss(0 to 3), + dout(35 to 38) => ex2_instr_iss(0 to 3) + --------------------------------------------- + ); + + +------------------------------------------------------------------------ +-- Debug Bus + + -- FU is the first unit in the DBG chain + trace_data_in(0 to 87) <= debug_data_in(0 to 87); + trigger_data_in(0 to 11) <= trace_triggers_in(0 to 11); + + -- Debug Events + dbg_group0 ( 0 to 63) <= ex7_ram_data(0 to 63); + dbg_group0 (64 to 87) <= ex7_ram_expo(3 to 13) & ex7_ram_frac(0) & ex7_ram_done & (0 to 10 => '0'); + + dbg_group1 (0 to 87) <= uc_hooks_debug(0 to 55) & (56 to 87 => '0'); + + dbg_group2 (0 to 31) <= rf1_instr(0 to 31) and not (0 to 31 => instr_trace_mode_q and (instr_trace_tid_q(0 to 1) /= rf1_tid(0 to 1))); --gate instr if not tid + + dbg_group2 (32 to 35) <= (f_scr_ex7_fx_thread0(0 to 3) and not (0 to 3 => instr_trace_mode_q)); + dbg_group2 (36 to 39) <= (f_scr_ex7_fx_thread1(0 to 3) and not (0 to 3 => instr_trace_mode_q)) or ("1010" and (0 to 3 => instr_trace_mode_q)); --A + dbg_group2 (40 to 43) <= (f_scr_ex7_fx_thread2(0 to 3) and not (0 to 3 => instr_trace_mode_q)) or ("1011" and (0 to 3 => instr_trace_mode_q)); --B + dbg_group2 (44 to 47) <= (f_scr_ex7_fx_thread3(0 to 3) and not (0 to 3 => instr_trace_mode_q)) or ("1100" and (0 to 3 => instr_trace_mode_q)); --C + dbg_group2 (48 to 51) <= (ex4_eff_addr(59 to 62) and not (0 to 3 => instr_trace_mode_q)) or ("1101" and (0 to 3 => instr_trace_mode_q)); --D + dbg_group2 (52 to 55) <= ((ex4_eff_addr(63) &perr_sm_l2(0 to 2)) and not (0 to 3 => instr_trace_mode_q)) or ("1110" and (0 to 3 => instr_trace_mode_q)); --E + dbg_group2 (56 to 61) <= perr_addr_l2(0 to 5) and not (0 to 5 => instr_trace_mode_q); + dbg_group2 (62 to 65) <= perr_tid_l2(0 to 3) and not (0 to 3 => instr_trace_mode_q); + dbg_group2 (66) <= rf0_perr_move_f0_to_f1 and not instr_trace_mode_q ; + dbg_group2 (67) <= rf0_perr_move_f1_to_f0 and not instr_trace_mode_q ; + dbg_group2 (68) <= rf1_regfile_ce and not instr_trace_mode_q ; + dbg_group2 (69) <= rf1_regfile_ue and not instr_trace_mode_q ; + dbg_group2 (70 to 87) <= (70 to 87=> tilo); + + dbg_group3 (0) <= rf1_regfile_ce; + dbg_group3 (1) <= rf1_regfile_ue; + dbg_group3 (2) <= rf1_bypsel_a_res0; + dbg_group3 (3) <= rf1_bypsel_c_res0; + dbg_group3 (4) <= rf1_bypsel_b_res0; + dbg_group3 (5) <= rf1_bypsel_a_res1; + dbg_group3 (6) <= rf1_bypsel_c_res1; + dbg_group3 (7) <= rf1_bypsel_b_res1; + dbg_group3 (8) <= rf1_bypsel_a_load0; + dbg_group3 (9) <= rf1_bypsel_c_load0; + dbg_group3 (10) <= rf1_bypsel_b_load0; + dbg_group3 (11) <= rf1_bypsel_a_load1; + dbg_group3 (12) <= rf1_bypsel_c_load1; + dbg_group3 (13) <= rf1_bypsel_b_load1; + dbg_group3 (14) <= rf1_frs_byp; + dbg_group3 (15) <= rf1_v; + dbg_group3 (16 to 31) <= (16 to 31 => '0'); + dbg_group3 (32 to 63) <= t0_events(0 to 7) & t1_events(0 to 7) & t2_events(0 to 7) & t3_events(0 to 7) ; + dbg_group3 (64 to 87) <= (64 to 87=> tilo); + + trg_group0 ( 0 to 3) <= evnt_fpu_fx(0 to 3); + trg_group0 ( 4 to 7) <= evnt_fpu_fex(0 to 3); + trg_group0 ( 8) <= ex6_instr_valid; + trg_group0 ( 9) <= ex6_is_ucode; + trg_group0 (10 to 11) <= ex6_instr_tid(0 to 1); + + trg_group1 ( 0 to 2) <= perr_sm_l2(0 to 2); + trg_group1 ( 3) <= rf1_regfile_ce; + trg_group1 ( 4) <= rf1_regfile_ue; + trg_group1 ( 5) <= ex6_instr_valid; + trg_group1 ( 6 to 7) <= ex6_instr_tid(0 to 1); + trg_group1 ( 8) <= ex3_instr_match; + trg_group1 ( 9) <= ex6_record; + trg_group1 (10) <= ex6_mcrfs; + trg_group1 (11) <= ex4_b_den_flush; + + trg_group2 ( 0 to 11) <= uc_hooks_debug( 0 to 11); --thread 0:1 hooks scr + trg_group3 ( 0 to 11) <= uc_hooks_debug(16 to 27); --thread 2:3 hooks scr + + + -- pc_fu_instr_trace_mode + debug_mux_ctrls_muxed(0 to 15) <= debug_mux_ctrls_q(0 to 15) when instr_trace_mode_q = '0' else + ("10" & "000" & "00" & "1111" & "00" & '0' & "11"); + --sel2 unused rot sel tsel trot trigssel + + dbgmux: entity clib.c_debug_mux4 + port map( + vd => vdd , + gd => gnd , + select_bits => debug_mux_ctrls_muxed , + trace_data_in => trace_data_in , + trigger_data_in => trigger_data_in , + dbg_group0 => dbg_group0 , + dbg_group1 => dbg_group1 , + dbg_group2 => dbg_group2 , + dbg_group3 => dbg_group3 , + trg_group0 => trg_group0 , + trg_group1 => trg_group1 , + trg_group2 => trg_group2 , + trg_group3 => trg_group3 , + trace_data_out => trace_data_out , + trigger_data_out => trigger_data_out ); + + + + debug_data_d(0 to 87) <= trace_data_out(0 to 87); + debug_trig_d(0 to 11) <= trigger_data_out(0 to 11); + ex4_b_den_flush_din <= ex3_b_den_flush and or_reduce(ex3_instr_v(0 to 3)); + + -- Trace Bus latches, using pc_fu_trace_bus_enable for act + dbg0_data: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 116) + port map (nclk => nclk, + act => dbg0_act, + forcee => func_slp_sl_force, + delay_lclkr => delay_lclkr(9), + mpw1_b => mpw1_b(9), + mpw2_b => mpw2_b(1), + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => dbg0_data_si(0 to 115), + scout => dbg0_data_so(0 to 115), + --------------------------------------------- + din(0 to 87) => debug_data_d(0 to 87), + din(88 to 99) => debug_trig_d(0 to 11), + din(100 to 115) => pc_fu_debug_mux_ctrls(0 to 15), + --------------------------------------------- + dout( 0 to 87) => debug_data_q(0 to 87), + dout(88 to 99) => debug_trig_q(0 to 11), + dout(100 to 115) => debug_mux_ctrls_q(0 to 15) + --------------------------------------------- + ); + --Another set, closer to the I/O on the bottom + dbg1_data: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 5) + port map (nclk => nclk, + act => tihi, + forcee => forcee, + delay_lclkr => delay_lclkr(9), + mpw1_b => mpw1_b(9), + mpw2_b => mpw2_b(1), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => dbg1_data_si(0 to 4), + scout => dbg1_data_so(0 to 4), + --------------------------------------------- + din( 0 to 4) => xu_fu_ex3_eff_addr(59 to 63), + --------------------------------------------- + dout( 0 to 4) => ex4_eff_addr(59 to 63) + --------------------------------------------- + ); + + -- To MMU, i'm the first in the chain + debug_data_out(0 to 87) <= debug_data_q(0 to 87); + trace_triggers_out(0 to 11) <= debug_trig_q(0 to 11); + fu_pc_event_data(0 to 7) <= event_data_q(0 to 7); + + +------------------------------------------------------------------------ +-- Spare Latches + + spare_lat: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 24) + port map (nclk => nclk, + act => tihi, + forcee => forcee, + delay_lclkr => delay_lclkr(9), + mpw1_b => mpw1_b(9), + mpw2_b => mpw2_b(1), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => spare_si(0 to 23), + scout => spare_so(0 to 23), + din( 0 to 23) => SPARE_L2(0 to 23) , + --------------------------------------------- + dout( 0 to 23) => SPARE_L2(0 to 23) + --------------------------------------------- + ); + +------------------------------------------------------------------------ +-- unused + + spare_unused( 0) <= iu_fu_rf0_ldst_tag(2); + spare_unused( 1) <= iu_fu_rf0_frt(0); + spare_unused( 2) <= iu_fu_rf0_fra(0); + spare_unused( 3) <= iu_fu_rf0_frb(0); + spare_unused( 4) <= iu_fu_rf0_frc(0); + spare_unused( 5 to 8) <= xu_is2_flush(0 to 3); + spare_unused( 9 to 10) <= f_rnd_ex6_res_expo(1 to 2); + +------------------------------------------------------------------------ +-- Scan Connections + + rf1_iu_si (0 to 14) <= rf1_iu_so (1 to 14) & f_dcd_si; + act_lat_si (0 to 2) <= act_lat_so (1 to 2) & rf1_iu_so (0); + rf0_thread_si(0 to 3) <= rf0_thread_so(1 to 3) & act_lat_so (0); + rf1_frt_si (0 to 31) <= rf1_frt_so (1 to 31) & rf0_thread_so(0); + rf1_ifr_si (62-eff_ifar to 61) <= rf1_ifr_so(63-eff_ifar to 61) & rf1_frt_so (0); + rf1_instl_si (0 to 31) <= rf1_instl_so (1 to 31) & rf1_ifr_so (62-eff_ifar); + rf1_byp_si (0 to 11) <= rf1_byp_so (1 to 11) & rf1_instl_so(0); + ex1_ctl_si (0 to 7) <= ex1_ctl_so (1 to 7) & rf1_byp_so (0); + ex1_frt_si (0 to 17) <= ex1_frt_so (1 to 17) & ex1_ctl_so (0); + ex1_perr_si (0 to 23) <= ex1_perr_so (1 to 23) & ex1_frt_so (0); + ex1_ifar_si (62-eff_ifar to 61) <= ex1_ifar_so(63-eff_ifar to 61) & ex1_perr_so (0); + ex2_ctl_si (0 to 15) <= ex2_ctl_so (1 to 15) & ex1_ifar_so(62-eff_ifar); + ex2_ctlng_si (0 to 16) <= ex2_ctlng_so (1 to 16) & ex2_ctl_so (0); + ex2_perr_si (0 to 23) <= ex2_perr_so (1 to 23) & ex2_ctlng_so(0); + ex2_stdv_si <= ex2_perr_so (0) ; + ex3_ctlng_si (0 to 15) <= ex3_ctlng_so(1 to 15) & ex2_stdv_so; + ex3_ctl_si (0 to 12) <= ex3_ctl_so (1 to 12) & ex3_ctlng_so(0); + ex4_ctl_si (0 to 15) <= ex4_ctl_so (1 to 15) & ex3_ctl_so (0); + ex5_ctl_si (0 to 14) <= ex5_ctl_so (1 to 14) & ex4_ctl_so (0); + ex6_ctl_si (0 to 15) <= ex6_ctl_so (1 to 15) & ex5_ctl_so (0); + ex7_ctl_si (0 to 6) <= ex7_ctl_so (1 to 6) & ex6_ctl_so (0); + perr_sm_si (0 to 2) <= perr_sm_so (1 to 2) & ex7_ctl_so (0); + perr_ctl_si (0 to 24) <= perr_ctl_so (1 to 24) & perr_sm_so (0); + spr_ctl_si (0 to 14) <= spr_ctl_so (1 to 14) & perr_ctl_so(0); + spr_data_si (64-(2**regmode) to 63) <= spr_data_so(65-(2**regmode) to 63) & spr_ctl_so (0); + ram_data_si (0 to 64) <= ram_data_so (1 to 64) & spr_data_so(64-(2**regmode)); + ram_datav_si(0) <= ram_data_so(0); + perf_data_si (0 to 38) <= perf_data_so(1 to 38) & ram_datav_so(0); + dbg0_data_si (0 to 115) <= dbg0_data_so(1 to 115) & perf_data_so(0); + dbg1_data_si (0 to 4) <= dbg1_data_so(1 to 4) & dbg0_data_so(0); + f_ucode_si <= dbg1_data_so(0); + spare_si (0 to 23) <= spare_so(1 to 23) & f_ucode_so; + f_dcd_so <= spare_so(0); + + axucr0_lat_si(0 to 2) <= axucr0_lat_so(1 to 2) & dcfg_scan_in; + dcfg_scan_out <= axucr0_lat_so(0); + +end architecture fuq_dcd; diff --git a/rel/src/vhdl/work/fuq_dcd_uc_hooks.vhdl b/rel/src/vhdl/work/fuq_dcd_uc_hooks.vhdl new file mode 100644 index 0000000..adccbd6 --- /dev/null +++ b/rel/src/vhdl/work/fuq_dcd_uc_hooks.vhdl @@ -0,0 +1,1789 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- +--***************************************************************************** +--* +--* TITLE: uc_hooks +--* +--* NAME: fuq_dcd_uc_hooks.vhdl +--* +--* DESC: This is for microcoded Divide and Square Root +--* +--***************************************************************************** + + + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + +--------------------------------------------------------------------- + + +entity fuq_dcd_uc_hooks is +generic(expand_type : integer := 2 ); -- 0 - ibm tech, 1 - other ); +port( + nclk : in clk_logic; + thold_0_b : in std_ulogic; + sg_0 : in std_ulogic; + f_ucode_si : in std_ulogic; + forcee : in std_ulogic; -- tidn, + delay_lclkr : in std_ulogic; -- tidn, + mpw1_b : in std_ulogic; -- tidn, + mpw2_b : in std_ulogic; -- tidn, + vdd : inout power_logic; + gnd : inout power_logic; + msr_fp_act : in std_ulogic; + perr_sm_running : in std_ulogic; + --------------------------------------------------------------- + iu_fu_rf0_instr_v : in std_ulogic; + iu_fu_rf0_instr : in std_ulogic_vector(0 to 31); + iu_fu_rf0_ucfmul : in std_ulogic; + ucode_mode_rf0 : in std_ulogic; + f_mad_ex3_uc_round_mode : in std_ulogic_vector(0 to 1); + rf0_instr_fra : in std_ulogic_vector(0 to 5); + f_dcd_rf0_fra : out std_ulogic_vector(0 to 5); + iu_fu_rf0_ifar : in std_ulogic_vector(58 to 61); + thread_id_rf0 : in std_ulogic_vector(0 to 3); + xu_rf0_flush : in std_ulogic_vector(0 to 3); + xu_rf1_flush : in std_ulogic_vector(0 to 3); + xu_ex1_flush : in std_ulogic_vector(0 to 3); + xu_ex2_flush : in std_ulogic_vector(0 to 3); + xu_ex3_flush : in std_ulogic_vector(0 to 3); + xu_ex4_flush : in std_ulogic_vector(0 to 3); + xu_ex5_flush : in std_ulogic_vector(0 to 3); + f_mad_ex6_uc_sign, f_mad_ex6_uc_zero : in std_ulogic; + f_mad_ex3_uc_special : in std_ulogic; + f_mad_ex3_uc_vxsnan : in std_ulogic; + f_mad_ex3_uc_zx : in std_ulogic; + f_mad_ex3_uc_vxidi : in std_ulogic; + f_mad_ex3_uc_vxzdz : in std_ulogic; + f_mad_ex3_uc_vxsqrt : in std_ulogic; + f_mad_ex3_uc_res_sign : in std_ulogic; + uc_ignore_flush_rf1 : out std_ulogic; + f_dcd_rf1_div_beg : out std_ulogic; + f_dcd_rf1_sqrt_beg : out std_ulogic; + f_dcd_rf1_uc_mid : out std_ulogic; + f_dcd_rf1_uc_end : out std_ulogic; + ex4_uc_special : out std_ulogic; -- to block iterations in fuq_axu_fu_dep (is1) + f_dcd_rf1_uc_special : out std_ulogic; + f_dcd_rf1_uc_ft_pos : out std_ulogic; + f_dcd_rf1_uc_ft_neg : out std_ulogic; + f_dcd_rf1_uc_fa_pos : out std_ulogic; + f_dcd_rf1_uc_fc_pos : out std_ulogic; + f_dcd_rf1_uc_fb_pos : out std_ulogic; + f_dcd_rf1_uc_fc_hulp : out std_ulogic; + f_dcd_rf1_uc_fc_0_5 : out std_ulogic; + f_dcd_rf1_uc_fc_1_0 : out std_ulogic; + f_dcd_rf1_uc_fc_1_minus : out std_ulogic; + f_dcd_rf1_uc_fb_1_0 : out std_ulogic; + f_dcd_rf1_uc_fb_0_75 : out std_ulogic; + f_dcd_rf1_uc_fb_0_5 : out std_ulogic; + f_dcd_rf1_uc_fa_dis_par : out std_ulogic; + f_dcd_rf1_uc_fb_dis_par : out std_ulogic; + f_dcd_rf1_uc_fc_dis_par : out std_ulogic; + uc_op_rnd_v_rf1 : out std_ulogic; + uc_op_rnd_rf1 : out std_ulogic_vector(0 to 1); + f_dcd_ex2_uc_inc_lsb : out std_ulogic; + f_dcd_ex2_uc_gs_v : out std_ulogic; + f_dcd_ex2_uc_gs : out std_ulogic_vector(0 to 1); + f_dcd_ex2_uc_vxsnan : out std_ulogic; + f_dcd_ex2_uc_zx : out std_ulogic; + f_dcd_ex2_uc_vxidi : out std_ulogic; + f_dcd_ex2_uc_vxzdz : out std_ulogic; + f_dcd_ex2_uc_vxsqrt : out std_ulogic; + uc_hooks_rc_rf0 : out std_ulogic; + uc_hooks_debug : out std_ulogic_vector(0 to 55); + evnt_div_sqrt_ip : out std_ulogic_vector(0 to 3); + f_ucode_so : out std_ulogic + +); + + -- synopsys translate_off + + + + -- synopsys translate_on + +end fuq_dcd_uc_hooks; + + +architecture fuq_dcd_uc_hooks of fuq_dcd_uc_hooks is + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + + +signal uc_sign_zero_t0, uc_scr_t0_ld, uc_scr_t0_l2, uc_scr_t0_scin, uc_scr_t0_scout : std_ulogic_vector(0 to 11); +signal uc_sign_zero_t1, uc_scr_t1_ld, uc_scr_t1_l2, uc_scr_t1_scin, uc_scr_t1_scout : std_ulogic_vector(0 to 11); +signal uc_sign_zero_t2, uc_scr_t2_ld, uc_scr_t2_l2, uc_scr_t2_scin, uc_scr_t2_scout : std_ulogic_vector(0 to 11); +signal uc_sign_zero_t3, uc_scr_t3_ld, uc_scr_t3_l2, uc_scr_t3_scin, uc_scr_t3_scout : std_ulogic_vector(0 to 11); +signal uc_scr_t0_upd, uc_scr_t1_upd, uc_scr_t2_upd, uc_scr_t3_upd : std_ulogic_vector(0 to 4); + +signal uc_scr_wr, uc_scr_wr_rf0 : std_ulogic; +signal uc_scr_sel, uc_scr_thread_rf0 : std_ulogic_vector(0 to 1); + +signal uc_scr_wr_pipe_rf1_scin, uc_scr_wr_pipe_rf1_scout : std_ulogic_vector(0 to 7); +signal uc_scr_wr_rf1 : std_ulogic; +signal uc_scr_sel_rf1, uc_scr_thread_rf1 : std_ulogic_vector(0 to 1); + +signal uc_scr_wr_pipe_ex1_scin, uc_scr_wr_pipe_ex1_scout : std_ulogic_vector(0 to 8); +signal uc_scr_wr_ex1 : std_ulogic; +signal uc_scr_sel_ex1, uc_scr_thread_ex1 : std_ulogic_vector(0 to 1); + +signal uc_scr_wr_pipe_ex2_scin, uc_scr_wr_pipe_ex2_scout : std_ulogic_vector(0 to 8); +signal uc_scr_wr_ex2 : std_ulogic; +signal uc_scr_sel_ex2, uc_scr_thread_ex2 : std_ulogic_vector(0 to 1); + +signal uc_scr_wr_pipe_ex3_scin, uc_scr_wr_pipe_ex3_scout : std_ulogic_vector(0 to 6); +signal uc_scr_wr_ex3 : std_ulogic; +signal uc_scr_sel_ex3, uc_scr_thread_ex3 : std_ulogic_vector(0 to 1); + +signal uc_scr_wr_pipe_ex4_scin, uc_scr_wr_pipe_ex4_scout : std_ulogic_vector(0 to 6); +signal uc_scr_wr_ex4 : std_ulogic; +signal uc_scr_sel_ex4, uc_scr_thread_ex4 : std_ulogic_vector(0 to 1); + +signal uc_scr_wr_pipe_ex5_scin, uc_scr_wr_pipe_ex5_scout : std_ulogic_vector(0 to 5); +signal uc_scr_wr_ex5 : std_ulogic; +signal uc_scr_sel_ex5, uc_scr_thread_ex5 : std_ulogic_vector(0 to 1); + +signal uc_scr_wr_pipe_ex6_scin, uc_scr_wr_pipe_ex6_scout : std_ulogic_vector(0 to 5); +signal uc_scr_wr_ex6 : std_ulogic; +signal uc_scr_sel_ex6, uc_scr_thread_ex6 : std_ulogic_vector(0 to 1); + +signal uc_scr_wr_rf1_l2 : std_ulogic; +signal uc_scr_wr_ex1_l2 : std_ulogic; +signal uc_scr_wr_ex2_l2 : std_ulogic; +signal uc_scr_wr_ex3_l2 : std_ulogic; +signal uc_scr_wr_ex4_l2 : std_ulogic; +signal uc_scr_wr_ex5_l2 : std_ulogic; + +signal q1r_sign_rf0, q1r_zero_rf0 : std_ulogic; +signal q1ulpr_zero_rf0 : std_ulogic; +signal q1_m_ulp_rf0 : std_ulogic; +signal uc_beg_rf0, uc_beg_rf0_v : std_ulogic; +signal uc_beg_rf1 : std_ulogic; +signal uc_beg_ex1 : std_ulogic; +signal uc_beg_ex2 : std_ulogic; +signal uc_beg_ex3 : std_ulogic; +signal uc_beg_ex4 : std_ulogic; +signal uc_end_rf0, uc_end_rf0_v, uc_end_rf0_vf : std_ulogic; +signal uc_normal_end_rf0, uc_normal_end_rf0_part : std_ulogic; +signal uc_fa_pos : std_ulogic; +signal uc_fc_pos : std_ulogic; +signal uc_fc_pos_rf0 : std_ulogic; +signal uc_fb_pos : std_ulogic; +signal uc_fc_hulp : std_ulogic; +signal uc_fc_0_5 : std_ulogic; +signal uc_fc_1_0 : std_ulogic; +signal uc_fc_1_minus : std_ulogic; +signal uc_fb_1_0 : std_ulogic; +signal uc_fb_0_75 : std_ulogic; +signal uc_fb_0_5 : std_ulogic; +signal uc_op_rnd_v : std_ulogic; +signal uc_op_rnd : std_ulogic_vector(0 to 1); +signal uc_inc_lsb : std_ulogic; +signal uc_gs_v_rf0 : std_ulogic; +signal uc_1st_instr_ld : std_ulogic_vector(0 to 3); +signal uc_1st_instr_l2 : std_ulogic_vector(0 to 3); +signal uc_1st_instr_scin : std_ulogic_vector(0 to 3); +signal uc_1st_instr_scout : std_ulogic_vector(0 to 3); +signal uc_div_beg_rf0 : std_ulogic; +signal uc_sqrt_beg_rf0 : std_ulogic; +signal uc_mid_rf0 : std_ulogic; +signal uc_div_beg_rf1 : std_ulogic; +signal uc_sqrt_beg_rf1 : std_ulogic; +signal pipe_rf1_scin : std_ulogic_vector(0 to 21); +signal pipe_rf1_scout : std_ulogic_vector(0 to 21); +signal fp_operation_rf0 : std_ulogic; +signal uc_special_cases_ex3 : std_ulogic_vector(0 to 7); +signal uc_special_cases_t0_ex3 : std_ulogic_vector(8 to 11); +signal uc_special_cases_t1_ex3 : std_ulogic_vector(8 to 11); +signal uc_special_cases_t2_ex3 : std_ulogic_vector(8 to 11); +signal uc_special_cases_t3_ex3 : std_ulogic_vector(8 to 11); +signal uc_round_mode_ld : std_ulogic_vector(0 to 7); +signal uc_round_mode_l2 : std_ulogic_vector(0 to 7); +signal uc_round_mode_scin : std_ulogic_vector(0 to 7); +signal uc_round_mode_scout : std_ulogic_vector(0 to 7); +signal uc_mid_rf1 : std_ulogic; +signal uc_end_rf1 : std_ulogic; +signal uc_end_rf1_v : std_ulogic; +signal uc_end_ex1 : std_ulogic; +signal uc_end_ex2 : std_ulogic; +signal uc_end_ex3 : std_ulogic; +signal uc_end_ex4 : std_ulogic; +signal uc_end_ex5 : std_ulogic; +signal uc_end_rf1_l2 : std_ulogic; +signal uc_end_ex1_l2 : std_ulogic; +signal uc_end_ex2_l2 : std_ulogic; +signal uc_end_ex3_l2 : std_ulogic; +signal uc_end_ex4_l2 : std_ulogic; +signal uc_end_ex5_l2 : std_ulogic; +signal uc_end_ex6_l2 : std_ulogic; +signal uc_fa_pos_rf1 : std_ulogic; +signal uc_fc_pos_rf1 : std_ulogic; +signal uc_fb_pos_rf1 : std_ulogic; +signal uc_fc_hulp_rf1 : std_ulogic; +signal uc_fc_0_5_rf1 : std_ulogic; +signal uc_fc_1_0_rf1 : std_ulogic; +signal uc_fc_1_minus_rf1 : std_ulogic; +signal uc_fb_1_0_rf1 : std_ulogic; +signal uc_fb_0_75_rf1 : std_ulogic; +signal uc_fb_0_5_rf1 : std_ulogic; +signal uc_fa_dis_par_rf0, uc_fa_dis_par_rf1 : std_ulogic; +signal uc_fb_dis_par_rf0, uc_fb_dis_par_rf1 : std_ulogic; +signal uc_fc_dis_par_rf0, uc_fc_dis_par_rf1 : std_ulogic; +signal uc_op_rnd_v_rf1_l2 : std_ulogic; +signal uc_op_rnd_rf1_l2 : std_ulogic_vector(0 to 1); + +signal uc_inc_lsb_rf1 : std_ulogic; +signal uc_gs_v_rf1 : std_ulogic; +signal special_rf1 : std_ulogic; +signal spare : std_ulogic; +signal q1r_zero_ex2 : std_ulogic; +signal q1r_sign_ex2 : std_ulogic; +signal q1ulpr_sign_ex2 : std_ulogic; +signal q1ulpr_zero_ex2 : std_ulogic; +signal q1hulpr_sign_ex2 : std_ulogic; +signal uc_gs_ex2 : std_ulogic_vector(0 to 1); +signal uc_round_mode_ex2 : std_ulogic_vector(0 to 1); +signal uc_gs_v_ex1 : std_ulogic; +signal uc_gs_v_ex2 : std_ulogic; +signal uc_inc_lsb_ex1 : std_ulogic; +signal uc_inc_lsb_ex2 : std_ulogic; +signal res_sign_rf1 : std_ulogic; +signal uc_scr_wr_ex4_ld : std_ulogic; +signal rf0_i : std_ulogic_vector(0 to 31); +signal uc_fdiv_beg_rf0 : std_ulogic; +signal uc_fdivs_beg_rf0 : std_ulogic; +signal uc_fsqrt_beg_rf0 : std_ulogic; +signal uc_fsqrts_beg_rf0 : std_ulogic; +signal uc_op_rf0 : std_ulogic_vector(0 to 3); +signal q1_p_ulp_early_ld, q1_p_ulp_early_l2 : std_ulogic_vector(0 to 3); +signal q1_p_ulp_early_scin, q1_p_ulp_early_scout : std_ulogic_vector(0 to 3); + +signal rf1_ucfmul : std_ulogic; + +signal fmulx_uc_rf0, uc_dvsq_beg_rf0 : std_ulogic; +signal uc_abort_rf0 : std_ulogic_vector(0 to 3); +signal rf0_instr_flush : std_ulogic; +signal rf1_instr_flush : std_ulogic; +signal ex1_instr_flush : std_ulogic; +signal ex2_instr_flush : std_ulogic; +signal ex3_instr_flush : std_ulogic; +signal ex3_instr_flush_th : std_ulogic_vector(0 to 3); +signal ex4_instr_flush : std_ulogic; +signal ex5_instr_flush : std_ulogic; + + signal uc_scr_t0_fbk_x , uc_scr_t1_fbk_x , uc_scr_t2_fbk_x , uc_scr_t3_fbk_x :std_ulogic; + signal uc_scr_t0_ld_x , uc_scr_t1_ld_x , uc_scr_t2_ld_x , uc_scr_t3_ld_x :std_ulogic_vector(0 to 11); + + signal uc_scr_t0_ld_x0_b :std_ulogic_vector(0 to 11); + signal uc_scr_t1_ld_x0_b :std_ulogic_vector(0 to 11); + signal uc_scr_t2_ld_x0_b :std_ulogic_vector(0 to 11); + signal uc_scr_t3_ld_x0_b :std_ulogic_vector(0 to 11); + signal uc_scr_t0_ld_x1_b :std_ulogic_vector(0 to 11); + signal uc_scr_t1_ld_x1_b :std_ulogic_vector(0 to 11); + signal uc_scr_t2_ld_x1_b :std_ulogic_vector(0 to 11); + signal uc_scr_t3_ld_x1_b :std_ulogic_vector(0 to 11); + signal uc_scr_t0_ld_x2_b :std_ulogic_vector(0 to 11); + signal uc_scr_t1_ld_x2_b :std_ulogic_vector(0 to 11); + signal uc_scr_t2_ld_x2_b :std_ulogic_vector(0 to 11); + signal uc_scr_t3_ld_x2_b :std_ulogic_vector(0 to 11); + signal uc_scr_t0_ld_x3_b :std_ulogic_vector(0 to 11); + signal uc_scr_t1_ld_x3_b :std_ulogic_vector(0 to 11); + signal uc_scr_t2_ld_x3_b :std_ulogic_vector(0 to 11); + signal uc_scr_t3_ld_x3_b :std_ulogic_vector(0 to 11); + signal uc_scr_t0_ld_x4_b :std_ulogic_vector(0 to 11); + signal uc_scr_t1_ld_x4_b :std_ulogic_vector(0 to 11); + signal uc_scr_t2_ld_x4_b :std_ulogic_vector(0 to 11); + signal uc_scr_t3_ld_x4_b :std_ulogic_vector(0 to 11); + signal uc_scr_t0_ld_xf_b :std_ulogic_vector(0 to 11); + signal uc_scr_t1_ld_xf_b :std_ulogic_vector(0 to 11); + signal uc_scr_t2_ld_xf_b :std_ulogic_vector(0 to 11); + signal uc_scr_t3_ld_xf_b :std_ulogic_vector(0 to 11); + signal uc_scr_t0_oth_b :std_ulogic_vector(0 to 11); + signal uc_scr_t1_oth_b :std_ulogic_vector(0 to 11); + signal uc_scr_t2_oth_b :std_ulogic_vector(0 to 11); + signal uc_scr_t3_oth_b :std_ulogic_vector(0 to 11); + + +---------------------------------- +signal uc_1st_v_th_b :std_ulogic_vector(0 to 3); +signal fdiving_n1st_th :std_ulogic_vector(0 to 3); +signal fdivsing_n1st_th :std_ulogic_vector(0 to 3); +signal fsqrting_n1st_th :std_ulogic_vector(0 to 3); +signal fsqrtsing_n1st_th :std_ulogic_vector(0 to 3); +signal uc_mode_rf0_th :std_ulogic_vector(0 to 3); +signal rf0_n1st_fdiving :std_ulogic; +signal rf0_n1st_fdivsing :std_ulogic; +signal rf0_n1st_fsqrting :std_ulogic; +signal rf0_n1st_fsqrtsing :std_ulogic; +signal rf0_ifar_dcd :std_ulogic_vector(1 to 12); +signal rf0_ifar_89 :std_ulogic; +signal rf0_ifar_45 :std_ulogic; +signal rf0_ifar_34 :std_ulogic; +signal rf0_ifar_78 :std_ulogic; +signal rf0_ifar_bc :std_ulogic; +signal rf0_ifar_67 :std_ulogic; +signal rf0_ifar_ab :std_ulogic; +signal rf0_ifar_ac :std_ulogic; +signal rf0_ifar_57 :std_ulogic; +signal rf0_ifar_9b :std_ulogic; +signal rf0_ifar_68 :std_ulogic; +signal rf0_ifar_abc :std_ulogic; +signal rf0_ifar_567 :std_ulogic; +signal rf0_ifar_9ab :std_ulogic; +signal rf0_ifar_678 :std_ulogic; +signal rf0_ifar_1245abc :std_ulogic; +signal rf0_ifar_13456abc :std_ulogic; +signal rf0_ifar_134567 :std_ulogic; +signal rf0_ifar_123c :std_ulogic; +signal rf0_ifar_12 :std_ulogic; +signal rf0_ifar_13 :std_ulogic; + + signal q1_p_ulp_th :std_ulogic_vector(0 to 3); + signal iu_fu_rf0_ucfmul_b :std_ulogic; +signal rf0_q1_p_ulp_mux0_b, rf0_q1_p_ulp_mux1_b, rf0_q1_p_ulp_mux :std_ulogic; +signal rf0_fra_fast_mux0_b, rf0_fra_fast_mux1_b, rf0_fra_fast_mux :std_ulogic_vector(4 to 4); +signal rf0_fra_fast_b, rf0_fra_fast :std_ulogic_vector(4 to 4); + signal rf0_fra_fast_i_b, rf0_fra_fast_ii :std_ulogic_vector(4 to 4); + +signal rf0_f2_dvsq , rf0_f2_dv , rf0_f2_sq , rf0_f2_mul :std_ulogic ; + + signal spare_unused : std_ulogic_vector(0 to 21); + + + +begin + +-- ucmode=0 on last iteration but uc_scr_t*_l2(7) won't have been cleared yet +uc_mid_rf0 <= (uc_scr_t0_l2(7) and thread_id_rf0(0) and ucode_mode_rf0) or + (uc_scr_t1_l2(7) and thread_id_rf0(1) and ucode_mode_rf0) or + (uc_scr_t2_l2(7) and thread_id_rf0(2) and ucode_mode_rf0) or + (uc_scr_t3_l2(7) and thread_id_rf0(3) and ucode_mode_rf0); + + + + +-- update # of inputs and outputs .i xx .o xx +-- run "espvhdlexpand fuq_dcd_uc_hooks.vhdl > fuq_dcd_uc_hooks_new.vhdl" in a typescript to regenerate logic below table +--@@ ESPRESSO ABLE START @@ +-- .i 9 +-- .o 18 +-- .ilb uc_1st_instr_rf0 fdiving_rf0 fdivsing_rf0 fsqrting_rf0 fsqrtsing_rf0 iu_fu_rf0_ifar(58) +-- iu_fu_rf0_ifar(59) iu_fu_rf0_ifar(60) iu_fu_rf0_ifar(61) +-- .ob uc_fa_pos uc_fc_pos uc_fb_pos uc_fc_0_5 +-- uc_fc_hulp uc_fb_1_0 uc_fb_0_75 uc_fb_0_5 uc_fa_dis_par_rf0 uc_fb_dis_par_rf0 uc_fc_dis_par_rf0 +-- uc_op_rnd_v uc_op_rnd(0) uc_op_rnd(1) uc_inc_lsb uc_scr_wr uc_scr_sel(0) uc_scr_sel(1) +-- .type fr +-- # +-- ################################################################################################################################## +-- # +-- # uc_1st_instr_rf0 # OUTPUTS ################################################################################## +-- # | 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +-- # | fdiving_rf0 uc_fa_pos uc_op_rnd_v +-- # | | fdivsing_rf0 | uc_fc_pos | uc_op_rnd(0:1) +-- # | | | | | uc_fb_pos uc_fa_dis_par_rf0 | | +-- # | | | fsqrting_rf0 | | | uc_fc_0_5 | uc_fb_dis_par_rf0 | | +-- # | | | | fsqrtsing_rf0 | | | | uc_fc_hulp | | uc_fc_dis_par_rf0 | | uc_inc_lsb +-- # | | | | | | | | | | uc_fb_1_0 | | | | | | +-- # | | | | | iu_fu_rf0_ifar | | | | | | uc_fb_0_75 | | | | | | uc_scr_wr +-- # | | | | | | | | | | | | | uc_fb_0_5 | | | | | | | uc_scr_sel +-- # | | | | | | | | | | | | | | | | | | | | | | +-- # | | | | | 5566 | | | | | | | | | | | | | | | | +-- # | | | | | 8901 | | | | | | | | | | | | | | | | +-- ######################################################################################################################################## +-- #--------------------------------------------------------------------------------------------------------------------------- not div or sqrt +-- 0 0 0 0 0 ---- 0 0 0 0 0 0 0 0 0 0 0 0 -- 0 0 00 +-- #--------------------------------------------------------------------------------------------------------------------------- shared +-- 1 - - - - ---- 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 00 # fre for fdiv(s), frsqrte for fsqrt(s) +-- #------ fdiv hooks --------------------------------------------------------------------------------------------------------- fdiv hooks +-- 0 1 0 0 0 0001 1 1 1 0 0 1 0 0 1 1 1 1 00 0 0 00 # fnmsub +-- 0 1 0 0 0 0010 1 1 0 0 0 0 0 0 1 0 1 1 00 0 0 00 # fmul +-- 0 1 0 0 0 0011 0 0 1 0 0 0 0 1 0 1 1 1 00 0 0 00 # fmadd +-- 0 1 0 0 0 0100 1 0 1 0 0 0 0 0 1 1 0 1 00 0 0 00 # fmadd +-- 0 1 0 0 0 0101 1 0 1 0 0 0 0 0 1 1 0 1 00 0 0 00 # fnmsub +-- 0 1 0 0 0 0110 0 0 1 0 0 0 1 0 0 1 0 1 00 0 0 00 # fmadd +-- 0 1 0 0 0 0111 0 0 0 0 0 0 0 0 0 0 0 1 00 0 0 00 # fmul +-- 0 1 0 0 0 1000 0 0 0 0 0 0 0 0 0 0 0 1 01 0 0 00 # fmadd +-- 0 1 0 0 0 1001 0 0 0 0 0 0 0 0 0 0 0 1 01 1 0 00 # fmadd +-- 0 1 0 0 0 1010 1 0 1 0 0 0 0 0 1 1 0 1 00 0 1 01 # fnmsub +-- 0 1 0 0 0 1011 1 0 1 0 0 0 0 0 1 1 0 1 00 0 1 10 # fnmsub +-- 0 1 0 0 0 1100 1 0 1 0 1 0 0 0 1 1 1 1 00 0 1 11 # fnmsub +-- # 0 0 0 0 0 1101 0 0 0 0 0 0 0 0 0 0 1 0 -- 0 0 00 # fmul_uc +-- #------ fdivs hooks -------------------------------------------------------------------------------------------------------- fdivs hooks +-- 0 0 1 0 0 0001 1 1 1 0 0 1 0 0 1 1 1 1 00 0 0 00 # fnmsub +-- 0 0 1 0 0 0010 1 1 0 0 0 0 0 0 1 0 1 1 00 0 0 00 # fmul +-- 0 0 1 0 0 0011 1 0 1 0 0 0 0 0 1 1 0 1 01 0 0 00 # fmadds +-- 0 0 1 0 0 0100 1 0 1 0 0 0 0 0 1 1 0 1 01 1 0 00 # fmadds +-- 0 0 1 0 0 0101 1 0 1 0 0 0 0 0 1 1 0 1 00 0 1 01 # fnmsub +-- 0 0 1 0 0 0110 1 0 1 0 0 0 0 0 1 1 0 1 00 0 1 10 # fnmsub +-- 0 0 1 0 0 0111 1 0 1 0 1 0 0 0 1 1 0 1 00 0 1 11 # fnmsub +-- # 0 0 0 0 0 1000 0 0 0 0 0 0 0 0 0 0 0 0 -- 0 0 00 # fmuls_uc +-- #------ fsqrt hooks -------------------------------------------------------------------------------------------------------- fsqrt hooks +-- 0 0 0 1 0 0001 0 1 0 1 0 0 0 0 0 0 1 1 00 0 0 00 # fmul +-- 0 0 0 1 0 0010 0 0 0 0 0 0 0 0 0 0 0 1 00 0 0 00 # fmul +-- 0 0 0 1 0 0011 0 0 1 0 0 0 0 1 0 1 1 1 00 0 0 00 # fnmsub +-- 0 0 0 1 0 0100 0 0 0 0 0 0 0 0 0 0 0 1 00 0 0 00 # fmadd +-- 0 0 0 1 0 0101 0 0 0 0 0 0 0 0 0 0 0 1 00 0 0 00 # fmadd +-- 0 0 0 1 0 0110 0 0 0 0 0 0 0 0 0 0 0 1 00 0 0 00 # fnmsub +-- 0 0 0 1 0 0111 0 0 0 0 0 0 0 0 0 0 0 1 01 0 0 00 # fmadd +-- 0 0 0 1 0 1000 0 0 0 0 0 0 0 0 0 0 0 1 01 1 0 00 # fmadd +-- 0 0 0 1 0 1001 0 0 0 0 0 0 0 0 0 0 0 1 00 0 1 01 # fnmsub +-- 0 0 0 1 0 1010 0 0 0 0 0 0 0 0 0 0 0 1 00 0 1 10 # fnmsub +-- 0 0 0 1 0 1011 0 0 0 0 0 0 0 0 0 0 0 1 00 0 1 11 # fnmsub +-- # 0 0 0 0 0 1100 0 0 0 0 0 0 0 0 0 0 0 0 -- 0 0 00 # fmul_uc +-- #------ fsqrts hooks ------------------------------------------------------------------------------------------------------- fsqrts hooks +-- 0 0 0 0 1 0001 0 1 0 1 0 0 0 0 0 0 1 1 00 0 0 00 # fmul +-- 0 0 0 0 1 0010 0 0 0 0 0 0 0 0 0 0 0 1 00 0 0 00 # fmul +-- 0 0 0 0 1 0011 0 0 0 0 0 0 0 0 0 0 0 1 00 0 0 00 # fnmsub +-- 0 0 0 0 1 0100 0 0 0 0 0 0 0 0 0 0 0 1 01 0 0 00 # fmadd +-- 0 0 0 0 1 0101 0 0 0 0 0 0 0 0 0 0 0 1 01 1 0 00 # fmadd +-- 0 0 0 0 1 0110 0 0 0 0 0 0 0 0 0 0 0 1 00 0 1 01 # fnmsub +-- 0 0 0 0 1 0111 0 0 0 0 0 0 0 0 0 0 0 1 00 0 1 10 # fnmsub +-- 0 0 0 0 1 1000 0 0 0 0 0 0 0 0 0 0 0 1 00 0 1 11 # fnmsub +-- # 0 0 0 0 0 1001 0 0 0 0 0 0 0 0 0 0 0 0 -- 0 0 00 # fmuls_uc +-- +-- +-- +-- +-- +-- +-- +-- +-- .e +--@@ ESPRESSO ABLE END @@ + +--/////////////////////////////////////////////////////////////////////// +--// begin experiment +--/////////////////////////////////////////////////////////////////////// + +uc_1st_v_th_b(0) <= not( iu_fu_rf0_instr_v and uc_1st_instr_l2(0) ); +uc_1st_v_th_b(1) <= not( iu_fu_rf0_instr_v and uc_1st_instr_l2(1) ); +uc_1st_v_th_b(2) <= not( iu_fu_rf0_instr_v and uc_1st_instr_l2(2) ); +uc_1st_v_th_b(3) <= not( iu_fu_rf0_instr_v and uc_1st_instr_l2(3) ); + + +fdiving_n1st_th(0) <= uc_scr_t0_l2(8) and uc_1st_v_th_b(0) ; +fdiving_n1st_th(1) <= uc_scr_t1_l2(8) and uc_1st_v_th_b(1) ; +fdiving_n1st_th(2) <= uc_scr_t2_l2(8) and uc_1st_v_th_b(2) ; +fdiving_n1st_th(3) <= uc_scr_t3_l2(8) and uc_1st_v_th_b(3) ; + +fdivsing_n1st_th(0) <= uc_scr_t0_l2(9) and uc_1st_v_th_b(0) ; +fdivsing_n1st_th(1) <= uc_scr_t1_l2(9) and uc_1st_v_th_b(1) ; +fdivsing_n1st_th(2) <= uc_scr_t2_l2(9) and uc_1st_v_th_b(2) ; +fdivsing_n1st_th(3) <= uc_scr_t3_l2(9) and uc_1st_v_th_b(3) ; + +fsqrting_n1st_th(0) <= uc_scr_t0_l2(10) and uc_1st_v_th_b(0) ; +fsqrting_n1st_th(1) <= uc_scr_t1_l2(10) and uc_1st_v_th_b(1) ; +fsqrting_n1st_th(2) <= uc_scr_t2_l2(10) and uc_1st_v_th_b(2) ; +fsqrting_n1st_th(3) <= uc_scr_t3_l2(10) and uc_1st_v_th_b(3) ; + +fsqrtsing_n1st_th(0) <= uc_scr_t0_l2(11) and uc_1st_v_th_b(0) ; +fsqrtsing_n1st_th(1) <= uc_scr_t1_l2(11) and uc_1st_v_th_b(1) ; +fsqrtsing_n1st_th(2) <= uc_scr_t2_l2(11) and uc_1st_v_th_b(2) ; +fsqrtsing_n1st_th(3) <= uc_scr_t3_l2(11) and uc_1st_v_th_b(3) ; + +uc_mode_rf0_th(0 to 3) <= thread_id_rf0(0 to 3) and (0 to 3=> ucode_mode_rf0 ); + + +rf0_n1st_fdiving <= (uc_mode_rf0_th(0) and fdiving_n1st_th(0) ) or + (uc_mode_rf0_th(1) and fdiving_n1st_th(1) ) or + (uc_mode_rf0_th(2) and fdiving_n1st_th(2) ) or + (uc_mode_rf0_th(3) and fdiving_n1st_th(3) ) ; + +rf0_n1st_fdivsing <= (uc_mode_rf0_th(0) and fdivsing_n1st_th(0) ) or + (uc_mode_rf0_th(1) and fdivsing_n1st_th(1) ) or + (uc_mode_rf0_th(2) and fdivsing_n1st_th(2) ) or + (uc_mode_rf0_th(3) and fdivsing_n1st_th(3) ) ; + +rf0_n1st_fsqrting <= (uc_mode_rf0_th(0) and fsqrting_n1st_th(0) ) or + (uc_mode_rf0_th(1) and fsqrting_n1st_th(1) ) or + (uc_mode_rf0_th(2) and fsqrting_n1st_th(2) ) or + (uc_mode_rf0_th(3) and fsqrting_n1st_th(3) ) ; + +rf0_n1st_fsqrtsing <= (uc_mode_rf0_th(0) and fsqrtsing_n1st_th(0) ) or + (uc_mode_rf0_th(1) and fsqrtsing_n1st_th(1) ) or + (uc_mode_rf0_th(2) and fsqrtsing_n1st_th(2) ) or + (uc_mode_rf0_th(3) and fsqrtsing_n1st_th(3) ) ; + + + + rf0_ifar_dcd(1) <= not iu_fu_rf0_ifar(58) and not iu_fu_rf0_ifar(59) and not iu_fu_rf0_ifar(60) and iu_fu_rf0_ifar(61) ; + rf0_ifar_dcd(2) <= not iu_fu_rf0_ifar(58) and not iu_fu_rf0_ifar(59) and iu_fu_rf0_ifar(60) and not iu_fu_rf0_ifar(61) ; + rf0_ifar_dcd(3) <= not iu_fu_rf0_ifar(58) and not iu_fu_rf0_ifar(59) and iu_fu_rf0_ifar(60) and iu_fu_rf0_ifar(61) ; + rf0_ifar_dcd(4) <= not iu_fu_rf0_ifar(58) and iu_fu_rf0_ifar(59) and not iu_fu_rf0_ifar(60) and not iu_fu_rf0_ifar(61) ; + rf0_ifar_dcd(5) <= not iu_fu_rf0_ifar(58) and iu_fu_rf0_ifar(59) and not iu_fu_rf0_ifar(60) and iu_fu_rf0_ifar(61) ; + rf0_ifar_dcd(6) <= not iu_fu_rf0_ifar(58) and iu_fu_rf0_ifar(59) and iu_fu_rf0_ifar(60) and not iu_fu_rf0_ifar(61) ; + rf0_ifar_dcd(7) <= not iu_fu_rf0_ifar(58) and iu_fu_rf0_ifar(59) and iu_fu_rf0_ifar(60) and iu_fu_rf0_ifar(61) ; + rf0_ifar_dcd(8) <= iu_fu_rf0_ifar(58) and not iu_fu_rf0_ifar(59) and not iu_fu_rf0_ifar(60) and not iu_fu_rf0_ifar(61) ; + rf0_ifar_dcd(9) <= iu_fu_rf0_ifar(58) and not iu_fu_rf0_ifar(59) and not iu_fu_rf0_ifar(60) and iu_fu_rf0_ifar(61) ; + rf0_ifar_dcd(10) <= iu_fu_rf0_ifar(58) and not iu_fu_rf0_ifar(59) and iu_fu_rf0_ifar(60) and not iu_fu_rf0_ifar(61) ; + rf0_ifar_dcd(11) <= iu_fu_rf0_ifar(58) and not iu_fu_rf0_ifar(59) and iu_fu_rf0_ifar(60) and iu_fu_rf0_ifar(61) ; + rf0_ifar_dcd(12) <= iu_fu_rf0_ifar(58) and iu_fu_rf0_ifar(59) and not iu_fu_rf0_ifar(60) and not iu_fu_rf0_ifar(61) ; + + rf0_ifar_89 <= rf0_ifar_dcd(8) or rf0_ifar_dcd(9) ; + rf0_ifar_45 <= rf0_ifar_dcd(4) or rf0_ifar_dcd(5) ; + rf0_ifar_34 <= rf0_ifar_dcd(3) or rf0_ifar_dcd(4) ; + rf0_ifar_78 <= rf0_ifar_dcd(7) or rf0_ifar_dcd(8) ; + rf0_ifar_bc <= rf0_ifar_dcd(11) or rf0_ifar_dcd(12) ; + rf0_ifar_67 <= rf0_ifar_dcd(6) or rf0_ifar_dcd(7) ; + rf0_ifar_ab <= rf0_ifar_dcd(10) or rf0_ifar_dcd(11) ; + rf0_ifar_ac <= rf0_ifar_dcd(10) or rf0_ifar_dcd(12) ; + rf0_ifar_57 <= rf0_ifar_dcd(5) or rf0_ifar_dcd(7) ; + rf0_ifar_9b <= rf0_ifar_dcd(9) or rf0_ifar_dcd(11) ; + rf0_ifar_68 <= rf0_ifar_dcd(6) or rf0_ifar_dcd(8) ; + rf0_ifar_abc <= rf0_ifar_dcd(10) or rf0_ifar_dcd(11) or rf0_ifar_dcd(12) ; + rf0_ifar_567 <= rf0_ifar_dcd(5) or rf0_ifar_dcd(6) or rf0_ifar_dcd(7) ; + rf0_ifar_9ab <= rf0_ifar_dcd(9) or rf0_ifar_dcd(10) or rf0_ifar_dcd(11) ; + rf0_ifar_678 <= rf0_ifar_dcd(6) or rf0_ifar_dcd(7) or rf0_ifar_dcd(8) ; + rf0_ifar_1245abc <= rf0_ifar_dcd(1) or rf0_ifar_dcd(2) or rf0_ifar_dcd(4) or rf0_ifar_dcd(5) or rf0_ifar_dcd(10) or rf0_ifar_dcd(11) or rf0_ifar_dcd(12); + rf0_ifar_13456abc <= rf0_ifar_dcd(1) or rf0_ifar_dcd(3) or rf0_ifar_dcd(4) or rf0_ifar_dcd(5) or rf0_ifar_dcd(6) or rf0_ifar_dcd(10) or rf0_ifar_dcd(11) or rf0_ifar_dcd(12); + rf0_ifar_134567 <= rf0_ifar_dcd(1) or rf0_ifar_dcd(3) or rf0_ifar_dcd(4) or rf0_ifar_dcd(5) or rf0_ifar_dcd(6) or rf0_ifar_dcd(7); + rf0_ifar_123c <= rf0_ifar_dcd(1) or rf0_ifar_dcd(2) or rf0_ifar_dcd(12) ; + rf0_ifar_12 <= rf0_ifar_dcd(1) or rf0_ifar_dcd(2) ; + rf0_ifar_13 <= rf0_ifar_dcd(1) or rf0_ifar_dcd(3) ; + +------------------------------------------------------------------------ + + uc_op_rnd_v <= + (rf0_n1st_fdiving and tiup ) or + (rf0_n1st_fdivsing and tiup ) or + (rf0_n1st_fsqrting and tiup ) or + (rf0_n1st_fsqrtsing and tiup ) ; + + uc_op_rnd(0) <= '0'; + + uc_op_rnd(1) <= + (rf0_n1st_fdiving and rf0_ifar_89 ) or + (rf0_n1st_fdivsing and rf0_ifar_34 ) or + (rf0_n1st_fsqrting and rf0_ifar_78 ) or + (rf0_n1st_fsqrtsing and rf0_ifar_45 ) ; + + uc_inc_lsb <= + (rf0_n1st_fdiving and rf0_ifar_dcd(9) ) or + (rf0_n1st_fdivsing and rf0_ifar_dcd(4) ) or + (rf0_n1st_fsqrting and rf0_ifar_dcd(8) ) or + (rf0_n1st_fsqrtsing and rf0_ifar_dcd(5) ) ; + + uc_scr_sel(0) <= + (rf0_n1st_fdiving and rf0_ifar_bc ) or + (rf0_n1st_fdivsing and rf0_ifar_67 ) or + (rf0_n1st_fsqrting and rf0_ifar_ab ) or + (rf0_n1st_fsqrtsing and rf0_ifar_78 ) ; + + uc_scr_sel(1) <= + (rf0_n1st_fdiving and rf0_ifar_ac ) or + (rf0_n1st_fdivsing and rf0_ifar_57 ) or + (rf0_n1st_fsqrting and rf0_ifar_9b ) or + (rf0_n1st_fsqrtsing and rf0_ifar_68 ) ; + + uc_scr_wr <= + (rf0_n1st_fdiving and rf0_ifar_abc ) or + (rf0_n1st_fdivsing and rf0_ifar_567 ) or + (rf0_n1st_fsqrting and rf0_ifar_9ab ) or + (rf0_n1st_fsqrtsing and rf0_ifar_678 ) ; + + uc_fa_dis_par_rf0 <= + (rf0_n1st_fdiving and rf0_ifar_1245abc ) or + (rf0_n1st_fdivsing and tiup ) or + (rf0_n1st_fsqrting and tidn ) or + (rf0_n1st_fsqrtsing and tidn ) ; + + uc_fb_dis_par_rf0 <= + (rf0_n1st_fdiving and rf0_ifar_13456abc ) or + (rf0_n1st_fdivsing and rf0_ifar_134567 ) or + (rf0_n1st_fsqrting and rf0_ifar_dcd(3) ) or + (rf0_n1st_fsqrtsing and tidn ) ; + + uc_fc_dis_par_rf0 <= + (rf0_n1st_fdiving and rf0_ifar_123c ) or + (rf0_n1st_fdivsing and rf0_ifar_12 ) or + (rf0_n1st_fsqrting and rf0_ifar_13 ) or + (rf0_n1st_fsqrtsing and rf0_ifar_dcd(1) ) ; + + uc_fa_pos <= + (rf0_n1st_fdiving and rf0_ifar_1245abc ) or + (rf0_n1st_fdivsing and tiup ) or + (rf0_n1st_fsqrting and tidn ) or + (rf0_n1st_fsqrtsing and tidn ) ; + + uc_fc_pos <= + (rf0_n1st_fdiving and rf0_ifar_12 ) or + (rf0_n1st_fdivsing and rf0_ifar_12 ) or + (rf0_n1st_fsqrting and rf0_ifar_dcd(1) ) or + (rf0_n1st_fsqrtsing and rf0_ifar_dcd(1) ) ; + + uc_fb_pos <= + (rf0_n1st_fdiving and rf0_ifar_13456abc) or + (rf0_n1st_fdivsing and rf0_ifar_134567 ) or + (rf0_n1st_fsqrting and rf0_ifar_dcd(3) ) or + (rf0_n1st_fsqrtsing and tidn ) ; + + uc_fc_0_5 <= + (rf0_n1st_fdiving and tidn ) or + (rf0_n1st_fdivsing and tidn ) or + (rf0_n1st_fsqrting and rf0_ifar_dcd(1) ) or + (rf0_n1st_fsqrtsing and rf0_ifar_dcd(1) ) ; + + uc_fc_hulp <= + (rf0_n1st_fdiving and rf0_ifar_dcd(12) ) or + (rf0_n1st_fdivsing and rf0_ifar_dcd(7) ) or + (rf0_n1st_fsqrting and tidn ) or + (rf0_n1st_fsqrtsing and tidn ) ; + + uc_fb_1_0 <= + (rf0_n1st_fdiving and rf0_ifar_dcd(1) ) or + (rf0_n1st_fdivsing and rf0_ifar_dcd(1) ) or + (rf0_n1st_fsqrting and tidn ) or + (rf0_n1st_fsqrtsing and tidn ) ; + + uc_fb_0_75 <= + (rf0_n1st_fdiving and rf0_ifar_dcd(6) ) or + (rf0_n1st_fdivsing and tidn ) or + (rf0_n1st_fsqrting and tidn ) or + (rf0_n1st_fsqrtsing and tidn ) ; + + uc_fb_0_5 <= + (rf0_n1st_fdiving and rf0_ifar_dcd(3) ) or + (rf0_n1st_fdivsing and tidn ) or + (rf0_n1st_fsqrting and rf0_ifar_dcd(3) ) or + (rf0_n1st_fsqrtsing and tidn ) ; + + + + + + +--/////////////////////////////////////////////////////////////////////// +--// end experiment +--/////////////////////////////////////////////////////////////////////// + + + + + + + + +uc_1st_instr_ld(0) <= uc_beg_rf0 when iu_fu_rf0_instr_v='1' and uc_scr_thread_rf0 = "00" else + uc_1st_instr_l2(0); + +uc_1st_instr_ld(1) <= uc_beg_rf0 when iu_fu_rf0_instr_v='1' and uc_scr_thread_rf0 = "01" else + uc_1st_instr_l2(1); + +uc_1st_instr_ld(2) <= uc_beg_rf0 when iu_fu_rf0_instr_v='1' and uc_scr_thread_rf0 = "10" else + uc_1st_instr_l2(2); + +uc_1st_instr_ld(3) <= uc_beg_rf0 when iu_fu_rf0_instr_v='1' and uc_scr_thread_rf0 = "11" else + uc_1st_instr_l2(3); + + + + + + +-- this register is used to force the ifar to 0000 on the first instruction of a ucode routine (table lookup) +-- subsequent instructions will already have ifar = 1,2,3 etc. + uc_1st_instr_reg: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 4) + port map ( + nclk => nclk, act => msr_fp_act, + vd => vdd, gd => gnd, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + thold_b => thold_0_b, sg => sg_0, + scin => uc_1st_instr_scin, + scout => uc_1st_instr_scout, + --------------------------------------------- + din(0 to 3) => uc_1st_instr_ld, + + --------------------------------------------- + dout(0 to 3) => uc_1st_instr_l2 + + --------------------------------------------- + ); + + + + + +-- +-- The first uc instruction of fdiv/fsqrt is fre or frsqrte, otherwise abort, it could be a prenorm for a previous instr +uc_abort_rf0(0) <= uc_1st_instr_l2(0) and not((iu_fu_rf0_instr(26 to 28) = "110") and iu_fu_rf0_instr(30) = '0'); +uc_abort_rf0(1) <= uc_1st_instr_l2(1) and not((iu_fu_rf0_instr(26 to 28) = "110") and iu_fu_rf0_instr(30) = '0'); +uc_abort_rf0(2) <= uc_1st_instr_l2(2) and not((iu_fu_rf0_instr(26 to 28) = "110") and iu_fu_rf0_instr(30) = '0'); +uc_abort_rf0(3) <= uc_1st_instr_l2(3) and not((iu_fu_rf0_instr(26 to 28) = "110") and iu_fu_rf0_instr(30) = '0'); + + + + + + + + + +uc_normal_end_rf0_part <= ((not uc_scr_t0_l2(0) and thread_id_rf0(0)) or + (not uc_scr_t1_l2(0) and thread_id_rf0(1)) or + (not uc_scr_t2_l2(0) and thread_id_rf0(2)) or + (not uc_scr_t3_l2(0) and thread_id_rf0(3))); + +uc_normal_end_rf0 <= uc_end_rf0_v and uc_normal_end_rf0_part; + + + +uc_gs_v_rf0 <= uc_normal_end_rf0; + + + + + + +uc_round_mode_ld(0 to 1) <= f_mad_ex3_uc_round_mode when uc_scr_wr_ex3 = '1' and uc_scr_sel_ex3 = "00" and uc_scr_thread_ex3 = "00" else + uc_round_mode_l2(0 to 1); + +uc_round_mode_ld(2 to 3) <= f_mad_ex3_uc_round_mode when uc_scr_wr_ex3 = '1' and uc_scr_sel_ex3 = "00" and uc_scr_thread_ex3 = "01" else + uc_round_mode_l2(2 to 3); + +uc_round_mode_ld(4 to 5) <= f_mad_ex3_uc_round_mode when uc_scr_wr_ex3 = '1' and uc_scr_sel_ex3 = "00" and uc_scr_thread_ex3 = "10" else + uc_round_mode_l2(4 to 5); + +uc_round_mode_ld(6 to 7) <= f_mad_ex3_uc_round_mode when uc_scr_wr_ex3 = '1' and uc_scr_sel_ex3 = "00" and uc_scr_thread_ex3 = "11" else + uc_round_mode_l2(6 to 7); + + uc_round_mode_reg: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 8) + port map ( + nclk => nclk, act => msr_fp_act, + vd => vdd, gd => gnd, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + thold_b => thold_0_b, sg => sg_0, + scin => uc_round_mode_scin, + scout => uc_round_mode_scout, + --------------------------------------------- + din(0 to 7) => uc_round_mode_ld, + + --------------------------------------------- + dout(0 to 7) => uc_round_mode_l2 + + --------------------------------------------- + ); + + + +uc_special_cases_ex3(0) <= f_mad_ex3_uc_special; -- '1' indicates special case (not handled by ucode) +uc_special_cases_ex3(1) <= f_mad_ex3_uc_res_sign; -- not really a special case but the cycle timing lines up here +uc_special_cases_ex3(2 to 7) <= f_mad_ex3_uc_vxsnan & f_mad_ex3_uc_zx & f_mad_ex3_uc_vxidi & f_mad_ex3_uc_vxzdz & f_mad_ex3_uc_vxsqrt & '1'; + +uc_special_cases_t0_ex3(8 to 11) <= "0000" when f_mad_ex3_uc_special='1' else + uc_scr_t0_l2(8 to 11); +uc_special_cases_t1_ex3(8 to 11) <= "0000" when f_mad_ex3_uc_special='1' else + uc_scr_t1_l2(8 to 11); +uc_special_cases_t2_ex3(8 to 11) <= "0000" when f_mad_ex3_uc_special='1' else + uc_scr_t2_l2(8 to 11); +uc_special_cases_t3_ex3(8 to 11) <= "0000" when f_mad_ex3_uc_special='1' else + uc_scr_t3_l2(8 to 11); + + + + + + + + + + + + +uc_hooks_rc_rf0 <= '0' when uc_beg_rf0_v ='1' and perr_sm_running='0' else + iu_fu_rf0_instr(31); + + +--//################################################################################################# +--//## flatten out the output mux +--//################################################################################################# + +q1_p_ulp_th(0) <= q1_p_ulp_early_l2(0) and not uc_scr_t0_l2(0) ; +q1_p_ulp_th(1) <= q1_p_ulp_early_l2(1) and not uc_scr_t1_l2(0) ; +q1_p_ulp_th(2) <= q1_p_ulp_early_l2(2) and not uc_scr_t2_l2(0) ; +q1_p_ulp_th(3) <= q1_p_ulp_early_l2(3) and not uc_scr_t3_l2(0) ; + +iu_fu_rf0_ucfmul_b <= not iu_fu_rf0_ucfmul ; + + + +u_q1pm0: rf0_q1_p_ulp_mux0_b <= not( (thread_id_rf0(0) and q1_p_ulp_th(0)) or (thread_id_rf0(1) and q1_p_ulp_th(1)) ); +u_q1pm1: rf0_q1_p_ulp_mux1_b <= not( (thread_id_rf0(2) and q1_p_ulp_th(2)) or (thread_id_rf0(3) and q1_p_ulp_th(3)) ); + +u_q1pm: rf0_q1_p_ulp_mux <= not( rf0_q1_p_ulp_mux0_b and rf0_q1_p_ulp_mux1_b ) ; + +u_afm0: rf0_fra_fast_mux0_b(4) <= not( rf0_q1_p_ulp_mux and iu_fu_rf0_ucfmul ); +u_afm1: rf0_fra_fast_mux1_b(4) <= not( rf0_instr_fra(4) and iu_fu_rf0_ucfmul_b ); + +u_afm: rf0_fra_fast_mux(4) <= not( rf0_fra_fast_mux0_b(4) and rf0_fra_fast_mux1_b(4) ); + +u_afb: rf0_fra_fast_b(4) <= not( rf0_fra_fast_mux(4) ); +u_af: rf0_fra_fast(4) <= not( rf0_fra_fast_b(4) ); +u_afi: rf0_fra_fast_i_b(4) <= not rf0_fra_fast(4) ; +u_afii: rf0_fra_fast_ii(4) <= not rf0_fra_fast_i_b(4); + + + + f_dcd_rf0_fra(0) <= rf0_instr_fra(0) ; + f_dcd_rf0_fra(1) <= rf0_instr_fra(1) ; + f_dcd_rf0_fra(2) <= rf0_instr_fra(2) ; + f_dcd_rf0_fra(3) <= rf0_instr_fra(3) ; + f_dcd_rf0_fra(4) <= rf0_fra_fast_ii(4); + f_dcd_rf0_fra(5) <= rf0_instr_fra(5) ; + + + + + + + + + +--//################################################################################################### + +rf0_i(0 to 31) <= iu_fu_rf0_instr(0 to 31); + +fp_operation_rf0 <= rf0_i(0) and rf0_i(1) and rf0_i(2) and rf0_i(4) and rf0_i(5) ; + +rf0_f2_dvsq <= rf0_i(26) and not rf0_i(27) and rf0_i(29) and not rf0_i(30) ; +rf0_f2_dv <= rf0_i(26) and not rf0_i(27) and not rf0_i(28) and rf0_i(29) and not rf0_i(30) ; +rf0_f2_sq <= rf0_i(26) and not rf0_i(27) and rf0_i(28) and rf0_i(29) and not rf0_i(30) ; +rf0_f2_mul <= rf0_i(26) and not rf0_i(27) and not rf0_i(28) and not rf0_i(29) and rf0_i(30) ; + + +-- 3F = double 3B = single + +uc_div_beg_rf0 <= fp_operation_rf0 and rf0_f2_dv and iu_fu_rf0_instr_v ;-- 1 load to latch +uc_sqrt_beg_rf0 <= fp_operation_rf0 and rf0_f2_sq and iu_fu_rf0_instr_v ;-- 1 load to latch +uc_fdiv_beg_rf0 <= fp_operation_rf0 and rf0_i(3) and rf0_f2_dv ; +uc_fdivs_beg_rf0 <= fp_operation_rf0 and not rf0_i(3) and rf0_f2_dv ; +uc_fsqrt_beg_rf0 <= fp_operation_rf0 and rf0_i(3) and rf0_f2_sq ; +uc_fsqrts_beg_rf0 <= fp_operation_rf0 and not rf0_i(3) and rf0_f2_sq ; +uc_dvsq_beg_rf0 <= fp_operation_rf0 and rf0_f2_dvsq ;-- fdiv,fdivs,fsqrt,fsqrts +fmulx_uc_rf0 <= fp_operation_rf0 and rf0_f2_mul ;-- fmuls, fmul + + + +uc_beg_rf0 <= uc_dvsq_beg_rf0 ; +uc_beg_rf0_v <= uc_dvsq_beg_rf0 and iu_fu_rf0_instr_v ; +uc_end_rf0 <= fmulx_uc_rf0 ; +uc_end_rf0_v <= fmulx_uc_rf0 and iu_fu_rf0_instr_v ; +uc_end_rf0_vf <= fmulx_uc_rf0 and iu_fu_rf0_instr_v and not rf0_instr_flush ; + + +uc_op_rf0(0) <= uc_fdiv_beg_rf0 ; +uc_op_rf0(1) <= uc_fdivs_beg_rf0 ; +uc_op_rf0(2) <= uc_fsqrt_beg_rf0 ; +uc_op_rf0(3) <= uc_fsqrts_beg_rf0; + + +------------------------------------------------------------------------------------------------------------------------------------------- +-------------------------------------------------------------------- uc_scr --------------------------------------------------------------- +------------------------------------------------------------------------------------------------------------------------------------------- +-- collect sign, zero, & rc info for ucode divide algorithm + + uc_sign_zero_t0(0 to 11) <= uc_scr_t0_l2(0 to 1) & f_mad_ex6_uc_sign & f_mad_ex6_uc_zero & uc_scr_t0_l2(4 to 11) when uc_scr_sel_ex6 = "01" else -- save sign & zero + uc_scr_t0_l2(0 to 3) & f_mad_ex6_uc_sign & f_mad_ex6_uc_zero & uc_scr_t0_l2(6 to 11) when uc_scr_sel_ex6 = "10" else -- save sign & zero + uc_scr_t0_l2(0 to 5) & f_mad_ex6_uc_sign & "00000"; -- last uc before the mult by 1 + + uc_sign_zero_t1(0 to 11) <= uc_scr_t1_l2(0 to 1) & f_mad_ex6_uc_sign & f_mad_ex6_uc_zero & uc_scr_t1_l2(4 to 11) when uc_scr_sel_ex6 = "01" else -- save sign & zero + uc_scr_t1_l2(0 to 3) & f_mad_ex6_uc_sign & f_mad_ex6_uc_zero & uc_scr_t1_l2(6 to 11) when uc_scr_sel_ex6 = "10" else -- save sign & zero + uc_scr_t1_l2(0 to 5) & f_mad_ex6_uc_sign & "00000"; -- last uc before the mult by 1 + + uc_sign_zero_t2(0 to 11) <= uc_scr_t2_l2(0 to 1) & f_mad_ex6_uc_sign & f_mad_ex6_uc_zero & uc_scr_t2_l2(4 to 11) when uc_scr_sel_ex6 = "01" else -- save sign & zero + uc_scr_t2_l2(0 to 3) & f_mad_ex6_uc_sign & f_mad_ex6_uc_zero & uc_scr_t2_l2(6 to 11) when uc_scr_sel_ex6 = "10" else -- save sign & zero + uc_scr_t2_l2(0 to 5) & f_mad_ex6_uc_sign & "00000"; -- last uc before the mult by 1 + + uc_sign_zero_t3(0 to 11) <= uc_scr_t3_l2(0 to 1) & f_mad_ex6_uc_sign & f_mad_ex6_uc_zero & uc_scr_t3_l2(4 to 11) when uc_scr_sel_ex6 = "01" else -- save sign & zero + uc_scr_t3_l2(0 to 3) & f_mad_ex6_uc_sign & f_mad_ex6_uc_zero & uc_scr_t3_l2(6 to 11) when uc_scr_sel_ex6 = "10" else -- save sign & zero + uc_scr_t3_l2(0 to 5) & f_mad_ex6_uc_sign & "00000"; -- last uc before the mult by 1 + + + + uc_scr_t0_upd(0) <= uc_1st_instr_l2(0) = '1' and uc_scr_t0_l2(7) = '0' and uc_scr_thread_rf1 = "00" ;-- clear bits 0:6 and latch rc of original ppc fdiv(s) or fsqrt(s) rc + uc_scr_t1_upd(0) <= uc_1st_instr_l2(1) = '1' and uc_scr_t1_l2(7) = '0' and uc_scr_thread_rf1 = "01" ;-- clear bits 0:6 and latch rc of original ppc fdiv(s) or fsqrt(s) rc + uc_scr_t2_upd(0) <= uc_1st_instr_l2(2) = '1' and uc_scr_t2_l2(7) = '0' and uc_scr_thread_rf1 = "10" ;-- clear bits 0:6 and latch rc of original ppc fdiv(s) or fsqrt(s) rc + uc_scr_t3_upd(0) <= uc_1st_instr_l2(3) = '1' and uc_scr_t3_l2(7) = '0' and uc_scr_thread_rf1 = "11" ;-- clear bits 0:6 and latch rc of original ppc fdiv(s) or fsqrt(s) rc + + uc_scr_t0_upd(1) <= uc_end_ex6_l2 and uc_scr_thread_ex6 = "00" ; -- clear bits 0:7 end of ucode + uc_scr_t1_upd(1) <= uc_end_ex6_l2 and uc_scr_thread_ex6 = "01" ; -- clear bits 0:7 end of ucode + uc_scr_t2_upd(1) <= uc_end_ex6_l2 and uc_scr_thread_ex6 = "10" ; -- clear bits 0:7 end of ucode + uc_scr_t3_upd(1) <= uc_end_ex6_l2 and uc_scr_thread_ex6 = "11" ; -- clear bits 0:7 end of ucode + + uc_scr_t0_upd(2) <= ((not ucode_mode_rf0 and not uc_end_rf0) or uc_abort_rf0(0) ) and iu_fu_rf0_instr_v and thread_id_rf0(0) ; -- clear bits 0:7 ppc instr + uc_scr_t1_upd(2) <= ((not ucode_mode_rf0 and not uc_end_rf0) or uc_abort_rf0(1) ) and iu_fu_rf0_instr_v and thread_id_rf0(1) ; -- clear bits 0:7 ppc instr + uc_scr_t2_upd(2) <= ((not ucode_mode_rf0 and not uc_end_rf0) or uc_abort_rf0(2) ) and iu_fu_rf0_instr_v and thread_id_rf0(2) ; -- clear bits 0:7 ppc instr + uc_scr_t3_upd(2) <= ((not ucode_mode_rf0 and not uc_end_rf0) or uc_abort_rf0(3) ) and iu_fu_rf0_instr_v and thread_id_rf0(3) ; -- clear bits 0:7 ppc instr + + uc_scr_t0_upd(3) <= uc_scr_wr_ex3_l2 and uc_scr_sel_ex3 = "00" and uc_scr_t0_l2(7) = '1' and uc_scr_thread_ex3 = "00" ; -- check for ugly ops, save final sig + uc_scr_t1_upd(3) <= uc_scr_wr_ex3_l2 and uc_scr_sel_ex3 = "00" and uc_scr_t1_l2(7) = '1' and uc_scr_thread_ex3 = "01" ; -- check for ugly ops, save final sig + uc_scr_t2_upd(3) <= uc_scr_wr_ex3_l2 and uc_scr_sel_ex3 = "00" and uc_scr_t2_l2(7) = '1' and uc_scr_thread_ex3 = "10" ; -- check for ugly ops, save final sig + uc_scr_t3_upd(3) <= uc_scr_wr_ex3_l2 and uc_scr_sel_ex3 = "00" and uc_scr_t3_l2(7) = '1' and uc_scr_thread_ex3 = "11" ; -- check for ugly ops, save final sig + + uc_scr_t0_upd(4) <= uc_scr_wr_ex6 = '1' and uc_scr_t0_l2(0) = '0' and uc_scr_t0_l2(7) = '1' and uc_scr_thread_ex6 = "00" ;-- save sign & zero + uc_scr_t1_upd(4) <= uc_scr_wr_ex6 = '1' and uc_scr_t1_l2(0) = '0' and uc_scr_t1_l2(7) = '1' and uc_scr_thread_ex6 = "01" ;-- save sign & zero + uc_scr_t2_upd(4) <= uc_scr_wr_ex6 = '1' and uc_scr_t2_l2(0) = '0' and uc_scr_t2_l2(7) = '1' and uc_scr_thread_ex6 = "10" ;-- save sign & zero + uc_scr_t3_upd(4) <= uc_scr_wr_ex6 = '1' and uc_scr_t3_l2(0) = '0' and uc_scr_t3_l2(7) = '1' and uc_scr_thread_ex6 = "11" ;-- save sign & zero + + + uc_scr_t0_fbk_x <= not( uc_scr_t0_upd(0) or uc_scr_t0_upd(1) or uc_scr_t0_upd(3) or uc_scr_t0_upd(4) ); + uc_scr_t1_fbk_x <= not( uc_scr_t1_upd(0) or uc_scr_t1_upd(1) or uc_scr_t1_upd(3) or uc_scr_t1_upd(4) ); + uc_scr_t2_fbk_x <= not( uc_scr_t2_upd(0) or uc_scr_t2_upd(1) or uc_scr_t2_upd(3) or uc_scr_t2_upd(4) ); + uc_scr_t3_fbk_x <= not( uc_scr_t3_upd(0) or uc_scr_t3_upd(1) or uc_scr_t3_upd(3) or uc_scr_t3_upd(4) ); + + + uc_scr_t0_ld_x(0 to 11) <= not( uc_scr_t0_ld_x0_b(0 to 11) and uc_scr_t0_ld_x1_b(0 to 11) and uc_scr_t0_ld_x3_b(0 to 11) and uc_scr_t0_ld_x4_b(0 to 11) and uc_scr_t0_ld_xf_b(0 to 11) ); + uc_scr_t1_ld_x(0 to 11) <= not( uc_scr_t1_ld_x0_b(0 to 11) and uc_scr_t1_ld_x1_b(0 to 11) and uc_scr_t1_ld_x3_b(0 to 11) and uc_scr_t1_ld_x4_b(0 to 11) and uc_scr_t1_ld_xf_b(0 to 11) ); + uc_scr_t2_ld_x(0 to 11) <= not( uc_scr_t2_ld_x0_b(0 to 11) and uc_scr_t2_ld_x1_b(0 to 11) and uc_scr_t2_ld_x3_b(0 to 11) and uc_scr_t2_ld_x4_b(0 to 11) and uc_scr_t2_ld_xf_b(0 to 11) ); + uc_scr_t3_ld_x(0 to 11) <= not( uc_scr_t3_ld_x0_b(0 to 11) and uc_scr_t3_ld_x1_b(0 to 11) and uc_scr_t3_ld_x3_b(0 to 11) and uc_scr_t3_ld_x4_b(0 to 11) and uc_scr_t3_ld_xf_b(0 to 11) ); + + + uc_scr_t0_ld_x0_b(0 to 11) <= not("00000001" & uc_scr_t0_l2(8 to 11) and (0 to 11 => uc_scr_t0_upd(0))) ; + uc_scr_t1_ld_x0_b(0 to 11) <= not("00000001" & uc_scr_t1_l2(8 to 11) and (0 to 11 => uc_scr_t1_upd(0))) ; + uc_scr_t2_ld_x0_b(0 to 11) <= not("00000001" & uc_scr_t2_l2(8 to 11) and (0 to 11 => uc_scr_t2_upd(0))) ; + uc_scr_t3_ld_x0_b(0 to 11) <= not("00000001" & uc_scr_t3_l2(8 to 11) and (0 to 11 => uc_scr_t3_upd(0))) ; + + uc_scr_t0_ld_x1_b(0 to 11) <= not("000000000000" and (0 to 11 => uc_scr_t0_upd(1))) ; + uc_scr_t1_ld_x1_b(0 to 11) <= not("000000000000" and (0 to 11 => uc_scr_t1_upd(1))) ; + uc_scr_t2_ld_x1_b(0 to 11) <= not("000000000000" and (0 to 11 => uc_scr_t2_upd(1))) ; + uc_scr_t3_ld_x1_b(0 to 11) <= not("000000000000" and (0 to 11 => uc_scr_t3_upd(1))) ; + + uc_scr_t0_ld_x2_b(0 to 11) <= not("00000000" & uc_op_rf0(0 to 3) and (0 to 11 => uc_scr_t0_upd(2))) ; + uc_scr_t1_ld_x2_b(0 to 11) <= not("00000000" & uc_op_rf0(0 to 3) and (0 to 11 => uc_scr_t1_upd(2))) ; + uc_scr_t2_ld_x2_b(0 to 11) <= not("00000000" & uc_op_rf0(0 to 3) and (0 to 11 => uc_scr_t2_upd(2))) ; + uc_scr_t3_ld_x2_b(0 to 11) <= not("00000000" & uc_op_rf0(0 to 3) and (0 to 11 => uc_scr_t3_upd(2))) ; + + uc_scr_t0_ld_x3_b(0 to 11) <= not(uc_special_cases_ex3(0 to 7) & uc_special_cases_t0_ex3(8 to 11) and (0 to 11 => uc_scr_t0_upd(3))) ; + uc_scr_t1_ld_x3_b(0 to 11) <= not(uc_special_cases_ex3(0 to 7) & uc_special_cases_t1_ex3(8 to 11) and (0 to 11 => uc_scr_t1_upd(3))) ; + uc_scr_t2_ld_x3_b(0 to 11) <= not(uc_special_cases_ex3(0 to 7) & uc_special_cases_t2_ex3(8 to 11) and (0 to 11 => uc_scr_t2_upd(3))) ; + uc_scr_t3_ld_x3_b(0 to 11) <= not(uc_special_cases_ex3(0 to 7) & uc_special_cases_t3_ex3(8 to 11) and (0 to 11 => uc_scr_t3_upd(3))) ; + + uc_scr_t0_ld_x4_b(0 to 11) <= not(uc_sign_zero_t0(0 to 11) and (0 to 11 => uc_scr_t0_upd(4))) ; + uc_scr_t1_ld_x4_b(0 to 11) <= not(uc_sign_zero_t1(0 to 11) and (0 to 11 => uc_scr_t1_upd(4))) ; + uc_scr_t2_ld_x4_b(0 to 11) <= not(uc_sign_zero_t2(0 to 11) and (0 to 11 => uc_scr_t2_upd(4))) ; + uc_scr_t3_ld_x4_b(0 to 11) <= not(uc_sign_zero_t3(0 to 11) and (0 to 11 => uc_scr_t3_upd(4))) ; + + uc_scr_t0_ld_xf_b(0 to 11) <= not(uc_scr_t0_l2(0 to 11) and (0 to 11 => uc_scr_t0_fbk_x )) ; + uc_scr_t1_ld_xf_b(0 to 11) <= not(uc_scr_t1_l2(0 to 11) and (0 to 11 => uc_scr_t1_fbk_x )) ; + uc_scr_t2_ld_xf_b(0 to 11) <= not(uc_scr_t2_l2(0 to 11) and (0 to 11 => uc_scr_t2_fbk_x )) ; + uc_scr_t3_ld_xf_b(0 to 11) <= not(uc_scr_t3_l2(0 to 11) and (0 to 11 => uc_scr_t3_fbk_x )) ; + + uc_scr_t0_oth_b(0 to 11) <= not( (0 to 11 => not uc_scr_t0_upd(2) ) and uc_scr_t0_ld_x(0 to 11) ); + uc_scr_t1_oth_b(0 to 11) <= not( (0 to 11 => not uc_scr_t1_upd(2) ) and uc_scr_t1_ld_x(0 to 11) ); + uc_scr_t2_oth_b(0 to 11) <= not( (0 to 11 => not uc_scr_t2_upd(2) ) and uc_scr_t2_ld_x(0 to 11) ); + uc_scr_t3_oth_b(0 to 11) <= not( (0 to 11 => not uc_scr_t3_upd(2) ) and uc_scr_t3_ld_x(0 to 11) ); + + uc_scr_t0_ld(0 to 11) <= not( uc_scr_t0_ld_x2_b(0 to 11) and uc_scr_t0_oth_b(0 to 11) ); + uc_scr_t1_ld(0 to 11) <= not( uc_scr_t1_ld_x2_b(0 to 11) and uc_scr_t1_oth_b(0 to 11) ); + uc_scr_t2_ld(0 to 11) <= not( uc_scr_t2_ld_x2_b(0 to 11) and uc_scr_t2_oth_b(0 to 11) ); + uc_scr_t3_ld(0 to 11) <= not( uc_scr_t3_ld_x2_b(0 to 11) and uc_scr_t3_oth_b(0 to 11) ); + + + + +-- uc scr thread 0,1,2,3 ---------------------------------------------------------------- +-- bit 0 = 0 indicates regular case +-- bit 1 final sign +-- bit 2 q1r_sign +-- bit 3 q1r_zero +-- bit 4 q1ulpr_sign +-- bit 5 q1ulpr_zero +-- bit 6 q1hulpr_sign +-- bit 7 divide or square root in progress +-- bit 8 fdiv +-- bit 9 fdivs +-- bit 10 fsqrt +-- bit 11 fsqrts +-- bit 0 = 1 indicates special case +-- bit 1 final sign (not used) +-- bit 2 NaN +-- bit 3 ZX +-- bit 4 VXIDI +-- bit 5 VXZDZ +-- bit 6 +-- bit 7 divide or square root in progress +-- bit 8 fdiv +-- bit 9 fdivs +-- bit 10 fsqrt +-- bit 11 fsqrts + + uc_scr_t0_is2: tri_rlmreg_p generic map (init => 0, expand_type => expand_type, width => 12) port map ( + nclk => nclk, act => msr_fp_act, + vd => vdd, gd => gnd, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + thold_b => thold_0_b, sg => sg_0, + scin => uc_scr_t0_scin, + scout => uc_scr_t0_scout, + din(0 to 11) => uc_scr_t0_ld, + dout(0 to 11) => uc_scr_t0_l2 ); + + uc_scr_t1_is2: tri_rlmreg_p generic map (init => 0, expand_type => expand_type, width => 12) port map ( + nclk => nclk, act => msr_fp_act, + vd => vdd, gd => gnd, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + thold_b => thold_0_b, sg => sg_0, + scin => uc_scr_t1_scin, + scout => uc_scr_t1_scout, + din(0 to 11) => uc_scr_t1_ld, + dout(0 to 11) => uc_scr_t1_l2 ); + + uc_scr_t2_is2: tri_rlmreg_p generic map (init => 0, expand_type => expand_type, width => 12) port map ( + nclk => nclk, act => msr_fp_act, + vd => vdd, gd => gnd, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + thold_b => thold_0_b, sg => sg_0, + scin => uc_scr_t2_scin, + scout => uc_scr_t2_scout, + din(0 to 11) => uc_scr_t2_ld, + dout(0 to 11) => uc_scr_t2_l2 ); + + uc_scr_t3_is2: tri_rlmreg_p generic map (init => 0, expand_type => expand_type, width => 12) port map ( + nclk => nclk, act => msr_fp_act, + vd => vdd, gd => gnd, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + thold_b => thold_0_b, sg => sg_0, + scin => uc_scr_t3_scin, + scout => uc_scr_t3_scout, + din(0 to 11) => uc_scr_t3_ld, + dout(0 to 11) => uc_scr_t3_l2 ); + + + +q1r_sign_rf0 <= (uc_scr_t0_l2(2) and thread_id_rf0(0)) or + (uc_scr_t1_l2(2) and thread_id_rf0(1)) or + (uc_scr_t2_l2(2) and thread_id_rf0(2)) or + (uc_scr_t3_l2(2) and thread_id_rf0(3)); + +q1r_zero_rf0 <= (uc_scr_t0_l2(3) and thread_id_rf0(0)) or + (uc_scr_t1_l2(3) and thread_id_rf0(1)) or + (uc_scr_t2_l2(3) and thread_id_rf0(2)) or + (uc_scr_t3_l2(3) and thread_id_rf0(3)); + + +q1ulpr_zero_rf0 <= (uc_scr_t0_l2(5) and thread_id_rf0(0)) or + (uc_scr_t1_l2(5) and thread_id_rf0(1)) or + (uc_scr_t2_l2(5) and thread_id_rf0(2)) or + (uc_scr_t3_l2(5) and thread_id_rf0(3)); + +ex4_uc_special <= ((uc_scr_t0_l2(0) and uc_scr_thread_ex4 = "00") or + (uc_scr_t1_l2(0) and uc_scr_thread_ex4 = "01") or + (uc_scr_t2_l2(0) and uc_scr_thread_ex4 = "10") or + (uc_scr_t3_l2(0) and uc_scr_thread_ex4 = "11") ) and not uc_end_ex4_l2 and not uc_beg_ex4 and not perr_sm_running ; + + +special_rf1 <= (uc_scr_t0_l2(0) and uc_scr_thread_rf1 = "00") or + (uc_scr_t1_l2(0) and uc_scr_thread_rf1 = "01") or + (uc_scr_t2_l2(0) and uc_scr_thread_rf1 = "10") or + (uc_scr_t3_l2(0) and uc_scr_thread_rf1 = "11"); + +f_dcd_ex2_uc_vxsnan <= ((uc_scr_t0_l2(0) and uc_scr_t0_l2(2) and uc_scr_thread_ex2 = "00") or + (uc_scr_t1_l2(0) and uc_scr_t1_l2(2) and uc_scr_thread_ex2 = "01") or + (uc_scr_t2_l2(0) and uc_scr_t2_l2(2) and uc_scr_thread_ex2 = "10") or + (uc_scr_t3_l2(0) and uc_scr_t3_l2(2) and uc_scr_thread_ex2 = "11")) and not perr_sm_running ; + + +f_dcd_ex2_uc_zx <= ((uc_scr_t0_l2(0) and uc_scr_t0_l2(3) and uc_scr_thread_ex2 = "00") or + (uc_scr_t1_l2(0) and uc_scr_t1_l2(3) and uc_scr_thread_ex2 = "01") or + (uc_scr_t2_l2(0) and uc_scr_t2_l2(3) and uc_scr_thread_ex2 = "10") or + (uc_scr_t3_l2(0) and uc_scr_t3_l2(3) and uc_scr_thread_ex2 = "11")) and not perr_sm_running ; + + +f_dcd_ex2_uc_vxidi <= ((uc_scr_t0_l2(0) and uc_scr_t0_l2(4) and uc_scr_thread_ex2 = "00") or + (uc_scr_t1_l2(0) and uc_scr_t1_l2(4) and uc_scr_thread_ex2 = "01") or + (uc_scr_t2_l2(0) and uc_scr_t2_l2(4) and uc_scr_thread_ex2 = "10") or + (uc_scr_t3_l2(0) and uc_scr_t3_l2(4) and uc_scr_thread_ex2 = "11")) and not perr_sm_running ; + + +f_dcd_ex2_uc_vxzdz <= ((uc_scr_t0_l2(0) and uc_scr_t0_l2(5) and uc_scr_thread_ex2 = "00") or + (uc_scr_t1_l2(0) and uc_scr_t1_l2(5) and uc_scr_thread_ex2 = "01") or + (uc_scr_t2_l2(0) and uc_scr_t2_l2(5) and uc_scr_thread_ex2 = "10") or + (uc_scr_t3_l2(0) and uc_scr_t3_l2(5) and uc_scr_thread_ex2 = "11")) and not perr_sm_running ; + + +f_dcd_ex2_uc_vxsqrt <= ((uc_scr_t0_l2(0) and uc_scr_t0_l2(6) and uc_scr_thread_ex2 = "00") or + (uc_scr_t1_l2(0) and uc_scr_t1_l2(6) and uc_scr_thread_ex2 = "01") or + (uc_scr_t2_l2(0) and uc_scr_t2_l2(6) and uc_scr_thread_ex2 = "10") or + (uc_scr_t3_l2(0) and uc_scr_t3_l2(6) and uc_scr_thread_ex2 = "11")) and not perr_sm_running ; + + +uc_scr_thread_rf0(0) <= thread_id_rf0(2) or thread_id_rf0(3); +uc_scr_thread_rf0(1) <= thread_id_rf0(1) or thread_id_rf0(3); + +uc_fc_pos_rf0 <= uc_fc_pos or uc_end_rf0_v; + + + pipe_rf1: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 22) + port map ( + nclk => nclk, act => tiup, + vd => vdd, gd => gnd, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + thold_b => thold_0_b, sg => sg_0, + scin => pipe_rf1_scin, + scout => pipe_rf1_scout, + --------------------------------------------- + din(00) => uc_div_beg_rf0, + din(01) => uc_sqrt_beg_rf0, + din(02) => uc_mid_rf0, -- 13 bit expt. overflow/underflow disable. do not set fpscr. + din(03) => uc_end_rf0_vf, -- 13 bit expt. overflow/underflow disable. do not set fpscr. + din(04) => '0', + din(05) => uc_fa_pos, + din(06) => uc_fc_pos_rf0, + din(07) => uc_fb_pos, + din(08) => uc_fc_hulp, + din(09) => uc_fc_0_5, + din(10) => uc_fc_1_0, + din(11) => uc_fc_1_minus, + din(12) => uc_fb_1_0, + din(13) => uc_fb_0_75, + din(14) => uc_fb_0_5, + din(15) => uc_fa_dis_par_rf0, + din(16) => uc_fb_dis_par_rf0, + din(17) => uc_fc_dis_par_rf0, + din(18) => uc_op_rnd_v, + din(19 to 20) => uc_op_rnd(0 to 1), + din(21) => iu_fu_rf0_ucfmul, + --------------------------------------------- + dout(00) => uc_div_beg_rf1, + dout(01) => uc_sqrt_beg_rf1, + dout(02) => uc_mid_rf1, + dout(03) => uc_end_rf1_l2, + dout(04) => spare, + dout(05) => uc_fa_pos_rf1, + dout(06) => uc_fc_pos_rf1, + dout(07) => uc_fb_pos_rf1, + dout(08) => uc_fc_hulp_rf1, + dout(09) => uc_fc_0_5_rf1, + dout(10) => uc_fc_1_0_rf1, + dout(11) => uc_fc_1_minus_rf1, + dout(12) => uc_fb_1_0_rf1, + dout(13) => uc_fb_0_75_rf1, + dout(14) => uc_fb_0_5_rf1, + dout(15) => uc_fa_dis_par_rf1, + dout(16) => uc_fb_dis_par_rf1, + dout(17) => uc_fc_dis_par_rf1, + dout(18) => uc_op_rnd_v_rf1_l2, + dout(19 to 20) => uc_op_rnd_rf1_l2(0 to 1), + dout(21) => rf1_ucfmul + --------------------------------------------- + ); + + +rf0_instr_flush <= ((thread_id_rf0(0) and xu_rf0_flush(0)) or + (thread_id_rf0(1) and xu_rf0_flush(1)) or + (thread_id_rf0(2) and xu_rf0_flush(2)) or + (thread_id_rf0(3) and xu_rf0_flush(3)) ); + +uc_scr_wr_rf0 <= (uc_scr_wr or uc_beg_rf0) and iu_fu_rf0_instr_v and not rf0_instr_flush; + +-- uc_scr write pipe ----------------------------- + uc_scr_wr_pipe_rf1: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 8) + port map ( + nclk => nclk, act => msr_fp_act, + vd => vdd, gd => gnd, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + thold_b => thold_0_b, sg => sg_0, + scin => uc_scr_wr_pipe_rf1_scin, + scout => uc_scr_wr_pipe_rf1_scout, + --------------------------------------------- + din(0) => uc_scr_wr_rf0, + din(1 to 2) => uc_scr_sel(0 to 1), + din(3 to 4) => uc_scr_thread_rf0(0 to 1), + din(5) => uc_gs_v_rf0, + din(6) => uc_inc_lsb, + din(7) => uc_beg_rf0_v, + --------------------------------------------- + dout(0) => uc_scr_wr_rf1_l2, + dout(1 to 2) => uc_scr_sel_rf1(0 to 1), + dout(3 to 4) => uc_scr_thread_rf1(0 to 1), + dout(5) => uc_gs_v_rf1, + dout(6) => uc_inc_lsb_rf1, + dout(7) => uc_beg_rf1 + --------------------------------------------- + ); + +rf1_instr_flush <= ((uc_scr_thread_rf1(0 to 1) = "00" and xu_rf1_flush(0)) or + (uc_scr_thread_rf1(0 to 1) = "01" and xu_rf1_flush(1)) or + (uc_scr_thread_rf1(0 to 1) = "10" and xu_rf1_flush(2)) or + (uc_scr_thread_rf1(0 to 1) = "11" and xu_rf1_flush(3)) ); + +uc_scr_wr_rf1 <= uc_scr_wr_rf1_l2 and not rf1_instr_flush; + +uc_end_rf1_v <= uc_end_rf1_l2 and not rf1_instr_flush; +uc_end_rf1 <= uc_end_rf1_l2; + + uc_scr_wr_pipe_ex1: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 9) + port map ( + nclk => nclk, act => msr_fp_act, + vd => vdd, gd => gnd, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + thold_b => thold_0_b, sg => sg_0, + scin => uc_scr_wr_pipe_ex1_scin, + scout => uc_scr_wr_pipe_ex1_scout, + --------------------------------------------- + din(0) => uc_scr_wr_rf1, + din(1 to 2) => uc_scr_sel_rf1(0 to 1), + din(3 to 4) => uc_scr_thread_rf1(0 to 1), + din(5) => uc_gs_v_rf1, + din(6) => uc_inc_lsb_rf1, + din(7) => uc_end_rf1_v, + din(8) => uc_beg_rf1, + --------------------------------------------- + dout(0) => uc_scr_wr_ex1_l2, + dout(1 to 2) => uc_scr_sel_ex1(0 to 1), + dout(3 to 4) => uc_scr_thread_ex1(0 to 1), + dout(5) => uc_gs_v_ex1, + dout(6) => uc_inc_lsb_ex1, + dout(7) => uc_end_ex1_l2, + dout(8) => uc_beg_ex1 + --------------------------------------------- + ); + +ex1_instr_flush <= ((uc_scr_thread_ex1(0 to 1) = "00" and xu_ex1_flush(0)) or + (uc_scr_thread_ex1(0 to 1) = "01" and xu_ex1_flush(1)) or + (uc_scr_thread_ex1(0 to 1) = "10" and xu_ex1_flush(2)) or + (uc_scr_thread_ex1(0 to 1) = "11" and xu_ex1_flush(3)) ); + +uc_scr_wr_ex1 <= uc_scr_wr_ex1_l2 and not ex1_instr_flush; + +uc_end_ex1 <= uc_end_ex1_l2 and not ex1_instr_flush; + +-- uc_scr write pipe ----------------------------- + uc_scr_wr_pipe_ex2: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 9) + port map ( + nclk => nclk, act => msr_fp_act, + vd => vdd, gd => gnd, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + thold_b => thold_0_b, sg => sg_0, + scin => uc_scr_wr_pipe_ex2_scin, + scout => uc_scr_wr_pipe_ex2_scout, + --------------------------------------------- + din(0) => uc_scr_wr_ex1, + din(1 to 2) => uc_scr_sel_ex1(0 to 1), + din(3 to 4) => uc_scr_thread_ex1(0 to 1), + din(5) => uc_gs_v_ex1, + din(6) => uc_inc_lsb_ex1, + din(7) => uc_end_ex1, + din(8) => uc_beg_ex1, + --------------------------------------------- + dout(0) => uc_scr_wr_ex2_l2, + dout(1 to 2) => uc_scr_sel_ex2(0 to 1), + dout(3 to 4) => uc_scr_thread_ex2(0 to 1), + dout(5) => uc_gs_v_ex2, + dout(6) => uc_inc_lsb_ex2, + dout(7) => uc_end_ex2_l2, + dout(8) => uc_beg_ex2 + --------------------------------------------- + ); + +ex2_instr_flush <= ((uc_scr_thread_ex2(0 to 1) = "00" and xu_ex2_flush(0)) or + (uc_scr_thread_ex2(0 to 1) = "01" and xu_ex2_flush(1)) or + (uc_scr_thread_ex2(0 to 1) = "10" and xu_ex2_flush(2)) or + (uc_scr_thread_ex2(0 to 1) = "11" and xu_ex2_flush(3)) ); + +uc_scr_wr_ex2 <= uc_scr_wr_ex2_l2 and not ex2_instr_flush; + +uc_end_ex2 <= uc_end_ex2_l2 and not ex2_instr_flush; + +-- uc_scr write pipe ----------------------------- + uc_scr_wr_pipe_ex3: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 7) + port map ( + nclk => nclk, act => msr_fp_act, + vd => vdd, gd => gnd, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + thold_b => thold_0_b, sg => sg_0, + scin => uc_scr_wr_pipe_ex3_scin, + scout => uc_scr_wr_pipe_ex3_scout, + --------------------------------------------- + din(0) => uc_scr_wr_ex2, + din(1 to 2) => uc_scr_sel_ex2(0 to 1), + din(3 to 4) => uc_scr_thread_ex2(0 to 1), + din(5) => uc_end_ex2, + din(6) => uc_beg_ex2, + --------------------------------------------- + dout(0) => uc_scr_wr_ex3_l2, + dout(1 to 2) => uc_scr_sel_ex3(0 to 1), + dout(3 to 4) => uc_scr_thread_ex3(0 to 1), + dout(5) => uc_end_ex3_l2, + dout(6) => uc_beg_ex3 + --------------------------------------------- + ); + + +ex3_instr_flush_th(0) <= uc_scr_thread_ex3(0 to 1) = "00" and xu_ex3_flush(0) ; +ex3_instr_flush_th(1) <= uc_scr_thread_ex3(0 to 1) = "01" and xu_ex3_flush(1) ; +ex3_instr_flush_th(2) <= uc_scr_thread_ex3(0 to 1) = "10" and xu_ex3_flush(2) ; +ex3_instr_flush_th(3) <= uc_scr_thread_ex3(0 to 1) = "11" and xu_ex3_flush(3) ; + +ex3_instr_flush <= ex3_instr_flush_th(0) or + ex3_instr_flush_th(1) or + ex3_instr_flush_th(2) or + ex3_instr_flush_th(3) ; + +uc_scr_wr_ex3 <= uc_scr_wr_ex3_l2 and not ex3_instr_flush ; + +uc_end_ex3 <= uc_end_ex3_l2 and not ex3_instr_flush; + +uc_scr_wr_ex4_ld <= uc_scr_wr_ex3 and (uc_scr_sel_ex3(0) or uc_scr_sel_ex3(1)); -- uc_scr_sel_ex2=00 only writes in ex3 + +-- uc_scr write pipe ----------------------------- + uc_scr_wr_pipe_ex4: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 7) + port map ( + nclk => nclk, act => msr_fp_act, + vd => vdd, gd => gnd, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + thold_b => thold_0_b, sg => sg_0, + scin => uc_scr_wr_pipe_ex4_scin, + scout => uc_scr_wr_pipe_ex4_scout, + --------------------------------------------- + din(0) => uc_scr_wr_ex4_ld, + din(1 to 2) => uc_scr_sel_ex3(0 to 1), + din(3 to 4) => uc_scr_thread_ex3(0 to 1), + din(5) => uc_end_ex3, + din(6) => uc_beg_ex3, + --------------------------------------------- + dout(0) => uc_scr_wr_ex4_l2, + dout(1 to 2) => uc_scr_sel_ex4(0 to 1), + dout(3 to 4) => uc_scr_thread_ex4(0 to 1), + dout(5) => uc_end_ex4_l2, + dout(6) => uc_beg_ex4 + --------------------------------------------- + ); + +ex4_instr_flush <= ((uc_scr_thread_ex4(0 to 1) = "00" and xu_ex4_flush(0)) or + (uc_scr_thread_ex4(0 to 1) = "01" and xu_ex4_flush(1)) or + (uc_scr_thread_ex4(0 to 1) = "10" and xu_ex4_flush(2)) or + (uc_scr_thread_ex4(0 to 1) = "11" and xu_ex4_flush(3)) ); + +uc_scr_wr_ex4 <= uc_scr_wr_ex4_l2 and not ex4_instr_flush; + +uc_end_ex4 <= uc_end_ex4_l2 and not ex4_instr_flush; + +-- uc_scr write pipe ----------------------------- + uc_scr_wr_pipe_ex5: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 6) + port map ( + nclk => nclk, act => msr_fp_act, + vd => vdd, gd => gnd, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + thold_b => thold_0_b, sg => sg_0, + scin => uc_scr_wr_pipe_ex5_scin, + scout => uc_scr_wr_pipe_ex5_scout, + --------------------------------------------- + din(0) => uc_scr_wr_ex4, + din(1 to 2) => uc_scr_sel_ex4(0 to 1), + din(3 to 4) => uc_scr_thread_ex4(0 to 1), + din(5) => uc_end_ex4, + --------------------------------------------- + dout(0) => uc_scr_wr_ex5_l2, + dout(1 to 2) => uc_scr_sel_ex5(0 to 1), + dout(3 to 4) => uc_scr_thread_ex5(0 to 1), + dout(5) => uc_end_ex5_l2 + --------------------------------------------- + ); + +ex5_instr_flush <= ((uc_scr_thread_ex5(0 to 1) = "00" and xu_ex5_flush(0)) or + (uc_scr_thread_ex5(0 to 1) = "01" and xu_ex5_flush(1)) or + (uc_scr_thread_ex5(0 to 1) = "10" and xu_ex5_flush(2)) or + (uc_scr_thread_ex5(0 to 1) = "11" and xu_ex5_flush(3)) ); + +uc_scr_wr_ex5 <= uc_scr_wr_ex5_l2 and not ex5_instr_flush; + +uc_end_ex5 <= uc_end_ex5_l2 and not ex5_instr_flush; + +-- uc_scr write pipe ----------------------------- + uc_scr_wr_pipe_ex6: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 6) + port map ( + nclk => nclk, act => msr_fp_act, + vd => vdd, gd => gnd, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + thold_b => thold_0_b, sg => sg_0, + scin => uc_scr_wr_pipe_ex6_scin, + scout => uc_scr_wr_pipe_ex6_scout, + --------------------------------------------- + din(0) => uc_scr_wr_ex5, + din(1 to 2) => uc_scr_sel_ex5(0 to 1), + din(3 to 4) => uc_scr_thread_ex5(0 to 1), + din(5) => uc_end_ex5, + --------------------------------------------- + dout(0) => uc_scr_wr_ex6, + dout(1 to 2) => uc_scr_sel_ex6(0 to 1), + dout(3 to 4) => uc_scr_thread_ex6(0 to 1), + dout(5) => uc_end_ex6_l2 + --------------------------------------------- + ); + + + +q1_p_ulp_early_ld(0) <= (not uc_scr_t0_l2(3) and not uc_scr_t0_l2(4)) or uc_scr_t0_l2(5); + +q1_p_ulp_early_ld(1) <= (not uc_scr_t1_l2(3) and not uc_scr_t1_l2(4)) or uc_scr_t1_l2(5); + +q1_p_ulp_early_ld(2) <= (not uc_scr_t2_l2(3) and not uc_scr_t2_l2(4)) or uc_scr_t2_l2(5); + +q1_p_ulp_early_ld(3) <= (not uc_scr_t3_l2(3) and not uc_scr_t3_l2(4)) or uc_scr_t3_l2(5); + + + q1_p_ulp_early: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 4) + port map ( + nclk => nclk, act => msr_fp_act, + vd => vdd, gd => gnd, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + thold_b => thold_0_b, sg => sg_0, + scin => q1_p_ulp_early_scin, + scout => q1_p_ulp_early_scout, + --------------------------------------------- + din(0 to 3) => q1_p_ulp_early_ld(0 to 3), + + --------------------------------------------- + dout(0 to 3) => q1_p_ulp_early_l2(0 to 3) + + --------------------------------------------- + ); + + + + + + + + + +-- q1_p_ulp_rf0 selects s3 instead of s1 +-- q1_m_ulp_rf0 changes multiply by 3ff000... to 3fefffff... + + +--@@ ESPRESSO ABLE START @@ +-- .i 4-- .o 3 +-- .ilb q1r_zero_rf0 q1ulpr_zero_rf0 q1r_sign_rf0 q1ulpr_sign_rf0 +-- .ob q1_p_ulp_rf0 q1_rf0 q1_m_ulp_rf0 +-- .type fr +-- # +-- ################################################################################################################### +-- # +-- # q1r_zero_rf0 q1r_sign_rf0 q1_p_ulp_rf0 +-- # | q1ulpr_zero_rf0 | q1ulpr_sign_rf0 | q1_rf0 +-- # | | | | | | q1_m_ulp_rf0 +-- # | | | | | | | +-- ################################################################################################################### +-- +-- 0 1 - - 1 0 0 +-- 1 0 - - 0 1 0 +-- 0 0 0 0 1 0 0 +-- 0 0 0 1 0 1 0 +-- 0 0 1 1 0 0 1 +-- ################################################################################################################### +-- .e +--@@ ESPRESSO ABLE END @@ + +--@@ ESPRESSO OGIC START @@ +-- logic generated on: Fri Jul 13 08:08:16 2007 + + +q1_m_ulp_rf0 <= (not q1r_zero_rf0 and not q1ulpr_zero_rf0 and q1r_sign_rf0); + + +--@@ ESPRESSO OGIC END @@ + + +uc_fc_1_minus <= q1_m_ulp_rf0 and uc_normal_end_rf0 ; -- 1 - 1/2 ulp (3FEFFF...) +uc_fc_1_0 <= not q1_m_ulp_rf0 and uc_end_rf0_v ; -- 1.0 (3FF000...) + + + + + f_dcd_rf1_div_beg <= uc_div_beg_rf1 and not perr_sm_running ; + f_dcd_rf1_sqrt_beg <= uc_sqrt_beg_rf1 and not perr_sm_running ; + f_dcd_rf1_uc_mid <= uc_mid_rf1 and not rf1_ucfmul and not perr_sm_running ; + f_dcd_rf1_uc_end <= uc_end_rf1 and not perr_sm_running ; + f_dcd_rf1_uc_special <= special_rf1 and not perr_sm_running ; + f_dcd_rf1_uc_fa_pos <= uc_fa_pos_rf1 and not perr_sm_running ; + f_dcd_rf1_uc_fc_pos <= uc_fc_pos_rf1 and not perr_sm_running ; + f_dcd_rf1_uc_fb_pos <= uc_fb_pos_rf1 and not perr_sm_running ; + f_dcd_rf1_uc_fc_hulp <= uc_fc_hulp_rf1 and not perr_sm_running ; + f_dcd_rf1_uc_fc_0_5 <= uc_fc_0_5_rf1 and not perr_sm_running ; + f_dcd_rf1_uc_fc_1_0 <= uc_fc_1_0_rf1 and not perr_sm_running ; + f_dcd_rf1_uc_fc_1_minus <= uc_fc_1_minus_rf1 and not perr_sm_running ; + f_dcd_rf1_uc_fb_1_0 <= uc_fb_1_0_rf1 and not perr_sm_running ; + f_dcd_rf1_uc_fb_0_75 <= uc_fb_0_75_rf1 and not perr_sm_running ; + f_dcd_rf1_uc_fb_0_5 <= uc_fb_0_5_rf1 and not perr_sm_running ; + + f_dcd_rf1_uc_fa_dis_par <= uc_fa_dis_par_rf1 and not perr_sm_running ; + f_dcd_rf1_uc_fb_dis_par <= uc_fb_dis_par_rf1 and not perr_sm_running ; + f_dcd_rf1_uc_fc_dis_par <= uc_fc_dis_par_rf1 and not perr_sm_running ; + + uc_op_rnd_v_rf1 <= uc_op_rnd_v_rf1_l2 and not perr_sm_running ; + uc_op_rnd_rf1 <= uc_op_rnd_rf1_l2 ; + + + + + f_dcd_rf1_uc_ft_pos <= + not res_sign_rf1 and not perr_sm_running when uc_end_rf1='1' and special_rf1='0' else + '0'; + + f_dcd_rf1_uc_ft_neg <= + res_sign_rf1 and not perr_sm_running when uc_end_rf1='1' and special_rf1='0' else + '0'; + + + +res_sign_rf1 <= (uc_scr_t0_l2(1) and uc_scr_thread_rf1 = "00") or + (uc_scr_t1_l2(1) and uc_scr_thread_rf1 = "01") or + (uc_scr_t2_l2(1) and uc_scr_thread_rf1 = "10") or + (uc_scr_t3_l2(1) and uc_scr_thread_rf1 = "11"); + + + +q1r_sign_ex2 <= (uc_scr_t0_l2(2) and uc_scr_thread_ex2 = "00") or + (uc_scr_t1_l2(2) and uc_scr_thread_ex2 = "01") or + (uc_scr_t2_l2(2) and uc_scr_thread_ex2 = "10") or + (uc_scr_t3_l2(2) and uc_scr_thread_ex2 = "11"); + +q1r_zero_ex2 <= (uc_scr_t0_l2(3) and uc_scr_thread_ex2 = "00") or + (uc_scr_t1_l2(3) and uc_scr_thread_ex2 = "01") or + (uc_scr_t2_l2(3) and uc_scr_thread_ex2 = "10") or + (uc_scr_t3_l2(3) and uc_scr_thread_ex2 = "11"); + +q1ulpr_sign_ex2 <= (uc_scr_t0_l2(4) and uc_scr_thread_ex2 = "00") or + (uc_scr_t1_l2(4) and uc_scr_thread_ex2 = "01") or + (uc_scr_t2_l2(4) and uc_scr_thread_ex2 = "10") or + (uc_scr_t3_l2(4) and uc_scr_thread_ex2 = "11"); + +q1ulpr_zero_ex2 <= (uc_scr_t0_l2(5) and uc_scr_thread_ex2 = "00") or + (uc_scr_t1_l2(5) and uc_scr_thread_ex2 = "01") or + (uc_scr_t2_l2(5) and uc_scr_thread_ex2 = "10") or + (uc_scr_t3_l2(5) and uc_scr_thread_ex2 = "11"); + +q1hulpr_sign_ex2 <= (uc_scr_t0_l2(6) and uc_scr_thread_ex2 = "00") or + (uc_scr_t1_l2(6) and uc_scr_thread_ex2 = "01") or + (uc_scr_t2_l2(6) and uc_scr_thread_ex2 = "10") or + (uc_scr_t3_l2(6) and uc_scr_thread_ex2 = "11"); + +uc_round_mode_ex2(0) <= (uc_round_mode_l2(0) and uc_scr_thread_ex2 = "00") or + (uc_round_mode_l2(2) and uc_scr_thread_ex2 = "01") or + (uc_round_mode_l2(4) and uc_scr_thread_ex2 = "10") or + (uc_round_mode_l2(6) and uc_scr_thread_ex2 = "11"); + +uc_round_mode_ex2(1) <= (uc_round_mode_l2(1) and uc_scr_thread_ex2 = "00") or + (uc_round_mode_l2(3) and uc_scr_thread_ex2 = "01") or + (uc_round_mode_l2(5) and uc_scr_thread_ex2 = "10") or + (uc_round_mode_l2(7) and uc_scr_thread_ex2 = "11"); + + + +--@@ ESPRESSO ABLE START @@ +-- .i 7 +-- .o 2 +-- .ilb q1r_zero_ex2 q1ulpr_zero_ex2 uc_round_mode_ex2(0) uc_round_mode_ex2(1) q1r_sign_ex2 q1ulpr_sign_ex2 q1hulpr_sign_ex2 +-- .ob uc_gs_ex2(0) uc_gs_ex2(1) +-- .type fr +-- # +-- ################################################################################################################### +-- # +-- # q1r_zero_ex2 uc_round_mode_ex2 q1r_sign_ex2 uc_gs_ex2(0:1) +-- # | q1ulpr_zero_ex2 | | q1ulpr_sign_ex2 | +-- # | | | | | q1hulpr_sign_ex2 | +-- # | | | | | | | +-- ################################################################################################################### +-- +-- 0 1 -- - - - 00 +-- 1 0 -- - - - 00 +-- # Nearest +-- 0 0 00 0 0 - 01 +-- 0 0 00 0 1 0 11 +-- 0 0 00 0 1 1 01 +-- 0 0 00 1 1 - 11 +-- # Zero +-- 0 0 01 - - - 01 +-- # +Inf +-- 0 0 10 - - - 01 +-- # -Inf +-- 0 0 11 - - - 01 +-- ################################################################################################################### +-- .e +--@@ ESPRESSO ABLE END @@ + +--@@ ESPRESSO OGIC START @@ +-- logic generated on: Thu Jul 19 13:06:53 2007 +uc_gs_ex2(0) <= (not q1r_zero_ex2 and not q1ulpr_zero_ex2 and not uc_round_mode_ex2(0) + and not uc_round_mode_ex2(1) and q1ulpr_sign_ex2 + and not q1hulpr_sign_ex2) or + (not q1r_zero_ex2 and not q1ulpr_zero_ex2 + and not uc_round_mode_ex2(0) and not uc_round_mode_ex2(1) + and q1r_sign_ex2); + +uc_gs_ex2(1) <= (not q1r_zero_ex2 and not q1ulpr_zero_ex2); + +--@@ ESPRESSO OGIC END @@ + + + + + f_dcd_ex2_uc_gs_v <= uc_gs_v_ex2 and not perr_sm_running ; + f_dcd_ex2_uc_gs <= uc_gs_ex2(0 to 1); + f_dcd_ex2_uc_inc_lsb <= uc_inc_lsb_ex2 and not perr_sm_running ; + + +uc_ignore_flush_rf1 <= uc_div_beg_rf1 or uc_sqrt_beg_rf1; + + + + + + + + +-- when stage rf1 is valid the uc_scr will be sent out for the active thread +-- when stage rf0 and rf1 are not valid the uc_scr will be sent out for thread 0 +-- when stage rf0 is valid and rf1 is not the stage 0 hook bits will be sent out + +evnt_div_sqrt_ip(0 to 3) <= uc_scr_t0_l2(7) & uc_scr_t1_l2(7) & uc_scr_t2_l2(7) & uc_scr_t3_l2(7); + + +uc_hooks_debug( 0 to 7) <= uc_scr_t0_l2(0 to 7); +uc_hooks_debug( 8 to 15) <= uc_scr_t1_l2(0 to 7); +uc_hooks_debug(16 to 23) <= uc_scr_t2_l2(0 to 7); +uc_hooks_debug(24 to 31) <= uc_scr_t3_l2(0 to 7); + +uc_hooks_debug(32 to 35) <= uc_1st_instr_l2(0 to 3); +uc_hooks_debug(36) <= uc_div_beg_rf1 ; +uc_hooks_debug(37) <= uc_sqrt_beg_rf1 ; +uc_hooks_debug(38) <= uc_mid_rf1 ; +uc_hooks_debug(39) <= uc_end_rf1 ; +uc_hooks_debug(40) <= uc_fa_pos_rf1 ; +uc_hooks_debug(41) <= uc_fc_pos_rf1 ; +uc_hooks_debug(42) <= uc_fb_pos_rf1 ; +uc_hooks_debug(43) <= uc_fc_hulp_rf1 ; +uc_hooks_debug(44) <= uc_fc_0_5_rf1 ; +uc_hooks_debug(45) <= uc_fc_1_0_rf1 ; +uc_hooks_debug(46) <= uc_fc_1_minus_rf1 ; +uc_hooks_debug(47) <= uc_fb_1_0_rf1 ; +uc_hooks_debug(48) <= uc_fb_0_75_rf1 ; +uc_hooks_debug(49) <= uc_fb_0_5_rf1 ; +uc_hooks_debug(50) <= uc_op_rnd_v_rf1_l2 ; +uc_hooks_debug(51) <= uc_op_rnd_rf1_l2(0) ; +uc_hooks_debug(52) <= uc_op_rnd_rf1_l2(1) ; + +uc_hooks_debug(53) <= uc_end_rf1_l2 ; +uc_hooks_debug(54 to 55) <= uc_scr_thread_ex1(0 to 1) ; + + +-- Unused Nets +spare_unused(0 to 19) <= rf0_i(6 to 25); +spare_unused(20) <= rf0_i(31); +spare_unused(21) <= spare; + +-- scan ring connections + + uc_1st_instr_scin <= f_ucode_si & uc_1st_instr_scout(0 to 2); + uc_round_mode_scin <= uc_1st_instr_scout(3) & uc_round_mode_scout(0 to 6); + uc_scr_t0_scin <= uc_round_mode_scout(7) & uc_scr_t0_scout(0 to 10); + uc_scr_t1_scin <= uc_scr_t0_scout(11) & uc_scr_t1_scout(0 to 10); + uc_scr_t2_scin <= uc_scr_t1_scout(11) & uc_scr_t2_scout(0 to 10); + uc_scr_t3_scin <= uc_scr_t2_scout(11) & uc_scr_t3_scout(0 to 10); + uc_scr_wr_pipe_rf1_scin <= uc_scr_t3_scout(11) & uc_scr_wr_pipe_rf1_scout(0 to 6); + uc_scr_wr_pipe_ex1_scin <= uc_scr_wr_pipe_rf1_scout(7) & uc_scr_wr_pipe_ex1_scout(0 to 7); + uc_scr_wr_pipe_ex2_scin <= uc_scr_wr_pipe_ex1_scout(8) & uc_scr_wr_pipe_ex2_scout(0 to 7); + uc_scr_wr_pipe_ex3_scin <= uc_scr_wr_pipe_ex2_scout(8) & uc_scr_wr_pipe_ex3_scout(0 to 5); + uc_scr_wr_pipe_ex4_scin <= uc_scr_wr_pipe_ex3_scout(6) & uc_scr_wr_pipe_ex4_scout(0 to 5); + uc_scr_wr_pipe_ex5_scin <= uc_scr_wr_pipe_ex4_scout(6) & uc_scr_wr_pipe_ex5_scout(0 to 4); + uc_scr_wr_pipe_ex6_scin <= uc_scr_wr_pipe_ex5_scout(5) & uc_scr_wr_pipe_ex6_scout(0 to 4); + q1_p_ulp_early_scin <= uc_scr_wr_pipe_ex6_scout(5) & q1_p_ulp_early_scout(0 to 2); + pipe_rf1_scin <= q1_p_ulp_early_scout(3) & pipe_rf1_scout(0 to 20); + f_ucode_so <= pipe_rf1_scout(21); + + + +end fuq_dcd_uc_hooks; diff --git a/rel/src/vhdl/work/fuq_eie.vhdl b/rel/src/vhdl/work/fuq_eie.vhdl new file mode 100644 index 0000000..e5df4d9 --- /dev/null +++ b/rel/src/vhdl/work/fuq_eie.vhdl @@ -0,0 +1,704 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + +-- assuming the operand latches are in here, does not need to be true. + +-- is1 +-- is2 +-- rf0 +-- rf1 +-- ex1 <== this macro +-- ex2 <== this macro +-- ex3 <== this macro + + +entity fuq_eie is +generic( expand_type : integer := 2 ); -- 0 - ibm tech, 1 - other ); +port( + + vdd :inout power_logic; + gnd :inout power_logic; + clkoff_b :in std_ulogic; -- tiup + act_dis :in std_ulogic; -- ??tidn?? + flush :in std_ulogic; -- ??tidn?? + delay_lclkr :in std_ulogic_vector(2 to 3); -- tidn, + mpw1_b :in std_ulogic_vector(2 to 3); -- tidn, + mpw2_b :in std_ulogic_vector(0 to 0); -- tidn, + sg_1 :in std_ulogic; + thold_1 :in std_ulogic; + fpu_enable :in std_ulogic; --dc_act + nclk :in clk_logic; + + f_eie_si :in std_ulogic ;-- perv + f_eie_so :out std_ulogic ;-- perv + ex1_act :in std_ulogic ;-- act + + f_byp_eie_ex1_a_expo :in std_ulogic_vector(1 to 13) ; + f_byp_eie_ex1_c_expo :in std_ulogic_vector(1 to 13) ; + f_byp_eie_ex1_b_expo :in std_ulogic_vector(1 to 13) ; + + f_pic_ex1_from_integer :in std_ulogic ; + f_pic_ex1_fsel :in std_ulogic ; + f_pic_ex2_frsp_ue1 :in std_ulogic ; + + f_alg_ex2_sel_byp :in std_ulogic ; + f_fmt_ex2_fsel_bsel :in std_ulogic ; + f_pic_ex2_force_sel_bexp :in std_ulogic ; + f_pic_ex2_sp_b :in std_ulogic ; + f_pic_ex2_math_bzer_b :in std_ulogic ; + + f_eie_ex2_tbl_expo :out std_ulogic_vector(1 to 13) ; + + f_eie_ex2_lt_bias :out std_ulogic ; --f_pic + f_eie_ex2_eq_bias_m1 :out std_ulogic ; --f_pic + f_eie_ex2_wd_ov :out std_ulogic ; --f_pic + f_eie_ex2_dw_ov :out std_ulogic ; --f_pic + f_eie_ex2_wd_ov_if :out std_ulogic ; --f_pic + f_eie_ex2_dw_ov_if :out std_ulogic ; --f_pic + f_eie_ex2_lzo_expo :out std_ulogic_vector(1 to 13) ; --dlza to lzo + f_eie_ex2_b_expo :out std_ulogic_vector(1 to 13) ; --dlza to lzo + f_eie_ex2_use_bexp :out std_ulogic; + f_eie_ex3_iexp :out std_ulogic_vector(1 to 13) --deov to lzasub + +); -- end ports + + + +end fuq_eie; -- ENTITY + + +architecture fuq_eie of fuq_eie is + + constant tiup :std_ulogic := '1'; + constant tidn :std_ulogic := '0'; + + signal sg_0 :std_ulogic ; + signal thold_0_b , thold_0, forcee :std_ulogic ; + + signal ex2_act :std_ulogic ; + signal act_spare_unused :std_ulogic_vector(0 to 3) ; + ------------------- + signal act_so :std_ulogic_vector(0 to 4) ;--SCAN + signal act_si :std_ulogic_vector(0 to 4) ;--SCAN + signal ex2_bop_so :std_ulogic_vector(0 to 12) ;--SCAN + signal ex2_bop_si :std_ulogic_vector(0 to 12) ;--SCAN + signal ex2_pop_so :std_ulogic_vector(0 to 12) ;--SCAN + signal ex2_pop_si :std_ulogic_vector(0 to 12) ;--SCAN + signal ex2_ctl_so :std_ulogic_vector(0 to 6) ;--SCAN + signal ex2_ctl_si :std_ulogic_vector(0 to 6) ;--SCAN + signal ex3_iexp_so :std_ulogic_vector(0 to 13) ;--SCAN + signal ex3_iexp_si :std_ulogic_vector(0 to 13) ;--SCAN + ------------------- + signal ex1_a_expo :std_ulogic_vector(1 to 13) ; + signal ex1_c_expo :std_ulogic_vector(1 to 13) ; + signal ex1_b_expo :std_ulogic_vector(1 to 13) ; + signal ex1_ep56_sum :std_ulogic_vector(1 to 13) ; + signal ex1_ep56_car :std_ulogic_vector(1 to 12) ; + signal ex1_ep56_p :std_ulogic_vector(1 to 13) ; + signal ex1_ep56_g :std_ulogic_vector(2 to 12) ; + signal ex1_ep56_t :std_ulogic_vector(2 to 11) ; + signal ex1_ep56_s :std_ulogic_vector(1 to 13) ; + signal ex1_ep56_c :std_ulogic_vector(2 to 12) ; + signal ex1_p_expo_adj :std_ulogic_vector(1 to 13) ; + signal ex1_from_k :std_ulogic_vector(1 to 13) ; + signal ex1_b_expo_adj :std_ulogic_vector(1 to 13) ; + signal ex2_p_expo :std_ulogic_vector(1 to 13) ; + signal ex2_b_expo :std_ulogic_vector(1 to 13) ; + signal ex2_iexp :std_ulogic_vector(1 to 13) ; + signal ex2_b_expo_adj :std_ulogic_vector(1 to 13) ; + signal ex2_p_expo_adj :std_ulogic_vector(1 to 13) ; + signal ex3_iexp :std_ulogic_vector(1 to 13) ; + signal ex1_wd_ge_bot :std_ulogic ; + signal ex1_dw_ge_bot :std_ulogic ; + signal ex1_ge_2048 :std_ulogic ; + signal ex1_ge_1024 :std_ulogic ; + signal ex1_dw_ge_mid :std_ulogic ; + signal ex1_wd_ge_mid :std_ulogic ; + signal ex1_dw_ge :std_ulogic ; + signal ex1_wd_ge :std_ulogic ; + signal ex1_dw_eq_top :std_ulogic ; + signal ex1_wd_eq_bot :std_ulogic ; + signal ex1_wd_eq :std_ulogic ; + signal ex1_dw_eq :std_ulogic ; + signal ex2_iexp_b_sel :std_ulogic ; + signal ex2_dw_ge :std_ulogic ; + signal ex2_wd_ge :std_ulogic ; + signal ex2_wd_eq :std_ulogic ; + signal ex2_dw_eq :std_ulogic ; + signal ex2_fsel :std_ulogic ; + signal ex3_sp_b :std_ulogic ; + + + signal ex2_b_expo_fixed :std_ulogic_vector(1 to 13); --experiment sp_den/dp_fmt + signal ex1_ge_bias, ex1_lt_bias, ex1_eq_bias_m1 :std_ulogic; + signal ex2_lt_bias, ex2_eq_bias_m1 :std_ulogic; + signal ex1_ep56_g2 :std_ulogic_vector( 2 to 12); + signal ex1_ep56_t2 :std_ulogic_vector( 2 to 10); + signal ex1_ep56_g4 :std_ulogic_vector( 2 to 12); + signal ex1_ep56_t4 :std_ulogic_vector( 2 to 8); + signal ex1_ep56_g8 :std_ulogic_vector( 2 to 12); + signal ex1_ep56_t8 :std_ulogic_vector( 2 to 4); + + + +begin + +--//############################################ +--//# pervasive +--//############################################ + + + thold_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => thold_1, + q(0) => thold_0 ); + + sg_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => sg_1 , + q(0) => sg_0 ); + + + lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map ( + clkoff_b => clkoff_b, + thold => thold_0, + sg => sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => thold_0_b ); + + + + +--//############################################ +--//# ACT LATCHES +--//############################################ + + + act_lat: tri_rlmreg_p generic map (width=> 5, expand_type => expand_type, needs_sreset => 0) port map ( + forcee => forcee,--tidn, + delay_lclkr => delay_lclkr(2) ,--tidn, + mpw1_b => mpw1_b(2) ,--tidn, + mpw2_b => mpw2_b(0) ,--tidn, + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => fpu_enable, + scout => act_so , + scin => act_si , + ------------------- + din(0) => act_spare_unused(0), + din(1) => act_spare_unused(1), + din(2) => ex1_act, + din(3) => act_spare_unused(2), + din(4) => act_spare_unused(3), + ------------------- + dout(0) => act_spare_unused(0), + dout(1) => act_spare_unused(1), + dout(2) => ex2_act, + dout(3) => act_spare_unused(2), + dout(4) => act_spare_unused(3) ); + + +--//############################################## +--//# EX1 latch inputs from rf1 +--//############################################## + + ex1_a_expo(1 to 13) <= f_byp_eie_ex1_a_expo(1 to 13); + ex1_c_expo(1 to 13) <= f_byp_eie_ex1_c_expo(1 to 13); + ex1_b_expo(1 to 13) <= f_byp_eie_ex1_b_expo(1 to 13); + + +--//############################################## +--//# EX1 logic +--//############################################## + + --//##------------------------------------------------------------------------- + --//## Product Exponent adder (+56 scouta subtract gives final resutl) + --//##------------------------------------------------------------------------- + -- rebiased from 1023 to 4095 ... (append 2 ones) + -- ep56 : Ec + Ea -bias + -- ep0 : Ec + Ea -bias + 56 = Ec + Ea -4095 + 56 + -- + -- 0_0011_1111_1111 + -- 1_1100_0000_0001 !1023 + 1 = -1023 + -- 11_1000 56 + -------------------- + -- 1_1100_0011_1001 + Ea + Ec + -- + + ex1_ep56_sum( 1) <= not( ex1_a_expo( 1) xor ex1_c_expo( 1) ); -- 1 + ex1_ep56_sum( 2) <= not( ex1_a_expo( 2) xor ex1_c_expo( 2) ); -- 1 + ex1_ep56_sum( 3) <= not( ex1_a_expo( 3) xor ex1_c_expo( 3) ); -- 1 + ex1_ep56_sum( 4) <= ( ex1_a_expo( 4) xor ex1_c_expo( 4) ); -- 0 + ex1_ep56_sum( 5) <= ( ex1_a_expo( 5) xor ex1_c_expo( 5) ); -- 0 + ex1_ep56_sum( 6) <= ( ex1_a_expo( 6) xor ex1_c_expo( 6) ); -- 0 + ex1_ep56_sum( 7) <= ( ex1_a_expo( 7) xor ex1_c_expo( 7) ); -- 0 + ex1_ep56_sum( 8) <= not( ex1_a_expo( 8) xor ex1_c_expo( 8) ); -- 1 + ex1_ep56_sum( 9) <= not( ex1_a_expo( 9) xor ex1_c_expo( 9) ); -- 1 + ex1_ep56_sum(10) <= not( ex1_a_expo(10) xor ex1_c_expo(10) ); -- 1 + ex1_ep56_sum(11) <= ( ex1_a_expo(11) xor ex1_c_expo(11) ); -- 0 + ex1_ep56_sum(12) <= ( ex1_a_expo(12) xor ex1_c_expo(12) ); -- 0 + ex1_ep56_sum(13) <= not( ex1_a_expo(13) xor ex1_c_expo(13) ); -- 1 + + ex1_ep56_car( 1) <= ( ex1_a_expo( 2) or ex1_c_expo( 2) ); -- 1 + ex1_ep56_car( 2) <= ( ex1_a_expo( 3) or ex1_c_expo( 3) ); -- 1 + ex1_ep56_car( 3) <= ( ex1_a_expo( 4) and ex1_c_expo( 4) ); -- 0 + ex1_ep56_car( 4) <= ( ex1_a_expo( 5) and ex1_c_expo( 5) ); -- 0 + ex1_ep56_car( 5) <= ( ex1_a_expo( 6) and ex1_c_expo( 6) ); -- 0 + ex1_ep56_car( 6) <= ( ex1_a_expo( 7) and ex1_c_expo( 7) ); -- 0 + ex1_ep56_car( 7) <= ( ex1_a_expo( 8) or ex1_c_expo( 8) ); -- 1 + ex1_ep56_car( 8) <= ( ex1_a_expo( 9) or ex1_c_expo( 9) ); -- 1 + ex1_ep56_car( 9) <= ( ex1_a_expo(10) or ex1_c_expo(10) ); -- 1 + ex1_ep56_car(10) <= ( ex1_a_expo(11) and ex1_c_expo(11) ); -- 0 + ex1_ep56_car(11) <= ( ex1_a_expo(12) and ex1_c_expo(12) ); -- 0 + ex1_ep56_car(12) <= ( ex1_a_expo(13) or ex1_c_expo(13) ); -- 1 + + ex1_ep56_p(1 to 12) <= ex1_ep56_sum(1 to 12) xor ex1_ep56_car(1 to 12); + ex1_ep56_p(13) <= ex1_ep56_sum(13); + ex1_ep56_g(2 to 12) <= ex1_ep56_sum(2 to 12) and ex1_ep56_car(2 to 12); + ex1_ep56_t(2 to 11) <= ex1_ep56_sum(2 to 11) or ex1_ep56_car(2 to 11); + + ex1_ep56_s(1 to 11) <= ex1_ep56_p(1 to 11) xor ex1_ep56_c(2 to 12); + ex1_ep56_s(12) <= ex1_ep56_p(12); + ex1_ep56_s(13) <= ex1_ep56_p(13); + + + ex1_ep56_g2(12) <= ex1_ep56_g(12) ; + ex1_ep56_g2(11) <= ex1_ep56_g(11) or (ex1_ep56_t(11) and ex1_ep56_g(12)) ; + ex1_ep56_g2(10) <= ex1_ep56_g(10) or (ex1_ep56_t(10) and ex1_ep56_g(11)) ; + ex1_ep56_g2( 9) <= ex1_ep56_g( 9) or (ex1_ep56_t( 9) and ex1_ep56_g(10)) ; + ex1_ep56_g2( 8) <= ex1_ep56_g( 8) or (ex1_ep56_t( 8) and ex1_ep56_g( 9)) ; + ex1_ep56_g2( 7) <= ex1_ep56_g( 7) or (ex1_ep56_t( 7) and ex1_ep56_g( 8)) ; + ex1_ep56_g2( 6) <= ex1_ep56_g( 6) or (ex1_ep56_t( 6) and ex1_ep56_g( 7)) ; + ex1_ep56_g2( 5) <= ex1_ep56_g( 5) or (ex1_ep56_t( 5) and ex1_ep56_g( 6)) ; + ex1_ep56_g2( 4) <= ex1_ep56_g( 4) or (ex1_ep56_t( 4) and ex1_ep56_g( 5)) ; + ex1_ep56_g2( 3) <= ex1_ep56_g( 3) or (ex1_ep56_t( 3) and ex1_ep56_g( 4)) ; + ex1_ep56_g2( 2) <= ex1_ep56_g( 2) or (ex1_ep56_t( 2) and ex1_ep56_g( 3)) ; + + ex1_ep56_t2(10) <= (ex1_ep56_t(10) and ex1_ep56_t(11)) ; + ex1_ep56_t2( 9) <= (ex1_ep56_t( 9) and ex1_ep56_t(10)) ; + ex1_ep56_t2( 8) <= (ex1_ep56_t( 8) and ex1_ep56_t( 9)) ; + ex1_ep56_t2( 7) <= (ex1_ep56_t( 7) and ex1_ep56_t( 8)) ; + ex1_ep56_t2( 6) <= (ex1_ep56_t( 6) and ex1_ep56_t( 7)) ; + ex1_ep56_t2( 5) <= (ex1_ep56_t( 5) and ex1_ep56_t( 6)) ; + ex1_ep56_t2( 4) <= (ex1_ep56_t( 4) and ex1_ep56_t( 5)) ; + ex1_ep56_t2( 3) <= (ex1_ep56_t( 3) and ex1_ep56_t( 4)) ; + ex1_ep56_t2( 2) <= (ex1_ep56_t( 2) and ex1_ep56_t( 3)) ; + + ex1_ep56_g4(12) <= ex1_ep56_g2(12) ; + ex1_ep56_g4(11) <= ex1_ep56_g2(11) ; + ex1_ep56_g4(10) <= ex1_ep56_g2(10) or (ex1_ep56_t2(10) and ex1_ep56_g2(12)) ; + ex1_ep56_g4( 9) <= ex1_ep56_g2( 9) or (ex1_ep56_t2( 9) and ex1_ep56_g2(11)) ; + ex1_ep56_g4( 8) <= ex1_ep56_g2( 8) or (ex1_ep56_t2( 8) and ex1_ep56_g2(10)) ; + ex1_ep56_g4( 7) <= ex1_ep56_g2( 7) or (ex1_ep56_t2( 7) and ex1_ep56_g2( 9)) ; + ex1_ep56_g4( 6) <= ex1_ep56_g2( 6) or (ex1_ep56_t2( 6) and ex1_ep56_g2( 8)) ; + ex1_ep56_g4( 5) <= ex1_ep56_g2( 5) or (ex1_ep56_t2( 5) and ex1_ep56_g2( 7)) ; + ex1_ep56_g4( 4) <= ex1_ep56_g2( 4) or (ex1_ep56_t2( 4) and ex1_ep56_g2( 6)) ; + ex1_ep56_g4( 3) <= ex1_ep56_g2( 3) or (ex1_ep56_t2( 3) and ex1_ep56_g2( 5)) ; + ex1_ep56_g4( 2) <= ex1_ep56_g2( 2) or (ex1_ep56_t2( 2) and ex1_ep56_g2( 4)) ; + + ex1_ep56_t4( 8) <= (ex1_ep56_t2( 8) and ex1_ep56_t2(10)) ; + ex1_ep56_t4( 7) <= (ex1_ep56_t2( 7) and ex1_ep56_t2( 9)) ; + ex1_ep56_t4( 6) <= (ex1_ep56_t2( 6) and ex1_ep56_t2( 8)) ; + ex1_ep56_t4( 5) <= (ex1_ep56_t2( 5) and ex1_ep56_t2( 7)) ; + ex1_ep56_t4( 4) <= (ex1_ep56_t2( 4) and ex1_ep56_t2( 6)) ; + ex1_ep56_t4( 3) <= (ex1_ep56_t2( 3) and ex1_ep56_t2( 5)) ; + ex1_ep56_t4( 2) <= (ex1_ep56_t2( 2) and ex1_ep56_t2( 4)) ; + + ex1_ep56_g8(12) <= ex1_ep56_g4(12) ; + ex1_ep56_g8(11) <= ex1_ep56_g4(11) ; + ex1_ep56_g8(10) <= ex1_ep56_g4(10) ; + ex1_ep56_g8( 9) <= ex1_ep56_g4( 9) ; + ex1_ep56_g8( 8) <= ex1_ep56_g4( 8) or (ex1_ep56_t4( 8) and ex1_ep56_g4(12)) ; + ex1_ep56_g8( 7) <= ex1_ep56_g4( 7) or (ex1_ep56_t4( 7) and ex1_ep56_g4(11)) ; + ex1_ep56_g8( 6) <= ex1_ep56_g4( 6) or (ex1_ep56_t4( 6) and ex1_ep56_g4(10)) ; + ex1_ep56_g8( 5) <= ex1_ep56_g4( 5) or (ex1_ep56_t4( 5) and ex1_ep56_g4( 9)) ; + ex1_ep56_g8( 4) <= ex1_ep56_g4( 4) or (ex1_ep56_t4( 4) and ex1_ep56_g4( 8)) ; + ex1_ep56_g8( 3) <= ex1_ep56_g4( 3) or (ex1_ep56_t4( 3) and ex1_ep56_g4( 7)) ; + ex1_ep56_g8( 2) <= ex1_ep56_g4( 2) or (ex1_ep56_t4( 2) and ex1_ep56_g4( 6)) ; + + ex1_ep56_t8( 4) <= (ex1_ep56_t4( 4) and ex1_ep56_t4( 8)) ; + ex1_ep56_t8( 3) <= (ex1_ep56_t4( 3) and ex1_ep56_t4( 7)) ; + ex1_ep56_t8( 2) <= (ex1_ep56_t4( 2) and ex1_ep56_t4( 6)) ; + + ex1_ep56_c(12) <= ex1_ep56_g8(12) ; + ex1_ep56_c(11) <= ex1_ep56_g8(11) ; + ex1_ep56_c(10) <= ex1_ep56_g8(10) ; + ex1_ep56_c( 9) <= ex1_ep56_g8( 9) ; + ex1_ep56_c( 8) <= ex1_ep56_g8( 8) ; + ex1_ep56_c( 7) <= ex1_ep56_g8( 7) ; + ex1_ep56_c( 6) <= ex1_ep56_g8( 6) ; + ex1_ep56_c( 5) <= ex1_ep56_g8( 5) ; + ex1_ep56_c( 4) <= ex1_ep56_g8( 4) or (ex1_ep56_t8( 4) and ex1_ep56_g8(12)) ; + ex1_ep56_c( 3) <= ex1_ep56_g8( 3) or (ex1_ep56_t8( 3) and ex1_ep56_g8(11)) ; + ex1_ep56_c( 2) <= ex1_ep56_g8( 2) or (ex1_ep56_t8( 2) and ex1_ep56_g8(10)) ; + + + + + --//##--------------------------------------- + --//## hold onto c_exponent for fsel + --//##--------------------------------------- + + ex1_p_expo_adj(1 to 13) <= + ( ex1_ep56_s(1 to 13) and (1 to 13 => not f_pic_ex1_fsel) ) or + ( ex1_c_expo(1 to 13) and (1 to 13 => f_pic_ex1_fsel) ); + + + --//##--------------------------------------- + --//## select b exponent + --//##--------------------------------------- + + -- From integer exponent + -- lsb is at position 162, and value = bias + -- therefore set b_expo to (bias+162) + -- 0_1111_1111_1111 1023 = bias + -- 101_0010 162 + -- ---------------- ---- + -- 1_0000_0101_0001 4096+57 + -- 1 2345 6789 0123 + + ex1_from_k( 1) <= tidn; -- 4096 + ex1_from_k( 2) <= tidn; -- 2048 + ex1_from_k( 3) <= tiup; -- 1024 + ex1_from_k( 4) <= tidn; -- 512 + ex1_from_k( 5) <= tidn; -- 256 + ex1_from_k( 6) <= tiup; -- 128 + ex1_from_k( 7) <= tidn; -- 64 + ex1_from_k( 8) <= tiup; -- 32 + ex1_from_k( 9) <= tidn; -- 16 + ex1_from_k(10) <= tidn; -- 8 + ex1_from_k(11) <= tidn; -- 4 + ex1_from_k(12) <= tidn; -- 2 + ex1_from_k(13) <= tiup; -- 1 + + ex1_b_expo_adj(1 to 13) <= + ( ex1_from_k (1 to 13) and (1 to 13=> f_pic_ex1_from_integer ) ) or + ( ex1_b_expo (1 to 13) and (1 to 13=> not f_pic_ex1_from_integer ) ) ; + + + + --//##--------------------------------------- + --//## to integer overflow boundaries + --//##--------------------------------------- + -- convert to signed_word: + -- pos int ov ge 2**31 1023+31 + -- ov eq 2**30 * rnd_up 1023+30 <= just look at final MSB position + -- neg int ov gt 2**31 1023+31 + -- neg int ov eq 2**31 1023+31 & frac[1:*] != 0 + + -- convert to signed_doubleword: + -- pos int ov ge 2**63 1023+63 1086 + -- ov eq 2**62 * rnd_up 1023+62 1085 <=== just look at final msb position + -- neg int ov gt 2**63 1023+63 1086 + -- neg int ov eq 2**63 1023+63 1086 & frac[1:*] != 0; + -- + -- 0_0011_1111_1111 bias 1023 + -- 10_0000 32 + -- 0_0100 0001 1111 <=== ge + -- + -- 0_0011_1111_1111 bias 1023 + -- 1_1111 31 + -- 0_0100 0001 1110 <=== eq + -- + -- 0_0011_1111_1111 bias 1023 + -- 100_0000 64 + -- 0_0100 0011 1111 <==== ge 1087 + -- + -- 0_0011_1111_1111 bias 1023 + -- 11_1111 63 + -- 0_0100 0011 1110 <==== eq 1086 + -- + -- 1111 + -- 1 2345 6789 0123 + -- + -- if exponent less than bias (1023) + -- positive input if +rnd_up result = +ulp (ok) int 1 + -- positive input if -rnd_up result = +0 (ok) int 0 + -- negative input if +rnd_up result = -ulp (ok) int -1 (no increment) + -- negative input if -rnd_up result = +0 <== ??force sign?? + -- normalizer shifts wrong (98)=1 + + + + ex1_wd_ge_bot <= ex1_b_expo( 9) and + ex1_b_expo(10) and + ex1_b_expo(11) and + ex1_b_expo(12) and + ex1_b_expo(13) ; + + ex1_dw_ge_bot <= ex1_b_expo( 8) and + ex1_wd_ge_bot ; + + ex1_ge_2048 <= not ex1_b_expo( 1) and ex1_b_expo( 2) ; + ex1_ge_1024 <= not ex1_b_expo( 1) and ex1_b_expo( 3) ; + + ex1_dw_ge_mid <= ex1_b_expo( 4) or + ex1_b_expo( 5) or + ex1_b_expo( 6) or + ex1_b_expo( 7) ; + + ex1_wd_ge_mid <= ex1_b_expo( 8) or + ex1_dw_ge_mid ; + + ex1_dw_ge <= ( ex1_ge_2048 ) or + ( ex1_ge_1024 and ex1_dw_ge_mid ) or + ( ex1_ge_1024 and ex1_dw_ge_bot ) ; + + ex1_wd_ge <= ( ex1_ge_2048 ) or + ( ex1_ge_1024 and ex1_wd_ge_mid ) or + ( ex1_ge_1024 and ex1_wd_ge_bot ) ; + + ex1_dw_eq_top <= not ex1_b_expo( 1) and + not ex1_b_expo( 2) and + ex1_b_expo( 3) and + not ex1_b_expo( 4) and + not ex1_b_expo( 5) and + not ex1_b_expo( 6) and + not ex1_b_expo( 7) ; + + ex1_wd_eq_bot <= ex1_b_expo( 9) and + ex1_b_expo(10) and + ex1_b_expo(11) and + ex1_b_expo(12) and + not ex1_b_expo(13) ; + + ex1_wd_eq <= ex1_dw_eq_top and + not ex1_b_expo( 8) and + ex1_wd_eq_bot ; + + ex1_dw_eq <= ex1_dw_eq_top and + ex1_b_expo( 8) and + ex1_wd_eq_bot ; + + + + + ex1_ge_bias <= -- for rnd_to_int + (not ex1_b_expo(1) and ex1_b_expo(2) ) or + (not ex1_b_expo(1) and ex1_b_expo(3) ) or + (not ex1_b_expo(1) and ex1_b_expo(4) and + ex1_b_expo(5) and + ex1_b_expo(6) and + ex1_b_expo(7) and + ex1_b_expo(8) and + ex1_b_expo(9) and + ex1_b_expo(10) and + ex1_b_expo(11) and + ex1_b_expo(12) and + ex1_b_expo(13) ); + + ex1_lt_bias <= not ex1_ge_bias; + ex1_eq_bias_m1 <= -- rnd-to-int nearest rounds up + not ex1_b_expo(1) and -- sign + not ex1_b_expo(2) and -- 2048 + not ex1_b_expo(3) and -- 1024 + ex1_b_expo(4) and -- 512 + ex1_b_expo(5) and -- 256 + ex1_b_expo(6) and -- 128 + ex1_b_expo(7) and -- 64 + ex1_b_expo(8) and -- 32 + ex1_b_expo(9) and -- 16 + ex1_b_expo(10) and -- 8 + ex1_b_expo(11) and -- 4 + ex1_b_expo(12) and -- 2 + not ex1_b_expo(13) ; -- 1 + + +--//############################################## +--//# EX2 latches +--//############################################## + + ex2_bop_lat: tri_rlmreg_p generic map (width=> 13, expand_type => expand_type, needs_sreset => 0) port map ( + forcee => forcee,--tidn, + delay_lclkr => delay_lclkr(2) ,--tidn, + mpw1_b => mpw1_b(2) ,--tidn, + mpw2_b => mpw2_b(0) ,--tidn, + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => ex1_act, + scout => ex2_bop_so , + scin => ex2_bop_si , + ------------------- + din(0 to 12) => ex1_b_expo_adj (1 to 13) , + dout(0 to 12) => ex2_b_expo_adj (1 to 13) );--LAT-- + + ex2_pop_lat: tri_rlmreg_p generic map (width=> 13, expand_type => expand_type, needs_sreset => 0) port map ( + forcee => forcee,--tidn, + delay_lclkr => delay_lclkr(2) ,--tidn, + mpw1_b => mpw1_b(2) ,--tidn, + mpw2_b => mpw2_b(0) ,--tidn, + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => ex1_act, + scout => ex2_pop_so , + scin => ex2_pop_si , + ------------------- + din(0 to 12) => ex1_p_expo_adj (1 to 13) , + dout(0 to 12) => ex2_p_expo_adj (1 to 13) );--LAT-- + + ex2_ctl_lat: tri_rlmreg_p generic map (width=> 7, expand_type => expand_type, needs_sreset => 0) port map ( + forcee => forcee,--tidn, + delay_lclkr => delay_lclkr(2) ,--tidn, + mpw1_b => mpw1_b(2) ,--tidn, + mpw2_b => mpw2_b(0) ,--tidn, + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => ex1_act, + scout => ex2_ctl_so , + scin => ex2_ctl_si , + ------------------- + din(0) => ex1_dw_ge , + din(1) => ex1_wd_ge , + din(2) => ex1_wd_eq , + din(3) => ex1_dw_eq , + din(4) => f_pic_ex1_fsel, + din(5) => ex1_lt_bias , + din(6) => ex1_eq_bias_m1, + ------------------- + dout(0) => ex2_dw_ge , --LAT-- + dout(1) => ex2_wd_ge , --LAT-- + dout(2) => ex2_wd_eq , --LAT-- + dout(3) => ex2_dw_eq , --LAT-- + dout(4) => ex2_fsel , --LAT-- + dout(5) => ex2_lt_bias , --LAT-- + dout(6) => ex2_eq_bias_m1 ); --LAT-- + + f_eie_ex2_lt_bias <= ex2_lt_bias;--output --f_pic + f_eie_ex2_eq_bias_m1 <= ex2_eq_bias_m1;--output --f_pic + + ex2_p_expo(1 to 13) <= ex2_p_expo_adj (1 to 13); + ex2_b_expo(1 to 13) <= ex2_b_expo_adj (1 to 13); + + f_eie_ex2_wd_ov <= ex2_wd_ge ;--output --f_pic + f_eie_ex2_dw_ov <= ex2_dw_ge ;--output --f_pic + f_eie_ex2_wd_ov_if <= ex2_wd_eq ;--output --f_pic + f_eie_ex2_dw_ov_if <= ex2_dw_eq ;--output --f_pic + + f_eie_ex2_lzo_expo(1 to 13) <= ex2_p_expo_adj (1 to 13) ;--output --dlza for lzo + f_eie_ex2_b_expo(1 to 13) <= ex2_b_expo(1 to 13); + f_eie_ex2_tbl_expo(1 to 13) <= ex2_b_expo(1 to 13); + +--//############################################## +--//# EX2 logic +--//############################################## + + ex2_b_expo_fixed(1 to 13) <= ex2_b_expo(1 to 13) ; + + f_eie_ex2_use_bexp <= ex2_iexp_b_sel ; + + ex2_iexp_b_sel <= + (f_alg_ex2_sel_byp and not ex2_fsel and f_pic_ex2_math_bzer_b ) or --NAN/shOv + f_fmt_ex2_fsel_bsel or -- fsel + f_pic_ex2_force_sel_bexp or -- by opcode + f_pic_ex2_frsp_ue1 ; -- frsp with ue=1 always does bypass because must normalize anyway + -- if frsp(ue=1) has a shift unf, then loose bits and canot normalize) + + ex2_iexp(1 to 13) <= + ( ex2_b_expo_fixed(1 to 13) and (1 to 13 => ex2_iexp_b_sel) ) or --experiment sp_den/dp_fmt + ( ex2_p_expo(1 to 13) and (1 to 13 => not ex2_iexp_b_sel) ) ; + +--//############################################## +--//# EX3 latches +--//############################################## + + ex3_iexp_lat: tri_rlmreg_p generic map (width=> 14, expand_type => expand_type, needs_sreset => 0) port map ( + forcee => forcee,--tidn, + delay_lclkr => delay_lclkr(3) ,--tidn, + mpw1_b => mpw1_b(3) ,--tidn, + mpw2_b => mpw2_b(0) ,--tidn, + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => ex2_act, + scout => ex3_iexp_so , + scin => ex3_iexp_si , + ------------------- + din(0) => f_pic_ex2_sp_b , + din(1 to 13) => ex2_iexp (1 to 13) , + ------------------- + dout(0) => ex3_sp_b ,--LAT-- + dout(1 to 13) => ex3_iexp (1 to 13) );--LAT-- + + + + + f_eie_ex3_iexp(1 to 13) <= ex3_iexp(1 to 13) ;--output--feov + + +--//############################################## +--//# EX3 logic +--//############################################## + +--//############################################ +--//# scan +--//############################################ + + + ex2_bop_si (0 to 12) <= ex2_bop_so (1 to 12) & f_eie_si; + ex2_pop_si (0 to 12) <= ex2_pop_so (1 to 12) & ex2_bop_so (0); + ex2_ctl_si (0 to 6) <= ex2_ctl_so (1 to 6) & ex2_pop_so (0); + ex3_iexp_si (0 to 13) <= ex3_iexp_so (1 to 13) & ex2_ctl_so (0); + act_si (0 to 4) <= act_so (1 to 4) & ex3_iexp_so (0); + f_eie_so <= act_so (0); + + +end; -- fuq_eie ARCHITECTURE diff --git a/rel/src/vhdl/work/fuq_eov.vhdl b/rel/src/vhdl/work/fuq_eov.vhdl new file mode 100644 index 0000000..b151c0a --- /dev/null +++ b/rel/src/vhdl/work/fuq_eov.vhdl @@ -0,0 +1,1108 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + + +entity fuq_eov is +generic( expand_type : integer := 2 ); -- 0 - ibm tech, 1 - other ); +port( + + + vdd :inout power_logic; + gnd :inout power_logic; + clkoff_b :in std_ulogic; -- tiup + act_dis :in std_ulogic; -- ??tidn?? + flush :in std_ulogic; -- ??tidn?? + delay_lclkr :in std_ulogic_vector(4 to 5); -- tidn, + mpw1_b :in std_ulogic_vector(4 to 5); -- tidn, + mpw2_b :in std_ulogic_vector(0 to 1); -- tidn, + sg_1 :in std_ulogic; + thold_1 :in std_ulogic; + fpu_enable :in std_ulogic; --dc_act + nclk :in clk_logic; + + + + f_eov_si :in std_ulogic ;-- perv + f_eov_so :out std_ulogic ;-- perv + ex2_act_b :in std_ulogic ;-- act + + f_tbl_ex4_unf_expo :in std_ulogic ; + f_tbe_ex3_may_ov :in std_ulogic; + f_tbe_ex3_expo :in std_ulogic_vector(1 to 13) ; + f_pic_ex3_sel_est :in std_ulogic; + f_eie_ex3_iexp :in std_ulogic_vector(1 to 13) ; + + f_pic_ex3_sp_b :in std_ulogic ; + f_pic_ex4_oe :in std_ulogic ; + f_pic_ex4_ue :in std_ulogic ; + f_pic_ex4_ov_en :in std_ulogic ; + f_pic_ex4_uf_en :in std_ulogic ; + f_pic_ex4_spec_sel_k_e :in std_ulogic ; + f_pic_ex4_spec_sel_k_f :in std_ulogic ; + f_pic_ex4_sel_ov_spec :in std_ulogic ; + f_pic_ex4_to_int_ov_all :in std_ulogic ; + + f_lza_ex4_sh_rgt_en_eov :in std_ulogic; + f_lza_ex4_lza_amt_eov :in std_ulogic_vector(0 to 7) ; + f_lza_ex4_no_lza_edge :in std_ulogic ; + f_nrm_ex4_extra_shift :in std_ulogic ; + f_eov_ex4_may_ovf :out std_ulogic ;--//#pic generate constant + + f_eov_ex5_sel_k_f :out std_ulogic ;--//#rnd + f_eov_ex5_sel_k_e :out std_ulogic ;--//#rnd + f_eov_ex5_sel_kif_f :out std_ulogic ;--//#rnd + f_eov_ex5_sel_kif_e :out std_ulogic ;--//#rnd + f_eov_ex5_unf_expo :out std_ulogic ;--//#rnd for ux + f_eov_ex5_ovf_expo :out std_ulogic ;--//#rnd for INF,ox + f_eov_ex5_ovf_if_expo :out std_ulogic ;--//#rnd for INF,ox + f_eov_ex5_expo_p0 :out std_ulogic_vector(1 to 13) ;--//#rnd result exponent + f_eov_ex5_expo_p1 :out std_ulogic_vector(1 to 13) ;--//#rnd result exponent if rnd_up_all1 + f_eov_ex5_expo_p0_ue1oe1 :out std_ulogic_vector(3 to 7) ;--//#rnd + f_eov_ex5_expo_p1_ue1oe1 :out std_ulogic_vector(3 to 7) --//#rnd + +); -- end ports + +-- synopsys translate_off + + + +-- synopsys translate_on + +end fuq_eov; -- ENTITY + + +architecture fuq_eov of fuq_eov is + + constant tiup :std_ulogic := '1'; + constant tidn :std_ulogic := '0'; + + signal sg_0 :std_ulogic ; + signal thold_0_b, thold_0, forcee :std_ulogic ; + signal ex3_act :std_ulogic ; + signal ex2_act :std_ulogic ; + signal ex4_act :std_ulogic ; + signal act_spare_unused :std_ulogic_vector(0 to 2) ; + ------------------- + signal act_so :std_ulogic_vector(0 to 4) ;--SCAN + signal act_si :std_ulogic_vector(0 to 4) ;--SCAN + signal ex4_iexp_so :std_ulogic_vector(0 to 15) ;--SCAN + signal ex4_iexp_si :std_ulogic_vector(0 to 15) ;--SCAN + signal ex5_ovctl_so :std_ulogic_vector(0 to 2) ;--SCAN + signal ex5_ovctl_si :std_ulogic_vector(0 to 2) ;--SCAN + signal ex5_misc_so :std_ulogic_vector(0 to 12) ;--SCAN + signal ex5_misc_si :std_ulogic_vector(0 to 12) ;--SCAN + signal ex5_urnd0_so :std_ulogic_vector(0 to 12) ;--SCAN + signal ex5_urnd0_si :std_ulogic_vector(0 to 12) ;--SCAN + signal ex5_urnd1_so :std_ulogic_vector(0 to 12) ;--SCAN + signal ex5_urnd1_si :std_ulogic_vector(0 to 12) ;--SCAN + ------------------- + signal ex4_sp :std_ulogic ; + signal ex4_unf_m1_co12 :std_ulogic ; + signal ex4_unf_p0_co12 :std_ulogic ; + signal ex4_ovf_m1_co12 :std_ulogic ; + signal ex4_ovf_p0_co12 :std_ulogic ; + signal ex4_ovf_p1_co12 :std_ulogic ; + signal ex4_ovf_m1 :std_ulogic ; + signal ex4_ovf_p0 :std_ulogic ; + signal ex4_ovf_p1 :std_ulogic ; + signal ex4_unf_m1 :std_ulogic ; + signal ex4_unf_p0 :std_ulogic ; + + + signal ex4_i_exp :std_ulogic_vector(1 to 13) ; + signal ex4_ue1oe1_k :std_ulogic_vector(3 to 7) ; + signal ex4_lzasub_sum :std_ulogic_vector(1 to 13) ; + signal ex4_lzasub_car :std_ulogic_vector(1 to 12) ; + signal ex4_lzasub_p :std_ulogic_vector(1 to 12) ; + signal ex4_lzasub_t :std_ulogic_vector(2 to 12) ; + signal ex4_lzasub_g :std_ulogic_vector(2 to 12) ; + signal ex4_lzasub_m1 :std_ulogic_vector(1 to 13) ; + signal ex4_lzasub_p0 :std_ulogic_vector(1 to 13) ; + signal ex4_lzasub_p1 :std_ulogic_vector(1 to 13) ; + signal ex4_lzasub_c0 :std_ulogic_vector(2 to 11) ; + signal ex4_lzasub_c1 :std_ulogic_vector(2 to 11) ; + signal ex4_lzasub_s0 :std_ulogic_vector(1 to 11) ; + signal ex4_lzasub_s1 :std_ulogic_vector(1 to 11) ; + signal ex4_ovf_sum :std_ulogic_vector(1 to 13) ; + signal ex4_ovf_car :std_ulogic_vector(1 to 12) ; + signal ex4_ovf_g :std_ulogic_vector(2 to 12) ; + signal ex4_ovf_t :std_ulogic_vector(2 to 12) ; + signal ex4_ovf_p :std_ulogic_vector(1 to 1) ; + signal ex4_unf_sum :std_ulogic_vector(1 to 13) ; + signal ex4_unf_car :std_ulogic_vector(1 to 12) ; + signal ex4_unf_g :std_ulogic_vector(2 to 12) ; + signal ex4_unf_t :std_ulogic_vector(2 to 12) ; + signal ex4_unf_p :std_ulogic_vector(1 to 1) ; + signal ex4_unf_ci0_02t11 :std_ulogic; + signal ex4_unf_ci1_02t11 :std_ulogic; + signal ex4_expo_p0 :std_ulogic_vector(1 to 13) ; + signal ex4_expo_p1 :std_ulogic_vector(1 to 13) ; + signal ex5_expo_p0 :std_ulogic_vector(1 to 13) ; + signal ex5_expo_p1 :std_ulogic_vector(1 to 13) ; + signal ex5_ue1oe1_k :std_ulogic_vector(3 to 7) ; + signal ex5_ue1oe1_p0_p :std_ulogic_vector(3 to 7) ; + signal ex5_ue1oe1_p0_t :std_ulogic_vector(4 to 6) ; + signal ex5_ue1oe1_p0_g :std_ulogic_vector(4 to 7) ; + signal ex5_ue1oe1_p0_c :std_ulogic_vector(4 to 7) ; + signal ex5_ue1oe1_p1_p :std_ulogic_vector(3 to 7) ; + signal ex5_ue1oe1_p1_t :std_ulogic_vector(4 to 6) ; + signal ex5_ue1oe1_p1_g :std_ulogic_vector(4 to 7) ; + signal ex5_ue1oe1_p1_c :std_ulogic_vector(4 to 7) ; + signal ex4_lzasub_m1_c12 :std_ulogic ; + signal ex4_lzasub_p0_c12 :std_ulogic ; + signal ex4_lzasub_p1_c12 :std_ulogic ; + signal ex4_may_ovf :std_ulogic ; + signal ex4_lza_amt_b :std_ulogic_vector(0 to 7) ; + signal ex4_lza_amt :std_ulogic_vector(0 to 7) ; + signal ex3_iexp :std_ulogic_vector(1 to 13) ; + signal ex3_sp :std_ulogic ; + signal ex3_may_ovf :std_ulogic ; + signal ex4_unf_c2_m1 :std_ulogic; + signal ex4_unf_c2_p0 :std_ulogic; + signal ex4_c2_m1 :std_ulogic; + signal ex4_c2_p0 :std_ulogic; + signal ex4_c2_p1 :std_ulogic; + signal ex5_ue1oe1_p0_g2_b :std_ulogic_vector(4 to 7); + signal ex5_ue1oe1_p0_t2_b :std_ulogic_vector(4 to 5); + signal ex5_ue1oe1_p1_g2_b :std_ulogic_vector(4 to 7); + signal ex5_ue1oe1_p1_t2_b :std_ulogic_vector(4 to 5); + signal ex4_unf_g2_02t03 :std_ulogic; + signal ex4_unf_g2_04t05 :std_ulogic; + signal ex4_unf_g2_06t07 :std_ulogic; + signal ex4_unf_g2_08t09 :std_ulogic; + signal ex4_unf_g2_10t11 :std_ulogic; + signal ex4_unf_ci0_g2 :std_ulogic; + signal ex4_unf_ci1_g2 :std_ulogic; + signal ex4_unf_t2_02t03 :std_ulogic; + signal ex4_unf_t2_04t05 :std_ulogic; + signal ex4_unf_t2_06t07 :std_ulogic; + signal ex4_unf_t2_08t09 :std_ulogic; + signal ex4_unf_t2_10t11 :std_ulogic; + signal ex4_unf_g4_02t05 :std_ulogic; + signal ex4_unf_g4_06t09 :std_ulogic; + signal ex4_unf_ci0_g4 :std_ulogic; + signal ex4_unf_ci1_g4 :std_ulogic; + signal ex4_unf_t4_02t05 :std_ulogic; + signal ex4_unf_t4_06t09 :std_ulogic; + signal ex4_unf_g8_02t09 :std_ulogic; + signal ex4_unf_ci0_g8 :std_ulogic; + signal ex4_unf_ci1_g8 :std_ulogic; + signal ex4_unf_t8_02t09 :std_ulogic; + + signal ex4_ovf_ci0_02t11 :std_ulogic; + signal ex4_ovf_ci1_02t11 :std_ulogic; + + signal ex4_ovf_g2_02t03 :std_ulogic; + signal ex4_ovf_g2_04t05 :std_ulogic; + signal ex4_ovf_g2_06t07 :std_ulogic; + signal ex4_ovf_g2_08t09 :std_ulogic; + signal ex4_ovf_g2_ci0 :std_ulogic; + signal ex4_ovf_g2_ci1 :std_ulogic; + signal ex4_ovf_t2_02t03 :std_ulogic; + signal ex4_ovf_t2_04t05 :std_ulogic; + signal ex4_ovf_t2_06t07 :std_ulogic; + signal ex4_ovf_t2_08t09 :std_ulogic; + signal ex4_ovf_g4_02t05 :std_ulogic; + signal ex4_ovf_g4_06t09 :std_ulogic; + signal ex4_ovf_g4_ci0 :std_ulogic; + signal ex4_ovf_g4_ci1 :std_ulogic; + signal ex4_ovf_t4_02t05 :std_ulogic; + signal ex4_ovf_t4_06t09 :std_ulogic; + signal ex4_ovf_g8_02t09 :std_ulogic; + signal ex4_ovf_g8_ci0 :std_ulogic; + signal ex4_ovf_g8_ci1 :std_ulogic; + signal ex4_ovf_t8_02t09 :std_ulogic; + + signal ex4_lzasub_gg02 :std_ulogic_vector(2 to 11); + signal ex4_lzasub_gt02 :std_ulogic_vector(2 to 11); + signal ex4_lzasub_gg04 :std_ulogic_vector(2 to 11); + signal ex4_lzasub_gt04 :std_ulogic_vector(2 to 11); + signal ex4_lzasub_gg08 :std_ulogic_vector(2 to 11); + signal ex4_lzasub_gt08 :std_ulogic_vector(2 to 11); + signal ex4_sh_rgt_en_b :std_ulogic; + + signal ex3_may_ov_usual :std_ulogic; + + + + signal ex4_ovf_calc :std_ulogic; + signal ex4_ovf_if_calc :std_ulogic; + signal ex4_unf_calc :std_ulogic; + signal ex4_unf_tbl :std_ulogic; + signal ex4_unf_tbl_spec_e :std_ulogic; + signal ex4_ov_en :std_ulogic; + signal ex4_ov_en_oe0 :std_ulogic; + signal ex4_sel_ov_spec :std_ulogic; + signal ex4_unf_en_nedge :std_ulogic; + signal ex4_unf_ue0_nestsp :std_ulogic; + signal ex4_sel_k_part_f :std_ulogic; + signal ex4_sel_k_part_e :std_ulogic; + signal ex5_ovf_calc :std_ulogic; + signal ex5_ovf_if_calc :std_ulogic; + signal ex5_unf_calc :std_ulogic; + signal ex5_unf_tbl :std_ulogic; + signal ex5_unf_tbl_b :std_ulogic; + signal ex5_unf_tbl_spec_e :std_ulogic; + signal ex5_ov_en :std_ulogic; + signal ex5_ov_en_oe0 :std_ulogic; + signal ex5_sel_ov_spec :std_ulogic; + signal ex5_unf_en_nedge :std_ulogic; + signal ex5_unf_ue0_nestsp :std_ulogic; + signal ex5_sel_k_part_f :std_ulogic; + signal ex5_sel_ov_spec_b :std_ulogic; + signal ex5_ovf_b :std_ulogic; + signal ex5_ovf_if_b :std_ulogic; + signal ex5_ovf_oe0_b :std_ulogic; + signal ex5_ovf_if_oe0_b :std_ulogic; + signal ex5_unf_b :std_ulogic; + signal ex5_unf_ue0_b :std_ulogic; + signal ex5_sel_k_part_f_b :std_ulogic; + signal ex5_unf_tbl_spec_e_b :std_ulogic; + signal ex4_sel_est :std_ulogic; + signal ex4_est_sp :std_ulogic; + +signal ex4_expo_p0_0_b, ex4_expo_p0_1_b, ex4_expo_p1_0_b, ex4_expo_p1_1_b :std_ulogic_vector(1 to 13) ; +signal ex4_ovf_calc_0_b, ex4_ovf_calc_1_b, ex4_ovf_if_calc_0_b, ex4_ovf_if_calc_1_b, ex4_unf_calc_0_b, ex4_unf_calc_1_b :std_ulogic ; + signal ex5_d1clk, ex5_d2clk :std_ulogic ; + signal ex5_lclk :clk_logic; + signal unused :std_ulogic ; + +-- synopsys translate_off + +-- synopsys translate_on + + +begin + +unused <= + or_reduce( ex4_expo_p0(1 to 13) ) or + or_reduce( ex4_expo_p1(1 to 13) ) or + ex4_ovf_calc or + ex4_ovf_if_calc or + ex4_unf_calc ; + +--//############################################ +--//# pervasive +--//############################################ + + thold_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => thold_1, + q(0) => thold_0 ); + + sg_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => sg_1 , + q(0) => sg_0 ); + + + lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map ( + clkoff_b => clkoff_b, + thold => thold_0, + sg => sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => thold_0_b ); + + ex5_lcb : tri_lcbnd generic map (expand_type => expand_type) port map( + delay_lclkr => delay_lclkr(5) , + mpw1_b => mpw1_b(5) , + mpw2_b => mpw2_b(1) , + forcee => forcee, + nclk => nclk , + vd => vdd , + gd => gnd , + act => ex4_act , + sg => sg_0 , + thold_b => thold_0_b , + d1clk => ex5_d1clk , + d2clk => ex5_d2clk , + lclk => ex5_lclk ); + + + +--//############################################ +--//# ACT LATCHES +--//############################################ + + ex2_act <= not ex2_act_b; + + act_lat: tri_rlmreg_p generic map (width=> 5, expand_type => expand_type, needs_sreset => 0) port map ( + forcee => forcee,-- tidn, + delay_lclkr => delay_lclkr(4) ,-- tidn, + mpw1_b => mpw1_b(4) ,-- tidn, + mpw2_b => mpw2_b(0) ,-- tidn, + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => fpu_enable, + scout => act_so , + scin => act_si , + ------------------- + din(0) => act_spare_unused(0), + din(1) => act_spare_unused(1), + din(2) => ex2_act, + din(3) => ex3_act, + din(4) => act_spare_unused(2), + ------------------- + dout(0) => act_spare_unused(0), + dout(1) => act_spare_unused(1), + dout(2) => ex3_act, + dout(3) => ex4_act, + dout(4) => act_spare_unused(2) ); + + +--//############################################## +--//# EX3 logic +--//############################################## + + ex3_iexp(1 to 13) <= + ( (1 to 13=> not f_pic_ex3_sel_est) and f_eie_ex3_iexp(1 to 13) ) or + ( (1 to 13=> f_pic_ex3_sel_est) and f_tbe_ex3_expo(1 to 13) ) ; + + ex3_sp <= not f_pic_ex3_sp_b; + + + + + ex3_may_ovf <= + ( ex3_may_ov_usual and not f_pic_ex3_sel_est) or + ( f_tbe_ex3_may_ov and f_pic_ex3_sel_est); + + ex3_may_ov_usual <= + (not f_eie_ex3_iexp(1) and f_eie_ex3_iexp(2) ) or + (not f_eie_ex3_iexp(1) and f_eie_ex3_iexp(3) and f_eie_ex3_iexp(4) ) or + (not f_eie_ex3_iexp(1) and f_eie_ex3_iexp(3) and f_eie_ex3_iexp(5) ) or + (not f_eie_ex3_iexp(1) and f_eie_ex3_iexp(3) and f_eie_ex3_iexp(6) ) or + (not f_eie_ex3_iexp(1) and f_eie_ex3_iexp(3) and f_eie_ex3_iexp(7) ) or + (not f_eie_ex3_iexp(1) and f_eie_ex3_iexp(3) and f_eie_ex3_iexp(8) and f_eie_ex3_iexp(9) ); + +--//############################################## +--//# EX4 latch inputs from ex3 +--//############################################## + + ex4_iexp_lat: tri_rlmreg_p generic map (width=> 16, expand_type => expand_type, needs_sreset => 0) port map ( + forcee => forcee,-- tidn, + delay_lclkr => delay_lclkr(4) ,-- tidn, + mpw1_b => mpw1_b(4) ,-- tidn, + mpw2_b => mpw2_b(0) ,-- tidn, + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => ex3_act, + scout => ex4_iexp_so , + scin => ex4_iexp_si , + ------------------- + din(0) => ex3_sp , + din(1 to 13) => ex3_iexp(1 to 13) , + din(14) => ex3_may_ovf , + din(15) => f_pic_ex3_sel_est, + ------------------- + dout(0) => ex4_sp ,--LAT-- + dout(1 to 13) => ex4_i_exp(1 to 13) ,--LAT-- + dout(14) => ex4_may_ovf ,--LAT-- + dout(15) => ex4_sel_est );--LAT-- + + f_eov_ex4_may_ovf <= ex4_may_ovf; + +--//############################################## +--//# EX4 logic +--//############################################## + + --//#------------------------------------------- + --//# ue1oe1 constant + --//#------------------------------------------- + -- need to know constant (sp/dp +/-192 +/-1536 ) + -- +1536 11000 UNF + -- -1536 01000 OVF + -- +192 00011 UNF + -- -192 11101 OVF + + ex4_ue1oe1_k(3) <= (not ex4_may_ovf and not ex4_sp) or + ( ex4_may_ovf and ex4_sp) ; + + ex4_ue1oe1_k(4) <= ( not ex4_sp) or + ( ex4_may_ovf and ex4_sp) ; + + ex4_ue1oe1_k(5) <= ( ex4_may_ovf and ex4_sp) ; + + ex4_ue1oe1_k(6) <= (not ex4_may_ovf and ex4_sp) ; + ex4_ue1oe1_k(7) <= ( ex4_sp) ; + + + + -- sort of 3:2 compresor to make room for extra carry for +1 +2; + + ex4_lza_amt_b(0 to 7) <= not f_lza_ex4_lza_amt_eov(0 to 7); + ex4_lza_amt (0 to 7) <= f_lza_ex4_lza_amt_eov(0 to 7); + ex4_sh_rgt_en_b <= not f_lza_ex4_sh_rgt_en_eov; + + ex4_lzasub_sum( 1) <= ex4_sh_rgt_en_b xor ex4_i_exp( 1); + ex4_lzasub_sum( 2) <= ex4_sh_rgt_en_b xor ex4_i_exp( 2); + ex4_lzasub_sum( 3) <= ex4_sh_rgt_en_b xor ex4_i_exp( 3); + ex4_lzasub_sum( 4) <= ex4_sh_rgt_en_b xor ex4_i_exp( 4); + ex4_lzasub_sum( 5) <= ex4_sh_rgt_en_b xor ex4_i_exp( 5); + ex4_lzasub_sum( 6) <= ex4_lza_amt_b(0) xor ex4_i_exp( 6); + ex4_lzasub_sum( 7) <= ex4_lza_amt_b(1) xor ex4_i_exp( 7); + ex4_lzasub_sum( 8) <= ex4_lza_amt_b(2) xor ex4_i_exp( 8); + ex4_lzasub_sum( 9) <= ex4_lza_amt_b(3) xor ex4_i_exp( 9); + ex4_lzasub_sum(10) <= ex4_lza_amt_b(4) xor ex4_i_exp(10); + ex4_lzasub_sum(11) <= ex4_lza_amt_b(5) xor ex4_i_exp(11); + ex4_lzasub_sum(12) <= ex4_lza_amt_b(6) xor ex4_i_exp(12); + ex4_lzasub_sum(13) <= not( ex4_lza_amt_b(7) xor ex4_i_exp(13) );--!!!!!!!! +1 for negation + + ex4_lzasub_car( 1) <= ex4_sh_rgt_en_b and ex4_i_exp( 2); + ex4_lzasub_car( 2) <= ex4_sh_rgt_en_b and ex4_i_exp( 3); + ex4_lzasub_car( 3) <= ex4_sh_rgt_en_b and ex4_i_exp( 4); + ex4_lzasub_car( 4) <= ex4_sh_rgt_en_b and ex4_i_exp( 5); + ex4_lzasub_car( 5) <= ex4_lza_amt_b(0) and ex4_i_exp( 6); + ex4_lzasub_car( 6) <= ex4_lza_amt_b(1) and ex4_i_exp( 7); + ex4_lzasub_car( 7) <= ex4_lza_amt_b(2) and ex4_i_exp( 8); + ex4_lzasub_car( 8) <= ex4_lza_amt_b(3) and ex4_i_exp( 9); + ex4_lzasub_car( 9) <= ex4_lza_amt_b(4) and ex4_i_exp(10); + ex4_lzasub_car(10) <= ex4_lza_amt_b(5) and ex4_i_exp(11); + ex4_lzasub_car(11) <= ex4_lza_amt_b(6) and ex4_i_exp(12); + ex4_lzasub_car(12) <= ex4_lza_amt_b(7) or ex4_i_exp(13);--!!!!!! +1 for negation + + ex4_lzasub_p(1 to 12) <= ex4_lzasub_car(1 to 12) xor ex4_lzasub_sum(1 to 12); + ex4_lzasub_t(2 to 12) <= ex4_lzasub_car(2 to 12) or ex4_lzasub_sum(2 to 12); + ex4_lzasub_g(2 to 12) <= ex4_lzasub_car(2 to 12) and ex4_lzasub_sum(2 to 12); + + + --//##------------------------------ + --//##-- add the 2 lower bits for the different conditions (+0,+1.+2) + --//##------------------------------ + + ex4_lzasub_m1_c12 <= ex4_lzasub_g(12); + ex4_lzasub_p0_c12 <= ex4_lzasub_g(12) or (ex4_lzasub_t(12) and ex4_lzasub_sum(13) ); + ex4_lzasub_p1_c12 <= ex4_lzasub_t(12); + + ex4_lzasub_m1(13) <= ex4_lzasub_sum(13); --LSB is done +0 + ex4_lzasub_p0(13) <= not ex4_lzasub_sum(13); --LSB is done +1 + ex4_lzasub_p1(13) <= ex4_lzasub_sum(13); --LSB is done +2 + + ex4_lzasub_m1(12) <= ex4_lzasub_p(12); -- +0 + ex4_lzasub_p0(12) <= ex4_lzasub_p(12) xor ex4_lzasub_sum(13); -- +1 + ex4_lzasub_p1(12) <= not ex4_lzasub_p(12); -- +2 + + + --//##----------------------------------- + --//## the conditional carry chain (+ci,-ci) + --//##----------------------------------- + + ex4_lzasub_gg02(11) <= ex4_lzasub_g(11) ; + ex4_lzasub_gg02(10) <= ex4_lzasub_g(10) or ( ex4_lzasub_t(10) and ex4_lzasub_g(11) );--final + ex4_lzasub_gg02( 9) <= ex4_lzasub_g( 9) or ( ex4_lzasub_t( 9) and ex4_lzasub_g(10) ); + ex4_lzasub_gg02( 8) <= ex4_lzasub_g( 8) or ( ex4_lzasub_t( 8) and ex4_lzasub_g( 9) ); + ex4_lzasub_gg02( 7) <= ex4_lzasub_g( 7) or ( ex4_lzasub_t( 7) and ex4_lzasub_g( 8) ); + ex4_lzasub_gg02( 6) <= ex4_lzasub_g( 6) or ( ex4_lzasub_t( 6) and ex4_lzasub_g( 7) ); + ex4_lzasub_gg02( 5) <= ex4_lzasub_g( 5) or ( ex4_lzasub_t( 5) and ex4_lzasub_g( 6) ); + ex4_lzasub_gg02( 4) <= ex4_lzasub_g( 4) or ( ex4_lzasub_t( 4) and ex4_lzasub_g( 5) ); + ex4_lzasub_gg02( 3) <= ex4_lzasub_g( 3) or ( ex4_lzasub_t( 3) and ex4_lzasub_g( 4) ); + ex4_lzasub_gg02( 2) <= ex4_lzasub_g( 2) or ( ex4_lzasub_t( 2) and ex4_lzasub_g( 3) ); + + ex4_lzasub_gt02(11) <= ex4_lzasub_t(11) ; + ex4_lzasub_gt02(10) <= ex4_lzasub_g(10) or ( ex4_lzasub_t(10) and ex4_lzasub_t(11) );--final + ex4_lzasub_gt02( 9) <= ( ex4_lzasub_t( 9) and ex4_lzasub_t(10) ); + ex4_lzasub_gt02( 8) <= ( ex4_lzasub_t( 8) and ex4_lzasub_t( 9) ); + ex4_lzasub_gt02( 7) <= ( ex4_lzasub_t( 7) and ex4_lzasub_t( 8) ); + ex4_lzasub_gt02( 6) <= ( ex4_lzasub_t( 6) and ex4_lzasub_t( 7) ); + ex4_lzasub_gt02( 5) <= ( ex4_lzasub_t( 5) and ex4_lzasub_t( 6) ); + ex4_lzasub_gt02( 4) <= ( ex4_lzasub_t( 4) and ex4_lzasub_t( 5) ); + ex4_lzasub_gt02( 3) <= ( ex4_lzasub_t( 3) and ex4_lzasub_t( 4) ); + ex4_lzasub_gt02( 2) <= ( ex4_lzasub_t( 2) and ex4_lzasub_t( 3) ); + + ex4_lzasub_gg04(11) <= ex4_lzasub_gg02(11) ; + ex4_lzasub_gg04(10) <= ex4_lzasub_gg02(10) ; + ex4_lzasub_gg04( 9) <= ex4_lzasub_gg02( 9) or ( ex4_lzasub_gt02( 9) and ex4_lzasub_gg02(11) );--final + ex4_lzasub_gg04( 8) <= ex4_lzasub_gg02( 8) or ( ex4_lzasub_gt02( 8) and ex4_lzasub_gg02(10) );--final + ex4_lzasub_gg04( 7) <= ex4_lzasub_gg02( 7) or ( ex4_lzasub_gt02( 7) and ex4_lzasub_gg02( 9) ); + ex4_lzasub_gg04( 6) <= ex4_lzasub_gg02( 6) or ( ex4_lzasub_gt02( 6) and ex4_lzasub_gg02( 8) ); + ex4_lzasub_gg04( 5) <= ex4_lzasub_gg02( 5) or ( ex4_lzasub_gt02( 5) and ex4_lzasub_gg02( 7) ); + ex4_lzasub_gg04( 4) <= ex4_lzasub_gg02( 4) or ( ex4_lzasub_gt02( 4) and ex4_lzasub_gg02( 6) ); + ex4_lzasub_gg04( 3) <= ex4_lzasub_gg02( 3) or ( ex4_lzasub_gt02( 3) and ex4_lzasub_gg02( 5) ); + ex4_lzasub_gg04( 2) <= ex4_lzasub_gg02( 2) or ( ex4_lzasub_gt02( 2) and ex4_lzasub_gg02( 4) ); + + ex4_lzasub_gt04(11) <= ex4_lzasub_gt02(11) ; + ex4_lzasub_gt04(10) <= ex4_lzasub_gt02(10) ; + ex4_lzasub_gt04( 9) <= ex4_lzasub_gg02( 9) or ( ex4_lzasub_gt02( 9) and ex4_lzasub_gt02(11) );--final + ex4_lzasub_gt04( 8) <= ex4_lzasub_gg02( 8) or ( ex4_lzasub_gt02( 8) and ex4_lzasub_gt02(10) );--final + ex4_lzasub_gt04( 7) <= ( ex4_lzasub_gt02( 7) and ex4_lzasub_gt02( 9) ); + ex4_lzasub_gt04( 6) <= ( ex4_lzasub_gt02( 6) and ex4_lzasub_gt02( 8) ); + ex4_lzasub_gt04( 5) <= ( ex4_lzasub_gt02( 5) and ex4_lzasub_gt02( 7) ); + ex4_lzasub_gt04( 4) <= ( ex4_lzasub_gt02( 4) and ex4_lzasub_gt02( 6) ); + ex4_lzasub_gt04( 3) <= ( ex4_lzasub_gt02( 3) and ex4_lzasub_gt02( 5) ); + ex4_lzasub_gt04( 2) <= ( ex4_lzasub_gt02( 2) and ex4_lzasub_gt02( 4) ); + + + ex4_lzasub_gg08(11) <= ex4_lzasub_gg04(11) ; + ex4_lzasub_gg08(10) <= ex4_lzasub_gg04(10) ; + ex4_lzasub_gg08( 9) <= ex4_lzasub_gg04( 9) ; + ex4_lzasub_gg08( 8) <= ex4_lzasub_gg04( 8) ; + ex4_lzasub_gg08( 7) <= ex4_lzasub_gg04( 7) or ( ex4_lzasub_gt04( 7) and ex4_lzasub_gg04(11) );--final + ex4_lzasub_gg08( 6) <= ex4_lzasub_gg04( 6) or ( ex4_lzasub_gt04( 6) and ex4_lzasub_gg04(10) );--final + ex4_lzasub_gg08( 5) <= ex4_lzasub_gg04( 5) or ( ex4_lzasub_gt04( 5) and ex4_lzasub_gg04( 9) );--final + ex4_lzasub_gg08( 4) <= ex4_lzasub_gg04( 4) or ( ex4_lzasub_gt04( 4) and ex4_lzasub_gg04( 8) );--final + ex4_lzasub_gg08( 3) <= ex4_lzasub_gg04( 3) or ( ex4_lzasub_gt04( 3) and ex4_lzasub_gg04( 7) ); + ex4_lzasub_gg08( 2) <= ex4_lzasub_gg04( 2) or ( ex4_lzasub_gt04( 2) and ex4_lzasub_gg04( 6) ); + + ex4_lzasub_gt08(11) <= ex4_lzasub_gt04(11) ; + ex4_lzasub_gt08(10) <= ex4_lzasub_gt04(10) ; + ex4_lzasub_gt08( 9) <= ex4_lzasub_gt04( 9) ; + ex4_lzasub_gt08( 8) <= ex4_lzasub_gt04( 8) ; + ex4_lzasub_gt08( 7) <= ex4_lzasub_gg04( 7) or ( ex4_lzasub_gt04( 7) and ex4_lzasub_gt04(11) );--final + ex4_lzasub_gt08( 6) <= ex4_lzasub_gg04( 6) or ( ex4_lzasub_gt04( 6) and ex4_lzasub_gt04(10) );--final + ex4_lzasub_gt08( 5) <= ex4_lzasub_gg04( 5) or ( ex4_lzasub_gt04( 5) and ex4_lzasub_gt04( 9) );--final + ex4_lzasub_gt08( 4) <= ex4_lzasub_gg04( 4) or ( ex4_lzasub_gt04( 4) and ex4_lzasub_gt04( 8) );--final + ex4_lzasub_gt08( 3) <= ( ex4_lzasub_gt04( 3) and ex4_lzasub_gt04( 7) ); + ex4_lzasub_gt08( 2) <= ( ex4_lzasub_gt04( 2) and ex4_lzasub_gt04( 6) ); + + + ex4_lzasub_c0(11) <= ex4_lzasub_gg08(11) ; + ex4_lzasub_c0(10) <= ex4_lzasub_gg08(10) ; + ex4_lzasub_c0( 9) <= ex4_lzasub_gg08( 9) ; + ex4_lzasub_c0( 8) <= ex4_lzasub_gg08( 8) ; + ex4_lzasub_c0( 7) <= ex4_lzasub_gg08( 7) ; + ex4_lzasub_c0( 6) <= ex4_lzasub_gg08( 6) ; + ex4_lzasub_c0( 5) <= ex4_lzasub_gg08( 5) ; + ex4_lzasub_c0( 4) <= ex4_lzasub_gg08( 4) ; + ex4_lzasub_c0( 3) <= ex4_lzasub_gg08( 3) or ( ex4_lzasub_gt08( 3) and ex4_lzasub_gg08(11) ); --final + ex4_lzasub_c0( 2) <= ex4_lzasub_gg08( 2) or ( ex4_lzasub_gt08( 2) and ex4_lzasub_gg08(10) ); --final + + ex4_lzasub_c1(11) <= ex4_lzasub_gt08(11) ; + ex4_lzasub_c1(10) <= ex4_lzasub_gt08(10) ; + ex4_lzasub_c1( 9) <= ex4_lzasub_gt08( 9) ; + ex4_lzasub_c1( 8) <= ex4_lzasub_gt08( 8) ; + ex4_lzasub_c1( 7) <= ex4_lzasub_gt08( 7) ; + ex4_lzasub_c1( 6) <= ex4_lzasub_gt08( 6) ; + ex4_lzasub_c1( 5) <= ex4_lzasub_gt08( 5) ; + ex4_lzasub_c1( 4) <= ex4_lzasub_gt08( 4) ; + ex4_lzasub_c1( 3) <= ex4_lzasub_gg08( 3) or ( ex4_lzasub_gt08( 3) and ex4_lzasub_gt08(11) ); --final + ex4_lzasub_c1( 2) <= ex4_lzasub_gg08( 2) or ( ex4_lzasub_gt08( 2) and ex4_lzasub_gt08(10) ); --final + + + + + + ex4_lzasub_s0(1 to 11) <= ex4_lzasub_p(1 to 11) xor (ex4_lzasub_c0(2 to 11) & tidn) ; + ex4_lzasub_s1(1 to 11) <= ex4_lzasub_p(1 to 11) xor (ex4_lzasub_c1(2 to 11) & tiup) ; + + ex4_lzasub_m1(1 to 11) <= + (ex4_lzasub_s0(1 to 11) and (1 to 11 => not ex4_lzasub_m1_c12) ) or + (ex4_lzasub_s1(1 to 11) and (1 to 11 => ex4_lzasub_m1_c12) ); + + ex4_lzasub_p0(1 to 11) <= + (ex4_lzasub_s0(1 to 11) and (1 to 11 => not ex4_lzasub_p0_c12) ) or + (ex4_lzasub_s1(1 to 11) and (1 to 11 => ex4_lzasub_p0_c12) ); + + ex4_lzasub_p1(1 to 11) <= + (ex4_lzasub_s0(1 to 11) and (1 to 11 => not ex4_lzasub_p1_c12) ) or + (ex4_lzasub_s1(1 to 11) and (1 to 11 => ex4_lzasub_p1_c12) ); + + --//#------------------------------------------- + --//# determine overflow (expo bias = 1023, with signed bit) + --//#------------------------------------------- + -- + -- dp overflow: ge 2047 = 2047 ge 2047 + -- sp overflow: ge 255 + 896 = 1151 ge 1151 + -- + -- using expo_m1 as the base: + -- m1 p0 p1 + -- dp ovf: ge 2047 ge 2046 ge 2045 + -- sp ovf: ge 1151 ge 1150 ge 1149 + -- + -- could just do the subtract, then decode the result. (triple compound add becomes critical). + -- doingg compare before the add (faster) + -- + -- 2047 0_0111_1111_1111 + -- 1151 0_0100_0111_1111 + -- + -- 0 0000 0000 1111 + -- 1 2345 6789 0123 + -- + --------------------------------- + -- 0_01dd_d111_1111 (minimum) + -- 1_10ss_s000_0000 !(minimum) + -- 1_10ss_s000_0001 -(minimum) + -- 1_10ss_s000_0010 BOUNDRY +1 for -lza = !lza+1 + -- 1_11 add the lza sign xtd + ---------------------------------- + --- 1_01ss_s000_0100 + ---------------------------------- + -- overflow if (iexp-lza) >= 2047 + -- overflow if (iexp-lza) - 2047 >= 0 + -- POSITIVE result means overflow. + -- NEGATIVE result means no overflow. + + + ex4_ovf_sum( 1) <= ex4_sh_rgt_en_b xor not ex4_i_exp( 1); -- 1 !R [1] + ex4_ovf_sum( 2) <= ex4_sh_rgt_en_b xor not ex4_i_exp( 2); -- 1 !R [2] + ex4_ovf_sum( 3) <= ex4_sh_rgt_en_b xor ex4_i_exp( 3); -- 0 !R [3] + ex4_ovf_sum( 4) <= ex4_sh_rgt_en_b xor ex4_i_exp( 4) xor ex4_sp; -- s !R [4] + ex4_ovf_sum( 5) <= ex4_sh_rgt_en_b xor ex4_i_exp( 5) xor ex4_sp; -- s !R [5] + ex4_ovf_sum( 6) <= not ex4_lza_amt(0) xor ex4_i_exp( 6) xor ex4_sp; -- s ![0] [6] + ex4_ovf_sum( 7) <= not ex4_lza_amt(1) xor ex4_i_exp( 7); -- 0 ![1] [7] + ex4_ovf_sum( 8) <= not ex4_lza_amt(2) xor ex4_i_exp( 8); -- 0 ![2] [8] + ex4_ovf_sum( 9) <= not ex4_lza_amt(3) xor ex4_i_exp( 9); -- 0 ![3] [9] + ex4_ovf_sum(10) <= not ex4_lza_amt(4) xor ex4_i_exp(10); -- 0 ![4] [10] + ex4_ovf_sum(11) <= not ex4_lza_amt(5) xor ex4_i_exp(11); -- 0 ![5] [11] + ex4_ovf_sum(12) <= not ex4_lza_amt(6) xor not ex4_i_exp(12); -- 1 ![6] [12] + ex4_ovf_sum(13) <= not ex4_lza_amt(7) xor ex4_i_exp(13); -- 0 ![7] [13] + + ex4_ovf_car( 1) <= ex4_sh_rgt_en_b or ex4_i_exp( 2); -- 1 !R [2] + ex4_ovf_car( 2) <= ex4_sh_rgt_en_b and ex4_i_exp( 3); -- 0 !R [3] + + ex4_ovf_car( 3) <= ( ex4_sp and ex4_i_exp( 4) ) or -- s !R [4] + ( ex4_sh_rgt_en_b and ex4_i_exp( 4) ) or + ( ex4_sh_rgt_en_b and ex4_sp ) ; + + ex4_ovf_car( 4) <= ( ex4_sp and ex4_i_exp( 5) ) or -- s !R [5] + ( ex4_sh_rgt_en_b and ex4_i_exp( 5) ) or + ( ex4_sh_rgt_en_b and ex4_sp ) ; + + ex4_ovf_car( 5) <= (not ex4_lza_amt(0) and ex4_i_exp( 6) ) or -- s ![0] [6] + (not ex4_lza_amt(0) and ex4_sp ) or + ( ex4_sp and ex4_i_exp( 6) ) ; + ex4_ovf_car( 6) <= not ex4_lza_amt(1) and ex4_i_exp( 7); -- 0 ![1] [7] + ex4_ovf_car( 7) <= not ex4_lza_amt(2) and ex4_i_exp( 8); -- 0 ![2] [8] + ex4_ovf_car( 8) <= not ex4_lza_amt(3) and ex4_i_exp( 9); -- 0 ![3] [9] + ex4_ovf_car( 9) <= not ex4_lza_amt(4) and ex4_i_exp(10); -- 0 ![4] [10] + ex4_ovf_car(10) <= not ex4_lza_amt(5) and ex4_i_exp(11); -- 0 ![5] [11] + ex4_ovf_car(11) <= not ex4_lza_amt(6) or ex4_i_exp(12); -- 1 ![6] [12] + ex4_ovf_car(12) <= not ex4_lza_amt(7) and ex4_i_exp(13); -- 0 ![7] [13] + + + + ex4_ovf_g(2 to 12) <= ex4_ovf_car(2 to 12) and ex4_ovf_sum(2 to 12); + ex4_ovf_t(2 to 12) <= ex4_ovf_car(2 to 12) or ex4_ovf_sum(2 to 12); + ex4_ovf_p(1) <= ex4_ovf_car(1) xor ex4_ovf_sum(1) ; + + -- lower bits (compute 3 possible combinations) + + ex4_ovf_m1_co12 <= ex4_ovf_g(12); + ex4_ovf_p0_co12 <= ex4_ovf_g(12) or (ex4_ovf_t(12) and ex4_ovf_sum(13) ); + ex4_ovf_p1_co12 <= ex4_ovf_t(12); + + -- upper bits (compute 2 possible combinations) + + + ex4_ovf_g2_02t03 <= ex4_ovf_g( 2) or (ex4_ovf_t( 2) and ex4_ovf_g( 3) ); + ex4_ovf_g2_04t05 <= ex4_ovf_g( 4) or (ex4_ovf_t( 4) and ex4_ovf_g( 5) ); + ex4_ovf_g2_06t07 <= ex4_ovf_g( 6) or (ex4_ovf_t( 6) and ex4_ovf_g( 7) ); + ex4_ovf_g2_08t09 <= ex4_ovf_g( 8) or (ex4_ovf_t( 8) and ex4_ovf_g( 9) ); + ex4_ovf_g2_ci0 <= ex4_ovf_g(10) or (ex4_ovf_t(10) and ex4_ovf_g(11) ); + ex4_ovf_g2_ci1 <= ex4_ovf_g(10) or (ex4_ovf_t(10) and ex4_ovf_t(11) ); + + ex4_ovf_t2_02t03 <= (ex4_ovf_t( 2) and ex4_ovf_t( 3) ); + ex4_ovf_t2_04t05 <= (ex4_ovf_t( 4) and ex4_ovf_t( 5) ); + ex4_ovf_t2_06t07 <= (ex4_ovf_t( 6) and ex4_ovf_t( 7) ); + ex4_ovf_t2_08t09 <= (ex4_ovf_t( 8) and ex4_ovf_t( 9) ); + + ex4_ovf_g4_02t05 <= ex4_ovf_g2_02t03 or ( ex4_ovf_t2_02t03 and ex4_ovf_g2_04t05 ); + ex4_ovf_g4_06t09 <= ex4_ovf_g2_06t07 or ( ex4_ovf_t2_06t07 and ex4_ovf_g2_08t09 ); + ex4_ovf_g4_ci0 <= ex4_ovf_g2_ci0; + ex4_ovf_g4_ci1 <= ex4_ovf_g2_ci1; + + ex4_ovf_t4_02t05 <= ( ex4_ovf_t2_02t03 and ex4_ovf_t2_04t05 ); + ex4_ovf_t4_06t09 <= ( ex4_ovf_t2_06t07 and ex4_ovf_t2_08t09 ); + + ex4_ovf_g8_02t09 <= ex4_ovf_g4_02t05 or ( ex4_ovf_t4_02t05 and ex4_ovf_g4_06t09 ); + ex4_ovf_g8_ci0 <= ex4_ovf_g4_ci0; + ex4_ovf_g8_ci1 <= ex4_ovf_g4_ci1; + + ex4_ovf_t8_02t09 <= ( ex4_ovf_t4_02t05 and ex4_ovf_t4_06t09 ); + + + ex4_ovf_ci0_02t11 <= ex4_ovf_g8_02t09 or (ex4_ovf_t8_02t09 and ex4_ovf_g8_ci0 ); + ex4_ovf_ci1_02t11 <= ex4_ovf_g8_02t09 or (ex4_ovf_t8_02t09 and ex4_ovf_g8_ci1 ); + + + -- 13 BITS HOLDS EVERYTHING -- positive result means overflow + ex4_c2_m1 <= (ex4_ovf_ci0_02t11 or (ex4_ovf_ci1_02t11 and ex4_ovf_m1_co12) ) ; + ex4_c2_p0 <= (ex4_ovf_ci0_02t11 or (ex4_ovf_ci1_02t11 and ex4_ovf_p0_co12) ) ; + ex4_c2_p1 <= (ex4_ovf_ci0_02t11 or (ex4_ovf_ci1_02t11 and ex4_ovf_p1_co12) ) ; + + ex4_ovf_m1 <= not ex4_ovf_p(1) xor ex4_c2_m1; + ex4_ovf_p0 <= not ex4_ovf_p(1) xor ex4_c2_p0; + ex4_ovf_p1 <= not ex4_ovf_p(1) xor ex4_c2_p1; + + + --//#------------------------------------------- + --//# determine underflow (expo bias = 1023, with signed bit) + --//#------------------------------------------- + -- dp underflow: le 0 = le 0 => !ge 1 + -- sp underflow: le 0 + 896 = le 896 => !ge 897 + -- + -- if the exponent will be incremented (then there are less overflows). + -- just need for m1, p0 because underflow is determined before rounding. + -- if there is an underflow exception it cannot round up the exponent. + -- m1 p0 + -- dp unf: !ge 1 !ge 0 + -- sp unf: !ge 897 !ge 896 + -- + -- 1 0_0000_0000_0001 dp: 0_0000_0000_0001 sp: 0_0011_1000_0001 emin + -- 0 0_0000_0000_0000 1_1111_1111_1110 1_1100_0111_1110 !emin + -- 1_1111_1111_1111 1_1100_0111_1111 -emin + -- 0 0000 0000 1111 0_0000_0000_0000 1_1100_1000_0000 <= +1 -lza=!lza+1 + -- 1 2345 6789 0123 + -- + -- 897 0_0011_1000_0001 + -- 896 0_0011_1000_0000 + --------------------------------- + -- if (exp-lza) >= emin NO_UNDERFLOW + -- if (exp-lza) - emin >= 0 UNDERFLOW {sign bit = "1"} + + + ex4_unf_sum( 1) <= ex4_sh_rgt_en_b xor ex4_i_exp( 1) xor ex4_sp; -- s !R [1] + ex4_unf_sum( 2) <= ex4_sh_rgt_en_b xor ex4_i_exp( 2) xor ex4_sp; -- s !R [2] + ex4_unf_sum( 3) <= ex4_sh_rgt_en_b xor ex4_i_exp( 3) xor ex4_sp; -- s !R [3] + ex4_unf_sum( 4) <= ex4_sh_rgt_en_b xor ex4_i_exp( 4); -- 0 !R [4] + ex4_unf_sum( 5) <= ex4_sh_rgt_en_b xor ex4_i_exp( 5); -- 0 !R [5] + ex4_unf_sum( 6) <= not ex4_lza_amt(0) xor ex4_i_exp( 6) xor ex4_sp; -- s ![0] [6] + ex4_unf_sum( 7) <= not ex4_lza_amt(1) xor ex4_i_exp( 7); -- 0 ![1] [7] + ex4_unf_sum( 8) <= not ex4_lza_amt(2) xor ex4_i_exp( 8); -- 0 ![2] [8] + ex4_unf_sum( 9) <= not ex4_lza_amt(3) xor ex4_i_exp( 9); -- 0 ![3] [9] + ex4_unf_sum(10) <= not ex4_lza_amt(4) xor ex4_i_exp(10); -- 0 ![4] [10] + ex4_unf_sum(11) <= not ex4_lza_amt(5) xor ex4_i_exp(11); -- 0 ![5] [11] + ex4_unf_sum(12) <= not ex4_lza_amt(6) xor ex4_i_exp(12); -- 0 ![6] [12] + ex4_unf_sum(13) <= not ex4_lza_amt(7) xor ex4_i_exp(13); -- 0 ![7] [13] + + ex4_unf_car( 1) <= ( ex4_sp and ex4_i_exp( 2) ) or -- s !R [2] + ( ex4_sh_rgt_en_b and ex4_i_exp( 2) ) or + ( ex4_sh_rgt_en_b and ex4_sp ) ; + ex4_unf_car( 2) <= ( ex4_sp and ex4_i_exp( 3) ) or -- s !R [3] + ( ex4_sh_rgt_en_b and ex4_i_exp( 3) ) or + ( ex4_sh_rgt_en_b and ex4_sp ) ; + ex4_unf_car( 3) <= ex4_sh_rgt_en_b and ex4_i_exp( 4) ; -- 0 !R [4] + ex4_unf_car( 4) <= ex4_sh_rgt_en_b and ex4_i_exp( 5) ; -- 0 !R [5] + ex4_unf_car( 5) <= (not ex4_lza_amt(0) and ex4_i_exp( 6) ) or -- s ![0] [6] + (not ex4_lza_amt(0) and ex4_sp ) or + ( ex4_sp and ex4_i_exp( 6) ) ; + ex4_unf_car( 6) <= not ex4_lza_amt(1) and ex4_i_exp( 7); -- 0 ![1] [7] + ex4_unf_car( 7) <= not ex4_lza_amt(2) and ex4_i_exp( 8); -- 0 ![2] [8] + ex4_unf_car( 8) <= not ex4_lza_amt(3) and ex4_i_exp( 9); -- 0 ![3] [9] + ex4_unf_car( 9) <= not ex4_lza_amt(4) and ex4_i_exp(10); -- 0 ![4] [10] + ex4_unf_car(10) <= not ex4_lza_amt(5) and ex4_i_exp(11); -- 0 ![5] [11] + ex4_unf_car(11) <= not ex4_lza_amt(6) and ex4_i_exp(12); -- 0 ![6] [12] + ex4_unf_car(12) <= not ex4_lza_amt(7) and ex4_i_exp(13); -- 0 ![7] [13] + + + + ex4_unf_g(2 to 12) <= ex4_unf_car(2 to 12) and ex4_unf_sum(2 to 12); + ex4_unf_t(2 to 12) <= ex4_unf_car(2 to 12) or ex4_unf_sum(2 to 12); + ex4_unf_p(1) <= ex4_unf_car(1) xor ex4_unf_sum(1) ; + + + ex4_unf_m1_co12 <= ex4_unf_g(12); + ex4_unf_p0_co12 <= ex4_unf_g(12) or (ex4_unf_t(12) and ex4_unf_sum(13) ); + + + + + ex4_unf_g2_02t03 <= ex4_unf_g( 2) or (ex4_unf_t( 2) and ex4_unf_g( 3) ); + ex4_unf_g2_04t05 <= ex4_unf_g( 4) or (ex4_unf_t( 4) and ex4_unf_g( 5) ); + ex4_unf_g2_06t07 <= ex4_unf_g( 6) or (ex4_unf_t( 6) and ex4_unf_g( 7) ); + ex4_unf_g2_08t09 <= ex4_unf_g( 8) or (ex4_unf_t( 8) and ex4_unf_g( 9) ); + ex4_unf_g2_10t11 <= ex4_unf_g(10) or (ex4_unf_t(10) and ex4_unf_g(11) ); + ex4_unf_ci0_g2 <= ex4_unf_g(12) ; + ex4_unf_ci1_g2 <= ex4_unf_t(12) ; + + ex4_unf_t2_02t03 <= (ex4_unf_t( 2) and ex4_unf_t( 3) ); + ex4_unf_t2_04t05 <= (ex4_unf_t( 4) and ex4_unf_t( 5) ); + ex4_unf_t2_06t07 <= (ex4_unf_t( 6) and ex4_unf_t( 7) ); + ex4_unf_t2_08t09 <= (ex4_unf_t( 8) and ex4_unf_t( 9) ); + ex4_unf_t2_10t11 <= (ex4_unf_t(10) and ex4_unf_t(11) ); + + ex4_unf_g4_02t05 <= ex4_unf_g2_02t03 or (ex4_unf_t2_02t03 and ex4_unf_g2_04t05 ); + ex4_unf_g4_06t09 <= ex4_unf_g2_06t07 or (ex4_unf_t2_06t07 and ex4_unf_g2_08t09 ); + ex4_unf_ci0_g4 <= ex4_unf_g2_10t11 or (ex4_unf_t2_10t11 and ex4_unf_ci0_g2 ); + ex4_unf_ci1_g4 <= ex4_unf_g2_10t11 or (ex4_unf_t2_10t11 and ex4_unf_ci1_g2 ); + + ex4_unf_t4_02t05 <= (ex4_unf_t2_02t03 and ex4_unf_t2_04t05 ); + ex4_unf_t4_06t09 <= (ex4_unf_t2_06t07 and ex4_unf_t2_08t09 ); + + + ex4_unf_g8_02t09 <= ex4_unf_g4_02t05 or (ex4_unf_t4_02t05 and ex4_unf_g4_06t09 ); + ex4_unf_ci0_g8 <= ex4_unf_ci0_g4; + ex4_unf_ci1_g8 <= ex4_unf_ci1_g4; + + ex4_unf_t8_02t09 <= (ex4_unf_t4_02t05 and ex4_unf_t4_06t09 ); + + ex4_unf_ci0_02t11 <= ex4_unf_g8_02t09 or ( ex4_unf_t8_02t09 and ex4_unf_ci0_g8); + ex4_unf_ci1_02t11 <= ex4_unf_g8_02t09 or ( ex4_unf_t8_02t09 and ex4_unf_ci1_g8); + + + ex4_unf_c2_m1 <= (ex4_unf_ci0_02t11 or (ex4_unf_ci1_02t11 and ex4_unf_m1_co12) ) ; + ex4_unf_c2_p0 <= (ex4_unf_ci0_02t11 or (ex4_unf_ci1_02t11 and ex4_unf_p0_co12) ) ; + + -- 13 BITS HOLDS EVERYTHING (sign==1 {neg} means underflow) + ex4_unf_m1 <= ex4_unf_p(1) xor ex4_unf_c2_m1; + ex4_unf_p0 <= ex4_unf_p(1) xor ex4_unf_c2_p0; + + + + u_expo_p0_0: ex4_expo_p0_0_b(1 to 13) <= not(ex4_lzasub_m1(1 to 13) and (1 to 13 => f_nrm_ex4_extra_shift) ); + u_expo_p0_1: ex4_expo_p0_1_b(1 to 13) <= not(ex4_lzasub_p0(1 to 13) and (1 to 13 => not f_nrm_ex4_extra_shift) ) ; + u_expo_p0: ex4_expo_p0(1 to 13) <= not(ex4_expo_p0_0_b(1 to 13) and ex4_expo_p0_1_b(1 to 13)); + + u_expo_p1_0: ex4_expo_p1_0_b(1 to 13) <= not(ex4_lzasub_p0(1 to 13) and (1 to 13 => f_nrm_ex4_extra_shift) ); + u_expo_p1_1: ex4_expo_p1_1_b(1 to 13) <= not(ex4_lzasub_p1(1 to 13) and (1 to 13 => not f_nrm_ex4_extra_shift) ) ; + u_expo_p1: ex4_expo_p1(1 to 13) <= not(ex4_expo_p1_0_b(1 to 13) and ex4_expo_p1_1_b(1 to 13)); + + u_ovf_calc_0: ex4_ovf_calc_0_b <= not(ex4_ovf_m1 and f_nrm_ex4_extra_shift ) ; + u_ovf_calc_1: ex4_ovf_calc_1_b <= not(ex4_ovf_p0 and not f_nrm_ex4_extra_shift ) ; + u_ovf_calc: ex4_ovf_calc <= not(ex4_ovf_calc_0_b and ex4_ovf_calc_1_b ) ; + + u_ovf_if_calc_0: ex4_ovf_if_calc_0_b <= not(ex4_ovf_p0 and f_nrm_ex4_extra_shift ) ; + u_ovf_if_calc_1: ex4_ovf_if_calc_1_b <= not(ex4_ovf_p1 and not f_nrm_ex4_extra_shift ) ; + u_ovf_if_calc: ex4_ovf_if_calc <= not(ex4_ovf_if_calc_0_b and ex4_ovf_if_calc_1_b ) ; + + -- for recip sp : do not zero out exponent ... let it go neg_sp (norm in dp range) + u_unf_calc_0: ex4_unf_calc_0_b <= not(ex4_unf_m1 and f_nrm_ex4_extra_shift ) ; + u_unf_calc_1: ex4_unf_calc_1_b <= not(ex4_unf_p0 and not f_nrm_ex4_extra_shift ) ; + u_unf_calc: ex4_unf_calc <= not(ex4_unf_calc_0_b and ex4_unf_calc_1_b ) ; + + + + + ex4_est_sp <= ex4_sel_est and ex4_sp; + + ex4_unf_tbl <= f_pic_ex4_uf_en and f_tbl_ex4_unf_expo ; + ex4_unf_tbl_spec_e <= (ex4_unf_tbl and not ex4_est_sp and not f_pic_ex4_ue) or ex4_sel_k_part_e; + ex4_ov_en <= f_pic_ex4_ov_en ; + ex4_ov_en_oe0 <= f_pic_ex4_ov_en and not f_pic_ex4_oe; + ex4_sel_ov_spec <= f_pic_ex4_sel_ov_spec; + ex4_unf_en_nedge <= f_pic_ex4_uf_en and not f_lza_ex4_no_lza_edge; + ex4_unf_ue0_nestsp <= f_pic_ex4_uf_en and not f_lza_ex4_no_lza_edge and not f_pic_ex4_ue and not(ex4_est_sp); + ex4_sel_k_part_e <= f_pic_ex4_spec_sel_k_e or f_pic_ex4_to_int_ov_all ; + ex4_sel_k_part_f <= f_pic_ex4_spec_sel_k_f or f_pic_ex4_to_int_ov_all ; + + +--//############################################## +--//# EX5 latches +--//############################################## + + + ex5_urnd0_lat: entity tri.tri_nand2_nlats(tri_nand2_nlats) generic map (width=> 13, btr => "NLA0001_X1_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd , + gd => gnd , + LCLK => ex5_lclk ,-- lclk.clk + D1CLK => ex5_d1clk , + D2CLK => ex5_d2clk , + SCANIN => ex5_urnd0_si , + SCANOUT => ex5_urnd0_so , + A1 => ex4_expo_p0_0_b(1 to 13) , + A2 => ex4_expo_p0_1_b(1 to 13) , + QB(0 to 12) => ex5_expo_p0(1 to 13) );--LAT-- + + ex5_urnd1_lat: entity tri.tri_nand2_nlats(tri_nand2_nlats) generic map (width=> 13, btr => "NLA0001_X1_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd , + gd => gnd , + LCLK => ex5_lclk ,--lclk.clk + D1CLK => ex5_d1clk , + D2CLK => ex5_d2clk , + SCANIN => ex5_urnd1_si , + SCANOUT => ex5_urnd1_so , + A1 => ex4_expo_p1_0_b(1 to 13) , + A2 => ex4_expo_p1_1_b(1 to 13) , + QB(0 to 12) => ex5_expo_p1(1 to 13) );--LAT-- + + ex5_ovctl_lat: entity tri.tri_nand2_nlats(tri_nand2_nlats) generic map (width=> 3, btr => "NLA0001_X1_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd , + gd => gnd , + LCLK => ex5_lclk ,--lclk.clk + D1CLK => ex5_d1clk , + D2CLK => ex5_d2clk , + SCANIN => ex5_ovctl_si , + SCANOUT => ex5_ovctl_so , + ------------------- + A1(0) => ex4_ovf_calc_0_b , + A1(1) => ex4_ovf_if_calc_0_b , + A1(2) => ex4_unf_calc_0_b , + ------------------- + A2(0) => ex4_ovf_calc_1_b , + A2(1) => ex4_ovf_if_calc_1_b , + A2(2) => ex4_unf_calc_1_b , + ------------------- + QB(0) => ex5_ovf_calc ,--LAT-- + QB(1) => ex5_ovf_if_calc ,--LAT-- + QB(2) => ex5_unf_calc );--LAT-- + + ex5_misc_lat: tri_rlmreg_p generic map (width=> 13, expand_type => expand_type, needs_sreset => 0) port map ( + forcee => forcee,-- tidn, + delay_lclkr => delay_lclkr(5) ,-- tidn, + mpw1_b => mpw1_b(5) ,-- tidn, + mpw2_b => mpw2_b(1) ,-- tidn, + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => ex4_act, + scout => ex5_misc_so , + scin => ex5_misc_si , + ------------------- + din(0) => ex4_unf_tbl , + din(1) => ex4_unf_tbl_spec_e , + din(2) => ex4_ov_en , + din(3) => ex4_ov_en_oe0 , + din(4) => ex4_sel_ov_spec , + din(5) => ex4_unf_en_nedge , + din(6) => ex4_unf_ue0_nestsp , + din(7) => ex4_sel_k_part_f , + din(8 to 12) => ex4_ue1oe1_k(3 to 7) , + ------------------- + dout(0) => ex5_unf_tbl ,--LAT-- + dout(1) => ex5_unf_tbl_spec_e ,--LAT-- + dout(2) => ex5_ov_en ,--LAT-- + dout(3) => ex5_ov_en_oe0 ,--LAT-- + dout(4) => ex5_sel_ov_spec ,--LAT-- + dout(5) => ex5_unf_en_nedge ,--LAT-- + dout(6) => ex5_unf_ue0_nestsp ,--LAT-- + dout(7) => ex5_sel_k_part_f ,--LAT-- + dout(8 to 12) => ex5_ue1oe1_k(3 to 7) );--LAT-- + + +--//############################################## +--//# EX5 logic +--//############################################## + + f_eov_ex5_expo_p0(1 to 13) <= ex5_expo_p0(1 to 13) ;--//#rnd result exponent + f_eov_ex5_expo_p1(1 to 13) <= ex5_expo_p1(1 to 13) ;--//#rnd result exponent if rnd_up_all1 + + + --------- LEVEL 1 ----------------------------------- + + ex5_sel_ov_spec_b <= not( ex5_sel_ov_spec ); + ex5_ovf_b <= not( ex5_ovf_calc and ex5_ov_en ); + ex5_ovf_if_b <= not( ex5_ovf_if_calc and ex5_ov_en ); + ex5_ovf_oe0_b <= not( ex5_ovf_calc and ex5_ov_en_oe0 ); + ex5_ovf_if_oe0_b <= not( ex5_ovf_if_calc and ex5_ov_en_oe0 ); + ex5_unf_b <= not( ex5_unf_calc and ex5_unf_en_nedge ); + ex5_unf_ue0_b <= not( ex5_unf_calc and ex5_unf_ue0_nestsp ); + ex5_sel_k_part_f_b <= not( ex5_sel_k_part_f ); + ex5_unf_tbl_spec_e_b <= not( ex5_unf_tbl_spec_e ); + ex5_unf_tbl_b <= not( ex5_unf_tbl ); + + --------- LEVEL 2 ----------------------------------- + + f_eov_ex5_ovf_expo <= not( ex5_ovf_b and ex5_sel_ov_spec_b ); + f_eov_ex5_ovf_if_expo <= not( ex5_ovf_if_b and ex5_sel_ov_spec_b ); + f_eov_ex5_sel_k_f <= not( ex5_ovf_oe0_b and ex5_sel_k_part_f_b ); + f_eov_ex5_sel_kif_f <= not( ex5_ovf_if_oe0_b and ex5_sel_k_part_f_b ); + f_eov_ex5_unf_expo <= not( ex5_unf_b and ex5_unf_tbl_b ); + f_eov_ex5_sel_k_e <= not( ex5_unf_ue0_b and ex5_unf_tbl_spec_e_b and ex5_ovf_oe0_b ); + f_eov_ex5_sel_kif_e <= not( ex5_unf_ue0_b and ex5_unf_tbl_spec_e_b and ex5_ovf_if_oe0_b ); + + --//#----------------------------- + --//# ue1 oe1 adders (does not need to be real fast) + --//#----------------------------- + + f_eov_ex5_expo_p0_ue1oe1(3 to 6) <= ex5_ue1oe1_p0_p(3 to 6) xor ex5_ue1oe1_p0_c(4 to 7); --output- + f_eov_ex5_expo_p0_ue1oe1(7) <= ex5_ue1oe1_p0_p(7); + + ex5_ue1oe1_p0_p(3 to 7) <= ex5_expo_p0(3 to 7) xor ex5_ue1oe1_k(3 to 7); + ex5_ue1oe1_p0_g(4 to 7) <= ex5_expo_p0(4 to 7) and ex5_ue1oe1_k(4 to 7); + ex5_ue1oe1_p0_t(4 to 6) <= ex5_expo_p0(4 to 6) or ex5_ue1oe1_k(4 to 6); + + + ex5_ue1oe1_p0_g2_b(7) <= not( ex5_ue1oe1_p0_g(7) ) ; + ex5_ue1oe1_p0_g2_b(6) <= not( ex5_ue1oe1_p0_g(6) or (ex5_ue1oe1_p0_t(6) and ex5_ue1oe1_p0_g(7) ) ); + ex5_ue1oe1_p0_g2_b(5) <= not( ex5_ue1oe1_p0_g(5) ) ; + ex5_ue1oe1_p0_g2_b(4) <= not( ex5_ue1oe1_p0_g(4) or (ex5_ue1oe1_p0_t(4) and ex5_ue1oe1_p0_g(5) ) ); + + ex5_ue1oe1_p0_t2_b(5) <= not( ex5_ue1oe1_p0_t(5) ) ; + ex5_ue1oe1_p0_t2_b(4) <= not( (ex5_ue1oe1_p0_t(4) and ex5_ue1oe1_p0_t(5) ) ); + + ex5_ue1oe1_p0_c(7) <= not( ex5_ue1oe1_p0_g2_b(7) ); + ex5_ue1oe1_p0_c(6) <= not( ex5_ue1oe1_p0_g2_b(6) ); + ex5_ue1oe1_p0_c(5) <= not( ex5_ue1oe1_p0_g2_b(5) and (ex5_ue1oe1_p0_t2_b(5) or ex5_ue1oe1_p0_g2_b(6) ) ); + ex5_ue1oe1_p0_c(4) <= not( ex5_ue1oe1_p0_g2_b(4) and (ex5_ue1oe1_p0_t2_b(4) or ex5_ue1oe1_p0_g2_b(6) ) ); + + --------------------- + + f_eov_ex5_expo_p1_ue1oe1(3 to 6) <= ex5_ue1oe1_p1_p(3 to 6) xor ex5_ue1oe1_p1_c(4 to 7); --output- + f_eov_ex5_expo_p1_ue1oe1(7) <= ex5_ue1oe1_p1_p(7); + + ex5_ue1oe1_p1_p(3 to 7) <= ex5_expo_p1(3 to 7) xor ex5_ue1oe1_k(3 to 7); + ex5_ue1oe1_p1_g(4 to 7) <= ex5_expo_p1(4 to 7) and ex5_ue1oe1_k(4 to 7); + ex5_ue1oe1_p1_t(4 to 6) <= ex5_expo_p1(4 to 6) or ex5_ue1oe1_k(4 to 6); + + + ex5_ue1oe1_p1_g2_b(7) <= not( ex5_ue1oe1_p1_g(7) ) ; + ex5_ue1oe1_p1_g2_b(6) <= not( ex5_ue1oe1_p1_g(6) or (ex5_ue1oe1_p1_t(6) and ex5_ue1oe1_p1_g(7) ) ); + ex5_ue1oe1_p1_g2_b(5) <= not( ex5_ue1oe1_p1_g(5) ) ; + ex5_ue1oe1_p1_g2_b(4) <= not( ex5_ue1oe1_p1_g(4) or (ex5_ue1oe1_p1_t(4) and ex5_ue1oe1_p1_g(5) ) ); + + ex5_ue1oe1_p1_t2_b(5) <= not( ex5_ue1oe1_p1_t(5) ) ; + ex5_ue1oe1_p1_t2_b(4) <= not( (ex5_ue1oe1_p1_t(4) and ex5_ue1oe1_p1_t(5) ) ); + + ex5_ue1oe1_p1_c(7) <= not( ex5_ue1oe1_p1_g2_b(7) ); + ex5_ue1oe1_p1_c(6) <= not( ex5_ue1oe1_p1_g2_b(6) ); + ex5_ue1oe1_p1_c(5) <= not( ex5_ue1oe1_p1_g2_b(5) and (ex5_ue1oe1_p1_t2_b(5) or ex5_ue1oe1_p1_g2_b(6) ) ); + ex5_ue1oe1_p1_c(4) <= not( ex5_ue1oe1_p1_g2_b(4) and (ex5_ue1oe1_p1_t2_b(4) or ex5_ue1oe1_p1_g2_b(6) ) ); + + + +--//############################################ +--//# scan +--//############################################ + + act_si (0 to 4) <= act_so (1 to 4) & f_eov_si ; + ex4_iexp_si (0 to 15) <= ex4_iexp_so (1 to 15) & act_so (0); + ex5_ovctl_si (0 to 2) <= ex5_ovctl_so (1 to 2) & ex4_iexp_so (0); + ex5_misc_si (0 to 12) <= ex5_misc_so (1 to 12) & ex5_ovctl_so (0); + ex5_urnd0_si (0 to 12) <= ex5_urnd0_so (1 to 12) & ex5_misc_so (0); + ex5_urnd1_si (0 to 12) <= ex5_urnd1_so (1 to 12) & ex5_urnd0_so (0); + f_eov_so <= ex5_urnd1_so (0); + +end; -- fuq_eov ARCHITECTURE diff --git a/rel/src/vhdl/work/fuq_fmt.vhdl b/rel/src/vhdl/work/fuq_fmt.vhdl new file mode 100644 index 0000000..a1ffed0 --- /dev/null +++ b/rel/src/vhdl/work/fuq_fmt.vhdl @@ -0,0 +1,1740 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + + +-- bias 127 0_0000_0111_1111 +-- bias 1023 0_0011_1111_1111 infinity=> 0_0111_1111_1111 2047 +-- bias 2047 0_0111_1111_1111 infinity=> 0_1111_1111_1111 4095 +-- bias 4095 0_1111_1111_1111 infinity=> 1_1111_1111_1111 8191 +-- + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + + +entity fuq_fmt is +generic( expand_type : integer := 2 ); -- 0 - ibm tech, 1 - other ); +port( + vdd :inout power_logic; + gnd :inout power_logic; + clkoff_b :in std_ulogic; -- tiup + act_dis :in std_ulogic; -- ??tidn?? + flush :in std_ulogic; -- ??tidn?? + delay_lclkr :in std_ulogic_vector(1 to 2); -- tidn, + mpw1_b :in std_ulogic_vector(1 to 2); -- tidn, + mpw2_b :in std_ulogic_vector(0 to 0); -- tidn, + sg_1 :in std_ulogic; + thold_1 :in std_ulogic; + fpu_enable :in std_ulogic; --dc_act + nclk :in clk_logic; + + + f_fmt_si :in std_ulogic; --perv + f_fmt_so :out std_ulogic; --perv + rf1_act :in std_ulogic; --act + ex1_act :in std_ulogic; --act + + f_byp_fmt_ex1_a_sign :in std_ulogic; + f_byp_fmt_ex1_c_sign :in std_ulogic; + f_byp_fmt_ex1_b_sign :in std_ulogic; + f_byp_fmt_ex1_a_expo :in std_ulogic_vector(1 to 13); + f_byp_fmt_ex1_c_expo :in std_ulogic_vector(1 to 13); + f_byp_fmt_ex1_b_expo :in std_ulogic_vector(1 to 13); + f_byp_fmt_ex1_a_frac :in std_ulogic_vector(0 to 52); + f_byp_fmt_ex1_c_frac :in std_ulogic_vector(0 to 52); + f_byp_fmt_ex1_b_frac :in std_ulogic_vector(0 to 52); + + f_dcd_rf1_aop_valid :in std_ulogic ; + f_dcd_rf1_cop_valid :in std_ulogic ; + f_dcd_rf1_bop_valid :in std_ulogic ; + f_dcd_rf1_from_integer_b :in std_ulogic ;--no NAN + f_dcd_rf1_fsel_b :in std_ulogic ;--modify nan mux + f_dcd_rf1_force_pass_b :in std_ulogic ;--force select of nan mux (fmr) + + f_dcd_rf1_sp :in std_ulogic ; + + f_dcd_ex1_perr_force_c :in std_ulogic; + f_dcd_ex1_perr_fsel_ovrd :in std_ulogic; + + + f_pic_ex1_ftdiv :in std_ulogic; + f_pic_ex1_flush_en_sp :in std_ulogic; + f_pic_ex1_flush_en_dp :in std_ulogic; + + f_pic_ex1_nj_deni :in std_ulogic ; + f_dcd_rf1_uc_end :in std_ulogic; + f_dcd_rf1_uc_mid :in std_ulogic; + f_dcd_rf1_uc_special :in std_ulogic; + f_dcd_rf1_sgncpy_b :in std_ulogic; + + f_fmt_ex2_lu_den_recip :out std_ulogic ;--pic + f_fmt_ex2_lu_den_rsqrto :out std_ulogic ;--pic + + f_fmt_ex1_bop_byt :out std_ulogic_vector(45 to 52) ;-- shadow reg + + f_fmt_ex1_a_zero :out std_ulogic ;--pic + f_fmt_ex1_a_expo_max :out std_ulogic ;--pic + f_fmt_ex1_a_frac_zero :out std_ulogic ;--pic + f_fmt_ex1_a_frac_msb :out std_ulogic ;--pic + + f_fmt_ex1_c_zero :out std_ulogic ;--pic + f_fmt_ex1_c_expo_max :out std_ulogic ;--pic + f_fmt_ex1_c_frac_zero :out std_ulogic ;--pic + f_fmt_ex1_c_frac_msb :out std_ulogic ;--pic + + f_fmt_ex1_b_zero :out std_ulogic ;--pic + f_fmt_ex1_b_expo_max :out std_ulogic ;--pic + f_fmt_ex1_b_frac_zero :out std_ulogic ;--pic + f_fmt_ex1_b_frac_msb :out std_ulogic ;--pic + f_fmt_ex1_b_imp :out std_ulogic ;--pic-- + f_fmt_ex1_b_frac_z32 :out std_ulogic ;--pic-- + + f_fmt_ex1_prod_zero :out std_ulogic ;--alg + f_fmt_ex1_pass_sel :out std_ulogic ;--alg + + f_fmt_ex1_sp_invalid :out std_ulogic ;--pic + f_fmt_ex1_bexpu_le126 :out std_ulogic ;--pic + f_fmt_ex1_gt126 :out std_ulogic ;--pic + f_fmt_ex1_ge128 :out std_ulogic ;--pic + f_fmt_ex1_inf_and_beyond_sp :out std_ulogic ;--pic + + f_mad_ex2_uc_a_expo_den :out std_ulogic ;--dvSq input operand is already prenormed + f_mad_ex2_uc_a_expo_den_sp :out std_ulogic ;--dvSq input operand is already prenormed + --exponent negative or all zeroes + + f_ex2_b_den_flush :out std_ulogic ;--iu (does not include all gating) ??? + + f_fmt_ex2_fsel_bsel :out std_ulogic ;--pic--expo + f_fmt_ex2_pass_sign :out std_ulogic ;--alg + f_fmt_ex2_pass_msb :out std_ulogic ;--alg + f_fmt_ex1_b_frac :out std_ulogic_vector(1 to 19) ;--clz (est) + f_fmt_ex1_b_sign_gst :out std_ulogic ; + f_fmt_ex1_b_expo_gst_b :out std_ulogic_vector(1 to 13); + + f_fpr_ex1_a_par :in std_ulogic_vector(0 to 7) ; + f_fpr_ex1_c_par :in std_ulogic_vector(0 to 7) ; + f_fpr_ex1_b_par :in std_ulogic_vector(0 to 7) ; + f_mad_ex2_a_parity_check :out std_ulogic ;-- raw calculation + f_mad_ex2_c_parity_check :out std_ulogic ;-- raw calculation + f_mad_ex2_b_parity_check :out std_ulogic ;-- raw calculation + + f_fmt_ex2_ae_ge_54 :out std_ulogic ;--unbiased exponent not LE -970 + f_fmt_ex2_be_ge_54 :out std_ulogic ;--unbiased exponent not LE -970 + f_fmt_ex2_be_ge_2 :out std_ulogic ;--unbiased exponent not le 1 + f_fmt_ex2_be_ge_2044 :out std_ulogic ;--unbiased exponent ge 1023 + f_fmt_ex2_tdiv_rng_chk :out std_ulogic ;--unbiased exponent ae-be >= 1023, <= -1021 + f_fmt_ex2_be_den :out std_ulogic ;--b expo <= 0 + f_fmt_ex2_pass_frac :out std_ulogic_vector(0 to 52) --alg + +); + + +end fuq_fmt; -- ENTITY + +architecture fuq_fmt of fuq_fmt is + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal thold_0_b, thold_0, forcee :std_ulogic; + signal sg_0 :std_ulogic; + signal spare_unused :std_ulogic_vector(0 to 3); + ---------------------------------------- + signal act_si :std_ulogic_vector(0 to 6);--SCAN + signal act_so :std_ulogic_vector(0 to 6);--SCAN + + signal ex1_ctl_si :std_ulogic_vector(0 to 8);--SCAN + signal ex1_ctl_so :std_ulogic_vector(0 to 8);--SCAN + signal ex2_pass_si :std_ulogic_vector(0 to 79);--SCAN + signal ex2_pass_so :std_ulogic_vector(0 to 79);--SCAN + ---------------------------------------- + signal ex2_pass_frac :std_ulogic_vector(0 to 52); + signal ex1_from_integer :std_ulogic; + signal ex1_fsel :std_ulogic; + signal ex1_force_pass :std_ulogic; + signal ex1_a_sign :std_ulogic; + signal ex1_c_sign :std_ulogic; + signal ex1_b_sign :std_ulogic; + signal ex2_fsel_bsel :std_ulogic; + signal ex2_pass_sign :std_ulogic; + ---------------------------------------- + signal ex1_a_frac :std_ulogic_vector(0 to 52); + signal ex1_c_frac :std_ulogic_vector(0 to 52); + signal ex1_b_frac :std_ulogic_vector(0 to 52); + signal ex1_pass_frac_ac :std_ulogic_vector(0 to 52); + signal ex1_pass_frac :std_ulogic_vector(0 to 52); + signal ex1_a_frac_msb :std_ulogic; + signal ex1_a_expo_min :std_ulogic; + signal ex1_a_expo_max :std_ulogic; + signal ex1_a_frac_zero :std_ulogic; + signal ex1_c_frac_msb :std_ulogic; + signal ex1_c_expo_min :std_ulogic; + signal ex1_c_expo_max :std_ulogic; + signal ex1_c_frac_zero :std_ulogic; + signal ex1_b_frac_msb :std_ulogic; + signal ex1_b_expo_min :std_ulogic; + signal ex1_b_expo_max :std_ulogic; + signal ex1_b_frac_zero :std_ulogic; + signal ex1_b_frac_z32 :std_ulogic; + signal ex1_a_nan :std_ulogic; + signal ex1_c_nan :std_ulogic; + signal ex1_b_nan :std_ulogic; + signal ex1_nan_pass :std_ulogic; + signal ex1_pass_sel :std_ulogic; + signal ex1_fsel_cif :std_ulogic; + signal ex1_fsel_bsel :std_ulogic; + signal ex1_mux_a_sel :std_ulogic; + signal ex1_mux_c_sel :std_ulogic; + signal ex1_pass_sign_ac :std_ulogic; + signal ex1_pass_sign :std_ulogic; + signal ex1_a_expo :std_ulogic_vector(1 to 13); + signal ex1_b_expo :std_ulogic_vector(1 to 13); + signal ex1_c_expo :std_ulogic_vector(1 to 13); + signal ex1_a_expo_b :std_ulogic_vector(1 to 13); + signal ex1_c_expo_b :std_ulogic_vector(1 to 13); + signal ex1_b_expo_b :std_ulogic_vector(1 to 13); + signal rf1_aop_valid_b :std_ulogic; + signal rf1_cop_valid_b :std_ulogic; + signal rf1_bop_valid_b :std_ulogic; + signal ex1_aop_valid :std_ulogic; + signal ex1_cop_valid :std_ulogic; + signal ex1_bop_valid :std_ulogic; + signal ex1_a_zero :std_ulogic; + signal ex1_c_zero :std_ulogic; + signal ex1_b_zero :std_ulogic; + signal ex1_a_zero_x :std_ulogic; + signal ex1_c_zero_x :std_ulogic; + signal ex1_b_zero_x :std_ulogic; + signal ex1_a_sp_expo_ok_1 :std_ulogic; + signal ex1_c_sp_expo_ok_1 :std_ulogic; + signal ex1_b_sp_expo_ok_1 :std_ulogic; + signal ex1_a_sp_expo_ok_2 :std_ulogic; + signal ex1_c_sp_expo_ok_2 :std_ulogic; + signal ex1_b_sp_expo_ok_2 :std_ulogic; + signal ex1_a_sp_expo_ok_3 :std_ulogic; + signal ex1_c_sp_expo_ok_3 :std_ulogic; + signal ex1_b_sp_expo_ok_3 :std_ulogic; + signal ex1_a_sp_expo_ok_4 :std_ulogic; + signal ex1_c_sp_expo_ok_4 :std_ulogic; + signal ex1_b_sp_expo_ok_4 :std_ulogic; + signal ex2_pass_dp :std_ulogic_vector(0 to 52); + signal ex1_from_integer_b :std_ulogic; + signal ex1_fsel_b :std_ulogic; + signal ex1_aop_valid_b :std_ulogic; + signal ex1_cop_valid_b :std_ulogic; + signal ex1_bop_valid_b :std_ulogic; + signal ex1_b_den_flush, ex1_b_den_sp , ex1_a_den_sp , ex1_b_den_dp , ex2_b_den_flush :std_ulogic; + signal ex1_lu_den_part, ex1_lu_den_recip, ex1_lu_den_rsqrto :std_ulogic; + signal ex2_lu_den_recip, ex2_lu_den_rsqrto :std_ulogic; + signal ex1_recip_lo , ex1_rsqrt_lo :std_ulogic; + signal ex1_bfrac_eq_126, ex1_bfrac_126_nz :std_ulogic; + signal ex1_bexpo_ge897_hi :std_ulogic; + signal ex1_bexpo_ge897_mid1 :std_ulogic; + signal ex1_bexpo_ge897_mid2 :std_ulogic; + signal ex1_bexpo_ge897_lo :std_ulogic; + signal ex1_bexpo_ge897 :std_ulogic; + signal ex1_bexpu_eq6 :std_ulogic ; + signal ex1_bexpu_ge7 :std_ulogic ; + signal ex1_bexpu_ge7_lo :std_ulogic ; + signal ex1_bexpu_ge7_mid :std_ulogic ; + signal ex1_a_sp, ex1_c_sp , ex1_b_sp :std_ulogic ; + signal ex1_b_frac_zero_sp, ex1_b_frac_zero_dp :std_ulogic ; + signal ex1_a_denz , ex1_c_denz , ex1_b_denz :std_ulogic ; + signal ex1_a_frac_chop, ex1_c_frac_chop, ex1_b_frac_chop :std_ulogic_vector(0 to 52); + + signal rf1_sgncpy, ex1_sgncpy , ex1_uc_mid :std_ulogic; + signal rf1_force_pass :std_ulogic; + signal rf1_uc_end_nspec, rf1_uc_end_spec, ex1_uc_end_nspec :std_ulogic; + signal ex1_uc_a_expo_den , ex2_uc_a_expo_den :std_ulogic ; + signal ex1_uc_a_expo_den_sp , ex2_uc_a_expo_den_sp :std_ulogic ; + + signal ex1_a_expo_ltx381_sp, ex1_a_expo_ltx381, ex1_a_expo_00xx_xxxx_xxxx, ex1_a_expo_xx11_1xxx_xxxx, ex1_a_expo_xxxx_x000_0000 :std_ulogic; + signal ex1_c_expo_ltx381_sp, ex1_c_expo_ltx381, ex1_c_expo_00xx_xxxx_xxxx, ex1_c_expo_xx11_1xxx_xxxx, ex1_c_expo_xxxx_x000_0000 :std_ulogic; + signal ex1_b_expo_ltx381_sp, ex1_b_expo_ltx381, ex1_b_expo_00xx_xxxx_xxxx, ex1_b_expo_xx11_1xxx_xxxx, ex1_b_expo_xxxx_x000_0000 :std_ulogic; + signal ex1_a_sp_inf_alias_tail, ex1_c_sp_inf_alias_tail, ex1_b_sp_inf_alias_tail :std_ulogic; + signal ex2_a_party_chick , ex2_c_party_chick , ex2_b_party_chick :std_ulogic ; + signal ex1_a_party_chick , ex1_c_party_chick , ex1_b_party_chick :std_ulogic ; + signal ex1_a_party, ex1_c_party, ex1_b_party :std_ulogic_vector(0 to 7); + signal ex1_b_expo_ge1151 :std_ulogic ; + signal ex1_ae_234567, ex1_ae_89, ex1_ae_abc, ex1_ae_ge_54, ex2_ae_ge_54 :std_ulogic ; + signal ex1_be_234567, ex1_be_89, ex1_be_abc, ex1_be_ge_54, ex2_be_ge_54 :std_ulogic ; +signal ex1_be_ge_2, ex2_be_ge_2, ex1_be_or_23456789abc :std_ulogic; +signal ex1_be_ge_2044, ex2_be_ge_2044, ex1_be_and_3456789ab :std_ulogic; + signal ex1_aembex_car_b, ex1_aembey_car_b :std_ulogic_vector(0 to 12) ; + signal ex1_aembex_sum_b, ex1_aembey_sum_b :std_ulogic_vector(1 to 13) ; + signal ex1_aembex_g1, ex1_aembey_g1 :std_ulogic_vector(2 to 12) ; + signal ex1_aembex_t1, ex1_aembey_t1 :std_ulogic_vector(2 to 12) ; + signal ex1_aembex_g2, ex1_aembey_g2 :std_ulogic_vector(0 to 5) ; + signal ex1_aembex_t2, ex1_aembey_t2 :std_ulogic_vector(0 to 4) ; + signal ex1_aembex_g4, ex1_aembey_g4 :std_ulogic_vector(0 to 2) ; + signal ex1_aembex_t4, ex1_aembey_t4 :std_ulogic_vector(0 to 1) ; + signal ex2_aembex_g4, ex2_aembey_g4 :std_ulogic_vector(0 to 2) ; + signal ex2_aembex_t4, ex2_aembey_t4 :std_ulogic_vector(0 to 1) ; + signal ex2_aembex_g8, ex2_aembey_g8 :std_ulogic_vector(0 to 1); + signal ex2_aembex_t8, ex2_aembey_t8 :std_ulogic_vector(0 to 0); + signal ex2_aembex_c2, ex2_aembey_c2 :std_ulogic; + signal ex1_aembex_sgn, ex1_aembey_sgn :std_ulogic; + signal ex2_aembex_sgn, ex2_aembey_sgn :std_ulogic; + signal ex2_aembex_res_sgn, ex2_aembey_res_sgn :std_ulogic; + signal unused :std_ulogic; + signal ex1_be_den, ex2_be_den :std_ulogic; + + + +--#=############################################################## +--# map block attributes +--#=############################################################## + +begin + +unused <= ex1_aembex_car_b(0) or + ex1_aembex_sum_b(13) or + ex1_aembex_t1(12) or + ex1_aembey_car_b(0) or + ex1_aembey_sum_b(13) or + ex1_aembey_t1(12) ; + +--#=############################################################## +--# pervasive +--#=############################################################## + + + thold_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => thold_1, + q(0) => thold_0 ); + + sg_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => sg_1 , + q(0) => sg_0 ); + + + lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map ( + clkoff_b => clkoff_b, + thold => thold_0, + sg => sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => thold_0_b ); + + +--#=############################################################## +--# act +--#=############################################################## + + + act_lat: tri_rlmreg_p generic map (width=> 7, expand_type => expand_type, needs_sreset => 0) port map ( + forcee => forcee,--i-- tidn, + delay_lclkr => delay_lclkr(1) ,--i-- tidn, + mpw1_b => mpw1_b(1) ,--i-- tidn, + mpw2_b => mpw2_b(0) ,--i-- tidn, + vd => vdd, + gd => gnd, + nclk => nclk, + act => fpu_enable, + thold_b => thold_0_b, + sg => sg_0, + scout => act_so , + scin => act_si , + ------------------- + din(0) => spare_unused(0), + din(1) => spare_unused(1), + din(2) => f_dcd_rf1_sp , + din(3) => f_dcd_rf1_sp , + din(4) => f_dcd_rf1_sp , + din(5) => spare_unused(2), + din(6) => spare_unused(3), + ------------------- + dout(0) => spare_unused(0), + dout(1) => spare_unused(1), + dout(2) => ex1_a_sp , + dout(3) => ex1_c_sp , + dout(4) => ex1_b_sp , + dout(5) => spare_unused(2) , + dout(6) => spare_unused(3) ); + + + +--#=############################################################## +--# rf1 logic (after bypass) +--#=############################################################## + + rf1_aop_valid_b <= not f_dcd_rf1_aop_valid; + rf1_cop_valid_b <= not f_dcd_rf1_cop_valid; + rf1_bop_valid_b <= not f_dcd_rf1_bop_valid; + + +--#=############################################################## +--# ex1 latches (from rf1 logic) +--#=############################################################## + + ex1_a_frac(0 to 52) <= f_byp_fmt_ex1_a_frac(0 to 52); + ex1_c_frac(0 to 52) <= f_byp_fmt_ex1_c_frac(0 to 52); + ex1_b_frac(0 to 52) <= f_byp_fmt_ex1_b_frac(0 to 52); + + + ex1_a_sign <= f_byp_fmt_ex1_a_sign ;--rename-- + ex1_c_sign <= f_byp_fmt_ex1_c_sign ;--rename-- + ex1_b_sign <= f_byp_fmt_ex1_b_sign ;--rename-- + + ex1_a_expo(1 to 13) <= f_byp_fmt_ex1_a_expo(1 to 13);--rename-- + ex1_c_expo(1 to 13) <= f_byp_fmt_ex1_c_expo(1 to 13);--rename-- + ex1_b_expo(1 to 13) <= f_byp_fmt_ex1_b_expo(1 to 13);--rename-- + + ex1_a_expo_b(1 to 13) <= not ex1_a_expo(1 to 13); + ex1_c_expo_b(1 to 13) <= not ex1_c_expo(1 to 13) ; + ex1_b_expo_b(1 to 13) <= not ex1_b_expo(1 to 13) ; + + f_fmt_ex1_b_sign_gst <= ex1_b_sign ; + rf1_sgncpy <= not f_dcd_rf1_sgncpy_b; + rf1_uc_end_nspec <= f_dcd_rf1_uc_end and not f_dcd_rf1_uc_special ; + rf1_uc_end_spec <= f_dcd_rf1_uc_end and f_dcd_rf1_uc_special ; + rf1_force_pass <= (not f_dcd_rf1_force_pass_b) or rf1_uc_end_spec; + + + ex1_ctl_lat: tri_rlmreg_p generic map (width=> 9, expand_type => expand_type, needs_sreset => 0) port map ( + forcee => forcee,--i-- tidn, + delay_lclkr => delay_lclkr(1) ,--i-- tidn, + mpw1_b => mpw1_b(1) ,--i-- tidn, + mpw2_b => mpw2_b(0) ,--i-- tidn, + vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_act, + thold_b => thold_0_b, + sg => sg_0, + scout => ex1_ctl_so , + scin => ex1_ctl_si , + ------------------- + din(0) => f_dcd_rf1_from_integer_b , + din(1) => f_dcd_rf1_fsel_b , + din(2) => rf1_force_pass , + din(3) => rf1_aop_valid_b, + din(4) => rf1_cop_valid_b, + din(5) => rf1_bop_valid_b, + din(6) => rf1_sgncpy , + din(7) => rf1_uc_end_nspec, + din(8) => f_dcd_rf1_uc_mid, + ------------------- + dout(0) => ex1_from_integer_b , + dout(1) => ex1_fsel_b , + dout(2) => ex1_force_pass , + dout(3) => ex1_aop_valid_b, + dout(4) => ex1_cop_valid_b, + dout(5) => ex1_bop_valid_b, + dout(6) => ex1_sgncpy , + dout(7) => ex1_uc_end_nspec , + dout(8) => ex1_uc_mid ); + + ex1_from_integer <= not ex1_from_integer_b ; + ex1_fsel <= not ex1_fsel_b ; + ex1_aop_valid <= not ex1_aop_valid_b ; + ex1_cop_valid <= not ex1_cop_valid_b ; + ex1_bop_valid <= not ex1_bop_valid_b ; + + +--#=############################################################## +--# ex1 logic +--#=############################################################## + f_fmt_ex1_bop_byt(45 to 52) <= ex1_b_frac(45 to 52);--output-- -- shadow reg + + --#=--------------------------------------------------- + --#= Boundary conditions for log2e/pow2e special cases + --#=--------------------------------------------------- + --#= exponent Lt 2**-126 ... -126 +1023 = 897 (sp denorms) x 0_0011_1000_0001 + --#= number less than -126 (2**6) <64>.<32><16>(8><4><2> + --#= x0_0011_1111_1111 bias = 1023 + --#= x0_0000_0000_0110 unbiased + --#= ----------------- + --#= x0_0100_0000_0101 biased 6 + + f_fmt_ex1_b_expo_gst_b(1 to 13) <= not ex1_b_expo(1 to 13) ; + + + ex1_bexpo_ge897_hi <= not ex1_b_expo(1) and -- positive exponent + ex1_b_frac(0); -- must be normalized (897 includes sp denorms) + ex1_bexpo_ge897_mid1 <= ex1_b_expo(2) or ex1_b_expo(3) ; + ex1_bexpo_ge897_mid2 <= ex1_b_expo(4) and ex1_b_expo(5) and ex1_b_expo(6) ; + ex1_bexpo_ge897_lo <= ex1_b_expo(7) or ex1_b_expo(8) or ex1_b_expo(9) or + ex1_b_expo(10) or ex1_b_expo(11) or ex1_b_expo(12) or + ex1_b_expo(13) ; + + ex1_bexpo_ge897 <= + ( ex1_bexpo_ge897_hi and ex1_bexpo_ge897_mid1 ) or + ( ex1_bexpo_ge897_hi and ex1_bexpo_ge897_mid2 and ex1_bexpo_ge897_lo ) ; + + ex1_bexpu_ge7_mid <= ex1_b_expo(4) or ex1_b_expo(5) or ex1_b_expo(6) or + ex1_b_expo(7) or ex1_b_expo(8) or ex1_b_expo(9) or ex1_b_expo(10); + ex1_bexpu_ge7_lo <= ex1_b_expo(11) and ex1_b_expo(12) ; + + ex1_bexpu_ge7 <= + ( not ex1_b_expo(1) and ex1_b_expo(2) ) or + ( not ex1_b_expo(1) and ex1_b_expo(3) and ex1_bexpu_ge7_mid ) or + ( not ex1_b_expo(1) and ex1_b_expo(3) and ex1_bexpu_ge7_lo ) ; + + ex1_bexpu_eq6 <= -- 0_0100_0000_0101 1023+6 - 1024+5 + not ex1_b_expo(1) and -- +expo + not ex1_b_expo(2) and -- 2048 + ex1_b_expo(3) and -- 1024 + not ex1_b_expo(4) and -- 512 + not ex1_b_expo(5) and -- 256 + not ex1_b_expo(6) and -- 128 + not ex1_b_expo(7) and -- 64 + not ex1_b_expo(8) and -- 32 + not ex1_b_expo(9) and -- 16 + not ex1_b_expo(10) and -- 8 + ex1_b_expo(11) and -- 4 + not ex1_b_expo(12) and -- 2 + ex1_b_expo(13) ; -- 1 + + + f_fmt_ex1_bexpu_le126 <= not ex1_bexpo_ge897; --output-- + f_fmt_ex1_gt126 <= ex1_bexpu_ge7 or --output-- + (ex1_bexpu_eq6 and ex1_bfrac_eq_126 and ex1_bfrac_126_nz ) ; + f_fmt_ex1_ge128 <= ex1_bexpu_ge7 ; --output-- + + -- exponent >= 1023 + 128 = 1151 (1024+127) + -- 1 2345 6789 abcd + ex1_b_expo_ge1151 <= -- 0_0100_0111 _1111 <-- 1151 aliases to sp infinity/nan range + ( ex1_b_expo_b(1) and not ex1_b_expo_b(2) ) or -- 0_1xxx_xxxx_xxxx + ( ex1_b_expo_b(1) and not ex1_b_expo_b(3) and not ex1_b_expo_b(4) ) or -- 0_x11x_xxxx_xxxx + ( ex1_b_expo_b(1) and not ex1_b_expo_b(3) and not ex1_b_expo_b(5) ) or -- 0_x1x1_xxxx_xxxx + ( ex1_b_expo_b(1) and not ex1_b_expo_b(3) and not ex1_b_expo_b(6) ) or -- 0_x1xx_1xxx_xxxx + ( ex1_b_expo_b(1) and not ex1_b_expo_b(3) and not ex1_b_expo_b(7) -- 0_x1xx_x111_1111 + and not ex1_b_expo_b(8) + and not ex1_b_expo_b(9) + and not ex1_b_expo_b(10) + and not ex1_b_expo_b(11) + and not ex1_b_expo_b(12) + and not ex1_b_expo_b(13) ); + + + f_fmt_ex1_inf_and_beyond_sp <= ex1_b_expo_max or ex1_b_expo_ge1151 ; + + + + + ex1_bfrac_eq_126 <= ex1_b_frac(0) and --64 + ex1_b_frac(1) and --32 + ex1_b_frac(2) and --16 + ex1_b_frac(3) and -- 8 + ex1_b_frac(4) and -- 4 + ex1_b_frac(5) ; -- 2 + + + ex1_bfrac_126_nz <= ex1_b_frac(6) or + ex1_b_frac(7) or + ex1_b_frac(8) or + ex1_b_frac(9) or + ex1_b_frac(10) or + ex1_b_frac(11) or + ex1_b_frac(12) or + ex1_b_frac(13) or + ex1_b_frac(14) or + ex1_b_frac(15) or + ex1_b_frac(16) or + ex1_b_frac(17) or + ex1_b_frac(18) or + ex1_b_frac(19) or + ex1_b_frac(20) or + ex1_b_frac(21) or + ex1_b_frac(22) or + ex1_b_frac(23) ; + + + --#=-------------------------------------------------- + --#= all1/all0 determination + --#=-------------------------------------------------- + + ex1_a_frac_msb <= ex1_a_frac(1); + ex1_c_frac_msb <= ex1_c_frac(1); + ex1_b_frac_msb <= ex1_b_frac(1); + + ex1_a_expo_min <= not ex1_a_frac(0) ;-- implicit bit off + ex1_c_expo_min <= not ex1_c_frac(0) ; + ex1_b_expo_min <= not ex1_b_frac(0) ; + + ex1_a_expo_max <= ex1_a_expo_b(1) and + ex1_a_expo_b(2) and + not ex1_a_expo_b(3) and + not ex1_a_expo_b(4) and + not ex1_a_expo_b(5) and + not ex1_a_expo_b(6) and + not ex1_a_expo_b(7) and + not ex1_a_expo_b(8) and + not ex1_a_expo_b(9) and + not ex1_a_expo_b(10) and + not ex1_a_expo_b(11) and + not ex1_a_expo_b(12) and + not ex1_a_expo_b(13) ; + + ex1_c_expo_max <= ex1_c_expo_b(1) and + ex1_c_expo_b(2) and + not ex1_c_expo_b(3) and + not ex1_c_expo_b(4) and + not ex1_c_expo_b(5) and + not ex1_c_expo_b(6) and + not ex1_c_expo_b(7) and + not ex1_c_expo_b(8) and + not ex1_c_expo_b(9) and + not ex1_c_expo_b(10) and + not ex1_c_expo_b(11) and + not ex1_c_expo_b(12) and + not ex1_c_expo_b(13) ; + + ex1_b_expo_max <= ex1_b_expo_b(1) and + ex1_b_expo_b(2) and + not ex1_b_expo_b(3) and + not ex1_b_expo_b(4) and + not ex1_b_expo_b(5) and + not ex1_b_expo_b(6) and + not ex1_b_expo_b(7) and + not ex1_b_expo_b(8) and + not ex1_b_expo_b(9) and + not ex1_b_expo_b(10) and + not ex1_b_expo_b(11) and + not ex1_b_expo_b(12) and + not ex1_b_expo_b(13) ; + + + ex1_a_frac_zero <= + not ex1_a_frac( 1) and + not ex1_a_frac( 2) and + not ex1_a_frac( 3) and + not ex1_a_frac( 4) and + not ex1_a_frac( 5) and + not ex1_a_frac( 6) and + not ex1_a_frac( 7) and + not ex1_a_frac( 8) and + not ex1_a_frac( 9) and + not ex1_a_frac(10) and + not ex1_a_frac(11) and + not ex1_a_frac(12) and + not ex1_a_frac(13) and + not ex1_a_frac(14) and + not ex1_a_frac(15) and + not ex1_a_frac(16) and + not ex1_a_frac(17) and + not ex1_a_frac(18) and + not ex1_a_frac(19) and + not ex1_a_frac(20) and + not ex1_a_frac(21) and + not ex1_a_frac(22) and + not ex1_a_frac(23) and + not ex1_a_frac(24) and + not ex1_a_frac(25) and + not ex1_a_frac(26) and + not ex1_a_frac(27) and + not ex1_a_frac(28) and + not ex1_a_frac(29) and + not ex1_a_frac(30) and + not ex1_a_frac(31) and + not ex1_a_frac(32) and + not ex1_a_frac(33) and + not ex1_a_frac(34) and + not ex1_a_frac(35) and + not ex1_a_frac(36) and + not ex1_a_frac(37) and + not ex1_a_frac(38) and + not ex1_a_frac(39) and + not ex1_a_frac(40) and + not ex1_a_frac(41) and + not ex1_a_frac(42) and + not ex1_a_frac(43) and + not ex1_a_frac(44) and + not ex1_a_frac(45) and + not ex1_a_frac(46) and + not ex1_a_frac(47) and + not ex1_a_frac(48) and + not ex1_a_frac(49) and + not ex1_a_frac(50) and + not ex1_a_frac(51) and + not ex1_a_frac(52) ; + + ex1_c_frac_zero <= + not ex1_c_frac( 1) and + not ex1_c_frac( 2) and + not ex1_c_frac( 3) and + not ex1_c_frac( 4) and + not ex1_c_frac( 5) and + not ex1_c_frac( 6) and + not ex1_c_frac( 7) and + not ex1_c_frac( 8) and + not ex1_c_frac( 9) and + not ex1_c_frac(10) and + not ex1_c_frac(11) and + not ex1_c_frac(12) and + not ex1_c_frac(13) and + not ex1_c_frac(14) and + not ex1_c_frac(15) and + not ex1_c_frac(16) and + not ex1_c_frac(17) and + not ex1_c_frac(18) and + not ex1_c_frac(19) and + not ex1_c_frac(20) and + not ex1_c_frac(21) and + not ex1_c_frac(22) and + not ex1_c_frac(23) and + not ex1_c_frac(24) and + not ex1_c_frac(25) and + not ex1_c_frac(26) and + not ex1_c_frac(27) and + not ex1_c_frac(28) and + not ex1_c_frac(29) and + not ex1_c_frac(30) and + not ex1_c_frac(31) and + not ex1_c_frac(32) and + not ex1_c_frac(33) and + not ex1_c_frac(34) and + not ex1_c_frac(35) and + not ex1_c_frac(36) and + not ex1_c_frac(37) and + not ex1_c_frac(38) and + not ex1_c_frac(39) and + not ex1_c_frac(40) and + not ex1_c_frac(41) and + not ex1_c_frac(42) and + not ex1_c_frac(43) and + not ex1_c_frac(44) and + not ex1_c_frac(45) and + not ex1_c_frac(46) and + not ex1_c_frac(47) and + not ex1_c_frac(48) and + not ex1_c_frac(49) and + not ex1_c_frac(50) and + not ex1_c_frac(51) and + not ex1_c_frac(52) ; + + + ex1_b_frac_zero_sp <= + not ex1_b_frac( 1) and + not ex1_b_frac( 2) and + not ex1_b_frac( 3) and + not ex1_b_frac( 4) and + not ex1_b_frac( 5) and + not ex1_b_frac( 6) and + not ex1_b_frac( 7) and + not ex1_b_frac( 8) and + not ex1_b_frac( 9) and + not ex1_b_frac(10) and + not ex1_b_frac(11) and + not ex1_b_frac(12) and + not ex1_b_frac(13) and + not ex1_b_frac(14) and + not ex1_b_frac(15) and + not ex1_b_frac(16) and + not ex1_b_frac(17) and + not ex1_b_frac(18) and + not ex1_b_frac(19) and + not ex1_b_frac(20) and + not ex1_b_frac(21) and + not ex1_b_frac(22) and + not ex1_b_frac(23) ; + + ex1_b_frac_zero <= ex1_b_frac_zero_sp and ex1_b_frac_zero_dp ; + + ex1_b_frac_z32 <= + not ex1_b_frac(24) and + not ex1_b_frac(25) and + not ex1_b_frac(26) and + not ex1_b_frac(27) and + not ex1_b_frac(28) and + not ex1_b_frac(29) and + not ex1_b_frac(30) and + not ex1_b_frac(31) ; + f_fmt_ex1_b_frac_z32 <= ex1_b_frac_zero_sp and ex1_b_frac_z32; + ex1_b_frac_zero_dp <= ex1_b_frac_z32 and + not ex1_b_frac(32) and + not ex1_b_frac(33) and + not ex1_b_frac(34) and + not ex1_b_frac(35) and + not ex1_b_frac(36) and + not ex1_b_frac(37) and + not ex1_b_frac(38) and + not ex1_b_frac(39) and + not ex1_b_frac(40) and + not ex1_b_frac(41) and + not ex1_b_frac(42) and + not ex1_b_frac(43) and + not ex1_b_frac(44) and + not ex1_b_frac(45) and + not ex1_b_frac(46) and + not ex1_b_frac(47) and + not ex1_b_frac(48) and + not ex1_b_frac(49) and + not ex1_b_frac(50) and + not ex1_b_frac(51) and + not ex1_b_frac(52) ; + + + f_fmt_ex1_b_frac(1 to 19) <= ex1_b_frac(1 to 19) ; --output-- to tables + + ex1_a_denz <= (not ex1_a_frac(0) or ex1_a_expo_ltx381_sp) and f_pic_ex1_nj_deni ; -- also true after prenorm + ex1_c_denz <= (not ex1_c_frac(0) or ex1_c_expo_ltx381_sp) and f_pic_ex1_nj_deni ; -- also true after prenorm + ex1_b_denz <= (not ex1_b_frac(0) or ex1_b_expo_ltx381_sp) and f_pic_ex1_nj_deni and not ex1_from_integer; -- also true after prenorm + + ex1_a_zero_x <= ( ex1_a_denz or (ex1_a_expo_min and ex1_a_frac_zero) ); + ex1_c_zero_x <= ( ex1_c_denz or (ex1_c_expo_min and ex1_c_frac_zero) ); + ex1_b_zero_x <= ( ex1_b_denz or (ex1_b_expo_min and ex1_b_frac_zero) ) and (not ex1_from_integer or not ex1_b_sign ); + + + -- from integer only does prenorm on SP denorm (exponent=x381) + + ex1_b_den_flush <= ex1_b_den_sp or ex1_b_den_dp or ex1_a_den_sp; + + ex1_b_den_dp <= f_pic_ex1_flush_en_dp and + ex1_bop_valid and + ex1_b_expo_min and -- really just the implicit bit + not ex1_b_frac_zero and + not f_pic_ex1_nj_deni and -- don't flush if converting inputs to zero + not ex1_b_expo(5) ; -- <== dp denorm !! + + -- from integer still needs to fix SP denorms + ex1_b_den_sp <= f_pic_ex1_flush_en_sp and + ex1_bop_valid and + ex1_b_expo_min and -- really just the implicit bit + not ex1_b_frac_zero and + not(f_pic_ex1_nj_deni and not ex1_from_integer) and -- don't flush if converting inputs to zero + ex1_b_expo(5) ; -- <== sp denorm !! + + ex1_a_den_sp <= f_pic_ex1_ftdiv and + ex1_aop_valid and + ex1_a_expo_min and -- really just the implicit bit + not ex1_a_frac_zero and + not f_pic_ex1_nj_deni and -- don't flush if converting inputs to zero + ex1_a_expo(5) ; -- <== sp denorm !! + + + + --lookup result will be denormal + ex1_lu_den_part <= ex1_b_frac(1) and + ex1_b_frac(2) and + ex1_b_frac(3) and + ex1_b_frac(4) and + ex1_b_frac(5) and + ex1_b_frac(6) and + ex1_b_frac(7) and + ex1_b_frac(8) and + ex1_b_frac(9) and + ex1_b_frac(10) and + ex1_b_frac(11) and + ex1_b_frac(12) ; + + ex1_recip_lo <= + ex1_b_frac(14) or + ex1_b_frac(15) or + ex1_b_frac(16) or + ex1_b_frac(17) or + ( ex1_b_frac(18) and ex1_b_frac(19) ) or + ( ex1_b_frac(18) and ex1_b_frac(20) ) ; + + -- 0 1 2 + -- 1234 56 78 9012 3456 7890 12 + -- 1111 11 11 1111 1011 recip + -- 1111 11 11 1111 1010 0001 01 recip + -- + -- 1111 11 11 1111 0001 rsqo + + -- 366FFF0980000000 real boubdary for recip sqrt even + -- FFF098 real boubdary for recip sqrt even + -- + -- 1111 1111 1111 0000 1001 1000 + -- 1234 5678 9012 3456 7890 + -- 0 1 2 + + -- 3CFFFF8500000000 real boundary for reciprocal + -- FFF85 + -- 1111 1111 1111 1000 01010 + -- 1234 5678 9012 3456 7890 + -- 0 1 2 + + ex1_rsqrt_lo <= + ex1_b_frac(13) or + ex1_b_frac(14) or + ex1_b_frac(15) or + ex1_b_frac(16) or + ( ex1_b_frac(17) and ex1_b_frac(18) ) or + ( ex1_b_frac(17) and ex1_b_frac(19) ) or + ( ex1_b_frac(17) and ex1_b_frac(20) and ex1_b_frac(21) ) ; + + + + ex1_lu_den_recip <= + (ex1_lu_den_part and ex1_b_frac(13) and ex1_recip_lo ); + + ex1_lu_den_rsqrto <= + (ex1_lu_den_part and ex1_rsqrt_lo ); + + f_fmt_ex2_lu_den_recip <= ex2_lu_den_recip; + f_fmt_ex2_lu_den_rsqrto <= ex2_lu_den_rsqrto; -- name is wrong (even biased, odd unbiased) + + + + + ex1_a_zero <= ex1_aop_valid and ex1_a_zero_x ; + ex1_c_zero <= ex1_cop_valid and ex1_c_zero_x ; + ex1_b_zero <= ex1_bop_valid and ex1_b_zero_x ; + + + + f_fmt_ex1_a_zero <= ex1_a_zero ;--output-- + f_fmt_ex1_a_expo_max <= ex1_aop_valid and ex1_a_expo_max ;--output-- + f_fmt_ex1_a_frac_zero <= ex1_a_frac_zero ;--output-- + f_fmt_ex1_a_frac_msb <= ex1_a_frac_msb ;--output-- + + f_fmt_ex1_c_zero <= ex1_c_zero ;--output-- + f_fmt_ex1_c_expo_max <= ex1_cop_valid and ex1_c_expo_max ;--output-- + f_fmt_ex1_c_frac_zero <= ex1_c_frac_zero ;--output-- + f_fmt_ex1_c_frac_msb <= ex1_c_frac_msb ;--output-- + + f_fmt_ex1_b_zero <= ex1_b_zero ;--output-- + f_fmt_ex1_b_expo_max <= ex1_bop_valid and ex1_b_expo_max ;--output-- + f_fmt_ex1_b_frac_zero <= ex1_b_frac_zero ;--output-- + f_fmt_ex1_b_frac_msb <= ex1_b_frac_msb ;--output-- + f_fmt_ex1_b_imp <= ex1_b_frac(0) ;--output-- + + f_fmt_ex1_prod_zero <= ex1_a_zero or ex1_c_zero ;--output--ex1_bop_valid and + + --#=-------------------------------------------------- + --#= NAN mux + --#=-------------------------------------------------- + -- need to zero out sp bits that were left on so we could do a parity check. + + ex1_a_nan <= ex1_a_expo_max and not ex1_a_frac_zero and not ex1_from_integer and not ex1_sgncpy and not ex1_uc_end_nspec and not ex1_uc_mid and not f_dcd_ex1_perr_fsel_ovrd; + ex1_c_nan <= ex1_c_expo_max and not ex1_c_frac_zero and not ex1_from_integer and not ex1_fsel and not ex1_uc_end_nspec and not ex1_uc_mid; + ex1_b_nan <= ex1_b_expo_max and not ex1_b_frac_zero and not ex1_from_integer and not ex1_fsel and not ex1_uc_end_nspec and not ex1_uc_mid; + + ex1_nan_pass <= ex1_a_nan or ex1_c_nan or ex1_b_nan ; + ex1_pass_sel <= ex1_nan_pass or ex1_fsel or ex1_force_pass ; + + f_fmt_ex1_pass_sel <= ex1_pass_sel ;--output-- + + ex1_fsel_cif <= ( ex1_fsel and not ex1_a_sign and not f_dcd_ex1_perr_fsel_ovrd ) or -- a positive + ( ex1_fsel and ex1_a_zero and not f_dcd_ex1_perr_fsel_ovrd ) or -- a zero + ( f_dcd_ex1_perr_force_c and f_dcd_ex1_perr_fsel_ovrd ); -- Parity error recover bypass + -- ( ex1_fsel and ex1_a_frac_zero ); -- a zero + + ex1_fsel_bsel <= ex1_fsel and ( ex1_a_nan or not ex1_fsel_cif ); + + ex1_mux_a_sel <= ex1_a_nan and not ex1_fsel; + + ex1_mux_c_sel <= + ( not ex1_a_nan and not ex1_b_nan and ex1_c_nan ) or + ( ex1_a_nan and not ex1_fsel ) or + ( not ex1_a_nan and ex1_fsel and ex1_fsel_cif ); + + ex1_pass_sign_ac <= + ( ex1_mux_a_sel and ex1_a_sign ) or + ( not ex1_mux_a_sel and ex1_c_sign ) ; + ex1_pass_sign <= + ( ex1_mux_c_sel and ex1_pass_sign_ac ) or + ( not ex1_mux_c_sel and ex1_b_sign ) ; + + + ex1_a_frac_chop(0 to 23) <= ex1_a_frac(0 to 23); + ex1_c_frac_chop(0 to 23) <= ex1_c_frac(0 to 23); + ex1_b_frac_chop(0 to 23) <= ex1_b_frac(0 to 23); + + ex1_a_frac_chop(24 to 52) <= ex1_a_frac(24 to 52); + ex1_c_frac_chop(24 to 52) <= ex1_c_frac(24 to 52); + ex1_b_frac_chop(24 to 52) <= ex1_b_frac(24 to 52); + + + ex1_a_expo_ltx381_sp <= ex1_a_expo_ltx381 and ex1_a_sp ; + ex1_c_expo_ltx381_sp <= ex1_c_expo_ltx381 and ex1_c_sp ; + ex1_b_expo_ltx381_sp <= ex1_b_expo_ltx381 and ex1_b_sp ; + + ex1_a_expo_ltx381 <= + ( not ex1_a_expo_b(1) ) or -- negative + ( ex1_a_expo_00xx_xxxx_xxxx and not ex1_a_expo_xx11_1xxx_xxxx ) or -- lt x380 + ( ex1_a_expo_00xx_xxxx_xxxx and ex1_a_expo_xx11_1xxx_xxxx and ex1_a_expo_xxxx_x000_0000 ) ;-- eq x380 + + + ex1_a_expo_00xx_xxxx_xxxx <= ex1_a_expo_b(2) and + ex1_a_expo_b(3) ; + ex1_a_expo_xx11_1xxx_xxxx <= not ex1_a_expo_b(4) and + not ex1_a_expo_b(5) and + not ex1_a_expo_b(6) ; + ex1_a_expo_xxxx_x000_0000 <= ex1_a_expo_b(7) and + ex1_a_expo_b(8) and + ex1_a_expo_b(9) and + ex1_a_expo_b(10) and + ex1_a_expo_b(11) and + ex1_a_expo_b(12) and + ex1_a_expo_b(13) ; + + ex1_c_expo_ltx381 <= + ( not ex1_c_expo_b(1) ) or -- negative + ( ex1_c_expo_00xx_xxxx_xxxx and not ex1_c_expo_xx11_1xxx_xxxx ) or -- lt x380 + ( ex1_c_expo_00xx_xxxx_xxxx and ex1_c_expo_xx11_1xxx_xxxx and ex1_c_expo_xxxx_x000_0000 ) ;-- eq x380 + + + ex1_c_expo_00xx_xxxx_xxxx <= ex1_c_expo_b(2) and + ex1_c_expo_b(3) ; + ex1_c_expo_xx11_1xxx_xxxx <= not ex1_c_expo_b(4) and + not ex1_c_expo_b(5) and + not ex1_c_expo_b(6) ; + ex1_c_expo_xxxx_x000_0000 <= ex1_c_expo_b(7) and + ex1_c_expo_b(8) and + ex1_c_expo_b(9) and + ex1_c_expo_b(10) and + ex1_c_expo_b(11) and + ex1_c_expo_b(12) and + ex1_c_expo_b(13) ; + + + ex1_b_expo_ltx381 <= + ( not ex1_b_expo_b(1) ) or -- negative + ( ex1_b_expo_00xx_xxxx_xxxx and not ex1_b_expo_xx11_1xxx_xxxx ) or -- lt x380 + ( ex1_b_expo_00xx_xxxx_xxxx and ex1_b_expo_xx11_1xxx_xxxx and ex1_b_expo_xxxx_x000_0000 ) ;-- eq x380 + + + ex1_b_expo_00xx_xxxx_xxxx <= ex1_b_expo_b(2) and + ex1_b_expo_b(3) ; + ex1_b_expo_xx11_1xxx_xxxx <= not ex1_b_expo_b(4) and + not ex1_b_expo_b(5) and + not ex1_b_expo_b(6) ; + ex1_b_expo_xxxx_x000_0000 <= ex1_b_expo_b(7) and + ex1_b_expo_b(8) and + ex1_b_expo_b(9) and + ex1_b_expo_b(10) and + ex1_b_expo_b(11) and + ex1_b_expo_b(12) and + ex1_b_expo_b(13) ; + + ex1_pass_frac_ac(0 to 52) <= + ( (0 to 52 => ex1_mux_a_sel) and ex1_a_frac_chop(0 to 52) ) or + ( (0 to 52 => not ex1_mux_a_sel) and ex1_c_frac_chop(0 to 52) ); + ex1_pass_frac(0 to 52) <= + ( (0 to 52 => ex1_mux_c_sel) and ex1_pass_frac_ac(0 to 52) ) or + ( (0 to 52 => not ex1_mux_c_sel) and ex1_b_frac_chop(0 to 52) ); + + + -- last iteration of divide = X * 1, check if x is a denorm + ex1_uc_a_expo_den <= + ( not ex1_a_expo_b(1) ) or -- expo is neg + ( ex1_a_expo_b(2) and -- expo is all zeroes + ex1_a_expo_b(3) and + ex1_a_expo_b(4) and + ex1_a_expo_b(5) and + ex1_a_expo_b(6) and + ex1_a_expo_b(7) and + ex1_a_expo_b(8) and + ex1_a_expo_b(9) and + ex1_a_expo_b(10) and + ex1_a_expo_b(11) and + ex1_a_expo_b(12) and + ex1_a_expo_b(13) ); + + + + -- for SP we also need to add denorms <= x381 + ex1_uc_a_expo_den_sp <= ex1_a_expo_ltx381 ; + + ex1_a_sp_inf_alias_tail <= + not ex1_a_expo_b(7) and + not ex1_a_expo_b(8) and + not ex1_a_expo_b(9) and + not ex1_a_expo_b(10) and + not ex1_a_expo_b(11) and + not ex1_a_expo_b(12) and + not ex1_a_expo_b(13) ; + ex1_c_sp_inf_alias_tail <= + not ex1_c_expo_b(7) and + not ex1_c_expo_b(8) and + not ex1_c_expo_b(9) and + not ex1_c_expo_b(10) and + not ex1_c_expo_b(11) and + not ex1_c_expo_b(12) and + not ex1_c_expo_b(13) ; + ex1_b_sp_inf_alias_tail <= + not ex1_b_expo_b(7) and + not ex1_b_expo_b(8) and + not ex1_b_expo_b(9) and + not ex1_b_expo_b(10) and + not ex1_b_expo_b(11) and + not ex1_b_expo_b(12) and + not ex1_b_expo_b(13) ; + + + ex1_a_sp_expo_ok_1 <= -- 1024:1151 1151=1024+127 (exclude 1151) + ex1_a_expo_b(1) and -- sign + ex1_a_expo_b(2) and -- 2048 + not ex1_a_expo_b(3) and -- 1024 + ex1_a_expo_b(4) and -- 512 + ex1_a_expo_b(5) and -- 256 + ex1_a_expo_b(6) and -- 128; + not ex1_a_sp_inf_alias_tail ; + + ex1_c_sp_expo_ok_1 <= -- 1024:1151 1151=1024+127 (exclude 1151) + ex1_c_expo_b(1) and -- sign + ex1_c_expo_b(2) and -- 2048 + not ex1_c_expo_b(3) and -- 1024 + ex1_c_expo_b(4) and -- 512 + ex1_c_expo_b(5) and -- 256 + ex1_c_expo_b(6) and -- 128; + not ex1_c_sp_inf_alias_tail ; + + ex1_b_sp_expo_ok_1 <= -- 1024:1151 1151=1024+127 (exclude 1151) + ex1_b_expo_b(1) and -- sign + ex1_b_expo_b(2) and -- 2048 + not ex1_b_expo_b(3) and -- 1024 + ex1_b_expo_b(4) and -- 512 + ex1_b_expo_b(5) and -- 256 + ex1_b_expo_b(6) and -- 128; + not ex1_b_sp_inf_alias_tail ; + + ex1_a_sp_expo_ok_2 <= -- 897:1023 + -- 895 0_0011_0111_1111 00x00000_00000000_00000000 <2> + -- 894 0_0011_0111_1110 000x0000_00000000_00000000 <3> + -- 893 0_0011_0111_1101 0000x000_00000000_00000000 <4> + -- 892 0_0011_0111_1100 00000x00_00000000_00000000 <5> + -- 891 0_0011_0111_1011 000000x0_00000000_00000000 <6> + -- 890 0_0011_0111_1010 0000000x_00000000_00000000 <7> + -- 889 0_0011_0111_1001 00000000_x0000000_00000000 <8> + -- 888 0_0011_0111_1000 00000000_0x000000_00000000 <9> + -- 887 0_0011_0111_0111 00000000_00x00000_00000000 <10> + -- 886 0_0011_0111_0110 00000000_000x0000_00000000 <11> + -- 885 0_0011_0111_0101 00000000_0000x000_00000000 <12> + -- 884 0_0011_0111_0100 00000000_00000x00_00000000 <13> + -- 883 0_0011_0111_0011 00000000_000000x0_00000000 <14> + -- 882 0_0011_0111_0010 00000000_0000000x_00000000 <15> + -- 881 0_0011_0111_0001 00000000_00000000_x0000000 <16> + -- 880 0_0011_0111_0000 00000000_00000000_0x000000 <17> + -- 879 0_0011_0110_1111 00000000_00000000_00x00000 <18> + -- 878 0_0011_0110_1110 00000000_00000000_000x0000 <19> + -- 877 0_0011_0110_1101 00000000_00000000_0000x000 <20> + -- 876 0_0011_0110_1100 00000000_00000000_00000x00 <21> + -- 875 0_0011_0110_1011 00000000_00000000_000000x0 <22> + -- x37A 874 0_0011_0110_1010 00000000_00000000_0000000x <23> + + + + + f_fmt_ex1_sp_invalid <= + ( not ex1_a_sp_expo_ok_1 and + not ex1_a_sp_expo_ok_2 and + not ex1_a_sp_expo_ok_3 and + not ex1_a_sp_expo_ok_4 and + not ex1_a_expo_max and + not ex1_a_zero_x ) or + ( not ex1_c_sp_expo_ok_1 and + not ex1_c_sp_expo_ok_2 and + not ex1_c_sp_expo_ok_3 and + not ex1_c_sp_expo_ok_4 and + not ex1_c_expo_max and + not ex1_c_zero_x ) or + ( not ex1_b_sp_expo_ok_1 and + not ex1_b_sp_expo_ok_2 and + not ex1_b_sp_expo_ok_3 and + not ex1_b_sp_expo_ok_4 and + not ex1_b_expo_max and + not ex1_b_zero_x ) ; + + + + ex1_a_party(0) <= ex1_a_sign xor ex1_a_expo(2) xor ex1_a_expo(3) xor ex1_a_expo(4) xor ex1_a_expo(5) xor + ex1_a_expo(6) xor ex1_a_expo(7) xor ex1_a_expo(8) xor ex1_a_expo(9) ; + ex1_a_party(1) <= ex1_a_expo(10) xor ex1_a_expo(11) xor ex1_a_expo(12) xor ex1_a_expo(13) xor ex1_a_frac(0) xor + ex1_a_frac(1) xor ex1_a_frac(2) xor ex1_a_frac(3) xor ex1_a_frac(4) ; + ex1_a_party(2) <= ex1_a_frac(5) xor ex1_a_frac(6) xor ex1_a_frac(7) xor ex1_a_frac(8) xor + ex1_a_frac(9) xor ex1_a_frac(10) xor ex1_a_frac(11) xor ex1_a_frac(12) ; + ex1_a_party(3) <= ex1_a_frac(13) xor ex1_a_frac(14) xor ex1_a_frac(15) xor ex1_a_frac(16) xor + ex1_a_frac(17) xor ex1_a_frac(18) xor ex1_a_frac(19) xor ex1_a_frac(20) ; + ex1_a_party(4) <= ex1_a_frac(21) xor ex1_a_frac(22) xor ex1_a_frac(23) xor ex1_a_frac(24) xor + ex1_a_frac(25) xor ex1_a_frac(26) xor ex1_a_frac(27) xor ex1_a_frac(28) ; + ex1_a_party(5) <= ex1_a_frac(29) xor ex1_a_frac(30) xor ex1_a_frac(31) xor ex1_a_frac(32) xor + ex1_a_frac(33) xor ex1_a_frac(34) xor ex1_a_frac(35) xor ex1_a_frac(36) ; + ex1_a_party(6) <= ex1_a_frac(37) xor ex1_a_frac(38) xor ex1_a_frac(39) xor ex1_a_frac(40) xor + ex1_a_frac(41) xor ex1_a_frac(42) xor ex1_a_frac(43) xor ex1_a_frac(44) ; + ex1_a_party(7) <= ex1_a_frac(45) xor ex1_a_frac(46) xor ex1_a_frac(47) xor ex1_a_frac(48) xor + ex1_a_frac(49) xor ex1_a_frac(50) xor ex1_a_frac(51) xor ex1_a_frac(52) ; + + ex1_c_party(0) <= ex1_c_sign xor ex1_c_expo(2) xor ex1_c_expo(3) xor ex1_c_expo(4) xor ex1_c_expo(5) xor + ex1_c_expo(6) xor ex1_c_expo(7) xor ex1_c_expo(8) xor ex1_c_expo(9) ; + ex1_c_party(1) <= ex1_c_expo(10) xor ex1_c_expo(11) xor ex1_c_expo(12) xor ex1_c_expo(13) xor ex1_c_frac(0) xor + ex1_c_frac(1) xor ex1_c_frac(2) xor ex1_c_frac(3) xor ex1_c_frac(4) ; + ex1_c_party(2) <= ex1_c_frac(5) xor ex1_c_frac(6) xor ex1_c_frac(7) xor ex1_c_frac(8) xor + ex1_c_frac(9) xor ex1_c_frac(10) xor ex1_c_frac(11) xor ex1_c_frac(12) ; + ex1_c_party(3) <= ex1_c_frac(13) xor ex1_c_frac(14) xor ex1_c_frac(15) xor ex1_c_frac(16) xor + ex1_c_frac(17) xor ex1_c_frac(18) xor ex1_c_frac(19) xor ex1_c_frac(20) ; + ex1_c_party(4) <= ex1_c_frac(21) xor ex1_c_frac(22) xor ex1_c_frac(23) xor ex1_c_frac(24) xor + ex1_c_frac(25) xor ex1_c_frac(26) xor ex1_c_frac(27) xor ex1_c_frac(28) ; + ex1_c_party(5) <= ex1_c_frac(29) xor ex1_c_frac(30) xor ex1_c_frac(31) xor ex1_c_frac(32) xor + ex1_c_frac(33) xor ex1_c_frac(34) xor ex1_c_frac(35) xor ex1_c_frac(36) ; + ex1_c_party(6) <= ex1_c_frac(37) xor ex1_c_frac(38) xor ex1_c_frac(39) xor ex1_c_frac(40) xor + ex1_c_frac(41) xor ex1_c_frac(42) xor ex1_c_frac(43) xor ex1_c_frac(44) ; + ex1_c_party(7) <= ex1_c_frac(45) xor ex1_c_frac(46) xor ex1_c_frac(47) xor ex1_c_frac(48) xor + ex1_c_frac(49) xor ex1_c_frac(50) xor ex1_c_frac(51) xor ex1_c_frac(52) ; + + + ex1_b_party(0) <= ex1_b_sign xor ex1_b_expo(2) xor ex1_b_expo(3) xor ex1_b_expo(4) xor ex1_b_expo(5) xor + ex1_b_expo(6) xor ex1_b_expo(7) xor ex1_b_expo(8) xor ex1_b_expo(9) ; + ex1_b_party(1) <= ex1_b_expo(10) xor ex1_b_expo(11) xor ex1_b_expo(12) xor ex1_b_expo(13) xor ex1_b_frac(0) xor + ex1_b_frac(1) xor ex1_b_frac(2) xor ex1_b_frac(3) xor ex1_b_frac(4) ; + ex1_b_party(2) <= ex1_b_frac(5) xor ex1_b_frac(6) xor ex1_b_frac(7) xor ex1_b_frac(8) xor + ex1_b_frac(9) xor ex1_b_frac(10) xor ex1_b_frac(11) xor ex1_b_frac(12) ; + ex1_b_party(3) <= ex1_b_frac(13) xor ex1_b_frac(14) xor ex1_b_frac(15) xor ex1_b_frac(16) xor + ex1_b_frac(17) xor ex1_b_frac(18) xor ex1_b_frac(19) xor ex1_b_frac(20) ; + ex1_b_party(4) <= ex1_b_frac(21) xor ex1_b_frac(22) xor ex1_b_frac(23) xor ex1_b_frac(24) xor + ex1_b_frac(25) xor ex1_b_frac(26) xor ex1_b_frac(27) xor ex1_b_frac(28) ; + ex1_b_party(5) <= ex1_b_frac(29) xor ex1_b_frac(30) xor ex1_b_frac(31) xor ex1_b_frac(32) xor + ex1_b_frac(33) xor ex1_b_frac(34) xor ex1_b_frac(35) xor ex1_b_frac(36) ; + ex1_b_party(6) <= ex1_b_frac(37) xor ex1_b_frac(38) xor ex1_b_frac(39) xor ex1_b_frac(40) xor + ex1_b_frac(41) xor ex1_b_frac(42) xor ex1_b_frac(43) xor ex1_b_frac(44) ; + ex1_b_party(7) <= ex1_b_frac(45) xor ex1_b_frac(46) xor ex1_b_frac(47) xor ex1_b_frac(48) xor + ex1_b_frac(49) xor ex1_b_frac(50) xor ex1_b_frac(51) xor ex1_b_frac(52) ; + + + ex1_a_party_chick <= (ex1_a_party(0) xor f_fpr_ex1_a_par(0) ) or + (ex1_a_party(1) xor f_fpr_ex1_a_par(1) ) or + (ex1_a_party(2) xor f_fpr_ex1_a_par(2) ) or + (ex1_a_party(3) xor f_fpr_ex1_a_par(3) ) or + (ex1_a_party(4) xor f_fpr_ex1_a_par(4) ) or + (ex1_a_party(5) xor f_fpr_ex1_a_par(5) ) or + (ex1_a_party(6) xor f_fpr_ex1_a_par(6) ) or + (ex1_a_party(7) xor f_fpr_ex1_a_par(7) ) ; + + ex1_c_party_chick <= (ex1_c_party(0) xor f_fpr_ex1_c_par(0) ) or + (ex1_c_party(1) xor f_fpr_ex1_c_par(1) ) or + (ex1_c_party(2) xor f_fpr_ex1_c_par(2) ) or + (ex1_c_party(3) xor f_fpr_ex1_c_par(3) ) or + (ex1_c_party(4) xor f_fpr_ex1_c_par(4) ) or + (ex1_c_party(5) xor f_fpr_ex1_c_par(5) ) or + (ex1_c_party(6) xor f_fpr_ex1_c_par(6) ) or + (ex1_c_party(7) xor f_fpr_ex1_c_par(7) ) ; + + ex1_b_party_chick <= (ex1_b_party(0) xor f_fpr_ex1_b_par(0) ) or + (ex1_b_party(1) xor f_fpr_ex1_b_par(1) ) or + (ex1_b_party(2) xor f_fpr_ex1_b_par(2) ) or + (ex1_b_party(3) xor f_fpr_ex1_b_par(3) ) or + (ex1_b_party(4) xor f_fpr_ex1_b_par(4) ) or + (ex1_b_party(5) xor f_fpr_ex1_b_par(5) ) or + (ex1_b_party(6) xor f_fpr_ex1_b_par(6) ) or + (ex1_b_party(7) xor f_fpr_ex1_b_par(7) ) ; + + + +-- --------------------------------------------------------------------- +-- more logic for ftdiv ftsqrt +-- --------------------------------------------------------------------- + + + ex1_be_den <= + ( ex1_b_expo(1) ) or -- it is negative + ( not ex1_b_expo(2) and -- it is x000 ... as oppossed to x001 + not ex1_b_expo(3) and -- it is x000 ... as oppossed to x001 + not ex1_b_expo(4) and -- it is x000 ... as oppossed to x001 + not ex1_b_expo(5) and -- it is x000 ... as oppossed to x001 + not ex1_b_expo(6) and -- it is x000 ... as oppossed to x001 + not ex1_b_expo(7) and -- it is x000 ... as oppossed to x001 + not ex1_b_expo(8) and -- it is x000 ... as oppossed to x001 + not ex1_b_expo(9) and -- it is x000 ... as oppossed to x001 + not ex1_b_expo(10) and -- it is x000 ... as oppossed to x001 + not ex1_b_expo(11) and -- it is x000 ... as oppossed to x001 + not ex1_b_expo(12) and -- it is x000 ... as oppossed to x001 + not ex1_b_expo(13) ); -- it is x000 ... as oppossed to x001 + + ------------------------------------------------------ + -- x LE 53 == !(x ge 54) + -- 1 - 2345 - 6789 - ABCD + -- 54 0 0000 0011 0110 + -- x_le_53 <= not x_ge_54 ; + -- x_ge_54 =( ![1] * [2+3+4+5+6+7] ) + + -- ( ![1] * [8][9][A] ) + + -- ( ![1] * [8][9][B][C] ); + ------------------------------------------------------ + + + ex1_ae_234567 <= ex1_a_expo(2) or ex1_a_expo(3) or ex1_a_expo(4) or + ex1_a_expo(5) or ex1_a_expo(6) or ex1_a_expo(7) ; + ex1_ae_89 <= ex1_a_expo(8) and ex1_a_expo(9) ; + ex1_ae_abc <= ex1_a_expo(10) or (ex1_a_expo(11) and ex1_a_expo(12) ) ; + + ex1_ae_ge_54 <= + (not ex1_a_expo(1) and ex1_ae_234567 ) or + (not ex1_a_expo(1) and ex1_ae_89 and ex1_ae_abc ) ; + + ex1_be_234567 <= ex1_b_expo(2) or ex1_b_expo(3) or ex1_b_expo(4) or + ex1_b_expo(5) or ex1_b_expo(6) or ex1_b_expo(7) ; + ex1_be_89 <= ex1_b_expo(8) and ex1_b_expo(9) ; + ex1_be_abc <= ex1_b_expo(10) or (ex1_b_expo(11) and ex1_b_expo(12) ) ; + + ex1_be_ge_54 <= + (not ex1_b_expo(1) and ex1_be_234567 ) or + (not ex1_b_expo(1) and ex1_be_89 and ex1_be_abc ) ; + + ------------------------------------------------------ + -- x le 1 == !(x ge 2) -1022+1023 = 1 + -- x ge 2044 1021+1023 = 2044 + -- + -- + -- 1 - 2345 - 6789 - ABCD + -- 2 0 0000 0000 0010 + -- 2044 0 1111 1111 1100 + ------------------------------------------------------ + + ex1_be_or_23456789abc <= + ex1_b_expo(2) or + ex1_b_expo(3) or + ex1_b_expo(4) or + ex1_b_expo(5) or + ex1_b_expo(6) or + ex1_b_expo(7) or + ex1_b_expo(8) or + ex1_b_expo(9) or + ex1_b_expo(10) or + ex1_b_expo(11) or + ex1_b_expo(12) ; + + ex1_be_and_3456789ab <= + ex1_b_expo(3) and + ex1_b_expo(4) and + ex1_b_expo(5) and + ex1_b_expo(6) and + ex1_b_expo(7) and + ex1_b_expo(8) and + ex1_b_expo(9) and + ex1_b_expo(10) and + ex1_b_expo(11) ; + + ex1_be_ge_2 <= not ex1_b_expo(1) and ex1_be_or_23456789abc ; + ex1_be_ge_2044 <= ( not ex1_b_expo(1) and ex1_be_and_3456789ab ) or + ( not ex1_b_expo(1) and ex1_b_expo(2) ) ; + + + ------------------------------------------------------ + -- ae - be >= 1023 (same for biased, unbiased) !! + -- ae - be <= -1021 ..... !(ae - be >= -1020) + -- + -- 1 - 2345 - 6789 - ABCD + -- 1023 0 0011 1111 1111 + -- 1022 0 0011 1111 1110 + -- -1022 1 1100 0000 0010 + -- (note ... a,b will always both be positive ) ... 1,2 ==0 + -- + -- ae - be - 1023 >= 0 , ae + !be + 1 - 1023 , (ae + !be -1022 >= 0) ... co = 1 <= x + -- !(ae - be +1022 >= 0) , !(ae + !be + 1 + 1020) , !(ae + !be +1021 >= 0) ... co = 0 <= y + + + + ex1_aembex_car_b( 0) <= not( ex1_a_expo( 1) or ex1_b_expo_b( 1) ) ; --1 + ex1_aembex_car_b( 1) <= not( ex1_a_expo( 2) or ex1_b_expo_b( 2) ) ; --1 + ex1_aembex_car_b( 2) <= not( ex1_a_expo( 3) or ex1_b_expo_b( 3) ) ; --1 + ex1_aembex_car_b( 3) <= not( ex1_a_expo( 4) and ex1_b_expo_b( 4) ) ; --0 + ex1_aembex_car_b( 4) <= not( ex1_a_expo( 5) and ex1_b_expo_b( 5) ) ; --0 + ex1_aembex_car_b( 5) <= not( ex1_a_expo( 6) and ex1_b_expo_b( 6) ) ; --0 + ex1_aembex_car_b( 6) <= not( ex1_a_expo( 7) and ex1_b_expo_b( 7) ) ; --0 + ex1_aembex_car_b( 7) <= not( ex1_a_expo( 8) and ex1_b_expo_b( 8) ) ; --0 + ex1_aembex_car_b( 8) <= not( ex1_a_expo( 9) and ex1_b_expo_b( 9) ) ; --0 + ex1_aembex_car_b( 9) <= not( ex1_a_expo(10) and ex1_b_expo_b(10) ) ; --0 + ex1_aembex_car_b(10) <= not( ex1_a_expo(11) and ex1_b_expo_b(11) ) ; --0 + ex1_aembex_car_b(11) <= not( ex1_a_expo(12) or ex1_b_expo_b(12) ) ; --1 + ex1_aembex_car_b(12) <= not( ex1_a_expo(13) and ex1_b_expo_b(13) ) ; --0 + + ex1_aembex_sum_b( 1) <= ( ex1_a_expo( 1) xor ex1_b_expo_b( 1) ) ; --1 + ex1_aembex_sum_b( 2) <= ( ex1_a_expo( 2) xor ex1_b_expo_b( 2) ) ; --1 + ex1_aembex_sum_b( 3) <= ( ex1_a_expo( 3) xor ex1_b_expo_b( 3) ) ; --1 + ex1_aembex_sum_b( 4) <= not( ex1_a_expo( 4) xor ex1_b_expo_b( 4) ) ; --0 + ex1_aembex_sum_b( 5) <= not( ex1_a_expo( 5) xor ex1_b_expo_b( 5) ) ; --0 + ex1_aembex_sum_b( 6) <= not( ex1_a_expo( 6) xor ex1_b_expo_b( 6) ) ; --0 + ex1_aembex_sum_b( 7) <= not( ex1_a_expo( 7) xor ex1_b_expo_b( 7) ) ; --0 + ex1_aembex_sum_b( 8) <= not( ex1_a_expo( 8) xor ex1_b_expo_b( 8) ) ; --0 + ex1_aembex_sum_b( 9) <= not( ex1_a_expo( 9) xor ex1_b_expo_b( 9) ) ; --0 + ex1_aembex_sum_b(10) <= not( ex1_a_expo(10) xor ex1_b_expo_b(10) ) ; --0 + ex1_aembex_sum_b(11) <= not( ex1_a_expo(11) xor ex1_b_expo_b(11) ) ; --0 + ex1_aembex_sum_b(12) <= ( ex1_a_expo(12) xor ex1_b_expo_b(12) ) ; --1 + ex1_aembex_sum_b(13) <= not( ex1_a_expo(13) xor ex1_b_expo_b(13) ) ; --0 + + -- want to know if the final sign is negative or positive + + ex1_aembex_sgn <= ex1_aembex_sum_b(1) xor ex1_aembex_car_b(1) ; + + ex1_aembex_g1(2 to 12) <= not(ex1_aembex_sum_b(2 to 12) or ex1_aembex_car_b(2 to 12) ); + ex1_aembex_t1(2 to 12) <= not(ex1_aembex_sum_b(2 to 12) and ex1_aembex_car_b(2 to 12) ); + + + ex1_aembex_g2(0) <= ex1_aembex_g1( 2) or ( ex1_aembex_t1( 2) and ex1_aembex_g1( 3) ); + ex1_aembex_g2(1) <= ex1_aembex_g1( 4) or ( ex1_aembex_t1( 4) and ex1_aembex_g1( 5) ); + ex1_aembex_g2(2) <= ex1_aembex_g1( 6) or ( ex1_aembex_t1( 6) and ex1_aembex_g1( 7) ); + ex1_aembex_g2(3) <= ex1_aembex_g1( 8) or ( ex1_aembex_t1( 8) and ex1_aembex_g1( 9) ); + ex1_aembex_g2(4) <= ex1_aembex_g1(10) or ( ex1_aembex_t1(10) and ex1_aembex_g1(11) ); + ex1_aembex_g2(5) <= ex1_aembex_g1(12) ; + + ex1_aembex_t2(0) <= ( ex1_aembex_t1( 2) and ex1_aembex_t1( 3) ); + ex1_aembex_t2(1) <= ( ex1_aembex_t1( 4) and ex1_aembex_t1( 5) ); + ex1_aembex_t2(2) <= ( ex1_aembex_t1( 6) and ex1_aembex_t1( 7) ); + ex1_aembex_t2(3) <= ( ex1_aembex_t1( 8) and ex1_aembex_t1( 9) ); + ex1_aembex_t2(4) <= ( ex1_aembex_t1(10) and ex1_aembex_t1(11) ); + + + ex1_aembex_g4(0) <= ex1_aembex_g2( 0) or ( ex1_aembex_t2( 0) and ex1_aembex_g2( 1) ); + ex1_aembex_g4(1) <= ex1_aembex_g2( 2) or ( ex1_aembex_t2( 2) and ex1_aembex_g2( 3) ); + ex1_aembex_g4(2) <= ex1_aembex_g2( 4) or ( ex1_aembex_t2( 4) and ex1_aembex_g2( 5) ); + + ex1_aembex_t4(0) <= ( ex1_aembex_t2( 0) and ex1_aembex_t2( 1) ); + ex1_aembex_t4(1) <= ( ex1_aembex_t2( 2) and ex1_aembex_t2( 3) ); + + + ---------------------------------------------- + + ex1_aembey_car_b( 0) <= not( ex1_a_expo( 1) and ex1_b_expo_b( 1) ) ; --0 + ex1_aembey_car_b( 1) <= not( ex1_a_expo( 2) and ex1_b_expo_b( 2) ) ; --0 + ex1_aembey_car_b( 2) <= not( ex1_a_expo( 3) and ex1_b_expo_b( 3) ) ; --0 + ex1_aembey_car_b( 3) <= not( ex1_a_expo( 4) or ex1_b_expo_b( 4) ) ; --1 + ex1_aembey_car_b( 4) <= not( ex1_a_expo( 5) or ex1_b_expo_b( 5) ) ; --1 + ex1_aembey_car_b( 5) <= not( ex1_a_expo( 6) or ex1_b_expo_b( 6) ) ; --1 + ex1_aembey_car_b( 6) <= not( ex1_a_expo( 7) or ex1_b_expo_b( 7) ) ; --1 + ex1_aembey_car_b( 7) <= not( ex1_a_expo( 8) or ex1_b_expo_b( 8) ) ; --1 + ex1_aembey_car_b( 8) <= not( ex1_a_expo( 9) or ex1_b_expo_b( 9) ) ; --1 + ex1_aembey_car_b( 9) <= not( ex1_a_expo(10) or ex1_b_expo_b(10) ) ; --1 + ex1_aembey_car_b(10) <= not( ex1_a_expo(11) or ex1_b_expo_b(11) ) ; --1 + ex1_aembey_car_b(11) <= not( ex1_a_expo(12) and ex1_b_expo_b(12) ) ; --0 + ex1_aembey_car_b(12) <= not( ex1_a_expo(13) or ex1_b_expo_b(13) ) ; --1 + + ex1_aembey_sum_b( 1) <= not( ex1_a_expo( 1) xor ex1_b_expo_b( 1) ) ; --0 + ex1_aembey_sum_b( 2) <= not( ex1_a_expo( 2) xor ex1_b_expo_b( 2) ) ; --0 + ex1_aembey_sum_b( 3) <= not( ex1_a_expo( 3) xor ex1_b_expo_b( 3) ) ; --0 + ex1_aembey_sum_b( 4) <= ( ex1_a_expo( 4) xor ex1_b_expo_b( 4) ) ; --1 + ex1_aembey_sum_b( 5) <= ( ex1_a_expo( 5) xor ex1_b_expo_b( 5) ) ; --1 + ex1_aembey_sum_b( 6) <= ( ex1_a_expo( 6) xor ex1_b_expo_b( 6) ) ; --1 + ex1_aembey_sum_b( 7) <= ( ex1_a_expo( 7) xor ex1_b_expo_b( 7) ) ; --1 + ex1_aembey_sum_b( 8) <= ( ex1_a_expo( 8) xor ex1_b_expo_b( 8) ) ; --1 + ex1_aembey_sum_b( 9) <= ( ex1_a_expo( 9) xor ex1_b_expo_b( 9) ) ; --1 + ex1_aembey_sum_b(10) <= ( ex1_a_expo(10) xor ex1_b_expo_b(10) ) ; --1 + ex1_aembey_sum_b(11) <= ( ex1_a_expo(11) xor ex1_b_expo_b(11) ) ; --1 + ex1_aembey_sum_b(12) <= not( ex1_a_expo(12) xor ex1_b_expo_b(12) ) ; --0 + ex1_aembey_sum_b(13) <= ( ex1_a_expo(13) xor ex1_b_expo_b(13) ) ; --1 + + -- want to know if the final sign is negative or positive + + ex1_aembey_sgn <= ex1_aembey_sum_b(1) xor ex1_aembey_car_b(1) ; + + ex1_aembey_g1(2 to 12) <= not(ex1_aembey_sum_b(2 to 12) or ex1_aembey_car_b(2 to 12) ); + ex1_aembey_t1(2 to 12) <= not(ex1_aembey_sum_b(2 to 12) and ex1_aembey_car_b(2 to 12) ); + + + ex1_aembey_g2(0) <= ex1_aembey_g1( 2) or ( ex1_aembey_t1( 2) and ex1_aembey_g1( 3) ); + ex1_aembey_g2(1) <= ex1_aembey_g1( 4) or ( ex1_aembey_t1( 4) and ex1_aembey_g1( 5) ); + ex1_aembey_g2(2) <= ex1_aembey_g1( 6) or ( ex1_aembey_t1( 6) and ex1_aembey_g1( 7) ); + ex1_aembey_g2(3) <= ex1_aembey_g1( 8) or ( ex1_aembey_t1( 8) and ex1_aembey_g1( 9) ); + ex1_aembey_g2(4) <= ex1_aembey_g1(10) or ( ex1_aembey_t1(10) and ex1_aembey_g1(11) ); + ex1_aembey_g2(5) <= ex1_aembey_g1(12) ; + + ex1_aembey_t2(0) <= ( ex1_aembey_t1( 2) and ex1_aembey_t1( 3) ); + ex1_aembey_t2(1) <= ( ex1_aembey_t1( 4) and ex1_aembey_t1( 5) ); + ex1_aembey_t2(2) <= ( ex1_aembey_t1( 6) and ex1_aembey_t1( 7) ); + ex1_aembey_t2(3) <= ( ex1_aembey_t1( 8) and ex1_aembey_t1( 9) ); + ex1_aembey_t2(4) <= ( ex1_aembey_t1(10) and ex1_aembey_t1(11) ); + + + ex1_aembey_g4(0) <= ex1_aembey_g2( 0) or ( ex1_aembey_t2( 0) and ex1_aembey_g2( 1) ); + ex1_aembey_g4(1) <= ex1_aembey_g2( 2) or ( ex1_aembey_t2( 2) and ex1_aembey_g2( 3) ); + ex1_aembey_g4(2) <= ex1_aembey_g2( 4) or ( ex1_aembey_t2( 4) and ex1_aembey_g2( 5) ); + + ex1_aembey_t4(0) <= ( ex1_aembey_t2( 0) and ex1_aembey_t2( 1) ); + ex1_aembey_t4(1) <= ( ex1_aembey_t2( 2) and ex1_aembey_t2( 3) ); + + + + + + + ------------------------------------------------------ + + ex2_pass_lat: tri_rlmreg_p generic map (width=> 80, expand_type => expand_type, ibuf => true, needs_sreset => 0) port map ( -- + forcee => forcee,--i-- tidn, + delay_lclkr => delay_lclkr(2) ,--i-- tidn, + mpw1_b => mpw1_b(2) ,--i-- tidn, + mpw2_b => mpw2_b(0) ,--i-- tidn, + vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_act, + thold_b => thold_0_b, + sg => sg_0, + scout => ex2_pass_so , + scin => ex2_pass_si , + ------------------- + din(0) => ex1_fsel_bsel , + din(1) => ex1_pass_sign , + din(2 to 54) => ex1_pass_frac(0 to 52) , + din(55) => ex1_b_den_flush, + din(56) => ex1_lu_den_recip, + din(57) => ex1_lu_den_rsqrto , + din(58) => ex1_uc_a_expo_den , + din(59) => ex1_uc_a_expo_den_sp , + din(60) => ex1_a_party_chick , + din(61) => ex1_c_party_chick , + din(62) => ex1_b_party_chick , + din(63) => ex1_ae_ge_54 , + din(64) => ex1_be_ge_54 , + din(65) => ex1_be_ge_2 , + din(66) => ex1_be_ge_2044 , + din(67) => ex1_aembex_g4(0) , + din(68) => ex1_aembex_t4(0) , + din(69) => ex1_aembex_g4(1) , + din(70) => ex1_aembex_t4(1) , + din(71) => ex1_aembex_g4(2) , + din(72) => ex1_aembey_g4(0) , + din(73) => ex1_aembey_t4(0) , + din(74) => ex1_aembey_g4(1) , + din(75) => ex1_aembey_t4(1) , + din(76) => ex1_aembey_g4(2) , + din(77) => ex1_aembex_sgn , + din(78) => ex1_aembey_sgn , + din(79) => ex1_be_den , + ------------------- + dout(0) => ex2_fsel_bsel , + dout(1) => ex2_pass_sign , + dout(2 to 54) => ex2_pass_frac (0 to 52), + dout(55) => ex2_b_den_flush , + dout(56) => ex2_lu_den_recip, + dout(57) => ex2_lu_den_rsqrto, + dout(58) => ex2_uc_a_expo_den , + dout(59) => ex2_uc_a_expo_den_sp , + dout(60) => ex2_a_party_chick , + dout(61) => ex2_c_party_chick , + dout(62) => ex2_b_party_chick , + dout(63) => ex2_ae_ge_54 , + dout(64) => ex2_be_ge_54 , + dout(65) => ex2_be_ge_2 , + dout(66) => ex2_be_ge_2044 , + dout(67) => ex2_aembex_g4(0) , + dout(68) => ex2_aembex_t4(0) , + dout(69) => ex2_aembex_g4(1) , + dout(70) => ex2_aembex_t4(1) , + dout(71) => ex2_aembex_g4(2) , + dout(72) => ex2_aembey_g4(0) , + dout(73) => ex2_aembey_t4(0) , + dout(74) => ex2_aembey_g4(1) , + dout(75) => ex2_aembey_t4(1) , + dout(76) => ex2_aembey_g4(2) , + dout(77) => ex2_aembex_sgn , + dout(78) => ex2_aembey_sgn , + dout(79) => ex2_be_den ); + + + f_mad_ex2_a_parity_check <= ex2_a_party_chick ;--output-- + f_mad_ex2_c_parity_check <= ex2_c_party_chick ;--output-- + f_mad_ex2_b_parity_check <= ex2_b_party_chick ;--output-- + + + f_mad_ex2_uc_a_expo_den <= ex2_uc_a_expo_den ; + f_mad_ex2_uc_a_expo_den_sp <= ex2_uc_a_expo_den_sp ; + f_ex2_b_den_flush <= ex2_b_den_flush ; + + f_fmt_ex2_fsel_bsel <= ex2_fsel_bsel ;--output-- + f_fmt_ex2_pass_sign <= ex2_pass_sign ;--output-- + f_fmt_ex2_pass_msb <= ex2_pass_frac(1) ;--output-- + + ex2_pass_dp( 0 to 52) <= ex2_pass_frac(0 to 52) ; + f_fmt_ex2_pass_frac(0 to 52) <= ex2_pass_dp(0 to 52) ; --output-- + + + + ex2_aembex_g8(0) <= ex2_aembex_g4(0) or ( ex2_aembex_t4(0) and ex2_aembex_g4(1) ); + ex2_aembex_g8(1) <= ex2_aembex_g4(2) ; + ex2_aembex_t8(0) <= ( ex2_aembex_t4(0) and ex2_aembex_t4(1) ); + ex2_aembex_c2 <= ex2_aembex_g8(0) or ( ex2_aembex_t8(0) and ex2_aembex_g8(1) ); + + ex2_aembey_g8(0) <= ex2_aembey_g4(0) or ( ex2_aembey_t4(0) and ex2_aembey_g4(1) ); + ex2_aembey_g8(1) <= ex2_aembey_g4(2) ; + ex2_aembey_t8(0) <= ( ex2_aembey_t4(0) and ex2_aembey_t4(1) ); + ex2_aembey_c2 <= ex2_aembey_g8(0) or ( ex2_aembey_t8(0) and ex2_aembey_g8(1) ); + + ex2_aembex_res_sgn <= ex2_aembex_c2 xor ex2_aembex_sgn ; + ex2_aembey_res_sgn <= ex2_aembey_c2 xor ex2_aembey_sgn ; + + + f_fmt_ex2_tdiv_rng_chk <= --output-- -- were the results positive or negative + ( not ex2_aembex_res_sgn ) or -- ae - be -1023 >= 0, ae + !be + 1 - 1023 set if positive + ( ex2_aembey_res_sgn ) ; -- !(ae - be +1022 >= 0) , !(ae + !be + 1 + 1020) set if negtive + + f_fmt_ex2_be_den <= ex2_be_den ; + + f_fmt_ex2_ae_ge_54 <= ex2_ae_ge_54 ;--output-- + f_fmt_ex2_be_ge_54 <= ex2_be_ge_54 ;--output-- + f_fmt_ex2_be_ge_2 <= ex2_be_ge_2 ;--output-- + f_fmt_ex2_be_ge_2044 <= ex2_be_ge_2044 ;--output-- + + + +--#=############################################################## +--# ex2 logic +--#=############################################################## + + +--#=############################################################## +--# scan string +--#=############################################################## + + + ex1_ctl_si (0 to 8) <= ex1_ctl_so (1 to 8) & f_fmt_si ; + ex2_pass_si (0 to 79) <= ex2_pass_so (1 to 79) & ex1_ctl_so (0); + act_si (0 to 6) <= act_so (1 to 6) & ex2_pass_so (0); + f_fmt_so <= act_so (0); + + + +end; -- fuq_fmt ARCHITECTURE diff --git a/rel/src/vhdl/work/fuq_fpr.vhdl b/rel/src/vhdl/work/fuq_fpr.vhdl new file mode 100644 index 0000000..cd4ffe2 --- /dev/null +++ b/rel/src/vhdl/work/fuq_fpr.vhdl @@ -0,0 +1,1541 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +--***************************************************************************** +--* +--* TITLE: F_DP_FPR +--* +--* NAME: fuq_fpr.vhdl +--* +--* DESC: This is the Floating Point Register file +--* +--***************************************************************************** + + +library IEEE,ibm; +use IEEE.STD_LOGIC_1164.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_support.all; + +library support; +use support.power_logic_pkg.all; + +library tri; use tri.tri_latches_pkg.all; + +entity fuq_fpr is +generic( + expand_type : integer := 2 ); -- 0 - ibm tech, 1 - other ); +port( + + + nclk : in clk_logic; + clkoff_b : in std_ulogic; -- tiup + act_dis : in std_ulogic; -- ??tidn?? + flush : in std_ulogic; -- ??tidn?? + delay_lclkra : in std_ulogic_vector(0 to 1); -- tidn, + delay_lclkrb : in std_ulogic_vector(6 to 7); -- tidn, + mpw1_ba : in std_ulogic_vector(0 to 1); -- tidn, + mpw1_bb : in std_ulogic_vector(6 to 7); -- tidn, + mpw2_b : in std_ulogic_vector(0 to 1); -- tidn, + abst_sl_thold_1 : in std_ulogic; + time_sl_thold_1 : in std_ulogic; + ary_nsl_thold_1 : in std_ulogic; + gptr_sl_thold_0 : in std_ulogic; + fce_1 : in std_ulogic; + thold_1 : in std_ulogic; + sg_1 : in std_ulogic; + scan_dis_dc_b : in std_ulogic; + scan_diag_dc : in std_ulogic; + lbist_en_dc : in std_ulogic; + an_ac_abist_mode_dc : in std_ulogic; + an_ac_lbist_ary_wrt_thru_dc : in std_ulogic; + f_dcd_msr_fp_act : in std_ulogic; + + iu_fu_rf0_fra_v : in std_ulogic; + iu_fu_rf0_frb_v : in std_ulogic; + iu_fu_rf0_frc_v : in std_ulogic; + iu_fu_rf0_str_v : in std_ulogic; + f_dcd_perr_sm_running : in std_ulogic; + + --bolt-on lbist + pc_fu_bolt_sl_thold_3 : in std_ulogic; + pc_fu_bo_enable_3 : in std_ulogic; + pc_fu_bo_unload : in std_ulogic; + pc_fu_bo_load : in std_ulogic; + pc_fu_bo_reset : in std_ulogic; + pc_fu_bo_shdata : in std_ulogic; + pc_fu_bo_select : in std_ulogic_vector(0 to 1); + fu_pc_bo_fail : out std_ulogic_vector(0 to 1); + fu_pc_bo_diagout : out std_ulogic_vector(0 to 1); + + -- BX scan repower + bx_fu_rp_abst_scan_out : in std_ulogic; + bx_rp_abst_scan_out : out std_ulogic; + rp_bx_abst_scan_in : in std_ulogic; + rp_fu_bx_abst_scan_in : out std_ulogic; + rp_bx_func_scan_in : in std_ulogic_vector(0 to 1); + rp_fu_bx_func_scan_in : out std_ulogic_vector(0 to 1); + bx_fu_rp_func_scan_out : in std_ulogic_vector(0 to 1); + bx_rp_func_scan_out : out std_ulogic_vector(0 to 1); + + f_fpr_si : in std_ulogic; + f_fpr_so : out std_ulogic; + f_fpr_ab_si : in std_ulogic; + f_fpr_ab_so : out std_ulogic; + time_scan_in : in std_ulogic; + time_scan_out : out std_ulogic; + gptr_scan_in : in std_ulogic; + gptr_scan_out : out std_ulogic; + vdd : inout power_logic; + gnd : inout power_logic; + -- ABIST + pc_fu_abist_di_0 : in std_ulogic_vector(0 to 3); + pc_fu_abist_di_1 : in std_ulogic_vector(0 to 3); + pc_fu_abist_ena_dc : in std_ulogic; + pc_fu_abist_grf_renb_0 : in std_ulogic; + pc_fu_abist_grf_renb_1 : in std_ulogic; + pc_fu_abist_grf_wenb_0 : in std_ulogic; + pc_fu_abist_grf_wenb_1 : in std_ulogic; + pc_fu_abist_raddr_0 : in std_ulogic_vector(0 to 9); + pc_fu_abist_raddr_1 : in std_ulogic_vector(0 to 9); + pc_fu_abist_raw_dc_b : in std_ulogic; + pc_fu_abist_waddr_0 : in std_ulogic_vector(0 to 9); + pc_fu_abist_waddr_1 : in std_ulogic_vector(0 to 9); + pc_fu_abist_wl144_comp_ena : in std_ulogic; + pc_fu_inj_regfile_parity : in std_ulogic_vector(0 to 3); + + -- Interface to IU + f_dcd_rf0_tid : in std_ulogic_vector(0 to 1); + f_dcd_rf0_fra : in std_ulogic_vector(0 to 5); + f_dcd_rf0_frb : in std_ulogic_vector(0 to 5); + f_dcd_rf0_frc : in std_ulogic_vector(0 to 5); + iu_fu_rf0_ldst_tid : in std_ulogic_vector(0 to 1); + iu_fu_rf0_ldst_tag : in std_ulogic_vector(0 to 8); + ------------------------------------------------ + f_dcd_rf0_bypsel_a_res1 : in std_ulogic; + f_dcd_rf0_bypsel_b_res1 : in std_ulogic; + f_dcd_rf0_bypsel_c_res1 : in std_ulogic; + f_dcd_rf0_bypsel_s_res1 : in std_ulogic; + f_dcd_rf0_bypsel_a_load1 : in std_ulogic; + f_dcd_rf0_bypsel_b_load1 : in std_ulogic; + f_dcd_rf0_bypsel_c_load1 : in std_ulogic; + f_dcd_rf0_bypsel_s_load1 : in std_ulogic; + ------------------------------------------------ + f_dcd_ex5_frt_tid : in std_ulogic_vector(0 to 1); + f_dcd_ex5_flush_int : in std_ulogic_vector(0 to 3); + f_dcd_ex6_frt_addr : in std_ulogic_vector(0 to 5); + f_dcd_ex6_frt_tid : in std_ulogic_vector(0 to 1); + f_dcd_ex6_frt_wen : in std_ulogic; + f_rnd_ex6_res_expo : in std_ulogic_vector (1 to 13); + f_rnd_ex6_res_frac : in std_ulogic_vector (0 to 52); + f_rnd_ex6_res_sign : in std_ulogic ; + ------------------------------------------------ + xu_fu_ex5_load_val : in std_ulogic_vector(0 to 3); + xu_fu_ex5_load_tag : in std_ulogic_vector(0 to 8); + xu_fu_ex6_load_data : in std_ulogic_vector(192 to 255); + ------------------------------------------------ + f_fpr_ex7_load_addr : out std_ulogic_vector(0 to 7); + f_fpr_ex7_load_v : out std_ulogic; + f_fpr_ex7_load_sign : out std_ulogic; + f_fpr_ex7_load_expo : out std_ulogic_vector(3 to 13); + f_fpr_ex7_load_frac : out std_ulogic_vector(0 to 52); + f_fpr_rf1_s_sign : out std_ulogic; + f_fpr_rf1_s_expo : out std_ulogic_vector(1 to 11) ; + f_fpr_rf1_s_frac : out std_ulogic_vector(0 to 52) ; + f_fpr_rf1_a_sign : out std_ulogic; + f_fpr_rf1_a_expo : out std_ulogic_vector(1 to 13) ; + f_fpr_rf1_a_frac : out std_ulogic_vector(0 to 52) ; + f_fpr_rf1_c_sign : out std_ulogic; + f_fpr_rf1_c_expo : out std_ulogic_vector(1 to 13) ; + f_fpr_rf1_c_frac : out std_ulogic_vector(0 to 52) ; + f_fpr_rf1_b_sign : out std_ulogic; + f_fpr_rf1_b_expo : out std_ulogic_vector(1 to 13) ; + f_fpr_rf1_b_frac : out std_ulogic_vector(0 to 52); + f_fpr_ex1_s_expo_extra : out std_ulogic; + f_fpr_ex1_a_par : out std_ulogic_vector(0 to 7); + f_fpr_ex1_b_par : out std_ulogic_vector(0 to 7); + f_fpr_ex1_c_par : out std_ulogic_vector(0 to 7); + f_fpr_ex1_s_par : out std_ulogic_vector(0 to 7) +); + -- synopsys translate_off + -- synopsys translate_on + +end fuq_fpr; + +architecture fuq_fpr of fuq_fpr is + + +-- ####################### SIGNALS ####################### -- +signal tilo : std_ulogic; +signal tihi : std_ulogic; + +signal thold_0 : std_ulogic; +signal thold_0_b : std_ulogic; +signal sg_0 : std_ulogic; +signal forcee : std_ulogic; +signal ab_thold_0 : std_ulogic; +signal ab_thold_0_b : std_ulogic; +signal ab_force : std_ulogic; +signal time_force : std_ulogic; +signal time_sl_thold_0 : std_ulogic; +signal time_sl_thold_0_b : std_ulogic; + +signal lcb_obs0_sg_0 : std_ulogic; +signal lcb_obs1_sg_0 : std_ulogic; +signal lcb_obs0_sl_thold_0 : std_ulogic; +signal lcb_obs1_sl_thold_0 : std_ulogic; + +signal load_tid_enc : std_ulogic_vector(0 to 1); +signal load_addr : std_ulogic_vector(0 to 7); +signal load_wen : std_ulogic; +signal ex7_load_data_raw : std_ulogic_vector(0 to 63); +signal ex7_load_sp_data_raw : std_ulogic_vector(0 to 31); +signal ex7_load_data : std_ulogic_vector(0 to 65); +signal ex6_load_val : std_ulogic_vector(0 to 3); +signal ex6_load_v : std_ulogic; +signal ex6_load_tag : std_ulogic_vector(0 to 8); +signal ex7_load_val : std_ulogic_vector(0 to 3); +signal ex7_load_tag : std_ulogic_vector(0 to 8); +signal perr_inject : std_ulogic_vector(0 to 3); +signal ex6_ld_perr_inj : std_ulogic; +signal ex7_ld_perr_inj : std_ulogic; +signal ex5_targ_perr_inj : std_ulogic; +signal ex6_targ_perr_inj : std_ulogic; + +signal load_data : std_ulogic_vector(0 to 65); +signal load_data_parity : std_ulogic_vector(0 to 7); +signal load_data_parity_inj : std_ulogic_vector(0 to 7); +signal load_sp : std_ulogic; +signal load_int : std_ulogic; +signal load_sign_ext : std_ulogic; +signal load_int_1up : std_ulogic; +signal load_dp_exp_zero : std_ulogic; +signal load_sp_exp_zero : std_ulogic; +signal load_sp_exp_ones : std_ulogic; +signal load_sp_data : std_ulogic_vector(0 to 65); +signal load_dp_data : std_ulogic_vector(0 to 65); + +signal rf0_fra_addr : std_ulogic_vector(0 to 7); +signal rf0_frb_addr : std_ulogic_vector(0 to 7); +signal rf0_frc_addr : std_ulogic_vector(0 to 7); +signal rf0_frs_addr : std_ulogic_vector(0 to 7); + +signal frt_addr : std_ulogic_vector(0 to 7); +signal frt_wen : std_ulogic; +signal frt_data_parity : std_ulogic_vector(0 to 7); + + + +signal rf1_fra : std_ulogic_vector(0 to 77); +signal rf1_frb : std_ulogic_vector(0 to 77); +signal rf1_frc : std_ulogic_vector(0 to 77); +signal rf1_frs : std_ulogic_vector(0 to 77); +signal rf1_bypsel_a_res1 : std_ulogic; +signal rf1_bypsel_b_res1 : std_ulogic; +signal rf1_bypsel_c_res1 : std_ulogic; +signal rf1_bypsel_s_res1 : std_ulogic; + +signal rf1_bypsel_a_res1_nlb : std_ulogic; +signal rf1_bypsel_b_res1_nlb : std_ulogic; +signal rf1_bypsel_c_res1_nlb : std_ulogic; +signal rf1_bypsel_s_res1_nlb : std_ulogic; +signal rf1_bypsel_a_load1_nlb : std_ulogic; +signal rf1_bypsel_b_load1_nlb : std_ulogic; +signal rf1_bypsel_c_load1_nlb : std_ulogic; +signal rf1_bypsel_s_load1_nlb : std_ulogic; + +signal rf1_a_r0e_byp_r : std_ulogic; +signal rf1_c_r1e_byp_r : std_ulogic; +signal rf1_b_r0e_byp_r : std_ulogic; +signal rf1_s_r1e_byp_r : std_ulogic; +signal r0e_sel_lbist : std_ulogic; +signal r1e_sel_lbist : std_ulogic; + +signal rf1_bypsel_a_load1 : std_ulogic; +signal rf1_bypsel_b_load1 : std_ulogic; +signal rf1_bypsel_c_load1 : std_ulogic; +signal rf1_bypsel_s_load1 : std_ulogic; +signal ex1_dcd_si, ex1_dcd_so : std_ulogic_vector(0 to 7); + +signal abist_raddr_0 : std_ulogic_vector(0 to 9); +signal abist_raddr_1 : std_ulogic_vector(0 to 9); +signal abist_waddr_0 : std_ulogic_vector(0 to 9); +signal abist_waddr_1 : std_ulogic_vector(0 to 9); +signal ab_reg_si, ab_reg_so : std_ulogic_vector(0 to 52); + +signal abist_comp_en : std_ulogic; -- when abist tested +signal r0e_abist_comp_en : std_ulogic; -- when abist tested +signal r1e_abist_comp_en : std_ulogic; -- when abist tested +signal Alcb_act_dis_dc : std_ulogic; + +signal lcb_clkoff_dc_b : std_ulogic_vector(0 to 1); + +signal Alcb_d_mode_dc : std_ulogic; + +signal Alcb_delay_lclkr_dc : std_ulogic_vector(0 to 4); -- + +signal lcb_delay_lclkr_dc : std_ulogic_vector(0 to 9); -- + +signal fce_0 : std_ulogic; +signal Alcb_mpw1_dc_b : std_ulogic_vector(0 to 4); -- +signal Alcb_mpw2_dc_b : std_ulogic; + +signal lcb_mpw1_dc_b : std_ulogic_vector(1 to 9); -- +signal lcb_mpw2_dc_b : std_ulogic; + +signal lcb_sg_0 : std_ulogic; +signal lcb_abst_sl_thold_0 : std_ulogic; +signal ary_nsl_thold_0 : std_ulogic; +signal Aclkoff_dc_b : std_ulogic; +signal Ad_mode_dc : std_ulogic; + + +signal r_scan_in_0 : std_ulogic; +signal r_scan_out_0 : std_ulogic; +signal w_scan_in_0 : std_ulogic; +signal w_scan_out_0 : std_ulogic; +signal r_scan_in_1 : std_ulogic; +signal r_scan_out_1 : std_ulogic; +signal w_scan_in_1 : std_ulogic; +signal w_scan_out_1 : std_ulogic; +signal r0e_fra_act : std_ulogic; +signal r0e_fra_en_func : std_ulogic; +signal r0e_frb_act : std_ulogic; +signal r0e_frb_en_func : std_ulogic; +signal r0e_en_abist : std_ulogic; +signal r0e_addr_abist : std_ulogic_vector(0 to 7); +signal r1e_frc_act : std_ulogic; +signal r1e_frc_en_func : std_ulogic; +signal r1e_frs_act : std_ulogic; +signal r1e_frs_en_func : std_ulogic; +signal r1e_en_abist : std_ulogic; +signal r1e_addr_abist : std_ulogic_vector(0 to 7); +signal w0e_act : std_ulogic; +signal w0e_en_func : std_ulogic; +signal w0e_en_abist : std_ulogic; +signal w0e_addr_func : std_ulogic_vector(0 to 7); +signal w0e_addr_abist : std_ulogic_vector(0 to 7); +signal w0e_data_func_f0 : std_ulogic_vector(0 to 77); +signal w0e_data_func_f1 : std_ulogic_vector(0 to 77); +signal w0e_data_abist : std_ulogic_vector(0 to 3); +signal w0l_act : std_ulogic; +signal w0l_en_func : std_ulogic; +signal w0l_en_abist : std_ulogic; +signal w0l_addr_func : std_ulogic_vector(0 to 7); +signal w0l_addr_abist : std_ulogic_vector(0 to 7); +signal w0l_data_func_f0 : std_ulogic_vector(0 to 77); +signal w0l_data_func_f1 : std_ulogic_vector(0 to 77); +signal w0l_data_abist : std_ulogic_vector(0 to 3); + +signal fra_data_out : std_ulogic_vector(0 to 77); +signal frb_data_out : std_ulogic_vector(0 to 77); +signal frc_data_out : std_ulogic_vector(0 to 77); +signal frs_data_out : std_ulogic_vector(0 to 77); +signal ex1_fra_par : std_ulogic_vector(0 to 7); +signal ex1_frb_par : std_ulogic_vector(0 to 7); +signal ex1_frc_par : std_ulogic_vector(0 to 7); +signal ex1_frs_par : std_ulogic_vector(0 to 7); +signal ex1_s_expo_extra : std_ulogic; + +signal ex7_ldat_si , ex7_ldat_so : std_ulogic_vector(0 to 63); +signal ex7_lctl_si , ex7_lctl_so : std_ulogic_vector(0 to 9); +signal ex7_ldv_si , ex7_ldv_so : std_ulogic_vector(0 to 3); +signal ex6_ldv_si , ex6_ldv_so : std_ulogic_vector(0 to 3); +signal ex6_lctl_si , ex6_lctl_so : std_ulogic_vector(0 to 13); +signal ex1_par_si , ex1_par_so : std_ulogic_vector(0 to 32); + signal ld_par3239, ld_par3239_inj, ld_par4047, ld_par4855, ld_par5663, ld_par6163, ld_par6163_inj :std_ulogic; --ld_pgen_premux-- + signal ld_par0007 , ld_par0815 , ld_par1623 , ld_par2431 :std_ulogic;--ld_pgen_premux-- + signal ld_par32_3436 , ld_par3744 , ld_par4552 , ld_par5360 :std_ulogic;--ld_pgen_premux-- + signal load_dp_nint, load_dp_int , load_sp_all1 , load_sp_nall1 :std_ulogic;--ld_pgen_premux-- + + signal xu_fu_ex5_load_val_din : std_ulogic_vector(0 to 3); + +signal lcb_bolt_sl_thold_2 : std_ulogic; +signal lcb_bolt_sl_thold_1 : std_ulogic; +signal lcb_bolt_sl_thold_0 : std_ulogic; +signal pc_bo_enable_2 : std_ulogic; + +signal SPARE_L2 : std_ulogic_vector(0 to 7); +signal spare_si, spare_so : std_ulogic_vector(0 to 7); +signal time_SPARE_L2 : std_ulogic_vector(0 to 1); +signal time_spare_si, time_spare_so : std_ulogic_vector(0 to 1); + +signal fpr_time_si,fpr_time_so : std_ulogic_vector(0 to 1); +signal obs0_scan_in,obs0_scan_out : std_ulogic_vector(0 to 1); +signal obs1_scan_in,obs1_scan_out : std_ulogic_vector(0 to 1); + +signal spare_unused : std_ulogic_vector(0 to 26); + + +signal abst_slat_d2clk : std_ulogic; +signal abst_slat_lclk : clk_logic; +signal func_slat_d2clk : std_ulogic; +signal func_slat_lclk : clk_logic; + +---------------------------------------------------------------- +begin + +------------------------------------------------------------------------ +-- Pervasive + + thold_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => thold_1, + q(0) => thold_0 ); + + sg_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => sg_1 , + q(0) => sg_0 ); + + + lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map ( + clkoff_b => clkoff_b, + thold => thold_0, + sg => sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => thold_0_b ); + + ab_thold_reg_0: tri_plat generic map (width => 4, expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => abst_sl_thold_1, + din(1) => time_sl_thold_1, + din(2) => ary_nsl_thold_1, + din(3) => fce_1, + q(0) => ab_thold_0, + q(1) => time_sl_thold_0, + q(2) => ary_nsl_thold_0, + q(3) => fce_0 ); + + ab_lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map ( + clkoff_b => clkoff_b, + thold => ab_thold_0, + sg => sg_0, + act_dis => act_dis, + forcee => ab_force, + thold_b => ab_thold_0_b ); + + time_lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map ( + clkoff_b => clkoff_b, + thold => time_sl_thold_0, + sg => sg_0, + act_dis => act_dis, + forcee => time_force, + thold_b => time_sl_thold_0_b ); + + --bolt on lbist staging + bo_thold_reg_0: tri_plat generic map (width => 4, expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => pc_fu_bolt_sl_thold_3, + din(1) => lcb_bolt_sl_thold_2, + din(2) => lcb_bolt_sl_thold_1, + din(3) => pc_fu_bo_enable_3, + q(0) => lcb_bolt_sl_thold_2, + q(1) => lcb_bolt_sl_thold_1, + q(2) => lcb_bolt_sl_thold_0, + q(3) => pc_bo_enable_2 ); + +------------------------------------------------------------------------ +-- Act Latches + + + tilo <= '0'; + tihi <= '1'; + +------------------------------------------------------------------------ +-- Load Data + + +xu_fu_ex5_load_val_din(0 to 3) <= xu_fu_ex5_load_val(0 to 3) and not f_dcd_ex5_flush_int(0 to 3); + + ex6_ldv: tri_rlmreg_p generic map (init => 0, expand_type => expand_type, width => 4) + port map (nclk => nclk, + act => tihi, + forcee => forcee, + delay_lclkr => delay_lclkrb(6), + mpw1_b => mpw1_bb(6), + mpw2_b => mpw2_b(1), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => ex6_ldv_si(0 to 3), + scout => ex6_ldv_so(0 to 3), + din(0 to 3) => xu_fu_ex5_load_val_din(0 to 3) , + dout(0 to 3) => ex6_load_val(0 to 3) ); + + ex6_lctl: tri_rlmreg_p generic map (init => 0, expand_type => expand_type, width => 14) + port map (nclk => nclk, + act => tihi, + forcee => forcee, + delay_lclkr => delay_lclkrb(6), + mpw1_b => mpw1_bb(6), + mpw2_b => mpw2_b(1), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => ex6_lctl_si(0 to 13), + scout => ex6_lctl_so(0 to 13), + din(0 to 8) => xu_fu_ex5_load_tag(0 to 8) , + din(9 to 12) => pc_fu_inj_regfile_parity(0 to 3), + din(13) => ex5_targ_perr_inj , + dout(0 to 8) => ex6_load_tag(0 to 8) , + dout(9 to 12) => perr_inject(0 to 3) , + dout(13) => ex6_targ_perr_inj ); + + ex6_load_v <= ex6_load_val(0) or ex6_load_val(1) or ex6_load_val(2) or ex6_load_val(3); + ex6_ld_perr_inj <= or_reduce(perr_inject(0 to 3) and ex6_load_val(0 to 3)); + + ex5_targ_perr_inj <= (f_dcd_ex5_frt_tid="00" and perr_inject(0)) or + (f_dcd_ex5_frt_tid="01" and perr_inject(1)) or + (f_dcd_ex5_frt_tid="10" and perr_inject(2)) or + (f_dcd_ex5_frt_tid="11" and perr_inject(3)); + + ex7_ldv: tri_rlmreg_p generic map (init => 0, expand_type => expand_type, width => 4) + port map (nclk => nclk, + act => tihi, + forcee => forcee, + delay_lclkr => delay_lclkrb(7), + mpw1_b => mpw1_bb(7), + mpw2_b => mpw2_b(1), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => ex7_ldv_si(0 to 3), + scout => ex7_ldv_so(0 to 3), + din(0 to 3) => ex6_load_val(0 to 3) , + dout(0 to 3) => ex7_load_val(0 to 3) ); + + ex7_lctl: tri_rlmreg_p generic map (init => 0, expand_type => expand_type, width => 10) + port map (nclk => nclk, + act => ex6_load_v, + forcee => forcee, + delay_lclkr => delay_lclkrb(7), + mpw1_b => mpw1_bb(7), + mpw2_b => mpw2_b(1), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => ex7_lctl_si(0 to 9), + scout => ex7_lctl_so(0 to 9), + din(0 to 8) => ex6_load_tag(0 to 8) , + din(9) => ex6_ld_perr_inj , + dout(0 to 8) => ex7_load_tag(0 to 8) , + dout(9) => ex7_ld_perr_inj ); + + ex7_ldat: tri_rlmreg_p generic map (init => 0, expand_type => expand_type, width => 64, needs_sreset => 0) + port map (nclk => nclk, + act => ex6_load_v, + forcee => forcee, + delay_lclkr => delay_lclkrb(7), + mpw1_b => mpw1_bb(7), + mpw2_b => mpw2_b(1), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => ex7_ldat_si(0 to 63), + scout => ex7_ldat_so(0 to 63), + din => xu_fu_ex6_load_data(192 to 255) , + dout => ex7_load_data_raw(0 to 63) ); + + + load_tid_enc(0) <= ex7_load_val(2) or ex7_load_val(3); + load_tid_enc(1) <= ex7_load_val(1) or ex7_load_val(3); + + load_addr(1 to 7) <= ex7_load_tag(4 to 8) & load_tid_enc(0 to 1); + + load_sp <= ex7_load_tag(0); -- bit 0 of the tag indicates that the instr was an lfs* + load_int <= ex7_load_tag(1); -- bit 1 is lfi* + load_sign_ext <= ex7_load_tag(2); -- bit 1 is lfiwax + + load_wen <= ex7_load_val(0) or ex7_load_val(1) or + ex7_load_val(2) or ex7_load_val(3) ; + +-- FPU LOADS +-- +-- Double precision (DP) loads are straight forward. +-- To get rid of the mathematical discontinuity in the ieee number system, +-- We add the implicit bit and change the zero exponent from x000 to x001. +-- This needs to be undone when data is stored. +-- +-- the spec says that Single Precision loads (SP) should be fully normalized +-- and converted to double format before storing. +-- there is not time to do that, so we take a short cut and deal with the problems +-- when the operand is used. +-- The Double precision exponent bias is 1023. +-- The Single precision exponent bias is 127. +-- The difference x380 is added to convert the exponent. +-- (actually no adder is needed) +-- x380 => "0_0011_1000_0000 +-- SP Dddd_dddd +-- if D=0 0_0011_1ddd_dddd --> {D, !D, !D, !D} +-- if D=1 0_0100_0ddd_dddd --> {D, !D, !D, !D} +-- +-- also for SP -> SP_infinity is converted to DP infinity +-- -> (0) is converted to x381 (instead of x380) and the implicit bit is added. +-- so .... there are now 2 numbers that mean zero +-- 1) (exp==x001) and (IMP_bit==0) and (FRAC==0) +-- 2) (exp==x381) and (IMP_bit==0) and (FRAC==0) +-- the only time the SP load needs correcting (prenormalization) is +-- (exp==x381) and (IMP_bit==0) and (FRAC==0) <== SP denorm can be converted to DP norm. +-- +-------------------------------------------------------------------------------------------------- +-- INPUT LOAD DATA FORMAT LdDin[0:63] : +-- +-- lfd lfs +-- [00:00] sign [00:00] sign +-- [01:11] exponent [01:08] exponent +-- [12:63] fraction [09:31] fraction +-- ----------------------------------------------------------------------------------------------- +-- OUTPUT LOAD DATA FORMAT ... add implicit bit +-- +-- DP | SP +-- ---------------------------------------------|------------------------------------------------- +-- [00:00] Din[00] | Din[00] <--- Sgn +-- [01:01] Din[01] | Din[01] <--- exp[00] //03 +-- [02:02] Din[02] | ~Din[01] | (Din[01:08]="11111111") <--- exp[01] //04 +-- [03:03] Din[03] | ~Din[01] | (Din[01:08]="11111111") <--- exp[02] //05 +-- [04:04] Din[04] | ~Din[01] | (Din[01:08]="11111111") <--- exp[03] //06 +-- [05:10] Din[05:10] | Din[02:07] <--- exp[04:09] //07:12 +-- [11:11] Din[11] | (Din[01:11]="00000000000") | Din[08] | (Din[01:08]="00000000") <--- exp[10] //13 +-- [12:12] ~(Din[01:11]="00000000000") | ~(Din[01:08]="00000000") <--- frac[00] //imlicit bit +-- [13:35] Din[12:34] | Din[09:31] <--- frac[01:23] +-- [36:64] Din[35:63] | (0:28=>'0') <--- frac[24:52] +-- ---------------------------------------------|------------------------------------------------- +-------------------------------------------------------------------------------- +-- LOAD FPU/FPR data format +-- +-- Double-precision load: lfd* +-- +-- Value Loaded Internal Representation [sign exponent imp fraction] Format name +-- ------------ ---------------------------------------------------- ----------- +-- 0 x 00000000001 0 0000... Zero +-- Denormal x 00000000001 0 xxxx... Denormal +-- Normal x xxxxxxxxxxx 1 xxxx... Normal +-- Inf x 11111111111 1 0000... Inf +-- NaN x 11111111111 1 qxxx... NaN +-- +-- Single-precision denormal form (SP_DENORM) +-- exp = 0x381, imp = 0, frac != 0 (frac == 0: SP_DENORM0) +-- +-- Single-precision load: lfs* +-- +-- Value Loaded Internal Representation [sign exponent imp fraction] Format name +-- ------------ ---------------------------------------------------- ----------- +-- 0 x 01110000001 0 000000000000000000000000000... SP_DENORM0 +-- Denormal x 01110000001 0 xxxxxxxxxxxxxxxxxxxxxxx0000... SP_DENORM +-- Normal x xXXXxxxxxxx 1 xxxxxxxxxxxxxxxxxxxxxxx0000... Normal +-- Inf x 11111111111 1 000000000000000000000000000... Inf +-- NaN x 11111111111 1 qxxxxxxxxxxxxxxxxxxxxxx0000... NaN +-------------------------------------------------------------------------------- + -- Convert Incoming SP loads to DP format + -- DP bias = 1023 + -- SP bias = 127 + -- diff = x380 => 0_0011_1000_0000 + -- SP Dddd_dddd + -- if D=0, 0_0011_1ddd_dddd -> {D,!D,!D,!D} + -- if D=1, 0_0100_0ddd_dddd -> {D,!D,!D,!D} + + -- For lfiwax and lfiwzx, either set upper (32) to zeros or ones + --load_int_zup <= (load_int and load_sign_ext and not load_sp_data(0)) or (load_int and not load_sign_ext); + load_int_1up <= load_int and load_sign_ext and load_sp_data(0); + + -- Due to the XU rotator, all SP loads (words) are aligned to the right + ex7_load_sp_data_raw(0 to 31) <= ex7_load_data_raw(32 to 63); + + load_dp_exp_zero <= ex7_load_data_raw( 1 to 11) = "00000000000"; + load_sp_exp_zero <= ex7_load_sp_data_raw( 1 to 8) = "00000000"; + load_sp_exp_ones <= ex7_load_sp_data_raw( 1 to 8) = "11111111"; + + load_sp_data(0) <= ex7_load_sp_data_raw( 0); -- sign + load_sp_data(1) <= tilo; -- exp02 + load_sp_data(2) <= ex7_load_sp_data_raw( 1); -- exp03 + load_sp_data(3) <= not ex7_load_sp_data_raw( 1) or load_sp_exp_ones; -- exp04 + load_sp_data(4) <= not ex7_load_sp_data_raw( 1) or load_sp_exp_ones; -- exp05 + load_sp_data(5) <= not ex7_load_sp_data_raw( 1) or load_sp_exp_ones; -- exp06 + load_sp_data(6 to 11) <= ex7_load_sp_data_raw( 2 to 7); -- exp07-12 + load_sp_data(12) <= ex7_load_sp_data_raw( 8) or load_sp_exp_zero; -- exp13 + load_sp_data(13) <= not load_sp_exp_zero; -- implicit + load_sp_data(14 to 36) <= ex7_load_sp_data_raw( 9 to 31); -- frac01:23 + load_sp_data(37 to 65) <= (37 to 65 => tilo); -- frac24:52 + + + load_dp_data( 0) <= (ex7_load_data_raw( 0) and not load_int) or load_int_1up; -- sign + load_dp_data( 1) <= tilo; -- exp02 + load_dp_data( 2 to 11) <= (ex7_load_data_raw( 1 to 10) and not (1 to 10 => load_int)) or (1 to 10 => load_int_1up); -- exp03-12 + load_dp_data(12) <= (ex7_load_data_raw(11) or load_dp_exp_zero) or load_int or load_int_1up; -- exp13 + load_dp_data(13) <= ( not load_dp_exp_zero and not load_int) or load_int_1up; -- implicit + load_dp_data(14 to 33) <= (ex7_load_data_raw(12 to 31) and not (14 to 33 => load_int)) or (14 to 33 => load_int_1up); -- fraction + load_dp_data(34 to 65) <= ex7_load_data_raw(32 to 63); -- fraction + + + ex7_load_data(0 to 65) <= (load_dp_data(0 to 65) and not (0 to 65 => load_sp)) or + (load_sp_data(0 to 65) and (0 to 65 => load_sp)) ; + + + load_data(0 to 65) <= ex7_load_data(0 to 65); + + + + ld_par0007 <= + ex7_load_data_raw( 0) xor + ex7_load_data_raw( 1) xor + ex7_load_data_raw( 2) xor + ex7_load_data_raw( 3) xor + ex7_load_data_raw( 4) xor + ex7_load_data_raw( 5) xor + ex7_load_data_raw( 6) xor + ex7_load_data_raw( 7) ; + ld_par32_3436 <= + ex7_load_data_raw(32) xor + ex7_load_data_raw(34) xor + ex7_load_data_raw(35) xor + ex7_load_data_raw(36) ; + ld_par0815 <= + ex7_load_data_raw( 8) xor + ex7_load_data_raw( 9) xor + ex7_load_data_raw(10) xor + ex7_load_data_raw(11) xor + ex7_load_data_raw(12) xor + ex7_load_data_raw(13) xor + ex7_load_data_raw(14) xor + ex7_load_data_raw(15) ; + ld_par3744 <= + ex7_load_data_raw(37) xor + ex7_load_data_raw(38) xor + ex7_load_data_raw(39) xor + ex7_load_data_raw(40) xor + ex7_load_data_raw(41) xor + ex7_load_data_raw(42) xor + ex7_load_data_raw(43) xor + ex7_load_data_raw(44) ; + ld_par1623 <= + ex7_load_data_raw(16) xor + ex7_load_data_raw(17) xor + ex7_load_data_raw(18) xor + ex7_load_data_raw(19) xor + ex7_load_data_raw(20) xor + ex7_load_data_raw(21) xor + ex7_load_data_raw(22) xor + ex7_load_data_raw(23) ; + ld_par4552 <= + ex7_load_data_raw(45) xor + ex7_load_data_raw(46) xor + ex7_load_data_raw(47) xor + ex7_load_data_raw(48) xor + ex7_load_data_raw(49) xor + ex7_load_data_raw(50) xor + ex7_load_data_raw(51) xor + ex7_load_data_raw(52) ; + ld_par2431 <= + ex7_load_data_raw(24) xor + ex7_load_data_raw(25) xor + ex7_load_data_raw(26) xor + ex7_load_data_raw(27) xor + ex7_load_data_raw(28) xor + ex7_load_data_raw(29) xor + ex7_load_data_raw(30) xor + ex7_load_data_raw(31) ; + ld_par5360 <= + ex7_load_data_raw(53) xor + ex7_load_data_raw(54) xor + ex7_load_data_raw(55) xor + ex7_load_data_raw(56) xor + ex7_load_data_raw(57) xor + ex7_load_data_raw(58) xor + ex7_load_data_raw(59) xor + ex7_load_data_raw(60) ; + ld_par3239 <= + ex7_load_data_raw(32) xor + ex7_load_data_raw(33) xor + ex7_load_data_raw(34) xor + ex7_load_data_raw(35) xor + ex7_load_data_raw(36) xor + ex7_load_data_raw(37) xor + ex7_load_data_raw(38) xor + ex7_load_data_raw(39) ; + ld_par3239_inj <= + ex7_load_data_raw(32) xor + ex7_load_data_raw(33) xor + ex7_load_data_raw(34) xor + ex7_load_data_raw(35) xor + ex7_load_data_raw(36) xor + ex7_load_data_raw(37) xor + ex7_load_data_raw(38) xor + ex7_load_data_raw(39) xor + ex7_ld_perr_inj ; + ld_par4047 <= + ex7_load_data_raw(40) xor + ex7_load_data_raw(41) xor + ex7_load_data_raw(42) xor + ex7_load_data_raw(43) xor + ex7_load_data_raw(44) xor + ex7_load_data_raw(45) xor + ex7_load_data_raw(46) xor + ex7_load_data_raw(47) ; + ld_par4855 <= + ex7_load_data_raw(48) xor + ex7_load_data_raw(49) xor + ex7_load_data_raw(50) xor + ex7_load_data_raw(51) xor + ex7_load_data_raw(52) xor + ex7_load_data_raw(53) xor + ex7_load_data_raw(54) xor + ex7_load_data_raw(55) ; + ld_par5663 <= + ex7_load_data_raw(56) xor + ex7_load_data_raw(57) xor + ex7_load_data_raw(58) xor + ex7_load_data_raw(59) xor + ex7_load_data_raw(60) xor + ex7_load_data_raw(61) xor + ex7_load_data_raw(62) xor + ex7_load_data_raw(63) ; + ld_par6163 <= + ex7_load_data_raw(61) xor + ex7_load_data_raw(62) xor + ex7_load_data_raw(63) ; + ld_par6163_inj <= + ex7_load_data_raw(61) xor + ex7_load_data_raw(62) xor + ex7_load_data_raw(63) xor + ex7_ld_perr_inj ; + + load_dp_nint <= not load_sp and not load_int ; + load_dp_int <= not load_sp and load_int ; + load_sp_all1 <= load_sp and load_sp_exp_ones ; + load_sp_nall1 <= load_sp and not load_sp_exp_ones ; + + load_data_parity(0) <= ( ld_par0007 and load_dp_nint) or ( ld_par32_3436 and load_sp_all1) or + (not ld_par32_3436 and load_sp_nall1) ; + load_data_parity(1) <= (not ld_par0815 and load_dp_nint) or (not ld_par3744 and load_sp) or load_dp_int; + load_data_parity(2) <= ( ld_par1623 and load_dp_nint) or ( ld_par4552 and load_sp); + load_data_parity(3) <= ( ld_par2431 and load_dp_nint) or ( ld_par5360 and load_sp); + load_data_parity(4) <= ( ld_par3239 and not load_sp ) or ( ld_par6163 and load_sp); + load_data_parity(5) <= ( ld_par4047 and not load_sp ) ; + load_data_parity(6) <= ( ld_par4855 and not load_sp ) ; + load_data_parity(7) <= ( ld_par5663 and not load_sp ) ; + + load_data_parity_inj(0) <= ( ld_par0007 and load_dp_nint) or ( ld_par32_3436 and load_sp_all1) or + (not ld_par32_3436 and load_sp_nall1) ; + load_data_parity_inj(1) <= (not ld_par0815 and load_dp_nint) or (not ld_par3744 and load_sp) or load_dp_int; + load_data_parity_inj(2) <= ( ld_par1623 and load_dp_nint) or ( ld_par4552 and load_sp); + load_data_parity_inj(3) <= ( ld_par2431 and load_dp_nint) or ( ld_par5360 and load_sp); + load_data_parity_inj(4) <= ( ld_par3239_inj and not load_sp ) or ( ld_par6163_inj and load_sp); + load_data_parity_inj(5) <= ( ld_par4047 and not load_sp ) ; + load_data_parity_inj(6) <= ( ld_par4855 and not load_sp ) ; + load_data_parity_inj(7) <= ( ld_par5663 and not load_sp ) ; + + + + +------------------------------------------------------------------------ +-- Load Bypass + + f_fpr_ex7_load_sign <= load_data(0); + f_fpr_ex7_load_expo(3 to 13) <= load_data(2 to 12); + f_fpr_ex7_load_frac(0 to 52) <= load_data(13 to 65); + +------------------------------------------------------------------------ +-- Target Data + + frt_addr(1 to 7) <= f_dcd_ex6_frt_addr(1 to 5) & f_dcd_ex6_frt_tid(0 to 1); + frt_wen <= f_dcd_ex6_frt_wen; + + frt_data_parity(0) <= f_rnd_ex6_res_sign xor f_rnd_ex6_res_expo(2) xor f_rnd_ex6_res_expo(3) xor f_rnd_ex6_res_expo(4) xor f_rnd_ex6_res_expo(5) xor + f_rnd_ex6_res_expo(6) xor f_rnd_ex6_res_expo(7) xor f_rnd_ex6_res_expo(8) xor f_rnd_ex6_res_expo(9) ; + frt_data_parity(1) <= f_rnd_ex6_res_expo(10) xor f_rnd_ex6_res_expo(11) xor f_rnd_ex6_res_expo(12) xor f_rnd_ex6_res_expo(13) xor f_rnd_ex6_res_frac(0) xor + f_rnd_ex6_res_frac(1) xor f_rnd_ex6_res_frac(2) xor f_rnd_ex6_res_frac(3) xor f_rnd_ex6_res_frac(4) ; + frt_data_parity(2) <= f_rnd_ex6_res_frac(5) xor f_rnd_ex6_res_frac(6) xor f_rnd_ex6_res_frac(7) xor f_rnd_ex6_res_frac(8) xor + f_rnd_ex6_res_frac(9) xor f_rnd_ex6_res_frac(10) xor f_rnd_ex6_res_frac(11) xor f_rnd_ex6_res_frac(12) ; + frt_data_parity(3) <= f_rnd_ex6_res_frac(13) xor f_rnd_ex6_res_frac(14) xor f_rnd_ex6_res_frac(15) xor f_rnd_ex6_res_frac(16) xor + f_rnd_ex6_res_frac(17) xor f_rnd_ex6_res_frac(18) xor f_rnd_ex6_res_frac(19) xor f_rnd_ex6_res_frac(20) ; + frt_data_parity(4) <= f_rnd_ex6_res_frac(21) xor f_rnd_ex6_res_frac(22) xor f_rnd_ex6_res_frac(23) xor f_rnd_ex6_res_frac(24) xor + f_rnd_ex6_res_frac(25) xor f_rnd_ex6_res_frac(26) xor f_rnd_ex6_res_frac(27) xor f_rnd_ex6_res_frac(28) ; + frt_data_parity(5) <= f_rnd_ex6_res_frac(29) xor f_rnd_ex6_res_frac(30) xor f_rnd_ex6_res_frac(31) xor f_rnd_ex6_res_frac(32) xor + f_rnd_ex6_res_frac(33) xor f_rnd_ex6_res_frac(34) xor f_rnd_ex6_res_frac(35) xor f_rnd_ex6_res_frac(36) ; + frt_data_parity(6) <= f_rnd_ex6_res_frac(37) xor f_rnd_ex6_res_frac(38) xor f_rnd_ex6_res_frac(39) xor f_rnd_ex6_res_frac(40) xor + f_rnd_ex6_res_frac(41) xor f_rnd_ex6_res_frac(42) xor f_rnd_ex6_res_frac(43) xor f_rnd_ex6_res_frac(44) ; + frt_data_parity(7) <= f_rnd_ex6_res_frac(45) xor f_rnd_ex6_res_frac(46) xor f_rnd_ex6_res_frac(47) xor f_rnd_ex6_res_frac(48) xor + f_rnd_ex6_res_frac(49) xor f_rnd_ex6_res_frac(50) xor f_rnd_ex6_res_frac(51) xor f_rnd_ex6_res_frac(52); + + +------------------------------------------------------------------------ +-- Source Address + + rf0_fra_addr(1 to 7) <= f_dcd_rf0_fra(1 to 5) & f_dcd_rf0_tid(0 to 1); --uc_hook + rf0_frb_addr(1 to 7) <= f_dcd_rf0_frb(1 to 5) & f_dcd_rf0_tid(0 to 1); + rf0_frc_addr(1 to 7) <= f_dcd_rf0_frc(1 to 5) & f_dcd_rf0_tid(0 to 1); + + rf0_frs_addr(1 to 7) <= iu_fu_rf0_ldst_tag(4 to 8) & iu_fu_rf0_ldst_tid(0 to 1); + + -- Microcode Scratch Registers + rf0_fra_addr(0) <= f_dcd_rf0_fra(0); -- uc_hook + rf0_frb_addr(0) <= f_dcd_rf0_frb(0); + rf0_frc_addr(0) <= f_dcd_rf0_frc(0); + + frt_addr(0) <= f_dcd_ex6_frt_addr(0); + + rf0_frs_addr(0) <= iu_fu_rf0_ldst_tag(3); -- Don't need to store from scratch regs? + load_addr(0) <= ex7_load_tag(3); + + -- For bypass writethru compare + f_fpr_ex7_load_addr(0 to 7) <= load_tid_enc(0 to 1) & load_addr(0) & ex7_load_tag(4 to 8); + f_fpr_ex7_load_v <= load_wen; + +------------------------------------------------------------------------ +-- RF0 + + +------------------------------------------------------------------------ +-- RF1 + + + + w0e_act <= load_wen; + w0e_en_func <= load_wen; + w0e_addr_func(0 to 7) <= load_addr(0 to 7); + + w0l_act <= frt_wen; + w0l_en_func <= frt_wen; + w0l_addr_func(0 to 7) <= frt_addr (0 to 7); + + --parity(0 to 7)<= data(66 to 73) 0:7 + --"000" 8:10 + --sign <= data(0); 11 + --expo(1) 12 + --expo(2 to 13) <= data(1 to 12); 13:24 + --frac(0 to 52) <= data(13 to 65); 25:77 + + w0e_data_func_f0(0 to 77) <= load_data_parity_inj(0 to 7) & "000" & load_data(0) & '0' & load_data(1 to 65); + w0e_data_func_f1(0 to 77) <= load_data_parity(0 to 7) & "000" & load_data(0) & '0' & load_data(1 to 65); + + w0l_data_func_f0(0 to 77) <= frt_data_parity(0 to 7) & "000" & f_rnd_ex6_res_sign & f_rnd_ex6_res_expo(1 to 13) & f_rnd_ex6_res_frac(0 to 52); + w0l_data_func_f1(0 to 77) <= frt_data_parity(0 to 6) & (frt_data_parity(7) xor ex6_targ_perr_inj) & "000" & f_rnd_ex6_res_sign & f_rnd_ex6_res_expo(1 to 13) & f_rnd_ex6_res_frac(0 to 52); + + rf1_fra(0 to 77) <= fra_data_out( 0 to 77); --frac + rf1_frb(0 to 77) <= frb_data_out( 0 to 77); --frac + rf1_frc(0 to 77) <= frc_data_out( 0 to 77); --frac + rf1_frs(0 to 77) <= frs_data_out( 0 to 77); --frac + + + rf1_byp: tri_rlmreg_p generic map (init => 0, expand_type => expand_type, width => 8, needs_sreset => 0) + port map (nclk => nclk, + act => f_dcd_msr_fp_act, + forcee => forcee, + delay_lclkr => delay_lclkra(0), + mpw1_b => mpw1_ba(0), + mpw2_b => mpw2_b(0), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => ex1_dcd_si(0 to 7), + scout => ex1_dcd_so(0 to 7), + din ( 0) => f_dcd_rf0_bypsel_a_res1 , + din ( 1) => f_dcd_rf0_bypsel_b_res1 , + din ( 2) => f_dcd_rf0_bypsel_c_res1 , + din ( 3) => f_dcd_rf0_bypsel_s_res1 , + din ( 4) => f_dcd_rf0_bypsel_a_load1 , + din ( 5) => f_dcd_rf0_bypsel_b_load1 , + din ( 6) => f_dcd_rf0_bypsel_c_load1 , + din ( 7) => f_dcd_rf0_bypsel_s_load1 , + + dout( 0) => rf1_bypsel_a_res1 , + dout( 1) => rf1_bypsel_b_res1 , + dout( 2) => rf1_bypsel_c_res1 , + dout( 3) => rf1_bypsel_s_res1 , + dout( 4) => rf1_bypsel_a_load1 , + dout( 5) => rf1_bypsel_b_load1 , + dout( 6) => rf1_bypsel_c_load1 , + dout( 7) => rf1_bypsel_s_load1 ); + + rf1_bypsel_a_res1_nlb <= rf1_bypsel_a_res1 ; + rf1_bypsel_b_res1_nlb <= rf1_bypsel_b_res1 ; + rf1_bypsel_c_res1_nlb <= rf1_bypsel_c_res1 ; + rf1_bypsel_s_res1_nlb <= rf1_bypsel_s_res1 ; + rf1_bypsel_a_load1_nlb <= rf1_bypsel_a_load1 ; + rf1_bypsel_b_load1_nlb <= rf1_bypsel_b_load1 ; + rf1_bypsel_c_load1_nlb <= rf1_bypsel_c_load1 ; + rf1_bypsel_s_load1_nlb <= rf1_bypsel_s_load1 ; + + rf1_a_r0e_byp_r <= not(rf1_bypsel_a_load1 or rf1_bypsel_a_res1) ; + rf1_c_r1e_byp_r <= not(rf1_bypsel_c_load1 or rf1_bypsel_c_res1) ; + + rf1_b_r0e_byp_r <= not(rf1_bypsel_b_load1 or rf1_bypsel_b_res1) ; + rf1_s_r1e_byp_r <= not(rf1_bypsel_s_load1 or rf1_bypsel_s_res1) ; + + + + + -- Array Instantiation + f0 : entity tri.tri_144x78_2r2w + generic map (expand_type => expand_type) + port map( + vdd => vdd , + gnd => gnd , + nclk => nclk , + + lcb_bolt_sl_thold_0 => lcb_bolt_sl_thold_0 , + pc_bo_enable_2 => pc_bo_enable_2 , + pc_bo_reset => pc_fu_bo_reset , + pc_bo_unload => pc_fu_bo_unload , + pc_bo_load => pc_fu_bo_load , + pc_bo_shdata => pc_fu_bo_shdata , + pc_bo_select => pc_fu_bo_select(0) , + bo_pc_failout => fu_pc_bo_fail(0) , + bo_pc_diagloop => fu_pc_bo_diagout(0) , + + tri_lcb_mpw1_dc_b => mpw1_ba(0), + tri_lcb_mpw2_dc_b => mpw2_b(0), + tri_lcb_delay_lclkr_dc => delay_lclkra(0), + tri_lcb_clkoff_dc_b => clkoff_b, + tri_lcb_act_dis_dc => tilo, + + abist_en => pc_fu_abist_ena_dc , + abist_raw_dc_b => pc_fu_abist_raw_dc_b , + r0e_abist_comp_en => r0e_abist_comp_en , + r1e_abist_comp_en => r1e_abist_comp_en , + lbist_en => an_ac_lbist_ary_wrt_thru_dc , + lcb_act_dis_dc => Alcb_act_dis_dc , + lcb_clkoff_dc_b => lcb_clkoff_dc_b , + lcb_d_mode_dc => Alcb_d_mode_dc , + lcb_delay_lclkr_dc => lcb_delay_lclkr_dc , + lcb_fce_0 => fce_0 , + lcb_mpw1_dc_b => lcb_mpw1_dc_b , + lcb_mpw2_dc_b => lcb_mpw2_dc_b , + lcb_scan_diag_dc => scan_diag_dc , + lcb_scan_dis_dc_b => scan_dis_dc_b , + lcb_sg_0 => lcb_sg_0 , + lcb_time_sg_0 => lcb_sg_0 , + lcb_abst_sl_thold_0 => lcb_abst_sl_thold_0 , + lcb_time_sl_thold_0 => time_sl_thold_0 , + lcb_obs0_sg_0 => lcb_obs0_sg_0 , + lcb_obs1_sg_0 => lcb_obs1_sg_0 , + lcb_obs0_sl_thold_0 => lcb_obs0_sl_thold_0 , + lcb_obs1_sl_thold_0 => lcb_obs1_sl_thold_0 , + lcb_ary_nsl_thold_0 => ary_nsl_thold_0 , + r_scan_in => r_scan_in_0 , + r_scan_out => r_scan_out_0 , + w_scan_in => w_scan_in_0 , + w_scan_out => w_scan_out_0 , + time_scan_in => fpr_time_si(0) , + time_scan_out => fpr_time_so(0) , + obs0_scan_in => obs0_scan_in(0) , + obs0_scan_out => obs0_scan_out(0) , + obs1_scan_in => obs1_scan_in(0) , + obs1_scan_out => obs1_scan_out(0) , + -- Read Port FRA + r0e_act => r0e_fra_act , + r0e_en_func => r0e_fra_en_func , + r0e_en_abist => r0e_en_abist , + r0e_addr_func => rf0_fra_addr , + r0e_addr_abist => r0e_addr_abist , + r0e_data_out => fra_data_out , + r0e_byp_e => rf1_bypsel_a_load1_nlb , + r0e_byp_l => rf1_bypsel_a_res1_nlb , + r0e_byp_r => rf1_a_r0e_byp_r, + r0e_sel_lbist => r0e_sel_lbist , + -- Read Port FRC + r1e_act => r1e_frc_act , + r1e_en_func => r1e_frc_en_func , + r1e_en_abist => r1e_en_abist , + r1e_addr_func => rf0_frc_addr , + r1e_addr_abist => r1e_addr_abist , + r1e_data_out => frc_data_out , + r1e_byp_e => rf1_bypsel_c_load1_nlb , + r1e_byp_l => rf1_bypsel_c_res1_nlb , + r1e_byp_r => rf1_c_r1e_byp_r, + r1e_sel_lbist => r1e_sel_lbist , + -- Write Ports + w0e_act => w0e_act , + w0e_en_func => w0e_en_func , + w0e_en_abist => w0e_en_abist , + w0e_addr_func => w0e_addr_func , + w0e_addr_abist => w0e_addr_abist , + w0e_data_func => w0e_data_func_f0 , + w0e_data_abist => w0e_data_abist , + w0l_act => w0l_act , + w0l_en_func => w0l_en_func , + w0l_en_abist => w0l_en_abist , + w0l_addr_func => w0l_addr_func , + w0l_addr_abist => w0l_addr_abist , + w0l_data_func => w0l_data_func_f0 , + w0l_data_abist => w0l_data_abist + ); + + -- Array Instantiation + f1 : entity tri.tri_144x78_2r2w + generic map (expand_type => expand_type) + port map( + vdd => vdd , + gnd => gnd , + nclk => nclk , + + lcb_bolt_sl_thold_0 => lcb_bolt_sl_thold_0 , + pc_bo_enable_2 => pc_bo_enable_2 , + pc_bo_reset => pc_fu_bo_reset , + pc_bo_unload => pc_fu_bo_unload , + pc_bo_load => pc_fu_bo_load , + pc_bo_shdata => pc_fu_bo_shdata , + pc_bo_select => pc_fu_bo_select(1) , + bo_pc_failout => fu_pc_bo_fail(1) , + bo_pc_diagloop => fu_pc_bo_diagout(1) , + + tri_lcb_mpw1_dc_b => mpw1_ba(0), + tri_lcb_mpw2_dc_b => mpw2_b(0), + tri_lcb_delay_lclkr_dc => delay_lclkra(0), + tri_lcb_clkoff_dc_b => clkoff_b, + tri_lcb_act_dis_dc => tilo, + + abist_en => pc_fu_abist_ena_dc , + abist_raw_dc_b => pc_fu_abist_raw_dc_b , + r0e_abist_comp_en => r0e_abist_comp_en , + r1e_abist_comp_en => r1e_abist_comp_en , + lbist_en => an_ac_lbist_ary_wrt_thru_dc , + lcb_act_dis_dc => Alcb_act_dis_dc , + lcb_clkoff_dc_b => lcb_clkoff_dc_b , + lcb_d_mode_dc => Alcb_d_mode_dc , + lcb_delay_lclkr_dc => lcb_delay_lclkr_dc , + lcb_fce_0 => fce_0 , + lcb_mpw1_dc_b => lcb_mpw1_dc_b , + lcb_mpw2_dc_b => lcb_mpw2_dc_b , + lcb_scan_diag_dc => scan_diag_dc , + lcb_scan_dis_dc_b => scan_dis_dc_b , + lcb_sg_0 => lcb_sg_0 , + lcb_time_sg_0 => lcb_sg_0 , + lcb_abst_sl_thold_0 => lcb_abst_sl_thold_0 , + lcb_time_sl_thold_0 => time_sl_thold_0 , + lcb_obs0_sg_0 => lcb_obs0_sg_0 , + lcb_obs1_sg_0 => lcb_obs1_sg_0 , + lcb_obs0_sl_thold_0 => lcb_obs0_sl_thold_0 , + lcb_obs1_sl_thold_0 => lcb_obs1_sl_thold_0 , + lcb_ary_nsl_thold_0 => ary_nsl_thold_0 , + r_scan_in => r_scan_in_1 , + r_scan_out => r_scan_out_1 , + w_scan_in => w_scan_in_1 , + w_scan_out => w_scan_out_1 , + time_scan_in => fpr_time_si(1) , + time_scan_out => fpr_time_so(1) , + obs0_scan_in => obs0_scan_in(1) , + obs0_scan_out => obs0_scan_out(1) , + obs1_scan_in => obs1_scan_in(1) , + obs1_scan_out => obs1_scan_out(1) , + -- Read Port FRB + r0e_act => r0e_frb_act , + r0e_en_func => r0e_frb_en_func , + r0e_en_abist => r0e_en_abist , + r0e_addr_func => rf0_frb_addr , + r0e_addr_abist => r0e_addr_abist , + r0e_data_out => frb_data_out , + r0e_byp_e => rf1_bypsel_b_load1_nlb , + r0e_byp_l => rf1_bypsel_b_res1_nlb , + r0e_byp_r => rf1_b_r0e_byp_r, + r0e_sel_lbist => r0e_sel_lbist , + -- Read Port FRS + r1e_act => r1e_frs_act , + r1e_en_func => r1e_frs_en_func , + r1e_en_abist => r1e_en_abist , + r1e_addr_func => rf0_frs_addr , + r1e_addr_abist => r1e_addr_abist , + r1e_data_out => frs_data_out , + r1e_byp_e => rf1_bypsel_s_load1_nlb , + r1e_byp_l => rf1_bypsel_s_res1_nlb , + r1e_byp_r => rf1_s_r1e_byp_r, + r1e_sel_lbist => r1e_sel_lbist , + -- Write Ports + w0e_act => w0e_act , + w0e_en_func => w0e_en_func , + w0e_en_abist => w0e_en_abist , + w0e_addr_func => w0e_addr_func , + w0e_addr_abist => w0e_addr_abist , + w0e_data_func => w0e_data_func_f1 , + w0e_data_abist => w0e_data_abist , + w0l_act => w0l_act , + w0l_en_func => w0l_en_func , + w0l_en_abist => w0l_en_abist , + w0l_addr_func => w0l_addr_func , + w0l_addr_abist => w0l_addr_abist , + w0l_data_func => w0l_data_func_f1 , + w0l_data_abist => w0l_data_abist + ); + + -- ABIST timing latches + ab_reg: tri_rlmreg_p generic map (init => 0, expand_type => expand_type, width => 53, needs_sreset => 0) + port map (nclk => nclk, + act => pc_fu_abist_ena_dc, + forcee => ab_force, + delay_lclkr => delay_lclkra(0), + mpw1_b => mpw1_ba(0), + mpw2_b => mpw2_b(0), + thold_b => ab_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => ab_reg_si(0 to 52), + scout => ab_reg_so(0 to 52), + din ( 0 to 3) => pc_fu_abist_di_0(0 to 3) , + din ( 4 to 7) => pc_fu_abist_di_1(0 to 3) , + din ( 8) => pc_fu_abist_grf_renb_0 , + din ( 9) => pc_fu_abist_grf_renb_1 , + din ( 10) => pc_fu_abist_grf_wenb_0 , + din ( 11) => pc_fu_abist_grf_wenb_1 , + din (12 to 21) => pc_fu_abist_raddr_0(0 to 9), + din (22 to 31) => pc_fu_abist_raddr_1(0 to 9), + din (32 to 41) => pc_fu_abist_waddr_0(0 to 9), + din (42 to 51) => pc_fu_abist_waddr_1(0 to 9), + din ( 52) => pc_fu_abist_wl144_comp_ena , + dout( 0 to 3) => w0e_data_abist(0 to 3) , + dout( 4 to 7) => w0l_data_abist(0 to 3) , + dout( 8) => r0e_en_abist , + dout( 9) => r1e_en_abist , + dout( 10) => w0e_en_abist , + dout( 11) => w0l_en_abist , + dout(12 to 21) => abist_raddr_0(0 to 9), + dout(22 to 31) => abist_raddr_1(0 to 9), + dout(32 to 41) => abist_waddr_0(0 to 9), + dout(42 to 51) => abist_waddr_1(0 to 9), + dout( 52) => abist_comp_en ); + +lcbctrlA : entity tri.tri_lcbcntl_array_mac + generic map( expand_type => expand_type ) + port map( + vdd => vdd, + gnd => gnd, + sg => sg_0, + nclk => nclk, + scan_in => gptr_scan_in, + scan_diag_dc => scan_diag_dc, + thold => gptr_sl_thold_0, --Connects to time thold + clkoff_dc_b => Aclkoff_dc_b, + delay_lclkr_dc => Alcb_delay_lclkr_dc(0 to 4), + act_dis_dc => Alcb_act_dis_dc, + d_mode_dc => Ad_mode_dc, + mpw1_dc_b => Alcb_mpw1_dc_b(0 to 4), + mpw2_dc_b => Alcb_mpw2_dc_b, + scan_out => gptr_scan_out -- Connects to time scan ring + ); + + + + lcb_mpw2_dc_b <= Alcb_mpw2_dc_b; + + --0 lcb_delay_lclkr_dc(0,2) --> Are driving L2 LCBs + --1 lcb_delay_lclkr_dc(1,3) --> Are driving L1 LCBs + --2 lcb_delay_lclkr_dc(4) --> Is driving the late write clock LCB + --3 lcb_delay_lclkr_dc(5:9) --> Are driving nLCBs + --Similar for mpw1 signals: + --0 lcb_mpw1_dc_b(2) --> unused + --1 lcb_mpw1_dc_b(1,3) --> Driving L1 LCBs + --2 lcb_mpw1_dc_b(4) --> Is driving the late write clock LCB + --3 lcb_mpw1_dc_b(5:9) --> Are driving nLCBs + + lcb_delay_lclkr_dc(0) <= Alcb_delay_lclkr_dc(0) ; + lcb_delay_lclkr_dc(1) <= Alcb_delay_lclkr_dc(1) ; + lcb_delay_lclkr_dc(2) <= Alcb_delay_lclkr_dc(0) ; + lcb_delay_lclkr_dc(3) <= Alcb_delay_lclkr_dc(1) ; + lcb_delay_lclkr_dc(4) <= Alcb_delay_lclkr_dc(2) ; + lcb_delay_lclkr_dc(5) <= Alcb_delay_lclkr_dc(3) ; + lcb_delay_lclkr_dc(6) <= Alcb_delay_lclkr_dc(4) ; + lcb_delay_lclkr_dc(7) <= Alcb_delay_lclkr_dc(4) ; + lcb_delay_lclkr_dc(8) <= Alcb_delay_lclkr_dc(3) ; + lcb_delay_lclkr_dc(9) <= Alcb_delay_lclkr_dc(3) ; + + lcb_mpw1_dc_b(1) <= Alcb_mpw1_dc_b (1) ; + lcb_mpw1_dc_b(2) <= Alcb_mpw1_dc_b (0) ; + lcb_mpw1_dc_b(3) <= Alcb_mpw1_dc_b (1) ; + lcb_mpw1_dc_b(4) <= Alcb_mpw1_dc_b (2) ; + lcb_mpw1_dc_b(5) <= Alcb_mpw1_dc_b (3) ; + lcb_mpw1_dc_b(6) <= Alcb_mpw1_dc_b (4) ; + lcb_mpw1_dc_b(7) <= Alcb_mpw1_dc_b (4) ; + lcb_mpw1_dc_b(8) <= Alcb_mpw1_dc_b (3) ; + lcb_mpw1_dc_b(9) <= Alcb_mpw1_dc_b (3) ; + + lcb_obs0_sg_0 <= sg_0 ; + lcb_obs1_sg_0 <= sg_0 ; + lcb_obs0_sl_thold_0 <= ab_thold_0 ; + lcb_obs1_sl_thold_0 <= ab_thold_0 ; + + -- Other inputs + r0e_abist_comp_en <= abist_comp_en; + r1e_abist_comp_en <= abist_comp_en; + + lcb_sg_0 <= sg_0; + lcb_abst_sl_thold_0 <= ab_thold_0; + + Alcb_d_mode_dc <= Ad_mode_dc; + + lcb_clkoff_dc_b <= Aclkoff_dc_b & Aclkoff_dc_b; + + r0e_frb_act <= iu_fu_rf0_frb_v or f_dcd_perr_sm_running or lbist_en_dc; --ports BC used by perrsm + r0e_frb_en_func <= iu_fu_rf0_frb_v or f_dcd_perr_sm_running or lbist_en_dc; + r0e_fra_act <= iu_fu_rf0_fra_v or lbist_en_dc; + r0e_fra_en_func <= iu_fu_rf0_fra_v or lbist_en_dc; + + r1e_frs_act <= iu_fu_rf0_str_v or lbist_en_dc; + r1e_frs_en_func <= iu_fu_rf0_str_v or lbist_en_dc; + r1e_frc_act <= iu_fu_rf0_frc_v or f_dcd_perr_sm_running or lbist_en_dc; + r1e_frc_en_func <= iu_fu_rf0_frc_v or f_dcd_perr_sm_running or lbist_en_dc; + + r0e_addr_abist(0 to 7) <= abist_raddr_0(2 to 9); + r1e_addr_abist(0 to 7) <= abist_raddr_1(2 to 9); + + w0e_addr_abist(0 to 7) <= abist_waddr_0(2 to 9); + w0l_addr_abist(0 to 7) <= abist_waddr_1(2 to 9); + + r0e_sel_lbist <= an_ac_lbist_ary_wrt_thru_dc; + r1e_sel_lbist <= an_ac_lbist_ary_wrt_thru_dc; + +------------------------------------------------------------------------ +-- Parity Checking + + + ex1_par: tri_rlmreg_p generic map (init => 0, expand_type => expand_type, width => 33, needs_sreset => 0) + port map (nclk => nclk, + act => f_dcd_msr_fp_act, + forcee => forcee, + delay_lclkr => delay_lclkra(1), + mpw1_b => mpw1_ba(1), + mpw2_b => mpw2_b(0), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => ex1_par_si(0 to 32), + scout => ex1_par_so(0 to 32), + din ( 0 to 7) => rf1_fra(0 to 7) , + din ( 8 to 15) => rf1_frb(0 to 7) , + din (16 to 23) => rf1_frc(0 to 7) , + din (24 to 31) => rf1_frs(0 to 7) , + din (32) => rf1_frs(13) , + + dout( 0 to 7) => ex1_fra_par(0 to 7) , + dout( 8 to 15) => ex1_frb_par(0 to 7) , + dout(16 to 23) => ex1_frc_par(0 to 7) , + dout(24 to 31) => ex1_frs_par(0 to 7) , + dout(32) => ex1_s_expo_extra ); + + + f_fpr_ex1_a_par(0 to 7) <= ex1_fra_par(0 to 7); + f_fpr_ex1_b_par(0 to 7) <= ex1_frb_par(0 to 7); + f_fpr_ex1_c_par(0 to 7) <= ex1_frc_par(0 to 7); + f_fpr_ex1_s_par(0 to 7) <= ex1_frs_par(0 to 7); + + +------------------------------------------------------------------------ +-- Outputs + + --parity(0 to 7)<= data(66 to 73) 0:7 + --"000" 8:10 + --sign <= data(0); 11 + --expo(1) 12 + --expo(2 to 13) <= data(1 to 12); 13:24 + --frac(0 to 52) <= data(13 to 65); 25:77 + + f_fpr_rf1_a_sign <= rf1_fra(11); + f_fpr_rf1_a_expo(1 to 13) <= rf1_fra(12 to 24); + f_fpr_rf1_a_frac(0 to 52) <= rf1_fra(25 to 77); + f_fpr_rf1_c_sign <= rf1_frc(11); + f_fpr_rf1_c_expo(1 to 13) <= rf1_frc(12 to 24); + f_fpr_rf1_c_frac(0 to 52) <= rf1_frc(25 to 77); + f_fpr_rf1_b_sign <= rf1_frb(11); + f_fpr_rf1_b_expo(1 to 13) <= rf1_frb(12 to 24); + f_fpr_rf1_b_frac(0 to 52) <= rf1_frb(25 to 77); + + f_fpr_rf1_s_sign <= rf1_frs(11); + f_fpr_rf1_s_expo(1 to 11) <= rf1_frs(14 to 24); + f_fpr_rf1_s_frac(0 to 52) <= rf1_frs(25 to 77); + -- For Parity checking only, not used by store + f_fpr_ex1_s_expo_extra <= ex1_s_expo_extra; + + + +------------------------------------------------------------------------ +-- Spare Latches + + spare_lat: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 8) + port map (nclk => nclk, + act => f_dcd_msr_fp_act, + forcee => forcee, + delay_lclkr => delay_lclkra(0), + mpw1_b => mpw1_ba(0), + mpw2_b => mpw2_b(0), + thold_b => thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => spare_si(0 to 7), + scout => spare_so(0 to 7), + din( 0 to 7) => SPARE_L2(0 to 7) , + --------------------------------------------- + dout( 0 to 7) => SPARE_L2(0 to 7) + --------------------------------------------- + ); + + spare_lat_time: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 2) + port map (nclk => nclk, + act => tihi, + forcee => time_force, + delay_lclkr => delay_lclkra(0), + mpw1_b => mpw1_ba(0), + mpw2_b => mpw2_b(0), + thold_b => time_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => time_spare_si(0 to 1), + scout => time_spare_so(0 to 1), + din( 0 to 1) => time_SPARE_L2(0 to 1) , + --------------------------------------------- + dout( 0 to 1) => time_SPARE_L2(0 to 1) + --------------------------------------------- + ); + + + +lcbs_abst: tri_lcbs + generic map (expand_type => expand_type ) + port map ( + vd => vdd, + gd => gnd, + delay_lclkr => delay_lclkra(0), + nclk => nclk, + forcee => ab_force, + thold_b => ab_thold_0_b, + dclk => abst_slat_d2clk, + lclk => abst_slat_lclk ); +bx_abst_stg: tri_slat_scan + generic map (width => 2, init => "00", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => abst_slat_d2clk, + lclk => abst_slat_lclk, + scan_in(0) => bx_fu_rp_abst_scan_out, + scan_in(1) => rp_bx_abst_scan_in, + scan_out(0) => bx_rp_abst_scan_out, + scan_out(1) => rp_fu_bx_abst_scan_in ); + + +lcbs_func: tri_lcbs + generic map (expand_type => expand_type ) + port map ( + vd => vdd, + gd => gnd, + delay_lclkr => delay_lclkra(0), + nclk => nclk, + forcee => forcee, + thold_b => thold_0_b, + dclk => func_slat_d2clk, + lclk => func_slat_lclk ); +bx_func_stg: tri_slat_scan + generic map (width => 4, init => "0000", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => func_slat_d2clk, + lclk => func_slat_lclk, + scan_in(0 to 1) => bx_fu_rp_func_scan_out, + scan_in(2 to 3) => rp_bx_func_scan_in, + scan_out(0 to 1) => bx_rp_func_scan_out, + scan_out(2 to 3) => rp_fu_bx_func_scan_in ); + +------------------------------------------------------------------------ +-- Scan Chains + + + + ex7_ldat_si (0 to 63) <= ex7_ldat_so (1 to 63) & f_fpr_si; + ex7_ldv_si (0 to 3) <= ex7_ldv_so (1 to 3) & ex7_ldat_so (0); + ex7_lctl_si (0 to 9) <= ex7_lctl_so (1 to 9) & ex7_ldv_so (0); + ex6_ldv_si (0 to 3) <= ex6_ldv_so (1 to 3) & ex7_lctl_so (0); + ex6_lctl_si (0 to 13) <= ex6_lctl_so (1 to 13) & ex6_ldv_so (0); + ex1_par_si (0 to 32) <= ex1_par_so (1 to 32) & ex6_lctl_so(0); + ex1_dcd_si(0 to 7) <= ex1_dcd_so (1 to 7) & ex1_par_so (0); + spare_si (0 to 7) <= spare_so(1 to 7) & ex1_dcd_so (0); + f_fpr_so <= spare_so (0); + + ab_reg_si (0 to 7) <= ab_reg_so (1 to 7) & f_fpr_ab_si; --broke up for timing + r_scan_in_0 <= ab_reg_so(0); + w_scan_in_0 <= r_scan_out_0; + r_scan_in_1 <= w_scan_out_0; + w_scan_in_1 <= r_scan_out_1; + obs0_scan_in(0 to 1) <= obs0_scan_out(1) & w_scan_out_1; + obs1_scan_in(0 to 1) <= obs1_scan_out(1) & obs0_scan_out(0); + + ab_reg_si (8 to 52) <= ab_reg_so (9 to 52) & obs1_scan_out(0); + f_fpr_ab_so <= ab_reg_so(8); + + --Time scan ring + time_spare_si(0) <= time_scan_in; + fpr_time_si(0 to 1) <= fpr_time_so(1) & time_spare_so(0); + time_spare_si(1) <= fpr_time_so(0); + time_scan_out <= time_spare_so(1); + +------------------------------------------------------------------------ +-- Unused + + spare_unused( 0 to 2) <= iu_fu_rf0_ldst_tag(0 to 2); + spare_unused( 3 to 5) <= rf1_fra(8 to 10); + spare_unused( 6 to 8) <= rf1_frb(8 to 10); + spare_unused( 9 to 11) <= rf1_frc(8 to 10); + spare_unused(12 to 14) <= rf1_frs(8 to 10); + + spare_unused(15 to 16) <= abist_raddr_0(0 to 1); + spare_unused(17 to 18) <= abist_raddr_1(0 to 1); + spare_unused(19 to 20) <= abist_waddr_0(0 to 1); + spare_unused(21 to 22) <= abist_waddr_1(0 to 1); + + spare_unused(23) <= Alcb_mpw1_dc_b(4); + spare_unused(24) <= Alcb_delay_lclkr_dc(4); + spare_unused(25) <= rf1_frs(12); + spare_unused(26) <= an_ac_abist_mode_dc; + + + +------------------------------------------------------------------------ +-- END + +end architecture fuq_fpr; diff --git a/rel/src/vhdl/work/fuq_gst.vhdl b/rel/src/vhdl/work/fuq_gst.vhdl new file mode 100644 index 0000000..639751a --- /dev/null +++ b/rel/src/vhdl/work/fuq_gst.vhdl @@ -0,0 +1,1429 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + + +--==########################################################################## +--==### FUQ_GST.VHDL ######### +--==### side pipe for graphics estimates ######### +--==### flogefp, fexptefp ######### +--==### ######### +--==########################################################################## + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + +entity fuq_gst is + +generic ( + expand_type : integer := 2 );-- 0 = ibm, 1 = non-ibm +port ( + vdd :inout power_logic; + gnd :inout power_logic; + clkoff_b :in std_ulogic; -- tiup + act_dis :in std_ulogic; -- ??tidn?? + flush :in std_ulogic; -- ??tidn?? + delay_lclkr :in std_ulogic_vector(2 to 5); -- tidn, + mpw1_b :in std_ulogic_vector(2 to 5); -- tidn, + mpw2_b :in std_ulogic_vector(0 to 1); -- tidn, + sg_1 :in std_ulogic; + thold_1 :in std_ulogic; + fpu_enable :in std_ulogic; --dc_act + nclk :in clk_logic; + ---------------------------------------------------------------------------- + f_gst_si :in std_ulogic; --perv scan + f_gst_so :out std_ulogic; --perv scan + rf1_act :in std_ulogic; + ---------------------------------------------------------------------------- + f_fmt_ex1_b_sign_gst :in std_ulogic; + f_fmt_ex1_b_expo_gst_b :in std_ulogic_vector(01 to 13); + f_fmt_ex1_b_frac_gst :in std_ulogic_vector(01 to 19); + ---------------------------------------------------------------------------- + f_pic_ex1_floges :in std_ulogic; + f_pic_ex1_fexptes :in std_ulogic; + ---------------------------------------------------------------------------- + f_gst_ex5_logexp_v :out std_ulogic; + f_gst_ex5_logexp_sign :out std_ulogic; -- needs to be right off of a latch + f_gst_ex5_logexp_exp :out std_ulogic_vector(01 to 11); -- needs to be right off of a latch + f_gst_ex5_logexp_fract :out std_ulogic_vector(00 to 19) -- needs to be right off of a latch +); ---------------------------------------------------------------------------- + + + + + + +end fuq_gst; + +--==################################################ +architecture fuq_gst of fuq_gst is + +constant tiup : std_ulogic := '1'; +constant tidn : std_ulogic := '0'; + +signal sg_0 :std_ulogic; +signal thold_0_b , thold_0, forcee :std_ulogic; + +------------------------------------------------------------------------ + + + +signal ex2_gst_ctrl_lat_scout :std_ulogic_vector(0 to 1); +signal ex2_gst_ctrl_lat_scin :std_ulogic_vector(0 to 1); +signal ex3_gst_ctrl_lat_scout :std_ulogic_vector(0 to 1); +signal ex3_gst_ctrl_lat_scin :std_ulogic_vector(0 to 1); +signal ex4_gst_ctrl_lat_scout :std_ulogic_vector(0 to 3); +signal ex4_gst_ctrl_lat_scin :std_ulogic_vector(0 to 3); +signal ex5_gst_ctrl_lat_scout :std_ulogic_vector(0 to 1); +signal ex5_gst_ctrl_lat_scin :std_ulogic_vector(0 to 1); +signal ex2_gst_stage_lat_scout :std_ulogic_vector(0 to 32); +signal ex2_gst_stage_lat_scin :std_ulogic_vector(0 to 32); +signal ex3_gst_stage_lat_scout :std_ulogic_vector(0 to 19); +signal ex3_gst_stage_lat_scin :std_ulogic_vector(0 to 19); +signal ex4_gst_stage_lat_scout :std_ulogic_vector(0 to 23); +signal ex4_gst_stage_lat_scin :std_ulogic_vector(0 to 23); +signal ex5_gst_stage_lat_scout :std_ulogic_vector(0 to 31); +signal ex5_gst_stage_lat_scin :std_ulogic_vector(0 to 31); + +signal ex4_log_dp_bias :std_ulogic_vector(1 to 11); +signal ex4_logof1_specialcase : std_ulogic; +signal ex3_logof1_specialcase : std_ulogic; + +signal ex4_signbit_din, ex5_signbit : std_ulogic; +signal ex4_log_signbit : std_ulogic; + +signal f1, f2, f3, f4, f5 : std_ulogic; +signal f6, f7, f8, f9, f10 : std_ulogic; +signal s1, s2, s3 : std_ulogic; +signal c4, c5, c6, c7 : std_ulogic; +signal a4, a5, a6 : std_ulogic; +signal a7, a8, a9, a10, a11 : std_ulogic; + +signal ex2_f :std_ulogic_vector(1 to 11); +signal ex2_a :std_ulogic_vector(4 to 11); +signal ex2_c :std_ulogic_vector(4 to 11); + +signal ex2_log_fsum :std_ulogic_vector(4 to 7) ; +signal ex2_log_fcarryin :std_ulogic_vector(3 to 6); + +signal ex2_b_sign :std_ulogic ; +signal ex2_b_biased_13exp :std_ulogic_vector(1 to 13); +signal ex2_b_biased_11exp :std_ulogic_vector(1 to 11); + +signal ex2_b_ubexp_sum :std_ulogic_vector(1 to 11); +signal ex2_b_ubexp_cout :std_ulogic_vector(2 to 11); +signal ex2_b_ubexp :std_ulogic_vector(1 to 11); + +signal ex2_b_fract :std_ulogic_vector(1 to 19); + +signal f_fmt_ex1_b_expo_gst :std_ulogic_vector(1 to 13); + +signal ex1_floges : std_ulogic; +signal ex1_fexptes : std_ulogic; +signal ex2_floges : std_ulogic; +signal ex2_fexptes : std_ulogic; +signal ex3_floges : std_ulogic; +signal ex3_fexptes : std_ulogic; +signal ex4_floges : std_ulogic; +signal ex4_fexptes : std_ulogic; +signal ex5_floges : std_ulogic; +signal ex5_fexptes : std_ulogic; + +signal ex2_log_a_addend_b, ex2_log_b_addend_b :std_ulogic_vector(1 to 11); + +signal ex3_mantissa, ex4_mantissa, ex3_mantissa_precomp,ex3_mantissa_precomp_b :std_ulogic_vector(1 to 19); +signal ex2_log_mantissa_precomp, ex3_mantissa_neg, ex2_mantissa_din :std_ulogic_vector(1 to 19); +signal ex2_shamt,ex3_shamt, ex4_shamt :std_ulogic_vector(0 to 4); +signal ex3_negate,ex4_negate, ex3_b_sign : std_ulogic; + +signal ex2_mantissa_shlev0 :std_ulogic_vector(00 to 19); +signal ex2_mantissa_shlev1 :std_ulogic_vector(00 to 22); -- 0 to 3 +signal ex2_mantissa_shlev2 :std_ulogic_vector(00 to 34); -- 0 to 12 +signal ex2_mantissa_shlev3 :std_ulogic_vector(00 to 50); -- 0 to 16 + +signal ex2_pow_int :std_ulogic_vector(1 to 8) ; +signal ex2_pow_frac :std_ulogic_vector(1 to 11) ; + + + +signal ex4_mantissa_shlev0 :std_ulogic_vector(01 to 19); +signal ex4_mantissa_shlev1 :std_ulogic_vector(01 to 22); -- 0 to 3 +signal ex4_mantissa_shlev2 :std_ulogic_vector(01 to 34); -- 0 to 12 +signal ex4_mantissa_shlev3 :std_ulogic_vector(01 to 50); -- 0 to 16 + +signal ex4_exponent_a_addend_b :std_ulogic_vector(01 to 11); +signal ex4_exponent_b_addend_b :std_ulogic_vector(01 to 11); + +signal ex4_log_a_addend_b :std_ulogic_vector(01 to 11); +signal ex4_log_b_addend_b :std_ulogic_vector(01 to 11); +signal ex4_pow_a_addend_b :std_ulogic_vector(01 to 11); +signal ex4_pow_b_addend_b :std_ulogic_vector(01 to 11); + +signal ex4_biased_exponent_result :std_ulogic_vector(01 to 11); +signal ex5_biased_exponent_result :std_ulogic_vector(01 to 11); + +signal ex4_log_mantissa_postsh :std_ulogic_vector(01 to 19); +signal ex4_log_fract :std_ulogic_vector(01 to 19); +signal ex4_pow_fract, ex4_pow_fract_b :std_ulogic_vector(01 to 11); +signal ex4_fract_din :std_ulogic_vector(00 to 19); +signal ex5_fract :std_ulogic_vector(00 to 19); + +signal l1_enc00, l1_enc01, l1_enc10, l1_enc11 :std_ulogic; +signal l2_enc00, l2_enc01, l2_enc10, l2_enc11 :std_ulogic; +signal l3_enc00, l3_enc01 :std_ulogic; +signal l1_e00, l1_e01, l1_e10, l1_e11 :std_ulogic; +signal l2_e00, l2_e01, l2_e10, l2_e11 :std_ulogic; +signal l3_e00, l3_e01 :std_ulogic; + + +signal ex4_f,ex4_f_b :std_ulogic_vector(01 to 11); + +------------------------------------------------------------------------ +signal eb1, eb2, eb3, eb4, eb5, eb6, eb7, eb8, eb9, eb10 : std_ulogic; + +signal ea4, ea5, ea6, ea7, ea8, ea9, ea10, ea11 : std_ulogic; +signal ec4, ec5, ec6, ec7 : std_ulogic; +signal es1, es2, es3 : std_ulogic; +signal ex4_ea, ex4_ec : std_ulogic_vector(4 to 11); + + +signal ex4_addend1, ex4_addend2, ex4_addend3 : std_ulogic_vector(1 to 11); +signal ex4_fsum : std_ulogic_vector(1 to 11); +signal ex4_fcarryin : std_ulogic_vector(1 to 11); +signal ex4_powf_a_addend_b : std_ulogic_vector(1 to 11); +signal ex4_powf_b_addend_b : std_ulogic_vector(1 to 11); + +signal zeros :std_ulogic_vector(01 to 16); +signal ex2_powsh_no_sat_lft, ex2_powsh_no_sat_rgt :std_ulogic ; + +signal ex1_act, ex2_act, ex3_act, ex4_act :std_ulogic; +signal act_so, act_si :std_ulogic_vector(0 to 7); +signal act_spare_unused :std_ulogic_vector(0 to 3); +signal unused :std_ulogic; +signal ex2_ube_g2_b , ex2_ube_g4, ex2_ube_g8_b :std_ulogic_vector(2 to 11) ; + + + +signal s2_0, s2_1, s3_0, s3_1, sx :std_ulogic; +signal s7_if_s1, s7_if_s20, s7_if_s30, s7_if_sx, s7_if_s31, s7_if_s21 :std_ulogic; +signal c6_if_s1, c6_if_s20, c6_if_s30, c6_if_sx, c6_if_s31, c6_if_s21 :std_ulogic; + +signal s6_if_s1, s6_if_s20, s6_if_s30, s6_if_sx, s6_if_s31, s6_if_s21 :std_ulogic; +signal c5_if_s1, c5_if_s20, c5_if_s30, c5_if_sx, c5_if_s31, c5_if_s21 :std_ulogic; + +signal s5_if_s1, s5_if_s20, s5_if_s30, s5_if_sx, s5_if_s31, s5_if_s21 :std_ulogic; +signal c4_if_s1, c4_if_s20, c4_if_s30, c4_if_sx, c4_if_s31, c4_if_s21 :std_ulogic; + +signal s4_if_s1, s4_if_s20, s4_if_s30, s4_if_sx, s4_if_s31, s4_if_s21 :std_ulogic; +signal c3_if_s1, c3_if_s20, c3_if_s30, c3_if_sx, c3_if_s31, c3_if_s21 :std_ulogic; + +signal es4_if_s1, es4_if_s20, es4_if_s30, es4_if_sx, es4_if_s31, es4_if_s21 :std_ulogic; +signal ec3_if_s1, ec3_if_s20, ec3_if_s30, ec3_if_sx, ec3_if_s31, ec3_if_s21 :std_ulogic; + +signal es5_if_s1, es5_if_s20, es5_if_s30, es5_if_sx, es5_if_s31, es5_if_s21 :std_ulogic; +signal ec4_if_s1, ec4_if_s20, ec4_if_s30, ec4_if_sx, ec4_if_s31, ec4_if_s21 :std_ulogic; + +signal es6_if_s1, es6_if_s20, es6_if_s30, es6_if_sx, es6_if_s31, es6_if_s21 :std_ulogic; +signal ec5_if_s1, ec5_if_s20, ec5_if_s30, ec5_if_sx, ec5_if_s31, ec5_if_s21 :std_ulogic; + +signal es7_if_s1, es7_if_s20, es7_if_s30, es7_if_sx, es7_if_s31, es7_if_s21 :std_ulogic; +signal ec6_if_s1, ec6_if_s20, ec6_if_s30, ec6_if_sx, ec6_if_s31, ec6_if_s21 :std_ulogic; + + signal es2_0, es2_1, esx, es3_0, es3_1 :std_ulogic ; + + + + +begin +--==########################################## +--# pervasive +--==########################################## + + +unused <= ex2_b_biased_13exp(1) or ex2_b_biased_13exp(2) or + ex2_b_ubexp(2) or ex2_b_ubexp(3) or + ex2_mantissa_shlev3(0) or + ex2_mantissa_shlev3(1) or + ex2_mantissa_shlev3(2) or + ex2_mantissa_shlev3(3) or + ex2_mantissa_shlev3(4) or + ex2_mantissa_shlev3(5) or + ex2_mantissa_shlev3(6) or + ex2_mantissa_shlev3(7) or + ex2_mantissa_shlev3(27) or + ex2_mantissa_shlev3(28) or + ex2_mantissa_shlev3(29) or + ex2_mantissa_shlev3(30) or + ex2_mantissa_shlev3(31) or + ex2_mantissa_shlev3(32) or + ex2_mantissa_shlev3(33) or + ex2_mantissa_shlev3(34) or + ex2_mantissa_shlev3(35) or + ex2_mantissa_shlev3(36) or + ex2_mantissa_shlev3(37) or + ex2_mantissa_shlev3(38) or + ex2_mantissa_shlev3(39) or + ex2_mantissa_shlev3(40) or + ex2_mantissa_shlev3(41) or + ex2_mantissa_shlev3(42) or + ex2_mantissa_shlev3(43) or + ex2_mantissa_shlev3(44) or + ex2_mantissa_shlev3(45) or + ex2_mantissa_shlev3(46) or + ex2_mantissa_shlev3(47) or + ex2_mantissa_shlev3(48) or + ex2_mantissa_shlev3(49) or + ex2_mantissa_shlev3(50) or + or_reduce( ex4_mantissa_shlev3(1 to 31) ) or + or_reduce( ex2_a(4 to 7) ) or + or_reduce( ex2_c(4 to 11) ) or + or_reduce( ex4_addend1(1 to 11) ) or + or_reduce( ex4_addend2(1 to 11) ) or + or_reduce( ex4_addend3(1 to 11) ) or + s2 or + s3 or + es2 or + es3 ; + + + thold_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => thold_1, + q(0) => thold_0 ); + + sg_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => sg_1 , + q(0) => sg_0 ); + + + lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map ( + clkoff_b => clkoff_b, + thold => thold_0, + sg => sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => thold_0_b ); + + +--==########################################## + + + + act_lat: tri_rlmreg_p generic map (width=> 8, expand_type => expand_type, needs_sreset => 0) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(4), + mpw1_b => mpw1_b(4), + mpw2_b => mpw2_b(0), + vd => vdd, + gd => gnd, + nclk => nclk, + act => fpu_enable, + thold_b => thold_0_b, + sg => sg_0, + scout => act_so , + scin => act_si , + ------------------- + din(0) => act_spare_unused(0), + din(1) => act_spare_unused(1), + din(2) => rf1_act, + din(3) => ex1_act, + din(4) => ex2_act, + din(5) => ex3_act, + din(6) => act_spare_unused(2), + din(7) => act_spare_unused(3), + ------------------- + dout(0) => act_spare_unused(0), + dout(1) => act_spare_unused(1), + dout(2) => ex1_act, + dout(3) => ex2_act, + dout(4) => ex3_act, + dout(5) => ex4_act, + dout(6) => act_spare_unused(2) , + dout(7) => act_spare_unused(3) ); + + +--==########################################## + + +zeros <= (1 to 16 => tidn); + + + + + + + + + ex1_floges <= f_pic_ex1_floges; + ex1_fexptes <= f_pic_ex1_fexptes; + + + + ----------------------------------------------------------------------- + ex2_gst_ctrl_lat : tri_rlmreg_p generic map (expand_type => expand_type, width=> 2, needs_sreset => 0) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(2), + mpw1_b => mpw1_b(2), + mpw2_b => mpw2_b(0), + vd => vdd, gd => gnd, + nclk => nclk, thold_b => thold_0_b, sg => sg_0, + ------------------- + act => ex1_act, + ------------------- + scout => ex2_gst_ctrl_lat_scout, + scin => ex2_gst_ctrl_lat_scin, + ------------------- + din(00) => ex1_floges, + din(01) => ex1_fexptes, + ------------------- + dout(00) => ex2_floges, + dout(01) => ex2_fexptes + ); + ----------------------------------------------------------------------- + + + +------------------------------------------------------------------------ +------------------------------------------------------------------------ + + +f_fmt_ex1_b_expo_gst <= not f_fmt_ex1_b_expo_gst_b; + + ----------------------------------------------------------------------- + ex2_gst_stage_lat: tri_rlmreg_p generic map (expand_type => expand_type, width=> 33, needs_sreset => 0) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(2), + mpw1_b => mpw1_b(2), + mpw2_b => mpw2_b(0), + vd => vdd, gd => gnd, + nclk => nclk, thold_b => thold_0_b, sg => sg_0, + ------------------- + act => ex1_act, + ------------------- + scout => ex2_gst_stage_lat_scout, + scin => ex2_gst_stage_lat_scin, + ------------------- + din(00) => f_fmt_ex1_b_sign_gst, + din(01 to 13) => f_fmt_ex1_b_expo_gst, + din(14 to 32) => f_fmt_ex1_b_frac_gst, + + ------------------- + dout(00) => ex2_b_sign, + dout(01 to 13) => ex2_b_biased_13exp, + dout(14 to 32) => ex2_b_fract + + ); + + +--****************************************************************************** +--* LOG ESTIMATE CALCULATION, FRACTIONAL PORTION +--****************************************************************************** + +ex2_f(1 to 11) <= ex2_b_fract(1 to 11); + + +f1 <= ex2_f(1); +f2 <= ex2_f(2); +f3 <= ex2_f(3); +f4 <= ex2_f(4); +f5 <= ex2_f(5); +f6 <= ex2_f(6); +f7 <= ex2_f(7); +f8 <= ex2_f(8); +f9 <= ex2_f(9); +f10 <= ex2_f(10); + +s1 <= (not f1 and not f2 and not f3 and not f4 ); --0 +s2_0 <= (not f1 and not f2 and not f3 and f4 ) or --1 + (not f1 and not f2 and f3 and not f4 ); --2 +s3_0 <= (not f1 and not f2 and f3 and f4 ) or --3 + (not f1 and f2 and not f3 ); --4,5 +sx <= (not f1 and f2 and f3 )or --6,7 + ( f1 and not f2 and not f3 and not f4 ); --8 +s3_1 <= ( f1 and not f2 and not f3 and f4 ) or --9 + ( f1 and not f2 and f3 ); --10,11 +s2_1 <= ( f1 and f2 ); --12,13,14,15 + +s2 <= s2_0 or s2_1 ; +s3 <= s3_0 or s3_1 ; + + +-------------------------------------------------------------------------------- + +c4 <= sx ; +c5 <= s3_0 or s3_1 ; +c6 <= sx or s2_0; +c7 <= sx or s3_0 ; + + + + + + + +a4 <= (s1 and f3) or + (s2_0 and f2) or + (s2_1 and not f2); + +a5 <= (s1 and f4) or + (s2_0 and f3) or + (s2_1 and not f3) or + (s3_0 and f2) or + (s3_1 and not f2); + +a6 <= (s1 and f5) or + (s2_0 and f4) or + (s2_1 and not f4) or + (s3_0 and f3) or + (s3_1 and not f3); + +a7 <= (s1 and f6) or + (s2_0 and f5) or + (s2_1 and not f5) or + (s3_0 and f4) or + (s3_1 and not f4); + + +a8 <= (s1 and f7) or + (s2_0 and f6) or + (s2_1 and not f6) or + (s3_0 and f5) or + (s3_1 and not f5); + +a9 <= (s1 and f8) or + (s2_0 and f7) or + (s2_1 and not f7) or + (s3_0 and f6) or + (s3_1 and not f6); + +a10 <= (s1 and f9) or + (s2_0 and f8) or + (s2_1 and not f8) or + (s3_0 and f7) or + (s3_1 and not f7); + +a11 <= (s1 and f10) or + (s2_0 and f9) or + (s2_1 and not f9) or + (s3_0 and f8) or + (s3_1 and not f8); + +-------------------------------------------------------------------------------- + +ex2_a(4 to 11) <= a4 & a5 & a6 & a7 & a8 & a9 & a10 & a11; +ex2_c(4 to 11) <= c4 & c5 & c6 & c7 & tidn & tidn & tidn & tidn; + + + + + + + c3_if_s1 <= f4 and f3 ; + c3_if_s20 <= f4 and f2 ; + c3_if_s30 <= tidn ; + c3_if_sx <= f4 ; + c3_if_s31 <= tidn ; + c3_if_s21 <= f4 and not f2 ; + + s4_if_s1 <= f4 xor f3 ; + s4_if_s20 <= f4 xor f2 ; + s4_if_s30 <= f4 ; + s4_if_sx <= not f4 ; + s4_if_s31 <= f4 ; + s4_if_s21 <= f4 xor not f2 ; + + + c4_if_s1 <= f5 and f4 ; + c4_if_s20 <= f5 and f3 ; + c4_if_s30 <= f5 or f2 ; + c4_if_sx <= tidn ; + c4_if_s31 <= f5 or not f2 ; + c4_if_s21 <= f5 and not f3 ; + + s5_if_s1 <= f5 xor f4 ; + s5_if_s20 <= f5 xor f3 ; + s5_if_s30 <= f5 xor not f2 ; + s5_if_sx <= f5 ; + s5_if_s31 <= f5 xor f2 ; + s5_if_s21 <= f5 xor not f3 ; + + + c5_if_s1 <= f6 and f5 ; + c5_if_s20 <= f6 or f4 ; + c5_if_s30 <= f6 and f3 ; + c5_if_sx <= f6 ; + c5_if_s31 <= f6 and not f3 ; + c5_if_s21 <= f6 and not f4 ; + + s6_if_s1 <= f6 xor f5 ; + s6_if_s20 <= f6 xor not f4 ; + s6_if_s30 <= f6 xor f3 ; + s6_if_sx <= not f6 ; + s6_if_s31 <= f6 xor not f3 ; + s6_if_s21 <= f6 xor not f4 ; + + + c6_if_s1 <= f7 and f6 ; + c6_if_s20 <= f7 and f5 ; + c6_if_s30 <= f7 or f4 ; + c6_if_sx <= f7 ; + c6_if_s31 <= f7 and not f4 ; + c6_if_s21 <= f7 and not f5 ; + + s7_if_s1 <= f7 xor f6 ; + s7_if_s20 <= f7 xor f5 ; + s7_if_s30 <= f7 xor not f4 ; + s7_if_sx <= not f7 ; + s7_if_s31 <= f7 xor not f4 ; + s7_if_s21 <= f7 xor not f5 ; + + + + ex2_log_fsum(4) <= + ( s1 and s4_if_s1 ) or + ( s2_0 and s4_if_s20 ) or + ( s3_0 and s4_if_s30 ) or + ( sx and s4_if_sx ) or + ( s3_1 and s4_if_s31 ) or + ( s2_1 and s4_if_s21 ) ; + + ex2_log_fcarryin(3) <= + ( s1 and c3_if_s1 ) or + ( s2_0 and c3_if_s20 ) or + ( s3_0 and c3_if_s30 ) or + ( sx and c3_if_sx ) or + ( s3_1 and c3_if_s31 ) or + ( s2_1 and c3_if_s21 ) ; + + + + ex2_log_fsum(5) <= + ( s1 and s5_if_s1 ) or + ( s2_0 and s5_if_s20 ) or + ( s3_0 and s5_if_s30 ) or + ( sx and s5_if_sx ) or + ( s3_1 and s5_if_s31 ) or + ( s2_1 and s5_if_s21 ) ; + + ex2_log_fcarryin(4) <= + ( s1 and c4_if_s1 ) or + ( s2_0 and c4_if_s20 ) or + ( s3_0 and c4_if_s30 ) or + ( sx and c4_if_sx ) or + ( s3_1 and c4_if_s31 ) or + ( s2_1 and c4_if_s21 ) ; + + + + ex2_log_fsum(6) <= + ( s1 and s6_if_s1 ) or + ( s2_0 and s6_if_s20 ) or + ( s3_0 and s6_if_s30 ) or + ( sx and s6_if_sx ) or + ( s3_1 and s6_if_s31 ) or + ( s2_1 and s6_if_s21 ) ; + + ex2_log_fcarryin(5) <= + ( s1 and c5_if_s1 ) or + ( s2_0 and c5_if_s20 ) or + ( s3_0 and c5_if_s30 ) or + ( sx and c5_if_sx ) or + ( s3_1 and c5_if_s31 ) or + ( s2_1 and c5_if_s21 ) ; + + + + + ex2_log_fsum(7) <= + ( s1 and s7_if_s1 ) or + ( s2_0 and s7_if_s20 ) or + ( s3_0 and s7_if_s30 ) or + ( sx and s7_if_sx ) or + ( s3_1 and s7_if_s31 ) or + ( s2_1 and s7_if_s21 ) ; + + ex2_log_fcarryin(6) <= + ( s1 and c6_if_s1 ) or + ( s2_0 and c6_if_s20 ) or + ( s3_0 and c6_if_s30 ) or + ( sx and c6_if_sx ) or + ( s3_1 and c6_if_s31 ) or + ( s2_1 and c6_if_s21 ) ; + + ex2_log_a_addend_b(1) <= not( ex2_f(1) ) ; + ex2_log_a_addend_b(2) <= not( ex2_f(2) ) ; + ex2_log_a_addend_b(3) <= not( ex2_f(3) ) ; + ex2_log_a_addend_b(4) <= not( ex2_log_fsum(4) ); + ex2_log_a_addend_b(5) <= not( ex2_log_fsum(5) ); + ex2_log_a_addend_b(6) <= not( ex2_log_fsum(6) ); + ex2_log_a_addend_b(7) <= not( ex2_log_fsum(7) ); + ex2_log_a_addend_b(8) <= not( ex2_f(8) ); + ex2_log_a_addend_b(9) <= not( ex2_f(9) ); + ex2_log_a_addend_b(10) <= not( ex2_f(10)); + ex2_log_a_addend_b(11) <= not( ex2_f(11)); + + ex2_log_b_addend_b(1) <= not( tidn ) ; + ex2_log_b_addend_b(2) <= not( tidn ) ; + ex2_log_b_addend_b(3) <= not( ex2_log_fcarryin(3) ); + ex2_log_b_addend_b(4) <= not( ex2_log_fcarryin(4) ); + ex2_log_b_addend_b(5) <= not( ex2_log_fcarryin(5) ); + ex2_log_b_addend_b(6) <= not( ex2_log_fcarryin(6) ); + ex2_log_b_addend_b(7) <= not( tidn ); + ex2_log_b_addend_b(8) <= not( ex2_a(8) ); + ex2_log_b_addend_b(9) <= not( ex2_a(9) ); + ex2_log_b_addend_b(10) <= not( ex2_a(10) ); + ex2_log_b_addend_b(11) <= not( ex2_a(11) ); + + + + +-------------------------------------------------------------------------------- +-- unbias the exponent +-------------------------------------------------------------------------------- +-- bias is DP, so subtract 1023 + +ex2_b_biased_11exp(1 to 11) <= ex2_b_biased_13exp(3 to 13); + +-- add -1023 (10000000001) + +ex2_b_ubexp_sum(01) <= not ex2_b_biased_11exp(01); +ex2_b_ubexp_sum(02 to 10) <= ex2_b_biased_11exp(02 to 10); +ex2_b_ubexp_sum(11) <= not ex2_b_biased_11exp(11); + + +ex2_ube_g2_b(11) <= not( ex2_b_biased_11exp(11) ); +ex2_ube_g2_b(10) <= not( ex2_b_biased_11exp(10) and ex2_b_biased_11exp(11) ); +ex2_ube_g2_b( 9) <= not( ex2_b_biased_11exp( 9) and ex2_b_biased_11exp(10) ); +ex2_ube_g2_b( 8) <= not( ex2_b_biased_11exp( 8) and ex2_b_biased_11exp( 9) ); +ex2_ube_g2_b( 7) <= not( ex2_b_biased_11exp( 7) and ex2_b_biased_11exp( 8) ); +ex2_ube_g2_b( 6) <= not( ex2_b_biased_11exp( 6) and ex2_b_biased_11exp( 7) ); +ex2_ube_g2_b( 5) <= not( ex2_b_biased_11exp( 5) and ex2_b_biased_11exp( 6) ); +ex2_ube_g2_b( 4) <= not( ex2_b_biased_11exp( 4) and ex2_b_biased_11exp( 5) ); +ex2_ube_g2_b( 3) <= not( ex2_b_biased_11exp( 3) and ex2_b_biased_11exp( 4) ); +ex2_ube_g2_b( 2) <= not( ex2_b_biased_11exp( 2) and ex2_b_biased_11exp( 3) ); + + +ex2_ube_g4 (11) <= not( ex2_ube_g2_b(11) ); +ex2_ube_g4 (10) <= not( ex2_ube_g2_b(10) ); +ex2_ube_g4 ( 9) <= not( ex2_ube_g2_b( 9) or ex2_ube_g2_b(11) ); +ex2_ube_g4 ( 8) <= not( ex2_ube_g2_b( 8) or ex2_ube_g2_b(10) ); +ex2_ube_g4 ( 7) <= not( ex2_ube_g2_b( 7) or ex2_ube_g2_b( 9) ); +ex2_ube_g4 ( 6) <= not( ex2_ube_g2_b( 6) or ex2_ube_g2_b( 8) ); +ex2_ube_g4 ( 5) <= not( ex2_ube_g2_b( 5) or ex2_ube_g2_b( 7) ); +ex2_ube_g4 ( 4) <= not( ex2_ube_g2_b( 4) or ex2_ube_g2_b( 6) ); +ex2_ube_g4 ( 3) <= not( ex2_ube_g2_b( 3) or ex2_ube_g2_b( 5) ); +ex2_ube_g4 ( 2) <= not( ex2_ube_g2_b( 2) or ex2_ube_g2_b( 4) ); + +ex2_ube_g8_b(11) <= not( ex2_ube_g4(11) ); +ex2_ube_g8_b(10) <= not( ex2_ube_g4(10) ); +ex2_ube_g8_b( 9) <= not( ex2_ube_g4( 9) ); +ex2_ube_g8_b( 8) <= not( ex2_ube_g4( 8) ); +ex2_ube_g8_b( 7) <= not( ex2_ube_g4( 7) and ex2_ube_g4(11) ); +ex2_ube_g8_b( 6) <= not( ex2_ube_g4( 6) and ex2_ube_g4(10) ); +ex2_ube_g8_b( 5) <= not( ex2_ube_g4( 5) and ex2_ube_g4( 9) ); +ex2_ube_g8_b( 4) <= not( ex2_ube_g4( 4) and ex2_ube_g4( 8) ); +ex2_ube_g8_b( 3) <= not( ex2_ube_g4( 3) and ex2_ube_g4( 7) ); +ex2_ube_g8_b( 2) <= not( ex2_ube_g4( 2) and ex2_ube_g4( 6) ); + +ex2_b_ubexp_cout(11) <= not( ex2_ube_g8_b(11) ) ; +ex2_b_ubexp_cout(10) <= not( ex2_ube_g8_b(10) ) ; +ex2_b_ubexp_cout( 9) <= not( ex2_ube_g8_b( 9) ) ; +ex2_b_ubexp_cout( 8) <= not( ex2_ube_g8_b( 8) ) ; +ex2_b_ubexp_cout( 7) <= not( ex2_ube_g8_b( 7) ) ; +ex2_b_ubexp_cout( 6) <= not( ex2_ube_g8_b( 6) ) ; +ex2_b_ubexp_cout( 5) <= not( ex2_ube_g8_b( 5) ) ; +ex2_b_ubexp_cout( 4) <= not( ex2_ube_g8_b( 4) ) ; +ex2_b_ubexp_cout( 3) <= not( ex2_ube_g8_b( 3) or ex2_ube_g8_b(11) ); +ex2_b_ubexp_cout( 2) <= not( ex2_ube_g8_b( 2) or ex2_ube_g8_b(10) ); + +ex2_b_ubexp(01 to 10) <= ex2_b_ubexp_sum(01 to 10) xor ex2_b_ubexp_cout(02 to 11); +ex2_b_ubexp(11) <= ex2_b_ubexp_sum(11); + +-------------------------------------------------------------------------------- + +ex2_logadd11: entity work.fuq_gst_add11(fuq_gst_add11) port map( -- not really an 11 bit adder + a_b(0 to 10) => ex2_log_a_addend_b(1 to 11), + b_b(0 to 10) => ex2_log_b_addend_b(1 to 11), + -------------------------------------------------------- + s0(0 to 10) => ex2_log_mantissa_precomp(9 to 19) + ); + ----------------------------------------------------------------------- + + + ex2_log_mantissa_precomp(1 to 8) <= ex2_b_ubexp(4 to 11); + +------------------------------------------------------------------------------------------------------------------------ +-- for fexptes, shift mantissa based on the exponent (un-normalize) + +ex2_mantissa_shlev0(00 to 19) <= tiup & ex2_b_fract(01 to 19); + +ex2_shamt(0 to 4) <= ex2_b_ubexp(1) & ex2_b_ubexp(08 to 11); + +--timing note: the shift amount comes after the adder to unbias the exponent. +-- it would be faster to use the biased exponent but use the shift controls different. +-- +-- 1 2 3 4 5 6 7 8 9 A B +-- 0 1 1 1 1 1 1 1 1 1 1 bias =1023 +-- 1 0 0 0 0 0 0 0 0 0 1 add -1023 to unbias +-- for small shifts unbiased 01 = biased 00 +-- for small shifts unbiased 10 = biased 01 +-- for small shifts unbiased 11 = biased 10 +-- for small shifts unbiased 00 = biased 11 + + +ex2_powsh_no_sat_lft <= not ex2_b_ubexp(2) and + not ex2_b_ubexp(3) and + not ex2_b_ubexp(4) and + not ex2_b_ubexp(5) and + not ex2_b_ubexp(6) and + not ex2_b_ubexp(7) ; + +ex2_powsh_no_sat_rgt <= ex2_b_ubexp(2) and + ex2_b_ubexp(3) and + ex2_b_ubexp(4) and + ex2_b_ubexp(5) and + ex2_b_ubexp(6) and + ex2_b_ubexp(7) ; + + +l1_e00 <= not ex2_shamt(3) and not ex2_shamt(4); +l1_e01 <= not ex2_shamt(3) and ex2_shamt(4); +l1_e10 <= ex2_shamt(3) and not ex2_shamt(4); +l1_e11 <= ex2_shamt(3) and ex2_shamt(4); + +l2_e00 <= not ex2_shamt(1) and not ex2_shamt(2); +l2_e01 <= not ex2_shamt(1) and ex2_shamt(2); +l2_e10 <= ex2_shamt(1) and not ex2_shamt(2); +l2_e11 <= ex2_shamt(1) and ex2_shamt(2); + + + l3_e00 <= not ex2_shamt(0) and ex2_powsh_no_sat_lft; + l3_e01 <= ex2_shamt(0) and ex2_powsh_no_sat_rgt; + + +ex2_mantissa_shlev1(00 to 22) <= (zeros(01 to 03) & (ex2_mantissa_shlev0(00 to 19) ) and (00 to 22 => l1_e00)) or + (zeros(01 to 02) & (ex2_mantissa_shlev0(00 to 19) & zeros(01) ) and (00 to 22 => l1_e01)) or + (zeros(01 ) & (ex2_mantissa_shlev0(00 to 19) & zeros(01 to 02)) and (00 to 22 => l1_e10)) or + ( (ex2_mantissa_shlev0(00 to 19) & zeros(01 to 03)) and (00 to 22 => l1_e11)) ; + + +ex2_mantissa_shlev2(00 to 34) <= (zeros(01 to 12) & (ex2_mantissa_shlev1(00 to 22) ) and (00 to 34 => l2_e00)) or + (zeros(01 to 08) & (ex2_mantissa_shlev1(00 to 22) & zeros(01 to 04)) and (00 to 34 => l2_e01)) or + (zeros(01 to 04) & (ex2_mantissa_shlev1(00 to 22) & zeros(01 to 08)) and (00 to 34 => l2_e10)) or + ( (ex2_mantissa_shlev1(00 to 22) & zeros(01 to 12)) and (00 to 34 => l2_e11)) ; + + +ex2_mantissa_shlev3(00 to 50) <= ( (ex2_mantissa_shlev2(00 to 34) & zeros(01 to 16)) and (00 to 50 => l3_e00)) or + (zeros(01 to 16) & (ex2_mantissa_shlev2(00 to 34) ) and (00 to 50 => l3_e01)) ; + + +ex2_pow_int(1 to 8) <= ex2_mantissa_shlev3(08 to 15); +ex2_pow_frac(1 to 11) <= ex2_mantissa_shlev3(16 to 26); + + + +ex2_mantissa_din(1 to 19) <= ((ex2_pow_int(1 to 8) & ex2_pow_frac(1 to 11)) and (1 to 19 => ex2_fexptes)) or + (ex2_log_mantissa_precomp(1 to 19) and (1 to 19 => ex2_floges )); + + ----------------------------------------------------------------------- + ----------------------------------------------------------------------- + ----------------------------------------------------------------------- + ----------------------------------------------------------------------- + ex3_gst_ctrl_lat : tri_rlmreg_p generic map (expand_type => expand_type, width=> 2, needs_sreset => 0) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(3), + mpw1_b => mpw1_b(3), + mpw2_b => mpw2_b(0), + vd => vdd, gd => gnd, + nclk => nclk, thold_b => thold_0_b, sg => sg_0, + ------------------- + act => ex2_act, + ------------------- + scout => ex3_gst_ctrl_lat_scout, + scin => ex3_gst_ctrl_lat_scin, + ------------------- + din(00) => ex2_floges, + din(01) => ex2_fexptes, + ------------------- + dout(00) => ex3_floges, + dout(01) => ex3_fexptes + ); + ----------------------------------------------------------------------- + + ex3_gst_stage_lat: tri_rlmreg_p generic map (expand_type => expand_type, width => 20, needs_sreset => 0 ) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(3), + mpw1_b => mpw1_b(3), + mpw2_b => mpw2_b(0), + vd => vdd, gd => gnd, + nclk => nclk, thold_b => thold_0_b, sg => sg_0, + ------------------- + act => ex2_act, + ------------------- + scout => ex3_gst_stage_lat_scout, + scin => ex3_gst_stage_lat_scin, + ------------------- + din(00 to 18) => ex2_mantissa_din, + din(19) => ex2_b_sign, + ------------------- + dout(00 to 18) => ex3_mantissa_precomp, + dout(19) => ex3_b_sign + + ); + ----------------------------------------------------------------------- + ----------------------------------------------------------------------- + ----------------------------------------------------------------------- + + +ex3_mantissa_precomp_b <= not ex3_mantissa_precomp(1 to 19); + + ----------------------------------------------------------------------- +ex3_log_inc: entity work.fuq_gst_inc19(fuq_gst_inc19) port map( + a(1 to 19) => ex3_mantissa_precomp_b(1 to 19), + -------------------------------------------------------- + o(1 to 19) => ex3_mantissa_neg(1 to 19) + ); + ----------------------------------------------------------------------- + +ex3_negate <= (ex3_mantissa_precomp(1) and ex3_floges) or (ex3_fexptes and ex3_b_sign); + + ex3_mantissa(1 to 19) <= ( ex3_mantissa_neg(1 to 19) and (1 to 19 => ex3_negate)) or + ( ex3_mantissa_precomp(1 to 19) and not (1 to 19 => ex3_negate)); + + + + ----------------------------------------------------------------------- +ex3_log_loa: entity work.fuq_gst_loa(fuq_gst_loa) port map( + a(1 to 19) => ex3_mantissa, + -------------------------------------------------------- + shamt(0 to 4) => ex3_shamt(0 to 4) + ); + ----------------------------------------------------------------------- + +ex3_logof1_specialcase <= not or_reduce(ex3_shamt(0 to 4)); + + ----------------------------------------------------------------------- + ex4_gst_ctrl_lat : tri_rlmreg_p generic map (expand_type => expand_type, width=> 4, needs_sreset => 0) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(4), + mpw1_b => mpw1_b(4), + mpw2_b => mpw2_b(0), + vd => vdd, gd => gnd, + nclk => nclk, thold_b => thold_0_b, sg => sg_0, + ------------------- + act => ex3_act, + ------------------- + scout => ex4_gst_ctrl_lat_scout, + scin => ex4_gst_ctrl_lat_scin, + ------------------- + din(00) => ex3_floges, + din(01) => ex3_fexptes, + din(02) => ex3_negate, + din(03) => ex3_logof1_specialcase, + ------------------- + dout(00) => ex4_floges, + dout(01) => ex4_fexptes, + dout(02) => ex4_negate, + dout(03) => ex4_logof1_specialcase + ); + + + ex4_gst_stage_lat: tri_rlmreg_p generic map (expand_type => expand_type, width => 24, needs_sreset => 0 ) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(4), + mpw1_b => mpw1_b(4), + mpw2_b => mpw2_b(0), + vd => vdd, gd => gnd, + nclk => nclk, thold_b => thold_0_b, sg => sg_0, + ------------------- + act => ex3_act, + ------------------- + scout => ex4_gst_stage_lat_scout, + scin => ex4_gst_stage_lat_scin, + ------------------- + din(00 to 18) => ex3_mantissa, + din(19 to 23) => ex3_shamt, + ------------------- + dout(00 to 18) => ex4_mantissa, + dout(19 to 23) => ex4_shamt + ); + ----------------------------------------------------------------------- + ----------------------------------------------------------------------- + ----------------------------------------------------------------------- + +-- shift mantissa for log (shamt is set to zeros for exp) +-- log mantissa gets normalized here + + + +ex4_mantissa_shlev0(01 to 19) <= ex4_mantissa(01 to 19); + + +l1_enc00 <= not ex4_shamt(3) and not ex4_shamt(4); +l1_enc01 <= not ex4_shamt(3) and ex4_shamt(4); +l1_enc10 <= ex4_shamt(3) and not ex4_shamt(4); +l1_enc11 <= ex4_shamt(3) and ex4_shamt(4); + +l2_enc00 <= not ex4_shamt(1) and not ex4_shamt(2); +l2_enc01 <= not ex4_shamt(1) and ex4_shamt(2); +l2_enc10 <= ex4_shamt(1) and not ex4_shamt(2); +l2_enc11 <= ex4_shamt(1) and ex4_shamt(2); + +l3_enc00 <= not ex4_shamt(0); +l3_enc01 <= ex4_shamt(0); + + + + + + +ex4_mantissa_shlev1(01 to 22) <= (zeros(01 to 03) & (ex4_mantissa_shlev0(01 to 19) ) and (01 to 22 => l1_enc00)) or + (zeros(01 to 02) & (ex4_mantissa_shlev0(01 to 19) & zeros(01) ) and (01 to 22 => l1_enc01)) or + (zeros(01 ) & (ex4_mantissa_shlev0(01 to 19) & zeros(01 to 02)) and (01 to 22 => l1_enc10)) or + ( (ex4_mantissa_shlev0(01 to 19) & zeros(01 to 03)) and (01 to 22 => l1_enc11)) ; + + + +ex4_mantissa_shlev2(01 to 34) <= (zeros(01 to 12) & (ex4_mantissa_shlev1(01 to 22) ) and (01 to 34 => l2_enc00)) or + (zeros(01 to 08) & (ex4_mantissa_shlev1(01 to 22) & zeros(01 to 04)) and (01 to 34 => l2_enc01)) or + (zeros(01 to 04) & (ex4_mantissa_shlev1(01 to 22) & zeros(01 to 08)) and (01 to 34 => l2_enc10)) or + ( (ex4_mantissa_shlev1(01 to 22) & zeros(01 to 12)) and (01 to 34 => l2_enc11)) ; + + +ex4_mantissa_shlev3(01 to 50) <= (zeros(01 to 16) & (ex4_mantissa_shlev2(01 to 34) ) and (01 to 50 => l3_enc00)) or + ( (ex4_mantissa_shlev2(01 to 34) & zeros(01 to 16)) and (01 to 50 => l3_enc01)) ; + + + + +ex4_log_mantissa_postsh(01 to 19) <= ex4_mantissa_shlev3(32 to 50); + +------------------------------------------------------------------------------------------------------------------------ +-- pow fract logic + +ex4_f(1 to 11) <= ex4_mantissa(9 to 19); +-- ************************************ +-- ** vexptefp fract logic +-- ************************************ + + eb1 <= ex4_f(1); + eb2 <= ex4_f(2); + eb3 <= ex4_f(3); + eb4 <= ex4_f(4); + eb5 <= ex4_f(5); + eb6 <= ex4_f(6); + eb7 <= ex4_f(7); + eb8 <= ex4_f(8); + eb9 <= ex4_f(9); + eb10 <= ex4_f(10); + + ex4_f_b(1 to 11) <= not ex4_f(1 to 11); + +--0000 ^s2 +--0001 ^s2 +--0010 ^s2 +--0011 ^s2 +--0100 ^s3 +--0101 ^s3 +--0110 ^s3 +--0111 -- +--1000 -- +--1001 -- +--1010 s3 +--1011 s3 +--1100 s3 +--1101 s2 +--1110 s2 +--1111 s1 + + es2_0 <= ( not eb1 and not eb2 ) ;--0,1,2,3 + es3_0 <= ( not eb1 and eb2 and not eb3 ) or --4,5 + ( not eb1 and eb2 and eb3 and not eb4 ) ;--6 + esx <= ( not eb1 and eb2 and eb3 and eb4 ) or --7 + ( eb1 and not eb2 and not eb3 ) ;--8,9 + es3_1 <= ( eb1 and not eb2 and eb3 ) or --10,11 + ( eb1 and eb2 and not eb3 and not eb4 ) ;--12 + es2_1 <= ( eb1 and eb2 and not eb3 and eb4 ) or --13 + ( eb1 and eb2 and eb3 and not eb4 ) ;--14 + es1 <= ( eb1 and eb2 and eb3 and eb4 ) ;--15 + + es2 <= es2_0 or es2_1; + es3 <= es3_0 or es3_1; + + ec4 <= esx ; + ec5 <= es3_0 or es3_1; + ec6 <= esx or es2_1; + ec7 <= esx or es3_1; + + + + + ec3_if_s20 <= not eb4 and eb2 ; + ec3_if_s30 <= tidn ; + ec3_if_sx <= not eb4 ; + ec3_if_s31 <= tidn ; + ec3_if_s21 <= not eb4 and not eb2 ; + ec3_if_s1 <= not eb4 and not eb3 ; + + es4_if_s20 <= not eb4 xor eb2 ; + es4_if_s30 <= not eb4 ; + es4_if_sx <= eb4 ; + es4_if_s31 <= not eb4 ; + es4_if_s21 <= not eb4 xor not eb2 ; + es4_if_s1 <= not eb4 xor not eb3 ; + + + ec4_if_s20 <= not eb5 and eb3 ; + ec4_if_s30 <= not eb5 or eb2 ; + ec4_if_sx <= tidn ; + ec4_if_s31 <= not eb5 or not eb2 ; + ec4_if_s21 <= not eb5 and not eb3 ; + ec4_if_s1 <= not eb5 and not eb4 ; + + es5_if_s20 <= not eb5 xor eb3 ; + es5_if_s30 <= not eb5 xor not eb2 ; + es5_if_sx <= not eb5 ; + es5_if_s31 <= not eb5 xor eb2 ; + es5_if_s21 <= not eb5 xor not eb3 ; + es5_if_s1 <= not eb5 xor not eb4 ; + + + ec5_if_s20 <= not eb6 and eb4 ; + ec5_if_s30 <= not eb6 and eb3 ; + ec5_if_sx <= not eb6 ; + ec5_if_s31 <= not eb6 and not eb3 ; + ec5_if_s21 <= not eb6 or not eb4 ; + ec5_if_s1 <= not eb6 and not eb5 ; + + es6_if_s20 <= not eb6 xor eb4 ; + es6_if_s30 <= not eb6 xor eb3 ; + es6_if_sx <= eb6 ; + es6_if_s31 <= not eb6 xor not eb3 ; + es6_if_s21 <= not eb6 xor eb4 ; + es6_if_s1 <= not eb6 xor not eb5 ; + + ec6_if_s20 <= not eb7 and eb5 ; + ec6_if_s30 <= not eb7 and eb4 ; + ec6_if_sx <= not eb7 ; + ec6_if_s31 <= not eb7 or not eb4 ; + ec6_if_s21 <= not eb7 and not eb5 ; + ec6_if_s1 <= not eb7 and not eb6 ; + + es7_if_s20 <= not eb7 xor eb5 ; + es7_if_s30 <= not eb7 xor eb4 ; + es7_if_sx <= eb7 ; + es7_if_s31 <= not eb7 xor eb4 ; + es7_if_s21 <= not eb7 xor not eb5 ; + es7_if_s1 <= not eb7 xor not eb6 ; + + + + + + + + + ea4 <= (es1 and not eb3) or + (es2_0 and eb2) or + (es2_1 and not eb2); + + ea5 <= (es1 and not eb4) or + (es2_0 and eb3) or + (es2_1 and not eb3) or + (es3_0 and eb2) or + (es3_1 and not eb2); + + ea6 <= (es1 and not eb5) or + (es2_0 and eb4) or + (es2_1 and not eb4) or + (es3_0 and eb3) or + (es3_1 and not eb3); + + ea7 <= (es1 and not eb6) or + (es2_0 and eb5) or + (es2_1 and not eb5) or + (es3_0 and eb4) or + (es3_1 and not eb4); + + ea8 <= (es1 and not eb7) or + (es2_0 and eb6) or + (es2_1 and not eb6) or + (es3_0 and eb5) or + (es3_1 and not eb5); + + ea9 <= (es1 and not eb8) or + (es2_0 and eb7) or + (es2_1 and not eb7) or + (es3_0 and eb6) or + (es3_1 and not eb6); + + ea10 <= (es1 and not eb9) or + (es2_0 and eb8) or + (es2_1 and not eb8) or + (es3_0 and eb7) or + (es3_1 and not eb7); + + ea11 <= (es1 and not eb10) or + (es2_0 and eb9) or + (es2_1 and not eb9) or + (es3_0 and eb8) or + (es3_1 and not eb8); + + +-------------------------------------------------------------------------------- + + + +ex4_ea(4 to 11) <= ea4 & ea5 & ea6 & ea7 & ea8 & ea9 & ea10 & ea11; +ex4_ec(4 to 11) <= ec4 & ec5 & ec6 & ec7 & zeros(1 to 4); + +ex4_addend1(1 to 11) <= ex4_f_b(1 to 11); +ex4_addend2(1 to 11) <= zeros(1 to 3) & ex4_ea(4 to 11); +ex4_addend3(1 to 11) <= zeros(1 to 3) & ex4_ec(4 to 11); + + ex4_fsum(1) <= ex4_f_b(1) ; + ex4_fsum(2) <= ex4_f_b(2) ; + ex4_fsum(3) <= ex4_f_b(3) ; + ex4_fsum(4) <= + ( es1 and es4_if_s1 ) or + ( es2_0 and es4_if_s20 ) or + ( es3_0 and es4_if_s30 ) or + ( esx and es4_if_sx ) or + ( es3_1 and es4_if_s31 ) or + ( es2_1 and es4_if_s21 ) ; + ex4_fsum(5) <= + ( es1 and es5_if_s1 ) or + ( es2_0 and es5_if_s20 ) or + ( es3_0 and es5_if_s30 ) or + ( esx and es5_if_sx ) or + ( es3_1 and es5_if_s31 ) or + ( es2_1 and es5_if_s21 ) ; + ex4_fsum(6) <= + ( es1 and es6_if_s1 ) or + ( es2_0 and es6_if_s20 ) or + ( es3_0 and es6_if_s30 ) or + ( esx and es6_if_sx ) or + ( es3_1 and es6_if_s31 ) or + ( es2_1 and es6_if_s21 ) ; + ex4_fsum(7) <= + ( es1 and es7_if_s1 ) or + ( es2_0 and es7_if_s20 ) or + ( es3_0 and es7_if_s30 ) or + ( esx and es7_if_sx ) or + ( es3_1 and es7_if_s31 ) or + ( es2_1 and es7_if_s21 ) ; + ex4_fsum(8) <= ex4_f_b(8) ; + ex4_fsum(9) <= ex4_f_b(9) ; + ex4_fsum(10) <= ex4_f_b(10) ; + ex4_fsum(11) <= ex4_f_b(11) ; + + + + ex4_fcarryin(1) <= tidn; + ex4_fcarryin(2) <= tidn; + ex4_fcarryin(3) <= + ( es1 and ec3_if_s1 ) or + ( es2_0 and ec3_if_s20 ) or + ( es3_0 and ec3_if_s30 ) or + ( esx and ec3_if_sx ) or + ( es3_1 and ec3_if_s31 ) or + ( es2_1 and ec3_if_s21 ) ; + ex4_fcarryin(4) <= + ( es1 and ec4_if_s1 ) or + ( es2_0 and ec4_if_s20 ) or + ( es3_0 and ec4_if_s30 ) or + ( esx and ec4_if_sx ) or + ( es3_1 and ec4_if_s31 ) or + ( es2_1 and ec4_if_s21 ) ; + ex4_fcarryin(5) <= + ( es1 and ec5_if_s1 ) or + ( es2_0 and ec5_if_s20 ) or + ( es3_0 and ec5_if_s30 ) or + ( esx and ec5_if_sx ) or + ( es3_1 and ec5_if_s31 ) or + ( es2_1 and ec5_if_s21 ) ; + ex4_fcarryin(6) <= + ( es1 and ec6_if_s1 ) or + ( es2_0 and ec6_if_s20 ) or + ( es3_0 and ec6_if_s30 ) or + ( esx and ec6_if_sx ) or + ( es3_1 and ec6_if_s31 ) or + ( es2_1 and ec6_if_s21 ) ; + ex4_fcarryin(7) <= tidn ; + ex4_fcarryin(8) <= ea8 ; + ex4_fcarryin(9) <= ea9 ; + ex4_fcarryin(10) <= ea10 ; + ex4_fcarryin(11) <= ea11 ; + +ex4_powf_a_addend_b <= not ex4_fsum(1 to 11); +ex4_powf_b_addend_b <= not (ex4_fcarryin(1 to 11) ); + +ex4_powfractadd11: entity work.fuq_gst_add11(fuq_gst_add11) port map( + a_b(0 to 10) => ex4_powf_a_addend_b, + b_b(0 to 10) => ex4_powf_b_addend_b, + -------------------------------------------------------- + s0(0 to 10) => ex4_pow_fract_b + ); + +ex4_pow_fract <= not ex4_pow_fract_b; + + +------------------------------------------------------------------------------------------------------------------------ +ex4_log_dp_bias <= ("01111110111" and (1 to 11 => not ex4_logof1_specialcase)) or -- not (dp bias +9) + ("11111111101" and (1 to 11 => ex4_logof1_specialcase)); -- results in exp of 000..1, which is zero + +ex4_log_a_addend_b(1 to 11) <= zeros(1 to 6) & ex4_shamt(0 to 4); +ex4_log_b_addend_b(1 to 11) <= ex4_log_dp_bias; + +ex4_pow_a_addend_b(1 to 11) <= not (ex4_mantissa(1) & ex4_mantissa(1) & ex4_mantissa(1) & ex4_mantissa(1 to 8)); +ex4_pow_b_addend_b(1 to 11) <= "10000000000"; -- dp bias + + +ex4_exponent_a_addend_b <= (ex4_log_a_addend_b and (1 to 11 => ex4_floges )) or + (ex4_pow_a_addend_b and (1 to 11 => ex4_fexptes)) ; + +ex4_exponent_b_addend_b <= (ex4_log_b_addend_b and (1 to 11 => ex4_floges )) or + (ex4_pow_b_addend_b and (1 to 11 => ex4_fexptes)) ; + + ----------------------------------------------------------------------- + +ex4_explogadd11: entity work.fuq_gst_add11(fuq_gst_add11) port map( + a_b(0 to 10) => ex4_exponent_a_addend_b, + b_b(0 to 10) => ex4_exponent_b_addend_b, + -------------------------------------------------------- + s0(0 to 10) => ex4_biased_exponent_result + ); + ----------------------------------------------------------------------- + + + + + ex4_log_fract <= ex4_log_mantissa_postsh(01 to 19); + ex4_log_signbit <= ex4_negate; + + + ex4_signbit_din <= ex4_log_signbit and ex4_floges; + + + ex4_fract_din <= (((not ex4_logof1_specialcase) & ex4_log_fract(1 to 19)) and (0 to 19 => ex4_floges )) or + ((tiup & ex4_pow_fract(1 to 11) & zeros(1 to 8)) and (0 to 19 => ex4_fexptes)) ; + + ----------------------------------------------------------------------- + ----------------------------------------------------------------------- + ----------------------------------------------------------------------- + ex5_gst_ctrl_lat : tri_rlmreg_p generic map (expand_type => expand_type, width=> 2, needs_sreset => 0) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(5), + mpw1_b => mpw1_b(5), + mpw2_b => mpw2_b(1), + vd => vdd, gd => gnd, + nclk => nclk, thold_b => thold_0_b, sg => sg_0, + ------------------- + act => ex4_act, + ------------------- + scout => ex5_gst_ctrl_lat_scout, + scin => ex5_gst_ctrl_lat_scin, + ------------------- + din(00) => ex4_floges, + din(01) => ex4_fexptes, + ------------------- + dout(00) => ex5_floges, + dout(01) => ex5_fexptes + ); + + + + ex5_gst_stage_lat: tri_rlmreg_p generic map (expand_type => expand_type, width => 32, needs_sreset => 0 ) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(5), + mpw1_b => mpw1_b(5), + mpw2_b => mpw2_b(1), + vd => vdd, gd => gnd, + nclk => nclk, thold_b => thold_0_b, sg => sg_0, + ------------------- + act => ex4_act, + ------------------- + scout => ex5_gst_stage_lat_scout, + scin => ex5_gst_stage_lat_scin, + ------------------- + din(00) => ex4_signbit_din, + din(01 to 11) => ex4_biased_exponent_result, + din(12 to 31) => ex4_fract_din, + ------------------- + dout(00) => ex5_signbit, + dout(01 to 11) => ex5_biased_exponent_result, + dout(12 to 31) => ex5_fract + + ); + + + ----------------------------------------------------------------------- + ----------------------------------------------------------------------- + ----------------------------------------------------------------------- + + + f_gst_ex5_logexp_sign <= ex5_signbit; + f_gst_ex5_logexp_exp <= ex5_biased_exponent_result; + f_gst_ex5_logexp_fract <= ex5_fract; + f_gst_ex5_logexp_v <= ex5_floges or ex5_fexptes; + + + +ex2_gst_ctrl_lat_scin(0 to 1) <= f_gst_si & ex2_gst_ctrl_lat_scout(0); +ex3_gst_ctrl_lat_scin(0 to 1) <= ex2_gst_ctrl_lat_scout(1) & ex3_gst_ctrl_lat_scout(0); +ex4_gst_ctrl_lat_scin(0 to 3) <= ex3_gst_ctrl_lat_scout(1) & ex4_gst_ctrl_lat_scout(0 to 2); +ex5_gst_ctrl_lat_scin(0 to 1) <= ex4_gst_ctrl_lat_scout(3) & ex5_gst_ctrl_lat_scout(0); +ex2_gst_stage_lat_scin(0 to 32) <= ex5_gst_ctrl_lat_scout(1) & ex2_gst_stage_lat_scout(0 to 31); +ex3_gst_stage_lat_scin(0 to 19) <= ex2_gst_stage_lat_scout(32) & ex3_gst_stage_lat_scout(0 to 18); +ex4_gst_stage_lat_scin(0 to 23) <= ex3_gst_stage_lat_scout(19) & ex4_gst_stage_lat_scout(0 to 22); +ex5_gst_stage_lat_scin(0 to 31) <= ex4_gst_stage_lat_scout(23) & ex5_gst_stage_lat_scout(0 to 30); + + +act_si(0 to 7) <= act_so(1 to 7) & ex5_gst_stage_lat_scout(31); + +f_gst_so <= act_so(0); + + + +end fuq_gst; diff --git a/rel/src/vhdl/work/fuq_gst_add11.vhdl b/rel/src/vhdl/work/fuq_gst_add11.vhdl new file mode 100644 index 0000000..0fc58a2 --- /dev/null +++ b/rel/src/vhdl/work/fuq_gst_add11.vhdl @@ -0,0 +1,173 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +--//############################################################################ +--//##### FUQ_GEST_add11.VHDL ######### +--//##### side pipe for graphics estimates ######### +--//##### flogefp, fexptefp ######### +--//##### ######### +--//############################################################################ + + +library ieee; + use ieee.std_logic_1164.all ; +library ibm; + + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; +library support; +use support.power_logic_pkg.all; +library tri; use tri.tri_latches_pkg.all; + +entity fuq_gst_add11 is + port( + a_b :in std_ulogic_vector(0 to 10);-- inverted adder input + b_b :in std_ulogic_vector(0 to 10);-- inverted adder input + s0 :out std_ulogic_vector(0 to 10) + + ); + + + + +end fuq_gst_add11; + +architecture fuq_gst_add11 of fuq_gst_add11 is + + signal p1 :std_ulogic_vector(0 to 10); + signal g1 :std_ulogic_vector(1 to 10); + signal t1 :std_ulogic_vector(1 to 9); + signal g2_b :std_ulogic_vector(1 to 10); + signal g4 :std_ulogic_vector(1 to 10); + signal g8_b :std_ulogic_vector(1 to 10); + signal c16 :std_ulogic_vector(1 to 10); + signal t2_b :std_ulogic_vector(1 to 8); + signal t4 :std_ulogic_vector(1 to 6); + signal t8_b :std_ulogic_vector(1 to 2); + + + + + + +begin + + +u_p1: p1(0 to 10) <= ( a_b(0 to 10) xor b_b(0 to 10) ); +u_g1: g1(1 to 10) <= not( a_b(1 to 10) or b_b(1 to 10) ); +u_t1: t1(1 to 9) <= not( a_b(1 to 9) and b_b(1 to 9) ); + +----------------------------------------------- +-- carry chain --- +----------------------------------------------- + + u_g2_01: g2_b(1) <= not( g1(1) or ( t1(1) and g1(2) ) ); + u_g2_02: g2_b(2) <= not( g1(2) or ( t1(2) and g1(3) ) ); + u_g2_03: g2_b(3) <= not( g1(3) or ( t1(3) and g1(4) ) ); + u_g2_04: g2_b(4) <= not( g1(4) or ( t1(4) and g1(5) ) ); + u_g2_05: g2_b(5) <= not( g1(5) or ( t1(5) and g1(6) ) ); + u_g2_06: g2_b(6) <= not( g1(6) or ( t1(6) and g1(7) ) ); + u_g2_07: g2_b(7) <= not( g1(7) or ( t1(7) and g1(8) ) ); + u_g2_08: g2_b(8) <= not( g1(8) or ( t1(8) and g1(9) ) ); + u_g2_09: g2_b(9) <= not( g1(9) or ( t1(9) and g1(10) ) ); + u_g2_10: g2_b(10) <= not( g1(10) ); + + u_t2_01: t2_b(1) <= not( t1(1) and t1(2) ); + u_t2_02: t2_b(2) <= not( t1(2) and t1(3) ); + u_t2_03: t2_b(3) <= not( t1(3) and t1(4) ); + u_t2_04: t2_b(4) <= not( t1(4) and t1(5) ); + u_t2_05: t2_b(5) <= not( t1(5) and t1(6) ); + u_t2_06: t2_b(6) <= not( t1(6) and t1(7) ); + u_t2_07: t2_b(7) <= not( t1(7) and t1(8) ); + u_t2_08: t2_b(8) <= not( t1(8) and t1(9) ); + + + + u_g4_01: g4(1) <= not( g2_b(1) and ( t2_b(1) or g2_b(3) ) ); + u_g4_02: g4(2) <= not( g2_b(2) and ( t2_b(2) or g2_b(4) ) ); + u_g4_03: g4(3) <= not( g2_b(3) and ( t2_b(3) or g2_b(5) ) ); + u_g4_04: g4(4) <= not( g2_b(4) and ( t2_b(4) or g2_b(6) ) ); + u_g4_05: g4(5) <= not( g2_b(5) and ( t2_b(5) or g2_b(7) ) ); + u_g4_06: g4(6) <= not( g2_b(6) and ( t2_b(6) or g2_b(8) ) ); + u_g4_07: g4(7) <= not( g2_b(7) and ( t2_b(7) or g2_b(9) ) ); + u_g4_08: g4(8) <= not( g2_b(8) and ( t2_b(8) or g2_b(10) ) ); + u_g4_09: g4(9) <= not( g2_b(9) ); + u_g4_10: g4(10) <= not( g2_b(10) ); + + u_t4_01: t4(1) <= not( t2_b(1) or t2_b(3) ); + u_t4_02: t4(2) <= not( t2_b(2) or t2_b(4) ); + u_t4_03: t4(3) <= not( t2_b(3) or t2_b(5) ); + u_t4_04: t4(4) <= not( t2_b(4) or t2_b(6) ); + u_t4_05: t4(5) <= not( t2_b(5) or t2_b(7) ); + u_t4_06: t4(6) <= not( t2_b(6) or t2_b(8) ); + + + + u_g8_01: g8_b(1) <= not( g4(1) or ( t4(1) and g4(5) ) ); + u_g8_02: g8_b(2) <= not( g4(2) or ( t4(2) and g4(6) ) ); + u_g8_03: g8_b(3) <= not( g4(3) or ( t4(3) and g4(7) ) ); + u_g8_04: g8_b(4) <= not( g4(4) or ( t4(4) and g4(8) ) ); + u_g8_05: g8_b(5) <= not( g4(5) or ( t4(5) and g4(9) ) ); + u_g8_06: g8_b(6) <= not( g4(6) or ( t4(6) and g4(10) ) ); + u_g8_07: g8_b(7) <= not( g4(7) ); + u_g8_08: g8_b(8) <= not( g4(8) ); + u_g8_09: g8_b(9) <= not( g4(9) ); + u_g8_10: g8_b(10) <= not( g4(10) ); + + u_t8_01: t8_b(1) <= not( t4(1) and t4(5) ); + u_t8_02: t8_b(2) <= not( t4(2) and t4(6) ); + + u_c16_01: c16(1) <= not( g8_b(1) and ( t8_b(1) or g8_b(9) ) ); + u_c16_02: c16(2) <= not( g8_b(2) and ( t8_b(2) or g8_b(10) ) ); + u_c16_03: c16(3) <= not( g8_b(3) ); + u_c16_04: c16(4) <= not( g8_b(4) ); + u_c16_05: c16(5) <= not( g8_b(5) ); + u_c16_06: c16(6) <= not( g8_b(6) ); + u_c16_07: c16(7) <= not( g8_b(7) ); + u_c16_08: c16(8) <= not( g8_b(8) ); + u_c16_09: c16(9) <= not( g8_b(9) ); + u_c16_10: c16(10) <= not( g8_b(10) ); + + +----------------------------------------------- +-- final result --- +----------------------------------------------- + + + s0(0 to 9) <= p1(0 to 9) xor c16(1 to 10); + s0(10) <= p1(10) ; + + +end fuq_gst_add11 ; + + + diff --git a/rel/src/vhdl/work/fuq_gst_inc19.vhdl b/rel/src/vhdl/work/fuq_gst_inc19.vhdl new file mode 100644 index 0000000..73bba05 --- /dev/null +++ b/rel/src/vhdl/work/fuq_gst_inc19.vhdl @@ -0,0 +1,185 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +--//############################################################################ +--//##### FUQ_GEST_inc19.VHDL ######### +--//##### side pipe for graphics estimates ######### +--//##### flogefp, fexptefp ######### +--//##### ######### +--//############################################################################ + + +library ieee; + use ieee.std_logic_1164.all ; +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; +library support; +use support.power_logic_pkg.all; + +library tri; use tri.tri_latches_pkg.all; + + +entity fuq_gst_inc19 is + port( + a :in std_ulogic_vector(1 to 19); + + o :out std_ulogic_vector(1 to 19) + + ); + + + + +end fuq_gst_inc19; + +architecture fuq_gst_inc19 of fuq_gst_inc19 is + + signal a_sum :std_ulogic_vector(01 to 19); + signal a_cout_b :std_ulogic_vector(02 to 19); + signal g2_b, g4, g8_b, g16 :std_ulogic_vector(02 to 19); + + + +begin + + + +g2_b(19) <= not( a(19) ); +g2_b(18) <= not( a(18) and a(19) ); +g2_b(17) <= not( a(17) and a(18) ); +g2_b(16) <= not( a(16) and a(17) ); +g2_b(15) <= not( a(15) and a(16) ); +g2_b(14) <= not( a(14) and a(15) ); +g2_b(13) <= not( a(13) and a(14) ); +g2_b(12) <= not( a(12) and a(13) ); +g2_b(11) <= not( a(11) and a(12) ); +g2_b(10) <= not( a(10) and a(11) ); +g2_b( 9) <= not( a( 9) and a(10) ); +g2_b( 8) <= not( a( 8) and a( 9) ); +g2_b( 7) <= not( a( 7) and a( 8) ); +g2_b( 6) <= not( a( 6) and a( 7) ); +g2_b( 5) <= not( a( 5) and a( 6) ); +g2_b( 4) <= not( a( 4) and a( 5) ); +g2_b( 3) <= not( a( 3) and a( 4) ); +g2_b( 2) <= not( a( 2) and a( 3) ); + + +g4(19) <= not( g2_b(19) ) ; +g4(18) <= not( g2_b(18) ) ; +g4(17) <= not( g2_b(17) or g2_b(19) ) ; +g4(16) <= not( g2_b(16) or g2_b(18) ) ; +g4(15) <= not( g2_b(15) or g2_b(17) ) ; +g4(14) <= not( g2_b(14) or g2_b(16) ) ; +g4(13) <= not( g2_b(13) or g2_b(15) ) ; +g4(12) <= not( g2_b(12) or g2_b(14) ) ; +g4(11) <= not( g2_b(11) or g2_b(13) ) ; +g4(10) <= not( g2_b(10) or g2_b(12) ) ; +g4( 9) <= not( g2_b( 9) or g2_b(11) ) ; +g4( 8) <= not( g2_b( 8) or g2_b(10) ) ; +g4( 7) <= not( g2_b( 7) or g2_b( 9) ) ; +g4( 6) <= not( g2_b( 6) or g2_b( 8) ) ; +g4( 5) <= not( g2_b( 5) or g2_b( 7) ) ; +g4( 4) <= not( g2_b( 4) or g2_b( 6) ) ; +g4( 3) <= not( g2_b( 3) or g2_b( 5) ) ; +g4( 2) <= not( g2_b( 2) or g2_b( 4) ) ; + + +g8_b(19) <= not( g4(19) ) ; +g8_b(18) <= not( g4(18) ) ; +g8_b(17) <= not( g4(17) ) ; +g8_b(16) <= not( g4(16) ) ; +g8_b(15) <= not( g4(15) and g4(19) ) ; +g8_b(14) <= not( g4(14) and g4(18) ) ; +g8_b(13) <= not( g4(13) and g4(17) ) ; +g8_b(12) <= not( g4(12) and g4(16) ) ; +g8_b(11) <= not( g4(11) and g4(15) ) ; +g8_b(10) <= not( g4(10) and g4(14) ) ; +g8_b( 9) <= not( g4( 9) and g4(13) ) ; +g8_b( 8) <= not( g4( 8) and g4(12) ) ; +g8_b( 7) <= not( g4( 7) and g4(11) ) ; +g8_b( 6) <= not( g4( 6) and g4(10) ) ; +g8_b( 5) <= not( g4( 5) and g4( 9) ) ; +g8_b( 4) <= not( g4( 4) and g4( 8) ) ; +g8_b( 3) <= not( g4( 3) and g4( 7) ) ; +g8_b( 2) <= not( g4( 2) and g4( 6) ) ; + +g16(19) <= not( g8_b(19) ); +g16(18) <= not( g8_b(18) ); +g16(17) <= not( g8_b(17) ); +g16(16) <= not( g8_b(16) ); +g16(15) <= not( g8_b(15) ); +g16(14) <= not( g8_b(14) ); +g16(13) <= not( g8_b(13) ); +g16(12) <= not( g8_b(12) ); +g16(11) <= not( g8_b(11) or g8_b(19) ) ; +g16(10) <= not( g8_b(10) or g8_b(18) ) ; +g16( 9) <= not( g8_b( 9) or g8_b(17) ) ; +g16( 8) <= not( g8_b( 8) or g8_b(16) ) ; +g16( 7) <= not( g8_b( 7) or g8_b(15) ) ; +g16( 6) <= not( g8_b( 6) or g8_b(14) ) ; +g16( 5) <= not( g8_b( 5) or g8_b(13) ) ; +g16( 4) <= not( g8_b( 4) or g8_b(12) ) ; +g16( 3) <= not( g8_b( 3) or g8_b(11) ) ; +g16( 2) <= not( g8_b( 2) or g8_b(10) ) ; + +a_cout_b(19) <= not( g16(19) ); +a_cout_b(18) <= not( g16(18) ); +a_cout_b(17) <= not( g16(17) ); +a_cout_b(16) <= not( g16(16) ); +a_cout_b(15) <= not( g16(15) ); +a_cout_b(14) <= not( g16(14) ); +a_cout_b(13) <= not( g16(13) ); +a_cout_b(12) <= not( g16(12) ); +a_cout_b(11) <= not( g16(11) ); +a_cout_b(10) <= not( g16(10) ); +a_cout_b( 9) <= not( g16( 9) ); +a_cout_b( 8) <= not( g16( 8) ); +a_cout_b( 7) <= not( g16( 7) ); +a_cout_b( 6) <= not( g16( 6) ); +a_cout_b( 5) <= not( g16( 5) ); +a_cout_b( 4) <= not( g16( 4) ); +a_cout_b( 3) <= not( g16( 3) and g16(19) ); +a_cout_b( 2) <= not( g16( 2) and g16(18) ); + + + +----------------------------------------------------------- +a_sum(1 to 18) <= a(1 to 18); +a_sum(19) <= not a(19); + + +o(01 to 18) <= not( a_sum(01 to 18) xor a_cout_b(02 to 19) ); --output +o(19) <= a_sum(19); --output + + +end fuq_gst_inc19; diff --git a/rel/src/vhdl/work/fuq_gst_loa.vhdl b/rel/src/vhdl/work/fuq_gst_loa.vhdl new file mode 100644 index 0000000..ff1c516 --- /dev/null +++ b/rel/src/vhdl/work/fuq_gst_loa.vhdl @@ -0,0 +1,195 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +--//############################################################################ +--//##### FUQ_GEST_loa.VHDL ######### +--//##### side pipe for graphics estimates ######### +--//##### flogefp, fexptefp ######### +--//##### ######### +--//############################################################################ + + +library ieee; + use ieee.std_logic_1164.all ; +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; +library support; +use support.power_logic_pkg.all; + +library tri; use tri.tri_latches_pkg.all; + + +entity fuq_gst_loa is + port( + a :in std_ulogic_vector(1 to 19); + + shamt :out std_ulogic_vector(0 to 4) + + ); + + + +end fuq_gst_loa; + +architecture fuq_gst_loa of fuq_gst_loa is + + signal unused :std_ulogic; + +begin + + unused <= a(19) ; + +--@@ ESPRESSO TABLE START @@ +-- ################################################################################################## + +-- ################################################################################################## +-- .i 19 +-- .o 5 +-- .ilb a(01) a(02) a(03) a(04) a(05) a(06) a(07) a(08) a(09) a(10) a(11) a(12) a(13) a(14) a(15) a(16) a(17) a(18) a(19) +-- .ob shamt(0) shamt(1) shamt(2) shamt(3) shamt(4) + +-- .type fr +--//####################### +-- +-- 0000000000000000001 10011 +-- 000000000000000001- 10010 +-- 00000000000000001-- 10001 +-- 0000000000000001--- 10000 +-- 000000000000001---- 01111 +-- 00000000000001----- 01110 +-- 0000000000001------ 01101 +-- 000000000001------- 01100 +-- 00000000001-------- 01011 +-- 0000000001--------- 01010 +-- 000000001---------- 01001 +-- 00000001----------- 01000 +-- 0000001------------ 00111 +-- 000001------------- 00110 +-- 00001-------------- 00101 +-- 0001--------------- 00100 +-- 001---------------- 00011 +-- 01----------------- 00010 +-- 1------------------ 00001 +-- 0000000000000000000 00000 + + +-- ############################################################################### +-- .e +--@@ ESPRESSO TABLE END @@ + +--@@ ESPRESSO LOGIC START @@ +-- logic generated on: Tue Dec 4 13:14:17 2007 +shamt(0) <= (not a(01) and not a(02) and not a(03) and not a(04) and not a(05) and not a(06) and not a(07) + and not a(08) and not a(09) and not a(10) and not a(11) and not a(12) and not a(13) + and not a(14) and not a(15) and a(19)) or + (not a(01) and not a(02) and not a(03) and not a(04) and not a(05) and not a(06) and not a(07) + and not a(08) and not a(09) and not a(10) and not a(11) and not a(12) and not a(13) and not a(14) + and not a(15) and a(18)) or + (not a(01) and not a(02) and not a(03) and not a(04) and not a(05) and not a(06) and not a(07) + and not a(08) and not a(09) and not a(10) and not a(11) and not a(12) and not a(13) and not a(14) + and not a(15) and a(17)) or + (not a(01) and not a(02) and not a(03) and not a(04) and not a(05) and not a(06) and not a(07) + and not a(08) and not a(09) and not a(10) and not a(11) and not a(12) and not a(13) and not a(14) + and not a(15) and a(16)); + +shamt(1) <= (not a(01) and not a(02) and not a(03) and not a(04) and not a(05) and not a(06) and not a(07) + and a(15)) or + (not a(01) and not a(02) and not a(03) and not a(04) and not a(05) and not a(06) and not a(07) + and a(14)) or + (not a(01) and not a(02) and not a(03) and not a(04) and not a(05) and not a(06) and not a(07) + and a(13)) or + (not a(01) and not a(02) and not a(03) and not a(04) and not a(05) and not a(06) and not a(07) + and a(12)) or + (not a(01) and not a(02) and not a(03) and not a(04) and not a(05) and not a(06) and not a(07) + and a(11)) or + (not a(01) and not a(02) and not a(03) and not a(04) and not a(05) and not a(06) and not a(07) + and a(10)) or + (not a(01) and not a(02) and not a(03) and not a(04) and not a(05) and not a(06) and not a(07) + and a(09)) or + (not a(01) and not a(02) and not a(03) and not a(04) and not a(05) and not a(06) and not a(07) + and a(08)); + +shamt(2) <= (not a(01) and not a(02) and not a(03) and not a(08) and not a(09) and not a(10) and not a(11) + and a(15)) or + (not a(01) and not a(02) and not a(03) and not a(08) and not a(09) and not a(10) and not a(11) + and a(14)) or + (not a(01) and not a(02) and not a(03) and not a(08) and not a(09) and not a(10) and not a(11) + and a(13)) or + (not a(01) and not a(02) and not a(03) and not a(08) and not a(09) and not a(10) and not a(11) + and a(12)) or + (not a(01) and not a(02) and not a(03) and a(07)) or + (not a(01) and not a(02) and not a(03) and a(06)) or + (not a(01) and not a(02) and not a(03) and a(05)) or + (not a(01) and not a(02) and not a(03) and a(04)); + +shamt(3) <= (not a(01) and not a(04) and not a(05) and not a(08) and not a(09) and not a(12) and not a(13) + and not a(16) and not a(17) and a(19)) or + (not a(01) and not a(04) and not a(05) and not a(08) and not a(09) and not a(12) and not a(13) + and not a(16) and not a(17) and a(18)) or + (not a(01) and not a(04) and not a(05) and not a(08) and not a(09) and not a(12) and not a(13) + and a(15)) or + (not a(01) and not a(04) and not a(05) and not a(08) and not a(09) and not a(12) and not a(13) + and a(14)) or + (not a(01) and not a(04) and not a(05) and not a(08) and not a(09) and a(11)) or + (not a(01) and not a(04) and not a(05) and not a(08) and not a(09) and a(10)) or + (not a(01) and not a(04) and not a(05) and a(07)) or + (not a(01) and not a(04) and not a(05) and a(06)) or + (not a(01) and a(03)) or + (not a(01) and a(02)); + +shamt(4) <= (not a(02) and not a(04) and not a(06) and not a(08) and not a(10) and not a(12) and not a(14) + and not a(16) and not a(18) and a(19)) or + (not a(02) and not a(04) and not a(06) and not a(08) and not a(10) and not a(12) and not a(14) + and not a(16) and a(17)) or + (not a(02) and not a(04) and not a(06) and not a(08) and not a(10) and not a(12) and not a(14) + and a(15)) or + (not a(02) and not a(04) and not a(06) and not a(08) and not a(10) and not a(12) and a(13)) or + (not a(02) and not a(04) and not a(06) and not a(08) and not a(10) and a(11)) or + (not a(02) and not a(04) and not a(06) and not a(08) and a(09)) or + (not a(02) and not a(04) and not a(06) and a(07)) or + (not a(02) and not a(04) and a(05)) or + (not a(02) and a(03)) or + ( a(01)); + +--@@ ESPRESSO LOGIC END @@ + + + + + + + + + + +end fuq_gst_loa; diff --git a/rel/src/vhdl/work/fuq_hc16pp.vhdl b/rel/src/vhdl/work/fuq_hc16pp.vhdl new file mode 100644 index 0000000..ad8faf3 --- /dev/null +++ b/rel/src/vhdl/work/fuq_hc16pp.vhdl @@ -0,0 +1,504 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; use ieee.std_logic_1164.all ; + +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + +ENTITY fuq_hc16pp IS PORT( + x : IN std_ulogic_vector(0 to 15); + y : IN std_ulogic_vector(0 to 15); + ci0 : IN std_ulogic; + ci0_b : IN std_ulogic; + ci1 : IN std_ulogic; + ci1_b : IN std_ulogic; + s0 : OUT std_ulogic_vector(0 to 15); + s1 : OUT std_ulogic_vector(0 to 15); + g16 : out std_ulogic; + t16 : out std_ulogic +); + + + +END fuq_hc16pp; + +ARCHITECTURE fuq_hc16pp OF fuq_hc16pp IS + + signal g01_b, t01_b, p01_b, p01 :std_ulogic_vector(0 to 15); + signal g01od, t01od :std_ulogic_vector(0 to 7); + signal g02ev , t02ev :std_ulogic_vector(0 to 7); + signal g02ev_b , t02ev_b :std_ulogic_vector(1 to 7); + signal g04ev, t04ev :std_ulogic_vector(1 to 7); + signal g08ev_b, t08ev_b :std_ulogic_vector(1 to 7); + signal g16ev, t16ev :std_ulogic_vector(1 to 7); + signal c0_b , c1_b :std_ulogic_vector(1 to 15); + signal s0_raw, s1_raw :std_ulogic_vector(0 to 15); + signal s0_x_b, s0_y_b :std_ulogic_vector(0 to 15); + signal s1_x_b, s1_y_b :std_ulogic_vector(0 to 15); + + signal glb_g04_e01_b, glb_g04_e23_b, glb_g04_e45_b, glb_g04_e67_b :std_ulogic; + signal glb_t04_e01_b, glb_t04_e23_b, glb_t04_e45_b, glb_t04_e67_b :std_ulogic; + signal glb_g08_e03 , glb_g08_e47 , glb_t08_e03 , glb_t08_e47 :std_ulogic; + signal glb_g16_e07_b, glb_t16_e07_b :std_ulogic; + + + + + + + + + + + +BEGIN + +--//##################################### +--//## group 1 +--//##################################### + + hc00_g01: g01_b( 0) <= not( x( 0) and y( 0) ); --critical + hc01_g01: g01_b( 1) <= not( x( 1) and y( 1) ); --critical + hc02_g01: g01_b( 2) <= not( x( 2) and y( 2) ); --critical + hc03_g01: g01_b( 3) <= not( x( 3) and y( 3) ); --critical + hc04_g01: g01_b( 4) <= not( x( 4) and y( 4) ); --critical + hc05_g01: g01_b( 5) <= not( x( 5) and y( 5) ); --critical + hc06_g01: g01_b( 6) <= not( x( 6) and y( 6) ); --critical + hc07_g01: g01_b( 7) <= not( x( 7) and y( 7) ); --critical + hc08_g01: g01_b( 8) <= not( x( 8) and y( 8) ); --critical + hc09_g01: g01_b( 9) <= not( x( 9) and y( 9) ); --critical + hc10_g01: g01_b(10) <= not( x(10) and y(10) ); --critical + hc11_g01: g01_b(11) <= not( x(11) and y(11) ); --critical + hc12_g01: g01_b(12) <= not( x(12) and y(12) ); --critical + hc13_g01: g01_b(13) <= not( x(13) and y(13) ); --critical + hc14_g01: g01_b(14) <= not( x(14) and y(14) ); --critical + hc15_g01: g01_b(15) <= not( x(15) and y(15) ); --critical + + hc00_t01: t01_b( 0) <= not( x( 0) or y( 0) ); --critical + hc01_t01: t01_b( 1) <= not( x( 1) or y( 1) ); --critical + hc02_t01: t01_b( 2) <= not( x( 2) or y( 2) ); --critical + hc03_t01: t01_b( 3) <= not( x( 3) or y( 3) ); --critical + hc04_t01: t01_b( 4) <= not( x( 4) or y( 4) ); --critical + hc05_t01: t01_b( 5) <= not( x( 5) or y( 5) ); --critical + hc06_t01: t01_b( 6) <= not( x( 6) or y( 6) ); --critical + hc07_t01: t01_b( 7) <= not( x( 7) or y( 7) ); --critical + hc08_t01: t01_b( 8) <= not( x( 8) or y( 8) ); --critical + hc09_t01: t01_b( 9) <= not( x( 9) or y( 9) ); --critical + hc10_t01: t01_b(10) <= not( x(10) or y(10) ); --critical + hc11_t01: t01_b(11) <= not( x(11) or y(11) ); --critical + hc12_t01: t01_b(12) <= not( x(12) or y(12) ); --critical + hc13_t01: t01_b(13) <= not( x(13) or y(13) ); --critical + hc14_t01: t01_b(14) <= not( x(14) or y(14) ); --critical + hc15_t01: t01_b(15) <= not( x(15) or y(15) ); --critical + + hc00_p01: p01( 0) <= ( x( 0) xor y( 0) ); --not critical + hc01_p01: p01( 1) <= ( x( 1) xor y( 1) ); --not critical + hc02_p01: p01( 2) <= ( x( 2) xor y( 2) ); --not critical + hc03_p01: p01( 3) <= ( x( 3) xor y( 3) ); --not critical + hc04_p01: p01( 4) <= ( x( 4) xor y( 4) ); --not critical + hc05_p01: p01( 5) <= ( x( 5) xor y( 5) ); --not critical + hc06_p01: p01( 6) <= ( x( 6) xor y( 6) ); --not critical + hc07_p01: p01( 7) <= ( x( 7) xor y( 7) ); --not critical + hc08_p01: p01( 8) <= ( x( 8) xor y( 8) ); --not critical + hc09_p01: p01( 9) <= ( x( 9) xor y( 9) ); --not critical + hc10_p01: p01(10) <= ( x(10) xor y(10) ); --not critical + hc11_p01: p01(11) <= ( x(11) xor y(11) ); --not critical + hc12_p01: p01(12) <= ( x(12) xor y(12) ); --not critical + hc13_p01: p01(13) <= ( x(13) xor y(13) ); --not critical + hc14_p01: p01(14) <= ( x(14) xor y(14) ); --not critical + hc15_p01: p01(15) <= ( x(15) xor y(15) ); --not critical + + hc00_p01b: p01_b( 0) <= not( p01( 0) ); --not critical + hc01_p01b: p01_b( 1) <= not( p01( 1) ); --not critical + hc02_p01b: p01_b( 2) <= not( p01( 2) ); --not critical + hc03_p01b: p01_b( 3) <= not( p01( 3) ); --not critical + hc04_p01b: p01_b( 4) <= not( p01( 4) ); --not critical + hc05_p01b: p01_b( 5) <= not( p01( 5) ); --not critical + hc06_p01b: p01_b( 6) <= not( p01( 6) ); --not critical + hc07_p01b: p01_b( 7) <= not( p01( 7) ); --not critical + hc08_p01b: p01_b( 8) <= not( p01( 8) ); --not critical + hc09_p01b: p01_b( 9) <= not( p01( 9) ); --not critical + hc10_p01b: p01_b(10) <= not( p01(10) ); --not critical + hc11_p01b: p01_b(11) <= not( p01(11) ); --not critical + hc12_p01b: p01_b(12) <= not( p01(12) ); --not critical + hc13_p01b: p01_b(13) <= not( p01(13) ); --not critical + hc14_p01b: p01_b(14) <= not( p01(14) ); --not critical + hc15_p01b: p01_b(15) <= not( p01(15) ); --not critical + + + hc01_g01o: g01od(0) <= not g01_b( 1); + hc03_g01o: g01od(1) <= not g01_b( 3); + hc05_g01o: g01od(2) <= not g01_b( 5); + hc07_g01o: g01od(3) <= not g01_b( 7); + hc09_g01o: g01od(4) <= not g01_b( 9); + hc11_g01o: g01od(5) <= not g01_b(11); + hc13_g01o: g01od(6) <= not g01_b(13); + hc15_g01o: g01od(7) <= not g01_b(15); + + hc01_t01o: t01od(0) <= not t01_b( 1); + hc03_t01o: t01od(1) <= not t01_b( 3); + hc05_t01o: t01od(2) <= not t01_b( 5); + hc07_t01o: t01od(3) <= not t01_b( 7); + hc09_t01o: t01od(4) <= not t01_b( 9); + hc11_t01o: t01od(5) <= not t01_b(11); + hc13_t01o: t01od(6) <= not t01_b(13); + hc15_t01o: t01od(7) <= not t01_b(15); + + + + +--//##################################### +--//## group 2 // local and global (shared) +--//##################################### + + hc14_g02: g02ev(7) <= not( ( t01_b(14) or g01_b(15) ) and g01_b(14) );--final + hc12_g02: g02ev(6) <= not( ( t01_b(12) or g01_b(13) ) and g01_b(12) ); + hc10_g02: g02ev(5) <= not( ( t01_b(10) or g01_b(11) ) and g01_b(10) ); + hc08_g02: g02ev(4) <= not( ( t01_b( 8) or g01_b( 9) ) and g01_b( 8) ); + hc06_g02: g02ev(3) <= not( ( t01_b( 6) or g01_b( 7) ) and g01_b( 6) ); + hc04_g02: g02ev(2) <= not( ( t01_b( 4) or g01_b( 5) ) and g01_b( 4) ); + hc02_g02: g02ev(1) <= not( ( t01_b( 2) or g01_b( 3) ) and g01_b( 2) ); + hc00_g02: g02ev(0) <= not( ( t01_b( 0) or g01_b( 1) ) and g01_b( 0) ); + + hc14_t02: t02ev(7) <= not( ( t01_b(14) or t01_b(15) ) and g01_b(14) );--final + hc12_t02: t02ev(6) <= not( t01_b(12) or t01_b(13) ); + hc10_t02: t02ev(5) <= not( t01_b(10) or t01_b(11) ); + hc08_t02: t02ev(4) <= not( t01_b( 8) or t01_b( 9) ); + hc06_t02: t02ev(3) <= not( t01_b( 6) or t01_b( 7) ); + hc04_t02: t02ev(2) <= not( t01_b( 4) or t01_b( 5) ); + hc02_t02: t02ev(1) <= not( t01_b( 2) or t01_b( 3) ); + hc00_t02: t02ev(0) <= not( t01_b( 0) or t01_b( 1) ); + + hc14_g02b: g02ev_b(7) <= not( g02ev(7) ); + hc12_g02b: g02ev_b(6) <= not( g02ev(6) ); + hc10_g02b: g02ev_b(5) <= not( g02ev(5) ); + hc08_g02b: g02ev_b(4) <= not( g02ev(4) ); + hc06_g02b: g02ev_b(3) <= not( g02ev(3) ); + hc04_g02b: g02ev_b(2) <= not( g02ev(2) ); + hc02_g02b: g02ev_b(1) <= not( g02ev(1) ); + + hc14_t02b: t02ev_b(7) <= not( t02ev(7) ); + hc12_t02b: t02ev_b(6) <= not( t02ev(6) ); + hc10_t02b: t02ev_b(5) <= not( t02ev(5) ); + hc08_t02b: t02ev_b(4) <= not( t02ev(4) ); + hc06_t02b: t02ev_b(3) <= not( t02ev(3) ); + hc04_t02b: t02ev_b(2) <= not( t02ev(2) ); + hc02_t02b: t02ev_b(1) <= not( t02ev(1) ); + +--//##################################### +--//## replicating for global chain +--//##################################### + + u_glb_g04_e01: glb_g04_e01_b <= not( g02ev(0) or ( t02ev(0) and g02ev(1) ) ); + u_glb_g04_e23: glb_g04_e23_b <= not( g02ev(2) or ( t02ev(2) and g02ev(3) ) ); + u_glb_g04_e45: glb_g04_e45_b <= not( g02ev(4) or ( t02ev(4) and g02ev(5) ) ); + u_glb_g04_e67: glb_g04_e67_b <= not( g02ev(6) or ( t02ev(6) and g02ev(7) ) ); + u_glb_t04_e01: glb_t04_e01_b <= not( t02ev(0) and t02ev(1) ); + u_glb_t04_e23: glb_t04_e23_b <= not( t02ev(2) and t02ev(3) ); + u_glb_t04_e45: glb_t04_e45_b <= not( t02ev(4) and t02ev(5) ); + u_glb_t04_e67: glb_t04_e67_b <= not( g02ev(6) or ( t02ev(6) and t02ev(7) ) ); + + u_glb_g08_e03: glb_g08_e03 <= not( glb_g04_e01_b and ( glb_t04_e01_b or glb_g04_e23_b ) ); + u_glb_g08_e47: glb_g08_e47 <= not( glb_g04_e45_b and ( glb_t04_e45_b or glb_g04_e67_b ) ); + u_glb_t08_e03: glb_t08_e03 <= not( glb_t04_e01_b or glb_t04_e23_b ); + u_glb_t08_e47: glb_t08_e47 <= not( glb_g04_e45_b and ( glb_t04_e45_b or glb_t04_e67_b ) ); + + u_glb_g16_e07: glb_g16_e07_b <= not( glb_g08_e03 or ( glb_t08_e03 and glb_g08_e47 ) ); + u_glb_t16_e07: glb_t16_e07_b <= not( glb_g08_e03 or ( glb_t08_e03 and glb_t08_e47 ) ); + + u_g16o: g16 <= not( glb_g16_e07_b );--output + u_t16o: t16 <= not( glb_t16_e07_b );--output + + +--//##################################### +--//## group 4 // delayed for local chain ... reverse phase +--//##################################### + + hc14_g04: g04ev(7) <= not( g02ev_b(7) ); + hc12_g04: g04ev(6) <= not( g02ev_b(6) and (t02ev_b(6) or g02ev_b(7)) );--final + hc10_g04: g04ev(5) <= not( g02ev_b(5) and (t02ev_b(5) or g02ev_b(6)) ); + hc08_g04: g04ev(4) <= not( g02ev_b(4) and (t02ev_b(4) or g02ev_b(5)) ); + hc06_g04: g04ev(3) <= not( g02ev_b(3) and (t02ev_b(3) or g02ev_b(4)) ); + hc04_g04: g04ev(2) <= not( g02ev_b(2) and (t02ev_b(2) or g02ev_b(3)) ); + hc02_g04: g04ev(1) <= not( g02ev_b(1) and (t02ev_b(1) or g02ev_b(2)) ); + + + hc14_t04: t04ev(7) <= not( t02ev_b(7) ); + hc12_t04: t04ev(6) <= not( g02ev_b(6) and (t02ev_b(6) or t02ev_b(7)) );--final + hc10_t04: t04ev(5) <= not( t02ev_b(5) or t02ev_b(6) ); + hc08_t04: t04ev(4) <= not( t02ev_b(4) or t02ev_b(5) ); + hc06_t04: t04ev(3) <= not( t02ev_b(3) or t02ev_b(4) ); + hc04_t04: t04ev(2) <= not( t02ev_b(2) or t02ev_b(3) ); + hc02_t04: t04ev(1) <= not( t02ev_b(1) or t02ev_b(2) ); + + +--//##################################### +--//## group 8 +--//##################################### + + hc14_g08: g08ev_b(7) <= not( g04ev(7) ); + hc12_g08: g08ev_b(6) <= not( g04ev(6) ); + hc10_g08: g08ev_b(5) <= not( g04ev(5) or (t04ev(5) and g04ev(7)) );--final + hc08_g08: g08ev_b(4) <= not( g04ev(4) or (t04ev(4) and g04ev(6)) );--final + hc06_g08: g08ev_b(3) <= not( g04ev(3) or (t04ev(3) and g04ev(5)) ); + hc04_g08: g08ev_b(2) <= not( g04ev(2) or (t04ev(2) and g04ev(4)) ); + hc02_g08: g08ev_b(1) <= not( g04ev(1) or (t04ev(1) and g04ev(3)) ); + + + hc14_t08: t08ev_b(7) <= not( t04ev(7) ); + hc12_t08: t08ev_b(6) <= not( t04ev(6) ); + hc10_t08: t08ev_b(5) <= not( g04ev(5) or (t04ev(5) and t04ev(7)) );--final + hc08_t08: t08ev_b(4) <= not( g04ev(4) or (t04ev(4) and t04ev(6)) );--final + hc06_t08: t08ev_b(3) <= not( t04ev(3) and t04ev(5) ); + hc04_t08: t08ev_b(2) <= not( t04ev(2) and t04ev(4) ); + hc02_t08: t08ev_b(1) <= not( t04ev(1) and t04ev(3) ); + + +--//##################################### +--//## group 16 +--//##################################### + + hc14_g16: g16ev(7) <= not( g08ev_b(7) ); + hc12_g16: g16ev(6) <= not( g08ev_b(6) ); + hc10_g16: g16ev(5) <= not( g08ev_b(5) ); + hc08_g16: g16ev(4) <= not( g08ev_b(4) ); + hc06_g16: g16ev(3) <= not( g08ev_b(3) and (t08ev_b(3) or g08ev_b(7)) ); --final + hc04_g16: g16ev(2) <= not( g08ev_b(2) and (t08ev_b(2) or g08ev_b(6)) ); --final + hc02_g16: g16ev(1) <= not( g08ev_b(1) and (t08ev_b(1) or g08ev_b(5)) ); --final + + hc14_t16: t16ev(7) <= not( t08ev_b(7) ); + hc12_t16: t16ev(6) <= not( t08ev_b(6) ); + hc10_t16: t16ev(5) <= not( t08ev_b(5) ); + hc08_t16: t16ev(4) <= not( t08ev_b(4) ); + hc06_t16: t16ev(3) <= not( g08ev_b(3) and (t08ev_b(3) or t08ev_b(7)) ); --final + hc04_t16: t16ev(2) <= not( g08ev_b(2) and (t08ev_b(2) or t08ev_b(6)) ); --final + hc02_t16: t16ev(1) <= not( g08ev_b(1) and (t08ev_b(1) or t08ev_b(5)) ); --final + + +--//##################################### +--//## group 16 delayed +--//##################################### + + hc14_c0: c0_b(14) <= not( g16ev(7) ); + hc12_c0: c0_b(12) <= not( g16ev(6) ); + hc10_c0: c0_b(10) <= not( g16ev(5) ); + hc08_c0: c0_b( 8) <= not( g16ev(4) ); + hc06_c0: c0_b( 6) <= not( g16ev(3) ); + hc04_c0: c0_b( 4) <= not( g16ev(2) ); + hc02_c0: c0_b( 2) <= not( g16ev(1) ); + + hc14_c1: c1_b(14) <= not( t16ev(7) ); + hc12_c1: c1_b(12) <= not( t16ev(6) ); + hc10_c1: c1_b(10) <= not( t16ev(5) ); + hc08_c1: c1_b( 8) <= not( t16ev(4) ); + hc06_c1: c1_b( 6) <= not( t16ev(3) ); + hc04_c1: c1_b( 4) <= not( t16ev(2) ); + hc02_c1: c1_b( 2) <= not( t16ev(1) ); + + hc15_c0: c0_b(15) <= not( g01od(7)); + hc13_c0: c0_b(13) <= not( (t01od(6) and g16ev(7)) or g01od(6)); + hc11_c0: c0_b(11) <= not( (t01od(5) and g16ev(6)) or g01od(5)); + hc09_c0: c0_b( 9) <= not( (t01od(4) and g16ev(5)) or g01od(4)); + hc07_c0: c0_b( 7) <= not( (t01od(3) and g16ev(4)) or g01od(3)); + hc05_c0: c0_b( 5) <= not( (t01od(2) and g16ev(3)) or g01od(2)); + hc03_c0: c0_b( 3) <= not( (t01od(1) and g16ev(2)) or g01od(1)); + hc01_c0: c0_b( 1) <= not( (t01od(0) and g16ev(1)) or g01od(0)); + + hc15_c1: c1_b(15) <= not( t01od(7) ); + hc13_c1: c1_b(13) <= not( (t01od(6) and t16ev(7)) or g01od(6) ); + hc11_c1: c1_b(11) <= not( (t01od(5) and t16ev(6)) or g01od(5) ); + hc09_c1: c1_b( 9) <= not( (t01od(4) and t16ev(5)) or g01od(4) ); + hc07_c1: c1_b( 7) <= not( (t01od(3) and t16ev(4)) or g01od(3) ); + hc05_c1: c1_b( 5) <= not( (t01od(2) and t16ev(3)) or g01od(2) ); + hc03_c1: c1_b( 3) <= not( (t01od(1) and t16ev(2)) or g01od(1) ); + hc01_c1: c1_b( 1) <= not( (t01od(0) and t16ev(1)) or g01od(0) ); + +--//##################################### +--//## sum before select +--//##################################### + + hc00_s0r: s0_raw( 0) <= ( p01_b( 0) xor c0_b( 1) ); + hc01_s0r: s0_raw( 1) <= ( p01_b( 1) xor c0_b( 2) ); + hc02_s0r: s0_raw( 2) <= ( p01_b( 2) xor c0_b( 3) ); + hc03_s0r: s0_raw( 3) <= ( p01_b( 3) xor c0_b( 4) ); + hc04_s0r: s0_raw( 4) <= ( p01_b( 4) xor c0_b( 5) ); + hc05_s0r: s0_raw( 5) <= ( p01_b( 5) xor c0_b( 6) ); + hc06_s0r: s0_raw( 6) <= ( p01_b( 6) xor c0_b( 7) ); + hc07_s0r: s0_raw( 7) <= ( p01_b( 7) xor c0_b( 8) ); + hc08_s0r: s0_raw( 8) <= ( p01_b( 8) xor c0_b( 9) ); + hc09_s0r: s0_raw( 9) <= ( p01_b( 9) xor c0_b(10) ); + hc10_s0r: s0_raw(10) <= ( p01_b(10) xor c0_b(11) ); + hc11_s0r: s0_raw(11) <= ( p01_b(11) xor c0_b(12) ); + hc12_s0r: s0_raw(12) <= ( p01_b(12) xor c0_b(13) ); + hc13_s0r: s0_raw(13) <= ( p01_b(13) xor c0_b(14) ); + hc14_s0r: s0_raw(14) <= ( p01_b(14) xor c0_b(15) ); + hc15_s0r: s0_raw(15) <= not p01_b(15); + + hc00_s1r: s1_raw( 0) <= ( p01_b( 0) xor c1_b( 1) ); + hc01_s1r: s1_raw( 1) <= ( p01_b( 1) xor c1_b( 2) ); + hc02_s1r: s1_raw( 2) <= ( p01_b( 2) xor c1_b( 3) ); + hc03_s1r: s1_raw( 3) <= ( p01_b( 3) xor c1_b( 4) ); + hc04_s1r: s1_raw( 4) <= ( p01_b( 4) xor c1_b( 5) ); + hc05_s1r: s1_raw( 5) <= ( p01_b( 5) xor c1_b( 6) ); + hc06_s1r: s1_raw( 6) <= ( p01_b( 6) xor c1_b( 7) ); + hc07_s1r: s1_raw( 7) <= ( p01_b( 7) xor c1_b( 8) ); + hc08_s1r: s1_raw( 8) <= ( p01_b( 8) xor c1_b( 9) ); + hc09_s1r: s1_raw( 9) <= ( p01_b( 9) xor c1_b(10) ); + hc10_s1r: s1_raw(10) <= ( p01_b(10) xor c1_b(11) ); + hc11_s1r: s1_raw(11) <= ( p01_b(11) xor c1_b(12) ); + hc12_s1r: s1_raw(12) <= ( p01_b(12) xor c1_b(13) ); + hc13_s1r: s1_raw(13) <= ( p01_b(13) xor c1_b(14) ); + hc14_s1r: s1_raw(14) <= ( p01_b(14) xor c1_b(15) ); + hc15_s1r: s1_raw(15) <= not s0_raw(15); + + +--//##################################### +--//## sum after select +--//##################################### + + + hc00_s0x: s0_x_b( 0) <= not( s0_raw( 0) and ci0_b ); + hc00_s0y: s0_y_b( 0) <= not( s1_raw( 0) and ci0 ); + hc00_s1x: s1_x_b( 0) <= not( s0_raw( 0) and ci1_b ); + hc00_s1y: s1_y_b( 0) <= not( s1_raw( 0) and ci1 ); + hc00_s0: s0 ( 0) <= not( s0_x_b( 0) and s0_y_b( 0) ); + hc00_s1: s1 ( 0) <= not( s1_x_b( 0) and s1_y_b( 0) ); + + hc01_s0x: s0_x_b( 1) <= not( s0_raw( 1) and ci0_b ); + hc01_s0y: s0_y_b( 1) <= not( s1_raw( 1) and ci0 ); + hc01_s1x: s1_x_b( 1) <= not( s0_raw( 1) and ci1_b ); + hc01_s1y: s1_y_b( 1) <= not( s1_raw( 1) and ci1 ); + hc01_s0: s0 ( 1) <= not( s0_x_b( 1) and s0_y_b( 1) ); + hc01_s1: s1 ( 1) <= not( s1_x_b( 1) and s1_y_b( 1) ); + + hc02_s0x: s0_x_b( 2) <= not( s0_raw( 2) and ci0_b ); + hc02_s0y: s0_y_b( 2) <= not( s1_raw( 2) and ci0 ); + hc02_s1x: s1_x_b( 2) <= not( s0_raw( 2) and ci1_b ); + hc02_s1y: s1_y_b( 2) <= not( s1_raw( 2) and ci1 ); + hc02_s0: s0 ( 2) <= not( s0_x_b( 2) and s0_y_b( 2) ); + hc02_s1: s1 ( 2) <= not( s1_x_b( 2) and s1_y_b( 2) ); + + hc03_s0x: s0_x_b( 3) <= not( s0_raw( 3) and ci0_b ); + hc03_s0y: s0_y_b( 3) <= not( s1_raw( 3) and ci0 ); + hc03_s1x: s1_x_b( 3) <= not( s0_raw( 3) and ci1_b ); + hc03_s1y: s1_y_b( 3) <= not( s1_raw( 3) and ci1 ); + hc03_s0: s0 ( 3) <= not( s0_x_b( 3) and s0_y_b( 3) ); + hc03_s1: s1 ( 3) <= not( s1_x_b( 3) and s1_y_b( 3) ); + + hc04_s0x: s0_x_b( 4) <= not( s0_raw( 4) and ci0_b ); + hc04_s0y: s0_y_b( 4) <= not( s1_raw( 4) and ci0 ); + hc04_s1x: s1_x_b( 4) <= not( s0_raw( 4) and ci1_b ); + hc04_s1y: s1_y_b( 4) <= not( s1_raw( 4) and ci1 ); + hc04_s0: s0 ( 4) <= not( s0_x_b( 4) and s0_y_b( 4) ); + hc04_s1: s1 ( 4) <= not( s1_x_b( 4) and s1_y_b( 4) ); + + hc05_s0x: s0_x_b( 5) <= not( s0_raw( 5) and ci0_b ); + hc05_s0y: s0_y_b( 5) <= not( s1_raw( 5) and ci0 ); + hc05_s1x: s1_x_b( 5) <= not( s0_raw( 5) and ci1_b ); + hc05_s1y: s1_y_b( 5) <= not( s1_raw( 5) and ci1 ); + hc05_s0: s0 ( 5) <= not( s0_x_b( 5) and s0_y_b( 5) ); + hc05_s1: s1 ( 5) <= not( s1_x_b( 5) and s1_y_b( 5) ); + + hc06_s0x: s0_x_b( 6) <= not( s0_raw( 6) and ci0_b ); + hc06_s0y: s0_y_b( 6) <= not( s1_raw( 6) and ci0 ); + hc06_s1x: s1_x_b( 6) <= not( s0_raw( 6) and ci1_b ); + hc06_s1y: s1_y_b( 6) <= not( s1_raw( 6) and ci1 ); + hc06_s0: s0 ( 6) <= not( s0_x_b( 6) and s0_y_b( 6) ); + hc06_s1: s1 ( 6) <= not( s1_x_b( 6) and s1_y_b( 6) ); + + hc07_s0x: s0_x_b( 7) <= not( s0_raw( 7) and ci0_b ); + hc07_s0y: s0_y_b( 7) <= not( s1_raw( 7) and ci0 ); + hc07_s1x: s1_x_b( 7) <= not( s0_raw( 7) and ci1_b ); + hc07_s1y: s1_y_b( 7) <= not( s1_raw( 7) and ci1 ); + hc07_s0: s0 ( 7) <= not( s0_x_b( 7) and s0_y_b( 7) ); + hc07_s1: s1 ( 7) <= not( s1_x_b( 7) and s1_y_b( 7) ); + + hc08_s0x: s0_x_b( 8) <= not( s0_raw( 8) and ci0_b ); + hc08_s0y: s0_y_b( 8) <= not( s1_raw( 8) and ci0 ); + hc08_s1x: s1_x_b( 8) <= not( s0_raw( 8) and ci1_b ); + hc08_s1y: s1_y_b( 8) <= not( s1_raw( 8) and ci1 ); + hc08_s0: s0 ( 8) <= not( s0_x_b( 8) and s0_y_b( 8) ); + hc08_s1: s1 ( 8) <= not( s1_x_b( 8) and s1_y_b( 8) ); + + hc09_s0x: s0_x_b( 9) <= not( s0_raw( 9) and ci0_b ); + hc09_s0y: s0_y_b( 9) <= not( s1_raw( 9) and ci0 ); + hc09_s1x: s1_x_b( 9) <= not( s0_raw( 9) and ci1_b ); + hc09_s1y: s1_y_b( 9) <= not( s1_raw( 9) and ci1 ); + hc09_s0: s0 ( 9) <= not( s0_x_b( 9) and s0_y_b( 9) ); + hc09_s1: s1 ( 9) <= not( s1_x_b( 9) and s1_y_b( 9) ); + + hc10_s0x: s0_x_b(10) <= not( s0_raw(10) and ci0_b ); + hc10_s0y: s0_y_b(10) <= not( s1_raw(10) and ci0 ); + hc10_s1x: s1_x_b(10) <= not( s0_raw(10) and ci1_b ); + hc10_s1y: s1_y_b(10) <= not( s1_raw(10) and ci1 ); + hc10_s0: s0 (10) <= not( s0_x_b(10) and s0_y_b(10) ); + hc10_s1: s1 (10) <= not( s1_x_b(10) and s1_y_b(10) ); + + hc11_s0x: s0_x_b(11) <= not( s0_raw(11) and ci0_b ); + hc11_s0y: s0_y_b(11) <= not( s1_raw(11) and ci0 ); + hc11_s1x: s1_x_b(11) <= not( s0_raw(11) and ci1_b ); + hc11_s1y: s1_y_b(11) <= not( s1_raw(11) and ci1 ); + hc11_s0: s0 (11) <= not( s0_x_b(11) and s0_y_b(11) ); + hc11_s1: s1 (11) <= not( s1_x_b(11) and s1_y_b(11) ); + + hc12_s0x: s0_x_b(12) <= not( s0_raw(12) and ci0_b ); + hc12_s0y: s0_y_b(12) <= not( s1_raw(12) and ci0 ); + hc12_s1x: s1_x_b(12) <= not( s0_raw(12) and ci1_b ); + hc12_s1y: s1_y_b(12) <= not( s1_raw(12) and ci1 ); + hc12_s0: s0 (12) <= not( s0_x_b(12) and s0_y_b(12) ); + hc12_s1: s1 (12) <= not( s1_x_b(12) and s1_y_b(12) ); + + hc13_s0x: s0_x_b(13) <= not( s0_raw(13) and ci0_b ); + hc13_s0y: s0_y_b(13) <= not( s1_raw(13) and ci0 ); + hc13_s1x: s1_x_b(13) <= not( s0_raw(13) and ci1_b ); + hc13_s1y: s1_y_b(13) <= not( s1_raw(13) and ci1 ); + hc13_s0: s0 (13) <= not( s0_x_b(13) and s0_y_b(13) ); + hc13_s1: s1 (13) <= not( s1_x_b(13) and s1_y_b(13) ); + + hc14_s0x: s0_x_b(14) <= not( s0_raw(14) and ci0_b ); + hc14_s0y: s0_y_b(14) <= not( s1_raw(14) and ci0 ); + hc14_s1x: s1_x_b(14) <= not( s0_raw(14) and ci1_b ); + hc14_s1y: s1_y_b(14) <= not( s1_raw(14) and ci1 ); + hc14_s0: s0 (14) <= not( s0_x_b(14) and s0_y_b(14) ); + hc14_s1: s1 (14) <= not( s1_x_b(14) and s1_y_b(14) ); + + hc15_s0x: s0_x_b(15) <= not( s0_raw(15) and ci0_b ); + hc15_s0y: s0_y_b(15) <= not( s1_raw(15) and ci0 ); + hc15_s1x: s1_x_b(15) <= not( s0_raw(15) and ci1_b ); + hc15_s1y: s1_y_b(15) <= not( s1_raw(15) and ci1 ); + hc15_s0: s0 (15) <= not( s0_x_b(15) and s0_y_b(15) ); + hc15_s1: s1 (15) <= not( s1_x_b(15) and s1_y_b(15) ); + + +END; -- ARCH fuq_hc16pp diff --git a/rel/src/vhdl/work/fuq_hc16pp_lsb.vhdl b/rel/src/vhdl/work/fuq_hc16pp_lsb.vhdl new file mode 100644 index 0000000..debcdcf --- /dev/null +++ b/rel/src/vhdl/work/fuq_hc16pp_lsb.vhdl @@ -0,0 +1,346 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; use ieee.std_logic_1164.all ; +library ibm; +library support; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + +ENTITY fuq_hc16pp_lsb IS PORT( + x : IN std_ulogic_vector(0 to 13); + y : IN std_ulogic_vector(0 to 12); + s0 : OUT std_ulogic_vector(0 to 13); + s1 : OUT std_ulogic_vector(0 to 13); + g16 : out std_ulogic; + t16 : out std_ulogic +); + + +END fuq_hc16pp_lsb; + +ARCHITECTURE fuq_hc16pp_lsb OF fuq_hc16pp_lsb IS + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + + signal g01_b :std_ulogic_vector(0 to 12); + signal t01_b, p01_b, p01 :std_ulogic_vector(0 to 13); + + signal g01od :std_ulogic_vector(0 to 5); + signal t01od :std_ulogic_vector(0 to 6); + + + signal g02ev , t02ev :std_ulogic_vector(0 to 6); + signal g02ev_b, t02ev_b :std_ulogic_vector(1 to 6); + signal g04ev , t04ev :std_ulogic_vector(1 to 6); + signal g08ev_b, t08ev_b :std_ulogic_vector(1 to 6); + signal g16ev , t16ev :std_ulogic_vector(1 to 6); + signal c0_b :std_ulogic_vector(1 to 12); + signal c1_b :std_ulogic_vector(1 to 13); + + signal glb_g04_e01_b, glb_g04_e23_b, glb_g04_e45_b, glb_g04_e67_b :std_ulogic; + signal glb_t04_e01_b, glb_t04_e23_b, glb_t04_e45_b, glb_t04_e67_b :std_ulogic; + signal glb_g08_e03 , glb_g08_e47 , glb_t08_e03 , glb_t08_e47 :std_ulogic; + signal glb_g16_e07_b, glb_t16_e07_b :std_ulogic; + + + + +BEGIN + +--//##################################### +--//## group 1 +--//##################################### + + hc00_g01: g01_b( 0) <= not( x( 0) and y( 0) ); --critical + hc01_g01: g01_b( 1) <= not( x( 1) and y( 1) ); --critical + hc02_g01: g01_b( 2) <= not( x( 2) and y( 2) ); --critical + hc03_g01: g01_b( 3) <= not( x( 3) and y( 3) ); --critical + hc04_g01: g01_b( 4) <= not( x( 4) and y( 4) ); --critical + hc05_g01: g01_b( 5) <= not( x( 5) and y( 5) ); --critical + hc06_g01: g01_b( 6) <= not( x( 6) and y( 6) ); --critical + hc07_g01: g01_b( 7) <= not( x( 7) and y( 7) ); --critical + hc08_g01: g01_b( 8) <= not( x( 8) and y( 8) ); --critical + hc09_g01: g01_b( 9) <= not( x( 9) and y( 9) ); --critical + hc10_g01: g01_b(10) <= not( x(10) and y(10) ); --critical + hc11_g01: g01_b(11) <= not( x(11) and y(11) ); --critical + hc12_g01: g01_b(12) <= not( x(12) and y(12) ); --critical + + hc00_t01: t01_b( 0) <= not( x( 0) or y( 0) ); --critical + hc01_t01: t01_b( 1) <= not( x( 1) or y( 1) ); --critical + hc02_t01: t01_b( 2) <= not( x( 2) or y( 2) ); --critical + hc03_t01: t01_b( 3) <= not( x( 3) or y( 3) ); --critical + hc04_t01: t01_b( 4) <= not( x( 4) or y( 4) ); --critical + hc05_t01: t01_b( 5) <= not( x( 5) or y( 5) ); --critical + hc06_t01: t01_b( 6) <= not( x( 6) or y( 6) ); --critical + hc07_t01: t01_b( 7) <= not( x( 7) or y( 7) ); --critical + hc08_t01: t01_b( 8) <= not( x( 8) or y( 8) ); --critical + hc09_t01: t01_b( 9) <= not( x( 9) or y( 9) ); --critical + hc10_t01: t01_b(10) <= not( x(10) or y(10) ); --critical + hc11_t01: t01_b(11) <= not( x(11) or y(11) ); --critical + hc12_t01: t01_b(12) <= not( x(12) or y(12) ); --critical + hc13_t01: t01_b(13) <= not( x(13) ); --critical + + hc00_p01: p01( 0) <= ( x( 0) xor y( 0) ); --not critical + hc01_p01: p01( 1) <= ( x( 1) xor y( 1) ); --not critical + hc02_p01: p01( 2) <= ( x( 2) xor y( 2) ); --not critical + hc03_p01: p01( 3) <= ( x( 3) xor y( 3) ); --not critical + hc04_p01: p01( 4) <= ( x( 4) xor y( 4) ); --not critical + hc05_p01: p01( 5) <= ( x( 5) xor y( 5) ); --not critical + hc06_p01: p01( 6) <= ( x( 6) xor y( 6) ); --not critical + hc07_p01: p01( 7) <= ( x( 7) xor y( 7) ); --not critical + hc08_p01: p01( 8) <= ( x( 8) xor y( 8) ); --not critical + hc09_p01: p01( 9) <= ( x( 9) xor y( 9) ); --not critical + hc10_p01: p01(10) <= ( x(10) xor y(10) ); --not critical + hc11_p01: p01(11) <= ( x(11) xor y(11) ); --not critical + hc12_p01: p01(12) <= ( x(12) xor y(12) ); --not critical + hc13_p01: p01(13) <= not p01_b(13) ; + + hc00_p01b: p01_b( 0) <= not( p01( 0) ); --not critical + hc01_p01b: p01_b( 1) <= not( p01( 1) ); --not critical + hc02_p01b: p01_b( 2) <= not( p01( 2) ); --not critical + hc03_p01b: p01_b( 3) <= not( p01( 3) ); --not critical + hc04_p01b: p01_b( 4) <= not( p01( 4) ); --not critical + hc05_p01b: p01_b( 5) <= not( p01( 5) ); --not critical + hc06_p01b: p01_b( 6) <= not( p01( 6) ); --not critical + hc07_p01b: p01_b( 7) <= not( p01( 7) ); --not critical + hc08_p01b: p01_b( 8) <= not( p01( 8) ); --not critical + hc09_p01b: p01_b( 9) <= not( p01( 9) ); --not critical + hc10_p01b: p01_b(10) <= not( p01(10) ); --not critical + hc11_p01b: p01_b(11) <= not( p01(11) ); --not critical + hc12_p01b: p01_b(12) <= not( p01(12) ); --not critical + hc13_p01b: p01_b(13) <= not( x(13) ); --not critical + + hc01_g01o: g01od(0) <= not g01_b( 1); + hc03_g01o: g01od(1) <= not g01_b( 3); + hc05_g01o: g01od(2) <= not g01_b( 5); + hc07_g01o: g01od(3) <= not g01_b( 7); + hc09_g01o: g01od(4) <= not g01_b( 9); + hc11_g01o: g01od(5) <= not g01_b(11); + + hc01_t01o: t01od(0) <= not t01_b( 1); + hc03_t01o: t01od(1) <= not t01_b( 3); + hc05_t01o: t01od(2) <= not t01_b( 5); + hc07_t01o: t01od(3) <= not t01_b( 7); + hc09_t01o: t01od(4) <= not t01_b( 9); + hc11_t01o: t01od(5) <= not t01_b(11); + hc13_t01o: t01od(6) <= not t01_b(13); + + +--//##################################### +--//## group 2 // local and global shared +--//##################################### + + hc12_g02: g02ev(6) <= not( g01_b(12) );--final + hc10_g02: g02ev(5) <= not( ( t01_b(10) or g01_b(11) ) and g01_b(10) ); + hc08_g02: g02ev(4) <= not( ( t01_b( 8) or g01_b( 9) ) and g01_b( 8) ); + hc06_g02: g02ev(3) <= not( ( t01_b( 6) or g01_b( 7) ) and g01_b( 6) ); + hc04_g02: g02ev(2) <= not( ( t01_b( 4) or g01_b( 5) ) and g01_b( 4) ); + hc02_g02: g02ev(1) <= not( ( t01_b( 2) or g01_b( 3) ) and g01_b( 2) ); + hc00_g02: g02ev(0) <= not( ( t01_b( 0) or g01_b( 1) ) and g01_b( 0) ); + + hc12_t02: t02ev(6) <= not( ( t01_b(12) or t01_b(13) ) and g01_b(12) );--final + hc10_t02: t02ev(5) <= not( ( t01_b(10) or t01_b(11) ) ); + hc08_t02: t02ev(4) <= not( ( t01_b( 8) or t01_b( 9) ) ); + hc06_t02: t02ev(3) <= not( ( t01_b( 6) or t01_b( 7) ) ); + hc04_t02: t02ev(2) <= not( ( t01_b( 4) or t01_b( 5) ) ); + hc02_t02: t02ev(1) <= not( ( t01_b( 2) or t01_b( 3) ) ); + hc00_t02: t02ev(0) <= not( ( t01_b( 0) or t01_b( 1) ) ); + + hc12_g02b: g02ev_b(6) <= not( g02ev(6) ); + hc10_g02b: g02ev_b(5) <= not( g02ev(5) ); + hc08_g02b: g02ev_b(4) <= not( g02ev(4) ); + hc06_g02b: g02ev_b(3) <= not( g02ev(3) ); + hc04_g02b: g02ev_b(2) <= not( g02ev(2) ); + hc02_g02b: g02ev_b(1) <= not( g02ev(1) ); + + hc12_t02b: t02ev_b(6) <= not( t02ev(6) ); + hc10_t02b: t02ev_b(5) <= not( t02ev(5) ); + hc08_t02b: t02ev_b(4) <= not( t02ev(4) ); + hc06_t02b: t02ev_b(3) <= not( t02ev(3) ); + hc04_t02b: t02ev_b(2) <= not( t02ev(2) ); + hc02_t02b: t02ev_b(1) <= not( t02ev(1) ); + +--//##################################### +--//## replicating for global chain +--//##################################### + + u_glb_g04_e01: glb_g04_e01_b <= not( g02ev(0) or ( t02ev(0) and g02ev(1) ) ); + u_glb_g04_e23: glb_g04_e23_b <= not( g02ev(2) or ( t02ev(2) and g02ev(3) ) ); + u_glb_g04_e45: glb_g04_e45_b <= not( g02ev(4) or ( t02ev(4) and g02ev(5) ) ); + u_glb_g04_e67: glb_g04_e67_b <= not( g02ev(6) ); + u_glb_t04_e01: glb_t04_e01_b <= not( t02ev(0) and t02ev(1) ); + u_glb_t04_e23: glb_t04_e23_b <= not( t02ev(2) and t02ev(3) ); + u_glb_t04_e45: glb_t04_e45_b <= not( t02ev(4) and t02ev(5) ); + u_glb_t04_e67: glb_t04_e67_b <= not( t02ev(6) ); + + u_glb_g08_e03: glb_g08_e03 <= not( glb_g04_e01_b and ( glb_t04_e01_b or glb_g04_e23_b ) ); + u_glb_g08_e47: glb_g08_e47 <= not( glb_g04_e45_b and ( glb_t04_e45_b or glb_g04_e67_b ) ); + u_glb_t08_e03: glb_t08_e03 <= not( glb_t04_e01_b or glb_t04_e23_b ); + u_glb_t08_e47: glb_t08_e47 <= not( glb_g04_e45_b and ( glb_t04_e45_b or glb_t04_e67_b ) ); + + u_glb_g16_e07: glb_g16_e07_b <= not( glb_g08_e03 or ( glb_t08_e03 and glb_g08_e47 ) ); + u_glb_t16_e07: glb_t16_e07_b <= not( glb_g08_e03 or ( glb_t08_e03 and glb_t08_e47 ) ); + + u_g16o: g16 <= not( glb_g16_e07_b );--output + u_t16o: t16 <= not( glb_t16_e07_b );--output + +--//##################################### +--//## group 4 +--//##################################### + + hc12_g04: g04ev (6) <= not( g02ev_b(6) ); + hc10_g04: g04ev (5) <= not( (t02ev_b(5) or g02ev_b(6)) and g02ev_b(5) );--final + hc08_g04: g04ev (4) <= not( (t02ev_b(4) or g02ev_b(5)) and g02ev_b(4) ); + hc06_g04: g04ev (3) <= not( (t02ev_b(3) or g02ev_b(4)) and g02ev_b(3) ); + hc04_g04: g04ev (2) <= not( (t02ev_b(2) or g02ev_b(3)) and g02ev_b(2) ); + hc02_g04: g04ev (1) <= not( (t02ev_b(1) or g02ev_b(2)) and g02ev_b(1) ); + + + hc12_t04: t04ev (6) <= not( t02ev_b(6) ); + hc10_t04: t04ev (5) <= not( (t02ev_b(5) or t02ev_b(6)) and g02ev_b(5) );--final + hc08_t04: t04ev (4) <= not( t02ev_b(4) or t02ev_b(5) ); + hc06_t04: t04ev (3) <= not( t02ev_b(3) or t02ev_b(4) ); + hc04_t04: t04ev (2) <= not( t02ev_b(2) or t02ev_b(3) ); + hc02_t04: t04ev (1) <= not( t02ev_b(1) or t02ev_b(2) ); + + +--//##################################### +--//## group 8 +--//##################################### + + hc12_g08: g08ev_b(6) <= not( g04ev (6) ); + hc10_g08: g08ev_b(5) <= not( g04ev (5) ); + hc08_g08: g08ev_b(4) <= not( g04ev (4) or (t04ev (4) and g04ev (6)) );--final + hc06_g08: g08ev_b(3) <= not( g04ev (3) or (t04ev (3) and g04ev (5)) );--final + hc04_g08: g08ev_b(2) <= not( g04ev (2) or (t04ev (2) and g04ev (4)) ); + hc02_g08: g08ev_b(1) <= not( g04ev (1) or (t04ev (1) and g04ev (3)) ); + + + hc12_t08: t08ev_b(6) <= not( t04ev (6) ); + hc10_t08: t08ev_b(5) <= not( t04ev (5) ); + hc08_t08: t08ev_b(4) <= not( g04ev (4) or (t04ev (4) and t04ev (6)) );--final + hc06_t08: t08ev_b(3) <= not( g04ev (3) or (t04ev (3) and t04ev (5)) );--final + hc04_t08: t08ev_b(2) <= not( t04ev (2) and t04ev (4) ); + hc02_t08: t08ev_b(1) <= not( t04ev (1) and t04ev (3) ); + + +--//##################################### +--//## group 16 +--//##################################### + + hc12_g16: g16ev (6) <= not( g08ev_b(6) ); + hc10_g16: g16ev (5) <= not( g08ev_b(5) ); + hc08_g16: g16ev (4) <= not( g08ev_b(4) ); + hc06_g16: g16ev (3) <= not( g08ev_b(3) ); + hc04_g16: g16ev (2) <= not( (t08ev_b(2) or g08ev_b(6)) and g08ev_b(2) ); --final + hc02_g16: g16ev (1) <= not( (t08ev_b(1) or g08ev_b(5)) and g08ev_b(1) ); --final + + + hc12_t16: t16ev (6) <= not( t08ev_b(6) ); + hc10_t16: t16ev (5) <= not( t08ev_b(5) ); + hc08_t16: t16ev (4) <= not( t08ev_b(4) ); + hc06_t16: t16ev (3) <= not( t08ev_b(3) ); + hc04_t16: t16ev (2) <= not( (t08ev_b(2) or t08ev_b(6)) and g08ev_b(2) ); --final + hc02_t16: t16ev (1) <= not( (t08ev_b(1) or t08ev_b(5)) and g08ev_b(1) ); --final + + +--//##################################### +--//## group 16 delayed +--//##################################### + + hc12_c0: c0_b(12) <= not( g16ev (6) ); + hc10_c0: c0_b(10) <= not( g16ev (5) ); + hc08_c0: c0_b( 8) <= not( g16ev (4) ); + hc06_c0: c0_b( 6) <= not( g16ev (3) ); + hc04_c0: c0_b( 4) <= not( g16ev (2) ); + hc02_c0: c0_b( 2) <= not( g16ev (1) ); + + hc12_c1: c1_b(12) <= not( t16ev (6) ); + hc10_c1: c1_b(10) <= not( t16ev (5) ); + hc08_c1: c1_b( 8) <= not( t16ev (4) ); + hc06_c1: c1_b( 6) <= not( t16ev (3) ); + hc04_c1: c1_b( 4) <= not( t16ev (2) ); + hc02_c1: c1_b( 2) <= not( t16ev (1) ); + + hc11_c0: c0_b(11) <= not( (t01od(5) and g16ev (6)) or g01od(5)); + hc09_c0: c0_b( 9) <= not( (t01od(4) and g16ev (5)) or g01od(4)); + hc07_c0: c0_b( 7) <= not( (t01od(3) and g16ev (4)) or g01od(3)); + hc05_c0: c0_b( 5) <= not( (t01od(2) and g16ev (3)) or g01od(2)); + hc03_c0: c0_b( 3) <= not( (t01od(1) and g16ev (2)) or g01od(1)); + hc01_c0: c0_b( 1) <= not( (t01od(0) and g16ev (1)) or g01od(0)); + + hc13_c1: c1_b(13) <= not( t01od(6)); + hc11_c1: c1_b(11) <= not( (t01od(5) and t16ev (6)) or g01od(5)); + hc09_c1: c1_b( 9) <= not( (t01od(4) and t16ev (5)) or g01od(4)); + hc07_c1: c1_b( 7) <= not( (t01od(3) and t16ev (4)) or g01od(3)); + hc05_c1: c1_b( 5) <= not( (t01od(2) and t16ev (3)) or g01od(2)); + hc03_c1: c1_b( 3) <= not( (t01od(1) and t16ev (2)) or g01od(1)); + hc01_c1: c1_b( 1) <= not( (t01od(0) and t16ev (1)) or g01od(0)); + +--//##################################### +--//## sum +--//##################################### + + hc00_s0: s0( 0) <= ( p01_b( 0) xor c0_b( 1) ); + hc01_s0: s0( 1) <= ( p01_b( 1) xor c0_b( 2) ); + hc02_s0: s0( 2) <= ( p01_b( 2) xor c0_b( 3) ); + hc03_s0: s0( 3) <= ( p01_b( 3) xor c0_b( 4) ); + hc04_s0: s0( 4) <= ( p01_b( 4) xor c0_b( 5) ); + hc05_s0: s0( 5) <= ( p01_b( 5) xor c0_b( 6) ); + hc06_s0: s0( 6) <= ( p01_b( 6) xor c0_b( 7) ); + hc07_s0: s0( 7) <= ( p01_b( 7) xor c0_b( 8) ); + hc08_s0: s0( 8) <= ( p01_b( 8) xor c0_b( 9) ); + hc09_s0: s0( 9) <= ( p01_b( 9) xor c0_b(10) ); + hc10_s0: s0(10) <= ( p01_b(10) xor c0_b(11) ); + hc11_s0: s0(11) <= ( p01_b(11) xor c0_b(12) ); + hc12_s0: s0(12) <= not( p01_b(12) ); + hc13_s0: s0(13) <= not( p01_b(13) ); + + hc00_s1: s1( 0) <= ( p01_b( 0) xor c1_b( 1) ); + hc01_s1: s1( 1) <= ( p01_b( 1) xor c1_b( 2) ); + hc02_s1: s1( 2) <= ( p01_b( 2) xor c1_b( 3) ); + hc03_s1: s1( 3) <= ( p01_b( 3) xor c1_b( 4) ); + hc04_s1: s1( 4) <= ( p01_b( 4) xor c1_b( 5) ); + hc05_s1: s1( 5) <= ( p01_b( 5) xor c1_b( 6) ); + hc06_s1: s1( 6) <= ( p01_b( 6) xor c1_b( 7) ); + hc07_s1: s1( 7) <= ( p01_b( 7) xor c1_b( 8) ); + hc08_s1: s1( 8) <= ( p01_b( 8) xor c1_b( 9) ); + hc09_s1: s1( 9) <= ( p01_b( 9) xor c1_b(10) ); + hc10_s1: s1(10) <= ( p01_b(10) xor c1_b(11) ); + hc11_s1: s1(11) <= ( p01_b(11) xor c1_b(12) ); + hc12_s1: s1(12) <= ( p01_b(12) xor c1_b(13) ); + hc13_s1: s1(13) <= not( p01(13) ); + + +END; -- ARCH fuq_hc16pp_lsb diff --git a/rel/src/vhdl/work/fuq_hc16pp_msb.vhdl b/rel/src/vhdl/work/fuq_hc16pp_msb.vhdl new file mode 100644 index 0000000..8829daa --- /dev/null +++ b/rel/src/vhdl/work/fuq_hc16pp_msb.vhdl @@ -0,0 +1,505 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + + +library ieee; use ieee.std_logic_1164.all ; +library ibm; +library support; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + +ENTITY fuq_hc16pp_msb IS PORT( + x : IN std_ulogic_vector(0 to 15); + y : IN std_ulogic_vector(0 to 15); + ci0 : IN std_ulogic; + ci0_b : IN std_ulogic; + ci1 : IN std_ulogic; + ci1_b : IN std_ulogic; + s0 : OUT std_ulogic_vector(0 to 15); + s1 : OUT std_ulogic_vector(0 to 15); + g16 : out std_ulogic; + t16 : out std_ulogic +); + + +END fuq_hc16pp_msb; + +ARCHITECTURE fuq_hc16pp_msb OF fuq_hc16pp_msb IS + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal g01_b :std_ulogic_vector(1 to 15); + signal t01_b, p01_b, p01 :std_ulogic_vector(0 to 15); + signal g01od, t01od :std_ulogic_vector(0 to 7); + signal g02ev , t02ev :std_ulogic_vector(0 to 7); + signal g02ev_b , t02ev_b :std_ulogic_vector(1 to 7); + signal g04ev, t04ev :std_ulogic_vector(1 to 7); + signal g08ev_b, t08ev_b :std_ulogic_vector(1 to 7); + signal g16ev, t16ev :std_ulogic_vector(1 to 7); + signal c0_b , c1_b :std_ulogic_vector(1 to 15); + signal s0_raw, s1_raw :std_ulogic_vector(0 to 15); + signal s0_x_b, s0_y_b :std_ulogic_vector(0 to 15); + signal s1_x_b, s1_y_b :std_ulogic_vector(0 to 15); + + signal glb_g04_e01_b, glb_g04_e23_b, glb_g04_e45_b, glb_g04_e67_b :std_ulogic; + signal glb_t04_e01_b, glb_t04_e23_b, glb_t04_e45_b, glb_t04_e67_b :std_ulogic; + signal glb_g08_e03 , glb_g08_e47 , glb_t08_e03 , glb_t08_e47 :std_ulogic; + signal glb_g16_e07_b, glb_t16_e07_b :std_ulogic; + + + + + + + + + + +BEGIN + +--//##################################### +--//## group 1 +--//##################################### + + hc01_g01: g01_b( 1) <= not( x( 1) and y( 1) ); --critical + hc02_g01: g01_b( 2) <= not( x( 2) and y( 2) ); --critical + hc03_g01: g01_b( 3) <= not( x( 3) and y( 3) ); --critical + hc04_g01: g01_b( 4) <= not( x( 4) and y( 4) ); --critical + hc05_g01: g01_b( 5) <= not( x( 5) and y( 5) ); --critical + hc06_g01: g01_b( 6) <= not( x( 6) and y( 6) ); --critical + hc07_g01: g01_b( 7) <= not( x( 7) and y( 7) ); --critical + hc08_g01: g01_b( 8) <= not( x( 8) and y( 8) ); --critical + hc09_g01: g01_b( 9) <= not( x( 9) and y( 9) ); --critical + hc10_g01: g01_b(10) <= not( x(10) and y(10) ); --critical + hc11_g01: g01_b(11) <= not( x(11) and y(11) ); --critical + hc12_g01: g01_b(12) <= not( x(12) and y(12) ); --critical + hc13_g01: g01_b(13) <= not( x(13) and y(13) ); --critical + hc14_g01: g01_b(14) <= not( x(14) and y(14) ); --critical + hc15_g01: g01_b(15) <= not( x(15) and y(15) ); --critical + + + hc00_t01: t01_b( 0) <= not( x( 0) and y( 0) ); --critical <==== different then MID + hc01_t01: t01_b( 1) <= not( x( 1) or y( 1) ); --critical + hc02_t01: t01_b( 2) <= not( x( 2) or y( 2) ); --critical + hc03_t01: t01_b( 3) <= not( x( 3) or y( 3) ); --critical + hc04_t01: t01_b( 4) <= not( x( 4) or y( 4) ); --critical + hc05_t01: t01_b( 5) <= not( x( 5) or y( 5) ); --critical + hc06_t01: t01_b( 6) <= not( x( 6) or y( 6) ); --critical + hc07_t01: t01_b( 7) <= not( x( 7) or y( 7) ); --critical + hc08_t01: t01_b( 8) <= not( x( 8) or y( 8) ); --critical + hc09_t01: t01_b( 9) <= not( x( 9) or y( 9) ); --critical + hc10_t01: t01_b(10) <= not( x(10) or y(10) ); --critical + hc11_t01: t01_b(11) <= not( x(11) or y(11) ); --critical + hc12_t01: t01_b(12) <= not( x(12) or y(12) ); --critical + hc13_t01: t01_b(13) <= not( x(13) or y(13) ); --critical + hc14_t01: t01_b(14) <= not( x(14) or y(14) ); --critical + hc15_t01: t01_b(15) <= not( x(15) or y(15) ); --critical + + + hc00_p01: p01( 0) <= not( x( 0) xor y( 0) ); --not critical <==== different than MID + hc01_p01: p01( 1) <= ( x( 1) xor y( 1) ); --not critical + hc02_p01: p01( 2) <= ( x( 2) xor y( 2) ); --not critical + hc03_p01: p01( 3) <= ( x( 3) xor y( 3) ); --not critical + hc04_p01: p01( 4) <= ( x( 4) xor y( 4) ); --not critical + hc05_p01: p01( 5) <= ( x( 5) xor y( 5) ); --not critical + hc06_p01: p01( 6) <= ( x( 6) xor y( 6) ); --not critical + hc07_p01: p01( 7) <= ( x( 7) xor y( 7) ); --not critical + hc08_p01: p01( 8) <= ( x( 8) xor y( 8) ); --not critical + hc09_p01: p01( 9) <= ( x( 9) xor y( 9) ); --not critical + hc10_p01: p01(10) <= ( x(10) xor y(10) ); --not critical + hc11_p01: p01(11) <= ( x(11) xor y(11) ); --not critical + hc12_p01: p01(12) <= ( x(12) xor y(12) ); --not critical + hc13_p01: p01(13) <= ( x(13) xor y(13) ); --not critical + hc14_p01: p01(14) <= ( x(14) xor y(14) ); --not critical + hc15_p01: p01(15) <= ( x(15) xor y(15) ); --not critical + + hc00_p01b: p01_b( 0) <= not( p01( 0) ); --not critical + hc01_p01b: p01_b( 1) <= not( p01( 1) ); --not critical + hc02_p01b: p01_b( 2) <= not( p01( 2) ); --not critical + hc03_p01b: p01_b( 3) <= not( p01( 3) ); --not critical + hc04_p01b: p01_b( 4) <= not( p01( 4) ); --not critical + hc05_p01b: p01_b( 5) <= not( p01( 5) ); --not critical + hc06_p01b: p01_b( 6) <= not( p01( 6) ); --not critical + hc07_p01b: p01_b( 7) <= not( p01( 7) ); --not critical + hc08_p01b: p01_b( 8) <= not( p01( 8) ); --not critical + hc09_p01b: p01_b( 9) <= not( p01( 9) ); --not critical + hc10_p01b: p01_b(10) <= not( p01(10) ); --not critical + hc11_p01b: p01_b(11) <= not( p01(11) ); --not critical + hc12_p01b: p01_b(12) <= not( p01(12) ); --not critical + hc13_p01b: p01_b(13) <= not( p01(13) ); --not critical + hc14_p01b: p01_b(14) <= not( p01(14) ); --not critical + hc15_p01b: p01_b(15) <= not( p01(15) ); --not critical + + + hc01_g01o: g01od(0) <= not g01_b( 1); + hc03_g01o: g01od(1) <= not g01_b( 3); + hc05_g01o: g01od(2) <= not g01_b( 5); + hc07_g01o: g01od(3) <= not g01_b( 7); + hc09_g01o: g01od(4) <= not g01_b( 9); + hc11_g01o: g01od(5) <= not g01_b(11); + hc13_g01o: g01od(6) <= not g01_b(13); + hc15_g01o: g01od(7) <= not g01_b(15); + + hc01_t01o: t01od(0) <= not t01_b( 1); + hc03_t01o: t01od(1) <= not t01_b( 3); + hc05_t01o: t01od(2) <= not t01_b( 5); + hc07_t01o: t01od(3) <= not t01_b( 7); + hc09_t01o: t01od(4) <= not t01_b( 9); + hc11_t01o: t01od(5) <= not t01_b(11); + hc13_t01o: t01od(6) <= not t01_b(13); + hc15_t01o: t01od(7) <= not t01_b(15); + +--//##################################### +--//## group 2 +--//##################################### + + hc14_g02: g02ev(7) <= not( ( t01_b(14) or g01_b(15) ) and g01_b(14) );--final + hc12_g02: g02ev(6) <= not( ( t01_b(12) or g01_b(13) ) and g01_b(12) ); + hc10_g02: g02ev(5) <= not( ( t01_b(10) or g01_b(11) ) and g01_b(10) ); + hc08_g02: g02ev(4) <= not( ( t01_b( 8) or g01_b( 9) ) and g01_b( 8) ); + hc06_g02: g02ev(3) <= not( ( t01_b( 6) or g01_b( 7) ) and g01_b( 6) ); + hc04_g02: g02ev(2) <= not( ( t01_b( 4) or g01_b( 5) ) and g01_b( 4) ); + hc02_g02: g02ev(1) <= not( ( t01_b( 2) or g01_b( 3) ) and g01_b( 2) ); + hc00_g02: g02ev(0) <= not( t01_b( 0) or g01_b( 1) ); -- <==== different than MID + + hc14_t02: t02ev(7) <= not( ( t01_b(14) or t01_b(15) ) and g01_b(14) );--final + hc12_t02: t02ev(6) <= not( t01_b(12) or t01_b(13) ); + hc10_t02: t02ev(5) <= not( t01_b(10) or t01_b(11) ); + hc08_t02: t02ev(4) <= not( t01_b( 8) or t01_b( 9) ); + hc06_t02: t02ev(3) <= not( t01_b( 6) or t01_b( 7) ); + hc04_t02: t02ev(2) <= not( t01_b( 4) or t01_b( 5) ); + hc02_t02: t02ev(1) <= not( t01_b( 2) or t01_b( 3) ); + hc00_t02: t02ev(0) <= not( t01_b( 0) or t01_b( 1) ); + + hc14_g02b: g02ev_b(7) <= not( g02ev(7) ); + hc12_g02b: g02ev_b(6) <= not( g02ev(6) ); + hc10_g02b: g02ev_b(5) <= not( g02ev(5) ); + hc08_g02b: g02ev_b(4) <= not( g02ev(4) ); + hc06_g02b: g02ev_b(3) <= not( g02ev(3) ); + hc04_g02b: g02ev_b(2) <= not( g02ev(2) ); + hc02_g02b: g02ev_b(1) <= not( g02ev(1) ); + + hc14_t02b: t02ev_b(7) <= not( t02ev(7) ); + hc12_t02b: t02ev_b(6) <= not( t02ev(6) ); + hc10_t02b: t02ev_b(5) <= not( t02ev(5) ); + hc08_t02b: t02ev_b(4) <= not( t02ev(4) ); + hc06_t02b: t02ev_b(3) <= not( t02ev(3) ); + hc04_t02b: t02ev_b(2) <= not( t02ev(2) ); + hc02_t02b: t02ev_b(1) <= not( t02ev(1) ); + +--//##################################### +--//## replicating for global chain +--//##################################### + + u_glb_g04_e01: glb_g04_e01_b <= not( g02ev(0) or ( t02ev(0) and g02ev(1) ) ); + u_glb_g04_e23: glb_g04_e23_b <= not( g02ev(2) or ( t02ev(2) and g02ev(3) ) ); + u_glb_g04_e45: glb_g04_e45_b <= not( g02ev(4) or ( t02ev(4) and g02ev(5) ) ); + u_glb_g04_e67: glb_g04_e67_b <= not( g02ev(6) or ( t02ev(6) and g02ev(7) ) ); + u_glb_t04_e01: glb_t04_e01_b <= not( t02ev(0) and t02ev(1) ); + u_glb_t04_e23: glb_t04_e23_b <= not( t02ev(2) and t02ev(3) ); + u_glb_t04_e45: glb_t04_e45_b <= not( t02ev(4) and t02ev(5) ); + u_glb_t04_e67: glb_t04_e67_b <= not( g02ev(6) or ( t02ev(6) and t02ev(7) ) ); + + u_glb_g08_e03: glb_g08_e03 <= not( glb_g04_e01_b and ( glb_t04_e01_b or glb_g04_e23_b ) ); + u_glb_g08_e47: glb_g08_e47 <= not( glb_g04_e45_b and ( glb_t04_e45_b or glb_g04_e67_b ) ); + u_glb_t08_e03: glb_t08_e03 <= not( glb_t04_e01_b or glb_t04_e23_b ); + u_glb_t08_e47: glb_t08_e47 <= not( glb_g04_e45_b and ( glb_t04_e45_b or glb_t04_e67_b ) ); + + u_glb_g16_e07: glb_g16_e07_b <= not( glb_g08_e03 or ( glb_t08_e03 and glb_g08_e47 ) ); + u_glb_t16_e07: glb_t16_e07_b <= not( glb_g08_e03 or ( glb_t08_e03 and glb_t08_e47 ) ); + + u_g16o: g16 <= not( glb_g16_e07_b );--output + u_t16o: t16 <= not( glb_t16_e07_b );--output + + +--//##################################### +--//## group 4 // delayed for local chain ... reverse phase +--//##################################### + + hc14_g04: g04ev(7) <= not( g02ev_b(7) ); + hc12_g04: g04ev(6) <= not( g02ev_b(6) and (t02ev_b(6) or g02ev_b(7)) );--final + hc10_g04: g04ev(5) <= not( g02ev_b(5) and (t02ev_b(5) or g02ev_b(6)) ); + hc08_g04: g04ev(4) <= not( g02ev_b(4) and (t02ev_b(4) or g02ev_b(5)) ); + hc06_g04: g04ev(3) <= not( g02ev_b(3) and (t02ev_b(3) or g02ev_b(4)) ); + hc04_g04: g04ev(2) <= not( g02ev_b(2) and (t02ev_b(2) or g02ev_b(3)) ); + hc02_g04: g04ev(1) <= not( g02ev_b(1) and (t02ev_b(1) or g02ev_b(2)) ); + + + hc14_t04: t04ev(7) <= not( t02ev_b(7) ); + hc12_t04: t04ev(6) <= not( g02ev_b(6) and (t02ev_b(6) or t02ev_b(7)) );--final + hc10_t04: t04ev(5) <= not( t02ev_b(5) or t02ev_b(6) ); + hc08_t04: t04ev(4) <= not( t02ev_b(4) or t02ev_b(5) ); + hc06_t04: t04ev(3) <= not( t02ev_b(3) or t02ev_b(4) ); + hc04_t04: t04ev(2) <= not( t02ev_b(2) or t02ev_b(3) ); + hc02_t04: t04ev(1) <= not( t02ev_b(1) or t02ev_b(2) ); + +--//##################################### +--//## group 8 +--//##################################### + + hc14_g08: g08ev_b(7) <= not( g04ev(7) ); + hc12_g08: g08ev_b(6) <= not( g04ev(6) ); + hc10_g08: g08ev_b(5) <= not( g04ev(5) or (t04ev(5) and g04ev(7)) );--final + hc08_g08: g08ev_b(4) <= not( g04ev(4) or (t04ev(4) and g04ev(6)) );--final + hc06_g08: g08ev_b(3) <= not( g04ev(3) or (t04ev(3) and g04ev(5)) ); + hc04_g08: g08ev_b(2) <= not( g04ev(2) or (t04ev(2) and g04ev(4)) ); + hc02_g08: g08ev_b(1) <= not( g04ev(1) or (t04ev(1) and g04ev(3)) ); + + + hc14_t08: t08ev_b(7) <= not( t04ev(7) ); + hc12_t08: t08ev_b(6) <= not( t04ev(6) ); + hc10_t08: t08ev_b(5) <= not( g04ev(5) or (t04ev(5) and t04ev(7)) );--final + hc08_t08: t08ev_b(4) <= not( g04ev(4) or (t04ev(4) and t04ev(6)) );--final + hc06_t08: t08ev_b(3) <= not( t04ev(3) and t04ev(5) ); + hc04_t08: t08ev_b(2) <= not( t04ev(2) and t04ev(4) ); + hc02_t08: t08ev_b(1) <= not( t04ev(1) and t04ev(3) ); + + +--//##################################### +--//## group 16 +--//##################################### + + hc14_g16: g16ev(7) <= not( g08ev_b(7) ); + hc12_g16: g16ev(6) <= not( g08ev_b(6) ); + hc10_g16: g16ev(5) <= not( g08ev_b(5) ); + hc08_g16: g16ev(4) <= not( g08ev_b(4) ); + hc06_g16: g16ev(3) <= not( g08ev_b(3) and (t08ev_b(3) or g08ev_b(7)) ); --final + hc04_g16: g16ev(2) <= not( g08ev_b(2) and (t08ev_b(2) or g08ev_b(6)) ); --final + hc02_g16: g16ev(1) <= not( g08ev_b(1) and (t08ev_b(1) or g08ev_b(5)) ); --final + + hc14_t16: t16ev(7) <= not( t08ev_b(7) ); + hc12_t16: t16ev(6) <= not( t08ev_b(6) ); + hc10_t16: t16ev(5) <= not( t08ev_b(5) ); + hc08_t16: t16ev(4) <= not( t08ev_b(4) ); + hc06_t16: t16ev(3) <= not( g08ev_b(3) and (t08ev_b(3) or t08ev_b(7)) ); --final + hc04_t16: t16ev(2) <= not( g08ev_b(2) and (t08ev_b(2) or t08ev_b(6)) ); --final + hc02_t16: t16ev(1) <= not( g08ev_b(1) and (t08ev_b(1) or t08ev_b(5)) ); --final + +--//##################################### +--//## group 16 delayed +--//##################################### + + hc14_c0: c0_b(14) <= not( g16ev(7) ); + hc12_c0: c0_b(12) <= not( g16ev(6) ); + hc10_c0: c0_b(10) <= not( g16ev(5) ); + hc08_c0: c0_b( 8) <= not( g16ev(4) ); + hc06_c0: c0_b( 6) <= not( g16ev(3) ); + hc04_c0: c0_b( 4) <= not( g16ev(2) ); + hc02_c0: c0_b( 2) <= not( g16ev(1) ); + + hc14_c1: c1_b(14) <= not( t16ev(7) ); + hc12_c1: c1_b(12) <= not( t16ev(6) ); + hc10_c1: c1_b(10) <= not( t16ev(5) ); + hc08_c1: c1_b( 8) <= not( t16ev(4) ); + hc06_c1: c1_b( 6) <= not( t16ev(3) ); + hc04_c1: c1_b( 4) <= not( t16ev(2) ); + hc02_c1: c1_b( 2) <= not( t16ev(1) ); + + hc15_c0: c0_b(15) <= not( g01od(7)); + hc13_c0: c0_b(13) <= not( (t01od(6) and g16ev(7)) or g01od(6)); + hc11_c0: c0_b(11) <= not( (t01od(5) and g16ev(6)) or g01od(5)); + hc09_c0: c0_b( 9) <= not( (t01od(4) and g16ev(5)) or g01od(4)); + hc07_c0: c0_b( 7) <= not( (t01od(3) and g16ev(4)) or g01od(3)); + hc05_c0: c0_b( 5) <= not( (t01od(2) and g16ev(3)) or g01od(2)); + hc03_c0: c0_b( 3) <= not( (t01od(1) and g16ev(2)) or g01od(1)); + hc01_c0: c0_b( 1) <= not( (t01od(0) and g16ev(1)) or g01od(0)); + + hc15_c1: c1_b(15) <= not( t01od(7) ); + hc13_c1: c1_b(13) <= not( (t01od(6) and t16ev(7)) or g01od(6) ); + hc11_c1: c1_b(11) <= not( (t01od(5) and t16ev(6)) or g01od(5) ); + hc09_c1: c1_b( 9) <= not( (t01od(4) and t16ev(5)) or g01od(4) ); + hc07_c1: c1_b( 7) <= not( (t01od(3) and t16ev(4)) or g01od(3) ); + hc05_c1: c1_b( 5) <= not( (t01od(2) and t16ev(3)) or g01od(2) ); + hc03_c1: c1_b( 3) <= not( (t01od(1) and t16ev(2)) or g01od(1) ); + hc01_c1: c1_b( 1) <= not( (t01od(0) and t16ev(1)) or g01od(0) ); + + +--//##################################### +--//## sum before select +--//##################################### + + hc00_s0r: s0_raw( 0) <= ( p01_b( 0) xor c0_b( 1) ); + hc01_s0r: s0_raw( 1) <= ( p01_b( 1) xor c0_b( 2) ); + hc02_s0r: s0_raw( 2) <= ( p01_b( 2) xor c0_b( 3) ); + hc03_s0r: s0_raw( 3) <= ( p01_b( 3) xor c0_b( 4) ); + hc04_s0r: s0_raw( 4) <= ( p01_b( 4) xor c0_b( 5) ); + hc05_s0r: s0_raw( 5) <= ( p01_b( 5) xor c0_b( 6) ); + hc06_s0r: s0_raw( 6) <= ( p01_b( 6) xor c0_b( 7) ); + hc07_s0r: s0_raw( 7) <= ( p01_b( 7) xor c0_b( 8) ); + hc08_s0r: s0_raw( 8) <= ( p01_b( 8) xor c0_b( 9) ); + hc09_s0r: s0_raw( 9) <= ( p01_b( 9) xor c0_b(10) ); + hc10_s0r: s0_raw(10) <= ( p01_b(10) xor c0_b(11) ); + hc11_s0r: s0_raw(11) <= ( p01_b(11) xor c0_b(12) ); + hc12_s0r: s0_raw(12) <= ( p01_b(12) xor c0_b(13) ); + hc13_s0r: s0_raw(13) <= ( p01_b(13) xor c0_b(14) ); + hc14_s0r: s0_raw(14) <= ( p01_b(14) xor c0_b(15) ); + hc15_s0r: s0_raw(15) <= not p01_b(15); + + hc00_s1r: s1_raw( 0) <= ( p01_b( 0) xor c1_b( 1) ); + hc01_s1r: s1_raw( 1) <= ( p01_b( 1) xor c1_b( 2) ); + hc02_s1r: s1_raw( 2) <= ( p01_b( 2) xor c1_b( 3) ); + hc03_s1r: s1_raw( 3) <= ( p01_b( 3) xor c1_b( 4) ); + hc04_s1r: s1_raw( 4) <= ( p01_b( 4) xor c1_b( 5) ); + hc05_s1r: s1_raw( 5) <= ( p01_b( 5) xor c1_b( 6) ); + hc06_s1r: s1_raw( 6) <= ( p01_b( 6) xor c1_b( 7) ); + hc07_s1r: s1_raw( 7) <= ( p01_b( 7) xor c1_b( 8) ); + hc08_s1r: s1_raw( 8) <= ( p01_b( 8) xor c1_b( 9) ); + hc09_s1r: s1_raw( 9) <= ( p01_b( 9) xor c1_b(10) ); + hc10_s1r: s1_raw(10) <= ( p01_b(10) xor c1_b(11) ); + hc11_s1r: s1_raw(11) <= ( p01_b(11) xor c1_b(12) ); + hc12_s1r: s1_raw(12) <= ( p01_b(12) xor c1_b(13) ); + hc13_s1r: s1_raw(13) <= ( p01_b(13) xor c1_b(14) ); + hc14_s1r: s1_raw(14) <= ( p01_b(14) xor c1_b(15) ); + hc15_s1r: s1_raw(15) <= not s0_raw(15); + + +--//##################################### +--//## sum after select +--//##################################### + + hc00_s0x: s0_x_b( 0) <= not( s0_raw( 0) and ci0_b ); + hc00_s0y: s0_y_b( 0) <= not( s1_raw( 0) and ci0 ); + hc00_s1x: s1_x_b( 0) <= not( s0_raw( 0) and ci1_b ); + hc00_s1y: s1_y_b( 0) <= not( s1_raw( 0) and ci1 ); + hc00_s0: s0 ( 0) <= not( s0_x_b( 0) and s0_y_b( 0) ); + hc00_s1: s1 ( 0) <= not( s1_x_b( 0) and s1_y_b( 0) ); + + hc01_s0x: s0_x_b( 1) <= not( s0_raw( 1) and ci0_b ); + hc01_s0y: s0_y_b( 1) <= not( s1_raw( 1) and ci0 ); + hc01_s1x: s1_x_b( 1) <= not( s0_raw( 1) and ci1_b ); + hc01_s1y: s1_y_b( 1) <= not( s1_raw( 1) and ci1 ); + hc01_s0: s0 ( 1) <= not( s0_x_b( 1) and s0_y_b( 1) ); + hc01_s1: s1 ( 1) <= not( s1_x_b( 1) and s1_y_b( 1) ); + + hc02_s0x: s0_x_b( 2) <= not( s0_raw( 2) and ci0_b ); + hc02_s0y: s0_y_b( 2) <= not( s1_raw( 2) and ci0 ); + hc02_s1x: s1_x_b( 2) <= not( s0_raw( 2) and ci1_b ); + hc02_s1y: s1_y_b( 2) <= not( s1_raw( 2) and ci1 ); + hc02_s0: s0 ( 2) <= not( s0_x_b( 2) and s0_y_b( 2) ); + hc02_s1: s1 ( 2) <= not( s1_x_b( 2) and s1_y_b( 2) ); + + hc03_s0x: s0_x_b( 3) <= not( s0_raw( 3) and ci0_b ); + hc03_s0y: s0_y_b( 3) <= not( s1_raw( 3) and ci0 ); + hc03_s1x: s1_x_b( 3) <= not( s0_raw( 3) and ci1_b ); + hc03_s1y: s1_y_b( 3) <= not( s1_raw( 3) and ci1 ); + hc03_s0: s0 ( 3) <= not( s0_x_b( 3) and s0_y_b( 3) ); + hc03_s1: s1 ( 3) <= not( s1_x_b( 3) and s1_y_b( 3) ); + + hc04_s0x: s0_x_b( 4) <= not( s0_raw( 4) and ci0_b ); + hc04_s0y: s0_y_b( 4) <= not( s1_raw( 4) and ci0 ); + hc04_s1x: s1_x_b( 4) <= not( s0_raw( 4) and ci1_b ); + hc04_s1y: s1_y_b( 4) <= not( s1_raw( 4) and ci1 ); + hc04_s0: s0 ( 4) <= not( s0_x_b( 4) and s0_y_b( 4) ); + hc04_s1: s1 ( 4) <= not( s1_x_b( 4) and s1_y_b( 4) ); + + hc05_s0x: s0_x_b( 5) <= not( s0_raw( 5) and ci0_b ); + hc05_s0y: s0_y_b( 5) <= not( s1_raw( 5) and ci0 ); + hc05_s1x: s1_x_b( 5) <= not( s0_raw( 5) and ci1_b ); + hc05_s1y: s1_y_b( 5) <= not( s1_raw( 5) and ci1 ); + hc05_s0: s0 ( 5) <= not( s0_x_b( 5) and s0_y_b( 5) ); + hc05_s1: s1 ( 5) <= not( s1_x_b( 5) and s1_y_b( 5) ); + + hc06_s0x: s0_x_b( 6) <= not( s0_raw( 6) and ci0_b ); + hc06_s0y: s0_y_b( 6) <= not( s1_raw( 6) and ci0 ); + hc06_s1x: s1_x_b( 6) <= not( s0_raw( 6) and ci1_b ); + hc06_s1y: s1_y_b( 6) <= not( s1_raw( 6) and ci1 ); + hc06_s0: s0 ( 6) <= not( s0_x_b( 6) and s0_y_b( 6) ); + hc06_s1: s1 ( 6) <= not( s1_x_b( 6) and s1_y_b( 6) ); + + hc07_s0x: s0_x_b( 7) <= not( s0_raw( 7) and ci0_b ); + hc07_s0y: s0_y_b( 7) <= not( s1_raw( 7) and ci0 ); + hc07_s1x: s1_x_b( 7) <= not( s0_raw( 7) and ci1_b ); + hc07_s1y: s1_y_b( 7) <= not( s1_raw( 7) and ci1 ); + hc07_s0: s0 ( 7) <= not( s0_x_b( 7) and s0_y_b( 7) ); + hc07_s1: s1 ( 7) <= not( s1_x_b( 7) and s1_y_b( 7) ); + + hc08_s0x: s0_x_b( 8) <= not( s0_raw( 8) and ci0_b ); + hc08_s0y: s0_y_b( 8) <= not( s1_raw( 8) and ci0 ); + hc08_s1x: s1_x_b( 8) <= not( s0_raw( 8) and ci1_b ); + hc08_s1y: s1_y_b( 8) <= not( s1_raw( 8) and ci1 ); + hc08_s0: s0 ( 8) <= not( s0_x_b( 8) and s0_y_b( 8) ); + hc08_s1: s1 ( 8) <= not( s1_x_b( 8) and s1_y_b( 8) ); + + hc09_s0x: s0_x_b( 9) <= not( s0_raw( 9) and ci0_b ); + hc09_s0y: s0_y_b( 9) <= not( s1_raw( 9) and ci0 ); + hc09_s1x: s1_x_b( 9) <= not( s0_raw( 9) and ci1_b ); + hc09_s1y: s1_y_b( 9) <= not( s1_raw( 9) and ci1 ); + hc09_s0: s0 ( 9) <= not( s0_x_b( 9) and s0_y_b( 9) ); + hc09_s1: s1 ( 9) <= not( s1_x_b( 9) and s1_y_b( 9) ); + + hc10_s0x: s0_x_b(10) <= not( s0_raw(10) and ci0_b ); + hc10_s0y: s0_y_b(10) <= not( s1_raw(10) and ci0 ); + hc10_s1x: s1_x_b(10) <= not( s0_raw(10) and ci1_b ); + hc10_s1y: s1_y_b(10) <= not( s1_raw(10) and ci1 ); + hc10_s0: s0 (10) <= not( s0_x_b(10) and s0_y_b(10) ); + hc10_s1: s1 (10) <= not( s1_x_b(10) and s1_y_b(10) ); + + hc11_s0x: s0_x_b(11) <= not( s0_raw(11) and ci0_b ); + hc11_s0y: s0_y_b(11) <= not( s1_raw(11) and ci0 ); + hc11_s1x: s1_x_b(11) <= not( s0_raw(11) and ci1_b ); + hc11_s1y: s1_y_b(11) <= not( s1_raw(11) and ci1 ); + hc11_s0: s0 (11) <= not( s0_x_b(11) and s0_y_b(11) ); + hc11_s1: s1 (11) <= not( s1_x_b(11) and s1_y_b(11) ); + + hc12_s0x: s0_x_b(12) <= not( s0_raw(12) and ci0_b ); + hc12_s0y: s0_y_b(12) <= not( s1_raw(12) and ci0 ); + hc12_s1x: s1_x_b(12) <= not( s0_raw(12) and ci1_b ); + hc12_s1y: s1_y_b(12) <= not( s1_raw(12) and ci1 ); + hc12_s0: s0 (12) <= not( s0_x_b(12) and s0_y_b(12) ); + hc12_s1: s1 (12) <= not( s1_x_b(12) and s1_y_b(12) ); + + hc13_s0x: s0_x_b(13) <= not( s0_raw(13) and ci0_b ); + hc13_s0y: s0_y_b(13) <= not( s1_raw(13) and ci0 ); + hc13_s1x: s1_x_b(13) <= not( s0_raw(13) and ci1_b ); + hc13_s1y: s1_y_b(13) <= not( s1_raw(13) and ci1 ); + hc13_s0: s0 (13) <= not( s0_x_b(13) and s0_y_b(13) ); + hc13_s1: s1 (13) <= not( s1_x_b(13) and s1_y_b(13) ); + + hc14_s0x: s0_x_b(14) <= not( s0_raw(14) and ci0_b ); + hc14_s0y: s0_y_b(14) <= not( s1_raw(14) and ci0 ); + hc14_s1x: s1_x_b(14) <= not( s0_raw(14) and ci1_b ); + hc14_s1y: s1_y_b(14) <= not( s1_raw(14) and ci1 ); + hc14_s0: s0 (14) <= not( s0_x_b(14) and s0_y_b(14) ); + hc14_s1: s1 (14) <= not( s1_x_b(14) and s1_y_b(14) ); + + hc15_s0x: s0_x_b(15) <= not( s0_raw(15) and ci0_b ); + hc15_s0y: s0_y_b(15) <= not( s1_raw(15) and ci0 ); + hc15_s1x: s1_x_b(15) <= not( s0_raw(15) and ci1_b ); + hc15_s1y: s1_y_b(15) <= not( s1_raw(15) and ci1 ); + hc15_s0: s0 (15) <= not( s0_x_b(15) and s0_y_b(15) ); + hc15_s1: s1 (15) <= not( s1_x_b(15) and s1_y_b(15) ); + + + + +END; -- ARCH fuq_hc16pp_msb diff --git a/rel/src/vhdl/work/fuq_loc8inc.vhdl b/rel/src/vhdl/work/fuq_loc8inc.vhdl new file mode 100644 index 0000000..7c8c131 --- /dev/null +++ b/rel/src/vhdl/work/fuq_loc8inc.vhdl @@ -0,0 +1,241 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; use ieee.std_logic_1164.all ; +library ibm; + + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + +entity fuq_loc8inc is port( + x :in std_ulogic_vector(0 to 7); + ci :in std_ulogic; + ci_b :in std_ulogic; + co_b :out std_ulogic; + s0 :out std_ulogic_vector(0 to 7); + s1 :out std_ulogic_vector(0 to 7) +); +END fuq_loc8inc; + +ARCHITECTURE fuq_loc8inc OF fuq_loc8inc IS + + + signal x_if_ci, x_b, x_p :std_ulogic_vector(0 to 7); + signal g2_6t7_b :std_ulogic; + signal g2_4t5_b :std_ulogic; + signal g2_2t3_b :std_ulogic; + signal g2_0t1_b :std_ulogic; + signal g4_4t7 :std_ulogic; + signal g4_0t3 :std_ulogic; + signal t2_6t7 :std_ulogic; + signal t2_4t5 :std_ulogic; + signal t2_2t3 :std_ulogic; + signal t4_6t7_b :std_ulogic; + signal t4_4t7_b :std_ulogic; + signal t4_2t5_b :std_ulogic; + signal t8_6t7 :std_ulogic; + signal t8_4t7 :std_ulogic; + signal t8_2t7 :std_ulogic; + signal t8_7t7_b :std_ulogic; + signal t8_6t7_b :std_ulogic; + signal t8_5t7_b :std_ulogic; + signal t8_4t7_b :std_ulogic; + signal t8_3t7_b :std_ulogic; + signal t8_2t7_b :std_ulogic; + signal t8_1t7_b :std_ulogic; + signal s1x_b, s1y_b, s0_b :std_ulogic_vector(0 to 7); + + + + -- i0_b0 i1_b0 i2_b0 i3_b0 i4_b0 i5_b0 i6_b0 i7_b0 <=== buffer inputs + -- i0_b1 i1_b1 i2_b1 i3_b1 i4_b1 i5_b1 i6_b1 i7_b1 <=== buffer inputs + -- i0_g2 i0_g4 i2_g2 i0_g8 i4_g2 i4_g4 i6_g2 skip <=== global chain + -- skip skip i2_t4 i2_t2 i4_t4 i4_t2 i6_t4 i6_t2 <=== local carry + -- skip skip i2_t8x skip i4_t8x skip i6_t8x skip <=== local carry + -- skip i1_t8 i2_t8 i3_t8 i4_t8 i5_t8 i6_t8 i7_t8 <=== local carry + -- i0_if i1_if i2_if i3_if i4_if i5_if i6_if i7_if <=== local carry + -- i0_s1x i1_s1x i2_s1x i3_s1x i4_s1x i5_s1x i6_s1x i7_s1x <=== carry select + -- i0_s1y i1_s1y i2_s1y i3_s1y i4_s1y i5_s1y i6_s1y i7_s1y <=== carry select + -- i0_s1 i1_s1 i2_s1 i3_s1 i4_s1 i5_s1 i6_s1 i7_s1 <=== carry select + -- i0_s0b i1_s0b i2_s0b i3_s0b i4_s0b i5_s0b i6_s0b i7_s0b <=== carry select + -- i0_s0 i1_s0 i2_s0 i3_s0 i4_s0 i5_s0 i6_s0 i7_s0 <=== carry select + + --FOLDED + + -- i0_b0 i2_b0 i4_b0 i6_b0 skip skip skip skip <=== buffer inputs + -- i1_b0 i3_b0 i5_b0 i7_b0 skip skip skip skip <=== buffer inputs + -- i0_b1 i2_b1 i4_b1 i6_b1 skip skip skip skip <=== buffer inputs + -- i1_b1 i3_b1 i5_b1 i7_b1 skip skip skip skip <=== buffer inputs + -- i0_g2 i2_g2 i4_g2 i6_g2 skip skip skip skip <=== global chain + -- i0_g4 i0_g8 i4_g4 skip skip skip skip skip <=== global chain + -- skip i2_t2 i4_t2 i6_t2 skip skip skip skip <=== local carry + -- skip i2_t4 i4_t4 i6_t4 skip skip skip skip <=== local carry + -- skip i2_t8x i4_t8x i6_t8x skip skip skip skip <=== local carry + -- skip i2_t8 i4_t8 i6_t8 skip skip skip skip <=== local carry + -- i1_t8 i3_t8 i5_t8 i7_t8 skip skip skip skip <=== local carry + -- i0_if i2_if i4_if i6_if skip skip skip skip <=== local carry + -- i1_if i3_if i5_if i7_if skip skip skip skip <=== local carry + -- i0_s1x i2_s1x i4_s1x i6_s1x skip skip skip skip <=== carry select + -- i1_s1x i3_s1x i5_s1x i7_s1x skip skip skip skip <=== carry select + -- i0_s1y i2_s1y i4_s1y i6_s1y skip skip skip skip <=== carry select + -- i1_s1y i3_s1y i5_s1y i7_s1y skip skip skip skip <=== carry select + -- i0_s1 i2_s1 i4_s1 i6_s1 skip skip skip skip <=== carry select + -- i1_s1 i3_s1 i5_s1 i7_s1 skip skip skip skip <=== carry select + -- i0_s0b i2_s0b i4_s0b i6_s0b skip skip skip skip <=== carry select + -- i1_s0b i3_s0b i5_s0b i7_s0b skip skip skip skip <=== carry select + -- i0_s0 i2_s0 i4_s0 i6_s0 skip skip skip skip <=== carry select + -- i1_s0 i3_s0 i5_s0 i7_s0 skip skip skip skip <=== carry select + + + + + + + +BEGIN + + i0_b0: x_b(0) <= not x(0); + i1_b0: x_b(1) <= not x(1); + i2_b0: x_b(2) <= not x(2); + i3_b0: x_b(3) <= not x(3); + i4_b0: x_b(4) <= not x(4); + i5_b0: x_b(5) <= not x(5); + i6_b0: x_b(6) <= not x(6); + i7_b0: x_b(7) <= not x(7); + + i0_b1: x_p(0) <= not x_b(0); + i1_b1: x_p(1) <= not x_b(1); + i2_b1: x_p(2) <= not x_b(2); + i3_b1: x_p(3) <= not x_b(3); + i4_b1: x_p(4) <= not x_b(4); + i5_b1: x_p(5) <= not x_b(5); + i6_b1: x_p(6) <= not x_b(6); + i7_b1: x_p(7) <= not x_b(7); + + ---------------------------------------------- + + i0_g2: g2_0t1_b <= not( x(0) and x(1) ); --0-- + i2_g2: g2_2t3_b <= not( x(2) and x(3) ); --2-- + i4_g2: g2_4t5_b <= not( x(4) and x(5) ); --4-- + i6_g2: g2_6t7_b <= not( x(6) and x(7) ); --6-- + + i0_g4: g4_0t3 <= not( g2_0t1_b or g2_2t3_b );--1-- + i4_g4: g4_4t7 <= not( g2_4t5_b or g2_6t7_b );--5-- + + i0_g8: co_b <= not( g4_0t3 and g4_4t7 ); --3-- ; --output + + --------------------------------------------- + + i2_t2: t2_2t3 <= not( x_b(2) or x_b(3) );--2-- + i4_t2: t2_4t5 <= not( x_b(4) or x_b(5) );--4-- + i6_t2: t2_6t7 <= not( x_b(6) or x_b(7) );--6-- + + i2_t4: t4_2t5_b <= not( t2_2t3 and t2_4t5 );--3-- + i4_t4: t4_4t7_b <= not( t2_4t5 and t2_6t7 );--5-- + i6_t4: t4_6t7_b <= not( t2_6t7 );--7-- + + i2_t8x: t8_2t7 <= not( t4_2t5_b or t4_6t7_b );--3-- + i4_t8x: t8_4t7 <= not( t4_4t7_b ); --5-- + i6_t8x: t8_6t7 <= not( t4_6t7_b ); --7-- + + + i1_t8: t8_1t7_b <= not( t8_2t7 and x_p(1) ); --1-- + i2_t8: t8_2t7_b <= not( t8_2t7 ); --2-- + i3_t8: t8_3t7_b <= not( t8_4t7 and x_p(3) ); --3-- + i4_t8: t8_4t7_b <= not( t8_4t7 ); --4-- + i5_t8: t8_5t7_b <= not( t8_6t7 and x_p(5) ); --5-- + i6_t8: t8_6t7_b <= not( t8_6t7 ); --6-- + i7_t8: t8_7t7_b <= not( x_p(7) ); --7-- + + + -------------------------------------- + + i0_if: x_if_ci(0) <= not (x_p(0) xor t8_1t7_b) ; + i1_if: x_if_ci(1) <= not (x_p(1) xor t8_2t7_b) ; + i2_if: x_if_ci(2) <= not (x_p(2) xor t8_3t7_b) ; + i3_if: x_if_ci(3) <= not (x_p(3) xor t8_4t7_b) ; + i4_if: x_if_ci(4) <= not (x_p(4) xor t8_5t7_b) ; + i5_if: x_if_ci(5) <= not (x_p(5) xor t8_6t7_b) ; + i6_if: x_if_ci(6) <= not (x_p(6) xor t8_7t7_b) ; + i7_if: x_if_ci(7) <= not (x_p(7) ) ; + + + + i0_s1x: s1x_b(0) <= not( x_p(0) and ci_b ) ; + i1_s1x: s1x_b(1) <= not( x_p(1) and ci_b ) ; + i2_s1x: s1x_b(2) <= not( x_p(2) and ci_b ) ; + i3_s1x: s1x_b(3) <= not( x_p(3) and ci_b ) ; + i4_s1x: s1x_b(4) <= not( x_p(4) and ci_b ) ; + i5_s1x: s1x_b(5) <= not( x_p(5) and ci_b ) ; + i6_s1x: s1x_b(6) <= not( x_p(6) and ci_b ) ; + i7_s1x: s1x_b(7) <= not( x_p(7) and ci_b ) ; + + i0_s1y: s1y_b(0) <= not( x_if_ci(0) and ci ) ; + i1_s1y: s1y_b(1) <= not( x_if_ci(1) and ci ) ; + i2_s1y: s1y_b(2) <= not( x_if_ci(2) and ci ) ; + i3_s1y: s1y_b(3) <= not( x_if_ci(3) and ci ) ; + i4_s1y: s1y_b(4) <= not( x_if_ci(4) and ci ) ; + i5_s1y: s1y_b(5) <= not( x_if_ci(5) and ci ) ; + i6_s1y: s1y_b(6) <= not( x_if_ci(6) and ci ) ; + i7_s1y: s1y_b(7) <= not( x_if_ci(7) and ci ) ; + + i0_s1: s1(0) <= not( s1x_b(0) and s1y_b(0) ); --output + i1_s1: s1(1) <= not( s1x_b(1) and s1y_b(1) ); --output + i2_s1: s1(2) <= not( s1x_b(2) and s1y_b(2) ); --output + i3_s1: s1(3) <= not( s1x_b(3) and s1y_b(3) ); --output + i4_s1: s1(4) <= not( s1x_b(4) and s1y_b(4) ); --output + i5_s1: s1(5) <= not( s1x_b(5) and s1y_b(5) ); --output + i6_s1: s1(6) <= not( s1x_b(6) and s1y_b(6) ); --output + i7_s1: s1(7) <= not( s1x_b(7) and s1y_b(7) ); --output + + i0_s0b: s0_b(0) <= not x_p(0) ; + i1_s0b: s0_b(1) <= not x_p(1) ; + i2_s0b: s0_b(2) <= not x_p(2) ; + i3_s0b: s0_b(3) <= not x_p(3) ; + i4_s0b: s0_b(4) <= not x_p(4) ; + i5_s0b: s0_b(5) <= not x_p(5) ; + i6_s0b: s0_b(6) <= not x_p(6) ; + i7_s0b: s0_b(7) <= not x_p(7) ; + + i0_s0: s0(0) <= not s0_b(0) ; -- output + i1_s0: s0(1) <= not s0_b(1) ; -- output + i2_s0: s0(2) <= not s0_b(2) ; -- output + i3_s0: s0(3) <= not s0_b(3) ; -- output + i4_s0: s0(4) <= not s0_b(4) ; -- output + i5_s0: s0(5) <= not s0_b(5) ; -- output + i6_s0: s0(6) <= not s0_b(6) ; -- output + i7_s0: s0(7) <= not s0_b(7) ; -- output + + + +END; -- ARCH fuq_loc8inc diff --git a/rel/src/vhdl/work/fuq_loc8inc_lsb.vhdl b/rel/src/vhdl/work/fuq_loc8inc_lsb.vhdl new file mode 100644 index 0000000..6c53ecd --- /dev/null +++ b/rel/src/vhdl/work/fuq_loc8inc_lsb.vhdl @@ -0,0 +1,114 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; use ieee.std_logic_1164.all ; +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + +entity fuq_loc8inc_lsb is port( + x :in std_ulogic_vector(0 to 4); --48 to 52 + co_b :out std_ulogic; + s0 :out std_ulogic_vector(0 to 4); + s1 :out std_ulogic_vector(0 to 4) +); +END fuq_loc8inc_lsb; + +ARCHITECTURE fuq_loc8inc_lsb OF fuq_loc8inc_lsb IS + + signal x_b, t2_b, t4 :std_ulogic_vector(0 to 4); + + +-- FOLDED layout +-- i0_xb i2_xb i4_xb skip skip skip skip +-- i1_xb i3_xb skip skip skip skip skip +-- i0_t2 i2_t2 i4_t2 skip skip skip skip +-- skip i1_t2 i3_t2 skip skip skip skip +-- i0_t2 i2_t2 i4_t2 skip skip skip skip +-- i0_t8 i1_t2 i3_t2 skip skip skip skip +-- i0_s0 i2_s0 i4_s0 skip skip skip skip +-- i1_s0 i3_s0 skip skip skip skip skip +-- i0_s1 i2_s1 i4_s1 skip skip skip skip +-- i1_s1 i3_s1 skip skip skip skip skip + + + +BEGIN + + --------------------------------- + -- buffer off non critical path + --------------------------------- + + i0_xb: x_b(0) <= not x(0) ; + i1_xb: x_b(1) <= not x(1) ; + i2_xb: x_b(2) <= not x(2) ; + i3_xb: x_b(3) <= not x(3) ; + i4_xb: x_b(4) <= not x(4) ; + + ---------------------------- + -- local carry chain + ---------------------------- + + i0_t2: t2_b(0) <= not( x(0) ); + i1_t2: t2_b(1) <= not( x(1) and x(2) ); + i2_t2: t2_b(2) <= not( x(2) and x(3) ); + i3_t2: t2_b(3) <= not( x(3) and x(4) ); + i4_t2: t2_b(4) <= not( x(4) ); + + i0_t4: t4(0) <= not( t2_b(0) ); + i1_t4: t4(1) <= not( t2_b(1) or t2_b(3) ); + i2_t4: t4(2) <= not( t2_b(2) or t2_b(4) ); + i3_t4: t4(3) <= not( t2_b(3) ); + i4_t4: t4(4) <= not( t2_b(4) ); + + i0_t8: co_b <= not( t4(0) and t4(1) ); + + -------------------------- + -- sum generation + -------------------------- + + i0_s0: s0(0) <= not( x_b(0) ); + i1_s0: s0(1) <= not( x_b(1) ); + i2_s0: s0(2) <= not( x_b(2) ); + i3_s0: s0(3) <= not( x_b(3) ); + i4_s0: s0(4) <= not( x_b(4) ); + + i0_s1: s1(0) <= not( x_b(0) xor t4(1) ); + i1_s1: s1(1) <= not( x_b(1) xor t4(2) ); + i2_s1: s1(2) <= not( x_b(2) xor t4(3) ); + i3_s1: s1(3) <= not( x_b(3) xor t4(4) ); + i4_s1: s1(4) <= not( t4(4) ); + + + + +END; -- ARCH fuq_loc8inc_lsb diff --git a/rel/src/vhdl/work/fuq_lza.vhdl b/rel/src/vhdl/work/fuq_lza.vhdl new file mode 100644 index 0000000..ae780c2 --- /dev/null +++ b/rel/src/vhdl/work/fuq_lza.vhdl @@ -0,0 +1,452 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + + +entity fuq_lza is +generic( expand_type: integer := 2 ); -- 0 - ibm tech, 1 - other ); +port( + + vdd :inout power_logic; + gnd :inout power_logic; + clkoff_b :in std_ulogic; -- tiup + act_dis :in std_ulogic; -- ??tidn?? + flush :in std_ulogic; -- ??tidn?? + delay_lclkr :in std_ulogic_vector(3 to 4); -- tidn, + mpw1_b :in std_ulogic_vector(3 to 4); -- tidn, + mpw2_b :in std_ulogic_vector(0 to 0); -- tidn, + sg_1 :in std_ulogic; + thold_1 :in std_ulogic; + fpu_enable :in std_ulogic; --dc_act + nclk :in clk_logic; + + f_lza_si :in std_ulogic; --perv + f_lza_so :out std_ulogic; --perv + ex1_act_b :in std_ulogic; --act + + f_sa3_ex3_s :in std_ulogic_vector( 0 to 162); -- data + f_sa3_ex3_c :in std_ulogic_vector(53 to 161); -- data + f_alg_ex2_effsub_eac_b :in std_ulogic; + + f_lze_ex2_lzo_din :in std_ulogic_vector(0 to 162); + f_lze_ex3_sh_rgt_amt :in std_ulogic_vector(0 to 7); + f_lze_ex3_sh_rgt_en :in std_ulogic ; + + + f_lza_ex4_no_lza_edge :out std_ulogic; --fpic + f_lza_ex4_lza_amt :out std_ulogic_vector(0 to 7); --fnrm + f_lza_ex4_lza_dcd64_cp1 :out std_ulogic_vector(0 to 2); --fnrm + f_lza_ex4_lza_dcd64_cp2 :out std_ulogic_vector(0 to 1); --fnrm + f_lza_ex4_lza_dcd64_cp3 :out std_ulogic_vector(0 to 0); --fnrm + f_lza_ex4_sh_rgt_en :out std_ulogic; + f_lza_ex4_sh_rgt_en_eov :out std_ulogic; + f_lza_ex4_lza_amt_eov :out std_ulogic_vector(0 to 7) --feov +); + + +end fuq_lza; -- ENTITY + +architecture fuq_lza of fuq_lza is + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal thold_0_b, thold_0, forcee :std_ulogic; + signal sg_0 :std_ulogic; + signal ex2_act :std_ulogic; + signal ex3_act :std_ulogic; + signal ex1_act :std_ulogic; + signal act_spare_unused :std_ulogic_vector(0 to 3); + ---------------------------------------- + signal act_so :std_ulogic_vector(0 to 5);--SCAN + signal act_si :std_ulogic_vector(0 to 5);--SCAN + signal ex3_lzo_so :std_ulogic_vector(0 to 162);--SCAN + signal ex3_lzo_si :std_ulogic_vector(0 to 162);--SCAN + signal ex3_sub_so :std_ulogic_vector(0 to 0);--SCAN + signal ex3_sub_si :std_ulogic_vector(0 to 0);--SCAN + signal ex4_amt_so :std_ulogic_vector(0 to 15);--SCAN + signal ex4_amt_si :std_ulogic_vector(0 to 15);--SCAN + signal ex4_dcd_so :std_ulogic_vector(0 to 8);--SCAN + signal ex4_dcd_si :std_ulogic_vector(0 to 8);--SCAN + ---------------------------------------- + signal ex3_lza_any_b :std_ulogic; + signal ex3_effsub :std_ulogic; + signal ex4_no_edge :std_ulogic; + signal ex3_no_edge_b :std_ulogic; + signal ex3_lzo :std_ulogic_vector(0 to 162); + signal ex3_lza_amt_b :std_ulogic_vector(0 to 7); + signal ex4_amt_eov :std_ulogic_vector(0 to 7); + signal ex4_amt :std_ulogic_vector(0 to 7); + signal ex3_sum :std_ulogic_vector(0 to 162); + signal ex3_car :std_ulogic_vector(53 to 162); + signal ex3_lv0_or :std_ulogic_vector(0 to 162); + signal ex3_sh_rgt_en_b :std_ulogic; + signal ex3_lv6_or_0_b , ex3_lv6_or_1_b , ex3_lv6_or_0_t , ex3_lv6_or_1_t :std_ulogic; + signal ex3_lza_dcd64_0_b , ex3_lza_dcd64_1_b , ex3_lza_dcd64_2_b :std_ulogic; + signal ex4_lza_dcd64_cp1 :std_ulogic_vector(0 to 2); + signal ex4_lza_dcd64_cp2 :std_ulogic_vector(0 to 1); + signal ex4_lza_dcd64_cp3 :std_ulogic_vector(0 to 0); + signal ex4_sh_rgt_en :std_ulogic; + signal ex4_sh_rgt_en_eov :std_ulogic; + signal ex2_effsub_eac, ex2_effsub_eac_b :std_ulogic; + signal ex3_lzo_b, ex3_lzo_l2_b :std_ulogic_vector(0 to 162); + signal ex3_lv6_or_0, ex3_lv6_or_1 :std_ulogic; + signal ex3_rgt_amt_b :std_ulogic_vector(0 to 7); + signal lza_ex4_d1clk , lza_ex4_d2clk :std_ulogic ; + signal lza_ex3_d1clk , lza_ex3_d2clk :std_ulogic ; + signal lza_ex4_lclk :clk_logic ; + signal lza_ex3_lclk :clk_logic ; + + +--=############################################################### +--= map block attributes +--=############################################################### + +begin + +--=############################################################### +--= pervasive +--=############################################################### + + + thold_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => thold_1, + q(0) => thold_0 ); + + sg_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => sg_1 , + q(0) => sg_0 ); + + + lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map ( + clkoff_b => clkoff_b, + thold => thold_0, + sg => sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => thold_0_b ); + + + +--=############################################################### +--= act +--=############################################################### + + ex1_act <= not ex1_act_b; + + act_lat: tri_rlmreg_p generic map (width=> 6, expand_type => expand_type, needs_sreset => 0) port map ( + forcee => forcee,--i-- tidn, + delay_lclkr => delay_lclkr(3) ,--i-- tidn, + mpw1_b => mpw1_b(3) ,--i-- tidn, + mpw2_b => mpw2_b(0) ,--i-- tidn, + vd => vdd, + gd => gnd, + nclk => nclk, + act => fpu_enable, + thold_b => thold_0_b, + sg => sg_0, + scout => act_so , + scin => act_si , + ------------------- + din(0) => act_spare_unused(0), + din(1) => act_spare_unused(1), + din(2) => ex1_act, + din(3) => ex2_act, + din(4) => act_spare_unused(2), + din(5) => act_spare_unused(3), + ------------------- + dout(0) => act_spare_unused(0), + dout(1) => act_spare_unused(1), + dout(2) => ex2_act, + dout(3) => ex3_act, + dout(4) => act_spare_unused(2) , + dout(5) => act_spare_unused(3) ); + + + lza_ex3_lcb : tri_lcbnd generic map (expand_type => expand_type) port map( + delay_lclkr => delay_lclkr(3) ,-- tidn ,--in + mpw1_b => mpw1_b(3) ,-- tidn ,--in + mpw2_b => mpw2_b(0) ,-- tidn ,--in + forcee => forcee,-- tidn ,--in + nclk => nclk ,--in + vd => vdd ,--inout + gd => gnd ,--inout + act => ex2_act ,--in + sg => sg_0 ,--in + thold_b => thold_0_b ,--in + d1clk => lza_ex3_d1clk ,--out + d2clk => lza_ex3_d2clk ,--out + lclk => lza_ex3_lclk );--out + + lza_ex4_lcb : tri_lcbnd generic map (expand_type => expand_type) port map( + delay_lclkr => delay_lclkr(4) ,-- tidn ,--in + mpw1_b => mpw1_b(4) ,-- tidn ,--in + mpw2_b => mpw2_b(0) ,-- tidn ,--in + forcee => forcee,-- tidn ,--in + nclk => nclk ,--in + vd => vdd ,--inout + gd => gnd ,--inout + act => ex3_act ,--in + sg => sg_0 ,--in + thold_b => thold_0_b ,--in + d1clk => lza_ex4_d1clk ,--out + d2clk => lza_ex4_d2clk ,--out + lclk => lza_ex4_lclk );--out + + +--=############################################################### +--= ex3 latches +--=############################################################### + + ex3_lzo_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 163, btr => "NLI0001_X1_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd ,--inout + gd => gnd ,--inout + LCLK => lza_ex3_lclk ,-- lclk.clk + D1CLK => lza_ex3_d1clk , + D2CLK => lza_ex3_d2clk , + SCANIN => ex3_lzo_si , + SCANOUT => ex3_lzo_so , + D => f_lze_ex2_lzo_din(0 to 162), + QB => ex3_lzo_l2_b(0 to 162) ); + + + zobx: ex3_lzo (0 to 162) <= not ex3_lzo_l2_b(0 to 162); + zob: ex3_lzo_b(0 to 162) <= not ex3_lzo (0 to 162); + + ex2_effsub_eac <= not f_alg_ex2_effsub_eac_b ; + ex2_effsub_eac_b <= not ex2_effsub_eac ; + + ex3_sub_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 1, btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd ,--inout + gd => gnd ,--inout + LCLK => lza_ex3_lclk ,-- lclk.clk + D1CLK => lza_ex3_d1clk , + D2CLK => lza_ex3_d2clk , + SCANIN(0) => ex3_sub_si(0) , + SCANOUT(0) => ex3_sub_so(0) , + D(0) => ex2_effsub_eac_b , + QB(0) => ex3_effsub ); + + + ex3_sum(0 to 52) <= f_sa3_ex3_s(0 to 52) ; + +--=############################################################### +--= ex3 logic +--=############################################################### + + ex3_sum(53 to 162) <= f_sa3_ex3_s(53 to 162); + ex3_car(53 to 162) <= f_sa3_ex3_c(53 to 161) & tidn; + + --=#------------------------------------------------ + --=#-- EDGE DETECTION + --=#------------------------------------------------ + + lzaej: entity work.fuq_lza_ej(fuq_lza_ej) port map( + effsub => ex3_effsub ,--i-- + sum(0 to 162) => ex3_sum(0 to 162) ,--i-- + car(53 to 162) => ex3_car(53 to 162) ,--i-- + lzo_b(0 to 162) => ex3_lzo_b(0 to 162) ,--i-- + edge(0 to 162) => ex3_lv0_or(0 to 162) );--o-- + + --=#------------------------------------------------ + --=#-- ENCODING TREE (CLZ) count leading zeroes + --=#------------------------------------------------ + + lzaclz: entity work.fuq_lza_clz(fuq_lza_clz) port map( + lv0_or(0 to 162) => ex3_lv0_or(0 to 162) ,--i-- + lv6_or_0 => ex3_lv6_or_0 ,--o-- + lv6_or_1 => ex3_lv6_or_1 ,--o-- + lza_any_b => ex3_lza_any_b ,--i-- + lza_amt_b(0 to 7) => ex3_lza_amt_b(0 to 7) );--o-- + + + ex3_no_edge_b <= not ex3_lza_any_b ; + +--=############################################################### +--= ex4 latches +--=############################################################### + + ex3_rgt_amt_b(0 to 7) <= not f_lze_ex3_sh_rgt_amt(0 to 7); + + + + ex3_sh_rgt_en_b <= not f_lze_ex3_sh_rgt_en ; + + +lzdz0b: ex3_lv6_or_0_b <= not ex3_lv6_or_0 ; +lzdz1b: ex3_lv6_or_1_b <= not ex3_lv6_or_1 ; +lzdz0t: ex3_lv6_or_0_t <= not ex3_lv6_or_0_b ; +lzdz1t: ex3_lv6_or_1_t <= not ex3_lv6_or_1_b ; + +lzd0b: ex3_lza_dcd64_0_b <= not(ex3_lv6_or_0_t and ex3_sh_rgt_en_b); +lzd1b: ex3_lza_dcd64_1_b <= not(ex3_lv6_or_0_b and ex3_lv6_or_1_t and ex3_sh_rgt_en_b); +lzd2b: ex3_lza_dcd64_2_b <= not(ex3_lv6_or_0_b and ex3_lv6_or_1_b and ex3_sh_rgt_en_b); + + + + + + + ex4_dcd_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 9, btr => "NLI0001_X2_A12TH" , expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd ,--inout + gd => gnd ,--inout + LCLK => lza_ex4_lclk ,-- lclk.clk + D1CLK => lza_ex4_d1clk , + D2CLK => lza_ex4_d2clk , + SCANIN => ex4_dcd_si(0 to 8) , + SCANOUT => ex4_dcd_so(0 to 8) , + D( 0) => ex3_lza_dcd64_0_b ,--( 0) + D( 1) => ex3_lza_dcd64_0_b ,--( 1) + D( 2) => ex3_lza_dcd64_0_b ,--( 2) + D( 3) => ex3_lza_dcd64_1_b ,--( 3) + D( 4) => ex3_lza_dcd64_1_b ,--( 4) + D( 5) => ex3_lza_dcd64_2_b ,--( 5) + D( 6) => ex3_sh_rgt_en_b ,--( 6) + D( 7) => ex3_sh_rgt_en_b ,--( 7) + D( 8) => ex3_no_edge_b ,--(24) + ------------------- + QB( 0) => ex4_lza_dcd64_cp1(0), --( 6) + QB( 1) => ex4_lza_dcd64_cp2(0), --( 9) + QB( 2) => ex4_lza_dcd64_cp3(0), --( 1) + QB( 3) => ex4_lza_dcd64_cp1(1), --( 7) + QB( 4) => ex4_lza_dcd64_cp2(1), --( 0) + QB( 5) => ex4_lza_dcd64_cp1(2), --( 8) + QB( 6) => ex4_sh_rgt_en , --( 2) + QB( 7) => ex4_sh_rgt_en_eov , --( 3) + QB( 8) => ex4_no_edge ); --(24) + + + ex4_amt_lat: entity tri.tri_nand2_nlats(tri_nand2_nlats) generic map (width=> 16, btr => "NLA0001_X1_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd ,--inout + gd => gnd ,--inout + LCLK => lza_ex4_lclk ,--in --lclk.clk + D1CLK => lza_ex4_d1clk ,--in + D2CLK => lza_ex4_d2clk ,--in + SCANIN => ex4_amt_si(0 to 15) , + SCANOUT => ex4_amt_so(0 to 15) , + A1( 0) => ex3_lza_amt_b(0) ,--( 8) + A1( 1) => ex3_lza_amt_b(0) ,--( 9) + A1( 2) => ex3_lza_amt_b(1) ,--(10) + A1( 3) => ex3_lza_amt_b(1) ,--(11) + A1( 4) => ex3_lza_amt_b(2) ,--(12) + A1( 5) => ex3_lza_amt_b(2) ,--(13) + A1( 6) => ex3_lza_amt_b(3) ,--(14) + A1( 7) => ex3_lza_amt_b(3) ,--(15) + A1( 8) => ex3_lza_amt_b(4) ,--(16) + A1( 9) => ex3_lza_amt_b(4) ,--(17) + A1(10) => ex3_lza_amt_b(5) ,--(18) + A1(11) => ex3_lza_amt_b(5) ,--(19) + A1(12) => ex3_lza_amt_b(6) ,--(20) + A1(13) => ex3_lza_amt_b(6) ,--(21) + A1(14) => ex3_lza_amt_b(7) ,--(22) + A1(15) => ex3_lza_amt_b(7) ,--(23) + + A2( 0) => ex3_rgt_amt_b(0) ,--( 8) + A2( 1) => ex3_rgt_amt_b(0) ,--( 9) + A2( 2) => ex3_rgt_amt_b(1) ,--(10) + A2( 3) => ex3_rgt_amt_b(1) ,--(11) + A2( 4) => ex3_rgt_amt_b(2) ,--(12) + A2( 5) => ex3_rgt_amt_b(2) ,--(13) + A2( 6) => ex3_rgt_amt_b(3) ,--(14) + A2( 7) => ex3_rgt_amt_b(3) ,--(15) + A2( 8) => ex3_rgt_amt_b(4) ,--(16) + A2( 9) => ex3_rgt_amt_b(4) ,--(17) + A2(10) => ex3_rgt_amt_b(5) ,--(18) + A2(11) => ex3_rgt_amt_b(5) ,--(19) + A2(12) => ex3_rgt_amt_b(6) ,--(20) + A2(13) => ex3_rgt_amt_b(6) ,--(21) + A2(14) => ex3_rgt_amt_b(7) ,--(22) + A2(15) => ex3_rgt_amt_b(7) ,--(23) + + ------------------- + QB( 0) => ex4_amt(0) , --( 0) + QB( 1) => ex4_amt_eov(0) , --( 8) + QB( 2) => ex4_amt(1) , --(11) + QB( 3) => ex4_amt_eov(1) , --(19) + QB( 4) => ex4_amt(2) , --(12) + QB( 5) => ex4_amt_eov(2) , --(10) + QB( 6) => ex4_amt(3) , --(13) + QB( 7) => ex4_amt_eov(3) , --(11) + QB( 8) => ex4_amt(4) , --(14) + QB( 9) => ex4_amt_eov(4) , --(12) + QB(10) => ex4_amt(5) , --(15) + QB(11) => ex4_amt_eov(5) , --(13) + QB(12) => ex4_amt(6) , --(26) + QB(13) => ex4_amt_eov(6) , --(24) + QB(14) => ex4_amt(7) , --(27) + QB(15) => ex4_amt_eov(7) ); --(24) + + + + + f_lza_ex4_sh_rgt_en <= ex4_sh_rgt_en ; + f_lza_ex4_sh_rgt_en_eov <= ex4_sh_rgt_en_eov ; + + f_lza_ex4_lza_amt <= ex4_amt(0 to 7) ;--output-- --fnrm-- + + f_lza_ex4_lza_dcd64_cp1(0 to 2) <= ex4_lza_dcd64_cp1(0 to 2); --ouptut-- --fnrm + f_lza_ex4_lza_dcd64_cp2(0 to 1) <= ex4_lza_dcd64_cp2(0 to 1); --ouptut-- --fnrm + f_lza_ex4_lza_dcd64_cp3(0) <= ex4_lza_dcd64_cp3(0) ; --ouptut-- --fnrm + + + f_lza_ex4_lza_amt_eov <= ex4_amt_eov(0 to 7) ;--output-- --feov-- + f_lza_ex4_no_lza_edge <= ex4_no_edge ;--output-- --fpic-- + +--=############################################################### +--= scan string +--=############################################################### + + ex3_lzo_si (0 to 162) <= ex3_lzo_so (1 to 162) & f_lza_si ; + ex3_sub_si (0) <= ex3_lzo_so (0); + ex4_amt_si (0 to 15) <= ex4_amt_so (1 to 15) & ex3_sub_so (0); + ex4_dcd_si (0 to 8) <= ex4_dcd_so (1 to 8) & ex4_amt_so (0); + act_si (0 to 5) <= act_so (1 to 5) & ex4_dcd_so (0); + f_lza_so <= act_so (0); + + + +end; -- fuq_lza ARCHITECTURE diff --git a/rel/src/vhdl/work/fuq_lza_clz.vhdl b/rel/src/vhdl/work/fuq_lza_clz.vhdl new file mode 100644 index 0000000..b34bf90 --- /dev/null +++ b/rel/src/vhdl/work/fuq_lza_clz.vhdl @@ -0,0 +1,981 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; use ieee.std_logic_1164.all ; +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + +entity fuq_lza_clz is port( + lv0_or :in std_ulogic_vector(0 to 162); + lv6_or_0 :out std_ulogic; + lv6_or_1 :out std_ulogic; + lza_any_b :out std_ulogic ; + lza_amt_b :out std_ulogic_vector(0 to 7) + ); +END fuq_lza_clz; + + +ARCHITECTURE fuq_lza_clz OF fuq_lza_clz IS + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal lv1_or_b :std_ulogic_vector(0 to 81);-- group_002 + signal lv1_inv_b :std_ulogic_vector(0 to 81); + signal lv1_enc7_b :std_ulogic_vector(0 to 81); + + signal lv2_or :std_ulogic_vector(0 to 40);-- group_004 + signal lv2_inv :std_ulogic_vector(0 to 40); + signal lv2_enc6 :std_ulogic_vector(0 to 40); + signal lv2_enc7 :std_ulogic_vector(0 to 40); + + signal lv3_or_b :std_ulogic_vector(0 to 20);-- group_008 + signal lv3_inv_b :std_ulogic_vector(0 to 20);-- group_008 + signal lv3_enc5_b :std_ulogic_vector(0 to 20); + signal lv3_enc6_b :std_ulogic_vector(0 to 20); + signal lv3_enc7_b :std_ulogic_vector(0 to 20); + + signal lv4_or :std_ulogic_vector(0 to 10);-- group_016 + signal lv4_inv :std_ulogic_vector(0 to 10);-- group_016 + signal lv4_enc4 :std_ulogic_vector(0 to 10); + signal lv4_enc5 :std_ulogic_vector(0 to 10); + signal lv4_enc6 :std_ulogic_vector(0 to 10); + signal lv4_enc7 :std_ulogic_vector(0 to 10); + + signal lv4_or_b :std_ulogic_vector(0 to 10);-- group_016 + signal lv4_enc4_b :std_ulogic_vector(0 to 10); + signal lv4_enc5_b :std_ulogic_vector(0 to 10); + signal lv4_enc6_b :std_ulogic_vector(0 to 10); + signal lv4_enc7_b :std_ulogic_vector(0 to 10); + + ------------------------------------------------------------- + + signal lv5_or :std_ulogic_vector(0 to 5);-- group_032 + signal lv5_inv :std_ulogic_vector(0 to 5); + signal lv5_enc3 :std_ulogic_vector(0 to 5); + signal lv5_enc4 :std_ulogic_vector(0 to 5); + signal lv5_enc5 :std_ulogic_vector(0 to 5); + signal lv5_enc6 :std_ulogic_vector(0 to 5); + signal lv5_enc7 :std_ulogic_vector(0 to 5); + + signal lv6_or_b :std_ulogic_vector(0 to 2);-- group_064 + signal lv6_inv_b :std_ulogic_vector(0 to 2); + signal lv6_enc2_b :std_ulogic_vector(0 to 2); + signal lv6_enc3_b :std_ulogic_vector(0 to 2); + signal lv6_enc4_b :std_ulogic_vector(0 to 2); + signal lv6_enc5_b :std_ulogic_vector(0 to 2); + signal lv6_enc6_b :std_ulogic_vector(0 to 2); + signal lv6_enc7_b :std_ulogic_vector(0 to 2); + + signal lv7_or :std_ulogic_vector(0 to 1);-- group_128 + signal lv7_inv :std_ulogic_vector(0 to 1); + signal lv7_enc1 :std_ulogic_vector(0 to 1); + signal lv7_enc2 :std_ulogic_vector(0 to 1); + signal lv7_enc3 :std_ulogic_vector(0 to 1); + signal lv7_enc4 :std_ulogic_vector(0 to 1); + signal lv7_enc5 :std_ulogic_vector(0 to 1); + signal lv7_enc6 :std_ulogic_vector(0 to 1); + signal lv7_enc7 :std_ulogic_vector(0 to 1); + + signal lv8_or_b :std_ulogic_vector(0 to 0);-- group_256 + signal lv8_inv_b :std_ulogic_vector(0 to 0); + signal lv8_enc0_b :std_ulogic_vector(0 to 0); + signal lv8_enc1_b :std_ulogic_vector(0 to 0); + signal lv8_enc2_b :std_ulogic_vector(0 to 0); + signal lv8_enc3_b :std_ulogic_vector(0 to 0); + signal lv8_enc4_b :std_ulogic_vector(0 to 0); + signal lv8_enc5_b :std_ulogic_vector(0 to 0); + signal lv8_enc6_b :std_ulogic_vector(0 to 0); + signal lv8_enc7_b :std_ulogic_vector(0 to 0); + + + + + + + + + + +BEGIN + +--=#------------------------------------------------ +--=#-- ENCODING TREE (CLZ) count leading zeroes +--=#------------------------------------------------ + ---------------------------------------------------------------------------------- + -- 002 bit group (phase_in=P, phase_out=N, level_in=lv0, level_out=lv1) + ---------------------------------------------------------------------------------- + + b000_002_any: lv1_or_b(0) <= not( lv0_or(0) or lv0_or(1) ); + b001_002_any: lv1_or_b(1) <= not( lv0_or(2) or lv0_or(3) ); + b002_002_any: lv1_or_b(2) <= not( lv0_or(4) or lv0_or(5) ); + b003_002_any: lv1_or_b(3) <= not( lv0_or(6) or lv0_or(7) ); + b004_002_any: lv1_or_b(4) <= not( lv0_or(8) or lv0_or(9) ); + b005_002_any: lv1_or_b(5) <= not( lv0_or(10) or lv0_or(11) ); + b006_002_any: lv1_or_b(6) <= not( lv0_or(12) or lv0_or(13) ); + b007_002_any: lv1_or_b(7) <= not( lv0_or(14) or lv0_or(15) ); + b008_002_any: lv1_or_b(8) <= not( lv0_or(16) or lv0_or(17) ); + b009_002_any: lv1_or_b(9) <= not( lv0_or(18) or lv0_or(19) ); + b010_002_any: lv1_or_b(10) <= not( lv0_or(20) or lv0_or(21) ); + b011_002_any: lv1_or_b(11) <= not( lv0_or(22) or lv0_or(23) ); + b012_002_any: lv1_or_b(12) <= not( lv0_or(24) or lv0_or(25) ); + b013_002_any: lv1_or_b(13) <= not( lv0_or(26) or lv0_or(27) ); + b014_002_any: lv1_or_b(14) <= not( lv0_or(28) or lv0_or(29) ); + b015_002_any: lv1_or_b(15) <= not( lv0_or(30) or lv0_or(31) ); + b016_002_any: lv1_or_b(16) <= not( lv0_or(32) or lv0_or(33) ); + b017_002_any: lv1_or_b(17) <= not( lv0_or(34) or lv0_or(35) ); + b018_002_any: lv1_or_b(18) <= not( lv0_or(36) or lv0_or(37) ); + b019_002_any: lv1_or_b(19) <= not( lv0_or(38) or lv0_or(39) ); + b020_002_any: lv1_or_b(20) <= not( lv0_or(40) or lv0_or(41) ); + b021_002_any: lv1_or_b(21) <= not( lv0_or(42) or lv0_or(43) ); + b022_002_any: lv1_or_b(22) <= not( lv0_or(44) or lv0_or(45) ); + b023_002_any: lv1_or_b(23) <= not( lv0_or(46) or lv0_or(47) ); + b024_002_any: lv1_or_b(24) <= not( lv0_or(48) or lv0_or(49) ); + b025_002_any: lv1_or_b(25) <= not( lv0_or(50) or lv0_or(51) ); + b026_002_any: lv1_or_b(26) <= not( lv0_or(52) or lv0_or(53) ); + b027_002_any: lv1_or_b(27) <= not( lv0_or(54) or lv0_or(55) ); + b028_002_any: lv1_or_b(28) <= not( lv0_or(56) or lv0_or(57) ); + b029_002_any: lv1_or_b(29) <= not( lv0_or(58) or lv0_or(59) ); + b030_002_any: lv1_or_b(30) <= not( lv0_or(60) or lv0_or(61) ); + b031_002_any: lv1_or_b(31) <= not( lv0_or(62) or lv0_or(63) ); + b032_002_any: lv1_or_b(32) <= not( lv0_or(64) or lv0_or(65) ); + b033_002_any: lv1_or_b(33) <= not( lv0_or(66) or lv0_or(67) ); + b034_002_any: lv1_or_b(34) <= not( lv0_or(68) or lv0_or(69) ); + b035_002_any: lv1_or_b(35) <= not( lv0_or(70) or lv0_or(71) ); + b036_002_any: lv1_or_b(36) <= not( lv0_or(72) or lv0_or(73) ); + b037_002_any: lv1_or_b(37) <= not( lv0_or(74) or lv0_or(75) ); + b038_002_any: lv1_or_b(38) <= not( lv0_or(76) or lv0_or(77) ); + b039_002_any: lv1_or_b(39) <= not( lv0_or(78) or lv0_or(79) ); + b040_002_any: lv1_or_b(40) <= not( lv0_or(80) or lv0_or(81) ); + b041_002_any: lv1_or_b(41) <= not( lv0_or(82) or lv0_or(83) ); + b042_002_any: lv1_or_b(42) <= not( lv0_or(84) or lv0_or(85) ); + b043_002_any: lv1_or_b(43) <= not( lv0_or(86) or lv0_or(87) ); + b044_002_any: lv1_or_b(44) <= not( lv0_or(88) or lv0_or(89) ); + b045_002_any: lv1_or_b(45) <= not( lv0_or(90) or lv0_or(91) ); + b046_002_any: lv1_or_b(46) <= not( lv0_or(92) or lv0_or(93) ); + b047_002_any: lv1_or_b(47) <= not( lv0_or(94) or lv0_or(95) ); + b048_002_any: lv1_or_b(48) <= not( lv0_or(96) or lv0_or(97) ); + b049_002_any: lv1_or_b(49) <= not( lv0_or(98) or lv0_or(99) ); + b050_002_any: lv1_or_b(50) <= not( lv0_or(100) or lv0_or(101) ); + b051_002_any: lv1_or_b(51) <= not( lv0_or(102) or lv0_or(103) ); + b052_002_any: lv1_or_b(52) <= not( lv0_or(104) or lv0_or(105) ); + b053_002_any: lv1_or_b(53) <= not( lv0_or(106) or lv0_or(107) ); + b054_002_any: lv1_or_b(54) <= not( lv0_or(108) or lv0_or(109) ); + b055_002_any: lv1_or_b(55) <= not( lv0_or(110) or lv0_or(111) ); + b056_002_any: lv1_or_b(56) <= not( lv0_or(112) or lv0_or(113) ); + b057_002_any: lv1_or_b(57) <= not( lv0_or(114) or lv0_or(115) ); + b058_002_any: lv1_or_b(58) <= not( lv0_or(116) or lv0_or(117) ); + b059_002_any: lv1_or_b(59) <= not( lv0_or(118) or lv0_or(119) ); + b060_002_any: lv1_or_b(60) <= not( lv0_or(120) or lv0_or(121) ); + b061_002_any: lv1_or_b(61) <= not( lv0_or(122) or lv0_or(123) ); + b062_002_any: lv1_or_b(62) <= not( lv0_or(124) or lv0_or(125) ); + b063_002_any: lv1_or_b(63) <= not( lv0_or(126) or lv0_or(127) ); + b064_002_any: lv1_or_b(64) <= not( lv0_or(128) or lv0_or(129) ); + b065_002_any: lv1_or_b(65) <= not( lv0_or(130) or lv0_or(131) ); + b066_002_any: lv1_or_b(66) <= not( lv0_or(132) or lv0_or(133) ); + b067_002_any: lv1_or_b(67) <= not( lv0_or(134) or lv0_or(135) ); + b068_002_any: lv1_or_b(68) <= not( lv0_or(136) or lv0_or(137) ); + b069_002_any: lv1_or_b(69) <= not( lv0_or(138) or lv0_or(139) ); + b070_002_any: lv1_or_b(70) <= not( lv0_or(140) or lv0_or(141) ); + b071_002_any: lv1_or_b(71) <= not( lv0_or(142) or lv0_or(143) ); + b072_002_any: lv1_or_b(72) <= not( lv0_or(144) or lv0_or(145) ); + b073_002_any: lv1_or_b(73) <= not( lv0_or(146) or lv0_or(147) ); + b074_002_any: lv1_or_b(74) <= not( lv0_or(148) or lv0_or(149) ); + b075_002_any: lv1_or_b(75) <= not( lv0_or(150) or lv0_or(151) ); + b076_002_any: lv1_or_b(76) <= not( lv0_or(152) or lv0_or(153) ); + b077_002_any: lv1_or_b(77) <= not( lv0_or(154) or lv0_or(155) ); + b078_002_any: lv1_or_b(78) <= not( lv0_or(156) or lv0_or(157) ); + b079_002_any: lv1_or_b(79) <= not( lv0_or(158) or lv0_or(159) ); + b080_002_any: lv1_or_b(80) <= not( lv0_or(160) or lv0_or(161) ); + b081_002_any: lv1_or_b(81) <= not( lv0_or(162) ); + + b000_002_inv: lv1_inv_b(0) <= not( lv0_or(0) ); + b001_002_inv: lv1_inv_b(1) <= not( lv0_or(2) ); + b002_002_inv: lv1_inv_b(2) <= not( lv0_or(4) ); + b003_002_inv: lv1_inv_b(3) <= not( lv0_or(6) ); + b004_002_inv: lv1_inv_b(4) <= not( lv0_or(8) ); + b005_002_inv: lv1_inv_b(5) <= not( lv0_or(10) ); + b006_002_inv: lv1_inv_b(6) <= not( lv0_or(12) ); + b007_002_inv: lv1_inv_b(7) <= not( lv0_or(14) ); + b008_002_inv: lv1_inv_b(8) <= not( lv0_or(16) ); + b009_002_inv: lv1_inv_b(9) <= not( lv0_or(18) ); + b010_002_inv: lv1_inv_b(10) <= not( lv0_or(20) ); + b011_002_inv: lv1_inv_b(11) <= not( lv0_or(22) ); + b012_002_inv: lv1_inv_b(12) <= not( lv0_or(24) ); + b013_002_inv: lv1_inv_b(13) <= not( lv0_or(26) ); + b014_002_inv: lv1_inv_b(14) <= not( lv0_or(28) ); + b015_002_inv: lv1_inv_b(15) <= not( lv0_or(30) ); + b016_002_inv: lv1_inv_b(16) <= not( lv0_or(32) ); + b017_002_inv: lv1_inv_b(17) <= not( lv0_or(34) ); + b018_002_inv: lv1_inv_b(18) <= not( lv0_or(36) ); + b019_002_inv: lv1_inv_b(19) <= not( lv0_or(38) ); + b020_002_inv: lv1_inv_b(20) <= not( lv0_or(40) ); + b021_002_inv: lv1_inv_b(21) <= not( lv0_or(42) ); + b022_002_inv: lv1_inv_b(22) <= not( lv0_or(44) ); + b023_002_inv: lv1_inv_b(23) <= not( lv0_or(46) ); + b024_002_inv: lv1_inv_b(24) <= not( lv0_or(48) ); + b025_002_inv: lv1_inv_b(25) <= not( lv0_or(50) ); + b026_002_inv: lv1_inv_b(26) <= not( lv0_or(52) ); + b027_002_inv: lv1_inv_b(27) <= not( lv0_or(54) ); + b028_002_inv: lv1_inv_b(28) <= not( lv0_or(56) ); + b029_002_inv: lv1_inv_b(29) <= not( lv0_or(58) ); + b030_002_inv: lv1_inv_b(30) <= not( lv0_or(60) ); + b031_002_inv: lv1_inv_b(31) <= not( lv0_or(62) ); + b032_002_inv: lv1_inv_b(32) <= not( lv0_or(64) ); + b033_002_inv: lv1_inv_b(33) <= not( lv0_or(66) ); + b034_002_inv: lv1_inv_b(34) <= not( lv0_or(68) ); + b035_002_inv: lv1_inv_b(35) <= not( lv0_or(70) ); + b036_002_inv: lv1_inv_b(36) <= not( lv0_or(72) ); + b037_002_inv: lv1_inv_b(37) <= not( lv0_or(74) ); + b038_002_inv: lv1_inv_b(38) <= not( lv0_or(76) ); + b039_002_inv: lv1_inv_b(39) <= not( lv0_or(78) ); + b040_002_inv: lv1_inv_b(40) <= not( lv0_or(80) ); + b041_002_inv: lv1_inv_b(41) <= not( lv0_or(82) ); + b042_002_inv: lv1_inv_b(42) <= not( lv0_or(84) ); + b043_002_inv: lv1_inv_b(43) <= not( lv0_or(86) ); + b044_002_inv: lv1_inv_b(44) <= not( lv0_or(88) ); + b045_002_inv: lv1_inv_b(45) <= not( lv0_or(90) ); + b046_002_inv: lv1_inv_b(46) <= not( lv0_or(92) ); + b047_002_inv: lv1_inv_b(47) <= not( lv0_or(94) ); + b048_002_inv: lv1_inv_b(48) <= not( lv0_or(96) ); + b049_002_inv: lv1_inv_b(49) <= not( lv0_or(98) ); + b050_002_inv: lv1_inv_b(50) <= not( lv0_or(100) ); + b051_002_inv: lv1_inv_b(51) <= not( lv0_or(102) ); + b052_002_inv: lv1_inv_b(52) <= not( lv0_or(104) ); + b053_002_inv: lv1_inv_b(53) <= not( lv0_or(106) ); + b054_002_inv: lv1_inv_b(54) <= not( lv0_or(108) ); + b055_002_inv: lv1_inv_b(55) <= not( lv0_or(110) ); + b056_002_inv: lv1_inv_b(56) <= not( lv0_or(112) ); + b057_002_inv: lv1_inv_b(57) <= not( lv0_or(114) ); + b058_002_inv: lv1_inv_b(58) <= not( lv0_or(116) ); + b059_002_inv: lv1_inv_b(59) <= not( lv0_or(118) ); + b060_002_inv: lv1_inv_b(60) <= not( lv0_or(120) ); + b061_002_inv: lv1_inv_b(61) <= not( lv0_or(122) ); + b062_002_inv: lv1_inv_b(62) <= not( lv0_or(124) ); + b063_002_inv: lv1_inv_b(63) <= not( lv0_or(126) ); + b064_002_inv: lv1_inv_b(64) <= not( lv0_or(128) ); + b065_002_inv: lv1_inv_b(65) <= not( lv0_or(130) ); + b066_002_inv: lv1_inv_b(66) <= not( lv0_or(132) ); + b067_002_inv: lv1_inv_b(67) <= not( lv0_or(134) ); + b068_002_inv: lv1_inv_b(68) <= not( lv0_or(136) ); + b069_002_inv: lv1_inv_b(69) <= not( lv0_or(138) ); + b070_002_inv: lv1_inv_b(70) <= not( lv0_or(140) ); + b071_002_inv: lv1_inv_b(71) <= not( lv0_or(142) ); + b072_002_inv: lv1_inv_b(72) <= not( lv0_or(144) ); + b073_002_inv: lv1_inv_b(73) <= not( lv0_or(146) ); + b074_002_inv: lv1_inv_b(74) <= not( lv0_or(148) ); + b075_002_inv: lv1_inv_b(75) <= not( lv0_or(150) ); + b076_002_inv: lv1_inv_b(76) <= not( lv0_or(152) ); + b077_002_inv: lv1_inv_b(77) <= not( lv0_or(154) ); + b078_002_inv: lv1_inv_b(78) <= not( lv0_or(156) ); + b079_002_inv: lv1_inv_b(79) <= not( lv0_or(158) ); + b080_002_inv: lv1_inv_b(80) <= not( lv0_or(160) ); + b081_002_inv: lv1_inv_b(81) <= not( lv0_or(162) ); + + b000_002_enc7: lv1_enc7_b(0) <= not( lv1_inv_b(0) and lv0_or(1) ); + b001_002_enc7: lv1_enc7_b(1) <= not( lv1_inv_b(1) and lv0_or(3) ); + b002_002_enc7: lv1_enc7_b(2) <= not( lv1_inv_b(2) and lv0_or(5) ); + b003_002_enc7: lv1_enc7_b(3) <= not( lv1_inv_b(3) and lv0_or(7) ); + b004_002_enc7: lv1_enc7_b(4) <= not( lv1_inv_b(4) and lv0_or(9) ); + b005_002_enc7: lv1_enc7_b(5) <= not( lv1_inv_b(5) and lv0_or(11) ); + b006_002_enc7: lv1_enc7_b(6) <= not( lv1_inv_b(6) and lv0_or(13) ); + b007_002_enc7: lv1_enc7_b(7) <= not( lv1_inv_b(7) and lv0_or(15) ); + b008_002_enc7: lv1_enc7_b(8) <= not( lv1_inv_b(8) and lv0_or(17) ); + b009_002_enc7: lv1_enc7_b(9) <= not( lv1_inv_b(9) and lv0_or(19) ); + b010_002_enc7: lv1_enc7_b(10) <= not( lv1_inv_b(10) and lv0_or(21) ); + b011_002_enc7: lv1_enc7_b(11) <= not( lv1_inv_b(11) and lv0_or(23) ); + b012_002_enc7: lv1_enc7_b(12) <= not( lv1_inv_b(12) and lv0_or(25) ); + b013_002_enc7: lv1_enc7_b(13) <= not( lv1_inv_b(13) and lv0_or(27) ); + b014_002_enc7: lv1_enc7_b(14) <= not( lv1_inv_b(14) and lv0_or(29) ); + b015_002_enc7: lv1_enc7_b(15) <= not( lv1_inv_b(15) and lv0_or(31) ); + b016_002_enc7: lv1_enc7_b(16) <= not( lv1_inv_b(16) and lv0_or(33) ); + b017_002_enc7: lv1_enc7_b(17) <= not( lv1_inv_b(17) and lv0_or(35) ); + b018_002_enc7: lv1_enc7_b(18) <= not( lv1_inv_b(18) and lv0_or(37) ); + b019_002_enc7: lv1_enc7_b(19) <= not( lv1_inv_b(19) and lv0_or(39) ); + b020_002_enc7: lv1_enc7_b(20) <= not( lv1_inv_b(20) and lv0_or(41) ); + b021_002_enc7: lv1_enc7_b(21) <= not( lv1_inv_b(21) and lv0_or(43) ); + b022_002_enc7: lv1_enc7_b(22) <= not( lv1_inv_b(22) and lv0_or(45) ); + b023_002_enc7: lv1_enc7_b(23) <= not( lv1_inv_b(23) and lv0_or(47) ); + b024_002_enc7: lv1_enc7_b(24) <= not( lv1_inv_b(24) and lv0_or(49) ); + b025_002_enc7: lv1_enc7_b(25) <= not( lv1_inv_b(25) and lv0_or(51) ); + b026_002_enc7: lv1_enc7_b(26) <= not( lv1_inv_b(26) and lv0_or(53) ); + b027_002_enc7: lv1_enc7_b(27) <= not( lv1_inv_b(27) and lv0_or(55) ); + b028_002_enc7: lv1_enc7_b(28) <= not( lv1_inv_b(28) and lv0_or(57) ); + b029_002_enc7: lv1_enc7_b(29) <= not( lv1_inv_b(29) and lv0_or(59) ); + b030_002_enc7: lv1_enc7_b(30) <= not( lv1_inv_b(30) and lv0_or(61) ); + b031_002_enc7: lv1_enc7_b(31) <= not( lv1_inv_b(31) and lv0_or(63) ); + b032_002_enc7: lv1_enc7_b(32) <= not( lv1_inv_b(32) and lv0_or(65) ); + b033_002_enc7: lv1_enc7_b(33) <= not( lv1_inv_b(33) and lv0_or(67) ); + b034_002_enc7: lv1_enc7_b(34) <= not( lv1_inv_b(34) and lv0_or(69) ); + b035_002_enc7: lv1_enc7_b(35) <= not( lv1_inv_b(35) and lv0_or(71) ); + b036_002_enc7: lv1_enc7_b(36) <= not( lv1_inv_b(36) and lv0_or(73) ); + b037_002_enc7: lv1_enc7_b(37) <= not( lv1_inv_b(37) and lv0_or(75) ); + b038_002_enc7: lv1_enc7_b(38) <= not( lv1_inv_b(38) and lv0_or(77) ); + b039_002_enc7: lv1_enc7_b(39) <= not( lv1_inv_b(39) and lv0_or(79) ); + b040_002_enc7: lv1_enc7_b(40) <= not( lv1_inv_b(40) and lv0_or(81) ); + b041_002_enc7: lv1_enc7_b(41) <= not( lv1_inv_b(41) and lv0_or(83) ); + b042_002_enc7: lv1_enc7_b(42) <= not( lv1_inv_b(42) and lv0_or(85) ); + b043_002_enc7: lv1_enc7_b(43) <= not( lv1_inv_b(43) and lv0_or(87) ); + b044_002_enc7: lv1_enc7_b(44) <= not( lv1_inv_b(44) and lv0_or(89) ); + b045_002_enc7: lv1_enc7_b(45) <= not( lv1_inv_b(45) and lv0_or(91) ); + b046_002_enc7: lv1_enc7_b(46) <= not( lv1_inv_b(46) and lv0_or(93) ); + b047_002_enc7: lv1_enc7_b(47) <= not( lv1_inv_b(47) and lv0_or(95) ); + b048_002_enc7: lv1_enc7_b(48) <= not( lv1_inv_b(48) and lv0_or(97) ); + b049_002_enc7: lv1_enc7_b(49) <= not( lv1_inv_b(49) and lv0_or(99) ); + b050_002_enc7: lv1_enc7_b(50) <= not( lv1_inv_b(50) and lv0_or(101) ); + b051_002_enc7: lv1_enc7_b(51) <= not( lv1_inv_b(51) and lv0_or(103) ); + b052_002_enc7: lv1_enc7_b(52) <= not( lv1_inv_b(52) and lv0_or(105) ); + b053_002_enc7: lv1_enc7_b(53) <= not( lv1_inv_b(53) and lv0_or(107) ); + b054_002_enc7: lv1_enc7_b(54) <= not( lv1_inv_b(54) and lv0_or(109) ); + b055_002_enc7: lv1_enc7_b(55) <= not( lv1_inv_b(55) and lv0_or(111) ); + b056_002_enc7: lv1_enc7_b(56) <= not( lv1_inv_b(56) and lv0_or(113) ); + b057_002_enc7: lv1_enc7_b(57) <= not( lv1_inv_b(57) and lv0_or(115) ); + b058_002_enc7: lv1_enc7_b(58) <= not( lv1_inv_b(58) and lv0_or(117) ); + b059_002_enc7: lv1_enc7_b(59) <= not( lv1_inv_b(59) and lv0_or(119) ); + b060_002_enc7: lv1_enc7_b(60) <= not( lv1_inv_b(60) and lv0_or(121) ); + b061_002_enc7: lv1_enc7_b(61) <= not( lv1_inv_b(61) and lv0_or(123) ); + b062_002_enc7: lv1_enc7_b(62) <= not( lv1_inv_b(62) and lv0_or(125) ); + b063_002_enc7: lv1_enc7_b(63) <= not( lv1_inv_b(63) and lv0_or(127) ); + b064_002_enc7: lv1_enc7_b(64) <= not( lv1_inv_b(64) and lv0_or(129) ); + b065_002_enc7: lv1_enc7_b(65) <= not( lv1_inv_b(65) and lv0_or(131) ); + b066_002_enc7: lv1_enc7_b(66) <= not( lv1_inv_b(66) and lv0_or(133) ); + b067_002_enc7: lv1_enc7_b(67) <= not( lv1_inv_b(67) and lv0_or(135) ); + b068_002_enc7: lv1_enc7_b(68) <= not( lv1_inv_b(68) and lv0_or(137) ); + b069_002_enc7: lv1_enc7_b(69) <= not( lv1_inv_b(69) and lv0_or(139) ); + b070_002_enc7: lv1_enc7_b(70) <= not( lv1_inv_b(70) and lv0_or(141) ); + b071_002_enc7: lv1_enc7_b(71) <= not( lv1_inv_b(71) and lv0_or(143) ); + b072_002_enc7: lv1_enc7_b(72) <= not( lv1_inv_b(72) and lv0_or(145) ); + b073_002_enc7: lv1_enc7_b(73) <= not( lv1_inv_b(73) and lv0_or(147) ); + b074_002_enc7: lv1_enc7_b(74) <= not( lv1_inv_b(74) and lv0_or(149) ); + b075_002_enc7: lv1_enc7_b(75) <= not( lv1_inv_b(75) and lv0_or(151) ); + b076_002_enc7: lv1_enc7_b(76) <= not( lv1_inv_b(76) and lv0_or(153) ); + b077_002_enc7: lv1_enc7_b(77) <= not( lv1_inv_b(77) and lv0_or(155) ); + b078_002_enc7: lv1_enc7_b(78) <= not( lv1_inv_b(78) and lv0_or(157) ); + b079_002_enc7: lv1_enc7_b(79) <= not( lv1_inv_b(79) and lv0_or(159) ); + b080_002_enc7: lv1_enc7_b(80) <= not( lv1_inv_b(80) and lv0_or(161) ); + b081_002_enc7: lv1_enc7_b(81) <= not( lv1_inv_b(81) );--dflt1 + + + ---------------------------------------------------------------------------------- + -- 004 bit group (phase_in=N, phase_out=P, level_in=lv1, level_out=lv2) + ---------------------------------------------------------------------------------- + + b000_004_any: lv2_or(0) <= not( lv1_or_b(0) and lv1_or_b(1) ); + b001_004_any: lv2_or(1) <= not( lv1_or_b(2) and lv1_or_b(3) ); + b002_004_any: lv2_or(2) <= not( lv1_or_b(4) and lv1_or_b(5) ); + b003_004_any: lv2_or(3) <= not( lv1_or_b(6) and lv1_or_b(7) ); + b004_004_any: lv2_or(4) <= not( lv1_or_b(8) and lv1_or_b(9) ); + b005_004_any: lv2_or(5) <= not( lv1_or_b(10) and lv1_or_b(11) ); + b006_004_any: lv2_or(6) <= not( lv1_or_b(12) and lv1_or_b(13) ); + b007_004_any: lv2_or(7) <= not( lv1_or_b(14) and lv1_or_b(15) ); + b008_004_any: lv2_or(8) <= not( lv1_or_b(16) and lv1_or_b(17) ); + b009_004_any: lv2_or(9) <= not( lv1_or_b(18) and lv1_or_b(19) ); + b010_004_any: lv2_or(10) <= not( lv1_or_b(20) and lv1_or_b(21) ); + b011_004_any: lv2_or(11) <= not( lv1_or_b(22) and lv1_or_b(23) ); + b012_004_any: lv2_or(12) <= not( lv1_or_b(24) and lv1_or_b(25) ); + b013_004_any: lv2_or(13) <= not( lv1_or_b(26) and lv1_or_b(27) ); + b014_004_any: lv2_or(14) <= not( lv1_or_b(28) and lv1_or_b(29) ); + b015_004_any: lv2_or(15) <= not( lv1_or_b(30) and lv1_or_b(31) ); + b016_004_any: lv2_or(16) <= not( lv1_or_b(32) and lv1_or_b(33) ); + b017_004_any: lv2_or(17) <= not( lv1_or_b(34) and lv1_or_b(35) ); + b018_004_any: lv2_or(18) <= not( lv1_or_b(36) and lv1_or_b(37) ); + b019_004_any: lv2_or(19) <= not( lv1_or_b(38) and lv1_or_b(39) ); + b020_004_any: lv2_or(20) <= not( lv1_or_b(40) and lv1_or_b(41) ); + b021_004_any: lv2_or(21) <= not( lv1_or_b(42) and lv1_or_b(43) ); + b022_004_any: lv2_or(22) <= not( lv1_or_b(44) and lv1_or_b(45) ); + b023_004_any: lv2_or(23) <= not( lv1_or_b(46) and lv1_or_b(47) ); + b024_004_any: lv2_or(24) <= not( lv1_or_b(48) and lv1_or_b(49) ); + b025_004_any: lv2_or(25) <= not( lv1_or_b(50) and lv1_or_b(51) ); + b026_004_any: lv2_or(26) <= not( lv1_or_b(52) and lv1_or_b(53) ); + b027_004_any: lv2_or(27) <= not( lv1_or_b(54) and lv1_or_b(55) ); + b028_004_any: lv2_or(28) <= not( lv1_or_b(56) and lv1_or_b(57) ); + b029_004_any: lv2_or(29) <= not( lv1_or_b(58) and lv1_or_b(59) ); + b030_004_any: lv2_or(30) <= not( lv1_or_b(60) and lv1_or_b(61) ); + b031_004_any: lv2_or(31) <= not( lv1_or_b(62) and lv1_or_b(63) ); + b032_004_any: lv2_or(32) <= not( lv1_or_b(64) and lv1_or_b(65) ); + b033_004_any: lv2_or(33) <= not( lv1_or_b(66) and lv1_or_b(67) ); + b034_004_any: lv2_or(34) <= not( lv1_or_b(68) and lv1_or_b(69) ); + b035_004_any: lv2_or(35) <= not( lv1_or_b(70) and lv1_or_b(71) ); + b036_004_any: lv2_or(36) <= not( lv1_or_b(72) and lv1_or_b(73) ); + b037_004_any: lv2_or(37) <= not( lv1_or_b(74) and lv1_or_b(75) ); + b038_004_any: lv2_or(38) <= not( lv1_or_b(76) and lv1_or_b(77) ); + b039_004_any: lv2_or(39) <= not( lv1_or_b(78) and lv1_or_b(79) ); + b040_004_any: lv2_or(40) <= not( lv1_or_b(80) and lv1_or_b(81) ); + + b000_004_inv: lv2_inv(0) <= not( lv1_or_b(0) ); + b001_004_inv: lv2_inv(1) <= not( lv1_or_b(2) ); + b002_004_inv: lv2_inv(2) <= not( lv1_or_b(4) ); + b003_004_inv: lv2_inv(3) <= not( lv1_or_b(6) ); + b004_004_inv: lv2_inv(4) <= not( lv1_or_b(8) ); + b005_004_inv: lv2_inv(5) <= not( lv1_or_b(10) ); + b006_004_inv: lv2_inv(6) <= not( lv1_or_b(12) ); + b007_004_inv: lv2_inv(7) <= not( lv1_or_b(14) ); + b008_004_inv: lv2_inv(8) <= not( lv1_or_b(16) ); + b009_004_inv: lv2_inv(9) <= not( lv1_or_b(18) ); + b010_004_inv: lv2_inv(10) <= not( lv1_or_b(20) ); + b011_004_inv: lv2_inv(11) <= not( lv1_or_b(22) ); + b012_004_inv: lv2_inv(12) <= not( lv1_or_b(24) ); + b013_004_inv: lv2_inv(13) <= not( lv1_or_b(26) ); + b014_004_inv: lv2_inv(14) <= not( lv1_or_b(28) ); + b015_004_inv: lv2_inv(15) <= not( lv1_or_b(30) ); + b016_004_inv: lv2_inv(16) <= not( lv1_or_b(32) ); + b017_004_inv: lv2_inv(17) <= not( lv1_or_b(34) ); + b018_004_inv: lv2_inv(18) <= not( lv1_or_b(36) ); + b019_004_inv: lv2_inv(19) <= not( lv1_or_b(38) ); + b020_004_inv: lv2_inv(20) <= not( lv1_or_b(40) ); + b021_004_inv: lv2_inv(21) <= not( lv1_or_b(42) ); + b022_004_inv: lv2_inv(22) <= not( lv1_or_b(44) ); + b023_004_inv: lv2_inv(23) <= not( lv1_or_b(46) ); + b024_004_inv: lv2_inv(24) <= not( lv1_or_b(48) ); + b025_004_inv: lv2_inv(25) <= not( lv1_or_b(50) ); + b026_004_inv: lv2_inv(26) <= not( lv1_or_b(52) ); + b027_004_inv: lv2_inv(27) <= not( lv1_or_b(54) ); + b028_004_inv: lv2_inv(28) <= not( lv1_or_b(56) ); + b029_004_inv: lv2_inv(29) <= not( lv1_or_b(58) ); + b030_004_inv: lv2_inv(30) <= not( lv1_or_b(60) ); + b031_004_inv: lv2_inv(31) <= not( lv1_or_b(62) ); + b032_004_inv: lv2_inv(32) <= not( lv1_or_b(64) ); + b033_004_inv: lv2_inv(33) <= not( lv1_or_b(66) ); + b034_004_inv: lv2_inv(34) <= not( lv1_or_b(68) ); + b035_004_inv: lv2_inv(35) <= not( lv1_or_b(70) ); + b036_004_inv: lv2_inv(36) <= not( lv1_or_b(72) ); + b037_004_inv: lv2_inv(37) <= not( lv1_or_b(74) ); + b038_004_inv: lv2_inv(38) <= not( lv1_or_b(76) ); + b039_004_inv: lv2_inv(39) <= not( lv1_or_b(78) ); + b040_004_inv: lv2_inv(40) <= not( lv1_or_b(80) ); + + b000_004_enc6: lv2_enc6(0) <= not( lv2_inv(0) or lv1_or_b(1) ); + b001_004_enc6: lv2_enc6(1) <= not( lv2_inv(1) or lv1_or_b(3) ); + b002_004_enc6: lv2_enc6(2) <= not( lv2_inv(2) or lv1_or_b(5) ); + b003_004_enc6: lv2_enc6(3) <= not( lv2_inv(3) or lv1_or_b(7) ); + b004_004_enc6: lv2_enc6(4) <= not( lv2_inv(4) or lv1_or_b(9) ); + b005_004_enc6: lv2_enc6(5) <= not( lv2_inv(5) or lv1_or_b(11) ); + b006_004_enc6: lv2_enc6(6) <= not( lv2_inv(6) or lv1_or_b(13) ); + b007_004_enc6: lv2_enc6(7) <= not( lv2_inv(7) or lv1_or_b(15) ); + b008_004_enc6: lv2_enc6(8) <= not( lv2_inv(8) or lv1_or_b(17) ); + b009_004_enc6: lv2_enc6(9) <= not( lv2_inv(9) or lv1_or_b(19) ); + b010_004_enc6: lv2_enc6(10) <= not( lv2_inv(10) or lv1_or_b(21) ); + b011_004_enc6: lv2_enc6(11) <= not( lv2_inv(11) or lv1_or_b(23) ); + b012_004_enc6: lv2_enc6(12) <= not( lv2_inv(12) or lv1_or_b(25) ); + b013_004_enc6: lv2_enc6(13) <= not( lv2_inv(13) or lv1_or_b(27) ); + b014_004_enc6: lv2_enc6(14) <= not( lv2_inv(14) or lv1_or_b(29) ); + b015_004_enc6: lv2_enc6(15) <= not( lv2_inv(15) or lv1_or_b(31) ); + b016_004_enc6: lv2_enc6(16) <= not( lv2_inv(16) or lv1_or_b(33) ); + b017_004_enc6: lv2_enc6(17) <= not( lv2_inv(17) or lv1_or_b(35) ); + b018_004_enc6: lv2_enc6(18) <= not( lv2_inv(18) or lv1_or_b(37) ); + b019_004_enc6: lv2_enc6(19) <= not( lv2_inv(19) or lv1_or_b(39) ); + b020_004_enc6: lv2_enc6(20) <= not( lv2_inv(20) or lv1_or_b(41) ); + b021_004_enc6: lv2_enc6(21) <= not( lv2_inv(21) or lv1_or_b(43) ); + b022_004_enc6: lv2_enc6(22) <= not( lv2_inv(22) or lv1_or_b(45) ); + b023_004_enc6: lv2_enc6(23) <= not( lv2_inv(23) or lv1_or_b(47) ); + b024_004_enc6: lv2_enc6(24) <= not( lv2_inv(24) or lv1_or_b(49) ); + b025_004_enc6: lv2_enc6(25) <= not( lv2_inv(25) or lv1_or_b(51) ); + b026_004_enc6: lv2_enc6(26) <= not( lv2_inv(26) or lv1_or_b(53) ); + b027_004_enc6: lv2_enc6(27) <= not( lv2_inv(27) or lv1_or_b(55) ); + b028_004_enc6: lv2_enc6(28) <= not( lv2_inv(28) or lv1_or_b(57) ); + b029_004_enc6: lv2_enc6(29) <= not( lv2_inv(29) or lv1_or_b(59) ); + b030_004_enc6: lv2_enc6(30) <= not( lv2_inv(30) or lv1_or_b(61) ); + b031_004_enc6: lv2_enc6(31) <= not( lv2_inv(31) or lv1_or_b(63) ); + b032_004_enc6: lv2_enc6(32) <= not( lv2_inv(32) or lv1_or_b(65) ); + b033_004_enc6: lv2_enc6(33) <= not( lv2_inv(33) or lv1_or_b(67) ); + b034_004_enc6: lv2_enc6(34) <= not( lv2_inv(34) or lv1_or_b(69) ); + b035_004_enc6: lv2_enc6(35) <= not( lv2_inv(35) or lv1_or_b(71) ); + b036_004_enc6: lv2_enc6(36) <= not( lv2_inv(36) or lv1_or_b(73) ); + b037_004_enc6: lv2_enc6(37) <= not( lv2_inv(37) or lv1_or_b(75) ); + b038_004_enc6: lv2_enc6(38) <= not( lv2_inv(38) or lv1_or_b(77) ); + b039_004_enc6: lv2_enc6(39) <= not( lv2_inv(39) or lv1_or_b(79) ); + b040_004_enc6: lv2_enc6(40) <= not( lv2_inv(40) );--dflt1 + + b000_004_enc7: lv2_enc7(0) <= not( lv1_enc7_b(0) and (lv1_enc7_b(1) or lv2_inv(0)) ); + b001_004_enc7: lv2_enc7(1) <= not( lv1_enc7_b(2) and (lv1_enc7_b(3) or lv2_inv(1)) ); + b002_004_enc7: lv2_enc7(2) <= not( lv1_enc7_b(4) and (lv1_enc7_b(5) or lv2_inv(2)) ); + b003_004_enc7: lv2_enc7(3) <= not( lv1_enc7_b(6) and (lv1_enc7_b(7) or lv2_inv(3)) ); + b004_004_enc7: lv2_enc7(4) <= not( lv1_enc7_b(8) and (lv1_enc7_b(9) or lv2_inv(4)) ); + b005_004_enc7: lv2_enc7(5) <= not( lv1_enc7_b(10) and (lv1_enc7_b(11) or lv2_inv(5)) ); + b006_004_enc7: lv2_enc7(6) <= not( lv1_enc7_b(12) and (lv1_enc7_b(13) or lv2_inv(6)) ); + b007_004_enc7: lv2_enc7(7) <= not( lv1_enc7_b(14) and (lv1_enc7_b(15) or lv2_inv(7)) ); + b008_004_enc7: lv2_enc7(8) <= not( lv1_enc7_b(16) and (lv1_enc7_b(17) or lv2_inv(8)) ); + b009_004_enc7: lv2_enc7(9) <= not( lv1_enc7_b(18) and (lv1_enc7_b(19) or lv2_inv(9)) ); + b010_004_enc7: lv2_enc7(10) <= not( lv1_enc7_b(20) and (lv1_enc7_b(21) or lv2_inv(10)) ); + b011_004_enc7: lv2_enc7(11) <= not( lv1_enc7_b(22) and (lv1_enc7_b(23) or lv2_inv(11)) ); + b012_004_enc7: lv2_enc7(12) <= not( lv1_enc7_b(24) and (lv1_enc7_b(25) or lv2_inv(12)) ); + b013_004_enc7: lv2_enc7(13) <= not( lv1_enc7_b(26) and (lv1_enc7_b(27) or lv2_inv(13)) ); + b014_004_enc7: lv2_enc7(14) <= not( lv1_enc7_b(28) and (lv1_enc7_b(29) or lv2_inv(14)) ); + b015_004_enc7: lv2_enc7(15) <= not( lv1_enc7_b(30) and (lv1_enc7_b(31) or lv2_inv(15)) ); + b016_004_enc7: lv2_enc7(16) <= not( lv1_enc7_b(32) and (lv1_enc7_b(33) or lv2_inv(16)) ); + b017_004_enc7: lv2_enc7(17) <= not( lv1_enc7_b(34) and (lv1_enc7_b(35) or lv2_inv(17)) ); + b018_004_enc7: lv2_enc7(18) <= not( lv1_enc7_b(36) and (lv1_enc7_b(37) or lv2_inv(18)) ); + b019_004_enc7: lv2_enc7(19) <= not( lv1_enc7_b(38) and (lv1_enc7_b(39) or lv2_inv(19)) ); + b020_004_enc7: lv2_enc7(20) <= not( lv1_enc7_b(40) and (lv1_enc7_b(41) or lv2_inv(20)) ); + b021_004_enc7: lv2_enc7(21) <= not( lv1_enc7_b(42) and (lv1_enc7_b(43) or lv2_inv(21)) ); + b022_004_enc7: lv2_enc7(22) <= not( lv1_enc7_b(44) and (lv1_enc7_b(45) or lv2_inv(22)) ); + b023_004_enc7: lv2_enc7(23) <= not( lv1_enc7_b(46) and (lv1_enc7_b(47) or lv2_inv(23)) ); + b024_004_enc7: lv2_enc7(24) <= not( lv1_enc7_b(48) and (lv1_enc7_b(49) or lv2_inv(24)) ); + b025_004_enc7: lv2_enc7(25) <= not( lv1_enc7_b(50) and (lv1_enc7_b(51) or lv2_inv(25)) ); + b026_004_enc7: lv2_enc7(26) <= not( lv1_enc7_b(52) and (lv1_enc7_b(53) or lv2_inv(26)) ); + b027_004_enc7: lv2_enc7(27) <= not( lv1_enc7_b(54) and (lv1_enc7_b(55) or lv2_inv(27)) ); + b028_004_enc7: lv2_enc7(28) <= not( lv1_enc7_b(56) and (lv1_enc7_b(57) or lv2_inv(28)) ); + b029_004_enc7: lv2_enc7(29) <= not( lv1_enc7_b(58) and (lv1_enc7_b(59) or lv2_inv(29)) ); + b030_004_enc7: lv2_enc7(30) <= not( lv1_enc7_b(60) and (lv1_enc7_b(61) or lv2_inv(30)) ); + b031_004_enc7: lv2_enc7(31) <= not( lv1_enc7_b(62) and (lv1_enc7_b(63) or lv2_inv(31)) ); + b032_004_enc7: lv2_enc7(32) <= not( lv1_enc7_b(64) and (lv1_enc7_b(65) or lv2_inv(32)) ); + b033_004_enc7: lv2_enc7(33) <= not( lv1_enc7_b(66) and (lv1_enc7_b(67) or lv2_inv(33)) ); + b034_004_enc7: lv2_enc7(34) <= not( lv1_enc7_b(68) and (lv1_enc7_b(69) or lv2_inv(34)) ); + b035_004_enc7: lv2_enc7(35) <= not( lv1_enc7_b(70) and (lv1_enc7_b(71) or lv2_inv(35)) ); + b036_004_enc7: lv2_enc7(36) <= not( lv1_enc7_b(72) and (lv1_enc7_b(73) or lv2_inv(36)) ); + b037_004_enc7: lv2_enc7(37) <= not( lv1_enc7_b(74) and (lv1_enc7_b(75) or lv2_inv(37)) ); + b038_004_enc7: lv2_enc7(38) <= not( lv1_enc7_b(76) and (lv1_enc7_b(77) or lv2_inv(38)) ); + b039_004_enc7: lv2_enc7(39) <= not( lv1_enc7_b(78) and (lv1_enc7_b(79) or lv2_inv(39)) ); + b040_004_enc7: lv2_enc7(40) <= not( lv1_enc7_b(80) and (lv1_enc7_b(81) or lv2_inv(40)) ); + + + ---------------------------------------------------------------------------------- + -- 008 bit group (phase_in=P, phase_out=N, level_in=lv2, level_out=lv3) + ---------------------------------------------------------------------------------- + + b000_008_any: lv3_or_b(0) <= not( lv2_or(0) or lv2_or(1) ); + b001_008_any: lv3_or_b(1) <= not( lv2_or(2) or lv2_or(3) ); + b002_008_any: lv3_or_b(2) <= not( lv2_or(4) or lv2_or(5) ); + b003_008_any: lv3_or_b(3) <= not( lv2_or(6) or lv2_or(7) ); + b004_008_any: lv3_or_b(4) <= not( lv2_or(8) or lv2_or(9) ); + b005_008_any: lv3_or_b(5) <= not( lv2_or(10) or lv2_or(11) ); + b006_008_any: lv3_or_b(6) <= not( lv2_or(12) or lv2_or(13) ); + b007_008_any: lv3_or_b(7) <= not( lv2_or(14) or lv2_or(15) ); + b008_008_any: lv3_or_b(8) <= not( lv2_or(16) or lv2_or(17) ); + b009_008_any: lv3_or_b(9) <= not( lv2_or(18) or lv2_or(19) ); + b010_008_any: lv3_or_b(10) <= not( lv2_or(20) or lv2_or(21) ); + b011_008_any: lv3_or_b(11) <= not( lv2_or(22) or lv2_or(23) ); + b012_008_any: lv3_or_b(12) <= not( lv2_or(24) or lv2_or(25) ); + b013_008_any: lv3_or_b(13) <= not( lv2_or(26) or lv2_or(27) ); + b014_008_any: lv3_or_b(14) <= not( lv2_or(28) or lv2_or(29) ); + b015_008_any: lv3_or_b(15) <= not( lv2_or(30) or lv2_or(31) ); + b016_008_any: lv3_or_b(16) <= not( lv2_or(32) or lv2_or(33) ); + b017_008_any: lv3_or_b(17) <= not( lv2_or(34) or lv2_or(35) ); + b018_008_any: lv3_or_b(18) <= not( lv2_or(36) or lv2_or(37) ); + b019_008_any: lv3_or_b(19) <= not( lv2_or(38) or lv2_or(39) ); + b020_008_any: lv3_or_b(20) <= not( lv2_or(40) ); + + b000_008_inv: lv3_inv_b(0) <= not( lv2_or(0) ); + b001_008_inv: lv3_inv_b(1) <= not( lv2_or(2) ); + b002_008_inv: lv3_inv_b(2) <= not( lv2_or(4) ); + b003_008_inv: lv3_inv_b(3) <= not( lv2_or(6) ); + b004_008_inv: lv3_inv_b(4) <= not( lv2_or(8) ); + b005_008_inv: lv3_inv_b(5) <= not( lv2_or(10) ); + b006_008_inv: lv3_inv_b(6) <= not( lv2_or(12) ); + b007_008_inv: lv3_inv_b(7) <= not( lv2_or(14) ); + b008_008_inv: lv3_inv_b(8) <= not( lv2_or(16) ); + b009_008_inv: lv3_inv_b(9) <= not( lv2_or(18) ); + b010_008_inv: lv3_inv_b(10) <= not( lv2_or(20) ); + b011_008_inv: lv3_inv_b(11) <= not( lv2_or(22) ); + b012_008_inv: lv3_inv_b(12) <= not( lv2_or(24) ); + b013_008_inv: lv3_inv_b(13) <= not( lv2_or(26) ); + b014_008_inv: lv3_inv_b(14) <= not( lv2_or(28) ); + b015_008_inv: lv3_inv_b(15) <= not( lv2_or(30) ); + b016_008_inv: lv3_inv_b(16) <= not( lv2_or(32) ); + b017_008_inv: lv3_inv_b(17) <= not( lv2_or(34) ); + b018_008_inv: lv3_inv_b(18) <= not( lv2_or(36) ); + b019_008_inv: lv3_inv_b(19) <= not( lv2_or(38) ); + b020_008_inv: lv3_inv_b(20) <= not( lv2_or(40) ); + + b000_008_enc5: lv3_enc5_b(0) <= not( lv3_inv_b(0) and lv2_or(1) ); + b001_008_enc5: lv3_enc5_b(1) <= not( lv3_inv_b(1) and lv2_or(3) ); + b002_008_enc5: lv3_enc5_b(2) <= not( lv3_inv_b(2) and lv2_or(5) ); + b003_008_enc5: lv3_enc5_b(3) <= not( lv3_inv_b(3) and lv2_or(7) ); + b004_008_enc5: lv3_enc5_b(4) <= not( lv3_inv_b(4) and lv2_or(9) ); + b005_008_enc5: lv3_enc5_b(5) <= not( lv3_inv_b(5) and lv2_or(11) ); + b006_008_enc5: lv3_enc5_b(6) <= not( lv3_inv_b(6) and lv2_or(13) ); + b007_008_enc5: lv3_enc5_b(7) <= not( lv3_inv_b(7) and lv2_or(15) ); + b008_008_enc5: lv3_enc5_b(8) <= not( lv3_inv_b(8) and lv2_or(17) ); + b009_008_enc5: lv3_enc5_b(9) <= not( lv3_inv_b(9) and lv2_or(19) ); + b010_008_enc5: lv3_enc5_b(10) <= not( lv3_inv_b(10) and lv2_or(21) ); + b011_008_enc5: lv3_enc5_b(11) <= not( lv3_inv_b(11) and lv2_or(23) ); + b012_008_enc5: lv3_enc5_b(12) <= not( lv3_inv_b(12) and lv2_or(25) ); + b013_008_enc5: lv3_enc5_b(13) <= not( lv3_inv_b(13) and lv2_or(27) ); + b014_008_enc5: lv3_enc5_b(14) <= not( lv3_inv_b(14) and lv2_or(29) ); + b015_008_enc5: lv3_enc5_b(15) <= not( lv3_inv_b(15) and lv2_or(31) ); + b016_008_enc5: lv3_enc5_b(16) <= not( lv3_inv_b(16) and lv2_or(33) ); + b017_008_enc5: lv3_enc5_b(17) <= not( lv3_inv_b(17) and lv2_or(35) ); + b018_008_enc5: lv3_enc5_b(18) <= not( lv3_inv_b(18) and lv2_or(37) ); + b019_008_enc5: lv3_enc5_b(19) <= not( lv3_inv_b(19) and lv2_or(39) ); + lv3_enc5_b(20) <= tiup ;--dflt0 + + b000_008_enc6: lv3_enc6_b(0) <= not( lv2_enc6(0) or (lv2_enc6(1) and lv3_inv_b(0)) ); + b001_008_enc6: lv3_enc6_b(1) <= not( lv2_enc6(2) or (lv2_enc6(3) and lv3_inv_b(1)) ); + b002_008_enc6: lv3_enc6_b(2) <= not( lv2_enc6(4) or (lv2_enc6(5) and lv3_inv_b(2)) ); + b003_008_enc6: lv3_enc6_b(3) <= not( lv2_enc6(6) or (lv2_enc6(7) and lv3_inv_b(3)) ); + b004_008_enc6: lv3_enc6_b(4) <= not( lv2_enc6(8) or (lv2_enc6(9) and lv3_inv_b(4)) ); + b005_008_enc6: lv3_enc6_b(5) <= not( lv2_enc6(10) or (lv2_enc6(11) and lv3_inv_b(5)) ); + b006_008_enc6: lv3_enc6_b(6) <= not( lv2_enc6(12) or (lv2_enc6(13) and lv3_inv_b(6)) ); + b007_008_enc6: lv3_enc6_b(7) <= not( lv2_enc6(14) or (lv2_enc6(15) and lv3_inv_b(7)) ); + b008_008_enc6: lv3_enc6_b(8) <= not( lv2_enc6(16) or (lv2_enc6(17) and lv3_inv_b(8)) ); + b009_008_enc6: lv3_enc6_b(9) <= not( lv2_enc6(18) or (lv2_enc6(19) and lv3_inv_b(9)) ); + b010_008_enc6: lv3_enc6_b(10) <= not( lv2_enc6(20) or (lv2_enc6(21) and lv3_inv_b(10)) ); + b011_008_enc6: lv3_enc6_b(11) <= not( lv2_enc6(22) or (lv2_enc6(23) and lv3_inv_b(11)) ); + b012_008_enc6: lv3_enc6_b(12) <= not( lv2_enc6(24) or (lv2_enc6(25) and lv3_inv_b(12)) ); + b013_008_enc6: lv3_enc6_b(13) <= not( lv2_enc6(26) or (lv2_enc6(27) and lv3_inv_b(13)) ); + b014_008_enc6: lv3_enc6_b(14) <= not( lv2_enc6(28) or (lv2_enc6(29) and lv3_inv_b(14)) ); + b015_008_enc6: lv3_enc6_b(15) <= not( lv2_enc6(30) or (lv2_enc6(31) and lv3_inv_b(15)) ); + b016_008_enc6: lv3_enc6_b(16) <= not( lv2_enc6(32) or (lv2_enc6(33) and lv3_inv_b(16)) ); + b017_008_enc6: lv3_enc6_b(17) <= not( lv2_enc6(34) or (lv2_enc6(35) and lv3_inv_b(17)) ); + b018_008_enc6: lv3_enc6_b(18) <= not( lv2_enc6(36) or (lv2_enc6(37) and lv3_inv_b(18)) ); + b019_008_enc6: lv3_enc6_b(19) <= not( lv2_enc6(38) or (lv2_enc6(39) and lv3_inv_b(19)) ); + b020_008_enc6: lv3_enc6_b(20) <= not( lv2_enc6(40) or lv3_inv_b(20) );--dflt1 + + b000_008_enc7: lv3_enc7_b(0) <= not( lv2_enc7(0) or (lv2_enc7(1) and lv3_inv_b(0)) ); + b001_008_enc7: lv3_enc7_b(1) <= not( lv2_enc7(2) or (lv2_enc7(3) and lv3_inv_b(1)) ); + b002_008_enc7: lv3_enc7_b(2) <= not( lv2_enc7(4) or (lv2_enc7(5) and lv3_inv_b(2)) ); + b003_008_enc7: lv3_enc7_b(3) <= not( lv2_enc7(6) or (lv2_enc7(7) and lv3_inv_b(3)) ); + b004_008_enc7: lv3_enc7_b(4) <= not( lv2_enc7(8) or (lv2_enc7(9) and lv3_inv_b(4)) ); + b005_008_enc7: lv3_enc7_b(5) <= not( lv2_enc7(10) or (lv2_enc7(11) and lv3_inv_b(5)) ); + b006_008_enc7: lv3_enc7_b(6) <= not( lv2_enc7(12) or (lv2_enc7(13) and lv3_inv_b(6)) ); + b007_008_enc7: lv3_enc7_b(7) <= not( lv2_enc7(14) or (lv2_enc7(15) and lv3_inv_b(7)) ); + b008_008_enc7: lv3_enc7_b(8) <= not( lv2_enc7(16) or (lv2_enc7(17) and lv3_inv_b(8)) ); + b009_008_enc7: lv3_enc7_b(9) <= not( lv2_enc7(18) or (lv2_enc7(19) and lv3_inv_b(9)) ); + b010_008_enc7: lv3_enc7_b(10) <= not( lv2_enc7(20) or (lv2_enc7(21) and lv3_inv_b(10)) ); + b011_008_enc7: lv3_enc7_b(11) <= not( lv2_enc7(22) or (lv2_enc7(23) and lv3_inv_b(11)) ); + b012_008_enc7: lv3_enc7_b(12) <= not( lv2_enc7(24) or (lv2_enc7(25) and lv3_inv_b(12)) ); + b013_008_enc7: lv3_enc7_b(13) <= not( lv2_enc7(26) or (lv2_enc7(27) and lv3_inv_b(13)) ); + b014_008_enc7: lv3_enc7_b(14) <= not( lv2_enc7(28) or (lv2_enc7(29) and lv3_inv_b(14)) ); + b015_008_enc7: lv3_enc7_b(15) <= not( lv2_enc7(30) or (lv2_enc7(31) and lv3_inv_b(15)) ); + b016_008_enc7: lv3_enc7_b(16) <= not( lv2_enc7(32) or (lv2_enc7(33) and lv3_inv_b(16)) ); + b017_008_enc7: lv3_enc7_b(17) <= not( lv2_enc7(34) or (lv2_enc7(35) and lv3_inv_b(17)) ); + b018_008_enc7: lv3_enc7_b(18) <= not( lv2_enc7(36) or (lv2_enc7(37) and lv3_inv_b(18)) ); + b019_008_enc7: lv3_enc7_b(19) <= not( lv2_enc7(38) or (lv2_enc7(39) and lv3_inv_b(19)) ); + b020_008_enc7: lv3_enc7_b(20) <= not( lv2_enc7(40) or lv3_inv_b(20) );--dflt1 + + + ---------------------------------------------------------------------------------- + -- 016 bit group (phase_in=N, phase_out=P, level_in=lv3, level_out=lv4) + ---------------------------------------------------------------------------------- + + b000_016_any: lv4_or(0) <= not( lv3_or_b(0) and lv3_or_b(1) ); + b001_016_any: lv4_or(1) <= not( lv3_or_b(2) and lv3_or_b(3) ); + b002_016_any: lv4_or(2) <= not( lv3_or_b(4) and lv3_or_b(5) ); + b003_016_any: lv4_or(3) <= not( lv3_or_b(6) and lv3_or_b(7) ); + b004_016_any: lv4_or(4) <= not( lv3_or_b(8) and lv3_or_b(9) ); + b005_016_any: lv4_or(5) <= not( lv3_or_b(10) and lv3_or_b(11) ); + b006_016_any: lv4_or(6) <= not( lv3_or_b(12) and lv3_or_b(13) ); + b007_016_any: lv4_or(7) <= not( lv3_or_b(14) and lv3_or_b(15) ); + b008_016_any: lv4_or(8) <= not( lv3_or_b(16) and lv3_or_b(17) ); + b009_016_any: lv4_or(9) <= not( lv3_or_b(18) and lv3_or_b(19) ); + b010_016_any: lv4_or(10) <= not( lv3_or_b(20) ); + + b000_016_inv: lv4_inv(0) <= not( lv3_or_b(0) ); + b001_016_inv: lv4_inv(1) <= not( lv3_or_b(2) ); + b002_016_inv: lv4_inv(2) <= not( lv3_or_b(4) ); + b003_016_inv: lv4_inv(3) <= not( lv3_or_b(6) ); + b004_016_inv: lv4_inv(4) <= not( lv3_or_b(8) ); + b005_016_inv: lv4_inv(5) <= not( lv3_or_b(10) ); + b006_016_inv: lv4_inv(6) <= not( lv3_or_b(12) ); + b007_016_inv: lv4_inv(7) <= not( lv3_or_b(14) ); + b008_016_inv: lv4_inv(8) <= not( lv3_or_b(16) ); + b009_016_inv: lv4_inv(9) <= not( lv3_or_b(18) ); + b010_016_inv: lv4_inv(10) <= not( lv3_or_b(20) ); + + b000_016_enc4: lv4_enc4(0) <= not( lv4_inv(0) or lv3_or_b(1) ); + b001_016_enc4: lv4_enc4(1) <= not( lv4_inv(1) or lv3_or_b(3) ); + b002_016_enc4: lv4_enc4(2) <= not( lv4_inv(2) or lv3_or_b(5) ); + b003_016_enc4: lv4_enc4(3) <= not( lv4_inv(3) or lv3_or_b(7) ); + b004_016_enc4: lv4_enc4(4) <= not( lv4_inv(4) or lv3_or_b(9) ); + b005_016_enc4: lv4_enc4(5) <= not( lv4_inv(5) or lv3_or_b(11) ); + b006_016_enc4: lv4_enc4(6) <= not( lv4_inv(6) or lv3_or_b(13) ); + b007_016_enc4: lv4_enc4(7) <= not( lv4_inv(7) or lv3_or_b(15) ); + b008_016_enc4: lv4_enc4(8) <= not( lv4_inv(8) or lv3_or_b(17) ); + b009_016_enc4: lv4_enc4(9) <= not( lv4_inv(9) or lv3_or_b(19) ); + lv4_enc4(10) <= tidn ;--dflt0 + + b000_016_enc5: lv4_enc5(0) <= not( lv3_enc5_b(0) and (lv3_enc5_b(1) or lv4_inv(0)) ); + b001_016_enc5: lv4_enc5(1) <= not( lv3_enc5_b(2) and (lv3_enc5_b(3) or lv4_inv(1)) ); + b002_016_enc5: lv4_enc5(2) <= not( lv3_enc5_b(4) and (lv3_enc5_b(5) or lv4_inv(2)) ); + b003_016_enc5: lv4_enc5(3) <= not( lv3_enc5_b(6) and (lv3_enc5_b(7) or lv4_inv(3)) ); + b004_016_enc5: lv4_enc5(4) <= not( lv3_enc5_b(8) and (lv3_enc5_b(9) or lv4_inv(4)) ); + b005_016_enc5: lv4_enc5(5) <= not( lv3_enc5_b(10) and (lv3_enc5_b(11) or lv4_inv(5)) ); + b006_016_enc5: lv4_enc5(6) <= not( lv3_enc5_b(12) and (lv3_enc5_b(13) or lv4_inv(6)) ); + b007_016_enc5: lv4_enc5(7) <= not( lv3_enc5_b(14) and (lv3_enc5_b(15) or lv4_inv(7)) ); + b008_016_enc5: lv4_enc5(8) <= not( lv3_enc5_b(16) and (lv3_enc5_b(17) or lv4_inv(8)) ); + b009_016_enc5: lv4_enc5(9) <= not( lv3_enc5_b(18) and (lv3_enc5_b(19) or lv4_inv(9)) ); + b010_016_enc5: lv4_enc5(10) <= not( lv3_enc5_b(20) );--dflt0 pass + + + b000_016_enc6: lv4_enc6(0) <= not( lv3_enc6_b(0) and (lv3_enc6_b(1) or lv4_inv(0)) ); + b001_016_enc6: lv4_enc6(1) <= not( lv3_enc6_b(2) and (lv3_enc6_b(3) or lv4_inv(1)) ); + b002_016_enc6: lv4_enc6(2) <= not( lv3_enc6_b(4) and (lv3_enc6_b(5) or lv4_inv(2)) ); + b003_016_enc6: lv4_enc6(3) <= not( lv3_enc6_b(6) and (lv3_enc6_b(7) or lv4_inv(3)) ); + b004_016_enc6: lv4_enc6(4) <= not( lv3_enc6_b(8) and (lv3_enc6_b(9) or lv4_inv(4)) ); + b005_016_enc6: lv4_enc6(5) <= not( lv3_enc6_b(10) and (lv3_enc6_b(11) or lv4_inv(5)) ); + b006_016_enc6: lv4_enc6(6) <= not( lv3_enc6_b(12) and (lv3_enc6_b(13) or lv4_inv(6)) ); + b007_016_enc6: lv4_enc6(7) <= not( lv3_enc6_b(14) and (lv3_enc6_b(15) or lv4_inv(7)) ); + b008_016_enc6: lv4_enc6(8) <= not( lv3_enc6_b(16) and (lv3_enc6_b(17) or lv4_inv(8)) ); + b009_016_enc6: lv4_enc6(9) <= not( lv3_enc6_b(18) and (lv3_enc6_b(19) or lv4_inv(9)) ); + b010_016_enc6: lv4_enc6(10) <= not( lv3_enc6_b(20) and lv4_inv(10) );--dflt1 + + b000_016_enc7: lv4_enc7(0) <= not( lv3_enc7_b(0) and (lv3_enc7_b(1) or lv4_inv(0)) ); + b001_016_enc7: lv4_enc7(1) <= not( lv3_enc7_b(2) and (lv3_enc7_b(3) or lv4_inv(1)) ); + b002_016_enc7: lv4_enc7(2) <= not( lv3_enc7_b(4) and (lv3_enc7_b(5) or lv4_inv(2)) ); + b003_016_enc7: lv4_enc7(3) <= not( lv3_enc7_b(6) and (lv3_enc7_b(7) or lv4_inv(3)) ); + b004_016_enc7: lv4_enc7(4) <= not( lv3_enc7_b(8) and (lv3_enc7_b(9) or lv4_inv(4)) ); + b005_016_enc7: lv4_enc7(5) <= not( lv3_enc7_b(10) and (lv3_enc7_b(11) or lv4_inv(5)) ); + b006_016_enc7: lv4_enc7(6) <= not( lv3_enc7_b(12) and (lv3_enc7_b(13) or lv4_inv(6)) ); + b007_016_enc7: lv4_enc7(7) <= not( lv3_enc7_b(14) and (lv3_enc7_b(15) or lv4_inv(7)) ); + b008_016_enc7: lv4_enc7(8) <= not( lv3_enc7_b(16) and (lv3_enc7_b(17) or lv4_inv(8)) ); + b009_016_enc7: lv4_enc7(9) <= not( lv3_enc7_b(18) and (lv3_enc7_b(19) or lv4_inv(9)) ); + b010_016_enc7: lv4_enc7(10) <= not( lv3_enc7_b(20) and lv4_inv(10) );--dflt1 + + + r000_004_or: lv4_or_b(0) <= not( lv4_or(0) );--repower,long wire + r001_004_or: lv4_or_b(1) <= not( lv4_or(1) );--repower,long wire + r002_004_or: lv4_or_b(2) <= not( lv4_or(2) );--repower,long wire + r003_004_or: lv4_or_b(3) <= not( lv4_or(3) );--repower,long wire + r004_004_or: lv4_or_b(4) <= not( lv4_or(4) );--repower,long wire + r005_004_or: lv4_or_b(5) <= not( lv4_or(5) );--repower,long wire + r006_004_or: lv4_or_b(6) <= not( lv4_or(6) );--repower,long wire + r007_004_or: lv4_or_b(7) <= not( lv4_or(7) );--repower,long wire + r008_004_or: lv4_or_b(8) <= not( lv4_or(8) );--repower,long wire + r009_004_or: lv4_or_b(9) <= not( lv4_or(9) );--repower,long wire + r010_004_or: lv4_or_b(10) <= not( lv4_or(10) );--repower,long wire + r000_004_enc4: lv4_enc4_b(0) <= not( lv4_enc4(0) );--repower,long wire + r001_004_enc4: lv4_enc4_b(1) <= not( lv4_enc4(1) );--repower,long wire + r002_004_enc4: lv4_enc4_b(2) <= not( lv4_enc4(2) );--repower,long wire + r003_004_enc4: lv4_enc4_b(3) <= not( lv4_enc4(3) );--repower,long wire + r004_004_enc4: lv4_enc4_b(4) <= not( lv4_enc4(4) );--repower,long wire + r005_004_enc4: lv4_enc4_b(5) <= not( lv4_enc4(5) );--repower,long wire + r006_004_enc4: lv4_enc4_b(6) <= not( lv4_enc4(6) );--repower,long wire + r007_004_enc4: lv4_enc4_b(7) <= not( lv4_enc4(7) );--repower,long wire + r008_004_enc4: lv4_enc4_b(8) <= not( lv4_enc4(8) );--repower,long wire + r009_004_enc4: lv4_enc4_b(9) <= not( lv4_enc4(9) );--repower,long wire + r010_004_enc4: lv4_enc4_b(10) <= not( lv4_enc4(10) );--repower,long wire + r000_004_enc5: lv4_enc5_b(0) <= not( lv4_enc5(0) );--repower,long wire + r001_004_enc5: lv4_enc5_b(1) <= not( lv4_enc5(1) );--repower,long wire + r002_004_enc5: lv4_enc5_b(2) <= not( lv4_enc5(2) );--repower,long wire + r003_004_enc5: lv4_enc5_b(3) <= not( lv4_enc5(3) );--repower,long wire + r004_004_enc5: lv4_enc5_b(4) <= not( lv4_enc5(4) );--repower,long wire + r005_004_enc5: lv4_enc5_b(5) <= not( lv4_enc5(5) );--repower,long wire + r006_004_enc5: lv4_enc5_b(6) <= not( lv4_enc5(6) );--repower,long wire + r007_004_enc5: lv4_enc5_b(7) <= not( lv4_enc5(7) );--repower,long wire + r008_004_enc5: lv4_enc5_b(8) <= not( lv4_enc5(8) );--repower,long wire + r009_004_enc5: lv4_enc5_b(9) <= not( lv4_enc5(9) );--repower,long wire + r010_004_enc5: lv4_enc5_b(10) <= not( lv4_enc5(10) );--repower,long wire + r000_004_enc6: lv4_enc6_b(0) <= not( lv4_enc6(0) );--repower,long wire + r001_004_enc6: lv4_enc6_b(1) <= not( lv4_enc6(1) );--repower,long wire + r002_004_enc6: lv4_enc6_b(2) <= not( lv4_enc6(2) );--repower,long wire + r003_004_enc6: lv4_enc6_b(3) <= not( lv4_enc6(3) );--repower,long wire + r004_004_enc6: lv4_enc6_b(4) <= not( lv4_enc6(4) );--repower,long wire + r005_004_enc6: lv4_enc6_b(5) <= not( lv4_enc6(5) );--repower,long wire + r006_004_enc6: lv4_enc6_b(6) <= not( lv4_enc6(6) );--repower,long wire + r007_004_enc6: lv4_enc6_b(7) <= not( lv4_enc6(7) );--repower,long wire + r008_004_enc6: lv4_enc6_b(8) <= not( lv4_enc6(8) );--repower,long wire + r009_004_enc6: lv4_enc6_b(9) <= not( lv4_enc6(9) );--repower,long wire + r010_004_enc6: lv4_enc6_b(10) <= not( lv4_enc6(10) );--repower,long wire + r000_004_enc7: lv4_enc7_b(0) <= not( lv4_enc7(0) );--repower,long wire + r001_004_enc7: lv4_enc7_b(1) <= not( lv4_enc7(1) );--repower,long wire + r002_004_enc7: lv4_enc7_b(2) <= not( lv4_enc7(2) );--repower,long wire + r003_004_enc7: lv4_enc7_b(3) <= not( lv4_enc7(3) );--repower,long wire + r004_004_enc7: lv4_enc7_b(4) <= not( lv4_enc7(4) );--repower,long wire + r005_004_enc7: lv4_enc7_b(5) <= not( lv4_enc7(5) );--repower,long wire + r006_004_enc7: lv4_enc7_b(6) <= not( lv4_enc7(6) );--repower,long wire + r007_004_enc7: lv4_enc7_b(7) <= not( lv4_enc7(7) );--repower,long wire + r008_004_enc7: lv4_enc7_b(8) <= not( lv4_enc7(8) );--repower,long wire + r009_004_enc7: lv4_enc7_b(9) <= not( lv4_enc7(9) );--repower,long wire + r010_004_enc7: lv4_enc7_b(10) <= not( lv4_enc7(10) );--repower,long wire + + + ---------------------------------------------------------------------------------- + -- 032 bit group (phase_in=N, phase_out=P, level_in=lv4, level_out=lv5) + ---------------------------------------------------------------------------------- + + b000_032_any: lv5_or(0) <= not( lv4_or_b(0) and lv4_or_b(1) ); + b001_032_any: lv5_or(1) <= not( lv4_or_b(2) and lv4_or_b(3) ); + b002_032_any: lv5_or(2) <= not( lv4_or_b(4) and lv4_or_b(5) ); + b003_032_any: lv5_or(3) <= not( lv4_or_b(6) and lv4_or_b(7) ); + b004_032_any: lv5_or(4) <= not( lv4_or_b(8) and lv4_or_b(9) ); + b005_032_any: lv5_or(5) <= not( lv4_or_b(10) ); + + b000_032_inv: lv5_inv(0) <= not( lv4_or_b(0) ); + b001_032_inv: lv5_inv(1) <= not( lv4_or_b(2) ); + b002_032_inv: lv5_inv(2) <= not( lv4_or_b(4) ); + b003_032_inv: lv5_inv(3) <= not( lv4_or_b(6) ); + b004_032_inv: lv5_inv(4) <= not( lv4_or_b(8) ); + b005_032_inv: lv5_inv(5) <= not( lv4_or_b(10) ); + + b000_032_enc3: lv5_enc3(0) <= not( lv5_inv(0) or lv4_or_b(1) ); + b001_032_enc3: lv5_enc3(1) <= not( lv5_inv(1) or lv4_or_b(3) ); + b002_032_enc3: lv5_enc3(2) <= not( lv5_inv(2) or lv4_or_b(5) ); + b003_032_enc3: lv5_enc3(3) <= not( lv5_inv(3) or lv4_or_b(7) ); + b004_032_enc3: lv5_enc3(4) <= not( lv5_inv(4) or lv4_or_b(9) ); + lv5_enc3(5) <= tidn ;--dflt0 + + b000_032_enc4: lv5_enc4(0) <= not( lv4_enc4_b(0) and (lv4_enc4_b(1) or lv5_inv(0)) ); + b001_032_enc4: lv5_enc4(1) <= not( lv4_enc4_b(2) and (lv4_enc4_b(3) or lv5_inv(1)) ); + b002_032_enc4: lv5_enc4(2) <= not( lv4_enc4_b(4) and (lv4_enc4_b(5) or lv5_inv(2)) ); + b003_032_enc4: lv5_enc4(3) <= not( lv4_enc4_b(6) and (lv4_enc4_b(7) or lv5_inv(3)) ); + b004_032_enc4: lv5_enc4(4) <= not( lv4_enc4_b(8) and (lv4_enc4_b(9) or lv5_inv(4)) ); + b005_032_enc4: lv5_enc4(5) <= not( lv4_enc4_b(10) );--dflt0 pass + + b000_032_enc5: lv5_enc5(0) <= not( lv4_enc5_b(0) and (lv4_enc5_b(1) or lv5_inv(0)) ); + b001_032_enc5: lv5_enc5(1) <= not( lv4_enc5_b(2) and (lv4_enc5_b(3) or lv5_inv(1)) ); + b002_032_enc5: lv5_enc5(2) <= not( lv4_enc5_b(4) and (lv4_enc5_b(5) or lv5_inv(2)) ); + b003_032_enc5: lv5_enc5(3) <= not( lv4_enc5_b(6) and (lv4_enc5_b(7) or lv5_inv(3)) ); + b004_032_enc5: lv5_enc5(4) <= not( lv4_enc5_b(8) and (lv4_enc5_b(9) or lv5_inv(4)) ); + b005_032_enc5: lv5_enc5(5) <= not( lv4_enc5_b(10) );--dflt0 pass + + b000_032_enc6: lv5_enc6(0) <= not( lv4_enc6_b(0) and (lv4_enc6_b(1) or lv5_inv(0)) ); + b001_032_enc6: lv5_enc6(1) <= not( lv4_enc6_b(2) and (lv4_enc6_b(3) or lv5_inv(1)) ); + b002_032_enc6: lv5_enc6(2) <= not( lv4_enc6_b(4) and (lv4_enc6_b(5) or lv5_inv(2)) ); + b003_032_enc6: lv5_enc6(3) <= not( lv4_enc6_b(6) and (lv4_enc6_b(7) or lv5_inv(3)) ); + b004_032_enc6: lv5_enc6(4) <= not( lv4_enc6_b(8) and (lv4_enc6_b(9) or lv5_inv(4)) ); + b005_032_enc6: lv5_enc6(5) <= not( lv4_enc6_b(10) and lv5_inv(5) );--dflt1 + + b000_032_enc7: lv5_enc7(0) <= not( lv4_enc7_b(0) and (lv4_enc7_b(1) or lv5_inv(0)) ); + b001_032_enc7: lv5_enc7(1) <= not( lv4_enc7_b(2) and (lv4_enc7_b(3) or lv5_inv(1)) ); + b002_032_enc7: lv5_enc7(2) <= not( lv4_enc7_b(4) and (lv4_enc7_b(5) or lv5_inv(2)) ); + b003_032_enc7: lv5_enc7(3) <= not( lv4_enc7_b(6) and (lv4_enc7_b(7) or lv5_inv(3)) ); + b004_032_enc7: lv5_enc7(4) <= not( lv4_enc7_b(8) and (lv4_enc7_b(9) or lv5_inv(4)) ); + b005_032_enc7: lv5_enc7(5) <= not( lv4_enc7_b(10) and lv5_inv(5) );--dflt1 + + + ---------------------------------------------------------------------------------- + -- 064 bit group (phase_in=P, phase_out=N, level_in=lv5, level_out=lv6) + ---------------------------------------------------------------------------------- + + lv6_or_0 <= not lv6_or_b(0) ; + lv6_or_1 <= not lv6_or_b(1) ; + + + b000_064_any: lv6_or_b(0) <= not( lv5_or(0) or lv5_or(1) ); + b001_064_any: lv6_or_b(1) <= not( lv5_or(2) or lv5_or(3) ); + b002_064_any: lv6_or_b(2) <= not( lv5_or(4) or lv5_or(5) ); + + b000_064_inv: lv6_inv_b(0) <= not( lv5_or(0) ); + b001_064_inv: lv6_inv_b(1) <= not( lv5_or(2) ); + b002_064_inv: lv6_inv_b(2) <= not( lv5_or(4) ); + + b000_064_enc2: lv6_enc2_b(0) <= not( lv6_inv_b(0) and lv5_or(1) ); + b001_064_enc2: lv6_enc2_b(1) <= not( lv6_inv_b(1) and lv5_or(3) ); + b002_064_enc2: lv6_enc2_b(2) <= not( lv6_inv_b(2) );--dflt1 + + b000_064_enc3: lv6_enc3_b(0) <= not( lv5_enc3(0) or (lv5_enc3(1) and lv6_inv_b(0)) ); + b001_064_enc3: lv6_enc3_b(1) <= not( lv5_enc3(2) or (lv5_enc3(3) and lv6_inv_b(1)) ); + b002_064_enc3: lv6_enc3_b(2) <= not( lv5_enc3(4) or (lv5_enc3(5) and lv6_inv_b(2)) ); + + b000_064_enc4: lv6_enc4_b(0) <= not( lv5_enc4(0) or (lv5_enc4(1) and lv6_inv_b(0)) ); + b001_064_enc4: lv6_enc4_b(1) <= not( lv5_enc4(2) or (lv5_enc4(3) and lv6_inv_b(1)) ); + b002_064_enc4: lv6_enc4_b(2) <= not( lv5_enc4(4) or (lv5_enc4(5) and lv6_inv_b(2)) ); + + b000_064_enc5: lv6_enc5_b(0) <= not( lv5_enc5(0) or (lv5_enc5(1) and lv6_inv_b(0)) ); + b001_064_enc5: lv6_enc5_b(1) <= not( lv5_enc5(2) or (lv5_enc5(3) and lv6_inv_b(1)) ); + b002_064_enc5: lv6_enc5_b(2) <= not( lv5_enc5(4) or (lv5_enc5(5) and lv6_inv_b(2)) ); + + b000_064_enc6: lv6_enc6_b(0) <= not( lv5_enc6(0) or (lv5_enc6(1) and lv6_inv_b(0)) ); + b001_064_enc6: lv6_enc6_b(1) <= not( lv5_enc6(2) or (lv5_enc6(3) and lv6_inv_b(1)) ); + b002_064_enc6: lv6_enc6_b(2) <= not( lv5_enc6(4) or (lv5_enc6(5) and lv6_inv_b(2)) ); + + b000_064_enc7: lv6_enc7_b(0) <= not( lv5_enc7(0) or (lv5_enc7(1) and lv6_inv_b(0)) ); + b001_064_enc7: lv6_enc7_b(1) <= not( lv5_enc7(2) or (lv5_enc7(3) and lv6_inv_b(1)) ); + b002_064_enc7: lv6_enc7_b(2) <= not( lv5_enc7(4) or (lv5_enc7(5) and lv6_inv_b(2)) ); + + + ---------------------------------------------------------------------------------- + -- 128 bit group (phase_in=N, phase_out=P, level_in=lv6, level_out=lv7) + ---------------------------------------------------------------------------------- + + b000_128_any: lv7_or(0) <= not( lv6_or_b(0) and lv6_or_b(1) ); + b001_128_any: lv7_or(1) <= not( lv6_or_b(2) ); + + b000_128_inv: lv7_inv(0) <= not( lv6_or_b(0) ); + b001_128_inv: lv7_inv(1) <= not( lv6_or_b(2) ); + + b000_128_enc1: lv7_enc1(0) <= not( lv7_inv(0) or lv6_or_b(1) ); + lv7_enc1(1) <= tidn ;--dflt0 + + b000_128_enc2: lv7_enc2(0) <= not( lv6_enc2_b(0) and (lv6_enc2_b(1) or lv7_inv(0)) ); + b001_128_enc2: lv7_enc2(1) <= not( lv6_enc2_b(2) and lv7_inv(1) );--dflt1 + + b000_128_enc3: lv7_enc3(0) <= not( lv6_enc3_b(0) and (lv6_enc3_b(1) or lv7_inv(0)) ); + b001_128_enc3: lv7_enc3(1) <= not( lv6_enc3_b(2) );--dflt0 pass + + b000_128_enc4: lv7_enc4(0) <= not( lv6_enc4_b(0) and (lv6_enc4_b(1) or lv7_inv(0)) ); + b001_128_enc4: lv7_enc4(1) <= not( lv6_enc4_b(2) );--dflt0 pass + + b000_128_enc5: lv7_enc5(0) <= not( lv6_enc5_b(0) and (lv6_enc5_b(1) or lv7_inv(0)) ); + b001_128_enc5: lv7_enc5(1) <= not( lv6_enc5_b(2) );--dflt0 pass + + b000_128_enc6: lv7_enc6(0) <= not( lv6_enc6_b(0) and (lv6_enc6_b(1) or lv7_inv(0)) ); + b001_128_enc6: lv7_enc6(1) <= not( lv6_enc6_b(2) and lv7_inv(1) );--dflt1 + + b000_128_enc7: lv7_enc7(0) <= not( lv6_enc7_b(0) and (lv6_enc7_b(1) or lv7_inv(0)) ); + b001_128_enc7: lv7_enc7(1) <= not( lv6_enc7_b(2) and lv7_inv(1) );--dflt1 + + + ---------------------------------------------------------------------------------- + -- 256 bit group (phase_in=P, phase_out=N, level_in=lv7, level_out=lv8) + ---------------------------------------------------------------------------------- + + b000_256_any: lv8_or_b(0) <= not( lv7_or(0) or lv7_or(1) ); + + b000_256_inv: lv8_inv_b(0) <= not( lv7_or(0) ); + + b000_256_enc0: lv8_enc0_b(0) <= not( lv8_inv_b(0) );--dflt1 + + b000_256_enc1: lv8_enc1_b(0) <= not( lv7_enc1(0) or (lv7_enc1(1) and lv8_inv_b(0)) ); + + b000_256_enc2: lv8_enc2_b(0) <= not( lv7_enc2(0) or (lv7_enc2(1) and lv8_inv_b(0)) ); + + b000_256_enc3: lv8_enc3_b(0) <= not( lv7_enc3(0) or (lv7_enc3(1) and lv8_inv_b(0)) ); + + b000_256_enc4: lv8_enc4_b(0) <= not( lv7_enc4(0) or (lv7_enc4(1) and lv8_inv_b(0)) ); + + b000_256_enc5: lv8_enc5_b(0) <= not( lv7_enc5(0) or (lv7_enc5(1) and lv8_inv_b(0)) ); + + b000_256_enc6: lv8_enc6_b(0) <= not( lv7_enc6(0) or (lv7_enc6(1) and lv8_inv_b(0)) ); + + b000_256_enc7: lv8_enc7_b(0) <= not( lv7_enc7(0) or (lv7_enc7(1) and lv8_inv_b(0)) ); + + + o_any: lza_any_b <= ( lv8_or_b(0) );--repower,long wire + o_enc0: lza_amt_b(0) <= ( lv8_enc0_b(0) );--repower,long wire + o_enc1: lza_amt_b(1) <= ( lv8_enc1_b(0) );--repower,long wire + o_enc2: lza_amt_b(2) <= ( lv8_enc2_b(0) );--repower,long wire + o_enc3: lza_amt_b(3) <= ( lv8_enc3_b(0) );--repower,long wire + o_enc4: lza_amt_b(4) <= ( lv8_enc4_b(0) );--repower,long wire + o_enc5: lza_amt_b(5) <= ( lv8_enc5_b(0) );--repower,long wire + o_enc6: lza_amt_b(6) <= ( lv8_enc6_b(0) );--repower,long wire + o_enc7: lza_amt_b(7) <= ( lv8_enc7_b(0) );--repower,long wire + + + + + + + + +END; -- ARCH fuq_lza_clz diff --git a/rel/src/vhdl/work/fuq_lza_ej.vhdl b/rel/src/vhdl/work/fuq_lza_ej.vhdl new file mode 100644 index 0000000..868a1d1 --- /dev/null +++ b/rel/src/vhdl/work/fuq_lza_ej.vhdl @@ -0,0 +1,169 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; use ieee.std_logic_1164.all ; +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + +entity fuq_lza_ej is port( + effsub :in std_ulogic; + sum :in std_ulogic_vector(0 to 162); + car :in std_ulogic_vector(53 to 162); + lzo_b :in std_ulogic_vector(0 to 162); + edge :out std_ulogic_vector(0 to 162) + ); +END fuq_lza_ej; + + -- generic 3 bit edge :: + -- P G !Z + -- P Z !G + -- !P G !G + -- !P Z !Z + +ARCHITECTURE fuq_lza_ej OF fuq_lza_ej IS + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal x0, x1, x2 :std_ulogic_vector(0 to 52); + signal x1_b, ej_b :std_ulogic_vector(0 to 52); + signal g_b, z, p, g, z_b, p_b :std_ulogic_vector(53 to 162); + signal sum_52_b :std_ulogic; + signal lzo_54 :std_ulogic; + signal gz, zg, gg, zz :std_ulogic_vector(55 to 162); + signal e0_b, e1_b :std_ulogic_vector(53 to 162); + signal e2_b : std_ulogic_vector(54 to 54); + signal unused :std_ulogic ; + + + + +BEGIN + +unused <= g(54) or z_b(53) or z_b(162) or p_b(161) or p_b(162) ; + + --------------------------------------------- + -- (0:52) only one data input + --------------------------------------------- + + x0(0 to 52) <= tidn & effsub & sum(0 to 50); -- just a rename + x1(0 to 52) <= effsub & sum(0 to 51); -- just a rename + x2(0 to 52) <= sum(0 to 52); -- just a rename + + + xb_00: x1_b(0 to 52) <= not x1(0 to 52) ; + ejx_00: ej_b(0 to 52) <= not( x1_b(0 to 52) and ( x0(0 to 52) or x2(0 to 52) ) ); + ej_00: edge(0 to 52) <= not( ej_b(0 to 52) and lzo_b(0 to 52) ); + + ------------------------------------------------------------------- + -- (53) psuedo bit + ------------------------------------------------------------------- + + glo_53: g_b(53) <= not( sum(53) and car(53) ); + zhi_53: z (53) <= not( sum(53) or car(53) ); + phi_53: p (53) <= ( sum(53) xor car(53) ); + + ghi_53: g (53) <= not( g_b(53) ); + zlo_53: z_b(53) <= not( z (53) );--UNUSED + plo_53: p_b(53) <= not( p (53) ); + s52_53: sum_52_b <= not( sum(52) ); + + e0_53: e0_b(53) <= not( sum(51) and sum_52_b ); + e1_53: e1_b(53) <= not( sum_52_b and g(53) ); + ej_53: edge(53) <= not( lzo_b(53) and e0_b(53) and e1_b(53) ); --output + + + ------------------------------------------------------------------- + -- (54) pseudo bit + 1 + ------------------------------------------------------------------- + + glo_54: g_b(54) <= not( sum(54) and car(54) ); + zhi_54: z (54) <= not( sum(54) or car(54) ); + phi_54: p (54) <= ( sum(54) xor car(54) ); + + ghi_54: g (54) <= not( g_b(54) );--UNUSED + zlo_54: z_b(54) <= not( z (54) ); + plo_54: p_b(54) <= not( p (54) ); + + zb_54: lzo_54 <= not lzo_b(54); + + e0_54: e0_b(54) <= not( sum_52_b and p(53) and z_b(54) ); --really is p54 (demotes to z54) + e1_54: e1_b(54) <= not( sum(52) and p(53) and g_b(54) ); --really is p54 (demotes to z54) + e2_54: e2_b(54) <= not( (sum(52) and z(53) ) or lzo_54 ); + ej_54: edge(54) <= not( e0_b(54) and e1_b(54) and e2_b(54) ); --output + + ------------------------------------------------------------------- + -- (55) pseudo bit + 2 + ------------------------------------------------------------------- + + glo_55: g_b(55) <= not( sum(55) and car(55) ); + zhi_55: z (55) <= not( sum(55) or car(55) ); + phi_55: p (55) <= ( sum(55) xor car(55) ); + + ghi_55: g (55) <= not( g_b(55) ); + zlo_55: z_b(55) <= not( z (55) ); + plo_55: p_b(55) <= not( p (55) ); + + gz_55: gz(55) <= not( g_b(54) or z(55) ); + zg_55: zg(55) <= not( z_b(54) or g(55) ); + gg_55: gg(55) <= not( g_b(54) or g(55) ); + zz_55: zz(55) <= not( z_b(54) or z(55) ); + + e1_55: e1_b(55) <= not( p_b(53) and ( gz(55) or zg(55) ) ); -- P is flipped for psuedo bit + e0_55: e0_b(55) <= not( p (53) and ( gg(55) or zz(55) ) ); -- P is flipped for psuedo bit + ej_55: edge(55) <= not( e0_b(55) and e1_b(55) and lzo_b(55) ); --output + + ------------------------------------------------------------------- + -- (56:162) normal 2 input edge + ------------------------------------------------------------------- + + glo_56: g_b(56 to 162) <= not( sum(56 to 162) and car(56 to 162) ); + zhi_56: z (56 to 162) <= not( sum(56 to 162) or car(56 to 162) ); + phi_56: p (56 to 162) <= ( sum(56 to 162) xor car(56 to 162) ); + + ghi_56: g (56 to 162) <= not( g_b(56 to 162) ); + zlo_56: z_b(56 to 162) <= not( z (56 to 162) );--162 unused + plo_56: p_b(56 to 162) <= not( p (56 to 162) );--161,162 unused + + gz_56: gz(56 to 162) <= not( g_b(55 to 161) or z(56 to 162) ); + zg_56: zg(56 to 162) <= not( z_b(55 to 161) or g(56 to 162) ); + gg_56: gg(56 to 162) <= not( g_b(55 to 161) or g(56 to 162) ); + zz_56: zz(56 to 162) <= not( z_b(55 to 161) or z(56 to 162) ); + + e1_56: e1_b(56 to 162) <= not( p (54 to 160) and ( gz(56 to 162) or zg(56 to 162) ) ); + e0_56: e0_b(56 to 162) <= not( p_b(54 to 160) and ( gg(56 to 162) or zz(56 to 162) ) ); + ej_56: edge(56 to 162) <= not( e0_b(56 to 162) and e1_b(56 to 162) and lzo_b(56 to 162) ); --output + + +END; -- ARCH fuq_lza_ej diff --git a/rel/src/vhdl/work/fuq_lze.vhdl b/rel/src/vhdl/work/fuq_lze.vhdl new file mode 100644 index 0000000..f9bb827 --- /dev/null +++ b/rel/src/vhdl/work/fuq_lze.vhdl @@ -0,0 +1,1000 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +-- LZE (exponent for leading zeroes anticipater) + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + +entity fuq_lze is +generic( expand_type: integer := 2 ); -- 0 - ibm tech, 1 - other ); +port( + vdd :inout power_logic; + gnd :inout power_logic; + clkoff_b :in std_ulogic; -- tiup + act_dis :in std_ulogic; -- ??tidn?? + flush :in std_ulogic; -- ??tidn?? + delay_lclkr :in std_ulogic_vector(2 to 3); -- tidn, + mpw1_b :in std_ulogic_vector(2 to 3); -- tidn, + mpw2_b :in std_ulogic_vector(0 to 0); -- tidn, + sg_1 :in std_ulogic; + thold_1 :in std_ulogic; + fpu_enable :in std_ulogic; --dc_act + nclk :in clk_logic; + + f_lze_si :in std_ulogic; --perv + f_lze_so :out std_ulogic; --perv + ex1_act_b :in std_ulogic; --act + + f_eie_ex2_lzo_expo :in std_ulogic_vector(1 to 13) ; + f_eie_ex2_b_expo :in std_ulogic_vector(1 to 13) ; + f_eie_ex2_use_bexp :in std_ulogic; + f_pic_ex2_lzo_dis_prod :in std_ulogic; + f_pic_ex2_sp_lzo :in std_ulogic; + f_pic_ex2_est_recip :in std_ulogic; + f_pic_ex2_est_rsqrt :in std_ulogic; + f_fmt_ex2_pass_msb_dp :in std_ulogic; + f_pic_ex2_frsp_ue1 :in std_ulogic; + f_alg_ex2_byp_nonflip :in std_ulogic; + f_pic_ex2_b_valid :in std_ulogic; + f_alg_ex2_sel_byp :in std_ulogic; + f_pic_ex2_to_integer :in std_ulogic; + f_pic_ex2_prenorm :in std_ulogic; + + f_lze_ex2_lzo_din :out std_ulogic_vector(0 to 162); + f_lze_ex3_sh_rgt_amt :out std_ulogic_vector(0 to 7); + f_lze_ex3_sh_rgt_en :out std_ulogic + +); + + + + + + +end fuq_lze; -- ENTITY + +architecture fuq_lze of fuq_lze is + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal thold_0_b, thold_0, forcee, sg_0 :std_ulogic; + signal ex1_act, ex2_act :std_ulogic; + signal spare_unused :std_ulogic_vector(0 to 3); + signal ex2_dp_001_by :std_ulogic; + signal ex2_sp_001_by :std_ulogic; + signal ex2_addr_dp_by :std_ulogic; + signal ex2_addr_sp_by :std_ulogic; + signal ex2_en_addr_dp_by :std_ulogic; + signal ex2_en_addr_sp_by :std_ulogic; + signal ex2_lzo_en, ex2_lzo_en_rapsp :std_ulogic; + signal ex2_lzo_en_by :std_ulogic; + signal ex2_expo_neg_dp_by :std_ulogic; + signal ex2_expo_neg_sp_by :std_ulogic; + signal ex2_expo_6_adj_by :std_ulogic; + signal ex2_addr_dp :std_ulogic; + signal ex2_addr_sp, ex2_addr_sp_rap :std_ulogic; + signal ex2_en_addr_dp :std_ulogic; + signal ex2_en_addr_sp, ex2_en_addr_sp_rap :std_ulogic; + signal ex2_lzo_cont :std_ulogic; + signal ex2_lzo_cont_dp :std_ulogic; + signal ex2_lzo_cont_sp :std_ulogic; + signal ex2_expo_neg_dp :std_ulogic; + signal ex2_expo_neg_sp :std_ulogic; + signal ex2_expo_6_adj :std_ulogic; + signal ex2_ins_est :std_ulogic; + signal ex2_sh_rgt_en_by :std_ulogic; + signal ex2_sh_rgt_en_p :std_ulogic; + signal ex2_sh_rgt_en :std_ulogic; + signal ex2_lzo_forbyp_0 :std_ulogic; + signal ex2_lzo_nonbyp_0 :std_ulogic; + signal ex3_sh_rgt_en :std_ulogic; + signal ex2_expo_by :std_ulogic_vector(1 to 13) ; + signal ex2_lzo_dcd_hi_by :std_ulogic_vector( 0 to 0) ; + signal ex2_lzo_dcd_lo_by :std_ulogic_vector( 0 to 0); + signal ex2_expo :std_ulogic_vector(1 to 13) ; + signal ex2_lzo_dcd_hi :std_ulogic_vector( 0 to 10); + signal ex2_lzo_dcd_lo :std_ulogic_vector( 0 to 15); + signal ex2_expo_p_sim_p :std_ulogic_vector(8 to 13); + signal ex2_expo_p_sim_g :std_ulogic_vector(9 to 13); + signal ex2_expo_p_sim :std_ulogic_vector(8 to 13) ; + signal ex2_expo_sim_p :std_ulogic_vector(8 to 13) ; + signal ex2_expo_sim_g :std_ulogic_vector(9 to 13) ; + signal ex2_expo_sim :std_ulogic_vector(8 to 13) ; + signal ex2_sh_rgt_amt :std_ulogic_vector(0 to 7); + signal ex3_shr_so, ex3_shr_si :std_ulogic_vector(0 to 8); + signal act_so, act_si :std_ulogic_vector(0 to 4); + signal ex3_sh_rgt_amt :std_ulogic_vector(0 to 7); + signal ex2_lzo_dcd_0 :std_ulogic; + signal ex2_lzo_dcd_b :std_ulogic_vector(0 to 162); +signal unused :std_ulogic; +signal f_alg_ex2_sel_byp_b , ex2_lzo_nonbyp_0_b , ex2_lzo_forbyp_0_b :std_ulogic ; + + + + + + +begin + + unused <= ex2_lzo_dcd_b(0) ; + +---=############################################################### +---= pervasive +---=############################################################### + + + thold_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => thold_1, + q(0) => thold_0 ); + + sg_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => sg_1 , + q(0) => sg_0 ); + + + lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map ( + clkoff_b => clkoff_b, + thold => thold_0, + sg => sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => thold_0_b ); + + +---=############################################################### +---= act +---=############################################################### + + ex1_act <= not ex1_act_b; + + act_lat: tri_rlmreg_p generic map (width=> 5, expand_type => expand_type, needs_sreset => 0) port map ( + forcee => forcee,-- tidn, + delay_lclkr => delay_lclkr(2) ,-- tidn, + mpw1_b => mpw1_b(2) ,-- tidn, + mpw2_b => mpw2_b(0) ,-- tidn, + vd => vdd, + gd => gnd, + nclk => nclk, + act => fpu_enable, + thold_b => thold_0_b, + sg => sg_0, + scout => act_so , + scin => act_si , + ------------------- + din(0) => spare_unused(0), + din(1) => spare_unused(1), + din(2) => ex1_act, + din(3) => spare_unused(2), + din(4) => spare_unused(3), + ------------------- + dout(0) => spare_unused(0), + dout(1) => spare_unused(1), + dout(2) => ex2_act, + dout(3) => spare_unused(2) , + dout(4) => spare_unused(3) ); + +---=############################################################### +---= ex2 logic +---=############################################################### + + +ex2_dp_001_by <= --x001 + not ex2_expo_by(1) and + not ex2_expo_by(2) and + not ex2_expo_by(3) and + not ex2_expo_by(4) and + not ex2_expo_by(5) and + not ex2_expo_by(6) and + not ex2_expo_by(7) and + not ex2_expo_by(8) and + not ex2_expo_by(9) and + not ex2_expo_by(10) and + not ex2_expo_by(11) and + not ex2_expo_by(12) and + ex2_expo_by(13) ; + +ex2_sp_001_by <= --x381 + not ex2_expo_by(1) and + not ex2_expo_by(2) and + not ex2_expo_by(3) and + ex2_expo_by(4) and + ex2_expo_by(5) and + ex2_expo_by(6) and + not ex2_expo_by(7) and + not ex2_expo_by(8) and + not ex2_expo_by(9) and + not ex2_expo_by(10) and + not ex2_expo_by(11) and + not ex2_expo_by(12) and + ex2_expo_by(13) ; + + + +------------------------------------------------------------------ +-- lzo dcd when B = denorm. +-- sp denorm in dp_format may need to denormalize. +-- sp is bypassed at [26] so there is room to do this on the left +------------------------------------------------------------------ +-- if B is normalized when bypassed, then no need for denorm because it will not shift left ? +-- for EffSub, b MSB can move right 1 position ... only if BFrac = 0000111111,can't if bypass norm +-- If B==0 then should NOT bypass ... except for Move instructions. + +ex2_expo_by(1 to 13) <= f_eie_ex2_b_expo(1 to 13); + + + + --=#------------------------------------------------ + --=#-- LZO Decode + --=#------------------------------------------------ + -- the product exponent points at [0] in the dataflow. + -- the lzo puts a marker (false edge) at the point where shifting must stop + -- so the lza will not create a denormal exponent. (001/897) dp/sp. + -- if p_expo==1 then maker @ 0 + -- if p_expo==2 then maker @ 1 + -- if p_expo==3 then maker @ 2 + -- + -- false edges are also used to control shifting for to-integer, aligner-bypass + + + ex2_addr_dp_by <= not ex2_expo_by(1) and + not ex2_expo_by(2) and -- x001 (1) in bits above decode 256 + not ex2_expo_by(3) and + not ex2_expo_by(4) and + not ex2_expo_by(5) ; + + ex2_addr_sp_by <= not ex2_expo_by(1) and + not ex2_expo_by(2) and -- x381 (897) in bits above decode 256 + not ex2_expo_by(3) and + ex2_expo_by(4) and + ex2_expo_by(5) ; + + ex2_en_addr_dp_by <= ex2_addr_dp_by and ex2_lzo_cont_dp ; + ex2_en_addr_sp_by <= ex2_addr_sp_by and ex2_lzo_cont_sp ; + + + + -- want to avoid shift right for sp op with shOv of sp_den in dp format + -- sp is bypassed 26 positions to the left , mark with LZO to create the denorm. + + ex2_lzo_en_by <= (ex2_en_addr_dp_by or ex2_en_addr_sp_by) and ex2_lzo_cont ; + + ex2_expo_neg_dp_by <= + (ex2_lzo_en_by and ex2_lzo_dcd_hi_by( 0) and ex2_lzo_dcd_lo_by( 0) ) or --decode 0 + (ex2_expo_by(1) ) ; --negative exponent + + -- dp denorm starts at 0, but sp denorm starts at 896 (x380) + -- sp addr 0_0011_xxxx_xxxx covers 0768-1023 + -- 0_000x_xxxx_xxxx covers 0000,0001 + -- 0_00x0_xxxx_xxxx covers 0000,0010 + + ex2_expo_neg_sp_by <= + ( ex2_expo_by(1)) or -- negative + (not ex2_expo_by(2) and not ex2_expo_by(3) and not ex2_expo_by(4) ) or + (not ex2_expo_by(2) and not ex2_expo_by(3) and not ex2_expo_by(5) ) or + (not ex2_expo_by(2) and not ex2_expo_by(3) and not ex2_expo_by(6) ) or + (not ex2_expo_by(2) and not ex2_expo_by(3) and ex2_expo_by(4) and ex2_expo_by(5) and ex2_expo_by(6) and + not(ex2_expo_by(7) or ex2_expo_by(8) or ex2_expo_by(9) or ex2_expo_by(10) or ex2_expo_by(11) or ex2_expo_by(12) or ex2_expo_by(13) ) ); + + + + ex2_expo_6_adj_by <= (not ex2_expo_by(6) and f_pic_ex2_sp_lzo) or + ( ex2_expo_by(6) and not f_pic_ex2_sp_lzo) ; + + + ex2_lzo_dcd_0 <= ex2_lzo_dcd_hi( 0) and ex2_lzo_dcd_lo(1) ; + + + ex2_lzo_dcd_hi_by( 0) <= not ex2_expo_6_adj_by and not ex2_expo_by( 7) and not ex2_expo_by( 8) and not ex2_expo_by( 9) and ex2_lzo_en_by; + + ex2_lzo_dcd_lo_by( 0) <= not ex2_expo_by(10) and not ex2_expo_by(11) and not ex2_expo_by(12) and not ex2_expo_by(13) ; + + + + --=#------------------------------------------------ + --=#-- LZO Decode + --=#------------------------------------------------ + -- the product exponent points at [0] in the dataflow. + -- the lzo puts a marker (false edge) at the point where shifting must stop + -- so the lza will not create a denormal exponent. (001/897) dp/sp. + -- if p_expo==1 then maker @ 0 + -- if p_expo==2 then maker @ 1 + -- if p_expo==3 then maker @ 2 + -- + -- false edges are also used to control shifting for to-integer, aligner-bypass + + + ex2_expo(1 to 13) <= f_eie_ex2_lzo_expo(1 to 13); + ex2_addr_dp <= not ex2_expo(1) and + not ex2_expo(2) and -- x001 (1) in bits above decode 256 + not ex2_expo(3) and + not ex2_expo(4) and + not ex2_expo(5) ; + + ex2_addr_sp <= not ex2_expo(1) and + not ex2_expo(2) and -- x381 (897) in bits above decode 256 + not ex2_expo(3) and + ex2_expo(4) and + ex2_expo(5) ; + + ex2_addr_sp_rap <= not ex2_expo(1) and + not ex2_expo(2) and -- x381 (897) in bits above decode 256 + ex2_expo(3) and + not ex2_expo(4) and + not ex2_expo(5) ; + + ex2_en_addr_dp <= ex2_addr_dp and ex2_lzo_cont_dp ; + ex2_en_addr_sp <= ex2_addr_sp and ex2_lzo_cont_sp ; + ex2_en_addr_sp_rap <= ex2_addr_sp_rap and ex2_lzo_cont_sp ; + + ex2_lzo_cont <= not f_pic_ex2_lzo_dis_prod ; + ex2_lzo_cont_dp <= not f_pic_ex2_lzo_dis_prod and not f_pic_ex2_sp_lzo ; + ex2_lzo_cont_sp <= not f_pic_ex2_lzo_dis_prod and f_pic_ex2_sp_lzo ; + + + + + -- want to avoid shift right for sp op with shOv of sp_den in dp format + -- sp is bypassed 26 positions to the left , mark with LZO to create the denorm. + + ex2_lzo_en <= (ex2_en_addr_dp or ex2_en_addr_sp) and ex2_lzo_cont ; + ex2_lzo_en_rapsp <= (ex2_en_addr_dp or ex2_en_addr_sp_rap) and ex2_lzo_cont ; + + ex2_expo_neg_dp <= + (ex2_lzo_en and ex2_lzo_dcd_hi( 0) and ex2_lzo_dcd_lo( 0) ) or --decode 0 + (ex2_expo(1) ) ; --negative exponent + + + ex2_expo_neg_sp <= + ( ex2_expo(1)) or -- negative + (not ex2_expo(2) and not ex2_expo(3) and not ex2_expo(4) ) or + (not ex2_expo(2) and not ex2_expo(3) and not ex2_expo(5) ) or + (not ex2_expo(2) and not ex2_expo(3) and not ex2_expo(6) ) or + (not ex2_expo(2) and not ex2_expo(3) and ex2_expo(4) and ex2_expo(5) and ex2_expo(6) and + not(ex2_expo(7) or ex2_expo(8) or ex2_expo(9) or ex2_expo(10) or ex2_expo(11) or ex2_expo(12) or ex2_expo(13)) ); + + + + ex2_expo_6_adj <= (not ex2_expo(6) and f_pic_ex2_sp_lzo) or + ( ex2_expo(6) and not f_pic_ex2_sp_lzo) ; + + + ex2_lzo_dcd_hi( 0) <= not ex2_expo_6_adj and not ex2_expo( 7) and not ex2_expo( 8) and not ex2_expo( 9) and ex2_lzo_en; + ex2_lzo_dcd_hi( 1) <= not ex2_expo_6_adj and not ex2_expo( 7) and not ex2_expo( 8) and ex2_expo( 9) and ex2_lzo_en; + ex2_lzo_dcd_hi( 2) <= not ex2_expo_6_adj and not ex2_expo( 7) and ex2_expo( 8) and not ex2_expo( 9) and ex2_lzo_en; + ex2_lzo_dcd_hi( 3) <= not ex2_expo_6_adj and not ex2_expo( 7) and ex2_expo( 8) and ex2_expo( 9) and ex2_lzo_en; + ex2_lzo_dcd_hi( 4) <= not ex2_expo_6_adj and ex2_expo( 7) and not ex2_expo( 8) and not ex2_expo( 9) and ex2_lzo_en; + ex2_lzo_dcd_hi( 5) <= not ex2_expo_6_adj and ex2_expo( 7) and not ex2_expo( 8) and ex2_expo( 9) and ex2_lzo_en; + ex2_lzo_dcd_hi( 6) <= not ex2_expo_6_adj and ex2_expo( 7) and ex2_expo( 8) and not ex2_expo( 9) and ex2_lzo_en; + ex2_lzo_dcd_hi( 7) <= not ex2_expo_6_adj and ex2_expo( 7) and ex2_expo( 8) and ex2_expo( 9) and ex2_lzo_en; + ex2_lzo_dcd_hi( 8) <= ex2_expo_6_adj and not ex2_expo( 7) and not ex2_expo( 8) and not ex2_expo( 9) and ex2_lzo_en_rapsp; + ex2_lzo_dcd_hi( 9) <= ex2_expo_6_adj and not ex2_expo( 7) and not ex2_expo( 8) and ex2_expo( 9) and ex2_lzo_en_rapsp; + ex2_lzo_dcd_hi(10) <= ex2_expo_6_adj and not ex2_expo( 7) and ex2_expo( 8) and not ex2_expo( 9) and ex2_lzo_en_rapsp; + + ex2_lzo_dcd_lo( 0) <= not ex2_expo(10) and not ex2_expo(11) and not ex2_expo(12) and not ex2_expo(13) ; + ex2_lzo_dcd_lo( 1) <= not ex2_expo(10) and not ex2_expo(11) and not ex2_expo(12) and ex2_expo(13) ; + ex2_lzo_dcd_lo( 2) <= not ex2_expo(10) and not ex2_expo(11) and ex2_expo(12) and not ex2_expo(13) ; + ex2_lzo_dcd_lo( 3) <= not ex2_expo(10) and not ex2_expo(11) and ex2_expo(12) and ex2_expo(13) ; + ex2_lzo_dcd_lo( 4) <= not ex2_expo(10) and ex2_expo(11) and not ex2_expo(12) and not ex2_expo(13) ; + ex2_lzo_dcd_lo( 5) <= not ex2_expo(10) and ex2_expo(11) and not ex2_expo(12) and ex2_expo(13) ; + ex2_lzo_dcd_lo( 6) <= not ex2_expo(10) and ex2_expo(11) and ex2_expo(12) and not ex2_expo(13) ; + ex2_lzo_dcd_lo( 7) <= not ex2_expo(10) and ex2_expo(11) and ex2_expo(12) and ex2_expo(13) ; + ex2_lzo_dcd_lo( 8) <= ex2_expo(10) and not ex2_expo(11) and not ex2_expo(12) and not ex2_expo(13) ; + ex2_lzo_dcd_lo( 9) <= ex2_expo(10) and not ex2_expo(11) and not ex2_expo(12) and ex2_expo(13) ; + ex2_lzo_dcd_lo(10) <= ex2_expo(10) and not ex2_expo(11) and ex2_expo(12) and not ex2_expo(13) ; + ex2_lzo_dcd_lo(11) <= ex2_expo(10) and not ex2_expo(11) and ex2_expo(12) and ex2_expo(13) ; + ex2_lzo_dcd_lo(12) <= ex2_expo(10) and ex2_expo(11) and not ex2_expo(12) and not ex2_expo(13) ; + ex2_lzo_dcd_lo(13) <= ex2_expo(10) and ex2_expo(11) and not ex2_expo(12) and ex2_expo(13) ; + ex2_lzo_dcd_lo(14) <= ex2_expo(10) and ex2_expo(11) and ex2_expo(12) and not ex2_expo(13) ; + ex2_lzo_dcd_lo(15) <= ex2_expo(10) and ex2_expo(11) and ex2_expo(12) and ex2_expo(13) ; + + + + + +u_lzo_dcd_0: ex2_lzo_dcd_b( 0) <= not( ex2_lzo_dcd_hi(0) and ex2_lzo_dcd_lo(1) ); +u_lzo_dcd_1: ex2_lzo_dcd_b( 1) <= not( ex2_lzo_dcd_hi(0) and ex2_lzo_dcd_lo(2) ); +u_lzo_dcd_2: ex2_lzo_dcd_b( 2) <= not( ex2_lzo_dcd_hi(0) and ex2_lzo_dcd_lo(3) ); +u_lzo_dcd_3: ex2_lzo_dcd_b( 3) <= not( ex2_lzo_dcd_hi(0) and ex2_lzo_dcd_lo(4) ); +u_lzo_dcd_4: ex2_lzo_dcd_b( 4) <= not( ex2_lzo_dcd_hi(0) and ex2_lzo_dcd_lo(5) ); +u_lzo_dcd_5: ex2_lzo_dcd_b( 5) <= not( ex2_lzo_dcd_hi(0) and ex2_lzo_dcd_lo(6) ); +u_lzo_dcd_6: ex2_lzo_dcd_b( 6) <= not( ex2_lzo_dcd_hi(0) and ex2_lzo_dcd_lo(7) ); +u_lzo_dcd_7: ex2_lzo_dcd_b( 7) <= not( ex2_lzo_dcd_hi(0) and ex2_lzo_dcd_lo(8) ); +u_lzo_dcd_8: ex2_lzo_dcd_b( 8) <= not( ex2_lzo_dcd_hi(0) and ex2_lzo_dcd_lo(9) ); +u_lzo_dcd_9: ex2_lzo_dcd_b( 9) <= not( ex2_lzo_dcd_hi(0) and ex2_lzo_dcd_lo(10) ); +u_lzo_dcd_10: ex2_lzo_dcd_b( 10) <= not( ex2_lzo_dcd_hi(0) and ex2_lzo_dcd_lo(11) ); +u_lzo_dcd_11: ex2_lzo_dcd_b( 11) <= not( ex2_lzo_dcd_hi(0) and ex2_lzo_dcd_lo(12) ); +u_lzo_dcd_12: ex2_lzo_dcd_b( 12) <= not( ex2_lzo_dcd_hi(0) and ex2_lzo_dcd_lo(13) ); +u_lzo_dcd_13: ex2_lzo_dcd_b( 13) <= not( ex2_lzo_dcd_hi(0) and ex2_lzo_dcd_lo(14) ); +u_lzo_dcd_14: ex2_lzo_dcd_b( 14) <= not( ex2_lzo_dcd_hi(0) and ex2_lzo_dcd_lo(15) ); + +u_lzo_dcd_15: ex2_lzo_dcd_b( 15) <= not( ex2_lzo_dcd_hi(1) and ex2_lzo_dcd_lo(0) ); +u_lzo_dcd_16: ex2_lzo_dcd_b( 16) <= not( ex2_lzo_dcd_hi(1) and ex2_lzo_dcd_lo(1) ); +u_lzo_dcd_17: ex2_lzo_dcd_b( 17) <= not( ex2_lzo_dcd_hi(1) and ex2_lzo_dcd_lo(2) ); +u_lzo_dcd_18: ex2_lzo_dcd_b( 18) <= not( ex2_lzo_dcd_hi(1) and ex2_lzo_dcd_lo(3) ); +u_lzo_dcd_19: ex2_lzo_dcd_b( 19) <= not( ex2_lzo_dcd_hi(1) and ex2_lzo_dcd_lo(4) ); +u_lzo_dcd_20: ex2_lzo_dcd_b( 20) <= not( ex2_lzo_dcd_hi(1) and ex2_lzo_dcd_lo(5) ); +u_lzo_dcd_21: ex2_lzo_dcd_b( 21) <= not( ex2_lzo_dcd_hi(1) and ex2_lzo_dcd_lo(6) ); +u_lzo_dcd_22: ex2_lzo_dcd_b( 22) <= not( ex2_lzo_dcd_hi(1) and ex2_lzo_dcd_lo(7) ); +u_lzo_dcd_23: ex2_lzo_dcd_b( 23) <= not( ex2_lzo_dcd_hi(1) and ex2_lzo_dcd_lo(8) ); +u_lzo_dcd_24: ex2_lzo_dcd_b( 24) <= not( ex2_lzo_dcd_hi(1) and ex2_lzo_dcd_lo(9) ); +u_lzo_dcd_25: ex2_lzo_dcd_b( 25) <= not( ex2_lzo_dcd_hi(1) and ex2_lzo_dcd_lo(10) ); +u_lzo_dcd_26: ex2_lzo_dcd_b( 26) <= not( ex2_lzo_dcd_hi(1) and ex2_lzo_dcd_lo(11) ); +u_lzo_dcd_27: ex2_lzo_dcd_b( 27) <= not( ex2_lzo_dcd_hi(1) and ex2_lzo_dcd_lo(12) ); +u_lzo_dcd_28: ex2_lzo_dcd_b( 28) <= not( ex2_lzo_dcd_hi(1) and ex2_lzo_dcd_lo(13) ); +u_lzo_dcd_29: ex2_lzo_dcd_b( 29) <= not( ex2_lzo_dcd_hi(1) and ex2_lzo_dcd_lo(14) ); +u_lzo_dcd_30: ex2_lzo_dcd_b( 30) <= not( ex2_lzo_dcd_hi(1) and ex2_lzo_dcd_lo(15) ); + +u_lzo_dcd_31: ex2_lzo_dcd_b( 31) <= not( ex2_lzo_dcd_hi(2) and ex2_lzo_dcd_lo(0 ) ); +u_lzo_dcd_32: ex2_lzo_dcd_b( 32) <= not( ex2_lzo_dcd_hi(2) and ex2_lzo_dcd_lo(1 ) ); +u_lzo_dcd_33: ex2_lzo_dcd_b( 33) <= not( ex2_lzo_dcd_hi(2) and ex2_lzo_dcd_lo(2 ) ); +u_lzo_dcd_34: ex2_lzo_dcd_b( 34) <= not( ex2_lzo_dcd_hi(2) and ex2_lzo_dcd_lo(3 ) ); +u_lzo_dcd_35: ex2_lzo_dcd_b( 35) <= not( ex2_lzo_dcd_hi(2) and ex2_lzo_dcd_lo(4 ) ); +u_lzo_dcd_36: ex2_lzo_dcd_b( 36) <= not( ex2_lzo_dcd_hi(2) and ex2_lzo_dcd_lo(5 ) ); +u_lzo_dcd_37: ex2_lzo_dcd_b( 37) <= not( ex2_lzo_dcd_hi(2) and ex2_lzo_dcd_lo(6 ) ); +u_lzo_dcd_38: ex2_lzo_dcd_b( 38) <= not( ex2_lzo_dcd_hi(2) and ex2_lzo_dcd_lo(7 ) ); +u_lzo_dcd_39: ex2_lzo_dcd_b( 39) <= not( ex2_lzo_dcd_hi(2) and ex2_lzo_dcd_lo(8 ) ); +u_lzo_dcd_40: ex2_lzo_dcd_b( 40) <= not( ex2_lzo_dcd_hi(2) and ex2_lzo_dcd_lo(9 ) ); +u_lzo_dcd_41: ex2_lzo_dcd_b( 41) <= not( ex2_lzo_dcd_hi(2) and ex2_lzo_dcd_lo(10) ); +u_lzo_dcd_42: ex2_lzo_dcd_b( 42) <= not( ex2_lzo_dcd_hi(2) and ex2_lzo_dcd_lo(11) ); +u_lzo_dcd_43: ex2_lzo_dcd_b( 43) <= not( ex2_lzo_dcd_hi(2) and ex2_lzo_dcd_lo(12) ); +u_lzo_dcd_44: ex2_lzo_dcd_b( 44) <= not( ex2_lzo_dcd_hi(2) and ex2_lzo_dcd_lo(13) ); +u_lzo_dcd_45: ex2_lzo_dcd_b( 45) <= not( ex2_lzo_dcd_hi(2) and ex2_lzo_dcd_lo(14) ); +u_lzo_dcd_46: ex2_lzo_dcd_b( 46) <= not( ex2_lzo_dcd_hi(2) and ex2_lzo_dcd_lo(15) ); + +u_lzo_dcd_47: ex2_lzo_dcd_b( 47) <= not( ex2_lzo_dcd_hi(3) and ex2_lzo_dcd_lo(0 ) ); +u_lzo_dcd_48: ex2_lzo_dcd_b( 48) <= not( ex2_lzo_dcd_hi(3) and ex2_lzo_dcd_lo(1 ) ); +u_lzo_dcd_49: ex2_lzo_dcd_b( 49) <= not( ex2_lzo_dcd_hi(3) and ex2_lzo_dcd_lo(2 ) ); +u_lzo_dcd_50: ex2_lzo_dcd_b( 50) <= not( ex2_lzo_dcd_hi(3) and ex2_lzo_dcd_lo(3 ) ); +u_lzo_dcd_51: ex2_lzo_dcd_b( 51) <= not( ex2_lzo_dcd_hi(3) and ex2_lzo_dcd_lo(4 ) ); +u_lzo_dcd_52: ex2_lzo_dcd_b( 52) <= not( ex2_lzo_dcd_hi(3) and ex2_lzo_dcd_lo(5 ) ); +u_lzo_dcd_53: ex2_lzo_dcd_b( 53) <= not( ex2_lzo_dcd_hi(3) and ex2_lzo_dcd_lo(6 ) ); +u_lzo_dcd_54: ex2_lzo_dcd_b( 54) <= not( ex2_lzo_dcd_hi(3) and ex2_lzo_dcd_lo(7 ) ); +u_lzo_dcd_55: ex2_lzo_dcd_b( 55) <= not( ex2_lzo_dcd_hi(3) and ex2_lzo_dcd_lo(8 ) ); +u_lzo_dcd_56: ex2_lzo_dcd_b( 56) <= not( ex2_lzo_dcd_hi(3) and ex2_lzo_dcd_lo(9 ) ); +u_lzo_dcd_57: ex2_lzo_dcd_b( 57) <= not( ex2_lzo_dcd_hi(3) and ex2_lzo_dcd_lo(10) ); +u_lzo_dcd_58: ex2_lzo_dcd_b( 58) <= not( ex2_lzo_dcd_hi(3) and ex2_lzo_dcd_lo(11) ); +u_lzo_dcd_59: ex2_lzo_dcd_b( 59) <= not( ex2_lzo_dcd_hi(3) and ex2_lzo_dcd_lo(12) ); +u_lzo_dcd_60: ex2_lzo_dcd_b( 60) <= not( ex2_lzo_dcd_hi(3) and ex2_lzo_dcd_lo(13) ); +u_lzo_dcd_61: ex2_lzo_dcd_b( 61) <= not( ex2_lzo_dcd_hi(3) and ex2_lzo_dcd_lo(14) ); +u_lzo_dcd_62: ex2_lzo_dcd_b( 62) <= not( ex2_lzo_dcd_hi(3) and ex2_lzo_dcd_lo(15) ); + +u_lzo_dcd_63: ex2_lzo_dcd_b( 63) <= not( ex2_lzo_dcd_hi(4) and ex2_lzo_dcd_lo(0 ) ); +u_lzo_dcd_64: ex2_lzo_dcd_b( 64) <= not( ex2_lzo_dcd_hi(4) and ex2_lzo_dcd_lo(1 ) ); +u_lzo_dcd_65: ex2_lzo_dcd_b( 65) <= not( ex2_lzo_dcd_hi(4) and ex2_lzo_dcd_lo(2 ) ); +u_lzo_dcd_66: ex2_lzo_dcd_b( 66) <= not( ex2_lzo_dcd_hi(4) and ex2_lzo_dcd_lo(3 ) ); +u_lzo_dcd_67: ex2_lzo_dcd_b( 67) <= not( ex2_lzo_dcd_hi(4) and ex2_lzo_dcd_lo(4 ) ); +u_lzo_dcd_68: ex2_lzo_dcd_b( 68) <= not( ex2_lzo_dcd_hi(4) and ex2_lzo_dcd_lo(5 ) ); +u_lzo_dcd_69: ex2_lzo_dcd_b( 69) <= not( ex2_lzo_dcd_hi(4) and ex2_lzo_dcd_lo(6 ) ); +u_lzo_dcd_70: ex2_lzo_dcd_b( 70) <= not( ex2_lzo_dcd_hi(4) and ex2_lzo_dcd_lo(7 ) ); +u_lzo_dcd_71: ex2_lzo_dcd_b( 71) <= not( ex2_lzo_dcd_hi(4) and ex2_lzo_dcd_lo(8 ) ); +u_lzo_dcd_72: ex2_lzo_dcd_b( 72) <= not( ex2_lzo_dcd_hi(4) and ex2_lzo_dcd_lo(9 ) ); +u_lzo_dcd_73: ex2_lzo_dcd_b( 73) <= not( ex2_lzo_dcd_hi(4) and ex2_lzo_dcd_lo(10) ); +u_lzo_dcd_74: ex2_lzo_dcd_b( 74) <= not( ex2_lzo_dcd_hi(4) and ex2_lzo_dcd_lo(11) ); +u_lzo_dcd_75: ex2_lzo_dcd_b( 75) <= not( ex2_lzo_dcd_hi(4) and ex2_lzo_dcd_lo(12) ); +u_lzo_dcd_76: ex2_lzo_dcd_b( 76) <= not( ex2_lzo_dcd_hi(4) and ex2_lzo_dcd_lo(13) ); +u_lzo_dcd_77: ex2_lzo_dcd_b( 77) <= not( ex2_lzo_dcd_hi(4) and ex2_lzo_dcd_lo(14) ); +u_lzo_dcd_78: ex2_lzo_dcd_b( 78) <= not( ex2_lzo_dcd_hi(4) and ex2_lzo_dcd_lo(15) ); + +u_lzo_dcd_79: ex2_lzo_dcd_b( 79) <= not( ex2_lzo_dcd_hi(5) and ex2_lzo_dcd_lo(0 ) ); +u_lzo_dcd_80: ex2_lzo_dcd_b( 80) <= not( ex2_lzo_dcd_hi(5) and ex2_lzo_dcd_lo(1 ) ); +u_lzo_dcd_81: ex2_lzo_dcd_b( 81) <= not( ex2_lzo_dcd_hi(5) and ex2_lzo_dcd_lo(2 ) ); +u_lzo_dcd_82: ex2_lzo_dcd_b( 82) <= not( ex2_lzo_dcd_hi(5) and ex2_lzo_dcd_lo(3 ) ); +u_lzo_dcd_83: ex2_lzo_dcd_b( 83) <= not( ex2_lzo_dcd_hi(5) and ex2_lzo_dcd_lo(4 ) ); +u_lzo_dcd_84: ex2_lzo_dcd_b( 84) <= not( ex2_lzo_dcd_hi(5) and ex2_lzo_dcd_lo(5 ) ); +u_lzo_dcd_85: ex2_lzo_dcd_b( 85) <= not( ex2_lzo_dcd_hi(5) and ex2_lzo_dcd_lo(6 ) ); +u_lzo_dcd_86: ex2_lzo_dcd_b( 86) <= not( ex2_lzo_dcd_hi(5) and ex2_lzo_dcd_lo(7 ) ); +u_lzo_dcd_87: ex2_lzo_dcd_b( 87) <= not( ex2_lzo_dcd_hi(5) and ex2_lzo_dcd_lo(8 ) ); +u_lzo_dcd_88: ex2_lzo_dcd_b( 88) <= not( ex2_lzo_dcd_hi(5) and ex2_lzo_dcd_lo(9 ) ); +u_lzo_dcd_89: ex2_lzo_dcd_b( 89) <= not( ex2_lzo_dcd_hi(5) and ex2_lzo_dcd_lo(10) ); +u_lzo_dcd_90: ex2_lzo_dcd_b( 90) <= not( ex2_lzo_dcd_hi(5) and ex2_lzo_dcd_lo(11) ); +u_lzo_dcd_91: ex2_lzo_dcd_b( 91) <= not( ex2_lzo_dcd_hi(5) and ex2_lzo_dcd_lo(12) ); +u_lzo_dcd_92: ex2_lzo_dcd_b( 92) <= not( ex2_lzo_dcd_hi(5) and ex2_lzo_dcd_lo(13) ); +u_lzo_dcd_93: ex2_lzo_dcd_b( 93) <= not( ex2_lzo_dcd_hi(5) and ex2_lzo_dcd_lo(14) ); +u_lzo_dcd_94: ex2_lzo_dcd_b( 94) <= not( ex2_lzo_dcd_hi(5) and ex2_lzo_dcd_lo(15) ); + +u_lzo_dcd_95: ex2_lzo_dcd_b( 95) <= not( ex2_lzo_dcd_hi(6) and ex2_lzo_dcd_lo(0 ) ); +u_lzo_dcd_96: ex2_lzo_dcd_b( 96) <= not( ex2_lzo_dcd_hi(6) and ex2_lzo_dcd_lo(1 ) ); +u_lzo_dcd_97: ex2_lzo_dcd_b( 97) <= not( ex2_lzo_dcd_hi(6) and ex2_lzo_dcd_lo(2 ) ); +u_lzo_dcd_98: ex2_lzo_dcd_b( 98) <= not( ex2_lzo_dcd_hi(6) and ex2_lzo_dcd_lo(3 ) ); +u_lzo_dcd_99: ex2_lzo_dcd_b( 99) <= not( ex2_lzo_dcd_hi(6) and ex2_lzo_dcd_lo(4 ) ); +u_lzo_dcd_100: ex2_lzo_dcd_b(100) <= not( ex2_lzo_dcd_hi(6) and ex2_lzo_dcd_lo(5 ) ); +u_lzo_dcd_101: ex2_lzo_dcd_b(101) <= not( ex2_lzo_dcd_hi(6) and ex2_lzo_dcd_lo(6 ) ); +u_lzo_dcd_102: ex2_lzo_dcd_b(102) <= not( ex2_lzo_dcd_hi(6) and ex2_lzo_dcd_lo(7 ) ); +u_lzo_dcd_103: ex2_lzo_dcd_b(103) <= not( ex2_lzo_dcd_hi(6) and ex2_lzo_dcd_lo(8 ) ); +u_lzo_dcd_104: ex2_lzo_dcd_b(104) <= not( ex2_lzo_dcd_hi(6) and ex2_lzo_dcd_lo(9 ) ); +u_lzo_dcd_105: ex2_lzo_dcd_b(105) <= not( ex2_lzo_dcd_hi(6) and ex2_lzo_dcd_lo(10) ); +u_lzo_dcd_106: ex2_lzo_dcd_b(106) <= not( ex2_lzo_dcd_hi(6) and ex2_lzo_dcd_lo(11) ); +u_lzo_dcd_107: ex2_lzo_dcd_b(107) <= not( ex2_lzo_dcd_hi(6) and ex2_lzo_dcd_lo(12) ); +u_lzo_dcd_108: ex2_lzo_dcd_b(108) <= not( ex2_lzo_dcd_hi(6) and ex2_lzo_dcd_lo(13) ); +u_lzo_dcd_109: ex2_lzo_dcd_b(109) <= not( ex2_lzo_dcd_hi(6) and ex2_lzo_dcd_lo(14) ); +u_lzo_dcd_110: ex2_lzo_dcd_b(110) <= not( ex2_lzo_dcd_hi(6) and ex2_lzo_dcd_lo(15) ); + +u_lzo_dcd_111: ex2_lzo_dcd_b(111) <= not( ex2_lzo_dcd_hi(7) and ex2_lzo_dcd_lo(0 ) ); +u_lzo_dcd_112: ex2_lzo_dcd_b(112) <= not( ex2_lzo_dcd_hi(7) and ex2_lzo_dcd_lo(1 ) ); +u_lzo_dcd_113: ex2_lzo_dcd_b(113) <= not( ex2_lzo_dcd_hi(7) and ex2_lzo_dcd_lo(2 ) ); +u_lzo_dcd_114: ex2_lzo_dcd_b(114) <= not( ex2_lzo_dcd_hi(7) and ex2_lzo_dcd_lo(3 ) ); +u_lzo_dcd_115: ex2_lzo_dcd_b(115) <= not( ex2_lzo_dcd_hi(7) and ex2_lzo_dcd_lo(4 ) ); +u_lzo_dcd_116: ex2_lzo_dcd_b(116) <= not( ex2_lzo_dcd_hi(7) and ex2_lzo_dcd_lo(5 ) ); +u_lzo_dcd_117: ex2_lzo_dcd_b(117) <= not( ex2_lzo_dcd_hi(7) and ex2_lzo_dcd_lo(6 ) ); +u_lzo_dcd_118: ex2_lzo_dcd_b(118) <= not( ex2_lzo_dcd_hi(7) and ex2_lzo_dcd_lo(7 ) ); +u_lzo_dcd_119: ex2_lzo_dcd_b(119) <= not( ex2_lzo_dcd_hi(7) and ex2_lzo_dcd_lo(8 ) ); +u_lzo_dcd_120: ex2_lzo_dcd_b(120) <= not( ex2_lzo_dcd_hi(7) and ex2_lzo_dcd_lo(9 ) ); +u_lzo_dcd_121: ex2_lzo_dcd_b(121) <= not( ex2_lzo_dcd_hi(7) and ex2_lzo_dcd_lo(10) ); +u_lzo_dcd_122: ex2_lzo_dcd_b(122) <= not( ex2_lzo_dcd_hi(7) and ex2_lzo_dcd_lo(11) ); +u_lzo_dcd_123: ex2_lzo_dcd_b(123) <= not( ex2_lzo_dcd_hi(7) and ex2_lzo_dcd_lo(12) ); +u_lzo_dcd_124: ex2_lzo_dcd_b(124) <= not( ex2_lzo_dcd_hi(7) and ex2_lzo_dcd_lo(13) ); +u_lzo_dcd_125: ex2_lzo_dcd_b(125) <= not( ex2_lzo_dcd_hi(7) and ex2_lzo_dcd_lo(14) ); +u_lzo_dcd_126: ex2_lzo_dcd_b(126) <= not( ex2_lzo_dcd_hi(7) and ex2_lzo_dcd_lo(15) ); + +u_lzo_dcd_127: ex2_lzo_dcd_b(127) <= not( ex2_lzo_dcd_hi(8) and ex2_lzo_dcd_lo(0 ) ); +u_lzo_dcd_128: ex2_lzo_dcd_b(128) <= not( ex2_lzo_dcd_hi(8) and ex2_lzo_dcd_lo(1 ) ); +u_lzo_dcd_129: ex2_lzo_dcd_b(129) <= not( ex2_lzo_dcd_hi(8) and ex2_lzo_dcd_lo(2 ) ); +u_lzo_dcd_130: ex2_lzo_dcd_b(130) <= not( ex2_lzo_dcd_hi(8) and ex2_lzo_dcd_lo(3 ) ); +u_lzo_dcd_131: ex2_lzo_dcd_b(131) <= not( ex2_lzo_dcd_hi(8) and ex2_lzo_dcd_lo(4 ) ); +u_lzo_dcd_132: ex2_lzo_dcd_b(132) <= not( ex2_lzo_dcd_hi(8) and ex2_lzo_dcd_lo(5 ) ); +u_lzo_dcd_133: ex2_lzo_dcd_b(133) <= not( ex2_lzo_dcd_hi(8) and ex2_lzo_dcd_lo(6 ) ); +u_lzo_dcd_134: ex2_lzo_dcd_b(134) <= not( ex2_lzo_dcd_hi(8) and ex2_lzo_dcd_lo(7 ) ); +u_lzo_dcd_135: ex2_lzo_dcd_b(135) <= not( ex2_lzo_dcd_hi(8) and ex2_lzo_dcd_lo(8 ) ); +u_lzo_dcd_136: ex2_lzo_dcd_b(136) <= not( ex2_lzo_dcd_hi(8) and ex2_lzo_dcd_lo(9 ) ); +u_lzo_dcd_137: ex2_lzo_dcd_b(137) <= not( ex2_lzo_dcd_hi(8) and ex2_lzo_dcd_lo(10) ); +u_lzo_dcd_138: ex2_lzo_dcd_b(138) <= not( ex2_lzo_dcd_hi(8) and ex2_lzo_dcd_lo(11) ); +u_lzo_dcd_139: ex2_lzo_dcd_b(139) <= not( ex2_lzo_dcd_hi(8) and ex2_lzo_dcd_lo(12) ); +u_lzo_dcd_140: ex2_lzo_dcd_b(140) <= not( ex2_lzo_dcd_hi(8) and ex2_lzo_dcd_lo(13) ); +u_lzo_dcd_141: ex2_lzo_dcd_b(141) <= not( ex2_lzo_dcd_hi(8) and ex2_lzo_dcd_lo(14) ); +u_lzo_dcd_142: ex2_lzo_dcd_b(142) <= not( ex2_lzo_dcd_hi(8) and ex2_lzo_dcd_lo(15) ); + +u_lzo_dcd_143: ex2_lzo_dcd_b(143) <= not( ex2_lzo_dcd_hi(9) and ex2_lzo_dcd_lo(0 ) ); +u_lzo_dcd_144: ex2_lzo_dcd_b(144) <= not( ex2_lzo_dcd_hi(9) and ex2_lzo_dcd_lo(1 ) ); +u_lzo_dcd_145: ex2_lzo_dcd_b(145) <= not( ex2_lzo_dcd_hi(9) and ex2_lzo_dcd_lo(2 ) ); +u_lzo_dcd_146: ex2_lzo_dcd_b(146) <= not( ex2_lzo_dcd_hi(9) and ex2_lzo_dcd_lo(3 ) ); +u_lzo_dcd_147: ex2_lzo_dcd_b(147) <= not( ex2_lzo_dcd_hi(9) and ex2_lzo_dcd_lo(4 ) ); +u_lzo_dcd_148: ex2_lzo_dcd_b(148) <= not( ex2_lzo_dcd_hi(9) and ex2_lzo_dcd_lo(5 ) ); +u_lzo_dcd_149: ex2_lzo_dcd_b(149) <= not( ex2_lzo_dcd_hi(9) and ex2_lzo_dcd_lo(6 ) ); +u_lzo_dcd_150: ex2_lzo_dcd_b(150) <= not( ex2_lzo_dcd_hi(9) and ex2_lzo_dcd_lo(7 ) ); +u_lzo_dcd_151: ex2_lzo_dcd_b(151) <= not( ex2_lzo_dcd_hi(9) and ex2_lzo_dcd_lo(8 ) ); +u_lzo_dcd_152: ex2_lzo_dcd_b(152) <= not( ex2_lzo_dcd_hi(9) and ex2_lzo_dcd_lo(9 ) ); +u_lzo_dcd_153: ex2_lzo_dcd_b(153) <= not( ex2_lzo_dcd_hi(9) and ex2_lzo_dcd_lo(10) ); +u_lzo_dcd_154: ex2_lzo_dcd_b(154) <= not( ex2_lzo_dcd_hi(9) and ex2_lzo_dcd_lo(11) ); +u_lzo_dcd_155: ex2_lzo_dcd_b(155) <= not( ex2_lzo_dcd_hi(9) and ex2_lzo_dcd_lo(12) ); +u_lzo_dcd_156: ex2_lzo_dcd_b(156) <= not( ex2_lzo_dcd_hi(9) and ex2_lzo_dcd_lo(13) ); +u_lzo_dcd_157: ex2_lzo_dcd_b(157) <= not( ex2_lzo_dcd_hi(9) and ex2_lzo_dcd_lo(14) ); +u_lzo_dcd_158: ex2_lzo_dcd_b(158) <= not( ex2_lzo_dcd_hi(9) and ex2_lzo_dcd_lo(15) ); + +u_lzo_dcd_159: ex2_lzo_dcd_b(159) <= not( ex2_lzo_dcd_hi(10) and ex2_lzo_dcd_lo(0) ); +u_lzo_dcd_160: ex2_lzo_dcd_b(160) <= not( ex2_lzo_dcd_hi(10) and ex2_lzo_dcd_lo(1) ); +u_lzo_dcd_161: ex2_lzo_dcd_b(161) <= not( ex2_lzo_dcd_hi(10) and ex2_lzo_dcd_lo(2) ); +u_lzo_dcd_162: ex2_lzo_dcd_b(162) <= not( ex2_lzo_dcd_hi(10) and ex2_lzo_dcd_lo(3) ); + + + +f_alg_ex2_sel_byp_b <= not( f_alg_ex2_sel_byp ); +ex2_lzo_nonbyp_0_b <= not( ex2_lzo_nonbyp_0 ); +ex2_lzo_forbyp_0_b <= not( ex2_lzo_forbyp_0 ); + + +u_lzo_din_0: f_lze_ex2_lzo_din( 0) <= not( ( f_alg_ex2_sel_byp or ex2_lzo_nonbyp_0_b ) and -- neg input and/or + ( f_alg_ex2_sel_byp_b or ex2_lzo_forbyp_0_b ) ); +u_lzo_din_1: f_lze_ex2_lzo_din( 1) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(1) ); -- neg input and -- +u_lzo_din_2: f_lze_ex2_lzo_din( 2) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(2) ); -- neg input and -- +u_lzo_din_3: f_lze_ex2_lzo_din( 3) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(3) ); -- neg input and -- +u_lzo_din_4: f_lze_ex2_lzo_din( 4) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(4) ); -- neg input and -- +u_lzo_din_5: f_lze_ex2_lzo_din( 5) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(5) ); -- neg input and -- +u_lzo_din_6: f_lze_ex2_lzo_din( 6) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(6) ); -- neg input and -- +u_lzo_din_7: f_lze_ex2_lzo_din( 7) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(7) ); -- neg input and -- +u_lzo_din_8: f_lze_ex2_lzo_din( 8) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(8) ); -- neg input and -- +u_lzo_din_9: f_lze_ex2_lzo_din( 9) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(9) ); -- neg input and -- +u_lzo_din_10: f_lze_ex2_lzo_din( 10) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(10) ); -- neg input and -- +u_lzo_din_11: f_lze_ex2_lzo_din( 11) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(11) ); -- neg input and -- +u_lzo_din_12: f_lze_ex2_lzo_din( 12) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(12) ); -- neg input and -- +u_lzo_din_13: f_lze_ex2_lzo_din( 13) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(13) ); -- neg input and -- +u_lzo_din_14: f_lze_ex2_lzo_din( 14) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(14) ); -- neg input and -- +u_lzo_din_15: f_lze_ex2_lzo_din( 15) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(15) ); -- neg input and -- +u_lzo_din_16: f_lze_ex2_lzo_din( 16) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(16) ); -- neg input and -- +u_lzo_din_17: f_lze_ex2_lzo_din( 17) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(17) ); -- neg input and -- +u_lzo_din_18: f_lze_ex2_lzo_din( 18) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(18) ); -- neg input and -- +u_lzo_din_19: f_lze_ex2_lzo_din( 19) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(19) ); -- neg input and -- +u_lzo_din_20: f_lze_ex2_lzo_din( 20) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(20) ); -- neg input and -- +u_lzo_din_21: f_lze_ex2_lzo_din( 21) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(21) ); -- neg input and -- +u_lzo_din_22: f_lze_ex2_lzo_din( 22) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(22) ); -- neg input and -- +u_lzo_din_23: f_lze_ex2_lzo_din( 23) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(23) ); -- neg input and -- +u_lzo_din_24: f_lze_ex2_lzo_din( 24) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(24) ); -- neg input and -- +u_lzo_din_25: f_lze_ex2_lzo_din( 25) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(25) ); -- neg input and -- +u_lzo_din_26: f_lze_ex2_lzo_din( 26) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(26) ); -- neg input and -- +u_lzo_din_27: f_lze_ex2_lzo_din( 27) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(27) ); -- neg input and -- +u_lzo_din_28: f_lze_ex2_lzo_din( 28) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(28) ); -- neg input and -- +u_lzo_din_29: f_lze_ex2_lzo_din( 29) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(29) ); -- neg input and -- +u_lzo_din_30: f_lze_ex2_lzo_din( 30) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(30) ); -- neg input and -- +u_lzo_din_31: f_lze_ex2_lzo_din( 31) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(31) ); -- neg input and -- +u_lzo_din_32: f_lze_ex2_lzo_din( 32) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(32) ); -- neg input and -- +u_lzo_din_33: f_lze_ex2_lzo_din( 33) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(33) ); -- neg input and -- +u_lzo_din_34: f_lze_ex2_lzo_din( 34) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(34) ); -- neg input and -- +u_lzo_din_35: f_lze_ex2_lzo_din( 35) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(35) ); -- neg input and -- +u_lzo_din_36: f_lze_ex2_lzo_din( 36) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(36) ); -- neg input and -- +u_lzo_din_37: f_lze_ex2_lzo_din( 37) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(37) ); -- neg input and -- +u_lzo_din_38: f_lze_ex2_lzo_din( 38) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(38) ); -- neg input and -- +u_lzo_din_39: f_lze_ex2_lzo_din( 39) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(39) ); -- neg input and -- +u_lzo_din_40: f_lze_ex2_lzo_din( 40) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(40) ); -- neg input and -- +u_lzo_din_41: f_lze_ex2_lzo_din( 41) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(41) ); -- neg input and -- +u_lzo_din_42: f_lze_ex2_lzo_din( 42) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(42) ); -- neg input and -- +u_lzo_din_43: f_lze_ex2_lzo_din( 43) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(43) ); -- neg input and -- +u_lzo_din_44: f_lze_ex2_lzo_din( 44) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(44) ); -- neg input and -- +u_lzo_din_45: f_lze_ex2_lzo_din( 45) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(45) ); -- neg input and -- +u_lzo_din_46: f_lze_ex2_lzo_din( 46) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(46) ); -- neg input and -- +u_lzo_din_47: f_lze_ex2_lzo_din( 47) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(47) ); -- neg input and -- +u_lzo_din_48: f_lze_ex2_lzo_din( 48) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(48) ); -- neg input and -- +u_lzo_din_49: f_lze_ex2_lzo_din( 49) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(49) ); -- neg input and -- +u_lzo_din_50: f_lze_ex2_lzo_din( 50) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(50) ); -- neg input and -- +u_lzo_din_51: f_lze_ex2_lzo_din( 51) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(51) ); -- neg input and -- +u_lzo_din_52: f_lze_ex2_lzo_din( 52) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(52) ); -- neg input and -- +u_lzo_din_53: f_lze_ex2_lzo_din( 53) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(53) ); -- neg input and -- +u_lzo_din_54: f_lze_ex2_lzo_din( 54) <= not( f_alg_ex2_sel_byp or ex2_lzo_dcd_b(54) ); -- neg input and -- +u_lzo_din_55: f_lze_ex2_lzo_din( 55) <= not ex2_lzo_dcd_b(55) ; +u_lzo_din_56: f_lze_ex2_lzo_din( 56) <= not ex2_lzo_dcd_b(56) ; +u_lzo_din_57: f_lze_ex2_lzo_din( 57) <= not ex2_lzo_dcd_b(57) ; +u_lzo_din_58: f_lze_ex2_lzo_din( 58) <= not ex2_lzo_dcd_b(58) ; +u_lzo_din_59: f_lze_ex2_lzo_din( 59) <= not ex2_lzo_dcd_b(59) ; +u_lzo_din_60: f_lze_ex2_lzo_din( 60) <= not ex2_lzo_dcd_b(60) ; +u_lzo_din_61: f_lze_ex2_lzo_din( 61) <= not ex2_lzo_dcd_b(61) ; +u_lzo_din_62: f_lze_ex2_lzo_din( 62) <= not ex2_lzo_dcd_b(62) ; +u_lzo_din_63: f_lze_ex2_lzo_din( 63) <= not ex2_lzo_dcd_b(63) ; +u_lzo_din_64: f_lze_ex2_lzo_din( 64) <= not ex2_lzo_dcd_b(64) ; +u_lzo_din_65: f_lze_ex2_lzo_din( 65) <= not ex2_lzo_dcd_b(65) ; +u_lzo_din_66: f_lze_ex2_lzo_din( 66) <= not ex2_lzo_dcd_b(66) ; +u_lzo_din_67: f_lze_ex2_lzo_din( 67) <= not ex2_lzo_dcd_b(67) ; +u_lzo_din_68: f_lze_ex2_lzo_din( 68) <= not ex2_lzo_dcd_b(68) ; +u_lzo_din_69: f_lze_ex2_lzo_din( 69) <= not ex2_lzo_dcd_b(69) ; +u_lzo_din_70: f_lze_ex2_lzo_din( 70) <= not ex2_lzo_dcd_b(70) ; +u_lzo_din_71: f_lze_ex2_lzo_din( 71) <= not ex2_lzo_dcd_b(71) ; +u_lzo_din_72: f_lze_ex2_lzo_din( 72) <= not ex2_lzo_dcd_b(72) ; +u_lzo_din_73: f_lze_ex2_lzo_din( 73) <= not ex2_lzo_dcd_b(73) ; +u_lzo_din_74: f_lze_ex2_lzo_din( 74) <= not ex2_lzo_dcd_b(74) ; +u_lzo_din_75: f_lze_ex2_lzo_din( 75) <= not ex2_lzo_dcd_b(75) ; +u_lzo_din_76: f_lze_ex2_lzo_din( 76) <= not ex2_lzo_dcd_b(76) ; +u_lzo_din_77: f_lze_ex2_lzo_din( 77) <= not ex2_lzo_dcd_b(77) ; +u_lzo_din_78: f_lze_ex2_lzo_din( 78) <= not ex2_lzo_dcd_b(78) ; +u_lzo_din_79: f_lze_ex2_lzo_din( 79) <= not ex2_lzo_dcd_b(79) ; +u_lzo_din_80: f_lze_ex2_lzo_din( 80) <= not ex2_lzo_dcd_b(80) ; +u_lzo_din_81: f_lze_ex2_lzo_din( 81) <= not ex2_lzo_dcd_b(81) ; +u_lzo_din_82: f_lze_ex2_lzo_din( 82) <= not ex2_lzo_dcd_b(82) ; +u_lzo_din_83: f_lze_ex2_lzo_din( 83) <= not ex2_lzo_dcd_b(83) ; +u_lzo_din_84: f_lze_ex2_lzo_din( 84) <= not ex2_lzo_dcd_b(84) ; +u_lzo_din_85: f_lze_ex2_lzo_din( 85) <= not ex2_lzo_dcd_b(85) ; +u_lzo_din_86: f_lze_ex2_lzo_din( 86) <= not ex2_lzo_dcd_b(86) ; +u_lzo_din_87: f_lze_ex2_lzo_din( 87) <= not ex2_lzo_dcd_b(87) ; +u_lzo_din_88: f_lze_ex2_lzo_din( 88) <= not ex2_lzo_dcd_b(88) ; +u_lzo_din_89: f_lze_ex2_lzo_din( 89) <= not ex2_lzo_dcd_b(89) ; +u_lzo_din_90: f_lze_ex2_lzo_din( 90) <= not ex2_lzo_dcd_b(90) ; +u_lzo_din_91: f_lze_ex2_lzo_din( 91) <= not ex2_lzo_dcd_b(91) ; +u_lzo_din_92: f_lze_ex2_lzo_din( 92) <= not ex2_lzo_dcd_b(92) ; +u_lzo_din_93: f_lze_ex2_lzo_din( 93) <= not ex2_lzo_dcd_b(93) ; +u_lzo_din_94: f_lze_ex2_lzo_din( 94) <= not ex2_lzo_dcd_b(94) ; +u_lzo_din_95: f_lze_ex2_lzo_din( 95) <= not ex2_lzo_dcd_b(95) ; +u_lzo_din_96: f_lze_ex2_lzo_din( 96) <= not ex2_lzo_dcd_b(96) ; +u_lzo_din_97: f_lze_ex2_lzo_din( 97) <= not ex2_lzo_dcd_b(97) ; +u_lzo_din_98: f_lze_ex2_lzo_din( 98) <= not ex2_lzo_dcd_b(98) ; +u_lzo_din_99: f_lze_ex2_lzo_din( 99) <= not(ex2_lzo_dcd_b(99) and not f_pic_ex2_to_integer ); +u_lzo_din_100: f_lze_ex2_lzo_din(100) <= not ex2_lzo_dcd_b(100) ; +u_lzo_din_101: f_lze_ex2_lzo_din(101) <= not ex2_lzo_dcd_b(101) ; +u_lzo_din_102: f_lze_ex2_lzo_din(102) <= not ex2_lzo_dcd_b(102) ; +u_lzo_din_103: f_lze_ex2_lzo_din(103) <= not ex2_lzo_dcd_b(103) ; +u_lzo_din_104: f_lze_ex2_lzo_din(104) <= not ex2_lzo_dcd_b(104) ; +u_lzo_din_105: f_lze_ex2_lzo_din(105) <= not ex2_lzo_dcd_b(105) ; +u_lzo_din_106: f_lze_ex2_lzo_din(106) <= not ex2_lzo_dcd_b(106) ; +u_lzo_din_107: f_lze_ex2_lzo_din(107) <= not ex2_lzo_dcd_b(107) ; +u_lzo_din_108: f_lze_ex2_lzo_din(108) <= not ex2_lzo_dcd_b(108) ; +u_lzo_din_109: f_lze_ex2_lzo_din(109) <= not ex2_lzo_dcd_b(109) ; +u_lzo_din_110: f_lze_ex2_lzo_din(110) <= not ex2_lzo_dcd_b(110) ; +u_lzo_din_111: f_lze_ex2_lzo_din(111) <= not ex2_lzo_dcd_b(111) ; +u_lzo_din_112: f_lze_ex2_lzo_din(112) <= not ex2_lzo_dcd_b(112) ; +u_lzo_din_113: f_lze_ex2_lzo_din(113) <= not ex2_lzo_dcd_b(113) ; +u_lzo_din_114: f_lze_ex2_lzo_din(114) <= not ex2_lzo_dcd_b(114) ; +u_lzo_din_115: f_lze_ex2_lzo_din(115) <= not ex2_lzo_dcd_b(115) ; +u_lzo_din_116: f_lze_ex2_lzo_din(116) <= not ex2_lzo_dcd_b(116) ; +u_lzo_din_117: f_lze_ex2_lzo_din(117) <= not ex2_lzo_dcd_b(117) ; +u_lzo_din_118: f_lze_ex2_lzo_din(118) <= not ex2_lzo_dcd_b(118) ; +u_lzo_din_119: f_lze_ex2_lzo_din(119) <= not ex2_lzo_dcd_b(119) ; +u_lzo_din_120: f_lze_ex2_lzo_din(120) <= not ex2_lzo_dcd_b(120) ; +u_lzo_din_121: f_lze_ex2_lzo_din(121) <= not ex2_lzo_dcd_b(121) ; +u_lzo_din_122: f_lze_ex2_lzo_din(122) <= not ex2_lzo_dcd_b(122) ; +u_lzo_din_123: f_lze_ex2_lzo_din(123) <= not ex2_lzo_dcd_b(123) ; +u_lzo_din_124: f_lze_ex2_lzo_din(124) <= not ex2_lzo_dcd_b(124) ; +u_lzo_din_125: f_lze_ex2_lzo_din(125) <= not ex2_lzo_dcd_b(125) ; +u_lzo_din_126: f_lze_ex2_lzo_din(126) <= not ex2_lzo_dcd_b(126) ; +u_lzo_din_127: f_lze_ex2_lzo_din(127) <= not ex2_lzo_dcd_b(127) ; +u_lzo_din_128: f_lze_ex2_lzo_din(128) <= not ex2_lzo_dcd_b(128) ; +u_lzo_din_129: f_lze_ex2_lzo_din(129) <= not ex2_lzo_dcd_b(129) ; +u_lzo_din_130: f_lze_ex2_lzo_din(130) <= not ex2_lzo_dcd_b(130) ; +u_lzo_din_131: f_lze_ex2_lzo_din(131) <= not ex2_lzo_dcd_b(131) ; +u_lzo_din_132: f_lze_ex2_lzo_din(132) <= not ex2_lzo_dcd_b(132) ; +u_lzo_din_133: f_lze_ex2_lzo_din(133) <= not ex2_lzo_dcd_b(133) ; +u_lzo_din_134: f_lze_ex2_lzo_din(134) <= not ex2_lzo_dcd_b(134) ; +u_lzo_din_135: f_lze_ex2_lzo_din(135) <= not ex2_lzo_dcd_b(135) ; +u_lzo_din_136: f_lze_ex2_lzo_din(136) <= not ex2_lzo_dcd_b(136) ; +u_lzo_din_137: f_lze_ex2_lzo_din(137) <= not ex2_lzo_dcd_b(137) ; +u_lzo_din_138: f_lze_ex2_lzo_din(138) <= not ex2_lzo_dcd_b(138) ; +u_lzo_din_139: f_lze_ex2_lzo_din(139) <= not ex2_lzo_dcd_b(139) ; +u_lzo_din_140: f_lze_ex2_lzo_din(140) <= not ex2_lzo_dcd_b(140) ; +u_lzo_din_141: f_lze_ex2_lzo_din(141) <= not ex2_lzo_dcd_b(141) ; +u_lzo_din_142: f_lze_ex2_lzo_din(142) <= not ex2_lzo_dcd_b(142) ; +u_lzo_din_143: f_lze_ex2_lzo_din(143) <= not ex2_lzo_dcd_b(143) ; +u_lzo_din_144: f_lze_ex2_lzo_din(144) <= not ex2_lzo_dcd_b(144) ; +u_lzo_din_145: f_lze_ex2_lzo_din(145) <= not ex2_lzo_dcd_b(145) ; +u_lzo_din_146: f_lze_ex2_lzo_din(146) <= not ex2_lzo_dcd_b(146) ; +u_lzo_din_147: f_lze_ex2_lzo_din(147) <= not ex2_lzo_dcd_b(147) ; +u_lzo_din_148: f_lze_ex2_lzo_din(148) <= not ex2_lzo_dcd_b(148) ; +u_lzo_din_149: f_lze_ex2_lzo_din(149) <= not ex2_lzo_dcd_b(149) ; +u_lzo_din_150: f_lze_ex2_lzo_din(150) <= not ex2_lzo_dcd_b(150) ; +u_lzo_din_151: f_lze_ex2_lzo_din(151) <= not ex2_lzo_dcd_b(151) ; +u_lzo_din_152: f_lze_ex2_lzo_din(152) <= not ex2_lzo_dcd_b(152) ; +u_lzo_din_153: f_lze_ex2_lzo_din(153) <= not ex2_lzo_dcd_b(153) ; +u_lzo_din_154: f_lze_ex2_lzo_din(154) <= not ex2_lzo_dcd_b(154) ; +u_lzo_din_155: f_lze_ex2_lzo_din(155) <= not ex2_lzo_dcd_b(155) ; +u_lzo_din_156: f_lze_ex2_lzo_din(156) <= not ex2_lzo_dcd_b(156) ; +u_lzo_din_157: f_lze_ex2_lzo_din(157) <= not ex2_lzo_dcd_b(157) ; +u_lzo_din_158: f_lze_ex2_lzo_din(158) <= not ex2_lzo_dcd_b(158) ; +u_lzo_din_159: f_lze_ex2_lzo_din(159) <= not ex2_lzo_dcd_b(159) ; +u_lzo_din_160: f_lze_ex2_lzo_din(160) <= not ex2_lzo_dcd_b(160) ; +u_lzo_din_161: f_lze_ex2_lzo_din(161) <= not ex2_lzo_dcd_b(161) ; +u_lzo_din_162: f_lze_ex2_lzo_din(162) <= not ex2_lzo_dcd_b(162) ; + + + + + + ex2_ins_est <= f_pic_ex2_est_recip or f_pic_ex2_est_rsqrt ; + + ex2_sh_rgt_en_by <= -- set LZO[0] so can just OR into result + ( f_eie_ex2_use_bexp and ex2_expo_neg_sp_by and ex2_lzo_cont_sp and not f_alg_ex2_byp_nonflip and not ex2_ins_est) or + ( f_eie_ex2_use_bexp and ex2_expo_neg_dp_by and ex2_lzo_cont_dp and not f_alg_ex2_byp_nonflip and not ex2_ins_est) ; + ex2_sh_rgt_en_p <= -- set LZO[0] so can just OR into result + (not f_eie_ex2_use_bexp and ex2_expo_neg_sp and ex2_lzo_cont_sp and not f_alg_ex2_byp_nonflip) or + (not f_eie_ex2_use_bexp and ex2_expo_neg_dp and ex2_lzo_cont_dp and not f_alg_ex2_byp_nonflip) ; + + ex2_sh_rgt_en <= ex2_sh_rgt_en_by or ex2_sh_rgt_en_p; + +--//---------------------------------------------------------------------------------------------- +--// you might be thinking that the shift right amount needs a limiter (so that amounts > 64 +--// do not wrap a round and leave bits in the result when the result should be zero). +--// (1) if the shift amount belongs to the "B" operand, (bypass) and since we only shift right +--// when B is a denorm (it has a bit on) then the maximum shift right is (52) because +--// the smallest b exponent (expo min) after prenorm is -52. +--// there is the possibility that a divide could create an artificially small Bexpo. +--// if that is true the shift right amount should be zero (right 64 followed by left 0). +--// (2) otherwise the right shift amount comes from the product exponent. +--// the product exponent could be very small, however for a multiply add if it becomes +--// too small then the exponent will come from the addend, so no problem. +--// a multiply instruction does not have an addend, and it could have a very small exponent. +--// BUT, the lead bit is at [55] and even if the shift right goes right 64 followed by left 64, +--// it will not but a bit into the result or guard fields. +--//----------------------------------------------------------------------------------------------- + + -- calculate shift right amount (DP) ... expo must be correct value to subtract in expo logic + -- decode = 0 shift right 1 -(-1) for expo 0_0000_0000_0000 -> 1_1111_1111_1111 -x = !x + 1, !x = -x - 1 + -- decode = -1 shift right 2 -(-2) for expo 0_0000_0000_0001 -> 1_1111_1111_1110 + -- decode = -2 shift right 3 -(-3) for expo 0_0000_0000_0010 -> 1_1111_1111_1101 + -- + -- max = -53 0_0000_0011_0101 -> 1_1111_1100_1010 + -- * **** **dd_dddd + + -- calculate shift right amount (SP) + -- decode = x380 shift right 1 -(-1) for expo 0_0011_1000_0000 -> 1_1100_0111_1111 -x = !x + 1, !x = -x - 1 + -- decode = x37F shift right 2 -(-2) for expo 0_0011_1000_0001 -> 1_1100_0111_1110 + -- decode = x37E shift right 3 -(-3) for expo 0_0011_1000_0010 -> 1_1100_0111_1101 + -- * **** **dd_dddd + + -- expo = Bexpo - lza + -- Bexpo + (!lza) ... lza is usually sign extended and inverted to make a negative number, + -- Bexpo must be added to in denorm cases + -- Make lza a negative number, so that when it is flipped it becomes a positive number. + -- + -- expo_adj + -- expo = x380 896 0_0011_1000_0000 1 -( 1) 1111_1111 + -- expo = x37f 895 0_0011_0111_1111 2 -( 2) 1111_1110 + -- expo = x37e 894 0_0011_0111_1110 3 1111_1101 + -- expo = x37d 893 0_0011_0111_1101 4 1111_1100 + -- expo = x37c 892 0_0011_0111_1100 5 + -- expo = x37b 891 0_0011_0111_1011 6 + -- expo = x37a 890 0_0011_0111_1010 7 + -- expo = x379 889 0_0011_0111_1001 8 + -- expo = x378 888 0_0011_0111_1000 9 + -- expo = x377 887 0_0011_0111_0111 10 + -- expo = x376 886 0_0011_0111_0110 11 + -- expo = x375 885 0_0011_0111_0101 12 + -- expo = x374 884 0_0011_0111_0100 13 + -- expo = x373 883 0_0011_0111_0011 14 + -- expo = x372 882 0_0011_0111_0010 15 + -- expo = x371 881 0_0011_0111_0001 16 + -- expo = x370 880 0_0011_0111_0000 17 + -- expo = x36f 879 0_0011_0110_1111 18 + -- expo = x36e 878 0_0011_0110_1110 19 + -- expo = x36d 877 0_0011_0110_1101 20 + -- expo = x36c 876 0_0011_0110_1100 21 + -- expo = x36b 875 0_0011_0110_1011 22 + -- expo = x36a 874 0_0011_0110_1010 23 -(23) 1110_1001 + ------------------------------- + -- expo = x369 873 0_0011_0110_1001 24 -(24) 1110_1000 + + + + +-- if p_exp an be more neg then -63 , then this needs to be detected and shAmt forced to a const. + + ex2_expo_p_sim_p(8 to 13) <= not ex2_expo(8 to 13); + + ex2_expo_p_sim_g(13) <= ex2_expo(13) ; + ex2_expo_p_sim_g(12) <= ex2_expo(13) or ex2_expo(12) ; + ex2_expo_p_sim_g(11) <= ex2_expo(13) or ex2_expo(12) or ex2_expo(11) ; + ex2_expo_p_sim_g(10) <= ex2_expo(13) or ex2_expo(12) or ex2_expo(11) or ex2_expo(10) ; + ex2_expo_p_sim_g( 9) <= ex2_expo(13) or ex2_expo(12) or ex2_expo(11) or ex2_expo(10) or ex2_expo( 9) ; + + ex2_expo_p_sim(13) <= ex2_expo_p_sim_p(13) ; + ex2_expo_p_sim(12) <= ex2_expo_p_sim_p(12) xor ( ex2_expo_p_sim_g(13) ) ; + ex2_expo_p_sim(11) <= ex2_expo_p_sim_p(11) xor ( ex2_expo_p_sim_g(12) ) ; + ex2_expo_p_sim(10) <= ex2_expo_p_sim_p(10) xor ( ex2_expo_p_sim_g(11) ) ; + ex2_expo_p_sim( 9) <= ex2_expo_p_sim_p( 9) xor ( ex2_expo_p_sim_g(10) ) ; + ex2_expo_p_sim( 8) <= ex2_expo_p_sim_p( 8) xor ( ex2_expo_p_sim_g( 9) ); + + + + + ex2_expo_sim_p(8 to 13) <= not ex2_expo_by(8 to 13); + + ex2_expo_sim_g(13) <= ex2_expo_by(13) ; + ex2_expo_sim_g(12) <= ex2_expo_by(13) or ex2_expo_by(12) ; + ex2_expo_sim_g(11) <= ex2_expo_by(13) or ex2_expo_by(12) or ex2_expo_by(11) ; + ex2_expo_sim_g(10) <= ex2_expo_by(13) or ex2_expo_by(12) or ex2_expo_by(11) or ex2_expo_by(10) ; + ex2_expo_sim_g( 9) <= ex2_expo_by(13) or ex2_expo_by(12) or ex2_expo_by(11) or ex2_expo_by(10) or ex2_expo_by( 9) ; + + ex2_expo_sim(13) <= ex2_expo_sim_p(13) ; + ex2_expo_sim(12) <= ex2_expo_sim_p(12) xor ( ex2_expo_sim_g(13) ) ; + ex2_expo_sim(11) <= ex2_expo_sim_p(11) xor ( ex2_expo_sim_g(12) ) ; + ex2_expo_sim(10) <= ex2_expo_sim_p(10) xor ( ex2_expo_sim_g(11) ) ; + ex2_expo_sim( 9) <= ex2_expo_sim_p( 9) xor ( ex2_expo_sim_g(10) ) ; + ex2_expo_sim( 8) <= ex2_expo_sim_p( 8) xor ( ex2_expo_sim_g( 9) ); + + + + ex2_lzo_forbyp_0 <= + ( f_pic_ex2_est_recip ) or -- could include these in lzo dis + ( f_pic_ex2_est_rsqrt ) or -- could include these in lzo_dis + ( f_alg_ex2_byp_nonflip and not f_pic_ex2_prenorm ) or + (not f_fmt_ex2_pass_msb_dp and not f_pic_ex2_lzo_dis_prod ) or -- allow norm to decr MSB then renormalize + ( (ex2_expo_neg_dp_by or ex2_dp_001_by) and ex2_lzo_cont_dp ) or + ( (ex2_expo_neg_sp_by or ex2_sp_001_by) and ex2_lzo_cont_sp ) ; + + + + + + ex2_lzo_nonbyp_0 <= ( ex2_lzo_dcd_0 ) or + ( ex2_expo_neg_dp and ex2_lzo_cont_dp) or + ( ex2_expo_neg_sp and ex2_lzo_cont_sp) or + ( f_pic_ex2_est_recip ) or + ( f_pic_ex2_est_rsqrt ) ; + + + + ex2_sh_rgt_amt(0) <= ex2_sh_rgt_en ;-- huge shift right should give "0" + ex2_sh_rgt_amt(1) <= ex2_sh_rgt_en ;-- huge shift right should give "0" + ex2_sh_rgt_amt(2) <= (ex2_sh_rgt_en_p and ex2_expo_p_sim( 8)) or (ex2_sh_rgt_en_by and ex2_expo_sim( 8)); + ex2_sh_rgt_amt(3) <= (ex2_sh_rgt_en_p and ex2_expo_p_sim( 9)) or (ex2_sh_rgt_en_by and ex2_expo_sim( 9)); + ex2_sh_rgt_amt(4) <= (ex2_sh_rgt_en_p and ex2_expo_p_sim(10)) or (ex2_sh_rgt_en_by and ex2_expo_sim(10)); + ex2_sh_rgt_amt(5) <= (ex2_sh_rgt_en_p and ex2_expo_p_sim(11)) or (ex2_sh_rgt_en_by and ex2_expo_sim(11)); + ex2_sh_rgt_amt(6) <= (ex2_sh_rgt_en_p and ex2_expo_p_sim(12)) or (ex2_sh_rgt_en_by and ex2_expo_sim(12)); + ex2_sh_rgt_amt(7) <= (ex2_sh_rgt_en_p and ex2_expo_p_sim(13)) or (ex2_sh_rgt_en_by and ex2_expo_sim(13)); + + +-- bit_to_set |------ b_expo ----------| +-- 0 897 x381 0_0011_1000_0001 <== all normal SP numbers go here +-- 1 896 x380 0_0011_1000_0000 +-- 2 895 x37f 0_0011_0111_1111 +-- 3 894 x37e 0_0011_0111_1110 +-- 4 893 x37d 0_0011_0111_1101 +-- 5 892 x37c 0_0011_0111_1100 +-- 6 891 x37b 0_0011_0111_1011 +-- 7 890 x37a 0_0011_0111_1010 +-- 8 889 x379 0_0011_0111_1001 +-- 9 888 x378 0_0011_0111_1000 +-- 10 887 x377 0_0011_0111_0111 +-- 11 886 x376 0_0011_0111_0110 +-- 12 885 x375 0_0011_0111_0101 +-- 13 884 x374 0_0011_0111_0100 expo = (884 +26 -13) = 884 + 13 = 897 +-- 14 883 x373 0_0011_0111_0011 +-- 15 882 x372 0_0011_0111_0010 +-- 16 881 x371 0_0011_0111_0001 +-- 17 880 x370 0_0011_0111_0000 +-- 18 879 x36f 0_0011_0011_1111 +-- 19 878 x36e 0_0011_0011_1110 +-- 20 877 x36d 0_0011_0011_1101 +-- 21 876 x36c 0_0011_0011_1100 +-- 22 875 x36b 0_0011_0011_1011 +-- 23 874 x36a 0_0011_0011_1010 +-- ----------------------------------------- +-- 24 873 x369 0_0011_0011_1001 <=== if this or smaller do nothing (special case sp invalid) +-- + +---=############################################################### +---=## ex3 latches +---=############################################################### + + ex3_shr_lat: tri_rlmreg_p generic map (width=> 9, expand_type => expand_type, needs_sreset => 0) port map ( + forcee => forcee,-- tidn, + delay_lclkr => delay_lclkr(3) ,-- tidn, + mpw1_b => mpw1_b(3) ,-- tidn, + mpw2_b => mpw2_b(0) ,-- tidn, + vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_act, + thold_b => thold_0_b, + sg => sg_0, + scout => ex3_shr_so , + scin => ex3_shr_si , + ------------------- + din(0 to 7) => ex2_sh_rgt_amt(0 to 7), + din(8) => ex2_sh_rgt_en , + ------------------- + dout(0 to 7) => ex3_sh_rgt_amt(0 to 7), + dout(8) => ex3_sh_rgt_en ); + + + + f_lze_ex3_sh_rgt_amt(0 to 7) <= ex3_sh_rgt_amt(0 to 7) ; --OUTPUT-- + f_lze_ex3_sh_rgt_en <= ex3_sh_rgt_en ; --OUTPUT-- + + +---=############################################################### +---= scan string +---=############################################################### + + ex3_shr_si(0 to 8) <= ex3_shr_so(1 to 8) & f_lze_si ; + act_si (0 to 4) <= act_so (1 to 4) & ex3_shr_so(0); + f_lze_so <= act_so(0); + + + +end; -- fuq_lze ARCHITECTURE diff --git a/rel/src/vhdl/work/fuq_mad.vhdl b/rel/src/vhdl/work/fuq_mad.vhdl new file mode 100644 index 0000000..705e81a --- /dev/null +++ b/rel/src/vhdl/work/fuq_mad.vhdl @@ -0,0 +1,1802 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + + + library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + +entity fuq_mad is +generic( + expand_type : integer := 2 ); -- 0 - ibm tech, 1 - other ); +port ( + f_dcd_ex6_cancel :in std_ulogic; + + f_dcd_rf1_bypsel_a_res0 :in std_ulogic; + f_dcd_rf1_bypsel_a_res1 :in std_ulogic; + f_dcd_rf1_bypsel_a_load0 :in std_ulogic; + f_dcd_rf1_bypsel_a_load1 :in std_ulogic; + f_dcd_rf1_bypsel_b_res0 :in std_ulogic; + f_dcd_rf1_bypsel_b_res1 :in std_ulogic; + f_dcd_rf1_bypsel_b_load0 :in std_ulogic; + f_dcd_rf1_bypsel_b_load1 :in std_ulogic; + f_dcd_rf1_bypsel_c_res0 :in std_ulogic; + f_dcd_rf1_bypsel_c_res1 :in std_ulogic; + f_dcd_rf1_bypsel_c_load0 :in std_ulogic; + f_dcd_rf1_bypsel_c_load1 :in std_ulogic; + f_fpr_ex7_frt_sign :in std_ulogic ; + f_fpr_ex7_frt_expo :in std_ulogic_vector (1 to 13); + f_fpr_ex7_frt_frac :in std_ulogic_vector (0 to 52); + f_fpr_ex7_load_sign :in std_ulogic ; + f_fpr_ex7_load_expo :in std_ulogic_vector (3 to 13); + f_fpr_ex7_load_frac :in std_ulogic_vector (0 to 52); + ---------------------------------------------------------------------------- + f_fpr_ex6_load_sign :in std_ulogic; + f_fpr_ex6_load_expo :in std_ulogic_vector(3 to 13); + f_fpr_ex6_load_frac :in std_ulogic_vector(0 to 52); + f_fpr_rf1_a_sign :in std_ulogic; + f_fpr_rf1_a_expo :in std_ulogic_vector(1 to 13) ; + f_fpr_rf1_a_frac :in std_ulogic_vector(0 to 52) ; + f_fpr_ex1_a_par :in std_ulogic_vector(0 to 7); + + f_fpr_rf1_c_sign :in std_ulogic; + f_fpr_rf1_c_expo :in std_ulogic_vector(1 to 13) ; + f_fpr_rf1_c_frac :in std_ulogic_vector(0 to 52) ; + f_fpr_ex1_c_par :in std_ulogic_vector(0 to 7); + + f_fpr_rf1_b_sign :in std_ulogic; + f_fpr_rf1_b_expo :in std_ulogic_vector(1 to 13) ; + f_fpr_rf1_b_frac :in std_ulogic_vector(0 to 52) ; + f_fpr_ex1_b_par :in std_ulogic_vector(0 to 7); + + ---------------------------------------------------------------------------- + f_dcd_rf1_aop_valid :in std_ulogic; + f_dcd_rf1_cop_valid :in std_ulogic; + f_dcd_rf1_bop_valid :in std_ulogic; + f_dcd_rf1_sp :in std_ulogic; -- off for frsp + f_dcd_rf1_emin_dp :in std_ulogic; -- prenorm_dp + f_dcd_rf1_emin_sp :in std_ulogic; -- prenorm_sp, frsp + f_dcd_rf1_force_pass_b :in std_ulogic; -- fmr,fnabbs,fabs,fneg,mtfsf + + f_dcd_rf1_fsel_b :in std_ulogic; -- fsel + f_dcd_rf1_from_integer_b :in std_ulogic; -- fcfid (signed integer) + f_dcd_rf1_to_integer_b :in std_ulogic; -- fcti* (signed integer 32/64) + f_dcd_rf1_rnd_to_int_b :in std_ulogic; -- fri* + f_dcd_rf1_math_b :in std_ulogic; -- fmul,fmad,fmsub,fadd,fsub,fnmsub,fnmadd + f_dcd_rf1_est_recip_b :in std_ulogic; -- fres + f_dcd_rf1_est_rsqrt_b :in std_ulogic; -- frsqrte + f_dcd_rf1_move_b :in std_ulogic; -- fmr,fneg,fabs,fnabs + f_dcd_rf1_prenorm_b :in std_ulogic; -- prenorm ?? need + f_dcd_rf1_frsp_b :in std_ulogic; -- round-to-single-precision ?? need + f_dcd_rf1_compare_b :in std_ulogic; -- fcomp* + f_dcd_rf1_ordered_b :in std_ulogic; -- fcompo + + f_dcd_rf1_pow2e_b :in std_ulogic; -- pow2e sp, den==>0 + f_dcd_rf1_log2e_b :in std_ulogic; -- log2e sp, den==>0 + + f_dcd_rf1_ftdiv :in std_ulogic; -- ftdiv + f_dcd_rf1_ftsqrt :in std_ulogic; -- ftsqrt + + + f_dcd_rf1_nj_deno :in std_ulogic; -- force output den to zero + f_dcd_rf1_nj_deni :in std_ulogic; -- force input den to zero + + f_dcd_rf1_sp_conv_b :in std_ulogic; -- for sp/dp convert + f_dcd_rf1_word_b :in std_ulogic; -- for converts word/dw + f_dcd_rf1_uns_b :in std_ulogic; -- for converts unsigned + f_dcd_rf1_sub_op_b :in std_ulogic; -- fsub, fnmsub, fmsub + + f_dcd_rf1_force_excp_dis :in std_ulogic; + + f_dcd_rf1_op_rnd_v_b :in std_ulogic; -- rounding mode = nearest + f_dcd_rf1_op_rnd_b :in std_ulogic_vector(0 to 1); -- rounding mode = positive infinity + f_dcd_rf1_inv_sign_b :in std_ulogic; -- fnmsub fnmadd + f_dcd_rf1_sign_ctl_b :in std_ulogic_vector(0 to 1); -- 0:fmr/fneg 1:fneg/fnabs + f_dcd_rf1_sgncpy_b :in std_ulogic; -- for sgncpy instruction : + -- BValid=1 Avalid=0 move=1 sgncpy=1 + -- sgnctl=fabs=00 <11 for _b> + -- force pass, rnd_v=0, ovf_unf_dis, + + f_dcd_rf1_fpscr_bit_data_b :in std_ulogic_vector(0 to 3); --data to write to nibble (other than mtfsf) + f_dcd_rf1_fpscr_bit_mask_b :in std_ulogic_vector(0 to 3); --enable update of bit within the nibble + f_dcd_rf1_fpscr_nib_mask_b :in std_ulogic_vector(0 to 8); --enable update of this nibble + -- [8] = 0 except + -- if (mtfsi AND w=1 AND bf=000 ) <= 0000_0000_1 + -- if (mtfsf AND L==1) <= 1111_1111_1 + -- if (mtfsf AND L=0 and w=1 and flm=xxxx_xxxx_1) <= 0000_0000_1 + -- if (mtfsf AND L=0 and w=1 and flm=xxxx_xxxx_0) <= 0000_0000_0 + -- if (mtfsf AND L=0 and w=0 and flm=xxxx_xxxx_1) <= dddd_dddd_0 + + f_dcd_rf1_mv_to_scr_b :in std_ulogic; --mcrfs,mtfsf,mtfsfi,mtfsb0,mtfsb1 + f_dcd_rf1_mv_from_scr_b :in std_ulogic; --mffs + f_dcd_rf1_mtfsbx_b :in std_ulogic; --fpscr set bit, reset bit + f_dcd_rf1_mcrfs_b :in std_ulogic; --move fpscr field to cr and reset exceptions + f_dcd_rf1_mtfsf_b :in std_ulogic; --move fpr data to fpscr + f_dcd_rf1_mtfsfi_b :in std_ulogic; --move immediate data to fpscr + + f_dcd_ex1_perr_force_c :in std_ulogic; + f_dcd_ex1_perr_fsel_ovrd :in std_ulogic; + + f_dcd_rf1_uc_fc_hulp :in std_ulogic;--byp : bit 53 of multiplier + f_dcd_rf1_uc_fa_pos :in std_ulogic;--byp : immediate data + f_dcd_rf1_uc_fc_pos :in std_ulogic;--byp : immediate data + f_dcd_rf1_uc_fb_pos :in std_ulogic;--byp : immediate data + f_dcd_rf1_uc_fc_0_5 :in std_ulogic;--byp : immediate data + f_dcd_rf1_uc_fc_1_0 :in std_ulogic;--byp : immediate data + f_dcd_rf1_uc_fc_1_minus :in std_ulogic;--byp : immediate data + f_dcd_rf1_uc_fb_1_0 :in std_ulogic;--byp : immediate data + f_dcd_rf1_uc_fb_0_75 :in std_ulogic;--byp : immediate data + f_dcd_rf1_uc_fb_0_5 :in std_ulogic;--byp : immediate data + f_dcd_rf1_uc_ft_pos :in std_ulogic;--pic + f_dcd_rf1_uc_ft_neg :in std_ulogic;--pic + + f_dcd_rf1_div_beg :in std_ulogic; --old + f_dcd_rf1_sqrt_beg :in std_ulogic; --old + f_dcd_rf1_uc_mid :in std_ulogic; + f_dcd_rf1_uc_end :in std_ulogic; + f_dcd_rf1_uc_special :in std_ulogic; + f_dcd_ex2_uc_zx :in std_ulogic; + f_dcd_ex2_uc_vxidi :in std_ulogic; + f_dcd_ex2_uc_vxzdz :in std_ulogic; + f_dcd_ex2_uc_vxsqrt :in std_ulogic; + f_dcd_ex2_uc_vxsnan :in std_ulogic; + + f_dcd_ex2_uc_inc_lsb :in std_ulogic; + f_dcd_ex2_uc_gs_v :in std_ulogic; + f_dcd_ex2_uc_gs :in std_ulogic_vector(0 to 1); + + f_mad_ex6_uc_sign :out std_ulogic; + f_mad_ex6_uc_zero :out std_ulogic; + f_mad_ex3_uc_special :out std_ulogic; + f_mad_ex3_uc_zx :out std_ulogic; + f_mad_ex3_uc_vxidi :out std_ulogic; + f_mad_ex3_uc_vxzdz :out std_ulogic; + f_mad_ex3_uc_vxsqrt :out std_ulogic; + f_mad_ex3_uc_vxsnan :out std_ulogic; + f_mad_ex3_uc_res_sign :out std_ulogic; + f_mad_ex3_uc_round_mode :out std_ulogic_vector(0 to 1); + + f_mad_ex2_a_parity_check :out std_ulogic; + f_mad_ex2_c_parity_check :out std_ulogic; + f_mad_ex2_b_parity_check :out std_ulogic; + + + f_ex2_b_den_flush :out std_ulogic ;--iu (does not include all gating) ??? + + f_scr_ex7_cr_fld :out std_ulogic_vector (0 to 3) ;--o-- + f_add_ex4_fpcc_iu :out std_ulogic_vector (0 to 3) ;--o-- + f_pic_ex5_fpr_wr_dis_b :out std_ulogic ;--o-- + f_rnd_ex6_res_expo :out std_ulogic_vector (1 to 13) ;--o-- + f_rnd_ex6_res_frac :out std_ulogic_vector (0 to 52) ;--o-- + f_rnd_ex6_res_sign :out std_ulogic ;--o-- + f_scr_ex7_fx_thread0 :out std_ulogic_vector (0 to 3) ;--o-- + f_scr_ex7_fx_thread1 :out std_ulogic_vector (0 to 3) ;--o-- + f_scr_ex7_fx_thread2 :out std_ulogic_vector (0 to 3) ;--o-- + f_scr_ex7_fx_thread3 :out std_ulogic_vector (0 to 3) ;--o-- + + ---------------------------------------------------------------------------- + rf1_thread_b :in std_ulogic_vector(0 to 3) ; + f_dcd_rf1_act :in std_ulogic; + ---------------------------------------------------------------------------- + vdd : inout power_logic; + gnd : inout power_logic; + scan_in :in std_ulogic_vector(0 to 17); + scan_out :out std_ulogic_vector(0 to 17); + + clkoff_b :in std_ulogic; -- tiup + act_dis :in std_ulogic; -- ??tidn?? + flush :in std_ulogic; -- ??tidn?? + delay_lclkr :in std_ulogic_vector(1 to 7); -- tidn, + mpw1_b :in std_ulogic_vector(1 to 7); -- tidn, + mpw2_b :in std_ulogic_vector(0 to 1); -- tidn, + thold_1 :in std_ulogic; + sg_1 :in std_ulogic; + fpu_enable :in std_ulogic; + nclk :in clk_logic +); ---------------------------------------------------------------------------- + +end fuq_mad; + + +architecture fuq_mad of fuq_mad is + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal f_fmt_ex1_inf_and_beyond_sp :std_ulogic ; + signal perv_eie_sg_1 :std_ulogic; --PERV-- + signal perv_eov_sg_1 :std_ulogic; --PERV-- + signal perv_fmt_sg_1 :std_ulogic; --PERV-- + signal perv_mul_sg_1 :std_ulogic; --PERV-- + signal perv_alg_sg_1 :std_ulogic; --PERV-- + signal perv_add_sg_1 :std_ulogic; --PERV-- + signal perv_lza_sg_1 :std_ulogic; --PERV-- + signal perv_nrm_sg_1 :std_ulogic; --PERV-- + signal perv_rnd_sg_1 :std_ulogic; --PERV-- + signal perv_scr_sg_1 :std_ulogic; --PERV-- + signal perv_pic_sg_1 :std_ulogic; --PERV-- + signal perv_cr2_sg_1 :std_ulogic; --PERV-- + signal perv_eie_thold_1 :std_ulogic; --PERV-- + signal perv_eov_thold_1 :std_ulogic; --PERV-- + signal perv_fmt_thold_1 :std_ulogic; --PERV-- + signal perv_mul_thold_1 :std_ulogic; --PERV-- + signal perv_alg_thold_1 :std_ulogic; --PERV-- + signal perv_add_thold_1 :std_ulogic; --PERV-- + signal perv_lza_thold_1 :std_ulogic; --PERV-- + signal perv_nrm_thold_1 :std_ulogic; --PERV-- + signal perv_rnd_thold_1 :std_ulogic; --PERV-- + signal perv_scr_thold_1 :std_ulogic; --PERV-- + signal perv_pic_thold_1 :std_ulogic; --PERV-- + signal perv_cr2_thold_1 :std_ulogic; --PERV-- + signal perv_eie_fpu_enable :std_ulogic; --PERV-- + signal perv_eov_fpu_enable :std_ulogic; --PERV-- + signal perv_fmt_fpu_enable :std_ulogic; --PERV-- + signal perv_mul_fpu_enable :std_ulogic; --PERV-- + signal perv_alg_fpu_enable :std_ulogic; --PERV-- + signal perv_add_fpu_enable :std_ulogic; --PERV-- + signal perv_lza_fpu_enable :std_ulogic; --PERV-- + signal perv_nrm_fpu_enable :std_ulogic; --PERV-- + signal perv_rnd_fpu_enable :std_ulogic; --PERV-- + signal perv_scr_fpu_enable :std_ulogic; --PERV-- + signal perv_pic_fpu_enable :std_ulogic; --PERV-- + signal perv_cr2_fpu_enable :std_ulogic; --PERV-- + + + + signal f_eov_ex4_may_ovf :std_ulogic ; + signal f_add_ex4_flag_eq :std_ulogic ;--o-- + signal f_add_ex4_flag_gt :std_ulogic ;--o-- + signal f_add_ex4_flag_lt :std_ulogic ;--o-- + signal f_add_ex4_flag_nan :std_ulogic ;--o-- + signal f_add_ex4_res :std_ulogic_vector (0 to 162) ;--o-- + signal f_add_ex4_sign_carry :std_ulogic ;--o-- + signal f_add_ex4_sticky :std_ulogic ;--o-- + signal f_add_ex4_to_int_ovf_dw :std_ulogic_vector(0 to 1) ;--o-- + signal f_add_ex4_to_int_ovf_wd :std_ulogic_vector(0 to 1) ;--o-- + signal f_alg_ex2_effsub_eac_b :std_ulogic ;--o-- + signal f_alg_ex2_prod_z :std_ulogic ;--o-- + signal f_alg_ex2_res :std_ulogic_vector (0 to 162) ;--o-- + signal f_alg_ex2_sel_byp :std_ulogic ;--o-- + signal f_alg_ex2_sh_ovf :std_ulogic ;--o-- + signal f_alg_ex2_sh_unf :std_ulogic ;--o-- + signal f_alg_ex3_frc_sel_p1 :std_ulogic ;--o-- + signal f_alg_ex3_int_fi :std_ulogic ;--o-- + signal f_alg_ex3_int_fr :std_ulogic ;--o-- + signal f_alg_ex3_sticky :std_ulogic ;--o-- + + signal f_byp_fmt_ex1_a_expo :std_ulogic_vector (1 to 13) ;--o-- + signal f_byp_eie_ex1_a_expo :std_ulogic_vector (1 to 13) ;--o-- + signal f_byp_alg_ex1_a_expo :std_ulogic_vector (1 to 13) ;--o-- + signal f_byp_fmt_ex1_b_expo :std_ulogic_vector (1 to 13) ;--o-- + signal f_byp_eie_ex1_b_expo :std_ulogic_vector (1 to 13) ;--o-- + signal f_byp_alg_ex1_b_expo :std_ulogic_vector (1 to 13) ;--o-- + signal f_byp_fmt_ex1_c_expo :std_ulogic_vector (1 to 13) ;--o-- + signal f_byp_eie_ex1_c_expo :std_ulogic_vector (1 to 13) ;--o-- + signal f_byp_alg_ex1_c_expo :std_ulogic_vector (1 to 13) ;--o-- + signal f_byp_fmt_ex1_a_frac :std_ulogic_vector (0 to 52) ;--o-- + signal f_byp_fmt_ex1_c_frac :std_ulogic_vector (0 to 52) ;--o-- + signal f_byp_fmt_ex1_b_frac :std_ulogic_vector (0 to 52) ;--o-- + signal f_byp_mul_ex1_a_frac :std_ulogic_vector (0 to 52) ;--o-- + signal f_byp_mul_ex1_a_frac_17 :std_ulogic ;--o-- + signal f_byp_mul_ex1_a_frac_35 :std_ulogic ;--o-- + signal f_byp_mul_ex1_c_frac :std_ulogic_vector (0 to 53) ;--o-- + signal f_byp_alg_ex1_b_frac :std_ulogic_vector (0 to 52) ;--o-- + signal f_byp_fmt_ex1_a_sign :std_ulogic ;--o-- + signal f_byp_fmt_ex1_b_sign :std_ulogic ;--o-- + signal f_byp_fmt_ex1_c_sign :std_ulogic ;--o-- + signal f_byp_pic_ex1_a_sign :std_ulogic ;--o-- + signal f_byp_pic_ex1_b_sign :std_ulogic ;--o-- + signal f_byp_pic_ex1_c_sign :std_ulogic ;--o-- + signal f_byp_alg_ex1_b_sign :std_ulogic ;--o-- + + signal f_cr2_ex1_fpscr_shadow :std_ulogic_vector(0 to 7) ;--o-- + signal f_pic_ex2_rnd_inf_ok :std_ulogic ;--o-- + signal f_pic_ex2_rnd_nr :std_ulogic ;--o-- + signal f_cr2_ex3_fpscr_bit_data_b :std_ulogic_vector(0 to 3); + signal f_cr2_ex3_fpscr_bit_mask_b :std_ulogic_vector(0 to 3); + signal f_cr2_ex3_fpscr_nib_mask_b :std_ulogic_vector(0 to 8); + signal f_cr2_ex3_mcrfs_b :std_ulogic ;--o-- + signal f_cr2_ex3_mtfsbx_b :std_ulogic ;--o-- + signal f_cr2_ex3_mtfsf_b :std_ulogic ;--o-- + signal f_cr2_ex3_mtfsfi_b :std_ulogic ;--o-- + signal f_cr2_ex3_thread_b :std_ulogic_vector(0 to 3);--o-- + signal f_pic_add_ex1_act_b :std_ulogic ;--o-- + signal f_pic_alg_ex1_act :std_ulogic ;--o-- + signal f_pic_cr2_ex1_act :std_ulogic ;--o-- + signal f_pic_eie_ex1_act :std_ulogic ;--o-- + signal f_pic_eov_ex2_act_b :std_ulogic ;--o-- + signal f_pic_ex1_effsub_raw :std_ulogic ;--o-- + signal f_pic_ex1_from_integer :std_ulogic ;--o-- + signal f_pic_ex1_fsel :std_ulogic ;--o-- + signal f_pic_ex1_sh_ovf_do :std_ulogic ;--o-- + signal f_pic_ex1_sh_ovf_ig_b :std_ulogic ;--o-- + signal f_pic_ex1_sh_unf_do :std_ulogic ;--o-- + signal f_pic_ex1_sh_unf_ig_b :std_ulogic ;--o-- + signal f_pic_ex2_force_sel_bexp :std_ulogic ;--o-- + signal f_pic_ex2_lzo_dis_prod :std_ulogic ;--o-- + signal f_pic_ex2_sp_b :std_ulogic ;--o-- + signal f_pic_ex2_sp_lzo :std_ulogic ;--o-- + signal f_pic_ex2_to_integer :std_ulogic ;--o-- + signal f_pic_ex2_prenorm :std_ulogic ;--o-- + signal f_pic_ex3_cmp_sgnneg :std_ulogic ;--o-- + signal f_pic_ex3_cmp_sgnpos :std_ulogic ;--o-- + signal f_pic_ex3_is_eq :std_ulogic ;--o-- + signal f_pic_ex3_is_gt :std_ulogic ;--o-- + signal f_pic_ex3_is_lt :std_ulogic ;--o-- + signal f_pic_ex3_is_nan :std_ulogic ;--o-- + signal f_pic_ex3_sel_est :std_ulogic ;--o-- + signal f_pic_ex3_sp_b :std_ulogic ;--o-- + signal f_pic_ex4_nj_deno :std_ulogic ;--o-- + signal f_pic_ex4_oe :std_ulogic ;--o-- + signal f_pic_ex4_ov_en :std_ulogic ;--o-- + signal f_pic_ex4_ovf_en_oe0_b :std_ulogic ;--o-- + signal f_pic_ex4_ovf_en_oe1_b :std_ulogic ;--o-- + signal f_pic_ex4_quiet_b :std_ulogic ;--o-- + signal f_pic_ex5_uc_inc_lsb :std_ulogic ;--o-- + signal f_pic_ex5_uc_guard :std_ulogic ;--o-- + signal f_pic_ex5_uc_sticky :std_ulogic ;--o-- + signal f_pic_ex5_uc_g_v :std_ulogic ;--o-- + signal f_pic_ex5_uc_s_v :std_ulogic ;--o-- + signal f_pic_ex4_rnd_inf_ok_b :std_ulogic ;--o-- + signal f_pic_ex4_rnd_ni_b :std_ulogic ;--o-- + signal f_pic_ex4_rnd_nr_b :std_ulogic ;--o-- + signal f_pic_ex4_sel_est_b :std_ulogic ;--o-- + signal f_pic_ex4_sel_fpscr_b :std_ulogic ;--o-- + signal f_pic_ex4_sp_b :std_ulogic ;--o-- + signal f_pic_ex4_spec_inf_b :std_ulogic ;--o-- + signal f_pic_ex4_spec_sel_k_e :std_ulogic ;--o-- + signal f_pic_ex4_spec_sel_k_f :std_ulogic ;--o-- + signal f_pic_ex4_to_int_ov_all :std_ulogic ;--o-- + signal f_pic_ex4_to_integer_b :std_ulogic ;--o-- + signal f_pic_ex4_word_b :std_ulogic ;--o-- + signal f_pic_ex4_uns_b :std_ulogic ;--o-- + signal f_pic_ex4_ue :std_ulogic ;--o-- + signal f_pic_ex4_uf_en :std_ulogic ;--o-- + signal f_pic_ex4_unf_en_ue0_b :std_ulogic ;--o-- + signal f_pic_ex4_unf_en_ue1_b :std_ulogic ;--o-- + signal f_pic_ex5_en_exact_zero :std_ulogic ;--o-- + signal f_pic_ex5_compare_b :std_ulogic ;--o-- + signal f_pic_ex2_ue1 :std_ulogic ;--o-- + signal f_pic_ex2_frsp_ue1 :std_ulogic ;--o-- + signal f_pic_ex1_frsp_ue1 :std_ulogic ;--o-- + signal f_pic_ex5_frsp :std_ulogic ;--o-- + signal f_pic_ex5_fi_pipe_v_b :std_ulogic ;--o-- + signal f_pic_ex5_fi_spec_b :std_ulogic ;--o-- + signal f_pic_ex5_flag_vxcvi_b :std_ulogic ;--o-- + signal f_pic_ex5_flag_vxidi_b :std_ulogic ;--o-- + signal f_pic_ex5_flag_vximz_b :std_ulogic ;--o-- + signal f_pic_ex5_flag_vxisi_b :std_ulogic ;--o-- + signal f_pic_ex5_flag_vxsnan_b :std_ulogic ;--o-- + signal f_pic_ex5_flag_vxsqrt_b :std_ulogic ;--o-- + signal f_pic_ex5_flag_vxvc_b :std_ulogic ;--o-- + signal f_pic_ex5_flag_vxzdz_b :std_ulogic ;--o-- + signal f_pic_ex5_flag_zx_b :std_ulogic ;--o-- + signal f_pic_ex5_fprf_hold_b :std_ulogic ;--o-- + signal f_pic_ex5_fprf_pipe_v_b :std_ulogic ;--o-- + signal f_pic_ex5_fprf_spec_b :std_ulogic_vector (0 to 4) ;--o-- + signal f_pic_ex5_fr_pipe_v_b :std_ulogic ;--o-- + signal f_pic_ex5_fr_spec_b :std_ulogic ;--o-- + signal f_pic_ex5_invert_sign :std_ulogic ;--o-- + signal f_pic_ex4_byp_prod_nz :std_ulogic ;--o-- + signal f_pic_ex5_k_nan :std_ulogic ; + signal f_pic_ex5_k_inf :std_ulogic ; + signal f_pic_ex5_k_max :std_ulogic ; + signal f_pic_ex5_k_zer :std_ulogic ; + signal f_pic_ex5_k_one :std_ulogic ; + signal f_pic_ex5_k_int_maxpos :std_ulogic ; + signal f_pic_ex5_k_int_maxneg :std_ulogic ; + signal f_pic_ex5_k_int_zer :std_ulogic ; + signal f_pic_ex5_ox_pipe_v_b :std_ulogic ;--o-- + signal f_pic_ex5_round_sign :std_ulogic ;--o-- + signal f_pic_ex5_scr_upd_move_b :std_ulogic ;--o-- + signal f_pic_ex5_scr_upd_pipe_b :std_ulogic ;--o-- + signal f_pic_ex5_ux_pipe_v_b :std_ulogic ;--o-- + signal f_pic_fmt_ex1_act :std_ulogic ;--o-- + signal f_pic_lza_ex1_act_b :std_ulogic ;--o-- + signal f_pic_mul_ex1_act :std_ulogic ;--o-- + signal f_pic_nrm_ex3_act_b :std_ulogic ;--o-- + signal f_pic_rnd_ex3_act_b :std_ulogic ;--o-- + signal f_pic_scr_ex2_act_b :std_ulogic ;--o-- + signal f_eie_ex2_dw_ov :std_ulogic ;--o-- + signal f_eie_ex2_dw_ov_if :std_ulogic ;--o-- + signal f_eie_ex2_lzo_expo :std_ulogic_vector (1 to 13) ;--o-- + signal f_eie_ex2_b_expo :std_ulogic_vector (1 to 13) ;--o-- + signal f_eie_ex2_tbl_expo :std_ulogic_vector (1 to 13) ;--o-- + signal f_eie_ex2_wd_ov :std_ulogic ;--o-- + signal f_eie_ex2_wd_ov_if :std_ulogic ;--o-- + signal f_eie_ex3_iexp :std_ulogic_vector (1 to 13) ;--o-- + signal f_eov_ex5_expo_p0 :std_ulogic_vector (1 to 13) ;--o-- + signal f_eov_ex5_expo_p0_ue1oe1 :std_ulogic_vector (3 to 7) ;--o-- + signal f_eov_ex5_expo_p1 :std_ulogic_vector (1 to 13) ;--o-- + signal f_eov_ex5_expo_p1_ue1oe1 :std_ulogic_vector (3 to 7) ;--o-- + signal f_eov_ex5_ovf_expo :std_ulogic ;--o-- + signal f_eov_ex5_ovf_if_expo :std_ulogic ;--o-- + signal f_eov_ex5_sel_k_e :std_ulogic ;--o-- + signal f_eov_ex5_sel_k_f :std_ulogic ;--o-- + signal f_eov_ex5_sel_kif_e :std_ulogic ;--o-- + signal f_eov_ex5_sel_kif_f :std_ulogic ;--o-- + signal f_eov_ex5_unf_expo :std_ulogic ;--o-- + signal f_fmt_ex1_a_expo_max :std_ulogic ;--o-- + signal f_fmt_ex1_a_zero :std_ulogic ;--o-- + signal f_fmt_ex1_a_frac_msb :std_ulogic ;--o-- + signal f_fmt_ex1_a_frac_zero :std_ulogic ;--o-- + signal f_fmt_ex1_b_expo_max :std_ulogic ;--o-- + signal f_fmt_ex1_b_zero :std_ulogic ;--o-- + signal f_fmt_ex1_b_frac_msb :std_ulogic ;--o-- + signal f_fmt_ex1_b_frac_z32 :std_ulogic; + signal f_fmt_ex1_b_frac_zero :std_ulogic ;--o-- + signal f_fmt_ex1_bop_byt :std_ulogic_vector(45 to 52) ;--o-- + signal f_fmt_ex1_c_expo_max :std_ulogic ;--o-- + signal f_fmt_ex1_c_zero :std_ulogic ;--o-- + signal f_fmt_ex1_c_frac_msb :std_ulogic ;--o-- + signal f_fmt_ex1_c_frac_zero :std_ulogic ;--o-- + signal f_fmt_ex1_sp_invalid :std_ulogic ;--o-- + signal f_fmt_ex1_pass_sel :std_ulogic ;--o-- + signal f_fmt_ex1_prod_zero :std_ulogic ;--o-- + signal f_fmt_ex2_fsel_bsel :std_ulogic ;--o-- + signal f_fmt_ex2_pass_frac :std_ulogic_vector (0 to 52) ;--o-- + signal f_fmt_ex2_pass_sign :std_ulogic ;--o-- + signal f_fmt_ex2_pass_msb :std_ulogic ;--o-- + signal f_fmt_ex1_b_imp :std_ulogic ;--o-- + signal f_lza_ex4_lza_amt :std_ulogic_vector (0 to 7) ;--o-- + signal f_lza_ex4_lza_dcd64_cp1 :std_ulogic_vector(0 to 2); + signal f_lza_ex4_lza_dcd64_cp2 :std_ulogic_vector(0 to 1); + signal f_lza_ex4_lza_dcd64_cp3 :std_ulogic_vector(0 to 0); + signal f_lza_ex4_sh_rgt_en :std_ulogic; + signal f_lza_ex4_sh_rgt_en_eov :std_ulogic; + signal f_lza_ex4_lza_amt_eov :std_ulogic_vector (0 to 7) ;--o-- + signal f_lza_ex4_no_lza_edge :std_ulogic ;--o-- + signal f_mul_ex2_car :std_ulogic_vector (1 to 108) ;--o-- + signal f_mul_ex2_sum :std_ulogic_vector (1 to 108) ;--o-- + signal f_nrm_ex4_extra_shift :std_ulogic ;--o-- + signal f_nrm_ex5_exact_zero :std_ulogic ;--o-- + signal f_nrm_ex5_fpscr_wr_dat :std_ulogic_vector (0 to 31) ;--o-- + signal f_nrm_ex5_fpscr_wr_dat_dfp :std_ulogic_vector (0 to 3) ;--o-- + signal f_nrm_ex5_int_lsbs :std_ulogic_vector (1 to 12) ;--o-- + signal f_nrm_ex5_int_sign :std_ulogic; + signal f_nrm_ex5_nrm_guard_dp :std_ulogic ;--o-- + signal f_nrm_ex5_nrm_guard_sp :std_ulogic ;--o-- + signal f_nrm_ex5_nrm_lsb_dp :std_ulogic ;--o-- + signal f_nrm_ex5_nrm_lsb_sp :std_ulogic ;--o-- + signal f_nrm_ex5_nrm_sticky_dp :std_ulogic ;--o-- + signal f_nrm_ex5_nrm_sticky_sp :std_ulogic ;--o-- + signal f_nrm_ex5_res :std_ulogic_vector (0 to 52) ;--o-- + signal f_rnd_ex6_flag_den :std_ulogic ;--o-- + signal f_rnd_ex6_flag_fi :std_ulogic ;--o-- + signal f_rnd_ex6_flag_inf :std_ulogic ;--o-- + signal f_rnd_ex6_flag_ox :std_ulogic ;--o-- + signal f_rnd_ex6_flag_sgn :std_ulogic ;--o-- + signal f_rnd_ex6_flag_up :std_ulogic ;--o-- + signal f_rnd_ex6_flag_ux :std_ulogic ;--o-- + signal f_rnd_ex6_flag_zer :std_ulogic ;--o-- + signal f_sa3_ex3_c_lza :std_ulogic_vector (53 to 161) ;--o-- + signal f_sa3_ex3_s_lza :std_ulogic_vector (0 to 162) ;--o-- + signal f_sa3_ex3_c_add :std_ulogic_vector (53 to 161) ;--o-- + signal f_sa3_ex3_s_add :std_ulogic_vector (0 to 162) ;--o-- + signal f_scr_ex5_fpscr_rd_dat_dfp :std_ulogic_vector (0 to 3) ;--o-- + signal f_scr_ex5_fpscr_rd_dat :std_ulogic_vector (0 to 31) ;--o-- + signal f_cr2_ex5_fpscr_rd_dat :std_ulogic_vector (24 to 31) ;--o-- + signal f_cr2_ex6_fpscr_rd_dat :std_ulogic_vector (24 to 31) ;--o-- + signal f_pic_tbl_ex1_act :std_ulogic; + + + signal f_pic_ex2_math_bzer_b :std_ulogic; + signal perv_sa3_thold_1 :std_ulogic; + signal perv_sa3_sg_1 :std_ulogic; + signal perv_sa3_fpu_enable :std_ulogic; + signal f_pic_ex2_b_valid :std_ulogic; + signal f_alg_ex2_byp_nonflip :std_ulogic; + signal f_pic_ex1_rnd_to_int :std_ulogic; + signal f_eie_ex2_lt_bias :std_ulogic; + signal f_eie_ex2_eq_bias_m1 :std_ulogic; + signal f_pic_ex2_est_recip :std_ulogic; + signal f_pic_ex2_est_rsqrt :std_ulogic; +signal f_tbe_ex3_may_ov :std_ulogic; +signal f_tbe_ex3_res_expo :std_ulogic_vector(1 to 13); +signal perv_tbe_sg_1, perv_tbe_thold_1, perv_tbe_fpu_enable :std_ulogic; +signal perv_tbl_sg_1, perv_tbl_thold_1, perv_tbl_fpu_enable :std_ulogic; +signal f_tbe_ex3_recip_2046 :std_ulogic; +signal f_tbe_ex3_recip_2045 :std_ulogic; +signal f_fmt_ex1_b_frac :std_ulogic_vector(1 to 19); +signal f_tbl_ex5_est_frac :std_ulogic_vector(0 to 26); +signal f_tbl_ex5_recip_den :std_ulogic; +signal f_eie_ex2_use_bexp :std_ulogic; +signal rnd_ex6_res_sign :std_ulogic; +signal rnd_ex6_res_expo :std_ulogic_vector(1 to 13); +signal rnd_ex6_res_frac :std_ulogic_vector(0 to 52); +signal f_pic_ex1_flush_en_dp, f_pic_ex1_flush_en_sp, f_pic_ex1_ftdiv :std_ulogic; +signal f_fmt_ex2_lu_den_recip , f_fmt_ex2_lu_den_rsqrto :std_ulogic; +signal f_tbe_ex3_recip_2044, f_tbe_ex3_lu_sh :std_ulogic; + +signal f_lze_ex2_lzo_din :std_ulogic_vector(0 to 162); +signal f_lze_ex3_sh_rgt_amt :std_ulogic_vector(0 to 7) ; +signal f_lze_ex3_sh_rgt_en :std_ulogic; +signal f_alg_ex1_sign_frmw :std_ulogic; +signal f_tbe_ex3_match_en_sp , f_tbe_ex3_match_en_dp :std_ulogic; +signal f_tbl_ex4_unf_expo :std_ulogic; +signal f_tbe_ex3_recip_ue1 :std_ulogic ; +signal f_fmt_ex1_bexpu_le126 :std_ulogic ; +signal f_fmt_ex1_gt126 :std_ulogic ; +signal f_fmt_ex1_ge128 :std_ulogic ; +signal f_gst_ex5_logexp_v :std_ulogic ; +signal f_gst_ex5_logexp_sign :std_ulogic ; +signal f_gst_ex5_logexp_exp :std_ulogic_vector(1 to 11); +signal f_gst_ex5_logexp_fract :std_ulogic_vector(0 to 19); +signal f_fmt_ex1_b_sign_gst :std_ulogic; +signal f_fmt_ex1_b_expo_gst_b :std_ulogic_vector(1 to 13); +signal f_pic_ex1_log2e :std_ulogic; +signal f_pic_ex1_pow2e :std_ulogic; +signal f_mad_ex2_uc_a_expo_den , f_mad_ex2_uc_a_expo_den_sp :std_ulogic; -- a exponent <= 0 +signal f_pic_ex1_nj_deni :std_ulogic; +signal f_fmt_ex2_ae_ge_54, f_fmt_ex2_be_ge_54, f_fmt_ex2_be_ge_2, f_fmt_ex2_be_ge_2044, f_fmt_ex2_tdiv_rng_chk :std_ulogic ; +signal f_fmt_ex2_be_den :std_ulogic; + + +begin + + + + + +fbyp : entity WORK.fuq_byp(fuq_byp) generic map( expand_type => expand_type) port map( -- fuq_byp.vhdl +----------------------------------------------------------- -- fuq_byp.vhdl + vdd => vdd ,--i-- + gnd => gnd ,--i-- + nclk => nclk ,--i-- + clkoff_b => clkoff_b ,--i-- + act_dis => act_dis ,--i-- + flush => flush ,--i-- + delay_lclkr => delay_lclkr(1) ,--i-- + mpw1_b => mpw1_b(1) ,--i-- + mpw2_b => mpw2_b(0) ,--i-- + thold_1 => perv_fmt_thold_1 ,--i-- + sg_1 => perv_fmt_sg_1 ,--i-- + fpu_enable => perv_fmt_fpu_enable ,--i-- + + f_byp_si => scan_in(0) ,--i--fbyp + f_byp_so => scan_out(0) ,--o--fbyp + rf1_act => f_dcd_rf1_act ,--i--fbyp + + f_fpr_ex7_frt_sign => f_fpr_ex7_frt_sign ,--i--fbyp + f_fpr_ex7_frt_expo(1 to 13) => f_fpr_ex7_frt_expo(1 to 13) ,--i--fbyp + f_fpr_ex7_frt_frac(0 to 52) => f_fpr_ex7_frt_frac(0 to 52) ,--i--fbyp + f_fpr_ex7_load_sign => f_fpr_ex7_load_sign ,--i--fbyp + f_fpr_ex7_load_expo(3 to 13) => f_fpr_ex7_load_expo(3 to 13) ,--i--fbyp + f_fpr_ex7_load_frac(0 to 52) => f_fpr_ex7_load_frac(0 to 52) ,--i--fbyp + + f_dcd_rf1_div_beg => f_dcd_rf1_div_beg ,--i--fbyp + f_dcd_rf1_uc_fa_pos => f_dcd_rf1_uc_fa_pos ,--i--fbyp + f_dcd_rf1_uc_fc_pos => f_dcd_rf1_uc_fc_pos ,--i--fbyp + f_dcd_rf1_uc_fb_pos => f_dcd_rf1_uc_fb_pos ,--i--fbyp + f_dcd_rf1_uc_fc_0_5 => f_dcd_rf1_uc_fc_0_5 ,--i--fbyp + f_dcd_rf1_uc_fc_1_0 => f_dcd_rf1_uc_fc_1_0 ,--i--fbyp + f_dcd_rf1_uc_fc_1_minus => f_dcd_rf1_uc_fc_1_minus ,--i--fbyp + f_dcd_rf1_uc_fb_1_0 => f_dcd_rf1_uc_fb_1_0 ,--i--fbyp + f_dcd_rf1_uc_fb_0_75 => f_dcd_rf1_uc_fb_0_75 ,--i--fbyp + f_dcd_rf1_uc_fb_0_5 => f_dcd_rf1_uc_fb_0_5 ,--i--fbyp + + f_dcd_rf1_uc_fc_hulp => f_dcd_rf1_uc_fc_hulp ,--i--fbyp + f_dcd_rf1_bypsel_a_res0 => f_dcd_rf1_bypsel_a_res0 ,--i--fbyp + f_dcd_rf1_bypsel_a_res1 => f_dcd_rf1_bypsel_a_res1 ,--i--fbyp + f_dcd_rf1_bypsel_a_load0 => f_dcd_rf1_bypsel_a_load0 ,--i--fbyp + f_dcd_rf1_bypsel_a_load1 => f_dcd_rf1_bypsel_a_load1 ,--i--fbyp + f_dcd_rf1_bypsel_b_res0 => f_dcd_rf1_bypsel_b_res0 ,--i--fbyp + f_dcd_rf1_bypsel_b_res1 => f_dcd_rf1_bypsel_b_res1 ,--i--fbyp + f_dcd_rf1_bypsel_b_load0 => f_dcd_rf1_bypsel_b_load0 ,--i--fbyp + f_dcd_rf1_bypsel_b_load1 => f_dcd_rf1_bypsel_b_load1 ,--i--fbyp + f_dcd_rf1_bypsel_c_res0 => f_dcd_rf1_bypsel_c_res0 ,--i--fbyp + f_dcd_rf1_bypsel_c_res1 => f_dcd_rf1_bypsel_c_res1 ,--i--fbyp + f_dcd_rf1_bypsel_c_load0 => f_dcd_rf1_bypsel_c_load0 ,--i--fbyp + f_dcd_rf1_bypsel_c_load1 => f_dcd_rf1_bypsel_c_load1 ,--i--fbyp + + f_rnd_ex6_res_sign => rnd_ex6_res_sign ,--i--fbyp + f_rnd_ex6_res_expo(1 to 13) => rnd_ex6_res_expo(1 to 13) ,--i--fbyp + f_rnd_ex6_res_frac(0 to 52) => rnd_ex6_res_frac(0 to 52) ,--i--fbyp + f_fpr_ex6_load_sign => f_fpr_ex6_load_sign ,--i--fbyp + f_fpr_ex6_load_expo(3 to 13) => f_fpr_ex6_load_expo(3 to 13) ,--i--fbyp + f_fpr_ex6_load_frac(0 to 52) => f_fpr_ex6_load_frac(0 to 52) ,--i--fbyp + f_fpr_rf1_a_sign => f_fpr_rf1_a_sign ,--i--fbyp + f_fpr_rf1_a_expo(1 to 13) => f_fpr_rf1_a_expo(1 to 13) ,--i--fbyp + f_fpr_rf1_a_frac(0 to 52) => f_fpr_rf1_a_frac(0 to 52) ,--i--fbyp + f_fpr_rf1_c_sign => f_fpr_rf1_c_sign ,--i--fbyp + f_fpr_rf1_c_expo(1 to 13) => f_fpr_rf1_c_expo(1 to 13) ,--i--fbyp + f_fpr_rf1_c_frac(0 to 52) => f_fpr_rf1_c_frac(0 to 52) ,--i--fbyp + f_fpr_rf1_b_sign => f_fpr_rf1_b_sign ,--i--fbyp + f_fpr_rf1_b_expo(1 to 13) => f_fpr_rf1_b_expo(1 to 13) ,--i--fbyp + f_fpr_rf1_b_frac(0 to 52) => f_fpr_rf1_b_frac(0 to 52) ,--i--fbyp + f_dcd_rf1_aop_valid => f_dcd_rf1_aop_valid ,--i--fbyp + f_dcd_rf1_cop_valid => f_dcd_rf1_cop_valid ,--i--fbyp + f_dcd_rf1_bop_valid => f_dcd_rf1_bop_valid ,--i--fbyp + f_dcd_rf1_sp => f_dcd_rf1_sp ,--i--fbyp + f_dcd_rf1_to_integer_b => f_dcd_rf1_to_integer_b ,--i--fbyp + f_dcd_rf1_emin_dp => f_dcd_rf1_emin_dp ,--i--fbyp + f_dcd_rf1_emin_sp => f_dcd_rf1_emin_sp ,--i--fbyp + + f_byp_fmt_ex1_a_expo(1 to 13) => f_byp_fmt_ex1_a_expo(1 to 13) ,--o--fbyp + f_byp_eie_ex1_a_expo(1 to 13) => f_byp_eie_ex1_a_expo(1 to 13) ,--o--fbyp + f_byp_alg_ex1_a_expo(1 to 13) => f_byp_alg_ex1_a_expo(1 to 13) ,--o--fbyp + f_byp_fmt_ex1_c_expo(1 to 13) => f_byp_fmt_ex1_c_expo(1 to 13) ,--o--fbyp + f_byp_eie_ex1_c_expo(1 to 13) => f_byp_eie_ex1_c_expo(1 to 13) ,--o--fbyp + f_byp_alg_ex1_c_expo(1 to 13) => f_byp_alg_ex1_c_expo(1 to 13) ,--o--fbyp + f_byp_fmt_ex1_b_expo(1 to 13) => f_byp_fmt_ex1_b_expo(1 to 13) ,--o--fbyp + f_byp_eie_ex1_b_expo(1 to 13) => f_byp_eie_ex1_b_expo(1 to 13) ,--o--fbyp + f_byp_alg_ex1_b_expo(1 to 13) => f_byp_alg_ex1_b_expo(1 to 13) ,--o--fbyp + f_byp_fmt_ex1_a_sign => f_byp_fmt_ex1_a_sign ,--o--fbyp + f_byp_fmt_ex1_c_sign => f_byp_fmt_ex1_c_sign ,--o--fbyp + f_byp_fmt_ex1_b_sign => f_byp_fmt_ex1_b_sign ,--o--fbyp + f_byp_pic_ex1_a_sign => f_byp_pic_ex1_a_sign ,--o--fbyp + f_byp_pic_ex1_c_sign => f_byp_pic_ex1_c_sign ,--o--fbyp + f_byp_pic_ex1_b_sign => f_byp_pic_ex1_b_sign ,--o--fbyp + f_byp_alg_ex1_b_sign => f_byp_alg_ex1_b_sign ,--o--fbyp + f_byp_mul_ex1_a_frac_17 => f_byp_mul_ex1_a_frac_17 ,--o--fbyp + f_byp_mul_ex1_a_frac_35 => f_byp_mul_ex1_a_frac_35 ,--o--fbyp + f_byp_mul_ex1_a_frac(0 to 52) => f_byp_mul_ex1_a_frac(0 to 52) ,--o--fbyp + f_byp_fmt_ex1_a_frac(0 to 52) => f_byp_fmt_ex1_a_frac(0 to 52) ,--o--fbyp + f_byp_mul_ex1_c_frac(0 to 52) => f_byp_mul_ex1_c_frac(0 to 52) ,--o--fbyp + f_byp_mul_ex1_c_frac(53) => f_byp_mul_ex1_c_frac(53) ,--o--fbyp + f_byp_fmt_ex1_c_frac(0 to 52) => f_byp_fmt_ex1_c_frac(0 to 52) ,--o--fbyp + f_byp_alg_ex1_b_frac(0 to 52) => f_byp_alg_ex1_b_frac(0 to 52) ,--o--fbyp + f_byp_fmt_ex1_b_frac(0 to 52) => f_byp_fmt_ex1_b_frac(0 to 52) );--o--fbyp +----------------------------------------------------------- -- fuq_byp.vhdl + + + +ffmt : entity WORK.fuq_fmt(fuq_fmt) generic map( expand_type => expand_type) port map( -- fuq_fmt.vhdl +------------------------------------------------------------- fuq_fmt.vhdl + vdd => vdd ,--i-- + gnd => gnd ,--i-- + nclk => nclk ,--i-- + clkoff_b => clkoff_b ,--i-- + act_dis => act_dis ,--i-- + flush => flush ,--i-- + delay_lclkr => delay_lclkr(1 to 2) ,--i-- + mpw1_b => mpw1_b(1 to 2) ,--i-- + mpw2_b => mpw2_b(0 to 0) ,--i-- + thold_1 => perv_fmt_thold_1 ,--i-- + sg_1 => perv_fmt_sg_1 ,--i-- + fpu_enable => perv_fmt_fpu_enable ,--i-- + + f_fmt_si => scan_in(1) ,--i--ffmt + f_fmt_so => scan_out(1) ,--o--ffmt + rf1_act => f_dcd_rf1_act ,--i--ffmt + ex1_act => f_pic_fmt_ex1_act ,--i--ffmt + + f_fpr_ex1_a_par(0 to 7) => f_fpr_ex1_a_par(0 to 7) ,--i--ffmt + f_fpr_ex1_c_par(0 to 7) => f_fpr_ex1_c_par(0 to 7) ,--i--ffmt + f_fpr_ex1_b_par(0 to 7) => f_fpr_ex1_b_par(0 to 7) ,--i--ffmt + + f_mad_ex2_a_parity_check => f_mad_ex2_a_parity_check ,--o--ffmt + f_mad_ex2_c_parity_check => f_mad_ex2_c_parity_check ,--o--ffmt + f_mad_ex2_b_parity_check => f_mad_ex2_b_parity_check ,--o--ffmt + f_fmt_ex2_ae_ge_54 => f_fmt_ex2_ae_ge_54 ,--o--ffmt + f_fmt_ex2_be_ge_54 => f_fmt_ex2_be_ge_54 ,--o--ffmt + f_fmt_ex2_be_ge_2 => f_fmt_ex2_be_ge_2 ,--o--ffmt + f_fmt_ex2_be_ge_2044 => f_fmt_ex2_be_ge_2044 ,--o--ffmt + f_fmt_ex2_tdiv_rng_chk => f_fmt_ex2_tdiv_rng_chk ,--o--ffmt + f_fmt_ex2_be_den => f_fmt_ex2_be_den ,--o--ffmt + f_byp_fmt_ex1_a_sign => f_byp_fmt_ex1_a_sign ,--i--ffmt + f_byp_fmt_ex1_c_sign => f_byp_fmt_ex1_c_sign ,--i--ffmt + f_byp_fmt_ex1_b_sign => f_byp_fmt_ex1_b_sign ,--i--ffmt + f_byp_fmt_ex1_a_expo(1 to 13) => f_byp_fmt_ex1_a_expo(1 to 13) ,--i--ffmt + f_byp_fmt_ex1_c_expo(1 to 13) => f_byp_fmt_ex1_c_expo(1 to 13) ,--i--ffmt + f_byp_fmt_ex1_b_expo(1 to 13) => f_byp_fmt_ex1_b_expo(1 to 13) ,--i--ffmt + + f_byp_fmt_ex1_a_frac(0 to 52) => f_byp_fmt_ex1_a_frac(0 to 52) ,--i--ffmt + f_byp_fmt_ex1_c_frac(0 to 52) => f_byp_fmt_ex1_c_frac(0 to 52) ,--i--ffmt + f_byp_fmt_ex1_b_frac(0 to 52) => f_byp_fmt_ex1_b_frac(0 to 52) ,--i--ffmt + + f_dcd_rf1_sp => f_dcd_rf1_sp ,--i--ffmt + f_dcd_rf1_from_integer_b => f_dcd_rf1_from_integer_b ,--i--ffmt + f_dcd_rf1_sgncpy_b => f_dcd_rf1_sgncpy_b ,--i--ffmt + f_dcd_rf1_uc_mid => f_dcd_rf1_uc_mid ,--i--ffmt + f_dcd_rf1_uc_end => f_dcd_rf1_uc_end ,--i--ffmt + f_dcd_rf1_uc_special => f_dcd_rf1_uc_special ,--i--ffmt + f_dcd_rf1_aop_valid => f_dcd_rf1_aop_valid ,--i--ffmt + f_dcd_rf1_cop_valid => f_dcd_rf1_cop_valid ,--i--ffmt + f_dcd_rf1_bop_valid => f_dcd_rf1_bop_valid ,--i--ffmt + f_dcd_rf1_fsel_b => f_dcd_rf1_fsel_b ,--i--ffmt + f_dcd_rf1_force_pass_b => f_dcd_rf1_force_pass_b ,--i--ffmt + f_dcd_ex1_perr_force_c => f_dcd_ex1_perr_force_c , + f_dcd_ex1_perr_fsel_ovrd => f_dcd_ex1_perr_fsel_ovrd , + f_pic_ex1_ftdiv => f_pic_ex1_ftdiv ,--i--ffmt + f_pic_ex1_flush_en_sp => f_pic_ex1_flush_en_sp ,--i--ffmt + f_pic_ex1_flush_en_dp => f_pic_ex1_flush_en_dp ,--i--ffmt + f_pic_ex1_nj_deni => f_pic_ex1_nj_deni ,--i--ffmt (connect) + f_fmt_ex2_lu_den_recip => f_fmt_ex2_lu_den_recip ,--o--ffmt + f_fmt_ex2_lu_den_rsqrto => f_fmt_ex2_lu_den_rsqrto ,--o--ffmt + f_fmt_ex1_bop_byt(45 to 52) => f_fmt_ex1_bop_byt(45 to 52) ,--o--ffmt + f_fmt_ex1_b_frac(1 to 19) => f_fmt_ex1_b_frac(1 to 19) ,--o--ffmt + f_fmt_ex1_bexpu_le126 => f_fmt_ex1_bexpu_le126 ,--o--ffmt + f_fmt_ex1_gt126 => f_fmt_ex1_gt126 ,--o--ffmt + f_fmt_ex1_ge128 => f_fmt_ex1_ge128 ,--o--ffmt + f_fmt_ex1_inf_and_beyond_sp => f_fmt_ex1_inf_and_beyond_sp ,--o--ffmt + + f_fmt_ex1_b_sign_gst => f_fmt_ex1_b_sign_gst ,--o--ffmt + f_fmt_ex1_b_expo_gst_b(1 to 13) => f_fmt_ex1_b_expo_gst_b(1 to 13) ,--o--ffmt + f_mad_ex2_uc_a_expo_den => f_mad_ex2_uc_a_expo_den ,--o--ffmt + f_mad_ex2_uc_a_expo_den_sp => f_mad_ex2_uc_a_expo_den_sp ,--o--ffmt + f_fmt_ex1_a_zero => f_fmt_ex1_a_zero ,--o--ffmt + f_fmt_ex1_a_expo_max => f_fmt_ex1_a_expo_max ,--o--ffmt + f_fmt_ex1_a_frac_zero => f_fmt_ex1_a_frac_zero ,--o--ffmt + f_fmt_ex1_a_frac_msb => f_fmt_ex1_a_frac_msb ,--o--ffmt + f_fmt_ex1_c_zero => f_fmt_ex1_c_zero ,--o--ffmt + f_fmt_ex1_c_expo_max => f_fmt_ex1_c_expo_max ,--o--ffmt + f_fmt_ex1_c_frac_zero => f_fmt_ex1_c_frac_zero ,--o--ffmt + f_fmt_ex1_c_frac_msb => f_fmt_ex1_c_frac_msb ,--o--ffmt + f_fmt_ex1_b_zero => f_fmt_ex1_b_zero ,--o--ffmt + f_fmt_ex1_b_expo_max => f_fmt_ex1_b_expo_max ,--o--ffmt + f_fmt_ex1_b_frac_zero => f_fmt_ex1_b_frac_zero ,--o--ffmt + f_fmt_ex1_b_frac_msb => f_fmt_ex1_b_frac_msb ,--o--ffmt + f_fmt_ex1_b_frac_z32 => f_fmt_ex1_b_frac_z32 ,--o--ffmt + f_fmt_ex1_prod_zero => f_fmt_ex1_prod_zero ,--o--ffmt + f_fmt_ex1_pass_sel => f_fmt_ex1_pass_sel ,--o--ffmt + f_fmt_ex1_sp_invalid => f_fmt_ex1_sp_invalid ,--o--ffmt + f_ex2_b_den_flush => f_ex2_b_den_flush ,--o--ffmt + f_fmt_ex2_fsel_bsel => f_fmt_ex2_fsel_bsel ,--o--ffmt + f_fmt_ex2_pass_sign => f_fmt_ex2_pass_sign ,--o--ffmt + f_fmt_ex2_pass_msb => f_fmt_ex2_pass_msb ,--o--ffmt + f_fmt_ex1_b_imp => f_fmt_ex1_b_imp ,--o--ffmt + f_fmt_ex2_pass_frac(0 to 52) => f_fmt_ex2_pass_frac(0 to 52) );--o--ffmt +------------------------------------------------------------- fuq_fmt.vhdl + + + + + +feie : entity WORK.fuq_eie(fuq_eie) generic map( expand_type => expand_type) port map( -- fuq_eie.vhdl +------------------------------------------------------------- fuq_eie.vhdl + vdd => vdd ,--i-- + gnd => gnd ,--i-- + nclk => nclk ,--i-- + clkoff_b => clkoff_b ,--i-- + act_dis => act_dis ,--i-- + flush => flush ,--i-- + delay_lclkr => delay_lclkr(2 to 3) ,--i-- + mpw1_b => mpw1_b(2 to 3) ,--i-- + mpw2_b => mpw2_b(0 to 0) ,--i-- + thold_1 => perv_eie_thold_1 ,--i-- + sg_1 => perv_eie_sg_1 ,--i-- + fpu_enable => perv_eie_fpu_enable ,--i-- + + f_eie_si => scan_in(2) ,--i--feie + f_eie_so => scan_out(2) ,--o--feie + ex1_act => f_pic_eie_ex1_act ,--i--feie + f_byp_eie_ex1_a_expo(1 to 13) => f_byp_eie_ex1_a_expo(1 to 13) ,--i--feie + f_byp_eie_ex1_c_expo(1 to 13) => f_byp_eie_ex1_c_expo(1 to 13) ,--i--feie + f_byp_eie_ex1_b_expo(1 to 13) => f_byp_eie_ex1_b_expo(1 to 13) ,--i--feie + f_pic_ex1_from_integer => f_pic_ex1_from_integer ,--i--feie + f_pic_ex1_fsel => f_pic_ex1_fsel ,--i--feie + f_pic_ex2_frsp_ue1 => f_pic_ex2_frsp_ue1 ,--i--feie + f_alg_ex2_sel_byp => f_alg_ex2_sel_byp ,--i--feie + f_fmt_ex2_fsel_bsel => f_fmt_ex2_fsel_bsel ,--i--feie + f_pic_ex2_force_sel_bexp => f_pic_ex2_force_sel_bexp ,--i--feie + f_pic_ex2_sp_b => f_pic_ex2_sp_b ,--i--feie + f_pic_ex2_math_bzer_b => f_pic_ex2_math_bzer_b ,--i--feie + f_eie_ex2_lt_bias => f_eie_ex2_lt_bias ,--o--feie + f_eie_ex2_eq_bias_m1 => f_eie_ex2_eq_bias_m1 ,--o--feie + f_eie_ex2_wd_ov => f_eie_ex2_wd_ov ,--o--feie + f_eie_ex2_dw_ov => f_eie_ex2_dw_ov ,--o--feie + f_eie_ex2_wd_ov_if => f_eie_ex2_wd_ov_if ,--o--feie + f_eie_ex2_dw_ov_if => f_eie_ex2_dw_ov_if ,--o--feie + f_eie_ex2_lzo_expo(1 to 13) => f_eie_ex2_lzo_expo(1 to 13) ,--o--feie + f_eie_ex2_b_expo(1 to 13) => f_eie_ex2_b_expo(1 to 13) ,--o--feie + f_eie_ex2_use_bexp => f_eie_ex2_use_bexp ,--o--feie + f_eie_ex2_tbl_expo(1 to 13) => f_eie_ex2_tbl_expo(1 to 13) ,--o--feie + f_eie_ex3_iexp(1 to 13) => f_eie_ex3_iexp(1 to 13) );--o--feie +------------------------------------------------------------- fuq_eie.vhdl + + + +feov : entity WORK.fuq_eov(fuq_eov) generic map( expand_type => expand_type) port map( -- fuq_eov.vhdl +------------------------------------------------------------- fuq_eov.vhdl + vdd => vdd ,--i-- + gnd => gnd ,--i-- + nclk => nclk ,--i-- + clkoff_b => clkoff_b ,--i-- + act_dis => act_dis ,--i-- + flush => flush ,--i-- + --d_mode => d_mode ,--i-- + delay_lclkr => delay_lclkr(4 to 5) ,--i-- + mpw1_b => mpw1_b(4 to 5) ,--i-- + mpw2_b => mpw2_b(0 to 1) ,--i-- + thold_1 => perv_eov_thold_1 ,--i-- + sg_1 => perv_eov_sg_1 ,--i-- + fpu_enable => perv_eov_fpu_enable ,--i-- + + f_eov_si => scan_in(3) ,--i--feov + f_eov_so => scan_out(3) ,--o--feov + ex2_act_b => f_pic_eov_ex2_act_b ,--i--feov + f_tbl_ex4_unf_expo => f_tbl_ex4_unf_expo ,--i--feov + f_tbe_ex3_may_ov => f_tbe_ex3_may_ov ,--i--feov + f_tbe_ex3_expo(1 to 13) => f_tbe_ex3_res_expo(1 to 13) ,--i--feov + f_pic_ex3_sel_est => f_pic_ex3_sel_est ,--i--feov + f_eie_ex3_iexp(1 to 13) => f_eie_ex3_iexp(1 to 13) ,--i--feov + f_pic_ex3_sp_b => f_pic_ex3_sp_b ,--i--feov + f_lza_ex4_sh_rgt_en_eov => f_lza_ex4_sh_rgt_en_eov ,--i--feov + f_pic_ex4_oe => f_pic_ex4_oe ,--i--feov + f_pic_ex4_ue => f_pic_ex4_ue ,--i--feov + f_pic_ex4_ov_en => f_pic_ex4_ov_en ,--i--feov + f_pic_ex4_uf_en => f_pic_ex4_uf_en ,--i--feov + f_pic_ex4_spec_sel_k_e => f_pic_ex4_spec_sel_k_e ,--i--feov + f_pic_ex4_spec_sel_k_f => f_pic_ex4_spec_sel_k_f ,--i--feov + f_pic_ex4_sel_ov_spec => tidn ,--i--feov UNUSED DELETE + + f_pic_ex4_to_int_ov_all => f_pic_ex4_to_int_ov_all ,--i--feov + + f_lza_ex4_no_lza_edge => f_lza_ex4_no_lza_edge ,--i--feov + f_lza_ex4_lza_amt_eov(0 to 7) => f_lza_ex4_lza_amt_eov(0 to 7) ,--i--feov + f_nrm_ex4_extra_shift => f_nrm_ex4_extra_shift ,--i--feov + f_eov_ex4_may_ovf => f_eov_ex4_may_ovf ,--o--feov + f_eov_ex5_sel_k_f => f_eov_ex5_sel_k_f ,--o--feov + f_eov_ex5_sel_k_e => f_eov_ex5_sel_k_e ,--o--feov + f_eov_ex5_sel_kif_f => f_eov_ex5_sel_kif_f ,--o--feov + f_eov_ex5_sel_kif_e => f_eov_ex5_sel_kif_e ,--o--feov + f_eov_ex5_unf_expo => f_eov_ex5_unf_expo ,--o--feov + f_eov_ex5_ovf_expo => f_eov_ex5_ovf_expo ,--o--feov + f_eov_ex5_ovf_if_expo => f_eov_ex5_ovf_if_expo ,--o--feov + f_eov_ex5_expo_p0(1 to 13) => f_eov_ex5_expo_p0(1 to 13) ,--o--feov + f_eov_ex5_expo_p1(1 to 13) => f_eov_ex5_expo_p1(1 to 13) ,--o--feov + f_eov_ex5_expo_p0_ue1oe1(3 to 7) => f_eov_ex5_expo_p0_ue1oe1(3 to 7) ,--o--feov + f_eov_ex5_expo_p1_ue1oe1(3 to 7) => f_eov_ex5_expo_p1_ue1oe1(3 to 7) );--o--feov +------------------------------------------------------------- fuq_eov.vhdl + + +fmul : entity WORK.fuq_mul(fuq_mul) generic map( expand_type => expand_type) port map( -- fuq_mul.vhdl +------------------------------------------------------------- fuq_mul.vhdl + vdd => vdd ,--i-- + gnd => gnd ,--i-- + nclk => nclk ,--i-- + clkoff_b => clkoff_b ,--i-- + act_dis => act_dis ,--i-- + flush => flush ,--i-- + delay_lclkr => delay_lclkr(2) ,--i-- + mpw1_b => mpw1_b(2) ,--i-- + mpw2_b => mpw2_b(0) ,--i-- + thold_1 => perv_mul_thold_1 ,--i-- + sg_1 => perv_mul_sg_1 ,--i-- + fpu_enable => perv_mul_fpu_enable ,--i-- + + f_mul_si => scan_in(4) ,--i--fmul + f_mul_so => scan_out(4) ,--o--fmul + ex1_act => f_pic_mul_ex1_act ,--i--fmul + f_fmt_ex1_a_frac(0 to 52) => f_byp_mul_ex1_a_frac(0 to 52) ,--i--fmul + f_fmt_ex1_a_frac_17 => f_byp_mul_ex1_a_frac_17 ,--i--fmul + f_fmt_ex1_a_frac_35 => f_byp_mul_ex1_a_frac_35 ,--i--fmul + f_fmt_ex1_c_frac(0 to 53) => f_byp_mul_ex1_c_frac(0 to 53) ,--i--fmul + f_mul_ex2_sum(1 to 108) => f_mul_ex2_sum(1 to 108) ,--o--fmul + f_mul_ex2_car(1 to 108) => f_mul_ex2_car(1 to 108) );--o--fmul +------------------------------------------------------------- fuq_mul.vhdl + + +falg : entity WORK.fuq_alg(fuq_alg) generic map( expand_type => expand_type) port map( -- fuq_alg.vhdl +------------------------------------------------------------- fuq_alg.vhdl + vdd => vdd ,--i-- + gnd => gnd ,--i-- + nclk => nclk ,--i-- + clkoff_b => clkoff_b ,--i-- + act_dis => act_dis ,--i-- + flush => flush ,--i-- + delay_lclkr => delay_lclkr(1 to 3) ,--i-- + mpw1_b => mpw1_b(1 to 3) ,--i-- + mpw2_b => mpw2_b(0 to 0) ,--i-- + thold_1 => perv_alg_thold_1 ,--i-- + sg_1 => perv_alg_sg_1 ,--i-- + fpu_enable => perv_alg_fpu_enable ,--i-- + + f_alg_si => scan_in(5) ,--i--falg + f_alg_so => scan_out(5) ,--o--falg + rf1_act => f_dcd_rf1_act ,--i--falg + ex1_act => f_pic_alg_ex1_act ,--i--falg + f_dcd_rf1_sp => f_dcd_rf1_sp ,--i--falg + + f_pic_ex1_frsp_ue1 => f_pic_ex1_frsp_ue1 ,--i--feie WRONG cycle (move to ex2) + + f_byp_alg_ex1_b_frac(0 to 52) => f_byp_alg_ex1_b_frac(0 to 52) ,--i--falg + f_byp_alg_ex1_b_sign => f_byp_alg_ex1_b_sign ,--i--falg + f_byp_alg_ex1_b_expo(1 to 13) => f_byp_alg_ex1_b_expo(1 to 13) ,--i--falg + f_byp_alg_ex1_a_expo(1 to 13) => f_byp_alg_ex1_a_expo(1 to 13) ,--i--falg + f_byp_alg_ex1_c_expo(1 to 13) => f_byp_alg_ex1_c_expo(1 to 13) ,--i--falg + + f_fmt_ex1_prod_zero => f_fmt_ex1_prod_zero ,--i--falg + f_fmt_ex1_b_zero => f_fmt_ex1_b_zero ,--i--falg + f_fmt_ex1_pass_sel => f_fmt_ex1_pass_sel ,--i--falg + f_fmt_ex2_pass_frac(0 to 52) => f_fmt_ex2_pass_frac(0 to 52) ,--i--falg + f_dcd_rf1_word_b => f_dcd_rf1_word_b ,--i--falg + f_dcd_rf1_uns_b => f_dcd_rf1_uns_b ,--i--falg + f_dcd_rf1_from_integer_b => f_dcd_rf1_from_integer_b ,--i--falg + f_dcd_rf1_to_integer_b => f_dcd_rf1_to_integer_b ,--i--falg + f_pic_ex1_rnd_to_int => f_pic_ex1_rnd_to_int ,--i--falg + f_pic_ex1_effsub_raw => f_pic_ex1_effsub_raw ,--i--falg + f_pic_ex1_sh_unf_ig_b => f_pic_ex1_sh_unf_ig_b ,--i--falg + f_pic_ex1_sh_unf_do => f_pic_ex1_sh_unf_do ,--i--falg + f_pic_ex1_sh_ovf_ig_b => f_pic_ex1_sh_ovf_ig_b ,--i--falg + f_pic_ex1_sh_ovf_do => f_pic_ex1_sh_ovf_do ,--i--falg + f_pic_ex2_rnd_nr => f_pic_ex2_rnd_nr ,--i--falg + f_pic_ex2_rnd_inf_ok => f_pic_ex2_rnd_inf_ok ,--i--falg + f_alg_ex1_sign_frmw => f_alg_ex1_sign_frmw ,--o--falg + f_alg_ex2_res(0 to 162) => f_alg_ex2_res(0 to 162) ,--o--falg + f_alg_ex2_sel_byp => f_alg_ex2_sel_byp ,--o--falg + f_alg_ex2_effsub_eac_b => f_alg_ex2_effsub_eac_b ,--o--falg + f_alg_ex2_prod_z => f_alg_ex2_prod_z ,--o--falg + f_alg_ex2_sh_unf => f_alg_ex2_sh_unf ,--o--falg + f_alg_ex2_sh_ovf => f_alg_ex2_sh_ovf ,--o--falg + f_alg_ex2_byp_nonflip => f_alg_ex2_byp_nonflip ,--o--falg + f_alg_ex3_frc_sel_p1 => f_alg_ex3_frc_sel_p1 ,--o--falg + f_alg_ex3_sticky => f_alg_ex3_sticky ,--o--falg + f_alg_ex3_int_fr => f_alg_ex3_int_fr ,--o--falg + f_alg_ex3_int_fi => f_alg_ex3_int_fi );--o--falg +------------------------------------------------------------- fuq_alg.vhdl + + + +fsa3 : entity WORK.fuq_sa3(fuq_sa3) generic map( expand_type => expand_type) port map( -- fuq_sa3.vhdl +------------------------------------------------------------- fuq_sa3.vhdl + vdd => vdd ,--i-- + gnd => gnd ,--i-- + nclk => nclk ,--i-- + clkoff_b => clkoff_b ,--i-- + act_dis => act_dis ,--i-- + flush => flush ,--i-- + --d_mode => d_mode ,--i-- + delay_lclkr => delay_lclkr(2 to 3) ,--i-- + mpw1_b => mpw1_b(2 to 3) ,--i-- + mpw2_b => mpw2_b(0 to 0) ,--i-- + thold_1 => perv_sa3_thold_1 ,--i-- + sg_1 => perv_sa3_sg_1 ,--i-- + fpu_enable => perv_sa3_fpu_enable ,--i-- + + f_sa3_si => scan_in(6) ,--i--fsa3 + f_sa3_so => scan_out(6) ,--o--fsa3 + ex1_act_b => f_pic_add_ex1_act_b ,--i--fsa3 + f_mul_ex2_sum(54 to 161) => f_mul_ex2_sum(1 to 108) ,--i--fsa3 + f_mul_ex2_car(54 to 161) => f_mul_ex2_car(1 to 108) ,--i--fsa3 + f_alg_ex2_res(0 to 162) => f_alg_ex2_res(0 to 162) ,--i--fsa3 + f_sa3_ex3_s_lza(0 to 162) => f_sa3_ex3_s_lza(0 to 162) ,--o--fsa3 + f_sa3_ex3_c_lza(53 to 161) => f_sa3_ex3_c_lza(53 to 161) ,--o--fsa3 + f_sa3_ex3_s_add(0 to 162) => f_sa3_ex3_s_add(0 to 162) ,--o--fsa3 + f_sa3_ex3_c_add(53 to 161) => f_sa3_ex3_c_add(53 to 161) );--o--fsa3 +------------------------------------------------------------- fuq_sa3.vhdl + + + +fadd : entity WORK.fuq_add(fuq_add) generic map( expand_type => expand_type) port map( -- fuq_add.vhdl +------------------------------------------------------------- fuq_add.vhdl + vdd => vdd ,--i-- + gnd => gnd ,--i-- + nclk => nclk ,--i-- + clkoff_b => clkoff_b ,--i-- + act_dis => act_dis ,--i-- + flush => flush ,--i-- + --d_mode => d_mode ,--i-- + delay_lclkr => delay_lclkr(3 to 4) ,--i-- + mpw1_b => mpw1_b(3 to 4) ,--i-- + mpw2_b => mpw2_b(0 to 0) ,--i-- + thold_1 => perv_add_thold_1 ,--i-- + sg_1 => perv_add_sg_1 ,--i-- + fpu_enable => perv_add_fpu_enable ,--i-- + + f_add_si => scan_in(7) ,--i--fadd + f_add_so => scan_out(7) ,--o--fadd + ex1_act_b => f_pic_add_ex1_act_b ,--i--fadd + f_sa3_ex3_s(0 to 162) => f_sa3_ex3_s_add(0 to 162) ,--i--fadd + f_sa3_ex3_c(53 to 161) => f_sa3_ex3_c_add(53 to 161) ,--i--fadd + f_alg_ex3_frc_sel_p1 => f_alg_ex3_frc_sel_p1 ,--i--fadd + f_alg_ex3_sticky => f_alg_ex3_sticky ,--i--fadd + f_alg_ex2_effsub_eac_b => f_alg_ex2_effsub_eac_b ,--i--fadd + f_alg_ex2_prod_z => f_alg_ex2_prod_z ,--i--fadd + f_pic_ex3_is_gt => f_pic_ex3_is_gt ,--i--fadd + f_pic_ex3_is_lt => f_pic_ex3_is_lt ,--i--fadd + f_pic_ex3_is_eq => f_pic_ex3_is_eq ,--i--fadd + f_pic_ex3_is_nan => f_pic_ex3_is_nan ,--i--fadd + f_pic_ex3_cmp_sgnpos => f_pic_ex3_cmp_sgnpos ,--i--fadd + f_pic_ex3_cmp_sgnneg => f_pic_ex3_cmp_sgnneg ,--i--fadd + f_add_ex4_res(0 to 162) => f_add_ex4_res(0 to 162) ,--o--fadd + f_add_ex4_flag_nan => f_add_ex4_flag_nan ,--o--fadd + f_add_ex4_flag_gt => f_add_ex4_flag_gt ,--o--fadd + f_add_ex4_flag_lt => f_add_ex4_flag_lt ,--o--fadd + f_add_ex4_flag_eq => f_add_ex4_flag_eq ,--o--fadd + f_add_ex4_fpcc_iu(0 to 3) => f_add_ex4_fpcc_iu(0 to 3) ,--o--fadd + f_add_ex4_sign_carry => f_add_ex4_sign_carry ,--o--fadd + f_add_ex4_to_int_ovf_wd(0 to 1) => f_add_ex4_to_int_ovf_wd(0 to 1) ,--o--fadd + f_add_ex4_to_int_ovf_dw(0 to 1) => f_add_ex4_to_int_ovf_dw(0 to 1) ,--o--fadd + f_add_ex4_sticky => f_add_ex4_sticky );--o--fadd +------------------------------------------------------------- fuq_add.vhdl + + + +flze : entity WORK.fuq_lze(fuq_lze) generic map( expand_type => expand_type) port map( -- fuq_lze.vhdl +------------------------------------------------------------- fuq_lze.vhdl + vdd => vdd ,--i-- + gnd => gnd ,--i-- + nclk => nclk ,--i-- + clkoff_b => clkoff_b ,--i-- + act_dis => act_dis ,--i-- + flush => flush ,--i-- + --d_mode => d_mode ,--i-- + delay_lclkr => delay_lclkr(2 to 3) ,--i-- + mpw1_b => mpw1_b(2 to 3) ,--i-- + mpw2_b => mpw2_b(0 to 0) ,--i-- + thold_1 => perv_lza_thold_1 ,--i-- + sg_1 => perv_lza_sg_1 ,--i-- + fpu_enable => perv_lza_fpu_enable ,--i-- + + f_lze_si => scan_in(8) ,--i--flze + f_lze_so => scan_out(8) ,--o--flze + ex1_act_b => f_pic_lza_ex1_act_b ,--i--flze + f_eie_ex2_lzo_expo(1 to 13) => f_eie_ex2_lzo_expo(1 to 13) ,--i--flze + f_eie_ex2_b_expo(1 to 13) => f_eie_ex2_b_expo(1 to 13) ,--i--flze + f_pic_ex2_est_recip => f_pic_ex2_est_recip ,--i--flze + f_pic_ex2_est_rsqrt => f_pic_ex2_est_rsqrt ,--i--flze + f_alg_ex2_byp_nonflip => f_alg_ex2_byp_nonflip ,--i--flze + f_eie_ex2_use_bexp => f_eie_ex2_use_bexp ,--i--flze + f_pic_ex2_b_valid => f_pic_ex2_b_valid ,--i--flze + f_pic_ex2_lzo_dis_prod => f_pic_ex2_lzo_dis_prod ,--i--flze + f_pic_ex2_sp_lzo => f_pic_ex2_sp_lzo ,--i--flze + f_pic_ex2_frsp_ue1 => f_pic_ex2_frsp_ue1 ,--i--flze + f_fmt_ex2_pass_msb_dp => f_fmt_ex2_pass_frac(0) ,--i--flze + f_alg_ex2_sel_byp => f_alg_ex2_sel_byp ,--i--flze + f_pic_ex2_to_integer => f_pic_ex2_to_integer ,--i--flze + f_pic_ex2_prenorm => f_pic_ex2_prenorm ,--i--flze + + + f_lze_ex2_lzo_din(0 to 162) => f_lze_ex2_lzo_din(0 to 162) ,--o--flze + f_lze_ex3_sh_rgt_amt(0 to 7) => f_lze_ex3_sh_rgt_amt(0 to 7) ,--o--flze + f_lze_ex3_sh_rgt_en => f_lze_ex3_sh_rgt_en );--o--flze + +------------------------------------------------------------- fuq_lze.vhdl + + +flza : entity WORK.fuq_lza(fuq_lza) generic map( expand_type => expand_type) port map( -- fuq_lza.vhdl +------------------------------------------------------------- fuq_lza.vhdl + vdd => vdd ,--i-- + gnd => gnd ,--i-- + nclk => nclk ,--i-- + clkoff_b => clkoff_b ,--i-- + act_dis => act_dis ,--i-- + flush => flush ,--i-- + --d_mode => d_mode ,--i-- + delay_lclkr => delay_lclkr(3 to 4) ,--i-- + mpw1_b => mpw1_b(3 to 4) ,--i-- + mpw2_b => mpw2_b(0 to 0) ,--i-- + thold_1 => perv_lza_thold_1 ,--i-- + sg_1 => perv_lza_sg_1 ,--i-- + fpu_enable => perv_lza_fpu_enable ,--i-- + + f_lza_si => scan_in(9) ,--i--flza + f_lza_so => scan_out(9) ,--o--flza + ex1_act_b => f_pic_lza_ex1_act_b ,--i--flza + f_sa3_ex3_s(0 to 162) => f_sa3_ex3_s_lza(0 to 162) ,--i--flza + f_sa3_ex3_c(53 to 161) => f_sa3_ex3_c_lza(53 to 161) ,--i--flza + f_alg_ex2_effsub_eac_b => f_alg_ex2_effsub_eac_b ,--i--flza + + f_lze_ex2_lzo_din(0 to 162) => f_lze_ex2_lzo_din(0 to 162) ,--i--flza + f_lze_ex3_sh_rgt_amt(0 to 7) => f_lze_ex3_sh_rgt_amt(0 to 7) ,--i--flza + f_lze_ex3_sh_rgt_en => f_lze_ex3_sh_rgt_en ,--i--flza + + f_lza_ex4_no_lza_edge => f_lza_ex4_no_lza_edge ,--o--flza + f_lza_ex4_lza_amt(0 to 7) => f_lza_ex4_lza_amt(0 to 7) ,--o--flza + f_lza_ex4_sh_rgt_en => f_lza_ex4_sh_rgt_en ,--o--flza + f_lza_ex4_sh_rgt_en_eov => f_lza_ex4_sh_rgt_en_eov ,--o--flza + f_lza_ex4_lza_dcd64_cp1(0 to 2) => f_lza_ex4_lza_dcd64_cp1(0 to 2) ,--o--flza + f_lza_ex4_lza_dcd64_cp2(0 to 1) => f_lza_ex4_lza_dcd64_cp2(0 to 1) ,--o--flza + f_lza_ex4_lza_dcd64_cp3(0) => f_lza_ex4_lza_dcd64_cp3(0) ,--o--flza + + f_lza_ex4_lza_amt_eov(0 to 7) => f_lza_ex4_lza_amt_eov(0 to 7) );--o--flza +------------------------------------------------------------- fuq_lza.vhdl + + +fnrm : entity WORK.fuq_nrm(fuq_nrm) generic map( expand_type => expand_type) port map( -- fuq_nrm.vhdl +------------------------------------------------------------- fuq_nrm.vhdl + vdd => vdd ,--i-- + gnd => gnd ,--i-- + nclk => nclk ,--i-- + clkoff_b => clkoff_b ,--i-- + act_dis => act_dis ,--i-- + flush => flush ,--i-- + --d_mode => d_mode ,--i-- + delay_lclkr => delay_lclkr(4 to 5) ,--i-- + mpw1_b => mpw1_b(4 to 5) ,--i-- + mpw2_b => mpw2_b(0 to 1) ,--i-- + thold_1 => perv_nrm_thold_1 ,--i-- + sg_1 => perv_nrm_sg_1 ,--i-- + fpu_enable => perv_nrm_fpu_enable ,--i-- + + f_nrm_si => scan_in(10) ,--i--fnrm + f_nrm_so => scan_out(10) ,--o--fnrm + ex3_act_b => f_pic_nrm_ex3_act_b ,--i--fnrm + + f_lza_ex4_sh_rgt_en => f_lza_ex4_sh_rgt_en ,--i--fnrm + f_lza_ex4_lza_amt_cp1 => f_lza_ex4_lza_amt(0 to 7) ,--i--fnrm + f_lza_ex4_lza_dcd64_cp1(0 to 2) => f_lza_ex4_lza_dcd64_cp1(0 to 2) ,--o--fnrm + f_lza_ex4_lza_dcd64_cp2(0 to 1) => f_lza_ex4_lza_dcd64_cp2(0 to 1) ,--o--fnrm + f_lza_ex4_lza_dcd64_cp3(0) => f_lza_ex4_lza_dcd64_cp3(0) ,--o--fnrm + + f_add_ex4_res(0 to 162) => f_add_ex4_res(0 to 162) ,--i--fnrm + f_add_ex4_sticky => f_add_ex4_sticky ,--i--fnrm + f_pic_ex4_byp_prod_nz => f_pic_ex4_byp_prod_nz ,--i--fnrm + f_nrm_ex5_res(0 to 52) => f_nrm_ex5_res(0 to 52) ,--o--fnrm + f_nrm_ex5_int_lsbs(1 to 12) => f_nrm_ex5_int_lsbs(1 to 12) ,--o--fnrm + f_nrm_ex5_int_sign => f_nrm_ex5_int_sign ,--o--fnrm + f_nrm_ex5_nrm_sticky_dp => f_nrm_ex5_nrm_sticky_dp ,--o--fnrm + f_nrm_ex5_nrm_guard_dp => f_nrm_ex5_nrm_guard_dp ,--o--fnrm + f_nrm_ex5_nrm_lsb_dp => f_nrm_ex5_nrm_lsb_dp ,--o--fnrm + f_nrm_ex5_nrm_sticky_sp => f_nrm_ex5_nrm_sticky_sp ,--o--fnrm + f_nrm_ex5_nrm_guard_sp => f_nrm_ex5_nrm_guard_sp ,--o--fnrm + f_nrm_ex5_nrm_lsb_sp => f_nrm_ex5_nrm_lsb_sp ,--o--fnrm + f_nrm_ex5_exact_zero => f_nrm_ex5_exact_zero ,--o--fnrm + f_nrm_ex4_extra_shift => f_nrm_ex4_extra_shift ,--o--fnrm + f_nrm_ex5_fpscr_wr_dat_dfp(0 to 3) => f_nrm_ex5_fpscr_wr_dat_dfp(0 to 3) ,--o--fnrm + f_nrm_ex5_fpscr_wr_dat(0 to 31) => f_nrm_ex5_fpscr_wr_dat(0 to 31) );--o--fnrm +------------------------------------------------------------- fuq_nrm.vhdl + + + +frnd : entity WORK.fuq_rnd(fuq_rnd) generic map( expand_type => expand_type) port map( -- fuq_rnd.vhdl +------------------------------------------------------------- fuq_rnd.vhdl + vdd => vdd ,--i-- + gnd => gnd ,--i-- + nclk => nclk ,--i-- + clkoff_b => clkoff_b ,--i-- + act_dis => act_dis ,--i-- + flush => flush ,--i-- + --d_mode => d_mode ,--i-- + delay_lclkr => delay_lclkr(5 to 6) ,--i-- + mpw1_b => mpw1_b(5 to 6) ,--i-- + mpw2_b => mpw2_b(1 to 1) ,--i-- + thold_1 => perv_rnd_thold_1 ,--i-- + sg_1 => perv_rnd_sg_1 ,--i-- + fpu_enable => perv_rnd_fpu_enable ,--i-- + + f_rnd_si => scan_in(11) ,--i--frnd + f_rnd_so => scan_out(11) ,--o--frnd + ex3_act_b => f_pic_rnd_ex3_act_b ,--i--frnd + f_pic_ex4_sel_est_b => f_pic_ex4_sel_est_b ,--i--frnd + f_tbl_ex5_est_frac(0 to 26) => f_tbl_ex5_est_frac(0 to 26) ,--i--frnd + f_nrm_ex5_res(0 to 52) => f_nrm_ex5_res(0 to 52) ,--i--frnd + f_nrm_ex5_int_lsbs(1 to 12) => f_nrm_ex5_int_lsbs(1 to 12) ,--i--frnd + f_nrm_ex5_int_sign => f_nrm_ex5_int_sign ,--i--frnd + f_nrm_ex5_nrm_sticky_dp => f_nrm_ex5_nrm_sticky_dp ,--i--frnd + f_nrm_ex5_nrm_guard_dp => f_nrm_ex5_nrm_guard_dp ,--i--frnd + f_nrm_ex5_nrm_lsb_dp => f_nrm_ex5_nrm_lsb_dp ,--i--frnd + f_nrm_ex5_nrm_sticky_sp => f_nrm_ex5_nrm_sticky_sp ,--i--frnd + f_nrm_ex5_nrm_guard_sp => f_nrm_ex5_nrm_guard_sp ,--i--frnd + f_nrm_ex5_nrm_lsb_sp => f_nrm_ex5_nrm_lsb_sp ,--i--frnd + f_nrm_ex5_exact_zero => f_nrm_ex5_exact_zero ,--i--frnd + f_pic_ex5_invert_sign => f_pic_ex5_invert_sign ,--i--frnd + f_pic_ex5_en_exact_zero => f_pic_ex5_en_exact_zero ,--i--frnd + f_pic_ex5_k_nan => f_pic_ex5_k_nan ,--i--frnd + f_pic_ex5_k_inf => f_pic_ex5_k_inf ,--i--frnd + f_pic_ex5_k_max => f_pic_ex5_k_max ,--i--frnd + f_pic_ex5_k_zer => f_pic_ex5_k_zer ,--i--frnd + f_pic_ex5_k_one => f_pic_ex5_k_one ,--i--frnd + f_pic_ex5_k_int_maxpos => f_pic_ex5_k_int_maxpos ,--i--frnd + f_pic_ex5_k_int_maxneg => f_pic_ex5_k_int_maxneg ,--i--frnd + f_pic_ex5_k_int_zer => f_pic_ex5_k_int_zer ,--i--frnd + f_tbl_ex5_recip_den => f_tbl_ex5_recip_den ,--i--frnd + f_pic_ex4_rnd_ni_b => f_pic_ex4_rnd_ni_b ,--i--frnd + f_pic_ex4_rnd_nr_b => f_pic_ex4_rnd_nr_b ,--i--frnd + f_pic_ex4_rnd_inf_ok_b => f_pic_ex4_rnd_inf_ok_b ,--i--frnd + f_pic_ex5_uc_inc_lsb => f_pic_ex5_uc_inc_lsb ,--i--frnd + f_pic_ex5_uc_guard => f_pic_ex5_uc_guard ,--i--frnd + f_pic_ex5_uc_sticky => f_pic_ex5_uc_sticky ,--i--frnd + f_pic_ex5_uc_g_v => f_pic_ex5_uc_g_v ,--i--frnd + f_pic_ex5_uc_s_v => f_pic_ex5_uc_s_v ,--i--frnd + f_pic_ex4_sel_fpscr_b => f_pic_ex4_sel_fpscr_b ,--i--frnd + f_pic_ex4_to_integer_b => f_pic_ex4_to_integer_b ,--i--frnd + f_pic_ex4_word_b => f_pic_ex4_word_b ,--i--frnd + f_pic_ex4_uns_b => f_pic_ex4_uns_b ,--i--frnd + f_pic_ex4_sp_b => f_pic_ex4_sp_b ,--i--frnd + f_pic_ex4_spec_inf_b => f_pic_ex4_spec_inf_b ,--i--frnd + f_pic_ex4_quiet_b => f_pic_ex4_quiet_b ,--i--frnd + f_pic_ex4_nj_deno => f_pic_ex4_nj_deno ,--i--frnd + f_pic_ex4_unf_en_ue0_b => f_pic_ex4_unf_en_ue0_b ,--i--frnd + f_pic_ex4_unf_en_ue1_b => f_pic_ex4_unf_en_ue1_b ,--i--frnd + f_pic_ex4_ovf_en_oe0_b => f_pic_ex4_ovf_en_oe0_b ,--i--frnd + f_pic_ex4_ovf_en_oe1_b => f_pic_ex4_ovf_en_oe1_b ,--i--frnd + f_pic_ex5_round_sign => f_pic_ex5_round_sign ,--i--frnd + f_scr_ex5_fpscr_rd_dat_dfp(0 to 3) => f_scr_ex5_fpscr_rd_dat_dfp(0 to 3) ,--i--frnd + f_scr_ex5_fpscr_rd_dat(0 to 31) => f_scr_ex5_fpscr_rd_dat(0 to 31) ,--i--frnd + f_eov_ex5_sel_k_f => f_eov_ex5_sel_k_f ,--i--frnd + f_eov_ex5_sel_k_e => f_eov_ex5_sel_k_e ,--i--frnd + f_eov_ex5_sel_kif_f => f_eov_ex5_sel_kif_f ,--i--frnd + f_eov_ex5_sel_kif_e => f_eov_ex5_sel_kif_e ,--i--frnd + f_eov_ex5_ovf_expo => f_eov_ex5_ovf_expo ,--i--frnd + f_eov_ex5_ovf_if_expo => f_eov_ex5_ovf_if_expo ,--i--frnd + f_eov_ex5_unf_expo => f_eov_ex5_unf_expo ,--i--frnd + f_pic_ex5_frsp => f_pic_ex5_frsp ,--i--frnd + f_eov_ex5_expo_p0(1 to 13) => f_eov_ex5_expo_p0(1 to 13) ,--i--frnd + f_eov_ex5_expo_p1(1 to 13) => f_eov_ex5_expo_p1(1 to 13) ,--i--frnd + f_eov_ex5_expo_p0_ue1oe1(3 to 7) => f_eov_ex5_expo_p0_ue1oe1(3 to 7) ,--i--frnd + f_eov_ex5_expo_p1_ue1oe1(3 to 7) => f_eov_ex5_expo_p1_ue1oe1(3 to 7) ,--i--frnd + f_gst_ex5_logexp_v => f_gst_ex5_logexp_v ,--i--frnd + f_gst_ex5_logexp_sign => f_gst_ex5_logexp_sign ,--i--frnd + f_gst_ex5_logexp_exp(1 to 11) => f_gst_ex5_logexp_exp(1 to 11) ,--i--frnd + f_gst_ex5_logexp_fract(0 to 19) => f_gst_ex5_logexp_fract(0 to 19) ,--i--frnd + f_mad_ex6_uc_sign => f_mad_ex6_uc_sign ,--o--frnd + f_mad_ex6_uc_zero => f_mad_ex6_uc_zero ,--o--frnd + f_rnd_ex6_res_sign => rnd_ex6_res_sign ,--o--frnd + f_rnd_ex6_res_expo(1 to 13) => rnd_ex6_res_expo(1 to 13) ,--o--frnd + f_rnd_ex6_res_frac(0 to 52) => rnd_ex6_res_frac(0 to 52) ,--o--frnd + f_rnd_ex6_flag_up => f_rnd_ex6_flag_up ,--o--frnd + f_rnd_ex6_flag_fi => f_rnd_ex6_flag_fi ,--o--frnd + f_rnd_ex6_flag_ox => f_rnd_ex6_flag_ox ,--o--frnd + f_rnd_ex6_flag_den => f_rnd_ex6_flag_den ,--o--frnd + f_rnd_ex6_flag_sgn => f_rnd_ex6_flag_sgn ,--o--frnd + f_rnd_ex6_flag_inf => f_rnd_ex6_flag_inf ,--o--frnd + f_rnd_ex6_flag_zer => f_rnd_ex6_flag_zer ,--o--frnd + f_rnd_ex6_flag_ux => f_rnd_ex6_flag_ux );--o--frnd +------------------------------------------------------------- fuq_rnd.vhdl + + + + f_rnd_ex6_res_sign <= rnd_ex6_res_sign ; + f_rnd_ex6_res_expo(1 to 13) <= rnd_ex6_res_expo(1 to 13) ; + f_rnd_ex6_res_frac(0 to 52) <= rnd_ex6_res_frac(0 to 52) ; + + +fgst : entity WORK.fuq_gst(fuq_gst) generic map( expand_type => expand_type) port map( -- fuq_gst.vhdl +------------------------------------------------------------- fuq_gst.vhdl + vdd => vdd ,--i-- + gnd => gnd ,--i-- + nclk => nclk ,--i-- + clkoff_b => clkoff_b ,--i-- + act_dis => act_dis ,--i-- + flush => flush ,--i-- + --d_mode => d_mode ,--i-- + delay_lclkr => delay_lclkr(2 to 5) ,--i-- + mpw1_b => mpw1_b(2 to 5) ,--i-- + mpw2_b => mpw2_b(0 to 1) ,--i-- + thold_1 => perv_rnd_thold_1 ,--i-- + sg_1 => perv_rnd_sg_1 ,--i-- + fpu_enable => perv_rnd_fpu_enable ,--i-- + + f_gst_si => scan_in(12) ,--i--fgst + f_gst_so => scan_out(12) ,--o--fgst + rf1_act => f_dcd_rf1_act ,--i--fgst (connect) + f_fmt_ex1_b_sign_gst => f_fmt_ex1_b_sign_gst ,--i--fgst + f_fmt_ex1_b_expo_gst_b(1 to 13) => f_fmt_ex1_b_expo_gst_b(1 to 13) ,--i--fgst + f_fmt_ex1_b_frac_gst(1 to 19) => f_fmt_ex1_b_frac(1 to 19) ,--i--fgst + f_pic_ex1_floges => f_pic_ex1_log2e ,--i--fgst + f_pic_ex1_fexptes => f_pic_ex1_pow2e ,--i--fgst + f_gst_ex5_logexp_v => f_gst_ex5_logexp_v ,--o--fgst + f_gst_ex5_logexp_sign => f_gst_ex5_logexp_sign ,--o--fgst + f_gst_ex5_logexp_exp(1 to 11) => f_gst_ex5_logexp_exp(1 to 11) ,--o--fgst + f_gst_ex5_logexp_fract(0 to 19) => f_gst_ex5_logexp_fract(0 to 19) );--o--fgst +------------------------------------------------------------- fuq_gst.vhdl + + + + +fpic : entity WORK.fuq_pic(fuq_pic) generic map( expand_type => expand_type) port map( -- fuq_pic.vhdl +------------------------------------------------------------- fuq_pic.vhdl + vdd => vdd ,--i-- + gnd => gnd ,--i-- + nclk => nclk ,--i-- + clkoff_b => clkoff_b ,--i-- + act_dis => act_dis ,--i-- + flush => flush ,--i-- + delay_lclkr => delay_lclkr(1 to 5) ,--i-- + mpw1_b => mpw1_b(1 to 5) ,--i-- + mpw2_b => mpw2_b(0 to 1) ,--i-- + thold_1 => perv_pic_thold_1 ,--i-- + sg_1 => perv_pic_sg_1 ,--i-- + fpu_enable => perv_pic_fpu_enable ,--i-- + + f_pic_si => scan_in(13) ,--i--fpic + f_pic_so => scan_out(13) ,--o--fpic + f_dcd_rf1_act => f_dcd_rf1_act ,--i--fpic + f_cr2_ex1_fpscr_shadow(0 to 7) => f_cr2_ex1_fpscr_shadow(0 to 7) ,--i--fpic + f_dcd_rf1_pow2e_b => f_dcd_rf1_pow2e_b ,--i--fpic + f_dcd_rf1_log2e_b => f_dcd_rf1_log2e_b ,--i--fpic + f_byp_pic_ex1_a_sign => f_byp_pic_ex1_a_sign ,--i--fpic + f_byp_pic_ex1_c_sign => f_byp_pic_ex1_c_sign ,--i--fpic + f_byp_pic_ex1_b_sign => f_byp_pic_ex1_b_sign ,--i--fpic + f_dcd_rf1_aop_valid => f_dcd_rf1_aop_valid ,--i--fpic + f_dcd_rf1_cop_valid => f_dcd_rf1_cop_valid ,--i--fpic + f_dcd_rf1_bop_valid => f_dcd_rf1_bop_valid ,--i--fpic + f_dcd_rf1_uc_ft_neg => f_dcd_rf1_uc_ft_neg ,--i--fpic + f_dcd_rf1_uc_ft_pos => f_dcd_rf1_uc_ft_pos ,--i--fpic + f_dcd_rf1_fsel_b => f_dcd_rf1_fsel_b ,--i--fpic + f_dcd_rf1_from_integer_b => f_dcd_rf1_from_integer_b ,--i--fpic + f_dcd_rf1_to_integer_b => f_dcd_rf1_to_integer_b ,--i--fpic + f_dcd_rf1_rnd_to_int_b => f_dcd_rf1_rnd_to_int_b ,--i--fpic + f_dcd_rf1_math_b => f_dcd_rf1_math_b ,--i--fpic + f_dcd_rf1_est_recip_b => f_dcd_rf1_est_recip_b ,--i--fpic + f_dcd_rf1_ftdiv => f_dcd_rf1_ftdiv ,--i--fpic + f_dcd_rf1_ftsqrt => f_dcd_rf1_ftsqrt ,--i--fpic + f_fmt_ex2_ae_ge_54 => f_fmt_ex2_ae_ge_54 ,--i--fpic + f_fmt_ex2_be_ge_54 => f_fmt_ex2_be_ge_54 ,--i--fpic + f_fmt_ex2_be_ge_2 => f_fmt_ex2_be_ge_2 ,--i--fpic + f_fmt_ex2_be_ge_2044 => f_fmt_ex2_be_ge_2044 ,--i--fpic + f_fmt_ex2_tdiv_rng_chk => f_fmt_ex2_tdiv_rng_chk ,--i--fpic + f_fmt_ex2_be_den => f_fmt_ex2_be_den ,--i--fpic + + f_dcd_rf1_est_rsqrt_b => f_dcd_rf1_est_rsqrt_b ,--i--fpic + f_dcd_rf1_move_b => f_dcd_rf1_move_b ,--i--fpic + f_dcd_rf1_prenorm_b => f_dcd_rf1_prenorm_b ,--i--fpic + f_dcd_rf1_frsp_b => f_dcd_rf1_frsp_b ,--i--fpic + f_dcd_rf1_sp => f_dcd_rf1_sp ,--i--fpic + f_dcd_rf1_sp_conv_b => f_dcd_rf1_sp_conv_b ,--i--fpic + f_dcd_rf1_word_b => f_dcd_rf1_word_b ,--i--fpic + f_dcd_rf1_uns_b => f_dcd_rf1_uns_b ,--i--fpic + f_dcd_rf1_sub_op_b => f_dcd_rf1_sub_op_b ,--i--fpic + f_dcd_rf1_op_rnd_v_b => f_dcd_rf1_op_rnd_v_b ,--i--fpic + f_dcd_rf1_op_rnd_b(0 to 1) => f_dcd_rf1_op_rnd_b(0 to 1) ,--i--fpic + f_dcd_rf1_inv_sign_b => f_dcd_rf1_inv_sign_b ,--i--fpic + f_dcd_rf1_sign_ctl_b(0 to 1) => f_dcd_rf1_sign_ctl_b(0 to 1) ,--i--fpic + f_dcd_rf1_sgncpy_b => f_dcd_rf1_sgncpy_b ,--i--fpic + f_dcd_rf1_nj_deno => f_dcd_rf1_nj_deno ,--i--fpic + f_dcd_rf1_mv_to_scr_b => f_dcd_rf1_mv_to_scr_b ,--i--fpic + f_dcd_rf1_mv_from_scr_b => f_dcd_rf1_mv_from_scr_b ,--i--fpic + f_dcd_rf1_compare_b => f_dcd_rf1_compare_b ,--i--fpic + f_dcd_rf1_ordered_b => f_dcd_rf1_ordered_b ,--i--fpic + f_alg_ex1_sign_frmw => f_alg_ex1_sign_frmw ,--i--fpic + f_dcd_rf1_force_excp_dis => f_dcd_rf1_force_excp_dis ,--i--fpic + f_pic_ex1_log2e => f_pic_ex1_log2e ,--i--fpic + f_pic_ex1_pow2e => f_pic_ex1_pow2e ,--i--fpic + f_fmt_ex1_bexpu_le126 => f_fmt_ex1_bexpu_le126 ,--i--fpic + f_fmt_ex1_gt126 => f_fmt_ex1_gt126 ,--i--fpic + f_fmt_ex1_ge128 => f_fmt_ex1_ge128 ,--i--fpic + f_fmt_ex1_inf_and_beyond_sp => f_fmt_ex1_inf_and_beyond_sp ,--i--fpic + f_fmt_ex1_sp_invalid => f_fmt_ex1_sp_invalid ,--i--fpic + f_fmt_ex1_a_zero => f_fmt_ex1_a_zero ,--i--fpic + f_fmt_ex1_a_expo_max => f_fmt_ex1_a_expo_max ,--i--fpic + f_fmt_ex1_a_frac_zero => f_fmt_ex1_a_frac_zero ,--i--fpic + f_fmt_ex1_a_frac_msb => f_fmt_ex1_a_frac_msb ,--i--fpic + f_fmt_ex1_c_zero => f_fmt_ex1_c_zero ,--i--fpic + f_fmt_ex1_c_expo_max => f_fmt_ex1_c_expo_max ,--i--fpic + f_fmt_ex1_c_frac_zero => f_fmt_ex1_c_frac_zero ,--i--fpic + f_fmt_ex1_c_frac_msb => f_fmt_ex1_c_frac_msb ,--i--fpic + f_fmt_ex1_b_zero => f_fmt_ex1_b_zero ,--i--fpic + f_fmt_ex1_b_expo_max => f_fmt_ex1_b_expo_max ,--i--fpic + f_fmt_ex1_b_frac_zero => f_fmt_ex1_b_frac_zero ,--i--fpic + f_fmt_ex1_b_frac_msb => f_fmt_ex1_b_frac_msb ,--i--fpic + f_fmt_ex1_prod_zero => f_fmt_ex1_prod_zero ,--i--fpic + f_fmt_ex2_pass_sign => f_fmt_ex2_pass_sign ,--i--fpic + f_fmt_ex2_pass_msb => f_fmt_ex2_pass_msb ,--i--fpic + f_fmt_ex1_b_frac_z32 => f_fmt_ex1_b_frac_z32 ,--i--fpic + f_fmt_ex1_b_imp => f_fmt_ex1_b_imp ,--i--fpic + f_eie_ex2_wd_ov => f_eie_ex2_wd_ov ,--i--fpic + f_eie_ex2_dw_ov => f_eie_ex2_dw_ov ,--i--fpic + f_eie_ex2_wd_ov_if => f_eie_ex2_wd_ov_if ,--i--fpic + f_eie_ex2_dw_ov_if => f_eie_ex2_dw_ov_if ,--i--fpic + f_eie_ex2_lt_bias => f_eie_ex2_lt_bias ,--i--fpic + f_eie_ex2_eq_bias_m1 => f_eie_ex2_eq_bias_m1 ,--i--fpic + f_alg_ex2_sel_byp => f_alg_ex2_sel_byp ,--i--fpic + f_alg_ex2_effsub_eac_b => f_alg_ex2_effsub_eac_b ,--i--fpic + f_alg_ex2_sh_unf => f_alg_ex2_sh_unf ,--i--fpic + f_alg_ex2_sh_ovf => f_alg_ex2_sh_ovf ,--i--fpic + f_alg_ex3_int_fr => f_alg_ex3_int_fr ,--i--fpic + f_alg_ex3_int_fi => f_alg_ex3_int_fi ,--i--fpic + f_eov_ex4_may_ovf => f_eov_ex4_may_ovf ,--i--fpic + f_add_ex4_fpcc_iu(0) => f_add_ex4_flag_lt ,--o--fadd + f_add_ex4_fpcc_iu(1) => f_add_ex4_flag_gt ,--o--fadd + f_add_ex4_fpcc_iu(2) => f_add_ex4_flag_eq ,--o--fadd + f_add_ex4_fpcc_iu(3) => f_add_ex4_flag_nan ,--o--fadd + f_add_ex4_sign_carry => f_add_ex4_sign_carry ,--i--fpic + f_dcd_rf1_div_beg => f_dcd_rf1_div_beg ,--i--fpic + f_dcd_rf1_sqrt_beg => f_dcd_rf1_sqrt_beg ,--i--fpic + f_pic_ex5_fpr_wr_dis_b => f_pic_ex5_fpr_wr_dis_b ,--o--fpic + f_add_ex4_to_int_ovf_wd(0 to 1) => f_add_ex4_to_int_ovf_wd(0 to 1) ,--i--fpic + f_add_ex4_to_int_ovf_dw(0 to 1) => f_add_ex4_to_int_ovf_dw(0 to 1) ,--i--fpic + f_pic_ex1_ftdiv => f_pic_ex1_ftdiv ,--o--fpic + f_pic_ex1_flush_en_sp => f_pic_ex1_flush_en_sp ,--o--fpic + f_pic_ex1_flush_en_dp => f_pic_ex1_flush_en_dp ,--o--fpic + f_pic_ex1_rnd_to_int => f_pic_ex1_rnd_to_int ,--o--fpic + + f_pic_fmt_ex1_act => f_pic_fmt_ex1_act ,--o--fpic + f_pic_eie_ex1_act => f_pic_eie_ex1_act ,--o--fpic + f_pic_mul_ex1_act => f_pic_mul_ex1_act ,--o--fpic + f_pic_alg_ex1_act => f_pic_alg_ex1_act ,--o--fpic + f_pic_cr2_ex1_act => f_pic_cr2_ex1_act ,--o--fpic + f_pic_tbl_ex1_act => f_pic_tbl_ex1_act ,--o--fpic + + f_pic_add_ex1_act_b => f_pic_add_ex1_act_b ,--o--fpic + f_pic_lza_ex1_act_b => f_pic_lza_ex1_act_b ,--o--fpic + f_pic_eov_ex2_act_b => f_pic_eov_ex2_act_b ,--o--fpic + f_pic_nrm_ex3_act_b => f_pic_nrm_ex3_act_b ,--o--fpic + f_pic_rnd_ex3_act_b => f_pic_rnd_ex3_act_b ,--o--fpic + f_pic_scr_ex2_act_b => f_pic_scr_ex2_act_b ,--o--fpic + f_pic_ex1_effsub_raw => f_pic_ex1_effsub_raw ,--o--fpic + f_pic_ex3_sel_est => f_pic_ex3_sel_est ,--o--fpic + f_pic_ex1_from_integer => f_pic_ex1_from_integer ,--o--fpic + f_pic_ex2_ue1 => f_pic_ex2_ue1 ,--o--fpic + f_pic_ex2_frsp_ue1 => f_pic_ex2_frsp_ue1 ,--o--fpic + f_pic_ex1_frsp_ue1 => f_pic_ex1_frsp_ue1 ,--o--fpic --wrong cycle (temporary) + f_pic_ex1_fsel => f_pic_ex1_fsel ,--o--fpic + f_pic_ex1_sh_ovf_do => f_pic_ex1_sh_ovf_do ,--o--fpic + f_pic_ex1_sh_ovf_ig_b => f_pic_ex1_sh_ovf_ig_b ,--o--fpic + f_pic_ex1_sh_unf_do => f_pic_ex1_sh_unf_do ,--o--fpic + f_pic_ex1_sh_unf_ig_b => f_pic_ex1_sh_unf_ig_b ,--o--fpic + f_pic_ex2_est_recip => f_pic_ex2_est_recip ,--o--fpic + f_pic_ex2_est_rsqrt => f_pic_ex2_est_rsqrt ,--o--fpic + f_pic_ex2_force_sel_bexp => f_pic_ex2_force_sel_bexp ,--o--fpic + f_pic_ex2_lzo_dis_prod => f_pic_ex2_lzo_dis_prod ,--o--fpic + f_pic_ex2_sp_b => f_pic_ex2_sp_b ,--o--fpic + f_pic_ex2_sp_lzo => f_pic_ex2_sp_lzo ,--o--fpic + f_pic_ex2_to_integer => f_pic_ex2_to_integer ,--o--fpic + f_pic_ex2_prenorm => f_pic_ex2_prenorm ,--o--fpic + f_pic_ex2_b_valid => f_pic_ex2_b_valid ,--i--fpic + f_pic_ex2_rnd_nr => f_pic_ex2_rnd_nr ,--i--falg + f_pic_ex2_rnd_inf_ok => f_pic_ex2_rnd_inf_ok ,--i--falg + f_pic_ex2_math_bzer_b => f_pic_ex2_math_bzer_b ,--o--fpic + f_pic_ex3_cmp_sgnneg => f_pic_ex3_cmp_sgnneg ,--o--fpic + f_pic_ex3_cmp_sgnpos => f_pic_ex3_cmp_sgnpos ,--o--fpic + f_pic_ex3_is_eq => f_pic_ex3_is_eq ,--o--fpic + f_pic_ex3_is_gt => f_pic_ex3_is_gt ,--o--fpic + f_pic_ex3_is_lt => f_pic_ex3_is_lt ,--o--fpic + f_pic_ex3_is_nan => f_pic_ex3_is_nan ,--o--fpic + f_pic_ex3_sp_b => f_pic_ex3_sp_b ,--o--fpic + f_dcd_rf1_uc_mid => f_dcd_rf1_uc_mid ,--i--fpic + f_dcd_rf1_uc_end => f_dcd_rf1_uc_end ,--i--fpic + f_dcd_rf1_uc_special => f_dcd_rf1_uc_special ,--i--fpic + f_mad_ex2_uc_a_expo_den_sp => f_mad_ex2_uc_a_expo_den_sp ,--i--fpic + f_mad_ex2_uc_a_expo_den => f_mad_ex2_uc_a_expo_den ,--i--fpic + f_dcd_ex2_uc_zx => f_dcd_ex2_uc_zx ,--i--fpic + f_dcd_ex2_uc_vxidi => f_dcd_ex2_uc_vxidi ,--i--fpic + f_dcd_ex2_uc_vxzdz => f_dcd_ex2_uc_vxzdz ,--i--fpic + f_dcd_ex2_uc_vxsqrt => f_dcd_ex2_uc_vxsqrt ,--i--fpic + f_dcd_ex2_uc_vxsnan => f_dcd_ex2_uc_vxsnan ,--i--fpic + f_mad_ex3_uc_special => f_mad_ex3_uc_special ,--o--fpic + f_mad_ex3_uc_zx => f_mad_ex3_uc_zx ,--o--fpic + f_mad_ex3_uc_vxidi => f_mad_ex3_uc_vxidi ,--o--fpic + f_mad_ex3_uc_vxzdz => f_mad_ex3_uc_vxzdz ,--o--fpic + f_mad_ex3_uc_vxsqrt => f_mad_ex3_uc_vxsqrt ,--o--fpic + f_mad_ex3_uc_vxsnan => f_mad_ex3_uc_vxsnan ,--o--fpic + f_mad_ex3_uc_res_sign => f_mad_ex3_uc_res_sign ,--o--fpic + f_mad_ex3_uc_round_mode(0 to 1) => f_mad_ex3_uc_round_mode(0 to 1) ,--o--fpic + f_pic_ex4_byp_prod_nz => f_pic_ex4_byp_prod_nz ,--o--fpic + f_pic_ex4_sel_est_b => f_pic_ex4_sel_est_b ,--o--fpic + f_pic_ex4_nj_deno => f_pic_ex4_nj_deno ,--o--fpic + f_pic_ex4_oe => f_pic_ex4_oe ,--o--fpic + f_pic_ex4_ov_en => f_pic_ex4_ov_en ,--o--fpic + f_pic_ex4_ovf_en_oe0_b => f_pic_ex4_ovf_en_oe0_b ,--o--fpic + f_pic_ex4_ovf_en_oe1_b => f_pic_ex4_ovf_en_oe1_b ,--o--fpic + f_pic_ex4_quiet_b => f_pic_ex4_quiet_b ,--o--fpic + f_pic_ex4_rnd_inf_ok_b => f_pic_ex4_rnd_inf_ok_b ,--o--fpic + f_pic_ex4_rnd_ni_b => f_pic_ex4_rnd_ni_b ,--o--fpic + f_pic_ex4_rnd_nr_b => f_pic_ex4_rnd_nr_b ,--o--fpic + f_pic_ex4_sel_fpscr_b => f_pic_ex4_sel_fpscr_b ,--o--fpic + f_pic_ex4_sp_b => f_pic_ex4_sp_b ,--o--fpic + f_pic_ex4_spec_inf_b => f_pic_ex4_spec_inf_b ,--o--fpic + f_pic_ex4_spec_sel_k_e => f_pic_ex4_spec_sel_k_e ,--o--fpic + f_pic_ex4_spec_sel_k_f => f_pic_ex4_spec_sel_k_f ,--o--fpic + f_dcd_ex2_uc_inc_lsb => f_dcd_ex2_uc_inc_lsb ,--i--fpic + f_dcd_ex2_uc_guard => f_dcd_ex2_uc_gs(0) ,--i--fpic + f_dcd_ex2_uc_sticky => f_dcd_ex2_uc_gs(1) ,--i--fpic + f_dcd_ex2_uc_gs_v => f_dcd_ex2_uc_gs_v ,--i--fpic + f_pic_ex5_uc_inc_lsb => f_pic_ex5_uc_inc_lsb ,--o--fpic + f_pic_ex5_uc_guard => f_pic_ex5_uc_guard ,--o--fpic + f_pic_ex5_uc_sticky => f_pic_ex5_uc_sticky ,--o--fpic + f_pic_ex5_uc_g_v => f_pic_ex5_uc_g_v ,--o--fpic + f_pic_ex5_uc_s_v => f_pic_ex5_uc_s_v ,--o--fpic + f_pic_ex4_to_int_ov_all => f_pic_ex4_to_int_ov_all ,--o--fpic + f_pic_ex4_to_integer_b => f_pic_ex4_to_integer_b ,--o--fpic + f_pic_ex4_word_b => f_pic_ex4_word_b ,--o--fpic + f_pic_ex4_uns_b => f_pic_ex4_uns_b ,--o--fpic + f_pic_ex4_ue => f_pic_ex4_ue ,--o--fpic + f_pic_ex4_uf_en => f_pic_ex4_uf_en ,--o--fpic + f_pic_ex4_unf_en_ue0_b => f_pic_ex4_unf_en_ue0_b ,--o--fpic + f_pic_ex4_unf_en_ue1_b => f_pic_ex4_unf_en_ue1_b ,--o--fpic + f_pic_ex5_en_exact_zero => f_pic_ex5_en_exact_zero ,--o--fpic + f_pic_ex5_compare_b => f_pic_ex5_compare_b ,--o--fpic + f_pic_ex5_frsp => f_pic_ex5_frsp ,--o--fpic + f_pic_ex5_fi_pipe_v_b => f_pic_ex5_fi_pipe_v_b ,--o--fpic + f_pic_ex5_fi_spec_b => f_pic_ex5_fi_spec_b ,--o--fpic + f_pic_ex5_flag_vxcvi_b => f_pic_ex5_flag_vxcvi_b ,--o--fpic + f_pic_ex5_flag_vxidi_b => f_pic_ex5_flag_vxidi_b ,--o--fpic + f_pic_ex5_flag_vximz_b => f_pic_ex5_flag_vximz_b ,--o--fpic + f_pic_ex5_flag_vxisi_b => f_pic_ex5_flag_vxisi_b ,--o--fpic + f_pic_ex5_flag_vxsnan_b => f_pic_ex5_flag_vxsnan_b ,--o--fpic + f_pic_ex5_flag_vxsqrt_b => f_pic_ex5_flag_vxsqrt_b ,--o--fpic + f_pic_ex5_flag_vxvc_b => f_pic_ex5_flag_vxvc_b ,--o--fpic + f_pic_ex5_flag_vxzdz_b => f_pic_ex5_flag_vxzdz_b ,--o--fpic + f_pic_ex5_flag_zx_b => f_pic_ex5_flag_zx_b ,--o--fpic + f_pic_ex5_fprf_hold_b => f_pic_ex5_fprf_hold_b ,--o--fpic + f_pic_ex5_fprf_pipe_v_b => f_pic_ex5_fprf_pipe_v_b ,--o--fpic + f_pic_ex5_fprf_spec_b(0 to 4) => f_pic_ex5_fprf_spec_b(0 to 4) ,--o--fpic + f_pic_ex5_fr_pipe_v_b => f_pic_ex5_fr_pipe_v_b ,--o--fpic + f_pic_ex5_fr_spec_b => f_pic_ex5_fr_spec_b ,--o--fpic + f_pic_ex5_invert_sign => f_pic_ex5_invert_sign ,--o--fpic + f_pic_ex5_k_nan => f_pic_ex5_k_nan ,--o--fpic + f_pic_ex5_k_inf => f_pic_ex5_k_inf ,--o--fpic + f_pic_ex5_k_max => f_pic_ex5_k_max ,--o--fpic + f_pic_ex5_k_zer => f_pic_ex5_k_zer ,--o--fpic + f_pic_ex5_k_one => f_pic_ex5_k_one ,--o--fpic + f_pic_ex5_k_int_maxpos => f_pic_ex5_k_int_maxpos ,--o--fpic + f_pic_ex5_k_int_maxneg => f_pic_ex5_k_int_maxneg ,--o--fpic + f_pic_ex5_k_int_zer => f_pic_ex5_k_int_zer ,--o--fpic + f_pic_ex5_ox_pipe_v_b => f_pic_ex5_ox_pipe_v_b ,--o--fpic + f_pic_ex5_round_sign => f_pic_ex5_round_sign ,--o--fpic + f_pic_ex5_scr_upd_move_b => f_pic_ex5_scr_upd_move_b ,--o--fpic + f_pic_ex5_scr_upd_pipe_b => f_pic_ex5_scr_upd_pipe_b ,--o--fpic + f_pic_ex1_nj_deni => f_pic_ex1_nj_deni ,--o--fpic + f_dcd_rf1_nj_deni => f_dcd_rf1_nj_deni ,--i--fpic + f_pic_ex5_ux_pipe_v_b => f_pic_ex5_ux_pipe_v_b );--o--fpic +------------------------------------------------------------- fuq_pic.vhdl + +fcr2 : entity WORK.fuq_cr2(fuq_cr2) generic map( expand_type => expand_type) port map( -- fuq_cr2.vhdl +------------------------------------------------------------- fuq_cr2.vhdl + vdd => vdd ,--i-- + gnd => gnd ,--i-- + nclk => nclk ,--i-- + clkoff_b => clkoff_b ,--i-- + act_dis => act_dis ,--i-- + flush => flush ,--i-- + --d_mode => d_mode ,--i-- + delay_lclkr => delay_lclkr(1 to 7) ,--i-- + mpw1_b => mpw1_b(1 to 7) ,--i-- + mpw2_b => mpw2_b(0 to 1) ,--i-- + thold_1 => perv_cr2_thold_1 ,--i-- + sg_1 => perv_cr2_sg_1 ,--i-- + fpu_enable => perv_cr2_fpu_enable ,--i-- + + + f_cr2_si => scan_in(14) ,--i--fcr2 + f_cr2_so => scan_out(14) ,--o--fcr2 + rf1_act => f_dcd_rf1_act ,--i--fcr2 + ex1_act => f_pic_cr2_ex1_act ,--i--fcr2 + rf1_thread_b(0 to 3) => rf1_thread_b(0 to 3) ,--i--fcr2 + f_dcd_ex6_cancel => f_dcd_ex6_cancel ,--i--fcr2 + f_fmt_ex1_bop_byt(45 to 52) => f_fmt_ex1_bop_byt(45 to 52) ,--i--fcr2 for mtfsf to shadow reg + f_dcd_rf1_fpscr_bit_data_b(0 to 3) => f_dcd_rf1_fpscr_bit_data_b(0 to 3) ,--i--fcr2 data to write to nibble (other than mtfsf) + f_dcd_rf1_fpscr_bit_mask_b(0 to 3) => f_dcd_rf1_fpscr_bit_mask_b(0 to 3) ,--i--fcr2 enable update of bit within the nibble + f_dcd_rf1_fpscr_nib_mask_b(0 to 8) => f_dcd_rf1_fpscr_nib_mask_b(0 to 8) ,--i--fcr2 enable update of this nibble + f_dcd_rf1_mtfsbx_b => f_dcd_rf1_mtfsbx_b ,--i--fcr2 fpscr set bit, reset bit + f_dcd_rf1_mcrfs_b => f_dcd_rf1_mcrfs_b ,--i--fcr2 move fpscr field to cr and reset exceptions + f_dcd_rf1_mtfsf_b => f_dcd_rf1_mtfsf_b ,--i--fcr2 move fpr data to fpscr + f_dcd_rf1_mtfsfi_b => f_dcd_rf1_mtfsfi_b ,--i--fcr2 move immediate data to fpscr + f_cr2_ex3_thread_b(0 to 3) => f_cr2_ex3_thread_b(0 to 3) ,--o--fcr2 + f_cr2_ex3_fpscr_bit_data_b(0 to 3) => f_cr2_ex3_fpscr_bit_data_b(0 to 3) ,--o--fcr2 data to write to nibble (other than mtfsf) + f_cr2_ex3_fpscr_bit_mask_b(0 to 3) => f_cr2_ex3_fpscr_bit_mask_b(0 to 3) ,--o--fcr2 enable update of bit within the nibble + f_cr2_ex3_fpscr_nib_mask_b(0 to 8) => f_cr2_ex3_fpscr_nib_mask_b(0 to 8) ,--o--fcr2 enable update of this nibble + f_cr2_ex3_mtfsbx_b => f_cr2_ex3_mtfsbx_b ,--o--fcr2 fpscr set bit, reset bit + f_cr2_ex3_mcrfs_b => f_cr2_ex3_mcrfs_b ,--o--fcr2 move fpscr field to cr and reset exceptions + f_cr2_ex3_mtfsf_b => f_cr2_ex3_mtfsf_b ,--o--fcr2 move fpr data to fpscr + f_cr2_ex3_mtfsfi_b => f_cr2_ex3_mtfsfi_b ,--o--fcr2 move immediate data to fpscr + f_cr2_ex5_fpscr_rd_dat(24 to 31) => f_cr2_ex5_fpscr_rd_dat(24 to 31) ,--o--fcr2 + f_cr2_ex6_fpscr_rd_dat(24 to 31) => f_cr2_ex6_fpscr_rd_dat(24 to 31) ,--o--fcr2 + f_cr2_ex1_fpscr_shadow(0 to 7) => f_cr2_ex1_fpscr_shadow(0 to 7) );--o--fcr2 +------------------------------------------------------------- fuq_cr2.vhdl + + + +fscr : entity WORK.fuq_scr(fuq_scr) generic map( expand_type => expand_type) port map( +------------------------------------------------------------- fuq_scr.vhdl + vdd => vdd ,--i-- + gnd => gnd ,--i-- + nclk => nclk ,--i-- + clkoff_b => clkoff_b ,--i-- + act_dis => act_dis ,--i-- + flush => flush ,--i-- + --d_mode => d_mode ,--i-- + delay_lclkr => delay_lclkr(4 to 7) ,--i-- + mpw1_b => mpw1_b(4 to 7) ,--i-- + mpw2_b => mpw2_b(0 to 1) ,--i-- + thold_1 => perv_scr_thold_1 ,--i-- + sg_1 => perv_scr_sg_1 ,--i-- + fpu_enable => perv_scr_fpu_enable ,--i-- + + f_scr_si => scan_in(15) ,--i--fscr + f_scr_so => scan_out(15) ,--o--fscr + ex2_act_b => f_pic_scr_ex2_act_b ,--i--fscr + f_cr2_ex3_thread_b(0 to 3) => f_cr2_ex3_thread_b(0 to 3) ,--i--fscr + + f_dcd_ex6_cancel => f_dcd_ex6_cancel ,--i--fcr2 + + f_pic_ex5_scr_upd_move_b => f_pic_ex5_scr_upd_move_b ,--i--fscr + f_pic_ex5_scr_upd_pipe_b => f_pic_ex5_scr_upd_pipe_b ,--i--fscr + f_pic_ex5_fprf_spec_b(0 to 4) => f_pic_ex5_fprf_spec_b(0 to 4) ,--i--fscr + f_pic_ex5_compare_b => f_pic_ex5_compare_b ,--i--fscr + f_pic_ex5_fprf_pipe_v_b => f_pic_ex5_fprf_pipe_v_b ,--i--fscr + f_pic_ex5_fprf_hold_b => f_pic_ex5_fprf_hold_b ,--i--fscr + f_pic_ex5_fi_spec_b => f_pic_ex5_fi_spec_b ,--i--fscr + f_pic_ex5_fi_pipe_v_b => f_pic_ex5_fi_pipe_v_b ,--i--fscr + f_pic_ex5_fr_spec_b => f_pic_ex5_fr_spec_b ,--i--fscr + f_pic_ex5_fr_pipe_v_b => f_pic_ex5_fr_pipe_v_b ,--i--fscr + f_pic_ex5_ox_spec_b => tiup ,--i--fscr + f_pic_ex5_ox_pipe_v_b => f_pic_ex5_ox_pipe_v_b ,--i--fscr + f_pic_ex5_ux_spec_b => tiup ,--i--fscr + f_pic_ex5_ux_pipe_v_b => f_pic_ex5_ux_pipe_v_b ,--i--fscr + f_pic_ex5_flag_vxsnan_b => f_pic_ex5_flag_vxsnan_b ,--i--fscr + f_pic_ex5_flag_vxisi_b => f_pic_ex5_flag_vxisi_b ,--i--fscr + f_pic_ex5_flag_vxidi_b => f_pic_ex5_flag_vxidi_b ,--i--fscr + f_pic_ex5_flag_vxzdz_b => f_pic_ex5_flag_vxzdz_b ,--i--fscr + f_pic_ex5_flag_vximz_b => f_pic_ex5_flag_vximz_b ,--i--fscr + f_pic_ex5_flag_vxvc_b => f_pic_ex5_flag_vxvc_b ,--i--fscr + f_pic_ex5_flag_vxsqrt_b => f_pic_ex5_flag_vxsqrt_b ,--i--fscr + f_pic_ex5_flag_vxcvi_b => f_pic_ex5_flag_vxcvi_b ,--i--fscr + f_pic_ex5_flag_zx_b => f_pic_ex5_flag_zx_b ,--i--fscr + f_nrm_ex5_fpscr_wr_dat_dfp(0 to 3) => f_nrm_ex5_fpscr_wr_dat_dfp(0 to 3) ,--i--fscr + f_nrm_ex5_fpscr_wr_dat(0 to 31) => f_nrm_ex5_fpscr_wr_dat(0 to 31) ,--i--fscr + f_cr2_ex3_fpscr_bit_data_b(0 to 3) => f_cr2_ex3_fpscr_bit_data_b(0 to 3) ,--o--fscr data to write to nibble (other than mtfsf) + f_cr2_ex3_fpscr_bit_mask_b(0 to 3) => f_cr2_ex3_fpscr_bit_mask_b(0 to 3) ,--o--fscr enable update of bit within the nibble + f_cr2_ex3_fpscr_nib_mask_b(0 to 8) => f_cr2_ex3_fpscr_nib_mask_b(0 to 8) ,--o--fscr enable update of this nibble + f_cr2_ex3_mtfsbx_b => f_cr2_ex3_mtfsbx_b ,--o--fscr fpscr set bit, reset bit + f_cr2_ex3_mcrfs_b => f_cr2_ex3_mcrfs_b ,--o--fscr move fpscr field to cr and reset exceptions + f_cr2_ex3_mtfsf_b => f_cr2_ex3_mtfsf_b ,--o--fscr move fpr data to fpscr + f_cr2_ex3_mtfsfi_b => f_cr2_ex3_mtfsfi_b ,--o--fscr move immediate data to fpscr + f_rnd_ex6_flag_up => f_rnd_ex6_flag_up ,--i--fscr + f_rnd_ex6_flag_fi => f_rnd_ex6_flag_fi ,--i--fscr + f_rnd_ex6_flag_ox => f_rnd_ex6_flag_ox ,--i--fscr + f_rnd_ex6_flag_den => f_rnd_ex6_flag_den ,--i--fscr + f_rnd_ex6_flag_sgn => f_rnd_ex6_flag_sgn ,--i--fscr + f_rnd_ex6_flag_inf => f_rnd_ex6_flag_inf ,--i--fscr + f_rnd_ex6_flag_zer => f_rnd_ex6_flag_zer ,--i--fscr + f_rnd_ex6_flag_ux => f_rnd_ex6_flag_ux ,--i--fscr + f_cr2_ex6_fpscr_rd_dat(24 to 31) => f_cr2_ex6_fpscr_rd_dat(24 to 31) ,--i--fscr + f_cr2_ex5_fpscr_rd_dat(24 to 31) => f_cr2_ex5_fpscr_rd_dat(24 to 31) ,--i--fscr + f_scr_ex5_fpscr_rd_dat(0 to 31) => f_scr_ex5_fpscr_rd_dat(0 to 31) ,--o--fscr + f_scr_ex5_fpscr_rd_dat_dfp(0 to 3) => f_scr_ex5_fpscr_rd_dat_dfp(0 to 3) ,--o--fscr + f_scr_ex7_cr_fld(0 to 3) => f_scr_ex7_cr_fld(0 to 3) ,--o--fscr + f_scr_ex7_fx_thread0(0 to 3) => f_scr_ex7_fx_thread0(0 to 3) ,--o--fscr --UNUSED ?? + f_scr_ex7_fx_thread1(0 to 3) => f_scr_ex7_fx_thread1(0 to 3) ,--o--fscr --UNUSED ?? + f_scr_ex7_fx_thread2(0 to 3) => f_scr_ex7_fx_thread2(0 to 3) ,--o--fscr --UNUSED ?? + f_scr_ex7_fx_thread3(0 to 3) => f_scr_ex7_fx_thread3(0 to 3) );--o--fscr --UNUSED ?? +------------------------------------------------------------- fuq_scr.vhdl + + +ftbe : entity WORK.fuq_tblexp(fuq_tblexp) generic map( expand_type => expand_type) port map( -- exponent for table lookups +------------------------------------------------------------- fuq_tblexp.vhdl + vdd => vdd ,--i-- + gnd => gnd ,--i-- + nclk => nclk ,--i-- + clkoff_b => clkoff_b ,--i-- + act_dis => act_dis ,--i-- + flush => flush ,--i-- + --d_mode => d_mode ,--i-- + delay_lclkr => delay_lclkr(2 to 3) ,--i-- + mpw1_b => mpw1_b(2 to 3) ,--i-- + mpw2_b => mpw2_b(0 to 0) ,--i-- + thold_1 => perv_tbe_thold_1 ,--i-- + sg_1 => perv_tbe_sg_1 ,--i-- + fpu_enable => perv_tbe_fpu_enable ,--i-- + + si => scan_in(16) ,--i--ftbe + so => scan_out(16) ,--o--ftbe + ex1_act_b => f_pic_lza_ex1_act_b ,--i--ftbe + f_pic_ex2_ue1 => f_pic_ex2_ue1 ,--i--ftbe + f_pic_ex2_sp_b => f_pic_ex2_sp_b ,--i--ftbe + f_pic_ex2_est_recip => f_pic_ex2_est_recip ,--i--ftbe + f_pic_ex2_est_rsqrt => f_pic_ex2_est_rsqrt ,--i--ftbe + f_eie_ex2_tbl_expo(1 to 13) => f_eie_ex2_tbl_expo(1 to 13) ,--i--ftbe + f_fmt_ex2_lu_den_recip => f_fmt_ex2_lu_den_recip ,--i--ftbe + f_fmt_ex2_lu_den_rsqrto => f_fmt_ex2_lu_den_rsqrto ,--i--ftbe + f_tbe_ex3_match_en_sp => f_tbe_ex3_match_en_sp ,--o--ftbe + f_tbe_ex3_match_en_dp => f_tbe_ex3_match_en_dp ,--o--ftbe + f_tbe_ex3_recip_2046 => f_tbe_ex3_recip_2046 ,--o--ftbe + f_tbe_ex3_recip_2045 => f_tbe_ex3_recip_2045 ,--o--ftbe + f_tbe_ex3_recip_2044 => f_tbe_ex3_recip_2044 ,--o--ftbe + f_tbe_ex3_lu_sh => f_tbe_ex3_lu_sh ,--o--ftbe + f_tbe_ex3_recip_ue1 => f_tbe_ex3_recip_ue1 ,--o--ftbe + f_tbe_ex3_may_ov => f_tbe_ex3_may_ov ,--o--ftbe + f_tbe_ex3_res_expo(1 to 13) => f_tbe_ex3_res_expo(1 to 13) );--o--ftbe + +ftbl : entity WORK.fuq_tbllut(fuq_tbllut) generic map( expand_type => expand_type) port map( +------------------------------------------------------------- fuq_tbllut.vhdl + vdd => vdd ,--i-- + gnd => gnd ,--i-- + nclk => nclk ,--i-- + clkoff_b => clkoff_b ,--i-- + act_dis => act_dis ,--i-- + flush => flush ,--i-- + --d_mode => d_mode ,--i-- + delay_lclkr => delay_lclkr(2 to 5) ,--i-- + mpw1_b => mpw1_b(2 to 5) ,--i-- + mpw2_b => mpw2_b(0 to 1) ,--i-- + thold_1 => perv_tbl_thold_1 ,--i-- + sg_1 => perv_tbl_sg_1 ,--i-- + fpu_enable => perv_tbl_fpu_enable ,--i-- + + si => scan_in(17) ,--i--ftbl + so => scan_out(17) ,--o--ftbl + ex1_act => f_pic_tbl_ex1_act ,--i--ftbl + f_fmt_ex1_b_frac(1 to 6) => f_fmt_ex1_b_frac(1 to 6) ,--i--ftbl + f_fmt_ex2_b_frac(7 to 22) => f_fmt_ex2_pass_frac(7 to 22) ,--i--ftbl + f_tbe_ex2_expo_lsb => f_eie_ex2_tbl_expo(13) ,--i--ftbl + f_tbe_ex2_est_recip => f_pic_ex2_est_recip ,--i--ftbl + f_tbe_ex2_est_rsqrt => f_pic_ex2_est_rsqrt ,--i--ftbl + f_tbe_ex3_recip_ue1 => f_tbe_ex3_recip_ue1 ,--i--ftbl + f_tbe_ex3_lu_sh => f_tbe_ex3_lu_sh ,--i--ftbl + f_tbe_ex3_match_en_sp => f_tbe_ex3_match_en_sp ,--i--ftbl + f_tbe_ex3_match_en_dp => f_tbe_ex3_match_en_dp ,--i--ftbl + f_tbe_ex3_recip_2046 => f_tbe_ex3_recip_2046 ,--i--ftbl + f_tbe_ex3_recip_2045 => f_tbe_ex3_recip_2045 ,--i--ftbl + f_tbe_ex3_recip_2044 => f_tbe_ex3_recip_2044 ,--i--ftbl + f_tbl_ex5_est_frac(0 to 26) => f_tbl_ex5_est_frac(0 to 26) ,--o--ftbl + f_tbl_ex4_unf_expo => f_tbl_ex4_unf_expo ,--o--ftbl + f_tbl_ex5_recip_den => f_tbl_ex5_recip_den );--o--ftbl +------------------------------------------------------------- fuq_tbllut.vhdl + + + + --------------------------------------------- + -- pervasive + --------------------------------------------- + + perv_tbl_sg_1 <= sg_1 ; + perv_tbe_sg_1 <= sg_1 ; + perv_eie_sg_1 <= sg_1 ; + perv_eov_sg_1 <= sg_1 ; + perv_fmt_sg_1 <= sg_1 ; + perv_mul_sg_1 <= sg_1 ; + perv_alg_sg_1 <= sg_1 ; + perv_sa3_sg_1 <= sg_1 ; + perv_add_sg_1 <= sg_1 ; + perv_lza_sg_1 <= sg_1 ; + perv_nrm_sg_1 <= sg_1 ; + perv_rnd_sg_1 <= sg_1 ; + perv_scr_sg_1 <= sg_1 ; + perv_pic_sg_1 <= sg_1 ; + perv_cr2_sg_1 <= sg_1 ; + + perv_tbl_thold_1 <= thold_1 ; + perv_tbe_thold_1 <= thold_1 ; + perv_eie_thold_1 <= thold_1 ; + perv_eov_thold_1 <= thold_1 ; + perv_fmt_thold_1 <= thold_1 ; + perv_mul_thold_1 <= thold_1 ; + perv_alg_thold_1 <= thold_1 ; + perv_sa3_thold_1 <= thold_1 ; + perv_add_thold_1 <= thold_1 ; + perv_lza_thold_1 <= thold_1 ; + perv_nrm_thold_1 <= thold_1 ; + perv_rnd_thold_1 <= thold_1 ; + perv_scr_thold_1 <= thold_1 ; + perv_pic_thold_1 <= thold_1 ; + perv_cr2_thold_1 <= thold_1 ; + + perv_tbl_fpu_enable <= fpu_enable ; + perv_tbe_fpu_enable <= fpu_enable ; + perv_eie_fpu_enable <= fpu_enable ; + perv_eov_fpu_enable <= fpu_enable ; + perv_fmt_fpu_enable <= fpu_enable ; + perv_mul_fpu_enable <= fpu_enable ; + perv_alg_fpu_enable <= fpu_enable ; + perv_sa3_fpu_enable <= fpu_enable ; + perv_add_fpu_enable <= fpu_enable ; + perv_lza_fpu_enable <= fpu_enable ; + perv_nrm_fpu_enable <= fpu_enable ; + perv_rnd_fpu_enable <= fpu_enable ; + perv_scr_fpu_enable <= fpu_enable ; + perv_pic_fpu_enable <= fpu_enable ; + perv_cr2_fpu_enable <= fpu_enable ; + + + + + +end fuq_mad; diff --git a/rel/src/vhdl/work/fuq_mul.vhdl b/rel/src/vhdl/work/fuq_mul.vhdl new file mode 100644 index 0000000..7881678 --- /dev/null +++ b/rel/src/vhdl/work/fuq_mul.vhdl @@ -0,0 +1,318 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; +library clib ; + + + +entity fuq_mul is +generic( expand_type : integer := 2 ); +port( + + vdd :inout power_logic; + gnd :inout power_logic; + clkoff_b :in std_ulogic; -- tiup + act_dis :in std_ulogic; -- ??tidn?? + flush :in std_ulogic; -- ??tidn?? + delay_lclkr :in std_ulogic; -- tidn, + mpw1_b :in std_ulogic; -- tidn, + mpw2_b :in std_ulogic; -- tidn, + sg_1 :in std_ulogic; + thold_1 :in std_ulogic; + fpu_enable :in std_ulogic; --dc_act + nclk :in clk_logic; + + f_mul_si :in std_ulogic; --perv + f_mul_so :out std_ulogic; --perv + ex1_act :in std_ulogic; --act + + f_fmt_ex1_a_frac :in std_ulogic_vector(0 to 52) ;-- implicit bit already generated + f_fmt_ex1_a_frac_17 :in std_ulogic;-- new port for replicated bit + f_fmt_ex1_a_frac_35 :in std_ulogic;-- new port for replicated bit + f_fmt_ex1_c_frac :in std_ulogic_vector(0 to 53) ;-- implicit bit already generated + + f_mul_ex2_sum :out std_ulogic_vector(1 to 108); + f_mul_ex2_car :out std_ulogic_vector(1 to 108) +); + + +end fuq_mul; -- ENTITY + +architecture fuq_mul of fuq_mul is + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal thold_0_b, thold_0, forcee :std_ulogic; + signal sg_0 :std_ulogic; + signal spare_unused :std_ulogic_vector(0 to 3); + ---------------------------------------- + signal act_so , act_si :std_ulogic_vector(0 to 3);--SCAN + signal m92_0_so, m92_1_so, m92_2_so :std_ulogic; + ---------------------------------------- + signal pp3_05 :std_ulogic_vector(36 to 108) ; + signal pp3_04 :std_ulogic_vector(35 to 108) ; + signal pp3_03 :std_ulogic_vector(18 to 90) ; + signal pp3_02 :std_ulogic_vector(17 to 90) ; + signal pp3_01 :std_ulogic_vector(0 to 72) ; + signal pp3_00 :std_ulogic_vector(0 to 72) ; + + + signal hot_one_msb_unused :std_ulogic; + signal hot_one_74 :std_ulogic; + signal hot_one_92 :std_ulogic; + signal xtd_unused :std_ulogic; + + + signal pp5_00 :std_ulogic_vector(1 to 108); + signal pp5_01 :std_ulogic_vector(1 to 108); + + +begin + +--//################################################################ +--//# pervasive +--//################################################################ + + thold_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => thold_1, + q(0) => thold_0 ); + + sg_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => sg_1 , + q(0) => sg_0 ); + + + lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map ( + clkoff_b => clkoff_b, + thold => thold_0, + sg => sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => thold_0_b ); + + +--//################################################################ +--//# act +--//################################################################ + + + act_lat: tri_rlmreg_p generic map (width=> 4, expand_type => expand_type, needs_sreset => 0) port map ( + forcee => forcee,--i-- tidn, + delay_lclkr => delay_lclkr ,--i-- tidn, + mpw1_b => mpw1_b ,--i-- tidn, + mpw2_b => mpw2_b ,--i-- tidn, + vd => vdd, + gd => gnd, + nclk => nclk, + act => fpu_enable, + thold_b => thold_0_b, + sg => sg_0, + scout => act_so, + scin => act_si, + ------------------- + din(0) => spare_unused(0), + din(1) => spare_unused(1), + din(2) => spare_unused(2), + din(3) => spare_unused(3), + ------------------- + dout(0) => spare_unused(0), + dout(1) => spare_unused(1), + dout(2) => spare_unused(2) , + dout(3) => spare_unused(3) ); + +act_si(0 to 3) <= act_so(1 to 3) & m92_2_so; + +f_mul_so <= act_so(0) ; + + + + + +--//################################################################ +--//# ex1 logic +--//################################################################ + +--//# NUMBERING SYSTEM RELATIVE TO COMPRESSOR TREE +--//# +--//# 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111111111 +--//# 0000000000111111111122222222223333333333444444444455555555556666666666777777777788888888889999999999000000000 +--//# 0123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678 +--//# 0 ..DdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s.................................................. +--//# 1 ..1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s................................................ +--//# 2 ....1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s.............................................. +--//# 3 ......1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s............................................ +--//# 4 ........1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s.......................................... +--//# 5 ..........1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s........................................ +--//# 6 ............1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s...................................... +--//# 7 ..............1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s.................................... +--//# 8 ................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s.................................. + +--//# 9 ..................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s................................ +--//# 10 ....................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s.............................. +--//# 11 ......................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s............................ +--//# 12 ........................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s.......................... +--//# 13 ..........................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s........................ +--//# 14 ............................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s...................... +--//# 15 ..............................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s.................... +--//# 16 ................................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s.................. +--//# 17 ..................................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s................ + +--//# 18 ....................................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s.............. +--//# 19 ......................................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s............ +--//# 20 ........................................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s.......... +--//# 21 ..........................................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s........ +--//# 22 ............................................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s...... +--//# 23 ..............................................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s.... +--//# 24 ................................................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s.. +--//# 25 ..................................................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s +--//# 26 ...................................................assDdddddddddddddddddddddddddddddddddddddddddddddddddddddD + + + +m92_2: entity work.fuq_mul_92(fuq_mul_92) generic map(inst=> 2, expand_type => expand_type) port map( + vdd => vdd ,--i-- + gnd => gnd ,--i-- + nclk => nclk ,--i-- + forcee => forcee,--i-- + lcb_delay_lclkr => delay_lclkr ,--i-- tidn + lcb_mpw1_b => mpw1_b ,--i-- mpw1_b others=0 + lcb_mpw2_b => mpw2_b ,--i-- mpw2_b others=0 + thold_b => thold_0_b ,--i-- + lcb_sg => sg_0 ,--i-- + si => f_mul_si ,--i-- + so => m92_0_so ,--o-- + ex1_act => ex1_act ,--i-- + ---------------------- + c_frac(0 to 53) => f_fmt_ex1_c_frac(0 to 53) ,--i-- Multiplicand (shift me) + a_frac(17 to 34) => f_fmt_ex1_a_frac(35 to 52) ,--i-- Multiplier (recode me) + a_frac(35) => tidn ,--i-- Multiplier (recode me) + hot_one_out => hot_one_92 ,--o-- + sum92(2 to 74) => pp3_05(36 to 108) ,--o-- + car92(1 to 74) => pp3_04(35 to 108) );--o-- + +m92_1: entity work.fuq_mul_92(fuq_mul_92) generic map(inst=> 1, expand_type => expand_type) port map( + vdd => vdd ,--i-- + gnd => gnd ,--i-- + nclk => nclk ,--i-- + forcee => forcee,--i-- + lcb_delay_lclkr => delay_lclkr ,--i-- tidn + lcb_mpw1_b => mpw1_b ,--i-- mpw1_b others=0 + lcb_mpw2_b => mpw2_b ,--i-- mpw2_b others=0 + thold_b => thold_0_b ,--i-- + lcb_sg => sg_0 ,--i-- + si => m92_0_so ,--i-- + so => m92_1_so ,--o-- v + ex1_act => ex1_act ,--i-- + --------------------- + c_frac(0 to 53) => f_fmt_ex1_c_frac(0 to 53) ,--i-- Multiplicand (shift me) + a_frac(17 to 34) => f_fmt_ex1_a_frac(17 to 34) ,--i-- Multiplier (recode me) + a_frac(35) => f_fmt_ex1_a_frac_35 ,--i-- Multiplier (recode me) + hot_one_out => hot_one_74 ,--o-- + sum92(2 to 74) => pp3_03(18 to 90) ,--o-- + car92(1 to 74) => pp3_02(17 to 90) );--o-- + +m92_0: entity work.fuq_mul_92(fuq_mul_92) generic map(inst=> 0, expand_type => expand_type) port map( + vdd => vdd ,--i-- + gnd => gnd ,--i-- + nclk => nclk ,--i-- + forcee => forcee,--i-- + lcb_delay_lclkr => delay_lclkr ,--i-- tidn + lcb_mpw1_b => mpw1_b ,--i-- mpw1_b others=0 + lcb_mpw2_b => mpw2_b ,--i-- mpw2_b others=0 + thold_b => thold_0_b ,--i-- + lcb_sg => sg_0 ,--i-- + si => m92_1_so ,--i-- + so => m92_2_so ,--o-- + ex1_act => ex1_act ,--i-- + --------------------- + c_frac(0 to 53) => f_fmt_ex1_c_frac(0 to 53) ,--i-- Multiplicand (shift me) + a_frac(17) => tidn ,--i-- Multiplier (recode me) + a_frac(18 to 34) => f_fmt_ex1_a_frac(0 to 16) ,--i-- Multiplier (recode me) + a_frac(35) => f_fmt_ex1_a_frac_17 ,--i-- Multiplier (recode me) + hot_one_out => hot_one_msb_unused ,--o-- + sum92(2 to 74) => pp3_01(0 to 72) ,--o-- + car92(1) => xtd_unused ,--o-- + car92(2 to 74) => pp3_00(0 to 72) );--o-- + + + + --//################################################## + --//# Compressor Level 4 , 5 + --//################################################## + + m62: entity work.fuq_mul_62(fuq_mul_62) port map( + vdd => vdd, + gnd => gnd, + hot_one_92 => hot_one_92 ,--i-- + hot_one_74 => hot_one_74 ,--i-- + pp3_05(36 to 108) => pp3_05(36 to 108) ,--i-- + pp3_04(35 to 108) => pp3_04(35 to 108) ,--i-- + pp3_03(18 to 90) => pp3_03(18 to 90) ,--i-- + pp3_02(17 to 90) => pp3_02(17 to 90) ,--i-- + pp3_01( 0 to 72) => pp3_01( 0 to 72) ,--i-- + pp3_00( 0 to 72) => pp3_00( 0 to 72) ,--i-- + + sum62(1 to 108) => pp5_01(1 to 108) ,--o-- + car62(1 to 108) => pp5_00(1 to 108) );--o-- + + +--//################################################################ +--//# ex2 logic +--//################################################################ + + f_mul_ex2_sum(1 to 108) <= pp5_01(1 to 108); --output + f_mul_ex2_car(1 to 108) <= pp5_00(1 to 108); --output + +--//################################################################ +--//# scan string +--//################################################################ + + +end; -- fuq_mul ARCHITECTURE diff --git a/rel/src/vhdl/work/fuq_mul_62.vhdl b/rel/src/vhdl/work/fuq_mul_62.vhdl new file mode 100644 index 0000000..252fe03 --- /dev/null +++ b/rel/src/vhdl/work/fuq_mul_62.vhdl @@ -0,0 +1,2057 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee,ibm,support,tri, work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; +library clib ; + +--//########################################## +--//## double precision 9:2 compressor +--//########################################## + +entity fuq_mul_62 is +port( + + vdd : inout power_logic; + gnd : inout power_logic; + hot_one_92 :in std_ulogic; + hot_one_74 :in std_ulogic; + pp3_05 :in std_ulogic_vector(36 to 108); + pp3_04 :in std_ulogic_vector(35 to 108); + pp3_03 :in std_ulogic_vector(18 to 90); + pp3_02 :in std_ulogic_vector(17 to 90); + pp3_01 :in std_ulogic_vector( 0 to 72); + pp3_00 :in std_ulogic_vector( 0 to 72); + + sum62 :out std_ulogic_vector(1 to 108); + car62 :out std_ulogic_vector(1 to 108) + +); + + + +end fuq_mul_62; -- ENTITY + +architecture fuq_mul_62 of fuq_mul_62 is + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + + signal pp4_03 :std_ulogic_vector( 18 to 108);-- sum + signal pp4_02 :std_ulogic_vector( 34 to 108);-- car + signal pp4_01 :std_ulogic_vector( 1 to 90);-- sum + signal pp4_00 :std_ulogic_vector( 0 to 74);-- car + signal pp5_00 :std_ulogic_vector( 0 to 108);-- sum + signal pp5_01 :std_ulogic_vector( 1 to 108);-- car + signal pp5_00_ko :std_ulogic_vector( 17 to 73);-- ko + + signal pp3_05_inv, pp3_05_buf :std_ulogic_vector(36 to 108); + signal pp3_04_inv, pp3_04_buf :std_ulogic_vector(35 to 108); + signal pp3_03_inv, pp3_03_buf :std_ulogic_vector(18 to 90); + signal pp3_02_inv, pp3_02_buf :std_ulogic_vector(17 to 90); + signal pp3_01_inv :std_ulogic_vector( 1 to 72); + signal pp3_01_buf :std_ulogic_vector( 1 to 72); + signal pp3_00_inv :std_ulogic_vector( 1 to 72); + signal pp3_00_buf :std_ulogic_vector( 1 to 72); + signal hot_one_92_inv, hot_one_92_buf :std_ulogic; + signal hot_one_74_inv, hot_one_74_buf :std_ulogic; + signal unused :std_ulogic; + + + + + + + + + + + + + + + + + + +begin + +unused <= pp4_02(92) or pp4_00(72) or pp4_00(73) or pp4_00(0) or pp5_00(0) or + pp3_00(0) or pp3_01(0) ;-- 2 primary inputs + + +--//########################################################### +--//# LEON CHART +--//########################################################### +-- o : no logic done on the signal +-- c : carry +-- u : sum +-- h : hot1 +-- H : hot 1 latched +-- s : sign +-- a : ! sign +-- d : data from the booth muxes +-- wWW : 01a / ass +-- Kz : 1a / 00 + + + --//################################################## + --//# Compressor Level 4 + --//################################################## + + +--//# 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111111111 +--//# 0000000000111111111122222222223333333333444444444455555555556666666666777777777788888888889999999999000000000 +--//# 0123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678 +--//# ....................................ddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddd pp3_05 +--//# ...................................dddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddd pp3_04 +--//# ..................ddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddd_d................ pp3_03 +--//# ------------------------------------------------------------------------------------------------------------- +--//# ..................ooooooooooooooooouuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuoooooooooooooooo pp4_03 +--//# ..................................cccccccccccccccccccccccccccccccccccccccccccccccccccccccccc_oooooooooooooooo pp4_02 + + + inv_p3_05: pp3_05_inv(36 to 108) <= not pp3_05(36 to 108); + inv_p3_04: pp3_04_inv(35 to 108) <= not pp3_04(35 to 108); + inv_p3_03: pp3_03_inv(18 to 90) <= not pp3_03(18 to 90); + inv_p3_02: pp3_02_inv(17 to 90) <= not pp3_02(17 to 90); + inv_p3_01: pp3_01_inv( 1 to 72) <= not pp3_01( 1 to 72); + inv_p3_00: pp3_00_inv( 1 to 72) <= not pp3_00( 1 to 72); + inv_hot_one_92: hot_one_92_inv <= not hot_one_92 ; + inv_hot_one_74: hot_one_74_inv <= not hot_one_74 ; + + buf_pp3_05: pp3_05_buf(36 to 108) <= not pp3_05_inv(36 to 108); + buf_pp3_04: pp3_04_buf(35 to 108) <= not pp3_04_inv(35 to 108); + buf_pp3_03: pp3_03_buf(18 to 90) <= not pp3_03_inv(18 to 90); + buf_pp3_02: pp3_02_buf(17 to 90) <= not pp3_02_inv(17 to 90); + buf_pp3_01: pp3_01_buf( 1 to 72) <= not pp3_01_inv( 1 to 72); + buf_pp3_00: pp3_00_buf( 1 to 72) <= not pp3_00_inv( 1 to 72); + buf_hot_one_92: hot_one_92_buf <= not hot_one_92_inv ; + buf_hot_one_74: hot_one_74_buf <= not hot_one_74_inv ; + +------------------------------------ + + + pp4_03(93 to 108) <= pp3_05_buf(93 to 108) ; + pp4_02(93 to 108) <= pp3_04_buf(93 to 108) ; + pp4_02(92) <= tidn ; + +pp4_01_csa_92: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(92) ,--i-- + b => pp3_04_buf(92) ,--i-- + c => hot_one_92_buf ,--i-- + sum => pp4_03(92) ,--o-- + car => pp4_02(91) );--o-- +pp4_01_csa_91: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp3_05_buf(91) ,--i-- + b => pp3_04_buf(91) ,--i-- + sum => pp4_03(91) ,--o-- + car => pp4_02(90) );--o-- +pp4_01_csa_90: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(90) ,--i-- + b => pp3_04_buf(90) ,--i-- + c => pp3_03_buf(90) ,--i-- + sum => pp4_03(90) ,--o-- + car => pp4_02(89) );--o-- +pp4_01_csa_89: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(89) ,--i-- + b => pp3_04_buf(89) ,--i-- + c => pp3_03_buf(89) ,--i-- + sum => pp4_03(89) ,--o-- + car => pp4_02(88) );--o-- +pp4_01_csa_88: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(88) ,--i-- + b => pp3_04_buf(88) ,--i-- + c => pp3_03_buf(88) ,--i-- + sum => pp4_03(88) ,--o-- + car => pp4_02(87) );--o-- +pp4_01_csa_87: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(87) ,--i-- + b => pp3_04_buf(87) ,--i-- + c => pp3_03_buf(87) ,--i-- + sum => pp4_03(87) ,--o-- + car => pp4_02(86) );--o-- +pp4_01_csa_86: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(86) ,--i-- + b => pp3_04_buf(86) ,--i-- + c => pp3_03_buf(86) ,--i-- + sum => pp4_03(86) ,--o-- + car => pp4_02(85) );--o-- +pp4_01_csa_85: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(85) ,--i-- + b => pp3_04_buf(85) ,--i-- + c => pp3_03_buf(85) ,--i-- + sum => pp4_03(85) ,--o-- + car => pp4_02(84) );--o-- +pp4_01_csa_84: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(84) ,--i-- + b => pp3_04_buf(84) ,--i-- + c => pp3_03_buf(84) ,--i-- + sum => pp4_03(84) ,--o-- + car => pp4_02(83) );--o-- +pp4_01_csa_83: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(83) ,--i-- + b => pp3_04_buf(83) ,--i-- + c => pp3_03_buf(83) ,--i-- + sum => pp4_03(83) ,--o-- + car => pp4_02(82) );--o-- +pp4_01_csa_82: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(82) ,--i-- + b => pp3_04_buf(82) ,--i-- + c => pp3_03_buf(82) ,--i-- + sum => pp4_03(82) ,--o-- + car => pp4_02(81) );--o-- +pp4_01_csa_81: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(81) ,--i-- + b => pp3_04_buf(81) ,--i-- + c => pp3_03_buf(81) ,--i-- + sum => pp4_03(81) ,--o-- + car => pp4_02(80) );--o-- +pp4_01_csa_80: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(80) ,--i-- + b => pp3_04_buf(80) ,--i-- + c => pp3_03_buf(80) ,--i-- + sum => pp4_03(80) ,--o-- + car => pp4_02(79) );--o-- +pp4_01_csa_79: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(79) ,--i-- + b => pp3_04_buf(79) ,--i-- + c => pp3_03_buf(79) ,--i-- + sum => pp4_03(79) ,--o-- + car => pp4_02(78) );--o-- +pp4_01_csa_78: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(78) ,--i-- + b => pp3_04_buf(78) ,--i-- + c => pp3_03_buf(78) ,--i-- + sum => pp4_03(78) ,--o-- + car => pp4_02(77) );--o-- +pp4_01_csa_77: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(77) ,--i-- + b => pp3_04_buf(77) ,--i-- + c => pp3_03_buf(77) ,--i-- + sum => pp4_03(77) ,--o-- + car => pp4_02(76) );--o-- +pp4_01_csa_76: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(76) ,--i-- + b => pp3_04_buf(76) ,--i-- + c => pp3_03_buf(76) ,--i-- + sum => pp4_03(76) ,--o-- + car => pp4_02(75) );--o-- +pp4_01_csa_75: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(75) ,--i-- + b => pp3_04_buf(75) ,--i-- + c => pp3_03_buf(75) ,--i-- + sum => pp4_03(75) ,--o-- + car => pp4_02(74) );--o-- +pp4_01_csa_74: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(74) ,--i-- + b => pp3_04_buf(74) ,--i-- + c => pp3_03_buf(74) ,--i-- + sum => pp4_03(74) ,--o-- + car => pp4_02(73) );--o-- +pp4_01_csa_73: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(73) ,--i-- + b => pp3_04_buf(73) ,--i-- + c => pp3_03_buf(73) ,--i-- + sum => pp4_03(73) ,--o-- + car => pp4_02(72) );--o-- +pp4_01_csa_72: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(72) ,--i-- + b => pp3_04_buf(72) ,--i-- + c => pp3_03_buf(72) ,--i-- + sum => pp4_03(72) ,--o-- + car => pp4_02(71) );--o-- +pp4_01_csa_71: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(71) ,--i-- + b => pp3_04_buf(71) ,--i-- + c => pp3_03_buf(71) ,--i-- + sum => pp4_03(71) ,--o-- + car => pp4_02(70) );--o-- +pp4_01_csa_70: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(70) ,--i-- + b => pp3_04_buf(70) ,--i-- + c => pp3_03_buf(70) ,--i-- + sum => pp4_03(70) ,--o-- + car => pp4_02(69) );--o-- +pp4_01_csa_69: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(69) ,--i-- + b => pp3_04_buf(69) ,--i-- + c => pp3_03_buf(69) ,--i-- + sum => pp4_03(69) ,--o-- + car => pp4_02(68) );--o-- +pp4_01_csa_68: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(68) ,--i-- + b => pp3_04_buf(68) ,--i-- + c => pp3_03_buf(68) ,--i-- + sum => pp4_03(68) ,--o-- + car => pp4_02(67) );--o-- +pp4_01_csa_67: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(67) ,--i-- + b => pp3_04_buf(67) ,--i-- + c => pp3_03_buf(67) ,--i-- + sum => pp4_03(67) ,--o-- + car => pp4_02(66) );--o-- +pp4_01_csa_66: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(66) ,--i-- + b => pp3_04_buf(66) ,--i-- + c => pp3_03_buf(66) ,--i-- + sum => pp4_03(66) ,--o-- + car => pp4_02(65) );--o-- +pp4_01_csa_65: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(65) ,--i-- + b => pp3_04_buf(65) ,--i-- + c => pp3_03_buf(65) ,--i-- + sum => pp4_03(65) ,--o-- + car => pp4_02(64) );--o-- +pp4_01_csa_64: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(64) ,--i-- + b => pp3_04_buf(64) ,--i-- + c => pp3_03_buf(64) ,--i-- + sum => pp4_03(64) ,--o-- + car => pp4_02(63) );--o-- +pp4_01_csa_63: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(63) ,--i-- + b => pp3_04_buf(63) ,--i-- + c => pp3_03_buf(63) ,--i-- + sum => pp4_03(63) ,--o-- + car => pp4_02(62) );--o-- +pp4_01_csa_62: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(62) ,--i-- + b => pp3_04_buf(62) ,--i-- + c => pp3_03_buf(62) ,--i-- + sum => pp4_03(62) ,--o-- + car => pp4_02(61) );--o-- +pp4_01_csa_61: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(61) ,--i-- + b => pp3_04_buf(61) ,--i-- + c => pp3_03_buf(61) ,--i-- + sum => pp4_03(61) ,--o-- + car => pp4_02(60) );--o-- +pp4_01_csa_60: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(60) ,--i-- + b => pp3_04_buf(60) ,--i-- + c => pp3_03_buf(60) ,--i-- + sum => pp4_03(60) ,--o-- + car => pp4_02(59) );--o-- +pp4_01_csa_59: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(59) ,--i-- + b => pp3_04_buf(59) ,--i-- + c => pp3_03_buf(59) ,--i-- + sum => pp4_03(59) ,--o-- + car => pp4_02(58) );--o-- +pp4_01_csa_58: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(58) ,--i-- + b => pp3_04_buf(58) ,--i-- + c => pp3_03_buf(58) ,--i-- + sum => pp4_03(58) ,--o-- + car => pp4_02(57) );--o-- +pp4_01_csa_57: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(57) ,--i-- + b => pp3_04_buf(57) ,--i-- + c => pp3_03_buf(57) ,--i-- + sum => pp4_03(57) ,--o-- + car => pp4_02(56) );--o-- +pp4_01_csa_56: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(56) ,--i-- + b => pp3_04_buf(56) ,--i-- + c => pp3_03_buf(56) ,--i-- + sum => pp4_03(56) ,--o-- + car => pp4_02(55) );--o-- +pp4_01_csa_55: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(55) ,--i-- + b => pp3_04_buf(55) ,--i-- + c => pp3_03_buf(55) ,--i-- + sum => pp4_03(55) ,--o-- + car => pp4_02(54) );--o-- +pp4_01_csa_54: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(54) ,--i-- + b => pp3_04_buf(54) ,--i-- + c => pp3_03_buf(54) ,--i-- + sum => pp4_03(54) ,--o-- + car => pp4_02(53) );--o-- +pp4_01_csa_53: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(53) ,--i-- + b => pp3_04_buf(53) ,--i-- + c => pp3_03_buf(53) ,--i-- + sum => pp4_03(53) ,--o-- + car => pp4_02(52) );--o-- +pp4_01_csa_52: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(52) ,--i-- + b => pp3_04_buf(52) ,--i-- + c => pp3_03_buf(52) ,--i-- + sum => pp4_03(52) ,--o-- + car => pp4_02(51) );--o-- +pp4_01_csa_51: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(51) ,--i-- + b => pp3_04_buf(51) ,--i-- + c => pp3_03_buf(51) ,--i-- + sum => pp4_03(51) ,--o-- + car => pp4_02(50) );--o-- +pp4_01_csa_50: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(50) ,--i-- + b => pp3_04_buf(50) ,--i-- + c => pp3_03_buf(50) ,--i-- + sum => pp4_03(50) ,--o-- + car => pp4_02(49) );--o-- +pp4_01_csa_49: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(49) ,--i-- + b => pp3_04_buf(49) ,--i-- + c => pp3_03_buf(49) ,--i-- + sum => pp4_03(49) ,--o-- + car => pp4_02(48) );--o-- +pp4_01_csa_48: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(48) ,--i-- + b => pp3_04_buf(48) ,--i-- + c => pp3_03_buf(48) ,--i-- + sum => pp4_03(48) ,--o-- + car => pp4_02(47) );--o-- +pp4_01_csa_47: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(47) ,--i-- + b => pp3_04_buf(47) ,--i-- + c => pp3_03_buf(47) ,--i-- + sum => pp4_03(47) ,--o-- + car => pp4_02(46) );--o-- +pp4_01_csa_46: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(46) ,--i-- + b => pp3_04_buf(46) ,--i-- + c => pp3_03_buf(46) ,--i-- + sum => pp4_03(46) ,--o-- + car => pp4_02(45) );--o-- +pp4_01_csa_45: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(45) ,--i-- + b => pp3_04_buf(45) ,--i-- + c => pp3_03_buf(45) ,--i-- + sum => pp4_03(45) ,--o-- + car => pp4_02(44) );--o-- +pp4_01_csa_44: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(44) ,--i-- + b => pp3_04_buf(44) ,--i-- + c => pp3_03_buf(44) ,--i-- + sum => pp4_03(44) ,--o-- + car => pp4_02(43) );--o-- +pp4_01_csa_43: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(43) ,--i-- + b => pp3_04_buf(43) ,--i-- + c => pp3_03_buf(43) ,--i-- + sum => pp4_03(43) ,--o-- + car => pp4_02(42) );--o-- +pp4_01_csa_42: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(42) ,--i-- + b => pp3_04_buf(42) ,--i-- + c => pp3_03_buf(42) ,--i-- + sum => pp4_03(42) ,--o-- + car => pp4_02(41) );--o-- +pp4_01_csa_41: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(41) ,--i-- + b => pp3_04_buf(41) ,--i-- + c => pp3_03_buf(41) ,--i-- + sum => pp4_03(41) ,--o-- + car => pp4_02(40) );--o-- +pp4_01_csa_40: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(40) ,--i-- + b => pp3_04_buf(40) ,--i-- + c => pp3_03_buf(40) ,--i-- + sum => pp4_03(40) ,--o-- + car => pp4_02(39) );--o-- +pp4_01_csa_39: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(39) ,--i-- + b => pp3_04_buf(39) ,--i-- + c => pp3_03_buf(39) ,--i-- + sum => pp4_03(39) ,--o-- + car => pp4_02(38) );--o-- +pp4_01_csa_38: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(38) ,--i-- + b => pp3_04_buf(38) ,--i-- + c => pp3_03_buf(38) ,--i-- + sum => pp4_03(38) ,--o-- + car => pp4_02(37) );--o-- +pp4_01_csa_37: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(37) ,--i-- + b => pp3_04_buf(37) ,--i-- + c => pp3_03_buf(37) ,--i-- + sum => pp4_03(37) ,--o-- + car => pp4_02(36) );--o-- +pp4_01_csa_36: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_05_buf(36) ,--i-- + b => pp3_04_buf(36) ,--i-- + c => pp3_03_buf(36) ,--i-- + sum => pp4_03(36) ,--o-- + car => pp4_02(35) );--o-- +pp4_01_csa_35: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp3_04_buf(35) ,--i-- + b => pp3_03_buf(35) ,--i-- + sum => pp4_03(35) ,--o-- + car => pp4_02(34) );--o-- + + pp4_03(18 to 34) <= pp3_03_buf(18 to 34) ; + + +--//# 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111111111 +--//# 0000000000111111111122222222223333333333444444444455555555556666666666777777777788888888889999999999000000000 +--//# 0123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678 +--//# .................dddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddd.................. pp3_02 +--//# ddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddd_d.................................. pp3_01 +--//# ddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddd.................................... pp3_00 +--//# ------------------------------------------------------------------------------------------------------------- +--//# uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuoooooooooooooooooo.................. pp4_01 +--//# cccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccc__o.................................. pp4_00 + + + + + pp4_01(73 to 90) <= pp3_02_buf(73 to 90) ; + pp4_00(74) <= hot_one_74_buf ; + pp4_00(73) <= tidn ; + pp4_00(72) <= tidn ; + +pp4_00_csa_72: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(72) ,--i-- + b => pp3_01_buf(72) ,--i-- + c => pp3_00_buf(72) ,--i-- + sum => pp4_01(72) ,--o-- + car => pp4_00(71) );--o-- +pp4_00_csa_71: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(71) ,--i-- + b => pp3_01_buf(71) ,--i-- + c => pp3_00_buf(71) ,--i-- + sum => pp4_01(71) ,--o-- + car => pp4_00(70) );--o-- +pp4_00_csa_70: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(70) ,--i-- + b => pp3_01_buf(70) ,--i-- + c => pp3_00_buf(70) ,--i-- + sum => pp4_01(70) ,--o-- + car => pp4_00(69) );--o-- +pp4_00_csa_69: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(69) ,--i-- + b => pp3_01_buf(69) ,--i-- + c => pp3_00_buf(69) ,--i-- + sum => pp4_01(69) ,--o-- + car => pp4_00(68) );--o-- +pp4_00_csa_68: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(68) ,--i-- + b => pp3_01_buf(68) ,--i-- + c => pp3_00_buf(68) ,--i-- + sum => pp4_01(68) ,--o-- + car => pp4_00(67) );--o-- +pp4_00_csa_67: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(67) ,--i-- + b => pp3_01_buf(67) ,--i-- + c => pp3_00_buf(67) ,--i-- + sum => pp4_01(67) ,--o-- + car => pp4_00(66) );--o-- +pp4_00_csa_66: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(66) ,--i-- + b => pp3_01_buf(66) ,--i-- + c => pp3_00_buf(66) ,--i-- + sum => pp4_01(66) ,--o-- + car => pp4_00(65) );--o-- +pp4_00_csa_65: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(65) ,--i-- + b => pp3_01_buf(65) ,--i-- + c => pp3_00_buf(65) ,--i-- + sum => pp4_01(65) ,--o-- + car => pp4_00(64) );--o-- +pp4_00_csa_64: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(64) ,--i-- + b => pp3_01_buf(64) ,--i-- + c => pp3_00_buf(64) ,--i-- + sum => pp4_01(64) ,--o-- + car => pp4_00(63) );--o-- +pp4_00_csa_63: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(63) ,--i-- + b => pp3_01_buf(63) ,--i-- + c => pp3_00_buf(63) ,--i-- + sum => pp4_01(63) ,--o-- + car => pp4_00(62) );--o-- +pp4_00_csa_62: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(62) ,--i-- + b => pp3_01_buf(62) ,--i-- + c => pp3_00_buf(62) ,--i-- + sum => pp4_01(62) ,--o-- + car => pp4_00(61) );--o-- +pp4_00_csa_61: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(61) ,--i-- + b => pp3_01_buf(61) ,--i-- + c => pp3_00_buf(61) ,--i-- + sum => pp4_01(61) ,--o-- + car => pp4_00(60) );--o-- +pp4_00_csa_60: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(60) ,--i-- + b => pp3_01_buf(60) ,--i-- + c => pp3_00_buf(60) ,--i-- + sum => pp4_01(60) ,--o-- + car => pp4_00(59) );--o-- +pp4_00_csa_59: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(59) ,--i-- + b => pp3_01_buf(59) ,--i-- + c => pp3_00_buf(59) ,--i-- + sum => pp4_01(59) ,--o-- + car => pp4_00(58) );--o-- +pp4_00_csa_58: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(58) ,--i-- + b => pp3_01_buf(58) ,--i-- + c => pp3_00_buf(58) ,--i-- + sum => pp4_01(58) ,--o-- + car => pp4_00(57) );--o-- +pp4_00_csa_57: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(57) ,--i-- + b => pp3_01_buf(57) ,--i-- + c => pp3_00_buf(57) ,--i-- + sum => pp4_01(57) ,--o-- + car => pp4_00(56) );--o-- +pp4_00_csa_56: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(56) ,--i-- + b => pp3_01_buf(56) ,--i-- + c => pp3_00_buf(56) ,--i-- + sum => pp4_01(56) ,--o-- + car => pp4_00(55) );--o-- +pp4_00_csa_55: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(55) ,--i-- + b => pp3_01_buf(55) ,--i-- + c => pp3_00_buf(55) ,--i-- + sum => pp4_01(55) ,--o-- + car => pp4_00(54) );--o-- +pp4_00_csa_54: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(54) ,--i-- + b => pp3_01_buf(54) ,--i-- + c => pp3_00_buf(54) ,--i-- + sum => pp4_01(54) ,--o-- + car => pp4_00(53) );--o-- +pp4_00_csa_53: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(53) ,--i-- + b => pp3_01_buf(53) ,--i-- + c => pp3_00_buf(53) ,--i-- + sum => pp4_01(53) ,--o-- + car => pp4_00(52) );--o-- +pp4_00_csa_52: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(52) ,--i-- + b => pp3_01_buf(52) ,--i-- + c => pp3_00_buf(52) ,--i-- + sum => pp4_01(52) ,--o-- + car => pp4_00(51) );--o-- +pp4_00_csa_51: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(51) ,--i-- + b => pp3_01_buf(51) ,--i-- + c => pp3_00_buf(51) ,--i-- + sum => pp4_01(51) ,--o-- + car => pp4_00(50) );--o-- +pp4_00_csa_50: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(50) ,--i-- + b => pp3_01_buf(50) ,--i-- + c => pp3_00_buf(50) ,--i-- + sum => pp4_01(50) ,--o-- + car => pp4_00(49) );--o-- +pp4_00_csa_49: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(49) ,--i-- + b => pp3_01_buf(49) ,--i-- + c => pp3_00_buf(49) ,--i-- + sum => pp4_01(49) ,--o-- + car => pp4_00(48) );--o-- +pp4_00_csa_48: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(48) ,--i-- + b => pp3_01_buf(48) ,--i-- + c => pp3_00_buf(48) ,--i-- + sum => pp4_01(48) ,--o-- + car => pp4_00(47) );--o-- +pp4_00_csa_47: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(47) ,--i-- + b => pp3_01_buf(47) ,--i-- + c => pp3_00_buf(47) ,--i-- + sum => pp4_01(47) ,--o-- + car => pp4_00(46) );--o-- +pp4_00_csa_46: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(46) ,--i-- + b => pp3_01_buf(46) ,--i-- + c => pp3_00_buf(46) ,--i-- + sum => pp4_01(46) ,--o-- + car => pp4_00(45) );--o-- +pp4_00_csa_45: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(45) ,--i-- + b => pp3_01_buf(45) ,--i-- + c => pp3_00_buf(45) ,--i-- + sum => pp4_01(45) ,--o-- + car => pp4_00(44) );--o-- +pp4_00_csa_44: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(44) ,--i-- + b => pp3_01_buf(44) ,--i-- + c => pp3_00_buf(44) ,--i-- + sum => pp4_01(44) ,--o-- + car => pp4_00(43) );--o-- +pp4_00_csa_43: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(43) ,--i-- + b => pp3_01_buf(43) ,--i-- + c => pp3_00_buf(43) ,--i-- + sum => pp4_01(43) ,--o-- + car => pp4_00(42) );--o-- +pp4_00_csa_42: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(42) ,--i-- + b => pp3_01_buf(42) ,--i-- + c => pp3_00_buf(42) ,--i-- + sum => pp4_01(42) ,--o-- + car => pp4_00(41) );--o-- +pp4_00_csa_41: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(41) ,--i-- + b => pp3_01_buf(41) ,--i-- + c => pp3_00_buf(41) ,--i-- + sum => pp4_01(41) ,--o-- + car => pp4_00(40) );--o-- +pp4_00_csa_40: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(40) ,--i-- + b => pp3_01_buf(40) ,--i-- + c => pp3_00_buf(40) ,--i-- + sum => pp4_01(40) ,--o-- + car => pp4_00(39) );--o-- +pp4_00_csa_39: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(39) ,--i-- + b => pp3_01_buf(39) ,--i-- + c => pp3_00_buf(39) ,--i-- + sum => pp4_01(39) ,--o-- + car => pp4_00(38) );--o-- +pp4_00_csa_38: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(38) ,--i-- + b => pp3_01_buf(38) ,--i-- + c => pp3_00_buf(38) ,--i-- + sum => pp4_01(38) ,--o-- + car => pp4_00(37) );--o-- +pp4_00_csa_37: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(37) ,--i-- + b => pp3_01_buf(37) ,--i-- + c => pp3_00_buf(37) ,--i-- + sum => pp4_01(37) ,--o-- + car => pp4_00(36) );--o-- +pp4_00_csa_36: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(36) ,--i-- + b => pp3_01_buf(36) ,--i-- + c => pp3_00_buf(36) ,--i-- + sum => pp4_01(36) ,--o-- + car => pp4_00(35) );--o-- +pp4_00_csa_35: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(35) ,--i-- + b => pp3_01_buf(35) ,--i-- + c => pp3_00_buf(35) ,--i-- + sum => pp4_01(35) ,--o-- + car => pp4_00(34) );--o-- +pp4_00_csa_34: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(34) ,--i-- + b => pp3_01_buf(34) ,--i-- + c => pp3_00_buf(34) ,--i-- + sum => pp4_01(34) ,--o-- + car => pp4_00(33) );--o-- +pp4_00_csa_33: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(33) ,--i-- + b => pp3_01_buf(33) ,--i-- + c => pp3_00_buf(33) ,--i-- + sum => pp4_01(33) ,--o-- + car => pp4_00(32) );--o-- +pp4_00_csa_32: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(32) ,--i-- + b => pp3_01_buf(32) ,--i-- + c => pp3_00_buf(32) ,--i-- + sum => pp4_01(32) ,--o-- + car => pp4_00(31) );--o-- +pp4_00_csa_31: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(31) ,--i-- + b => pp3_01_buf(31) ,--i-- + c => pp3_00_buf(31) ,--i-- + sum => pp4_01(31) ,--o-- + car => pp4_00(30) );--o-- +pp4_00_csa_30: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(30) ,--i-- + b => pp3_01_buf(30) ,--i-- + c => pp3_00_buf(30) ,--i-- + sum => pp4_01(30) ,--o-- + car => pp4_00(29) );--o-- +pp4_00_csa_29: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(29) ,--i-- + b => pp3_01_buf(29) ,--i-- + c => pp3_00_buf(29) ,--i-- + sum => pp4_01(29) ,--o-- + car => pp4_00(28) );--o-- +pp4_00_csa_28: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(28) ,--i-- + b => pp3_01_buf(28) ,--i-- + c => pp3_00_buf(28) ,--i-- + sum => pp4_01(28) ,--o-- + car => pp4_00(27) );--o-- +pp4_00_csa_27: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(27) ,--i-- + b => pp3_01_buf(27) ,--i-- + c => pp3_00_buf(27) ,--i-- + sum => pp4_01(27) ,--o-- + car => pp4_00(26) );--o-- +pp4_00_csa_26: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(26) ,--i-- + b => pp3_01_buf(26) ,--i-- + c => pp3_00_buf(26) ,--i-- + sum => pp4_01(26) ,--o-- + car => pp4_00(25) );--o-- +pp4_00_csa_25: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(25) ,--i-- + b => pp3_01_buf(25) ,--i-- + c => pp3_00_buf(25) ,--i-- + sum => pp4_01(25) ,--o-- + car => pp4_00(24) );--o-- +pp4_00_csa_24: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(24) ,--i-- + b => pp3_01_buf(24) ,--i-- + c => pp3_00_buf(24) ,--i-- + sum => pp4_01(24) ,--o-- + car => pp4_00(23) );--o-- +pp4_00_csa_23: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(23) ,--i-- + b => pp3_01_buf(23) ,--i-- + c => pp3_00_buf(23) ,--i-- + sum => pp4_01(23) ,--o-- + car => pp4_00(22) );--o-- +pp4_00_csa_22: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(22) ,--i-- + b => pp3_01_buf(22) ,--i-- + c => pp3_00_buf(22) ,--i-- + sum => pp4_01(22) ,--o-- + car => pp4_00(21) );--o-- +pp4_00_csa_21: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(21) ,--i-- + b => pp3_01_buf(21) ,--i-- + c => pp3_00_buf(21) ,--i-- + sum => pp4_01(21) ,--o-- + car => pp4_00(20) );--o-- +pp4_00_csa_20: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(20) ,--i-- + b => pp3_01_buf(20) ,--i-- + c => pp3_00_buf(20) ,--i-- + sum => pp4_01(20) ,--o-- + car => pp4_00(19) );--o-- +pp4_00_csa_19: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(19) ,--i-- + b => pp3_01_buf(19) ,--i-- + c => pp3_00_buf(19) ,--i-- + sum => pp4_01(19) ,--o-- + car => pp4_00(18) );--o-- +pp4_00_csa_18: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(18) ,--i-- + b => pp3_01_buf(18) ,--i-- + c => pp3_00_buf(18) ,--i-- + sum => pp4_01(18) ,--o-- + car => pp4_00(17) );--o-- +pp4_00_csa_17: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp3_02_buf(17) ,--i-- + b => pp3_01_buf(17) ,--i-- + c => pp3_00_buf(17) ,--i-- + sum => pp4_01(17) ,--o-- + car => pp4_00(16) );--o-- +pp4_00_csa_16: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp3_01_buf(16) ,--i-- + b => pp3_00_buf(16) ,--i-- + sum => pp4_01(16) ,--o-- + car => pp4_00(15) );--o-- +pp4_00_csa_15: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp3_01_buf(15) ,--i-- + b => pp3_00_buf(15) ,--i-- + sum => pp4_01(15) ,--o-- + car => pp4_00(14) );--o-- +pp4_00_csa_14: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp3_01_buf(14) ,--i-- + b => pp3_00_buf(14) ,--i-- + sum => pp4_01(14) ,--o-- + car => pp4_00(13) );--o-- +pp4_00_csa_13: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp3_01_buf(13) ,--i-- + b => pp3_00_buf(13) ,--i-- + sum => pp4_01(13) ,--o-- + car => pp4_00(12) );--o-- +pp4_00_csa_12: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp3_01_buf(12) ,--i-- + b => pp3_00_buf(12) ,--i-- + sum => pp4_01(12) ,--o-- + car => pp4_00(11) );--o-- +pp4_00_csa_11: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp3_01_buf(11) ,--i-- + b => pp3_00_buf(11) ,--i-- + sum => pp4_01(11) ,--o-- + car => pp4_00(10) );--o-- +pp4_00_csa_10: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp3_01_buf(10) ,--i-- + b => pp3_00_buf(10) ,--i-- + sum => pp4_01(10) ,--o-- + car => pp4_00(9) );--o-- +pp4_00_csa_09: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp3_01_buf(9) ,--i-- + b => pp3_00_buf(9) ,--i-- + sum => pp4_01(9) ,--o-- + car => pp4_00(8) );--o-- +pp4_00_csa_08: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp3_01_buf(8) ,--i-- + b => pp3_00_buf(8) ,--i-- + sum => pp4_01(8) ,--o-- + car => pp4_00(7) );--o-- +pp4_00_csa_07: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp3_01_buf(7) ,--i-- + b => pp3_00_buf(7) ,--i-- + sum => pp4_01(7) ,--o-- + car => pp4_00(6) );--o-- +pp4_00_csa_06: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp3_01_buf(6) ,--i-- + b => pp3_00_buf(6) ,--i-- + sum => pp4_01(6) ,--o-- + car => pp4_00(5) );--o-- +pp4_00_csa_05: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp3_01_buf(5) ,--i-- + b => pp3_00_buf(5) ,--i-- + sum => pp4_01(5) ,--o-- + car => pp4_00(4) );--o-- +pp4_00_csa_04: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp3_01_buf(4) ,--i-- + b => pp3_00_buf(4) ,--i-- + sum => pp4_01(4) ,--o-- + car => pp4_00(3) );--o-- +pp4_00_csa_03: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp3_01_buf(3) ,--i-- + b => pp3_00_buf(3) ,--i-- + sum => pp4_01(3) ,--o-- + car => pp4_00(2) );--o-- +pp4_00_csa_02: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp3_01_buf(2) ,--i-- + b => pp3_00_buf(2) ,--i-- + sum => pp4_01(2) ,--o-- + car => pp4_00(1) );--o-- +pp4_00_csa_01: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp3_01_buf(1) ,--i-- + b => pp3_00_buf(1) ,--i-- + sum => pp4_01(1) ,--o-- + car => pp4_00(0) );--o-- + + + --//################################################## + --//# Compressor Level 5 + --//################################################## + +--//# 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111111111 +--//# 0000000000111111111122222222223333333333444444444455555555556666666666777777777788888888889999999999000000000 +--//# 0123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678 +--//# ..................ooooooooooooooooouuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuoooooooooooooooo pp4_03 +--//# ..................................cccccccccccccccccccccccccccccccccccccccccccccccccccccccccc_oooooooooooooooo pp4_02 +--//# uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuoooooooooooooooooo.................. pp4_01 +--//# cccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccc__o.................................. pp4_00 +--//# ------------------------------------------------------------------------------------------------------------- +--//# uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuoooooooooooooooooo pp5_01 +--//# cccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccc_o_oooooooooooooooo pp5_00 + + + + pp5_01(91 to 108) <= pp4_03(91 to 108) ; + pp5_00(93 to 108) <= pp4_02(93 to 108) ; + pp5_00(92) <= tidn ; + pp5_00(91) <= pp4_02(91); + pp5_00(90) <= tidn; + +pp5_00_csa_90: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp4_03(90) ,--i-- + b => pp4_02(90) ,--i-- + c => pp4_01(90) ,--i-- + sum => pp5_01(90) ,--o-- + car => pp5_00(89) );--o-- +pp5_00_csa_89: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp4_03(89) ,--i-- + b => pp4_02(89) ,--i-- + c => pp4_01(89) ,--i-- + sum => pp5_01(89) ,--o-- + car => pp5_00(88) );--o-- +pp5_00_csa_88: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp4_03(88) ,--i-- + b => pp4_02(88) ,--i-- + c => pp4_01(88) ,--i-- + sum => pp5_01(88) ,--o-- + car => pp5_00(87) );--o-- +pp5_00_csa_87: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp4_03(87) ,--i-- + b => pp4_02(87) ,--i-- + c => pp4_01(87) ,--i-- + sum => pp5_01(87) ,--o-- + car => pp5_00(86) );--o-- +pp5_00_csa_86: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp4_03(86) ,--i-- + b => pp4_02(86) ,--i-- + c => pp4_01(86) ,--i-- + sum => pp5_01(86) ,--o-- + car => pp5_00(85) );--o-- +pp5_00_csa_85: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp4_03(85) ,--i-- + b => pp4_02(85) ,--i-- + c => pp4_01(85) ,--i-- + sum => pp5_01(85) ,--o-- + car => pp5_00(84) );--o-- +pp5_00_csa_84: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp4_03(84) ,--i-- + b => pp4_02(84) ,--i-- + c => pp4_01(84) ,--i-- + sum => pp5_01(84) ,--o-- + car => pp5_00(83) );--o-- +pp5_00_csa_83: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp4_03(83) ,--i-- + b => pp4_02(83) ,--i-- + c => pp4_01(83) ,--i-- + sum => pp5_01(83) ,--o-- + car => pp5_00(82) );--o-- +pp5_00_csa_82: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp4_03(82) ,--i-- + b => pp4_02(82) ,--i-- + c => pp4_01(82) ,--i-- + sum => pp5_01(82) ,--o-- + car => pp5_00(81) );--o-- +pp5_00_csa_81: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp4_03(81) ,--i-- + b => pp4_02(81) ,--i-- + c => pp4_01(81) ,--i-- + sum => pp5_01(81) ,--o-- + car => pp5_00(80) );--o-- +pp5_00_csa_80: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp4_03(80) ,--i-- + b => pp4_02(80) ,--i-- + c => pp4_01(80) ,--i-- + sum => pp5_01(80) ,--o-- + car => pp5_00(79) );--o-- +pp5_00_csa_79: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp4_03(79) ,--i-- + b => pp4_02(79) ,--i-- + c => pp4_01(79) ,--i-- + sum => pp5_01(79) ,--o-- + car => pp5_00(78) );--o-- +pp5_00_csa_78: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp4_03(78) ,--i-- + b => pp4_02(78) ,--i-- + c => pp4_01(78) ,--i-- + sum => pp5_01(78) ,--o-- + car => pp5_00(77) );--o-- +pp5_00_csa_77: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp4_03(77) ,--i-- + b => pp4_02(77) ,--i-- + c => pp4_01(77) ,--i-- + sum => pp5_01(77) ,--o-- + car => pp5_00(76) );--o-- +pp5_00_csa_76: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp4_03(76) ,--i-- + b => pp4_02(76) ,--i-- + c => pp4_01(76) ,--i-- + sum => pp5_01(76) ,--o-- + car => pp5_00(75) );--o-- +pp5_00_csa_75: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp4_03(75) ,--i-- + b => pp4_02(75) ,--i-- + c => pp4_01(75) ,--i-- + sum => pp5_01(75) ,--o-- + car => pp5_00(74) );--o-- +pp5_00_csa_74: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(74) ,--i-- + b => pp4_02(74) ,--i-- + c => pp4_01(74) ,--i-- + d => pp4_00(74) ,--i-- + ki => tidn ,--i-- + ko => pp5_00_ko(73) ,--o-- + sum => pp5_01(74) ,--o-- + car => pp5_00(73) );--o-- +pp5_00_csa_73: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(73) ,--i-- + b => pp4_02(73) ,--i-- + c => pp4_01(73) ,--i-- + d => tidn ,--i-- + ki => pp5_00_ko(73) ,--i-- + ko => pp5_00_ko(72) ,--o-- + sum => pp5_01(73) ,--o-- + car => pp5_00(72) );--o-- +pp5_00_csa_72: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(72) ,--i-- + b => pp4_02(72) ,--i-- + c => pp4_01(72) ,--i-- + d => tidn ,--i-- + ki => pp5_00_ko(72) ,--i-- + ko => pp5_00_ko(71) ,--o-- + sum => pp5_01(72) ,--o-- + car => pp5_00(71) );--o-- +pp5_00_csa_71: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(71) ,--i-- + b => pp4_02(71) ,--i-- + c => pp4_01(71) ,--i-- + d => pp4_00(71) ,--i-- + ki => pp5_00_ko(71) ,--i-- + ko => pp5_00_ko(70) ,--o-- + sum => pp5_01(71) ,--o-- + car => pp5_00(70) );--o-- +pp5_00_csa_70: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(70) ,--i-- + b => pp4_02(70) ,--i-- + c => pp4_01(70) ,--i-- + d => pp4_00(70) ,--i-- + ki => pp5_00_ko(70) ,--i-- + ko => pp5_00_ko(69) ,--o-- + sum => pp5_01(70) ,--o-- + car => pp5_00(69) );--o-- +pp5_00_csa_69: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(69) ,--i-- + b => pp4_02(69) ,--i-- + c => pp4_01(69) ,--i-- + d => pp4_00(69) ,--i-- + ki => pp5_00_ko(69) ,--i-- + ko => pp5_00_ko(68) ,--o-- + sum => pp5_01(69) ,--o-- + car => pp5_00(68) );--o-- +pp5_00_csa_68: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(68) ,--i-- + b => pp4_02(68) ,--i-- + c => pp4_01(68) ,--i-- + d => pp4_00(68) ,--i-- + ki => pp5_00_ko(68) ,--i-- + ko => pp5_00_ko(67) ,--o-- + sum => pp5_01(68) ,--o-- + car => pp5_00(67) );--o-- +pp5_00_csa_67: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(67) ,--i-- + b => pp4_02(67) ,--i-- + c => pp4_01(67) ,--i-- + d => pp4_00(67) ,--i-- + ki => pp5_00_ko(67) ,--i-- + ko => pp5_00_ko(66) ,--o-- + sum => pp5_01(67) ,--o-- + car => pp5_00(66) );--o-- +pp5_00_csa_66: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(66) ,--i-- + b => pp4_02(66) ,--i-- + c => pp4_01(66) ,--i-- + d => pp4_00(66) ,--i-- + ki => pp5_00_ko(66) ,--i-- + ko => pp5_00_ko(65) ,--o-- + sum => pp5_01(66) ,--o-- + car => pp5_00(65) );--o-- +pp5_00_csa_65: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(65) ,--i-- + b => pp4_02(65) ,--i-- + c => pp4_01(65) ,--i-- + d => pp4_00(65) ,--i-- + ki => pp5_00_ko(65) ,--i-- + ko => pp5_00_ko(64) ,--o-- + sum => pp5_01(65) ,--o-- + car => pp5_00(64) );--o-- +pp5_00_csa_64: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(64) ,--i-- + b => pp4_02(64) ,--i-- + c => pp4_01(64) ,--i-- + d => pp4_00(64) ,--i-- + ki => pp5_00_ko(64) ,--i-- + ko => pp5_00_ko(63) ,--o-- + sum => pp5_01(64) ,--o-- + car => pp5_00(63) );--o-- +pp5_00_csa_63: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(63) ,--i-- + b => pp4_02(63) ,--i-- + c => pp4_01(63) ,--i-- + d => pp4_00(63) ,--i-- + ki => pp5_00_ko(63) ,--i-- + ko => pp5_00_ko(62) ,--o-- + sum => pp5_01(63) ,--o-- + car => pp5_00(62) );--o-- +pp5_00_csa_62: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(62) ,--i-- + b => pp4_02(62) ,--i-- + c => pp4_01(62) ,--i-- + d => pp4_00(62) ,--i-- + ki => pp5_00_ko(62) ,--i-- + ko => pp5_00_ko(61) ,--o-- + sum => pp5_01(62) ,--o-- + car => pp5_00(61) );--o-- +pp5_00_csa_61: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(61) ,--i-- + b => pp4_02(61) ,--i-- + c => pp4_01(61) ,--i-- + d => pp4_00(61) ,--i-- + ki => pp5_00_ko(61) ,--i-- + ko => pp5_00_ko(60) ,--o-- + sum => pp5_01(61) ,--o-- + car => pp5_00(60) );--o-- +pp5_00_csa_60: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(60) ,--i-- + b => pp4_02(60) ,--i-- + c => pp4_01(60) ,--i-- + d => pp4_00(60) ,--i-- + ki => pp5_00_ko(60) ,--i-- + ko => pp5_00_ko(59) ,--o-- + sum => pp5_01(60) ,--o-- + car => pp5_00(59) );--o-- +pp5_00_csa_59: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(59) ,--i-- + b => pp4_02(59) ,--i-- + c => pp4_01(59) ,--i-- + d => pp4_00(59) ,--i-- + ki => pp5_00_ko(59) ,--i-- + ko => pp5_00_ko(58) ,--o-- + sum => pp5_01(59) ,--o-- + car => pp5_00(58) );--o-- +pp5_00_csa_58: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(58) ,--i-- + b => pp4_02(58) ,--i-- + c => pp4_01(58) ,--i-- + d => pp4_00(58) ,--i-- + ki => pp5_00_ko(58) ,--i-- + ko => pp5_00_ko(57) ,--o-- + sum => pp5_01(58) ,--o-- + car => pp5_00(57) );--o-- +pp5_00_csa_57: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(57) ,--i-- + b => pp4_02(57) ,--i-- + c => pp4_01(57) ,--i-- + d => pp4_00(57) ,--i-- + ki => pp5_00_ko(57) ,--i-- + ko => pp5_00_ko(56) ,--o-- + sum => pp5_01(57) ,--o-- + car => pp5_00(56) );--o-- +pp5_00_csa_56: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(56) ,--i-- + b => pp4_02(56) ,--i-- + c => pp4_01(56) ,--i-- + d => pp4_00(56) ,--i-- + ki => pp5_00_ko(56) ,--i-- + ko => pp5_00_ko(55) ,--o-- + sum => pp5_01(56) ,--o-- + car => pp5_00(55) );--o-- +pp5_00_csa_55: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(55) ,--i-- + b => pp4_02(55) ,--i-- + c => pp4_01(55) ,--i-- + d => pp4_00(55) ,--i-- + ki => pp5_00_ko(55) ,--i-- + ko => pp5_00_ko(54) ,--o-- + sum => pp5_01(55) ,--o-- + car => pp5_00(54) );--o-- +pp5_00_csa_54: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(54) ,--i-- + b => pp4_02(54) ,--i-- + c => pp4_01(54) ,--i-- + d => pp4_00(54) ,--i-- + ki => pp5_00_ko(54) ,--i-- + ko => pp5_00_ko(53) ,--o-- + sum => pp5_01(54) ,--o-- + car => pp5_00(53) );--o-- +pp5_00_csa_53: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(53) ,--i-- + b => pp4_02(53) ,--i-- + c => pp4_01(53) ,--i-- + d => pp4_00(53) ,--i-- + ki => pp5_00_ko(53) ,--i-- + ko => pp5_00_ko(52) ,--o-- + sum => pp5_01(53) ,--o-- + car => pp5_00(52) );--o-- +pp5_00_csa_52: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(52) ,--i-- + b => pp4_02(52) ,--i-- + c => pp4_01(52) ,--i-- + d => pp4_00(52) ,--i-- + ki => pp5_00_ko(52) ,--i-- + ko => pp5_00_ko(51) ,--o-- + sum => pp5_01(52) ,--o-- + car => pp5_00(51) );--o-- +pp5_00_csa_51: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(51) ,--i-- + b => pp4_02(51) ,--i-- + c => pp4_01(51) ,--i-- + d => pp4_00(51) ,--i-- + ki => pp5_00_ko(51) ,--i-- + ko => pp5_00_ko(50) ,--o-- + sum => pp5_01(51) ,--o-- + car => pp5_00(50) );--o-- +pp5_00_csa_50: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(50) ,--i-- + b => pp4_02(50) ,--i-- + c => pp4_01(50) ,--i-- + d => pp4_00(50) ,--i-- + ki => pp5_00_ko(50) ,--i-- + ko => pp5_00_ko(49) ,--o-- + sum => pp5_01(50) ,--o-- + car => pp5_00(49) );--o-- +pp5_00_csa_49: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(49) ,--i-- + b => pp4_02(49) ,--i-- + c => pp4_01(49) ,--i-- + d => pp4_00(49) ,--i-- + ki => pp5_00_ko(49) ,--i-- + ko => pp5_00_ko(48) ,--o-- + sum => pp5_01(49) ,--o-- + car => pp5_00(48) );--o-- +pp5_00_csa_48: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(48) ,--i-- + b => pp4_02(48) ,--i-- + c => pp4_01(48) ,--i-- + d => pp4_00(48) ,--i-- + ki => pp5_00_ko(48) ,--i-- + ko => pp5_00_ko(47) ,--o-- + sum => pp5_01(48) ,--o-- + car => pp5_00(47) );--o-- +pp5_00_csa_47: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(47) ,--i-- + b => pp4_02(47) ,--i-- + c => pp4_01(47) ,--i-- + d => pp4_00(47) ,--i-- + ki => pp5_00_ko(47) ,--i-- + ko => pp5_00_ko(46) ,--o-- + sum => pp5_01(47) ,--o-- + car => pp5_00(46) );--o-- +pp5_00_csa_46: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(46) ,--i-- + b => pp4_02(46) ,--i-- + c => pp4_01(46) ,--i-- + d => pp4_00(46) ,--i-- + ki => pp5_00_ko(46) ,--i-- + ko => pp5_00_ko(45) ,--o-- + sum => pp5_01(46) ,--o-- + car => pp5_00(45) );--o-- +pp5_00_csa_45: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(45) ,--i-- + b => pp4_02(45) ,--i-- + c => pp4_01(45) ,--i-- + d => pp4_00(45) ,--i-- + ki => pp5_00_ko(45) ,--i-- + ko => pp5_00_ko(44) ,--o-- + sum => pp5_01(45) ,--o-- + car => pp5_00(44) );--o-- +pp5_00_csa_44: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(44) ,--i-- + b => pp4_02(44) ,--i-- + c => pp4_01(44) ,--i-- + d => pp4_00(44) ,--i-- + ki => pp5_00_ko(44) ,--i-- + ko => pp5_00_ko(43) ,--o-- + sum => pp5_01(44) ,--o-- + car => pp5_00(43) );--o-- +pp5_00_csa_43: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(43) ,--i-- + b => pp4_02(43) ,--i-- + c => pp4_01(43) ,--i-- + d => pp4_00(43) ,--i-- + ki => pp5_00_ko(43) ,--i-- + ko => pp5_00_ko(42) ,--o-- + sum => pp5_01(43) ,--o-- + car => pp5_00(42) );--o-- +pp5_00_csa_42: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(42) ,--i-- + b => pp4_02(42) ,--i-- + c => pp4_01(42) ,--i-- + d => pp4_00(42) ,--i-- + ki => pp5_00_ko(42) ,--i-- + ko => pp5_00_ko(41) ,--o-- + sum => pp5_01(42) ,--o-- + car => pp5_00(41) );--o-- +pp5_00_csa_41: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(41) ,--i-- + b => pp4_02(41) ,--i-- + c => pp4_01(41) ,--i-- + d => pp4_00(41) ,--i-- + ki => pp5_00_ko(41) ,--i-- + ko => pp5_00_ko(40) ,--o-- + sum => pp5_01(41) ,--o-- + car => pp5_00(40) );--o-- +pp5_00_csa_40: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(40) ,--i-- + b => pp4_02(40) ,--i-- + c => pp4_01(40) ,--i-- + d => pp4_00(40) ,--i-- + ki => pp5_00_ko(40) ,--i-- + ko => pp5_00_ko(39) ,--o-- + sum => pp5_01(40) ,--o-- + car => pp5_00(39) );--o-- +pp5_00_csa_39: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(39) ,--i-- + b => pp4_02(39) ,--i-- + c => pp4_01(39) ,--i-- + d => pp4_00(39) ,--i-- + ki => pp5_00_ko(39) ,--i-- + ko => pp5_00_ko(38) ,--o-- + sum => pp5_01(39) ,--o-- + car => pp5_00(38) );--o-- +pp5_00_csa_38: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(38) ,--i-- + b => pp4_02(38) ,--i-- + c => pp4_01(38) ,--i-- + d => pp4_00(38) ,--i-- + ki => pp5_00_ko(38) ,--i-- + ko => pp5_00_ko(37) ,--o-- + sum => pp5_01(38) ,--o-- + car => pp5_00(37) );--o-- +pp5_00_csa_37: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(37) ,--i-- + b => pp4_02(37) ,--i-- + c => pp4_01(37) ,--i-- + d => pp4_00(37) ,--i-- + ki => pp5_00_ko(37) ,--i-- + ko => pp5_00_ko(36) ,--o-- + sum => pp5_01(37) ,--o-- + car => pp5_00(36) );--o-- +pp5_00_csa_36: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(36) ,--i-- + b => pp4_02(36) ,--i-- + c => pp4_01(36) ,--i-- + d => pp4_00(36) ,--i-- + ki => pp5_00_ko(36) ,--i-- + ko => pp5_00_ko(35) ,--o-- + sum => pp5_01(36) ,--o-- + car => pp5_00(35) );--o-- +pp5_00_csa_35: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(35) ,--i-- + b => pp4_02(35) ,--i-- + c => pp4_01(35) ,--i-- + d => pp4_00(35) ,--i-- + ki => pp5_00_ko(35) ,--i-- + ko => pp5_00_ko(34) ,--o-- + sum => pp5_01(35) ,--o-- + car => pp5_00(34) );--o-- +pp5_00_csa_34: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(34) ,--i-- + b => pp4_02(34) ,--i-- + c => pp4_01(34) ,--i-- + d => pp4_00(34) ,--i-- + ki => pp5_00_ko(34) ,--i-- + ko => pp5_00_ko(33) ,--o-- + sum => pp5_01(34) ,--o-- + car => pp5_00(33) );--o-- +pp5_00_csa_33: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(33) ,--i-- + b => pp4_01(33) ,--i-- + c => pp4_00(33) ,--i-- + d => tidn ,--i-- + ki => pp5_00_ko(33) ,--i-- + ko => pp5_00_ko(32) ,--o-- + sum => pp5_01(33) ,--o-- + car => pp5_00(32) );--o-- +pp5_00_csa_32: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(32) ,--i-- + b => pp4_01(32) ,--i-- + c => pp4_00(32) ,--i-- + d => tidn ,--i-- + ki => pp5_00_ko(32) ,--i-- + ko => pp5_00_ko(31) ,--o-- + sum => pp5_01(32) ,--o-- + car => pp5_00(31) );--o-- +pp5_00_csa_31: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(31) ,--i-- + b => pp4_01(31) ,--i-- + c => pp4_00(31) ,--i-- + d => tidn ,--i-- + ki => pp5_00_ko(31) ,--i-- + ko => pp5_00_ko(30) ,--o-- + sum => pp5_01(31) ,--o-- + car => pp5_00(30) );--o-- +pp5_00_csa_30: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(30) ,--i-- + b => pp4_01(30) ,--i-- + c => pp4_00(30) ,--i-- + d => tidn ,--i-- + ki => pp5_00_ko(30) ,--i-- + ko => pp5_00_ko(29) ,--o-- + sum => pp5_01(30) ,--o-- + car => pp5_00(29) );--o-- +pp5_00_csa_29: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(29) ,--i-- + b => pp4_01(29) ,--i-- + c => pp4_00(29) ,--i-- + d => tidn ,--i-- + ki => pp5_00_ko(29) ,--i-- + ko => pp5_00_ko(28) ,--o-- + sum => pp5_01(29) ,--o-- + car => pp5_00(28) );--o-- +pp5_00_csa_28: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(28) ,--i-- + b => pp4_01(28) ,--i-- + c => pp4_00(28) ,--i-- + d => tidn ,--i-- + ki => pp5_00_ko(28) ,--i-- + ko => pp5_00_ko(27) ,--o-- + sum => pp5_01(28) ,--o-- + car => pp5_00(27) );--o-- +pp5_00_csa_27: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(27) ,--i-- + b => pp4_01(27) ,--i-- + c => pp4_00(27) ,--i-- + d => tidn ,--i-- + ki => pp5_00_ko(27) ,--i-- + ko => pp5_00_ko(26) ,--o-- + sum => pp5_01(27) ,--o-- + car => pp5_00(26) );--o-- +pp5_00_csa_26: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(26) ,--i-- + b => pp4_01(26) ,--i-- + c => pp4_00(26) ,--i-- + d => tidn ,--i-- + ki => pp5_00_ko(26) ,--i-- + ko => pp5_00_ko(25) ,--o-- + sum => pp5_01(26) ,--o-- + car => pp5_00(25) );--o-- +pp5_00_csa_25: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(25) ,--i-- + b => pp4_01(25) ,--i-- + c => pp4_00(25) ,--i-- + d => tidn ,--i-- + ki => pp5_00_ko(25) ,--i-- + ko => pp5_00_ko(24) ,--o-- + sum => pp5_01(25) ,--o-- + car => pp5_00(24) );--o-- +pp5_00_csa_24: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(24) ,--i-- + b => pp4_01(24) ,--i-- + c => pp4_00(24) ,--i-- + d => tidn ,--i-- + ki => pp5_00_ko(24) ,--i-- + ko => pp5_00_ko(23) ,--o-- + sum => pp5_01(24) ,--o-- + car => pp5_00(23) );--o-- +pp5_00_csa_23: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(23) ,--i-- + b => pp4_01(23) ,--i-- + c => pp4_00(23) ,--i-- + d => tidn ,--i-- + ki => pp5_00_ko(23) ,--i-- + ko => pp5_00_ko(22) ,--o-- + sum => pp5_01(23) ,--o-- + car => pp5_00(22) );--o-- +pp5_00_csa_22: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(22) ,--i-- + b => pp4_01(22) ,--i-- + c => pp4_00(22) ,--i-- + d => tidn ,--i-- + ki => pp5_00_ko(22) ,--i-- + ko => pp5_00_ko(21) ,--o-- + sum => pp5_01(22) ,--o-- + car => pp5_00(21) );--o-- +pp5_00_csa_21: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(21) ,--i-- + b => pp4_01(21) ,--i-- + c => pp4_00(21) ,--i-- + d => tidn ,--i-- + ki => pp5_00_ko(21) ,--i-- + ko => pp5_00_ko(20) ,--o-- + sum => pp5_01(21) ,--o-- + car => pp5_00(20) );--o-- +pp5_00_csa_20: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(20) ,--i-- + b => pp4_01(20) ,--i-- + c => pp4_00(20) ,--i-- + d => tidn ,--i-- + ki => pp5_00_ko(20) ,--i-- + ko => pp5_00_ko(19) ,--o-- + sum => pp5_01(20) ,--o-- + car => pp5_00(19) );--o-- +pp5_00_csa_19: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(19) ,--i-- + b => pp4_01(19) ,--i-- + c => pp4_00(19) ,--i-- + d => tidn ,--i-- + ki => pp5_00_ko(19) ,--i-- + ko => pp5_00_ko(18) ,--o-- + sum => pp5_01(19) ,--o-- + car => pp5_00(18) );--o-- +pp5_00_csa_18: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp4_03(18) ,--i-- + b => pp4_01(18) ,--i-- + c => pp4_00(18) ,--i-- + d => tidn ,--i-- + ki => pp5_00_ko(18) ,--i-- + ko => pp5_00_ko(17) ,--o-- + sum => pp5_01(18) ,--o-- + car => pp5_00(17) );--o-- +pp5_00_csa_17: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp4_01(17) ,--i-- + b => pp4_00(17) ,--i-- + c => pp5_00_ko(17) ,--i-- + sum => pp5_01(17) ,--o-- + car => pp5_00(16) );--o-- +pp5_00_csa_16: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp4_01(16) ,--i-- + b => pp4_00(16) ,--i-- + sum => pp5_01(16) ,--o-- + car => pp5_00(15) );--o-- +pp5_00_csa_15: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp4_01(15) ,--i-- + b => pp4_00(15) ,--i-- + sum => pp5_01(15) ,--o-- + car => pp5_00(14) );--o-- +pp5_00_csa_14: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp4_01(14) ,--i-- + b => pp4_00(14) ,--i-- + sum => pp5_01(14) ,--o-- + car => pp5_00(13) );--o-- +pp5_00_csa_13: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp4_01(13) ,--i-- + b => pp4_00(13) ,--i-- + sum => pp5_01(13) ,--o-- + car => pp5_00(12) );--o-- +pp5_00_csa_12: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp4_01(12) ,--i-- + b => pp4_00(12) ,--i-- + sum => pp5_01(12) ,--o-- + car => pp5_00(11) );--o-- +pp5_00_csa_11: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp4_01(11) ,--i-- + b => pp4_00(11) ,--i-- + sum => pp5_01(11) ,--o-- + car => pp5_00(10) );--o-- +pp5_00_csa_10: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp4_01(10) ,--i-- + b => pp4_00(10) ,--i-- + sum => pp5_01(10) ,--o-- + car => pp5_00(9) );--o-- +pp5_00_csa_09: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp4_01(9) ,--i-- + b => pp4_00(9) ,--i-- + sum => pp5_01(9) ,--o-- + car => pp5_00(8) );--o-- +pp5_00_csa_08: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp4_01(8) ,--i-- + b => pp4_00(8) ,--i-- + sum => pp5_01(8) ,--o-- + car => pp5_00(7) );--o-- +pp5_00_csa_07: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp4_01(7) ,--i-- + b => pp4_00(7) ,--i-- + sum => pp5_01(7) ,--o-- + car => pp5_00(6) );--o-- +pp5_00_csa_06: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp4_01(6) ,--i-- + b => pp4_00(6) ,--i-- + sum => pp5_01(6) ,--o-- + car => pp5_00(5) );--o-- +pp5_00_csa_05: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp4_01(5) ,--i-- + b => pp4_00(5) ,--i-- + sum => pp5_01(5) ,--o-- + car => pp5_00(4) );--o-- +pp5_00_csa_04: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp4_01(4) ,--i-- + b => pp4_00(4) ,--i-- + sum => pp5_01(4) ,--o-- + car => pp5_00(3) );--o-- +pp5_00_csa_03: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp4_01(3) ,--i-- + b => pp4_00(3) ,--i-- + sum => pp5_01(3) ,--o-- + car => pp5_00(2) );--o-- +pp5_00_csa_02: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp4_01(2) ,--i-- + b => pp4_00(2) ,--i-- + sum => pp5_01(2) ,--o-- + car => pp5_00(1) );--o-- +pp5_00_csa_01: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp4_01(1) ,--i-- + b => pp4_00(1) ,--i-- + sum => pp5_01(1) ,--o-- + car => pp5_00(0) );--o-- + + + + sum62(1 to 108) <= pp5_01(1 to 108); -- just a rename + car62(1 to 108) <= pp5_00(1 to 108); -- just a rename + + +end; -- fuq_mul_62 ARCHITECTURE diff --git a/rel/src/vhdl/work/fuq_mul_92.vhdl b/rel/src/vhdl/work/fuq_mul_92.vhdl new file mode 100644 index 0000000..e55bb71 --- /dev/null +++ b/rel/src/vhdl/work/fuq_mul_92.vhdl @@ -0,0 +1,3672 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; +library clib ; + + +entity fuq_mul_92 is + generic(expand_type : integer := 2; -- 0 - ibm tech, 1 - other (FPGA), 2 - MPG + inst : natural := 0 ); + port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; --perv + si : in std_ulogic; --perv + so : out std_ulogic; --perv + ex1_act : in std_ulogic; --act + lcb_delay_lclkr : in std_ulogic; --perv + lcb_mpw1_b : in std_ulogic; --perv + lcb_mpw2_b : in std_ulogic; --perv added bmf 2007 7 13 + thold_b : in std_ulogic; --lcbor bmf 2007 7 13 + forcee : in std_ulogic; --lcbor bmf 2007 7 13 + lcb_sg : in std_ulogic; --perv + c_frac : in std_ulogic_vector(0 to 53); -- Multiplicand + a_frac : in std_ulogic_vector(17 to 35); -- Multiplier + hot_one_out : out std_ulogic; + sum92 : out std_ulogic_vector(2 to 74); + car92 : out std_ulogic_vector(1 to 74) + ); + +-- synopsys translate_off + + + + + + + +-- synopsys translate_on +end fuq_mul_92; -- ENTITY + +architecture fuq_mul_92 of fuq_mul_92 is + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal s_neg : std_ulogic_vector(0 to 8); + signal s_x : std_ulogic_vector(0 to 8); + signal s_x2 : std_ulogic_vector(0 to 8); + signal xtd_2_add : std_ulogic_vector(0 to 7); + signal hot_one_din, hot_one_out_b : std_ulogic; + + signal pp0_00 : std_ulogic_vector(2 to 60); + signal pp0_01 : std_ulogic_vector(4 to 62); + signal pp0_02 : std_ulogic_vector(6 to 64); + signal pp0_03 : std_ulogic_vector(8 to 66); + signal pp0_04 : std_ulogic_vector(10 to 68); + signal pp0_05 : std_ulogic_vector(12 to 70); + signal pp0_06 : std_ulogic_vector(14 to 72); + signal pp0_07 : std_ulogic_vector(16 to 74); + signal pp0_08 : std_ulogic_vector(17 to 74); -- missing the hot one from neighbor 9:2 + signal pp1_05 : std_ulogic_vector(14 to 74); -- sum + signal pp1_04 : std_ulogic_vector(15 to 74); -- car + signal pp1_03 : std_ulogic_vector(8 to 70); -- sum + signal pp1_02 : std_ulogic_vector(9 to 68); -- car + signal pp1_01 : std_ulogic_vector(2 to 64); -- sum + signal pp1_00 : std_ulogic_vector(3 to 62); -- car + signal pp2_03 : std_ulogic_vector(8 to 74); -- sum + signal pp2_02 : std_ulogic_vector(13 to 74); -- car + signal pp2_01 : std_ulogic_vector(2 to 68); -- sum + signal pp2_00 : std_ulogic_vector(2 to 64); -- car + signal pp3_01 : std_ulogic_vector(2 to 74); -- sum + signal pp3_00 : std_ulogic_vector(1 to 74); -- car + signal pp3_00_ko : std_ulogic_vector(7 to 63); -- ko + signal pp3_01_q_b : std_ulogic_vector(2 to 74); + signal pp3_00_q_b : std_ulogic_vector(1 to 74); + + signal pp3_lat_sum_so :std_ulogic_vector(0 to 72); + signal pp3_lat_car_so :std_ulogic_vector(0 to 70); + signal mul92_d1clk, mul92_d2clk :std_ulogic ; + signal mul92_lclk :clk_logic ; + + signal unused :std_ulogic ; + + + + + + + + + + + + +begin + +unused <= + pp0_00(2) or + pp0_00(3) or + pp0_00(59) or + pp0_01(4) or pp0_01(61) or + pp0_02(63) or pp0_02(6) or + pp0_03(65) or pp0_03(8) or + pp0_04(10) or pp0_04(67) or + pp0_05(12) or pp0_05(69) or + pp0_06(14) or pp0_06(71) or + pp0_07(16) or pp0_07(73) or + pp1_00(60) or pp1_00(61) or + pp1_01(63) or + pp1_02(66) or pp1_02(67) or + pp1_03(69) or pp1_03(8) or + pp1_04(72) or pp1_04(73) or + pp1_05(14) or + pp2_00(62) or pp2_00(63) or + pp2_01(66) or pp2_01(67) or + pp2_02(70) or pp2_02(72) or pp2_02(73) or + pp2_03(8) or + pp3_00(68) or pp3_00(70) or pp3_00(72) or pp3_00(73) ; + + + --//################################################## + --//# Booth Decoders + --//################################################## + bd_00: entity work.fuq_mul_bthdcd(fuq_mul_bthdcd) port map ( + i0 => a_frac(17) , --i-- + i1 => a_frac(18) , --i-- + i2 => a_frac(19) , --i-- + s_neg => s_neg(0) , --o-- + s_x => s_x(0) , --o-- + s_x2 => s_x2(0)); --o-- + + bd_01: entity work.fuq_mul_bthdcd(fuq_mul_bthdcd) port map ( + i0 => a_frac(19) , --i-- + i1 => a_frac(20) , --i-- + i2 => a_frac(21) , --i-- + s_neg => s_neg(1) , --o-- + s_x => s_x(1) , --o-- + s_x2 => s_x2(1)); --o-- + + bd_02: entity work.fuq_mul_bthdcd(fuq_mul_bthdcd) port map ( + i0 => a_frac(21) , --i-- + i1 => a_frac(22) , --i-- + i2 => a_frac(23) , --i-- + s_neg => s_neg(2) , --o-- + s_x => s_x(2) , --o-- + s_x2 => s_x2(2)); --o-- + + bd_03: entity work.fuq_mul_bthdcd(fuq_mul_bthdcd) port map ( + i0 => a_frac(23) , --i-- + i1 => a_frac(24) , --i-- + i2 => a_frac(25) , --i-- + s_neg => s_neg(3) , --o-- + s_x => s_x(3) , --o-- + s_x2 => s_x2(3)); --o-- + + bd_04: entity work.fuq_mul_bthdcd(fuq_mul_bthdcd) port map ( + i0 => a_frac(25) , --i-- + i1 => a_frac(26) , --i-- + i2 => a_frac(27) , --i-- + s_neg => s_neg(4) , --o-- + s_x => s_x(4) , --o-- + s_x2 => s_x2(4)); --o-- + + bd_05: entity work.fuq_mul_bthdcd(fuq_mul_bthdcd) port map ( + i0 => a_frac(27) , --i-- + i1 => a_frac(28) , --i-- + i2 => a_frac(29) , --i-- + s_neg => s_neg(5) , --o-- + s_x => s_x(5) , --o-- + s_x2 => s_x2(5)); --o-- + + bd_06: entity work.fuq_mul_bthdcd(fuq_mul_bthdcd) port map ( + i0 => a_frac(29) , --i-- + i1 => a_frac(30) , --i-- + i2 => a_frac(31) , --i-- + s_neg => s_neg(6) , --o-- + s_x => s_x(6) , --o-- + s_x2 => s_x2(6)); --o-- + + bd_07: entity work.fuq_mul_bthdcd(fuq_mul_bthdcd) port map ( + i0 => a_frac(31) , --i-- + i1 => a_frac(32) , --i-- + i2 => a_frac(33) , --i-- + s_neg => s_neg(7) , --o-- + s_x => s_x(7) , --o-- + s_x2 => s_x2(7)); --o-- + + bd_08: entity work.fuq_mul_bthdcd(fuq_mul_bthdcd) port map ( + i0 => a_frac(33) , --i-- + i1 => a_frac(34) , --i-- + i2 => a_frac(35) , --i-- + s_neg => s_neg(8) , --o-- + s_x => s_x(8) , --o-- + s_x2 => s_x2(8)); --o-- + + + + --//################################################## + --//# Booth Mux Rows + --//################################################## + +--//# NUMBERING SYSTEM RELATIVE TO COMPRESSOR TREE +--//# +--//# 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111111111 +--//# 0000000000111111111122222222223333333333444444444455555555556666666666777777777788888888889999999999000000000 +--//# 0123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678 +--//# 0 ..DdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s.................................................. +--//# 1 ..1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s................................................ +--//# 2 ....1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s.............................................. +--//# 3 ......1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s............................................ +--//# 4 ........1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s.......................................... +--//# 5 ..........1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s........................................ +--//# 6 ............1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s...................................... +--//# 7 ..............1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s.................................... +--//# 8 ................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s.................................. +--//# 9 ..................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s................................ +--//# 10 ....................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s.............................. +--//# 11 ......................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s............................ +--//# 12 ........................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s.......................... +--//# 13 ..........................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s........................ +--//# 14 ............................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s...................... +--//# 15 ..............................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s.................... +--//# 16 ................................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s.................. +--//# 17 ..................................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s................ +--//# 18 ....................................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s.............. +--//# 19 ......................................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s............ +--//# 20 ........................................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s.......... +--//# 21 ..........................................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s........ +--//# 22 ............................................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s...... +--//# 23 ..............................................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s.... +--//# 24 ................................................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s.. +--//# 25 ..................................................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s +--//# 26 ...................................................assDdddddddddddddddddddddddddddddddddddddddddddddddddddddD + + + + pp0_00(2) <= tiup; + pp0_00(3) <= xtd_2_add(0); + + sx_00_2: xtd_2_add(0) <= not(s_neg(0) and (s_x(0) or s_x2(0)) ); + + bm_00: entity work.fuq_mul_bthrow(fuq_mul_bthrow) port map ( + s_neg => s_neg(0) , --i-- + s_x => s_x(0) , --i-- + s_x2 => s_x2(0) , --i-- + x => c_frac(0 to 53) , --i-- + q => pp0_00(4 to 58) , --o-- + hot_one => hot_one_din); --o-- + + ---------------------------------------------------------------------------- + + pp0_01(4) <= tiup; + pp0_01(5) <= xtd_2_add(1); + + sx_01_2: xtd_2_add(1) <= not(s_neg(1) and (s_x(1) or s_x2(1)) ); + + bm_01: entity work.fuq_mul_bthrow(fuq_mul_bthrow) port map ( + s_neg => s_neg(1) , --i-- + s_x => s_x(1) , --i-- + s_x2 => s_x2(1) , --i-- + x => c_frac(0 to 53) , --i-- + q => pp0_01(6 to 60) , --o-- + hot_one => pp0_00(60)); --i-- + pp0_00(59) <= tidn; + + ---------------------------------------------------------------------------- + + pp0_02(6) <= tiup; + pp0_02(7) <= xtd_2_add(2); + + sx_02_2: xtd_2_add(2) <= not(s_neg(2) and (s_x(2) or s_x2(2)) ); + + bm_02: entity work.fuq_mul_bthrow(fuq_mul_bthrow) port map ( + s_neg => s_neg(2) , --i-- + s_x => s_x(2) , --i-- + s_x2 => s_x2(2) , --i-- + x => c_frac(0 to 53) , --i-- + q => pp0_02(8 to 62) , --o-- + hot_one => pp0_01(62)); --i-- + pp0_01(61) <= tidn; + + ---------------------------------------------------------------------------- + + pp0_03(8) <= tiup; + pp0_03(9) <= xtd_2_add(3); + + sx_03_2: xtd_2_add(3) <= not(s_neg(3) and (s_x(3) or s_x2(3)) ); + + bm_03: entity work.fuq_mul_bthrow(fuq_mul_bthrow) port map ( + s_neg => s_neg(3) , --i-- + s_x => s_x(3) , --i-- + s_x2 => s_x2(3) , --i-- + x => c_frac(0 to 53) , --i-- + q => pp0_03(10 to 64) , --o-- + hot_one => pp0_02(64)); --i-- + pp0_02(63) <= tidn; + + ---------------------------------------------------------------------------- + + pp0_04(10) <= tiup; + pp0_04(11) <= xtd_2_add(4); + + sx_04_2: xtd_2_add(4) <= not(s_neg(4) and (s_x(4) or s_x2(4)) ); + + bm_04: entity work.fuq_mul_bthrow(fuq_mul_bthrow) port map ( + s_neg => s_neg(4) , --i-- + s_x => s_x(4) , --i-- + s_x2 => s_x2(4) , --i-- + x => c_frac(0 to 53) , --i-- + q => pp0_04(12 to 66) , --o-- + hot_one => pp0_03(66)); --i-- + pp0_03(65) <= tidn; + + ---------------------------------------------------------------------------- + + pp0_05(12) <= tiup; + pp0_05(13) <= xtd_2_add(5); + + sx_05_2: xtd_2_add(5) <= not(s_neg(5) and (s_x(5) or s_x2(5)) ); + + bm_05: entity work.fuq_mul_bthrow(fuq_mul_bthrow) port map ( + s_neg => s_neg(5) , --i-- + s_x => s_x(5) , --i-- + s_x2 => s_x2(5) , --i-- + x => c_frac(0 to 53) , --i-- + q => pp0_05(14 to 68) , --o-- + hot_one => pp0_04(68)); --i-- + pp0_04(67) <= tidn; + + ---------------------------------------------------------------------------- + + pp0_06(14) <= tiup; + pp0_06(15) <= xtd_2_add(6); + + sx_06_2: xtd_2_add(6) <= not(s_neg(6) and (s_x(6) or s_x2(6)) ); + + bm_06: entity work.fuq_mul_bthrow(fuq_mul_bthrow) port map ( + s_neg => s_neg(6) , --i-- + s_x => s_x(6) , --i-- + s_x2 => s_x2(6) , --i-- + x => c_frac(0 to 53) , --i-- + q => pp0_06(16 to 70) , --o-- + hot_one => pp0_05(70)); --i-- + pp0_05(69) <= tidn; + + ---------------------------------------------------------------------------- + + pp0_07(16) <= tiup; + pp0_07(17) <= xtd_2_add(7); + + sx_07_2: xtd_2_add(7) <= not(s_neg(7) and (s_x(7) or s_x2(7)) ); + + bm_07: entity work.fuq_mul_bthrow(fuq_mul_bthrow) port map ( + s_neg => s_neg(7) , --i-- + s_x => s_x(7) , --i-- + s_x2 => s_x2(7) , --i-- + x => c_frac(0 to 53) , --i-- + q => pp0_07(18 to 72) , --o-- + hot_one => pp0_06(72)); --i-- + pp0_06(71) <= tidn; + + + ---------------------------------------------------------------------------- + -- LSB ROW OF LSB 9:2 HAS unique sign extension + ---------------------------------------------------------------------------- + + -- to get a "1" ctl_s=1 ctl_a=1 + -- to get a "0" ctl_s=0 ctl_a=0 + -- to get a "A" ctl_s=0 ctl_a=1 + -- to get a "S" ctl_s=1 ctl_a=0 + + +--/####################################################################### +--/# this is the unique part for the 3 version of fuq_mul_92 +--/# MSB/LSB sx_08_0 sx_08_1 sx_08_2 +--/# mul_92_0 10 '0' '1' Add +--/# mul_92_1 00 '0' '1' Add +--/# mul_92_2 01 Add Sub Sub +--/####################################################################### + + + g0: if (inst = 0) generate + begin + pp0_08(17) <= tidn ; -- inst.0 + pp0_08(18) <= tiup ; -- inst.0 + sx_08_2: pp0_08(19) <= not( s_neg(8) and ( s_x(8) or s_x2(8)) ); -- inst.0 + end generate ; + + g1: if (inst = 1) generate + begin + pp0_08(17) <= tidn ; -- inst.0 + pp0_08(18) <= tiup ; -- inst.0 + sx_08_2: pp0_08(19) <= not( s_neg(8) and ( s_x(8) or s_x2(8)) ); -- inst.0 + end generate ; + + + g2: if (inst = 2) generate + begin + sx_08_0: pp0_08(17) <= not( s_neg(8) and ( s_x(8) or s_x2(8)) ); -- inst.2 + sx_08_1: pp0_08(18) <= ( s_neg(8) and ( s_x(8) or s_x2(8)) ); -- inst.2 + sx_08_2: pp0_08(19) <= ( s_neg(8) and ( s_x(8) or s_x2(8)) ); -- inst.2 + end generate ; + + + + bm_08: entity work.fuq_mul_bthrow(fuq_mul_bthrow) port map ( + s_neg => s_neg(8) , --i-- + s_x => s_x(8) , --i-- + s_x2 => s_x2(8) , --i-- + x => c_frac(0 to 53) , --i-- + q => pp0_08(20 to 74) , --o-- + hot_one => pp0_07(74)); --i-- + pp0_07(73) <= tidn; + + + --//################################################## + --//# Compressor Level 1 + --//################################################## + +--//########################################################### +--//# LEON CHART +--//########################################################### +-- o: no logic done on the signal +-- c: carry +-- u: sum +-- h: hot1 +-- H: hot 1 latched +-- s: sign +-- a: ! sign +-- d: data from the booth muxes +-- wWW: 01a / ass +-- Kz: 1a / 00 + + +--//# 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111111111 +--//# 0000000000111111111122222222223333333333444444444455555555556666666666777777777788888888889999999999000000000 +--//# 0123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678 +--//# 0 ..zzddddddddddddddddddddddddddddddddddddddddddddddddddddddd0h................................................ +--//# 1 ....1addddddddddddddddddddddddddddddddddddddddddddddddddddddd0h.............................................. +--//# 2 ......1addddddddddddddddddddddddddddddddddddddddddddddddddddddd0h............................................ +--//# 3 ........1addddddddddddddddddddddddddddddddddddddddddddddddddddddd0h.......................................... +--//# 4 ..........1addddddddddddddddddddddddddddddddddddddddddddddddddddddd0h........................................ +--//# 5 ............1addddddddddddddddddddddddddddddddddddddddddddddddddddddd0h...................................... +--//# 6 ..............1addddddddddddddddddddddddddddddddddddddddddddddddddddddd0h.................................... +--//# 7 ................1addddddddddddddddddddddddddddddddddddddddddddddddddddddd0h.................................. +--//# 8 .................wWWddddddddddddddddddddddddddddddddddddddddddddddddddddddd0h................................ + + + +--//# 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111111111 +--//# 0000000000111111111122222222223333333333444444444455555555556666666666777777777788888888889999999999000000000 +--//# 0123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678 +--//# 8 .................wWWddddddddddddddddddddddddddddddddddddddddddddddddddddddd.................................. pp0_08 +--//# 7 ................1addddddddddddddddddddddddddddddddddddddddddddddddddddddd0h.................................. pp0_07 +--//# 6 ..............1addddddddddddddddddddddddddddddddddddddddddddddddddddddd0h.................................... pp0_06 +--//# ------------------------------------------------------------------------------------- +--//# ................233333333333333333333333333333333333333333333333333333323.... +--//# ...............ouuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuoo................................. pp1_05 +--//# ..............occccccccccccccccccccccccccccccccccccccccccccccccccccccccc__o................................. pp1_04 + + + + pp1_05(74) <= pp0_08(74); + pp1_05(73) <= pp0_08(73); + + pp1_04(74) <= pp0_07(74); + pp1_04(73) <= tidn; + pp1_04(72) <= tidn; + + pp1_02_csa_72: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(72) , --i-- + b => pp0_07(72) , --i-- + c => pp0_06(72) , --i-- + sum => pp1_05(72) , --o-- + car => pp1_04(71)); --o-- + pp1_02_csa_71: entity work.fuq_csa22_h2(fuq_csa22_h2) port map ( + a => pp0_08(71) , --i-- + b => pp0_07(71) , --i-- + sum => pp1_05(71) , --o-- + car => pp1_04(70)); --o-- + pp1_02_csa_70: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(70) , --i-- + b => pp0_07(70) , --i-- + c => pp0_06(70) , --i-- + sum => pp1_05(70) , --o-- + car => pp1_04(69)); --o-- + pp1_02_csa_69: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(69) , --i-- + b => pp0_07(69) , --i-- + c => pp0_06(69) , --i-- + sum => pp1_05(69) , --o-- + car => pp1_04(68)); --o-- + pp1_02_csa_68: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(68) , --i-- + b => pp0_07(68) , --i-- + c => pp0_06(68) , --i-- + sum => pp1_05(68) , --o-- + car => pp1_04(67)); --o-- + pp1_02_csa_67: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(67) , --i-- + b => pp0_07(67) , --i-- + c => pp0_06(67) , --i-- + sum => pp1_05(67) , --o-- + car => pp1_04(66)); --o-- + pp1_02_csa_66: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(66) , --i-- + b => pp0_07(66) , --i-- + c => pp0_06(66) , --i-- + sum => pp1_05(66) , --o-- + car => pp1_04(65)); --o-- + pp1_02_csa_65: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(65) , --i-- + b => pp0_07(65) , --i-- + c => pp0_06(65) , --i-- + sum => pp1_05(65) , --o-- + car => pp1_04(64)); --o-- + pp1_02_csa_64: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(64) , --i-- + b => pp0_07(64) , --i-- + c => pp0_06(64) , --i-- + sum => pp1_05(64) , --o-- + car => pp1_04(63)); --o-- + pp1_02_csa_63: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(63) , --i-- + b => pp0_07(63) , --i-- + c => pp0_06(63) , --i-- + sum => pp1_05(63) , --o-- + car => pp1_04(62)); --o-- + pp1_02_csa_62: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(62) , --i-- + b => pp0_07(62) , --i-- + c => pp0_06(62) , --i-- + sum => pp1_05(62) , --o-- + car => pp1_04(61)); --o-- + pp1_02_csa_61: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(61) , --i-- + b => pp0_07(61) , --i-- + c => pp0_06(61) , --i-- + sum => pp1_05(61) , --o-- + car => pp1_04(60)); --o-- + pp1_02_csa_60: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(60) , --i-- + b => pp0_07(60) , --i-- + c => pp0_06(60) , --i-- + sum => pp1_05(60) , --o-- + car => pp1_04(59)); --o-- + pp1_02_csa_59: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(59) , --i-- + b => pp0_07(59) , --i-- + c => pp0_06(59) , --i-- + sum => pp1_05(59) , --o-- + car => pp1_04(58)); --o-- + pp1_02_csa_58: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(58) , --i-- + b => pp0_07(58) , --i-- + c => pp0_06(58) , --i-- + sum => pp1_05(58) , --o-- + car => pp1_04(57)); --o-- + pp1_02_csa_57: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(57) , --i-- + b => pp0_07(57) , --i-- + c => pp0_06(57) , --i-- + sum => pp1_05(57) , --o-- + car => pp1_04(56)); --o-- + pp1_02_csa_56: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(56) , --i-- + b => pp0_07(56) , --i-- + c => pp0_06(56) , --i-- + sum => pp1_05(56) , --o-- + car => pp1_04(55)); --o-- + pp1_02_csa_55: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(55) , --i-- + b => pp0_07(55) , --i-- + c => pp0_06(55) , --i-- + sum => pp1_05(55) , --o-- + car => pp1_04(54)); --o-- + pp1_02_csa_54: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(54) , --i-- + b => pp0_07(54) , --i-- + c => pp0_06(54) , --i-- + sum => pp1_05(54) , --o-- + car => pp1_04(53)); --o-- + pp1_02_csa_53: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(53) , --i-- + b => pp0_07(53) , --i-- + c => pp0_06(53) , --i-- + sum => pp1_05(53) , --o-- + car => pp1_04(52)); --o-- + pp1_02_csa_52: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(52) , --i-- + b => pp0_07(52) , --i-- + c => pp0_06(52) , --i-- + sum => pp1_05(52) , --o-- + car => pp1_04(51)); --o-- + pp1_02_csa_51: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(51) , --i-- + b => pp0_07(51) , --i-- + c => pp0_06(51) , --i-- + sum => pp1_05(51) , --o-- + car => pp1_04(50)); --o-- + pp1_02_csa_50: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(50) , --i-- + b => pp0_07(50) , --i-- + c => pp0_06(50) , --i-- + sum => pp1_05(50) , --o-- + car => pp1_04(49)); --o-- + pp1_02_csa_49: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(49) , --i-- + b => pp0_07(49) , --i-- + c => pp0_06(49) , --i-- + sum => pp1_05(49) , --o-- + car => pp1_04(48)); --o-- + pp1_02_csa_48: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(48) , --i-- + b => pp0_07(48) , --i-- + c => pp0_06(48) , --i-- + sum => pp1_05(48) , --o-- + car => pp1_04(47)); --o-- + pp1_02_csa_47: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(47) , --i-- + b => pp0_07(47) , --i-- + c => pp0_06(47) , --i-- + sum => pp1_05(47) , --o-- + car => pp1_04(46)); --o-- + pp1_02_csa_46: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(46) , --i-- + b => pp0_07(46) , --i-- + c => pp0_06(46) , --i-- + sum => pp1_05(46) , --o-- + car => pp1_04(45)); --o-- + pp1_02_csa_45: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(45) , --i-- + b => pp0_07(45) , --i-- + c => pp0_06(45) , --i-- + sum => pp1_05(45) , --o-- + car => pp1_04(44)); --o-- + pp1_02_csa_44: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(44) , --i-- + b => pp0_07(44) , --i-- + c => pp0_06(44) , --i-- + sum => pp1_05(44) , --o-- + car => pp1_04(43)); --o-- + pp1_02_csa_43: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(43) , --i-- + b => pp0_07(43) , --i-- + c => pp0_06(43) , --i-- + sum => pp1_05(43) , --o-- + car => pp1_04(42)); --o-- + pp1_02_csa_42: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(42) , --i-- + b => pp0_07(42) , --i-- + c => pp0_06(42) , --i-- + sum => pp1_05(42) , --o-- + car => pp1_04(41)); --o-- + pp1_02_csa_41: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(41) , --i-- + b => pp0_07(41) , --i-- + c => pp0_06(41) , --i-- + sum => pp1_05(41) , --o-- + car => pp1_04(40)); --o-- + pp1_02_csa_40: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(40) , --i-- + b => pp0_07(40) , --i-- + c => pp0_06(40) , --i-- + sum => pp1_05(40) , --o-- + car => pp1_04(39)); --o-- + pp1_02_csa_39: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(39) , --i-- + b => pp0_07(39) , --i-- + c => pp0_06(39) , --i-- + sum => pp1_05(39) , --o-- + car => pp1_04(38)); --o-- + pp1_02_csa_38: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(38) , --i-- + b => pp0_07(38) , --i-- + c => pp0_06(38) , --i-- + sum => pp1_05(38) , --o-- + car => pp1_04(37)); --o-- + pp1_02_csa_37: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(37) , --i-- + b => pp0_07(37) , --i-- + c => pp0_06(37) , --i-- + sum => pp1_05(37) , --o-- + car => pp1_04(36)); --o-- + pp1_02_csa_36: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(36) , --i-- + b => pp0_07(36) , --i-- + c => pp0_06(36) , --i-- + sum => pp1_05(36) , --o-- + car => pp1_04(35)); --o-- + pp1_02_csa_35: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(35) , --i-- + b => pp0_07(35) , --i-- + c => pp0_06(35) , --i-- + sum => pp1_05(35) , --o-- + car => pp1_04(34)); --o-- + pp1_02_csa_34: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(34) , --i-- + b => pp0_07(34) , --i-- + c => pp0_06(34) , --i-- + sum => pp1_05(34) , --o-- + car => pp1_04(33)); --o-- + pp1_02_csa_33: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(33) , --i-- + b => pp0_07(33) , --i-- + c => pp0_06(33) , --i-- + sum => pp1_05(33) , --o-- + car => pp1_04(32)); --o-- + pp1_02_csa_32: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(32) , --i-- + b => pp0_07(32) , --i-- + c => pp0_06(32) , --i-- + sum => pp1_05(32) , --o-- + car => pp1_04(31)); --o-- + pp1_02_csa_31: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(31) , --i-- + b => pp0_07(31) , --i-- + c => pp0_06(31) , --i-- + sum => pp1_05(31) , --o-- + car => pp1_04(30)); --o-- + pp1_02_csa_30: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(30) , --i-- + b => pp0_07(30) , --i-- + c => pp0_06(30) , --i-- + sum => pp1_05(30) , --o-- + car => pp1_04(29)); --o-- + pp1_02_csa_29: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(29) , --i-- + b => pp0_07(29) , --i-- + c => pp0_06(29) , --i-- + sum => pp1_05(29) , --o-- + car => pp1_04(28)); --o-- + pp1_02_csa_28: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(28) , --i-- + b => pp0_07(28) , --i-- + c => pp0_06(28) , --i-- + sum => pp1_05(28) , --o-- + car => pp1_04(27)); --o-- + pp1_02_csa_27: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(27) , --i-- + b => pp0_07(27) , --i-- + c => pp0_06(27) , --i-- + sum => pp1_05(27) , --o-- + car => pp1_04(26)); --o-- + pp1_02_csa_26: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(26) , --i-- + b => pp0_07(26) , --i-- + c => pp0_06(26) , --i-- + sum => pp1_05(26) , --o-- + car => pp1_04(25)); --o-- + pp1_02_csa_25: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(25) , --i-- + b => pp0_07(25) , --i-- + c => pp0_06(25) , --i-- + sum => pp1_05(25) , --o-- + car => pp1_04(24)); --o-- + pp1_02_csa_24: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(24) , --i-- + b => pp0_07(24) , --i-- + c => pp0_06(24) , --i-- + sum => pp1_05(24) , --o-- + car => pp1_04(23)); --o-- + pp1_02_csa_23: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(23) , --i-- + b => pp0_07(23) , --i-- + c => pp0_06(23) , --i-- + sum => pp1_05(23) , --o-- + car => pp1_04(22)); --o-- + pp1_02_csa_22: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(22) , --i-- + b => pp0_07(22) , --i-- + c => pp0_06(22) , --i-- + sum => pp1_05(22) , --o-- + car => pp1_04(21)); --o-- + pp1_02_csa_21: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(21) , --i-- + b => pp0_07(21) , --i-- + c => pp0_06(21) , --i-- + sum => pp1_05(21) , --o-- + car => pp1_04(20)); --o-- + pp1_02_csa_20: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(20) , --i-- + b => pp0_07(20) , --i-- + c => pp0_06(20) , --i-- + sum => pp1_05(20) , --o-- + car => pp1_04(19)); --o-- + pp1_02_csa_19: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(19) , --i-- + b => pp0_07(19) , --i-- + c => pp0_06(19) , --i-- + sum => pp1_05(19) , --o-- + car => pp1_04(18)); --o-- + pp1_02_csa_18: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(18) , --i-- + b => pp0_07(18) , --i-- + c => pp0_06(18) , --i-- + sum => pp1_05(18) , --o-- + car => pp1_04(17)); --o-- + pp1_02_csa_17: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_08(17) , --i-- + b => pp0_07(17) , --i-- + c => pp0_06(17) , --i-- + sum => pp1_05(17) , --o-- + car => pp1_04(16)); --o-- + pp1_02_csa_16: entity work.fuq_csa22_h2(fuq_csa22_h2) port map ( + a => tiup , --i-- + b => pp0_06(16) , --i-- + sum => pp1_05(16) , --o-- + car => pp1_04(15)); --o-- + pp1_05(15) <= pp0_06(15); + pp1_05(14) <= tiup; + +--//# 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111111111 +--//# 0000000000111111111122222222223333333333444444444455555555556666666666777777777788888888889999999999000000000 +--//# 0123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678 +--//# 5 ............1addddddddddddddddddddddddddddddddddddddddddddddddddddddd0h...................................... pp0_05 +--//# 4 ..........1addddddddddddddddddddddddddddddddddddddddddddddddddddddd0h........................................ pp0_04 +--//# 3 ........1addddddddddddddddddddddddddddddddddddddddddddddddddddddd0h.......................................... pp0_03 +--//# ------------------------------------------------------------------------------------- +--//# ..........223333333333333333333333333333333333333333333333333333323.... +--//# .........ouuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuoo_o..................................... pp1_03 +--//# ........occccccccccccccccccccccccccccccccccccccccccccccccccccccccc__o....................................... pp1_02 + + pp1_03(70) <= pp0_05(70); + pp1_03(69) <= tidn; + pp1_03(68) <= pp0_05(68); + pp1_03(67) <= pp0_05(67); + + pp1_02(68) <= pp0_04(68); + pp1_02(67) <= tidn; + pp1_02(66) <= tidn; + + pp1_01_csa_66: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(66) , --i-- + b => pp0_04(66) , --i-- + c => pp0_03(66) , --i-- + sum => pp1_03(66) , --o-- + car => pp1_02(65)); --o-- + pp1_01_csa_65: entity work.fuq_csa22_h2(fuq_csa22_h2) port map ( + a => pp0_05(65) , --i-- + b => pp0_04(65) , --i-- + sum => pp1_03(65) , --o-- + car => pp1_02(64)); --o-- + pp1_01_csa_64: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(64) , --i-- + b => pp0_04(64) , --i-- + c => pp0_03(64) , --i-- + sum => pp1_03(64) , --o-- + car => pp1_02(63)); --o-- + pp1_01_csa_63: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(63) , --i-- + b => pp0_04(63) , --i-- + c => pp0_03(63) , --i-- + sum => pp1_03(63) , --o-- + car => pp1_02(62)); --o-- + pp1_01_csa_62: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(62) , --i-- + b => pp0_04(62) , --i-- + c => pp0_03(62) , --i-- + sum => pp1_03(62) , --o-- + car => pp1_02(61)); --o-- + pp1_01_csa_61: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(61) , --i-- + b => pp0_04(61) , --i-- + c => pp0_03(61) , --i-- + sum => pp1_03(61) , --o-- + car => pp1_02(60)); --o-- + pp1_01_csa_60: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(60) , --i-- + b => pp0_04(60) , --i-- + c => pp0_03(60) , --i-- + sum => pp1_03(60) , --o-- + car => pp1_02(59)); --o-- + pp1_01_csa_59: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(59) , --i-- + b => pp0_04(59) , --i-- + c => pp0_03(59) , --i-- + sum => pp1_03(59) , --o-- + car => pp1_02(58)); --o-- + pp1_01_csa_58: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(58) , --i-- + b => pp0_04(58) , --i-- + c => pp0_03(58) , --i-- + sum => pp1_03(58) , --o-- + car => pp1_02(57)); --o-- + pp1_01_csa_57: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(57) , --i-- + b => pp0_04(57) , --i-- + c => pp0_03(57) , --i-- + sum => pp1_03(57) , --o-- + car => pp1_02(56)); --o-- + pp1_01_csa_56: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(56) , --i-- + b => pp0_04(56) , --i-- + c => pp0_03(56) , --i-- + sum => pp1_03(56) , --o-- + car => pp1_02(55)); --o-- + pp1_01_csa_55: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(55) , --i-- + b => pp0_04(55) , --i-- + c => pp0_03(55) , --i-- + sum => pp1_03(55) , --o-- + car => pp1_02(54)); --o-- + pp1_01_csa_54: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(54) , --i-- + b => pp0_04(54) , --i-- + c => pp0_03(54) , --i-- + sum => pp1_03(54) , --o-- + car => pp1_02(53)); --o-- + pp1_01_csa_53: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(53) , --i-- + b => pp0_04(53) , --i-- + c => pp0_03(53) , --i-- + sum => pp1_03(53) , --o-- + car => pp1_02(52)); --o-- + pp1_01_csa_52: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(52) , --i-- + b => pp0_04(52) , --i-- + c => pp0_03(52) , --i-- + sum => pp1_03(52) , --o-- + car => pp1_02(51)); --o-- + pp1_01_csa_51: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(51) , --i-- + b => pp0_04(51) , --i-- + c => pp0_03(51) , --i-- + sum => pp1_03(51) , --o-- + car => pp1_02(50)); --o-- + pp1_01_csa_50: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(50) , --i-- + b => pp0_04(50) , --i-- + c => pp0_03(50) , --i-- + sum => pp1_03(50) , --o-- + car => pp1_02(49)); --o-- + pp1_01_csa_49: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(49) , --i-- + b => pp0_04(49) , --i-- + c => pp0_03(49) , --i-- + sum => pp1_03(49) , --o-- + car => pp1_02(48)); --o-- + pp1_01_csa_48: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(48) , --i-- + b => pp0_04(48) , --i-- + c => pp0_03(48) , --i-- + sum => pp1_03(48) , --o-- + car => pp1_02(47)); --o-- + pp1_01_csa_47: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(47) , --i-- + b => pp0_04(47) , --i-- + c => pp0_03(47) , --i-- + sum => pp1_03(47) , --o-- + car => pp1_02(46)); --o-- + pp1_01_csa_46: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(46) , --i-- + b => pp0_04(46) , --i-- + c => pp0_03(46) , --i-- + sum => pp1_03(46) , --o-- + car => pp1_02(45)); --o-- + pp1_01_csa_45: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(45) , --i-- + b => pp0_04(45) , --i-- + c => pp0_03(45) , --i-- + sum => pp1_03(45) , --o-- + car => pp1_02(44)); --o-- + pp1_01_csa_44: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(44) , --i-- + b => pp0_04(44) , --i-- + c => pp0_03(44) , --i-- + sum => pp1_03(44) , --o-- + car => pp1_02(43)); --o-- + pp1_01_csa_43: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(43) , --i-- + b => pp0_04(43) , --i-- + c => pp0_03(43) , --i-- + sum => pp1_03(43) , --o-- + car => pp1_02(42)); --o-- + pp1_01_csa_42: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(42) , --i-- + b => pp0_04(42) , --i-- + c => pp0_03(42) , --i-- + sum => pp1_03(42) , --o-- + car => pp1_02(41)); --o-- + pp1_01_csa_41: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(41) , --i-- + b => pp0_04(41) , --i-- + c => pp0_03(41) , --i-- + sum => pp1_03(41) , --o-- + car => pp1_02(40)); --o-- + pp1_01_csa_40: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(40) , --i-- + b => pp0_04(40) , --i-- + c => pp0_03(40) , --i-- + sum => pp1_03(40) , --o-- + car => pp1_02(39)); --o-- + pp1_01_csa_39: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(39) , --i-- + b => pp0_04(39) , --i-- + c => pp0_03(39) , --i-- + sum => pp1_03(39) , --o-- + car => pp1_02(38)); --o-- + pp1_01_csa_38: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(38) , --i-- + b => pp0_04(38) , --i-- + c => pp0_03(38) , --i-- + sum => pp1_03(38) , --o-- + car => pp1_02(37)); --o-- + pp1_01_csa_37: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(37) , --i-- + b => pp0_04(37) , --i-- + c => pp0_03(37) , --i-- + sum => pp1_03(37) , --o-- + car => pp1_02(36)); --o-- + pp1_01_csa_36: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(36) , --i-- + b => pp0_04(36) , --i-- + c => pp0_03(36) , --i-- + sum => pp1_03(36) , --o-- + car => pp1_02(35)); --o-- + pp1_01_csa_35: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(35) , --i-- + b => pp0_04(35) , --i-- + c => pp0_03(35) , --i-- + sum => pp1_03(35) , --o-- + car => pp1_02(34)); --o-- + pp1_01_csa_34: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(34) , --i-- + b => pp0_04(34) , --i-- + c => pp0_03(34) , --i-- + sum => pp1_03(34) , --o-- + car => pp1_02(33)); --o-- + pp1_01_csa_33: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(33) , --i-- + b => pp0_04(33) , --i-- + c => pp0_03(33) , --i-- + sum => pp1_03(33) , --o-- + car => pp1_02(32)); --o-- + pp1_01_csa_32: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(32) , --i-- + b => pp0_04(32) , --i-- + c => pp0_03(32) , --i-- + sum => pp1_03(32) , --o-- + car => pp1_02(31)); --o-- + pp1_01_csa_31: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(31) , --i-- + b => pp0_04(31) , --i-- + c => pp0_03(31) , --i-- + sum => pp1_03(31) , --o-- + car => pp1_02(30)); --o-- + pp1_01_csa_30: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(30) , --i-- + b => pp0_04(30) , --i-- + c => pp0_03(30) , --i-- + sum => pp1_03(30) , --o-- + car => pp1_02(29)); --o-- + pp1_01_csa_29: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(29) , --i-- + b => pp0_04(29) , --i-- + c => pp0_03(29) , --i-- + sum => pp1_03(29) , --o-- + car => pp1_02(28)); --o-- + pp1_01_csa_28: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(28) , --i-- + b => pp0_04(28) , --i-- + c => pp0_03(28) , --i-- + sum => pp1_03(28) , --o-- + car => pp1_02(27)); --o-- + pp1_01_csa_27: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(27) , --i-- + b => pp0_04(27) , --i-- + c => pp0_03(27) , --i-- + sum => pp1_03(27) , --o-- + car => pp1_02(26)); --o-- + pp1_01_csa_26: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(26) , --i-- + b => pp0_04(26) , --i-- + c => pp0_03(26) , --i-- + sum => pp1_03(26) , --o-- + car => pp1_02(25)); --o-- + pp1_01_csa_25: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(25) , --i-- + b => pp0_04(25) , --i-- + c => pp0_03(25) , --i-- + sum => pp1_03(25) , --o-- + car => pp1_02(24)); --o-- + pp1_01_csa_24: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(24) , --i-- + b => pp0_04(24) , --i-- + c => pp0_03(24) , --i-- + sum => pp1_03(24) , --o-- + car => pp1_02(23)); --o-- + pp1_01_csa_23: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(23) , --i-- + b => pp0_04(23) , --i-- + c => pp0_03(23) , --i-- + sum => pp1_03(23) , --o-- + car => pp1_02(22)); --o-- + pp1_01_csa_22: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(22) , --i-- + b => pp0_04(22) , --i-- + c => pp0_03(22) , --i-- + sum => pp1_03(22) , --o-- + car => pp1_02(21)); --o-- + pp1_01_csa_21: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(21) , --i-- + b => pp0_04(21) , --i-- + c => pp0_03(21) , --i-- + sum => pp1_03(21) , --o-- + car => pp1_02(20)); --o-- + pp1_01_csa_20: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(20) , --i-- + b => pp0_04(20) , --i-- + c => pp0_03(20) , --i-- + sum => pp1_03(20) , --o-- + car => pp1_02(19)); --o-- + pp1_01_csa_19: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(19) , --i-- + b => pp0_04(19) , --i-- + c => pp0_03(19) , --i-- + sum => pp1_03(19) , --o-- + car => pp1_02(18)); --o-- + pp1_01_csa_18: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(18) , --i-- + b => pp0_04(18) , --i-- + c => pp0_03(18) , --i-- + sum => pp1_03(18) , --o-- + car => pp1_02(17)); --o-- + pp1_01_csa_17: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(17) , --i-- + b => pp0_04(17) , --i-- + c => pp0_03(17) , --i-- + sum => pp1_03(17) , --o-- + car => pp1_02(16)); --o-- + pp1_01_csa_16: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(16) , --i-- + b => pp0_04(16) , --i-- + c => pp0_03(16) , --i-- + sum => pp1_03(16) , --o-- + car => pp1_02(15)); --o-- + pp1_01_csa_15: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(15) , --i-- + b => pp0_04(15) , --i-- + c => pp0_03(15) , --i-- + sum => pp1_03(15) , --o-- + car => pp1_02(14)); --o-- + pp1_01_csa_14: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(14) , --i-- + b => pp0_04(14) , --i-- + c => pp0_03(14) , --i-- + sum => pp1_03(14) , --o-- + car => pp1_02(13)); --o-- + pp1_01_csa_13: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_05(13) , --i-- + b => pp0_04(13) , --i-- + c => pp0_03(13) , --i-- + sum => pp1_03(13) , --o-- + car => pp1_02(12)); --o-- + pp1_01_csa_12: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => tiup , --i-- + b => pp0_04(12) , --i-- + c => pp0_03(12) , --i-- + sum => pp1_03(12) , --o-- + car => pp1_02(11)); --o-- + pp1_01_csa_11: entity work.fuq_csa22_h2(fuq_csa22_h2) port map ( + a => pp0_04(11) , --i-- + b => pp0_03(11) , --i-- + sum => pp1_03(11) , --o-- + car => pp1_02(10)); --o-- + pp1_01_csa_10: entity work.fuq_csa22_h2(fuq_csa22_h2) port map ( + a => tiup , --i-- + b => pp0_03(10) , --i-- + sum => pp1_03(10) , --o-- + car => pp1_02(9)); --o-- + pp1_03(9) <= pp0_03(9); + pp1_03(8) <= tiup; + + + +--//# 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111111111 +--//# 0000000000111111111122222222223333333333444444444455555555556666666666777777777788888888889999999999000000000 +--//# 0123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678 +--//# 2 ......1addddddddddddddddddddddddddddddddddddddddddddddddddddddd0h............................................ pp0_02 +--//# 1 ....1addddddddddddddddddddddddddddddddddddddddddddddddddddddd0h.............................................. pp0_01 +--//# 0 ..zzddddddddddddddddddddddddddddddddddddddddddddddddddddddd0h................................................ pp0_00 +--//# ------------------------------------------------------------------------------------- +--//# ....223333333333333333333333333333333333333333333333333333323.... +--//# ...ouuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuoo_o............................................ pp1_01 +--//# ..occccccccccccccccccccccccccccccccccccccccccccccccccccccccc__o.............................................. pp1_00 + + pp1_01(64) <= pp0_02(64); + pp1_01(63) <= tidn; + pp1_01(62) <= pp0_02(62); + pp1_01(61) <= pp0_02(61); + + pp1_00(62) <= pp0_01(62); + pp1_00(61) <= tidn; + pp1_00(60) <= tidn; + + pp1_00_csa_60: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(60) , --i-- + b => pp0_01(60) , --i-- + c => pp0_00(60) , --i-- + sum => pp1_01(60) , --o-- + car => pp1_00(59)); --o-- + pp1_00_csa_59: entity work.fuq_csa22_h2(fuq_csa22_h2) port map ( + a => pp0_02(59) , --i-- + b => pp0_01(59) , --i-- + sum => pp1_01(59) , --o-- + car => pp1_00(58)); --o-- + pp1_00_csa_58: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(58) , --i-- + b => pp0_01(58) , --i-- + c => pp0_00(58) , --i-- + sum => pp1_01(58) , --o-- + car => pp1_00(57)); --o-- + pp1_00_csa_57: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(57) , --i-- + b => pp0_01(57) , --i-- + c => pp0_00(57) , --i-- + sum => pp1_01(57) , --o-- + car => pp1_00(56)); --o-- + pp1_00_csa_56: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(56) , --i-- + b => pp0_01(56) , --i-- + c => pp0_00(56) , --i-- + sum => pp1_01(56) , --o-- + car => pp1_00(55)); --o-- + pp1_00_csa_55: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(55) , --i-- + b => pp0_01(55) , --i-- + c => pp0_00(55) , --i-- + sum => pp1_01(55) , --o-- + car => pp1_00(54)); --o-- + pp1_00_csa_54: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(54) , --i-- + b => pp0_01(54) , --i-- + c => pp0_00(54) , --i-- + sum => pp1_01(54) , --o-- + car => pp1_00(53)); --o-- + pp1_00_csa_53: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(53) , --i-- + b => pp0_01(53) , --i-- + c => pp0_00(53) , --i-- + sum => pp1_01(53) , --o-- + car => pp1_00(52)); --o-- + pp1_00_csa_52: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(52) , --i-- + b => pp0_01(52) , --i-- + c => pp0_00(52) , --i-- + sum => pp1_01(52) , --o-- + car => pp1_00(51)); --o-- + pp1_00_csa_51: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(51) , --i-- + b => pp0_01(51) , --i-- + c => pp0_00(51) , --i-- + sum => pp1_01(51) , --o-- + car => pp1_00(50)); --o-- + pp1_00_csa_50: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(50) , --i-- + b => pp0_01(50) , --i-- + c => pp0_00(50) , --i-- + sum => pp1_01(50) , --o-- + car => pp1_00(49)); --o-- + pp1_00_csa_49: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(49) , --i-- + b => pp0_01(49) , --i-- + c => pp0_00(49) , --i-- + sum => pp1_01(49) , --o-- + car => pp1_00(48)); --o-- + pp1_00_csa_48: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(48) , --i-- + b => pp0_01(48) , --i-- + c => pp0_00(48) , --i-- + sum => pp1_01(48) , --o-- + car => pp1_00(47)); --o-- + pp1_00_csa_47: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(47) , --i-- + b => pp0_01(47) , --i-- + c => pp0_00(47) , --i-- + sum => pp1_01(47) , --o-- + car => pp1_00(46)); --o-- + pp1_00_csa_46: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(46) , --i-- + b => pp0_01(46) , --i-- + c => pp0_00(46) , --i-- + sum => pp1_01(46) , --o-- + car => pp1_00(45)); --o-- + pp1_00_csa_45: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(45) , --i-- + b => pp0_01(45) , --i-- + c => pp0_00(45) , --i-- + sum => pp1_01(45) , --o-- + car => pp1_00(44)); --o-- + pp1_00_csa_44: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(44) , --i-- + b => pp0_01(44) , --i-- + c => pp0_00(44) , --i-- + sum => pp1_01(44) , --o-- + car => pp1_00(43)); --o-- + pp1_00_csa_43: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(43) , --i-- + b => pp0_01(43) , --i-- + c => pp0_00(43) , --i-- + sum => pp1_01(43) , --o-- + car => pp1_00(42)); --o-- + pp1_00_csa_42: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(42) , --i-- + b => pp0_01(42) , --i-- + c => pp0_00(42) , --i-- + sum => pp1_01(42) , --o-- + car => pp1_00(41)); --o-- + pp1_00_csa_41: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(41) , --i-- + b => pp0_01(41) , --i-- + c => pp0_00(41) , --i-- + sum => pp1_01(41) , --o-- + car => pp1_00(40)); --o-- + pp1_00_csa_40: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(40) , --i-- + b => pp0_01(40) , --i-- + c => pp0_00(40) , --i-- + sum => pp1_01(40) , --o-- + car => pp1_00(39)); --o-- + pp1_00_csa_39: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(39) , --i-- + b => pp0_01(39) , --i-- + c => pp0_00(39) , --i-- + sum => pp1_01(39) , --o-- + car => pp1_00(38)); --o-- + pp1_00_csa_38: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(38) , --i-- + b => pp0_01(38) , --i-- + c => pp0_00(38) , --i-- + sum => pp1_01(38) , --o-- + car => pp1_00(37)); --o-- + pp1_00_csa_37: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(37) , --i-- + b => pp0_01(37) , --i-- + c => pp0_00(37) , --i-- + sum => pp1_01(37) , --o-- + car => pp1_00(36)); --o-- + pp1_00_csa_36: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(36) , --i-- + b => pp0_01(36) , --i-- + c => pp0_00(36) , --i-- + sum => pp1_01(36) , --o-- + car => pp1_00(35)); --o-- + pp1_00_csa_35: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(35) , --i-- + b => pp0_01(35) , --i-- + c => pp0_00(35) , --i-- + sum => pp1_01(35) , --o-- + car => pp1_00(34)); --o-- + pp1_00_csa_34: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(34) , --i-- + b => pp0_01(34) , --i-- + c => pp0_00(34) , --i-- + sum => pp1_01(34) , --o-- + car => pp1_00(33)); --o-- + pp1_00_csa_33: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(33) , --i-- + b => pp0_01(33) , --i-- + c => pp0_00(33) , --i-- + sum => pp1_01(33) , --o-- + car => pp1_00(32)); --o-- + pp1_00_csa_32: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(32) , --i-- + b => pp0_01(32) , --i-- + c => pp0_00(32) , --i-- + sum => pp1_01(32) , --o-- + car => pp1_00(31)); --o-- + pp1_00_csa_31: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(31) , --i-- + b => pp0_01(31) , --i-- + c => pp0_00(31) , --i-- + sum => pp1_01(31) , --o-- + car => pp1_00(30)); --o-- + pp1_00_csa_30: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(30) , --i-- + b => pp0_01(30) , --i-- + c => pp0_00(30) , --i-- + sum => pp1_01(30) , --o-- + car => pp1_00(29)); --o-- + pp1_00_csa_29: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(29) , --i-- + b => pp0_01(29) , --i-- + c => pp0_00(29) , --i-- + sum => pp1_01(29) , --o-- + car => pp1_00(28)); --o-- + pp1_00_csa_28: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(28) , --i-- + b => pp0_01(28) , --i-- + c => pp0_00(28) , --i-- + sum => pp1_01(28) , --o-- + car => pp1_00(27)); --o-- + pp1_00_csa_27: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(27) , --i-- + b => pp0_01(27) , --i-- + c => pp0_00(27) , --i-- + sum => pp1_01(27) , --o-- + car => pp1_00(26)); --o-- + pp1_00_csa_26: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(26) , --i-- + b => pp0_01(26) , --i-- + c => pp0_00(26) , --i-- + sum => pp1_01(26) , --o-- + car => pp1_00(25)); --o-- + pp1_00_csa_25: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(25) , --i-- + b => pp0_01(25) , --i-- + c => pp0_00(25) , --i-- + sum => pp1_01(25) , --o-- + car => pp1_00(24)); --o-- + pp1_00_csa_24: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(24) , --i-- + b => pp0_01(24) , --i-- + c => pp0_00(24) , --i-- + sum => pp1_01(24) , --o-- + car => pp1_00(23)); --o-- + pp1_00_csa_23: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(23) , --i-- + b => pp0_01(23) , --i-- + c => pp0_00(23) , --i-- + sum => pp1_01(23) , --o-- + car => pp1_00(22)); --o-- + pp1_00_csa_22: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(22) , --i-- + b => pp0_01(22) , --i-- + c => pp0_00(22) , --i-- + sum => pp1_01(22) , --o-- + car => pp1_00(21)); --o-- + pp1_00_csa_21: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(21) , --i-- + b => pp0_01(21) , --i-- + c => pp0_00(21) , --i-- + sum => pp1_01(21) , --o-- + car => pp1_00(20)); --o-- + pp1_00_csa_20: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(20) , --i-- + b => pp0_01(20) , --i-- + c => pp0_00(20) , --i-- + sum => pp1_01(20) , --o-- + car => pp1_00(19)); --o-- + pp1_00_csa_19: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(19) , --i-- + b => pp0_01(19) , --i-- + c => pp0_00(19) , --i-- + sum => pp1_01(19) , --o-- + car => pp1_00(18)); --o-- + pp1_00_csa_18: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(18) , --i-- + b => pp0_01(18) , --i-- + c => pp0_00(18) , --i-- + sum => pp1_01(18) , --o-- + car => pp1_00(17)); --o-- + pp1_00_csa_17: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(17) , --i-- + b => pp0_01(17) , --i-- + c => pp0_00(17) , --i-- + sum => pp1_01(17) , --o-- + car => pp1_00(16)); --o-- + pp1_00_csa_16: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(16) , --i-- + b => pp0_01(16) , --i-- + c => pp0_00(16) , --i-- + sum => pp1_01(16) , --o-- + car => pp1_00(15)); --o-- + pp1_00_csa_15: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(15) , --i-- + b => pp0_01(15) , --i-- + c => pp0_00(15) , --i-- + sum => pp1_01(15) , --o-- + car => pp1_00(14)); --o-- + pp1_00_csa_14: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(14) , --i-- + b => pp0_01(14) , --i-- + c => pp0_00(14) , --i-- + sum => pp1_01(14) , --o-- + car => pp1_00(13)); --o-- + pp1_00_csa_13: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(13) , --i-- + b => pp0_01(13) , --i-- + c => pp0_00(13) , --i-- + sum => pp1_01(13) , --o-- + car => pp1_00(12)); --o-- + pp1_00_csa_12: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(12) , --i-- + b => pp0_01(12) , --i-- + c => pp0_00(12) , --i-- + sum => pp1_01(12) , --o-- + car => pp1_00(11)); --o-- + pp1_00_csa_11: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(11) , --i-- + b => pp0_01(11) , --i-- + c => pp0_00(11) , --i-- + sum => pp1_01(11) , --o-- + car => pp1_00(10)); --o-- + pp1_00_csa_10: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(10) , --i-- + b => pp0_01(10) , --i-- + c => pp0_00(10) , --i-- + sum => pp1_01(10) , --o-- + car => pp1_00(9)); --o-- + pp1_00_csa_09: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(9) , --i-- + b => pp0_01(9) , --i-- + c => pp0_00(9) , --i-- + sum => pp1_01(9) , --o-- + car => pp1_00(8)); --o-- + pp1_00_csa_08: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(8) , --i-- + b => pp0_01(8) , --i-- + c => pp0_00(8) , --i-- + sum => pp1_01(8) , --o-- + car => pp1_00(7)); --o-- + pp1_00_csa_07: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp0_02(7) , --i-- + b => pp0_01(7) , --i-- + c => pp0_00(7) , --i-- + sum => pp1_01(7) , --o-- + car => pp1_00(6)); --o-- + pp1_00_csa_06: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => tiup , --i-- + b => pp0_01(6) , --i-- + c => pp0_00(6) , --i-- + sum => pp1_01(6) , --o-- + car => pp1_00(5)); --o-- + pp1_00_csa_05: entity work.fuq_csa22_h2(fuq_csa22_h2) port map ( + a => pp0_01(5) , --i-- + b => pp0_00(5) , --i-- + sum => pp1_01(5) , --o-- + car => pp1_00(4)); --o-- + pp1_00_csa_04: entity work.fuq_csa22_h2(fuq_csa22_h2) port map ( + a => tiup , --i-- + b => pp0_00(4) , --i-- + sum => pp1_01(4) , --o-- + car => pp1_00(3)); --o-- + + gg0: if (inst = 0) generate + pp1_01(3) <= tidn ; --unique for different copies of fuq_mul_92 ("0" for msb copy) + pp1_01(2) <= tidn ; --unique for different copies of fuq_mul_92 ("0" for msb copy) + end generate ; + + gg1: if (inst = 1) generate + pp1_01(3) <= pp0_00(3) ; --unique for different copies of fuq_mul_92 ("0" for msb copy) + pp1_01(2) <= pp0_00(2) ; --unique for different copies of fuq_mul_92 ("0" for msb copy) + end generate ; + + gg2: if (inst = 2) generate + pp1_01(3) <= pp0_00(3) ; --unique for different copies of fuq_mul_92 ("0" for msb copy) + pp1_01(2) <= pp0_00(2) ; --unique for different copies of fuq_mul_92 ("0" for msb copy) + end generate ; + + + + + --//################################################## + --//# Compressor Level 2 + --//################################################## + +--//# 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111111111 +--//# 0000000000111111111122222222223333333333444444444455555555556666666666777777777788888888889999999999000000000 +--//# 0123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678 +--//# ...............ouuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuoo.................................. pp1_05 +--//# ..............occccccccccccccccccccccccccccccccccccccccccccccccccccccccc__o.................................. pp1_04 +--//# .........ouuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuoo_o...................................... pp1_03 +--//# ------------------------------------------------------------------------------------- +--//# ..............233333333333333333333333333333333333333333333333333333323 +--//# .........ooooouuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuoooo................................. pp2_03 +--//# .............ccccccccccccccccccccccccccccccccccccccccccccccccccccccccc_o__o................................. pp2_02 + + pp2_03(74) <= pp1_05(74); + pp2_03(73) <= pp1_05(73); + pp2_03(72) <= pp1_05(72); + pp2_03(71) <= pp1_05(71); + + pp2_02(74) <= pp1_04(74); + pp2_02(73) <= tidn; + pp2_02(72) <= tidn; + pp2_02(71) <= pp1_04(71); + pp2_02(70) <= tidn; + + pp2_01_csa_70: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(70) , --i-- + b => pp1_04(70) , --i-- + c => pp1_03(70) , --i-- + sum => pp2_03(70) , --o-- + car => pp2_02(69)); --o-- + pp2_01_csa_69: entity work.fuq_csa22_h2(fuq_csa22_h2) port map ( + a => pp1_05(69) , --i-- + b => pp1_04(69) , --i-- + sum => pp2_03(69) , --o-- + car => pp2_02(68)); --o-- + pp2_01_csa_68: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(68) , --i-- + b => pp1_04(68) , --i-- + c => pp1_03(68) , --i-- + sum => pp2_03(68) , --o-- + car => pp2_02(67)); --o-- + pp2_01_csa_67: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(67) , --i-- + b => pp1_04(67) , --i-- + c => pp1_03(67) , --i-- + sum => pp2_03(67) , --o-- + car => pp2_02(66)); --o-- + pp2_01_csa_66: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(66) , --i-- + b => pp1_04(66) , --i-- + c => pp1_03(66) , --i-- + sum => pp2_03(66) , --o-- + car => pp2_02(65)); --o-- + pp2_01_csa_65: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(65) , --i-- + b => pp1_04(65) , --i-- + c => pp1_03(65) , --i-- + sum => pp2_03(65) , --o-- + car => pp2_02(64)); --o-- + pp2_01_csa_64: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(64) , --i-- + b => pp1_04(64) , --i-- + c => pp1_03(64) , --i-- + sum => pp2_03(64) , --o-- + car => pp2_02(63)); --o-- + pp2_01_csa_63: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(63) , --i-- + b => pp1_04(63) , --i-- + c => pp1_03(63) , --i-- + sum => pp2_03(63) , --o-- + car => pp2_02(62)); --o-- + pp2_01_csa_62: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(62) , --i-- + b => pp1_04(62) , --i-- + c => pp1_03(62) , --i-- + sum => pp2_03(62) , --o-- + car => pp2_02(61)); --o-- + pp2_01_csa_61: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(61) , --i-- + b => pp1_04(61) , --i-- + c => pp1_03(61) , --i-- + sum => pp2_03(61) , --o-- + car => pp2_02(60)); --o-- + pp2_01_csa_60: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(60) , --i-- + b => pp1_04(60) , --i-- + c => pp1_03(60) , --i-- + sum => pp2_03(60) , --o-- + car => pp2_02(59)); --o-- + pp2_01_csa_59: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(59) , --i-- + b => pp1_04(59) , --i-- + c => pp1_03(59) , --i-- + sum => pp2_03(59) , --o-- + car => pp2_02(58)); --o-- + pp2_01_csa_58: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(58) , --i-- + b => pp1_04(58) , --i-- + c => pp1_03(58) , --i-- + sum => pp2_03(58) , --o-- + car => pp2_02(57)); --o-- + pp2_01_csa_57: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(57) , --i-- + b => pp1_04(57) , --i-- + c => pp1_03(57) , --i-- + sum => pp2_03(57) , --o-- + car => pp2_02(56)); --o-- + pp2_01_csa_56: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(56) , --i-- + b => pp1_04(56) , --i-- + c => pp1_03(56) , --i-- + sum => pp2_03(56) , --o-- + car => pp2_02(55)); --o-- + pp2_01_csa_55: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(55) , --i-- + b => pp1_04(55) , --i-- + c => pp1_03(55) , --i-- + sum => pp2_03(55) , --o-- + car => pp2_02(54)); --o-- + pp2_01_csa_54: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(54) , --i-- + b => pp1_04(54) , --i-- + c => pp1_03(54) , --i-- + sum => pp2_03(54) , --o-- + car => pp2_02(53)); --o-- + pp2_01_csa_53: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(53) , --i-- + b => pp1_04(53) , --i-- + c => pp1_03(53) , --i-- + sum => pp2_03(53) , --o-- + car => pp2_02(52)); --o-- + pp2_01_csa_52: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(52) , --i-- + b => pp1_04(52) , --i-- + c => pp1_03(52) , --i-- + sum => pp2_03(52) , --o-- + car => pp2_02(51)); --o-- + pp2_01_csa_51: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(51) , --i-- + b => pp1_04(51) , --i-- + c => pp1_03(51) , --i-- + sum => pp2_03(51) , --o-- + car => pp2_02(50)); --o-- + pp2_01_csa_50: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(50) , --i-- + b => pp1_04(50) , --i-- + c => pp1_03(50) , --i-- + sum => pp2_03(50) , --o-- + car => pp2_02(49)); --o-- + pp2_01_csa_49: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(49) , --i-- + b => pp1_04(49) , --i-- + c => pp1_03(49) , --i-- + sum => pp2_03(49) , --o-- + car => pp2_02(48)); --o-- + pp2_01_csa_48: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(48) , --i-- + b => pp1_04(48) , --i-- + c => pp1_03(48) , --i-- + sum => pp2_03(48) , --o-- + car => pp2_02(47)); --o-- + pp2_01_csa_47: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(47) , --i-- + b => pp1_04(47) , --i-- + c => pp1_03(47) , --i-- + sum => pp2_03(47) , --o-- + car => pp2_02(46)); --o-- + pp2_01_csa_46: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(46) , --i-- + b => pp1_04(46) , --i-- + c => pp1_03(46) , --i-- + sum => pp2_03(46) , --o-- + car => pp2_02(45)); --o-- + pp2_01_csa_45: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(45) , --i-- + b => pp1_04(45) , --i-- + c => pp1_03(45) , --i-- + sum => pp2_03(45) , --o-- + car => pp2_02(44)); --o-- + pp2_01_csa_44: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(44) , --i-- + b => pp1_04(44) , --i-- + c => pp1_03(44) , --i-- + sum => pp2_03(44) , --o-- + car => pp2_02(43)); --o-- + pp2_01_csa_43: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(43) , --i-- + b => pp1_04(43) , --i-- + c => pp1_03(43) , --i-- + sum => pp2_03(43) , --o-- + car => pp2_02(42)); --o-- + pp2_01_csa_42: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(42) , --i-- + b => pp1_04(42) , --i-- + c => pp1_03(42) , --i-- + sum => pp2_03(42) , --o-- + car => pp2_02(41)); --o-- + pp2_01_csa_41: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(41) , --i-- + b => pp1_04(41) , --i-- + c => pp1_03(41) , --i-- + sum => pp2_03(41) , --o-- + car => pp2_02(40)); --o-- + pp2_01_csa_40: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(40) , --i-- + b => pp1_04(40) , --i-- + c => pp1_03(40) , --i-- + sum => pp2_03(40) , --o-- + car => pp2_02(39)); --o-- + pp2_01_csa_39: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(39) , --i-- + b => pp1_04(39) , --i-- + c => pp1_03(39) , --i-- + sum => pp2_03(39) , --o-- + car => pp2_02(38)); --o-- + pp2_01_csa_38: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(38) , --i-- + b => pp1_04(38) , --i-- + c => pp1_03(38) , --i-- + sum => pp2_03(38) , --o-- + car => pp2_02(37)); --o-- + pp2_01_csa_37: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(37) , --i-- + b => pp1_04(37) , --i-- + c => pp1_03(37) , --i-- + sum => pp2_03(37) , --o-- + car => pp2_02(36)); --o-- + pp2_01_csa_36: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(36) , --i-- + b => pp1_04(36) , --i-- + c => pp1_03(36) , --i-- + sum => pp2_03(36) , --o-- + car => pp2_02(35)); --o-- + pp2_01_csa_35: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(35) , --i-- + b => pp1_04(35) , --i-- + c => pp1_03(35) , --i-- + sum => pp2_03(35) , --o-- + car => pp2_02(34)); --o-- + pp2_01_csa_34: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(34) , --i-- + b => pp1_04(34) , --i-- + c => pp1_03(34) , --i-- + sum => pp2_03(34) , --o-- + car => pp2_02(33)); --o-- + pp2_01_csa_33: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(33) , --i-- + b => pp1_04(33) , --i-- + c => pp1_03(33) , --i-- + sum => pp2_03(33) , --o-- + car => pp2_02(32)); --o-- + pp2_01_csa_32: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(32) , --i-- + b => pp1_04(32) , --i-- + c => pp1_03(32) , --i-- + sum => pp2_03(32) , --o-- + car => pp2_02(31)); --o-- + pp2_01_csa_31: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(31) , --i-- + b => pp1_04(31) , --i-- + c => pp1_03(31) , --i-- + sum => pp2_03(31) , --o-- + car => pp2_02(30)); --o-- + pp2_01_csa_30: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(30) , --i-- + b => pp1_04(30) , --i-- + c => pp1_03(30) , --i-- + sum => pp2_03(30) , --o-- + car => pp2_02(29)); --o-- + pp2_01_csa_29: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(29) , --i-- + b => pp1_04(29) , --i-- + c => pp1_03(29) , --i-- + sum => pp2_03(29) , --o-- + car => pp2_02(28)); --o-- + pp2_01_csa_28: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(28) , --i-- + b => pp1_04(28) , --i-- + c => pp1_03(28) , --i-- + sum => pp2_03(28) , --o-- + car => pp2_02(27)); --o-- + pp2_01_csa_27: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(27) , --i-- + b => pp1_04(27) , --i-- + c => pp1_03(27) , --i-- + sum => pp2_03(27) , --o-- + car => pp2_02(26)); --o-- + pp2_01_csa_26: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(26) , --i-- + b => pp1_04(26) , --i-- + c => pp1_03(26) , --i-- + sum => pp2_03(26) , --o-- + car => pp2_02(25)); --o-- + pp2_01_csa_25: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(25) , --i-- + b => pp1_04(25) , --i-- + c => pp1_03(25) , --i-- + sum => pp2_03(25) , --o-- + car => pp2_02(24)); --o-- + pp2_01_csa_24: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(24) , --i-- + b => pp1_04(24) , --i-- + c => pp1_03(24) , --i-- + sum => pp2_03(24) , --o-- + car => pp2_02(23)); --o-- + pp2_01_csa_23: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(23) , --i-- + b => pp1_04(23) , --i-- + c => pp1_03(23) , --i-- + sum => pp2_03(23) , --o-- + car => pp2_02(22)); --o-- + pp2_01_csa_22: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(22) , --i-- + b => pp1_04(22) , --i-- + c => pp1_03(22) , --i-- + sum => pp2_03(22) , --o-- + car => pp2_02(21)); --o-- + pp2_01_csa_21: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(21) , --i-- + b => pp1_04(21) , --i-- + c => pp1_03(21) , --i-- + sum => pp2_03(21) , --o-- + car => pp2_02(20)); --o-- + pp2_01_csa_20: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(20) , --i-- + b => pp1_04(20) , --i-- + c => pp1_03(20) , --i-- + sum => pp2_03(20) , --o-- + car => pp2_02(19)); --o-- + pp2_01_csa_19: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(19) , --i-- + b => pp1_04(19) , --i-- + c => pp1_03(19) , --i-- + sum => pp2_03(19) , --o-- + car => pp2_02(18)); --o-- + pp2_01_csa_18: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(18) , --i-- + b => pp1_04(18) , --i-- + c => pp1_03(18) , --i-- + sum => pp2_03(18) , --o-- + car => pp2_02(17)); --o-- + pp2_01_csa_17: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(17) , --i-- + b => pp1_04(17) , --i-- + c => pp1_03(17) , --i-- + sum => pp2_03(17) , --o-- + car => pp2_02(16)); --o-- + pp2_01_csa_16: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(16) , --i-- + b => pp1_04(16) , --i-- + c => pp1_03(16) , --i-- + sum => pp2_03(16) , --o-- + car => pp2_02(15)); --o-- + pp2_01_csa_15: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_05(15) , --i-- + b => pp1_04(15) , --i-- + c => pp1_03(15) , --i-- + sum => pp2_03(15) , --o-- + car => pp2_02(14)); --o-- + pp2_01_csa_14: entity work.fuq_csa22_h2(fuq_csa22_h2) port map ( + a => tiup , --i-- + b => pp1_03(14) , --i-- + sum => pp2_03(14) , --o-- + car => pp2_02(13)); --o-- + pp2_03(13) <= pp1_03(13); + pp2_03(12) <= pp1_03(12); + pp2_03(11) <= pp1_03(11); + pp2_03(10) <= pp1_03(10); + pp2_03(9) <= pp1_03(9); + pp2_03(8) <= tiup; + + +--//# 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111111111 +--//# 0000000000111111111122222222223333333333444444444455555555556666666666777777777788888888889999999999000000000 +--//# 0123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678 +--//# ........occccccccccccccccccccccccccccccccccccccccccccccccccccccccc__o........................................ pp1_02 +--//# ...ouuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuoo_o............................................ pp1_01 +--//# ..occccccccccccccccccccccccccccccccccccccccccccccccccccccccc__o.............................................. pp1_00 +--//# ------------------------------------------------------------------------------------- +--//# 222223333333333333333333333333333333333333333333333333333223 +--//# ..ouuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuooo__o........................................ pp2_01 +--//# ..cccccccccccccccccccccccccccccccccccccccccccccccccccccccccccc__o............................................ pp2_00 + + pp2_01(68) <= pp1_02(68); + pp2_01(67) <= tidn; + pp2_01(66) <= tidn; + pp2_01(65) <= pp1_02(65); + pp2_01(64) <= pp1_02(64); + pp2_01(63) <= pp1_02(63); + + pp2_00(64) <= pp1_01(64); + pp2_00(63) <= tidn; + pp2_00(62) <= tidn; + + pp2_00_csa_62: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(62) , --i-- + b => pp1_01(62) , --i-- + c => pp1_00(62) , --i-- + sum => pp2_01(62) , --o-- + car => pp2_00(61)); --o-- + pp2_00_csa_61: entity work.fuq_csa22_h2(fuq_csa22_h2) port map ( + a => pp1_02(61) , --i-- + b => pp1_01(61) , --i-- + sum => pp2_01(61) , --o-- + car => pp2_00(60)); --o-- + pp2_00_csa_60: entity work.fuq_csa22_h2(fuq_csa22_h2) port map ( + a => pp1_02(60) , --i-- + b => pp1_01(60) , --i-- + sum => pp2_01(60) , --o-- + car => pp2_00(59)); --o-- + pp2_00_csa_59: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(59) , --i-- + b => pp1_01(59) , --i-- + c => pp1_00(59) , --i-- + sum => pp2_01(59) , --o-- + car => pp2_00(58)); --o-- + pp2_00_csa_58: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(58) , --i-- + b => pp1_01(58) , --i-- + c => pp1_00(58) , --i-- + sum => pp2_01(58) , --o-- + car => pp2_00(57)); --o-- + pp2_00_csa_57: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(57) , --i-- + b => pp1_01(57) , --i-- + c => pp1_00(57) , --i-- + sum => pp2_01(57) , --o-- + car => pp2_00(56)); --o-- + pp2_00_csa_56: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(56) , --i-- + b => pp1_01(56) , --i-- + c => pp1_00(56) , --i-- + sum => pp2_01(56) , --o-- + car => pp2_00(55)); --o-- + pp2_00_csa_55: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(55) , --i-- + b => pp1_01(55) , --i-- + c => pp1_00(55) , --i-- + sum => pp2_01(55) , --o-- + car => pp2_00(54)); --o-- + pp2_00_csa_54: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(54) , --i-- + b => pp1_01(54) , --i-- + c => pp1_00(54) , --i-- + sum => pp2_01(54) , --o-- + car => pp2_00(53)); --o-- + pp2_00_csa_53: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(53) , --i-- + b => pp1_01(53) , --i-- + c => pp1_00(53) , --i-- + sum => pp2_01(53) , --o-- + car => pp2_00(52)); --o-- + pp2_00_csa_52: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(52) , --i-- + b => pp1_01(52) , --i-- + c => pp1_00(52) , --i-- + sum => pp2_01(52) , --o-- + car => pp2_00(51)); --o-- + pp2_00_csa_51: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(51) , --i-- + b => pp1_01(51) , --i-- + c => pp1_00(51) , --i-- + sum => pp2_01(51) , --o-- + car => pp2_00(50)); --o-- + pp2_00_csa_50: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(50) , --i-- + b => pp1_01(50) , --i-- + c => pp1_00(50) , --i-- + sum => pp2_01(50) , --o-- + car => pp2_00(49)); --o-- + pp2_00_csa_49: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(49) , --i-- + b => pp1_01(49) , --i-- + c => pp1_00(49) , --i-- + sum => pp2_01(49) , --o-- + car => pp2_00(48)); --o-- + pp2_00_csa_48: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(48) , --i-- + b => pp1_01(48) , --i-- + c => pp1_00(48) , --i-- + sum => pp2_01(48) , --o-- + car => pp2_00(47)); --o-- + pp2_00_csa_47: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(47) , --i-- + b => pp1_01(47) , --i-- + c => pp1_00(47) , --i-- + sum => pp2_01(47) , --o-- + car => pp2_00(46)); --o-- + pp2_00_csa_46: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(46) , --i-- + b => pp1_01(46) , --i-- + c => pp1_00(46) , --i-- + sum => pp2_01(46) , --o-- + car => pp2_00(45)); --o-- + pp2_00_csa_45: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(45) , --i-- + b => pp1_01(45) , --i-- + c => pp1_00(45) , --i-- + sum => pp2_01(45) , --o-- + car => pp2_00(44)); --o-- + pp2_00_csa_44: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(44) , --i-- + b => pp1_01(44) , --i-- + c => pp1_00(44) , --i-- + sum => pp2_01(44) , --o-- + car => pp2_00(43)); --o-- + pp2_00_csa_43: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(43) , --i-- + b => pp1_01(43) , --i-- + c => pp1_00(43) , --i-- + sum => pp2_01(43) , --o-- + car => pp2_00(42)); --o-- + pp2_00_csa_42: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(42) , --i-- + b => pp1_01(42) , --i-- + c => pp1_00(42) , --i-- + sum => pp2_01(42) , --o-- + car => pp2_00(41)); --o-- + pp2_00_csa_41: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(41) , --i-- + b => pp1_01(41) , --i-- + c => pp1_00(41) , --i-- + sum => pp2_01(41) , --o-- + car => pp2_00(40)); --o-- + pp2_00_csa_40: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(40) , --i-- + b => pp1_01(40) , --i-- + c => pp1_00(40) , --i-- + sum => pp2_01(40) , --o-- + car => pp2_00(39)); --o-- + pp2_00_csa_39: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(39) , --i-- + b => pp1_01(39) , --i-- + c => pp1_00(39) , --i-- + sum => pp2_01(39) , --o-- + car => pp2_00(38)); --o-- + pp2_00_csa_38: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(38) , --i-- + b => pp1_01(38) , --i-- + c => pp1_00(38) , --i-- + sum => pp2_01(38) , --o-- + car => pp2_00(37)); --o-- + pp2_00_csa_37: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(37) , --i-- + b => pp1_01(37) , --i-- + c => pp1_00(37) , --i-- + sum => pp2_01(37) , --o-- + car => pp2_00(36)); --o-- + pp2_00_csa_36: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(36) , --i-- + b => pp1_01(36) , --i-- + c => pp1_00(36) , --i-- + sum => pp2_01(36) , --o-- + car => pp2_00(35)); --o-- + pp2_00_csa_35: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(35) , --i-- + b => pp1_01(35) , --i-- + c => pp1_00(35) , --i-- + sum => pp2_01(35) , --o-- + car => pp2_00(34)); --o-- + pp2_00_csa_34: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(34) , --i-- + b => pp1_01(34) , --i-- + c => pp1_00(34) , --i-- + sum => pp2_01(34) , --o-- + car => pp2_00(33)); --o-- + pp2_00_csa_33: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(33) , --i-- + b => pp1_01(33) , --i-- + c => pp1_00(33) , --i-- + sum => pp2_01(33) , --o-- + car => pp2_00(32)); --o-- + pp2_00_csa_32: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(32) , --i-- + b => pp1_01(32) , --i-- + c => pp1_00(32) , --i-- + sum => pp2_01(32) , --o-- + car => pp2_00(31)); --o-- + pp2_00_csa_31: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(31) , --i-- + b => pp1_01(31) , --i-- + c => pp1_00(31) , --i-- + sum => pp2_01(31) , --o-- + car => pp2_00(30)); --o-- + pp2_00_csa_30: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(30) , --i-- + b => pp1_01(30) , --i-- + c => pp1_00(30) , --i-- + sum => pp2_01(30) , --o-- + car => pp2_00(29)); --o-- + pp2_00_csa_29: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(29) , --i-- + b => pp1_01(29) , --i-- + c => pp1_00(29) , --i-- + sum => pp2_01(29) , --o-- + car => pp2_00(28)); --o-- + pp2_00_csa_28: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(28) , --i-- + b => pp1_01(28) , --i-- + c => pp1_00(28) , --i-- + sum => pp2_01(28) , --o-- + car => pp2_00(27)); --o-- + pp2_00_csa_27: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(27) , --i-- + b => pp1_01(27) , --i-- + c => pp1_00(27) , --i-- + sum => pp2_01(27) , --o-- + car => pp2_00(26)); --o-- + pp2_00_csa_26: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(26) , --i-- + b => pp1_01(26) , --i-- + c => pp1_00(26) , --i-- + sum => pp2_01(26) , --o-- + car => pp2_00(25)); --o-- + pp2_00_csa_25: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(25) , --i-- + b => pp1_01(25) , --i-- + c => pp1_00(25) , --i-- + sum => pp2_01(25) , --o-- + car => pp2_00(24)); --o-- + pp2_00_csa_24: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(24) , --i-- + b => pp1_01(24) , --i-- + c => pp1_00(24) , --i-- + sum => pp2_01(24) , --o-- + car => pp2_00(23)); --o-- + pp2_00_csa_23: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(23) , --i-- + b => pp1_01(23) , --i-- + c => pp1_00(23) , --i-- + sum => pp2_01(23) , --o-- + car => pp2_00(22)); --o-- + pp2_00_csa_22: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(22) , --i-- + b => pp1_01(22) , --i-- + c => pp1_00(22) , --i-- + sum => pp2_01(22) , --o-- + car => pp2_00(21)); --o-- + pp2_00_csa_21: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(21) , --i-- + b => pp1_01(21) , --i-- + c => pp1_00(21) , --i-- + sum => pp2_01(21) , --o-- + car => pp2_00(20)); --o-- + pp2_00_csa_20: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(20) , --i-- + b => pp1_01(20) , --i-- + c => pp1_00(20) , --i-- + sum => pp2_01(20) , --o-- + car => pp2_00(19)); --o-- + pp2_00_csa_19: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(19) , --i-- + b => pp1_01(19) , --i-- + c => pp1_00(19) , --i-- + sum => pp2_01(19) , --o-- + car => pp2_00(18)); --o-- + pp2_00_csa_18: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(18) , --i-- + b => pp1_01(18) , --i-- + c => pp1_00(18) , --i-- + sum => pp2_01(18) , --o-- + car => pp2_00(17)); --o-- + pp2_00_csa_17: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(17) , --i-- + b => pp1_01(17) , --i-- + c => pp1_00(17) , --i-- + sum => pp2_01(17) , --o-- + car => pp2_00(16)); --o-- + pp2_00_csa_16: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(16) , --i-- + b => pp1_01(16) , --i-- + c => pp1_00(16) , --i-- + sum => pp2_01(16) , --o-- + car => pp2_00(15)); --o-- + pp2_00_csa_15: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(15) , --i-- + b => pp1_01(15) , --i-- + c => pp1_00(15) , --i-- + sum => pp2_01(15) , --o-- + car => pp2_00(14)); --o-- + pp2_00_csa_14: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(14) , --i-- + b => pp1_01(14) , --i-- + c => pp1_00(14) , --i-- + sum => pp2_01(14) , --o-- + car => pp2_00(13)); --o-- + pp2_00_csa_13: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(13) , --i-- + b => pp1_01(13) , --i-- + c => pp1_00(13) , --i-- + sum => pp2_01(13) , --o-- + car => pp2_00(12)); --o-- + pp2_00_csa_12: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(12) , --i-- + b => pp1_01(12) , --i-- + c => pp1_00(12) , --i-- + sum => pp2_01(12) , --o-- + car => pp2_00(11)); --o-- + pp2_00_csa_11: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(11) , --i-- + b => pp1_01(11) , --i-- + c => pp1_00(11) , --i-- + sum => pp2_01(11) , --o-- + car => pp2_00(10)); --o-- + pp2_00_csa_10: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(10) , --i-- + b => pp1_01(10) , --i-- + c => pp1_00(10) , --i-- + sum => pp2_01(10) , --o-- + car => pp2_00(9)); --o-- + pp2_00_csa_09: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp1_02(9) , --i-- + b => pp1_01(9) , --i-- + c => pp1_00(9) , --i-- + sum => pp2_01(9) , --o-- + car => pp2_00(8)); --o-- + pp2_00_csa_08: entity work.fuq_csa22_h2(fuq_csa22_h2) port map ( + a => pp1_01(8) , --i-- + b => pp1_00(8) , --i-- + sum => pp2_01(8) , --o-- + car => pp2_00(7)); --o-- + pp2_00_csa_07: entity work.fuq_csa22_h2(fuq_csa22_h2) port map ( + a => pp1_01(7) , --i-- + b => pp1_00(7) , --i-- + sum => pp2_01(7) , --o-- + car => pp2_00(6)); --o-- + pp2_00_csa_06: entity work.fuq_csa22_h2(fuq_csa22_h2) port map ( + a => pp1_01(6) , --i-- + b => pp1_00(6) , --i-- + sum => pp2_01(6) , --o-- + car => pp2_00(5)); --o-- + pp2_00_csa_05: entity work.fuq_csa22_h2(fuq_csa22_h2) port map ( + a => pp1_01(5) , --i-- + b => pp1_00(5) , --i-- + sum => pp2_01(5) , --o-- + car => pp2_00(4)); --o-- + pp2_00_csa_04: entity work.fuq_csa22_h2(fuq_csa22_h2) port map ( + a => pp1_01(4) , --i-- + b => pp1_00(4) , --i-- + sum => pp2_01(4) , --o-- + car => pp2_00(3)); --o-- + pp2_00_csa_03: entity work.fuq_csa22_h2(fuq_csa22_h2) port map ( + a => pp1_01(3) , --i-- + b => pp1_00(3) , --i-- + sum => pp2_01(3) , --o-- + car => pp2_00(2)); --o-- + pp2_01(2) <= pp1_01(2); + + + + + --//################################################## + --//# Compressor Level 3 + --//################################################## + +--//# 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111111111 +--//# 0000000000111111111122222222223333333333444444444455555555556666666666777777777788888888889999999999000000000 +--//# 0123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678 +--//# .........ooooouuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuoooo.................................. pp2_03 +--//# .............ccccccccccccccccccccccccccccccccccccccccccccccccccccccccc_o__o.................................. pp2_02 +--//# ..ouuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuooo__o........................................ pp2_01 +--//# ..cccccccccccccccccccccccccccccccccccccccccccccccccccccccccccc__o............................................ pp2_00 +--//# ---------------------------------------------------------------------------------------------------------- +--//# ..2222223333344444444444444444444444444444444444444444444444443343223........................................ +--//# ..uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuoooooo.................................. pp3_01 +--//# .ccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccc_o_o__o.................................. pp3_00 + + + + pp3_01(74) <= pp2_03(74); + pp3_01(73) <= pp2_03(73); + pp3_01(72) <= pp2_03(72); + pp3_01(71) <= pp2_03(71); + pp3_01(70) <= pp2_03(70); + pp3_01(69) <= pp2_03(69); + + pp3_00(74) <= pp2_02(74); + pp3_00(73) <= tidn; + pp3_00(72) <= tidn; + pp3_00(71) <= pp2_02(71); + pp3_00(70) <= tidn; + pp3_00(69) <= pp2_02(69); + pp3_00(68) <= tidn; + + pp3_00_csa_68: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(68) , --i-- + b => pp2_02(68) , --i-- + c => pp2_01(68) , --i-- + sum => pp3_01(68) , --o-- + car => pp3_00(67)); --o-- + pp3_00_csa_67: entity work.fuq_csa22_h2(fuq_csa22_h2) port map ( + a => pp2_03(67) , --i-- + b => pp2_02(67) , --i-- + sum => pp3_01(67) , --o-- + car => pp3_00(66)); --o-- + pp3_00_csa_66: entity work.fuq_csa22_h2(fuq_csa22_h2) port map ( + a => pp2_03(66) , --i-- + b => pp2_02(66) , --i-- + sum => pp3_01(66) , --o-- + car => pp3_00(65)); --o-- + pp3_00_csa_65: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(65) , --i-- + b => pp2_02(65) , --i-- + c => pp2_01(65) , --i-- + sum => pp3_01(65) , --o-- + car => pp3_00(64)); --o-- + pp3_00_csa_64: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(64) , --i-- + b => pp2_02(64) , --i-- + c => pp2_01(64) , --i-- + d => pp2_00(64) , --i-- + ki => tidn , --i-- + ko => pp3_00_ko(63) , --o-- + sum => pp3_01(64) , --o-- + car => pp3_00(63)); --o-- + pp3_00_csa_63: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(63) , --i-- + b => pp2_02(63) , --i-- + c => pp2_01(63) , --i-- + d => tidn , --i-- + ki => pp3_00_ko(63) , --i-- + ko => pp3_00_ko(62) , --o-- + sum => pp3_01(63) , --o-- + car => pp3_00(62)); --o-- + pp3_00_csa_62: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(62) , --i-- + b => pp2_02(62) , --i-- + c => pp2_01(62) , --i-- + d => tidn , --i-- + ki => pp3_00_ko(62) , --i-- + ko => pp3_00_ko(61) , --o-- + sum => pp3_01(62) , --o-- + car => pp3_00(61)); --o-- + pp3_00_csa_61: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(61) , --i-- + b => pp2_02(61) , --i-- + c => pp2_01(61) , --i-- + d => pp2_00(61) , --i-- + ki => pp3_00_ko(61) , --i-- + ko => pp3_00_ko(60) , --o-- + sum => pp3_01(61) , --o-- + car => pp3_00(60)); --o-- + pp3_00_csa_60: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(60) , --i-- + b => pp2_02(60) , --i-- + c => pp2_01(60) , --i-- + d => pp2_00(60) , --i-- + ki => pp3_00_ko(60) , --i-- + ko => pp3_00_ko(59) , --o-- + sum => pp3_01(60) , --o-- + car => pp3_00(59)); --o-- + pp3_00_csa_59: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(59) , --i-- + b => pp2_02(59) , --i-- + c => pp2_01(59) , --i-- + d => pp2_00(59) , --i-- + ki => pp3_00_ko(59) , --i-- + ko => pp3_00_ko(58) , --o-- + sum => pp3_01(59) , --o-- + car => pp3_00(58)); --o-- + pp3_00_csa_58: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(58) , --i-- + b => pp2_02(58) , --i-- + c => pp2_01(58) , --i-- + d => pp2_00(58) , --i-- + ki => pp3_00_ko(58) , --i-- + ko => pp3_00_ko(57) , --o-- + sum => pp3_01(58) , --o-- + car => pp3_00(57)); --o-- + pp3_00_csa_57: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(57) , --i-- + b => pp2_02(57) , --i-- + c => pp2_01(57) , --i-- + d => pp2_00(57) , --i-- + ki => pp3_00_ko(57) , --i-- + ko => pp3_00_ko(56) , --o-- + sum => pp3_01(57) , --o-- + car => pp3_00(56)); --o-- + pp3_00_csa_56: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(56) , --i-- + b => pp2_02(56) , --i-- + c => pp2_01(56) , --i-- + d => pp2_00(56) , --i-- + ki => pp3_00_ko(56) , --i-- + ko => pp3_00_ko(55) , --o-- + sum => pp3_01(56) , --o-- + car => pp3_00(55)); --o-- + pp3_00_csa_55: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(55) , --i-- + b => pp2_02(55) , --i-- + c => pp2_01(55) , --i-- + d => pp2_00(55) , --i-- + ki => pp3_00_ko(55) , --i-- + ko => pp3_00_ko(54) , --o-- + sum => pp3_01(55) , --o-- + car => pp3_00(54)); --o-- + pp3_00_csa_54: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(54) , --i-- + b => pp2_02(54) , --i-- + c => pp2_01(54) , --i-- + d => pp2_00(54) , --i-- + ki => pp3_00_ko(54) , --i-- + ko => pp3_00_ko(53) , --o-- + sum => pp3_01(54) , --o-- + car => pp3_00(53)); --o-- + pp3_00_csa_53: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(53) , --i-- + b => pp2_02(53) , --i-- + c => pp2_01(53) , --i-- + d => pp2_00(53) , --i-- + ki => pp3_00_ko(53) , --i-- + ko => pp3_00_ko(52) , --o-- + sum => pp3_01(53) , --o-- + car => pp3_00(52)); --o-- + pp3_00_csa_52: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(52) , --i-- + b => pp2_02(52) , --i-- + c => pp2_01(52) , --i-- + d => pp2_00(52) , --i-- + ki => pp3_00_ko(52) , --i-- + ko => pp3_00_ko(51) , --o-- + sum => pp3_01(52) , --o-- + car => pp3_00(51)); --o-- + pp3_00_csa_51: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(51) , --i-- + b => pp2_02(51) , --i-- + c => pp2_01(51) , --i-- + d => pp2_00(51) , --i-- + ki => pp3_00_ko(51) , --i-- + ko => pp3_00_ko(50) , --o-- + sum => pp3_01(51) , --o-- + car => pp3_00(50)); --o-- + pp3_00_csa_50: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(50) , --i-- + b => pp2_02(50) , --i-- + c => pp2_01(50) , --i-- + d => pp2_00(50) , --i-- + ki => pp3_00_ko(50) , --i-- + ko => pp3_00_ko(49) , --o-- + sum => pp3_01(50) , --o-- + car => pp3_00(49)); --o-- + pp3_00_csa_49: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(49) , --i-- + b => pp2_02(49) , --i-- + c => pp2_01(49) , --i-- + d => pp2_00(49) , --i-- + ki => pp3_00_ko(49) , --i-- + ko => pp3_00_ko(48) , --o-- + sum => pp3_01(49) , --o-- + car => pp3_00(48)); --o-- + pp3_00_csa_48: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(48) , --i-- + b => pp2_02(48) , --i-- + c => pp2_01(48) , --i-- + d => pp2_00(48) , --i-- + ki => pp3_00_ko(48) , --i-- + ko => pp3_00_ko(47) , --o-- + sum => pp3_01(48) , --o-- + car => pp3_00(47)); --o-- + pp3_00_csa_47: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(47) , --i-- + b => pp2_02(47) , --i-- + c => pp2_01(47) , --i-- + d => pp2_00(47) , --i-- + ki => pp3_00_ko(47) , --i-- + ko => pp3_00_ko(46) , --o-- + sum => pp3_01(47) , --o-- + car => pp3_00(46)); --o-- + pp3_00_csa_46: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(46) , --i-- + b => pp2_02(46) , --i-- + c => pp2_01(46) , --i-- + d => pp2_00(46) , --i-- + ki => pp3_00_ko(46) , --i-- + ko => pp3_00_ko(45) , --o-- + sum => pp3_01(46) , --o-- + car => pp3_00(45)); --o-- + pp3_00_csa_45: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(45) , --i-- + b => pp2_02(45) , --i-- + c => pp2_01(45) , --i-- + d => pp2_00(45) , --i-- + ki => pp3_00_ko(45) , --i-- + ko => pp3_00_ko(44) , --o-- + sum => pp3_01(45) , --o-- + car => pp3_00(44)); --o-- + pp3_00_csa_44: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(44) , --i-- + b => pp2_02(44) , --i-- + c => pp2_01(44) , --i-- + d => pp2_00(44) , --i-- + ki => pp3_00_ko(44) , --i-- + ko => pp3_00_ko(43) , --o-- + sum => pp3_01(44) , --o-- + car => pp3_00(43)); --o-- + pp3_00_csa_43: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(43) , --i-- + b => pp2_02(43) , --i-- + c => pp2_01(43) , --i-- + d => pp2_00(43) , --i-- + ki => pp3_00_ko(43) , --i-- + ko => pp3_00_ko(42) , --o-- + sum => pp3_01(43) , --o-- + car => pp3_00(42)); --o-- + pp3_00_csa_42: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(42) , --i-- + b => pp2_02(42) , --i-- + c => pp2_01(42) , --i-- + d => pp2_00(42) , --i-- + ki => pp3_00_ko(42) , --i-- + ko => pp3_00_ko(41) , --o-- + sum => pp3_01(42) , --o-- + car => pp3_00(41)); --o-- + pp3_00_csa_41: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(41) , --i-- + b => pp2_02(41) , --i-- + c => pp2_01(41) , --i-- + d => pp2_00(41) , --i-- + ki => pp3_00_ko(41) , --i-- + ko => pp3_00_ko(40) , --o-- + sum => pp3_01(41) , --o-- + car => pp3_00(40)); --o-- + pp3_00_csa_40: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(40) , --i-- + b => pp2_02(40) , --i-- + c => pp2_01(40) , --i-- + d => pp2_00(40) , --i-- + ki => pp3_00_ko(40) , --i-- + ko => pp3_00_ko(39) , --o-- + sum => pp3_01(40) , --o-- + car => pp3_00(39)); --o-- + pp3_00_csa_39: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(39) , --i-- + b => pp2_02(39) , --i-- + c => pp2_01(39) , --i-- + d => pp2_00(39) , --i-- + ki => pp3_00_ko(39) , --i-- + ko => pp3_00_ko(38) , --o-- + sum => pp3_01(39) , --o-- + car => pp3_00(38)); --o-- + pp3_00_csa_38: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(38) , --i-- + b => pp2_02(38) , --i-- + c => pp2_01(38) , --i-- + d => pp2_00(38) , --i-- + ki => pp3_00_ko(38) , --i-- + ko => pp3_00_ko(37) , --o-- + sum => pp3_01(38) , --o-- + car => pp3_00(37)); --o-- + pp3_00_csa_37: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(37) , --i-- + b => pp2_02(37) , --i-- + c => pp2_01(37) , --i-- + d => pp2_00(37) , --i-- + ki => pp3_00_ko(37) , --i-- + ko => pp3_00_ko(36) , --o-- + sum => pp3_01(37) , --o-- + car => pp3_00(36)); --o-- + pp3_00_csa_36: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(36) , --i-- + b => pp2_02(36) , --i-- + c => pp2_01(36) , --i-- + d => pp2_00(36) , --i-- + ki => pp3_00_ko(36) , --i-- + ko => pp3_00_ko(35) , --o-- + sum => pp3_01(36) , --o-- + car => pp3_00(35)); --o-- + pp3_00_csa_35: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(35) , --i-- + b => pp2_02(35) , --i-- + c => pp2_01(35) , --i-- + d => pp2_00(35) , --i-- + ki => pp3_00_ko(35) , --i-- + ko => pp3_00_ko(34) , --o-- + sum => pp3_01(35) , --o-- + car => pp3_00(34)); --o-- + pp3_00_csa_34: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(34) , --i-- + b => pp2_02(34) , --i-- + c => pp2_01(34) , --i-- + d => pp2_00(34) , --i-- + ki => pp3_00_ko(34) , --i-- + ko => pp3_00_ko(33) , --o-- + sum => pp3_01(34) , --o-- + car => pp3_00(33)); --o-- + pp3_00_csa_33: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(33) , --i-- + b => pp2_02(33) , --i-- + c => pp2_01(33) , --i-- + d => pp2_00(33) , --i-- + ki => pp3_00_ko(33) , --i-- + ko => pp3_00_ko(32) , --o-- + sum => pp3_01(33) , --o-- + car => pp3_00(32)); --o-- + pp3_00_csa_32: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(32) , --i-- + b => pp2_02(32) , --i-- + c => pp2_01(32) , --i-- + d => pp2_00(32) , --i-- + ki => pp3_00_ko(32) , --i-- + ko => pp3_00_ko(31) , --o-- + sum => pp3_01(32) , --o-- + car => pp3_00(31)); --o-- + pp3_00_csa_31: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(31) , --i-- + b => pp2_02(31) , --i-- + c => pp2_01(31) , --i-- + d => pp2_00(31) , --i-- + ki => pp3_00_ko(31) , --i-- + ko => pp3_00_ko(30) , --o-- + sum => pp3_01(31) , --o-- + car => pp3_00(30)); --o-- + pp3_00_csa_30: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(30) , --i-- + b => pp2_02(30) , --i-- + c => pp2_01(30) , --i-- + d => pp2_00(30) , --i-- + ki => pp3_00_ko(30) , --i-- + ko => pp3_00_ko(29) , --o-- + sum => pp3_01(30) , --o-- + car => pp3_00(29)); --o-- + pp3_00_csa_29: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(29) , --i-- + b => pp2_02(29) , --i-- + c => pp2_01(29) , --i-- + d => pp2_00(29) , --i-- + ki => pp3_00_ko(29) , --i-- + ko => pp3_00_ko(28) , --o-- + sum => pp3_01(29) , --o-- + car => pp3_00(28)); --o-- + pp3_00_csa_28: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(28) , --i-- + b => pp2_02(28) , --i-- + c => pp2_01(28) , --i-- + d => pp2_00(28) , --i-- + ki => pp3_00_ko(28) , --i-- + ko => pp3_00_ko(27) , --o-- + sum => pp3_01(28) , --o-- + car => pp3_00(27)); --o-- + pp3_00_csa_27: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(27) , --i-- + b => pp2_02(27) , --i-- + c => pp2_01(27) , --i-- + d => pp2_00(27) , --i-- + ki => pp3_00_ko(27) , --i-- + ko => pp3_00_ko(26) , --o-- + sum => pp3_01(27) , --o-- + car => pp3_00(26)); --o-- + pp3_00_csa_26: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(26) , + b => pp2_02(26) , + c => pp2_01(26) , + d => pp2_00(26) , + ki => pp3_00_ko(26) , + ko => pp3_00_ko(25) , + sum => pp3_01(26) , + car => pp3_00(25)); + pp3_00_csa_25: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(25) , --i-- + b => pp2_02(25) , --i-- + c => pp2_01(25) , --i-- + d => pp2_00(25) , --i-- + ki => pp3_00_ko(25) , --i-- + ko => pp3_00_ko(24) , --o-- + sum => pp3_01(25) , --o-- + car => pp3_00(24)); --o-- + pp3_00_csa_24: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(24) , --i-- + b => pp2_02(24) , --i-- + c => pp2_01(24) , --i-- + d => pp2_00(24) , --i-- + ki => pp3_00_ko(24) , --i-- + ko => pp3_00_ko(23) , --o-- + sum => pp3_01(24) , --o-- + car => pp3_00(23)); --o-- + pp3_00_csa_23: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(23) , --i-- + b => pp2_02(23) , --i-- + c => pp2_01(23) , --i-- + d => pp2_00(23) , --i-- + ki => pp3_00_ko(23) , --i-- + ko => pp3_00_ko(22) , --o-- + sum => pp3_01(23) , --o-- + car => pp3_00(22)); --o-- + pp3_00_csa_22: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(22) , --i-- + b => pp2_02(22) , --i-- + c => pp2_01(22) , --i-- + d => pp2_00(22) , --i-- + ki => pp3_00_ko(22) , --i-- + ko => pp3_00_ko(21) , --o-- + sum => pp3_01(22) , --o-- + car => pp3_00(21)); --o-- + pp3_00_csa_21: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(21) , --i-- + b => pp2_02(21) , --i-- + c => pp2_01(21) , --i-- + d => pp2_00(21) , --i-- + ki => pp3_00_ko(21) , --i-- + ko => pp3_00_ko(20) , --o-- + sum => pp3_01(21) , --o-- + car => pp3_00(20)); --o-- + pp3_00_csa_20: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(20) , --i-- + b => pp2_02(20) , --i-- + c => pp2_01(20) , --i-- + d => pp2_00(20) , --i-- + ki => pp3_00_ko(20) , --i-- + ko => pp3_00_ko(19) , --o-- + sum => pp3_01(20) , --o-- + car => pp3_00(19)); --o-- + pp3_00_csa_19: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(19) , --i-- + b => pp2_02(19) , --i-- + c => pp2_01(19) , --i-- + d => pp2_00(19) , --i-- + ki => pp3_00_ko(19) , --i-- + ko => pp3_00_ko(18) , --o-- + sum => pp3_01(19) , --o-- + car => pp3_00(18)); --o-- + pp3_00_csa_18: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(18) , --i-- + b => pp2_02(18) , --i-- + c => pp2_01(18) , --i-- + d => pp2_00(18) , --i-- + ki => pp3_00_ko(18) , --i-- + ko => pp3_00_ko(17) , --o-- + sum => pp3_01(18) , --o-- + car => pp3_00(17)); --o-- + pp3_00_csa_17: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(17) , --i-- + b => pp2_02(17) , --i-- + c => pp2_01(17) , --i-- + d => pp2_00(17) , --i-- + ki => pp3_00_ko(17) , --i-- + ko => pp3_00_ko(16) , --o-- + sum => pp3_01(17) , --o-- + car => pp3_00(16)); --o-- + pp3_00_csa_16: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(16) , --i-- + b => pp2_02(16) , --i-- + c => pp2_01(16) , --i-- + d => pp2_00(16) , --i-- + ki => pp3_00_ko(16) , --i-- + ko => pp3_00_ko(15) , --o-- + sum => pp3_01(16) , --o-- + car => pp3_00(15)); --o-- + pp3_00_csa_15: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(15) , --i-- + b => pp2_02(15) , --i-- + c => pp2_01(15) , --i-- + d => pp2_00(15) , --i-- + ki => pp3_00_ko(15) , --i-- + ko => pp3_00_ko(14) , --o-- + sum => pp3_01(15) , --o-- + car => pp3_00(14)); --o-- + pp3_00_csa_14: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(14) , --i-- + b => pp2_02(14) , --i-- + c => pp2_01(14) , --i-- + d => pp2_00(14) , --i-- + ki => pp3_00_ko(14) , --i-- + ko => pp3_00_ko(13) , --o-- + sum => pp3_01(14) , --o-- + car => pp3_00(13)); --o-- + pp3_00_csa_13: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(13) , --i-- + b => pp2_02(13) , --i-- + c => pp2_01(13) , --i-- + d => pp2_00(13) , --i-- + ki => pp3_00_ko(13) , --i-- + ko => pp3_00_ko(12) , --o-- + sum => pp3_01(13) , --o-- + car => pp3_00(12)); --o-- + pp3_00_csa_12: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(12) , --i-- + b => pp2_01(12) , --i-- + c => pp2_00(12) , --i-- + d => tidn , --i-- + ki => pp3_00_ko(12) , --i-- + ko => pp3_00_ko(11) , --o-- + sum => pp3_01(12) , --o-- + car => pp3_00(11)); --o-- + pp3_00_csa_11: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(11) , --i-- + b => pp2_01(11) , --i-- + c => pp2_00(11) , --i-- + d => tidn , --i-- + ki => pp3_00_ko(11) , --i-- + ko => pp3_00_ko(10) , --o-- + sum => pp3_01(11) , --o-- + car => pp3_00(10)); --o-- + pp3_00_csa_10: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(10) , --i-- + b => pp2_01(10) , --i-- + c => pp2_00(10) , --i-- + d => tidn , --i-- + ki => pp3_00_ko(10) , --i-- + ko => pp3_00_ko(9) , --o-- + sum => pp3_01(10) , --o-- + car => pp3_00(9)); --o-- + pp3_00_csa_09: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => pp2_03(9) , --i-- + b => pp2_01(9) , --i-- + c => pp2_00(9) , --i-- + d => tidn , --i-- + ki => pp3_00_ko(9) , --i-- + ko => pp3_00_ko(8) , --o-- + sum => pp3_01(9) , --o-- + car => pp3_00(8)); --o-- + pp3_00_csa_08: entity clib.c_prism_csa42 port map ( + vd => vdd, + gd => gnd, + a => tiup , --i-- + b => pp2_01(8) , --i-- + c => pp2_00(8) , --i-- + d => tidn , --i-- + ki => pp3_00_ko(8) , --i-- + ko => pp3_00_ko(7) , --o-- + sum => pp3_01(8) , --o-- + car => pp3_00(7)); --o-- + pp3_00_csa_07: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => pp2_01(7) , --i-- + b => pp2_00(7) , --i-- + c => pp3_00_ko(7) , --i-- + sum => pp3_01(7) , --o-- + car => pp3_00(6)); --o-- + pp3_00_csa_06: entity work.fuq_csa22_h2(fuq_csa22_h2) port map ( + a => pp2_01(6) , --i-- + b => pp2_00(6) , --i-- + sum => pp3_01(6) , --o-- + car => pp3_00(5)); --o-- + pp3_00_csa_05: entity work.fuq_csa22_h2(fuq_csa22_h2) port map ( + a => pp2_01(5) , --i-- + b => pp2_00(5) , --i-- + sum => pp3_01(5) , --o-- + car => pp3_00(4)); --o-- + pp3_00_csa_04: entity work.fuq_csa22_h2(fuq_csa22_h2) port map ( + a => pp2_01(4) , --i-- + b => pp2_00(4) , --i-- + sum => pp3_01(4) , --o-- + car => pp3_00(3)); --o-- + pp3_00_csa_03: entity work.fuq_csa22_h2(fuq_csa22_h2) port map ( + a => pp2_01(3) , --i-- + b => pp2_00(3) , --i-- + sum => pp3_01(3) , --o-- + car => pp3_00(2)); --o-- + pp3_00_csa_02: entity work.fuq_csa22_h2(fuq_csa22_h2) port map ( + a => pp2_01(2) , --i-- + b => pp2_00(2) , --i-- + sum => pp3_01(2) , --o-- + car => pp3_00(1)); --o-- + + + + --//##################################################################### + --//## LATCH ROW scan(r-l-r) + --//##################################################################### + + mul92_lcb: tri_lcbnd generic map (expand_type => expand_type) port map ( + delay_lclkr => lcb_delay_lclkr ,--in -- tidn , + mpw1_b => lcb_mpw1_b ,--in -- tidn , + mpw2_b => lcb_mpw2_b ,--in -- tidn , + forcee => forcee,--in -- tidn , + nclk => nclk ,--in + vd => vdd ,--inout + gd => gnd ,--inout + act => ex1_act ,--in + sg => lcb_sg ,--in + thold_b => thold_b ,--in + d1clk => mul92_d1clk ,--out + d2clk => mul92_d2clk ,--out + lclk => mul92_lclk );--out + + + pp3_lat_sum: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 73, btr => "NLI0001_X1_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd, + gd => gnd, + LCLK => mul92_lclk ,--lclk.clk + D1CLK => mul92_d1clk , + D2CLK => mul92_d2clk , + SCANIN(0) => si , + SCANIN(1 to 72) => pp3_lat_sum_so(0 to 71) , + SCANOUT => pp3_lat_sum_so(0 to 72) , + D(0 to 72) => pp3_01(2 to 74) , + QB(0 to 72) => pp3_01_q_b(2 to 74) ); + + pp3_lat_car: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 71, btr => "NLI0001_X1_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd, + gd => gnd, + LCLK => mul92_lclk ,--lclk.clk + D1CLK => mul92_d1clk , + D2CLK => mul92_d2clk , + SCANIN(0 to 69) => pp3_lat_car_so(1 to 70) , + SCANIN(70) => pp3_lat_sum_so(72) , + SCANOUT => pp3_lat_car_so(0 to 70) , + D(0 to 66) => pp3_00(1 to 67) , + D(67) => pp3_00(69) , + D(68) => hot_one_din , + D(69) => pp3_00(71) , + D(70) => pp3_00(74) , + -------------------------------- + QB(0 to 66) => pp3_00_q_b(1 to 67) , + QB(67) => pp3_00_q_b(69) , + QB(68) => hot_one_out_b , + QB(69) => pp3_00_q_b(71) , + QB(70) => pp3_00_q_b(74) ) ; + + + + pp3_00_q_b(68) <= tiup; + pp3_00_q_b(70) <= tiup; + pp3_00_q_b(72) <= tiup; + pp3_00_q_b(73) <= tiup; + hot_one_out <= not hot_one_out_b ; + + invo_s: sum92(2 to 74) <= not pp3_01_q_b(2 to 74); + invo_c: car92(1 to 74) <= not pp3_00_q_b(1 to 74); + + + so <= pp3_lat_car_so(0); + +end; -- fuq_mul_92 ARCHITECTURE diff --git a/rel/src/vhdl/work/fuq_mul_bthdcd.vhdl b/rel/src/vhdl/work/fuq_mul_bthdcd.vhdl new file mode 100644 index 0000000..eee35c9 --- /dev/null +++ b/rel/src/vhdl/work/fuq_mul_bthdcd.vhdl @@ -0,0 +1,114 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; +use ieee.std_logic_1164.all; +library ibm; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_ao_support.all; +use ibm.std_ulogic_mux_support.all; + +entity fuq_mul_bthdcd is + port( + i0 : in std_ulogic; + i1 : in std_ulogic; + i2 : in std_ulogic; + s_neg : out std_ulogic; + s_x : out std_ulogic; + s_x2 : out std_ulogic); + + + + + +end fuq_mul_bthdcd; + +architecture fuq_mul_bthdcd of fuq_mul_bthdcd is + + + signal s_add :std_ulogic; + signal sx1_a0_b :std_ulogic; + signal sx1_a1_b :std_ulogic; + signal sx1_t :std_ulogic; + signal sx1_i :std_ulogic; + signal sx2_a0_b :std_ulogic; + signal sx2_a1_b :std_ulogic; + signal sx2_t :std_ulogic; + signal sx2_i :std_ulogic; + signal i0_b, i1_b, i2_b :std_ulogic; + + + + + + + + + +begin +-- i0:2 booth recode table +---------------------------------- +-- 000 add sh1=0 sh2=0 sub_adj=0 +-- 001 add sh1=1 sh2=0 sub_adj=0 +-- 010 add sh1=1 sh2=0 sub_adj=0 +-- 011 add sh1=0 sh2=1 sub_adj=0 +-- 100 sub sh1=0 sh2=1 sub_adj=1 +-- 101 sub sh1=1 sh2=0 sub_adj=1 +-- 110 sub sh1=1 sh2=0 sub_adj=1 +-- 111 sub sh1=0 sh2=0 sub_adj=0 + +-- logically correct +------------------------------------ +-- s_neg <= (i0); +-- s_x <= ( not i1 and i2) or ( i1 and not i2); +-- s_x2 <= (i0 and not i1 and not i2) or (not i0 and i1 and i2); + + +u_0i: i0_b <= not( i0 ); +u_1i: i1_b <= not( i1 ); +u_2i: i2_b <= not( i2 ); + + +u_add: s_add <= not( i0 ); +u_sub: s_neg <= not( s_add ); + +u_sx1_a0: sx1_a0_b <= not( i1_b and i2 ) ; +u_sx1_a1: sx1_a1_b <= not( i1 and i2_b ) ; +u_sx1_t: sx1_t <= not( sx1_a0_b and sx1_a1_b ) ; +u_sx1_i: sx1_i <= not( sx1_t ); +u_sx1_ii: s_x <= not( sx1_i ); + +u_sx2_a0: sx2_a0_b <= not( i0 and i1_b and i2_b ) ; +u_sx2_a1: sx2_a1_b <= not( i0_b and i1 and i2 ) ; +u_sx2_t: sx2_t <= not( sx2_a0_b and sx2_a1_b ) ; +u_sx2_i: sx2_i <= not( sx2_t ); +u_sx2_ii: s_x2 <= not( sx2_i ); + +end; diff --git a/rel/src/vhdl/work/fuq_mul_bthmux.vhdl b/rel/src/vhdl/work/fuq_mul_bthmux.vhdl new file mode 100644 index 0000000..d143124 --- /dev/null +++ b/rel/src/vhdl/work/fuq_mul_bthmux.vhdl @@ -0,0 +1,72 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; +use ieee.std_logic_1164.all; +library ibm; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_ao_support.all; +use ibm.std_ulogic_mux_support.all; + +entity fuq_mul_bthmux is port( + X : IN STD_ULOGIC; + SNEG : IN STD_ULOGIC; -- DO NOT FLIP THE INPUT (ADD) + SX : IN STD_ULOGIC; -- SHIFT BY 1 + SX2 : IN STD_ULOGIC; -- SHIFT BY 2 + RIGHT : IN STD_ULOGIC; -- BIT FROM THE RIGHT (LSB) + LEFT : OUT STD_ULOGIC; -- BIT FROM THE LEFT + Q : OUT STD_ULOGIC -- FINAL OUTPUT +); + + + + +end fuq_mul_bthmux; + +architecture fuq_mul_bthmux of fuq_mul_bthmux is + + signal center, q_b :std_ulogic ; + + + +begin + + u_bmx_xor: center <= x xor sneg ; + + left <= center ; --output-- rename, no gate + + u_bmx_aoi: q_b <= not( ( sx and center ) or + ( sx2 and right ) ); + + u_bmx_inv: q <= not q_b ; -- output-- + + + +end; diff --git a/rel/src/vhdl/work/fuq_mul_bthrow.vhdl b/rel/src/vhdl/work/fuq_mul_bthrow.vhdl new file mode 100644 index 0000000..628afd3 --- /dev/null +++ b/rel/src/vhdl/work/fuq_mul_bthrow.vhdl @@ -0,0 +1,571 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; +use ieee.std_logic_1164.all; +library ibm; + +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_ao_support.all; +use ibm.std_ulogic_mux_support.all; + + +entity fuq_mul_bthrow is + port( + x : in std_ulogic_vector(0 to 53); + s_neg : in std_ulogic; -- negate the row + s_x : in std_ulogic; -- shift by 1 + s_x2 : in std_ulogic; -- shift by 2 + hot_one : out std_ulogic; -- lsb term for row below + q : out std_ulogic_vector(0 to 54)); -- final output + + +end fuq_mul_bthrow; -- ENTITY + +architecture fuq_mul_bthrow of fuq_mul_bthrow is + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal left : std_ulogic_vector(0 to 54); + signal unused : std_ulogic; + + + + + +begin + + unused <= left(0) ; -- dangling pin from edge bit + +--//############################################################### +--# A row of the repeated part of the booth_mux row +--//############################################################### + u00 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , --i-- + SX => s_x , --i-- + SX2 => s_x2 , --i-- + X => tidn , --i-- ******** + RIGHT => left(1) , --i-- [n+1] + LEFT => left(0) , --o-- [n] + Q => q(0)); --o-- + + u01 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , --i-- + SX => s_x , --i-- + SX2 => s_x2 , --i-- + X => x(0) , --i-- [n-1] + RIGHT => left(2) , --i-- [n+1] + LEFT => left(1) , --o-- [n] + Q => q(1)); --o-- + + u02 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , --i-- + SX => s_x , --i-- + SX2 => s_x2 , --i-- + X => x(1) , --i-- + RIGHT => left(3) , --i-- + LEFT => left(2) , --o-- + Q => q(2)); --o-- + + u03 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , --i-- + SX => s_x , --i-- + SX2 => s_x2 , --i-- + X => x(2) , --i-- + RIGHT => left(4) , --i-- + LEFT => left(3) , --o-- + Q => q(3)); --o-- + + u04 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , --i-- + SX => s_x , --i-- + SX2 => s_x2 , --i-- + X => x(3) , --i-- + RIGHT => left(5) , --i-- + LEFT => left(4) , --o-- + Q => q(4)); --o-- + + u05 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , --i-- + SX => s_x , --i-- + SX2 => s_x2 , --i-- + X => x(4) , --i-- + RIGHT => left(6) , --i-- + LEFT => left(5) , --o-- + Q => q(5)); --o-- + + u06 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , --i-- + SX => s_x , --i-- + SX2 => s_x2 , --i-- + X => x(5) , --i-- + RIGHT => left(7) , --i-- + LEFT => left(6) , --o-- + Q => q(6)); --o-- + + u07 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , --i-- + SX => s_x , --i-- + SX2 => s_x2 , --i-- + X => x(6) , --i-- + RIGHT => left(8) , --i-- + LEFT => left(7) , --o-- + Q => q(7)); --o-- + + u08 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , --i-- + SX => s_x , --i-- + SX2 => s_x2 , --i-- + X => x(7) , --i-- + RIGHT => left(9) , --i-- + LEFT => left(8) , --o-- + Q => q(8)); --o-- + + u09 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , --i-- + SX => s_x , --i-- + SX2 => s_x2 , --i-- + X => x(8) , --i-- + RIGHT => left(10) , --i-- + LEFT => left(9) , --o-- + Q => q(9)); --o-- + + u10 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , --i-- + SX => s_x , --i-- + SX2 => s_x2 , --i-- + X => x(9) , --i-- + RIGHT => left(11) , --i-- + LEFT => left(10) , --o-- + Q => q(10)); --o-- + + u11 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , --i-- + SX => s_x , --i-- + SX2 => s_x2 , --i-- + X => x(10) , --i-- + RIGHT => left(12) , --i-- + LEFT => left(11) , --o-- + Q => q(11)); --o-- + + u12 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , --i-- + SX => s_x , --i-- + SX2 => s_x2 , --i-- + X => x(11) , --i-- + RIGHT => left(13) , --i-- + LEFT => left(12) , --o-- + Q => q(12)); --o-- + + u13 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , --i-- + SX => s_x , --i-- + SX2 => s_x2 , --i-- + X => x(12) , --i-- + RIGHT => left(14) , --i-- + LEFT => left(13) , --o-- + Q => q(13)); --o-- + + u14 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , --i-- + SX => s_x , --i-- + SX2 => s_x2 , --i-- + X => x(13) , --i-- + RIGHT => left(15) , --i-- + LEFT => left(14) , --o-- + Q => q(14)); --o-- + + u15 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , --i-- + SX => s_x , --i-- + SX2 => s_x2 , --i-- + X => x(14) , --i-- + RIGHT => left(16) , --i-- + LEFT => left(15) , --o-- + Q => q(15)); --o-- + + u16 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , --i-- + SX => s_x , --i-- + SX2 => s_x2 , --i-- + X => x(15) , --i-- + RIGHT => left(17) , --i-- + LEFT => left(16) , --o-- + Q => q(16)); --o-- + + u17 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , --i-- + SX => s_x , --i-- + SX2 => s_x2 , --i-- + X => x(16) , --i-- + RIGHT => left(18) , --i-- + LEFT => left(17) , --o-- + Q => q(17)); --o-- + + u18 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , --i-- + SX => s_x , --i-- + SX2 => s_x2 , --i-- + X => x(17) , --i-- + RIGHT => left(19) , --i-- + LEFT => left(18) , --o-- + Q => q(18)); --o-- + + u19 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , --i-- + SX => s_x , --i-- + SX2 => s_x2 , --i-- + X => x(18) , --i-- + RIGHT => left(20) , --i-- + LEFT => left(19) , --o-- + Q => q(19)); --o-- + + u20 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , --i-- + SX => s_x , --i-- + SX2 => s_x2 , --i-- + X => x(19) , --i-- + RIGHT => left(21) , --i-- + LEFT => left(20) , --o-- + Q => q(20)); --o-- + + u21 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , --i-- + SX => s_x , --i-- + SX2 => s_x2 , --i-- + X => x(20) , --i-- + RIGHT => left(22) , --i-- + LEFT => left(21) , --o-- + Q => q(21)); --o-- + + u22 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , --i-- + SX => s_x , --i-- + SX2 => s_x2 , --i-- + X => x(21) , --i-- + RIGHT => left(23) , --i-- + LEFT => left(22) , --o-- + Q => q(22)); --o-- + + u23 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , --i-- + SX => s_x , --i-- + SX2 => s_x2 , --i-- + X => x(22) , --i-- + RIGHT => left(24) , --i-- + LEFT => left(23) , --o-- + Q => q(23)); --o-- + + u24 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , --i-- + SX => s_x , --i-- + SX2 => s_x2 , --i-- + X => x(23) , --i-- + RIGHT => left(25) , --i-- + LEFT => left(24) , --o-- + Q => q(24)); --o-- + + u25 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , --i-- + SX => s_x , --i-- + SX2 => s_x2 , --i-- + X => x(24) , --i-- + RIGHT => left(26) , --i-- + LEFT => left(25) , --o-- + Q => q(25)); --o-- + + u26 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , --i-- + SX => s_x , --i-- + SX2 => s_x2 , --i-- + X => x(25) , --i-- + RIGHT => left(27) , --i-- + LEFT => left(26) , --o-- + Q => q(26)); --o-- + + u27 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , --i-- + SX => s_x , --i-- + SX2 => s_x2 , --i-- + X => x(26) , --i-- + RIGHT => left(28) , --i-- + LEFT => left(27) , --o-- + Q => q(27)); --o-- + + u28 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , --i-- + SX => s_x , --i-- + SX2 => s_x2 , --i-- + X => x(27) , --i-- + RIGHT => left(29) , --i-- + LEFT => left(28) , --o-- + Q => q(28)); --o-- + + u29 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , --i-- + SX => s_x , --i-- + SX2 => s_x2 , --i-- + X => x(28) , --i-- + RIGHT => left(30) , --i-- + LEFT => left(29) , --o-- + Q => q(29)); --o-- + + u30 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , --i-- + SX => s_x , --i-- + SX2 => s_x2 , --i-- + X => x(29) , --i-- + RIGHT => left(31) , --i-- + LEFT => left(30) , --o-- + Q => q(30)); --o-- + + u31 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , --i-- + SX => s_x , --i-- + SX2 => s_x2 , --i-- + X => x(30) , --i-- + RIGHT => left(32) , --i-- + LEFT => left(31) , --o-- + Q => q(31)); --o-- + + u32 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , --i-- + SX => s_x , --i-- + SX2 => s_x2 , --i-- + X => x(31) , --i-- + RIGHT => left(33) , --i-- + LEFT => left(32) , --o-- + Q => q(32)); --o-- + + u33 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , --i-- + SX => s_x , --i-- + SX2 => s_x2 , --i-- + X => x(32) , --i-- + RIGHT => left(34) , --i-- + LEFT => left(33) , --o-- + Q => q(33)); --o-- + + u34 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , --i-- + SX => s_x , --i-- + SX2 => s_x2 , --i-- + X => x(33) , --i-- + RIGHT => left(35) , --i-- + LEFT => left(34) , --o-- + Q => q(34)); --o-- + + u35 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , --i-- + SX => s_x , --i-- + SX2 => s_x2 , --i-- + X => x(34) , --i-- + RIGHT => left(36) , --i-- + LEFT => left(35) , --o-- + Q => q(35)); --o-- + + u36 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , --i-- + SX => s_x , --i-- + SX2 => s_x2 , --i-- + X => x(35) , --i-- + RIGHT => left(37) , --i-- + LEFT => left(36) , --o-- + Q => q(36)); --o-- + + u37 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , --i-- + SX => s_x , --i-- + SX2 => s_x2 , --i-- + X => x(36) , --i-- + RIGHT => left(38) , --i-- + LEFT => left(37) , --o-- + Q => q(37)); --o-- + + u38 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , --i-- + SX => s_x , --i-- + SX2 => s_x2 , --i-- + X => x(37) , --i-- + RIGHT => left(39) , --i-- + LEFT => left(38) , --o-- + Q => q(38)); --o-- + + u39 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , --i-- + SX => s_x , --i-- + SX2 => s_x2 , --i-- + X => x(38) , --i-- + RIGHT => left(40) , --i-- + LEFT => left(39) , --o-- + Q => q(39)); --o-- + + u40 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , --i-- + SX => s_x , --i-- + SX2 => s_x2 , --i-- + X => x(39) , --i-- + RIGHT => left(41) , --i-- + LEFT => left(40) , --o-- + Q => q(40)); --o-- + + u41 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , --i-- + SX => s_x , --i-- + SX2 => s_x2 , --i-- + X => x(40) , --i-- + RIGHT => left(42) , --i-- + LEFT => left(41) , --o-- + Q => q(41)); --o-- + + u42 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , --i-- + SX => s_x , --i-- + SX2 => s_x2 , --i-- + X => x(41) , --i-- + RIGHT => left(43) , --i-- + LEFT => left(42) , --o-- + Q => q(42)); --o-- + + u43 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , --i-- + SX => s_x , --i-- + SX2 => s_x2 , --i-- + X => x(42) , --i-- + RIGHT => left(44) , --i-- + LEFT => left(43) , --o-- + Q => q(43)); --o-- + + u44 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , --i-- + SX => s_x , --i-- + SX2 => s_x2 , --i-- + X => x(43) , --i-- + RIGHT => left(45) , --i-- + LEFT => left(44) , --o-- + Q => q(44)); --o-- + + u45 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , --i-- + SX => s_x , --i-- + SX2 => s_x2 , --i-- + X => x(44) , --i-- + RIGHT => left(46) , --i-- + LEFT => left(45) , --o-- + Q => q(45)); --o-- + + u46 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , --i-- + SX => s_x , --i-- + SX2 => s_x2 , --i-- + X => x(45) , --i-- + RIGHT => left(47) , --i-- + LEFT => left(46) , --o-- + Q => q(46)); --o-- + + u47 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , --i-- + SX => s_x , --i-- + SX2 => s_x2 , --i-- + X => x(46) , --i-- + RIGHT => left(48) , --i-- + LEFT => left(47) , --o-- + Q => q(47)); --o-- + + u48 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , --i-- + SX => s_x , --i-- + SX2 => s_x2 , --i-- + X => x(47) , --i-- + RIGHT => left(49) , --i-- + LEFT => left(48) , --o-- + Q => q(48)); --o-- + + u49 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , --i-- + SX => s_x , --i-- + SX2 => s_x2 , --i-- + X => x(48) , --i-- + RIGHT => left(50) , --i-- + LEFT => left(49) , --o-- + Q => q(49)); --o-- + + u50 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , --i-- + SX => s_x , --i-- + SX2 => s_x2 , --i-- + X => x(49) , --i-- + RIGHT => left(51) , --i-- + LEFT => left(50) , --o-- + Q => q(50)); --o-- + + u51 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , --i-- + SX => s_x , --i-- + SX2 => s_x2 , --i-- + X => x(50) , --i-- + RIGHT => left(52) , --i-- + LEFT => left(51) , --o-- + Q => q(51)); --o-- + + u52 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , --i-- + SX => s_x , --i-- + SX2 => s_x2 , --i-- + X => x(51) , --i-- + RIGHT => left(53) , --i-- + LEFT => left(52) , --o-- + Q => q(52)); --o-- + + u53 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , --i-- + SX => s_x , --i-- + SX2 => s_x2 , --i-- + X => x(52) , --i-- + RIGHT => left(54) , --i-- + LEFT => left(53) , --o-- + Q => q(53)); --o-- + + u54 : entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg , --i-- + SX => s_x , --i-- + SX2 => s_x2 , --i-- + X => x(53) , --i-- + RIGHT => s_neg , --i-- + LEFT => left(54) , --o-- + Q => q(54)); --o-- + + -- For negate -A = !A + 1 ... this term is the plus 1. + -- this has same bit weight as LSB, so it jumps down a row to free spot in compressor tree. + + u55: hot_one <= ( s_neg and (s_x or s_x2) ); + +end; -- fuq_mul_bthrow ARCHITECTURE diff --git a/rel/src/vhdl/work/fuq_nrm.vhdl b/rel/src/vhdl/work/fuq_nrm.vhdl new file mode 100644 index 0000000..d4d8d25 --- /dev/null +++ b/rel/src/vhdl/work/fuq_nrm.vhdl @@ -0,0 +1,614 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + +entity fuq_nrm is +generic( expand_type : integer := 2 ); -- 0 - ibm tech, 1 - other ); +port( + + vdd :inout power_logic; + gnd :inout power_logic; + clkoff_b :in std_ulogic; -- tiup + act_dis :in std_ulogic; -- ??tidn?? + flush :in std_ulogic; -- ??tidn?? + delay_lclkr :in std_ulogic_vector(4 to 5); -- tidn, + mpw1_b :in std_ulogic_vector(4 to 5); -- tidn, + mpw2_b :in std_ulogic_vector(0 to 1); -- tidn, + sg_1 :in std_ulogic; + thold_1 :in std_ulogic; + fpu_enable :in std_ulogic; --dc_act + nclk :in clk_logic; + + f_nrm_si :in std_ulogic ;-- perv + f_nrm_so :out std_ulogic ;-- perv + ex3_act_b :in std_ulogic ;-- act + + f_lza_ex4_lza_amt_cp1 :in std_ulogic_vector(0 to 7) ;-- shift amount + + f_lza_ex4_lza_dcd64_cp1 :in std_ulogic_vector(0 to 2); --fnrm + f_lza_ex4_lza_dcd64_cp2 :in std_ulogic_vector(0 to 1); --fnrm + f_lza_ex4_lza_dcd64_cp3 :in std_ulogic_vector(0 to 0); --fnrm + f_lza_ex4_sh_rgt_en :in std_ulogic; + + f_add_ex4_res :in std_ulogic_vector(0 to 162) ;-- data to shift + f_add_ex4_sticky :in std_ulogic ;-- or into sticky + f_pic_ex4_byp_prod_nz :in std_ulogic ; + -- f_pic_ex4_byp_prod_nz_sub :in std_ulogic ; + f_nrm_ex5_res :out std_ulogic_vector(0 to 52) ;--rnd, + f_nrm_ex5_int_sign :out std_ulogic ;--rnd, (151:162) + f_nrm_ex5_int_lsbs :out std_ulogic_vector(1 to 12) ;--rnd, (151:162) + f_nrm_ex5_nrm_sticky_dp :out std_ulogic ;--rnd, + f_nrm_ex5_nrm_guard_dp :out std_ulogic ;--rnd, + f_nrm_ex5_nrm_lsb_dp :out std_ulogic ;--rnd, + f_nrm_ex5_nrm_sticky_sp :out std_ulogic ;--rnd, + f_nrm_ex5_nrm_guard_sp :out std_ulogic ;--rnd, + f_nrm_ex5_nrm_lsb_sp :out std_ulogic ;--rnd, + f_nrm_ex5_exact_zero :out std_ulogic ;--rnd, + f_nrm_ex4_extra_shift :out std_ulogic ;--expo_ov, + f_nrm_ex5_fpscr_wr_dat_dfp :out std_ulogic_vector(0 to 3) ;--fpscr, (17:20) + f_nrm_ex5_fpscr_wr_dat :out std_ulogic_vector(0 to 31) --fpscr, (21:52) + + +); -- end ports + + + +end fuq_nrm; -- ENTITY + + +architecture fuq_nrm of fuq_nrm is + + constant tiup :std_ulogic := '1'; + constant tidn :std_ulogic := '0'; + + signal sg_0 :std_ulogic ;-- + signal thold_0_b, thold_0, forcee :std_ulogic ;-- + signal ex3_act :std_ulogic ;-- + signal ex4_act :std_ulogic ;-- + signal act_spare_unused :std_ulogic_vector(0 to 2) ;-- + ------------------- + signal act_so :std_ulogic_vector(0 to 3) ;--SCAN + signal act_si :std_ulogic_vector(0 to 3) ;--SCAN + signal ex5_res_so :std_ulogic_vector(0 to 52) ;--SCAN + signal ex5_res_si :std_ulogic_vector(0 to 52) ;--SCAN + signal ex5_nrm_lg_so :std_ulogic_vector(0 to 3) ;--SCAN + signal ex5_nrm_lg_si :std_ulogic_vector(0 to 3) ;--SCAN + signal ex5_nrm_x_so :std_ulogic_vector(0 to 2) ;--SCAN + signal ex5_nrm_x_si :std_ulogic_vector(0 to 2) ;--SCAN + signal ex5_nrm_pass_so :std_ulogic_vector(0 to 12) ;--SCAN + signal ex5_nrm_pass_si :std_ulogic_vector(0 to 12) ;--SCAN + signal ex5_fmv_so :std_ulogic_vector(0 to 35) ;--SCAN + signal ex5_fmv_si :std_ulogic_vector(0 to 35) ;--SCAN + ------------------- + signal ex4_sh2 :std_ulogic_vector(26 to 72) ; + signal ex4_sh4_25 :std_ulogic ;--shifting + signal ex4_sh4_54 :std_ulogic ;--shifting + signal ex4_nrm_res , ex4_sh5_x_b, ex4_sh5_y_b :std_ulogic_vector(0 to 53) ;--shifting + signal ex4_lt064_x :std_ulogic ;--sticky + signal ex4_lt128_x :std_ulogic ;--sticky + signal ex4_lt016_x :std_ulogic ;--sticky + signal ex4_lt032_x :std_ulogic ;--sticky + signal ex4_lt048_x :std_ulogic ;--sticky + signal ex4_lt016 :std_ulogic ;--sticky + signal ex4_lt032 :std_ulogic ;--sticky + signal ex4_lt048 :std_ulogic ;--sticky + signal ex4_lt064 :std_ulogic ;--sticky + signal ex4_lt080 :std_ulogic ;--sticky + signal ex4_lt096 :std_ulogic ;--sticky + signal ex4_lt112 :std_ulogic ;--sticky + signal ex4_lt128 :std_ulogic ;--sticky + signal ex4_lt04_x :std_ulogic ;--sticky + signal ex4_lt08_x :std_ulogic ;--sticky + signal ex4_lt12_x :std_ulogic ;--sticky + signal ex4_lt01_x :std_ulogic ;--sticky + signal ex4_lt02_x :std_ulogic ;--sticky + signal ex4_lt03_x :std_ulogic ;--sticky + signal ex4_sticky_sp :std_ulogic ;--sticky + signal ex4_sticky_dp :std_ulogic ;--sticky + signal ex4_sticky16_dp :std_ulogic ;--sticky + signal ex4_sticky16_sp :std_ulogic ;--sticky + signal ex4_or_grp16 :std_ulogic_vector(0 to 10) ;--sticky + signal ex4_lt :std_ulogic_vector(0 to 14) ;--sticky + signal ex4_exact_zero :std_ulogic ;--sticky + signal ex4_exact_zero_b :std_ulogic ;--sticky + -------------------- + signal ex5_res :std_ulogic_vector(0 to 52); -- LATCH OUTPUTS + signal ex5_nrm_sticky_dp :std_ulogic; + signal ex5_nrm_guard_dp :std_ulogic; + signal ex5_nrm_lsb_dp :std_ulogic; + signal ex5_nrm_sticky_sp :std_ulogic; + signal ex5_nrm_guard_sp :std_ulogic; + signal ex5_nrm_lsb_sp :std_ulogic; + signal ex5_exact_zero :std_ulogic; + signal ex5_int_sign :std_ulogic; + signal ex5_int_lsbs :std_ulogic_vector(1 to 12); + signal ex5_fpscr_wr_dat :std_ulogic_vector(0 to 31); + signal ex5_fpscr_wr_dat_dfp :std_ulogic_vector(0 to 3); + signal ex4_rgt_4more, ex4_rgt_3more, ex4_rgt_2more :std_ulogic; + signal ex4_shift_extra_cp2 :std_ulogic; + signal unused :std_ulogic; + + signal ex4_sticky_dp_x2_b, ex4_sticky_dp_x1_b, ex4_sticky_dp_x1 :std_ulogic; + signal ex4_sticky_sp_x2_b, ex4_sticky_sp_x1_b, ex4_sticky_sp_x1 :std_ulogic; + signal ex5_d1clk, ex5_d2clk :std_ulogic ; + signal ex5_lclk :clk_logic; + signal ex4_sticky_stuff :std_ulogic ; + + + + +begin + + unused <= or_reduce( ex4_sh2(41 to 54) ) or -- sticky bit sp/dp does not look at all the bits + or_reduce( ex4_nrm_res(0 to 53) ) or + ex4_sticky_sp or + ex4_sticky_dp or + ex4_exact_zero ; + +--//############################################ +--# pervasive +--//############################################ + + + thold_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => thold_1, + q(0) => thold_0 ); + + sg_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => sg_1 , + q(0) => sg_0 ); + + + lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map ( + clkoff_b => clkoff_b, + thold => thold_0, + sg => sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => thold_0_b ); + + ex5_lcb : tri_lcbnd generic map (expand_type => expand_type) port map( + delay_lclkr => delay_lclkr(5) ,-- tidn + mpw1_b => mpw1_b(5) ,-- tidn + mpw2_b => mpw2_b(1) ,-- tidn + forcee => forcee,-- tidn + nclk => nclk ,--in + vd => vdd ,--inout + gd => gnd ,--inout + act => ex4_act ,--in + sg => sg_0 ,--in + thold_b => thold_0_b ,--in + d1clk => ex5_d1clk ,--out + d2clk => ex5_d2clk ,--out + lclk => ex5_lclk );--out + + + + +--//############################################ +--# ACT LATCHES +--//############################################ + + ex3_act <= not ex3_act_b ; + + act_lat: tri_rlmreg_p generic map (width=> 4, expand_type => expand_type, needs_sreset => 0) port map ( + forcee => forcee,--i-- tidn, + delay_lclkr => delay_lclkr(4) ,--i-- tidn, + mpw1_b => mpw1_b(4) ,--i-- tidn, + mpw2_b => mpw2_b(0) ,--i-- tidn, + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => fpu_enable, + scout => act_so (0 to 3), + scin => act_si (0 to 3), + ------------------- + din(0) => act_spare_unused(0), + din(1) => act_spare_unused(1), + din(2) => ex3_act, + din(3) => act_spare_unused(2), + ------------------- + dout(0) => act_spare_unused(0), + dout(1) => act_spare_unused(1), + dout(2) => ex4_act, + dout(3) => act_spare_unused(2) ); + +--//############################################## +--# EX4 logic: shifting +--//############################################## + + sh: entity work.fuq_nrm_sh(fuq_nrm_sh) generic map (expand_type => expand_type) port map( + f_lza_ex4_sh_rgt_en => f_lza_ex4_sh_rgt_en ,--i-- + f_lza_ex4_lza_amt_cp1(2 to 7) => f_lza_ex4_lza_amt_cp1(2 to 7) ,--i-- + f_lza_ex4_lza_dcd64_cp1(0 to 2) => f_lza_ex4_lza_dcd64_cp1(0 to 2) ,--i-- + f_lza_ex4_lza_dcd64_cp2(0 to 1) => f_lza_ex4_lza_dcd64_cp2(0 to 1) ,--i-- + f_lza_ex4_lza_dcd64_cp3(0 to 0) => f_lza_ex4_lza_dcd64_cp3(0 to 0) ,--i-- + f_add_ex4_res(0 to 162) => f_add_ex4_res(0 to 162) ,--i-- + ex4_shift_extra_cp1 => f_nrm_ex4_extra_shift ,--o-- <30ish> loads feov + ex4_shift_extra_cp2 => ex4_shift_extra_cp2 ,--o-- <2> loads sticky sp/dp + ex4_sh4_25 => ex4_sh4_25 ,--o-- + ex4_sh4_54 => ex4_sh4_54 ,--o-- + ex4_sh2_o(26 to 72) => ex4_sh2(26 to 72) ,--o-- + ex4_sh5_x_b(0 to 53) => ex4_sh5_x_b(0 to 53) ,--o-- + ex4_sh5_y_b(0 to 53) => ex4_sh5_y_b(0 to 53) );--o-- + + ex4_nrm_res(0 to 53) <= not( ex4_sh5_x_b(0 to 53) and ex4_sh5_y_b(0 to 53) ) ; -- unused SIM_ONLY + +--//############################################## +--# EX4 logic: stciky bit +--//############################################## + + --# thermometer decode 1 --------------- + --# + --# the smaller the shift the more sticky bits. + --# the multiple of 16 shifter is 0:68 ... bits after 68 are known sticky DP. + --# 53-24=29 extra sp bits 68-29 = 39 + --# bits after 39 are known sticky SP. + + ex4_lt064_x <= not( f_lza_ex4_lza_amt_cp1(0) or f_lza_ex4_lza_amt_cp1(1) ); -- 00 + ex4_lt128_x <= not( f_lza_ex4_lza_amt_cp1(0) ); -- 00 01 + + ex4_lt016_x <= not( f_lza_ex4_lza_amt_cp1(2) or f_lza_ex4_lza_amt_cp1(3) ); -- 00 + ex4_lt032_x <= not( f_lza_ex4_lza_amt_cp1(2) ); -- 00 01 + ex4_lt048_x <= not( f_lza_ex4_lza_amt_cp1(2) and f_lza_ex4_lza_amt_cp1(3) ); -- 00 01 10 + + ex4_lt016 <= ex4_lt064_x and ex4_lt016_x ; --tail=067 sticky_dp=069:162 sticky_sp=039:162 + ex4_lt032 <= ex4_lt064_x and ex4_lt032_x ; --tail=083 sticky_dp=085:162 sticky_sp=055:162 + ex4_lt048 <= ex4_lt064_x and ex4_lt048_x ; --tail=099 sticky_dp=101:162 sticky_sp=071:162 + ex4_lt064 <= ex4_lt064_x ; --tail=115 sticky_dp=117:162 sticky_sp=087:162 + ex4_lt080 <= ex4_lt064_x or (ex4_lt128_x and ex4_lt016_x); --tail=131 sticky_dp=133:162 sticky_sp=103:162 + ex4_lt096 <= ex4_lt064_x or (ex4_lt128_x and ex4_lt032_x); --tail=147 sticky_dp=149:162 sticky_sp=119:162 + ex4_lt112 <= ex4_lt064_x or (ex4_lt128_x and ex4_lt048_x); --tail=163 sticky_dp=xxxxxxx sticky_sp=135:162 + ex4_lt128 <= ex4_lt128_x ; --tail=179 sticky_dp=xxxxxxx sticky_sp=151:162 + + + -- 1111xxxx shift right 1 -> 16 (shift right sticky groups of 16 may be off by one from shift left sticky groups) + -- 1110xxxx shift right 17 -> 32 + -- 1101xxxx shift right 33 -> 48 + -- 1100xxxx shift right 49 -> 64 + -- x0xxxxxx shift > 64 + -- 0xxxxxxx shift > 64 + + + -- for shift right Amt[0]==Amt[1]==shRgtEn + -- xx00_dddd Right64, then Left00 4 more sticky16 group than 0000_dddd + -- xx01_dddd Right64, then Left16 3 more sticky16 group than 0000_dddd + -- xx10_dddd Right64, then Left32 2 more sticky16 group than 0000_dddd + -- xx11_dddd Right64, then Left48 1 more sticky16 group than 0000_dddd + + + ex4_rgt_2more <= f_lza_ex4_sh_rgt_en and ( not f_lza_ex4_lza_amt_cp1(2) or not f_lza_ex4_lza_amt_cp1(3) ); -- 234 + ex4_rgt_3more <= f_lza_ex4_sh_rgt_en and ( not f_lza_ex4_lza_amt_cp1(2) ); -- 23 + ex4_rgt_4more <= f_lza_ex4_sh_rgt_en and ( not f_lza_ex4_lza_amt_cp1(2) and not f_lza_ex4_lza_amt_cp1(3) ); -- 2 + + + + --#------------------------ + --# sticky group 16 ors + --#------------------------ + + or16: entity work.fuq_nrm_or16(fuq_nrm_or16) generic map (expand_type => expand_type) port map( + f_add_ex4_res(0 to 162) => f_add_ex4_res(0 to 162) ,--i-- + ex4_or_grp16(0 to 10) => ex4_or_grp16(0 to 10) );--o-- + + --#------------------------ + --# enable the 16 bit ors + --#------------------------ + + + ex4_sticky_stuff <= + ( f_pic_ex4_byp_prod_nz ) or + ( f_add_ex4_sticky ) ; + + ex4_sticky16_dp <= + ( ex4_or_grp16(1) and ex4_rgt_4more ) or + ( ex4_or_grp16(2) and ex4_rgt_3more ) or + ( ex4_or_grp16(3) and ex4_rgt_2more ) or + ( ex4_or_grp16(4) and f_lza_ex4_sh_rgt_en ) or + ( ex4_or_grp16(5) and (ex4_lt016 or f_lza_ex4_sh_rgt_en) ) or -- 71: 86 + ( ex4_or_grp16(6) and (ex4_lt032 or f_lza_ex4_sh_rgt_en) ) or -- 87:102 + ( ex4_or_grp16(7) and (ex4_lt048 or f_lza_ex4_sh_rgt_en) ) or --103:118 + ( ex4_or_grp16(8) and (ex4_lt064 or f_lza_ex4_sh_rgt_en) ) or --119:134 + ( ex4_or_grp16(9) and (ex4_lt080 or f_lza_ex4_sh_rgt_en) ) or --135:150 + ( ex4_or_grp16(10) and (ex4_lt096 or f_lza_ex4_sh_rgt_en) ) or --151:162 + ( ex4_sh2(70) ) or -- so group16s match for sp/dp + ( ex4_sh2(71) ) or -- so group16s match for sp/dp + ( ex4_sh2(72) ) or -- so group16s match for sp/dp + ( ex4_sticky_stuff ) ; + + ex4_sticky16_sp <= + ( ex4_or_grp16(0) and ex4_rgt_3more ) or + ( ex4_or_grp16(1) and ex4_rgt_2more ) or + ( ex4_or_grp16(2) and f_lza_ex4_sh_rgt_en ) or + ( ex4_or_grp16(3) and (ex4_lt016 or f_lza_ex4_sh_rgt_en) ) or -- 39: 54 + ( ex4_or_grp16(4) and (ex4_lt032 or f_lza_ex4_sh_rgt_en) ) or -- 55: 70 + ( ex4_or_grp16(5) and (ex4_lt048 or f_lza_ex4_sh_rgt_en) ) or -- 71: 86 + ( ex4_or_grp16(6) and (ex4_lt064 or f_lza_ex4_sh_rgt_en) ) or -- 87:102 + ( ex4_or_grp16(7) and (ex4_lt080 or f_lza_ex4_sh_rgt_en) ) or --103:118 + ( ex4_or_grp16(8) and (ex4_lt096 or f_lza_ex4_sh_rgt_en) ) or --119:134 + ( ex4_or_grp16(9) and (ex4_lt112 or f_lza_ex4_sh_rgt_en) ) or --135:150 + ( ex4_or_grp16(10) and (ex4_lt128 or f_lza_ex4_sh_rgt_en) ) or --151:162 + ( ex4_sticky_stuff ) ; + + ex4_exact_zero_b <= + ex4_or_grp16(0) or + ex4_or_grp16(1) or + ex4_or_grp16(2) or + ex4_or_grp16(3) or + ex4_or_grp16(4) or + ex4_or_grp16(5) or + ex4_or_grp16(6) or + ex4_or_grp16(7) or + ex4_or_grp16(8) or + ex4_or_grp16(9) or + ex4_or_grp16(10) or + ( ex4_sticky_stuff ) ; + + + ex4_exact_zero <= not ex4_exact_zero_b ; + + --#------------------------ + --# thermometer decode 2 + --#------------------------ + + ex4_lt04_x <= not( f_lza_ex4_lza_amt_cp1(4) or f_lza_ex4_lza_amt_cp1(5) ); -- 00 + ex4_lt08_x <= not( f_lza_ex4_lza_amt_cp1(4) ); -- 00 01 + ex4_lt12_x <= not( f_lza_ex4_lza_amt_cp1(4) and f_lza_ex4_lza_amt_cp1(5) ); -- 00 01 10 + + ex4_lt01_x <= not( f_lza_ex4_lza_amt_cp1(6) or f_lza_ex4_lza_amt_cp1(7) ); -- 00 + ex4_lt02_x <= not( f_lza_ex4_lza_amt_cp1(6) ); -- 00 01 + ex4_lt03_x <= not( f_lza_ex4_lza_amt_cp1(6) and f_lza_ex4_lza_amt_cp1(7) ); -- 00 01 10 + + ex4_lt(0) <= ex4_lt04_x and ex4_lt01_x ; -- 1 + ex4_lt(1) <= ex4_lt04_x and ex4_lt02_x ; -- 2 + ex4_lt(2) <= ex4_lt04_x and ex4_lt03_x ; -- 3 + ex4_lt(3) <= ex4_lt04_x ; -- 4 + + ex4_lt(4) <= ex4_lt04_x or (ex4_lt08_x and ex4_lt01_x); -- 5 + ex4_lt(5) <= ex4_lt04_x or (ex4_lt08_x and ex4_lt02_x); -- 6 + ex4_lt(6) <= ex4_lt04_x or (ex4_lt08_x and ex4_lt03_x); -- 7 + ex4_lt(7) <= (ex4_lt08_x ); -- 8 + + ex4_lt(8) <= ex4_lt08_x or (ex4_lt12_x and ex4_lt01_x); -- 9 + ex4_lt(9) <= ex4_lt08_x or (ex4_lt12_x and ex4_lt02_x); --10 + ex4_lt(10) <= ex4_lt08_x or (ex4_lt12_x and ex4_lt03_x); --11 + ex4_lt(11) <= (ex4_lt12_x ); --12 + + ex4_lt(12) <= ex4_lt12_x or ex4_lt01_x ; --13 + ex4_lt(13) <= ex4_lt12_x or ex4_lt02_x ; --14 + ex4_lt(14) <= ex4_lt12_x or ex4_lt03_x ; --15 + + --#------------------------ + --# final sticky bits + --#------------------------ + + ex4_sticky_sp_x1 <= + (ex4_lt(14) and ex4_sh2(40) ) or -- lt 01 + (ex4_lt(13) and ex4_sh2(39) ) or -- lt 02 + (ex4_lt(12) and ex4_sh2(38) ) or -- lt 03 + (ex4_lt(11) and ex4_sh2(37) ) or -- lt 04 + (ex4_lt(10) and ex4_sh2(36) ) or -- lt 05 + (ex4_lt(9) and ex4_sh2(35) ) or -- lt 06 + (ex4_lt(8) and ex4_sh2(34) ) or -- lt 07 + (ex4_lt(7) and ex4_sh2(33) ) or -- lt 08 + (ex4_lt(6) and ex4_sh2(32) ) or -- lt 09 + (ex4_lt(5) and ex4_sh2(31) ) or -- lt 10 + (ex4_lt(4) and ex4_sh2(30) ) or -- lt 11 + (ex4_lt(3) and ex4_sh2(29) ) or -- lt 12 + (ex4_lt(2) and ex4_sh2(28) ) or -- lt 13 + (ex4_lt(1) and ex4_sh2(27) ) or -- lt 14 + (ex4_lt(0) and ex4_sh2(26) ) or -- lt 15 + (ex4_sticky16_sp ) ; + + + ex4_sticky_sp_x2_b <= not(not ex4_shift_extra_cp2 and ex4_sh4_25 ); + ex4_sticky_sp_x1_b <= not ex4_sticky_sp_x1 ; + ex4_sticky_sp <= not( ex4_sticky_sp_x1_b and ex4_sticky_sp_x2_b ); + + + + + ex4_sticky_dp_x1 <= + (ex4_lt(14) and ex4_sh2(69) ) or -- lt 01 + (ex4_lt(13) and ex4_sh2(68) ) or -- lt 02 + (ex4_lt(12) and ex4_sh2(67) ) or -- lt 03 + (ex4_lt(11) and ex4_sh2(66) ) or -- lt 04 + (ex4_lt(10) and ex4_sh2(65) ) or -- lt 05 + (ex4_lt(9) and ex4_sh2(64) ) or -- lt 06 + (ex4_lt(8) and ex4_sh2(63) ) or -- lt 07 + (ex4_lt(7) and ex4_sh2(62) ) or -- lt 08 + (ex4_lt(6) and ex4_sh2(61) ) or -- lt 09 + (ex4_lt(5) and ex4_sh2(60) ) or -- lt 10 + (ex4_lt(4) and ex4_sh2(59) ) or -- lt 11 + (ex4_lt(3) and ex4_sh2(58) ) or -- lt 12 + (ex4_lt(2) and ex4_sh2(57) ) or -- lt 13 + (ex4_lt(1) and ex4_sh2(56) ) or -- lt 14 + (ex4_lt(0) and ex4_sh2(55) ) or -- lt 15 + (ex4_sticky16_dp ) ; + + ex4_sticky_dp_x2_b <= not(not ex4_shift_extra_cp2 and ex4_sh4_54 ) ; + ex4_sticky_dp_x1_b <= not ex4_sticky_dp_x1 ; + ex4_sticky_dp <= not( ex4_sticky_dp_x1_b and ex4_sticky_dp_x2_b ); + + + + + + ex5_res_lat: entity tri.tri_nand2_nlats(tri_nand2_nlats) generic map (width=> 53, btr => "NLA0001_X1_A12TH", expand_type => expand_type, needs_sreset => 0) port map ( + vd => vdd, + gd => gnd, + LCLK => ex5_lclk ,--lclk.clk + D1CLK => ex5_d1clk , + D2CLK => ex5_d2clk , + SCANIN => ex5_res_si , + SCANOUT => ex5_res_so , + A1 => ex4_sh5_x_b(0 to 52) , + A2 => ex4_sh5_y_b(0 to 52) , + QB => ex5_res(0 to 52) );--LAT-- + + ex5_nrm_lg_lat: entity tri.tri_nand2_nlats(tri_nand2_nlats) generic map (width=> 4, btr => "NLA0001_X1_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd, + gd => gnd, + LCLK => ex5_lclk ,--lclk.clk + D1CLK => ex5_d1clk , + D2CLK => ex5_d2clk , + SCANIN => ex5_nrm_lg_si , + SCANOUT => ex5_nrm_lg_so , + ------------------- + A1(0) => ex4_sh5_x_b(23) , + A1(1) => ex4_sh5_x_b(24) , + A1(2) => ex4_sh5_x_b(52) , + A1(3) => ex4_sh5_x_b(53) , + ------------------- + A2(0) => ex4_sh5_y_b(23) , + A2(1) => ex4_sh5_y_b(24) , + A2(2) => ex4_sh5_y_b(52) , + A2(3) => ex4_sh5_y_b(53) , + ------------------- + QB(0) => ex5_nrm_lsb_sp ,--LAT-- --sp lsb + QB(1) => ex5_nrm_guard_sp ,--LAT-- --sp guard + QB(2) => ex5_nrm_lsb_dp ,--LAT-- --dp lsb + QB(3) => ex5_nrm_guard_dp );--LAT-- --dp guard + + + + + + ex5_nrm_x_lat: entity tri.tri_nand2_nlats(tri_nand2_nlats) generic map (width=> 3, btr => "NLA0001_X1_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd, + gd => gnd, + LCLK => ex5_lclk ,--lclk.clk + D1CLK => ex5_d1clk , + D2CLK => ex5_d2clk , + SCANIN => ex5_nrm_x_si , + SCANOUT => ex5_nrm_x_so , + ------------------- + A1(0) => ex4_sticky_sp_x2_b , + A1(1) => ex4_sticky_dp_x2_b , + A1(2) => ex4_exact_zero_b , + ------------------- + A2(0) => ex4_sticky_sp_x1_b , + A2(1) => ex4_sticky_dp_x1_b , + A2(2) => tiup , + ------------------- + QB(0) => ex5_nrm_sticky_sp ,--LAT-- + QB(1) => ex5_nrm_sticky_dp ,--LAT-- + QB(2) => ex5_exact_zero );--LAT-- + + ex5_nrm_pass_lat: tri_rlmreg_p generic map (width=> 13, expand_type => expand_type, ibuf => true, needs_sreset => 0) port map ( + forcee => forcee,--i-- tidn, + delay_lclkr => delay_lclkr(5) ,--i-- tidn, + mpw1_b => mpw1_b(5) ,--i-- tidn, + mpw2_b => mpw2_b(1) ,--i-- tidn, + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => ex4_act, + scout => ex5_nrm_pass_so, + scin => ex5_nrm_pass_si, + ------------------- + din(0) => f_add_ex4_res(99) , + din(1 to 12) => f_add_ex4_res(151 to 162) , -- (151:162) + ------------------- + dout(0) => ex5_int_sign ,--LAT-- + dout(1 to 12) => ex5_int_lsbs (1 to 12) );--LAT-- --(151:162) + + ex5_fmv_lat: tri_rlmreg_p generic map (width=> 36, expand_type => expand_type, ibuf => true, needs_sreset => 1) port map ( + forcee => forcee,--i-- tidn, + delay_lclkr => delay_lclkr(5) ,--i-- tidn, + mpw1_b => mpw1_b(5) ,--i-- tidn, + mpw2_b => mpw2_b(1) ,--i-- tidn, + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => ex4_act, + scout => ex5_fmv_so , + scin => ex5_fmv_si , + ------------------- + din => f_add_ex4_res(17 to 52) ,--LAT + ------------------- + dout(0 to 3) => ex5_fpscr_wr_dat_dfp(0 to 3) , + dout(4 to 35) => ex5_fpscr_wr_dat(0 to 31) );--LAT + + + + f_nrm_ex5_res <= ex5_res(0 to 52) ;--output--rnd + f_nrm_ex5_nrm_lsb_sp <= ex5_nrm_lsb_sp ;--output--rnd + f_nrm_ex5_nrm_guard_sp <= ex5_nrm_guard_sp ;--output--rnd + f_nrm_ex5_nrm_sticky_sp <= ex5_nrm_sticky_sp ;--output--rnd + f_nrm_ex5_nrm_lsb_dp <= ex5_nrm_lsb_dp ;--output--rnd + f_nrm_ex5_nrm_guard_dp <= ex5_nrm_guard_dp ;--output--rnd + f_nrm_ex5_nrm_sticky_dp <= ex5_nrm_sticky_dp ;--output--rnd + f_nrm_ex5_exact_zero <= ex5_exact_zero ;--output--rnd + f_nrm_ex5_int_lsbs <= ex5_int_lsbs (1 to 12) ;--output--rnd (151:162) + f_nrm_ex5_fpscr_wr_dat <= ex5_fpscr_wr_dat(0 to 31) ;--output--fpscr, (21:52) + f_nrm_ex5_fpscr_wr_dat_dfp <= ex5_fpscr_wr_dat_dfp(0 to 3) ;--output--fpscr (17:20) + f_nrm_ex5_int_sign <= ex5_int_sign ;--output--rnd (151:162) + + +--//############################################ +--# scan +--//############################################ + + act_si (0 to 3) <= act_so (1 to 3) & f_nrm_si; + ex5_res_si (0 to 52) <= ex5_res_so (1 to 52) & act_so(0) ; + ex5_nrm_lg_si(0 to 3) <= ex5_nrm_lg_so(1 to 3) & ex5_res_so(0); + ex5_nrm_x_si(0 to 2) <= ex5_nrm_x_so(1 to 2) & ex5_nrm_lg_so(0); + ex5_nrm_pass_si(0 to 12) <= ex5_nrm_pass_so(1 to 12) & ex5_nrm_x_so(0); + ex5_fmv_si (0 to 35) <= ex5_fmv_so (1 to 35) & ex5_nrm_pass_so(0); + f_nrm_so <= ex5_fmv_so (0) ; + + + +end; -- fuq_nrm ARCHITECTURE diff --git a/rel/src/vhdl/work/fuq_nrm_or16.vhdl b/rel/src/vhdl/work/fuq_nrm_or16.vhdl new file mode 100644 index 0000000..ed06eff --- /dev/null +++ b/rel/src/vhdl/work/fuq_nrm_or16.vhdl @@ -0,0 +1,331 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + + +entity fuq_nrm_or16 is +generic( expand_type : integer := 2 ); -- 0 - ibm tech, 1 - other ); +port( + f_add_ex4_res :in std_ulogic_vector(0 to 162) ; + ex4_or_grp16 :out std_ulogic_vector(0 to 10) +); + + + +end fuq_nrm_or16; -- ENTITY + +architecture fuq_nrm_or16 of fuq_nrm_or16 is + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + +signal ex4_res_b :std_ulogic_vector(0 to 162); +signal g00_or02 :std_ulogic_vector(0 to 3); +signal g01_or02, g02_or02, g03_or02, g04_or02, g05_or02, g06_or02, g07_or02, g08_or02, g09_or02 :std_ulogic_vector(0 to 7); +signal g10_or02 :std_ulogic_vector(0 to 5); + +signal g00_or04_b :std_ulogic_vector(0 to 1); +signal g01_or04_b :std_ulogic_vector(0 to 3); +signal g02_or04_b :std_ulogic_vector(0 to 3); +signal g03_or04_b :std_ulogic_vector(0 to 3); +signal g04_or04_b :std_ulogic_vector(0 to 3); +signal g05_or04_b :std_ulogic_vector(0 to 3); +signal g06_or04_b :std_ulogic_vector(0 to 3); +signal g07_or04_b :std_ulogic_vector(0 to 3); +signal g08_or04_b :std_ulogic_vector(0 to 3); +signal g09_or04_b :std_ulogic_vector(0 to 3); +signal g10_or04_b :std_ulogic_vector(0 to 2); + + +signal g00_or08 :std_ulogic_vector(0 to 0); +signal g01_or08 :std_ulogic_vector(0 to 1); +signal g02_or08 :std_ulogic_vector(0 to 1); +signal g03_or08 :std_ulogic_vector(0 to 1); +signal g04_or08 :std_ulogic_vector(0 to 1); +signal g05_or08 :std_ulogic_vector(0 to 1); +signal g06_or08 :std_ulogic_vector(0 to 1); +signal g07_or08 :std_ulogic_vector(0 to 1); +signal g08_or08 :std_ulogic_vector(0 to 1); +signal g09_or08 :std_ulogic_vector(0 to 1); +signal g10_or08 :std_ulogic_vector(0 to 1); + +signal g00_or16_b :std_ulogic ; +signal g01_or16_b :std_ulogic ; +signal g02_or16_b :std_ulogic ; +signal g03_or16_b :std_ulogic ; +signal g04_or16_b :std_ulogic ; +signal g05_or16_b :std_ulogic ; +signal g06_or16_b :std_ulogic ; +signal g07_or16_b :std_ulogic ; +signal g08_or16_b :std_ulogic ; +signal g09_or16_b :std_ulogic ; +signal g10_or16_b :std_ulogic ; + + + + + + + + + +begin + +--===============================================================-- + + +u_or_inv: ex4_res_b(0 to 162) <= not f_add_ex4_res(0 to 162); -- small + +--===============================================================-- + + +u_g00_or02_0: g00_or02(0) <= not( ex4_res_b( 0) and ex4_res_b( 1) ); +u_g00_or02_1: g00_or02(1) <= not( ex4_res_b( 2) and ex4_res_b( 3) ); +u_g00_or02_2: g00_or02(2) <= not( ex4_res_b( 4) and ex4_res_b( 5) ); +u_g00_or02_3: g00_or02(3) <= not( ex4_res_b( 6) and ex4_res_b( 7) ); + +u_g01_or02_0: g01_or02(0) <= not( ex4_res_b( 8) and ex4_res_b( 9) ); +u_g01_or02_1: g01_or02(1) <= not( ex4_res_b( 10) and ex4_res_b( 11) ); +u_g01_or02_2: g01_or02(2) <= not( ex4_res_b( 12) and ex4_res_b( 13) ); +u_g01_or02_3: g01_or02(3) <= not( ex4_res_b( 14) and ex4_res_b( 15) ); +u_g01_or02_4: g01_or02(4) <= not( ex4_res_b( 16) and ex4_res_b( 17) ); +u_g01_or02_5: g01_or02(5) <= not( ex4_res_b( 18) and ex4_res_b( 19) ); +u_g01_or02_6: g01_or02(6) <= not( ex4_res_b( 20) and ex4_res_b( 21) ); +u_g01_or02_7: g01_or02(7) <= not( ex4_res_b( 22) and ex4_res_b( 23) ); + +u_g02_or02_0: g02_or02(0) <= not( ex4_res_b( 24) and ex4_res_b( 25) ); +u_g02_or02_1: g02_or02(1) <= not( ex4_res_b( 26) and ex4_res_b( 27) ); +u_g02_or02_2: g02_or02(2) <= not( ex4_res_b( 28) and ex4_res_b( 29) ); +u_g02_or02_3: g02_or02(3) <= not( ex4_res_b( 30) and ex4_res_b( 31) ); +u_g02_or02_4: g02_or02(4) <= not( ex4_res_b( 32) and ex4_res_b( 33) ); +u_g02_or02_5: g02_or02(5) <= not( ex4_res_b( 34) and ex4_res_b( 35) ); +u_g02_or02_6: g02_or02(6) <= not( ex4_res_b( 36) and ex4_res_b( 37) ); +u_g02_or02_7: g02_or02(7) <= not( ex4_res_b( 38) and ex4_res_b( 39) ); + +u_g03_or02_0: g03_or02(0) <= not( ex4_res_b( 40) and ex4_res_b( 41) ); +u_g03_or02_1: g03_or02(1) <= not( ex4_res_b( 42) and ex4_res_b( 43) ); +u_g03_or02_2: g03_or02(2) <= not( ex4_res_b( 44) and ex4_res_b( 45) ); +u_g03_or02_3: g03_or02(3) <= not( ex4_res_b( 46) and ex4_res_b( 47) ); +u_g03_or02_4: g03_or02(4) <= not( ex4_res_b( 48) and ex4_res_b( 49) ); +u_g03_or02_5: g03_or02(5) <= not( ex4_res_b( 50) and ex4_res_b( 51) ); +u_g03_or02_6: g03_or02(6) <= not( ex4_res_b( 52) and ex4_res_b( 53) ); +u_g03_or02_7: g03_or02(7) <= not( ex4_res_b( 54) and ex4_res_b( 55) ); + +u_g04_or02_0: g04_or02(0) <= not( ex4_res_b( 56) and ex4_res_b( 57) ); +u_g04_or02_1: g04_or02(1) <= not( ex4_res_b( 58) and ex4_res_b( 59) ); +u_g04_or02_2: g04_or02(2) <= not( ex4_res_b( 60) and ex4_res_b( 61) ); +u_g04_or02_3: g04_or02(3) <= not( ex4_res_b( 62) and ex4_res_b( 63) ); +u_g04_or02_4: g04_or02(4) <= not( ex4_res_b( 64) and ex4_res_b( 65) ); +u_g04_or02_5: g04_or02(5) <= not( ex4_res_b( 66) and ex4_res_b( 67) ); +u_g04_or02_6: g04_or02(6) <= not( ex4_res_b( 68) and ex4_res_b( 69) ); +u_g04_or02_7: g04_or02(7) <= not( ex4_res_b( 70) and ex4_res_b( 71) ); + +u_g05_or02_0: g05_or02(0) <= not( ex4_res_b( 72) and ex4_res_b( 73) ); +u_g05_or02_1: g05_or02(1) <= not( ex4_res_b( 74) and ex4_res_b( 75) ); +u_g05_or02_2: g05_or02(2) <= not( ex4_res_b( 76) and ex4_res_b( 77) ); +u_g05_or02_3: g05_or02(3) <= not( ex4_res_b( 78) and ex4_res_b( 79) ); +u_g05_or02_4: g05_or02(4) <= not( ex4_res_b( 80) and ex4_res_b( 81) ); +u_g05_or02_5: g05_or02(5) <= not( ex4_res_b( 82) and ex4_res_b( 83) ); +u_g05_or02_6: g05_or02(6) <= not( ex4_res_b( 84) and ex4_res_b( 85) ); +u_g05_or02_7: g05_or02(7) <= not( ex4_res_b( 86) and ex4_res_b( 87) ); + +u_g06_or02_0: g06_or02(0) <= not( ex4_res_b( 88) and ex4_res_b( 89) ); +u_g06_or02_1: g06_or02(1) <= not( ex4_res_b( 90) and ex4_res_b( 91) ); +u_g06_or02_2: g06_or02(2) <= not( ex4_res_b( 92) and ex4_res_b( 93) ); +u_g06_or02_3: g06_or02(3) <= not( ex4_res_b( 94) and ex4_res_b( 95) ); +u_g06_or02_4: g06_or02(4) <= not( ex4_res_b( 96) and ex4_res_b( 97) ); +u_g06_or02_5: g06_or02(5) <= not( ex4_res_b( 98) and ex4_res_b( 99) ); +u_g06_or02_6: g06_or02(6) <= not( ex4_res_b(100) and ex4_res_b(101) ); +u_g06_or02_7: g06_or02(7) <= not( ex4_res_b(102) and ex4_res_b(103) ); + +u_g07_or02_0: g07_or02(0) <= not( ex4_res_b(104) and ex4_res_b(105) ); +u_g07_or02_1: g07_or02(1) <= not( ex4_res_b(106) and ex4_res_b(107) ); +u_g07_or02_2: g07_or02(2) <= not( ex4_res_b(108) and ex4_res_b(109) ); +u_g07_or02_3: g07_or02(3) <= not( ex4_res_b(110) and ex4_res_b(111) ); +u_g07_or02_4: g07_or02(4) <= not( ex4_res_b(112) and ex4_res_b(113) ); +u_g07_or02_5: g07_or02(5) <= not( ex4_res_b(114) and ex4_res_b(115) ); +u_g07_or02_6: g07_or02(6) <= not( ex4_res_b(116) and ex4_res_b(117) ); +u_g07_or02_7: g07_or02(7) <= not( ex4_res_b(118) and ex4_res_b(119) ); + +u_g08_or02_0: g08_or02(0) <= not( ex4_res_b(120) and ex4_res_b(121) ); +u_g08_or02_1: g08_or02(1) <= not( ex4_res_b(122) and ex4_res_b(123) ); +u_g08_or02_2: g08_or02(2) <= not( ex4_res_b(124) and ex4_res_b(125) ); +u_g08_or02_3: g08_or02(3) <= not( ex4_res_b(126) and ex4_res_b(127) ); +u_g08_or02_4: g08_or02(4) <= not( ex4_res_b(128) and ex4_res_b(129) ); +u_g08_or02_5: g08_or02(5) <= not( ex4_res_b(130) and ex4_res_b(131) ); +u_g08_or02_6: g08_or02(6) <= not( ex4_res_b(132) and ex4_res_b(133) ); +u_g08_or02_7: g08_or02(7) <= not( ex4_res_b(134) and ex4_res_b(135) ); + +u_g09_or02_0: g09_or02(0) <= not( ex4_res_b(136) and ex4_res_b(137) ); +u_g09_or02_1: g09_or02(1) <= not( ex4_res_b(138) and ex4_res_b(139) ); +u_g09_or02_2: g09_or02(2) <= not( ex4_res_b(140) and ex4_res_b(141) ); +u_g09_or02_3: g09_or02(3) <= not( ex4_res_b(142) and ex4_res_b(143) ); +u_g09_or02_4: g09_or02(4) <= not( ex4_res_b(144) and ex4_res_b(145) ); +u_g09_or02_5: g09_or02(5) <= not( ex4_res_b(146) and ex4_res_b(147) ); +u_g09_or02_6: g09_or02(6) <= not( ex4_res_b(148) and ex4_res_b(149) ); +u_g09_or02_7: g09_or02(7) <= not( ex4_res_b(150) and ex4_res_b(151) ); + +u_g10_or02_0: g10_or02(0) <= not( ex4_res_b(152) and ex4_res_b(153) ); +u_g10_or02_1: g10_or02(1) <= not( ex4_res_b(154) and ex4_res_b(155) ); +u_g10_or02_2: g10_or02(2) <= not( ex4_res_b(156) and ex4_res_b(157) ); +u_g10_or02_3: g10_or02(3) <= not( ex4_res_b(158) and ex4_res_b(159) ); +u_g10_or02_4: g10_or02(4) <= not( ex4_res_b(160) and ex4_res_b(161) ); +u_g10_or02_5: g10_or02(5) <= not( ex4_res_b(162) ); + +--===============================================================-- + +u_g00_or04_0: g00_or04_b(0) <= not( g00_or02(0) or g00_or02(1) ); +u_g00_or04_1: g00_or04_b(1) <= not( g00_or02(2) or g00_or02(3) ); + +u_g01_or04_0: g01_or04_b(0) <= not( g01_or02(0) or g01_or02(1) ); +u_g01_or04_1: g01_or04_b(1) <= not( g01_or02(2) or g01_or02(3) ); +u_g01_or04_2: g01_or04_b(2) <= not( g01_or02(4) or g01_or02(5) ); +u_g01_or04_3: g01_or04_b(3) <= not( g01_or02(6) or g01_or02(7) ); + +u_g02_or04_0: g02_or04_b(0) <= not( g02_or02(0) or g02_or02(1) ); +u_g02_or04_1: g02_or04_b(1) <= not( g02_or02(2) or g02_or02(3) ); +u_g02_or04_2: g02_or04_b(2) <= not( g02_or02(4) or g02_or02(5) ); +u_g02_or04_3: g02_or04_b(3) <= not( g02_or02(6) or g02_or02(7) ); + +u_g03_or04_0: g03_or04_b(0) <= not( g03_or02(0) or g03_or02(1) ); +u_g03_or04_1: g03_or04_b(1) <= not( g03_or02(2) or g03_or02(3) ); +u_g03_or04_2: g03_or04_b(2) <= not( g03_or02(4) or g03_or02(5) ); +u_g03_or04_3: g03_or04_b(3) <= not( g03_or02(6) or g03_or02(7) ); + +u_g04_or04_0: g04_or04_b(0) <= not( g04_or02(0) or g04_or02(1) ); +u_g04_or04_1: g04_or04_b(1) <= not( g04_or02(2) or g04_or02(3) ); +u_g04_or04_2: g04_or04_b(2) <= not( g04_or02(4) or g04_or02(5) ); +u_g04_or04_3: g04_or04_b(3) <= not( g04_or02(6) or g04_or02(7) ); + +u_g05_or04_0: g05_or04_b(0) <= not( g05_or02(0) or g05_or02(1) ); +u_g05_or04_1: g05_or04_b(1) <= not( g05_or02(2) or g05_or02(3) ); +u_g05_or04_2: g05_or04_b(2) <= not( g05_or02(4) or g05_or02(5) ); +u_g05_or04_3: g05_or04_b(3) <= not( g05_or02(6) or g05_or02(7) ); + +u_g06_or04_0: g06_or04_b(0) <= not( g06_or02(0) or g06_or02(1) ); +u_g06_or04_1: g06_or04_b(1) <= not( g06_or02(2) or g06_or02(3) ); +u_g06_or04_2: g06_or04_b(2) <= not( g06_or02(4) or g06_or02(5) ); +u_g06_or04_3: g06_or04_b(3) <= not( g06_or02(6) or g06_or02(7) ); + +u_g07_or04_0: g07_or04_b(0) <= not( g07_or02(0) or g07_or02(1) ); +u_g07_or04_1: g07_or04_b(1) <= not( g07_or02(2) or g07_or02(3) ); +u_g07_or04_2: g07_or04_b(2) <= not( g07_or02(4) or g07_or02(5) ); +u_g07_or04_3: g07_or04_b(3) <= not( g07_or02(6) or g07_or02(7) ); + +u_g08_or04_0: g08_or04_b(0) <= not( g08_or02(0) or g08_or02(1) ); +u_g08_or04_1: g08_or04_b(1) <= not( g08_or02(2) or g08_or02(3) ); +u_g08_or04_2: g08_or04_b(2) <= not( g08_or02(4) or g08_or02(5) ); +u_g08_or04_3: g08_or04_b(3) <= not( g08_or02(6) or g08_or02(7) ); + +u_g09_or04_0: g09_or04_b(0) <= not( g09_or02(0) or g09_or02(1) ); +u_g09_or04_1: g09_or04_b(1) <= not( g09_or02(2) or g09_or02(3) ); +u_g09_or04_2: g09_or04_b(2) <= not( g09_or02(4) or g09_or02(5) ); +u_g09_or04_3: g09_or04_b(3) <= not( g09_or02(6) or g09_or02(7) ); + +u_g10_or04_0: g10_or04_b(0) <= not( g10_or02(0) or g10_or02(1) ); +u_g10_or04_1: g10_or04_b(1) <= not( g10_or02(2) or g10_or02(3) ); +u_g10_or04_2: g10_or04_b(2) <= not( g10_or02(4) or g10_or02(5) ); + + + +u_g00_or08_0: g00_or08(0) <= not( g00_or04_b(0) and g00_or04_b(1) ); + +u_g01_or08_0: g01_or08(0) <= not( g01_or04_b(0) and g01_or04_b(1) ); +u_g01_or08_1: g01_or08(1) <= not( g01_or04_b(2) and g01_or04_b(3) ); + +u_g02_or08_0: g02_or08(0) <= not( g02_or04_b(0) and g02_or04_b(1) ); +u_g02_or08_1: g02_or08(1) <= not( g02_or04_b(2) and g02_or04_b(3) ); + +u_g03_or08_0: g03_or08(0) <= not( g03_or04_b(0) and g03_or04_b(1) ); +u_g03_or08_1: g03_or08(1) <= not( g03_or04_b(2) and g03_or04_b(3) ); + +u_g04_or08_0: g04_or08(0) <= not( g04_or04_b(0) and g04_or04_b(1) ); +u_g04_or08_1: g04_or08(1) <= not( g04_or04_b(2) and g04_or04_b(3) ); + +u_g05_or08_0: g05_or08(0) <= not( g05_or04_b(0) and g05_or04_b(1) ); +u_g05_or08_1: g05_or08(1) <= not( g05_or04_b(2) and g05_or04_b(3) ); + +u_g06_or08_0: g06_or08(0) <= not( g06_or04_b(0) and g06_or04_b(1) ); +u_g06_or08_1: g06_or08(1) <= not( g06_or04_b(2) and g06_or04_b(3) ); + +u_g07_or08_0: g07_or08(0) <= not( g07_or04_b(0) and g07_or04_b(1) ); +u_g07_or08_1: g07_or08(1) <= not( g07_or04_b(2) and g07_or04_b(3) ); + +u_g08_or08_0: g08_or08(0) <= not( g08_or04_b(0) and g08_or04_b(1) ); +u_g08_or08_1: g08_or08(1) <= not( g08_or04_b(2) and g08_or04_b(3) ); + +u_g09_or08_0: g09_or08(0) <= not( g09_or04_b(0) and g09_or04_b(1) ); +u_g09_or08_1: g09_or08(1) <= not( g09_or04_b(2) and g09_or04_b(3) ); + +u_g10_or08_0: g10_or08(0) <= not( g10_or04_b(0) and g10_or04_b(1) ); +u_g10_or08_1: g10_or08(1) <= not( g10_or04_b(2) ); + + +--===============================================================-- + +u_g00_or16_0: g00_or16_b <= not( g00_or08(0) ); +u_g01_or16_0: g01_or16_b <= not( g01_or08(0) or g01_or08(1) ); +u_g02_or16_0: g02_or16_b <= not( g02_or08(0) or g02_or08(1) ); +u_g03_or16_0: g03_or16_b <= not( g03_or08(0) or g03_or08(1) ); +u_g04_or16_0: g04_or16_b <= not( g04_or08(0) or g04_or08(1) ); +u_g05_or16_0: g05_or16_b <= not( g05_or08(0) or g05_or08(1) ); +u_g06_or16_0: g06_or16_b <= not( g06_or08(0) or g06_or08(1) ); +u_g07_or16_0: g07_or16_b <= not( g07_or08(0) or g07_or08(1) ); +u_g08_or16_0: g08_or16_b <= not( g08_or08(0) or g08_or08(1) ); +u_g09_or16_0: g09_or16_b <= not( g09_or08(0) or g09_or08(1) ); +u_g10_or16_0: g10_or16_b <= not( g10_or08(0) or g10_or08(1) ); + +--===============================================================-- + + +--/////////////////////////////////////////////////////////-- + +u_g00_drv: ex4_or_grp16(0) <= not( g00_or16_b ); --output-- +u_g01_drv: ex4_or_grp16(1) <= not( g01_or16_b ); --output-- +u_g02_drv: ex4_or_grp16(2) <= not( g02_or16_b ); --output-- +u_g03_drv: ex4_or_grp16(3) <= not( g03_or16_b ); --output-- +u_g04_drv: ex4_or_grp16(4) <= not( g04_or16_b ); --output-- +u_g05_drv: ex4_or_grp16(5) <= not( g05_or16_b ); --output-- +u_g06_drv: ex4_or_grp16(6) <= not( g06_or16_b ); --output-- +u_g07_drv: ex4_or_grp16(7) <= not( g07_or16_b ); --output-- +u_g08_drv: ex4_or_grp16(8) <= not( g08_or16_b ); --output-- +u_g09_drv: ex4_or_grp16(9) <= not( g09_or16_b ); --output-- +u_g10_drv: ex4_or_grp16(10) <= not( g10_or16_b ); --output-- + +end; -- fuq_nrm_or16 ARCHITECTURE diff --git a/rel/src/vhdl/work/fuq_nrm_sh.vhdl b/rel/src/vhdl/work/fuq_nrm_sh.vhdl new file mode 100644 index 0000000..7885d93 --- /dev/null +++ b/rel/src/vhdl/work/fuq_nrm_sh.vhdl @@ -0,0 +1,1322 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + + +entity fuq_nrm_sh is +generic( expand_type : integer := 2 ); -- 0 - ibm tech, 1 - other ); +port( + ----------- SHIFT CONTROLS ----------------- + f_lza_ex4_sh_rgt_en :in std_ulogic; + f_lza_ex4_lza_amt_cp1 :in std_ulogic_vector(2 to 7) ; + f_lza_ex4_lza_dcd64_cp1 :in std_ulogic_vector(0 to 2) ; + f_lza_ex4_lza_dcd64_cp2 :in std_ulogic_vector(0 to 1) ; + f_lza_ex4_lza_dcd64_cp3 :in std_ulogic_vector(0 to 0) ; + + ----------- SHIFT DATA ----------------- + f_add_ex4_res :in std_ulogic_vector(0 to 162) ; + + ---------- SHIFT OUTPUT --------------- + ex4_sh2_o :out std_ulogic_vector(26 to 72); + ex4_sh4_25 :out std_ulogic; + ex4_sh4_54 :out std_ulogic; + ex4_shift_extra_cp1 :out std_ulogic ; + ex4_shift_extra_cp2 :out std_ulogic ; + ex4_sh5_x_b :out std_ulogic_vector(0 to 53); + ex4_sh5_y_b :out std_ulogic_vector(0 to 53) +); + + + + + +end fuq_nrm_sh; -- ENTITY + +architecture fuq_nrm_sh of fuq_nrm_sh is + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal ex4_sh1_x_b :std_ulogic_vector(0 to 120); + signal ex4_sh1_y_b :std_ulogic_vector(0 to 99); + signal ex4_sh1_u_b :std_ulogic_vector(0 to 35); + signal ex4_sh1_z_b :std_ulogic_vector(65 to 118); + signal ex4_sh2_x_b, ex4_sh2_y_b :std_ulogic_vector(0 to 72); + signal ex4_sh3_x_b, ex4_sh3_y_b :std_ulogic_vector(0 to 57); + signal ex4_sh4_x_b, ex4_sh4_y_b :std_ulogic_vector(0 to 54); + signal ex4_sh4_x_00_b, ex4_sh4_y_00_b :std_ulogic; + signal ex4_shift_extra_cp1_b :std_ulogic ; + signal ex4_shift_extra_cp2_b :std_ulogic ; + signal ex4_shift_extra_cp3_b :std_ulogic ; + signal ex4_shift_extra_cp4_b :std_ulogic ; + signal ex4_shift_extra_cp3 :std_ulogic ; + signal ex4_shift_extra_cp4 :std_ulogic ; + signal ex4_sh4 :std_ulogic_vector(0 to 54); + signal ex4_sh3 :std_ulogic_vector(0 to 57); + signal ex4_sh2 :std_ulogic_vector(0 to 72); + signal ex4_sh1 :std_ulogic_vector(0 to 120); + signal ex4_shctl_64 :std_ulogic_vector(0 to 2); + signal ex4_shctl_64_cp2 :std_ulogic_vector(0 to 1); + signal ex4_shctl_64_cp3 :std_ulogic_vector(0 to 0); + signal ex4_shctl_16 :std_ulogic_vector(0 to 3); + signal ex4_shctl_04 :std_ulogic_vector(0 to 3); + signal ex4_shctl_01 :std_ulogic_vector(0 to 3); + signal ex4_shift_extra_10_cp3 :std_ulogic; + signal ex4_shift_extra_20_cp3_b :std_ulogic; + signal ex4_shift_extra_11_cp3 :std_ulogic; + signal ex4_shift_extra_21_cp3_b :std_ulogic; + signal ex4_shift_extra_31_cp3 :std_ulogic; + signal ex4_shift_extra_10_cp4 :std_ulogic; + signal ex4_shift_extra_20_cp4_b :std_ulogic; + signal ex4_shift_extra_11_cp4 :std_ulogic; + signal ex4_shift_extra_21_cp4_b :std_ulogic; + signal ex4_shift_extra_31_cp4 :std_ulogic; + signal ex4_shift_extra_00_cp3_b :std_ulogic; + signal ex4_shift_extra_00_cp4_b :std_ulogic; + +begin + + +--//############################################## +--# EX4 logic: shift decode +--//############################################## + + ex4_shctl_64(0 to 2) <= f_lza_ex4_lza_dcd64_cp1(0 to 2) ; + ex4_shctl_64_cp2(0 to 1) <= f_lza_ex4_lza_dcd64_cp2(0 to 1) ; + ex4_shctl_64_cp3(0) <= f_lza_ex4_lza_dcd64_cp3(0) ; + + ex4_shctl_16(0) <= not f_lza_ex4_lza_amt_cp1(2) and not f_lza_ex4_lza_amt_cp1(3) ; --SH000 + ex4_shctl_16(1) <= not f_lza_ex4_lza_amt_cp1(2) and f_lza_ex4_lza_amt_cp1(3) ; --SH016 + ex4_shctl_16(2) <= f_lza_ex4_lza_amt_cp1(2) and not f_lza_ex4_lza_amt_cp1(3) ; --SH032 + ex4_shctl_16(3) <= f_lza_ex4_lza_amt_cp1(2) and f_lza_ex4_lza_amt_cp1(3) ; --SH048 + + ex4_shctl_04(0) <= not f_lza_ex4_lza_amt_cp1(4) and not f_lza_ex4_lza_amt_cp1(5) ; --SH000 + ex4_shctl_04(1) <= not f_lza_ex4_lza_amt_cp1(4) and f_lza_ex4_lza_amt_cp1(5) ; --SH004 + ex4_shctl_04(2) <= f_lza_ex4_lza_amt_cp1(4) and not f_lza_ex4_lza_amt_cp1(5) ; --SH008 + ex4_shctl_04(3) <= f_lza_ex4_lza_amt_cp1(4) and f_lza_ex4_lza_amt_cp1(5) ; --SH012 + + ex4_shctl_01(0) <= not f_lza_ex4_lza_amt_cp1(6) and not f_lza_ex4_lza_amt_cp1(7) ; --SH000 + ex4_shctl_01(1) <= not f_lza_ex4_lza_amt_cp1(6) and f_lza_ex4_lza_amt_cp1(7) ; --SH001 + ex4_shctl_01(2) <= f_lza_ex4_lza_amt_cp1(6) and not f_lza_ex4_lza_amt_cp1(7) ; --SH002 + ex4_shctl_01(3) <= f_lza_ex4_lza_amt_cp1(6) and f_lza_ex4_lza_amt_cp1(7) ; --SH003 + +--//############################################## +--# EX4 logic: shifting +--//############################################## + --//## big shifts first (come sooner from LZA, + --//## when shift amount is [0] we need to start out with a "dummy" leading bit to sacrifice for shift_extra + + ex4_sh2_o(26 to 72) <= ex4_sh2(26 to 72); -- for sticky bit + + ex4_sh4_25 <= ex4_sh4(25) ; -- for sticky bit + ex4_sh4_54 <= ex4_sh4(54) ; -- for sticky bit + + + + +--------------------------------------------------------- +u_sh1x_000: ex4_sh1_x_b( 0) <= not( tidn and ex4_shctl_64(0) ); +u_sh1x_001: ex4_sh1_x_b( 1) <= not( f_add_ex4_res( 0) and ex4_shctl_64(0) ); +u_sh1x_002: ex4_sh1_x_b( 2) <= not( f_add_ex4_res( 1) and ex4_shctl_64(0) ); +u_sh1x_003: ex4_sh1_x_b( 3) <= not( f_add_ex4_res( 2) and ex4_shctl_64(0) ); +u_sh1x_004: ex4_sh1_x_b( 4) <= not( f_add_ex4_res( 3) and ex4_shctl_64(0) ); +u_sh1x_005: ex4_sh1_x_b( 5) <= not( f_add_ex4_res( 4) and ex4_shctl_64(0) ); +u_sh1x_006: ex4_sh1_x_b( 6) <= not( f_add_ex4_res( 5) and ex4_shctl_64(0) ); +u_sh1x_007: ex4_sh1_x_b( 7) <= not( f_add_ex4_res( 6) and ex4_shctl_64(0) ); +u_sh1x_008: ex4_sh1_x_b( 8) <= not( f_add_ex4_res( 7) and ex4_shctl_64(0) ); +u_sh1x_009: ex4_sh1_x_b( 9) <= not( f_add_ex4_res( 8) and ex4_shctl_64(0) ); +u_sh1x_010: ex4_sh1_x_b( 10) <= not( f_add_ex4_res( 9) and ex4_shctl_64(0) ); +u_sh1x_011: ex4_sh1_x_b( 11) <= not( f_add_ex4_res( 10) and ex4_shctl_64(0) ); +u_sh1x_012: ex4_sh1_x_b( 12) <= not( f_add_ex4_res( 11) and ex4_shctl_64(0) ); +u_sh1x_013: ex4_sh1_x_b( 13) <= not( f_add_ex4_res( 12) and ex4_shctl_64(0) ); +u_sh1x_014: ex4_sh1_x_b( 14) <= not( f_add_ex4_res( 13) and ex4_shctl_64(0) ); +u_sh1x_015: ex4_sh1_x_b( 15) <= not( f_add_ex4_res( 14) and ex4_shctl_64(0) ); +u_sh1x_016: ex4_sh1_x_b( 16) <= not( f_add_ex4_res( 15) and ex4_shctl_64(0) ); +u_sh1x_017: ex4_sh1_x_b( 17) <= not( f_add_ex4_res( 16) and ex4_shctl_64(0) ); +u_sh1x_018: ex4_sh1_x_b( 18) <= not( f_add_ex4_res( 17) and ex4_shctl_64(0) ); +u_sh1x_019: ex4_sh1_x_b( 19) <= not( f_add_ex4_res( 18) and ex4_shctl_64(0) ); +u_sh1x_020: ex4_sh1_x_b( 20) <= not( f_add_ex4_res( 19) and ex4_shctl_64(0) ); +u_sh1x_021: ex4_sh1_x_b( 21) <= not( f_add_ex4_res( 20) and ex4_shctl_64(0) ); +u_sh1x_022: ex4_sh1_x_b( 22) <= not( f_add_ex4_res( 21) and ex4_shctl_64(0) ); +u_sh1x_023: ex4_sh1_x_b( 23) <= not( f_add_ex4_res( 22) and ex4_shctl_64(0) ); +u_sh1x_024: ex4_sh1_x_b( 24) <= not( f_add_ex4_res( 23) and ex4_shctl_64(0) ); +u_sh1x_025: ex4_sh1_x_b( 25) <= not( f_add_ex4_res( 24) and ex4_shctl_64(0) ); +u_sh1x_026: ex4_sh1_x_b( 26) <= not( f_add_ex4_res( 25) and ex4_shctl_64(0) ); +u_sh1x_027: ex4_sh1_x_b( 27) <= not( f_add_ex4_res( 26) and ex4_shctl_64(0) ); +u_sh1x_028: ex4_sh1_x_b( 28) <= not( f_add_ex4_res( 27) and ex4_shctl_64(0) ); +u_sh1x_029: ex4_sh1_x_b( 29) <= not( f_add_ex4_res( 28) and ex4_shctl_64(0) ); +u_sh1x_030: ex4_sh1_x_b( 30) <= not( f_add_ex4_res( 29) and ex4_shctl_64(0) ); +u_sh1x_031: ex4_sh1_x_b( 31) <= not( f_add_ex4_res( 30) and ex4_shctl_64(0) ); +u_sh1x_032: ex4_sh1_x_b( 32) <= not( f_add_ex4_res( 31) and ex4_shctl_64(0) ); +u_sh1x_033: ex4_sh1_x_b( 33) <= not( f_add_ex4_res( 32) and ex4_shctl_64(0) ); +u_sh1x_034: ex4_sh1_x_b( 34) <= not( f_add_ex4_res( 33) and ex4_shctl_64(0) ); +u_sh1x_035: ex4_sh1_x_b( 35) <= not( f_add_ex4_res( 34) and ex4_shctl_64(0) ); +u_sh1x_036: ex4_sh1_x_b( 36) <= not( f_add_ex4_res( 35) and ex4_shctl_64(0) ); +u_sh1x_037: ex4_sh1_x_b( 37) <= not( f_add_ex4_res( 36) and ex4_shctl_64(0) ); +u_sh1x_038: ex4_sh1_x_b( 38) <= not( f_add_ex4_res( 37) and ex4_shctl_64(0) ); +u_sh1x_039: ex4_sh1_x_b( 39) <= not( f_add_ex4_res( 38) and ex4_shctl_64(0) ); +u_sh1x_040: ex4_sh1_x_b( 40) <= not( f_add_ex4_res( 39) and ex4_shctl_64_cp2(0) );---------- +u_sh1x_041: ex4_sh1_x_b( 41) <= not( f_add_ex4_res( 40) and ex4_shctl_64_cp2(0) ); +u_sh1x_042: ex4_sh1_x_b( 42) <= not( f_add_ex4_res( 41) and ex4_shctl_64_cp2(0) ); +u_sh1x_043: ex4_sh1_x_b( 43) <= not( f_add_ex4_res( 42) and ex4_shctl_64_cp2(0) ); +u_sh1x_044: ex4_sh1_x_b( 44) <= not( f_add_ex4_res( 43) and ex4_shctl_64_cp2(0) ); +u_sh1x_045: ex4_sh1_x_b( 45) <= not( f_add_ex4_res( 44) and ex4_shctl_64_cp2(0) ); +u_sh1x_046: ex4_sh1_x_b( 46) <= not( f_add_ex4_res( 45) and ex4_shctl_64_cp2(0) ); +u_sh1x_047: ex4_sh1_x_b( 47) <= not( f_add_ex4_res( 46) and ex4_shctl_64_cp2(0) ); +u_sh1x_048: ex4_sh1_x_b( 48) <= not( f_add_ex4_res( 47) and ex4_shctl_64_cp2(0) ); +u_sh1x_049: ex4_sh1_x_b( 49) <= not( f_add_ex4_res( 48) and ex4_shctl_64_cp2(0) ); +u_sh1x_050: ex4_sh1_x_b( 50) <= not( f_add_ex4_res( 49) and ex4_shctl_64_cp2(0) ); +u_sh1x_051: ex4_sh1_x_b( 51) <= not( f_add_ex4_res( 50) and ex4_shctl_64_cp2(0) ); +u_sh1x_052: ex4_sh1_x_b( 52) <= not( f_add_ex4_res( 51) and ex4_shctl_64_cp2(0) ); +u_sh1x_053: ex4_sh1_x_b( 53) <= not( f_add_ex4_res( 52) and ex4_shctl_64_cp2(0) ); +u_sh1x_054: ex4_sh1_x_b( 54) <= not( f_add_ex4_res( 53) and ex4_shctl_64_cp2(0) ); +u_sh1x_055: ex4_sh1_x_b( 55) <= not( f_add_ex4_res( 54) and ex4_shctl_64_cp2(0) ); +u_sh1x_056: ex4_sh1_x_b( 56) <= not( f_add_ex4_res( 55) and ex4_shctl_64_cp2(0) ); +u_sh1x_057: ex4_sh1_x_b( 57) <= not( f_add_ex4_res( 56) and ex4_shctl_64_cp2(0) ); +u_sh1x_058: ex4_sh1_x_b( 58) <= not( f_add_ex4_res( 57) and ex4_shctl_64_cp2(0) ); +u_sh1x_059: ex4_sh1_x_b( 59) <= not( f_add_ex4_res( 58) and ex4_shctl_64_cp2(0) ); +u_sh1x_060: ex4_sh1_x_b( 60) <= not( f_add_ex4_res( 59) and ex4_shctl_64_cp2(0) ); +u_sh1x_061: ex4_sh1_x_b( 61) <= not( f_add_ex4_res( 60) and ex4_shctl_64_cp2(0) ); +u_sh1x_062: ex4_sh1_x_b( 62) <= not( f_add_ex4_res( 61) and ex4_shctl_64_cp2(0) ); +u_sh1x_063: ex4_sh1_x_b( 63) <= not( f_add_ex4_res( 62) and ex4_shctl_64_cp2(0) ); +u_sh1x_064: ex4_sh1_x_b( 64) <= not( f_add_ex4_res( 63) and ex4_shctl_64_cp2(0) ); +u_sh1x_065: ex4_sh1_x_b( 65) <= not( f_add_ex4_res( 64) and ex4_shctl_64_cp2(0) ); +u_sh1x_066: ex4_sh1_x_b( 66) <= not( f_add_ex4_res( 65) and ex4_shctl_64_cp2(0) ); +u_sh1x_067: ex4_sh1_x_b( 67) <= not( f_add_ex4_res( 66) and ex4_shctl_64_cp2(0) ); +u_sh1x_068: ex4_sh1_x_b( 68) <= not( f_add_ex4_res( 67) and ex4_shctl_64_cp2(0) ); +u_sh1x_069: ex4_sh1_x_b( 69) <= not( f_add_ex4_res( 68) and ex4_shctl_64_cp2(0) ); +u_sh1x_070: ex4_sh1_x_b( 70) <= not( f_add_ex4_res( 69) and ex4_shctl_64_cp2(0) ); +u_sh1x_071: ex4_sh1_x_b( 71) <= not( f_add_ex4_res( 70) and ex4_shctl_64_cp2(0) ); +u_sh1x_072: ex4_sh1_x_b( 72) <= not( f_add_ex4_res( 71) and ex4_shctl_64_cp2(0) ); +u_sh1x_073: ex4_sh1_x_b( 73) <= not( f_add_ex4_res( 72) and ex4_shctl_64_cp2(0) ); +u_sh1x_074: ex4_sh1_x_b( 74) <= not( f_add_ex4_res( 73) and ex4_shctl_64_cp2(0) ); +u_sh1x_075: ex4_sh1_x_b( 75) <= not( f_add_ex4_res( 74) and ex4_shctl_64_cp2(0) ); +u_sh1x_076: ex4_sh1_x_b( 76) <= not( f_add_ex4_res( 75) and ex4_shctl_64_cp2(0) ); +u_sh1x_077: ex4_sh1_x_b( 77) <= not( f_add_ex4_res( 76) and ex4_shctl_64_cp2(0) ); +u_sh1x_078: ex4_sh1_x_b( 78) <= not( f_add_ex4_res( 77) and ex4_shctl_64_cp2(0) ); +u_sh1x_079: ex4_sh1_x_b( 79) <= not( f_add_ex4_res( 78) and ex4_shctl_64_cp2(0) ); +u_sh1x_080: ex4_sh1_x_b( 80) <= not( f_add_ex4_res( 79) and ex4_shctl_64_cp2(0) ); +u_sh1x_081: ex4_sh1_x_b( 81) <= not( f_add_ex4_res( 80) and ex4_shctl_64_cp3(0) );------ +u_sh1x_082: ex4_sh1_x_b( 82) <= not( f_add_ex4_res( 81) and ex4_shctl_64_cp3(0) ); +u_sh1x_083: ex4_sh1_x_b( 83) <= not( f_add_ex4_res( 82) and ex4_shctl_64_cp3(0) ); +u_sh1x_084: ex4_sh1_x_b( 84) <= not( f_add_ex4_res( 83) and ex4_shctl_64_cp3(0) ); +u_sh1x_085: ex4_sh1_x_b( 85) <= not( f_add_ex4_res( 84) and ex4_shctl_64_cp3(0) ); +u_sh1x_086: ex4_sh1_x_b( 86) <= not( f_add_ex4_res( 85) and ex4_shctl_64_cp3(0) ); +u_sh1x_087: ex4_sh1_x_b( 87) <= not( f_add_ex4_res( 86) and ex4_shctl_64_cp3(0) ); +u_sh1x_088: ex4_sh1_x_b( 88) <= not( f_add_ex4_res( 87) and ex4_shctl_64_cp3(0) ); +u_sh1x_089: ex4_sh1_x_b( 89) <= not( f_add_ex4_res( 88) and ex4_shctl_64_cp3(0) ); +u_sh1x_090: ex4_sh1_x_b( 90) <= not( f_add_ex4_res( 89) and ex4_shctl_64_cp3(0) ); +u_sh1x_091: ex4_sh1_x_b( 91) <= not( f_add_ex4_res( 90) and ex4_shctl_64_cp3(0) ); +u_sh1x_092: ex4_sh1_x_b( 92) <= not( f_add_ex4_res( 91) and ex4_shctl_64_cp3(0) ); +u_sh1x_093: ex4_sh1_x_b( 93) <= not( f_add_ex4_res( 92) and ex4_shctl_64_cp3(0) ); +u_sh1x_094: ex4_sh1_x_b( 94) <= not( f_add_ex4_res( 93) and ex4_shctl_64_cp3(0) ); +u_sh1x_095: ex4_sh1_x_b( 95) <= not( f_add_ex4_res( 94) and ex4_shctl_64_cp3(0) ); +u_sh1x_096: ex4_sh1_x_b( 96) <= not( f_add_ex4_res( 95) and ex4_shctl_64_cp3(0) ); +u_sh1x_097: ex4_sh1_x_b( 97) <= not( f_add_ex4_res( 96) and ex4_shctl_64_cp3(0) ); +u_sh1x_098: ex4_sh1_x_b( 98) <= not( f_add_ex4_res( 97) and ex4_shctl_64_cp3(0) ); +u_sh1x_099: ex4_sh1_x_b( 99) <= not( f_add_ex4_res( 98) and ex4_shctl_64_cp3(0) ); +u_sh1x_100: ex4_sh1_x_b(100) <= not( f_add_ex4_res( 99) and ex4_shctl_64_cp3(0) ); +u_sh1x_101: ex4_sh1_x_b(101) <= not( f_add_ex4_res(100) and ex4_shctl_64_cp3(0) ); +u_sh1x_102: ex4_sh1_x_b(102) <= not( f_add_ex4_res(101) and ex4_shctl_64_cp3(0) ); +u_sh1x_103: ex4_sh1_x_b(103) <= not( f_add_ex4_res(102) and ex4_shctl_64_cp3(0) ); +u_sh1x_104: ex4_sh1_x_b(104) <= not( f_add_ex4_res(103) and ex4_shctl_64_cp3(0) ); +u_sh1x_105: ex4_sh1_x_b(105) <= not( f_add_ex4_res(104) and ex4_shctl_64_cp3(0) ); +u_sh1x_106: ex4_sh1_x_b(106) <= not( f_add_ex4_res(105) and ex4_shctl_64_cp3(0) ); +u_sh1x_107: ex4_sh1_x_b(107) <= not( f_add_ex4_res(106) and ex4_shctl_64_cp3(0) ); +u_sh1x_108: ex4_sh1_x_b(108) <= not( f_add_ex4_res(107) and ex4_shctl_64_cp3(0) ); +u_sh1x_109: ex4_sh1_x_b(109) <= not( f_add_ex4_res(108) and ex4_shctl_64_cp3(0) ); +u_sh1x_110: ex4_sh1_x_b(110) <= not( f_add_ex4_res(109) and ex4_shctl_64_cp3(0) ); +u_sh1x_111: ex4_sh1_x_b(111) <= not( f_add_ex4_res(110) and ex4_shctl_64_cp3(0) ); +u_sh1x_112: ex4_sh1_x_b(112) <= not( f_add_ex4_res(111) and ex4_shctl_64_cp3(0) ); +u_sh1x_113: ex4_sh1_x_b(113) <= not( f_add_ex4_res(112) and ex4_shctl_64_cp3(0) ); +u_sh1x_114: ex4_sh1_x_b(114) <= not( f_add_ex4_res(113) and ex4_shctl_64_cp3(0) ); +u_sh1x_115: ex4_sh1_x_b(115) <= not( f_add_ex4_res(114) and ex4_shctl_64_cp3(0) ); +u_sh1x_116: ex4_sh1_x_b(116) <= not( f_add_ex4_res(115) and ex4_shctl_64_cp3(0) ); +u_sh1x_117: ex4_sh1_x_b(117) <= not( f_add_ex4_res(116) and ex4_shctl_64_cp3(0) ); +u_sh1x_118: ex4_sh1_x_b(118) <= not( f_add_ex4_res(117) and ex4_shctl_64_cp3(0) ); +u_sh1x_119: ex4_sh1_x_b(119) <= not( f_add_ex4_res(118) and ex4_shctl_64_cp3(0) ); +u_sh1x_120: ex4_sh1_x_b(120) <= not( f_add_ex4_res(119) and ex4_shctl_64_cp3(0) ); + + +u_sh1y_000: ex4_sh1_y_b( 0) <= not( f_add_ex4_res( 63) and ex4_shctl_64(1) ); +u_sh1y_001: ex4_sh1_y_b( 1) <= not( f_add_ex4_res( 64) and ex4_shctl_64(1) ); +u_sh1y_002: ex4_sh1_y_b( 2) <= not( f_add_ex4_res( 65) and ex4_shctl_64(1) ); +u_sh1y_003: ex4_sh1_y_b( 3) <= not( f_add_ex4_res( 66) and ex4_shctl_64(1) ); +u_sh1y_004: ex4_sh1_y_b( 4) <= not( f_add_ex4_res( 67) and ex4_shctl_64(1) ); +u_sh1y_005: ex4_sh1_y_b( 5) <= not( f_add_ex4_res( 68) and ex4_shctl_64(1) ); +u_sh1y_006: ex4_sh1_y_b( 6) <= not( f_add_ex4_res( 69) and ex4_shctl_64(1) ); +u_sh1y_007: ex4_sh1_y_b( 7) <= not( f_add_ex4_res( 70) and ex4_shctl_64(1) ); +u_sh1y_008: ex4_sh1_y_b( 8) <= not( f_add_ex4_res( 71) and ex4_shctl_64(1) ); +u_sh1y_009: ex4_sh1_y_b( 9) <= not( f_add_ex4_res( 72) and ex4_shctl_64(1) ); +u_sh1y_010: ex4_sh1_y_b( 10) <= not( f_add_ex4_res( 73) and ex4_shctl_64(1) ); +u_sh1y_011: ex4_sh1_y_b( 11) <= not( f_add_ex4_res( 74) and ex4_shctl_64(1) ); +u_sh1y_012: ex4_sh1_y_b( 12) <= not( f_add_ex4_res( 75) and ex4_shctl_64(1) ); +u_sh1y_013: ex4_sh1_y_b( 13) <= not( f_add_ex4_res( 76) and ex4_shctl_64(1) ); +u_sh1y_014: ex4_sh1_y_b( 14) <= not( f_add_ex4_res( 77) and ex4_shctl_64(1) ); +u_sh1y_015: ex4_sh1_y_b( 15) <= not( f_add_ex4_res( 78) and ex4_shctl_64(1) ); +u_sh1y_016: ex4_sh1_y_b( 16) <= not( f_add_ex4_res( 79) and ex4_shctl_64(1) ); +u_sh1y_017: ex4_sh1_y_b( 17) <= not( f_add_ex4_res( 80) and ex4_shctl_64(1) ); +u_sh1y_018: ex4_sh1_y_b( 18) <= not( f_add_ex4_res( 81) and ex4_shctl_64(1) ); +u_sh1y_019: ex4_sh1_y_b( 19) <= not( f_add_ex4_res( 82) and ex4_shctl_64(1) ); +u_sh1y_020: ex4_sh1_y_b( 20) <= not( f_add_ex4_res( 83) and ex4_shctl_64(1) ); +u_sh1y_021: ex4_sh1_y_b( 21) <= not( f_add_ex4_res( 84) and ex4_shctl_64(1) ); +u_sh1y_022: ex4_sh1_y_b( 22) <= not( f_add_ex4_res( 85) and ex4_shctl_64(1) ); +u_sh1y_023: ex4_sh1_y_b( 23) <= not( f_add_ex4_res( 86) and ex4_shctl_64(1) ); +u_sh1y_024: ex4_sh1_y_b( 24) <= not( f_add_ex4_res( 87) and ex4_shctl_64(1) ); +u_sh1y_025: ex4_sh1_y_b( 25) <= not( f_add_ex4_res( 88) and ex4_shctl_64(1) ); +u_sh1y_026: ex4_sh1_y_b( 26) <= not( f_add_ex4_res( 89) and ex4_shctl_64(1) ); +u_sh1y_027: ex4_sh1_y_b( 27) <= not( f_add_ex4_res( 90) and ex4_shctl_64(1) ); +u_sh1y_028: ex4_sh1_y_b( 28) <= not( f_add_ex4_res( 91) and ex4_shctl_64(1) ); +u_sh1y_029: ex4_sh1_y_b( 29) <= not( f_add_ex4_res( 92) and ex4_shctl_64(1) ); +u_sh1y_030: ex4_sh1_y_b( 30) <= not( f_add_ex4_res( 93) and ex4_shctl_64(1) ); +u_sh1y_031: ex4_sh1_y_b( 31) <= not( f_add_ex4_res( 94) and ex4_shctl_64(1) ); +u_sh1y_032: ex4_sh1_y_b( 32) <= not( f_add_ex4_res( 95) and ex4_shctl_64(1) ); +u_sh1y_033: ex4_sh1_y_b( 33) <= not( f_add_ex4_res( 96) and ex4_shctl_64(1) ); +u_sh1y_034: ex4_sh1_y_b( 34) <= not( f_add_ex4_res( 97) and ex4_shctl_64(1) ); +u_sh1y_035: ex4_sh1_y_b( 35) <= not( f_add_ex4_res( 98) and ex4_shctl_64(1) ); +u_sh1y_036: ex4_sh1_y_b( 36) <= not( f_add_ex4_res( 99) and ex4_shctl_64(1) ); +u_sh1y_037: ex4_sh1_y_b( 37) <= not( f_add_ex4_res(100) and ex4_shctl_64(1) ); +u_sh1y_038: ex4_sh1_y_b( 38) <= not( f_add_ex4_res(101) and ex4_shctl_64(1) ); +u_sh1y_039: ex4_sh1_y_b( 39) <= not( f_add_ex4_res(102) and ex4_shctl_64(1) ); +u_sh1y_040: ex4_sh1_y_b( 40) <= not( f_add_ex4_res(103) and ex4_shctl_64(1) ); +u_sh1y_041: ex4_sh1_y_b( 41) <= not( f_add_ex4_res(104) and ex4_shctl_64(1) ); +u_sh1y_042: ex4_sh1_y_b( 42) <= not( f_add_ex4_res(105) and ex4_shctl_64(1) ); +u_sh1y_043: ex4_sh1_y_b( 43) <= not( f_add_ex4_res(106) and ex4_shctl_64(1) ); +u_sh1y_044: ex4_sh1_y_b( 44) <= not( f_add_ex4_res(107) and ex4_shctl_64(1) ); +u_sh1y_045: ex4_sh1_y_b( 45) <= not( f_add_ex4_res(108) and ex4_shctl_64(1) ); +u_sh1y_046: ex4_sh1_y_b( 46) <= not( f_add_ex4_res(109) and ex4_shctl_64(1) ); +u_sh1y_047: ex4_sh1_y_b( 47) <= not( f_add_ex4_res(110) and ex4_shctl_64(1) ); +u_sh1y_048: ex4_sh1_y_b( 48) <= not( f_add_ex4_res(111) and ex4_shctl_64(1) ); +u_sh1y_049: ex4_sh1_y_b( 49) <= not( f_add_ex4_res(112) and ex4_shctl_64(1) ); +u_sh1y_050: ex4_sh1_y_b( 50) <= not( f_add_ex4_res(113) and ex4_shctl_64(1) ); +u_sh1y_051: ex4_sh1_y_b( 51) <= not( f_add_ex4_res(114) and ex4_shctl_64(1) ); +u_sh1y_052: ex4_sh1_y_b( 52) <= not( f_add_ex4_res(115) and ex4_shctl_64(1) ); +u_sh1y_053: ex4_sh1_y_b( 53) <= not( f_add_ex4_res(116) and ex4_shctl_64(1) ); +u_sh1y_054: ex4_sh1_y_b( 54) <= not( f_add_ex4_res(117) and ex4_shctl_64(1) ); +u_sh1y_055: ex4_sh1_y_b( 55) <= not( f_add_ex4_res(118) and ex4_shctl_64_cp2(1) ); +u_sh1y_056: ex4_sh1_y_b( 56) <= not( f_add_ex4_res(119) and ex4_shctl_64_cp2(1) ); +u_sh1y_057: ex4_sh1_y_b( 57) <= not( f_add_ex4_res(120) and ex4_shctl_64_cp2(1) ); +u_sh1y_058: ex4_sh1_y_b( 58) <= not( f_add_ex4_res(121) and ex4_shctl_64_cp2(1) ); +u_sh1y_059: ex4_sh1_y_b( 59) <= not( f_add_ex4_res(122) and ex4_shctl_64_cp2(1) ); +u_sh1y_060: ex4_sh1_y_b( 60) <= not( f_add_ex4_res(123) and ex4_shctl_64_cp2(1) ); +u_sh1y_061: ex4_sh1_y_b( 61) <= not( f_add_ex4_res(124) and ex4_shctl_64_cp2(1) ); +u_sh1y_062: ex4_sh1_y_b( 62) <= not( f_add_ex4_res(125) and ex4_shctl_64_cp2(1) ); +u_sh1y_063: ex4_sh1_y_b( 63) <= not( f_add_ex4_res(126) and ex4_shctl_64_cp2(1) ); +u_sh1y_064: ex4_sh1_y_b( 64) <= not( f_add_ex4_res(127) and ex4_shctl_64_cp2(1) ); +u_sh1y_065: ex4_sh1_y_b( 65) <= not( f_add_ex4_res(128) and ex4_shctl_64_cp2(1) ); +u_sh1y_066: ex4_sh1_y_b( 66) <= not( f_add_ex4_res(129) and ex4_shctl_64_cp2(1) ); +u_sh1y_067: ex4_sh1_y_b( 67) <= not( f_add_ex4_res(130) and ex4_shctl_64_cp2(1) ); +u_sh1y_068: ex4_sh1_y_b( 68) <= not( f_add_ex4_res(131) and ex4_shctl_64_cp2(1) ); +u_sh1y_069: ex4_sh1_y_b( 69) <= not( f_add_ex4_res(132) and ex4_shctl_64_cp2(1) ); +u_sh1y_070: ex4_sh1_y_b( 70) <= not( f_add_ex4_res(133) and ex4_shctl_64_cp2(1) ); +u_sh1y_071: ex4_sh1_y_b( 71) <= not( f_add_ex4_res(134) and ex4_shctl_64_cp2(1) ); +u_sh1y_072: ex4_sh1_y_b( 72) <= not( f_add_ex4_res(135) and ex4_shctl_64_cp2(1) ); +u_sh1y_073: ex4_sh1_y_b( 73) <= not( f_add_ex4_res(136) and ex4_shctl_64_cp2(1) ); +u_sh1y_074: ex4_sh1_y_b( 74) <= not( f_add_ex4_res(137) and ex4_shctl_64_cp2(1) ); +u_sh1y_075: ex4_sh1_y_b( 75) <= not( f_add_ex4_res(138) and ex4_shctl_64_cp2(1) ); +u_sh1y_076: ex4_sh1_y_b( 76) <= not( f_add_ex4_res(139) and ex4_shctl_64_cp2(1) ); +u_sh1y_077: ex4_sh1_y_b( 77) <= not( f_add_ex4_res(140) and ex4_shctl_64_cp2(1) ); +u_sh1y_078: ex4_sh1_y_b( 78) <= not( f_add_ex4_res(141) and ex4_shctl_64_cp2(1) ); +u_sh1y_079: ex4_sh1_y_b( 79) <= not( f_add_ex4_res(142) and ex4_shctl_64_cp2(1) ); +u_sh1y_080: ex4_sh1_y_b( 80) <= not( f_add_ex4_res(143) and ex4_shctl_64_cp2(1) ); +u_sh1y_081: ex4_sh1_y_b( 81) <= not( f_add_ex4_res(144) and ex4_shctl_64_cp2(1) ); +u_sh1y_082: ex4_sh1_y_b( 82) <= not( f_add_ex4_res(145) and ex4_shctl_64_cp2(1) ); +u_sh1y_083: ex4_sh1_y_b( 83) <= not( f_add_ex4_res(146) and ex4_shctl_64_cp2(1) ); +u_sh1y_084: ex4_sh1_y_b( 84) <= not( f_add_ex4_res(147) and ex4_shctl_64_cp2(1) ); +u_sh1y_085: ex4_sh1_y_b( 85) <= not( f_add_ex4_res(148) and ex4_shctl_64_cp2(1) ); +u_sh1y_086: ex4_sh1_y_b( 86) <= not( f_add_ex4_res(149) and ex4_shctl_64_cp2(1) ); +u_sh1y_087: ex4_sh1_y_b( 87) <= not( f_add_ex4_res(150) and ex4_shctl_64_cp2(1) ); +u_sh1y_088: ex4_sh1_y_b( 88) <= not( f_add_ex4_res(151) and ex4_shctl_64_cp2(1) ); +u_sh1y_089: ex4_sh1_y_b( 89) <= not( f_add_ex4_res(152) and ex4_shctl_64_cp2(1) ); +u_sh1y_090: ex4_sh1_y_b( 90) <= not( f_add_ex4_res(153) and ex4_shctl_64_cp2(1) ); +u_sh1y_091: ex4_sh1_y_b( 91) <= not( f_add_ex4_res(154) and ex4_shctl_64_cp2(1) ); +u_sh1y_092: ex4_sh1_y_b( 92) <= not( f_add_ex4_res(155) and ex4_shctl_64_cp2(1) ); +u_sh1y_093: ex4_sh1_y_b( 93) <= not( f_add_ex4_res(156) and ex4_shctl_64_cp2(1) ); +u_sh1y_094: ex4_sh1_y_b( 94) <= not( f_add_ex4_res(157) and ex4_shctl_64_cp2(1) ); +u_sh1y_095: ex4_sh1_y_b( 95) <= not( f_add_ex4_res(158) and ex4_shctl_64_cp2(1) ); +u_sh1y_096: ex4_sh1_y_b( 96) <= not( f_add_ex4_res(159) and ex4_shctl_64_cp2(1) ); +u_sh1y_097: ex4_sh1_y_b( 97) <= not( f_add_ex4_res(160) and ex4_shctl_64_cp2(1) ); +u_sh1y_098: ex4_sh1_y_b( 98) <= not( f_add_ex4_res(161) and ex4_shctl_64_cp2(1) ); +u_sh1y_099: ex4_sh1_y_b( 99) <= not( f_add_ex4_res(162) and ex4_shctl_64_cp2(1) ); + +u_sh1u_000: ex4_sh1_u_b( 0) <= not( f_add_ex4_res(127) and ex4_shctl_64(2) ); +u_sh1u_001: ex4_sh1_u_b( 1) <= not( f_add_ex4_res(128) and ex4_shctl_64(2) ); +u_sh1u_002: ex4_sh1_u_b( 2) <= not( f_add_ex4_res(129) and ex4_shctl_64(2) ); +u_sh1u_003: ex4_sh1_u_b( 3) <= not( f_add_ex4_res(130) and ex4_shctl_64(2) ); +u_sh1u_004: ex4_sh1_u_b( 4) <= not( f_add_ex4_res(131) and ex4_shctl_64(2) ); +u_sh1u_005: ex4_sh1_u_b( 5) <= not( f_add_ex4_res(132) and ex4_shctl_64(2) ); +u_sh1u_006: ex4_sh1_u_b( 6) <= not( f_add_ex4_res(133) and ex4_shctl_64(2) ); +u_sh1u_007: ex4_sh1_u_b( 7) <= not( f_add_ex4_res(134) and ex4_shctl_64(2) ); +u_sh1u_008: ex4_sh1_u_b( 8) <= not( f_add_ex4_res(135) and ex4_shctl_64(2) ); +u_sh1u_009: ex4_sh1_u_b( 9) <= not( f_add_ex4_res(136) and ex4_shctl_64(2) ); +u_sh1u_010: ex4_sh1_u_b( 10) <= not( f_add_ex4_res(137) and ex4_shctl_64(2) ); +u_sh1u_011: ex4_sh1_u_b( 11) <= not( f_add_ex4_res(138) and ex4_shctl_64(2) ); +u_sh1u_012: ex4_sh1_u_b( 12) <= not( f_add_ex4_res(139) and ex4_shctl_64(2) ); +u_sh1u_013: ex4_sh1_u_b( 13) <= not( f_add_ex4_res(140) and ex4_shctl_64(2) ); +u_sh1u_014: ex4_sh1_u_b( 14) <= not( f_add_ex4_res(141) and ex4_shctl_64(2) ); +u_sh1u_015: ex4_sh1_u_b( 15) <= not( f_add_ex4_res(142) and ex4_shctl_64(2) ); +u_sh1u_016: ex4_sh1_u_b( 16) <= not( f_add_ex4_res(143) and ex4_shctl_64(2) ); +u_sh1u_017: ex4_sh1_u_b( 17) <= not( f_add_ex4_res(144) and ex4_shctl_64(2) ); +u_sh1u_018: ex4_sh1_u_b( 18) <= not( f_add_ex4_res(145) and ex4_shctl_64(2) ); +u_sh1u_019: ex4_sh1_u_b( 19) <= not( f_add_ex4_res(146) and ex4_shctl_64(2) ); +u_sh1u_020: ex4_sh1_u_b( 20) <= not( f_add_ex4_res(147) and ex4_shctl_64(2) ); +u_sh1u_021: ex4_sh1_u_b( 21) <= not( f_add_ex4_res(148) and ex4_shctl_64(2) ); +u_sh1u_022: ex4_sh1_u_b( 22) <= not( f_add_ex4_res(149) and ex4_shctl_64(2) ); +u_sh1u_023: ex4_sh1_u_b( 23) <= not( f_add_ex4_res(150) and ex4_shctl_64(2) ); +u_sh1u_024: ex4_sh1_u_b( 24) <= not( f_add_ex4_res(151) and ex4_shctl_64(2) ); +u_sh1u_025: ex4_sh1_u_b( 25) <= not( f_add_ex4_res(152) and ex4_shctl_64(2) ); +u_sh1u_026: ex4_sh1_u_b( 26) <= not( f_add_ex4_res(153) and ex4_shctl_64(2) ); +u_sh1u_027: ex4_sh1_u_b( 27) <= not( f_add_ex4_res(154) and ex4_shctl_64(2) ); +u_sh1u_028: ex4_sh1_u_b( 28) <= not( f_add_ex4_res(155) and ex4_shctl_64(2) ); +u_sh1u_029: ex4_sh1_u_b( 29) <= not( f_add_ex4_res(156) and ex4_shctl_64(2) ); +u_sh1u_030: ex4_sh1_u_b( 30) <= not( f_add_ex4_res(157) and ex4_shctl_64(2) ); +u_sh1u_031: ex4_sh1_u_b( 31) <= not( f_add_ex4_res(158) and ex4_shctl_64(2) ); +u_sh1u_032: ex4_sh1_u_b( 32) <= not( f_add_ex4_res(159) and ex4_shctl_64(2) ); +u_sh1u_033: ex4_sh1_u_b( 33) <= not( f_add_ex4_res(160) and ex4_shctl_64(2) ); +u_sh1u_034: ex4_sh1_u_b( 34) <= not( f_add_ex4_res(161) and ex4_shctl_64(2) ); +u_sh1u_035: ex4_sh1_u_b( 35) <= not( f_add_ex4_res(162) and ex4_shctl_64(2) ); + +u_sh1z_065: ex4_sh1_z_b( 65) <= not( f_add_ex4_res( 0) and f_lza_ex4_sh_rgt_en ); +u_sh1z_066: ex4_sh1_z_b( 66) <= not( f_add_ex4_res( 1) and f_lza_ex4_sh_rgt_en ); +u_sh1z_067: ex4_sh1_z_b( 67) <= not( f_add_ex4_res( 2) and f_lza_ex4_sh_rgt_en ); +u_sh1z_068: ex4_sh1_z_b( 68) <= not( f_add_ex4_res( 3) and f_lza_ex4_sh_rgt_en ); +u_sh1z_069: ex4_sh1_z_b( 69) <= not( f_add_ex4_res( 4) and f_lza_ex4_sh_rgt_en ); +u_sh1z_070: ex4_sh1_z_b( 70) <= not( f_add_ex4_res( 5) and f_lza_ex4_sh_rgt_en ); +u_sh1z_071: ex4_sh1_z_b( 71) <= not( f_add_ex4_res( 6) and f_lza_ex4_sh_rgt_en ); +u_sh1z_072: ex4_sh1_z_b( 72) <= not( f_add_ex4_res( 7) and f_lza_ex4_sh_rgt_en ); +u_sh1z_073: ex4_sh1_z_b( 73) <= not( f_add_ex4_res( 8) and f_lza_ex4_sh_rgt_en ); +u_sh1z_074: ex4_sh1_z_b( 74) <= not( f_add_ex4_res( 9) and f_lza_ex4_sh_rgt_en ); +u_sh1z_075: ex4_sh1_z_b( 75) <= not( f_add_ex4_res( 10) and f_lza_ex4_sh_rgt_en ); +u_sh1z_076: ex4_sh1_z_b( 76) <= not( f_add_ex4_res( 11) and f_lza_ex4_sh_rgt_en ); +u_sh1z_077: ex4_sh1_z_b( 77) <= not( f_add_ex4_res( 12) and f_lza_ex4_sh_rgt_en ); +u_sh1z_078: ex4_sh1_z_b( 78) <= not( f_add_ex4_res( 13) and f_lza_ex4_sh_rgt_en ); +u_sh1z_079: ex4_sh1_z_b( 79) <= not( f_add_ex4_res( 14) and f_lza_ex4_sh_rgt_en ); +u_sh1z_080: ex4_sh1_z_b( 80) <= not( f_add_ex4_res( 15) and f_lza_ex4_sh_rgt_en ); +u_sh1z_081: ex4_sh1_z_b( 81) <= not( f_add_ex4_res( 16) and f_lza_ex4_sh_rgt_en ); +u_sh1z_082: ex4_sh1_z_b( 82) <= not( f_add_ex4_res( 17) and f_lza_ex4_sh_rgt_en ); +u_sh1z_083: ex4_sh1_z_b( 83) <= not( f_add_ex4_res( 18) and f_lza_ex4_sh_rgt_en ); +u_sh1z_084: ex4_sh1_z_b( 84) <= not( f_add_ex4_res( 19) and f_lza_ex4_sh_rgt_en ); +u_sh1z_085: ex4_sh1_z_b( 85) <= not( f_add_ex4_res( 20) and f_lza_ex4_sh_rgt_en ); +u_sh1z_086: ex4_sh1_z_b( 86) <= not( f_add_ex4_res( 21) and f_lza_ex4_sh_rgt_en ); +u_sh1z_087: ex4_sh1_z_b( 87) <= not( f_add_ex4_res( 22) and f_lza_ex4_sh_rgt_en ); +u_sh1z_088: ex4_sh1_z_b( 88) <= not( f_add_ex4_res( 23) and f_lza_ex4_sh_rgt_en ); +u_sh1z_089: ex4_sh1_z_b( 89) <= not( f_add_ex4_res( 24) and f_lza_ex4_sh_rgt_en ); +u_sh1z_090: ex4_sh1_z_b( 90) <= not( f_add_ex4_res( 25) and f_lza_ex4_sh_rgt_en ); +u_sh1z_091: ex4_sh1_z_b( 91) <= not( f_add_ex4_res( 26) and f_lza_ex4_sh_rgt_en ); +u_sh1z_092: ex4_sh1_z_b( 92) <= not( f_add_ex4_res( 27) and f_lza_ex4_sh_rgt_en ); +u_sh1z_093: ex4_sh1_z_b( 93) <= not( f_add_ex4_res( 28) and f_lza_ex4_sh_rgt_en ); +u_sh1z_094: ex4_sh1_z_b( 94) <= not( f_add_ex4_res( 29) and f_lza_ex4_sh_rgt_en ); +u_sh1z_095: ex4_sh1_z_b( 95) <= not( f_add_ex4_res( 30) and f_lza_ex4_sh_rgt_en ); +u_sh1z_096: ex4_sh1_z_b( 96) <= not( f_add_ex4_res( 31) and f_lza_ex4_sh_rgt_en ); +u_sh1z_097: ex4_sh1_z_b( 97) <= not( f_add_ex4_res( 32) and f_lza_ex4_sh_rgt_en ); +u_sh1z_098: ex4_sh1_z_b( 98) <= not( f_add_ex4_res( 33) and f_lza_ex4_sh_rgt_en ); +u_sh1z_099: ex4_sh1_z_b( 99) <= not( f_add_ex4_res( 34) and f_lza_ex4_sh_rgt_en ); +u_sh1z_100: ex4_sh1_z_b(100) <= not( f_add_ex4_res( 35) and f_lza_ex4_sh_rgt_en ); +u_sh1z_101: ex4_sh1_z_b(101) <= not( f_add_ex4_res( 36) and f_lza_ex4_sh_rgt_en ); +u_sh1z_102: ex4_sh1_z_b(102) <= not( f_add_ex4_res( 37) and f_lza_ex4_sh_rgt_en ); +u_sh1z_103: ex4_sh1_z_b(103) <= not( f_add_ex4_res( 38) and f_lza_ex4_sh_rgt_en ); +u_sh1z_104: ex4_sh1_z_b(104) <= not( f_add_ex4_res( 39) and f_lza_ex4_sh_rgt_en ); +u_sh1z_105: ex4_sh1_z_b(105) <= not( f_add_ex4_res( 40) and f_lza_ex4_sh_rgt_en ); +u_sh1z_106: ex4_sh1_z_b(106) <= not( f_add_ex4_res( 41) and f_lza_ex4_sh_rgt_en ); +u_sh1z_107: ex4_sh1_z_b(107) <= not( f_add_ex4_res( 42) and f_lza_ex4_sh_rgt_en ); +u_sh1z_108: ex4_sh1_z_b(108) <= not( f_add_ex4_res( 43) and f_lza_ex4_sh_rgt_en ); +u_sh1z_109: ex4_sh1_z_b(109) <= not( f_add_ex4_res( 44) and f_lza_ex4_sh_rgt_en ); +u_sh1z_110: ex4_sh1_z_b(110) <= not( f_add_ex4_res( 45) and f_lza_ex4_sh_rgt_en ); +u_sh1z_111: ex4_sh1_z_b(111) <= not( f_add_ex4_res( 46) and f_lza_ex4_sh_rgt_en ); +u_sh1z_112: ex4_sh1_z_b(112) <= not( f_add_ex4_res( 47) and f_lza_ex4_sh_rgt_en ); +u_sh1z_113: ex4_sh1_z_b(113) <= not( f_add_ex4_res( 48) and f_lza_ex4_sh_rgt_en ); +u_sh1z_114: ex4_sh1_z_b(114) <= not( f_add_ex4_res( 49) and f_lza_ex4_sh_rgt_en ); +u_sh1z_115: ex4_sh1_z_b(115) <= not( f_add_ex4_res( 50) and f_lza_ex4_sh_rgt_en ); +u_sh1z_116: ex4_sh1_z_b(116) <= not( f_add_ex4_res( 51) and f_lza_ex4_sh_rgt_en ); +u_sh1z_117: ex4_sh1_z_b(117) <= not( f_add_ex4_res( 52) and f_lza_ex4_sh_rgt_en ); +u_sh1z_118: ex4_sh1_z_b(118) <= not( f_add_ex4_res( 53) and f_lza_ex4_sh_rgt_en ); + + + + +u_sh1_000: ex4_sh1( 0) <= not( ex4_sh1_x_b( 0) and ex4_sh1_y_b( 0) and ex4_sh1_u_b( 0) ); +u_sh1_001: ex4_sh1( 1) <= not( ex4_sh1_x_b( 1) and ex4_sh1_y_b( 1) and ex4_sh1_u_b( 1) ); +u_sh1_002: ex4_sh1( 2) <= not( ex4_sh1_x_b( 2) and ex4_sh1_y_b( 2) and ex4_sh1_u_b( 2) ); +u_sh1_003: ex4_sh1( 3) <= not( ex4_sh1_x_b( 3) and ex4_sh1_y_b( 3) and ex4_sh1_u_b( 3) ); +u_sh1_004: ex4_sh1( 4) <= not( ex4_sh1_x_b( 4) and ex4_sh1_y_b( 4) and ex4_sh1_u_b( 4) ); +u_sh1_005: ex4_sh1( 5) <= not( ex4_sh1_x_b( 5) and ex4_sh1_y_b( 5) and ex4_sh1_u_b( 5) ); +u_sh1_006: ex4_sh1( 6) <= not( ex4_sh1_x_b( 6) and ex4_sh1_y_b( 6) and ex4_sh1_u_b( 6) ); +u_sh1_007: ex4_sh1( 7) <= not( ex4_sh1_x_b( 7) and ex4_sh1_y_b( 7) and ex4_sh1_u_b( 7) ); +u_sh1_008: ex4_sh1( 8) <= not( ex4_sh1_x_b( 8) and ex4_sh1_y_b( 8) and ex4_sh1_u_b( 8) ); +u_sh1_009: ex4_sh1( 9) <= not( ex4_sh1_x_b( 9) and ex4_sh1_y_b( 9) and ex4_sh1_u_b( 9) ); +u_sh1_010: ex4_sh1( 10) <= not( ex4_sh1_x_b( 10) and ex4_sh1_y_b( 10) and ex4_sh1_u_b( 10) ); +u_sh1_011: ex4_sh1( 11) <= not( ex4_sh1_x_b( 11) and ex4_sh1_y_b( 11) and ex4_sh1_u_b( 11) ); +u_sh1_012: ex4_sh1( 12) <= not( ex4_sh1_x_b( 12) and ex4_sh1_y_b( 12) and ex4_sh1_u_b( 12) ); +u_sh1_013: ex4_sh1( 13) <= not( ex4_sh1_x_b( 13) and ex4_sh1_y_b( 13) and ex4_sh1_u_b( 13) ); +u_sh1_014: ex4_sh1( 14) <= not( ex4_sh1_x_b( 14) and ex4_sh1_y_b( 14) and ex4_sh1_u_b( 14) ); +u_sh1_015: ex4_sh1( 15) <= not( ex4_sh1_x_b( 15) and ex4_sh1_y_b( 15) and ex4_sh1_u_b( 15) ); +u_sh1_016: ex4_sh1( 16) <= not( ex4_sh1_x_b( 16) and ex4_sh1_y_b( 16) and ex4_sh1_u_b( 16) ); +u_sh1_017: ex4_sh1( 17) <= not( ex4_sh1_x_b( 17) and ex4_sh1_y_b( 17) and ex4_sh1_u_b( 17) ); +u_sh1_018: ex4_sh1( 18) <= not( ex4_sh1_x_b( 18) and ex4_sh1_y_b( 18) and ex4_sh1_u_b( 18) ); +u_sh1_019: ex4_sh1( 19) <= not( ex4_sh1_x_b( 19) and ex4_sh1_y_b( 19) and ex4_sh1_u_b( 19) ); +u_sh1_020: ex4_sh1( 20) <= not( ex4_sh1_x_b( 20) and ex4_sh1_y_b( 20) and ex4_sh1_u_b( 20) ); +u_sh1_021: ex4_sh1( 21) <= not( ex4_sh1_x_b( 21) and ex4_sh1_y_b( 21) and ex4_sh1_u_b( 21) ); +u_sh1_022: ex4_sh1( 22) <= not( ex4_sh1_x_b( 22) and ex4_sh1_y_b( 22) and ex4_sh1_u_b( 22) ); +u_sh1_023: ex4_sh1( 23) <= not( ex4_sh1_x_b( 23) and ex4_sh1_y_b( 23) and ex4_sh1_u_b( 23) ); +u_sh1_024: ex4_sh1( 24) <= not( ex4_sh1_x_b( 24) and ex4_sh1_y_b( 24) and ex4_sh1_u_b( 24) ); +u_sh1_025: ex4_sh1( 25) <= not( ex4_sh1_x_b( 25) and ex4_sh1_y_b( 25) and ex4_sh1_u_b( 25) ); +u_sh1_026: ex4_sh1( 26) <= not( ex4_sh1_x_b( 26) and ex4_sh1_y_b( 26) and ex4_sh1_u_b( 26) ); +u_sh1_027: ex4_sh1( 27) <= not( ex4_sh1_x_b( 27) and ex4_sh1_y_b( 27) and ex4_sh1_u_b( 27) ); +u_sh1_028: ex4_sh1( 28) <= not( ex4_sh1_x_b( 28) and ex4_sh1_y_b( 28) and ex4_sh1_u_b( 28) ); +u_sh1_029: ex4_sh1( 29) <= not( ex4_sh1_x_b( 29) and ex4_sh1_y_b( 29) and ex4_sh1_u_b( 29) ); +u_sh1_030: ex4_sh1( 30) <= not( ex4_sh1_x_b( 30) and ex4_sh1_y_b( 30) and ex4_sh1_u_b( 30) ); +u_sh1_031: ex4_sh1( 31) <= not( ex4_sh1_x_b( 31) and ex4_sh1_y_b( 31) and ex4_sh1_u_b( 31) ); +u_sh1_032: ex4_sh1( 32) <= not( ex4_sh1_x_b( 32) and ex4_sh1_y_b( 32) and ex4_sh1_u_b( 32) ); +u_sh1_033: ex4_sh1( 33) <= not( ex4_sh1_x_b( 33) and ex4_sh1_y_b( 33) and ex4_sh1_u_b( 33) ); +u_sh1_034: ex4_sh1( 34) <= not( ex4_sh1_x_b( 34) and ex4_sh1_y_b( 34) and ex4_sh1_u_b( 34) ); +u_sh1_035: ex4_sh1( 35) <= not( ex4_sh1_x_b( 35) and ex4_sh1_y_b( 35) and ex4_sh1_u_b( 35) ); +u_sh1_036: ex4_sh1( 36) <= not( ex4_sh1_x_b( 36) and ex4_sh1_y_b( 36) ); +u_sh1_037: ex4_sh1( 37) <= not( ex4_sh1_x_b( 37) and ex4_sh1_y_b( 37) ); +u_sh1_038: ex4_sh1( 38) <= not( ex4_sh1_x_b( 38) and ex4_sh1_y_b( 38) ); +u_sh1_039: ex4_sh1( 39) <= not( ex4_sh1_x_b( 39) and ex4_sh1_y_b( 39) ); +u_sh1_040: ex4_sh1( 40) <= not( ex4_sh1_x_b( 40) and ex4_sh1_y_b( 40) ); +u_sh1_041: ex4_sh1( 41) <= not( ex4_sh1_x_b( 41) and ex4_sh1_y_b( 41) ); +u_sh1_042: ex4_sh1( 42) <= not( ex4_sh1_x_b( 42) and ex4_sh1_y_b( 42) ); +u_sh1_043: ex4_sh1( 43) <= not( ex4_sh1_x_b( 43) and ex4_sh1_y_b( 43) ); +u_sh1_044: ex4_sh1( 44) <= not( ex4_sh1_x_b( 44) and ex4_sh1_y_b( 44) ); +u_sh1_045: ex4_sh1( 45) <= not( ex4_sh1_x_b( 45) and ex4_sh1_y_b( 45) ); +u_sh1_046: ex4_sh1( 46) <= not( ex4_sh1_x_b( 46) and ex4_sh1_y_b( 46) ); +u_sh1_047: ex4_sh1( 47) <= not( ex4_sh1_x_b( 47) and ex4_sh1_y_b( 47) ); +u_sh1_048: ex4_sh1( 48) <= not( ex4_sh1_x_b( 48) and ex4_sh1_y_b( 48) ); +u_sh1_049: ex4_sh1( 49) <= not( ex4_sh1_x_b( 49) and ex4_sh1_y_b( 49) ); +u_sh1_050: ex4_sh1( 50) <= not( ex4_sh1_x_b( 50) and ex4_sh1_y_b( 50) ); +u_sh1_051: ex4_sh1( 51) <= not( ex4_sh1_x_b( 51) and ex4_sh1_y_b( 51) ); +u_sh1_052: ex4_sh1( 52) <= not( ex4_sh1_x_b( 52) and ex4_sh1_y_b( 52) ); +u_sh1_053: ex4_sh1( 53) <= not( ex4_sh1_x_b( 53) and ex4_sh1_y_b( 53) ); +u_sh1_054: ex4_sh1( 54) <= not( ex4_sh1_x_b( 54) and ex4_sh1_y_b( 54) ); +u_sh1_055: ex4_sh1( 55) <= not( ex4_sh1_x_b( 55) and ex4_sh1_y_b( 55) ); +u_sh1_056: ex4_sh1( 56) <= not( ex4_sh1_x_b( 56) and ex4_sh1_y_b( 56) ); +u_sh1_057: ex4_sh1( 57) <= not( ex4_sh1_x_b( 57) and ex4_sh1_y_b( 57) ); +u_sh1_058: ex4_sh1( 58) <= not( ex4_sh1_x_b( 58) and ex4_sh1_y_b( 58) ); +u_sh1_059: ex4_sh1( 59) <= not( ex4_sh1_x_b( 59) and ex4_sh1_y_b( 59) ); +u_sh1_060: ex4_sh1( 60) <= not( ex4_sh1_x_b( 60) and ex4_sh1_y_b( 60) ); +u_sh1_061: ex4_sh1( 61) <= not( ex4_sh1_x_b( 61) and ex4_sh1_y_b( 61) ); +u_sh1_062: ex4_sh1( 62) <= not( ex4_sh1_x_b( 62) and ex4_sh1_y_b( 62) ); +u_sh1_063: ex4_sh1( 63) <= not( ex4_sh1_x_b( 63) and ex4_sh1_y_b( 63) ); +u_sh1_064: ex4_sh1( 64) <= not( ex4_sh1_x_b( 64) and ex4_sh1_y_b( 64) ); +u_sh1_065: ex4_sh1( 65) <= not( ex4_sh1_x_b( 65) and ex4_sh1_y_b( 65) and ex4_sh1_z_b( 65) ); +u_sh1_066: ex4_sh1( 66) <= not( ex4_sh1_x_b( 66) and ex4_sh1_y_b( 66) and ex4_sh1_z_b( 66) ); +u_sh1_067: ex4_sh1( 67) <= not( ex4_sh1_x_b( 67) and ex4_sh1_y_b( 67) and ex4_sh1_z_b( 67) ); +u_sh1_068: ex4_sh1( 68) <= not( ex4_sh1_x_b( 68) and ex4_sh1_y_b( 68) and ex4_sh1_z_b( 68) ); +u_sh1_069: ex4_sh1( 69) <= not( ex4_sh1_x_b( 69) and ex4_sh1_y_b( 69) and ex4_sh1_z_b( 69) ); +u_sh1_070: ex4_sh1( 70) <= not( ex4_sh1_x_b( 70) and ex4_sh1_y_b( 70) and ex4_sh1_z_b( 70) ); +u_sh1_071: ex4_sh1( 71) <= not( ex4_sh1_x_b( 71) and ex4_sh1_y_b( 71) and ex4_sh1_z_b( 71) ); +u_sh1_072: ex4_sh1( 72) <= not( ex4_sh1_x_b( 72) and ex4_sh1_y_b( 72) and ex4_sh1_z_b( 72) ); +u_sh1_073: ex4_sh1( 73) <= not( ex4_sh1_x_b( 73) and ex4_sh1_y_b( 73) and ex4_sh1_z_b( 73) ); +u_sh1_074: ex4_sh1( 74) <= not( ex4_sh1_x_b( 74) and ex4_sh1_y_b( 74) and ex4_sh1_z_b( 74) ); +u_sh1_075: ex4_sh1( 75) <= not( ex4_sh1_x_b( 75) and ex4_sh1_y_b( 75) and ex4_sh1_z_b( 75) ); +u_sh1_076: ex4_sh1( 76) <= not( ex4_sh1_x_b( 76) and ex4_sh1_y_b( 76) and ex4_sh1_z_b( 76) ); +u_sh1_077: ex4_sh1( 77) <= not( ex4_sh1_x_b( 77) and ex4_sh1_y_b( 77) and ex4_sh1_z_b( 77) ); +u_sh1_078: ex4_sh1( 78) <= not( ex4_sh1_x_b( 78) and ex4_sh1_y_b( 78) and ex4_sh1_z_b( 78) ); +u_sh1_079: ex4_sh1( 79) <= not( ex4_sh1_x_b( 79) and ex4_sh1_y_b( 79) and ex4_sh1_z_b( 79) ); +u_sh1_080: ex4_sh1( 80) <= not( ex4_sh1_x_b( 80) and ex4_sh1_y_b( 80) and ex4_sh1_z_b( 80) ); +u_sh1_081: ex4_sh1( 81) <= not( ex4_sh1_x_b( 81) and ex4_sh1_y_b( 81) and ex4_sh1_z_b( 81) ); +u_sh1_082: ex4_sh1( 82) <= not( ex4_sh1_x_b( 82) and ex4_sh1_y_b( 82) and ex4_sh1_z_b( 82) ); +u_sh1_083: ex4_sh1( 83) <= not( ex4_sh1_x_b( 83) and ex4_sh1_y_b( 83) and ex4_sh1_z_b( 83) ); +u_sh1_084: ex4_sh1( 84) <= not( ex4_sh1_x_b( 84) and ex4_sh1_y_b( 84) and ex4_sh1_z_b( 84) ); +u_sh1_085: ex4_sh1( 85) <= not( ex4_sh1_x_b( 85) and ex4_sh1_y_b( 85) and ex4_sh1_z_b( 85) ); +u_sh1_086: ex4_sh1( 86) <= not( ex4_sh1_x_b( 86) and ex4_sh1_y_b( 86) and ex4_sh1_z_b( 86) ); +u_sh1_087: ex4_sh1( 87) <= not( ex4_sh1_x_b( 87) and ex4_sh1_y_b( 87) and ex4_sh1_z_b( 87) ); +u_sh1_088: ex4_sh1( 88) <= not( ex4_sh1_x_b( 88) and ex4_sh1_y_b( 88) and ex4_sh1_z_b( 88) ); +u_sh1_089: ex4_sh1( 89) <= not( ex4_sh1_x_b( 89) and ex4_sh1_y_b( 89) and ex4_sh1_z_b( 89) ); +u_sh1_090: ex4_sh1( 90) <= not( ex4_sh1_x_b( 90) and ex4_sh1_y_b( 90) and ex4_sh1_z_b( 90) ); +u_sh1_091: ex4_sh1( 91) <= not( ex4_sh1_x_b( 91) and ex4_sh1_y_b( 91) and ex4_sh1_z_b( 91) ); +u_sh1_092: ex4_sh1( 92) <= not( ex4_sh1_x_b( 92) and ex4_sh1_y_b( 92) and ex4_sh1_z_b( 92) ); +u_sh1_093: ex4_sh1( 93) <= not( ex4_sh1_x_b( 93) and ex4_sh1_y_b( 93) and ex4_sh1_z_b( 93) ); +u_sh1_094: ex4_sh1( 94) <= not( ex4_sh1_x_b( 94) and ex4_sh1_y_b( 94) and ex4_sh1_z_b( 94) ); +u_sh1_095: ex4_sh1( 95) <= not( ex4_sh1_x_b( 95) and ex4_sh1_y_b( 95) and ex4_sh1_z_b( 95) ); +u_sh1_096: ex4_sh1( 96) <= not( ex4_sh1_x_b( 96) and ex4_sh1_y_b( 96) and ex4_sh1_z_b( 96) ); +u_sh1_097: ex4_sh1( 97) <= not( ex4_sh1_x_b( 97) and ex4_sh1_y_b( 97) and ex4_sh1_z_b( 97) ); +u_sh1_098: ex4_sh1( 98) <= not( ex4_sh1_x_b( 98) and ex4_sh1_y_b( 98) and ex4_sh1_z_b( 98) ); +u_sh1_099: ex4_sh1( 99) <= not( ex4_sh1_x_b( 99) and ex4_sh1_y_b( 99) and ex4_sh1_z_b( 99) ); +u_sh1_100: ex4_sh1(100) <= not( ex4_sh1_x_b(100) and ex4_sh1_z_b(100) ); +u_sh1_101: ex4_sh1(101) <= not( ex4_sh1_x_b(101) and ex4_sh1_z_b(101) ); +u_sh1_102: ex4_sh1(102) <= not( ex4_sh1_x_b(102) and ex4_sh1_z_b(102) ); +u_sh1_103: ex4_sh1(103) <= not( ex4_sh1_x_b(103) and ex4_sh1_z_b(103) ); +u_sh1_104: ex4_sh1(104) <= not( ex4_sh1_x_b(104) and ex4_sh1_z_b(104) ); +u_sh1_105: ex4_sh1(105) <= not( ex4_sh1_x_b(105) and ex4_sh1_z_b(105) ); +u_sh1_106: ex4_sh1(106) <= not( ex4_sh1_x_b(106) and ex4_sh1_z_b(106) ); +u_sh1_107: ex4_sh1(107) <= not( ex4_sh1_x_b(107) and ex4_sh1_z_b(107) ); +u_sh1_108: ex4_sh1(108) <= not( ex4_sh1_x_b(108) and ex4_sh1_z_b(108) ); +u_sh1_109: ex4_sh1(109) <= not( ex4_sh1_x_b(109) and ex4_sh1_z_b(109) ); +u_sh1_110: ex4_sh1(110) <= not( ex4_sh1_x_b(110) and ex4_sh1_z_b(110) ); +u_sh1_111: ex4_sh1(111) <= not( ex4_sh1_x_b(111) and ex4_sh1_z_b(111) ); +u_sh1_112: ex4_sh1(112) <= not( ex4_sh1_x_b(112) and ex4_sh1_z_b(112) ); +u_sh1_113: ex4_sh1(113) <= not( ex4_sh1_x_b(113) and ex4_sh1_z_b(113) ); +u_sh1_114: ex4_sh1(114) <= not( ex4_sh1_x_b(114) and ex4_sh1_z_b(114) ); +u_sh1_115: ex4_sh1(115) <= not( ex4_sh1_x_b(115) and ex4_sh1_z_b(115) ); +u_sh1_116: ex4_sh1(116) <= not( ex4_sh1_x_b(116) and ex4_sh1_z_b(116) ); +u_sh1_117: ex4_sh1(117) <= not( ex4_sh1_x_b(117) and ex4_sh1_z_b(117) ); +u_sh1_118: ex4_sh1(118) <= not( ex4_sh1_x_b(118) and ex4_sh1_z_b(118) ); +u_sh1_119: ex4_sh1(119) <= not( ex4_sh1_x_b(119) ); +u_sh1_120: ex4_sh1(120) <= not( ex4_sh1_x_b(120) ); + + ------------------------------------------------------------------------------------ + + +u_sh2x_00: ex4_sh2_x_b( 0) <= not( (ex4_sh1( 0) and ex4_shctl_16(0) ) or ( ex4_sh1( 16) and ex4_shctl_16(1) ) ); +u_sh2x_01: ex4_sh2_x_b( 1) <= not( (ex4_sh1( 1) and ex4_shctl_16(0) ) or ( ex4_sh1( 17) and ex4_shctl_16(1) ) ); +u_sh2x_02: ex4_sh2_x_b( 2) <= not( (ex4_sh1( 2) and ex4_shctl_16(0) ) or ( ex4_sh1( 18) and ex4_shctl_16(1) ) ); +u_sh2x_03: ex4_sh2_x_b( 3) <= not( (ex4_sh1( 3) and ex4_shctl_16(0) ) or ( ex4_sh1( 19) and ex4_shctl_16(1) ) ); +u_sh2x_04: ex4_sh2_x_b( 4) <= not( (ex4_sh1( 4) and ex4_shctl_16(0) ) or ( ex4_sh1( 20) and ex4_shctl_16(1) ) ); +u_sh2x_05: ex4_sh2_x_b( 5) <= not( (ex4_sh1( 5) and ex4_shctl_16(0) ) or ( ex4_sh1( 21) and ex4_shctl_16(1) ) ); +u_sh2x_06: ex4_sh2_x_b( 6) <= not( (ex4_sh1( 6) and ex4_shctl_16(0) ) or ( ex4_sh1( 22) and ex4_shctl_16(1) ) ); +u_sh2x_07: ex4_sh2_x_b( 7) <= not( (ex4_sh1( 7) and ex4_shctl_16(0) ) or ( ex4_sh1( 23) and ex4_shctl_16(1) ) ); +u_sh2x_08: ex4_sh2_x_b( 8) <= not( (ex4_sh1( 8) and ex4_shctl_16(0) ) or ( ex4_sh1( 24) and ex4_shctl_16(1) ) ); +u_sh2x_09: ex4_sh2_x_b( 9) <= not( (ex4_sh1( 9) and ex4_shctl_16(0) ) or ( ex4_sh1( 25) and ex4_shctl_16(1) ) ); +u_sh2x_10: ex4_sh2_x_b(10) <= not( (ex4_sh1( 10) and ex4_shctl_16(0) ) or ( ex4_sh1( 26) and ex4_shctl_16(1) ) ); +u_sh2x_11: ex4_sh2_x_b(11) <= not( (ex4_sh1( 11) and ex4_shctl_16(0) ) or ( ex4_sh1( 27) and ex4_shctl_16(1) ) ); +u_sh2x_12: ex4_sh2_x_b(12) <= not( (ex4_sh1( 12) and ex4_shctl_16(0) ) or ( ex4_sh1( 28) and ex4_shctl_16(1) ) ); +u_sh2x_13: ex4_sh2_x_b(13) <= not( (ex4_sh1( 13) and ex4_shctl_16(0) ) or ( ex4_sh1( 29) and ex4_shctl_16(1) ) ); +u_sh2x_14: ex4_sh2_x_b(14) <= not( (ex4_sh1( 14) and ex4_shctl_16(0) ) or ( ex4_sh1( 30) and ex4_shctl_16(1) ) ); +u_sh2x_15: ex4_sh2_x_b(15) <= not( (ex4_sh1( 15) and ex4_shctl_16(0) ) or ( ex4_sh1( 31) and ex4_shctl_16(1) ) ); +u_sh2x_16: ex4_sh2_x_b(16) <= not( (ex4_sh1( 16) and ex4_shctl_16(0) ) or ( ex4_sh1( 32) and ex4_shctl_16(1) ) ); +u_sh2x_17: ex4_sh2_x_b(17) <= not( (ex4_sh1( 17) and ex4_shctl_16(0) ) or ( ex4_sh1( 33) and ex4_shctl_16(1) ) ); +u_sh2x_18: ex4_sh2_x_b(18) <= not( (ex4_sh1( 18) and ex4_shctl_16(0) ) or ( ex4_sh1( 34) and ex4_shctl_16(1) ) ); +u_sh2x_19: ex4_sh2_x_b(19) <= not( (ex4_sh1( 19) and ex4_shctl_16(0) ) or ( ex4_sh1( 35) and ex4_shctl_16(1) ) ); +u_sh2x_20: ex4_sh2_x_b(20) <= not( (ex4_sh1( 20) and ex4_shctl_16(0) ) or ( ex4_sh1( 36) and ex4_shctl_16(1) ) ); +u_sh2x_21: ex4_sh2_x_b(21) <= not( (ex4_sh1( 21) and ex4_shctl_16(0) ) or ( ex4_sh1( 37) and ex4_shctl_16(1) ) ); +u_sh2x_22: ex4_sh2_x_b(22) <= not( (ex4_sh1( 22) and ex4_shctl_16(0) ) or ( ex4_sh1( 38) and ex4_shctl_16(1) ) ); +u_sh2x_23: ex4_sh2_x_b(23) <= not( (ex4_sh1( 23) and ex4_shctl_16(0) ) or ( ex4_sh1( 39) and ex4_shctl_16(1) ) ); +u_sh2x_24: ex4_sh2_x_b(24) <= not( (ex4_sh1( 24) and ex4_shctl_16(0) ) or ( ex4_sh1( 40) and ex4_shctl_16(1) ) ); +u_sh2x_25: ex4_sh2_x_b(25) <= not( (ex4_sh1( 25) and ex4_shctl_16(0) ) or ( ex4_sh1( 41) and ex4_shctl_16(1) ) ); +u_sh2x_26: ex4_sh2_x_b(26) <= not( (ex4_sh1( 26) and ex4_shctl_16(0) ) or ( ex4_sh1( 42) and ex4_shctl_16(1) ) ); +u_sh2x_27: ex4_sh2_x_b(27) <= not( (ex4_sh1( 27) and ex4_shctl_16(0) ) or ( ex4_sh1( 43) and ex4_shctl_16(1) ) ); +u_sh2x_28: ex4_sh2_x_b(28) <= not( (ex4_sh1( 28) and ex4_shctl_16(0) ) or ( ex4_sh1( 44) and ex4_shctl_16(1) ) ); +u_sh2x_29: ex4_sh2_x_b(29) <= not( (ex4_sh1( 29) and ex4_shctl_16(0) ) or ( ex4_sh1( 45) and ex4_shctl_16(1) ) ); +u_sh2x_30: ex4_sh2_x_b(30) <= not( (ex4_sh1( 30) and ex4_shctl_16(0) ) or ( ex4_sh1( 46) and ex4_shctl_16(1) ) ); +u_sh2x_31: ex4_sh2_x_b(31) <= not( (ex4_sh1( 31) and ex4_shctl_16(0) ) or ( ex4_sh1( 47) and ex4_shctl_16(1) ) ); +u_sh2x_32: ex4_sh2_x_b(32) <= not( (ex4_sh1( 32) and ex4_shctl_16(0) ) or ( ex4_sh1( 48) and ex4_shctl_16(1) ) ); +u_sh2x_33: ex4_sh2_x_b(33) <= not( (ex4_sh1( 33) and ex4_shctl_16(0) ) or ( ex4_sh1( 49) and ex4_shctl_16(1) ) ); +u_sh2x_34: ex4_sh2_x_b(34) <= not( (ex4_sh1( 34) and ex4_shctl_16(0) ) or ( ex4_sh1( 50) and ex4_shctl_16(1) ) ); +u_sh2x_35: ex4_sh2_x_b(35) <= not( (ex4_sh1( 35) and ex4_shctl_16(0) ) or ( ex4_sh1( 51) and ex4_shctl_16(1) ) ); +u_sh2x_36: ex4_sh2_x_b(36) <= not( (ex4_sh1( 36) and ex4_shctl_16(0) ) or ( ex4_sh1( 52) and ex4_shctl_16(1) ) ); +u_sh2x_37: ex4_sh2_x_b(37) <= not( (ex4_sh1( 37) and ex4_shctl_16(0) ) or ( ex4_sh1( 53) and ex4_shctl_16(1) ) ); +u_sh2x_38: ex4_sh2_x_b(38) <= not( (ex4_sh1( 38) and ex4_shctl_16(0) ) or ( ex4_sh1( 54) and ex4_shctl_16(1) ) ); +u_sh2x_39: ex4_sh2_x_b(39) <= not( (ex4_sh1( 39) and ex4_shctl_16(0) ) or ( ex4_sh1( 55) and ex4_shctl_16(1) ) ); +u_sh2x_40: ex4_sh2_x_b(40) <= not( (ex4_sh1( 40) and ex4_shctl_16(0) ) or ( ex4_sh1( 56) and ex4_shctl_16(1) ) ); +u_sh2x_41: ex4_sh2_x_b(41) <= not( (ex4_sh1( 41) and ex4_shctl_16(0) ) or ( ex4_sh1( 57) and ex4_shctl_16(1) ) ); +u_sh2x_42: ex4_sh2_x_b(42) <= not( (ex4_sh1( 42) and ex4_shctl_16(0) ) or ( ex4_sh1( 58) and ex4_shctl_16(1) ) ); +u_sh2x_43: ex4_sh2_x_b(43) <= not( (ex4_sh1( 43) and ex4_shctl_16(0) ) or ( ex4_sh1( 59) and ex4_shctl_16(1) ) ); +u_sh2x_44: ex4_sh2_x_b(44) <= not( (ex4_sh1( 44) and ex4_shctl_16(0) ) or ( ex4_sh1( 60) and ex4_shctl_16(1) ) ); +u_sh2x_45: ex4_sh2_x_b(45) <= not( (ex4_sh1( 45) and ex4_shctl_16(0) ) or ( ex4_sh1( 61) and ex4_shctl_16(1) ) ); +u_sh2x_46: ex4_sh2_x_b(46) <= not( (ex4_sh1( 46) and ex4_shctl_16(0) ) or ( ex4_sh1( 62) and ex4_shctl_16(1) ) ); +u_sh2x_47: ex4_sh2_x_b(47) <= not( (ex4_sh1( 47) and ex4_shctl_16(0) ) or ( ex4_sh1( 63) and ex4_shctl_16(1) ) ); +u_sh2x_48: ex4_sh2_x_b(48) <= not( (ex4_sh1( 48) and ex4_shctl_16(0) ) or ( ex4_sh1( 64) and ex4_shctl_16(1) ) ); +u_sh2x_49: ex4_sh2_x_b(49) <= not( (ex4_sh1( 49) and ex4_shctl_16(0) ) or ( ex4_sh1( 65) and ex4_shctl_16(1) ) ); +u_sh2x_50: ex4_sh2_x_b(50) <= not( (ex4_sh1( 50) and ex4_shctl_16(0) ) or ( ex4_sh1( 66) and ex4_shctl_16(1) ) ); +u_sh2x_51: ex4_sh2_x_b(51) <= not( (ex4_sh1( 51) and ex4_shctl_16(0) ) or ( ex4_sh1( 67) and ex4_shctl_16(1) ) ); +u_sh2x_52: ex4_sh2_x_b(52) <= not( (ex4_sh1( 52) and ex4_shctl_16(0) ) or ( ex4_sh1( 68) and ex4_shctl_16(1) ) ); +u_sh2x_53: ex4_sh2_x_b(53) <= not( (ex4_sh1( 53) and ex4_shctl_16(0) ) or ( ex4_sh1( 69) and ex4_shctl_16(1) ) ); +u_sh2x_54: ex4_sh2_x_b(54) <= not( (ex4_sh1( 54) and ex4_shctl_16(0) ) or ( ex4_sh1( 70) and ex4_shctl_16(1) ) ); +u_sh2x_55: ex4_sh2_x_b(55) <= not( (ex4_sh1( 55) and ex4_shctl_16(0) ) or ( ex4_sh1( 71) and ex4_shctl_16(1) ) ); +u_sh2x_56: ex4_sh2_x_b(56) <= not( (ex4_sh1( 56) and ex4_shctl_16(0) ) or ( ex4_sh1( 72) and ex4_shctl_16(1) ) ); +u_sh2x_57: ex4_sh2_x_b(57) <= not( (ex4_sh1( 57) and ex4_shctl_16(0) ) or ( ex4_sh1( 73) and ex4_shctl_16(1) ) ); +u_sh2x_58: ex4_sh2_x_b(58) <= not( (ex4_sh1( 58) and ex4_shctl_16(0) ) or ( ex4_sh1( 74) and ex4_shctl_16(1) ) ); +u_sh2x_59: ex4_sh2_x_b(59) <= not( (ex4_sh1( 59) and ex4_shctl_16(0) ) or ( ex4_sh1( 75) and ex4_shctl_16(1) ) ); +u_sh2x_60: ex4_sh2_x_b(60) <= not( (ex4_sh1( 60) and ex4_shctl_16(0) ) or ( ex4_sh1( 76) and ex4_shctl_16(1) ) ); +u_sh2x_61: ex4_sh2_x_b(61) <= not( (ex4_sh1( 61) and ex4_shctl_16(0) ) or ( ex4_sh1( 77) and ex4_shctl_16(1) ) ); +u_sh2x_62: ex4_sh2_x_b(62) <= not( (ex4_sh1( 62) and ex4_shctl_16(0) ) or ( ex4_sh1( 78) and ex4_shctl_16(1) ) ); +u_sh2x_63: ex4_sh2_x_b(63) <= not( (ex4_sh1( 63) and ex4_shctl_16(0) ) or ( ex4_sh1( 79) and ex4_shctl_16(1) ) ); +u_sh2x_64: ex4_sh2_x_b(64) <= not( (ex4_sh1( 64) and ex4_shctl_16(0) ) or ( ex4_sh1( 80) and ex4_shctl_16(1) ) ); +u_sh2x_65: ex4_sh2_x_b(65) <= not( (ex4_sh1( 65) and ex4_shctl_16(0) ) or ( ex4_sh1( 81) and ex4_shctl_16(1) ) ); +u_sh2x_66: ex4_sh2_x_b(66) <= not( (ex4_sh1( 66) and ex4_shctl_16(0) ) or ( ex4_sh1( 82) and ex4_shctl_16(1) ) ); +u_sh2x_67: ex4_sh2_x_b(67) <= not( (ex4_sh1( 67) and ex4_shctl_16(0) ) or ( ex4_sh1( 83) and ex4_shctl_16(1) ) ); +u_sh2x_68: ex4_sh2_x_b(68) <= not( (ex4_sh1( 68) and ex4_shctl_16(0) ) or ( ex4_sh1( 84) and ex4_shctl_16(1) ) ); +u_sh2x_69: ex4_sh2_x_b(69) <= not( (ex4_sh1( 69) and ex4_shctl_16(0) ) or ( ex4_sh1( 85) and ex4_shctl_16(1) ) ); +u_sh2x_70: ex4_sh2_x_b(70) <= not( (ex4_sh1( 70) and ex4_shctl_16(0) ) or ( ex4_sh1( 86) and ex4_shctl_16(1) ) ); +u_sh2x_71: ex4_sh2_x_b(71) <= not( (ex4_sh1( 71) and ex4_shctl_16(0) ) or ( ex4_sh1( 87) and ex4_shctl_16(1) ) ); +u_sh2x_72: ex4_sh2_x_b(72) <= not( (ex4_sh1( 72) and ex4_shctl_16(0) ) or ( ex4_sh1( 88) and ex4_shctl_16(1) ) ); + +u_sh2y_00: ex4_sh2_y_b( 0) <= not( (ex4_sh1( 32) and ex4_shctl_16(2) ) or ( ex4_sh1( 48) and ex4_shctl_16(3) ) ); +u_sh2y_01: ex4_sh2_y_b( 1) <= not( (ex4_sh1( 33) and ex4_shctl_16(2) ) or ( ex4_sh1( 49) and ex4_shctl_16(3) ) ); +u_sh2y_02: ex4_sh2_y_b( 2) <= not( (ex4_sh1( 34) and ex4_shctl_16(2) ) or ( ex4_sh1( 50) and ex4_shctl_16(3) ) ); +u_sh2y_03: ex4_sh2_y_b( 3) <= not( (ex4_sh1( 35) and ex4_shctl_16(2) ) or ( ex4_sh1( 51) and ex4_shctl_16(3) ) ); +u_sh2y_04: ex4_sh2_y_b( 4) <= not( (ex4_sh1( 36) and ex4_shctl_16(2) ) or ( ex4_sh1( 52) and ex4_shctl_16(3) ) ); +u_sh2y_05: ex4_sh2_y_b( 5) <= not( (ex4_sh1( 37) and ex4_shctl_16(2) ) or ( ex4_sh1( 53) and ex4_shctl_16(3) ) ); +u_sh2y_06: ex4_sh2_y_b( 6) <= not( (ex4_sh1( 38) and ex4_shctl_16(2) ) or ( ex4_sh1( 54) and ex4_shctl_16(3) ) ); +u_sh2y_07: ex4_sh2_y_b( 7) <= not( (ex4_sh1( 39) and ex4_shctl_16(2) ) or ( ex4_sh1( 55) and ex4_shctl_16(3) ) ); +u_sh2y_08: ex4_sh2_y_b( 8) <= not( (ex4_sh1( 40) and ex4_shctl_16(2) ) or ( ex4_sh1( 56) and ex4_shctl_16(3) ) ); +u_sh2y_09: ex4_sh2_y_b( 9) <= not( (ex4_sh1( 41) and ex4_shctl_16(2) ) or ( ex4_sh1( 57) and ex4_shctl_16(3) ) ); +u_sh2y_10: ex4_sh2_y_b(10) <= not( (ex4_sh1( 42) and ex4_shctl_16(2) ) or ( ex4_sh1( 58) and ex4_shctl_16(3) ) ); +u_sh2y_11: ex4_sh2_y_b(11) <= not( (ex4_sh1( 43) and ex4_shctl_16(2) ) or ( ex4_sh1( 59) and ex4_shctl_16(3) ) ); +u_sh2y_12: ex4_sh2_y_b(12) <= not( (ex4_sh1( 44) and ex4_shctl_16(2) ) or ( ex4_sh1( 60) and ex4_shctl_16(3) ) ); +u_sh2y_13: ex4_sh2_y_b(13) <= not( (ex4_sh1( 45) and ex4_shctl_16(2) ) or ( ex4_sh1( 61) and ex4_shctl_16(3) ) ); +u_sh2y_14: ex4_sh2_y_b(14) <= not( (ex4_sh1( 46) and ex4_shctl_16(2) ) or ( ex4_sh1( 62) and ex4_shctl_16(3) ) ); +u_sh2y_15: ex4_sh2_y_b(15) <= not( (ex4_sh1( 47) and ex4_shctl_16(2) ) or ( ex4_sh1( 63) and ex4_shctl_16(3) ) ); +u_sh2y_16: ex4_sh2_y_b(16) <= not( (ex4_sh1( 48) and ex4_shctl_16(2) ) or ( ex4_sh1( 64) and ex4_shctl_16(3) ) ); +u_sh2y_17: ex4_sh2_y_b(17) <= not( (ex4_sh1( 49) and ex4_shctl_16(2) ) or ( ex4_sh1( 65) and ex4_shctl_16(3) ) ); +u_sh2y_18: ex4_sh2_y_b(18) <= not( (ex4_sh1( 50) and ex4_shctl_16(2) ) or ( ex4_sh1( 66) and ex4_shctl_16(3) ) ); +u_sh2y_19: ex4_sh2_y_b(19) <= not( (ex4_sh1( 51) and ex4_shctl_16(2) ) or ( ex4_sh1( 67) and ex4_shctl_16(3) ) ); +u_sh2y_20: ex4_sh2_y_b(20) <= not( (ex4_sh1( 52) and ex4_shctl_16(2) ) or ( ex4_sh1( 68) and ex4_shctl_16(3) ) ); +u_sh2y_21: ex4_sh2_y_b(21) <= not( (ex4_sh1( 53) and ex4_shctl_16(2) ) or ( ex4_sh1( 69) and ex4_shctl_16(3) ) ); +u_sh2y_22: ex4_sh2_y_b(22) <= not( (ex4_sh1( 54) and ex4_shctl_16(2) ) or ( ex4_sh1( 70) and ex4_shctl_16(3) ) ); +u_sh2y_23: ex4_sh2_y_b(23) <= not( (ex4_sh1( 55) and ex4_shctl_16(2) ) or ( ex4_sh1( 71) and ex4_shctl_16(3) ) ); +u_sh2y_24: ex4_sh2_y_b(24) <= not( (ex4_sh1( 56) and ex4_shctl_16(2) ) or ( ex4_sh1( 72) and ex4_shctl_16(3) ) ); +u_sh2y_25: ex4_sh2_y_b(25) <= not( (ex4_sh1( 57) and ex4_shctl_16(2) ) or ( ex4_sh1( 73) and ex4_shctl_16(3) ) ); +u_sh2y_26: ex4_sh2_y_b(26) <= not( (ex4_sh1( 58) and ex4_shctl_16(2) ) or ( ex4_sh1( 74) and ex4_shctl_16(3) ) ); +u_sh2y_27: ex4_sh2_y_b(27) <= not( (ex4_sh1( 59) and ex4_shctl_16(2) ) or ( ex4_sh1( 75) and ex4_shctl_16(3) ) ); +u_sh2y_28: ex4_sh2_y_b(28) <= not( (ex4_sh1( 60) and ex4_shctl_16(2) ) or ( ex4_sh1( 76) and ex4_shctl_16(3) ) ); +u_sh2y_29: ex4_sh2_y_b(29) <= not( (ex4_sh1( 61) and ex4_shctl_16(2) ) or ( ex4_sh1( 77) and ex4_shctl_16(3) ) ); +u_sh2y_30: ex4_sh2_y_b(30) <= not( (ex4_sh1( 62) and ex4_shctl_16(2) ) or ( ex4_sh1( 78) and ex4_shctl_16(3) ) ); +u_sh2y_31: ex4_sh2_y_b(31) <= not( (ex4_sh1( 63) and ex4_shctl_16(2) ) or ( ex4_sh1( 79) and ex4_shctl_16(3) ) ); +u_sh2y_32: ex4_sh2_y_b(32) <= not( (ex4_sh1( 64) and ex4_shctl_16(2) ) or ( ex4_sh1( 80) and ex4_shctl_16(3) ) ); +u_sh2y_33: ex4_sh2_y_b(33) <= not( (ex4_sh1( 65) and ex4_shctl_16(2) ) or ( ex4_sh1( 81) and ex4_shctl_16(3) ) ); +u_sh2y_34: ex4_sh2_y_b(34) <= not( (ex4_sh1( 66) and ex4_shctl_16(2) ) or ( ex4_sh1( 82) and ex4_shctl_16(3) ) ); +u_sh2y_35: ex4_sh2_y_b(35) <= not( (ex4_sh1( 67) and ex4_shctl_16(2) ) or ( ex4_sh1( 83) and ex4_shctl_16(3) ) ); +u_sh2y_36: ex4_sh2_y_b(36) <= not( (ex4_sh1( 68) and ex4_shctl_16(2) ) or ( ex4_sh1( 84) and ex4_shctl_16(3) ) ); +u_sh2y_37: ex4_sh2_y_b(37) <= not( (ex4_sh1( 69) and ex4_shctl_16(2) ) or ( ex4_sh1( 85) and ex4_shctl_16(3) ) ); +u_sh2y_38: ex4_sh2_y_b(38) <= not( (ex4_sh1( 70) and ex4_shctl_16(2) ) or ( ex4_sh1( 86) and ex4_shctl_16(3) ) ); +u_sh2y_39: ex4_sh2_y_b(39) <= not( (ex4_sh1( 71) and ex4_shctl_16(2) ) or ( ex4_sh1( 87) and ex4_shctl_16(3) ) ); +u_sh2y_40: ex4_sh2_y_b(40) <= not( (ex4_sh1( 72) and ex4_shctl_16(2) ) or ( ex4_sh1( 88) and ex4_shctl_16(3) ) ); +u_sh2y_41: ex4_sh2_y_b(41) <= not( (ex4_sh1( 73) and ex4_shctl_16(2) ) or ( ex4_sh1( 89) and ex4_shctl_16(3) ) ); +u_sh2y_42: ex4_sh2_y_b(42) <= not( (ex4_sh1( 74) and ex4_shctl_16(2) ) or ( ex4_sh1( 90) and ex4_shctl_16(3) ) ); +u_sh2y_43: ex4_sh2_y_b(43) <= not( (ex4_sh1( 75) and ex4_shctl_16(2) ) or ( ex4_sh1( 91) and ex4_shctl_16(3) ) ); +u_sh2y_44: ex4_sh2_y_b(44) <= not( (ex4_sh1( 76) and ex4_shctl_16(2) ) or ( ex4_sh1( 92) and ex4_shctl_16(3) ) ); +u_sh2y_45: ex4_sh2_y_b(45) <= not( (ex4_sh1( 77) and ex4_shctl_16(2) ) or ( ex4_sh1( 93) and ex4_shctl_16(3) ) ); +u_sh2y_46: ex4_sh2_y_b(46) <= not( (ex4_sh1( 78) and ex4_shctl_16(2) ) or ( ex4_sh1( 94) and ex4_shctl_16(3) ) ); +u_sh2y_47: ex4_sh2_y_b(47) <= not( (ex4_sh1( 79) and ex4_shctl_16(2) ) or ( ex4_sh1( 95) and ex4_shctl_16(3) ) ); +u_sh2y_48: ex4_sh2_y_b(48) <= not( (ex4_sh1( 80) and ex4_shctl_16(2) ) or ( ex4_sh1( 96) and ex4_shctl_16(3) ) ); +u_sh2y_49: ex4_sh2_y_b(49) <= not( (ex4_sh1( 81) and ex4_shctl_16(2) ) or ( ex4_sh1( 97) and ex4_shctl_16(3) ) ); +u_sh2y_50: ex4_sh2_y_b(50) <= not( (ex4_sh1( 82) and ex4_shctl_16(2) ) or ( ex4_sh1( 98) and ex4_shctl_16(3) ) ); +u_sh2y_51: ex4_sh2_y_b(51) <= not( (ex4_sh1( 83) and ex4_shctl_16(2) ) or ( ex4_sh1( 99) and ex4_shctl_16(3) ) ); +u_sh2y_52: ex4_sh2_y_b(52) <= not( (ex4_sh1( 84) and ex4_shctl_16(2) ) or ( ex4_sh1(100) and ex4_shctl_16(3) ) ); +u_sh2y_53: ex4_sh2_y_b(53) <= not( (ex4_sh1( 85) and ex4_shctl_16(2) ) or ( ex4_sh1(101) and ex4_shctl_16(3) ) ); +u_sh2y_54: ex4_sh2_y_b(54) <= not( (ex4_sh1( 86) and ex4_shctl_16(2) ) or ( ex4_sh1(102) and ex4_shctl_16(3) ) ); +u_sh2y_55: ex4_sh2_y_b(55) <= not( (ex4_sh1( 87) and ex4_shctl_16(2) ) or ( ex4_sh1(103) and ex4_shctl_16(3) ) ); +u_sh2y_56: ex4_sh2_y_b(56) <= not( (ex4_sh1( 88) and ex4_shctl_16(2) ) or ( ex4_sh1(104) and ex4_shctl_16(3) ) ); +u_sh2y_57: ex4_sh2_y_b(57) <= not( (ex4_sh1( 89) and ex4_shctl_16(2) ) or ( ex4_sh1(105) and ex4_shctl_16(3) ) ); +u_sh2y_58: ex4_sh2_y_b(58) <= not( (ex4_sh1( 90) and ex4_shctl_16(2) ) or ( ex4_sh1(106) and ex4_shctl_16(3) ) ); +u_sh2y_59: ex4_sh2_y_b(59) <= not( (ex4_sh1( 91) and ex4_shctl_16(2) ) or ( ex4_sh1(107) and ex4_shctl_16(3) ) ); +u_sh2y_60: ex4_sh2_y_b(60) <= not( (ex4_sh1( 92) and ex4_shctl_16(2) ) or ( ex4_sh1(108) and ex4_shctl_16(3) ) ); +u_sh2y_61: ex4_sh2_y_b(61) <= not( (ex4_sh1( 93) and ex4_shctl_16(2) ) or ( ex4_sh1(109) and ex4_shctl_16(3) ) ); +u_sh2y_62: ex4_sh2_y_b(62) <= not( (ex4_sh1( 94) and ex4_shctl_16(2) ) or ( ex4_sh1(110) and ex4_shctl_16(3) ) ); +u_sh2y_63: ex4_sh2_y_b(63) <= not( (ex4_sh1( 95) and ex4_shctl_16(2) ) or ( ex4_sh1(111) and ex4_shctl_16(3) ) ); +u_sh2y_64: ex4_sh2_y_b(64) <= not( (ex4_sh1( 96) and ex4_shctl_16(2) ) or ( ex4_sh1(112) and ex4_shctl_16(3) ) ); +u_sh2y_65: ex4_sh2_y_b(65) <= not( (ex4_sh1( 97) and ex4_shctl_16(2) ) or ( ex4_sh1(113) and ex4_shctl_16(3) ) ); +u_sh2y_66: ex4_sh2_y_b(66) <= not( (ex4_sh1( 98) and ex4_shctl_16(2) ) or ( ex4_sh1(114) and ex4_shctl_16(3) ) ); +u_sh2y_67: ex4_sh2_y_b(67) <= not( (ex4_sh1( 99) and ex4_shctl_16(2) ) or ( ex4_sh1(115) and ex4_shctl_16(3) ) ); +u_sh2y_68: ex4_sh2_y_b(68) <= not( (ex4_sh1(100) and ex4_shctl_16(2) ) or ( ex4_sh1(116) and ex4_shctl_16(3) ) ); +u_sh2y_69: ex4_sh2_y_b(69) <= not( (ex4_sh1(101) and ex4_shctl_16(2) ) or ( ex4_sh1(117) and ex4_shctl_16(3) ) ); +u_sh2y_70: ex4_sh2_y_b(70) <= not( (ex4_sh1(102) and ex4_shctl_16(2) ) or ( ex4_sh1(118) and ex4_shctl_16(3) ) ); +u_sh2y_71: ex4_sh2_y_b(71) <= not( (ex4_sh1(103) and ex4_shctl_16(2) ) or ( ex4_sh1(119) and ex4_shctl_16(3) ) ); +u_sh2y_72: ex4_sh2_y_b(72) <= not( (ex4_sh1(104) and ex4_shctl_16(2) ) or ( ex4_sh1(120) and ex4_shctl_16(3) ) ); + + + +u_sh2_00: ex4_sh2( 0) <= not( ex4_sh2_x_b( 0) and ex4_sh2_y_b( 0) ); +u_sh2_01: ex4_sh2( 1) <= not( ex4_sh2_x_b( 1) and ex4_sh2_y_b( 1) ); +u_sh2_02: ex4_sh2( 2) <= not( ex4_sh2_x_b( 2) and ex4_sh2_y_b( 2) ); +u_sh2_03: ex4_sh2( 3) <= not( ex4_sh2_x_b( 3) and ex4_sh2_y_b( 3) ); +u_sh2_04: ex4_sh2( 4) <= not( ex4_sh2_x_b( 4) and ex4_sh2_y_b( 4) ); +u_sh2_05: ex4_sh2( 5) <= not( ex4_sh2_x_b( 5) and ex4_sh2_y_b( 5) ); +u_sh2_06: ex4_sh2( 6) <= not( ex4_sh2_x_b( 6) and ex4_sh2_y_b( 6) ); +u_sh2_07: ex4_sh2( 7) <= not( ex4_sh2_x_b( 7) and ex4_sh2_y_b( 7) ); +u_sh2_08: ex4_sh2( 8) <= not( ex4_sh2_x_b( 8) and ex4_sh2_y_b( 8) ); +u_sh2_09: ex4_sh2( 9) <= not( ex4_sh2_x_b( 9) and ex4_sh2_y_b( 9) ); +u_sh2_10: ex4_sh2(10) <= not( ex4_sh2_x_b(10) and ex4_sh2_y_b(10) ); +u_sh2_11: ex4_sh2(11) <= not( ex4_sh2_x_b(11) and ex4_sh2_y_b(11) ); +u_sh2_12: ex4_sh2(12) <= not( ex4_sh2_x_b(12) and ex4_sh2_y_b(12) ); +u_sh2_13: ex4_sh2(13) <= not( ex4_sh2_x_b(13) and ex4_sh2_y_b(13) ); +u_sh2_14: ex4_sh2(14) <= not( ex4_sh2_x_b(14) and ex4_sh2_y_b(14) ); +u_sh2_15: ex4_sh2(15) <= not( ex4_sh2_x_b(15) and ex4_sh2_y_b(15) ); +u_sh2_16: ex4_sh2(16) <= not( ex4_sh2_x_b(16) and ex4_sh2_y_b(16) ); +u_sh2_17: ex4_sh2(17) <= not( ex4_sh2_x_b(17) and ex4_sh2_y_b(17) ); +u_sh2_18: ex4_sh2(18) <= not( ex4_sh2_x_b(18) and ex4_sh2_y_b(18) ); +u_sh2_19: ex4_sh2(19) <= not( ex4_sh2_x_b(19) and ex4_sh2_y_b(19) ); +u_sh2_20: ex4_sh2(20) <= not( ex4_sh2_x_b(20) and ex4_sh2_y_b(20) ); +u_sh2_21: ex4_sh2(21) <= not( ex4_sh2_x_b(21) and ex4_sh2_y_b(21) ); +u_sh2_22: ex4_sh2(22) <= not( ex4_sh2_x_b(22) and ex4_sh2_y_b(22) ); +u_sh2_23: ex4_sh2(23) <= not( ex4_sh2_x_b(23) and ex4_sh2_y_b(23) ); +u_sh2_24: ex4_sh2(24) <= not( ex4_sh2_x_b(24) and ex4_sh2_y_b(24) ); +u_sh2_25: ex4_sh2(25) <= not( ex4_sh2_x_b(25) and ex4_sh2_y_b(25) ); +u_sh2_26: ex4_sh2(26) <= not( ex4_sh2_x_b(26) and ex4_sh2_y_b(26) ); +u_sh2_27: ex4_sh2(27) <= not( ex4_sh2_x_b(27) and ex4_sh2_y_b(27) ); +u_sh2_28: ex4_sh2(28) <= not( ex4_sh2_x_b(28) and ex4_sh2_y_b(28) ); +u_sh2_29: ex4_sh2(29) <= not( ex4_sh2_x_b(29) and ex4_sh2_y_b(29) ); +u_sh2_30: ex4_sh2(30) <= not( ex4_sh2_x_b(30) and ex4_sh2_y_b(30) ); +u_sh2_31: ex4_sh2(31) <= not( ex4_sh2_x_b(31) and ex4_sh2_y_b(31) ); +u_sh2_32: ex4_sh2(32) <= not( ex4_sh2_x_b(32) and ex4_sh2_y_b(32) ); +u_sh2_33: ex4_sh2(33) <= not( ex4_sh2_x_b(33) and ex4_sh2_y_b(33) ); +u_sh2_34: ex4_sh2(34) <= not( ex4_sh2_x_b(34) and ex4_sh2_y_b(34) ); +u_sh2_35: ex4_sh2(35) <= not( ex4_sh2_x_b(35) and ex4_sh2_y_b(35) ); +u_sh2_36: ex4_sh2(36) <= not( ex4_sh2_x_b(36) and ex4_sh2_y_b(36) ); +u_sh2_37: ex4_sh2(37) <= not( ex4_sh2_x_b(37) and ex4_sh2_y_b(37) ); +u_sh2_38: ex4_sh2(38) <= not( ex4_sh2_x_b(38) and ex4_sh2_y_b(38) ); +u_sh2_39: ex4_sh2(39) <= not( ex4_sh2_x_b(39) and ex4_sh2_y_b(39) ); +u_sh2_40: ex4_sh2(40) <= not( ex4_sh2_x_b(40) and ex4_sh2_y_b(40) ); +u_sh2_41: ex4_sh2(41) <= not( ex4_sh2_x_b(41) and ex4_sh2_y_b(41) ); +u_sh2_42: ex4_sh2(42) <= not( ex4_sh2_x_b(42) and ex4_sh2_y_b(42) ); +u_sh2_43: ex4_sh2(43) <= not( ex4_sh2_x_b(43) and ex4_sh2_y_b(43) ); +u_sh2_44: ex4_sh2(44) <= not( ex4_sh2_x_b(44) and ex4_sh2_y_b(44) ); +u_sh2_45: ex4_sh2(45) <= not( ex4_sh2_x_b(45) and ex4_sh2_y_b(45) ); +u_sh2_46: ex4_sh2(46) <= not( ex4_sh2_x_b(46) and ex4_sh2_y_b(46) ); +u_sh2_47: ex4_sh2(47) <= not( ex4_sh2_x_b(47) and ex4_sh2_y_b(47) ); +u_sh2_48: ex4_sh2(48) <= not( ex4_sh2_x_b(48) and ex4_sh2_y_b(48) ); +u_sh2_49: ex4_sh2(49) <= not( ex4_sh2_x_b(49) and ex4_sh2_y_b(49) ); +u_sh2_50: ex4_sh2(50) <= not( ex4_sh2_x_b(50) and ex4_sh2_y_b(50) ); +u_sh2_51: ex4_sh2(51) <= not( ex4_sh2_x_b(51) and ex4_sh2_y_b(51) ); +u_sh2_52: ex4_sh2(52) <= not( ex4_sh2_x_b(52) and ex4_sh2_y_b(52) ); +u_sh2_53: ex4_sh2(53) <= not( ex4_sh2_x_b(53) and ex4_sh2_y_b(53) ); +u_sh2_54: ex4_sh2(54) <= not( ex4_sh2_x_b(54) and ex4_sh2_y_b(54) ); +u_sh2_55: ex4_sh2(55) <= not( ex4_sh2_x_b(55) and ex4_sh2_y_b(55) ); +u_sh2_56: ex4_sh2(56) <= not( ex4_sh2_x_b(56) and ex4_sh2_y_b(56) ); +u_sh2_57: ex4_sh2(57) <= not( ex4_sh2_x_b(57) and ex4_sh2_y_b(57) ); +u_sh2_58: ex4_sh2(58) <= not( ex4_sh2_x_b(58) and ex4_sh2_y_b(58) ); +u_sh2_59: ex4_sh2(59) <= not( ex4_sh2_x_b(59) and ex4_sh2_y_b(59) ); +u_sh2_60: ex4_sh2(60) <= not( ex4_sh2_x_b(60) and ex4_sh2_y_b(60) ); +u_sh2_61: ex4_sh2(61) <= not( ex4_sh2_x_b(61) and ex4_sh2_y_b(61) ); +u_sh2_62: ex4_sh2(62) <= not( ex4_sh2_x_b(62) and ex4_sh2_y_b(62) ); +u_sh2_63: ex4_sh2(63) <= not( ex4_sh2_x_b(63) and ex4_sh2_y_b(63) ); +u_sh2_64: ex4_sh2(64) <= not( ex4_sh2_x_b(64) and ex4_sh2_y_b(64) ); +u_sh2_65: ex4_sh2(65) <= not( ex4_sh2_x_b(65) and ex4_sh2_y_b(65) ); +u_sh2_66: ex4_sh2(66) <= not( ex4_sh2_x_b(66) and ex4_sh2_y_b(66) ); +u_sh2_67: ex4_sh2(67) <= not( ex4_sh2_x_b(67) and ex4_sh2_y_b(67) ); +u_sh2_68: ex4_sh2(68) <= not( ex4_sh2_x_b(68) and ex4_sh2_y_b(68) ); +u_sh2_69: ex4_sh2(69) <= not( ex4_sh2_x_b(69) and ex4_sh2_y_b(69) ); +u_sh2_70: ex4_sh2(70) <= not( ex4_sh2_x_b(70) and ex4_sh2_y_b(70) ); +u_sh2_71: ex4_sh2(71) <= not( ex4_sh2_x_b(71) and ex4_sh2_y_b(71) ); +u_sh2_72: ex4_sh2(72) <= not( ex4_sh2_x_b(72) and ex4_sh2_y_b(72) ); + + ----------------------------------------------- + + +u_sh3x_00: ex4_sh3_x_b( 0) <= not( (ex4_sh2( 0) and ex4_shctl_04(0) ) or ( ex4_sh2( 4) and ex4_shctl_04(1) ) ); +u_sh3x_01: ex4_sh3_x_b( 1) <= not( (ex4_sh2( 1) and ex4_shctl_04(0) ) or ( ex4_sh2( 5) and ex4_shctl_04(1) ) ); +u_sh3x_02: ex4_sh3_x_b( 2) <= not( (ex4_sh2( 2) and ex4_shctl_04(0) ) or ( ex4_sh2( 6) and ex4_shctl_04(1) ) ); +u_sh3x_03: ex4_sh3_x_b( 3) <= not( (ex4_sh2( 3) and ex4_shctl_04(0) ) or ( ex4_sh2( 7) and ex4_shctl_04(1) ) ); +u_sh3x_04: ex4_sh3_x_b( 4) <= not( (ex4_sh2( 4) and ex4_shctl_04(0) ) or ( ex4_sh2( 8) and ex4_shctl_04(1) ) ); +u_sh3x_05: ex4_sh3_x_b( 5) <= not( (ex4_sh2( 5) and ex4_shctl_04(0) ) or ( ex4_sh2( 9) and ex4_shctl_04(1) ) ); +u_sh3x_06: ex4_sh3_x_b( 6) <= not( (ex4_sh2( 6) and ex4_shctl_04(0) ) or ( ex4_sh2(10) and ex4_shctl_04(1) ) ); +u_sh3x_07: ex4_sh3_x_b( 7) <= not( (ex4_sh2( 7) and ex4_shctl_04(0) ) or ( ex4_sh2(11) and ex4_shctl_04(1) ) ); +u_sh3x_08: ex4_sh3_x_b( 8) <= not( (ex4_sh2( 8) and ex4_shctl_04(0) ) or ( ex4_sh2(12) and ex4_shctl_04(1) ) ); +u_sh3x_09: ex4_sh3_x_b( 9) <= not( (ex4_sh2( 9) and ex4_shctl_04(0) ) or ( ex4_sh2(13) and ex4_shctl_04(1) ) ); +u_sh3x_10: ex4_sh3_x_b(10) <= not( (ex4_sh2(10) and ex4_shctl_04(0) ) or ( ex4_sh2(14) and ex4_shctl_04(1) ) ); +u_sh3x_11: ex4_sh3_x_b(11) <= not( (ex4_sh2(11) and ex4_shctl_04(0) ) or ( ex4_sh2(15) and ex4_shctl_04(1) ) ); +u_sh3x_12: ex4_sh3_x_b(12) <= not( (ex4_sh2(12) and ex4_shctl_04(0) ) or ( ex4_sh2(16) and ex4_shctl_04(1) ) ); +u_sh3x_13: ex4_sh3_x_b(13) <= not( (ex4_sh2(13) and ex4_shctl_04(0) ) or ( ex4_sh2(17) and ex4_shctl_04(1) ) ); +u_sh3x_14: ex4_sh3_x_b(14) <= not( (ex4_sh2(14) and ex4_shctl_04(0) ) or ( ex4_sh2(18) and ex4_shctl_04(1) ) ); +u_sh3x_15: ex4_sh3_x_b(15) <= not( (ex4_sh2(15) and ex4_shctl_04(0) ) or ( ex4_sh2(19) and ex4_shctl_04(1) ) ); +u_sh3x_16: ex4_sh3_x_b(16) <= not( (ex4_sh2(16) and ex4_shctl_04(0) ) or ( ex4_sh2(20) and ex4_shctl_04(1) ) ); +u_sh3x_17: ex4_sh3_x_b(17) <= not( (ex4_sh2(17) and ex4_shctl_04(0) ) or ( ex4_sh2(21) and ex4_shctl_04(1) ) ); +u_sh3x_18: ex4_sh3_x_b(18) <= not( (ex4_sh2(18) and ex4_shctl_04(0) ) or ( ex4_sh2(22) and ex4_shctl_04(1) ) ); +u_sh3x_19: ex4_sh3_x_b(19) <= not( (ex4_sh2(19) and ex4_shctl_04(0) ) or ( ex4_sh2(23) and ex4_shctl_04(1) ) ); +u_sh3x_20: ex4_sh3_x_b(20) <= not( (ex4_sh2(20) and ex4_shctl_04(0) ) or ( ex4_sh2(24) and ex4_shctl_04(1) ) ); +u_sh3x_21: ex4_sh3_x_b(21) <= not( (ex4_sh2(21) and ex4_shctl_04(0) ) or ( ex4_sh2(25) and ex4_shctl_04(1) ) ); +u_sh3x_22: ex4_sh3_x_b(22) <= not( (ex4_sh2(22) and ex4_shctl_04(0) ) or ( ex4_sh2(26) and ex4_shctl_04(1) ) ); +u_sh3x_23: ex4_sh3_x_b(23) <= not( (ex4_sh2(23) and ex4_shctl_04(0) ) or ( ex4_sh2(27) and ex4_shctl_04(1) ) ); +u_sh3x_24: ex4_sh3_x_b(24) <= not( (ex4_sh2(24) and ex4_shctl_04(0) ) or ( ex4_sh2(28) and ex4_shctl_04(1) ) ); +u_sh3x_25: ex4_sh3_x_b(25) <= not( (ex4_sh2(25) and ex4_shctl_04(0) ) or ( ex4_sh2(29) and ex4_shctl_04(1) ) ); +u_sh3x_26: ex4_sh3_x_b(26) <= not( (ex4_sh2(26) and ex4_shctl_04(0) ) or ( ex4_sh2(30) and ex4_shctl_04(1) ) ); +u_sh3x_27: ex4_sh3_x_b(27) <= not( (ex4_sh2(27) and ex4_shctl_04(0) ) or ( ex4_sh2(31) and ex4_shctl_04(1) ) ); +u_sh3x_28: ex4_sh3_x_b(28) <= not( (ex4_sh2(28) and ex4_shctl_04(0) ) or ( ex4_sh2(32) and ex4_shctl_04(1) ) ); +u_sh3x_29: ex4_sh3_x_b(29) <= not( (ex4_sh2(29) and ex4_shctl_04(0) ) or ( ex4_sh2(33) and ex4_shctl_04(1) ) ); +u_sh3x_30: ex4_sh3_x_b(30) <= not( (ex4_sh2(30) and ex4_shctl_04(0) ) or ( ex4_sh2(34) and ex4_shctl_04(1) ) ); +u_sh3x_31: ex4_sh3_x_b(31) <= not( (ex4_sh2(31) and ex4_shctl_04(0) ) or ( ex4_sh2(35) and ex4_shctl_04(1) ) ); +u_sh3x_32: ex4_sh3_x_b(32) <= not( (ex4_sh2(32) and ex4_shctl_04(0) ) or ( ex4_sh2(36) and ex4_shctl_04(1) ) ); +u_sh3x_33: ex4_sh3_x_b(33) <= not( (ex4_sh2(33) and ex4_shctl_04(0) ) or ( ex4_sh2(37) and ex4_shctl_04(1) ) ); +u_sh3x_34: ex4_sh3_x_b(34) <= not( (ex4_sh2(34) and ex4_shctl_04(0) ) or ( ex4_sh2(38) and ex4_shctl_04(1) ) ); +u_sh3x_35: ex4_sh3_x_b(35) <= not( (ex4_sh2(35) and ex4_shctl_04(0) ) or ( ex4_sh2(39) and ex4_shctl_04(1) ) ); +u_sh3x_36: ex4_sh3_x_b(36) <= not( (ex4_sh2(36) and ex4_shctl_04(0) ) or ( ex4_sh2(40) and ex4_shctl_04(1) ) ); +u_sh3x_37: ex4_sh3_x_b(37) <= not( (ex4_sh2(37) and ex4_shctl_04(0) ) or ( ex4_sh2(41) and ex4_shctl_04(1) ) ); +u_sh3x_38: ex4_sh3_x_b(38) <= not( (ex4_sh2(38) and ex4_shctl_04(0) ) or ( ex4_sh2(42) and ex4_shctl_04(1) ) ); +u_sh3x_39: ex4_sh3_x_b(39) <= not( (ex4_sh2(39) and ex4_shctl_04(0) ) or ( ex4_sh2(43) and ex4_shctl_04(1) ) ); +u_sh3x_40: ex4_sh3_x_b(40) <= not( (ex4_sh2(40) and ex4_shctl_04(0) ) or ( ex4_sh2(44) and ex4_shctl_04(1) ) ); +u_sh3x_41: ex4_sh3_x_b(41) <= not( (ex4_sh2(41) and ex4_shctl_04(0) ) or ( ex4_sh2(45) and ex4_shctl_04(1) ) ); +u_sh3x_42: ex4_sh3_x_b(42) <= not( (ex4_sh2(42) and ex4_shctl_04(0) ) or ( ex4_sh2(46) and ex4_shctl_04(1) ) ); +u_sh3x_43: ex4_sh3_x_b(43) <= not( (ex4_sh2(43) and ex4_shctl_04(0) ) or ( ex4_sh2(47) and ex4_shctl_04(1) ) ); +u_sh3x_44: ex4_sh3_x_b(44) <= not( (ex4_sh2(44) and ex4_shctl_04(0) ) or ( ex4_sh2(48) and ex4_shctl_04(1) ) ); +u_sh3x_45: ex4_sh3_x_b(45) <= not( (ex4_sh2(45) and ex4_shctl_04(0) ) or ( ex4_sh2(49) and ex4_shctl_04(1) ) ); +u_sh3x_46: ex4_sh3_x_b(46) <= not( (ex4_sh2(46) and ex4_shctl_04(0) ) or ( ex4_sh2(50) and ex4_shctl_04(1) ) ); +u_sh3x_47: ex4_sh3_x_b(47) <= not( (ex4_sh2(47) and ex4_shctl_04(0) ) or ( ex4_sh2(51) and ex4_shctl_04(1) ) ); +u_sh3x_48: ex4_sh3_x_b(48) <= not( (ex4_sh2(48) and ex4_shctl_04(0) ) or ( ex4_sh2(52) and ex4_shctl_04(1) ) ); +u_sh3x_49: ex4_sh3_x_b(49) <= not( (ex4_sh2(49) and ex4_shctl_04(0) ) or ( ex4_sh2(53) and ex4_shctl_04(1) ) ); +u_sh3x_50: ex4_sh3_x_b(50) <= not( (ex4_sh2(50) and ex4_shctl_04(0) ) or ( ex4_sh2(54) and ex4_shctl_04(1) ) ); +u_sh3x_51: ex4_sh3_x_b(51) <= not( (ex4_sh2(51) and ex4_shctl_04(0) ) or ( ex4_sh2(55) and ex4_shctl_04(1) ) ); +u_sh3x_52: ex4_sh3_x_b(52) <= not( (ex4_sh2(52) and ex4_shctl_04(0) ) or ( ex4_sh2(56) and ex4_shctl_04(1) ) ); +u_sh3x_53: ex4_sh3_x_b(53) <= not( (ex4_sh2(53) and ex4_shctl_04(0) ) or ( ex4_sh2(57) and ex4_shctl_04(1) ) ); +u_sh3x_54: ex4_sh3_x_b(54) <= not( (ex4_sh2(54) and ex4_shctl_04(0) ) or ( ex4_sh2(58) and ex4_shctl_04(1) ) ); +u_sh3x_55: ex4_sh3_x_b(55) <= not( (ex4_sh2(55) and ex4_shctl_04(0) ) or ( ex4_sh2(59) and ex4_shctl_04(1) ) ); +u_sh3x_56: ex4_sh3_x_b(56) <= not( (ex4_sh2(56) and ex4_shctl_04(0) ) or ( ex4_sh2(60) and ex4_shctl_04(1) ) ); +u_sh3x_57: ex4_sh3_x_b(57) <= not( (ex4_sh2(57) and ex4_shctl_04(0) ) or ( ex4_sh2(61) and ex4_shctl_04(1) ) ); + +u_sh3y_00: ex4_sh3_y_b( 0) <= not( (ex4_sh2( 8) and ex4_shctl_04(2) ) or ( ex4_sh2(12) and ex4_shctl_04(3) ) ); +u_sh3y_01: ex4_sh3_y_b( 1) <= not( (ex4_sh2( 9) and ex4_shctl_04(2) ) or ( ex4_sh2(13) and ex4_shctl_04(3) ) ); +u_sh3y_02: ex4_sh3_y_b( 2) <= not( (ex4_sh2(10) and ex4_shctl_04(2) ) or ( ex4_sh2(14) and ex4_shctl_04(3) ) ); +u_sh3y_03: ex4_sh3_y_b( 3) <= not( (ex4_sh2(11) and ex4_shctl_04(2) ) or ( ex4_sh2(15) and ex4_shctl_04(3) ) ); +u_sh3y_04: ex4_sh3_y_b( 4) <= not( (ex4_sh2(12) and ex4_shctl_04(2) ) or ( ex4_sh2(16) and ex4_shctl_04(3) ) ); +u_sh3y_05: ex4_sh3_y_b( 5) <= not( (ex4_sh2(13) and ex4_shctl_04(2) ) or ( ex4_sh2(17) and ex4_shctl_04(3) ) ); +u_sh3y_06: ex4_sh3_y_b( 6) <= not( (ex4_sh2(14) and ex4_shctl_04(2) ) or ( ex4_sh2(18) and ex4_shctl_04(3) ) ); +u_sh3y_07: ex4_sh3_y_b( 7) <= not( (ex4_sh2(15) and ex4_shctl_04(2) ) or ( ex4_sh2(19) and ex4_shctl_04(3) ) ); +u_sh3y_08: ex4_sh3_y_b( 8) <= not( (ex4_sh2(16) and ex4_shctl_04(2) ) or ( ex4_sh2(20) and ex4_shctl_04(3) ) ); +u_sh3y_09: ex4_sh3_y_b( 9) <= not( (ex4_sh2(17) and ex4_shctl_04(2) ) or ( ex4_sh2(21) and ex4_shctl_04(3) ) ); +u_sh3y_10: ex4_sh3_y_b(10) <= not( (ex4_sh2(18) and ex4_shctl_04(2) ) or ( ex4_sh2(22) and ex4_shctl_04(3) ) ); +u_sh3y_11: ex4_sh3_y_b(11) <= not( (ex4_sh2(19) and ex4_shctl_04(2) ) or ( ex4_sh2(23) and ex4_shctl_04(3) ) ); +u_sh3y_12: ex4_sh3_y_b(12) <= not( (ex4_sh2(20) and ex4_shctl_04(2) ) or ( ex4_sh2(24) and ex4_shctl_04(3) ) ); +u_sh3y_13: ex4_sh3_y_b(13) <= not( (ex4_sh2(21) and ex4_shctl_04(2) ) or ( ex4_sh2(25) and ex4_shctl_04(3) ) ); +u_sh3y_14: ex4_sh3_y_b(14) <= not( (ex4_sh2(22) and ex4_shctl_04(2) ) or ( ex4_sh2(26) and ex4_shctl_04(3) ) ); +u_sh3y_15: ex4_sh3_y_b(15) <= not( (ex4_sh2(23) and ex4_shctl_04(2) ) or ( ex4_sh2(27) and ex4_shctl_04(3) ) ); +u_sh3y_16: ex4_sh3_y_b(16) <= not( (ex4_sh2(24) and ex4_shctl_04(2) ) or ( ex4_sh2(28) and ex4_shctl_04(3) ) ); +u_sh3y_17: ex4_sh3_y_b(17) <= not( (ex4_sh2(25) and ex4_shctl_04(2) ) or ( ex4_sh2(29) and ex4_shctl_04(3) ) ); +u_sh3y_18: ex4_sh3_y_b(18) <= not( (ex4_sh2(26) and ex4_shctl_04(2) ) or ( ex4_sh2(30) and ex4_shctl_04(3) ) ); +u_sh3y_19: ex4_sh3_y_b(19) <= not( (ex4_sh2(27) and ex4_shctl_04(2) ) or ( ex4_sh2(31) and ex4_shctl_04(3) ) ); +u_sh3y_20: ex4_sh3_y_b(20) <= not( (ex4_sh2(28) and ex4_shctl_04(2) ) or ( ex4_sh2(32) and ex4_shctl_04(3) ) ); +u_sh3y_21: ex4_sh3_y_b(21) <= not( (ex4_sh2(29) and ex4_shctl_04(2) ) or ( ex4_sh2(33) and ex4_shctl_04(3) ) ); +u_sh3y_22: ex4_sh3_y_b(22) <= not( (ex4_sh2(30) and ex4_shctl_04(2) ) or ( ex4_sh2(34) and ex4_shctl_04(3) ) ); +u_sh3y_23: ex4_sh3_y_b(23) <= not( (ex4_sh2(31) and ex4_shctl_04(2) ) or ( ex4_sh2(35) and ex4_shctl_04(3) ) ); +u_sh3y_24: ex4_sh3_y_b(24) <= not( (ex4_sh2(32) and ex4_shctl_04(2) ) or ( ex4_sh2(36) and ex4_shctl_04(3) ) ); +u_sh3y_25: ex4_sh3_y_b(25) <= not( (ex4_sh2(33) and ex4_shctl_04(2) ) or ( ex4_sh2(37) and ex4_shctl_04(3) ) ); +u_sh3y_26: ex4_sh3_y_b(26) <= not( (ex4_sh2(34) and ex4_shctl_04(2) ) or ( ex4_sh2(38) and ex4_shctl_04(3) ) ); +u_sh3y_27: ex4_sh3_y_b(27) <= not( (ex4_sh2(35) and ex4_shctl_04(2) ) or ( ex4_sh2(39) and ex4_shctl_04(3) ) ); +u_sh3y_28: ex4_sh3_y_b(28) <= not( (ex4_sh2(36) and ex4_shctl_04(2) ) or ( ex4_sh2(40) and ex4_shctl_04(3) ) ); +u_sh3y_29: ex4_sh3_y_b(29) <= not( (ex4_sh2(37) and ex4_shctl_04(2) ) or ( ex4_sh2(41) and ex4_shctl_04(3) ) ); +u_sh3y_30: ex4_sh3_y_b(30) <= not( (ex4_sh2(38) and ex4_shctl_04(2) ) or ( ex4_sh2(42) and ex4_shctl_04(3) ) ); +u_sh3y_31: ex4_sh3_y_b(31) <= not( (ex4_sh2(39) and ex4_shctl_04(2) ) or ( ex4_sh2(43) and ex4_shctl_04(3) ) ); +u_sh3y_32: ex4_sh3_y_b(32) <= not( (ex4_sh2(40) and ex4_shctl_04(2) ) or ( ex4_sh2(44) and ex4_shctl_04(3) ) ); +u_sh3y_33: ex4_sh3_y_b(33) <= not( (ex4_sh2(41) and ex4_shctl_04(2) ) or ( ex4_sh2(45) and ex4_shctl_04(3) ) ); +u_sh3y_34: ex4_sh3_y_b(34) <= not( (ex4_sh2(42) and ex4_shctl_04(2) ) or ( ex4_sh2(46) and ex4_shctl_04(3) ) ); +u_sh3y_35: ex4_sh3_y_b(35) <= not( (ex4_sh2(43) and ex4_shctl_04(2) ) or ( ex4_sh2(47) and ex4_shctl_04(3) ) ); +u_sh3y_36: ex4_sh3_y_b(36) <= not( (ex4_sh2(44) and ex4_shctl_04(2) ) or ( ex4_sh2(48) and ex4_shctl_04(3) ) ); +u_sh3y_37: ex4_sh3_y_b(37) <= not( (ex4_sh2(45) and ex4_shctl_04(2) ) or ( ex4_sh2(49) and ex4_shctl_04(3) ) ); +u_sh3y_38: ex4_sh3_y_b(38) <= not( (ex4_sh2(46) and ex4_shctl_04(2) ) or ( ex4_sh2(50) and ex4_shctl_04(3) ) ); +u_sh3y_39: ex4_sh3_y_b(39) <= not( (ex4_sh2(47) and ex4_shctl_04(2) ) or ( ex4_sh2(51) and ex4_shctl_04(3) ) ); +u_sh3y_40: ex4_sh3_y_b(40) <= not( (ex4_sh2(48) and ex4_shctl_04(2) ) or ( ex4_sh2(52) and ex4_shctl_04(3) ) ); +u_sh3y_41: ex4_sh3_y_b(41) <= not( (ex4_sh2(49) and ex4_shctl_04(2) ) or ( ex4_sh2(53) and ex4_shctl_04(3) ) ); +u_sh3y_42: ex4_sh3_y_b(42) <= not( (ex4_sh2(50) and ex4_shctl_04(2) ) or ( ex4_sh2(54) and ex4_shctl_04(3) ) ); +u_sh3y_43: ex4_sh3_y_b(43) <= not( (ex4_sh2(51) and ex4_shctl_04(2) ) or ( ex4_sh2(55) and ex4_shctl_04(3) ) ); +u_sh3y_44: ex4_sh3_y_b(44) <= not( (ex4_sh2(52) and ex4_shctl_04(2) ) or ( ex4_sh2(56) and ex4_shctl_04(3) ) ); +u_sh3y_45: ex4_sh3_y_b(45) <= not( (ex4_sh2(53) and ex4_shctl_04(2) ) or ( ex4_sh2(57) and ex4_shctl_04(3) ) ); +u_sh3y_46: ex4_sh3_y_b(46) <= not( (ex4_sh2(54) and ex4_shctl_04(2) ) or ( ex4_sh2(58) and ex4_shctl_04(3) ) ); +u_sh3y_47: ex4_sh3_y_b(47) <= not( (ex4_sh2(55) and ex4_shctl_04(2) ) or ( ex4_sh2(59) and ex4_shctl_04(3) ) ); +u_sh3y_48: ex4_sh3_y_b(48) <= not( (ex4_sh2(56) and ex4_shctl_04(2) ) or ( ex4_sh2(60) and ex4_shctl_04(3) ) ); +u_sh3y_49: ex4_sh3_y_b(49) <= not( (ex4_sh2(57) and ex4_shctl_04(2) ) or ( ex4_sh2(61) and ex4_shctl_04(3) ) ); +u_sh3y_50: ex4_sh3_y_b(50) <= not( (ex4_sh2(58) and ex4_shctl_04(2) ) or ( ex4_sh2(62) and ex4_shctl_04(3) ) ); +u_sh3y_51: ex4_sh3_y_b(51) <= not( (ex4_sh2(59) and ex4_shctl_04(2) ) or ( ex4_sh2(63) and ex4_shctl_04(3) ) ); +u_sh3y_52: ex4_sh3_y_b(52) <= not( (ex4_sh2(60) and ex4_shctl_04(2) ) or ( ex4_sh2(64) and ex4_shctl_04(3) ) ); +u_sh3y_53: ex4_sh3_y_b(53) <= not( (ex4_sh2(61) and ex4_shctl_04(2) ) or ( ex4_sh2(65) and ex4_shctl_04(3) ) ); +u_sh3y_54: ex4_sh3_y_b(54) <= not( (ex4_sh2(62) and ex4_shctl_04(2) ) or ( ex4_sh2(66) and ex4_shctl_04(3) ) ); +u_sh3y_55: ex4_sh3_y_b(55) <= not( (ex4_sh2(63) and ex4_shctl_04(2) ) or ( ex4_sh2(67) and ex4_shctl_04(3) ) ); +u_sh3y_56: ex4_sh3_y_b(56) <= not( (ex4_sh2(64) and ex4_shctl_04(2) ) or ( ex4_sh2(68) and ex4_shctl_04(3) ) ); +u_sh3y_57: ex4_sh3_y_b(57) <= not( (ex4_sh2(65) and ex4_shctl_04(2) ) or ( ex4_sh2(69) and ex4_shctl_04(3) ) ); + +u_sh3_00: ex4_sh3( 0) <= not( ex4_sh3_x_b( 0) and ex4_sh3_y_b( 0) ); +u_sh3_01: ex4_sh3( 1) <= not( ex4_sh3_x_b( 1) and ex4_sh3_y_b( 1) ); +u_sh3_02: ex4_sh3( 2) <= not( ex4_sh3_x_b( 2) and ex4_sh3_y_b( 2) ); +u_sh3_03: ex4_sh3( 3) <= not( ex4_sh3_x_b( 3) and ex4_sh3_y_b( 3) ); +u_sh3_04: ex4_sh3( 4) <= not( ex4_sh3_x_b( 4) and ex4_sh3_y_b( 4) ); +u_sh3_05: ex4_sh3( 5) <= not( ex4_sh3_x_b( 5) and ex4_sh3_y_b( 5) ); +u_sh3_06: ex4_sh3( 6) <= not( ex4_sh3_x_b( 6) and ex4_sh3_y_b( 6) ); +u_sh3_07: ex4_sh3( 7) <= not( ex4_sh3_x_b( 7) and ex4_sh3_y_b( 7) ); +u_sh3_08: ex4_sh3( 8) <= not( ex4_sh3_x_b( 8) and ex4_sh3_y_b( 8) ); +u_sh3_09: ex4_sh3( 9) <= not( ex4_sh3_x_b( 9) and ex4_sh3_y_b( 9) ); +u_sh3_10: ex4_sh3(10) <= not( ex4_sh3_x_b(10) and ex4_sh3_y_b(10) ); +u_sh3_11: ex4_sh3(11) <= not( ex4_sh3_x_b(11) and ex4_sh3_y_b(11) ); +u_sh3_12: ex4_sh3(12) <= not( ex4_sh3_x_b(12) and ex4_sh3_y_b(12) ); +u_sh3_13: ex4_sh3(13) <= not( ex4_sh3_x_b(13) and ex4_sh3_y_b(13) ); +u_sh3_14: ex4_sh3(14) <= not( ex4_sh3_x_b(14) and ex4_sh3_y_b(14) ); +u_sh3_15: ex4_sh3(15) <= not( ex4_sh3_x_b(15) and ex4_sh3_y_b(15) ); +u_sh3_16: ex4_sh3(16) <= not( ex4_sh3_x_b(16) and ex4_sh3_y_b(16) ); +u_sh3_17: ex4_sh3(17) <= not( ex4_sh3_x_b(17) and ex4_sh3_y_b(17) ); +u_sh3_18: ex4_sh3(18) <= not( ex4_sh3_x_b(18) and ex4_sh3_y_b(18) ); +u_sh3_19: ex4_sh3(19) <= not( ex4_sh3_x_b(19) and ex4_sh3_y_b(19) ); +u_sh3_20: ex4_sh3(20) <= not( ex4_sh3_x_b(20) and ex4_sh3_y_b(20) ); +u_sh3_21: ex4_sh3(21) <= not( ex4_sh3_x_b(21) and ex4_sh3_y_b(21) ); +u_sh3_22: ex4_sh3(22) <= not( ex4_sh3_x_b(22) and ex4_sh3_y_b(22) ); +u_sh3_23: ex4_sh3(23) <= not( ex4_sh3_x_b(23) and ex4_sh3_y_b(23) ); +u_sh3_24: ex4_sh3(24) <= not( ex4_sh3_x_b(24) and ex4_sh3_y_b(24) ); +u_sh3_25: ex4_sh3(25) <= not( ex4_sh3_x_b(25) and ex4_sh3_y_b(25) ); +u_sh3_26: ex4_sh3(26) <= not( ex4_sh3_x_b(26) and ex4_sh3_y_b(26) ); +u_sh3_27: ex4_sh3(27) <= not( ex4_sh3_x_b(27) and ex4_sh3_y_b(27) ); +u_sh3_28: ex4_sh3(28) <= not( ex4_sh3_x_b(28) and ex4_sh3_y_b(28) ); +u_sh3_29: ex4_sh3(29) <= not( ex4_sh3_x_b(29) and ex4_sh3_y_b(29) ); +u_sh3_30: ex4_sh3(30) <= not( ex4_sh3_x_b(30) and ex4_sh3_y_b(30) ); +u_sh3_31: ex4_sh3(31) <= not( ex4_sh3_x_b(31) and ex4_sh3_y_b(31) ); +u_sh3_32: ex4_sh3(32) <= not( ex4_sh3_x_b(32) and ex4_sh3_y_b(32) ); +u_sh3_33: ex4_sh3(33) <= not( ex4_sh3_x_b(33) and ex4_sh3_y_b(33) ); +u_sh3_34: ex4_sh3(34) <= not( ex4_sh3_x_b(34) and ex4_sh3_y_b(34) ); +u_sh3_35: ex4_sh3(35) <= not( ex4_sh3_x_b(35) and ex4_sh3_y_b(35) ); +u_sh3_36: ex4_sh3(36) <= not( ex4_sh3_x_b(36) and ex4_sh3_y_b(36) ); +u_sh3_37: ex4_sh3(37) <= not( ex4_sh3_x_b(37) and ex4_sh3_y_b(37) ); +u_sh3_38: ex4_sh3(38) <= not( ex4_sh3_x_b(38) and ex4_sh3_y_b(38) ); +u_sh3_39: ex4_sh3(39) <= not( ex4_sh3_x_b(39) and ex4_sh3_y_b(39) ); +u_sh3_40: ex4_sh3(40) <= not( ex4_sh3_x_b(40) and ex4_sh3_y_b(40) ); +u_sh3_41: ex4_sh3(41) <= not( ex4_sh3_x_b(41) and ex4_sh3_y_b(41) ); +u_sh3_42: ex4_sh3(42) <= not( ex4_sh3_x_b(42) and ex4_sh3_y_b(42) ); +u_sh3_43: ex4_sh3(43) <= not( ex4_sh3_x_b(43) and ex4_sh3_y_b(43) ); +u_sh3_44: ex4_sh3(44) <= not( ex4_sh3_x_b(44) and ex4_sh3_y_b(44) ); +u_sh3_45: ex4_sh3(45) <= not( ex4_sh3_x_b(45) and ex4_sh3_y_b(45) ); +u_sh3_46: ex4_sh3(46) <= not( ex4_sh3_x_b(46) and ex4_sh3_y_b(46) ); +u_sh3_47: ex4_sh3(47) <= not( ex4_sh3_x_b(47) and ex4_sh3_y_b(47) ); +u_sh3_48: ex4_sh3(48) <= not( ex4_sh3_x_b(48) and ex4_sh3_y_b(48) ); +u_sh3_49: ex4_sh3(49) <= not( ex4_sh3_x_b(49) and ex4_sh3_y_b(49) ); +u_sh3_50: ex4_sh3(50) <= not( ex4_sh3_x_b(50) and ex4_sh3_y_b(50) ); +u_sh3_51: ex4_sh3(51) <= not( ex4_sh3_x_b(51) and ex4_sh3_y_b(51) ); +u_sh3_52: ex4_sh3(52) <= not( ex4_sh3_x_b(52) and ex4_sh3_y_b(52) ); +u_sh3_53: ex4_sh3(53) <= not( ex4_sh3_x_b(53) and ex4_sh3_y_b(53) ); +u_sh3_54: ex4_sh3(54) <= not( ex4_sh3_x_b(54) and ex4_sh3_y_b(54) ); +u_sh3_55: ex4_sh3(55) <= not( ex4_sh3_x_b(55) and ex4_sh3_y_b(55) ); +u_sh3_56: ex4_sh3(56) <= not( ex4_sh3_x_b(56) and ex4_sh3_y_b(56) ); +u_sh3_57: ex4_sh3(57) <= not( ex4_sh3_x_b(57) and ex4_sh3_y_b(57) ); + + ----------------------------------------------- + +u_sh4x_00cp1: ex4_sh4_x_00_b <= not( (ex4_sh3( 0) and ex4_shctl_01(0) ) or ( ex4_sh3( 1) and ex4_shctl_01(1) ) ); +u_sh4x_00: ex4_sh4_x_b( 0) <= not( (ex4_sh3( 0) and ex4_shctl_01(0) ) or ( ex4_sh3( 1) and ex4_shctl_01(1) ) ); +u_sh4x_01: ex4_sh4_x_b( 1) <= not( (ex4_sh3( 1) and ex4_shctl_01(0) ) or ( ex4_sh3( 2) and ex4_shctl_01(1) ) ); +u_sh4x_02: ex4_sh4_x_b( 2) <= not( (ex4_sh3( 2) and ex4_shctl_01(0) ) or ( ex4_sh3( 3) and ex4_shctl_01(1) ) ); +u_sh4x_03: ex4_sh4_x_b( 3) <= not( (ex4_sh3( 3) and ex4_shctl_01(0) ) or ( ex4_sh3( 4) and ex4_shctl_01(1) ) ); +u_sh4x_04: ex4_sh4_x_b( 4) <= not( (ex4_sh3( 4) and ex4_shctl_01(0) ) or ( ex4_sh3( 5) and ex4_shctl_01(1) ) ); +u_sh4x_05: ex4_sh4_x_b( 5) <= not( (ex4_sh3( 5) and ex4_shctl_01(0) ) or ( ex4_sh3( 6) and ex4_shctl_01(1) ) ); +u_sh4x_06: ex4_sh4_x_b( 6) <= not( (ex4_sh3( 6) and ex4_shctl_01(0) ) or ( ex4_sh3( 7) and ex4_shctl_01(1) ) ); +u_sh4x_07: ex4_sh4_x_b( 7) <= not( (ex4_sh3( 7) and ex4_shctl_01(0) ) or ( ex4_sh3( 8) and ex4_shctl_01(1) ) ); +u_sh4x_08: ex4_sh4_x_b( 8) <= not( (ex4_sh3( 8) and ex4_shctl_01(0) ) or ( ex4_sh3( 9) and ex4_shctl_01(1) ) ); +u_sh4x_09: ex4_sh4_x_b( 9) <= not( (ex4_sh3( 9) and ex4_shctl_01(0) ) or ( ex4_sh3(10) and ex4_shctl_01(1) ) ); +u_sh4x_10: ex4_sh4_x_b(10) <= not( (ex4_sh3(10) and ex4_shctl_01(0) ) or ( ex4_sh3(11) and ex4_shctl_01(1) ) ); +u_sh4x_11: ex4_sh4_x_b(11) <= not( (ex4_sh3(11) and ex4_shctl_01(0) ) or ( ex4_sh3(12) and ex4_shctl_01(1) ) ); +u_sh4x_12: ex4_sh4_x_b(12) <= not( (ex4_sh3(12) and ex4_shctl_01(0) ) or ( ex4_sh3(13) and ex4_shctl_01(1) ) ); +u_sh4x_13: ex4_sh4_x_b(13) <= not( (ex4_sh3(13) and ex4_shctl_01(0) ) or ( ex4_sh3(14) and ex4_shctl_01(1) ) ); +u_sh4x_14: ex4_sh4_x_b(14) <= not( (ex4_sh3(14) and ex4_shctl_01(0) ) or ( ex4_sh3(15) and ex4_shctl_01(1) ) ); +u_sh4x_15: ex4_sh4_x_b(15) <= not( (ex4_sh3(15) and ex4_shctl_01(0) ) or ( ex4_sh3(16) and ex4_shctl_01(1) ) ); +u_sh4x_16: ex4_sh4_x_b(16) <= not( (ex4_sh3(16) and ex4_shctl_01(0) ) or ( ex4_sh3(17) and ex4_shctl_01(1) ) ); +u_sh4x_17: ex4_sh4_x_b(17) <= not( (ex4_sh3(17) and ex4_shctl_01(0) ) or ( ex4_sh3(18) and ex4_shctl_01(1) ) ); +u_sh4x_18: ex4_sh4_x_b(18) <= not( (ex4_sh3(18) and ex4_shctl_01(0) ) or ( ex4_sh3(19) and ex4_shctl_01(1) ) ); +u_sh4x_19: ex4_sh4_x_b(19) <= not( (ex4_sh3(19) and ex4_shctl_01(0) ) or ( ex4_sh3(20) and ex4_shctl_01(1) ) ); +u_sh4x_20: ex4_sh4_x_b(20) <= not( (ex4_sh3(20) and ex4_shctl_01(0) ) or ( ex4_sh3(21) and ex4_shctl_01(1) ) ); +u_sh4x_21: ex4_sh4_x_b(21) <= not( (ex4_sh3(21) and ex4_shctl_01(0) ) or ( ex4_sh3(22) and ex4_shctl_01(1) ) ); +u_sh4x_22: ex4_sh4_x_b(22) <= not( (ex4_sh3(22) and ex4_shctl_01(0) ) or ( ex4_sh3(23) and ex4_shctl_01(1) ) ); +u_sh4x_23: ex4_sh4_x_b(23) <= not( (ex4_sh3(23) and ex4_shctl_01(0) ) or ( ex4_sh3(24) and ex4_shctl_01(1) ) ); +u_sh4x_24: ex4_sh4_x_b(24) <= not( (ex4_sh3(24) and ex4_shctl_01(0) ) or ( ex4_sh3(25) and ex4_shctl_01(1) ) ); +u_sh4x_25: ex4_sh4_x_b(25) <= not( (ex4_sh3(25) and ex4_shctl_01(0) ) or ( ex4_sh3(26) and ex4_shctl_01(1) ) ); +u_sh4x_26: ex4_sh4_x_b(26) <= not( (ex4_sh3(26) and ex4_shctl_01(0) ) or ( ex4_sh3(27) and ex4_shctl_01(1) ) ); +u_sh4x_27: ex4_sh4_x_b(27) <= not( (ex4_sh3(27) and ex4_shctl_01(0) ) or ( ex4_sh3(28) and ex4_shctl_01(1) ) ); +u_sh4x_28: ex4_sh4_x_b(28) <= not( (ex4_sh3(28) and ex4_shctl_01(0) ) or ( ex4_sh3(29) and ex4_shctl_01(1) ) ); +u_sh4x_29: ex4_sh4_x_b(29) <= not( (ex4_sh3(29) and ex4_shctl_01(0) ) or ( ex4_sh3(30) and ex4_shctl_01(1) ) ); +u_sh4x_30: ex4_sh4_x_b(30) <= not( (ex4_sh3(30) and ex4_shctl_01(0) ) or ( ex4_sh3(31) and ex4_shctl_01(1) ) ); +u_sh4x_31: ex4_sh4_x_b(31) <= not( (ex4_sh3(31) and ex4_shctl_01(0) ) or ( ex4_sh3(32) and ex4_shctl_01(1) ) ); +u_sh4x_32: ex4_sh4_x_b(32) <= not( (ex4_sh3(32) and ex4_shctl_01(0) ) or ( ex4_sh3(33) and ex4_shctl_01(1) ) ); +u_sh4x_33: ex4_sh4_x_b(33) <= not( (ex4_sh3(33) and ex4_shctl_01(0) ) or ( ex4_sh3(34) and ex4_shctl_01(1) ) ); +u_sh4x_34: ex4_sh4_x_b(34) <= not( (ex4_sh3(34) and ex4_shctl_01(0) ) or ( ex4_sh3(35) and ex4_shctl_01(1) ) ); +u_sh4x_35: ex4_sh4_x_b(35) <= not( (ex4_sh3(35) and ex4_shctl_01(0) ) or ( ex4_sh3(36) and ex4_shctl_01(1) ) ); +u_sh4x_36: ex4_sh4_x_b(36) <= not( (ex4_sh3(36) and ex4_shctl_01(0) ) or ( ex4_sh3(37) and ex4_shctl_01(1) ) ); +u_sh4x_37: ex4_sh4_x_b(37) <= not( (ex4_sh3(37) and ex4_shctl_01(0) ) or ( ex4_sh3(38) and ex4_shctl_01(1) ) ); +u_sh4x_38: ex4_sh4_x_b(38) <= not( (ex4_sh3(38) and ex4_shctl_01(0) ) or ( ex4_sh3(39) and ex4_shctl_01(1) ) ); +u_sh4x_39: ex4_sh4_x_b(39) <= not( (ex4_sh3(39) and ex4_shctl_01(0) ) or ( ex4_sh3(40) and ex4_shctl_01(1) ) ); +u_sh4x_40: ex4_sh4_x_b(40) <= not( (ex4_sh3(40) and ex4_shctl_01(0) ) or ( ex4_sh3(41) and ex4_shctl_01(1) ) ); +u_sh4x_41: ex4_sh4_x_b(41) <= not( (ex4_sh3(41) and ex4_shctl_01(0) ) or ( ex4_sh3(42) and ex4_shctl_01(1) ) ); +u_sh4x_42: ex4_sh4_x_b(42) <= not( (ex4_sh3(42) and ex4_shctl_01(0) ) or ( ex4_sh3(43) and ex4_shctl_01(1) ) ); +u_sh4x_43: ex4_sh4_x_b(43) <= not( (ex4_sh3(43) and ex4_shctl_01(0) ) or ( ex4_sh3(44) and ex4_shctl_01(1) ) ); +u_sh4x_44: ex4_sh4_x_b(44) <= not( (ex4_sh3(44) and ex4_shctl_01(0) ) or ( ex4_sh3(45) and ex4_shctl_01(1) ) ); +u_sh4x_45: ex4_sh4_x_b(45) <= not( (ex4_sh3(45) and ex4_shctl_01(0) ) or ( ex4_sh3(46) and ex4_shctl_01(1) ) ); +u_sh4x_46: ex4_sh4_x_b(46) <= not( (ex4_sh3(46) and ex4_shctl_01(0) ) or ( ex4_sh3(47) and ex4_shctl_01(1) ) ); +u_sh4x_47: ex4_sh4_x_b(47) <= not( (ex4_sh3(47) and ex4_shctl_01(0) ) or ( ex4_sh3(48) and ex4_shctl_01(1) ) ); +u_sh4x_48: ex4_sh4_x_b(48) <= not( (ex4_sh3(48) and ex4_shctl_01(0) ) or ( ex4_sh3(49) and ex4_shctl_01(1) ) ); +u_sh4x_49: ex4_sh4_x_b(49) <= not( (ex4_sh3(49) and ex4_shctl_01(0) ) or ( ex4_sh3(50) and ex4_shctl_01(1) ) ); +u_sh4x_50: ex4_sh4_x_b(50) <= not( (ex4_sh3(50) and ex4_shctl_01(0) ) or ( ex4_sh3(51) and ex4_shctl_01(1) ) ); +u_sh4x_51: ex4_sh4_x_b(51) <= not( (ex4_sh3(51) and ex4_shctl_01(0) ) or ( ex4_sh3(52) and ex4_shctl_01(1) ) ); +u_sh4x_52: ex4_sh4_x_b(52) <= not( (ex4_sh3(52) and ex4_shctl_01(0) ) or ( ex4_sh3(53) and ex4_shctl_01(1) ) ); +u_sh4x_53: ex4_sh4_x_b(53) <= not( (ex4_sh3(53) and ex4_shctl_01(0) ) or ( ex4_sh3(54) and ex4_shctl_01(1) ) ); +u_sh4x_54: ex4_sh4_x_b(54) <= not( (ex4_sh3(54) and ex4_shctl_01(0) ) or ( ex4_sh3(55) and ex4_shctl_01(1) ) ); + +u_sh4y_00cp1: ex4_sh4_y_00_b <= not( (ex4_sh3( 2) and ex4_shctl_01(2) ) or ( ex4_sh3( 3) and ex4_shctl_01(3) ) ); +u_sh4y_00: ex4_sh4_y_b( 0) <= not( (ex4_sh3( 2) and ex4_shctl_01(2) ) or ( ex4_sh3( 3) and ex4_shctl_01(3) ) ); +u_sh4y_01: ex4_sh4_y_b( 1) <= not( (ex4_sh3( 3) and ex4_shctl_01(2) ) or ( ex4_sh3( 4) and ex4_shctl_01(3) ) ); +u_sh4y_02: ex4_sh4_y_b( 2) <= not( (ex4_sh3( 4) and ex4_shctl_01(2) ) or ( ex4_sh3( 5) and ex4_shctl_01(3) ) ); +u_sh4y_03: ex4_sh4_y_b( 3) <= not( (ex4_sh3( 5) and ex4_shctl_01(2) ) or ( ex4_sh3( 6) and ex4_shctl_01(3) ) ); +u_sh4y_04: ex4_sh4_y_b( 4) <= not( (ex4_sh3( 6) and ex4_shctl_01(2) ) or ( ex4_sh3( 7) and ex4_shctl_01(3) ) ); +u_sh4y_05: ex4_sh4_y_b( 5) <= not( (ex4_sh3( 7) and ex4_shctl_01(2) ) or ( ex4_sh3( 8) and ex4_shctl_01(3) ) ); +u_sh4y_06: ex4_sh4_y_b( 6) <= not( (ex4_sh3( 8) and ex4_shctl_01(2) ) or ( ex4_sh3( 9) and ex4_shctl_01(3) ) ); +u_sh4y_07: ex4_sh4_y_b( 7) <= not( (ex4_sh3( 9) and ex4_shctl_01(2) ) or ( ex4_sh3(10) and ex4_shctl_01(3) ) ); +u_sh4y_08: ex4_sh4_y_b( 8) <= not( (ex4_sh3(10) and ex4_shctl_01(2) ) or ( ex4_sh3(11) and ex4_shctl_01(3) ) ); +u_sh4y_09: ex4_sh4_y_b( 9) <= not( (ex4_sh3(11) and ex4_shctl_01(2) ) or ( ex4_sh3(12) and ex4_shctl_01(3) ) ); +u_sh4y_10: ex4_sh4_y_b(10) <= not( (ex4_sh3(12) and ex4_shctl_01(2) ) or ( ex4_sh3(13) and ex4_shctl_01(3) ) ); +u_sh4y_11: ex4_sh4_y_b(11) <= not( (ex4_sh3(13) and ex4_shctl_01(2) ) or ( ex4_sh3(14) and ex4_shctl_01(3) ) ); +u_sh4y_12: ex4_sh4_y_b(12) <= not( (ex4_sh3(14) and ex4_shctl_01(2) ) or ( ex4_sh3(15) and ex4_shctl_01(3) ) ); +u_sh4y_13: ex4_sh4_y_b(13) <= not( (ex4_sh3(15) and ex4_shctl_01(2) ) or ( ex4_sh3(16) and ex4_shctl_01(3) ) ); +u_sh4y_14: ex4_sh4_y_b(14) <= not( (ex4_sh3(16) and ex4_shctl_01(2) ) or ( ex4_sh3(17) and ex4_shctl_01(3) ) ); +u_sh4y_15: ex4_sh4_y_b(15) <= not( (ex4_sh3(17) and ex4_shctl_01(2) ) or ( ex4_sh3(18) and ex4_shctl_01(3) ) ); +u_sh4y_16: ex4_sh4_y_b(16) <= not( (ex4_sh3(18) and ex4_shctl_01(2) ) or ( ex4_sh3(19) and ex4_shctl_01(3) ) ); +u_sh4y_17: ex4_sh4_y_b(17) <= not( (ex4_sh3(19) and ex4_shctl_01(2) ) or ( ex4_sh3(20) and ex4_shctl_01(3) ) ); +u_sh4y_18: ex4_sh4_y_b(18) <= not( (ex4_sh3(20) and ex4_shctl_01(2) ) or ( ex4_sh3(21) and ex4_shctl_01(3) ) ); +u_sh4y_19: ex4_sh4_y_b(19) <= not( (ex4_sh3(21) and ex4_shctl_01(2) ) or ( ex4_sh3(22) and ex4_shctl_01(3) ) ); +u_sh4y_20: ex4_sh4_y_b(20) <= not( (ex4_sh3(22) and ex4_shctl_01(2) ) or ( ex4_sh3(23) and ex4_shctl_01(3) ) ); +u_sh4y_21: ex4_sh4_y_b(21) <= not( (ex4_sh3(23) and ex4_shctl_01(2) ) or ( ex4_sh3(24) and ex4_shctl_01(3) ) ); +u_sh4y_22: ex4_sh4_y_b(22) <= not( (ex4_sh3(24) and ex4_shctl_01(2) ) or ( ex4_sh3(25) and ex4_shctl_01(3) ) ); +u_sh4y_23: ex4_sh4_y_b(23) <= not( (ex4_sh3(25) and ex4_shctl_01(2) ) or ( ex4_sh3(26) and ex4_shctl_01(3) ) ); +u_sh4y_24: ex4_sh4_y_b(24) <= not( (ex4_sh3(26) and ex4_shctl_01(2) ) or ( ex4_sh3(27) and ex4_shctl_01(3) ) ); +u_sh4y_25: ex4_sh4_y_b(25) <= not( (ex4_sh3(27) and ex4_shctl_01(2) ) or ( ex4_sh3(28) and ex4_shctl_01(3) ) ); +u_sh4y_26: ex4_sh4_y_b(26) <= not( (ex4_sh3(28) and ex4_shctl_01(2) ) or ( ex4_sh3(29) and ex4_shctl_01(3) ) ); +u_sh4y_27: ex4_sh4_y_b(27) <= not( (ex4_sh3(29) and ex4_shctl_01(2) ) or ( ex4_sh3(30) and ex4_shctl_01(3) ) ); +u_sh4y_28: ex4_sh4_y_b(28) <= not( (ex4_sh3(30) and ex4_shctl_01(2) ) or ( ex4_sh3(31) and ex4_shctl_01(3) ) ); +u_sh4y_29: ex4_sh4_y_b(29) <= not( (ex4_sh3(31) and ex4_shctl_01(2) ) or ( ex4_sh3(32) and ex4_shctl_01(3) ) ); +u_sh4y_30: ex4_sh4_y_b(30) <= not( (ex4_sh3(32) and ex4_shctl_01(2) ) or ( ex4_sh3(33) and ex4_shctl_01(3) ) ); +u_sh4y_31: ex4_sh4_y_b(31) <= not( (ex4_sh3(33) and ex4_shctl_01(2) ) or ( ex4_sh3(34) and ex4_shctl_01(3) ) ); +u_sh4y_32: ex4_sh4_y_b(32) <= not( (ex4_sh3(34) and ex4_shctl_01(2) ) or ( ex4_sh3(35) and ex4_shctl_01(3) ) ); +u_sh4y_33: ex4_sh4_y_b(33) <= not( (ex4_sh3(35) and ex4_shctl_01(2) ) or ( ex4_sh3(36) and ex4_shctl_01(3) ) ); +u_sh4y_34: ex4_sh4_y_b(34) <= not( (ex4_sh3(36) and ex4_shctl_01(2) ) or ( ex4_sh3(37) and ex4_shctl_01(3) ) ); +u_sh4y_35: ex4_sh4_y_b(35) <= not( (ex4_sh3(37) and ex4_shctl_01(2) ) or ( ex4_sh3(38) and ex4_shctl_01(3) ) ); +u_sh4y_36: ex4_sh4_y_b(36) <= not( (ex4_sh3(38) and ex4_shctl_01(2) ) or ( ex4_sh3(39) and ex4_shctl_01(3) ) ); +u_sh4y_37: ex4_sh4_y_b(37) <= not( (ex4_sh3(39) and ex4_shctl_01(2) ) or ( ex4_sh3(40) and ex4_shctl_01(3) ) ); +u_sh4y_38: ex4_sh4_y_b(38) <= not( (ex4_sh3(40) and ex4_shctl_01(2) ) or ( ex4_sh3(41) and ex4_shctl_01(3) ) ); +u_sh4y_39: ex4_sh4_y_b(39) <= not( (ex4_sh3(41) and ex4_shctl_01(2) ) or ( ex4_sh3(42) and ex4_shctl_01(3) ) ); +u_sh4y_40: ex4_sh4_y_b(40) <= not( (ex4_sh3(42) and ex4_shctl_01(2) ) or ( ex4_sh3(43) and ex4_shctl_01(3) ) ); +u_sh4y_41: ex4_sh4_y_b(41) <= not( (ex4_sh3(43) and ex4_shctl_01(2) ) or ( ex4_sh3(44) and ex4_shctl_01(3) ) ); +u_sh4y_42: ex4_sh4_y_b(42) <= not( (ex4_sh3(44) and ex4_shctl_01(2) ) or ( ex4_sh3(45) and ex4_shctl_01(3) ) ); +u_sh4y_43: ex4_sh4_y_b(43) <= not( (ex4_sh3(45) and ex4_shctl_01(2) ) or ( ex4_sh3(46) and ex4_shctl_01(3) ) ); +u_sh4y_44: ex4_sh4_y_b(44) <= not( (ex4_sh3(46) and ex4_shctl_01(2) ) or ( ex4_sh3(47) and ex4_shctl_01(3) ) ); +u_sh4y_45: ex4_sh4_y_b(45) <= not( (ex4_sh3(47) and ex4_shctl_01(2) ) or ( ex4_sh3(48) and ex4_shctl_01(3) ) ); +u_sh4y_46: ex4_sh4_y_b(46) <= not( (ex4_sh3(48) and ex4_shctl_01(2) ) or ( ex4_sh3(49) and ex4_shctl_01(3) ) ); +u_sh4y_47: ex4_sh4_y_b(47) <= not( (ex4_sh3(49) and ex4_shctl_01(2) ) or ( ex4_sh3(50) and ex4_shctl_01(3) ) ); +u_sh4y_48: ex4_sh4_y_b(48) <= not( (ex4_sh3(50) and ex4_shctl_01(2) ) or ( ex4_sh3(51) and ex4_shctl_01(3) ) ); +u_sh4y_49: ex4_sh4_y_b(49) <= not( (ex4_sh3(51) and ex4_shctl_01(2) ) or ( ex4_sh3(52) and ex4_shctl_01(3) ) ); +u_sh4y_50: ex4_sh4_y_b(50) <= not( (ex4_sh3(52) and ex4_shctl_01(2) ) or ( ex4_sh3(53) and ex4_shctl_01(3) ) ); +u_sh4y_51: ex4_sh4_y_b(51) <= not( (ex4_sh3(53) and ex4_shctl_01(2) ) or ( ex4_sh3(54) and ex4_shctl_01(3) ) ); +u_sh4y_52: ex4_sh4_y_b(52) <= not( (ex4_sh3(54) and ex4_shctl_01(2) ) or ( ex4_sh3(55) and ex4_shctl_01(3) ) ); +u_sh4y_53: ex4_sh4_y_b(53) <= not( (ex4_sh3(55) and ex4_shctl_01(2) ) or ( ex4_sh3(56) and ex4_shctl_01(3) ) ); +u_sh4y_54: ex4_sh4_y_b(54) <= not( (ex4_sh3(56) and ex4_shctl_01(2) ) or ( ex4_sh3(57) and ex4_shctl_01(3) ) ); + +u_extra_cp1: ex4_shift_extra_cp1_b <= not(ex4_sh4_x_00_b and ex4_sh4_y_00_b ); -- shift extra when implicit bit is not 1 +u_extra_cp2: ex4_shift_extra_cp2_b <= not(ex4_sh4_x_00_b and ex4_sh4_y_00_b ); -- shift extra when implicit bit is not 1 +u_extra_cp3: ex4_shift_extra_00_cp3_b <= not(ex4_sh4_x_b(0) and ex4_sh4_y_b(0) ); -- shift extra when implicit bit is not 1 +u_extra_cp4: ex4_shift_extra_00_cp4_b <= not(ex4_sh4_x_b(0) and ex4_sh4_y_b(0) ); -- shift extra when implicit bit is not 1 + + ex4_shift_extra_cp1 <= not ex4_shift_extra_cp1_b ; --output-- + ex4_shift_extra_cp2 <= not ex4_shift_extra_cp2_b ; --output-- + + +u_extra_10_cp3: ex4_shift_extra_10_cp3 <= not ex4_shift_extra_00_cp3_b ; -- x4 +u_extra_20_cp3: ex4_shift_extra_20_cp3_b <= not ex4_shift_extra_10_cp3 ; -- x6 +u_extra_30_cp3: ex4_shift_extra_cp3 <= not ex4_shift_extra_20_cp3_b ; -- x9 + +u_extra_11_cp3: ex4_shift_extra_11_cp3 <= not ex4_shift_extra_00_cp3_b ; -- x2 +u_extra_21_cp3: ex4_shift_extra_21_cp3_b <= not ex4_shift_extra_11_cp3 ; -- x4 +u_extra_31_cp3: ex4_shift_extra_31_cp3 <= not ex4_shift_extra_21_cp3_b ; -- x6 +u_extra_41_cp3: ex4_shift_extra_cp3_b <= not ex4_shift_extra_31_cp3 ; -- x9 + +u_extra_10_cp4: ex4_shift_extra_10_cp4 <= not ex4_shift_extra_00_cp4_b ; -- x4 +u_extra_20_cp4: ex4_shift_extra_20_cp4_b <= not ex4_shift_extra_10_cp4 ; -- x6 +u_extra_30_cp4: ex4_shift_extra_cp4 <= not ex4_shift_extra_20_cp4_b ; -- x9 + +u_extra_11_cp4: ex4_shift_extra_11_cp4 <= not ex4_shift_extra_00_cp4_b ; -- x2 +u_extra_21_cp4: ex4_shift_extra_21_cp4_b <= not ex4_shift_extra_11_cp4 ; -- x4 +u_extra_31_cp4: ex4_shift_extra_31_cp4 <= not ex4_shift_extra_21_cp4_b ; -- x6 +u_extra_41_cp4: ex4_shift_extra_cp4_b <= not ex4_shift_extra_31_cp4 ; -- x9 + + + + + + +u_sh4_00: ex4_sh4( 0) <= not( ex4_sh4_x_b( 0) and ex4_sh4_y_b( 0) ); +u_sh4_01: ex4_sh4( 1) <= not( ex4_sh4_x_b( 1) and ex4_sh4_y_b( 1) ); +u_sh4_02: ex4_sh4( 2) <= not( ex4_sh4_x_b( 2) and ex4_sh4_y_b( 2) ); +u_sh4_03: ex4_sh4( 3) <= not( ex4_sh4_x_b( 3) and ex4_sh4_y_b( 3) ); +u_sh4_04: ex4_sh4( 4) <= not( ex4_sh4_x_b( 4) and ex4_sh4_y_b( 4) ); +u_sh4_05: ex4_sh4( 5) <= not( ex4_sh4_x_b( 5) and ex4_sh4_y_b( 5) ); +u_sh4_06: ex4_sh4( 6) <= not( ex4_sh4_x_b( 6) and ex4_sh4_y_b( 6) ); +u_sh4_07: ex4_sh4( 7) <= not( ex4_sh4_x_b( 7) and ex4_sh4_y_b( 7) ); +u_sh4_08: ex4_sh4( 8) <= not( ex4_sh4_x_b( 8) and ex4_sh4_y_b( 8) ); +u_sh4_09: ex4_sh4( 9) <= not( ex4_sh4_x_b( 9) and ex4_sh4_y_b( 9) ); +u_sh4_10: ex4_sh4(10) <= not( ex4_sh4_x_b(10) and ex4_sh4_y_b(10) ); +u_sh4_11: ex4_sh4(11) <= not( ex4_sh4_x_b(11) and ex4_sh4_y_b(11) ); +u_sh4_12: ex4_sh4(12) <= not( ex4_sh4_x_b(12) and ex4_sh4_y_b(12) ); +u_sh4_13: ex4_sh4(13) <= not( ex4_sh4_x_b(13) and ex4_sh4_y_b(13) ); +u_sh4_14: ex4_sh4(14) <= not( ex4_sh4_x_b(14) and ex4_sh4_y_b(14) ); +u_sh4_15: ex4_sh4(15) <= not( ex4_sh4_x_b(15) and ex4_sh4_y_b(15) ); +u_sh4_16: ex4_sh4(16) <= not( ex4_sh4_x_b(16) and ex4_sh4_y_b(16) ); +u_sh4_17: ex4_sh4(17) <= not( ex4_sh4_x_b(17) and ex4_sh4_y_b(17) ); +u_sh4_18: ex4_sh4(18) <= not( ex4_sh4_x_b(18) and ex4_sh4_y_b(18) ); +u_sh4_19: ex4_sh4(19) <= not( ex4_sh4_x_b(19) and ex4_sh4_y_b(19) ); +u_sh4_20: ex4_sh4(20) <= not( ex4_sh4_x_b(20) and ex4_sh4_y_b(20) ); +u_sh4_21: ex4_sh4(21) <= not( ex4_sh4_x_b(21) and ex4_sh4_y_b(21) ); +u_sh4_22: ex4_sh4(22) <= not( ex4_sh4_x_b(22) and ex4_sh4_y_b(22) ); +u_sh4_23: ex4_sh4(23) <= not( ex4_sh4_x_b(23) and ex4_sh4_y_b(23) ); +u_sh4_24: ex4_sh4(24) <= not( ex4_sh4_x_b(24) and ex4_sh4_y_b(24) ); +u_sh4_25: ex4_sh4(25) <= not( ex4_sh4_x_b(25) and ex4_sh4_y_b(25) ); +u_sh4_26: ex4_sh4(26) <= not( ex4_sh4_x_b(26) and ex4_sh4_y_b(26) ); +u_sh4_27: ex4_sh4(27) <= not( ex4_sh4_x_b(27) and ex4_sh4_y_b(27) ); +u_sh4_28: ex4_sh4(28) <= not( ex4_sh4_x_b(28) and ex4_sh4_y_b(28) ); +u_sh4_29: ex4_sh4(29) <= not( ex4_sh4_x_b(29) and ex4_sh4_y_b(29) ); +u_sh4_30: ex4_sh4(30) <= not( ex4_sh4_x_b(30) and ex4_sh4_y_b(30) ); +u_sh4_31: ex4_sh4(31) <= not( ex4_sh4_x_b(31) and ex4_sh4_y_b(31) ); +u_sh4_32: ex4_sh4(32) <= not( ex4_sh4_x_b(32) and ex4_sh4_y_b(32) ); +u_sh4_33: ex4_sh4(33) <= not( ex4_sh4_x_b(33) and ex4_sh4_y_b(33) ); +u_sh4_34: ex4_sh4(34) <= not( ex4_sh4_x_b(34) and ex4_sh4_y_b(34) ); +u_sh4_35: ex4_sh4(35) <= not( ex4_sh4_x_b(35) and ex4_sh4_y_b(35) ); +u_sh4_36: ex4_sh4(36) <= not( ex4_sh4_x_b(36) and ex4_sh4_y_b(36) ); +u_sh4_37: ex4_sh4(37) <= not( ex4_sh4_x_b(37) and ex4_sh4_y_b(37) ); +u_sh4_38: ex4_sh4(38) <= not( ex4_sh4_x_b(38) and ex4_sh4_y_b(38) ); +u_sh4_39: ex4_sh4(39) <= not( ex4_sh4_x_b(39) and ex4_sh4_y_b(39) ); +u_sh4_40: ex4_sh4(40) <= not( ex4_sh4_x_b(40) and ex4_sh4_y_b(40) ); +u_sh4_41: ex4_sh4(41) <= not( ex4_sh4_x_b(41) and ex4_sh4_y_b(41) ); +u_sh4_42: ex4_sh4(42) <= not( ex4_sh4_x_b(42) and ex4_sh4_y_b(42) ); +u_sh4_43: ex4_sh4(43) <= not( ex4_sh4_x_b(43) and ex4_sh4_y_b(43) ); +u_sh4_44: ex4_sh4(44) <= not( ex4_sh4_x_b(44) and ex4_sh4_y_b(44) ); +u_sh4_45: ex4_sh4(45) <= not( ex4_sh4_x_b(45) and ex4_sh4_y_b(45) ); +u_sh4_46: ex4_sh4(46) <= not( ex4_sh4_x_b(46) and ex4_sh4_y_b(46) ); +u_sh4_47: ex4_sh4(47) <= not( ex4_sh4_x_b(47) and ex4_sh4_y_b(47) ); +u_sh4_48: ex4_sh4(48) <= not( ex4_sh4_x_b(48) and ex4_sh4_y_b(48) ); +u_sh4_49: ex4_sh4(49) <= not( ex4_sh4_x_b(49) and ex4_sh4_y_b(49) ); +u_sh4_50: ex4_sh4(50) <= not( ex4_sh4_x_b(50) and ex4_sh4_y_b(50) ); +u_sh4_51: ex4_sh4(51) <= not( ex4_sh4_x_b(51) and ex4_sh4_y_b(51) ); +u_sh4_52: ex4_sh4(52) <= not( ex4_sh4_x_b(52) and ex4_sh4_y_b(52) ); +u_sh4_53: ex4_sh4(53) <= not( ex4_sh4_x_b(53) and ex4_sh4_y_b(53) ); +u_sh4_54: ex4_sh4(54) <= not( ex4_sh4_x_b(54) and ex4_sh4_y_b(54) ); + + ----------------------------------------------- + + +u_nrm_sh5x_00: ex4_sh5_x_b( 0) <= not( ex4_sh4( 0) and ex4_shift_extra_cp3_b ); +u_nrm_sh5x_01: ex4_sh5_x_b( 1) <= not( ex4_sh4( 1) and ex4_shift_extra_cp3_b ); +u_nrm_sh5x_02: ex4_sh5_x_b( 2) <= not( ex4_sh4( 2) and ex4_shift_extra_cp3_b ); +u_nrm_sh5x_03: ex4_sh5_x_b( 3) <= not( ex4_sh4( 3) and ex4_shift_extra_cp3_b ); +u_nrm_sh5x_04: ex4_sh5_x_b( 4) <= not( ex4_sh4( 4) and ex4_shift_extra_cp3_b ); +u_nrm_sh5x_05: ex4_sh5_x_b( 5) <= not( ex4_sh4( 5) and ex4_shift_extra_cp3_b ); +u_nrm_sh5x_06: ex4_sh5_x_b( 6) <= not( ex4_sh4( 6) and ex4_shift_extra_cp3_b ); +u_nrm_sh5x_07: ex4_sh5_x_b( 7) <= not( ex4_sh4( 7) and ex4_shift_extra_cp3_b ); +u_nrm_sh5x_08: ex4_sh5_x_b( 8) <= not( ex4_sh4( 8) and ex4_shift_extra_cp3_b ); +u_nrm_sh5x_09: ex4_sh5_x_b( 9) <= not( ex4_sh4( 9) and ex4_shift_extra_cp3_b ); +u_nrm_sh5x_10: ex4_sh5_x_b(10) <= not( ex4_sh4(10) and ex4_shift_extra_cp3_b ); +u_nrm_sh5x_11: ex4_sh5_x_b(11) <= not( ex4_sh4(11) and ex4_shift_extra_cp3_b ); +u_nrm_sh5x_12: ex4_sh5_x_b(12) <= not( ex4_sh4(12) and ex4_shift_extra_cp3_b ); +u_nrm_sh5x_13: ex4_sh5_x_b(13) <= not( ex4_sh4(13) and ex4_shift_extra_cp3_b ); +u_nrm_sh5x_14: ex4_sh5_x_b(14) <= not( ex4_sh4(14) and ex4_shift_extra_cp3_b ); +u_nrm_sh5x_15: ex4_sh5_x_b(15) <= not( ex4_sh4(15) and ex4_shift_extra_cp3_b ); +u_nrm_sh5x_16: ex4_sh5_x_b(16) <= not( ex4_sh4(16) and ex4_shift_extra_cp3_b ); +u_nrm_sh5x_17: ex4_sh5_x_b(17) <= not( ex4_sh4(17) and ex4_shift_extra_cp3_b ); +u_nrm_sh5x_18: ex4_sh5_x_b(18) <= not( ex4_sh4(18) and ex4_shift_extra_cp3_b ); +u_nrm_sh5x_19: ex4_sh5_x_b(19) <= not( ex4_sh4(19) and ex4_shift_extra_cp3_b ); +u_nrm_sh5x_20: ex4_sh5_x_b(20) <= not( ex4_sh4(20) and ex4_shift_extra_cp3_b ); +u_nrm_sh5x_21: ex4_sh5_x_b(21) <= not( ex4_sh4(21) and ex4_shift_extra_cp3_b ); +u_nrm_sh5x_22: ex4_sh5_x_b(22) <= not( ex4_sh4(22) and ex4_shift_extra_cp3_b ); +u_nrm_sh5x_23: ex4_sh5_x_b(23) <= not( ex4_sh4(23) and ex4_shift_extra_cp3_b ); +u_nrm_sh5x_24: ex4_sh5_x_b(24) <= not( ex4_sh4(24) and ex4_shift_extra_cp3_b ); +u_nrm_sh5x_25: ex4_sh5_x_b(25) <= not( ex4_sh4(25) and ex4_shift_extra_cp3_b ); +u_nrm_sh5x_26: ex4_sh5_x_b(26) <= not( ex4_sh4(26) and ex4_shift_extra_cp4_b ); +u_nrm_sh5x_27: ex4_sh5_x_b(27) <= not( ex4_sh4(27) and ex4_shift_extra_cp4_b ); +u_nrm_sh5x_28: ex4_sh5_x_b(28) <= not( ex4_sh4(28) and ex4_shift_extra_cp4_b ); +u_nrm_sh5x_29: ex4_sh5_x_b(29) <= not( ex4_sh4(29) and ex4_shift_extra_cp4_b ); +u_nrm_sh5x_30: ex4_sh5_x_b(30) <= not( ex4_sh4(30) and ex4_shift_extra_cp4_b ); +u_nrm_sh5x_31: ex4_sh5_x_b(31) <= not( ex4_sh4(31) and ex4_shift_extra_cp4_b ); +u_nrm_sh5x_32: ex4_sh5_x_b(32) <= not( ex4_sh4(32) and ex4_shift_extra_cp4_b ); +u_nrm_sh5x_33: ex4_sh5_x_b(33) <= not( ex4_sh4(33) and ex4_shift_extra_cp4_b ); +u_nrm_sh5x_34: ex4_sh5_x_b(34) <= not( ex4_sh4(34) and ex4_shift_extra_cp4_b ); +u_nrm_sh5x_35: ex4_sh5_x_b(35) <= not( ex4_sh4(35) and ex4_shift_extra_cp4_b ); +u_nrm_sh5x_36: ex4_sh5_x_b(36) <= not( ex4_sh4(36) and ex4_shift_extra_cp4_b ); +u_nrm_sh5x_37: ex4_sh5_x_b(37) <= not( ex4_sh4(37) and ex4_shift_extra_cp4_b ); +u_nrm_sh5x_38: ex4_sh5_x_b(38) <= not( ex4_sh4(38) and ex4_shift_extra_cp4_b ); +u_nrm_sh5x_39: ex4_sh5_x_b(39) <= not( ex4_sh4(39) and ex4_shift_extra_cp4_b ); +u_nrm_sh5x_40: ex4_sh5_x_b(40) <= not( ex4_sh4(40) and ex4_shift_extra_cp4_b ); +u_nrm_sh5x_41: ex4_sh5_x_b(41) <= not( ex4_sh4(41) and ex4_shift_extra_cp4_b ); +u_nrm_sh5x_42: ex4_sh5_x_b(42) <= not( ex4_sh4(42) and ex4_shift_extra_cp4_b ); +u_nrm_sh5x_43: ex4_sh5_x_b(43) <= not( ex4_sh4(43) and ex4_shift_extra_cp4_b ); +u_nrm_sh5x_44: ex4_sh5_x_b(44) <= not( ex4_sh4(44) and ex4_shift_extra_cp4_b ); +u_nrm_sh5x_45: ex4_sh5_x_b(45) <= not( ex4_sh4(45) and ex4_shift_extra_cp4_b ); +u_nrm_sh5x_46: ex4_sh5_x_b(46) <= not( ex4_sh4(46) and ex4_shift_extra_cp4_b ); +u_nrm_sh5x_47: ex4_sh5_x_b(47) <= not( ex4_sh4(47) and ex4_shift_extra_cp4_b ); +u_nrm_sh5x_48: ex4_sh5_x_b(48) <= not( ex4_sh4(48) and ex4_shift_extra_cp4_b ); +u_nrm_sh5x_49: ex4_sh5_x_b(49) <= not( ex4_sh4(49) and ex4_shift_extra_cp4_b ); +u_nrm_sh5x_50: ex4_sh5_x_b(50) <= not( ex4_sh4(50) and ex4_shift_extra_cp4_b ); +u_nrm_sh5x_51: ex4_sh5_x_b(51) <= not( ex4_sh4(51) and ex4_shift_extra_cp4_b ); +u_nrm_sh5x_52: ex4_sh5_x_b(52) <= not( ex4_sh4(52) and ex4_shift_extra_cp4_b ); +u_nrm_sh5x_53: ex4_sh5_x_b(53) <= not( ex4_sh4(53) and ex4_shift_extra_cp4_b ); + + +u_nrm_sh5y_00: ex4_sh5_y_b( 0) <= not( ex4_sh4( 1) and ex4_shift_extra_cp3 ); +u_nrm_sh5y_01: ex4_sh5_y_b( 1) <= not( ex4_sh4( 2) and ex4_shift_extra_cp3 ); +u_nrm_sh5y_02: ex4_sh5_y_b( 2) <= not( ex4_sh4( 3) and ex4_shift_extra_cp3 ); +u_nrm_sh5y_03: ex4_sh5_y_b( 3) <= not( ex4_sh4( 4) and ex4_shift_extra_cp3 ); +u_nrm_sh5y_04: ex4_sh5_y_b( 4) <= not( ex4_sh4( 5) and ex4_shift_extra_cp3 ); +u_nrm_sh5y_05: ex4_sh5_y_b( 5) <= not( ex4_sh4( 6) and ex4_shift_extra_cp3 ); +u_nrm_sh5y_06: ex4_sh5_y_b( 6) <= not( ex4_sh4( 7) and ex4_shift_extra_cp3 ); +u_nrm_sh5y_07: ex4_sh5_y_b( 7) <= not( ex4_sh4( 8) and ex4_shift_extra_cp3 ); +u_nrm_sh5y_08: ex4_sh5_y_b( 8) <= not( ex4_sh4( 9) and ex4_shift_extra_cp3 ); +u_nrm_sh5y_09: ex4_sh5_y_b( 9) <= not( ex4_sh4(10) and ex4_shift_extra_cp3 ); +u_nrm_sh5y_10: ex4_sh5_y_b(10) <= not( ex4_sh4(11) and ex4_shift_extra_cp3 ); +u_nrm_sh5y_11: ex4_sh5_y_b(11) <= not( ex4_sh4(12) and ex4_shift_extra_cp3 ); +u_nrm_sh5y_12: ex4_sh5_y_b(12) <= not( ex4_sh4(13) and ex4_shift_extra_cp3 ); +u_nrm_sh5y_13: ex4_sh5_y_b(13) <= not( ex4_sh4(14) and ex4_shift_extra_cp3 ); +u_nrm_sh5y_14: ex4_sh5_y_b(14) <= not( ex4_sh4(15) and ex4_shift_extra_cp3 ); +u_nrm_sh5y_15: ex4_sh5_y_b(15) <= not( ex4_sh4(16) and ex4_shift_extra_cp3 ); +u_nrm_sh5y_16: ex4_sh5_y_b(16) <= not( ex4_sh4(17) and ex4_shift_extra_cp3 ); +u_nrm_sh5y_17: ex4_sh5_y_b(17) <= not( ex4_sh4(18) and ex4_shift_extra_cp3 ); +u_nrm_sh5y_18: ex4_sh5_y_b(18) <= not( ex4_sh4(19) and ex4_shift_extra_cp3 ); +u_nrm_sh5y_19: ex4_sh5_y_b(19) <= not( ex4_sh4(20) and ex4_shift_extra_cp3 ); +u_nrm_sh5y_20: ex4_sh5_y_b(20) <= not( ex4_sh4(21) and ex4_shift_extra_cp3 ); +u_nrm_sh5y_21: ex4_sh5_y_b(21) <= not( ex4_sh4(22) and ex4_shift_extra_cp3 ); +u_nrm_sh5y_22: ex4_sh5_y_b(22) <= not( ex4_sh4(23) and ex4_shift_extra_cp3 ); +u_nrm_sh5y_23: ex4_sh5_y_b(23) <= not( ex4_sh4(24) and ex4_shift_extra_cp3 ); +u_nrm_sh5y_24: ex4_sh5_y_b(24) <= not( ex4_sh4(25) and ex4_shift_extra_cp3 ); +u_nrm_sh5y_25: ex4_sh5_y_b(25) <= not( ex4_sh4(26) and ex4_shift_extra_cp3 ); +u_nrm_sh5y_26: ex4_sh5_y_b(26) <= not( ex4_sh4(27) and ex4_shift_extra_cp4 ); +u_nrm_sh5y_27: ex4_sh5_y_b(27) <= not( ex4_sh4(28) and ex4_shift_extra_cp4 ); +u_nrm_sh5y_28: ex4_sh5_y_b(28) <= not( ex4_sh4(29) and ex4_shift_extra_cp4 ); +u_nrm_sh5y_29: ex4_sh5_y_b(29) <= not( ex4_sh4(30) and ex4_shift_extra_cp4 ); +u_nrm_sh5y_30: ex4_sh5_y_b(30) <= not( ex4_sh4(31) and ex4_shift_extra_cp4 ); +u_nrm_sh5y_31: ex4_sh5_y_b(31) <= not( ex4_sh4(32) and ex4_shift_extra_cp4 ); +u_nrm_sh5y_32: ex4_sh5_y_b(32) <= not( ex4_sh4(33) and ex4_shift_extra_cp4 ); +u_nrm_sh5y_33: ex4_sh5_y_b(33) <= not( ex4_sh4(34) and ex4_shift_extra_cp4 ); +u_nrm_sh5y_34: ex4_sh5_y_b(34) <= not( ex4_sh4(35) and ex4_shift_extra_cp4 ); +u_nrm_sh5y_35: ex4_sh5_y_b(35) <= not( ex4_sh4(36) and ex4_shift_extra_cp4 ); +u_nrm_sh5y_36: ex4_sh5_y_b(36) <= not( ex4_sh4(37) and ex4_shift_extra_cp4 ); +u_nrm_sh5y_37: ex4_sh5_y_b(37) <= not( ex4_sh4(38) and ex4_shift_extra_cp4 ); +u_nrm_sh5y_38: ex4_sh5_y_b(38) <= not( ex4_sh4(39) and ex4_shift_extra_cp4 ); +u_nrm_sh5y_39: ex4_sh5_y_b(39) <= not( ex4_sh4(40) and ex4_shift_extra_cp4 ); +u_nrm_sh5y_40: ex4_sh5_y_b(40) <= not( ex4_sh4(41) and ex4_shift_extra_cp4 ); +u_nrm_sh5y_41: ex4_sh5_y_b(41) <= not( ex4_sh4(42) and ex4_shift_extra_cp4 ); +u_nrm_sh5y_42: ex4_sh5_y_b(42) <= not( ex4_sh4(43) and ex4_shift_extra_cp4 ); +u_nrm_sh5y_43: ex4_sh5_y_b(43) <= not( ex4_sh4(44) and ex4_shift_extra_cp4 ); +u_nrm_sh5y_44: ex4_sh5_y_b(44) <= not( ex4_sh4(45) and ex4_shift_extra_cp4 ); +u_nrm_sh5y_45: ex4_sh5_y_b(45) <= not( ex4_sh4(46) and ex4_shift_extra_cp4 ); +u_nrm_sh5y_46: ex4_sh5_y_b(46) <= not( ex4_sh4(47) and ex4_shift_extra_cp4 ); +u_nrm_sh5y_47: ex4_sh5_y_b(47) <= not( ex4_sh4(48) and ex4_shift_extra_cp4 ); +u_nrm_sh5y_48: ex4_sh5_y_b(48) <= not( ex4_sh4(49) and ex4_shift_extra_cp4 ); +u_nrm_sh5y_49: ex4_sh5_y_b(49) <= not( ex4_sh4(50) and ex4_shift_extra_cp4 ); +u_nrm_sh5y_50: ex4_sh5_y_b(50) <= not( ex4_sh4(51) and ex4_shift_extra_cp4 ); +u_nrm_sh5y_51: ex4_sh5_y_b(51) <= not( ex4_sh4(52) and ex4_shift_extra_cp4 ); +u_nrm_sh5y_52: ex4_sh5_y_b(52) <= not( ex4_sh4(53) and ex4_shift_extra_cp4 ); +u_nrm_sh5y_53: ex4_sh5_y_b(53) <= not( ex4_sh4(54) and ex4_shift_extra_cp4 ); + + + +end; -- fuq_nrm_sh ARCHITECTURE diff --git a/rel/src/vhdl/work/fuq_perv.vhdl b/rel/src/vhdl/work/fuq_perv.vhdl new file mode 100644 index 0000000..678fb70 --- /dev/null +++ b/rel/src/vhdl/work/fuq_perv.vhdl @@ -0,0 +1,298 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + + +library ieee; +use ieee.std_logic_1164.all; + +library ibm; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; + +library support; +use support.power_logic_pkg.all; + +library tri; +use tri.tri_latches_pkg.all; + +entity fuq_perv is +generic(expand_type : integer := 2 ); -- 0 = ibm umbra, 1 = xilinx, 2 = ibm mpg +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + pc_fu_sg_3 : in std_ulogic_vector(0 to 1); + pc_fu_abst_sl_thold_3 : in std_ulogic; + pc_fu_func_sl_thold_3 : in std_ulogic_vector(0 to 1); + pc_fu_func_slp_sl_thold_3 : in std_ulogic_vector(0 to 1); + pc_fu_gptr_sl_thold_3 : in std_ulogic; + pc_fu_time_sl_thold_3 : in std_ulogic; + pc_fu_ary_nsl_thold_3 : in std_ulogic; + pc_fu_cfg_sl_thold_3 : in std_ulogic; + pc_fu_repr_sl_thold_3 : in std_ulogic; + pc_fu_fce_3 : in std_ulogic; + tc_ac_ccflush_dc : in std_ulogic; + tc_ac_scan_diag_dc : in std_ulogic; + abst_sl_thold_1 : out std_ulogic; + func_sl_thold_1 : out std_ulogic_vector(0 to 1); + time_sl_thold_1 : out std_ulogic; + ary_nsl_thold_1 : out std_ulogic; + gptr_sl_thold_0 : out std_ulogic; + cfg_sl_thold_1 : out std_ulogic; + func_slp_sl_thold_1 : out std_ulogic; + + fce_1 : out std_ulogic; + sg_1 : out std_ulogic_vector(0 to 1); + clkoff_dc_b : out std_ulogic; + act_dis : out std_ulogic; + delay_lclkr_dc : out std_ulogic_vector(0 to 9); + mpw1_dc_b : out std_ulogic_vector(0 to 9); + mpw2_dc_b : out std_ulogic_vector(0 to 1); + repr_scan_in : in std_ulogic; --tc_ac_repr_scan_in(2) + repr_scan_out : out std_ulogic; --tc_ac_repr_scan_in(2) + gptr_scan_in : in std_ulogic; + gptr_scan_out : out std_ulogic +); + +-- synopsys translate_off + + +-- synopsys translate_on + +end fuq_perv; +architecture fuq_perv of fuq_perv is + + +signal abst_sl_thold_2 : std_ulogic; +signal time_sl_thold_2 : std_ulogic; +signal func_sl_thold_2 : std_ulogic_vector(0 to 1); +signal gptr_sl_thold_2 : std_ulogic; +signal ary_nsl_thold_2 : std_ulogic; +signal cfg_sl_thold_2 : std_ulogic; +signal repr_sl_thold_2 : std_ulogic; +signal func_slp_sl_thold_2 : std_ulogic; + +signal sg_2 : std_ulogic_vector(0 to 1); +signal fce_2 : std_ulogic; + +signal gptr_sl_thold_1 : std_ulogic; +signal repr_sl_thold_1 : std_ulogic; +signal sg_1_int : std_ulogic_vector(0 to 1); + +signal gptr_sl_thold_0_int : std_ulogic; +signal repr_sl_thold_0 : std_ulogic; +signal repr_sl_force : std_ulogic; +signal repr_sl_thold_0_b : std_ulogic; +signal repr_in : std_ulogic; +signal repr_UNUSED : std_ulogic; + +signal spare_unused : std_ulogic; + +signal sg_0 : std_ulogic; +signal gptr_sio : std_ulogic; +signal prv_delay_lclkr_dc : std_ulogic_vector(0 to 9); +signal prv_mpw1_dc_b : std_ulogic_vector(0 to 9); +signal prv_mpw2_dc_b : std_ulogic_vector(0 to 1); +signal prv_act_dis : std_ulogic; +signal prv_clkoff_dc_b : std_ulogic; +signal tihi : std_ulogic; + +begin + +tihi <= '1'; + +perv_3to2_reg: tri_plat + generic map (width => 12, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + + din(0 to 1) => pc_fu_func_sl_thold_3(0 to 1), + din(2) => pc_fu_gptr_sl_thold_3, + din(3) => pc_fu_abst_sl_thold_3, + din(4 to 5) => pc_fu_sg_3(0 to 1), + din(6) => pc_fu_time_sl_thold_3, + din(7) => pc_fu_fce_3, + din(8) => pc_fu_ary_nsl_thold_3, + din(9) => pc_fu_cfg_sl_thold_3, + din(10) => pc_fu_repr_sl_thold_3, + din(11) => pc_fu_func_slp_sl_thold_3(0), + + q(0 to 1) => func_sl_thold_2(0 to 1), + q(2) => gptr_sl_thold_2, + q(3) => abst_sl_thold_2, + q(4 to 5) => sg_2(0 to 1), + q(6) => time_sl_thold_2, + q(7) => fce_2, + q(8) => ary_nsl_thold_2, + q(9) => cfg_sl_thold_2, + q(10) => repr_sl_thold_2, + q(11) => func_slp_sl_thold_2 ); + + +perv_2to1_reg: tri_plat + generic map (width => 12, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + + din(0 to 1) => func_sl_thold_2(0 to 1), + din(2) => gptr_sl_thold_2, + din(3) => abst_sl_thold_2, + din(4 to 5) => sg_2(0 to 1), + din(6) => time_sl_thold_2, + din(7) => fce_2, + din(8) => ary_nsl_thold_2, + din(9) => cfg_sl_thold_2, + din(10) => repr_sl_thold_2, + din(11) => func_slp_sl_thold_2, + + q(0 to 1) => func_sl_thold_1(0 to 1), + q(2) => gptr_sl_thold_1, + q(3) => abst_sl_thold_1, + q(4 to 5) => sg_1_int(0 to 1), + q(6) => time_sl_thold_1, + q(7) => fce_1, + q(8) => ary_nsl_thold_1, + q(9) => cfg_sl_thold_1, + q(10) => repr_sl_thold_1, + q(11) => func_slp_sl_thold_1 ); + +sg_1(0 to 1) <= sg_1_int(0 to 1); + +perv_1to0_reg: tri_plat + generic map (width => 3, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => gptr_sl_thold_1, + din(1) => sg_1_int(0), + din(2) => repr_sl_thold_1, + + q(0) => gptr_sl_thold_0_int, + q(1) => sg_0, + q(2) => repr_sl_thold_0 ); + + gptr_sl_thold_0 <= gptr_sl_thold_0_int; + +-- Pipeline mapping of mpw1_b and delay_lclkr, mpw2_b +-- RF0 8 1 +-- RF1 0 0 +-- EX1 1 0 +-- EX2 2 0 +-- EX3 3 0 +-- EX4 4 0 +-- EX5 5 1 +-- EX6 6 1 +-- EX7 7 1 +-- Ctrl 9 1 +perv_lcbctrl0: tri_lcbcntl_mac + generic map (expand_type => expand_type) + port map ( + vdd => vdd, + gnd => gnd, + sg => sg_0, + nclk => nclk, + scan_in => gptr_scan_in, + scan_diag_dc => tc_ac_scan_diag_dc, + thold => gptr_sl_thold_0_int, + clkoff_dc_b => prv_clkoff_dc_b, + delay_lclkr_dc => prv_delay_lclkr_dc(0 to 4), + act_dis_dc => open, + mpw1_dc_b => prv_mpw1_dc_b(0 to 4), + mpw2_dc_b => prv_mpw2_dc_b(0), + scan_out => gptr_sio); + +perv_lcbctrl1: tri_lcbcntl_mac + generic map (expand_type => expand_type) + port map ( + vdd => vdd, + gnd => gnd, + sg => sg_0, + nclk => nclk, + scan_in => gptr_sio, + scan_diag_dc => tc_ac_scan_diag_dc, + thold => gptr_sl_thold_0_int, + clkoff_dc_b => open, + delay_lclkr_dc => prv_delay_lclkr_dc(5 to 9), + act_dis_dc => open, + mpw1_dc_b => prv_mpw1_dc_b(5 to 9), + mpw2_dc_b => prv_mpw2_dc_b(1), + scan_out => gptr_scan_out); + +--Outputs + delay_lclkr_dc(0 to 9) <= prv_delay_lclkr_dc(0 to 9); + mpw1_dc_b(0 to 9) <= prv_mpw1_dc_b(0 to 9); + mpw2_dc_b(0 to 1) <= prv_mpw2_dc_b(0 to 1); + +--never disable act pins, they are used functionally + prv_act_dis <= '0'; + act_dis <= prv_act_dis; + clkoff_dc_b <= prv_clkoff_dc_b; + +-- Repower latch for repr scan ins/outs + repr_sl_lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map ( + clkoff_b => prv_clkoff_dc_b, + thold => repr_sl_thold_0, + sg => sg_0, + act_dis => prv_act_dis, + forcee => repr_sl_force, + thold_b => repr_sl_thold_0_b ); + + repr_in <= '0'; + repr_rpwr_lat: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 1) + port map (nclk => nclk, + act => tihi, + forcee => repr_sl_force, + delay_lclkr => prv_delay_lclkr_dc(9), + mpw1_b => prv_mpw1_dc_b(9), + mpw2_b => prv_mpw2_dc_b(1), + thold_b => repr_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin(0) => repr_scan_in, + scout(0) => repr_scan_out, + --------------------------------------------- + din(0) => repr_in, + --------------------------------------------- + dout(0) => repr_UNUSED + --------------------------------------------- + ); + +-- Unused logic + spare_unused <= pc_fu_func_slp_sl_thold_3(1); + +end fuq_perv; diff --git a/rel/src/vhdl/work/fuq_pic.vhdl b/rel/src/vhdl/work/fuq_pic.vhdl new file mode 100644 index 0000000..d77c285 --- /dev/null +++ b/rel/src/vhdl/work/fuq_pic.vhdl @@ -0,0 +1,2960 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + + +entity fuq_pic is +generic( expand_type : integer := 2 ); -- 0 - ibm tech, 1 - other ); +port( + vdd :inout power_logic; + gnd :inout power_logic; + clkoff_b :in std_ulogic; -- tiup + act_dis :in std_ulogic; -- ??tidn?? + flush :in std_ulogic; -- ??tidn?? + delay_lclkr :in std_ulogic_vector(1 to 5); -- tidn, + mpw1_b :in std_ulogic_vector(1 to 5); -- tidn, + mpw2_b :in std_ulogic_vector(0 to 1); -- tidn, + sg_1 :in std_ulogic; + thold_1 :in std_ulogic; + fpu_enable :in std_ulogic; --dc_act + nclk :in clk_logic; + + f_pic_si :in std_ulogic; --perv + f_pic_so :out std_ulogic; --perv + f_dcd_rf1_act :in std_ulogic; --act + f_dcd_rf1_aop_valid :in std_ulogic; + f_dcd_rf1_cop_valid :in std_ulogic; + f_dcd_rf1_bop_valid :in std_ulogic; + + f_dcd_rf1_fsel_b :in std_ulogic; -- fsel + f_dcd_rf1_from_integer_b :in std_ulogic; -- fcfid (signed integer) + f_dcd_rf1_to_integer_b :in std_ulogic; -- fcti* (signed integer 32/64) + f_dcd_rf1_rnd_to_int_b :in std_ulogic; -- fcti* (signed integer 32/64) + f_dcd_rf1_math_b :in std_ulogic; -- fmul,fmad,fmsub,fadd,fsub,fnmsub,fnmadd + f_dcd_rf1_est_recip_b :in std_ulogic; -- fres + f_dcd_rf1_est_rsqrt_b :in std_ulogic; -- frsqrte + f_dcd_rf1_move_b :in std_ulogic; -- fmr,fneg,fabs,fnabs + f_dcd_rf1_compare_b :in std_ulogic; -- fcomp* + f_dcd_rf1_prenorm_b :in std_ulogic; -- prenorm ?? need + f_dcd_rf1_frsp_b :in std_ulogic; -- round-to-single-precision ?? need + f_dcd_rf1_mv_to_scr_b :in std_ulogic; --mcrfs,mtfsf,mtfsfi,mtfsb0,mtfsb1 + f_dcd_rf1_mv_from_scr_b :in std_ulogic; --mffs + f_dcd_rf1_div_beg :in std_ulogic; + f_dcd_rf1_sqrt_beg :in std_ulogic; + f_dcd_rf1_force_excp_dis :in std_ulogic; -- ve=ue=xe=ze=oe= 0 + f_dcd_rf1_ftdiv :in std_ulogic; + f_dcd_rf1_ftsqrt :in std_ulogic; + f_fmt_ex2_ae_ge_54 :in std_ulogic; + f_fmt_ex2_be_ge_54 :in std_ulogic; + f_fmt_ex2_be_ge_2 :in std_ulogic; + f_fmt_ex2_be_ge_2044 :in std_ulogic; + f_fmt_ex2_tdiv_rng_chk :in std_ulogic; + f_fmt_ex2_be_den :in std_ulogic; + f_dcd_rf1_sp :in std_ulogic; -- single precision output + f_dcd_rf1_uns_b :in std_ulogic; -- convert unsigned + f_dcd_rf1_word_b :in std_ulogic; -- convert word/dw + f_dcd_rf1_sp_conv_b :in std_ulogic; -- convert sp/d + f_dcd_rf1_pow2e_b :in std_ulogic; + f_dcd_rf1_log2e_b :in std_ulogic; + f_dcd_rf1_ordered_b :in std_ulogic; -- fcompo + f_dcd_rf1_sub_op_b :in std_ulogic; -- fsub, fnmsub, fmsub (fcomp) + f_dcd_rf1_op_rnd_v_b :in std_ulogic; -- fctidz, fctiwz, prenorm, fri* + f_dcd_rf1_op_rnd_b :in std_ulogic_vector(0 to 1); -- + f_dcd_rf1_inv_sign_b :in std_ulogic; -- fnmsub fnmadd + f_dcd_rf1_sign_ctl_b :in std_ulogic_vector(0 to 1); -- 0:fmr/fneg 1:fneg/fnabs + f_dcd_rf1_sgncpy_b :in std_ulogic; + + f_byp_pic_ex1_a_sign :in std_ulogic; + f_byp_pic_ex1_c_sign :in std_ulogic; + f_byp_pic_ex1_b_sign :in std_ulogic; + + + f_dcd_rf1_nj_deno :in std_ulogic; -- force output den to zero + f_dcd_rf1_nj_deni :in std_ulogic; -- force output den to zero + + f_cr2_ex1_fpscr_shadow :in std_ulogic_vector(0 to 7); + + f_fmt_ex1_sp_invalid :in std_ulogic; + f_fmt_ex1_a_zero :in std_ulogic; + f_fmt_ex1_a_expo_max :in std_ulogic; + f_fmt_ex1_a_frac_zero :in std_ulogic; + f_fmt_ex1_a_frac_msb :in std_ulogic; + f_fmt_ex1_c_zero :in std_ulogic; + f_fmt_ex1_c_expo_max :in std_ulogic; + f_fmt_ex1_c_frac_zero :in std_ulogic; + f_fmt_ex1_c_frac_msb :in std_ulogic; + f_fmt_ex1_b_zero :in std_ulogic; + f_fmt_ex1_b_expo_max :in std_ulogic; + f_fmt_ex1_b_frac_zero :in std_ulogic; + f_fmt_ex1_b_frac_msb :in std_ulogic; + f_fmt_ex1_prod_zero :in std_ulogic; + f_fmt_ex1_bexpu_le126 :in std_ulogic; -- log2e/pow2e special cases + f_fmt_ex1_gt126 :in std_ulogic; -- log2e/pow2e special cases + f_fmt_ex1_ge128 :in std_ulogic; -- log2e/pow2e special cases + f_fmt_ex1_inf_and_beyond_sp :in std_ulogic; + f_alg_ex1_sign_frmw :in std_ulogic; --?? from_int word is always unsigned (do not need this signal) + + f_fmt_ex2_pass_sign :in std_ulogic; + f_fmt_ex2_pass_msb :in std_ulogic; + f_fmt_ex1_b_imp :in std_ulogic; + f_fmt_ex1_b_frac_z32 :in std_ulogic; + + f_eie_ex2_wd_ov :in std_ulogic; + f_eie_ex2_dw_ov :in std_ulogic; + f_eie_ex2_wd_ov_if :in std_ulogic; + f_eie_ex2_dw_ov_if :in std_ulogic; + f_eie_ex2_lt_bias :in std_ulogic; + f_eie_ex2_eq_bias_m1 :in std_ulogic; + + f_alg_ex2_sel_byp :in std_ulogic; + f_alg_ex2_effsub_eac_b :in std_ulogic; + f_alg_ex2_sh_unf :in std_ulogic; + f_alg_ex2_sh_ovf :in std_ulogic; + + f_mad_ex2_uc_a_expo_den :in std_ulogic; + f_mad_ex2_uc_a_expo_den_sp :in std_ulogic; + + f_alg_ex3_int_fr :in std_ulogic; + f_alg_ex3_int_fi :in std_ulogic; + + f_eov_ex4_may_ovf :in std_ulogic; + f_add_ex4_fpcc_iu :in std_ulogic_vector(0 to 3); + f_add_ex4_sign_carry :in std_ulogic; + f_add_ex4_to_int_ovf_wd :in std_ulogic_vector(0 to 1); + f_add_ex4_to_int_ovf_dw :in std_ulogic_vector(0 to 1); + + + f_pic_fmt_ex1_act :out std_ulogic; + f_pic_eie_ex1_act :out std_ulogic; + f_pic_mul_ex1_act :out std_ulogic; + f_pic_alg_ex1_act :out std_ulogic; + f_pic_cr2_ex1_act :out std_ulogic; + f_pic_tbl_ex1_act :out std_ulogic; + f_pic_add_ex1_act_b :out std_ulogic;--set + f_pic_lza_ex1_act_b :out std_ulogic;--set + f_pic_eov_ex2_act_b :out std_ulogic;--set + f_pic_nrm_ex3_act_b :out std_ulogic;--set + f_pic_rnd_ex3_act_b :out std_ulogic;--set + f_pic_scr_ex2_act_b :out std_ulogic;--set + + + + f_pic_ex1_rnd_to_int :out std_ulogic; + f_pic_ex1_fsel :out std_ulogic; + f_pic_ex1_frsp_ue1 :out std_ulogic; + f_pic_ex2_frsp_ue1 :out std_ulogic; + f_pic_ex2_ue1 :out std_ulogic; + f_pic_ex1_effsub_raw :out std_ulogic; + f_pic_ex1_from_integer :out std_ulogic; + f_pic_ex1_sh_ovf_do :out std_ulogic; + f_pic_ex1_sh_ovf_ig_b :out std_ulogic; + f_pic_ex1_sh_unf_do :out std_ulogic; + f_pic_ex1_sh_unf_ig_b :out std_ulogic; + + f_pic_ex1_log2e :out std_ulogic; + f_pic_ex1_pow2e :out std_ulogic; + + f_pic_ex1_ftdiv :out std_ulogic; + f_pic_ex1_flush_en_sp :out std_ulogic; + f_pic_ex1_flush_en_dp :out std_ulogic; + + f_pic_ex2_est_recip :out std_ulogic; + f_pic_ex2_est_rsqrt :out std_ulogic; + + f_pic_ex2_force_sel_bexp :out std_ulogic; + f_pic_ex2_lzo_dis_prod :out std_ulogic; + f_pic_ex2_sp_b :out std_ulogic; + f_pic_ex2_sp_lzo :out std_ulogic; + f_pic_ex2_to_integer :out std_ulogic; + f_pic_ex2_prenorm :out std_ulogic; + f_pic_ex2_math_bzer_b :out std_ulogic; + f_pic_ex2_b_valid :out std_ulogic; + f_pic_ex2_rnd_nr :out std_ulogic; + f_pic_ex2_rnd_inf_ok :out std_ulogic; + + f_pic_ex3_cmp_sgnneg :out std_ulogic; + f_pic_ex3_cmp_sgnpos :out std_ulogic; + f_pic_ex3_is_eq :out std_ulogic; + f_pic_ex3_is_gt :out std_ulogic; + f_pic_ex3_is_lt :out std_ulogic; + f_pic_ex3_is_nan :out std_ulogic; + f_pic_ex3_sp_b :out std_ulogic; + f_pic_ex3_sel_est :out std_ulogic; + + + f_dcd_rf1_uc_ft_pos :in std_ulogic; -- force div/sqrt result poitive + f_dcd_rf1_uc_ft_neg :in std_ulogic; -- force div/sqrt result poitive + f_dcd_rf1_uc_mid :in std_ulogic; + f_dcd_rf1_uc_end :in std_ulogic; + f_dcd_rf1_uc_special :in std_ulogic; + f_dcd_ex2_uc_zx :in std_ulogic; + f_dcd_ex2_uc_vxidi :in std_ulogic; + f_dcd_ex2_uc_vxzdz :in std_ulogic; + f_dcd_ex2_uc_vxsqrt :in std_ulogic; + f_dcd_ex2_uc_vxsnan :in std_ulogic; + + f_mad_ex3_uc_special :out std_ulogic; + f_mad_ex3_uc_zx :out std_ulogic; + f_mad_ex3_uc_vxidi :out std_ulogic; + f_mad_ex3_uc_vxzdz :out std_ulogic; + f_mad_ex3_uc_vxsqrt :out std_ulogic; + f_mad_ex3_uc_vxsnan :out std_ulogic; + f_mad_ex3_uc_res_sign :out std_ulogic; + f_mad_ex3_uc_round_mode :out std_ulogic_vector(0 to 1); + + + + + + f_pic_ex4_byp_prod_nz :out std_ulogic; + f_pic_ex4_sel_est_b :out std_ulogic; + f_pic_ex1_nj_deni :out std_ulogic; + f_pic_ex4_nj_deno :out std_ulogic; + f_pic_ex4_oe :out std_ulogic; + f_pic_ex4_ov_en :out std_ulogic; + f_pic_ex4_ovf_en_oe0_b :out std_ulogic; + f_pic_ex4_ovf_en_oe1_b :out std_ulogic; + f_pic_ex4_quiet_b :out std_ulogic; + + f_dcd_ex2_uc_inc_lsb :in std_ulogic; + f_dcd_ex2_uc_guard :in std_ulogic; + f_dcd_ex2_uc_sticky :in std_ulogic; + f_dcd_ex2_uc_gs_v :in std_ulogic; + + f_pic_ex5_uc_inc_lsb :out std_ulogic; + f_pic_ex5_uc_guard :out std_ulogic; + f_pic_ex5_uc_sticky :out std_ulogic; + f_pic_ex5_uc_g_v :out std_ulogic; + f_pic_ex5_uc_s_v :out std_ulogic; + + f_pic_ex4_rnd_inf_ok_b :out std_ulogic; + f_pic_ex4_rnd_ni_b :out std_ulogic; + f_pic_ex4_rnd_nr_b :out std_ulogic; + f_pic_ex4_sel_fpscr_b :out std_ulogic; + f_pic_ex4_sp_b :out std_ulogic; + f_pic_ex4_spec_inf_b :out std_ulogic; + f_pic_ex4_spec_sel_k_e :out std_ulogic; + f_pic_ex4_spec_sel_k_f :out std_ulogic; + + f_pic_ex4_to_int_ov_all :out std_ulogic; + + f_pic_ex4_to_integer_b :out std_ulogic; + f_pic_ex4_word_b :out std_ulogic; + f_pic_ex4_uns_b :out std_ulogic; + f_pic_ex4_ue :out std_ulogic; + f_pic_ex4_uf_en :out std_ulogic; + f_pic_ex4_unf_en_ue0_b :out std_ulogic; + f_pic_ex4_unf_en_ue1_b :out std_ulogic; + + f_pic_ex5_en_exact_zero :out std_ulogic; + f_pic_ex5_frsp :out std_ulogic; + f_pic_ex5_compare_b :out std_ulogic; + f_pic_ex5_fi_pipe_v_b :out std_ulogic; + f_pic_ex5_fi_spec_b :out std_ulogic; + f_pic_ex5_flag_vxcvi_b :out std_ulogic; + f_pic_ex5_flag_vxidi_b :out std_ulogic; + f_pic_ex5_flag_vximz_b :out std_ulogic; + f_pic_ex5_flag_vxisi_b :out std_ulogic; + f_pic_ex5_flag_vxsnan_b :out std_ulogic; + f_pic_ex5_flag_vxsqrt_b :out std_ulogic; + f_pic_ex5_flag_vxvc_b :out std_ulogic; + f_pic_ex5_flag_vxzdz_b :out std_ulogic; + f_pic_ex5_flag_zx_b :out std_ulogic; + f_pic_ex5_fprf_hold_b :out std_ulogic; + f_pic_ex5_fprf_pipe_v_b :out std_ulogic; + f_pic_ex5_fprf_spec_b :out std_ulogic_vector(0 to 4); + f_pic_ex5_fr_pipe_v_b :out std_ulogic; + f_pic_ex5_fr_spec_b :out std_ulogic; + f_pic_ex5_invert_sign :out std_ulogic; + + f_pic_ex5_k_nan :out std_ulogic; + f_pic_ex5_k_inf :out std_ulogic; + f_pic_ex5_k_max :out std_ulogic; + f_pic_ex5_k_zer :out std_ulogic; + f_pic_ex5_k_one :out std_ulogic; + f_pic_ex5_k_int_maxpos :out std_ulogic; + f_pic_ex5_k_int_maxneg :out std_ulogic; + f_pic_ex5_k_int_zer :out std_ulogic; + f_pic_ex5_ox_pipe_v_b :out std_ulogic; + f_pic_ex5_round_sign :out std_ulogic; + f_pic_ex5_ux_pipe_v_b :out std_ulogic; + f_pic_ex5_scr_upd_move_b :out std_ulogic; + f_pic_ex5_scr_upd_pipe_b :out std_ulogic; + f_pic_ex5_fpr_wr_dis_b :out std_ulogic + +); + + + +end fuq_pic; -- ENTITY + +architecture fuq_pic of fuq_pic is + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal thold_0_b , thold_0, forcee, sg_0 :std_ulogic; + signal rf1_act , ex1_act , ex2_act , ex3_act , ex4_act :std_ulogic; + signal ex1_act_add :std_ulogic; + signal ex1_act_lza :std_ulogic; + signal ex2_act_eov :std_ulogic; + signal ex2_act_scr :std_ulogic; + signal ex3_act_nrm :std_ulogic; + signal ex3_act_rnd :std_ulogic; + signal spare_unused :std_ulogic_vector(0 to 3); + signal act_so , act_si :std_ulogic_vector(0 to 20); + + signal ex1_ctl_so , ex1_ctl_si :std_ulogic_vector(0 to 42); + signal ex2_ctl_so , ex2_ctl_si :std_ulogic_vector(0 to 56); + signal ex3_ctl_so , ex3_ctl_si :std_ulogic_vector(0 to 33); + signal ex4_ctl_so , ex4_ctl_si :std_ulogic_vector(0 to 28); + signal ex2_flg_so , ex2_flg_si :std_ulogic_vector(0 to 17); + signal ex3_scr_so , ex3_scr_si :std_ulogic_vector(0 to 7); + signal ex3_flg_so , ex3_flg_si :std_ulogic_vector(0 to 46); + signal ex4_scr_so , ex4_scr_si :std_ulogic_vector(0 to 7); + signal ex4_flg_so , ex4_flg_si :std_ulogic_vector(0 to 37); + signal ex5_flg_so , ex5_flg_si :std_ulogic_vector(0 to 41); + + signal ex4_may_ovf :std_ulogic; + signal ex5_unused :std_ulogic; + signal ex2_a_sign :std_ulogic; + signal ex3_pass_nan :std_ulogic; + signal ex2_pass_x :std_ulogic; + + signal ex1_rnd_fpscr, ex2_rnd_fpscr, ex3_rnd_fpscr :std_ulogic_vector(0 to 1); + signal ex1_div_sign, ex2_div_sign, ex3_div_sign :std_ulogic ; + + signal ex3_ve :std_ulogic ; + signal ex3_oe :std_ulogic ; + signal ex3_ue :std_ulogic ; + signal ex3_ze :std_ulogic ; + signal ex3_xe :std_ulogic ; + signal ex3_nonieee :std_ulogic ; + signal ex3_rnd0 :std_ulogic ; + signal ex3_rnd1 :std_ulogic ; + signal ex4_ve :std_ulogic ; + signal ex4_oe :std_ulogic ; + signal ex4_ue :std_ulogic ; + signal ex4_ze :std_ulogic ; + signal ex4_xe :std_ulogic ; + signal ex4_nonieee :std_ulogic ; + signal ex4_rnd0 :std_ulogic ; + signal ex4_rnd1 :std_ulogic ; + signal ex2_toint_nan_sign :std_ulogic ; + + signal ex1_uc_ft_neg, ex2_uc_ft_neg, ex3_uc_ft_neg :std_ulogic; + signal ex1_uc_ft_pos, ex2_uc_ft_pos, ex3_uc_ft_pos :std_ulogic; + signal ex1_a_inf :std_ulogic; + signal ex1_a_nan :std_ulogic; + signal ex1_a_sign :std_ulogic; + signal ex1_b_inf :std_ulogic; + signal ex1_b_nan :std_ulogic; + signal ex1_b_sign :std_ulogic; + signal ex1_b_sign_adj :std_ulogic; + signal ex1_b_sign_adj_x :std_ulogic; + signal ex1_b_sign_alt :std_ulogic; + signal ex1_a_valid :std_ulogic; + signal ex1_c_valid :std_ulogic; + signal ex1_b_valid :std_ulogic; + signal ex1_c_inf :std_ulogic; + signal ex1_sp_invalid :std_ulogic; + signal ex2_sp_invalid :std_ulogic; + signal ex1_c_nan :std_ulogic; + signal ex1_c_sign :std_ulogic; + signal ex1_compare :std_ulogic; + signal ex1_div_beg :std_ulogic; + signal ex1_est_recip :std_ulogic; + signal ex1_est_rsqrt :std_ulogic; + signal ex1_op_rnd_v :std_ulogic; + signal ex1_op_rnd :std_ulogic_vector(0 to 1); + signal ex1_from_integer :std_ulogic; + signal ex1_frsp :std_ulogic; + signal ex1_fsel :std_ulogic; + signal ex1_inv_sign :std_ulogic; + signal ex1_lzo_dis :std_ulogic; + signal ex1_uc_mid, ex2_uc_mid, ex3_uc_mid, ex4_uc_mid :std_ulogic; + signal ex1_math :std_ulogic; + signal ex1_move :std_ulogic; + signal ex1_mv_from_scr :std_ulogic; + signal ex1_mv_to_scr :std_ulogic; + signal ex1_p_sign :std_ulogic; + signal ex1_prenorm :std_ulogic; + signal ex1_sign_ctl :std_ulogic_vector(0 to 1); + signal ex1_sp :std_ulogic; + signal ex1_sp_b :std_ulogic; + signal ex1_sqrt_beg :std_ulogic; + signal ex1_sub_op :std_ulogic; + signal ex1_to_integer :std_ulogic; + signal ex1_ordered :std_ulogic; + signal ex1_word :std_ulogic; + signal rf1_uns :std_ulogic; + signal rf1_sp_conv :std_ulogic; + signal ex1_uns :std_ulogic; + signal ex2_uns :std_ulogic; + signal ex3_uns :std_ulogic; + signal ex4_uns :std_ulogic; + signal ex1_sp_conv :std_ulogic; + signal ex2_a_frac_msb :std_ulogic; + signal ex2_a_inf :std_ulogic; + signal ex2_a_nan :std_ulogic; + signal ex2_a_zero :std_ulogic; + signal ex2_any_inf :std_ulogic; + signal ex2_b_frac_msb :std_ulogic; + signal ex2_b_inf :std_ulogic; + signal ex2_b_nan :std_ulogic; + signal ex2_b_sign_adj :std_ulogic; + signal ex2_to_int_uns_neg :std_ulogic; + signal ex3_to_int_uns_neg :std_ulogic; + signal ex4_to_int_uns_neg :std_ulogic; + signal ex2_wd_ov_x :std_ulogic; + signal ex2_dw_ov_x :std_ulogic; + signal ex2_b_sign_alt :std_ulogic; + signal ex2_b_zero :std_ulogic; + signal ex3_b_zero :std_ulogic; + signal ex2_c_frac_msb :std_ulogic; + signal ex2_c_inf :std_ulogic; + signal ex2_c_nan :std_ulogic; + signal ex2_c_zero :std_ulogic; + signal ex2_cmp_sgnneg :std_ulogic; + signal ex2_cmp_sgnpos :std_ulogic; + signal ex2_cmp_zero :std_ulogic; + signal ex2_compare :std_ulogic; + signal ex2_div_beg :std_ulogic; + signal ex3_div_beg :std_ulogic; + signal ex4_div_beg :std_ulogic; + signal ex2_est_recip :std_ulogic; + signal ex2_est_rsqrt :std_ulogic; + signal ex2_rnd_dis :std_ulogic; + signal ex2_op_rnd :std_ulogic_vector(0 to 1); + signal ex2_from_integer :std_ulogic; + signal ex2_frsp :std_ulogic; + signal ex2_fsel :std_ulogic; + signal ex2_gen_inf :std_ulogic; + signal ex2_gen_max :std_ulogic; + signal ex2_gen_nan :std_ulogic; + signal ex2_gen_zero :std_ulogic; + signal ex2_inf_sign :std_ulogic; + signal ex2_inv_sign :std_ulogic; + signal ex2_is_eq :std_ulogic; + signal ex2_is_gt :std_ulogic; + signal ex2_is_lt :std_ulogic; + signal ex2_is_nan :std_ulogic; + signal ex2_lzo_dis :std_ulogic; + signal ex2_math :std_ulogic; + signal ex2_move :std_ulogic; + signal ex2_mv_from_scr :std_ulogic; + signal ex2_mv_to_scr :std_ulogic; + signal ex2_neg_sqrt_nz :std_ulogic; + signal ex2_p_inf :std_ulogic; + signal ex2_p_sign :std_ulogic; + signal ex2_p_zero :std_ulogic; + signal ex2_pass_en :std_ulogic; + signal ex2_pass_nan :std_ulogic; + signal ex2_prenorm :std_ulogic; + signal ex2_quiet :std_ulogic; + signal ex2_rnd0 :std_ulogic; + signal ex2_rnd1 :std_ulogic; + signal ex2_rnd_inf_ok :std_ulogic; + signal ex2_rnd_nr :std_ulogic; + signal ex2_sp :std_ulogic; + signal ex2_sp_notrunc :std_ulogic; + signal ex2_sp_o_frsp :std_ulogic; + signal ex2_spec_sign :std_ulogic; + signal ex2_sqrt_beg :std_ulogic; + signal ex3_sqrt_beg :std_ulogic; + signal ex4_sqrt_beg :std_ulogic; + signal ex2_sub_op :std_ulogic; + signal ex2_to_integer :std_ulogic; + signal ex2_ue :std_ulogic; + signal ex2_ordered :std_ulogic; + signal ex2_nonieee :std_ulogic; + signal ex2_ze :std_ulogic; + signal ex2_ve :std_ulogic; + signal ex2_oe :std_ulogic; + signal ex2_xe :std_ulogic; + signal ex2_vxcvi :std_ulogic; + signal ex2_vxidi :std_ulogic; + signal ex2_vximz :std_ulogic; + signal ex2_vxisi :std_ulogic; + signal ex2_vxsnan :std_ulogic; + signal ex2_vxsqrt :std_ulogic; + signal ex2_vxvc :std_ulogic; + signal ex2_vxzdz :std_ulogic; + signal ex2_word :std_ulogic; + signal ex2_zx :std_ulogic; + signal ex3_b_sign_adj :std_ulogic; + signal ex3_b_sign_alt :std_ulogic; + signal ex3_cmp_sgnneg :std_ulogic; + signal ex3_cmp_sgnpos :std_ulogic; + signal ex3_compare :std_ulogic; + signal ex3_dw_ov :std_ulogic; + signal ex3_dw_ov_if :std_ulogic; + signal ex3_effsub_eac :std_ulogic; + signal ex4_effsub_eac :std_ulogic; + signal ex3_est_recip :std_ulogic; + signal ex3_est_rsqrt :std_ulogic; + signal ex3_rnd_dis :std_ulogic; + signal ex3_from_integer :std_ulogic; + signal ex3_frsp :std_ulogic; + signal ex3_fsel :std_ulogic; + signal ex3_gen_inf :std_ulogic; + signal ex3_gen_inf_mutex :std_ulogic; + signal ex3_gen_max_mutex :std_ulogic; + signal ex3_gen_max :std_ulogic; + signal ex3_gen_nan :std_ulogic; + signal ex3_gen_nan_mutex :std_ulogic; + signal ex3_gen_zer_mutex :std_ulogic; + signal ex3_gen_zero :std_ulogic; + signal ex3_inv_sign :std_ulogic; + signal ex3_is_eq :std_ulogic; + signal ex3_is_gt :std_ulogic; + signal ex3_is_lt :std_ulogic; + signal ex3_is_nan :std_ulogic; + signal ex3_math :std_ulogic; + signal ex3_move :std_ulogic; + signal ex3_mv_from_scr :std_ulogic; + signal ex3_mv_to_scr :std_ulogic; + signal ex3_oe_x :std_ulogic; + signal ex3_ov_en :std_ulogic; + signal ex3_ovf_en_oe0 :std_ulogic; + signal ex3_ovf_en_oe1 :std_ulogic; + signal ex3_p_sign :std_ulogic; + signal ex3_p_sign_may :std_ulogic; + signal ex3_prenorm :std_ulogic; + signal ex3_quiet :std_ulogic; + signal ex3_sel_byp :std_ulogic; + signal ex3_sh_ovf :std_ulogic; + signal ex3_sh_unf :std_ulogic; + signal ex3_sign_nco :std_ulogic; + signal ex3_sign_pco :std_ulogic; + signal ex3_sp :std_ulogic; + signal ex3_sp_x :std_ulogic; + signal ex3_sp_conv :std_ulogic; + signal ex2_sp_conv :std_ulogic; + signal ex3_spec_sel_e :std_ulogic; + signal ex3_spec_sel_f :std_ulogic; + signal ex3_spec_sign :std_ulogic; + signal ex3_spec_sign_x :std_ulogic; + signal ex3_spec_sign_sel :std_ulogic; + signal ex3_sub_op :std_ulogic; + signal ex3_to_int_dw :std_ulogic; + signal ex3_to_int_ov :std_ulogic; + signal ex3_to_int_ov_if :std_ulogic; + signal ex3_to_int_wd :std_ulogic; + signal ex3_to_integer :std_ulogic; + signal ex3_ue_x :std_ulogic; + signal ex3_uf_en :std_ulogic; + signal ex3_unf_en_oe0 :std_ulogic; + signal ex3_unf_en_oe1 :std_ulogic; + signal ex3_vxcvi :std_ulogic; + signal ex3_vxidi :std_ulogic; + signal ex3_vximz :std_ulogic; + signal ex3_vxisi :std_ulogic; + signal ex3_vxsnan :std_ulogic; + signal ex3_vxsqrt :std_ulogic; + signal ex3_vxvc :std_ulogic; + signal ex3_vxzdz :std_ulogic; + signal ex3_wd_ov :std_ulogic; + signal ex3_wd_ov_if :std_ulogic; + signal ex3_word :std_ulogic; + signal ex3_word_to :std_ulogic; + signal ex3_zx :std_ulogic; + signal ex4_compare :std_ulogic; + signal ex5_compare :std_ulogic; + signal ex4_en_exact_zero :std_ulogic; + signal ex4_est_recip :std_ulogic; + signal ex4_est_rsqrt :std_ulogic; + signal ex4_rnd_dis :std_ulogic; + signal ex4_fpr_wr_dis :std_ulogic; + signal ex4_fprf_pipe_v :std_ulogic; + signal ex4_fprf_spec :std_ulogic_vector(0 to 4); + signal ex4_fprf_spec_x :std_ulogic_vector(0 to 4); + signal ex4_fr_pipe_v :std_ulogic; + signal ex4_from_integer :std_ulogic; + signal ex4_frsp :std_ulogic; + signal ex5_frsp :std_ulogic; + signal ex4_fsel :std_ulogic; + signal ex4_gen_inf :std_ulogic; + signal ex4_gen_inf_sign :std_ulogic; + signal ex4_gen_max :std_ulogic; + signal ex4_gen_nan :std_ulogic; + signal ex4_pass_nan :std_ulogic; + signal ex4_gen_zero :std_ulogic; + signal ex4_inv_sign :std_ulogic; + signal ex4_invert_sign :std_ulogic; + signal ex4_k_max_fp :std_ulogic; + signal ex4_math :std_ulogic; + signal ex4_move :std_ulogic; + signal ex4_mv_from_scr :std_ulogic; + signal ex4_mv_to_scr :std_ulogic; + signal ex4_ov_en :std_ulogic; + signal ex4_ovf_en_oe0 :std_ulogic; + signal ex4_ovf_en_oe1 :std_ulogic; + signal ex4_ox_pipe_v :std_ulogic; + signal ex4_prenorm :std_ulogic; + signal ex4_quiet :std_ulogic; + signal ex4_rnd_en :std_ulogic; + signal ex4_rnd_inf_ok :std_ulogic; + signal ex4_rnd_pi :std_ulogic; + signal ex4_rnd_ni :std_ulogic; + signal ex4_rnd_nr :std_ulogic; + signal ex4_rnd_zr :std_ulogic; + signal ex4_rnd_nr_ok :std_ulogic; + signal ex4_round_sign :std_ulogic; + signal ex4_round_sign_x :std_ulogic; + signal ex4_scr_upd_move :std_ulogic; + signal ex4_scr_upd_pipe :std_ulogic; + signal ex4_sel_spec_e :std_ulogic; + signal ex4_sel_spec_f :std_ulogic; + signal ex4_sel_spec_fr :std_ulogic; + signal ex4_sign_nco :std_ulogic; + signal ex4_sign_pco :std_ulogic; + signal ex4_sign_nco_x :std_ulogic; + signal ex4_sign_pco_x :std_ulogic; + signal ex4_sign_nco_xx :std_ulogic; + signal ex4_sign_pco_xx :std_ulogic; + signal ex4_sp :std_ulogic; + signal ex4_spec_sel_e :std_ulogic; + signal ex4_spec_sel_f :std_ulogic; + signal ex4_sub_op :std_ulogic; + signal ex4_to_int_dw :std_ulogic; + signal ex4_to_int_ov :std_ulogic; + signal ex4_to_int_ov_if :std_ulogic; + signal ex4_to_int_wd :std_ulogic; + signal ex4_to_integer :std_ulogic; + signal ex4_uf_en :std_ulogic; + signal ex4_unf_en_oe0 :std_ulogic; + signal ex4_unf_en_oe1 :std_ulogic; + signal ex4_upd_fpscr_ops :std_ulogic; + signal ex4_vx :std_ulogic; + signal ex4_vxidi :std_ulogic; + signal ex4_vximz :std_ulogic; + signal ex4_vxisi :std_ulogic; + signal ex4_vxsnan :std_ulogic; + signal ex4_vxsqrt :std_ulogic; + signal ex4_vxvc :std_ulogic; + signal ex4_vxcvi :std_ulogic; + signal ex4_vxcvi_ov :std_ulogic; + signal ex4_to_int_ov_all_x :std_ulogic; + signal ex4_to_int_ov_all :std_ulogic; + signal ex4_to_int_ov_all_gt :std_ulogic; + signal ex4_to_int_k_sign :std_ulogic; + signal ex4_vxzdz :std_ulogic; + signal ex4_word :std_ulogic; + signal ex4_zx :std_ulogic; + signal ex5_en_exact_zero :std_ulogic; + signal ex5_fpr_wr_dis :std_ulogic; + signal ex5_fprf_pipe_v :std_ulogic; + signal ex5_fprf_spec :std_ulogic_vector(0 to 4); + signal ex5_fr_pipe_v :std_ulogic; + signal ex5_invert_sign :std_ulogic; + signal ex5_ox_pipe_v :std_ulogic; + signal ex5_round_sign :std_ulogic; + signal ex5_scr_upd_move :std_ulogic; + signal ex5_scr_upd_pipe :std_ulogic; + signal ex5_vxcvi :std_ulogic; + signal ex5_vxidi :std_ulogic; + signal ex5_vximz :std_ulogic; + signal ex5_vxisi :std_ulogic; + signal ex5_vxsnan :std_ulogic; + signal ex5_vxsqrt :std_ulogic; + signal ex5_vxvc :std_ulogic; + signal ex5_vxzdz :std_ulogic; + signal ex5_zx :std_ulogic; + signal ex5_k_nan :std_ulogic; + signal ex5_k_inf :std_ulogic; + signal ex5_k_max :std_ulogic; + signal ex5_k_zer :std_ulogic; + signal ex5_k_int_maxpos :std_ulogic; + signal ex5_k_int_maxneg :std_ulogic; + signal ex5_k_int_zer :std_ulogic; + signal ex4_gen_any :std_ulogic; + signal ex4_k_nan :std_ulogic; + signal ex4_k_inf :std_ulogic; + signal ex4_k_max :std_ulogic; + signal ex4_k_zer :std_ulogic; + signal ex4_k_int_maxpos :std_ulogic; + signal ex4_k_int_maxneg :std_ulogic; + signal ex4_k_int_zer :std_ulogic; + signal ex4_k_nan_x :std_ulogic; + signal ex4_k_inf_x :std_ulogic; + signal ex4_k_max_x :std_ulogic; + signal ex4_k_zer_x :std_ulogic; + signal ex2_a_valid :std_ulogic; + signal ex2_c_valid :std_ulogic; + signal ex2_b_valid :std_ulogic; + signal ex2_prod_zero :std_ulogic; + signal ex4_byp_prod_nz :std_ulogic ; + signal ex3_byp_prod_nz :std_ulogic ; + signal ex3_byp_prod_nz_sub :std_ulogic ; + signal ex3_a_valid :std_ulogic ; + signal ex3_c_valid :std_ulogic ; + signal ex3_b_valid :std_ulogic ; + signal ex3_prod_zero :std_ulogic ; + signal ex4_int_fr :std_ulogic ; + signal ex4_int_fi :std_ulogic ; + signal ex4_fi_spec :std_ulogic; + signal ex4_fr_spec :std_ulogic; + signal ex5_fi_spec :std_ulogic; + signal ex5_fr_spec :std_ulogic; + signal ex2_toint_genz :std_ulogic; + signal ex2_a_snan :std_ulogic; + signal ex2_b_snan :std_ulogic; + signal ex2_c_snan :std_ulogic; + signal ex2_a_qnan :std_ulogic; + signal ex2_b_qnan :std_ulogic; + signal ex2_nan_op_grp1 :std_ulogic; + signal ex2_nan_op_grp2 :std_ulogic; + signal ex2_compo :std_ulogic; + signal ex5_fprf_hold :std_ulogic; + signal ex4_fprf_hold :std_ulogic; + signal ex4_fprf_hold_ops :std_ulogic; + signal ex1_bf_10000 :std_ulogic; + signal ex2_bf_10000 :std_ulogic; + signal ex3_bf_10000 :std_ulogic; + + signal ex1_rnd_to_int :std_ulogic; + signal ex2_rnd_to_int :std_ulogic; + signal ex3_rnd_to_int :std_ulogic; + signal ex4_rnd_to_int :std_ulogic; + signal ex3_lt_bias :std_ulogic; + signal ex3_eq_bias_m1 :std_ulogic; +signal ex3_gen_rnd2int :std_ulogic; +signal ex3_gen_one_rnd2int :std_ulogic; +signal ex3_gen_zer_rnd2int :std_ulogic; +signal ex2_gen_one, ex3_gen_one, ex3_gen_one_mutex :std_ulogic; +signal ex4_gen_one :std_ulogic; +signal ex4_k_one :std_ulogic; +signal ex5_k_one :std_ulogic; +signal ex4_k_one_x :std_ulogic; +signal ex3_rnd2int_up :std_ulogic; +signal ex4_sel_est :std_ulogic; +signal ex1_ve :std_ulogic; +signal ex1_oe :std_ulogic; +signal ex1_ue :std_ulogic; +signal ex1_ze :std_ulogic; +signal ex1_xe :std_ulogic; +signal ex1_nonieee :std_ulogic; +signal ex1_rnd0 :std_ulogic; +signal ex1_rnd1 :std_ulogic; +signal ex1_rnd_dis :std_ulogic; + signal rf1_fsel :std_ulogic; + signal rf1_from_integer :std_ulogic; + signal rf1_to_integer :std_ulogic; + signal rf1_math :std_ulogic; + signal rf1_est_recip :std_ulogic; + signal rf1_est_rsqrt :std_ulogic; + signal rf1_move :std_ulogic; + signal rf1_compare :std_ulogic; + signal rf1_prenorm :std_ulogic; + signal rf1_frsp :std_ulogic; + signal rf1_mv_to_scr :std_ulogic; + signal rf1_mv_from_scr :std_ulogic; + signal rf1_div_beg :std_ulogic; + signal rf1_sqrt_beg :std_ulogic; + signal rf1_sp :std_ulogic; + signal rf1_word :std_ulogic; + signal rf1_ordered :std_ulogic; + signal rf1_sub_op :std_ulogic; + signal rf1_op_rnd_v :std_ulogic; + signal rf1_inv_sign :std_ulogic; + signal rf1_sign_ctl :std_ulogic_vector(0 to 1); + signal rf1_sgncpy, ex1_sgncpy :std_ulogic; + signal rf1_op_rnd :std_ulogic_vector(0 to 1); + signal rf1_rnd_to_int :std_ulogic; + signal ex2_effsub_eac :std_ulogic; + signal ex1_flush_dis_dp, ex1_flush_dis_sp :std_ulogic; + signal ex4_to_integer_ken :std_ulogic; + signal rf1_log2e, rf1_pow2e :std_ulogic; + signal ex1_log2e, ex1_pow2e :std_ulogic; + signal ex2_log2e, ex2_pow2e :std_ulogic; + signal ex3_log2e, ex3_pow2e :std_ulogic; + signal ex4_log2e, ex4_pow2e :std_ulogic; + signal ex2_log_ofzero :std_ulogic ; + signal ex2_bexpu_le126 , ex2_gt126 , ex2_ge128 :std_ulogic; + signal ex2_gen_nan_log :std_ulogic ; + signal ex2_gen_inf_log :std_ulogic ; + signal ex2_gen_inf_pow :std_ulogic ; + signal ex2_gen_zero_pow :std_ulogic ; + signal ex1_ovf_unf_dis, ex2_ovf_unf_dis, ex3_ovf_unf_dis, ex4_ovf_unf_dis :std_ulogic; + signal ex2_exact_zero_sign :std_ulogic ; + signal ex2_rnd_ni :std_ulogic ; + signal ex2_gen_inf_sq :std_ulogic; + signal ex2_gen_inf_dv :std_ulogic; + signal ex2_gen_zer_sq :std_ulogic; + signal ex2_gen_zer_dv :std_ulogic; + signal ex2_gen_nan_sq :std_ulogic; + signal ex2_gen_nan_dv :std_ulogic; + signal ex2_prenorm_special :std_ulogic ; + signal ex2_prenorm_sign :std_ulogic ; + + signal ex3_uc_inc_lsb , ex4_uc_inc_lsb , ex5_uc_inc_lsb :std_ulogic; + signal ex3_uc_guard , ex4_uc_guard , ex5_uc_guard :std_ulogic; + signal ex3_uc_sticky , ex4_uc_sticky , ex5_uc_sticky :std_ulogic; + signal ex3_uc_gs_v , ex4_uc_gs_v , ex4_uc_s_v , ex4_uc_g_v, ex5_uc_s_v , ex5_uc_g_v :std_ulogic; + signal ex2_uc_g_ig ,ex3_uc_g_ig , ex4_uc_g_ig :std_ulogic; + signal ex1_force_excp_dis :std_ulogic ; + signal rf1_uc_end_nspec, ex1_uc_end_nspec :std_ulogic; + signal rf1_uc_end_spec, ex1_uc_end_spec, ex2_uc_end_spec, ex3_uc_end_spec, ex4_uc_end_spec :std_ulogic; + signal unused :std_ulogic; + signal rf1_nj_deno_x, ex1_nj_deno, ex2_nj_deno, ex3_nj_deno, ex3_nj_deno_x, ex4_nj_deno : std_ulogic; + signal rf1_nj_deni_x, ex1_nj_deni, rf1_den_ok :std_ulogic; + signal ex2_gen_nan_pow :std_ulogic ; + signal ex2_inf_and_beyond_sp :std_ulogic ; + signal ex1_ftdiv, ex1_ftsqrt, ex2_ftdiv, ex2_ftsqrt, ex2_accuracy , ex2_b_imp :std_ulogic ; + + +begin + + unused <= ex3_byp_prod_nz_sub or ex4_sel_spec_f or + rf1_act or + ex2_op_rnd(0) or --lat-- + ex2_op_rnd(1) or --lat-- + ex3_b_sign_adj or --lat-- + ex3_b_valid or --lat-- + ex3_gen_max or --lat-- ???? + ex3_sh_unf or --lat-- + ex3_sh_ovf or --lat-- + ex4_nonieee or --lat-- + ex4_xe or --lat-- + ex4_fsel or --lat-- + ex4_move or --lat-- + ex4_prenorm or --lat-- + ex4_div_beg or --lat-- + ex4_sqrt_beg or --lat-- + ex4_sub_op or --lat-- + ex4_log2e or --lat-- + ex4_pow2e or --lat-- + ex5_unused; --lat-- + + +--//################################################################ +--//# pervasive +--//################################################################ + + thold_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => thold_1, + q(0) => thold_0 ); + + sg_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => sg_1 , + q(0) => sg_0 ); + + + lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map ( + clkoff_b => clkoff_b, + thold => thold_0, + sg => sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => thold_0_b ); + + + +--//################################################################ +--//# act +--//################################################################ + + + + act_lat: tri_rlmreg_p generic map (width=> 21, expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + forcee => forcee, --tidn, + delay_lclkr => delay_lclkr(4), --tidn, + mpw1_b => mpw1_b(4), --tidn, + mpw2_b => mpw2_b(0), --tidn, + act => fpu_enable, --tiup + thold_b => thold_0_b, --tiup, + sg => sg_0, --tidn, + scout => act_so , + scin => act_si , + ------------------- + din(0) => spare_unused(0), + din(1) => spare_unused(1), + din(2) => tiup, + din(3) => f_dcd_rf1_act, + din(4) => f_dcd_rf1_act, + din(5) => f_dcd_rf1_act, + din(6) => f_dcd_rf1_act, + din(7) => tiup, + din(8) => f_dcd_rf1_act , + din(9) => f_dcd_rf1_act, + din(10) => f_dcd_rf1_act, + din(11) => f_dcd_rf1_act, + din(12) => ex1_act, + din(13) => ex1_act, + din(14) => ex1_act, + din(15) => ex2_act, + din(16) => ex2_act, + din(17) => ex2_act, + din(18) => ex3_act, + din(19) => spare_unused(2), + din(20) => spare_unused(3), + ------------------- + dout(0) => spare_unused(0), + dout(1) => spare_unused(1), + dout(2) => f_pic_fmt_ex1_act , --output + dout(3) => f_pic_eie_ex1_act , --output + dout(4) => f_pic_mul_ex1_act , --output + dout(5) => f_pic_alg_ex1_act , --output + dout(6) => f_pic_cr2_ex1_act , --output + dout(7) => rf1_act, + dout(8) => f_pic_tbl_ex1_act , --output + dout(9) => ex1_act, + dout(10) => ex1_act_add , + dout(11) => ex1_act_lza , + dout(12) => ex2_act, + dout(13) => ex2_act_eov , + dout(14) => ex2_act_scr , + dout(15) => ex3_act, + dout(16) => ex3_act_nrm , + dout(17) => ex3_act_rnd , + dout(18) => ex4_act, + dout(19) => spare_unused(2) , + dout(20) => spare_unused(3) ); + + + + f_pic_add_ex1_act_b <= not ex1_act_add ; + f_pic_lza_ex1_act_b <= not ex1_act_lza ; + f_pic_eov_ex2_act_b <= not ex2_act_eov ; + f_pic_scr_ex2_act_b <= not ex2_act_scr ; + f_pic_nrm_ex3_act_b <= not ex3_act_nrm ; + f_pic_rnd_ex3_act_b <= not ex3_act_rnd ; + + + +--//################################################################ +--//# ex1 latches +--//################################################################ + + + rf1_fsel <= not f_dcd_rf1_fsel_b ; + rf1_from_integer <= not f_dcd_rf1_from_integer_b ; + rf1_to_integer <= not f_dcd_rf1_to_integer_b ; + rf1_math <= not f_dcd_rf1_math_b ; + rf1_est_recip <= not f_dcd_rf1_est_recip_b ; + rf1_est_rsqrt <= not f_dcd_rf1_est_rsqrt_b ; + rf1_move <= not f_dcd_rf1_move_b ; + rf1_compare <= not f_dcd_rf1_compare_b ; + rf1_prenorm <= not(f_dcd_rf1_prenorm_b) or f_dcd_rf1_div_beg or f_dcd_rf1_sqrt_beg ; + rf1_frsp <= not f_dcd_rf1_frsp_b ; + rf1_mv_to_scr <= not f_dcd_rf1_mv_to_scr_b ; + rf1_mv_from_scr <= not f_dcd_rf1_mv_from_scr_b ; + rf1_div_beg <= f_dcd_rf1_div_beg ; + rf1_sqrt_beg <= f_dcd_rf1_sqrt_beg ; + rf1_sp <= not f_dcd_rf1_sp ; + rf1_word <= not f_dcd_rf1_word_b ; + rf1_uns <= not f_dcd_rf1_uns_b ; + rf1_sp_conv <= not f_dcd_rf1_sp_conv_b ; + rf1_ordered <= not f_dcd_rf1_ordered_b ; + rf1_sub_op <= not f_dcd_rf1_sub_op_b ; + rf1_op_rnd_v <= not f_dcd_rf1_op_rnd_v_b ; + rf1_inv_sign <= not f_dcd_rf1_inv_sign_b ; + rf1_sign_ctl(0) <= not f_dcd_rf1_sign_ctl_b(0) ; + rf1_sign_ctl(1) <= not f_dcd_rf1_sign_ctl_b(1) ; + rf1_sgncpy <= not f_dcd_rf1_sgncpy_b ; + rf1_op_rnd(0) <= not f_dcd_rf1_op_rnd_b(0) ; + rf1_op_rnd(1) <= not f_dcd_rf1_op_rnd_b(1) ; + rf1_rnd_to_int <= not f_dcd_rf1_rnd_to_int_b ; + rf1_log2e <= not f_dcd_rf1_log2e_b ; + rf1_pow2e <= not f_dcd_rf1_pow2e_b ; + rf1_uc_end_nspec <= f_dcd_rf1_uc_end and not f_dcd_rf1_uc_special ; + rf1_uc_end_spec <= f_dcd_rf1_uc_end and f_dcd_rf1_uc_special ; + + + rf1_den_ok <= rf1_move or rf1_mv_to_scr or rf1_mv_from_scr or rf1_fsel or f_dcd_rf1_uc_mid ; + + + rf1_nj_deno_x <= f_dcd_rf1_nj_deno and + not f_dcd_rf1_div_beg and + not f_dcd_rf1_sqrt_beg and + not rf1_to_integer and -- do not want denorm outputs in the middle of a divide + not rf1_den_ok ; + + rf1_nj_deni_x <= f_dcd_rf1_nj_deni and + not rf1_den_ok ; -- do not want denorm outputs in the middle of a divide + + + + ex1_ctl_lat: tri_rlmreg_p generic map (width=> 43, expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + forcee => forcee,--tidn, + delay_lclkr => delay_lclkr(1), --tidn, + mpw1_b => mpw1_b(1), --tidn, + mpw2_b => mpw2_b(0), --tidn, + nclk => nclk, + act => f_dcd_rf1_act, + thold_b => thold_0_b, + sg => sg_0, + scout => ex1_ctl_so , + scin => ex1_ctl_si , + ------------------- + din( 0) => rf1_fsel , + din( 1) => rf1_from_integer , + din( 2) => rf1_to_integer , + din( 3) => rf1_math , + din( 4) => rf1_est_recip , + din( 5) => rf1_est_rsqrt , + din( 6) => rf1_move , + din( 7) => rf1_compare , + din( 8) => rf1_prenorm , + din( 9) => rf1_frsp , + din(10) => rf1_mv_to_scr , + din(11) => rf1_mv_from_scr , + din(12) => rf1_div_beg , + din(13) => rf1_sqrt_beg , + din(14) => rf1_sp , + din(15) => rf1_word , + din(16) => rf1_ordered , + din(17) => rf1_sub_op , + din(18) => f_dcd_rf1_uc_mid , + din(19) => rf1_op_rnd_v , + din(20) => rf1_inv_sign , + din(21) => rf1_sign_ctl(0) , + din(22) => rf1_sign_ctl(1) , + din(23) => f_dcd_rf1_aop_valid , + din(24) => f_dcd_rf1_cop_valid , + din(25) => f_dcd_rf1_bop_valid , + din(26) => rf1_op_rnd(0) , + din(27) => rf1_op_rnd(1) , + din(28) => rf1_rnd_to_int , + din(29) => rf1_uns , + din(30) => rf1_sp_conv , + din(31) => rf1_sgncpy , + din(32) => rf1_log2e , + din(33) => rf1_pow2e , + din(34) => f_dcd_rf1_uc_ft_pos , + din(35) => f_dcd_rf1_uc_ft_neg , + din(36) => f_dcd_rf1_force_excp_dis , + din(37) => rf1_uc_end_nspec , + din(38) => rf1_uc_end_spec , + din(39) => rf1_nj_deno_x , + din(40) => rf1_nj_deni_x , + din(41) => f_dcd_rf1_ftdiv , + din(42) => f_dcd_rf1_ftsqrt , + + ------------------- + dout( 0) => ex1_fsel , + dout( 1) => ex1_from_integer , + dout( 2) => ex1_to_integer , + dout( 3) => ex1_math , + dout( 4) => ex1_est_recip , + dout( 5) => ex1_est_rsqrt , + dout( 6) => ex1_move , + dout( 7) => ex1_compare , + dout( 8) => ex1_prenorm , + dout( 9) => ex1_frsp , + dout(10) => ex1_mv_to_scr , + dout(11) => ex1_mv_from_scr , + dout(12) => ex1_div_beg , + dout(13) => ex1_sqrt_beg , + dout(14) => ex1_sp_b , + dout(15) => ex1_word , + dout(16) => ex1_ordered , + dout(17) => ex1_sub_op , + dout(18) => ex1_uc_mid , + dout(19) => ex1_op_rnd_v , + dout(20) => ex1_inv_sign , + dout(21) => ex1_sign_ctl (0) , + dout(22) => ex1_sign_ctl (1) , + dout(23) => ex1_a_valid , + dout(24) => ex1_c_valid , + dout(25) => ex1_b_valid , + dout(26) => ex1_op_rnd(0) , + dout(27) => ex1_op_rnd(1) , + dout(28) => ex1_rnd_to_int , + dout(29) => ex1_uns , + dout(30) => ex1_sp_conv , + dout(31) => ex1_sgncpy , + dout(32) => ex1_log2e , + dout(33) => ex1_pow2e , + dout(34) => ex1_uc_ft_pos , + dout(35) => ex1_uc_ft_neg , + dout(36) => ex1_force_excp_dis , + dout(37) => ex1_uc_end_nspec , + dout(38) => ex1_uc_end_spec , + dout(39) => ex1_nj_deno , + dout(40) => ex1_nj_deni , + dout(41) => ex1_ftdiv , + dout(42) => ex1_ftsqrt ); + + f_pic_ex1_ftdiv <= ex1_ftdiv ; + + f_pic_ex1_nj_deni <= ex1_nj_deni ; + + ex1_ovf_unf_dis <= ex1_uc_mid or + ex1_prenorm or + ex1_move or + ex1_fsel or + ex1_mv_to_scr or + ex1_mv_from_scr ; + + ex1_ve <= f_cr2_ex1_fpscr_shadow(0) and not ex1_force_excp_dis; -- 24 + ex1_oe <= f_cr2_ex1_fpscr_shadow(1) and not ex1_force_excp_dis; -- 25 + ex1_ue <= f_cr2_ex1_fpscr_shadow(2) and not ex1_force_excp_dis; -- 26 + ex1_ze <= f_cr2_ex1_fpscr_shadow(3) and not ex1_force_excp_dis; -- 27 + ex1_xe <= f_cr2_ex1_fpscr_shadow(4) and not ex1_force_excp_dis; -- 28 + ex1_nonieee <= f_cr2_ex1_fpscr_shadow(5); -- 29 + + ex1_rnd_fpscr(0 to 1) <= f_cr2_ex1_fpscr_shadow(6 to 7); + + + + ex1_rnd0 <= ( f_cr2_ex1_fpscr_shadow(6) and not ex1_op_rnd_v ) or -- 30 + ( ex1_op_rnd(0) and ex1_op_rnd_v ); + ex1_rnd1 <= ( f_cr2_ex1_fpscr_shadow(7) and not ex1_op_rnd_v ) or -- 31 + ( ex1_op_rnd(1) and ex1_op_rnd_v ) ; + ex1_rnd_dis <= tidn and f_fmt_ex1_prod_zero and ex1_nj_deni ; -- force truncate "01" + + f_pic_ex1_rnd_to_int <= ex1_rnd_to_int ; --output-- + + + + ex1_flush_dis_sp <= ex1_uc_mid or + ex1_fsel or + ex1_log2e or -- denorm input forced to zero + ex1_pow2e or -- denorm input forced to zero + ex1_prenorm or + ex1_move or + ex1_to_integer or + ex1_frsp ;-- (never prenorm frsp) + + ex1_flush_dis_dp <= ex1_flush_dis_sp or + ex1_from_integer or + ex1_ftdiv or + ex1_ftsqrt or + ex1_mv_to_scr ; + + f_pic_ex1_flush_en_sp <= not ex1_flush_dis_sp ; + f_pic_ex1_flush_en_dp <= not ex1_flush_dis_dp ; + + f_pic_ex1_log2e <= ex1_log2e;--output-- + f_pic_ex1_pow2e <= ex1_pow2e;--output-- + + +--//################################################################ +--//# ex1 logic +--//################################################################ + -- fmr/fneg/fabs/fnabs + -- fsel + -- mffs + -- mcrfs, mtcrf, mtfs* + -- prenorm_sp prenorm_dp + -- fcomp + -- fmul fadd fsub fmadd fmsub fnmsub fnmadd + -- fres,frsqrte + -- frsp + --------------------------------------------- + -- + -- + + f_pic_ex1_from_integer <= ex1_from_integer ; --output-- + f_pic_ex1_fsel <= ex1_fsel ; --output-- + + f_pic_ex1_sh_ovf_do <= ex1_fsel or --output-- + ex1_move or + ex1_prenorm or + ex1_mv_to_scr or + ex1_mv_from_scr ; + + f_pic_ex1_sh_ovf_ig_b <= not( ex1_from_integer or not ex1_b_valid ); --output-- + + f_pic_ex1_sh_unf_do <= not ex1_b_valid --output-- + or ex1_est_recip + or ex1_est_rsqrt ; + + f_pic_ex1_sh_unf_ig_b <= not ex1_from_integer ; --output-- --UNSET-- + + +ex1_a_sign <= f_byp_pic_ex1_a_sign ; +ex1_c_sign <= f_byp_pic_ex1_c_sign ; +ex1_b_sign <= f_byp_pic_ex1_b_sign ; + + ex1_b_sign_adj_x <= ex1_b_sign xor ex1_sub_op ; --addend sign adjusted + ex1_p_sign <= ex1_a_sign xor ex1_c_sign ; --product sign + + ex1_b_sign_adj <= -- multiply/divide always use p-sign + (ex1_b_sign_adj_x and ex1_b_valid ) or + (ex1_p_sign and not ex1_b_valid ) ; + + ex1_div_sign <= (ex1_a_sign xor ex1_b_sign) and ex1_div_beg ; + + --//#------------------------------------------ + --//# effective subtract + --//#------------------------------------------ + + f_pic_ex1_effsub_raw <= --output-- + (ex1_math or ex1_compare) and ( ex1_b_sign_adj xor ex1_p_sign ); + + --//#--------------------------------------------- + --//# sign logic alter b-sign for funny moves + --//#--------------------------------------------- + + ex1_b_sign_alt <= + ( ex1_a_sign and ex1_move and ex1_sgncpy and ex1_b_valid ) or + ( ex1_b_sign and ex1_move and ex1_sign_ctl(0) and ex1_b_valid and not ex1_sgncpy ) or + (not ex1_b_sign and ex1_move and ex1_sign_ctl(1) and ex1_b_valid and not ex1_sgncpy ) or + ( f_alg_ex1_sign_frmw and ex1_from_integer and not ex1_uns and ex1_word ) or + ( ex1_b_sign and ex1_from_integer and not ex1_uns and not ex1_word ) or + ( ex1_b_sign_adj and (ex1_math or ex1_compare) ) or + ( ex1_b_sign and not ex1_move + and not (ex1_math or ex1_compare) + and ex1_b_valid + and not ex1_from_integer ) ; + + + +--//################################################################ +--//# ex2 latches +--//################################################################ + + ex1_lzo_dis <= + ( ex1_uc_mid ) or + ( ex1_prenorm ) or + ( ex1_fsel ) or + ( ex1_move ) or + ( ex1_from_integer ) or + ( ex1_est_recip ) or + ( ex1_est_rsqrt ) or + ( ex1_to_integer and not ex1_rnd_to_int); --f_pic_ex2_to_integer + + + + ex1_a_nan <= f_fmt_ex1_a_expo_max and not f_fmt_ex1_a_frac_zero and not ex1_uc_end_nspec and not ex1_uc_mid; + ex1_c_nan <= f_fmt_ex1_c_expo_max and not f_fmt_ex1_c_frac_zero and not ex1_uc_end_nspec and not ex1_uc_mid; + ex1_b_nan <= f_fmt_ex1_b_expo_max and not f_fmt_ex1_b_frac_zero and not ex1_uc_end_nspec and not ex1_uc_mid; + + ex1_a_inf <= f_fmt_ex1_a_expo_max and f_fmt_ex1_a_frac_zero and not ex1_uc_end_nspec and not ex1_uc_mid; + ex1_c_inf <= f_fmt_ex1_c_expo_max and f_fmt_ex1_c_frac_zero and not ex1_uc_end_nspec and not ex1_uc_mid; + ex1_b_inf <= f_fmt_ex1_b_expo_max and f_fmt_ex1_b_frac_zero and not ex1_uc_end_nspec and not ex1_uc_mid; + + ex1_bf_10000 <= ( f_fmt_ex1_b_imp and f_fmt_ex1_b_frac_zero ) or -- imp=1, frac=0 + ( f_fmt_ex1_b_imp and f_fmt_ex1_b_frac_z32 and ex1_word ); + + + f_pic_ex1_frsp_ue1 <= ex1_frsp and ex1_ue ;--output + + + ex1_sp <= not ex1_sp_b ; + + + ex2_ctl_lat: tri_rlmreg_p generic map (width=> 57, expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + forcee => forcee,--tidn, + delay_lclkr => delay_lclkr(2), --tidn, + mpw1_b => mpw1_b(2), --tidn, + mpw2_b => mpw2_b(0), --tidn, + nclk => nclk, + act => ex1_act, + thold_b => thold_0_b, + sg => sg_0, + scout => ex2_ctl_so , + scin => ex2_ctl_si , + ------------------- + din( 0) => ex1_fsel , + din( 1) => ex1_from_integer , + din( 2) => ex1_to_integer , + din( 3) => ex1_math , + din( 4) => ex1_est_recip , + din( 5) => ex1_est_rsqrt , + din( 6) => ex1_move , + din( 7) => ex1_compare , + din( 8) => ex1_prenorm , + din( 9) => ex1_frsp , + din(10) => ex1_mv_to_scr , + din(11) => ex1_mv_from_scr , + din(12) => ex1_div_beg , + din(13) => ex1_sqrt_beg , + din(14) => ex1_sp , + din(15) => ex1_word , + din(16) => ex1_ordered , + din(17) => ex1_sub_op , + din(18) => ex1_lzo_dis , + din(19) => ex1_rnd_dis , + din(20) => ex1_inv_sign , + din(21) => ex1_p_sign , + din(22) => ex1_b_sign_adj , + din(23) => ex1_b_sign_alt , + din(24) => ex1_a_sign , + din(25) => ex1_a_valid , + din(26) => ex1_c_valid , + din(27) => ex1_b_valid , + din(28) => f_fmt_ex1_prod_zero , + din(29) => ex1_rnd0 , + din(30) => ex1_rnd1 , + din(31) => ex1_rnd_to_int , + din(32) => ex1_ve , + din(33) => ex1_oe , + din(34) => ex1_ue , + din(35) => ex1_ze , + din(36) => ex1_xe , + din(37) => ex1_nonieee , + din(38) => ex1_rnd0 , + din(39) => ex1_rnd1 , + din(40) => ex1_sp_conv , + din(41) => ex1_uns , + din(42) => ex1_log2e , + din(43) => ex1_pow2e , + din(44) => ex1_ovf_unf_dis , + din(45) => ex1_rnd_fpscr(0) , + din(46) => ex1_rnd_fpscr(1) , + din(47) => ex1_div_sign , + din(48) => ex1_uc_ft_pos , + din(49) => ex1_uc_ft_neg , + din(50) => ex1_uc_mid , + din(51) => ex1_uc_end_spec , + din(52) => ex1_nj_deno , + din(53) => ex1_ftdiv , + din(54) => ex1_ftsqrt , + din(55) => tiup , -- tie to the accuracy level + din(56) => f_fmt_ex1_b_imp , + dout( 0) => ex2_fsel , + dout( 1) => ex2_from_integer , + dout( 2) => ex2_to_integer , + dout( 3) => ex2_math , + dout( 4) => ex2_est_recip , + dout( 5) => ex2_est_rsqrt , + dout( 6) => ex2_move , + dout( 7) => ex2_compare , + dout( 8) => ex2_prenorm , + dout( 9) => ex2_frsp , + dout(10) => ex2_mv_to_scr , + dout(11) => ex2_mv_from_scr , + dout(12) => ex2_div_beg , + dout(13) => ex2_sqrt_beg , + dout(14) => ex2_sp , + dout(15) => ex2_word , + dout(16) => ex2_ordered , + dout(17) => ex2_sub_op , + dout(18) => ex2_lzo_dis , + dout(19) => ex2_rnd_dis , + dout(20) => ex2_inv_sign , + dout(21) => ex2_p_sign , + dout(22) => ex2_b_sign_adj , + dout(23) => ex2_b_sign_alt , + dout(24) => ex2_a_sign , + dout(25) => ex2_a_valid , + dout(26) => ex2_c_valid , + dout(27) => ex2_b_valid , + dout(28) => ex2_prod_zero , + dout(29) => ex2_op_rnd(0) , + dout(30) => ex2_op_rnd(1) , + dout(31) => ex2_rnd_to_int , + dout(32) => ex2_ve , + dout(33) => ex2_oe , + dout(34) => ex2_ue , + dout(35) => ex2_ze , + dout(36) => ex2_xe , + dout(37) => ex2_nonieee , + dout(38) => ex2_rnd0 , + dout(39) => ex2_rnd1 , + dout(40) => ex2_sp_conv , + dout(41) => ex2_uns , + dout(42) => ex2_log2e , + dout(43) => ex2_pow2e , + dout(44) => ex2_ovf_unf_dis , + dout(45) => ex2_rnd_fpscr(0) , + dout(46) => ex2_rnd_fpscr(1) , + dout(47) => ex2_div_sign , + dout(48) => ex2_uc_ft_pos , + dout(49) => ex2_uc_ft_neg , + dout(50) => ex2_uc_mid , + dout(51) => ex2_uc_end_spec , + dout(52) => ex2_nj_deno , + dout(53) => ex2_ftdiv , + dout(54) => ex2_ftsqrt , + dout(55) => ex2_accuracy , + dout(56) => ex2_b_imp ); + + + ex2_to_int_uns_neg <= ex2_to_integer and not ex2_rnd_to_int and ex2_uns and ex2_b_sign_alt; + ex2_wd_ov_x <= f_eie_ex2_wd_ov; -- or ex2_to_int_uns_neg; -- keep uns neg seperate + ex2_dw_ov_x <= f_eie_ex2_dw_ov; -- or ex2_to_int_uns_neg; -- keep uns neg seperate + + + f_pic_ex2_frsp_ue1 <= ex2_frsp and ex2_ue;--output + f_pic_ex2_b_valid <= ex2_b_valid; --output + f_pic_ex2_ue1 <= ex2_ue or ex2_ovf_unf_dis ;--output + + + ex1_sp_invalid <= ( f_fmt_ex1_sp_invalid and ex1_sp and not ex1_from_integer + and not ex1_uc_mid and not ex1_uc_end_nspec); + + + ex2_flg_lat: tri_rlmreg_p generic map (width=> 18, expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + forcee => forcee,--tidn, + delay_lclkr => delay_lclkr(2), --tidn, + mpw1_b => mpw1_b(2), --tidn, + mpw2_b => mpw2_b(0), --tidn, + nclk => nclk, + act => ex1_act, + thold_b => thold_0_b, + sg => sg_0, + scout => ex2_flg_so , + scin => ex2_flg_si , + ------------------- + din( 0) => f_fmt_ex1_a_frac_msb , + din( 1) => f_fmt_ex1_c_frac_msb , + din( 2) => f_fmt_ex1_b_frac_msb , + din( 3) => f_fmt_ex1_a_zero , + din( 4) => f_fmt_ex1_c_zero , + din( 5) => f_fmt_ex1_b_zero , + din( 6) => ex1_a_nan , + din( 7) => ex1_c_nan , + din( 8) => ex1_b_nan , + din( 9) => ex1_a_inf , + din(10) => ex1_b_inf , + din(11) => ex1_c_inf , + din(12) => ex1_sp_invalid , + din(13) => ex1_bf_10000 , + din(14) => f_fmt_ex1_bexpu_le126 , + din(15) => f_fmt_ex1_gt126 , + din(16) => f_fmt_ex1_ge128 , + din(17) => f_fmt_ex1_inf_and_beyond_sp , + ------------------- + dout( 0) => ex2_a_frac_msb , + dout( 1) => ex2_c_frac_msb , + dout( 2) => ex2_b_frac_msb , + dout( 3) => ex2_a_zero , + dout( 4) => ex2_c_zero , + dout( 5) => ex2_b_zero , + dout( 6) => ex2_a_nan , + dout( 7) => ex2_c_nan , + dout( 8) => ex2_b_nan , + dout( 9) => ex2_a_inf , + dout(10) => ex2_b_inf , + dout(11) => ex2_c_inf , + dout(12) => ex2_sp_invalid , + dout(13) => ex2_bf_10000 , + dout(14) => ex2_bexpu_le126 , + dout(15) => ex2_gt126 , + dout(16) => ex2_ge128 , + dout(17) => ex2_inf_and_beyond_sp ); + + + +--//################################################################ +--//# ex2 logic +--//################################################################ + + f_pic_ex2_sp_b <= not ex2_sp; --output-- + f_pic_ex2_to_integer <= ex2_to_integer and not ex2_rnd_to_int; --output-- --lza only + f_pic_ex2_prenorm <= ex2_prenorm ; + + + f_pic_ex2_force_sel_bexp <= --output-- + (ex2_from_integer ) or + (ex2_move ) or + (ex2_mv_to_scr ) or + (ex2_mv_from_scr ) or + (ex2_prenorm ) or + (ex2_est_recip ) or + (ex2_est_rsqrt ) ; + + f_pic_ex2_est_recip <= ex2_est_recip;--output--feie + f_pic_ex2_est_rsqrt <= ex2_est_rsqrt;--output--feie + + f_pic_ex2_sp_lzo <= --output-- + (ex2_frsp ) or + (ex2_math and ex2_sp ); + + f_pic_ex2_lzo_dis_prod <= --output-- + (ex2_math and ex2_ue ) or + (ex2_frsp and ex2_ue ) or + (ex2_lzo_dis ); -- intermediate steps div/sqrt + + f_pic_ex2_math_bzer_b <= not( ex2_math and ex2_b_zero ); + + + ex2_rnd_nr <= not ex2_rnd_dis and not ex2_rnd0 and not ex2_rnd1 ; + ex2_rnd_inf_ok <= not ex2_rnd_dis and ex2_rnd0 and not (ex2_rnd1 xor ex2_b_sign_alt) ; + + f_pic_ex2_rnd_nr <= ex2_rnd_nr ; + f_pic_ex2_rnd_inf_ok <= ex2_rnd_inf_ok ; + + --//#------------------------------------------------------ + --//# special cases from inputs + --//#------------------------------------------------------ + --//# special cases can force 4 different results: PassNan genNan Inf Zero + --//# (the value of inf can be modified based on round-mode) + --//# + --//# ................................................................... + --//# @@ Specail Cases From inputs (other than NAN) + --//# COMPARE : no special cases other than NAN which sets NAN compare + --//# + --//# FROMINT : BZero T=+Zero FI=0 FR=0 UX=0 OX=0 FPRF=+Zero // all others are +/- NORM + --//# + --//# TOINT : BZero+ T=+Zero FI=0 FR=0 UX=0 OX=0 FPRF=00000 (ALL TOINTEGER UX=0 OX=0 FPRF=00000) + --//# TOINT : BZero- T=+Zero FI=0 FR=0 UX=0 OX=0 FPRF=00000 (ALL TOINTEGER UX=0 OX=0 FPRF=00000) + --//# TOINT : BNan T=80000 Fi=0 Fr=0 Ux=0 Ox=0 FPRF=00000 (ALL TOINTEGER UX=0 OX=0 FPRF=00000) + --//# TOINT : BInf+ T=PIPE Fi=0 Fr=0 Ux=0 Ox=0 FPRF=00000 (ALL TOINTEGER UX=0 OX=0 FPRF=00000) + --//# TOINT : BInf- T=PIPE Fi=0 Fr=0 Ux=0 Ox=0 FPRF=00000 (ALL TOINTEGER UX=0 OX=0 FPRF=00000) + --//# + --//# FRES : BZer+ T=+INF Fi=0 Fr=0 Ux=0 Ox=0 FPRF=+INF // ZX (Ve=1: hold FPRF) + --//# FRES : BZer- T=-INF Fi=0 Fr=0 Ux=0 Ox=0 FPRF=-INF // ZX (Ve=1: hold FPRF) + --//# FRES : BInf+ T=+Zer Fi=0 Fr=0 Ux=0 Ox=0 FPRF=+Zer + --//# FRES : BInf- T=-Zer Fi=0 Fr=0 Ux=0 Ox=0 FPRF=-Zer + --//# FRES : BNAN T=PASS Fi=0 Fr=0 Ux=0 Ox=0 FPRF=qNAN + --//# + --//# FRSQRTE : BZer+ T=Inf+ Fi=0 Fr=0 Ux=0 Ox=0 FPRF=Inf+ // ZX (Ve=1: hold FPRF) + --//# FRSQRTE : BZer- T=Inf- Fi=0 Fr=0 Ux=0 Ox=0 FPRF=Inf- // ZX (Ve=1: hold FPRF) + --//# FRSQRTE : BInf- T=NAN Fi=0 Fr=0 Ux=0 Ox=0 FPRF=nan // vxsqrt + --//# FRSQRTE : B- T=NAN Fi=0 Fr=0 Ux=0 Ox=0 FPRF=nan // vxsqrt + --//# FRSQRTE : BInf+ T=Zer+ Fi=0 Fr=0 Ux=0 Ox=0 FPRF=Zer+ + --//# FRSQRTE : BNan T=PASS Fi=0 Fr=0 Ux=0 Ox=0 FPRF=nan // vxsnan[?12] + --//# + --//# SQRT_END : BZer+ T=Zer+ Fi=0 Fr=0 Ux=0 Ox=0 FPRF=Zer+ + --//# SQRT_END : BZer- T=Zer- Fi=0 Fr=0 Ux=0 Ox=0 FPRF=Zer- + --//# SQRT_END : BINF- T=NAN Fi=0 Fr=0 Ux=0 Ox=0 FPRF=NAN // vxsqrt + --//# SQRT_END : B- T=NAN Fi=0 Fr=0 Ux=0 Ox=0 FPRF=NAN // vxsqrt + --//# SQRT_END : BINF+ T=Inf+ Fi=0 Fr=0 Ux=0 Ox=0 FPRF=Inf+ + --//# SQRT_END : BNan T=PASS Fi=0 Fr=0 Ux=0 Ox=0 FPRF=nan // vxsnan[?12] + --//# + --//# DIV_BEG : BZer+ T=Inf? Fi=0 Fr=0 Ux=0 Ox=0 FPRF=Inf? // ZX (Ve=1: hold FPRF) (vxZDZ if A=Zer) + --//# DIV_BEG : BZer- T=Inf? Fi=0 Fr=0 Ux=0 Ox=0 FPRF=Inf? // ZX (Ve=1: hold FPRF) (vxZDZ if A=Zer) + --//# DIV_BEG : BNAN T=Pass Fi=0 Fr=0 Ux=0 Ox=0 FPRF=nan // vxsnan[?12] + --//# DIV_BEG : BInf+ T=Zer? Fi=0 Fr=0 Ux=0 Ox=0 FPRF=Zer? // (vxIDI if A=Inf) + --//# DIV_BEG : BInf- T=Zer? Fi=0 Fr=0 Ux=0 Ox=0 FPRF=Zer? // (vxIDI if A=Inf) + --//# DIV_BEG : Both,AInf T=Inf? Fi=0 Fr=0 Ux=0 Ox=0 FPRF=Inf? // + --//# DIV_BEG : Both,AZer T=Zer? Fi=0 Fr=0 Ux=0 Ox=0 FPRF=Zer? // + --//# + --//# FRSP : BZer+ T=Zer+ Fi=0 Fr=0 Ux=0 Ox=0 Fprf=Zer+ + --//# FRSP : BZer- T=Zer- Fi=0 Fr=0 Ux=0 Ox=0 Fprf=Zer- + --//# FRSP : BInf+ T=Inf+ Fi=0 Fr=0 Ux=0 Ox=0 Fprf=Inf+ + --//# FRSP : BInf- T=Inf- Fi=0 Fr=0 Ux=0 Ox=0 Fprf=Inf- + --//# FRSP : BNan T=Pass Fi=0 Fr=0 Ux=0 Ox=0 Fprf=Nan? + --//# + --//# MATH : ANAN T=Pass Fi=0 Fr=0 Ux=0 Ox=0 Fprf=Nan? + --//# MATH : BNAN T=Pass Fi=0 Fr=0 Ux=0 Ox=0 Fprf=Nan? + --//# MATH : CNAN T=Pass Fi=0 Fr=0 Ux=0 Ox=0 Fprf=Nan? + --//# MATH : BZer*AZer T=Zer@@ Fi-0 Fr=0 Ux=0 Ox=0 Fprf=Zer@@ @@:ExactZero Rounding Rule + --//# MATH : BZer*CZer T=Zer@@ Fi-0 Fr=0 Ux=0 Ox=0 Fprf=Zer@@ @@:ExactZero Rounding Rule + --//# + --//# MATH : AINF|CINF|BINF T=??? Fi=0 Fr=0 Ux=0 Ox=0 Fprf=??? + --//# + --//# A C B + --//# Z I x => GenNan : vxIMZ + --//# I Z x => GenNan : vxIMZ + --//# I !Z I => GenNan : vxISI if effsub + --//# !Z I I => GenNan : vxISI if effsub + --//# I !Z I => INF : if effadd // sign = psign + --//# !Z I I => INF : if effadd // sign = psign + --//# I !Z !I => INF : psign + --//# !Z I !I => INF : psign + --//# !ZI !ZI I => INF : bsign xor sub_op + --//# + + --//#---------------------------------------------------- + --//# pass NAN (math,est,frsp) + --//#---------------------------------------------------- + + ex2_a_snan <= ex2_a_nan and not ex2_a_frac_msb; + ex2_b_snan <= ex2_b_nan and not ex2_b_frac_msb; + ex2_c_snan <= ex2_c_nan and not ex2_c_frac_msb; + ex2_a_qnan <= ex2_a_nan and ex2_a_frac_msb; + ex2_b_qnan <= ex2_b_nan and ex2_b_frac_msb; + ex2_nan_op_grp1 <= ex2_math or ex2_est_recip or ex2_est_rsqrt or ex2_frsp or ex2_compare + or ex2_rnd_to_int or ex2_div_beg or ex2_sqrt_beg ; + ex2_nan_op_grp2 <= ex2_nan_op_grp1 or ex2_to_integer or ex2_div_beg; + ex2_compo <= ex2_compare and ex2_ordered ; + + ex2_pass_en <= (ex2_a_nan or ex2_c_nan or ex2_b_nan ); + ex2_pass_nan <= ex2_nan_op_grp1 and ex2_pass_en ; + + + ex2_vxsnan <= + (ex2_a_snan and ex2_nan_op_grp1 ) or + (ex2_c_snan and ex2_nan_op_grp1 ) or + (ex2_b_snan and ex2_nan_op_grp2 ) or + (f_dcd_ex2_uc_vxsnan ) ; + + ex2_vxvc <= --(2) + (ex2_compo and ex2_a_qnan and not ex2_b_snan ) or -- qnan + (ex2_compo and ex2_b_qnan and not ex2_a_snan ) or -- qnan + (ex2_compo and ex2_a_snan and not ex2_ve ) or -- snan + (ex2_compo and ex2_b_snan and not ex2_ve ) ; -- snan + + ex2_vxcvi <= --(3) + (ex2_to_integer and ex2_b_nan and not ex2_rnd_to_int) and not ex2_sp_invalid; + + ex2_vxzdz <= f_dcd_ex2_uc_vxzdz or --(4) FDIV only + (ex2_a_zero and ex2_b_zero and ex2_div_beg and not ex2_sp_invalid) ; + + ex2_vxidi <= f_dcd_ex2_uc_vxidi or --(5) FDIV only + (ex2_a_inf and ex2_b_inf and ex2_div_beg and not ex2_sp_invalid) ; + + + + --//#---------------------------------------------------- + --//# special case genNAN + --//#---------------------------------------------------- + + ex2_p_inf <= ex2_a_inf or ex2_c_inf; + ex2_p_zero <= ex2_a_zero or ex2_c_zero; + + + ex2_vximz <= --(6) + (ex2_math and ex2_p_inf and ex2_p_zero) and not ex2_sp_invalid; + + ex2_vxisi <= --(7) + (ex2_math and ex2_b_inf and ex2_p_inf and not ex2_p_zero and not f_alg_ex2_effsub_eac_b ) and not ex2_sp_invalid; + + ex2_vxsqrt <= f_dcd_ex2_uc_vxsqrt or --(8) + ( (ex2_est_rsqrt or ex2_sqrt_beg) and ex2_b_sign_alt and not ex2_b_zero and not ex2_b_nan and not ex2_sp_invalid) ; + + ex2_gen_nan_dv <= (ex2_a_zero and ex2_b_zero and ex2_div_beg ) or + ( (ex2_vxidi or ex2_sp_invalid) and ex2_div_beg ); + + ex2_gen_nan_sq <= (ex2_vxsqrt or ex2_sp_invalid) and ex2_sqrt_beg ; + + ex2_gen_nan <= (ex2_b_nan and ex2_to_integer and not ex2_rnd_to_int) or + ex2_gen_nan_log or + ex2_gen_nan_pow or + ex2_vxisi or + ex2_vximz or + (ex2_a_zero and ex2_b_zero and ex2_div_beg ) or + ex2_vxsqrt or + ex2_vxidi or + (ex2_sp_invalid and not ex2_pow2e and not ex2_log2e ) ;-- sp op requires exponent in sp range (except frsp) + + -- NAN *log:QNAN_PASS *pow: QNAN_PASS + -- -INF *log:QNAN_dflt pow: +0 + -- +INF *log:+INF *pow: +INF + -- -0 *log:-INF *pow: +1 + -- +0 *log:-INF *pow: +1 + -- NEG *log:QNAN_dflt *pow: xxxxx + -- -0 8, expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + forcee => forcee, --tidn, + delay_lclkr => delay_lclkr(3), --tidn, + mpw1_b => mpw1_b(3), --tidn, + mpw2_b => mpw2_b(0) ,--tidn, + nclk => nclk, + act => ex2_act, + thold_b => thold_0_b, + sg => sg_0, + scout => ex3_scr_so , + scin => ex3_scr_si , + ------------------- + din(0) => ex2_ve , + din(1) => ex2_oe , + din(2) => ex2_ue , + din(3) => ex2_ze , + din(4) => ex2_xe , + din(5) => ex2_nonieee , + din(6) => ex2_rnd0 , + din(7) => ex2_rnd1 , + ------------------- + dout(0) => ex3_ve , + dout(1) => ex3_oe , + dout(2) => ex3_ue , + dout(3) => ex3_ze , + dout(4) => ex3_xe , + dout(5) => ex3_nonieee , + dout(6) => ex3_rnd0 , + dout(7) => ex3_rnd1 ); + + + --//#---------------------------------------------------- + --//# Don't truncate NaN's to SP on first divide/sqrt pass (*_beg = 1) + + ex2_sp_notrunc <= ex2_sp and not ( + ( ex2_div_beg and (ex2_a_nan or ex2_b_nan)) or + ( ex2_sqrt_beg and ex2_b_nan) ); + + + + ex2_sp_o_frsp <= ex2_sp_notrunc or ex2_frsp; + + + ex3_ctl_lat: tri_rlmreg_p generic map (width=> 34, expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + forcee => forcee,--tidn, + delay_lclkr => delay_lclkr(3), --tidn, + mpw1_b => mpw1_b(3), --tidn, + mpw2_b => mpw2_b(0), --tidn, + nclk => nclk, + act => ex2_act, + thold_b => thold_0_b, + sg => sg_0, + scout => ex3_ctl_so , + scin => ex3_ctl_si , + ------------------- + din( 0) => ex2_fsel , + din( 1) => ex2_from_integer , + din( 2) => ex2_to_integer , + din( 3) => ex2_math , + din( 4) => ex2_est_recip , + din( 5) => ex2_est_rsqrt , + din( 6) => ex2_move , + din( 7) => ex2_compare , + din( 8) => ex2_prenorm , + din( 9) => ex2_frsp , + din(10) => ex2_mv_to_scr , + din(11) => ex2_mv_from_scr , + din(12) => ex2_div_beg , + din(13) => ex2_sqrt_beg , + din(14) => ex2_sp_o_frsp , + din(15) => ex2_word , + din(16) => ex2_sub_op , + din(17) => ex2_rnd_dis , + din(18) => ex2_inv_sign , + din(19) => ex2_p_sign , + din(20) => ex2_b_sign_adj , + din(21) => ex2_b_sign_alt , + din(22) => ex2_a_valid , + din(23) => ex2_c_valid , + din(24) => ex2_b_valid , + din(25) => ex2_prod_zero , + din(26) => ex2_b_zero , + din(27) => ex2_rnd_to_int , + din(28) => ex2_sp_conv , + din(29) => ex2_uns , + din(30) => ex2_log2e , + din(31) => ex2_pow2e , + din(32) => ex2_ovf_unf_dis , + din(33) => ex2_nj_deno , + ------------------- + dout( 0) => ex3_fsel , + dout( 1) => ex3_from_integer , + dout( 2) => ex3_to_integer , + dout( 3) => ex3_math , + dout( 4) => ex3_est_recip , + dout( 5) => ex3_est_rsqrt , + dout( 6) => ex3_move , + dout( 7) => ex3_compare , + dout( 8) => ex3_prenorm , + dout( 9) => ex3_frsp , + dout(10) => ex3_mv_to_scr , + dout(11) => ex3_mv_from_scr , + dout(12) => ex3_div_beg , + dout(13) => ex3_sqrt_beg , + dout(14) => ex3_sp , + dout(15) => ex3_word , + dout(16) => ex3_sub_op , + dout(17) => ex3_rnd_dis , + dout(18) => ex3_inv_sign , + dout(19) => ex3_p_sign , + dout(20) => ex3_b_sign_adj , + dout(21) => ex3_b_sign_alt , + dout(22) => ex3_a_valid , + dout(23) => ex3_c_valid , + dout(24) => ex3_b_valid , + dout(25) => ex3_prod_zero , + dout(26) => ex3_b_zero , + dout(27) => ex3_rnd_to_int , + dout(28) => ex3_sp_conv , + dout(29) => ex3_uns , + dout(30) => ex3_log2e , + dout(31) => ex3_pow2e , + dout(32) => ex3_ovf_unf_dis , + dout(33) => ex3_nj_deno ); + + ex3_nj_deno_x <= ex3_nj_deno and not ex3_ue ; + + ex3_byp_prod_nz <= ( ex3_math and + not ex3_b_zero and -- math,b=z cancells byp + not ex3_prod_zero and + (ex3_a_valid or ex3_c_valid) and + ex3_sel_byp ); + + ex3_byp_prod_nz_sub <= ( ex3_math and + ex3_effsub_eac and + not ex3_b_zero and -- math,b=z cancells byp + not ex3_prod_zero and + (ex3_a_valid or ex3_c_valid) and + ex3_sel_byp ); + + + ex2_uc_g_ig <= (f_mad_ex2_uc_a_expo_den and not ex2_ue ) or + (f_mad_ex2_uc_a_expo_den_sp and not ex2_ue and ex2_sp ) ; + + ex2_effsub_eac <= not f_alg_ex2_effsub_eac_b ; + + ex3_flg_lat: tri_rlmreg_p generic map (width=> 47, expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + forcee => forcee,--tidn, + delay_lclkr => delay_lclkr(3), --tidn, + mpw1_b => mpw1_b(3) ,--tidn, + mpw2_b => mpw2_b(0), --tidn, + nclk => nclk, + act => ex2_act, + thold_b => thold_0_b, + sg => sg_0, + scout => ex3_flg_so, + scin => ex3_flg_si , + ------------------- + din( 0) => ex2_vxsnan ,--exceptions + din( 1) => ex2_vxvc , + din( 2) => ex2_vxcvi , + din( 3) => ex2_vxzdz , + din( 4) => ex2_vxidi , + din( 5) => ex2_vximz , + din( 6) => ex2_vxisi , + din( 7) => ex2_vxsqrt , + din( 8) => ex2_zx , + din( 9) => ex2_gen_nan , --sel_k + din(10) => ex2_gen_inf , + din(11) => ex2_gen_max , + din(12) => ex2_gen_zero , + din(13) => ex2_spec_sign ,--sign special + din(14) => ex2_quiet , + din(15) => ex2_is_nan ,--compares + din(16) => ex2_is_eq , + din(17) => ex2_is_gt , + din(18) => ex2_is_lt , + din(19) => ex2_cmp_sgnneg , + din(20) => ex2_cmp_sgnpos , + din(21) => ex2_wd_ov_x , --f_eie_ex2_wd_ov ,-- flags from toInt exponent + din(22) => ex2_dw_ov_x , --f_eie_ex2_dw_ov , + din(23) => f_eie_ex2_wd_ov_if , + din(24) => f_eie_ex2_dw_ov_if , + din(25) => ex2_to_int_uns_neg , + din(26) => f_alg_ex2_sel_byp , + din(27) => ex2_effsub_eac , + din(28) => f_alg_ex2_sh_unf , + din(29) => f_alg_ex2_sh_ovf , + din(30) => ex2_pass_nan , + din(31) => ex2_bf_10000 , + din(32) => f_eie_ex2_lt_bias , + din(33) => f_eie_ex2_eq_bias_m1 , + din(34) => ex2_gen_one , + din(35) => ex2_rnd_fpscr(0) , + din(36) => ex2_rnd_fpscr(1) , + din(37) => ex2_div_sign , + din(38) => ex2_uc_ft_pos , + din(39) => ex2_uc_ft_neg , + din(40) => f_dcd_ex2_uc_inc_lsb , + din(41) => f_dcd_ex2_uc_guard , + din(42) => f_dcd_ex2_uc_sticky , + din(43) => f_dcd_ex2_uc_gs_v , + din(44) => ex2_uc_g_ig , + din(45) => ex2_uc_mid , + din(46) => ex2_uc_end_spec , + ------------------- + dout( 0) => ex3_vxsnan ,--exceptions + dout( 1) => ex3_vxvc , + dout( 2) => ex3_vxcvi , + dout( 3) => ex3_vxzdz , + dout( 4) => ex3_vxidi , + dout( 5) => ex3_vximz , + dout( 6) => ex3_vxisi , + dout( 7) => ex3_vxsqrt , + dout( 8) => ex3_zx , + dout( 9) => ex3_gen_nan , --sel_k + dout(10) => ex3_gen_inf , + dout(11) => ex3_gen_max , + dout(12) => ex3_gen_zero , + dout(13) => ex3_spec_sign ,--sign special + dout(14) => ex3_quiet , + dout(15) => ex3_is_nan ,--compares + dout(16) => ex3_is_eq , + dout(17) => ex3_is_gt , + dout(18) => ex3_is_lt , + dout(19) => ex3_cmp_sgnneg , + dout(20) => ex3_cmp_sgnpos , + dout(21) => ex3_wd_ov ,-- flags from toInt exponent + dout(22) => ex3_dw_ov , + dout(23) => ex3_wd_ov_if , + dout(24) => ex3_dw_ov_if , + dout(25) => ex3_to_int_uns_neg , + dout(26) => ex3_sel_byp , + dout(27) => ex3_effsub_eac , + dout(28) => ex3_sh_unf , + dout(29) => ex3_sh_ovf , + dout(30) => ex3_pass_nan , + dout(31) => ex3_bf_10000 , + dout(32) => ex3_lt_bias , + dout(33) => ex3_eq_bias_m1 , + dout(34) => ex3_gen_one , + dout(35) => ex3_rnd_fpscr(0) , + dout(36) => ex3_rnd_fpscr(1) , + dout(37) => ex3_div_sign , + dout(38) => ex3_uc_ft_pos , + dout(39) => ex3_uc_ft_neg , + dout(40) => ex3_uc_inc_lsb , + dout(41) => ex3_uc_guard , + dout(42) => ex3_uc_sticky , + dout(43) => ex3_uc_gs_v , + dout(44) => ex3_uc_g_ig , + dout(45) => ex3_uc_mid , + dout(46) => ex3_uc_end_spec ); + + + f_mad_ex3_uc_round_mode(0 to 1) <= ex3_rnd_fpscr(0 to 1); --output-- + f_mad_ex3_uc_res_sign <= ex3_div_sign ;--output-- + f_mad_ex3_uc_zx <= ex3_zx and not ex3_pass_nan ;--output-- + f_mad_ex3_uc_special <= ex3_pass_nan or --output-- + ex3_gen_nan or + ex3_gen_zero or + ex3_gen_inf ; + + f_mad_ex3_uc_vxidi <= ex3_vxidi ;--output-- + f_mad_ex3_uc_vxzdz <= ex3_vxzdz ;--output-- + f_mad_ex3_uc_vxsqrt <= ex3_vxsqrt ;--output-- + f_mad_ex3_uc_vxsnan <= ex3_vxsnan ;--output-- + + f_pic_ex3_cmp_sgnneg <= ex3_cmp_sgnneg; --output-- + f_pic_ex3_cmp_sgnpos <= ex3_cmp_sgnpos; --output-- + f_pic_ex3_is_eq <= ex3_is_eq ; --output-- + f_pic_ex3_is_gt <= ex3_is_gt ; --output-- + f_pic_ex3_is_lt <= ex3_is_lt ; --output-- + f_pic_ex3_is_nan <= ex3_is_nan ; --output-- + + f_pic_ex3_sel_est <= ex3_est_recip or ex3_est_rsqrt; --output-- + f_pic_ex3_sp_b <= not ex3_sp ; --output-- + + + +--//################################################################ +--//# ex3 logic +--//################################################################ + + --//##----------------------------------------- + --//## mutex selects for specials + --//##----------------------------------------- + + + ex3_gen_rnd2int <= ex3_rnd_to_int and ex3_lt_bias ; + ex3_gen_one_rnd2int <= ex3_gen_rnd2int and ex3_rnd2int_up ; + ex3_gen_zer_rnd2int <= ex3_gen_rnd2int and not ex3_rnd2int_up ; + + + ex3_rnd2int_up <= + (not ex3_rnd0 and not ex3_rnd1 and ex3_eq_bias_m1 and not ex3_b_zero ) or + ( ex3_rnd0 and not ex3_rnd1 and not ex3_b_sign_alt and not ex3_b_zero ) or --pos_inf --f_alg_ex3_int_fi and **1 + ( ex3_rnd0 and ex3_rnd1 and ex3_b_sign_alt and not ex3_b_zero ); --neg_inf --f_alg_ex3_int_fi and **1 + +-- **1 rnd_rnd to int spec does not block round up becuase b is zero. i think that may be a mistake. + + + + ex3_gen_nan_mutex <= ex3_gen_nan and not ex3_pass_nan ; + ex3_gen_inf_mutex <= ex3_gen_inf and not ex3_pass_nan and not ex3_gen_nan ; + ex3_gen_max_mutex <= ex3_gen_inf and not ex3_pass_nan and not ex3_gen_nan and not ex3_gen_inf; + ex3_gen_zer_mutex <= (ex3_gen_zero or ex3_gen_zer_rnd2int) and not ex3_pass_nan and not ex3_gen_nan and not ex3_gen_one_rnd2int; + ex3_gen_one_mutex <= (ex3_gen_one or ex3_gen_one_rnd2int) and not ex3_pass_nan and not ex3_gen_nan ; + + + + + + ex3_word_to <= ex3_word and ex3_to_integer; + ex3_to_int_wd <= ex3_to_integer and ex3_word and not ex3_rnd_to_int; + ex3_to_int_dw <= ex3_to_integer and not ex3_word and not ex3_rnd_to_int; + ex3_to_int_ov <= + ( ex3_to_int_wd and ex3_wd_ov ) or -- definitely overflowed (includes unsigned) + ( ex3_to_int_dw and ex3_dw_ov ) or -- definitely overflowed (includes unsigned) + ( ex3_to_int_wd and ex3_wd_ov_if and not ex3_b_sign_alt and not ex3_uns ) or -- definitely overflowed (excludes unsigned) + ( ex3_to_int_dw and ex3_dw_ov_if and not ex3_b_sign_alt and not ex3_uns ) or -- definitely overflowed (excludes unsigned) + ( ex3_to_int_wd and ex3_wd_ov_if and ex3_b_sign_alt and not(ex3_bf_10000 and not f_alg_ex3_int_fr) and not ex3_uns ) or -- definitely overflowed + ( ex3_to_int_dw and ex3_dw_ov_if and ex3_b_sign_alt and not(ex3_bf_10000 and not f_alg_ex3_int_fr) and not ex3_uns ) ; -- definitely overflowed + + ex3_to_int_ov_if <= ex3_to_integer and not ex3_b_sign_alt; -- -- to_int positive + + + ex3_spec_sel_e <= + ex3_gen_rnd2int or + ex3_pass_nan or + ex3_gen_nan or + ex3_gen_inf or + ex3_gen_zero or + ex3_mv_from_scr ; + + ex3_spec_sel_f <= + (ex3_gen_rnd2int and not ex3_pass_nan) or + (ex3_gen_nan and not ex3_pass_nan) or + (ex3_gen_inf and not ex3_pass_nan) or + (ex3_gen_zero and not ex3_pass_nan) ; + + + ex3_ov_en <= (ex3_math or ex3_frsp or ex3_est_recip) and not ex3_ovf_unf_dis ; + ex3_uf_en <= ex3_ov_en ; + + ex3_oe_x <= ex3_oe and ex3_ov_en; + ex3_ue_x <= ex3_ue and ex3_uf_en; + + ex3_ovf_en_oe0 <= ex3_ov_en and not ex3_oe ; + ex3_ovf_en_oe1 <= ex3_ov_en and ex3_oe ; + ex3_unf_en_oe0 <= ex3_uf_en and not ex3_ue ; + ex3_unf_en_oe1 <= ex3_uf_en and ex3_ue ; + + + --//##----------------------------------------- + --//## sign logic + --//##----------------------------------------- + -- multiply always uses p_sign (already replicated) + + ex3_spec_sign_sel <= ex3_spec_sel_e or + ex3_prenorm or + ex3_fsel or + ex3_mv_from_scr or + ex3_rnd_to_int or + ex3_log2e or-- log2e/pow2e regular sign merged in later + ex3_pow2e or + ex3_uc_ft_pos or + ex3_uc_ft_neg; + + ex3_p_sign_may <= ex3_math and ex3_effsub_eac ; + + ex3_spec_sign_x <= (ex3_spec_sign and not ex3_uc_ft_pos) or ex3_uc_ft_neg; + + + ex3_sign_pco <= -- favors p-sign + ( ex3_spec_sign_sel and ex3_spec_sign_x ) or + ( not ex3_spec_sign_sel and ex3_b_sign_alt and not ex3_p_sign_may ) or + ( not ex3_spec_sign_sel and ex3_p_sign and ex3_p_sign_may and not (ex3_prod_zero and ex3_math) ) or + ( not ex3_spec_sign_sel and ex3_b_sign_alt and ex3_p_sign_may and (ex3_prod_zero and ex3_math) ); + + ex3_sign_nco <= -- favors b-sign + ( ex3_spec_sign_sel and ex3_spec_sign_x ) or + ( not ex3_spec_sign_sel and ex3_b_sign_alt and not(ex3_b_zero and ex3_math) ) or + ( not ex3_spec_sign_sel and ex3_p_sign and (ex3_b_zero and ex3_math) ); + + +--//################################################################ +--//# ex4 latches +--//################################################################ + + + + ex4_scr_lat: tri_rlmreg_p generic map (width=> 8, expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + forcee => forcee, --tidn, + delay_lclkr => delay_lclkr(4), --tidn, + mpw1_b => mpw1_b(4) ,--tidn, + mpw2_b => mpw2_b(0) ,--tidn, + nclk => nclk, + act => ex3_act, + thold_b => thold_0_b, + sg => sg_0, + scout => ex4_scr_so , + scin => ex4_scr_si , + ------------------- + din(0) => ex3_ve , + din(1) => ex3_oe_x , + din(2) => ex3_ue_x , + din(3) => ex3_ze , + din(4) => ex3_xe , + din(5) => ex3_nonieee , + din(6) => ex3_rnd0 , + din(7) => ex3_rnd1 , + ------------------- + dout(0) => ex4_ve , + dout(1) => ex4_oe , + dout(2) => ex4_ue , + dout(3) => ex4_ze , + dout(4) => ex4_xe , + dout(5) => ex4_nonieee , + dout(6) => ex4_rnd0 , + dout(7) => ex4_rnd1 ); + + ex3_sp_x <= ex3_sp or ex3_sp_conv ; + + ex4_ctl_lat: tri_rlmreg_p generic map (width=> 29, expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + forcee => forcee, --tidn, + delay_lclkr => delay_lclkr(4), --tidn, + mpw1_b => mpw1_b(4) ,--tidn, + mpw2_b => mpw2_b(0) ,--tidn, + nclk => nclk, + act => ex3_act, + thold_b => thold_0_b, + sg => sg_0, + scout => ex4_ctl_so , + scin => ex4_ctl_si , + ------------------- + din( 0) => ex3_fsel , + din( 1) => ex3_from_integer , + din( 2) => ex3_to_integer , + din( 3) => ex3_math , + din( 4) => ex3_est_recip , + din( 5) => ex3_est_rsqrt , + din( 6) => ex3_move , + din( 7) => ex3_compare , + din( 8) => ex3_prenorm , + din( 9) => ex3_frsp , + din(10) => ex3_mv_to_scr , + din(11) => ex3_mv_from_scr , + din(12) => ex3_div_beg , + din(13) => ex3_sqrt_beg , + din(14) => ex3_sp_x , + din(15) => ex3_word_to , + din(16) => ex3_sub_op , + din(17) => ex3_rnd_dis , + din(18) => ex3_inv_sign , + din(19) => ex3_sign_pco , + din(20) => ex3_sign_nco , + din(21) => ex3_byp_prod_nz , + din(22) => ex3_effsub_eac , + din(23) => ex3_rnd_to_int , + din(24) => ex3_uns , + din(25) => ex3_log2e , + din(26) => ex3_pow2e , + din(27) => ex3_ovf_unf_dis , + din(28) => ex3_nj_deno_x , + ------------------- + dout( 0) => ex4_fsel , + dout( 1) => ex4_from_integer , + dout( 2) => ex4_to_integer , + dout( 3) => ex4_math , + dout( 4) => ex4_est_recip , + dout( 5) => ex4_est_rsqrt , + dout( 6) => ex4_move , + dout( 7) => ex4_compare , + dout( 8) => ex4_prenorm , + dout( 9) => ex4_frsp , + dout(10) => ex4_mv_to_scr , + dout(11) => ex4_mv_from_scr , + dout(12) => ex4_div_beg , + dout(13) => ex4_sqrt_beg , + dout(14) => ex4_sp , + dout(15) => ex4_word , + dout(16) => ex4_sub_op , + dout(17) => ex4_rnd_dis , + dout(18) => ex4_inv_sign , + dout(19) => ex4_sign_pco , + dout(20) => ex4_sign_nco , + dout(21) => ex4_byp_prod_nz , + dout(22) => ex4_effsub_eac , + dout(23) => ex4_rnd_to_int , + dout(24) => ex4_uns , + dout(25) => ex4_log2e , + dout(26) => ex4_pow2e , + dout(27) => ex4_ovf_unf_dis , + dout(28) => ex4_nj_deno ); + + + f_pic_ex4_byp_prod_nz <= ex4_byp_prod_nz ; + + + ex4_flg_lat: tri_rlmreg_p generic map (width=> 38, expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + forcee => forcee, --tidn, + delay_lclkr => delay_lclkr(4), --tidn, + mpw1_b => mpw1_b(4) ,--tidn, + mpw2_b => mpw2_b(0) ,--tidn, + nclk => nclk, + act => ex3_act, + thold_b => thold_0_b, + sg => sg_0, + scout => ex4_flg_so , + scin => ex4_flg_si , + ------------------- + din( 0) => ex3_vxsnan ,--exceptions + din( 1) => ex3_vxvc , + din( 2) => ex3_vxcvi , + din( 3) => ex3_vxzdz , + din( 4) => ex3_vxidi , + din( 5) => ex3_vximz , + din( 6) => ex3_vxisi , + din( 7) => ex3_vxsqrt , + din( 8) => ex3_zx , + din( 9) => ex3_gen_nan_mutex , --sel_k + din(10) => ex3_gen_inf_mutex , + din(11) => ex3_gen_max_mutex , + din(12) => ex3_gen_zer_mutex , + din(13) => ex3_gen_one_mutex , + din(14) => ex3_quiet , + din(15) => ex3_to_int_wd ,-- flags from toInt exponent + din(16) => ex3_to_int_dw , + din(17) => ex3_to_int_ov , + din(18) => ex3_to_int_ov_if , + din(19) => ex3_to_int_uns_neg , + din(20) => ex3_spec_sel_e , + din(21) => ex3_spec_sel_f , + din(22) => ex3_ov_en , + din(23) => ex3_uf_en , + din(24) => ex3_ovf_en_oe0, + din(25) => ex3_ovf_en_oe1, + din(26) => ex3_unf_en_oe0, + din(27) => ex3_unf_en_oe1, + din(28) => ex3_pass_nan , + din(29) => f_alg_ex3_int_fr , + din(30) => f_alg_ex3_int_fi , + din(31) => ex3_uc_inc_lsb , + din(32) => ex3_uc_guard , + din(33) => ex3_uc_sticky , + din(34) => ex3_uc_gs_v , + din(35) => ex3_uc_g_ig , + din(36) => ex3_uc_mid , + din(37) => ex3_uc_end_spec , + ------------------- + dout( 0) => ex4_vxsnan ,--exceptions + dout( 1) => ex4_vxvc , + dout( 2) => ex4_vxcvi , + dout( 3) => ex4_vxzdz , + dout( 4) => ex4_vxidi , + dout( 5) => ex4_vximz , + dout( 6) => ex4_vxisi , + dout( 7) => ex4_vxsqrt , + dout( 8) => ex4_zx , + dout( 9) => ex4_gen_nan , --sel_k + dout(10) => ex4_gen_inf , + dout(11) => ex4_gen_max , + dout(12) => ex4_gen_zero , + dout(13) => ex4_gen_one , + dout(14) => ex4_quiet , + dout(15) => ex4_to_int_wd ,-- flags from toInt exponent + dout(16) => ex4_to_int_dw , + dout(17) => ex4_to_int_ov , + dout(18) => ex4_to_int_ov_if , + dout(19) => ex4_to_int_uns_neg , + dout(20) => ex4_spec_sel_e , + dout(21) => ex4_spec_sel_f , + dout(22) => ex4_ov_en , + dout(23) => ex4_uf_en , + dout(24) => ex4_ovf_en_oe0 , + dout(25) => ex4_ovf_en_oe1 , + dout(26) => ex4_unf_en_oe0 , + dout(27) => ex4_unf_en_oe1 , + dout(28) => ex4_pass_nan , + dout(29) => ex4_int_fr , + dout(30) => ex4_int_fi , + dout(31) => ex4_uc_inc_lsb , + dout(32) => ex4_uc_guard , + dout(33) => ex4_uc_sticky , + dout(34) => ex4_uc_gs_v , + dout(35) => ex4_uc_g_ig , + dout(36) => ex4_uc_mid , + dout(37) => ex4_uc_end_spec ); + + + ex4_to_int_ov_all_x <= + ( ex4_to_int_ov ) or + ( f_add_ex4_to_int_ovf_wd(0) and ex4_to_int_wd and ex4_uns and not ex4_to_int_uns_neg ) or + ( f_add_ex4_to_int_ovf_dw(0) and ex4_to_int_dw and ex4_uns and not ex4_to_int_uns_neg ) or + ( f_add_ex4_to_int_ovf_wd(1) and ex4_to_int_wd and not ex4_uns and ex4_to_int_ov_if ) or + ( f_add_ex4_to_int_ovf_dw(1) and ex4_to_int_dw and not ex4_uns and ex4_to_int_ov_if ) ; + + ex4_to_int_ov_all <= + ex4_to_int_uns_neg or -- may not set vxcvi ... but the result will be zero + ex4_to_int_ov_all_x ; + + + + -- only set flag if dont successfuly round to zero + -- adder bit [99] was not flipped for the negate, + -- so it is the carry-out ... "0" co means negative + ex4_vxcvi_ov <= ex4_vxcvi or + ex4_to_int_ov_all_x or + (ex4_to_int_uns_neg and not f_add_ex4_to_int_ovf_dw(0) and ex4_to_int_dw) or + (ex4_to_int_uns_neg and not f_add_ex4_to_int_ovf_dw(0) and ex4_to_int_wd) ; + + + ex4_fr_spec <= ( ex4_int_fr and ex4_to_integer and not ex4_rnd_to_int and not ex4_vxcvi_ov ); + ex4_fi_spec <= ( ex4_int_fi and ex4_to_integer and not ex4_rnd_to_int and not ex4_vxcvi_ov ); + + ex4_sel_est <= (ex4_est_recip or ex4_est_rsqrt) and + not (ex4_pass_nan ); + + f_pic_ex4_quiet_b <= not ex4_quiet ;--output-- + f_pic_ex4_sp_b <= not ex4_sp ;--output-- + f_pic_ex4_sel_est_b <= not ex4_sel_est ;--output-- + + f_pic_ex4_to_int_ov_all <= ex4_to_int_ov_all ;--output-- + + f_pic_ex4_to_integer_b <= not( ex4_to_integer and not ex4_rnd_to_int ) ;--output-- + f_pic_ex4_word_b <= not ex4_word ;--output-- + f_pic_ex4_uns_b <= not ex4_uns ;--output-- + + f_pic_ex4_spec_sel_k_e <= ex4_spec_sel_e ;--output-- + f_pic_ex4_spec_sel_k_f <= ex4_spec_sel_f ;--output-- + + f_pic_ex4_sel_fpscr_b <= not ex4_mv_from_scr ;--output-- + f_pic_ex4_spec_inf_b <= not ex4_gen_inf ;--output-- + + + f_pic_ex4_oe <= ex4_oe ;--output-- + f_pic_ex4_ue <= ex4_ue ;--output-- + f_pic_ex4_ov_en <= ex4_ov_en and not ex4_spec_sel_e ;--output-- + f_pic_ex4_uf_en <= ex4_uf_en and not ex4_spec_sel_e ;--output-- + f_pic_ex4_ovf_en_oe0_b <= not ex4_ovf_en_oe0 ;--output-- + f_pic_ex4_unf_en_ue0_b <= not ex4_unf_en_oe0 ;--output-- + + f_pic_ex4_ovf_en_oe1_b <= not( ex4_ovf_en_oe1 and not ex4_uc_mid );--output-- + f_pic_ex4_unf_en_ue1_b <= not( ex4_unf_en_oe1 and not ex4_uc_mid );--output-- + +--//################################################################ +--//# ex4 logic +--//################################################################ + -- fmr/fneg/fabs/fnabs + -- fsel + -- mffs + -- mcrfs, mtcrf, mtfs* + -- prenorm_sp prenorm_dp + -- fcomp + -- fmul fadd fsub fmadd fmsub fnmsub fnmadd + -- fres,frsqrte + -- frsp + + ex4_rnd_nr <= not ex4_rnd0 and not ex4_rnd1; + ex4_rnd_zr <= not ex4_rnd0 and ex4_rnd1; + ex4_rnd_pi <= ex4_rnd0 and not ex4_rnd1; + ex4_rnd_ni <= ex4_rnd0 and ex4_rnd1; + + ex4_rnd_en <= not ex4_rnd_dis and + not ex4_sel_spec_e and + ( ex4_math or ex4_frsp or ex4_from_integer); + ex4_rnd_inf_ok <= ( ex4_rnd_en and ex4_rnd_pi and not ex4_round_sign ) or + ( ex4_rnd_en and ex4_rnd_ni and ex4_round_sign ) ; + ex4_rnd_nr_ok <= ex4_rnd_en and ex4_rnd_nr ; + f_pic_ex4_rnd_inf_ok_b <= not ex4_rnd_inf_ok ;--output-- + f_pic_ex4_rnd_ni_b <= not ex4_rnd_ni ;--output-- + f_pic_ex4_rnd_nr_b <= not ex4_rnd_nr_ok ;--output-- + + +---------------------------- + + ex4_uc_g_v <= ex4_uc_gs_v and not ex4_uc_g_ig ; + ex4_uc_s_v <= ex4_uc_gs_v ; + + f_pic_ex4_nj_deno <= ex4_nj_deno ;--output-- + f_pic_ex5_uc_inc_lsb <= ex5_uc_inc_lsb ;--output-- + f_pic_ex5_uc_guard <= ex5_uc_guard ;--output-- + f_pic_ex5_uc_sticky <= ex5_uc_sticky ;--output-- + f_pic_ex5_uc_g_v <= ex5_uc_g_v ;--output-- + f_pic_ex5_uc_s_v <= ex5_uc_s_v ;--output-- +---------------------------- + + ex4_vx <= ex4_vxsnan or + ex4_vxisi or + ex4_vxidi or + ex4_vxzdz or + ex4_vximz or + ex4_vxvc or + ex4_vxsqrt or + ex4_vxcvi_ov ; + + ex4_upd_fpscr_ops <= + ( ex4_math and not ex4_uc_mid ) or -- microcode only changes fpscr on last iteration + ex4_est_recip or + ex4_est_rsqrt or + ex4_to_integer or + ex4_from_integer or + ex4_frsp or + ex4_rnd_to_int or + ex4_compare ; + + + ex4_scr_upd_pipe <= ex4_upd_fpscr_ops and not ex4_ovf_unf_dis; + ex4_scr_upd_move <= ex4_mv_to_scr ; + + + ex4_fpr_wr_dis <= -- does not include include iu cancel + (ex4_fprf_hold ) ; + + + + ex4_sel_spec_e <= + ex4_gen_one or + ex4_pass_nan or + ex4_gen_nan or + ex4_gen_inf or + ex4_gen_zero ; + + ex4_sel_spec_f <= + ex4_gen_one or + ex4_gen_nan or + ex4_gen_inf or + ex4_gen_zero ; + + ex4_sel_spec_fr <= + ex4_gen_one or + ex4_sel_spec_e or + ex4_est_recip or + ex4_est_rsqrt or + ex4_rnd_to_int ; + +--$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$ +--$$ the spec has changed , overflow for to_ineger should now set fr_pipe_v fr=00 +--$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$ + + ex4_ox_pipe_v <= not ex4_sel_spec_e and not ex4_compare and not ex4_to_integer and not ex4_from_integer and not ex4_rnd_to_int and not ex4_uc_end_spec; + ex4_fr_pipe_v <= not ex4_sel_spec_fr and not ex4_compare and not ex4_to_integer and not ex4_rnd_to_int and not ex4_uc_end_spec; + + + ex4_fprf_pipe_v <= not ex4_sel_spec_e and not ex4_compare and not( ex4_to_integer and not ex4_rnd_to_int) and not ex4_fprf_hold; + + ex4_fprf_hold_ops <= ex4_to_integer or + ex4_frsp or + ex4_rnd_to_int or + (ex4_math and not ex4_uc_mid) or + (ex4_est_recip and not ex4_uc_mid) or + (ex4_est_rsqrt and not ex4_uc_mid) ; + + ex4_fprf_hold <= + (ex4_ve and ex4_vx and ex4_fprf_hold_ops ) or + (ex4_ze and ex4_zx and ex4_fprf_hold_ops ); + + -- FPRF + -- 1 0 0 0 1 QNAN [0] qnan | den | (sign*zero) + -- 0 1 0 0 1 -INF [1] sign * !zero + -- 0 1 0 0 0 -norm [2] !sign * !zero * !qnan + -- 1 1 0 0 0 -den [3] zero + -- 1 0 0 1 0 -zero [4] inf | qnan + -- 0 0 0 1 0 +zero + -- 1 0 1 0 0 +den + -- 0 0 1 0 0 +norm + -- 0 0 1 0 1 +inf + -- + -- ex4_pass_nan 10001 @ + -- ex4_gen_nan 10001 @ + -- ex4_gen_inf (-) 01001 + -- ex4_gen_inf (+) 00101 + -- ex4_gen_zero (-) 10010 @ + -- ex4_gen_zero (+) 00010 @ + -- ex4_gen_one (+) 00100 +norm + -- ex4_gen_one (-) 01000 -norm + + ex4_gen_inf_sign <= ex4_round_sign xor (ex4_inv_sign and not ex4_pass_nan and not ex4_gen_nan) ; + + + --[0] nan, -zer, -den, +den ... (spec does not create den) + ex4_fprf_spec_x(0) <= + ex4_pass_nan or + ex4_gen_nan or + ( ex4_gen_zero and (ex4_math and ex4_effsub_eac) and (ex4_rnd_ni xor ex4_inv_sign) ) or + ( ex4_gen_zero and not(ex4_math and ex4_effsub_eac) and (ex4_round_sign xor ex4_inv_sign) ); + + ex4_fprf_spec_x(1) <= ( ex4_gen_inf and ex4_gen_inf_sign ) or + ( ex4_gen_one and ex4_round_sign ); + ex4_fprf_spec_x(2) <= ( ex4_gen_inf and not ex4_gen_inf_sign ) or + ( ex4_gen_one and not ex4_round_sign ); + ex4_fprf_spec_x(3) <= ex4_gen_zero ; + ex4_fprf_spec_x(4) <= ex4_pass_nan or ex4_gen_nan or ex4_gen_inf ; + + ex4_fprf_spec(0 to 4) <= + ( (tidn & f_add_ex4_fpcc_iu(0 to 3)) and (0 to 4 => ex4_compare ) ) or + ( ex4_fprf_spec_x(0 to 4) and not (0 to 4 => ex4_to_integer_ken ) and not (0 to 4 => ex4_compare or ex4_fprf_hold) ) ; + + -- selects for constant (pipe and spec) ??? need mayOvf + + -- k depends on the rounding mode (also diff for to intetger) + -- NAN : pipe does not create nan + -- +/- INF frac=0 + -- MAX FP frac=1 + -- MAX +int frac=1 + -- MAX -INT frac=0 + + ex4_may_ovf <= f_eov_ex4_may_ovf; + + ex4_k_max_fp <= + ( ex4_may_ovf and ex4_rnd_zr ) or + ( ex4_may_ovf and ex4_rnd_pi and ex4_round_sign ) or + ( ex4_may_ovf and ex4_rnd_ni and not ex4_round_sign ) ; + + --exponent 1 <= tidn (sign) + --exponent 2 <= tidn (2048) + --exponent 3 <= msb (1024) for inf/nan + --exponent 4 <= sp (512) + --exponent 5 <= sp (256) + --exponent 6 <= sp (128) + --exponent 7 <= mid (64) + --exponent 8 <= mid (64) + --exponent 9 <= mid (32) + --exponent 10 <= mid (16) + --exponent 11 <= mid (8) + --exponent 12 <= mid (4) + --exponent 13 <= lsb (1) + + + ex4_gen_any <= ex4_gen_nan or + ex4_gen_inf or + ex4_gen_zero or + ex4_gen_one ; + + ex4_k_nan <= (ex4_gen_nan or ex4_pass_nan) and not ex4_to_integer_ken ; + + ex4_k_inf <= ( ex4_gen_inf and not ex4_to_integer_ken ) or + ( not ex4_gen_any and not ex4_to_integer_ken and ex4_may_ovf and not ex4_k_max_fp ); + + ex4_k_max <= ( ex4_gen_max and not ex4_to_integer_ken ) or + ( not ex4_gen_any and not ex4_to_integer_ken and ex4_may_ovf and ex4_k_max_fp ); + + ex4_k_zer <= ( ex4_gen_zero and not ex4_to_integer_ken ) or + (not ex4_gen_any and not ex4_to_integer_ken and not ex4_may_ovf ); + + ex4_k_one <= ex4_gen_one ; + + + ex4_to_integer_ken <= ex4_to_integer and not ex4_rnd_to_int ; + + + ex4_k_int_zer <= + (ex4_to_integer_ken and ex4_uns and ex4_gen_zero ) or --uns + (ex4_to_integer_ken and ex4_uns and ex4_gen_nan ) or --uns + (ex4_to_integer_ken and ex4_uns and ex4_sign_nco ) or --uns + (ex4_to_integer_ken and not ex4_uns and ex4_gen_zero ) ; --sgn + + ex4_k_int_maxpos <= + ( ex4_to_integer_ken and ex4_uns and not ex4_gen_zero and not ex4_gen_nan and not ex4_sign_nco ) or --uns + ( ex4_to_integer_ken and not ex4_uns and not ex4_gen_zero and not ex4_gen_nan and not ex4_sign_nco ); --sgn + + ex4_k_int_maxneg <= + ( ex4_to_integer_ken and not ex4_uns and not ex4_gen_zero and ex4_gen_nan ) or --sgn + ( ex4_to_integer_ken and not ex4_uns and not ex4_gen_zero and ex4_sign_nco ); --sgn + + + + + + + + ex4_en_exact_zero <= ex4_math and + ex4_effsub_eac and + not ex4_sel_spec_e ; -- nan_pass, gen_nan, gen_inf, gen_zero + + ex4_invert_sign <= ex4_inv_sign and + not ex4_pass_nan and + not ex4_gen_nan and + not (ex4_gen_zero and ex4_effsub_eac) ; -- (sign-of-exact-zero) + + + ex4_sign_pco_x <= (not (ex4_gen_zero and ex4_math and ex4_effsub_eac) and ex4_sign_pco ) or + ( (ex4_gen_zero and ex4_math and ex4_effsub_eac) and (ex4_rnd_ni xor ex4_inv_sign) ); + ex4_sign_nco_x <= (not (ex4_gen_zero and ex4_math and ex4_effsub_eac) and ex4_sign_nco ) or + ( (ex4_gen_zero and ex4_math and ex4_effsub_eac) and (ex4_rnd_ni xor ex4_inv_sign) ); + + ex4_round_sign <= -- co means a 42, expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + forcee => forcee,--tidn, + delay_lclkr => delay_lclkr(5), --tidn, + mpw1_b => mpw1_b(5), --tidn, + mpw2_b => mpw2_b(1), --tidn, + nclk => nclk, + act => ex4_act, + thold_b => thold_0_b, + sg => sg_0, + scout => ex5_flg_so , + scin => ex5_flg_si , + ------------------- + din( 0) => ex4_zx ,--exceptions + din( 1) => ex4_vxsnan , + din( 2) => ex4_vxisi , + din( 3) => ex4_vxidi , + din( 4) => ex4_vxzdz , + din( 5) => ex4_vximz , + din( 6) => ex4_vxvc , + din( 7) => ex4_vxsqrt , + din( 8) => ex4_vxcvi_ov , + din( 9) => ex4_scr_upd_move ,-- write enables + din(10) => ex4_scr_upd_pipe , + din(11) => ex4_fpr_wr_dis , + din(12) => ex4_ox_pipe_v ,-- select pipe value + din(13) => ex4_fr_pipe_v , + din(14) => ex4_fprf_pipe_v , + din(15 to 19) => ex4_fprf_spec(0 to 4) , -- generate special value + din(20) => ex4_k_nan_x , + din(21) => ex4_k_inf_x , + din(22) => ex4_k_max_x , + din(23) => ex4_k_zer_x , + din(24) => ex4_k_one_x , + din(25) => ex4_k_int_maxpos , + din(26) => ex4_k_int_maxneg , + din(27) => ex4_k_int_zer , + din(28) => ex4_en_exact_zero , -- sign + din(29) => ex4_invert_sign , + + din(30) => ex4_round_sign_x , + + din(31) => tidn , + din(32) => ex4_compare , + din(33) => ex4_frsp , + din(34) => ex4_fr_spec , + din(35) => ex4_fi_spec , + din(36) => ex4_fprf_hold , + din(37) => ex4_uc_inc_lsb , + din(38) => ex4_uc_guard , + din(39) => ex4_uc_sticky , + din(40) => ex4_uc_g_v , + din(41) => ex4_uc_s_v , + ------------------- + dout( 0) => ex5_zx ,--exceptions + dout( 1) => ex5_vxsnan , + dout( 2) => ex5_vxisi , + dout( 3) => ex5_vxidi , + dout( 4) => ex5_vxzdz , + dout( 5) => ex5_vximz , + dout( 6) => ex5_vxvc , + dout( 7) => ex5_vxsqrt , + dout( 8) => ex5_vxcvi , + dout( 9) => ex5_scr_upd_move ,-- write enables + dout(10) => ex5_scr_upd_pipe , + dout(11) => ex5_fpr_wr_dis , + dout(12) => ex5_ox_pipe_v ,-- select pipe values + dout(13) => ex5_fr_pipe_v , + dout(14) => ex5_fprf_pipe_v , + dout(15 to 19) => ex5_fprf_spec(0 to 4) , -- generate special value + dout(20) => ex5_k_nan , + dout(21) => ex5_k_inf , + dout(22) => ex5_k_max , + dout(23) => ex5_k_zer , + dout(24) => ex5_k_one , + dout(25) => ex5_k_int_maxpos , + dout(26) => ex5_k_int_maxneg , + dout(27) => ex5_k_int_zer , + dout(28) => ex5_en_exact_zero , -- sign + dout(29) => ex5_invert_sign , + dout(30) => ex5_round_sign , + dout(31) => ex5_unused , + dout(32) => ex5_compare , + dout(33) => ex5_frsp , + dout(34) => ex5_fr_spec , + dout(35) => ex5_fi_spec , + dout(36) => ex5_fprf_hold , + dout(37) => ex5_uc_inc_lsb , + dout(38) => ex5_uc_guard , + dout(39) => ex5_uc_sticky , + dout(40) => ex5_uc_g_v , + dout(41) => ex5_uc_s_v ); + + + f_pic_ex5_frsp <= ex5_frsp ; + +--//################################################################ +--//# ex5 logic +--//################################################################ + + + f_pic_ex5_flag_zx_b <= not ex5_zx ;--output-- [05] + f_pic_ex5_flag_vxsnan_b <= not ex5_vxsnan ;--output-- [07] + f_pic_ex5_flag_vxisi_b <= not ex5_vxisi ;--output-- [08] + f_pic_ex5_flag_vxidi_b <= not ex5_vxidi ;--output-- [09] + f_pic_ex5_flag_vxzdz_b <= not ex5_vxzdz ;--output-- [10] + f_pic_ex5_flag_vximz_b <= not ex5_vximz ;--output-- [11] + f_pic_ex5_flag_vxvc_b <= not ex5_vxvc ;--output-- [12] + f_pic_ex5_flag_vxsqrt_b <= not ex5_vxsqrt ;--output-- [22] + f_pic_ex5_flag_vxcvi_b <= not ex5_vxcvi ;--output-- [23] + + f_pic_ex5_scr_upd_move_b <= not ex5_scr_upd_move ;--output-- + f_pic_ex5_scr_upd_pipe_b <= not ex5_scr_upd_pipe ;--output-- + f_pic_ex5_fpr_wr_dis_b <= not ex5_fpr_wr_dis ;--output-- + f_pic_ex5_compare_b <= not ex5_compare ;--output-- + + f_pic_ex5_ox_pipe_v_b <= not ex5_ox_pipe_v; --output-- [03] + f_pic_ex5_fr_pipe_v_b <= not ex5_fr_pipe_v; --output-- [13] + f_pic_ex5_fprf_pipe_v_b <= not ex5_fprf_pipe_v; --output-- [15:19] + + f_pic_ex5_fprf_spec_b(0 to 4) <= not ex5_fprf_spec(0 to 4); --output-- + + f_pic_ex5_k_nan <= ex5_k_nan ;--output-- + f_pic_ex5_k_inf <= ex5_k_inf ;--output-- + f_pic_ex5_k_max <= ex5_k_max ;--output-- + f_pic_ex5_k_zer <= ex5_k_zer ;--output-- + f_pic_ex5_k_one <= ex5_k_one ;--output-- + f_pic_ex5_k_int_maxpos <= ex5_k_int_maxpos ;--output-- + f_pic_ex5_k_int_maxneg <= ex5_k_int_maxneg ;--output-- + f_pic_ex5_k_int_zer <= ex5_k_int_zer ;--output-- + + f_pic_ex5_en_exact_zero <= ex5_en_exact_zero;--output-- + f_pic_ex5_invert_sign <= ex5_invert_sign; --output-- + f_pic_ex5_round_sign <= ex5_round_sign; --output-- + + ----------------------------------------------------------- + + + f_pic_ex5_fi_pipe_v_b <= not ex5_fr_pipe_v ;--output-- [14] + f_pic_ex5_ux_pipe_v_b <= not ex5_ox_pipe_v ;--output-- [04] + f_pic_ex5_fprf_hold_b <= not ex5_fprf_hold ; --output-- toint | (ve=1*(math|fprsp)*vx) ... not vxvc + f_pic_ex5_fi_spec_b <= not ex5_fi_spec; --output-- + f_pic_ex5_fr_spec_b <= not ex5_fr_spec; --output-- + + + + +--//################################################################ +--//# scan string +--//################################################################ + + + ex1_ctl_si (0 to 42) <= ex1_ctl_so (1 to 42) & f_pic_si ; + ex2_ctl_si (0 to 56) <= ex2_ctl_so (1 to 56) & ex1_ctl_so (0); + ex2_flg_si (0 to 17) <= ex2_flg_so (1 to 17) & ex2_ctl_so (0); + ex3_scr_si (0 to 7) <= ex3_scr_so (1 to 7) & ex2_flg_so (0); + ex3_ctl_si (0 to 33) <= ex3_ctl_so (1 to 33) & ex3_scr_so (0); + ex3_flg_si (0 to 46) <= ex3_flg_so (1 to 46) & ex3_ctl_so (0); + ex4_scr_si (0 to 7) <= ex4_scr_so (1 to 7) & ex3_flg_so (0); + ex4_ctl_si (0 to 28) <= ex4_ctl_so (1 to 28) & ex4_scr_so (0); + ex4_flg_si (0 to 37) <= ex4_flg_so (1 to 37) & ex4_ctl_so (0); + ex5_flg_si (0 to 41) <= ex5_flg_so (1 to 41) & ex4_flg_so (0); + act_si (0 to 20) <= act_so (1 to 20) & ex5_flg_so (0); + f_pic_so <= act_so (0) ; + + +------------------------- + + +end; -- fuq_pic ARCHITECTURE diff --git a/rel/src/vhdl/work/fuq_rnd.vhdl b/rel/src/vhdl/work/fuq_rnd.vhdl new file mode 100644 index 0000000..8d3a2f8 --- /dev/null +++ b/rel/src/vhdl/work/fuq_rnd.vhdl @@ -0,0 +1,1254 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + +entity fuq_rnd is +generic( expand_type : integer := 2 ); -- 0 - ibm tech, 1 - other ); +port( + vdd :inout power_logic; + gnd :inout power_logic; + clkoff_b :in std_ulogic; -- tiup + act_dis :in std_ulogic; -- ??tidn?? + flush :in std_ulogic; -- ??tidn?? + delay_lclkr :in std_ulogic_vector(5 to 6); -- tidn, + mpw1_b :in std_ulogic_vector(5 to 6); -- tidn, + mpw2_b :in std_ulogic_vector(1 to 1); -- tidn, + sg_1 :in std_ulogic; + thold_1 :in std_ulogic; + fpu_enable :in std_ulogic; --dc_act + nclk :in clk_logic; + + f_rnd_si :in std_ulogic ;-- perv + f_rnd_so :out std_ulogic ;-- perv + ex3_act_b :in std_ulogic ;-- act + + f_nrm_ex5_res :in std_ulogic_vector(0 to 52) ; + f_nrm_ex5_int_lsbs :in std_ulogic_vector(1 to 12) ; + f_nrm_ex5_int_sign :in std_ulogic ; + f_nrm_ex5_nrm_sticky_dp :in std_ulogic ; + f_nrm_ex5_nrm_guard_dp :in std_ulogic ; + f_nrm_ex5_nrm_lsb_dp :in std_ulogic ; + f_nrm_ex5_nrm_sticky_sp :in std_ulogic ; + f_nrm_ex5_nrm_guard_sp :in std_ulogic ; + f_nrm_ex5_nrm_lsb_sp :in std_ulogic ; + f_nrm_ex5_exact_zero :in std_ulogic ; + f_tbl_ex5_recip_den :in std_ulogic ; + + f_pic_ex5_invert_sign :in std_ulogic ;--//# nmadd nmsub + f_pic_ex5_en_exact_zero :in std_ulogic ;--//# math, frsp (no specail override) + + + f_pic_ex5_k_nan :in std_ulogic ; + f_pic_ex5_k_inf :in std_ulogic ; + f_pic_ex5_k_max :in std_ulogic ; + f_pic_ex5_k_zer :in std_ulogic ; + f_pic_ex5_k_one :in std_ulogic ; + f_pic_ex5_k_int_maxpos :in std_ulogic ; + f_pic_ex5_k_int_maxneg :in std_ulogic ; + f_pic_ex5_k_int_zer :in std_ulogic ; + + f_pic_ex4_sel_est_b :in std_ulogic ;--//# off for nan_pass + f_tbl_ex5_est_frac :in std_ulogic_vector(0 to 26) ;--//# + + f_pic_ex4_rnd_ni_b :in std_ulogic ;--//# for sign of exact zero + f_pic_ex4_rnd_nr_b :in std_ulogic ;--//# (off for specials) + f_pic_ex4_rnd_inf_ok_b :in std_ulogic ;--//# pi*pos/ ni*pos (off for specials) + f_pic_ex5_uc_inc_lsb :in std_ulogic ;--//# ?? div ?? + f_pic_ex5_uc_guard :in std_ulogic ; + f_pic_ex5_uc_sticky :in std_ulogic ; + f_pic_ex5_uc_g_v :in std_ulogic ; + f_pic_ex5_uc_s_v :in std_ulogic ; + + f_pic_ex4_sel_fpscr_b :in std_ulogic ;--//# + f_pic_ex4_to_integer_b :in std_ulogic ;--//# same for wd/dw + f_pic_ex4_word_b :in std_ulogic ;--//# same for wd/dw + f_pic_ex4_uns_b :in std_ulogic ;--//# same for wd/dw + f_pic_ex4_sp_b :in std_ulogic ;--//# single precision round, output + f_pic_ex4_spec_inf_b :in std_ulogic ;--//# for INF + f_pic_ex4_quiet_b :in std_ulogic ; + f_pic_ex4_nj_deno :in std_ulogic ; + f_pic_ex4_unf_en_ue0_b :in std_ulogic ;--//# for ux (needs tiny) + f_pic_ex4_unf_en_ue1_b :in std_ulogic ;--//# for ux + f_pic_ex4_ovf_en_oe0_b :in std_ulogic ;--//# + f_pic_ex4_ovf_en_oe1_b :in std_ulogic ;--//# + f_pic_ex5_round_sign :in std_ulogic ;--//# includes special sign + f_scr_ex5_fpscr_rd_dat_dfp :in std_ulogic_vector(0 to 3) ;--//# + f_scr_ex5_fpscr_rd_dat :in std_ulogic_vector(0 to 31) ;--//# + + f_eov_ex5_sel_k_f :in std_ulogic ;--//# + f_eov_ex5_sel_k_e :in std_ulogic ;--//# + f_eov_ex5_sel_kif_f :in std_ulogic ;--//# + f_eov_ex5_sel_kif_e :in std_ulogic ;--//# + f_eov_ex5_ovf_expo :in std_ulogic ;--//# for INF,ox + f_eov_ex5_ovf_if_expo :in std_ulogic ;--//# for INF,ox + f_eov_ex5_unf_expo :in std_ulogic ;--//# for ux + f_eov_ex5_expo_p0 :in std_ulogic_vector(1 to 13) ;--//# result exponent + f_eov_ex5_expo_p1 :in std_ulogic_vector(1 to 13) ;--//# result exponent if rnd_up_all1 + f_eov_ex5_expo_p0_ue1oe1 :in std_ulogic_vector(3 to 7) ;--//# + f_eov_ex5_expo_p1_ue1oe1 :in std_ulogic_vector(3 to 7) ;--//# + f_pic_ex5_frsp :in std_ulogic ; + + f_gst_ex5_logexp_v :in std_ulogic; + f_gst_ex5_logexp_sign :in std_ulogic; + f_gst_ex5_logexp_exp :in std_ulogic_vector(1 to 11); + f_gst_ex5_logexp_fract :in std_ulogic_vector(0 to 19); + + f_rnd_ex6_res_sign :out std_ulogic ;--//# dbyp / f_scr + f_rnd_ex6_res_expo :out std_ulogic_vector(1 to 13) ;--//# dbyp + f_rnd_ex6_res_frac :out std_ulogic_vector(0 to 52) ;--//# dbyp + + f_rnd_ex6_flag_up :out std_ulogic ;--//# f_scr + f_rnd_ex6_flag_fi :out std_ulogic ;--//# f_scr + f_rnd_ex6_flag_ox :out std_ulogic ;--//# f_scr + f_rnd_ex6_flag_den :out std_ulogic ;--//# f_scr + f_rnd_ex6_flag_sgn :out std_ulogic ;--//# f_scr + f_rnd_ex6_flag_inf :out std_ulogic ;--//# f_scr + f_rnd_ex6_flag_zer :out std_ulogic ;--//# f_scr + f_rnd_ex6_flag_ux :out std_ulogic ;--//# f_scr + + f_mad_ex6_uc_sign :out std_ulogic ; + f_mad_ex6_uc_zero :out std_ulogic + +); -- end ports + + + +end fuq_rnd; -- ENTITY + + +architecture fuq_rnd of fuq_rnd is + + constant tiup :std_ulogic := '1'; + constant tidn :std_ulogic := '0'; + + signal sg_0 :std_ulogic ; + signal thold_0_b, thold_0, forcee :std_ulogic ; + signal ex4_act :std_ulogic ; + signal ex3_act :std_ulogic ; + signal ex5_act :std_ulogic ; + signal act_spare_unused :std_ulogic_vector(0 to 2) ; + signal flag_spare_unused :std_ulogic ; + ------------------- + signal act_so :std_ulogic_vector(0 to 4) ;--SCAN + signal act_si :std_ulogic_vector(0 to 4) ;--SCAN + signal ex5_ctl_so :std_ulogic_vector(0 to 15) ;--SCAN + signal ex5_ctl_si :std_ulogic_vector(0 to 15) ;--SCAN + signal ex6_frac_so :std_ulogic_vector(0 to 52) ;--SCAN + signal ex6_frac_si :std_ulogic_vector(0 to 52) ;--SCAN + signal ex6_expo_so :std_ulogic_vector(0 to 13) ;--SCAN + signal ex6_expo_si :std_ulogic_vector(0 to 13) ;--SCAN + signal ex6_flag_so :std_ulogic_vector(0 to 9) ;--SCAN + signal ex6_flag_si :std_ulogic_vector(0 to 9) ;--SCAN + ------------------- + signal ex5_quiet :std_ulogic ; + signal ex5_rnd_ni :std_ulogic ; + signal ex5_rnd_nr :std_ulogic ; + signal ex5_rnd_inf_ok :std_ulogic ; + signal ex5_rnd_frc_up :std_ulogic ; + signal ex5_sel_fpscr :std_ulogic ; + signal ex5_to_integer :std_ulogic ; + signal ex5_word :std_ulogic ; + signal ex5_sp :std_ulogic ; + signal ex5_spec_inf :std_ulogic ; + ------------------- + signal ex5_flag_den :std_ulogic ; + signal ex5_flag_inf :std_ulogic ; + signal ex5_flag_zer :std_ulogic ; + signal ex5_flag_ux :std_ulogic ; + signal ex5_flag_up :std_ulogic ; + signal ex5_flag_fi :std_ulogic ; + signal ex5_flag_ox :std_ulogic ; + signal ex5_all0_lo :std_ulogic ; + signal ex5_all0_sp :std_ulogic ; + signal ex5_all0 :std_ulogic ; + signal ex5_all1 :std_ulogic ; + signal ex5_frac_c :std_ulogic_vector(0 to 52) ; + signal ex5_frac_p1 :std_ulogic_vector(0 to 52) ; + signal ex5_frac_p0 :std_ulogic_vector(0 to 52) ; + signal ex5_frac_px :std_ulogic_vector(0 to 52) ; + signal ex5_frac_k :std_ulogic_vector(0 to 52) ; + signal ex5_frac_misc :std_ulogic_vector(0 to 52); + signal ex5_to_int_data :std_ulogic_vector(0 to 63); + signal ex5_to_int_imp :std_ulogic ; + signal ex5_p0_sel_dflt :std_ulogic ; + + signal ex5_up :std_ulogic ; + signal ex5_up_sp :std_ulogic ; + signal ex5_up_dp :std_ulogic ; + signal ex5_res_frac :std_ulogic_vector(0 to 52) ; + ------------------- + signal ex5_res_sign :std_ulogic ; + signal ex5_res_expo :std_ulogic_vector(1 to 13) ; + signal ex6_res_frac :std_ulogic_vector(0 to 52) ; + signal ex6_res_sign :std_ulogic ; + signal ex6_res_expo :std_ulogic_vector(1 to 13) ; + signal ex6_flag_sgn :std_ulogic ; + signal ex6_flag_den :std_ulogic ; + signal ex6_flag_inf :std_ulogic ; + signal ex6_flag_zer :std_ulogic ; + signal ex6_flag_ux :std_ulogic ; + signal ex6_flag_up :std_ulogic ; + signal ex6_flag_fi :std_ulogic ; + signal ex6_flag_ox :std_ulogic ; + + signal ex5_sel_up :std_ulogic ; + signal ex5_sel_up_b :std_ulogic ; + signal ex5_sel_up_dp :std_ulogic ; + signal ex5_sel_up_dp_b :std_ulogic ; + signal ex5_gox :std_ulogic ; + + signal ex5_sgn_result_fp :std_ulogic; + signal ex5_res_sign_prez :std_ulogic; + signal ex5_exact_sgn_rst :std_ulogic; + signal ex5_exact_sgn_set :std_ulogic; + signal ex5_res_sel_k_f :std_ulogic; + signal ex5_res_sel_p1_e :std_ulogic; + signal ex5_res_clip_e :std_ulogic; + signal ex5_expo_sel_k :std_ulogic; + signal ex5_expo_sel_k_both :std_ulogic; + signal ex5_expo_p0_sel_k :std_ulogic; + signal ex5_expo_p0_sel_int :std_ulogic; + signal ex5_expo_p0_sel_gst :std_ulogic; + signal ex5_expo_p0_sel_dflt :std_ulogic; + signal ex5_expo_p1_sel_k :std_ulogic; + signal ex5_expo_p1_sel_dflt :std_ulogic; + signal ex5_sel_p0_joke :std_ulogic; + signal ex5_sel_p1_joke :std_ulogic; + signal ex5_expo_k :std_ulogic_vector(1 to 13); + signal ex5_expo_p0k :std_ulogic_vector(1 to 13); + signal ex5_expo_p1k :std_ulogic_vector(1 to 13); + signal ex5_expo_p0kx :std_ulogic_vector(1 to 13); + signal ex5_expo_p1kx :std_ulogic_vector(1 to 13); + signal ex5_unf_en_ue0 :std_ulogic; + signal ex5_unf_en_ue1 :std_ulogic; + signal ex5_ovf_en_oe0 :std_ulogic; + signal ex5_ovf_en_oe1 :std_ulogic; + signal ex5_ov_oe0 :std_ulogic; + signal ex5_k_zero :std_ulogic; + signal ex5_sel_est :std_ulogic; + signal ex5_k_inf_nan_maxdp :std_ulogic; + signal ex5_k_inf_nan_max :std_ulogic; + signal ex5_k_inf_nan_zer :std_ulogic; + signal ex5_k_zer_sp :std_ulogic; + signal ex5_k_notzer :std_ulogic; + signal ex5_k_max_intmax_nan :std_ulogic; + signal ex5_k_max_intmax :std_ulogic; + signal ex5_k_max_intsgn :std_ulogic; + signal ex5_k_max_intmax_nsp :std_ulogic; + signal ex5_pwr4_spec_frsp :std_ulogic; + signal ex5_exact_zero_rnd :std_ulogic; + signal ex5_rnd_ni_adj :std_ulogic; + signal ex5_nrm_res_b :std_ulogic_vector(0 to 52); + signal ex5_all0_gp2 :std_ulogic_vector(0 to 27); + signal ex5_all0_gp4 :std_ulogic_vector(0 to 13); + signal ex5_all0_gp8 :std_ulogic_vector(0 to 6); + signal ex5_all0_gp16 :std_ulogic_vector(0 to 3); + + signal ex5_frac_c_gp2 :std_ulogic_vector(0 to 52); + signal ex5_frac_c_gp4 :std_ulogic_vector(0 to 52); + signal ex5_frac_c_gp8 :std_ulogic_vector(0 to 52); + signal ex5_frac_g16 :std_ulogic_vector(0 to 6); + signal ex5_frac_g32 :std_ulogic_vector(0 to 6); + signal ex5_frac_g :std_ulogic_vector(1 to 6); + signal ex4_quiet :std_ulogic; + signal ex4_rnd_ni :std_ulogic; + signal ex4_rnd_nr :std_ulogic; + signal ex4_rnd_inf_ok :std_ulogic; + signal ex4_sel_fpscr :std_ulogic; + signal ex4_to_integer :std_ulogic; + signal ex4_word :std_ulogic; + signal ex4_uns :std_ulogic; + signal ex5_uns :std_ulogic; + signal ex4_sp :std_ulogic; + signal ex4_spec_inf :std_ulogic; + signal ex4_nj_deno :std_ulogic; + signal ex4_unf_en_ue0 :std_ulogic; + signal ex4_unf_en_ue1 :std_ulogic; + signal ex4_ovf_en_oe0 :std_ulogic; + signal ex4_ovf_en_oe1 :std_ulogic; + signal ex4_sel_est :std_ulogic; + signal ex5_guard_dp, ex5_guard_sp, ex5_sticky_dp, ex5_sticky_sp :std_ulogic; + signal unused :std_ulogic; + signal ex5_nj_deno, ex6_nj_deno :std_ulogic; + signal ex5_clip_deno :std_ulogic; + signal ex5_est_log_pow :std_ulogic ; + + +begin + + + unused <= ex5_frac_c(0) or + f_nrm_ex5_int_lsbs(1) ; -- primay input + +--//############################################ +--//# pervasive +--//############################################ + + + thold_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => thold_1, + q(0) => thold_0 ); + + sg_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => sg_1 , + q(0) => sg_0 ); + + + lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map ( + clkoff_b => clkoff_b, + thold => thold_0, + sg => sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => thold_0_b ); + + +--//############################################ +--//# ACT LATCHES +--//############################################ + + ex3_act <= not ex3_act_b ; + + act_lat: tri_rlmreg_p generic map (width=> 5, expand_type => expand_type, needs_sreset => 0) port map ( + forcee => forcee,--i-- tidn, + delay_lclkr => delay_lclkr(5) ,--i-- tidn, + mpw1_b => mpw1_b(5) ,--i-- tidn, + mpw2_b => mpw2_b(1) ,--i-- tidn, + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => fpu_enable, + scout => act_so , + scin => act_si , + ------------------- + din(0) => act_spare_unused(0), + din(1) => act_spare_unused(1), + din(2) => ex3_act, + din(3) => ex4_act, + din(4) => act_spare_unused(2), + ------------------- + dout(0) => act_spare_unused(0), + dout(1) => act_spare_unused(1), + dout(2) => ex4_act, + dout(3) => ex5_act, + dout(4) => act_spare_unused(2) ); + + +--//############################################## +--//# EX5 latch inputs from ex4 +--//############################################## + + ex4_quiet <= not f_pic_ex4_quiet_b ; + ex4_rnd_ni <= not f_pic_ex4_rnd_ni_b ; + ex4_rnd_nr <= not f_pic_ex4_rnd_nr_b ; + ex4_rnd_inf_ok <= not f_pic_ex4_rnd_inf_ok_b ; + ex4_sel_fpscr <= not f_pic_ex4_sel_fpscr_b ; + ex4_to_integer <= not f_pic_ex4_to_integer_b ; + ex4_word <= not f_pic_ex4_word_b ; + ex4_uns <= not f_pic_ex4_uns_b ; + ex4_sp <= not f_pic_ex4_sp_b ; + ex4_spec_inf <= not f_pic_ex4_spec_inf_b ; + ex4_nj_deno <= f_pic_ex4_nj_deno ; + ex4_unf_en_ue0 <= not f_pic_ex4_unf_en_ue0_b ; + ex4_unf_en_ue1 <= not f_pic_ex4_unf_en_ue1_b ; + ex4_ovf_en_oe0 <= not f_pic_ex4_ovf_en_oe0_b ; + ex4_ovf_en_oe1 <= not f_pic_ex4_ovf_en_oe1_b ; + ex4_sel_est <= not f_pic_ex4_sel_est_b ; + + + ex5_ctl_lat: tri_rlmreg_p generic map (width=> 16, expand_type => expand_type, needs_sreset => 0) port map ( + forcee => forcee,--i-- tidn, + delay_lclkr => delay_lclkr(5) ,--i-- tidn, + mpw1_b => mpw1_b(5) ,--i-- tidn, + mpw2_b => mpw2_b(1) ,--i-- tidn, + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => ex4_act, + scout => ex5_ctl_so , + scin => ex5_ctl_si , + ------------------- + din( 0) => ex4_quiet ,--//# for too int only + din( 1) => ex4_rnd_ni ,--//# for sign of exact zero + din( 2) => ex4_rnd_nr ,--//# (off for specials) + din( 3) => ex4_rnd_inf_ok ,--//# pi*pos/ ni*pos (off for specials) + din( 4) => ex4_sel_fpscr ,--//# + din( 5) => ex4_to_integer ,--//# same for wd/dw + din( 6) => ex4_word ,--//# single precision round, output + din( 7) => ex4_sp ,--//# single precision round, output + din( 8) => ex4_spec_inf ,--//# for INF + din( 9) => ex4_nj_deno , + din(10) => ex4_unf_en_ue0 , + din(11) => ex4_unf_en_ue1 , + din(12) => ex4_ovf_en_oe0 , + din(13) => ex4_ovf_en_oe1 , + din(14) => ex4_sel_est , + din(15) => ex4_uns , + ------------------- + dout( 0) => ex5_quiet ,--LAT--//# for too int only + dout( 1) => ex5_rnd_ni ,--LAT--//# for sign of exact zero + dout( 2) => ex5_rnd_nr ,--LAT--//# (off for specials) + dout( 3) => ex5_rnd_inf_ok ,--LAT--//# pi*pos/ ni*pos (off for specials) + dout( 4) => ex5_sel_fpscr ,--LAT--//# + dout( 5) => ex5_to_integer ,--LAT--//# same for wd/dw + dout( 6) => ex5_word ,--LAT--//# word + dout( 7) => ex5_sp ,--LAT--//# single precision round, output + dout( 8) => ex5_spec_inf ,--LAT--//# for INF + dout( 9) => ex5_nj_deno ,--LAT--//# for INF + dout(10) => ex5_unf_en_ue0 , + dout(11) => ex5_unf_en_ue1 , + dout(12) => ex5_ovf_en_oe0 , + dout(13) => ex5_ovf_en_oe1 , + dout(14) => ex5_sel_est , + dout(15) => ex5_uns ); + + ex5_rnd_frc_up <= f_pic_ex5_uc_inc_lsb ; + + +--//############################################## +--//# EX5 logic +--//############################################## + + --//##------------------------------------------- + --//## round up decision + --//##------------------------------------------- + + + ex5_guard_dp <= ( f_nrm_ex5_nrm_guard_dp and not f_pic_ex5_uc_g_v ) or + ( f_pic_ex5_uc_guard and f_pic_ex5_uc_g_v ) ; + + ex5_guard_sp <= ( f_nrm_ex5_nrm_guard_sp and not f_pic_ex5_uc_g_v ) or + ( f_pic_ex5_uc_guard and f_pic_ex5_uc_g_v ) ; + + ex5_sticky_dp <= ( f_nrm_ex5_nrm_sticky_dp ) or + ( f_pic_ex5_uc_sticky and f_pic_ex5_uc_s_v ) ; + + ex5_sticky_sp <= ( f_nrm_ex5_nrm_sticky_sp ) or + ( f_pic_ex5_uc_sticky and f_pic_ex5_uc_s_v ) ; + + + + ex5_up_sp <= + ( ex5_rnd_frc_up ) or -- may need for divide + ( ex5_rnd_nr and ex5_guard_sp and ex5_sticky_sp ) or + ( ex5_rnd_nr and ex5_guard_sp and f_nrm_ex5_nrm_lsb_sp ) or + ( ex5_rnd_inf_ok and ex5_guard_sp ) or + ( ex5_rnd_inf_ok and ex5_sticky_sp ) ; + + ex5_up_dp <= + ( ex5_rnd_frc_up ) or -- may need for divide + ( ex5_rnd_nr and ex5_guard_dp and ex5_sticky_dp ) or + ( ex5_rnd_nr and ex5_guard_dp and f_nrm_ex5_nrm_lsb_dp ) or + ( ex5_rnd_inf_ok and ex5_guard_dp ) or + ( ex5_rnd_inf_ok and ex5_sticky_dp ) ; + + ex5_up <= + (ex5_up_sp and ex5_sp) or + (ex5_up_dp and not ex5_sp); + + ex5_sel_up <= ex5_up; + ex5_sel_up_b <= not ex5_up; + ex5_sel_up_dp <= ex5_up_dp and not ex5_sp; + ex5_sel_up_dp_b <= not ex5_up_dp and not ex5_sp; + + ex5_gox <= + ( ex5_sp and ex5_guard_sp ) or + ( ex5_sp and ex5_sticky_sp ) or + (not ex5_sp and ex5_guard_dp ) or + (not ex5_sp and ex5_sticky_dp ) ; + + --//##------------------------------------------- + --//## conditional increment of round result + --//##------------------------------------------- + + ex5_nrm_res_b(0 to 52) <= not f_nrm_ex5_res(0 to 52); + + ex5_all0_gp2( 0) <= ex5_nrm_res_b( 0) and ex5_nrm_res_b( 1); + ex5_all0_gp2( 1) <= ex5_nrm_res_b( 2) and ex5_nrm_res_b( 3); + ex5_all0_gp2( 2) <= ex5_nrm_res_b( 4) and ex5_nrm_res_b( 5); + ex5_all0_gp2( 3) <= ex5_nrm_res_b( 6) and ex5_nrm_res_b( 7); + ex5_all0_gp2( 4) <= ex5_nrm_res_b( 8) and ex5_nrm_res_b( 9); + ex5_all0_gp2( 5) <= ex5_nrm_res_b(10) and ex5_nrm_res_b(11); + ex5_all0_gp2( 6) <= ex5_nrm_res_b(12) and ex5_nrm_res_b(13); + ex5_all0_gp2( 7) <= ex5_nrm_res_b(14) and ex5_nrm_res_b(15); + ex5_all0_gp2( 8) <= ex5_nrm_res_b(16) and ex5_nrm_res_b(17); + ex5_all0_gp2( 9) <= ex5_nrm_res_b(18) and ex5_nrm_res_b(19); + ex5_all0_gp2(10) <= ex5_nrm_res_b(20) and ex5_nrm_res_b(21); + ex5_all0_gp2(11) <= ex5_nrm_res_b(22) and ex5_nrm_res_b(23); + ex5_all0_gp2(12) <= ex5_nrm_res_b(24) and ex5_nrm_res_b(25); + ex5_all0_gp2(13) <= ex5_nrm_res_b(26) and ex5_nrm_res_b(27); + ex5_all0_gp2(14) <= ex5_nrm_res_b(28) and ex5_nrm_res_b(29); + ex5_all0_gp2(15) <= ex5_nrm_res_b(30) and ex5_nrm_res_b(31); + ex5_all0_gp2(16) <= ex5_nrm_res_b(32) and ex5_nrm_res_b(33); + ex5_all0_gp2(17) <= ex5_nrm_res_b(34) and ex5_nrm_res_b(35); + ex5_all0_gp2(18) <= ex5_nrm_res_b(36) and ex5_nrm_res_b(37); + ex5_all0_gp2(19) <= ex5_nrm_res_b(38) and ex5_nrm_res_b(39); + ex5_all0_gp2(20) <= ex5_nrm_res_b(40) and ex5_nrm_res_b(41); + ex5_all0_gp2(21) <= ex5_nrm_res_b(40) and ex5_nrm_res_b(41); + ex5_all0_gp2(22) <= ex5_nrm_res_b(42) and ex5_nrm_res_b(43); + ex5_all0_gp2(23) <= ex5_nrm_res_b(44) and ex5_nrm_res_b(45); + ex5_all0_gp2(24) <= ex5_nrm_res_b(46) and ex5_nrm_res_b(47); + ex5_all0_gp2(25) <= ex5_nrm_res_b(48) and ex5_nrm_res_b(49); + ex5_all0_gp2(26) <= ex5_nrm_res_b(50) and ex5_nrm_res_b(51); + ex5_all0_gp2(27) <= ex5_nrm_res_b(52) ; + + ex5_all0_gp4( 0) <= ex5_all0_gp2( 0) and ex5_all0_gp2( 1); + ex5_all0_gp4( 1) <= ex5_all0_gp2( 2) and ex5_all0_gp2( 3); + ex5_all0_gp4( 2) <= ex5_all0_gp2( 4) and ex5_all0_gp2( 5); + ex5_all0_gp4( 3) <= ex5_all0_gp2( 6) and ex5_all0_gp2( 7); + ex5_all0_gp4( 4) <= ex5_all0_gp2( 8) and ex5_all0_gp2( 9); + ex5_all0_gp4( 5) <= ex5_all0_gp2(10) and ex5_all0_gp2(11); + ex5_all0_gp4( 6) <= ex5_all0_gp2(12) and ex5_all0_gp2(13); + ex5_all0_gp4( 7) <= ex5_all0_gp2(14) and ex5_all0_gp2(15); + ex5_all0_gp4( 8) <= ex5_all0_gp2(16) and ex5_all0_gp2(17); + ex5_all0_gp4( 9) <= ex5_all0_gp2(18) and ex5_all0_gp2(19); + ex5_all0_gp4(10) <= ex5_all0_gp2(20) and ex5_all0_gp2(21); + ex5_all0_gp4(11) <= ex5_all0_gp2(22) and ex5_all0_gp2(23); + ex5_all0_gp4(12) <= ex5_all0_gp2(24) and ex5_all0_gp2(25); + ex5_all0_gp4(13) <= ex5_all0_gp2(26) and ex5_all0_gp2(27); + + ex5_all0_gp8( 0) <= ex5_all0_gp4( 0) and ex5_all0_gp4( 1); + ex5_all0_gp8( 1) <= ex5_all0_gp4( 2) and ex5_all0_gp4( 3); + ex5_all0_gp8( 2) <= ex5_all0_gp4( 4) and ex5_all0_gp4( 5); + ex5_all0_gp8( 3) <= ex5_all0_gp4( 6) and ex5_all0_gp4( 7); + ex5_all0_gp8( 4) <= ex5_all0_gp4( 8) and ex5_all0_gp4( 9); + ex5_all0_gp8( 5) <= ex5_all0_gp4(10) and ex5_all0_gp4(11); + ex5_all0_gp8( 6) <= ex5_all0_gp4(12) and ex5_all0_gp4(13); + + + ex5_all0_gp16( 0) <= ex5_all0_gp8( 0) and ex5_all0_gp8( 1); + ex5_all0_gp16( 1) <= ex5_all0_gp8( 2) ; + ex5_all0_gp16( 2) <= ex5_all0_gp8( 3) and ex5_all0_gp8( 4); + ex5_all0_gp16( 3) <= ex5_all0_gp8( 5) and ex5_all0_gp8( 6); + + ex5_all0_sp <= ex5_all0_gp16( 0) and ex5_all0_gp16( 1); + ex5_all0_lo <= ex5_all0_gp16( 2) and ex5_all0_gp16( 3); + + + ex5_all0 <= ex5_all0_sp and (ex5_sp or ex5_all0_lo ); + + + + + ex5_frac_c_gp2( 0) <= f_nrm_ex5_res( 0) and f_nrm_ex5_res( 1); + ex5_frac_c_gp2( 1) <= f_nrm_ex5_res( 1) and f_nrm_ex5_res( 2); + ex5_frac_c_gp2( 2) <= f_nrm_ex5_res( 2) and f_nrm_ex5_res( 3); + ex5_frac_c_gp2( 3) <= f_nrm_ex5_res( 3) and f_nrm_ex5_res( 4); + ex5_frac_c_gp2( 4) <= f_nrm_ex5_res( 4) and f_nrm_ex5_res( 5); + ex5_frac_c_gp2( 5) <= f_nrm_ex5_res( 5) and f_nrm_ex5_res( 6); + ex5_frac_c_gp2( 6) <= f_nrm_ex5_res( 6) and f_nrm_ex5_res( 7); + ex5_frac_c_gp2( 7) <= f_nrm_ex5_res( 7) ; + ex5_frac_c_gp2( 8) <= f_nrm_ex5_res( 8) and f_nrm_ex5_res( 9); + ex5_frac_c_gp2( 9) <= f_nrm_ex5_res( 9) and f_nrm_ex5_res(10); + ex5_frac_c_gp2(10) <= f_nrm_ex5_res(10) and f_nrm_ex5_res(11); + ex5_frac_c_gp2(11) <= f_nrm_ex5_res(11) and f_nrm_ex5_res(12); + ex5_frac_c_gp2(12) <= f_nrm_ex5_res(12) and f_nrm_ex5_res(13); + ex5_frac_c_gp2(13) <= f_nrm_ex5_res(13) and f_nrm_ex5_res(14); + ex5_frac_c_gp2(14) <= f_nrm_ex5_res(14) and f_nrm_ex5_res(15); + ex5_frac_c_gp2(15) <= f_nrm_ex5_res(15) ; + ex5_frac_c_gp2(16) <= f_nrm_ex5_res(16) and f_nrm_ex5_res(17); + ex5_frac_c_gp2(17) <= f_nrm_ex5_res(17) and f_nrm_ex5_res(18); + ex5_frac_c_gp2(18) <= f_nrm_ex5_res(18) and f_nrm_ex5_res(19); + ex5_frac_c_gp2(19) <= f_nrm_ex5_res(19) and f_nrm_ex5_res(20); + ex5_frac_c_gp2(20) <= f_nrm_ex5_res(20) and f_nrm_ex5_res(21); + ex5_frac_c_gp2(21) <= f_nrm_ex5_res(21) and f_nrm_ex5_res(22); + ex5_frac_c_gp2(22) <= f_nrm_ex5_res(22) and f_nrm_ex5_res(23); + ex5_frac_c_gp2(23) <= f_nrm_ex5_res(23) ; + ex5_frac_c_gp2(24) <= f_nrm_ex5_res(24) and f_nrm_ex5_res(25); + ex5_frac_c_gp2(25) <= f_nrm_ex5_res(25) and f_nrm_ex5_res(26); + ex5_frac_c_gp2(26) <= f_nrm_ex5_res(26) and f_nrm_ex5_res(27); + ex5_frac_c_gp2(27) <= f_nrm_ex5_res(27) and f_nrm_ex5_res(28); + ex5_frac_c_gp2(28) <= f_nrm_ex5_res(28) and f_nrm_ex5_res(29); + ex5_frac_c_gp2(29) <= f_nrm_ex5_res(29) and f_nrm_ex5_res(30); + ex5_frac_c_gp2(30) <= f_nrm_ex5_res(30) and f_nrm_ex5_res(31); + ex5_frac_c_gp2(31) <= f_nrm_ex5_res(31) ; + ex5_frac_c_gp2(32) <= f_nrm_ex5_res(32) and f_nrm_ex5_res(33); + ex5_frac_c_gp2(33) <= f_nrm_ex5_res(33) and f_nrm_ex5_res(34); + ex5_frac_c_gp2(34) <= f_nrm_ex5_res(34) and f_nrm_ex5_res(35); + ex5_frac_c_gp2(35) <= f_nrm_ex5_res(35) and f_nrm_ex5_res(36); + ex5_frac_c_gp2(36) <= f_nrm_ex5_res(36) and f_nrm_ex5_res(37); + ex5_frac_c_gp2(37) <= f_nrm_ex5_res(37) and f_nrm_ex5_res(38); + ex5_frac_c_gp2(38) <= f_nrm_ex5_res(38) and f_nrm_ex5_res(39); + ex5_frac_c_gp2(39) <= f_nrm_ex5_res(39) ; + ex5_frac_c_gp2(40) <= f_nrm_ex5_res(40) and f_nrm_ex5_res(41); + ex5_frac_c_gp2(41) <= f_nrm_ex5_res(41) and f_nrm_ex5_res(42); + ex5_frac_c_gp2(42) <= f_nrm_ex5_res(42) and f_nrm_ex5_res(43); + ex5_frac_c_gp2(43) <= f_nrm_ex5_res(43) and f_nrm_ex5_res(44); + ex5_frac_c_gp2(44) <= f_nrm_ex5_res(44) and f_nrm_ex5_res(45); + ex5_frac_c_gp2(45) <= f_nrm_ex5_res(45) and f_nrm_ex5_res(46); + ex5_frac_c_gp2(46) <= f_nrm_ex5_res(46) and f_nrm_ex5_res(47); + ex5_frac_c_gp2(47) <= f_nrm_ex5_res(47) ; + ex5_frac_c_gp2(48) <= f_nrm_ex5_res(48) and f_nrm_ex5_res(49); + ex5_frac_c_gp2(49) <= f_nrm_ex5_res(49) and f_nrm_ex5_res(50); + ex5_frac_c_gp2(50) <= f_nrm_ex5_res(50) and f_nrm_ex5_res(51); + ex5_frac_c_gp2(51) <= f_nrm_ex5_res(51) and f_nrm_ex5_res(52); + ex5_frac_c_gp2(52) <= f_nrm_ex5_res(52) ; + + ex5_frac_c_gp4( 0) <= ex5_frac_c_gp2( 0) and ex5_frac_c_gp2( 2); + ex5_frac_c_gp4( 1) <= ex5_frac_c_gp2( 1) and ex5_frac_c_gp2( 3); + ex5_frac_c_gp4( 2) <= ex5_frac_c_gp2( 2) and ex5_frac_c_gp2( 4); + ex5_frac_c_gp4( 3) <= ex5_frac_c_gp2( 3) and ex5_frac_c_gp2( 5); + ex5_frac_c_gp4( 4) <= ex5_frac_c_gp2( 4) and ex5_frac_c_gp2( 6); + ex5_frac_c_gp4( 5) <= ex5_frac_c_gp2( 5) and ex5_frac_c_gp2( 7); + ex5_frac_c_gp4( 6) <= ex5_frac_c_gp2( 6) ; + ex5_frac_c_gp4( 7) <= ex5_frac_c_gp2( 7) ; + ex5_frac_c_gp4( 8) <= ex5_frac_c_gp2( 8) and ex5_frac_c_gp2(10); + ex5_frac_c_gp4( 9) <= ex5_frac_c_gp2( 9) and ex5_frac_c_gp2(11); + ex5_frac_c_gp4(10) <= ex5_frac_c_gp2(10) and ex5_frac_c_gp2(12); + ex5_frac_c_gp4(11) <= ex5_frac_c_gp2(11) and ex5_frac_c_gp2(13); + ex5_frac_c_gp4(12) <= ex5_frac_c_gp2(12) and ex5_frac_c_gp2(14); + ex5_frac_c_gp4(13) <= ex5_frac_c_gp2(13) and ex5_frac_c_gp2(15); + ex5_frac_c_gp4(14) <= ex5_frac_c_gp2(14) ; + ex5_frac_c_gp4(15) <= ex5_frac_c_gp2(15) ; + ex5_frac_c_gp4(16) <= ex5_frac_c_gp2(16) and ex5_frac_c_gp2(18); + ex5_frac_c_gp4(17) <= ex5_frac_c_gp2(17) and ex5_frac_c_gp2(19); + ex5_frac_c_gp4(18) <= ex5_frac_c_gp2(18) and ex5_frac_c_gp2(20); + ex5_frac_c_gp4(19) <= ex5_frac_c_gp2(19) and ex5_frac_c_gp2(21); + ex5_frac_c_gp4(20) <= ex5_frac_c_gp2(20) and ex5_frac_c_gp2(22); + ex5_frac_c_gp4(21) <= ex5_frac_c_gp2(21) and ex5_frac_c_gp2(23); + ex5_frac_c_gp4(22) <= ex5_frac_c_gp2(22) ; + ex5_frac_c_gp4(23) <= ex5_frac_c_gp2(23) ; + ex5_frac_c_gp4(24) <= ex5_frac_c_gp2(24) and ex5_frac_c_gp2(26); + ex5_frac_c_gp4(25) <= ex5_frac_c_gp2(25) and ex5_frac_c_gp2(27); + ex5_frac_c_gp4(26) <= ex5_frac_c_gp2(26) and ex5_frac_c_gp2(28); + ex5_frac_c_gp4(27) <= ex5_frac_c_gp2(27) and ex5_frac_c_gp2(29); + ex5_frac_c_gp4(28) <= ex5_frac_c_gp2(28) and ex5_frac_c_gp2(30); + ex5_frac_c_gp4(29) <= ex5_frac_c_gp2(29) and ex5_frac_c_gp2(31); + ex5_frac_c_gp4(30) <= ex5_frac_c_gp2(30) ; + ex5_frac_c_gp4(31) <= ex5_frac_c_gp2(31) ; + ex5_frac_c_gp4(32) <= ex5_frac_c_gp2(32) and ex5_frac_c_gp2(34); + ex5_frac_c_gp4(33) <= ex5_frac_c_gp2(33) and ex5_frac_c_gp2(35); + ex5_frac_c_gp4(34) <= ex5_frac_c_gp2(34) and ex5_frac_c_gp2(36); + ex5_frac_c_gp4(35) <= ex5_frac_c_gp2(35) and ex5_frac_c_gp2(37); + ex5_frac_c_gp4(36) <= ex5_frac_c_gp2(36) and ex5_frac_c_gp2(38); + ex5_frac_c_gp4(37) <= ex5_frac_c_gp2(37) and ex5_frac_c_gp2(39); + ex5_frac_c_gp4(38) <= ex5_frac_c_gp2(38) ; + ex5_frac_c_gp4(39) <= ex5_frac_c_gp2(39) ; + ex5_frac_c_gp4(40) <= ex5_frac_c_gp2(40) and ex5_frac_c_gp2(42); + ex5_frac_c_gp4(41) <= ex5_frac_c_gp2(41) and ex5_frac_c_gp2(43); + ex5_frac_c_gp4(42) <= ex5_frac_c_gp2(42) and ex5_frac_c_gp2(44); + ex5_frac_c_gp4(43) <= ex5_frac_c_gp2(43) and ex5_frac_c_gp2(45); + ex5_frac_c_gp4(44) <= ex5_frac_c_gp2(44) and ex5_frac_c_gp2(46); + ex5_frac_c_gp4(45) <= ex5_frac_c_gp2(45) and ex5_frac_c_gp2(47); + ex5_frac_c_gp4(46) <= ex5_frac_c_gp2(46) ; + ex5_frac_c_gp4(47) <= ex5_frac_c_gp2(47) ; + ex5_frac_c_gp4(48) <= ex5_frac_c_gp2(48) and ex5_frac_c_gp2(50); + ex5_frac_c_gp4(49) <= ex5_frac_c_gp2(49) and ex5_frac_c_gp2(51); + ex5_frac_c_gp4(50) <= ex5_frac_c_gp2(50) and ex5_frac_c_gp2(52); + ex5_frac_c_gp4(51) <= ex5_frac_c_gp2(51) ; + ex5_frac_c_gp4(52) <= ex5_frac_c_gp2(52) ; + + + ex5_frac_c_gp8( 0) <= ex5_frac_c_gp4( 0) and ex5_frac_c_gp4( 4); + ex5_frac_c_gp8( 1) <= ex5_frac_c_gp4( 1) and ex5_frac_c_gp4( 5); + ex5_frac_c_gp8( 2) <= ex5_frac_c_gp4( 2) and ex5_frac_c_gp4( 6); + ex5_frac_c_gp8( 3) <= ex5_frac_c_gp4( 3) and ex5_frac_c_gp4( 7); + ex5_frac_c_gp8( 4) <= ex5_frac_c_gp4( 4) ; + ex5_frac_c_gp8( 5) <= ex5_frac_c_gp4( 5) ; + ex5_frac_c_gp8( 6) <= ex5_frac_c_gp4( 6) ; + ex5_frac_c_gp8( 7) <= ex5_frac_c_gp4( 7) ; + ex5_frac_c_gp8( 8) <= ex5_frac_c_gp4( 8) and ex5_frac_c_gp4(12); + ex5_frac_c_gp8( 9) <= ex5_frac_c_gp4( 9) and ex5_frac_c_gp4(13); + ex5_frac_c_gp8(10) <= ex5_frac_c_gp4(10) and ex5_frac_c_gp4(14); + ex5_frac_c_gp8(11) <= ex5_frac_c_gp4(11) and ex5_frac_c_gp4(15); + ex5_frac_c_gp8(12) <= ex5_frac_c_gp4(12) ; + ex5_frac_c_gp8(13) <= ex5_frac_c_gp4(13) ; + ex5_frac_c_gp8(14) <= ex5_frac_c_gp4(14) ; + ex5_frac_c_gp8(15) <= ex5_frac_c_gp4(15) ; + ex5_frac_c_gp8(16) <= ex5_frac_c_gp4(16) and ex5_frac_c_gp4(20); + ex5_frac_c_gp8(17) <= ex5_frac_c_gp4(17) and ex5_frac_c_gp4(21); + ex5_frac_c_gp8(18) <= ex5_frac_c_gp4(18) and ex5_frac_c_gp4(22); + ex5_frac_c_gp8(19) <= ex5_frac_c_gp4(19) and ex5_frac_c_gp4(23); + ex5_frac_c_gp8(20) <= ex5_frac_c_gp4(20) ; + ex5_frac_c_gp8(21) <= ex5_frac_c_gp4(21) ; + ex5_frac_c_gp8(22) <= ex5_frac_c_gp4(22) ; + ex5_frac_c_gp8(23) <= ex5_frac_c_gp4(23) ; + ex5_frac_c_gp8(24) <= ex5_frac_c_gp4(24) and ex5_frac_c_gp4(28); + ex5_frac_c_gp8(25) <= ex5_frac_c_gp4(25) and ex5_frac_c_gp4(29); + ex5_frac_c_gp8(26) <= ex5_frac_c_gp4(26) and ex5_frac_c_gp4(30); + ex5_frac_c_gp8(27) <= ex5_frac_c_gp4(27) and ex5_frac_c_gp4(31); + ex5_frac_c_gp8(28) <= ex5_frac_c_gp4(28) ; + ex5_frac_c_gp8(29) <= ex5_frac_c_gp4(29) ; + ex5_frac_c_gp8(30) <= ex5_frac_c_gp4(30) ; + ex5_frac_c_gp8(31) <= ex5_frac_c_gp4(31) ; + ex5_frac_c_gp8(32) <= ex5_frac_c_gp4(32) and ex5_frac_c_gp4(36); + ex5_frac_c_gp8(33) <= ex5_frac_c_gp4(33) and ex5_frac_c_gp4(37); + ex5_frac_c_gp8(34) <= ex5_frac_c_gp4(34) and ex5_frac_c_gp4(38); + ex5_frac_c_gp8(35) <= ex5_frac_c_gp4(35) and ex5_frac_c_gp4(39); + ex5_frac_c_gp8(36) <= ex5_frac_c_gp4(36) ; + ex5_frac_c_gp8(37) <= ex5_frac_c_gp4(37) ; + ex5_frac_c_gp8(38) <= ex5_frac_c_gp4(38) ; + ex5_frac_c_gp8(39) <= ex5_frac_c_gp4(39) ; + ex5_frac_c_gp8(40) <= ex5_frac_c_gp4(40) and ex5_frac_c_gp4(44); + ex5_frac_c_gp8(41) <= ex5_frac_c_gp4(41) and ex5_frac_c_gp4(45); + ex5_frac_c_gp8(42) <= ex5_frac_c_gp4(42) and ex5_frac_c_gp4(46); + ex5_frac_c_gp8(43) <= ex5_frac_c_gp4(43) and ex5_frac_c_gp4(47); + ex5_frac_c_gp8(44) <= ex5_frac_c_gp4(44) ; + ex5_frac_c_gp8(45) <= ex5_frac_c_gp4(45) ; + ex5_frac_c_gp8(46) <= ex5_frac_c_gp4(46) ; + ex5_frac_c_gp8(47) <= ex5_frac_c_gp4(47) ; + ex5_frac_c_gp8(48) <= ex5_frac_c_gp4(48) and ex5_frac_c_gp4(52); + ex5_frac_c_gp8(49) <= ex5_frac_c_gp4(49) ; + ex5_frac_c_gp8(50) <= ex5_frac_c_gp4(50) ; + ex5_frac_c_gp8(51) <= ex5_frac_c_gp4(51) ; + ex5_frac_c_gp8(52) <= ex5_frac_c_gp4(52) ; + + ex5_frac_c( 0 to 7) <= ex5_frac_c_gp8( 0 to 7) and ( 0 to 7 => ex5_frac_g( 1) ); + ex5_frac_c( 8 to 15) <= ex5_frac_c_gp8( 8 to 15) and ( 8 to 15 => ex5_frac_g( 2) ); + ex5_frac_c(16 to 23) <= ex5_frac_c_gp8(16 to 23) and (16 to 23 => ex5_frac_g( 3) ); + ex5_frac_c(24) <= (ex5_frac_c_gp8(24) and ex5_frac_g( 4) ) or ex5_sp ; + ex5_frac_c(25 to 31) <= ex5_frac_c_gp8(25 to 31) and (25 to 31 => ex5_frac_g( 4) ); + ex5_frac_c(32 to 39) <= ex5_frac_c_gp8(32 to 39) and (32 to 39 => ex5_frac_g( 5) ); + ex5_frac_c(40 to 47) <= ex5_frac_c_gp8(40 to 47) and (40 to 47 => ex5_frac_g( 6) ); + ex5_frac_c(48 to 52) <= ex5_frac_c_gp8(48 to 52) ; + + + ex5_frac_g16(0) <= ex5_frac_c_gp8( 0) and ex5_frac_c_gp8( 8); + ex5_frac_g16(1) <= ex5_frac_c_gp8( 8) and ex5_frac_c_gp8(16); + ex5_frac_g16(2) <= ex5_frac_c_gp8(16) ; + ex5_frac_g16(3) <= ex5_frac_c_gp8(24) and ex5_frac_c_gp8(32) ; + ex5_frac_g16(4) <= ex5_frac_c_gp8(32) and ex5_frac_c_gp8(40) ; + ex5_frac_g16(5) <= ex5_frac_c_gp8(40) and ex5_frac_c_gp8(48) ; + ex5_frac_g16(6) <= ex5_frac_c_gp8(48) ; + + ex5_frac_g32(0) <= ex5_frac_g16(0) and ex5_frac_g16(2); + ex5_frac_g32(1) <= ex5_frac_g16(1) ; + ex5_frac_g32(2) <= ex5_frac_g16(2) ; + ex5_frac_g32(3) <= ex5_frac_g16(3) and ex5_frac_g16(5); + ex5_frac_g32(4) <= ex5_frac_g16(4) and ex5_frac_g16(6); + ex5_frac_g32(5) <= ex5_frac_g16(5) ; + ex5_frac_g32(6) <= ex5_frac_g16(6) ; + + ex5_all1 <= ex5_frac_g32(0) and (ex5_sp or ex5_frac_g32(3) ); + ex5_frac_g(1) <= ex5_frac_g32(1) and (ex5_sp or ex5_frac_g32(3) ); + ex5_frac_g(2) <= ex5_frac_g32(2) and (ex5_sp or ex5_frac_g32(3) ); + ex5_frac_g(3) <= ex5_frac_g32(3) or ex5_sp ; + ex5_frac_g(4) <= ex5_frac_g32(4) ; + ex5_frac_g(5) <= ex5_frac_g32(5) ; + ex5_frac_g(6) <= ex5_frac_g32(6) ; + + + ex5_frac_p1(0) <= f_nrm_ex5_res(0) or ex5_frac_c(1); -- roll over does not go to zero + ex5_frac_p1(1 to 51) <= f_nrm_ex5_res(1 to 51) xor ex5_frac_c(2 to 52); + ex5_frac_p1(52) <= not f_nrm_ex5_res(52); + + --//##------------------------------------------- + --//## final selection muxing fraction + --//##------------------------------------------- + + + ex5_to_int_data( 0) <= f_nrm_ex5_int_sign ; ---and not ex5_word ; --sign + ex5_to_int_data( 1 to 10) <= f_nrm_ex5_res( 1 to 10) or ( 1 to 10 => ex5_word) ; --expo + ex5_to_int_data( 11) <= f_nrm_ex5_res(11) or not ex5_to_int_imp or ex5_word ; --expo + ex5_to_int_imp <= -- or together what will be the fraction bits + f_nrm_ex5_res(1) or + f_nrm_ex5_res(2) or + f_nrm_ex5_res(3) or + f_nrm_ex5_res(4) or + f_nrm_ex5_res(5) or + f_nrm_ex5_res(6) or + f_nrm_ex5_res(7) or + f_nrm_ex5_res(8) or + f_nrm_ex5_res(9) or + f_nrm_ex5_res(10) or + f_nrm_ex5_res(11) or + ex5_word ; + ex5_to_int_data(12) <= f_nrm_ex5_res(12) or ex5_word ; --frac start (no implicit) + ex5_to_int_data(13 to 31) <= f_nrm_ex5_res(13 to 31) and (13 to 31 => not ex5_word) ; --frac start (no implicit) + ex5_to_int_data(32 to 52) <= f_nrm_ex5_res(32 to 52) ; + ex5_to_int_data(53 to 63) <= f_nrm_ex5_int_lsbs(2 to 12) ; + + + + ex5_p0_sel_dflt <= not ex5_to_integer and + not ex5_sel_est and + not f_gst_ex5_logexp_v and + not ex5_sel_fpscr ; + + ex5_frac_misc( 0) <= ( ex5_sel_est and f_tbl_ex5_est_frac(0) ) or + ( f_gst_ex5_logexp_v and f_gst_ex5_logexp_fract(0) ) ; + + + ex5_frac_misc( 1 to 16) <= ( ( 1 to 16 => ex5_sel_est ) and f_tbl_ex5_est_frac(1 to 16) ) or + ( ( 1 to 16 => f_gst_ex5_logexp_v) and f_gst_ex5_logexp_fract(1 to 16) ); + + ex5_frac_misc(17 to 19) <= ( (17 to 19 => ex5_sel_est ) and f_tbl_ex5_est_frac(17 to 19) ) or + ( (17 to 19 => ex5_sel_fpscr) and f_scr_ex5_fpscr_rd_dat_dfp(0 to 2) ) or + ( (17 to 19 => f_gst_ex5_logexp_v) and f_gst_ex5_logexp_fract(17 to 19) ); + + ex5_frac_misc( 20) <= ( ( ex5_sel_est ) and f_tbl_ex5_est_frac(20) ) or + ( ( ex5_sel_fpscr) and f_scr_ex5_fpscr_rd_dat_dfp(3) ) ; + + + ex5_frac_misc(21 to 26) <= ( (21 to 26 => ex5_sel_est ) and f_tbl_ex5_est_frac(21 to 26) ) or + ( (21 to 26 => ex5_sel_fpscr) and f_scr_ex5_fpscr_rd_dat(0 to 5) ) ; + ex5_frac_misc(27 to 52) <= (27 to 52 => ex5_sel_fpscr) and f_scr_ex5_fpscr_rd_dat(6 to 31); + + + ex5_frac_p0(0) <= -- toInteger never rounds up + ( ex5_p0_sel_dflt and f_nrm_ex5_res(0) ) or + ( ex5_to_integer and ex5_to_int_imp ) or + ( ex5_frac_misc(0) ) ; + ex5_frac_p0(1) <= -- toInteger never rounds up + ( ex5_p0_sel_dflt and f_nrm_ex5_res(1) ) or + ( ex5_to_integer and ex5_to_int_data(12) ) or + ( ex5_frac_misc(1) ) or + ( ex5_quiet ) ; + ex5_frac_p0(2 to 19) <= -- toInteger never rounds up + ( (2 to 19 => ex5_p0_sel_dflt) and f_nrm_ex5_res( 2 to 19) ) or + ( (2 to 19 => ex5_to_integer ) and ex5_to_int_data(13 to 30) ) or + ( ex5_frac_misc(2 to 19) ) ; + ex5_frac_p0(20 to 52) <= -- toInteger never rounds up + ( (20 to 52 => ex5_p0_sel_dflt) and f_nrm_ex5_res( 20 to 52) ) or + ( (20 to 52 => ex5_to_integer ) and ex5_to_int_data(31 to 63) ) or + ( ex5_frac_misc(20 to 52) ) ; + + + ex5_frac_px(0 to 23) <= + ( (0 to 23 => ex5_sel_up_b) and ex5_frac_p0(0 to 23) ) or + ( (0 to 23 => ex5_sel_up ) and ex5_frac_p1(0 to 23) ) ; + ex5_frac_px(24 to 52) <= + ( (24 to 52 => ex5_sel_up_dp_b) and ex5_frac_p0(24 to 52) ) or + ( (24 to 52 => ex5_sel_up_dp ) and ex5_frac_p1(24 to 52) ) ; + + -- int 32:63 => frac 21:52 [21] is the integer sign bit + + + ex5_frac_k(0) <= ex5_k_notzer or ex5_word ; -- implicit bit + ex5_frac_k(1) <= ex5_k_max_intmax_nan or ex5_word; + ex5_frac_k( 2 to 20) <= ( 2 to 20 => ex5_k_max_intmax and not ex5_word ); + ex5_frac_k(21) <= ex5_k_max_intsgn ; -- sign of int word + ex5_frac_k(22) <= ex5_k_max_intmax ; + ex5_frac_k(23) <= ex5_k_max_intmax ; + ex5_frac_k(24 to 52) <= (24 to 52 => ex5_k_max_intmax_nsp ); + + ex5_k_notzer <= not (f_pic_ex5_k_zer or f_pic_ex5_k_int_zer or f_pic_ex5_k_int_maxneg ); + ex5_k_max_intmax_nan <= f_pic_ex5_k_max or f_pic_ex5_k_int_maxpos or f_pic_ex5_k_nan ; + ex5_k_max_intmax <= f_pic_ex5_k_max or f_pic_ex5_k_int_maxpos ; + ex5_k_max_intmax_nsp <= (f_pic_ex5_k_max or f_pic_ex5_k_int_maxpos )and not ex5_sp; + + ex5_k_max_intsgn <= ( f_pic_ex5_k_max ) or -- not to-integer + ( f_pic_ex5_k_int_maxpos and not ex5_word ) or -- dw-to_integer + ( f_pic_ex5_k_int_maxneg and ex5_word and not ex5_uns ) or -- wd-to-integer signed + ( f_pic_ex5_k_int_maxpos and ex5_word and ex5_uns ) ; -- wd-to-integer unsigned + + + + ex5_res_frac(0) <= -- for to integer (impl needs extra logic) + (ex5_frac_k(0) and ex5_res_sel_k_f ) or + (ex5_frac_px(0) and not ex5_res_sel_k_f ) ; + + ex5_res_frac(1 to 52) <= + (ex5_frac_k (1 to 52) and (1 to 52=> ex5_res_sel_k_f) ) or + (ex5_frac_px (1 to 52) and (1 to 52=> not ex5_res_sel_k_f) ) ; + + + --//##------------------------------------------- + --//## final selection muxing exponent + --//##------------------------------------------- + + -- max sp expo 1151 is wrong 1151 =127+1024 0_0100_0111_1111 + -- 1150 0_0100_0111_1110 + + ex5_k_inf_nan_max <= f_pic_ex5_k_nan or + f_pic_ex5_k_inf or + f_pic_ex5_k_max ; + + ex5_k_inf_nan_maxdp <= f_pic_ex5_k_nan or + f_pic_ex5_k_inf or + ( f_pic_ex5_k_max and not ex5_sp) ; + + ex5_k_inf_nan_zer <= f_pic_ex5_k_nan or + f_pic_ex5_k_inf or + f_pic_ex5_k_zer ; + + ex5_k_zer_sp <= f_pic_ex5_k_zer and ex5_sp ; + + + ex5_expo_k( 1) <= tidn ;-- 4096 sign + ex5_expo_k( 2) <= tidn ;-- 2048 + ex5_expo_k( 3) <= ex5_k_inf_nan_max or f_pic_ex5_k_int_maxpos or ex5_word ; -- 1024 + ex5_expo_k( 4) <= ex5_k_inf_nan_maxdp or f_pic_ex5_k_int_maxpos or ex5_k_zer_sp or ex5_word or f_pic_ex5_k_one ;-- 0512 + ex5_expo_k( 5) <= ex5_k_inf_nan_maxdp or f_pic_ex5_k_int_maxpos or ex5_k_zer_sp or ex5_word or f_pic_ex5_k_one ;-- 0256 + ex5_expo_k( 6) <= ex5_k_inf_nan_maxdp or f_pic_ex5_k_int_maxpos or ex5_k_zer_sp or ex5_word or f_pic_ex5_k_one ;-- 0128 + ex5_expo_k( 7) <= ex5_k_inf_nan_max or f_pic_ex5_k_int_maxpos or ex5_word or f_pic_ex5_k_one ;-- 0064 + ex5_expo_k( 8) <= ex5_k_inf_nan_max or f_pic_ex5_k_int_maxpos or ex5_word or f_pic_ex5_k_one ;-- 0032 + ex5_expo_k( 9) <= ex5_k_inf_nan_max or f_pic_ex5_k_int_maxpos or ex5_word or f_pic_ex5_k_one ;-- 0016 + ex5_expo_k(10) <= ex5_k_inf_nan_max or f_pic_ex5_k_int_maxpos or ex5_word or f_pic_ex5_k_one ;-- 0008 + ex5_expo_k(11) <= ex5_k_inf_nan_max or f_pic_ex5_k_int_maxpos or ex5_word or f_pic_ex5_k_one ;-- 0004 + ex5_expo_k(12) <= ex5_k_inf_nan_max or f_pic_ex5_k_int_maxpos or ex5_word or f_pic_ex5_k_one ;-- 0002 + ex5_expo_k(13) <= ex5_k_inf_nan_zer or f_pic_ex5_k_int_maxpos or ex5_k_zero + or f_pic_ex5_k_int_maxneg or ex5_word or f_pic_ex5_k_one ;-- 0001 + + + ----------- + + ex5_expo_p0k(1 to 13) <= + ( ex5_expo_k(1 to 13) and (1 to 13 => ex5_expo_p0_sel_k ) ) or + ( (tidn & tidn & ex5_to_int_data(1 to 11)) and (1 to 13 => ex5_expo_p0_sel_int ) ) or + ( (tidn & tidn & f_gst_ex5_logexp_exp(1 to 11)) and (1 to 13 => ex5_expo_p0_sel_gst ) ) or + ( ((1 to 12=>tidn) & tiup) and (1 to 13 => ex5_sel_fpscr ) ) or + ( f_eov_ex5_expo_p0(1 to 13) and (1 to 13 => ex5_expo_p0_sel_dflt) ) ; + + ex5_expo_p1k(1 to 13) <= + ( ex5_expo_k (1 to 13) and (1 to 13 => ex5_expo_p1_sel_k ) ) or + ( f_eov_ex5_expo_p1 (1 to 13) and (1 to 13 => ex5_expo_p1_sel_dflt) ) ; + + ------------- + ex5_expo_p0kx(1 to 7) <= + ( ex5_expo_p0k(1 to 7) and (1 to 7 => not ex5_sel_p0_joke) ) or + ( (tidn & tidn & f_eov_ex5_expo_p0_ue1oe1(3 to 7) ) + and (1 to 7 => ex5_sel_p0_joke) ) ; + + ex5_expo_p1kx(1 to 7) <= + ( ex5_expo_p1k(1 to 7) and (1 to 7 => not ex5_sel_p1_joke) ) or + ( (tidn & tidn & f_eov_ex5_expo_p1_ue1oe1(3 to 7) ) + and (1 to 7 => ex5_sel_p1_joke) ) ; + + + ex5_expo_p0kx(8 to 12) <= ex5_expo_p0k(8 to 12); -- joke does not effect these bits + ex5_expo_p1kx(8 to 12) <= ex5_expo_p1k(8 to 12); -- joke does not effect these bits + + -- the silly exceptions enabled logic could wrap around and hit the exponent Zero + -- if it is nonZero: it will normalize + -- overflow + -- DP constant = 1536 overflow = 2047 = 2047 Expo>=2047, subtracting 1536 cannot hit zero + -- SP constant = 192 overflow = 255 + 896 = 1151 Expo>=1151, subtracting 192 cannot hit zero + -- underflow + -- DP constant = 1536 underflow at zero ... worst expo = -53??? + -- SP constant = 192 underflow at 896 ... worst expo = + + + ex5_expo_p0kx(13) <= ex5_expo_p0k(13); --or not ex5_res_frac(0) ; -- joke does not effect these bits + ex5_expo_p1kx(13) <= ex5_expo_p1k(13) ; --or not ex5_res_frac(0) ; -- joke does not effect these bits + ------------- + + + ex5_res_expo( 1) <= ( ex5_expo_p0kx( 1) and not ex5_res_sel_p1_e and not ex5_res_clip_e ) or -- 4096 /sign + ( ex5_expo_p1kx( 1) and ex5_res_sel_p1_e ); + ex5_res_expo( 2) <= ( ex5_expo_p0kx( 2) and not ex5_res_sel_p1_e and not ex5_res_clip_e ) or -- 2048 + ( ex5_expo_p1kx( 2) and ex5_res_sel_p1_e ); + ex5_res_expo( 3) <= ( ex5_expo_p0kx( 3) and not ex5_res_sel_p1_e and not ex5_res_clip_e ) or -- 1024 + ( ex5_expo_p1kx( 3) and ex5_res_sel_p1_e ); + + ex5_res_expo( 4) <= ( ex5_expo_p0kx( 4) and not ex5_res_sel_p1_e and not ex5_res_clip_e ) or -- 512 + ( ex5_sp and not ex5_res_sel_p1_e and ex5_res_clip_e ) or + ( ex5_expo_p1kx( 4) and ex5_res_sel_p1_e ); + ex5_res_expo( 5) <= ( ex5_expo_p0kx( 5) and not ex5_res_sel_p1_e and not ex5_res_clip_e ) or -- 256 + ( ex5_sp and not ex5_res_sel_p1_e and ex5_res_clip_e ) or + ( ex5_expo_p1kx( 5) and ex5_res_sel_p1_e ); + ex5_res_expo( 6) <= ( ex5_expo_p0kx( 6) and not ex5_res_sel_p1_e and not ex5_res_clip_e ) or -- 128 + ( ex5_sp and not ex5_res_sel_p1_e and ex5_res_clip_e ) or + ( ex5_expo_p1kx( 6) and ex5_res_sel_p1_e ); + + ex5_res_expo( 7) <= ( ex5_expo_p0kx( 7) and not ex5_res_sel_p1_e and not ex5_res_clip_e ) or -- 64 + ( ex5_expo_p1kx( 7) and ex5_res_sel_p1_e ); + ex5_res_expo( 8) <= ( ex5_expo_p0kx( 8) and not ex5_res_sel_p1_e and not ex5_res_clip_e ) or -- 32 + ( ex5_expo_p1kx( 8) and ex5_res_sel_p1_e ); + ex5_res_expo( 9) <= ( ex5_expo_p0kx( 9) and not ex5_res_sel_p1_e and not ex5_res_clip_e ) or -- 16 + ( ex5_expo_p1kx( 9) and ex5_res_sel_p1_e ); + ex5_res_expo(10) <= ( ex5_expo_p0kx(10) and not ex5_res_sel_p1_e and not ex5_res_clip_e ) or -- 8 + ( ex5_expo_p1kx(10) and ex5_res_sel_p1_e ); + ex5_res_expo(11) <= ( ex5_expo_p0kx(11) and not ex5_res_sel_p1_e and not ex5_res_clip_e ) or -- 4 + ( ex5_expo_p1kx(11) and ex5_res_sel_p1_e ); + ex5_res_expo(12) <= ( ex5_expo_p0kx(12) and not ex5_res_sel_p1_e and not ex5_res_clip_e ) or -- 2 + ( ex5_expo_p1kx(12) and ex5_res_sel_p1_e ); + ex5_res_expo(13) <= ( ex5_expo_p0kx(13) and not ex5_res_sel_p1_e ) or + ( not ex5_res_sel_p1_e and ex5_res_clip_e ) or + ( ex5_expo_p1kx(13) and ex5_res_sel_p1_e ); + + --//##------------------------------------------- + --//## final selection muxing sign + --//##------------------------------------------- + -- actually know to_integer sign for signed convert ahead of time. + -- may be unsigned converts in the future + + ex5_sgn_result_fp <= f_pic_ex5_round_sign xor f_pic_ex5_invert_sign; + + ex5_res_sign_prez <= + ( ex5_sgn_result_fp and not ( (ex5_to_integer or f_gst_ex5_logexp_v) and not ex5_expo_sel_k) ) or + ( ex5_to_int_data(0) and ( ex5_to_integer and not ex5_expo_sel_k) and not ex5_word ) or + ( f_gst_ex5_logexp_sign and ( f_gst_ex5_logexp_v and not ex5_expo_sel_k) ) ; + + + ex5_exact_zero_rnd <= f_nrm_ex5_exact_zero and + not f_nrm_ex5_nrm_sticky_dp ; -- really just after aligner sicky from shift underflow + + + ex5_rnd_ni_adj <= ex5_rnd_ni xor f_pic_ex5_invert_sign; + + ex5_exact_sgn_rst <= f_pic_ex5_en_exact_zero and ex5_exact_zero_rnd and not ex5_rnd_ni_adj ; + ex5_exact_sgn_set <= f_pic_ex5_en_exact_zero and ex5_exact_zero_rnd and ex5_rnd_ni_adj ; + + ex5_res_sign <= (ex5_res_sign_prez and not ex5_exact_sgn_rst) or ex5_exact_sgn_set; + + + --//##------------------------------------------- + --//## selects for final selection muxing + --//##------------------------------------------- + + ex5_res_sel_k_f <= + ( f_eov_ex5_sel_kif_f and ex5_all1 and ex5_up ) or + ( f_eov_ex5_sel_k_f ) or + ( ex5_clip_deno ) or + ( ex5_sel_est and f_tbl_ex5_recip_den and ex5_nj_deno ) ; + + --------------------- + + ex5_res_sel_p1_e <= ex5_all1 and ex5_up ; + + + ex5_est_log_pow <= f_gst_ex5_logexp_v or ex5_sel_est ; + + -- ??? should al he sel_k override massive cancellation ??? + -- i.e : unf_expo + ex5_res_clip_e <= + ( ex5_unf_en_ue0 and not f_nrm_ex5_res(0) and not ex5_expo_sel_k and not ex5_est_log_pow) or + ( ex5_unf_en_ue0 and f_eov_ex5_unf_expo and not ex5_expo_sel_k and not ex5_est_log_pow) or -- might NOT need this term since implicit catches it above + ( ex5_all0 and not ex5_to_integer and not ex5_expo_sel_k and not ex5_est_log_pow) or -- massive cancel (surprise) + ( ex5_nj_deno and not f_nrm_ex5_res(0) and not ex5_expo_sel_k and not ex5_est_log_pow) ; -- force denorm result = 0; + + ex5_clip_deno <= ( ex5_nj_deno and not f_nrm_ex5_res(0) and not ex5_expo_sel_k and not ex5_est_log_pow) ; + + ex5_expo_sel_k <= f_eov_ex5_sel_k_e; + ex5_expo_sel_k_both <= f_eov_ex5_sel_k_e or f_eov_ex5_sel_kif_e; + + + ex5_expo_p0_sel_k <= ex5_expo_sel_k ; + ex5_expo_p0_sel_gst <= not ex5_expo_sel_k and f_gst_ex5_logexp_v; + ex5_expo_p0_sel_int <= not ex5_expo_sel_k and ex5_to_integer; + ex5_expo_p0_sel_dflt <= not ex5_expo_sel_k and not ex5_to_integer and not f_gst_ex5_logexp_v; + + + ex5_expo_p1_sel_k <= ex5_expo_sel_k_both; + ex5_expo_p1_sel_dflt <= not ex5_expo_sel_k_both; + + ex5_sel_p0_joke <= -- ue1/oe1 exponent wrapping + ( ex5_unf_en_ue1 and f_eov_ex5_unf_expo ) or -- for UX + ( ex5_ovf_en_oe1 and f_eov_ex5_ovf_expo ); + + ex5_sel_p1_joke <= -- ue1/oe1/exponent wrapping + ( ex5_unf_en_ue1 and f_eov_ex5_unf_expo ) or -- for UX + ( ex5_ovf_en_oe1 and f_eov_ex5_ovf_expo ) or + ( ex5_ovf_en_oe1 and f_eov_ex5_ovf_if_expo ); + + + + + --//##------------------------------------------- + --//## flags for fspscr + --//##------------------------------------------- + + ex5_pwr4_spec_frsp <= ex5_unf_en_ue1 and not f_nrm_ex5_res(0) and f_pic_ex5_frsp ; + -- frsp : + -- For ue=1 with sp output , normalize then add 192 to exponent. + -- the 192 thing works for madd when both operands are in sp range, + -- however it does not work with frsp and a small dp number, smaller than an sp madd can create. + -- also frsp needs to know ue=1 to set up a dummy pExpo in rf2 (early). + -- this is hard since we are not suppose to stall/flush for mvto_fpscr ops. + -- if we set up the constant like ue=0 for both modes, then + -- we math the spec up to emin - 160, then give zero as a result. + -- this is simillar to (but not exactly inclusive of all) the range where the +192 works. + -- power4 seems to do it the ignore ue=1 way. + -- + -- power 4 sets the exact denorms to : fprf=+/-norm fi/fr=00 + -- i like fprf=+/-zero fi/fr=10 fprf=+/-norm fi/fr=11 + -- although that allows round up out of zero ???? + + ex5_flag_ox <= + ( f_eov_ex5_ovf_expo ) or + ( f_eov_ex5_ovf_if_expo and ex5_all1 and ex5_up ) ; + + ex5_ov_oe0 <= ex5_flag_ox and ex5_ovf_en_oe0; + + ex5_flag_inf <= + ( ex5_spec_inf ) or + ( ex5_ov_oe0 and not f_pic_ex5_k_max ); -- rnd mode decides if to use infinity + + --fr is undefined for the ovf case (usin Loki reference model that sets it to 1). + + ex5_flag_up <= ex5_ov_oe0 or ex5_up; + ex5_flag_fi <= ex5_ov_oe0 or ex5_gox; + + + + ex5_flag_ux <= -- ue=0: lzo limits exponent to 381 ... look at pre-round implicit bit + ( ex5_unf_en_ue0 and not f_nrm_ex5_res(0) and not ex5_exact_zero_rnd and ex5_gox and not ex5_sel_est ) or -- tiny with precision loss + ( ex5_unf_en_ue0 and f_eov_ex5_unf_expo and not ex5_exact_zero_rnd and ex5_gox ) or -- tiny with precision loss + ( ex5_unf_en_ue1 and f_eov_ex5_unf_expo and not ex5_exact_zero_rnd ) or -- tiny + ( ex5_unf_en_ue1 and f_eov_ex5_unf_expo and ex5_sel_est ) or -- tiny + ( ex5_unf_en_ue0 and f_eov_ex5_unf_expo and ex5_sel_est ) or -- tiny + ( ex5_pwr4_spec_frsp ); -- (power4 mode) + + + + ex5_k_zero <= f_pic_ex5_k_zer or f_pic_ex5_k_int_zer ; + + ex5_flag_zer <= + ( not ex5_sel_est and not ex5_res_sel_k_f and ex5_all0 and not ex5_up ) or -- start with zero + ( ex5_res_sel_k_f and ex5_k_zero ) ; -- forcing zero + + ex5_flag_den <= + ( not ex5_sel_est and not ex5_res_frac(0) ) or -- !implicit_bit :: denorm + ( ex5_sel_est and f_tbl_ex5_recip_den ) or + ( ex5_sel_est and ex5_unf_en_ue0 and f_eov_ex5_unf_expo ) ; + + + +--//############################################## +--//# EX6 latches +--//############################################## + + ex6_frac_lat: tri_rlmreg_p generic map (width=> 53, expand_type => expand_type, needs_sreset => 0) port map ( + forcee => forcee,--i-- tidn, + delay_lclkr => delay_lclkr(6) ,--i-- tidn, + mpw1_b => mpw1_b(6) ,--i-- tidn, + mpw2_b => mpw2_b(1) ,--i-- tidn, + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => ex5_act, + scout => ex6_frac_so , + scin => ex6_frac_si , + ------------------- + din => ex5_res_frac(0 to 52), + ------------------- + dout => ex6_res_frac(0 to 52) );--LAT-- + + ex6_expo_lat: tri_rlmreg_p generic map (width=> 14, expand_type => expand_type, needs_sreset => 0) port map ( + forcee => forcee,--i-- tidn, + delay_lclkr => delay_lclkr(6) ,--i-- tidn, + mpw1_b => mpw1_b(6) ,--i-- tidn, + mpw2_b => mpw2_b(1) ,--i-- tidn, + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => ex5_act, + scout => ex6_expo_so , + scin => ex6_expo_si , + ------------------- + din(0) => ex5_res_sign , + din(1 to 13) => ex5_res_expo(1 to 13) , + ------------------- + dout(0) => ex6_res_sign ,--LAT-- + dout(1 to 13) => ex6_res_expo(1 to 13) );--LAT-- + + ex6_flag_lat: tri_rlmreg_p generic map (width=> 10, expand_type => expand_type, needs_sreset => 1) port map ( + forcee => forcee,--i-- tidn, + delay_lclkr => delay_lclkr(6) ,--i-- tidn, + mpw1_b => mpw1_b(6) ,--i-- tidn, + mpw2_b => mpw2_b(1) ,--i-- tidn, + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => ex5_act, + scout => ex6_flag_so , + scin => ex6_flag_si , + ------------------- + din(0) => flag_spare_unused , + din(1) => ex5_res_sign , + din(2) => ex5_flag_den , + din(3) => ex5_flag_inf , + din(4) => ex5_flag_zer , + din(5) => ex5_flag_ux , + din(6) => ex5_flag_up , + din(7) => ex5_flag_fi , + din(8) => ex5_flag_ox , + din(9) => ex5_nj_deno , + ------------------- + dout(0) => flag_spare_unused ,--LAT-- + dout(1) => ex6_flag_sgn ,--LAT-- + dout(2) => ex6_flag_den ,--LAT-- + dout(3) => ex6_flag_inf ,--LAT-- + dout(4) => ex6_flag_zer ,--LAT-- + dout(5) => ex6_flag_ux ,--LAT-- + dout(6) => ex6_flag_up ,--LAT-- + dout(7) => ex6_flag_fi ,--LAT-- + dout(8) => ex6_flag_ox ,--LAT-- + dout(9) => ex6_nj_deno );--LAT-- + + + f_rnd_ex6_res_sign <= ex6_res_sign ;--output-- + f_rnd_ex6_res_expo(1 to 13) <= ex6_res_expo(1 to 13) ;--output-- + f_rnd_ex6_res_frac(0 to 52) <= ex6_res_frac(0 to 52) ;--output-- + + f_rnd_ex6_flag_sgn <= ex6_flag_sgn ;--output-- + f_rnd_ex6_flag_den <= ex6_flag_den and not ex6_nj_deno ;--output-- + f_rnd_ex6_flag_inf <= ex6_flag_inf ;--output-- + f_rnd_ex6_flag_zer <= ex6_flag_zer or (ex6_flag_den and ex6_nj_deno) ;--output-- + f_rnd_ex6_flag_ux <= ex6_flag_ux and not(ex6_flag_den and ex6_nj_deno) ;--output-- + f_rnd_ex6_flag_up <= ex6_flag_up and not(ex6_flag_den and ex6_nj_deno) ;--output-- + f_rnd_ex6_flag_fi <= ex6_flag_fi and not(ex6_flag_den and ex6_nj_deno) ;--output-- + f_rnd_ex6_flag_ox <= ex6_flag_ox ;--output-- + + + f_mad_ex6_uc_sign <= ex6_res_sign;--output-- + f_mad_ex6_uc_zero <= ex6_flag_zer and not ex6_flag_fi;--output-- ??exact zero?? + +--//############################################ +--//# scan +--//############################################ + + act_si (0 to 4) <= act_so (1 to 4) & f_rnd_si ; + ex5_ctl_si (0 to 15) <= ex5_ctl_so (1 to 15) & act_so (0) ; + ex6_frac_si (0 to 52) <= ex6_frac_so (1 to 52) & ex5_ctl_so (0) ; + ex6_expo_si (0 to 13) <= ex6_expo_so (1 to 13) & ex6_frac_so (0) ; + ex6_flag_si (0 to 9) <= ex6_flag_so (1 to 9) & ex6_expo_so (0) ; + f_rnd_so <= ex6_flag_so (0); + + +end; -- fuq_rnd ARCHITECTURE diff --git a/rel/src/vhdl/work/fuq_sa3.vhdl b/rel/src/vhdl/work/fuq_sa3.vhdl new file mode 100644 index 0000000..93ad7ef --- /dev/null +++ b/rel/src/vhdl/work/fuq_sa3.vhdl @@ -0,0 +1,1174 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee,ibm,support,tri, work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; +library clib ; + +entity fuq_sa3 is +generic(expand_type: integer := 2 ); +port( + vdd :inout power_logic; + gnd :inout power_logic; + clkoff_b :in std_ulogic; -- tiup + act_dis :in std_ulogic; -- ??tidn?? + flush :in std_ulogic; -- ??tidn?? + delay_lclkr :in std_ulogic_vector(2 to 3); -- tidn, + mpw1_b :in std_ulogic_vector(2 to 3); -- tidn, + mpw2_b :in std_ulogic_vector(0 to 0); -- tidn, + sg_1 :in std_ulogic; + thold_1 :in std_ulogic; + fpu_enable :in std_ulogic; --dc_act + nclk :in clk_logic; + + + + f_sa3_si :in std_ulogic; --perv + f_sa3_so :out std_ulogic; --perv + ex1_act_b :in std_ulogic; --act + + f_mul_ex2_sum :in std_ulogic_vector(54 to 161); + f_mul_ex2_car :in std_ulogic_vector(54 to 161); + f_alg_ex2_res :in std_ulogic_vector(0 to 162); + + f_sa3_ex3_s_lza :out std_ulogic_vector(0 to 162); -- data + f_sa3_ex3_c_lza :out std_ulogic_vector(53 to 161); -- data + + f_sa3_ex3_s_add :out std_ulogic_vector(0 to 162); -- data + f_sa3_ex3_c_add :out std_ulogic_vector(53 to 161) -- data +); + + + +end fuq_sa3; -- ENTITY + +architecture fuq_sa3 of fuq_sa3 is + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + +--//################################# +--//# sigdef : functional +--//################################# + signal thold_0_b, thold_0, forcee , sg_0 :std_ulogic; + signal act_spare_unused :std_ulogic_vector(0 to 3); + signal ex2_act :std_ulogic; + signal act_so , act_si :std_ulogic_vector(0 to 4); + signal ex3_sum :std_ulogic_vector(0 to 162); + signal ex3_car :std_ulogic_vector(53 to 161); + signal ex1_act :std_ulogic; + signal ex3_053_sum_si, ex3_053_sum_so :std_ulogic_vector(0 to 109); + signal ex3_053_car_si, ex3_053_car_so :std_ulogic_vector(0 to 108); + signal ex3_000_si, ex3_000_so :std_ulogic_vector(0 to 52); + signal ex3_sum_lza_b, ex3_sum_add_b :std_ulogic_vector(0 to 162); + signal ex3_car_lza_b, ex3_car_add_b :std_ulogic_vector(53 to 161); + signal sa3_ex3_d2clk , sa3_ex3_d1clk :std_ulogic; + signal sa3_ex3_lclk : clk_logic; + + signal ex2_alg_b :std_ulogic_vector(0 to 52) ; + signal ex2_sum_b :std_ulogic_vector(53 to 162) ; + signal ex2_car_b :std_ulogic_vector(53 to 161) ; + + signal f_alg_ex2_res_b, f_mul_ex2_sum_b, f_mul_ex2_car_b :std_ulogic_vector(55 to 161); + + + + + + + + + + + + + + + + + + +begin + + +--//################################################################ +--//# ex2 logic +--//################################################################ + + + -- this model @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ + -- + -- aligner 000 001 002 ....... 052 053 054 055 056 .... 158 159 160 161 162 + -- mul sum xxx xxx xxx ....... xxx xxx 054* 055 056 .... 158 159 160 xxx xxx + -- mul car xxx xxx xxx ....... xxx xxx 054* 055 056 .... 158 159 xxx xxx xxx + -- rid PB "1" "1" "1" ....... "1" "1" "1" "0" "0" .... "0" "0" "0" "0" "0" + -- + -- 54* is the pseudo bit ... at most 1 is on + + + + ex2_sum_b(54) <= not( not(f_mul_ex2_sum(54) or f_mul_ex2_car(54)) xor f_alg_ex2_res(54) ); + ex2_car_b(53) <= not( (f_mul_ex2_sum(54) or f_mul_ex2_car(54)) or f_alg_ex2_res(54) ); + + -- rest of bits are normal as expected + + + -- with 3:2 is it equivalent to invert all the inputs, or invert all the outputs + + u_algi: ex2_alg_b(0 to 52) <= not f_alg_ex2_res(0 to 52) ; + + + + u_pre_a: f_alg_ex2_res_b(55 to 161) <= not( f_alg_ex2_res(55 to 161) ); + u_pre_s: f_mul_ex2_sum_b(55 to 161) <= not( f_mul_ex2_sum(55 to 161) ); + u_pre_c: f_mul_ex2_car_b(55 to 161) <= not( f_mul_ex2_car(55 to 161) ); + + + res_csa_55: entity clib.c_prism_csa32 port map ( --MLT32_X1_A12TH + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(55), --i-- + b => f_mul_ex2_sum_b(55), --i-- + c => f_mul_ex2_car_b(55), --i-- + sum => ex2_sum_b(55) , --o-- + car => ex2_car_b(54) ); --o-- + res_csa_56: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(56), --i-- + b => f_mul_ex2_sum_b(56), --i-- + c => f_mul_ex2_car_b(56), --i-- + sum => ex2_sum_b(56) , --o-- + car => ex2_car_b(55) ); --o-- + res_csa_57: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(57), --i-- + b => f_mul_ex2_sum_b(57), --i-- + c => f_mul_ex2_car_b(57), --i-- + sum => ex2_sum_b(57) , --o-- + car => ex2_car_b(56) ); --o-- + res_csa_58: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(58), --i-- + b => f_mul_ex2_sum_b(58), --i-- + c => f_mul_ex2_car_b(58), --i-- + sum => ex2_sum_b(58) , --o-- + car => ex2_car_b(57) ); --o-- + res_csa_59: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(59), --i-- + b => f_mul_ex2_sum_b(59), --i-- + c => f_mul_ex2_car_b(59), --i-- + sum => ex2_sum_b(59) , --o-- + car => ex2_car_b(58) ); --o-- + res_csa_60: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(60), --i-- + b => f_mul_ex2_sum_b(60), --i-- + c => f_mul_ex2_car_b(60), --i-- + sum => ex2_sum_b(60) , --o-- + car => ex2_car_b(59) ); --o-- + res_csa_61: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(61), --i-- + b => f_mul_ex2_sum_b(61), --i-- + c => f_mul_ex2_car_b(61), --i-- + sum => ex2_sum_b(61) , --o-- + car => ex2_car_b(60) ); --o-- + res_csa_62: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(62), --i-- + b => f_mul_ex2_sum_b(62), --i-- + c => f_mul_ex2_car_b(62), --i-- + sum => ex2_sum_b(62) , --o-- + car => ex2_car_b(61) ); --o-- + res_csa_63: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(63), --i-- + b => f_mul_ex2_sum_b(63), --i-- + c => f_mul_ex2_car_b(63), --i-- + sum => ex2_sum_b(63) , --o-- + car => ex2_car_b(62) ); --o-- + res_csa_64: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(64), --i-- + b => f_mul_ex2_sum_b(64), --i-- + c => f_mul_ex2_car_b(64), --i-- + sum => ex2_sum_b(64) , --o-- + car => ex2_car_b(63) ); --o-- + res_csa_65: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(65), --i-- + b => f_mul_ex2_sum_b(65), --i-- + c => f_mul_ex2_car_b(65), --i-- + sum => ex2_sum_b(65) , --o-- + car => ex2_car_b(64) ); --o-- + res_csa_66: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(66), --i-- + b => f_mul_ex2_sum_b(66), --i-- + c => f_mul_ex2_car_b(66), --i-- + sum => ex2_sum_b(66) , --o-- + car => ex2_car_b(65) ); --o-- + res_csa_67: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(67), --i-- + b => f_mul_ex2_sum_b(67), --i-- + c => f_mul_ex2_car_b(67), --i-- + sum => ex2_sum_b(67) , --o-- + car => ex2_car_b(66) ); --o-- + res_csa_68: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(68), --i-- + b => f_mul_ex2_sum_b(68), --i-- + c => f_mul_ex2_car_b(68), --i-- + sum => ex2_sum_b(68) , --o-- + car => ex2_car_b(67) ); --o-- + res_csa_69: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(69), --i-- + b => f_mul_ex2_sum_b(69), --i-- + c => f_mul_ex2_car_b(69), --i-- + sum => ex2_sum_b(69) , --o-- + car => ex2_car_b(68) ); --o-- + res_csa_70: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(70), --i-- + b => f_mul_ex2_sum_b(70), --i-- + c => f_mul_ex2_car_b(70), --i-- + sum => ex2_sum_b(70) , --o-- + car => ex2_car_b(69) ); --o-- + res_csa_71: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(71), --i-- + b => f_mul_ex2_sum_b(71), --i-- + c => f_mul_ex2_car_b(71), --i-- + sum => ex2_sum_b(71) , --o-- + car => ex2_car_b(70) ); --o-- + res_csa_72: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(72), --i-- + b => f_mul_ex2_sum_b(72), --i-- + c => f_mul_ex2_car_b(72), --i-- + sum => ex2_sum_b(72) , --o-- + car => ex2_car_b(71) ); --o-- + res_csa_73: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(73), --i-- + b => f_mul_ex2_sum_b(73), --i-- + c => f_mul_ex2_car_b(73), --i-- + sum => ex2_sum_b(73) , --o-- + car => ex2_car_b(72) ); --o-- + res_csa_74: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(74), --i-- + b => f_mul_ex2_sum_b(74), --i-- + c => f_mul_ex2_car_b(74), --i-- + sum => ex2_sum_b(74) , --o-- + car => ex2_car_b(73) ); --o-- + res_csa_75: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(75), --i-- + b => f_mul_ex2_sum_b(75), --i-- + c => f_mul_ex2_car_b(75), --i-- + sum => ex2_sum_b(75) , --o-- + car => ex2_car_b(74) ); --o-- + res_csa_76: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(76), --i-- + b => f_mul_ex2_sum_b(76), --i-- + c => f_mul_ex2_car_b(76), --i-- + sum => ex2_sum_b(76) , --o-- + car => ex2_car_b(75) ); --o-- + res_csa_77: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(77), --i-- + b => f_mul_ex2_sum_b(77), --i-- + c => f_mul_ex2_car_b(77), --i-- + sum => ex2_sum_b(77) , --o-- + car => ex2_car_b(76) ); --o-- + res_csa_78: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(78), --i-- + b => f_mul_ex2_sum_b(78), --i-- + c => f_mul_ex2_car_b(78), --i-- + sum => ex2_sum_b(78) , --o-- + car => ex2_car_b(77) ); --o-- + res_csa_79: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(79), --i-- + b => f_mul_ex2_sum_b(79), --i-- + c => f_mul_ex2_car_b(79), --i-- + sum => ex2_sum_b(79) , --o-- + car => ex2_car_b(78) ); --o-- + res_csa_80: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(80), --i-- + b => f_mul_ex2_sum_b(80), --i-- + c => f_mul_ex2_car_b(80), --i-- + sum => ex2_sum_b(80) , --o-- + car => ex2_car_b(79) ); --o-- + res_csa_81: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(81), --i-- + b => f_mul_ex2_sum_b(81), --i-- + c => f_mul_ex2_car_b(81), --i-- + sum => ex2_sum_b(81) , --o-- + car => ex2_car_b(80) ); --o-- + res_csa_82: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(82), --i-- + b => f_mul_ex2_sum_b(82), --i-- + c => f_mul_ex2_car_b(82), --i-- + sum => ex2_sum_b(82) , --o-- + car => ex2_car_b(81) ); --o-- + res_csa_83: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(83), --i-- + b => f_mul_ex2_sum_b(83), --i-- + c => f_mul_ex2_car_b(83), --i-- + sum => ex2_sum_b(83) , --o-- + car => ex2_car_b(82) ); --o-- + res_csa_84: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(84), --i-- + b => f_mul_ex2_sum_b(84), --i-- + c => f_mul_ex2_car_b(84), --i-- + sum => ex2_sum_b(84) , --o-- + car => ex2_car_b(83) ); --o-- + res_csa_85: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(85), --i-- + b => f_mul_ex2_sum_b(85), --i-- + c => f_mul_ex2_car_b(85), --i-- + sum => ex2_sum_b(85) , --o-- + car => ex2_car_b(84) ); --o-- + res_csa_86: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(86), --i-- + b => f_mul_ex2_sum_b(86), --i-- + c => f_mul_ex2_car_b(86), --i-- + sum => ex2_sum_b(86) , --o-- + car => ex2_car_b(85) ); --o-- + res_csa_87: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(87), --i-- + b => f_mul_ex2_sum_b(87), --i-- + c => f_mul_ex2_car_b(87), --i-- + sum => ex2_sum_b(87) , --o-- + car => ex2_car_b(86) ); --o-- + res_csa_88: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(88), --i-- + b => f_mul_ex2_sum_b(88), --i-- + c => f_mul_ex2_car_b(88), --i-- + sum => ex2_sum_b(88) , --o-- + car => ex2_car_b(87) ); --o-- + res_csa_89: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(89), --i-- + b => f_mul_ex2_sum_b(89), --i-- + c => f_mul_ex2_car_b(89), --i-- + sum => ex2_sum_b(89) , --o-- + car => ex2_car_b(88) ); --o-- + res_csa_90: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(90), --i-- + b => f_mul_ex2_sum_b(90), --i-- + c => f_mul_ex2_car_b(90), --i-- + sum => ex2_sum_b(90) , --o-- + car => ex2_car_b(89) ); --o-- + res_csa_91: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(91), --i-- + b => f_mul_ex2_sum_b(91), --i-- + c => f_mul_ex2_car_b(91), --i-- + sum => ex2_sum_b(91) , --o-- + car => ex2_car_b(90) ); --o-- + res_csa_92: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(92), --i-- + b => f_mul_ex2_sum_b(92), --i-- + c => f_mul_ex2_car_b(92), --i-- + sum => ex2_sum_b(92) , --o-- + car => ex2_car_b(91) ); --o-- + res_csa_93: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(93), --i-- + b => f_mul_ex2_sum_b(93), --i-- + c => f_mul_ex2_car_b(93), --i-- + sum => ex2_sum_b(93) , --o-- + car => ex2_car_b(92) ); --o-- + res_csa_94: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(94), --i-- + b => f_mul_ex2_sum_b(94), --i-- + c => f_mul_ex2_car_b(94), --i-- + sum => ex2_sum_b(94) , --o-- + car => ex2_car_b(93) ); --o-- + res_csa_95: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(95), --i-- + b => f_mul_ex2_sum_b(95), --i-- + c => f_mul_ex2_car_b(95), --i-- + sum => ex2_sum_b(95) , --o-- + car => ex2_car_b(94) ); --o-- + res_csa_96: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(96), --i-- + b => f_mul_ex2_sum_b(96), --i-- + c => f_mul_ex2_car_b(96), --i-- + sum => ex2_sum_b(96) , --o-- + car => ex2_car_b(95) ); --o-- + res_csa_97: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(97), --i-- + b => f_mul_ex2_sum_b(97), --i-- + c => f_mul_ex2_car_b(97), --i-- + sum => ex2_sum_b(97) , --o-- + car => ex2_car_b(96) ); --o-- + res_csa_98: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(98), --i-- + b => f_mul_ex2_sum_b(98), --i-- + c => f_mul_ex2_car_b(98), --i-- + sum => ex2_sum_b(98) , --o-- + car => ex2_car_b(97) ); --o-- + res_csa_99: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(99), --i-- + b => f_mul_ex2_sum_b(99), --i-- + c => f_mul_ex2_car_b(99), --i-- + sum => ex2_sum_b(99) , --o-- + car => ex2_car_b(98) ); --o-- + res_csa_100: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(100), --i-- + b => f_mul_ex2_sum_b(100), --i-- + c => f_mul_ex2_car_b(100), --i-- + sum => ex2_sum_b(100) , --o-- + car => ex2_car_b(99) ); --o-- + res_csa_101: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(101), --i-- + b => f_mul_ex2_sum_b(101), --i-- + c => f_mul_ex2_car_b(101), --i-- + sum => ex2_sum_b(101) , --o-- + car => ex2_car_b(100) ); --o-- + res_csa_102: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(102), --i-- + b => f_mul_ex2_sum_b(102), --i-- + c => f_mul_ex2_car_b(102), --i-- + sum => ex2_sum_b(102) , --o-- + car => ex2_car_b(101) ); --o-- + res_csa_103: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(103), --i-- + b => f_mul_ex2_sum_b(103), --i-- + c => f_mul_ex2_car_b(103), --i-- + sum => ex2_sum_b(103) , --o-- + car => ex2_car_b(102) ); --o-- + res_csa_104: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(104), --i-- + b => f_mul_ex2_sum_b(104), --i-- + c => f_mul_ex2_car_b(104), --i-- + sum => ex2_sum_b(104) , --o-- + car => ex2_car_b(103) ); --o-- + res_csa_105: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(105), --i-- + b => f_mul_ex2_sum_b(105), --i-- + c => f_mul_ex2_car_b(105), --i-- + sum => ex2_sum_b(105) , --o-- + car => ex2_car_b(104) ); --o-- + res_csa_106: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(106), --i-- + b => f_mul_ex2_sum_b(106), --i-- + c => f_mul_ex2_car_b(106), --i-- + sum => ex2_sum_b(106) , --o-- + car => ex2_car_b(105) ); --o-- + res_csa_107: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(107), --i-- + b => f_mul_ex2_sum_b(107), --i-- + c => f_mul_ex2_car_b(107), --i-- + sum => ex2_sum_b(107) , --o-- + car => ex2_car_b(106) ); --o-- + res_csa_108: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(108), --i-- + b => f_mul_ex2_sum_b(108), --i-- + c => f_mul_ex2_car_b(108), --i-- + sum => ex2_sum_b(108) , --o-- + car => ex2_car_b(107) ); --o-- + res_csa_109: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(109), --i-- + b => f_mul_ex2_sum_b(109), --i-- + c => f_mul_ex2_car_b(109), --i-- + sum => ex2_sum_b(109) , --o-- + car => ex2_car_b(108) ); --o-- + res_csa_110: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(110), --i-- + b => f_mul_ex2_sum_b(110), --i-- + c => f_mul_ex2_car_b(110), --i-- + sum => ex2_sum_b(110) , --o-- + car => ex2_car_b(109) ); --o-- + res_csa_111: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(111), --i-- + b => f_mul_ex2_sum_b(111), --i-- + c => f_mul_ex2_car_b(111), --i-- + sum => ex2_sum_b(111) , --o-- + car => ex2_car_b(110) ); --o-- + res_csa_112: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(112), --i-- + b => f_mul_ex2_sum_b(112), --i-- + c => f_mul_ex2_car_b(112), --i-- + sum => ex2_sum_b(112) , --o-- + car => ex2_car_b(111) ); --o-- + res_csa_113: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(113), --i-- + b => f_mul_ex2_sum_b(113), --i-- + c => f_mul_ex2_car_b(113), --i-- + sum => ex2_sum_b(113) , --o-- + car => ex2_car_b(112) ); --o-- + res_csa_114: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(114), --i-- + b => f_mul_ex2_sum_b(114), --i-- + c => f_mul_ex2_car_b(114), --i-- + sum => ex2_sum_b(114) , --o-- + car => ex2_car_b(113) ); --o-- + res_csa_115: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(115), --i-- + b => f_mul_ex2_sum_b(115), --i-- + c => f_mul_ex2_car_b(115), --i-- + sum => ex2_sum_b(115) , --o-- + car => ex2_car_b(114) ); --o-- + res_csa_116: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(116), --i-- + b => f_mul_ex2_sum_b(116), --i-- + c => f_mul_ex2_car_b(116), --i-- + sum => ex2_sum_b(116) , --o-- + car => ex2_car_b(115) ); --o-- + res_csa_117: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(117), --i-- + b => f_mul_ex2_sum_b(117), --i-- + c => f_mul_ex2_car_b(117), --i-- + sum => ex2_sum_b(117) , --o-- + car => ex2_car_b(116) ); --o-- + res_csa_118: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(118), --i-- + b => f_mul_ex2_sum_b(118), --i-- + c => f_mul_ex2_car_b(118), --i-- + sum => ex2_sum_b(118) , --o-- + car => ex2_car_b(117) ); --o-- + res_csa_119: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(119), --i-- + b => f_mul_ex2_sum_b(119), --i-- + c => f_mul_ex2_car_b(119), --i-- + sum => ex2_sum_b(119) , --o-- + car => ex2_car_b(118) ); --o-- + res_csa_120: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(120), --i-- + b => f_mul_ex2_sum_b(120), --i-- + c => f_mul_ex2_car_b(120), --i-- + sum => ex2_sum_b(120) , --o-- + car => ex2_car_b(119) ); --o-- + res_csa_121: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(121), --i-- + b => f_mul_ex2_sum_b(121), --i-- + c => f_mul_ex2_car_b(121), --i-- + sum => ex2_sum_b(121) , --o-- + car => ex2_car_b(120) ); --o-- + res_csa_122: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(122), --i-- + b => f_mul_ex2_sum_b(122), --i-- + c => f_mul_ex2_car_b(122), --i-- + sum => ex2_sum_b(122) , --o-- + car => ex2_car_b(121) ); --o-- + res_csa_123: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(123), --i-- + b => f_mul_ex2_sum_b(123), --i-- + c => f_mul_ex2_car_b(123), --i-- + sum => ex2_sum_b(123) , --o-- + car => ex2_car_b(122) ); --o-- + res_csa_124: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(124), --i-- + b => f_mul_ex2_sum_b(124), --i-- + c => f_mul_ex2_car_b(124), --i-- + sum => ex2_sum_b(124) , --o-- + car => ex2_car_b(123) ); --o-- + res_csa_125: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(125), --i-- + b => f_mul_ex2_sum_b(125), --i-- + c => f_mul_ex2_car_b(125), --i-- + sum => ex2_sum_b(125) , --o-- + car => ex2_car_b(124) ); --o-- + res_csa_126: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(126), --i-- + b => f_mul_ex2_sum_b(126), --i-- + c => f_mul_ex2_car_b(126), --i-- + sum => ex2_sum_b(126) , --o-- + car => ex2_car_b(125) ); --o-- + res_csa_127: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(127), --i-- + b => f_mul_ex2_sum_b(127), --i-- + c => f_mul_ex2_car_b(127), --i-- + sum => ex2_sum_b(127) , --o-- + car => ex2_car_b(126) ); --o-- + res_csa_128: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(128), --i-- + b => f_mul_ex2_sum_b(128), --i-- + c => f_mul_ex2_car_b(128), --i-- + sum => ex2_sum_b(128) , --o-- + car => ex2_car_b(127) ); --o-- + res_csa_129: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(129), --i-- + b => f_mul_ex2_sum_b(129), --i-- + c => f_mul_ex2_car_b(129), --i-- + sum => ex2_sum_b(129) , --o-- + car => ex2_car_b(128) ); --o-- + res_csa_130: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(130), --i-- + b => f_mul_ex2_sum_b(130), --i-- + c => f_mul_ex2_car_b(130), --i-- + sum => ex2_sum_b(130) , --o-- + car => ex2_car_b(129) ); --o-- + res_csa_131: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(131), --i-- + b => f_mul_ex2_sum_b(131), --i-- + c => f_mul_ex2_car_b(131), --i-- + sum => ex2_sum_b(131) , --o-- + car => ex2_car_b(130) ); --o-- + res_csa_132: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(132), --i-- + b => f_mul_ex2_sum_b(132), --i-- + c => f_mul_ex2_car_b(132), --i-- + sum => ex2_sum_b(132) , --o-- + car => ex2_car_b(131) ); --o-- + res_csa_133: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(133), --i-- + b => f_mul_ex2_sum_b(133), --i-- + c => f_mul_ex2_car_b(133), --i-- + sum => ex2_sum_b(133) , --o-- + car => ex2_car_b(132) ); --o-- + res_csa_134: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(134), --i-- + b => f_mul_ex2_sum_b(134), --i-- + c => f_mul_ex2_car_b(134), --i-- + sum => ex2_sum_b(134) , --o-- + car => ex2_car_b(133) ); --o-- + res_csa_135: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(135), --i-- + b => f_mul_ex2_sum_b(135), --i-- + c => f_mul_ex2_car_b(135), --i-- + sum => ex2_sum_b(135) , --o-- + car => ex2_car_b(134) ); --o-- + res_csa_136: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(136), --i-- + b => f_mul_ex2_sum_b(136), --i-- + c => f_mul_ex2_car_b(136), --i-- + sum => ex2_sum_b(136) , --o-- + car => ex2_car_b(135) ); --o-- + res_csa_137: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(137), --i-- + b => f_mul_ex2_sum_b(137), --i-- + c => f_mul_ex2_car_b(137), --i-- + sum => ex2_sum_b(137) , --o-- + car => ex2_car_b(136) ); --o-- + res_csa_138: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(138), --i-- + b => f_mul_ex2_sum_b(138), --i-- + c => f_mul_ex2_car_b(138), --i-- + sum => ex2_sum_b(138) , --o-- + car => ex2_car_b(137) ); --o-- + res_csa_139: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(139), --i-- + b => f_mul_ex2_sum_b(139), --i-- + c => f_mul_ex2_car_b(139), --i-- + sum => ex2_sum_b(139) , --o-- + car => ex2_car_b(138) ); --o-- + res_csa_140: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(140), --i-- + b => f_mul_ex2_sum_b(140), --i-- + c => f_mul_ex2_car_b(140), --i-- + sum => ex2_sum_b(140) , --o-- + car => ex2_car_b(139) ); --o-- + res_csa_141: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(141), --i-- + b => f_mul_ex2_sum_b(141), --i-- + c => f_mul_ex2_car_b(141), --i-- + sum => ex2_sum_b(141) , --o-- + car => ex2_car_b(140) ); --o-- + res_csa_142: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(142), --i-- + b => f_mul_ex2_sum_b(142), --i-- + c => f_mul_ex2_car_b(142), --i-- + sum => ex2_sum_b(142) , --o-- + car => ex2_car_b(141) ); --o-- + res_csa_143: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(143), --i-- + b => f_mul_ex2_sum_b(143), --i-- + c => f_mul_ex2_car_b(143), --i-- + sum => ex2_sum_b(143) , --o-- + car => ex2_car_b(142) ); --o-- + res_csa_144: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(144), --i-- + b => f_mul_ex2_sum_b(144), --i-- + c => f_mul_ex2_car_b(144), --i-- + sum => ex2_sum_b(144) , --o-- + car => ex2_car_b(143) ); --o-- + res_csa_145: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(145), --i-- + b => f_mul_ex2_sum_b(145), --i-- + c => f_mul_ex2_car_b(145), --i-- + sum => ex2_sum_b(145) , --o-- + car => ex2_car_b(144) ); --o-- + res_csa_146: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(146), --i-- + b => f_mul_ex2_sum_b(146), --i-- + c => f_mul_ex2_car_b(146), --i-- + sum => ex2_sum_b(146) , --o-- + car => ex2_car_b(145) ); --o-- + res_csa_147: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(147), --i-- + b => f_mul_ex2_sum_b(147), --i-- + c => f_mul_ex2_car_b(147), --i-- + sum => ex2_sum_b(147) , --o-- + car => ex2_car_b(146) ); --o-- + res_csa_148: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(148), --i-- + b => f_mul_ex2_sum_b(148), --i-- + c => f_mul_ex2_car_b(148), --i-- + sum => ex2_sum_b(148) , --o-- + car => ex2_car_b(147) ); --o-- + res_csa_149: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(149), --i-- + b => f_mul_ex2_sum_b(149), --i-- + c => f_mul_ex2_car_b(149), --i-- + sum => ex2_sum_b(149) , --o-- + car => ex2_car_b(148) ); --o-- + res_csa_150: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(150), --i-- + b => f_mul_ex2_sum_b(150), --i-- + c => f_mul_ex2_car_b(150), --i-- + sum => ex2_sum_b(150) , --o-- + car => ex2_car_b(149) ); --o-- + res_csa_151: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(151), --i-- + b => f_mul_ex2_sum_b(151), --i-- + c => f_mul_ex2_car_b(151), --i-- + sum => ex2_sum_b(151) , --o-- + car => ex2_car_b(150) ); --o-- + res_csa_152: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(152), --i-- + b => f_mul_ex2_sum_b(152), --i-- + c => f_mul_ex2_car_b(152), --i-- + sum => ex2_sum_b(152) , --o-- + car => ex2_car_b(151) ); --o-- + res_csa_153: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(153), --i-- + b => f_mul_ex2_sum_b(153), --i-- + c => f_mul_ex2_car_b(153), --i-- + sum => ex2_sum_b(153) , --o-- + car => ex2_car_b(152) ); --o-- + res_csa_154: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(154), --i-- + b => f_mul_ex2_sum_b(154), --i-- + c => f_mul_ex2_car_b(154), --i-- + sum => ex2_sum_b(154) , --o-- + car => ex2_car_b(153) ); --o-- + res_csa_155: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(155), --i-- + b => f_mul_ex2_sum_b(155), --i-- + c => f_mul_ex2_car_b(155), --i-- + sum => ex2_sum_b(155) , --o-- + car => ex2_car_b(154) ); --o-- + res_csa_156: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(156), --i-- + b => f_mul_ex2_sum_b(156), --i-- + c => f_mul_ex2_car_b(156), --i-- + sum => ex2_sum_b(156) , --o-- + car => ex2_car_b(155) ); --o-- + res_csa_157: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(157), --i-- + b => f_mul_ex2_sum_b(157), --i-- + c => f_mul_ex2_car_b(157), --i-- + sum => ex2_sum_b(157) , --o-- + car => ex2_car_b(156) ); --o-- + res_csa_158: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(158), --i-- + b => f_mul_ex2_sum_b(158), --i-- + c => f_mul_ex2_car_b(158), --i-- + sum => ex2_sum_b(158) , --o-- + car => ex2_car_b(157) ); --o-- + res_csa_159: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(159), --i-- + b => f_mul_ex2_sum_b(159), --i-- + c => f_mul_ex2_car_b(159), --i-- + sum => ex2_sum_b(159) , --o-- + car => ex2_car_b(158) ); --o-- + res_csa_160: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(160), --i-- + b => f_mul_ex2_sum_b(160), --i-- + c => f_mul_ex2_car_b(160), --i-- + sum => ex2_sum_b(160) , --o-- + car => ex2_car_b(159) ); --o-- + res_csa_161: entity clib.c_prism_csa32 port map ( + vd => vdd, + gd => gnd, + a => f_alg_ex2_res_b(161), --i-- + b => f_mul_ex2_sum_b(161), --i-- + c => f_mul_ex2_car_b(161), --i-- + sum => ex2_sum_b(161) , --o-- + car => ex2_car_b(160) ); --o-- + + ex2_sum_b(53) <= not f_alg_ex2_res(53) ; + ex2_sum_b(162) <= not f_alg_ex2_res(162) ; + ex2_car_b(161) <= tiup; + +--//################################################################ +--//# functional latches +--//################################################################ + +-- 053:068 : 16sum, 16 carry +-- 069:084 +-- 085:100 +-- 101:116 +-- 117:132 +-- 133:148 +-- 149:164 + + + + ex3_000_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 53, btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd, + gd => gnd, + LCLK => sa3_ex3_lclk ,--lclk.clk + D1CLK => sa3_ex3_d1clk , + D2CLK => sa3_ex3_d2clk , + SCANIN => ex3_000_si , + SCANOUT => ex3_000_so , + D => ex2_alg_b(0 to 52) , + QB => ex3_sum(0 to 52) ); + + ex3_053_sum_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 110, btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd, + gd => gnd, + LCLK => sa3_ex3_lclk ,--lclk.clk + D1CLK => sa3_ex3_d1clk , + D2CLK => sa3_ex3_d2clk , + SCANIN => ex3_053_sum_si , + SCANOUT => ex3_053_sum_so , + D => ex2_sum_b(53 to 162) , + QB => ex3_sum(53 to 162) ); + + ex3_053_car_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 109, btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd, + gd => gnd, + LCLK => sa3_ex3_lclk ,--lclk.clk + D1CLK => sa3_ex3_d1clk , + D2CLK => sa3_ex3_d2clk , + SCANIN => ex3_053_car_si , + SCANOUT => ex3_053_car_so , + D => ex2_car_b(53 to 161) , + QB => ex3_car(53 to 161) ); + + + + + + inv_sum_lza: ex3_sum_lza_b(0 to 162) <= not ex3_sum(0 to 162) ; + inv_car_lza: ex3_car_lza_b(53 to 161) <= not ex3_car(53 to 161) ; + inv_sum_add: ex3_sum_add_b(0 to 162) <= not ex3_sum(0 to 162) ; + inv_car_add: ex3_car_add_b(53 to 161) <= not ex3_car(53 to 161) ; + + buf_sum_lza: f_sa3_ex3_s_lza(0 to 162) <= not ex3_sum_lza_b(0 to 162) ; + buf_car_lza: f_sa3_ex3_c_lza(53 to 161) <= not ex3_car_lza_b(53 to 161) ; + buf_sum_add: f_sa3_ex3_s_add(0 to 162) <= not ex3_sum_add_b(0 to 162) ; + buf_car_add: f_sa3_ex3_c_add(53 to 161) <= not ex3_car_add_b(53 to 161) ; + + + + +--//################################################################ +--//# pervasive +--//################################################################ + + + thold_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => thold_1, + q(0) => thold_0 ); + + sg_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => sg_1 , + q(0) => sg_0 ); + + + lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map ( + clkoff_b => clkoff_b, + thold => thold_0, + sg => sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => thold_0_b ); + +--//################################################################ +--//# act +--//################################################################ + + ex1_act <= not ex1_act_b ; + + act_lat: tri_rlmreg_p generic map (width=> 5, expand_type => expand_type, needs_sreset => 0) port map ( + forcee => forcee,-- tidn, + delay_lclkr => delay_lclkr(2) ,-- tidn, + mpw1_b => mpw1_b(2) ,-- tidn, + mpw2_b => mpw2_b(0) ,-- tidn, + vd => vdd, + gd => gnd, + nclk => nclk, + act => fpu_enable, + thold_b => thold_0_b, + sg => sg_0, + scout => act_so , + scin => act_si , + ------------------- + din(0) => act_spare_unused(0), + din(1) => act_spare_unused(1), + din(2) => ex1_act, + din(3) => act_spare_unused(2), + din(4) => act_spare_unused(3), + ------------------- + dout(0) => act_spare_unused(0), + dout(1) => act_spare_unused(1), + dout(2) => ex2_act, + dout(3) => act_spare_unused(2) , + dout(4) => act_spare_unused(3) ); + + sa3_ex3_lcb : tri_lcbnd generic map (expand_type => expand_type) port map( + delay_lclkr => delay_lclkr(3) ,-- tidn ,--in + mpw1_b => mpw1_b(3) ,-- tidn ,--in + mpw2_b => mpw2_b(0) ,-- tidn ,--in + forcee => forcee,-- tidn ,--in + nclk => nclk ,--in + vd => vdd ,--inout + gd => gnd ,--inout + act => ex2_act ,--in + sg => sg_0 ,--in + thold_b => thold_0_b ,--in + d1clk => sa3_ex3_d1clk ,--out + d2clk => sa3_ex3_d2clk ,--out + lclk => sa3_ex3_lclk );--out + + +--//################################################################ +--//# scan string +--//################################################################ + + ex3_053_car_si(0 to 108) <= ex3_053_car_so(1 to 108) & f_sa3_si ; + ex3_053_sum_si(0 to 109) <= ex3_053_sum_so(1 to 109) & ex3_053_car_so(0); + ex3_000_si(0 to 52) <= ex3_000_so(1 to 52) & ex3_053_sum_so(0) ; + act_si(0 to 4) <= act_so (1 to 4) & ex3_000_so(0); + f_sa3_so <= act_so(0); + + +end; -- fuq_sa3 ARCHITECTURE diff --git a/rel/src/vhdl/work/fuq_scr.vhdl b/rel/src/vhdl/work/fuq_scr.vhdl new file mode 100644 index 0000000..7c11fd3 --- /dev/null +++ b/rel/src/vhdl/work/fuq_scr.vhdl @@ -0,0 +1,1110 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + + +--//## some inputs and their latches can be droped (fr/fi always enabled together) +--//## (ox/ux always enabled together) +--//## spec always sets fr=fi=ox=ux=0 +--//############################################################################## + +-- cyc ex4 NORM : fpscr_rd +-- cyc ex5 RND : +-- cyc ex6 FPSCR : fpscr_wr +-- +-- +-- FPSCR BIT DEFINITIONS +-- ---------------- status 3:12,21:23 resetable +-- [ 0] fx exception transition 0->1 (except mtfs,mtfsi) +-- [ 1] fex "or" of enabled exceptions +-- [ 2] vex "or" of invalid exceptions +-- [ 3] ox +-- [ 4] ux +-- [ 5] zx +-- [ 6] xx +-- [ 7] vxsnan +-- [ 8] vxisi (inf-sub-inf) +-- [ 9] vxidi +-- [10] vxzdz +-- [11] vximz +-- [12] vxvc +-- [13] fr +-- [14] fi +-- [15] FPRF C +-- [16] FPRF fpcc(lt) +-- [17] FPRF fpcc(gt) +-- [18] FPRF fpcc(eq) +-- [19] FPRF fpcc(nan) +-- [20] RESERVED +-- [21] vx-soft +-- [22] vx-sqrt +-- [23] vx-vci +-- -------------- control +-- [24] ve +-- [25] oe +-- [26] ue +-- [27] ze +-- [28] xe +-- [29] non-ieee +-- [30:31] rnd_mode 00:nr 01:zr 02:pi 03:ni +----------------- +-- FPRF +-- 10001 QNAN [0] qnan | den | (sign*zero) +-- 01001 -INF [1] sign * !zero +-- 01000 -norm [2] !sign * !zero * !qnan +-- 11000 -den [3] zero +-- 10010 -zero [4] inf | qnan +-- 00010 +zero +-- 10100 +den +-- 00100 +norm +-- 00101 +inf + + +ENTITY fuq_scr IS +generic( expand_type : integer := 2 ); -- 0 - ibm tech, 1 - other ); +PORT( + + vdd :inout power_logic; + gnd :inout power_logic; + clkoff_b :in std_ulogic; -- tiup + act_dis :in std_ulogic; -- ??tidn?? + flush :in std_ulogic; -- ??tidn?? + delay_lclkr :in std_ulogic_vector(4 to 7); -- tidn, + mpw1_b :in std_ulogic_vector(4 to 7); -- tidn, + mpw2_b :in std_ulogic_vector(0 to 1); -- tidn, + sg_1 :in std_ulogic; + thold_1 :in std_ulogic; + fpu_enable :in std_ulogic; --dc_act + nclk :in clk_logic; + + + f_scr_si :in std_ulogic ;-- perv + f_scr_so :out std_ulogic ;-- perv + ex2_act_b :in std_ulogic ;-- act writes + f_cr2_ex3_thread_b :in std_ulogic_vector(0 to 3) ;-- thread write + f_pic_ex5_scr_upd_move_b :in std_ulogic ; + f_pic_ex5_scr_upd_pipe_b :in std_ulogic ; + f_dcd_ex6_cancel :in std_ulogic ; + + f_pic_ex5_fprf_spec_b :in std_ulogic_vector(0 to 4) ;--FPRF for special cases + f_pic_ex5_compare_b :in std_ulogic ; + f_pic_ex5_fprf_pipe_v_b :in std_ulogic ; + f_pic_ex5_fprf_hold_b :in std_ulogic ;--compare + f_pic_ex5_fi_spec_b :in std_ulogic ; + f_pic_ex5_fi_pipe_v_b :in std_ulogic ; + f_pic_ex5_fr_spec_b :in std_ulogic ; + f_pic_ex5_fr_pipe_v_b :in std_ulogic ; + f_pic_ex5_ox_spec_b :in std_ulogic ; + f_pic_ex5_ox_pipe_v_b :in std_ulogic ; + f_pic_ex5_ux_spec_b :in std_ulogic ; + f_pic_ex5_ux_pipe_v_b :in std_ulogic ; + + f_pic_ex5_flag_vxsnan_b :in std_ulogic ;--//# sig_nan + f_pic_ex5_flag_vxisi_b :in std_ulogic ;--//# inf_sub_inf + f_pic_ex5_flag_vxidi_b :in std_ulogic ;--//# inf_div_inf + f_pic_ex5_flag_vxzdz_b :in std_ulogic ;--//# zer_div_zer + f_pic_ex5_flag_vximz_b :in std_ulogic ;--//# inf_mul_zer + f_pic_ex5_flag_vxvc_b :in std_ulogic ;--//# inval_cmp + f_pic_ex5_flag_vxsqrt_b :in std_ulogic ;--//# inval_sqrt + f_pic_ex5_flag_vxcvi_b :in std_ulogic ;--//# inval_convert + f_pic_ex5_flag_zx_b :in std_ulogic ;--//# div_zer + + f_cr2_ex3_fpscr_bit_data_b :in std_ulogic_vector(0 to 3) ; + f_cr2_ex3_fpscr_bit_mask_b :in std_ulogic_vector(0 to 3) ; + f_cr2_ex3_fpscr_nib_mask_b :in std_ulogic_vector(0 to 8) ; + f_cr2_ex3_mcrfs_b :in std_ulogic ; + f_cr2_ex3_mtfsf_b :in std_ulogic ; + f_cr2_ex3_mtfsfi_b :in std_ulogic ; + f_cr2_ex3_mtfsbx_b :in std_ulogic ; + + + f_nrm_ex5_fpscr_wr_dat_dfp :in std_ulogic_vector(0 to 3) ; + f_scr_ex5_fpscr_rd_dat_dfp :out std_ulogic_vector(0 to 3) ; + + f_nrm_ex5_fpscr_wr_dat :in std_ulogic_vector(0 to 31) ; + + f_cr2_ex6_fpscr_rd_dat :in std_ulogic_vector(24 to 31) ;--//# for update + f_cr2_ex5_fpscr_rd_dat :in std_ulogic_vector(24 to 31) ;--//# for mffs + f_scr_ex5_fpscr_rd_dat :out std_ulogic_vector(0 to 31) ;--//# f_rnd + + f_rnd_ex6_flag_up :in std_ulogic ; + f_rnd_ex6_flag_fi :in std_ulogic ; + f_rnd_ex6_flag_ox :in std_ulogic ; + f_rnd_ex6_flag_den :in std_ulogic ; + f_rnd_ex6_flag_sgn :in std_ulogic ; + f_rnd_ex6_flag_inf :in std_ulogic ; + f_rnd_ex6_flag_zer :in std_ulogic ; + f_rnd_ex6_flag_ux :in std_ulogic ; + + f_scr_ex7_cr_fld :out std_ulogic_vector(0 to 3) ;--//#iu + f_scr_ex7_fx_thread0 :out std_ulogic_vector(0 to 3) ;--//#iu + f_scr_ex7_fx_thread1 :out std_ulogic_vector(0 to 3) ;--//#iu + f_scr_ex7_fx_thread2 :out std_ulogic_vector(0 to 3) ;--//#iu + f_scr_ex7_fx_thread3 :out std_ulogic_vector(0 to 3) --//#iu + + +); -- end ports + + + +end fuq_scr; -- ENTITY + + +architecture fuq_scr of fuq_scr is + + constant tiup :std_ulogic := '1'; + constant tidn :std_ulogic := '0'; + + signal sg_0 :std_ulogic ; + signal thold_0_b , thold_0, forcee :std_ulogic ; + signal ex3_act :std_ulogic ; + signal ex2_act :std_ulogic ; + signal ex4_act :std_ulogic ; + signal ex5_act :std_ulogic ; + signal ex6_act :std_ulogic ; + signal ex6_th0_act :std_ulogic ; + signal ex6_th1_act :std_ulogic ; + signal ex6_th2_act :std_ulogic ; + signal ex6_th3_act :std_ulogic ; + signal ex6_th0_act_wocan :std_ulogic ; + signal ex6_th1_act_wocan :std_ulogic ; + signal ex6_th2_act_wocan :std_ulogic ; + signal ex6_th3_act_wocan :std_ulogic ; + signal act_spare_unused :std_ulogic_vector(0 to 3) ; + ------------------- + signal act_so :std_ulogic_vector(0 to 13) ;--SCAN + signal act_si :std_ulogic_vector(0 to 13) ;--SCAN + + signal ex4_ctl_so :std_ulogic_vector(0 to 24) ;--SCAN + signal ex4_ctl_si :std_ulogic_vector(0 to 24) ;--SCAN + signal ex5_ctl_so :std_ulogic_vector(0 to 24) ;--SCAN + signal ex5_ctl_si :std_ulogic_vector(0 to 24) ;--SCAN + signal ex6_ctl_so :std_ulogic_vector(0 to 24) ;--SCAN + signal ex6_ctl_si :std_ulogic_vector(0 to 24) ;--SCAN + + signal ex6_flag_so :std_ulogic_vector(0 to 24) ;--SCAN + signal ex6_flag_si :std_ulogic_vector(0 to 24) ;--SCAN + signal ex6_mvdat_so :std_ulogic_vector(0 to 27) ;--SCAN + signal ex6_mvdat_si :std_ulogic_vector(0 to 27) ;--SCAN + + signal fpscr_th0_so :std_ulogic_vector(0 to 27) ;--SCAN + signal fpscr_th0_si :std_ulogic_vector(0 to 27) ;--SCAN + signal fpscr_th1_so :std_ulogic_vector(0 to 27) ;--SCAN + signal fpscr_th1_si :std_ulogic_vector(0 to 27) ;--SCAN + signal fpscr_th2_so :std_ulogic_vector(0 to 27) ;--SCAN + signal fpscr_th2_si :std_ulogic_vector(0 to 27) ;--SCAN + signal fpscr_th3_so :std_ulogic_vector(0 to 27) ;--SCAN + signal fpscr_th3_si :std_ulogic_vector(0 to 27) ;--SCAN + + signal ex7_crf_so :std_ulogic_vector(0 to 3) ;--SCAN + signal ex7_crf_si :std_ulogic_vector(0 to 3) ;--SCAN + ------------------- + signal ex6_mrg :std_ulogic_vector(0 to 23) ; + signal ex6_mrg_dfp :std_ulogic_vector(0 to 3) ; + signal ex6_fpscr_dfp_din :std_ulogic_vector(0 to 3) ; + signal ex6_fpscr_din :std_ulogic_vector(0 to 23) ; + signal ex6_cr_fld , ex6_cr_fld_x :std_ulogic_vector(0 to 3) ; + signal ex6_fpscr_move :std_ulogic_vector(0 to 23) ; + signal ex6_fpscr_pipe :std_ulogic_vector(0 to 23) ; + signal ex6_fpscr_move_dfp :std_ulogic_vector(0 to 3) ; + signal ex6_fpscr_pipe_dfp :std_ulogic_vector(0 to 3) ; + + signal fpscr_dfp_th0 :std_ulogic_vector(0 to 3) ; + signal fpscr_dfp_th1 :std_ulogic_vector(0 to 3) ; + signal fpscr_dfp_th2 :std_ulogic_vector(0 to 3) ; + signal fpscr_dfp_th3 :std_ulogic_vector(0 to 3) ; + + signal fpscr_th0 :std_ulogic_vector(0 to 23) ; + signal fpscr_th1 :std_ulogic_vector(0 to 23) ; + signal fpscr_th2 :std_ulogic_vector(0 to 23) ; + signal fpscr_th3 :std_ulogic_vector(0 to 23) ; + + signal fpscr_rd_dat :std_ulogic_vector(0 to 31) ; + signal fpscr_rd_dat_dfp :std_ulogic_vector(0 to 3) ; + signal ex7_cr_fld :std_ulogic_vector(0 to 3) ; + signal ex6_fprf_pipe :std_ulogic_vector(0 to 4) ; + + signal ex4_thread :std_ulogic_vector(0 to 3) ; + signal ex5_thread :std_ulogic_vector(0 to 3) ; + signal ex6_thread :std_ulogic_vector(0 to 3) ; + + signal ex5_th0_act :std_ulogic ; + signal ex5_th1_act :std_ulogic ; + signal ex5_th2_act :std_ulogic ; + signal ex5_th3_act :std_ulogic ; + signal ex6_upd_move :std_ulogic ; + signal ex6_upd_pipe :std_ulogic ; + + signal ex6_fprf_spec :std_ulogic_vector(0 to 4) ; + signal ex6_compare :std_ulogic ; + signal ex6_fprf_pipe_v :std_ulogic ; + signal ex6_fprf_hold :std_ulogic ; + signal ex6_fi_spec :std_ulogic ; + signal ex6_fi_pipe_v :std_ulogic ; + signal ex6_fr_spec :std_ulogic ; + signal ex6_fr_pipe_v :std_ulogic ; + signal ex6_ox_spec :std_ulogic ; + signal ex6_ox_pipe_v :std_ulogic ; + signal ex6_ux_spec :std_ulogic ; + signal ex6_ux_pipe_v :std_ulogic ; + signal ex6_mv_data :std_ulogic_vector(0 to 23) ; + signal ex6_mv_data_dfp :std_ulogic_vector(0 to 3) ; + signal ex6_mv_sel :std_ulogic_vector(0 to 23) ; + signal ex6_mv_sel_dfp :std_ulogic_vector(0 to 3) ; + + signal ex6_flag_vxsnan :std_ulogic ; + signal ex6_flag_vxisi :std_ulogic ; + signal ex6_flag_vxidi :std_ulogic ; + signal ex6_flag_vxzdz :std_ulogic ; + signal ex6_flag_vximz :std_ulogic ; + signal ex6_flag_vxvc :std_ulogic ; + signal ex6_flag_vxsqrt :std_ulogic ; + signal ex6_flag_vxcvi :std_ulogic ; + signal ex6_flag_zx :std_ulogic ; + signal ex6_fpscr_wr_dat :std_ulogic_vector(0 to 23) ; + signal ex6_fpscr_wr_dat_dfp :std_ulogic_vector(0 to 3) ; + signal ex6_new_excp :std_ulogic ; + signal ex4_bit_data :std_ulogic_vector(0 to 3); + signal ex4_bit_mask :std_ulogic_vector(0 to 3); + signal ex4_nib_mask :std_ulogic_vector(0 to 8); + signal ex4_mcrfs :std_ulogic; + signal ex4_mtfsf :std_ulogic; + signal ex4_mtfsfi :std_ulogic; + signal ex4_mtfsbx :std_ulogic; + signal ex5_bit_data :std_ulogic_vector(0 to 3); + signal ex5_bit_mask :std_ulogic_vector(0 to 3); + signal ex5_nib_mask :std_ulogic_vector(0 to 8); + signal ex5_mcrfs :std_ulogic; + signal ex5_mtfsf :std_ulogic; + signal ex5_mtfsfi :std_ulogic; + signal ex5_mtfsbx :std_ulogic; + signal ex6_bit_data :std_ulogic_vector(0 to 3); + signal ex6_bit_mask :std_ulogic_vector(0 to 3); + signal ex6_nib_mask :std_ulogic_vector(0 to 8); + signal ex6_mcrfs :std_ulogic; + signal ex6_mtfsf :std_ulogic; + signal ex6_mtfsfi :std_ulogic; + signal ex6_mtfsbx :std_ulogic; + signal unused_stuff :std_ulogic; + signal ex5_scr_upd_move, ex5_scr_upd_pipe :std_ulogic ; + signal ex3_thread :std_ulogic_vector(0 to 3); + signal ex3_fpscr_bit_data :std_ulogic_vector(0 to 3); + signal ex3_fpscr_bit_mask :std_ulogic_vector(0 to 3); + signal ex3_fpscr_nib_mask :std_ulogic_vector(0 to 8); + signal ex3_mcrfs :std_ulogic ; + signal ex3_mtfsf :std_ulogic ; + signal ex3_mtfsfi :std_ulogic ; + signal ex3_mtfsbx :std_ulogic ; + signal ex5_flag_vxsnan :std_ulogic; + signal ex5_flag_vxisi :std_ulogic; + signal ex5_flag_vxidi :std_ulogic; + signal ex5_flag_vxzdz :std_ulogic; + signal ex5_flag_vximz :std_ulogic; + signal ex5_flag_vxvc :std_ulogic; + signal ex5_flag_vxsqrt :std_ulogic; + signal ex5_flag_vxcvi :std_ulogic; + signal ex5_flag_zx :std_ulogic; + signal ex5_fprf_spec :std_ulogic_vector(0 to 4); + signal ex5_compare :std_ulogic; + signal ex5_fprf_pipe_v :std_ulogic; + signal ex5_fprf_hold :std_ulogic; + signal ex5_fi_spec :std_ulogic; + signal ex5_fi_pipe_v :std_ulogic; + signal ex5_fr_spec :std_ulogic; + signal ex5_fr_pipe_v :std_ulogic; + signal ex5_ox_spec :std_ulogic; + signal ex5_ox_pipe_v :std_ulogic; + signal ex5_ux_spec :std_ulogic; + signal ex5_ux_pipe_v :std_ulogic; + signal ex6_upd_move_nmcrfs :std_ulogic; + + +begin + + +--//############################################ +--//# pervasive +--//############################################ + + thold_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => thold_1, + q(0) => thold_0 ); + + sg_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => sg_1 , + q(0) => sg_0 ); + + + lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map ( + clkoff_b => clkoff_b, + thold => thold_0, + sg => sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => thold_0_b ); + + + +--//############################################ +--//# ACT LATCHES +--//############################################ + + ex2_act <= not ex2_act_b ; + ex5_scr_upd_move <= not f_pic_ex5_scr_upd_move_b ; + ex5_scr_upd_pipe <= not f_pic_ex5_scr_upd_pipe_b ; + + + act_lat: tri_rlmreg_p generic map (width=> 14, expand_type => expand_type) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(6) , + mpw1_b => mpw1_b(6) , + mpw2_b => mpw2_b(1) , + vd => vdd, + gd => gnd, + nclk => nclk, + act => fpu_enable, + thold_b => thold_0_b, + sg => sg_0, + scout => act_so , + scin => act_si , + ------------------- + din(0) => act_spare_unused(0), + din(1) => act_spare_unused(1), + din(2) => ex2_act, + din(3) => ex3_act, + din(4) => ex4_act, + din(5) => ex5_act, + din(6) => ex5_th0_act , + din(7) => ex5_th1_act , + din(8) => ex5_th2_act , + din(9) => ex5_th3_act , + din(10) => ex5_scr_upd_move , + din(11) => ex5_scr_upd_pipe , + din(12) => act_spare_unused(2), + din(13) => act_spare_unused(3), + ------------------- + dout(0) => act_spare_unused(0), + dout(1) => act_spare_unused(1), + dout(2) => ex3_act, + dout(3) => ex4_act, + dout(4) => ex5_act, + dout(5) => ex6_act, + dout(6) => ex6_th0_act_wocan , + dout(7) => ex6_th1_act_wocan , + dout(8) => ex6_th2_act_wocan , + dout(9) => ex6_th3_act_wocan , + dout(10) => ex6_upd_move , + dout(11) => ex6_upd_pipe , + dout(12) => act_spare_unused(2) , + dout(13) => act_spare_unused(3) ); + + + ex5_th0_act <= ( ex5_thread(0) and ex5_act and ( ex5_scr_upd_move or ex5_scr_upd_pipe) ) ; + ex5_th1_act <= ( ex5_thread(1) and ex5_act and ( ex5_scr_upd_move or ex5_scr_upd_pipe) ) ; + ex5_th2_act <= ( ex5_thread(2) and ex5_act and ( ex5_scr_upd_move or ex5_scr_upd_pipe) ) ; + ex5_th3_act <= ( ex5_thread(3) and ex5_act and ( ex5_scr_upd_move or ex5_scr_upd_pipe) ) ; + + ex6_th0_act <= ex6_th0_act_wocan and not f_dcd_ex6_cancel; + ex6_th1_act <= ex6_th1_act_wocan and not f_dcd_ex6_cancel; + ex6_th2_act <= ex6_th2_act_wocan and not f_dcd_ex6_cancel; + ex6_th3_act <= ex6_th3_act_wocan and not f_dcd_ex6_cancel; + +--//############################################## +--//# EX4 latches +--//############################################## + + ex3_thread(0 to 3) <= not f_cr2_ex3_thread_b(0 to 3) ; + ex3_fpscr_bit_data(0 to 3) <= not f_cr2_ex3_fpscr_bit_data_b(0 to 3) ; + ex3_fpscr_bit_mask(0 to 3) <= not f_cr2_ex3_fpscr_bit_mask_b(0 to 3) ; + ex3_fpscr_nib_mask(0 to 8) <= not f_cr2_ex3_fpscr_nib_mask_b(0 to 8) ; + ex3_mcrfs <= not f_cr2_ex3_mcrfs_b ; + ex3_mtfsf <= not f_cr2_ex3_mtfsf_b ; + ex3_mtfsfi <= not f_cr2_ex3_mtfsfi_b ; + ex3_mtfsbx <= not f_cr2_ex3_mtfsbx_b ; + + + + ex4_ctl_lat: tri_rlmreg_p generic map (width=> 25, expand_type => expand_type) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(4) , + mpw1_b => mpw1_b(4) , + mpw2_b => mpw2_b(0) , + vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_act , + thold_b => thold_0_b, + sg => sg_0, + scout => ex4_ctl_so , + scin => ex4_ctl_si , + ------------------- + din(0 to 3) => ex3_thread(0 to 3) , + din(4 to 7) => ex3_fpscr_bit_data(0 to 3) , + din(8 to 11) => ex3_fpscr_bit_mask(0 to 3) , + din(12 to 20) => ex3_fpscr_nib_mask(0 to 8) , + din(21) => ex3_mcrfs , + din(22) => ex3_mtfsf , + din(23) => ex3_mtfsfi , + din(24) => ex3_mtfsbx , + ------------------- + dout(0 to 3) => ex4_thread(0 to 3) , + dout(4 to 7) => ex4_bit_data(0 to 3) , + dout(8 to 11) => ex4_bit_mask(0 to 3) , + dout(12 to 20) => ex4_nib_mask(0 to 8) , + dout(21) => ex4_mcrfs , + dout(22) => ex4_mtfsf , + dout(23) => ex4_mtfsfi , + dout(24) => ex4_mtfsbx ); + + +--//############################################## +--//# EX5 latches +--//############################################## + + + ex5_ctl_lat: tri_rlmreg_p generic map (width=> 25, expand_type => expand_type) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(5) , + mpw1_b => mpw1_b(5) , + mpw2_b => mpw2_b(1) , + vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_act , + thold_b => thold_0_b, + sg => sg_0, + scout => ex5_ctl_so , + scin => ex5_ctl_si , + ------------------- + din(0 to 3) => ex4_thread(0 to 3) , + din(4 to 7) => ex4_bit_data(0 to 3), + din(8 to 11) => ex4_bit_mask(0 to 3), + din(12 to 20) => ex4_nib_mask(0 to 8), + din(21) => ex4_mcrfs , + din(22) => ex4_mtfsf , + din(23) => ex4_mtfsfi , + din(24) => ex4_mtfsbx , + ------------------- + dout(0 to 3) => ex5_thread(0 to 3) , + dout(4 to 7) => ex5_bit_data(0 to 3) , + dout(8 to 11) => ex5_bit_mask(0 to 3) , + dout(12 to 20) => ex5_nib_mask(0 to 8) , + dout(21) => ex5_mcrfs , + dout(22) => ex5_mtfsf , + dout(23) => ex5_mtfsfi , + dout(24) => ex5_mtfsbx ); + +--//############################################## +--//# EX6 latches +--//############################################## + + + ex6_ctl_lat: tri_rlmreg_p generic map (width=> 25, expand_type => expand_type) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(6) , + mpw1_b => mpw1_b(6) , + mpw2_b => mpw2_b(1) , + vd => vdd, + gd => gnd, + nclk => nclk, + act => ex5_act, + thold_b => thold_0_b, + sg => sg_0, + scout => ex6_ctl_so , + scin => ex6_ctl_si , + ------------------- + din(0 to 3) => ex5_thread(0 to 3), + din(4 to 7) => ex5_bit_data(0 to 3), + din(8 to 11) => ex5_bit_mask(0 to 3), + din(12 to 20) => ex5_nib_mask(0 to 8), + din(21) => ex5_mcrfs , + din(22) => ex5_mtfsf , + din(23) => ex5_mtfsfi , + din(24) => ex5_mtfsbx , + ------------------- + dout(0 to 3) => ex6_thread(0 to 3) , + dout(4 to 7) => ex6_bit_data(0 to 3) , + dout(8 to 11) => ex6_bit_mask(0 to 3) , + dout(12 to 20) => ex6_nib_mask(0 to 8) , + dout(21) => ex6_mcrfs , + dout(22) => ex6_mtfsf , + dout(23) => ex6_mtfsfi , + dout(24) => ex6_mtfsbx ); + + + ex5_flag_vxsnan <= not f_pic_ex5_flag_vxsnan_b ; + ex5_flag_vxisi <= not f_pic_ex5_flag_vxisi_b ; + ex5_flag_vxidi <= not f_pic_ex5_flag_vxidi_b ; + ex5_flag_vxzdz <= not f_pic_ex5_flag_vxzdz_b ; + ex5_flag_vximz <= not f_pic_ex5_flag_vximz_b ; + ex5_flag_vxvc <= not f_pic_ex5_flag_vxvc_b ; + ex5_flag_vxsqrt <= not f_pic_ex5_flag_vxsqrt_b ; + ex5_flag_vxcvi <= not f_pic_ex5_flag_vxcvi_b ; + ex5_flag_zx <= not f_pic_ex5_flag_zx_b ; + ex5_fprf_spec(0 to 4) <= not f_pic_ex5_fprf_spec_b(0 to 4) ; + ex5_compare <= not f_pic_ex5_compare_b ; + ex5_fprf_pipe_v <= not f_pic_ex5_fprf_pipe_v_b ; + ex5_fprf_hold <= not f_pic_ex5_fprf_hold_b ; + ex5_fi_spec <= not f_pic_ex5_fi_spec_b ; + ex5_fi_pipe_v <= not f_pic_ex5_fi_pipe_v_b ; + ex5_fr_spec <= not f_pic_ex5_fr_spec_b ; + ex5_fr_pipe_v <= not f_pic_ex5_fr_pipe_v_b ; + ex5_ox_spec <= not f_pic_ex5_ox_spec_b ; + ex5_ox_pipe_v <= not f_pic_ex5_ox_pipe_v_b ; + ex5_ux_spec <= not f_pic_ex5_ux_spec_b ; + ex5_ux_pipe_v <= not f_pic_ex5_ux_pipe_v_b ; + + + ex6_flag_lat: tri_rlmreg_p generic map (width=> 25, expand_type => expand_type) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(6) , + mpw1_b => mpw1_b(6) , + mpw2_b => mpw2_b(1) , + vd => vdd, + gd => gnd, + nclk => nclk, + act => ex5_act, + thold_b => thold_0_b, + sg => sg_0, + scout => ex6_flag_so , + scin => ex6_flag_si , + ------------------- + din(0) => ex5_flag_vxsnan ,--//# sig_nan + din(1) => ex5_flag_vxisi ,--//# inf_sub_inf + din(2) => ex5_flag_vxidi ,--//# inf_div_inf + din(3) => ex5_flag_vxzdz ,--//# zer_div_zer + din(4) => ex5_flag_vximz ,--//# inf_mul_zer + din(5) => ex5_flag_vxvc ,--//# inval_cmp + din(6) => ex5_flag_vxsqrt ,--//# inval_sqrt + din(7) => ex5_flag_vxcvi ,--//# inval_convert + din(8) => ex5_flag_zx ,--//# div_zer + din(9 to 13) => ex5_fprf_spec(0 to 4) ,--FPRF/'0'FPCC for special cases + din(14) => ex5_compare , + din(15) => ex5_fprf_pipe_v ,--fprf update exluding compare + din(16) => ex5_fprf_hold ,--fprf update including compare + din(17) => ex5_fi_spec , + din(18) => ex5_fi_pipe_v , + din(19) => ex5_fr_spec , + din(20) => ex5_fr_pipe_v , + din(21) => ex5_ox_spec , + din(22) => ex5_ox_pipe_v , + din(23) => ex5_ux_spec , + din(24) => ex5_ux_pipe_v , + ------------------- + dout(0) => ex6_flag_vxsnan ,--LAT-- + dout(1) => ex6_flag_vxisi ,--LAT-- + dout(2) => ex6_flag_vxidi ,--LAT-- + dout(3) => ex6_flag_vxzdz ,--LAT-- + dout(4) => ex6_flag_vximz ,--LAT-- + dout(5) => ex6_flag_vxvc ,--LAT-- + dout(6) => ex6_flag_vxsqrt ,--LAT-- + dout(7) => ex6_flag_vxcvi ,--LAT-- + dout(8) => ex6_flag_zx ,--LAT-- + dout(9 to 13) => ex6_fprf_spec (0 to 4) ,--LAT-- + dout(14) => ex6_compare ,--LAT-- + dout(15) => ex6_fprf_pipe_v ,--LAT-- + dout(16) => ex6_fprf_hold ,--LAT-- + dout(17) => ex6_fi_spec ,--LAT-- + dout(18) => ex6_fi_pipe_v ,--LAT-- + dout(19) => ex6_fr_spec ,--LAT-- + dout(20) => ex6_fr_pipe_v ,--LAT-- + dout(21) => ex6_ox_spec ,--LAT-- + dout(22) => ex6_ox_pipe_v ,--LAT-- + dout(23) => ex6_ux_spec ,--LAT-- + dout(24) => ex6_ux_pipe_v );--LAT-- + + + ex6_mvdat_lat: tri_rlmreg_p generic map (width=> 28, expand_type => expand_type) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(6) , + mpw1_b => mpw1_b(6) , + mpw2_b => mpw2_b(1) , + vd => vdd, + gd => gnd, + nclk => nclk, + act => ex5_act, + thold_b => thold_0_b, + sg => sg_0, + scout => ex6_mvdat_so , + scin => ex6_mvdat_si , + ------------------- + din(0 to 3) => f_nrm_ex5_fpscr_wr_dat_dfp(0 to 3) , + din(4 to 27) => f_nrm_ex5_fpscr_wr_dat(0 to 23) , + dout(0 to 3) => ex6_fpscr_wr_dat_dfp(0 to 3) ,--LAT-- + dout(4 to 27) => ex6_fpscr_wr_dat(0 to 23) );--LAT-- + + + + + +--//############################################## +--//# EX6 logic +--//############################################## + + --//#----------------------------------------- + --//# select field for mcrfs + --//#----------------------------------------- + + ex6_cr_fld_x(0 to 3) <= + ( ex6_mrg( 0 to 3) and (0 to 3=> ex6_nib_mask(0) ) ) or + ( ex6_mrg( 4 to 7) and (0 to 3=> ex6_nib_mask(1) ) ) or + ( ex6_mrg( 8 to 11) and (0 to 3=> ex6_nib_mask(2) ) ) or + ( ex6_mrg(12 to 15) and (0 to 3=> ex6_nib_mask(3) ) ) or + ( ex6_mrg(16 to 19) and (0 to 3=> ex6_nib_mask(4) ) ) or + ( (tidn & ex6_mrg(21 to 23)) and (0 to 3=> ex6_nib_mask(5) ) ) or --[20] is a reserved bit + ( f_cr2_ex6_fpscr_rd_dat(24 to 27) and (0 to 3=> ex6_nib_mask(6) ) ) or + ( f_cr2_ex6_fpscr_rd_dat(28 to 31) and (0 to 3=> ex6_nib_mask(7) ) ); + + ex6_upd_move_nmcrfs <= ex6_upd_move and not ex6_mcrfs ; + + ex6_cr_fld(0 to 3) <= + ( ex6_mrg(0 to 3) and (0 to 3 => not ex6_upd_move and not ex6_upd_pipe) ) or -- fmr + ( ex6_cr_fld_x(0 to 3) and (0 to 3 => ex6_mcrfs ) ) or -- the old value + ( ex6_fpscr_din(0 to 3) and (0 to 3 => ex6_upd_pipe ) ) or -- what the math update will be + ( ex6_fpscr_din(0 to 3) and (0 to 3 => ex6_upd_move_nmcrfs ) ) ; -- what the math update will be + + + --//#----------------------------------------------------------------------- + --//# move to logic mtfsf mtfsfi mcrf mtfsb0 mtfsb1 + --//#----------------------------------------------------------------------- + -- if mcrfs : if nib_mask selects -> reset if (0,3:12,21:23) (bit mask=1111) + -- if mtfsfi : if nib_mask selects -> load with bit data (bit mask=1111) + -- if mtfsf : if nib_mask selects -> load with wr_data (bit mask=1111) + -- if mtfsb0 : if nib_mask selects -> load with bit data (if bit mask) + -- if mtfsb1 : if nib_mask selects -> load with bit_data (if bit mask) + + + ex6_mv_data_dfp(0 to 3) <= ( ex6_bit_data(0 to 3) and (0 to 3 => not ex6_mtfsf) ) or (ex6_fpscr_wr_dat_dfp(0 to 3) and (0 to 3 => ex6_mtfsf) ); + + ex6_mv_data( 0 to 3) <= ( ex6_bit_data(0 to 3) and (0 to 3 => not ex6_mtfsf) ) or (ex6_fpscr_wr_dat( 0 to 3) and (0 to 3 => ex6_mtfsf) ); + ex6_mv_data( 4 to 7) <= ( ex6_bit_data(0 to 3) and (0 to 3 => not ex6_mtfsf) ) or (ex6_fpscr_wr_dat( 4 to 7) and (0 to 3 => ex6_mtfsf) ); + ex6_mv_data( 8 to 11) <= ( ex6_bit_data(0 to 3) and (0 to 3 => not ex6_mtfsf) ) or (ex6_fpscr_wr_dat( 8 to 11) and (0 to 3 => ex6_mtfsf) ); + ex6_mv_data(12 to 15) <= ( ex6_bit_data(0 to 3) and (0 to 3 => not ex6_mtfsf) ) or (ex6_fpscr_wr_dat(12 to 15) and (0 to 3 => ex6_mtfsf) ); + ex6_mv_data(16 to 19) <= ( ex6_bit_data(0 to 3) and (0 to 3 => not ex6_mtfsf) ) or (ex6_fpscr_wr_dat(16 to 19) and (0 to 3 => ex6_mtfsf) ); + ex6_mv_data(20 to 23) <= ( ex6_bit_data(0 to 3) and (0 to 3 => not ex6_mtfsf) ) or (ex6_fpscr_wr_dat(20 to 23) and (0 to 3 => ex6_mtfsf) ); + + + ex6_mv_sel_dfp(0) <= ex6_bit_mask(0) and ex6_nib_mask(8) ; + ex6_mv_sel_dfp(1) <= ex6_bit_mask(1) and ex6_nib_mask(8) ; + ex6_mv_sel_dfp(2) <= ex6_bit_mask(2) and ex6_nib_mask(8) ; + ex6_mv_sel_dfp(3) <= ex6_bit_mask(3) and ex6_nib_mask(8) ; + + ex6_mv_sel( 0) <= ex6_bit_mask(0) and ex6_nib_mask(0) ; -- fx + ex6_mv_sel( 1) <= tidn; --UNUSED -- fex + ex6_mv_sel( 2) <= tidn; --UNUSED -- vx + ex6_mv_sel( 3) <= ex6_bit_mask(3) and ex6_nib_mask(0) ; -- ox + ex6_mv_sel( 4) <= ex6_bit_mask(0) and ex6_nib_mask(1) ; -- ux + ex6_mv_sel( 5) <= ex6_bit_mask(1) and ex6_nib_mask(1) ; -- zx + ex6_mv_sel( 6) <= ex6_bit_mask(2) and ex6_nib_mask(1) ; -- xx + ex6_mv_sel( 7) <= ex6_bit_mask(3) and ex6_nib_mask(1) ; -- vxsnan + ex6_mv_sel( 8) <= ex6_bit_mask(0) and ex6_nib_mask(2) ; -- vxisi + ex6_mv_sel( 9) <= ex6_bit_mask(1) and ex6_nib_mask(2) ; -- vxidi + ex6_mv_sel(10) <= ex6_bit_mask(2) and ex6_nib_mask(2) ; -- vxzdz + ex6_mv_sel(11) <= ex6_bit_mask(3) and ex6_nib_mask(2) ; -- vximz + ex6_mv_sel(12) <= ex6_bit_mask(0) and ex6_nib_mask(3) ; -- vxvc + ex6_mv_sel(13) <= ex6_bit_mask(1) and ex6_nib_mask(3) and not ex6_mcrfs; -- fr + ex6_mv_sel(14) <= ex6_bit_mask(2) and ex6_nib_mask(3) and not ex6_mcrfs; -- fi + ex6_mv_sel(15) <= ex6_bit_mask(3) and ex6_nib_mask(3) and not ex6_mcrfs; -- FPRF C + ex6_mv_sel(16) <= ex6_bit_mask(0) and ex6_nib_mask(4) and not ex6_mcrfs; -- FPRF fpcc(lt) + ex6_mv_sel(17) <= ex6_bit_mask(1) and ex6_nib_mask(4) and not ex6_mcrfs; -- FPRF fpcc(gt) + ex6_mv_sel(18) <= ex6_bit_mask(2) and ex6_nib_mask(4) and not ex6_mcrfs; -- FPRF fpcc(eq) + ex6_mv_sel(19) <= ex6_bit_mask(3) and ex6_nib_mask(4) and not ex6_mcrfs; -- FPRF fpcc(nan) + ex6_mv_sel(20) <= ex6_bit_mask(0) and ex6_nib_mask(5) and not ex6_mcrfs; -- RESERVED + ex6_mv_sel(21) <= ex6_bit_mask(1) and ex6_nib_mask(5) ; -- vx-soft + ex6_mv_sel(22) <= ex6_bit_mask(2) and ex6_nib_mask(5) ; -- vx-sqrt + ex6_mv_sel(23) <= ex6_bit_mask(3) and ex6_nib_mask(5) ; -- vx-vci + + ex6_fpscr_move( 0) <= (ex6_mrg( 0) and not ex6_mv_sel( 0)) or (ex6_mv_data(0) and ex6_mv_sel( 0) ); + ex6_fpscr_move( 1) <= tidn; --//unused (from other bits after move/pipe selection) + ex6_fpscr_move( 2) <= tidn; --//unused (from other bits after move/pipe selection) + ex6_fpscr_move( 3 to 23) <= + ( ex6_mrg(3 to 23) and not ex6_mv_sel(3 to 23) ) or + ( ex6_mv_data(3 to 23) and ex6_mv_sel(3 to 23) ) ; + + ex6_fpscr_move_dfp(0 to 3) <= + ( ex6_mrg_dfp(0 to 3) and not ex6_mv_sel_dfp(0 to 3) ) or + ( ex6_mv_data_dfp(0 to 3) and ex6_mv_sel_dfp(0 to 3) ) ; + + --//#------------------------------------------------------------------------ + --//# decode fprf field for pipe settings + --//#------------------------------------------------------------------------ + -- FPRF + -- 10001 QNAN [0] qnan | den | (sign*zero) + -- 01001 -INF [1] sign * !zero + -- 01000 -norm [2] !sign * !zero * !qnan + -- 11000 -den [3] zero + -- 10010 -zero [4] inf | qnan + -- 00010 +zero + -- 10100 +den + -- 00100 +norm + -- 00101 +inf + + ex6_fprf_pipe(0) <= ( f_rnd_ex6_flag_sgn and f_rnd_ex6_flag_zer) or + ( f_rnd_ex6_flag_den and not f_rnd_ex6_flag_zer) ; + + ex6_fprf_pipe(1) <= ( f_rnd_ex6_flag_sgn and not f_rnd_ex6_flag_zer); + ex6_fprf_pipe(2) <= (not f_rnd_ex6_flag_sgn and not f_rnd_ex6_flag_zer); + ex6_fprf_pipe(3) <= f_rnd_ex6_flag_zer; + ex6_fprf_pipe(4) <= f_rnd_ex6_flag_inf ; + + --//#------------------------------------------------------------------------ + --//# functional updates (excp enable cases, special setting vs pipe setting) + --//#------------------------------------------------------------------------ + + ex6_fpscr_pipe( 0) <= ex6_mrg( 0) ; -- check 0->1 excp after selection for move/pipe + ex6_fpscr_pipe( 1) <= tidn ; --// unused (from other bits after move/pipe selection) + ex6_fpscr_pipe( 2) <= tidn ; --// unused (from other bits after move/pipe selection) + ex6_fpscr_pipe( 3) <= ex6_mrg( 3) or --ox STICKY + ex6_ox_spec or + (ex6_ox_pipe_v and f_rnd_ex6_flag_ox ); + ex6_fpscr_pipe( 4) <= ex6_mrg( 4) or --ux STICKY + ex6_ux_spec or + (ex6_ux_pipe_v and f_rnd_ex6_flag_ux ); + ex6_fpscr_pipe( 5) <= ex6_mrg( 5) or ex6_flag_zx ; --sticky + + ex6_fpscr_pipe( 6) <= (ex6_mrg( 6) ) or -- ex6_fpscr_pipe(14); --sticky version of fi + (ex6_fi_spec ) or + (ex6_fi_pipe_v and f_rnd_ex6_flag_fi ); + + ex6_fpscr_pipe( 7) <= ex6_mrg( 7) or ex6_flag_vxsnan ; --sticky + ex6_fpscr_pipe( 8) <= ex6_mrg( 8) or ex6_flag_vxisi ; --sticky + ex6_fpscr_pipe( 9) <= ex6_mrg( 9) or ex6_flag_vxidi ; --sticky + ex6_fpscr_pipe(10) <= ex6_mrg(10) or ex6_flag_vxzdz ; --sticky + ex6_fpscr_pipe(11) <= ex6_mrg(11) or ex6_flag_vximz ; --sticky + ex6_fpscr_pipe(12) <= ex6_mrg(12) or ex6_flag_vxvc ; --sticky + + + ex6_fpscr_pipe(13) <= --fr NOT sticky + (ex6_mrg(13) and ex6_compare ) or + (ex6_fr_spec ) or + (ex6_fr_pipe_v and f_rnd_ex6_flag_up ); + ex6_fpscr_pipe(14) <= --fi NOT sticky + (ex6_mrg(14) and ex6_compare ) or + (ex6_fi_spec ) or + (ex6_fi_pipe_v and f_rnd_ex6_flag_fi ); + + + + ex6_fpscr_pipe(15) <= --FPRF C NOT sticky + (ex6_mrg(15) and ex6_fprf_hold ) or + (ex6_mrg(15) and ex6_compare ) or + (ex6_fprf_spec(0) ) or + (ex6_fprf_pipe_v and ex6_fprf_pipe(0) ) ; + + + ex6_fpscr_pipe(16) <= --FPRF fpdd(lt) + (ex6_mrg(16) and ex6_fprf_hold ) or + (ex6_fprf_spec(1) ) or + (ex6_fprf_pipe_v and ex6_fprf_pipe(1) ) ; + ex6_fpscr_pipe(17) <= --FPRF fpcc(gt) + (ex6_mrg(17) and ex6_fprf_hold ) or + (ex6_fprf_spec(2) ) or + (ex6_fprf_pipe_v and ex6_fprf_pipe(2) ) ; + ex6_fpscr_pipe(18) <= --FPRF fpcc(eq) + (ex6_mrg(18) and ex6_fprf_hold ) or + (ex6_fprf_spec(3) ) or + (ex6_fprf_pipe_v and ex6_fprf_pipe(3) ) ; + ex6_fpscr_pipe(19) <= --FPRF fpcc(nan) + (ex6_mrg(19) and ex6_fprf_hold ) or + (ex6_fprf_spec(4) ) or + (ex6_fprf_pipe_v and ex6_fprf_pipe(4) ) ; + + ex6_fpscr_pipe(20) <= tidn ; -- reseved bit + ex6_fpscr_pipe(21) <= ex6_mrg(21) ; -- VXSOFT + ex6_fpscr_pipe(22) <= ex6_mrg(22) or ex6_flag_vxsqrt ;--sticky + ex6_fpscr_pipe(23) <= ex6_mrg(23) or ex6_flag_vxcvi ;--sticky + + ex6_fpscr_pipe_dfp(0 to 3) <= ex6_mrg_dfp(0 to 3); + + + --//#------------------------------------------------------------------------ + --//# creating the funny or bits afer the selection + --//#------------------------------------------------------------------------ + + + ex6_fpscr_dfp_din(0) <= (ex6_fpscr_move_dfp(0) and ex6_upd_move) or (ex6_fpscr_pipe_dfp(0) and ex6_upd_pipe) ; + ex6_fpscr_dfp_din(1) <= (ex6_fpscr_move_dfp(1) and ex6_upd_move) or (ex6_fpscr_pipe_dfp(1) and ex6_upd_pipe) ; + ex6_fpscr_dfp_din(2) <= (ex6_fpscr_move_dfp(2) and ex6_upd_move) or (ex6_fpscr_pipe_dfp(2) and ex6_upd_pipe) ; + ex6_fpscr_dfp_din(3) <= (ex6_fpscr_move_dfp(3) and ex6_upd_move) or (ex6_fpscr_pipe_dfp(3) and ex6_upd_pipe) ; + + + ex6_fpscr_din(23) <= (ex6_fpscr_move(23) and ex6_upd_move) or (ex6_fpscr_pipe(23) and ex6_upd_pipe) ; + ex6_fpscr_din(22) <= (ex6_fpscr_move(22) and ex6_upd_move) or (ex6_fpscr_pipe(22) and ex6_upd_pipe) ; + ex6_fpscr_din(21) <= (ex6_fpscr_move(21) and ex6_upd_move) or (ex6_fpscr_pipe(21) and ex6_upd_pipe) ; + ex6_fpscr_din(20) <= tidn; -- reserved + ex6_fpscr_din(19) <= (ex6_fpscr_move(19) and ex6_upd_move) or (ex6_fpscr_pipe(19) and ex6_upd_pipe) ; + ex6_fpscr_din(18) <= (ex6_fpscr_move(18) and ex6_upd_move) or (ex6_fpscr_pipe(18) and ex6_upd_pipe) ; + ex6_fpscr_din(17) <= (ex6_fpscr_move(17) and ex6_upd_move) or (ex6_fpscr_pipe(17) and ex6_upd_pipe) ; + ex6_fpscr_din(16) <= (ex6_fpscr_move(16) and ex6_upd_move) or (ex6_fpscr_pipe(16) and ex6_upd_pipe) ; + ex6_fpscr_din(15) <= (ex6_fpscr_move(15) and ex6_upd_move) or (ex6_fpscr_pipe(15) and ex6_upd_pipe) ; + ex6_fpscr_din(14) <= (ex6_fpscr_move(14) and ex6_upd_move) or (ex6_fpscr_pipe(14) and ex6_upd_pipe) ; + ex6_fpscr_din(13) <= (ex6_fpscr_move(13) and ex6_upd_move) or (ex6_fpscr_pipe(13) and ex6_upd_pipe) ; + ex6_fpscr_din(12) <= (ex6_fpscr_move(12) and ex6_upd_move) or (ex6_fpscr_pipe(12) and ex6_upd_pipe) ; + ex6_fpscr_din(11) <= (ex6_fpscr_move(11) and ex6_upd_move) or (ex6_fpscr_pipe(11) and ex6_upd_pipe) ; + ex6_fpscr_din(10) <= (ex6_fpscr_move(10) and ex6_upd_move) or (ex6_fpscr_pipe(10) and ex6_upd_pipe) ; + ex6_fpscr_din( 9) <= (ex6_fpscr_move( 9) and ex6_upd_move) or (ex6_fpscr_pipe( 9) and ex6_upd_pipe) ; + ex6_fpscr_din( 8) <= (ex6_fpscr_move( 8) and ex6_upd_move) or (ex6_fpscr_pipe( 8) and ex6_upd_pipe) ; + ex6_fpscr_din( 7) <= (ex6_fpscr_move( 7) and ex6_upd_move) or (ex6_fpscr_pipe( 7) and ex6_upd_pipe) ; + ex6_fpscr_din( 6) <= (ex6_fpscr_move( 6) and ex6_upd_move) or (ex6_fpscr_pipe( 6) and ex6_upd_pipe) ; + ex6_fpscr_din( 5) <= (ex6_fpscr_move( 5) and ex6_upd_move) or (ex6_fpscr_pipe( 5) and ex6_upd_pipe) ; + ex6_fpscr_din( 4) <= (ex6_fpscr_move( 4) and ex6_upd_move) or (ex6_fpscr_pipe( 4) and ex6_upd_pipe) ; + ex6_fpscr_din( 3) <= (ex6_fpscr_move( 3) and ex6_upd_move) or (ex6_fpscr_pipe( 3) and ex6_upd_pipe) ; + + ex6_fpscr_din(2) <= -- or all invalid operation exceptions + ex6_fpscr_din(7) or -- vxsnan + ex6_fpscr_din(8) or -- vxisi + ex6_fpscr_din(9) or -- vxidi + ex6_fpscr_din(10) or -- vxzdz + ex6_fpscr_din(11) or -- vximx + ex6_fpscr_din(12) or -- vxvc + ex6_fpscr_din(21) or -- vxzdz + ex6_fpscr_din(22) or -- vximx + ex6_fpscr_din(23) ; -- vxvc + + ex6_fpscr_din(1) <= -- masked or of all exception bits + ( ex6_fpscr_din(2) and f_cr2_ex6_fpscr_rd_dat(24) ) or -- vx* / ve + ( ex6_fpscr_din(3) and f_cr2_ex6_fpscr_rd_dat(25) ) or -- ox / oe + ( ex6_fpscr_din(4) and f_cr2_ex6_fpscr_rd_dat(26) ) or -- ux / ue + ( ex6_fpscr_din(5) and f_cr2_ex6_fpscr_rd_dat(27) ) or -- zx / ze + ( ex6_fpscr_din(6) and f_cr2_ex6_fpscr_rd_dat(28) ) ; -- xx / xe + + ex6_fpscr_din( 0) <= + (ex6_fpscr_move( 0) and ex6_upd_move) or + (ex6_fpscr_pipe( 0) and ex6_upd_pipe) or + (ex6_new_excp and not ex6_mtfsf and not ex6_mtfsfi ); + + ex6_new_excp <= -- only check the exception bits + (not ex6_mrg( 3) and ex6_fpscr_din( 3) ) or -- ox + (not ex6_mrg( 4) and ex6_fpscr_din( 4) ) or -- ux + (not ex6_mrg( 5) and ex6_fpscr_din( 5) ) or -- zx + (not ex6_mrg( 6) and ex6_fpscr_din( 6) ) or -- xx + (not ex6_mrg( 7) and ex6_fpscr_din( 7) ) or -- vxsnan + (not ex6_mrg( 8) and ex6_fpscr_din( 8) ) or -- vxisi + (not ex6_mrg( 9) and ex6_fpscr_din( 9) ) or -- vxidi + (not ex6_mrg(10) and ex6_fpscr_din(10) ) or -- vxzdz + (not ex6_mrg(11) and ex6_fpscr_din(11) ) or -- vximx + (not ex6_mrg(12) and ex6_fpscr_din(12) ) or -- vxvc + (not ex6_mrg(21) and ex6_fpscr_din(21) ) or -- vxzdz + (not ex6_mrg(22) and ex6_fpscr_din(22) ) or -- vximx + (not ex6_mrg(23) and ex6_fpscr_din(23) ) ; -- vxvc + + + +--//############################################## +--//# EX7 latches +--//############################################## + + + fpscr_th0_lat: tri_rlmreg_p generic map (width=> 28, expand_type => expand_type) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(7) , + mpw1_b => mpw1_b(7) , + mpw2_b => mpw2_b(1) , + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => ex6_th0_act, + scout => fpscr_th0_so , + scin => fpscr_th0_si , + ------------------- + din(0 to 3) => ex6_fpscr_dfp_din(0 to 3), + din(4 to 27) => ex6_fpscr_din(0 to 23), + dout(0 to 3) => fpscr_dfp_th0(0 to 3) ,--LAT-- + dout(4 to 27) => fpscr_th0(0 to 23) );--LAT-- + + fpscr_th1_lat: tri_rlmreg_p generic map (width=> 28, expand_type => expand_type) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(7) , + mpw1_b => mpw1_b(7) , + mpw2_b => mpw2_b(1) , + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => ex6_th1_act, + scout => fpscr_th1_so , + scin => fpscr_th1_si , + ------------------- + din(0 to 3) => ex6_fpscr_dfp_din(0 to 3), + din(4 to 27) => ex6_fpscr_din(0 to 23), + dout(0 to 3) => fpscr_dfp_th1(0 to 3) ,--LAT-- + dout(4 to 27) => fpscr_th1(0 to 23) );--LAT-- + + fpscr_th2_lat: tri_rlmreg_p generic map (width=> 28, expand_type => expand_type) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(7) , + mpw1_b => mpw1_b(7) , + mpw2_b => mpw2_b(1) , + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => ex6_th2_act, + scout => fpscr_th2_so , + scin => fpscr_th2_si , + ------------------- + din(0 to 3) => ex6_fpscr_dfp_din(0 to 3), + din(4 to 27) => ex6_fpscr_din(0 to 23), + dout(0 to 3) => fpscr_dfp_th2(0 to 3) ,--LAT-- + dout(4 to 27) => fpscr_th2(0 to 23) );--LAT-- + + fpscr_th3_lat: tri_rlmreg_p generic map (width=> 28, expand_type => expand_type) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(7) , + mpw1_b => mpw1_b(7) , + mpw2_b => mpw2_b(1) , + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => ex6_th3_act, + scout => fpscr_th3_so , + scin => fpscr_th3_si , + ------------------- + din(0 to 3) => ex6_fpscr_dfp_din(0 to 3), + din(4 to 27) => ex6_fpscr_din(0 to 23), + dout(0 to 3) => fpscr_dfp_th3(0 to 3) ,--LAT-- + dout(4 to 27) => fpscr_th3(0 to 23) );--LAT-- + + + ex7_crf_lat: tri_rlmreg_p generic map (width=> 4, expand_type => expand_type) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(7) , + mpw1_b => mpw1_b(7) , + mpw2_b => mpw2_b(1) , + vd => vdd, + gd => gnd, + nclk => nclk, + act => ex6_act, + thold_b => thold_0_b, + sg => sg_0, + scout => ex7_crf_so , + scin => ex7_crf_si , + ------------------- + din => ex6_cr_fld(0 to 3), + dout => ex7_cr_fld(0 to 3) );--LAT-- + + + f_scr_ex7_cr_fld(0 to 3) <= ex7_cr_fld(0 to 3) ;--output--//#iu + f_scr_ex7_fx_thread0(0 to 3) <= fpscr_th0(0 to 3) ;--output--//#iu + f_scr_ex7_fx_thread1(0 to 3) <= fpscr_th1(0 to 3) ;--output--//#iu + f_scr_ex7_fx_thread2(0 to 3) <= fpscr_th2(0 to 3) ;--output--//#iu + f_scr_ex7_fx_thread3(0 to 3) <= fpscr_th3(0 to 3) ;--output--//#iu + +--//############################################## +--//# read fpscr (mixed cycles) +--//############################################## + + fpscr_rd_dat_dfp(0 to 3) <= -- write data to bit 20 is "0" + ( fpscr_dfp_th0(0 to 3) and (0 to 3 => ex5_thread(0) ) ) or + ( fpscr_dfp_th1(0 to 3) and (0 to 3 => ex5_thread(1) ) ) or + ( fpscr_dfp_th2(0 to 3) and (0 to 3 => ex5_thread(2) ) ) or + ( fpscr_dfp_th3(0 to 3) and (0 to 3 => ex5_thread(3) ) ) ; + + fpscr_rd_dat(0 to 23) <= -- write data to bit 20 is "0" + ( fpscr_th0(0 to 23) and (0 to 23 => ex5_thread(0) ) ) or + ( fpscr_th1(0 to 23) and (0 to 23 => ex5_thread(1) ) ) or + ( fpscr_th2(0 to 23) and (0 to 23 => ex5_thread(2) ) ) or + ( fpscr_th3(0 to 23) and (0 to 23 => ex5_thread(3) ) ) ; + + ex6_mrg_dfp(0 to 3) <= -- write data to bit 20 is "0" + ( fpscr_dfp_th0(0 to 3) and (0 to 3 => ex6_thread(0) ) ) or + ( fpscr_dfp_th1(0 to 3) and (0 to 3 => ex6_thread(1) ) ) or + ( fpscr_dfp_th2(0 to 3) and (0 to 3 => ex6_thread(2) ) ) or + ( fpscr_dfp_th3(0 to 3) and (0 to 3 => ex6_thread(3) ) ) ; + + ex6_mrg(0 to 23) <= -- write data to bit 20 is "0" + ( fpscr_th0(0 to 23) and (0 to 23 => ex6_thread(0) ) ) or + ( fpscr_th1(0 to 23) and (0 to 23 => ex6_thread(1) ) ) or + ( fpscr_th2(0 to 23) and (0 to 23 => ex6_thread(2) ) ) or + ( fpscr_th3(0 to 23) and (0 to 23 => ex6_thread(3) ) ) ; + + + + fpscr_rd_dat (24 to 31) <= f_cr2_ex5_fpscr_rd_dat(24 to 31) ; + f_scr_ex5_fpscr_rd_dat(0 to 31) <= fpscr_rd_dat(0 to 31) ;--output--//#f_rnd + f_scr_ex5_fpscr_rd_dat_dfp(0 to 3) <= fpscr_rd_dat_dfp(0 to 3) ; + +--//############################################ +--//# scan +--//############################################ + + + ex4_ctl_si (0 to 24) <= ex4_ctl_so (1 to 24) & f_scr_si; + ex5_ctl_si (0 to 24) <= ex5_ctl_so (1 to 24) & ex4_ctl_so (0); + ex6_ctl_si (0 to 24) <= ex6_ctl_so (1 to 24) & ex5_ctl_so (0); + ex6_flag_si (0 to 24) <= ex6_flag_so (1 to 24) & ex6_ctl_so (0); + ex6_mvdat_si (0 to 27) <= ex6_mvdat_so (1 to 27) & ex6_flag_so (0) ; + fpscr_th0_si (0 to 27) <= fpscr_th0_so (1 to 27) & ex6_mvdat_so (0) ; + fpscr_th1_si (0 to 27) <= fpscr_th1_so (1 to 27) & fpscr_th0_so (0) ; + fpscr_th2_si (0 to 27) <= fpscr_th2_so (1 to 27) & fpscr_th1_so (0) ; + fpscr_th3_si (0 to 27) <= fpscr_th3_so (1 to 27) & fpscr_th2_so (0) ; + ex7_crf_si (0 to 3) <= ex7_crf_so (1 to 3) & fpscr_th3_so (0) ; + act_si (0 to 13) <= act_so (1 to 13) & ex7_crf_so (0) ; + f_scr_so <= act_so (0) ; + + + unused_stuff <= + or_reduce( f_nrm_ex5_fpscr_wr_dat(24 to 31) ) or + ex6_mtfsbx or + ex6_fpscr_move(1) or + ex6_fpscr_move(2) or + ex6_fpscr_move(20) or + ex6_fpscr_pipe(1) or + ex6_fpscr_pipe(2) or + ex6_fpscr_pipe(20) or + ex6_mv_data(1) or + ex6_mv_data(2) or + ex6_mv_sel(1) or + ex6_mv_sel(2) ; + +end; -- fuq_scr ARCHITECTURE diff --git a/rel/src/vhdl/work/fuq_sto.vhdl b/rel/src/vhdl/work/fuq_sto.vhdl new file mode 100644 index 0000000..68cf4e7 --- /dev/null +++ b/rel/src/vhdl/work/fuq_sto.vhdl @@ -0,0 +1,870 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + + +-- PPC FP STORE reformating +-- (1) DP STORE : sp_denorm needs to normalize +-- (2) SP STORE : dp_norm may need to denormalize +-- (3) stfwix : pass througn + + +ENTITY fuq_sto IS +generic( + expand_type : integer := 2 ); -- 0 - ibm tech, 1 - other ); +PORT( + vdd :inout power_logic; + gnd :inout power_logic; + clkoff_b :in std_ulogic; -- tiup + act_dis :in std_ulogic; -- ??tidn?? + flush :in std_ulogic; -- ??tidn?? + delay_lclkr :in std_ulogic_vector(1 to 2); -- tidn, + mpw1_b :in std_ulogic_vector(1 to 2); -- tidn, + mpw2_b :in std_ulogic_vector(0 to 0); -- tidn, + sg_1 :in std_ulogic; + thold_1 :in std_ulogic; + fpu_enable :in std_ulogic; --dc_act + nclk :in clk_logic; + + f_sto_si :in std_ulogic; + f_sto_so :out std_ulogic; + f_dcd_rf1_sto_act :in std_ulogic; + + f_fpr_ex1_s_expo_extra :in std_ulogic ; + f_fpr_ex1_s_par :in std_ulogic_vector(0 to 7) ; + f_sto_ex2_s_parity_check :out std_ulogic ; + + f_dcd_rf1_sto_dp :in std_ulogic ; + f_dcd_rf1_sto_sp :in std_ulogic ; + f_dcd_rf1_sto_wd :in std_ulogic ; + + f_byp_rf1_s_sign :in std_ulogic ; + f_byp_rf1_s_expo :in std_ulogic_vector(1 to 11) ; + f_byp_rf1_s_frac :in std_ulogic_vector(0 to 52) ; + + f_sto_ex2_sto_data :out std_ulogic_vector(0 to 63) + +); -- end ports + + + +end fuq_sto; -- ENTITY + + +architecture fuq_sto of fuq_sto is + + constant tiup :std_ulogic := '1'; + constant tidn :std_ulogic := '0'; + + signal sg_0 :std_ulogic ; + signal thold_0_b, thold_0 :std_ulogic ; + + signal rf1_act :std_ulogic ; + signal ex1_act :std_ulogic ; + signal spare_unused :std_ulogic_vector(0 to 2) ; + ------------------- + signal act_so :std_ulogic_vector(0 to 3) ;--SCAN + signal act_si :std_ulogic_vector(0 to 3) ;--SCAN + signal ex1_sins_so :std_ulogic_vector(0 to 2) ; + signal ex1_sins_si :std_ulogic_vector(0 to 2) ; + signal ex1_sop_so :std_ulogic_vector(0 to 64) ; + signal ex1_sop_si :std_ulogic_vector(0 to 64) ; + signal ex2_sto_so :std_ulogic_vector(0 to 72) ; + signal ex2_sto_si :std_ulogic_vector(0 to 72) ; + ------------------- + signal ex1_s_sign :std_ulogic; + signal ex1_s_expo :std_ulogic_vector(1 to 11); + signal ex1_s_frac :std_ulogic_vector(0 to 52); + signal ex1_sto_data :std_ulogic_vector(0 to 63) ; + signal ex2_sto_data :std_ulogic_vector(0 to 63) ; + signal ex1_sto_dp :std_ulogic ; + signal ex1_sto_sp :std_ulogic ; + signal ex1_sto_wd :std_ulogic ; + signal ex1_den_ramt8_02 :std_ulogic; + signal ex1_den_ramt8_18 :std_ulogic; + signal ex1_den_ramt4_12 :std_ulogic; + signal ex1_den_ramt4_08 :std_ulogic; + signal ex1_den_ramt4_04 :std_ulogic; + signal ex1_den_ramt4_00 :std_ulogic; + signal ex1_den_ramt1_03 :std_ulogic; + signal ex1_den_ramt1_02 :std_ulogic; + signal ex1_den_ramt1_01 :std_ulogic; + signal ex1_den_ramt1_00 :std_ulogic; + signal ex1_expo_eq896 :std_ulogic; + signal ex1_expo_ge896 :std_ulogic; + signal ex1_expo_lt896 :std_ulogic; + signal ex1_sts_lt896 :std_ulogic; + signal ex1_sts_ge896 :std_ulogic; + signal ex1_sts_expo_nz :std_ulogic; + signal ex1_fixden :std_ulogic; + signal ex1_fixden_small :std_ulogic; + signal ex1_fixden_big :std_ulogic; + signal ex1_std_nonden :std_ulogic; + signal ex1_std_fixden_big :std_ulogic; + signal ex1_std_fixden_small :std_ulogic; + signal ex1_std_nonbig :std_ulogic; + signal ex1_std_nonden_wd :std_ulogic; + signal ex1_std_lamt8_02 :std_ulogic; + signal ex1_std_lamt8_10 :std_ulogic; + signal ex1_std_lamt8_18 :std_ulogic; + signal ex1_std_lamt2_0 :std_ulogic; + signal ex1_std_lamt2_2 :std_ulogic; + signal ex1_std_lamt2_4 :std_ulogic; + signal ex1_std_lamt2_6 :std_ulogic; + signal ex1_std_lamt1_0 :std_ulogic; + signal ex1_std_lamt1_1 :std_ulogic; + signal ex1_sts_sh8 :std_ulogic_vector(0 to 23) ; + signal ex1_sts_sh4 :std_ulogic_vector(0 to 23) ; + signal ex1_sts_sh1 :std_ulogic_vector(0 to 23) ; + signal ex1_sts_nrm :std_ulogic_vector(0 to 23) ; + signal ex1_sts_frac :std_ulogic_vector(1 to 23) ; + signal ex1_sts_expo :std_ulogic_vector(1 to 8) ; + signal ex1_clz02_or :std_ulogic_vector(0 to 10) ; + signal ex1_clz02_enc4 :std_ulogic_vector(0 to 10) ; + signal ex1_clz04_or :std_ulogic_vector(0 to 5) ; + signal ex1_clz04_enc3 :std_ulogic_vector(0 to 5) ; + signal ex1_clz04_enc4 :std_ulogic_vector(0 to 5) ; + signal ex1_clz08_or :std_ulogic_vector(0 to 2) ; + signal ex1_clz08_enc2 :std_ulogic_vector(0 to 2) ; + signal ex1_clz08_enc3 :std_ulogic_vector(0 to 2) ; + signal ex1_clz08_enc4 :std_ulogic_vector(0 to 2) ; + signal ex1_clz16_or :std_ulogic_vector(0 to 1) ; + signal ex1_clz16_enc1 :std_ulogic_vector(0 to 1) ; + signal ex1_clz16_enc2 :std_ulogic_vector(0 to 1) ; + signal ex1_clz16_enc3 :std_ulogic_vector(0 to 1) ; + signal ex1_clz16_enc4 :std_ulogic_vector(0 to 1) ; + signal ex1_sto_clz :std_ulogic_vector(0 to 4) ; + signal ex1_expo_nonden :std_ulogic_vector(1 to 11) ; + signal ex1_expo_fixden :std_ulogic_vector(1 to 11) ; + signal ex1_std_expo :std_ulogic_vector(1 to 11) ; + signal ex1_std_frac_nrm :std_ulogic_vector(1 to 52) ; + signal ex1_std_sh8 :std_ulogic_vector(0 to 23) ; + signal ex1_std_sh2 :std_ulogic_vector(0 to 23) ; + signal ex1_std_frac_den :std_ulogic_vector(1 to 23) ; + signal ex1_ge874 :std_ulogic; + signal ex1_any_edge :std_ulogic; + signal ex2_sto_data_rot0_b , ex2_sto_data_rot1_b :std_ulogic_vector(0 to 63); + + signal ex2_sto_wd, ex2_sto_sp :std_ulogic_vector(0 to 3); + signal forcee :std_ulogic; + + + signal ex1_s_party_chick, ex2_s_party_chick :std_ulogic ; + signal ex1_s_party : std_ulogic_vector(0 to 7); + signal unused :std_ulogic; + + + + + +begin + + +--//############################################ +--//# pervasive +--//############################################ + + + unused <= ex1_sts_sh1(0) or ex1_sts_nrm(0) or ex1_std_sh2(0) ; + + thold_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => thold_1, + q(0) => thold_0 ); + + sg_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => sg_1 , + q(0) => sg_0 ); + + + lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map ( + clkoff_b => clkoff_b, + thold => thold_0, + sg => sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => thold_0_b ); + + + +--//############################################ +--//# ACT LATCHES +--//############################################ + + rf1_act <= f_dcd_rf1_sto_act; + + act_lat: tri_rlmreg_p generic map (width=> 4, expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + forcee => forcee, -- tidn + delay_lclkr => delay_lclkr(1), -- tidn, + mpw1_b => mpw1_b(1), -- tidn, + mpw2_b => mpw2_b(0), -- tidn, + act => fpu_enable, + thold_b => thold_0_b, + sg => sg_0, + scout => act_so , + scin => act_si , + ------------------- + din(0) => rf1_act, + din(1 to 3) => spare_unused(0 to 2) , + ------------------- + dout(0) => ex1_act , + dout(1 to 3) => spare_unused(0 to 2) ); + + +--//############################################## +--//# EX1 latch inputs from rf1 +--//############################################## + + ex1_sins_lat: entity tri.tri_rlmreg_p generic map (width=> 3, expand_type => expand_type, ibuf => true ) port map ( + forcee => forcee,--tidn, + delay_lclkr => delay_lclkr(1) ,--tidn, + mpw1_b => mpw1_b(1) ,--tidn, + mpw2_b => mpw2_b(0) ,--tidn, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => rf1_act, + vd => vdd, + gd => gnd, + scout => ex1_sins_so , + scin => ex1_sins_si , + ------------------- + din(0) => f_dcd_rf1_sto_dp , + din(1) => f_dcd_rf1_sto_sp , + din(2) => f_dcd_rf1_sto_wd , + ------------------- + dout(0) => ex1_sto_dp , + dout(1) => ex1_sto_sp , + dout(2) => ex1_sto_wd ); + + ex1_sop_lat: entity tri.tri_rlmreg_p generic map (width=> 65, expand_type => expand_type, needs_sreset => 0, ibuf => true) port map ( + forcee => forcee,--tidn, + delay_lclkr => delay_lclkr(1) ,--tidn, + mpw1_b => mpw1_b(1) ,--tidn, + mpw2_b => mpw2_b(0) ,--tidn, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => rf1_act, + vd => vdd, + gd => gnd, + scout => ex1_sop_so , + scin => ex1_sop_si , + ------------------- + din(0) => f_byp_rf1_s_sign , + din(1 to 11) => f_byp_rf1_s_expo(1 to 11) , + din(12 to 64) => f_byp_rf1_s_frac(0 to 52) , + ------------------- + dout(0) => ex1_s_sign , + dout(1 to 11) => ex1_s_expo(1 to 11), + dout(12 to 64) => ex1_s_frac(0 to 52) ); + + + +--//############################################## +--//# EX1 logic +--//############################################## + + + --//################################################### + --//# shifting for store sp + --//################################################### + -- output of dp instr with expo below x381 needs to denormalize to sp format. + -- x380 d896 011_1000_0000 => right 1 11 11 11 <== treat as special case + -- x37F d895 011_0111_1111 => right 2 00 00 00 + -- x37E d894 011_0111_1110 => right 3 00 00 01 + -- x37D d893 011_0111_1101 => right 4 00 00 10 + -- x37C d892 011_0111_1100 => right 5 00 00 11 + -- x37B d891 011_0111_1011 => right 6 00 01 00 + -- x37A d890 011_0111_1010 => right 7 00 01 01 + -- x379 d889 011_0111_1001 => right 8 00 01 10 + -- x378 d888 011_0111_1000 => right 9 00 01 11 + -- x377 d887 011_0111_0111 => right 10 00 10 00 + -- x376 d886 011_0111_0110 => right 11 00 10 01 + -- x375 d885 011_0111_0101 => right 12 00 10 10 + -- x374 d884 011_0111_0100 => right 13 00 10 11 + -- x373 d883 011_0111_0011 => right 14 00 11 00 + -- x372 d882 011_0111_0010 => right 15 00 11 01 + -- x371 d881 011_0111_0001 => right 16 00 11 10 + -- x370 d880 011_0111_0000 => right 17 00 11 11 + -- x36F d879 011_0110_1111 => right 18 01 00 00 + -- x36E d878 011_0110_1110 => right 19 01 00 01 + -- x36B d877 011_0110_1101 => right 20 01 00 10 + -- x36C d876 011_0110_1100 => right 21 01 00 11 + -- x36B d875 011_0110_1011 => right 22 01 01 00 + -- x36A d874 011_0110_1010 => right 23 01 01 01 + -- x369 d873 011_0110_1001 => right 24 01 01 10 ===> result is zero after here + -------------------------- + -- 000 0000 0011 + -- 123 4567 8901 + + ex1_den_ramt8_02 <= ex1_s_expo(6) and ex1_s_expo(7); + ex1_den_ramt8_18 <= ex1_s_expo(6) and not ex1_s_expo(7); + + ex1_den_ramt4_12 <= not ex1_s_expo(8) and not ex1_s_expo(9); + ex1_den_ramt4_08 <= not ex1_s_expo(8) and ex1_s_expo(9); + ex1_den_ramt4_04 <= ex1_s_expo(8) and not ex1_s_expo(9); + ex1_den_ramt4_00 <= ex1_s_expo(8) and ex1_s_expo(9); + + ex1_den_ramt1_03 <= not ex1_s_expo(10) and not ex1_s_expo(11); + ex1_den_ramt1_02 <= not ex1_s_expo(10) and ex1_s_expo(11); + ex1_den_ramt1_01 <= ex1_s_expo(10) and not ex1_s_expo(11); + ex1_den_ramt1_00 <= ex1_s_expo(10) and ex1_s_expo(11); + + ex1_expo_eq896 <= not ex1_s_expo(1) and -- 011_1000_0000 + ex1_s_expo(2) and + ex1_s_expo(3) and + ex1_s_expo(4) and + not ex1_s_expo(5) and + not ex1_s_expo(6) and + not ex1_s_expo(7) and + not ex1_s_expo(8) and + not ex1_s_expo(9) and + not ex1_s_expo(10) and + not ex1_s_expo(11) ; + + ex1_expo_ge896 <= + ( ex1_s_expo(1) ) or + ( ex1_s_expo(2) and ex1_s_expo(3) and ex1_s_expo(4) ) ; + + + ex1_ge874 <= -- 011_0110_1010 -- enough so shifter does not wrap 011_0110_xxxx + ( ex1_s_expo(1) ) or + ( ex1_s_expo(2) and ex1_s_expo(3) and ex1_s_expo(4) ) or + ( ex1_s_expo(2) and ex1_s_expo(3) and ex1_s_expo(5) and ex1_s_expo(6) ); + + + ex1_expo_lt896 <= not ex1_expo_ge896; + ex1_sts_lt896 <= ex1_sto_sp and ex1_expo_lt896 and ex1_ge874 ; -- result = zero when lt 874 + ex1_sts_ge896 <= ex1_sto_sp and ex1_expo_ge896 ; + + ex1_sts_sh8(0 to 23) <= + ( (0 to 23 => ex1_den_ramt8_02) and ( (0 to 1 => tidn) & ex1_s_frac(0 to 21) ) ) or + ( (0 to 23 => ex1_den_ramt8_18) and ( (0 to 17 => tidn) & ex1_s_frac(0 to 5) ) ) ; + + ex1_sts_sh4(0 to 23) <= + ( (0 to 23 => ex1_den_ramt4_12) and ( (0 to 11 => tidn) & ex1_sts_sh8(0 to 11) ) ) or + ( (0 to 23 => ex1_den_ramt4_08) and ( (0 to 7 => tidn) & ex1_sts_sh8(0 to 15) ) ) or + ( (0 to 23 => ex1_den_ramt4_04) and ( (0 to 3 => tidn) & ex1_sts_sh8(0 to 19) ) ) or + ( (0 to 23 => ex1_den_ramt4_00) and ( ex1_sts_sh8(0 to 23) ) ) ; + + ex1_sts_sh1(0 to 23) <= + ( (0 to 23 => ex1_den_ramt1_03) and ( (0 to 2 => tidn) & ex1_sts_sh4(0 to 20) ) ) or + ( (0 to 23 => ex1_den_ramt1_02) and ( (0 to 1 => tidn) & ex1_sts_sh4(0 to 21) ) ) or + ( (0 to 23 => ex1_den_ramt1_01) and ( tidn & ex1_sts_sh4(0 to 22) ) ) or + ( (0 to 23 => ex1_den_ramt1_00) and ( ex1_sts_sh4(0 to 23) ) ) ; + + ex1_sts_nrm(0 to 23) <= + ( (0 to 23 => ex1_expo_eq896) and ( tidn & ex1_s_frac(0 to 22) ) ) or + ( (0 to 23 => not ex1_expo_eq896) and ( ex1_s_frac(0 to 23) ) ) ; + + ex1_sts_frac(1 to 23) <= + ( (1 to 23 => ex1_sts_lt896) and ex1_sts_sh1(1 to 23) ) or + ( (1 to 23 => ex1_sts_ge896) and ex1_sts_nrm(1 to 23) ) ; + + --//################################################### + --//# store_sp : calc shift amount : + --//################################################### + + ex1_sts_expo_nz <= ex1_sto_sp and ex1_expo_ge896 ; + ex1_sts_expo(1) <= ex1_s_expo(1) and ex1_sts_expo_nz ; + ex1_sts_expo(2 to 7) <= ex1_s_expo(5 to 10) and (2 to 7=> ex1_sts_expo_nz); + ex1_sts_expo(8) <= ex1_s_expo(11) and ex1_s_frac(0) and ex1_sts_expo_nz ; + + --//################################################### + --//# normalization shift left amount for store_dp + --//################################################### + -- count leading zeroes to get the shift amount + --bit pos dp_expo bin_expo inv clz lsb shift left to norm + -- + -- 00 x381 011_1000_0001 1_1110 00 0_0000 <== normal + -- 01 x380 011_1000_0000 1_1111 01 0_0001 + -- 02 x37F 011_0111_1111 0_0000 02 0_0010 <=== start clz on bit 2; + -- 03 x37E 011_0111_1110 0_0001 03 0_0010 + -- 04 x37D 011_0111_1101 0_0010 04 0_0010 + -- 05 x37C 011_0111_1100 0_0011 05 0_0010 + -- 06 x37B 011_0111_1011 0_0100 06 0_0010 + -- 07 x37A 011_0111_1010 0_0101 07 0_0010 + -- 08 x379 011_0111_1001 0_0110 08 0_0010 + -- 09 x378 011_0111_1000 0_0111 09 0_0010 + -- 10 x377 011_0111_0111 0_1000 10 0_0010 + -- 11 x376 011_0111_0110 0_1001 11 0_0010 + -- 12 x375 011_0111_0101 0_1010 12 0_0010 + -- 13 x374 011_0111_0100 0_1011 13 0_0010 + -- 14 x373 011_0111_0011 0_1100 14 0_0010 + -- 15 x372 011_0111_0010 0_1101 15 0_0010 + -- 16 x371 011_0111_0001 0_1110 16 0_0010 + -- 17 x370 011_0111_0000 0_1111 17 0_0010 + -- 18 x36F 011_0110_1111 1_0000 18 0_0010 + -- 19 x36E 011_0110_1110 1_0001 19 0_0010 + -- 20 x36D 011_0110_1101 1_0010 20 0_0010 + -- 21 x36C 011_0110_1100 1_0011 21 0_0010 + -- 22 x36B 011_0110_1011 1_0100 22 0_0010 + -- 23 x36A 011_0110_1010 1_0101 23 0_0010 + + + -- if clz does not find leading bit (shift of 0 is ok) + + ex1_clz02_or ( 0) <= ex1_s_frac( 2) or ex1_s_frac( 3); + ex1_clz02_enc4( 0) <= not ex1_s_frac( 2) and ex1_s_frac( 3); + + ex1_clz02_or ( 1) <= ex1_s_frac( 4) or ex1_s_frac( 5); + ex1_clz02_enc4( 1) <= not ex1_s_frac( 4) and ex1_s_frac( 5); + + ex1_clz02_or ( 2) <= ex1_s_frac( 6) or ex1_s_frac( 7); + ex1_clz02_enc4( 2) <= not ex1_s_frac( 6) and ex1_s_frac( 7); + + ex1_clz02_or ( 3) <= ex1_s_frac( 8) or ex1_s_frac( 9); + ex1_clz02_enc4( 3) <= not ex1_s_frac( 8) and ex1_s_frac( 9); + + ex1_clz02_or ( 4) <= ex1_s_frac(10) or ex1_s_frac(11); + ex1_clz02_enc4( 4) <= not ex1_s_frac(10) and ex1_s_frac(11); + + ex1_clz02_or ( 5) <= ex1_s_frac(12) or ex1_s_frac(13); + ex1_clz02_enc4( 5) <= not ex1_s_frac(12) and ex1_s_frac(13); + + ex1_clz02_or ( 6) <= ex1_s_frac(14) or ex1_s_frac(15); + ex1_clz02_enc4( 6) <= not ex1_s_frac(14) and ex1_s_frac(15); + + ex1_clz02_or ( 7) <= ex1_s_frac(16) or ex1_s_frac(17); + ex1_clz02_enc4( 7) <= not ex1_s_frac(16) and ex1_s_frac(17); + + ex1_clz02_or ( 8) <= ex1_s_frac(18) or ex1_s_frac(19); + ex1_clz02_enc4( 8) <= not ex1_s_frac(18) and ex1_s_frac(19); + + ex1_clz02_or ( 9) <= ex1_s_frac(20) or ex1_s_frac(21); + ex1_clz02_enc4( 9) <= not ex1_s_frac(20) and ex1_s_frac(21); + + ex1_clz02_or (10) <= ex1_s_frac(22) or ex1_s_frac(23); + ex1_clz02_enc4(10) <= not ex1_s_frac(22) and ex1_s_frac(23); + + + ex1_clz04_or ( 0) <= ex1_clz02_or( 0) or ex1_clz02_or ( 1) ; + ex1_clz04_enc3( 0) <= not ex1_clz02_or( 0) and ex1_clz02_or ( 1) ; + ex1_clz04_enc4( 0) <= ex1_clz02_enc4( 0) or (not ex1_clz02_or( 0) and ex1_clz02_enc4( 1) ); + + ex1_clz04_or ( 1) <= ex1_clz02_or( 2) or ex1_clz02_or ( 3) ; + ex1_clz04_enc3( 1) <= not ex1_clz02_or( 2) and ex1_clz02_or ( 3) ; + ex1_clz04_enc4( 1) <= ex1_clz02_enc4( 2) or (not ex1_clz02_or( 2) and ex1_clz02_enc4( 3) ); + + ex1_clz04_or ( 2) <= ex1_clz02_or( 4) or ex1_clz02_or ( 5) ; + ex1_clz04_enc3( 2) <= not ex1_clz02_or( 4) and ex1_clz02_or ( 5) ; + ex1_clz04_enc4( 2) <= ex1_clz02_enc4( 4) or (not ex1_clz02_or( 4) and ex1_clz02_enc4( 5) ); + + ex1_clz04_or ( 3) <= ex1_clz02_or( 6) or ex1_clz02_or ( 7) ; + ex1_clz04_enc3( 3) <= not ex1_clz02_or( 6) and ex1_clz02_or ( 7) ; + ex1_clz04_enc4( 3) <= ex1_clz02_enc4( 6) or (not ex1_clz02_or( 6) and ex1_clz02_enc4( 7) ); + + ex1_clz04_or ( 4) <= ex1_clz02_or( 8) or ex1_clz02_or ( 9) ; + ex1_clz04_enc3( 4) <= not ex1_clz02_or( 8) and ex1_clz02_or ( 9) ; + ex1_clz04_enc4( 4) <= ex1_clz02_enc4( 8) or (not ex1_clz02_or( 8) and ex1_clz02_enc4( 9) ); + + ex1_clz04_or ( 5) <= ex1_clz02_or(10) ; + ex1_clz04_enc3( 5) <= tidn; + ex1_clz04_enc4( 5) <= ex1_clz02_enc4(10); + + + ex1_clz08_or ( 0) <= ex1_clz04_or( 0) or ex1_clz04_or ( 1) ; + ex1_clz08_enc2( 0) <= not ex1_clz04_or( 0) and ex1_clz04_or ( 1) ; + ex1_clz08_enc3( 0) <= ex1_clz04_enc3( 0) or (not ex1_clz04_or( 0) and ex1_clz04_enc3( 1) ); + ex1_clz08_enc4( 0) <= ex1_clz04_enc4( 0) or (not ex1_clz04_or( 0) and ex1_clz04_enc4( 1) ); + + ex1_clz08_or ( 1) <= ex1_clz04_or( 2) or ex1_clz04_or ( 3) ; + ex1_clz08_enc2( 1) <= not ex1_clz04_or( 2) and ex1_clz04_or ( 3) ; + ex1_clz08_enc3( 1) <= ex1_clz04_enc3( 2) or (not ex1_clz04_or( 2) and ex1_clz04_enc3( 3) ); + ex1_clz08_enc4( 1) <= ex1_clz04_enc4( 2) or (not ex1_clz04_or( 2) and ex1_clz04_enc4( 3) ); + + ex1_clz08_or ( 2) <= ex1_clz04_or( 4) or ex1_clz04_or ( 5) ; + ex1_clz08_enc2( 2) <= not ex1_clz04_or( 4) and ex1_clz04_or ( 5) ; + ex1_clz08_enc3( 2) <= ex1_clz04_enc3( 4) or (not ex1_clz04_or( 4) and ex1_clz04_enc3( 5) ); + ex1_clz08_enc4( 2) <= ex1_clz04_enc4( 4) or (not ex1_clz04_or( 4) and ex1_clz04_enc4( 5) ); + + + ex1_clz16_or ( 0) <= ex1_clz08_or( 0) or ex1_clz08_or ( 1) ; + ex1_clz16_enc1( 0) <= not ex1_clz08_or( 0) and ex1_clz08_or ( 1) ; + ex1_clz16_enc2( 0) <= ex1_clz08_enc2( 0) or (not ex1_clz08_or( 0) and ex1_clz08_enc2( 1) ); + ex1_clz16_enc3( 0) <= ex1_clz08_enc3( 0) or (not ex1_clz08_or( 0) and ex1_clz08_enc3( 1) ); + ex1_clz16_enc4( 0) <= ex1_clz08_enc4( 0) or (not ex1_clz08_or( 0) and ex1_clz08_enc4( 1) ); + + ex1_clz16_or ( 1) <= ex1_clz08_or( 2) ; + ex1_clz16_enc1( 1) <= tidn; + ex1_clz16_enc2( 1) <= ex1_clz08_enc2( 2) ; + ex1_clz16_enc3( 1) <= ex1_clz08_enc3( 2) ; + ex1_clz16_enc4( 1) <= ex1_clz08_enc4( 2) ; + + + ex1_sto_clz( 0) <= not ex1_clz16_or( 0) and ex1_clz16_or ( 1) ; + ex1_sto_clz( 1) <= ex1_clz16_enc1( 0) or (not ex1_clz16_or( 0) and ex1_clz16_enc1( 1) ); + ex1_sto_clz( 2) <= ex1_clz16_enc2( 0) or (not ex1_clz16_or( 0) and ex1_clz16_enc2( 1) ); + ex1_sto_clz( 3) <= ex1_clz16_enc3( 0) or (not ex1_clz16_or( 0) and ex1_clz16_enc3( 1) ); + ex1_sto_clz( 4) <= ex1_clz16_enc4( 0) or (not ex1_clz16_or( 0) and ex1_clz16_enc4( 1) ); + + ex1_any_edge <= ( ex1_clz16_or( 0) or ex1_clz16_or ( 1) ); + + + --//################################################### + --//# exponent for store dp + --//################################################### + -- exponent must be zero when input is zero x001 * !imp + + ex1_fixden <= ex1_s_expo(2) and not ex1_s_frac(0); -- sp denorm or zero + ex1_fixden_small <= ex1_s_expo(2) and not ex1_s_frac(0) and ex1_s_frac(1); + ex1_fixden_big <= ex1_s_expo(2) and not ex1_s_frac(0) and not ex1_s_frac(1); + +--ex1_std_fixden <= ex1_sto_dp and ex1_fixden ; -- x381 denorm + ex1_std_nonden <= ex1_sto_dp and not ex1_fixden ; + ex1_std_fixden_big <= ex1_sto_dp and ex1_fixden_big ; -- denorm more than 1 + ex1_std_fixden_small <= ex1_sto_dp and ex1_fixden_small ; -- denorm by 1 + ex1_std_nonbig <= ex1_sto_dp and not ex1_fixden_big; + + -- dp denorm/zero turn of expo lsb + -- sp denorm(1) goes to x380 (turn off lsb) + ex1_expo_nonden(1 to 10) <= ex1_s_expo(1 to 10) and (1 to 10=> ex1_std_nonbig ); + ex1_expo_nonden(11) <= ex1_s_expo(11) and ex1_s_frac(0) and ex1_std_nonden ; + + ex1_expo_fixden(1) <= tidn ; -- 011_011x_xxx + ex1_expo_fixden(2) <= ex1_any_edge; -- 011_011x_xxx + ex1_expo_fixden(3) <= ex1_any_edge; -- 011_011x_xxx + ex1_expo_fixden(4) <= tidn ; -- 011_011x_xxx + ex1_expo_fixden(5) <= ex1_any_edge; -- 011_011x_xxx + ex1_expo_fixden(6) <= ex1_any_edge; -- 011_011x_xxx + ex1_expo_fixden(7 to 11) <= not ex1_sto_clz(0 to 4) and (0 to 4 => ex1_any_edge) ; + + ex1_std_expo(1 to 11) <= + ( ex1_expo_nonden(1 to 11) ) or + ( ex1_expo_fixden(1 to 11) and (1 to 11=> ex1_std_fixden_big) ); + + --//######################################################################### + --//# shifting for store dp + --//######################################################################### + + ex1_std_nonden_wd <= ex1_std_nonden or ex1_sto_wd; + + ex1_std_frac_nrm(1 to 20) <= + ( ex1_s_frac( 2 to 21) and ( 1 to 20=> ex1_std_fixden_small) ) or + ( ex1_s_frac( 1 to 20) and ( 1 to 20=> ex1_std_nonden) ) ; + ex1_std_frac_nrm(21 to 52) <= -- stfiwx has a 32 bit result f[21:52] + ( (ex1_s_frac(22 to 52) & tidn) and (21 to 52=> ex1_std_fixden_small) ) or + ( ex1_s_frac(21 to 52) and (21 to 52=> ex1_std_nonden_wd) ) ; + + + ex1_std_lamt8_02 <= not ex1_sto_clz(0) and not ex1_sto_clz(1) ; -- 0 + 2 + ex1_std_lamt8_10 <= not ex1_sto_clz(0) and ex1_sto_clz(1) ; -- 8 + 2 + ex1_std_lamt8_18 <= ex1_sto_clz(0) and not ex1_sto_clz(1) ; --16 + 2 + + ex1_std_lamt2_0 <= not ex1_sto_clz(2) and not ex1_sto_clz(3) ; + ex1_std_lamt2_2 <= not ex1_sto_clz(2) and ex1_sto_clz(3) ; + ex1_std_lamt2_4 <= ex1_sto_clz(2) and not ex1_sto_clz(3) ; + ex1_std_lamt2_6 <= ex1_sto_clz(2) and ex1_sto_clz(3) ; + + ex1_std_lamt1_0 <= ex1_std_fixden_big and not ex1_sto_clz(4) ; + ex1_std_lamt1_1 <= ex1_std_fixden_big and ex1_sto_clz(4) ; + + + ex1_std_sh8(0 to 23) <= + ( ( ex1_s_frac( 2 to 23) & (0 to 1=> tidn) ) and (0 to 23=> ex1_std_lamt8_02 ) ) or + ( ( ex1_s_frac(10 to 23) & (0 to 9=> tidn) ) and (0 to 23=> ex1_std_lamt8_10 ) ) or + ( ( ex1_s_frac(18 to 23) & (0 to 17=> tidn) ) and (0 to 23=> ex1_std_lamt8_18 ) ) ; + ex1_std_sh2(0 to 23) <= + ( ex1_std_sh8(0 to 23) and (0 to 23=> ex1_std_lamt2_0) ) or + ( (ex1_std_sh8(2 to 23) & (0 to 1=> tidn) ) and (0 to 23=> ex1_std_lamt2_2) ) or + ( (ex1_std_sh8(4 to 23) & (0 to 3=> tidn) ) and (0 to 23=> ex1_std_lamt2_4) ) or + ( (ex1_std_sh8(6 to 23) & (0 to 5=> tidn) ) and (0 to 23=> ex1_std_lamt2_6) ) ; + ex1_std_frac_den(1 to 23) <= + ( ex1_std_sh2(1 to 23) and (1 to 23=> ex1_std_lamt1_0) ) or + ( (ex1_std_sh2(2 to 23) & tidn) and (1 to 23=> ex1_std_lamt1_1) ) ; + + + + --//################################################### + --//# final combinations + --//################################################### + + ex1_sto_data(0) <= ex1_s_sign and not ex1_sto_wd; -- sign bit + + ex1_sto_data(1 to 8) <= ex1_sts_expo(1 to 8) or + ex1_std_expo(1 to 8); + + ex1_sto_data(9 to 11) <= ex1_sts_frac(1 to 3) or + ex1_std_expo(9 to 11); + + ex1_sto_data(12 to 31) <= ex1_sts_frac(4 to 23) or + ex1_std_frac_nrm(1 to 20) or + ex1_std_frac_den(1 to 20) ; + + ex1_sto_data(32 to 34) <= ex1_std_frac_nrm(21 to 23) or --03 bits (includes stfwix) + ex1_std_frac_den(21 to 23) ; + + ex1_sto_data(35 to 63) <= ex1_std_frac_nrm(24 to 52) ; --29 bits (includes stfwix) + +--//############################################## +--//# EX2 latches +--//############################################## + + ex2_sto_lat: entity tri.tri_rlmreg_p generic map (width=> 73, expand_type => expand_type, needs_sreset => 0, ibuf => true) port map ( + forcee => forcee,--tidn, + delay_lclkr => delay_lclkr(2) ,--tidn, + mpw1_b => mpw1_b(2) ,--tidn, + mpw2_b => mpw2_b(0) ,--tidn, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => ex1_act, + vd => vdd, + gd => gnd, + scout => ex2_sto_so , + scin => ex2_sto_si , + ------------------- + din(0 to 63) => ex1_sto_data(0 to 63) , + din(64) => ex1_sto_sp , + din(65) => ex1_sto_sp , + din(66) => ex1_sto_sp , + din(67) => ex1_sto_sp , + din(68) => ex1_sto_wd , + din(69) => ex1_sto_wd , + din(70) => ex1_sto_wd , + din(71) => ex1_sto_wd , + din(72) => ex1_s_party_chick , + + dout(0 to 63) => ex2_sto_data(0 to 63) ,--LAT-- + dout(64) => ex2_sto_sp(0) ,--LAT-- + dout(65) => ex2_sto_sp(1) ,--LAT-- + dout(66) => ex2_sto_sp(2) ,--LAT-- + dout(67) => ex2_sto_sp(3) ,--LAT-- + dout(68) => ex2_sto_wd(0) ,--LAT-- + dout(69) => ex2_sto_wd(1) ,--LAT-- + dout(70) => ex2_sto_wd(2) ,--LAT-- + dout(71) => ex2_sto_wd(3) ,--LAT-- + dout(72) => ex2_s_party_chick );--LAT-- + + f_sto_ex2_s_parity_check <= ex2_s_party_chick ; + + + + + + ex1_s_party(0) <= ex1_s_sign xor f_fpr_ex1_s_expo_extra xor ex1_s_expo(1) xor ex1_s_expo(2) xor ex1_s_expo(3) xor + ex1_s_expo(4) xor ex1_s_expo(5) xor ex1_s_expo(6) xor ex1_s_expo(7) ; + ex1_s_party(1) <= ex1_s_expo(8) xor ex1_s_expo(9) xor ex1_s_expo(10) xor ex1_s_expo(11) xor ex1_s_frac(0) xor + ex1_s_frac(1) xor ex1_s_frac(2) xor ex1_s_frac(3) xor ex1_s_frac(4) ; + ex1_s_party(2) <= ex1_s_frac(5) xor ex1_s_frac(6) xor ex1_s_frac(7) xor ex1_s_frac(8) xor + ex1_s_frac(9) xor ex1_s_frac(10) xor ex1_s_frac(11) xor ex1_s_frac(12) ; + ex1_s_party(3) <= ex1_s_frac(13) xor ex1_s_frac(14) xor ex1_s_frac(15) xor ex1_s_frac(16) xor + ex1_s_frac(17) xor ex1_s_frac(18) xor ex1_s_frac(19) xor ex1_s_frac(20) ; + ex1_s_party(4) <= ex1_s_frac(21) xor ex1_s_frac(22) xor ex1_s_frac(23) xor ex1_s_frac(24) xor + ex1_s_frac(25) xor ex1_s_frac(26) xor ex1_s_frac(27) xor ex1_s_frac(28) ; + ex1_s_party(5) <= ex1_s_frac(29) xor ex1_s_frac(30) xor ex1_s_frac(31) xor ex1_s_frac(32) xor + ex1_s_frac(33) xor ex1_s_frac(34) xor ex1_s_frac(35) xor ex1_s_frac(36) ; + ex1_s_party(6) <= ex1_s_frac(37) xor ex1_s_frac(38) xor ex1_s_frac(39) xor ex1_s_frac(40) xor + ex1_s_frac(41) xor ex1_s_frac(42) xor ex1_s_frac(43) xor ex1_s_frac(44) ; + ex1_s_party(7) <= ex1_s_frac(45) xor ex1_s_frac(46) xor ex1_s_frac(47) xor ex1_s_frac(48) xor + ex1_s_frac(49) xor ex1_s_frac(50) xor ex1_s_frac(51) xor ex1_s_frac(52) ; + + + ex1_s_party_chick <= (ex1_s_party(0) xor f_fpr_ex1_s_par(0) ) or + (ex1_s_party(1) xor f_fpr_ex1_s_par(1) ) or + (ex1_s_party(2) xor f_fpr_ex1_s_par(2) ) or + (ex1_s_party(3) xor f_fpr_ex1_s_par(3) ) or + (ex1_s_party(4) xor f_fpr_ex1_s_par(4) ) or + (ex1_s_party(5) xor f_fpr_ex1_s_par(5) ) or + (ex1_s_party(6) xor f_fpr_ex1_s_par(6) ) or + (ex1_s_party(7) xor f_fpr_ex1_s_par(7) ) ; + + + +u_rot0_0: ex2_sto_data_rot0_b(0) <= not( ex2_sto_data(0) and not ex2_sto_wd(0) ); +u_rot0_1: ex2_sto_data_rot0_b(1) <= not( ex2_sto_data(1) and not ex2_sto_wd(0) ); +u_rot0_2: ex2_sto_data_rot0_b(2) <= not( ex2_sto_data(2) and not ex2_sto_wd(0) ); +u_rot0_3: ex2_sto_data_rot0_b(3) <= not( ex2_sto_data(3) and not ex2_sto_wd(0) ); +u_rot0_4: ex2_sto_data_rot0_b(4) <= not( ex2_sto_data(4) and not ex2_sto_wd(0) ); +u_rot0_5: ex2_sto_data_rot0_b(5) <= not( ex2_sto_data(5) and not ex2_sto_wd(0) ); +u_rot0_6: ex2_sto_data_rot0_b(6) <= not( ex2_sto_data(6) and not ex2_sto_wd(0) ); +u_rot0_7: ex2_sto_data_rot0_b(7) <= not( ex2_sto_data(7) and not ex2_sto_wd(0) ); +u_rot0_8: ex2_sto_data_rot0_b(8) <= not( ex2_sto_data(8) and not ex2_sto_wd(1) ); +u_rot0_9: ex2_sto_data_rot0_b(9) <= not( ex2_sto_data(9) and not ex2_sto_wd(1) ); +u_rot0_10: ex2_sto_data_rot0_b(10) <= not( ex2_sto_data(10) and not ex2_sto_wd(1) ); +u_rot0_11: ex2_sto_data_rot0_b(11) <= not( ex2_sto_data(11) and not ex2_sto_wd(1) ); +u_rot0_12: ex2_sto_data_rot0_b(12) <= not( ex2_sto_data(12) and not ex2_sto_wd(1) ); +u_rot0_13: ex2_sto_data_rot0_b(13) <= not( ex2_sto_data(13) and not ex2_sto_wd(1) ); +u_rot0_14: ex2_sto_data_rot0_b(14) <= not( ex2_sto_data(14) and not ex2_sto_wd(1) ); +u_rot0_15: ex2_sto_data_rot0_b(15) <= not( ex2_sto_data(15) and not ex2_sto_wd(1) ); +u_rot0_16: ex2_sto_data_rot0_b(16) <= not( ex2_sto_data(16) and not ex2_sto_wd(2) ); +u_rot0_17: ex2_sto_data_rot0_b(17) <= not( ex2_sto_data(17) and not ex2_sto_wd(2) ); +u_rot0_18: ex2_sto_data_rot0_b(18) <= not( ex2_sto_data(18) and not ex2_sto_wd(2) ); +u_rot0_19: ex2_sto_data_rot0_b(19) <= not( ex2_sto_data(19) and not ex2_sto_wd(2) ); +u_rot0_20: ex2_sto_data_rot0_b(20) <= not( ex2_sto_data(20) and not ex2_sto_wd(2) ); +u_rot0_21: ex2_sto_data_rot0_b(21) <= not( ex2_sto_data(21) and not ex2_sto_wd(2) ); +u_rot0_22: ex2_sto_data_rot0_b(22) <= not( ex2_sto_data(22) and not ex2_sto_wd(2) ); +u_rot0_23: ex2_sto_data_rot0_b(23) <= not( ex2_sto_data(23) and not ex2_sto_wd(2) ); +u_rot0_24: ex2_sto_data_rot0_b(24) <= not( ex2_sto_data(24) and not ex2_sto_wd(3) ); +u_rot0_25: ex2_sto_data_rot0_b(25) <= not( ex2_sto_data(25) and not ex2_sto_wd(3) ); +u_rot0_26: ex2_sto_data_rot0_b(26) <= not( ex2_sto_data(26) and not ex2_sto_wd(3) ); +u_rot0_27: ex2_sto_data_rot0_b(27) <= not( ex2_sto_data(27) and not ex2_sto_wd(3) ); +u_rot0_28: ex2_sto_data_rot0_b(28) <= not( ex2_sto_data(28) and not ex2_sto_wd(3) ); +u_rot0_29: ex2_sto_data_rot0_b(29) <= not( ex2_sto_data(29) and not ex2_sto_wd(3) ); +u_rot0_30: ex2_sto_data_rot0_b(30) <= not( ex2_sto_data(30) and not ex2_sto_wd(3) ); +u_rot0_31: ex2_sto_data_rot0_b(31) <= not( ex2_sto_data(31) and not ex2_sto_wd(3) ); +u_rot0_32: ex2_sto_data_rot0_b(32) <= not( ex2_sto_data(0) and ex2_sto_sp(0) ); +u_rot0_33: ex2_sto_data_rot0_b(33) <= not( ex2_sto_data(1) and ex2_sto_sp(0) ); +u_rot0_34: ex2_sto_data_rot0_b(34) <= not( ex2_sto_data(2) and ex2_sto_sp(0) ); +u_rot0_35: ex2_sto_data_rot0_b(35) <= not( ex2_sto_data(3) and ex2_sto_sp(0) ); +u_rot0_36: ex2_sto_data_rot0_b(36) <= not( ex2_sto_data(4) and ex2_sto_sp(0) ); +u_rot0_37: ex2_sto_data_rot0_b(37) <= not( ex2_sto_data(5) and ex2_sto_sp(0) ); +u_rot0_38: ex2_sto_data_rot0_b(38) <= not( ex2_sto_data(6) and ex2_sto_sp(0) ); +u_rot0_39: ex2_sto_data_rot0_b(39) <= not( ex2_sto_data(7) and ex2_sto_sp(0) ); +u_rot0_40: ex2_sto_data_rot0_b(40) <= not( ex2_sto_data(8) and ex2_sto_sp(1) ); +u_rot0_41: ex2_sto_data_rot0_b(41) <= not( ex2_sto_data(9) and ex2_sto_sp(1) ); +u_rot0_42: ex2_sto_data_rot0_b(42) <= not( ex2_sto_data(10) and ex2_sto_sp(1) ); +u_rot0_43: ex2_sto_data_rot0_b(43) <= not( ex2_sto_data(11) and ex2_sto_sp(1) ); +u_rot0_44: ex2_sto_data_rot0_b(44) <= not( ex2_sto_data(12) and ex2_sto_sp(1) ); +u_rot0_45: ex2_sto_data_rot0_b(45) <= not( ex2_sto_data(13) and ex2_sto_sp(1) ); +u_rot0_46: ex2_sto_data_rot0_b(46) <= not( ex2_sto_data(14) and ex2_sto_sp(1) ); +u_rot0_47: ex2_sto_data_rot0_b(47) <= not( ex2_sto_data(15) and ex2_sto_sp(1) ); +u_rot0_48: ex2_sto_data_rot0_b(48) <= not( ex2_sto_data(16) and ex2_sto_sp(2) ); +u_rot0_49: ex2_sto_data_rot0_b(49) <= not( ex2_sto_data(17) and ex2_sto_sp(2) ); +u_rot0_50: ex2_sto_data_rot0_b(50) <= not( ex2_sto_data(18) and ex2_sto_sp(2) ); +u_rot0_51: ex2_sto_data_rot0_b(51) <= not( ex2_sto_data(19) and ex2_sto_sp(2) ); +u_rot0_52: ex2_sto_data_rot0_b(52) <= not( ex2_sto_data(20) and ex2_sto_sp(2) ); +u_rot0_53: ex2_sto_data_rot0_b(53) <= not( ex2_sto_data(21) and ex2_sto_sp(2) ); +u_rot0_54: ex2_sto_data_rot0_b(54) <= not( ex2_sto_data(22) and ex2_sto_sp(2) ); +u_rot0_55: ex2_sto_data_rot0_b(55) <= not( ex2_sto_data(23) and ex2_sto_sp(2) ); +u_rot0_56: ex2_sto_data_rot0_b(56) <= not( ex2_sto_data(24) and ex2_sto_sp(3) ); +u_rot0_57: ex2_sto_data_rot0_b(57) <= not( ex2_sto_data(25) and ex2_sto_sp(3) ); +u_rot0_58: ex2_sto_data_rot0_b(58) <= not( ex2_sto_data(26) and ex2_sto_sp(3) ); +u_rot0_59: ex2_sto_data_rot0_b(59) <= not( ex2_sto_data(27) and ex2_sto_sp(3) ); +u_rot0_60: ex2_sto_data_rot0_b(60) <= not( ex2_sto_data(28) and ex2_sto_sp(3) ); +u_rot0_61: ex2_sto_data_rot0_b(61) <= not( ex2_sto_data(29) and ex2_sto_sp(3) ); +u_rot0_62: ex2_sto_data_rot0_b(62) <= not( ex2_sto_data(30) and ex2_sto_sp(3) ); +u_rot0_63: ex2_sto_data_rot0_b(63) <= not( ex2_sto_data(31) and ex2_sto_sp(3) ); + + +u_rot1_0: ex2_sto_data_rot1_b(0) <= not( ex2_sto_data(32) and ex2_sto_wd(0) ); +u_rot1_1: ex2_sto_data_rot1_b(1) <= not( ex2_sto_data(33) and ex2_sto_wd(0) ); +u_rot1_2: ex2_sto_data_rot1_b(2) <= not( ex2_sto_data(34) and ex2_sto_wd(0) ); +u_rot1_3: ex2_sto_data_rot1_b(3) <= not( ex2_sto_data(35) and ex2_sto_wd(0) ); +u_rot1_4: ex2_sto_data_rot1_b(4) <= not( ex2_sto_data(36) and ex2_sto_wd(0) ); +u_rot1_5: ex2_sto_data_rot1_b(5) <= not( ex2_sto_data(37) and ex2_sto_wd(0) ); +u_rot1_6: ex2_sto_data_rot1_b(6) <= not( ex2_sto_data(38) and ex2_sto_wd(0) ); +u_rot1_7: ex2_sto_data_rot1_b(7) <= not( ex2_sto_data(39) and ex2_sto_wd(0) ); +u_rot1_8: ex2_sto_data_rot1_b(8) <= not( ex2_sto_data(40) and ex2_sto_wd(1) ); +u_rot1_9: ex2_sto_data_rot1_b(9) <= not( ex2_sto_data(41) and ex2_sto_wd(1) ); +u_rot1_10: ex2_sto_data_rot1_b(10) <= not( ex2_sto_data(42) and ex2_sto_wd(1) ); +u_rot1_11: ex2_sto_data_rot1_b(11) <= not( ex2_sto_data(43) and ex2_sto_wd(1) ); +u_rot1_12: ex2_sto_data_rot1_b(12) <= not( ex2_sto_data(44) and ex2_sto_wd(1) ); +u_rot1_13: ex2_sto_data_rot1_b(13) <= not( ex2_sto_data(45) and ex2_sto_wd(1) ); +u_rot1_14: ex2_sto_data_rot1_b(14) <= not( ex2_sto_data(46) and ex2_sto_wd(1) ); +u_rot1_15: ex2_sto_data_rot1_b(15) <= not( ex2_sto_data(47) and ex2_sto_wd(1) ); +u_rot1_16: ex2_sto_data_rot1_b(16) <= not( ex2_sto_data(48) and ex2_sto_wd(2) ); +u_rot1_17: ex2_sto_data_rot1_b(17) <= not( ex2_sto_data(49) and ex2_sto_wd(2) ); +u_rot1_18: ex2_sto_data_rot1_b(18) <= not( ex2_sto_data(50) and ex2_sto_wd(2) ); +u_rot1_19: ex2_sto_data_rot1_b(19) <= not( ex2_sto_data(51) and ex2_sto_wd(2) ); +u_rot1_20: ex2_sto_data_rot1_b(20) <= not( ex2_sto_data(52) and ex2_sto_wd(2) ); +u_rot1_21: ex2_sto_data_rot1_b(21) <= not( ex2_sto_data(53) and ex2_sto_wd(2) ); +u_rot1_22: ex2_sto_data_rot1_b(22) <= not( ex2_sto_data(54) and ex2_sto_wd(2) ); +u_rot1_23: ex2_sto_data_rot1_b(23) <= not( ex2_sto_data(55) and ex2_sto_wd(2) ); +u_rot1_24: ex2_sto_data_rot1_b(24) <= not( ex2_sto_data(56) and ex2_sto_wd(3) ); +u_rot1_25: ex2_sto_data_rot1_b(25) <= not( ex2_sto_data(57) and ex2_sto_wd(3) ); +u_rot1_26: ex2_sto_data_rot1_b(26) <= not( ex2_sto_data(58) and ex2_sto_wd(3) ); +u_rot1_27: ex2_sto_data_rot1_b(27) <= not( ex2_sto_data(59) and ex2_sto_wd(3) ); +u_rot1_28: ex2_sto_data_rot1_b(28) <= not( ex2_sto_data(60) and ex2_sto_wd(3) ); +u_rot1_29: ex2_sto_data_rot1_b(29) <= not( ex2_sto_data(61) and ex2_sto_wd(3) ); +u_rot1_30: ex2_sto_data_rot1_b(30) <= not( ex2_sto_data(62) and ex2_sto_wd(3) ); +u_rot1_31: ex2_sto_data_rot1_b(31) <= not( ex2_sto_data(63) and ex2_sto_wd(3) ); +u_rot1_32: ex2_sto_data_rot1_b(32) <= not( ex2_sto_data(32) and not ex2_sto_sp(0) ); +u_rot1_33: ex2_sto_data_rot1_b(33) <= not( ex2_sto_data(33) and not ex2_sto_sp(0) ); +u_rot1_34: ex2_sto_data_rot1_b(34) <= not( ex2_sto_data(34) and not ex2_sto_sp(0) ); +u_rot1_35: ex2_sto_data_rot1_b(35) <= not( ex2_sto_data(35) and not ex2_sto_sp(0) ); +u_rot1_36: ex2_sto_data_rot1_b(36) <= not( ex2_sto_data(36) and not ex2_sto_sp(0) ); +u_rot1_37: ex2_sto_data_rot1_b(37) <= not( ex2_sto_data(37) and not ex2_sto_sp(0) ); +u_rot1_38: ex2_sto_data_rot1_b(38) <= not( ex2_sto_data(38) and not ex2_sto_sp(0) ); +u_rot1_39: ex2_sto_data_rot1_b(39) <= not( ex2_sto_data(39) and not ex2_sto_sp(0) ); +u_rot1_40: ex2_sto_data_rot1_b(40) <= not( ex2_sto_data(40) and not ex2_sto_sp(1) ); +u_rot1_41: ex2_sto_data_rot1_b(41) <= not( ex2_sto_data(41) and not ex2_sto_sp(1) ); +u_rot1_42: ex2_sto_data_rot1_b(42) <= not( ex2_sto_data(42) and not ex2_sto_sp(1) ); +u_rot1_43: ex2_sto_data_rot1_b(43) <= not( ex2_sto_data(43) and not ex2_sto_sp(1) ); +u_rot1_44: ex2_sto_data_rot1_b(44) <= not( ex2_sto_data(44) and not ex2_sto_sp(1) ); +u_rot1_45: ex2_sto_data_rot1_b(45) <= not( ex2_sto_data(45) and not ex2_sto_sp(1) ); +u_rot1_46: ex2_sto_data_rot1_b(46) <= not( ex2_sto_data(46) and not ex2_sto_sp(1) ); +u_rot1_47: ex2_sto_data_rot1_b(47) <= not( ex2_sto_data(47) and not ex2_sto_sp(1) ); +u_rot1_48: ex2_sto_data_rot1_b(48) <= not( ex2_sto_data(48) and not ex2_sto_sp(2) ); +u_rot1_49: ex2_sto_data_rot1_b(49) <= not( ex2_sto_data(49) and not ex2_sto_sp(2) ); +u_rot1_50: ex2_sto_data_rot1_b(50) <= not( ex2_sto_data(50) and not ex2_sto_sp(2) ); +u_rot1_51: ex2_sto_data_rot1_b(51) <= not( ex2_sto_data(51) and not ex2_sto_sp(2) ); +u_rot1_52: ex2_sto_data_rot1_b(52) <= not( ex2_sto_data(52) and not ex2_sto_sp(2) ); +u_rot1_53: ex2_sto_data_rot1_b(53) <= not( ex2_sto_data(53) and not ex2_sto_sp(2) ); +u_rot1_54: ex2_sto_data_rot1_b(54) <= not( ex2_sto_data(54) and not ex2_sto_sp(2) ); +u_rot1_55: ex2_sto_data_rot1_b(55) <= not( ex2_sto_data(55) and not ex2_sto_sp(2) ); +u_rot1_56: ex2_sto_data_rot1_b(56) <= not( ex2_sto_data(56) and not ex2_sto_sp(3) ); +u_rot1_57: ex2_sto_data_rot1_b(57) <= not( ex2_sto_data(57) and not ex2_sto_sp(3) ); +u_rot1_58: ex2_sto_data_rot1_b(58) <= not( ex2_sto_data(58) and not ex2_sto_sp(3) ); +u_rot1_59: ex2_sto_data_rot1_b(59) <= not( ex2_sto_data(59) and not ex2_sto_sp(3) ); +u_rot1_60: ex2_sto_data_rot1_b(60) <= not( ex2_sto_data(60) and not ex2_sto_sp(3) ); +u_rot1_61: ex2_sto_data_rot1_b(61) <= not( ex2_sto_data(61) and not ex2_sto_sp(3) ); +u_rot1_62: ex2_sto_data_rot1_b(62) <= not( ex2_sto_data(62) and not ex2_sto_sp(3) ); +u_rot1_63: ex2_sto_data_rot1_b(63) <= not( ex2_sto_data(63) and not ex2_sto_sp(3) ); + + +u_rot: f_sto_ex2_sto_data(0 to 63) <= not( ex2_sto_data_rot0_b(0 to 63) and ex2_sto_data_rot1_b(0 to 63) ); + + + + +--//############################################ +--//# scan +--//############################################ + + ex1_sins_si (0 to 2) <= ex1_sins_so (1 to 2) & f_sto_si ; + ex1_sop_si (0 to 64) <= ex1_sop_so (1 to 64) & ex1_sins_so (0) ; + ex2_sto_si (0 to 72) <= ex2_sto_so (1 to 72) & ex1_sop_so (0) ; + act_si (0 to 3 ) <= act_so ( 1 to 3) & ex2_sto_so (0); + f_sto_so <= act_so (0) ; -- xor dc_scan_diag; + + +end; -- fuq_sto ARCHITECTURE diff --git a/rel/src/vhdl/work/fuq_tblexp.vhdl b/rel/src/vhdl/work/fuq_tblexp.vhdl new file mode 100644 index 0000000..e2a4542 --- /dev/null +++ b/rel/src/vhdl/work/fuq_tblexp.vhdl @@ -0,0 +1,706 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + + +ENTITY fuq_tblexp IS +generic( + expand_type : integer := 2 ); -- 0 - ibm tech, 1 - other ); +PORT( + vdd :inout power_logic; + gnd :inout power_logic; + clkoff_b :in std_ulogic; -- tiup + act_dis :in std_ulogic; -- ??tidn?? + flush :in std_ulogic; -- ??tidn?? + delay_lclkr :in std_ulogic_vector(2 to 3); -- tidn, + mpw1_b :in std_ulogic_vector(2 to 3); -- tidn, + mpw2_b :in std_ulogic_vector(0 to 0); -- tidn, + sg_1 :in std_ulogic; + thold_1 :in std_ulogic; + fpu_enable :in std_ulogic; --dc_act + nclk :in clk_logic; + + si :in std_ulogic ;-- perv + so :out std_ulogic ;-- perv + ex1_act_b :in std_ulogic ;-- act + + f_pic_ex2_ue1 :in std_ulogic; + f_pic_ex2_sp_b :in std_ulogic; + f_pic_ex2_est_recip :in std_ulogic; + f_pic_ex2_est_rsqrt :in std_ulogic; + f_eie_ex2_tbl_expo :in std_ulogic_vector(1 to 13); + f_fmt_ex2_lu_den_recip :in std_ulogic ; + f_fmt_ex2_lu_den_rsqrto :in std_ulogic ; + + f_tbe_ex3_recip_ue1 :out std_ulogic ; + f_tbe_ex3_lu_sh :out std_ulogic ; + f_tbe_ex3_match_en_sp :out std_ulogic ; + f_tbe_ex3_match_en_dp :out std_ulogic ; + f_tbe_ex3_recip_2046 :out std_ulogic ; + f_tbe_ex3_recip_2045 :out std_ulogic ; + f_tbe_ex3_recip_2044 :out std_ulogic ; + f_tbe_ex3_may_ov :out std_ulogic ; + f_tbe_ex3_res_expo :out std_ulogic_vector(1 to 13) -- to rounder + +); -- end ports + + +end fuq_tblexp; -- ENTITY + + +architecture fuq_tblexp of fuq_tblexp is + + constant tiup :std_ulogic := '1'; + constant tidn :std_ulogic := '0'; + + signal thold_0_b, thold_0, forcee, sg_0 : std_ulogic; + signal act_spare_unused :std_ulogic_vector(0 to 3); + signal ex2_act :std_ulogic; + signal act_so , act_si :std_ulogic_vector(0 to 4); + signal ex3_expo_so , ex3_expo_si :std_ulogic_vector(0 to 19); + signal ex2_res_expo :std_ulogic_vector(1 to 13); + signal ex3_res_expo :std_ulogic_vector(1 to 13); + signal ex3_recip_2044, ex2_recip_2044, ex2_recip_ue1 :std_ulogic; + signal ex3_recip_2045, ex2_recip_2045, ex3_recip_ue1 :std_ulogic; + signal ex3_recip_2046, ex2_recip_2046 :std_ulogic; + signal ex3_force_expo_den :std_ulogic; + + signal ex2_b_expo_adj_b :std_ulogic_vector(1 to 13); + signal ex2_b_expo_adj :std_ulogic_vector(1 to 13); + signal ex2_recip_k :std_ulogic_vector(1 to 13); + signal ex2_recip_p :std_ulogic_vector(1 to 13); + signal ex2_recip_g :std_ulogic_vector(2 to 13); + signal ex2_recip_t :std_ulogic_vector(2 to 12); + signal ex2_recip_c :std_ulogic_vector(2 to 13); + signal ex2_recip_expo :std_ulogic_vector(1 to 13); + signal ex2_rsqrt_k :std_ulogic_vector(1 to 13); + signal ex2_rsqrt_p :std_ulogic_vector(1 to 13); + signal ex2_rsqrt_g :std_ulogic_vector(2 to 13); + signal ex2_rsqrt_t :std_ulogic_vector(2 to 12); + signal ex2_rsqrt_c :std_ulogic_vector(2 to 13); + signal ex2_rsqrt_expo :std_ulogic_vector(1 to 13); + signal ex2_rsqrt_bsh_b :std_ulogic_vector(1 to 13); + + signal ex2_recip_g2 :std_ulogic_vector(2 to 13); + signal ex2_recip_t2 :std_ulogic_vector(2 to 11); + signal ex2_recip_g4 :std_ulogic_vector(2 to 13); + signal ex2_recip_t4 :std_ulogic_vector(2 to 9); + signal ex2_recip_g8 :std_ulogic_vector(2 to 13); + signal ex2_recip_t8 :std_ulogic_vector(2 to 5); + + signal ex2_rsqrt_g2 :std_ulogic_vector(2 to 13); + signal ex2_rsqrt_t2 :std_ulogic_vector(2 to 11); + signal ex2_rsqrt_g4 :std_ulogic_vector(2 to 13); + signal ex2_rsqrt_t4 :std_ulogic_vector(2 to 9); + signal ex2_rsqrt_g8 :std_ulogic_vector(2 to 13); + signal ex2_rsqrt_t8 :std_ulogic_vector(2 to 5); + signal ex1_act :std_ulogic; + + signal ex2_lu_sh, ex3_lu_sh :std_ulogic; + signal ex3_res_expo_c, ex3_res_expo_g8_b, ex3_res_expo_g4, ex3_res_expo_g2_b :std_ulogic_vector(2 to 13); + signal ex3_res_decr, ex3_res_expo_b :std_ulogic_vector(1 to 13); + signal ex3_decr_expo :std_ulogic; + + signal ex2_mid_match_ifsp, ex2_mid_match_ifdp :std_ulogic; + signal ex2_match_en_dp, ex2_match_en_sp :std_ulogic; + signal ex3_match_en_dp, ex3_match_en_sp :std_ulogic; + signal ex2_com_match :std_ulogic; + signal ex3_recip_2044_dp, ex3_recip_2045_dp, ex3_recip_2046_dp :std_ulogic; + + + + +begin + +--//############################################ +--//# pervasive +--//############################################ + + thold_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => thold_1, + q(0) => thold_0 ); + + sg_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => sg_1 , + q(0) => sg_0 ); + + + lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map ( + clkoff_b => clkoff_b, + thold => thold_0, + sg => sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => thold_0_b ); + + + + + +--//############################################ +--//# ACT LATCHES +--//############################################ + + ex1_act <= not ex1_act_b ; + + act_lat: tri_rlmreg_p generic map (width=> 5, expand_type => expand_type) port map ( + forcee => forcee,--tidn, + delay_lclkr => delay_lclkr(2) ,--tidn, + mpw1_b => mpw1_b(2) ,--tidn, + mpw2_b => mpw2_b(0) ,--tidn, + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => fpu_enable, + scout => act_so , + scin => act_si , + ------------------- + din(0) => act_spare_unused(0), + din(1) => act_spare_unused(1), + din(2) => ex1_act, + din(3) => act_spare_unused(2), + din(4) => act_spare_unused(3), + ------------------- + dout(0) => act_spare_unused(0), + dout(1) => act_spare_unused(1), + dout(2) => ex2_act, + dout(3) => act_spare_unused(2), + dout(4) => act_spare_unused(3) ); + + + + +--//############################################## +--//# EX2 logic +--//############################################## + -- 1* 2 3 4 5* 6 7 8 9* 10 11 12 13* + -- * * * * + -- 0 B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 sqrt_q0 + -- 0 0 1 1 1 1 1 1 1 1 1 1 0 + -- * * * * + -- !B01 !B02 !B03 !B04 !B05 !B06 !B07 !B08 !B09 !B10 !B11 !B12 !B13 fres + -- 0 0 1 1 1 1 1 1 1 1 1 1 0 + -- * * * * + -- 1 !B01 !B02 !B03 !B04 !B05 !B06 !B07 !B08 !B09 !B10 !B11 !B12 rsqrte + -- 0 0 1 0 1 1 1 1 1 1 1 1 !B13 + -- * * * * + ------------------------------------------------------------------------------- + -- 1 !B01 !B02 !B03 !B04 !B05 !B06 !B07 !B08 !B09 !B10 !B11 !B12 rsqrte + -- 0 0 1 0 1 1 1 1 1 1 1 1 (!c5 +!B13 +<1>) + -- 1 1 1 1 1 1 1 1 !c0 !c1 !c2 !c3 !c4 + -- + + -- !c5 + !b13 + <1> | or xnor | or+xnor => put into LSB position + --------------------+-----------+-------- + -- 0 0 | 0 1 | 1+0 + -- 0 1 | 1 0 | 1+0 + -- 1 0 | 1 0 | 1+0 + -- 1 1 | 1 1 | 1+1 + + --//#-------------------------------------------- + --//# first generate B - clz (upper half should be carry select) + --//#---------------------------------------------- + --//# upper half should be carry select decrementer + + ex2_b_expo_adj(1 to 13) <= f_eie_ex2_tbl_expo(1 to 13); + ex2_b_expo_adj_b(1 to 13) <= not ex2_b_expo_adj(1 to 13); + + + --//#-------------------------------------------- + --//# adder for !(B-clz) + K_res + --//#-------------------------------------------- + -- 1 2 3 4 5 6 7 8 9 10 11 12 13 + -- !B01 !B02 !B03 !B04 !B05 !B06 !B07 !B08 !B09 !B10 !B11 !B12 !B13 fres + -- 0 0 1 1 1 1 1 1 1 1 1 1 0 + + ex2_recip_k(1 to 13) <= (1 to 2=> tidn) & (3 to 12=> tiup) & tidn ; + + ex2_recip_p(1 to 13) <= ex2_recip_k(1 to 13) xor ex2_b_expo_adj_b(1 to 13) ; + ex2_recip_g(2 to 13) <= ex2_recip_k(2 to 13) and ex2_b_expo_adj_b(2 to 13) ; + ex2_recip_t(2 to 12) <= ex2_recip_k(2 to 12) or ex2_b_expo_adj_b(2 to 12) ; + + ex2_recip_g2(13) <= ex2_recip_g(13); + ex2_recip_g2(12) <= ex2_recip_g(12) or (ex2_recip_t(12) and ex2_recip_g(13) ); + ex2_recip_g2(11) <= ex2_recip_g(11) or (ex2_recip_t(11) and ex2_recip_g(12) ); + ex2_recip_g2(10) <= ex2_recip_g(10) or (ex2_recip_t(10) and ex2_recip_g(11) ); + ex2_recip_g2( 9) <= ex2_recip_g( 9) or (ex2_recip_t( 9) and ex2_recip_g(10) ); + ex2_recip_g2( 8) <= ex2_recip_g( 8) or (ex2_recip_t( 8) and ex2_recip_g( 9) ); + ex2_recip_g2( 7) <= ex2_recip_g( 7) or (ex2_recip_t( 7) and ex2_recip_g( 8) ); + ex2_recip_g2( 6) <= ex2_recip_g( 6) or (ex2_recip_t( 6) and ex2_recip_g( 7) ); + ex2_recip_g2( 5) <= ex2_recip_g( 5) or (ex2_recip_t( 5) and ex2_recip_g( 6) ); + ex2_recip_g2( 4) <= ex2_recip_g( 4) or (ex2_recip_t( 4) and ex2_recip_g( 5) ); + ex2_recip_g2( 3) <= ex2_recip_g( 3) or (ex2_recip_t( 3) and ex2_recip_g( 4) ); + ex2_recip_g2( 2) <= ex2_recip_g( 2) or (ex2_recip_t( 2) and ex2_recip_g( 3) ); + + ex2_recip_t2(11) <= (ex2_recip_t(11) and ex2_recip_t(12) ); + ex2_recip_t2(10) <= (ex2_recip_t(10) and ex2_recip_t(11) ); + ex2_recip_t2( 9) <= (ex2_recip_t( 9) and ex2_recip_t(10) ); + ex2_recip_t2( 8) <= (ex2_recip_t( 8) and ex2_recip_t( 9) ); + ex2_recip_t2( 7) <= (ex2_recip_t( 7) and ex2_recip_t( 8) ); + ex2_recip_t2( 6) <= (ex2_recip_t( 6) and ex2_recip_t( 7) ); + ex2_recip_t2( 5) <= (ex2_recip_t( 5) and ex2_recip_t( 6) ); + ex2_recip_t2( 4) <= (ex2_recip_t( 4) and ex2_recip_t( 5) ); + ex2_recip_t2( 3) <= (ex2_recip_t( 3) and ex2_recip_t( 4) ); + ex2_recip_t2( 2) <= (ex2_recip_t( 2) and ex2_recip_t( 3) ); + + ex2_recip_g4(13) <= ex2_recip_g2(13); + ex2_recip_g4(12) <= ex2_recip_g2(12); + ex2_recip_g4(11) <= ex2_recip_g2(11) or (ex2_recip_t2(11) and ex2_recip_g2(13) ); + ex2_recip_g4(10) <= ex2_recip_g2(10) or (ex2_recip_t2(10) and ex2_recip_g2(12) ); + ex2_recip_g4( 9) <= ex2_recip_g2( 9) or (ex2_recip_t2( 9) and ex2_recip_g2(11) ); + ex2_recip_g4( 8) <= ex2_recip_g2( 8) or (ex2_recip_t2( 8) and ex2_recip_g2(10) ); + ex2_recip_g4( 7) <= ex2_recip_g2( 7) or (ex2_recip_t2( 7) and ex2_recip_g2( 9) ); + ex2_recip_g4( 6) <= ex2_recip_g2( 6) or (ex2_recip_t2( 6) and ex2_recip_g2( 8) ); + ex2_recip_g4( 5) <= ex2_recip_g2( 5) or (ex2_recip_t2( 5) and ex2_recip_g2( 7) ); + ex2_recip_g4( 4) <= ex2_recip_g2( 4) or (ex2_recip_t2( 4) and ex2_recip_g2( 6) ); + ex2_recip_g4( 3) <= ex2_recip_g2( 3) or (ex2_recip_t2( 3) and ex2_recip_g2( 5) ); + ex2_recip_g4( 2) <= ex2_recip_g2( 2) or (ex2_recip_t2( 2) and ex2_recip_g2( 4) ); + + ex2_recip_t4( 9) <= (ex2_recip_t2( 9) and ex2_recip_t2(11) ); + ex2_recip_t4( 8) <= (ex2_recip_t2( 8) and ex2_recip_t2(10) ); + ex2_recip_t4( 7) <= (ex2_recip_t2( 7) and ex2_recip_t2( 9) ); + ex2_recip_t4( 6) <= (ex2_recip_t2( 6) and ex2_recip_t2( 8) ); + ex2_recip_t4( 5) <= (ex2_recip_t2( 5) and ex2_recip_t2( 7) ); + ex2_recip_t4( 4) <= (ex2_recip_t2( 4) and ex2_recip_t2( 6) ); + ex2_recip_t4( 3) <= (ex2_recip_t2( 3) and ex2_recip_t2( 5) ); + ex2_recip_t4( 2) <= (ex2_recip_t2( 2) and ex2_recip_t2( 4) ); + + ex2_recip_g8(13) <= ex2_recip_g4(13); + ex2_recip_g8(12) <= ex2_recip_g4(12); + ex2_recip_g8(11) <= ex2_recip_g4(11); + ex2_recip_g8(10) <= ex2_recip_g4(10); + ex2_recip_g8( 9) <= ex2_recip_g4( 9) or (ex2_recip_t4( 9) and ex2_recip_g4(13) ); + ex2_recip_g8( 8) <= ex2_recip_g4( 8) or (ex2_recip_t4( 8) and ex2_recip_g4(12) ); + ex2_recip_g8( 7) <= ex2_recip_g4( 7) or (ex2_recip_t4( 7) and ex2_recip_g4(11) ); + ex2_recip_g8( 6) <= ex2_recip_g4( 6) or (ex2_recip_t4( 6) and ex2_recip_g4(10) ); + ex2_recip_g8( 5) <= ex2_recip_g4( 5) or (ex2_recip_t4( 5) and ex2_recip_g4( 9) ); + ex2_recip_g8( 4) <= ex2_recip_g4( 4) or (ex2_recip_t4( 4) and ex2_recip_g4( 8) ); + ex2_recip_g8( 3) <= ex2_recip_g4( 3) or (ex2_recip_t4( 3) and ex2_recip_g4( 7) ); + ex2_recip_g8( 2) <= ex2_recip_g4( 2) or (ex2_recip_t4( 2) and ex2_recip_g4( 6) ); + + ex2_recip_t8( 5) <= (ex2_recip_t4( 5) and ex2_recip_t4( 9) ); + ex2_recip_t8( 4) <= (ex2_recip_t4( 4) and ex2_recip_t4( 8) ); + ex2_recip_t8( 3) <= (ex2_recip_t4( 3) and ex2_recip_t4( 7) ); + ex2_recip_t8( 2) <= (ex2_recip_t4( 2) and ex2_recip_t4( 6) ); + + ex2_recip_c(13) <= ex2_recip_g8(13); + ex2_recip_c(12) <= ex2_recip_g8(12); + ex2_recip_c(11) <= ex2_recip_g8(11); + ex2_recip_c(10) <= ex2_recip_g8(10); + ex2_recip_c( 9) <= ex2_recip_g8( 9); + ex2_recip_c( 8) <= ex2_recip_g8( 8); + ex2_recip_c( 7) <= ex2_recip_g8( 7); + ex2_recip_c( 6) <= ex2_recip_g8( 6); + ex2_recip_c( 5) <= ex2_recip_g8( 5) or (ex2_recip_t8( 5) and ex2_recip_g8(13) ); + ex2_recip_c( 4) <= ex2_recip_g8( 4) or (ex2_recip_t8( 4) and ex2_recip_g8(12) ); + ex2_recip_c( 3) <= ex2_recip_g8( 3) or (ex2_recip_t8( 3) and ex2_recip_g8(11) ); + ex2_recip_c( 2) <= ex2_recip_g8( 2) or (ex2_recip_t8( 2) and ex2_recip_g8(10) ); + + + ex2_recip_expo(1 to 12) <= ex2_recip_p(1 to 12) xor ex2_recip_c(2 to 13); + ex2_recip_expo(13) <= ex2_recip_p(13); + + + --//#-------------------------------------------- + --//# adder for !(B-clz) + K_rsqrt + --//#-------------------------------------------- + -- 1 2 3 4 5 6 7 8 9 10 11 12 13 + -- 1 !B01 !B02 !B03 !B04 !B05 !B06 !B07 !B08 !B09 !B10 !B11 !B12 rsqrte + -- 0 0 1 0 1 1 1 1 1 1 1 1 !B13 + + ex2_rsqrt_k(1 to 13) <= tidn & tidn & tiup & tidn & (5 to 12=> tiup) & ex2_b_expo_adj_b(13); + ex2_rsqrt_bsh_b(1 to 13) <= ex2_b_expo_adj_b(1) & ex2_b_expo_adj_b(1 to 12); --negative expo in -> positive + + ex2_rsqrt_p(1 to 13) <= ex2_rsqrt_k(1 to 13) xor ex2_rsqrt_bsh_b(1 to 13) ; + ex2_rsqrt_g(2 to 13) <= ex2_rsqrt_k(2 to 13) and ex2_rsqrt_bsh_b(2 to 13) ; + ex2_rsqrt_t(2 to 12) <= ex2_rsqrt_k(2 to 12) or ex2_rsqrt_bsh_b(2 to 12) ; + + + + ex2_rsqrt_g2(13) <= ex2_rsqrt_g(13); + ex2_rsqrt_g2(12) <= ex2_rsqrt_g(12) or (ex2_rsqrt_t(12) and ex2_rsqrt_g(13) ); + ex2_rsqrt_g2(11) <= ex2_rsqrt_g(11) or (ex2_rsqrt_t(11) and ex2_rsqrt_g(12) ); + ex2_rsqrt_g2(10) <= ex2_rsqrt_g(10) or (ex2_rsqrt_t(10) and ex2_rsqrt_g(11) ); + ex2_rsqrt_g2( 9) <= ex2_rsqrt_g( 9) or (ex2_rsqrt_t( 9) and ex2_rsqrt_g(10) ); + ex2_rsqrt_g2( 8) <= ex2_rsqrt_g( 8) or (ex2_rsqrt_t( 8) and ex2_rsqrt_g( 9) ); + ex2_rsqrt_g2( 7) <= ex2_rsqrt_g( 7) or (ex2_rsqrt_t( 7) and ex2_rsqrt_g( 8) ); + ex2_rsqrt_g2( 6) <= ex2_rsqrt_g( 6) or (ex2_rsqrt_t( 6) and ex2_rsqrt_g( 7) ); + ex2_rsqrt_g2( 5) <= ex2_rsqrt_g( 5) or (ex2_rsqrt_t( 5) and ex2_rsqrt_g( 6) ); + ex2_rsqrt_g2( 4) <= ex2_rsqrt_g( 4) or (ex2_rsqrt_t( 4) and ex2_rsqrt_g( 5) ); + ex2_rsqrt_g2( 3) <= ex2_rsqrt_g( 3) or (ex2_rsqrt_t( 3) and ex2_rsqrt_g( 4) ); + ex2_rsqrt_g2( 2) <= ex2_rsqrt_g( 2) or (ex2_rsqrt_t( 2) and ex2_rsqrt_g( 3) ); + + ex2_rsqrt_t2(11) <= (ex2_rsqrt_t(11) and ex2_rsqrt_t(12) ); + ex2_rsqrt_t2(10) <= (ex2_rsqrt_t(10) and ex2_rsqrt_t(11) ); + ex2_rsqrt_t2( 9) <= (ex2_rsqrt_t( 9) and ex2_rsqrt_t(10) ); + ex2_rsqrt_t2( 8) <= (ex2_rsqrt_t( 8) and ex2_rsqrt_t( 9) ); + ex2_rsqrt_t2( 7) <= (ex2_rsqrt_t( 7) and ex2_rsqrt_t( 8) ); + ex2_rsqrt_t2( 6) <= (ex2_rsqrt_t( 6) and ex2_rsqrt_t( 7) ); + ex2_rsqrt_t2( 5) <= (ex2_rsqrt_t( 5) and ex2_rsqrt_t( 6) ); + ex2_rsqrt_t2( 4) <= (ex2_rsqrt_t( 4) and ex2_rsqrt_t( 5) ); + ex2_rsqrt_t2( 3) <= (ex2_rsqrt_t( 3) and ex2_rsqrt_t( 4) ); + ex2_rsqrt_t2( 2) <= (ex2_rsqrt_t( 2) and ex2_rsqrt_t( 3) ); + + ex2_rsqrt_g4(13) <= ex2_rsqrt_g2(13); + ex2_rsqrt_g4(12) <= ex2_rsqrt_g2(12); + ex2_rsqrt_g4(11) <= ex2_rsqrt_g2(11) or (ex2_rsqrt_t2(11) and ex2_rsqrt_g2(13) ); + ex2_rsqrt_g4(10) <= ex2_rsqrt_g2(10) or (ex2_rsqrt_t2(10) and ex2_rsqrt_g2(12) ); + ex2_rsqrt_g4( 9) <= ex2_rsqrt_g2( 9) or (ex2_rsqrt_t2( 9) and ex2_rsqrt_g2(11) ); + ex2_rsqrt_g4( 8) <= ex2_rsqrt_g2( 8) or (ex2_rsqrt_t2( 8) and ex2_rsqrt_g2(10) ); + ex2_rsqrt_g4( 7) <= ex2_rsqrt_g2( 7) or (ex2_rsqrt_t2( 7) and ex2_rsqrt_g2( 9) ); + ex2_rsqrt_g4( 6) <= ex2_rsqrt_g2( 6) or (ex2_rsqrt_t2( 6) and ex2_rsqrt_g2( 8) ); + ex2_rsqrt_g4( 5) <= ex2_rsqrt_g2( 5) or (ex2_rsqrt_t2( 5) and ex2_rsqrt_g2( 7) ); + ex2_rsqrt_g4( 4) <= ex2_rsqrt_g2( 4) or (ex2_rsqrt_t2( 4) and ex2_rsqrt_g2( 6) ); + ex2_rsqrt_g4( 3) <= ex2_rsqrt_g2( 3) or (ex2_rsqrt_t2( 3) and ex2_rsqrt_g2( 5) ); + ex2_rsqrt_g4( 2) <= ex2_rsqrt_g2( 2) or (ex2_rsqrt_t2( 2) and ex2_rsqrt_g2( 4) ); + + ex2_rsqrt_t4( 9) <= (ex2_rsqrt_t2( 9) and ex2_rsqrt_t2(11) ); + ex2_rsqrt_t4( 8) <= (ex2_rsqrt_t2( 8) and ex2_rsqrt_t2(10) ); + ex2_rsqrt_t4( 7) <= (ex2_rsqrt_t2( 7) and ex2_rsqrt_t2( 9) ); + ex2_rsqrt_t4( 6) <= (ex2_rsqrt_t2( 6) and ex2_rsqrt_t2( 8) ); + ex2_rsqrt_t4( 5) <= (ex2_rsqrt_t2( 5) and ex2_rsqrt_t2( 7) ); + ex2_rsqrt_t4( 4) <= (ex2_rsqrt_t2( 4) and ex2_rsqrt_t2( 6) ); + ex2_rsqrt_t4( 3) <= (ex2_rsqrt_t2( 3) and ex2_rsqrt_t2( 5) ); + ex2_rsqrt_t4( 2) <= (ex2_rsqrt_t2( 2) and ex2_rsqrt_t2( 4) ); + + ex2_rsqrt_g8(13) <= ex2_rsqrt_g4(13); + ex2_rsqrt_g8(12) <= ex2_rsqrt_g4(12); + ex2_rsqrt_g8(11) <= ex2_rsqrt_g4(11); + ex2_rsqrt_g8(10) <= ex2_rsqrt_g4(10); + ex2_rsqrt_g8( 9) <= ex2_rsqrt_g4( 9) or (ex2_rsqrt_t4( 9) and ex2_rsqrt_g4(13) ); + ex2_rsqrt_g8( 8) <= ex2_rsqrt_g4( 8) or (ex2_rsqrt_t4( 8) and ex2_rsqrt_g4(12) ); + ex2_rsqrt_g8( 7) <= ex2_rsqrt_g4( 7) or (ex2_rsqrt_t4( 7) and ex2_rsqrt_g4(11) ); + ex2_rsqrt_g8( 6) <= ex2_rsqrt_g4( 6) or (ex2_rsqrt_t4( 6) and ex2_rsqrt_g4(10) ); + ex2_rsqrt_g8( 5) <= ex2_rsqrt_g4( 5) or (ex2_rsqrt_t4( 5) and ex2_rsqrt_g4( 9) ); + ex2_rsqrt_g8( 4) <= ex2_rsqrt_g4( 4) or (ex2_rsqrt_t4( 4) and ex2_rsqrt_g4( 8) ); + ex2_rsqrt_g8( 3) <= ex2_rsqrt_g4( 3) or (ex2_rsqrt_t4( 3) and ex2_rsqrt_g4( 7) ); + ex2_rsqrt_g8( 2) <= ex2_rsqrt_g4( 2) or (ex2_rsqrt_t4( 2) and ex2_rsqrt_g4( 6) ); + + ex2_rsqrt_t8( 5) <= (ex2_rsqrt_t4( 5) and ex2_rsqrt_t4( 9) ); + ex2_rsqrt_t8( 4) <= (ex2_rsqrt_t4( 4) and ex2_rsqrt_t4( 8) ); + ex2_rsqrt_t8( 3) <= (ex2_rsqrt_t4( 3) and ex2_rsqrt_t4( 7) ); + ex2_rsqrt_t8( 2) <= (ex2_rsqrt_t4( 2) and ex2_rsqrt_t4( 6) ); + + ex2_rsqrt_c(13) <= ex2_rsqrt_g8(13); + ex2_rsqrt_c(12) <= ex2_rsqrt_g8(12); + ex2_rsqrt_c(11) <= ex2_rsqrt_g8(11); + ex2_rsqrt_c(10) <= ex2_rsqrt_g8(10); + ex2_rsqrt_c( 9) <= ex2_rsqrt_g8( 9); + ex2_rsqrt_c( 8) <= ex2_rsqrt_g8( 8); + ex2_rsqrt_c( 7) <= ex2_rsqrt_g8( 7); + ex2_rsqrt_c( 6) <= ex2_rsqrt_g8( 6); + ex2_rsqrt_c( 5) <= ex2_rsqrt_g8( 5) or (ex2_rsqrt_t8( 5) and ex2_rsqrt_g8(13) ); + ex2_rsqrt_c( 4) <= ex2_rsqrt_g8( 4) or (ex2_rsqrt_t8( 4) and ex2_rsqrt_g8(12) ); + ex2_rsqrt_c( 3) <= ex2_rsqrt_g8( 3) or (ex2_rsqrt_t8( 3) and ex2_rsqrt_g8(11) ); + ex2_rsqrt_c( 2) <= ex2_rsqrt_g8( 2) or (ex2_rsqrt_t8( 2) and ex2_rsqrt_g8(10) ); + + + + ex2_rsqrt_expo(1 to 12) <= ex2_rsqrt_p(1 to 12) xor ex2_rsqrt_c(2 to 13); + ex2_rsqrt_expo(13) <= ex2_rsqrt_p(13); + + --//#-------------------------------------------- + --//# select the result + --//#-------------------------------------------- + + ex2_res_expo(1 to 13) <= + ( (1 to 13=> f_pic_ex2_est_rsqrt) and ex2_rsqrt_expo(1 to 13) ) or + ( (1 to 13=> f_pic_ex2_est_recip) and ex2_recip_expo(1 to 13) ) ; + + + --//#-------------------------------------------- + + --//## -------------------------------------------------- + --//## DETECT: exponents that require denormalization + -- + -- rsqrte: -( (e - bias)/2 ) + bias = -e/2 + 3/2 bias + -- expo = 7ff inf/nan (2047) <=== special case logic gives result + -- expo = 7fe (2046) -(2046 - 1023)/2 + 1023 = -1023/2 + 1023 = -512 + 1023 = 611 : norm + -- + -- + -- recip : 2bias -expo = -(e - bias) + bias + -- expo = 7ff inf/nan (2047) <=== special case logic gives result + -- expo = 7fe (2046) 2bias -expo = 2046 - 2046 = x000 denorm + -- expo = 7fd (2045) 2046 - 2045 = x001 denorm ? + -- expo = 7fc (2044) 2046 - 2044 = x002 norm (denorm if adjust) + --//## -------------------------------------------------- + -- for sp underflow, no need to denormalize, but must set the UX flag + -- 2046 -1151 = 895 - 1 = 894 <=== INF/NAN in sp range + -- 2046 -1150 = 896 - 1 = 895 x380 + -- 2046 -1149 = 897 - 1 = 896 x380 + -- 2046 -1148 = 898 - 1 = 897 (denorm if adjust) + -- + -- 2046 111_1111_11110 + -- 2045 111_1111_11101 + -- 2044 111_1111_11100 + -- + -- 1150 100_0111_11110 + -- 1149 100_0111_11101 + -- 1148 100_0111_11100 + -- + + + ex2_mid_match_ifsp <= not f_eie_ex2_tbl_expo( 4) and -- 0512 + not f_eie_ex2_tbl_expo( 5) and -- 0256 + not f_eie_ex2_tbl_expo( 6) ; -- 0128 + + ex2_mid_match_ifdp <= f_eie_ex2_tbl_expo( 4) and -- 0512 total = 896 + f_eie_ex2_tbl_expo( 5) and -- 0256 + f_eie_ex2_tbl_expo( 6) ; -- 0128 + + ex2_com_match <= not f_eie_ex2_tbl_expo( 1) and -- sign + not f_eie_ex2_tbl_expo( 2) and -- 2048 + f_eie_ex2_tbl_expo( 3) and -- 1024 + f_eie_ex2_tbl_expo( 7) and -- 0064 + f_eie_ex2_tbl_expo( 8) and -- 0032 + f_eie_ex2_tbl_expo( 9) and -- 0016 + f_eie_ex2_tbl_expo(10) and -- 0008 + f_eie_ex2_tbl_expo(11) ; -- 0004 + + ex2_match_en_dp <= ex2_com_match and f_pic_ex2_sp_b and ex2_mid_match_ifdp ; + ex2_match_en_sp <= ex2_com_match and not f_pic_ex2_sp_b and ex2_mid_match_ifsp ; + + ex2_recip_2046 <= f_pic_ex2_est_recip and -- not f_pic_ex2_ue1 and + f_eie_ex2_tbl_expo(12) and -- 0002 + not f_eie_ex2_tbl_expo(13) ; -- 0001 + + ex2_recip_2045 <= f_pic_ex2_est_recip and -- not f_pic_ex2_ue1 and + not f_eie_ex2_tbl_expo(12) and -- 0002 + f_eie_ex2_tbl_expo(13) ; -- 0001 + + ex2_recip_2044 <= f_pic_ex2_est_recip and -- not f_pic_ex2_ue1 and + not f_eie_ex2_tbl_expo(12) and -- 0002 + not f_eie_ex2_tbl_expo(13) ; -- 0001 + + ex2_recip_ue1 <= f_pic_ex2_est_recip and f_pic_ex2_ue1 ; + + +--//############################################## +--//# EX3 latches +--//############################################## + + -- name says odd(unbiased) but it is really for even biased. + ex2_lu_sh <= (f_fmt_ex2_lu_den_recip and f_pic_ex2_est_recip ) or + (f_fmt_ex2_lu_den_rsqrto and f_pic_ex2_est_rsqrt and not f_eie_ex2_tbl_expo(13) ); + + ex3_expo_lat: tri_rlmreg_p generic map (width=> 20, expand_type => expand_type) port map ( + forcee => forcee,--tidn, + delay_lclkr => delay_lclkr(3) ,--tidn, + mpw1_b => mpw1_b(3) ,--tidn, + mpw2_b => mpw2_b(0) ,--tidn, + vd => vdd, + gd => gnd, + nclk => nclk, + thold_b => thold_0_b, + sg => sg_0, + act => ex2_act, + scout => ex3_expo_so , + scin => ex3_expo_si , + + din(0 to 12) => ex2_res_expo(1 to 13) , + din(13) => ex2_match_en_dp , + din(14) => ex2_match_en_sp , + din(15) => ex2_recip_2046 , + din(16) => ex2_recip_2045 , + din(17) => ex2_recip_2044 , + din(18) => ex2_lu_sh , + din(19) => ex2_recip_ue1 , + ------------------- + dout(0 to 12) => ex3_res_expo(1 to 13) ,--LAT-- + dout(13) => ex3_match_en_dp ,--LAT-- + dout(14) => ex3_match_en_sp ,--LAT-- + dout(15) => ex3_recip_2046 ,--LAT-- + dout(16) => ex3_recip_2045 ,--LAT-- + dout(17) => ex3_recip_2044 ,--LAT-- + dout(18) => ex3_lu_sh ,--LAT-- + dout(19) => ex3_recip_ue1 );--LAT-- + + + +--//############################################## +--//# EX3 logic +--//############################################## + + + f_tbe_ex3_match_en_sp <= ex3_match_en_sp ; --output + f_tbe_ex3_match_en_dp <= ex3_match_en_dp ; --output + f_tbe_ex3_recip_2046 <= ex3_recip_2046 ; --output + f_tbe_ex3_recip_2045 <= ex3_recip_2045 ; --output + f_tbe_ex3_recip_2044 <= ex3_recip_2044 ; --output + f_tbe_ex3_lu_sh <= ex3_lu_sh ; --output-- + f_tbe_ex3_recip_ue1 <= ex3_recip_ue1 ; --output-- + + ex3_recip_2046_dp <= ex3_recip_2046 and ex3_match_en_dp and not ex3_recip_ue1 ; -- for shifting + ex3_recip_2045_dp <= ex3_recip_2045 and ex3_match_en_dp and not ex3_recip_ue1 ; -- for shifting + ex3_recip_2044_dp <= ex3_recip_2044 and ex3_match_en_dp and not ex3_recip_ue1 ; -- for shifting + ex3_force_expo_den <= ex3_recip_2046_dp or ex3_recip_2045_dp; -- do not force DEN for ue1 mode + -- 2044 conditionally backs into denorm depending on lu_sh ... decrement + + ex3_decr_expo <= -- for denormalization / normalization + ( ex3_lu_sh and ex3_recip_ue1 ) or + ( ex3_lu_sh and not ex3_recip_ue1 and not ex3_recip_2046_dp + and not ex3_recip_2045_dp + and not ex3_recip_2044_dp ); + + + -- decrement is like add 11111....11111 (lsb does not change + -- t = 1 + -- g = d + + ex3_res_expo_b(1 to 13) <= not ex3_res_expo(1 to 13); + + ex3_res_expo_g2_b(13) <= not( ex3_res_expo (13) ); + ex3_res_expo_g2_b(12) <= not( ex3_res_expo (12) or ex3_res_expo (13) ); + ex3_res_expo_g2_b(11) <= not( ex3_res_expo (11) or ex3_res_expo (12) ); + ex3_res_expo_g2_b(10) <= not( ex3_res_expo (10) or ex3_res_expo (11) ); + ex3_res_expo_g2_b( 9) <= not( ex3_res_expo ( 9) or ex3_res_expo (10) ); + ex3_res_expo_g2_b( 8) <= not( ex3_res_expo ( 8) or ex3_res_expo ( 9) ); + ex3_res_expo_g2_b( 7) <= not( ex3_res_expo ( 7) or ex3_res_expo ( 8) ); + ex3_res_expo_g2_b( 6) <= not( ex3_res_expo ( 6) or ex3_res_expo ( 7) ); + ex3_res_expo_g2_b( 5) <= not( ex3_res_expo ( 5) or ex3_res_expo ( 6) ); + ex3_res_expo_g2_b( 4) <= not( ex3_res_expo ( 4) or ex3_res_expo ( 5) ); + ex3_res_expo_g2_b( 3) <= not( ex3_res_expo ( 3) or ex3_res_expo ( 4) ); + ex3_res_expo_g2_b( 2) <= not( ex3_res_expo ( 2) or ex3_res_expo ( 3) ); + + ex3_res_expo_g4 (13) <= not( ex3_res_expo_g2_b(13) ); + ex3_res_expo_g4 (12) <= not( ex3_res_expo_g2_b(12) ); + ex3_res_expo_g4 (11) <= not( ex3_res_expo_g2_b(11) and ex3_res_expo_g2_b(13) ); + ex3_res_expo_g4 (10) <= not( ex3_res_expo_g2_b(10) and ex3_res_expo_g2_b(12) ); + ex3_res_expo_g4 ( 9) <= not( ex3_res_expo_g2_b( 9) and ex3_res_expo_g2_b(11) ); + ex3_res_expo_g4 ( 8) <= not( ex3_res_expo_g2_b( 8) and ex3_res_expo_g2_b(10) ); + ex3_res_expo_g4 ( 7) <= not( ex3_res_expo_g2_b( 7) and ex3_res_expo_g2_b( 9) ); + ex3_res_expo_g4 ( 6) <= not( ex3_res_expo_g2_b( 6) and ex3_res_expo_g2_b( 8) ); + ex3_res_expo_g4 ( 5) <= not( ex3_res_expo_g2_b( 5) and ex3_res_expo_g2_b( 7) ); + ex3_res_expo_g4 ( 4) <= not( ex3_res_expo_g2_b( 4) and ex3_res_expo_g2_b( 6) ); + ex3_res_expo_g4 ( 3) <= not( ex3_res_expo_g2_b( 3) and ex3_res_expo_g2_b( 5) ); + ex3_res_expo_g4 ( 2) <= not( ex3_res_expo_g2_b( 2) and ex3_res_expo_g2_b( 4) ); + + ex3_res_expo_g8_b(13) <= not( ex3_res_expo_g4 (13) ); + ex3_res_expo_g8_b(12) <= not( ex3_res_expo_g4 (12) ); + ex3_res_expo_g8_b(11) <= not( ex3_res_expo_g4 (11) ); + ex3_res_expo_g8_b(10) <= not( ex3_res_expo_g4 (10) ); + ex3_res_expo_g8_b( 9) <= not( ex3_res_expo_g4 ( 9) or ex3_res_expo_g4 (13) ); + ex3_res_expo_g8_b( 8) <= not( ex3_res_expo_g4 ( 8) or ex3_res_expo_g4 (12) ); + ex3_res_expo_g8_b( 7) <= not( ex3_res_expo_g4 ( 7) or ex3_res_expo_g4 (11) ); + ex3_res_expo_g8_b( 6) <= not( ex3_res_expo_g4 ( 6) or ex3_res_expo_g4 (10) ); + ex3_res_expo_g8_b( 5) <= not( ex3_res_expo_g4 ( 5) or ex3_res_expo_g4 ( 9) ); + ex3_res_expo_g8_b( 4) <= not( ex3_res_expo_g4 ( 4) or ex3_res_expo_g4 ( 8) ); + ex3_res_expo_g8_b( 3) <= not( ex3_res_expo_g4 ( 3) or ex3_res_expo_g4 ( 7) ); + ex3_res_expo_g8_b( 2) <= not( ex3_res_expo_g4 ( 2) or ex3_res_expo_g4 ( 6) ); + + ex3_res_expo_c (13) <= not( ex3_res_expo_g8_b(13) ); + ex3_res_expo_c (12) <= not( ex3_res_expo_g8_b(12) ); + ex3_res_expo_c (11) <= not( ex3_res_expo_g8_b(11) ); + ex3_res_expo_c (10) <= not( ex3_res_expo_g8_b(10) ); + ex3_res_expo_c ( 9) <= not( ex3_res_expo_g8_b( 9) ); + ex3_res_expo_c ( 8) <= not( ex3_res_expo_g8_b( 8) ); + ex3_res_expo_c ( 7) <= not( ex3_res_expo_g8_b( 7) ); + ex3_res_expo_c ( 6) <= not( ex3_res_expo_g8_b( 6) ); + ex3_res_expo_c ( 5) <= not( ex3_res_expo_g8_b( 5) and ex3_res_expo_g8_b(13) ); + ex3_res_expo_c ( 4) <= not( ex3_res_expo_g8_b( 4) and ex3_res_expo_g8_b(12) ); + ex3_res_expo_c ( 3) <= not( ex3_res_expo_g8_b( 3) and ex3_res_expo_g8_b(11) ); + ex3_res_expo_c ( 2) <= not( ex3_res_expo_g8_b( 2) and ex3_res_expo_g8_b(10) ); + + + ex3_res_decr(1 to 12) <= ex3_res_expo_b(1 to 12) xor ex3_res_expo_c(2 to 13); + ex3_res_decr(13) <= ex3_res_expo_b(13) ; + + + f_tbe_ex3_res_expo( 1) <= ( ex3_res_expo( 1) and not ex3_decr_expo and not ex3_force_expo_den ) or --output + ( ex3_res_decr( 1) and ex3_decr_expo ); + f_tbe_ex3_res_expo( 2) <= ( ex3_res_expo( 2) and not ex3_decr_expo and not ex3_force_expo_den ) or --output + ( ex3_res_decr( 2) and ex3_decr_expo ); + f_tbe_ex3_res_expo( 3) <= ( ex3_res_expo( 3) and not ex3_decr_expo and not ex3_force_expo_den ) or --output + ( ex3_res_decr( 3) and ex3_decr_expo ); + f_tbe_ex3_res_expo( 4) <= ( ex3_res_expo( 4) and not ex3_decr_expo and not ex3_force_expo_den ) or --output + ( ex3_res_decr( 4) and ex3_decr_expo ); + f_tbe_ex3_res_expo( 5) <= ( ex3_res_expo( 5) and not ex3_decr_expo and not ex3_force_expo_den ) or --output + ( ex3_res_decr( 5) and ex3_decr_expo ); + f_tbe_ex3_res_expo( 6) <= ( ex3_res_expo( 6) and not ex3_decr_expo and not ex3_force_expo_den ) or --output + ( ex3_res_decr( 6) and ex3_decr_expo ); + f_tbe_ex3_res_expo( 7) <= ( ex3_res_expo( 7) and not ex3_decr_expo and not ex3_force_expo_den ) or --output + ( ex3_res_decr( 7) and ex3_decr_expo ); + f_tbe_ex3_res_expo( 8) <= ( ex3_res_expo( 8) and not ex3_decr_expo and not ex3_force_expo_den ) or --output + ( ex3_res_decr( 8) and ex3_decr_expo ); + f_tbe_ex3_res_expo( 9) <= ( ex3_res_expo( 9) and not ex3_decr_expo and not ex3_force_expo_den ) or --output + ( ex3_res_decr( 9) and ex3_decr_expo ); + f_tbe_ex3_res_expo(10) <= ( ex3_res_expo(10) and not ex3_decr_expo and not ex3_force_expo_den ) or --output + ( ex3_res_decr(10) and ex3_decr_expo ); + f_tbe_ex3_res_expo(11) <= ( ex3_res_expo(11) and not ex3_decr_expo and not ex3_force_expo_den ) or --output + ( ex3_res_decr(11) and ex3_decr_expo ); + f_tbe_ex3_res_expo(12) <= ( ex3_res_expo(12) and not ex3_decr_expo and not ex3_force_expo_den ) or --output + ( ex3_res_decr(12) and ex3_decr_expo ); + f_tbe_ex3_res_expo(13) <= ( ex3_res_expo(13) and not ex3_decr_expo ) or --output + ( ex3_res_decr(13) and ex3_decr_expo ) or + ( ex3_force_expo_den ); + + + + + f_tbe_ex3_may_ov <= -- before the den adjustments on purpose + (not ex3_res_expo(1) and ex3_res_expo(2) ) or + (not ex3_res_expo(1) and ex3_res_expo(3) and ex3_res_expo(4) ) or + (not ex3_res_expo(1) and ex3_res_expo(3) and ex3_res_expo(5) ) or + (not ex3_res_expo(1) and ex3_res_expo(3) and ex3_res_expo(6) ) or + (not ex3_res_expo(1) and ex3_res_expo(3) and ex3_res_expo(7) ) or + (not ex3_res_expo(1) and ex3_res_expo(3) and ex3_res_expo(8) and ex3_res_expo(9) ); + + + +--//############################################ +--//# scan +--//############################################ + + + ex3_expo_si (0 to 19) <= ex3_expo_so (1 to 19) & si; + act_si (0 to 4) <= act_so (1 to 4) & ex3_expo_so (0); + so <= act_so (0); + + +end; -- fuq_tblexp ARCHITECTURE diff --git a/rel/src/vhdl/work/fuq_tbllut.vhdl b/rel/src/vhdl/work/fuq_tbllut.vhdl new file mode 100644 index 0000000..3eef3b1 --- /dev/null +++ b/rel/src/vhdl/work/fuq_tbllut.vhdl @@ -0,0 +1,855 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + + +entity fuq_tbllut is +generic( expand_type : integer := 2 ); +port( + vdd :inout power_logic; + gnd :inout power_logic; + clkoff_b :in std_ulogic; -- tiup + act_dis :in std_ulogic; -- ??tidn?? + flush :in std_ulogic; -- ??tidn?? + delay_lclkr :in std_ulogic_vector(2 to 5); -- tidn, + mpw1_b :in std_ulogic_vector(2 to 5); -- tidn, + mpw2_b :in std_ulogic_vector(0 to 1); -- tidn, + sg_1 :in std_ulogic; + thold_1 :in std_ulogic; + fpu_enable :in std_ulogic; --dc_act + nclk :in clk_logic; + + + si :in std_ulogic; --perv + so :out std_ulogic; --perv + ex1_act :in std_ulogic; --act + ------------------------------ + f_fmt_ex1_b_frac :in std_ulogic_vector(1 to 6); + f_fmt_ex2_b_frac :in std_ulogic_vector(7 to 22); + f_tbe_ex2_expo_lsb :in std_ulogic; + f_tbe_ex2_est_recip :in std_ulogic; + f_tbe_ex2_est_rsqrt :in std_ulogic; + f_tbe_ex3_recip_ue1 :in std_ulogic ; + f_tbe_ex3_lu_sh :in std_ulogic; + f_tbe_ex3_match_en_sp :in std_ulogic; + f_tbe_ex3_match_en_dp :in std_ulogic; + f_tbe_ex3_recip_2046 :in std_ulogic; + f_tbe_ex3_recip_2045 :in std_ulogic; + f_tbe_ex3_recip_2044 :in std_ulogic; + ------------------------------ + f_tbl_ex5_est_frac :out std_ulogic_vector(0 to 26); + f_tbl_ex4_unf_expo :out std_ulogic ; + f_tbl_ex5_recip_den :out std_ulogic --generates den flag +); + + +end fuq_tbllut; -- ENTITY + +architecture fuq_tbllut of fuq_tbllut is + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal ex4_unf_expo :std_ulogic ; + signal ex2_f :std_ulogic_vector(1 to 6); + signal ex2_sel_recip, ex2_sel_rsqte, ex2_sel_rsqto : std_ulogic; + signal ex2_est, ex2_est_recip, ex2_est_rsqte, ex2_est_rsqto :std_ulogic_vector(1 to 20); + signal ex2_rng :std_ulogic_vector(6 to 20); + signal ex2_rng_recip, ex2_rng_rsqte, ex2_rng_rsqto :std_ulogic_vector(6 to 20); + + signal thold_0_b, thold_0, forcee, sg_0 :std_ulogic ; + signal ex2_act, ex3_act, ex4_act :std_ulogic; + signal spare_unused :std_ulogic_vector(0 to 3); + + signal ex2_lut_so, ex2_lut_si :std_ulogic_vector(0 to 5); + signal act_so, act_si :std_ulogic_vector(0 to 6); + signal ex3_lut_e_so, ex3_lut_e_si :std_ulogic_vector(0 to 19); + signal ex3_lut_r_so, ex3_lut_r_si :std_ulogic_vector(0 to 14); + signal ex3_lut_b_so, ex3_lut_b_si :std_ulogic_vector(0 to 15); + + + signal ex3_rng, ex3_rng_b :std_ulogic_vector(6 to 20); + signal ex3_est, ex3_est_b :std_ulogic_vector(1 to 20); + signal ex3_bop, ex3_bop_b :std_ulogic_vector(7 to 22); + signal ex3_tbl_sum :std_ulogic_vector(0 to 36) ; + signal ex3_tbl_car :std_ulogic_vector(0 to 35) ; + signal ex4_tbl_sum :std_ulogic_vector(0 to 38) ; + signal ex4_tbl_car :std_ulogic_vector(0 to 38) ; + + signal ex4_lut_so , ex4_lut_si :std_ulogic_vector(0 to 79); + + signal ex5_lut_so , ex5_lut_si :std_ulogic_vector(0 to 27) ; + signal ex4_lu , ex4_lux :std_ulogic_vector(0 to 27) ; + signal ex4_lu_nrm :std_ulogic_vector(0 to 26) ; + signal ex5_lu :std_ulogic_vector(0 to 26); + + signal lua_p :std_ulogic_vector(0 to 27); + signal lua_t :std_ulogic_vector(1 to 37); + signal lua_g :std_ulogic_vector(1 to 38); + signal lua_g2 :std_ulogic_vector(1 to 38); + signal lua_g4 :std_ulogic_vector(1 to 36); + signal lua_g8 :std_ulogic_vector(1 to 32); + signal lua_t2 :std_ulogic_vector(1 to 36); + signal lua_t4 :std_ulogic_vector(1 to 32); + signal lua_t8 :std_ulogic_vector(1 to 28); + signal lua_gt8 :std_ulogic_vector(1 to 28); + signal lua_s0_b :std_ulogic_vector(0 to 27); + signal lua_s1_b :std_ulogic_vector(0 to 27); + signal lua_g16 : std_ulogic_vector(0 to 3); + signal lua_t16 : std_ulogic_vector(0 to 1); + signal lua_c32 , lua_c24 , lua_c16 , lua_c08 :std_ulogic; + signal ex4_recip_den, ex5_recip_den :std_ulogic ; + signal ex4_lu_sh , ex4_recip_ue1, ex4_recip_2044, ex4_recip_2046 , ex4_recip_2045 :std_ulogic; + signal ex4_recip_2044_dp, ex4_recip_2046_dp , ex4_recip_2045_dp :std_ulogic; + signal ex4_recip_2044_sp, ex4_recip_2046_sp , ex4_recip_2045_sp :std_ulogic; + + signal ex4_shlft_1, ex4_shlft_0, ex4_shrgt_1, ex4_shrgt_2 :std_ulogic; + signal ex4_match_en_sp , ex4_match_en_dp :std_ulogic; + signal tbl_ex3_d1clk, tbl_ex3_d2clk :std_ulogic; + signal tbl_ex4_d1clk, tbl_ex4_d2clk :std_ulogic; + signal tbl_ex3_lclk :clk_logic; + signal tbl_ex4_lclk :clk_logic; + signal unused :std_ulogic; + signal ex4_tbl_sum_b :std_ulogic_vector(0 to 36) ; + signal ex4_tbl_car_b :std_ulogic_vector(0 to 35) ; + signal ex4_match_en_sp_b :std_ulogic; + signal ex4_match_en_dp_b :std_ulogic; + signal ex4_recip_2046_b :std_ulogic; + signal ex4_recip_2045_b :std_ulogic; + signal ex4_recip_2044_b :std_ulogic; + signal ex4_lu_sh_b :std_ulogic; + signal ex4_recip_ue1_b :std_ulogic; + + signal ex4_sp_chop_24, ex4_sp_chop_23, ex4_sp_chop_22, ex4_sp_chop_21 :std_ulogic; + + + +begin + + unused <= or_reduce(lua_g8(29 to 31) ) or or_reduce(lua_g4(33 to 35) ) ; + +--==############################################################## +--= ex2 logic +--==############################################################## + + ex2_lut_lat: tri_rlmreg_p generic map (width=> 6, expand_type => expand_type) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(2) , + mpw1_b => mpw1_b(2) , + mpw2_b => mpw2_b(0) , + vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_act, + thold_b => thold_0_b, + sg => sg_0, + scout => ex2_lut_so , + scin => ex2_lut_si , + ------------------- + din => f_fmt_ex1_b_frac(1 to 6), + dout => ex2_f(1 to 6) ); + +--==############################################################## +--= ex2 logic +--==############################################################## + + --==########################################### + --= rsqrt ev lookup table + --==########################################### + +ftbe: entity WORK.fuq_tblsqe(fuq_tblsqe) generic map( expand_type => expand_type) port map( + f(1 to 6) => ex2_f(1 to 6) ,--i-- + est(1 to 20) => ex2_est_rsqte(1 to 20) ,--o-- + rng(6 to 20) => ex2_rng_rsqte(6 to 20) );--o-- + + --==########################################### + --= rsqrt od lookup table + --==########################################### + +ftbo: entity WORK.fuq_tblsqo(fuq_tblsqo) generic map( expand_type => expand_type) port map( + f(1 to 6) => ex2_f(1 to 6) ,--i-- + est(1 to 20) => ex2_est_rsqto(1 to 20) ,--o-- + rng(6 to 20) => ex2_rng_rsqto(6 to 20) );--o-- + + --==########################################### + --= recip lookup table + --==########################################### + +ftbr: entity WORK.fuq_tblres(fuq_tblres) generic map( expand_type => expand_type) port map( + f(1 to 6) => ex2_f(1 to 6) ,--i-- + est(1 to 20) => ex2_est_recip(1 to 20) ,--o-- + rng(6 to 20) => ex2_rng_recip(6 to 20) );--o-- + + + + --==########################################### + --= muxing + --==########################################### + + ex2_sel_recip <= f_tbe_ex2_est_recip; + ex2_sel_rsqte <= f_tbe_ex2_est_rsqrt and not f_tbe_ex2_expo_lsb ; + ex2_sel_rsqto <= f_tbe_ex2_est_rsqrt and f_tbe_ex2_expo_lsb ; + + ex2_est(1 to 20) <= -- nand2 / nand3 + ( (1 to 20=> ex2_sel_recip) and ex2_est_recip(1 to 20) ) or + ( (1 to 20=> ex2_sel_rsqte) and ex2_est_rsqte(1 to 20) ) or + ( (1 to 20=> ex2_sel_rsqto) and ex2_est_rsqto(1 to 20) ) ; + + + ex2_rng(6 to 20) <= -- nand2 / nand3 + ( (6 to 20=> ex2_sel_recip ) and ( ex2_rng_recip(6 to 20)) ) or + ( (6 to 20=> ex2_sel_rsqte ) and ( ex2_rng_rsqte(6 to 20)) ) or + ( (6 to 20=> ex2_sel_rsqto ) and ( ex2_rng_rsqto(6 to 20)) ) ; + + +--==############################################################## +--= ex3 latches +--==############################################################## + + ex3_lut_e_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 20, btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd, + gd => gnd, + LCLK => tbl_ex3_lclk ,-- lclk.clk + D1CLK => tbl_ex3_d1clk , + D2CLK => tbl_ex3_d2clk , + SCANIN => ex3_lut_e_si , + SCANOUT => ex3_lut_e_so , + D(0 to 19) => ex2_est(1 to 20) , --0:19 + QB(0 to 19) => ex3_est_b(1 to 20) ); --0:19 + + ex3_lut_r_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 15, btr => "NLI0001_X4_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd, + gd => gnd, + LCLK => tbl_ex3_lclk ,-- lclk.clk + D1CLK => tbl_ex3_d1clk , + D2CLK => tbl_ex3_d2clk , + SCANIN => ex3_lut_r_si , + SCANOUT => ex3_lut_r_so , + D(0 to 14) => ex2_rng(6 to 20) , --20:34 + QB(0 to 14) => ex3_rng_b(6 to 20) ); --20:34 + + ex3_lut_b_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 16, btr => "NLI0001_X1_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + vd => vdd, + gd => gnd, + LCLK => tbl_ex3_lclk ,-- lclk.clk + D1CLK => tbl_ex3_d1clk , + D2CLK => tbl_ex3_d2clk , + SCANIN => ex3_lut_b_si , + SCANOUT => ex3_lut_b_so , + D(0 to 15) => f_fmt_ex2_b_frac(7 to 22) , --35:50 + QB(0 to 15) => ex3_bop_b(7 to 22) ); --35:50 + + ex3_est(1 to 20) <= not ex3_est_b(1 to 20); + ex3_rng(6 to 20) <= not ex3_rng_b(6 to 20); + ex3_bop(7 to 22) <= not ex3_bop_b(7 to 22); + + +--==############################################################## +--= ex3 logic : multiply +--==############################################################## + +ftbm: entity WORK.fuq_tblmul(fuq_tblmul) generic map( expand_type => expand_type) port map( + vdd => vdd, + gnd => gnd, + x(1 to 15) => ex3_rng(6 to 20) ,--i-- RECODED + y(7 to 22) => ex3_bop(7 to 22) ,--i-- SHIFTED + z(0) => tiup ,--i-- + z(1 to 20) => ex3_est(1 to 20) ,--i-- + tbl_sum(0 to 36) => ex3_tbl_sum(0 to 36) ,--o-- + tbl_car(0 to 35) => ex3_tbl_car(0 to 35) );--o-- + + +--==############################################################## +--= ex4 latches +--==############################################################## + + + ex4_lut_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 80, btr => "NLI0001_X2_A12TH", expand_type => expand_type , needs_sreset => 0 ) port map ( + vd => vdd, + gd => gnd, + LCLK => tbl_ex4_lclk ,-- lclk.clk + D1CLK => tbl_ex4_d1clk , + D2CLK => tbl_ex4_d2clk , + SCANIN => ex4_lut_si , + SCANOUT => ex4_lut_so , + D(0 to 36) => ex3_tbl_sum(0 to 36) , + D(37 to 72) => ex3_tbl_car(0 to 35) , + D(73) => f_tbe_ex3_match_en_sp , + D(74) => f_tbe_ex3_match_en_dp , + D(75) => f_tbe_ex3_recip_2046 , + D(76) => f_tbe_ex3_recip_2045 , + D(77) => f_tbe_ex3_recip_2044 , + D(78) => f_tbe_ex3_lu_sh , + D(79) => f_tbe_ex3_recip_ue1 , + ------ + QB(0 to 36) => ex4_tbl_sum_b(0 to 36) , + QB(37 to 72) => ex4_tbl_car_b(0 to 35) , + QB(73) => ex4_match_en_sp_b , + QB(74) => ex4_match_en_dp_b , + QB(75) => ex4_recip_2046_b , + QB(76) => ex4_recip_2045_b , + QB(77) => ex4_recip_2044_b , + QB(78) => ex4_lu_sh_b , + QB(79) => ex4_recip_ue1_b ); + + + ex4_tbl_sum (0 to 36) <= not ex4_tbl_sum_b(0 to 36) ; + ex4_tbl_car (0 to 35) <= not ex4_tbl_car_b(0 to 35) ; + ex4_match_en_sp <= not ex4_match_en_sp_b ; + ex4_match_en_dp <= not ex4_match_en_dp_b ; + ex4_recip_2046 <= not ex4_recip_2046_b ; + ex4_recip_2045 <= not ex4_recip_2045_b ; + ex4_recip_2044 <= not ex4_recip_2044_b ; + ex4_lu_sh <= not ex4_lu_sh_b ; + ex4_recip_ue1 <= not ex4_recip_ue1_b ; + + + + + ex4_tbl_sum(37) <= tidn; + ex4_tbl_sum(38) <= tidn; + + ex4_tbl_car(36) <= tidn; --tiup; -- the +1 in -mul = !mul + 1 + ex4_tbl_car(37) <= tidn; --tiup; -- the +1 in -mul = !mul + 1 + ex4_tbl_car(38) <= tidn; --tiup; -- the +1 in -mul = !mul + 1 + +--==############################################################## +--= ex4 logic : add +--==############################################################## + -- all bits paricipate in the carry, but only upper bits of sum are returned + + -- P/G/T ------------------------------------------------------ + lua_p(0 to 27) <= ex4_tbl_sum(0 to 27) xor ex4_tbl_car(0 to 27); + lua_t(1 to 37) <= ex4_tbl_sum(1 to 37) or ex4_tbl_car(1 to 37); + lua_g(1 to 38) <= ex4_tbl_sum(1 to 38) and ex4_tbl_car(1 to 38); + + -- LOCAL BYTE CARRY -------------------------------------------------- + + + lua_g2(38) <= lua_g(38) ; + lua_g2(37) <= lua_g(37) or (lua_t(37) and lua_g(38) ); + lua_g2(36) <= lua_g(36) or (lua_t(36) and lua_g(37) ); + lua_g2(35) <= lua_g(35) or (lua_t(35) and lua_g(36) ); + lua_g2(34) <= lua_g(34) or (lua_t(34) and lua_g(35) ); + lua_g2(33) <= lua_g(33) or (lua_t(33) and lua_g(34) ); + lua_g2(32) <= lua_g(32) or (lua_t(32) and lua_g(33) ); + lua_t2(36) <= lua_t(36) and lua_t(37) ; + lua_t2(35) <= lua_t(35) and lua_t(36) ; + lua_t2(34) <= lua_t(34) and lua_t(35) ; + lua_t2(33) <= lua_t(33) and lua_t(34) ; + lua_t2(32) <= lua_t(32) and lua_t(33) ; + lua_g4(36) <= lua_g2(36) or (lua_t2(36) and lua_g2(38) ); + lua_g4(35) <= lua_g2(35) or (lua_t2(35) and lua_g2(37) ); + lua_g4(34) <= lua_g2(34) or (lua_t2(34) and lua_g2(36) ); + lua_g4(33) <= lua_g2(33) or (lua_t2(33) and lua_g2(35) ); + lua_g4(32) <= lua_g2(32) or (lua_t2(32) and lua_g2(34) ); + lua_t4(32) <= lua_t2(32) and lua_t2(34) ; + lua_g8(32) <= lua_g4(32) or (lua_t4(32) and lua_g4(36) ); + + + + + lua_g2(31) <= lua_g(31) ; + lua_g2(30) <= lua_g(30) or (lua_t(30) and lua_g(31) ); + lua_g2(29) <= lua_g(29) or (lua_t(29) and lua_g(30) ); + lua_g2(28) <= lua_g(28) or (lua_t(28) and lua_g(29) ); + lua_g2(27) <= lua_g(27) or (lua_t(27) and lua_g(28) ); + lua_g2(26) <= lua_g(26) or (lua_t(26) and lua_g(27) ); + lua_g2(25) <= lua_g(25) or (lua_t(25) and lua_g(26) ); + lua_g2(24) <= lua_g(24) or (lua_t(24) and lua_g(25) ); + lua_t2(31) <= lua_t(31) ; + lua_t2(30) <= lua_t(30) and lua_t(31) ; + lua_t2(29) <= lua_t(29) and lua_t(30) ; + lua_t2(28) <= lua_t(28) and lua_t(29) ; + lua_t2(27) <= lua_t(27) and lua_t(28) ; + lua_t2(26) <= lua_t(26) and lua_t(27) ; + lua_t2(25) <= lua_t(25) and lua_t(26) ; + lua_t2(24) <= lua_t(24) and lua_t(25) ; + lua_g4(31) <= lua_g2(31) ; + lua_g4(30) <= lua_g2(30) ; + lua_g4(29) <= lua_g2(29) or (lua_t2(29) and lua_g2(31) ); + lua_g4(28) <= lua_g2(28) or (lua_t2(28) and lua_g2(30) ); + lua_g4(27) <= lua_g2(27) or (lua_t2(27) and lua_g2(29) ); + lua_g4(26) <= lua_g2(26) or (lua_t2(26) and lua_g2(28) ); + lua_g4(25) <= lua_g2(25) or (lua_t2(25) and lua_g2(27) ); + lua_g4(24) <= lua_g2(24) or (lua_t2(24) and lua_g2(26) ); + lua_t4(31) <= lua_t2(31) ; + lua_t4(30) <= lua_t2(30) ; + lua_t4(29) <= lua_t2(29) and lua_t2(31) ; + lua_t4(28) <= lua_t2(28) and lua_t2(30) ; + lua_t4(27) <= lua_t2(27) and lua_t2(29) ; + lua_t4(26) <= lua_t2(26) and lua_t2(28) ; + lua_t4(25) <= lua_t2(25) and lua_t2(27) ; + lua_t4(24) <= lua_t2(24) and lua_t2(26) ; + lua_g8(31) <= lua_g4(31) ; + lua_g8(30) <= lua_g4(30) ; + lua_g8(29) <= lua_g4(29) ; + lua_g8(28) <= lua_g4(28) ; + lua_g8(27) <= lua_g4(27) or (lua_t4(27) and lua_g4(31) ); + lua_g8(26) <= lua_g4(26) or (lua_t4(26) and lua_g4(30) ); + lua_g8(25) <= lua_g4(25) or (lua_t4(25) and lua_g4(29) ); + lua_g8(24) <= lua_g4(24) or (lua_t4(24) and lua_g4(28) ); + lua_t8(28) <= lua_t4(28) ; + lua_t8(27) <= lua_t4(27) and lua_t4(31) ; + lua_t8(26) <= lua_t4(26) and lua_t4(30) ; + lua_t8(25) <= lua_t4(25) and lua_t4(29) ; + lua_t8(24) <= lua_t4(24) and lua_t4(28) ; + + + + + lua_g2(23) <= lua_g(23) ; + lua_g2(22) <= lua_g(22) or (lua_t(22) and lua_g(23) ); + lua_g2(21) <= lua_g(21) or (lua_t(21) and lua_g(22) ); + lua_g2(20) <= lua_g(20) or (lua_t(20) and lua_g(21) ); + lua_g2(19) <= lua_g(19) or (lua_t(19) and lua_g(20) ); + lua_g2(18) <= lua_g(18) or (lua_t(18) and lua_g(19) ); + lua_g2(17) <= lua_g(17) or (lua_t(17) and lua_g(18) ); + lua_g2(16) <= lua_g(16) or (lua_t(16) and lua_g(17) ); + lua_t2(23) <= lua_t(23) ; + lua_t2(22) <= lua_t(22) and lua_t(23) ; + lua_t2(21) <= lua_t(21) and lua_t(22) ; + lua_t2(20) <= lua_t(20) and lua_t(21) ; + lua_t2(19) <= lua_t(19) and lua_t(20) ; + lua_t2(18) <= lua_t(18) and lua_t(19) ; + lua_t2(17) <= lua_t(17) and lua_t(18) ; + lua_t2(16) <= lua_t(16) and lua_t(17) ; + lua_g4(23) <= lua_g2(23) ; + lua_g4(22) <= lua_g2(22) ; + lua_g4(21) <= lua_g2(21) or (lua_t2(21) and lua_g2(23) ); + lua_g4(20) <= lua_g2(20) or (lua_t2(20) and lua_g2(22) ); + lua_g4(19) <= lua_g2(19) or (lua_t2(19) and lua_g2(21) ); + lua_g4(18) <= lua_g2(18) or (lua_t2(18) and lua_g2(20) ); + lua_g4(17) <= lua_g2(17) or (lua_t2(17) and lua_g2(19) ); + lua_g4(16) <= lua_g2(16) or (lua_t2(16) and lua_g2(18) ); + lua_t4(23) <= lua_t2(23) ; + lua_t4(22) <= lua_t2(22) ; + lua_t4(21) <= lua_t2(21) and lua_t2(23) ; + lua_t4(20) <= lua_t2(20) and lua_t2(22) ; + lua_t4(19) <= lua_t2(19) and lua_t2(21) ; + lua_t4(18) <= lua_t2(18) and lua_t2(20) ; + lua_t4(17) <= lua_t2(17) and lua_t2(19) ; + lua_t4(16) <= lua_t2(16) and lua_t2(18) ; + lua_g8(23) <= lua_g4(23) ; + lua_g8(22) <= lua_g4(22) ; + lua_g8(21) <= lua_g4(21) ; + lua_g8(20) <= lua_g4(20) ; + lua_g8(19) <= lua_g4(19) or (lua_t4(19) and lua_g4(23) ); + lua_g8(18) <= lua_g4(18) or (lua_t4(18) and lua_g4(22) ); + lua_g8(17) <= lua_g4(17) or (lua_t4(17) and lua_g4(21) ); + lua_g8(16) <= lua_g4(16) or (lua_t4(16) and lua_g4(20) ); + lua_t8(23) <= lua_t4(23) ; + lua_t8(22) <= lua_t4(22) ; + lua_t8(21) <= lua_t4(21) ; + lua_t8(20) <= lua_t4(20) ; + lua_t8(19) <= lua_t4(19) and lua_t4(23) ; + lua_t8(18) <= lua_t4(18) and lua_t4(22) ; + lua_t8(17) <= lua_t4(17) and lua_t4(21) ; + lua_t8(16) <= lua_t4(16) and lua_t4(20) ; + + + + + lua_g2(15) <= lua_g(15) ; + lua_g2(14) <= lua_g(14) or (lua_t(14) and lua_g(15) ); + lua_g2(13) <= lua_g(13) or (lua_t(13) and lua_g(14) ); + lua_g2(12) <= lua_g(12) or (lua_t(12) and lua_g(13) ); + lua_g2(11) <= lua_g(11) or (lua_t(11) and lua_g(12) ); + lua_g2(10) <= lua_g(10) or (lua_t(10) and lua_g(11) ); + lua_g2(9) <= lua_g(9) or (lua_t(9) and lua_g(10) ); + lua_g2(8) <= lua_g(8) or (lua_t(8) and lua_g(9) ); + lua_t2(15) <= lua_t(15) ; + lua_t2(14) <= lua_t(14) and lua_t(15) ; + lua_t2(13) <= lua_t(13) and lua_t(14) ; + lua_t2(12) <= lua_t(12) and lua_t(13) ; + lua_t2(11) <= lua_t(11) and lua_t(12) ; + lua_t2(10) <= lua_t(10) and lua_t(11) ; + lua_t2(9) <= lua_t(9) and lua_t(10) ; + lua_t2(8) <= lua_t(8) and lua_t(9) ; + lua_g4(15) <= lua_g2(15) ; + lua_g4(14) <= lua_g2(14) ; + lua_g4(13) <= lua_g2(13) or (lua_t2(13) and lua_g2(15) ); + lua_g4(12) <= lua_g2(12) or (lua_t2(12) and lua_g2(14) ); + lua_g4(11) <= lua_g2(11) or (lua_t2(11) and lua_g2(13) ); + lua_g4(10) <= lua_g2(10) or (lua_t2(10) and lua_g2(12) ); + lua_g4(9) <= lua_g2(9) or (lua_t2(9) and lua_g2(11) ); + lua_g4(8) <= lua_g2(8) or (lua_t2(8) and lua_g2(10) ); + lua_t4(15) <= lua_t2(15) ; + lua_t4(14) <= lua_t2(14) ; + lua_t4(13) <= lua_t2(13) and lua_t2(15) ; + lua_t4(12) <= lua_t2(12) and lua_t2(14) ; + lua_t4(11) <= lua_t2(11) and lua_t2(13) ; + lua_t4(10) <= lua_t2(10) and lua_t2(12) ; + lua_t4(9) <= lua_t2(9) and lua_t2(11) ; + lua_t4(8) <= lua_t2(8) and lua_t2(10) ; + lua_g8(15) <= lua_g4(15) ; + lua_g8(14) <= lua_g4(14) ; + lua_g8(13) <= lua_g4(13) ; + lua_g8(12) <= lua_g4(12) ; + lua_g8(11) <= lua_g4(11) or (lua_t4(11) and lua_g4(15) ); + lua_g8(10) <= lua_g4(10) or (lua_t4(10) and lua_g4(14) ); + lua_g8(9) <= lua_g4(9) or (lua_t4(9) and lua_g4(13) ); + lua_g8(8) <= lua_g4(8) or (lua_t4(8) and lua_g4(12) ); + lua_t8(15) <= lua_t4(15) ; + lua_t8(14) <= lua_t4(14) ; + lua_t8(13) <= lua_t4(13) ; + lua_t8(12) <= lua_t4(12) ; + lua_t8(11) <= lua_t4(11) and lua_t4(15) ; + lua_t8(10) <= lua_t4(10) and lua_t4(14) ; + lua_t8(9) <= lua_t4(9) and lua_t4(13) ; + lua_t8(8) <= lua_t4(8) and lua_t4(12) ; + + + + + lua_g2(7) <= lua_g(7) ; + lua_g2(6) <= lua_g(6) or (lua_t(6) and lua_g(7) ); + lua_g2(5) <= lua_g(5) or (lua_t(5) and lua_g(6) ); + lua_g2(4) <= lua_g(4) or (lua_t(4) and lua_g(5) ); + lua_g2(3) <= lua_g(3) or (lua_t(3) and lua_g(4) ); + lua_g2(2) <= lua_g(2) or (lua_t(2) and lua_g(3) ); + lua_g2(1) <= lua_g(1) or (lua_t(1) and lua_g(2) ); + lua_t2(7) <= lua_t(7) ; + lua_t2(6) <= lua_t(6) and lua_t(7) ; + lua_t2(5) <= lua_t(5) and lua_t(6) ; + lua_t2(4) <= lua_t(4) and lua_t(5) ; + lua_t2(3) <= lua_t(3) and lua_t(4) ; + lua_t2(2) <= lua_t(2) and lua_t(3) ; + lua_t2(1) <= lua_t(1) and lua_t(2) ; + lua_g4(7) <= lua_g2(7) ; + lua_g4(6) <= lua_g2(6) ; + lua_g4(5) <= lua_g2(5) or (lua_t2(5) and lua_g2(7) ); + lua_g4(4) <= lua_g2(4) or (lua_t2(4) and lua_g2(6) ); + lua_g4(3) <= lua_g2(3) or (lua_t2(3) and lua_g2(5) ); + lua_g4(2) <= lua_g2(2) or (lua_t2(2) and lua_g2(4) ); + lua_g4(1) <= lua_g2(1) or (lua_t2(1) and lua_g2(3) ); + lua_t4(7) <= lua_t2(7) ; + lua_t4(6) <= lua_t2(6) ; + lua_t4(5) <= lua_t2(5) and lua_t2(7) ; + lua_t4(4) <= lua_t2(4) and lua_t2(6) ; + lua_t4(3) <= lua_t2(3) and lua_t2(5) ; + lua_t4(2) <= lua_t2(2) and lua_t2(4) ; + lua_t4(1) <= lua_t2(1) and lua_t2(3) ; + lua_g8(7) <= lua_g4(7) ; + lua_g8(6) <= lua_g4(6) ; + lua_g8(5) <= lua_g4(5) ; + lua_g8(4) <= lua_g4(4) ; + lua_g8(3) <= lua_g4(3) or (lua_t4(3) and lua_g4(7) ); + lua_g8(2) <= lua_g4(2) or (lua_t4(2) and lua_g4(6) ); + lua_g8(1) <= lua_g4(1) or (lua_t4(1) and lua_g4(5) ); + lua_t8(7) <= lua_t4(7) ; + lua_t8(6) <= lua_t4(6) ; + lua_t8(5) <= lua_t4(5) ; + lua_t8(4) <= lua_t4(4) ; + lua_t8(3) <= lua_t4(3) and lua_t4(7) ; + lua_t8(2) <= lua_t4(2) and lua_t4(6) ; + lua_t8(1) <= lua_t4(1) and lua_t4(5) ; + + + + -- CONDITIONL SUM --------------------------------------------- + + lua_gt8(1 to 28) <= lua_g8(1 to 28) or lua_t8(1 to 28); + + lua_s1_b(0 to 27) <= not( lua_p(0 to 27) xor lua_gt8(1 to 28) ); + lua_s0_b(0 to 27) <= not( lua_p(0 to 27) xor lua_g8(1 to 28) ); + + + -- BYTE SELECT ------------------------------ + -- ex4_lu(0 to 27) <= not( ex4_lu_p(0 to 27) xor ex4_lu_c(1 to 28) ); -- invert + + ex4_lu( 0) <= ( lua_s0_b( 0) and not lua_c08 ) or ( lua_s1_b( 0) and lua_c08 ) ; + ex4_lu( 1) <= ( lua_s0_b( 1) and not lua_c08 ) or ( lua_s1_b( 1) and lua_c08 ) ; + ex4_lu( 2) <= ( lua_s0_b( 2) and not lua_c08 ) or ( lua_s1_b( 2) and lua_c08 ) ; + ex4_lu( 3) <= ( lua_s0_b( 3) and not lua_c08 ) or ( lua_s1_b( 3) and lua_c08 ) ; + ex4_lu( 4) <= ( lua_s0_b( 4) and not lua_c08 ) or ( lua_s1_b( 4) and lua_c08 ) ; + ex4_lu( 5) <= ( lua_s0_b( 5) and not lua_c08 ) or ( lua_s1_b( 5) and lua_c08 ) ; + ex4_lu( 6) <= ( lua_s0_b( 6) and not lua_c08 ) or ( lua_s1_b( 6) and lua_c08 ) ; + ex4_lu( 7) <= ( lua_s0_b( 7) and not lua_c08 ) or ( lua_s1_b( 7) and lua_c08 ) ; + + ex4_lu( 8) <= ( lua_s0_b( 8) and not lua_c16 ) or ( lua_s1_b( 8) and lua_c16 ) ; + ex4_lu( 9) <= ( lua_s0_b( 9) and not lua_c16 ) or ( lua_s1_b( 9) and lua_c16 ) ; + ex4_lu(10) <= ( lua_s0_b(10) and not lua_c16 ) or ( lua_s1_b(10) and lua_c16 ) ; + ex4_lu(11) <= ( lua_s0_b(11) and not lua_c16 ) or ( lua_s1_b(11) and lua_c16 ) ; + ex4_lu(12) <= ( lua_s0_b(12) and not lua_c16 ) or ( lua_s1_b(12) and lua_c16 ) ; + ex4_lu(13) <= ( lua_s0_b(13) and not lua_c16 ) or ( lua_s1_b(13) and lua_c16 ) ; + ex4_lu(14) <= ( lua_s0_b(14) and not lua_c16 ) or ( lua_s1_b(14) and lua_c16 ) ; + ex4_lu(15) <= ( lua_s0_b(15) and not lua_c16 ) or ( lua_s1_b(15) and lua_c16 ) ; + + ex4_lu(16) <= ( lua_s0_b(16) and not lua_c24 ) or ( lua_s1_b(16) and lua_c24 ) ; + ex4_lu(17) <= ( lua_s0_b(17) and not lua_c24 ) or ( lua_s1_b(17) and lua_c24 ) ; + ex4_lu(18) <= ( lua_s0_b(18) and not lua_c24 ) or ( lua_s1_b(18) and lua_c24 ) ; + ex4_lu(19) <= ( lua_s0_b(19) and not lua_c24 ) or ( lua_s1_b(19) and lua_c24 ) ; + ex4_lu(20) <= ( lua_s0_b(20) and not lua_c24 ) or ( lua_s1_b(20) and lua_c24 ) ; + ex4_lu(21) <= ( lua_s0_b(21) and not lua_c24 ) or ( lua_s1_b(21) and lua_c24 ) ; + ex4_lu(22) <= ( lua_s0_b(22) and not lua_c24 ) or ( lua_s1_b(22) and lua_c24 ) ; + ex4_lu(23) <= ( lua_s0_b(23) and not lua_c24 ) or ( lua_s1_b(23) and lua_c24 ) ; + + ex4_lu(24) <= ( lua_s0_b(24) and not lua_c32 ) or ( lua_s1_b(24) and lua_c32 ) ; + ex4_lu(25) <= ( lua_s0_b(25) and not lua_c32 ) or ( lua_s1_b(25) and lua_c32 ) ; + ex4_lu(26) <= ( lua_s0_b(26) and not lua_c32 ) or ( lua_s1_b(26) and lua_c32 ) ; + ex4_lu(27) <= ( lua_s0_b(27) and not lua_c32 ) or ( lua_s1_b(27) and lua_c32 ) ; + + -- GLOBAL BYTE CARRY ------------------------------ + + + lua_g16(3) <= lua_g8(32); + lua_g16(2) <= lua_g8(24) or ( lua_t8(24) and lua_g8(32) ); + lua_g16(1) <= lua_g8(16) or ( lua_t8(16) and lua_g8(24) ); + lua_g16(0) <= lua_g8( 8) or ( lua_t8( 8) and lua_g8(16) ); + + lua_t16(1) <= lua_t8(16) and lua_t8(24) ; + lua_t16(0) <= lua_t8( 8) and lua_t8(16) ; + + lua_c32 <= lua_g16(3); + lua_c24 <= lua_g16(2); + lua_c16 <= lua_g16(1) or ( lua_t16(1) and lua_g16(3) ); + lua_c08 <= lua_g16(0) or ( lua_t16(0) and lua_g16(2) ); + + ----------------------------------------------------------------- + -- normalize + ----------------------------------------------------------------- + -- expo=2046 ==> imp=0 shift right 1 + -- expo=2045 ==> imp=0 shift right 0 + -- expo=other => imp=1 shift right 0 + ex4_recip_2044_dp <= ex4_recip_2044 and ex4_match_en_dp and not ex4_recip_ue1; + ex4_recip_2045_dp <= ex4_recip_2045 and ex4_match_en_dp and not ex4_recip_ue1; + ex4_recip_2046_dp <= ex4_recip_2046 and ex4_match_en_dp and not ex4_recip_ue1; + + ex4_recip_2044_sp <= ex4_recip_2044 and ex4_match_en_sp and not ex4_recip_ue1; + ex4_recip_2045_sp <= ex4_recip_2045 and ex4_match_en_sp and not ex4_recip_ue1; + ex4_recip_2046_sp <= ex4_recip_2046 and ex4_match_en_sp and not ex4_recip_ue1; + + + + -- lu_sh means : shift left one, and decr exponent (unless it will create a denorm exponent) + + ex4_recip_den <= + ex4_recip_2046_sp or -- result in norm dp fmt, but set fpscr flag for sp unf + ex4_recip_2045_sp or -- result in norm dp fmt, but set fpscr flag for sp unf + (ex4_lu_sh and ex4_recip_2044_sp) or -- result in norm dp fmt, but set fpscr flag for sp unf + ex4_recip_2046_dp or -- use in round to set implicit bit + ex4_recip_2045_dp or + (ex4_lu_sh and ex4_recip_2044_dp); -- cannot shift left , denorm result + + + + + -- by not denormalizing sp the fpscr(ux) is set even though the implicit bit is set + -- divide does not want the denormed result + ex4_unf_expo <= -- for setting UX (same for ue=0, ue=1 + (ex4_match_en_sp or ex4_match_en_dp) and -- leave SP normalized + (ex4_recip_2046 or ex4_recip_2045 or ( ex4_recip_2044 and ex4_lu_sh ) ); + + f_tbl_ex4_unf_expo <= ex4_unf_expo ;--output-- + + ex4_shlft_1 <= not ex4_recip_2046_dp and not ex4_recip_2045_dp and (ex4_lu_sh and not ex4_recip_2044_dp); + ex4_shlft_0 <= not ex4_recip_2046_dp and not ex4_recip_2045_dp and not(ex4_lu_sh and not ex4_recip_2044_dp); + ex4_shrgt_1 <= ex4_recip_2045_dp ; + ex4_shrgt_2 <= ex4_recip_2046_dp ; + + + -- the final sp result will be in dp_norm format for an sp_denorm. + -- emulate the dropping of bits when an sp is shifted right then fitted into 23 frac bits. + + + ex4_sp_chop_24 <= ex4_recip_2046_sp or ex4_recip_2045_sp or ex4_recip_2044_sp ; + ex4_sp_chop_23 <= ex4_recip_2046_sp or ex4_recip_2045_sp ; + ex4_sp_chop_22 <= ex4_recip_2046_sp ; + ex4_sp_chop_21 <= tidn ; + + + ex4_lux(0 to 20) <= ex4_lu(0 to 20); + ex4_lux(21) <= ex4_lu(21) and not ex4_sp_chop_21; + ex4_lux(22) <= ex4_lu(22) and not ex4_sp_chop_22; + ex4_lux(23) <= ex4_lu(23) and not ex4_sp_chop_23; + ex4_lux(24) <= ex4_lu(24) and not ex4_sp_chop_24; + ex4_lux(25 to 27) <= ex4_lu(25 to 27) ; + + + + ex4_lu_nrm(0 to 26) <= + ( (0 to 26=> ex4_shlft_1) and ( ex4_lux(1 to 27) ) ) or + ( (0 to 26=> ex4_shlft_0) and ( ex4_lux(0 to 26) ) ) or + ( (0 to 26=> ex4_shrgt_1) and ( tidn & ex4_lux(0 to 25) ) ) or + ( (0 to 26=> ex4_shrgt_2) and (tidn & tidn & ex4_lux(0 to 24) ) ) ; + + + + + +--==############################################################## +--= ex5 latches +--==############################################################## + + ex5_lut_lat: tri_rlmreg_p generic map (width=> 28, expand_type => expand_type) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(5) , + mpw1_b => mpw1_b(5) , + mpw2_b => mpw2_b(1) , + vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_act, + thold_b => thold_0_b, + sg => sg_0, + scout => ex5_lut_so , + scin => ex5_lut_si , + ------------------- + din(0 to 26) => ex4_lu_nrm(0 to 26) , + din(27) => ex4_recip_den , + dout(0 to 26) => ex5_lu(0 to 26) , + dout(27) => ex5_recip_den ); + + f_tbl_ex5_est_frac(0 to 26) <= ex5_lu(0 to 26); + f_tbl_ex5_recip_den <= ex5_recip_den ; + + +--==############################################################## +--= pervasive +--==############################################################## + + thold_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => thold_1, + q(0) => thold_0 ); + + sg_reg_0: tri_plat generic map (expand_type => expand_type) port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => flush , + din(0) => sg_1 , + q(0) => sg_0 ); + + + lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map ( + clkoff_b => clkoff_b, + thold => thold_0, + sg => sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => thold_0_b ); + +--==############################################################## +--= act +--==############################################################## + + + act_lat: tri_rlmreg_p generic map (width=> 7, expand_type => expand_type) port map ( + forcee => forcee, + delay_lclkr => delay_lclkr(4) , + mpw1_b => mpw1_b(4) , + mpw2_b => mpw2_b(0) , + vd => vdd, + gd => gnd, + nclk => nclk, + act => fpu_enable, + thold_b => thold_0_b, + sg => sg_0, + scout => act_so , + scin => act_si , + ------------------- + din(0) => spare_unused(0), + din(1) => spare_unused(1), + din(2) => ex1_act, + din(3) => ex2_act, + din(4) => ex3_act, + din(5) => spare_unused(2), + din(6) => spare_unused(3), + ------------------- + dout(0) => spare_unused(0), + dout(1) => spare_unused(1), + dout(2) => ex2_act, + dout(3) => ex3_act, + dout(4) => ex4_act, + dout(5) => spare_unused(2) , + dout(6) => spare_unused(3) ); + + + tbl_ex3_lcb : tri_lcbnd generic map (expand_type => expand_type) port map( + delay_lclkr => delay_lclkr(3) ,-- tidn ,--in + mpw1_b => mpw1_b(3) ,-- tidn ,--in + mpw2_b => mpw2_b(0) ,-- tidn ,--in + forcee => forcee,-- tidn ,--in + nclk => nclk ,--in + vd => vdd ,--inout + gd => gnd ,--inout + act => ex2_act ,--in + sg => sg_0 ,--in + thold_b => thold_0_b ,--in + d1clk => tbl_ex3_d1clk ,--out + d2clk => tbl_ex3_d2clk ,--out + lclk => tbl_ex3_lclk );--out + + tbl_ex4_lcb : tri_lcbnd generic map (expand_type => expand_type) port map( + delay_lclkr => delay_lclkr(4) ,-- tidn ,--in + mpw1_b => mpw1_b(4) ,-- tidn ,--in + mpw2_b => mpw2_b(0) ,-- tidn ,--in + forcee => forcee,-- tidn ,--in + nclk => nclk ,--in + vd => vdd ,--inout + gd => gnd ,--inout + act => ex3_act ,--in + sg => sg_0 ,--in + thold_b => thold_0_b ,--in + d1clk => tbl_ex4_d1clk ,--out + d2clk => tbl_ex4_d2clk ,--out + lclk => tbl_ex4_lclk );--out + + + +--==############################################################## +--= scan string +--==############################################################## + + ex2_lut_si(0 to 5) <= ex2_lut_so(1 to 5) & si; + ex3_lut_e_si(0 to 19) <= ex3_lut_e_so(1 to 19) & ex2_lut_so(0); + ex3_lut_r_si(0 to 14) <= ex3_lut_r_so(1 to 14) & ex3_lut_e_so(0); + ex3_lut_b_si(0 to 15) <= ex3_lut_b_so(1 to 15) & ex3_lut_r_so(0); + ex4_lut_si(0 to 79) <= ex4_lut_so(1 to 79) & ex3_lut_b_so(0); + ex5_lut_si(0 to 27) <= ex5_lut_so(1 to 27) & ex4_lut_so(0); + act_si(0 to 6) <= act_so(1 to 6) & ex5_lut_so(0); + so <= act_so (0) ;--SCAN + + +end; -- fuq_tbllut ARCHITECTURE diff --git a/rel/src/vhdl/work/fuq_tblmul.vhdl b/rel/src/vhdl/work/fuq_tblmul.vhdl new file mode 100644 index 0000000..68170d7 --- /dev/null +++ b/rel/src/vhdl/work/fuq_tblmul.vhdl @@ -0,0 +1,1602 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; + use ieee.std_logic_1164.all ; +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; +library support; + use support.power_logic_pkg.all; +library tri; use tri.tri_latches_pkg.all; +library clib; + +entity fuq_tblmul is + generic( expand_type : integer := 2 ); -- 0 - ibm tech, 1 - other ); +port( + vdd :inout power_logic; + gnd :inout power_logic; + x :in std_ulogic_vector(1 to 15); -- rng from lookup (recode) + y :in std_ulogic_vector(7 to 22); -- b operand bits (shift) + z :in std_ulogic_vector(0 to 20); -- estimate from table + + -- multiplier output msb comes out at [6] + + tbl_sum :out std_ulogic_vector(0 to 36); + tbl_car :out std_ulogic_vector(0 to 35) +); + + +end fuq_tblmul; -- ENTITY + +architecture fuq_tblmul of fuq_tblmul is + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal sub_adj_lsb, sub_adj_lsb_b :std_ulogic_vector(1 to 7); + signal sub_adj_msb_b :std_ulogic_vector(1 to 7); + signal sub_adj_msb_7x_b, sub_adj_msb_7x, sub_adj_msb_7y :std_ulogic; + signal s_x, s_x2, s_neg :std_ulogic_vector(0 to 7); + + signal pp0_0 :std_ulogic_vector( 6 to 24); + signal pp0_1 :std_ulogic_vector( 6 to 26); + signal pp0_2 :std_ulogic_vector( 8 to 28); + signal pp0_3 :std_ulogic_vector(10 to 30); + signal pp0_4 :std_ulogic_vector(12 to 32); + signal pp0_5 :std_ulogic_vector(14 to 34); + signal pp0_6 :std_ulogic_vector(16 to 36); + signal pp0_7 :std_ulogic_vector(17 to 36); + + + signal pp1_0_sum :std_ulogic_vector(0 to 26); + signal pp1_0_car :std_ulogic_vector(0 to 24); + signal pp1_1_sum :std_ulogic_vector(8 to 32); + signal pp1_1_car :std_ulogic_vector(9 to 30); + signal pp1_2_sum :std_ulogic_vector(14 to 36); + signal pp1_2_car :std_ulogic_vector(15 to 36); + signal pp1_0_car_unused :std_ulogic; + + + signal pp2_0_sum :std_ulogic_vector(0 to 32); + signal pp2_0_car :std_ulogic_vector(0 to 26); + signal pp2_1_sum :std_ulogic_vector(9 to 36); + signal pp2_1_car :std_ulogic_vector(13 to 36); + signal pp2_0_car_unused :std_ulogic; + + + signal pp3_0_sum :std_ulogic_vector(0 to 36); + signal pp3_0_ko :std_ulogic_vector(8 to 25); + signal pp3_0_car :std_ulogic_vector(0 to 35); + signal pp3_0_car_unused :std_ulogic; + signal z_b :std_ulogic_vector(0 to 20); + signal unused :std_ulogic; + + + + + + + + +begin + + unused <= pp1_0_car_unused or + pp2_0_car_unused or + pp3_0_car_unused or + pp0_0(23) or + pp0_1(25) or + pp0_2(27) or + pp0_3(29) or + pp0_4(31) or + pp0_5(33) or + pp0_6(35) or + pp1_0_car(23) or + pp1_0_sum(25) or + pp1_1_car(28) or + pp1_1_sum(31) or + pp1_2_car(34) or + pp2_0_car(24) or + pp2_0_sum(31) or + pp2_1_car(30) or + pp2_1_car(34) or + s_neg(0) or + pp1_1_car(29) or + pp1_2_car(35) or + pp2_0_car(25) or + pp2_1_car(35) ; + + + +--=################################################# +--= Booth Decoders +--=################################################# +-- 0 1 2 3 4 5 6 7 +-- (x,1) (2,3) (4,5) (6,7) (8,9) (10,11) (12,13) (14,15) + + bd0: entity work.fuq_tblmul_bthdcd(fuq_tblmul_bthdcd) port map( + i0 => tidn ,--i-- + i1 => x(1) ,--i-- + i2 => x(2) ,--i-- + s_neg => s_neg(0) ,--o-- + s_x => s_x(0) ,--o-- + s_x2 => s_x2(0) );--o-- + + bd1: entity work.fuq_tblmul_bthdcd(fuq_tblmul_bthdcd) port map( + i0 => x(2) ,--i-- + i1 => x(3) ,--i-- + i2 => x(4) ,--i-- + s_neg => s_neg(1) ,--o-- + s_x => s_x(1) ,--o-- + s_x2 => s_x2(1) );--o-- + + bd2: entity work.fuq_tblmul_bthdcd(fuq_tblmul_bthdcd) port map( + i0 => x(4) ,--i-- + i1 => x(5) ,--i-- + i2 => x(6) ,--i-- + s_neg => s_neg(2) ,--o-- + s_x => s_x(2) ,--o-- + s_x2 => s_x2(2) );--o-- + + bd3: entity work.fuq_tblmul_bthdcd(fuq_tblmul_bthdcd) port map( + i0 => x(6) ,--i-- + i1 => x(7) ,--i-- + i2 => x(8) ,--i-- + s_neg => s_neg(3) ,--o-- + s_x => s_x(3) ,--o-- + s_x2 => s_x2(3) );--o-- + + bd4: entity work.fuq_tblmul_bthdcd(fuq_tblmul_bthdcd) port map( + i0 => x(8) ,--i-- + i1 => x(9) ,--i-- + i2 => x(10) ,--i-- + s_neg => s_neg(4) ,--o-- + s_x => s_x(4) ,--o-- + s_x2 => s_x2(4) );--o-- + + bd5: entity work.fuq_tblmul_bthdcd(fuq_tblmul_bthdcd) port map( + i0 => x(10) ,--i-- + i1 => x(11) ,--i-- + i2 => x(12) ,--i-- + s_neg => s_neg(5) ,--o-- + s_x => s_x(5) ,--o-- + s_x2 => s_x2(5) );--o-- + + bd6: entity work.fuq_tblmul_bthdcd(fuq_tblmul_bthdcd) port map( + i0 => x(12) ,--i-- + i1 => x(13) ,--i-- + i2 => x(14) ,--i-- + s_neg => s_neg(6) ,--o-- + s_x => s_x(6) ,--o-- + s_x2 => s_x2(6) );--o-- + + bd7: entity work.fuq_tblmul_bthdcd(fuq_tblmul_bthdcd) port map( + i0 => x(14) ,--i-- + i1 => x(15) ,--i-- + i2 => tidn ,--i-- + s_neg => s_neg(7) ,--o-- + s_x => s_x(7) ,--o-- + s_x2 => s_x2(7) );--o-- + + + + +--=############################################################### +--= booth muxes +--=############################################################### + +--= NUMBERING SYSTEM RELATIVE TO COMPRESSOR TREE +--= +--= 00000000000000000000000000000000000000 +--= 00000000001111111111222222222233333333 +--= 01234567890123456789012345678901234567 +--= 0 .......DddddddddddddddddD0s................ +--= 1 .......1aDddddddddddddddddD0s.............. +--= 2 .........1aDddddddddddddddddD0s............ +--= 3 ...........1aDddddddddddddddddD0s.......... +--= 4 .............1aDddddddddddddddddD0s........ +--= 5 ...............1aDddddddddddddddddD0s...... +--= 6 .................1aDddddddddddddddddD0s.... +--= 7 ..................assDddddddddddddddddD.... +--= EST dddddddddddddddddddd (the ass from sgnXtd.7 is already added into the est. +--= +--=############################ +--= want (est - mult ) +--= will calc -(r - e) = -(r + !e + 1) +--= = -(r + !e) -1 +--= = !(r + !e) + 1 - 1 +--= = !(r + !e) +--= = !(R + ASS + !e) ... seperate out the overlapping SGNxtd piece +--= = !(R + (ASS + !e)) .... invert the final adder output +--= +--= table estimate will be : ADD !e + 100 +--= SUB !e + 011 +--= +--= more "0" in table if read out POS version of est, then invert +--= +--= !e + adj = -e -1 + adj +--= = -(e +1 -adj) +--= = -(e -adj) -1 +--= = !(e -adj) +1 -1 +--= = !(e -adj) ... invert the table input + + sa1_1_lsb: sub_adj_lsb_b(1) <= not( s_neg(1) and ( s_x(1) or s_x2(1) ) ); + sa2_1_lsb: sub_adj_lsb_b(2) <= not( s_neg(2) and ( s_x(2) or s_x2(2) ) ); + sa3_1_lsb: sub_adj_lsb_b(3) <= not( s_neg(3) and ( s_x(3) or s_x2(3) ) ); + sa4_1_lsb: sub_adj_lsb_b(4) <= not( s_neg(4) and ( s_x(4) or s_x2(4) ) ); + sa5_1_lsb: sub_adj_lsb_b(5) <= not( s_neg(5) and ( s_x(5) or s_x2(5) ) ); + sa6_1_lsb: sub_adj_lsb_b(6) <= not( s_neg(6) and ( s_x(6) or s_x2(6) ) ); + sa7_1_lsb: sub_adj_lsb_b(7) <= not( s_neg(7) and ( s_x(7) or s_x2(7) ) ); + + sa1_2_lsb: sub_adj_lsb (1) <= not sub_adj_lsb_b(1); + sa2_2_lsb: sub_adj_lsb (2) <= not sub_adj_lsb_b(2); + sa3_2_lsb: sub_adj_lsb (3) <= not sub_adj_lsb_b(3); + sa4_2_lsb: sub_adj_lsb (4) <= not sub_adj_lsb_b(4); + sa5_2_lsb: sub_adj_lsb (5) <= not sub_adj_lsb_b(5); + sa6_2_lsb: sub_adj_lsb (6) <= not sub_adj_lsb_b(6); + sa7_2_lsb: sub_adj_lsb (7) <= not sub_adj_lsb_b(7); + + sa1_1_msb: sub_adj_msb_b(1) <= not( s_neg(1) and ( s_x(1) or s_x2(1) ) ); + sa2_1_msb: sub_adj_msb_b(2) <= not( s_neg(2) and ( s_x(2) or s_x2(2) ) ); + sa3_1_msb: sub_adj_msb_b(3) <= not( s_neg(3) and ( s_x(3) or s_x2(3) ) ); + sa4_1_msb: sub_adj_msb_b(4) <= not( s_neg(4) and ( s_x(4) or s_x2(4) ) ); + sa5_1_msb: sub_adj_msb_b(5) <= not( s_neg(5) and ( s_x(5) or s_x2(5) ) ); + sa6_1_msb: sub_adj_msb_b(6) <= not( s_neg(6) and ( s_x(6) or s_x2(6) ) ); + sa7_1_msb: sub_adj_msb_b(7) <= not( s_neg(7) and ( s_x(7) or s_x2(7) ) ); + sa7x_1_msb: sub_adj_msb_7x_b <= not( s_neg(7) and ( s_x(7) or s_x2(7) ) ); + + sa7x_2_msb: sub_adj_msb_7x <= not sub_adj_msb_7x_b ; + sa7y_2_msb: sub_adj_msb_7y <= not sub_adj_msb_7x_b ; + + + bm0: entity work.fuq_tblmul_bthrow(fuq_tblmul_bthrow) port map( + s_neg => tidn ,--i-- (tidn) msb term is never sub + s_x => s_x(0) ,--i-- + s_x2 => s_x2(0) ,--i-- + x => y(7 to 22) ,--i-- + q => pp0_0(6 to 22) );--o-- + pp0_0(23) <= tidn; + pp0_0(24) <= sub_adj_lsb(1); + + pp0_1(6) <= tiup; + pp0_1(7) <= sub_adj_msb_b(1); + bm1: entity work.fuq_tblmul_bthrow(fuq_tblmul_bthrow) port map( + s_neg => s_neg(1) ,--i-- + s_x => s_x(1) ,--i-- + s_x2 => s_x2(1) ,--i-- + x => y(7 to 22) ,--i-- + q => pp0_1(8 to 24) );--o-- + pp0_1(25) <= tidn; + pp0_1(26) <= sub_adj_lsb(2); + + pp0_2(8) <= tiup; + pp0_2(9) <= sub_adj_msb_b(2); + bm2: entity work.fuq_tblmul_bthrow(fuq_tblmul_bthrow) port map( + s_neg => s_neg(2) ,--i-- + s_x => s_x(2) ,--i-- + s_x2 => s_x2(2) ,--i-- + x => y(7 to 22) ,--i-- + q => pp0_2(10 to 26) );--o-- + pp0_2(27) <= tidn; + pp0_2(28) <= sub_adj_lsb(3); + + pp0_3(10) <= tiup; + pp0_3(11) <= sub_adj_msb_b(3); + bm3: entity work.fuq_tblmul_bthrow(fuq_tblmul_bthrow) port map( + s_neg => s_neg(3) ,--i-- + s_x => s_x(3) ,--i-- + s_x2 => s_x2(3) ,--i-- + x => y(7 to 22) ,--i-- + q => pp0_3(12 to 28) );--o-- + pp0_3(29) <= tidn; + pp0_3(30) <= sub_adj_lsb(4); + + pp0_4(12) <= tiup; + pp0_4(13) <= sub_adj_msb_b(4); + bm4: entity work.fuq_tblmul_bthrow(fuq_tblmul_bthrow) port map( + s_neg => s_neg(4) ,--i-- + s_x => s_x(4) ,--i-- + s_x2 => s_x2(4) ,--i-- + x => y(7 to 22) ,--i-- + q => pp0_4(14 to 30) );--o-- + pp0_4(31) <= tidn; + pp0_4(32) <= sub_adj_lsb(5); + + pp0_5(14) <= tiup; + pp0_5(15) <= sub_adj_msb_b(5); + bm5: entity work.fuq_tblmul_bthrow(fuq_tblmul_bthrow) port map( + s_neg => s_neg(5) ,--i-- + s_x => s_x(5) ,--i-- + s_x2 => s_x2(5) ,--i-- + x => y(7 to 22) ,--i-- + q => pp0_5(16 to 32) );--o-- + pp0_5(33) <= tidn; + pp0_5(34) <= sub_adj_lsb(6); + + pp0_6(16) <= tiup; + pp0_6(17) <= sub_adj_msb_b(6); + bm6: entity work.fuq_tblmul_bthrow(fuq_tblmul_bthrow) port map( + s_neg => s_neg(6) ,--i-- + s_x => s_x(6) ,--i-- + s_x2 => s_x2(6) ,--i-- + x => y(7 to 22) ,--i-- + q => pp0_6(18 to 34) );--o-- + pp0_6(35) <= tidn; + pp0_6(36) <= sub_adj_lsb(7); + + pp0_7(17) <= sub_adj_msb_b(7); + pp0_7(18) <= sub_adj_msb_7x; + pp0_7(19) <= sub_adj_msb_7y; + bm7: entity work.fuq_tblmul_bthrow(fuq_tblmul_bthrow) port map( + s_neg => s_neg(7) ,--i-- + s_x => s_x(7) ,--i-- + s_x2 => s_x2(7) ,--i-- + x => y(7 to 22) ,--i-- + q => pp0_7(20 to 36) );--o-- + + + +--=#################################################################### +--=# compressor tree level 1 +--=#################################################################### +--= 0 1 2 3 +--= 0123456789012345678901234567890123456 +--==------------------------------------- +-- ddddddddddddddddddddd________________ +-- 111111ddddddddddddddddd_S____________ bm0 +-- ______1addddddddddddddddd_S__________ bm1 +-- ________1addddddddddddddddd_S________ bm2 +-- __________1addddddddddddddddd_S______ bm3 +-- ____________1addddddddddddddddd_S____ bm4 +-- ______________1addddddddddddddddd_S__ bm5 +-- ________________1addddddddddddddddd_S bm6 +-- _________________assddddddddddddddddd bm7 + +--= 0 1 2 3 +--= 0123456789012345678901234567890123456 +--==------------------------------------- +-- ddddddddddddddddddddd________________ +-- 111111ddddddddddddddddd_S____________ bm0 +-- ______1addddddddddddddddd_S__________ bm1 +-- 111111333333333333333221201 +-- sssssssssssssssssssssssss_s pp1_0_sum +-- ccccccccccccccccccccccc_c__ pp1_0_car + + +--= 0 1 2 3 +--= 0123456789012345678901234567890123456 +--==------------------------------------- +-- ________1addddddddddddddddd_S________ bm2 +-- __________1addddddddddddddddd_S______ bm3 +-- ____________1addddddddddddddddd_S____ bm4 +-- 1122333333333333333231201 +-- ________sssssssssssssssssssssss_s pp1_1_sum +-- _ccccccccccccccccccc__c__ pp1_1_car + +--= 0 1 2 3 +--= 0123456789012345678901234567890123456 +--==------------------------------------- +-- ______________1addddddddddddddddd_S__ bm5 +-- ________________1addddddddddddddddd_S bm6 +-- _________________assddddddddddddddddd bm7 +-- 11233333333333333332312 +-- sssssssssssssssssssssss pp1_2_sum +-- _ccccccccccccccccccc__c pp1_2_car + + + z_b(0 to 20) <= not z(0 to 20); + +--====================================================== +--== compressor level 1 , row 0 +--====================================================== + + pp1_0_sum(26) <= pp0_1(26) ; + pp1_0_sum(25) <= tidn ; + pp1_0_sum(24) <= pp0_0(24) ; + pp1_0_car(24) <= pp0_1(24) ; + pp1_0_sum(23) <= pp0_1(23) ; + pp1_0_car(23) <= tidn ; + pp1_0_sum(22) <= pp0_0(22) ; + pp1_0_car(22) <= pp0_1(22) ; + pp1_0_sum(21) <= pp0_0(21) ; + pp1_0_car(21) <= pp0_1(21) ; + pp1_0_car(20) <= tidn ; + pp1_0_csa_20: entity clib.c_prism_csa32 port map( -- MLT32_X1_A12TH + vd => vdd, + gd => gnd, + a => z_b(20) ,--i-- + b => pp0_0(20) ,--i-- + c => pp0_1(20) ,--i-- + sum => pp1_0_sum(20) ,--o-- + car => pp1_0_car(19) );--o-- + pp1_0_csa_19: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => z_b(19) ,--i-- + b => pp0_0(19) ,--i-- + c => pp0_1(19) ,--i-- + sum => pp1_0_sum(19) ,--o-- + car => pp1_0_car(18) );--o-- + pp1_0_csa_18: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => z_b(18) ,--i-- + b => pp0_0(18) ,--i-- + c => pp0_1(18) ,--i-- + sum => pp1_0_sum(18) ,--o-- + car => pp1_0_car(17) );--o-- + pp1_0_csa_17: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => z_b(17) ,--i-- + b => pp0_0(17) ,--i-- + c => pp0_1(17) ,--i-- + sum => pp1_0_sum(17) ,--o-- + car => pp1_0_car(16) );--o-- + pp1_0_csa_16: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => z_b(16) ,--i-- + b => pp0_0(16) ,--i-- + c => pp0_1(16) ,--i-- + sum => pp1_0_sum(16) ,--o-- + car => pp1_0_car(15) );--o-- + pp1_0_csa_15: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => z_b(15) ,--i-- + b => pp0_0(15) ,--i-- + c => pp0_1(15) ,--i-- + sum => pp1_0_sum(15) ,--o-- + car => pp1_0_car(14) );--o-- + pp1_0_csa_14: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => z_b(14) ,--i-- + b => pp0_0(14) ,--i-- + c => pp0_1(14) ,--i-- + sum => pp1_0_sum(14) ,--o-- + car => pp1_0_car(13) );--o-- + pp1_0_csa_13: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => z_b(13) ,--i-- + b => pp0_0(13) ,--i-- + c => pp0_1(13) ,--i-- + sum => pp1_0_sum(13) ,--o-- + car => pp1_0_car(12) );--o-- + pp1_0_csa_12: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => z_b(12) ,--i-- + b => pp0_0(12) ,--i-- + c => pp0_1(12) ,--i-- + sum => pp1_0_sum(12) ,--o-- + car => pp1_0_car(11) );--o-- + pp1_0_csa_11: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => z_b(11) ,--i-- + b => pp0_0(11) ,--i-- + c => pp0_1(11) ,--i-- + sum => pp1_0_sum(11) ,--o-- + car => pp1_0_car(10) );--o-- + pp1_0_csa_10: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => z_b(10) ,--i-- + b => pp0_0(10) ,--i-- + c => pp0_1(10) ,--i-- + sum => pp1_0_sum(10) ,--o-- + car => pp1_0_car(9) );--o-- + pp1_0_csa_9: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => z_b(9) ,--i-- + b => pp0_0(9) ,--i-- + c => pp0_1(9) ,--i-- + sum => pp1_0_sum(9) ,--o-- + car => pp1_0_car(8) );--o-- + pp1_0_csa_8: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => z_b(8) ,--i-- + b => pp0_0(8) ,--i-- + c => pp0_1(8) ,--i-- + sum => pp1_0_sum(8) ,--o-- + car => pp1_0_car(7) );--o-- + pp1_0_csa_7: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => z_b(7) ,--i-- + b => pp0_0(7) ,--i-- + c => pp0_1(7) ,--i-- + sum => pp1_0_sum(7) ,--o-- + car => pp1_0_car(6) );--o-- + pp1_0_csa_6: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => z_b(6) ,--i-- + b => pp0_0(6) ,--i-- + c => pp0_1(6) ,--i-- + sum => pp1_0_sum(6) ,--o-- + car => pp1_0_car(5) );--o-- + pp1_0_csa_5: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => z_b(5) ,--i-- + b => tiup ,--i-- + sum => pp1_0_sum(5) ,--o-- + car => pp1_0_car(4) );--o-- + pp1_0_csa_4: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => z_b(4) ,--i-- + b => tiup ,--i-- + sum => pp1_0_sum(4) ,--o-- + car => pp1_0_car(3) );--o-- + pp1_0_csa_3: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => z_b(3) ,--i-- + b => tiup ,--i-- + sum => pp1_0_sum(3) ,--o-- + car => pp1_0_car(2) );--o-- + pp1_0_csa_2: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => z_b(2) ,--i-- + b => tiup ,--i-- + sum => pp1_0_sum(2) ,--o-- + car => pp1_0_car(1) );--o-- + pp1_0_csa_1: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => z_b(1) ,--i-- + b => tiup ,--i-- + sum => pp1_0_sum(1) ,--o-- + car => pp1_0_car(0) );--o-- + pp1_0_csa_0: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => z_b(0) ,--i-- + b => tiup ,--i-- + sum => pp1_0_sum(0) ,--o-- + car => pp1_0_car_unused );--o-- + + +--====================================================== +--== compressor level 1 , row 1 +--====================================================== + + pp1_1_sum(32) <= pp0_4(32) ; + pp1_1_sum(31) <= tidn ; + pp1_1_sum(30) <= pp0_3(30) ; + pp1_1_car(30) <= pp0_4(30) ; + pp1_1_sum(29) <= pp0_4(29) ; + pp1_1_car(29) <= tidn ; + pp1_1_car(28) <= tidn ; + pp1_1_csa_28: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_2(28) ,--i-- + b => pp0_3(28) ,--i-- + c => pp0_4(28) ,--i-- + sum => pp1_1_sum(28) ,--o-- + car => pp1_1_car(27) );--o-- + pp1_1_csa_27: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp0_3(27) ,--i-- + b => pp0_4(27) ,--i-- + sum => pp1_1_sum(27) ,--o-- + car => pp1_1_car(26) );--o-- + pp1_1_csa_26: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_2(26) ,--i-- + b => pp0_3(26) ,--i-- + c => pp0_4(26) ,--i-- + sum => pp1_1_sum(26) ,--o-- + car => pp1_1_car(25) );--o-- + pp1_1_csa_25: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_2(25) ,--i-- + b => pp0_3(25) ,--i-- + c => pp0_4(25) ,--i-- + sum => pp1_1_sum(25) ,--o-- + car => pp1_1_car(24) );--o-- + pp1_1_csa_24: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_2(24) ,--i-- + b => pp0_3(24) ,--i-- + c => pp0_4(24) ,--i-- + sum => pp1_1_sum(24) ,--o-- + car => pp1_1_car(23) );--o-- + pp1_1_csa_23: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_2(23) ,--i-- + b => pp0_3(23) ,--i-- + c => pp0_4(23) ,--i-- + sum => pp1_1_sum(23) ,--o-- + car => pp1_1_car(22) );--o-- + pp1_1_csa_22: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_2(22) ,--i-- + b => pp0_3(22) ,--i-- + c => pp0_4(22) ,--i-- + sum => pp1_1_sum(22) ,--o-- + car => pp1_1_car(21) );--o-- + pp1_1_csa_21: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_2(21) ,--i-- + b => pp0_3(21) ,--i-- + c => pp0_4(21) ,--i-- + sum => pp1_1_sum(21) ,--o-- + car => pp1_1_car(20) );--o-- + pp1_1_csa_20: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_2(20) ,--i-- + b => pp0_3(20) ,--i-- + c => pp0_4(20) ,--i-- + sum => pp1_1_sum(20) ,--o-- + car => pp1_1_car(19) );--o-- + pp1_1_csa_19: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_2(19) ,--i-- + b => pp0_3(19) ,--i-- + c => pp0_4(19) ,--i-- + sum => pp1_1_sum(19) ,--o-- + car => pp1_1_car(18) );--o-- + pp1_1_csa_18: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_2(18) ,--i-- + b => pp0_3(18) ,--i-- + c => pp0_4(18) ,--i-- + sum => pp1_1_sum(18) ,--o-- + car => pp1_1_car(17) );--o-- + pp1_1_csa_17: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_2(17) ,--i-- + b => pp0_3(17) ,--i-- + c => pp0_4(17) ,--i-- + sum => pp1_1_sum(17) ,--o-- + car => pp1_1_car(16) );--o-- + pp1_1_csa_16: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_2(16) ,--i-- + b => pp0_3(16) ,--i-- + c => pp0_4(16) ,--i-- + sum => pp1_1_sum(16) ,--o-- + car => pp1_1_car(15) );--o-- + pp1_1_csa_15: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_2(15) ,--i-- + b => pp0_3(15) ,--i-- + c => pp0_4(15) ,--i-- + sum => pp1_1_sum(15) ,--o-- + car => pp1_1_car(14) );--o-- + pp1_1_csa_14: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_2(14) ,--i-- + b => pp0_3(14) ,--i-- + c => pp0_4(14) ,--i-- + sum => pp1_1_sum(14) ,--o-- + car => pp1_1_car(13) );--o-- + pp1_1_csa_13: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_2(13) ,--i-- + b => pp0_3(13) ,--i-- + c => pp0_4(13) ,--i-- + sum => pp1_1_sum(13) ,--o-- + car => pp1_1_car(12) );--o-- + pp1_1_csa_12: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_2(12) ,--i-- + b => pp0_3(12) ,--i-- + c => pp0_4(12) ,--i-- + sum => pp1_1_sum(12) ,--o-- + car => pp1_1_car(11) );--o-- + pp1_1_csa_11: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp0_2(11) ,--i-- + b => pp0_3(11) ,--i-- + sum => pp1_1_sum(11) ,--o-- + car => pp1_1_car(10) );--o-- + pp1_1_csa_10: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp0_2(10) ,--i-- + b => pp0_3(10) ,--i-- + sum => pp1_1_sum(10) ,--o-- + car => pp1_1_car(9) );--o-- + pp1_1_sum(9) <= pp0_2(9) ; + pp1_1_sum(8) <= pp0_2(8) ; + + +--====================================================== +--== compressor level 1 , row 2 +--====================================================== + + pp1_2_sum(36) <= pp0_6(36) ; + pp1_2_car(36) <= pp0_7(36) ; + pp1_2_sum(35) <= pp0_7(35) ; + pp1_2_car(35) <= tidn ; + pp1_2_car(34) <= tidn ; + pp1_2_csa_34: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_5(34) ,--i-- + b => pp0_6(34) ,--i-- + c => pp0_7(34) ,--i-- + sum => pp1_2_sum(34) ,--o-- + car => pp1_2_car(33) );--o-- + pp1_2_csa_33: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp0_6(33) ,--i-- + b => pp0_7(33) ,--i-- + sum => pp1_2_sum(33) ,--o-- + car => pp1_2_car(32) );--o-- + pp1_2_csa_32: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_5(32) ,--i-- + b => pp0_6(32) ,--i-- + c => pp0_7(32) ,--i-- + sum => pp1_2_sum(32) ,--o-- + car => pp1_2_car(31) );--o-- + pp1_2_csa_31: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_5(31) ,--i-- + b => pp0_6(31) ,--i-- + c => pp0_7(31) ,--i-- + sum => pp1_2_sum(31) ,--o-- + car => pp1_2_car(30) );--o-- + pp1_2_csa_30: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_5(30) ,--i-- + b => pp0_6(30) ,--i-- + c => pp0_7(30) ,--i-- + sum => pp1_2_sum(30) ,--o-- + car => pp1_2_car(29) );--o-- + pp1_2_csa_29: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_5(29) ,--i-- + b => pp0_6(29) ,--i-- + c => pp0_7(29) ,--i-- + sum => pp1_2_sum(29) ,--o-- + car => pp1_2_car(28) );--o-- + pp1_2_csa_28: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_5(28) ,--i-- + b => pp0_6(28) ,--i-- + c => pp0_7(28) ,--i-- + sum => pp1_2_sum(28) ,--o-- + car => pp1_2_car(27) );--o-- + pp1_2_csa_27: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_5(27) ,--i-- + b => pp0_6(27) ,--i-- + c => pp0_7(27) ,--i-- + sum => pp1_2_sum(27) ,--o-- + car => pp1_2_car(26) );--o-- + pp1_2_csa_26: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_5(26) ,--i-- + b => pp0_6(26) ,--i-- + c => pp0_7(26) ,--i-- + sum => pp1_2_sum(26) ,--o-- + car => pp1_2_car(25) );--o-- + pp1_2_csa_25: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_5(25) ,--i-- + b => pp0_6(25) ,--i-- + c => pp0_7(25) ,--i-- + sum => pp1_2_sum(25) ,--o-- + car => pp1_2_car(24) );--o-- + pp1_2_csa_24: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_5(24) ,--i-- + b => pp0_6(24) ,--i-- + c => pp0_7(24) ,--i-- + sum => pp1_2_sum(24) ,--o-- + car => pp1_2_car(23) );--o-- + pp1_2_csa_23: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_5(23) ,--i-- + b => pp0_6(23) ,--i-- + c => pp0_7(23) ,--i-- + sum => pp1_2_sum(23) ,--o-- + car => pp1_2_car(22) );--o-- + pp1_2_csa_22: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_5(22) ,--i-- + b => pp0_6(22) ,--i-- + c => pp0_7(22) ,--i-- + sum => pp1_2_sum(22) ,--o-- + car => pp1_2_car(21) );--o-- + pp1_2_csa_21: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_5(21) ,--i-- + b => pp0_6(21) ,--i-- + c => pp0_7(21) ,--i-- + sum => pp1_2_sum(21) ,--o-- + car => pp1_2_car(20) );--o-- + pp1_2_csa_20: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_5(20) ,--i-- + b => pp0_6(20) ,--i-- + c => pp0_7(20) ,--i-- + sum => pp1_2_sum(20) ,--o-- + car => pp1_2_car(19) );--o-- + pp1_2_csa_19: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_5(19) ,--i-- + b => pp0_6(19) ,--i-- + c => pp0_7(19) ,--i-- + sum => pp1_2_sum(19) ,--o-- + car => pp1_2_car(18) );--o-- + pp1_2_csa_18: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_5(18) ,--i-- + b => pp0_6(18) ,--i-- + c => pp0_7(18) ,--i-- + sum => pp1_2_sum(18) ,--o-- + car => pp1_2_car(17) );--o-- + pp1_2_csa_17: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp0_5(17) ,--i-- + b => pp0_6(17) ,--i-- + c => pp0_7(17) ,--i-- + sum => pp1_2_sum(17) ,--o-- + car => pp1_2_car(16) );--o-- + pp1_2_csa_16: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp0_5(16) ,--i-- + b => pp0_6(16) ,--i-- + sum => pp1_2_sum(16) ,--o-- + car => pp1_2_car(15) );--o-- + pp1_2_sum(15) <= pp0_5(15) ; + pp1_2_sum(14) <= pp0_5(14) ; + + +--=#################################################################### +--=# compressor tree level 2 +--=#################################################################### + +--= 0 1 2 3 +--= 0123456789012345678901234567890123456 +--==------------------------------------- +-- sssssssssssssssssssssssss_s______ pp1_0_sum +-- ccccccccccccccccccccccc_c________ pp1_0_car +-- ________sssssssssssssssssssssss_s pp1_1_sum +-- 222222223333333333333332312111101 +-- sssssssssssssssssssssssssssssss_s pp2_0_sum +-- cccccccccccccccccccccccc__c pp2_0_car + + +--= 0 1 2 3 +--= 0123456789012345678901234567890123456 +--==------------------------------------- +-- _________ccccccccccccccccccc__c______ pp1_1_car +-- ______________sssssssssssssssssssssss pp1_2_sum +-- _______________ccccccccccccccccccc__c pp1_2_car +-- 1111123333333333333223222112 +-- ssssssssssssssssssssssssssss pp2_1_sum +-- ccccccccccccccccc_ccc__c pp2_1_car + +--====================================================== +--== compressor level 2 , row 0 +--====================================================== + + + + pp2_0_sum(32) <= pp1_1_sum(32) ; + pp2_0_sum(31) <= tidn ; + pp2_0_sum(30) <= pp1_1_sum(30) ; + pp2_0_sum(29) <= pp1_1_sum(29) ; + pp2_0_sum(28) <= pp1_1_sum(28) ; + pp2_0_sum(27) <= pp1_1_sum(27) ; + pp2_0_sum(26) <= pp1_0_sum(26) ; + pp2_0_car(26) <= pp1_1_sum(26) ; + pp2_0_sum(25) <= pp1_1_sum(25) ; + pp2_0_car(25) <= tidn ; + pp2_0_car(24) <= tidn ; + pp2_0_csa_24: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp1_0_sum(24) ,--i-- + b => pp1_0_car(24) ,--i-- + c => pp1_1_sum(24) ,--i-- + sum => pp2_0_sum(24) ,--o-- + car => pp2_0_car(23) );--o-- + pp2_0_csa_23: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp1_0_sum(23) ,--i-- + b => pp1_1_sum(23) ,--i-- + sum => pp2_0_sum(23) ,--o-- + car => pp2_0_car(22) );--o-- + pp2_0_csa_22: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp1_0_sum(22) ,--i-- + b => pp1_0_car(22) ,--i-- + c => pp1_1_sum(22) ,--i-- + sum => pp2_0_sum(22) ,--o-- + car => pp2_0_car(21) );--o-- + pp2_0_csa_21: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp1_0_sum(21) ,--i-- + b => pp1_0_car(21) ,--i-- + c => pp1_1_sum(21) ,--i-- + sum => pp2_0_sum(21) ,--o-- + car => pp2_0_car(20) );--o-- + pp2_0_csa_20: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp1_0_sum(20) ,--i-- + b => pp1_0_car(20) ,--i-- + c => pp1_1_sum(20) ,--i-- + sum => pp2_0_sum(20) ,--o-- + car => pp2_0_car(19) );--o-- + pp2_0_csa_19: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp1_0_sum(19) ,--i-- + b => pp1_0_car(19) ,--i-- + c => pp1_1_sum(19) ,--i-- + sum => pp2_0_sum(19) ,--o-- + car => pp2_0_car(18) );--o-- + pp2_0_csa_18: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp1_0_sum(18) ,--i-- + b => pp1_0_car(18) ,--i-- + c => pp1_1_sum(18) ,--i-- + sum => pp2_0_sum(18) ,--o-- + car => pp2_0_car(17) );--o-- + pp2_0_csa_17: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp1_0_sum(17) ,--i-- + b => pp1_0_car(17) ,--i-- + c => pp1_1_sum(17) ,--i-- + sum => pp2_0_sum(17) ,--o-- + car => pp2_0_car(16) );--o-- + pp2_0_csa_16: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp1_0_sum(16) ,--i-- + b => pp1_0_car(16) ,--i-- + c => pp1_1_sum(16) ,--i-- + sum => pp2_0_sum(16) ,--o-- + car => pp2_0_car(15) );--o-- + pp2_0_csa_15: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp1_0_sum(15) ,--i-- + b => pp1_0_car(15) ,--i-- + c => pp1_1_sum(15) ,--i-- + sum => pp2_0_sum(15) ,--o-- + car => pp2_0_car(14) );--o-- + pp2_0_csa_14: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp1_0_sum(14) ,--i-- + b => pp1_0_car(14) ,--i-- + c => pp1_1_sum(14) ,--i-- + sum => pp2_0_sum(14) ,--o-- + car => pp2_0_car(13) );--o-- + pp2_0_csa_13: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp1_0_sum(13) ,--i-- + b => pp1_0_car(13) ,--i-- + c => pp1_1_sum(13) ,--i-- + sum => pp2_0_sum(13) ,--o-- + car => pp2_0_car(12) );--o-- + pp2_0_csa_12: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp1_0_sum(12) ,--i-- + b => pp1_0_car(12) ,--i-- + c => pp1_1_sum(12) ,--i-- + sum => pp2_0_sum(12) ,--o-- + car => pp2_0_car(11) );--o-- + pp2_0_csa_11: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp1_0_sum(11) ,--i-- + b => pp1_0_car(11) ,--i-- + c => pp1_1_sum(11) ,--i-- + sum => pp2_0_sum(11) ,--o-- + car => pp2_0_car(10) );--o-- + pp2_0_csa_10: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp1_0_sum(10) ,--i-- + b => pp1_0_car(10) ,--i-- + c => pp1_1_sum(10) ,--i-- + sum => pp2_0_sum(10) ,--o-- + car => pp2_0_car(9) );--o-- + pp2_0_csa_9: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp1_0_sum(9) ,--i-- + b => pp1_0_car(9) ,--i-- + c => pp1_1_sum(9) ,--i-- + sum => pp2_0_sum(9) ,--o-- + car => pp2_0_car(8) );--o-- + pp2_0_csa_8: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp1_0_sum(8) ,--i-- + b => pp1_0_car(8) ,--i-- + c => pp1_1_sum(8) ,--i-- + sum => pp2_0_sum(8) ,--o-- + car => pp2_0_car(7) );--o-- + pp2_0_csa_7: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp1_0_sum(7) ,--i-- + b => pp1_0_car(7) ,--i-- + sum => pp2_0_sum(7) ,--o-- + car => pp2_0_car(6) );--o-- + pp2_0_csa_6: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp1_0_sum(6) ,--i-- + b => pp1_0_car(6) ,--i-- + sum => pp2_0_sum(6) ,--o-- + car => pp2_0_car(5) );--o-- + pp2_0_csa_5: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp1_0_sum(5) ,--i-- + b => pp1_0_car(5) ,--i-- + sum => pp2_0_sum(5) ,--o-- + car => pp2_0_car(4) );--o-- + pp2_0_csa_4: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp1_0_sum(4) ,--i-- + b => pp1_0_car(4) ,--i-- + sum => pp2_0_sum(4) ,--o-- + car => pp2_0_car(3) );--o-- + pp2_0_csa_3: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp1_0_sum(3) ,--i-- + b => pp1_0_car(3) ,--i-- + sum => pp2_0_sum(3) ,--o-- + car => pp2_0_car(2) );--o-- + pp2_0_csa_2: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp1_0_sum(2) ,--i-- + b => pp1_0_car(2) ,--i-- + sum => pp2_0_sum(2) ,--o-- + car => pp2_0_car(1) );--o-- + pp2_0_csa_1: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp1_0_sum(1) ,--i-- + b => pp1_0_car(1) ,--i-- + sum => pp2_0_sum(1) ,--o-- + car => pp2_0_car(0) );--o-- + pp2_0_csa_0: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp1_0_sum(0) ,--i-- + b => pp1_0_car(0) ,--i-- + sum => pp2_0_sum(0) ,--o-- + car => pp2_0_car_unused );--o-- + +--====================================================== +--== compressor level 2 , row 1 +--====================================================== + +--====================================================== +--== compressor level 2 , row 1 +--====================================================== + + pp2_1_sum(36) <= pp1_2_sum(36) ; + pp2_1_car(36) <= pp1_2_car(36) ; + pp2_1_sum(35) <= pp1_2_sum(35) ; + pp2_1_car(35) <= tidn ; + pp2_1_sum(34) <= pp1_2_sum(34) ; + pp2_1_car(34) <= tidn ; + pp2_1_sum(33) <= pp1_2_sum(33) ; + pp2_1_car(33) <= pp1_2_car(33) ; + pp2_1_sum(32) <= pp1_2_sum(32) ; + pp2_1_car(32) <= pp1_2_car(32) ; + pp2_1_sum(31) <= pp1_2_sum(31) ; + pp2_1_car(31) <= pp1_2_car(31) ; + pp2_1_car(30) <= tidn ; + pp2_1_csa_30: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp1_1_car(30) ,--i-- + b => pp1_2_sum(30) ,--i-- + c => pp1_2_car(30) ,--i-- + sum => pp2_1_sum(30) ,--o-- + car => pp2_1_car(29) );--o-- + pp2_1_csa_29: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp1_2_sum(29) ,--i-- + b => pp1_2_car(29) ,--i-- + sum => pp2_1_sum(29) ,--o-- + car => pp2_1_car(28) );--o-- + pp2_1_csa_28: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp1_2_sum(28) ,--i-- + b => pp1_2_car(28) ,--i-- + sum => pp2_1_sum(28) ,--o-- + car => pp2_1_car(27) );--o-- + pp2_1_csa_27: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp1_1_car(27) ,--i-- + b => pp1_2_sum(27) ,--i-- + c => pp1_2_car(27) ,--i-- + sum => pp2_1_sum(27) ,--o-- + car => pp2_1_car(26) );--o-- + pp2_1_csa_26: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp1_1_car(26) ,--i-- + b => pp1_2_sum(26) ,--i-- + c => pp1_2_car(26) ,--i-- + sum => pp2_1_sum(26) ,--o-- + car => pp2_1_car(25) );--o-- + pp2_1_csa_25: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp1_1_car(25) ,--i-- + b => pp1_2_sum(25) ,--i-- + c => pp1_2_car(25) ,--i-- + sum => pp2_1_sum(25) ,--o-- + car => pp2_1_car(24) );--o-- + pp2_1_csa_24: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp1_1_car(24) ,--i-- + b => pp1_2_sum(24) ,--i-- + c => pp1_2_car(24) ,--i-- + sum => pp2_1_sum(24) ,--o-- + car => pp2_1_car(23) );--o-- + pp2_1_csa_23: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp1_1_car(23) ,--i-- + b => pp1_2_sum(23) ,--i-- + c => pp1_2_car(23) ,--i-- + sum => pp2_1_sum(23) ,--o-- + car => pp2_1_car(22) );--o-- + pp2_1_csa_22: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp1_1_car(22) ,--i-- + b => pp1_2_sum(22) ,--i-- + c => pp1_2_car(22) ,--i-- + sum => pp2_1_sum(22) ,--o-- + car => pp2_1_car(21) );--o-- + pp2_1_csa_21: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp1_1_car(21) ,--i-- + b => pp1_2_sum(21) ,--i-- + c => pp1_2_car(21) ,--i-- + sum => pp2_1_sum(21) ,--o-- + car => pp2_1_car(20) );--o-- + pp2_1_csa_20: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp1_1_car(20) ,--i-- + b => pp1_2_sum(20) ,--i-- + c => pp1_2_car(20) ,--i-- + sum => pp2_1_sum(20) ,--o-- + car => pp2_1_car(19) );--o-- + pp2_1_csa_19: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp1_1_car(19) ,--i-- + b => pp1_2_sum(19) ,--i-- + c => pp1_2_car(19) ,--i-- + sum => pp2_1_sum(19) ,--o-- + car => pp2_1_car(18) );--o-- + pp2_1_csa_18: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp1_1_car(18) ,--i-- + b => pp1_2_sum(18) ,--i-- + c => pp1_2_car(18) ,--i-- + sum => pp2_1_sum(18) ,--o-- + car => pp2_1_car(17) );--o-- + pp2_1_csa_17: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp1_1_car(17) ,--i-- + b => pp1_2_sum(17) ,--i-- + c => pp1_2_car(17) ,--i-- + sum => pp2_1_sum(17) ,--o-- + car => pp2_1_car(16) );--o-- + pp2_1_csa_16: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp1_1_car(16) ,--i-- + b => pp1_2_sum(16) ,--i-- + c => pp1_2_car(16) ,--i-- + sum => pp2_1_sum(16) ,--o-- + car => pp2_1_car(15) );--o-- + pp2_1_csa_15: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp1_1_car(15) ,--i-- + b => pp1_2_sum(15) ,--i-- + c => pp1_2_car(15) ,--i-- + sum => pp2_1_sum(15) ,--o-- + car => pp2_1_car(14) );--o-- + pp2_1_csa_14: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp1_1_car(14) ,--i-- + b => pp1_2_sum(14) ,--i-- + sum => pp2_1_sum(14) ,--o-- + car => pp2_1_car(13) );--o-- + pp2_1_sum(13) <= pp1_1_car(13) ; + pp2_1_sum(12) <= pp1_1_car(12) ; + pp2_1_sum(11) <= pp1_1_car(11) ; + pp2_1_sum(10) <= pp1_1_car(10) ; + pp2_1_sum(9) <= pp1_1_car(9) ; + + + + + +--=#################################################################### +--=# compressor tree level 3 +--=#################################################################### + +--= 0 1 2 3 +--= 0123456789012345678901234567890123456 +--==------------------------------------- +-- sssssssssssssssssssssssssssssss_s pp2_0_sum +-- cccccccccccccccccccccccc__c pp2_0_car +-- ssssssssssssssssssssssssssss pp2_1_sum +-- ccccccccccccccccc_ccc__c pp2_1_car +-- 2222222223333444444444443343332232112 + +--====================================================== +--== compressor level 3 , row 0 +--====================================================== + + pp3_0_csa_36: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp2_1_sum(36) ,--i-- + b => pp2_1_car(36) ,--i-- + sum => pp3_0_sum(36) ,--o-- + car => pp3_0_car(35) );--o-- + pp3_0_sum(35) <= pp2_1_sum(35) ; + pp3_0_sum(34) <= pp2_1_sum(34) ; + pp3_0_car(34) <= tidn ; + pp3_0_sum(33) <= pp2_1_sum(33) ; + pp3_0_car(33) <= pp2_1_car(33) ; + pp3_0_car(32) <= tidn ; + pp3_0_csa_32: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp2_0_sum(32) ,--i-- + b => pp2_1_sum(32) ,--i-- + c => pp2_1_car(32) ,--i-- + sum => pp3_0_sum(32) ,--o-- + car => pp3_0_car(31) );--o-- + pp3_0_csa_31: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp2_1_sum(31) ,--i-- + b => pp2_1_car(31) ,--i-- + sum => pp3_0_sum(31) ,--o-- + car => pp3_0_car(30) );--o-- + pp3_0_csa_30: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp2_0_sum(30) ,--i-- + b => pp2_1_sum(30) ,--i-- + sum => pp3_0_sum(30) ,--o-- + car => pp3_0_car(29) );--o-- + pp3_0_csa_29: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp2_0_sum(29) ,--i-- + b => pp2_1_sum(29) ,--i-- + c => pp2_1_car(29) ,--i-- + sum => pp3_0_sum(29) ,--o-- + car => pp3_0_car(28) );--o-- + pp3_0_csa_28: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp2_0_sum(28) ,--i-- + b => pp2_1_sum(28) ,--i-- + c => pp2_1_car(28) ,--i-- + sum => pp3_0_sum(28) ,--o-- + car => pp3_0_car(27) );--o-- + pp3_0_csa_27: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp2_0_sum(27) ,--i-- + b => pp2_1_sum(27) ,--i-- + c => pp2_1_car(27) ,--i-- + sum => pp3_0_sum(27) ,--o-- + car => pp3_0_car(26) );--o-- + pp3_0_csa_26: entity clib.c_prism_csa42 port map( -- MLT42_X1_A12TH + vd => vdd, + gd => gnd, + a => pp2_0_sum(26) ,--i-- + b => pp2_0_car(26) ,--i-- + c => pp2_1_sum(26) ,--i-- + d => pp2_1_car(26) ,--i-- + ki => tidn ,--i-- + ko => pp3_0_ko(25) ,--i-- + sum => pp3_0_sum(26) ,--o-- + car => pp3_0_car(25) );--o-- + pp3_0_csa_25: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp2_0_sum(25) ,--i-- + b => tidn ,--i-- + c => pp2_1_sum(25) ,--i-- + d => pp2_1_car(25) ,--i-- + ki => pp3_0_ko(25) ,--i-- + ko => pp3_0_ko(24) ,--i-- + sum => pp3_0_sum(25) ,--o-- + car => pp3_0_car(24) );--o-- + pp3_0_csa_24: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp2_0_sum(24) ,--i-- + b => tidn ,--i-- + c => pp2_1_sum(24) ,--i-- + d => pp2_1_car(24) ,--i-- + ki => pp3_0_ko(24) ,--i-- + ko => pp3_0_ko(23) ,--i-- + sum => pp3_0_sum(24) ,--o-- + car => pp3_0_car(23) );--o-- + pp3_0_csa_23: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp2_0_sum(23) ,--i-- + b => pp2_0_car(23) ,--i-- + c => pp2_1_sum(23) ,--i-- + d => pp2_1_car(23) ,--i-- + ki => pp3_0_ko(23) ,--i-- + ko => pp3_0_ko(22) ,--i-- + sum => pp3_0_sum(23) ,--o-- + car => pp3_0_car(22) );--o-- + pp3_0_csa_22: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp2_0_sum(22) ,--i-- + b => pp2_0_car(22) ,--i-- + c => pp2_1_sum(22) ,--i-- + d => pp2_1_car(22) ,--i-- + ki => pp3_0_ko(22) ,--i-- + ko => pp3_0_ko(21) ,--i-- + sum => pp3_0_sum(22) ,--o-- + car => pp3_0_car(21) );--o-- + pp3_0_csa_21: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp2_0_sum(21) ,--i-- + b => pp2_0_car(21) ,--i-- + c => pp2_1_sum(21) ,--i-- + d => pp2_1_car(21) ,--i-- + ki => pp3_0_ko(21) ,--i-- + ko => pp3_0_ko(20) ,--i-- + sum => pp3_0_sum(21) ,--o-- + car => pp3_0_car(20) );--o-- + pp3_0_csa_20: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp2_0_sum(20) ,--i-- + b => pp2_0_car(20) ,--i-- + c => pp2_1_sum(20) ,--i-- + d => pp2_1_car(20) ,--i-- + ki => pp3_0_ko(20) ,--i-- + ko => pp3_0_ko(19) ,--i-- + sum => pp3_0_sum(20) ,--o-- + car => pp3_0_car(19) );--o-- + pp3_0_csa_19: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp2_0_sum(19) ,--i-- + b => pp2_0_car(19) ,--i-- + c => pp2_1_sum(19) ,--i-- + d => pp2_1_car(19) ,--i-- + ki => pp3_0_ko(19) ,--i-- + ko => pp3_0_ko(18) ,--i-- + sum => pp3_0_sum(19) ,--o-- + car => pp3_0_car(18) );--o-- + pp3_0_csa_18: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp2_0_sum(18) ,--i-- + b => pp2_0_car(18) ,--i-- + c => pp2_1_sum(18) ,--i-- + d => pp2_1_car(18) ,--i-- + ki => pp3_0_ko(18) ,--i-- + ko => pp3_0_ko(17) ,--i-- + sum => pp3_0_sum(18) ,--o-- + car => pp3_0_car(17) );--o-- + pp3_0_csa_17: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp2_0_sum(17) ,--i-- + b => pp2_0_car(17) ,--i-- + c => pp2_1_sum(17) ,--i-- + d => pp2_1_car(17) ,--i-- + ki => pp3_0_ko(17) ,--i-- + ko => pp3_0_ko(16) ,--i-- + sum => pp3_0_sum(17) ,--o-- + car => pp3_0_car(16) );--o-- + pp3_0_csa_16: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp2_0_sum(16) ,--i-- + b => pp2_0_car(16) ,--i-- + c => pp2_1_sum(16) ,--i-- + d => pp2_1_car(16) ,--i-- + ki => pp3_0_ko(16) ,--i-- + ko => pp3_0_ko(15) ,--i-- + sum => pp3_0_sum(16) ,--o-- + car => pp3_0_car(15) );--o-- + pp3_0_csa_15: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp2_0_sum(15) ,--i-- + b => pp2_0_car(15) ,--i-- + c => pp2_1_sum(15) ,--i-- + d => pp2_1_car(15) ,--i-- + ki => pp3_0_ko(15) ,--i-- + ko => pp3_0_ko(14) ,--i-- + sum => pp3_0_sum(15) ,--o-- + car => pp3_0_car(14) );--o-- + pp3_0_csa_14: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp2_0_sum(14) ,--i-- + b => pp2_0_car(14) ,--i-- + c => pp2_1_sum(14) ,--i-- + d => pp2_1_car(14) ,--i-- + ki => pp3_0_ko(14) ,--i-- + ko => pp3_0_ko(13) ,--i-- + sum => pp3_0_sum(14) ,--o-- + car => pp3_0_car(13) );--o-- + pp3_0_csa_13: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp2_0_sum(13) ,--i-- + b => pp2_0_car(13) ,--i-- + c => pp2_1_sum(13) ,--i-- + d => pp2_1_car(13) ,--i-- + ki => pp3_0_ko(13) ,--i-- + ko => pp3_0_ko(12) ,--i-- + sum => pp3_0_sum(13) ,--o-- + car => pp3_0_car(12) );--o-- + pp3_0_csa_12: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp2_0_sum(12) ,--i-- + b => pp2_0_car(12) ,--i-- + c => pp2_1_sum(12) ,--i-- + d => tidn ,--i-- + ki => pp3_0_ko(12) ,--i-- + ko => pp3_0_ko(11) ,--i-- + sum => pp3_0_sum(12) ,--o-- + car => pp3_0_car(11) );--o-- + pp3_0_csa_11: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp2_0_sum(11) ,--i-- + b => pp2_0_car(11) ,--i-- + c => pp2_1_sum(11) ,--i-- + d => tidn ,--i-- + ki => pp3_0_ko(11) ,--i-- + ko => pp3_0_ko(10) ,--i-- + sum => pp3_0_sum(11) ,--o-- + car => pp3_0_car(10) );--o-- + pp3_0_csa_10: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp2_0_sum(10) ,--i-- + b => pp2_0_car(10) ,--i-- + c => pp2_1_sum(10) ,--i-- + d => tidn ,--i-- + ki => pp3_0_ko(10) ,--i-- + ko => pp3_0_ko(9) ,--i-- + sum => pp3_0_sum(10) ,--o-- + car => pp3_0_car(9) );--o-- + pp3_0_csa_9: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => pp2_0_sum(9) ,--i-- + b => pp2_0_car(9) ,--i-- + c => pp2_1_sum(9) ,--i-- + d => tidn ,--i-- + ki => pp3_0_ko(9) ,--i-- + ko => pp3_0_ko(8) ,--i-- + sum => pp3_0_sum(9) ,--o-- + car => pp3_0_car(8) );--o-- + pp3_0_csa_8: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => pp2_0_sum(8) ,--i-- + b => pp2_0_car(8) ,--i-- + c => pp3_0_ko(8) ,--i-- + sum => pp3_0_sum(8) ,--o-- + car => pp3_0_car(7) );--o-- + pp3_0_csa_7: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp2_0_sum(7) ,--i-- + b => pp2_0_car(7) ,--i-- + sum => pp3_0_sum(7) ,--o-- + car => pp3_0_car(6) );--o-- + pp3_0_csa_6: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp2_0_sum(6) ,--i-- + b => pp2_0_car(6) ,--i-- + sum => pp3_0_sum(6) ,--o-- + car => pp3_0_car(5) );--o-- + pp3_0_csa_5: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp2_0_sum(5) ,--i-- + b => pp2_0_car(5) ,--i-- + sum => pp3_0_sum(5) ,--o-- + car => pp3_0_car(4) );--o-- + pp3_0_csa_4: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp2_0_sum(4) ,--i-- + b => pp2_0_car(4) ,--i-- + sum => pp3_0_sum(4) ,--o-- + car => pp3_0_car(3) );--o-- + pp3_0_csa_3: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp2_0_sum(3) ,--i-- + b => pp2_0_car(3) ,--i-- + sum => pp3_0_sum(3) ,--o-- + car => pp3_0_car(2) );--o-- + pp3_0_csa_2: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp2_0_sum(2) ,--i-- + b => pp2_0_car(2) ,--i-- + sum => pp3_0_sum(2) ,--o-- + car => pp3_0_car(1) );--o-- + pp3_0_csa_1: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp2_0_sum(1) ,--i-- + b => pp2_0_car(1) ,--i-- + sum => pp3_0_sum(1) ,--o-- + car => pp3_0_car(0) );--o-- + pp3_0_csa_0: entity work.fuq_csa22_h2(fuq_csa22_h2) port map( + a => pp2_0_sum(0) ,--i-- + b => pp2_0_car(0) ,--i-- + sum => pp3_0_sum(0) ,--o-- + car => pp3_0_car_unused );--o-- + + +--===================================================================== + + + tbl_sum(0 to 36) <= pp3_0_sum(0 to 36); + tbl_car(0 to 35) <= pp3_0_car(0 to 35); + + + +end; -- fuq_tblmul ARCHITECTURE diff --git a/rel/src/vhdl/work/fuq_tblmul_bthdcd.vhdl b/rel/src/vhdl/work/fuq_tblmul_bthdcd.vhdl new file mode 100644 index 0000000..ab85971 --- /dev/null +++ b/rel/src/vhdl/work/fuq_tblmul_bthdcd.vhdl @@ -0,0 +1,122 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; +use ieee.std_logic_1164.all; +library ibm; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_ao_support.all; + + +ENTITY fuq_tblmul_bthdcd IS + PORT( + i0 :in std_ulogic; + i1 :in std_ulogic; + i2 :in std_ulogic; + s_neg :out std_ulogic; + s_x :out std_ulogic; + s_x2 :out std_ulogic + ); + + + + +END fuq_tblmul_bthdcd; + +ARCHITECTURE fuq_tblmul_bthdcd OF fuq_tblmul_bthdcd IS + + signal s_add :std_ulogic; + signal sx1_a0_b :std_ulogic; + signal sx1_a1_b :std_ulogic; + signal sx1_t :std_ulogic; + signal sx1_i :std_ulogic; + signal sx2_a0_b :std_ulogic; + signal sx2_a1_b :std_ulogic; + signal sx2_t :std_ulogic; + signal sx2_i :std_ulogic; + signal i0_b, i1_b, i2_b :std_ulogic; + + + + + + + + +BEGIN +--// -- 000 add sh1=0 sh2=0 sub_adj=0 +--// -- 001 add sh1=1 sh2=0 sub_adj=0 +--// -- 010 add sh1=1 sh2=0 sub_adj=0 +--// -- 011 add sh1=0 sh2=1 sub_adj=0 +--// -- 100 sub sh1=0 sh2=1 sub_adj=1 +--// -- 101 sub sh1=1 sh2=0 sub_adj=1 +--// -- 110 sub sh1=1 sh2=0 sub_adj=1 +--// -- 111 sub sh1=0 sh2=0 sub_adj=0 +--// +--// s_neg <= ( i0 ); +--// +--// s_x <= ( not i1 and i2 ) or +--// ( i1 and not i2 ); +--// s_x2 <= ( i0 and not i1 and not i2 ) or +--// ( not i0 and i1 and i2 ); +--// +--// sub_adj <= i0 and not( i1 and i2 ); +--// + + +-- logically correct +------------------------------------ +-- s_neg <= (i0); +-- s_x <= ( not i1 and i2) or ( i1 and not i2); +-- s_x2 <= (i0 and not i1 and not i2) or (not i0 and i1 and i2); + + +u_0i: i0_b <= not( i0 ); +u_1i: i1_b <= not( i1 ); +u_2i: i2_b <= not( i2 ); + + +u_add: s_add <= not( i0 ); +u_sub: s_neg <= not( s_add ); + +u_sx1_a0: sx1_a0_b <= not( i1_b and i2 ) ; +u_sx1_a1: sx1_a1_b <= not( i1 and i2_b ) ; +u_sx1_t: sx1_t <= not( sx1_a0_b and sx1_a1_b ) ; +u_sx1_i: sx1_i <= not( sx1_t ); +u_sx1_ii: s_x <= not( sx1_i ); + +u_sx2_a0: sx2_a0_b <= not( i0 and i1_b and i2_b ) ; +u_sx2_a1: sx2_a1_b <= not( i0_b and i1 and i2 ) ; +u_sx2_t: sx2_t <= not( sx2_a0_b and sx2_a1_b ) ; +u_sx2_i: sx2_i <= not( sx2_t ); +u_sx2_ii: s_x2 <= not( sx2_i ); + + +END; diff --git a/rel/src/vhdl/work/fuq_tblmul_bthrow.vhdl b/rel/src/vhdl/work/fuq_tblmul_bthrow.vhdl new file mode 100644 index 0000000..fddd579 --- /dev/null +++ b/rel/src/vhdl/work/fuq_tblmul_bthrow.vhdl @@ -0,0 +1,223 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; + use ieee.std_logic_1164.all ; +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + +ENTITY fuq_tblmul_bthrow IS +PORT( + + x :in std_ulogic_vector(0 to 15); -- + s_neg :in std_ulogic; -- negate the row + s_x :in std_ulogic; -- shift by 1 + s_x2 :in std_ulogic; -- shift by 2 + q :out std_ulogic_vector(0 to 16) -- final output + +); + + +end fuq_tblmul_bthrow; -- ENTITY + +architecture fuq_tblmul_bthrow of fuq_tblmul_bthrow is + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal left :std_ulogic_vector( 0 to 16); + signal unused :std_ulogic; +begin + +--//################################################################ +--//# A row of the repeated part of the booth_mux row +--//################################################################ + + unused <= left(0); + + u00: entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg ,--i-- + SX => s_x ,--i-- + SX2 => s_x2 ,--i-- + X => tidn ,--i-- ******** + LEFT => left(0) ,--o-- [n] + RIGHT => left(1) ,--i-- [n+1] + Q => q(0) );--o-- + + u01: entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg ,--i-- + SX => s_x ,--i-- + SX2 => s_x2 ,--i-- + X => x(0) ,--i-- [n-1] + LEFT => left(1) ,--o-- [n] + RIGHT => left(2) ,--i-- [n+1] + Q => q(1) );--o-- + + u02: entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg ,--i-- + SX => s_x ,--i-- + SX2 => s_x2 ,--i-- + X => x(1) ,--i-- + LEFT => left(2) ,--o-- + RIGHT => left(3) ,--i-- + Q => q(2) );--o-- + + u03: entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg ,--i-- + SX => s_x ,--i-- + SX2 => s_x2 ,--i-- + X => x(2) ,--i-- + LEFT => left(3) ,--o-- + RIGHT => left(4) ,--i-- + Q => q(3) );--o-- + + u04: entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg ,--i-- + SX => s_x ,--i-- + SX2 => s_x2 ,--i-- + X => x(3) ,--i-- + LEFT => left(4) ,--o-- + RIGHT => left(5) ,--i-- + Q => q(4) );--o-- + + u05: entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg ,--i-- + SX => s_x ,--i-- + SX2 => s_x2 ,--i-- + X => x(4) ,--i-- + LEFT => left(5) ,--o-- + RIGHT => left(6) ,--i-- + Q => q(5) );--o-- + + u06: entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg ,--i-- + SX => s_x ,--i-- + SX2 => s_x2 ,--i-- + X => x(5) ,--i-- + LEFT => left(6) ,--o-- + RIGHT => left(7) ,--i-- + Q => q(6) );--o-- + + u07: entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg ,--i-- + SX => s_x ,--i-- + SX2 => s_x2 ,--i-- + X => x(6) ,--i-- + LEFT => left(7) ,--o-- + RIGHT => left(8) ,--i-- + Q => q(7) );--o-- + + u08: entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg ,--i-- + SX => s_x ,--i-- + SX2 => s_x2 ,--i-- + X => x(7) ,--i-- + LEFT => left(8) ,--o-- + RIGHT => left(9) ,--i-- + Q => q(8) );--o-- + + u09: entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg ,--i-- + SX => s_x ,--i-- + SX2 => s_x2 ,--i-- + X => x(8) ,--i-- + LEFT => left(9) ,--o-- + RIGHT => left(10) ,--i-- + Q => q(9) );--o-- + + u10: entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg ,--i-- + SX => s_x ,--i-- + SX2 => s_x2 ,--i-- + X => x(9) ,--i-- + LEFT => left(10) ,--o-- + RIGHT => left(11) ,--i-- + Q => q(10) );--o-- + + u11: entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg ,--i-- + SX => s_x ,--i-- + SX2 => s_x2 ,--i-- + X => x(10) ,--i-- + LEFT => left(11) ,--o-- + RIGHT => left(12) ,--i-- + Q => q(11) );--o-- + + u12: entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg ,--i-- + SX => s_x ,--i-- + SX2 => s_x2 ,--i-- + X => x(11) ,--i-- + LEFT => left(12) ,--o-- + RIGHT => left(13) ,--i-- + Q => q(12) );--o-- + + u13: entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg ,--i-- + SX => s_x ,--i-- + SX2 => s_x2 ,--i-- + X => x(12) ,--i-- + LEFT => left(13) ,--o-- + RIGHT => left(14) ,--i-- + Q => q(13) );--o-- + + u14: entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg ,--i-- + SX => s_x ,--i-- + SX2 => s_x2 ,--i-- + X => x(13) ,--i-- + LEFT => left(14) ,--o-- + RIGHT => left(15) ,--i-- + Q => q(14) );--o-- + + u15: entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg ,--i-- + SX => s_x ,--i-- + SX2 => s_x2 ,--i-- + X => x(14) ,--i-- + LEFT => left(15) ,--o-- + RIGHT => left(16) ,--i-- + Q => q(15) );--o-- + + u16: entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map( + SNEG => s_neg ,--i-- + SX => s_x ,--i-- + SX2 => s_x2 ,--i-- + X => x(15) ,--i-- + LEFT => left(16) ,--o-- + RIGHT => s_neg ,--i-- + Q => q(16) );--o-- + + + +end; -- fuq_tblmul_bthrow ARCHITECTURE diff --git a/rel/src/vhdl/work/fuq_tblres.vhdl b/rel/src/vhdl/work/fuq_tblres.vhdl new file mode 100644 index 0000000..d39f669 --- /dev/null +++ b/rel/src/vhdl/work/fuq_tblres.vhdl @@ -0,0 +1,1241 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; + use ieee.std_logic_1164.all ; +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + +-- 11111111111111000000 111111000000101 0 +-- 11111000000110111001 111101000110110 1 +-- 11110000011110000001 111011010010000 2 +-- 11101001000011110001 111001100010010 3 +-- 11100001110111011111 110111110111100 4 +-- 11011010111000100001 110110010001100 5 +-- 11010100000110010101 110100101111100 6 +-- 11001101100000010111 110011010001110 7 +-- 11000111000110000111 110001111000000 8 +-- 11000000110111000111 110000100001100 9 +-- 10111010110010111001 101111001110110 10 +-- 10110100111001000001 101101111111010 11 +-- 10101111001001000111 101100110010110 12 +-- 10101001100010101111 101011101001010 13 +-- 10100100000101100101 101010100010100 14 +-- 10011110110001001111 101001011110100 15 +-- 10011001100101011001 101000011101000 16 +-- 10010100100001110001 100111011101110 17 +-- 10001111100110000001 100110100001000 18 +-- 10001010110001111001 100101100110010 19 +-- 10000110000101000111 100100101101110 20 +-- 10000001011111011001 100011110111000 21 +-- 01111101000000011111 100011000010010 22 +-- 01111000101000001101 100010001111010 23 +-- 01110100010110010001 100001011110000 24 +-- 01110000001010100001 100000101110100 25 +-- 01101100000100101101 100000000000100 26 +-- 01101000000100101001 011111010011110 27 +-- 01100100001010001001 011110101000110 28 +-- 01100000010101000001 011101111111000 29 +-- 01011100100101001001 011101010110100 30 +-- 01011000111010010011 011100101111100 31 +-- 01010101010100010101 011100001001100 32 +-- 01010001110011000111 011011100100110 33 +-- 01001110010110100001 011011000001010 34 +-- 01001010111110010111 011010011110100 35 +-- 01000111101010100001 011001111101000 36 +-- 01000100011010111001 011001011100100 37 +-- 01000001001111010101 011000111100110 38 +-- 00111110000111101101 011000011110000 39 +-- 00111011000011111011 011000000000010 40 +-- 00111000000011111001 010111100011010 41 +-- 00110101000111011101 010111000111000 42 +-- 00110010001110100011 010110101011110 43 +-- 00101111011001000101 010110010001000 44 +-- 00101100100110111011 010101110111010 45 +-- 00101001111000000001 010101011110000 46 +-- 00100111001100010001 010101000101100 47 +-- 00100100100011100101 010100101101100 48 +-- 00100001111101110111 010100010110010 49 +-- 00011111011011000101 010011111111100 50 +-- 00011100111011000111 010011101001100 51 +-- 00011010011101111001 010011010100000 52 +-- 00011000000011011001 010010111111000 53 +-- 00010101101011011111 010010101010110 54 +-- 00010011010110001001 010010010110110 55 +-- 00010001000011010001 010010000011010 56 +-- 00001110110010110101 010001110000100 57 +-- 00001100100100110001 010001011110000 58 +-- 00001010011001000001 010001001100000 59 +-- 00001000001111100001 010000111010010 60 +-- 00000110001000001101 010000101001000 61 +-- 00000100000011000101 010000011000010 62 +-- 00000010000000000001 010000001000000 63 + + + +entity fuq_tblres is +generic( expand_type : integer := 2 ); -- 0 - ibm tech, 1 - other ); +port( + f :in std_ulogic_vector(1 to 6); + est :out std_ulogic_vector(1 to 20); + rng :out std_ulogic_vector(6 to 20) + +); -- end ports + + + +end fuq_tblres; -- ENTITY + + +architecture fuq_tblres of fuq_tblres is + + constant tiup :std_ulogic := '1'; + constant tidn :std_ulogic := '0'; + + + signal dcd_00x :std_ulogic; + signal dcd_01x :std_ulogic; + signal dcd_10x :std_ulogic; + signal dcd_11x :std_ulogic; + signal dcd_000 :std_ulogic; + signal dcd_001 :std_ulogic; + signal dcd_010 :std_ulogic; + signal dcd_011 :std_ulogic; + signal dcd_100 :std_ulogic; + signal dcd_101 :std_ulogic; + signal dcd_110 :std_ulogic; + signal dcd_111 :std_ulogic; + signal combo2_1000 :std_ulogic; + signal combo2_0100 :std_ulogic; + signal combo2_1100 :std_ulogic; + signal combo2_0010 :std_ulogic; + signal combo2_1010 :std_ulogic; + signal combo2_0110 :std_ulogic; + signal combo2_1110 :std_ulogic; + signal combo2_0001 :std_ulogic; + signal combo2_1001 :std_ulogic; + signal combo2_0101 :std_ulogic; + signal combo2_1101 :std_ulogic; + signal combo2_0011 :std_ulogic; + signal combo2_1011 :std_ulogic; + signal combo2_0111 :std_ulogic; + signal combo2_1000_xxxx_b :std_ulogic; + signal combo2_0100_xxxx_b :std_ulogic; + signal combo2_1100_xxxx_b :std_ulogic; + signal combo2_0010_xxxx_b :std_ulogic; + signal combo2_1010_xxxx_b :std_ulogic; + signal combo2_0110_xxxx_b :std_ulogic; + signal combo2_1110_xxxx_b :std_ulogic; + signal combo2_0001_xxxx_b :std_ulogic; + signal combo2_1001_xxxx_b :std_ulogic; + signal combo2_0101_xxxx_b :std_ulogic; + signal combo2_1101_xxxx_b :std_ulogic; + signal combo2_0011_xxxx_b :std_ulogic; + signal combo2_1011_xxxx_b :std_ulogic; + signal combo2_0111_xxxx_b :std_ulogic; + signal combo2_xxxx_1000_b :std_ulogic; + signal combo2_xxxx_0100_b :std_ulogic; + signal combo2_xxxx_1100_b :std_ulogic; + signal combo2_xxxx_0010_b :std_ulogic; + signal combo2_xxxx_1010_b :std_ulogic; + signal combo2_xxxx_0110_b :std_ulogic; + signal combo2_xxxx_1110_b :std_ulogic; + signal combo2_xxxx_0001_b :std_ulogic; + signal combo2_xxxx_1001_b :std_ulogic; + signal combo2_xxxx_0101_b :std_ulogic; + signal combo2_xxxx_1101_b :std_ulogic; + signal combo2_xxxx_0011_b :std_ulogic; + signal combo2_xxxx_1011_b :std_ulogic; + signal combo2_xxxx_0111_b :std_ulogic; + signal combo3_0000_0001 :std_ulogic; + signal combo3_0000_0010 :std_ulogic; + signal combo3_0000_0011 :std_ulogic; + signal combo3_0000_0100 :std_ulogic; + signal combo3_0000_0101 :std_ulogic; + signal combo3_0000_0110 :std_ulogic; + signal combo3_0000_1001 :std_ulogic; + signal combo3_0000_1010 :std_ulogic; + signal combo3_0000_1011 :std_ulogic; + signal combo3_0000_1110 :std_ulogic; + signal combo3_0000_1111 :std_ulogic; + signal combo3_0001_0001 :std_ulogic; + signal combo3_0001_0010 :std_ulogic; + signal combo3_0001_0100 :std_ulogic; + signal combo3_0001_0101 :std_ulogic; + signal combo3_0001_0111 :std_ulogic; + signal combo3_0001_1000 :std_ulogic; + signal combo3_0001_1010 :std_ulogic; + signal combo3_0001_1011 :std_ulogic; + signal combo3_0001_1100 :std_ulogic; + signal combo3_0001_1110 :std_ulogic; + signal combo3_0001_1111 :std_ulogic; + signal combo3_0010_0000 :std_ulogic; + signal combo3_0010_0100 :std_ulogic; + signal combo3_0010_0101 :std_ulogic; + signal combo3_0010_0110 :std_ulogic; + signal combo3_0010_0111 :std_ulogic; + signal combo3_0010_1000 :std_ulogic; + signal combo3_0010_1001 :std_ulogic; + signal combo3_0010_1101 :std_ulogic; + signal combo3_0011_0000 :std_ulogic; + signal combo3_0011_0001 :std_ulogic; + signal combo3_0011_0011 :std_ulogic; + signal combo3_0011_0101 :std_ulogic; + signal combo3_0011_1000 :std_ulogic; + signal combo3_0011_1001 :std_ulogic; + signal combo3_0011_1010 :std_ulogic; + signal combo3_0011_1011 :std_ulogic; + signal combo3_0011_1100 :std_ulogic; + signal combo3_0011_1110 :std_ulogic; + signal combo3_0011_1111 :std_ulogic; + signal combo3_0100_0000 :std_ulogic; + signal combo3_0100_0011 :std_ulogic; + signal combo3_0100_0110 :std_ulogic; + signal combo3_0100_1000 :std_ulogic; + signal combo3_0100_1001 :std_ulogic; + signal combo3_0100_1010 :std_ulogic; + signal combo3_0100_1100 :std_ulogic; + signal combo3_0100_1101 :std_ulogic; + signal combo3_0100_1110 :std_ulogic; + signal combo3_0101_0000 :std_ulogic; + signal combo3_0101_0001 :std_ulogic; + signal combo3_0101_0010 :std_ulogic; + signal combo3_0101_0100 :std_ulogic; + signal combo3_0101_0101 :std_ulogic; + signal combo3_0101_0110 :std_ulogic; + signal combo3_0101_1000 :std_ulogic; + signal combo3_0101_1011 :std_ulogic; + signal combo3_0101_1111 :std_ulogic; + signal combo3_0110_0000 :std_ulogic; + signal combo3_0110_0010 :std_ulogic; + signal combo3_0110_0011 :std_ulogic; + signal combo3_0110_0110 :std_ulogic; + signal combo3_0110_0111 :std_ulogic; + signal combo3_0110_1000 :std_ulogic; + signal combo3_0110_1010 :std_ulogic; + signal combo3_0110_1011 :std_ulogic; + signal combo3_0110_1100 :std_ulogic; + signal combo3_0110_1101 :std_ulogic; + signal combo3_0111_0000 :std_ulogic; + signal combo3_0111_0001 :std_ulogic; + signal combo3_0111_0101 :std_ulogic; + signal combo3_0111_0110 :std_ulogic; + signal combo3_0111_1000 :std_ulogic; + signal combo3_0111_1001 :std_ulogic; + signal combo3_0111_1010 :std_ulogic; + signal combo3_0111_1011 :std_ulogic; + signal combo3_0111_1101 :std_ulogic; + signal combo3_0111_1111 :std_ulogic; + signal combo3_1000_0000 :std_ulogic; + signal combo3_1000_0001 :std_ulogic; + signal combo3_1000_0011 :std_ulogic; + signal combo3_1000_0100 :std_ulogic; + signal combo3_1000_0101 :std_ulogic; + signal combo3_1000_1010 :std_ulogic; + signal combo3_1000_1100 :std_ulogic; + signal combo3_1000_1101 :std_ulogic; + signal combo3_1001_0100 :std_ulogic; + signal combo3_1001_0110 :std_ulogic; + signal combo3_1001_0111 :std_ulogic; + signal combo3_1001_1000 :std_ulogic; + signal combo3_1001_1001 :std_ulogic; + signal combo3_1001_1010 :std_ulogic; + signal combo3_1001_1011 :std_ulogic; + signal combo3_1001_1111 :std_ulogic; + signal combo3_1010_0100 :std_ulogic; + signal combo3_1010_0110 :std_ulogic; + signal combo3_1010_1000 :std_ulogic; + signal combo3_1010_1001 :std_ulogic; + signal combo3_1010_1010 :std_ulogic; + signal combo3_1010_1011 :std_ulogic; + signal combo3_1010_1100 :std_ulogic; + signal combo3_1010_1101 :std_ulogic; + signal combo3_1011_0010 :std_ulogic; + signal combo3_1011_0011 :std_ulogic; + signal combo3_1011_0100 :std_ulogic; + signal combo3_1011_0101 :std_ulogic; + signal combo3_1011_0110 :std_ulogic; + signal combo3_1011_0111 :std_ulogic; + signal combo3_1100_0000 :std_ulogic; + signal combo3_1100_0001 :std_ulogic; + signal combo3_1100_0010 :std_ulogic; + signal combo3_1100_0011 :std_ulogic; + signal combo3_1100_0100 :std_ulogic; + signal combo3_1100_0111 :std_ulogic; + signal combo3_1100_1000 :std_ulogic; + signal combo3_1100_1001 :std_ulogic; + signal combo3_1100_1010 :std_ulogic; + signal combo3_1100_1101 :std_ulogic; + signal combo3_1100_1110 :std_ulogic; + signal combo3_1100_1111 :std_ulogic; + signal combo3_1101_0010 :std_ulogic; + signal combo3_1101_0011 :std_ulogic; + signal combo3_1101_0100 :std_ulogic; + signal combo3_1101_0101 :std_ulogic; + signal combo3_1101_0110 :std_ulogic; + signal combo3_1101_0111 :std_ulogic; + signal combo3_1101_1100 :std_ulogic; + signal combo3_1101_1101 :std_ulogic; + signal combo3_1101_1110 :std_ulogic; + signal combo3_1110_0000 :std_ulogic; + signal combo3_1110_0100 :std_ulogic; + signal combo3_1110_0101 :std_ulogic; + signal combo3_1110_0110 :std_ulogic; + signal combo3_1110_1000 :std_ulogic; + signal combo3_1110_1010 :std_ulogic; + signal combo3_1110_1101 :std_ulogic; + signal combo3_1111_0000 :std_ulogic; + signal combo3_1111_0001 :std_ulogic; + signal combo3_1111_0010 :std_ulogic; + signal combo3_1111_0100 :std_ulogic; + signal combo3_1111_1000 :std_ulogic; + signal combo3_1111_1001 :std_ulogic; + signal combo3_1111_1010 :std_ulogic; + signal combo3_1111_1100 :std_ulogic; + signal combo3_1111_1110 :std_ulogic; + signal e_00_b :std_ulogic_vector(0 to 7); + signal e_01_b :std_ulogic_vector(0 to 7); + signal e_02_b :std_ulogic_vector(0 to 7); + signal e_03_b :std_ulogic_vector(0 to 7); + signal e_04_b :std_ulogic_vector(0 to 7); + signal e_05_b :std_ulogic_vector(0 to 7); + signal e_06_b :std_ulogic_vector(0 to 7); + signal e_07_b :std_ulogic_vector(0 to 7); + signal e_08_b :std_ulogic_vector(0 to 7); + signal e_09_b :std_ulogic_vector(0 to 7); + signal e_10_b :std_ulogic_vector(0 to 7); + signal e_11_b :std_ulogic_vector(0 to 7); + signal e_12_b :std_ulogic_vector(0 to 7); + signal e_13_b :std_ulogic_vector(0 to 7); + signal e_14_b :std_ulogic_vector(0 to 7); + signal e_15_b :std_ulogic_vector(0 to 7); + signal e_16_b :std_ulogic_vector(0 to 7); + signal e_17_b :std_ulogic_vector(0 to 7); + signal e_18_b :std_ulogic_vector(0 to 7); + signal e_19_b :std_ulogic_vector(0 to 7); + signal e :std_ulogic_vector(0 to 19); + signal r_00_b :std_ulogic_vector(0 to 7); + signal r_01_b :std_ulogic_vector(0 to 7); + signal r_02_b :std_ulogic_vector(0 to 7); + signal r_03_b :std_ulogic_vector(0 to 7); + signal r_04_b :std_ulogic_vector(0 to 7); + signal r_05_b :std_ulogic_vector(0 to 7); + signal r_06_b :std_ulogic_vector(0 to 7); + signal r_07_b :std_ulogic_vector(0 to 7); + signal r_08_b :std_ulogic_vector(0 to 7); + signal r_09_b :std_ulogic_vector(0 to 7); + signal r_10_b :std_ulogic_vector(0 to 7); + signal r_11_b :std_ulogic_vector(0 to 7); + signal r_12_b :std_ulogic_vector(0 to 7); + signal r_13_b :std_ulogic_vector(0 to 7); + signal r_14_b :std_ulogic_vector(0 to 7); + signal r :std_ulogic_vector(0 to 14); + + +begin + + +--//####################################### +--//## decode the upper 3 index bits +--//####################################### + + dcd_00x <= not f(1) and not f(2) ; + dcd_01x <= not f(1) and f(2) ; + dcd_10x <= f(1) and not f(2) ; + dcd_11x <= f(1) and f(2) ; + + dcd_000 <= not f(3) and dcd_00x ; + dcd_001 <= f(3) and dcd_00x ; + dcd_010 <= not f(3) and dcd_01x ; + dcd_011 <= f(3) and dcd_01x ; + dcd_100 <= not f(3) and dcd_10x ; + dcd_101 <= f(3) and dcd_10x ; + dcd_110 <= not f(3) and dcd_11x ; + dcd_111 <= f(3) and dcd_11x ; + + +--//####################################### +--//## combos based on lower 2 index bits +--//####################################### + + combo2_1000 <= not f(5) and not f(6) ;-- [0] + combo2_0100 <= not f(5) and f(6) ;-- [1] + combo2_1100 <= not f(5) ;-- [0,1] + combo2_0010 <= f(5) and not f(6) ;-- [2] + combo2_1010 <= not f(6) ;-- [0,2] + combo2_0110 <= f(5) xor f(6) ;-- [1,2] + combo2_1110 <= not( f(5) and f(6) ) ;-- [0,1,2] + combo2_0001 <= f(5) and f(6) ;-- [3] + combo2_1001 <= not( f(5) xor f(6) ) ;-- [0,3] + combo2_0101 <= f(6) ;-- [1,3] + combo2_1101 <= not( f(5) and not f(6) ) ;-- [1,2,3] + combo2_0011 <= f(5) ;-- [2,3] + combo2_1011 <= not( not f(5) and f(6) ) ;-- [0,2,3] + combo2_0111 <= not( not f(5) and not f(6) ) ;-- [1,2,3] + + +--//####################################### +--//## combos based on lower 3 index bits +--//####################################### + + combo2_1000_xxxx_b <= not( not f(4) and combo2_1000 ); + combo2_0100_xxxx_b <= not( not f(4) and combo2_0100 ); + combo2_1100_xxxx_b <= not( not f(4) and combo2_1100 ); + combo2_0010_xxxx_b <= not( not f(4) and combo2_0010 ); + combo2_1010_xxxx_b <= not( not f(4) and combo2_1010 ); + combo2_0110_xxxx_b <= not( not f(4) and combo2_0110 ); + combo2_1110_xxxx_b <= not( not f(4) and combo2_1110 ); + combo2_0001_xxxx_b <= not( not f(4) and combo2_0001 ); + combo2_1001_xxxx_b <= not( not f(4) and combo2_1001 ); + combo2_0101_xxxx_b <= not( not f(4) and combo2_0101 ); + combo2_1101_xxxx_b <= not( not f(4) and combo2_1101 ); + combo2_0011_xxxx_b <= not( not f(4) and combo2_0011 ); + combo2_1011_xxxx_b <= not( not f(4) and combo2_1011 ); + combo2_0111_xxxx_b <= not( not f(4) and combo2_0111 ); + + + combo2_xxxx_1000_b <= not( f(4) and combo2_1000 ); + combo2_xxxx_0100_b <= not( f(4) and combo2_0100 ); + combo2_xxxx_1100_b <= not( f(4) and combo2_1100 ); + combo2_xxxx_0010_b <= not( f(4) and combo2_0010 ); + combo2_xxxx_1010_b <= not( f(4) and combo2_1010 ); + combo2_xxxx_0110_b <= not( f(4) and combo2_0110 ); + combo2_xxxx_1110_b <= not( f(4) and combo2_1110 ); + combo2_xxxx_0001_b <= not( f(4) and combo2_0001 ); + combo2_xxxx_1001_b <= not( f(4) and combo2_1001 ); + combo2_xxxx_0101_b <= not( f(4) and combo2_0101 ); + combo2_xxxx_1101_b <= not( f(4) and combo2_1101 ); + combo2_xxxx_0011_b <= not( f(4) and combo2_0011 ); + combo2_xxxx_1011_b <= not( f(4) and combo2_1011 ); + combo2_xxxx_0111_b <= not( f(4) and combo2_0111 ); + + + combo3_0000_0001 <= not( combo2_xxxx_0001_b );--i=1, 2 1 + combo3_0000_0010 <= not( combo2_xxxx_0010_b );--i=2, 1 2 + combo3_0000_0011 <= not( combo2_xxxx_0011_b );--i=3, 3 3 + combo3_0000_0100 <= not( combo2_xxxx_0100_b );--i=4, 1 4 + combo3_0000_0101 <= not( combo2_xxxx_0101_b );--i=5, 2 5 + combo3_0000_0110 <= not( combo2_xxxx_0110_b );--i=6, 2 6 + combo3_0000_1001 <= not( combo2_xxxx_1001_b );--i=9, 1 7 + combo3_0000_1010 <= not( combo2_xxxx_1010_b );--i=10, 2 8 + combo3_0000_1011 <= not( combo2_xxxx_1011_b );--i=11, 2 9 + combo3_0000_1110 <= not( combo2_xxxx_1110_b );--i=14, 1 10 + combo3_0000_1111 <= not( not f(4) );--i=15, 2 11 + combo3_0001_0001 <= not( not combo2_0001 );--i=17, 2 12* + combo3_0001_0010 <= not( combo2_0001_xxxx_b and combo2_xxxx_0010_b );--i=18, 1 13 + combo3_0001_0100 <= not( combo2_0001_xxxx_b and combo2_xxxx_0100_b );--i=20, 1 14 + combo3_0001_0101 <= not( combo2_0001_xxxx_b and combo2_xxxx_0101_b );--i=21, 1 15 + combo3_0001_0111 <= not( combo2_0001_xxxx_b and combo2_xxxx_0111_b );--i=23, 1 16 + combo3_0001_1000 <= not( combo2_0001_xxxx_b and combo2_xxxx_1000_b );--i=24, 3 17 + combo3_0001_1010 <= not( combo2_0001_xxxx_b and combo2_xxxx_1010_b );--i=26, 1 18 + combo3_0001_1011 <= not( combo2_0001_xxxx_b and combo2_xxxx_1011_b );--i=27, 1 19 + combo3_0001_1100 <= not( combo2_0001_xxxx_b and combo2_xxxx_1100_b );--i=28, 1 20 + combo3_0001_1110 <= not( combo2_0001_xxxx_b and combo2_xxxx_1110_b );--i=30, 1 21 + combo3_0001_1111 <= not( combo2_0001_xxxx_b and not f(4) );--i=31, 4 22 + combo3_0010_0000 <= not( combo2_0010_xxxx_b );--i=32, 2 23 + combo3_0010_0100 <= not( combo2_0010_xxxx_b and combo2_xxxx_0100_b );--i=36, 1 24 + combo3_0010_0101 <= not( combo2_0010_xxxx_b and combo2_xxxx_0101_b );--i=37, 1 25 + combo3_0010_0110 <= not( combo2_0010_xxxx_b and combo2_xxxx_0110_b );--i=38, 2 26 + combo3_0010_0111 <= not( combo2_0010_xxxx_b and combo2_xxxx_0111_b );--i=39, 1 27 + combo3_0010_1000 <= not( combo2_0010_xxxx_b and combo2_xxxx_1000_b );--i=40, 2 28 + combo3_0010_1001 <= not( combo2_0010_xxxx_b and combo2_xxxx_1001_b );--i=41, 1 29 + combo3_0010_1101 <= not( combo2_0010_xxxx_b and combo2_xxxx_1101_b );--i=45, 4 30 + combo3_0011_0000 <= not( combo2_0011_xxxx_b );--i=48, 1 31 + combo3_0011_0001 <= not( combo2_0011_xxxx_b and combo2_xxxx_0001_b );--i=49, 3 32 + combo3_0011_0011 <= not( not combo2_0011 );--i=51, 1 33* + combo3_0011_0101 <= not( combo2_0011_xxxx_b and combo2_xxxx_0101_b );--i=53, 1 34 + combo3_0011_1000 <= not( combo2_0011_xxxx_b and combo2_xxxx_1000_b );--i=56, 3 35 + combo3_0011_1001 <= not( combo2_0011_xxxx_b and combo2_xxxx_1001_b );--i=57, 1 36 + combo3_0011_1010 <= not( combo2_0011_xxxx_b and combo2_xxxx_1010_b );--i=58, 1 37 + combo3_0011_1011 <= not( combo2_0011_xxxx_b and combo2_xxxx_1011_b );--i=59, 1 38 + combo3_0011_1100 <= not( combo2_0011_xxxx_b and combo2_xxxx_1100_b );--i=60, 3 39 + combo3_0011_1110 <= not( combo2_0011_xxxx_b and combo2_xxxx_1110_b );--i=62, 1 40 + combo3_0011_1111 <= not( combo2_0011_xxxx_b and not f(4) );--i=63, 4 41 + combo3_0100_0000 <= not( combo2_0100_xxxx_b );--i=64, 1 42 + combo3_0100_0011 <= not( combo2_0100_xxxx_b and combo2_xxxx_0011_b );--i=67, 2 43 + combo3_0100_0110 <= not( combo2_0100_xxxx_b and combo2_xxxx_0110_b );--i=70, 1 44 + combo3_0100_1000 <= not( combo2_0100_xxxx_b and combo2_xxxx_1000_b );--i=72, 2 45 + combo3_0100_1001 <= not( combo2_0100_xxxx_b and combo2_xxxx_1001_b );--i=73, 2 46 + combo3_0100_1010 <= not( combo2_0100_xxxx_b and combo2_xxxx_1010_b );--i=74, 2 47 + combo3_0100_1100 <= not( combo2_0100_xxxx_b and combo2_xxxx_1100_b );--i=76, 1 48 + combo3_0100_1101 <= not( combo2_0100_xxxx_b and combo2_xxxx_1101_b );--i=77, 1 49 + combo3_0100_1110 <= not( combo2_0100_xxxx_b and combo2_xxxx_1110_b );--i=78, 1 50 + combo3_0101_0000 <= not( combo2_0101_xxxx_b );--i=80, 3 51 + combo3_0101_0001 <= not( combo2_0101_xxxx_b and combo2_xxxx_0001_b );--i=81, 1 52 + combo3_0101_0010 <= not( combo2_0101_xxxx_b and combo2_xxxx_0010_b );--i=82, 1 53 + combo3_0101_0100 <= not( combo2_0101_xxxx_b and combo2_xxxx_0100_b );--i=84, 3 54 + combo3_0101_0101 <= not( not combo2_0101 );--i=85, 1 55* + combo3_0101_0110 <= not( combo2_0101_xxxx_b and combo2_xxxx_0110_b );--i=86, 1 56 + combo3_0101_1000 <= not( combo2_0101_xxxx_b and combo2_xxxx_1000_b );--i=88, 1 57 + combo3_0101_1011 <= not( combo2_0101_xxxx_b and combo2_xxxx_1011_b );--i=91, 3 58 + combo3_0101_1111 <= not( combo2_0101_xxxx_b and not f(4) );--i=95, 1 59 + combo3_0110_0000 <= not( combo2_0110_xxxx_b );--i=96, 1 60 + combo3_0110_0010 <= not( combo2_0110_xxxx_b and combo2_xxxx_0010_b );--i=98, 1 61 + combo3_0110_0011 <= not( combo2_0110_xxxx_b and combo2_xxxx_0011_b );--i=99, 1 62 + combo3_0110_0110 <= not( not combo2_0110 );--i=102, 1 63* + combo3_0110_0111 <= not( combo2_0110_xxxx_b and combo2_xxxx_0111_b );--i=103, 3 64 + combo3_0110_1000 <= not( combo2_0110_xxxx_b and combo2_xxxx_1000_b );--i=104, 1 65 + combo3_0110_1010 <= not( combo2_0110_xxxx_b and combo2_xxxx_1010_b );--i=106, 2 66 + combo3_0110_1011 <= not( combo2_0110_xxxx_b and combo2_xxxx_1011_b );--i=107, 1 67 + combo3_0110_1100 <= not( combo2_0110_xxxx_b and combo2_xxxx_1100_b );--i=108, 1 68 + combo3_0110_1101 <= not( combo2_0110_xxxx_b and combo2_xxxx_1101_b );--i=109, 1 69 + combo3_0111_0000 <= not( combo2_0111_xxxx_b );--i=112, 3 70 + combo3_0111_0001 <= not( combo2_0111_xxxx_b and combo2_xxxx_0001_b );--i=113, 1 71 + combo3_0111_0101 <= not( combo2_0111_xxxx_b and combo2_xxxx_0101_b );--i=117, 1 72 + combo3_0111_0110 <= not( combo2_0111_xxxx_b and combo2_xxxx_0110_b );--i=118, 1 73 + combo3_0111_1000 <= not( combo2_0111_xxxx_b and combo2_xxxx_1000_b );--i=120, 3 74 + combo3_0111_1001 <= not( combo2_0111_xxxx_b and combo2_xxxx_1001_b );--i=121, 1 75 + combo3_0111_1010 <= not( combo2_0111_xxxx_b and combo2_xxxx_1010_b );--i=122, 2 76 + combo3_0111_1011 <= not( combo2_0111_xxxx_b and combo2_xxxx_1011_b );--i=123, 1 77 + combo3_0111_1101 <= not( combo2_0111_xxxx_b and combo2_xxxx_1101_b );--i=125, 1 78 + combo3_0111_1111 <= not( combo2_0111_xxxx_b and not f(4) );--i=127, 3 79 + combo3_1000_0000 <= not( combo2_1000_xxxx_b );--i=128, 7 80 + combo3_1000_0001 <= not( combo2_1000_xxxx_b and combo2_xxxx_0001_b );--i=129, 1 81 + combo3_1000_0011 <= not( combo2_1000_xxxx_b and combo2_xxxx_0011_b );--i=131, 1 82 + combo3_1000_0100 <= not( combo2_1000_xxxx_b and combo2_xxxx_0100_b );--i=132, 2 83 + combo3_1000_0101 <= not( combo2_1000_xxxx_b and combo2_xxxx_0101_b );--i=133, 1 84 + combo3_1000_1010 <= not( combo2_1000_xxxx_b and combo2_xxxx_1010_b );--i=138, 1 85 + combo3_1000_1100 <= not( combo2_1000_xxxx_b and combo2_xxxx_1100_b );--i=140, 1 86 + combo3_1000_1101 <= not( combo2_1000_xxxx_b and combo2_xxxx_1101_b );--i=141, 1 87 + combo3_1001_0100 <= not( combo2_1001_xxxx_b and combo2_xxxx_0100_b );--i=148, 1 88 + combo3_1001_0110 <= not( combo2_1001_xxxx_b and combo2_xxxx_0110_b );--i=150, 3 89 + combo3_1001_0111 <= not( combo2_1001_xxxx_b and combo2_xxxx_0111_b );--i=151, 1 90 + combo3_1001_1000 <= not( combo2_1001_xxxx_b and combo2_xxxx_1000_b );--i=152, 1 91 + combo3_1001_1001 <= not( not combo2_1001 );--i=153, 3 92* + combo3_1001_1010 <= not( combo2_1001_xxxx_b and combo2_xxxx_1010_b );--i=154, 1 93 + combo3_1001_1011 <= not( combo2_1001_xxxx_b and combo2_xxxx_1011_b );--i=155, 1 94 + combo3_1001_1111 <= not( combo2_1001_xxxx_b and not f(4) );--i=159, 1 95 + combo3_1010_0100 <= not( combo2_1010_xxxx_b and combo2_xxxx_0100_b );--i=164, 1 96 + combo3_1010_0110 <= not( combo2_1010_xxxx_b and combo2_xxxx_0110_b );--i=166, 1 97 + combo3_1010_1000 <= not( combo2_1010_xxxx_b and combo2_xxxx_1000_b );--i=168, 2 98 + combo3_1010_1001 <= not( combo2_1010_xxxx_b and combo2_xxxx_1001_b );--i=169, 1 99 + combo3_1010_1010 <= not( not combo2_1010 );--i=170, 1 100* + combo3_1010_1011 <= not( combo2_1010_xxxx_b and combo2_xxxx_1011_b );--i=171, 1 101 + combo3_1010_1100 <= not( combo2_1010_xxxx_b and combo2_xxxx_1100_b );--i=172, 2 102 + combo3_1010_1101 <= not( combo2_1010_xxxx_b and combo2_xxxx_1101_b );--i=173, 2 103 + combo3_1011_0010 <= not( combo2_1011_xxxx_b and combo2_xxxx_0010_b );--i=178, 1 104 + combo3_1011_0011 <= not( combo2_1011_xxxx_b and combo2_xxxx_0011_b );--i=179, 3 105 + combo3_1011_0100 <= not( combo2_1011_xxxx_b and combo2_xxxx_0100_b );--i=180, 1 106 + combo3_1011_0101 <= not( combo2_1011_xxxx_b and combo2_xxxx_0101_b );--i=181, 2 107 + combo3_1011_0110 <= not( combo2_1011_xxxx_b and combo2_xxxx_0110_b );--i=182, 3 108 + combo3_1011_0111 <= not( combo2_1011_xxxx_b and combo2_xxxx_0111_b );--i=183, 1 109 + combo3_1100_0000 <= not( combo2_1100_xxxx_b );--i=192, 4 110 + combo3_1100_0001 <= not( combo2_1100_xxxx_b and combo2_xxxx_0001_b );--i=193, 1 111 + combo3_1100_0010 <= not( combo2_1100_xxxx_b and combo2_xxxx_0010_b );--i=194, 1 112 + combo3_1100_0011 <= not( combo2_1100_xxxx_b and combo2_xxxx_0011_b );--i=195, 2 113 + combo3_1100_0100 <= not( combo2_1100_xxxx_b and combo2_xxxx_0100_b );--i=196, 1 114 + combo3_1100_0111 <= not( combo2_1100_xxxx_b and combo2_xxxx_0111_b );--i=199, 1 115 + combo3_1100_1000 <= not( combo2_1100_xxxx_b and combo2_xxxx_1000_b );--i=200, 1 116 + combo3_1100_1001 <= not( combo2_1100_xxxx_b and combo2_xxxx_1001_b );--i=201, 2 117 + combo3_1100_1010 <= not( combo2_1100_xxxx_b and combo2_xxxx_1010_b );--i=202, 2 118 + combo3_1100_1101 <= not( combo2_1100_xxxx_b and combo2_xxxx_1101_b );--i=205, 2 119 + combo3_1100_1110 <= not( combo2_1100_xxxx_b and combo2_xxxx_1110_b );--i=206, 2 120 + combo3_1100_1111 <= not( combo2_1100_xxxx_b and not f(4) );--i=207, 2 121 + combo3_1101_0010 <= not( combo2_1101_xxxx_b and combo2_xxxx_0010_b );--i=210, 1 122 + combo3_1101_0011 <= not( combo2_1101_xxxx_b and combo2_xxxx_0011_b );--i=211, 1 123 + combo3_1101_0100 <= not( combo2_1101_xxxx_b and combo2_xxxx_0100_b );--i=212, 2 124 + combo3_1101_0101 <= not( combo2_1101_xxxx_b and combo2_xxxx_0101_b );--i=213, 1 125 + combo3_1101_0110 <= not( combo2_1101_xxxx_b and combo2_xxxx_0110_b );--i=214, 2 126 + combo3_1101_0111 <= not( combo2_1101_xxxx_b and combo2_xxxx_0111_b );--i=215, 1 127 + combo3_1101_1100 <= not( combo2_1101_xxxx_b and combo2_xxxx_1100_b );--i=220, 1 128 + combo3_1101_1101 <= not( not combo2_1101 );--i=221, 1 129* + combo3_1101_1110 <= not( combo2_1101_xxxx_b and combo2_xxxx_1110_b );--i=222, 1 130 + combo3_1110_0000 <= not( combo2_1110_xxxx_b );--i=224, 2 131 + combo3_1110_0100 <= not( combo2_1110_xxxx_b and combo2_xxxx_0100_b );--i=228, 2 132 + combo3_1110_0101 <= not( combo2_1110_xxxx_b and combo2_xxxx_0101_b );--i=229, 1 133 + combo3_1110_0110 <= not( combo2_1110_xxxx_b and combo2_xxxx_0110_b );--i=230, 1 134 + combo3_1110_1000 <= not( combo2_1110_xxxx_b and combo2_xxxx_1000_b );--i=232, 1 135 + combo3_1110_1010 <= not( combo2_1110_xxxx_b and combo2_xxxx_1010_b );--i=234, 1 136 + combo3_1110_1101 <= not( combo2_1110_xxxx_b and combo2_xxxx_1101_b );--i=237, 2 137 + combo3_1111_0000 <= not( f(4) );--i=240, 2 138 + combo3_1111_0001 <= not( f(4) and combo2_xxxx_0001_b );--i=241, 1 139 + combo3_1111_0010 <= not( f(4) and combo2_xxxx_0010_b );--i=242, 1 140 + combo3_1111_0100 <= not( f(4) and combo2_xxxx_0100_b );--i=244, 2 141 + combo3_1111_1000 <= not( f(4) and combo2_xxxx_1000_b );--i=248, 1 142 + combo3_1111_1001 <= not( f(4) and combo2_xxxx_1001_b );--i=249, 1 143 + combo3_1111_1010 <= not( f(4) and combo2_xxxx_1010_b );--i=250, 1 144 + combo3_1111_1100 <= not( f(4) and combo2_xxxx_1100_b );--i=252, 2 145 + combo3_1111_1110 <= not( f(4) and combo2_xxxx_1110_b );--i=254, 2 146 + + +--//####################################### +--//## ESTIMATE VECTORs +--//####################################### + + e_00_b(0) <= not( dcd_000 and tiup ); + e_00_b(1) <= not( dcd_001 and tiup ); + e_00_b(2) <= not( dcd_010 and combo3_1111_1100 ); + e_00_b(3) <= not( dcd_011 and tidn ); + e_00_b(4) <= not( dcd_100 and tidn ); + e_00_b(5) <= not( dcd_101 and tidn ); + e_00_b(6) <= not( dcd_110 and tidn ); + e_00_b(7) <= not( dcd_111 and tidn ); + + e( 0) <= not( e_00_b(0) and + e_00_b(1) and + e_00_b(2) and + e_00_b(3) and + e_00_b(4) and + e_00_b(5) and + e_00_b(6) and + e_00_b(7) ); + + e_01_b(0) <= not( dcd_000 and tiup ); + e_01_b(1) <= not( dcd_001 and combo3_1100_0000 ); + e_01_b(2) <= not( dcd_010 and combo3_0000_0011 ); + e_01_b(3) <= not( dcd_011 and tiup ); + e_01_b(4) <= not( dcd_100 and combo3_1111_1110 ); + e_01_b(5) <= not( dcd_101 and tidn ); + e_01_b(6) <= not( dcd_110 and tidn ); + e_01_b(7) <= not( dcd_111 and tidn ); + + e( 1) <= not( e_01_b(0) and + e_01_b(1) and + e_01_b(2) and + e_01_b(3) and + e_01_b(4) and + e_01_b(5) and + e_01_b(6) and + e_01_b(7) ); + + e_02_b(0) <= not( dcd_000 and combo3_1111_1000 ); + e_02_b(1) <= not( dcd_001 and combo3_0011_1110 ); + e_02_b(2) <= not( dcd_010 and combo3_0000_0011 ); + e_02_b(3) <= not( dcd_011 and combo3_1111_1100 ); + e_02_b(4) <= not( dcd_100 and combo3_0000_0001 ); + e_02_b(5) <= not( dcd_101 and tiup ); + e_02_b(6) <= not( dcd_110 and combo3_1100_0000 ); + e_02_b(7) <= not( dcd_111 and tidn ); + + e( 2) <= not( e_02_b(0) and + e_02_b(1) and + e_02_b(2) and + e_02_b(3) and + e_02_b(4) and + e_02_b(5) and + e_02_b(6) and + e_02_b(7) ); + + e_03_b(0) <= not( dcd_000 and combo3_1110_0110 ); + e_03_b(1) <= not( dcd_001 and combo3_0011_0001 ); + e_03_b(2) <= not( dcd_010 and combo3_1100_0011 ); + e_03_b(3) <= not( dcd_011 and combo3_1100_0011 ); + e_03_b(4) <= not( dcd_100 and combo3_1100_0001 ); + e_03_b(5) <= not( dcd_101 and combo3_1111_0000 ); + e_03_b(6) <= not( dcd_110 and combo3_0011_1111 ); + e_03_b(7) <= not( dcd_111 and combo3_1000_0000 ); + + e( 3) <= not( e_03_b(0) and + e_03_b(1) and + e_03_b(2) and + e_03_b(3) and + e_03_b(4) and + e_03_b(5) and + e_03_b(6) and + e_03_b(7) ); + + e_04_b(0) <= not( dcd_000 and combo3_1101_0101 ); + e_04_b(1) <= not( dcd_001 and combo3_0010_1101 ); + e_04_b(2) <= not( dcd_010 and combo3_1011_0011 ); + e_04_b(3) <= not( dcd_011 and combo3_0011_0011 ); + e_04_b(4) <= not( dcd_100 and combo3_0011_0001 ); + e_04_b(5) <= not( dcd_101 and combo3_1100_1110 ); + e_04_b(6) <= not( dcd_110 and combo3_0011_1100 ); + e_04_b(7) <= not( dcd_111 and combo3_0111_1000 ); + + e( 4) <= not( e_04_b(0) and + e_04_b(1) and + e_04_b(2) and + e_04_b(3) and + e_04_b(4) and + e_04_b(5) and + e_04_b(6) and + e_04_b(7) ); + + e_05_b(0) <= not( dcd_000 and combo3_1000_0011 ); + e_05_b(1) <= not( dcd_001 and combo3_1001_1011 ); + e_05_b(2) <= not( dcd_010 and combo3_0110_1010 ); + e_05_b(3) <= not( dcd_011 and combo3_1010_1010 ); + e_05_b(4) <= not( dcd_100 and combo3_1010_1101 ); + e_05_b(5) <= not( dcd_101 and combo3_0010_1101 ); + e_05_b(6) <= not( dcd_110 and combo3_1011_0010 ); + e_05_b(7) <= not( dcd_111 and combo3_0110_0110 ); + + e( 5) <= not( e_05_b(0) and + e_05_b(1) and + e_05_b(2) and + e_05_b(3) and + e_05_b(4) and + e_05_b(5) and + e_05_b(6) and + e_05_b(7) ); + + e_06_b(0) <= not( dcd_000 and combo3_1000_0100 ); + e_06_b(1) <= not( dcd_001 and combo3_1010_1001 ); + e_06_b(2) <= not( dcd_010 and combo3_0011_1000 ); + e_06_b(3) <= not( dcd_011 and tidn ); + e_06_b(4) <= not( dcd_100 and combo3_0011_1001 ); + e_06_b(5) <= not( dcd_101 and combo3_1001_1001 ); + e_06_b(6) <= not( dcd_110 and combo3_0010_1001 ); + e_06_b(7) <= not( dcd_111 and combo3_0101_0101 ); + + e( 6) <= not( e_06_b(0) and + e_06_b(1) and + e_06_b(2) and + e_06_b(3) and + e_06_b(4) and + e_06_b(5) and + e_06_b(6) and + e_06_b(7) ); + + e_07_b(0) <= not( dcd_000 and combo3_1001_1001 ); + e_07_b(1) <= not( dcd_001 and combo3_1000_1100 ); + e_07_b(2) <= not( dcd_010 and combo3_1010_0110 ); + e_07_b(3) <= not( dcd_011 and tidn ); + e_07_b(4) <= not( dcd_100 and combo3_1100_1010 ); + e_07_b(5) <= not( dcd_101 and combo3_1010_1011 ); + e_07_b(6) <= not( dcd_110 and combo3_0110_0011 ); + e_07_b(7) <= not( dcd_111 and combo3_1000_0000 ); + + e( 7) <= not( e_07_b(0) and + e_07_b(1) and + e_07_b(2) and + e_07_b(3) and + e_07_b(4) and + e_07_b(5) and + e_07_b(6) and + e_07_b(7) ); + + e_08_b(0) <= not( dcd_000 and combo3_1000_1101 ); + e_08_b(1) <= not( dcd_001 and combo3_0111_0101 ); + e_08_b(2) <= not( dcd_010 and combo3_1111_0001 ); + e_08_b(3) <= not( dcd_011 and combo3_0000_0011 ); + e_08_b(4) <= not( dcd_100 and combo3_0101_1000 ); + e_08_b(5) <= not( dcd_101 and combo3_0000_0110 ); + e_08_b(6) <= not( dcd_110 and combo3_1101_0010 ); + e_08_b(7) <= not( dcd_111 and combo3_0110_0000 ); + + e( 8) <= not( e_08_b(0) and + e_08_b(1) and + e_08_b(2) and + e_08_b(3) and + e_08_b(4) and + e_08_b(5) and + e_08_b(6) and + e_08_b(7) ); + + e_09_b(0) <= not( dcd_000 and combo3_1010_1100 ); + e_09_b(1) <= not( dcd_001 and combo3_0111_0001 ); + e_09_b(2) <= not( dcd_010 and combo3_0001_0100 ); + e_09_b(3) <= not( dcd_011 and combo3_1000_0101 ); + e_09_b(4) <= not( dcd_100 and combo3_1111_0100 ); + e_09_b(5) <= not( dcd_101 and combo3_0000_1010 ); + e_09_b(6) <= not( dcd_110 and combo3_0111_1001 ); + e_09_b(7) <= not( dcd_111 and combo3_0101_0000 ); + + e( 9) <= not( e_09_b(0) and + e_09_b(1) and + e_09_b(2) and + e_09_b(3) and + e_09_b(4) and + e_09_b(5) and + e_09_b(6) and + e_09_b(7) ); + + e_10_b(0) <= not( dcd_000 and combo3_1010_0100 ); + e_10_b(1) <= not( dcd_001 and combo3_0001_1000 ); + e_10_b(2) <= not( dcd_010 and combo3_0000_0101 ); + e_10_b(3) <= not( dcd_011 and combo3_0100_1001 ); + e_10_b(4) <= not( dcd_100 and combo3_0001_1110 ); + e_10_b(5) <= not( dcd_101 and combo3_0001_1011 ); + e_10_b(6) <= not( dcd_110 and combo3_0111_1010 ); + e_10_b(7) <= not( dcd_111 and combo3_0001_1100 ); + + e(10) <= not( e_10_b(0) and + e_10_b(1) and + e_10_b(2) and + e_10_b(3) and + e_10_b(4) and + e_10_b(5) and + e_10_b(6) and + e_10_b(7) ); + + e_11_b(0) <= not( dcd_000 and combo3_1110_1010 ); + e_11_b(1) <= not( dcd_001 and combo3_1100_0010 ); + e_11_b(2) <= not( dcd_010 and combo3_1010_1100 ); + e_11_b(3) <= not( dcd_011 and combo3_1011_0110 ); + e_11_b(4) <= not( dcd_100 and combo3_1011_0011 ); + e_11_b(5) <= not( dcd_101 and combo3_0011_0101 ); + e_11_b(6) <= not( dcd_110 and combo3_0100_1001 ); + e_11_b(7) <= not( dcd_111 and combo3_0010_1000 ); + + e(11) <= not( e_11_b(0) and + e_11_b(1) and + e_11_b(2) and + e_11_b(3) and + e_11_b(4) and + e_11_b(5) and + e_11_b(6) and + e_11_b(7) ); + + e_12_b(0) <= not( dcd_000 and combo3_1111_1010 ); + e_12_b(1) <= not( dcd_001 and combo3_1110_0100 ); + e_12_b(2) <= not( dcd_010 and combo3_0010_0100 ); + e_12_b(3) <= not( dcd_011 and combo3_1100_1001 ); + e_12_b(4) <= not( dcd_100 and combo3_0111_1111 ); + e_12_b(5) <= not( dcd_101 and combo3_1111_0100 ); + e_12_b(6) <= not( dcd_110 and combo3_1011_0111 ); + e_12_b(7) <= not( dcd_111 and combo3_1100_1010 ); + + e(12) <= not( e_12_b(0) and + e_12_b(1) and + e_12_b(2) and + e_12_b(3) and + e_12_b(4) and + e_12_b(5) and + e_12_b(6) and + e_12_b(7) ); + + e_13_b(0) <= not( dcd_000 and combo3_1001_1000 ); + e_13_b(1) <= not( dcd_001 and combo3_0101_1011 ); + e_13_b(2) <= not( dcd_010 and combo3_1101_1100 ); + e_13_b(3) <= not( dcd_011 and combo3_0000_0110 ); + e_13_b(4) <= not( dcd_100 and combo3_0100_0011 ); + e_13_b(5) <= not( dcd_101 and combo3_1110_1000 ); + e_13_b(6) <= not( dcd_110 and combo3_1111_1110 ); + e_13_b(7) <= not( dcd_111 and combo3_1001_1010 ); + + e(13) <= not( e_13_b(0) and + e_13_b(1) and + e_13_b(2) and + e_13_b(3) and + e_13_b(4) and + e_13_b(5) and + e_13_b(6) and + e_13_b(7) ); + + e_14_b(0) <= not( dcd_000 and combo3_0101_0100 ); + e_14_b(1) <= not( dcd_001 and combo3_0010_0110 ); + e_14_b(2) <= not( dcd_010 and combo3_0101_0000 ); + e_14_b(3) <= not( dcd_011 and combo3_0111_0000 ); + e_14_b(4) <= not( dcd_100 and combo3_0010_1101 ); + e_14_b(5) <= not( dcd_101 and combo3_1101_0100 ); + e_14_b(6) <= not( dcd_110 and combo3_1100_1000 ); + e_14_b(7) <= not( dcd_111 and combo3_0110_1000 ); + + e(14) <= not( e_14_b(0) and + e_14_b(1) and + e_14_b(2) and + e_14_b(3) and + e_14_b(4) and + e_14_b(5) and + e_14_b(6) and + e_14_b(7) ); + + e_15_b(0) <= not( dcd_000 and combo3_0101_1011 ); + e_15_b(1) <= not( dcd_001 and combo3_0010_0000 ); + e_15_b(2) <= not( dcd_010 and combo3_1101_0110 ); + e_15_b(3) <= not( dcd_011 and combo3_1000_0001 ); + e_15_b(4) <= not( dcd_100 and combo3_1001_0110 ); + e_15_b(5) <= not( dcd_101 and combo3_1110_0101 ); + e_15_b(6) <= not( dcd_110 and combo3_0100_1110 ); + e_15_b(7) <= not( dcd_111 and combo3_1110_0000 ); + + e(15) <= not( e_15_b(0) and + e_15_b(1) and + e_15_b(2) and + e_15_b(3) and + e_15_b(4) and + e_15_b(5) and + e_15_b(6) and + e_15_b(7) ); + + e_16_b(0) <= not( dcd_000 and combo3_0100_1000 ); + e_16_b(1) <= not( dcd_001 and combo3_0010_0101 ); + e_16_b(2) <= not( dcd_010 and combo3_1001_0111 ); + e_16_b(3) <= not( dcd_011 and combo3_0011_1010 ); + e_16_b(4) <= not( dcd_100 and combo3_0000_0101 ); + e_16_b(5) <= not( dcd_101 and combo3_1110_0100 ); + e_16_b(6) <= not( dcd_110 and combo3_0000_1111 ); + e_16_b(7) <= not( dcd_111 and combo3_0000_0100 ); + + e(16) <= not( e_16_b(0) and + e_16_b(1) and + e_16_b(2) and + e_16_b(3) and + e_16_b(4) and + e_16_b(5) and + e_16_b(6) and + e_16_b(7) ); + + e_17_b(0) <= not( dcd_000 and combo3_0000_1011 ); + e_17_b(1) <= not( dcd_001 and combo3_1100_1111 ); + e_17_b(2) <= not( dcd_010 and combo3_0000_1011 ); + e_17_b(3) <= not( dcd_011 and combo3_0010_0000 ); + e_17_b(4) <= not( dcd_100 and combo3_1101_0011 ); + e_17_b(5) <= not( dcd_101 and combo3_0010_1000 ); + e_17_b(6) <= not( dcd_110 and combo3_1111_0010 ); + e_17_b(7) <= not( dcd_111 and combo3_0100_0110 ); + + e(17) <= not( e_17_b(0) and + e_17_b(1) and + e_17_b(2) and + e_17_b(3) and + e_17_b(4) and + e_17_b(5) and + e_17_b(6) and + e_17_b(7) ); + + e_18_b(0) <= not( dcd_000 and combo3_0000_1001 ); + e_18_b(1) <= not( dcd_001 and combo3_1100_1101 ); + e_18_b(2) <= not( dcd_010 and combo3_0000_1010 ); + e_18_b(3) <= not( dcd_011 and combo3_0000_0001 ); + e_18_b(4) <= not( dcd_100 and combo3_0101_0000 ); + e_18_b(5) <= not( dcd_101 and combo3_1001_0100 ); + e_18_b(6) <= not( dcd_110 and combo3_0101_0010 ); + e_18_b(7) <= not( dcd_111 and tidn ); + + e(18) <= not( e_18_b(0) and + e_18_b(1) and + e_18_b(2) and + e_18_b(3) and + e_18_b(4) and + e_18_b(5) and + e_18_b(6) and + e_18_b(7) ); + + e_19_b(0) <= not( dcd_000 and combo3_0111_1111 ); + e_19_b(1) <= not( dcd_001 and tiup ); + e_19_b(2) <= not( dcd_010 and tiup ); + e_19_b(3) <= not( dcd_011 and tiup ); + e_19_b(4) <= not( dcd_100 and tiup ); + e_19_b(5) <= not( dcd_101 and tiup ); + e_19_b(6) <= not( dcd_110 and tiup ); + e_19_b(7) <= not( dcd_111 and tiup ); + + e(19) <= not( e_19_b(0) and + e_19_b(1) and + e_19_b(2) and + e_19_b(3) and + e_19_b(4) and + e_19_b(5) and + e_19_b(6) and + e_19_b(7) ); + + + +--//####################################### +--//## RANGE VECTORs +--//####################################### + + r_00_b(0) <= not( dcd_000 and tiup ); + r_00_b(1) <= not( dcd_001 and tiup ); + r_00_b(2) <= not( dcd_010 and tiup ); + r_00_b(3) <= not( dcd_011 and combo3_1110_0000 ); + r_00_b(4) <= not( dcd_100 and tidn ); + r_00_b(5) <= not( dcd_101 and tidn ); + r_00_b(6) <= not( dcd_110 and tidn ); + r_00_b(7) <= not( dcd_111 and tidn ); + + r( 0) <= not( r_00_b(0) and + r_00_b(1) and + r_00_b(2) and + r_00_b(3) and + r_00_b(4) and + r_00_b(5) and + r_00_b(6) and + r_00_b(7) ); + + r_01_b(0) <= not( dcd_000 and tiup ); + r_01_b(1) <= not( dcd_001 and combo3_1100_0000 ); + r_01_b(2) <= not( dcd_010 and tidn ); + r_01_b(3) <= not( dcd_011 and combo3_0001_1111 ); + r_01_b(4) <= not( dcd_100 and tiup ); + r_01_b(5) <= not( dcd_101 and tiup ); + r_01_b(6) <= not( dcd_110 and tiup ); + r_01_b(7) <= not( dcd_111 and tiup ); + + r( 1) <= not( r_01_b(0) and + r_01_b(1) and + r_01_b(2) and + r_01_b(3) and + r_01_b(4) and + r_01_b(5) and + r_01_b(6) and + r_01_b(7) ); + + r_02_b(0) <= not( dcd_000 and combo3_1111_0000 ); + r_02_b(1) <= not( dcd_001 and combo3_0011_1111 ); + r_02_b(2) <= not( dcd_010 and combo3_1000_0000 ); + r_02_b(3) <= not( dcd_011 and combo3_0001_1111 ); + r_02_b(4) <= not( dcd_100 and tiup ); + r_02_b(5) <= not( dcd_101 and combo3_1000_0000 ); + r_02_b(6) <= not( dcd_110 and tidn ); + r_02_b(7) <= not( dcd_111 and tidn ); + + r( 2) <= not( r_02_b(0) and + r_02_b(1) and + r_02_b(2) and + r_02_b(3) and + r_02_b(4) and + r_02_b(5) and + r_02_b(6) and + r_02_b(7) ); + + r_03_b(0) <= not( dcd_000 and combo3_1100_1110 ); + r_03_b(1) <= not( dcd_001 and combo3_0011_1000 ); + r_03_b(2) <= not( dcd_010 and combo3_0111_1000 ); + r_03_b(3) <= not( dcd_011 and combo3_0001_1111 ); + r_03_b(4) <= not( dcd_100 and combo3_1000_0000 ); + r_03_b(5) <= not( dcd_101 and combo3_0111_1111 ); + r_03_b(6) <= not( dcd_110 and combo3_1100_0000 ); + r_03_b(7) <= not( dcd_111 and tidn ); + + r( 3) <= not( r_03_b(0) and + r_03_b(1) and + r_03_b(2) and + r_03_b(3) and + r_03_b(4) and + r_03_b(5) and + r_03_b(6) and + r_03_b(7) ); + + r_04_b(0) <= not( dcd_000 and combo3_1010_1101 ); + r_04_b(1) <= not( dcd_001 and combo3_0010_0110 ); + r_04_b(2) <= not( dcd_010 and combo3_0110_0111 ); + r_04_b(3) <= not( dcd_011 and combo3_0001_1000 ); + r_04_b(4) <= not( dcd_100 and combo3_0111_0000 ); + r_04_b(5) <= not( dcd_101 and combo3_0111_1000 ); + r_04_b(6) <= not( dcd_110 and combo3_0011_1111 ); + r_04_b(7) <= not( dcd_111 and combo3_1000_0000 ); + + r( 4) <= not( r_04_b(0) and + r_04_b(1) and + r_04_b(2) and + r_04_b(3) and + r_04_b(4) and + r_04_b(5) and + r_04_b(6) and + r_04_b(7) ); + + r_05_b(0) <= not( dcd_000 and combo3_1111_1001 ); + r_05_b(1) <= not( dcd_001 and combo3_1011_0101 ); + r_05_b(2) <= not( dcd_010 and combo3_0101_0110 ); + r_05_b(3) <= not( dcd_011 and combo3_1001_0110 ); + r_05_b(4) <= not( dcd_100 and combo3_0110_1100 ); + r_05_b(5) <= not( dcd_101 and combo3_0110_0111 ); + r_05_b(6) <= not( dcd_110 and combo3_0011_1000 ); + r_05_b(7) <= not( dcd_111 and combo3_0111_0000 ); + + r( 5) <= not( r_05_b(0) and + r_05_b(1) and + r_05_b(2) and + r_05_b(3) and + r_05_b(4) and + r_05_b(5) and + r_05_b(6) and + r_05_b(7) ); + + r_06_b(0) <= not( dcd_000 and combo3_0001_1010 ); + r_06_b(1) <= not( dcd_001 and combo3_1101_1110 ); + r_06_b(2) <= not( dcd_010 and combo3_0011_1100 ); + r_06_b(3) <= not( dcd_011 and combo3_0100_1101 ); + r_06_b(4) <= not( dcd_100 and combo3_0100_1010 ); + r_06_b(5) <= not( dcd_101 and combo3_0101_0100 ); + r_06_b(6) <= not( dcd_110 and combo3_1011_0110 ); + r_06_b(7) <= not( dcd_111 and combo3_0100_1100 ); + + r( 6) <= not( r_06_b(0) and + r_06_b(1) and + r_06_b(2) and + r_06_b(3) and + r_06_b(4) and + r_06_b(5) and + r_06_b(6) and + r_06_b(7) ); + + r_07_b(0) <= not( dcd_000 and combo3_0010_1101 ); + r_07_b(1) <= not( dcd_001 and combo3_1001_1001 ); + r_07_b(2) <= not( dcd_010 and combo3_1100_0100 ); + r_07_b(3) <= not( dcd_011 and combo3_1001_0110 ); + r_07_b(4) <= not( dcd_100 and combo3_0001_1111 ); + r_07_b(5) <= not( dcd_101 and combo3_0000_1110 ); + r_07_b(6) <= not( dcd_110 and combo3_0110_1101 ); + r_07_b(7) <= not( dcd_111 and combo3_0110_1010 ); + + r( 7) <= not( r_07_b(0) and + r_07_b(1) and + r_07_b(2) and + r_07_b(3) and + r_07_b(4) and + r_07_b(5) and + r_07_b(6) and + r_07_b(7) ); + + r_08_b(0) <= not( dcd_000 and combo3_0000_0010 ); + r_08_b(1) <= not( dcd_001 and combo3_1011_0101 ); + r_08_b(2) <= not( dcd_010 and combo3_1100_1001 ); + r_08_b(3) <= not( dcd_011 and combo3_1100_1101 ); + r_08_b(4) <= not( dcd_100 and combo3_1001_1111 ); + r_08_b(5) <= not( dcd_101 and combo3_0001_0010 ); + r_08_b(6) <= not( dcd_110 and combo3_1011_0110 ); + r_08_b(7) <= not( dcd_111 and combo3_0011_1111 ); + + r( 8) <= not( r_08_b(0) and + r_08_b(1) and + r_08_b(2) and + r_08_b(3) and + r_08_b(4) and + r_08_b(5) and + r_08_b(6) and + r_08_b(7) ); + + r_09_b(0) <= not( dcd_000 and combo3_0100_1010 ); + r_09_b(1) <= not( dcd_001 and combo3_0011_0001 ); + r_09_b(2) <= not( dcd_010 and combo3_1101_1101 ); + r_09_b(3) <= not( dcd_011 and combo3_1100_0111 ); + r_09_b(4) <= not( dcd_100 and combo3_0101_1111 ); + r_09_b(5) <= not( dcd_101 and combo3_0010_0111 ); + r_09_b(6) <= not( dcd_110 and combo3_1110_1101 ); + r_09_b(7) <= not( dcd_111 and combo3_0011_0000 ); + + r( 9) <= not( r_09_b(0) and + r_09_b(1) and + r_09_b(2) and + r_09_b(3) and + r_09_b(4) and + r_09_b(5) and + r_09_b(6) and + r_09_b(7) ); + + r_10_b(0) <= not( dcd_000 and combo3_0111_1010 ); + r_10_b(1) <= not( dcd_001 and combo3_0011_1011 ); + r_10_b(2) <= not( dcd_010 and combo3_0001_0111 ); + r_10_b(3) <= not( dcd_011 and combo3_1101_0111 ); + r_10_b(4) <= not( dcd_100 and combo3_0001_0001 ); + r_10_b(5) <= not( dcd_101 and combo3_0111_0110 ); + r_10_b(6) <= not( dcd_110 and combo3_0110_0111 ); + r_10_b(7) <= not( dcd_111 and combo3_1010_1000 ); + + r(10) <= not( r_10_b(0) and + r_10_b(1) and + r_10_b(2) and + r_10_b(3) and + r_10_b(4) and + r_10_b(5) and + r_10_b(6) and + r_10_b(7) ); + + r_11_b(0) <= not( dcd_000 and combo3_0000_1111 ); + r_11_b(1) <= not( dcd_001 and combo3_0101_0100 ); + r_11_b(2) <= not( dcd_010 and combo3_1110_1101 ); + r_11_b(3) <= not( dcd_011 and combo3_0001_0101 ); + r_11_b(4) <= not( dcd_100 and combo3_1010_1000 ); + r_11_b(5) <= not( dcd_101 and combo3_0111_1101 ); + r_11_b(6) <= not( dcd_110 and combo3_1011_0100 ); + r_11_b(7) <= not( dcd_111 and combo3_1000_0100 ); + + r(11) <= not( r_11_b(0) and + r_11_b(1) and + r_11_b(2) and + r_11_b(3) and + r_11_b(4) and + r_11_b(5) and + r_11_b(6) and + r_11_b(7) ); + + r_12_b(0) <= not( dcd_000 and combo3_1100_1111 ); + r_12_b(1) <= not( dcd_001 and combo3_0110_1011 ); + r_12_b(2) <= not( dcd_010 and combo3_0100_1000 ); + r_12_b(3) <= not( dcd_011 and combo3_0111_1011 ); + r_12_b(4) <= not( dcd_100 and combo3_1101_0110 ); + r_12_b(5) <= not( dcd_101 and combo3_0001_0001 ); + r_12_b(6) <= not( dcd_110 and combo3_1011_0011 ); + r_12_b(7) <= not( dcd_111 and combo3_0100_0000 ); + + r(12) <= not( r_12_b(0) and + r_12_b(1) and + r_12_b(2) and + r_12_b(3) and + r_12_b(4) and + r_12_b(5) and + r_12_b(6) and + r_12_b(7) ); + + r_13_b(0) <= not( dcd_000 and combo3_0101_0001 ); + r_13_b(1) <= not( dcd_001 and combo3_0011_1100 ); + r_13_b(2) <= not( dcd_010 and combo3_0101_1011 ); + r_13_b(3) <= not( dcd_011 and combo3_0001_1000 ); + r_13_b(4) <= not( dcd_100 and combo3_0110_0010 ); + r_13_b(5) <= not( dcd_101 and combo3_1101_0100 ); + r_13_b(6) <= not( dcd_110 and combo3_0100_0011 ); + r_13_b(7) <= not( dcd_111 and combo3_1000_1010 ); + + r(13) <= not( r_13_b(0) and + r_13_b(1) and + r_13_b(2) and + r_13_b(3) and + r_13_b(4) and + r_13_b(5) and + r_13_b(6) and + r_13_b(7) ); + + r_14_b(0) <= not( dcd_000 and combo3_1000_0000 ); + r_14_b(1) <= not( dcd_001 and tidn ); + r_14_b(2) <= not( dcd_010 and tidn ); + r_14_b(3) <= not( dcd_011 and tidn ); + r_14_b(4) <= not( dcd_100 and tidn ); + r_14_b(5) <= not( dcd_101 and tidn ); + r_14_b(6) <= not( dcd_110 and tidn ); + r_14_b(7) <= not( dcd_111 and tidn ); + + r(14) <= not( r_14_b(0) and + r_14_b(1) and + r_14_b(2) and + r_14_b(3) and + r_14_b(4) and + r_14_b(5) and + r_14_b(6) and + r_14_b(7) ); + + + + +--//####################################### +--//## RENUMBERING OUTPUTS +--//####################################### + + est(1 to 20) <= e(0 to 19);-- renumbering + rng(6 to 20) <= r(0 to 14);-- renumbering + + +end; -- fuq_tblres ARCHITECTURE diff --git a/rel/src/vhdl/work/fuq_tblsqe.vhdl b/rel/src/vhdl/work/fuq_tblsqe.vhdl new file mode 100644 index 0000000..4dc293c --- /dev/null +++ b/rel/src/vhdl/work/fuq_tblsqe.vhdl @@ -0,0 +1,1219 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; + use ieee.std_logic_1164.all ; +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + +-- 01101010000001011111 010110010111010 0 +-- 01100111001110100011 010101110110100 1 +-- 01100100011111101101 010101010111010 2 +-- 01100001110100110011 010100111001000 3 +-- 01011111001101101011 010100011011110 4 +-- 01011100101010001011 010011111111100 5 +-- 01011010001010001101 010011100100100 6 +-- 01010111101101101001 010011001010010 7 +-- 01010101010100010101 010010110001000 8 +-- 01010010111110001101 010010011000100 9 +-- 01010000101011000111 010010000001000 10 +-- 01001110011010111101 010001101010010 11 +-- 01001100001101101011 010001010100000 12 +-- 01001010000011001011 010000111110110 13 +-- 01000111111011010101 010000101010000 14 +-- 01000101110110000011 010000010110000 15 +-- 01000011110011010011 010000000010100 16 +-- 01000001110010111111 001111101111110 17 +-- 00111111110101000001 001111011101010 18 +-- 00111101111001010101 001111001011110 19 +-- 00111011111111110111 001110111010100 20 +-- 00111010001000100001 001110101001110 21 +-- 00111000010011010011 001110011001100 22 +-- 00110110100000000101 001110001001110 23 +-- 00110100101110110111 001101111010100 24 +-- 00110010111111100001 001101101011100 25 +-- 00110001010010000011 001101011101000 26 +-- 00101111100110011001 001101001111000 27 +-- 00101101111100100001 001101000001010 28 +-- 00101100010100010101 001100110100000 29 +-- 00101010101101110101 001100100111000 30 +-- 00101001001000111011 001100011010010 31 +-- 00100111100101100111 001100001110000 32 +-- 00100110000011110101 001100000010000 33 +-- 00100100100011100101 001011110110010 34 +-- 00100011000100110001 001011101011000 35 +-- 00100001100111011001 001011011111110 36 +-- 00100000001011011001 001011010101000 37 +-- 00011110110000110001 001011001010100 38 +-- 00011101010111011101 001011000000000 39 +-- 00011011111111011011 001010110110000 40 +-- 00011010101000101001 001010101100000 41 +-- 00011001010011000111 001010100010100 42 +-- 00010111111110110011 001010011001000 43 +-- 00010110101011101001 001010010000000 44 +-- 00010101011001101001 001010000111000 45 +-- 00010100001000101111 001001111110010 46 +-- 00010010111000111101 001001110101110 47 +-- 00010001101010001111 001001101101010 48 +-- 00010000011100100011 001001100101000 49 +-- 00001111001111111011 001001011101000 50 +-- 00001110000100010001 001001010101010 51 +-- 00001100111001100111 001001001101100 52 +-- 00001011101111111001 001001000110000 53 +-- 00001010100111000111 001000111110110 54 +-- 00001001011111010001 001000110111100 55 +-- 00001000011000010101 001000110000100 56 +-- 00000111010010010001 001000101001100 57 +-- 00000110001101000011 001000100010110 58 +-- 00000101001000101101 001000011100000 59 +-- 00000100000101001011 001000010101100 60 +-- 00000011000010011101 001000001111010 61 +-- 00000010000000100001 001000001001000 62 +-- 00000000111111011001 001000000011000 63 + + +entity fuq_tblsqe is +generic( expand_type : integer := 2 ); -- 0 - ibm tech, 1 - other ); +port( + f :in std_ulogic_vector(1 to 6); + est :out std_ulogic_vector(1 to 20); + rng :out std_ulogic_vector(6 to 20) + +); -- end ports + + + +end fuq_tblsqe; -- ENTITY + + +architecture fuq_tblsqe of fuq_tblsqe is + + constant tiup :std_ulogic := '1'; + constant tidn :std_ulogic := '0'; + + signal dcd_00x :std_ulogic; + signal dcd_01x :std_ulogic; + signal dcd_10x :std_ulogic; + signal dcd_11x :std_ulogic; + signal dcd_000 :std_ulogic; + signal dcd_001 :std_ulogic; + signal dcd_010 :std_ulogic; + signal dcd_011 :std_ulogic; + signal dcd_100 :std_ulogic; + signal dcd_101 :std_ulogic; + signal dcd_110 :std_ulogic; + signal dcd_111 :std_ulogic; + signal combo2_1000 :std_ulogic; + signal combo2_0100 :std_ulogic; + signal combo2_1100 :std_ulogic; + signal combo2_0010 :std_ulogic; + signal combo2_1010 :std_ulogic; + signal combo2_0110 :std_ulogic; + signal combo2_1110 :std_ulogic; + signal combo2_0001 :std_ulogic; + signal combo2_1001 :std_ulogic; + signal combo2_0101 :std_ulogic; + signal combo2_1101 :std_ulogic; + signal combo2_0011 :std_ulogic; + signal combo2_1011 :std_ulogic; + signal combo2_0111 :std_ulogic; + signal combo2_1000_xxxx_b :std_ulogic; + signal combo2_0100_xxxx_b :std_ulogic; + signal combo2_1100_xxxx_b :std_ulogic; + signal combo2_0010_xxxx_b :std_ulogic; + signal combo2_1010_xxxx_b :std_ulogic; + signal combo2_0110_xxxx_b :std_ulogic; + signal combo2_1110_xxxx_b :std_ulogic; + signal combo2_0001_xxxx_b :std_ulogic; + signal combo2_1001_xxxx_b :std_ulogic; + signal combo2_0101_xxxx_b :std_ulogic; + signal combo2_1101_xxxx_b :std_ulogic; + signal combo2_0011_xxxx_b :std_ulogic; + signal combo2_1011_xxxx_b :std_ulogic; + signal combo2_0111_xxxx_b :std_ulogic; + signal combo2_xxxx_1000_b :std_ulogic; + signal combo2_xxxx_0100_b :std_ulogic; + signal combo2_xxxx_1100_b :std_ulogic; + signal combo2_xxxx_0010_b :std_ulogic; + signal combo2_xxxx_1010_b :std_ulogic; + signal combo2_xxxx_0110_b :std_ulogic; + signal combo2_xxxx_1110_b :std_ulogic; + signal combo2_xxxx_0001_b :std_ulogic; + signal combo2_xxxx_1001_b :std_ulogic; + signal combo2_xxxx_0101_b :std_ulogic; + signal combo2_xxxx_1101_b :std_ulogic; + signal combo2_xxxx_0011_b :std_ulogic; + signal combo2_xxxx_1011_b :std_ulogic; + signal combo2_xxxx_0111_b :std_ulogic; + signal combo3_0000_0001 :std_ulogic; + signal combo3_0000_0011 :std_ulogic; + signal combo3_0000_0100 :std_ulogic; + signal combo3_0000_0111 :std_ulogic; + signal combo3_0000_1001 :std_ulogic; + signal combo3_0000_1010 :std_ulogic; + signal combo3_0000_1011 :std_ulogic; + signal combo3_0000_1101 :std_ulogic; + signal combo3_0000_1111 :std_ulogic; + signal combo3_0001_0001 :std_ulogic; + signal combo3_0001_0010 :std_ulogic; + signal combo3_0001_0100 :std_ulogic; + signal combo3_0001_0101 :std_ulogic; + signal combo3_0001_0111 :std_ulogic; + signal combo3_0001_1000 :std_ulogic; + signal combo3_0001_1100 :std_ulogic; + signal combo3_0001_1101 :std_ulogic; + signal combo3_0001_1110 :std_ulogic; + signal combo3_0001_1111 :std_ulogic; + signal combo3_0010_0001 :std_ulogic; + signal combo3_0010_0011 :std_ulogic; + signal combo3_0010_0100 :std_ulogic; + signal combo3_0010_0101 :std_ulogic; + signal combo3_0010_1000 :std_ulogic; + signal combo3_0010_1001 :std_ulogic; + signal combo3_0010_1010 :std_ulogic; + signal combo3_0010_1100 :std_ulogic; + signal combo3_0010_1101 :std_ulogic; + signal combo3_0010_1110 :std_ulogic; + signal combo3_0010_1111 :std_ulogic; + signal combo3_0011_0000 :std_ulogic; + signal combo3_0011_0001 :std_ulogic; + signal combo3_0011_0011 :std_ulogic; + signal combo3_0011_0101 :std_ulogic; + signal combo3_0011_0110 :std_ulogic; + signal combo3_0011_1000 :std_ulogic; + signal combo3_0011_1001 :std_ulogic; + signal combo3_0011_1110 :std_ulogic; + signal combo3_0011_1111 :std_ulogic; + signal combo3_0100_0000 :std_ulogic; + signal combo3_0100_0010 :std_ulogic; + signal combo3_0100_0100 :std_ulogic; + signal combo3_0100_0101 :std_ulogic; + signal combo3_0100_1001 :std_ulogic; + signal combo3_0100_1100 :std_ulogic; + signal combo3_0100_1110 :std_ulogic; + signal combo3_0100_1111 :std_ulogic; + signal combo3_0101_0010 :std_ulogic; + signal combo3_0101_0100 :std_ulogic; + signal combo3_0101_0110 :std_ulogic; + signal combo3_0101_1001 :std_ulogic; + signal combo3_0101_1100 :std_ulogic; + signal combo3_0101_1111 :std_ulogic; + signal combo3_0110_0000 :std_ulogic; + signal combo3_0110_0011 :std_ulogic; + signal combo3_0110_0110 :std_ulogic; + signal combo3_0110_0111 :std_ulogic; + signal combo3_0110_1100 :std_ulogic; + signal combo3_0110_1101 :std_ulogic; + signal combo3_0110_1111 :std_ulogic; + signal combo3_0111_0000 :std_ulogic; + signal combo3_0111_0101 :std_ulogic; + signal combo3_0111_0111 :std_ulogic; + signal combo3_0111_1000 :std_ulogic; + signal combo3_0111_1001 :std_ulogic; + signal combo3_0111_1010 :std_ulogic; + signal combo3_0111_1111 :std_ulogic; + signal combo3_1000_0000 :std_ulogic; + signal combo3_1000_0011 :std_ulogic; + signal combo3_1000_0110 :std_ulogic; + signal combo3_1000_0111 :std_ulogic; + signal combo3_1000_1010 :std_ulogic; + signal combo3_1000_1110 :std_ulogic; + signal combo3_1001_0000 :std_ulogic; + signal combo3_1001_0001 :std_ulogic; + signal combo3_1001_0010 :std_ulogic; + signal combo3_1001_0100 :std_ulogic; + signal combo3_1001_0110 :std_ulogic; + signal combo3_1001_0111 :std_ulogic; + signal combo3_1001_1000 :std_ulogic; + signal combo3_1001_1001 :std_ulogic; + signal combo3_1001_1010 :std_ulogic; + signal combo3_1001_1011 :std_ulogic; + signal combo3_1001_1100 :std_ulogic; + signal combo3_1010_0000 :std_ulogic; + signal combo3_1010_0001 :std_ulogic; + signal combo3_1010_0010 :std_ulogic; + signal combo3_1010_0100 :std_ulogic; + signal combo3_1010_0101 :std_ulogic; + signal combo3_1010_0110 :std_ulogic; + signal combo3_1010_0111 :std_ulogic; + signal combo3_1010_1001 :std_ulogic; + signal combo3_1010_1010 :std_ulogic; + signal combo3_1010_1100 :std_ulogic; + signal combo3_1010_1101 :std_ulogic; + signal combo3_1010_1111 :std_ulogic; + signal combo3_1011_0001 :std_ulogic; + signal combo3_1011_0010 :std_ulogic; + signal combo3_1011_0100 :std_ulogic; + signal combo3_1011_0101 :std_ulogic; + signal combo3_1011_1000 :std_ulogic; + signal combo3_1011_1010 :std_ulogic; + signal combo3_1011_1100 :std_ulogic; + signal combo3_1100_0000 :std_ulogic; + signal combo3_1100_0001 :std_ulogic; + signal combo3_1100_0011 :std_ulogic; + signal combo3_1100_0101 :std_ulogic; + signal combo3_1100_0110 :std_ulogic; + signal combo3_1100_0111 :std_ulogic; + signal combo3_1100_1001 :std_ulogic; + signal combo3_1100_1010 :std_ulogic; + signal combo3_1100_1011 :std_ulogic; + signal combo3_1100_1101 :std_ulogic; + signal combo3_1100_1111 :std_ulogic; + signal combo3_1101_0010 :std_ulogic; + signal combo3_1101_0011 :std_ulogic; + signal combo3_1101_1000 :std_ulogic; + signal combo3_1101_1001 :std_ulogic; + signal combo3_1101_1010 :std_ulogic; + signal combo3_1101_1100 :std_ulogic; + signal combo3_1101_1110 :std_ulogic; + signal combo3_1101_1111 :std_ulogic; + signal combo3_1110_0000 :std_ulogic; + signal combo3_1110_0001 :std_ulogic; + signal combo3_1110_0011 :std_ulogic; + signal combo3_1110_0110 :std_ulogic; + signal combo3_1110_1000 :std_ulogic; + signal combo3_1110_1010 :std_ulogic; + signal combo3_1110_1101 :std_ulogic; + signal combo3_1111_0000 :std_ulogic; + signal combo3_1111_0001 :std_ulogic; + signal combo3_1111_0010 :std_ulogic; + signal combo3_1111_1000 :std_ulogic; + signal combo3_1111_1001 :std_ulogic; + signal combo3_1111_1010 :std_ulogic; + signal combo3_1111_1100 :std_ulogic; + signal e_00_b :std_ulogic_vector(0 to 7); + signal e_01_b :std_ulogic_vector(0 to 7); + signal e_02_b :std_ulogic_vector(0 to 7); + signal e_03_b :std_ulogic_vector(0 to 7); + signal e_04_b :std_ulogic_vector(0 to 7); + signal e_05_b :std_ulogic_vector(0 to 7); + signal e_06_b :std_ulogic_vector(0 to 7); + signal e_07_b :std_ulogic_vector(0 to 7); + signal e_08_b :std_ulogic_vector(0 to 7); + signal e_09_b :std_ulogic_vector(0 to 7); + signal e_10_b :std_ulogic_vector(0 to 7); + signal e_11_b :std_ulogic_vector(0 to 7); + signal e_12_b :std_ulogic_vector(0 to 7); + signal e_13_b :std_ulogic_vector(0 to 7); + signal e_14_b :std_ulogic_vector(0 to 7); + signal e_15_b :std_ulogic_vector(0 to 7); + signal e_16_b :std_ulogic_vector(0 to 7); + signal e_17_b :std_ulogic_vector(0 to 7); + signal e_18_b :std_ulogic_vector(0 to 7); + signal e_19_b :std_ulogic_vector(0 to 7); + signal e :std_ulogic_vector(0 to 19); + signal r_00_b :std_ulogic_vector(0 to 7); + signal r_01_b :std_ulogic_vector(0 to 7); + signal r_02_b :std_ulogic_vector(0 to 7); + signal r_03_b :std_ulogic_vector(0 to 7); + signal r_04_b :std_ulogic_vector(0 to 7); + signal r_05_b :std_ulogic_vector(0 to 7); + signal r_06_b :std_ulogic_vector(0 to 7); + signal r_07_b :std_ulogic_vector(0 to 7); + signal r_08_b :std_ulogic_vector(0 to 7); + signal r_09_b :std_ulogic_vector(0 to 7); + signal r_10_b :std_ulogic_vector(0 to 7); + signal r_11_b :std_ulogic_vector(0 to 7); + signal r_12_b :std_ulogic_vector(0 to 7); + signal r_13_b :std_ulogic_vector(0 to 7); + signal r_14_b :std_ulogic_vector(0 to 7); + signal r :std_ulogic_vector(0 to 14); + + +begin + + +--//####################################### +--//## decode the upper 3 index bits +--//####################################### + + dcd_00x <= not f(1) and not f(2) ; + dcd_01x <= not f(1) and f(2) ; + dcd_10x <= f(1) and not f(2) ; + dcd_11x <= f(1) and f(2) ; + + dcd_000 <= not f(3) and dcd_00x ; + dcd_001 <= f(3) and dcd_00x ; + dcd_010 <= not f(3) and dcd_01x ; + dcd_011 <= f(3) and dcd_01x ; + dcd_100 <= not f(3) and dcd_10x ; + dcd_101 <= f(3) and dcd_10x ; + dcd_110 <= not f(3) and dcd_11x ; + dcd_111 <= f(3) and dcd_11x ; + + +--//####################################### +--//## combos based on lower 2 index bits +--//####################################### + + combo2_1000 <= not f(5) and not f(6) ;-- [0] + combo2_0100 <= not f(5) and f(6) ;-- [1] + combo2_1100 <= not f(5) ;-- [0,1] + combo2_0010 <= f(5) and not f(6) ;-- [2] + combo2_1010 <= not f(6) ;-- [0,2] + combo2_0110 <= f(5) xor f(6) ;-- [1,2] + combo2_1110 <= not( f(5) and f(6) ) ;-- [0,1,2] + combo2_0001 <= f(5) and f(6) ;-- [3] + combo2_1001 <= not( f(5) xor f(6) ) ;-- [0,3] + combo2_0101 <= f(6) ;-- [1,3] + combo2_1101 <= not( f(5) and not f(6) ) ;-- [1,2,3] + combo2_0011 <= f(5) ;-- [2,3] + combo2_1011 <= not( not f(5) and f(6) ) ;-- [0,2,3] + combo2_0111 <= not( not f(5) and not f(6) ) ;-- [1,2,3] + + +--//####################################### +--//## combos based on lower 3 index bits +--//####################################### + + combo2_1000_xxxx_b <= not( not f(4) and combo2_1000 ); + combo2_0100_xxxx_b <= not( not f(4) and combo2_0100 ); + combo2_1100_xxxx_b <= not( not f(4) and combo2_1100 ); + combo2_0010_xxxx_b <= not( not f(4) and combo2_0010 ); + combo2_1010_xxxx_b <= not( not f(4) and combo2_1010 ); + combo2_0110_xxxx_b <= not( not f(4) and combo2_0110 ); + combo2_1110_xxxx_b <= not( not f(4) and combo2_1110 ); + combo2_0001_xxxx_b <= not( not f(4) and combo2_0001 ); + combo2_1001_xxxx_b <= not( not f(4) and combo2_1001 ); + combo2_0101_xxxx_b <= not( not f(4) and combo2_0101 ); + combo2_1101_xxxx_b <= not( not f(4) and combo2_1101 ); + combo2_0011_xxxx_b <= not( not f(4) and combo2_0011 ); + combo2_1011_xxxx_b <= not( not f(4) and combo2_1011 ); + combo2_0111_xxxx_b <= not( not f(4) and combo2_0111 ); + + + combo2_xxxx_1000_b <= not( f(4) and combo2_1000 ); + combo2_xxxx_0100_b <= not( f(4) and combo2_0100 ); + combo2_xxxx_1100_b <= not( f(4) and combo2_1100 ); + combo2_xxxx_0010_b <= not( f(4) and combo2_0010 ); + combo2_xxxx_1010_b <= not( f(4) and combo2_1010 ); + combo2_xxxx_0110_b <= not( f(4) and combo2_0110 ); + combo2_xxxx_1110_b <= not( f(4) and combo2_1110 ); + combo2_xxxx_0001_b <= not( f(4) and combo2_0001 ); + combo2_xxxx_1001_b <= not( f(4) and combo2_1001 ); + combo2_xxxx_0101_b <= not( f(4) and combo2_0101 ); + combo2_xxxx_1101_b <= not( f(4) and combo2_1101 ); + combo2_xxxx_0011_b <= not( f(4) and combo2_0011 ); + combo2_xxxx_1011_b <= not( f(4) and combo2_1011 ); + combo2_xxxx_0111_b <= not( f(4) and combo2_0111 ); + + + combo3_0000_0001 <= not( combo2_xxxx_0001_b );--i=1, 1 1 + combo3_0000_0011 <= not( combo2_xxxx_0011_b );--i=3, 5 2 + combo3_0000_0100 <= not( combo2_xxxx_0100_b );--i=4, 1 3 + combo3_0000_0111 <= not( combo2_xxxx_0111_b );--i=7, 1 4 + combo3_0000_1001 <= not( combo2_xxxx_1001_b );--i=9, 1 5 + combo3_0000_1010 <= not( combo2_xxxx_1010_b );--i=10, 1 6 + combo3_0000_1011 <= not( combo2_xxxx_1011_b );--i=11, 1 7 + combo3_0000_1101 <= not( combo2_xxxx_1101_b );--i=13, 2 8 + combo3_0000_1111 <= not( not f(4) );--i=15, 1 9 + combo3_0001_0001 <= not( not combo2_0001 );--i=17, 1 10* + combo3_0001_0010 <= not( combo2_0001_xxxx_b and combo2_xxxx_0010_b );--i=18, 1 11 + combo3_0001_0100 <= not( combo2_0001_xxxx_b and combo2_xxxx_0100_b );--i=20, 1 12 + combo3_0001_0101 <= not( combo2_0001_xxxx_b and combo2_xxxx_0101_b );--i=21, 2 13 + combo3_0001_0111 <= not( combo2_0001_xxxx_b and combo2_xxxx_0111_b );--i=23, 1 14 + combo3_0001_1000 <= not( combo2_0001_xxxx_b and combo2_xxxx_1000_b );--i=24, 2 15 + combo3_0001_1100 <= not( combo2_0001_xxxx_b and combo2_xxxx_1100_b );--i=28, 4 16 + combo3_0001_1101 <= not( combo2_0001_xxxx_b and combo2_xxxx_1101_b );--i=29, 2 17 + combo3_0001_1110 <= not( combo2_0001_xxxx_b and combo2_xxxx_1110_b );--i=30, 1 18 + combo3_0001_1111 <= not( combo2_0001_xxxx_b and not f(4) );--i=31, 1 19 + combo3_0010_0001 <= not( combo2_0010_xxxx_b and combo2_xxxx_0001_b );--i=33, 1 20 + combo3_0010_0011 <= not( combo2_0010_xxxx_b and combo2_xxxx_0011_b );--i=35, 1 21 + combo3_0010_0100 <= not( combo2_0010_xxxx_b and combo2_xxxx_0100_b );--i=36, 1 22 + combo3_0010_0101 <= not( combo2_0010_xxxx_b and combo2_xxxx_0101_b );--i=37, 1 23 + combo3_0010_1000 <= not( combo2_0010_xxxx_b and combo2_xxxx_1000_b );--i=40, 3 24 + combo3_0010_1001 <= not( combo2_0010_xxxx_b and combo2_xxxx_1001_b );--i=41, 2 25 + combo3_0010_1010 <= not( combo2_0010_xxxx_b and combo2_xxxx_1010_b );--i=42, 1 26 + combo3_0010_1100 <= not( combo2_0010_xxxx_b and combo2_xxxx_1100_b );--i=44, 1 27 + combo3_0010_1101 <= not( combo2_0010_xxxx_b and combo2_xxxx_1101_b );--i=45, 1 28 + combo3_0010_1110 <= not( combo2_0010_xxxx_b and combo2_xxxx_1110_b );--i=46, 1 29 + combo3_0010_1111 <= not( combo2_0010_xxxx_b and not f(4) );--i=47, 1 30 + combo3_0011_0000 <= not( combo2_0011_xxxx_b );--i=48, 2 31 + combo3_0011_0001 <= not( combo2_0011_xxxx_b and combo2_xxxx_0001_b );--i=49, 1 32 + combo3_0011_0011 <= not( not combo2_0011 );--i=51, 1 33* + combo3_0011_0101 <= not( combo2_0011_xxxx_b and combo2_xxxx_0101_b );--i=53, 1 34 + combo3_0011_0110 <= not( combo2_0011_xxxx_b and combo2_xxxx_0110_b );--i=54, 2 35 + combo3_0011_1000 <= not( combo2_0011_xxxx_b and combo2_xxxx_1000_b );--i=56, 1 36 + combo3_0011_1001 <= not( combo2_0011_xxxx_b and combo2_xxxx_1001_b );--i=57, 1 37 + combo3_0011_1110 <= not( combo2_0011_xxxx_b and combo2_xxxx_1110_b );--i=62, 1 38 + combo3_0011_1111 <= not( combo2_0011_xxxx_b and not f(4) );--i=63, 5 39 + combo3_0100_0000 <= not( combo2_0100_xxxx_b );--i=64, 1 40 + combo3_0100_0010 <= not( combo2_0100_xxxx_b and combo2_xxxx_0010_b );--i=66, 1 41 + combo3_0100_0100 <= not( not combo2_0100 );--i=68, 1 42* + combo3_0100_0101 <= not( combo2_0100_xxxx_b and combo2_xxxx_0101_b );--i=69, 1 43 + combo3_0100_1001 <= not( combo2_0100_xxxx_b and combo2_xxxx_1001_b );--i=73, 1 44 + combo3_0100_1100 <= not( combo2_0100_xxxx_b and combo2_xxxx_1100_b );--i=76, 2 45 + combo3_0100_1110 <= not( combo2_0100_xxxx_b and combo2_xxxx_1110_b );--i=78, 1 46 + combo3_0100_1111 <= not( combo2_0100_xxxx_b and not f(4) );--i=79, 1 47 + combo3_0101_0010 <= not( combo2_0101_xxxx_b and combo2_xxxx_0010_b );--i=82, 2 48 + combo3_0101_0100 <= not( combo2_0101_xxxx_b and combo2_xxxx_0100_b );--i=84, 1 49 + combo3_0101_0110 <= not( combo2_0101_xxxx_b and combo2_xxxx_0110_b );--i=86, 4 50 + combo3_0101_1001 <= not( combo2_0101_xxxx_b and combo2_xxxx_1001_b );--i=89, 2 51 + combo3_0101_1100 <= not( combo2_0101_xxxx_b and combo2_xxxx_1100_b );--i=92, 1 52 + combo3_0101_1111 <= not( combo2_0101_xxxx_b and not f(4) );--i=95, 2 53 + combo3_0110_0000 <= not( combo2_0110_xxxx_b );--i=96, 1 54 + combo3_0110_0011 <= not( combo2_0110_xxxx_b and combo2_xxxx_0011_b );--i=99, 1 55 + combo3_0110_0110 <= not( not combo2_0110 );--i=102, 2 56* + combo3_0110_0111 <= not( combo2_0110_xxxx_b and combo2_xxxx_0111_b );--i=103, 1 57 + combo3_0110_1100 <= not( combo2_0110_xxxx_b and combo2_xxxx_1100_b );--i=108, 2 58 + combo3_0110_1101 <= not( combo2_0110_xxxx_b and combo2_xxxx_1101_b );--i=109, 2 59 + combo3_0110_1111 <= not( combo2_0110_xxxx_b and not f(4) );--i=111, 1 60 + combo3_0111_0000 <= not( combo2_0111_xxxx_b );--i=112, 1 61 + combo3_0111_0101 <= not( combo2_0111_xxxx_b and combo2_xxxx_0101_b );--i=117, 1 62 + combo3_0111_0111 <= not( not combo2_0111 );--i=119, 3 63* + combo3_0111_1000 <= not( combo2_0111_xxxx_b and combo2_xxxx_1000_b );--i=120, 1 64 + combo3_0111_1001 <= not( combo2_0111_xxxx_b and combo2_xxxx_1001_b );--i=121, 2 65 + combo3_0111_1010 <= not( combo2_0111_xxxx_b and combo2_xxxx_1010_b );--i=122, 2 66 + combo3_0111_1111 <= not( combo2_0111_xxxx_b and not f(4) );--i=127, 4 67 + combo3_1000_0000 <= not( combo2_1000_xxxx_b );--i=128, 3 68 + combo3_1000_0011 <= not( combo2_1000_xxxx_b and combo2_xxxx_0011_b );--i=131, 1 69 + combo3_1000_0110 <= not( combo2_1000_xxxx_b and combo2_xxxx_0110_b );--i=134, 1 70 + combo3_1000_0111 <= not( combo2_1000_xxxx_b and combo2_xxxx_0111_b );--i=135, 1 71 + combo3_1000_1010 <= not( combo2_1000_xxxx_b and combo2_xxxx_1010_b );--i=138, 1 72 + combo3_1000_1110 <= not( combo2_1000_xxxx_b and combo2_xxxx_1110_b );--i=142, 2 73 + combo3_1001_0000 <= not( combo2_1001_xxxx_b );--i=144, 2 74 + combo3_1001_0001 <= not( combo2_1001_xxxx_b and combo2_xxxx_0001_b );--i=145, 1 75 + combo3_1001_0010 <= not( combo2_1001_xxxx_b and combo2_xxxx_0010_b );--i=146, 2 76 + combo3_1001_0100 <= not( combo2_1001_xxxx_b and combo2_xxxx_0100_b );--i=148, 1 77 + combo3_1001_0110 <= not( combo2_1001_xxxx_b and combo2_xxxx_0110_b );--i=150, 1 78 + combo3_1001_0111 <= not( combo2_1001_xxxx_b and combo2_xxxx_0111_b );--i=151, 1 79 + combo3_1001_1000 <= not( combo2_1001_xxxx_b and combo2_xxxx_1000_b );--i=152, 1 80 + combo3_1001_1001 <= not( not combo2_1001 );--i=153, 2 81* + combo3_1001_1010 <= not( combo2_1001_xxxx_b and combo2_xxxx_1010_b );--i=154, 1 82 + combo3_1001_1011 <= not( combo2_1001_xxxx_b and combo2_xxxx_1011_b );--i=155, 2 83 + combo3_1001_1100 <= not( combo2_1001_xxxx_b and combo2_xxxx_1100_b );--i=156, 1 84 + combo3_1010_0000 <= not( combo2_1010_xxxx_b );--i=160, 1 85 + combo3_1010_0001 <= not( combo2_1010_xxxx_b and combo2_xxxx_0001_b );--i=161, 1 86 + combo3_1010_0010 <= not( combo2_1010_xxxx_b and combo2_xxxx_0010_b );--i=162, 1 87 + combo3_1010_0100 <= not( combo2_1010_xxxx_b and combo2_xxxx_0100_b );--i=164, 1 88 + combo3_1010_0101 <= not( combo2_1010_xxxx_b and combo2_xxxx_0101_b );--i=165, 2 89 + combo3_1010_0110 <= not( combo2_1010_xxxx_b and combo2_xxxx_0110_b );--i=166, 1 90 + combo3_1010_0111 <= not( combo2_1010_xxxx_b and combo2_xxxx_0111_b );--i=167, 1 91 + combo3_1010_1001 <= not( combo2_1010_xxxx_b and combo2_xxxx_1001_b );--i=169, 2 92 + combo3_1010_1010 <= not( not combo2_1010 );--i=170, 2 93* + combo3_1010_1100 <= not( combo2_1010_xxxx_b and combo2_xxxx_1100_b );--i=172, 2 94 + combo3_1010_1101 <= not( combo2_1010_xxxx_b and combo2_xxxx_1101_b );--i=173, 1 95 + combo3_1010_1111 <= not( combo2_1010_xxxx_b and not f(4) );--i=175, 1 96 + combo3_1011_0001 <= not( combo2_1011_xxxx_b and combo2_xxxx_0001_b );--i=177, 1 97 + combo3_1011_0010 <= not( combo2_1011_xxxx_b and combo2_xxxx_0010_b );--i=178, 1 98 + combo3_1011_0100 <= not( combo2_1011_xxxx_b and combo2_xxxx_0100_b );--i=180, 1 99 + combo3_1011_0101 <= not( combo2_1011_xxxx_b and combo2_xxxx_0101_b );--i=181, 1 100 + combo3_1011_1000 <= not( combo2_1011_xxxx_b and combo2_xxxx_1000_b );--i=184, 1 101 + combo3_1011_1010 <= not( combo2_1011_xxxx_b and combo2_xxxx_1010_b );--i=186, 1 102 + combo3_1011_1100 <= not( combo2_1011_xxxx_b and combo2_xxxx_1100_b );--i=188, 1 103 + combo3_1100_0000 <= not( combo2_1100_xxxx_b );--i=192, 4 104 + combo3_1100_0001 <= not( combo2_1100_xxxx_b and combo2_xxxx_0001_b );--i=193, 1 105 + combo3_1100_0011 <= not( combo2_1100_xxxx_b and combo2_xxxx_0011_b );--i=195, 1 106 + combo3_1100_0101 <= not( combo2_1100_xxxx_b and combo2_xxxx_0101_b );--i=197, 1 107 + combo3_1100_0110 <= not( combo2_1100_xxxx_b and combo2_xxxx_0110_b );--i=198, 1 108 + combo3_1100_0111 <= not( combo2_1100_xxxx_b and combo2_xxxx_0111_b );--i=199, 1 109 + combo3_1100_1001 <= not( combo2_1100_xxxx_b and combo2_xxxx_1001_b );--i=201, 1 110 + combo3_1100_1010 <= not( combo2_1100_xxxx_b and combo2_xxxx_1010_b );--i=202, 2 111 + combo3_1100_1011 <= not( combo2_1100_xxxx_b and combo2_xxxx_1011_b );--i=203, 3 112 + combo3_1100_1101 <= not( combo2_1100_xxxx_b and combo2_xxxx_1101_b );--i=205, 1 113 + combo3_1100_1111 <= not( combo2_1100_xxxx_b and not f(4) );--i=207, 1 114 + combo3_1101_0010 <= not( combo2_1101_xxxx_b and combo2_xxxx_0010_b );--i=210, 1 115 + combo3_1101_0011 <= not( combo2_1101_xxxx_b and combo2_xxxx_0011_b );--i=211, 2 116 + combo3_1101_1000 <= not( combo2_1101_xxxx_b and combo2_xxxx_1000_b );--i=216, 1 117 + combo3_1101_1001 <= not( combo2_1101_xxxx_b and combo2_xxxx_1001_b );--i=217, 2 118 + combo3_1101_1010 <= not( combo2_1101_xxxx_b and combo2_xxxx_1010_b );--i=218, 2 119 + combo3_1101_1100 <= not( combo2_1101_xxxx_b and combo2_xxxx_1100_b );--i=220, 1 120 + combo3_1101_1110 <= not( combo2_1101_xxxx_b and combo2_xxxx_1110_b );--i=222, 1 121 + combo3_1101_1111 <= not( combo2_1101_xxxx_b and not f(4) );--i=223, 2 122 + combo3_1110_0000 <= not( combo2_1110_xxxx_b );--i=224, 5 123 + combo3_1110_0001 <= not( combo2_1110_xxxx_b and combo2_xxxx_0001_b );--i=225, 1 124 + combo3_1110_0011 <= not( combo2_1110_xxxx_b and combo2_xxxx_0011_b );--i=227, 2 125 + combo3_1110_0110 <= not( combo2_1110_xxxx_b and combo2_xxxx_0110_b );--i=230, 1 126 + combo3_1110_1000 <= not( combo2_1110_xxxx_b and combo2_xxxx_1000_b );--i=232, 1 127 + combo3_1110_1010 <= not( combo2_1110_xxxx_b and combo2_xxxx_1010_b );--i=234, 1 128 + combo3_1110_1101 <= not( combo2_1110_xxxx_b and combo2_xxxx_1101_b );--i=237, 3 129 + combo3_1111_0000 <= not( f(4) );--i=240, 2 130 + combo3_1111_0001 <= not( f(4) and combo2_xxxx_0001_b );--i=241, 1 131 + combo3_1111_0010 <= not( f(4) and combo2_xxxx_0010_b );--i=242, 2 132 + combo3_1111_1000 <= not( f(4) and combo2_xxxx_1000_b );--i=248, 3 133 + combo3_1111_1001 <= not( f(4) and combo2_xxxx_1001_b );--i=249, 2 134 + combo3_1111_1010 <= not( f(4) and combo2_xxxx_1010_b );--i=250, 2 135 + combo3_1111_1100 <= not( f(4) and combo2_xxxx_1100_b );--i=252, 4 136 + + +--//####################################### +--//## ESTIMATE VECTORs +--//####################################### + + e_00_b(0) <= not( dcd_000 and tidn ); + e_00_b(1) <= not( dcd_001 and tidn ); + e_00_b(2) <= not( dcd_010 and tidn ); + e_00_b(3) <= not( dcd_011 and tidn ); + e_00_b(4) <= not( dcd_100 and tidn ); + e_00_b(5) <= not( dcd_101 and tidn ); + e_00_b(6) <= not( dcd_110 and tidn ); + e_00_b(7) <= not( dcd_111 and tidn ); + + e( 0) <= not( e_00_b(0) and + e_00_b(1) and + e_00_b(2) and + e_00_b(3) and + e_00_b(4) and + e_00_b(5) and + e_00_b(6) and + e_00_b(7) ); + + e_01_b(0) <= not( dcd_000 and tiup ); + e_01_b(1) <= not( dcd_001 and tiup ); + e_01_b(2) <= not( dcd_010 and combo3_1100_0000 ); + e_01_b(3) <= not( dcd_011 and tidn ); + e_01_b(4) <= not( dcd_100 and tidn ); + e_01_b(5) <= not( dcd_101 and tidn ); + e_01_b(6) <= not( dcd_110 and tidn ); + e_01_b(7) <= not( dcd_111 and tidn ); + + e( 1) <= not( e_01_b(0) and + e_01_b(1) and + e_01_b(2) and + e_01_b(3) and + e_01_b(4) and + e_01_b(5) and + e_01_b(6) and + e_01_b(7) ); + + e_02_b(0) <= not( dcd_000 and combo3_1111_0000 ); + e_02_b(1) <= not( dcd_001 and tidn ); + e_02_b(2) <= not( dcd_010 and combo3_0011_1111 ); + e_02_b(3) <= not( dcd_011 and tiup ); + e_02_b(4) <= not( dcd_100 and combo3_1111_1100 ); + e_02_b(5) <= not( dcd_101 and tidn ); + e_02_b(6) <= not( dcd_110 and tidn ); + e_02_b(7) <= not( dcd_111 and tidn ); + + e( 2) <= not( e_02_b(0) and + e_02_b(1) and + e_02_b(2) and + e_02_b(3) and + e_02_b(4) and + e_02_b(5) and + e_02_b(6) and + e_02_b(7) ); + + e_03_b(0) <= not( dcd_000 and combo3_0000_1111 ); + e_03_b(1) <= not( dcd_001 and combo3_1110_0000 ); + e_03_b(2) <= not( dcd_010 and combo3_0011_1111 ); + e_03_b(3) <= not( dcd_011 and combo3_1110_0000 ); + e_03_b(4) <= not( dcd_100 and combo3_0000_0011 ); + e_03_b(5) <= not( dcd_101 and tiup ); + e_03_b(6) <= not( dcd_110 and combo3_1100_0000 ); + e_03_b(7) <= not( dcd_111 and tidn ); + + e( 3) <= not( e_03_b(0) and + e_03_b(1) and + e_03_b(2) and + e_03_b(3) and + e_03_b(4) and + e_03_b(5) and + e_03_b(6) and + e_03_b(7) ); + + e_04_b(0) <= not( dcd_000 and combo3_1000_1110 ); + e_04_b(1) <= not( dcd_001 and combo3_0001_1100 ); + e_04_b(2) <= not( dcd_010 and combo3_0011_1110 ); + e_04_b(3) <= not( dcd_011 and combo3_0001_1111 ); + e_04_b(4) <= not( dcd_100 and combo3_0000_0011 ); + e_04_b(5) <= not( dcd_101 and combo3_1110_0000 ); + e_04_b(6) <= not( dcd_110 and combo3_0011_1111 ); + e_04_b(7) <= not( dcd_111 and combo3_1000_0000 ); + + e( 4) <= not( e_04_b(0) and + e_04_b(1) and + e_04_b(2) and + e_04_b(3) and + e_04_b(4) and + e_04_b(5) and + e_04_b(6) and + e_04_b(7) ); + + e_05_b(0) <= not( dcd_000 and combo3_0110_1101 ); + e_05_b(1) <= not( dcd_001 and combo3_1001_1011 ); + e_05_b(2) <= not( dcd_010 and combo3_0011_0001 ); + e_05_b(3) <= not( dcd_011 and combo3_1001_1100 ); + e_05_b(4) <= not( dcd_100 and combo3_1110_0011 ); + e_05_b(5) <= not( dcd_101 and combo3_0001_1110 ); + e_05_b(6) <= not( dcd_110 and combo3_0011_1000 ); + e_05_b(7) <= not( dcd_111 and combo3_0111_1000 ); + + e( 5) <= not( e_05_b(0) and + e_05_b(1) and + e_05_b(2) and + e_05_b(3) and + e_05_b(4) and + e_05_b(5) and + e_05_b(6) and + e_05_b(7) ); + + e_06_b(0) <= not( dcd_000 and combo3_1100_1011 ); + e_06_b(1) <= not( dcd_001 and combo3_0101_0110 ); + e_06_b(2) <= not( dcd_010 and combo3_1010_1101 ); + e_06_b(3) <= not( dcd_011 and combo3_0101_0010 ); + e_06_b(4) <= not( dcd_100 and combo3_1101_0010 ); + e_06_b(5) <= not( dcd_101 and combo3_1101_1001 ); + e_06_b(6) <= not( dcd_110 and combo3_0011_0110 ); + e_06_b(7) <= not( dcd_111 and combo3_0110_0110 ); + + e( 6) <= not( e_06_b(0) and + e_06_b(1) and + e_06_b(2) and + e_06_b(3) and + e_06_b(4) and + e_06_b(5) and + e_06_b(6) and + e_06_b(7) ); + + e_07_b(0) <= not( dcd_000 and combo3_0101_1001 ); + e_07_b(1) <= not( dcd_001 and combo3_1000_0011 ); + e_07_b(2) <= not( dcd_010 and combo3_1111_1000 ); + e_07_b(3) <= not( dcd_011 and combo3_0011_1001 ); + e_07_b(4) <= not( dcd_100 and combo3_1001_1001 ); + e_07_b(5) <= not( dcd_101 and combo3_1011_0100 ); + e_07_b(6) <= not( dcd_110 and combo3_1010_0101 ); + e_07_b(7) <= not( dcd_111 and combo3_0101_0100 ); + + e( 7) <= not( e_07_b(0) and + e_07_b(1) and + e_07_b(2) and + e_07_b(3) and + e_07_b(4) and + e_07_b(5) and + e_07_b(6) and + e_07_b(7) ); + + e_08_b(0) <= not( dcd_000 and combo3_0001_0101 ); + e_08_b(1) <= not( dcd_001 and combo3_0110_0011 ); + e_08_b(2) <= not( dcd_010 and combo3_1111_1001 ); + e_08_b(3) <= not( dcd_011 and combo3_1101_1010 ); + e_08_b(4) <= not( dcd_100 and combo3_1010_1010 ); + e_08_b(5) <= not( dcd_101 and combo3_1101_1001 ); + e_08_b(6) <= not( dcd_110 and combo3_1000_1110 ); + e_08_b(7) <= not( dcd_111 and combo3_0000_0001 ); + + e( 8) <= not( e_08_b(0) and + e_08_b(1) and + e_08_b(2) and + e_08_b(3) and + e_08_b(4) and + e_08_b(5) and + e_08_b(6) and + e_08_b(7) ); + + e_09_b(0) <= not( dcd_000 and combo3_0011_0000 ); + e_09_b(1) <= not( dcd_001 and combo3_1101_0011 ); + e_09_b(2) <= not( dcd_010 and combo3_1111_1010 ); + e_09_b(3) <= not( dcd_011 and combo3_0110_1100 ); + e_09_b(4) <= not( dcd_100 and combo3_0000_0011 ); + e_09_b(5) <= not( dcd_101 and combo3_1011_0101 ); + e_09_b(6) <= not( dcd_110 and combo3_0100_1001 ); + e_09_b(7) <= not( dcd_111 and combo3_1100_0001 ); + + e( 9) <= not( e_09_b(0) and + e_09_b(1) and + e_09_b(2) and + e_09_b(3) and + e_09_b(4) and + e_09_b(5) and + e_09_b(6) and + e_09_b(7) ); + + e_10_b(0) <= not( dcd_000 and combo3_0110_1111 ); + e_10_b(1) <= not( dcd_001 and combo3_0111_1010 ); + e_10_b(2) <= not( dcd_010 and combo3_0001_1100 ); + e_10_b(3) <= not( dcd_011 and combo3_1100_1011 ); + e_10_b(4) <= not( dcd_100 and combo3_0000_0100 ); + e_10_b(5) <= not( dcd_101 and combo3_1101_1111 ); + e_10_b(6) <= not( dcd_110 and combo3_1110_1101 ); + e_10_b(7) <= not( dcd_111 and combo3_1011_0001 ); + + e(10) <= not( e_10_b(0) and + e_10_b(1) and + e_10_b(2) and + e_10_b(3) and + e_10_b(4) and + e_10_b(5) and + e_10_b(6) and + e_10_b(7) ); + + e_11_b(0) <= not( dcd_000 and combo3_0111_1001 ); + e_11_b(1) <= not( dcd_001 and combo3_1100_1001 ); + e_11_b(2) <= not( dcd_010 and combo3_0010_1000 ); + e_11_b(3) <= not( dcd_011 and combo3_1101_1110 ); + e_11_b(4) <= not( dcd_100 and combo3_1001_1001 ); + e_11_b(5) <= not( dcd_101 and combo3_1001_0000 ); + e_11_b(6) <= not( dcd_110 and combo3_0111_0111 ); + e_11_b(7) <= not( dcd_111 and combo3_0010_1001 ); + + e(11) <= not( e_11_b(0) and + e_11_b(1) and + e_11_b(2) and + e_11_b(3) and + e_11_b(4) and + e_11_b(5) and + e_11_b(6) and + e_11_b(7) ); + + e_12_b(0) <= not( dcd_000 and combo3_0110_0110 ); + e_12_b(1) <= not( dcd_001 and combo3_0111_0111 ); + e_12_b(2) <= not( dcd_010 and combo3_1100_1010 ); + e_12_b(3) <= not( dcd_011 and combo3_1111_0000 ); + e_12_b(4) <= not( dcd_100 and combo3_0110_1101 ); + e_12_b(5) <= not( dcd_101 and combo3_1011_1000 ); + e_12_b(6) <= not( dcd_110 and combo3_1010_0111 ); + e_12_b(7) <= not( dcd_111 and combo3_0100_0101 ); + + e(12) <= not( e_12_b(0) and + e_12_b(1) and + e_12_b(2) and + e_12_b(3) and + e_12_b(4) and + e_12_b(5) and + e_12_b(6) and + e_12_b(7) ); + + e_13_b(0) <= not( dcd_000 and combo3_1010_1001 ); + e_13_b(1) <= not( dcd_001 and combo3_0010_1110 ); + e_13_b(2) <= not( dcd_010 and combo3_1011_1010 ); + e_13_b(3) <= not( dcd_011 and combo3_0100_0010 ); + e_13_b(4) <= not( dcd_100 and combo3_1110_1101 ); + e_13_b(5) <= not( dcd_101 and combo3_1010_1100 ); + e_13_b(6) <= not( dcd_110 and combo3_0010_1111 ); + e_13_b(7) <= not( dcd_111 and combo3_0010_1001 ); + + e(13) <= not( e_13_b(0) and + e_13_b(1) and + e_13_b(2) and + e_13_b(3) and + e_13_b(4) and + e_13_b(5) and + e_13_b(6) and + e_13_b(7) ); + + e_14_b(0) <= not( dcd_000 and combo3_0111_1001 ); + e_14_b(1) <= not( dcd_001 and combo3_0001_1000 ); + e_14_b(2) <= not( dcd_010 and combo3_0100_1100 ); + e_14_b(3) <= not( dcd_011 and combo3_1100_1011 ); + e_14_b(4) <= not( dcd_100 and combo3_1111_0010 ); + e_14_b(5) <= not( dcd_101 and combo3_0101_1111 ); + e_14_b(6) <= not( dcd_110 and combo3_0110_1100 ); + e_14_b(7) <= not( dcd_111 and combo3_0001_0010 ); + + e(14) <= not( e_14_b(0) and + e_14_b(1) and + e_14_b(2) and + e_14_b(3) and + e_14_b(4) and + e_14_b(5) and + e_14_b(6) and + e_14_b(7) ); + + e_15_b(0) <= not( dcd_000 and combo3_1001_0000 ); + e_15_b(1) <= not( dcd_001 and combo3_1001_0010 ); + e_15_b(2) <= not( dcd_010 and combo3_1101_1010 ); + e_15_b(3) <= not( dcd_011 and combo3_1001_0111 ); + e_15_b(4) <= not( dcd_100 and combo3_0101_1111 ); + e_15_b(5) <= not( dcd_101 and combo3_1001_0001 ); + e_15_b(6) <= not( dcd_110 and combo3_0011_0101 ); + e_15_b(7) <= not( dcd_111 and combo3_1100_0101 ); + + e(15) <= not( e_15_b(0) and + e_15_b(1) and + e_15_b(2) and + e_15_b(3) and + e_15_b(4) and + e_15_b(5) and + e_15_b(6) and + e_15_b(7) ); + + e_16_b(0) <= not( dcd_000 and combo3_1010_1111 ); + e_16_b(1) <= not( dcd_001 and combo3_0101_1100 ); + e_16_b(2) <= not( dcd_010 and combo3_0100_0000 ); + e_16_b(3) <= not( dcd_011 and combo3_0001_0001 ); + e_16_b(4) <= not( dcd_100 and combo3_0000_1101 ); + e_16_b(5) <= not( dcd_101 and combo3_1100_1111 ); + e_16_b(6) <= not( dcd_110 and combo3_1010_0100 ); + e_16_b(7) <= not( dcd_111 and combo3_0001_1101 ); + + e(16) <= not( e_16_b(0) and + e_16_b(1) and + e_16_b(2) and + e_16_b(3) and + e_16_b(4) and + e_16_b(5) and + e_16_b(6) and + e_16_b(7) ); + + e_17_b(0) <= not( dcd_000 and combo3_1010_0010 ); + e_17_b(1) <= not( dcd_001 and combo3_1111_0010 ); + e_17_b(2) <= not( dcd_010 and combo3_0101_1001 ); + e_17_b(3) <= not( dcd_011 and combo3_1000_0110 ); + e_17_b(4) <= not( dcd_100 and combo3_1110_0001 ); + e_17_b(5) <= not( dcd_101 and combo3_0010_0011 ); + e_17_b(6) <= not( dcd_110 and combo3_1000_1010 ); + e_17_b(7) <= not( dcd_111 and combo3_1001_0100 ); + + e(17) <= not( e_17_b(0) and + e_17_b(1) and + e_17_b(2) and + e_17_b(3) and + e_17_b(4) and + e_17_b(5) and + e_17_b(6) and + e_17_b(7) ); + + e_18_b(0) <= not( dcd_000 and combo3_1101_1100 ); + e_18_b(1) <= not( dcd_001 and combo3_0010_1101 ); + e_18_b(2) <= not( dcd_010 and combo3_1100_1010 ); + e_18_b(3) <= not( dcd_011 and combo3_1010_0001 ); + e_18_b(4) <= not( dcd_100 and combo3_1000_0000 ); + e_18_b(5) <= not( dcd_101 and combo3_1011_0010 ); + e_18_b(6) <= not( dcd_110 and combo3_1110_1010 ); + e_18_b(7) <= not( dcd_111 and combo3_0010_1000 ); + + e(18) <= not( e_18_b(0) and + e_18_b(1) and + e_18_b(2) and + e_18_b(3) and + e_18_b(4) and + e_18_b(5) and + e_18_b(6) and + e_18_b(7) ); + + e_19_b(0) <= not( dcd_000 and tiup ); + e_19_b(1) <= not( dcd_001 and tiup ); + e_19_b(2) <= not( dcd_010 and tiup ); + e_19_b(3) <= not( dcd_011 and tiup ); + e_19_b(4) <= not( dcd_100 and tiup ); + e_19_b(5) <= not( dcd_101 and tiup ); + e_19_b(6) <= not( dcd_110 and tiup ); + e_19_b(7) <= not( dcd_111 and tiup ); + + e(19) <= not( e_19_b(0) and + e_19_b(1) and + e_19_b(2) and + e_19_b(3) and + e_19_b(4) and + e_19_b(5) and + e_19_b(6) and + e_19_b(7) ); + + + +--//####################################### +--//## RANGE VECTORs +--//####################################### + + r_00_b(0) <= not( dcd_000 and tidn ); + r_00_b(1) <= not( dcd_001 and tidn ); + r_00_b(2) <= not( dcd_010 and tidn ); + r_00_b(3) <= not( dcd_011 and tidn ); + r_00_b(4) <= not( dcd_100 and tidn ); + r_00_b(5) <= not( dcd_101 and tidn ); + r_00_b(6) <= not( dcd_110 and tidn ); + r_00_b(7) <= not( dcd_111 and tidn ); + + r( 0) <= not( r_00_b(0) and + r_00_b(1) and + r_00_b(2) and + r_00_b(3) and + r_00_b(4) and + r_00_b(5) and + r_00_b(6) and + r_00_b(7) ); + + r_01_b(0) <= not( dcd_000 and tiup ); + r_01_b(1) <= not( dcd_001 and tiup ); + r_01_b(2) <= not( dcd_010 and combo3_1000_0000 ); + r_01_b(3) <= not( dcd_011 and tidn ); + r_01_b(4) <= not( dcd_100 and tidn ); + r_01_b(5) <= not( dcd_101 and tidn ); + r_01_b(6) <= not( dcd_110 and tidn ); + r_01_b(7) <= not( dcd_111 and tidn ); + + r( 1) <= not( r_01_b(0) and + r_01_b(1) and + r_01_b(2) and + r_01_b(3) and + r_01_b(4) and + r_01_b(5) and + r_01_b(6) and + r_01_b(7) ); + + r_02_b(0) <= not( dcd_000 and tidn ); + r_02_b(1) <= not( dcd_001 and tidn ); + r_02_b(2) <= not( dcd_010 and combo3_0111_1111 ); + r_02_b(3) <= not( dcd_011 and tiup ); + r_02_b(4) <= not( dcd_100 and tiup ); + r_02_b(5) <= not( dcd_101 and tiup ); + r_02_b(6) <= not( dcd_110 and tiup ); + r_02_b(7) <= not( dcd_111 and tiup ); + + r( 2) <= not( r_02_b(0) and + r_02_b(1) and + r_02_b(2) and + r_02_b(3) and + r_02_b(4) and + r_02_b(5) and + r_02_b(6) and + r_02_b(7) ); + + r_03_b(0) <= not( dcd_000 and combo3_1111_1000 ); + r_03_b(1) <= not( dcd_001 and tidn ); + r_03_b(2) <= not( dcd_010 and combo3_0111_1111 ); + r_03_b(3) <= not( dcd_011 and tiup ); + r_03_b(4) <= not( dcd_100 and combo3_1100_0000 ); + r_03_b(5) <= not( dcd_101 and tidn ); + r_03_b(6) <= not( dcd_110 and tidn ); + r_03_b(7) <= not( dcd_111 and tidn ); + + r( 3) <= not( r_03_b(0) and + r_03_b(1) and + r_03_b(2) and + r_03_b(3) and + r_03_b(4) and + r_03_b(5) and + r_03_b(6) and + r_03_b(7) ); + + r_04_b(0) <= not( dcd_000 and combo3_1000_0111 ); + r_04_b(1) <= not( dcd_001 and combo3_1110_0000 ); + r_04_b(2) <= not( dcd_010 and combo3_0111_1111 ); + r_04_b(3) <= not( dcd_011 and tidn ); + r_04_b(4) <= not( dcd_100 and combo3_0011_1111 ); + r_04_b(5) <= not( dcd_101 and combo3_1111_1100 ); + r_04_b(6) <= not( dcd_110 and tidn ); + r_04_b(7) <= not( dcd_111 and tidn ); + + r( 4) <= not( r_04_b(0) and + r_04_b(1) and + r_04_b(2) and + r_04_b(3) and + r_04_b(4) and + r_04_b(5) and + r_04_b(6) and + r_04_b(7) ); + + r_05_b(0) <= not( dcd_000 and combo3_0110_0111 ); + r_05_b(1) <= not( dcd_001 and combo3_0001_1000 ); + r_05_b(2) <= not( dcd_010 and combo3_0111_0000 ); + r_05_b(3) <= not( dcd_011 and combo3_1111_1000 ); + r_05_b(4) <= not( dcd_100 and combo3_0011_1111 ); + r_05_b(5) <= not( dcd_101 and combo3_0000_0011 ); + r_05_b(6) <= not( dcd_110 and combo3_1111_1100 ); + r_05_b(7) <= not( dcd_111 and tidn ); + + r( 5) <= not( r_05_b(0) and + r_05_b(1) and + r_05_b(2) and + r_05_b(3) and + r_05_b(4) and + r_05_b(5) and + r_05_b(6) and + r_05_b(7) ); + + r_06_b(0) <= not( dcd_000 and combo3_0101_0110 ); + r_06_b(1) <= not( dcd_001 and combo3_1001_0110 ); + r_06_b(2) <= not( dcd_010 and combo3_0100_1100 ); + r_06_b(3) <= not( dcd_011 and combo3_1100_0110 ); + r_06_b(4) <= not( dcd_100 and combo3_0011_0000 ); + r_06_b(5) <= not( dcd_101 and combo3_1110_0011 ); + r_06_b(6) <= not( dcd_110 and combo3_1100_0011 ); + r_06_b(7) <= not( dcd_111 and combo3_1110_0000 ); + + r( 6) <= not( r_06_b(0) and + r_06_b(1) and + r_06_b(2) and + r_06_b(3) and + r_06_b(4) and + r_06_b(5) and + r_06_b(6) and + r_06_b(7) ); + + r_07_b(0) <= not( dcd_000 and combo3_1111_1100 ); + r_07_b(1) <= not( dcd_001 and combo3_1100_1101 ); + r_07_b(2) <= not( dcd_010 and combo3_0010_1010 ); + r_07_b(3) <= not( dcd_011 and combo3_1010_0101 ); + r_07_b(4) <= not( dcd_100 and combo3_0010_1100 ); + r_07_b(5) <= not( dcd_101 and combo3_1001_1011 ); + r_07_b(6) <= not( dcd_110 and combo3_0011_0011 ); + r_07_b(7) <= not( dcd_111 and combo3_1001_1000 ); + + r( 7) <= not( r_07_b(0) and + r_07_b(1) and + r_07_b(2) and + r_07_b(3) and + r_07_b(4) and + r_07_b(5) and + r_07_b(6) and + r_07_b(7) ); + + r_08_b(0) <= not( dcd_000 and combo3_0001_1101 ); + r_08_b(1) <= not( dcd_001 and combo3_0101_0110 ); + r_08_b(2) <= not( dcd_010 and combo3_0111_1111 ); + r_08_b(3) <= not( dcd_011 and combo3_1111_0001 ); + r_08_b(4) <= not( dcd_100 and combo3_1001_1010 ); + r_08_b(5) <= not( dcd_101 and combo3_0101_0010 ); + r_08_b(6) <= not( dcd_110 and combo3_1010_1010 ); + r_08_b(7) <= not( dcd_111 and combo3_0101_0110 ); + + r( 8) <= not( r_08_b(0) and + r_08_b(1) and + r_08_b(2) and + r_08_b(3) and + r_08_b(4) and + r_08_b(5) and + r_08_b(6) and + r_08_b(7) ); + + r_09_b(0) <= not( dcd_000 and combo3_1110_0110 ); + r_09_b(1) <= not( dcd_001 and combo3_0000_1101 ); + r_09_b(2) <= not( dcd_010 and combo3_0110_0000 ); + r_09_b(3) <= not( dcd_011 and combo3_0011_0110 ); + r_09_b(4) <= not( dcd_100 and combo3_1010_1100 ); + r_09_b(5) <= not( dcd_101 and combo3_1100_0111 ); + r_09_b(6) <= not( dcd_110 and tiup ); + r_09_b(7) <= not( dcd_111 and combo3_0001_1100 ); + + r( 9) <= not( r_09_b(0) and + r_09_b(1) and + r_09_b(2) and + r_09_b(3) and + r_09_b(4) and + r_09_b(5) and + r_09_b(6) and + r_09_b(7) ); + + r_10_b(0) <= not( dcd_000 and combo3_1110_1101 ); + r_10_b(1) <= not( dcd_001 and combo3_0001_0111 ); + r_10_b(2) <= not( dcd_010 and combo3_1101_1000 ); + r_10_b(3) <= not( dcd_011 and combo3_1101_0011 ); + r_10_b(4) <= not( dcd_100 and combo3_1111_1010 ); + r_10_b(5) <= not( dcd_101 and combo3_1010_0110 ); + r_10_b(6) <= not( dcd_110 and combo3_0000_0111 ); + r_10_b(7) <= not( dcd_111 and combo3_0010_0101 ); + + r(10) <= not( r_10_b(0) and + r_10_b(1) and + r_10_b(2) and + r_10_b(3) and + r_10_b(4) and + r_10_b(5) and + r_10_b(6) and + r_10_b(7) ); + + r_11_b(0) <= not( dcd_000 and combo3_1011_1100 ); + r_11_b(1) <= not( dcd_001 and combo3_1010_0000 ); + r_11_b(2) <= not( dcd_010 and combo3_0111_0111 ); + r_11_b(3) <= not( dcd_011 and combo3_0111_1010 ); + r_11_b(4) <= not( dcd_100 and combo3_0001_1100 ); + r_11_b(5) <= not( dcd_101 and combo3_0001_0101 ); + r_11_b(6) <= not( dcd_110 and combo3_1111_1001 ); + r_11_b(7) <= not( dcd_111 and combo3_0100_1111 ); + + r(11) <= not( r_11_b(0) and + r_11_b(1) and + r_11_b(2) and + r_11_b(3) and + r_11_b(4) and + r_11_b(5) and + r_11_b(6) and + r_11_b(7) ); + + r_12_b(0) <= not( dcd_000 and combo3_0100_1110 ); + r_12_b(1) <= not( dcd_001 and combo3_0100_0100 ); + r_12_b(2) <= not( dcd_010 and combo3_1101_1111 ); + r_12_b(3) <= not( dcd_011 and combo3_1100_0000 ); + r_12_b(4) <= not( dcd_100 and combo3_0000_1010 ); + r_12_b(5) <= not( dcd_101 and combo3_0010_0001 ); + r_12_b(6) <= not( dcd_110 and combo3_0000_1011 ); + r_12_b(7) <= not( dcd_111 and combo3_1110_1000 ); + + r(12) <= not( r_12_b(0) and + r_12_b(1) and + r_12_b(2) and + r_12_b(3) and + r_12_b(4) and + r_12_b(5) and + r_12_b(6) and + r_12_b(7) ); + + r_13_b(0) <= not( dcd_000 and combo3_1010_1001 ); + r_13_b(1) <= not( dcd_001 and combo3_0001_0100 ); + r_13_b(2) <= not( dcd_010 and combo3_0111_0101 ); + r_13_b(3) <= not( dcd_011 and combo3_0000_1001 ); + r_13_b(4) <= not( dcd_100 and combo3_0010_1000 ); + r_13_b(5) <= not( dcd_101 and combo3_0000_0011 ); + r_13_b(6) <= not( dcd_110 and combo3_1001_0010 ); + r_13_b(7) <= not( dcd_111 and combo3_0010_0100 ); + + r(13) <= not( r_13_b(0) and + r_13_b(1) and + r_13_b(2) and + r_13_b(3) and + r_13_b(4) and + r_13_b(5) and + r_13_b(6) and + r_13_b(7) ); + + r_14_b(0) <= not( dcd_000 and tidn ); + r_14_b(1) <= not( dcd_001 and tidn ); + r_14_b(2) <= not( dcd_010 and tidn ); + r_14_b(3) <= not( dcd_011 and tidn ); + r_14_b(4) <= not( dcd_100 and tidn ); + r_14_b(5) <= not( dcd_101 and tidn ); + r_14_b(6) <= not( dcd_110 and tidn ); + r_14_b(7) <= not( dcd_111 and tidn ); + + r(14) <= not( r_14_b(0) and + r_14_b(1) and + r_14_b(2) and + r_14_b(3) and + r_14_b(4) and + r_14_b(5) and + r_14_b(6) and + r_14_b(7) ); + + + + +--//####################################### +--//## RENUMBERING OUTPUTS +--//####################################### + + est(1 to 20) <= e(0 to 19);-- renumbering + rng(6 to 20) <= r(0 to 14);-- renumbering + + +end; -- fuq_tblsqe ARCHITECTURE diff --git a/rel/src/vhdl/work/fuq_tblsqo.vhdl b/rel/src/vhdl/work/fuq_tblsqo.vhdl new file mode 100644 index 0000000..446e6e3 --- /dev/null +++ b/rel/src/vhdl/work/fuq_tblsqo.vhdl @@ -0,0 +1,1234 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; + use ieee.std_logic_1164.all ; +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + +-- 11111111111111000001 011111101000010 0 +-- 11111100000001111101 011110111010000 1 +-- 11111000001010101101 011110001101100 2 +-- 11110100011000111111 011101100010110 3 +-- 11110000101100101001 011100111001100 4 +-- 11101101000101011011 011100010001110 5 +-- 11101001100011001101 011011101011010 6 +-- 11100110000101110001 011011000110010 7 +-- 11100010101100111101 011010100010100 8 +-- 11011111011000101001 011010000000000 9 +-- 11011100001000100111 011001011110100 10 +-- 11011000111100110011 011000111110010 11 +-- 11010101110100111111 011000011111000 12 +-- 11010010110001000101 011000000000110 13 +-- 11001111110000111101 010111100011100 14 +-- 11001100110100100001 010111000111010 15 +-- 11001001111011100101 010110101011110 16 +-- 11000111000110000111 010110010001000 17 +-- 11000100010011111101 010101110111010 18 +-- 11000001100101000011 010101011110010 19 +-- 10111110111001010001 010101000101110 20 +-- 10111100010000100001 010100101110010 21 +-- 10111001101010101101 010100010111010 22 +-- 10110111000111110011 010100000001000 23 +-- 10110100100111101001 010011101011010 24 +-- 10110010001010001101 010011010110010 25 +-- 10101111101111011001 010011000001110 26 +-- 10101101010111001011 010010101110000 27 +-- 10101011000001011001 010010011010100 28 +-- 10101000101110000101 010010000111110 29 +-- 10100110011101000101 010001110101010 30 +-- 10100100001110011011 010001100011100 31 +-- 10100010000001111101 010001010010000 32 +-- 10011111110111101101 010001000001000 33 +-- 10011101101111100011 010000110000100 34 +-- 10011011101001011101 010000100000100 35 +-- 10011001100101011001 010000010000110 36 +-- 10010111100011010011 010000000001010 37 +-- 10010101100011000111 001111110010010 38 +-- 10010011100100110101 001111100011110 39 +-- 10010001101000010101 001111010101100 40 +-- 10001111101101101001 001111000111100 41 +-- 10001101110100101011 001110111010000 42 +-- 10001011111101011011 001110101100110 43 +-- 10001010000111110101 001110011111110 44 +-- 10001000010011110101 001110010011000 45 +-- 10000110100001011101 001110000110100 46 +-- 10000100110000100111 001101111010100 47 +-- 10000011000001010001 001101101110110 48 +-- 10000001010011011011 001101100011000 49 +-- 01111111100111000011 001101010111110 50 +-- 01111101111100000011 001101001100110 51 +-- 01111100010010011101 001101000001110 52 +-- 01111010101010001111 001100110111010 53 +-- 01111001000011010011 001100101100110 54 +-- 01110111011101101101 001100100010100 55 +-- 01110101111001010111 001100011000100 56 +-- 01110100010110010001 001100001110110 57 +-- 01110010110100011001 001100000101010 58 +-- 01110001010011101111 001011111100000 59 +-- 01101111110100001111 001011110010110 60 +-- 01101110010101110111 001011101001110 61 +-- 01101100111000101001 001011100001000 62 +-- 01101011011100100001 001011011000010 63 + + + + +entity fuq_tblsqo is +generic( expand_type : integer := 2 ); -- 0 - ibm tech, 1 - other ); +port( + f :in std_ulogic_vector(1 to 6); + est :out std_ulogic_vector(1 to 20); + rng :out std_ulogic_vector(6 to 20) + +); + + + +end fuq_tblsqo; -- ENTITY + + +architecture fuq_tblsqo of fuq_tblsqo is + + constant tiup :std_ulogic := '1'; + constant tidn :std_ulogic := '0'; + + + signal dcd_00x :std_ulogic; + signal dcd_01x :std_ulogic; + signal dcd_10x :std_ulogic; + signal dcd_11x :std_ulogic; + signal dcd_000 :std_ulogic; + signal dcd_001 :std_ulogic; + signal dcd_010 :std_ulogic; + signal dcd_011 :std_ulogic; + signal dcd_100 :std_ulogic; + signal dcd_101 :std_ulogic; + signal dcd_110 :std_ulogic; + signal dcd_111 :std_ulogic; + signal combo2_1000 :std_ulogic; + signal combo2_0100 :std_ulogic; + signal combo2_1100 :std_ulogic; + signal combo2_0010 :std_ulogic; + signal combo2_1010 :std_ulogic; + signal combo2_0110 :std_ulogic; + signal combo2_1110 :std_ulogic; + signal combo2_0001 :std_ulogic; + signal combo2_1001 :std_ulogic; + signal combo2_0101 :std_ulogic; + signal combo2_1101 :std_ulogic; + signal combo2_0011 :std_ulogic; + signal combo2_1011 :std_ulogic; + signal combo2_0111 :std_ulogic; + signal combo2_1000_xxxx_b :std_ulogic; + signal combo2_0100_xxxx_b :std_ulogic; + signal combo2_1100_xxxx_b :std_ulogic; + signal combo2_0010_xxxx_b :std_ulogic; + signal combo2_1010_xxxx_b :std_ulogic; + signal combo2_0110_xxxx_b :std_ulogic; + signal combo2_1110_xxxx_b :std_ulogic; + signal combo2_0001_xxxx_b :std_ulogic; + signal combo2_1001_xxxx_b :std_ulogic; + signal combo2_0101_xxxx_b :std_ulogic; + signal combo2_1101_xxxx_b :std_ulogic; + signal combo2_0011_xxxx_b :std_ulogic; + signal combo2_1011_xxxx_b :std_ulogic; + signal combo2_0111_xxxx_b :std_ulogic; + signal combo2_xxxx_1000_b :std_ulogic; + signal combo2_xxxx_0100_b :std_ulogic; + signal combo2_xxxx_1100_b :std_ulogic; + signal combo2_xxxx_0010_b :std_ulogic; + signal combo2_xxxx_1010_b :std_ulogic; + signal combo2_xxxx_0110_b :std_ulogic; + signal combo2_xxxx_1110_b :std_ulogic; + signal combo2_xxxx_0001_b :std_ulogic; + signal combo2_xxxx_1001_b :std_ulogic; + signal combo2_xxxx_0101_b :std_ulogic; + signal combo2_xxxx_1101_b :std_ulogic; + signal combo2_xxxx_0011_b :std_ulogic; + signal combo2_xxxx_1011_b :std_ulogic; + signal combo2_xxxx_0111_b :std_ulogic; + signal combo3_0000_0001 :std_ulogic; + signal combo3_0000_0011 :std_ulogic; + signal combo3_0000_0100 :std_ulogic; + signal combo3_0000_1011 :std_ulogic; + signal combo3_0000_1100 :std_ulogic; + signal combo3_0000_1101 :std_ulogic; + signal combo3_0000_1111 :std_ulogic; + signal combo3_0001_0001 :std_ulogic; + signal combo3_0001_0010 :std_ulogic; + signal combo3_0001_0100 :std_ulogic; + signal combo3_0001_0101 :std_ulogic; + signal combo3_0001_0111 :std_ulogic; + signal combo3_0001_1000 :std_ulogic; + signal combo3_0001_1110 :std_ulogic; + signal combo3_0001_1111 :std_ulogic; + signal combo3_0010_0001 :std_ulogic; + signal combo3_0010_0010 :std_ulogic; + signal combo3_0010_0011 :std_ulogic; + signal combo3_0010_0100 :std_ulogic; + signal combo3_0010_0110 :std_ulogic; + signal combo3_0010_1001 :std_ulogic; + signal combo3_0010_1101 :std_ulogic; + signal combo3_0010_1110 :std_ulogic; + signal combo3_0011_0000 :std_ulogic; + signal combo3_0011_0001 :std_ulogic; + signal combo3_0011_0011 :std_ulogic; + signal combo3_0011_0100 :std_ulogic; + signal combo3_0011_0101 :std_ulogic; + signal combo3_0011_1000 :std_ulogic; + signal combo3_0011_1001 :std_ulogic; + signal combo3_0011_1010 :std_ulogic; + signal combo3_0011_1100 :std_ulogic; + signal combo3_0011_1110 :std_ulogic; + signal combo3_0011_1111 :std_ulogic; + signal combo3_0100_0000 :std_ulogic; + signal combo3_0100_0101 :std_ulogic; + signal combo3_0100_0110 :std_ulogic; + signal combo3_0100_1000 :std_ulogic; + signal combo3_0100_1001 :std_ulogic; + signal combo3_0100_1010 :std_ulogic; + signal combo3_0100_1100 :std_ulogic; + signal combo3_0100_1101 :std_ulogic; + signal combo3_0101_0000 :std_ulogic; + signal combo3_0101_0001 :std_ulogic; + signal combo3_0101_0011 :std_ulogic; + signal combo3_0101_0101 :std_ulogic; + signal combo3_0101_0110 :std_ulogic; + signal combo3_0101_1001 :std_ulogic; + signal combo3_0101_1010 :std_ulogic; + signal combo3_0101_1110 :std_ulogic; + signal combo3_0101_1111 :std_ulogic; + signal combo3_0110_0011 :std_ulogic; + signal combo3_0110_0110 :std_ulogic; + signal combo3_0110_0111 :std_ulogic; + signal combo3_0110_1001 :std_ulogic; + signal combo3_0110_1010 :std_ulogic; + signal combo3_0110_1011 :std_ulogic; + signal combo3_0110_1100 :std_ulogic; + signal combo3_0110_1101 :std_ulogic; + signal combo3_0110_1110 :std_ulogic; + signal combo3_0110_1111 :std_ulogic; + signal combo3_0111_0000 :std_ulogic; + signal combo3_0111_0010 :std_ulogic; + signal combo3_0111_0011 :std_ulogic; + signal combo3_0111_0110 :std_ulogic; + signal combo3_0111_1000 :std_ulogic; + signal combo3_0111_1001 :std_ulogic; + signal combo3_0111_1100 :std_ulogic; + signal combo3_0111_1110 :std_ulogic; + signal combo3_0111_1111 :std_ulogic; + signal combo3_1000_0000 :std_ulogic; + signal combo3_1000_0001 :std_ulogic; + signal combo3_1000_0011 :std_ulogic; + signal combo3_1000_0110 :std_ulogic; + signal combo3_1000_1000 :std_ulogic; + signal combo3_1000_1010 :std_ulogic; + signal combo3_1000_1101 :std_ulogic; + signal combo3_1000_1110 :std_ulogic; + signal combo3_1000_1111 :std_ulogic; + signal combo3_1001_0000 :std_ulogic; + signal combo3_1001_0010 :std_ulogic; + signal combo3_1001_0011 :std_ulogic; + signal combo3_1001_0100 :std_ulogic; + signal combo3_1001_0111 :std_ulogic; + signal combo3_1001_1000 :std_ulogic; + signal combo3_1001_1001 :std_ulogic; + signal combo3_1001_1010 :std_ulogic; + signal combo3_1001_1100 :std_ulogic; + signal combo3_1001_1101 :std_ulogic; + signal combo3_1001_1110 :std_ulogic; + signal combo3_1001_1111 :std_ulogic; + signal combo3_1010_0010 :std_ulogic; + signal combo3_1010_0100 :std_ulogic; + signal combo3_1010_0101 :std_ulogic; + signal combo3_1010_0110 :std_ulogic; + signal combo3_1010_0111 :std_ulogic; + signal combo3_1010_1010 :std_ulogic; + signal combo3_1010_1100 :std_ulogic; + signal combo3_1010_1101 :std_ulogic; + signal combo3_1010_1110 :std_ulogic; + signal combo3_1011_0011 :std_ulogic; + signal combo3_1011_0110 :std_ulogic; + signal combo3_1011_0111 :std_ulogic; + signal combo3_1011_1000 :std_ulogic; + signal combo3_1011_1001 :std_ulogic; + signal combo3_1011_1010 :std_ulogic; + signal combo3_1011_1011 :std_ulogic; + signal combo3_1011_1110 :std_ulogic; + signal combo3_1100_0000 :std_ulogic; + signal combo3_1100_0001 :std_ulogic; + signal combo3_1100_0011 :std_ulogic; + signal combo3_1100_0110 :std_ulogic; + signal combo3_1100_0111 :std_ulogic; + signal combo3_1100_1010 :std_ulogic; + signal combo3_1100_1100 :std_ulogic; + signal combo3_1100_1110 :std_ulogic; + signal combo3_1101_0000 :std_ulogic; + signal combo3_1101_0011 :std_ulogic; + signal combo3_1101_0101 :std_ulogic; + signal combo3_1101_1000 :std_ulogic; + signal combo3_1101_1010 :std_ulogic; + signal combo3_1101_1011 :std_ulogic; + signal combo3_1101_1101 :std_ulogic; + signal combo3_1110_0000 :std_ulogic; + signal combo3_1110_0001 :std_ulogic; + signal combo3_1110_0010 :std_ulogic; + signal combo3_1110_0011 :std_ulogic; + signal combo3_1110_0100 :std_ulogic; + signal combo3_1110_0101 :std_ulogic; + signal combo3_1110_0110 :std_ulogic; + signal combo3_1110_1010 :std_ulogic; + signal combo3_1110_1011 :std_ulogic; + signal combo3_1111_0000 :std_ulogic; + signal combo3_1111_0011 :std_ulogic; + signal combo3_1111_0101 :std_ulogic; + signal combo3_1111_1000 :std_ulogic; + signal combo3_1111_1001 :std_ulogic; + signal combo3_1111_1011 :std_ulogic; + signal combo3_1111_1100 :std_ulogic; + signal combo3_1111_1110 :std_ulogic; + signal e_00_b :std_ulogic_vector(0 to 7); + signal e_01_b :std_ulogic_vector(0 to 7); + signal e_02_b :std_ulogic_vector(0 to 7); + signal e_03_b :std_ulogic_vector(0 to 7); + signal e_04_b :std_ulogic_vector(0 to 7); + signal e_05_b :std_ulogic_vector(0 to 7); + signal e_06_b :std_ulogic_vector(0 to 7); + signal e_07_b :std_ulogic_vector(0 to 7); + signal e_08_b :std_ulogic_vector(0 to 7); + signal e_09_b :std_ulogic_vector(0 to 7); + signal e_10_b :std_ulogic_vector(0 to 7); + signal e_11_b :std_ulogic_vector(0 to 7); + signal e_12_b :std_ulogic_vector(0 to 7); + signal e_13_b :std_ulogic_vector(0 to 7); + signal e_14_b :std_ulogic_vector(0 to 7); + signal e_15_b :std_ulogic_vector(0 to 7); + signal e_16_b :std_ulogic_vector(0 to 7); + signal e_17_b :std_ulogic_vector(0 to 7); + signal e_18_b :std_ulogic_vector(0 to 7); + signal e_19_b :std_ulogic_vector(0 to 7); + signal e :std_ulogic_vector(0 to 19); + signal r_00_b :std_ulogic_vector(0 to 7); + signal r_01_b :std_ulogic_vector(0 to 7); + signal r_02_b :std_ulogic_vector(0 to 7); + signal r_03_b :std_ulogic_vector(0 to 7); + signal r_04_b :std_ulogic_vector(0 to 7); + signal r_05_b :std_ulogic_vector(0 to 7); + signal r_06_b :std_ulogic_vector(0 to 7); + signal r_07_b :std_ulogic_vector(0 to 7); + signal r_08_b :std_ulogic_vector(0 to 7); + signal r_09_b :std_ulogic_vector(0 to 7); + signal r_10_b :std_ulogic_vector(0 to 7); + signal r_11_b :std_ulogic_vector(0 to 7); + signal r_12_b :std_ulogic_vector(0 to 7); + signal r_13_b :std_ulogic_vector(0 to 7); + signal r_14_b :std_ulogic_vector(0 to 7); + signal r :std_ulogic_vector(0 to 14); + + + +begin + + + + +--//####################################### +--//## decode the upper 3 index bits +--//####################################### + + dcd_00x <= not f(1) and not f(2) ; + dcd_01x <= not f(1) and f(2) ; + dcd_10x <= f(1) and not f(2) ; + dcd_11x <= f(1) and f(2) ; + + dcd_000 <= not f(3) and dcd_00x ; + dcd_001 <= f(3) and dcd_00x ; + dcd_010 <= not f(3) and dcd_01x ; + dcd_011 <= f(3) and dcd_01x ; + dcd_100 <= not f(3) and dcd_10x ; + dcd_101 <= f(3) and dcd_10x ; + dcd_110 <= not f(3) and dcd_11x ; + dcd_111 <= f(3) and dcd_11x ; + + + + +--//####################################### +--//## combos based on lower 2 index bits +--//####################################### + + combo2_1000 <= not f(5) and not f(6) ;-- [0] + combo2_0100 <= not f(5) and f(6) ;-- [1] + combo2_1100 <= not f(5) ;-- [0,1] + combo2_0010 <= f(5) and not f(6) ;-- [2] + combo2_1010 <= not f(6) ;-- [0,2] + combo2_0110 <= f(5) xor f(6) ;-- [1,2] + combo2_1110 <= not( f(5) and f(6) ) ;-- [0,1,2] + combo2_0001 <= f(5) and f(6) ;-- [3] + combo2_1001 <= not( f(5) xor f(6) ) ;-- [0,3] + combo2_0101 <= f(6) ;-- [1,3] + combo2_1101 <= not( f(5) and not f(6) ) ;-- [1,2,3] + combo2_0011 <= f(5) ;-- [2,3] + combo2_1011 <= not( not f(5) and f(6) ) ;-- [0,2,3] + combo2_0111 <= not( not f(5) and not f(6) ) ;-- [1,2,3] + + +--//####################################### +--//## combos based on lower 3 index bits +--//####################################### + + combo2_1000_xxxx_b <= not( not f(4) and combo2_1000 ); + combo2_0100_xxxx_b <= not( not f(4) and combo2_0100 ); + combo2_1100_xxxx_b <= not( not f(4) and combo2_1100 ); + combo2_0010_xxxx_b <= not( not f(4) and combo2_0010 ); + combo2_1010_xxxx_b <= not( not f(4) and combo2_1010 ); + combo2_0110_xxxx_b <= not( not f(4) and combo2_0110 ); + combo2_1110_xxxx_b <= not( not f(4) and combo2_1110 ); + combo2_0001_xxxx_b <= not( not f(4) and combo2_0001 ); + combo2_1001_xxxx_b <= not( not f(4) and combo2_1001 ); + combo2_0101_xxxx_b <= not( not f(4) and combo2_0101 ); + combo2_1101_xxxx_b <= not( not f(4) and combo2_1101 ); + combo2_0011_xxxx_b <= not( not f(4) and combo2_0011 ); + combo2_1011_xxxx_b <= not( not f(4) and combo2_1011 ); + combo2_0111_xxxx_b <= not( not f(4) and combo2_0111 ); + + + combo2_xxxx_1000_b <= not( f(4) and combo2_1000 ); + combo2_xxxx_0100_b <= not( f(4) and combo2_0100 ); + combo2_xxxx_1100_b <= not( f(4) and combo2_1100 ); + combo2_xxxx_0010_b <= not( f(4) and combo2_0010 ); + combo2_xxxx_1010_b <= not( f(4) and combo2_1010 ); + combo2_xxxx_0110_b <= not( f(4) and combo2_0110 ); + combo2_xxxx_1110_b <= not( f(4) and combo2_1110 ); + combo2_xxxx_0001_b <= not( f(4) and combo2_0001 ); + combo2_xxxx_1001_b <= not( f(4) and combo2_1001 ); + combo2_xxxx_0101_b <= not( f(4) and combo2_0101 ); + combo2_xxxx_1101_b <= not( f(4) and combo2_1101 ); + combo2_xxxx_0011_b <= not( f(4) and combo2_0011 ); + combo2_xxxx_1011_b <= not( f(4) and combo2_1011 ); + combo2_xxxx_0111_b <= not( f(4) and combo2_0111 ); + + + combo3_0000_0001 <= not( combo2_xxxx_0001_b );--i=1, 1 1 + combo3_0000_0011 <= not( combo2_xxxx_0011_b );--i=3, 4 2 + combo3_0000_0100 <= not( combo2_xxxx_0100_b );--i=4, 1 3 + combo3_0000_1011 <= not( combo2_xxxx_1011_b );--i=11, 1 4 + combo3_0000_1100 <= not( combo2_xxxx_1100_b );--i=12, 1 5 + combo3_0000_1101 <= not( combo2_xxxx_1101_b );--i=13, 1 6 + combo3_0000_1111 <= not( not f(4) );--i=15, 4 7 + combo3_0001_0001 <= not( not combo2_0001 );--i=17, 1 8* + combo3_0001_0010 <= not( combo2_0001_xxxx_b and combo2_xxxx_0010_b );--i=18, 1 9 + combo3_0001_0100 <= not( combo2_0001_xxxx_b and combo2_xxxx_0100_b );--i=20, 1 10 + combo3_0001_0101 <= not( combo2_0001_xxxx_b and combo2_xxxx_0101_b );--i=21, 2 11 + combo3_0001_0111 <= not( combo2_0001_xxxx_b and combo2_xxxx_0111_b );--i=23, 1 12 + combo3_0001_1000 <= not( combo2_0001_xxxx_b and combo2_xxxx_1000_b );--i=24, 1 13 + combo3_0001_1110 <= not( combo2_0001_xxxx_b and combo2_xxxx_1110_b );--i=30, 1 14 + combo3_0001_1111 <= not( combo2_0001_xxxx_b and not f(4) );--i=31, 2 15 + combo3_0010_0001 <= not( combo2_0010_xxxx_b and combo2_xxxx_0001_b );--i=33, 1 16 + combo3_0010_0010 <= not( not combo2_0010 );--i=34, 1 17* + combo3_0010_0011 <= not( combo2_0010_xxxx_b and combo2_xxxx_0011_b );--i=35, 1 18 + combo3_0010_0100 <= not( combo2_0010_xxxx_b and combo2_xxxx_0100_b );--i=36, 1 19 + combo3_0010_0110 <= not( combo2_0010_xxxx_b and combo2_xxxx_0110_b );--i=38, 2 20 + combo3_0010_1001 <= not( combo2_0010_xxxx_b and combo2_xxxx_1001_b );--i=41, 2 21 + combo3_0010_1101 <= not( combo2_0010_xxxx_b and combo2_xxxx_1101_b );--i=45, 2 22 + combo3_0010_1110 <= not( combo2_0010_xxxx_b and combo2_xxxx_1110_b );--i=46, 1 23 + combo3_0011_0000 <= not( combo2_0011_xxxx_b );--i=48, 1 24 + combo3_0011_0001 <= not( combo2_0011_xxxx_b and combo2_xxxx_0001_b );--i=49, 3 25 + combo3_0011_0011 <= not( not combo2_0011 );--i=51, 1 26* + combo3_0011_0100 <= not( combo2_0011_xxxx_b and combo2_xxxx_0100_b );--i=52, 1 27 + combo3_0011_0101 <= not( combo2_0011_xxxx_b and combo2_xxxx_0101_b );--i=53, 1 28 + combo3_0011_1000 <= not( combo2_0011_xxxx_b and combo2_xxxx_1000_b );--i=56, 5 29 + combo3_0011_1001 <= not( combo2_0011_xxxx_b and combo2_xxxx_1001_b );--i=57, 4 30 + combo3_0011_1010 <= not( combo2_0011_xxxx_b and combo2_xxxx_1010_b );--i=58, 1 31 + combo3_0011_1100 <= not( combo2_0011_xxxx_b and combo2_xxxx_1100_b );--i=60, 2 32 + combo3_0011_1110 <= not( combo2_0011_xxxx_b and combo2_xxxx_1110_b );--i=62, 2 33 + combo3_0011_1111 <= not( combo2_0011_xxxx_b and not f(4) );--i=63, 3 34 + combo3_0100_0000 <= not( combo2_0100_xxxx_b );--i=64, 1 35 + combo3_0100_0101 <= not( combo2_0100_xxxx_b and combo2_xxxx_0101_b );--i=69, 1 36 + combo3_0100_0110 <= not( combo2_0100_xxxx_b and combo2_xxxx_0110_b );--i=70, 1 37 + combo3_0100_1000 <= not( combo2_0100_xxxx_b and combo2_xxxx_1000_b );--i=72, 1 38 + combo3_0100_1001 <= not( combo2_0100_xxxx_b and combo2_xxxx_1001_b );--i=73, 1 39 + combo3_0100_1010 <= not( combo2_0100_xxxx_b and combo2_xxxx_1010_b );--i=74, 2 40 + combo3_0100_1100 <= not( combo2_0100_xxxx_b and combo2_xxxx_1100_b );--i=76, 1 41 + combo3_0100_1101 <= not( combo2_0100_xxxx_b and combo2_xxxx_1101_b );--i=77, 1 42 + combo3_0101_0000 <= not( combo2_0101_xxxx_b );--i=80, 1 43 + combo3_0101_0001 <= not( combo2_0101_xxxx_b and combo2_xxxx_0001_b );--i=81, 2 44 + combo3_0101_0011 <= not( combo2_0101_xxxx_b and combo2_xxxx_0011_b );--i=83, 1 45 + combo3_0101_0101 <= not( not combo2_0101 );--i=85, 1 46* + combo3_0101_0110 <= not( combo2_0101_xxxx_b and combo2_xxxx_0110_b );--i=86, 1 47 + combo3_0101_1001 <= not( combo2_0101_xxxx_b and combo2_xxxx_1001_b );--i=89, 1 48 + combo3_0101_1010 <= not( combo2_0101_xxxx_b and combo2_xxxx_1010_b );--i=90, 1 49 + combo3_0101_1110 <= not( combo2_0101_xxxx_b and combo2_xxxx_1110_b );--i=94, 1 50 + combo3_0101_1111 <= not( combo2_0101_xxxx_b and not f(4) );--i=95, 1 51 + combo3_0110_0011 <= not( combo2_0110_xxxx_b and combo2_xxxx_0011_b );--i=99, 1 52 + combo3_0110_0110 <= not( not combo2_0110 );--i=102, 2 53* + combo3_0110_0111 <= not( combo2_0110_xxxx_b and combo2_xxxx_0111_b );--i=103, 1 54 + combo3_0110_1001 <= not( combo2_0110_xxxx_b and combo2_xxxx_1001_b );--i=105, 1 55 + combo3_0110_1010 <= not( combo2_0110_xxxx_b and combo2_xxxx_1010_b );--i=106, 1 56 + combo3_0110_1011 <= not( combo2_0110_xxxx_b and combo2_xxxx_1011_b );--i=107, 1 57 + combo3_0110_1100 <= not( combo2_0110_xxxx_b and combo2_xxxx_1100_b );--i=108, 1 58 + combo3_0110_1101 <= not( combo2_0110_xxxx_b and combo2_xxxx_1101_b );--i=109, 4 59 + combo3_0110_1110 <= not( combo2_0110_xxxx_b and combo2_xxxx_1110_b );--i=110, 1 60 + combo3_0110_1111 <= not( combo2_0110_xxxx_b and not f(4) );--i=111, 1 61 + combo3_0111_0000 <= not( combo2_0111_xxxx_b );--i=112, 1 62 + combo3_0111_0010 <= not( combo2_0111_xxxx_b and combo2_xxxx_0010_b );--i=114, 3 63 + combo3_0111_0011 <= not( combo2_0111_xxxx_b and combo2_xxxx_0011_b );--i=115, 1 64 + combo3_0111_0110 <= not( combo2_0111_xxxx_b and combo2_xxxx_0110_b );--i=118, 1 65 + combo3_0111_1000 <= not( combo2_0111_xxxx_b and combo2_xxxx_1000_b );--i=120, 2 66 + combo3_0111_1001 <= not( combo2_0111_xxxx_b and combo2_xxxx_1001_b );--i=121, 1 67 + combo3_0111_1100 <= not( combo2_0111_xxxx_b and combo2_xxxx_1100_b );--i=124, 2 68 + combo3_0111_1110 <= not( combo2_0111_xxxx_b and combo2_xxxx_1110_b );--i=126, 1 69 + combo3_0111_1111 <= not( combo2_0111_xxxx_b and not f(4) );--i=127, 3 70 + combo3_1000_0000 <= not( combo2_1000_xxxx_b );--i=128, 4 71 + combo3_1000_0001 <= not( combo2_1000_xxxx_b and combo2_xxxx_0001_b );--i=129, 1 72 + combo3_1000_0011 <= not( combo2_1000_xxxx_b and combo2_xxxx_0011_b );--i=131, 2 73 + combo3_1000_0110 <= not( combo2_1000_xxxx_b and combo2_xxxx_0110_b );--i=134, 1 74 + combo3_1000_1000 <= not( not combo2_1000 );--i=136, 1 75* + combo3_1000_1010 <= not( combo2_1000_xxxx_b and combo2_xxxx_1010_b );--i=138, 2 76 + combo3_1000_1101 <= not( combo2_1000_xxxx_b and combo2_xxxx_1101_b );--i=141, 1 77 + combo3_1000_1110 <= not( combo2_1000_xxxx_b and combo2_xxxx_1110_b );--i=142, 1 78 + combo3_1000_1111 <= not( combo2_1000_xxxx_b and not f(4) );--i=143, 1 79 + combo3_1001_0000 <= not( combo2_1001_xxxx_b );--i=144, 1 80 + combo3_1001_0010 <= not( combo2_1001_xxxx_b and combo2_xxxx_0010_b );--i=146, 2 81 + combo3_1001_0011 <= not( combo2_1001_xxxx_b and combo2_xxxx_0011_b );--i=147, 2 82 + combo3_1001_0100 <= not( combo2_1001_xxxx_b and combo2_xxxx_0100_b );--i=148, 2 83 + combo3_1001_0111 <= not( combo2_1001_xxxx_b and combo2_xxxx_0111_b );--i=151, 1 84 + combo3_1001_1000 <= not( combo2_1001_xxxx_b and combo2_xxxx_1000_b );--i=152, 1 85 + combo3_1001_1001 <= not( not combo2_1001 );--i=153, 3 86* + combo3_1001_1010 <= not( combo2_1001_xxxx_b and combo2_xxxx_1010_b );--i=154, 2 87 + combo3_1001_1100 <= not( combo2_1001_xxxx_b and combo2_xxxx_1100_b );--i=156, 2 88 + combo3_1001_1101 <= not( combo2_1001_xxxx_b and combo2_xxxx_1101_b );--i=157, 1 89 + combo3_1001_1110 <= not( combo2_1001_xxxx_b and combo2_xxxx_1110_b );--i=158, 1 90 + combo3_1001_1111 <= not( combo2_1001_xxxx_b and not f(4) );--i=159, 1 91 + combo3_1010_0010 <= not( combo2_1010_xxxx_b and combo2_xxxx_0010_b );--i=162, 1 92 + combo3_1010_0100 <= not( combo2_1010_xxxx_b and combo2_xxxx_0100_b );--i=164, 2 93 + combo3_1010_0101 <= not( combo2_1010_xxxx_b and combo2_xxxx_0101_b );--i=165, 1 94 + combo3_1010_0110 <= not( combo2_1010_xxxx_b and combo2_xxxx_0110_b );--i=166, 1 95 + combo3_1010_0111 <= not( combo2_1010_xxxx_b and combo2_xxxx_0111_b );--i=167, 2 96 + combo3_1010_1010 <= not( not combo2_1010 );--i=170, 2 97* + combo3_1010_1100 <= not( combo2_1010_xxxx_b and combo2_xxxx_1100_b );--i=172, 1 98 + combo3_1010_1101 <= not( combo2_1010_xxxx_b and combo2_xxxx_1101_b );--i=173, 1 99 + combo3_1010_1110 <= not( combo2_1010_xxxx_b and combo2_xxxx_1110_b );--i=174, 1 100 + combo3_1011_0011 <= not( combo2_1011_xxxx_b and combo2_xxxx_0011_b );--i=179, 1 101 + combo3_1011_0110 <= not( combo2_1011_xxxx_b and combo2_xxxx_0110_b );--i=182, 2 102 + combo3_1011_0111 <= not( combo2_1011_xxxx_b and combo2_xxxx_0111_b );--i=183, 1 103 + combo3_1011_1000 <= not( combo2_1011_xxxx_b and combo2_xxxx_1000_b );--i=184, 1 104 + combo3_1011_1001 <= not( combo2_1011_xxxx_b and combo2_xxxx_1001_b );--i=185, 1 105 + combo3_1011_1010 <= not( combo2_1011_xxxx_b and combo2_xxxx_1010_b );--i=186, 1 106 + combo3_1011_1011 <= not( not combo2_1011 );--i=187, 2 107* + combo3_1011_1110 <= not( combo2_1011_xxxx_b and combo2_xxxx_1110_b );--i=190, 2 108 + combo3_1100_0000 <= not( combo2_1100_xxxx_b );--i=192, 3 109 + combo3_1100_0001 <= not( combo2_1100_xxxx_b and combo2_xxxx_0001_b );--i=193, 1 110 + combo3_1100_0011 <= not( combo2_1100_xxxx_b and combo2_xxxx_0011_b );--i=195, 2 111 + combo3_1100_0110 <= not( combo2_1100_xxxx_b and combo2_xxxx_0110_b );--i=198, 1 112 + combo3_1100_0111 <= not( combo2_1100_xxxx_b and combo2_xxxx_0111_b );--i=199, 2 113 + combo3_1100_1010 <= not( combo2_1100_xxxx_b and combo2_xxxx_1010_b );--i=202, 2 114 + combo3_1100_1100 <= not( not combo2_1100 );--i=204, 2 115* + combo3_1100_1110 <= not( combo2_1100_xxxx_b and combo2_xxxx_1110_b );--i=206, 1 116 + combo3_1101_0000 <= not( combo2_1101_xxxx_b );--i=208, 1 117 + combo3_1101_0011 <= not( combo2_1101_xxxx_b and combo2_xxxx_0011_b );--i=211, 2 118 + combo3_1101_0101 <= not( combo2_1101_xxxx_b and combo2_xxxx_0101_b );--i=213, 3 119 + combo3_1101_1000 <= not( combo2_1101_xxxx_b and combo2_xxxx_1000_b );--i=216, 1 120 + combo3_1101_1010 <= not( combo2_1101_xxxx_b and combo2_xxxx_1010_b );--i=218, 2 121 + combo3_1101_1011 <= not( combo2_1101_xxxx_b and combo2_xxxx_1011_b );--i=219, 1 122 + combo3_1101_1101 <= not( not combo2_1101 );--i=221, 1 123* + combo3_1110_0000 <= not( combo2_1110_xxxx_b );--i=224, 1 124 + combo3_1110_0001 <= not( combo2_1110_xxxx_b and combo2_xxxx_0001_b );--i=225, 1 125 + combo3_1110_0010 <= not( combo2_1110_xxxx_b and combo2_xxxx_0010_b );--i=226, 1 126 + combo3_1110_0011 <= not( combo2_1110_xxxx_b and combo2_xxxx_0011_b );--i=227, 4 127 + combo3_1110_0100 <= not( combo2_1110_xxxx_b and combo2_xxxx_0100_b );--i=228, 1 128 + combo3_1110_0101 <= not( combo2_1110_xxxx_b and combo2_xxxx_0101_b );--i=229, 1 129 + combo3_1110_0110 <= not( combo2_1110_xxxx_b and combo2_xxxx_0110_b );--i=230, 2 130 + combo3_1110_1010 <= not( combo2_1110_xxxx_b and combo2_xxxx_1010_b );--i=234, 1 131 + combo3_1110_1011 <= not( combo2_1110_xxxx_b and combo2_xxxx_1011_b );--i=235, 1 132 + combo3_1111_0000 <= not( f(4) );--i=240, 4 133 + combo3_1111_0011 <= not( f(4) and combo2_xxxx_0011_b );--i=243, 2 134 + combo3_1111_0101 <= not( f(4) and combo2_xxxx_0101_b );--i=245, 1 135 + combo3_1111_1000 <= not( f(4) and combo2_xxxx_1000_b );--i=248, 2 136 + combo3_1111_1001 <= not( f(4) and combo2_xxxx_1001_b );--i=249, 1 137 + combo3_1111_1011 <= not( f(4) and combo2_xxxx_1011_b );--i=251, 1 138 + combo3_1111_1100 <= not( f(4) and combo2_xxxx_1100_b );--i=252, 4 139 + combo3_1111_1110 <= not( f(4) and combo2_xxxx_1110_b );--i=254, 2 140 + + +--//####################################### +--//## ESTIMATE VECTORs +--//####################################### + + e_00_b(0) <= not( dcd_000 and tiup ); + e_00_b(1) <= not( dcd_001 and tiup ); + e_00_b(2) <= not( dcd_010 and tiup ); + e_00_b(3) <= not( dcd_011 and tiup ); + e_00_b(4) <= not( dcd_100 and tiup ); + e_00_b(5) <= not( dcd_101 and tiup ); + e_00_b(6) <= not( dcd_110 and combo3_1100_0000 ); + e_00_b(7) <= not( dcd_111 and tidn ); + + e( 0) <= not( e_00_b(0) and + e_00_b(1) and + e_00_b(2) and + e_00_b(3) and + e_00_b(4) and + e_00_b(5) and + e_00_b(6) and + e_00_b(7) ); + + e_01_b(0) <= not( dcd_000 and tiup ); + e_01_b(1) <= not( dcd_001 and tiup ); + e_01_b(2) <= not( dcd_010 and combo3_1111_0000 ); + e_01_b(3) <= not( dcd_011 and tidn ); + e_01_b(4) <= not( dcd_100 and tidn ); + e_01_b(5) <= not( dcd_101 and tidn ); + e_01_b(6) <= not( dcd_110 and combo3_0011_1111 ); + e_01_b(7) <= not( dcd_111 and tiup ); + + e( 1) <= not( e_01_b(0) and + e_01_b(1) and + e_01_b(2) and + e_01_b(3) and + e_01_b(4) and + e_01_b(5) and + e_01_b(6) and + e_01_b(7) ); + + e_02_b(0) <= not( dcd_000 and tiup ); + e_02_b(1) <= not( dcd_001 and combo3_1000_0000 ); + e_02_b(2) <= not( dcd_010 and combo3_0000_1111 ); + e_02_b(3) <= not( dcd_011 and tiup ); + e_02_b(4) <= not( dcd_100 and combo3_1000_0000 ); + e_02_b(5) <= not( dcd_101 and tidn ); + e_02_b(6) <= not( dcd_110 and combo3_0011_1111 ); + e_02_b(7) <= not( dcd_111 and tiup ); + + e( 2) <= not( e_02_b(0) and + e_02_b(1) and + e_02_b(2) and + e_02_b(3) and + e_02_b(4) and + e_02_b(5) and + e_02_b(6) and + e_02_b(7) ); + + e_03_b(0) <= not( dcd_000 and combo3_1111_1000 ); + e_03_b(1) <= not( dcd_001 and combo3_0111_1100 ); + e_03_b(2) <= not( dcd_010 and combo3_0000_1111 ); + e_03_b(3) <= not( dcd_011 and combo3_1100_0000 ); + e_03_b(4) <= not( dcd_100 and combo3_0111_1111 ); + e_03_b(5) <= not( dcd_101 and combo3_1000_0000 ); + e_03_b(6) <= not( dcd_110 and combo3_0011_1111 ); + e_03_b(7) <= not( dcd_111 and combo3_1111_0000 ); + + e( 3) <= not( e_03_b(0) and + e_03_b(1) and + e_03_b(2) and + e_03_b(3) and + e_03_b(4) and + e_03_b(5) and + e_03_b(6) and + e_03_b(7) ); + + e_04_b(0) <= not( dcd_000 and combo3_1110_0110 ); + e_04_b(1) <= not( dcd_001 and combo3_0111_0011 ); + e_04_b(2) <= not( dcd_010 and combo3_1000_1110 ); + e_04_b(3) <= not( dcd_011 and combo3_0011_1100 ); + e_04_b(4) <= not( dcd_100 and combo3_0111_1000 ); + e_04_b(5) <= not( dcd_101 and combo3_0111_1100 ); + e_04_b(6) <= not( dcd_110 and combo3_0011_1110 ); + e_04_b(7) <= not( dcd_111 and combo3_0000_1111 ); + + e( 4) <= not( e_04_b(0) and + e_04_b(1) and + e_04_b(2) and + e_04_b(3) and + e_04_b(4) and + e_04_b(5) and + e_04_b(6) and + e_04_b(7) ); + + e_05_b(0) <= not( dcd_000 and combo3_1101_0101 ); + e_05_b(1) <= not( dcd_001 and combo3_0110_1011 ); + e_05_b(2) <= not( dcd_010 and combo3_0110_1101 ); + e_05_b(3) <= not( dcd_011 and combo3_1011_0011 ); + e_05_b(4) <= not( dcd_100 and combo3_0110_0110 ); + e_05_b(5) <= not( dcd_101 and combo3_0110_0011 ); + e_05_b(6) <= not( dcd_110 and combo3_0011_1001 ); + e_05_b(7) <= not( dcd_111 and combo3_1100_1110 ); + + e( 5) <= not( e_05_b(0) and + e_05_b(1) and + e_05_b(2) and + e_05_b(3) and + e_05_b(4) and + e_05_b(5) and + e_05_b(6) and + e_05_b(7) ); + + e_06_b(0) <= not( dcd_000 and combo3_1000_0001 ); + e_06_b(1) <= not( dcd_001 and combo3_1100_0110 ); + e_06_b(2) <= not( dcd_010 and combo3_0100_1001 ); + e_06_b(3) <= not( dcd_011 and combo3_0110_1010 ); + e_06_b(4) <= not( dcd_100 and combo3_1101_0101 ); + e_06_b(5) <= not( dcd_101 and combo3_0101_1010 ); + e_06_b(6) <= not( dcd_110 and combo3_1010_0101 ); + e_06_b(7) <= not( dcd_111 and combo3_0010_1101 ); + + e( 6) <= not( e_06_b(0) and + e_06_b(1) and + e_06_b(2) and + e_06_b(3) and + e_06_b(4) and + e_06_b(5) and + e_06_b(6) and + e_06_b(7) ); + + e_07_b(0) <= not( dcd_000 and combo3_1000_0110 ); + e_07_b(1) <= not( dcd_001 and combo3_0100_1010 ); + e_07_b(2) <= not( dcd_010 and combo3_1101_0011 ); + e_07_b(3) <= not( dcd_011 and combo3_0011_1000 ); + e_07_b(4) <= not( dcd_100 and combo3_0111_1111 ); + e_07_b(5) <= not( dcd_101 and combo3_1111_0000 ); + e_07_b(6) <= not( dcd_110 and combo3_1111_0011 ); + e_07_b(7) <= not( dcd_111 and combo3_1001_1001 ); + + e( 7) <= not( e_07_b(0) and + e_07_b(1) and + e_07_b(2) and + e_07_b(3) and + e_07_b(4) and + e_07_b(5) and + e_07_b(6) and + e_07_b(7) ); + + e_08_b(0) <= not( dcd_000 and combo3_1000_1010 ); + e_08_b(1) <= not( dcd_001 and combo3_1001_1111 ); + e_08_b(2) <= not( dcd_010 and combo3_1001_1010 ); + e_08_b(3) <= not( dcd_011 and combo3_1010_0100 ); + e_08_b(4) <= not( dcd_100 and combo3_0111_1111 ); + e_08_b(5) <= not( dcd_101 and combo3_1111_0011 ); + e_08_b(6) <= not( dcd_110 and combo3_0011_0100 ); + e_08_b(7) <= not( dcd_111 and combo3_1010_1010 ); + + e( 8) <= not( e_08_b(0) and + e_08_b(1) and + e_08_b(2) and + e_08_b(3) and + e_08_b(4) and + e_08_b(5) and + e_08_b(6) and + e_08_b(7) ); + + e_09_b(0) <= not( dcd_000 and combo3_1001_0000 ); + e_09_b(1) <= not( dcd_001 and combo3_0101_1111 ); + e_09_b(2) <= not( dcd_010 and combo3_1010_1100 ); + e_09_b(3) <= not( dcd_011 and combo3_0001_0010 ); + e_09_b(4) <= not( dcd_100 and combo3_0100_0000 ); + e_09_b(5) <= not( dcd_101 and combo3_0011_0101 ); + e_09_b(6) <= not( dcd_110 and combo3_0101_1001 ); + e_09_b(7) <= not( dcd_111 and tiup ); + + e( 9) <= not( e_09_b(0) and + e_09_b(1) and + e_09_b(2) and + e_09_b(3) and + e_09_b(4) and + e_09_b(5) and + e_09_b(6) and + e_09_b(7) ); + + e_10_b(0) <= not( dcd_000 and combo3_1011_1000 ); + e_10_b(1) <= not( dcd_001 and combo3_1111_0000 ); + e_10_b(2) <= not( dcd_010 and combo3_1000_1010 ); + e_10_b(3) <= not( dcd_011 and combo3_0110_0111 ); + e_10_b(4) <= not( dcd_100 and combo3_0011_0000 ); + e_10_b(5) <= not( dcd_101 and combo3_1101_0000 ); + e_10_b(6) <= not( dcd_110 and combo3_0001_0101 ); + e_10_b(7) <= not( dcd_111 and combo3_1000_0011 ); + + e(10) <= not( e_10_b(0) and + e_10_b(1) and + e_10_b(2) and + e_10_b(3) and + e_10_b(4) and + e_10_b(5) and + e_10_b(6) and + e_10_b(7) ); + + e_11_b(0) <= not( dcd_000 and combo3_1000_1101 ); + e_11_b(1) <= not( dcd_001 and combo3_1001_1001 ); + e_11_b(2) <= not( dcd_010 and combo3_0101_0001 ); + e_11_b(3) <= not( dcd_011 and combo3_1011_0111 ); + e_11_b(4) <= not( dcd_100 and combo3_0110_1001 ); + e_11_b(5) <= not( dcd_101 and combo3_0111_1000 ); + e_11_b(6) <= not( dcd_110 and combo3_0011_0001 ); + e_11_b(7) <= not( dcd_111 and combo3_0110_1101 ); + + e(11) <= not( e_11_b(0) and + e_11_b(1) and + e_11_b(2) and + e_11_b(3) and + e_11_b(4) and + e_11_b(5) and + e_11_b(6) and + e_11_b(7) ); + + e_12_b(0) <= not( dcd_000 and combo3_1010_0010 ); + e_12_b(1) <= not( dcd_001 and tidn ); + e_12_b(2) <= not( dcd_010 and combo3_1110_0011 ); + e_12_b(3) <= not( dcd_011 and combo3_1111_0101 ); + e_12_b(4) <= not( dcd_100 and combo3_0110_0110 ); + e_12_b(5) <= not( dcd_101 and combo3_0000_1100 ); + e_12_b(6) <= not( dcd_110 and combo3_0110_1110 ); + e_12_b(7) <= not( dcd_111 and combo3_0101_0000 ); + + e(12) <= not( e_12_b(0) and + e_12_b(1) and + e_12_b(2) and + e_12_b(3) and + e_12_b(4) and + e_12_b(5) and + e_12_b(6) and + e_12_b(7) ); + + e_13_b(0) <= not( dcd_000 and combo3_1100_0111 ); + e_13_b(1) <= not( dcd_001 and combo3_0000_0100 ); + e_13_b(2) <= not( dcd_010 and combo3_1011_1001 ); + e_13_b(3) <= not( dcd_011 and combo3_1011_1010 ); + e_13_b(4) <= not( dcd_100 and combo3_1111_1110 ); + e_13_b(5) <= not( dcd_101 and combo3_0101_1110 ); + e_13_b(6) <= not( dcd_110 and combo3_1110_0011 ); + e_13_b(7) <= not( dcd_111 and combo3_1001_0100 ); + + e(13) <= not( e_13_b(0) and + e_13_b(1) and + e_13_b(2) and + e_13_b(3) and + e_13_b(4) and + e_13_b(5) and + e_13_b(6) and + e_13_b(7) ); + + e_14_b(0) <= not( dcd_000 and combo3_0111_1001 ); + e_14_b(1) <= not( dcd_001 and combo3_1111_1011 ); + e_14_b(2) <= not( dcd_010 and combo3_1010_0111 ); + e_14_b(3) <= not( dcd_011 and combo3_1000_0000 ); + e_14_b(4) <= not( dcd_100 and combo3_1110_0001 ); + e_14_b(5) <= not( dcd_101 and combo3_0110_1101 ); + e_14_b(6) <= not( dcd_110 and combo3_0000_0001 ); + e_14_b(7) <= not( dcd_111 and combo3_0001_0111 ); + + e(14) <= not( e_14_b(0) and + e_14_b(1) and + e_14_b(2) and + e_14_b(3) and + e_14_b(4) and + e_14_b(5) and + e_14_b(6) and + e_14_b(7) ); + + e_15_b(0) <= not( dcd_000 and combo3_0101_0101 ); + e_15_b(1) <= not( dcd_001 and combo3_1001_1010 ); + e_15_b(2) <= not( dcd_010 and combo3_0010_1001 ); + e_15_b(3) <= not( dcd_011 and combo3_0010_1001 ); + e_15_b(4) <= not( dcd_100 and combo3_1001_1101 ); + e_15_b(5) <= not( dcd_101 and combo3_1001_1110 ); + e_15_b(6) <= not( dcd_110 and combo3_1100_1010 ); + e_15_b(7) <= not( dcd_111 and combo3_1110_0100 ); + + e(15) <= not( e_15_b(0) and + e_15_b(1) and + e_15_b(2) and + e_15_b(3) and + e_15_b(4) and + e_15_b(5) and + e_15_b(6) and + e_15_b(7) ); + + e_16_b(0) <= not( dcd_000 and combo3_0111_1110 ); + e_16_b(1) <= not( dcd_001 and combo3_1100_1010 ); + e_16_b(2) <= not( dcd_010 and combo3_0010_0010 ); + e_16_b(3) <= not( dcd_011 and combo3_1111_1001 ); + e_16_b(4) <= not( dcd_100 and combo3_1101_1000 ); + e_16_b(5) <= not( dcd_101 and combo3_0111_0010 ); + e_16_b(6) <= not( dcd_110 and combo3_0100_1101 ); + e_16_b(7) <= not( dcd_111 and combo3_0011_1010 ); + + e(16) <= not( e_16_b(0) and + e_16_b(1) and + e_16_b(2) and + e_16_b(3) and + e_16_b(4) and + e_16_b(5) and + e_16_b(6) and + e_16_b(7) ); + + e_17_b(0) <= not( dcd_000 and combo3_0111_0010 ); + e_17_b(1) <= not( dcd_001 and combo3_1010_1110 ); + e_17_b(2) <= not( dcd_010 and combo3_1110_0010 ); + e_17_b(3) <= not( dcd_011 and combo3_0100_0110 ); + e_17_b(4) <= not( dcd_100 and combo3_1101_0011 ); + e_17_b(5) <= not( dcd_101 and combo3_1000_1111 ); + e_17_b(6) <= not( dcd_110 and combo3_0000_1101 ); + e_17_b(7) <= not( dcd_111 and combo3_1001_1100 ); + + e(17) <= not( e_17_b(0) and + e_17_b(1) and + e_17_b(2) and + e_17_b(3) and + e_17_b(4) and + e_17_b(5) and + e_17_b(6) and + e_17_b(7) ); + + e_18_b(0) <= not( dcd_000 and combo3_0001_0100 ); + e_18_b(1) <= not( dcd_001 and combo3_0011_1000 ); + e_18_b(2) <= not( dcd_010 and combo3_0101_0001 ); + e_18_b(3) <= not( dcd_011 and combo3_0001_0001 ); + e_18_b(4) <= not( dcd_100 and combo3_0010_0110 ); + e_18_b(5) <= not( dcd_101 and combo3_0011_0001 ); + e_18_b(6) <= not( dcd_110 and combo3_0111_0110 ); + e_18_b(7) <= not( dcd_111 and combo3_1001_1100 ); + + e(18) <= not( e_18_b(0) and + e_18_b(1) and + e_18_b(2) and + e_18_b(3) and + e_18_b(4) and + e_18_b(5) and + e_18_b(6) and + e_18_b(7) ); + + e_19_b(0) <= not( dcd_000 and tiup ); + e_19_b(1) <= not( dcd_001 and tiup ); + e_19_b(2) <= not( dcd_010 and tiup ); + e_19_b(3) <= not( dcd_011 and tiup ); + e_19_b(4) <= not( dcd_100 and tiup ); + e_19_b(5) <= not( dcd_101 and tiup ); + e_19_b(6) <= not( dcd_110 and tiup ); + e_19_b(7) <= not( dcd_111 and tiup ); + + e(19) <= not( e_19_b(0) and + e_19_b(1) and + e_19_b(2) and + e_19_b(3) and + e_19_b(4) and + e_19_b(5) and + e_19_b(6) and + e_19_b(7) ); + + + +--//####################################### +--//## RANGE VECTORs +--//####################################### + + r_00_b(0) <= not( dcd_000 and tidn ); + r_00_b(1) <= not( dcd_001 and tidn ); + r_00_b(2) <= not( dcd_010 and tidn ); + r_00_b(3) <= not( dcd_011 and tidn ); + r_00_b(4) <= not( dcd_100 and tidn ); + r_00_b(5) <= not( dcd_101 and tidn ); + r_00_b(6) <= not( dcd_110 and tidn ); + r_00_b(7) <= not( dcd_111 and tidn ); + + r( 0) <= not( r_00_b(0) and + r_00_b(1) and + r_00_b(2) and + r_00_b(3) and + r_00_b(4) and + r_00_b(5) and + r_00_b(6) and + r_00_b(7) ); + + r_01_b(0) <= not( dcd_000 and tiup ); + r_01_b(1) <= not( dcd_001 and tiup ); + r_01_b(2) <= not( dcd_010 and tiup ); + r_01_b(3) <= not( dcd_011 and tiup ); + r_01_b(4) <= not( dcd_100 and combo3_1111_1100 ); + r_01_b(5) <= not( dcd_101 and tidn ); + r_01_b(6) <= not( dcd_110 and tidn ); + r_01_b(7) <= not( dcd_111 and tidn ); + + r( 1) <= not( r_01_b(0) and + r_01_b(1) and + r_01_b(2) and + r_01_b(3) and + r_01_b(4) and + r_01_b(5) and + r_01_b(6) and + r_01_b(7) ); + + r_02_b(0) <= not( dcd_000 and tiup ); + r_02_b(1) <= not( dcd_001 and combo3_1111_1100 ); + r_02_b(2) <= not( dcd_010 and tidn ); + r_02_b(3) <= not( dcd_011 and tidn ); + r_02_b(4) <= not( dcd_100 and combo3_0000_0011 ); + r_02_b(5) <= not( dcd_101 and tiup ); + r_02_b(6) <= not( dcd_110 and tiup ); + r_02_b(7) <= not( dcd_111 and tiup ); + + r( 2) <= not( r_02_b(0) and + r_02_b(1) and + r_02_b(2) and + r_02_b(3) and + r_02_b(4) and + r_02_b(5) and + r_02_b(6) and + r_02_b(7) ); + + r_03_b(0) <= not( dcd_000 and combo3_1111_1100 ); + r_03_b(1) <= not( dcd_001 and combo3_0000_0011 ); + r_03_b(2) <= not( dcd_010 and tiup ); + r_03_b(3) <= not( dcd_011 and tidn ); + r_03_b(4) <= not( dcd_100 and combo3_0000_0011 ); + r_03_b(5) <= not( dcd_101 and tiup ); + r_03_b(6) <= not( dcd_110 and tiup ); + r_03_b(7) <= not( dcd_111 and combo3_1110_0000 ); + + r( 3) <= not( r_03_b(0) and + r_03_b(1) and + r_03_b(2) and + r_03_b(3) and + r_03_b(4) and + r_03_b(5) and + r_03_b(6) and + r_03_b(7) ); + + r_04_b(0) <= not( dcd_000 and combo3_1110_0011 ); + r_04_b(1) <= not( dcd_001 and combo3_1100_0011 ); + r_04_b(2) <= not( dcd_010 and combo3_1100_0000 ); + r_04_b(3) <= not( dcd_011 and combo3_1111_1100 ); + r_04_b(4) <= not( dcd_100 and combo3_0000_0011 ); + r_04_b(5) <= not( dcd_101 and combo3_1111_1110 ); + r_04_b(6) <= not( dcd_110 and tidn ); + r_04_b(7) <= not( dcd_111 and combo3_0001_1111 ); + + r( 4) <= not( r_04_b(0) and + r_04_b(1) and + r_04_b(2) and + r_04_b(3) and + r_04_b(4) and + r_04_b(5) and + r_04_b(6) and + r_04_b(7) ); + + r_05_b(0) <= not( dcd_000 and combo3_1001_0011 ); + r_05_b(1) <= not( dcd_001 and combo3_0010_0011 ); + r_05_b(2) <= not( dcd_010 and combo3_0011_1000 ); + r_05_b(3) <= not( dcd_011 and combo3_1110_0011 ); + r_05_b(4) <= not( dcd_100 and combo3_1100_0011 ); + r_05_b(5) <= not( dcd_101 and combo3_1100_0001 ); + r_05_b(6) <= not( dcd_110 and combo3_1111_1000 ); + r_05_b(7) <= not( dcd_111 and combo3_0001_1111 ); + + r( 5) <= not( r_05_b(0) and + r_05_b(1) and + r_05_b(2) and + r_05_b(3) and + r_05_b(4) and + r_05_b(5) and + r_05_b(6) and + r_05_b(7) ); + + r_06_b(0) <= not( dcd_000 and combo3_1101_1010 ); + r_06_b(1) <= not( dcd_001 and combo3_1001_0010 ); + r_06_b(2) <= not( dcd_010 and combo3_1010_0100 ); + r_06_b(3) <= not( dcd_011 and combo3_1001_0011 ); + r_06_b(4) <= not( dcd_100 and combo3_0011_0011 ); + r_06_b(5) <= not( dcd_101 and combo3_0011_0001 ); + r_06_b(6) <= not( dcd_110 and combo3_1100_0111 ); + r_06_b(7) <= not( dcd_111 and combo3_0001_1110 ); + + r( 6) <= not( r_06_b(0) and + r_06_b(1) and + r_06_b(2) and + r_06_b(3) and + r_06_b(4) and + r_06_b(5) and + r_06_b(6) and + r_06_b(7) ); + + r_07_b(0) <= not( dcd_000 and combo3_0100_1100 ); + r_07_b(1) <= not( dcd_001 and combo3_0011_1000 ); + r_07_b(2) <= not( dcd_010 and combo3_0111_0010 ); + r_07_b(3) <= not( dcd_011 and combo3_0100_1010 ); + r_07_b(4) <= not( dcd_100 and combo3_1010_1010 ); + r_07_b(5) <= not( dcd_101 and combo3_1010_1101 ); + r_07_b(6) <= not( dcd_110 and combo3_0010_0100 ); + r_07_b(7) <= not( dcd_111 and combo3_1001_1001 ); + + r( 7) <= not( r_07_b(0) and + r_07_b(1) and + r_07_b(2) and + r_07_b(3) and + r_07_b(4) and + r_07_b(5) and + r_07_b(6) and + r_07_b(7) ); + + r_08_b(0) <= not( dcd_000 and combo3_1110_1010 ); + r_08_b(1) <= not( dcd_001 and combo3_0011_1000 ); + r_08_b(2) <= not( dcd_010 and combo3_1001_0100 ); + r_08_b(3) <= not( dcd_011 and combo3_1001_1000 ); + r_08_b(4) <= not( dcd_100 and tidn ); + r_08_b(5) <= not( dcd_101 and combo3_0011_1001 ); + r_08_b(6) <= not( dcd_110 and combo3_1001_0010 ); + r_08_b(7) <= not( dcd_111 and combo3_1101_0101 ); + + r( 8) <= not( r_08_b(0) and + r_08_b(1) and + r_08_b(2) and + r_08_b(3) and + r_08_b(4) and + r_08_b(5) and + r_08_b(6) and + r_08_b(7) ); + + r_09_b(0) <= not( dcd_000 and combo3_0010_0001 ); + r_09_b(1) <= not( dcd_001 and combo3_0011_1001 ); + r_09_b(2) <= not( dcd_010 and combo3_0011_1110 ); + r_09_b(3) <= not( dcd_011 and combo3_0101_0110 ); + r_09_b(4) <= not( dcd_100 and tidn ); + r_09_b(5) <= not( dcd_101 and combo3_1101_1010 ); + r_09_b(6) <= not( dcd_110 and combo3_1011_0110 ); + r_09_b(7) <= not( dcd_111 and combo3_0111_0000 ); + + r( 9) <= not( r_09_b(0) and + r_09_b(1) and + r_09_b(2) and + r_09_b(3) and + r_09_b(4) and + r_09_b(5) and + r_09_b(6) and + r_09_b(7) ); + + r_10_b(0) <= not( dcd_000 and combo3_0101_0011 ); + r_10_b(1) <= not( dcd_001 and combo3_1011_1011 ); + r_10_b(2) <= not( dcd_010 and combo3_1011_0110 ); + r_10_b(3) <= not( dcd_011 and combo3_1101_1101 ); + r_10_b(4) <= not( dcd_100 and combo3_1000_0011 ); + r_10_b(5) <= not( dcd_101 and combo3_0110_1111 ); + r_10_b(6) <= not( dcd_110 and combo3_1110_0101 ); + r_10_b(7) <= not( dcd_111 and combo3_0100_1000 ); + + r(10) <= not( r_10_b(0) and + r_10_b(1) and + r_10_b(2) and + r_10_b(3) and + r_10_b(4) and + r_10_b(5) and + r_10_b(6) and + r_10_b(7) ); + + r_11_b(0) <= not( dcd_000 and combo3_0010_1110 ); + r_11_b(1) <= not( dcd_001 and combo3_0000_1011 ); + r_11_b(2) <= not( dcd_010 and combo3_1110_1011 ); + r_11_b(3) <= not( dcd_011 and combo3_1010_0111 ); + r_11_b(4) <= not( dcd_100 and combo3_0100_0101 ); + r_11_b(5) <= not( dcd_101 and combo3_1100_1100 ); + r_11_b(6) <= not( dcd_110 and combo3_0110_1100 ); + r_11_b(7) <= not( dcd_111 and combo3_0010_0110 ); + + r(11) <= not( r_11_b(0) and + r_11_b(1) and + r_11_b(2) and + r_11_b(3) and + r_11_b(4) and + r_11_b(5) and + r_11_b(6) and + r_11_b(7) ); + + r_12_b(0) <= not( dcd_000 and combo3_0011_1100 ); + r_12_b(1) <= not( dcd_001 and combo3_1010_0110 ); + r_12_b(2) <= not( dcd_010 and combo3_1000_1000 ); + r_12_b(3) <= not( dcd_011 and combo3_0010_1101 ); + r_12_b(4) <= not( dcd_100 and combo3_0011_1001 ); + r_12_b(5) <= not( dcd_101 and combo3_1101_1011 ); + r_12_b(6) <= not( dcd_110 and combo3_1011_1011 ); + r_12_b(7) <= not( dcd_111 and combo3_1100_1100 ); + + r(12) <= not( r_12_b(0) and + r_12_b(1) and + r_12_b(2) and + r_12_b(3) and + r_12_b(4) and + r_12_b(5) and + r_12_b(6) and + r_12_b(7) ); + + r_13_b(0) <= not( dcd_000 and combo3_1001_0111 ); + r_13_b(1) <= not( dcd_001 and combo3_0001_0101 ); + r_13_b(2) <= not( dcd_010 and combo3_1011_1110 ); + r_13_b(3) <= not( dcd_011 and combo3_1110_0110 ); + r_13_b(4) <= not( dcd_100 and combo3_0000_1111 ); + r_13_b(5) <= not( dcd_101 and combo3_0001_1000 ); + r_13_b(6) <= not( dcd_110 and combo3_1011_1110 ); + r_13_b(7) <= not( dcd_111 and combo3_0110_1101 ); + + r(13) <= not( r_13_b(0) and + r_13_b(1) and + r_13_b(2) and + r_13_b(3) and + r_13_b(4) and + r_13_b(5) and + r_13_b(6) and + r_13_b(7) ); + + r_14_b(0) <= not( dcd_000 and tidn ); + r_14_b(1) <= not( dcd_001 and tidn ); + r_14_b(2) <= not( dcd_010 and tidn ); + r_14_b(3) <= not( dcd_011 and tidn ); + r_14_b(4) <= not( dcd_100 and tidn ); + r_14_b(5) <= not( dcd_101 and tidn ); + r_14_b(6) <= not( dcd_110 and tidn ); + r_14_b(7) <= not( dcd_111 and tidn ); + + r(14) <= not( r_14_b(0) and + r_14_b(1) and + r_14_b(2) and + r_14_b(3) and + r_14_b(4) and + r_14_b(5) and + r_14_b(6) and + r_14_b(7) ); + + + +--//####################################### +--//## RENUMBERING OUTPUTS +--//####################################### + + est(1 to 20) <= e(0 to 19);-- renumbering + rng(6 to 20) <= r(0 to 14);-- renumbering + + +end; -- fuq_tblsqo ARCHITECTURE diff --git a/rel/src/vhdl/work/iuq.vhdl b/rel/src/vhdl/work/iuq.vhdl new file mode 100644 index 0000000..330e830 --- /dev/null +++ b/rel/src/vhdl/work/iuq.vhdl @@ -0,0 +1,1882 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +--******************************************************************** +--* +--* TITLE: Instruction Unit +--* +--* NAME: iuq.vhdl +--* +--********************************************************************* +library ieee; +use ieee.std_logic_1164.all; +library support; +use support.power_logic_pkg.all; +library work; +use work.iuq_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity iuq is + generic(expand_type : integer := 2; + a2mode : integer := 1; + lmq_entries : integer := 8; + fpr_addr_width : integer := 5; + regmode : integer := 6; + threads : integer := 4; + ucode_mode : integer := 1; + bcfg_epn_0to15 : integer := 0; + bcfg_epn_16to31 : integer := 0; + bcfg_epn_32to47 : integer := (2**16)-1; + bcfg_epn_48to51 : integer := (2**4)-1; + bcfg_rpn_22to31 : integer := (2**10)-1; + bcfg_rpn_32to47 : integer := (2**16)-1; + bcfg_rpn_48to51 : integer := (2**4)-1; + uc_ifar : integer := 21); +port( + vcs : inout power_logic; + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + + tc_ac_ccflush_dc : in std_ulogic; + an_ac_scan_dis_dc_b : in std_ulogic; + an_ac_scan_diag_dc : in std_ulogic; + + pc_iu_gptr_sl_thold_4 : in std_ulogic; + pc_iu_time_sl_thold_4 : in std_ulogic; + pc_iu_repr_sl_thold_4 : in std_ulogic; + pc_iu_abst_sl_thold_4 : in std_ulogic; + pc_iu_abst_slp_sl_thold_4 : in std_ulogic; + pc_iu_bolt_sl_thold_4 : in std_ulogic; + pc_iu_regf_slp_sl_thold_4 : in std_ulogic; + pc_iu_func_sl_thold_4 : in std_ulogic; + pc_iu_func_slp_sl_thold_4 : in std_ulogic; + pc_iu_cfg_sl_thold_4 : in std_ulogic; + pc_iu_cfg_slp_sl_thold_4 : in std_ulogic; + pc_iu_func_nsl_thold_4 : in std_ulogic; + pc_iu_func_slp_nsl_thold_4 : in std_ulogic; + pc_iu_ary_nsl_thold_4 : in std_ulogic; + pc_iu_ary_slp_nsl_thold_4 : in std_ulogic; + pc_iu_sg_4 : in std_ulogic; + pc_iu_fce_4 : in std_ulogic; + + pc_iu_abist_dcomp_g6t_2r : in std_ulogic_vector(0 to 3); + pc_iu_abist_di_0 : in std_ulogic_vector(0 to 3); + pc_iu_abist_di_g6t_2r : in std_ulogic_vector(0 to 3); + pc_iu_abist_ena_dc : in std_ulogic; + pc_iu_abist_g6t_bw : in std_ulogic_vector(0 to 1); + pc_iu_abist_g6t_r_wb : in std_ulogic; + pc_iu_abist_g8t1p_renb_0 : in std_ulogic; + pc_iu_abist_g8t_bw_0 : in std_ulogic; + pc_iu_abist_g8t_bw_1 : in std_ulogic; + pc_iu_abist_g8t_dcomp : in std_ulogic_vector(0 to 3); + pc_iu_abist_g8t_wenb : in std_ulogic; + pc_iu_abist_raddr_0 : in std_ulogic_vector(0 to 9); + pc_iu_abist_raw_dc_b : in std_ulogic; + pc_iu_abist_waddr_0 : in std_ulogic_vector(0 to 9); + pc_iu_abist_wl256_comp_ena : in std_ulogic; + pc_iu_abist_wl64_comp_ena : in std_ulogic; + pc_iu_abist_wl128_comp_ena : in std_ulogic; + an_ac_lbist_ary_wrt_thru_dc: in std_ulogic; + an_ac_lbist_en_dc : in std_ulogic; + an_ac_atpg_en_dc : in std_ulogic; + an_ac_grffence_en_dc : in std_ulogic; + + pc_iu_bo_enable_4 : in std_ulogic; + pc_iu_bo_reset : in std_ulogic; + pc_iu_bo_unload : in std_ulogic; + pc_iu_bo_repair : in std_ulogic; + pc_iu_bo_shdata : in std_ulogic; + pc_iu_bo_select : in std_ulogic_vector(0 to 4); + iu_pc_bo_fail : out std_ulogic_vector(0 to 4); + iu_pc_bo_diagout : out std_ulogic_vector(0 to 4); + + + iu_pc_err_icache_parity : out std_ulogic; + iu_pc_err_icachedir_parity : out std_ulogic; + iu_pc_err_icachedir_multihit : out std_ulogic; + + iu_pc_err_ucode_illegal : out std_ulogic_vector(0 to 3); + + pc_iu_inj_icache_parity : in std_ulogic; + pc_iu_inj_icachedir_parity : in std_ulogic; + pc_iu_inj_icachedir_multihit : in std_ulogic; + + pc_iu_trace_bus_enable : in std_ulogic; + pc_iu_debug_mux1_ctrls : in std_ulogic_vector(0 to 15); + pc_iu_debug_mux2_ctrls : in std_ulogic_vector(0 to 15); + debug_data_in : in std_ulogic_vector(0 to 87); + trace_triggers_in : in std_ulogic_vector(0 to 11); + debug_data_out : out std_ulogic_vector(0 to 87); + trace_triggers_out : out std_ulogic_vector(0 to 11); + pc_iu_event_mux_ctrls : in std_ulogic_vector(0 to 47); + pc_iu_event_count_mode : in std_ulogic_vector(0 to 2); + pc_iu_event_bus_enable : in std_ulogic; + iu_pc_event_data : out std_ulogic_vector(0 to 7); + + pc_iu_init_reset : in std_ulogic; + + gptr_scan_in : in std_ulogic; + time_scan_in : in std_ulogic; + repr_scan_in : in std_ulogic; + abst_scan_in : in std_ulogic_vector(0 to 2); + func_scan_in : in std_ulogic_vector(0 to 13); + ccfg_scan_in : in std_ulogic; + bcfg_scan_in : in std_ulogic; + dcfg_scan_in : in std_ulogic; + regf_scan_in : in std_ulogic_vector(0 to 4); + + gptr_scan_out : out std_ulogic; + time_scan_out : out std_ulogic; + repr_scan_out : out std_ulogic; + abst_scan_out : out std_ulogic_vector(0 to 2); + func_scan_out : out std_ulogic_vector(0 to 13); + ccfg_scan_out : out std_ulogic; + bcfg_scan_out : out std_ulogic; + dcfg_scan_out : out std_ulogic; + regf_scan_out : out std_ulogic_vector(0 to 4); + + slowspr_val_in : in std_ulogic; + slowspr_rw_in : in std_ulogic; + slowspr_etid_in : in std_ulogic_vector(0 to 1); + slowspr_addr_in : in std_ulogic_vector(0 to 9); + slowspr_data_in : in std_ulogic_vector(64-(2**regmode) to 63); + slowspr_done_in : in std_ulogic; + + slowspr_val_out : out std_ulogic; + slowspr_rw_out : out std_ulogic; + slowspr_etid_out : out std_ulogic_vector(0 to 1); + slowspr_addr_out : out std_ulogic_vector(0 to 9); + slowspr_data_out : out std_ulogic_vector(64-(2**regmode) to 63); + slowspr_done_out : out std_ulogic; + + xu_iu_run_thread : in std_ulogic_vector(0 to 3); + xu_iu_l_flush : in std_ulogic_vector(0 to 3); + xu_iu_u_flush : in std_ulogic_vector(0 to 3); + xu_iu_iu0_flush_ifar0 : in EFF_IFAR; + xu_iu_iu0_flush_ifar1 : in EFF_IFAR; + xu_iu_iu0_flush_ifar2 : in EFF_IFAR; + xu_iu_iu0_flush_ifar3 : in EFF_IFAR; + xu_iu_flush_2ucode : in std_ulogic_vector(0 to 3); + xu_iu_flush_2ucode_type : in std_ulogic_vector(0 to 3); + xu_iu_membar_tid : in std_ulogic_vector(0 to 3); + xu_iu_set_barr_tid : in std_ulogic_vector(0 to 3); + xu_iu_larx_done_tid : in std_ulogic_vector(0 to 3); + xu_iu_msr_cm : in std_ulogic_vector(0 to threads-1); + xu_iu_ex6_icbi_val : in std_ulogic_vector(0 to threads-1); + xu_iu_ex6_icbi_addr : in std_ulogic_vector(REAL_IFAR'left to 57); + xu_iu_ici : in std_ulogic; + iu_xu_request : out std_ulogic; + iu_xu_thread : out std_ulogic_vector(0 to 3); + iu_xu_ra : out std_ulogic_vector(REAL_IFAR'left to 59); + iu_xu_wimge : out std_ulogic_vector(0 to 4); + iu_xu_userdef : out std_ulogic_vector(0 to 3); + + an_ac_reld_data_vld : in std_ulogic; + an_ac_reld_data_vld_clone : in std_ulogic; + an_ac_reld_ditc_clone : in std_ulogic; + an_ac_reld_data_coming_clone: in std_ulogic; + an_ac_reld_core_tag : in std_ulogic_vector(0 to 4); + an_ac_reld_core_tag_clone : in std_ulogic_vector(1 to 4); + an_ac_reld_qw : in std_ulogic_vector(57 to 59); + an_ac_reld_data : in std_ulogic_vector(0 to 127); + an_ac_reld_ecc_err : in std_ulogic; + an_ac_reld_ecc_err_ue : in std_ulogic; + an_ac_back_inv : in std_ulogic; + an_ac_back_inv_addr : in std_ulogic_vector(REAL_IFAR'left to 63); + an_ac_back_inv_target_iiu_a: in std_ulogic_vector(0 to 1); + an_ac_back_inv_target_iiu_b: in std_ulogic_vector(3 to 4); + an_ac_sync_ack : in std_ulogic_vector(0 to 3); + an_ac_stcx_complete : in std_ulogic_vector(0 to 3); + an_ac_icbi_ack : in std_ulogic; + an_ac_icbi_ack_thread : in std_ulogic_vector(0 to 1); + + iu_mm_ierat_req : out std_ulogic; + iu_mm_ierat_epn : out std_ulogic_vector(0 to 51); + iu_mm_ierat_thdid : out std_ulogic_vector(0 to 3); + iu_mm_ierat_state : out std_ulogic_vector(0 to 3); + iu_mm_ierat_tid : out std_ulogic_vector(0 to 13); + iu_mm_ierat_flush : out std_ulogic_vector(0 to 3); + mm_iu_ierat_rel_val : in std_ulogic_vector(0 to 4); + mm_iu_ierat_rel_data : in std_ulogic_vector(0 to 131); + mm_iu_ierat_snoop_coming : in std_ulogic; + mm_iu_ierat_snoop_val : in std_ulogic; + mm_iu_ierat_snoop_attr : in std_ulogic_vector(0 to 25); + mm_iu_ierat_snoop_vpn : in std_ulogic_vector(EFF_IFAR'left to 51); + iu_mm_ierat_snoop_ack : out std_ulogic; + mm_iu_ierat_pid0 : in std_ulogic_vector(0 to 13); + mm_iu_ierat_pid1 : in std_ulogic_vector(0 to 13); + mm_iu_ierat_pid2 : in std_ulogic_vector(0 to 13); + mm_iu_ierat_pid3 : in std_ulogic_vector(0 to 13); + mm_iu_ierat_mmucr0_0 : in std_ulogic_vector(0 to 19); + mm_iu_ierat_mmucr0_1 : in std_ulogic_vector(0 to 19); + mm_iu_ierat_mmucr0_2 : in std_ulogic_vector(0 to 19); + mm_iu_ierat_mmucr0_3 : in std_ulogic_vector(0 to 19); + iu_mm_ierat_mmucr0 : out std_ulogic_vector(0 to 17); + iu_mm_ierat_mmucr0_we : out std_ulogic_vector(0 to 3); + mm_iu_ierat_mmucr1 : in std_ulogic_vector(0 to 8); + iu_mm_ierat_mmucr1 : out std_ulogic_vector(0 to 3); + iu_mm_ierat_mmucr1_we : out std_ulogic; + mm_iu_barrier_done : in std_ulogic_vector(0 to 3); + iu_mm_lmq_empty : out std_ulogic; + + xu_iu_ex1_rb : in std_ulogic_vector(64-(2**regmode) to 51); + xu_wl_rf1_flush : in std_ulogic_vector(0 to 3); + xu_wl_ex1_flush : in std_ulogic_vector(0 to 3); + xu_wl_ex2_flush : in std_ulogic_vector(0 to 3); + xu_wl_ex3_flush : in std_ulogic_vector(0 to 3); + xu_wl_ex4_flush : in std_ulogic_vector(0 to 3); + xu_wl_ex5_flush : in std_ulogic_vector(0 to 3); + xu_wu_rf1_flush : in std_ulogic_vector(0 to 3); + xu_wu_ex1_flush : in std_ulogic_vector(0 to 3); + xu_wu_ex2_flush : in std_ulogic_vector(0 to 3); + xu_wu_ex3_flush : in std_ulogic_vector(0 to 3); + xu_wu_ex4_flush : in std_ulogic_vector(0 to 3); + xu_wu_ex5_flush : in std_ulogic_vector(0 to 3); + xu_iu_ex4_rs_data : in std_ulogic_vector(64-(2**regmode) to 63); + xu_iu_hid_mmu_mode : in std_ulogic; + xu_iu_msr_hv : in std_ulogic_vector(0 to threads-1); + xu_iu_msr_is : in std_ulogic_vector(0 to threads-1); + xu_iu_msr_pr : in std_ulogic_vector(0 to threads-1); + xu_iu_spr_ccr2_ifratsc : in std_ulogic_vector(0 to 8); + xu_iu_spr_ccr2_ifrat : in std_ulogic; + xu_iu_xucr4_mmu_mchk : in std_ulogic; + xu_iu_rf1_val : in std_ulogic_vector(0 to 3); + xu_iu_rf1_is_eratre : in std_ulogic; + xu_iu_rf1_is_eratsx : in std_ulogic; + xu_iu_rf1_is_eratwe : in std_ulogic; + xu_iu_rf1_is_eratilx : in std_ulogic; + xu_iu_ex1_is_isync : in std_ulogic; + xu_iu_ex1_is_csync : in std_ulogic; + xu_iu_rf1_ws : in std_ulogic_vector(0 to 1); + xu_iu_rf1_t : in std_ulogic_vector(0 to 2); + xu_iu_ex1_ra_entry : in std_ulogic_vector(8 to 11); + xu_iu_ex1_rs_is : in std_ulogic_vector(0 to 8); + iu_xu_ex4_tlb_data : out std_ulogic_vector(64-(2**regmode) to 63); + iu_xu_ierat_ex3_par_err : out std_ulogic_vector(0 to threads-1); + iu_xu_ierat_ex4_par_err : out std_ulogic_vector(0 to threads-1); + iu_xu_ierat_ex2_flush_req : out std_ulogic_vector(0 to threads-1); + + xu_iu_ex5_ifar : in EFF_IFAR; + xu_iu_ex5_tid : in std_ulogic_vector(0 to 3); + xu_iu_ex5_val : in std_ulogic; + xu_iu_ex5_br_update : in std_ulogic; + xu_iu_ex5_br_hist : in std_ulogic_vector(0 to 1); + xu_iu_ex5_br_taken : in std_ulogic; + xu_iu_ex5_bclr : in std_ulogic; + xu_iu_ex5_getNIA : in std_ulogic; + xu_iu_ex5_lk : in std_ulogic; + xu_iu_ex5_bh : in std_ulogic_vector(0 to 1); + xu_iu_ex5_gshare : in std_ulogic_vector(0 to 3); + + pc_iu_ram_instr : in std_ulogic_vector(0 to 31); + pc_iu_ram_instr_ext : in std_ulogic_vector(0 to 3); + pc_iu_ram_force_cmplt : in std_ulogic; + pc_iu_ram_mode : in std_ulogic; + pc_iu_ram_thread : in std_ulogic_vector(0 to 1); + xu_iu_ram_issue : in std_ulogic_vector(0 to 3); + + xu_iu_ex6_pri : in std_ulogic_vector(0 to 2); + xu_iu_ex6_pri_val : in std_ulogic_vector(0 to 3); + xu_iu_raise_iss_pri : in std_ulogic_vector(0 to 3); + xu_iu_msr_gs : in std_ulogic_vector(0 to 3); + + xu_iu_ucode_restart : in std_ulogic_vector(0 to 3); + xu_iu_spr_xer0 : in std_ulogic_vector(57 to 63); + xu_iu_spr_xer1 : in std_ulogic_vector(57 to 63); + xu_iu_spr_xer2 : in std_ulogic_vector(57 to 63); + xu_iu_spr_xer3 : in std_ulogic_vector(57 to 63); + xu_iu_uc_flush_ifar0 : in std_ulogic_vector(62-uc_ifar to 61); + xu_iu_uc_flush_ifar1 : in std_ulogic_vector(62-uc_ifar to 61); + xu_iu_uc_flush_ifar2 : in std_ulogic_vector(62-uc_ifar to 61); + xu_iu_uc_flush_ifar3 : in std_ulogic_vector(62-uc_ifar to 61); + + xu_iu_slowspr_done : in std_ulogic_vector(0 to 3); + + xu_iu_ex4_loadmiss_tid : in std_ulogic_vector(0 to 3); + xu_iu_ex4_loadmiss_qentry : in std_ulogic_vector(0 to lmq_entries-1); + xu_iu_ex4_loadmiss_target : in std_ulogic_vector(0 to 8); + xu_iu_ex4_loadmiss_target_type : in std_ulogic_vector(0 to 1); + xu_iu_ex5_loadmiss_tid : in std_ulogic_vector(0 to 3); + xu_iu_ex5_loadmiss_qentry : in std_ulogic_vector(0 to lmq_entries-1); + xu_iu_ex5_loadmiss_target : in std_ulogic_vector(0 to 8); + xu_iu_ex5_loadmiss_target_type : in std_ulogic_vector(0 to 1); + + xu_iu_complete_tid : in std_ulogic_vector(0 to 3); + xu_iu_complete_qentry : in std_ulogic_vector(0 to lmq_entries-1); + xu_iu_complete_target_type : in std_ulogic_vector(0 to 1); + iu_xu_quiesce : out std_ulogic_vector(0 to 3); + xu_iu_single_instr_mode : in std_ulogic_vector(0 to 3); + xu_iu_need_hole : in std_ulogic; + xu_iu_xucr0_rel : in std_ulogic; + xu_iu_spr_ccr2_en_dcr : in std_ulogic; + + xu_iu_ex5_ppc_cpl : in std_ulogic_vector(0 to 3); + xu_iu_multdiv_done : in std_ulogic_vector(0 to 3); + iu_xu_is2_ucode_vld : out std_ulogic; + iu_xu_is2_vld : out std_ulogic; + iu_xu_is2_tid : out std_ulogic_vector(0 to 3); + iu_xu_is2_instr : out std_ulogic_vector(0 to 31); + iu_xu_is2_ta_vld : out std_ulogic; + iu_xu_is2_ta : out std_ulogic_vector(0 to 5); + iu_xu_is2_s1_vld : out std_ulogic; + iu_xu_is2_s1 : out std_ulogic_vector(0 to 5); + iu_xu_is2_s2_vld : out std_ulogic; + iu_xu_is2_s2 : out std_ulogic_vector(0 to 5); + iu_xu_is2_s3_vld : out std_ulogic; + iu_xu_is2_s3 : out std_ulogic_vector(0 to 5); + iu_xu_is2_pred_update : out std_ulogic; + iu_xu_is2_pred_taken_cnt : out std_ulogic_vector(0 to 1); + iu_xu_is2_gshare : out std_ulogic_vector(0 to 3); + iu_xu_is2_ifar : out eff_ifar; + iu_xu_is2_axu_ld_or_st : out std_ulogic; + iu_xu_is2_axu_store : out std_ulogic; + iu_xu_is2_axu_ldst_size : out std_ulogic_vector(0 to 5); + iu_xu_is2_axu_ldst_tag : out std_ulogic_vector(0 to 8); + iu_xu_is2_axu_ldst_indexed : out std_ulogic; + iu_xu_is2_axu_ldst_update : out std_ulogic; + iu_xu_is2_axu_ldst_extpid : out std_ulogic; + iu_xu_is2_axu_ldst_forcealign : out std_ulogic; + iu_xu_is2_axu_ldst_forceexcept : out std_ulogic; + iu_xu_is2_axu_mftgpr : out std_ulogic; + iu_xu_is2_axu_mffgpr : out std_ulogic; + iu_xu_is2_axu_movedp : out std_ulogic; + iu_xu_is2_axu_instr_type : out std_ulogic_vector(0 to 2); + iu_xu_is2_error : out std_ulogic_vector(0 to 2); + iu_xu_is2_is_ucode : out std_ulogic; + iu_xu_is2_match : out std_ulogic; + + iu_fu_is2_tid_decode : out std_ulogic_vector(0 to 3); + iu_fu_rf0_ucfmul : out std_ulogic; + iu_fu_rf0_instr : out std_ulogic_vector(0 to 31); + iu_fu_rf0_instr_v : out std_ulogic; + iu_fu_rf0_instr_match : out std_ulogic; + iu_fu_rf0_is_ucode : out std_ulogic; + iu_fu_rf0_fra : out std_ulogic_vector(0 to 6); + iu_fu_rf0_frb : out std_ulogic_vector(0 to 6); + iu_fu_rf0_frc : out std_ulogic_vector(0 to 6); + iu_fu_rf0_frt : out std_ulogic_vector(0 to 6); + iu_fu_rf0_fra_v : out std_ulogic; + iu_fu_rf0_frb_v : out std_ulogic; + iu_fu_rf0_frc_v : out std_ulogic; + iu_fu_rf0_tid : out std_ulogic_vector(0 to 1); + iu_fu_rf0_bypsel : out std_ulogic_vector(0 to 5); + iu_fu_rf0_ifar : out EFF_IFAR; + iu_fu_rf0_str_val : out std_ulogic; + iu_fu_rf0_ldst_val : out std_ulogic; + iu_fu_rf0_ldst_tid : out std_ulogic_vector(0 to 1); + iu_fu_rf0_ldst_tag : out std_ulogic_vector(0 to 8); + + fu_iu_uc_special : in std_ulogic_vector(0 to 3); + iu_fu_ex2_n_flush : out std_ulogic_vector(0 to 3); + + rtim_sl_thold_7 : in std_ulogic; + func_sl_thold_7 : in std_ulogic; + func_nsl_thold_7 : in std_ulogic; + ary_nsl_thold_7 : in std_ulogic; + sg_7 : in std_ulogic; + fce_7 : in std_ulogic; + rtim_sl_thold_6 : out std_ulogic; + func_sl_thold_6 : out std_ulogic; + func_nsl_thold_6 : out std_ulogic; + ary_nsl_thold_6 : out std_ulogic; + sg_6 : out std_ulogic; + fce_6 : out std_ulogic; + an_ac_scom_dch : in std_ulogic; + an_ac_scom_cch : in std_ulogic; + an_ac_checkstop : in std_ulogic; + an_ac_debug_stop : in std_ulogic; + an_ac_pm_thread_stop : in std_ulogic_vector(0 to 3); + an_ac_reset_1_complete : in std_ulogic; + an_ac_reset_2_complete : in std_ulogic; + an_ac_reset_3_complete : in std_ulogic; + an_ac_reset_wd_complete : in std_ulogic; + an_ac_abist_start_test : in std_ulogic; + ac_rp_trace_to_perfcntr : in std_ulogic_vector(0 to 7); + rp_pc_scom_dch_q : out std_ulogic; + rp_pc_scom_cch_q : out std_ulogic; + rp_pc_checkstop_q : out std_ulogic; + rp_pc_debug_stop_q : out std_ulogic; + rp_pc_pm_thread_stop_q : out std_ulogic_vector(0 to 3); + rp_pc_reset_1_complete_q : out std_ulogic; + rp_pc_reset_2_complete_q : out std_ulogic; + rp_pc_reset_3_complete_q : out std_ulogic; + rp_pc_reset_wd_complete_q : out std_ulogic; + rp_pc_abist_start_test_q : out std_ulogic; + rp_pc_trace_to_perfcntr_q : out std_ulogic_vector(0 to 7); + pc_rp_scom_dch : in std_ulogic; + pc_rp_scom_cch : in std_ulogic; + pc_rp_special_attn : in std_ulogic_vector(0 to 3); + pc_rp_checkstop : in std_ulogic_vector(0 to 2); + pc_rp_local_checkstop : in std_ulogic_vector(0 to 2); + pc_rp_recov_err : in std_ulogic_vector(0 to 2); + pc_rp_trace_error : in std_ulogic; + pc_rp_event_bus_enable : in std_ulogic; + pc_rp_event_bus : in std_ulogic_vector(0 to 7); + pc_rp_fu_bypass_events : in std_ulogic_vector(0 to 7); + pc_rp_iu_bypass_events : in std_ulogic_vector(0 to 7); + pc_rp_mm_bypass_events : in std_ulogic_vector(0 to 7); + pc_rp_lsu_bypass_events : in std_ulogic_vector(0 to 7); + pc_rp_pm_thread_running : in std_ulogic_vector(0 to 3); + pc_rp_power_managed : in std_ulogic; + pc_rp_rvwinkle_mode : in std_ulogic; + ac_an_scom_dch_q : out std_ulogic; + ac_an_scom_cch_q : out std_ulogic; + ac_an_special_attn_q : out std_ulogic_vector(0 to 3); + ac_an_checkstop_q : out std_ulogic_vector(0 to 2); + ac_an_local_checkstop_q : out std_ulogic_vector(0 to 2); + ac_an_recov_err_q : out std_ulogic_vector(0 to 2); + ac_an_trace_error_q : out std_ulogic; + rp_mm_event_bus_enable_q : out std_ulogic; + ac_an_event_bus_q : out std_ulogic_vector(0 to 7); + ac_an_fu_bypass_events_q : out std_ulogic_vector(0 to 7); + ac_an_iu_bypass_events_q : out std_ulogic_vector(0 to 7); + ac_an_mm_bypass_events_q : out std_ulogic_vector(0 to 7); + ac_an_lsu_bypass_events_q : out std_ulogic_vector(0 to 7); + ac_an_pm_thread_running_q : out std_ulogic_vector(0 to 3); + ac_an_power_managed_q : out std_ulogic; + ac_an_rvwinkle_mode_q : out std_ulogic; + + pc_func_scan_in : in std_ulogic_vector(0 to 1); + pc_func_scan_in_q : out std_ulogic_vector(0 to 1); + pc_func_scan_out : in std_ulogic; + pc_func_scan_out_q : out std_ulogic; + pc_bcfg_scan_in : in std_ulogic; + pc_bcfg_scan_in_q : out std_ulogic; + pc_dcfg_scan_in : in std_ulogic; + pc_dcfg_scan_in_q : out std_ulogic; + pc_bcfg_scan_out : in std_ulogic; + pc_bcfg_scan_out_q : out std_ulogic; + pc_ccfg_scan_out : in std_ulogic; + pc_ccfg_scan_out_q : out std_ulogic; + pc_dcfg_scan_out : in std_ulogic; + pc_dcfg_scan_out_q : out std_ulogic; + fu_abst_scan_in : in std_ulogic; + fu_abst_scan_in_q : out std_ulogic; + fu_abst_scan_out : in std_ulogic; + fu_abst_scan_out_q : out std_ulogic; + fu_ccfg_scan_out : in std_ulogic; + fu_ccfg_scan_out_q : out std_ulogic; + fu_bcfg_scan_out : in std_ulogic; + fu_bcfg_scan_out_q : out std_ulogic; + fu_dcfg_scan_out : in std_ulogic; + fu_dcfg_scan_out_q : out std_ulogic; + fu_func_scan_in : in std_ulogic_vector(0 to 3); + fu_func_scan_in_q : out std_ulogic_vector(0 to 3); + fu_func_scan_out : in std_ulogic_vector(0 to 3); + fu_func_scan_out_q : out std_ulogic_vector(0 to 3); + bx_abst_scan_in : in std_ulogic; + bx_abst_scan_in_q : out std_ulogic; + bx_abst_scan_out : in std_ulogic; + bx_abst_scan_out_q : out std_ulogic; + bx_func_scan_in : in std_ulogic_vector(0 to 1); + bx_func_scan_in_q : out std_ulogic_vector(0 to 1); + bx_func_scan_out : in std_ulogic_vector(0 to 1); + bx_func_scan_out_q : out std_ulogic_vector(0 to 1); + spare_func_scan_in : in std_ulogic_vector(0 to 3); + spare_func_scan_out_q : out std_ulogic_vector(0 to 3); + rp_abst_scan_in : in std_ulogic; + rp_func_scan_in : in std_ulogic; + rp_abst_scan_out : out std_ulogic; + rp_func_scan_out : out std_ulogic; + + bg_an_ac_func_scan_sn : in std_ulogic_vector(60 to 69); + bg_an_ac_abst_scan_sn : in std_ulogic_vector(10 to 11); + bg_an_ac_func_scan_sn_q : out std_ulogic_vector(60 to 69); + bg_an_ac_abst_scan_sn_q : out std_ulogic_vector(10 to 11); + + bg_ac_an_func_scan_ns : in std_ulogic_vector(60 to 69); + bg_ac_an_abst_scan_ns : in std_ulogic_vector(10 to 11); + bg_ac_an_func_scan_ns_q : out std_ulogic_vector(60 to 69); + bg_ac_an_abst_scan_ns_q : out std_ulogic_vector(10 to 11); + + bg_pc_l1p_abist_di_0 : in std_ulogic_vector(0 to 3); + bg_pc_l1p_abist_g8t1p_renb_0 : in std_ulogic; + bg_pc_l1p_abist_g8t_bw_0 : in std_ulogic; + bg_pc_l1p_abist_g8t_bw_1 : in std_ulogic; + bg_pc_l1p_abist_g8t_dcomp : in std_ulogic_vector(0 to 3); + bg_pc_l1p_abist_g8t_wenb : in std_ulogic; + bg_pc_l1p_abist_raddr_0 : in std_ulogic_vector(0 to 9); + bg_pc_l1p_abist_waddr_0 : in std_ulogic_vector(0 to 9); + bg_pc_l1p_abist_wl128_comp_ena : in std_ulogic; + bg_pc_l1p_abist_wl32_comp_ena : in std_ulogic; + bg_pc_l1p_abist_di_0_q : out std_ulogic_vector(0 to 3); + bg_pc_l1p_abist_g8t1p_renb_0_q : out std_ulogic; + bg_pc_l1p_abist_g8t_bw_0_q : out std_ulogic; + bg_pc_l1p_abist_g8t_bw_1_q : out std_ulogic; + bg_pc_l1p_abist_g8t_dcomp_q: out std_ulogic_vector(0 to 3); + bg_pc_l1p_abist_g8t_wenb_q : out std_ulogic; + bg_pc_l1p_abist_raddr_0_q : out std_ulogic_vector(0 to 9); + bg_pc_l1p_abist_waddr_0_q : out std_ulogic_vector(0 to 9); + bg_pc_l1p_abist_wl128_comp_ena_q : out std_ulogic; + bg_pc_l1p_abist_wl32_comp_ena_q : out std_ulogic; + + bg_pc_l1p_gptr_sl_thold_3 : in std_ulogic; + bg_pc_l1p_time_sl_thold_3 : in std_ulogic; + bg_pc_l1p_repr_sl_thold_3 : in std_ulogic; + bg_pc_l1p_abst_sl_thold_3 : in std_ulogic; + bg_pc_l1p_func_sl_thold_3 : in std_ulogic_vector(0 to 1); + bg_pc_l1p_func_slp_sl_thold_3 : in std_ulogic; + bg_pc_l1p_bolt_sl_thold_3 : in std_ulogic; + bg_pc_l1p_ary_nsl_thold_3 : in std_ulogic; + bg_pc_l1p_sg_3 : in std_ulogic_vector(0 to 1); + bg_pc_l1p_fce_3 : in std_ulogic; + bg_pc_l1p_bo_enable_3 : in std_ulogic; + bg_pc_l1p_gptr_sl_thold_2 : out std_ulogic; + bg_pc_l1p_time_sl_thold_2 : out std_ulogic; + bg_pc_l1p_repr_sl_thold_2 : out std_ulogic; + bg_pc_l1p_abst_sl_thold_2 : out std_ulogic; + bg_pc_l1p_func_sl_thold_2 : out std_ulogic_vector(0 to 1); + bg_pc_l1p_func_slp_sl_thold_2 : out std_ulogic; + bg_pc_l1p_bolt_sl_thold_2 : out std_ulogic; + bg_pc_l1p_ary_nsl_thold_2 : out std_ulogic; + bg_pc_l1p_sg_2 : out std_ulogic_vector(0 to 1); + bg_pc_l1p_fce_2 : out std_ulogic; + bg_pc_l1p_bo_enable_2 : out std_ulogic; + + + bg_pc_bo_unload_iiu : in std_ulogic; + bg_pc_bo_load_iiu : in std_ulogic; + bg_pc_bo_repair_iiu : in std_ulogic; + bg_pc_bo_reset_iiu : in std_ulogic; + bg_pc_bo_shdata_iiu : in std_ulogic; + bg_pc_bo_select_iiu : in std_ulogic_vector(0 to 10); + bg_pc_l1p_ccflush_dc_iiu : in std_ulogic; + bg_pc_l1p_abist_ena_dc_iiu : in std_ulogic; + bg_pc_l1p_abist_raw_dc_b_iiu : in std_ulogic; + + bg_pc_bo_unload_oiu : out std_ulogic; + bg_pc_bo_load_oiu : out std_ulogic; + bg_pc_bo_repair_oiu : out std_ulogic; + bg_pc_bo_reset_oiu : out std_ulogic; + bg_pc_bo_shdata_oiu : out std_ulogic; + bg_pc_bo_select_oiu : out std_ulogic_vector(0 to 10); + bg_pc_l1p_ccflush_dc_oiu : out std_ulogic; + bg_pc_l1p_abist_ena_dc_oiu : out std_ulogic; + bg_pc_l1p_abist_raw_dc_b_oiu : out std_ulogic; + + ac_an_abist_done_dc_iiu : in std_ulogic; + ac_an_psro_ringsig_iiu : in std_ulogic; + mm_pc_bo_fail_iiu : in std_ulogic_vector(0 to 4); + mm_pc_bo_diagout_iiu : in std_ulogic_vector(0 to 4); + mm_pc_event_data_iiu : in std_ulogic_vector(0 to 7); + + ac_an_abist_done_dc_oiu : out std_ulogic; + ac_an_psro_ringsig_oiu : out std_ulogic; + mm_pc_bo_fail_oiu : out std_ulogic_vector(0 to 4); + mm_pc_bo_diagout_oiu : out std_ulogic_vector(0 to 4); + mm_pc_event_data_oiu : out std_ulogic_vector(0 to 7); + + bg_pc_bo_fail_iiu : in std_ulogic_vector(0 to 10); + bg_pc_bo_diagout_iiu : in std_ulogic_vector(0 to 10); + + bg_pc_bo_fail_oiu : out std_ulogic_vector(0 to 10); + bg_pc_bo_diagout_oiu : out std_ulogic_vector(0 to 10); + + an_ac_abist_mode_dc_iiu : in std_ulogic; + an_ac_ccenable_dc_iiu : in std_ulogic; + an_ac_ccflush_dc_iiu : in std_ulogic; + an_ac_gsd_test_enable_dc_iiu : in std_ulogic; + an_ac_gsd_test_acmode_dc_iiu : in std_ulogic; + an_ac_lbist_ip_dc_iiu : in std_ulogic; + an_ac_lbist_ac_mode_dc_iiu : in std_ulogic; + an_ac_malf_alert_iiu : in std_ulogic; + an_ac_psro_enable_dc_iiu : in std_ulogic_vector(0 to 2); + an_ac_scan_type_dc_iiu : in std_ulogic_vector(0 to 8); + an_ac_scom_sat_id_iiu : in std_ulogic_vector(0 to 3); + + pc_mm_abist_dcomp_g6t_2r_iiu : in std_ulogic_vector(0 to 3); + pc_mm_abist_di_g6t_2r_iiu : in std_ulogic_vector(0 to 3); + pc_mm_abist_di_0_iiu : in std_ulogic_vector(0 to 3); + pc_mm_abist_ena_dc_iiu : in std_ulogic; + pc_mm_abist_g6t_r_wb_iiu : in std_ulogic; + pc_mm_abist_g8t_bw_0_iiu : in std_ulogic; + pc_mm_abist_g8t_bw_1_iiu : in std_ulogic; + pc_mm_abist_g8t_dcomp_iiu : in std_ulogic_vector(0 to 3); + pc_mm_abist_g8t_wenb_iiu : in std_ulogic; + pc_mm_abist_g8t1p_renb_0_iiu : in std_ulogic; + pc_mm_abist_raddr_0_iiu : in std_ulogic_vector(0 to 9); + pc_mm_abist_raw_dc_b_iiu : in std_ulogic; + pc_mm_abist_waddr_0_iiu : in std_ulogic_vector(0 to 9); + pc_mm_abist_wl128_comp_ena_iiu : in std_ulogic; + pc_mm_bo_enable_4_iiu : in std_ulogic; + pc_mm_bo_repair_iiu : in std_ulogic; + pc_mm_bo_reset_iiu : in std_ulogic; + pc_mm_bo_select_iiu : in std_ulogic_vector(0 to 4); + pc_mm_bo_shdata_iiu : in std_ulogic; + pc_mm_bo_unload_iiu : in std_ulogic; + pc_mm_ccflush_dc_iiu : in std_ulogic; + pc_mm_debug_mux1_ctrls_iiu : in std_ulogic_vector(0 to 15); + pc_mm_event_count_mode_iiu : in std_ulogic_vector(0 to 2); + pc_mm_event_mux_ctrls_iiu : in std_ulogic_vector(0 to 39); + pc_mm_trace_bus_enable_iiu : in std_ulogic; + + an_ac_abist_mode_dc_oiu : out std_ulogic; + an_ac_ccenable_dc_oiu : out std_ulogic; + an_ac_ccflush_dc_oiu : out std_ulogic; + an_ac_gsd_test_enable_dc_oiu : out std_ulogic; + an_ac_gsd_test_acmode_dc_oiu : out std_ulogic; + an_ac_lbist_ip_dc_oiu : out std_ulogic; + an_ac_lbist_ac_mode_dc_oiu : out std_ulogic; + an_ac_malf_alert_oiu : out std_ulogic; + an_ac_psro_enable_dc_oiu : out std_ulogic_vector(0 to 2); + an_ac_scan_type_dc_oiu : out std_ulogic_vector(0 to 8); + an_ac_scom_sat_id_oiu : out std_ulogic_vector(0 to 3); + + pc_mm_abist_dcomp_g6t_2r_oiu : out std_ulogic_vector(0 to 3); + pc_mm_abist_di_g6t_2r_oiu : out std_ulogic_vector(0 to 3); + pc_mm_abist_di_0_oiu : out std_ulogic_vector(0 to 3); + pc_mm_abist_ena_dc_oiu : out std_ulogic; + pc_mm_abist_g6t_r_wb_oiu : out std_ulogic; + pc_mm_abist_g8t_bw_0_oiu : out std_ulogic; + pc_mm_abist_g8t_bw_1_oiu : out std_ulogic; + pc_mm_abist_g8t_dcomp_oiu : out std_ulogic_vector(0 to 3); + pc_mm_abist_g8t_wenb_oiu : out std_ulogic; + pc_mm_abist_g8t1p_renb_0_oiu : out std_ulogic; + pc_mm_abist_raddr_0_oiu : out std_ulogic_vector(0 to 9); + pc_mm_abist_raw_dc_b_oiu : out std_ulogic; + pc_mm_abist_waddr_0_oiu : out std_ulogic_vector(0 to 9); + pc_mm_abist_wl128_comp_ena_oiu : out std_ulogic; + pc_mm_abst_sl_thold_3_oiu : out std_ulogic; + pc_mm_abst_slp_sl_thold_3_oiu : out std_ulogic; + pc_mm_ary_nsl_thold_3_oiu : out std_ulogic; + pc_mm_ary_slp_nsl_thold_3_oiu : out std_ulogic; + pc_mm_bo_enable_3_oiu : out std_ulogic; + pc_mm_bo_repair_oiu : out std_ulogic; + pc_mm_bo_reset_oiu : out std_ulogic; + pc_mm_bo_select_oiu : out std_ulogic_vector(0 to 4); + pc_mm_bo_shdata_oiu : out std_ulogic; + pc_mm_bo_unload_oiu : out std_ulogic; + pc_mm_bolt_sl_thold_3_oiu : out std_ulogic; + pc_mm_ccflush_dc_oiu : out std_ulogic; + pc_mm_cfg_sl_thold_3_oiu : out std_ulogic; + pc_mm_cfg_slp_sl_thold_3_oiu : out std_ulogic; + pc_mm_debug_mux1_ctrls_oiu : out std_ulogic_vector(0 to 15); + pc_mm_event_count_mode_oiu : out std_ulogic_vector(0 to 2); + pc_mm_event_mux_ctrls_oiu : out std_ulogic_vector(0 to 39); + pc_mm_fce_3_oiu : out std_ulogic; + pc_mm_func_nsl_thold_3_oiu : out std_ulogic; + pc_mm_func_sl_thold_3_oiu : out std_ulogic_vector(0 to 1); + pc_mm_func_slp_nsl_thold_3_oiu : out std_ulogic; + pc_mm_func_slp_sl_thold_3_oiu : out std_ulogic_vector(0 to 1); + pc_mm_gptr_sl_thold_3_oiu : out std_ulogic; + pc_mm_repr_sl_thold_3_oiu : out std_ulogic; + pc_mm_sg_3_oiu : out std_ulogic_vector(0 to 1); + pc_mm_time_sl_thold_3_oiu : out std_ulogic; + pc_mm_trace_bus_enable_oiu : out std_ulogic; + + an_ac_back_inv_oiu : out std_ulogic; + an_ac_back_inv_addr_oiu : out std_ulogic_vector(REAL_IFAR'left to 63); + an_ac_back_inv_target_bit1_oiu : out std_ulogic; + an_ac_back_inv_target_bit3_oiu : out std_ulogic; + an_ac_back_inv_target_bit4_oiu : out std_ulogic; + an_ac_atpg_en_dc_oiu : out std_ulogic; + an_ac_lbist_ary_wrt_thru_dc_oiu : out std_ulogic; + an_ac_lbist_en_dc_oiu : out std_ulogic; + an_ac_scan_diag_dc_oiu : out std_ulogic; + an_ac_scan_dis_dc_b_oiu : out std_ulogic; + an_ac_grffence_en_dc_oiu : out std_ulogic + +); +-- synopsys translate_off +-- synopsys translate_on +end iuq; +architecture iuq of iuq is +signal clkoff_b : std_ulogic_vector(0 to 3); +signal delay_lclkr : std_ulogic_vector(5 to 14); +signal mpw1_b : std_ulogic_vector(5 to 14); +signal pc_iu_sg_2 : std_ulogic_vector(0 to 3); +signal pc_iu_func_sl_thold_2 : std_ulogic_vector(0 to 3); +-- BP +signal bp_ib_iu4_t0_val : std_ulogic_vector(0 to 3); +signal bp_ib_iu4_t1_val : std_ulogic_vector(0 to 3); +signal bp_ib_iu4_t2_val : std_ulogic_vector(0 to 3); +signal bp_ib_iu4_t3_val : std_ulogic_vector(0 to 3); +signal bp_ib_iu4_ifar_t0 : EFF_IFAR; +signal bp_ib_iu3_0_instr_t0 : std_ulogic_vector(0 to 31); +signal bp_ib_iu4_0_instr_t0 : std_ulogic_vector(32 to 43); +signal bp_ib_iu4_1_instr_t0 : std_ulogic_vector(0 to 43); +signal bp_ib_iu4_2_instr_t0 : std_ulogic_vector(0 to 43); +signal bp_ib_iu4_3_instr_t0 : std_ulogic_vector(0 to 43); +signal bp_ib_iu4_ifar_t1 : EFF_IFAR; +signal bp_ib_iu3_0_instr_t1 : std_ulogic_vector(0 to 31); +signal bp_ib_iu4_0_instr_t1 : std_ulogic_vector(32 to 43); +signal bp_ib_iu4_1_instr_t1 : std_ulogic_vector(0 to 43); +signal bp_ib_iu4_2_instr_t1 : std_ulogic_vector(0 to 43); +signal bp_ib_iu4_3_instr_t1 : std_ulogic_vector(0 to 43); +signal bp_ib_iu4_ifar_t2 : EFF_IFAR; +signal bp_ib_iu3_0_instr_t2 : std_ulogic_vector(0 to 31); +signal bp_ib_iu4_0_instr_t2 : std_ulogic_vector(32 to 43); +signal bp_ib_iu4_1_instr_t2 : std_ulogic_vector(0 to 43); +signal bp_ib_iu4_2_instr_t2 : std_ulogic_vector(0 to 43); +signal bp_ib_iu4_3_instr_t2 : std_ulogic_vector(0 to 43); +signal bp_ib_iu4_ifar_t3 : EFF_IFAR; +signal bp_ib_iu3_0_instr_t3 : std_ulogic_vector(0 to 31); +signal bp_ib_iu4_0_instr_t3 : std_ulogic_vector(32 to 43); +signal bp_ib_iu4_1_instr_t3 : std_ulogic_vector(0 to 43); +signal bp_ib_iu4_2_instr_t3 : std_ulogic_vector(0 to 43); +signal bp_ib_iu4_3_instr_t3 : std_ulogic_vector(0 to 43); +-- UC +signal uc_ib_iu4_val : std_ulogic_vector(0 to 3); +signal uc_ib_iu4_ifar_t0 : std_ulogic_vector(62-uc_ifar to 61); +signal uc_ib_iu4_instr_t0 : std_ulogic_vector(0 to 36); +signal uc_ib_iu4_ifar_t1 : std_ulogic_vector(62-uc_ifar to 61); +signal uc_ib_iu4_instr_t1 : std_ulogic_vector(0 to 36); +signal uc_ib_iu4_ifar_t2 : std_ulogic_vector(62-uc_ifar to 61); +signal uc_ib_iu4_instr_t2 : std_ulogic_vector(0 to 36); +signal uc_ib_iu4_ifar_t3 : std_ulogic_vector(62-uc_ifar to 61); +signal uc_ib_iu4_instr_t3 : std_ulogic_vector(0 to 36); +signal uc_flush_tid : std_ulogic_vector(0 to 3); +-- RAM +signal rm_ib_iu4_val : std_ulogic_vector(0 to 3); +signal rm_ib_iu4_force_ram_t0 : std_ulogic; +signal rm_ib_iu4_instr_t0 : std_ulogic_vector(0 to 35); +signal rm_ib_iu4_force_ram_t1 : std_ulogic; +signal rm_ib_iu4_instr_t1 : std_ulogic_vector(0 to 35); +signal rm_ib_iu4_force_ram_t2 : std_ulogic; +signal rm_ib_iu4_instr_t2 : std_ulogic_vector(0 to 35); +signal rm_ib_iu4_force_ram_t3 : std_ulogic; +signal rm_ib_iu4_instr_t3 : std_ulogic_vector(0 to 35); +-- IB +signal iu_au_ib1_instr_vld_t0 : std_ulogic; +signal iu_au_ib1_ifar_t0 : EFF_IFAR; +signal iu_au_ib1_data_t0 : std_ulogic_vector(0 to 49); +signal iu_au_ib1_instr_vld_t1 : std_ulogic; +signal iu_au_ib1_ifar_t1 : EFF_IFAR; +signal iu_au_ib1_data_t1 : std_ulogic_vector(0 to 49); +signal iu_au_ib1_instr_vld_t2 : std_ulogic; +signal iu_au_ib1_ifar_t2 : EFF_IFAR; +signal iu_au_ib1_data_t2 : std_ulogic_vector(0 to 49); +signal iu_au_ib1_instr_vld_t3 : std_ulogic; +signal iu_au_ib1_ifar_t3 : EFF_IFAR; +signal iu_au_ib1_data_t3 : std_ulogic_vector(0 to 49); +signal ib_ic_empty : std_ulogic_vector(0 to 3); +signal ib_ic_below_water : std_ulogic_vector(0 to 3); +signal ib_ic_iu5_redirect_tid : std_ulogic_vector(0 to 3); +-- SPR +signal iu_au_config_iucr_t0 : std_ulogic_vector(0 to 7); +signal iu_au_config_iucr_t1 : std_ulogic_vector(0 to 7); +signal iu_au_config_iucr_t2 : std_ulogic_vector(0 to 7); +signal iu_au_config_iucr_t3 : std_ulogic_vector(0 to 7); +signal spr_fiss_pri_rand : std_ulogic_vector(0 to 4); +signal spr_fiss_pri_rand_always : std_ulogic; +signal spr_fiss_pri_rand_flush : std_ulogic; +signal spr_fdep_ll_hold_t0 : std_ulogic; +signal spr_fdep_ll_hold_t1 : std_ulogic; +signal spr_fdep_ll_hold_t2 : std_ulogic; +signal spr_fdep_ll_hold_t3 : std_ulogic; +signal spr_issue_high_mask : std_ulogic_vector(0 to 3); +signal spr_issue_med_mask : std_ulogic_vector(0 to 3); +signal spr_fiss_count0_max : std_ulogic_vector(0 to 5); +signal spr_fiss_count1_max : std_ulogic_vector(0 to 5); +signal spr_fiss_count2_max : std_ulogic_vector(0 to 5); +signal spr_fiss_count3_max : std_ulogic_vector(0 to 5); +signal spr_dec_mask_pt_in_t0 : std_ulogic_vector(0 to 31); +signal spr_dec_mask_pt_in_t1 : std_ulogic_vector(0 to 31); +signal spr_dec_mask_pt_in_t2 : std_ulogic_vector(0 to 31); +signal spr_dec_mask_pt_in_t3 : std_ulogic_vector(0 to 31); +signal spr_dec_mask_pt_out_t0 : std_ulogic_vector(0 to 31); +signal spr_dec_mask_pt_out_t1 : std_ulogic_vector(0 to 31); +signal spr_dec_mask_pt_out_t2 : std_ulogic_vector(0 to 31); +signal spr_dec_mask_pt_out_t3 : std_ulogic_vector(0 to 31); +signal spr_dec_match_t0 : std_ulogic_vector(0 to 31); +signal spr_dec_match_t1 : std_ulogic_vector(0 to 31); +signal spr_dec_match_t2 : std_ulogic_vector(0 to 31); +signal spr_dec_match_t3 : std_ulogic_vector(0 to 31); +signal ic_fdep_load_quiesce : std_ulogic_vector(0 to 3); +signal ic_fdep_icbi_ack : std_ulogic_vector(0 to 3); +-- FXU Issue +signal iu_xu_is2_vld_internal : std_ulogic; +signal iu_xu_is2_tid_internal : std_ulogic_vector(0 to 3); +signal iu_xu_is2_instr_internal : std_ulogic_vector(0 to 31); +signal iu_xu_is2_error_internal : std_ulogic_vector(0 to 2); +signal iu_xu_is2_pred_update_internal : std_ulogic; +signal iu_xu_is2_pred_taken_cnt_internal : std_ulogic_vector(0 to 1); +signal iu_xu_is2_ifar_internal : EFF_IFAR; +signal iu_xu_is2_axu_store_internal : std_ulogic; +signal fiss_uc_is2_ucode_vld : std_ulogic; +signal fiss_uc_is2_tid : std_ulogic_vector(0 to 3); +signal fiss_uc_is2_instr : std_ulogic_vector(0 to 31); +signal fiss_uc_is2_2ucode : std_ulogic; +signal fiss_uc_is2_2ucode_type : std_ulogic; +signal iuq_mi_scan_out : std_ulogic_vector(0 to 1); +signal iuq_bp_scan_out : std_ulogic; +signal iuq_b0_scan_in : std_ulogic; +signal iuq_b0_scan_out : std_ulogic; +signal iuq_b1_scan_in : std_ulogic; +signal iuq_b1_scan_out : std_ulogic; +signal iuq_b2_scan_in : std_ulogic; +signal iuq_b2_scan_out : std_ulogic; +signal iuq_b3_scan_in : std_ulogic; +signal iuq_b3_scan_out : std_ulogic; +signal iuq_s0_scan_in : std_ulogic; +signal iuq_s0_scan_out : std_ulogic; +signal iuq_s1_scan_in : std_ulogic; +signal iuq_s1_scan_out : std_ulogic; +signal iuq_s2_scan_in : std_ulogic; +signal iuq_s2_scan_out : std_ulogic; +signal iuq_s3_scan_in : std_ulogic; +signal iuq_s3_scan_out : std_ulogic; +signal iuq_fi_scan_in : std_ulogic; +signal iuq_fi_scan_out : std_ulogic; +signal iuq_ai_scan_in : std_ulogic; +signal iuq_ai_scan_out : std_ulogic; +--perf +signal ib_perf_event_t0 : std_ulogic_vector(0 to 1); +signal ib_perf_event_t1 : std_ulogic_vector(0 to 1); +signal ib_perf_event_t2 : std_ulogic_vector(0 to 1); +signal ib_perf_event_t3 : std_ulogic_vector(0 to 1); +signal fdep_perf_event_pt_in_t0 : std_ulogic_vector(0 to 11); +signal fdep_perf_event_pt_in_t1 : std_ulogic_vector(0 to 11); +signal fdep_perf_event_pt_in_t2 : std_ulogic_vector(0 to 11); +signal fdep_perf_event_pt_in_t3 : std_ulogic_vector(0 to 11); +signal fdep_perf_event_pt_out_t0: std_ulogic_vector(0 to 11); +signal fdep_perf_event_pt_out_t1: std_ulogic_vector(0 to 11); +signal fdep_perf_event_pt_out_t2: std_ulogic_vector(0 to 11); +signal fdep_perf_event_pt_out_t3: std_ulogic_vector(0 to 11); +signal fiss_perf_event_t0 : std_ulogic_vector(0 to 7); +signal fiss_perf_event_t1 : std_ulogic_vector(0 to 7); +signal fiss_perf_event_t2 : std_ulogic_vector(0 to 7); +signal fiss_perf_event_t3 : std_ulogic_vector(0 to 7); +signal fdec_ibuf_stall_t0 : std_ulogic; +signal fdec_ibuf_stall_t1 : std_ulogic; +signal fdec_ibuf_stall_t2 : std_ulogic; +signal fdec_ibuf_stall_t3 : std_ulogic; +--debug groups (misc) +signal fiss_dbg_data : std_ulogic_vector(0 to 87); +signal fdep_dbg_data_pt_in : std_ulogic_vector(0 to 87); +signal fdep_dbg_data_pt_out : std_ulogic_vector(0 to 87); +signal ib_dbg_data : std_ulogic_vector(0 to 63); +signal fu_iss_dbg_data : std_ulogic_vector(0 to 23); +signal axu_dbg_data_t0 : std_ulogic_vector(0 to 37); +signal axu_dbg_data_t1 : std_ulogic_vector(0 to 37); +signal axu_dbg_data_t2 : std_ulogic_vector(0 to 37); +signal axu_dbg_data_t3 : std_ulogic_vector(0 to 37); +-- IU pass thru signals +signal an_ac_scan_dis_dc_b_oif : std_ulogic_vector(0 to 3); +signal an_ac_back_inv_oif : std_ulogic; +signal an_ac_back_inv_target_oif: std_ulogic_vector(1 to 1); +signal an_ac_sync_ack_oif : std_ulogic_vector(0 to 3); +signal mm_iu_barrier_done_oif : std_ulogic_vector(0 to 3); +-- IU repower +signal iu_func_scan_in_q : std_ulogic_vector(0 to 4); +signal iu_func_scan_out : std_ulogic_vector(0 to 7); +signal unused : std_ulogic_vector(6 to 14); +-- synopsys translate_off +-- synopsys translate_on +begin +------------------------------------------ +--tie off unused signals +------------------------------------------ +unused(6 to 8) <= pc_iu_abist_waddr_0(0 to 2); +unused(9 to 10) <= pc_iu_abist_raddr_0(0 to 1); +unused(11) <= xu_iu_ex5_loadmiss_target(0); +unused(12 to 13)<= xu_iu_ex5_loadmiss_target(7 to 8); +unused(14) <= xu_iu_ex5_loadmiss_target_type(1); +------------------------------------------ +------------------------------------------ +iuq_ifetch0 : entity work.iuq_ifetch +generic map(expand_type => expand_type, + a2mode => a2mode, + regmode => regmode, + threads => threads, + ucode_mode => ucode_mode, + bcfg_epn_0to15 => bcfg_epn_0to15, + bcfg_epn_16to31 => bcfg_epn_16to31, + bcfg_epn_32to47 => bcfg_epn_32to47, + bcfg_epn_48to51 => bcfg_epn_48to51, + bcfg_rpn_22to31 => bcfg_rpn_22to31, + bcfg_rpn_32to47 => bcfg_rpn_32to47, + bcfg_rpn_48to51 => bcfg_rpn_48to51, + uc_ifar => uc_ifar) +port map( + vcs => vcs, + vdd => vdd, + gnd => gnd, + nclk => nclk, + tc_ac_ccflush_dc => tc_ac_ccflush_dc, + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b, + an_ac_scan_diag_dc => an_ac_scan_diag_dc, + pc_iu_gptr_sl_thold_4 => pc_iu_gptr_sl_thold_4, + pc_iu_time_sl_thold_4 => pc_iu_time_sl_thold_4, + pc_iu_repr_sl_thold_4 => pc_iu_repr_sl_thold_4, + pc_iu_abst_sl_thold_4 => pc_iu_abst_sl_thold_4, + pc_iu_abst_slp_sl_thold_4 => pc_iu_abst_slp_sl_thold_4, + pc_iu_bolt_sl_thold_4 => pc_iu_bolt_sl_thold_4, + pc_iu_regf_slp_sl_thold_4 => pc_iu_regf_slp_sl_thold_4, + pc_iu_func_sl_thold_4 => pc_iu_func_sl_thold_4, + pc_iu_func_slp_sl_thold_4 => pc_iu_func_slp_sl_thold_4, + pc_iu_cfg_sl_thold_4 => pc_iu_cfg_sl_thold_4, + pc_iu_cfg_slp_sl_thold_4 => pc_iu_cfg_slp_sl_thold_4, + pc_iu_func_nsl_thold_4 => pc_iu_func_nsl_thold_4, + pc_iu_func_slp_nsl_thold_4 => pc_iu_func_slp_nsl_thold_4, + pc_iu_ary_nsl_thold_4 => pc_iu_ary_nsl_thold_4, + pc_iu_ary_slp_nsl_thold_4 => pc_iu_ary_slp_nsl_thold_4, + pc_iu_sg_4 => pc_iu_sg_4, + pc_iu_fce_4 => pc_iu_fce_4, + pc_iu_abist_dcomp_g6t_2r => pc_iu_abist_dcomp_g6t_2r, + pc_iu_abist_di_0 => pc_iu_abist_di_0, + pc_iu_abist_di_g6t_2r => pc_iu_abist_di_g6t_2r, + pc_iu_abist_ena_dc => pc_iu_abist_ena_dc, + pc_iu_abist_g6t_bw => pc_iu_abist_g6t_bw, + pc_iu_abist_g6t_r_wb => pc_iu_abist_g6t_r_wb, + pc_iu_abist_g8t1p_renb_0 => pc_iu_abist_g8t1p_renb_0, + pc_iu_abist_g8t_bw_0 => pc_iu_abist_g8t_bw_0, + pc_iu_abist_g8t_bw_1 => pc_iu_abist_g8t_bw_1, + pc_iu_abist_g8t_dcomp => pc_iu_abist_g8t_dcomp, + pc_iu_abist_g8t_wenb => pc_iu_abist_g8t_wenb, + pc_iu_abist_raddr_0 => pc_iu_abist_raddr_0(2 to 9), + pc_iu_abist_raw_dc_b => pc_iu_abist_raw_dc_b, + pc_iu_abist_waddr_0 => pc_iu_abist_waddr_0(3 to 9), + pc_iu_abist_wl256_comp_ena => pc_iu_abist_wl256_comp_ena, + pc_iu_abist_wl64_comp_ena => pc_iu_abist_wl64_comp_ena, + pc_iu_abist_wl128_comp_ena => pc_iu_abist_wl128_comp_ena, + an_ac_lbist_ary_wrt_thru_dc=> an_ac_lbist_ary_wrt_thru_dc, + an_ac_lbist_en_dc => an_ac_lbist_en_dc, + an_ac_atpg_en_dc => an_ac_atpg_en_dc, + an_ac_grffence_en_dc => an_ac_grffence_en_dc, + pc_iu_bo_enable_4 => pc_iu_bo_enable_4, + pc_iu_bo_reset => pc_iu_bo_reset, + pc_iu_bo_unload => pc_iu_bo_unload, + pc_iu_bo_repair => pc_iu_bo_repair, + pc_iu_bo_shdata => pc_iu_bo_shdata, + pc_iu_bo_select => pc_iu_bo_select, + iu_pc_bo_fail => iu_pc_bo_fail, + iu_pc_bo_diagout => iu_pc_bo_diagout, + iu_pc_err_icache_parity => iu_pc_err_icache_parity, + iu_pc_err_icachedir_parity => iu_pc_err_icachedir_parity, + iu_pc_err_icachedir_multihit => iu_pc_err_icachedir_multihit, + iu_pc_err_ucode_illegal => iu_pc_err_ucode_illegal, + pc_iu_inj_icache_parity => pc_iu_inj_icache_parity, + pc_iu_inj_icachedir_parity => pc_iu_inj_icachedir_parity, + pc_iu_inj_icachedir_multihit => pc_iu_inj_icachedir_multihit, + pc_iu_trace_bus_enable => pc_iu_trace_bus_enable, + pc_iu_debug_mux1_ctrls => pc_iu_debug_mux1_ctrls, + pc_iu_debug_mux2_ctrls => pc_iu_debug_mux2_ctrls, + debug_data_in => debug_data_in, + trace_triggers_in => trace_triggers_in, + debug_data_out => debug_data_out, + trace_triggers_out => trace_triggers_out, + pc_iu_event_mux_ctrls => pc_iu_event_mux_ctrls, + pc_iu_event_count_mode => pc_iu_event_count_mode, + pc_iu_event_bus_enable => pc_iu_event_bus_enable, + iu_pc_event_data => iu_pc_event_data, + pc_iu_init_reset => pc_iu_init_reset, + gptr_scan_in => gptr_scan_in, + time_scan_in => time_scan_in, + repr_scan_in => repr_scan_in, + abst_scan_in => abst_scan_in, + func_scan_in => func_scan_in, + ccfg_scan_in => ccfg_scan_in, + bcfg_scan_in => bcfg_scan_in, + dcfg_scan_in => dcfg_scan_in, + regf_scan_in => regf_scan_in, + gptr_scan_out => gptr_scan_out, + time_scan_out => time_scan_out, + repr_scan_out => repr_scan_out, + abst_scan_out => abst_scan_out, + func_scan_out => func_scan_out, + ccfg_scan_out => ccfg_scan_out, + bcfg_scan_out => bcfg_scan_out, + dcfg_scan_out => dcfg_scan_out, + regf_scan_out => regf_scan_out, + iuq_mi_scan_out => iuq_mi_scan_out, + iuq_bp_scan_out => iuq_bp_scan_out, + slowspr_val_in => slowspr_val_in, + slowspr_rw_in => slowspr_rw_in, + slowspr_etid_in => slowspr_etid_in, + slowspr_addr_in => slowspr_addr_in, + slowspr_data_in => slowspr_data_in, + slowspr_done_in => slowspr_done_in, + slowspr_val_out => slowspr_val_out, + slowspr_rw_out => slowspr_rw_out, + slowspr_etid_out => slowspr_etid_out, + slowspr_addr_out => slowspr_addr_out, + slowspr_data_out => slowspr_data_out, + slowspr_done_out => slowspr_done_out, + xu_iu_run_thread => xu_iu_run_thread, + xu_iu_flush => xu_iu_l_flush, + xu_iu_iu0_flush_ifar0 => xu_iu_iu0_flush_ifar0, + xu_iu_iu0_flush_ifar1 => xu_iu_iu0_flush_ifar1, + xu_iu_iu0_flush_ifar2 => xu_iu_iu0_flush_ifar2, + xu_iu_iu0_flush_ifar3 => xu_iu_iu0_flush_ifar3, + xu_iu_flush_2ucode => xu_iu_flush_2ucode, + xu_iu_flush_2ucode_type => xu_iu_flush_2ucode_type, + xu_iu_msr_cm => xu_iu_msr_cm, + xu_iu_ex6_icbi_val => xu_iu_ex6_icbi_val, + xu_iu_ex6_icbi_addr => xu_iu_ex6_icbi_addr, + xu_iu_ici => xu_iu_ici, + iu_xu_request => iu_xu_request, + iu_xu_thread => iu_xu_thread, + iu_xu_ra => iu_xu_ra, + iu_xu_wimge => iu_xu_wimge, + iu_xu_userdef => iu_xu_userdef, + an_ac_reld_data_vld => an_ac_reld_data_vld, + an_ac_reld_core_tag => an_ac_reld_core_tag, + an_ac_reld_qw => an_ac_reld_qw, + an_ac_reld_data => an_ac_reld_data, + an_ac_reld_ecc_err => an_ac_reld_ecc_err, + an_ac_reld_ecc_err_ue => an_ac_reld_ecc_err_ue, + an_ac_back_inv => an_ac_back_inv, + an_ac_back_inv_addr => an_ac_back_inv_addr, + an_ac_back_inv_target_iiu_a=> an_ac_back_inv_target_iiu_a, + an_ac_back_inv_target_iiu_b=> an_ac_back_inv_target_iiu_b, + an_ac_icbi_ack => an_ac_icbi_ack, + an_ac_icbi_ack_thread => an_ac_icbi_ack_thread, + iu_mm_ierat_req => iu_mm_ierat_req, + iu_mm_ierat_epn => iu_mm_ierat_epn, + iu_mm_ierat_thdid => iu_mm_ierat_thdid, + iu_mm_ierat_state => iu_mm_ierat_state, + iu_mm_ierat_tid => iu_mm_ierat_tid, + iu_mm_ierat_flush => iu_mm_ierat_flush, + mm_iu_ierat_rel_val => mm_iu_ierat_rel_val, + mm_iu_ierat_rel_data => mm_iu_ierat_rel_data, + mm_iu_ierat_snoop_coming => mm_iu_ierat_snoop_coming, + mm_iu_ierat_snoop_val => mm_iu_ierat_snoop_val, + mm_iu_ierat_snoop_attr => mm_iu_ierat_snoop_attr, + mm_iu_ierat_snoop_vpn => mm_iu_ierat_snoop_vpn, + iu_mm_ierat_snoop_ack => iu_mm_ierat_snoop_ack, + mm_iu_ierat_pid0 => mm_iu_ierat_pid0, + mm_iu_ierat_pid1 => mm_iu_ierat_pid1, + mm_iu_ierat_pid2 => mm_iu_ierat_pid2, + mm_iu_ierat_pid3 => mm_iu_ierat_pid3, + mm_iu_ierat_mmucr0_0 => mm_iu_ierat_mmucr0_0, + mm_iu_ierat_mmucr0_1 => mm_iu_ierat_mmucr0_1, + mm_iu_ierat_mmucr0_2 => mm_iu_ierat_mmucr0_2, + mm_iu_ierat_mmucr0_3 => mm_iu_ierat_mmucr0_3, + iu_mm_ierat_mmucr0 => iu_mm_ierat_mmucr0, + iu_mm_ierat_mmucr0_we => iu_mm_ierat_mmucr0_we, + mm_iu_ierat_mmucr1 => mm_iu_ierat_mmucr1, + iu_mm_ierat_mmucr1 => iu_mm_ierat_mmucr1, + iu_mm_ierat_mmucr1_we => iu_mm_ierat_mmucr1_we, + iu_mm_lmq_empty => iu_mm_lmq_empty, + xu_iu_ex1_rb => xu_iu_ex1_rb, + xu_rf1_flush => xu_wl_rf1_flush, + xu_ex1_flush => xu_wl_ex1_flush, + xu_ex2_flush => xu_wl_ex2_flush, + xu_ex3_flush => xu_wl_ex3_flush, + xu_ex4_flush => xu_wl_ex4_flush, + xu_ex5_flush => xu_wl_ex5_flush, + xu_iu_ex4_rs_data => xu_iu_ex4_rs_data, + xu_iu_hid_mmu_mode => xu_iu_hid_mmu_mode, + xu_iu_msr_hv => xu_iu_msr_hv, + xu_iu_msr_is => xu_iu_msr_is, + xu_iu_msr_pr => xu_iu_msr_pr, + xu_iu_spr_ccr2_ifratsc => xu_iu_spr_ccr2_ifratsc, + xu_iu_spr_ccr2_ifrat => xu_iu_spr_ccr2_ifrat, + xu_iu_xucr4_mmu_mchk => xu_iu_xucr4_mmu_mchk, + xu_iu_rf1_val => xu_iu_rf1_val, + xu_iu_rf1_is_eratre => xu_iu_rf1_is_eratre, + xu_iu_rf1_is_eratsx => xu_iu_rf1_is_eratsx, + xu_iu_rf1_is_eratwe => xu_iu_rf1_is_eratwe, + xu_iu_rf1_is_eratilx => xu_iu_rf1_is_eratilx, + xu_iu_ex1_is_isync => xu_iu_ex1_is_isync, + xu_iu_ex1_is_csync => xu_iu_ex1_is_csync, + xu_iu_rf1_ws => xu_iu_rf1_ws, + xu_iu_rf1_t => xu_iu_rf1_t, + xu_iu_ex1_ra_entry => xu_iu_ex1_ra_entry, + xu_iu_ex1_rs_is => xu_iu_ex1_rs_is, + iu_xu_ex4_tlb_data => iu_xu_ex4_tlb_data, + iu_xu_ierat_ex3_par_err => iu_xu_ierat_ex3_par_err, + iu_xu_ierat_ex4_par_err => iu_xu_ierat_ex4_par_err, + iu_xu_ierat_ex2_flush_req => iu_xu_ierat_ex2_flush_req, + xu_iu_ex5_ifar => xu_iu_ex5_ifar, + xu_iu_ex5_tid => xu_iu_ex5_tid, + xu_iu_ex5_val => xu_iu_ex5_val, + xu_iu_ex5_br_update => xu_iu_ex5_br_update, + xu_iu_ex5_br_hist => xu_iu_ex5_br_hist, + xu_iu_ex5_br_taken => xu_iu_ex5_br_taken, + xu_iu_ex5_bclr => xu_iu_ex5_bclr, + xu_iu_ex5_getNIA => xu_iu_ex5_getNIA, + xu_iu_ex5_lk => xu_iu_ex5_lk, + xu_iu_ex5_bh => xu_iu_ex5_bh, + xu_iu_ex5_gshare => xu_iu_ex5_gshare, + pc_iu_ram_instr => pc_iu_ram_instr, + pc_iu_ram_instr_ext => pc_iu_ram_instr_ext, + pc_iu_ram_force_cmplt => pc_iu_ram_force_cmplt, + xu_iu_ram_issue => xu_iu_ram_issue, + xu_iu_ex6_pri => xu_iu_ex6_pri, + xu_iu_ex6_pri_val => xu_iu_ex6_pri_val, + xu_iu_raise_iss_pri => xu_iu_raise_iss_pri, + xu_iu_msr_gs => xu_iu_msr_gs, + xu_iu_ucode_restart => xu_iu_ucode_restart, + xu_iu_spr_xer0 => xu_iu_spr_xer0, + xu_iu_spr_xer1 => xu_iu_spr_xer1, + xu_iu_spr_xer2 => xu_iu_spr_xer2, + xu_iu_spr_xer3 => xu_iu_spr_xer3, + xu_iu_uc_flush_ifar0 => xu_iu_uc_flush_ifar0, + xu_iu_uc_flush_ifar1 => xu_iu_uc_flush_ifar1, + xu_iu_uc_flush_ifar2 => xu_iu_uc_flush_ifar2, + xu_iu_uc_flush_ifar3 => xu_iu_uc_flush_ifar3, + rtim_sl_thold_7 => rtim_sl_thold_7, + func_sl_thold_7 => func_sl_thold_7, + func_nsl_thold_7 => func_nsl_thold_7, + ary_nsl_thold_7 => ary_nsl_thold_7, + sg_7 => sg_7, + fce_7 => fce_7, + rtim_sl_thold_6 => rtim_sl_thold_6, + func_sl_thold_6 => func_sl_thold_6, + func_nsl_thold_6 => func_nsl_thold_6, + ary_nsl_thold_6 => ary_nsl_thold_6, + sg_6 => sg_6, + fce_6 => fce_6, + an_ac_scom_dch => an_ac_scom_dch, + an_ac_scom_cch => an_ac_scom_cch, + an_ac_checkstop => an_ac_checkstop, + an_ac_debug_stop => an_ac_debug_stop, + an_ac_pm_thread_stop => an_ac_pm_thread_stop, + an_ac_reset_1_complete => an_ac_reset_1_complete, + an_ac_reset_2_complete => an_ac_reset_2_complete, + an_ac_reset_3_complete => an_ac_reset_3_complete, + an_ac_reset_wd_complete => an_ac_reset_wd_complete, + an_ac_abist_start_test => an_ac_abist_start_test, + ac_rp_trace_to_perfcntr => ac_rp_trace_to_perfcntr, + rp_pc_scom_dch_q => rp_pc_scom_dch_q, + rp_pc_scom_cch_q => rp_pc_scom_cch_q, + rp_pc_checkstop_q => rp_pc_checkstop_q, + rp_pc_debug_stop_q => rp_pc_debug_stop_q, + rp_pc_pm_thread_stop_q => rp_pc_pm_thread_stop_q, + rp_pc_reset_1_complete_q => rp_pc_reset_1_complete_q, + rp_pc_reset_2_complete_q => rp_pc_reset_2_complete_q, + rp_pc_reset_3_complete_q => rp_pc_reset_3_complete_q, + rp_pc_reset_wd_complete_q => rp_pc_reset_wd_complete_q, + rp_pc_abist_start_test_q => rp_pc_abist_start_test_q, + rp_pc_trace_to_perfcntr_q => rp_pc_trace_to_perfcntr_q, + pc_rp_scom_dch => pc_rp_scom_dch, + pc_rp_scom_cch => pc_rp_scom_cch, + pc_rp_special_attn => pc_rp_special_attn, + pc_rp_checkstop => pc_rp_checkstop, + pc_rp_local_checkstop => pc_rp_local_checkstop, + pc_rp_recov_err => pc_rp_recov_err, + pc_rp_trace_error => pc_rp_trace_error, + pc_rp_event_bus_enable => pc_rp_event_bus_enable, + pc_rp_event_bus => pc_rp_event_bus, + pc_rp_fu_bypass_events => pc_rp_fu_bypass_events, + pc_rp_iu_bypass_events => pc_rp_iu_bypass_events, + pc_rp_mm_bypass_events => pc_rp_mm_bypass_events, + pc_rp_lsu_bypass_events => pc_rp_lsu_bypass_events, + pc_rp_pm_thread_running => pc_rp_pm_thread_running, + pc_rp_power_managed => pc_rp_power_managed, + pc_rp_rvwinkle_mode => pc_rp_rvwinkle_mode, + ac_an_scom_dch_q => ac_an_scom_dch_q, + ac_an_scom_cch_q => ac_an_scom_cch_q, + ac_an_special_attn_q => ac_an_special_attn_q, + ac_an_checkstop_q => ac_an_checkstop_q, + ac_an_local_checkstop_q => ac_an_local_checkstop_q, + ac_an_recov_err_q => ac_an_recov_err_q, + ac_an_trace_error_q => ac_an_trace_error_q, + rp_mm_event_bus_enable_q => rp_mm_event_bus_enable_q, + ac_an_event_bus_q => ac_an_event_bus_q, + ac_an_fu_bypass_events_q => ac_an_fu_bypass_events_q, + ac_an_iu_bypass_events_q => ac_an_iu_bypass_events_q, + ac_an_mm_bypass_events_q => ac_an_mm_bypass_events_q, + ac_an_lsu_bypass_events_q => ac_an_lsu_bypass_events_q, + ac_an_pm_thread_running_q => ac_an_pm_thread_running_q, + ac_an_power_managed_q => ac_an_power_managed_q, + ac_an_rvwinkle_mode_q => ac_an_rvwinkle_mode_q, + pc_func_scan_in => pc_func_scan_in, + pc_func_scan_in_q => pc_func_scan_in_q, + pc_func_scan_out => pc_func_scan_out, + pc_func_scan_out_q => pc_func_scan_out_q, + pc_bcfg_scan_in => pc_bcfg_scan_in, + pc_bcfg_scan_in_q => pc_bcfg_scan_in_q, + pc_dcfg_scan_in => pc_dcfg_scan_in, + pc_dcfg_scan_in_q => pc_dcfg_scan_in_q, + pc_bcfg_scan_out => pc_bcfg_scan_out, + pc_bcfg_scan_out_q => pc_bcfg_scan_out_q, + pc_ccfg_scan_out => pc_ccfg_scan_out, + pc_ccfg_scan_out_q => pc_ccfg_scan_out_q, + pc_dcfg_scan_out => pc_dcfg_scan_out, + pc_dcfg_scan_out_q => pc_dcfg_scan_out_q, + fu_abst_scan_in => fu_abst_scan_in, + fu_abst_scan_in_q => fu_abst_scan_in_q, + fu_abst_scan_out => fu_abst_scan_out, + fu_abst_scan_out_q => fu_abst_scan_out_q, + fu_ccfg_scan_out => fu_ccfg_scan_out, + fu_ccfg_scan_out_q => fu_ccfg_scan_out_q, + fu_bcfg_scan_out => fu_bcfg_scan_out, + fu_bcfg_scan_out_q => fu_bcfg_scan_out_q, + fu_dcfg_scan_out => fu_dcfg_scan_out, + fu_dcfg_scan_out_q => fu_dcfg_scan_out_q, + fu_func_scan_in => fu_func_scan_in, + fu_func_scan_in_q => fu_func_scan_in_q, + fu_func_scan_out => fu_func_scan_out, + fu_func_scan_out_q => fu_func_scan_out_q, + bx_abst_scan_in => bx_abst_scan_in, + bx_abst_scan_in_q => bx_abst_scan_in_q, + bx_abst_scan_out => bx_abst_scan_out, + bx_abst_scan_out_q => bx_abst_scan_out_q, + bx_func_scan_in => bx_func_scan_in, + bx_func_scan_in_q => bx_func_scan_in_q, + bx_func_scan_out => bx_func_scan_out, + bx_func_scan_out_q => bx_func_scan_out_q, + iu_func_scan_in_q => iu_func_scan_in_q, + iu_func_scan_out => iu_func_scan_out, + spare_func_scan_in => spare_func_scan_in, + spare_func_scan_out_q => spare_func_scan_out_q, + rp_abst_scan_in => rp_abst_scan_in, + rp_func_scan_in => rp_func_scan_in, + rp_abst_scan_out => rp_abst_scan_out, + rp_func_scan_out => rp_func_scan_out, + bg_an_ac_func_scan_sn => bg_an_ac_func_scan_sn, + bg_an_ac_abst_scan_sn => bg_an_ac_abst_scan_sn, + bg_an_ac_func_scan_sn_q => bg_an_ac_func_scan_sn_q, + bg_an_ac_abst_scan_sn_q => bg_an_ac_abst_scan_sn_q, + bg_ac_an_func_scan_ns => bg_ac_an_func_scan_ns, + bg_ac_an_abst_scan_ns => bg_ac_an_abst_scan_ns, + bg_ac_an_func_scan_ns_q => bg_ac_an_func_scan_ns_q, + bg_ac_an_abst_scan_ns_q => bg_ac_an_abst_scan_ns_q, + bg_pc_l1p_abist_di_0 => bg_pc_l1p_abist_di_0, + bg_pc_l1p_abist_g8t1p_renb_0 => bg_pc_l1p_abist_g8t1p_renb_0, + bg_pc_l1p_abist_g8t_bw_0 => bg_pc_l1p_abist_g8t_bw_0, + bg_pc_l1p_abist_g8t_bw_1 => bg_pc_l1p_abist_g8t_bw_1, + bg_pc_l1p_abist_g8t_dcomp => bg_pc_l1p_abist_g8t_dcomp, + bg_pc_l1p_abist_g8t_wenb => bg_pc_l1p_abist_g8t_wenb, + bg_pc_l1p_abist_raddr_0 => bg_pc_l1p_abist_raddr_0, + bg_pc_l1p_abist_waddr_0 => bg_pc_l1p_abist_waddr_0, + bg_pc_l1p_abist_wl128_comp_ena => bg_pc_l1p_abist_wl128_comp_ena, + bg_pc_l1p_abist_wl32_comp_ena => bg_pc_l1p_abist_wl32_comp_ena, + bg_pc_l1p_abist_di_0_q => bg_pc_l1p_abist_di_0_q, + bg_pc_l1p_abist_g8t1p_renb_0_q => bg_pc_l1p_abist_g8t1p_renb_0_q, + bg_pc_l1p_abist_g8t_bw_0_q => bg_pc_l1p_abist_g8t_bw_0_q, + bg_pc_l1p_abist_g8t_bw_1_q => bg_pc_l1p_abist_g8t_bw_1_q, + bg_pc_l1p_abist_g8t_dcomp_q=> bg_pc_l1p_abist_g8t_dcomp_q, + bg_pc_l1p_abist_g8t_wenb_q => bg_pc_l1p_abist_g8t_wenb_q, + bg_pc_l1p_abist_raddr_0_q => bg_pc_l1p_abist_raddr_0_q, + bg_pc_l1p_abist_waddr_0_q => bg_pc_l1p_abist_waddr_0_q, + bg_pc_l1p_abist_wl128_comp_ena_q => bg_pc_l1p_abist_wl128_comp_ena_q, + bg_pc_l1p_abist_wl32_comp_ena_q => bg_pc_l1p_abist_wl32_comp_ena_q, + bg_pc_l1p_gptr_sl_thold_3 => bg_pc_l1p_gptr_sl_thold_3, + bg_pc_l1p_time_sl_thold_3 => bg_pc_l1p_time_sl_thold_3, + bg_pc_l1p_repr_sl_thold_3 => bg_pc_l1p_repr_sl_thold_3, + bg_pc_l1p_abst_sl_thold_3 => bg_pc_l1p_abst_sl_thold_3, + bg_pc_l1p_func_sl_thold_3 => bg_pc_l1p_func_sl_thold_3, + bg_pc_l1p_func_slp_sl_thold_3 => bg_pc_l1p_func_slp_sl_thold_3, + bg_pc_l1p_bolt_sl_thold_3 => bg_pc_l1p_bolt_sl_thold_3, + bg_pc_l1p_ary_nsl_thold_3 => bg_pc_l1p_ary_nsl_thold_3, + bg_pc_l1p_sg_3 => bg_pc_l1p_sg_3, + bg_pc_l1p_fce_3 => bg_pc_l1p_fce_3, + bg_pc_l1p_bo_enable_3 => bg_pc_l1p_bo_enable_3, + bg_pc_l1p_gptr_sl_thold_2 => bg_pc_l1p_gptr_sl_thold_2, + bg_pc_l1p_time_sl_thold_2 => bg_pc_l1p_time_sl_thold_2, + bg_pc_l1p_repr_sl_thold_2 => bg_pc_l1p_repr_sl_thold_2, + bg_pc_l1p_abst_sl_thold_2 => bg_pc_l1p_abst_sl_thold_2, + bg_pc_l1p_func_sl_thold_2 => bg_pc_l1p_func_sl_thold_2, + bg_pc_l1p_func_slp_sl_thold_2 => bg_pc_l1p_func_slp_sl_thold_2, + bg_pc_l1p_bolt_sl_thold_2 => bg_pc_l1p_bolt_sl_thold_2, + bg_pc_l1p_ary_nsl_thold_2 => bg_pc_l1p_ary_nsl_thold_2, + bg_pc_l1p_sg_2 => bg_pc_l1p_sg_2, + bg_pc_l1p_fce_2 => bg_pc_l1p_fce_2, + bg_pc_l1p_bo_enable_2 => bg_pc_l1p_bo_enable_2, + bg_pc_bo_unload_iiu => bg_pc_bo_unload_iiu, + bg_pc_bo_load_iiu => bg_pc_bo_load_iiu, + bg_pc_bo_repair_iiu => bg_pc_bo_repair_iiu, + bg_pc_bo_reset_iiu => bg_pc_bo_reset_iiu, + bg_pc_bo_shdata_iiu => bg_pc_bo_shdata_iiu, + bg_pc_bo_select_iiu => bg_pc_bo_select_iiu, + bg_pc_l1p_ccflush_dc_iiu => bg_pc_l1p_ccflush_dc_iiu, + bg_pc_l1p_abist_ena_dc_iiu => bg_pc_l1p_abist_ena_dc_iiu, + bg_pc_l1p_abist_raw_dc_b_iiu => bg_pc_l1p_abist_raw_dc_b_iiu, + bg_pc_bo_unload_oiu => bg_pc_bo_unload_oiu, + bg_pc_bo_load_oiu => bg_pc_bo_load_oiu, + bg_pc_bo_repair_oiu => bg_pc_bo_repair_oiu, + bg_pc_bo_reset_oiu => bg_pc_bo_reset_oiu, + bg_pc_bo_shdata_oiu => bg_pc_bo_shdata_oiu, + bg_pc_bo_select_oiu => bg_pc_bo_select_oiu, + bg_pc_l1p_ccflush_dc_oiu => bg_pc_l1p_ccflush_dc_oiu, + bg_pc_l1p_abist_ena_dc_oiu => bg_pc_l1p_abist_ena_dc_oiu, + bg_pc_l1p_abist_raw_dc_b_oiu => bg_pc_l1p_abist_raw_dc_b_oiu, + ac_an_abist_done_dc_iiu => ac_an_abist_done_dc_iiu, + ac_an_psro_ringsig_iiu => ac_an_psro_ringsig_iiu, + mm_pc_bo_fail_iiu => mm_pc_bo_fail_iiu, + mm_pc_bo_diagout_iiu => mm_pc_bo_diagout_iiu, + mm_pc_event_data_iiu => mm_pc_event_data_iiu, + ac_an_abist_done_dc_oiu => ac_an_abist_done_dc_oiu, + ac_an_psro_ringsig_oiu => ac_an_psro_ringsig_oiu, + mm_pc_bo_fail_oiu => mm_pc_bo_fail_oiu, + mm_pc_bo_diagout_oiu => mm_pc_bo_diagout_oiu, + mm_pc_event_data_oiu => mm_pc_event_data_oiu, + bg_pc_bo_fail_iiu => bg_pc_bo_fail_iiu, + bg_pc_bo_diagout_iiu => bg_pc_bo_diagout_iiu, + bg_pc_bo_fail_oiu => bg_pc_bo_fail_oiu, + bg_pc_bo_diagout_oiu => bg_pc_bo_diagout_oiu, + an_ac_abist_mode_dc_iiu => an_ac_abist_mode_dc_iiu, + an_ac_ccenable_dc_iiu => an_ac_ccenable_dc_iiu, + an_ac_ccflush_dc_iiu => an_ac_ccflush_dc_iiu, + an_ac_gsd_test_enable_dc_iiu => an_ac_gsd_test_enable_dc_iiu, + an_ac_gsd_test_acmode_dc_iiu => an_ac_gsd_test_acmode_dc_iiu, + an_ac_lbist_ip_dc_iiu => an_ac_lbist_ip_dc_iiu, + an_ac_lbist_ac_mode_dc_iiu => an_ac_lbist_ac_mode_dc_iiu, + an_ac_malf_alert_iiu => an_ac_malf_alert_iiu, + an_ac_psro_enable_dc_iiu => an_ac_psro_enable_dc_iiu, + an_ac_scan_type_dc_iiu => an_ac_scan_type_dc_iiu, + an_ac_scom_sat_id_iiu => an_ac_scom_sat_id_iiu, + pc_mm_abist_dcomp_g6t_2r_iiu => pc_mm_abist_dcomp_g6t_2r_iiu, + pc_mm_abist_di_g6t_2r_iiu => pc_mm_abist_di_g6t_2r_iiu, + pc_mm_abist_di_0_iiu => pc_mm_abist_di_0_iiu, + pc_mm_abist_ena_dc_iiu => pc_mm_abist_ena_dc_iiu, + pc_mm_abist_g6t_r_wb_iiu => pc_mm_abist_g6t_r_wb_iiu, + pc_mm_abist_g8t_bw_0_iiu => pc_mm_abist_g8t_bw_0_iiu, + pc_mm_abist_g8t_bw_1_iiu => pc_mm_abist_g8t_bw_1_iiu, + pc_mm_abist_g8t_dcomp_iiu => pc_mm_abist_g8t_dcomp_iiu, + pc_mm_abist_g8t_wenb_iiu => pc_mm_abist_g8t_wenb_iiu, + pc_mm_abist_g8t1p_renb_0_iiu => pc_mm_abist_g8t1p_renb_0_iiu, + pc_mm_abist_raddr_0_iiu => pc_mm_abist_raddr_0_iiu, + pc_mm_abist_raw_dc_b_iiu => pc_mm_abist_raw_dc_b_iiu, + pc_mm_abist_waddr_0_iiu => pc_mm_abist_waddr_0_iiu, + pc_mm_abist_wl128_comp_ena_iiu => pc_mm_abist_wl128_comp_ena_iiu, + pc_mm_bo_enable_4_iiu => pc_mm_bo_enable_4_iiu, + pc_mm_bo_repair_iiu => pc_mm_bo_repair_iiu, + pc_mm_bo_reset_iiu => pc_mm_bo_reset_iiu, + pc_mm_bo_select_iiu => pc_mm_bo_select_iiu, + pc_mm_bo_shdata_iiu => pc_mm_bo_shdata_iiu, + pc_mm_bo_unload_iiu => pc_mm_bo_unload_iiu, + pc_mm_ccflush_dc_iiu => pc_mm_ccflush_dc_iiu, + pc_mm_debug_mux1_ctrls_iiu => pc_mm_debug_mux1_ctrls_iiu, + pc_mm_event_count_mode_iiu => pc_mm_event_count_mode_iiu, + pc_mm_event_mux_ctrls_iiu => pc_mm_event_mux_ctrls_iiu, + pc_mm_trace_bus_enable_iiu => pc_mm_trace_bus_enable_iiu, + an_ac_abist_mode_dc_oiu => an_ac_abist_mode_dc_oiu, + an_ac_ccenable_dc_oiu => an_ac_ccenable_dc_oiu, + an_ac_ccflush_dc_oiu => an_ac_ccflush_dc_oiu, + an_ac_gsd_test_enable_dc_oiu => an_ac_gsd_test_enable_dc_oiu, + an_ac_gsd_test_acmode_dc_oiu => an_ac_gsd_test_acmode_dc_oiu, + an_ac_lbist_ip_dc_oiu => an_ac_lbist_ip_dc_oiu, + an_ac_lbist_ac_mode_dc_oiu => an_ac_lbist_ac_mode_dc_oiu, + an_ac_malf_alert_oiu => an_ac_malf_alert_oiu, + an_ac_psro_enable_dc_oiu => an_ac_psro_enable_dc_oiu, + an_ac_scan_type_dc_oiu => an_ac_scan_type_dc_oiu, + an_ac_scom_sat_id_oiu => an_ac_scom_sat_id_oiu, + pc_mm_abist_dcomp_g6t_2r_oiu => pc_mm_abist_dcomp_g6t_2r_oiu, + pc_mm_abist_di_g6t_2r_oiu => pc_mm_abist_di_g6t_2r_oiu, + pc_mm_abist_di_0_oiu => pc_mm_abist_di_0_oiu, + pc_mm_abist_ena_dc_oiu => pc_mm_abist_ena_dc_oiu, + pc_mm_abist_g6t_r_wb_oiu => pc_mm_abist_g6t_r_wb_oiu, + pc_mm_abist_g8t_bw_0_oiu => pc_mm_abist_g8t_bw_0_oiu, + pc_mm_abist_g8t_bw_1_oiu => pc_mm_abist_g8t_bw_1_oiu, + pc_mm_abist_g8t_dcomp_oiu => pc_mm_abist_g8t_dcomp_oiu, + pc_mm_abist_g8t_wenb_oiu => pc_mm_abist_g8t_wenb_oiu, + pc_mm_abist_g8t1p_renb_0_oiu => pc_mm_abist_g8t1p_renb_0_oiu, + pc_mm_abist_raddr_0_oiu => pc_mm_abist_raddr_0_oiu, + pc_mm_abist_raw_dc_b_oiu => pc_mm_abist_raw_dc_b_oiu, + pc_mm_abist_waddr_0_oiu => pc_mm_abist_waddr_0_oiu, + pc_mm_abist_wl128_comp_ena_oiu => pc_mm_abist_wl128_comp_ena_oiu, + pc_mm_abst_sl_thold_3_oiu => pc_mm_abst_sl_thold_3_oiu, + pc_mm_abst_slp_sl_thold_3_oiu => pc_mm_abst_slp_sl_thold_3_oiu, + pc_mm_ary_nsl_thold_3_oiu => pc_mm_ary_nsl_thold_3_oiu, + pc_mm_ary_slp_nsl_thold_3_oiu => pc_mm_ary_slp_nsl_thold_3_oiu, + pc_mm_bo_enable_3_oiu => pc_mm_bo_enable_3_oiu, + pc_mm_bo_repair_oiu => pc_mm_bo_repair_oiu, + pc_mm_bo_reset_oiu => pc_mm_bo_reset_oiu, + pc_mm_bo_select_oiu => pc_mm_bo_select_oiu, + pc_mm_bo_shdata_oiu => pc_mm_bo_shdata_oiu, + pc_mm_bo_unload_oiu => pc_mm_bo_unload_oiu, + pc_mm_bolt_sl_thold_3_oiu => pc_mm_bolt_sl_thold_3_oiu, + pc_mm_ccflush_dc_oiu => pc_mm_ccflush_dc_oiu, + pc_mm_cfg_sl_thold_3_oiu => pc_mm_cfg_sl_thold_3_oiu, + pc_mm_cfg_slp_sl_thold_3_oiu => pc_mm_cfg_slp_sl_thold_3_oiu, + pc_mm_debug_mux1_ctrls_oiu => pc_mm_debug_mux1_ctrls_oiu, + pc_mm_event_count_mode_oiu => pc_mm_event_count_mode_oiu, + pc_mm_event_mux_ctrls_oiu => pc_mm_event_mux_ctrls_oiu, + pc_mm_fce_3_oiu => pc_mm_fce_3_oiu, + pc_mm_func_nsl_thold_3_oiu => pc_mm_func_nsl_thold_3_oiu, + pc_mm_func_sl_thold_3_oiu => pc_mm_func_sl_thold_3_oiu, + pc_mm_func_slp_nsl_thold_3_oiu => pc_mm_func_slp_nsl_thold_3_oiu, + pc_mm_func_slp_sl_thold_3_oiu => pc_mm_func_slp_sl_thold_3_oiu, + pc_mm_gptr_sl_thold_3_oiu => pc_mm_gptr_sl_thold_3_oiu, + pc_mm_repr_sl_thold_3_oiu => pc_mm_repr_sl_thold_3_oiu, + pc_mm_sg_3_oiu => pc_mm_sg_3_oiu, + pc_mm_time_sl_thold_3_oiu => pc_mm_time_sl_thold_3_oiu, + pc_mm_trace_bus_enable_oiu => pc_mm_trace_bus_enable_oiu, + an_ac_back_inv_oiu => an_ac_back_inv_oiu, + an_ac_back_inv_addr_oiu => an_ac_back_inv_addr_oiu, + an_ac_back_inv_target_bit1_oiu => an_ac_back_inv_target_bit1_oiu, + an_ac_back_inv_target_bit3_oiu => an_ac_back_inv_target_bit3_oiu, + an_ac_back_inv_target_bit4_oiu => an_ac_back_inv_target_bit4_oiu, + an_ac_atpg_en_dc_oiu => an_ac_atpg_en_dc_oiu, + an_ac_lbist_ary_wrt_thru_dc_oiu => an_ac_lbist_ary_wrt_thru_dc_oiu, + an_ac_lbist_en_dc_oiu => an_ac_lbist_en_dc_oiu, + an_ac_scan_diag_dc_oiu => an_ac_scan_diag_dc_oiu, + an_ac_scan_dis_dc_b_oiu => an_ac_scan_dis_dc_b_oiu, + an_ac_grffence_en_dc_oiu => an_ac_grffence_en_dc_oiu, + an_ac_sync_ack => an_ac_sync_ack, + mm_iu_barrier_done => mm_iu_barrier_done, + an_ac_scan_dis_dc_b_oif => an_ac_scan_dis_dc_b_oif, + an_ac_back_inv_oif => an_ac_back_inv_oif, + an_ac_back_inv_target_oif => an_ac_back_inv_target_oif, + an_ac_sync_ack_oif => an_ac_sync_ack_oif, + mm_iu_barrier_done_oif => mm_iu_barrier_done_oif, + pc_iu_sg_2 => pc_iu_sg_2, + pc_iu_func_sl_thold_2 => pc_iu_func_sl_thold_2, + clkoff_b => clkoff_b, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + fiss_dbg_data => fiss_dbg_data, + fdep_dbg_data => fdep_dbg_data_pt_out, + ib_dbg_data => ib_dbg_data, + fu_iss_dbg_data => fu_iss_dbg_data, + axu_dbg_data_t0 => axu_dbg_data_t0, + axu_dbg_data_t1 => axu_dbg_data_t1, + axu_dbg_data_t2 => axu_dbg_data_t2, + axu_dbg_data_t3 => axu_dbg_data_t3, + ib_perf_event_t0 => ib_perf_event_t0, + ib_perf_event_t1 => ib_perf_event_t1, + ib_perf_event_t2 => ib_perf_event_t2, + ib_perf_event_t3 => ib_perf_event_t3, + fdep_perf_event_t0 => fdep_perf_event_pt_out_t0, + fdep_perf_event_t1 => fdep_perf_event_pt_out_t1, + fdep_perf_event_t2 => fdep_perf_event_pt_out_t2, + fdep_perf_event_t3 => fdep_perf_event_pt_out_t3, + fiss_perf_event_t0 => fiss_perf_event_t0, + fiss_perf_event_t1 => fiss_perf_event_t1, + fiss_perf_event_t2 => fiss_perf_event_t2, + fiss_perf_event_t3 => fiss_perf_event_t3, + ib_ic_empty => ib_ic_empty, + ib_ic_below_water => ib_ic_below_water, + ib_ic_iu5_redirect_tid => ib_ic_iu5_redirect_tid, + bp_ib_iu4_t0_val => bp_ib_iu4_t0_val, + bp_ib_iu4_t1_val => bp_ib_iu4_t1_val, + bp_ib_iu4_t2_val => bp_ib_iu4_t2_val, + bp_ib_iu4_t3_val => bp_ib_iu4_t3_val, + bp_ib_iu4_ifar_t0 => bp_ib_iu4_ifar_t0, + bp_ib_iu3_0_instr_t0 => bp_ib_iu3_0_instr_t0, + bp_ib_iu4_0_instr_t0 => bp_ib_iu4_0_instr_t0, + bp_ib_iu4_1_instr_t0 => bp_ib_iu4_1_instr_t0, + bp_ib_iu4_2_instr_t0 => bp_ib_iu4_2_instr_t0, + bp_ib_iu4_3_instr_t0 => bp_ib_iu4_3_instr_t0, + bp_ib_iu4_ifar_t1 => bp_ib_iu4_ifar_t1, + bp_ib_iu3_0_instr_t1 => bp_ib_iu3_0_instr_t1, + bp_ib_iu4_0_instr_t1 => bp_ib_iu4_0_instr_t1, + bp_ib_iu4_1_instr_t1 => bp_ib_iu4_1_instr_t1, + bp_ib_iu4_2_instr_t1 => bp_ib_iu4_2_instr_t1, + bp_ib_iu4_3_instr_t1 => bp_ib_iu4_3_instr_t1, + bp_ib_iu4_ifar_t2 => bp_ib_iu4_ifar_t2, + bp_ib_iu3_0_instr_t2 => bp_ib_iu3_0_instr_t2, + bp_ib_iu4_0_instr_t2 => bp_ib_iu4_0_instr_t2, + bp_ib_iu4_1_instr_t2 => bp_ib_iu4_1_instr_t2, + bp_ib_iu4_2_instr_t2 => bp_ib_iu4_2_instr_t2, + bp_ib_iu4_3_instr_t2 => bp_ib_iu4_3_instr_t2, + bp_ib_iu4_ifar_t3 => bp_ib_iu4_ifar_t3, + bp_ib_iu3_0_instr_t3 => bp_ib_iu3_0_instr_t3, + bp_ib_iu4_0_instr_t3 => bp_ib_iu4_0_instr_t3, + bp_ib_iu4_1_instr_t3 => bp_ib_iu4_1_instr_t3, + bp_ib_iu4_2_instr_t3 => bp_ib_iu4_2_instr_t3, + bp_ib_iu4_3_instr_t3 => bp_ib_iu4_3_instr_t3, + uc_ib_iu4_val => uc_ib_iu4_val, + uc_ib_iu4_ifar_t0 => uc_ib_iu4_ifar_t0, + uc_ib_iu4_instr_t0 => uc_ib_iu4_instr_t0, + uc_ib_iu4_ifar_t1 => uc_ib_iu4_ifar_t1, + uc_ib_iu4_instr_t1 => uc_ib_iu4_instr_t1, + uc_ib_iu4_ifar_t2 => uc_ib_iu4_ifar_t2, + uc_ib_iu4_instr_t2 => uc_ib_iu4_instr_t2, + uc_ib_iu4_ifar_t3 => uc_ib_iu4_ifar_t3, + uc_ib_iu4_instr_t3 => uc_ib_iu4_instr_t3, + rm_ib_iu4_val => rm_ib_iu4_val, + rm_ib_iu4_force_ram_t0 => rm_ib_iu4_force_ram_t0, + rm_ib_iu4_instr_t0 => rm_ib_iu4_instr_t0, + rm_ib_iu4_force_ram_t1 => rm_ib_iu4_force_ram_t1, + rm_ib_iu4_instr_t1 => rm_ib_iu4_instr_t1, + rm_ib_iu4_force_ram_t2 => rm_ib_iu4_force_ram_t2, + rm_ib_iu4_instr_t2 => rm_ib_iu4_instr_t2, + rm_ib_iu4_force_ram_t3 => rm_ib_iu4_force_ram_t3, + rm_ib_iu4_instr_t3 => rm_ib_iu4_instr_t3, + iu_au_config_iucr_t0 => iu_au_config_iucr_t0, + iu_au_config_iucr_t1 => iu_au_config_iucr_t1, + iu_au_config_iucr_t2 => iu_au_config_iucr_t2, + iu_au_config_iucr_t3 => iu_au_config_iucr_t3, + spr_issue_high_mask => spr_issue_high_mask, + spr_issue_med_mask => spr_issue_med_mask, + spr_fiss_count0_max => spr_fiss_count0_max, + spr_fiss_count1_max => spr_fiss_count1_max, + spr_fiss_count2_max => spr_fiss_count2_max, + spr_fiss_count3_max => spr_fiss_count3_max, + spr_fiss_pri_rand => spr_fiss_pri_rand, + spr_fiss_pri_rand_always => spr_fiss_pri_rand_always, + spr_fiss_pri_rand_flush => spr_fiss_pri_rand_flush, + spr_dec_mask_t0 => spr_dec_mask_pt_in_t0, + spr_dec_mask_t1 => spr_dec_mask_pt_in_t1, + spr_dec_mask_t2 => spr_dec_mask_pt_in_t2, + spr_dec_mask_t3 => spr_dec_mask_pt_in_t3, + spr_dec_match_t0 => spr_dec_match_t0, + spr_dec_match_t1 => spr_dec_match_t1, + spr_dec_match_t2 => spr_dec_match_t2, + spr_dec_match_t3 => spr_dec_match_t3, + spr_fdep_ll_hold_t0 => spr_fdep_ll_hold_t0, + spr_fdep_ll_hold_t1 => spr_fdep_ll_hold_t1, + spr_fdep_ll_hold_t2 => spr_fdep_ll_hold_t2, + spr_fdep_ll_hold_t3 => spr_fdep_ll_hold_t3, + ic_fdep_load_quiesce => ic_fdep_load_quiesce, + ic_fdep_icbi_ack => ic_fdep_icbi_ack, + fiss_uc_is2_ucode_vld => fiss_uc_is2_ucode_vld, + fiss_uc_is2_tid => fiss_uc_is2_tid, + fiss_uc_is2_instr => fiss_uc_is2_instr, + fiss_uc_is2_2ucode => fiss_uc_is2_2ucode, + fiss_uc_is2_2ucode_type => fiss_uc_is2_2ucode_type, + uc_flush_tid => uc_flush_tid +); +iuq_ib_buff_wrap0 : entity work.iuq_ib_buff_wrap +generic map(expand_type => expand_type, + uc_ifar => uc_ifar) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_iu_func_sl_thold_2 => pc_iu_func_sl_thold_2, + pc_iu_sg_2 => pc_iu_sg_2, + clkoff_b => clkoff_b, + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b_oif, + tc_ac_ccflush_dc => tc_ac_ccflush_dc, + delay_lclkr => delay_lclkr(5 to 8), + mpw1_b => mpw1_b(5 to 8), + iuq_b0_scan_in => iuq_b0_scan_in, + iuq_b0_scan_out => iuq_b0_scan_out, + iuq_b1_scan_in => iuq_b1_scan_in, + iuq_b1_scan_out => iuq_b1_scan_out, + iuq_b2_scan_in => iuq_b2_scan_in, + iuq_b2_scan_out => iuq_b2_scan_out, + iuq_b3_scan_in => iuq_b3_scan_in, + iuq_b3_scan_out => iuq_b3_scan_out, + + spr_dec_mask_pt_in_t0 => spr_dec_mask_pt_in_t0, + spr_dec_mask_pt_in_t1 => spr_dec_mask_pt_in_t1, + spr_dec_mask_pt_in_t2 => spr_dec_mask_pt_in_t2, + spr_dec_mask_pt_in_t3 => spr_dec_mask_pt_in_t3, + spr_dec_mask_pt_out_t0 => spr_dec_mask_pt_out_t0, + spr_dec_mask_pt_out_t1 => spr_dec_mask_pt_out_t1, + spr_dec_mask_pt_out_t2 => spr_dec_mask_pt_out_t2, + spr_dec_mask_pt_out_t3 => spr_dec_mask_pt_out_t3, + fdep_dbg_data_pt_in => fdep_dbg_data_pt_in, + fdep_dbg_data_pt_out => fdep_dbg_data_pt_out, + fdep_perf_event_pt_in_t0 => fdep_perf_event_pt_in_t0, + fdep_perf_event_pt_in_t1 => fdep_perf_event_pt_in_t1, + fdep_perf_event_pt_in_t2 => fdep_perf_event_pt_in_t2, + fdep_perf_event_pt_in_t3 => fdep_perf_event_pt_in_t3, + fdep_perf_event_pt_out_t0 => fdep_perf_event_pt_out_t0, + fdep_perf_event_pt_out_t1 => fdep_perf_event_pt_out_t1, + fdep_perf_event_pt_out_t2 => fdep_perf_event_pt_out_t2, + fdep_perf_event_pt_out_t3 => fdep_perf_event_pt_out_t3, + + pc_iu_trace_bus_enable => pc_iu_trace_bus_enable, + pc_iu_event_bus_enable => pc_iu_event_bus_enable, + ib_dbg_data => ib_dbg_data, + ib_perf_event_t0 => ib_perf_event_t0, + ib_perf_event_t1 => ib_perf_event_t1, + ib_perf_event_t2 => ib_perf_event_t2, + ib_perf_event_t3 => ib_perf_event_t3, + xu_iu_flush => xu_iu_u_flush, + uc_flush_tid => uc_flush_tid, + fdec_ibuf_stall_t0 => fdec_ibuf_stall_t0, + fdec_ibuf_stall_t1 => fdec_ibuf_stall_t1, + fdec_ibuf_stall_t2 => fdec_ibuf_stall_t2, + fdec_ibuf_stall_t3 => fdec_ibuf_stall_t3, + ib_ic_below_water => ib_ic_below_water, + ib_ic_empty => ib_ic_empty, + bp_ib_iu4_t0_val => bp_ib_iu4_t0_val, + bp_ib_iu4_t1_val => bp_ib_iu4_t1_val, + bp_ib_iu4_t2_val => bp_ib_iu4_t2_val, + bp_ib_iu4_t3_val => bp_ib_iu4_t3_val, + bp_ib_iu4_ifar_t0 => bp_ib_iu4_ifar_t0, + bp_ib_iu3_0_instr_t0 => bp_ib_iu3_0_instr_t0, + bp_ib_iu4_0_instr_t0 => bp_ib_iu4_0_instr_t0, + bp_ib_iu4_1_instr_t0 => bp_ib_iu4_1_instr_t0, + bp_ib_iu4_2_instr_t0 => bp_ib_iu4_2_instr_t0, + bp_ib_iu4_3_instr_t0 => bp_ib_iu4_3_instr_t0, + bp_ib_iu4_ifar_t1 => bp_ib_iu4_ifar_t1, + bp_ib_iu3_0_instr_t1 => bp_ib_iu3_0_instr_t1, + bp_ib_iu4_0_instr_t1 => bp_ib_iu4_0_instr_t1, + bp_ib_iu4_1_instr_t1 => bp_ib_iu4_1_instr_t1, + bp_ib_iu4_2_instr_t1 => bp_ib_iu4_2_instr_t1, + bp_ib_iu4_3_instr_t1 => bp_ib_iu4_3_instr_t1, + bp_ib_iu4_ifar_t2 => bp_ib_iu4_ifar_t2, + bp_ib_iu3_0_instr_t2 => bp_ib_iu3_0_instr_t2, + bp_ib_iu4_0_instr_t2 => bp_ib_iu4_0_instr_t2, + bp_ib_iu4_1_instr_t2 => bp_ib_iu4_1_instr_t2, + bp_ib_iu4_2_instr_t2 => bp_ib_iu4_2_instr_t2, + bp_ib_iu4_3_instr_t2 => bp_ib_iu4_3_instr_t2, + bp_ib_iu4_ifar_t3 => bp_ib_iu4_ifar_t3, + bp_ib_iu3_0_instr_t3 => bp_ib_iu3_0_instr_t3, + bp_ib_iu4_0_instr_t3 => bp_ib_iu4_0_instr_t3, + bp_ib_iu4_1_instr_t3 => bp_ib_iu4_1_instr_t3, + bp_ib_iu4_2_instr_t3 => bp_ib_iu4_2_instr_t3, + bp_ib_iu4_3_instr_t3 => bp_ib_iu4_3_instr_t3, + uc_ib_iu4_val => uc_ib_iu4_val, + uc_ib_iu4_ifar_t0 => uc_ib_iu4_ifar_t0, + uc_ib_iu4_instr_t0 => uc_ib_iu4_instr_t0, + uc_ib_iu4_ifar_t1 => uc_ib_iu4_ifar_t1, + uc_ib_iu4_instr_t1 => uc_ib_iu4_instr_t1, + uc_ib_iu4_ifar_t2 => uc_ib_iu4_ifar_t2, + uc_ib_iu4_instr_t2 => uc_ib_iu4_instr_t2, + uc_ib_iu4_ifar_t3 => uc_ib_iu4_ifar_t3, + uc_ib_iu4_instr_t3 => uc_ib_iu4_instr_t3, + rm_ib_iu4_val => rm_ib_iu4_val, + rm_ib_iu4_force_ram_t0 => rm_ib_iu4_force_ram_t0, + rm_ib_iu4_instr_t0 => rm_ib_iu4_instr_t0, + rm_ib_iu4_force_ram_t1 => rm_ib_iu4_force_ram_t1, + rm_ib_iu4_instr_t1 => rm_ib_iu4_instr_t1, + rm_ib_iu4_force_ram_t2 => rm_ib_iu4_force_ram_t2, + rm_ib_iu4_instr_t2 => rm_ib_iu4_instr_t2, + rm_ib_iu4_force_ram_t3 => rm_ib_iu4_force_ram_t3, + rm_ib_iu4_instr_t3 => rm_ib_iu4_instr_t3, + ib_ic_iu5_redirect_tid => ib_ic_iu5_redirect_tid, + iu_au_ib1_instr_vld_t0 => iu_au_ib1_instr_vld_t0, + iu_au_ib1_instr_vld_t1 => iu_au_ib1_instr_vld_t1, + iu_au_ib1_instr_vld_t2 => iu_au_ib1_instr_vld_t2, + iu_au_ib1_instr_vld_t3 => iu_au_ib1_instr_vld_t3, + iu_au_ib1_ifar_t0 => iu_au_ib1_ifar_t0, + iu_au_ib1_ifar_t1 => iu_au_ib1_ifar_t1, + iu_au_ib1_ifar_t2 => iu_au_ib1_ifar_t2, + iu_au_ib1_ifar_t3 => iu_au_ib1_ifar_t3, + iu_au_ib1_data_t0 => iu_au_ib1_data_t0, + iu_au_ib1_data_t1 => iu_au_ib1_data_t1, + iu_au_ib1_data_t2 => iu_au_ib1_data_t2, + iu_au_ib1_data_t3 => iu_au_ib1_data_t3 +); +iuq_slice_wrap0 : entity work.iuq_slice_wrap +generic map(expand_type => expand_type, + fpr_addr_width => fpr_addr_width, + regmode => regmode, + a2mode => a2mode, + lmq_entries => lmq_entries) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_iu_func_sl_thold_2 => pc_iu_func_sl_thold_2, + pc_iu_sg_2 => pc_iu_sg_2, + clkoff_b => clkoff_b, + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b_oif, + tc_ac_ccflush_dc => tc_ac_ccflush_dc, + delay_lclkr => delay_lclkr(9 to 14), + mpw1_b => mpw1_b(9 to 14), + iuq_s0_scan_in => iuq_s0_scan_in, + iuq_s0_scan_out => iuq_s0_scan_out, + iuq_s1_scan_in => iuq_s1_scan_in, + iuq_s1_scan_out => iuq_s1_scan_out, + iuq_s2_scan_in => iuq_s2_scan_in, + iuq_s2_scan_out => iuq_s2_scan_out, + iuq_s3_scan_in => iuq_s3_scan_in, + iuq_s3_scan_out => iuq_s3_scan_out, + pc_iu_ram_mode => pc_iu_ram_mode, + pc_iu_ram_thread => pc_iu_ram_thread, + pc_iu_trace_bus_enable => pc_iu_trace_bus_enable, + pc_iu_event_bus_enable => pc_iu_event_bus_enable, + fdep_dbg_data => fdep_dbg_data_pt_in, + fdep_perf_event_t0 => fdep_perf_event_pt_in_t0, + fdep_perf_event_t1 => fdep_perf_event_pt_in_t1, + fdep_perf_event_t2 => fdep_perf_event_pt_in_t2, + fdep_perf_event_t3 => fdep_perf_event_pt_in_t3, + iu_au_config_iucr_t0 => iu_au_config_iucr_t0, + iu_au_config_iucr_t1 => iu_au_config_iucr_t1, + iu_au_config_iucr_t2 => iu_au_config_iucr_t2, + iu_au_config_iucr_t3 => iu_au_config_iucr_t3, + spr_dec_mask_t0 => spr_dec_mask_pt_out_t0, + spr_dec_mask_t1 => spr_dec_mask_pt_out_t1, + spr_dec_mask_t2 => spr_dec_mask_pt_out_t2, + spr_dec_mask_t3 => spr_dec_mask_pt_out_t3, + spr_dec_match_t0 => spr_dec_match_t0, + spr_dec_match_t1 => spr_dec_match_t1, + spr_dec_match_t2 => spr_dec_match_t2, + spr_dec_match_t3 => spr_dec_match_t3, + uc_flush_tid => uc_flush_tid, + xu_iu_flush => xu_iu_u_flush, + xu_rf1_flush => xu_wu_rf1_flush, + xu_ex1_flush => xu_wu_ex1_flush, + xu_ex2_flush => xu_wu_ex2_flush, + xu_ex3_flush => xu_wu_ex3_flush, + xu_ex4_flush => xu_wu_ex4_flush, + xu_ex5_flush => xu_wu_ex5_flush, + fdec_ibuf_stall_t0 => fdec_ibuf_stall_t0, + fdec_ibuf_stall_t1 => fdec_ibuf_stall_t1, + fdec_ibuf_stall_t2 => fdec_ibuf_stall_t2, + fdec_ibuf_stall_t3 => fdec_ibuf_stall_t3, + iu_au_ib1_instr_vld_t0 => iu_au_ib1_instr_vld_t0, + iu_au_ib1_instr_vld_t1 => iu_au_ib1_instr_vld_t1, + iu_au_ib1_instr_vld_t2 => iu_au_ib1_instr_vld_t2, + iu_au_ib1_instr_vld_t3 => iu_au_ib1_instr_vld_t3, + iu_au_ib1_ifar_t0 => iu_au_ib1_ifar_t0, + iu_au_ib1_ifar_t1 => iu_au_ib1_ifar_t1, + iu_au_ib1_ifar_t2 => iu_au_ib1_ifar_t2, + iu_au_ib1_ifar_t3 => iu_au_ib1_ifar_t3, + iu_au_ib1_data_t0 => iu_au_ib1_data_t0, + iu_au_ib1_data_t1 => iu_au_ib1_data_t1, + iu_au_ib1_data_t2 => iu_au_ib1_data_t2, + iu_au_ib1_data_t3 => iu_au_ib1_data_t3, + xu_iu_ucode_restart => xu_iu_ucode_restart, + xu_iu_slowspr_done => xu_iu_slowspr_done, + xu_iu_multdiv_done => xu_iu_multdiv_done, + xu_iu_ex4_loadmiss_tid => xu_iu_ex4_loadmiss_tid, + xu_iu_ex4_loadmiss_qentry => xu_iu_ex4_loadmiss_qentry, + xu_iu_ex4_loadmiss_target => xu_iu_ex4_loadmiss_target, + xu_iu_ex4_loadmiss_target_type => xu_iu_ex4_loadmiss_target_type, + xu_iu_ex5_loadmiss_tid => xu_iu_ex5_loadmiss_tid, + xu_iu_ex5_loadmiss_qentry => xu_iu_ex5_loadmiss_qentry, + xu_iu_ex5_loadmiss_target => xu_iu_ex5_loadmiss_target(1 to 6), + xu_iu_ex5_loadmiss_target_type => xu_iu_ex5_loadmiss_target_type(0 to 0), + xu_iu_complete_tid => xu_iu_complete_tid, + xu_iu_complete_qentry => xu_iu_complete_qentry, + xu_iu_complete_target_type => xu_iu_complete_target_type, + ic_fdep_load_quiesce => ic_fdep_load_quiesce, + iu_xu_quiesce => iu_xu_quiesce, + xu_iu_membar_tid => xu_iu_membar_tid, + xu_iu_set_barr_tid => xu_iu_set_barr_tid, + xu_iu_larx_done_tid => xu_iu_larx_done_tid, + an_ac_sync_ack => an_ac_sync_ack_oif, + ic_fdep_icbi_ack => ic_fdep_icbi_ack, + an_ac_stcx_complete => an_ac_stcx_complete, + mm_iu_barrier_done => mm_iu_barrier_done_oif, + spr_fdep_ll_hold_t0 => spr_fdep_ll_hold_t0, + spr_fdep_ll_hold_t1 => spr_fdep_ll_hold_t1, + spr_fdep_ll_hold_t2 => spr_fdep_ll_hold_t2, + spr_fdep_ll_hold_t3 => spr_fdep_ll_hold_t3, + xu_iu_spr_ccr2_en_dcr => xu_iu_spr_ccr2_en_dcr, + xu_iu_single_instr_mode => xu_iu_single_instr_mode, + fu_iu_uc_special => fu_iu_uc_special, + iu_fu_ex2_n_flush => iu_fu_ex2_n_flush, + axu_dbg_data_t0 => axu_dbg_data_t0, + axu_dbg_data_t1 => axu_dbg_data_t1, + axu_dbg_data_t2 => axu_dbg_data_t2, + axu_dbg_data_t3 => axu_dbg_data_t3, + iuq_fi_scan_in => iuq_fi_scan_in, + iuq_fi_scan_out => iuq_fi_scan_out, + fiss_dbg_data => fiss_dbg_data, + fiss_perf_event_t0 => fiss_perf_event_t0, + fiss_perf_event_t1 => fiss_perf_event_t1, + fiss_perf_event_t2 => fiss_perf_event_t2, + fiss_perf_event_t3 => fiss_perf_event_t3, + xu_iu_need_hole => xu_iu_need_hole, + xu_iu_xucr0_rel => xu_iu_xucr0_rel, + an_ac_reld_data_vld_clone => an_ac_reld_data_vld_clone, + an_ac_reld_core_tag_clone => an_ac_reld_core_tag_clone(1 to 4), + an_ac_reld_ditc_clone => an_ac_reld_ditc_clone, + an_ac_reld_data_coming_clone => an_ac_reld_data_coming_clone, + an_ac_back_inv => an_ac_back_inv_oif, + an_ac_back_inv_target => an_ac_back_inv_target_oif, + fiss_uc_is2_ucode_vld => fiss_uc_is2_ucode_vld, + spr_issue_high_mask => spr_issue_high_mask, + spr_issue_med_mask => spr_issue_med_mask, + spr_fiss_count0_max => spr_fiss_count0_max, + spr_fiss_count1_max => spr_fiss_count1_max, + spr_fiss_count2_max => spr_fiss_count2_max, + spr_fiss_count3_max => spr_fiss_count3_max, + spr_fiss_pri_rand => spr_fiss_pri_rand, + spr_fiss_pri_rand_always => spr_fiss_pri_rand_always, + spr_fiss_pri_rand_flush => spr_fiss_pri_rand_flush, + xu_iu_ex5_ppc_cpl => xu_iu_ex5_ppc_cpl, + iu_xu_is2_vld_internal => iu_xu_is2_vld_internal, + iu_xu_is2_tid_internal => iu_xu_is2_tid_internal, + iu_xu_is2_instr_internal => iu_xu_is2_instr_internal, + iu_xu_is2_ta_vld => iu_xu_is2_ta_vld, + iu_xu_is2_ta => iu_xu_is2_ta, + iu_xu_is2_s1_vld => iu_xu_is2_s1_vld, + iu_xu_is2_s1 => iu_xu_is2_s1, + iu_xu_is2_s2_vld => iu_xu_is2_s2_vld, + iu_xu_is2_s2 => iu_xu_is2_s2, + iu_xu_is2_s3_vld => iu_xu_is2_s3_vld, + iu_xu_is2_s3 => iu_xu_is2_s3, + iu_xu_is2_pred_update_internal => iu_xu_is2_pred_update_internal, + iu_xu_is2_pred_taken_cnt_internal => iu_xu_is2_pred_taken_cnt_internal, + iu_xu_is2_gshare => iu_xu_is2_gshare, + iu_xu_is2_ifar_internal => iu_xu_is2_ifar_internal, + iu_xu_is2_error_internal => iu_xu_is2_error_internal, + iu_xu_is2_is_ucode => iu_xu_is2_is_ucode, + iu_xu_is2_axu_ld_or_st => iu_xu_is2_axu_ld_or_st, + iu_xu_is2_axu_store_internal => iu_xu_is2_axu_store_internal, + iu_xu_is2_axu_ldst_indexed => iu_xu_is2_axu_ldst_indexed, + iu_xu_is2_axu_ldst_tag => iu_xu_is2_axu_ldst_tag, + iu_xu_is2_axu_ldst_size => iu_xu_is2_axu_ldst_size, + iu_xu_is2_axu_ldst_update => iu_xu_is2_axu_ldst_update, + iu_xu_is2_axu_ldst_extpid => iu_xu_is2_axu_ldst_extpid, + iu_xu_is2_axu_ldst_forcealign => iu_xu_is2_axu_ldst_forcealign, + iu_xu_is2_axu_ldst_forceexcept => iu_xu_is2_axu_ldst_forceexcept, + iu_xu_is2_axu_mftgpr => iu_xu_is2_axu_mftgpr, + iu_xu_is2_axu_mffgpr => iu_xu_is2_axu_mffgpr, + iu_xu_is2_axu_movedp => iu_xu_is2_axu_movedp, + iu_xu_is2_axu_instr_type => iu_xu_is2_axu_instr_type, + iu_xu_is2_match => iu_xu_is2_match, + fiss_uc_is2_2ucode => fiss_uc_is2_2ucode, + fiss_uc_is2_2ucode_type => fiss_uc_is2_2ucode_type, + iu_fu_rf0_str_val => iu_fu_rf0_str_val, + iu_fu_rf0_ldst_val => iu_fu_rf0_ldst_val, + iu_fu_rf0_ldst_tid => iu_fu_rf0_ldst_tid, + iu_fu_rf0_ldst_tag => iu_fu_rf0_ldst_tag, + iuq_ai_scan_in => iuq_ai_scan_in, + iuq_ai_scan_out => iuq_ai_scan_out, + iu_fu_is2_tid_decode => iu_fu_is2_tid_decode, + iu_fu_rf0_instr_match => iu_fu_rf0_instr_match, + iu_fu_rf0_instr => iu_fu_rf0_instr, + iu_fu_rf0_instr_v => iu_fu_rf0_instr_v, + iu_fu_rf0_is_ucode => iu_fu_rf0_is_ucode, + iu_fu_rf0_fra => iu_fu_rf0_fra, + iu_fu_rf0_frb => iu_fu_rf0_frb, + iu_fu_rf0_frc => iu_fu_rf0_frc, + iu_fu_rf0_frt => iu_fu_rf0_frt, + iu_fu_rf0_fra_v => iu_fu_rf0_fra_v, + iu_fu_rf0_frb_v => iu_fu_rf0_frb_v, + iu_fu_rf0_frc_v => iu_fu_rf0_frc_v, + iu_fu_rf0_ucfmul => iu_fu_rf0_ucfmul, + fu_iss_dbg_data => fu_iss_dbg_data, + iu_fu_rf0_tid => iu_fu_rf0_tid, + iu_fu_rf0_bypsel => iu_fu_rf0_bypsel, + iu_fu_rf0_ifar => iu_fu_rf0_ifar +); +iu_xu_is2_vld <= iu_xu_is2_vld_internal; +iu_xu_is2_instr(0 to 31) <= iu_xu_is2_instr_internal(0 to 31); +iu_xu_is2_tid(0 to 3) <= iu_xu_is2_tid_internal(0 to 3); +iu_xu_is2_axu_store <= iu_xu_is2_axu_store_internal; +iu_xu_is2_error(0 to 2) <= iu_xu_is2_error_internal(0 to 2); +iu_xu_is2_ifar <= iu_xu_is2_ifar_internal; +iu_xu_is2_pred_update <= iu_xu_is2_pred_update_internal; +iu_xu_is2_pred_taken_cnt(0 to 1)<= iu_xu_is2_pred_taken_cnt_internal(0 to 1); +fiss_uc_is2_instr(0 to 31) <= iu_xu_is2_instr_internal(0 to 31); +fiss_uc_is2_tid(0 to 3) <= iu_xu_is2_tid_internal(0 to 3); +iu_xu_is2_ucode_vld <= fiss_uc_is2_ucode_vld; +--------------------------------------- +-- scan chains +--------------------------------------- +iuq_b0_scan_in <= iuq_bp_scan_out; +iu_func_scan_out(0) <= iuq_b0_scan_out; +iuq_b1_scan_in <= iuq_mi_scan_out(0); +iu_func_scan_out(1) <= iuq_b1_scan_out; +iuq_fi_scan_in <= iu_func_scan_in_q(0); +iuq_ai_scan_in <= iuq_fi_scan_out; +iuq_b2_scan_in <= iuq_ai_scan_out; +iu_func_scan_out(2) <= iuq_b2_scan_out; +iuq_b3_scan_in <= iuq_mi_scan_out(1); +iu_func_scan_out(3) <= iuq_b3_scan_out; +iuq_s0_scan_in <= iu_func_scan_in_q(1); +iu_func_scan_out(4) <= iuq_s0_scan_out; +iuq_s1_scan_in <= iu_func_scan_in_q(2); +iu_func_scan_out(5) <= iuq_s1_scan_out; +iuq_s2_scan_in <= iu_func_scan_in_q(3); +iu_func_scan_out(6) <= iuq_s2_scan_out; +iuq_s3_scan_in <= iu_func_scan_in_q(4); +iu_func_scan_out(7) <= iuq_s3_scan_out; +end iuq; diff --git a/rel/src/vhdl/work/iuq_axu_fu_dec.vhdl b/rel/src/vhdl/work/iuq_axu_fu_dec.vhdl new file mode 100644 index 0000000..10bebc6 --- /dev/null +++ b/rel/src/vhdl/work/iuq_axu_fu_dec.vhdl @@ -0,0 +1,1879 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + + + + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + use work.iuq_pkg.all; + + +--------------------------------------------------------------------- + + +entity iuq_axu_fu_dec is +generic( + expand_type : integer := 2; -- 0 - ibm tech, 1 - other ); + fpr_addr_width : integer := 5; + needs_sreset : integer := 1); +port( + nclk : in clk_logic; + --------------------------------------------------------------------- + vdd : inout power_logic; + gnd : inout power_logic; + --------------------------------------------------------------------- + + i_dec_si : in std_ulogic; + i_dec_so : out std_ulogic; + + pc_iu_sg_0 : in std_ulogic; + pc_iu_func_sl_thold_0_b : in std_ulogic; + forcee : in std_ulogic; + d_mode : in std_ulogic; + delay_lclkr : in std_ulogic; + mpw1_b : in std_ulogic; + mpw2_b : in std_ulogic; + + pc_au_ram_mode : in std_ulogic; + pc_au_ram_thread_v : in std_ulogic; + + -- AXU interface signals--------------------------------------------- + iu_au_is0_instr_v : in std_ulogic; + iu_au_is0_instr : in std_ulogic_vector(0 to 31); + iu_au_is0_ucode_ext : in std_ulogic_vector(0 to 3); -- TACB + iu_au_is0_is_ucode : in std_ulogic; + iu_au_is0_2ucode : in std_ulogic; + iu_au_ucode_restart : in std_ulogic; + + iu_au_is0_cr_setter : in std_ulogic; -- from FXU + + iu_au_is1_stall : in std_ulogic; + iu_au_is0_flush : in std_ulogic; + iu_au_is1_flush : in std_ulogic; + + iu_au_config_iucr : in std_ulogic_vector(0 to 7); -- 0: graphics mode, 1: disable axu bypass 5: disable clock gating + ifdp_ex5_fmul_uc_complete : in std_ulogic; + + -- out to AXU + au_iu_is0_i_dec_b : out std_ulogic; -- decoded a valid FU instruction (inverted) + au_iu_is0_to_ucode : out std_ulogic; + au_iu_is0_ucode_only : out std_ulogic; + + au_iu_is0_ldst : out std_ulogic; -- load or store + au_iu_is0_ldst_v : out std_ulogic; -- load or store + au_iu_is0_st_v : out std_ulogic; -- store + au_iu_is0_mftgpr : out std_ulogic; + au_iu_is0_mffgpr : out std_ulogic; + au_iu_is0_movedp : out std_ulogic; + au_iu_is0_ldst_extpid : out std_ulogic; + au_iu_is0_instr_type : out std_ulogic_vector(0 to 2); + au_iu_is0_ldst_size : out std_ulogic_vector(0 to 5); + au_iu_is0_ldst_tag : out std_ulogic_vector(0 to 8); + au_iu_is0_ldst_ra_v : out std_ulogic; + au_iu_is0_ldst_ra : out std_ulogic_vector(0 to 6); + au_iu_is0_ldst_rb_v : out std_ulogic; + au_iu_is0_ldst_rb : out std_ulogic_vector(0 to 6); + au_iu_is0_ldst_dimm : out std_ulogic_vector(0 to 15); + au_iu_is0_ldst_indexed : out std_ulogic; + au_iu_is0_ldst_update : out std_ulogic; + au_iu_is0_ldst_forcealign : out std_ulogic; + au_iu_is0_ldst_forceexcept : out std_ulogic; + --------------------------------------------------------------------- + i_afd_is1_is_ucode : out std_ulogic; + i_afd_is1_to_ucode : out std_ulogic; + + i_afd_in_ucode_mode_or1d : out std_ulogic; + + i_afd_config_iucr : out std_ulogic_vector(1 to 7); -- IUCR2(33 to 39) + i_afd_fmul_uc_is1 : out std_ulogic; + + i_afd_is1_fra_v : out std_ulogic; + i_afd_is1_frb_v : out std_ulogic; + i_afd_is1_frc_v : out std_ulogic; + i_afd_is1_frt_v : out std_ulogic; + i_afd_is1_prebubble1 : out std_ulogic; + i_afd_is1_est_bubble3 : out std_ulogic; + + --i_afd_is1_cr_user : out std_ulogic; + i_afd_is1_cr_setter : out std_ulogic; -- FXU alters CR + i_afd_is1_cr_writer : out std_ulogic; -- AXU alters CR + + i_afd_is1_fra : out std_ulogic_vector(0 to 6); + i_afd_is1_frb : out std_ulogic_vector(0 to 6); + i_afd_is1_frc : out std_ulogic_vector(0 to 6); + i_afd_is1_frt : out std_ulogic_vector(0 to 6); + i_afd_is1_fra_buf : out std_ulogic_vector(1 to 6); + i_afd_is1_frb_buf : out std_ulogic_vector(1 to 6); + i_afd_is1_frc_buf : out std_ulogic_vector(1 to 6); + i_afd_is1_frt_buf : out std_ulogic_vector(1 to 6); + + i_afd_is1_instr_v : out std_ulogic; + + i_afd_is1_instr_ldst_v : out std_ulogic; + i_afd_is1_instr_ld_v : out std_ulogic; + i_afd_is1_instr_sto_v : out std_ulogic; + + i_afd_ignore_flush_is1 : out std_ulogic; + + i_afd_is1_divsqrt : out std_ulogic; + i_afd_is1_stall_rep : out std_ulogic; + + fu_dec_debug : out std_ulogic_vector(0 to 13) +); + + + + + +end iuq_axu_fu_dec; + +-------------------------------------------------------------------------------------------------------------------------------------------------------- + +architecture iuq_axu_fu_dec of iuq_axu_fu_dec is + + signal tidn : std_ulogic; + signal tiup : std_ulogic; + + + + signal iu_au_config_iucr_int : std_ulogic_vector(0 to 7); + signal iu_au_config_iucr_l2 : std_ulogic_vector(0 to 7); + signal iu_au_config_iucr_din : std_ulogic_vector(0 to 7); + signal is0_instr : std_ulogic_vector(00 to 31); + signal pri_is0 : std_ulogic_vector(0 to 5); -- primary opcode + signal sec_is0 : std_ulogic_vector(20 to 31); -- secondary opcode + signal av,bv,cv,tv : std_ulogic; -- source/target valids + signal isfu_dec_is0, ld_st_is0 : std_ulogic; + + signal st_is0, indexed, fdiv_is0, fsqrt_is0: std_ulogic; + signal update_form, forcealign : std_ulogic; + signal cr_writer : std_ulogic; + signal is1_st : std_ulogic; + signal is1_ldst : std_ulogic; + signal is1_fra_v : std_ulogic; + signal is1_frb_v : std_ulogic; + signal is1_frc_v : std_ulogic; + signal is1_frt_v : std_ulogic; + + + signal is0_instr_v : std_ulogic; + signal ucode_restart : std_ulogic; + signal is1_instr_v : std_ulogic; + signal is1_cr_setter : std_ulogic; + signal is1_cr_writer : std_ulogic; + signal is1_is_ucode : std_ulogic; + signal is1_to_ucode : std_ulogic; + + signal mffgpr, mftgpr : std_ulogic; + signal bubble3,prebubble1 :std_ulogic; + signal ldst_tag :std_ulogic_vector(0 to 8); + signal ldst_tag_addr :std_ulogic_vector(0 to 5); + signal is0_to_ucode : std_ulogic; + + + signal cmd_is0_ld, cmd_is1_l2, cmd_is1_scin, cmd_is1_scout : std_ulogic_vector(6 to 53); + + signal config_reg_scin : std_ulogic_vector(0 to 7); + signal config_reg_scout : std_ulogic_vector(0 to 7); + + + signal size : std_ulogic_vector(0 to 5); + signal spare_unused : std_ulogic_vector(2 to 49); + + signal is0_is_ucode, in_ucode_mode,in_fdivsqrt_mode_is0, only_from_ucode, only_graphics_mode ,graphics_mode : std_ulogic; + signal is0_invalid_kill, is0_invalid_kill_uc : std_ulogic; + signal is0_in_divsqrt_mode_or1d,is1_in_divsqrt_mode_or1d : std_ulogic; + + signal ldst_extpid : std_ulogic; + signal single_precision_ldst :std_ulogic; + signal int_word_ldst :std_ulogic; + signal sign_ext_ldst :std_ulogic; + signal is1_stall, is1_stall_b :std_ulogic; + signal io_port, io_port_ext :std_ulogic; + + signal ignore_flush_is0 : std_ulogic; + signal ucmodelat_din, ucmodelat_dout : std_ulogic; + signal final_fmul_uc : std_ulogic; + signal is1_fmul_uc : std_ulogic; + + signal is0_st_or_mtdp :std_ulogic; + signal is0_mftgpr :std_ulogic; + signal is0_usual_fra :std_ulogic; + signal is0_kill_or_divsqrt_b :std_ulogic; + signal au_iu_is0_i_dec : std_ulogic; + signal is0_i_dec_b : std_ulogic; + + signal is0_frt : std_ulogic_vector(0 to 5); + signal is0_fra_or_frs : std_ulogic_vector(0 to 5); + signal tag_in_16to20,mftgpr_not_DITC :std_ulogic; + signal cmd_is0_40_part :std_ulogic; + signal cmd_is0_41_part :std_ulogic; + signal cmd_is0_43_part :std_ulogic; + signal cmd_is0_50_part :std_ulogic; + + signal is1_frt_buf, is1_frt_buf_b : std_ulogic_vector(1 to 6); + signal is1_fra_buf, is1_fra_buf_b : std_ulogic_vector(1 to 6); + signal is1_frb_buf, is1_frb_buf_b : std_ulogic_vector(1 to 6); + signal is1_frc_buf, is1_frc_buf_b : std_ulogic_vector(1 to 6); + + signal is0_ins, is0_ins_b, is0_ins_dly, is0_ins_dly_b :std_ulogic_vector(0 to 31); + signal is0_ins_v, is0_ins_v_b :std_ulogic; + signal is1_v_nstall1_b, is1_v_nstall2_b :std_ulogic; + signal is1_v_nstall1, is1_v_nstall2,is1_v_nstall3,is1_v_nstall4,is1_v_nstall5,is1_v_nstall6,is1_v_nstall7,is1_v_nstall8 :std_ulogic; + + signal is1_v_nstall01_INVA_b, is1_v_nstall01_INVB :std_ulogic; + signal is1_v_nstall02_INVA_b, is1_v_nstall02_INVB :std_ulogic; + signal is1_v_nstall03_INVA_b, is1_v_nstall03_INVB :std_ulogic; + signal is1_v_nstall04_INVA_b, is1_v_nstall04_INVB :std_ulogic; + signal is1_v_nstall05_INVA_b, is1_v_nstall05_INVB :std_ulogic; + signal is1_v_nstall06_INVA_b, is1_v_nstall06_INVB :std_ulogic; + signal is1_v_nstall07_INVA_b, is1_v_nstall07_INVB :std_ulogic; + signal is1_v_nstall08_INVA_b, is1_v_nstall08_INVB :std_ulogic; + signal is1_v_nstall09_INVA_b, is1_v_nstall09_INVB :std_ulogic; + signal is1_v_nstall10_INVA_b, is1_v_nstall10_INVB :std_ulogic; + signal is1_v_nstall11_INVA_b, is1_v_nstall11_INVB :std_ulogic; + signal is1_v_nstall12_INVA_b, is1_v_nstall12_INVB :std_ulogic; + signal is1_v_nstall13_INVA_b, is1_v_nstall13_INVB :std_ulogic; + signal is1_v_nstall14_INVA_b, is1_v_nstall14_INVB :std_ulogic; + signal is1_v_nstall15_INVA_b, is1_v_nstall15_INVB :std_ulogic; + signal is1_v_nstall16_INVA_b, is1_v_nstall16_INVB :std_ulogic; + signal is1_v_nstall17_INVA_b, is1_v_nstall17_INVB :std_ulogic; + signal is1_v_nstall18_INVA_b, is1_v_nstall18_INVB :std_ulogic; + signal is1_v_nstall19_INVA_b, is1_v_nstall19_INVB :std_ulogic; + signal is1_v_nstall20_INVA_b, is1_v_nstall20_INVB :std_ulogic; + signal is1_v_nstall21_INVA_b, is1_v_nstall21_INVB :std_ulogic; + signal is1_v_nstall22_INVA_b, is1_v_nstall22_INVB :std_ulogic; + signal is1_v_nstall23_INVA_b, is1_v_nstall23_INVB :std_ulogic; + signal is1_v_nstall24_INVA_b, is1_v_nstall24_INVB :std_ulogic; + signal is1_v_nstall25_INVA_b, is1_v_nstall25_INVB :std_ulogic; + signal is1_v_nstall26_INVA_b, is1_v_nstall26_INVB :std_ulogic; + signal is1_v_nstall27_INVA_b, is1_v_nstall27_INVB :std_ulogic; + signal is1_v_nstall28_INVA_b, is1_v_nstall28_INVB :std_ulogic; + signal is1_v_nstall29_INVA_b, is1_v_nstall29_INVB :std_ulogic; + signal is1_v_nstall30_INVA_b, is1_v_nstall30_INVB :std_ulogic; + signal is1_v_nstall31_INVA_b, is1_v_nstall31_INVB :std_ulogic; + signal is1_v_nstall32_INVA_b, is1_v_nstall32_INVB :std_ulogic; + + signal ram_mode_v :std_ulogic; + + signal cmd_is0_go_b, cmd_is1_ho_b :std_ulogic_vector(6 to 53); +signal iu_au_is0_flush_b, iu_au_is1_flush_b :std_ulogic; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + begin + + + tidn <= '0'; + tiup <= '1'; + + is1_stall <= iu_au_is1_stall; + + + is0_instr <= iu_au_is0_instr; + is0_instr_v <= iu_au_is0_instr_v; + ucode_restart <= iu_au_ucode_restart; + spare_unused(48) <= tidn; + + pri_is0(0 to 5) <= is0_instr(0 to 5); + sec_is0(20 to 31) <= is0_instr(20 to 31); + + + spare_unused(49) <= d_mode; + +iu_au_is1_stall_INV: is1_stall_b <= not iu_au_is1_stall; + +is0_ins_inv: is0_ins_b(0 to 31) <= not( iu_au_is0_instr(0 to 31) ); +is0_ins_buf: is0_ins (0 to 31) <= not( is0_ins_b (0 to 31) ); +is0_ins_inv_dly: is0_ins_dly_b(0 to 31) <= not( is0_ins (0 to 31) ); +is0_ins_buf_dly: is0_ins_dly (0 to 31) <= not( is0_ins_dly_b (0 to 31) ); +is0_ins_v_inv: is0_ins_v_b <= not( iu_au_is0_instr_v ); +is0_ins_v_buf: is0_ins_v <= not( is0_ins_v_b ); + +spare_unused(12 to 27) <= is0_ins_dly(0 to 15); +spare_unused(28 to 33) <= is0_ins_dly(26 to 31); + + + +-- update # of inputs and outputs .i xx .o xx +-- run "espvhdlexpand iuq_axu_fu_dec.vhdl > iuq_axu_fu_dec_new.vhdl" to regenerate logic below table +-- + +--@@ ESPRESSO TABLE START @@ +-- .i 20 +-- .o 32 +-- .ilb pri_is0(0) pri_is0(1) pri_is0(2) pri_is0(3) pri_is0(4) pri_is0(5) +-- is0_instr(16) is0_instr(17) +-- sec_is0(20) sec_is0(21) sec_is0(22) sec_is0(23) sec_is0(24) sec_is0(25) sec_is0(26) sec_is0(27) sec_is0(28) sec_is0(29) sec_is0(30) sec_is0(31) +-- .ob isfu_dec_is0 tv av bv cv +-- bubble3 prebubble1 +-- ld_st_is0 st_is0 indexed update_form forcealign single_precision_ldst int_word_ldst sign_ext_ldst ldst_extpid io_port io_port_ext +-- size(0) size(1) size(2) size(3) size(4) size(5) +-- cr_writer mffgpr mftgpr fdiv_is0 +-- fsqrt_is0 only_from_ucode final_fmul_uc only_graphics_mode +-- .type fd +--# +--# +-- ################################################################################################################### +--# s +--# i +--# n +--# g o +--# l n +--# e l +--# | o y +--# p n | +--# r i s l f g +--# e n i y i r +--# u c t g l i | n a +--# p p f i | n d o f a p +--# r d o s w | s | c r l h +--# e l a r i o e t p LD/ST r o | i +--# b b d i t c o r x | io size m f c +--# u u n e e n d t e or in w mm | m s +--# b b o s d a | | | x |t bytes r ff f u u | +--#pri_is000 sec_is0 i b b r t e f l l l l t p| 1to16 i ft fs c l m +--# s l l o x o i d d d p oe pwrs t gg dq o | o +--#000000 112 2222222223 3 F T A B C e e s r e r g s s s i rx oftwo e pp ir d u d +--#012345 670 1234567890 1 U V V V V 3 1 t e d m n t t t d tt 012345 r rr vt e c e +-- ############# ############################################################################################################### + +-- 000000 --- ---------- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 # reserved +-- 000001 --- ---------- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 # open for vxu new instructions +-- 000010 --- ---------- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 000011 --- ---------- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + +-- 000100 --- 000------- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 000100 --- 0010------ - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 000100 --- 00110000-- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 000100 --- 0011000100 - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 000100 --- 0011000101 1 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 000100 --- 001100011- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 000100 --- 0011001--- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 000100 --- 001101---- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 000100 --- 00111000-- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 000100 --- 0011100100 - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + +-- 000100 --- 0011100101 1 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 000100 --- 001110011- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 000100 --- 0011101--- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 000100 --- 001111---- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 000100 --- 01-------- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 000100 --- 1--------- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + +-- 000101 --- ---------- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 000110 --- ---------- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 000111 --- ---------- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 001--- --- ---------- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 010--- --- ---------- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 01-0-- --- ---------- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 01--0- --- ---------- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 01---0 --- ---------- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + +-- 011111 --- 0000000000 - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + + +-- 011111 001 0000000011 0 1 1 0 0 0 0 0 1 0 1 0 0 1 0 1 0 11 000000 0 10 00 0 0 0 # mfdpx (DITC to FPR) 4 bytes +-- 011111 011 0000000011 0 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 11 000000 0 10 00 0 0 0 # mfdpx (DITC to FPR) 8 bytes +-- 011111 1-1 0000000011 0 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 11 000000 0 00 00 0 0 0 # mfdpx (DITC to FPR) >8 bytes + +-- 011111 001 0000000011 1 1 1 0 0 0 0 0 1 0 1 0 0 1 0 1 0 11 000000 1 10 00 0 0 0 # mfdpx. (DITC to FPR) 4 bytes +-- 011111 011 0000000011 1 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 11 000000 1 10 00 0 0 0 # mfdpx. (DITC to FPR) 8 bytes +-- 011111 1-1 0000000011 1 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 11 000000 1 00 00 0 0 0 # mfdpx. (DITC to FPR) >8 bytes + + +-- 011111 001 0000100011 0 1 1 0 0 0 0 0 1 0 0 0 0 1 0 1 0 10 000000 0 10 00 0 0 0 # mfdp (DITC to FPR) 4 bytes +-- 011111 011 0000100011 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 10 000000 0 10 00 0 0 0 # mfdp (DITC to FPR) 8 bytes +-- 011111 1-1 0000100011 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 10 000000 0 00 00 0 0 0 # mfdp (DITC to FPR) >8 bytes + +-- 011111 001 0000100011 1 1 1 0 0 0 0 0 1 0 0 0 0 1 0 1 0 10 000000 1 10 00 0 0 0 # mfdp. (DITC to FPR) 4 bytes +-- 011111 011 0000100011 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 10 000000 1 10 00 0 0 0 # mfdp. (DITC to FPR) 8 bytes +-- 011111 1-1 0000100011 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 10 000000 1 00 00 0 0 0 # mfdp. (DITC to FPR) >8 bytes + + +-- 011111 001 0001000011 0 1 0 1 0 0 0 0 1 1 1 0 0 1 0 1 0 11 000000 0 01 00 0 0 0 # mtdpx (DITC from FPR) 4 bytes +-- 011111 011 0001000011 0 1 0 1 0 0 0 0 1 1 1 0 0 0 0 0 0 11 000000 0 01 00 0 0 0 # mtdpx (DITC from FPR) 8 bytes +-- 011111 1-1 0001000011 0 1 0 1 0 0 0 0 1 1 1 0 0 0 0 0 0 11 000000 0 00 00 0 0 0 # mtdpx (DITC from FPR) >8 bytes + +-- 011111 001 0001000011 1 1 0 1 0 0 0 0 1 1 1 0 0 1 0 1 0 11 000000 1 01 00 0 0 0 # mtdpx. (DITC from FPR) 4 bytes +-- 011111 011 0001000011 1 1 0 1 0 0 0 0 1 1 1 0 0 0 0 0 0 11 000000 1 01 00 0 0 0 # mtdpx. (DITC from FPR) 8 bytes +-- 011111 1-1 0001000011 1 1 0 1 0 0 0 0 1 1 1 0 0 0 0 0 0 11 000000 1 00 00 0 0 0 # mtdpx. (DITC from FPR) >8 bytes + + +-- 011111 001 0001100011 0 1 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 10 000000 0 01 00 0 0 0 # mtdp (DITC from FPR) 4 bytes +-- 011111 011 0001100011 0 1 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 10 000000 0 01 00 0 0 0 # mtdp (DITC from FPR) 8 bytes +-- 011111 1-1 0001100011 0 1 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 10 000000 0 00 00 0 0 0 # mtdp (DITC from FPR) >8 bytes + +-- 011111 001 0001100011 1 1 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 10 000000 1 01 00 0 0 0 # mtdp. (DITC from FPR) 4 bytes +-- 011111 011 0001100011 1 1 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 10 000000 1 01 00 0 0 0 # mtdp. (DITC from FPR) 8 bytes +-- 011111 1-1 0001100011 1 1 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 10 000000 1 00 00 0 0 0 # mtdp. (DITC from FPR) >8 bytes + + +-- 011111 --- 01-------- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 011111 --- 100000---- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 011111 --- 10000100-- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 011111 --- 100001010- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 011111 --- 1000010110 - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 011111 --- 1000010111 - 1 1 0 0 0 0 0 1 0 1 0 0 1 0 0 0 00 000100 0 00 00 0 0 0 # lfsx +-- 011111 --- 1000011--- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- +-- 011111 --- 100010---- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 011111 --- 10001100-- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 011111 --- 100011010- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 011111 --- 1000110110 - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 011111 --- 1000110111 - 1 1 0 0 0 0 0 1 0 1 1 0 1 0 0 0 00 000100 0 00 00 0 0 0 # lfsux +-- 011111 --- 1000111--- - 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1 0 0 1 0 0 0 1 1 0 0 0 1 0 0 0 00 000000 0 01 00 1 0 1 # mfstgpr (mftgpr single) +-- 011111 --- 1011111111 - 1 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 00 000000 0 01 00 1 0 1 # mftgpr (mftgpr double) + +-- 011111 --- 110000---- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 011111 --- 11000100-- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 011111 --- 110001010- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 011111 --- 1100010110 - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +--#011111 --- 1100010111 - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 # lfdpx (ucoded) +-- 011111 --- 1100011--- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 011111 --- 11001----- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + +-- 011111 --- 110100---- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 011111 --- 11010100-- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 011111 --- 110101010- - 0 - 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1 1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 00 001000 0 00 00 0 0 0 # lfdu +-- 110100 --- ---------- - 1 0 1 0 0 0 0 1 1 0 0 0 1 0 0 0 00 000100 0 00 00 0 0 0 # stfs + +-- 110101 --- ---------- - 1 0 1 0 0 0 0 1 1 0 1 0 1 0 0 0 00 000100 0 00 00 0 0 0 # stfsu +-- +-- 110110 --- ---------- - 1 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 00 001000 0 00 00 0 0 0 # stfd +-- +-- 110111 --- ---------- - 1 0 1 0 0 0 0 1 1 0 1 0 0 0 0 0 00 001000 0 00 00 0 0 0 # stfdu +-- +-- 111000 --- ---------- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- +--#111001 --- ---------0 0 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 # lfdp (ucoded) + +-- 111001 --- ---------0 1 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 111001 --- ---------1 - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- +-- 111010 --- ---------- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + +-- 111011 --- 000--0---- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 111011 --- 0010-0---- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 111011 --- 00110000-- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 111011 --- 0011000100 - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 111011 --- 0011000101 0 1 1 0 1 0 0 0 0 0 0 0 0 - - - 0 00 ------ 0 00 00 0 0 1 # fexptes +-- 111011 --- 001100011- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 111011 --- 00110010-- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 111011 --- 001100110- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 111011 --- 0011001110 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 0 0 0 # fcfiwus (removed) +-- 111011 --- 0011001110 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # fcfiwus. (removed) +-- 111011 --- 0011001111 - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + +-- 111011 --- 00111000-- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 111011 --- 0011100100 - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 111011 --- 0011100101 0 1 1 0 1 0 0 0 0 0 0 0 0 - - - 0 00 ------ 0 00 00 0 0 1 # floges +-- 111011 --- 001110011- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 111011 --- 0011101--- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 111011 --- 01---0---- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 111011 --- 10---0---- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 111011 --- 1100-0---- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 111011 --- 1101000--- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 111011 --- 11010010-- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 111011 --- 110100110- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 111011 --- 1101001110 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 0 0 0 # fcfids +-- 111011 --- 1101001110 1 1 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # fcfids. +-- 111011 --- 1101001111 - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 111011 --- 110110---- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 111011 --- 1110-0---- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 111011 --- 1111000--- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 111011 --- 11110010-- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 111011 --- 111100110- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 111011 --- 1111001110 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 0 0 0 # fcfidus +-- 111011 --- 1111001110 1 1 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # fcfidus. +-- 111011 --- 1111001111 - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 111011 --- 111110---- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + +-- 111011 --- -----10000 - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + +-- 111011 --- -----10001 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 1 1 0 # fmuls_uc (last uc for fdivs, fsqrts) 11/07/07 +-- 111011 --- -----10001 1 1 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 1 1 0 # fmuls_uc. (last uc for fdivs, fsqrts) 11/07/07 +-- 111011 --- -----10010 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 00 ------ 0 00 10 0 0 0 # fdivs (ucoded) +-- 111011 --- -----10010 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 00 ------ 0 00 10 0 0 0 # fdivs. (ucoded) +-- 111011 --- -----10011 - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 111011 --- -----10100 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 0 0 0 # fsubs +-- 111011 --- -----10100 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # fsubs. +-- 111011 --- -----10101 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 0 0 0 # fadds +-- 111011 --- -----10101 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # fadds. +-- 111011 --- -----10110 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 00 ------ 0 00 01 0 0 0 # fsqrts (ucoded) +-- 111011 --- -----10110 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 00 ------ 0 00 01 0 0 0 # fsqrts. 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1100101111 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 0 0 0 # fctidz +-- 111111 --- 1100101111 1 1 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # fctidz. + +--#111111 --- 110011---- - 0 0 0 0 00 0 0 0 +-- 111111 --- 1101000--- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 111111 --- 11010010-- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 111111 --- 110100110- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 111111 --- 1101001110 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 0 0 0 # fcfid +-- 111111 --- 1101001110 1 1 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # fcfid. + +-- 111111 --- 1101001111 - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +--#111111 --- 110101---- - 0 0 0 0 00 0 0 0 +-- 111111 --- 110110---- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +--#111111 --- 110111---- - 0 0 0 0 00 0 0 0 +-- 111111 --- 111000---- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +--#111111 --- 111001---- - 0 0 0 0 00 0 0 0 +-- 111111 --- 1110100--- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 111111 --- 11101010-- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 111111 --- 111010110- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +-- 111111 --- 1110101110 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 0 0 0 # fctidu +-- 111111 --- 1110101110 1 1 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # fctidu. +-- 111111 --- 1110101111 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 0 0 0 # fctiwuz +-- 111111 --- 1110101111 1 1 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # fctiwuz. +--#111111 --- 111011---- - 0 0 0 0 00 0 0 0 +-- 111111 --- 1111000--- - 0 - - - - - - 0 0 - 0 - - - - 0 00 000000 - 00 00 0 0 0 +-- 111111 --- 11110010-- - 0 - - - - - - 0 0 - 0 - - - - 0 00 000000 - 00 00 0 0 0 +-- 111111 --- 111100110- - 0 - - - - - - 0 0 - 0 - - - - 0 00 000000 - 00 00 0 0 0 +-- 111111 --- 1111001110 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 0 0 0 # fcfidu +-- 111111 --- 1111001110 1 1 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # fcfidu. +-- 111111 --- 1111001111 - 0 - - - - - - 0 0 - 0 - - - - 0 00 000000 - 00 00 0 0 0 +--#111111 --- 111101---- - 0 0 0 0 00 0 0 0 +--#111111 --- 111110---- - 0 - - - - - - 0 0 - 0 1 0 0 0 0 00 ------ - 00 00 1 0 0 # reserve for +--#111111 --- 111111---- - 0 0 0 0 00 0 0 0 # div rnd inst + +-- ####################################################################### +-- .e +--@@ ESPRESSO TABLE END @@ + +--@@ ESPRESSO LOGIC START @@ +-- logic generated on: Wed Apr 21 11:18:41 2010 +isfu_dec_is0 <= ( pri_is0(0) and pri_is0(1) and pri_is0(3) and pri_is0(4) + and pri_is0(5) and not sec_is0(21) and not sec_is0(22) + and not sec_is0(23) and not sec_is0(24) and not sec_is0(25) + and sec_is0(27) and not sec_is0(29) and not sec_is0(30)) or + ( pri_is0(0) and pri_is0(1) and pri_is0(4) and pri_is0(5) + and sec_is0(26) and sec_is0(28) and not sec_is0(30)) or + ( pri_is0(0) and pri_is0(1) and pri_is0(3) and pri_is0(4) + and pri_is0(5) and sec_is0(26) and not sec_is0(30)) or + ( pri_is0(0) and pri_is0(1) and pri_is0(4) and pri_is0(5) + and sec_is0(26) and sec_is0(27) and not sec_is0(30)) or + (not pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(3) + and pri_is0(4) and pri_is0(5) and sec_is0(20) + and not sec_is0(21) and not sec_is0(22) and not sec_is0(23) + and not sec_is0(26) and not sec_is0(27) and not sec_is0(28) + and sec_is0(29) and sec_is0(30)) or + ( pri_is0(0) and pri_is0(1) and pri_is0(4) and pri_is0(5) + and sec_is0(21) and sec_is0(22) and sec_is0(24) + and not sec_is0(25) and sec_is0(27) and sec_is0(28) + and sec_is0(29) and not sec_is0(30)) or + ( pri_is0(0) and pri_is0(1) and not pri_is0(3) and pri_is0(4) + and pri_is0(5) and not sec_is0(21) and not sec_is0(22) + and sec_is0(23) and sec_is0(24) and not sec_is0(27) + and sec_is0(28) and not sec_is0(29) and sec_is0(30) + and not sec_is0(31)) or + ( pri_is0(0) and pri_is0(1) and pri_is0(3) and pri_is0(4) + and pri_is0(5) and not sec_is0(21) and sec_is0(22) + and sec_is0(23) and sec_is0(27) and not sec_is0(28) + and not sec_is0(29) and not sec_is0(30)) or + ( pri_is0(0) and pri_is0(1) and pri_is0(3) and pri_is0(4) + and pri_is0(5) and sec_is0(21) and sec_is0(22) + and not sec_is0(24) and sec_is0(25) and sec_is0(27) + and sec_is0(28) and sec_is0(29)) or + ( pri_is0(0) and pri_is0(1) and pri_is0(3) and pri_is0(4) + and pri_is0(5) and not sec_is0(21) and not sec_is0(24) + and not sec_is0(25) and sec_is0(27) and not sec_is0(28) + and not sec_is0(29) and not sec_is0(30)) or + ( pri_is0(1) and pri_is0(2) and pri_is0(3) and pri_is0(4) + and pri_is0(5) and sec_is0(21) and sec_is0(24) + and not sec_is0(25) and sec_is0(26) and not sec_is0(27) + and sec_is0(28) and sec_is0(29) and sec_is0(30)) or + ( pri_is0(1) and pri_is0(2) and pri_is0(3) and pri_is0(4) + and pri_is0(5) and sec_is0(21) and not sec_is0(23) + and sec_is0(24) and sec_is0(26) and not sec_is0(27) + and sec_is0(28) and sec_is0(29) and sec_is0(30)) or + ( pri_is0(1) and pri_is0(2) and pri_is0(3) and pri_is0(4) + and pri_is0(5) and sec_is0(21) and not sec_is0(22) + and sec_is0(23) and sec_is0(24) and not sec_is0(25) + and sec_is0(26) and sec_is0(27) and sec_is0(28) + and sec_is0(30)) or + ( pri_is0(0) and pri_is0(1) and pri_is0(3) and pri_is0(4) + and pri_is0(5) and not sec_is0(21) and not sec_is0(22) + and not sec_is0(23) and not sec_is0(24) and not sec_is0(28) + and not sec_is0(29) and not sec_is0(30)) or + ( pri_is0(1) and pri_is0(2) and pri_is0(3) and pri_is0(4) + and pri_is0(5) and sec_is0(21) and not sec_is0(22) + and not sec_is0(23) and sec_is0(24) and sec_is0(25) + and sec_is0(26) and sec_is0(27) and sec_is0(28)) or + ( pri_is0(1) and pri_is0(2) and pri_is0(3) and pri_is0(4) + and pri_is0(5) and sec_is0(21) and not sec_is0(22) + and sec_is0(26) and not sec_is0(27) and sec_is0(28) + and sec_is0(29) and sec_is0(30)) or + ( pri_is0(1) and pri_is0(2) and pri_is0(3) and pri_is0(4) + and pri_is0(5) and sec_is0(21) and not sec_is0(22) + and sec_is0(24) and sec_is0(25) and sec_is0(26) + and sec_is0(27) and sec_is0(28) and sec_is0(29)) or + ( pri_is0(0) and pri_is0(1) and pri_is0(3) and pri_is0(4) + and pri_is0(5) and sec_is0(21) and not sec_is0(22) + and sec_is0(24) and not sec_is0(25) and not sec_is0(27) + and sec_is0(28) and sec_is0(29) and sec_is0(30)) or + ( pri_is0(0) and pri_is0(1) and pri_is0(3) and pri_is0(4) + and pri_is0(5) and not sec_is0(21) and not sec_is0(22) + and not sec_is0(23) and not sec_is0(25) and not sec_is0(28) + and not sec_is0(29) and not sec_is0(30)) or + ( pri_is0(0) and pri_is0(1) and pri_is0(3) and pri_is0(4) + and pri_is0(5) and not sec_is0(21) and not sec_is0(22) + and sec_is0(23) and not sec_is0(24) and not sec_is0(25) + and sec_is0(28) and sec_is0(29) and not sec_is0(30)) or + ( pri_is0(0) and pri_is0(1) and pri_is0(3) and pri_is0(4) + and pri_is0(5) and not sec_is0(21) and not sec_is0(22) + and not sec_is0(24) and not sec_is0(25) and sec_is0(27) + and sec_is0(28) and sec_is0(29)) or + ( pri_is0(0) and pri_is0(1) and pri_is0(3) and pri_is0(4) + and pri_is0(5) and not sec_is0(21) and not sec_is0(22) + and not sec_is0(23) and not sec_is0(24) and sec_is0(25) + and not sec_is0(27) and sec_is0(28) and sec_is0(29) + and not sec_is0(30)) or + ( pri_is0(1) and pri_is0(2) and pri_is0(3) and pri_is0(4) + and pri_is0(5) and sec_is0(21) and not sec_is0(22) + and sec_is0(24) and sec_is0(26) and sec_is0(28) + and sec_is0(29) and sec_is0(30)) or + ( pri_is0(0) and pri_is0(1) and pri_is0(3) and pri_is0(4) + and pri_is0(5) and not sec_is0(21) and not sec_is0(22) + and not sec_is0(24) and not sec_is0(27) and not sec_is0(28) + and not sec_is0(29) and not sec_is0(30)) or + ( pri_is0(0) and pri_is0(1) and pri_is0(3) and pri_is0(4) + and pri_is0(5) and not sec_is0(21) and not sec_is0(22) + and not sec_is0(23) and sec_is0(24) and not sec_is0(25) + and not sec_is0(27) and sec_is0(28) and sec_is0(29) + and not sec_is0(30)) or + ( pri_is0(0) and pri_is0(1) and pri_is0(4) and pri_is0(5) + and sec_is0(26) and not sec_is0(29) and sec_is0(30)) or + ( pri_is0(0) and pri_is0(1) and pri_is0(4) and pri_is0(5) + and sec_is0(26) and sec_is0(29) and not sec_is0(30)) or + ( pri_is0(0) and pri_is0(1) and pri_is0(4) and pri_is0(5) + and sec_is0(26) and sec_is0(27) and sec_is0(28)) or + ( pri_is0(0) and pri_is0(1) and not pri_is0(2)) or + ( pri_is0(0) and pri_is0(1) and pri_is0(3) and pri_is0(4) + and pri_is0(5) and sec_is0(26) and sec_is0(28)); + +tv <= (not pri_is0(3) and sec_is0(30) and not sec_is0(31)) or + ( pri_is0(2) and pri_is0(4) and not sec_is0(21) and sec_is0(22)) or + ( pri_is0(2) and sec_is0(20) and not sec_is0(23) and not sec_is0(24) + and not sec_is0(26) and not sec_is0(27) and not sec_is0(28) and sec_is0(29) + and sec_is0(30)) or + ( pri_is0(2) and sec_is0(22) and not sec_is0(23) and sec_is0(24) + and sec_is0(26) and not sec_is0(27) and sec_is0(28) and sec_is0(29) + and sec_is0(30)) or + ( pri_is0(2) and pri_is0(4) and sec_is0(22) and not sec_is0(24) + and sec_is0(27)) or + ( pri_is0(2) and pri_is0(4) and sec_is0(21) and not sec_is0(22) + and not sec_is0(23) and sec_is0(28)) or + ( pri_is0(0) and pri_is0(2) and pri_is0(4) and not sec_is0(25) + and sec_is0(27)) or + ( pri_is0(0) and pri_is0(2) and pri_is0(4) and not sec_is0(23) + and sec_is0(27)) or + ( pri_is0(0) and pri_is0(2) and pri_is0(4) and sec_is0(26)) or + (not pri_is0(2) and not pri_is0(3)); + +av <= ( pri_is0(3) and sec_is0(20) and not sec_is0(22) and not sec_is0(23) + and sec_is0(24) and not sec_is0(26) and not sec_is0(27) and not sec_is0(28) + and sec_is0(29) and sec_is0(30)) or + ( pri_is0(0) and pri_is0(3) and pri_is0(4) and not sec_is0(22) + and not sec_is0(23) and not sec_is0(24) and not sec_is0(25) and not sec_is0(26) + and not sec_is0(28)) or + ( pri_is0(0) and pri_is0(3) and pri_is0(4) and not sec_is0(23) + and sec_is0(25) and not sec_is0(26) and not sec_is0(27) and not sec_is0(29)) or + (not pri_is0(0) and sec_is0(21) and sec_is0(23) and sec_is0(24) + and not sec_is0(25) and sec_is0(29)) or + ( pri_is0(0) and pri_is0(3) and pri_is0(4) and not sec_is0(24) + and not sec_is0(25) and not sec_is0(26) and not sec_is0(27) and not sec_is0(29) + and not sec_is0(30)) or + (not pri_is0(0) and sec_is0(21) and not sec_is0(22) and sec_is0(23) + and not sec_is0(27)) or + ( pri_is0(0) and pri_is0(2) and pri_is0(4) and sec_is0(26) + and sec_is0(27) and sec_is0(28)) or + ( pri_is0(0) and pri_is0(2) and pri_is0(4) and sec_is0(26) + and not sec_is0(27) and not sec_is0(28) and sec_is0(29)) or + ( pri_is0(0) and pri_is0(2) and pri_is0(4) and sec_is0(26) + and sec_is0(28) and not sec_is0(29)) or + ( pri_is0(0) and pri_is0(2) and sec_is0(26) and sec_is0(30)) or + ( pri_is0(1) and not pri_is0(2) and pri_is0(3)); + +bv <= (not pri_is0(0) and sec_is0(21) and not sec_is0(25) and not sec_is0(29)) or + ( pri_is0(2) and not pri_is0(3) and sec_is0(28) and sec_is0(30) + and not sec_is0(31)) or + (not pri_is0(0) and sec_is0(21) and sec_is0(23) and sec_is0(25) + and sec_is0(27) and sec_is0(28) and sec_is0(29)) or + ( pri_is0(0) and pri_is0(2) and pri_is0(4) and not sec_is0(24) + and not sec_is0(27) and not sec_is0(28) and not sec_is0(29) and not sec_is0(30)) or + ( pri_is0(2) and pri_is0(4) and sec_is0(22) and not sec_is0(24) + and not sec_is0(26)) or + ( pri_is0(0) and pri_is0(2) and pri_is0(4) and sec_is0(23) + and sec_is0(24) and not sec_is0(25) and sec_is0(29)) or + ( pri_is0(0) and pri_is0(2) and pri_is0(4) and not sec_is0(25) + and not sec_is0(26) and sec_is0(27)) or + ( pri_is0(0) and pri_is0(2) and pri_is0(4) and not sec_is0(21) + and sec_is0(24) and sec_is0(27) and not sec_is0(30)) or + ( pri_is0(0) and pri_is0(2) and sec_is0(26) and sec_is0(28) + and sec_is0(30)) or + ( pri_is0(0) and pri_is0(2) and pri_is0(4) and not sec_is0(23) + and not sec_is0(26) and sec_is0(27)) or + ( pri_is0(0) and pri_is0(2) and pri_is0(4) and sec_is0(26) + and not sec_is0(30)); + +cv <= ( pri_is0(0) and pri_is0(2) and sec_is0(26) and not sec_is0(28) + and sec_is0(30)) or + ( pri_is0(0) and pri_is0(2) and sec_is0(26) and sec_is0(29) + and sec_is0(30)) or + ( pri_is0(0) and pri_is0(2) and pri_is0(4) and sec_is0(26) + and sec_is0(27) and sec_is0(28)); + +bubble3 <= ( pri_is0(0) and pri_is0(2) and not sec_is0(23) and not sec_is0(26) + and sec_is0(29) and sec_is0(31)) or + ( pri_is0(0) and pri_is0(2) and pri_is0(4) and not sec_is0(23) + and sec_is0(24) and not sec_is0(26) and not sec_is0(27) and not sec_is0(28)) or + ( pri_is0(0) and pri_is0(2) and not sec_is0(25) and sec_is0(27) + and sec_is0(31)) or + ( pri_is0(2) and not sec_is0(21) and sec_is0(22) and sec_is0(27) + and sec_is0(31)) or + ( pri_is0(0) and pri_is0(2) and pri_is0(4) and sec_is0(23) + and not sec_is0(24) and not sec_is0(26) and not sec_is0(27) and not sec_is0(28) + and not sec_is0(29) and not sec_is0(30)) or + ( pri_is0(2) and sec_is0(22) and not sec_is0(24) and sec_is0(27) + and sec_is0(31)) or + ( pri_is0(0) and pri_is0(2) and not sec_is0(25) and not sec_is0(26) + and sec_is0(28) and sec_is0(29) and sec_is0(31)) or + ( pri_is0(0) and pri_is0(2) and not sec_is0(23) and sec_is0(27) + and sec_is0(31)) or + ( pri_is0(0) and pri_is0(2) and sec_is0(26) and sec_is0(30) + and sec_is0(31)) or + ( pri_is0(0) and pri_is0(2) and sec_is0(26) and sec_is0(28) + and not sec_is0(29) and sec_is0(31)) or + ( pri_is0(0) and pri_is0(2) and sec_is0(26) and sec_is0(27) + and sec_is0(31)); + +prebubble1 <= ( pri_is0(0) and pri_is0(2) and not sec_is0(23) and not sec_is0(26) + and not sec_is0(27) and sec_is0(30)); + +ld_st_is0 <= (not pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(3) + and pri_is0(4) and pri_is0(5) and sec_is0(20) and not sec_is0(21) + and not sec_is0(22) and not sec_is0(23) and not sec_is0(26) and not sec_is0(27) + and not sec_is0(28) and sec_is0(29) and sec_is0(30)) or + (not pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(3) + and pri_is0(4) and pri_is0(5) and sec_is0(21) + and not sec_is0(22) and not sec_is0(23) and sec_is0(24) + and sec_is0(25) and sec_is0(26) and sec_is0(27) + and sec_is0(28)) or + (not pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(3) + and pri_is0(4) and pri_is0(5) and sec_is0(21) + and not sec_is0(22) and sec_is0(23) and sec_is0(24) + and not sec_is0(25) and sec_is0(26) and sec_is0(27) + and sec_is0(28) and sec_is0(30)) or + (not pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(3) + and pri_is0(4) and pri_is0(5) and sec_is0(21) + and not sec_is0(22) and sec_is0(24) and sec_is0(25) + and sec_is0(26) and sec_is0(27) and sec_is0(28) + and sec_is0(29)) or + (not pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(3) + and pri_is0(4) and pri_is0(5) and sec_is0(21) + and sec_is0(24) and not sec_is0(25) and sec_is0(26) + and not sec_is0(27) and sec_is0(28) and sec_is0(29) + and sec_is0(30)) or + (not pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(3) + and pri_is0(4) and pri_is0(5) and sec_is0(21) + and not sec_is0(22) and sec_is0(26) and not sec_is0(27) + and sec_is0(28) and sec_is0(29) and sec_is0(30)) or + (not pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(3) + and pri_is0(4) and pri_is0(5) and sec_is0(21) + and not sec_is0(23) and sec_is0(24) and sec_is0(26) + and not sec_is0(27) and sec_is0(28) and sec_is0(29) + and sec_is0(30)) or + (not pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(3) + and pri_is0(4) and pri_is0(5) and sec_is0(21) + and not sec_is0(22) and sec_is0(24) and sec_is0(26) + and sec_is0(28) and sec_is0(29) and sec_is0(30)) or + ( pri_is0(0) and pri_is0(1) and not pri_is0(2)); + +st_is0 <= (not pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(3) + and pri_is0(4) and pri_is0(5) and sec_is0(20) + and not sec_is0(21) and not sec_is0(22) and not sec_is0(23) + and sec_is0(24) and not sec_is0(26) and not sec_is0(27) + and not sec_is0(28) and sec_is0(29) and sec_is0(30)) or + (not pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(3) + and pri_is0(4) and pri_is0(5) and sec_is0(21) and not sec_is0(22) + and sec_is0(23) and sec_is0(24) and sec_is0(25) and sec_is0(26) + and sec_is0(27) and sec_is0(28) and sec_is0(29)) or + (not pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(3) + and pri_is0(4) and pri_is0(5) and sec_is0(21) and not sec_is0(22) + and sec_is0(23) and sec_is0(24) and not sec_is0(25) and sec_is0(26) + and sec_is0(27) and sec_is0(28) and sec_is0(30)) or + (not pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(3) + and pri_is0(4) and pri_is0(5) and sec_is0(21) and sec_is0(23) + and sec_is0(24) and not sec_is0(25) and sec_is0(26) and not sec_is0(27) + and sec_is0(28) and sec_is0(29) and sec_is0(30)) or + (not pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(3) + and pri_is0(4) and pri_is0(5) and sec_is0(21) and not sec_is0(22) + and sec_is0(23) and sec_is0(26) and not sec_is0(27) and sec_is0(28) + and sec_is0(29) and sec_is0(30)) or + ( pri_is0(0) and pri_is0(1) and not pri_is0(2) and pri_is0(3)); + +indexed <= ( pri_is0(2) and sec_is0(20) and not sec_is0(23) and not sec_is0(25) + and not sec_is0(26) and not sec_is0(27) and not sec_is0(28) and sec_is0(29) + and sec_is0(30)) or + (not pri_is0(0) and sec_is0(21) and not sec_is0(25) and sec_is0(27) + and sec_is0(29)) or + (not pri_is0(0) and sec_is0(21) and not sec_is0(22) and not sec_is0(27)) or + (not pri_is0(0) and sec_is0(21) and sec_is0(24) and sec_is0(26) + and not sec_is0(27) and sec_is0(28) and sec_is0(29) and sec_is0(30)) or + (not pri_is0(0) and sec_is0(21) and not sec_is0(22) and not sec_is0(23) + and sec_is0(28) and not sec_is0(29)); + +update_form <= (not pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(3) + and pri_is0(4) and pri_is0(5) and sec_is0(21) and not sec_is0(22) + and sec_is0(25) and sec_is0(26) and not sec_is0(27) and sec_is0(28) + and sec_is0(29) and sec_is0(30)) or + ( pri_is0(0) and pri_is0(1) and not pri_is0(2) and pri_is0(5)); + +forcealign <= '0'; + +single_precision_ldst <= ( pri_is0(2) and not is0_instr(16) and not is0_instr(17) + and sec_is0(20) and not sec_is0(22) and not sec_is0(23) + and not sec_is0(26) and not sec_is0(27) and not sec_is0(28) + and sec_is0(29) and sec_is0(30)) or + ( pri_is0(1) and not pri_is0(2) and not pri_is0(4)) or + (not pri_is0(0) and sec_is0(21) and not sec_is0(22) + and sec_is0(28) and sec_is0(29) and not sec_is0(30)) or + (not pri_is0(0) and sec_is0(21) and not sec_is0(22) + and not sec_is0(24)); + +int_word_ldst <= (not pri_is0(0) and sec_is0(22) and sec_is0(24) + and sec_is0(26) and not sec_is0(27) and sec_is0(28) + and sec_is0(29) and sec_is0(30)) or + (not pri_is0(0) and sec_is0(21) and not sec_is0(22) + and not sec_is0(23) and sec_is0(28) and not sec_is0(29)) or + (not pri_is0(0) and sec_is0(21) and not sec_is0(25) + and not sec_is0(29)); + +sign_ext_ldst <= ( pri_is0(2) and not is0_instr(16) and not is0_instr(17) + and sec_is0(20) and not sec_is0(22) and not sec_is0(23) + and not sec_is0(26) and not sec_is0(27) and not sec_is0(28) + and sec_is0(29) and sec_is0(30)) or + (not pri_is0(0) and sec_is0(21) and not sec_is0(22) + and not sec_is0(23) and sec_is0(28) and not sec_is0(29) + and not sec_is0(30)) or + (not pri_is0(0) and sec_is0(22) and not sec_is0(23) + and sec_is0(24) and not sec_is0(25)); + +ldst_extpid <= (not pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(3) + and pri_is0(4) and pri_is0(5) and sec_is0(21) + and not sec_is0(22) and sec_is0(24) and not sec_is0(25) + and sec_is0(26) and sec_is0(27) and sec_is0(28) + and sec_is0(29) and sec_is0(30)); + +io_port <= (not pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(3) + and pri_is0(4) and pri_is0(5) and sec_is0(20) + and not sec_is0(21) and not sec_is0(22) and not sec_is0(23) + and not sec_is0(26) and not sec_is0(27) and not sec_is0(28) + and sec_is0(29) and sec_is0(30)); + +io_port_ext <= (not pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(3) + and pri_is0(4) and pri_is0(5) and sec_is0(20) + and not sec_is0(21) and not sec_is0(22) and not sec_is0(23) + and not sec_is0(25) and not sec_is0(26) and not sec_is0(27) + and not sec_is0(28) and sec_is0(29) and sec_is0(30)); + +size(0) <= '0'; + +size(1) <= '0'; + +size(2) <= (not pri_is0(0) and sec_is0(21) and not sec_is0(25) and sec_is0(27) + and sec_is0(29)) or + ( pri_is0(4) and sec_is0(21) and not sec_is0(22) and sec_is0(24) + and not sec_is0(27)) or + (not pri_is0(2) and pri_is0(4)); + +size(3) <= (not pri_is0(0) and sec_is0(21) and not sec_is0(22) and not sec_is0(24)) or + ( pri_is0(2) and sec_is0(22) and sec_is0(24) and sec_is0(26) + and not sec_is0(27) and sec_is0(28) and sec_is0(29) and sec_is0(30)) or + ( pri_is0(1) and not pri_is0(2) and not pri_is0(4)); + +size(4) <= '0'; + +size(5) <= '0'; + +cr_writer <= ( pri_is0(2) and sec_is0(20) and not sec_is0(22) and not sec_is0(23) + and not sec_is0(26) and not sec_is0(27) and not sec_is0(28) and sec_is0(29) + and sec_is0(30) and sec_is0(31)) or + ( pri_is0(0) and pri_is0(2) and not sec_is0(21) and sec_is0(24) + and sec_is0(27) and sec_is0(31)) or + ( pri_is0(0) and pri_is0(2) and not sec_is0(25) and not sec_is0(26) + and not sec_is0(29) and not sec_is0(30) and sec_is0(31)) or + ( pri_is0(2) and sec_is0(22) and not sec_is0(24) + and sec_is0(27) and sec_is0(31)) or + ( pri_is0(0) and pri_is0(2) and pri_is0(4) and not sec_is0(22) + and not sec_is0(26) and not sec_is0(27) and not sec_is0(28) + and not sec_is0(29) and not sec_is0(30)) or + ( pri_is0(0) and pri_is0(2) and not sec_is0(25) and not sec_is0(26) + and sec_is0(28) and sec_is0(29) and sec_is0(31)) or + ( pri_is0(0) and pri_is0(2) and not sec_is0(23) and not sec_is0(26) + and sec_is0(31)) or + ( pri_is0(0) and pri_is0(2) and sec_is0(26) and sec_is0(30) + and sec_is0(31)) or + ( pri_is0(0) and pri_is0(2) and sec_is0(26) and sec_is0(28) + and not sec_is0(29) and sec_is0(31)) or + ( pri_is0(0) and pri_is0(2) and sec_is0(26) and sec_is0(27) + and sec_is0(31)); + +mffgpr <= (not pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(3) + and pri_is0(4) and pri_is0(5) and sec_is0(21) + and not sec_is0(22) and not sec_is0(23) and sec_is0(24) + and sec_is0(25) and sec_is0(26) and sec_is0(27) + and sec_is0(28)) or + (not pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(3) + and pri_is0(4) and pri_is0(5) and not is0_instr(16) and sec_is0(20) + and not sec_is0(21) and not sec_is0(22) and not sec_is0(23) and not sec_is0(24) + and not sec_is0(26) and not sec_is0(27) and not sec_is0(28) and sec_is0(29) + and sec_is0(30)); + +mftgpr <= (not pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(3) + and pri_is0(4) and pri_is0(5) and sec_is0(21) and not sec_is0(22) + and sec_is0(23) and sec_is0(24) and not sec_is0(25) and sec_is0(26) + and sec_is0(27) and sec_is0(28) and not sec_is0(29) and sec_is0(30)) or + (not pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(3) + and pri_is0(4) and pri_is0(5) and sec_is0(21) and not sec_is0(22) + and sec_is0(23) and sec_is0(24) and sec_is0(25) and sec_is0(26) + and sec_is0(27) and sec_is0(28) and sec_is0(29)) or + (not pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(3) + and pri_is0(4) and pri_is0(5) and not is0_instr(16) and sec_is0(20) + and not sec_is0(21) and not sec_is0(22) and not sec_is0(23) and sec_is0(24) + and not sec_is0(26) and not sec_is0(27) and not sec_is0(28) and sec_is0(29) + and sec_is0(30)); + +fdiv_is0 <= ( pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(4) + and pri_is0(5) and sec_is0(26) and not sec_is0(27) and not sec_is0(28) + and sec_is0(29) and not sec_is0(30)); + +fsqrt_is0 <= ( pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(4) + and pri_is0(5) and sec_is0(26) and not sec_is0(27) and sec_is0(28) + and sec_is0(29) and not sec_is0(30)); + +only_from_ucode <= (not pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(3) + and pri_is0(4) and pri_is0(5) and sec_is0(21) and not sec_is0(22) + and sec_is0(24) and sec_is0(25) and sec_is0(26) and sec_is0(27) + and sec_is0(28) and sec_is0(29)) or + (not pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(3) + and pri_is0(4) and pri_is0(5) and sec_is0(21) + and not sec_is0(22) and sec_is0(23) and sec_is0(24) + and not sec_is0(25) and sec_is0(26) and sec_is0(27) + and sec_is0(28) and not sec_is0(29) and sec_is0(30)) or + (not pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(3) + and pri_is0(4) and pri_is0(5) and sec_is0(21) + and not sec_is0(22) and not sec_is0(23) and sec_is0(24) + and sec_is0(25) and sec_is0(26) and sec_is0(27) + and sec_is0(28)) or + ( pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(4) + and pri_is0(5) and sec_is0(26) and not sec_is0(27) + and not sec_is0(28) and not sec_is0(29) and sec_is0(30)) or + ( pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(3) + and pri_is0(4) and pri_is0(5) and sec_is0(26) + and not sec_is0(27) and not sec_is0(28) and not sec_is0(29)); + +final_fmul_uc <= ( pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(4) + and pri_is0(5) and sec_is0(26) and not sec_is0(27) + and not sec_is0(28) and not sec_is0(29) and sec_is0(30)); + +only_graphics_mode <= ( pri_is0(0) and pri_is0(1) and pri_is0(2) + and not pri_is0(3) and pri_is0(4) and pri_is0(5) + and not sec_is0(21) and not sec_is0(22) and sec_is0(23) + and sec_is0(24) and not sec_is0(26) and not sec_is0(27) + and sec_is0(28) and not sec_is0(29) and sec_is0(30) + and not sec_is0(31)) or + (not pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(3) + and pri_is0(4) and pri_is0(5) and sec_is0(21) + and not sec_is0(22) and not sec_is0(23) and sec_is0(24) + and sec_is0(25) and sec_is0(26) and sec_is0(27) + and sec_is0(28)) or + (not pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(3) + and pri_is0(4) and pri_is0(5) and sec_is0(21) + and not sec_is0(22) and sec_is0(23) and sec_is0(24) + and not sec_is0(25) and sec_is0(26) and sec_is0(27) + and sec_is0(28) and not sec_is0(29) and sec_is0(30)) or + (not pri_is0(0) and pri_is0(1) and pri_is0(2) and pri_is0(3) + and pri_is0(4) and pri_is0(5) and sec_is0(21) + and not sec_is0(22) and sec_is0(24) and sec_is0(25) + and sec_is0(26) and sec_is0(27) and sec_is0(28) + and sec_is0(29)); + +--@@ ESPRESSO LOGIC END @@ + + + + + + + + + + + + +ldst_tag <= single_precision_ldst & + int_word_ldst & + sign_ext_ldst & -- for lfiwax + ldst_tag_addr(0 to 5); + +tag_in_16to20 <= mftgpr and not io_port; +mftgpr_not_DITC <= mftgpr and not io_port; + +ldst_tag_addr <= (iu_au_is0_ucode_ext(0) & is0_instr(06 to 10)) when tag_in_16to20='0' else + (iu_au_is0_ucode_ext(2) & is0_instr(16 to 20)) ; + +ram_mode_v <= pc_au_ram_mode and pc_au_ram_thread_v; + +------------------------------------------------------------------------------------------------------------------------ +-- config bits +iu_au_config_iucr_din <= iu_au_config_iucr; + + config_reg: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => iu_au_config_iucr_l2'length) + port map ( + vd => vdd, gd => gnd, + forcee => forcee, delay_lclkr => delay_lclkr, + nclk => nclk, mpw1_b => mpw1_b, + act => tiup, mpw2_b => mpw2_b, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + scin => config_reg_scin(0 to 7), + scout => config_reg_scout(0 to 7), + --------------------------------------------- + din => iu_au_config_iucr_din, + --------------------------------------------- + dout => iu_au_config_iucr_l2 + --------------------------------------------- + ); + + +iu_au_config_iucr_int(0 to 7) <= iu_au_config_iucr_l2(0 to 7); + + graphics_mode <= iu_au_config_iucr_int(0); --IUCR2(32) GME +i_afd_config_iucr(1) <= iu_au_config_iucr_int(1); --IUCR2(33) DISBYP +i_afd_config_iucr(2) <= iu_au_config_iucr_int(2); --IUCR2(34) SSAXU +i_afd_config_iucr(3) <= iu_au_config_iucr_int(3); --IUCR2(35) SSUC +i_afd_config_iucr(4) <= iu_au_config_iucr_int(4); --IUCR2(36) RESERVED FOR BGQ (disable store bypass) +i_afd_config_iucr(5) <= iu_au_config_iucr_int(5); --IUCR2(37) DISCGAT (disable clock gating in IU_AXU) +i_afd_config_iucr(6) <= iu_au_config_iucr_int(6); --IUCR2(38) SSFDIVPN (PROPOSED, single step fdiv* and fsqrt* prenorms) +i_afd_config_iucr(7) <= iu_au_config_iucr_int(7); --IUCR2(39) RESERVED FOR BGQ + + +spare_unused(4 to 7) <= tidn & tidn & tidn & tidn; +spare_unused(34) <= io_port_ext; + + +is0_is_ucode <= iu_au_is0_is_ucode; + +in_ucode_mode <= iu_au_is0_is_ucode and is0_instr_v; + +in_fdivsqrt_mode_is0 <= (fdiv_is0 or fsqrt_is0) and (is0_instr_v and not iu_au_is0_flush); +is0_in_divsqrt_mode_or1d <= in_fdivsqrt_mode_is0 or ucmodelat_dout; +ucmodelat_din <= (in_fdivsqrt_mode_is0 or ucmodelat_dout) and (not ifdp_ex5_fmul_uc_complete); + +au_iu_is0_ucode_only <= only_from_ucode; + + +is0_invalid_kill_uc <= (not (in_ucode_mode or ram_mode_v) and only_from_ucode) or -- special ucode instructions getting issued when not doing ucode is bad + (not (graphics_mode or in_ucode_mode or ram_mode_v) and only_graphics_mode); -- can use any graphics mode insr in ucode + + + + +is0_invalid_kill <= (not (graphics_mode or in_ucode_mode or ram_mode_v) and only_graphics_mode); -- can use any graphics mode insr in ucode + +is0_kill_or_divsqrt_b <= not (is0_invalid_kill); + +is0_i_dec_b <= not (isfu_dec_is0 and is0_kill_or_divsqrt_b); -- inverted for timing +au_iu_is0_i_dec_b <= is0_i_dec_b; + +au_iu_is0_i_dec <= not is0_i_dec_b; +spare_unused(2) <= au_iu_is0_i_dec; + +-- fdiv and fsqrt will be handled by ucode. The fu may issue them lateer +-- This signal is passed down the pipe to rf1, because +-- these opcodes are used to initiate some operand checking so they should continue down the pipe and not be flushed because of ucode. + + +-- During fdiv/fsqrt the axu may select this thread before or after the "real" fxu selection. +-- If the axu selects this thread earlier than the fxu, s1 is simply updated early. +-- If the axu selects this thread later than the fxu, ucode instructions would get wiped out by the flush +-- This signal protects the instruction from being flushed +ignore_flush_is0 <= (fdiv_is0 or fsqrt_is0) and isfu_dec_is0; -- these opcodes will not change the FpScr or any Fpr. Only scratch reg s0 will be changed + +-- Source/Target Muxing in IS0 for timing + -- redirect the target of fdiv(s)(.) and fsqrt(s)(.) to scratch register 1 + is0_frt(0 to 5) <= "100001" when (fdiv_is0 ='1' or fsqrt_is0 ='1') else -- scratch reg s1 (prenorm target fdiv, fsqrt) + iu_au_is0_ucode_ext(0) & is0_instr(06 to 10); -- usual case + +is0_st_or_mtdp <= st_is0 and not (mftgpr and not io_port); -- 100, 111 +is0_mftgpr <= st_is0 and mftgpr and not io_port; -- 110 +is0_usual_fra <= not (st_is0 or mftgpr or io_port); -- 000 + +is0_fra_or_frs(0 to 5) <= ((iu_au_is0_ucode_ext(0) & is0_instr(06 to 10)) and (0 to 5 => is0_st_or_mtdp)) or + ((iu_au_is0_ucode_ext(2) & is0_instr(16 to 20)) and (0 to 5 => is0_mftgpr)) or + ((iu_au_is0_ucode_ext(1) & is0_instr(11 to 15)) and (0 to 5 => is0_usual_fra)); + +------------------------------------------------------------------------------------------------------------------------ + +is0_to_ucode <= (iu_au_is0_2ucode or fdiv_is0 or fsqrt_is0) and isfu_dec_is0; --uCode from either a denorm or fdiv(s)(.) or fsqrt(s)(.) +au_iu_is0_to_ucode <= (iu_au_is0_2ucode or fdiv_is0 or fsqrt_is0) and isfu_dec_is0; + +au_iu_is0_ldst <= ld_st_is0; +au_iu_is0_ldst_v <= ld_st_is0 and not is0_invalid_kill; +au_iu_is0_st_v <= st_is0 and not is0_invalid_kill; + +au_iu_is0_instr_type <= "001"; -- 0=AP,1=Vec,2=FP + +au_iu_is0_mffgpr <= mffgpr; -- and ld_st_is0; -- This is for LVSL, and also misaligned loads +au_iu_is0_mftgpr <= mftgpr; -- and ld_st_is0; -- This is for misaligned stores + +au_iu_is0_movedp <= io_port and ld_st_is0; + +au_iu_is0_ldst_size <= size(0 to 5); +au_iu_is0_ldst_tag <= ldst_tag; +au_iu_is0_ldst_ra_v <= ld_st_is0 and (not mftgpr or (io_port and indexed)); -- mftgpr uses ra as targ, + -- but don't want source dep checks +au_iu_is0_ldst_ra <= '0' & iu_au_is0_ucode_ext(1) & is0_instr(11 to 15) when mftgpr_not_DITC='0' else + '0' & iu_au_is0_ucode_ext(0) & is0_instr( 6 to 10); -- for mftgpr, make RA the target, same as updates +au_iu_is0_ldst_rb_v <= (indexed or mffgpr) and ld_st_is0; +au_iu_is0_ldst_rb <= '0' & iu_au_is0_ucode_ext(2) & is0_instr(16 to 20); -- todo should ucode bit be tied down? should be okay if we don't use AXU ldst's in ucode +au_iu_is0_ldst_dimm <= is0_instr(16 to 31); +au_iu_is0_ldst_indexed <= indexed; +au_iu_is0_ldst_update <= update_form; +au_iu_is0_ldst_forcealign <= forcealign; +au_iu_is0_ldst_forceexcept <= '0'; + +au_iu_is0_ldst_extpid <= ldst_extpid; + + + +------------------------------------------------------------------------------------------------------------------------ + + + + +is1_v_nstall1_b_NAND2: is1_v_nstall1_b <= not( is1_stall_b and is0_ins_v ); +is1_v_nstall2_b_NAND2: is1_v_nstall2_b <= not( is1_stall_b and is0_ins_v ); + +is1_v_nstall1_INV: is1_v_nstall1 <= not( is1_v_nstall1_b ); +is1_v_nstall2_INV: is1_v_nstall2 <= not( is1_v_nstall1_b ); +is1_v_nstall3_INV: is1_v_nstall3 <= not( is1_v_nstall1_b ); +is1_v_nstall4_INV: is1_v_nstall4 <= not( is1_v_nstall1_b ); + +is1_v_nstall5_INV: is1_v_nstall5 <= not( is1_v_nstall2_b ); +is1_v_nstall6_INV: is1_v_nstall6 <= not( is1_v_nstall2_b ); +is1_v_nstall7_INV: is1_v_nstall7 <= not( is1_v_nstall2_b ); +is1_v_nstall8_INV: is1_v_nstall8 <= not( is1_v_nstall2_b ); + + +is1_v_nstall01_INVaa: is1_v_nstall01_INVA_b <= not( is1_v_nstall1); +is1_v_nstall02_INVaa: is1_v_nstall02_INVA_b <= not( is1_v_nstall1); +is1_v_nstall03_INVaa: is1_v_nstall03_INVA_b <= not( is1_v_nstall1); +is1_v_nstall04_INVaa: is1_v_nstall04_INVA_b <= not( is1_v_nstall1); +is1_v_nstall05_INVaa: is1_v_nstall05_INVA_b <= not( is1_v_nstall2); +is1_v_nstall06_INVaa: is1_v_nstall06_INVA_b <= not( is1_v_nstall2); +is1_v_nstall07_INVaa: is1_v_nstall07_INVA_b <= not( is1_v_nstall2); +is1_v_nstall08_INVaa: is1_v_nstall08_INVA_b <= not( is1_v_nstall2); +is1_v_nstall09_INVaa: is1_v_nstall09_INVA_b <= not( is1_v_nstall3); +is1_v_nstall10_INVaa: is1_v_nstall10_INVA_b <= not( is1_v_nstall3); +is1_v_nstall11_INVaa: is1_v_nstall11_INVA_b <= not( is1_v_nstall3); +is1_v_nstall12_INVaa: is1_v_nstall12_INVA_b <= not( is1_v_nstall3); +is1_v_nstall13_INVaa: is1_v_nstall13_INVA_b <= not( is1_v_nstall4); +is1_v_nstall14_INVaa: is1_v_nstall14_INVA_b <= not( is1_v_nstall4); +is1_v_nstall15_INVaa: is1_v_nstall15_INVA_b <= not( is1_v_nstall4); +is1_v_nstall16_INVaa: is1_v_nstall16_INVA_b <= not( is1_v_nstall4); +is1_v_nstall17_INVaa: is1_v_nstall17_INVA_b <= not( is1_v_nstall5); +is1_v_nstall18_INVaa: is1_v_nstall18_INVA_b <= not( is1_v_nstall5); +is1_v_nstall19_INVaa: is1_v_nstall19_INVA_b <= not( is1_v_nstall5); +is1_v_nstall20_INVaa: is1_v_nstall20_INVA_b <= not( is1_v_nstall5); +is1_v_nstall21_INVaa: is1_v_nstall21_INVA_b <= not( is1_v_nstall6); +is1_v_nstall22_INVaa: is1_v_nstall22_INVA_b <= not( is1_v_nstall6); +is1_v_nstall23_INVaa: is1_v_nstall23_INVA_b <= not( is1_v_nstall6); +is1_v_nstall24_INVaa: is1_v_nstall24_INVA_b <= not( is1_v_nstall6); +is1_v_nstall25_INVaa: is1_v_nstall25_INVA_b <= not( is1_v_nstall7); +is1_v_nstall26_INVaa: is1_v_nstall26_INVA_b <= not( is1_v_nstall7); +is1_v_nstall27_INVaa: is1_v_nstall27_INVA_b <= not( is1_v_nstall7); +is1_v_nstall28_INVaa: is1_v_nstall28_INVA_b <= not( is1_v_nstall7); +is1_v_nstall29_INVaa: is1_v_nstall29_INVA_b <= not( is1_v_nstall8); +is1_v_nstall30_INVaa: is1_v_nstall30_INVA_b <= not( is1_v_nstall8); +is1_v_nstall31_INVaa: is1_v_nstall31_INVA_b <= not( is1_v_nstall8); +is1_v_nstall32_INVaa: is1_v_nstall32_INVA_b <= not( is1_v_nstall8); + + + +is1_v_nstall01_INVbb: is1_v_nstall01_INVB <= not( is1_v_nstall01_INVA_b ); +is1_v_nstall02_INVbb: is1_v_nstall02_INVB <= not( is1_v_nstall02_INVA_b ); +is1_v_nstall03_INVbb: is1_v_nstall03_INVB <= not( is1_v_nstall03_INVA_b ); +is1_v_nstall04_INVbb: is1_v_nstall04_INVB <= not( is1_v_nstall04_INVA_b ); +is1_v_nstall05_INVbb: is1_v_nstall05_INVB <= not( is1_v_nstall05_INVA_b ); +is1_v_nstall06_INVbb: is1_v_nstall06_INVB <= not( is1_v_nstall06_INVA_b ); +is1_v_nstall07_INVbb: is1_v_nstall07_INVB <= not( is1_v_nstall07_INVA_b ); +is1_v_nstall08_INVbb: is1_v_nstall08_INVB <= not( is1_v_nstall08_INVA_b ); +is1_v_nstall09_INVbb: is1_v_nstall09_INVB <= not( is1_v_nstall09_INVA_b ); +is1_v_nstall10_INVbb: is1_v_nstall10_INVB <= not( is1_v_nstall10_INVA_b ); +is1_v_nstall11_INVbb: is1_v_nstall11_INVB <= not( is1_v_nstall11_INVA_b ); +is1_v_nstall12_INVbb: is1_v_nstall12_INVB <= not( is1_v_nstall12_INVA_b ); +is1_v_nstall13_INVbb: is1_v_nstall13_INVB <= not( is1_v_nstall13_INVA_b ); +is1_v_nstall14_INVbb: is1_v_nstall14_INVB <= not( is1_v_nstall14_INVA_b ); +is1_v_nstall15_INVbb: is1_v_nstall15_INVB <= not( is1_v_nstall15_INVA_b ); +is1_v_nstall16_INVbb: is1_v_nstall16_INVB <= not( is1_v_nstall16_INVA_b ); +is1_v_nstall17_INVbb: is1_v_nstall17_INVB <= not( is1_v_nstall17_INVA_b ); +is1_v_nstall18_INVbb: is1_v_nstall18_INVB <= not( is1_v_nstall18_INVA_b ); +is1_v_nstall19_INVbb: is1_v_nstall19_INVB <= not( is1_v_nstall19_INVA_b ); +is1_v_nstall20_INVbb: is1_v_nstall20_INVB <= not( is1_v_nstall20_INVA_b ); +is1_v_nstall21_INVbb: is1_v_nstall21_INVB <= not( is1_v_nstall21_INVA_b ); +is1_v_nstall22_INVbb: is1_v_nstall22_INVB <= not( is1_v_nstall22_INVA_b ); +is1_v_nstall23_INVbb: is1_v_nstall23_INVB <= not( is1_v_nstall23_INVA_b ); +is1_v_nstall24_INVbb: is1_v_nstall24_INVB <= not( is1_v_nstall24_INVA_b ); +is1_v_nstall25_INVbb: is1_v_nstall25_INVB <= not( is1_v_nstall25_INVA_b ); +is1_v_nstall26_INVbb: is1_v_nstall26_INVB <= not( is1_v_nstall26_INVA_b ); +is1_v_nstall27_INVbb: is1_v_nstall27_INVB <= not( is1_v_nstall27_INVA_b ); +is1_v_nstall28_INVbb: is1_v_nstall28_INVB <= not( is1_v_nstall28_INVA_b ); +is1_v_nstall29_INVbb: is1_v_nstall29_INVB <= not( is1_v_nstall29_INVA_b ); +is1_v_nstall30_INVbb: is1_v_nstall30_INVB <= not( is1_v_nstall30_INVA_b ); +is1_v_nstall31_INVbb: is1_v_nstall31_INVB <= not( is1_v_nstall31_INVA_b ); +is1_v_nstall32_INVbb: is1_v_nstall32_INVB <= not( is1_v_nstall32_INVA_b ); + + + iu_au_is0_flush_b <= not iu_au_is0_flush ; + iu_au_is1_flush_b <= not iu_au_is1_flush ; + + cmd_is0_40_part <= ld_st_is0 and isfu_dec_is0 ; + cmd_is0_41_part <= st_is0 and isfu_dec_is0 ; + cmd_is0_43_part <= is0_ins_v and isfu_dec_is0 and not is0_invalid_kill_uc; + cmd_is0_50_part <= bubble3 and isfu_dec_is0 ; + + + cmd_is1_go_06: cmd_is0_go_b( 6) <= not( is1_v_nstall01_INVB and is0_frt(1) ); + cmd_is1_go_07: cmd_is0_go_b( 7) <= not( is1_v_nstall02_INVB and is0_frt(2) ); + cmd_is1_go_08: cmd_is0_go_b( 8) <= not( is1_v_nstall03_INVB and is0_frt(3) ); + cmd_is1_go_09: cmd_is0_go_b( 9) <= not( is1_v_nstall04_INVB and is0_frt(4) ); + cmd_is1_go_10: cmd_is0_go_b(10) <= not( is1_v_nstall05_INVB and is0_frt(5) ); + cmd_is1_go_11: cmd_is0_go_b(11) <= not( is1_v_nstall06_INVB and is0_fra_or_frs(1) ); + cmd_is1_go_12: cmd_is0_go_b(12) <= not( is1_v_nstall07_INVB and is0_fra_or_frs(2) ); + cmd_is1_go_13: cmd_is0_go_b(13) <= not( is1_v_nstall08_INVB and is0_fra_or_frs(3) ); + cmd_is1_go_14: cmd_is0_go_b(14) <= not( is1_v_nstall09_INVB and is0_fra_or_frs(4) ); + cmd_is1_go_15: cmd_is0_go_b(15) <= not( is1_v_nstall10_INVB and is0_fra_or_frs(5) ); + cmd_is1_go_16: cmd_is0_go_b(16) <= not( is1_v_nstall11_INVB and is0_ins_dly(16) ); + cmd_is1_go_17: cmd_is0_go_b(17) <= not( is1_v_nstall12_INVB and is0_ins_dly(17) ); + cmd_is1_go_18: cmd_is0_go_b(18) <= not( is1_v_nstall13_INVB and is0_ins_dly(18) ); + cmd_is1_go_19: cmd_is0_go_b(19) <= not( is1_v_nstall14_INVB and is0_ins_dly(19) ); + cmd_is1_go_20: cmd_is0_go_b(20) <= not( is1_v_nstall15_INVB and is0_ins_dly(20) ); + cmd_is1_go_21: cmd_is0_go_b(21) <= not( is1_v_nstall16_INVB and is0_ins_dly(21) ); + cmd_is1_go_22: cmd_is0_go_b(22) <= not( is1_v_nstall17_INVB and is0_ins_dly(22) ); + cmd_is1_go_23: cmd_is0_go_b(23) <= not( is1_v_nstall18_INVB and is0_ins_dly(23) ); + cmd_is1_go_24: cmd_is0_go_b(24) <= not( is1_v_nstall19_INVB and is0_ins_dly(24) ); + cmd_is1_go_25: cmd_is0_go_b(25) <= not( is1_v_nstall19_INVB and is0_ins_dly(25) ); +cmd_is0_go_b(26) <= tidn; -- spare +cmd_is0_go_b(27) <= tidn; -- spare +cmd_is0_go_b(28) <= tidn; -- spare +cmd_is0_go_b(29) <= tidn; -- spare +cmd_is0_go_b(30) <= tidn; -- spare +cmd_is0_go_b(31) <= tidn; -- spare + +spare_unused(35 to 40) <= cmd_is0_go_b(26 to 31); + + + cmd_is1_go_32: cmd_is0_go_b(32) <= not( is1_v_nstall20_INVB and is0_frt(0) ); + cmd_is1_go_33: cmd_is0_go_b(33) <= not( is1_v_nstall20_INVB and is0_fra_or_frs(0) ); + cmd_is1_go_34: cmd_is0_go_b(34) <= not( is1_v_nstall21_INVB and iu_au_is0_ucode_ext(2) ); + cmd_is1_go_35: cmd_is0_go_b(35) <= not( is1_v_nstall21_INVB and iu_au_is0_ucode_ext(3) ); + cmd_is1_go_36: cmd_is0_go_b(36) <= not( is1_v_nstall22_INVB and tv ); + cmd_is1_go_37: cmd_is0_go_b(37) <= not( is1_v_nstall22_INVB and av ); + cmd_is1_go_38: cmd_is0_go_b(38) <= not( is1_v_nstall23_INVB and bv ); + cmd_is1_go_39: cmd_is0_go_b(39) <= not( is1_v_nstall23_INVB and cv ); + cmd_is1_go_40: cmd_is0_go_b(40) <= not( is1_v_nstall29_INVB and iu_au_is0_flush_b and cmd_is0_40_part ); + cmd_is1_go_41: cmd_is0_go_b(41) <= not( is1_v_nstall30_INVB and iu_au_is0_flush_b and cmd_is0_41_part ); + cmd_is1_go_42: cmd_is0_go_b(42) <= not( is1_v_nstall24_INVB and cr_writer ); + cmd_is1_go_43: cmd_is0_go_b(43) <= not( is1_v_nstall31_INVB and iu_au_is0_flush_b and cmd_is0_43_part ); + cmd_is1_go_44: cmd_is0_go_b(44) <= not( is1_v_nstall24_INVB and is0_in_divsqrt_mode_or1d ); + cmd_is1_go_45: cmd_is0_go_b(45) <= not( is1_v_nstall25_INVB and tidn ); + cmd_is1_go_46: cmd_is0_go_b(46) <= ucode_restart; + cmd_is1_go_47: cmd_is0_go_b(47) <= not( is1_v_nstall26_INVB and is0_is_ucode ); + cmd_is1_go_48: cmd_is0_go_b(48) <= not( is1_v_nstall26_INVB and iu_au_is0_cr_setter ); + cmd_is1_go_49: cmd_is0_go_b(49) <= not( is1_v_nstall27_INVB and final_fmul_uc ); + cmd_is1_go_50: cmd_is0_go_b(50) <= not( is1_v_nstall27_INVB and cmd_is0_50_part ); + cmd_is1_go_51: cmd_is0_go_b(51) <= not( is1_v_nstall28_INVB and prebubble1 ); + cmd_is1_go_52: cmd_is0_go_b(52) <= not( is1_v_nstall32_INVB and iu_au_is0_flush_b and ignore_flush_is0 ); + cmd_is1_go_53: cmd_is0_go_b(53) <= not( is1_v_nstall28_INVB and is0_to_ucode ); + + + + + cmd_is1_ho_06: cmd_is1_ho_b( 6) <= not( is1_v_nstall01_INVA_b and is1_frt_buf(2) ); + cmd_is1_ho_07: cmd_is1_ho_b( 7) <= not( is1_v_nstall02_INVA_b and is1_frt_buf(3) ); + cmd_is1_ho_08: cmd_is1_ho_b( 8) <= not( is1_v_nstall03_INVA_b and is1_frt_buf(4) ); + cmd_is1_ho_09: cmd_is1_ho_b( 9) <= not( is1_v_nstall04_INVA_b and is1_frt_buf(5) ); + cmd_is1_ho_10: cmd_is1_ho_b(10) <= not( is1_v_nstall05_INVA_b and is1_frt_buf(6) ); + cmd_is1_ho_11: cmd_is1_ho_b(11) <= not( is1_v_nstall06_INVA_b and is1_fra_buf(2) ); + cmd_is1_ho_12: cmd_is1_ho_b(12) <= not( is1_v_nstall07_INVA_b and is1_fra_buf(3) ); + cmd_is1_ho_13: cmd_is1_ho_b(13) <= not( is1_v_nstall08_INVA_b and is1_fra_buf(4) ); + cmd_is1_ho_14: cmd_is1_ho_b(14) <= not( is1_v_nstall09_INVA_b and is1_fra_buf(5) ); + cmd_is1_ho_15: cmd_is1_ho_b(15) <= not( is1_v_nstall10_INVA_b and is1_fra_buf(6) ); + cmd_is1_ho_16: cmd_is1_ho_b(16) <= not( is1_v_nstall11_INVA_b and is1_frb_buf(2) ); + cmd_is1_ho_17: cmd_is1_ho_b(17) <= not( is1_v_nstall12_INVA_b and is1_frb_buf(3) ); + cmd_is1_ho_18: cmd_is1_ho_b(18) <= not( is1_v_nstall13_INVA_b and is1_frb_buf(4) ); + cmd_is1_ho_19: cmd_is1_ho_b(19) <= not( is1_v_nstall14_INVA_b and is1_frb_buf(5) ); + cmd_is1_ho_20: cmd_is1_ho_b(20) <= not( is1_v_nstall15_INVA_b and is1_frb_buf(6) ); + cmd_is1_ho_21: cmd_is1_ho_b(21) <= not( is1_v_nstall16_INVA_b and is1_frc_buf(2) ); + cmd_is1_ho_22: cmd_is1_ho_b(22) <= not( is1_v_nstall16_INVA_b and is1_frc_buf(3) ); + cmd_is1_ho_23: cmd_is1_ho_b(23) <= not( is1_v_nstall17_INVA_b and is1_frc_buf(4) ); + cmd_is1_ho_24: cmd_is1_ho_b(24) <= not( is1_v_nstall17_INVA_b and is1_frc_buf(5) ); + cmd_is1_ho_25: cmd_is1_ho_b(25) <= not( is1_v_nstall18_INVA_b and is1_frc_buf(6) ); +cmd_is1_ho_b(26) <= tidn; -- spare +cmd_is1_ho_b(27) <= tidn; -- spare +cmd_is1_ho_b(28) <= tidn; -- spare +cmd_is1_ho_b(29) <= tidn; -- spare +cmd_is1_ho_b(30) <= tidn; -- spare +cmd_is1_ho_b(31) <= tidn; -- spare +spare_unused(41 to 46) <= cmd_is1_ho_b(26 to 31); + + cmd_is1_ho_32: cmd_is1_ho_b(32) <= not( is1_v_nstall18_INVA_b and is1_frt_buf(1) ); + cmd_is1_ho_33: cmd_is1_ho_b(33) <= not( is1_v_nstall19_INVA_b and is1_fra_buf(1) ); + cmd_is1_ho_34: cmd_is1_ho_b(34) <= not( is1_v_nstall19_INVA_b and is1_frb_buf(1) ); + cmd_is1_ho_35: cmd_is1_ho_b(35) <= not( is1_v_nstall20_INVA_b and is1_frc_buf(1) ); + cmd_is1_ho_36: cmd_is1_ho_b(36) <= not( is1_v_nstall20_INVA_b and cmd_is1_l2(36) ); + cmd_is1_ho_37: cmd_is1_ho_b(37) <= not( is1_v_nstall21_INVA_b and cmd_is1_l2(37) ); + cmd_is1_ho_38: cmd_is1_ho_b(38) <= not( is1_v_nstall21_INVA_b and cmd_is1_l2(38) ); + cmd_is1_ho_39: cmd_is1_ho_b(39) <= not( is1_v_nstall22_INVA_b and cmd_is1_l2(39) ); + cmd_is1_ho_40: cmd_is1_ho_b(40) <= not( is1_v_nstall26_INVA_b and iu_au_is1_flush_b and is1_stall and cmd_is1_l2(40) );-- -- ldst val + cmd_is1_ho_41: cmd_is1_ho_b(41) <= not( is1_v_nstall27_INVA_b and iu_au_is1_flush_b and is1_stall and cmd_is1_l2(41) );-- -- st val + cmd_is1_ho_42: cmd_is1_ho_b(42) <= not( is1_v_nstall22_INVA_b and cmd_is1_l2(42) ); + cmd_is1_ho_43: cmd_is1_ho_b(43) <= not( is1_v_nstall28_INVA_b and iu_au_is1_flush_b and is1_stall and cmd_is1_l2(43) );-- -- Valid + cmd_is1_ho_44: cmd_is1_ho_b(44) <= not( is1_v_nstall29_INVA_b and iu_au_is1_flush_b and is1_stall and cmd_is1_l2(44) ); + cmd_is1_ho_45: cmd_is1_ho_b(45) <= not( is1_v_nstall23_INVA_b and cmd_is1_l2(45) ); + cmd_is1_ho_46: cmd_is1_ho_b(46) <= tidn; + cmd_is1_ho_47: cmd_is1_ho_b(47) <= not( is1_v_nstall24_INVA_b and cmd_is1_l2(47) ); + cmd_is1_ho_48: cmd_is1_ho_b(48) <= not( is1_v_nstall24_INVA_b and cmd_is1_l2(48) ); + cmd_is1_ho_49: cmd_is1_ho_b(49) <= not( is1_v_nstall30_INVA_b and iu_au_is1_flush_b and is1_stall and cmd_is1_l2(49) ); + cmd_is1_ho_50: cmd_is1_ho_b(50) <= not( is1_v_nstall31_INVA_b and iu_au_is1_flush_b and is1_stall and cmd_is1_l2(50) );-- -- bubble3 + cmd_is1_ho_51: cmd_is1_ho_b(51) <= not( is1_v_nstall25_INVA_b and cmd_is1_l2(51) ); + cmd_is1_ho_52: cmd_is1_ho_b(52) <= not( is1_v_nstall32_INVA_b and iu_au_is1_flush_b and is1_stall and cmd_is1_l2(52) );-- -- ignore flush + cmd_is1_ho_53: cmd_is1_ho_b(53) <= not( is1_v_nstall25_INVA_b and cmd_is1_l2(53) ); + + + + + + + is1_cmd_din_a: cmd_is0_ld(06 to 25) <= not( cmd_is0_go_b(6 to 25) and cmd_is1_ho_b(6 to 25) ); + is1_cmd_din_b: cmd_is0_ld(32 to 53) <= not( cmd_is0_go_b(32 to 53) and cmd_is1_ho_b(32 to 53) ); + + + cmd_is0_ld(26) <= ucmodelat_din; + + cmd_is0_ld(27 to 31) <= cmd_is1_l2(27 to 31); -- spares + + + -- note that ibuf=>true and init=>1 in this latch here (prevents a built in inverter on the output) + cmd_reg_is1: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, ibuf => false, width => 48) + port map ( + vd => vdd, gd => gnd, + forcee => forcee, delay_lclkr => delay_lclkr, + nclk => nclk, mpw1_b => mpw1_b, + act => tiup, mpw2_b => mpw2_b, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + scin => cmd_is1_scin(6 to 53), + scout => cmd_is1_scout(6 to 53), + --------------------------------------------- + din => cmd_is0_ld, + --------------------------------------------- + dout => cmd_is1_l2 + --------------------------------------------- + ); + + + + ucmodelat_dout <= cmd_is1_l2(26); + + i_afd_fmul_uc_is1 <= cmd_is1_l2(49); + is1_fmul_uc <= cmd_is1_l2(49); + + i_afd_is1_is_ucode <= cmd_is1_l2(47); -- to _fu_dep for div and sqrt + i_afd_is1_to_ucode <= cmd_is1_l2(53); -- to _fu_dep for div and sqrt + is1_is_ucode <= cmd_is1_l2(47); -- to _fu_dep for div and sqrt + is1_to_ucode <= cmd_is1_l2(53); -- to _fu_dep for div and sqrt + + spare_unused(3) <= tidn; + spare_unused(8 to 11) <= tidn & tidn & tidn & tidn; + + + + + -- internal renaming + is1_instr_v <= cmd_is1_l2(43); + is1_ldst <= cmd_is1_l2(40); + is1_st <= cmd_is1_l2(41); + + + + + -- external signals + i_afd_is1_frt(0 to 6) <= tidn & cmd_is1_l2(32) & cmd_is1_l2(06 to 10); + + i_afd_is1_fra(0 to 6) <= tidn & cmd_is1_l2(33) & cmd_is1_l2(11 to 15); + + i_afd_is1_frb(0 to 6) <= tidn & cmd_is1_l2(34) & cmd_is1_l2(16 to 20); -- cmd_is1_l2(35) indicates scratch reg + + i_afd_is1_frc(0 to 6) <= tidn & cmd_is1_l2(35) & cmd_is1_l2(21 to 25); -- cmd_is1_l2(34) indicates scratch reg + + -- buffered these off for timing + is1frtbufa: is1_frt_buf_b <= not (cmd_is1_l2(32) & cmd_is1_l2(06 to 10)); + is1frabufa: is1_fra_buf_b <= not (cmd_is1_l2(33) & cmd_is1_l2(11 to 15)); + is1frbbufa: is1_frb_buf_b <= not (cmd_is1_l2(34) & cmd_is1_l2(16 to 20)); + is1frcbufa: is1_frc_buf_b <= not (cmd_is1_l2(35) & cmd_is1_l2(21 to 25)); + + is1frtbufb: is1_frt_buf <= not is1_frt_buf_b; + is1frabufb: is1_fra_buf <= not is1_fra_buf_b; + is1frbbufb: is1_frb_buf <= not is1_frb_buf_b; + is1frcbufb: is1_frc_buf <= not is1_frc_buf_b; + + i_afd_is1_frt_buf <= is1_frt_buf; + i_afd_is1_fra_buf <= is1_fra_buf; + i_afd_is1_frb_buf <= is1_frb_buf; + i_afd_is1_frc_buf <= is1_frc_buf; + + + i_afd_is1_est_bubble3 <= cmd_is1_l2(50); + i_afd_is1_prebubble1 <= cmd_is1_l2(51) or cmd_is1_l2(52); + + i_afd_is1_instr_v <= is1_instr_v; + + + i_afd_is1_cr_writer <= cmd_is1_l2(42); + is1_cr_writer <= cmd_is1_l2(42); + spare_unused(47) <= cmd_is1_l2(46); + + i_afd_is1_cr_setter <= cmd_is1_l2(48); -- fxu + is1_cr_setter <= cmd_is1_l2(48); -- fxu cr setter + + is1_in_divsqrt_mode_or1d <= cmd_is1_l2(44); + i_afd_in_ucode_mode_or1d <= is1_in_divsqrt_mode_or1d; + + i_afd_is1_frt_v <= cmd_is1_l2(36); + i_afd_is1_fra_v <= cmd_is1_l2(37); + i_afd_is1_frb_v <= cmd_is1_l2(38); + i_afd_is1_frc_v <= cmd_is1_l2(39); + is1_frt_v <= cmd_is1_l2(36); + is1_fra_v <= cmd_is1_l2(37); + is1_frb_v <= cmd_is1_l2(38); + is1_frc_v <= cmd_is1_l2(39); + + i_afd_is1_instr_ldst_v <= is1_ldst; + i_afd_is1_instr_ld_v <= is1_ldst and not is1_st; + i_afd_is1_instr_sto_v <= is1_st; + + i_afd_is1_divsqrt <= cmd_is1_l2(52); + i_afd_is1_stall_rep <= is1_stall; + + + i_afd_ignore_flush_is1 <= cmd_is1_l2(52) ; + + + + + + + +fu_dec_debug(0 to 13) <= is1_instr_v & -- 00 + is1_frt_v & -- 01 + is1_fra_v & -- 02 + is1_frb_v & -- 03 + is1_frc_v & -- 04 + is1_ldst & -- 05 + is1_st & -- 06 + is1_cr_setter & -- 07 FXU CR + is1_cr_writer & -- 08 AXU CR + is1_is_ucode & -- 09 + is1_to_ucode & -- 10 + is1_frt_buf(1) & -- 11 frt scratch bit + is1_fmul_uc & -- 12 + is1_in_divsqrt_mode_or1d; -- 13 + + + +-- ################################################## +-- pre-scanopt scanchain + +config_reg_scin(0) <= i_dec_si; +config_reg_scin(1 to 7) <= config_reg_scout(0 to 6); + +cmd_is1_scin(6) <= config_reg_scout(7); +cmd_is1_scin(7 to 53) <= cmd_is1_scout(6 to 52); -- starts with bit 6 + +i_dec_so <= cmd_is1_scout(53); + + +end iuq_axu_fu_dec; diff --git a/rel/src/vhdl/work/iuq_axu_fu_dep.vhdl b/rel/src/vhdl/work/iuq_axu_fu_dep.vhdl new file mode 100644 index 0000000..2621162 --- /dev/null +++ b/rel/src/vhdl/work/iuq_axu_fu_dep.vhdl @@ -0,0 +1,2141 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + use work.iuq_pkg.all; + +--------------------------------------------------------------------- + + +entity iuq_axu_fu_dep is +generic( + expand_type : integer := 2; + fpr_addr_width : integer := 5; + lmq_entries : integer := 8; + needs_sreset : integer := 1); +port( + nclk : in clk_logic; + --------------------------------------------------------------------- + vdd : inout power_logic; + gnd : inout power_logic; + --------------------------------------------------------------------- + i_dep_si : in std_ulogic; + i_dep_so : out std_ulogic; + + pc_iu_func_sl_thold_0_b : in std_ulogic; + pc_iu_sg_0 : in std_ulogic; + forcee : in std_ulogic; + d_mode : in std_ulogic; + delay_lclkr : in std_ulogic; + mpw1_b : in std_ulogic; + mpw2_b : in std_ulogic; + + --------------------------------------------------------------------- + + i_afd_is1_is_ucode : in std_ulogic; + i_afd_is1_to_ucode : in std_ulogic; + i_afd_is2_is_ucode : out std_ulogic; + + i_afd_config_iucr : in std_ulogic_vector(1 to 7); -- IUCR2(33:39) + + + i_afd_is1_instr_v : in std_ulogic; + i_afd_is1_instr : in std_ulogic_vector(26 to 31); + + i_afd_is1_fra_v : in std_ulogic; + i_afd_is1_frb_v : in std_ulogic; + i_afd_is1_frc_v : in std_ulogic; + i_afd_is1_frt_v : in std_ulogic; + + i_afd_is1_prebubble1 : in std_ulogic; + i_afd_is1_est_bubble3 : in std_ulogic; + + iu_au_is1_cr_user_v : in std_ulogic; -- FXU op reads CR + i_afd_is1_cr_setter : in std_ulogic; -- FXU op alters CR + i_afd_is1_cr_writer : in std_ulogic; -- AXU op alters CR + + i_afd_is1_fra : in std_ulogic_vector(0 to 6); + i_afd_is1_frb : in std_ulogic_vector(0 to 6); + i_afd_is1_frc : in std_ulogic_vector(0 to 6); + i_afd_is1_frt : in std_ulogic_vector(0 to 6); + i_afd_is1_fra_buf : in std_ulogic_vector(1 to 6); + i_afd_is1_frb_buf : in std_ulogic_vector(1 to 6); + i_afd_is1_frc_buf : in std_ulogic_vector(1 to 6); + i_afd_is1_frt_buf : in std_ulogic_vector(1 to 6); + + i_afd_is1_ifar : in std_ulogic_vector(56 to 61); + + i_afd_is1_instr_ldst_v : in std_ulogic; + i_afd_is1_instr_ld_v : in std_ulogic; + i_afd_is1_instr_sto_v : in std_ulogic; + + --------------------------------------------------------------------- + + i_afi_is2_take : in std_ulogic; + + -- LMQ signals + --------------------------------------------------------------------- + xu_au_loadmiss_vld : in std_ulogic; + xu_au_loadmiss_qentry : in std_ulogic_vector(0 to lmq_entries-1); + xu_au_loadmiss_target : in std_ulogic_vector(0 to 8); + xu_au_loadmiss_target_type : in std_ulogic_vector(0 to 1); + + xu_au_loadmiss_complete_vld : in std_ulogic; + xu_au_loadmiss_complete_qentry : in std_ulogic_vector(0 to lmq_entries-1); + xu_au_loadmiss_complete_type : in std_ulogic_vector(0 to 1); + + -- AXU signals + --------------------------------------------------------------------- + iu_au_is1_hold : in std_ulogic; + + iu_au_is1_instr_match : in std_ulogic; + + iu_au_is2_stall : in std_ulogic; + + xu_iu_is2_flush : in std_ulogic; + + iu_au_is1_flush : in std_ulogic; + iu_au_is2_flush : in std_ulogic; + iu_au_rf0_flush : in std_ulogic; + iu_au_rf1_flush : in std_ulogic; + iu_au_ex1_flush : in std_ulogic; + iu_au_ex2_flush : in std_ulogic; + iu_au_ex3_flush : in std_ulogic; + iu_au_ex4_flush : in std_ulogic; + iu_au_ex5_flush : in std_ulogic; + + au_iu_is1_dep_hit : out std_ulogic; + au_iu_is1_dep_hit_b : out std_ulogic; + + au_iu_is2_issue_stall : out std_ulogic; + --------------------------------------------------------------------- + + i_axu_is1_early_v : out std_ulogic; + + i_axu_is2_instr_v : out std_ulogic; + + i_axu_is2_instr_match : out std_ulogic; + --------------------------------------------------------------------- + + i_axu_is2_fra : out std_ulogic_vector(0 to 6); + i_axu_is2_frb : out std_ulogic_vector(0 to 6); + i_axu_is2_frc : out std_ulogic_vector(0 to 6); + i_axu_is2_frt : out std_ulogic_vector(0 to 6); + + i_axu_is2_fra_v : out std_ulogic; + i_axu_is2_frb_v : out std_ulogic; + i_axu_is2_frc_v : out std_ulogic; + + + --------------------------------------------------------------------- + fu_iu_uc_special : in std_ulogic; + + iu_fu_ex2_n_flush : out std_ulogic; + + --------------------------------------------------------------------- + + ifdp_is2_est_bubble3 : out std_ulogic; + ifdp_ex5_fmul_uc_complete : out std_ulogic; + ifdp_is2_bypsel : out std_ulogic_vector(0 to 5); + + i_afd_ignore_flush_is1 : in std_ulogic; + i_afd_ignore_flush_is2 : out std_ulogic; + + i_afd_is1_divsqrt : in std_ulogic; + i_afd_is1_stall_rep : in std_ulogic; + + i_afd_fmul_uc_is1 : in std_ulogic; + i_afd_in_ucode_mode_or1d : in std_ulogic; + i_afd_in_ucode_mode_or1d_b : out std_ulogic; + + fu_dep_debug : out std_ulogic_vector(0 to 23); + au_iu_is2_axubusy : out std_ulogic -- for single step + + + ); + + -- synopsys translate_off + + -- synopsys translate_on + + +end iuq_axu_fu_dep; + +-------------------------------------------------------------------------------------------------------------------------------------------------------- + +architecture iuq_axu_fu_dep of iuq_axu_fu_dep is + +signal tidn : std_ulogic; +signal tiup : std_ulogic; + +signal is1_ex6_a_bypass, is1_ex6_b_bypass, is1_ex6_c_bypass : std_ulogic; + +signal spare_unused : std_ulogic_vector(00 to 58); +signal iucr2_ss_ignore_flush,disable_cgat : std_ulogic; + +signal lm_tar : std_ulogic_vector(0 to 5); +signal lm0_valid : std_ulogic; +signal lm0_valid_din : std_ulogic; +signal lm0_ta : std_ulogic_vector(0 to 5); +signal lm0_ta_din : std_ulogic_vector(0 to 5); +signal lm1_valid : std_ulogic; +signal lm1_valid_din : std_ulogic; +signal lm1_ta : std_ulogic_vector(0 to 5); +signal lm1_ta_din : std_ulogic_vector(0 to 5); +signal lm2_valid : std_ulogic; +signal lm2_valid_din : std_ulogic; +signal lm2_ta : std_ulogic_vector(0 to 5); +signal lm2_ta_din : std_ulogic_vector(0 to 5); +signal lm3_valid : std_ulogic; +signal lm3_valid_din : std_ulogic; +signal lm3_ta : std_ulogic_vector(0 to 5); +signal lm3_ta_din : std_ulogic_vector(0 to 5); +signal lm4_valid : std_ulogic; +signal lm4_valid_din : std_ulogic; +signal lm4_ta : std_ulogic_vector(0 to 5); +signal lm4_ta_din : std_ulogic_vector(0 to 5); +signal lm5_valid : std_ulogic; +signal lm5_valid_din : std_ulogic; +signal lm5_ta : std_ulogic_vector(0 to 5); +signal lm5_ta_din : std_ulogic_vector(0 to 5); +signal lm6_valid : std_ulogic; +signal lm6_valid_din : std_ulogic; +signal lm6_ta : std_ulogic_vector(0 to 5); +signal lm6_ta_din : std_ulogic_vector(0 to 5); +signal lm7_valid : std_ulogic; +signal lm7_valid_din : std_ulogic; +signal lm7_ta : std_ulogic_vector(0 to 5); +signal lm7_ta_din : std_ulogic_vector(0 to 5); + +signal lmiss_qentry : std_ulogic_vector(0 to 7); +signal lmiss_complete : std_ulogic_vector(0 to 7); +signal lmiss_comp_v : std_ulogic; +signal lmiss_comp, lmiss_comp_ex0, lmiss_comp_ex1, lmiss_comp_ex2, lmiss_comp_ex3 : std_ulogic_vector(0 to 7); + +signal lmiss_comp_ex1_latch_scout, lmiss_comp_ex1_latch_scin : std_ulogic_vector(0 to 7); +signal lmiss_comp_ex2_latch_scout, lmiss_comp_ex2_latch_scin : std_ulogic_vector(0 to 7); +signal lmiss_comp_ex3_latch_scout, lmiss_comp_ex3_latch_scin : std_ulogic_vector(0 to 7); +signal lmc_ex4_latch_scin, lmc_ex4_latch_scout : std_ulogic_vector(0 to 6); +signal lmc_ex5_latch_scin, lmc_ex5_latch_scout : std_ulogic; +signal lmc_ex6_latch_scin, lmc_ex6_latch_scout : std_ulogic; + + +signal is1_cancel_bypass : std_ulogic; +signal is1_bypsel : std_ulogic_vector(0 to 5); +signal is2_bypsel : std_ulogic_vector(0 to 5); + +signal spare_l2 : std_ulogic_vector(0 to 4); + +signal is2_frt_v_din, rf1_frt_v_din, rf0_frt_v_din : std_ulogic; +signal ex1_frt_v_din, ex2_frt_v_din, ex3_frt_v_din: std_ulogic; +signal disable_bypass_chicken_switch, dis_byp_is1: std_ulogic; +signal is1_ld_v, is1_ld_v_din : std_ulogic; +signal is2_ld_v, is2_ld_v_din : std_ulogic; +signal rf0_ld_v_din : std_ulogic; +signal rf1_ld_v_din : std_ulogic; +signal ex1_ld_v_din : std_ulogic; +signal ex2_ld_v_din : std_ulogic; +signal ex3_ld_v_din : std_ulogic; + +signal rf0_ld_v : std_ulogic; +signal rf1_ld_v : std_ulogic; +signal ex1_ld_v, ex2_ld_v, ex3_ld_v, ex4_ld_v: std_ulogic; + + +signal bubble3_is1, bubble3_is2 : std_ulogic; +signal bubble3_rf0, bubble3_rf1, bubble3_ex1 : std_ulogic; + +signal bubble3_is1_db : std_ulogic; + +signal bubble3_is2_din : std_ulogic; +signal bubble3_rf0_din, bubble3_rf1_din : std_ulogic; + + +signal is1_fra : std_ulogic_vector(0 to 5); +signal is1_frb : std_ulogic_vector(0 to 5); +signal is1_frc : std_ulogic_vector(0 to 5); + +signal is2_fra : std_ulogic_vector(0 to 5); +signal is2_frb : std_ulogic_vector(0 to 5); +signal is2_frc : std_ulogic_vector(0 to 5); + +signal is1_ldst_v : std_ulogic ; +signal is2_act, rf0_act, rf1_act, ex1_act, ex2_act, ex3_act : std_ulogic; +signal is2_act_l2, rf0_act_l2, rf1_act_l2, ex1_act_l2, ex2_act_l2, ex3_act_l2 : std_ulogic; +signal is2_act_din, rf0_act_din, rf1_act_din, ex1_act_din, ex2_act_din, ex3_act_din : std_ulogic; + +signal is1_fra_v : std_ulogic; +signal is1_frb_v : std_ulogic; +signal is1_frc_v : std_ulogic; +signal is1_crs_v : std_ulogic; + +signal is2_fra_v : std_ulogic; +signal is2_frb_v : std_ulogic; +signal is2_frc_v : std_ulogic; + +signal is1_prebubble_skip : std_ulogic; + +signal is1_frt_v : std_ulogic; +signal is2_frt_v : std_ulogic; +signal rf0_frt_v : std_ulogic; +signal rf1_frt_v : std_ulogic; +signal ex1_frt_v, ex2_frt_v, ex3_frt_v, ex4_frt_v: std_ulogic; + +signal ex3_frt_v_forbyp : std_ulogic; + +signal is1_instr_v : std_ulogic; +signal is2_instr_v : std_ulogic; +signal rf0_instr_v : std_ulogic; +signal rf1_instr_v : std_ulogic; +signal ex1_instr_v, ex2_instr_v, ex3_instr_v, ex4_instr_v, ex5_instr_v, ex6_instr_v : std_ulogic; + +signal is1_instr_v_din : std_ulogic; +signal is2_instr_v_din : std_ulogic; +signal rf0_instr_v_din : std_ulogic; +signal rf1_instr_v_din : std_ulogic; +signal ex1_instr_v_din, ex2_instr_v_din, ex3_instr_v_din, ex4_instr_v_din, ex5_instr_v_din: std_ulogic; + +signal is1_fmul_uc_din : std_ulogic; +signal is2_fmul_uc_din : std_ulogic; +signal rf0_fmul_uc_din : std_ulogic; +signal rf1_fmul_uc_din : std_ulogic; +signal ex1_fmul_uc_din, ex2_fmul_uc_din, ex3_fmul_uc_din, ex4_fmul_uc_din, ex5_fmul_uc_din: std_ulogic; +signal is1_fmul_uc : std_ulogic; +signal is2_fmul_uc : std_ulogic; +signal rf0_fmul_uc : std_ulogic; +signal rf1_fmul_uc : std_ulogic; +signal ex1_fmul_uc, ex2_fmul_uc, ex3_fmul_uc, ex4_fmul_uc, ex5_fmul_uc: std_ulogic; + + +signal is1_lmq_waw_hit, is1_lmq_waw_hit_b, is1_waw_cr_hit : std_ulogic; + +signal is1_ta : std_ulogic_vector(0 to 5); +signal is2_ta : std_ulogic_vector(0 to 5); +signal rf0_ta : std_ulogic_vector(0 to 5); +signal rf1_ta : std_ulogic_vector(0 to 5); +signal ex1_ta : std_ulogic_vector(0 to 5); +signal ex2_ta : std_ulogic_vector(0 to 5); +signal ex3_ta : std_ulogic_vector(0 to 5); +signal ex4_ta : std_ulogic_vector(0 to 5); + + + +signal is1_crt_v, is1_crt_v_din: std_ulogic; +signal is2_crt_v, is2_crt_v_din: std_ulogic; +signal rf0_crt_v, rf0_crt_v_din: std_ulogic; +signal rf1_crt_v, rf1_crt_v_din: std_ulogic; +signal ex1_crt_v, ex1_crt_v_din: std_ulogic; +signal ex2_crt_v, ex2_crt_v_din: std_ulogic; +signal ex3_crt_v, ex3_crt_v_din: std_ulogic; +signal ex4_crt_v: std_ulogic; + +signal raw_cr_hit : std_ulogic; +signal is1_store_v : std_ulogic; +signal raw_fra_hit, raw_frb_hit, raw_frc_hit, is1_raw_hit, is1_dep_hit: std_ulogic; +signal raw_fra_hit_b, raw_frb_hit_b, raw_frc_hit_b, is1_dep_hit_b, is1_dep_hit_buf1,is1_dep_hit_buf2_b : std_ulogic; +signal is1_waw_load_hit : std_ulogic; +signal stall_is2_b : std_ulogic; +signal stall_is2 : std_ulogic; + +signal is1_stage_din, is1_stage_din_premux : std_ulogic_vector(0 to 42); +signal is2_stage_dout_premux : std_ulogic_vector(0 to 42); +signal is2_stage_dout : std_ulogic_vector(0 to 42); +signal is2_stage_latch_scin : std_ulogic_vector(0 to 42); +signal is2_stage_latch_scout : std_ulogic_vector(0 to 42); + +signal is2_instr_ldst_v : std_ulogic; +signal is2_bypass_latch_scin, is2_bypass_latch_scout : std_ulogic_vector(0 to 5); +signal rf0_sp_latch_scin, rf0_sp_latch_scout : std_ulogic_vector(0 to 14); +signal rf1_sp_latch_scin, rf1_sp_latch_scout : std_ulogic_vector(0 to 14); +signal ex1_sp_latch_scin, ex1_sp_latch_scout : std_ulogic_vector(0 to 14); +signal ex2_sp_latch_scin, ex2_sp_latch_scout : std_ulogic_vector(0 to 13); +signal ex3_sp_latch_scin, ex3_sp_latch_scout : std_ulogic_vector(0 to 13); +signal ex4_sp_latch_scin, ex4_sp_latch_scout : std_ulogic_vector(0 to 12); +signal ex5_sp_latch_scin, ex5_sp_latch_scout : std_ulogic_vector(0 to 10); +signal ex6_sp_latch_scin, ex6_sp_latch_scout : std_ulogic_vector(0 to 1); +signal busy_latch_scin, busy_latch_scout : std_ulogic_vector(0 to 2); +signal act_latch_scin, act_latch_scout : std_ulogic_vector(0 to 7); + +signal lmq0_latch_scin,lmq0_latch_scout : std_ulogic_vector(0 to 6); +signal lmq1_latch_scin,lmq1_latch_scout : std_ulogic_vector(0 to 6); +signal lmq2_latch_scin,lmq2_latch_scout : std_ulogic_vector(0 to 6); +signal lmq3_latch_scin,lmq3_latch_scout : std_ulogic_vector(0 to 6); +signal lmq4_latch_scin,lmq4_latch_scout : std_ulogic_vector(0 to 6); +signal lmq5_latch_scin,lmq5_latch_scout : std_ulogic_vector(0 to 6); +signal lmq6_latch_scin,lmq6_latch_scout : std_ulogic_vector(0 to 6); +signal lmq7_latch_scin,lmq7_latch_scout : std_ulogic_vector(0 to 6); + +signal is1_cmiss_flush : std_ulogic; +signal is2_cmiss_flush : std_ulogic; +signal is2_cmiss_flush_q : std_ulogic; +signal is2_cmiss_flush_din : std_ulogic; +signal rf0_cmiss_flush : std_ulogic; +signal rf1_cmiss_flush : std_ulogic; +signal ex1_cmiss_flush : std_ulogic; +signal ex2_cmiss_flush : std_ulogic; +signal rf0_cmiss_flush_din : std_ulogic; +signal rf1_cmiss_flush_din : std_ulogic; +signal ex1_cmiss_flush_din : std_ulogic; + +signal rf0_cmiss_waw_flush : std_ulogic; +signal rf1_cmiss_waw_flush : std_ulogic; +signal ex1_cmiss_waw_flush : std_ulogic; + +signal ignore_flush_is1, ignore_flush_is2 : std_ulogic; +signal ignore_flush_rf0, ignore_flush_rf1 : std_ulogic; +signal ignore_flush_ex1, ignore_flush_ex2 : std_ulogic; +signal ignore_flush_ex3, ignore_flush_ex4 : std_ulogic; +signal ignore_flush_ex5, ignore_flush_ex6 : std_ulogic; + +signal ignore_flush_rf0_din, ignore_flush_rf1_din : std_ulogic; +signal ignore_flush_ex1_din, ignore_flush_ex2_din : std_ulogic; +signal ignore_flush_ex3_din, ignore_flush_ex4_din : std_ulogic; +signal ignore_flush_ex5_din, ignore_flush_is2_din : std_ulogic; + + + + +signal is1_hold_v_b : std_ulogic; +signal is1_WAW_CRorLDhit_b : std_ulogic; +signal is1_allbut_RAW : std_ulogic; +signal is1_raw_hit_b : std_ulogic; + +signal debug_scin :std_ulogic_vector(0 to 15); +signal debug_scout :std_ulogic_vector(0 to 15); + +signal uc_rc_ld :std_ulogic; +signal uc_rc_l2 :std_ulogic; +signal uc_end_is1 :std_ulogic; +signal ppc_rc_latch_scin :std_ulogic; +signal ppc_rc_latch_scout :std_ulogic; +signal raw_frb_uc_hit_b, raw_frb_uc_hit :std_ulogic; +signal is1_dep_hit_db :std_ulogic; +signal is1_raw_hit_db :std_ulogic; +signal raw_fra_hit_db :std_ulogic; +signal raw_frb_hit_db :std_ulogic; +signal raw_frc_hit_db :std_ulogic; +signal is1_prebubble_skip_db :std_ulogic; +signal is1_instr_v_din_db :std_ulogic; +signal raw_cr_hit_db :std_ulogic; +signal is1_raw_hit_earlystuff_b :std_ulogic; +signal is1_lmq_waw_hit_db :std_ulogic; +signal is1_waw_load_hit_db :std_ulogic; +signal iu_au_is1_hold_db :std_ulogic; +signal iu_au_is2_stall_db :std_ulogic; +signal iu_au_is1_flush_db :std_ulogic; +signal iu_au_is2_flush_db :std_ulogic; +signal iu_au_rf0_flush_db :std_ulogic; + +signal lmiss_comp_type :std_ulogic_vector(0 to 1); + +signal lm_v :std_ulogic_vector(0 to 7); +signal set_lm0, set_lm0_1d, clear_lm0 :std_ulogic; +signal set_lm1, set_lm1_1d, clear_lm1 :std_ulogic; +signal set_lm2, set_lm2_1d, clear_lm2 :std_ulogic; +signal set_lm3, set_lm3_1d, clear_lm3 :std_ulogic; +signal set_lm4, set_lm4_1d, clear_lm4 :std_ulogic; +signal set_lm5, set_lm5_1d, clear_lm5 :std_ulogic; +signal set_lm6, set_lm6_1d, clear_lm6 :std_ulogic; +signal set_lm7, set_lm7_1d, clear_lm7 :std_ulogic; + + +signal lmc_ex3, lmc_ex4 :std_ulogic_vector(0 to 5); +signal lmc_ex3_v, lmc_ex4_v, lmc_ex5_v, lmc_ex6_v :std_ulogic; + +signal is1_ld6_a_bypass, is1_ld6_b_bypass, is1_ld6_c_bypass :std_ulogic; + +signal ppc_div_sqrt_is1 :std_ulogic; + +signal fu_busy,fu_busy_l2 :std_ulogic; + +signal is1_to_ucode, is1_is_ucode, is1_singlestep_ucode ,is1_singlestep_pn , is1_singlestep :std_ulogic; +signal config_iucr :std_ulogic_vector(1 to 7); +signal is2_axubusy, fmul_uc_busy, fmul_uc_busy_l2, ignore_flush_busy, ignore_flush_busy_l2, is2_ignore_flush_busy :std_ulogic; + +signal is1_stall_rep_b, is1_stall_rep, uc_rc_adv, uc_rc_go_b, uc_rc_ho_b :std_ulogic; + + + + + + + + + + + + + + + + +begin + + + + +tidn <= '0'; +tiup <= '1'; + +-- ############################################ + + +spare_unused(49) <= d_mode; +spare_unused(43 to 48) <= i_afd_is1_fra_buf(1 to 6); +spare_unused(37 to 42) <= i_afd_is1_frb_buf(1 to 6); +spare_unused(31 to 36) <= i_afd_is1_frc_buf(1 to 6); +spare_unused(25 to 30) <= i_afd_is1_frt_buf(1 to 6); +spare_unused(24) <= i_afd_is1_instr_sto_v; + +spare_unused(18 to 22) <= i_afd_is1_instr(26 to 30); +spare_unused(17) <= i_afd_is1_fra(0); +spare_unused(16) <= i_afd_is1_frb(0); +spare_unused(15) <= i_afd_is1_frc(0); + +spare_unused(23) <= tidn; +spare_unused(11) <= tidn; +spare_unused(12) <= tidn; +spare_unused(13) <= tidn; + +-- ############################################ + +uc_end_is1 <= is1_fmul_uc and is1_instr_v; +spare_unused(50 to 55) <= i_afd_is1_ifar(56 to 61); + + + + + is1_stall_rep_b <= not i_afd_is1_stall_rep ; + is1_stall_rep <= i_afd_is1_stall_rep ; + -- hold on to the original rc bit + uc_rc_adv <= (i_afd_is1_divsqrt and i_afd_is1_instr(31)) or (not i_afd_is1_divsqrt and uc_rc_l2); + + +uc_rc_go: uc_rc_go_b <= not( is1_stall_rep_b and uc_rc_adv ); +uc_rc_ho: uc_rc_ho_b <= not( is1_stall_rep and uc_rc_l2 ); +uc_rc_do: uc_rc_ld <= not( uc_rc_go_b and uc_rc_ho_b ); + + + ppc_rc_latch: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 1) + port map ( + nclk => nclk, vd => vdd, gd => gnd, + forcee => forcee, mpw1_b => mpw1_b, mpw2_b => mpw2_b, + delay_lclkr => delay_lclkr, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + scin(0) => ppc_rc_latch_scin, + scout(0) => ppc_rc_latch_scout, + --------------------------------------------- + din(0) => uc_rc_ld, + --------------------------------------------- + dout(0) => uc_rc_l2 + --------------------------------------------- + ); + + + +-- sig reassign for portability +is1_ta(0 to 5) <= i_afd_is1_frt(1 to 6); -- bit 1 is the ucode bit + + +is1_frt_v <= i_afd_is1_frt_v; + +is1_fra(0 to 5) <= i_afd_is1_fra(1 to 6);-- bit 1 is the ucode bit + +is1_frb(0 to 5) <= i_afd_is1_frb(1 to 6);-- bit 1 is the ucode bit + +is1_frc(0 to 5) <= i_afd_is1_frc(1 to 6);-- bit 1 is the ucode bit + + + + +is1_fra_v <= i_afd_is1_fra_v; +is1_frb_v <= i_afd_is1_frb_v; +is1_frc_v <= i_afd_is1_frc_v; + +is1_crs_v <= iu_au_is1_cr_user_v; -- FXU op reads CR +is1_crt_v <= i_afd_is1_cr_writer or (uc_end_is1 and uc_rc_l2); -- AXU cr writer op + + +is1_instr_v <= i_afd_is1_instr_v; + +bubble3_is1 <= i_afd_is1_est_bubble3; + + +config_iucr(1) <= i_afd_config_iucr(1); --IUCR2(33) DISBYP +config_iucr(2) <= i_afd_config_iucr(2); --IUCR2(34) SSAXU +config_iucr(3) <= i_afd_config_iucr(3); --IUCR2(35) SSUC +config_iucr(4) <= i_afd_config_iucr(4); --IUCR2(36) RESERVED FOR BGQ (disable store bypass) +config_iucr(5) <= i_afd_config_iucr(5); --IUCR2(37) DISCGAT (disable clock gating in IU_AXU) +config_iucr(6) <= i_afd_config_iucr(6); --IUCR2(38) SSFDIVPN (PROPOSED, single step fdiv* and fsqrt* prenorms) +config_iucr(7) <= i_afd_config_iucr(7); --IUCR2(39) RESERVED FOR BGQ + +spare_unused(56) <= config_iucr(4); +iucr2_ss_ignore_flush <= config_iucr(6); +spare_unused(57) <= config_iucr(7); + disable_cgat <= config_iucr(5); +spare_unused(58) <= disable_cgat; + +----------------------------------------------------------------------- +-- RAW + +---------------------------------------------------- +--and regular bypass is ex6-rf1, loads ex7-rf1 +--ok. writethru for math is ex6-rf0, loads ex7-rf0 + +-- Math Bypass/Writethru Load Bypass/Writethru +-- +-- IS1 <-\ fadd stfd IS1 <-\ fadd stfd +-- IS2 | IS2 | +-- RF0<-\WT| fadd stfd RF0<-\WT| fadd stfd +-- RF1<-\BP| fadd xxxx RF1<-\BP| fadd xxxx +-- EX1 | | EX1 | | +-- EX2 | | EX2 | | +-- EX3 |>-/BYP fadd xxxx EX3 | | +-- EX4 |>-/WT fadd fadd EX4 |>-/BYP lfd xxxx +-- EX5 | EX5 |>-/WT lfd lfd +-- EX6>-/ fadd fadd EX6 | +-- EX7 EX7>-/ lfd lfd + +-- dis_byp_is1 will shut off bypasses and WT cases for math target writers, but for loads, WT is allowed. + + + + + + +axu_raw_cmp: entity work.iuq_axu_fu_dep_cmp(iuq_axu_fu_dep_cmp) +port map ( + vdd => vdd, + gnd => gnd, + lm_v => lm_v, + is1_instr_v => is1_instr_v, + lmc_ex4_v => lmc_ex4_v, + dis_byp_is1 => dis_byp_is1, + is1_store_v => is1_store_v, + ex3_ld_v => ex3_ld_v , + ex4_ld_v => ex4_ld_v , + uc_end_is1 => uc_end_is1 , + + is2_frt_v => is2_frt_v, + rf0_frt_v => rf0_frt_v, + rf1_frt_v => rf1_frt_v, + ex1_frt_v => ex1_frt_v, + ex2_frt_v => ex2_frt_v, + ex3_frt_v => ex3_frt_v, + ex4_frt_v => ex4_frt_v, + lm0_ta => lm0_ta, + lm1_ta => lm1_ta, + lm2_ta => lm2_ta, + lm3_ta => lm3_ta, + lm4_ta => lm4_ta, + lm5_ta => lm5_ta, + lm6_ta => lm6_ta, + lm7_ta => lm7_ta, + lmc_ex4 => lmc_ex4, + ex4_ta => ex4_ta , + ex3_ta => ex3_ta , + ex2_ta => ex2_ta , + ex1_ta => ex1_ta , + rf1_ta => rf1_ta , + rf0_ta => rf0_ta , + is2_ta => is2_ta , + + is1_fra_v => is1_fra_v, + is1_frb_v => is1_frb_v, + is1_frc_v => is1_frc_v, + is1_frt_v => is1_frt_v, + + is1_fra => is1_fra , + is1_frb => is1_frb , + is1_frc => is1_frc , + is1_ta => is1_ta , + + raw_fra_hit_b => raw_fra_hit_b , + raw_frb_hit_b => raw_frb_hit_b , + raw_frc_hit_b => raw_frc_hit_b , + raw_frb_uc_hit_b => raw_frb_uc_hit_b, + is1_lmq_waw_hit_b => is1_lmq_waw_hit_b + +); + + raw_fra_hit <= not raw_fra_hit_b; + raw_frb_hit <= not raw_frb_hit_b; + raw_frc_hit <= not raw_frc_hit_b; + + +-- FXU read CR, AXU write CR dependency for fcmp* (AXU does not read the CR) +-- (bubble3's are 3 cycles longer) +-- IS1 >-\ +-- IS2 | +-- RF0 | +-- RF1>-\ | +-- EX1 | | +-- EX2 |<-/ +-- EX3 | +-- EX4 | +-- EX5<-/ +-- EX6 + +raw_cr_hit <= is1_crs_v and ((is2_crt_v and is2_instr_v) or + (rf0_crt_v and rf0_instr_v) or + (rf1_crt_v and rf1_instr_v) or + (ex1_crt_v and ex1_instr_v) or + (ex2_crt_v and ex2_instr_v) or -- these stages, ex2,ex3,ex4 are only active for bubble3 instrs + (ex3_crt_v and ex3_instr_v) or + (ex4_crt_v and ex4_instr_v) ); + + + + + +is1_raw_hit_earlystuff_b <= not ((is1_instr_v and (is1_prebubble_skip or is1_singlestep)) or raw_cr_hit); + +axudep_rawhit_nand4: is1_raw_hit <= not(raw_fra_hit_b and raw_frb_hit_b and raw_frc_hit_b and is1_raw_hit_earlystuff_b); + +is1_prebubble_skip <= i_afd_is1_prebubble1 and is2_instr_v; + + -- is1_prebubble_skip is meant to hold off issueing an instruction for a cycle based on the instruction. + -- currently, this is used for mffs instructions, since the fpscr is updated in ex7 we need to make sure + -- nothing is updating the fpscr while its being read. +----------------------------------------------------------------------- +-- WAW + + +-- everything is an ex6 exit except for loads, which are ex7 +-- This is redundant due to the waw_load_hit logic below +-- is1_waw_hit <= ((is1_frt_v and is1_instr_v and not is1_ld_v) and (is2_frt_v and is2_instr_v and is2_ld_v) and (is1_ta = is2_ta)); + +-- this is fxu cr write following fpu cr write (like rc=1) bubble3 indicates fpu cr writer +-- bubble3 instructions write in essentially ex8, but they write the ex4 CR bus. So the below +-- ensures we don't write out of order. +is1_waw_cr_hit <= i_afd_is1_cr_setter and (bubble3_is2 or bubble3_rf0 or bubble3_rf1); + + +-- WAWs involving loads need additional protection. Cache misses occur in stage ex4 and LMQ reflects them in ex5. +-- Instructions with WAWs dependencies on loads will be stalled in is1 until the load is in rf1. +-- After that the LMQ would continue the stall if necessary, or cmiss_flush if already issued +-- Instructions in is0 when the load is in ex4 are protected by the LMQ from the beginning. +is1_waw_load_hit <= (is1_frt_v and is2_frt_v and is2_ld_v and (is2_ta = is1_ta)) or + (is1_frt_v and rf0_frt_v and rf0_ld_v and (rf0_ta = is1_ta)) ; + +----------------------------------------------------------------------- + + + + + + +is1_lmq_waw_hit <= not is1_lmq_waw_hit_b; + +axudep_hold_v_nand2: is1_hold_v_b <= not (iu_au_is1_hold and is1_instr_v); + +axudep_WAW_CRorLDhit_nor2: is1_WAW_CRorLDhit_b <= not (is1_waw_load_hit or is1_waw_cr_hit); + +axudep_allbut_RAW_nand3: is1_allbut_RAW <= not (is1_lmq_waw_hit_b and is1_WAW_CRorLDhit_b and is1_hold_v_b); + +is1_raw_hit_b <= not is1_raw_hit; +spare_unused(10) <= is1_raw_hit_b; + +raw_frb_uc_hit <= not raw_frb_uc_hit_b; + +axudep_dephit_nor3: is1_dep_hit_b <= not (is1_allbut_RAW or is1_raw_hit or raw_frb_uc_hit); + +axudep_dephit_buf1: is1_dep_hit_buf1 <= not is1_dep_hit_b; +axudep_dephit_buf2: is1_dep_hit_buf2_b <= not is1_dep_hit_buf1; +au_iu_is1_dep_hit_b <= is1_dep_hit_buf2_b; + + +is1_dep_hit <= not is1_dep_hit_b; + +au_iu_is1_dep_hit <= is1_dep_hit; + +------------------------------------------------------------------------------------------------------------------------ +----------------------------------------------------------------------- +-- shadow pipe logic + +-- "exit" is defined as the cycle where the register address and write enable are valid to write to the regfile. +-- latches exist in the bypass macro to ensure that the data can then be read in the following cycle (writethru latches) +-- bypass happens in the same cycle as "exit" + +-- instr valids + +is2_instr_v_din <= is2_instr_v and (not iu_au_is2_flush or ignore_flush_is2); + + +rf0_instr_v_din <= rf0_instr_v and not iu_au_rf0_flush; +rf1_instr_v_din <= rf1_instr_v and not iu_au_rf1_flush; +ex1_instr_v_din <= ex1_instr_v and not iu_au_ex1_flush; +ex2_instr_v_din <= ex2_instr_v and not iu_au_ex2_flush; +ex3_instr_v_din <= ex3_instr_v and not iu_au_ex3_flush; +ex4_instr_v_din <= ex4_instr_v and not iu_au_ex4_flush; +ex5_instr_v_din <= ex5_instr_v and not iu_au_ex5_flush; + +is2_fmul_uc_din <= is2_fmul_uc and is2_instr_v_din and i_afi_is2_take; +rf0_fmul_uc_din <= rf0_fmul_uc and rf0_instr_v_din; +rf1_fmul_uc_din <= rf1_fmul_uc and rf1_instr_v_din; +ex1_fmul_uc_din <= ex1_fmul_uc and ex1_instr_v_din; +ex2_fmul_uc_din <= ex2_fmul_uc and ex2_instr_v_din; +ex3_fmul_uc_din <= ex3_fmul_uc and ex3_instr_v_din; +ex4_fmul_uc_din <= ex4_fmul_uc and ex4_instr_v_din; +ex5_fmul_uc_din <= ex5_fmul_uc and ex5_instr_v_din; + + +bubble3_is2_din <= bubble3_is2 and is2_instr_v_din; +bubble3_rf0_din <= bubble3_rf0 and rf0_instr_v_din; +bubble3_rf1_din <= bubble3_rf1 and rf1_instr_v_din; + + + +ignore_flush_is2_din <= ignore_flush_is2 and i_afi_is2_take and not iu_au_is2_flush; +ignore_flush_rf0_din <= ignore_flush_rf0 and not iu_au_rf0_flush; +ignore_flush_rf1_din <= ignore_flush_rf1 and not iu_au_rf1_flush; +ignore_flush_ex1_din <= ignore_flush_ex1 and not iu_au_ex1_flush; +ignore_flush_ex2_din <= ignore_flush_ex2 and not iu_au_ex2_flush; +ignore_flush_ex3_din <= ignore_flush_ex3 and not iu_au_ex3_flush; +ignore_flush_ex4_din <= ignore_flush_ex4 and not iu_au_ex4_flush; +ignore_flush_ex5_din <= ignore_flush_ex5 and not iu_au_ex5_flush; + + + + + + -- frt valids (target valids are shut off to line up RAW stalls correctly for bypass) + + +-- everything is an ex6 exit now, except for loads, which are ex7 +is2_frt_v_din <= is2_frt_v and (not iu_au_is2_flush or ignore_flush_is2) and stall_is2_b; +rf0_frt_v_din <= rf0_frt_v and not iu_au_rf0_flush; +rf1_frt_v_din <= rf1_frt_v and not iu_au_rf1_flush; +ex1_frt_v_din <= ex1_frt_v and not iu_au_ex1_flush; +ex2_frt_v_din <= ex2_frt_v and not iu_au_ex2_flush; +ex3_frt_v_din <= ex3_frt_v and not iu_au_ex3_flush; + + + +is1_crt_v_din <= is1_crt_v; +is2_crt_v_din <= is2_crt_v; +rf0_crt_v_din <= rf0_crt_v; +rf1_crt_v_din <= rf1_crt_v; +ex1_crt_v_din <= ex1_crt_v and bubble3_ex1; -- bubble3=1 for rc=1 instructions and mcrfs. bubble3=0 for fcmpu fcmpo ; +ex2_crt_v_din <= ex2_crt_v; -- (so ex2_crt_v, ex3_crt_v and ex4_crt_v will only be on for bubble3 instructions) +ex3_crt_v_din <= ex3_crt_v; + + +------------------------------------------------------------------------------------------------------------------------ + +-- Load Miss Queue + + + +four_loadmiss_entries : + if (lmq_entries = 4) generate + +lmiss_qentry(0 to 3) <= xu_au_loadmiss_qentry(0 to 3); +lmiss_complete(0 to 3) <= xu_au_loadmiss_complete_qentry(0 to 3); +lmiss_qentry(4 to 7) <= "0000"; +lmiss_complete(4 to 7) <= "0000"; + + + end generate four_loadmiss_entries; + +eight_loadmiss_entries : + if (lmq_entries = 8) generate + +lmiss_qentry <= xu_au_loadmiss_qentry; +lmiss_complete <= xu_au_loadmiss_complete_qentry; + + end generate eight_loadmiss_entries; + +lmiss_comp_type <= xu_au_loadmiss_complete_type; +lmiss_comp(0 to 7) <= lmiss_complete(0 to 7); +lmiss_comp_v <= xu_au_loadmiss_complete_vld and (lmiss_comp_type = "01"); -- this is equivalent to stage RF1/ex0 + + + +lm_tar(0 to 5) <= xu_au_loadmiss_target(3) & xu_au_loadmiss_target(4 to 8); -- tack on ucode addr bit + +lm_v(0 to 7) <= lm0_valid & lm1_valid & lm2_valid & lm3_valid & lm4_valid & lm5_valid & lm6_valid & lm7_valid ; + +set_lm0 <= xu_au_loadmiss_vld and lmiss_qentry(0) and (xu_au_loadmiss_target_type = "01") and not iu_au_ex4_flush; +set_lm1 <= xu_au_loadmiss_vld and lmiss_qentry(1) and (xu_au_loadmiss_target_type = "01") and not iu_au_ex4_flush; +set_lm2 <= xu_au_loadmiss_vld and lmiss_qentry(2) and (xu_au_loadmiss_target_type = "01") and not iu_au_ex4_flush; +set_lm3 <= xu_au_loadmiss_vld and lmiss_qentry(3) and (xu_au_loadmiss_target_type = "01") and not iu_au_ex4_flush; +set_lm4 <= xu_au_loadmiss_vld and lmiss_qentry(4) and (xu_au_loadmiss_target_type = "01") and not iu_au_ex4_flush; +set_lm5 <= xu_au_loadmiss_vld and lmiss_qentry(5) and (xu_au_loadmiss_target_type = "01") and not iu_au_ex4_flush; +set_lm6 <= xu_au_loadmiss_vld and lmiss_qentry(6) and (xu_au_loadmiss_target_type = "01") and not iu_au_ex4_flush; +set_lm7 <= xu_au_loadmiss_vld and lmiss_qentry(7) and (xu_au_loadmiss_target_type = "01") and not iu_au_ex4_flush; + +clear_lm0 <= lmiss_comp_ex3(0) or (set_lm0_1d and iu_au_ex5_flush); +clear_lm1 <= lmiss_comp_ex3(1) or (set_lm1_1d and iu_au_ex5_flush); +clear_lm2 <= lmiss_comp_ex3(2) or (set_lm2_1d and iu_au_ex5_flush); +clear_lm3 <= lmiss_comp_ex3(3) or (set_lm3_1d and iu_au_ex5_flush); +clear_lm4 <= lmiss_comp_ex3(4) or (set_lm4_1d and iu_au_ex5_flush); +clear_lm5 <= lmiss_comp_ex3(5) or (set_lm5_1d and iu_au_ex5_flush); +clear_lm6 <= lmiss_comp_ex3(6) or (set_lm6_1d and iu_au_ex5_flush); +clear_lm7 <= lmiss_comp_ex3(7) or (set_lm7_1d and iu_au_ex5_flush); + +lmiss_comp_ex0(0) <= (lmiss_comp_v and lmiss_comp(0)); +lmiss_comp_ex0(1) <= (lmiss_comp_v and lmiss_comp(1)); +lmiss_comp_ex0(2) <= (lmiss_comp_v and lmiss_comp(2)); +lmiss_comp_ex0(3) <= (lmiss_comp_v and lmiss_comp(3)); +lmiss_comp_ex0(4) <= (lmiss_comp_v and lmiss_comp(4)); +lmiss_comp_ex0(5) <= (lmiss_comp_v and lmiss_comp(5)); +lmiss_comp_ex0(6) <= (lmiss_comp_v and lmiss_comp(6)); +lmiss_comp_ex0(7) <= (lmiss_comp_v and lmiss_comp(7)); + + + +-- Q entry 0 +lm0_valid_din <= '1' when set_lm0 ='1' else -- set + '0' when clear_lm0 ='1' else -- clear + lm0_valid; -- hold +lm0_ta_din(0 to 5) <= lm_tar(0 to 5) when set_lm0 ='1' else -- set + lm0_ta(0 to 5); -- hold + + +lm1_valid_din <= '1' when set_lm1 ='1' else -- set + '0' when clear_lm1 ='1' else -- clear + lm1_valid; -- hold +lm1_ta_din(0 to 5) <= lm_tar(0 to 5) when set_lm1 ='1' else -- set + lm1_ta(0 to 5); -- hold + + +lm2_valid_din <= '1' when set_lm2 ='1' else -- set + '0' when clear_lm2 ='1' else -- clear + lm2_valid; -- hold +lm2_ta_din(0 to 5) <= lm_tar(0 to 5) when set_lm2 ='1' else -- set + lm2_ta(0 to 5); -- hold + + +lm3_valid_din <= '1' when set_lm3 ='1' else -- set + '0' when clear_lm3 ='1' else -- clear + lm3_valid; -- hold +lm3_ta_din(0 to 5) <= lm_tar(0 to 5) when set_lm3 ='1' else -- set + lm3_ta(0 to 5); -- hold + + +lm4_valid_din <= '1' when set_lm4 ='1' else -- set + '0' when clear_lm4 ='1' else -- clear + lm4_valid; -- hold +lm4_ta_din(0 to 5) <= lm_tar(0 to 5) when set_lm4 ='1' else -- set + lm4_ta(0 to 5); -- hold + + +lm5_valid_din <= '1' when set_lm5 ='1' else -- set + '0' when clear_lm5 ='1' else -- clear + lm5_valid; -- hold +lm5_ta_din(0 to 5) <= lm_tar(0 to 5) when set_lm5 ='1' else -- set + lm5_ta(0 to 5); -- hold + + +lm6_valid_din <= '1' when set_lm6 ='1' else -- set + '0' when clear_lm6 ='1' else -- clear + lm6_valid; -- hold +lm6_ta_din(0 to 5) <= lm_tar(0 to 5) when set_lm6 ='1' else -- set + lm6_ta(0 to 5); -- hold + + +lm7_valid_din <= '1' when set_lm7 ='1' else -- set + '0' when clear_lm7 ='1' else -- clear + lm7_valid; -- hold +lm7_ta_din(0 to 5) <= lm_tar(0 to 5) when set_lm7 ='1' else -- set + lm7_ta(0 to 5); -- hold + + +-- lmiss_comp is equivalent to stage RF1 (10/13/2008) +lmc_ex3(0 to 5) <= (lm0_ta(0 to 5) and (0 to 5 => lmiss_comp_ex3(0))) or + (lm1_ta(0 to 5) and (0 to 5 => lmiss_comp_ex3(1))) or + (lm2_ta(0 to 5) and (0 to 5 => lmiss_comp_ex3(2))) or + (lm3_ta(0 to 5) and (0 to 5 => lmiss_comp_ex3(3))) or + (lm4_ta(0 to 5) and (0 to 5 => lmiss_comp_ex3(4))) or + (lm5_ta(0 to 5) and (0 to 5 => lmiss_comp_ex3(5))) or + (lm6_ta(0 to 5) and (0 to 5 => lmiss_comp_ex3(6))) or + (lm7_ta(0 to 5) and (0 to 5 => lmiss_comp_ex3(7))); + +-- lmiss_comp is equivalent to stage RF1 (10/13/2008) +lmc_ex3_v <= or_reduce(lmiss_comp_ex3(0 to 7)); + + + lmiss_comp_ex1_latch : tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 8) + port map ( + nclk => nclk, vd => vdd, gd => gnd, + forcee => forcee, mpw1_b => mpw1_b, mpw2_b => mpw2_b, + delay_lclkr => delay_lclkr, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + scin => lmiss_comp_ex1_latch_scin(0 to 7), + scout => lmiss_comp_ex1_latch_scout(0 to 7), + --------------------------------------------- + din => lmiss_comp_ex0, + --------------------------------------------- + dout => lmiss_comp_ex1 + --------------------------------------------- + ); + + lmiss_comp_ex2_latch : tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 8) + port map ( + nclk => nclk, vd => vdd, gd => gnd, + forcee => forcee, mpw1_b => mpw1_b, mpw2_b => mpw2_b, + delay_lclkr => delay_lclkr, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + scin => lmiss_comp_ex2_latch_scin(0 to 7), + scout => lmiss_comp_ex2_latch_scout(0 to 7), + --------------------------------------------- + din => lmiss_comp_ex1, + --------------------------------------------- + dout => lmiss_comp_ex2 + --------------------------------------------- + ); + + lmiss_comp_ex3_latch : tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 8) + port map ( + nclk => nclk, vd => vdd, gd => gnd, + forcee => forcee, mpw1_b => mpw1_b, mpw2_b => mpw2_b, + delay_lclkr => delay_lclkr, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + scin => lmiss_comp_ex3_latch_scin(0 to 7), + scout => lmiss_comp_ex3_latch_scout(0 to 7), + --------------------------------------------- + din => lmiss_comp_ex2, + --------------------------------------------- + dout => lmiss_comp_ex3 + --------------------------------------------- + ); + + lmc_ex4_latch : tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 7) + port map ( + nclk => nclk, vd => vdd, gd => gnd, + forcee => forcee, mpw1_b => mpw1_b, mpw2_b => mpw2_b, + delay_lclkr => delay_lclkr, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + scin => lmc_ex4_latch_scin(0 to 6), + scout => lmc_ex4_latch_scout(0 to 6), + --------------------------------------------- + din(0 to 5) => lmc_ex3(0 to 5), + din(6) => lmc_ex3_v, + --------------------------------------------- + dout(0 to 5) => lmc_ex4(0 to 5), + dout(6) => lmc_ex4_v + --------------------------------------------- + ); + + lmc_ex5_latch : tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 1) + port map ( + nclk => nclk, vd => vdd, gd => gnd, + forcee => forcee, mpw1_b => mpw1_b, mpw2_b => mpw2_b, + delay_lclkr => delay_lclkr, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + scin(0) => lmc_ex5_latch_scin, + scout(0) => lmc_ex5_latch_scout, + --------------------------------------------- + din(0) => lmc_ex4_v, + --------------------------------------------- + dout(0) => lmc_ex5_v + --------------------------------------------- + ); + + lmc_ex6_latch : tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 1) + port map ( + nclk => nclk, vd => vdd, gd => gnd, + forcee => forcee, mpw1_b => mpw1_b, mpw2_b => mpw2_b, + delay_lclkr => delay_lclkr, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + scin(0) => lmc_ex6_latch_scin, + scout(0) => lmc_ex6_latch_scout, + --------------------------------------------- + din(0) => lmc_ex5_v, + --------------------------------------------- + dout(0) => lmc_ex6_v + --------------------------------------------- + ); + + + + +------------------------------------------------------------------------------------------------------------------------ +-- +------------------------------------------------------------------------------------------------------------------------ +-- +------------------------------------------------------------------------------------------------------------------------ + +is1_fmul_uc <= i_afd_fmul_uc_is1 ; + +is1_fmul_uc_din <= is1_fmul_uc and is1_instr_v_din; + +ppc_div_sqrt_is1 <= i_afd_ignore_flush_is1; + +is1_to_ucode <= i_afd_is1_to_ucode; +is1_is_ucode <= i_afd_is1_is_ucode; + + + + + + +-- block ucode on special cases (invalid op, div by 0, etc) except last instruction +-- ppc_div_sqrt_is1 is activated by the fdiv and fsqrt instruction. + +is1_instr_v_din <= is1_instr_v + and + (not is1_dep_hit) + and + (not iu_au_is1_flush) + and + (not i_afd_is1_to_ucode or ppc_div_sqrt_is1); -- to_ucode (e.g. prenorms) dies here unless fdiv or fsqrt + + +-- Out to Issue for Early IS2 valid. +i_axu_is1_early_v <= is1_instr_v + and + (not i_afd_is1_to_ucode or ppc_div_sqrt_is1) -- to_ucode (e.g. prenorms) dies here unless fdiv or fsqrt + and not i_afd_is1_instr_ldst_v; + +is1_ldst_v <= i_afd_is1_instr_ldst_v and not is1_dep_hit and not i_afd_is1_to_ucode and not iu_au_is1_flush; + +is1_ld_v <= i_afd_is1_instr_ld_v; +spare_unused(14) <= is1_ld_v; + +is1_ld_v_din <= i_afd_is1_instr_ld_v and is1_instr_v and not is1_dep_hit and not iu_au_is1_flush and not i_afd_is1_to_ucode; +is1_store_v <= i_afd_is1_instr_ldst_v and not i_afd_is1_instr_ld_v; + +-- can't have back-to-back fdiv or fsqrt. The flush would be real for the 2nd instr. + +ignore_flush_is1 <= (i_afd_is1_divsqrt and not i_afd_is1_stall_rep) and not iu_au_is1_flush; + + +spare_unused(00) <= i_afd_is1_frt(0); + +is1_stage_din_premux <= + is1_ta(0 to 5) & -- 0 to 5 + is1_ld_v_din & -- 6 + i_afd_in_ucode_mode_or1d & -- 7 + is1_instr_v_din & -- 8 instruction valid + is1_frt_v & -- 9 + is1_is_ucode & -- 10 + fu_iu_uc_special & -- 11 unused + is1_fmul_uc_din & -- 12 + is1_cmiss_flush & -- 13 + is1_raw_hit & -- 14 + is1_fra(0 to 5) & -- 15 to 20 + tidn & -- 21 spare + is1_frb(0 to 5) & -- 22 to 27 + is1_frc(0 to 5) & -- 28 to 33 + ignore_flush_is1 & -- 34 + is1_fra_v & -- 35 + is1_frb_v & -- 36 + is1_frc_v & -- 37 + is1_ldst_v & -- 38 + is1_crt_v_din & -- 39 + bubble3_is1 & -- 40 + iu_au_is1_instr_match & -- 41 + tidn ; -- 42 used to wrap is2_cmiss_flush (not spare) + + + +-- iu_au_is2_stall (from iuq_fxu_dep.vhdl) is ignored by the fu issue logic (iuq_axu_fu_iss.vhdl) during the ppc instructions +-- of div and sqrt, that action is mirrored here +stall_is2 <= iu_au_is2_stall and not (i_afi_is2_take and ignore_flush_is2); -- ignore_flush_is2 indicates ppc div or sqrt + +stall_is2_b <= not stall_is2; + +is1_stage_din <= (is1_stage_din_premux and (0 to (is1_stage_din'length-1) => stall_is2_b)) + or + (is2_stage_dout_premux and (0 to (is1_stage_din'length-1) => stall_is2)); -- feedback if stalled + + + is2_stage_latch : tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => is2_stage_dout'length) + port map ( + nclk => nclk, vd => vdd, gd => gnd, + forcee => forcee, mpw1_b => mpw1_b, mpw2_b => mpw2_b, + delay_lclkr => delay_lclkr, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + scin => is2_stage_latch_scin(0 to ((is2_stage_dout'length)-1)), + scout => is2_stage_latch_scout(0 to ((is2_stage_dout'length)-1)), + --------------------------------------------- + din => is1_stage_din, + --------------------------------------------- + dout => is2_stage_dout + --------------------------------------------- + ); + + is2_stage_dout_premux <= is2_stage_dout(0 to 5) & + (is2_stage_dout(6) and (not iu_au_is2_flush or ignore_flush_is2)) & -- flushing on a stall + is2_stage_dout(7) & + (is2_stage_dout(8) and (not iu_au_is2_flush or ignore_flush_is2)) & -- flushing on a stall + is2_stage_dout(9 to 41) & + (is2_stage_dout(42) or is2_cmiss_flush) ; + +is2_ta(0 to 5) <= is2_stage_dout(0 to 5); +is2_ld_v <= is2_stage_dout(6); + +is2_ld_v_din <= is2_ld_v and is2_instr_v and not iu_au_is2_flush and stall_is2_b; +rf0_ld_v_din <= rf0_ld_v and rf0_instr_v_din; +rf1_ld_v_din <= rf1_ld_v and rf1_instr_v_din; +ex1_ld_v_din <= ex1_ld_v and ex1_instr_v_din; +ex2_ld_v_din <= ex2_ld_v and ex2_instr_v_din; +ex3_ld_v_din <= ex3_ld_v and ex3_instr_v_din; + +i_afd_in_ucode_mode_or1d_b <= not is2_stage_dout(7); + +is2_instr_v <= is2_stage_dout(8); + +is2_frt_v <= is2_stage_dout(9) and is2_instr_v; + + +is2_cmiss_flush_q <= is2_stage_dout(13); -- from is1 + + +i_afd_is2_is_ucode <= is2_stage_dout(10); + +is2_crt_v <= is2_stage_dout(39); + +spare_unused(01) <= is2_stage_dout(11); -- fu_iu_uc_special + + + + +ifdp_is2_est_bubble3 <= is2_stage_dout(40); +bubble3_is2 <= is2_stage_dout(40); + +spare_unused(02) <= is2_stage_dout(14); + +i_axu_is2_fra <= tidn & is2_stage_dout(15 to 20); +i_axu_is2_frb <= tidn & is2_stage_dout(22 to 27); +i_axu_is2_frc <= tidn & is2_stage_dout(28 to 33); +i_axu_is2_frt <= is2_stage_dout(7) & is2_stage_dout(0 to 5); + +is2_fra <= is2_stage_dout(15 to 20); +is2_frb <= is2_stage_dout(22 to 27); +is2_frc <= is2_stage_dout(28 to 33); + +ignore_flush_is2 <= is2_stage_dout(34) and not xu_iu_is2_flush; + +i_afd_ignore_flush_is2 <= is2_stage_dout(34); + +is2_fra_v <= is2_stage_dout(35); +is2_frb_v <= is2_stage_dout(36); +is2_frc_v <= is2_stage_dout(37); + + +i_axu_is2_fra_v <= is2_fra_v; +i_axu_is2_frb_v <= is2_frb_v; +i_axu_is2_frc_v <= is2_frc_v; + +is2_instr_ldst_v <= is2_stage_dout(38); +spare_unused(03) <= is2_stage_dout(21); + +i_axu_is2_instr_match <= is2_stage_dout(41); + +is2_fmul_uc <= is2_stage_dout(12); + + +-------------------------------------- + +au_iu_is2_issue_stall <= (is2_instr_v and not is2_instr_ldst_v) and not i_afi_is2_take; + +i_axu_is2_instr_v <= is2_instr_v and not is2_instr_ldst_v; + +-------------------------------------- +------------------------------------------------------------------------------------------------------------------------ + + + + ----------------------------------------------------------------------- + -- bypass + + + + + + disable_bypass_chicken_switch <= config_iucr(1); + +-- this is for the ex6-ex1 FPR bypass + dis_byp_is1 <= disable_bypass_chicken_switch; +-- note: this does not disable the writethru case for loads (EX8->RF1) we can cover that with the single step AXU chicken switches + +-- this is for the ex6-ex1 bypass +is1_cancel_bypass <= stall_is2 or dis_byp_is1 or is1_store_v; + + +-- arith to arith bypass logic + is1_ex6_a_bypass <= (is1_fra_v and is1_instr_v_din and ex3_frt_v_forbyp and ex3_instr_v_din and not ex3_ld_v and (ex3_ta = is1_fra)) and not is1_cancel_bypass; + + is1_ex6_b_bypass <= (is1_frb_v and is1_instr_v_din and ex3_frt_v_forbyp and ex3_instr_v_din and not ex3_ld_v and (ex3_ta = is1_frb)) and not is1_cancel_bypass; + + is1_ex6_c_bypass <= (is1_frc_v and is1_instr_v_din and ex3_frt_v_forbyp and ex3_instr_v_din and not ex3_ld_v and (ex3_ta = is1_frc)) and not is1_cancel_bypass; + + + +-- load to arith bypass logic +is1_ld6_a_bypass <= ((is1_fra_v and is1_instr_v_din and ex4_ld_v and (ex4_ta = is1_fra)) and not is1_cancel_bypass); -- or -- load hit + -- ((is1_fra_v and is1_instr_v and lmc_ex3_v and (lmc_ex3 = is1_fra)) and not is1_cancel_bypass); -- load miss complete + +is1_ld6_b_bypass <= ((is1_frb_v and is1_instr_v_din and ex4_ld_v and (ex4_ta = is1_frb)) and not is1_cancel_bypass); -- or -- load hit + -- ((is1_frb_v and is1_instr_v and lmc_ex3_v and (lmc_ex3 = is1_frb)) and not is1_cancel_bypass); -- load miss complete + +is1_ld6_c_bypass <= ((is1_frc_v and is1_instr_v_din and ex4_ld_v and (ex4_ta = is1_frc)) and not is1_cancel_bypass); -- or -- load hit + -- ((is1_frc_v and is1_instr_v and lmc_ex3_v and (lmc_ex3 = is1_frc)) and not is1_cancel_bypass); -- load miss complete + + +is1_bypsel(0) <= is1_ld6_a_bypass; -- ld bypassed to fa ex1 +is1_bypsel(1) <= is1_ld6_c_bypass; -- ld bypassed to fc ex1 +is1_bypsel(2) <= is1_ld6_b_bypass; -- ld bypassed to fb ex1 + +is1_bypsel(3) <= is1_ex6_a_bypass; -- ex6 bypassed to fa ex1 +is1_bypsel(4) <= is1_ex6_c_bypass; -- ex6 bypassed to fc ex1 +is1_bypsel(5) <= is1_ex6_b_bypass; -- ex6 bypassed to fb ex1 + + + is2_bypass_latch: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 6) + port map ( + nclk => nclk, vd => vdd, gd => gnd, + forcee => forcee, mpw1_b => mpw1_b, mpw2_b => mpw2_b, + delay_lclkr => delay_lclkr, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + scin => is2_bypass_latch_scin, + scout => is2_bypass_latch_scout, + --------------------------------------------- + din(0 to 5) => is1_bypsel, + --------------------------------------------- + dout(0 to 5) => is2_bypsel + --------------------------------------------- + ); + + ifdp_is2_bypsel <= is2_bypsel; + +-- + + ----------------------------------------------------------------------- + -- latches for clock gating/timing + + +is2_act_din <= is2_instr_v or disable_cgat; +rf0_act_din <= rf0_instr_v or disable_cgat; +rf1_act_din <= rf1_instr_v or disable_cgat; +ex1_act_din <= ex1_instr_v or disable_cgat; +ex2_act_din <= ex2_instr_v or disable_cgat; +ex3_act_din <= ex3_instr_v or disable_cgat; + + + act_latch: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 8) + port map ( + nclk => nclk, vd => vdd, gd => gnd, + forcee => forcee, mpw1_b => mpw1_b, mpw2_b => mpw2_b, + delay_lclkr => delay_lclkr, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + scin => act_latch_scin, + scout => act_latch_scout, + --------------------------------------------- + din(0) => is2_act_din, + din(1) => rf0_act_din, + din(2) => rf1_act_din, + din(3) => ex1_act_din, + din(4) => ex2_act_din, + din(5) => ex3_act_din, + din(6) => spare_l2(3), + din(7) => spare_l2(4), + + --------------------------------------------- + dout(0) => is2_act_l2, + dout(1) => rf0_act_l2, + dout(2) => rf1_act_l2, + dout(3) => ex1_act_l2, + dout(4) => ex2_act_l2, + dout(5) => ex3_act_l2, + dout(6) => spare_l2(3), + dout(7) => spare_l2(4) + + --------------------------------------------- + ); + + ----------------------------------------------------------------------- + + +-- shadow pipe staging + +is2_act <= is2_instr_v or is2_act_l2; + + rf0_sp_latch : tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 15) + port map ( + nclk => nclk, vd => vdd, gd => gnd, + forcee => forcee, mpw1_b => mpw1_b, mpw2_b => mpw2_b, + delay_lclkr => delay_lclkr, + act => is2_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + scin => rf0_sp_latch_scin(0 to 14), + scout => rf0_sp_latch_scout(0 to 14), + --------------------------------------------- + din(0 to 5) => is2_ta(0 to 5), + din(6) => is2_ld_v_din, + din(7) => spare_l2(0), + din(8) => is2_instr_v_din, + din(9) => is2_frt_v_din, + din(10) => is2_fmul_uc_din, + din(11) => is2_crt_v_din, + din(12) => bubble3_is2_din, + din(13) => is2_cmiss_flush_din, -- flush due to waw with cmiss + din(14) => ignore_flush_is2_din, + --------------------------------------------- + dout(0 to 5) => rf0_ta(0 to 5), + dout(6) => rf0_ld_v, + dout(7) => spare_l2(0), + dout(8) => rf0_instr_v, + dout(9) => rf0_frt_v, + dout(10) => rf0_fmul_uc, + dout(11) => rf0_crt_v, + dout(12) => bubble3_rf0, + dout(13) => rf0_cmiss_flush, + dout(14) => ignore_flush_rf0 + --------------------------------------------- + ); + +spare_unused(04) <= tidn; + +rf0_act <= rf0_instr_v or rf0_act_l2; + + rf1_sp_latch : tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 15) + port map ( + nclk => nclk, vd => vdd, gd => gnd, + forcee => forcee, mpw1_b => mpw1_b, mpw2_b => mpw2_b, + delay_lclkr => delay_lclkr, + act => rf0_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + scin => rf1_sp_latch_scin(0 to 14), + scout => rf1_sp_latch_scout(0 to 14), + --------------------------------------------- + din(0 to 5) => rf0_ta(0 to 5), + din(6) => rf0_ld_v_din, + din(7) => spare_l2(1), + din(8) => rf0_instr_v_din, + din(9) => rf0_frt_v_din, + din(10) => rf0_fmul_uc_din, + din(11) => rf0_crt_v_din, + din(12) => bubble3_rf0_din, + din(13) => rf0_cmiss_flush_din, + din(14) => ignore_flush_rf0_din, + + --------------------------------------------- + dout(0 to 5) => rf1_ta(0 to 5), + dout(6) => rf1_ld_v, + dout(7) => spare_l2(1), + dout(8) => rf1_instr_v, + dout(9) => rf1_frt_v, + dout(10) => rf1_fmul_uc, + dout(11) => rf1_crt_v, + dout(12) => bubble3_rf1, + dout(13) => rf1_cmiss_flush, + dout(14) => ignore_flush_rf1 + --------------------------------------------- + ); + + spare_unused(05) <= tidn; + + rf1_act <= rf1_instr_v or rf1_act_l2; + + ex1_sp_latch: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 15) + port map ( + nclk => nclk, vd => vdd, gd => gnd, + forcee => forcee, mpw1_b => mpw1_b, mpw2_b => mpw2_b, + delay_lclkr => delay_lclkr, + act => rf1_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + scin => ex1_sp_latch_scin, + scout => ex1_sp_latch_scout, + --------------------------------------------- + din(0 to 5) => rf1_ta(0 to 5), + din(6) => rf1_ld_v_din, + din(7) => spare_l2(2), + din(8) => rf1_instr_v_din, + din(9) => rf1_frt_v_din, + din(10) => rf1_fmul_uc_din, + din(11) => rf1_crt_v_din, + din(12) => bubble3_rf1_din, + din(13) => rf1_cmiss_flush_din, -- one flush will suffice + din(14) => ignore_flush_rf1_din, + --------------------------------------------- + dout(0 to 5) => ex1_ta(0 to 5), + dout(6) => ex1_ld_v, + dout(7) => spare_l2(2), + dout(8) => ex1_instr_v, + dout(9) => ex1_frt_v, + dout(10) => ex1_fmul_uc, + dout(11) => ex1_crt_v, + dout(12) => bubble3_ex1, + dout(13) => ex1_cmiss_flush, + dout(14) => ignore_flush_ex1 + --------------------------------------------- + ); + + spare_unused(06) <= tidn; + + + ex1_act <= ex1_instr_v or ex1_act_l2; + + ex2_sp_latch: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 14) + port map ( + nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act, + forcee => forcee, mpw1_b => mpw1_b, mpw2_b => mpw2_b, + delay_lclkr => delay_lclkr, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + scin => ex2_sp_latch_scin, + scout => ex2_sp_latch_scout, + --------------------------------------------- + din(0 to 5) => ex1_ta(0 to 5), + din(06) => ex1_ld_v_din, + din(07) => xu_au_loadmiss_target(0), + din(08) => ex1_instr_v_din, + din(09) => ex1_frt_v_din, + din(10) => ex1_fmul_uc_din, + din(11) => ex1_crt_v_din, + din(12) => ex1_cmiss_flush_din, + din(13) => ignore_flush_ex1_din, + --------------------------------------------- + dout(0 to 5) => ex2_ta(0 to 5), + dout(06) => ex2_ld_v, + dout(07) => spare_unused(07), + dout(08) => ex2_instr_v, + dout(09) => ex2_frt_v, + dout(10) => ex2_fmul_uc, + dout(11) => ex2_crt_v, + dout(12) => ex2_cmiss_flush, + dout(13) => ignore_flush_ex2 + --------------------------------------------- + ); + + ex2_act <= ex2_instr_v or ex2_act_l2; + + ex3_sp_latch: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 14) + port map ( + nclk => nclk, vd => vdd, gd => gnd, + act => ex2_act, + forcee => forcee, mpw1_b => mpw1_b, mpw2_b => mpw2_b, + delay_lclkr => delay_lclkr, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + scin => ex3_sp_latch_scin, + scout => ex3_sp_latch_scout, + --------------------------------------------- + din(0 to 5) => ex2_ta(0 to 5), + din(6) => ex2_ld_v_din, + din(7) => xu_au_loadmiss_target(1), + din(8) => ex2_instr_v_din, + din(9) => ex2_frt_v_din, + din(10) => ex2_fmul_uc_din, + din(11) => ex2_crt_v_din, + din(12) => ex2_frt_v, -- for bypass + din(13) => ignore_flush_ex2_din, + --------------------------------------------- + dout(0 to 5) => ex3_ta(0 to 5), + dout(6) => ex3_ld_v, + dout(7) => spare_unused(08), + dout(8) => ex3_instr_v, + dout(9) => ex3_frt_v, + dout(10) => ex3_fmul_uc, + dout(11) => ex3_crt_v, + dout(12) => ex3_frt_v_forbyp, + dout(13) => ignore_flush_ex3 + --------------------------------------------- + ); + + + ex3_act <= ex3_instr_v or ex3_act_l2; + + ex4_sp_latch: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 13) + port map ( + nclk => nclk, vd => vdd, gd => gnd, + forcee => forcee, mpw1_b => mpw1_b, mpw2_b => mpw2_b, + delay_lclkr => delay_lclkr, + act => ex3_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + scin => ex4_sp_latch_scin, + scout => ex4_sp_latch_scout, + --------------------------------------------- + din(0 to 5) => ex3_ta(0 to 5), + din(6) => ex3_ld_v_din, + din(7) => ex3_instr_v_din, + din(8) => ex3_frt_v_din, + din(9) => ex3_fmul_uc_din, + din(10) => ex3_crt_v_din, + din(11) => xu_au_loadmiss_target(2), + din(12) => ignore_flush_ex3_din, + --------------------------------------------- + dout(0 to 5) => ex4_ta(0 to 5), + dout(6) => ex4_ld_v, + dout(7) => ex4_instr_v, + dout(8) => ex4_frt_v, + dout(9) => ex4_fmul_uc, + dout(10) => ex4_crt_v, + dout(11) => spare_unused(09), + dout(12) => ignore_flush_ex4 + --------------------------------------------- + ); + + + + + ex5_sp_latch: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 11) + port map ( + nclk => nclk, vd => vdd, gd => gnd, + forcee => forcee, mpw1_b => mpw1_b, mpw2_b => mpw2_b, + delay_lclkr => delay_lclkr, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + scin => ex5_sp_latch_scin, + scout => ex5_sp_latch_scout, + --------------------------------------------- + din(0) => ex4_instr_v_din, + din(1) => ex4_fmul_uc_din, + din(2) => set_lm0, + din(3) => set_lm1, + din(4) => set_lm2, + din(5) => set_lm3, + din(6) => set_lm4, + din(7) => set_lm5, + din(8) => set_lm6, + din(9) => set_lm7, + din(10) => ignore_flush_ex4_din, + --------------------------------------------- + dout(0) => ex5_instr_v, + dout(1) => ex5_fmul_uc, + dout(2) => set_lm0_1d, + dout(3) => set_lm1_1d, + dout(4) => set_lm2_1d, + dout(5) => set_lm3_1d, + dout(6) => set_lm4_1d, + dout(7) => set_lm5_1d, + dout(8) => set_lm6_1d, + dout(9) => set_lm7_1d, + dout(10) => ignore_flush_ex5 + + --------------------------------------------- + ); + +ifdp_ex5_fmul_uc_complete <= ex5_fmul_uc; + + ex6_sp_latch: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 2) + port map ( + nclk => nclk, vd => vdd, gd => gnd, + forcee => forcee, mpw1_b => mpw1_b, mpw2_b => mpw2_b, + delay_lclkr => delay_lclkr, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + scin => ex6_sp_latch_scin, + scout => ex6_sp_latch_scout, + --------------------------------------------- + din(0) => ex5_instr_v_din, + din(1) => ignore_flush_ex5_din, + --------------------------------------------- + dout(0) => ex6_instr_v, + dout(1) => ignore_flush_ex6 + --------------------------------------------- + ); + + ---------------------------------------------------------------------------------- + ---------------------------------------------------------------------------------- + -- Single step chicken switch stuff + + + busy_latch: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 3) + port map ( + nclk => nclk, vd => vdd, gd => gnd, + forcee => forcee, mpw1_b => mpw1_b, mpw2_b => mpw2_b, + delay_lclkr => delay_lclkr, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + scin => busy_latch_scin, + scout => busy_latch_scout, + --------------------------------------------- + din(0) => fu_busy, + din(1) => fmul_uc_busy, + din(2) => ignore_flush_busy, + + --------------------------------------------- + dout(0) => fu_busy_l2, + dout(1) => fmul_uc_busy_l2, + dout(2) => ignore_flush_busy_l2 + + --------------------------------------------- + ); + + + + + +ignore_flush_busy <= is2_stage_dout(34) or + ignore_flush_rf0 or ignore_flush_rf1 or ignore_flush_ex1 or ignore_flush_ex2 or + ignore_flush_ex3 or ignore_flush_ex4 or ignore_flush_ex5 or ignore_flush_ex6; + +is2_ignore_flush_busy <= is2_stage_dout(34) or ignore_flush_busy_l2; + + +fu_busy <= is2_instr_v or rf0_instr_v or rf1_instr_v or + ex1_instr_v or ex2_instr_v or ex3_instr_v or ex4_instr_v or ex5_instr_v or ex6_instr_v or + lmc_ex4_v or lmc_ex5_v or lmc_ex6_v or -- want to cover the time when the reload is coming back also + lm0_valid or lm1_valid or lm2_valid or lm3_valid or + lm4_valid or lm5_valid or lm6_valid or lm7_valid; + + is2_axubusy <= is2_instr_v or fu_busy_l2; +au_iu_is2_axubusy <= is2_axubusy ; + +fmul_uc_busy <= is2_fmul_uc_din or rf0_fmul_uc_din or rf1_fmul_uc_din or ex1_fmul_uc_din or + ex2_fmul_uc_din or ex3_fmul_uc_din or ex4_fmul_uc_din or ex5_fmul_uc_din; + + +is1_singlestep_ucode <= ( ((is1_to_ucode or is1_is_ucode) and is2_axubusy) -- create stall when (is1 has ucode op) and (axu is busy) + or ( is1_fmul_uc and is2_axubusy) -- create stall when (is1 is fmul_uc) and (axu is busy) + or ( fmul_uc_busy_l2 ) ) -- create stall when fmul_uc is in the pipe + and config_iucr(3); -- note: nop after fmul_uc will issue since its an XU op + +is1_singlestep_pn <= ((ppc_div_sqrt_is1 and is2_axubusy) or -- create stall when (is1 has fdiv/fsqrt op) and (axu is busy) + (is1_instr_v and is2_ignore_flush_busy)) + and iucr2_ss_ignore_flush ; + + + is1_singlestep <= is1_singlestep_ucode or is1_singlestep_pn or (is2_axubusy and config_iucr(2)); + + + + +----------------------------------------------------------------------- +--LMQ latches +----------------------------------------------------------------------- + lmq0_latch: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 7) + port map ( + nclk => nclk, vd => vdd, gd => gnd, + forcee => forcee, mpw1_b => mpw1_b, mpw2_b => mpw2_b, + delay_lclkr => delay_lclkr, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + scin => lmq0_latch_scin, + scout => lmq0_latch_scout, + --------------------------------------------- + din(0) => lm0_valid_din, + din(1 to 6) => lm0_ta_din(0 to 5), + --------------------------------------------- + dout(0) => lm0_valid, + dout(1 to 6) => lm0_ta(0 to 5) + --------------------------------------------- + ); + lmq1_latch: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 7) + port map ( + nclk => nclk, vd => vdd, gd => gnd, + forcee => forcee, mpw1_b => mpw1_b, mpw2_b => mpw2_b, + --d_mode => d_mode, + delay_lclkr => delay_lclkr, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + scin => lmq1_latch_scin , + scout => lmq1_latch_scout, + --------------------------------------------- + din(0) => lm1_valid_din, + din(1 to 6) => lm1_ta_din(0 to 5), + --------------------------------------------- + dout(0) => lm1_valid, + dout(1 to 6) => lm1_ta(0 to 5) + --------------------------------------------- + ); + lmq2_latch: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 7) + port map ( + nclk => nclk, vd => vdd, gd => gnd, + forcee => forcee, mpw1_b => mpw1_b, mpw2_b => mpw2_b, + delay_lclkr => delay_lclkr, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + scin => lmq2_latch_scin, + scout => lmq2_latch_scout, + --------------------------------------------- + din(0) => lm2_valid_din, + din(1 to 6) => lm2_ta_din(0 to 5), + --------------------------------------------- + dout(0) => lm2_valid, + dout(1 to 6) => lm2_ta(0 to 5) + --------------------------------------------- + ); + lmq3_latch: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 7) + port map ( + nclk => nclk, vd => vdd, gd => gnd, + forcee => forcee, mpw1_b => mpw1_b, mpw2_b => mpw2_b, + delay_lclkr => delay_lclkr, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + scin => lmq3_latch_scin, + scout => lmq3_latch_scout, + --------------------------------------------- + din(0) => lm3_valid_din, + din(1 to 6) => lm3_ta_din(0 to 5), + --------------------------------------------- + dout(0) => lm3_valid, + dout(1 to 6) => lm3_ta(0 to 5) + --------------------------------------------- + ); + lmq4_latch: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 7) + port map ( + nclk => nclk, vd => vdd, gd => gnd, + forcee => forcee, mpw1_b => mpw1_b, mpw2_b => mpw2_b, + delay_lclkr => delay_lclkr, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + scin => lmq4_latch_scin, + scout => lmq4_latch_scout, + --------------------------------------------- + din(0) => lm4_valid_din, + din(1 to 6) => lm4_ta_din(0 to 5), + --------------------------------------------- + dout(0) => lm4_valid, + dout(1 to 6) => lm4_ta(0 to 5) + --------------------------------------------- + ); + lmq5_latch: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 7) + port map ( + nclk => nclk, vd => vdd, gd => gnd, + forcee => forcee, mpw1_b => mpw1_b, mpw2_b => mpw2_b, + delay_lclkr => delay_lclkr, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + scin => lmq5_latch_scin, + scout => lmq5_latch_scout, + --------------------------------------------- + din(0) => lm5_valid_din, + din(1 to 6) => lm5_ta_din(0 to 5), + --------------------------------------------- + dout(0) => lm5_valid, + dout(1 to 6) => lm5_ta(0 to 5) + --------------------------------------------- + ); + lmq6_latch: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 7) + port map ( + nclk => nclk, vd => vdd, gd => gnd, + forcee => forcee, mpw1_b => mpw1_b, mpw2_b => mpw2_b, + delay_lclkr => delay_lclkr, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + scin => lmq6_latch_scin, + scout => lmq6_latch_scout, + --------------------------------------------- + din(0) => lm6_valid_din, + din(1 to 6) => lm6_ta_din(0 to 5), + --------------------------------------------- + dout(0) => lm6_valid, + dout(1 to 6) => lm6_ta(0 to 5) + --------------------------------------------- + ); + lmq7_latch: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 7) + port map ( + nclk => nclk, vd => vdd, gd => gnd, + forcee => forcee, mpw1_b => mpw1_b, mpw2_b => mpw2_b, + delay_lclkr => delay_lclkr, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + scin => lmq7_latch_scin, + scout => lmq7_latch_scout, + --------------------------------------------- + din(0) => lm7_valid_din, + din(1 to 6) => lm7_ta_din(0 to 5), + --------------------------------------------- + dout(0) => lm7_valid, + dout(1 to 6) => lm7_ta(0 to 5) + --------------------------------------------- + ); + + +----------------------------------------------------------------------- + + +-- cache miss (xu_au_loadmiss_vld=1) is a stage ex4 signal +-- fop in is1 has raw or waw dependency on load that just got a cmiss. is1 must be flushed + +is1_cmiss_flush <= ex4_ld_v and xu_au_loadmiss_vld and not is1_stall_rep and is1_instr_v and + ((is1_frt_v and (ex4_ta(0 to 5) = is1_ta(0 to 5))) + or + (is1_fra_v and (ex4_ta(0 to 5) = is1_fra(0 to 5))) + or + (is1_frb_v and (ex4_ta(0 to 5) = is1_frb(0 to 5))) + or + (is1_frc_v and (ex4_ta(0 to 5) = is1_frc(0 to 5)))); + + +-- cache miss (xu_au_loadmiss_vld=1) is a stage ex4 signal +-- fop in is2 has raw or war dependency on load that just got a cmiss. is2 must be flushed + + +is2_cmiss_flush <= ex4_ld_v and xu_au_loadmiss_vld and is2_instr_v and + ((is2_frt_v and (ex4_ta(0 to 5) = is2_ta(0 to 5))) + or + (is2_fra_v and (ex4_ta(0 to 5) = is2_fra(0 to 5))) + or + (is2_frb_v and (ex4_ta(0 to 5) = is2_frb(0 to 5))) + or + (is2_frc_v and (ex4_ta(0 to 5) = is2_frc(0 to 5)))); + +-- WAW checking for loads +rf0_cmiss_waw_flush <= ex4_ld_v and xu_au_loadmiss_vld and rf0_instr_v and (rf0_frt_v and (ex4_ta(0 to 5) = rf0_ta(0 to 5))); +rf1_cmiss_waw_flush <= ex4_ld_v and xu_au_loadmiss_vld and rf1_instr_v and (rf1_frt_v and (ex4_ta(0 to 5) = rf1_ta(0 to 5))); +ex1_cmiss_waw_flush <= ex4_ld_v and xu_au_loadmiss_vld and ex1_instr_v and (ex1_frt_v and (ex4_ta(0 to 5) = ex1_ta(0 to 5))); + + +is2_cmiss_flush_din <= (is2_cmiss_flush or is2_cmiss_flush_q or is2_stage_dout(42)); -- passing the flush down the pipe + +rf0_cmiss_flush_din <= rf0_cmiss_flush or rf0_cmiss_waw_flush; +rf1_cmiss_flush_din <= rf1_cmiss_flush or rf1_cmiss_waw_flush; +ex1_cmiss_flush_din <= ex1_cmiss_flush or ex1_cmiss_waw_flush; + +-- Output to FU +iu_fu_ex2_n_flush <= ex2_cmiss_flush and ex2_instr_v; -- fop in ex1 must be flushed due to waw dependency that got a cmiss + + +----------------------------------------------------------------------- + + + + + debug_latch_for_timing: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 16) + port map ( + nclk => nclk, vd => vdd, gd => gnd, + forcee => forcee, mpw1_b => mpw1_b, mpw2_b => mpw2_b, + delay_lclkr => delay_lclkr, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + scin => debug_scin, + scout => debug_scout, + --------------------------------------------- + din(0) => is1_dep_hit, + din(1) => is1_raw_hit, + din(2) => raw_fra_hit, + din(3) => raw_frb_hit, + din(4) => raw_frc_hit, + din(5) => is1_prebubble_skip, + din(6) => raw_cr_hit, + din(7) => bubble3_is1, + din(8) => is1_lmq_waw_hit, + din(9) => is1_waw_load_hit, + din(10) => iu_au_is1_hold, + din(11) => iu_au_is2_stall, + din(12) => iu_au_is1_flush, + din(13) => iu_au_is2_flush, + din(14) => iu_au_rf0_flush, + din(15) => is1_instr_v_din, + --------------------------------------------- + dout(0) => is1_dep_hit_db, + dout(1) => is1_raw_hit_db, + dout(2) => raw_fra_hit_db, + dout(3) => raw_frb_hit_db, + dout(4) => raw_frc_hit_db, + dout(5) => is1_prebubble_skip_db, + dout(6) => raw_cr_hit_db, + dout(7) => bubble3_is1_db, + dout(8) => is1_lmq_waw_hit_db, + dout(9) => is1_waw_load_hit_db, + dout(10) => iu_au_is1_hold_db, + dout(11) => iu_au_is2_stall_db, + dout(12) => iu_au_is1_flush_db, + dout(13) => iu_au_is2_flush_db, + dout(14) => iu_au_rf0_flush_db, + dout(15) => is1_instr_v_din_db + --------------------------------------------- + ); + + ----------------------------------------------------------------------- + +-- note that is1 instr_v_db is delayed by 1 cycle from the other valids (for timing) +fu_dep_debug(0 to 23) <= is1_dep_hit_db & is1_raw_hit_db & raw_fra_hit_db & raw_frb_hit_db & + raw_frc_hit_db & is1_prebubble_skip_db & raw_cr_hit_db & bubble3_is1_db & + is1_lmq_waw_hit_db & is1_waw_load_hit_db & iu_au_is1_hold_db & iu_au_is2_stall_db & + iu_au_is1_flush_db & iu_au_is2_flush_db & iu_au_rf0_flush_db & is1_instr_v_din_db & + is2_instr_v & rf0_instr_v & rf1_instr_v & + is2_ta(1 to 5); + + ----------------------------------------------------------------------- + + + +-- scan chain + +ppc_rc_latch_scin <= i_dep_si; + +is2_stage_latch_scin(0) <= ppc_rc_latch_scout; + +is2_stage_latch_scin(1 to 42) <= is2_stage_latch_scout(0 to 41); + +is2_bypass_latch_scin(0) <= is2_stage_latch_scout(42); +is2_bypass_latch_scin(1 to 5) <= is2_bypass_latch_scout(0 to 4); + +rf0_sp_latch_scin(0) <= is2_bypass_latch_scout(5); +rf0_sp_latch_scin(1 to 14) <= rf0_sp_latch_scout(0 to 13); + +rf1_sp_latch_scin(0) <= rf0_sp_latch_scout(14); +rf1_sp_latch_scin(1 to 14) <= rf1_sp_latch_scout(0 to 13); + +ex1_sp_latch_scin(0) <= rf1_sp_latch_scout(14); +ex1_sp_latch_scin(1 to 14) <= ex1_sp_latch_scout(0 to 13); + +ex2_sp_latch_scin(0) <= ex1_sp_latch_scout(14); +ex2_sp_latch_scin(1 to 13) <= ex2_sp_latch_scout(0 to 12); + +ex3_sp_latch_scin(0) <= ex2_sp_latch_scout(13); +ex3_sp_latch_scin(1 to 13) <= ex3_sp_latch_scout(0 to 12); + +ex4_sp_latch_scin(0) <= ex3_sp_latch_scout(13); +ex4_sp_latch_scin(1 to 12) <= ex4_sp_latch_scout(0 to 11); + +ex5_sp_latch_scin(0) <= ex4_sp_latch_scout(12); +ex5_sp_latch_scin(1 to 10) <= ex5_sp_latch_scout(0 to 9); + +ex6_sp_latch_scin(0) <= ex5_sp_latch_scout(10); +ex6_sp_latch_scin(1) <= ex6_sp_latch_scout(0); + +busy_latch_scin(0) <= ex6_sp_latch_scout(1); +busy_latch_scin(1 to 2) <= busy_latch_scout(0 to 1); + +act_latch_scin(0) <= busy_latch_scout(2); +act_latch_scin(1 to 7) <= act_latch_scout(0 to 6); + + +lmq0_latch_scin(0) <= act_latch_scout(7); +lmq0_latch_scin(1 to 6) <= lmq0_latch_scout(0 to 5); + +lmq1_latch_scin(0) <= lmq0_latch_scout(6); +lmq1_latch_scin(1 to 6) <= lmq1_latch_scout(0 to 5); + +lmq2_latch_scin(0) <= lmq1_latch_scout(6); +lmq2_latch_scin(1 to 6) <= lmq2_latch_scout(0 to 5); + +lmq3_latch_scin(0) <= lmq2_latch_scout(6); +lmq3_latch_scin(1 to 6) <= lmq3_latch_scout(0 to 5); + +lmq4_latch_scin(0) <= lmq3_latch_scout(6); +lmq4_latch_scin(1 to 6) <= lmq4_latch_scout(0 to 5); + +lmq5_latch_scin(0) <= lmq4_latch_scout(6); +lmq5_latch_scin(1 to 6) <= lmq5_latch_scout(0 to 5); + +lmq6_latch_scin(0) <= lmq5_latch_scout(6); +lmq6_latch_scin(1 to 6) <= lmq6_latch_scout(0 to 5); + +lmq7_latch_scin(0) <= lmq6_latch_scout(6); +lmq7_latch_scin(1 to 6) <= lmq7_latch_scout(0 to 5); + +lmiss_comp_ex1_latch_scin(0) <= lmq7_latch_scout(6); +lmiss_comp_ex1_latch_scin(1 to 7) <= lmiss_comp_ex1_latch_scout(0 to 6); + +lmiss_comp_ex2_latch_scin(0) <= lmiss_comp_ex1_latch_scout(7); +lmiss_comp_ex2_latch_scin(1 to 7) <= lmiss_comp_ex2_latch_scout(0 to 6); + +lmiss_comp_ex3_latch_scin(0) <= lmiss_comp_ex2_latch_scout(7); +lmiss_comp_ex3_latch_scin(1 to 7) <= lmiss_comp_ex3_latch_scout(0 to 6); + +lmc_ex4_latch_scin(0) <= lmiss_comp_ex3_latch_scout(7); +lmc_ex4_latch_scin(1 to 6) <= lmc_ex4_latch_scout(0 to 5); + +lmc_ex5_latch_scin <= lmc_ex4_latch_scout(6); +lmc_ex6_latch_scin <= lmc_ex5_latch_scout; + +debug_scin(0) <= lmc_ex6_latch_scout; +debug_scin(1 to 15) <= debug_scout(0 to 14); + + +i_dep_so <= debug_scout(15); + + + +end iuq_axu_fu_dep; diff --git a/rel/src/vhdl/work/iuq_axu_fu_dep_cmp.vhdl b/rel/src/vhdl/work/iuq_axu_fu_dep_cmp.vhdl new file mode 100644 index 0000000..2f9c2a2 --- /dev/null +++ b/rel/src/vhdl/work/iuq_axu_fu_dep_cmp.vhdl @@ -0,0 +1,1197 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; + use ieee.std_logic_1164.all ; +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; +library support; + use support.power_logic_pkg.all; + + + +entity iuq_axu_fu_dep_cmp is + +port( + lm_v : in std_ulogic_vector(0 to 7); + is1_instr_v : in std_ulogic; + --------------------------------------------------------------------- + vdd : inout power_logic; + gnd : inout power_logic; + --------------------------------------------------------------------- + lmc_ex4_v : in std_ulogic; + dis_byp_is1 : in std_ulogic; -- note: dis_byp does NOT disable the writethru case for loads + is1_store_v : in std_ulogic; + ex3_ld_v : in std_ulogic; + ex4_ld_v : in std_ulogic; + uc_end_is1 : in std_ulogic; + + is2_frt_v : in std_ulogic; + rf0_frt_v : in std_ulogic; + rf1_frt_v : in std_ulogic; + ex1_frt_v : in std_ulogic; + ex2_frt_v : in std_ulogic; + ex3_frt_v : in std_ulogic; + ex4_frt_v : in std_ulogic; + + + lm0_ta : in std_ulogic_vector(0 to 5); + lm1_ta : in std_ulogic_vector(0 to 5); + lm2_ta : in std_ulogic_vector(0 to 5); + lm3_ta : in std_ulogic_vector(0 to 5); + lm4_ta : in std_ulogic_vector(0 to 5); + lm5_ta : in std_ulogic_vector(0 to 5); + lm6_ta : in std_ulogic_vector(0 to 5); + lm7_ta : in std_ulogic_vector(0 to 5); + lmc_ex4 : in std_ulogic_vector(0 to 5); + ex4_ta : in std_ulogic_vector(0 to 5); + ex3_ta : in std_ulogic_vector(0 to 5); + ex2_ta : in std_ulogic_vector(0 to 5); + ex1_ta : in std_ulogic_vector(0 to 5); + rf1_ta : in std_ulogic_vector(0 to 5); + rf0_ta : in std_ulogic_vector(0 to 5); + is2_ta : in std_ulogic_vector(0 to 5); + + is1_fra_v : in std_ulogic; + is1_frb_v : in std_ulogic; + is1_frc_v : in std_ulogic; + is1_frt_v : in std_ulogic; + + is1_fra : in std_ulogic_vector(0 to 5); + is1_frb : in std_ulogic_vector(0 to 5); + is1_frc : in std_ulogic_vector(0 to 5); + is1_ta : in std_ulogic_vector(0 to 5); + + raw_fra_hit_b : out std_ulogic; + raw_frb_hit_b : out std_ulogic; + raw_frc_hit_b : out std_ulogic; + + raw_frb_uc_hit_b : out std_ulogic; + is1_lmq_waw_hit_b : out std_ulogic + + ); + + +end iuq_axu_fu_dep_cmp; +------------------------------------------------------------------------------------------------------------------------------------ + +architecture iuq_axu_fu_dep_cmp of iuq_axu_fu_dep_cmp is + + signal lm0_ta_buf, lm0_ta_buf_b :std_ulogic_vector(0 to 5); + signal lm1_ta_buf, lm1_ta_buf_b :std_ulogic_vector(0 to 5); + signal lm2_ta_buf, lm2_ta_buf_b :std_ulogic_vector(0 to 5); + signal lm3_ta_buf, lm3_ta_buf_b :std_ulogic_vector(0 to 5); + signal lm4_ta_buf, lm4_ta_buf_b :std_ulogic_vector(0 to 5); + signal lm5_ta_buf, lm5_ta_buf_b :std_ulogic_vector(0 to 5); + signal lm6_ta_buf, lm6_ta_buf_b :std_ulogic_vector(0 to 5); + signal lm7_ta_buf, lm7_ta_buf_b :std_ulogic_vector(0 to 5); + signal lmc_ex4_buf, lmc_ex4_buf_b :std_ulogic_vector(0 to 5); + signal ex4_ta_buf, ex4_ta_buf_b :std_ulogic_vector(0 to 5); + signal ex3_ta_buf, ex3_ta_buf_b :std_ulogic_vector(0 to 5); + signal ex2_ta_buf, ex2_ta_buf_b :std_ulogic_vector(0 to 5); + signal ex1_ta_buf, ex1_ta_buf_b :std_ulogic_vector(0 to 5); + signal rf1_ta_buf, rf1_ta_buf_b :std_ulogic_vector(0 to 5); + signal rf0_ta_buf, rf0_ta_buf_b :std_ulogic_vector(0 to 5); + signal is2_ta_buf, is2_ta_buf_b :std_ulogic_vector(0 to 5); + + + signal is1_fra_buf1 :std_ulogic_vector(0 to 5); + signal is1_frb_buf1 :std_ulogic_vector(0 to 5); + signal is1_frc_buf1 :std_ulogic_vector(0 to 5); + signal is1_frt_buf1 :std_ulogic_vector(0 to 5); + signal is1_fra_buf2 :std_ulogic_vector(0 to 5); + signal is1_frb_buf2 :std_ulogic_vector(0 to 5); + signal is1_frc_buf2 :std_ulogic_vector(0 to 5); + signal is1_frt_buf2 :std_ulogic_vector(0 to 5); + signal is1_fra_buf3 :std_ulogic_vector(0 to 5); + signal is1_frb_buf3 :std_ulogic_vector(0 to 5); + signal is1_frc_buf3 :std_ulogic_vector(0 to 5); + signal is1_frt_buf3 :std_ulogic_vector(0 to 5); + signal is1_fra_buf4 :std_ulogic_vector(0 to 5); + signal is1_frb_buf4 :std_ulogic_vector(0 to 5); + signal is1_frc_buf4 :std_ulogic_vector(0 to 5); + signal is1_frt_buf4 :std_ulogic_vector(0 to 5); + signal is1_fra_buf5 :std_ulogic_vector(0 to 5); + signal is1_frb_buf5 :std_ulogic_vector(0 to 5); + signal is1_frc_buf5 :std_ulogic_vector(0 to 5); + signal is1_frt_buf5 :std_ulogic_vector(0 to 5); + signal is1_fra_buf6 :std_ulogic_vector(0 to 5); + signal is1_frb_buf6 :std_ulogic_vector(0 to 5); + signal is1_frc_buf6 :std_ulogic_vector(0 to 5); + signal is1_frt_buf6 :std_ulogic_vector(0 to 5); + + + + + signal is1_fra_buf2_b, is1_fra_buf1_b :std_ulogic_vector(0 to 5); + signal is1_frb_buf2_b, is1_frb_buf1_b :std_ulogic_vector(0 to 5); + signal is1_frc_buf2_b, is1_frc_buf1_b :std_ulogic_vector(0 to 5); + signal is1_frt_buf2_b, is1_frt_buf1_b :std_ulogic_vector(0 to 5); + + signal a_eq_lm0_x :std_ulogic_vector(0 to 5); + signal a_eq_lm0_01_b , a_eq_lm0_23_b , a_eq_lm0_45_b :std_ulogic; + signal a_eq_lm0_u ,a_eq_lm0_v , a_eq_lm0_b :std_ulogic; + signal b_eq_lm0_x :std_ulogic_vector(0 to 5); + signal b_eq_lm0_01_b , b_eq_lm0_23_b , b_eq_lm0_45_b :std_ulogic; + signal b_eq_lm0_u ,b_eq_lm0_v , b_eq_lm0_b :std_ulogic; + signal c_eq_lm0_x :std_ulogic_vector(0 to 5); + signal c_eq_lm0_01_b , c_eq_lm0_23_b , c_eq_lm0_45_b :std_ulogic; + signal c_eq_lm0_u ,c_eq_lm0_v , c_eq_lm0_b :std_ulogic; + signal t_eq_lm0_x :std_ulogic_vector(0 to 5); + signal t_eq_lm0_01_b , t_eq_lm0_23_b , t_eq_lm0_45_b :std_ulogic; + signal t_eq_lm0_u ,t_eq_lm0_v , t_eq_lm0_b :std_ulogic; + signal a_eq_lm1_x :std_ulogic_vector(0 to 5); + signal a_eq_lm1_01_b , a_eq_lm1_23_b , a_eq_lm1_45_b :std_ulogic; + signal a_eq_lm1_u ,a_eq_lm1_v , a_eq_lm1_b :std_ulogic; + signal b_eq_lm1_x :std_ulogic_vector(0 to 5); + signal b_eq_lm1_01_b , b_eq_lm1_23_b , b_eq_lm1_45_b :std_ulogic; + signal b_eq_lm1_u ,b_eq_lm1_v , b_eq_lm1_b :std_ulogic; + signal c_eq_lm1_x :std_ulogic_vector(0 to 5); + signal c_eq_lm1_01_b , c_eq_lm1_23_b , c_eq_lm1_45_b :std_ulogic; + signal c_eq_lm1_u ,c_eq_lm1_v , c_eq_lm1_b :std_ulogic; + signal t_eq_lm1_x :std_ulogic_vector(0 to 5); + signal t_eq_lm1_01_b , t_eq_lm1_23_b , t_eq_lm1_45_b :std_ulogic; + signal t_eq_lm1_u ,t_eq_lm1_v , t_eq_lm1_b :std_ulogic; + signal a_eq_lm2_x :std_ulogic_vector(0 to 5); + signal a_eq_lm2_01_b , a_eq_lm2_23_b , a_eq_lm2_45_b :std_ulogic; + signal a_eq_lm2_u ,a_eq_lm2_v , a_eq_lm2_b :std_ulogic; + signal b_eq_lm2_x :std_ulogic_vector(0 to 5); + signal b_eq_lm2_01_b , b_eq_lm2_23_b , b_eq_lm2_45_b :std_ulogic; + signal b_eq_lm2_u ,b_eq_lm2_v , b_eq_lm2_b :std_ulogic; + signal c_eq_lm2_x :std_ulogic_vector(0 to 5); + signal c_eq_lm2_01_b , c_eq_lm2_23_b , c_eq_lm2_45_b :std_ulogic; + signal c_eq_lm2_u ,c_eq_lm2_v , c_eq_lm2_b :std_ulogic; + signal t_eq_lm2_x :std_ulogic_vector(0 to 5); + signal t_eq_lm2_01_b , t_eq_lm2_23_b , t_eq_lm2_45_b :std_ulogic; + signal t_eq_lm2_u ,t_eq_lm2_v , t_eq_lm2_b :std_ulogic; + signal a_eq_lm3_x :std_ulogic_vector(0 to 5); + signal a_eq_lm3_01_b , a_eq_lm3_23_b , a_eq_lm3_45_b :std_ulogic; + signal a_eq_lm3_u ,a_eq_lm3_v , a_eq_lm3_b :std_ulogic; + signal b_eq_lm3_x :std_ulogic_vector(0 to 5); + signal b_eq_lm3_01_b , b_eq_lm3_23_b , b_eq_lm3_45_b :std_ulogic; + signal b_eq_lm3_u ,b_eq_lm3_v , b_eq_lm3_b :std_ulogic; + signal c_eq_lm3_x :std_ulogic_vector(0 to 5); + signal c_eq_lm3_01_b , c_eq_lm3_23_b , c_eq_lm3_45_b :std_ulogic; + signal c_eq_lm3_u ,c_eq_lm3_v , c_eq_lm3_b :std_ulogic; + signal t_eq_lm3_x :std_ulogic_vector(0 to 5); + signal t_eq_lm3_01_b , t_eq_lm3_23_b , t_eq_lm3_45_b :std_ulogic; + signal t_eq_lm3_u ,t_eq_lm3_v , t_eq_lm3_b :std_ulogic; + signal a_eq_lm4_x :std_ulogic_vector(0 to 5); + signal a_eq_lm4_01_b , a_eq_lm4_23_b , a_eq_lm4_45_b :std_ulogic; + signal a_eq_lm4_u ,a_eq_lm4_v , a_eq_lm4_b :std_ulogic; + signal b_eq_lm4_x :std_ulogic_vector(0 to 5); + signal b_eq_lm4_01_b , b_eq_lm4_23_b , b_eq_lm4_45_b :std_ulogic; + signal b_eq_lm4_u ,b_eq_lm4_v , b_eq_lm4_b :std_ulogic; + signal c_eq_lm4_x :std_ulogic_vector(0 to 5); + signal c_eq_lm4_01_b , c_eq_lm4_23_b , c_eq_lm4_45_b :std_ulogic; + signal c_eq_lm4_u ,c_eq_lm4_v , c_eq_lm4_b :std_ulogic; + signal t_eq_lm4_x :std_ulogic_vector(0 to 5); + signal t_eq_lm4_01_b , t_eq_lm4_23_b , t_eq_lm4_45_b :std_ulogic; + signal t_eq_lm4_u ,t_eq_lm4_v , t_eq_lm4_b :std_ulogic; + signal a_eq_lm5_x :std_ulogic_vector(0 to 5); + signal a_eq_lm5_01_b , a_eq_lm5_23_b , a_eq_lm5_45_b :std_ulogic; + signal a_eq_lm5_u ,a_eq_lm5_v , a_eq_lm5_b :std_ulogic; + signal b_eq_lm5_x :std_ulogic_vector(0 to 5); + signal b_eq_lm5_01_b , b_eq_lm5_23_b , b_eq_lm5_45_b :std_ulogic; + signal b_eq_lm5_u ,b_eq_lm5_v , b_eq_lm5_b :std_ulogic; + signal c_eq_lm5_x :std_ulogic_vector(0 to 5); + signal c_eq_lm5_01_b , c_eq_lm5_23_b , c_eq_lm5_45_b :std_ulogic; + signal c_eq_lm5_u ,c_eq_lm5_v , c_eq_lm5_b :std_ulogic; + signal t_eq_lm5_x :std_ulogic_vector(0 to 5); + signal t_eq_lm5_01_b , t_eq_lm5_23_b , t_eq_lm5_45_b :std_ulogic; + signal t_eq_lm5_u ,t_eq_lm5_v , t_eq_lm5_b :std_ulogic; + signal a_eq_lm6_x :std_ulogic_vector(0 to 5); + signal a_eq_lm6_01_b , a_eq_lm6_23_b , a_eq_lm6_45_b :std_ulogic; + signal a_eq_lm6_u ,a_eq_lm6_v , a_eq_lm6_b :std_ulogic; + signal b_eq_lm6_x :std_ulogic_vector(0 to 5); + signal b_eq_lm6_01_b , b_eq_lm6_23_b , b_eq_lm6_45_b :std_ulogic; + signal b_eq_lm6_u ,b_eq_lm6_v , b_eq_lm6_b :std_ulogic; + signal c_eq_lm6_x :std_ulogic_vector(0 to 5); + signal c_eq_lm6_01_b , c_eq_lm6_23_b , c_eq_lm6_45_b :std_ulogic; + signal c_eq_lm6_u ,c_eq_lm6_v , c_eq_lm6_b :std_ulogic; + signal t_eq_lm6_x :std_ulogic_vector(0 to 5); + signal t_eq_lm6_01_b , t_eq_lm6_23_b , t_eq_lm6_45_b :std_ulogic; + signal t_eq_lm6_u ,t_eq_lm6_v , t_eq_lm6_b :std_ulogic; + signal a_eq_lm7_x :std_ulogic_vector(0 to 5); + signal a_eq_lm7_01_b , a_eq_lm7_23_b , a_eq_lm7_45_b :std_ulogic; + signal a_eq_lm7_u ,a_eq_lm7_v , a_eq_lm7_b :std_ulogic; + signal b_eq_lm7_x :std_ulogic_vector(0 to 5); + signal b_eq_lm7_01_b , b_eq_lm7_23_b , b_eq_lm7_45_b :std_ulogic; + signal b_eq_lm7_u ,b_eq_lm7_v , b_eq_lm7_b :std_ulogic; + signal c_eq_lm7_x :std_ulogic_vector(0 to 5); + signal c_eq_lm7_01_b , c_eq_lm7_23_b , c_eq_lm7_45_b :std_ulogic; + signal c_eq_lm7_u ,c_eq_lm7_v , c_eq_lm7_b :std_ulogic; + signal t_eq_lm7_x :std_ulogic_vector(0 to 5); + signal t_eq_lm7_01_b , t_eq_lm7_23_b , t_eq_lm7_45_b :std_ulogic; + signal t_eq_lm7_u ,t_eq_lm7_v , t_eq_lm7_b :std_ulogic; + signal a_eq_lmc_ex4_x :std_ulogic_vector(0 to 5); + signal a_eq_lmc_ex4_01_b , a_eq_lmc_ex4_23_b , a_eq_lmc_ex4_45_b :std_ulogic; + signal a_eq_lmc_ex4_u ,a_eq_lmc_ex4_v , a_eq_lmc_ex4_b :std_ulogic; + signal b_eq_lmc_ex4_x :std_ulogic_vector(0 to 5); + signal b_eq_lmc_ex4_01_b , b_eq_lmc_ex4_23_b , b_eq_lmc_ex4_45_b :std_ulogic; + signal b_eq_lmc_ex4_u ,b_eq_lmc_ex4_v , b_eq_lmc_ex4_b :std_ulogic; + signal c_eq_lmc_ex4_x :std_ulogic_vector(0 to 5); + signal c_eq_lmc_ex4_01_b , c_eq_lmc_ex4_23_b , c_eq_lmc_ex4_45_b :std_ulogic; + signal c_eq_lmc_ex4_u ,c_eq_lmc_ex4_v , c_eq_lmc_ex4_b :std_ulogic; + signal a_eq_ex4_x :std_ulogic_vector(0 to 5); + signal a_eq_ex4_01_b , a_eq_ex4_23_b , a_eq_ex4_45_b :std_ulogic; + signal a_eq_ex4_u ,a_eq_ex4_v , a_eq_ex4_b :std_ulogic; + signal b_eq_ex4_x :std_ulogic_vector(0 to 5); + signal b_eq_ex4_01_b , b_eq_ex4_23_b , b_eq_ex4_45_b :std_ulogic; + signal b_eq_ex4_u ,b_eq_ex4_v , b_eq_ex4_b :std_ulogic; + signal u_eq_ex4_b :std_ulogic; + signal c_eq_ex4_x :std_ulogic_vector(0 to 5); + signal c_eq_ex4_01_b , c_eq_ex4_23_b , c_eq_ex4_45_b :std_ulogic; + signal c_eq_ex4_u ,c_eq_ex4_v , c_eq_ex4_b :std_ulogic; + signal a_eq_ex3_x :std_ulogic_vector(0 to 5); + signal a_eq_ex3_01_b , a_eq_ex3_23_b , a_eq_ex3_45_b :std_ulogic; + signal a_eq_ex3_u ,a_eq_ex3_v , a_eq_ex3_b :std_ulogic; + signal b_eq_ex3_x :std_ulogic_vector(0 to 5); + signal b_eq_ex3_01_b , b_eq_ex3_23_b , b_eq_ex3_45_b :std_ulogic; + signal b_eq_ex3_u ,b_eq_ex3_v , b_eq_ex3_b :std_ulogic; + signal u_eq_ex3_b :std_ulogic; + signal c_eq_ex3_x :std_ulogic_vector(0 to 5); + signal c_eq_ex3_01_b , c_eq_ex3_23_b , c_eq_ex3_45_b :std_ulogic; + signal c_eq_ex3_u ,c_eq_ex3_v , c_eq_ex3_b :std_ulogic; + signal a_eq_ex2_x :std_ulogic_vector(0 to 5); + signal a_eq_ex2_01_b , a_eq_ex2_23_b , a_eq_ex2_45_b :std_ulogic; + signal a_eq_ex2_u ,a_eq_ex2_v , a_eq_ex2_b :std_ulogic; + signal b_eq_ex2_x :std_ulogic_vector(0 to 5); + signal b_eq_ex2_01_b , b_eq_ex2_23_b , b_eq_ex2_45_b :std_ulogic; + signal b_eq_ex2_u ,b_eq_ex2_v , b_eq_ex2_b :std_ulogic; + signal u_eq_ex2_b :std_ulogic; + signal c_eq_ex2_x :std_ulogic_vector(0 to 5); + signal c_eq_ex2_01_b , c_eq_ex2_23_b , c_eq_ex2_45_b :std_ulogic; + signal c_eq_ex2_u ,c_eq_ex2_v , c_eq_ex2_b :std_ulogic; + signal a_eq_ex1_x :std_ulogic_vector(0 to 5); + signal a_eq_ex1_01_b , a_eq_ex1_23_b , a_eq_ex1_45_b :std_ulogic; + signal a_eq_ex1_u ,a_eq_ex1_v , a_eq_ex1_b :std_ulogic; + signal b_eq_ex1_x :std_ulogic_vector(0 to 5); + signal b_eq_ex1_01_b , b_eq_ex1_23_b , b_eq_ex1_45_b :std_ulogic; + signal b_eq_ex1_u ,b_eq_ex1_v , b_eq_ex1_b :std_ulogic; + signal u_eq_ex1_b :std_ulogic; + signal c_eq_ex1_x :std_ulogic_vector(0 to 5); + signal c_eq_ex1_01_b , c_eq_ex1_23_b , c_eq_ex1_45_b :std_ulogic; + signal c_eq_ex1_u ,c_eq_ex1_v , c_eq_ex1_b :std_ulogic; + signal a_eq_rf1_x :std_ulogic_vector(0 to 5); + signal a_eq_rf1_01_b , a_eq_rf1_23_b , a_eq_rf1_45_b :std_ulogic; + signal a_eq_rf1_u ,a_eq_rf1_v , a_eq_rf1_b :std_ulogic; + signal b_eq_rf1_x :std_ulogic_vector(0 to 5); + signal b_eq_rf1_01_b , b_eq_rf1_23_b , b_eq_rf1_45_b :std_ulogic; + signal b_eq_rf1_u ,b_eq_rf1_v , b_eq_rf1_b :std_ulogic; + signal u_eq_rf1_b :std_ulogic ; + signal c_eq_rf1_x :std_ulogic_vector(0 to 5); + signal c_eq_rf1_01_b , c_eq_rf1_23_b , c_eq_rf1_45_b :std_ulogic; + signal c_eq_rf1_u ,c_eq_rf1_v , c_eq_rf1_b :std_ulogic; + + signal a_eq_rf0_x :std_ulogic_vector(0 to 5); + signal a_eq_rf0_01_b , a_eq_rf0_23_b , a_eq_rf0_45_b :std_ulogic; + signal a_eq_rf0_u ,a_eq_rf0_v , a_eq_rf0_b :std_ulogic; + signal b_eq_rf0_x :std_ulogic_vector(0 to 5); + signal b_eq_rf0_01_b , b_eq_rf0_23_b , b_eq_rf0_45_b :std_ulogic; + signal b_eq_rf0_u ,b_eq_rf0_v , b_eq_rf0_b :std_ulogic; + signal u_eq_rf0_b :std_ulogic; + signal c_eq_rf0_x :std_ulogic_vector(0 to 5); + signal c_eq_rf0_01_b , c_eq_rf0_23_b , c_eq_rf0_45_b :std_ulogic; + signal c_eq_rf0_u ,c_eq_rf0_v , c_eq_rf0_b :std_ulogic; + signal a_eq_is2_x :std_ulogic_vector(0 to 5); + signal a_eq_is2_01_b , a_eq_is2_23_b , a_eq_is2_45_b :std_ulogic; + signal a_eq_is2_u ,a_eq_is2_v , a_eq_is2_b :std_ulogic; + signal b_eq_is2_x :std_ulogic_vector(0 to 5); + signal b_eq_is2_01_b , b_eq_is2_23_b , b_eq_is2_45_b :std_ulogic; + signal b_eq_is2_u ,b_eq_is2_v , b_eq_is2_b :std_ulogic; + signal u_eq_is2_b :std_ulogic; + signal c_eq_is2_x :std_ulogic_vector(0 to 5); + signal c_eq_is2_01_b , c_eq_is2_23_b , c_eq_is2_45_b :std_ulogic; + signal c_eq_is2_u ,c_eq_is2_v , c_eq_is2_b :std_ulogic; + + signal a_or_1_1 , a_or_1_2 , a_or_1_3 , a_or_1_4 :std_ulogic; + signal a_or_1_5 , a_or_1_6 , a_or_1_7 , a_or_1_8 :std_ulogic; + signal a_or_2_1_b , a_or_2_2_b , a_or_2_3_b , a_or_2_4_b :std_ulogic; + signal a_or_3_1 , a_or_3_2 , a_or_4_b :std_ulogic; + signal b_or_1_1 , b_or_1_2 , b_or_1_3 , b_or_1_4 :std_ulogic; + signal b_or_1_5 , b_or_1_6 , b_or_1_7 , b_or_1_8 :std_ulogic; + signal b_or_2_1_b , b_or_2_2_b , b_or_2_3_b , b_or_2_4_b :std_ulogic; + signal b_or_3_1 , b_or_3_2 , b_or_4_b :std_ulogic; + signal c_or_1_1 , c_or_1_2 , c_or_1_3 , c_or_1_4 :std_ulogic; + signal c_or_1_5 , c_or_1_6 , c_or_1_7 , c_or_1_8 :std_ulogic; + signal c_or_2_1_b , c_or_2_2_b , c_or_2_3_b , c_or_2_4_b :std_ulogic; + signal c_or_3_1 , c_or_3_2 , c_or_4_b :std_ulogic; + + signal t_or_1_1 , t_or_1_2 , t_or_1_3 , t_or_1_4 :std_ulogic; + signal t_or_2_1_b , t_or_2_2_b :std_ulogic; + signal t_or_3_1 , t_or_4_b :std_ulogic; + signal u_or_1_5 , u_or_1_6 , u_or_1_7 , u_or_1_8 :std_ulogic; + signal u_or_2_3_b , u_or_2_4_b , u_or_3_1 , u_or_4_b :std_ulogic; + + signal a_group_en :std_ulogic; + signal c_group_en :std_ulogic; + signal b_group_en :std_ulogic; + signal u_group_en :std_ulogic; + signal t_group_en :std_ulogic; + + signal lm0_a_cmp_en , lm0_b_cmp_en , lm0_c_cmp_en , lm0_t_cmp_en :std_ulogic; + signal lm1_a_cmp_en , lm1_b_cmp_en , lm1_c_cmp_en , lm1_t_cmp_en :std_ulogic; + signal lm2_a_cmp_en , lm2_b_cmp_en , lm2_c_cmp_en , lm2_t_cmp_en :std_ulogic; + signal lm3_a_cmp_en , lm3_b_cmp_en , lm3_c_cmp_en , lm3_t_cmp_en :std_ulogic; + signal lm4_a_cmp_en , lm4_b_cmp_en , lm4_c_cmp_en , lm4_t_cmp_en :std_ulogic; + signal lm5_a_cmp_en , lm5_b_cmp_en , lm5_c_cmp_en , lm5_t_cmp_en :std_ulogic; + signal lm6_a_cmp_en , lm6_b_cmp_en , lm6_c_cmp_en , lm6_t_cmp_en :std_ulogic; + signal lm7_a_cmp_en , lm7_b_cmp_en , lm7_c_cmp_en , lm7_t_cmp_en :std_ulogic; + signal lmc_ex4_a_cmp_en , lmc_ex4_b_cmp_en , lmc_ex4_c_cmp_en :std_ulogic; + signal is2_a_cmp_en , is2_b_cmp_en , is2_c_cmp_en , is2_u_cmp_en :std_ulogic; + signal rf0_a_cmp_en , rf0_b_cmp_en , rf0_c_cmp_en , rf0_u_cmp_en :std_ulogic; + signal rf1_a_cmp_en , rf1_b_cmp_en , rf1_c_cmp_en , rf1_u_cmp_en :std_ulogic; + signal ex1_a_cmp_en , ex1_b_cmp_en , ex1_c_cmp_en , ex1_u_cmp_en :std_ulogic; + signal ex2_a_cmp_en , ex2_b_cmp_en , ex2_c_cmp_en , ex2_u_cmp_en :std_ulogic; + signal ex3_a_cmp_en , ex3_b_cmp_en , ex3_c_cmp_en , ex3_u_cmp_en :std_ulogic; + signal ex4_a_cmp_en , ex4_b_cmp_en , ex4_c_cmp_en , ex4_u_cmp_en :std_ulogic; + +signal lm0_valid : std_ulogic; +signal lm1_valid : std_ulogic; +signal lm2_valid : std_ulogic; +signal lm3_valid : std_ulogic; +signal lm4_valid : std_ulogic; +signal lm5_valid : std_ulogic; +signal lm6_valid : std_ulogic; +signal lm7_valid : std_ulogic; + + + + + + + + + + + + + + + + + + + + + + + + +begin + + +----------------------------------------------------------------------- +-- RAW + +-- target address buffering + ucmp_lm0tabufb: lm0_ta_buf_b(0 to 5) <= not lm0_ta(0 to 5); + ucmp_lm1tabufb: lm1_ta_buf_b(0 to 5) <= not lm1_ta(0 to 5); + ucmp_lm2tabufb: lm2_ta_buf_b(0 to 5) <= not lm2_ta(0 to 5); + ucmp_lm3tabufb: lm3_ta_buf_b(0 to 5) <= not lm3_ta(0 to 5); + ucmp_lm4tabufb: lm4_ta_buf_b(0 to 5) <= not lm4_ta(0 to 5); + ucmp_lm5tabufb: lm5_ta_buf_b(0 to 5) <= not lm5_ta(0 to 5); + ucmp_lm6tabufb: lm6_ta_buf_b(0 to 5) <= not lm6_ta(0 to 5); + ucmp_lm7tabufb: lm7_ta_buf_b(0 to 5) <= not lm7_ta(0 to 5); + ucmp_lmxtabufb: lmc_ex4_buf_b(0 to 5) <= not lmc_ex4(0 to 5); + ucmp_ex4tabufb: ex4_ta_buf_b(0 to 5) <= not ex4_ta(0 to 5); + ucmp_ex3tabufb: ex3_ta_buf_b(0 to 5) <= not ex3_ta(0 to 5); + ucmp_ex2tabufb: ex2_ta_buf_b(0 to 5) <= not ex2_ta(0 to 5); + ucmp_ex1tabufb: ex1_ta_buf_b(0 to 5) <= not ex1_ta(0 to 5); + ucmp_rf1tabufb: rf1_ta_buf_b(0 to 5) <= not rf1_ta(0 to 5); + ucmp_rf0tabufb: rf0_ta_buf_b(0 to 5) <= not rf0_ta(0 to 5); + ucmp_is2tabufb: is2_ta_buf_b(0 to 5) <= not is2_ta(0 to 5); + + ucmp_lm0tabuf: lm0_ta_buf(0 to 5) <= not lm0_ta_buf_b (0 to 5); + ucmp_lm1tabuf: lm1_ta_buf(0 to 5) <= not lm1_ta_buf_b (0 to 5); + ucmp_lm2tabuf: lm2_ta_buf(0 to 5) <= not lm2_ta_buf_b (0 to 5); + ucmp_lm3tabuf: lm3_ta_buf(0 to 5) <= not lm3_ta_buf_b (0 to 5); + ucmp_lm4tabuf: lm4_ta_buf(0 to 5) <= not lm4_ta_buf_b (0 to 5); + ucmp_lm5tabuf: lm5_ta_buf(0 to 5) <= not lm5_ta_buf_b (0 to 5); + ucmp_lm6tabuf: lm6_ta_buf(0 to 5) <= not lm6_ta_buf_b (0 to 5); + ucmp_lm7tabuf: lm7_ta_buf(0 to 5) <= not lm7_ta_buf_b (0 to 5); + ucmp_lmxtabuf: lmc_ex4_buf(0 to 5) <= not lmc_ex4_buf_b (0 to 5); + ucmp_ex4tabuf: ex4_ta_buf(0 to 5) <= not ex4_ta_buf_b (0 to 5); + ucmp_ex3tabuf: ex3_ta_buf(0 to 5) <= not ex3_ta_buf_b (0 to 5); + ucmp_ex2tabuf: ex2_ta_buf(0 to 5) <= not ex2_ta_buf_b (0 to 5); + ucmp_ex1tabuf: ex1_ta_buf(0 to 5) <= not ex1_ta_buf_b (0 to 5); + ucmp_rf1tabuf: rf1_ta_buf(0 to 5) <= not rf1_ta_buf_b (0 to 5); + ucmp_rf0tabuf: rf0_ta_buf(0 to 5) <= not rf0_ta_buf_b (0 to 5); + ucmp_is2tabuf: is2_ta_buf(0 to 5) <= not is2_ta_buf_b (0 to 5); + + -- buffer is1 source addresses + ucmp_is1frabufb1: is1_fra_buf1_b(0 to 5) <= not is1_fra(0 to 5); + ucmp_is1frbbufb1: is1_frb_buf1_b(0 to 5) <= not is1_frb(0 to 5); + ucmp_is1frcbufb1: is1_frc_buf1_b(0 to 5) <= not is1_frc(0 to 5); + ucmp_is1frtbufb1: is1_frt_buf1_b(0 to 5) <= not is1_ta(0 to 5); + + ucmp_is1frabufb2: is1_fra_buf2_b(0 to 5) <= not is1_fra(0 to 5); + ucmp_is1frbbufb2: is1_frb_buf2_b(0 to 5) <= not is1_frb(0 to 5); + ucmp_is1frcbufb2: is1_frc_buf2_b(0 to 5) <= not is1_frc(0 to 5); + ucmp_is1frtbufb2: is1_frt_buf2_b(0 to 5) <= not is1_ta(0 to 5); + + ucmp_is1frabuf1: is1_fra_buf1(0 to 5) <= not is1_fra_buf1_b(0 to 5); + ucmp_is1frbbuf1: is1_frb_buf1(0 to 5) <= not is1_frb_buf1_b(0 to 5); + ucmp_is1frcbuf1: is1_frc_buf1(0 to 5) <= not is1_frc_buf1_b(0 to 5); + ucmp_is1frtbuf1: is1_frt_buf1(0 to 5) <= not is1_frt_buf1_b(0 to 5); + + ucmp_is1frabuf2: is1_fra_buf2(0 to 5) <= not is1_fra_buf1_b(0 to 5); + ucmp_is1frbbuf2: is1_frb_buf2(0 to 5) <= not is1_frb_buf1_b(0 to 5); + ucmp_is1frcbuf2: is1_frc_buf2(0 to 5) <= not is1_frc_buf1_b(0 to 5); + ucmp_is1frtbuf2: is1_frt_buf2(0 to 5) <= not is1_frt_buf1_b(0 to 5); + + ucmp_is1frabuf3: is1_fra_buf3(0 to 5) <= not is1_fra_buf1_b(0 to 5); + ucmp_is1frbbuf3: is1_frb_buf3(0 to 5) <= not is1_frb_buf1_b(0 to 5); + ucmp_is1frcbuf3: is1_frc_buf3(0 to 5) <= not is1_frc_buf1_b(0 to 5); + ucmp_is1frtbuf3: is1_frt_buf3(0 to 5) <= not is1_frt_buf1_b(0 to 5); + + + ucmp_is1frabuf4: is1_fra_buf4(0 to 5) <= not is1_fra_buf2_b(0 to 5); + ucmp_is1frbbuf4: is1_frb_buf4(0 to 5) <= not is1_frb_buf2_b(0 to 5); + ucmp_is1frcbuf4: is1_frc_buf4(0 to 5) <= not is1_frc_buf2_b(0 to 5); + ucmp_is1frtbuf4: is1_frt_buf4(0 to 5) <= not is1_frt_buf2_b(0 to 5); + + ucmp_is1frabuf5: is1_fra_buf5(0 to 5) <= not is1_fra_buf2_b(0 to 5); + ucmp_is1frbbuf5: is1_frb_buf5(0 to 5) <= not is1_frb_buf2_b(0 to 5); + ucmp_is1frcbuf5: is1_frc_buf5(0 to 5) <= not is1_frc_buf2_b(0 to 5); + ucmp_is1frtbuf5: is1_frt_buf5(0 to 5) <= not is1_frt_buf2_b(0 to 5); + + ucmp_is1frabuf6: is1_fra_buf6(0 to 5) <= not is1_fra_buf2_b(0 to 5); + ucmp_is1frbbuf6: is1_frb_buf6(0 to 5) <= not is1_frb_buf2_b(0 to 5); + ucmp_is1frcbuf6: is1_frc_buf6(0 to 5) <= not is1_frc_buf2_b(0 to 5); + ucmp_is1frtbuf6: is1_frt_buf6(0 to 5) <= not is1_frt_buf2_b(0 to 5); + + + +------------------------------------------------------------------------------------ +-- RAW fra address compares + + + + + ucmp_aeqis2_x: a_eq_is2_x(0 to 5) <= not( is2_ta_buf(0 to 5) xor is1_fra_buf1(0 to 5) ); + ucmp_aeqis2_01: a_eq_is2_01_b <= not( a_eq_is2_x(0) and a_eq_is2_x(1) ); + ucmp_aeqis2_23: a_eq_is2_23_b <= not( a_eq_is2_x(2) and a_eq_is2_x(3) ); + ucmp_aeqis2_45: a_eq_is2_45_b <= not( a_eq_is2_x(4) and a_eq_is2_x(5) ); + ucmp_aeqis2_u: a_eq_is2_u <= not( a_eq_is2_01_b or a_eq_is2_23_b ); + ucmp_aeqis2_w: a_eq_is2_v <= not( a_eq_is2_45_b ); + ucmp_aeqis2: a_eq_is2_b <= not( a_eq_is2_u and a_eq_is2_v and is2_a_cmp_en ); + + ucmp_aeqrf0_x: a_eq_rf0_x(0 to 5) <= not( rf0_ta_buf(0 to 5) xor is1_fra_buf1(0 to 5) ); + ucmp_aeqrf0_01: a_eq_rf0_01_b <= not( a_eq_rf0_x(0) and a_eq_rf0_x(1) ); + ucmp_aeqrf0_23: a_eq_rf0_23_b <= not( a_eq_rf0_x(2) and a_eq_rf0_x(3) ); + ucmp_aeqrf0_45: a_eq_rf0_45_b <= not( a_eq_rf0_x(4) and a_eq_rf0_x(5) ); + ucmp_aeqrf0_u: a_eq_rf0_u <= not( a_eq_rf0_01_b or a_eq_rf0_23_b ); + ucmp_aeqrf0_w: a_eq_rf0_v <= not( a_eq_rf0_45_b ); + ucmp_aeqrf0: a_eq_rf0_b <= not( a_eq_rf0_u and a_eq_rf0_v and rf0_a_cmp_en ); + + ucmp_aeqrf1_x: a_eq_rf1_x(0 to 5) <= not( rf1_ta_buf(0 to 5) xor is1_fra_buf1(0 to 5) ); + ucmp_aeqrf1_01: a_eq_rf1_01_b <= not( a_eq_rf1_x(0) and a_eq_rf1_x(1) ); + ucmp_aeqrf1_23: a_eq_rf1_23_b <= not( a_eq_rf1_x(2) and a_eq_rf1_x(3) ); + ucmp_aeqrf1_45: a_eq_rf1_45_b <= not( a_eq_rf1_x(4) and a_eq_rf1_x(5) ); + ucmp_aeqrf1_u: a_eq_rf1_u <= not( a_eq_rf1_01_b or a_eq_rf1_23_b ); + ucmp_aeqrf1_w: a_eq_rf1_v <= not( a_eq_rf1_45_b ); + ucmp_aeqrf1: a_eq_rf1_b <= not( a_eq_rf1_u and a_eq_rf1_v and rf1_a_cmp_en ); + + ucmp_aeqex1_x: a_eq_ex1_x(0 to 5) <= not( ex1_ta_buf(0 to 5) xor is1_fra_buf2(0 to 5) ); + ucmp_aeqex1_01: a_eq_ex1_01_b <= not( a_eq_ex1_x(0) and a_eq_ex1_x(1) ); + ucmp_aeqex1_23: a_eq_ex1_23_b <= not( a_eq_ex1_x(2) and a_eq_ex1_x(3) ); + ucmp_aeqex1_45: a_eq_ex1_45_b <= not( a_eq_ex1_x(4) and a_eq_ex1_x(5) ); + ucmp_aeqex1_u: a_eq_ex1_u <= not( a_eq_ex1_01_b or a_eq_ex1_23_b ); + ucmp_aeqex1_w: a_eq_ex1_v <= not( a_eq_ex1_45_b ); + ucmp_aeqex1: a_eq_ex1_b <= not( a_eq_ex1_u and a_eq_ex1_v and ex1_a_cmp_en ); + + ucmp_aeqex2_x: a_eq_ex2_x(0 to 5) <= not( ex2_ta_buf(0 to 5) xor is1_fra_buf2(0 to 5) ); + ucmp_aeqex2_01: a_eq_ex2_01_b <= not( a_eq_ex2_x(0) and a_eq_ex2_x(1) ); + ucmp_aeqex2_23: a_eq_ex2_23_b <= not( a_eq_ex2_x(2) and a_eq_ex2_x(3) ); + ucmp_aeqex2_45: a_eq_ex2_45_b <= not( a_eq_ex2_x(4) and a_eq_ex2_x(5) ); + ucmp_aeqex2_u: a_eq_ex2_u <= not( a_eq_ex2_01_b or a_eq_ex2_23_b ); + ucmp_aeqex2_w: a_eq_ex2_v <= not( a_eq_ex2_45_b ); + ucmp_aeqex2: a_eq_ex2_b <= not( a_eq_ex2_u and a_eq_ex2_v and ex2_a_cmp_en ); + + ucmp_aeqex3_x: a_eq_ex3_x(0 to 5) <= not( ex3_ta_buf(0 to 5) xor is1_fra_buf2(0 to 5) ); + ucmp_aeqex3_01: a_eq_ex3_01_b <= not( a_eq_ex3_x(0) and a_eq_ex3_x(1) ); + ucmp_aeqex3_23: a_eq_ex3_23_b <= not( a_eq_ex3_x(2) and a_eq_ex3_x(3) ); + ucmp_aeqex3_45: a_eq_ex3_45_b <= not( a_eq_ex3_x(4) and a_eq_ex3_x(5) ); + ucmp_aeqex3_u: a_eq_ex3_u <= not( a_eq_ex3_01_b or a_eq_ex3_23_b ); + ucmp_aeqex3_w: a_eq_ex3_v <= not( a_eq_ex3_45_b ); + ucmp_aeqex3: a_eq_ex3_b <= not( a_eq_ex3_u and a_eq_ex3_v and ex3_a_cmp_en ); + + ucmp_aeqex4_x: a_eq_ex4_x(0 to 5) <= not( ex4_ta_buf(0 to 5) xor is1_fra_buf3(0 to 5) ); + ucmp_aeqex4_01: a_eq_ex4_01_b <= not( a_eq_ex4_x(0) and a_eq_ex4_x(1) ); + ucmp_aeqex4_23: a_eq_ex4_23_b <= not( a_eq_ex4_x(2) and a_eq_ex4_x(3) ); + ucmp_aeqex4_45: a_eq_ex4_45_b <= not( a_eq_ex4_x(4) and a_eq_ex4_x(5) ); + ucmp_aeqex4_u: a_eq_ex4_u <= not( a_eq_ex4_01_b or a_eq_ex4_23_b ); + ucmp_aeqex4_w: a_eq_ex4_v <= not( a_eq_ex4_45_b ); + ucmp_aeqex4: a_eq_ex4_b <= not( a_eq_ex4_u and a_eq_ex4_v and ex4_a_cmp_en ); + + + ucmp_aeqlmx_x: a_eq_lmc_ex4_x(0 to 5) <= not( lmc_ex4_buf(0 to 5) xor is1_fra_buf3(0 to 5) ); + ucmp_aeqlmx_01: a_eq_lmc_ex4_01_b <= not( a_eq_lmc_ex4_x(0) and a_eq_lmc_ex4_x(1) ); + ucmp_aeqlmx_23: a_eq_lmc_ex4_23_b <= not( a_eq_lmc_ex4_x(2) and a_eq_lmc_ex4_x(3) ); + ucmp_aeqlmx_45: a_eq_lmc_ex4_45_b <= not( a_eq_lmc_ex4_x(4) and a_eq_lmc_ex4_x(5) ); + ucmp_aeqlmx_u: a_eq_lmc_ex4_u <= not( a_eq_lmc_ex4_01_b or a_eq_lmc_ex4_23_b ); + ucmp_aeqlmx_w: a_eq_lmc_ex4_v <= not( a_eq_lmc_ex4_45_b ); + ucmp_aeqlmx: a_eq_lmc_ex4_b <= not( a_eq_lmc_ex4_u and a_eq_lmc_ex4_v and lmc_ex4_a_cmp_en ); + + ucmp_aeqlm0_x: a_eq_lm0_x(0 to 5) <= not( lm0_ta_buf(0 to 5) xor is1_fra_buf3(0 to 5) ); + ucmp_aeqlm0_01: a_eq_lm0_01_b <= not( a_eq_lm0_x(0) and a_eq_lm0_x(1) ); + ucmp_aeqlm0_23: a_eq_lm0_23_b <= not( a_eq_lm0_x(2) and a_eq_lm0_x(3) ); + ucmp_aeqlm0_45: a_eq_lm0_45_b <= not( a_eq_lm0_x(4) and a_eq_lm0_x(5) ); + ucmp_aeqlm0_u: a_eq_lm0_u <= not( a_eq_lm0_01_b or a_eq_lm0_23_b ); + ucmp_aeqlm0_w: a_eq_lm0_v <= not( a_eq_lm0_45_b ); + ucmp_aeqlm0: a_eq_lm0_b <= not( a_eq_lm0_u and a_eq_lm0_v and lm0_a_cmp_en ); + + ucmp_aeqlm1_x: a_eq_lm1_x(0 to 5) <= not( lm1_ta_buf(0 to 5) xor is1_fra_buf4(0 to 5) ); + ucmp_aeqlm1_01: a_eq_lm1_01_b <= not( a_eq_lm1_x(0) and a_eq_lm1_x(1) ); + ucmp_aeqlm1_23: a_eq_lm1_23_b <= not( a_eq_lm1_x(2) and a_eq_lm1_x(3) ); + ucmp_aeqlm1_45: a_eq_lm1_45_b <= not( a_eq_lm1_x(4) and a_eq_lm1_x(5) ); + ucmp_aeqlm1_u: a_eq_lm1_u <= not( a_eq_lm1_01_b or a_eq_lm1_23_b ); + ucmp_aeqlm1_w: a_eq_lm1_v <= not( a_eq_lm1_45_b ); + ucmp_aeqlm1: a_eq_lm1_b <= not( a_eq_lm1_u and a_eq_lm1_v and lm1_a_cmp_en ); + + ucmp_aeqlm2_x: a_eq_lm2_x(0 to 5) <= not( lm2_ta_buf(0 to 5) xor is1_fra_buf4(0 to 5) ); + ucmp_aeqlm2_01: a_eq_lm2_01_b <= not( a_eq_lm2_x(0) and a_eq_lm2_x(1) ); + ucmp_aeqlm2_23: a_eq_lm2_23_b <= not( a_eq_lm2_x(2) and a_eq_lm2_x(3) ); + ucmp_aeqlm2_45: a_eq_lm2_45_b <= not( a_eq_lm2_x(4) and a_eq_lm2_x(5) ); + ucmp_aeqlm2_u: a_eq_lm2_u <= not( a_eq_lm2_01_b or a_eq_lm2_23_b ); + ucmp_aeqlm2_w: a_eq_lm2_v <= not( a_eq_lm2_45_b ); + ucmp_aeqlm2: a_eq_lm2_b <= not( a_eq_lm2_u and a_eq_lm2_v and lm2_a_cmp_en ); + + ucmp_aeqlm3_x: a_eq_lm3_x(0 to 5) <= not( lm3_ta_buf(0 to 5) xor is1_fra_buf4(0 to 5) ); + ucmp_aeqlm3_01: a_eq_lm3_01_b <= not( a_eq_lm3_x(0) and a_eq_lm3_x(1) ); + ucmp_aeqlm3_23: a_eq_lm3_23_b <= not( a_eq_lm3_x(2) and a_eq_lm3_x(3) ); + ucmp_aeqlm3_45: a_eq_lm3_45_b <= not( a_eq_lm3_x(4) and a_eq_lm3_x(5) ); + ucmp_aeqlm3_u: a_eq_lm3_u <= not( a_eq_lm3_01_b or a_eq_lm3_23_b ); + ucmp_aeqlm3_w: a_eq_lm3_v <= not( a_eq_lm3_45_b ); + ucmp_aeqlm3: a_eq_lm3_b <= not( a_eq_lm3_u and a_eq_lm3_v and lm3_a_cmp_en ); + + ucmp_aeqlm4_x: a_eq_lm4_x(0 to 5) <= not( lm4_ta_buf(0 to 5) xor is1_fra_buf5(0 to 5) ); + ucmp_aeqlm4_01: a_eq_lm4_01_b <= not( a_eq_lm4_x(0) and a_eq_lm4_x(1) ); + ucmp_aeqlm4_23: a_eq_lm4_23_b <= not( a_eq_lm4_x(2) and a_eq_lm4_x(3) ); + ucmp_aeqlm4_45: a_eq_lm4_45_b <= not( a_eq_lm4_x(4) and a_eq_lm4_x(5) ); + ucmp_aeqlm4_u: a_eq_lm4_u <= not( a_eq_lm4_01_b or a_eq_lm4_23_b ); + ucmp_aeqlm4_w: a_eq_lm4_v <= not( a_eq_lm4_45_b ); + ucmp_aeqlm4: a_eq_lm4_b <= not( a_eq_lm4_u and a_eq_lm4_v and lm4_a_cmp_en ); + + ucmp_aeqlm5_x: a_eq_lm5_x(0 to 5) <= not( lm5_ta_buf(0 to 5) xor is1_fra_buf5(0 to 5) ); + ucmp_aeqlm5_01: a_eq_lm5_01_b <= not( a_eq_lm5_x(0) and a_eq_lm5_x(1) ); + ucmp_aeqlm5_23: a_eq_lm5_23_b <= not( a_eq_lm5_x(2) and a_eq_lm5_x(3) ); + ucmp_aeqlm5_45: a_eq_lm5_45_b <= not( a_eq_lm5_x(4) and a_eq_lm5_x(5) ); + ucmp_aeqlm5_u: a_eq_lm5_u <= not( a_eq_lm5_01_b or a_eq_lm5_23_b ); + ucmp_aeqlm5_w: a_eq_lm5_v <= not( a_eq_lm5_45_b ); + ucmp_aeqlm5: a_eq_lm5_b <= not( a_eq_lm5_u and a_eq_lm5_v and lm5_a_cmp_en ); + + ucmp_aeqlm6_x: a_eq_lm6_x(0 to 5) <= not( lm6_ta_buf(0 to 5) xor is1_fra_buf6(0 to 5) ); + ucmp_aeqlm6_01: a_eq_lm6_01_b <= not( a_eq_lm6_x(0) and a_eq_lm6_x(1) ); + ucmp_aeqlm6_23: a_eq_lm6_23_b <= not( a_eq_lm6_x(2) and a_eq_lm6_x(3) ); + ucmp_aeqlm6_45: a_eq_lm6_45_b <= not( a_eq_lm6_x(4) and a_eq_lm6_x(5) ); + ucmp_aeqlm6_u: a_eq_lm6_u <= not( a_eq_lm6_01_b or a_eq_lm6_23_b ); + ucmp_aeqlm6_w: a_eq_lm6_v <= not( a_eq_lm6_45_b ); + ucmp_aeqlm6: a_eq_lm6_b <= not( a_eq_lm6_u and a_eq_lm6_v and lm6_a_cmp_en ); + + ucmp_aeqlm7_x: a_eq_lm7_x(0 to 5) <= not( lm7_ta_buf(0 to 5) xor is1_fra_buf6(0 to 5) ); + ucmp_aeqlm7_01: a_eq_lm7_01_b <= not( a_eq_lm7_x(0) and a_eq_lm7_x(1) ); + ucmp_aeqlm7_23: a_eq_lm7_23_b <= not( a_eq_lm7_x(2) and a_eq_lm7_x(3) ); + ucmp_aeqlm7_45: a_eq_lm7_45_b <= not( a_eq_lm7_x(4) and a_eq_lm7_x(5) ); + ucmp_aeqlm7_u: a_eq_lm7_u <= not( a_eq_lm7_01_b or a_eq_lm7_23_b ); + ucmp_aeqlm7_w: a_eq_lm7_v <= not( a_eq_lm7_45_b ); + ucmp_aeqlm7: a_eq_lm7_b <= not( a_eq_lm7_u and a_eq_lm7_v and lm7_a_cmp_en ); + + + + + + ucmp_beqis2_x: b_eq_is2_x(0 to 5) <= not( is2_ta_buf(0 to 5) xor is1_frb_buf1(0 to 5) ); + ucmp_beqis2_01: b_eq_is2_01_b <= not( b_eq_is2_x(0) and b_eq_is2_x(1) ); + ucmp_beqis2_23: b_eq_is2_23_b <= not( b_eq_is2_x(2) and b_eq_is2_x(3) ); + ucmp_beqis2_45: b_eq_is2_45_b <= not( b_eq_is2_x(4) and b_eq_is2_x(5) ); + ucmp_beqis2_u: b_eq_is2_u <= not( b_eq_is2_01_b or b_eq_is2_23_b ); + ucmp_beqis2_w: b_eq_is2_v <= not( b_eq_is2_45_b ); + ucmp_beqis2: b_eq_is2_b <= not( b_eq_is2_u and b_eq_is2_v and is2_b_cmp_en ); + ucmp_beqis2_uc: u_eq_is2_b <= not( b_eq_is2_u and b_eq_is2_v and is2_u_cmp_en ); + + ucmp_beqrf0_x: b_eq_rf0_x(0 to 5) <= not( rf0_ta_buf(0 to 5) xor is1_frb_buf1(0 to 5) ); + ucmp_beqrf0_01: b_eq_rf0_01_b <= not( b_eq_rf0_x(0) and b_eq_rf0_x(1) ); + ucmp_beqrf0_23: b_eq_rf0_23_b <= not( b_eq_rf0_x(2) and b_eq_rf0_x(3) ); + ucmp_beqrf0_45: b_eq_rf0_45_b <= not( b_eq_rf0_x(4) and b_eq_rf0_x(5) ); + ucmp_beqrf0_u: b_eq_rf0_u <= not( b_eq_rf0_01_b or b_eq_rf0_23_b ); + ucmp_beqrf0_w: b_eq_rf0_v <= not( b_eq_rf0_45_b ); + ucmp_beqrf0: b_eq_rf0_b <= not( b_eq_rf0_u and b_eq_rf0_v and rf0_b_cmp_en ); + ucmp_beqrf0_uc: u_eq_rf0_b <= not( b_eq_rf0_u and b_eq_rf0_v and rf0_u_cmp_en ); + + ucmp_beqrf1_x: b_eq_rf1_x(0 to 5) <= not( rf1_ta_buf(0 to 5) xor is1_frb_buf1(0 to 5) ); + ucmp_beqrf1_01: b_eq_rf1_01_b <= not( b_eq_rf1_x(0) and b_eq_rf1_x(1) ); + ucmp_beqrf1_23: b_eq_rf1_23_b <= not( b_eq_rf1_x(2) and b_eq_rf1_x(3) ); + ucmp_beqrf1_45: b_eq_rf1_45_b <= not( b_eq_rf1_x(4) and b_eq_rf1_x(5) ); + ucmp_beqrf1_u: b_eq_rf1_u <= not( b_eq_rf1_01_b or b_eq_rf1_23_b ); + ucmp_beqrf1_w: b_eq_rf1_v <= not( b_eq_rf1_45_b ); + ucmp_beqrf1: b_eq_rf1_b <= not( b_eq_rf1_u and b_eq_rf1_v and rf1_b_cmp_en ); + ucmp_beqrf1_uc: u_eq_rf1_b <= not( b_eq_rf1_u and b_eq_rf1_v and rf1_u_cmp_en ); + + ucmp_beqex1_x: b_eq_ex1_x(0 to 5) <= not( ex1_ta_buf(0 to 5) xor is1_frb_buf2(0 to 5) ); + ucmp_beqex1_01: b_eq_ex1_01_b <= not( b_eq_ex1_x(0) and b_eq_ex1_x(1) ); + ucmp_beqex1_23: b_eq_ex1_23_b <= not( b_eq_ex1_x(2) and b_eq_ex1_x(3) ); + ucmp_beqex1_45: b_eq_ex1_45_b <= not( b_eq_ex1_x(4) and b_eq_ex1_x(5) ); + ucmp_beqex1_u: b_eq_ex1_u <= not( b_eq_ex1_01_b or b_eq_ex1_23_b ); + ucmp_beqex1_w: b_eq_ex1_v <= not( b_eq_ex1_45_b ); + ucmp_beqex1: b_eq_ex1_b <= not( b_eq_ex1_u and b_eq_ex1_v and ex1_b_cmp_en ); + ucmp_beqex1_uc: u_eq_ex1_b <= not( b_eq_ex1_u and b_eq_ex1_v and ex1_u_cmp_en ); + + ucmp_beqex2_x: b_eq_ex2_x(0 to 5) <= not( ex2_ta_buf(0 to 5) xor is1_frb_buf2(0 to 5) ); + ucmp_beqex2_01: b_eq_ex2_01_b <= not( b_eq_ex2_x(0) and b_eq_ex2_x(1) ); + ucmp_beqex2_23: b_eq_ex2_23_b <= not( b_eq_ex2_x(2) and b_eq_ex2_x(3) ); + ucmp_beqex2_45: b_eq_ex2_45_b <= not( b_eq_ex2_x(4) and b_eq_ex2_x(5) ); + ucmp_beqex2_u: b_eq_ex2_u <= not( b_eq_ex2_01_b or b_eq_ex2_23_b ); + ucmp_beqex2_w: b_eq_ex2_v <= not( b_eq_ex2_45_b ); + ucmp_beqex2: b_eq_ex2_b <= not( b_eq_ex2_u and b_eq_ex2_v and ex2_b_cmp_en ); + ucmp_beqex2_uc: u_eq_ex2_b <= not( b_eq_ex2_u and b_eq_ex2_v and ex2_u_cmp_en ); + + ucmp_beqex3_x: b_eq_ex3_x(0 to 5) <= not( ex3_ta_buf(0 to 5) xor is1_frb_buf2(0 to 5) ); + ucmp_beqex3_01: b_eq_ex3_01_b <= not( b_eq_ex3_x(0) and b_eq_ex3_x(1) ); + ucmp_beqex3_23: b_eq_ex3_23_b <= not( b_eq_ex3_x(2) and b_eq_ex3_x(3) ); + ucmp_beqex3_45: b_eq_ex3_45_b <= not( b_eq_ex3_x(4) and b_eq_ex3_x(5) ); + ucmp_beqex3_u: b_eq_ex3_u <= not( b_eq_ex3_01_b or b_eq_ex3_23_b ); + ucmp_beqex3_w: b_eq_ex3_v <= not( b_eq_ex3_45_b ); + ucmp_beqex3: b_eq_ex3_b <= not( b_eq_ex3_u and b_eq_ex3_v and ex3_b_cmp_en ); + ucmp_beqex3_uc: u_eq_ex3_b <= not( b_eq_ex3_u and b_eq_ex3_v and ex3_u_cmp_en ); + + ucmp_beqex4_x: b_eq_ex4_x(0 to 5) <= not( ex4_ta_buf(0 to 5) xor is1_frb_buf3(0 to 5) ); + ucmp_beqex4_01: b_eq_ex4_01_b <= not( b_eq_ex4_x(0) and b_eq_ex4_x(1) ); + ucmp_beqex4_23: b_eq_ex4_23_b <= not( b_eq_ex4_x(2) and b_eq_ex4_x(3) ); + ucmp_beqex4_45: b_eq_ex4_45_b <= not( b_eq_ex4_x(4) and b_eq_ex4_x(5) ); + ucmp_beqex4_u: b_eq_ex4_u <= not( b_eq_ex4_01_b or b_eq_ex4_23_b ); + ucmp_beqex4_w: b_eq_ex4_v <= not( b_eq_ex4_45_b ); + ucmp_beqex4: b_eq_ex4_b <= not( b_eq_ex4_u and b_eq_ex4_v and ex4_b_cmp_en ); + ucmp_beqex4_uc: u_eq_ex4_b <= not( b_eq_ex4_u and b_eq_ex4_v and ex4_u_cmp_en ); + + ucmp_beqlmx_x: b_eq_lmc_ex4_x(0 to 5) <= not( lmc_ex4_buf(0 to 5) xor is1_frb_buf3(0 to 5) ); + ucmp_beqlmx_01: b_eq_lmc_ex4_01_b <= not( b_eq_lmc_ex4_x(0) and b_eq_lmc_ex4_x(1) ); + ucmp_beqlmx_23: b_eq_lmc_ex4_23_b <= not( b_eq_lmc_ex4_x(2) and b_eq_lmc_ex4_x(3) ); + ucmp_beqlmx_45: b_eq_lmc_ex4_45_b <= not( b_eq_lmc_ex4_x(4) and b_eq_lmc_ex4_x(5) ); + ucmp_beqlmx_u: b_eq_lmc_ex4_u <= not( b_eq_lmc_ex4_01_b or b_eq_lmc_ex4_23_b ); + ucmp_beqlmx_w: b_eq_lmc_ex4_v <= not( b_eq_lmc_ex4_45_b ); + ucmp_beqlmx: b_eq_lmc_ex4_b <= not( b_eq_lmc_ex4_u and b_eq_lmc_ex4_v and lmc_ex4_b_cmp_en ); + + ucmp_beqlm0_x: b_eq_lm0_x(0 to 5) <= not( lm0_ta_buf(0 to 5) xor is1_frb_buf3(0 to 5) ); + ucmp_beqlm0_01: b_eq_lm0_01_b <= not( b_eq_lm0_x(0) and b_eq_lm0_x(1) ); + ucmp_beqlm0_23: b_eq_lm0_23_b <= not( b_eq_lm0_x(2) and b_eq_lm0_x(3) ); + ucmp_beqlm0_45: b_eq_lm0_45_b <= not( b_eq_lm0_x(4) and b_eq_lm0_x(5) ); + ucmp_beqlm0_u: b_eq_lm0_u <= not( b_eq_lm0_01_b or b_eq_lm0_23_b ); + ucmp_beqlm0_w: b_eq_lm0_v <= not( b_eq_lm0_45_b ); + ucmp_beqlm0: b_eq_lm0_b <= not( b_eq_lm0_u and b_eq_lm0_v and lm0_b_cmp_en ); + + ucmp_beqlm1_x: b_eq_lm1_x(0 to 5) <= not( lm1_ta_buf(0 to 5) xor is1_frb_buf4(0 to 5) ); + ucmp_beqlm1_01: b_eq_lm1_01_b <= not( b_eq_lm1_x(0) and b_eq_lm1_x(1) ); + ucmp_beqlm1_23: b_eq_lm1_23_b <= not( b_eq_lm1_x(2) and b_eq_lm1_x(3) ); + ucmp_beqlm1_45: b_eq_lm1_45_b <= not( b_eq_lm1_x(4) and b_eq_lm1_x(5) ); + ucmp_beqlm1_u: b_eq_lm1_u <= not( b_eq_lm1_01_b or b_eq_lm1_23_b ); + ucmp_beqlm1_w: b_eq_lm1_v <= not( b_eq_lm1_45_b ); + ucmp_beqlm1: b_eq_lm1_b <= not( b_eq_lm1_u and b_eq_lm1_v and lm1_b_cmp_en ); + + ucmp_beqlm2_x: b_eq_lm2_x(0 to 5) <= not( lm2_ta_buf(0 to 5) xor is1_frb_buf4(0 to 5) ); + ucmp_beqlm2_01: b_eq_lm2_01_b <= not( b_eq_lm2_x(0) and b_eq_lm2_x(1) ); + ucmp_beqlm2_23: b_eq_lm2_23_b <= not( b_eq_lm2_x(2) and b_eq_lm2_x(3) ); + ucmp_beqlm2_45: b_eq_lm2_45_b <= not( b_eq_lm2_x(4) and b_eq_lm2_x(5) ); + ucmp_beqlm2_u: b_eq_lm2_u <= not( b_eq_lm2_01_b or b_eq_lm2_23_b ); + ucmp_beqlm2_w: b_eq_lm2_v <= not( b_eq_lm2_45_b ); + ucmp_beqlm2: b_eq_lm2_b <= not( b_eq_lm2_u and b_eq_lm2_v and lm2_b_cmp_en ); + + ucmp_beqlm3_x: b_eq_lm3_x(0 to 5) <= not( lm3_ta_buf(0 to 5) xor is1_frb_buf4(0 to 5) ); + ucmp_beqlm3_01: b_eq_lm3_01_b <= not( b_eq_lm3_x(0) and b_eq_lm3_x(1) ); + ucmp_beqlm3_23: b_eq_lm3_23_b <= not( b_eq_lm3_x(2) and b_eq_lm3_x(3) ); + ucmp_beqlm3_45: b_eq_lm3_45_b <= not( b_eq_lm3_x(4) and b_eq_lm3_x(5) ); + ucmp_beqlm3_u: b_eq_lm3_u <= not( b_eq_lm3_01_b or b_eq_lm3_23_b ); + ucmp_beqlm3_w: b_eq_lm3_v <= not( b_eq_lm3_45_b ); + ucmp_beqlm3: b_eq_lm3_b <= not( b_eq_lm3_u and b_eq_lm3_v and lm3_b_cmp_en ); + + ucmp_beqlm4_x: b_eq_lm4_x(0 to 5) <= not( lm4_ta_buf(0 to 5) xor is1_frb_buf5(0 to 5) ); + ucmp_beqlm4_01: b_eq_lm4_01_b <= not( b_eq_lm4_x(0) and b_eq_lm4_x(1) ); + ucmp_beqlm4_23: b_eq_lm4_23_b <= not( b_eq_lm4_x(2) and b_eq_lm4_x(3) ); + ucmp_beqlm4_45: b_eq_lm4_45_b <= not( b_eq_lm4_x(4) and b_eq_lm4_x(5) ); + ucmp_beqlm4_u: b_eq_lm4_u <= not( b_eq_lm4_01_b or b_eq_lm4_23_b ); + ucmp_beqlm4_w: b_eq_lm4_v <= not( b_eq_lm4_45_b ); + ucmp_beqlm4: b_eq_lm4_b <= not( b_eq_lm4_u and b_eq_lm4_v and lm4_b_cmp_en ); + + ucmp_beqlm5_x: b_eq_lm5_x(0 to 5) <= not( lm5_ta_buf(0 to 5) xor is1_frb_buf5(0 to 5) ); + ucmp_beqlm5_01: b_eq_lm5_01_b <= not( b_eq_lm5_x(0) and b_eq_lm5_x(1) ); + ucmp_beqlm5_23: b_eq_lm5_23_b <= not( b_eq_lm5_x(2) and b_eq_lm5_x(3) ); + ucmp_beqlm5_45: b_eq_lm5_45_b <= not( b_eq_lm5_x(4) and b_eq_lm5_x(5) ); + ucmp_beqlm5_u: b_eq_lm5_u <= not( b_eq_lm5_01_b or b_eq_lm5_23_b ); + ucmp_beqlm5_w: b_eq_lm5_v <= not( b_eq_lm5_45_b ); + ucmp_beqlm5: b_eq_lm5_b <= not( b_eq_lm5_u and b_eq_lm5_v and lm5_b_cmp_en ); + + ucmp_beqlm6_x: b_eq_lm6_x(0 to 5) <= not( lm6_ta_buf(0 to 5) xor is1_frb_buf6(0 to 5) ); + ucmp_beqlm6_01: b_eq_lm6_01_b <= not( b_eq_lm6_x(0) and b_eq_lm6_x(1) ); + ucmp_beqlm6_23: b_eq_lm6_23_b <= not( b_eq_lm6_x(2) and b_eq_lm6_x(3) ); + ucmp_beqlm6_45: b_eq_lm6_45_b <= not( b_eq_lm6_x(4) and b_eq_lm6_x(5) ); + ucmp_beqlm6_u: b_eq_lm6_u <= not( b_eq_lm6_01_b or b_eq_lm6_23_b ); + ucmp_beqlm6_w: b_eq_lm6_v <= not( b_eq_lm6_45_b ); + ucmp_beqlm6: b_eq_lm6_b <= not( b_eq_lm6_u and b_eq_lm6_v and lm6_b_cmp_en ); + + ucmp_beqlm7_x: b_eq_lm7_x(0 to 5) <= not( lm7_ta_buf(0 to 5) xor is1_frb_buf6(0 to 5) ); + ucmp_beqlm7_01: b_eq_lm7_01_b <= not( b_eq_lm7_x(0) and b_eq_lm7_x(1) ); + ucmp_beqlm7_23: b_eq_lm7_23_b <= not( b_eq_lm7_x(2) and b_eq_lm7_x(3) ); + ucmp_beqlm7_45: b_eq_lm7_45_b <= not( b_eq_lm7_x(4) and b_eq_lm7_x(5) ); + ucmp_beqlm7_u: b_eq_lm7_u <= not( b_eq_lm7_01_b or b_eq_lm7_23_b ); + ucmp_beqlm7_w: b_eq_lm7_v <= not( b_eq_lm7_45_b ); + ucmp_beqlm7: b_eq_lm7_b <= not( b_eq_lm7_u and b_eq_lm7_v and lm7_b_cmp_en ); + + + + + + + + + + + ucmp_ceqis2_x: c_eq_is2_x(0 to 5) <= not( is2_ta_buf(0 to 5) xor is1_frc_buf1(0 to 5) ); + ucmp_ceqis2_01: c_eq_is2_01_b <= not( c_eq_is2_x(0) and c_eq_is2_x(1) ); + ucmp_ceqis2_23: c_eq_is2_23_b <= not( c_eq_is2_x(2) and c_eq_is2_x(3) ); + ucmp_ceqis2_45: c_eq_is2_45_b <= not( c_eq_is2_x(4) and c_eq_is2_x(5) ); + ucmp_ceqis2_u: c_eq_is2_u <= not( c_eq_is2_01_b or c_eq_is2_23_b ); + ucmp_ceqis2_w: c_eq_is2_v <= not( c_eq_is2_45_b ); + ucmp_ceqis2: c_eq_is2_b <= not( c_eq_is2_u and c_eq_is2_v and is2_c_cmp_en ); + + ucmp_ceqrf0_x: c_eq_rf0_x(0 to 5) <= not( rf0_ta_buf(0 to 5) xor is1_frc_buf1(0 to 5) ); + ucmp_ceqrf0_01: c_eq_rf0_01_b <= not( c_eq_rf0_x(0) and c_eq_rf0_x(1) ); + ucmp_ceqrf0_23: c_eq_rf0_23_b <= not( c_eq_rf0_x(2) and c_eq_rf0_x(3) ); + ucmp_ceqrf0_45: c_eq_rf0_45_b <= not( c_eq_rf0_x(4) and c_eq_rf0_x(5) ); + ucmp_ceqrf0_u: c_eq_rf0_u <= not( c_eq_rf0_01_b or c_eq_rf0_23_b ); + ucmp_ceqrf0_w: c_eq_rf0_v <= not( c_eq_rf0_45_b ); + ucmp_ceqrf0: c_eq_rf0_b <= not( c_eq_rf0_u and c_eq_rf0_v and rf0_c_cmp_en ); + + ucmp_ceqrf1_x: c_eq_rf1_x(0 to 5) <= not( rf1_ta_buf(0 to 5) xor is1_frc_buf1(0 to 5) ); + ucmp_ceqrf1_01: c_eq_rf1_01_b <= not( c_eq_rf1_x(0) and c_eq_rf1_x(1) ); + ucmp_ceqrf1_23: c_eq_rf1_23_b <= not( c_eq_rf1_x(2) and c_eq_rf1_x(3) ); + ucmp_ceqrf1_45: c_eq_rf1_45_b <= not( c_eq_rf1_x(4) and c_eq_rf1_x(5) ); + ucmp_ceqrf1_u: c_eq_rf1_u <= not( c_eq_rf1_01_b or c_eq_rf1_23_b ); + ucmp_ceqrf1_w: c_eq_rf1_v <= not( c_eq_rf1_45_b ); + ucmp_ceqrf1: c_eq_rf1_b <= not( c_eq_rf1_u and c_eq_rf1_v and rf1_c_cmp_en ); + + ucmp_ceqex1_x: c_eq_ex1_x(0 to 5) <= not( ex1_ta_buf(0 to 5) xor is1_frc_buf2(0 to 5) ); + ucmp_ceqex1_01: c_eq_ex1_01_b <= not( c_eq_ex1_x(0) and c_eq_ex1_x(1) ); + ucmp_ceqex1_23: c_eq_ex1_23_b <= not( c_eq_ex1_x(2) and c_eq_ex1_x(3) ); + ucmp_ceqex1_45: c_eq_ex1_45_b <= not( c_eq_ex1_x(4) and c_eq_ex1_x(5) ); + ucmp_ceqex1_u: c_eq_ex1_u <= not( c_eq_ex1_01_b or c_eq_ex1_23_b ); + ucmp_ceqex1_w: c_eq_ex1_v <= not( c_eq_ex1_45_b ); + ucmp_ceqex1: c_eq_ex1_b <= not( c_eq_ex1_u and c_eq_ex1_v and ex1_c_cmp_en ); + + ucmp_ceqex2_x: c_eq_ex2_x(0 to 5) <= not( ex2_ta_buf(0 to 5) xor is1_frc_buf2(0 to 5) ); + ucmp_ceqex2_01: c_eq_ex2_01_b <= not( c_eq_ex2_x(0) and c_eq_ex2_x(1) ); + ucmp_ceqex2_23: c_eq_ex2_23_b <= not( c_eq_ex2_x(2) and c_eq_ex2_x(3) ); + ucmp_ceqex2_45: c_eq_ex2_45_b <= not( c_eq_ex2_x(4) and c_eq_ex2_x(5) ); + ucmp_ceqex2_u: c_eq_ex2_u <= not( c_eq_ex2_01_b or c_eq_ex2_23_b ); + ucmp_ceqex2_w: c_eq_ex2_v <= not( c_eq_ex2_45_b ); + ucmp_ceqex2: c_eq_ex2_b <= not( c_eq_ex2_u and c_eq_ex2_v and ex2_c_cmp_en ); + + ucmp_ceqex3_x: c_eq_ex3_x(0 to 5) <= not( ex3_ta_buf(0 to 5) xor is1_frc_buf2(0 to 5) ); + ucmp_ceqex3_01: c_eq_ex3_01_b <= not( c_eq_ex3_x(0) and c_eq_ex3_x(1) ); + ucmp_ceqex3_23: c_eq_ex3_23_b <= not( c_eq_ex3_x(2) and c_eq_ex3_x(3) ); + ucmp_ceqex3_45: c_eq_ex3_45_b <= not( c_eq_ex3_x(4) and c_eq_ex3_x(5) ); + ucmp_ceqex3_u: c_eq_ex3_u <= not( c_eq_ex3_01_b or c_eq_ex3_23_b ); + ucmp_ceqex3_w: c_eq_ex3_v <= not( c_eq_ex3_45_b ); + ucmp_ceqex3: c_eq_ex3_b <= not( c_eq_ex3_u and c_eq_ex3_v and ex3_c_cmp_en ); + + ucmp_ceqex4_x: c_eq_ex4_x(0 to 5) <= not( ex4_ta_buf(0 to 5) xor is1_frc_buf3(0 to 5) ); + ucmp_ceqex4_01: c_eq_ex4_01_b <= not( c_eq_ex4_x(0) and c_eq_ex4_x(1) ); + ucmp_ceqex4_23: c_eq_ex4_23_b <= not( c_eq_ex4_x(2) and c_eq_ex4_x(3) ); + ucmp_ceqex4_45: c_eq_ex4_45_b <= not( c_eq_ex4_x(4) and c_eq_ex4_x(5) ); + ucmp_ceqex4_u: c_eq_ex4_u <= not( c_eq_ex4_01_b or c_eq_ex4_23_b ); + ucmp_ceqex4_w: c_eq_ex4_v <= not( c_eq_ex4_45_b ); + ucmp_ceqex4: c_eq_ex4_b <= not( c_eq_ex4_u and c_eq_ex4_v and ex4_c_cmp_en ); + + ucmp_ceqlmx_x: c_eq_lmc_ex4_x(0 to 5) <= not( lmc_ex4_buf(0 to 5) xor is1_frc_buf3(0 to 5) ); + ucmp_ceqlmx_01: c_eq_lmc_ex4_01_b <= not( c_eq_lmc_ex4_x(0) and c_eq_lmc_ex4_x(1) ); + ucmp_ceqlmx_23: c_eq_lmc_ex4_23_b <= not( c_eq_lmc_ex4_x(2) and c_eq_lmc_ex4_x(3) ); + ucmp_ceqlmx_45: c_eq_lmc_ex4_45_b <= not( c_eq_lmc_ex4_x(4) and c_eq_lmc_ex4_x(5) ); + ucmp_ceqlmx_u: c_eq_lmc_ex4_u <= not( c_eq_lmc_ex4_01_b or c_eq_lmc_ex4_23_b ); + ucmp_ceqlmx_w: c_eq_lmc_ex4_v <= not( c_eq_lmc_ex4_45_b ); + ucmp_ceqlmx: c_eq_lmc_ex4_b <= not( c_eq_lmc_ex4_u and c_eq_lmc_ex4_v and lmc_ex4_c_cmp_en ); + + ucmp_ceqlm0_x: c_eq_lm0_x(0 to 5) <= not( lm0_ta_buf(0 to 5) xor is1_frc_buf3(0 to 5) ); + ucmp_ceqlm0_01: c_eq_lm0_01_b <= not( c_eq_lm0_x(0) and c_eq_lm0_x(1) ); + ucmp_ceqlm0_23: c_eq_lm0_23_b <= not( c_eq_lm0_x(2) and c_eq_lm0_x(3) ); + ucmp_ceqlm0_45: c_eq_lm0_45_b <= not( c_eq_lm0_x(4) and c_eq_lm0_x(5) ); + ucmp_ceqlm0_u: c_eq_lm0_u <= not( c_eq_lm0_01_b or c_eq_lm0_23_b ); + ucmp_ceqlm0_w: c_eq_lm0_v <= not( c_eq_lm0_45_b ); + ucmp_ceqlm0: c_eq_lm0_b <= not( c_eq_lm0_u and c_eq_lm0_v and lm0_c_cmp_en ); + + + ucmp_ceqlm1_x: c_eq_lm1_x(0 to 5) <= not( lm1_ta_buf(0 to 5) xor is1_frc_buf4(0 to 5) ); + ucmp_ceqlm1_01: c_eq_lm1_01_b <= not( c_eq_lm1_x(0) and c_eq_lm1_x(1) ); + ucmp_ceqlm1_23: c_eq_lm1_23_b <= not( c_eq_lm1_x(2) and c_eq_lm1_x(3) ); + ucmp_ceqlm1_45: c_eq_lm1_45_b <= not( c_eq_lm1_x(4) and c_eq_lm1_x(5) ); + ucmp_ceqlm1_u: c_eq_lm1_u <= not( c_eq_lm1_01_b or c_eq_lm1_23_b ); + ucmp_ceqlm1_w: c_eq_lm1_v <= not( c_eq_lm1_45_b ); + ucmp_ceqlm1: c_eq_lm1_b <= not( c_eq_lm1_u and c_eq_lm1_v and lm1_c_cmp_en ); + + ucmp_ceqlm2_x: c_eq_lm2_x(0 to 5) <= not( lm2_ta_buf(0 to 5) xor is1_frc_buf4(0 to 5) ); + ucmp_ceqlm2_01: c_eq_lm2_01_b <= not( c_eq_lm2_x(0) and c_eq_lm2_x(1) ); + ucmp_ceqlm2_23: c_eq_lm2_23_b <= not( c_eq_lm2_x(2) and c_eq_lm2_x(3) ); + ucmp_ceqlm2_45: c_eq_lm2_45_b <= not( c_eq_lm2_x(4) and c_eq_lm2_x(5) ); + ucmp_ceqlm2_u: c_eq_lm2_u <= not( c_eq_lm2_01_b or c_eq_lm2_23_b ); + ucmp_ceqlm2_w: c_eq_lm2_v <= not( c_eq_lm2_45_b ); + ucmp_ceqlm2: c_eq_lm2_b <= not( c_eq_lm2_u and c_eq_lm2_v and lm2_c_cmp_en ); + + ucmp_ceqlm3_x: c_eq_lm3_x(0 to 5) <= not( lm3_ta_buf(0 to 5) xor is1_frc_buf4(0 to 5) ); + ucmp_ceqlm3_01: c_eq_lm3_01_b <= not( c_eq_lm3_x(0) and c_eq_lm3_x(1) ); + ucmp_ceqlm3_23: c_eq_lm3_23_b <= not( c_eq_lm3_x(2) and c_eq_lm3_x(3) ); + ucmp_ceqlm3_45: c_eq_lm3_45_b <= not( c_eq_lm3_x(4) and c_eq_lm3_x(5) ); + ucmp_ceqlm3_u: c_eq_lm3_u <= not( c_eq_lm3_01_b or c_eq_lm3_23_b ); + ucmp_ceqlm3_w: c_eq_lm3_v <= not( c_eq_lm3_45_b ); + ucmp_ceqlm3: c_eq_lm3_b <= not( c_eq_lm3_u and c_eq_lm3_v and lm3_c_cmp_en ); + + ucmp_ceqlm4_x: c_eq_lm4_x(0 to 5) <= not( lm4_ta_buf(0 to 5) xor is1_frc_buf5(0 to 5) ); + ucmp_ceqlm4_01: c_eq_lm4_01_b <= not( c_eq_lm4_x(0) and c_eq_lm4_x(1) ); + ucmp_ceqlm4_23: c_eq_lm4_23_b <= not( c_eq_lm4_x(2) and c_eq_lm4_x(3) ); + ucmp_ceqlm4_45: c_eq_lm4_45_b <= not( c_eq_lm4_x(4) and c_eq_lm4_x(5) ); + ucmp_ceqlm4_u: c_eq_lm4_u <= not( c_eq_lm4_01_b or c_eq_lm4_23_b ); + ucmp_ceqlm4_w: c_eq_lm4_v <= not( c_eq_lm4_45_b ); + ucmp_ceqlm4: c_eq_lm4_b <= not( c_eq_lm4_u and c_eq_lm4_v and lm4_c_cmp_en ); + + ucmp_ceqlm5_x: c_eq_lm5_x(0 to 5) <= not( lm5_ta_buf(0 to 5) xor is1_frc_buf5(0 to 5) ); + ucmp_ceqlm5_01: c_eq_lm5_01_b <= not( c_eq_lm5_x(0) and c_eq_lm5_x(1) ); + ucmp_ceqlm5_23: c_eq_lm5_23_b <= not( c_eq_lm5_x(2) and c_eq_lm5_x(3) ); + ucmp_ceqlm5_45: c_eq_lm5_45_b <= not( c_eq_lm5_x(4) and c_eq_lm5_x(5) ); + ucmp_ceqlm5_u: c_eq_lm5_u <= not( c_eq_lm5_01_b or c_eq_lm5_23_b ); + ucmp_ceqlm5_w: c_eq_lm5_v <= not( c_eq_lm5_45_b ); + ucmp_ceqlm5: c_eq_lm5_b <= not( c_eq_lm5_u and c_eq_lm5_v and lm5_c_cmp_en ); + + ucmp_ceqlm6_x: c_eq_lm6_x(0 to 5) <= not( lm6_ta_buf(0 to 5) xor is1_frc_buf6(0 to 5) ); + ucmp_ceqlm6_01: c_eq_lm6_01_b <= not( c_eq_lm6_x(0) and c_eq_lm6_x(1) ); + ucmp_ceqlm6_23: c_eq_lm6_23_b <= not( c_eq_lm6_x(2) and c_eq_lm6_x(3) ); + ucmp_ceqlm6_45: c_eq_lm6_45_b <= not( c_eq_lm6_x(4) and c_eq_lm6_x(5) ); + ucmp_ceqlm6_u: c_eq_lm6_u <= not( c_eq_lm6_01_b or c_eq_lm6_23_b ); + ucmp_ceqlm6_w: c_eq_lm6_v <= not( c_eq_lm6_45_b ); + ucmp_ceqlm6: c_eq_lm6_b <= not( c_eq_lm6_u and c_eq_lm6_v and lm6_c_cmp_en ); + + ucmp_ceqlm7_x: c_eq_lm7_x(0 to 5) <= not( lm7_ta_buf(0 to 5) xor is1_frc_buf6(0 to 5) ); + ucmp_ceqlm7_01: c_eq_lm7_01_b <= not( c_eq_lm7_x(0) and c_eq_lm7_x(1) ); + ucmp_ceqlm7_23: c_eq_lm7_23_b <= not( c_eq_lm7_x(2) and c_eq_lm7_x(3) ); + ucmp_ceqlm7_45: c_eq_lm7_45_b <= not( c_eq_lm7_x(4) and c_eq_lm7_x(5) ); + ucmp_ceqlm7_u: c_eq_lm7_u <= not( c_eq_lm7_01_b or c_eq_lm7_23_b ); + ucmp_ceqlm7_w: c_eq_lm7_v <= not( c_eq_lm7_45_b ); + ucmp_ceqlm7: c_eq_lm7_b <= not( c_eq_lm7_u and c_eq_lm7_v and lm7_c_cmp_en ); + + + +------------------------------------------------------------------------------------------------------- + + + ucmp_teqlm0_x: t_eq_lm0_x(0 to 5) <= not( lm0_ta_buf(0 to 5) xor is1_frt_buf1(0 to 5) ); + ucmp_teqlm0_01: t_eq_lm0_01_b <= not( t_eq_lm0_x(0) and t_eq_lm0_x(1) ); + ucmp_teqlm0_23: t_eq_lm0_23_b <= not( t_eq_lm0_x(2) and t_eq_lm0_x(3) ); + ucmp_teqlm0_45: t_eq_lm0_45_b <= not( t_eq_lm0_x(4) and t_eq_lm0_x(5) ); + ucmp_teqlm0_u: t_eq_lm0_u <= not( t_eq_lm0_01_b or t_eq_lm0_23_b ); + ucmp_teqlm0_w: t_eq_lm0_v <= not( t_eq_lm0_45_b ); + ucmp_teqlm0: t_eq_lm0_b <= not( t_eq_lm0_u and t_eq_lm0_v and lm0_t_cmp_en ); + + + ucmp_teqlm1_x: t_eq_lm1_x(0 to 5) <= not( lm1_ta_buf(0 to 5) xor is1_frt_buf1(0 to 5) ); + ucmp_teqlm1_01: t_eq_lm1_01_b <= not( t_eq_lm1_x(0) and t_eq_lm1_x(1) ); + ucmp_teqlm1_23: t_eq_lm1_23_b <= not( t_eq_lm1_x(2) and t_eq_lm1_x(3) ); + ucmp_teqlm1_45: t_eq_lm1_45_b <= not( t_eq_lm1_x(4) and t_eq_lm1_x(5) ); + ucmp_teqlm1_u: t_eq_lm1_u <= not( t_eq_lm1_01_b or t_eq_lm1_23_b ); + ucmp_teqlm1_w: t_eq_lm1_v <= not( t_eq_lm1_45_b ); + ucmp_teqlm1: t_eq_lm1_b <= not( t_eq_lm1_u and t_eq_lm1_v and lm1_t_cmp_en ); + + ucmp_teqlm2_x: t_eq_lm2_x(0 to 5) <= not( lm2_ta_buf(0 to 5) xor is1_frt_buf2(0 to 5) ); + ucmp_teqlm2_01: t_eq_lm2_01_b <= not( t_eq_lm2_x(0) and t_eq_lm2_x(1) ); + ucmp_teqlm2_23: t_eq_lm2_23_b <= not( t_eq_lm2_x(2) and t_eq_lm2_x(3) ); + ucmp_teqlm2_45: t_eq_lm2_45_b <= not( t_eq_lm2_x(4) and t_eq_lm2_x(5) ); + ucmp_teqlm2_u: t_eq_lm2_u <= not( t_eq_lm2_01_b or t_eq_lm2_23_b ); + ucmp_teqlm2_w: t_eq_lm2_v <= not( t_eq_lm2_45_b ); + ucmp_teqlm2: t_eq_lm2_b <= not( t_eq_lm2_u and t_eq_lm2_v and lm2_t_cmp_en ); + + ucmp_teqlm3_x: t_eq_lm3_x(0 to 5) <= not( lm3_ta_buf(0 to 5) xor is1_frt_buf3(0 to 5) ); + ucmp_teqlm3_01: t_eq_lm3_01_b <= not( t_eq_lm3_x(0) and t_eq_lm3_x(1) ); + ucmp_teqlm3_23: t_eq_lm3_23_b <= not( t_eq_lm3_x(2) and t_eq_lm3_x(3) ); + ucmp_teqlm3_45: t_eq_lm3_45_b <= not( t_eq_lm3_x(4) and t_eq_lm3_x(5) ); + ucmp_teqlm3_u: t_eq_lm3_u <= not( t_eq_lm3_01_b or t_eq_lm3_23_b ); + ucmp_teqlm3_w: t_eq_lm3_v <= not( t_eq_lm3_45_b ); + ucmp_teqlm3: t_eq_lm3_b <= not( t_eq_lm3_u and t_eq_lm3_v and lm3_t_cmp_en ); + + ucmp_teqlm4_x: t_eq_lm4_x(0 to 5) <= not( lm4_ta_buf(0 to 5) xor is1_frt_buf4(0 to 5) ); + ucmp_teqlm4_01: t_eq_lm4_01_b <= not( t_eq_lm4_x(0) and t_eq_lm4_x(1) ); + ucmp_teqlm4_23: t_eq_lm4_23_b <= not( t_eq_lm4_x(2) and t_eq_lm4_x(3) ); + ucmp_teqlm4_45: t_eq_lm4_45_b <= not( t_eq_lm4_x(4) and t_eq_lm4_x(5) ); + ucmp_teqlm4_u: t_eq_lm4_u <= not( t_eq_lm4_01_b or t_eq_lm4_23_b ); + ucmp_teqlm4_w: t_eq_lm4_v <= not( t_eq_lm4_45_b ); + ucmp_teqlm4: t_eq_lm4_b <= not( t_eq_lm4_u and t_eq_lm4_v and lm4_t_cmp_en ); + + ucmp_teqlm5_x: t_eq_lm5_x(0 to 5) <= not( lm5_ta_buf(0 to 5) xor is1_frt_buf5(0 to 5) ); + ucmp_teqlm5_01: t_eq_lm5_01_b <= not( t_eq_lm5_x(0) and t_eq_lm5_x(1) ); + ucmp_teqlm5_23: t_eq_lm5_23_b <= not( t_eq_lm5_x(2) and t_eq_lm5_x(3) ); + ucmp_teqlm5_45: t_eq_lm5_45_b <= not( t_eq_lm5_x(4) and t_eq_lm5_x(5) ); + ucmp_teqlm5_u: t_eq_lm5_u <= not( t_eq_lm5_01_b or t_eq_lm5_23_b ); + ucmp_teqlm5_w: t_eq_lm5_v <= not( t_eq_lm5_45_b ); + ucmp_teqlm5: t_eq_lm5_b <= not( t_eq_lm5_u and t_eq_lm5_v and lm5_t_cmp_en ); + + ucmp_teqlm6_x: t_eq_lm6_x(0 to 5) <= not( lm6_ta_buf(0 to 5) xor is1_frt_buf6(0 to 5) ); + ucmp_teqlm6_01: t_eq_lm6_01_b <= not( t_eq_lm6_x(0) and t_eq_lm6_x(1) ); + ucmp_teqlm6_23: t_eq_lm6_23_b <= not( t_eq_lm6_x(2) and t_eq_lm6_x(3) ); + ucmp_teqlm6_45: t_eq_lm6_45_b <= not( t_eq_lm6_x(4) and t_eq_lm6_x(5) ); + ucmp_teqlm6_u: t_eq_lm6_u <= not( t_eq_lm6_01_b or t_eq_lm6_23_b ); + ucmp_teqlm6_w: t_eq_lm6_v <= not( t_eq_lm6_45_b ); + ucmp_teqlm6: t_eq_lm6_b <= not( t_eq_lm6_u and t_eq_lm6_v and lm6_t_cmp_en ); + + ucmp_teqlm7_x: t_eq_lm7_x(0 to 5) <= not( lm7_ta_buf(0 to 5) xor is1_frt_buf6(0 to 5) ); + ucmp_teqlm7_01: t_eq_lm7_01_b <= not( t_eq_lm7_x(0) and t_eq_lm7_x(1) ); + ucmp_teqlm7_23: t_eq_lm7_23_b <= not( t_eq_lm7_x(2) and t_eq_lm7_x(3) ); + ucmp_teqlm7_45: t_eq_lm7_45_b <= not( t_eq_lm7_x(4) and t_eq_lm7_x(5) ); + ucmp_teqlm7_u: t_eq_lm7_u <= not( t_eq_lm7_01_b or t_eq_lm7_23_b ); + ucmp_teqlm7_w: t_eq_lm7_v <= not( t_eq_lm7_45_b ); + ucmp_teqlm7: t_eq_lm7_b <= not( t_eq_lm7_u and t_eq_lm7_v and lm7_t_cmp_en ); + + + + + + +-- #################################################### +-- # oring the compares together +-- #################################################### + + -- ## A GROUP ##################### + + ucmp_aor11: a_or_1_1 <= not( a_eq_lm0_b and a_eq_lm1_b ); + ucmp_aor12: a_or_1_2 <= not( a_eq_lm2_b and a_eq_lm3_b ); + ucmp_aor13: a_or_1_3 <= not( a_eq_lm4_b and a_eq_lm5_b ); + ucmp_aor14: a_or_1_4 <= not( a_eq_lm6_b and a_eq_lm7_b ); + ucmp_aor15: a_or_1_5 <= not( a_eq_lmc_ex4_b and a_eq_ex4_b ); + ucmp_aor16: a_or_1_6 <= not( a_eq_ex3_b and a_eq_ex2_b ); + ucmp_aor17: a_or_1_7 <= not( a_eq_ex1_b and a_eq_rf1_b ); + ucmp_aor18: a_or_1_8 <= not( a_eq_rf0_b and a_eq_is2_b ); + + ucmp_aor21: a_or_2_1_b <= not( a_or_1_1 or a_or_1_2 ); + ucmp_aor22: a_or_2_2_b <= not( a_or_1_3 or a_or_1_4 ); + ucmp_aor23: a_or_2_3_b <= not( a_or_1_5 or a_or_1_6 ); + ucmp_aor24: a_or_2_4_b <= not( a_or_1_7 or a_or_1_8 ); + + ucmp_aor31: a_or_3_1 <= not( a_or_2_1_b and a_or_2_2_b ); + ucmp_aor32: a_or_3_2 <= not( a_or_2_3_b and a_or_2_4_b ); + + ucmp_aor4: a_or_4_b <= not( a_group_en and (a_or_3_1 or a_or_3_2) ); + + + -- ## B GROUPs ##################### {2 parts because of ucode_end} + + ucmp_bor11: b_or_1_1 <= not( b_eq_lm0_b and b_eq_lm1_b ); + ucmp_bor12: b_or_1_2 <= not( b_eq_lm2_b and b_eq_lm3_b ); + ucmp_bor13: b_or_1_3 <= not( b_eq_lm4_b and b_eq_lm5_b ); + ucmp_bor14: b_or_1_4 <= not( b_eq_lm6_b and b_eq_lm7_b ); + ucmp_bor15: b_or_1_5 <= not( b_eq_lmc_ex4_b and b_eq_ex4_b ); + ucmp_bor16: b_or_1_6 <= not( b_eq_ex3_b and b_eq_ex2_b ); + ucmp_bor17: b_or_1_7 <= not( b_eq_ex1_b and b_eq_rf1_b ); + ucmp_bor18: b_or_1_8 <= not( b_eq_rf0_b and b_eq_is2_b ); + + ucmp_bor21: b_or_2_1_b <= not( b_or_1_1 or b_or_1_2 ); + ucmp_bor22: b_or_2_2_b <= not( b_or_1_3 or b_or_1_4 ); + ucmp_bor23: b_or_2_3_b <= not( b_or_1_5 or b_or_1_6 ); + ucmp_bor24: b_or_2_4_b <= not( b_or_1_7 or b_or_1_8 ); + + ucmp_bor31: b_or_3_1 <= not( b_or_2_1_b and b_or_2_2_b ); + ucmp_bor32: b_or_3_2 <= not( b_or_2_3_b and b_or_2_4_b ); + + ucmp_bor4: b_or_4_b <= not( b_group_en and (b_or_3_1 or b_or_3_2) ); + + ---------- b miro-code ------------ + + ucmp_uor15: u_or_1_5 <= not( u_eq_ex4_b ); + ucmp_uor16: u_or_1_6 <= not( u_eq_ex3_b and u_eq_ex2_b ); + ucmp_uor17: u_or_1_7 <= not( u_eq_ex1_b and u_eq_rf1_b ); + ucmp_uor18: u_or_1_8 <= not( u_eq_rf0_b and u_eq_is2_b ); + + ucmp_uor23: u_or_2_3_b <= not( u_or_1_5 or u_or_1_6 ); + ucmp_uor24: u_or_2_4_b <= not( u_or_1_7 or u_or_1_8 ); + + ucmp_uor31: u_or_3_1 <= not( u_or_2_3_b and u_or_2_4_b ); + + ucmp_uor4: u_or_4_b <= not( u_or_3_1 and u_group_en); + + -- ## C GROUP ##################### + + ucmp_cor11: c_or_1_1 <= not( c_eq_lm0_b and c_eq_lm1_b ); + ucmp_cor12: c_or_1_2 <= not( c_eq_lm2_b and c_eq_lm3_b ); + ucmp_cor13: c_or_1_3 <= not( c_eq_lm4_b and c_eq_lm5_b ); + ucmp_cor14: c_or_1_4 <= not( c_eq_lm6_b and c_eq_lm7_b ); + ucmp_cor15: c_or_1_5 <= not( c_eq_lmc_ex4_b and c_eq_ex4_b ); + ucmp_cor16: c_or_1_6 <= not( c_eq_ex3_b and c_eq_ex2_b ); + ucmp_cor17: c_or_1_7 <= not( c_eq_ex1_b and c_eq_rf1_b ); + ucmp_cor18: c_or_1_8 <= not( c_eq_rf0_b and c_eq_is2_b ); + + ucmp_cor21: c_or_2_1_b <= not( c_or_1_1 or c_or_1_2 ); + ucmp_cor22: c_or_2_2_b <= not( c_or_1_3 or c_or_1_4 ); + ucmp_cor23: c_or_2_3_b <= not( c_or_1_5 or c_or_1_6 ); + ucmp_cor24: c_or_2_4_b <= not( c_or_1_7 or c_or_1_8 ); + + ucmp_cor31: c_or_3_1 <= not( c_or_2_1_b and c_or_2_2_b ); + ucmp_cor32: c_or_3_2 <= not( c_or_2_3_b and c_or_2_4_b ); + + ucmp_cor4: c_or_4_b <= not( c_group_en and (c_or_3_1 or c_or_3_2) ); + + -- ## T GROUP ##################### + + ucmp_tor11: t_or_1_1 <= not( t_eq_lm0_b and t_eq_lm1_b ); + ucmp_tor12: t_or_1_2 <= not( t_eq_lm2_b and t_eq_lm3_b ); + ucmp_tor13: t_or_1_3 <= not( t_eq_lm4_b and t_eq_lm5_b ); + ucmp_tor14: t_or_1_4 <= not( t_eq_lm6_b and t_eq_lm7_b ); + + + ucmp_tor21: t_or_2_1_b <= not( t_or_1_1 or t_or_1_2 ); + ucmp_tor22: t_or_2_2_b <= not( t_or_1_3 or t_or_1_4 ); + + + ucmp_tor31: t_or_3_1 <= not( t_or_2_1_b and t_or_2_2_b ); + + + ucmp_tor4: t_or_4_b <= not( t_group_en and t_or_3_1 ); + + + +-- #################################################### +-- # compare enables +-- #################################################### +lm0_valid <= lm_v(0); +lm1_valid <= lm_v(1); +lm2_valid <= lm_v(2); +lm3_valid <= lm_v(3); +lm4_valid <= lm_v(4); +lm5_valid <= lm_v(5); +lm6_valid <= lm_v(6); +lm7_valid <= lm_v(7); + + + + lm0_a_cmp_en <= lm0_valid ; + lm0_b_cmp_en <= lm0_valid ; + lm0_c_cmp_en <= lm0_valid ; + lm0_t_cmp_en <= lm0_valid ; + + lm1_a_cmp_en <= lm1_valid ; + lm1_b_cmp_en <= lm1_valid ; + lm1_c_cmp_en <= lm1_valid ; + lm1_t_cmp_en <= lm1_valid ; + + lm2_a_cmp_en <= lm2_valid ; + lm2_b_cmp_en <= lm2_valid ; + lm2_c_cmp_en <= lm2_valid ; + lm2_t_cmp_en <= lm2_valid ; + + lm3_a_cmp_en <= lm3_valid ; + lm3_b_cmp_en <= lm3_valid ; + lm3_c_cmp_en <= lm3_valid ; + lm3_t_cmp_en <= lm3_valid ; + + lm4_a_cmp_en <= lm4_valid ; + lm4_b_cmp_en <= lm4_valid ; + lm4_c_cmp_en <= lm4_valid ; + lm4_t_cmp_en <= lm4_valid ; + + lm5_a_cmp_en <= lm5_valid ; + lm5_b_cmp_en <= lm5_valid ; + lm5_c_cmp_en <= lm5_valid ; + lm5_t_cmp_en <= lm5_valid ; + + lm6_a_cmp_en <= lm6_valid ; + lm6_b_cmp_en <= lm6_valid ; + lm6_c_cmp_en <= lm6_valid ; + lm6_t_cmp_en <= lm6_valid ; + + lm7_a_cmp_en <= lm7_valid ; + lm7_b_cmp_en <= lm7_valid ; + lm7_c_cmp_en <= lm7_valid ; + lm7_t_cmp_en <= lm7_valid ; + + lmc_ex4_a_cmp_en <= lmc_ex4_v; + lmc_ex4_b_cmp_en <= lmc_ex4_v; + lmc_ex4_c_cmp_en <= lmc_ex4_v; + + is2_a_cmp_en <= is2_frt_v ; + is2_b_cmp_en <= is2_frt_v ; + is2_c_cmp_en <= is2_frt_v ; + + rf0_a_cmp_en <= rf0_frt_v ; + rf0_b_cmp_en <= rf0_frt_v ; + rf0_c_cmp_en <= rf0_frt_v ; + + rf1_a_cmp_en <= rf1_frt_v ; + rf1_b_cmp_en <= rf1_frt_v ; + rf1_c_cmp_en <= rf1_frt_v ; + + ex1_a_cmp_en <= ex1_frt_v ; + ex1_b_cmp_en <= ex1_frt_v ; + ex1_c_cmp_en <= ex1_frt_v ; + + ex2_a_cmp_en <= ex2_frt_v ; + ex2_b_cmp_en <= ex2_frt_v ; + ex2_c_cmp_en <= ex2_frt_v ; + + ex3_a_cmp_en <= ex3_frt_v and (dis_byp_is1 or is1_store_v or ex3_ld_v) ; + ex3_b_cmp_en <= ex3_frt_v and (dis_byp_is1 or is1_store_v or ex3_ld_v) ; + ex3_c_cmp_en <= ex3_frt_v and (dis_byp_is1 or ex3_ld_v) ; + + ex4_a_cmp_en <= ex4_frt_v and (dis_byp_is1 or (is1_store_v and ex4_ld_v)); + ex4_b_cmp_en <= ex4_frt_v and (dis_byp_is1 or (is1_store_v and ex4_ld_v)); + ex4_c_cmp_en <= ex4_frt_v and dis_byp_is1 ; + + -- + + is2_u_cmp_en <= is2_frt_v ; + rf0_u_cmp_en <= rf0_frt_v ; + rf1_u_cmp_en <= rf1_frt_v ; + ex1_u_cmp_en <= ex1_frt_v ; + ex2_u_cmp_en <= ex2_frt_v ; + ex3_u_cmp_en <= ex3_frt_v ; + ex4_u_cmp_en <= ex4_frt_v ; + + ----------------------------------------------- + + a_group_en <= is1_fra_v and is1_instr_v ; + c_group_en <= is1_frc_v and is1_instr_v ; + b_group_en <= is1_frb_v and is1_instr_v ; + u_group_en <= uc_end_is1 and is1_instr_v ; + t_group_en <= is1_frt_v and is1_instr_v ; + + + raw_fra_hit_b <= a_or_4_b; + raw_frb_hit_b <= b_or_4_b; + raw_frc_hit_b <= c_or_4_b; + + raw_frb_uc_hit_b <= u_or_4_b; + is1_lmq_waw_hit_b <= t_or_4_b; + + +end iuq_axu_fu_dep_cmp; diff --git a/rel/src/vhdl/work/iuq_axu_fu_iss.vhdl b/rel/src/vhdl/work/iuq_axu_fu_iss.vhdl new file mode 100644 index 0000000..637ae73 --- /dev/null +++ b/rel/src/vhdl/work/iuq_axu_fu_iss.vhdl @@ -0,0 +1,1350 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + + +--------------------------------------------------------------------- + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + use work.iuq_pkg.all; + +--------------------------------------------------------------------- + + +entity iuq_axu_fu_iss is +generic( + expand_type : integer := 2; + fpr_addr_width : integer := 5; + needs_sreset : integer := 1); -- 0 - ibm tech, 1 - other ); +port( + nclk : in clk_logic; + --------------------------------------------------------------------- + vdd : inout power_logic; + gnd : inout power_logic; + --------------------------------------------------------------------- + iu_au_is1_flush : in std_ulogic_vector(0 to 3); + xu_iu_is2_flush : in std_ulogic_vector(0 to 3); + uc_flush : in std_ulogic_vector(0 to 3); + --------------------------------------------------------------------- + -- pervasive + i_iss_si : in std_ulogic; + i_iss_so : out std_ulogic; + an_ac_scan_dis_dc_b : in std_ulogic; + pc_iu_func_sl_thold_2 : in std_ulogic; + pc_iu_sg_2 : in std_ulogic; + mpw1_b : in std_ulogic; + + clkoff_b :in std_ulogic; + + tc_ac_ccflush_dc :in std_ulogic; + delay_lclkr : in std_ulogic; + + -------------------------------------------------------- + i_axu_is2_instr_match_t0 : in std_ulogic; + i_axu_is2_instr_match_t1 : in std_ulogic; + i_axu_is2_instr_match_t2 : in std_ulogic; + i_axu_is2_instr_match_t3 : in std_ulogic; + + i_afd_is2_is_ucode_t0 : in std_ulogic; + i_afd_is2_is_ucode_t1 : in std_ulogic; + i_afd_is2_is_ucode_t2 : in std_ulogic; + i_afd_is2_is_ucode_t3 : in std_ulogic; + + i_afd_is2_t0_instr_v : in std_ulogic; + i_afd_is2_t1_instr_v : in std_ulogic; + i_afd_is2_t2_instr_v : in std_ulogic; + i_afd_is2_t3_instr_v : in std_ulogic; + + i_afd_is2_t0_instr : in std_ulogic_vector(0 to 31); + i_afd_is2_t1_instr : in std_ulogic_vector(0 to 31); + i_afd_is2_t2_instr : in std_ulogic_vector(0 to 31); + i_afd_is2_t3_instr : in std_ulogic_vector(0 to 31); + + i_afd_is2_fra_t0 : in std_ulogic_vector(0 to 6); + i_afd_is2_fra_t1 : in std_ulogic_vector(0 to 6); + i_afd_is2_fra_t2 : in std_ulogic_vector(0 to 6); + i_afd_is2_fra_t3 : in std_ulogic_vector(0 to 6); + + i_afd_is2_frb_t0 : in std_ulogic_vector(0 to 6); + i_afd_is2_frb_t1 : in std_ulogic_vector(0 to 6); + i_afd_is2_frb_t2 : in std_ulogic_vector(0 to 6); + i_afd_is2_frb_t3 : in std_ulogic_vector(0 to 6); + + i_afd_is2_frc_t0 : in std_ulogic_vector(0 to 6); + i_afd_is2_frc_t1 : in std_ulogic_vector(0 to 6); + i_afd_is2_frc_t2 : in std_ulogic_vector(0 to 6); + i_afd_is2_frc_t3 : in std_ulogic_vector(0 to 6); + + i_afd_is2_frt_t0 : in std_ulogic_vector(0 to 6); + i_afd_is2_frt_t1 : in std_ulogic_vector(0 to 6); + i_afd_is2_frt_t2 : in std_ulogic_vector(0 to 6); + i_afd_is2_frt_t3 : in std_ulogic_vector(0 to 6); + + i_afd_is2_fra_v_t0 : in std_ulogic; + i_afd_is2_fra_v_t1 : in std_ulogic; + i_afd_is2_fra_v_t2 : in std_ulogic; + i_afd_is2_fra_v_t3 : in std_ulogic; + + i_afd_is2_frb_v_t0 : in std_ulogic; + i_afd_is2_frb_v_t1 : in std_ulogic; + i_afd_is2_frb_v_t2 : in std_ulogic; + i_afd_is2_frb_v_t3 : in std_ulogic; + + i_afd_is2_frc_v_t0 : in std_ulogic; + i_afd_is2_frc_v_t1 : in std_ulogic; + i_afd_is2_frc_v_t2 : in std_ulogic; + i_afd_is2_frc_v_t3 : in std_ulogic; + + i_afd_is2_bypsel_t0 : in std_ulogic_vector(0 to 5); + i_afd_is2_bypsel_t1 : in std_ulogic_vector(0 to 5); + i_afd_is2_bypsel_t2 : in std_ulogic_vector(0 to 5); + i_afd_is2_bypsel_t3 : in std_ulogic_vector(0 to 5); + + i_afd_is2_ifar_t0 : in EFF_IFAR; + i_afd_is2_ifar_t1 : in EFF_IFAR; + i_afd_is2_ifar_t2 : in EFF_IFAR; + i_afd_is2_ifar_t3 : in EFF_IFAR; + + + i_axu_is1_dep_hit_t0_b : in std_ulogic; + i_axu_is1_dep_hit_t1_b : in std_ulogic; + i_axu_is1_dep_hit_t2_b : in std_ulogic; + i_axu_is1_dep_hit_t3_b : in std_ulogic; + + i_axu_is1_early_v_t0 : in std_ulogic; + i_axu_is1_early_v_t1 : in std_ulogic; + i_axu_is1_early_v_t2 : in std_ulogic; + i_axu_is1_early_v_t3 : in std_ulogic; + + ifdp_is2_est_bubble3_t0 : in std_ulogic; + ifdp_is2_est_bubble3_t1 : in std_ulogic; + ifdp_is2_est_bubble3_t2 : in std_ulogic; + ifdp_is2_est_bubble3_t3 : in std_ulogic; + + iu_au_md_pri_mask : in std_ulogic_vector(0 to 3); + iu_au_hi_pri_mask : in std_ulogic_vector(0 to 3); + + spr_fiss_pri_rand : in std_ulogic_vector(0 to 4); + spr_fiss_pri_rand_always : in std_ulogic; + spr_fiss_pri_rand_flush : in std_ulogic; + + -------------------------------------------------------- + iu_is2_take_t : out std_ulogic_vector(0 to 3); + iu_fu_is2_tid_decode : out std_ulogic_vector(0 to 3); + -------------------------------------------------------- + -- to FU + iu_fu_rf0_instr_match : out std_ulogic; + iu_fu_rf0_instr : out std_ulogic_vector(0 to 31); + iu_fu_rf0_instr_v : out std_ulogic; + iu_fu_rf0_is_ucode : out std_ulogic; + + iu_fu_rf0_fra : out std_ulogic_vector(0 to 6); + iu_fu_rf0_frb : out std_ulogic_vector(0 to 6); + iu_fu_rf0_frc : out std_ulogic_vector(0 to 6); + iu_fu_rf0_frt : out std_ulogic_vector(0 to 6); + + iu_fu_rf0_fra_v : out std_ulogic; + iu_fu_rf0_frb_v : out std_ulogic; + iu_fu_rf0_frc_v : out std_ulogic; + + iu_fu_rf0_ucfmul : out std_ulogic; + + + + i_afd_ignore_flush_is2_t0 : in std_ulogic; -- for ppc div or sqrt + i_afd_ignore_flush_is2_t1 : in std_ulogic; + i_afd_ignore_flush_is2_t2 : in std_ulogic; + i_afd_ignore_flush_is2_t3 : in std_ulogic; + + i_afd_config_iucr_t0 : in std_ulogic_vector(2 to 4); + i_afd_config_iucr_t1 : in std_ulogic_vector(2 to 4); + i_afd_config_iucr_t2 : in std_ulogic_vector(2 to 4); + i_afd_config_iucr_t3 : in std_ulogic_vector(2 to 4); + + i_afd_in_ucode_mode_or1d_b_t0 : in std_ulogic; + i_afd_in_ucode_mode_or1d_b_t1 : in std_ulogic; + i_afd_in_ucode_mode_or1d_b_t2 : in std_ulogic; + i_afd_in_ucode_mode_or1d_b_t3 : in std_ulogic; + + fu_iss_debug : out std_ulogic_vector(0 to 23); + + iu_fu_rf0_tid : out std_ulogic_vector(0 to 1); + + iu_fu_rf0_bypsel : out std_ulogic_vector(0 to 5); + + iu_fu_rf0_ifar : out EFF_IFAR + +); + + -- synopsys translate_off + + + + + + -- synopsys translate_on + +end iuq_axu_fu_iss; + +-------------------------------------------------------------------------------------------------------------------------------------------------------- + +architecture iuq_axu_fu_iss of iuq_axu_fu_iss is +signal act_dis : std_ulogic; +signal d_mode : std_ulogic; +signal mpw2_b : std_ulogic; + +signal tidn : std_ulogic; +signal tiup : std_ulogic; + +signal is2_issue_sel : std_ulogic_vector(0 to 3); + +signal is2_issue_sel_buf1_b : std_ulogic_vector(0 to 3); +signal is2_issue_sel_buf2 : std_ulogic_vector(0 to 3); +signal is2_issue_sel_buf3_b : std_ulogic_vector(0 to 3); +signal is2_issue_sel_buf4 : std_ulogic_vector(0 to 3); + + +signal rf0_wpc_sp_latch_scout : std_ulogic_vector(0 to 4); +signal rf0_wpc_sp_latch_scin : std_ulogic_vector(0 to 4); + +signal debug_reg_scin : std_ulogic_vector(0 to 4); +signal debug_reg_scout : std_ulogic_vector(0 to 4); + +signal hi_n230, hi_n231, hi_n232 : std_ulogic; +signal hi_n220, hi_n221, hi_n210 : std_ulogic; +signal md_n230, md_n231, md_n232 : std_ulogic; +signal md_n220, md_n221, md_n210 : std_ulogic; + + +signal medpri_v, medpri_v_b, highpri_v, highpri_v_b : std_ulogic_vector(0 to 3); + +signal is2_bubble_latch_scin: std_ulogic_vector(0 to 2); +signal is2_bubble_latch_scout: std_ulogic_vector(0 to 2); +signal is2_skip_latch_scin: std_ulogic_vector(0 to 3); +signal is2_skip_latch_scout: std_ulogic_vector(0 to 3); + + + + +signal rf0_stage_latch_scin : std_ulogic_vector(0 to 76+EFF_IFAR'length); +signal rf0_stage_latch_scout : std_ulogic_vector(0 to 76+EFF_IFAR'length); + + +signal spare_unused : std_ulogic_vector(00 to 10); +signal spare_l2 : std_ulogic_vector(00 to 6); + + + +signal skip_b :std_ulogic_vector(0 to 3); + +signal is2_insert_one_bubble, is2_insert_two_bubbles, is2_insert_three_bubbles, is2_insert_seven_bubbles :std_ulogic; +signal single_step_mode, single_step_divsqrt_mode, divsqrt_mode :std_ulogic; + +signal bubble_din, bubble_dout : std_ulogic_vector(2 to 4); +signal skip_din, skip_dout : std_ulogic_vector(0 to 3); + +signal hi_mask_v_b, md_mask_v_b: std_ulogic_vector(0 to 3); +signal hi_mask_v, md_mask_v: std_ulogic_vector(0 to 3); + +signal is2_v_t : std_ulogic_vector(0 to 3); + +signal iu_fu_is2_instr_match : std_ulogic; +signal iu_fu_is2_instr : std_ulogic_vector(0 to 31); +signal iu_fu_is2_instr_v : std_ulogic; +signal is2_instr_v, disable_cgat : std_ulogic; +signal is2_act_din, is2_act_l2, is2_act : std_ulogic; + +signal iu_fu_is2_fra : std_ulogic_vector(0 to 6); +signal iu_fu_is2_frb : std_ulogic_vector(0 to 6); +signal iu_fu_is2_frc : std_ulogic_vector(0 to 6); +signal iu_fu_is2_frt : std_ulogic_vector(0 to 6); +signal iu_fu_is2_fra_v : std_ulogic; +signal iu_fu_is2_frb_v : std_ulogic; +signal iu_fu_is2_frc_v : std_ulogic; +signal iu_fu_is2_ucfmul : std_ulogic; +signal iu_fu_is2_tid : std_ulogic_vector(0 to 1); +signal rf0_tid : std_ulogic_vector(0 to 1); + +signal iu_fu_is2_bypsel : std_ulogic_vector(0 to 5); +signal iu_fu_is2_bypsel_din : std_ulogic_vector(0 to 5); +signal is2_ifar : EFF_IFAR; +signal is2_ifar_t0 : EFF_IFAR; +signal is2_ifar_t1 : EFF_IFAR; +signal is2_ifar_t2 : EFF_IFAR; +signal is2_ifar_t3 : EFF_IFAR; + +signal rf0_ifar : EFF_IFAR; + + +signal pc_iu_sg_0, pc_iu_sg_1 : std_ulogic; +signal pc_iu_func_sl_thold_0 , pc_iu_func_sl_thold_1 : std_ulogic; +signal pc_iu_func_sl_thold_0_b : std_ulogic; +signal forcee : std_ulogic; + +signal is2_flush : std_ulogic_vector(0 to 3); + +signal is2_is_ucode : std_ulogic; +signal is2_issue_sel_db : std_ulogic_vector(0 to 3); + +signal is2_stall : std_ulogic_vector(0 to 3); +signal dep_hit_b : std_ulogic_vector(0 to 3); + +signal is1_v_din_premux : std_ulogic_vector(0 to 3); +signal is2_v_dout_premux : std_ulogic_vector(0 to 3); +signal is1_v_din : std_ulogic_vector(0 to 3); +signal is2_v_dout : std_ulogic_vector(0 to 3); +signal ignore_flush_is2 : std_ulogic_vector(0 to 3); + +signal is2v_scin, is2v_scout : std_ulogic_vector(0 to 3); +signal mask_scin, mask_scout : std_ulogic_vector(0 to 7); +signal hi_pri_mask_q : std_ulogic_vector(0 to 3); +signal md_pri_mask_q : std_ulogic_vector(0 to 3); + +signal rf0_took_latch_scout : std_ulogic_vector(0 to 11); +signal rf0_took_latch_scin : std_ulogic_vector(0 to 11); + + +signal hi_did0no1, hi_did0no2, hi_did0no3 : std_ulogic; +signal hi_did1no0, hi_did1no2, hi_did1no3 : std_ulogic; +signal hi_did2no1, hi_did2no0, hi_did2no3 : std_ulogic; +signal hi_did3no1, hi_did3no2, hi_did3no0 : std_ulogic; + +signal md_did0no1, md_did0no2, md_did0no3 : std_ulogic; +signal md_did1no0, md_did1no2, md_did1no3 : std_ulogic; +signal md_did2no1, md_did2no0, md_did2no3 : std_ulogic; +signal md_did3no1, md_did3no2, md_did3no0 : std_ulogic; + +signal hi_sel, hi_sel_b, md_sel, md_sel_b, hi_later, md_later : std_ulogic_vector(0 to 3); + +signal hi_did3no0_din : std_ulogic; +signal hi_did3no1_din : std_ulogic; +signal hi_did3no2_din : std_ulogic; + +signal hi_did2no0_din : std_ulogic; +signal hi_did2no1_din : std_ulogic; + +signal hi_did1no0_din : std_ulogic; + +signal md_did3no0_din : std_ulogic; +signal md_did3no1_din : std_ulogic; +signal md_did3no2_din : std_ulogic; + +signal md_did2no0_din : std_ulogic; +signal md_did2no1_din : std_ulogic; + +signal md_did1no0_din : std_ulogic; +signal pri_rand : std_ulogic_vector(0 to 5); +signal hi_did3no0_d : std_ulogic; +signal hi_did3no1_d : std_ulogic; +signal hi_did3no2_d : std_ulogic; + +signal hi_did2no0_d : std_ulogic; +signal hi_did2no1_d : std_ulogic; + +signal hi_did1no0_d : std_ulogic; + +signal md_did3no0_d : std_ulogic; +signal md_did3no1_d : std_ulogic; +signal md_did3no2_d : std_ulogic; + +signal md_did2no0_d : std_ulogic; +signal md_did2no1_d : std_ulogic; + +signal md_did1no0_d : std_ulogic; + + +signal issselhi_b, issselmd_b : std_ulogic_vector(0 to 3); +signal issselhi2_b, issselmd2_b : std_ulogic_vector(0 to 3); +signal no_hi_v,no_hi_v_n01, no_hi_v_n23 : std_ulogic; + +signal hi_l30, hi_l31, hi_l32 : std_ulogic; +signal hi_l23, hi_l20, hi_l21 : std_ulogic; +signal hi_l12, hi_l13, hi_l10 : std_ulogic; +signal hi_l01, hi_l02, hi_l03 : std_ulogic; + +signal md_l30, md_l31, md_l32 : std_ulogic; +signal md_l23, md_l20, md_l21 : std_ulogic; +signal md_l12, md_l13, md_l10 : std_ulogic; +signal md_l01, md_l02, md_l03 : std_ulogic; + +signal iu_is2_take_t_int_b : std_ulogic_vector(0 to 3); +signal iu_is2_take_t_int : std_ulogic_vector(0 to 3); + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +begin + +tidn <= '0'; +tiup <= '1'; + +act_dis <= '0'; +d_mode <= '0'; +mpw2_b <= '1'; + + +-- ############################################ +-- # pervasive +-- ############################################ + + + + + + + + + + + auperv_2to1_reg: tri_plat + generic map (width => 2, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_iu_func_sl_thold_2, + din(1) => pc_iu_sg_2, + q(0) => pc_iu_func_sl_thold_1, + q(1) => pc_iu_sg_1); +auperv_1to0_reg: tri_plat + generic map (width => 2, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_iu_func_sl_thold_1, + din(1) => pc_iu_sg_1, + q(0) => pc_iu_func_sl_thold_0, + q(1) => pc_iu_sg_0); + + + + + lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map ( + clkoff_b => clkoff_b, + thold => pc_iu_func_sl_thold_0, + sg => pc_iu_sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => pc_iu_func_sl_thold_0_b ); + + + + + + + ignore_flush_is2(0 to 3) <= (i_afd_ignore_flush_is2_t0 and not xu_iu_is2_flush(0)) & + (i_afd_ignore_flush_is2_t1 and not xu_iu_is2_flush(1)) & + (i_afd_ignore_flush_is2_t2 and not xu_iu_is2_flush(2)) & + (i_afd_ignore_flush_is2_t3 and not xu_iu_is2_flush(3)); + + +-- ############################################ +-- # IS2 Early Valid Logic. Duplicate latch in DEP +-- ############################################ + + + is2_stall(0 to 3) <= is2_v_t(0 to 3) and not is2_issue_sel(0 to 3); + + dep_hit_b(0 to 3) <= i_axu_is1_dep_hit_t0_b & i_axu_is1_dep_hit_t1_b & i_axu_is1_dep_hit_t2_b & i_axu_is1_dep_hit_t3_b; + + is1_v_din_premux(0 to 3) <= ((i_axu_is1_early_v_t0 & i_axu_is1_early_v_t1 & i_axu_is1_early_v_t2 & i_axu_is1_early_v_t3) + and not is2_stall(0 to 3)) + and (not iu_au_is1_flush(0 to 3)); + + + is1_v_din(0 to 3) <= (is1_v_din_premux(0 to 3) and dep_hit_b(0 to 3)) or + (is2_v_dout_premux(0 to 3) and is2_stall(0 to 3)); + + is2v_reg: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 4) + port map ( + nclk => nclk, act => tiup, + vd => vdd, gd => gnd, + forcee => forcee, delay_lclkr => delay_lclkr, + thold_b => pc_iu_func_sl_thold_0_b, sg => pc_iu_sg_0, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + scin => is2v_scin, + scout => is2v_scout , + --------------------------------------------- + din(0 to 3) => is1_v_din(0 to 3), + + --------------------------------------------- + dout(0 to 3) => is2_v_dout(0 to 3) + + --------------------------------------------- + ); + +-- if a fdiv or fsqrt is issued in the fxu and stalled (in is2) by the axu, it should not be flushed + is2_v_dout_premux(0 to 3) <= is2_v_dout(0 to 3) and (not is2_flush(0 to 3) or ignore_flush_is2(0 to 3)); + + is2_v_t(0 to 3) <= is2_v_dout(0 to 3); + + + + mask_reg: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 8) + port map ( + nclk => nclk, act => tiup, + vd => vdd, gd => gnd, + forcee => forcee, delay_lclkr => delay_lclkr, + thold_b => pc_iu_func_sl_thold_0_b, sg => pc_iu_sg_0, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + scin => mask_scin, + scout => mask_scout , + --------------------------------------------- + din(0 to 3) => iu_au_hi_pri_mask(0 to 3), + din(4 to 7) => iu_au_md_pri_mask(0 to 3), + + --------------------------------------------- + dout(0 to 3) => hi_pri_mask_q(0 to 3), + dout(4 to 7) => md_pri_mask_q(0 to 3) + + --------------------------------------------- + ); + + + +-- iu_au_is2_flush +is2_flush(0 to 3) <= xu_iu_is2_flush(0 to 3) or uc_flush(0 to 3); + + +------------------------------------------------------------------------------------------------------------------------ +-- Issue selection logic (replaced table 2/08/2008 -- priority scheme from NorthStar/Sherman +------------------------------------------------------------------------------------------------------------------------ + + + + + + skip_b(0) <= not skip_dout(0); + skip_b(1) <= not skip_dout(1); + skip_b(2) <= not skip_dout(2); + skip_b(3) <= not skip_dout(3); + + + +hi_mask_v_nand2: hi_mask_v_b <= not(hi_pri_mask_q(0 to 3) and is2_v_dout(0 to 3)); +md_mask_v_nand2: md_mask_v_b <= not(md_pri_mask_q(0 to 3) and is2_v_dout(0 to 3)); + +hi_mask_v_inv: hi_mask_v <= not hi_mask_v_b; +md_mask_v_inv: md_mask_v <= not md_mask_v_b; + +highpri0v_nand2: highpri_v_b(0) <= not(hi_mask_v(0) and skip_b(0)); +highpri1v_nand2: highpri_v_b(1) <= not(hi_mask_v(1) and skip_b(1)); +highpri2v_nand2: highpri_v_b(2) <= not(hi_mask_v(2) and skip_b(2)); +highpri3v_nand2: highpri_v_b(3) <= not(hi_mask_v(3) and skip_b(3)); + + +medpri0v_nand2: medpri_v_b(0) <= not(md_mask_v(0) and skip_b(0)); +medpri1v_nand2: medpri_v_b(1) <= not(md_mask_v(1) and skip_b(1)); +medpri2v_nand2: medpri_v_b(2) <= not(md_mask_v(2) and skip_b(2)); +medpri3v_nand2: medpri_v_b(3) <= not(md_mask_v(3) and skip_b(3)); + + +-- selection priority among high priority threads only +highpri0v_inv: highpri_v(0) <= not highpri_v_b(0); +highpri1v_inv: highpri_v(1) <= not highpri_v_b(1); +highpri2v_inv: highpri_v(2) <= not highpri_v_b(2); +highpri3v_inv: highpri_v(3) <= not highpri_v_b(3); + +hi_sel_nor23: hi_sel(3) <= not (highpri_v_b(3) or hi_later(3)); +hi_sel_nand33: hi_later(3) <= not (hi_l30 and hi_l31 and hi_l32); +hi_sel_nand230: hi_l30 <= not (hi_did3no0 and highpri_v(0)); +hi_sel_nand231: hi_l31 <= not (hi_did3no1 and highpri_v(1)); +hi_sel_nand232: hi_l32 <= not (hi_did3no2 and highpri_v(2)); + +hi_sel_nor22: hi_sel(2) <= not (highpri_v_b(2) or hi_later(2)) ; +hi_sel_nand32: hi_later(2) <= not (hi_l23 and hi_l20 and hi_l21); +hi_sel_nand223: hi_l23 <= not (hi_did2no3 and highpri_v(3)); +hi_sel_nand220: hi_l20 <= not (hi_did2no0 and highpri_v(0)); +hi_sel_nand221: hi_l21 <= not (hi_did2no1 and highpri_v(1)); + +hi_sel_nor21: hi_sel(1) <= not (highpri_v_b(1) or hi_later(1)) ; +hi_sel_nand31: hi_later(1) <= not (hi_l12 and hi_l13 and hi_l10); +hi_sel_nand212: hi_l12 <= not (hi_did1no2 and highpri_v(2)); +hi_sel_nand213: hi_l13 <= not (hi_did1no3 and highpri_v(3)); +hi_sel_nand210: hi_l10 <= not (hi_did1no0 and highpri_v(0)); + +hi_sel_nor20: hi_sel(0) <= not (highpri_v_b(0) or hi_later(0)) ; +hi_sel_nand30: hi_later(0) <= not (hi_l01 and hi_l02 and hi_l03); +hi_sel_nand201: hi_l01 <= not (hi_did0no1 and highpri_v(1)); +hi_sel_nand202: hi_l02 <= not (hi_did0no2 and highpri_v(2)); +hi_sel_nand203: hi_l03 <= not (hi_did0no3 and highpri_v(3)); + + +-- selection priority among med priority threads only +medpri0v_inv: medpri_v(0) <= not medpri_v_b(0); +medpri1v_inv: medpri_v(1) <= not medpri_v_b(1); +medpri2v_inv: medpri_v(2) <= not medpri_v_b(2); +medpri3v_inv: medpri_v(3) <= not medpri_v_b(3); + +md_sel_nor23: md_sel(3) <= not (medpri_v_b(3) or md_later(3)); +md_sel_nand33: md_later(3) <= not (md_l30 and md_l31 and md_l32); +md_sel_nand230: md_l30 <= not (md_did3no0 and medpri_v(0)); +md_sel_nand231: md_l31 <= not (md_did3no1 and medpri_v(1)); +md_sel_nand232: md_l32 <= not (md_did3no2 and medpri_v(2)); + +md_sel_nor22: md_sel(2) <= not (medpri_v_b(2) or md_later(2)) ; +md_sel_nand32: md_later(2) <= not (md_l23 and md_l20 and md_l21); +md_sel_nand223: md_l23 <= not (md_did2no3 and medpri_v(3)); +md_sel_nand220: md_l20 <= not (md_did2no0 and medpri_v(0)); +md_sel_nand221: md_l21 <= not (md_did2no1 and medpri_v(1)); + +md_sel_nor21: md_sel(1) <= not (medpri_v_b(1) or md_later(1)) ; +md_sel_nand31: md_later(1) <= not (md_l12 and md_l13 and md_l10); +md_sel_nand212: md_l12 <= not (md_did1no2 and medpri_v(2)); +md_sel_nand213: md_l13 <= not (md_did1no3 and medpri_v(3)); +md_sel_nand210: md_l10 <= not (md_did1no0 and medpri_v(0)); + +md_sel_nor20: md_sel(0) <= not (medpri_v_b(0) or md_later(0)) ; +md_sel_nand30: md_later(0) <= not (md_l01 and md_l02 and md_l03); +md_sel_nand201: md_l01 <= not (md_did0no1 and medpri_v(1)); +md_sel_nand202: md_l02 <= not (md_did0no2 and medpri_v(2)); +md_sel_nand203: md_l03 <= not (md_did0no3 and medpri_v(3)); + + + + +-- reorder section + +hi_sel_inv0: hi_sel_b(0) <= not hi_sel(0); +hi_sel_inv1: hi_sel_b(1) <= not hi_sel(1); +hi_sel_inv2: hi_sel_b(2) <= not hi_sel(2); +hi_sel_inv3: hi_sel_b(3) <= not hi_sel(3); + +hi_reordf_nand230: hi_did3no0_din <= not (hi_sel_b(3) and hi_n230); +hi_reordf_nand231: hi_did3no1_din <= not (hi_sel_b(3) and hi_n231); +hi_reordf_nand232: hi_did3no2_din <= not (hi_sel_b(3) and hi_n232); +hi_reord_nand230: hi_n230 <= not (hi_sel_b(0) and hi_did3no0); +hi_reord_nand231: hi_n231 <= not (hi_sel_b(1) and hi_did3no1); +hi_reord_nand232: hi_n232 <= not (hi_sel_b(2) and hi_did3no2); + + + +hi_reordf_nand220: hi_did2no0_din <= not(hi_sel_b(2) and hi_n220); +hi_reord_nand220: hi_n220 <= not(hi_sel_b(0) and hi_did2no0); + +hi_reordf_nand221: hi_did2no1_din <= not(hi_sel_b(2) and hi_n221); +hi_reord_nand221: hi_n221 <= not(hi_sel_b(1) and hi_did2no1); + +hi_reord_inv23: hi_did2no3 <= not hi_did3no2; + +hi_reordf_nand210: hi_did1no0_din <= not(hi_sel_b(1) and hi_n210); +hi_reord_nand210: hi_n210 <= not(hi_sel_b(0) and hi_did1no0); + +hi_reord_inv12: hi_did1no2 <= not hi_did2no1; +hi_reord_inv13: hi_did1no3 <= not hi_did3no1; + +hi_reord_inv01: hi_did0no1 <= not hi_did1no0; +hi_reord_inv02: hi_did0no2 <= not hi_did2no0; +hi_reord_inv03: hi_did0no3 <= not hi_did3no0; + + +-- med section + +md_sel_inv0: md_sel_b(0) <= not md_sel(0); +md_sel_inv1: md_sel_b(1) <= not md_sel(1); +md_sel_inv2: md_sel_b(2) <= not md_sel(2); +md_sel_inv3: md_sel_b(3) <= not md_sel(3); + +md_reordf_nand230: md_did3no0_din <= not (md_sel_b(3) and md_n230); +md_reordf_nand231: md_did3no1_din <= not (md_sel_b(3) and md_n231); +md_reordf_nand232: md_did3no2_din <= not (md_sel_b(3) and md_n232); +md_reord_nand230: md_n230 <= not (md_sel_b(0) and md_did3no0); +md_reord_nand231: md_n231 <= not (md_sel_b(1) and md_did3no1); +md_reord_nand232: md_n232 <= not (md_sel_b(2) and md_did3no2); + + +md_reordf_nand220: md_did2no0_din <= not(md_sel_b(2) and md_n220); +md_reord_nand220: md_n220 <= not(md_sel_b(0) and md_did2no0); + +md_reordf_nand221: md_did2no1_din <= not(md_sel_b(2) and md_n221); +md_reord_nand221: md_n221 <= not(md_sel_b(1) and md_did2no1); + +md_reord_inv23: md_did2no3 <= not md_did3no2; + +md_reordf_nand210: md_did1no0_din <= not(md_sel_b(1) and md_n210); +md_reord_nand210: md_n210 <= not(md_sel_b(0) and md_did1no0); + +md_reord_inv12: md_did1no2 <= not md_did2no1; +md_reord_inv13: md_did1no3 <= not md_did3no1; + +md_reord_inv01: md_did0no1 <= not md_did1no0; +md_reord_inv02: md_did0no2 <= not md_did2no0; +md_reord_inv03: md_did0no3 <= not md_did3no0; + + + + + +nohi_nand21: no_hi_v_n01 <= not (hi_mask_v_b(0) and hi_mask_v_b(1)); +nohi_nand22: no_hi_v_n23 <= not (hi_mask_v_b(2) and hi_mask_v_b(3)); +nohi_nor2: no_hi_v <= not (no_hi_v_n01 or no_hi_v_n23); + + +isssel0_inv: issselhi_b(0) <= not (hi_sel(0)); +isssel1_inv: issselhi_b(1) <= not (hi_sel(1)); +isssel2_inv: issselhi_b(2) <= not (hi_sel(2)); +isssel3_inv: issselhi_b(3) <= not (hi_sel(3)); + +isssel0_bnand2: issselmd_b(0) <= not (md_sel(0) and no_hi_v); +isssel1_bnand2: issselmd_b(1) <= not (md_sel(1) and no_hi_v); +isssel2_bnand2: issselmd_b(2) <= not (md_sel(2) and no_hi_v); +isssel3_bnand2: issselmd_b(3) <= not (md_sel(3) and no_hi_v); + +isssel0_2inv: issselhi2_b(0) <= not (hi_sel(0)); +isssel1_2inv: issselhi2_b(1) <= not (hi_sel(1)); +isssel2_2inv: issselhi2_b(2) <= not (hi_sel(2)); +isssel3_2inv: issselhi2_b(3) <= not (hi_sel(3)); + +isssel0_2bnand2: issselmd2_b(0) <= not (md_sel(0) and no_hi_v); +isssel1_2bnand2: issselmd2_b(1) <= not (md_sel(1) and no_hi_v); +isssel2_2bnand2: issselmd2_b(2) <= not (md_sel(2) and no_hi_v); +isssel3_2bnand2: issselmd2_b(3) <= not (md_sel(3) and no_hi_v); + + + + +isssel0_fnand2: iu_is2_take_t(0) <= not (issselhi2_b(0) and issselmd2_b(0)); +isssel1_fnand2: iu_is2_take_t(1) <= not (issselhi2_b(1) and issselmd2_b(1)); +isssel2_fnand2: iu_is2_take_t(2) <= not (issselhi2_b(2) and issselmd2_b(2)); +isssel3_fnand2: iu_is2_take_t(3) <= not (issselhi2_b(3) and issselmd2_b(3)); + + + + + + iu_is2_take_t_int(0) <= not (issselhi_b(0) and issselmd_b(0)); + iu_is2_take_t_int(1) <= not (issselhi_b(1) and issselmd_b(1)); + iu_is2_take_t_int(2) <= not (issselhi_b(2) and issselmd_b(2)); + iu_is2_take_t_int(3) <= not (issselhi_b(3) and issselmd_b(3)); + + + +fu_tid_invB0: iu_is2_take_t_int_b(0) <= not iu_is2_take_t_int(0); +fu_tid_invB1: iu_is2_take_t_int_b(1) <= not iu_is2_take_t_int(1); +fu_tid_invB2: iu_is2_take_t_int_b(2) <= not iu_is2_take_t_int(2); +fu_tid_invB3: iu_is2_take_t_int_b(3) <= not iu_is2_take_t_int(3); + +fu_tid_invA0: iu_fu_is2_tid_decode(0) <= not iu_is2_take_t_int_b(0); +fu_tid_invA1: iu_fu_is2_tid_decode(1) <= not iu_is2_take_t_int_b(1); +fu_tid_invA2: iu_fu_is2_tid_decode(2) <= not iu_is2_take_t_int_b(2); +fu_tid_invA3: iu_fu_is2_tid_decode(3) <= not iu_is2_take_t_int_b(3); + + + +is2_issue_sel(0 to 3) <= not (issselhi_b(0 to 3) and issselmd_b(0 to 3)); + + + +-- issue_sel mapping/buffering +is2_issue_sel_buf1_b(0 to 3) <= not is2_issue_sel(0 to 3); + +is2_issue_sel_buf2(0 to 3) <= not is2_issue_sel_buf1_b(0 to 3); + +is2_issue_sel_buf3_b(0 to 3) <= not is2_issue_sel_buf2(0 to 3); + +is2_issue_sel_buf4(0 to 3) <= not is2_issue_sel_buf3_b(0 to 3); + + +------------------------------------------------------------------------------------------------------------------------ +-- +------------------------------------------------------------------------------------------------------------------------ + + +iu_fu_is2_instr(0 to 31) <= (i_afd_is2_t0_instr and (0 to 31 => is2_issue_sel_buf4(0))) or + (i_afd_is2_t1_instr and (0 to 31 => is2_issue_sel_buf4(1))) or + (i_afd_is2_t2_instr and (0 to 31 => is2_issue_sel_buf4(2))) or + (i_afd_is2_t3_instr and (0 to 31 => is2_issue_sel_buf4(3))); + +is2_instr_v <= i_afd_is2_t0_instr_v or i_afd_is2_t1_instr_v or i_afd_is2_t2_instr_v or i_afd_is2_t3_instr_v; + +iu_fu_is2_instr_v <= ((i_afd_is2_t0_instr_v and (not is2_flush(0) or ignore_flush_is2(0))) and is2_issue_sel_buf4(0)) or + ((i_afd_is2_t1_instr_v and (not is2_flush(1) or ignore_flush_is2(1))) and is2_issue_sel_buf4(1)) or + ((i_afd_is2_t2_instr_v and (not is2_flush(2) or ignore_flush_is2(2))) and is2_issue_sel_buf4(2)) or + ((i_afd_is2_t3_instr_v and (not is2_flush(3) or ignore_flush_is2(3))) and is2_issue_sel_buf4(3)) ; + + +iu_fu_is2_fra <= (i_afd_is2_fra_t0 and (0 to 6 => is2_issue_sel_buf4(0))) or + (i_afd_is2_fra_t1 and (0 to 6 => is2_issue_sel_buf4(1))) or + (i_afd_is2_fra_t2 and (0 to 6 => is2_issue_sel_buf4(2))) or + (i_afd_is2_fra_t3 and (0 to 6 => is2_issue_sel_buf4(3))) ; + +iu_fu_is2_frb <= (i_afd_is2_frb_t0 and (0 to 6 => is2_issue_sel_buf4(0))) or + (i_afd_is2_frb_t1 and (0 to 6 => is2_issue_sel_buf4(1))) or + (i_afd_is2_frb_t2 and (0 to 6 => is2_issue_sel_buf4(2))) or + (i_afd_is2_frb_t3 and (0 to 6 => is2_issue_sel_buf4(3))) ; + +iu_fu_is2_frc <= (i_afd_is2_frc_t0 and (0 to 6 => is2_issue_sel_buf4(0))) or + (i_afd_is2_frc_t1 and (0 to 6 => is2_issue_sel_buf4(1))) or + (i_afd_is2_frc_t2 and (0 to 6 => is2_issue_sel_buf4(2))) or + (i_afd_is2_frc_t3 and (0 to 6 => is2_issue_sel_buf4(3))) ; + +iu_fu_is2_frt <= (i_afd_is2_frt_t0 and (0 to 6 => is2_issue_sel_buf4(0))) or + (i_afd_is2_frt_t1 and (0 to 6 => is2_issue_sel_buf4(1))) or + (i_afd_is2_frt_t2 and (0 to 6 => is2_issue_sel_buf4(2))) or + (i_afd_is2_frt_t3 and (0 to 6 => is2_issue_sel_buf4(3))) ; + + +iu_fu_is2_fra_v <= (i_afd_is2_fra_v_t0 and is2_issue_sel_buf4(0)) or + (i_afd_is2_fra_v_t1 and is2_issue_sel_buf4(1)) or + (i_afd_is2_fra_v_t2 and is2_issue_sel_buf4(2)) or + (i_afd_is2_fra_v_t3 and is2_issue_sel_buf4(3)) ; + +iu_fu_is2_frb_v <= (i_afd_is2_frb_v_t0 and is2_issue_sel_buf4(0)) or + (i_afd_is2_frb_v_t1 and is2_issue_sel_buf4(1)) or + (i_afd_is2_frb_v_t2 and is2_issue_sel_buf4(2)) or + (i_afd_is2_frb_v_t3 and is2_issue_sel_buf4(3)) ; + +iu_fu_is2_frc_v <= (i_afd_is2_frc_v_t0 and is2_issue_sel_buf4(0)) or + (i_afd_is2_frc_v_t1 and is2_issue_sel_buf4(1)) or + (i_afd_is2_frc_v_t2 and is2_issue_sel_buf4(2)) or + (i_afd_is2_frc_v_t3 and is2_issue_sel_buf4(3)) ; + + + +iu_fu_is2_instr_match <= (i_axu_is2_instr_match_t0 and is2_issue_sel_buf4(0)) or + (i_axu_is2_instr_match_t1 and is2_issue_sel_buf4(1)) or + (i_axu_is2_instr_match_t2 and is2_issue_sel_buf4(2)) or + (i_axu_is2_instr_match_t3 and is2_issue_sel_buf4(3)) ; + + + + +-- Early decode for special fmul, ending for sp and dp fdiv/fsqrt + +iu_fu_is2_ucfmul <= iu_fu_is2_instr(0 to 2) = "111" and iu_fu_is2_instr(4 to 5) = "11" and + iu_fu_is2_instr(26 to 30) = "10001"; + + + +-- "ORing" i_afd_ignore_flush_is2_t* gets is_ucode to go active during the original ppc instruction. Otherwise it +-- would never go active on the special cases where the ucode instructions get blocked. + is2_is_ucode <= (i_afd_is2_is_ucode_t0 and is2_issue_sel_buf4(0)) or + (i_afd_is2_is_ucode_t1 and is2_issue_sel_buf4(1)) or + (i_afd_is2_is_ucode_t2 and is2_issue_sel_buf4(2)) or + (i_afd_is2_is_ucode_t3 and is2_issue_sel_buf4(3)) ; + +is2_ifar_t0 <= i_afd_is2_ifar_t0; +is2_ifar_t1 <= i_afd_is2_ifar_t1; +is2_ifar_t2 <= i_afd_is2_ifar_t2; +is2_ifar_t3 <= i_afd_is2_ifar_t3; + + +is2_ifar <= (is2_ifar_t0 and (0 to EFF_IFAR'length-1 => is2_issue_sel_buf4(0))) or + (is2_ifar_t1 and (0 to EFF_IFAR'length-1 => is2_issue_sel_buf4(1))) or + (is2_ifar_t2 and (0 to EFF_IFAR'length-1 => is2_issue_sel_buf4(2))) or + (is2_ifar_t3 and (0 to EFF_IFAR'length-1 => is2_issue_sel_buf4(3))) ; + + +iu_fu_is2_tid(0) <= is2_issue_sel(2) or is2_issue_sel(3); +iu_fu_is2_tid(1) <= is2_issue_sel(1) or is2_issue_sel(3); + + + + +hi_did3no0_d <= pri_rand(0) when (spr_fiss_pri_rand_always or (spr_fiss_pri_rand_flush and or_reduce(xu_iu_is2_flush(0 to 3)))) = '1' else hi_did3no0_din; +hi_did3no1_d <= pri_rand(1) when (spr_fiss_pri_rand_always or (spr_fiss_pri_rand_flush and or_reduce(xu_iu_is2_flush(0 to 3)))) = '1' else hi_did3no1_din; +hi_did3no2_d <= pri_rand(2) when (spr_fiss_pri_rand_always or (spr_fiss_pri_rand_flush and or_reduce(xu_iu_is2_flush(0 to 3)))) = '1' else hi_did3no2_din; +hi_did2no0_d <= pri_rand(3) when (spr_fiss_pri_rand_always or (spr_fiss_pri_rand_flush and or_reduce(xu_iu_is2_flush(0 to 3)))) = '1' else hi_did2no0_din; +hi_did2no1_d <= pri_rand(4) when (spr_fiss_pri_rand_always or (spr_fiss_pri_rand_flush and or_reduce(xu_iu_is2_flush(0 to 3)))) = '1' else hi_did2no1_din; +hi_did1no0_d <= pri_rand(5) when (spr_fiss_pri_rand_always or (spr_fiss_pri_rand_flush and or_reduce(xu_iu_is2_flush(0 to 3)))) = '1' else hi_did1no0_din; +md_did3no0_d <= pri_rand(0) when (spr_fiss_pri_rand_always or (spr_fiss_pri_rand_flush and or_reduce(xu_iu_is2_flush(0 to 3)))) = '1' else md_did3no0_din; +md_did3no1_d <= pri_rand(1) when (spr_fiss_pri_rand_always or (spr_fiss_pri_rand_flush and or_reduce(xu_iu_is2_flush(0 to 3)))) = '1' else md_did3no1_din; +md_did3no2_d <= pri_rand(2) when (spr_fiss_pri_rand_always or (spr_fiss_pri_rand_flush and or_reduce(xu_iu_is2_flush(0 to 3)))) = '1' else md_did3no2_din; +md_did2no0_d <= pri_rand(3) when (spr_fiss_pri_rand_always or (spr_fiss_pri_rand_flush and or_reduce(xu_iu_is2_flush(0 to 3)))) = '1' else md_did2no0_din; +md_did2no1_d <= pri_rand(4) when (spr_fiss_pri_rand_always or (spr_fiss_pri_rand_flush and or_reduce(xu_iu_is2_flush(0 to 3)))) = '1' else md_did2no1_din; +md_did1no0_d <= pri_rand(5) when (spr_fiss_pri_rand_always or (spr_fiss_pri_rand_flush and or_reduce(xu_iu_is2_flush(0 to 3)))) = '1' else md_did1no0_din; + +pri_rand(0 TO 5) <= "001000" when spr_fiss_pri_rand(0 to 4) = "00000" else + "100111" when spr_fiss_pri_rand(0 to 4) = "00001" else + "110111" when spr_fiss_pri_rand(0 to 4) = "00010" else + "000001" when spr_fiss_pri_rand(0 to 4) = "00011" else + "000110" when spr_fiss_pri_rand(0 to 4) = "00100" else + "001001" when spr_fiss_pri_rand(0 to 4) = "00101" else + "011000" when spr_fiss_pri_rand(0 to 4) = "00110" else + "111101" when spr_fiss_pri_rand(0 to 4) = "00111" else + "100101" when spr_fiss_pri_rand(0 to 4) = "01000" else + "010110" when spr_fiss_pri_rand(0 to 4) = "01001" else + "101101" when spr_fiss_pri_rand(0 to 4) = "01010" else + "111110" when spr_fiss_pri_rand(0 to 4) = "01011" else + "110110" when spr_fiss_pri_rand(0 to 4) = "01100" else + "101001" when spr_fiss_pri_rand(0 to 4) = "01101" else + "000000" when spr_fiss_pri_rand(0 to 4) = "01110" else + "111010" when spr_fiss_pri_rand(0 to 4) = "01111" else + "000111" when spr_fiss_pri_rand(0 to 4) = "10000" else + "111001" when spr_fiss_pri_rand(0 to 4) = "10001" else + "111000" when spr_fiss_pri_rand(0 to 4) = "10010" else + "011010" when spr_fiss_pri_rand(0 to 4) = "10011" else + "111111" when spr_fiss_pri_rand(0 to 4) = "10100" else + "010010" when spr_fiss_pri_rand(0 to 4) = "10101" else + "000010" when spr_fiss_pri_rand(0 to 4) = "10110" else + "000101" when spr_fiss_pri_rand(0 to 4) = "10111" else + "111111" when spr_fiss_pri_rand(0 to 4) = "11000" else + "000000" when spr_fiss_pri_rand(0 to 4) = "11001" else + "011010" when spr_fiss_pri_rand(0 to 4) = "11010" else + "100101" when spr_fiss_pri_rand(0 to 4) = "11011" else + "001001" when spr_fiss_pri_rand(0 to 4) = "11100" else + "110110" when spr_fiss_pri_rand(0 to 4) = "11101" else + "000111" when spr_fiss_pri_rand(0 to 4) = "11110" else + "111000" ; + + + + +---------------------------------------------------------------------------------- +---RF0 latches ------------------------------------------------------------------- +---------------------------------------------------------------------------------- + + rf0_took_latch: tri_rlmreg_p --init to 000001000001 + generic map (init => 65, expand_type => expand_type, needs_sreset => needs_sreset, width => 12) + port map ( + nclk => nclk, act => tiup, + vd => vdd, gd => gnd, + forcee => forcee, delay_lclkr => delay_lclkr, + thold_b => pc_iu_func_sl_thold_0_b, sg => pc_iu_sg_0, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + scin => rf0_took_latch_scin, + scout => rf0_took_latch_scout, + --------------------------------------------- + din(00) => hi_did3no0_d, + din(01) => hi_did3no1_d, + din(02) => hi_did3no2_d, + din(03) => hi_did2no0_d, + din(04) => hi_did2no1_d, + din(05) => hi_did1no0_d, + din(06) => md_did3no0_d, + din(07) => md_did3no1_d, + din(08) => md_did3no2_d, + din(09) => md_did2no0_d, + din(10) => md_did2no1_d, + din(11) => md_did1no0_d, + + --------------------------------------------- + dout(00) => hi_did3no0, + dout(01) => hi_did3no1, + dout(02) => hi_did3no2, + dout(03) => hi_did2no0, + dout(04) => hi_did2no1, + dout(05) => hi_did1no0, + dout(06) => md_did3no0, + dout(07) => md_did3no1, + dout(08) => md_did3no2, + dout(09) => md_did2no0, + dout(10) => md_did2no1, + dout(11) => md_did1no0 + + --------------------------------------------- + ); + + + +---------------------------------------------------------------------------------- + + +is2_act <= is2_instr_v or is2_act_l2; + +---------------------------------------------------------------------------------- + rf0_stage_latch: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 77+EFF_IFAR'length) + port map ( + nclk => nclk, act => is2_act, + vd => vdd, gd => gnd, + forcee => forcee, delay_lclkr => delay_lclkr, + thold_b => pc_iu_func_sl_thold_0_b, sg => pc_iu_sg_0, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + scin => rf0_stage_latch_scin, + scout => rf0_stage_latch_scout, + --------------------------------------------- + + din(00 to 31) => iu_fu_is2_instr(0 to 31), + din(32 ) => iu_fu_is2_instr_v, + din(33 ) => is2_is_ucode, + din(34 ) => iu_fu_is2_fra_v, + din(35 to 41) => iu_fu_is2_fra(0 to 6), + din(42 ) => iu_fu_is2_frb_v, + din(43 to 49) => iu_fu_is2_frb(0 to 6), + din(50 ) => iu_fu_is2_frc_v, + din(51 to 57) => iu_fu_is2_frc(0 to 6), + din(58 ) => iu_fu_is2_ucfmul, + din(59 to 65) => iu_fu_is2_frt(0 to 6), + din(66 ) => spare_l2(0), + din(67 ) => spare_l2(1), + din(68 ) => iu_fu_is2_instr_match, + din(69 to 70) => iu_fu_is2_tid(0 to 1), + din(71 to 76) => iu_fu_is2_bypsel_din(0 to 5), + din(77 to 76+EFF_IFAR'length) => is2_ifar, + + --------------------------------------------- + dout(00 to 31) => iu_fu_rf0_instr(0 to 31), + dout(32 ) => iu_fu_rf0_instr_v, + dout(33 ) => iu_fu_rf0_is_ucode, + dout(34 ) => iu_fu_rf0_fra_v, + dout(35 to 41) => iu_fu_rf0_fra(0 to 6), + dout(42 ) => iu_fu_rf0_frb_v, + dout(43 to 49) => iu_fu_rf0_frb(0 to 6), + dout(50 ) => iu_fu_rf0_frc_v, + dout(51 to 57) => iu_fu_rf0_frc(0 to 6), + dout(58 ) => iu_fu_rf0_ucfmul, + dout(59 to 65) => iu_fu_rf0_frt(0 to 6), + dout(66 to 67) => spare_l2(0 to 1), + dout(68 ) => iu_fu_rf0_instr_match, + dout(69 to 70) => rf0_tid(0 to 1), + dout(71 to 76) => iu_fu_rf0_bypsel(0 to 5), + dout(77 to 76+EFF_IFAR'length) => rf0_ifar + + --------------------------------------------- + ); + +iu_fu_rf0_ifar <= rf0_ifar; +iu_fu_rf0_tid <= rf0_tid; + +spare_unused(0 to 1) <= tidn & tidn; + +---------------------------------------------------------------------------------- + + + + + --shadow pipe latches + --------------------------------------------- + --------------------------------------------- + + rf0_wpc_sp_latch: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 5) + port map ( + nclk => nclk, act => tiup, + vd => vdd, gd => gnd, + forcee => forcee, delay_lclkr => delay_lclkr, + thold_b => pc_iu_func_sl_thold_0_b, sg => pc_iu_sg_0, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + scin => rf0_wpc_sp_latch_scin, + scout => rf0_wpc_sp_latch_scout , + --------------------------------------------- + din(0) => is2_act_din, + din(1) => spare_l2(2), + din(2) => spare_l2(3), + din(3) => spare_l2(4), + din(4) => spare_l2(5), + + --------------------------------------------- + dout(0) => is2_act_l2, + dout(1) => spare_l2(2), + dout(2) => spare_l2(3), + dout(3) => spare_l2(4), + dout(4) => spare_l2(5) + + --------------------------------------------- + ); + + disable_cgat <= i_afd_config_iucr_t0(4) or i_afd_config_iucr_t1(4) or i_afd_config_iucr_t2(4) or i_afd_config_iucr_t3(4); + is2_act_din <= is2_instr_v or disable_cgat; + + spare_unused(2) <= d_mode; + spare_unused(3 to 6) <= tidn & tidn & tidn & tidn; + spare_unused(8) <= tidn; + +---------------------------------------------------------------------------------- + debug_reg: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 5) + port map ( + nclk => nclk, act => tiup, + vd => vdd, gd => gnd, + forcee => forcee, delay_lclkr => delay_lclkr, + thold_b => pc_iu_func_sl_thold_0_b, sg => pc_iu_sg_0, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + scin => debug_reg_scin, + scout => debug_reg_scout, + --------------------------------------------- + din(0 to 3) => is2_issue_sel(0 to 3), + din(4) => spare_l2(6), + + --------------------------------------------- + dout(0 to 3) => is2_issue_sel_db(0 to 3), + dout(4) => spare_l2(6) + + --------------------------------------------- + ); + +spare_unused(7) <= tidn; + +---------------------------------------------------------------------------------- + + + + + +single_step_mode <= i_afd_config_iucr_t0(2) and i_afd_config_iucr_t1(2) and i_afd_config_iucr_t2(2) and i_afd_config_iucr_t3(2); +single_step_divsqrt_mode <= i_afd_config_iucr_t0(3) and i_afd_config_iucr_t1(3) and i_afd_config_iucr_t2(3) and i_afd_config_iucr_t3(3); + +divsqrt_mode <= ((not i_afd_in_ucode_mode_or1d_b_t0) or + (not i_afd_in_ucode_mode_or1d_b_t1) or + (not i_afd_in_ucode_mode_or1d_b_t2) or + (not i_afd_in_ucode_mode_or1d_b_t3)); + +-- this inserts a bubble in the pipe following the fp operation + is2_insert_one_bubble <= '0'; -- reserved + spare_unused(09) <= is2_insert_one_bubble; + + is2_insert_two_bubbles <= '0'; -- reserved + spare_unused(10) <= is2_insert_two_bubbles; + + -- this inserts 3 bubbles in the pipe following the fp operation + is2_insert_three_bubbles <= ((ifdp_is2_est_bubble3_t0 and is2_issue_sel(0)) or + (ifdp_is2_est_bubble3_t1 and is2_issue_sel(1)) or + (ifdp_is2_est_bubble3_t2 and is2_issue_sel(2)) or + (ifdp_is2_est_bubble3_t3 and is2_issue_sel(3))); + + is2_insert_seven_bubbles <= (single_step_mode and or_reduce(is2_issue_sel(0 to 3))) or + (single_step_divsqrt_mode and or_reduce(is2_issue_sel(0 to 3)) and divsqrt_mode); + + + +skip_din(0) <= or_reduce(bubble_din(2 to 4)); +skip_din(1) <= or_reduce(bubble_din(2 to 4)); +skip_din(2) <= or_reduce(bubble_din(2 to 4)); +skip_din(3) <= or_reduce(bubble_din(2 to 4)); + + + +--@@ ESPRESSO TABLE START @@ +-- .i 5 +-- .o 3 +-- .ilb is2_insert_three_bubbles is2_insert_seven_bubbles bubble_dout(2) bubble_dout(3) bubble_dout(4) +-- .ob bubble_din(2) bubble_din(3) bubble_din(4) +-- .type fd +--# +--#3 7 234 234 +-- ####################################################################### +-- 0 0 111 110 +-- 0 0 110 101 +-- 0 0 101 100 +-- 0 0 100 011 +-- 0 0 011 010 +-- 0 0 010 001 +-- 0 0 001 000 +-- 0 0 000 000 +-- +-- 1 0 --- 011 +-- 0 1 --- 111 +-- 1 1 --- 111 + + +-- ####################################################################### +-- .e +--@@ ESPRESSO TABLE END @@ + +--@@ ESPRESSO LOGIC START @@ +-- logic generated on: Mon May 5 10:46:28 2008 +bubble_din(2) <= (not is2_insert_three_bubbles and bubble_dout(2) + and bubble_dout(3)) or + (not is2_insert_three_bubbles and bubble_dout(2) + and bubble_dout(4)) or + ( is2_insert_seven_bubbles); + +bubble_din(3) <= ( bubble_dout(2) and not bubble_dout(3) and not bubble_dout(4)) or + ( bubble_dout(3) and bubble_dout(4)) or + ( is2_insert_three_bubbles) or + ( is2_insert_seven_bubbles); + +bubble_din(4) <= ( bubble_dout(2) and not bubble_dout(4)) or + ( bubble_dout(3) and not bubble_dout(4)) or + ( is2_insert_three_bubbles) or + ( is2_insert_seven_bubbles); + +--@@ ESPRESSO LOGIC END @@ +-- + + + + +is2_bubble_latch: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 3) + port map ( + nclk => nclk, act => tiup, + vd => vdd, gd => gnd, + forcee => forcee, delay_lclkr => delay_lclkr, + thold_b => pc_iu_func_sl_thold_0_b, sg => pc_iu_sg_0, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + scin => is2_bubble_latch_scin, + scout => is2_bubble_latch_scout, + --------------------------------------------- + din(0 to 2) => bubble_din, + --------------------------------------------- + dout(0 to 2) => bubble_dout + --------------------------------------------- + ); + + + +is2_skip_latch: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, needs_sreset => needs_sreset, width => 4) + port map ( + nclk => nclk, act => tiup, + vd => vdd, gd => gnd, + forcee => forcee, delay_lclkr => delay_lclkr, + thold_b => pc_iu_func_sl_thold_0_b, sg => pc_iu_sg_0, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + scin => is2_skip_latch_scin, + scout => is2_skip_latch_scout, + --------------------------------------------- + din(0 to 3) => skip_din, + --------------------------------------------- + dout(0 to 3) => skip_dout + --------------------------------------------- + ); +---------------------------------------------------------------------------------- + + iu_fu_is2_bypsel <= (i_afd_is2_bypsel_t0 and (0 to 5 => is2_issue_sel_buf4(0))) or + (i_afd_is2_bypsel_t1 and (0 to 5 => is2_issue_sel_buf4(1))) or + (i_afd_is2_bypsel_t2 and (0 to 5 => is2_issue_sel_buf4(2))) or + (i_afd_is2_bypsel_t3 and (0 to 5 => is2_issue_sel_buf4(3))) ; + + + iu_fu_is2_bypsel_din <= iu_fu_is2_bypsel; + + + + +fu_iss_debug(0 to 23) <= highpri_v(0 to 3) & medpri_v(0 to 3) & + hi_did3no0 & + hi_did3no1 & + hi_did3no2 & + hi_did2no1 & + hi_did2no0 & + hi_did1no0 & + md_did3no0 & + md_did3no1 & + md_did3no2 & + md_did2no1 & + md_did2no0 & + md_did1no0 & + is2_issue_sel_db(0 to 3); + + + +-- scan chain *********************************************************************************** + +is2v_scin(0 to 3) <= i_iss_si & is2v_scout(0 to 2); +mask_scin(0 to 7) <= is2v_scout(3) & mask_scout(0 to 6); + +rf0_took_latch_scin(0 to 11) <= mask_scout(7) & rf0_took_latch_scout(0 to 10); + +rf0_stage_latch_scin(0 to 76+EFF_IFAR'length) <= rf0_took_latch_scout(11) & rf0_stage_latch_scout(0 to 75+EFF_IFAR'length); + +rf0_wpc_sp_latch_scin <= rf0_stage_latch_scout(76+EFF_IFAR'length) & rf0_wpc_sp_latch_scout(0 to 3); + + +debug_reg_scin(0 to 4) <= rf0_wpc_sp_latch_scout(4) & debug_reg_scout(0 to 3); + + +is2_bubble_latch_scin <= debug_reg_scout(4) & is2_bubble_latch_scout(0 to 1); +is2_skip_latch_scin <= is2_bubble_latch_scout(2) & is2_skip_latch_scout(0 to 2); + + +i_iss_so <= is2_skip_latch_scout(3) and an_ac_scan_dis_dc_b; + + +end iuq_axu_fu_iss; diff --git a/rel/src/vhdl/work/iuq_bd.vhdl b/rel/src/vhdl/work/iuq_bd.vhdl new file mode 100644 index 0000000..65bbd6f --- /dev/null +++ b/rel/src/vhdl/work/iuq_bd.vhdl @@ -0,0 +1,93 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +--******************************************************************** +--* +--* TITLE: IU Branch Decode +--* +--* NAME: iuq_bd.vhdl +--* +--********************************************************************* + +library ieee, ibm, support; + +use ieee.std_logic_1164.all; +use ibm.std_ulogic_support.all; + +entity iuq_bd is +port( + instruction : in std_ulogic_vector(0 to 31); + branch_decode : out std_ulogic_vector(0 to 3); + + bp_bc_en : in std_ulogic; + bp_bclr_en : in std_ulogic; + bp_bcctr_en : in std_ulogic; + bp_sw_en : in std_ulogic +); + +-- synopsys translate_off +-- synopsys translate_on +end iuq_bd; +---- +architecture iuq_bd of iuq_bd is + +signal b : std_ulogic; +signal bc : std_ulogic; +signal bclr : std_ulogic; +signal bcctr : std_ulogic; +signal br_val : std_ulogic; + +signal bo : std_ulogic_vector(0 to 4); +signal hint : std_ulogic; +signal hint_val : std_ulogic; + +signal unused_instruction : std_ulogic_vector(0 to 10); + +begin + +unused_instruction <= instruction(11 to 20) & instruction(31); + +b <= instruction(0 to 5) = "010010"; +bc <= bp_bc_en and instruction(0 to 5) = "010000"; +bclr <= bp_bclr_en and instruction(0 to 5) = "010011" and instruction(21 to 30) = "0000010000"; +bcctr <= bp_bcctr_en and instruction(0 to 5) = "010011" and instruction(21 to 30) = "1000010000"; + +br_val <= b or bc or bclr or bcctr; + +bo(0 to 4) <= instruction(6 to 10); + + +hint_val <= (bo(0) and bo(2)) or (bp_sw_en and ((bo(0) = '0' and bo(2) = '1' and bo(3) = '1') or + (bo(0) = '1' and bo(2) = '0' and bo(1) = '1'))); + +hint <= (bo(0) and bo(2)) or bo(4); + +branch_decode(0 to 3) <= br_val & b & hint_val & hint; + +end iuq_bd; diff --git a/rel/src/vhdl/work/iuq_bp.vhdl b/rel/src/vhdl/work/iuq_bp.vhdl new file mode 100644 index 0000000..b28f999 --- /dev/null +++ b/rel/src/vhdl/work/iuq_bp.vhdl @@ -0,0 +1,2735 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; +use ieee.std_logic_1164.all; + +library ibm; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; + +library support; +use support.power_logic_pkg.all; + +library tri; +use tri.tri_latches_pkg.all; + +library work; +use work.iuq_pkg.all; + +entity iuq_bp is +generic(expand_type : integer := 2 ); -- 0 = ibm umbra, 1 = xilinx, 2 = ibm mpg +port( + + bp_dbg_data0 : out std_ulogic_vector(0 to 87); + bp_dbg_data1 : out std_ulogic_vector(0 to 87); + + --in from bht + iu3_0_bh_rd_data : in std_ulogic_vector(0 to 1); + iu3_1_bh_rd_data : in std_ulogic_vector(0 to 1); + iu3_2_bh_rd_data : in std_ulogic_vector(0 to 1); + iu3_3_bh_rd_data : in std_ulogic_vector(0 to 1); + + --out to bht + iu1_bh_rd_addr : out std_ulogic_vector(0 to 7); + iu1_bh_rd_act : out std_ulogic; + ex6_bh_wr_data : out std_ulogic_vector(0 to 1); + ex6_bh_wr_addr : out std_ulogic_vector(0 to 7); + ex6_bh_wr_act : out std_ulogic_vector(0 to 3); + + --iu1 + ic_bp_iu1_val : in std_ulogic; + ic_bp_iu1_tid : in std_ulogic_vector(0 to 3); --unlatched version for timing, must latch before use + ic_bp_iu1_ifar : in std_ulogic_vector(52 to 59); + + + --iu3 + ic_bp_iu3_val : in std_ulogic_vector(0 to 3); + ic_bp_iu3_tid : in std_ulogic_vector(0 to 3); + ic_bp_iu3_ifar : in EFF_IFAR; + ic_bp_iu3_error : in std_ulogic_vector(0 to 2); + ic_bp_iu3_2ucode : in std_ulogic; + ic_bp_iu3_2ucode_type : in std_ulogic; + ic_bp_iu3_flush : in std_ulogic; + + --iu3 instruction(0:31) + predecode(32:35) + ic_bp_iu3_0_instr : in std_ulogic_vector(0 to 35); + ic_bp_iu3_1_instr : in std_ulogic_vector(0 to 35); + ic_bp_iu3_2_instr : in std_ulogic_vector(0 to 35); + ic_bp_iu3_3_instr : in std_ulogic_vector(0 to 35); + + --iu4 + bp_ib_iu4_t0_val : out std_ulogic_vector(0 to 3); + bp_ib_iu4_t1_val : out std_ulogic_vector(0 to 3); + bp_ib_iu4_t2_val : out std_ulogic_vector(0 to 3); + bp_ib_iu4_t3_val : out std_ulogic_vector(0 to 3); + bp_ib_iu4_ifar : out EFF_IFAR; + + --iu4 instruction(0:31) + prediction(32:34) + error(35:37) + 2ucode + 2ucode_type + gshare(40:43) + bp_ib_iu3_0_instr : out std_ulogic_vector(0 to 31); + bp_ib_iu4_0_instr : out std_ulogic_vector(32 to 43); + bp_ib_iu4_1_instr : out std_ulogic_vector(0 to 43); + bp_ib_iu4_2_instr : out std_ulogic_vector(0 to 43); + bp_ib_iu4_3_instr : out std_ulogic_vector(0 to 43); + + --iu5 hold/redirect + bp_ic_iu5_hold_tid : out std_ulogic_vector(0 to 3); + bp_ic_iu5_redirect_tid : out std_ulogic_vector(0 to 3); + bp_ic_iu5_redirect_ifar : out EFF_IFAR; + + --ex5 update + xu_iu_ex5_ifar : in EFF_IFAR; + xu_iu_ex5_tid : in std_ulogic_vector(0 to 3); + xu_iu_ex5_val : in std_ulogic; + xu_iu_ex5_br_update : in std_ulogic; + xu_iu_ex5_br_hist : in std_ulogic_vector(0 to 1); + xu_iu_ex5_br_taken : in std_ulogic; + xu_iu_ex5_bclr : in std_ulogic; + xu_iu_ex5_getNIA : in std_ulogic; + xu_iu_ex5_lk : in std_ulogic; + xu_iu_ex5_bh : in std_ulogic_vector(0 to 1); + xu_iu_ex5_gshare : in std_ulogic_vector(0 to 3); + + --flush conditions + xu_iu_iu3_flush_tid : in std_ulogic_vector(0 to 3); + xu_iu_iu4_flush_tid : in std_ulogic_vector(0 to 3); + xu_iu_iu5_flush_tid : in std_ulogic_vector(0 to 3); + xu_iu_ex5_flush_tid : in std_ulogic_vector(0 to 3); + ib_ic_iu5_redirect_tid : in std_ulogic_vector(0 to 3); + uc_flush_tid : in std_ulogic_vector(0 to 3); + + --config bits + spr_bp_config : in std_ulogic_vector(0 to 3); + spr_bp_gshare_mask : in std_ulogic_vector(0 to 3); + + --pervasive + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + an_ac_scan_dis_dc_b : in std_ulogic; + pc_iu_sg_2 : in std_ulogic; + pc_iu_func_sl_thold_2 : in std_ulogic; + clkoff_b : in std_ulogic; + tc_ac_ccflush_dc : in std_ulogic; + delay_lclkr : in std_ulogic; + mpw1_b : in std_ulogic; + scan_in : in std_ulogic_vector(0 to 1); + scan_out : out std_ulogic_vector(0 to 1) + +); + +-- synopsys translate_off + + +-- synopsys translate_on + +end iuq_bp; +---- +architecture iuq_bp of iuq_bp is + +---------------------------- +-- constants +---------------------------- + +--scan chain 0, ~473 latches +constant ic_bp_iu1_tid_offset : natural := 0; +constant gshare_t0_offset : natural := ic_bp_iu1_tid_offset + 4; +constant gshare_t1_offset : natural := gshare_t0_offset + 4; +constant gshare_t2_offset : natural := gshare_t1_offset + 4; +constant gshare_t3_offset : natural := gshare_t2_offset + 4; +constant cp_gshare_t0_offset : natural := gshare_t3_offset + 4; +constant cp_gshare_t1_offset : natural := cp_gshare_t0_offset + 4; +constant cp_gshare_t2_offset : natural := cp_gshare_t1_offset + 4; +constant cp_gshare_t3_offset : natural := cp_gshare_t2_offset + 4; +constant iu2_gshare_offset : natural := cp_gshare_t3_offset + 4; +constant iu3_gshare_offset : natural := iu2_gshare_offset + 4; +constant iu4_bh_offset : natural := iu3_gshare_offset + 4; +constant iu4_lk_offset : natural := iu4_bh_offset + 2; +constant iu4_aa_offset : natural := iu4_lk_offset + 1; +constant iu4_b_offset : natural := iu4_aa_offset + 1; +constant iu4_opcode_offset : natural := iu4_b_offset + 1; +constant iu4_excode_offset : natural := iu4_opcode_offset + 6; +constant iu4_bo_offset : natural := iu4_excode_offset + 10; +constant iu4_bi_offset : natural := iu4_bo_offset + 5; +constant iu4_tar_offset : natural := iu4_bi_offset + 5; +constant iu4_ifar_offset : natural := iu4_tar_offset + 24; +constant iu4_ifar_pri_offset : natural := iu4_ifar_offset + EFF_IFAR'length; +constant iu4_pr_taken_offset : natural := iu4_ifar_pri_offset + 2; +constant iu4_tid_offset : natural := iu4_pr_taken_offset + 4; +constant iu4_t0_val_offset : natural := iu4_tid_offset + 4; +constant iu4_t1_val_offset : natural := iu4_t0_val_offset + 4; +constant iu4_t2_val_offset : natural := iu4_t1_val_offset + 4; +constant iu4_t3_val_offset : natural := iu4_t2_val_offset + 4; +constant iu4_0_instr_offset : natural := iu4_t3_val_offset + 4; +constant iu4_1_instr_offset : natural := iu4_0_instr_offset + 12; +constant iu4_2_instr_offset : natural := iu4_1_instr_offset + 44; +constant iu4_3_instr_offset : natural := iu4_2_instr_offset + 44; +constant iu5_redirect_ifar_offset : natural := iu4_3_instr_offset + 44; +constant iu5_redirect_tid_offset : natural := iu5_redirect_ifar_offset + EFF_IFAR'length; +constant iu5_hold_tid_offset : natural := iu5_redirect_tid_offset + 4; +constant iu5_ls_push_offset : natural := iu5_hold_tid_offset + 4; +constant iu5_ls_pop_offset : natural := iu5_ls_push_offset + 4; +constant iu5_ifar_offset : natural := iu5_ls_pop_offset + 4; +constant scan_right0 : natural := iu5_ifar_offset + EFF_IFAR'length - 1; + +--scan chain 1, ~1115 latches +constant iu6_ls_t0_ptr_offset : natural := 0; +constant iu6_ls_t1_ptr_offset : natural := iu6_ls_t0_ptr_offset + 4; +constant iu6_ls_t2_ptr_offset : natural := iu6_ls_t1_ptr_offset + 4; +constant iu6_ls_t3_ptr_offset : natural := iu6_ls_t2_ptr_offset + 4; +constant iu6_ls_t00_offset : natural := iu6_ls_t3_ptr_offset + 4; +constant iu6_ls_t01_offset : natural := iu6_ls_t00_offset + EFF_IFAR'length; +constant iu6_ls_t02_offset : natural := iu6_ls_t01_offset + EFF_IFAR'length; +constant iu6_ls_t03_offset : natural := iu6_ls_t02_offset + EFF_IFAR'length; +constant iu6_ls_t10_offset : natural := iu6_ls_t03_offset + EFF_IFAR'length; +constant iu6_ls_t11_offset : natural := iu6_ls_t10_offset + EFF_IFAR'length; +constant iu6_ls_t12_offset : natural := iu6_ls_t11_offset + EFF_IFAR'length; +constant iu6_ls_t13_offset : natural := iu6_ls_t12_offset + EFF_IFAR'length; +constant iu6_ls_t20_offset : natural := iu6_ls_t13_offset + EFF_IFAR'length; +constant iu6_ls_t21_offset : natural := iu6_ls_t20_offset + EFF_IFAR'length; +constant iu6_ls_t22_offset : natural := iu6_ls_t21_offset + EFF_IFAR'length; +constant iu6_ls_t23_offset : natural := iu6_ls_t22_offset + EFF_IFAR'length; +constant iu6_ls_t30_offset : natural := iu6_ls_t23_offset + EFF_IFAR'length; +constant iu6_ls_t31_offset : natural := iu6_ls_t30_offset + EFF_IFAR'length; +constant iu6_ls_t32_offset : natural := iu6_ls_t31_offset + EFF_IFAR'length; +constant iu6_ls_t33_offset : natural := iu6_ls_t32_offset + EFF_IFAR'length; +constant ex6_val_offset : natural := iu6_ls_t33_offset + EFF_IFAR'length; +constant ex6_ifar_offset : natural := ex6_val_offset + 1; +constant ex6_tid_offset : natural := ex6_ifar_offset + EFF_IFAR'length; +constant ex6_br_update_offset : natural := ex6_tid_offset + 4; +constant ex6_br_hist_offset : natural := ex6_br_update_offset + 1; +constant ex6_br_taken_offset : natural := ex6_br_hist_offset + 2; +constant ex6_bclr_offset : natural := ex6_br_taken_offset + 1; +constant ex6_lk_offset : natural := ex6_bclr_offset + 1; +constant ex6_gshare_offset : natural := ex6_lk_offset + 1; +constant ex6_ls_push_offset : natural := ex6_gshare_offset + 4; +constant ex6_ls_pop_offset : natural := ex6_ls_push_offset + 4; +constant ex6_flush_tid_offset : natural := ex6_ls_pop_offset + 4; +constant ex7_ls_t0_ptr_offset : natural := ex6_flush_tid_offset + 4; +constant ex7_ls_t1_ptr_offset : natural := ex7_ls_t0_ptr_offset + 4; +constant ex7_ls_t2_ptr_offset : natural := ex7_ls_t1_ptr_offset + 4; +constant ex7_ls_t3_ptr_offset : natural := ex7_ls_t2_ptr_offset + 4; +constant bp_config_offset : natural := ex7_ls_t3_ptr_offset + 4; +constant gshare_mask_offset : natural := bp_config_offset + 4; +constant dft_offset : natural := gshare_mask_offset + 4; +constant spare_offset : natural := dft_offset + 1; +constant scan_right1 : natural := spare_offset + 12 - 1; + +signal spare_l2 : std_ulogic_vector(0 to 11); + +---------------------------- +-- signals +---------------------------- + +signal bp_dy_en : std_ulogic; +signal bp_st_en : std_ulogic; +signal bp_ti_en : std_ulogic; +signal bp_gs_en : std_ulogic; + +signal bp_config_d : std_ulogic_vector(0 to 3); +signal bp_config_q : std_ulogic_vector(0 to 3); + +signal iu1_bh_ti0gs1_rd_addr : std_ulogic_vector(0 to 7); +signal iu1_bh_ti1gs1_rd_addr : std_ulogic_vector(0 to 7); +signal iu1_gshare : std_ulogic_vector(0 to 3); +signal iu1_tid_enc : std_ulogic_vector(0 to 1); + +signal ex6_bh_ti0gs1_wr_addr : std_ulogic_vector(0 to 7); +signal ex6_bh_ti1gs1_wr_addr : std_ulogic_vector(0 to 7); +signal ex6_gshare : std_ulogic_vector(0 to 3); +signal ex6_tid_enc : std_ulogic_vector(0 to 1); + +signal gshare_act : std_ulogic_vector(0 to 3); +signal gshare_taken : std_ulogic_vector(0 to 3); + +signal gshare_t0_shift1 : std_ulogic_vector(0 to 4); +signal gshare_t0_shift2 : std_ulogic_vector(0 to 4); +signal gshare_t0_shift3 : std_ulogic_vector(0 to 4); +signal gshare_t0_shift4 : std_ulogic_vector(1 to 4); +signal gshare_t0_shift : std_ulogic_vector(1 to 4); + +signal gshare_t1_shift1 : std_ulogic_vector(0 to 4); +signal gshare_t1_shift2 : std_ulogic_vector(0 to 4); +signal gshare_t1_shift3 : std_ulogic_vector(0 to 4); +signal gshare_t1_shift4 : std_ulogic_vector(1 to 4); +signal gshare_t1_shift : std_ulogic_vector(1 to 4); + +signal gshare_t2_shift1 : std_ulogic_vector(0 to 4); +signal gshare_t2_shift2 : std_ulogic_vector(0 to 4); +signal gshare_t2_shift3 : std_ulogic_vector(0 to 4); +signal gshare_t2_shift4 : std_ulogic_vector(1 to 4); +signal gshare_t2_shift : std_ulogic_vector(1 to 4); + +signal gshare_t3_shift1 : std_ulogic_vector(0 to 4); +signal gshare_t3_shift2 : std_ulogic_vector(0 to 4); +signal gshare_t3_shift3 : std_ulogic_vector(0 to 4); +signal gshare_t3_shift4 : std_ulogic_vector(1 to 4); +signal gshare_t3_shift : std_ulogic_vector(1 to 4); + +signal cp_gshare_act : std_ulogic_vector(0 to 3); +signal cp_gshare_shift : std_ulogic_vector(0 to 3); +signal cp_gshare_taken : std_ulogic; +signal cp_gshare_t0_d : std_ulogic_vector(0 to 3); +signal cp_gshare_t0_q : std_ulogic_vector(0 to 3); +signal cp_gshare_t1_d : std_ulogic_vector(0 to 3); +signal cp_gshare_t1_q : std_ulogic_vector(0 to 3); +signal cp_gshare_t2_d : std_ulogic_vector(0 to 3); +signal cp_gshare_t2_q : std_ulogic_vector(0 to 3); +signal cp_gshare_t3_d : std_ulogic_vector(0 to 3); +signal cp_gshare_t3_q : std_ulogic_vector(0 to 3); + +signal gshare_t0_d : std_ulogic_vector(0 to 3); +signal gshare_t0_q : std_ulogic_vector(0 to 3); +signal gshare_t1_d : std_ulogic_vector(0 to 3); +signal gshare_t1_q : std_ulogic_vector(0 to 3); +signal gshare_t2_d : std_ulogic_vector(0 to 3); +signal gshare_t2_q : std_ulogic_vector(0 to 3); +signal gshare_t3_d : std_ulogic_vector(0 to 3); +signal gshare_t3_q : std_ulogic_vector(0 to 3); + +signal gshare_mask_d : std_ulogic_vector(0 to 3); +signal gshare_mask_q : std_ulogic_vector(0 to 3); + +signal iu2_gshare_d : std_ulogic_vector(0 to 3); +signal iu2_gshare_q : std_ulogic_vector(0 to 3); +signal iu3_gshare_d : std_ulogic_vector(0 to 3); +signal iu3_gshare_q : std_ulogic_vector(0 to 3); + + + +signal ic_bp_iu1_tid_d : std_ulogic_vector(0 to 3); +signal ic_bp_iu1_tid_q : std_ulogic_vector(0 to 3); + +signal iu3_0_br_hist : std_ulogic_vector(0 to 1); +signal iu3_1_br_hist : std_ulogic_vector(0 to 1); +signal iu3_2_br_hist : std_ulogic_vector(0 to 1); +signal iu3_3_br_hist : std_ulogic_vector(0 to 1); + +signal iu3_br_val : std_ulogic_vector(0 to 3); +signal iu3_br_hard : std_ulogic_vector(0 to 3); +signal iu3_hint_val : std_ulogic_vector(0 to 3); +signal iu3_hint : std_ulogic_vector(0 to 3); +signal iu3_br_hist0 : std_ulogic_vector(0 to 3); +signal iu3_br_hist1 : std_ulogic_vector(0 to 3); + +signal iu3_br_update : std_ulogic_vector(0 to 3); +signal iu3_br_dynamic : std_ulogic_vector(0 to 3); +signal iu3_br_static : std_ulogic_vector(0 to 3); +signal iu3_br_pred : std_ulogic_vector(0 to 3); + +signal iu3_instr_pri : std_ulogic_vector(0 to 31); +signal iu3_instr_val : std_ulogic_vector(0 to 3); + + +signal iu4_b_d : std_ulogic; +signal iu4_b_q : std_ulogic; +signal iu4_bd : EFF_IFAR; +signal iu4_li : EFF_IFAR; + +signal iu3_flush_tid : std_ulogic_vector(0 to 3); + +signal iu4_act : std_ulogic; +signal iu4_instr_act : std_ulogic_vector(0 to 3); + +signal iu4_br_update : std_ulogic_vector(0 to 3); +signal iu4_br_pred : std_ulogic_vector(0 to 3); + +signal iu4_bh_d : std_ulogic_vector(0 to 1); +signal iu4_bh_q : std_ulogic_vector(0 to 1); +signal iu4_lk_d : std_ulogic; +signal iu4_lk_q : std_ulogic; +signal iu4_aa_d : std_ulogic; +signal iu4_aa_q : std_ulogic; + + +signal iu4_opcode_d : std_ulogic_vector(0 to 5); +signal iu4_opcode_q : std_ulogic_vector(0 to 5); +signal iu4_excode_d : std_ulogic_vector(21 to 30); +signal iu4_excode_q : std_ulogic_vector(21 to 30); +signal iu4_bclr : std_ulogic; +signal iu4_bcctr : std_ulogic; + +signal iu4_bo_d : std_ulogic_vector(6 to 10); +signal iu4_bo_q : std_ulogic_vector(6 to 10); +signal iu4_bi_d : std_ulogic_vector(11 to 15); +signal iu4_bi_q : std_ulogic_vector(11 to 15); +signal iu4_getNIA : std_ulogic; + +signal iu4_tar_d : std_ulogic_vector(6 to 29); +signal iu4_tar_q : std_ulogic_vector(6 to 29); +signal iu4_abs : EFF_IFAR; + +signal iu4_ifar_d : EFF_IFAR; +signal iu4_ifar_q : EFF_IFAR; +signal iu4_ifar_pri_d : std_ulogic_vector(60 to 61); +signal iu4_ifar_pri_q : std_ulogic_vector(60 to 61); + +signal iu4_off : EFF_IFAR; + +signal iu4_bta : EFF_IFAR; +signal iu4_lnk : EFF_IFAR; + +signal iu4_pr_taken_d : std_ulogic_vector(0 to 3); +signal iu4_pr_taken_q : std_ulogic_vector(0 to 3); + +signal iu4_tid_d : std_ulogic_vector(0 to 3); +signal iu4_tid_q : std_ulogic_vector(0 to 3); + + +signal iu4_t0_val_d : std_ulogic_vector(0 to 3); +signal iu4_t0_val_q : std_ulogic_vector(0 to 3); +signal iu4_t1_val_d : std_ulogic_vector(0 to 3); +signal iu4_t1_val_q : std_ulogic_vector(0 to 3); +signal iu4_t2_val_d : std_ulogic_vector(0 to 3); +signal iu4_t2_val_q : std_ulogic_vector(0 to 3); +signal iu4_t3_val_d : std_ulogic_vector(0 to 3); +signal iu4_t3_val_q : std_ulogic_vector(0 to 3); + + +signal iu4_0_instr_d : std_ulogic_vector(0 to 43); +signal iu4_0_instr_q : std_ulogic_vector(32 to 43); +signal iu4_1_instr_d : std_ulogic_vector(0 to 43); +signal iu4_1_instr_q : std_ulogic_vector(0 to 43); +signal iu4_2_instr_d : std_ulogic_vector(0 to 43); +signal iu4_2_instr_q : std_ulogic_vector(0 to 43); +signal iu4_3_instr_d : std_ulogic_vector(0 to 43); +signal iu4_3_instr_q : std_ulogic_vector(0 to 43); + +signal iu4_flush_tid : std_ulogic_vector(0 to 3); +signal iu4_redirect_tid : std_ulogic_vector(0 to 3); + + + + +signal iu5_flush_tid : std_ulogic_vector(0 to 3); + +signal iu5_redirect_ifar_d : EFF_IFAR; +signal iu5_redirect_ifar_q : EFF_IFAR; +signal iu5_redirect_tid_d : std_ulogic_vector(0 to 3); +signal iu5_redirect_tid_q : std_ulogic_vector(0 to 3); +signal iu5_redirect_act : std_ulogic; + +signal iu5_hold_tid_d : std_ulogic_vector(0 to 3); +signal iu5_hold_tid_q : std_ulogic_vector(0 to 3); + +signal iu5_act : std_ulogic; + +signal iu5_ls_push_d : std_ulogic_vector(0 to 3); +signal iu5_ls_push_q : std_ulogic_vector(0 to 3); +signal iu5_ls_pop_d : std_ulogic_vector(0 to 3); +signal iu5_ls_pop_q : std_ulogic_vector(0 to 3); + +signal iu5_ifar_d : EFF_IFAR; +signal iu5_ifar_q : EFF_IFAR; + +signal ex6_ifar_d : EFF_IFAR; +signal ex6_ifar_q : EFF_IFAR; +signal ex6_tid_d : std_ulogic_vector(0 to 3); +signal ex6_tid_q : std_ulogic_vector(0 to 3); +signal ex6_val_d : std_ulogic; +signal ex6_val_q : std_ulogic; +signal ex6_br_update_d : std_ulogic; +signal ex6_br_update_q : std_ulogic; +signal ex6_br_hist_d : std_ulogic_vector(0 to 1); +signal ex6_br_hist_q : std_ulogic_vector(0 to 1); +signal ex6_br_taken_d : std_ulogic; +signal ex6_br_taken_q : std_ulogic; +signal ex6_bclr_d : std_ulogic; +signal ex6_bclr_q : std_ulogic; +signal ex6_getNIA_d : std_ulogic; +signal ex6_lk_d : std_ulogic; +signal ex6_lk_q : std_ulogic; +signal ex6_bh_d : std_ulogic_vector(0 to 1); +signal ex6_gshare_d : std_ulogic_vector(0 to 3); +signal ex6_gshare_q : std_ulogic_vector(0 to 3); + +signal ex6_ls_push_d : std_ulogic_vector(0 to 3); +signal ex6_ls_push_q : std_ulogic_vector(0 to 3); +signal ex6_ls_pop_d : std_ulogic_vector(0 to 3); +signal ex6_ls_pop_q : std_ulogic_vector(0 to 3); + +signal ex7_ls_t0_ptr_d : std_ulogic_vector(0 to 3); +signal ex7_ls_t0_ptr_q : std_ulogic_vector(0 to 3); +signal ex7_ls_t1_ptr_d : std_ulogic_vector(0 to 3); +signal ex7_ls_t1_ptr_q : std_ulogic_vector(0 to 3); +signal ex7_ls_t2_ptr_d : std_ulogic_vector(0 to 3); +signal ex7_ls_t2_ptr_q : std_ulogic_vector(0 to 3); +signal ex7_ls_t3_ptr_d : std_ulogic_vector(0 to 3); +signal ex7_ls_t3_ptr_q : std_ulogic_vector(0 to 3); +signal ex7_ls_ptr_act : std_ulogic_vector(0 to 3); + +signal ex6_flush_tid_d : std_ulogic_vector(0 to 3); +signal ex6_flush_tid_q : std_ulogic_vector(0 to 3); + +signal ex6_br_hist_dec : std_ulogic; +signal ex6_br_hist_inc : std_ulogic; + +signal ex6_flush : std_ulogic; +signal ex6_val : std_ulogic; + +signal iu6_ls_t0_ptr_d : std_ulogic_vector(0 to 3); +signal iu6_ls_t0_ptr_q : std_ulogic_vector(0 to 3); +signal iu6_ls_t1_ptr_d : std_ulogic_vector(0 to 3); +signal iu6_ls_t1_ptr_q : std_ulogic_vector(0 to 3); +signal iu6_ls_t2_ptr_d : std_ulogic_vector(0 to 3); +signal iu6_ls_t2_ptr_q : std_ulogic_vector(0 to 3); +signal iu6_ls_t3_ptr_d : std_ulogic_vector(0 to 3); +signal iu6_ls_t3_ptr_q : std_ulogic_vector(0 to 3); +signal iu6_ls_ptr_act : std_ulogic_vector(0 to 3); + +signal iu5_ls_update : std_ulogic_vector(0 to 3); +signal ex6_ls_update : std_ulogic_vector(0 to 3); +signal ex6_repair : std_ulogic_vector(0 to 3); + +signal iu5_nia : EFF_IFAR; +signal ex6_nia : EFF_IFAR; + +signal iu6_ls_t00_d : EFF_IFAR; +signal iu6_ls_t00_q : EFF_IFAR; +signal iu6_ls_t01_d : EFF_IFAR; +signal iu6_ls_t01_q : EFF_IFAR; +signal iu6_ls_t02_d : EFF_IFAR; +signal iu6_ls_t02_q : EFF_IFAR; +signal iu6_ls_t03_d : EFF_IFAR; +signal iu6_ls_t03_q : EFF_IFAR; +signal iu6_ls_t0_act : std_ulogic_vector(0 to 3); + +signal iu6_ls_t10_d : EFF_IFAR; +signal iu6_ls_t10_q : EFF_IFAR; +signal iu6_ls_t11_d : EFF_IFAR; +signal iu6_ls_t11_q : EFF_IFAR; +signal iu6_ls_t12_d : EFF_IFAR; +signal iu6_ls_t12_q : EFF_IFAR; +signal iu6_ls_t13_d : EFF_IFAR; +signal iu6_ls_t13_q : EFF_IFAR; +signal iu6_ls_t1_act : std_ulogic_vector(0 to 3); + +signal iu6_ls_t20_d : EFF_IFAR; +signal iu6_ls_t20_q : EFF_IFAR; +signal iu6_ls_t21_d : EFF_IFAR; +signal iu6_ls_t21_q : EFF_IFAR; +signal iu6_ls_t22_d : EFF_IFAR; +signal iu6_ls_t22_q : EFF_IFAR; +signal iu6_ls_t23_d : EFF_IFAR; +signal iu6_ls_t23_q : EFF_IFAR; +signal iu6_ls_t2_act : std_ulogic_vector(0 to 3); + +signal iu6_ls_t30_d : EFF_IFAR; +signal iu6_ls_t30_q : EFF_IFAR; +signal iu6_ls_t31_d : EFF_IFAR; +signal iu6_ls_t31_q : EFF_IFAR; +signal iu6_ls_t32_d : EFF_IFAR; +signal iu6_ls_t32_q : EFF_IFAR; +signal iu6_ls_t33_d : EFF_IFAR; +signal iu6_ls_t33_q : EFF_IFAR; +signal iu6_ls_t3_act : std_ulogic_vector(0 to 3); + +signal tiup : std_ulogic; + + +signal pc_iu_func_sl_thold_1 : std_ulogic; +signal pc_iu_func_sl_thold_0 : std_ulogic; +signal pc_iu_func_sl_thold_0_b : std_ulogic; +signal pc_iu_sg_1 : std_ulogic; +signal pc_iu_sg_0 : std_ulogic; +signal forcee : std_ulogic; + +signal dclk : std_ulogic; +signal lclk : clk_logic; +signal dft_q : std_ulogic_vector(0 to 0); + +signal siv0 : std_ulogic_vector(0 to scan_right0); +signal sov0 : std_ulogic_vector(0 to scan_right0); + +signal siv1 : std_ulogic_vector(0 to scan_right1); +signal sov1 : std_ulogic_vector(0 to scan_right1); + +signal act_dis : std_ulogic; +signal d_mode : std_ulogic; +signal mpw2_b : std_ulogic; + + +begin + + +tiup <= '1'; + +act_dis <= '0'; +d_mode <= '0'; +mpw2_b <= '1'; + +------------------------------------------------- +-- config bits +------------------------------------------------- + +bp_config_d(0 to 3) <= spr_bp_config(0 to 3); + +bp_dy_en <= bp_config_q(0); --dynamic prediction enable default = 1 +bp_st_en <= bp_config_q(1); --static prediction enable default = 0 +bp_ti_en <= bp_config_q(2); --thread isolation enable default = 1 +bp_gs_en <= bp_config_q(3); --gshare enable default = 0 + +------------------------------------------------- +-- latched xu interface +------------------------------------------------- + +ex6_flush_tid_d <= xu_iu_ex5_flush_tid; + +ex6_ifar_d <= xu_iu_ex5_ifar; +ex6_tid_d <= xu_iu_ex5_tid; +ex6_val_d <= xu_iu_ex5_val; +ex6_br_update_d <= xu_iu_ex5_br_update; +ex6_br_hist_d <= xu_iu_ex5_br_hist; +ex6_br_taken_d <= xu_iu_ex5_br_taken; +ex6_bclr_d <= xu_iu_ex5_bclr; +ex6_getNIA_d <= xu_iu_ex5_getNIA; +ex6_lk_d <= xu_iu_ex5_lk; +ex6_bh_d <= xu_iu_ex5_bh; +ex6_gshare_d <= xu_iu_ex5_gshare; + +------------------------------------------------- +-- read branch history table +------------------------------------------------- + +iu1_bh_rd_act <= ic_bp_iu1_val; + + + +iu1_bh_ti0gs1_rd_addr(0 to 7) <= (ic_bp_iu1_ifar(52 to 55) xor iu1_gshare(0 to 3)) & ic_bp_iu1_ifar(56 to 59); +iu1_bh_ti1gs1_rd_addr(0 to 7) <= iu1_tid_enc(0 to 1) & (ic_bp_iu1_ifar(54 to 57) xor iu1_gshare(0 to 3)) & ic_bp_iu1_ifar(58 to 59); + +iu1_bh_rd_addr(0 to 7) <= gate(iu1_bh_ti0gs1_rd_addr(0 to 7), bp_ti_en = '0') or + gate(iu1_bh_ti1gs1_rd_addr(0 to 7), bp_ti_en = '1') ; + +ic_bp_iu1_tid_d <= ic_bp_iu1_tid; + +iu1_gshare(0 to 3) <= gate(gshare_t0_q(0 to 3), bp_gs_en and ic_bp_iu1_tid_q(0)) or + gate(gshare_t1_q(0 to 3), bp_gs_en and ic_bp_iu1_tid_q(1)) or + gate(gshare_t2_q(0 to 3), bp_gs_en and ic_bp_iu1_tid_q(2)) or + gate(gshare_t3_q(0 to 3), bp_gs_en and ic_bp_iu1_tid_q(3)); + +iu1_tid_enc(0 to 1) <= gate("00", ic_bp_iu1_tid_q(0)) or + gate("01", ic_bp_iu1_tid_q(1)) or + gate("10", ic_bp_iu1_tid_q(2)) or + gate("11", ic_bp_iu1_tid_q(3)); + +iu2_gshare_d(0 to 3) <= iu1_gshare(0 to 3); +iu3_gshare_d(0 to 3) <= iu2_gshare_q(0 to 3); + +------------------------------------------------- +-- write branch history table +------------------------------------------------- + +ex6_bh_ti0gs1_wr_addr(0 to 7) <= (ex6_ifar_q(52 to 55) xor ex6_gshare(0 to 3)) & ex6_ifar_q(56 to 59); +ex6_bh_ti1gs1_wr_addr(0 to 7) <= ex6_tid_enc(0 to 1) & (ex6_ifar_q(54 to 57) xor ex6_gshare(0 to 3)) & ex6_ifar_q(58 to 59); + +ex6_bh_wr_addr(0 to 7) <= gate(ex6_bh_ti0gs1_wr_addr(0 to 7), bp_ti_en = '0') or + gate(ex6_bh_ti1gs1_wr_addr(0 to 7), bp_ti_en = '1') ; + + +ex6_gshare(0 to 3) <= ex6_gshare_q(0 to 3); + +ex6_tid_enc(0 to 1) <= gate("00", ex6_tid_q(0)) or + gate("01", ex6_tid_q(1)) or + gate("10", ex6_tid_q(2)) or + gate("11", ex6_tid_q(3)); + +------------------------------------------------- +-- update branch hitstory +------------------------------------------------- + +ex6_flush <= or_reduce(ex6_tid_q(0 to 3) and ex6_flush_tid_q(0 to 3)); +ex6_val <= not ex6_flush; + +ex6_br_hist_dec <= ex6_val and ex6_val_q = '1' and ex6_br_update_q = '1' and ex6_br_taken_q = '0' and ex6_br_hist_q(0 to 1) /= "00"; +ex6_br_hist_inc <= ex6_val and ex6_val_q = '1' and ex6_br_update_q = '1' and ex6_br_taken_q = '1' and ex6_br_hist_q(0 to 1) /= "11"; + +ex6_bh_wr_data(0 to 1) <= ex6_br_hist_q(0 to 1) + 1 when ex6_br_taken_q = '1' else + ex6_br_hist_q(0 to 1) - 1; + +ex6_bh_wr_act(0) <= (ex6_br_hist_dec or ex6_br_hist_inc) and ex6_ifar_q(60 to 61) = "00"; +ex6_bh_wr_act(1) <= (ex6_br_hist_dec or ex6_br_hist_inc) and ex6_ifar_q(60 to 61) = "01"; +ex6_bh_wr_act(2) <= (ex6_br_hist_dec or ex6_br_hist_inc) and ex6_ifar_q(60 to 61) = "10"; +ex6_bh_wr_act(3) <= (ex6_br_hist_dec or ex6_br_hist_inc) and ex6_ifar_q(60 to 61) = "11"; + +------------------------------------------------- +-- update global history +------------------------------------------------- + +gshare_mask_d(0 to 3) <= spr_bp_gshare_mask(0 to 3); + + + + + + + +gshare_t0_shift1(0 to 4) <= "01000" when (iu4_t0_val_q(0) and iu4_br_update(0)) = '1' else "10000"; +gshare_t0_shift2(0 to 4) <= '0' & gshare_t0_shift1(0 to 3) when (iu4_t0_val_q(1) and iu4_br_update(1)) = '1' else gshare_t0_shift1(0 to 4); +gshare_t0_shift3(0 to 4) <= '0' & gshare_t0_shift2(0 to 3) when (iu4_t0_val_q(2) and iu4_br_update(2)) = '1' else gshare_t0_shift2(0 to 4); +gshare_t0_shift4(1 to 4) <= gshare_t0_shift3(0 to 3) when (iu4_t0_val_q(3) and iu4_br_update(3)) = '1' else gshare_t0_shift3(1 to 4); +gshare_t0_shift(1 to 4) <= gate( gshare_t0_shift4(1 to 4), not iu4_flush_tid(0)); + +gshare_t1_shift1(0 to 4) <= "01000" when (iu4_t1_val_q(0) and iu4_br_update(0)) = '1' else "10000"; +gshare_t1_shift2(0 to 4) <= '0' & gshare_t1_shift1(0 to 3) when (iu4_t1_val_q(1) and iu4_br_update(1)) = '1' else gshare_t1_shift1(0 to 4); +gshare_t1_shift3(0 to 4) <= '0' & gshare_t1_shift2(0 to 3) when (iu4_t1_val_q(2) and iu4_br_update(2)) = '1' else gshare_t1_shift2(0 to 4); +gshare_t1_shift4(1 to 4) <= gshare_t1_shift3(0 to 3) when (iu4_t1_val_q(3) and iu4_br_update(3)) = '1' else gshare_t1_shift3(1 to 4); +gshare_t1_shift(1 to 4) <= gate( gshare_t1_shift4(1 to 4), not iu4_flush_tid(1)); + +gshare_t2_shift1(0 to 4) <= "01000" when (iu4_t2_val_q(0) and iu4_br_update(0)) = '1' else "10000"; +gshare_t2_shift2(0 to 4) <= '0' & gshare_t2_shift1(0 to 3) when (iu4_t2_val_q(1) and iu4_br_update(1)) = '1' else gshare_t2_shift1(0 to 4); +gshare_t2_shift3(0 to 4) <= '0' & gshare_t2_shift2(0 to 3) when (iu4_t2_val_q(2) and iu4_br_update(2)) = '1' else gshare_t2_shift2(0 to 4); +gshare_t2_shift4(1 to 4) <= gshare_t2_shift3(0 to 3) when (iu4_t2_val_q(3) and iu4_br_update(3)) = '1' else gshare_t2_shift3(1 to 4); +gshare_t2_shift(1 to 4) <= gate( gshare_t2_shift4(1 to 4), not iu4_flush_tid(2)); + +gshare_t3_shift1(0 to 4) <= "01000" when (iu4_t3_val_q(0) and iu4_br_update(0)) = '1' else "10000"; +gshare_t3_shift2(0 to 4) <= '0' & gshare_t3_shift1(0 to 3) when (iu4_t3_val_q(1) and iu4_br_update(1)) = '1' else gshare_t3_shift1(0 to 4); +gshare_t3_shift3(0 to 4) <= '0' & gshare_t3_shift2(0 to 3) when (iu4_t3_val_q(2) and iu4_br_update(2)) = '1' else gshare_t3_shift2(0 to 4); +gshare_t3_shift4(1 to 4) <= gshare_t3_shift3(0 to 3) when (iu4_t3_val_q(3) and iu4_br_update(3)) = '1' else gshare_t3_shift3(1 to 4); +gshare_t3_shift(1 to 4) <= gate( gshare_t3_shift4(1 to 4), not iu4_flush_tid(3)); + +gshare_taken(0) <= or_reduce(iu4_t0_val_q(0 to 3) and iu4_br_update(0 to 3) and iu4_br_pred(0 to 3)); +gshare_taken(1) <= or_reduce(iu4_t1_val_q(0 to 3) and iu4_br_update(0 to 3) and iu4_br_pred(0 to 3)); +gshare_taken(2) <= or_reduce(iu4_t2_val_q(0 to 3) and iu4_br_update(0 to 3) and iu4_br_pred(0 to 3)); +gshare_taken(3) <= or_reduce(iu4_t3_val_q(0 to 3) and iu4_br_update(0 to 3) and iu4_br_pred(0 to 3)); + + + + + +gshare_t0_d(0 to 3) <= cp_gshare_t0_d(0 to 3) when ex6_repair(0) = '1' else + (gshare_taken(0) & "000" ) and gshare_mask_q(0 to 3) when gshare_t0_shift(4) = '1' else + (gshare_taken(0) & "00" & gshare_t0_q(0) ) and gshare_mask_q(0 to 3) when gshare_t0_shift(3) = '1' else + (gshare_taken(0) & '0' & gshare_t0_q(0 to 1)) and gshare_mask_q(0 to 3) when gshare_t0_shift(2) = '1' else + (gshare_taken(0) & gshare_t0_q(0 to 2)) and gshare_mask_q(0 to 3) when gshare_t0_shift(1) = '1' else + gshare_t0_q(0 to 3); + +gshare_t1_d(0 to 3) <= cp_gshare_t1_d(0 to 3) when ex6_repair(1) = '1' else + (gshare_taken(1) & "000" ) and gshare_mask_q(0 to 3) when gshare_t1_shift(4) = '1' else + (gshare_taken(1) & "00" & gshare_t1_q(0) ) and gshare_mask_q(0 to 3) when gshare_t1_shift(3) = '1' else + (gshare_taken(1) & '0' & gshare_t1_q(0 to 1)) and gshare_mask_q(0 to 3) when gshare_t1_shift(2) = '1' else + (gshare_taken(1) & gshare_t1_q(0 to 2)) and gshare_mask_q(0 to 3) when gshare_t1_shift(1) = '1' else + gshare_t1_q(0 to 3); + +gshare_t2_d(0 to 3) <= cp_gshare_t2_d(0 to 3) when ex6_repair(2) = '1' else + (gshare_taken(2) & "000" ) and gshare_mask_q(0 to 3) when gshare_t2_shift(4) = '1' else + (gshare_taken(2) & "00" & gshare_t2_q(0) ) and gshare_mask_q(0 to 3) when gshare_t2_shift(3) = '1' else + (gshare_taken(2) & '0' & gshare_t2_q(0 to 1)) and gshare_mask_q(0 to 3) when gshare_t2_shift(2) = '1' else + (gshare_taken(2) & gshare_t2_q(0 to 2)) and gshare_mask_q(0 to 3) when gshare_t2_shift(1) = '1' else + gshare_t2_q(0 to 3); +gshare_t3_d(0 to 3) <= cp_gshare_t3_d(0 to 3) when ex6_repair(3) = '1' else + (gshare_taken(3) & "000" ) and gshare_mask_q(0 to 3) when gshare_t3_shift(4) = '1' else + (gshare_taken(3) & "00" & gshare_t3_q(0) ) and gshare_mask_q(0 to 3) when gshare_t3_shift(3) = '1' else + (gshare_taken(3) & '0' & gshare_t3_q(0 to 1)) and gshare_mask_q(0 to 3) when gshare_t3_shift(2) = '1' else + (gshare_taken(3) & gshare_t3_q(0 to 2)) and gshare_mask_q(0 to 3) when gshare_t3_shift(1) = '1' else + gshare_t3_q(0 to 3); + + +gshare_act(0) <= tiup; +gshare_act(1) <= tiup; +gshare_act(2) <= tiup; +gshare_act(3) <= tiup; + + + + +--completion gshare repair +cp_gshare_shift(0 to 3) <= gate(ex6_tid_q(0 to 3) and not ex6_flush_tid_q(0 to 3), ex6_val_q and ex6_br_update_q); +cp_gshare_taken <= ex6_br_taken_q; + +cp_gshare_t0_d(0 to 3) <= (cp_gshare_taken & cp_gshare_t0_q(0 to 2)) and gshare_mask_q(0 to 3) when cp_gshare_shift(0) = '1' else + cp_gshare_t0_q(0 to 3); +cp_gshare_t1_d(0 to 3) <= (cp_gshare_taken & cp_gshare_t1_q(0 to 2)) and gshare_mask_q(0 to 3) when cp_gshare_shift(1) = '1' else + cp_gshare_t1_q(0 to 3); +cp_gshare_t2_d(0 to 3) <= (cp_gshare_taken & cp_gshare_t2_q(0 to 2)) and gshare_mask_q(0 to 3) when cp_gshare_shift(2) = '1' else + cp_gshare_t2_q(0 to 3); +cp_gshare_t3_d(0 to 3) <= (cp_gshare_taken & cp_gshare_t3_q(0 to 2)) and gshare_mask_q(0 to 3) when cp_gshare_shift(3) = '1' else + cp_gshare_t3_q(0 to 3); + + +cp_gshare_act(0 to 3) <= cp_gshare_shift(0 to 3); + +--------------------------------------------------- +---- branch history table +--------------------------------------------------- + +-- TBD...external ports for now + + + +with ic_bp_iu3_ifar(60 to 61) select +iu3_0_br_hist <= iu3_3_bh_rd_data(0 to 1) when "11", + iu3_2_bh_rd_data(0 to 1) when "10", + iu3_1_bh_rd_data(0 to 1) when "01", + iu3_0_bh_rd_data(0 to 1) when others; + +with ic_bp_iu3_ifar(60 to 61) select +iu3_1_br_hist <= iu3_3_bh_rd_data(0 to 1) when "10", + iu3_2_bh_rd_data(0 to 1) when "01", + iu3_1_bh_rd_data(0 to 1) when others; + +with ic_bp_iu3_ifar(60 to 61) select +iu3_2_br_hist <= iu3_3_bh_rd_data(0 to 1) when "01", + iu3_2_bh_rd_data(0 to 1) when others; + +iu3_3_br_hist <= iu3_3_bh_rd_data(0 to 1); + + +------------------------------------------------- +-- predict branches +------------------------------------------------- + +iu3_br_val(0 to 3) <= ic_bp_iu3_0_instr(32) & ic_bp_iu3_1_instr(32) & ic_bp_iu3_2_instr(32) & ic_bp_iu3_3_instr(32); +iu3_br_hard(0 to 3) <= ic_bp_iu3_0_instr(33) & ic_bp_iu3_1_instr(33) & ic_bp_iu3_2_instr(33) & ic_bp_iu3_3_instr(33); +iu3_hint_val(0 to 3) <= ic_bp_iu3_0_instr(34) & ic_bp_iu3_1_instr(34) & ic_bp_iu3_2_instr(34) & ic_bp_iu3_3_instr(34); +iu3_hint(0 to 3) <= ic_bp_iu3_0_instr(35) & ic_bp_iu3_1_instr(35) & ic_bp_iu3_2_instr(35) & ic_bp_iu3_3_instr(35); + +iu3_br_hist0(0 to 3) <= iu3_0_br_hist(0) & iu3_1_br_hist(0) & iu3_2_br_hist(0) & iu3_3_br_hist(0); +iu3_br_hist1(0 to 3) <= iu3_0_br_hist(1) & iu3_1_br_hist(1) & iu3_2_br_hist(1) & iu3_3_br_hist(1); + + + + +iu3_br_dynamic(0 to 3) <= gate(not(iu3_br_hard(0 to 3) or iu3_hint_val(0 to 3)), bp_dy_en); +iu3_br_static(0 to 3) <= gate(not(iu3_br_hard(0 to 3) or iu3_hint_val(0 to 3)), bp_st_en and not bp_dy_en); + +iu3_br_pred(0 to 3) <= iu3_br_val(0 to 3) and + (iu3_br_hard(0 to 3) or + (iu3_hint_val(0 to 3) and iu3_hint(0 to 3)) or + (iu3_br_dynamic(0 to 3) and iu3_br_hist0(0 to 3)) or + (iu3_br_static(0 to 3))); + +iu3_br_update(0 to 3) <= iu3_br_val(0 to 3) and iu3_br_dynamic(0 to 3); + +------------------------------------------------- +-- prioritize branch instructions +------------------------------------------------- + +iu3_instr_pri(0 to 31) <= ic_bp_iu3_0_instr(0 to 31) when iu3_br_pred(0) = '1' else + ic_bp_iu3_1_instr(0 to 31) when iu3_br_pred(1) = '1' else + ic_bp_iu3_2_instr(0 to 31) when iu3_br_pred(2) = '1' else + ic_bp_iu3_3_instr(0 to 31); + +iu4_b_d <= ic_bp_iu3_0_instr(33) when iu3_br_pred(0) = '1' else + ic_bp_iu3_1_instr(33) when iu3_br_pred(1) = '1' else + ic_bp_iu3_2_instr(33) when iu3_br_pred(2) = '1' else + ic_bp_iu3_3_instr(33); + +iu4_ifar_pri_d(60 to 61) <= ic_bp_iu3_ifar(60 to 61) when iu3_br_pred(0) = '1' else + ic_bp_iu3_ifar(60 to 61) + 1 when iu3_br_pred(1) = '1' else + ic_bp_iu3_ifar(60 to 61) + 2 when iu3_br_pred(2) = '1' else + ic_bp_iu3_ifar(60 to 61) + 3; + + +------------------------------------------------- +-- decode priority branch instruction +------------------------------------------------- + + + +iu4_tar_d(6 to 29) <= iu3_instr_pri(6 to 29); + + +sign_extend: for i in EFF_IFAR'left to 61 generate +begin + bd0:if(i < 48) generate begin iu4_bd(i) <= iu4_tar_q(16); end generate; + bd1:if(i > 47) generate begin iu4_bd(i) <= iu4_tar_q(i - 32); end generate; + li0:if(i < 38) generate begin iu4_li(i) <= iu4_tar_q(6); end generate; + li1:if(i > 37) generate begin iu4_li(i) <= iu4_tar_q(i - 32); end generate; +end generate; + +iu4_bh_d(0 to 1) <= iu3_instr_pri(19 to 20); +iu4_lk_d <= iu3_instr_pri(31); +iu4_aa_d <= iu3_instr_pri(30); + + +iu4_opcode_d(0 to 5) <= iu3_instr_pri(0 to 5); +iu4_excode_d(21 to 30) <= iu3_instr_pri(21 to 30); + +iu4_bclr <= (iu4_opcode_q(0 to 5) = "010011" and iu4_excode_q(21 to 30) = "0000010000") or dft_q(0); +iu4_bcctr <= iu4_opcode_q(0 to 5) = "010011" and iu4_excode_q(21 to 30) = "1000010000"; + +-- bcl 20,31,$+4 is special case. not a subroutine call, used to get next instruction address, should not be placed on link stack. +iu4_bo_d( 6 to 10) <= iu3_instr_pri( 6 to 10); +iu4_bi_d(11 to 15) <= iu3_instr_pri(11 to 15); + +iu4_getNIA <= iu4_opcode_q(0 to 5) = "010000" and + iu4_bo_q(6 to 10) = "10100" and + iu4_bi_q(11 to 15) = "11111" and + iu4_bd(EFF_IFAR'left to 61) = 1 and + iu4_aa_q = '0' and + iu4_lk_q = '1' ; + +--use pr_taken to validate control signals in iu4 +iu4_pr_taken_d(0) <= ic_bp_iu3_tid(0) and not iu3_flush_tid(0) and or_reduce(iu3_br_pred(0 to 3) and ic_bp_iu3_val(0 to 3)); +iu4_pr_taken_d(1) <= ic_bp_iu3_tid(1) and not iu3_flush_tid(1) and or_reduce(iu3_br_pred(0 to 3) and ic_bp_iu3_val(0 to 3)); +iu4_pr_taken_d(2) <= ic_bp_iu3_tid(2) and not iu3_flush_tid(2) and or_reduce(iu3_br_pred(0 to 3) and ic_bp_iu3_val(0 to 3)); +iu4_pr_taken_d(3) <= ic_bp_iu3_tid(3) and not iu3_flush_tid(3) and or_reduce(iu3_br_pred(0 to 3) and ic_bp_iu3_val(0 to 3)); + + + + +------------------------------------------------- +-- calculate branch target address +------------------------------------------------- + +iu4_abs(EFF_IFAR'left to 61) <= iu4_li(EFF_IFAR'left to 61) when iu4_b_q = '1' else + iu4_bd(EFF_IFAR'left to 61); + +iu4_off(EFF_IFAR'left to 61) <= iu4_abs(EFF_IFAR'left to 61) + (iu4_ifar_q(EFF_IFAR'left to 59) & iu4_ifar_pri_q(60 to 61)); + +iu4_bta(EFF_IFAR'left to 61) <= iu4_abs(EFF_IFAR'left to 61) when iu4_aa_q = '1' else + iu4_off(EFF_IFAR'left to 61); + +------------------------------------------------- +-- forward validated instructions +------------------------------------------------- + +iu4_act <= ic_bp_iu3_val(0); +iu4_instr_act(0 to 3) <= ic_bp_iu3_val(0 to 3); + +iu4_tid_d(0 to 3) <= ic_bp_iu3_tid(0 to 3); +iu4_ifar_d(EFF_IFAR'left to 61) <= ic_bp_iu3_ifar(EFF_IFAR'left to 61); + + + +iu3_instr_val(0) <= ic_bp_iu3_val(0); +iu3_instr_val(1) <= ic_bp_iu3_val(1) and not iu3_br_pred(0); +iu3_instr_val(2) <= ic_bp_iu3_val(2) and not iu3_br_pred(0) and not iu3_br_pred(1); +iu3_instr_val(3) <= ic_bp_iu3_val(3) and not iu3_br_pred(0) and not iu3_br_pred(1) and not iu3_br_pred(2); + + + +iu4_t0_val_d(0 to 3) <= gate(iu3_instr_val(0 to 3), ic_bp_iu3_tid(0) and not iu3_flush_tid(0)); +iu4_t1_val_d(0 to 3) <= gate(iu3_instr_val(0 to 3), ic_bp_iu3_tid(1) and not iu3_flush_tid(1)); +iu4_t2_val_d(0 to 3) <= gate(iu3_instr_val(0 to 3), ic_bp_iu3_tid(2) and not iu3_flush_tid(2)); +iu4_t3_val_d(0 to 3) <= gate(iu3_instr_val(0 to 3), ic_bp_iu3_tid(3) and not iu3_flush_tid(3)); + + +iu4_0_instr_d(0 to 31) <= ic_bp_iu3_0_instr(0 to 31); +iu4_1_instr_d(0 to 31) <= ic_bp_iu3_1_instr(0 to 31); +iu4_2_instr_d(0 to 31) <= ic_bp_iu3_2_instr(0 to 31); +iu4_3_instr_d(0 to 31) <= ic_bp_iu3_3_instr(0 to 31); + +iu4_0_instr_d(32) <= iu3_br_pred(0); +iu4_1_instr_d(32) <= iu3_br_pred(1); +iu4_2_instr_d(32) <= iu3_br_pred(2); +iu4_3_instr_d(32) <= iu3_br_pred(3); + +iu4_0_instr_d(33) <= iu3_br_hist1(0); +iu4_1_instr_d(33) <= iu3_br_hist1(1); +iu4_2_instr_d(33) <= iu3_br_hist1(2); +iu4_3_instr_d(33) <= iu3_br_hist1(3); + +iu4_0_instr_d(34) <= iu3_br_update(0); +iu4_1_instr_d(34) <= iu3_br_update(1); +iu4_2_instr_d(34) <= iu3_br_update(2); +iu4_3_instr_d(34) <= iu3_br_update(3); + +iu4_0_instr_d(35 to 37) <= ic_bp_iu3_error(0 to 2); +iu4_1_instr_d(35 to 37) <= ic_bp_iu3_error(0 to 2); +iu4_2_instr_d(35 to 37) <= ic_bp_iu3_error(0 to 2); +iu4_3_instr_d(35 to 37) <= ic_bp_iu3_error(0 to 2); + +iu4_0_instr_d(38) <= ic_bp_iu3_2ucode; +iu4_1_instr_d(38) <= ic_bp_iu3_2ucode; +iu4_2_instr_d(38) <= ic_bp_iu3_2ucode; +iu4_3_instr_d(38) <= ic_bp_iu3_2ucode; + +iu4_0_instr_d(39) <= ic_bp_iu3_2ucode_type; +iu4_1_instr_d(39) <= ic_bp_iu3_2ucode_type; +iu4_2_instr_d(39) <= ic_bp_iu3_2ucode_type; +iu4_3_instr_d(39) <= ic_bp_iu3_2ucode_type; + +iu4_0_instr_d(40 to 43) <= iu3_gshare_q(0 to 3); +iu4_1_instr_d(40 to 43) <= iu3_gshare_q(0 to 3); +iu4_2_instr_d(40 to 43) <= iu3_gshare_q(0 to 3); +iu4_3_instr_d(40 to 43) <= iu3_gshare_q(0 to 3); + + +iu4_br_pred(0 to 3) <= iu4_0_instr_q(32) & iu4_1_instr_q(32) & iu4_2_instr_q(32) & iu4_3_instr_q(32); +iu4_br_update(0 to 3) <= iu4_0_instr_q(34) & iu4_1_instr_q(34) & iu4_2_instr_q(34) & iu4_3_instr_q(34); + +------------------------------------------------- +-- detect incoming flushes +------------------------------------------------- + + + +iu3_flush_tid(0 to 3) <= xu_iu_iu3_flush_tid(0 to 3) or (0 to 3 => ic_bp_iu3_flush) or iu4_redirect_tid(0 to 3) or + iu5_redirect_tid_q(0 to 3) or ib_ic_iu5_redirect_tid(0 to 3) or uc_flush_tid(0 to 3) ; + + +iu4_flush_tid(0 to 3) <= xu_iu_iu4_flush_tid(0 to 3) or iu5_redirect_tid_q(0 to 3) or ib_ic_iu5_redirect_tid(0 to 3) or uc_flush_tid(0 to 3); + + +iu5_flush_tid(0 to 3) <= xu_iu_iu5_flush_tid(0 to 3) or ib_ic_iu5_redirect_tid(0 to 3) or uc_flush_tid(0 to 3); + + + +------------------------------------------------- +-- ex link stack pointers +------------------------------------------------- + +--valid can be concurrent with flush +ex6_ls_push_d(0 to 3) <= gate(ex6_tid_d(0 to 3) and not ex6_flush_tid_d(0 to 3), ex6_val_d and ex6_br_taken_d and not ex6_bclr_d and ex6_lk_d and not ex6_getNIA_d); +ex6_ls_pop_d(0 to 3) <= gate(ex6_tid_d(0 to 3) and not ex6_flush_tid_d(0 to 3), ex6_val_d and ex6_br_taken_d and ex6_bclr_d and ex6_bh_d(0 to 1) = "00"); + +--use ptr_d signal later...cannot eliminate feedback path +ex7_ls_t0_ptr_d(0 to 3) <= ex7_ls_t0_ptr_q(3) & ex7_ls_t0_ptr_q(0 to 2) when ex6_ls_push_q(0) = '1' and ex6_ls_pop_q(0) = '0' else + ex7_ls_t0_ptr_q(1 to 3) & ex7_ls_t0_ptr_q(0) when ex6_ls_push_q(0) = '0' and ex6_ls_pop_q(0) = '1' else + ex7_ls_t0_ptr_q(0 to 3); +ex7_ls_t1_ptr_d(0 to 3) <= ex7_ls_t1_ptr_q(3) & ex7_ls_t1_ptr_q(0 to 2) when ex6_ls_push_q(1) = '1' and ex6_ls_pop_q(1) = '0' else + ex7_ls_t1_ptr_q(1 to 3) & ex7_ls_t1_ptr_q(0) when ex6_ls_push_q(1) = '0' and ex6_ls_pop_q(1) = '1' else + ex7_ls_t1_ptr_q(0 to 3); +ex7_ls_t2_ptr_d(0 to 3) <= ex7_ls_t2_ptr_q(3) & ex7_ls_t2_ptr_q(0 to 2) when ex6_ls_push_q(2) = '1' and ex6_ls_pop_q(2) = '0' else + ex7_ls_t2_ptr_q(1 to 3) & ex7_ls_t2_ptr_q(0) when ex6_ls_push_q(2) = '0' and ex6_ls_pop_q(2) = '1' else + ex7_ls_t2_ptr_q(0 to 3); +ex7_ls_t3_ptr_d(0 to 3) <= ex7_ls_t3_ptr_q(3) & ex7_ls_t3_ptr_q(0 to 2) when ex6_ls_push_q(3) = '1' and ex6_ls_pop_q(3) = '0' else + ex7_ls_t3_ptr_q(1 to 3) & ex7_ls_t3_ptr_q(0) when ex6_ls_push_q(3) = '0' and ex6_ls_pop_q(3) = '1' else + ex7_ls_t3_ptr_q(0 to 3); + +ex7_ls_ptr_act(0 to 3) <= ex6_ls_push_q(0 to 3) xor ex6_ls_pop_q(0 to 3); + +------------------------------------------------- +-- iu link stack pointers +------------------------------------------------- +iu5_ls_push_d(0 to 3) <= gate(iu4_pr_taken_q(0 to 3) and not iu4_flush_tid(0 to 3), not iu4_bclr and iu4_lk_q and not iu4_getNIA); +iu5_ls_pop_d(0 to 3) <= gate(iu4_pr_taken_q(0 to 3) and not iu4_flush_tid(0 to 3), iu4_bclr and iu4_bh_q(0 to 1) = "00"); + +ex6_repair(0 to 3) <= gate(ex6_tid_q(0 to 3) and not ex6_flush_tid_q(0 to 3), ex6_val_q and (ex6_br_taken_q xor ex6_br_hist_q(0))) or + ex6_flush_tid_q(0 to 3); + +--use ptr_d signal later...cannot eliminate feedback path + +iu6_ls_t0_ptr_d(0 to 3) <= ex7_ls_t0_ptr_d(0 to 3) when ex6_repair(0) = '1' else + iu6_ls_t0_ptr_q(3) & iu6_ls_t0_ptr_q(0 to 2) when iu5_ls_push_q(0) = '1' and iu5_ls_pop_q(0) = '0' else + iu6_ls_t0_ptr_q(1 to 3) & iu6_ls_t0_ptr_q(0) when iu5_ls_push_q(0) = '0' and iu5_ls_pop_q(0) = '1' else + iu6_ls_t0_ptr_q(0 to 3); +iu6_ls_t1_ptr_d(0 to 3) <= ex7_ls_t1_ptr_d(0 to 3) when ex6_repair(1) = '1' else + iu6_ls_t1_ptr_q(3) & iu6_ls_t1_ptr_q(0 to 2) when iu5_ls_push_q(1) = '1' and iu5_ls_pop_q(1) = '0' else + iu6_ls_t1_ptr_q(1 to 3) & iu6_ls_t1_ptr_q(0) when iu5_ls_push_q(1) = '0' and iu5_ls_pop_q(1) = '1' else + iu6_ls_t1_ptr_q(0 to 3); +iu6_ls_t2_ptr_d(0 to 3) <= ex7_ls_t2_ptr_d(0 to 3) when ex6_repair(2) = '1' else + iu6_ls_t2_ptr_q(3) & iu6_ls_t2_ptr_q(0 to 2) when iu5_ls_push_q(2) = '1' and iu5_ls_pop_q(2) = '0' else + iu6_ls_t2_ptr_q(1 to 3) & iu6_ls_t2_ptr_q(0) when iu5_ls_push_q(2) = '0' and iu5_ls_pop_q(2) = '1' else + iu6_ls_t2_ptr_q(0 to 3); +iu6_ls_t3_ptr_d(0 to 3) <= ex7_ls_t3_ptr_d(0 to 3) when ex6_repair(3) = '1' else + iu6_ls_t3_ptr_q(3) & iu6_ls_t3_ptr_q(0 to 2) when iu5_ls_push_q(3) = '1' and iu5_ls_pop_q(3) = '0' else + iu6_ls_t3_ptr_q(1 to 3) & iu6_ls_t3_ptr_q(0) when iu5_ls_push_q(3) = '0' and iu5_ls_pop_q(3) = '1' else + iu6_ls_t3_ptr_q(0 to 3); + +iu6_ls_ptr_act(0 to 3) <= ex6_repair(0 to 3) or not ib_ic_iu5_redirect_tid(0 to 3); + +------------------------------------------------- +-- maintain link stack contents +------------------------------------------------- + +iu5_ls_update(0 to 3) <= iu5_ls_push_q(0 to 3) and not ib_ic_iu5_redirect_tid(0 to 3); +ex6_ls_update(0 to 3) <= gate(ex6_ls_push_q(0 to 3), not ex6_br_hist_q(0)); + +iu5_ifar_d(EFF_IFAR'left to 61) <= (iu4_ifar_q(EFF_IFAR'left to 59) & iu4_ifar_pri_q(60 to 61)); +iu5_act <= or_reduce(iu4_pr_taken_q(0 to 3)) and iu4_lk_q; + +iu5_nia(EFF_IFAR'left to 61) <= iu5_ifar_q(EFF_IFAR'left to 61) + 1; +ex6_nia(EFF_IFAR'left to 61) <= ex6_ifar_q(EFF_IFAR'left to 61) + 1; + + +iu6_ls_t00_d(EFF_IFAR'left to 61) <= ex6_nia(EFF_IFAR'left to 61) when ex6_ls_update(0) = '1' else + iu5_nia(EFF_IFAR'left to 61) when iu5_ls_update(0) = '1' else + iu6_ls_t00_q(EFF_IFAR'left to 61); +iu6_ls_t01_d(EFF_IFAR'left to 61) <= ex6_nia(EFF_IFAR'left to 61) when ex6_ls_update(0) = '1' else + iu5_nia(EFF_IFAR'left to 61) when iu5_ls_update(0) = '1' else + iu6_ls_t01_q(EFF_IFAR'left to 61); +iu6_ls_t02_d(EFF_IFAR'left to 61) <= ex6_nia(EFF_IFAR'left to 61) when ex6_ls_update(0) = '1' else + iu5_nia(EFF_IFAR'left to 61) when iu5_ls_update(0) = '1' else + iu6_ls_t02_q(EFF_IFAR'left to 61); +iu6_ls_t03_d(EFF_IFAR'left to 61) <= ex6_nia(EFF_IFAR'left to 61) when ex6_ls_update(0) = '1' else + iu5_nia(EFF_IFAR'left to 61) when iu5_ls_update(0) = '1' else + iu6_ls_t03_q(EFF_IFAR'left to 61); + +iu6_ls_t0_act(0 to 3) <= ex7_ls_t0_ptr_d(0 to 3) when ex6_ls_update(0) = '1' else + iu6_ls_t0_ptr_d(0 to 3) when iu5_ls_push_q(0) = '1' else + "0000"; + +iu6_ls_t10_d(EFF_IFAR'left to 61) <= ex6_nia(EFF_IFAR'left to 61) when ex6_ls_update(1) = '1' else + iu5_nia(EFF_IFAR'left to 61) when iu5_ls_update(1) = '1' else + iu6_ls_t10_q(EFF_IFAR'left to 61); +iu6_ls_t11_d(EFF_IFAR'left to 61) <= ex6_nia(EFF_IFAR'left to 61) when ex6_ls_update(1) = '1' else + iu5_nia(EFF_IFAR'left to 61) when iu5_ls_update(1) = '1' else + iu6_ls_t11_q(EFF_IFAR'left to 61); +iu6_ls_t12_d(EFF_IFAR'left to 61) <= ex6_nia(EFF_IFAR'left to 61) when ex6_ls_update(1) = '1' else + iu5_nia(EFF_IFAR'left to 61) when iu5_ls_update(1) = '1' else + iu6_ls_t12_q(EFF_IFAR'left to 61); +iu6_ls_t13_d(EFF_IFAR'left to 61) <= ex6_nia(EFF_IFAR'left to 61) when ex6_ls_update(1) = '1' else + iu5_nia(EFF_IFAR'left to 61) when iu5_ls_update(1) = '1' else + iu6_ls_t13_q(EFF_IFAR'left to 61); + +iu6_ls_t1_act(0 to 3) <= ex7_ls_t1_ptr_d(0 to 3) when ex6_ls_update(1) = '1' else + iu6_ls_t1_ptr_d(0 to 3) when iu5_ls_push_q(1) = '1' else + "0000"; + +iu6_ls_t20_d(EFF_IFAR'left to 61) <= ex6_nia(EFF_IFAR'left to 61) when ex6_ls_update(2) = '1' else + iu5_nia(EFF_IFAR'left to 61) when iu5_ls_update(2) = '1' else + iu6_ls_t20_q(EFF_IFAR'left to 61); +iu6_ls_t21_d(EFF_IFAR'left to 61) <= ex6_nia(EFF_IFAR'left to 61) when ex6_ls_update(2) = '1' else + iu5_nia(EFF_IFAR'left to 61) when iu5_ls_update(2) = '1' else + iu6_ls_t21_q(EFF_IFAR'left to 61); +iu6_ls_t22_d(EFF_IFAR'left to 61) <= ex6_nia(EFF_IFAR'left to 61) when ex6_ls_update(2) = '1' else + iu5_nia(EFF_IFAR'left to 61) when iu5_ls_update(2) = '1' else + iu6_ls_t22_q(EFF_IFAR'left to 61); +iu6_ls_t23_d(EFF_IFAR'left to 61) <= ex6_nia(EFF_IFAR'left to 61) when ex6_ls_update(2) = '1' else + iu5_nia(EFF_IFAR'left to 61) when iu5_ls_update(2) = '1' else + iu6_ls_t23_q(EFF_IFAR'left to 61); + +iu6_ls_t2_act(0 to 3) <= ex7_ls_t2_ptr_d(0 to 3) when ex6_ls_update(2) = '1' else + iu6_ls_t2_ptr_d(0 to 3) when iu5_ls_push_q(2) = '1' else + "0000"; + +iu6_ls_t30_d(EFF_IFAR'left to 61) <= ex6_nia(EFF_IFAR'left to 61) when ex6_ls_update(3) = '1' else + iu5_nia(EFF_IFAR'left to 61) when iu5_ls_update(3) = '1' else + iu6_ls_t30_q(EFF_IFAR'left to 61); +iu6_ls_t31_d(EFF_IFAR'left to 61) <= ex6_nia(EFF_IFAR'left to 61) when ex6_ls_update(3) = '1' else + iu5_nia(EFF_IFAR'left to 61) when iu5_ls_update(3) = '1' else + iu6_ls_t31_q(EFF_IFAR'left to 61); +iu6_ls_t32_d(EFF_IFAR'left to 61) <= ex6_nia(EFF_IFAR'left to 61) when ex6_ls_update(3) = '1' else + iu5_nia(EFF_IFAR'left to 61) when iu5_ls_update(3) = '1' else + iu6_ls_t32_q(EFF_IFAR'left to 61); +iu6_ls_t33_d(EFF_IFAR'left to 61) <= ex6_nia(EFF_IFAR'left to 61) when ex6_ls_update(3) = '1' else + iu5_nia(EFF_IFAR'left to 61) when iu5_ls_update(3) = '1' else + iu6_ls_t33_q(EFF_IFAR'left to 61); + +iu6_ls_t3_act(0 to 3) <= ex7_ls_t3_ptr_d(0 to 3) when ex6_ls_update(3) = '1' else + iu6_ls_t3_ptr_d(0 to 3) when iu5_ls_push_q(3) = '1' else + "0000"; + +------------------------------------------------- +-- mux out link address +------------------------------------------------- + +iu4_lnk(EFF_IFAR'left to 61) <= gate(iu6_ls_t00_q(EFF_IFAR'left to 61), iu4_tid_q(0) and iu6_ls_t0_ptr_q(0)) or + gate(iu6_ls_t01_q(EFF_IFAR'left to 61), iu4_tid_q(0) and iu6_ls_t0_ptr_q(1)) or + gate(iu6_ls_t02_q(EFF_IFAR'left to 61), iu4_tid_q(0) and iu6_ls_t0_ptr_q(2)) or + gate(iu6_ls_t03_q(EFF_IFAR'left to 61), iu4_tid_q(0) and iu6_ls_t0_ptr_q(3)) or + + gate(iu6_ls_t10_q(EFF_IFAR'left to 61), iu4_tid_q(1) and iu6_ls_t1_ptr_q(0)) or + gate(iu6_ls_t11_q(EFF_IFAR'left to 61), iu4_tid_q(1) and iu6_ls_t1_ptr_q(1)) or + gate(iu6_ls_t12_q(EFF_IFAR'left to 61), iu4_tid_q(1) and iu6_ls_t1_ptr_q(2)) or + gate(iu6_ls_t13_q(EFF_IFAR'left to 61), iu4_tid_q(1) and iu6_ls_t1_ptr_q(3)) or + + gate(iu6_ls_t20_q(EFF_IFAR'left to 61), iu4_tid_q(2) and iu6_ls_t2_ptr_q(0)) or + gate(iu6_ls_t21_q(EFF_IFAR'left to 61), iu4_tid_q(2) and iu6_ls_t2_ptr_q(1)) or + gate(iu6_ls_t22_q(EFF_IFAR'left to 61), iu4_tid_q(2) and iu6_ls_t2_ptr_q(2)) or + gate(iu6_ls_t23_q(EFF_IFAR'left to 61), iu4_tid_q(2) and iu6_ls_t2_ptr_q(3)) or + + gate(iu6_ls_t30_q(EFF_IFAR'left to 61), iu4_tid_q(3) and iu6_ls_t3_ptr_q(0)) or + gate(iu6_ls_t31_q(EFF_IFAR'left to 61), iu4_tid_q(3) and iu6_ls_t3_ptr_q(1)) or + gate(iu6_ls_t32_q(EFF_IFAR'left to 61), iu4_tid_q(3) and iu6_ls_t3_ptr_q(2)) or + gate(iu6_ls_t33_q(EFF_IFAR'left to 61), iu4_tid_q(3) and iu6_ls_t3_ptr_q(3)) ; + + +------------------------------------------------- +-- hold thread +------------------------------------------------- + + + + + +iu5_hold_tid_d(0) <= '0' when iu5_flush_tid(0) = '1' else + '1' when iu4_pr_taken_q(0) = '1' and not iu4_flush_tid(0) = '1' and iu4_bcctr = '1' else + iu5_hold_tid_q(0); + +iu5_hold_tid_d(1) <= '0' when iu5_flush_tid(1) = '1' else + '1' when iu4_pr_taken_q(1) = '1' and not iu4_flush_tid(1) = '1' and iu4_bcctr = '1' else + iu5_hold_tid_q(1); + +iu5_hold_tid_d(2) <= '0' when iu5_flush_tid(2) = '1' else + '1' when iu4_pr_taken_q(2) = '1' and not iu4_flush_tid(2) = '1' and iu4_bcctr = '1' else + iu5_hold_tid_q(2); + +iu5_hold_tid_d(3) <= '0' when iu5_flush_tid(3) = '1' else + '1' when iu4_pr_taken_q(3) = '1' and not iu4_flush_tid(3) = '1' and iu4_bcctr = '1' else + iu5_hold_tid_q(3); + +bp_ic_iu5_hold_tid(0 to 3) <= iu5_hold_tid_q(0 to 3); + +------------------------------------------------- +-- redirect instruction pointer +------------------------------------------------- + +iu5_redirect_act <= or_reduce(iu4_redirect_tid(0 to 3)); + +iu5_redirect_ifar_d(EFF_IFAR'left to 61) <= iu4_lnk(EFF_IFAR'left to 61) when iu4_bclr = '1' else + iu4_bta(EFF_IFAR'left to 61); + +iu4_redirect_tid(0 to 3) <= iu4_pr_taken_q(0 to 3); +iu5_redirect_tid_d(0 to 3) <= iu4_redirect_tid(0 to 3) and not iu4_flush_tid(0 to 3); + +bp_ic_iu5_redirect_ifar(EFF_IFAR'left to 61) <= iu5_redirect_ifar_q(EFF_IFAR'left to 61); +bp_ic_iu5_redirect_tid(0 to 3) <= iu5_redirect_tid_q(0 to 3); + +------------------------------------------------- +-- output validated instructions +------------------------------------------------- + + +bp_ib_iu4_ifar(EFF_IFAR'left to 61) <= iu4_ifar_q(EFF_IFAR'left to 61); + +bp_ib_iu4_t0_val(0 to 3) <= iu4_t0_val_q(0 to 3); +bp_ib_iu4_t1_val(0 to 3) <= iu4_t1_val_q(0 to 3); +bp_ib_iu4_t2_val(0 to 3) <= iu4_t2_val_q(0 to 3); +bp_ib_iu4_t3_val(0 to 3) <= iu4_t3_val_q(0 to 3); + +bp_ib_iu3_0_instr(0 to 31) <= iu4_0_instr_d(0 to 31); +bp_ib_iu4_0_instr(32 to 43) <= iu4_0_instr_q(32 to 43); +bp_ib_iu4_1_instr(0 to 43) <= iu4_1_instr_q(0 to 43); +bp_ib_iu4_2_instr(0 to 43) <= iu4_2_instr_q(0 to 43); +bp_ib_iu4_3_instr(0 to 43) <= iu4_3_instr_q(0 to 43); + + +------------------------------------------------- +-- debug +------------------------------------------------- +bp_dbg_data0(0 to 7) <= iu6_ls_t00_q(54 to 61); +bp_dbg_data0(8 to 15) <= iu6_ls_t01_q(54 to 61); +bp_dbg_data0(16 to 23) <= iu6_ls_t02_q(54 to 61); +bp_dbg_data0(24 to 31) <= iu6_ls_t03_q(54 to 61); + +bp_dbg_data0(32 to 39) <= iu6_ls_t10_q(54 to 61); +bp_dbg_data0(40 to 47) <= iu6_ls_t11_q(54 to 61); +bp_dbg_data0(48 to 55) <= iu6_ls_t12_q(54 to 61); +bp_dbg_data0(56 to 63) <= iu6_ls_t13_q(54 to 61); + +bp_dbg_data0(64 to 67) <= iu6_ls_t0_ptr_q; +bp_dbg_data0(68 to 71) <= iu6_ls_t1_ptr_q; +bp_dbg_data0(72 to 75) <= ex7_ls_t0_ptr_q; +bp_dbg_data0(76 to 79) <= ex7_ls_t1_ptr_q; + +bp_dbg_data0(80 to 83) <= ex6_tid_q; +bp_dbg_data0(84) <= ex6_val_q; +bp_dbg_data0(85) <= ex6_br_update_q; +bp_dbg_data0(86 to 87) <= ex6_br_hist_q(0 to 1); + +bp_dbg_data1(0 to 7) <= iu6_ls_t20_q(54 to 61); +bp_dbg_data1(8 to 15) <= iu6_ls_t21_q(54 to 61); +bp_dbg_data1(16 to 23) <= iu6_ls_t22_q(54 to 61); +bp_dbg_data1(24 to 31) <= iu6_ls_t23_q(54 to 61); + +bp_dbg_data1(32 to 39) <= iu6_ls_t30_q(54 to 61); +bp_dbg_data1(40 to 47) <= iu6_ls_t31_q(54 to 61); +bp_dbg_data1(48 to 55) <= iu6_ls_t32_q(54 to 61); +bp_dbg_data1(56 to 63) <= iu6_ls_t33_q(54 to 61); + +bp_dbg_data1(64 to 67) <= iu6_ls_t2_ptr_q; +bp_dbg_data1(68 to 71) <= iu6_ls_t3_ptr_q; +bp_dbg_data1(72 to 75) <= ex7_ls_t2_ptr_q; +bp_dbg_data1(76 to 79) <= ex7_ls_t3_ptr_q; + +bp_dbg_data1(80 to 83) <= ex6_gshare_q(0 to 3); +bp_dbg_data1(84) <= ex6_br_taken_q; +bp_dbg_data1(85) <= ex6_bclr_q; +bp_dbg_data1(86) <= ex6_lk_q; +bp_dbg_data1(87) <= '0'; + + +------------------------------------------------- +-- latches +------------------------------------------------- + +--scan chain 0 +ic_bp_iu1_tid_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(ic_bp_iu1_tid_offset to ic_bp_iu1_tid_offset+3), + scout => sov0(ic_bp_iu1_tid_offset to ic_bp_iu1_tid_offset+3), + din => ic_bp_iu1_tid_d(0 to 3), + dout => ic_bp_iu1_tid_q(0 to 3)); + +gshare_t0_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => gshare_act(0), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(gshare_t0_offset to gshare_t0_offset+3), + scout => sov0(gshare_t0_offset to gshare_t0_offset+3), + din => gshare_t0_d(0 to 3), + dout => gshare_t0_q(0 to 3)); + +gshare_t1_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => gshare_act(1), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(gshare_t1_offset to gshare_t1_offset+3), + scout => sov0(gshare_t1_offset to gshare_t1_offset+3), + din => gshare_t1_d(0 to 3), + dout => gshare_t1_q(0 to 3)); + +gshare_t2_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => gshare_act(2), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(gshare_t2_offset to gshare_t2_offset+3), + scout => sov0(gshare_t2_offset to gshare_t2_offset+3), + din => gshare_t2_d(0 to 3), + dout => gshare_t2_q(0 to 3)); + +gshare_t3_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => gshare_act(3), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(gshare_t3_offset to gshare_t3_offset+3), + scout => sov0(gshare_t3_offset to gshare_t3_offset+3), + din => gshare_t3_d(0 to 3), + dout => gshare_t3_q(0 to 3)); + +cp_gshare_t0_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cp_gshare_act(0), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(cp_gshare_t0_offset to cp_gshare_t0_offset+3), + scout => sov0(cp_gshare_t0_offset to cp_gshare_t0_offset+3), + din => cp_gshare_t0_d(0 to 3), + dout => cp_gshare_t0_q(0 to 3)); + +cp_gshare_t1_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cp_gshare_act(1), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(cp_gshare_t1_offset to cp_gshare_t1_offset+3), + scout => sov0(cp_gshare_t1_offset to cp_gshare_t1_offset+3), + din => cp_gshare_t1_d(0 to 3), + dout => cp_gshare_t1_q(0 to 3)); + +cp_gshare_t2_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cp_gshare_act(2), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(cp_gshare_t2_offset to cp_gshare_t2_offset+3), + scout => sov0(cp_gshare_t2_offset to cp_gshare_t2_offset+3), + din => cp_gshare_t2_d(0 to 3), + dout => cp_gshare_t2_q(0 to 3)); + +cp_gshare_t3_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cp_gshare_act(3), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(cp_gshare_t3_offset to cp_gshare_t3_offset+3), + scout => sov0(cp_gshare_t3_offset to cp_gshare_t3_offset+3), + din => cp_gshare_t3_d(0 to 3), + dout => cp_gshare_t3_q(0 to 3)); + +iu2_gshare_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(iu2_gshare_offset to iu2_gshare_offset+3), + scout => sov0(iu2_gshare_offset to iu2_gshare_offset+3), + din => iu2_gshare_d(0 to 3), + dout => iu2_gshare_q(0 to 3)); + +iu3_gshare_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(iu3_gshare_offset to iu3_gshare_offset+3), + scout => sov0(iu3_gshare_offset to iu3_gshare_offset+3), + din => iu3_gshare_d(0 to 3), + dout => iu3_gshare_q(0 to 3)); + + +iu4_bh_reg: tri_rlmreg_p + generic map (width => 2, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu4_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(iu4_bh_offset to iu4_bh_offset+1), + scout => sov0(iu4_bh_offset to iu4_bh_offset+1), + din => iu4_bh_d(0 to 1), + dout => iu4_bh_q(0 to 1)); + +iu4_lk_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu4_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(iu4_lk_offset), + scout => sov0(iu4_lk_offset), + din => iu4_lk_d, + dout => iu4_lk_q); + +iu4_aa_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu4_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(iu4_aa_offset), + scout => sov0(iu4_aa_offset), + din => iu4_aa_d, + dout => iu4_aa_q); + +iu4_b_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu4_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(iu4_b_offset), + scout => sov0(iu4_b_offset), + din => iu4_b_d, + dout => iu4_b_q); + + +iu4_opcode_reg: tri_rlmreg_p + generic map (width => 6, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu4_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(iu4_opcode_offset to iu4_opcode_offset+5), + scout => sov0(iu4_opcode_offset to iu4_opcode_offset+5), + din => iu4_opcode_d(0 to 5), + dout => iu4_opcode_q(0 to 5)); + +iu4_excode_reg: tri_rlmreg_p + generic map (width => 10, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu4_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(iu4_excode_offset to iu4_excode_offset+9), + scout => sov0(iu4_excode_offset to iu4_excode_offset+9), + din => iu4_excode_d(21 to 30), + dout => iu4_excode_q(21 to 30)); + +iu4_bo_reg: tri_rlmreg_p + generic map (width => 5, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu4_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(iu4_bo_offset to iu4_bo_offset+4), + scout => sov0(iu4_bo_offset to iu4_bo_offset+4), + din => iu4_bo_d(6 to 10), + dout => iu4_bo_q(6 to 10)); + +iu4_bi_reg: tri_rlmreg_p + generic map (width => 5, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu4_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(iu4_bi_offset to iu4_bi_offset+4), + scout => sov0(iu4_bi_offset to iu4_bi_offset+4), + din => iu4_bi_d(11 to 15), + dout => iu4_bi_q(11 to 15)); + + +iu4_tar_reg: tri_rlmreg_p + generic map (width => 24, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu4_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(iu4_tar_offset to iu4_tar_offset+23), + scout => sov0(iu4_tar_offset to iu4_tar_offset+23), + din => iu4_tar_d(6 to 29), + dout => iu4_tar_q(6 to 29)); + +iu4_ifar_reg: tri_rlmreg_p + generic map (width => EFF_IFAR'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu4_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(iu4_ifar_offset to iu4_ifar_offset+EFF_IFAR'length-1), + scout => sov0(iu4_ifar_offset to iu4_ifar_offset+EFF_IFAR'length-1), + din => iu4_ifar_d(EFF_IFAR'left to 61), + dout => iu4_ifar_q(EFF_IFAR'left to 61)); + +iu4_ifar_pri_reg: tri_rlmreg_p + generic map (width => 2, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu4_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(iu4_ifar_pri_offset to iu4_ifar_pri_offset+1), + scout => sov0(iu4_ifar_pri_offset to iu4_ifar_pri_offset+1), + din => iu4_ifar_pri_d(60 to 61), + dout => iu4_ifar_pri_q(60 to 61)); + + +iu4_pr_taken_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(iu4_pr_taken_offset to iu4_pr_taken_offset+3), + scout => sov0(iu4_pr_taken_offset to iu4_pr_taken_offset+3), + din => iu4_pr_taken_d(0 to 3), + dout => iu4_pr_taken_q(0 to 3)); + +iu4_tid_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu4_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(iu4_tid_offset to iu4_tid_offset+3), + scout => sov0(iu4_tid_offset to iu4_tid_offset+3), + din => iu4_tid_d(0 to 3), + dout => iu4_tid_q(0 to 3)); + + +iu4_t0_val_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(iu4_t0_val_offset to iu4_t0_val_offset+3), + scout => sov0(iu4_t0_val_offset to iu4_t0_val_offset+3), + din => iu4_t0_val_d(0 to 3), + dout => iu4_t0_val_q(0 to 3)); + +iu4_t1_val_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(iu4_t1_val_offset to iu4_t1_val_offset+3), + scout => sov0(iu4_t1_val_offset to iu4_t1_val_offset+3), + din => iu4_t1_val_d(0 to 3), + dout => iu4_t1_val_q(0 to 3)); + +iu4_t2_val_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(iu4_t2_val_offset to iu4_t2_val_offset+3), + scout => sov0(iu4_t2_val_offset to iu4_t2_val_offset+3), + din => iu4_t2_val_d(0 to 3), + dout => iu4_t2_val_q(0 to 3)); + +iu4_t3_val_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(iu4_t3_val_offset to iu4_t3_val_offset+3), + scout => sov0(iu4_t3_val_offset to iu4_t3_val_offset+3), + din => iu4_t3_val_d(0 to 3), + dout => iu4_t3_val_q(0 to 3)); + + +iu4_0_instr_reg: tri_rlmreg_p + generic map (width => 12, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu4_instr_act(0), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(iu4_0_instr_offset to iu4_0_instr_offset+11), + scout => sov0(iu4_0_instr_offset to iu4_0_instr_offset+11), + din => iu4_0_instr_d(32 to 43), + dout => iu4_0_instr_q(32 to 43)); + +iu4_1_instr_reg: tri_rlmreg_p + generic map (width => 44, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu4_instr_act(1), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(iu4_1_instr_offset to iu4_1_instr_offset+43), + scout => sov0(iu4_1_instr_offset to iu4_1_instr_offset+43), + din => iu4_1_instr_d(0 to 43), + dout => iu4_1_instr_q(0 to 43)); + +iu4_2_instr_reg: tri_rlmreg_p + generic map (width => 44, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu4_instr_act(2), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(iu4_2_instr_offset to iu4_2_instr_offset+43), + scout => sov0(iu4_2_instr_offset to iu4_2_instr_offset+43), + din => iu4_2_instr_d(0 to 43), + dout => iu4_2_instr_q(0 to 43)); + +iu4_3_instr_reg: tri_rlmreg_p + generic map (width => 44, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu4_instr_act(3), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(iu4_3_instr_offset to iu4_3_instr_offset+43), + scout => sov0(iu4_3_instr_offset to iu4_3_instr_offset+43), + din => iu4_3_instr_d(0 to 43), + dout => iu4_3_instr_q(0 to 43)); + +iu5_redirect_ifar_reg: tri_rlmreg_p + generic map (width => EFF_IFAR'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu5_redirect_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(iu5_redirect_ifar_offset to iu5_redirect_ifar_offset+EFF_IFAR'length-1), + scout => sov0(iu5_redirect_ifar_offset to iu5_redirect_ifar_offset+EFF_IFAR'length-1), + din => iu5_redirect_ifar_d(EFF_IFAR'left to 61), + dout => iu5_redirect_ifar_q(EFF_IFAR'left to 61)); + +iu5_redirect_tid_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(iu5_redirect_tid_offset to iu5_redirect_tid_offset+3), + scout => sov0(iu5_redirect_tid_offset to iu5_redirect_tid_offset+3), + din => iu5_redirect_tid_d(0 to 3), + dout => iu5_redirect_tid_q(0 to 3)); + +iu5_hold_tid_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(iu5_hold_tid_offset to iu5_hold_tid_offset+3), + scout => sov0(iu5_hold_tid_offset to iu5_hold_tid_offset+3), + din => iu5_hold_tid_d(0 to 3), + dout => iu5_hold_tid_q(0 to 3)); + + +iu5_ls_push_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(iu5_ls_push_offset to iu5_ls_push_offset+3), + scout => sov0(iu5_ls_push_offset to iu5_ls_push_offset+3), + din => iu5_ls_push_d(0 to 3), + dout => iu5_ls_push_q(0 to 3)); + +iu5_ls_pop_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(iu5_ls_pop_offset to iu5_ls_pop_offset+3), + scout => sov0(iu5_ls_pop_offset to iu5_ls_pop_offset+3), + din => iu5_ls_pop_d(0 to 3), + dout => iu5_ls_pop_q(0 to 3)); + +iu5_ifar_reg: tri_rlmreg_p + generic map (width => EFF_IFAR'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu5_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv0(iu5_ifar_offset to iu5_ifar_offset+EFF_IFAR'length-1), + scout => sov0(iu5_ifar_offset to iu5_ifar_offset+EFF_IFAR'length-1), + din => iu5_ifar_d(EFF_IFAR'left to 61), + dout => iu5_ifar_q(EFF_IFAR'left to 61)); + +--scan chain 1 +iu6_ls_t0_ptr_reg: tri_rlmreg_p + generic map (width => 4, init => 8, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu6_ls_ptr_act(0), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(iu6_ls_t0_ptr_offset to iu6_ls_t0_ptr_offset+3), + scout => sov1(iu6_ls_t0_ptr_offset to iu6_ls_t0_ptr_offset+3), + din => iu6_ls_t0_ptr_d(0 to 3), + dout => iu6_ls_t0_ptr_q(0 to 3)); + +iu6_ls_t1_ptr_reg: tri_rlmreg_p + generic map (width => 4, init => 8, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu6_ls_ptr_act(1), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(iu6_ls_t1_ptr_offset to iu6_ls_t1_ptr_offset+3), + scout => sov1(iu6_ls_t1_ptr_offset to iu6_ls_t1_ptr_offset+3), + din => iu6_ls_t1_ptr_d(0 to 3), + dout => iu6_ls_t1_ptr_q(0 to 3)); + +iu6_ls_t2_ptr_reg: tri_rlmreg_p + generic map (width => 4, init => 8, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu6_ls_ptr_act(2), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(iu6_ls_t2_ptr_offset to iu6_ls_t2_ptr_offset+3), + scout => sov1(iu6_ls_t2_ptr_offset to iu6_ls_t2_ptr_offset+3), + din => iu6_ls_t2_ptr_d(0 to 3), + dout => iu6_ls_t2_ptr_q(0 to 3)); + +iu6_ls_t3_ptr_reg: tri_rlmreg_p + generic map (width => 4, init => 8, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu6_ls_ptr_act(3), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(iu6_ls_t3_ptr_offset to iu6_ls_t3_ptr_offset+3), + scout => sov1(iu6_ls_t3_ptr_offset to iu6_ls_t3_ptr_offset+3), + din => iu6_ls_t3_ptr_d(0 to 3), + dout => iu6_ls_t3_ptr_q(0 to 3)); + +iu6_ls_t00_reg: tri_rlmreg_p + generic map (width => EFF_IFAR'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu6_ls_t0_act(0), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(iu6_ls_t00_offset to iu6_ls_t00_offset+EFF_IFAR'length-1), + scout => sov1(iu6_ls_t00_offset to iu6_ls_t00_offset+EFF_IFAR'length-1), + din => iu6_ls_t00_d(EFF_IFAR'left to 61), + dout => iu6_ls_t00_q(EFF_IFAR'left to 61)); + +iu6_ls_t01_reg: tri_rlmreg_p + generic map (width => EFF_IFAR'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu6_ls_t0_act(1), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(iu6_ls_t01_offset to iu6_ls_t01_offset+EFF_IFAR'length-1), + scout => sov1(iu6_ls_t01_offset to iu6_ls_t01_offset+EFF_IFAR'length-1), + din => iu6_ls_t01_d(EFF_IFAR'left to 61), + dout => iu6_ls_t01_q(EFF_IFAR'left to 61)); + +iu6_ls_t02_reg: tri_rlmreg_p + generic map (width => EFF_IFAR'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu6_ls_t0_act(2), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(iu6_ls_t02_offset to iu6_ls_t02_offset+EFF_IFAR'length-1), + scout => sov1(iu6_ls_t02_offset to iu6_ls_t02_offset+EFF_IFAR'length-1), + din => iu6_ls_t02_d(EFF_IFAR'left to 61), + dout => iu6_ls_t02_q(EFF_IFAR'left to 61)); + +iu6_ls_t03_reg: tri_rlmreg_p + generic map (width => EFF_IFAR'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu6_ls_t0_act(3), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(iu6_ls_t03_offset to iu6_ls_t03_offset+EFF_IFAR'length-1), + scout => sov1(iu6_ls_t03_offset to iu6_ls_t03_offset+EFF_IFAR'length-1), + din => iu6_ls_t03_d(EFF_IFAR'left to 61), + dout => iu6_ls_t03_q(EFF_IFAR'left to 61)); + +iu6_ls_t10_reg: tri_rlmreg_p + generic map (width => EFF_IFAR'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu6_ls_t1_act(0), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(iu6_ls_t10_offset to iu6_ls_t10_offset+EFF_IFAR'length-1), + scout => sov1(iu6_ls_t10_offset to iu6_ls_t10_offset+EFF_IFAR'length-1), + din => iu6_ls_t10_d(EFF_IFAR'left to 61), + dout => iu6_ls_t10_q(EFF_IFAR'left to 61)); + +iu6_ls_t11_reg: tri_rlmreg_p + generic map (width => EFF_IFAR'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu6_ls_t1_act(1), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(iu6_ls_t11_offset to iu6_ls_t11_offset+EFF_IFAR'length-1), + scout => sov1(iu6_ls_t11_offset to iu6_ls_t11_offset+EFF_IFAR'length-1), + din => iu6_ls_t11_d(EFF_IFAR'left to 61), + dout => iu6_ls_t11_q(EFF_IFAR'left to 61)); + +iu6_ls_t12_reg: tri_rlmreg_p + generic map (width => EFF_IFAR'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu6_ls_t1_act(2), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(iu6_ls_t12_offset to iu6_ls_t12_offset+EFF_IFAR'length-1), + scout => sov1(iu6_ls_t12_offset to iu6_ls_t12_offset+EFF_IFAR'length-1), + din => iu6_ls_t12_d(EFF_IFAR'left to 61), + dout => iu6_ls_t12_q(EFF_IFAR'left to 61)); + +iu6_ls_t13_reg: tri_rlmreg_p + generic map (width => EFF_IFAR'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu6_ls_t1_act(3), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(iu6_ls_t13_offset to iu6_ls_t13_offset+EFF_IFAR'length-1), + scout => sov1(iu6_ls_t13_offset to iu6_ls_t13_offset+EFF_IFAR'length-1), + din => iu6_ls_t13_d(EFF_IFAR'left to 61), + dout => iu6_ls_t13_q(EFF_IFAR'left to 61)); + +iu6_ls_t20_reg: tri_rlmreg_p + generic map (width => EFF_IFAR'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu6_ls_t2_act(0), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(iu6_ls_t20_offset to iu6_ls_t20_offset+EFF_IFAR'length-1), + scout => sov1(iu6_ls_t20_offset to iu6_ls_t20_offset+EFF_IFAR'length-1), + din => iu6_ls_t20_d(EFF_IFAR'left to 61), + dout => iu6_ls_t20_q(EFF_IFAR'left to 61)); + +iu6_ls_t21_reg: tri_rlmreg_p + generic map (width => EFF_IFAR'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu6_ls_t2_act(1), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(iu6_ls_t21_offset to iu6_ls_t21_offset+EFF_IFAR'length-1), + scout => sov1(iu6_ls_t21_offset to iu6_ls_t21_offset+EFF_IFAR'length-1), + din => iu6_ls_t21_d(EFF_IFAR'left to 61), + dout => iu6_ls_t21_q(EFF_IFAR'left to 61)); + +iu6_ls_t22_reg: tri_rlmreg_p + generic map (width => EFF_IFAR'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu6_ls_t2_act(2), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(iu6_ls_t22_offset to iu6_ls_t22_offset+EFF_IFAR'length-1), + scout => sov1(iu6_ls_t22_offset to iu6_ls_t22_offset+EFF_IFAR'length-1), + din => iu6_ls_t22_d(EFF_IFAR'left to 61), + dout => iu6_ls_t22_q(EFF_IFAR'left to 61)); + +iu6_ls_t23_reg: tri_rlmreg_p + generic map (width => EFF_IFAR'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu6_ls_t2_act(3), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(iu6_ls_t23_offset to iu6_ls_t23_offset+EFF_IFAR'length-1), + scout => sov1(iu6_ls_t23_offset to iu6_ls_t23_offset+EFF_IFAR'length-1), + din => iu6_ls_t23_d(EFF_IFAR'left to 61), + dout => iu6_ls_t23_q(EFF_IFAR'left to 61)); + +iu6_ls_t30_reg: tri_rlmreg_p + generic map (width => EFF_IFAR'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu6_ls_t3_act(0), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(iu6_ls_t30_offset to iu6_ls_t30_offset+EFF_IFAR'length-1), + scout => sov1(iu6_ls_t30_offset to iu6_ls_t30_offset+EFF_IFAR'length-1), + din => iu6_ls_t30_d(EFF_IFAR'left to 61), + dout => iu6_ls_t30_q(EFF_IFAR'left to 61)); + +iu6_ls_t31_reg: tri_rlmreg_p + generic map (width => EFF_IFAR'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu6_ls_t3_act(1), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(iu6_ls_t31_offset to iu6_ls_t31_offset+EFF_IFAR'length-1), + scout => sov1(iu6_ls_t31_offset to iu6_ls_t31_offset+EFF_IFAR'length-1), + din => iu6_ls_t31_d(EFF_IFAR'left to 61), + dout => iu6_ls_t31_q(EFF_IFAR'left to 61)); + +iu6_ls_t32_reg: tri_rlmreg_p + generic map (width => EFF_IFAR'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu6_ls_t3_act(2), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(iu6_ls_t32_offset to iu6_ls_t32_offset+EFF_IFAR'length-1), + scout => sov1(iu6_ls_t32_offset to iu6_ls_t32_offset+EFF_IFAR'length-1), + din => iu6_ls_t32_d(EFF_IFAR'left to 61), + dout => iu6_ls_t32_q(EFF_IFAR'left to 61)); + +iu6_ls_t33_reg: tri_rlmreg_p + generic map (width => EFF_IFAR'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu6_ls_t3_act(3), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(iu6_ls_t33_offset to iu6_ls_t33_offset+EFF_IFAR'length-1), + scout => sov1(iu6_ls_t33_offset to iu6_ls_t33_offset+EFF_IFAR'length-1), + din => iu6_ls_t33_d(EFF_IFAR'left to 61), + dout => iu6_ls_t33_q(EFF_IFAR'left to 61)); + +ex6_val_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(ex6_val_offset), + scout => sov1(ex6_val_offset), + din => ex6_val_d, + dout => ex6_val_q); + +ex6_ifar_reg: tri_rlmreg_p + generic map (width => EFF_IFAR'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex6_val_d, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(ex6_ifar_offset to ex6_ifar_offset+EFF_IFAR'length-1), + scout => sov1(ex6_ifar_offset to ex6_ifar_offset+EFF_IFAR'length-1), + din => ex6_ifar_d(EFF_IFAR'left to 61), + dout => ex6_ifar_q(EFF_IFAR'left to 61)); + +ex6_tid_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex6_val_d, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(ex6_tid_offset to ex6_tid_offset+3), + scout => sov1(ex6_tid_offset to ex6_tid_offset+3), + din => ex6_tid_d(0 to 3), + dout => ex6_tid_q(0 to 3)); + +ex6_br_update_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex6_val_d, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(ex6_br_update_offset), + scout => sov1(ex6_br_update_offset), + din => ex6_br_update_d, + dout => ex6_br_update_q); + +ex6_br_hist_reg: tri_rlmreg_p + generic map (width => 2, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex6_val_d, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(ex6_br_hist_offset to ex6_br_hist_offset+1), + scout => sov1(ex6_br_hist_offset to ex6_br_hist_offset+1), + din => ex6_br_hist_d(0 to 1), + dout => ex6_br_hist_q(0 to 1)); + +ex6_br_taken_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex6_val_d, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(ex6_br_taken_offset), + scout => sov1(ex6_br_taken_offset), + din => ex6_br_taken_d, + dout => ex6_br_taken_q); + +ex6_bclr_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex6_val_d, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(ex6_bclr_offset), + scout => sov1(ex6_bclr_offset), + din => ex6_bclr_d, + dout => ex6_bclr_q); + + +ex6_lk_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex6_val_d, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(ex6_lk_offset), + scout => sov1(ex6_lk_offset), + din => ex6_lk_d, + dout => ex6_lk_q); + + +ex6_gshare_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex6_val_d, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(ex6_gshare_offset to ex6_gshare_offset+3), + scout => sov1(ex6_gshare_offset to ex6_gshare_offset+3), + din => ex6_gshare_d(0 to 3), + dout => ex6_gshare_q(0 to 3)); + +ex6_ls_push_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(ex6_ls_push_offset to ex6_ls_push_offset+3), + scout => sov1(ex6_ls_push_offset to ex6_ls_push_offset+3), + din => ex6_ls_push_d(0 to 3), + dout => ex6_ls_push_q(0 to 3)); + +ex6_ls_pop_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(ex6_ls_pop_offset to ex6_ls_pop_offset+3), + scout => sov1(ex6_ls_pop_offset to ex6_ls_pop_offset+3), + din => ex6_ls_pop_d(0 to 3), + dout => ex6_ls_pop_q(0 to 3)); + +ex6_flush_tid_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(ex6_flush_tid_offset to ex6_flush_tid_offset+3), + scout => sov1(ex6_flush_tid_offset to ex6_flush_tid_offset+3), + din => ex6_flush_tid_d(0 to 3), + dout => ex6_flush_tid_q(0 to 3)); + +ex7_ls_t0_ptr_reg: tri_rlmreg_p + generic map (width => 4, init => 8, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex7_ls_ptr_act(0), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(ex7_ls_t0_ptr_offset to ex7_ls_t0_ptr_offset+3), + scout => sov1(ex7_ls_t0_ptr_offset to ex7_ls_t0_ptr_offset+3), + din => ex7_ls_t0_ptr_d(0 to 3), + dout => ex7_ls_t0_ptr_q(0 to 3)); + +ex7_ls_t1_ptr_reg: tri_rlmreg_p + generic map (width => 4, init => 8, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex7_ls_ptr_act(1), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(ex7_ls_t1_ptr_offset to ex7_ls_t1_ptr_offset+3), + scout => sov1(ex7_ls_t1_ptr_offset to ex7_ls_t1_ptr_offset+3), + din => ex7_ls_t1_ptr_d(0 to 3), + dout => ex7_ls_t1_ptr_q(0 to 3)); + +ex7_ls_t2_ptr_reg: tri_rlmreg_p + generic map (width => 4, init => 8, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex7_ls_ptr_act(2), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(ex7_ls_t2_ptr_offset to ex7_ls_t2_ptr_offset+3), + scout => sov1(ex7_ls_t2_ptr_offset to ex7_ls_t2_ptr_offset+3), + din => ex7_ls_t2_ptr_d(0 to 3), + dout => ex7_ls_t2_ptr_q(0 to 3)); + +ex7_ls_t3_ptr_reg: tri_rlmreg_p + generic map (width => 4, init => 8, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex7_ls_ptr_act(3), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(ex7_ls_t3_ptr_offset to ex7_ls_t3_ptr_offset+3), + scout => sov1(ex7_ls_t3_ptr_offset to ex7_ls_t3_ptr_offset+3), + din => ex7_ls_t3_ptr_d(0 to 3), + dout => ex7_ls_t3_ptr_q(0 to 3)); + +bp_config_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(bp_config_offset to bp_config_offset+3), + scout => sov1(bp_config_offset to bp_config_offset+3), + din => bp_config_d(0 to 3), + dout => bp_config_q(0 to 3)); + +gshare_mask_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + + scin => siv1(gshare_mask_offset to gshare_mask_offset+3), + scout => sov1(gshare_mask_offset to gshare_mask_offset+3), + din => gshare_mask_d(0 to 3), + dout => gshare_mask_q(0 to 3)); + +spare_latch: tri_rlmreg_p + generic map (width => spare_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv1(spare_offset to spare_offset + spare_l2'length-1), + scout => sov1(spare_offset to spare_offset + spare_l2'length-1), + din => spare_l2, + dout => spare_l2); + + +------------------------------------------------- +-- pervasive +------------------------------------------------- + +perv_2to1_reg: tri_plat + generic map (width => 2, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_iu_func_sl_thold_2, + din(1) => pc_iu_sg_2, + q(0) => pc_iu_func_sl_thold_1, + q(1) => pc_iu_sg_1); + +perv_1to0_reg: tri_plat + generic map (width => 2, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_iu_func_sl_thold_1, + din(1) => pc_iu_sg_1, + q(0) => pc_iu_func_sl_thold_0, + q(1) => pc_iu_sg_0); + +perv_lcbor: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_b, + thold => pc_iu_func_sl_thold_0, + sg => pc_iu_sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => pc_iu_func_sl_thold_0_b); + +slat_lcb: tri_lcbs + generic map (expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + delay_lclkr => delay_lclkr, + nclk => nclk, + forcee => forcee, + thold_b => pc_iu_func_sl_thold_0_b, + dclk => dclk, + lclk => lclk ); + +dft_latch: tri_slat_scan + generic map (width => 1, init => "0", expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + dclk => dclk, + lclk => lclk, + scan_in => siv1(dft_offset to dft_offset), + scan_out => sov1(dft_offset to dft_offset), + q => dft_q, + q_b => open); + + +------------------------------------------------- +-- scan +------------------------------------------------- + +siv0(0 to scan_right0) <= scan_in(0) & sov0(0 to scan_right0-1); +scan_out(0) <= sov0(scan_right0) and an_ac_scan_dis_dc_b; + +siv1(0 to scan_right1) <= scan_in(1) & sov1(0 to scan_right1-1); +scan_out(1) <= sov1(scan_right1) and an_ac_scan_dis_dc_b; + +end iuq_bp; diff --git a/rel/src/vhdl/work/iuq_dbg.vhdl b/rel/src/vhdl/work/iuq_dbg.vhdl new file mode 100644 index 0000000..d62b8b1 --- /dev/null +++ b/rel/src/vhdl/work/iuq_dbg.vhdl @@ -0,0 +1,359 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +--******************************************************************** +--* +--* TITLE: debug event mux +--* +--* NAME: iuq_dbg.vhdl +--* +--********************************************************************* + + + +library ieee; +use ieee.std_logic_1164.all; + +library ibm,clib; +use ibm.std_ulogic_unsigned.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; + +library support; +use support.power_logic_pkg.all; + +library tri; +use tri.tri_latches_pkg.all; + +library work; +use work.iuq_pkg.all; + + +entity iuq_dbg is +generic(expand_type : integer := 2 ); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + pc_iu_func_slp_sl_thold_2 : in std_ulogic; + pc_iu_sg_2 : in std_ulogic; + clkoff_b : in std_ulogic; + act_dis : in std_ulogic; + tc_ac_ccflush_dc : in std_ulogic; + d_mode : in std_ulogic; + delay_lclkr : in std_ulogic; + mpw1_b : in std_ulogic; + mpw2_b : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + fiss_dbg_data : in std_ulogic_vector(0 to 87); + fdep_dbg_data : in std_ulogic_vector(0 to 87); + ib_dbg_data : in std_ulogic_vector(0 to 63); + bp_dbg_data0 : in std_ulogic_vector(0 to 87); + bp_dbg_data1 : in std_ulogic_vector(0 to 87); + fu_iss_dbg_data : in std_ulogic_vector(0 to 23); + axu_dbg_data_t0 : in std_ulogic_vector(0 to 37); + axu_dbg_data_t1 : in std_ulogic_vector(0 to 37); + axu_dbg_data_t2 : in std_ulogic_vector(0 to 37); + axu_dbg_data_t3 : in std_ulogic_vector(0 to 37); + bht_dbg_data : in std_ulogic_vector(0 to 31); + + pc_iu_trace_bus_enable : in std_ulogic; + pc_iu_debug_mux_ctrls : in std_ulogic_vector(0 to 15); + + debug_data_in : in std_ulogic_vector(0 to 87); + trace_triggers_in : in std_ulogic_vector(0 to 11); + + debug_data_out : out std_ulogic_vector(0 to 87); + trace_triggers_out : out std_ulogic_vector(0 to 11) +); + + -- synopsys translate_off + + + -- synopsys translate_on +end iuq_dbg; + + +architecture iuq_dbg of iuq_dbg is + +signal trigger_data_out_d : std_ulogic_vector(0 to 11); +signal trigger_data_out_q : std_ulogic_vector(0 to 11); +signal trace_data_out_d : std_ulogic_vector(0 to 87); +signal trace_data_out_q : std_ulogic_vector(0 to 87); + +constant trigger_data_out_offset: natural := 0; +constant trace_data_out_offset : natural := trigger_data_out_offset + trigger_data_out_q'length; +constant trace_bus_enable_offset: natural := trace_data_out_offset + trace_data_out_q'length; +constant debug_mux_ctrls_offset : natural := trace_bus_enable_offset + 1; +constant scan_right : natural := debug_mux_ctrls_offset + 16-1; + + + + + +signal dbg_group0 : std_ulogic_vector(0 to 87); +signal dbg_group1 : std_ulogic_vector(0 to 87); +signal dbg_group2 : std_ulogic_vector(0 to 87); +signal dbg_group3 : std_ulogic_vector(0 to 87); +signal dbg_group4 : std_ulogic_vector(0 to 87); +signal dbg_group5 : std_ulogic_vector(0 to 87); +signal dbg_group6 : std_ulogic_vector(0 to 87); +signal dbg_group7 : std_ulogic_vector(0 to 87); + +signal trg_group0 : std_ulogic_vector(0 to 11); +signal trg_group1 : std_ulogic_vector(0 to 11); +signal trg_group2 : std_ulogic_vector(0 to 11); +signal trg_group3 : std_ulogic_vector(0 to 11); + +signal siv : std_ulogic_vector(0 to scan_right); +signal sov : std_ulogic_vector(0 to scan_right); + +signal tiup : std_ulogic; + +signal pc_iu_func_slp_sl_thold_1 : std_ulogic; +signal pc_iu_func_slp_sl_thold_0 : std_ulogic; +signal pc_iu_func_slp_sl_thold_0_b : std_ulogic; +signal pc_iu_sg_1 : std_ulogic; +signal pc_iu_sg_0 : std_ulogic; +signal forcee : std_ulogic; + +signal trace_bus_enable_d : std_ulogic; +signal trace_bus_enable_q : std_ulogic; +signal debug_mux_ctrls_d : std_ulogic_vector(0 to 15); +signal debug_mux_ctrls_q : std_ulogic_vector(0 to 15); + +begin + +----------------------------------------------------------------------- +-- Logic +----------------------------------------------------------------------- + +tiup <= '1'; + + + + + + + + + +dbg_group0 <= bp_dbg_data0(0 to 87); +dbg_group1 <= bp_dbg_data1(0 to 87); +dbg_group2 <= ib_dbg_data(0 to 63) & fu_iss_dbg_data(0 to 23); +dbg_group3 <= fdep_dbg_data(0 to 87); +dbg_group4 <= fiss_dbg_data(0 to 87); +dbg_group5(0 to 75) <= axu_dbg_data_t0(0 to 37) & axu_dbg_data_t1(0 to 37); +dbg_group6(0 to 75) <= axu_dbg_data_t2(0 to 37) & axu_dbg_data_t3(0 to 37); +dbg_group7(0 to 31) <= bht_dbg_data(0 to 31); + +dbg_group5(76 to 87) <= (others => '0'); +dbg_group6(76 to 87) <= (others => '0'); +dbg_group7(32 to 87) <= (others => '0'); + +trg_group0 <= ib_dbg_data(0) & ib_dbg_data( 4 to 5) & --t0: bp_val, rm_val, uc_val + ib_dbg_data(16) & ib_dbg_data(20 to 21) & --t1 + ib_dbg_data(32) & ib_dbg_data(36 to 37) & --t2 + ib_dbg_data(48) & ib_dbg_data(52 to 53) ; --t3 + +trg_group1 <= fiss_dbg_data(0 to 7) & --high pri mask(0 to 3), low pri mask (0 to 3) + fiss_dbg_data(44 to 45) & --is2 instr_val, uc_val + bp_dbg_data0(84 to 85); --ex6 val, br_update + +trg_group2 <= fdep_dbg_data(14) & fdep_dbg_data(36) & fdep_dbg_data(58) & fdep_dbg_data(80) & --is1 val + bht_dbg_data(27 to 31) & --r_act, w_act(0 to 3) + bp_dbg_data1(84 to 86) ; --ex6 br_taken, bclr, lk + +trg_group3 <= axu_dbg_data_t0(10) & -- 0 is1_to_ucode + axu_dbg_data_t1(10) & -- 1 is1_to_ucode + axu_dbg_data_t2(10) & -- 2 is1_to_ucode + axu_dbg_data_t3(10) & -- 3 is1_to_ucode + axu_dbg_data_t0(21) & -- 4 bubble3_is1_db + axu_dbg_data_t1(21) & -- 5 bubble3_is1_db + axu_dbg_data_t2(21) & -- 6 bubble3_is1_db + axu_dbg_data_t3(21) & -- 7 bubble3_is1_db + fu_iss_dbg_data(20) & -- 8 is2_issue_sel_db(0) + fu_iss_dbg_data(21) & -- 9 is2_issue_sel_db(1) + fu_iss_dbg_data(22) & -- 10 is2_issue_sel_db(2) + fu_iss_dbg_data(23) ; -- 11 is2_issue_sel_db(3) + + +dbg_mux0: entity clib.c_debug_mux8 + port map( + vd => vdd, + gd => gnd, + + select_bits => debug_mux_ctrls_q, + trace_data_in => debug_data_in, + trigger_data_in => trace_triggers_in, + + dbg_group0 => dbg_group0, + dbg_group1 => dbg_group1, + dbg_group2 => dbg_group2, + dbg_group3 => dbg_group3, + dbg_group4 => dbg_group4, + dbg_group5 => dbg_group5, + dbg_group6 => dbg_group6, + dbg_group7 => dbg_group7, + + trg_group0 => trg_group0, + trg_group1 => trg_group1, + trg_group2 => trg_group2, + trg_group3 => trg_group3, + + trace_data_out => trace_data_out_d, + trigger_data_out=> trigger_data_out_d +); + +trace_triggers_out <= trigger_data_out_q; +debug_data_out <= trace_data_out_q; + +----------------------------------------------------------------------- +-- Latches +----------------------------------------------------------------------- +trace_bus_enable_d <= pc_iu_trace_bus_enable; +debug_mux_ctrls_d <= pc_iu_debug_mux_ctrls; + +trace_enable_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(trace_bus_enable_offset), + scout => sov(trace_bus_enable_offset), + din => trace_bus_enable_d, + dout => trace_bus_enable_q); + +debug_mux_ctrls_reg: tri_rlmreg_p + generic map (width => debug_mux_ctrls_q'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => trace_bus_enable_q, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(debug_mux_ctrls_offset to debug_mux_ctrls_offset + debug_mux_ctrls_q'length-1), + scout => sov(debug_mux_ctrls_offset to debug_mux_ctrls_offset + debug_mux_ctrls_q'length-1), + din => debug_mux_ctrls_d, + dout => debug_mux_ctrls_q); + +trigger_data_reg: tri_rlmreg_p + generic map (width => trigger_data_out_q'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => trace_bus_enable_q, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(trigger_data_out_offset to trigger_data_out_offset + trigger_data_out_q'length-1), + scout => sov(trigger_data_out_offset to trigger_data_out_offset + trigger_data_out_q'length-1), + din => trigger_data_out_d, + dout => trigger_data_out_q); + +trace_data_reg: tri_rlmreg_p + generic map (width => trace_data_out_q'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => trace_bus_enable_q, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(trace_data_out_offset to trace_data_out_offset + trace_data_out_q'length-1), + scout => sov(trace_data_out_offset to trace_data_out_offset + trace_data_out_q'length-1), + din => trace_data_out_d, + dout => trace_data_out_q); + +------------------------------------------------- +-- pervasive +------------------------------------------------- + +perv_2to1_reg: tri_plat + generic map (width => 2, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_iu_func_slp_sl_thold_2, + din(1) => pc_iu_sg_2, + q(0) => pc_iu_func_slp_sl_thold_1, + q(1) => pc_iu_sg_1); + +perv_1to0_reg: tri_plat + generic map (width => 2, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_iu_func_slp_sl_thold_1, + din(1) => pc_iu_sg_1, + q(0) => pc_iu_func_slp_sl_thold_0, + q(1) => pc_iu_sg_0); + +perv_lcbor: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_b, + thold => pc_iu_func_slp_sl_thold_0, + sg => pc_iu_sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => pc_iu_func_slp_sl_thold_0_b); + +----------------------------------------------------------------------- +-- Scan +----------------------------------------------------------------------- +siv(0 to scan_right) <= sov(1 to scan_right) & scan_in; +scan_out <= sov(0); + + +end iuq_dbg; + diff --git a/rel/src/vhdl/work/iuq_fxu_decode.vhdl b/rel/src/vhdl/work/iuq_fxu_decode.vhdl new file mode 100644 index 0000000..4a393e2 --- /dev/null +++ b/rel/src/vhdl/work/iuq_fxu_decode.vhdl @@ -0,0 +1,4770 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; +use ieee.std_logic_1164.all; +library ibm; +use ibm.std_ulogic_unsigned.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +library support; +use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; +library work; +use work.iuq_pkg.all; + +entity iuq_fxu_decode is + generic(a2mode : integer := 1; + regmode : integer := 6; + expand_type : integer := 2 ); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + + pc_iu_sg_0 : in std_ulogic; + pc_iu_func_sl_thold_0_b : in std_ulogic; + forcee : in std_ulogic; + d_mode : in std_ulogic; + delay_lclkr : in std_ulogic; + mpw1_b : in std_ulogic; + mpw2_b : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + pc_au_ram_mode : in std_ulogic; + pc_au_ram_thread_v : in std_ulogic; + + spr_dec_mask : in std_ulogic_vector(0 to 31); + spr_dec_match : in std_ulogic_vector(0 to 31); + + + au_iu_i_dec_b : in std_ulogic; + iu_au_is1_cr_user_v : out std_ulogic; + iu_au_is0_cr_setter : out std_ulogic; + + au_iu_ib1_ldst : in std_ulogic; + au_iu_ib1_ldst_v : in std_ulogic; + au_iu_ib1_store : in std_ulogic; + au_iu_ib1_ldst_size : in std_ulogic_vector(0 to 5); + au_iu_ib1_ldst_tag : in std_ulogic_vector(0 to 8); + au_iu_ib1_ldst_ra_v : in std_ulogic; + au_iu_ib1_ldst_ra : in std_ulogic_vector(0 to 6); + au_iu_ib1_ldst_rb_v : in std_ulogic; + au_iu_ib1_ldst_rb : in std_ulogic_vector(0 to 6); + au_iu_ib1_ldst_dimm : in std_ulogic_vector(0 to 15); + au_iu_ib1_ldst_indexed : in std_ulogic; + au_iu_ib1_ldst_update : in std_ulogic; + au_iu_ib1_ldst_extpid : in std_ulogic; + au_iu_ib1_ldst_forcealign : in std_ulogic; + au_iu_ib1_ldst_forceexcept : in std_ulogic; + au_iu_ib1_mftgpr : in std_ulogic; + au_iu_ib1_mffgpr : in std_ulogic; + au_iu_ib1_movedp : in std_ulogic; + au_iu_ib1_instr_type : in std_ulogic_vector(0 to 2); + + iu_au_ib1_instr_vld : in std_ulogic; + iu_au_ib1_ifar : in EFF_IFAR; + iu_au_ib1_instr : in std_ulogic_vector(0 to 31); + iu_au_ib1_instr_ucode_ext : in std_ulogic_vector(0 to 3); + iu_au_ib1_instr_pred_vld : in std_ulogic; + iu_au_ib1_instr_pred_taken_cnt : in std_ulogic_vector(0 to 1); + iu_au_ib1_instr_gshare : in std_ulogic_vector(0 to 3); + iu_au_ib1_instr_error : in std_ulogic_vector(0 to 2); + iu_au_ib1_instr_is_ucode : in std_ulogic; + iu_au_ib1_instr_2ucode : in std_ulogic; + iu_au_ib1_instr_2ucode_type : in std_ulogic; + iu_au_ib1_instr_force_ram : in std_ulogic; + + au_iu_is0_to_ucode : in std_ulogic; + au_iu_is0_ucode_only : in std_ulogic; + iu_au_is1_stall : in std_ulogic; + + xu_iu_ib1_flush : in std_ulogic; + fdep_fdec_buff_stall : in std_ulogic; + fdep_fdec_weak_stall : in std_ulogic; + fdec_ibuf_stall : out std_ulogic; + + fdec_fdep_is1_vld : out std_ulogic; + fdec_fdep_is1_instr : out std_ulogic_vector(0 to 31); + fdec_fdep_is1_ta_vld : out std_ulogic; + fdec_fdep_is1_ta : out std_ulogic_vector(0 to 5); + fdec_fdep_is1_s1_vld : out std_ulogic; + fdec_fdep_is1_s1 : out std_ulogic_vector(0 to 5); + fdec_fdep_is1_s2_vld : out std_ulogic; + fdec_fdep_is1_s2 : out std_ulogic_vector(0 to 5); + fdec_fdep_is1_s3_vld : out std_ulogic; + fdec_fdep_is1_s3 : out std_ulogic_vector(0 to 5); + fdec_fdep_is1_pred_update : out std_ulogic; + fdec_fdep_is1_pred_taken_cnt : out std_ulogic_vector(0 to 1); + fdec_fdep_is1_gshare : out std_ulogic_vector(0 to 3); + fdec_fdep_is1_UpdatesLR : out std_ulogic; + fdec_fdep_is1_UpdatesCR : out std_ulogic; + fdec_fdep_is1_UpdatesCTR : out std_ulogic; + fdec_fdep_is1_UpdatesXER : out std_ulogic; + fdec_fdep_is1_UpdatesMSR : out std_ulogic; + fdec_fdep_is1_UpdatesSPR : out std_ulogic; + fdec_fdep_is1_UsesLR : out std_ulogic; + fdec_fdep_is1_UsesCR : out std_ulogic; + fdec_fdep_is1_UsesCTR : out std_ulogic; + fdec_fdep_is1_UsesXER : out std_ulogic; + fdec_fdep_is1_UsesMSR : out std_ulogic; + fdec_fdep_is1_UsesSPR : out std_ulogic; + fdec_fdep_is1_hole_delay : out std_ulogic_vector(0 to 2); + fdec_fdep_is1_ld_vld : out std_ulogic; + fdec_fdep_is1_to_ucode : out std_ulogic; + fdec_fdep_is1_is_ucode : out std_ulogic; + fdec_fdep_is1_ifar : out EFF_IFAR; + fdec_fdep_is1_error : out std_ulogic_vector(0 to 2); + fdec_fdep_is1_complete : out std_ulogic_vector(0 to 4); + fdec_fdep_is1_axu_ld_or_st : out std_ulogic; + fdec_fdep_is1_axu_store : out std_ulogic; + fdec_fdep_is1_axu_ldst_indexed : out std_ulogic; + fdec_fdep_is1_axu_ldst_tag : out std_ulogic_vector(0 to 8); + fdec_fdep_is1_axu_ldst_size : out std_ulogic_vector(0 to 5); + fdec_fdep_is1_axu_ldst_update : out std_ulogic; + fdec_fdep_is1_axu_ldst_extpid : out std_ulogic; + fdec_fdep_is1_axu_ldst_forcealign : out std_ulogic; + fdec_fdep_is1_axu_ldst_forceexcept : out std_ulogic; + fdec_fdep_is1_axu_mftgpr : out std_ulogic; + fdec_fdep_is1_axu_mffgpr : out std_ulogic; + fdec_fdep_is1_axu_movedp : out std_ulogic; + fdec_fdep_is1_axu_instr_type : out std_ulogic_vector(0 to 2); + fdec_fdep_is1_2ucode : out std_ulogic; + fdec_fdep_is1_2ucode_type : out std_ulogic; + fdec_fdep_is1_force_ram : out std_ulogic; + fdec_fdep_is1_match : out std_ulogic +); +end iuq_fxu_decode; +ARCHITECTURE IUQ_FXU_DECODE + OF IUQ_FXU_DECODE + IS +--@@ Signal Declarations +SIGNAL BR_DEP_PT : STD_ULOGIC_VECTOR(1 TO 105) := +(OTHERS=> 'U'); +SIGNAL INSTRUCTION_DECODER1_PT : STD_ULOGIC_VECTOR(1 TO 15) := +(OTHERS=> 'U'); +SIGNAL INSTRUCTION_DECODER2_PT : STD_ULOGIC_VECTOR(1 TO 121) := +(OTHERS=> 'U'); +SIGNAL INSTRUCTION_DECODER_PT : STD_ULOGIC_VECTOR(1 TO 58) := +(OTHERS=> 'U'); +SIGNAL MICROCODE_PT : STD_ULOGIC_VECTOR(1 TO 13) := +(OTHERS=> 'U'); +SIGNAL UpdatesCR : STD_ULOGIC := +'U'; +SIGNAL UpdatesCTR : STD_ULOGIC := +'U'; +SIGNAL UpdatesLR : STD_ULOGIC := +'U'; +SIGNAL UpdatesMSR : STD_ULOGIC := +'U'; +SIGNAL UpdatesSPR : STD_ULOGIC := +'U'; +SIGNAL UpdatesXER : STD_ULOGIC := +'U'; +SIGNAL UsesCR : STD_ULOGIC := +'U'; +SIGNAL UsesCTR : STD_ULOGIC := +'U'; +SIGNAL UsesLR : STD_ULOGIC := +'U'; +SIGNAL UsesMSR : STD_ULOGIC := +'U'; +SIGNAL UsesSPR : STD_ULOGIC := +'U'; +SIGNAL UsesXER : STD_ULOGIC := +'U'; +SIGNAL compl_ex : STD_ULOGIC_VECTOR(1 TO 5) := +"UUUUU"; +SIGNAL hole_delay : STD_ULOGIC_VECTOR(1 TO 3) := +"UUU"; +SIGNAL isFxuIssue : STD_ULOGIC := +'U'; +SIGNAL ld_vld : STD_ULOGIC := +'U'; +SIGNAL s1_sel : STD_ULOGIC := +'U'; +SIGNAL s1_vld : STD_ULOGIC := +'U'; +SIGNAL s2_sel : STD_ULOGIC := +'U'; +SIGNAL s2_vld : STD_ULOGIC := +'U'; +SIGNAL s3_sel : STD_ULOGIC := +'U'; +SIGNAL s3_vld : STD_ULOGIC := +'U'; +SIGNAL ta_sel : STD_ULOGIC := +'U'; +SIGNAL ta_vld : STD_ULOGIC := +'U'; +SIGNAL to_uc : STD_ULOGIC := +'U'; +-- Scan chain connenctions +constant is1_vld_offset : natural := 0; +constant is1_vld_type_offset : natural := is1_vld_offset + 1; +constant is1_instr_offset : natural := is1_vld_type_offset + 3; +constant is1_axu_instr_offset : natural := is1_instr_offset + 32; +constant is1_ta_vld_offset : natural := is1_axu_instr_offset + 26; +constant is1_ta_offset : natural := is1_ta_vld_offset + 1; +constant is1_s1_vld_offset : natural := is1_ta_offset + 6; +constant is1_s1_offset : natural := is1_s1_vld_offset + 1; +constant is1_s2_vld_offset : natural := is1_s1_offset + 6; +constant is1_s2_offset : natural := is1_s2_vld_offset + 1; +constant is1_s3_vld_offset : natural := is1_s2_offset + 6; +constant is1_s3_offset : natural := is1_s3_vld_offset + 1; +constant is1_ld_vld_offset : natural := is1_s3_offset + 6; +constant is1_pred_update_offset : natural := is1_ld_vld_offset + 1; +constant is1_pred_taken_cnt_offset : natural := is1_pred_update_offset + 1; +constant is1_gshare_offset : natural := is1_pred_taken_cnt_offset + 2; +constant is1_UpdatesLR_offset : natural := is1_gshare_offset + 4; +constant is1_UpdatesCR_offset : natural := is1_UpdatesLR_offset + 1; +constant is1_UpdatesCTR_offset : natural := is1_UpdatesCR_offset + 1; +constant is1_UpdatesXER_offset : natural := is1_UpdatesCTR_offset + 1; +constant is1_UpdatesMSR_offset : natural := is1_UpdatesXER_offset + 1; +constant is1_UpdatesSPR_offset : natural := is1_UpdatesMSR_offset + 1; +constant is1_UsesLR_offset : natural := is1_UpdatesSPR_offset + 1; +constant is1_UsesCR_offset : natural := is1_UsesLR_offset + 1; +constant is1_UsesCTR_offset : natural := is1_UsesCR_offset + 1; +constant is1_UsesXER_offset : natural := is1_UsesCTR_offset + 1; +constant is1_UsesMSR_offset : natural := is1_UsesXER_offset + 1; +constant is1_UsesSPR_offset : natural := is1_UsesMSR_offset + 1; +constant is1_to_ucode_offset : natural := is1_UsesSPR_offset + 1; +constant is1_is_ucode_offset : natural := is1_to_ucode_offset + 1; +constant is1_ifar_offset : natural := is1_is_ucode_offset + 1; +constant is1_error_offset : natural := is1_ifar_offset + EFF_IFAR'length; +constant is1_axu_ldst_ra_v_offset : natural := is1_error_offset + 3; +constant is1_axu_ldst_rb_v_offset : natural := is1_axu_ldst_ra_v_offset + 1; +constant is1_axu_ld_or_st_offset : natural := is1_axu_ldst_rb_v_offset + 1; +constant is1_axu_store_offset : natural := is1_axu_ld_or_st_offset + 1; +constant is1_axu_ldst_size_offset : natural := is1_axu_store_offset + 1; +constant is1_axu_ldst_update_offset : natural := is1_axu_ldst_size_offset + 6; +constant is1_axu_ldst_extpid_offset : natural := is1_axu_ldst_update_offset + 1; +constant is1_axu_ldst_forcealign_offset : natural := is1_axu_ldst_extpid_offset + 1; +constant is1_axu_ldst_forceexcept_offset: natural := is1_axu_ldst_forcealign_offset + 1; +constant is1_axu_mftgpr_offset : natural := is1_axu_ldst_forceexcept_offset + 1; +constant is1_axu_mffgpr_offset : natural := is1_axu_mftgpr_offset + 1; +constant is1_axu_movedp_offset : natural := is1_axu_mffgpr_offset + 1; +constant is1_axu_instr_type_offset : natural := is1_axu_movedp_offset + 1; +constant is1_force_ram_offset : natural := is1_axu_instr_type_offset + 3; +constant is1_2ucode_offset : natural := is1_force_ram_offset + 1; +constant is1_2ucode_type_offset : natural := is1_2ucode_offset + 1; +constant spare_offset : natural := is1_2ucode_type_offset + 1; +constant scan_right : natural := spare_offset + 6-1; +signal spare_l2 : std_ulogic_vector(0 to 5); +-- signals for hooking up scanchains +signal siv : std_ulogic_vector(0 to scan_right); +signal sov : std_ulogic_vector(0 to scan_right); +signal tiup : std_ulogic; +signal is1_vld_d : std_ulogic; +signal is1_vld_type_d : std_ulogic_vector(0 to 2); +signal is1_instr_d : std_ulogic_vector(0 to 31); +signal is1_axu_instr_d : std_ulogic_vector(6 to 31); +signal is1_ta_vld_d : std_ulogic; +signal is1_ta_d : std_ulogic_vector(0 to 5); +signal is1_s1_vld_d : std_ulogic; +signal is1_s1_d : std_ulogic_vector(0 to 5); +signal is1_s2_vld_d : std_ulogic; +signal is1_s2_d : std_ulogic_vector(0 to 5); +signal is1_s3_vld_d : std_ulogic; +signal is1_s3_d : std_ulogic_vector(0 to 5); +signal is1_pred_update_d : std_ulogic; +signal is1_pred_taken_cnt_d : std_ulogic_vector(0 to 1); +signal is1_gshare_d : std_ulogic_vector(0 to 3); +signal is1_UpdatesLR_d : std_ulogic; +signal is1_UpdatesCR_d : std_ulogic; +signal is1_UpdatesCTR_d : std_ulogic; +signal is1_UpdatesXER_d : std_ulogic; +signal is1_UpdatesMSR_d : std_ulogic; +signal is1_UpdatesSPR_d : std_ulogic; +signal is1_UsesLR_d : std_ulogic; +signal is1_UsesCR_d : std_ulogic; +signal is1_UsesCTR_d : std_ulogic; +signal is1_UsesXER_d : std_ulogic; +signal is1_UsesMSR_d : std_ulogic; +signal is1_UsesSPR_d : std_ulogic; +signal is1_ld_vld_d : std_ulogic; +signal is1_to_ucode_d : std_ulogic; +signal is1_is_ucode_d : std_ulogic; +signal is1_ifar_d : EFF_IFAR; +signal is1_error_d : std_ulogic_vector(0 to 2); +signal is1_axu_ld_or_st_d : std_ulogic; +signal is1_axu_store_d : std_ulogic; +signal is1_axu_ldst_size_d : std_ulogic_vector(0 to 5); +signal is1_axu_ldst_update_d : std_ulogic; +signal is1_axu_ldst_extpid_d : std_ulogic; +signal is1_axu_ldst_forcealign_d : std_ulogic; +signal is1_axu_ldst_forceexcept_d : std_ulogic; +signal is1_axu_mftgpr_d : std_ulogic; +signal is1_axu_mffgpr_d : std_ulogic; +signal is1_axu_movedp_d : std_ulogic; +signal is1_axu_instr_type_d : std_ulogic_vector(0 to 2); +signal is1_axu_ldst_ra_v_d : std_ulogic; +signal is1_axu_ldst_rb_v_d : std_ulogic; +signal is1_force_ram_d : std_ulogic; +signal is1_2ucode_d : std_ulogic; +signal is1_2ucode_type_d : std_ulogic; +signal is1_vld_L2 : std_ulogic; +signal is1_vld_type_L2 : std_ulogic_vector(0 to 2); +signal is1_instr_L2 : std_ulogic_vector(0 to 31); +signal is1_axu_instr_L2 : std_ulogic_vector(6 to 31); +signal is1_ta_vld_L2 : std_ulogic; +signal is1_ta_L2 : std_ulogic_vector(0 to 5); +signal is1_s1_vld_L2 : std_ulogic; +signal is1_s1_L2 : std_ulogic_vector(0 to 5); +signal is1_s2_vld_L2 : std_ulogic; +signal is1_s2_L2 : std_ulogic_vector(0 to 5); +signal is1_s3_vld_L2 : std_ulogic; +signal is1_s3_L2 : std_ulogic_vector(0 to 5); +signal is1_pred_update_L2 : std_ulogic; +signal is1_pred_taken_cnt_L2 : std_ulogic_vector(0 to 1); +signal is1_gshare_L2 : std_ulogic_vector(0 to 3); +signal is1_UpdatesLR_L2 : std_ulogic; +signal is1_UpdatesCR_L2 : std_ulogic; +signal is1_UpdatesCTR_L2 : std_ulogic; +signal is1_UpdatesXER_L2 : std_ulogic; +signal is1_UpdatesMSR_L2 : std_ulogic; +signal is1_UpdatesSPR_L2 : std_ulogic; +signal is1_UsesLR_L2 : std_ulogic; +signal is1_UsesCR_L2 : std_ulogic; +signal is1_UsesCTR_L2 : std_ulogic; +signal is1_UsesXER_L2 : std_ulogic; +signal is1_UsesMSR_L2 : std_ulogic; +signal is1_UsesSPR_L2 : std_ulogic; +signal is1_ld_vld_L2 : std_ulogic; +signal is1_to_ucode_L2 : std_ulogic; +signal is1_is_ucode_L2 : std_ulogic; +signal is1_ifar_L2 : EFF_IFAR; +signal is1_error_L2 : std_ulogic_vector(0 to 2); +signal is1_axu_ld_or_st_L2 : std_ulogic; +signal is1_axu_store_L2 : std_ulogic; +signal is1_axu_ldst_size_L2 : std_ulogic_vector(0 to 5); +signal is1_axu_ldst_update_L2 : std_ulogic; +signal is1_axu_ldst_extpid_L2 : std_ulogic; +signal is1_axu_ldst_forcealign_L2 : std_ulogic; +signal is1_axu_ldst_forceexcept_L2 : std_ulogic; +signal is1_axu_mftgpr_L2 : std_ulogic; +signal is1_axu_mffgpr_L2 : std_ulogic; +signal is1_axu_movedp_L2 : std_ulogic; +signal is1_axu_instr_type_L2 : std_ulogic_vector(0 to 2); +signal is1_axu_ldst_ra_v_L2 : std_ulogic; +signal is1_axu_ldst_rb_v_L2 : std_ulogic; +signal is1_force_ram_L2 : std_ulogic; +signal is1_2ucode_L2 : std_ulogic; +signal is1_2ucode_type_L2 : std_ulogic; +signal is1_vld_din : std_ulogic; +signal is1_vld_type_din : std_ulogic_vector(0 to 2); +signal is1_instr_din : std_ulogic_vector(0 to 31); +signal is1_axu_instr_din : std_ulogic_vector(6 to 31); +signal is1_ta_vld_din : std_ulogic; +signal is1_ta_din : std_ulogic_vector(0 to 5); +signal is1_s1_vld_din : std_ulogic; +signal is1_s1_din : std_ulogic_vector(0 to 5); +signal is1_s2_vld_din : std_ulogic; +signal is1_s2_din : std_ulogic_vector(0 to 5); +signal is1_s3_vld_din : std_ulogic; +signal is1_s3_din : std_ulogic_vector(0 to 5); +signal is1_pred_update_din : std_ulogic; +signal is1_pred_taken_cnt_din : std_ulogic_vector(0 to 1); +signal is1_gshare_din : std_ulogic_vector(0 to 3); +signal is1_UpdatesLR_din : std_ulogic; +signal is1_UpdatesCR_din : std_ulogic; +signal is1_UpdatesCTR_din : std_ulogic; +signal is1_UpdatesXER_din : std_ulogic; +signal is1_UpdatesMSR_din : std_ulogic; +signal is1_UpdatesSPR_din : std_ulogic; +signal is1_UsesLR_din : std_ulogic; +signal is1_UsesCR_din : std_ulogic; +signal is1_UsesCTR_din : std_ulogic; +signal is1_UsesXER_din : std_ulogic; +signal is1_UsesMSR_din : std_ulogic; +signal is1_UsesSPR_din : std_ulogic; +signal is1_ld_vld_din : std_ulogic; +signal is1_to_ucode_din : std_ulogic; +signal is1_is_ucode_din : std_ulogic; +signal is1_ifar_din : EFF_IFAR; +signal is1_error_din : std_ulogic_vector(0 to 2); +signal is1_axu_ld_or_st_din : std_ulogic; +signal is1_axu_store_din : std_ulogic; +signal is1_axu_ldst_size_din : std_ulogic_vector(0 to 5); +signal is1_axu_ldst_update_din : std_ulogic; +signal is1_axu_ldst_extpid_din : std_ulogic; +signal is1_axu_ldst_forcealign_din : std_ulogic; +signal is1_axu_ldst_forceexcept_din : std_ulogic; +signal is1_axu_mftgpr_din : std_ulogic; +signal is1_axu_mffgpr_din : std_ulogic; +signal is1_axu_movedp_din : std_ulogic; +signal is1_axu_instr_type_din : std_ulogic_vector(0 to 2); +signal is1_axu_ldst_ra_v_din : std_ulogic; +signal is1_axu_ldst_rb_v_din : std_ulogic; +signal is1_force_ram_din : std_ulogic; +signal is1_2ucode_din : std_ulogic; +signal is1_2ucode_type_din : std_ulogic; +signal act_valid : std_ulogic; +signal act_nonvalid : std_ulogic; +signal is1_ta_d0 : std_ulogic_vector(0 to 5); +signal is1_s1_d0 : std_ulogic_vector(0 to 5); +signal is1_s2_d0 : std_ulogic_vector(0 to 5); +signal is1_s3_d0 : std_ulogic_vector(0 to 5); +signal core64 : std_ulogic; +signal au_iu_i_dec : std_ulogic; +signal au_ib1_ld_or_st : std_ulogic; +signal au_ib1_store : std_ulogic; +signal unused : std_ulogic_vector(0 to 1); +-- synopsys translate_off +-- synopsys translate_on + BEGIN --@@ START OF EXECUTABLE CODE FOR IUQ_FXU_DECODE + +unused(0) <= au_iu_ib1_ldst_ra(0); +unused(1) <= au_iu_ib1_ldst_rb(0); +----------------------------------------------------------------------- +tiup <= '1'; +au_iu_i_dec <= not au_iu_i_dec_b and (not (au_iu_is0_ucode_only and not iu_au_ib1_instr_is_ucode) or (pc_au_ram_mode and pc_au_ram_thread_v)); +au_ib1_ld_or_st <= au_iu_ib1_ldst_v and (not (au_iu_is0_ucode_only and not iu_au_ib1_instr_is_ucode) or (pc_au_ram_mode and pc_au_ram_thread_v)); +au_ib1_store <= au_iu_ib1_store and (not (au_iu_is0_ucode_only and not iu_au_ib1_instr_is_ucode) or (pc_au_ram_mode and pc_au_ram_thread_v)); +fdec_ibuf_stall <= fdep_fdec_buff_stall and iu_au_ib1_instr_vld and not xu_iu_ib1_flush; +--64-bit mode +c64: if (regmode = 6) generate +begin +core64 <= '1'; +end generate; +--32-bit core +c32: if (regmode = 5) generate +begin +core64 <= '0'; +end generate; +--------------------------------------------------------------------------------------------------------- +-- branch dependency. branches bite. branches can update LR and CTR, and can use LR, CR, and CTR. +--------------------------------------------------------------------------------------------------------- +--------------------------------------------------------------------------------------------------------- +-- Main Instruction Decoder. Select and Type definitions +--------------------------------------------------------------------------------------------------------- +---------------------------- +-- ucode table +---------------------------- +-- +-- Final Table Listing +-- *INPUTS*====================================*OUTPUTS*=========================* +-- | | | +-- | | UpdatesLR | +-- | | | UpdatesCR | +-- | | | | UpdatesCTR | +-- | | | | | UpdatesXER | +-- | core64 | | | | | UpdatesMSR | +-- | | | | | | | | UpdatesSPR | +-- | | iu_au_ib1_instr | | | | | | | UsesLR | +-- | | | iu_au_ib1_instr | | | | | | | | UsesCR | +-- | | | | iu_au_ib1_instr | | | | | | | | | UsesCTR | +-- | | | | | iu_au_ib1_instr | | | | | | | | | | UsesXER | +-- | | | | | | | | | | | | | | | | | UsesMSR | +-- | | | | | | | | | | | | | | | | | | UsesSPR | +-- | | | | 1111111112 22222222233 | | | | | | | | | | | | | | +-- | | 012345 8 1234567890 12345678901 | | | | | | | | | | | | | | +-- *TYPE*======================================+=================================+ +-- | P PPPPPP P PPPPPPPPPP PPPPPPPPPPP | S S S S S S S S S S S S | +-- *POLARITY*--------------------------------->| + + + + + + + + + + + + | +-- *PHASE*------------------------------------>| T T T T T T T T T T T T | +-- *TERMS*=====================================+=================================+ +-- 1 | - 011111 - 0100000000 0111010011- | 1 . . . . . . . . . . . | +-- 2 | - 011111 - 0100100000 0111010011- | . . 1 . . . . . . . . . | +-- 3 | - 011111 - 0100000000 0101010011- | . . . . . . 1 . . . . . | +-- 4 | - 011111 - 0100100000 0101010011- | . . . . . . . . 1 . . . | +-- 5 | - 011111 - 0000100000 0111010011- | . . . 1 . . . . . . . . | +-- 6 | - 0111-1 - 0000100000 0101010011- | . . . . . . . . . 1 . . | +-- 7 | - 01001- - ---------- 00000100001 | 1 . . . . . . . . . . . | +-- 8 | - 010011 1 ---------- 1000010000- | . . . . . . . 1 1 . . . | +-- 9 | - 01001- 1 ---------- -0000100001 | 1 . . . . . . . . . . . | +-- 10 | - 010011 0 ---------- 0000010000- | . . 1 . . . . . 1 . . . | +-- 11 | - 010011 - ---------- 000-100110- | . . . . 1 . . . . . . 1 | +-- 12 | - 010011 - ---------- 0000010000- | . . . . . . 1 1 . . . . | +-- 13 | - 011111 - ---------- 1110110110- | . . . . . . . . . . 1 1 | +-- 14 | - 01-1-1 - ---------- 11101101101 | . 1 . . . . . . . 1 . . | +-- 15 | - 011111 - ---------1 0111010011- | . . . . . 1 . . . . . . | +-- 16 | - 011111 - --------1- 0111010011- | . . . . . 1 . . . . . . | +-- 17 | - 011111 - -------1-- 0111010011- | . . . . . 1 . . . . . . | +-- 18 | - 011111 - ------1--- 0111010011- | . . . . . 1 . . . . . . | +-- 19 | - 011111 - -----1---- 0111010011- | . . . . . 1 . . . . . . | +-- 20 | - 011111 - ---1------ 0111010011- | . . . . . 1 . . . . . . | +-- 21 | - 011111 - --1------- 0111010011- | . . . . . 1 . . . . . . | +-- 22 | - 011111 - 1--------- 0111010011- | . . . . . 1 . . . . . . | +-- 23 | - 010011 - ---------- 0000000000- | . 1 . . . . . 1 . . . . | +-- 24 | 1 011111 - ---------- 110011101-- | . . . 1 . . . . . . . . | +-- 25 | 1 01-1-1 - ---------- 110011101-1 | . 1 . . . . . . . 1 . . | +-- 26 | 1 011111 - ---------- 10111010--- | . . . 1 . . . . . . . . | +-- 27 | - 011111 - ---------- 00110101001 | . 1 . . . 1 . . . 1 . . | +-- 28 | - 010011 - ---------- 0-00100001- | . 1 . . . . . 1 . . . . | +-- 29 | - 010011 - ---------- 01-0100001- | . 1 . . . . . 1 . . . . | +-- 30 | - 010011 - ---------- 000011001-- | . . . . 1 . . . . . . 1 | +-- 31 | - 011111 - ---------- 100-101000- | . . . 1 . . . . . . . . | +-- 32 | - 010011 - ---------- 0011-00001- | . 1 . . . . . 1 . . . . | +-- 33 | - 011111 - ---------- 0110010110- | . . . . . . . . . . 1 1 | +-- 34 | - 011111 - ---------- 1110-00110- | . . . . . . . . . . . 1 | +-- 35 | 1 0111-- - ---------- 00110101-01 | . 1 . . . . . . . 1 . . | +-- 36 | - 010011 - ---------- 0-11000001- | . 1 . . . . . 1 . . . . | +-- 37 | - 011111 - ---------- 101110101-- | . . . 1 . . . . . . . . | +-- 38 | - 010011 - ---------- 001-000001- | . 1 . . . . . 1 . . . . | +-- 39 | - 010011 - ---------- 0100-00001- | . 1 . . . . . 1 . . . . | +-- 40 | - 011111 - ---------1 0101-10011- | . . . . . . . . . . . 1 | +-- 41 | - 011111 - --------1- 0101-10011- | . . . . . . . . . . . 1 | +-- 42 | - 011111 - -------1-- 0101-10011- | . . . . . . . . . . . 1 | +-- 43 | - 011111 - ------1--- 0101-10011- | . . . . . . . . . . . 1 | +-- 44 | - 011111 - -----1---- 0101-10011- | . . . . . . . . . . . 1 | +-- 45 | - 011111 - ---1------ 0101-10011- | . . . . . . . . . . . 1 | +-- 46 | - 011111 - --1------- 0101-10011- | . . . . . . . . . . . 1 | +-- 47 | - 011111 - 1--------- 0101-10011- | . . . . . . . . . . . 1 | +-- 48 | - 0111-1 - ---------- 1110000110- | . 1 . . . . . . . 1 . . | +-- 49 | - 011111 - ---------- 0101110011- | . . . . . . . . . . . 1 | +-- 50 | 1 011111 - ---------- 1100-110-0- | . . . 1 . . . . . . . . | +-- 51 | 1 01-1-1 - ---------- 1100-110-01 | . 1 . . . . . . . 1 . . | +-- 52 | - 011111 - ---------- 0001010011- | . . . . . . . . . . 1 . | +-- 53 | - 011111 - ---------- 1100-11000- | . . . 1 . . . . . . . . | +-- 54 | - 011111 - ---------- 0010010010- | . . . . 1 . . . . . . . | +-- 55 | - 011111 - ---------- 1-00001010- | . . . 1 . . . . . . . . | +-- 56 | - 01-1-1 - ---------- 1100-110001 | . 1 . . . . . . . 1 . . | +-- 57 | - 011111 - ---------- 0000010011- | . . . . . . . 1 . . . . | +-- 58 | - 0111-1 - ---------- 10-0010101- | . . . . . . . . . 1 . . | +-- 59 | - 01-1-1 - ---------- 000-1111001 | . 1 . . . . . . . 1 . . | +-- 60 | - 011111 - ---------- 1000000000- | . 1 . 1 . . . . . 1 . . | +-- 61 | 1 011111 - ---------- 111--010-1- | . . . 1 . . . . . . . . | +-- 62 | 1 01-1-1 - ---------- 111-0110101 | . 1 . . . . . . . 1 . . | +-- 63 | - 01-1-1 - ---------- 11010100101 | . 1 . . . . . . . . . . | +-- 64 | - 011111 - ---------- 0010-00011- | . . . . 1 . . . . . . . | +-- 65 | 1 01-1-1 - ---------- 0000-110101 | . 1 . . . . . . . 1 . . | +-- 66 | - 0111-1 - ---------- 0010010000- | . 1 . . . . . . . . . . | +-- 67 | - 01-1-1 - ---------- 011-0111001 | . 1 . . . . . . . 1 . . | +-- 68 | - 01-1-1 - ---------- 00100100111 | . 1 . . . . . . . . . . | +-- 69 | - 011111 - ---------- 111--01011- | . . . 1 . . . . . . . . | +-- 70 | - 01-1-1 - ---------- 111001-0101 | . 1 . . . . . . . . . . | +-- 71 | - 01-1-1 - ---------- -011-010-01 | . 1 . . . . . . . . . . | +-- 72 | 1 01-1-1 - ---------- -0000-10111 | . 1 . . . . . . . 1 . . | +-- 73 | 1 01-1-1 - ---------- -0111010--1 | . 1 . . . . . . . 1 . . | +-- 74 | - 01-1-1 - ---------- 0-100101101 | . 1 . . . . . . . 1 . . | +-- 75 | - 01-1-1 - ---------- -01-0010-01 | . 1 . . . . . . . . . . | +-- 76 | - 01-1-1 - ---------- 1110-110101 | . 1 . . . . . . . 1 . . | +-- 77 | - 01-1-1 - ---------- 0-00-111001 | . 1 . . . . . . . 1 . . | +-- 78 | - 01-1-1 - ---------- 01-0-111001 | . 1 . . . . . . . 1 . . | +-- 79 | - 01-1-1 - ---------- -00-1010001 | . 1 . . . . . . . 1 . . | +-- 80 | - 01-1-1 - ---------- -01110101-1 | . 1 . . . . . . . 1 . . | +-- 81 | - 011111 - ---------- -0-00010-0- | . . . 1 . . . . . . . . | +-- 82 | - 0111-1 - ---------- 0000-00000- | . 1 . . . . . . . 1 . . | +-- 83 | 1 01-1-1 - ---------- -00-0010-11 | . 1 . . . . . . . 1 . . | +-- 84 | - 01-1-1 - ---------- -0000-10001 | . 1 . . . . . . . 1 . . | +-- 85 | - 0111-1 - ---------- -01-0010-0- | . . . . . . . . . 1 . . | +-- 86 | - 011111 - ---------- -011-010-0- | . . . 1 . . . . . 1 . . | +-- 87 | - 01-1-1 - ---------- --000010101 | . 1 . . . . . . . 1 . . | +-- 88 | - 01-1-1 - ---------- -00-0010111 | . 1 . . . . . . . 1 . . | +-- 89 | - 010000 0 ---------- ----------- | . . 1 . . . . . 1 . . . | +-- 90 | - 01-1-1 - ---------- 00000-10-01 | . 1 . . . . . . . 1 . . | +-- 91 | 1 01-1-1 - ---------- -11--010-11 | . 1 . . . . . . . 1 . . | +-- 92 | - 011111 - ---------- -----01111- | . . . . . . . 1 . . . . | +-- 93 | - 01-1-1 - ---------- 000--000111 | . 1 . . . . . . . 1 . . | +-- 94 | - 01-1-1 - ---------- -11--010111 | . 1 . . . . . . . 1 . . | +-- 95 | - 010000 - ---------- ----------- | . . . . . . . 1 . . . . | +-- 96 | - 0100-0 - ---------- ----------1 | 1 . . . . . . . . . . . | +-- 97 | 1 0111-0 - ---------- -------00-1 | . 1 . . . . . . . 1 . . | +-- 98 | - 001-00 - ---------- ----------- | . . . 1 . . . . . . . . | +-- 99 | - 010001 - ---------- ---------1- | . . . . 1 1 . . . . 1 . | +-- 100 | 1 0111-0 - ---------- ------0---1 | . 1 . . . . . . . 1 . . | +-- 101 | - 00101- - ---------- ----------- | . 1 . . . . . . . 1 . . | +-- 102 | - 001101 - ---------- ----------- | . 1 . 1 . . . . . 1 . . | +-- 103 | - 01-10- - ---------- ----------1 | . 1 . . . . . . . 1 . . | +-- 104 | - 0101-1 - ---------- ----------1 | . 1 . . . . . . . 1 . . | +-- 105 | - 01110- - ---------- ----------- | . 1 . . . . . . . 1 . . | +-- *=============================================================================* +-- +-- Table BR_DEP Signal Assignments for Product Terms +MQQ1:BR_DEP_PT(1) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(11) & IU_AU_IB1_INSTR(12) & + IU_AU_IB1_INSTR(13) & IU_AU_IB1_INSTR(14) & + IU_AU_IB1_INSTR(15) & IU_AU_IB1_INSTR(16) & + IU_AU_IB1_INSTR(17) & IU_AU_IB1_INSTR(18) & + IU_AU_IB1_INSTR(19) & IU_AU_IB1_INSTR(20) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("01111101000000000111010011")); +MQQ2:BR_DEP_PT(2) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(11) & IU_AU_IB1_INSTR(12) & + IU_AU_IB1_INSTR(13) & IU_AU_IB1_INSTR(14) & + IU_AU_IB1_INSTR(15) & IU_AU_IB1_INSTR(16) & + IU_AU_IB1_INSTR(17) & IU_AU_IB1_INSTR(18) & + IU_AU_IB1_INSTR(19) & IU_AU_IB1_INSTR(20) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("01111101001000000111010011")); +MQQ3:BR_DEP_PT(3) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(11) & IU_AU_IB1_INSTR(12) & + IU_AU_IB1_INSTR(13) & IU_AU_IB1_INSTR(14) & + IU_AU_IB1_INSTR(15) & IU_AU_IB1_INSTR(16) & + IU_AU_IB1_INSTR(17) & IU_AU_IB1_INSTR(18) & + IU_AU_IB1_INSTR(19) & IU_AU_IB1_INSTR(20) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("01111101000000000101010011")); +MQQ4:BR_DEP_PT(4) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(11) & IU_AU_IB1_INSTR(12) & + IU_AU_IB1_INSTR(13) & IU_AU_IB1_INSTR(14) & + IU_AU_IB1_INSTR(15) & IU_AU_IB1_INSTR(16) & + IU_AU_IB1_INSTR(17) & IU_AU_IB1_INSTR(18) & + IU_AU_IB1_INSTR(19) & IU_AU_IB1_INSTR(20) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("01111101001000000101010011")); +MQQ5:BR_DEP_PT(5) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(11) & IU_AU_IB1_INSTR(12) & + IU_AU_IB1_INSTR(13) & IU_AU_IB1_INSTR(14) & + IU_AU_IB1_INSTR(15) & IU_AU_IB1_INSTR(16) & + IU_AU_IB1_INSTR(17) & IU_AU_IB1_INSTR(18) & + IU_AU_IB1_INSTR(19) & IU_AU_IB1_INSTR(20) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("01111100001000000111010011")); +MQQ6:BR_DEP_PT(6) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(11) & + IU_AU_IB1_INSTR(12) & IU_AU_IB1_INSTR(13) & + IU_AU_IB1_INSTR(14) & IU_AU_IB1_INSTR(15) & + IU_AU_IB1_INSTR(16) & IU_AU_IB1_INSTR(17) & + IU_AU_IB1_INSTR(18) & IU_AU_IB1_INSTR(19) & + IU_AU_IB1_INSTR(20) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("0111100001000000101010011")); +MQQ7:BR_DEP_PT(7) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) & IU_AU_IB1_INSTR(31) + ) , STD_ULOGIC_VECTOR'("0100100000100001")); +MQQ8:BR_DEP_PT(8) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(8) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("01001111000010000")); +MQQ9:BR_DEP_PT(9) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(8) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) & IU_AU_IB1_INSTR(31) + ) , STD_ULOGIC_VECTOR'("0100110000100001")); +MQQ10:BR_DEP_PT(10) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(8) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("01001100000010000")); +MQQ11:BR_DEP_PT(11) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("010011000100110")); +MQQ12:BR_DEP_PT(12) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("0100110000010000")); +MQQ13:BR_DEP_PT(13) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("0111111110110110")); +MQQ14:BR_DEP_PT(14) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) & + IU_AU_IB1_INSTR(31) ) , STD_ULOGIC_VECTOR'("011111101101101")); +MQQ15:BR_DEP_PT(15) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(20) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("01111110111010011")); +MQQ16:BR_DEP_PT(16) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(19) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("01111110111010011")); +MQQ17:BR_DEP_PT(17) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(18) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("01111110111010011")); +MQQ18:BR_DEP_PT(18) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(17) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("01111110111010011")); +MQQ19:BR_DEP_PT(19) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(16) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("01111110111010011")); +MQQ20:BR_DEP_PT(20) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(14) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("01111110111010011")); +MQQ21:BR_DEP_PT(21) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(13) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("01111110111010011")); +MQQ22:BR_DEP_PT(22) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(11) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("01111110111010011")); +MQQ23:BR_DEP_PT(23) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("0100110000000000")); +MQQ24:BR_DEP_PT(24) <= + Eq(( CORE64 & IU_AU_IB1_INSTR(0) & + IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) + ) , STD_ULOGIC_VECTOR'("1011111110011101")); +MQQ25:BR_DEP_PT(25) <= + Eq(( CORE64 & IU_AU_IB1_INSTR(0) & + IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(31) ) , STD_ULOGIC_VECTOR'("101111100111011")); +MQQ26:BR_DEP_PT(26) <= + Eq(( CORE64 & IU_AU_IB1_INSTR(0) & + IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) ) , STD_ULOGIC_VECTOR'("101111110111010")); +MQQ27:BR_DEP_PT(27) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) & + IU_AU_IB1_INSTR(31) ) , STD_ULOGIC_VECTOR'("01111100110101001")); +MQQ28:BR_DEP_PT(28) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("010011000100001")); +MQQ29:BR_DEP_PT(29) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("010011010100001")); +MQQ30:BR_DEP_PT(30) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) ) , STD_ULOGIC_VECTOR'("010011000011001")); +MQQ31:BR_DEP_PT(31) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("011111100101000")); +MQQ32:BR_DEP_PT(32) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("010011001100001")); +MQQ33:BR_DEP_PT(33) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("0111110110010110")); +MQQ34:BR_DEP_PT(34) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("011111111000110")); +MQQ35:BR_DEP_PT(35) <= + Eq(( CORE64 & IU_AU_IB1_INSTR(0) & + IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(30) & + IU_AU_IB1_INSTR(31) ) , STD_ULOGIC_VECTOR'("101110011010101")); +MQQ36:BR_DEP_PT(36) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("010011011000001")); +MQQ37:BR_DEP_PT(37) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) ) , STD_ULOGIC_VECTOR'("011111101110101")); +MQQ38:BR_DEP_PT(38) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("010011001000001")); +MQQ39:BR_DEP_PT(39) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("010011010000001")); +MQQ40:BR_DEP_PT(40) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(20) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("0111111010110011")); +MQQ41:BR_DEP_PT(41) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(19) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("0111111010110011")); +MQQ42:BR_DEP_PT(42) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(18) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("0111111010110011")); +MQQ43:BR_DEP_PT(43) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(17) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("0111111010110011")); +MQQ44:BR_DEP_PT(44) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(16) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("0111111010110011")); +MQQ45:BR_DEP_PT(45) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(14) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("0111111010110011")); +MQQ46:BR_DEP_PT(46) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(13) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("0111111010110011")); +MQQ47:BR_DEP_PT(47) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(11) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("0111111010110011")); +MQQ48:BR_DEP_PT(48) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("011111110000110")); +MQQ49:BR_DEP_PT(49) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("0111110101110011")); +MQQ50:BR_DEP_PT(50) <= + Eq(( CORE64 & IU_AU_IB1_INSTR(0) & + IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("101111111001100")); +MQQ51:BR_DEP_PT(51) <= + Eq(( CORE64 & IU_AU_IB1_INSTR(0) & + IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(30) & IU_AU_IB1_INSTR(31) + ) , STD_ULOGIC_VECTOR'("10111110011001")); +MQQ52:BR_DEP_PT(52) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("0111110001010011")); +MQQ53:BR_DEP_PT(53) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("011111110011000")); +MQQ54:BR_DEP_PT(54) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("0111110010010010")); +MQQ55:BR_DEP_PT(55) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("011111100001010")); +MQQ56:BR_DEP_PT(56) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) & IU_AU_IB1_INSTR(31) + ) , STD_ULOGIC_VECTOR'("01111100110001")); +MQQ57:BR_DEP_PT(57) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("0111110000010011")); +MQQ58:BR_DEP_PT(58) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("01111100010101")); +MQQ59:BR_DEP_PT(59) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) & IU_AU_IB1_INSTR(31) + ) , STD_ULOGIC_VECTOR'("01110001111001")); +MQQ60:BR_DEP_PT(60) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("0111111000000000")); +MQQ61:BR_DEP_PT(61) <= + Eq(( CORE64 & IU_AU_IB1_INSTR(0) & + IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("10111111110101")); +MQQ62:BR_DEP_PT(62) <= + Eq(( CORE64 & IU_AU_IB1_INSTR(0) & + IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) & + IU_AU_IB1_INSTR(31) ) , STD_ULOGIC_VECTOR'("101111110110101")); +MQQ63:BR_DEP_PT(63) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) & + IU_AU_IB1_INSTR(31) ) , STD_ULOGIC_VECTOR'("011111010100101")); +MQQ64:BR_DEP_PT(64) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("011111001000011")); +MQQ65:BR_DEP_PT(65) <= + Eq(( CORE64 & IU_AU_IB1_INSTR(0) & + IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) & + IU_AU_IB1_INSTR(31) ) , STD_ULOGIC_VECTOR'("101110000110101")); +MQQ66:BR_DEP_PT(66) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("011110010010000")); +MQQ67:BR_DEP_PT(67) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) & IU_AU_IB1_INSTR(31) + ) , STD_ULOGIC_VECTOR'("01110110111001")); +MQQ68:BR_DEP_PT(68) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) & + IU_AU_IB1_INSTR(31) ) , STD_ULOGIC_VECTOR'("011100100100111")); +MQQ69:BR_DEP_PT(69) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("01111111101011")); +MQQ70:BR_DEP_PT(70) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) & IU_AU_IB1_INSTR(31) + ) , STD_ULOGIC_VECTOR'("01111110010101")); +MQQ71:BR_DEP_PT(71) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(30) & IU_AU_IB1_INSTR(31) + ) , STD_ULOGIC_VECTOR'("011101101001")); +MQQ72:BR_DEP_PT(72) <= + Eq(( CORE64 & IU_AU_IB1_INSTR(0) & + IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) & IU_AU_IB1_INSTR(31) + ) , STD_ULOGIC_VECTOR'("10111000010111")); +MQQ73:BR_DEP_PT(73) <= + Eq(( CORE64 & IU_AU_IB1_INSTR(0) & + IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(31) ) , STD_ULOGIC_VECTOR'("1011101110101")); +MQQ74:BR_DEP_PT(74) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) & IU_AU_IB1_INSTR(31) + ) , STD_ULOGIC_VECTOR'("01110100101101")); +MQQ75:BR_DEP_PT(75) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(30) & IU_AU_IB1_INSTR(31) + ) , STD_ULOGIC_VECTOR'("011101001001")); +MQQ76:BR_DEP_PT(76) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) & IU_AU_IB1_INSTR(31) + ) , STD_ULOGIC_VECTOR'("01111110110101")); +MQQ77:BR_DEP_PT(77) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) & + IU_AU_IB1_INSTR(31) ) , STD_ULOGIC_VECTOR'("0111000111001")); +MQQ78:BR_DEP_PT(78) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) & + IU_AU_IB1_INSTR(31) ) , STD_ULOGIC_VECTOR'("0111010111001")); +MQQ79:BR_DEP_PT(79) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) & + IU_AU_IB1_INSTR(31) ) , STD_ULOGIC_VECTOR'("0111001010001")); +MQQ80:BR_DEP_PT(80) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(31) ) , STD_ULOGIC_VECTOR'("0111011101011")); +MQQ81:BR_DEP_PT(81) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("0111110000100")); +MQQ82:BR_DEP_PT(82) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("01111000000000")); +MQQ83:BR_DEP_PT(83) <= + Eq(( CORE64 & IU_AU_IB1_INSTR(0) & + IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(30) & + IU_AU_IB1_INSTR(31) ) , STD_ULOGIC_VECTOR'("1011100001011")); +MQQ84:BR_DEP_PT(84) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) & + IU_AU_IB1_INSTR(31) ) , STD_ULOGIC_VECTOR'("0111000010001")); +MQQ85:BR_DEP_PT(85) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("011110100100")); +MQQ86:BR_DEP_PT(86) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("0111110110100")); +MQQ87:BR_DEP_PT(87) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) & + IU_AU_IB1_INSTR(31) ) , STD_ULOGIC_VECTOR'("0111000010101")); +MQQ88:BR_DEP_PT(88) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) & + IU_AU_IB1_INSTR(31) ) , STD_ULOGIC_VECTOR'("0111000010111")); +MQQ89:BR_DEP_PT(89) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(8) ) , STD_ULOGIC_VECTOR'("0100000")); +MQQ90:BR_DEP_PT(90) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(30) & + IU_AU_IB1_INSTR(31) ) , STD_ULOGIC_VECTOR'("0111000001001")); +MQQ91:BR_DEP_PT(91) <= + Eq(( CORE64 & IU_AU_IB1_INSTR(0) & + IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(30) & IU_AU_IB1_INSTR(31) + ) , STD_ULOGIC_VECTOR'("101111101011")); +MQQ92:BR_DEP_PT(92) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("01111101111")); +MQQ93:BR_DEP_PT(93) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) & + IU_AU_IB1_INSTR(31) ) , STD_ULOGIC_VECTOR'("0111000000111")); +MQQ94:BR_DEP_PT(94) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) & IU_AU_IB1_INSTR(31) + ) , STD_ULOGIC_VECTOR'("011111010111")); +MQQ95:BR_DEP_PT(95) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) + ) , STD_ULOGIC_VECTOR'("010000")); +MQQ96:BR_DEP_PT(96) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(31) + ) , STD_ULOGIC_VECTOR'("010001")); +MQQ97:BR_DEP_PT(97) <= + Eq(( CORE64 & IU_AU_IB1_INSTR(0) & + IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(31) ) , STD_ULOGIC_VECTOR'("101110001")); +MQQ98:BR_DEP_PT(98) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) ) , STD_ULOGIC_VECTOR'("00100")); +MQQ99:BR_DEP_PT(99) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("0100011")); +MQQ100:BR_DEP_PT(100) <= + Eq(( CORE64 & IU_AU_IB1_INSTR(0) & + IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(31) + ) , STD_ULOGIC_VECTOR'("10111001")); +MQQ101:BR_DEP_PT(101) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) ) , STD_ULOGIC_VECTOR'("00101")); +MQQ102:BR_DEP_PT(102) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) + ) , STD_ULOGIC_VECTOR'("001101")); +MQQ103:BR_DEP_PT(103) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(31) ) , STD_ULOGIC_VECTOR'("01101")); +MQQ104:BR_DEP_PT(104) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(31) + ) , STD_ULOGIC_VECTOR'("010111")); +MQQ105:BR_DEP_PT(105) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) ) , STD_ULOGIC_VECTOR'("01110")); +-- Table BR_DEP Signal Assignments for Outputs +MQQ106:UPDATESLR <= + (BR_DEP_PT(1) OR BR_DEP_PT(7) + OR BR_DEP_PT(9) OR BR_DEP_PT(96) + ); +MQQ107:UPDATESCR <= + (BR_DEP_PT(14) OR BR_DEP_PT(23) + OR BR_DEP_PT(25) OR BR_DEP_PT(27) + OR BR_DEP_PT(28) OR BR_DEP_PT(29) + OR BR_DEP_PT(32) OR BR_DEP_PT(35) + OR BR_DEP_PT(36) OR BR_DEP_PT(38) + OR BR_DEP_PT(39) OR BR_DEP_PT(48) + OR BR_DEP_PT(51) OR BR_DEP_PT(56) + OR BR_DEP_PT(59) OR BR_DEP_PT(60) + OR BR_DEP_PT(62) OR BR_DEP_PT(63) + OR BR_DEP_PT(65) OR BR_DEP_PT(66) + OR BR_DEP_PT(67) OR BR_DEP_PT(68) + OR BR_DEP_PT(70) OR BR_DEP_PT(71) + OR BR_DEP_PT(72) OR BR_DEP_PT(73) + OR BR_DEP_PT(74) OR BR_DEP_PT(75) + OR BR_DEP_PT(76) OR BR_DEP_PT(77) + OR BR_DEP_PT(78) OR BR_DEP_PT(79) + OR BR_DEP_PT(80) OR BR_DEP_PT(82) + OR BR_DEP_PT(83) OR BR_DEP_PT(84) + OR BR_DEP_PT(87) OR BR_DEP_PT(88) + OR BR_DEP_PT(90) OR BR_DEP_PT(91) + OR BR_DEP_PT(93) OR BR_DEP_PT(94) + OR BR_DEP_PT(97) OR BR_DEP_PT(100) + OR BR_DEP_PT(101) OR BR_DEP_PT(102) + OR BR_DEP_PT(103) OR BR_DEP_PT(104) + OR BR_DEP_PT(105)); +MQQ108:UPDATESCTR <= + (BR_DEP_PT(2) OR BR_DEP_PT(10) + OR BR_DEP_PT(89)); +MQQ109:UPDATESXER <= + (BR_DEP_PT(5) OR BR_DEP_PT(24) + OR BR_DEP_PT(26) OR BR_DEP_PT(31) + OR BR_DEP_PT(37) OR BR_DEP_PT(50) + OR BR_DEP_PT(53) OR BR_DEP_PT(55) + OR BR_DEP_PT(60) OR BR_DEP_PT(61) + OR BR_DEP_PT(69) OR BR_DEP_PT(81) + OR BR_DEP_PT(86) OR BR_DEP_PT(98) + OR BR_DEP_PT(102)); +MQQ110:UPDATESMSR <= + (BR_DEP_PT(11) OR BR_DEP_PT(30) + OR BR_DEP_PT(54) OR BR_DEP_PT(64) + OR BR_DEP_PT(99)); +MQQ111:UPDATESSPR <= + (BR_DEP_PT(15) OR BR_DEP_PT(16) + OR BR_DEP_PT(17) OR BR_DEP_PT(18) + OR BR_DEP_PT(19) OR BR_DEP_PT(20) + OR BR_DEP_PT(21) OR BR_DEP_PT(22) + OR BR_DEP_PT(27) OR BR_DEP_PT(99) + ); +MQQ112:USESLR <= + (BR_DEP_PT(3) OR BR_DEP_PT(12) + ); +MQQ113:USESCR <= + (BR_DEP_PT(8) OR BR_DEP_PT(12) + OR BR_DEP_PT(23) OR BR_DEP_PT(28) + OR BR_DEP_PT(29) OR BR_DEP_PT(32) + OR BR_DEP_PT(36) OR BR_DEP_PT(38) + OR BR_DEP_PT(39) OR BR_DEP_PT(57) + OR BR_DEP_PT(92) OR BR_DEP_PT(95) + ); +MQQ114:USESCTR <= + (BR_DEP_PT(4) OR BR_DEP_PT(8) + OR BR_DEP_PT(10) OR BR_DEP_PT(89) + ); +MQQ115:USESXER <= + (BR_DEP_PT(6) OR BR_DEP_PT(14) + OR BR_DEP_PT(25) OR BR_DEP_PT(27) + OR BR_DEP_PT(35) OR BR_DEP_PT(48) + OR BR_DEP_PT(51) OR BR_DEP_PT(56) + OR BR_DEP_PT(58) OR BR_DEP_PT(59) + OR BR_DEP_PT(60) OR BR_DEP_PT(62) + OR BR_DEP_PT(65) OR BR_DEP_PT(67) + OR BR_DEP_PT(72) OR BR_DEP_PT(73) + OR BR_DEP_PT(74) OR BR_DEP_PT(76) + OR BR_DEP_PT(77) OR BR_DEP_PT(78) + OR BR_DEP_PT(79) OR BR_DEP_PT(80) + OR BR_DEP_PT(82) OR BR_DEP_PT(83) + OR BR_DEP_PT(84) OR BR_DEP_PT(85) + OR BR_DEP_PT(86) OR BR_DEP_PT(87) + OR BR_DEP_PT(88) OR BR_DEP_PT(90) + OR BR_DEP_PT(91) OR BR_DEP_PT(93) + OR BR_DEP_PT(94) OR BR_DEP_PT(97) + OR BR_DEP_PT(100) OR BR_DEP_PT(101) + OR BR_DEP_PT(102) OR BR_DEP_PT(103) + OR BR_DEP_PT(104) OR BR_DEP_PT(105) + ); +MQQ116:USESMSR <= + (BR_DEP_PT(13) OR BR_DEP_PT(33) + OR BR_DEP_PT(52) OR BR_DEP_PT(99) + ); +MQQ117:USESSPR <= + (BR_DEP_PT(11) OR BR_DEP_PT(13) + OR BR_DEP_PT(30) OR BR_DEP_PT(33) + OR BR_DEP_PT(34) OR BR_DEP_PT(40) + OR BR_DEP_PT(41) OR BR_DEP_PT(42) + OR BR_DEP_PT(43) OR BR_DEP_PT(44) + OR BR_DEP_PT(45) OR BR_DEP_PT(46) + OR BR_DEP_PT(47) OR BR_DEP_PT(49) + ); + +-- +-- Final Table Listing +-- *INPUTS*====================================*OUTPUTS*================================* +-- | | | +-- | core64 | | +-- | | | | +-- | | iu_au_ib1_instr | ta_vld s1_vld s2_vld s3_vld ld_vld | +-- | | | iu_au_ib1_instr | | | | | | | +-- | | | | iu_au_ib1_instr | | | | | | | +-- | | | | | iu_au_ib1_instr | | | | | | | +-- | | | | | | | | | | | | | +-- | | | | | | | | | | | | | +-- | | | | | | | | | | | | | +-- | | | | | | | | | | | | | +-- | | | | | | | | | | | | | +-- | | | | | | | | | | | | | +-- | | | | | | | | | | | | | +-- | | | | | | | | | | | | | +-- | | | | | | | | | | | | | +-- | | | | | | | | | | | | | +-- | | | | 1 1111111112 22222222233 | | | | | | | +-- | | 012345 67890 1234567890 12345678901 | | | | | | | +-- *TYPE*======================================+========================================+ +-- | P PPPPPP PPPPP PPPPPPPPPP PPPPPPPPPPP | S S S S S | +-- *POLARITY*--------------------------------->| + + + + + | +-- *PHASE*------------------------------------>| C C T T T | +-- *TERMS*=====================================+========================================+ +-- 1 | - -1-000 00000 0000000000 00000000000 | 1 1 . . . | +-- 2 | - -11111 ----- ---------- 001101--1-- | 1 . 1 1 . | +-- 3 | - -1-111 ----- ---------- -1-00-00--- | . . 1 . . | +-- 4 | - -11111 ----- ---------- --0-0100-1- | . 1 . . . | +-- 5 | - -11111 ----- ---------- 1-0001-1--- | . . 1 . 1 | +-- 6 | - -11111 ----- ---------- --1001-1-1- | 1 . . 1 . | +-- 7 | - -11111 ----- ---------- 0----10100- | . . 1 . 1 | +-- 8 | - -11111 ----- ---------- -1-100---0- | . 1 . . . | +-- 9 | - -11111 ----- ---------- -00-11-0-1- | 1 . 1 . . | +-- 10 | - -11111 ----- ---------- --0-01-1-1- | . . . . 1 | +-- 11 | - -11111 ----- ---------- --0-100-1-- | . 1 . . . | +-- 12 | - -11111 ----- ---------- 0----10110- | 1 . 1 . . | +-- 13 | - -1-111 ----- ---------- 1101---0--- | . . 1 . . | +-- 14 | - -11111 ----- ---------- -01-1-00--- | . 1 . . . | +-- 15 | - -11111 ----- ---------- 010---00--- | . 1 . . . | +-- 16 | - -11111 ----- ---------- 1---1-00-0- | . 1 . . . | +-- 17 | - -11111 ----- ---------- --11--00-0- | . 1 . . . | +-- 18 | - -11111 ----- ---------- -1-0-100-1- | 1 . 1 1 . | +-- 19 | - -11111 ----- ---------- --10-101-0- | 1 . 1 1 . | +-- 20 | - -11111 ----- ---------- --11--0-01- | 1 . . 1 . | +-- 21 | - -11111 ----- ---------- 1-01---1-0- | 1 1 . . . | +-- 22 | - -1-111 ----- ---------- 0-0---0--0- | . . 1 . . | +-- 23 | - -11111 ----- ---------- -0-1-000--- | 1 . . 1 . | +-- 24 | - -11111 ----- ---------- 1-0-11-1--- | 1 1 . . . | +-- 25 | - -11111 ----- ---------- 0-0---01-1- | . . 1 . 1 | +-- 26 | - -11111 ----- ---------- --1-110--1- | . . 1 1 . | +-- 27 | - -11111 ----- ---------- 1-1--1-11-- | 1 . 1 . . | +-- 28 | - 01111- ----- ---------- ------1110- | 1 1 . . . | +-- 29 | - 01-11- ----- ---------- 0----11-0-- | . . 1 . . | +-- 30 | - 01-11- ----- ---------- 1-0-0-1---- | . . 1 . . | +-- 31 | - 01-11- ----- ---------- ---0-010--- | . . 1 . . | +-- 32 | - -11111 ----- ---------- 1---000---- | . 1 . . . | +-- 33 | - -11111 ----- ---------- 10----00--- | . 1 . . . | +-- 34 | - -1111- ----- ---------- ----1111-1- | 1 . 1 . . | +-- 35 | - -11111 ----- ---------- --11--00--- | 1 . . . . | +-- 36 | - -1-111 ----- ---------- ----10-1--- | . . 1 . . | +-- 37 | - -1-111 ----- ---------- --10-1---1- | . . 1 . . | +-- 38 | - -1-111 ----- ---------- 01-0--0---- | . . 1 . . | +-- 39 | - -11111 ----- ---------- -0---0-1-0- | 1 . 1 . . | +-- 40 | - 01-110 ----- ---------- -------11-- | . . 1 . . | +-- 41 | - 101-10 ----- ---------- ----------- | . . . . 1 | +-- 42 | - 000-0- ----- ---------- ----------- | 1 1 . . . | +-- 43 | - -11111 ----- ---------- --1--00---- | 1 . . . . | +-- 44 | - -11111 ----- ---------- ------00-0- | 1 . . . . | +-- 45 | - 01-110 ----- ---------- ------1---- | . . 1 . . | +-- 46 | - 00-01- ----- ---------- ----------- | 1 . . . . | +-- 47 | - -1-11- ----- ---------- -----01--1- | . . 1 . . | +-- 48 | - -1-11- ----- ---------- ----0-1--1- | . . 1 . . | +-- 49 | - 0-01-0 ----- ---------- ----------- | . . 1 . . | +-- 50 | - 1--100 ----- ---------- ----------- | 1 . . 1 . | +-- 51 | - 1-01-0 ----- ---------- ----------- | 1 . . 1 . | +-- 52 | - 1--0-- ----- ---------- ----------- | . . . . 1 | +-- 53 | - 11-1-- ----- ---------- ----------0 | 1 . . . . | +-- 54 | - 1-1111 ----- ---------- ----------- | 1 . . . . | +-- 55 | - -100-- ----- ---------- ----------- | 1 1 . . . | +-- 56 | - 1--1-1 ----- ---------- ----------- | . . . 1 . | +-- 57 | - 11-1-- ----- ---------- ----------- | . . . 1 . | +-- 58 | - -1011- ----- ---------- ----------- | . . 1 . . | +-- *====================================================================================* +-- +-- Table INSTRUCTION_DECODER Signal Assignments for Product Terms +MQQ118:INSTRUCTION_DECODER_PT(1) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(6) & IU_AU_IB1_INSTR(7) & + IU_AU_IB1_INSTR(8) & IU_AU_IB1_INSTR(9) & + IU_AU_IB1_INSTR(10) & IU_AU_IB1_INSTR(11) & + IU_AU_IB1_INSTR(12) & IU_AU_IB1_INSTR(13) & + IU_AU_IB1_INSTR(14) & IU_AU_IB1_INSTR(15) & + IU_AU_IB1_INSTR(16) & IU_AU_IB1_INSTR(17) & + IU_AU_IB1_INSTR(18) & IU_AU_IB1_INSTR(19) & + IU_AU_IB1_INSTR(20) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) & IU_AU_IB1_INSTR(31) + ) , STD_ULOGIC_VECTOR'("100000000000000000000000000000")); +MQQ119:INSTRUCTION_DECODER_PT(2) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(29) + ) , STD_ULOGIC_VECTOR'("111110011011")); +MQQ120:INSTRUCTION_DECODER_PT(3) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) ) , STD_ULOGIC_VECTOR'("111110000")); +MQQ121:INSTRUCTION_DECODER_PT(4) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("11111001001")); +MQQ122:INSTRUCTION_DECODER_PT(5) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(28) ) , STD_ULOGIC_VECTOR'("11111100011")); +MQQ123:INSTRUCTION_DECODER_PT(6) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("11111100111")); +MQQ124:INSTRUCTION_DECODER_PT(7) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("11111010100")); +MQQ125:INSTRUCTION_DECODER_PT(8) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("1111111000")); +MQQ126:INSTRUCTION_DECODER_PT(9) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("11111001101")); +MQQ127:INSTRUCTION_DECODER_PT(10) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("1111100111")); +MQQ128:INSTRUCTION_DECODER_PT(11) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(29) + ) , STD_ULOGIC_VECTOR'("1111101001")); +MQQ129:INSTRUCTION_DECODER_PT(12) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("11111010110")); +MQQ130:INSTRUCTION_DECODER_PT(13) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(28) ) , STD_ULOGIC_VECTOR'("111111010")); +MQQ131:INSTRUCTION_DECODER_PT(14) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) + ) , STD_ULOGIC_VECTOR'("1111101100")); +MQQ132:INSTRUCTION_DECODER_PT(15) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) + ) , STD_ULOGIC_VECTOR'("1111101000")); +MQQ133:INSTRUCTION_DECODER_PT(16) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("1111111000")); +MQQ134:INSTRUCTION_DECODER_PT(17) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("1111111000")); +MQQ135:INSTRUCTION_DECODER_PT(18) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("11111101001")); +MQQ136:INSTRUCTION_DECODER_PT(19) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("11111101010")); +MQQ137:INSTRUCTION_DECODER_PT(20) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(29) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("1111111001")); +MQQ138:INSTRUCTION_DECODER_PT(21) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("1111110110")); +MQQ139:INSTRUCTION_DECODER_PT(22) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("11110000")); +MQQ140:INSTRUCTION_DECODER_PT(23) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) + ) , STD_ULOGIC_VECTOR'("1111101000")); +MQQ141:INSTRUCTION_DECODER_PT(24) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(28) + ) , STD_ULOGIC_VECTOR'("1111110111")); +MQQ142:INSTRUCTION_DECODER_PT(25) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("1111100011")); +MQQ143:INSTRUCTION_DECODER_PT(26) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("1111111101")); +MQQ144:INSTRUCTION_DECODER_PT(27) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) + ) , STD_ULOGIC_VECTOR'("1111111111")); +MQQ145:INSTRUCTION_DECODER_PT(28) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(29) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("011111110")); +MQQ146:INSTRUCTION_DECODER_PT(29) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(29) + ) , STD_ULOGIC_VECTOR'("01110110")); +MQQ147:INSTRUCTION_DECODER_PT(30) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(27) + ) , STD_ULOGIC_VECTOR'("01111001")); +MQQ148:INSTRUCTION_DECODER_PT(31) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) + ) , STD_ULOGIC_VECTOR'("01110010")); +MQQ149:INSTRUCTION_DECODER_PT(32) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) ) , STD_ULOGIC_VECTOR'("111111000")); +MQQ150:INSTRUCTION_DECODER_PT(33) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) ) , STD_ULOGIC_VECTOR'("111111000")); +MQQ151:INSTRUCTION_DECODER_PT(34) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("111111111")); +MQQ152:INSTRUCTION_DECODER_PT(35) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) ) , STD_ULOGIC_VECTOR'("111111100")); +MQQ153:INSTRUCTION_DECODER_PT(36) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(28) ) , STD_ULOGIC_VECTOR'("1111101")); +MQQ154:INSTRUCTION_DECODER_PT(37) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(24) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("11111011")); +MQQ155:INSTRUCTION_DECODER_PT(38) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(27) + ) , STD_ULOGIC_VECTOR'("11110100")); +MQQ156:INSTRUCTION_DECODER_PT(39) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(22) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("111110010")); +MQQ157:INSTRUCTION_DECODER_PT(40) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(29) ) , STD_ULOGIC_VECTOR'("0111011")); +MQQ158:INSTRUCTION_DECODER_PT(41) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) ) , STD_ULOGIC_VECTOR'("10110")); +MQQ159:INSTRUCTION_DECODER_PT(42) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(4) + ) , STD_ULOGIC_VECTOR'("0000")); +MQQ160:INSTRUCTION_DECODER_PT(43) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) + ) , STD_ULOGIC_VECTOR'("11111100")); +MQQ161:INSTRUCTION_DECODER_PT(44) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("11111000")); +MQQ162:INSTRUCTION_DECODER_PT(45) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(27) + ) , STD_ULOGIC_VECTOR'("011101")); +MQQ163:INSTRUCTION_DECODER_PT(46) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) + ) , STD_ULOGIC_VECTOR'("0001")); +MQQ164:INSTRUCTION_DECODER_PT(47) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("111011")); +MQQ165:INSTRUCTION_DECODER_PT(48) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("111011")); +MQQ166:INSTRUCTION_DECODER_PT(49) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(5) + ) , STD_ULOGIC_VECTOR'("0010")); +MQQ167:INSTRUCTION_DECODER_PT(50) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(4) & IU_AU_IB1_INSTR(5) + ) , STD_ULOGIC_VECTOR'("1100")); +MQQ168:INSTRUCTION_DECODER_PT(51) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(5) + ) , STD_ULOGIC_VECTOR'("1010")); +MQQ169:INSTRUCTION_DECODER_PT(52) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(3) + ) , STD_ULOGIC_VECTOR'("10")); +MQQ170:INSTRUCTION_DECODER_PT(53) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(31) + ) , STD_ULOGIC_VECTOR'("1110")); +MQQ171:INSTRUCTION_DECODER_PT(54) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) & + IU_AU_IB1_INSTR(5) ) , STD_ULOGIC_VECTOR'("11111")); +MQQ172:INSTRUCTION_DECODER_PT(55) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) ) , STD_ULOGIC_VECTOR'("100")); +MQQ173:INSTRUCTION_DECODER_PT(56) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(5) ) , STD_ULOGIC_VECTOR'("111")); +MQQ174:INSTRUCTION_DECODER_PT(57) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) ) , STD_ULOGIC_VECTOR'("111")); +MQQ175:INSTRUCTION_DECODER_PT(58) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(3) & IU_AU_IB1_INSTR(4) + ) , STD_ULOGIC_VECTOR'("1011")); +-- Table INSTRUCTION_DECODER Signal Assignments for Outputs +MQQ176:TA_VLD <= NOT ( + (INSTRUCTION_DECODER_PT(1) OR INSTRUCTION_DECODER_PT(2) + OR INSTRUCTION_DECODER_PT(6) OR INSTRUCTION_DECODER_PT(9) + OR INSTRUCTION_DECODER_PT(12) OR INSTRUCTION_DECODER_PT(18) + OR INSTRUCTION_DECODER_PT(19) OR INSTRUCTION_DECODER_PT(20) + OR INSTRUCTION_DECODER_PT(21) OR INSTRUCTION_DECODER_PT(23) + OR INSTRUCTION_DECODER_PT(24) OR INSTRUCTION_DECODER_PT(27) + OR INSTRUCTION_DECODER_PT(28) OR INSTRUCTION_DECODER_PT(34) + OR INSTRUCTION_DECODER_PT(35) OR INSTRUCTION_DECODER_PT(39) + OR INSTRUCTION_DECODER_PT(42) OR INSTRUCTION_DECODER_PT(43) + OR INSTRUCTION_DECODER_PT(44) OR INSTRUCTION_DECODER_PT(46) + OR INSTRUCTION_DECODER_PT(50) OR INSTRUCTION_DECODER_PT(51) + OR INSTRUCTION_DECODER_PT(53) OR INSTRUCTION_DECODER_PT(54) + OR INSTRUCTION_DECODER_PT(55))); +MQQ177:S1_VLD <= NOT ( + (INSTRUCTION_DECODER_PT(1) OR INSTRUCTION_DECODER_PT(4) + OR INSTRUCTION_DECODER_PT(8) OR INSTRUCTION_DECODER_PT(11) + OR INSTRUCTION_DECODER_PT(14) OR INSTRUCTION_DECODER_PT(15) + OR INSTRUCTION_DECODER_PT(16) OR INSTRUCTION_DECODER_PT(17) + OR INSTRUCTION_DECODER_PT(21) OR INSTRUCTION_DECODER_PT(24) + OR INSTRUCTION_DECODER_PT(28) OR INSTRUCTION_DECODER_PT(32) + OR INSTRUCTION_DECODER_PT(33) OR INSTRUCTION_DECODER_PT(42) + OR INSTRUCTION_DECODER_PT(55))); +MQQ178:S2_VLD <= + (INSTRUCTION_DECODER_PT(2) OR INSTRUCTION_DECODER_PT(3) + OR INSTRUCTION_DECODER_PT(5) OR INSTRUCTION_DECODER_PT(7) + OR INSTRUCTION_DECODER_PT(9) OR INSTRUCTION_DECODER_PT(12) + OR INSTRUCTION_DECODER_PT(13) OR INSTRUCTION_DECODER_PT(18) + OR INSTRUCTION_DECODER_PT(19) OR INSTRUCTION_DECODER_PT(22) + OR INSTRUCTION_DECODER_PT(25) OR INSTRUCTION_DECODER_PT(26) + OR INSTRUCTION_DECODER_PT(27) OR INSTRUCTION_DECODER_PT(29) + OR INSTRUCTION_DECODER_PT(30) OR INSTRUCTION_DECODER_PT(31) + OR INSTRUCTION_DECODER_PT(34) OR INSTRUCTION_DECODER_PT(36) + OR INSTRUCTION_DECODER_PT(37) OR INSTRUCTION_DECODER_PT(38) + OR INSTRUCTION_DECODER_PT(39) OR INSTRUCTION_DECODER_PT(40) + OR INSTRUCTION_DECODER_PT(45) OR INSTRUCTION_DECODER_PT(47) + OR INSTRUCTION_DECODER_PT(48) OR INSTRUCTION_DECODER_PT(49) + OR INSTRUCTION_DECODER_PT(58)); +MQQ179:S3_VLD <= + (INSTRUCTION_DECODER_PT(2) OR INSTRUCTION_DECODER_PT(6) + OR INSTRUCTION_DECODER_PT(18) OR INSTRUCTION_DECODER_PT(19) + OR INSTRUCTION_DECODER_PT(20) OR INSTRUCTION_DECODER_PT(23) + OR INSTRUCTION_DECODER_PT(26) OR INSTRUCTION_DECODER_PT(50) + OR INSTRUCTION_DECODER_PT(51) OR INSTRUCTION_DECODER_PT(56) + OR INSTRUCTION_DECODER_PT(57)); +MQQ180:LD_VLD <= + (INSTRUCTION_DECODER_PT(5) OR INSTRUCTION_DECODER_PT(7) + OR INSTRUCTION_DECODER_PT(10) OR INSTRUCTION_DECODER_PT(25) + OR INSTRUCTION_DECODER_PT(41) OR INSTRUCTION_DECODER_PT(52) + ); + +-- +-- Final Table Listing +-- *INPUTS*====================================*OUTPUTS*========================* +-- | | | +-- | core64 | | +-- | | | | +-- | | iu_au_ib1_instr | | +-- | | | iu_au_ib1_instr | | +-- | | | | iu_au_ib1_instr | ta_sel s1_sel s2_sel s3_sel| +-- | | | | | iu_au_ib1_instr | | | | | | +-- | | | | | | | | | | | | +-- | | | | | | | | | | | | +-- | | | | | | | | | | | | +-- | | | | | | | | | | | | +-- | | | | | | | | | | | | +-- | | | | | | | | | | | | +-- | | | | | | | | | | | | +-- | | | | | | | | | | | | +-- | | | | | | | | | | | | +-- | | | | | | | | | | | | +-- | | | | 1 1111111112 22222222233 | | | | | | +-- | | 012345 67890 1234567890 12345678901 | | | | | | +-- *TYPE*======================================+================================+ +-- | P PPPPPP PPPPP PPPPPPPPPP PPPPPPPPPPP | S S S S | +-- *POLARITY*--------------------------------->| + + + + | +-- *PHASE*------------------------------------>| T T T T | +-- *TERMS*=====================================+================================+ +-- 1 | - -1---1 ----- ---------- 0-1--1-0-0- | . 1 . . | +-- 2 | - --1--- ----- ---------- 01----00--- | . . 1 . | +-- 3 | - 01---- ----- ---------- --1--00--1- | . 1 . . | +-- 4 | - -11--1 ----- ---------- --1-11-0--- | . . 1 1 | +-- 5 | - -11--1 ----- ---------- --11-1-0--- | . 1 1 1 | +-- 6 | - 01---- ----- ---------- --1-11-1--- | 1 . . . | +-- 7 | - 1--1-1 ----- ---------- ----------- | 1 . . . | +-- 8 | - -----0 ----- ---------- ------0---- | . . 1 . | +-- 9 | - 01---- ----- ---------- -----11--0- | 1 1 . . | +-- 10 | - 01---- ----- ---------- -----110--- | 1 1 . . | +-- 11 | - -1-1-0 ----- ---------- ----------- | 1 . . . | +-- 12 | - 01---0 ----- ---------- ----------- | . 1 . . | +-- 13 | - 01-0-- ----- ---------- ----------- | 1 1 . . | +-- 14 | - -10--- ----- ---------- ----------- | 1 1 . . | +-- 15 | - -1--0- ----- ---------- ----------- | 1 1 1 . | +-- *============================================================================* +-- +-- Table INSTRUCTION_DECODER1 Signal Assignments for Product Terms +MQQ181:INSTRUCTION_DECODER1_PT(1) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(5) & + IU_AU_IB1_INSTR(21) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(28) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("1101100")); +MQQ182:INSTRUCTION_DECODER1_PT(2) <= + Eq(( IU_AU_IB1_INSTR(2) & IU_AU_IB1_INSTR(21) & + IU_AU_IB1_INSTR(22) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) ) , STD_ULOGIC_VECTOR'("10100")); +MQQ183:INSTRUCTION_DECODER1_PT(3) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(27) & IU_AU_IB1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("011001")); +MQQ184:INSTRUCTION_DECODER1_PT(4) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(25) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(28) ) , STD_ULOGIC_VECTOR'("1111110")); +MQQ185:INSTRUCTION_DECODER1_PT(5) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) & + IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(23) & + IU_AU_IB1_INSTR(24) & IU_AU_IB1_INSTR(26) & + IU_AU_IB1_INSTR(28) ) , STD_ULOGIC_VECTOR'("1111110")); +MQQ186:INSTRUCTION_DECODER1_PT(6) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(23) & IU_AU_IB1_INSTR(25) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(28) + ) , STD_ULOGIC_VECTOR'("011111")); +MQQ187:INSTRUCTION_DECODER1_PT(7) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(5) ) , STD_ULOGIC_VECTOR'("111")); +MQQ188:INSTRUCTION_DECODER1_PT(8) <= + Eq(( IU_AU_IB1_INSTR(5) & IU_AU_IB1_INSTR(27) + ) , STD_ULOGIC_VECTOR'("00")); +MQQ189:INSTRUCTION_DECODER1_PT(9) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(30) ) , STD_ULOGIC_VECTOR'("01110")); +MQQ190:INSTRUCTION_DECODER1_PT(10) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(26) & IU_AU_IB1_INSTR(27) & + IU_AU_IB1_INSTR(28) ) , STD_ULOGIC_VECTOR'("01110")); +MQQ191:INSTRUCTION_DECODER1_PT(11) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(3) & + IU_AU_IB1_INSTR(5) ) , STD_ULOGIC_VECTOR'("110")); +MQQ192:INSTRUCTION_DECODER1_PT(12) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(5) ) , STD_ULOGIC_VECTOR'("010")); +MQQ193:INSTRUCTION_DECODER1_PT(13) <= + Eq(( IU_AU_IB1_INSTR(0) & IU_AU_IB1_INSTR(1) & + IU_AU_IB1_INSTR(3) ) , STD_ULOGIC_VECTOR'("010")); +MQQ194:INSTRUCTION_DECODER1_PT(14) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(2) + ) , STD_ULOGIC_VECTOR'("10")); +MQQ195:INSTRUCTION_DECODER1_PT(15) <= + Eq(( IU_AU_IB1_INSTR(1) & IU_AU_IB1_INSTR(4) + ) , STD_ULOGIC_VECTOR'("10")); +-- Table INSTRUCTION_DECODER1 Signal Assignments for Outputs +MQQ196:TA_SEL <= + (INSTRUCTION_DECODER1_PT(6) OR INSTRUCTION_DECODER1_PT(7) + OR INSTRUCTION_DECODER1_PT(9) OR INSTRUCTION_DECODER1_PT(10) + OR INSTRUCTION_DECODER1_PT(11) OR INSTRUCTION_DECODER1_PT(13) + OR INSTRUCTION_DECODER1_PT(14) OR INSTRUCTION_DECODER1_PT(15) + ); +MQQ197:S1_SEL <= + (INSTRUCTION_DECODER1_PT(1) OR INSTRUCTION_DECODER1_PT(3) + OR INSTRUCTION_DECODER1_PT(5) OR INSTRUCTION_DECODER1_PT(9) + OR INSTRUCTION_DECODER1_PT(10) OR INSTRUCTION_DECODER1_PT(12) + OR INSTRUCTION_DECODER1_PT(13) OR INSTRUCTION_DECODER1_PT(14) + OR INSTRUCTION_DECODER1_PT(15)); +MQQ198:S2_SEL <= + (INSTRUCTION_DECODER1_PT(2) OR INSTRUCTION_DECODER1_PT(4) + OR INSTRUCTION_DECODER1_PT(5) OR INSTRUCTION_DECODER1_PT(8) + OR INSTRUCTION_DECODER1_PT(15)); +MQQ199:S3_SEL <= + (INSTRUCTION_DECODER1_PT(4) OR INSTRUCTION_DECODER1_PT(5) + ); + +-- +-- Final Table Listing +-- *INPUTS*====================================*OUTPUTS*=================================* +-- | | | +-- | core64 | | +-- | | | | +-- | | is1_instr_L2 | | +-- | | | is1_instr_L2 | | +-- | | | | is1_instr_L2 | | +-- | | | | | is1_instr_L2 | | +-- | | | | | | | | +-- | | | | | | | | +-- | | | | | | | | +-- | | | | | | | | +-- | | | | | | | isFxuIssue | +-- | | | | | | | | | +-- | | | | | | | | | +-- | | | | | | | | hole_delay | +-- | | | | | | | | | compl_ex | +-- | | | | | | | | | | | +-- | | | | 1 1111111112 22222222233 | | | | | +-- | | 012345 67890 1234567890 12345678901 | | 123 12345 | +-- *TYPE*======================================+=========================================+ +-- | P PPPPPP PPPPP PPPPPPPPPP PPPPPPPPPPP | S SSS SSSSS | +-- *POLARITY*--------------------------------->| + +++ +++++ | +-- *PHASE*------------------------------------>| T TTT TTTTT | +-- *TERMS*=====================================+=========================================+ +-- 1 | - 0--000 ----- ---------- 0100000000- | 1 ... ..... | +-- 2 | 1 011111 ----- ---------- 1011101001- | 1 ..1 ..... | +-- 3 | 1 011111 ----- ---------- 0011101001- | 1 .1. ..... | +-- 4 | - 011111 ----- ---------- 011-0111000 | . ... 1.... | +-- 5 | - 011111 ----- ---------- 000-1111000 | . ... 1.... | +-- 6 | - 0-0011 ----- ---------- 0000000000- | . ... 1.... | +-- 7 | - 011111 ----- ---------- 01-0-111000 | . ... 1.... | +-- 8 | - 011111 ----- 1--------- 000001001-- | . ... 1.... | +-- 9 | - 011111 ----- ---------- 0-00-111000 | . ... 1.... | +-- 10 | - 0-0-11 ----- ---------- 0010010110- | 1 ... ..... | +-- 11 | 1 011111 ----- ---------- 001-01011-1 | 1 ... 1.... | +-- 12 | - 0-0011 ----- ---------- 0-11000001- | 1 ... 1.... | +-- 13 | - 0-0011 ----- ---------- 01-0100001- | 1 ... 1.... | +-- 14 | 1 011111 ----- ---------- -00-001001- | 1 ..1 ..... | +-- 15 | - 011111 ----- ---------- 001001011-1 | 1 ... 1.... | +-- 16 | - 0-0011 ----- ---------- 0011-00001- | 1 ... 1.... | +-- 17 | - 0-0011 ----- ---------- 0-00100001- | 1 ... 1.... | +-- 18 | - 0-0011 ----- ---------- 001-000001- | 1 ... 1.... | +-- 19 | - 01-01- --1-- ---------- -000010000- | 1 ... ..... | +-- 20 | - 0-0011 ----- ---------- 0100-00001- | 1 ... 1.... | +-- 21 | - 0-0011 ----- ---------- 000-100110- | 1 ... 1.... | +-- 22 | - 011--1 ----- ---------- 00110101001 | 1 ... ..... | +-- 23 | - 0-0011 ----- ---------- 000011001-- | 1 ... 1.... | +-- 24 | - 011--1 ----- ---------- 1110--0110- | 1 ... ..... | +-- 25 | 1 011--1 ----- ---------- 00-1111100- | 1 ... ..... | +-- 26 | - 01-01- ----- ---------- 00000-0000- | 1 ... ..... | +-- 27 | 1 011--1 ----- ---------- 110011101-- | 1 ... .1... | +-- 28 | 1 011--1 ----- ---------- 01-1111010- | 1 ... ..... | +-- 29 | - 011--1 ----- ---------- 1100110011- | 1 ... ..... | +-- 30 | - 011--1 ----- ----1----- 0101-10011- | 1 ... ....1 | +-- 31 | - 011--1 ----- ---------1 0101-10011- | 1 ... ...1. | +-- 32 | - 011--1 ----- --------1- 0101-10011- | 1 ... ...1. | +-- 33 | - 011--1 ----- -------1-- 0101-10011- | 1 ... ...1. | +-- 34 | - 011--1 ----- ------1--- 0101-10011- | 1 ... ...1. | +-- 35 | - 011--1 ----- -----1---- 0101-10011- | 1 ... ...1. | +-- 36 | - 011--1 ----- ---1------ 0101-10011- | 1 ... ...1. | +-- 37 | - 011--1 ----- --1------- 0101-10011- | 1 ... ...1. | +-- 38 | - 011--1 ----- -1-------- 0101-10011- | 1 ... ...1. | +-- 39 | - 011--1 ----- 1--------- 0101-10011- | 1 ... ...1. | +-- 40 | 1 011--1 ----- ---------- -000011011- | 1 ... .1... | +-- 41 | - 011--1 ----- ---------- 000001001-- | . ... ....1 | +-- 42 | 1 011--- ----- ---------- 10-001010-- | 1 ... ..... | +-- 43 | 1 011--1 ----- ---------- 1100-110-0- | 1 ... .1... | +-- 44 | - 011--1 ----- ---------- 0-11100110- | 1 ... ..... | +-- 45 | 1 011--1 ----- ---------- 111-01-010- | 1 ... .1... | +-- 46 | - 011--1 ----- ---------- 010000111-- | 1 ... ..... | +-- 47 | - 011--1 ----- ---------- 1100-11000- | 1 ... .1... | +-- 48 | - 011--1 ----- ---------- -011110110- | 1 ... ..... | +-- 49 | - 011--1 ----- ---------- 1-0-010110- | 1 ... ..... | +-- 50 | - 011--1 ----- ---------- 1111--1111- | 1 ... ..... | +-- 51 | - 011--1 ----- ---------- 00-111-111- | . ... .1... | +-- 52 | - 011--1 ----- ---------- 01110-0011- | 1 ... ..... | +-- 53 | - 011--1 ----- ---------- 0-01111010- | 1 ... ..... | +-- 54 | - 011--1 ----- ---------- 00000-0100- | 1 ... ..... | +-- 55 | - 011--1 ----- ---------- 0010-00110- | 1 ... ..... | +-- 56 | - 011--1 ----- ---------- 000-111100- | 1 ... .1... | +-- 57 | 1 011--- ----- ---------- 000-0-0100- | 1 ... ..... | +-- 58 | 1 111-10 ----- ---------- ---------01 | . ... .1... | +-- 59 | 1 011--1 ----- ---------- 00-0-11010- | 1 ... ..... | +-- 60 | 1 011--- ----- ---------- 0101-101-1- | 1 ... ..... | +-- 61 | - 011--1 ----- ---------- 0101110-11- | 1 ... ...1. | +-- 62 | - 011--1 ----- ---------- 11--010-101 | 1 ... ..... | +-- 63 | - 011--1 ----- ---------- 0001-00011- | 1 ... ....1 | +-- 64 | - 011--1 ----- ---------- 00100100-0- | 1 ... ..... | +-- 65 | - 011--1 ----- ---------- 0011-0111-- | 1 ... ..... | +-- 66 | - 011--1 ----- ---------- -00-101000- | 1 ... .1... | +-- 67 | 1 011--- ----- ---------- 00-01101-1- | 1 ... .1... | +-- 68 | - 011--1 ----- ---------- 10--010101- | 1 ... ..... | +-- 69 | - 011--1 ----- ---------- -00000-000- | 1 ... ..... | +-- 70 | - 011--1 ----- ---------- 0-0001011-- | 1 ... ..... | +-- 71 | - 011--1 ----- ---------- 111-010-10- | 1 ... ..... | +-- 72 | - 011--1 ----- ---------- 111--10110- | 1 ... ..... | +-- 73 | - 011--1 ----- ---------- 000-01011-- | 1 ... ..... | +-- 74 | - 011--1 ----- ---------- 00-1010011- | 1 ... ...1. | +-- 75 | 1 011--1 ----- ---------- -11--010-1- | 1 ... ..... | +-- 76 | 1 011--1 ----- ---------- 00-001-1-1- | 1 ... ..... | +-- 77 | - 011--1 ----- ---------- -0000-1000- | 1 ... .1... | +-- 78 | - 011--1 ----- ---------- 011--11100- | 1 ... .1... | +-- 79 | - 011--1 ----- ---------- --11101-11- | 1 ... ....1 | +-- 80 | - 011--1 ----- ---------- 1110-1-010- | 1 ... .1... | +-- 81 | - 011--1 ----- ---------- --00001010- | 1 ... .1... | +-- 82 | - 011--1 ----- ---------- 01--000011- | 1 ... ..... | +-- 83 | - 011--1 ----- ---------- 0-00-1-111- | 1 ... ..... | +-- 84 | - 011111 ----- ---------- -----01111- | 1 ... 1.... | +-- 85 | - 011--1 ----- ---------- 000011-11-- | 1 ... ..... | +-- 86 | - 011--1 ----- ---------- 0000-0-000- | 1 ... .1... | +-- 87 | - 011--1 ----- ---------- 0-00-11100- | 1 ... .1... | +-- 88 | - 011--1 ----- ---------- -000-10110- | 1 ... ..... | +-- 89 | - 011--1 ----- ---------- -011-010-0- | 1 ... .1... | +-- 90 | - 011--1 ----- ---------- 00-001-010- | 1 ... ..... | +-- 91 | - 011--1 ----- ---------- -01-0010-0- | 1 ... .1... | +-- 92 | - 011--1 ----- ---------- -00-001-11- | 1 ... ....1 | +-- 93 | - 011--1 ----- ---------- -11-0-0110- | 1 ... ..... | +-- 94 | - 011--1 ----- ---------- 0-10-10111- | 1 ... .1... | +-- 95 | - 011--1 ----- ---------- 1--0010-10- | 1 ... ..... | +-- 96 | - 011--1 ----- ---------- 10---10010- | 1 ... ..... | +-- 97 | - 011--1 ----- ---------- -11--01-11- | 1 ... ..... | +-- 98 | - 011--1 ----- ---------- 00-1-1-111- | 1 ... ..... | +-- 99 | - 011--1 ----- ---------- 0--0-00011- | 1 ... ..... | +-- 100 | - 011--1 ----- ---------- 0--001-111- | 1 ... ..... | +-- 101 | 1 --1010 ----- ---------- ----------0 | 1 ... ..... | +-- 102 | - 011--1 ----- ---------- 0-0--10111- | 1 ... ..... | +-- 103 | - 011--1 ----- ---------- 00-0-10-11- | 1 ... ..... | +-- 104 | - 10-1-0 ----- ---------- ----------- | . ... 1.... | +-- 105 | 1 -0-01- ----- ---------- ----------- | 1 ... ..... | +-- 106 | 1 1-1-10 ----- ---------- ---------0- | 1 ... ..... | +-- 107 | - 000111 ----- ---------- ----------- | 1 1.. ..... | +-- 108 | - 10-1-- ----- ---------- ----------- | . ... .1... | +-- 109 | 1 0-1--0 ----- ---------- -------00-- | 1 ... .1... | +-- 110 | - 01100- ----- ---------- ----------- | . ... 1.... | +-- 111 | - 0110-0 ----- ---------- ----------- | . ... 1.... | +-- 112 | - -0-011 ----- ---------- ----------- | 1 ... .1... | +-- 113 | 1 0-1--0 ----- ---------- ------0---- | 1 ... .1... | +-- 114 | - 01-0-0 ----- ---------- ----------- | 1 ... ..... | +-- 115 | - 0101-1 ----- ---------- ----------- | 1 ... .1... | +-- 116 | - 10---- ----- ---------- ----------- | 1 ... ..... | +-- 117 | - 001--0 ----- ---------- ----------- | 1 ... .1... | +-- 118 | - 01--0- ----- ---------- ---------1- | 1 ... ..... | +-- 119 | - 01-10- ----- ---------- ----------- | 1 ... .1... | +-- 120 | - -011-- ----- ---------- ----------- | 1 ... .1... | +-- 121 | - 0110-- ----- ---------- ----------- | 1 ... .1... | +-- *=====================================================================================* +-- +-- Table INSTRUCTION_DECODER2 Signal Assignments for Product Terms +MQQ200:INSTRUCTION_DECODER2_PT(1) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(3) & + IS1_INSTR_L2(4) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("00000100000000")); +MQQ201:INSTRUCTION_DECODER2_PT(2) <= + Eq(( CORE64 & IS1_INSTR_L2(0) & + IS1_INSTR_L2(1) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(3) & IS1_INSTR_L2(4) & + IS1_INSTR_L2(5) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(25) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("10111111011101001")); +MQQ202:INSTRUCTION_DECODER2_PT(3) <= + Eq(( CORE64 & IS1_INSTR_L2(0) & + IS1_INSTR_L2(1) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(3) & IS1_INSTR_L2(4) & + IS1_INSTR_L2(5) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(25) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("10111110011101001")); +MQQ203:INSTRUCTION_DECODER2_PT(4) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(3) & + IS1_INSTR_L2(4) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(25) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) & IS1_INSTR_L2(31) + ) , STD_ULOGIC_VECTOR'("0111110110111000")); +MQQ204:INSTRUCTION_DECODER2_PT(5) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(3) & + IS1_INSTR_L2(4) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(25) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) & IS1_INSTR_L2(31) + ) , STD_ULOGIC_VECTOR'("0111110001111000")); +MQQ205:INSTRUCTION_DECODER2_PT(6) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(3) & IS1_INSTR_L2(4) & + IS1_INSTR_L2(5) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(25) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("000110000000000")); +MQQ206:INSTRUCTION_DECODER2_PT(7) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(3) & + IS1_INSTR_L2(4) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) & + IS1_INSTR_L2(31) ) , STD_ULOGIC_VECTOR'("011111010111000")); +MQQ207:INSTRUCTION_DECODER2_PT(8) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(3) & + IS1_INSTR_L2(4) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(11) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(25) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) + ) , STD_ULOGIC_VECTOR'("0111111000001001")); +MQQ208:INSTRUCTION_DECODER2_PT(9) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(3) & + IS1_INSTR_L2(4) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) & + IS1_INSTR_L2(31) ) , STD_ULOGIC_VECTOR'("011111000111000")); +MQQ209:INSTRUCTION_DECODER2_PT(10) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(4) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("00110010010110")); +MQQ210:INSTRUCTION_DECODER2_PT(11) <= + Eq(( CORE64 & IS1_INSTR_L2(0) & + IS1_INSTR_L2(1) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(3) & IS1_INSTR_L2(4) & + IS1_INSTR_L2(5) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(31) + ) , STD_ULOGIC_VECTOR'("1011111001010111")); +MQQ211:INSTRUCTION_DECODER2_PT(12) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(3) & IS1_INSTR_L2(4) & + IS1_INSTR_L2(5) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("00011011000001")); +MQQ212:INSTRUCTION_DECODER2_PT(13) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(3) & IS1_INSTR_L2(4) & + IS1_INSTR_L2(5) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("00011010100001")); +MQQ213:INSTRUCTION_DECODER2_PT(14) <= + Eq(( CORE64 & IS1_INSTR_L2(0) & + IS1_INSTR_L2(1) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(3) & IS1_INSTR_L2(4) & + IS1_INSTR_L2(5) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(25) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("101111100001001")); +MQQ214:INSTRUCTION_DECODER2_PT(15) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(3) & + IS1_INSTR_L2(4) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(31) + ) , STD_ULOGIC_VECTOR'("0111110010010111")); +MQQ215:INSTRUCTION_DECODER2_PT(16) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(3) & IS1_INSTR_L2(4) & + IS1_INSTR_L2(5) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("00011001100001")); +MQQ216:INSTRUCTION_DECODER2_PT(17) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(3) & IS1_INSTR_L2(4) & + IS1_INSTR_L2(5) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("00011000100001")); +MQQ217:INSTRUCTION_DECODER2_PT(18) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(3) & IS1_INSTR_L2(4) & + IS1_INSTR_L2(5) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("00011001000001")); +MQQ218:INSTRUCTION_DECODER2_PT(19) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(3) & IS1_INSTR_L2(4) & + IS1_INSTR_L2(8) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("01011000010000")); +MQQ219:INSTRUCTION_DECODER2_PT(20) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(3) & IS1_INSTR_L2(4) & + IS1_INSTR_L2(5) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("00011010000001")); +MQQ220:INSTRUCTION_DECODER2_PT(21) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(3) & IS1_INSTR_L2(4) & + IS1_INSTR_L2(5) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("00011000100110")); +MQQ221:INSTRUCTION_DECODER2_PT(22) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) & + IS1_INSTR_L2(31) ) , STD_ULOGIC_VECTOR'("011100110101001")); +MQQ222:INSTRUCTION_DECODER2_PT(23) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(3) & IS1_INSTR_L2(4) & + IS1_INSTR_L2(5) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(25) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) + ) , STD_ULOGIC_VECTOR'("00011000011001")); +MQQ223:INSTRUCTION_DECODER2_PT(24) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("011111100110")); +MQQ224:INSTRUCTION_DECODER2_PT(25) <= + Eq(( CORE64 & IS1_INSTR_L2(0) & + IS1_INSTR_L2(1) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(5) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("10111001111100")); +MQQ225:INSTRUCTION_DECODER2_PT(26) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(3) & IS1_INSTR_L2(4) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("0101000000000")); +MQQ226:INSTRUCTION_DECODER2_PT(27) <= + Eq(( CORE64 & IS1_INSTR_L2(0) & + IS1_INSTR_L2(1) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(5) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(25) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) + ) , STD_ULOGIC_VECTOR'("10111110011101")); +MQQ227:INSTRUCTION_DECODER2_PT(28) <= + Eq(( CORE64 & IS1_INSTR_L2(0) & + IS1_INSTR_L2(1) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(5) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("10111011111010")); +MQQ228:INSTRUCTION_DECODER2_PT(29) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("01111100110011")); +MQQ229:INSTRUCTION_DECODER2_PT(30) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(15) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("01111010110011")); +MQQ230:INSTRUCTION_DECODER2_PT(31) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(20) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("01111010110011")); +MQQ231:INSTRUCTION_DECODER2_PT(32) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(19) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("01111010110011")); +MQQ232:INSTRUCTION_DECODER2_PT(33) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(18) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("01111010110011")); +MQQ233:INSTRUCTION_DECODER2_PT(34) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(17) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("01111010110011")); +MQQ234:INSTRUCTION_DECODER2_PT(35) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(16) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("01111010110011")); +MQQ235:INSTRUCTION_DECODER2_PT(36) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(14) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("01111010110011")); +MQQ236:INSTRUCTION_DECODER2_PT(37) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(13) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("01111010110011")); +MQQ237:INSTRUCTION_DECODER2_PT(38) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(12) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("01111010110011")); +MQQ238:INSTRUCTION_DECODER2_PT(39) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(11) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("01111010110011")); +MQQ239:INSTRUCTION_DECODER2_PT(40) <= + Eq(( CORE64 & IS1_INSTR_L2(0) & + IS1_INSTR_L2(1) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(5) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("10111000011011")); +MQQ240:INSTRUCTION_DECODER2_PT(41) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) ) , STD_ULOGIC_VECTOR'("0111000001001")); +MQQ241:INSTRUCTION_DECODER2_PT(42) <= + Eq(( CORE64 & IS1_INSTR_L2(0) & + IS1_INSTR_L2(1) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(25) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) + ) , STD_ULOGIC_VECTOR'("101110001010")); +MQQ242:INSTRUCTION_DECODER2_PT(43) <= + Eq(( CORE64 & IS1_INSTR_L2(0) & + IS1_INSTR_L2(1) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(5) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("1011111001100")); +MQQ243:INSTRUCTION_DECODER2_PT(44) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(25) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("0111011100110")); +MQQ244:INSTRUCTION_DECODER2_PT(45) <= + Eq(( CORE64 & IS1_INSTR_L2(0) & + IS1_INSTR_L2(1) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(5) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("1011111101010")); +MQQ245:INSTRUCTION_DECODER2_PT(46) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) ) , STD_ULOGIC_VECTOR'("0111010000111")); +MQQ246:INSTRUCTION_DECODER2_PT(47) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("0111110011000")); +MQQ247:INSTRUCTION_DECODER2_PT(48) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(25) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("0111011110110")); +MQQ248:INSTRUCTION_DECODER2_PT(49) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("011110010110")); +MQQ249:INSTRUCTION_DECODER2_PT(50) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("011111111111")); +MQQ250:INSTRUCTION_DECODER2_PT(51) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(25) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("011100111111")); +MQQ251:INSTRUCTION_DECODER2_PT(52) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("0111011100011")); +MQQ252:INSTRUCTION_DECODER2_PT(53) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(25) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("0111001111010")); +MQQ253:INSTRUCTION_DECODER2_PT(54) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("0111000000100")); +MQQ254:INSTRUCTION_DECODER2_PT(55) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("0111001000110")); +MQQ255:INSTRUCTION_DECODER2_PT(56) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(25) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("0111000111100")); +MQQ256:INSTRUCTION_DECODER2_PT(57) <= + Eq(( CORE64 & IS1_INSTR_L2(0) & + IS1_INSTR_L2(1) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(25) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("101100000100")); +MQQ257:INSTRUCTION_DECODER2_PT(58) <= + Eq(( CORE64 & IS1_INSTR_L2(0) & + IS1_INSTR_L2(1) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(4) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(30) & IS1_INSTR_L2(31) + ) , STD_ULOGIC_VECTOR'("11111001")); +MQQ258:INSTRUCTION_DECODER2_PT(59) <= + Eq(( CORE64 & IS1_INSTR_L2(0) & + IS1_INSTR_L2(1) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(5) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("1011100011010")); +MQQ259:INSTRUCTION_DECODER2_PT(60) <= + Eq(( CORE64 & IS1_INSTR_L2(0) & + IS1_INSTR_L2(1) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("101101011011")); +MQQ260:INSTRUCTION_DECODER2_PT(61) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("0111010111011")); +MQQ261:INSTRUCTION_DECODER2_PT(62) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) & IS1_INSTR_L2(31) + ) , STD_ULOGIC_VECTOR'("011111010101")); +MQQ262:INSTRUCTION_DECODER2_PT(63) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("0111000100011")); +MQQ263:INSTRUCTION_DECODER2_PT(64) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("0111001001000")); +MQQ264:INSTRUCTION_DECODER2_PT(65) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) + ) , STD_ULOGIC_VECTOR'("011100110111")); +MQQ265:INSTRUCTION_DECODER2_PT(66) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("011100101000")); +MQQ266:INSTRUCTION_DECODER2_PT(67) <= + Eq(( CORE64 & IS1_INSTR_L2(0) & + IS1_INSTR_L2(1) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(25) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("101100011011")); +MQQ267:INSTRUCTION_DECODER2_PT(68) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("011110010101")); +MQQ268:INSTRUCTION_DECODER2_PT(69) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(25) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("011100000000")); +MQQ269:INSTRUCTION_DECODER2_PT(70) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(25) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) + ) , STD_ULOGIC_VECTOR'("011100001011")); +MQQ270:INSTRUCTION_DECODER2_PT(71) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(25) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("011111101010")); +MQQ271:INSTRUCTION_DECODER2_PT(72) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("011111110110")); +MQQ272:INSTRUCTION_DECODER2_PT(73) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(25) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) + ) , STD_ULOGIC_VECTOR'("011100001011")); +MQQ273:INSTRUCTION_DECODER2_PT(74) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(25) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("0111001010011")); +MQQ274:INSTRUCTION_DECODER2_PT(75) <= + Eq(( CORE64 & IS1_INSTR_L2(0) & + IS1_INSTR_L2(1) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(5) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("10111110101")); +MQQ275:INSTRUCTION_DECODER2_PT(76) <= + Eq(( CORE64 & IS1_INSTR_L2(0) & + IS1_INSTR_L2(1) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(5) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("101110000111")); +MQQ276:INSTRUCTION_DECODER2_PT(77) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(25) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("011100001000")); +MQQ277:INSTRUCTION_DECODER2_PT(78) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("011101111100")); +MQQ278:INSTRUCTION_DECODER2_PT(79) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("01111110111")); +MQQ279:INSTRUCTION_DECODER2_PT(80) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("011111101010")); +MQQ280:INSTRUCTION_DECODER2_PT(81) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("011100001010")); +MQQ281:INSTRUCTION_DECODER2_PT(82) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("011101000011")); +MQQ282:INSTRUCTION_DECODER2_PT(83) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("01110001111")); +MQQ283:INSTRUCTION_DECODER2_PT(84) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(3) & + IS1_INSTR_L2(4) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("01111101111")); +MQQ284:INSTRUCTION_DECODER2_PT(85) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) + ) , STD_ULOGIC_VECTOR'("011100001111")); +MQQ285:INSTRUCTION_DECODER2_PT(86) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("011100000000")); +MQQ286:INSTRUCTION_DECODER2_PT(87) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("011100011100")); +MQQ287:INSTRUCTION_DECODER2_PT(88) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("011100010110")); +MQQ288:INSTRUCTION_DECODER2_PT(89) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("01110110100")); +MQQ289:INSTRUCTION_DECODER2_PT(90) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(25) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("011100001010")); +MQQ290:INSTRUCTION_DECODER2_PT(91) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("01110100100")); +MQQ291:INSTRUCTION_DECODER2_PT(92) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("01110000111")); +MQQ292:INSTRUCTION_DECODER2_PT(93) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("01111100110")); +MQQ293:INSTRUCTION_DECODER2_PT(94) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("011101010111")); +MQQ294:INSTRUCTION_DECODER2_PT(95) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("01111001010")); +MQQ295:INSTRUCTION_DECODER2_PT(96) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("01111010010")); +MQQ296:INSTRUCTION_DECODER2_PT(97) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("0111110111")); +MQQ297:INSTRUCTION_DECODER2_PT(98) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("01110011111")); +MQQ298:INSTRUCTION_DECODER2_PT(99) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("01110000011")); +MQQ299:INSTRUCTION_DECODER2_PT(100) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("01110001111")); +MQQ300:INSTRUCTION_DECODER2_PT(101) <= + Eq(( CORE64 & IS1_INSTR_L2(2) & + IS1_INSTR_L2(3) & IS1_INSTR_L2(4) & + IS1_INSTR_L2(5) & IS1_INSTR_L2(31) + ) , STD_ULOGIC_VECTOR'("110100")); +MQQ301:INSTRUCTION_DECODER2_PT(102) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("01110010111")); +MQQ302:INSTRUCTION_DECODER2_PT(103) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("01110001011")); +MQQ303:INSTRUCTION_DECODER2_PT(104) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(3) & IS1_INSTR_L2(5) + ) , STD_ULOGIC_VECTOR'("1010")); +MQQ304:INSTRUCTION_DECODER2_PT(105) <= + Eq(( CORE64 & IS1_INSTR_L2(1) & + IS1_INSTR_L2(3) & IS1_INSTR_L2(4) + ) , STD_ULOGIC_VECTOR'("1001")); +MQQ305:INSTRUCTION_DECODER2_PT(106) <= + Eq(( CORE64 & IS1_INSTR_L2(0) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(4) & + IS1_INSTR_L2(5) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("111100")); +MQQ306:INSTRUCTION_DECODER2_PT(107) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(3) & + IS1_INSTR_L2(4) & IS1_INSTR_L2(5) + ) , STD_ULOGIC_VECTOR'("000111")); +MQQ307:INSTRUCTION_DECODER2_PT(108) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(3) ) , STD_ULOGIC_VECTOR'("101")); +MQQ308:INSTRUCTION_DECODER2_PT(109) <= + Eq(( CORE64 & IS1_INSTR_L2(0) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) + ) , STD_ULOGIC_VECTOR'("101000")); +MQQ309:INSTRUCTION_DECODER2_PT(110) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(3) & + IS1_INSTR_L2(4) ) , STD_ULOGIC_VECTOR'("01100")); +MQQ310:INSTRUCTION_DECODER2_PT(111) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(3) & + IS1_INSTR_L2(5) ) , STD_ULOGIC_VECTOR'("01100")); +MQQ311:INSTRUCTION_DECODER2_PT(112) <= + Eq(( IS1_INSTR_L2(1) & IS1_INSTR_L2(3) & + IS1_INSTR_L2(4) & IS1_INSTR_L2(5) + ) , STD_ULOGIC_VECTOR'("0011")); +MQQ312:INSTRUCTION_DECODER2_PT(113) <= + Eq(( CORE64 & IS1_INSTR_L2(0) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(27) ) , STD_ULOGIC_VECTOR'("10100")); +MQQ313:INSTRUCTION_DECODER2_PT(114) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(3) & IS1_INSTR_L2(5) + ) , STD_ULOGIC_VECTOR'("0100")); +MQQ314:INSTRUCTION_DECODER2_PT(115) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(3) & + IS1_INSTR_L2(5) ) , STD_ULOGIC_VECTOR'("01011")); +MQQ315:INSTRUCTION_DECODER2_PT(116) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) + ) , STD_ULOGIC_VECTOR'("10")); +MQQ316:INSTRUCTION_DECODER2_PT(117) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(5) + ) , STD_ULOGIC_VECTOR'("0010")); +MQQ317:INSTRUCTION_DECODER2_PT(118) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(4) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("0101")); +MQQ318:INSTRUCTION_DECODER2_PT(119) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(3) & IS1_INSTR_L2(4) + ) , STD_ULOGIC_VECTOR'("0110")); +MQQ319:INSTRUCTION_DECODER2_PT(120) <= + Eq(( IS1_INSTR_L2(1) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(3) ) , STD_ULOGIC_VECTOR'("011")); +MQQ320:INSTRUCTION_DECODER2_PT(121) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(3) + ) , STD_ULOGIC_VECTOR'("0110")); +-- Table INSTRUCTION_DECODER2 Signal Assignments for Outputs +MQQ321:ISFXUISSUE <= + (INSTRUCTION_DECODER2_PT(1) OR INSTRUCTION_DECODER2_PT(2) + OR INSTRUCTION_DECODER2_PT(3) OR INSTRUCTION_DECODER2_PT(10) + OR INSTRUCTION_DECODER2_PT(11) OR INSTRUCTION_DECODER2_PT(12) + OR INSTRUCTION_DECODER2_PT(13) OR INSTRUCTION_DECODER2_PT(14) + OR INSTRUCTION_DECODER2_PT(15) OR INSTRUCTION_DECODER2_PT(16) + OR INSTRUCTION_DECODER2_PT(17) OR INSTRUCTION_DECODER2_PT(18) + OR INSTRUCTION_DECODER2_PT(19) OR INSTRUCTION_DECODER2_PT(20) + OR INSTRUCTION_DECODER2_PT(21) OR INSTRUCTION_DECODER2_PT(22) + OR INSTRUCTION_DECODER2_PT(23) OR INSTRUCTION_DECODER2_PT(24) + OR INSTRUCTION_DECODER2_PT(25) OR INSTRUCTION_DECODER2_PT(26) + OR INSTRUCTION_DECODER2_PT(27) OR INSTRUCTION_DECODER2_PT(28) + OR INSTRUCTION_DECODER2_PT(29) OR INSTRUCTION_DECODER2_PT(30) + OR INSTRUCTION_DECODER2_PT(31) OR INSTRUCTION_DECODER2_PT(32) + OR INSTRUCTION_DECODER2_PT(33) OR INSTRUCTION_DECODER2_PT(34) + OR INSTRUCTION_DECODER2_PT(35) OR INSTRUCTION_DECODER2_PT(36) + OR INSTRUCTION_DECODER2_PT(37) OR INSTRUCTION_DECODER2_PT(38) + OR INSTRUCTION_DECODER2_PT(39) OR INSTRUCTION_DECODER2_PT(40) + OR INSTRUCTION_DECODER2_PT(42) OR INSTRUCTION_DECODER2_PT(43) + OR INSTRUCTION_DECODER2_PT(44) OR INSTRUCTION_DECODER2_PT(45) + OR INSTRUCTION_DECODER2_PT(46) OR INSTRUCTION_DECODER2_PT(47) + OR INSTRUCTION_DECODER2_PT(48) OR INSTRUCTION_DECODER2_PT(49) + OR INSTRUCTION_DECODER2_PT(50) OR INSTRUCTION_DECODER2_PT(52) + OR INSTRUCTION_DECODER2_PT(53) OR INSTRUCTION_DECODER2_PT(54) + OR INSTRUCTION_DECODER2_PT(55) OR INSTRUCTION_DECODER2_PT(56) + OR INSTRUCTION_DECODER2_PT(57) OR INSTRUCTION_DECODER2_PT(59) + OR INSTRUCTION_DECODER2_PT(60) OR INSTRUCTION_DECODER2_PT(61) + OR INSTRUCTION_DECODER2_PT(62) OR INSTRUCTION_DECODER2_PT(63) + OR INSTRUCTION_DECODER2_PT(64) OR INSTRUCTION_DECODER2_PT(65) + OR INSTRUCTION_DECODER2_PT(66) OR INSTRUCTION_DECODER2_PT(67) + OR INSTRUCTION_DECODER2_PT(68) OR INSTRUCTION_DECODER2_PT(69) + OR INSTRUCTION_DECODER2_PT(70) OR INSTRUCTION_DECODER2_PT(71) + OR INSTRUCTION_DECODER2_PT(72) OR INSTRUCTION_DECODER2_PT(73) + OR INSTRUCTION_DECODER2_PT(74) OR INSTRUCTION_DECODER2_PT(75) + OR INSTRUCTION_DECODER2_PT(76) OR INSTRUCTION_DECODER2_PT(77) + OR INSTRUCTION_DECODER2_PT(78) OR INSTRUCTION_DECODER2_PT(79) + OR INSTRUCTION_DECODER2_PT(80) OR INSTRUCTION_DECODER2_PT(81) + OR INSTRUCTION_DECODER2_PT(82) OR INSTRUCTION_DECODER2_PT(83) + OR INSTRUCTION_DECODER2_PT(84) OR INSTRUCTION_DECODER2_PT(85) + OR INSTRUCTION_DECODER2_PT(86) OR INSTRUCTION_DECODER2_PT(87) + OR INSTRUCTION_DECODER2_PT(88) OR INSTRUCTION_DECODER2_PT(89) + OR INSTRUCTION_DECODER2_PT(90) OR INSTRUCTION_DECODER2_PT(91) + OR INSTRUCTION_DECODER2_PT(92) OR INSTRUCTION_DECODER2_PT(93) + OR INSTRUCTION_DECODER2_PT(94) OR INSTRUCTION_DECODER2_PT(95) + OR INSTRUCTION_DECODER2_PT(96) OR INSTRUCTION_DECODER2_PT(97) + OR INSTRUCTION_DECODER2_PT(98) OR INSTRUCTION_DECODER2_PT(99) + OR INSTRUCTION_DECODER2_PT(100) OR INSTRUCTION_DECODER2_PT(101) + OR INSTRUCTION_DECODER2_PT(102) OR INSTRUCTION_DECODER2_PT(103) + OR INSTRUCTION_DECODER2_PT(105) OR INSTRUCTION_DECODER2_PT(106) + OR INSTRUCTION_DECODER2_PT(107) OR INSTRUCTION_DECODER2_PT(109) + OR INSTRUCTION_DECODER2_PT(112) OR INSTRUCTION_DECODER2_PT(113) + OR INSTRUCTION_DECODER2_PT(114) OR INSTRUCTION_DECODER2_PT(115) + OR INSTRUCTION_DECODER2_PT(116) OR INSTRUCTION_DECODER2_PT(117) + OR INSTRUCTION_DECODER2_PT(118) OR INSTRUCTION_DECODER2_PT(119) + OR INSTRUCTION_DECODER2_PT(120) OR INSTRUCTION_DECODER2_PT(121) + ); +MQQ322:HOLE_DELAY(1) <= + (INSTRUCTION_DECODER2_PT(107)); +MQQ323:HOLE_DELAY(2) <= + (INSTRUCTION_DECODER2_PT(3)); +MQQ324:HOLE_DELAY(3) <= + (INSTRUCTION_DECODER2_PT(2) OR INSTRUCTION_DECODER2_PT(14) + ); +MQQ325:COMPL_EX(1) <= + (INSTRUCTION_DECODER2_PT(4) OR INSTRUCTION_DECODER2_PT(5) + OR INSTRUCTION_DECODER2_PT(6) OR INSTRUCTION_DECODER2_PT(7) + OR INSTRUCTION_DECODER2_PT(8) OR INSTRUCTION_DECODER2_PT(9) + OR INSTRUCTION_DECODER2_PT(11) OR INSTRUCTION_DECODER2_PT(12) + OR INSTRUCTION_DECODER2_PT(13) OR INSTRUCTION_DECODER2_PT(15) + OR INSTRUCTION_DECODER2_PT(16) OR INSTRUCTION_DECODER2_PT(17) + OR INSTRUCTION_DECODER2_PT(18) OR INSTRUCTION_DECODER2_PT(20) + OR INSTRUCTION_DECODER2_PT(21) OR INSTRUCTION_DECODER2_PT(23) + OR INSTRUCTION_DECODER2_PT(84) OR INSTRUCTION_DECODER2_PT(104) + OR INSTRUCTION_DECODER2_PT(110) OR INSTRUCTION_DECODER2_PT(111) + ); +MQQ326:COMPL_EX(2) <= + (INSTRUCTION_DECODER2_PT(27) OR INSTRUCTION_DECODER2_PT(40) + OR INSTRUCTION_DECODER2_PT(43) OR INSTRUCTION_DECODER2_PT(45) + OR INSTRUCTION_DECODER2_PT(47) OR INSTRUCTION_DECODER2_PT(51) + OR INSTRUCTION_DECODER2_PT(56) OR INSTRUCTION_DECODER2_PT(58) + OR INSTRUCTION_DECODER2_PT(66) OR INSTRUCTION_DECODER2_PT(67) + OR INSTRUCTION_DECODER2_PT(77) OR INSTRUCTION_DECODER2_PT(78) + OR INSTRUCTION_DECODER2_PT(80) OR INSTRUCTION_DECODER2_PT(81) + OR INSTRUCTION_DECODER2_PT(86) OR INSTRUCTION_DECODER2_PT(87) + OR INSTRUCTION_DECODER2_PT(89) OR INSTRUCTION_DECODER2_PT(91) + OR INSTRUCTION_DECODER2_PT(94) OR INSTRUCTION_DECODER2_PT(108) + OR INSTRUCTION_DECODER2_PT(109) OR INSTRUCTION_DECODER2_PT(112) + OR INSTRUCTION_DECODER2_PT(113) OR INSTRUCTION_DECODER2_PT(115) + OR INSTRUCTION_DECODER2_PT(117) OR INSTRUCTION_DECODER2_PT(119) + OR INSTRUCTION_DECODER2_PT(120) OR INSTRUCTION_DECODER2_PT(121) + ); +MQQ327:COMPL_EX(3) <= + ('0'); +MQQ328:COMPL_EX(4) <= + (INSTRUCTION_DECODER2_PT(31) OR INSTRUCTION_DECODER2_PT(32) + OR INSTRUCTION_DECODER2_PT(33) OR INSTRUCTION_DECODER2_PT(34) + OR INSTRUCTION_DECODER2_PT(35) OR INSTRUCTION_DECODER2_PT(36) + OR INSTRUCTION_DECODER2_PT(37) OR INSTRUCTION_DECODER2_PT(38) + OR INSTRUCTION_DECODER2_PT(39) OR INSTRUCTION_DECODER2_PT(61) + OR INSTRUCTION_DECODER2_PT(74)); +MQQ329:COMPL_EX(5) <= + (INSTRUCTION_DECODER2_PT(30) OR INSTRUCTION_DECODER2_PT(41) + OR INSTRUCTION_DECODER2_PT(63) OR INSTRUCTION_DECODER2_PT(79) + OR INSTRUCTION_DECODER2_PT(92)); + +-- +-- Final Table Listing +-- *INPUTS*=====================*OUTPUTS*==* +-- | | | +-- | core64 | | +-- | | | | +-- | | is1_instr_L2 | to_uc | +-- | | | is1_instr_L2 | | | +-- | | | | | | | +-- | | | 22222222233 | | | +-- | | 012345 12345678901 | | | +-- *TYPE*=======================+==========+ +-- | P PPPPPP PPPPPPPPPPP | S | +-- *POLARITY*------------------>| + | +-- *PHASE*--------------------->| T | +-- *TERMS*======================+==========+ +-- 1 | 1 011111 00-0-11010- | 1 | +-- 2 | 1 011111 01-1111010- | 1 | +-- 3 | - 011111 1000000000- | 1 | +-- 4 | 1 011111 01011101-1- | 1 | +-- 5 | 1 011111 0011111100- | 1 | +-- 6 | - 011111 10--010101- | 1 | +-- 7 | - 011111 00-0011010- | 1 | +-- 8 | 1 011111 00001101-1- | 1 | +-- 9 | - 011111 0-01111010- | 1 | +-- 10 | - 011111 0-0-110111- | 1 | +-- 11 | 1 111010 ---------01 | 1 | +-- 12 | - 10-0-1 ----------- | 1 | +-- 13 | - 10111- ----------- | 1 | +-- *=======================================* +-- +-- Table MICROCODE Signal Assignments for Product Terms +MQQ330:MICROCODE_PT(1) <= + Eq(( CORE64 & IS1_INSTR_L2(0) & + IS1_INSTR_L2(1) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(3) & IS1_INSTR_L2(4) & + IS1_INSTR_L2(5) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("101111100011010")); +MQQ331:MICROCODE_PT(2) <= + Eq(( CORE64 & IS1_INSTR_L2(0) & + IS1_INSTR_L2(1) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(3) & IS1_INSTR_L2(4) & + IS1_INSTR_L2(5) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("1011111011111010")); +MQQ332:MICROCODE_PT(3) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(3) & + IS1_INSTR_L2(4) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(23) & IS1_INSTR_L2(24) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("0111111000000000")); +MQQ333:MICROCODE_PT(4) <= + Eq(( CORE64 & IS1_INSTR_L2(0) & + IS1_INSTR_L2(1) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(3) & IS1_INSTR_L2(4) & + IS1_INSTR_L2(5) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(25) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("1011111010111011")); +MQQ334:MICROCODE_PT(5) <= + Eq(( CORE64 & IS1_INSTR_L2(0) & + IS1_INSTR_L2(1) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(3) & IS1_INSTR_L2(4) & + IS1_INSTR_L2(5) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(25) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("10111110011111100")); +MQQ335:MICROCODE_PT(6) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(3) & + IS1_INSTR_L2(4) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("01111110010101")); +MQQ336:MICROCODE_PT(7) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(3) & + IS1_INSTR_L2(4) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(22) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(25) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("011111000011010")); +MQQ337:MICROCODE_PT(8) <= + Eq(( CORE64 & IS1_INSTR_L2(0) & + IS1_INSTR_L2(1) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(3) & IS1_INSTR_L2(4) & + IS1_INSTR_L2(5) & IS1_INSTR_L2(21) & + IS1_INSTR_L2(22) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(25) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("1011111000011011")); +MQQ338:MICROCODE_PT(9) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(3) & + IS1_INSTR_L2(4) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(24) & IS1_INSTR_L2(25) & + IS1_INSTR_L2(26) & IS1_INSTR_L2(27) & + IS1_INSTR_L2(28) & IS1_INSTR_L2(29) & + IS1_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("011111001111010")); +MQQ339:MICROCODE_PT(10) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(3) & + IS1_INSTR_L2(4) & IS1_INSTR_L2(5) & + IS1_INSTR_L2(21) & IS1_INSTR_L2(23) & + IS1_INSTR_L2(25) & IS1_INSTR_L2(26) & + IS1_INSTR_L2(27) & IS1_INSTR_L2(28) & + IS1_INSTR_L2(29) & IS1_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("01111100110111")); +MQQ340:MICROCODE_PT(11) <= + Eq(( CORE64 & IS1_INSTR_L2(0) & + IS1_INSTR_L2(1) & IS1_INSTR_L2(2) & + IS1_INSTR_L2(3) & IS1_INSTR_L2(4) & + IS1_INSTR_L2(5) & IS1_INSTR_L2(30) & + IS1_INSTR_L2(31) ) , STD_ULOGIC_VECTOR'("111101001")); +MQQ341:MICROCODE_PT(12) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(3) & IS1_INSTR_L2(5) + ) , STD_ULOGIC_VECTOR'("1001")); +MQQ342:MICROCODE_PT(13) <= + Eq(( IS1_INSTR_L2(0) & IS1_INSTR_L2(1) & + IS1_INSTR_L2(2) & IS1_INSTR_L2(3) & + IS1_INSTR_L2(4) ) , STD_ULOGIC_VECTOR'("10111")); +-- Table MICROCODE Signal Assignments for Outputs +MQQ343:TO_UC <= + (MICROCODE_PT(1) OR MICROCODE_PT(2) + OR MICROCODE_PT(3) OR MICROCODE_PT(4) + OR MICROCODE_PT(5) OR MICROCODE_PT(6) + OR MICROCODE_PT(7) OR MICROCODE_PT(8) + OR MICROCODE_PT(9) OR MICROCODE_PT(10) + OR MICROCODE_PT(11) OR MICROCODE_PT(12) + OR MICROCODE_PT(13)); + +is1_UpdatesLR_din <= UpdatesLR; +is1_UpdatesCR_din <= UpdatesCR; +is1_UpdatesCTR_din <= UpdatesCTR; +is1_UpdatesXER_din <= UpdatesXER; +is1_UpdatesMSR_din <= UpdatesMSR; +is1_UpdatesSPR_din <= UpdatesSPR; +is1_UsesLR_din <= UsesLR; +is1_UsesCR_din <= UsesCR; +is1_UsesCTR_din <= UsesCTR; +is1_UsesXER_din <= UsesXER; +is1_UsesMSR_din <= UsesMSR; +is1_UsesSPR_din <= UsesSPR; +is1_vld_din <= iu_au_ib1_instr_vld; +is1_vld_type_din(0) <= au_iu_is0_to_ucode; +is1_vld_type_din(1) <= au_ib1_ld_or_st; +is1_vld_type_din(2) <= not au_iu_i_dec; +is1_ifar_din <= iu_au_ib1_ifar; +is1_instr_din(0 TO 31) <= iu_au_ib1_instr(0 to 31); +is1_axu_instr_din(6 TO 31) <= au_iu_ib1_ldst_indexed & + au_iu_ib1_ldst_tag(0 to 8) & + au_iu_ib1_ldst_dimm(0 to 15) ; +with ta_sel select is1_ta_d0 <= + iu_au_ib1_instr_ucode_ext(0) & iu_au_ib1_instr(6 to 10) when '0', + iu_au_ib1_instr_ucode_ext(0) & iu_au_ib1_instr(11 to 15) when others; +is1_ta_vld_din <= ta_vld; +is1_ta_din <= au_iu_ib1_ldst_ra(1 to 6) when (au_iu_ib1_ldst_update = '1' or au_iu_ib1_mftgpr = '1') else is1_ta_d0; +with s1_sel select is1_s1_d0 <= + iu_au_ib1_instr_ucode_ext(1) & iu_au_ib1_instr(11 to 15) when '0', + iu_au_ib1_instr_ucode_ext(1) & iu_au_ib1_instr(6 to 10) when others; +is1_s1_vld_din <= s1_vld; +is1_s1_din <= au_iu_ib1_ldst_ra(1 to 6) when au_iu_ib1_ldst = '1' else is1_s1_d0; +with s2_sel select is1_s2_d0 <= + iu_au_ib1_instr_ucode_ext(2) & iu_au_ib1_instr(16 to 20) when '0', + iu_au_ib1_instr_ucode_ext(2) & iu_au_ib1_instr(11 to 15) when others; +is1_s2_vld_din <= s2_vld; +is1_s2_din <= au_iu_ib1_ldst_rb(1 to 6) when au_iu_ib1_ldst_rb_v = '1' else is1_s2_d0; +with s3_sel select is1_s3_d0 <= + iu_au_ib1_instr_ucode_ext(3) & iu_au_ib1_instr(6 to 10) when '0', + iu_au_ib1_instr_ucode_ext(3) & iu_au_ib1_instr(16 to 20) when others; +is1_s3_vld_din <= s3_vld; +is1_s3_din <= au_iu_ib1_ldst_rb(1 to 6) when au_iu_ib1_mffgpr = '1' else is1_s3_d0; +is1_pred_update_din <= iu_au_ib1_instr_pred_vld; +is1_pred_taken_cnt_din <= iu_au_ib1_instr_pred_taken_cnt; +is1_gshare_din <= iu_au_ib1_instr_gshare; +is1_ld_vld_din <= ld_vld; +is1_to_ucode_din <= au_iu_is0_to_ucode; +is1_is_ucode_din <= iu_au_ib1_instr_is_ucode; +is1_axu_ld_or_st_din <= au_ib1_ld_or_st; +is1_axu_store_din <= au_ib1_store; +is1_axu_ldst_size_din <= au_iu_ib1_ldst_size; +is1_axu_ldst_update_din <= au_iu_ib1_ldst_update; +is1_axu_ldst_extpid_din <= au_iu_ib1_ldst_extpid; +is1_axu_ldst_forcealign_din <= au_iu_ib1_ldst_forcealign; +is1_axu_ldst_forceexcept_din <= au_iu_ib1_ldst_forceexcept; +is1_axu_mftgpr_din <= au_iu_ib1_mftgpr; +is1_axu_mffgpr_din <= au_iu_ib1_mffgpr; +is1_axu_movedp_din <= au_iu_ib1_movedp; +is1_axu_instr_type_din <= au_iu_ib1_instr_type; +is1_error_din(0 TO 2) <= iu_au_ib1_instr_error(0 to 2); +is1_force_ram_din <= iu_au_ib1_instr_force_ram; +is1_2ucode_din <= iu_au_ib1_instr_2ucode; +is1_2ucode_type_din <= iu_au_ib1_instr_2ucode_type; +is1_axu_ldst_ra_v_din <= au_iu_ib1_ldst_ra_v; +is1_axu_ldst_rb_v_din <= au_iu_ib1_ldst_rb_v; +is1_instr_proc : process ( + +xu_iu_ib1_flush, +iu_au_is1_stall, +is1_vld_din, +is1_vld_type_din, +is1_instr_din, +is1_axu_instr_din, +is1_ta_vld_din, +is1_ta_din, +is1_s1_vld_din, +is1_s1_din, +is1_s2_vld_din, +is1_s2_din, +is1_s3_vld_din, +is1_s3_din, +is1_pred_update_din, +is1_pred_taken_cnt_din, +is1_gshare_din, + +is1_UpdatesLR_din, +is1_UpdatesCR_din, +is1_UpdatesCTR_din, +is1_UpdatesXER_din, +is1_UpdatesMSR_din, +is1_UpdatesSPR_din, +is1_UsesLR_din, +is1_UsesCR_din, +is1_UsesCTR_din, +is1_UsesXER_din, +is1_UsesMSR_din, +is1_UsesSPR_din, + +is1_ld_vld_din, +is1_to_ucode_din, +is1_is_ucode_din, + +is1_ifar_din, +is1_error_din, +is1_axu_ldst_ra_v_din, +is1_axu_ldst_rb_v_din, +is1_axu_ld_or_st_din, +is1_axu_store_din, +is1_axu_ldst_size_din, +is1_axu_ldst_update_din, +is1_axu_ldst_extpid_din, +is1_axu_ldst_forcealign_din, +is1_axu_ldst_forceexcept_din, +is1_axu_mftgpr_din, +is1_axu_mffgpr_din, +is1_axu_movedp_din, +is1_axu_instr_type_din, + +is1_force_ram_din, +is1_2ucode_din, +is1_2ucode_type_din, +is1_vld_L2, +is1_vld_type_L2, +is1_instr_L2, +is1_axu_instr_L2, +is1_ta_vld_L2, +is1_ta_L2, +is1_s1_vld_L2, +is1_s1_L2, +is1_s2_vld_L2, +is1_s2_L2, +is1_s3_vld_L2, +is1_s3_L2, +is1_pred_update_L2, +is1_pred_taken_cnt_L2, +is1_gshare_L2, + +is1_UpdatesLR_L2, +is1_UpdatesCR_L2, +is1_UpdatesCTR_L2, +is1_UpdatesXER_L2, +is1_UpdatesMSR_L2, +is1_UpdatesSPR_L2, +is1_UsesLR_L2, +is1_UsesCR_L2, +is1_UsesCTR_L2, +is1_UsesXER_L2, +is1_UsesMSR_L2, +is1_UsesSPR_L2, + +is1_ld_vld_L2, +is1_to_ucode_L2, +is1_is_ucode_L2, + +is1_ifar_L2, +is1_error_L2, +is1_axu_ldst_ra_v_L2, +is1_axu_ldst_rb_v_L2, +is1_axu_ld_or_st_L2, +is1_axu_store_L2, +is1_axu_ldst_size_L2, +is1_axu_ldst_update_L2, +is1_axu_ldst_extpid_L2, +is1_axu_ldst_forcealign_L2, +is1_axu_ldst_forceexcept_L2, +is1_axu_mftgpr_L2, +is1_axu_mffgpr_L2, +is1_axu_movedp_L2, +is1_axu_instr_type_L2, + +is1_force_ram_L2, +is1_2ucode_L2, +is1_2ucode_type_L2 +) + +begin + +is1_vld_d <= is1_vld_din; +is1_vld_type_d <= is1_vld_type_din; +is1_instr_d <= is1_instr_din; +is1_axu_instr_d <= is1_axu_instr_din; +is1_ta_vld_d <= is1_ta_vld_din; +is1_ta_d <= is1_ta_din; +is1_s1_vld_d <= is1_s1_vld_din; +is1_s1_d <= is1_s1_din; +is1_s2_vld_d <= is1_s2_vld_din; +is1_s2_d <= is1_s2_din; +is1_s3_vld_d <= is1_s3_vld_din; +is1_s3_d <= is1_s3_din; +is1_pred_update_d <= is1_pred_update_din; +is1_pred_taken_cnt_d <= is1_pred_taken_cnt_din; +is1_gshare_d <= is1_gshare_din; +is1_UpdatesLR_d <= is1_UpdatesLR_din; +is1_UpdatesCR_d <= is1_UpdatesCR_din; +is1_UpdatesCTR_d <= is1_UpdatesCTR_din; +is1_UpdatesXER_d <= is1_UpdatesXER_din; +is1_UpdatesMSR_d <= is1_UpdatesMSR_din; +is1_UpdatesSPR_d <= is1_UpdatesSPR_din; +is1_UsesLR_d <= is1_UsesLR_din; +is1_UsesCR_d <= is1_UsesCR_din; +is1_UsesCTR_d <= is1_UsesCTR_din; +is1_UsesXER_d <= is1_UsesXER_din; +is1_UsesMSR_d <= is1_UsesMSR_din; +is1_UsesSPR_d <= is1_UsesSPR_din; +is1_ld_vld_d <= is1_ld_vld_din; +is1_to_ucode_d <= is1_to_ucode_din; +is1_is_ucode_d <= is1_is_ucode_din; +is1_ifar_d <= is1_ifar_din; +is1_error_d <= is1_error_din; +is1_axu_ldst_ra_v_d <= is1_axu_ldst_ra_v_din; +is1_axu_ldst_rb_v_d <= is1_axu_ldst_rb_v_din; +is1_axu_ld_or_st_d <= is1_axu_ld_or_st_din; +is1_axu_store_d <= is1_axu_store_din; +is1_axu_ldst_size_d <= is1_axu_ldst_size_din; +is1_axu_ldst_update_d <= is1_axu_ldst_update_din; +is1_axu_ldst_extpid_d <= is1_axu_ldst_extpid_din; +is1_axu_ldst_forcealign_d <= is1_axu_ldst_forcealign_din; +is1_axu_ldst_forceexcept_d <= is1_axu_ldst_forceexcept_din; +is1_axu_mftgpr_d <= is1_axu_mftgpr_din; +is1_axu_mffgpr_d <= is1_axu_mffgpr_din; +is1_axu_movedp_d <= is1_axu_movedp_din; +is1_axu_instr_type_d <= is1_axu_instr_type_din; +is1_force_ram_d <= is1_force_ram_din; +is1_2ucode_d <= is1_2ucode_din; +is1_2ucode_type_d <= is1_2ucode_type_din; +if (iu_au_is1_stall = '1') then +is1_vld_d <= is1_vld_l2; +is1_vld_type_d <= is1_vld_type_l2; +is1_instr_d <= is1_instr_l2; +is1_axu_instr_d <= is1_axu_instr_l2; +is1_ta_vld_d <= is1_ta_vld_l2; +is1_ta_d <= is1_ta_l2; +is1_s1_vld_d <= is1_s1_vld_l2; +is1_s1_d <= is1_s1_l2; +is1_s2_vld_d <= is1_s2_vld_l2; +is1_s2_d <= is1_s2_l2; +is1_s3_vld_d <= is1_s3_vld_l2; +is1_s3_d <= is1_s3_l2; +is1_pred_update_d <= is1_pred_update_l2; +is1_pred_taken_cnt_d <= is1_pred_taken_cnt_l2; +is1_gshare_d <= is1_gshare_l2; +is1_UpdatesLR_d <= is1_UpdatesLR_l2; +is1_UpdatesCR_d <= is1_UpdatesCR_l2; +is1_UpdatesCTR_d <= is1_UpdatesCTR_l2; +is1_UpdatesXER_d <= is1_UpdatesXER_l2; +is1_UpdatesMSR_d <= is1_UpdatesMSR_l2; +is1_UpdatesSPR_d <= is1_UpdatesSPR_l2; +is1_UsesLR_d <= is1_UsesLR_l2; +is1_UsesCR_d <= is1_UsesCR_l2; +is1_UsesCTR_d <= is1_UsesCTR_l2; +is1_UsesXER_d <= is1_UsesXER_l2; +is1_UsesMSR_d <= is1_UsesMSR_l2; +is1_UsesSPR_d <= is1_UsesSPR_l2; +is1_ld_vld_d <= is1_ld_vld_l2; +is1_to_ucode_d <= is1_to_ucode_l2; +is1_is_ucode_d <= is1_is_ucode_l2; +is1_ifar_d <= is1_ifar_l2; +is1_error_d <= is1_error_l2; +is1_axu_ldst_ra_v_d <= is1_axu_ldst_ra_v_l2; +is1_axu_ldst_rb_v_d <= is1_axu_ldst_rb_v_l2; +is1_axu_ld_or_st_d <= is1_axu_ld_or_st_l2; +is1_axu_store_d <= is1_axu_store_l2; +is1_axu_ldst_size_d <= is1_axu_ldst_size_l2; +is1_axu_ldst_update_d <= is1_axu_ldst_update_l2; +is1_axu_ldst_extpid_d <= is1_axu_ldst_extpid_l2; +is1_axu_ldst_forcealign_d <= is1_axu_ldst_forcealign_l2; +is1_axu_ldst_forceexcept_d <= is1_axu_ldst_forceexcept_l2; +is1_axu_mftgpr_d <= is1_axu_mftgpr_l2; +is1_axu_mffgpr_d <= is1_axu_mffgpr_l2; +is1_axu_movedp_d <= is1_axu_movedp_l2; +is1_axu_instr_type_d <= is1_axu_instr_type_l2; +is1_force_ram_d <= is1_force_ram_l2; +is1_2ucode_d <= is1_2ucode_l2; +is1_2ucode_type_d <= is1_2ucode_type_l2; +end if; +if (xu_iu_ib1_flush = '1') then +is1_vld_d <= '0'; +end if; +end process is1_instr_proc; +act_valid <= tiup; +act_nonvalid <= not fdep_fdec_weak_stall; +is1_vld: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_valid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_vld_offset), + scout => sov(is1_vld_offset), + din => is1_vld_d, + dout => is1_vld_l2); +is1_vld_type: tri_rlmreg_p + generic map (width => is1_vld_type_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_vld_type_offset to is1_vld_type_offset + is1_vld_type_l2'length-1), + scout => sov(is1_vld_type_offset to is1_vld_type_offset + is1_vld_type_l2'length-1), + din => is1_vld_type_d, + dout => is1_vld_type_l2); +is1_instr: tri_rlmreg_p + generic map (width => is1_instr_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_instr_offset to is1_instr_offset + is1_instr_l2'length-1), + scout => sov(is1_instr_offset to is1_instr_offset + is1_instr_l2'length-1), + din => is1_instr_d, + dout => is1_instr_l2); +is1_axu_instr: tri_rlmreg_p + generic map (width => is1_axu_instr_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_axu_instr_offset to is1_axu_instr_offset + is1_axu_instr_l2'length-1), + scout => sov(is1_axu_instr_offset to is1_axu_instr_offset + is1_axu_instr_l2'length-1), + din => is1_axu_instr_d, + dout => is1_axu_instr_l2); +is1_ta_vld: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_ta_vld_offset), + scout => sov(is1_ta_vld_offset), + din => is1_ta_vld_d, + dout => is1_ta_vld_l2); +is1_ta: tri_rlmreg_p + generic map (width => is1_ta_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_ta_offset to is1_ta_offset + is1_ta_l2'length-1), + scout => sov(is1_ta_offset to is1_ta_offset + is1_ta_l2'length-1), + din => is1_ta_d, + dout => is1_ta_l2); +is1_s1_vld: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_s1_vld_offset), + scout => sov(is1_s1_vld_offset), + din => is1_s1_vld_d, + dout => is1_s1_vld_l2); +is1_s1: tri_rlmreg_p + generic map (width => is1_s1_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_s1_offset to is1_s1_offset + is1_s1_l2'length-1), + scout => sov(is1_s1_offset to is1_s1_offset + is1_s1_l2'length-1), + din => is1_s1_d, + dout => is1_s1_l2); +is1_s2_vld: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_s2_vld_offset), + scout => sov(is1_s2_vld_offset), + din => is1_s2_vld_d, + dout => is1_s2_vld_l2); +is1_s2: tri_rlmreg_p + generic map (width => is1_s2_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_s2_offset to is1_s2_offset + is1_s2_l2'length-1), + scout => sov(is1_s2_offset to is1_s2_offset + is1_s2_l2'length-1), + din => is1_s2_d, + dout => is1_s2_l2); +is1_s3_vld: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_s3_vld_offset), + scout => sov(is1_s3_vld_offset), + din => is1_s3_vld_d, + dout => is1_s3_vld_l2); +is1_s3: tri_rlmreg_p + generic map (width => is1_s3_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_s3_offset to is1_s3_offset + is1_s3_l2'length-1), + scout => sov(is1_s3_offset to is1_s3_offset + is1_s3_l2'length-1), + din => is1_s3_d, + dout => is1_s3_l2); +is1_pred_update: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_pred_update_offset), + scout => sov(is1_pred_update_offset), + din => is1_pred_update_d, + dout => is1_pred_update_l2); +is1_pred_taken_cnt: tri_rlmreg_p + generic map (width => is1_pred_taken_cnt_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_pred_taken_cnt_offset to is1_pred_taken_cnt_offset + is1_pred_taken_cnt_l2'length-1), + scout => sov(is1_pred_taken_cnt_offset to is1_pred_taken_cnt_offset + is1_pred_taken_cnt_l2'length-1), + din => is1_pred_taken_cnt_d, + dout => is1_pred_taken_cnt_l2); +is1_gshare: tri_rlmreg_p + generic map (width => is1_gshare_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_gshare_offset to is1_gshare_offset + is1_gshare_l2'length-1), + scout => sov(is1_gshare_offset to is1_gshare_offset + is1_gshare_l2'length-1), + din => is1_gshare_d, + dout => is1_gshare_l2); +is1_UpdatesLR: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_UpdatesLR_offset), + scout => sov(is1_UpdatesLR_offset), + din => is1_UpdatesLR_d, + dout => is1_UpdatesLR_l2); +is1_UpdatesCR: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_UpdatesCR_offset), + scout => sov(is1_UpdatesCR_offset), + din => is1_UpdatesCR_d, + dout => is1_UpdatesCR_l2); +is1_UpdatesCTR: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_UpdatesCTR_offset), + scout => sov(is1_UpdatesCTR_offset), + din => is1_UpdatesCTR_d, + dout => is1_UpdatesCTR_l2); +is1_UpdatesXER: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_UpdatesXER_offset), + scout => sov(is1_UpdatesXER_offset), + din => is1_UpdatesXER_d, + dout => is1_UpdatesXER_l2); +is1_UpdatesMSR: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_UpdatesMSR_offset), + scout => sov(is1_UpdatesMSR_offset), + din => is1_UpdatesMSR_d, + dout => is1_UpdatesMSR_l2); +is1_UpdatesSPR: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_UpdatesSPR_offset), + scout => sov(is1_UpdatesSPR_offset), + din => is1_UpdatesSPR_d, + dout => is1_UpdatesSPR_l2); +is1_UsesLR: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_UsesLR_offset), + scout => sov(is1_UsesLR_offset), + din => is1_UsesLR_d, + dout => is1_UsesLR_l2); +is1_UsesCR: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_UsesCR_offset), + scout => sov(is1_UsesCR_offset), + din => is1_UsesCR_d, + dout => is1_UsesCR_l2); +is1_UsesCTR: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_UsesCTR_offset), + scout => sov(is1_UsesCTR_offset), + din => is1_UsesCTR_d, + dout => is1_UsesCTR_l2); +is1_UsesXER: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_UsesXER_offset), + scout => sov(is1_UsesXER_offset), + din => is1_UsesXER_d, + dout => is1_UsesXER_l2); +is1_UsesMSR: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_UsesMSR_offset), + scout => sov(is1_UsesMSR_offset), + din => is1_UsesMSR_d, + dout => is1_UsesMSR_l2); +is1_UsesSPR: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_UsesSPR_offset), + scout => sov(is1_UsesSPR_offset), + din => is1_UsesSPR_d, + dout => is1_UsesSPR_l2); +is1_ld_vld: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_ld_vld_offset), + scout => sov(is1_ld_vld_offset), + din => is1_ld_vld_d, + dout => is1_ld_vld_l2); +is1_is_ucode: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_is_ucode_offset), + scout => sov(is1_is_ucode_offset), + din => is1_is_ucode_d, + dout => is1_is_ucode_l2); +is1_to_ucode: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_to_ucode_offset), + scout => sov(is1_to_ucode_offset), + din => is1_to_ucode_d, + dout => is1_to_ucode_l2); +is1_ifar: tri_rlmreg_p + generic map (width => is1_ifar_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_ifar_offset to is1_ifar_offset + is1_ifar_l2'length-1), + scout => sov(is1_ifar_offset to is1_ifar_offset + is1_ifar_l2'length-1), + din => is1_ifar_d, + dout => is1_ifar_l2); +is1_error: tri_rlmreg_p + generic map (width => is1_error_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_error_offset to is1_error_offset + is1_error_l2'length-1), + scout => sov(is1_error_offset to is1_error_offset + is1_error_l2'length-1), + din => is1_error_d, + dout => is1_error_l2); +--axu +is1_axu_ldst_ra_v: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_axu_ldst_ra_v_offset), + scout => sov(is1_axu_ldst_ra_v_offset), + din => is1_axu_ldst_ra_v_d, + dout => is1_axu_ldst_ra_v_l2); +is1_axu_ldst_rb_v: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_axu_ldst_rb_v_offset), + scout => sov(is1_axu_ldst_rb_v_offset), + din => is1_axu_ldst_rb_v_d, + dout => is1_axu_ldst_rb_v_l2); +is1_axu_ld_or_st: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_axu_ld_or_st_offset), + scout => sov(is1_axu_ld_or_st_offset), + din => is1_axu_ld_or_st_d, + dout => is1_axu_ld_or_st_l2); +is1_axu_store: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_axu_store_offset), + scout => sov(is1_axu_store_offset), + din => is1_axu_store_d, + dout => is1_axu_store_l2); +is1_axu_ldst_size: tri_rlmreg_p + generic map (width => is1_axu_ldst_size_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_axu_ldst_size_offset to is1_axu_ldst_size_offset + is1_axu_ldst_size_l2'length-1), + scout => sov(is1_axu_ldst_size_offset to is1_axu_ldst_size_offset + is1_axu_ldst_size_l2'length-1), + din => is1_axu_ldst_size_d, + dout => is1_axu_ldst_size_l2); +is1_axu_ldst_update: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_axu_ldst_update_offset), + scout => sov(is1_axu_ldst_update_offset), + din => is1_axu_ldst_update_d, + dout => is1_axu_ldst_update_l2); +is1_axu_ldst_extpid: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_axu_ldst_extpid_offset), + scout => sov(is1_axu_ldst_extpid_offset), + din => is1_axu_ldst_extpid_d, + dout => is1_axu_ldst_extpid_l2); +is1_axu_ldst_forcealign: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_axu_ldst_forcealign_offset), + scout => sov(is1_axu_ldst_forcealign_offset), + din => is1_axu_ldst_forcealign_d, + dout => is1_axu_ldst_forcealign_l2); +is1_axu_ldst_forceexcept: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_axu_ldst_forceexcept_offset), + scout => sov(is1_axu_ldst_forceexcept_offset), + din => is1_axu_ldst_forceexcept_d, + dout => is1_axu_ldst_forceexcept_l2); +is1_axu_movedp: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_axu_movedp_offset), + scout => sov(is1_axu_movedp_offset), + din => is1_axu_movedp_d, + dout => is1_axu_movedp_l2); +is1_axu_mffgpr: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_axu_mffgpr_offset), + scout => sov(is1_axu_mffgpr_offset), + din => is1_axu_mffgpr_d, + dout => is1_axu_mffgpr_l2); +is1_axu_mftgpr: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_axu_mftgpr_offset), + scout => sov(is1_axu_mftgpr_offset), + din => is1_axu_mftgpr_d, + dout => is1_axu_mftgpr_l2); +is1_axu_instr_type: tri_rlmreg_p + generic map (width => is1_axu_instr_type_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_axu_instr_type_offset to is1_axu_instr_type_offset + is1_axu_instr_type_l2'length-1), + scout => sov(is1_axu_instr_type_offset to is1_axu_instr_type_offset + is1_axu_instr_type_l2'length-1), + din => is1_axu_instr_type_d, + dout => is1_axu_instr_type_l2); +is1_force_ram: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_force_ram_offset), + scout => sov(is1_force_ram_offset), + din => is1_force_ram_d, + dout => is1_force_ram_l2); +is1_2ucode: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_2ucode_offset), + scout => sov(is1_2ucode_offset), + din => is1_2ucode_d, + dout => is1_2ucode_l2); +is1_2ucode_type: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is1_2ucode_type_offset), + scout => sov(is1_2ucode_type_offset), + din => is1_2ucode_type_d, + dout => is1_2ucode_type_l2); +spare_latch: tri_rlmreg_p + generic map (width => spare_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(spare_offset to spare_offset + spare_l2'length-1), + scout => sov(spare_offset to spare_offset + spare_l2'length-1), + din => spare_l2, + dout => spare_l2); +iu_au_is1_cr_user_v <= is1_UsesCR_L2 and is1_vld_L2; +iu_au_is0_cr_setter <= UpdatesCR; +-- Outputs to FXU dependency +fdec_fdep_is1_vld <= is1_vld_L2 and or_reduce(is1_vld_type_L2(0 to 2)); +fdec_fdep_is1_instr(0 TO 15) <= is1_instr_L2(0 to 15); +fdec_fdep_is1_instr(16 TO 31) <= is1_axu_instr_L2(16 to 31) when is1_axu_ld_or_st_L2 = '1' and is1_to_ucode_L2 = '0' else + is1_instr_L2(16 to 31); +fdec_fdep_is1_axu_ldst_indexed <= is1_axu_instr_L2(6); +fdec_fdep_is1_axu_ldst_tag <= is1_axu_instr_L2(7 to 15); +fdec_fdep_is1_ta_vld <= (is1_ta_vld_L2 and is1_vld_type_L2(2)) or + (is1_axu_ldst_update_L2 or (is1_axu_mftgpr_L2 and not is1_axu_movedp_L2)); +fdec_fdep_is1_ta <= is1_ta_L2; +fdec_fdep_is1_s1_vld <= (is1_s1_vld_L2 and is1_vld_type_L2(2)) or + is1_axu_ldst_ra_v_L2; +fdec_fdep_is1_s1 <= is1_s1_L2; +fdec_fdep_is1_s2_vld <= (is1_s2_vld_L2 and is1_vld_type_L2(2)) or + is1_axu_ldst_rb_v_L2; +fdec_fdep_is1_s2 <= is1_s2_L2; +fdec_fdep_is1_s3_vld <= (is1_s3_vld_L2 and is1_vld_type_L2(2)) or + (is1_axu_ldst_rb_v_L2 and is1_axu_mffgpr_L2); +fdec_fdep_is1_s3 <= is1_s3_L2; +fdec_fdep_is1_pred_update <= is1_pred_update_L2; +fdec_fdep_is1_pred_taken_cnt <= is1_pred_taken_cnt_L2; +fdec_fdep_is1_gshare <= is1_gshare_L2; +fdec_fdep_is1_UpdatesLR <= is1_UpdatesLR_L2; +fdec_fdep_is1_UpdatesCR <= is1_UpdatesCR_L2; +fdec_fdep_is1_UpdatesCTR <= is1_UpdatesCTR_L2; +fdec_fdep_is1_UpdatesXER <= is1_UpdatesXER_L2; +fdec_fdep_is1_UpdatesMSR <= is1_UpdatesMSR_L2; +fdec_fdep_is1_UpdatesSPR <= is1_UpdatesSPR_L2; +fdec_fdep_is1_UsesLR <= is1_UsesLR_L2; +fdec_fdep_is1_UsesCR <= is1_UsesCR_L2; +fdec_fdep_is1_UsesCTR <= is1_UsesCTR_L2; +fdec_fdep_is1_UsesXER <= is1_UsesXER_L2; +fdec_fdep_is1_UsesMSR <= is1_UsesMSR_L2; +fdec_fdep_is1_UsesSPR <= is1_UsesSPR_L2; +fdec_fdep_is1_hole_delay <= hole_delay; +fdec_fdep_is1_ld_vld <= (is1_ld_vld_L2 and is1_vld_type_L2(2)) or + (is1_axu_ldst_update_L2 and not is1_axu_store_L2); +fdec_fdep_is1_to_ucode <= is1_to_ucode_L2 or is1_2ucode_L2 or to_uc; +fdec_fdep_is1_is_ucode <= is1_is_ucode_L2; +fdec_fdep_is1_complete <= compl_ex; +fdec_fdep_is1_ifar <= is1_ifar_L2; +fdec_fdep_is1_error(0 TO 1) <= is1_error_L2(0 to 1); +fdec_fdep_is1_error(2) <= not is1_axu_ld_or_st_L2 and not is1_to_ucode_L2 and not isFxuIssue when is1_error_L2(0 to 1) = "00" else + is1_error_L2(2); +fdec_fdep_is1_axu_ld_or_st <= is1_axu_ld_or_st_L2; +fdec_fdep_is1_axu_store <= is1_axu_store_L2; +fdec_fdep_is1_axu_ldst_size <= is1_axu_ldst_size_L2; +fdec_fdep_is1_axu_ldst_update <= is1_axu_ldst_update_L2; +fdec_fdep_is1_axu_ldst_extpid <= is1_axu_ldst_extpid_L2; +fdec_fdep_is1_axu_ldst_forcealign <= is1_axu_ldst_forcealign_L2; +fdec_fdep_is1_axu_ldst_forceexcept <= is1_axu_ldst_forceexcept_L2; +fdec_fdep_is1_axu_mftgpr <= is1_axu_mftgpr_L2; +fdec_fdep_is1_axu_mffgpr <= is1_axu_mffgpr_L2; +fdec_fdep_is1_axu_movedp <= is1_axu_movedp_L2; +fdec_fdep_is1_axu_instr_type <= gate(is1_axu_instr_type_L2, is1_axu_ld_or_st_L2 or is1_to_ucode_L2); +fdec_fdep_is1_match <= (spr_dec_mask(0 to 31) and is1_instr_L2(0 to 31)) = (spr_dec_mask(0 to 31) and spr_dec_match(0 to 31)); +fdec_fdep_is1_force_ram <= is1_force_ram_L2; +fdec_fdep_is1_2ucode <= is1_2ucode_L2; +fdec_fdep_is1_2ucode_type <= is1_2ucode_type_L2; +----------------------------------------------------------------------- +-- Scan +----------------------------------------------------------------------- +siv(0 TO scan_right) <= sov(1 to scan_right) & scan_in; +scan_out <= sov(0); +END IUQ_FXU_DECODE; diff --git a/rel/src/vhdl/work/iuq_fxu_dep.vhdl b/rel/src/vhdl/work/iuq_fxu_dep.vhdl new file mode 100644 index 0000000..085ceb2 --- /dev/null +++ b/rel/src/vhdl/work/iuq_fxu_dep.vhdl @@ -0,0 +1,3087 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee, ibm; +use ieee.std_logic_1164.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +library support; +use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; +library work; +use work.iuq_pkg.all; + +entity iuq_fxu_dep is + generic(expand_type : integer := 2; + regmode : integer := 6; + lmq_entries : integer := 8); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + + pc_iu_func_sl_thold_0_b : in std_ulogic; + pc_iu_sg_0 : in std_ulogic; + forcee : in std_ulogic; + d_mode : in std_ulogic; + delay_lclkr : in std_ulogic; + mpw1_b : in std_ulogic; + mpw2_b : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + pc_iu_trace_bus_enable : in std_ulogic; + pc_iu_event_bus_enable : in std_ulogic; + fdep_dbg_data : out std_ulogic_vector(0 to 21); + fdep_perf_event : out std_ulogic_vector(0 to 11); + + + + fdec_fdep_is1_vld : in std_ulogic; + fdec_fdep_is1_instr : in std_ulogic_vector(0 to 31); + fdec_fdep_is1_ta_vld : in std_ulogic; + fdec_fdep_is1_ta : in std_ulogic_vector(0 to 5); + fdec_fdep_is1_s1_vld : in std_ulogic; + fdec_fdep_is1_s1 : in std_ulogic_vector(0 to 5); + fdec_fdep_is1_s2_vld : in std_ulogic; + fdec_fdep_is1_s2 : in std_ulogic_vector(0 to 5); + fdec_fdep_is1_s3_vld : in std_ulogic; + fdec_fdep_is1_s3 : in std_ulogic_vector(0 to 5); + fdec_fdep_is1_pred_update : in std_ulogic; + fdec_fdep_is1_pred_taken_cnt : in std_ulogic_vector(0 to 1); + fdec_fdep_is1_gshare : in std_ulogic_vector(0 to 3); + fdec_fdep_is1_UpdatesLR : in std_ulogic; + fdec_fdep_is1_UpdatesCR : in std_ulogic; + fdec_fdep_is1_UpdatesCTR : in std_ulogic; + fdec_fdep_is1_UpdatesXER : in std_ulogic; + fdec_fdep_is1_UpdatesMSR : in std_ulogic; + fdec_fdep_is1_UpdatesSPR : in std_ulogic; + fdec_fdep_is1_UsesLR : in std_ulogic; + fdec_fdep_is1_UsesCR : in std_ulogic; + fdec_fdep_is1_UsesCTR : in std_ulogic; + fdec_fdep_is1_UsesXER : in std_ulogic; + fdec_fdep_is1_UsesMSR : in std_ulogic; + fdec_fdep_is1_UsesSPR : in std_ulogic; + fdec_fdep_is1_hole_delay : in std_ulogic_vector(0 to 2); + fdec_fdep_is1_ld_vld : in std_ulogic; + fdec_fdep_is1_to_ucode : in std_ulogic; + fdec_fdep_is1_is_ucode : in std_ulogic; + fdec_fdep_is1_ifar : in EFF_IFAR; + fdec_fdep_is1_error : in std_ulogic_vector(0 to 2); + fdec_fdep_is1_complete : in std_ulogic_vector(0 to 4); + + fdec_fdep_is1_axu_ld_or_st : in std_ulogic; + fdec_fdep_is1_axu_store : in std_ulogic; + fdec_fdep_is1_axu_ldst_indexed : in std_ulogic; + fdec_fdep_is1_axu_ldst_tag : in std_ulogic_vector(0 to 8); + fdec_fdep_is1_axu_ldst_size : in std_ulogic_vector(0 to 5); + fdec_fdep_is1_axu_ldst_update : in std_ulogic; + fdec_fdep_is1_axu_ldst_extpid : in std_ulogic; + fdec_fdep_is1_axu_ldst_forcealign : in std_ulogic; + fdec_fdep_is1_axu_ldst_forceexcept : in std_ulogic; + fdec_fdep_is1_axu_mftgpr : in std_ulogic; + fdec_fdep_is1_axu_mffgpr : in std_ulogic; + fdec_fdep_is1_axu_movedp : in std_ulogic; + fdec_fdep_is1_axu_instr_type : in std_ulogic_vector(0 to 2); + fdec_fdep_is1_match : in std_ulogic; + fdec_fdep_is1_force_ram : in std_ulogic; + fdec_fdep_is1_2ucode : in std_ulogic; + fdec_fdep_is1_2ucode_type : in std_ulogic; + + + fdep_fiss_is2_instr : out std_ulogic_vector(0 to 31); + fdep_fiss_is2_ta_vld : out std_ulogic; + fdep_fiss_is2_ta : out std_ulogic_vector(0 to 5); + fdep_fiss_is2_s1_vld : out std_ulogic; + fdep_fiss_is2_s1 : out std_ulogic_vector(0 to 5); + fdep_fiss_is2_s2_vld : out std_ulogic; + fdep_fiss_is2_s2 : out std_ulogic_vector(0 to 5); + fdep_fiss_is2_s3_vld : out std_ulogic; + fdep_fiss_is2_s3 : out std_ulogic_vector(0 to 5); + fdep_fiss_is2_pred_update : out std_ulogic; + fdep_fiss_is2_pred_taken_cnt : out std_ulogic_vector(0 to 1); + fdep_fiss_is2_gshare : out std_ulogic_vector(0 to 3); + fdep_fiss_is2_ifar : out EFF_IFAR; + fdep_fiss_is2_error : out std_ulogic_vector(0 to 2); + fdep_fiss_is2_axu_ld_or_st : out std_ulogic; + fdep_fiss_is2_axu_store : out std_ulogic; + fdep_fiss_is2_axu_ldst_indexed : out std_ulogic; + fdep_fiss_is2_axu_ldst_tag : out std_ulogic_vector(0 to 8); + fdep_fiss_is2_axu_ldst_size : out std_ulogic_vector(0 to 5); + fdep_fiss_is2_axu_ldst_update : out std_ulogic; + fdep_fiss_is2_axu_ldst_extpid : out std_ulogic; + fdep_fiss_is2_axu_ldst_forcealign : out std_ulogic; + fdep_fiss_is2_axu_ldst_forceexcept : out std_ulogic; + fdep_fiss_is2_axu_mftgpr : out std_ulogic; + fdep_fiss_is2_axu_mffgpr : out std_ulogic; + fdep_fiss_is2_axu_movedp : out std_ulogic; + fdep_fiss_is2_axu_instr_type : out std_ulogic_vector(0 to 2); + fdep_fiss_is2_match : out std_ulogic; + fdep_fiss_is2_2ucode : out std_ulogic; + fdep_fiss_is2_2ucode_type : out std_ulogic; + fdep_fiss_is2_hole_delay : out std_ulogic_vector(0 to 2); + fdep_fiss_is2_to_ucode : out std_ulogic; + fdep_fiss_is2_is_ucode : out std_ulogic; + fdep_fiss_is2early_vld : out std_ulogic; + fdep_fiss_is1_xu_dep_hit_b : out std_ulogic; + fiss_fdep_is2_take : in std_ulogic; + + i_afd_is1_instr_v : in std_ulogic; + au_iu_issue_stall : in std_ulogic; + iu_au_is2_stall : out std_ulogic; + au_iu_is1_dep_hit : in std_ulogic; + au_iu_is1_dep_hit_b : in std_ulogic; + au_iu_is2_axubusy : in std_ulogic; + iu_au_is1_stall : out std_ulogic; + fdep_fdec_buff_stall : out std_ulogic; + fdep_fdec_weak_stall : out std_ulogic; + + xu_iu_slowspr_done : in std_ulogic; + xu_iu_multdiv_done : in std_ulogic; + iu_au_is1_hold : out std_ulogic; + xu_iu_loadmiss_vld : in std_ulogic; + xu_iu_loadmiss_qentry : in std_ulogic_vector(0 to lmq_entries-1); + xu_iu_loadmiss_target : in std_ulogic_vector(0 to 5); + xu_iu_loadmiss_target_type : in std_ulogic; + xu_iu_complete_vld : in std_ulogic; + xu_iu_complete_qentry : in std_ulogic_vector(0 to lmq_entries-1); + xu_iu_complete_target_type : in std_ulogic; + xu_iu_single_instr_mode : in std_ulogic; + + ic_fdep_load_quiesce : in std_ulogic; + iu_xu_quiesce : out std_ulogic; + + xu_iu_membar_tid : in std_ulogic; + xu_iu_set_barr_tid : in std_ulogic; + xu_iu_larx_done_tid : in std_ulogic; + an_ac_sync_ack : in std_ulogic; + ic_fdep_icbi_ack : in std_ulogic; + an_ac_stcx_complete : in std_ulogic; + mm_iu_barrier_done : in std_ulogic; + + spr_fdep_ll_hold : in std_ulogic; + xu_iu_spr_ccr2_en_dcr : in std_ulogic; + + xu_iu_is1_flush : in std_ulogic; + xu_iu_is2_flush : in std_ulogic; + xu_iu_rf0_flush : in std_ulogic; + xu_iu_rf1_flush : in std_ulogic; + xu_iu_ex1_flush : in std_ulogic; + xu_iu_ex2_flush : in std_ulogic; + xu_iu_ex3_flush : in std_ulogic; + xu_iu_ex4_flush : in std_ulogic; + xu_iu_ex5_flush : in std_ulogic +); +end iuq_fxu_dep; +ARCHITECTURE IUQ_FXU_DEP + OF IUQ_FXU_DEP + IS +--@@ Signal Declarations +SIGNAL BARRIER_PT : STD_ULOGIC_VECTOR(1 TO 24) := +(OTHERS=> 'U'); +SIGNAL SLOWSPR_TABLE_PT : STD_ULOGIC_VECTOR(1 TO 20) := +(OTHERS=> 'U'); +SIGNAL is_bar : STD_ULOGIC := +'U'; +SIGNAL is_slowspr : STD_ULOGIC := +'U'; +-- Scan chain connenctions +constant is2_vld_offset : natural := 0; +constant is2_instr_offset : natural := is2_vld_offset + 1; +constant is2_ta_vld_offset : natural := is2_instr_offset + 32; +constant is2_ta_offset : natural := is2_ta_vld_offset + 1; +constant is2_s1_vld_offset : natural := is2_ta_offset + 6; +constant is2_s1_offset : natural := is2_s1_vld_offset + 1; +constant is2_s2_vld_offset : natural := is2_s1_offset + 6; +constant is2_s2_offset : natural := is2_s2_vld_offset + 1; +constant is2_s3_vld_offset : natural := is2_s2_offset + 6; +constant is2_s3_offset : natural := is2_s3_vld_offset + 1; +constant is2_is_barrier_offset : natural := is2_s3_offset + 6; +constant is2_is_slowspr_offset : natural := is2_is_barrier_offset + 1; +constant is2_pred_update_offset : natural := is2_is_slowspr_offset + 1; +constant is2_pred_taken_cnt_offset : natural := is2_pred_update_offset + 1; +constant is2_gshare_offset : natural := is2_pred_taken_cnt_offset + 2; +constant is2_hole_delay_offset : natural := is2_gshare_offset + 4; +constant is2_to_ucode_offset : natural := is2_hole_delay_offset +3; +constant is2_is_ucode_offset : natural := is2_to_ucode_offset + 1; +constant is2_ifar_offset : natural := is2_is_ucode_offset + 1; +constant is2_error_offset : natural := is2_ifar_offset + EFF_IFAR'length; +constant is2_axu_ld_or_st_offset : natural := is2_error_offset + 3; +constant is2_axu_store_offset : natural := is2_axu_ld_or_st_offset + 1; +constant is2_axu_ldst_indexed_offset : natural := is2_axu_store_offset + 1; +constant is2_axu_ldst_tag_offset : natural := is2_axu_ldst_indexed_offset + 1; +constant is2_axu_ldst_size_offset : natural := is2_axu_ldst_tag_offset + 9; +constant is2_axu_ldst_update_offset : natural := is2_axu_ldst_size_offset + 6; +constant is2_axu_ldst_extpid_offset : natural := is2_axu_ldst_update_offset + 1; +constant is2_axu_ldst_forcealign_offset : natural := is2_axu_ldst_extpid_offset + 1; +constant is2_axu_ldst_forceexcept_offset: natural := is2_axu_ldst_forcealign_offset + 1; +constant is2_axu_mftgpr_offset : natural := is2_axu_ldst_forceexcept_offset + 1; +constant is2_axu_mffgpr_offset : natural := is2_axu_mftgpr_offset + 1; +constant is2_axu_movedp_offset : natural := is2_axu_mffgpr_offset + 1; +constant is2_axu_instr_type_offset : natural := is2_axu_movedp_offset + 1; +constant is2_match_offset : natural := is2_axu_instr_type_offset + 3; +constant is2_2ucode_offset : natural := is2_match_offset + 1; +constant is2_2ucode_type_offset : natural := is2_2ucode_offset + 1; +constant sp_ex3_i_nobyp_vld_offset : natural := is2_2ucode_type_offset + 1; +constant sp_ex3_barrier_offset : natural := sp_ex3_i_nobyp_vld_offset + 1; +constant sp_ex4_i_nobyp_vld_offset : natural := sp_ex3_barrier_offset + 1; +constant sp_ex4_barrier_offset : natural := sp_ex4_i_nobyp_vld_offset + 1; +constant sp_ex5_i_nobyp_vld_offset : natural := sp_ex4_barrier_offset + 1; +constant sp_ex5_barrier_offset : natural := sp_ex5_i_nobyp_vld_offset + 1; +constant sp_is2_offset : natural := sp_ex5_barrier_offset + 1; +constant sp_rf0_offset : natural := sp_is2_offset +21; +constant sp_rf1_offset : natural := sp_rf0_offset +21; +constant sp_ex1_offset : natural := sp_rf1_offset +21; +constant sp_ex2_offset : natural := sp_ex1_offset +21; +constant sp_lm_offset : natural := sp_ex2_offset +21; +constant barrier_offset : natural := sp_lm_offset +7*lmq_entries; +constant xu_barrier_offset : natural := barrier_offset +1; +constant mult_hole_barrier_offset : natural := xu_barrier_offset +1; +constant single_instr_mode_offset : natural := mult_hole_barrier_offset +6; +constant quiesce_offset : natural := single_instr_mode_offset +1; +constant perf_event_offset : natural := quiesce_offset +1; +constant perf_early_offset : natural := perf_event_offset +12; +constant fdep_dbg_data_offset : natural := perf_early_offset +12; +constant an_ac_sync_ack_offset : natural := fdep_dbg_data_offset +22; +constant xu_iu_membar_tid_offset : natural := an_ac_sync_ack_offset +1; +constant xu_iu_multdiv_done_offset : natural := xu_iu_membar_tid_offset +1; +constant mm_iu_barrier_done_offset : natural := xu_iu_multdiv_done_offset +1; +constant spr_fdep_ll_hold_offset : natural := mm_iu_barrier_done_offset +1; +constant en_dcr_offset : natural := spr_fdep_ll_hold_offset +1; +constant spare_offset : natural := en_dcr_offset +1; +constant trace_bus_enable_offset : natural := spare_offset + 6; +constant event_bus_enable_offset : natural := trace_bus_enable_offset + 1; +constant scan_right : natural := event_bus_enable_offset + 1 - 1; +signal spare_l2 : std_ulogic_vector(0 to 5); +signal trace_bus_enable_d : std_ulogic; +signal trace_bus_enable_q : std_ulogic; +signal event_bus_enable_d : std_ulogic; +signal event_bus_enable_q : std_ulogic; +signal siv : std_ulogic_vector(0 to scan_right); +signal sov : std_ulogic_vector(0 to scan_right); +signal tiup : std_ulogic; +signal tidn : std_ulogic; +signal unused : std_ulogic_vector(0 to 4); +-- synopsys translate_off +-- synopsys translate_on +signal single_instr_mode_d : std_ulogic; +signal single_instr_mode_l2 : std_ulogic; +signal is2_vld_d : std_ulogic; +signal is2_instr_d : std_ulogic_vector(0 to 31); +signal is2_ta_vld_d : std_ulogic; +signal is2_ta_d : std_ulogic_vector(0 to 5); +signal is2_s1_vld_d : std_ulogic; +signal is2_s1_d : std_ulogic_vector(0 to 5); +signal is2_s2_vld_d : std_ulogic; +signal is2_s2_d : std_ulogic_vector(0 to 5); +signal is2_s3_vld_d : std_ulogic; +signal is2_s3_d : std_ulogic_vector(0 to 5); +signal is2_is_barrier_d : std_ulogic; +signal is2_is_slowspr_d : std_ulogic; +signal is2_pred_update_d : std_ulogic; +signal is2_pred_taken_cnt_d : std_ulogic_vector(0 to 1); +signal is2_gshare_d : std_ulogic_vector(0 to 3); +signal is2_hole_delay_d : std_ulogic_vector(0 to 2); +signal is2_to_ucode_d : std_ulogic; +signal is2_is_ucode_d : std_ulogic; +signal is2_ifar_d : EFF_IFAR; +signal is2_error_d : std_ulogic_vector(0 to 2); +signal is2_axu_ld_or_st_d : std_ulogic; +signal is2_axu_store_d : std_ulogic; +signal is2_axu_ldst_indexed_d : std_ulogic; +signal is2_axu_ldst_tag_d : std_ulogic_vector(0 to 8); +signal is2_axu_ldst_size_d : std_ulogic_vector(0 to 5); +signal is2_axu_ldst_update_d : std_ulogic; +signal is2_axu_ldst_extpid_d : std_ulogic; +signal is2_axu_ldst_forcealign_d : std_ulogic; +signal is2_axu_ldst_forceexcept_d : std_ulogic; +signal is2_axu_mftgpr_d : std_ulogic; +signal is2_axu_mffgpr_d : std_ulogic; +signal is2_axu_movedp_d : std_ulogic; +signal is2_axu_instr_type_d : std_ulogic_vector(0 to 2); +signal is2_match_d : std_ulogic; +signal is2_2ucode_d : std_ulogic; +signal is2_2ucode_type_d : std_ulogic; +signal is2_vld_L2 : std_ulogic; +signal is2_instr_L2 : std_ulogic_vector(0 to 31); +signal is2_ta_vld_L2 : std_ulogic; +signal is2_ta_L2 : std_ulogic_vector(0 to 5); +signal is2_s1_vld_L2 : std_ulogic; +signal is2_s1_L2 : std_ulogic_vector(0 to 5); +signal is2_s2_vld_L2 : std_ulogic; +signal is2_s2_L2 : std_ulogic_vector(0 to 5); +signal is2_s3_vld_L2 : std_ulogic; +signal is2_s3_L2 : std_ulogic_vector(0 to 5); +signal is2_is_barrier_L2 : std_ulogic; +signal is2_is_slowspr_L2 : std_ulogic; +signal is2_pred_update_L2 : std_ulogic; +signal is2_pred_taken_cnt_L2 : std_ulogic_vector(0 to 1); +signal is2_gshare_L2 : std_ulogic_vector(0 to 3); +signal is2_hole_delay_L2 : std_ulogic_vector(0 to 2); +signal is2_to_ucode_L2 : std_ulogic; +signal is2_is_ucode_L2 : std_ulogic; +signal is2_ifar_L2 : EFF_IFAR; +signal is2_error_L2 : std_ulogic_vector(0 to 2); +signal is2_axu_ld_or_st_L2 : std_ulogic; +signal is2_axu_store_L2 : std_ulogic; +signal is2_axu_ldst_indexed_L2 : std_ulogic; +signal is2_axu_ldst_tag_L2 : std_ulogic_vector(0 to 8); +signal is2_axu_ldst_size_L2 : std_ulogic_vector(0 to 5); +signal is2_axu_ldst_update_L2 : std_ulogic; +signal is2_axu_ldst_extpid_L2 : std_ulogic; +signal is2_axu_ldst_forcealign_L2 : std_ulogic; +signal is2_axu_ldst_forceexcept_L2 : std_ulogic; +signal is2_axu_mftgpr_L2 : std_ulogic; +signal is2_axu_mffgpr_L2 : std_ulogic; +signal is2_axu_movedp_L2 : std_ulogic; +signal is2_axu_instr_type_L2 : std_ulogic_vector(0 to 2); +signal is2_match_L2 : std_ulogic; +signal is2_2ucode_L2 : std_ulogic; +signal is2_2ucode_type_L2 : std_ulogic; +signal is1_instr_is_isync : std_ulogic; +signal is1_instr_is_sync : std_ulogic; +signal is1_instr_is_tlbsync : std_ulogic; +signal RAW_dep_hit : std_ulogic; +signal RAW_s1_hit_b : std_ulogic; +signal RAW_s2_hit_b : std_ulogic; +signal RAW_s3_hit_b : std_ulogic; +signal lr_dep_hit : std_ulogic; +signal cr_dep_hit : std_ulogic; +signal ctr_dep_hit : std_ulogic; +signal xer_dep_hit : std_ulogic; +signal msr_dep_hit : std_ulogic; +signal spr_dep_hit : std_ulogic; +signal br_sprs_dep_hit : std_ulogic; +signal WAW_LMQ_dep_hit : std_ulogic; +signal WAW_LMQ_dep_hit_b : std_ulogic; +signal single_instr_dep_hit : std_ulogic; +signal internal_is2_stall : std_ulogic; +signal dep_hit : std_ulogic; +signal dep_hit_no_stall : std_ulogic; +signal xu_dep_hit : std_ulogic; +signal is2_instr_is_barrier : std_ulogic; +signal act_nonvalid : std_ulogic; +signal sp_IS2_d : std_ulogic_vector(0 to 20); +signal sp_IS2_l2 : std_ulogic_vector(0 to 20); +signal sp_RF0_d : std_ulogic_vector(0 to 20); +signal sp_RF0_l2 : std_ulogic_vector(0 to 20); +signal sp_RF1_d : std_ulogic_vector(0 to 20); +signal sp_RF1_l2 : std_ulogic_vector(0 to 20); +signal sp_EX1_d : std_ulogic_vector(0 to 20); +signal sp_EX1_l2 : std_ulogic_vector(0 to 20); +signal sp_EX2_d : std_ulogic_vector(0 to 20); +signal sp_EX2_l2 : std_ulogic_vector(0 to 20); +signal sp_IS2_act : std_ulogic; +signal sp_RF0_act : std_ulogic; +signal sp_RF1_act : std_ulogic; +signal sp_EX1_act : std_ulogic; +signal sp_EX2_act : std_ulogic; +signal sp_EX3_act : std_ulogic; +signal sp_EX4_act : std_ulogic; +signal sp_EX5_act : std_ulogic; +signal sp_LM_d : std_ulogic_vector(0 to 7*lmq_entries-1); +signal sp_LM_l2 : std_ulogic_vector(0 to 7*lmq_entries-1); +signal lm_shadow_pipe_vld : std_ulogic_vector(0 to lmq_entries-1); +signal fdep_dbg_data_d : std_ulogic_vector(0 to 21); +signal fdep_dbg_data_l2 : std_ulogic_vector(0 to 21); +signal perf_event_d : std_ulogic_vector(0 to 11); +signal perf_event_l2 : std_ulogic_vector(0 to 11); +signal perf_early_d : std_ulogic_vector(0 to 11); +signal perf_early_l2 : std_ulogic_vector(0 to 11); +signal perf_dep_hit : std_ulogic; +signal perf_fdec_fdep_is1_vld : std_ulogic; +signal perf_internal_is2_stall : std_ulogic; +signal perf_i_afd_is1_instr_v : std_ulogic; +signal perf_au_iu_is1_dep_hit : std_ulogic; +signal perf_barrier_in_progress : std_ulogic; +signal perf_is2_is_slowspr_L2 : std_ulogic; +signal perf_RAW_dep_hit : std_ulogic; +signal perf_WAW_LMQ_dep_hit : std_ulogic; +signal perf_sync_dep_hit : std_ulogic; +signal perf_xu_dep_hit : std_ulogic; +signal perf_br_sprs_dep_hit : std_ulogic; +signal isMFSPR : std_ulogic; +signal isMTSPR : std_ulogic; +signal is1_is_slowspr : std_ulogic; +signal is1_is_barrier : std_ulogic; +signal an_ac_sync_ack_d : std_ulogic; +signal an_ac_sync_ack_l2 : std_ulogic; +signal xu_iu_membar_tid_d : std_ulogic; +signal xu_iu_membar_tid_l2 : std_ulogic; +signal xu_iu_multdiv_done_d : std_ulogic; +signal xu_iu_multdiv_done_l2 : std_ulogic; +signal mm_iu_barrier_done_d : std_ulogic; +signal mm_iu_barrier_done_l2 : std_ulogic; +signal spr_fdep_ll_hold_d : std_ulogic; +signal spr_fdep_ll_hold_l2 : std_ulogic; +signal is2_mult_hole_barrier : std_ulogic; +signal mult_hole_barrier_d : std_ulogic_vector(0 to 5); +signal mult_hole_barrier_l2 : std_ulogic_vector(0 to 5); +signal mult_hole_barrier_act : std_ulogic; +signal xu_barrier_d : std_ulogic; +signal xu_barrier_l2 : std_ulogic; +signal en_dcr_d : std_ulogic; +signal en_dcr_l2 : std_ulogic; +-------------------------------------------------------------------------------------------------------------------------------------------------------- +-- Shadow Pipe +-------------------------------------------------------------------------------------------------------------------------------------------------------- +type PIPE_STAGE is record + i_nobyp_vld : std_ulogic; + i_vld : std_ulogic; + ta_vld : std_ulogic; + ta : std_ulogic_vector(0 to 5); + UpdatesLR : std_ulogic; + UpdatesCR : std_ulogic; + UPdatesCTR : std_ulogic; + UpdatesXER : std_ulogic; + UpdatesMSR : std_ulogic; + UPdatesSPR : std_ulogic; + complete : std_ulogic_vector(0 to 4); + barrier : std_ulogic; +end record; +type SHADOW_PIPE_STAGES is (IS2, RF0, RF1, EX1, EX2); +type MACHINE is array (SHADOW_PIPE_STAGES'left to SHADOW_PIPE_STAGES'right) of PIPE_STAGE; +signal sp_d : MACHINE; +signal sp_L2 : MACHINE; +signal sp_barrier_clr : std_ulogic; +signal sp_EX3_i_nobyp_vld_d : std_ulogic; +signal sp_EX3_i_nobyp_vld_l2 : std_ulogic; +signal sp_EX3_barrier_d : std_ulogic; +signal sp_EX3_barrier_l2 : std_ulogic; +signal sp_EX4_i_nobyp_vld_d : std_ulogic; +signal sp_EX4_i_nobyp_vld_l2 : std_ulogic; +signal sp_EX4_barrier_d : std_ulogic; +signal sp_EX4_barrier_l2 : std_ulogic; +signal sp_EX5_i_nobyp_vld_d : std_ulogic; +signal sp_EX5_i_nobyp_vld_l2 : std_ulogic; +signal sp_EX5_barrier_d : std_ulogic; +signal sp_EX5_barrier_l2 : std_ulogic; +type PIPE_STAGE_LM is record + ta_vld : std_ulogic; + ta : std_ulogic_vector(0 to 5); +end record; +type MACHINE_LM is array (0 to lmq_entries-1) of PIPE_STAGE_LM; +signal sp_d_LM : MACHINE_LM; +signal sp_L2_LM : MACHINE_LM; +signal loadmiss_qentry : std_ulogic_vector(0 to lmq_entries-1); +signal loadmiss_target : std_ulogic_vector(0 to 5); +signal loadmiss_complete : std_ulogic_vector(0 to lmq_entries-1); +-------------------------------------------------------------------------------------------------------------------------------------------------------- +-- ISYNC +-------------------------------------------------------------------------------------------------------------------------------------------------------- +signal shadow_pipe_vld : std_ulogic; +signal sync_dep_hit : std_ulogic; +-------------------------------------------------------------------------------------------------------------------------------------------------------- +-- barrier +-------------------------------------------------------------------------------------------------------------------------------------------------------- +signal set_barrier : std_ulogic; +signal clr_barrier : std_ulogic; +signal barrier_d : std_ulogic; +signal barrier_L2 : std_ulogic; +signal barrier_in_progress : std_ulogic; +signal quiesce_barrier : std_ulogic; +-------------------------------------------------------------------------------------------------------------------------------------------------------- +-- General Use +-------------------------------------------------------------------------------------------------------------------------------------------------------- +subtype s2 is std_ulogic_vector(0 to 1); +subtype s15 is std_ulogic_vector(0 to 14); +signal quiesce_d : std_ulogic; +signal quiesce_l2 : std_ulogic; +signal core64 : std_ulogic; +--mapping +signal is1_force_ram_b : std_ulogic; +signal is1_valid : std_ulogic; +signal is1_dep : std_ulogic; +signal is1_dep0_b : std_ulogic; +signal is1_dep1_b : std_ulogic; +signal is1_stall_b : std_ulogic; +signal is2_stall_b : std_ulogic; +signal fxu_dep0_b : std_ulogic; +signal fxu_dep1_b : std_ulogic; +signal fxu_dep_hit : std_ulogic; +signal fxu_dep_hit_b : std_ulogic; +signal is2_vld_b : std_ulogic; +signal fxu_iss_stall : std_ulogic; +signal is2_iss_stall_b : std_ulogic; + BEGIN + +tiup <= '1'; +tidn <= '0'; +--64-bit mode +c64: if (regmode = 6) generate +begin +core64 <= '1'; +end generate; +--32-bit core +c32: if (regmode = 5) generate +begin +core64 <= '0'; +end generate; +en_dcr_d <= xu_iu_spr_ccr2_en_dcr; +-------------------------------------------------------------------------------------------------------------------------------------------------------- +-- Mmmmmmm IS1 Decode +-------------------------------------------------------------------------------------------------------------------------------------------------------- +is1_instr_is_ISYNC <= (fdec_fdep_is1_instr(0 to 5) = "010011") and (fdec_fdep_is1_instr(21 to 30) = "0010010110"); +is1_instr_is_SYNC <= (fdec_fdep_is1_instr(0 to 5) = "011111") and (fdec_fdep_is1_instr(21 to 30) = "1001010110"); +is1_instr_is_TLBSYNC <= (fdec_fdep_is1_instr(0 to 5) = "011111") and (fdec_fdep_is1_instr(21 to 30) = "1000110110"); +-------------------------------------------------------------------------------------------------------------------------------------------------------- +-- RAW hazard dependency tree. GPR, and VRF +-------------------------------------------------------------------------------------------------------------------------------------------------------- + +raw_s1_cmp: entity work.iuq_fxu_dep_cmp(iuq_fxu_dep_cmp) +port map ( + is1_v => fdec_fdep_is1_s1_vld, + + is2_v => sp_L2(IS2).ta_vld, + rf0_v => sp_L2(RF0).ta_vld, + rf1_v => sp_L2(RF1).ta_vld, + ex1_v => sp_L2(EX1).ta_vld, + ex2_v => sp_L2(EX2).ta_vld, + lm0_v => sp_L2_LM(0).ta_vld, + lm1_v => sp_L2_LM(1).ta_vld, + lm2_v => sp_L2_LM(2).ta_vld, + lm3_v => sp_L2_LM(3).ta_vld, + lm4_v => sp_L2_LM(4).ta_vld, + lm5_v => sp_L2_LM(5).ta_vld, + lm6_v => sp_L2_LM(6).ta_vld, + lm7_v => sp_L2_LM(7).ta_vld, + + is1_ad => fdec_fdep_is1_s1, + + is2_ad => sp_L2(IS2).ta, + rf0_ad => sp_L2(RF0).ta, + rf1_ad => sp_L2(RF1).ta, + ex1_ad => sp_L2(EX1).ta, + ex2_ad => sp_L2(EX2).ta, + lm0_ad => sp_L2_LM(0).ta, + lm1_ad => sp_L2_LM(1).ta, + lm2_ad => sp_L2_LM(2).ta, + lm3_ad => sp_L2_LM(3).ta, + lm4_ad => sp_L2_LM(4).ta, + lm5_ad => sp_L2_LM(5).ta, + lm6_ad => sp_L2_LM(6).ta, + lm7_ad => sp_L2_LM(7).ta, + + ad_hit_b => RAW_s1_hit_b +); + + +raw_s2_cmp: entity work.iuq_fxu_dep_cmp(iuq_fxu_dep_cmp) +port map ( + is1_v => fdec_fdep_is1_s2_vld, + + is2_v => sp_L2(IS2).ta_vld, + rf0_v => sp_L2(RF0).ta_vld, + rf1_v => sp_L2(RF1).ta_vld, + ex1_v => sp_L2(EX1).ta_vld, + ex2_v => sp_L2(EX2).ta_vld, + lm0_v => sp_L2_LM(0).ta_vld, + lm1_v => sp_L2_LM(1).ta_vld, + lm2_v => sp_L2_LM(2).ta_vld, + lm3_v => sp_L2_LM(3).ta_vld, + lm4_v => sp_L2_LM(4).ta_vld, + lm5_v => sp_L2_LM(5).ta_vld, + lm6_v => sp_L2_LM(6).ta_vld, + lm7_v => sp_L2_LM(7).ta_vld, + + is1_ad => fdec_fdep_is1_s2, + + is2_ad => sp_L2(IS2).ta, + rf0_ad => sp_L2(RF0).ta, + rf1_ad => sp_L2(RF1).ta, + ex1_ad => sp_L2(EX1).ta, + ex2_ad => sp_L2(EX2).ta, + lm0_ad => sp_L2_LM(0).ta, + lm1_ad => sp_L2_LM(1).ta, + lm2_ad => sp_L2_LM(2).ta, + lm3_ad => sp_L2_LM(3).ta, + lm4_ad => sp_L2_LM(4).ta, + lm5_ad => sp_L2_LM(5).ta, + lm6_ad => sp_L2_LM(6).ta, + lm7_ad => sp_L2_LM(7).ta, + + ad_hit_b => RAW_s2_hit_b +); + + +raw_s3_cmp: entity work.iuq_fxu_dep_cmp(iuq_fxu_dep_cmp) +port map ( + is1_v => fdec_fdep_is1_s3_vld, + + is2_v => sp_L2(IS2).ta_vld, + rf0_v => sp_L2(RF0).ta_vld, + rf1_v => sp_L2(RF1).ta_vld, + ex1_v => sp_L2(EX1).ta_vld, + ex2_v => sp_L2(EX2).ta_vld, + lm0_v => sp_L2_LM(0).ta_vld, + lm1_v => sp_L2_LM(1).ta_vld, + lm2_v => sp_L2_LM(2).ta_vld, + lm3_v => sp_L2_LM(3).ta_vld, + lm4_v => sp_L2_LM(4).ta_vld, + lm5_v => sp_L2_LM(5).ta_vld, + lm6_v => sp_L2_LM(6).ta_vld, + lm7_v => sp_L2_LM(7).ta_vld, + + is1_ad => fdec_fdep_is1_s3, + + is2_ad => sp_L2(IS2).ta, + rf0_ad => sp_L2(RF0).ta, + rf1_ad => sp_L2(RF1).ta, + ex1_ad => sp_L2(EX1).ta, + ex2_ad => sp_L2(EX2).ta, + lm0_ad => sp_L2_LM(0).ta, + lm1_ad => sp_L2_LM(1).ta, + lm2_ad => sp_L2_LM(2).ta, + lm3_ad => sp_L2_LM(3).ta, + lm4_ad => sp_L2_LM(4).ta, + lm5_ad => sp_L2_LM(5).ta, + lm6_ad => sp_L2_LM(6).ta, + lm7_ad => sp_L2_LM(7).ta, + + ad_hit_b => RAW_s3_hit_b +); +raw_dep_nand3: RAW_dep_hit <= not(RAW_s1_hit_b and RAW_s2_hit_b and RAW_s3_hit_b); +-------------------------------------------------------------------------------------------------------------------------------------------------------- +-- Dependency tree for branch related setters and users +-------------------------------------------------------------------------------------------------------------------------------------------------------- +lr_dep_hit <= (sp_L2(IS2).i_vld and fdec_fdep_is1_UsesLR and sp_L2(IS2).UpdatesLR) or + (sp_L2(RF0).i_vld and fdec_fdep_is1_UsesLR and sp_L2(RF0).UpdatesLR) or + (sp_L2(RF1).i_vld and fdec_fdep_is1_UsesLR and sp_L2(RF1).UpdatesLR) or + (sp_L2(EX1).i_vld and fdec_fdep_is1_UsesLR and sp_L2(EX1).UpdatesLR) or + (sp_L2(EX2).i_vld and fdec_fdep_is1_UsesLR and sp_L2(EX2).UpdatesLR); +cr_dep_hit <= (sp_L2(IS2).i_vld and fdec_fdep_is1_UsesCR and sp_L2(IS2).UpdatesCR) or + (sp_L2(RF0).i_vld and fdec_fdep_is1_UsesCR and sp_L2(RF0).UpdatesCR) or + (sp_L2(RF1).i_vld and fdec_fdep_is1_UsesCR and sp_L2(RF1).UpdatesCR) or + (sp_L2(EX1).i_vld and fdec_fdep_is1_UsesCR and sp_L2(EX1).UpdatesCR) or + (sp_L2(EX2).i_vld and fdec_fdep_is1_UsesCR and sp_L2(EX2).UpdatesCR); +ctr_dep_hit <= (sp_L2(IS2).i_vld and fdec_fdep_is1_UsesCTR and sp_L2(IS2).UpdatesCTR) or + (sp_L2(RF0).i_vld and fdec_fdep_is1_UsesCTR and sp_L2(RF0).UpdatesCTR) or + (sp_L2(RF1).i_vld and fdec_fdep_is1_UsesCTR and sp_L2(RF1).UpdatesCTR) or + (sp_L2(EX1).i_vld and fdec_fdep_is1_UsesCTR and sp_L2(EX1).UpdatesCTR) or + (sp_L2(EX2).i_vld and fdec_fdep_is1_UsesCTR and sp_L2(EX2).UpdatesCTR); +xer_dep_hit <= (sp_L2(IS2).i_vld and fdec_fdep_is1_UsesXER and sp_L2(IS2).UpdatesXER) or + (sp_L2(RF0).i_vld and fdec_fdep_is1_UsesXER and sp_L2(RF0).UpdatesXER) or + (sp_L2(RF1).i_vld and fdec_fdep_is1_UsesXER and sp_L2(RF1).UpdatesXER) or + (sp_L2(EX1).i_vld and fdec_fdep_is1_UsesXER and sp_L2(EX1).UpdatesXER) or + (sp_L2(EX2).i_vld and fdec_fdep_is1_UsesXER and sp_L2(EX2).UpdatesXER); +msr_dep_hit <= (sp_L2(IS2).i_vld and fdec_fdep_is1_UsesMSR and sp_L2(IS2).UpdatesMSR) or + (sp_L2(RF0).i_vld and fdec_fdep_is1_UsesMSR and sp_L2(RF0).UpdatesMSR) or + (sp_L2(RF1).i_vld and fdec_fdep_is1_UsesMSR and sp_L2(RF1).UpdatesMSR) or + (sp_L2(EX1).i_vld and fdec_fdep_is1_UsesMSR and sp_L2(EX1).UpdatesMSR) or + (sp_L2(EX2).i_vld and fdec_fdep_is1_UsesMSR and sp_L2(EX2).UpdatesMSR); +spr_dep_hit <= (sp_L2(IS2).i_vld and fdec_fdep_is1_UsesSPR and sp_L2(IS2).UpdatesSPR) or + (sp_L2(RF0).i_vld and fdec_fdep_is1_UsesSPR and sp_L2(RF0).UpdatesSPR) or + (sp_L2(RF1).i_vld and fdec_fdep_is1_UsesSPR and sp_L2(RF1).UpdatesSPR) or + (sp_L2(EX1).i_vld and fdec_fdep_is1_UsesSPR and sp_L2(EX1).UpdatesSPR) or + (sp_L2(EX2).i_vld and fdec_fdep_is1_UsesSPR and sp_L2(EX2).UpdatesSPR); +br_sprs_dep_hit <= lr_dep_hit or cr_dep_hit or ctr_dep_hit or xer_dep_hit or msr_dep_hit or spr_dep_hit; +-------------------------------------------------------------------------------------------------------------------------------------------------------- +-- WAW hazard dependency tree for load miss targets against instructions that could be issued under the load miss +-------------------------------------------------------------------------------------------------------------------------------------------------------- + + +waw_cmp: entity work.iuq_fxu_dep_cmp(iuq_fxu_dep_cmp) +port map ( + is1_v => fdec_fdep_is1_ld_vld, + + is2_v => tidn, + rf0_v => tidn, + rf1_v => tidn, + ex1_v => tidn, + ex2_v => tidn, + lm0_v => sp_L2_LM(0).ta_vld, + lm1_v => sp_L2_LM(1).ta_vld, + lm2_v => sp_L2_LM(2).ta_vld, + lm3_v => sp_L2_LM(3).ta_vld, + lm4_v => sp_L2_LM(4).ta_vld, + lm5_v => sp_L2_LM(5).ta_vld, + lm6_v => sp_L2_LM(6).ta_vld, + lm7_v => sp_L2_LM(7).ta_vld, + + is1_ad => fdec_fdep_is1_ta, + + is2_ad => sp_L2(IS2).ta, + rf0_ad => sp_L2(RF0).ta, + rf1_ad => sp_L2(RF1).ta, + ex1_ad => sp_L2(EX1).ta, + ex2_ad => sp_L2(EX2).ta, + lm0_ad => sp_L2_LM(0).ta, + lm1_ad => sp_L2_LM(1).ta, + lm2_ad => sp_L2_LM(2).ta, + lm3_ad => sp_L2_LM(3).ta, + lm4_ad => sp_L2_LM(4).ta, + lm5_ad => sp_L2_LM(5).ta, + lm6_ad => sp_L2_LM(6).ta, + lm7_ad => sp_L2_LM(7).ta, + + ad_hit_b => WAW_LMQ_dep_hit_b +); +WAW_LMQ_dep_hit <= not WAW_LMQ_dep_hit_b; +-------------------------------------------------------------------------------------------------------------------------------------------------------- +-- single instruction outstanding mode OR run control. these two modes should not be used in concert +-------------------------------------------------------------------------------------------------------------------------------------------------------- +single_instr_mode_d <= xu_iu_single_instr_mode; +single_instr_dep_hit <= ((shadow_pipe_vld or au_iu_is2_axubusy) and single_instr_mode_l2); +-------------------------------------------------------------------------------------------------------------------------------------------------------- +-- dep_hit calculation +-------------------------------------------------------------------------------------------------------------------------------------------------------- +dep_hit <= (not fdec_fdep_is1_force_ram and (RAW_dep_hit or WAW_LMQ_dep_hit or sync_dep_hit or single_instr_dep_hit or br_sprs_dep_hit or barrier_in_progress)) or au_iu_is1_dep_hit or internal_is2_stall; +dep_hit_no_stall <= (not fdec_fdep_is1_force_ram and (RAW_dep_hit or WAW_LMQ_dep_hit or sync_dep_hit or single_instr_dep_hit or br_sprs_dep_hit or barrier_in_progress)) or au_iu_is1_dep_hit; +-------------------------------------------------------------------------------------------------------------------------------------------------------- +-- derivation of internal_is1_stall and dp_ib_instr_stall +-------------------------------------------------------------------------------------------------------------------------------------------------------- +--mapping +is1_force_ram_b <= not fdec_fdep_is1_force_ram; +--is1 stall +is1_valid <= fdec_fdep_is1_vld or i_afd_is1_instr_v; +is1_dep0_nor2: is1_dep0_b <= not (RAW_dep_hit or br_sprs_dep_hit); +is1_dep1_nor3: is1_dep1_b <= not (sync_dep_hit or single_instr_dep_hit or barrier_in_progress); +is1_dep_nand3: is1_dep <= not (WAW_LMQ_dep_hit_b and is1_dep0_b and is1_dep1_b); +is1_stall_nand2: is1_stall_b <= not (is1_dep and fdec_fdep_is1_vld and is1_force_ram_b); +is2_stall_nand2: is2_stall_b <= not (internal_is2_stall and is1_valid); +fxu_stall_nand3: iu_au_is1_stall <= not (au_iu_is1_dep_hit_b and is1_stall_b and is2_stall_b); +--buffer stall +buf_stall_nand3: fdep_fdec_buff_stall <= not (au_iu_is1_dep_hit_b and is1_stall_b and is2_stall_b); +--fxu dep hit +fxu_dep0_nor2: fxu_dep0_b <= not (RAW_dep_hit or br_sprs_dep_hit); +fxu_dep1_nor3: fxu_dep1_b <= not (sync_dep_hit or single_instr_dep_hit or barrier_in_progress); +fxu_dep_nand3: fxu_dep_hit <= not (WAW_LMQ_dep_hit_b and fxu_dep0_b and fxu_dep1_b); +fxu_dep_nand2: fxu_dep_hit_b <= not (fxu_dep_hit and is1_force_ram_b); +xu_dep_hit <= not fxu_dep_hit_b; +--weak stall for clock gating +fdep_fdec_weak_stall <= (sync_dep_hit or single_instr_dep_hit or barrier_in_progress) and fdec_fdep_is1_vld and is1_force_ram_b; +-------------------------------------------------------------------------------------------------------------------------------------------------------- +-- Dependency shadow pipeline +-------------------------------------------------------------------------------------------------------------------------------------------------------- +loadmiss_qentry <= gate_and(not xu_iu_ex5_flush and xu_iu_loadmiss_vld and xu_iu_loadmiss_target_type, xu_iu_loadmiss_qentry); +loadmiss_target <= gate_and(not xu_iu_ex5_flush and xu_iu_loadmiss_vld and xu_iu_loadmiss_target_type, xu_iu_loadmiss_target); +loadmiss_complete <= gate_and( xu_iu_complete_vld and xu_iu_complete_target_type, xu_iu_complete_qentry); +shadow_pipe_vld <= sp_L2(IS2).i_nobyp_vld or + sp_L2(RF0).i_nobyp_vld or + sp_L2(RF1).i_nobyp_vld or + sp_L2(EX1).i_nobyp_vld or + sp_L2(EX2).i_nobyp_vld or + sp_EX3_i_nobyp_vld_L2 or + sp_EX4_i_nobyp_vld_L2 or + sp_EX5_i_nobyp_vld_L2 or + or_reduce(lm_shadow_pipe_vld); +lm_shadow_pipe_vld_g: for i in 0 to lmq_entries-1 generate +lm_shadow_pipe_vld(i) <= sp_L2_LM(i).ta_vld; +end generate; + + + +sp_d_proc : process( +xu_iu_is2_flush, +xu_iu_rf0_flush, +xu_iu_rf1_flush, +xu_iu_ex1_flush, +xu_iu_ex2_flush, +xu_iu_ex3_flush, +xu_iu_ex4_flush, +internal_is2_stall, +sp_L2(IS2).i_nobyp_vld, sp_L2(IS2).i_vld, sp_L2(IS2).ta_vld, +sp_L2(IS2).ta, sp_L2(IS2).UpdatesLR, sp_L2(IS2).UpdatesCR, sp_L2(IS2).UPdatesCTR, +sp_L2(IS2).UpdatesXER, sp_L2(IS2).UpdatesMSR, sp_L2(IS2).UPdatesSPR, sp_L2(IS2).complete, sp_L2(IS2).barrier, +sp_L2(RF0).i_nobyp_vld, sp_L2(RF0).i_vld, sp_L2(RF0).ta_vld, +sp_L2(RF0).ta, sp_L2(RF0).UpdatesLR, sp_L2(RF0).UpdatesCR, sp_L2(RF0).UPdatesCTR, +sp_L2(RF0).UpdatesXER, sp_L2(RF0).UpdatesMSR, sp_L2(RF0).UPdatesSPR, sp_L2(RF0).complete, sp_L2(RF0).barrier, +sp_L2(RF1).i_nobyp_vld, sp_L2(RF1).i_vld, sp_L2(RF1).ta_vld, +sp_L2(RF1).ta, sp_L2(RF1).UpdatesLR, sp_L2(RF1).UpdatesCR, sp_L2(RF1).UPdatesCTR, +sp_L2(RF1).UpdatesXER, sp_L2(RF1).UpdatesMSR, sp_L2(RF1).UPdatesSPR, sp_L2(RF1).complete, sp_L2(RF1).barrier, +sp_L2(EX1).i_nobyp_vld, sp_L2(EX1).i_vld, sp_L2(EX1).ta_vld, +sp_L2(EX1).ta, sp_L2(EX1).UpdatesLR, sp_L2(EX1).UpdatesCR, sp_L2(EX1).UPdatesCTR, +sp_L2(EX1).UpdatesXER, sp_L2(EX1).UpdatesMSR, sp_L2(EX1).UPdatesSPR, sp_L2(EX1).complete, sp_L2(EX1).barrier, + +sp_L2(EX2).i_nobyp_vld, sp_L2(EX2).barrier, + +sp_EX3_i_nobyp_vld_l2, +sp_EX4_i_nobyp_vld_l2, +sp_EX3_barrier_l2, +sp_EX4_barrier_l2, +sp_LM_l2, + +fdec_fdep_is1_vld, +fdec_fdep_is1_ta_vld, + +fdec_fdep_is1_ta, +fdec_fdep_is1_UpdatesLR, +fdec_fdep_is1_UpdatesCR, +fdec_fdep_is1_UpdatesCTR, +fdec_fdep_is1_UpdatesXER, +fdec_fdep_is1_UpdatesMSR, +fdec_fdep_is1_UpdatesSPR, +fdec_fdep_is1_complete, +xu_iu_is1_flush, +loadmiss_qentry, +loadmiss_target, +loadmiss_complete, +is2_instr_is_barrier, +dep_hit_no_stall +) begin + + + +sp_d(IS2).i_nobyp_vld <= fdec_fdep_is1_vld and not dep_hit_no_stall; +sp_d(IS2).i_vld <= fdec_fdep_is1_vld and not dep_hit_no_stall and not fdec_fdep_is1_complete(0); +sp_d(IS2).ta_vld <= fdec_fdep_is1_vld and fdec_fdep_is1_ta_vld and not dep_hit_no_stall and not fdec_fdep_is1_complete(0); +sp_d(IS2).ta <= fdec_fdep_is1_ta; +sp_d(IS2).UpdatesLR <= fdec_fdep_is1_UpdatesLR; +sp_d(IS2).UpdatesCR <= fdec_fdep_is1_UpdatesCR; +sp_d(IS2).UpdatesCTR <= fdec_fdep_is1_UpdatesCTR; +sp_d(IS2).UpdatesXER <= fdec_fdep_is1_UpdatesXER; +sp_d(IS2).UpdatesMSR <= fdec_fdep_is1_UpdatesMSR; +sp_d(IS2).UpdatesSPR <= fdec_fdep_is1_UpdatesSPR; +sp_d(IS2).complete <= fdec_fdep_is1_complete; +sp_d(IS2).barrier <= '0'; +if ib(internal_is2_stall) then +sp_d(IS2) <= sp_L2(IS2); +end if; +if ib(xu_iu_is1_flush) then +sp_d(IS2).i_nobyp_vld <= '0'; +sp_d(IS2).i_vld <= '0'; +sp_d(IS2).ta_vld <= '0'; +end if; +sp_d(RF0) <= sp_L2(IS2); +sp_d(RF0).i_vld <=sp_L2(IS2).i_vld and not sp_L2(IS2).complete(1); +sp_d(RF0).ta_vld <=sp_L2(IS2).ta_vld and not sp_L2(IS2).complete(1); +sp_d(RF0).barrier <=is2_instr_is_barrier; +if ib(xu_iu_is2_flush) or ib(internal_is2_stall) then +sp_d(RF0).ta_vld <= '0'; +sp_d(RF0).i_nobyp_vld <= '0'; +sp_d(RF0).i_vld <= '0'; +sp_d(RF0).barrier <= '0'; +end if; +sp_d(RF1) <= sp_L2(RF0); +sp_d(RF1).i_vld <=sp_L2(RF0).i_vld and not sp_L2(RF0).complete(2); +sp_d(RF1).ta_vld <=sp_L2(RF0).ta_vld and not sp_L2(RF0).complete(2); +if ib(xu_iu_rf0_flush) then +sp_d(RF1).ta_vld <= '0'; +sp_d(RF1).i_nobyp_vld <= '0'; +sp_d(RF1).i_vld <= '0'; +sp_d(RF1).barrier <= '0'; +end if; +sp_d(EX1) <= sp_L2(RF1); +sp_d(EX1).i_vld <=sp_L2(RF1).i_vld and not sp_L2(RF1).complete(3); +sp_d(EX1).ta_vld <=sp_L2(RF1).ta_vld and not sp_L2(RF1).complete(3); +if ib(xu_iu_rf1_flush) then +sp_d(EX1).ta_vld <= '0'; +sp_d(EX1).i_nobyp_vld <= '0'; +sp_d(EX1).i_vld <= '0'; +sp_d(EX1).barrier <= '0'; +end if; +sp_d(EX2) <= sp_L2(EX1); +sp_d(EX2).i_vld <=sp_L2(EX1).i_vld and not sp_L2(EX1).complete(4); +sp_d(EX2).ta_vld <=sp_L2(EX1).ta_vld and not sp_L2(EX1).complete(4); +if ib(xu_iu_ex1_flush) then +sp_d(EX2).ta_vld <= '0'; +sp_d(EX2).i_nobyp_vld <= '0'; +sp_d(EX2).i_vld <= '0'; +sp_d(EX2).barrier <= '0'; +end if; +sp_EX3_i_nobyp_vld_d <= sp_L2(EX2).i_nobyp_vld; +sp_EX3_barrier_d <= sp_L2(EX2).barrier; +if ib(xu_iu_ex2_flush) then +sp_EX3_i_nobyp_vld_d <= '0'; +sp_EX3_barrier_d <= '0'; +end if; +sp_EX4_i_nobyp_vld_d <= sp_EX3_i_nobyp_vld_l2; +sp_EX4_barrier_d <= sp_EX3_barrier_l2; +if ib(xu_iu_ex3_flush) then +sp_EX4_i_nobyp_vld_d <= '0'; +sp_EX4_barrier_d <= '0'; +end if; +sp_EX5_i_nobyp_vld_d <= sp_EX4_i_nobyp_vld_l2; +sp_EX5_barrier_d <= sp_EX4_barrier_l2; +if ib(xu_iu_ex4_flush) then +sp_EX5_i_nobyp_vld_d <= '0'; +sp_EX5_barrier_d <= '0'; +end if; +lm_loop: for i in 0 to lmq_entries-1 loop +sp_d_LM(i).ta_vld <= sp_LM_l2(0+7*i); +sp_d_LM(i).ta <= sp_LM_l2(1+7*i to 6+7*i); +if ib(loadmiss_qentry(i)) then +sp_d_LM(i).ta_vld <='1'; +sp_d_LM(i).ta <= loadmiss_target; +elsif ib(loadmiss_complete(i)) then +sp_d_LM(i).ta_vld <= '0'; +end if; +end loop; + + +end process sp_d_proc; +--tie off unused SP signals +unused(0 TO 4) <= sp_L2(EX2).complete(0 to 4); + +is2_instr_proc : process ( +fdec_fdep_is1_vld, + +fdec_fdep_is1_instr, +fdec_fdep_is1_ta_vld, +fdec_fdep_is1_ta, +fdec_fdep_is1_s1_vld, +fdec_fdep_is1_s1, +fdec_fdep_is1_s2_vld, +fdec_fdep_is1_s2, +fdec_fdep_is1_s3_vld, +fdec_fdep_is1_s3, +fdec_fdep_is1_pred_update, +fdec_fdep_is1_pred_taken_cnt, +fdec_fdep_is1_gshare, + +fdec_fdep_is1_hole_delay, + +fdec_fdep_is1_to_ucode, +fdec_fdep_is1_is_ucode, +fdec_fdep_is1_ifar, +fdec_fdep_is1_error, +is1_is_barrier, +is1_is_slowspr, +is2_vld_l2, +is2_instr_l2, +is2_ta_vld_l2, +is2_ta_l2, +is2_s1_vld_l2, +is2_s1_l2, +is2_s2_vld_l2, +is2_s2_l2, +is2_s3_vld_l2, +is2_s3_l2, +is2_is_barrier_l2, +is2_is_slowspr_l2, +is2_pred_update_l2, +is2_pred_taken_cnt_l2, +is2_gshare_l2, + +is2_hole_delay_l2, + +is2_to_ucode_l2, +is2_is_ucode_l2, +is2_error_l2, +is2_ifar_l2, +is2_axu_ld_or_st_l2, +is2_axu_store_l2, +is2_axu_ldst_indexed_l2, +is2_axu_ldst_tag_l2, +is2_axu_ldst_size_l2, +is2_axu_ldst_update_l2, +is2_axu_ldst_extpid_l2, +is2_axu_ldst_forcealign_l2, +is2_axu_ldst_forceexcept_l2, +is2_axu_mftgpr_l2, +is2_axu_mffgpr_l2, +is2_axu_movedp_l2, +is2_axu_instr_type_l2, +is2_match_l2, +is2_2ucode_l2, +is2_2ucode_type_l2, +dep_hit_no_stall, +xu_iu_is1_flush, +internal_is2_stall, +fdec_fdep_is1_axu_ld_or_st, +fdec_fdep_is1_axu_store, +fdec_fdep_is1_axu_ldst_indexed, +fdec_fdep_is1_axu_ldst_tag, +fdec_fdep_is1_axu_ldst_size, +fdec_fdep_is1_axu_ldst_update, +fdec_fdep_is1_axu_ldst_extpid, +fdec_fdep_is1_axu_ldst_forcealign, +fdec_fdep_is1_axu_ldst_forceexcept, +fdec_fdep_is1_axu_mftgpr, +fdec_fdep_is1_axu_mffgpr, +fdec_fdep_is1_axu_movedp, +fdec_fdep_is1_axu_instr_type, +fdec_fdep_is1_match, +fdec_fdep_is1_2ucode, +fdec_fdep_is1_2ucode_type +) begin + + is2_vld_d <= fdec_fdep_is1_vld and not dep_hit_no_stall; +is2_instr_d <= fdec_fdep_is1_instr; +is2_ta_vld_d <= fdec_fdep_is1_ta_vld; +is2_ta_d <= fdec_fdep_is1_ta; +is2_s1_vld_d <= fdec_fdep_is1_s1_vld; +is2_s1_d <= fdec_fdep_is1_s1; +is2_s2_vld_d <= fdec_fdep_is1_s2_vld; +is2_s2_d <= fdec_fdep_is1_s2; +is2_s3_vld_d <= fdec_fdep_is1_s3_vld; +is2_s3_d <= fdec_fdep_is1_s3; +is2_is_barrier_d <= is1_is_barrier; +is2_is_slowspr_d <= is1_is_slowspr; +is2_pred_update_d <= fdec_fdep_is1_pred_update; +is2_pred_taken_cnt_d <= fdec_fdep_is1_pred_taken_cnt; +is2_gshare_d <= fdec_fdep_is1_gshare; +is2_hole_delay_d <= fdec_fdep_is1_hole_delay; +is2_to_ucode_d <= fdec_fdep_is1_to_ucode; +is2_is_ucode_d <= fdec_fdep_is1_is_ucode; +is2_ifar_d <= fdec_fdep_is1_ifar; +is2_error_d <= fdec_fdep_is1_error; +is2_axu_ld_or_st_d <= fdec_fdep_is1_axu_ld_or_st; +is2_axu_store_d <= fdec_fdep_is1_axu_store; +is2_axu_ldst_indexed_d <= fdec_fdep_is1_axu_ldst_indexed; +is2_axu_ldst_tag_d <= fdec_fdep_is1_axu_ldst_tag; +is2_axu_ldst_size_d <= fdec_fdep_is1_axu_ldst_size; +is2_axu_ldst_update_d <= fdec_fdep_is1_axu_ldst_update; +is2_axu_ldst_extpid_d <= fdec_fdep_is1_axu_ldst_extpid; +is2_axu_ldst_forcealign_d <= fdec_fdep_is1_axu_ldst_forcealign; +is2_axu_ldst_forceexcept_d <= fdec_fdep_is1_axu_ldst_forceexcept; +is2_axu_mftgpr_d <= fdec_fdep_is1_axu_mftgpr; +is2_axu_mffgpr_d <= fdec_fdep_is1_axu_mffgpr; +is2_axu_movedp_d <= fdec_fdep_is1_axu_movedp; +is2_axu_instr_type_d <= fdec_fdep_is1_axu_instr_type; +is2_match_d <= fdec_fdep_is1_match; +is2_2ucode_d <= fdec_fdep_is1_2ucode; +is2_2ucode_type_d <= fdec_fdep_is1_2ucode_type; +if (internal_is2_stall = '1') then +is2_vld_d <= is2_vld_l2; +is2_instr_d <= is2_instr_l2; +is2_ta_vld_d <= is2_ta_vld_l2; +is2_ta_d <= is2_ta_l2; +is2_s1_vld_d <= is2_s1_vld_l2; +is2_s1_d <= is2_s1_l2; +is2_s2_vld_d <= is2_s2_vld_l2; +is2_s2_d <= is2_s2_l2; +is2_s3_vld_d <= is2_s3_vld_l2; +is2_s3_d <= is2_s3_l2; +is2_is_barrier_d <= is2_is_barrier_l2; +is2_is_slowspr_d <= is2_is_slowspr_l2; +is2_pred_update_d <= is2_pred_update_l2; +is2_pred_taken_cnt_d <= is2_pred_taken_cnt_l2; +is2_gshare_d <= is2_gshare_l2; +is2_hole_delay_d <= is2_hole_delay_l2; +is2_to_ucode_d <= is2_to_ucode_l2; +is2_is_ucode_d <= is2_is_ucode_l2; +is2_ifar_d <= is2_ifar_l2; +is2_error_d <= is2_error_l2; +is2_axu_ld_or_st_d <= is2_axu_ld_or_st_l2; +is2_axu_store_d <= is2_axu_store_l2; +is2_axu_ldst_indexed_d <= is2_axu_ldst_indexed_l2; +is2_axu_ldst_tag_d <= is2_axu_ldst_tag_l2; +is2_axu_ldst_size_d <= is2_axu_ldst_size_l2; +is2_axu_ldst_update_d <= is2_axu_ldst_update_l2; +is2_axu_ldst_extpid_d <= is2_axu_ldst_extpid_l2; +is2_axu_ldst_forcealign_d <= is2_axu_ldst_forcealign_l2; +is2_axu_ldst_forceexcept_d <= is2_axu_ldst_forceexcept_l2; +is2_axu_mftgpr_d <= is2_axu_mftgpr_l2; +is2_axu_mffgpr_d <= is2_axu_mffgpr_l2; +is2_axu_movedp_d <= is2_axu_movedp_l2; +is2_axu_instr_type_d <= is2_axu_instr_type_l2; +is2_match_d <= is2_match_l2; +is2_2ucode_d <= is2_2ucode_l2; +is2_2ucode_type_d <= is2_2ucode_type_l2; +end if; +if (xu_iu_is1_flush = '1') then +is2_vld_d <= '0'; +end if; + + +end process is2_instr_proc; +-------------------------------------------------------------------------------------------------------------------------------------------------------- +-- Mmmmmmm IS2 Decode +-------------------------------------------------------------------------------------------------------------------------------------------------------- +mult_hole_barrier_d(0) <= not xu_iu_is2_flush and ( mult_hole_barrier_L2(1)); +mult_hole_barrier_d(1) <= not xu_iu_is2_flush and ( mult_hole_barrier_L2(2)); +mult_hole_barrier_d(2) <= not xu_iu_is2_flush and ( mult_hole_barrier_L2(3)); +mult_hole_barrier_d(3) <= not xu_iu_is2_flush and ((is2_vld_l2 and is2_hole_delay_L2(0)) or mult_hole_barrier_L2(4)); +mult_hole_barrier_d(4) <= not xu_iu_is2_flush and ((is2_vld_l2 and is2_hole_delay_L2(1)) or mult_hole_barrier_L2(5)); +mult_hole_barrier_d(5) <= not xu_iu_is2_flush and ((is2_vld_l2 and is2_hole_delay_L2(2)) ); +is2_mult_hole_barrier <= (is2_vld_l2 and or_reduce(is2_hole_delay_L2(0 to 2))) or or_reduce(mult_hole_barrier_L2(0 to 5)); +mult_hole_barrier_act <= is2_mult_hole_barrier; +is1_is_slowspr <= is_slowspr and (isMTSPR or isMFSPR); +is1_is_barrier <= is_bar or is1_is_slowspr or fdec_fdep_is1_to_ucode; +is2_instr_is_barrier <= is2_vld_l2 and is2_is_barrier_L2; +-- +-- Final Table Listing +-- *INPUTS*========================*OUTPUTS*==* +-- | | | +-- | core64 | | +-- | | en_dcr_l2 | | +-- | | | | | +-- | | | fdec_fdep_is1_instr | is_bar | +-- | | | | fdec_fdep_is1_instr| | | +-- | | | | | | | | +-- | | | | 22222222233 | | | +-- | | | 012345 12345678901 | | | +-- *TYPE*==========================+==========+ +-- | P P PPPPPP PPPPPPPPPPP | S | +-- *POLARITY*--------------------->| + | +-- *PHASE*------------------------>| T | +-- *TERMS*=========================+==========+ +-- 1 | - - 011111 11-1010-101 | 1 | +-- 2 | - - 011111 1111010-10- | 1 | +-- 3 | - - 010011 000-100110- | 1 | +-- 4 | 1 - 011111 000-010100- | 1 | +-- 5 | - - 010011 000011001-- | 1 | +-- 6 | - - 010011 0010010110- | 1 | +-- 7 | 1 - 011111 001-0101101 | 1 | +-- 8 | - - 011111 0000010100- | 1 | +-- 9 | - - 011111 1-01010110- | 1 | +-- 10 | 1 - 011111 -11--010-1- | 1 | +-- 11 | - - 011111 1000110110- | 1 | +-- 12 | - - 011111 0-100101101 | 1 | +-- 13 | - - 011111 1110110-101 | 1 | +-- 14 | - - 011111 00-0010010- | 1 | +-- 15 | - 1 011111 01--000011- | 1 | +-- 16 | - 1 011111 01-0-00011- | 1 | +-- 17 | - - 011111 00-0110011- | 1 | +-- 18 | - - 011111 0100001110- | 1 | +-- 19 | - - 011111 -11--01011- | 1 | +-- 20 | - - 011111 11-0010010- | 1 | +-- 21 | - - 011111 1111011111- | 1 | +-- 22 | - - 011111 1100110011- | 1 | +-- 23 | - - 011111 1110-10010- | 1 | +-- 24 | - - 010001 ---------1- | 1 | +-- *==========================================* +-- +-- Table BARRIER Signal Assignments for Product Terms +MQQ1:BARRIER_PT(1) <= + Eq(( FDEC_FDEP_IS1_INSTR(0) & FDEC_FDEP_IS1_INSTR(1) & + FDEC_FDEP_IS1_INSTR(2) & FDEC_FDEP_IS1_INSTR(3) & + FDEC_FDEP_IS1_INSTR(4) & FDEC_FDEP_IS1_INSTR(5) & + FDEC_FDEP_IS1_INSTR(21) & FDEC_FDEP_IS1_INSTR(22) & + FDEC_FDEP_IS1_INSTR(24) & FDEC_FDEP_IS1_INSTR(25) & + FDEC_FDEP_IS1_INSTR(26) & FDEC_FDEP_IS1_INSTR(27) & + FDEC_FDEP_IS1_INSTR(29) & FDEC_FDEP_IS1_INSTR(30) & + FDEC_FDEP_IS1_INSTR(31) ) , STD_ULOGIC_VECTOR'("011111111010101")); +MQQ2:BARRIER_PT(2) <= + Eq(( FDEC_FDEP_IS1_INSTR(0) & FDEC_FDEP_IS1_INSTR(1) & + FDEC_FDEP_IS1_INSTR(2) & FDEC_FDEP_IS1_INSTR(3) & + FDEC_FDEP_IS1_INSTR(4) & FDEC_FDEP_IS1_INSTR(5) & + FDEC_FDEP_IS1_INSTR(21) & FDEC_FDEP_IS1_INSTR(22) & + FDEC_FDEP_IS1_INSTR(23) & FDEC_FDEP_IS1_INSTR(24) & + FDEC_FDEP_IS1_INSTR(25) & FDEC_FDEP_IS1_INSTR(26) & + FDEC_FDEP_IS1_INSTR(27) & FDEC_FDEP_IS1_INSTR(29) & + FDEC_FDEP_IS1_INSTR(30) ) , STD_ULOGIC_VECTOR'("011111111101010")); +MQQ3:BARRIER_PT(3) <= + Eq(( FDEC_FDEP_IS1_INSTR(0) & FDEC_FDEP_IS1_INSTR(1) & + FDEC_FDEP_IS1_INSTR(2) & FDEC_FDEP_IS1_INSTR(3) & + FDEC_FDEP_IS1_INSTR(4) & FDEC_FDEP_IS1_INSTR(5) & + FDEC_FDEP_IS1_INSTR(21) & FDEC_FDEP_IS1_INSTR(22) & + FDEC_FDEP_IS1_INSTR(23) & FDEC_FDEP_IS1_INSTR(25) & + FDEC_FDEP_IS1_INSTR(26) & FDEC_FDEP_IS1_INSTR(27) & + FDEC_FDEP_IS1_INSTR(28) & FDEC_FDEP_IS1_INSTR(29) & + FDEC_FDEP_IS1_INSTR(30) ) , STD_ULOGIC_VECTOR'("010011000100110")); +MQQ4:BARRIER_PT(4) <= + Eq(( CORE64 & FDEC_FDEP_IS1_INSTR(0) & + FDEC_FDEP_IS1_INSTR(1) & FDEC_FDEP_IS1_INSTR(2) & + FDEC_FDEP_IS1_INSTR(3) & FDEC_FDEP_IS1_INSTR(4) & + FDEC_FDEP_IS1_INSTR(5) & FDEC_FDEP_IS1_INSTR(21) & + FDEC_FDEP_IS1_INSTR(22) & FDEC_FDEP_IS1_INSTR(23) & + FDEC_FDEP_IS1_INSTR(25) & FDEC_FDEP_IS1_INSTR(26) & + FDEC_FDEP_IS1_INSTR(27) & FDEC_FDEP_IS1_INSTR(28) & + FDEC_FDEP_IS1_INSTR(29) & FDEC_FDEP_IS1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("1011111000010100")); +MQQ5:BARRIER_PT(5) <= + Eq(( FDEC_FDEP_IS1_INSTR(0) & FDEC_FDEP_IS1_INSTR(1) & + FDEC_FDEP_IS1_INSTR(2) & FDEC_FDEP_IS1_INSTR(3) & + FDEC_FDEP_IS1_INSTR(4) & FDEC_FDEP_IS1_INSTR(5) & + FDEC_FDEP_IS1_INSTR(21) & FDEC_FDEP_IS1_INSTR(22) & + FDEC_FDEP_IS1_INSTR(23) & FDEC_FDEP_IS1_INSTR(24) & + FDEC_FDEP_IS1_INSTR(25) & FDEC_FDEP_IS1_INSTR(26) & + FDEC_FDEP_IS1_INSTR(27) & FDEC_FDEP_IS1_INSTR(28) & + FDEC_FDEP_IS1_INSTR(29) ) , STD_ULOGIC_VECTOR'("010011000011001")); +MQQ6:BARRIER_PT(6) <= + Eq(( FDEC_FDEP_IS1_INSTR(0) & FDEC_FDEP_IS1_INSTR(1) & + FDEC_FDEP_IS1_INSTR(2) & FDEC_FDEP_IS1_INSTR(3) & + FDEC_FDEP_IS1_INSTR(4) & FDEC_FDEP_IS1_INSTR(5) & + FDEC_FDEP_IS1_INSTR(21) & FDEC_FDEP_IS1_INSTR(22) & + FDEC_FDEP_IS1_INSTR(23) & FDEC_FDEP_IS1_INSTR(24) & + FDEC_FDEP_IS1_INSTR(25) & FDEC_FDEP_IS1_INSTR(26) & + FDEC_FDEP_IS1_INSTR(27) & FDEC_FDEP_IS1_INSTR(28) & + FDEC_FDEP_IS1_INSTR(29) & FDEC_FDEP_IS1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("0100110010010110")); +MQQ7:BARRIER_PT(7) <= + Eq(( CORE64 & FDEC_FDEP_IS1_INSTR(0) & + FDEC_FDEP_IS1_INSTR(1) & FDEC_FDEP_IS1_INSTR(2) & + FDEC_FDEP_IS1_INSTR(3) & FDEC_FDEP_IS1_INSTR(4) & + FDEC_FDEP_IS1_INSTR(5) & FDEC_FDEP_IS1_INSTR(21) & + FDEC_FDEP_IS1_INSTR(22) & FDEC_FDEP_IS1_INSTR(23) & + FDEC_FDEP_IS1_INSTR(25) & FDEC_FDEP_IS1_INSTR(26) & + FDEC_FDEP_IS1_INSTR(27) & FDEC_FDEP_IS1_INSTR(28) & + FDEC_FDEP_IS1_INSTR(29) & FDEC_FDEP_IS1_INSTR(30) & + FDEC_FDEP_IS1_INSTR(31) ) , STD_ULOGIC_VECTOR'("10111110010101101")); +MQQ8:BARRIER_PT(8) <= + Eq(( FDEC_FDEP_IS1_INSTR(0) & FDEC_FDEP_IS1_INSTR(1) & + FDEC_FDEP_IS1_INSTR(2) & FDEC_FDEP_IS1_INSTR(3) & + FDEC_FDEP_IS1_INSTR(4) & FDEC_FDEP_IS1_INSTR(5) & + FDEC_FDEP_IS1_INSTR(21) & FDEC_FDEP_IS1_INSTR(22) & + FDEC_FDEP_IS1_INSTR(23) & FDEC_FDEP_IS1_INSTR(24) & + FDEC_FDEP_IS1_INSTR(25) & FDEC_FDEP_IS1_INSTR(26) & + FDEC_FDEP_IS1_INSTR(27) & FDEC_FDEP_IS1_INSTR(28) & + FDEC_FDEP_IS1_INSTR(29) & FDEC_FDEP_IS1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("0111110000010100")); +MQQ9:BARRIER_PT(9) <= + Eq(( FDEC_FDEP_IS1_INSTR(0) & FDEC_FDEP_IS1_INSTR(1) & + FDEC_FDEP_IS1_INSTR(2) & FDEC_FDEP_IS1_INSTR(3) & + FDEC_FDEP_IS1_INSTR(4) & FDEC_FDEP_IS1_INSTR(5) & + FDEC_FDEP_IS1_INSTR(21) & FDEC_FDEP_IS1_INSTR(23) & + FDEC_FDEP_IS1_INSTR(24) & FDEC_FDEP_IS1_INSTR(25) & + FDEC_FDEP_IS1_INSTR(26) & FDEC_FDEP_IS1_INSTR(27) & + FDEC_FDEP_IS1_INSTR(28) & FDEC_FDEP_IS1_INSTR(29) & + FDEC_FDEP_IS1_INSTR(30) ) , STD_ULOGIC_VECTOR'("011111101010110")); +MQQ10:BARRIER_PT(10) <= + Eq(( CORE64 & FDEC_FDEP_IS1_INSTR(0) & + FDEC_FDEP_IS1_INSTR(1) & FDEC_FDEP_IS1_INSTR(2) & + FDEC_FDEP_IS1_INSTR(3) & FDEC_FDEP_IS1_INSTR(4) & + FDEC_FDEP_IS1_INSTR(5) & FDEC_FDEP_IS1_INSTR(22) & + FDEC_FDEP_IS1_INSTR(23) & FDEC_FDEP_IS1_INSTR(26) & + FDEC_FDEP_IS1_INSTR(27) & FDEC_FDEP_IS1_INSTR(28) & + FDEC_FDEP_IS1_INSTR(30) ) , STD_ULOGIC_VECTOR'("1011111110101")); +MQQ11:BARRIER_PT(11) <= + Eq(( FDEC_FDEP_IS1_INSTR(0) & FDEC_FDEP_IS1_INSTR(1) & + FDEC_FDEP_IS1_INSTR(2) & FDEC_FDEP_IS1_INSTR(3) & + FDEC_FDEP_IS1_INSTR(4) & FDEC_FDEP_IS1_INSTR(5) & + FDEC_FDEP_IS1_INSTR(21) & FDEC_FDEP_IS1_INSTR(22) & + FDEC_FDEP_IS1_INSTR(23) & FDEC_FDEP_IS1_INSTR(24) & + FDEC_FDEP_IS1_INSTR(25) & FDEC_FDEP_IS1_INSTR(26) & + FDEC_FDEP_IS1_INSTR(27) & FDEC_FDEP_IS1_INSTR(28) & + FDEC_FDEP_IS1_INSTR(29) & FDEC_FDEP_IS1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("0111111000110110")); +MQQ12:BARRIER_PT(12) <= + Eq(( FDEC_FDEP_IS1_INSTR(0) & FDEC_FDEP_IS1_INSTR(1) & + FDEC_FDEP_IS1_INSTR(2) & FDEC_FDEP_IS1_INSTR(3) & + FDEC_FDEP_IS1_INSTR(4) & FDEC_FDEP_IS1_INSTR(5) & + FDEC_FDEP_IS1_INSTR(21) & FDEC_FDEP_IS1_INSTR(23) & + FDEC_FDEP_IS1_INSTR(24) & FDEC_FDEP_IS1_INSTR(25) & + FDEC_FDEP_IS1_INSTR(26) & FDEC_FDEP_IS1_INSTR(27) & + FDEC_FDEP_IS1_INSTR(28) & FDEC_FDEP_IS1_INSTR(29) & + FDEC_FDEP_IS1_INSTR(30) & FDEC_FDEP_IS1_INSTR(31) + ) , STD_ULOGIC_VECTOR'("0111110100101101")); +MQQ13:BARRIER_PT(13) <= + Eq(( FDEC_FDEP_IS1_INSTR(0) & FDEC_FDEP_IS1_INSTR(1) & + FDEC_FDEP_IS1_INSTR(2) & FDEC_FDEP_IS1_INSTR(3) & + FDEC_FDEP_IS1_INSTR(4) & FDEC_FDEP_IS1_INSTR(5) & + FDEC_FDEP_IS1_INSTR(21) & FDEC_FDEP_IS1_INSTR(22) & + FDEC_FDEP_IS1_INSTR(23) & FDEC_FDEP_IS1_INSTR(24) & + FDEC_FDEP_IS1_INSTR(25) & FDEC_FDEP_IS1_INSTR(26) & + FDEC_FDEP_IS1_INSTR(27) & FDEC_FDEP_IS1_INSTR(29) & + FDEC_FDEP_IS1_INSTR(30) & FDEC_FDEP_IS1_INSTR(31) + ) , STD_ULOGIC_VECTOR'("0111111110110101")); +MQQ14:BARRIER_PT(14) <= + Eq(( FDEC_FDEP_IS1_INSTR(0) & FDEC_FDEP_IS1_INSTR(1) & + FDEC_FDEP_IS1_INSTR(2) & FDEC_FDEP_IS1_INSTR(3) & + FDEC_FDEP_IS1_INSTR(4) & FDEC_FDEP_IS1_INSTR(5) & + FDEC_FDEP_IS1_INSTR(21) & FDEC_FDEP_IS1_INSTR(22) & + FDEC_FDEP_IS1_INSTR(24) & FDEC_FDEP_IS1_INSTR(25) & + FDEC_FDEP_IS1_INSTR(26) & FDEC_FDEP_IS1_INSTR(27) & + FDEC_FDEP_IS1_INSTR(28) & FDEC_FDEP_IS1_INSTR(29) & + FDEC_FDEP_IS1_INSTR(30) ) , STD_ULOGIC_VECTOR'("011111000010010")); +MQQ15:BARRIER_PT(15) <= + Eq(( EN_DCR_L2 & FDEC_FDEP_IS1_INSTR(0) & + FDEC_FDEP_IS1_INSTR(1) & FDEC_FDEP_IS1_INSTR(2) & + FDEC_FDEP_IS1_INSTR(3) & FDEC_FDEP_IS1_INSTR(4) & + FDEC_FDEP_IS1_INSTR(5) & FDEC_FDEP_IS1_INSTR(21) & + FDEC_FDEP_IS1_INSTR(22) & FDEC_FDEP_IS1_INSTR(25) & + FDEC_FDEP_IS1_INSTR(26) & FDEC_FDEP_IS1_INSTR(27) & + FDEC_FDEP_IS1_INSTR(28) & FDEC_FDEP_IS1_INSTR(29) & + FDEC_FDEP_IS1_INSTR(30) ) , STD_ULOGIC_VECTOR'("101111101000011")); +MQQ16:BARRIER_PT(16) <= + Eq(( EN_DCR_L2 & FDEC_FDEP_IS1_INSTR(0) & + FDEC_FDEP_IS1_INSTR(1) & FDEC_FDEP_IS1_INSTR(2) & + FDEC_FDEP_IS1_INSTR(3) & FDEC_FDEP_IS1_INSTR(4) & + FDEC_FDEP_IS1_INSTR(5) & FDEC_FDEP_IS1_INSTR(21) & + FDEC_FDEP_IS1_INSTR(22) & FDEC_FDEP_IS1_INSTR(24) & + FDEC_FDEP_IS1_INSTR(26) & FDEC_FDEP_IS1_INSTR(27) & + FDEC_FDEP_IS1_INSTR(28) & FDEC_FDEP_IS1_INSTR(29) & + FDEC_FDEP_IS1_INSTR(30) ) , STD_ULOGIC_VECTOR'("101111101000011")); +MQQ17:BARRIER_PT(17) <= + Eq(( FDEC_FDEP_IS1_INSTR(0) & FDEC_FDEP_IS1_INSTR(1) & + FDEC_FDEP_IS1_INSTR(2) & FDEC_FDEP_IS1_INSTR(3) & + FDEC_FDEP_IS1_INSTR(4) & FDEC_FDEP_IS1_INSTR(5) & + FDEC_FDEP_IS1_INSTR(21) & FDEC_FDEP_IS1_INSTR(22) & + FDEC_FDEP_IS1_INSTR(24) & FDEC_FDEP_IS1_INSTR(25) & + FDEC_FDEP_IS1_INSTR(26) & FDEC_FDEP_IS1_INSTR(27) & + FDEC_FDEP_IS1_INSTR(28) & FDEC_FDEP_IS1_INSTR(29) & + FDEC_FDEP_IS1_INSTR(30) ) , STD_ULOGIC_VECTOR'("011111000110011")); +MQQ18:BARRIER_PT(18) <= + Eq(( FDEC_FDEP_IS1_INSTR(0) & FDEC_FDEP_IS1_INSTR(1) & + FDEC_FDEP_IS1_INSTR(2) & FDEC_FDEP_IS1_INSTR(3) & + FDEC_FDEP_IS1_INSTR(4) & FDEC_FDEP_IS1_INSTR(5) & + FDEC_FDEP_IS1_INSTR(21) & FDEC_FDEP_IS1_INSTR(22) & + FDEC_FDEP_IS1_INSTR(23) & FDEC_FDEP_IS1_INSTR(24) & + FDEC_FDEP_IS1_INSTR(25) & FDEC_FDEP_IS1_INSTR(26) & + FDEC_FDEP_IS1_INSTR(27) & FDEC_FDEP_IS1_INSTR(28) & + FDEC_FDEP_IS1_INSTR(29) & FDEC_FDEP_IS1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("0111110100001110")); +MQQ19:BARRIER_PT(19) <= + Eq(( FDEC_FDEP_IS1_INSTR(0) & FDEC_FDEP_IS1_INSTR(1) & + FDEC_FDEP_IS1_INSTR(2) & FDEC_FDEP_IS1_INSTR(3) & + FDEC_FDEP_IS1_INSTR(4) & FDEC_FDEP_IS1_INSTR(5) & + FDEC_FDEP_IS1_INSTR(22) & FDEC_FDEP_IS1_INSTR(23) & + FDEC_FDEP_IS1_INSTR(26) & FDEC_FDEP_IS1_INSTR(27) & + FDEC_FDEP_IS1_INSTR(28) & FDEC_FDEP_IS1_INSTR(29) & + FDEC_FDEP_IS1_INSTR(30) ) , STD_ULOGIC_VECTOR'("0111111101011")); +MQQ20:BARRIER_PT(20) <= + Eq(( FDEC_FDEP_IS1_INSTR(0) & FDEC_FDEP_IS1_INSTR(1) & + FDEC_FDEP_IS1_INSTR(2) & FDEC_FDEP_IS1_INSTR(3) & + FDEC_FDEP_IS1_INSTR(4) & FDEC_FDEP_IS1_INSTR(5) & + FDEC_FDEP_IS1_INSTR(21) & FDEC_FDEP_IS1_INSTR(22) & + FDEC_FDEP_IS1_INSTR(24) & FDEC_FDEP_IS1_INSTR(25) & + FDEC_FDEP_IS1_INSTR(26) & FDEC_FDEP_IS1_INSTR(27) & + FDEC_FDEP_IS1_INSTR(28) & FDEC_FDEP_IS1_INSTR(29) & + FDEC_FDEP_IS1_INSTR(30) ) , STD_ULOGIC_VECTOR'("011111110010010")); +MQQ21:BARRIER_PT(21) <= + Eq(( FDEC_FDEP_IS1_INSTR(0) & FDEC_FDEP_IS1_INSTR(1) & + FDEC_FDEP_IS1_INSTR(2) & FDEC_FDEP_IS1_INSTR(3) & + FDEC_FDEP_IS1_INSTR(4) & FDEC_FDEP_IS1_INSTR(5) & + FDEC_FDEP_IS1_INSTR(21) & FDEC_FDEP_IS1_INSTR(22) & + FDEC_FDEP_IS1_INSTR(23) & FDEC_FDEP_IS1_INSTR(24) & + FDEC_FDEP_IS1_INSTR(25) & FDEC_FDEP_IS1_INSTR(26) & + FDEC_FDEP_IS1_INSTR(27) & FDEC_FDEP_IS1_INSTR(28) & + FDEC_FDEP_IS1_INSTR(29) & FDEC_FDEP_IS1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("0111111111011111")); +MQQ22:BARRIER_PT(22) <= + Eq(( FDEC_FDEP_IS1_INSTR(0) & FDEC_FDEP_IS1_INSTR(1) & + FDEC_FDEP_IS1_INSTR(2) & FDEC_FDEP_IS1_INSTR(3) & + FDEC_FDEP_IS1_INSTR(4) & FDEC_FDEP_IS1_INSTR(5) & + FDEC_FDEP_IS1_INSTR(21) & FDEC_FDEP_IS1_INSTR(22) & + FDEC_FDEP_IS1_INSTR(23) & FDEC_FDEP_IS1_INSTR(24) & + FDEC_FDEP_IS1_INSTR(25) & FDEC_FDEP_IS1_INSTR(26) & + FDEC_FDEP_IS1_INSTR(27) & FDEC_FDEP_IS1_INSTR(28) & + FDEC_FDEP_IS1_INSTR(29) & FDEC_FDEP_IS1_INSTR(30) + ) , STD_ULOGIC_VECTOR'("0111111100110011")); +MQQ23:BARRIER_PT(23) <= + Eq(( FDEC_FDEP_IS1_INSTR(0) & FDEC_FDEP_IS1_INSTR(1) & + FDEC_FDEP_IS1_INSTR(2) & FDEC_FDEP_IS1_INSTR(3) & + FDEC_FDEP_IS1_INSTR(4) & FDEC_FDEP_IS1_INSTR(5) & + FDEC_FDEP_IS1_INSTR(21) & FDEC_FDEP_IS1_INSTR(22) & + FDEC_FDEP_IS1_INSTR(23) & FDEC_FDEP_IS1_INSTR(24) & + FDEC_FDEP_IS1_INSTR(26) & FDEC_FDEP_IS1_INSTR(27) & + FDEC_FDEP_IS1_INSTR(28) & FDEC_FDEP_IS1_INSTR(29) & + FDEC_FDEP_IS1_INSTR(30) ) , STD_ULOGIC_VECTOR'("011111111010010")); +MQQ24:BARRIER_PT(24) <= + Eq(( FDEC_FDEP_IS1_INSTR(0) & FDEC_FDEP_IS1_INSTR(1) & + FDEC_FDEP_IS1_INSTR(2) & FDEC_FDEP_IS1_INSTR(3) & + FDEC_FDEP_IS1_INSTR(4) & FDEC_FDEP_IS1_INSTR(5) & + FDEC_FDEP_IS1_INSTR(30) ) , STD_ULOGIC_VECTOR'("0100011")); +-- Table BARRIER Signal Assignments for Outputs +MQQ25:IS_BAR <= + (BARRIER_PT(1) OR BARRIER_PT(2) + OR BARRIER_PT(3) OR BARRIER_PT(4) + OR BARRIER_PT(5) OR BARRIER_PT(6) + OR BARRIER_PT(7) OR BARRIER_PT(8) + OR BARRIER_PT(9) OR BARRIER_PT(10) + OR BARRIER_PT(11) OR BARRIER_PT(12) + OR BARRIER_PT(13) OR BARRIER_PT(14) + OR BARRIER_PT(15) OR BARRIER_PT(16) + OR BARRIER_PT(17) OR BARRIER_PT(18) + OR BARRIER_PT(19) OR BARRIER_PT(20) + OR BARRIER_PT(21) OR BARRIER_PT(22) + OR BARRIER_PT(23) OR BARRIER_PT(24) + ); + +isMFSPR <= (fdec_fdep_is1_instr(0 to 5) = "011111") and (fdec_fdep_is1_instr(21 to 30) = "0101010011"); +isMTSPR <= (fdec_fdep_is1_instr(0 to 5) = "011111") and (fdec_fdep_is1_instr(21 to 30) = "0111010011"); +-- +-- Final Table Listing +-- *INPUTS*=============*OUTPUTS*========* +-- | | | +-- | fdec_fdep_is1_instr| | +-- | | | is_slowspr | +-- | 1111211111 | | | +-- | 6789012345 | | | +-- *TYPE*===============+================+ +-- | PPPPPPPPPP | S | +-- *POLARITY*---------->| + | +-- *PHASE*------------->| T | +-- *TERMS*=*=*==========+================+ +-- 1 | 01010111-0 | 1 | +-- 2 | 010101-101 | 1 | +-- 3 | 111--10100 | 1 | +-- 4 | 1001110-1- | 1 | +-- 5 | 11-1111-00 | 1 | +-- 6 | 11-1110-11 | 1 | +-- 7 | 1-0111000- | 1 | +-- 8 | 1-011101-0 | 1 | +-- 9 | 11100-0010 | 1 | +-- 10 | 000011100- | 1 | +-- 11 | 1-10110000 | 1 | +-- 12 | 000011-000 | 1 | +-- 13 | 010011111- | 1 | +-- 14 | 111--10011 | 1 | +-- 15 | 0101011-00 | 1 | +-- 16 | 0101010-1- | 1 | +-- 17 | 1111-111-- | 1 | +-- 18 | 11011110-- | 1 | +-- 19 | -10111010- | 1 | +-- 20 | 111-01---- | 1 | +-- *=====================================* +-- +-- Table SLOWSPR_TABLE Signal Assignments for Product Terms +MQQ26:SLOWSPR_TABLE_PT(1) <= + Eq(( FDEC_FDEP_IS1_INSTR(16) & FDEC_FDEP_IS1_INSTR(17) & + FDEC_FDEP_IS1_INSTR(18) & FDEC_FDEP_IS1_INSTR(19) & + FDEC_FDEP_IS1_INSTR(20) & FDEC_FDEP_IS1_INSTR(11) & + FDEC_FDEP_IS1_INSTR(12) & FDEC_FDEP_IS1_INSTR(13) & + FDEC_FDEP_IS1_INSTR(15) ) , STD_ULOGIC_VECTOR'("010101110")); +MQQ27:SLOWSPR_TABLE_PT(2) <= + Eq(( FDEC_FDEP_IS1_INSTR(16) & FDEC_FDEP_IS1_INSTR(17) & + FDEC_FDEP_IS1_INSTR(18) & FDEC_FDEP_IS1_INSTR(19) & + FDEC_FDEP_IS1_INSTR(20) & FDEC_FDEP_IS1_INSTR(11) & + FDEC_FDEP_IS1_INSTR(13) & FDEC_FDEP_IS1_INSTR(14) & + FDEC_FDEP_IS1_INSTR(15) ) , STD_ULOGIC_VECTOR'("010101101")); +MQQ28:SLOWSPR_TABLE_PT(3) <= + Eq(( FDEC_FDEP_IS1_INSTR(16) & FDEC_FDEP_IS1_INSTR(17) & + FDEC_FDEP_IS1_INSTR(18) & FDEC_FDEP_IS1_INSTR(11) & + FDEC_FDEP_IS1_INSTR(12) & FDEC_FDEP_IS1_INSTR(13) & + FDEC_FDEP_IS1_INSTR(14) & FDEC_FDEP_IS1_INSTR(15) + ) , STD_ULOGIC_VECTOR'("11110100")); +MQQ29:SLOWSPR_TABLE_PT(4) <= + Eq(( FDEC_FDEP_IS1_INSTR(16) & FDEC_FDEP_IS1_INSTR(17) & + FDEC_FDEP_IS1_INSTR(18) & FDEC_FDEP_IS1_INSTR(19) & + FDEC_FDEP_IS1_INSTR(20) & FDEC_FDEP_IS1_INSTR(11) & + FDEC_FDEP_IS1_INSTR(12) & FDEC_FDEP_IS1_INSTR(14) + ) , STD_ULOGIC_VECTOR'("10011101")); +MQQ30:SLOWSPR_TABLE_PT(5) <= + Eq(( FDEC_FDEP_IS1_INSTR(16) & FDEC_FDEP_IS1_INSTR(17) & + FDEC_FDEP_IS1_INSTR(19) & FDEC_FDEP_IS1_INSTR(20) & + FDEC_FDEP_IS1_INSTR(11) & FDEC_FDEP_IS1_INSTR(12) & + FDEC_FDEP_IS1_INSTR(14) & FDEC_FDEP_IS1_INSTR(15) + ) , STD_ULOGIC_VECTOR'("11111100")); +MQQ31:SLOWSPR_TABLE_PT(6) <= + Eq(( FDEC_FDEP_IS1_INSTR(16) & FDEC_FDEP_IS1_INSTR(17) & + FDEC_FDEP_IS1_INSTR(19) & FDEC_FDEP_IS1_INSTR(20) & + FDEC_FDEP_IS1_INSTR(11) & FDEC_FDEP_IS1_INSTR(12) & + FDEC_FDEP_IS1_INSTR(14) & FDEC_FDEP_IS1_INSTR(15) + ) , STD_ULOGIC_VECTOR'("11111011")); +MQQ32:SLOWSPR_TABLE_PT(7) <= + Eq(( FDEC_FDEP_IS1_INSTR(16) & FDEC_FDEP_IS1_INSTR(18) & + FDEC_FDEP_IS1_INSTR(19) & FDEC_FDEP_IS1_INSTR(20) & + FDEC_FDEP_IS1_INSTR(11) & FDEC_FDEP_IS1_INSTR(12) & + FDEC_FDEP_IS1_INSTR(13) & FDEC_FDEP_IS1_INSTR(14) + ) , STD_ULOGIC_VECTOR'("10111000")); +MQQ33:SLOWSPR_TABLE_PT(8) <= + Eq(( FDEC_FDEP_IS1_INSTR(16) & FDEC_FDEP_IS1_INSTR(18) & + FDEC_FDEP_IS1_INSTR(19) & FDEC_FDEP_IS1_INSTR(20) & + FDEC_FDEP_IS1_INSTR(11) & FDEC_FDEP_IS1_INSTR(12) & + FDEC_FDEP_IS1_INSTR(13) & FDEC_FDEP_IS1_INSTR(15) + ) , STD_ULOGIC_VECTOR'("10111010")); +MQQ34:SLOWSPR_TABLE_PT(9) <= + Eq(( FDEC_FDEP_IS1_INSTR(16) & FDEC_FDEP_IS1_INSTR(17) & + FDEC_FDEP_IS1_INSTR(18) & FDEC_FDEP_IS1_INSTR(19) & + FDEC_FDEP_IS1_INSTR(20) & FDEC_FDEP_IS1_INSTR(12) & + FDEC_FDEP_IS1_INSTR(13) & FDEC_FDEP_IS1_INSTR(14) & + FDEC_FDEP_IS1_INSTR(15) ) , STD_ULOGIC_VECTOR'("111000010")); +MQQ35:SLOWSPR_TABLE_PT(10) <= + Eq(( FDEC_FDEP_IS1_INSTR(16) & FDEC_FDEP_IS1_INSTR(17) & + FDEC_FDEP_IS1_INSTR(18) & FDEC_FDEP_IS1_INSTR(19) & + FDEC_FDEP_IS1_INSTR(20) & FDEC_FDEP_IS1_INSTR(11) & + FDEC_FDEP_IS1_INSTR(12) & FDEC_FDEP_IS1_INSTR(13) & + FDEC_FDEP_IS1_INSTR(14) ) , STD_ULOGIC_VECTOR'("000011100")); +MQQ36:SLOWSPR_TABLE_PT(11) <= + Eq(( FDEC_FDEP_IS1_INSTR(16) & FDEC_FDEP_IS1_INSTR(18) & + FDEC_FDEP_IS1_INSTR(19) & FDEC_FDEP_IS1_INSTR(20) & + FDEC_FDEP_IS1_INSTR(11) & FDEC_FDEP_IS1_INSTR(12) & + FDEC_FDEP_IS1_INSTR(13) & FDEC_FDEP_IS1_INSTR(14) & + FDEC_FDEP_IS1_INSTR(15) ) , STD_ULOGIC_VECTOR'("110110000")); +MQQ37:SLOWSPR_TABLE_PT(12) <= + Eq(( FDEC_FDEP_IS1_INSTR(16) & FDEC_FDEP_IS1_INSTR(17) & + FDEC_FDEP_IS1_INSTR(18) & FDEC_FDEP_IS1_INSTR(19) & + FDEC_FDEP_IS1_INSTR(20) & FDEC_FDEP_IS1_INSTR(11) & + FDEC_FDEP_IS1_INSTR(13) & FDEC_FDEP_IS1_INSTR(14) & + FDEC_FDEP_IS1_INSTR(15) ) , STD_ULOGIC_VECTOR'("000011000")); +MQQ38:SLOWSPR_TABLE_PT(13) <= + Eq(( FDEC_FDEP_IS1_INSTR(16) & FDEC_FDEP_IS1_INSTR(17) & + FDEC_FDEP_IS1_INSTR(18) & FDEC_FDEP_IS1_INSTR(19) & + FDEC_FDEP_IS1_INSTR(20) & FDEC_FDEP_IS1_INSTR(11) & + FDEC_FDEP_IS1_INSTR(12) & FDEC_FDEP_IS1_INSTR(13) & + FDEC_FDEP_IS1_INSTR(14) ) , STD_ULOGIC_VECTOR'("010011111")); +MQQ39:SLOWSPR_TABLE_PT(14) <= + Eq(( FDEC_FDEP_IS1_INSTR(16) & FDEC_FDEP_IS1_INSTR(17) & + FDEC_FDEP_IS1_INSTR(18) & FDEC_FDEP_IS1_INSTR(11) & + FDEC_FDEP_IS1_INSTR(12) & FDEC_FDEP_IS1_INSTR(13) & + FDEC_FDEP_IS1_INSTR(14) & FDEC_FDEP_IS1_INSTR(15) + ) , STD_ULOGIC_VECTOR'("11110011")); +MQQ40:SLOWSPR_TABLE_PT(15) <= + Eq(( FDEC_FDEP_IS1_INSTR(16) & FDEC_FDEP_IS1_INSTR(17) & + FDEC_FDEP_IS1_INSTR(18) & FDEC_FDEP_IS1_INSTR(19) & + FDEC_FDEP_IS1_INSTR(20) & FDEC_FDEP_IS1_INSTR(11) & + FDEC_FDEP_IS1_INSTR(12) & FDEC_FDEP_IS1_INSTR(14) & + FDEC_FDEP_IS1_INSTR(15) ) , STD_ULOGIC_VECTOR'("010101100")); +MQQ41:SLOWSPR_TABLE_PT(16) <= + Eq(( FDEC_FDEP_IS1_INSTR(16) & FDEC_FDEP_IS1_INSTR(17) & + FDEC_FDEP_IS1_INSTR(18) & FDEC_FDEP_IS1_INSTR(19) & + FDEC_FDEP_IS1_INSTR(20) & FDEC_FDEP_IS1_INSTR(11) & + FDEC_FDEP_IS1_INSTR(12) & FDEC_FDEP_IS1_INSTR(14) + ) , STD_ULOGIC_VECTOR'("01010101")); +MQQ42:SLOWSPR_TABLE_PT(17) <= + Eq(( FDEC_FDEP_IS1_INSTR(16) & FDEC_FDEP_IS1_INSTR(17) & + FDEC_FDEP_IS1_INSTR(18) & FDEC_FDEP_IS1_INSTR(19) & + FDEC_FDEP_IS1_INSTR(11) & FDEC_FDEP_IS1_INSTR(12) & + FDEC_FDEP_IS1_INSTR(13) ) , STD_ULOGIC_VECTOR'("1111111")); +MQQ43:SLOWSPR_TABLE_PT(18) <= + Eq(( FDEC_FDEP_IS1_INSTR(16) & FDEC_FDEP_IS1_INSTR(17) & + FDEC_FDEP_IS1_INSTR(18) & FDEC_FDEP_IS1_INSTR(19) & + FDEC_FDEP_IS1_INSTR(20) & FDEC_FDEP_IS1_INSTR(11) & + FDEC_FDEP_IS1_INSTR(12) & FDEC_FDEP_IS1_INSTR(13) + ) , STD_ULOGIC_VECTOR'("11011110")); +MQQ44:SLOWSPR_TABLE_PT(19) <= + Eq(( FDEC_FDEP_IS1_INSTR(17) & FDEC_FDEP_IS1_INSTR(18) & + FDEC_FDEP_IS1_INSTR(19) & FDEC_FDEP_IS1_INSTR(20) & + FDEC_FDEP_IS1_INSTR(11) & FDEC_FDEP_IS1_INSTR(12) & + FDEC_FDEP_IS1_INSTR(13) & FDEC_FDEP_IS1_INSTR(14) + ) , STD_ULOGIC_VECTOR'("10111010")); +MQQ45:SLOWSPR_TABLE_PT(20) <= + Eq(( FDEC_FDEP_IS1_INSTR(16) & FDEC_FDEP_IS1_INSTR(17) & + FDEC_FDEP_IS1_INSTR(18) & FDEC_FDEP_IS1_INSTR(20) & + FDEC_FDEP_IS1_INSTR(11) ) , STD_ULOGIC_VECTOR'("11101")); +-- Table SLOWSPR_TABLE Signal Assignments for Outputs +MQQ46:IS_SLOWSPR <= + (SLOWSPR_TABLE_PT(1) OR SLOWSPR_TABLE_PT(2) + OR SLOWSPR_TABLE_PT(3) OR SLOWSPR_TABLE_PT(4) + OR SLOWSPR_TABLE_PT(5) OR SLOWSPR_TABLE_PT(6) + OR SLOWSPR_TABLE_PT(7) OR SLOWSPR_TABLE_PT(8) + OR SLOWSPR_TABLE_PT(9) OR SLOWSPR_TABLE_PT(10) + OR SLOWSPR_TABLE_PT(11) OR SLOWSPR_TABLE_PT(12) + OR SLOWSPR_TABLE_PT(13) OR SLOWSPR_TABLE_PT(14) + OR SLOWSPR_TABLE_PT(15) OR SLOWSPR_TABLE_PT(16) + OR SLOWSPR_TABLE_PT(17) OR SLOWSPR_TABLE_PT(18) + OR SLOWSPR_TABLE_PT(19) OR SLOWSPR_TABLE_PT(20) + ); + +-- | 1101110010 | 1 | IAR 882 +-------------------------------------------------------------------------------------------------------------------------------------------------------- +-- axu hold +-------------------------------------------------------------------------------------------------------------------------------------------------------- +iu_au_is1_hold <= (barrier_in_progress or single_instr_dep_hit); +-------------------------------------------------------------------------------------------------------------------------------------------------------- +-- Creation of internal_is2_stall +-------------------------------------------------------------------------------------------------------------------------------------------------------- +is2_vld_b <= not is2_vld_L2; +fxu_iss_stall_nor2: fxu_iss_stall <= not (fiss_fdep_is2_take or is2_vld_b); +is2_iss_stall_nor2: is2_iss_stall_b <= not (fxu_iss_stall or au_iu_issue_stall); +internal_is2_stall <= not is2_iss_stall_b; +iu_au_is2_stall <= internal_is2_stall; +-------------------------------------------------------------------------------------------------------------------------------------------------------- +-- ISYNC +-------------------------------------------------------------------------------------------------------------------------------------------------------- +-- Notes: +-- ISYNC is a context synchronizing instruction. Simple to implement in dependency. +-- Just make ISYNC dependent on all instructions that are valid in the shadow pipe. +-- Then it is allowed to issue. The FXU generates an N+1 flush when ISYNC hits the +-- appropriate flush point +sync_dep_hit <= (is1_instr_is_ISYNC or is1_instr_is_SYNC or is1_instr_is_TLBSYNC) and (shadow_pipe_vld or au_iu_is2_axubusy); +-------------------------------------------------------------------------------------------------------------------------------------------------------- +-- BARRIER +-------------------------------------------------------------------------------------------------------------------------------------------------------- +-- Barrier is allowed to issue, it is not dependent on any instruction in front of it. +-- When Barrier moves from IS1 to IS2 an IS2 latch is set that represents an barrier in +-- progress. This status bit is cleared by the IU when it is finished handling the barrier. +-- barrier inprogress is logically or'd into dep_hit. Therefore when the IU is finished +-- handling the barrier, the issue block will be released. A flush will also cause +-- barrier_in_progress to be cleared. +sp_barrier_clr <= (xu_iu_rf0_flush and sp_L2(RF0).barrier) or + (xu_iu_rf1_flush and sp_L2(RF1).barrier) or + (xu_iu_ex1_flush and sp_L2(EX1).barrier) or + (xu_iu_ex2_flush and sp_L2(EX2).barrier) or + (xu_iu_ex3_flush and sp_EX3_barrier_L2) or + (xu_iu_ex4_flush and sp_EX4_barrier_L2) or + (xu_iu_ex5_flush and sp_EX5_barrier_L2) ; +an_ac_sync_ack_d <= an_ac_sync_ack; +xu_iu_membar_tid_d <= xu_iu_membar_tid; +xu_iu_multdiv_done_d <= xu_iu_multdiv_done; +mm_iu_barrier_done_d <= mm_iu_barrier_done; +spr_fdep_ll_hold_d <= spr_fdep_ll_hold; +clr_barrier <= xu_iu_larx_done_tid or an_ac_sync_ack_l2 or ic_fdep_icbi_ack or an_ac_stcx_complete or sp_barrier_clr or xu_iu_slowspr_done or xu_iu_multdiv_done_l2 or mm_iu_barrier_done_l2; +set_barrier <= (not xu_iu_is2_flush and not barrier_L2 and is2_instr_is_barrier and not internal_is2_stall); +barrier_d_proc : process(barrier_L2, clr_barrier, set_barrier) +begin +barrier_d <= barrier_L2; +if ib(set_barrier) then +barrier_d <= '1'; +elsif ib(clr_barrier) then +barrier_d <= '0'; +end if; +end process barrier_d_proc; +xu_barrier_d_proc : process(xu_barrier_L2, xu_iu_membar_tid_l2, xu_iu_set_barr_tid) +begin +xu_barrier_d <= xu_barrier_L2; +if ib(xu_iu_set_barr_tid) then +xu_barrier_d <= '1'; +elsif ib(xu_iu_membar_tid_l2) then +xu_barrier_d <= '0'; +end if; +end process xu_barrier_d_proc; +barrier_in_progress <= barrier_L2 or is2_instr_is_barrier or is2_mult_hole_barrier or xu_barrier_L2 or spr_fdep_ll_hold_L2; +quiesce_barrier <= barrier_L2 or is2_instr_is_barrier or is2_mult_hole_barrier or xu_barrier_L2; +quiesce_d <= ic_fdep_load_quiesce and not quiesce_barrier and not au_iu_is2_axubusy; +iu_xu_quiesce <= quiesce_L2; +----------------------------------- +-- Perf +----------------------------------- +perf_early_d(0) <= dep_hit; +perf_early_d(1) <= fdec_fdep_is1_vld; +perf_early_d(2) <= internal_is2_stall; +perf_early_d(3) <= i_afd_is1_instr_v; +perf_early_d(4) <= au_iu_is1_dep_hit; +perf_early_d(5) <= barrier_in_progress; +perf_early_d(6) <= is2_is_slowspr_L2; +perf_early_d(7) <= RAW_dep_hit; +perf_early_d(8) <= WAW_LMQ_dep_hit; +perf_early_d(9) <= sync_dep_hit; +perf_early_d(10) <= xu_dep_hit; +perf_early_d(11) <= br_sprs_dep_hit; +perf_dep_hit <= perf_early_l2(0); +perf_fdec_fdep_is1_vld <= perf_early_l2(1); +perf_internal_is2_stall <= perf_early_l2(2); +perf_i_afd_is1_instr_v <= perf_early_l2(3); +perf_au_iu_is1_dep_hit <= perf_early_l2(4); +perf_barrier_in_progress <= perf_early_l2(5); +perf_is2_is_slowspr_L2 <= perf_early_l2(6); +perf_RAW_dep_hit <= perf_early_l2(7); +perf_WAW_LMQ_dep_hit <= perf_early_l2(8); +perf_sync_dep_hit <= perf_early_l2(9); +perf_xu_dep_hit <= perf_early_l2(10); +perf_br_sprs_dep_hit <= perf_early_l2(11); +perf_event_d(0) <= (perf_dep_hit and perf_fdec_fdep_is1_vld) or + (perf_internal_is2_stall and perf_i_afd_is1_instr_v) or + (perf_au_iu_is1_dep_hit); +perf_event_d(1) <= perf_internal_is2_stall and (perf_fdec_fdep_is1_vld or perf_i_afd_is1_instr_v); +perf_event_d(2) <= perf_barrier_in_progress and perf_fdec_fdep_is1_vld; +perf_event_d(3) <= perf_barrier_in_progress and perf_is2_is_slowspr_L2 and perf_fdec_fdep_is1_vld; +perf_event_d(4) <= perf_RAW_dep_hit and perf_fdec_fdep_is1_vld; +perf_event_d(5) <= perf_WAW_LMQ_dep_hit and perf_fdec_fdep_is1_vld; +perf_event_d(6) <= perf_sync_dep_hit and perf_fdec_fdep_is1_vld; +perf_event_d(7) <= perf_br_sprs_dep_hit and perf_fdec_fdep_is1_vld; +perf_event_d(8) <= perf_au_iu_is1_dep_hit; +perf_event_d(9) <= perf_xu_dep_hit and perf_fdec_fdep_is1_vld; +perf_event_d(10) <= (perf_xu_dep_hit and perf_fdec_fdep_is1_vld) or perf_au_iu_is1_dep_hit; +perf_event_d(11) <= '0'; +fdep_perf_event(0 TO 11) <= perf_event_l2(0 to 11); +----------------------------------- +-- Debug +----------------------------------- +fdep_dbg_data_d(0) <= barrier_l2; +fdep_dbg_data_d(1) <= is2_instr_is_barrier; +fdep_dbg_data_d(2) <= is2_mult_hole_barrier; +fdep_dbg_data_d(3) <= xu_barrier_L2; +fdep_dbg_data_d(4) <= xu_iu_larx_done_tid; +fdep_dbg_data_d(5) <= an_ac_sync_ack; +fdep_dbg_data_d(6) <= an_ac_stcx_complete; +fdep_dbg_data_d(7) <= ic_fdep_icbi_ack; +fdep_dbg_data_d(8) <= sp_barrier_clr; +fdep_dbg_data_d(9) <= xu_iu_slowspr_done; +fdep_dbg_data_d(10) <= xu_iu_multdiv_done; +fdep_dbg_data_d(11) <= mm_iu_barrier_done; +fdep_dbg_data_d(12) <= xu_iu_set_barr_tid; +fdep_dbg_data_d(13) <= xu_iu_membar_tid; +fdep_dbg_data_d(14) <= fdec_fdep_is1_vld; +fdep_dbg_data_d(15) <= internal_is2_stall; +fdep_dbg_data_d(16) <= RAW_dep_hit; +fdep_dbg_data_d(17) <= br_sprs_dep_hit; +fdep_dbg_data_d(18) <= sync_dep_hit; +fdep_dbg_data_d(19) <= single_instr_dep_hit; +fdep_dbg_data_d(20) <= WAW_LMQ_dep_hit; +fdep_dbg_data_d(21) <= fdec_fdep_is1_force_ram; +fdep_dbg_data(0 TO 21) <= fdep_dbg_data_l2(0 to 21); +-- Reduce power using act pins to hold state +act_nonvalid <= fdec_fdep_is1_vld or i_afd_is1_instr_v; +-- Latches +is2_vld: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_vld_offset), + scout => sov(is2_vld_offset), + din => is2_vld_d, + dout => is2_vld_l2); + + +is2_instr: tri_rlmreg_p + generic map (width => is2_instr_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_instr_offset to is2_instr_offset + is2_instr_l2'length-1), + scout => sov(is2_instr_offset to is2_instr_offset + is2_instr_l2'length-1), + din => is2_instr_d, + dout => is2_instr_l2); + + +is2_ta_vld: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_ta_vld_offset), + scout => sov(is2_ta_vld_offset), + din => is2_ta_vld_d, + dout => is2_ta_vld_l2); + + +is2_ta: tri_rlmreg_p + generic map (width => is2_ta_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_ta_offset to is2_ta_offset + is2_ta_l2'length-1), + scout => sov(is2_ta_offset to is2_ta_offset + is2_ta_l2'length-1), + din => is2_ta_d, + dout => is2_ta_l2); + + + + +is2_s1_vld: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_s1_vld_offset), + scout => sov(is2_s1_vld_offset), + din => is2_s1_vld_d, + dout => is2_s1_vld_l2); + + +is2_s1: tri_rlmreg_p + generic map (width => is2_s1_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_s1_offset to is2_s1_offset + is2_s1_l2'length-1), + scout => sov(is2_s1_offset to is2_s1_offset + is2_s1_l2'length-1), + din => is2_s1_d, + dout => is2_s1_l2); + + + +is2_s2_vld: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_s2_vld_offset), + scout => sov(is2_s2_vld_offset), + din => is2_s2_vld_d, + dout => is2_s2_vld_l2); + + +is2_s2: tri_rlmreg_p + generic map (width => is2_s2_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_s2_offset to is2_s2_offset + is2_s2_l2'length-1), + scout => sov(is2_s2_offset to is2_s2_offset + is2_s2_l2'length-1), + din => is2_s2_d, + dout => is2_s2_l2); + + + +is2_s3_vld: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_s3_vld_offset), + scout => sov(is2_s3_vld_offset), + din => is2_s3_vld_d, + dout => is2_s3_vld_l2); + + +is2_s3: tri_rlmreg_p + generic map (width => is2_s3_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_s3_offset to is2_s3_offset + is2_s3_l2'length-1), + scout => sov(is2_s3_offset to is2_s3_offset + is2_s3_l2'length-1), + din => is2_s3_d, + dout => is2_s3_l2); + + + + + +is2_is_slowspr: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_is_slowspr_offset), + scout => sov(is2_is_slowspr_offset), + din => is2_is_slowspr_d, + dout => is2_is_slowspr_l2); + + +is2_is_barrier: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_is_barrier_offset), + scout => sov(is2_is_barrier_offset), + din => is2_is_barrier_d, + dout => is2_is_barrier_l2); + + +is2_pred_update: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_pred_update_offset), + scout => sov(is2_pred_update_offset), + din => is2_pred_update_d, + dout => is2_pred_update_l2); + + +is2_pred_taken_cnt: tri_rlmreg_p + generic map (width => is2_pred_taken_cnt_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_pred_taken_cnt_offset to is2_pred_taken_cnt_offset + is2_pred_taken_cnt_l2'length-1), + scout => sov(is2_pred_taken_cnt_offset to is2_pred_taken_cnt_offset + is2_pred_taken_cnt_l2'length-1), + din => is2_pred_taken_cnt_d, + dout => is2_pred_taken_cnt_l2); + + +is2_gshare: tri_rlmreg_p + generic map (width => is2_gshare_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_gshare_offset to is2_gshare_offset + is2_gshare_l2'length-1), + scout => sov(is2_gshare_offset to is2_gshare_offset + is2_gshare_l2'length-1), + din => is2_gshare_d, + dout => is2_gshare_l2); + + +is2_hole_delay: tri_rlmreg_p + generic map (width => is2_hole_delay_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_hole_delay_offset to is2_hole_delay_offset + is2_hole_delay_l2'length-1), + scout => sov(is2_hole_delay_offset to is2_hole_delay_offset + is2_hole_delay_l2'length-1), + din => is2_hole_delay_d, + dout => is2_hole_delay_l2); + +is2_is_ucode: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_is_ucode_offset), + scout => sov(is2_is_ucode_offset), + din => is2_is_ucode_d, + dout => is2_is_ucode_l2); + + +is2_to_ucode: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_to_ucode_offset), + scout => sov(is2_to_ucode_offset), + din => is2_to_ucode_d, + dout => is2_to_ucode_l2); + + +is2_ifar: tri_rlmreg_p + generic map (width => is2_ifar_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_ifar_offset to is2_ifar_offset + is2_ifar_l2'length-1), + scout => sov(is2_ifar_offset to is2_ifar_offset + is2_ifar_l2'length-1), + din => is2_ifar_d, + dout => is2_ifar_l2); + + +is2_error: tri_rlmreg_p + generic map (width => is2_error_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_error_offset to is2_error_offset + is2_error_l2'length-1), + scout => sov(is2_error_offset to is2_error_offset + is2_error_l2'length-1), + din => is2_error_d, + dout => is2_error_l2); +--?generate begin a(IS2, RF0, RF1, EX1, EX2, EX3, EX4); +sp_IS2_d <= sp_d(IS2).i_nobyp_vld & sp_d(IS2).i_vld & sp_d(IS2).ta_vld & sp_d(IS2).ta & + sp_d(IS2).UpdatesLR & sp_d(IS2).UpdatesCR & sp_d(IS2).UpdatesCTR & sp_d(IS2).UpdatesXER & sp_d(IS2).UpdatesMSR & sp_d(IS2).UpdatesSPR & + sp_d(IS2).complete & sp_d(IS2).barrier; +sp_l2(IS2).i_nobyp_vld <= sp_IS2_l2(0); +sp_l2(IS2).i_vld <= sp_IS2_l2(1); +sp_l2(IS2).ta_vld <= sp_IS2_l2(2); +sp_l2(IS2).ta <= sp_IS2_l2(3 to 8); +sp_l2(IS2).updateslr <= sp_IS2_l2(9); +sp_l2(IS2).updatescr <= sp_IS2_l2(10); +sp_l2(IS2).updatesctr <= sp_IS2_l2(11); +sp_l2(IS2).updatesxer <= sp_IS2_l2(12); +sp_l2(IS2).updatesmsr <= sp_IS2_l2(13); +sp_l2(IS2).updatesspr <= sp_IS2_l2(14); +sp_l2(IS2).complete <= sp_IS2_l2(15 to 19); +sp_l2(IS2).barrier <= sp_IS2_l2(20); + + + +sp_IS2: tri_rlmreg_p + generic map (width => 21, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => sp_IS2_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(sp_IS2_offset to sp_IS2_offset + 21-1), + scout => sov(sp_IS2_offset to sp_IS2_offset + 21-1), + din => sp_IS2_d, + dout => sp_IS2_l2); +sp_RF0_d <= sp_d(RF0).i_nobyp_vld & sp_d(RF0).i_vld & sp_d(RF0).ta_vld & sp_d(RF0).ta & + sp_d(RF0).UpdatesLR & sp_d(RF0).UpdatesCR & sp_d(RF0).UpdatesCTR & sp_d(RF0).UpdatesXER & sp_d(RF0).UpdatesMSR & sp_d(RF0).UpdatesSPR & + sp_d(RF0).complete & sp_d(RF0).barrier; +sp_l2(RF0).i_nobyp_vld <= sp_RF0_l2(0); +sp_l2(RF0).i_vld <= sp_RF0_l2(1); +sp_l2(RF0).ta_vld <= sp_RF0_l2(2); +sp_l2(RF0).ta <= sp_RF0_l2(3 to 8); +sp_l2(RF0).updateslr <= sp_RF0_l2(9); +sp_l2(RF0).updatescr <= sp_RF0_l2(10); +sp_l2(RF0).updatesctr <= sp_RF0_l2(11); +sp_l2(RF0).updatesxer <= sp_RF0_l2(12); +sp_l2(RF0).updatesmsr <= sp_RF0_l2(13); +sp_l2(RF0).updatesspr <= sp_RF0_l2(14); +sp_l2(RF0).complete <= sp_RF0_l2(15 to 19); +sp_l2(RF0).barrier <= sp_RF0_l2(20); + + + +sp_RF0: tri_rlmreg_p + generic map (width => 21, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => sp_RF0_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(sp_RF0_offset to sp_RF0_offset + 21-1), + scout => sov(sp_RF0_offset to sp_RF0_offset + 21-1), + din => sp_RF0_d, + dout => sp_RF0_l2); +sp_RF1_d <= sp_d(RF1).i_nobyp_vld & sp_d(RF1).i_vld & sp_d(RF1).ta_vld & sp_d(RF1).ta & + sp_d(RF1).UpdatesLR & sp_d(RF1).UpdatesCR & sp_d(RF1).UpdatesCTR & sp_d(RF1).UpdatesXER & sp_d(RF1).UpdatesMSR & sp_d(RF1).UpdatesSPR & + sp_d(RF1).complete & sp_d(RF1).barrier; +sp_l2(RF1).i_nobyp_vld <= sp_RF1_l2(0); +sp_l2(RF1).i_vld <= sp_RF1_l2(1); +sp_l2(RF1).ta_vld <= sp_RF1_l2(2); +sp_l2(RF1).ta <= sp_RF1_l2(3 to 8); +sp_l2(RF1).updateslr <= sp_RF1_l2(9); +sp_l2(RF1).updatescr <= sp_RF1_l2(10); +sp_l2(RF1).updatesctr <= sp_RF1_l2(11); +sp_l2(RF1).updatesxer <= sp_RF1_l2(12); +sp_l2(RF1).updatesmsr <= sp_RF1_l2(13); +sp_l2(RF1).updatesspr <= sp_RF1_l2(14); +sp_l2(RF1).complete <= sp_RF1_l2(15 to 19); +sp_l2(RF1).barrier <= sp_RF1_l2(20); + + + +sp_RF1: tri_rlmreg_p + generic map (width => 21, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => sp_RF1_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(sp_RF1_offset to sp_RF1_offset + 21-1), + scout => sov(sp_RF1_offset to sp_RF1_offset + 21-1), + din => sp_RF1_d, + dout => sp_RF1_l2); +sp_EX1_d <= sp_d(EX1).i_nobyp_vld & sp_d(EX1).i_vld & sp_d(EX1).ta_vld & sp_d(EX1).ta & + sp_d(EX1).UpdatesLR & sp_d(EX1).UpdatesCR & sp_d(EX1).UpdatesCTR & sp_d(EX1).UpdatesXER & sp_d(EX1).UpdatesMSR & sp_d(EX1).UpdatesSPR & + sp_d(EX1).complete & sp_d(EX1).barrier; +sp_l2(EX1).i_nobyp_vld <= sp_EX1_l2(0); +sp_l2(EX1).i_vld <= sp_EX1_l2(1); +sp_l2(EX1).ta_vld <= sp_EX1_l2(2); +sp_l2(EX1).ta <= sp_EX1_l2(3 to 8); +sp_l2(EX1).updateslr <= sp_EX1_l2(9); +sp_l2(EX1).updatescr <= sp_EX1_l2(10); +sp_l2(EX1).updatesctr <= sp_EX1_l2(11); +sp_l2(EX1).updatesxer <= sp_EX1_l2(12); +sp_l2(EX1).updatesmsr <= sp_EX1_l2(13); +sp_l2(EX1).updatesspr <= sp_EX1_l2(14); +sp_l2(EX1).complete <= sp_EX1_l2(15 to 19); +sp_l2(EX1).barrier <= sp_EX1_l2(20); + + + +sp_EX1: tri_rlmreg_p + generic map (width => 21, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => sp_EX1_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(sp_EX1_offset to sp_EX1_offset + 21-1), + scout => sov(sp_EX1_offset to sp_EX1_offset + 21-1), + din => sp_EX1_d, + dout => sp_EX1_l2); +sp_EX2_d <= sp_d(EX2).i_nobyp_vld & sp_d(EX2).i_vld & sp_d(EX2).ta_vld & sp_d(EX2).ta & + sp_d(EX2).UpdatesLR & sp_d(EX2).UpdatesCR & sp_d(EX2).UpdatesCTR & sp_d(EX2).UpdatesXER & sp_d(EX2).UpdatesMSR & sp_d(EX2).UpdatesSPR & + sp_d(EX2).complete & sp_d(EX2).barrier; +sp_l2(EX2).i_nobyp_vld <= sp_EX2_l2(0); +sp_l2(EX2).i_vld <= sp_EX2_l2(1); +sp_l2(EX2).ta_vld <= sp_EX2_l2(2); +sp_l2(EX2).ta <= sp_EX2_l2(3 to 8); +sp_l2(EX2).updateslr <= sp_EX2_l2(9); +sp_l2(EX2).updatescr <= sp_EX2_l2(10); +sp_l2(EX2).updatesctr <= sp_EX2_l2(11); +sp_l2(EX2).updatesxer <= sp_EX2_l2(12); +sp_l2(EX2).updatesmsr <= sp_EX2_l2(13); +sp_l2(EX2).updatesspr <= sp_EX2_l2(14); +sp_l2(EX2).complete <= sp_EX2_l2(15 to 19); +sp_l2(EX2).barrier <= sp_EX2_l2(20); + + + +sp_EX2: tri_rlmreg_p + generic map (width => 21, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => sp_EX2_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(sp_EX2_offset to sp_EX2_offset + 21-1), + scout => sov(sp_EX2_offset to sp_EX2_offset + 21-1), + din => sp_EX2_d, + dout => sp_EX2_l2); +sp_IS2_act <= sp_l2(IS2).i_nobyp_vld or fdec_fdep_is1_vld; +sp_RF0_act <= sp_l2(RF0).i_nobyp_vld or sp_l2(IS2).i_nobyp_vld; +sp_RF1_act <= sp_l2(RF1).i_nobyp_vld or sp_l2(RF0).i_nobyp_vld; +sp_EX1_act <= sp_l2(EX1).i_nobyp_vld or sp_l2(RF1).i_nobyp_vld; +sp_EX2_act <= sp_l2(EX2).i_nobyp_vld or sp_l2(EX1).i_nobyp_vld; +sp_EX3_act <= sp_ex3_i_nobyp_vld_l2 or sp_l2(EX2).i_nobyp_vld; +sp_EX4_act <= sp_ex4_i_nobyp_vld_l2 or sp_ex3_i_nobyp_vld_l2; +sp_EX5_act <= sp_ex5_i_nobyp_vld_l2 or sp_ex4_i_nobyp_vld_l2; + + +sp_ex3_i_nobyp_vld: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => sp_EX3_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(sp_ex3_i_nobyp_vld_offset), + scout => sov(sp_ex3_i_nobyp_vld_offset), + din => sp_ex3_i_nobyp_vld_d, + dout => sp_ex3_i_nobyp_vld_l2); + + +sp_ex3_barrier: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => sp_EX3_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(sp_ex3_barrier_offset), + scout => sov(sp_ex3_barrier_offset), + din => sp_ex3_barrier_d, + dout => sp_ex3_barrier_l2); + + +sp_ex4_i_nobyp_vld: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => sp_EX4_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(sp_ex4_i_nobyp_vld_offset), + scout => sov(sp_ex4_i_nobyp_vld_offset), + din => sp_ex4_i_nobyp_vld_d, + dout => sp_ex4_i_nobyp_vld_l2); + + +sp_ex4_barrier: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => sp_EX4_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(sp_ex4_barrier_offset), + scout => sov(sp_ex4_barrier_offset), + din => sp_ex4_barrier_d, + dout => sp_ex4_barrier_l2); + + +sp_ex5_i_nobyp_vld: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => sp_EX5_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(sp_ex5_i_nobyp_vld_offset), + scout => sov(sp_ex5_i_nobyp_vld_offset), + din => sp_ex5_i_nobyp_vld_d, + dout => sp_ex5_i_nobyp_vld_l2); + + +sp_ex5_barrier: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => sp_EX5_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(sp_ex5_barrier_offset), + scout => sov(sp_ex5_barrier_offset), + din => sp_ex5_barrier_d, + dout => sp_ex5_barrier_l2); +lm_assign: for i in 0 to lmq_entries-1 generate +sp_LM_d(7*i TO 6+7*i) <= sp_d_LM(i).ta_vld & sp_d_LM(i).ta; +sp_l2_LM(i).ta_vld <= sp_LM_l2(0+7*i); +sp_l2_LM(i).ta <= sp_LM_l2(1+7*i to 6+7*i); +end generate; + + +sp_LM: tri_rlmreg_p + generic map (width => 7*lmq_entries, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(sp_lm_offset to sp_lm_offset + 7*lmq_entries-1), + scout => sov(sp_lm_offset to sp_lm_offset + 7*lmq_entries-1), + din => sp_LM_d, + dout => sp_LM_l2); + + + +barrier: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(barrier_offset), + scout => sov(barrier_offset), + din => barrier_d, + dout => barrier_l2); + + +xu_barrier: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_barrier_offset), + scout => sov(xu_barrier_offset), + din => xu_barrier_d, + dout => xu_barrier_l2); + + +mult_hole_barrier: tri_rlmreg_p + generic map (width => mult_hole_barrier_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => mult_hole_barrier_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(mult_hole_barrier_offset to mult_hole_barrier_offset + mult_hole_barrier_l2'length-1), + scout => sov(mult_hole_barrier_offset to mult_hole_barrier_offset + mult_hole_barrier_l2'length-1), + din => mult_hole_barrier_d, + dout => mult_hole_barrier_l2); + +is2_axu_ld_or_st: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_axu_ld_or_st_offset), + scout => sov(is2_axu_ld_or_st_offset), + din => is2_axu_ld_or_st_d, + dout => is2_axu_ld_or_st_l2); + + +is2_axu_store: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_axu_store_offset), + scout => sov(is2_axu_store_offset), + din => is2_axu_store_d, + dout => is2_axu_store_l2); + + +is2_axu_ldst_indexed: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_axu_ldst_indexed_offset), + scout => sov(is2_axu_ldst_indexed_offset), + din => is2_axu_ldst_indexed_d, + dout => is2_axu_ldst_indexed_l2); + + +is2_axu_ldst_tag: tri_rlmreg_p + generic map (width => is2_axu_ldst_tag_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_axu_ldst_tag_offset to is2_axu_ldst_tag_offset + is2_axu_ldst_tag_l2'length-1), + scout => sov(is2_axu_ldst_tag_offset to is2_axu_ldst_tag_offset + is2_axu_ldst_tag_l2'length-1), + din => is2_axu_ldst_tag_d, + dout => is2_axu_ldst_tag_l2); + + +is2_axu_ldst_size: tri_rlmreg_p + generic map (width => is2_axu_ldst_size_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_axu_ldst_size_offset to is2_axu_ldst_size_offset + is2_axu_ldst_size_l2'length-1), + scout => sov(is2_axu_ldst_size_offset to is2_axu_ldst_size_offset + is2_axu_ldst_size_l2'length-1), + din => is2_axu_ldst_size_d, + dout => is2_axu_ldst_size_l2); + + + +is2_axu_ldst_update: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_axu_ldst_update_offset), + scout => sov(is2_axu_ldst_update_offset), + din => is2_axu_ldst_update_d, + dout => is2_axu_ldst_update_l2); + + +is2_axu_ldst_extpid: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_axu_ldst_extpid_offset), + scout => sov(is2_axu_ldst_extpid_offset), + din => is2_axu_ldst_extpid_d, + dout => is2_axu_ldst_extpid_l2); + + +is2_axu_ldst_forcealign: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_axu_ldst_forcealign_offset), + scout => sov(is2_axu_ldst_forcealign_offset), + din => is2_axu_ldst_forcealign_d, + dout => is2_axu_ldst_forcealign_l2); + + +is2_axu_ldst_forceexcept: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_axu_ldst_forceexcept_offset), + scout => sov(is2_axu_ldst_forceexcept_offset), + din => is2_axu_ldst_forceexcept_d, + dout => is2_axu_ldst_forceexcept_l2); + + +is2_axu_movedp: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_axu_movedp_offset), + scout => sov(is2_axu_movedp_offset), + din => is2_axu_movedp_d, + dout => is2_axu_movedp_l2); + + +is2_axu_mffgpr: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_axu_mffgpr_offset), + scout => sov(is2_axu_mffgpr_offset), + din => is2_axu_mffgpr_d, + dout => is2_axu_mffgpr_l2); + + +is2_axu_mftgpr: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_axu_mftgpr_offset), + scout => sov(is2_axu_mftgpr_offset), + din => is2_axu_mftgpr_d, + dout => is2_axu_mftgpr_l2); + + +is2_axu_instr_type: tri_rlmreg_p + generic map (width => is2_axu_instr_type_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_axu_instr_type_offset to is2_axu_instr_type_offset + is2_axu_instr_type_l2'length-1), + scout => sov(is2_axu_instr_type_offset to is2_axu_instr_type_offset + is2_axu_instr_type_l2'length-1), + din => is2_axu_instr_type_d, + dout => is2_axu_instr_type_l2); + + +is2_match: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_match_offset), + scout => sov(is2_match_offset), + din => is2_match_d, + dout => is2_match_l2); + + +is2_2ucode: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_2ucode_offset), + scout => sov(is2_2ucode_offset), + din => is2_2ucode_d, + dout => is2_2ucode_l2); + + +is2_2ucode_type: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => act_nonvalid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_2ucode_type_offset), + scout => sov(is2_2ucode_type_offset), + din => is2_2ucode_type_d, + dout => is2_2ucode_type_l2); + + + +single_instr_mode: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(single_instr_mode_offset), + scout => sov(single_instr_mode_offset), + din => single_instr_mode_d, + dout => single_instr_mode_l2); +event_bus_enable_d <= pc_iu_event_bus_enable; + + +event_enable_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(event_bus_enable_offset), + scout => sov(event_bus_enable_offset), + din => event_bus_enable_d, + dout => event_bus_enable_q); +trace_bus_enable_d <= pc_iu_trace_bus_enable; + + +trace_enable_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(trace_bus_enable_offset), + scout => sov(trace_bus_enable_offset), + din => trace_bus_enable_d, + dout => trace_bus_enable_q); + + +perf_early: tri_rlmreg_p + generic map (width => perf_early_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => event_bus_enable_q, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(perf_early_offset to perf_early_offset + perf_early_l2'length-1), + scout => sov(perf_early_offset to perf_early_offset + perf_early_l2'length-1), + din => perf_early_d, + dout => perf_early_l2); + + +perf_event: tri_rlmreg_p + generic map (width => perf_event_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => event_bus_enable_q, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(perf_event_offset to perf_event_offset + perf_event_l2'length-1), + scout => sov(perf_event_offset to perf_event_offset + perf_event_l2'length-1), + din => perf_event_d, + dout => perf_event_l2); + + +fdep_dbg_data_reg: tri_rlmreg_p + generic map (width => fdep_dbg_data_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => trace_bus_enable_q, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(fdep_dbg_data_offset to fdep_dbg_data_offset + fdep_dbg_data_l2'length-1), + scout => sov(fdep_dbg_data_offset to fdep_dbg_data_offset + fdep_dbg_data_l2'length-1), + din => fdep_dbg_data_d, + dout => fdep_dbg_data_l2); + +quiesce: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + + scin => siv(quiesce_offset), + scout => sov(quiesce_offset), + din => quiesce_d, + dout => quiesce_l2); + +an_ac_sync_ack_latch: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(an_ac_sync_ack_offset), + scout => sov(an_ac_sync_ack_offset), + din => an_ac_sync_ack_d, + dout => an_ac_sync_ack_l2); + + +xu_iu_membar_tid_latch: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_iu_membar_tid_offset), + scout => sov(xu_iu_membar_tid_offset), + din => xu_iu_membar_tid_d, + dout => xu_iu_membar_tid_l2); + + +xu_iu_multdiv_done_latch: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_iu_multdiv_done_offset), + scout => sov(xu_iu_multdiv_done_offset), + din => xu_iu_multdiv_done_d, + dout => xu_iu_multdiv_done_l2); + + +mm_iu_barrier_done_latch: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(mm_iu_barrier_done_offset), + scout => sov(mm_iu_barrier_done_offset), + din => mm_iu_barrier_done_d, + dout => mm_iu_barrier_done_l2); + + +spr_fdep_ll_hold_latch: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(spr_fdep_ll_hold_offset), + scout => sov(spr_fdep_ll_hold_offset), + din => spr_fdep_ll_hold_d, + dout => spr_fdep_ll_hold_l2); + + +en_dcr_latch: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(en_dcr_offset), + scout => sov(en_dcr_offset), + din => en_dcr_d, + dout => en_dcr_l2); + + +spare_latch: tri_rlmreg_p + generic map (width => spare_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(spare_offset to spare_offset + spare_l2'length-1), + scout => sov(spare_offset to spare_offset + spare_l2'length-1), + din => spare_l2, + dout => spare_l2); +-------------------------------------------------------------------------------------------------------------------------------------------------------- +-- Instruction routed to issue +-------------------------------------------------------------------------------------------------------------------------------------------------------- +fdep_fiss_is2_instr <= is2_instr_l2; +fdep_fiss_is2_ta_vld <= is2_ta_vld_l2; +fdep_fiss_is2_ta <= is2_ta_l2; +fdep_fiss_is2_s1_vld <= is2_s1_vld_l2; +fdep_fiss_is2_s1 <= is2_s1_l2; +fdep_fiss_is2_s2_vld <= is2_s2_vld_l2; +fdep_fiss_is2_s2 <= is2_s2_l2; +fdep_fiss_is2_s3_vld <= is2_s3_vld_l2; +fdep_fiss_is2_s3 <= is2_s3_l2; +fdep_fiss_is2_pred_update <= is2_pred_update_l2; +fdep_fiss_is2_pred_taken_cnt <= is2_pred_taken_cnt_l2; +fdep_fiss_is2_gshare <= is2_gshare_l2; +fdep_fiss_is2_ifar <= is2_ifar_l2; +fdep_fiss_is2_error <= is2_error_l2; +fdep_fiss_is2_axu_ld_or_st <= is2_axu_ld_or_st_L2; +fdep_fiss_is2_axu_store <= is2_axu_store_L2; +fdep_fiss_is2_axu_ldst_indexed <= is2_axu_ldst_indexed_L2; +fdep_fiss_is2_axu_ldst_tag <= is2_axu_ldst_tag_L2; +fdep_fiss_is2_axu_ldst_size <= is2_axu_ldst_size_L2; +fdep_fiss_is2_axu_ldst_update <= is2_axu_ldst_update_L2; +fdep_fiss_is2_axu_ldst_extpid <= is2_axu_ldst_extpid_L2; +fdep_fiss_is2_axu_ldst_forcealign <= is2_axu_ldst_forcealign_L2; +fdep_fiss_is2_axu_ldst_forceexcept <= is2_axu_ldst_forceexcept_L2; +fdep_fiss_is2_axu_mftgpr <= is2_axu_mftgpr_L2; +fdep_fiss_is2_axu_mffgpr <= is2_axu_mffgpr_L2; +fdep_fiss_is2_axu_movedp <= is2_axu_movedp_L2; +fdep_fiss_is2_axu_instr_type <= is2_axu_instr_type_L2; +fdep_fiss_is2_match <= is2_match_L2; +fdep_fiss_is2_2ucode <= is2_2ucode_L2; +fdep_fiss_is2_2ucode_type <= is2_2ucode_type_L2; +fdep_fiss_is2_hole_delay <= is2_hole_delay_L2; +fdep_fiss_is2_to_ucode <= is2_to_ucode_L2; +fdep_fiss_is2_is_ucode <= is2_is_ucode_L2; +fdep_fiss_is2early_vld <= fdec_fdep_is1_vld; +fdep_fiss_is1_xu_dep_hit_b <= fxu_dep_hit_b; +----------------------------------------------------------------------- +-- Scan +----------------------------------------------------------------------- +siv(0 TO scan_right) <= sov(1 to scan_right) & scan_in; +scan_out <= sov(0); +END IUQ_FXU_DEP; diff --git a/rel/src/vhdl/work/iuq_fxu_dep_cmp.vhdl b/rel/src/vhdl/work/iuq_fxu_dep_cmp.vhdl new file mode 100644 index 0000000..cc29558 --- /dev/null +++ b/rel/src/vhdl/work/iuq_fxu_dep_cmp.vhdl @@ -0,0 +1,366 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; + use ieee.std_logic_1164.all ; +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + +entity iuq_fxu_dep_cmp is + +port( + is1_v : in std_ulogic; + is2_v : in std_ulogic; + rf0_v : in std_ulogic; + rf1_v : in std_ulogic; + ex1_v : in std_ulogic; + ex2_v : in std_ulogic; + lm0_v : in std_ulogic; + lm1_v : in std_ulogic; + lm2_v : in std_ulogic; + lm3_v : in std_ulogic; + lm4_v : in std_ulogic; + lm5_v : in std_ulogic; + lm6_v : in std_ulogic; + lm7_v : in std_ulogic; + + is1_ad : in std_ulogic_vector(0 to 5); + is2_ad : in std_ulogic_vector(0 to 5); + rf0_ad : in std_ulogic_vector(0 to 5); + rf1_ad : in std_ulogic_vector(0 to 5); + ex1_ad : in std_ulogic_vector(0 to 5); + ex2_ad : in std_ulogic_vector(0 to 5); + lm0_ad : in std_ulogic_vector(0 to 5); + lm1_ad : in std_ulogic_vector(0 to 5); + lm2_ad : in std_ulogic_vector(0 to 5); + lm3_ad : in std_ulogic_vector(0 to 5); + lm4_ad : in std_ulogic_vector(0 to 5); + lm5_ad : in std_ulogic_vector(0 to 5); + lm6_ad : in std_ulogic_vector(0 to 5); + lm7_ad : in std_ulogic_vector(0 to 5); + + ad_hit_b : out std_ulogic + + ); + + + +end iuq_fxu_dep_cmp; +------------------------------------------------------------------------------------------------------------------------------------ + +architecture iuq_fxu_dep_cmp of iuq_fxu_dep_cmp is + +signal lm0_ad_buf, lm0_ad_buf_b :std_ulogic_vector(0 to 5); +signal lm1_ad_buf, lm1_ad_buf_b :std_ulogic_vector(0 to 5); +signal lm2_ad_buf, lm2_ad_buf_b :std_ulogic_vector(0 to 5); +signal lm3_ad_buf, lm3_ad_buf_b :std_ulogic_vector(0 to 5); +signal lm4_ad_buf, lm4_ad_buf_b :std_ulogic_vector(0 to 5); +signal lm5_ad_buf, lm5_ad_buf_b :std_ulogic_vector(0 to 5); +signal lm6_ad_buf, lm6_ad_buf_b :std_ulogic_vector(0 to 5); +signal lm7_ad_buf, lm7_ad_buf_b :std_ulogic_vector(0 to 5); +signal ex2_ad_buf, ex2_ad_buf_b :std_ulogic_vector(0 to 5); +signal ex1_ad_buf, ex1_ad_buf_b :std_ulogic_vector(0 to 5); +signal rf1_ad_buf, rf1_ad_buf_b :std_ulogic_vector(0 to 5); +signal rf0_ad_buf, rf0_ad_buf_b :std_ulogic_vector(0 to 5); +signal is2_ad_buf, is2_ad_buf_b :std_ulogic_vector(0 to 5); +signal is1_ad_buf0, is1_ad_buf0_b :std_ulogic_vector(0 to 5); +signal is1_ad_buf1, is1_ad_buf1_b :std_ulogic_vector(0 to 5); +signal is1_ad_buf2, is1_ad_buf2_b :std_ulogic_vector(0 to 5); + +signal a_eq_lm0_x :std_ulogic_vector(0 to 5); +signal a_eq_lm0_01_b , a_eq_lm0_23_b , a_eq_lm0_45_b :std_ulogic; +signal a_eq_lm0_u ,a_eq_lm0_v , a_eq_lm0_b :std_ulogic; + +signal a_eq_lm1_x :std_ulogic_vector(0 to 5); +signal a_eq_lm1_01_b , a_eq_lm1_23_b , a_eq_lm1_45_b :std_ulogic; +signal a_eq_lm1_u ,a_eq_lm1_v , a_eq_lm1_b :std_ulogic; + +signal a_eq_lm2_x :std_ulogic_vector(0 to 5); +signal a_eq_lm2_01_b , a_eq_lm2_23_b , a_eq_lm2_45_b :std_ulogic; +signal a_eq_lm2_u ,a_eq_lm2_v , a_eq_lm2_b :std_ulogic; + +signal a_eq_lm3_x :std_ulogic_vector(0 to 5); +signal a_eq_lm3_01_b , a_eq_lm3_23_b , a_eq_lm3_45_b :std_ulogic; +signal a_eq_lm3_u ,a_eq_lm3_v , a_eq_lm3_b :std_ulogic; + +signal a_eq_lm4_x :std_ulogic_vector(0 to 5); +signal a_eq_lm4_01_b , a_eq_lm4_23_b , a_eq_lm4_45_b :std_ulogic; +signal a_eq_lm4_u ,a_eq_lm4_v , a_eq_lm4_b :std_ulogic; + +signal a_eq_lm5_x :std_ulogic_vector(0 to 5); +signal a_eq_lm5_01_b , a_eq_lm5_23_b , a_eq_lm5_45_b :std_ulogic; +signal a_eq_lm5_u ,a_eq_lm5_v , a_eq_lm5_b :std_ulogic; + +signal a_eq_lm6_x :std_ulogic_vector(0 to 5); +signal a_eq_lm6_01_b , a_eq_lm6_23_b , a_eq_lm6_45_b :std_ulogic; +signal a_eq_lm6_u ,a_eq_lm6_v , a_eq_lm6_b :std_ulogic; + +signal a_eq_lm7_x :std_ulogic_vector(0 to 5); +signal a_eq_lm7_01_b , a_eq_lm7_23_b , a_eq_lm7_45_b :std_ulogic; +signal a_eq_lm7_u ,a_eq_lm7_v , a_eq_lm7_b :std_ulogic; + +signal a_eq_ex2_x :std_ulogic_vector(0 to 5); +signal a_eq_ex2_01_b , a_eq_ex2_23_b , a_eq_ex2_45_b :std_ulogic; +signal a_eq_ex2_u ,a_eq_ex2_v , a_eq_ex2_b :std_ulogic; + +signal a_eq_ex1_x :std_ulogic_vector(0 to 5); +signal a_eq_ex1_01_b , a_eq_ex1_23_b , a_eq_ex1_45_b :std_ulogic; +signal a_eq_ex1_u ,a_eq_ex1_v , a_eq_ex1_b :std_ulogic; + +signal a_eq_rf1_x :std_ulogic_vector(0 to 5); +signal a_eq_rf1_01_b , a_eq_rf1_23_b , a_eq_rf1_45_b :std_ulogic; +signal a_eq_rf1_u ,a_eq_rf1_v , a_eq_rf1_b :std_ulogic; + +signal a_eq_rf0_x :std_ulogic_vector(0 to 5); +signal a_eq_rf0_01_b , a_eq_rf0_23_b , a_eq_rf0_45_b :std_ulogic; +signal a_eq_rf0_u ,a_eq_rf0_v , a_eq_rf0_b :std_ulogic; + +signal a_eq_is2_x :std_ulogic_vector(0 to 5); +signal a_eq_is2_01_b , a_eq_is2_23_b , a_eq_is2_45_b :std_ulogic; +signal a_eq_is2_u ,a_eq_is2_v , a_eq_is2_b :std_ulogic; + +signal a_or_1_1 , a_or_1_2 , a_or_1_3 , a_or_1_4 :std_ulogic; +signal a_or_1_5 , a_or_1_6 :std_ulogic; +signal a_or_2_1_b , a_or_2_2_b , a_or_2_3_b :std_ulogic; +signal a_or_3_1 , a_or_4_b :std_ulogic; + + +signal a_group_en :std_ulogic; + +signal lm0_a_cmp_en :std_ulogic; +signal lm1_a_cmp_en :std_ulogic; +signal lm2_a_cmp_en :std_ulogic; +signal lm3_a_cmp_en :std_ulogic; +signal lm4_a_cmp_en :std_ulogic; +signal lm5_a_cmp_en :std_ulogic; +signal lm6_a_cmp_en :std_ulogic; +signal lm7_a_cmp_en :std_ulogic; + +signal is2_a_cmp_en :std_ulogic; +signal rf0_a_cmp_en :std_ulogic; +signal rf1_a_cmp_en :std_ulogic; +signal ex1_a_cmp_en :std_ulogic; +signal ex2_a_cmp_en :std_ulogic; + + + + + +begin + + + +-- address buffering + +ucmp_lm0adbufb: lm0_ad_buf_b(0 to 5) <= not lm0_ad(0 to 5); +ucmp_lm1adbufb: lm1_ad_buf_b(0 to 5) <= not lm1_ad(0 to 5); +ucmp_lm2adbufb: lm2_ad_buf_b(0 to 5) <= not lm2_ad(0 to 5); +ucmp_lm3adbufb: lm3_ad_buf_b(0 to 5) <= not lm3_ad(0 to 5); +ucmp_lm4adbufb: lm4_ad_buf_b(0 to 5) <= not lm4_ad(0 to 5); +ucmp_lm5adbufb: lm5_ad_buf_b(0 to 5) <= not lm5_ad(0 to 5); +ucmp_lm6adbufb: lm6_ad_buf_b(0 to 5) <= not lm6_ad(0 to 5); +ucmp_lm7adbufb: lm7_ad_buf_b(0 to 5) <= not lm7_ad(0 to 5); +ucmp_ex2adbufb: ex2_ad_buf_b(0 to 5) <= not ex2_ad(0 to 5); +ucmp_ex1adbufb: ex1_ad_buf_b(0 to 5) <= not ex1_ad(0 to 5); +ucmp_rf1adbufb: rf1_ad_buf_b(0 to 5) <= not rf1_ad(0 to 5); +ucmp_rf0adbufb: rf0_ad_buf_b(0 to 5) <= not rf0_ad(0 to 5); +ucmp_is2adbufb: is2_ad_buf_b(0 to 5) <= not is2_ad(0 to 5); +ucmp_is1adbuf0b: is1_ad_buf0_b(0 to 5) <= not is1_ad(0 to 5); +ucmp_is1adbuf1b: is1_ad_buf1_b(0 to 5) <= not is1_ad(0 to 5); +ucmp_is1adbuf2b: is1_ad_buf2_b(0 to 5) <= not is1_ad(0 to 5); + +ucmp_lm0adbuf: lm0_ad_buf(0 to 5) <= not lm0_ad_buf_b(0 to 5); +ucmp_lm1adbuf: lm1_ad_buf(0 to 5) <= not lm1_ad_buf_b(0 to 5); +ucmp_lm2adbuf: lm2_ad_buf(0 to 5) <= not lm2_ad_buf_b(0 to 5); +ucmp_lm3adbuf: lm3_ad_buf(0 to 5) <= not lm3_ad_buf_b(0 to 5); +ucmp_lm4adbuf: lm4_ad_buf(0 to 5) <= not lm4_ad_buf_b(0 to 5); +ucmp_lm5adbuf: lm5_ad_buf(0 to 5) <= not lm5_ad_buf_b(0 to 5); +ucmp_lm6adbuf: lm6_ad_buf(0 to 5) <= not lm6_ad_buf_b(0 to 5); +ucmp_lm7adbuf: lm7_ad_buf(0 to 5) <= not lm7_ad_buf_b(0 to 5); +ucmp_ex2adbuf: ex2_ad_buf(0 to 5) <= not ex2_ad_buf_b(0 to 5); +ucmp_ex1adbuf: ex1_ad_buf(0 to 5) <= not ex1_ad_buf_b(0 to 5); +ucmp_rf1adbuf: rf1_ad_buf(0 to 5) <= not rf1_ad_buf_b(0 to 5); +ucmp_rf0adbuf: rf0_ad_buf(0 to 5) <= not rf0_ad_buf_b(0 to 5); +ucmp_is2adbuf: is2_ad_buf(0 to 5) <= not is2_ad_buf_b(0 to 5); +ucmp_is1adbuf0: is1_ad_buf0(0 to 5) <= not is1_ad_buf0_b(0 to 5); +ucmp_is1adbuf1: is1_ad_buf1(0 to 5) <= not is1_ad_buf1_b(0 to 5); +ucmp_is1adbuf2: is1_ad_buf2(0 to 5) <= not is1_ad_buf2_b(0 to 5); + + +-- address compare + +ucmp_aeqis2_x: a_eq_is2_x(0 to 5) <= not( is2_ad_buf(0 to 5) xor is1_ad_buf0(0 to 5) ); +ucmp_aeqis2_01: a_eq_is2_01_b <= not( a_eq_is2_x(0) and a_eq_is2_x(1) ); +ucmp_aeqis2_23: a_eq_is2_23_b <= not( a_eq_is2_x(2) and a_eq_is2_x(3) ); +ucmp_aeqis2_45: a_eq_is2_45_b <= not( a_eq_is2_x(4) and a_eq_is2_x(5) ); +ucmp_aeqis2_u: a_eq_is2_u <= not( a_eq_is2_01_b or a_eq_is2_23_b ); +ucmp_aeqis2_w: a_eq_is2_v <= not( a_eq_is2_45_b ); +ucmp_aeqis2: a_eq_is2_b <= not( a_eq_is2_u and a_eq_is2_v and is2_a_cmp_en ); + +ucmp_aeqrf0_x: a_eq_rf0_x(0 to 5) <= not( rf0_ad_buf(0 to 5) xor is1_ad_buf0(0 to 5) ); +ucmp_aeqrf0_01: a_eq_rf0_01_b <= not( a_eq_rf0_x(0) and a_eq_rf0_x(1) ); +ucmp_aeqrf0_23: a_eq_rf0_23_b <= not( a_eq_rf0_x(2) and a_eq_rf0_x(3) ); +ucmp_aeqrf0_45: a_eq_rf0_45_b <= not( a_eq_rf0_x(4) and a_eq_rf0_x(5) ); +ucmp_aeqrf0_u: a_eq_rf0_u <= not( a_eq_rf0_01_b or a_eq_rf0_23_b ); +ucmp_aeqrf0_w: a_eq_rf0_v <= not( a_eq_rf0_45_b ); +ucmp_aeqrf0: a_eq_rf0_b <= not( a_eq_rf0_u and a_eq_rf0_v and rf0_a_cmp_en ); + +ucmp_aeqrf1_x: a_eq_rf1_x(0 to 5) <= not( rf1_ad_buf(0 to 5) xor is1_ad_buf0(0 to 5) ); +ucmp_aeqrf1_01: a_eq_rf1_01_b <= not( a_eq_rf1_x(0) and a_eq_rf1_x(1) ); +ucmp_aeqrf1_23: a_eq_rf1_23_b <= not( a_eq_rf1_x(2) and a_eq_rf1_x(3) ); +ucmp_aeqrf1_45: a_eq_rf1_45_b <= not( a_eq_rf1_x(4) and a_eq_rf1_x(5) ); +ucmp_aeqrf1_u: a_eq_rf1_u <= not( a_eq_rf1_01_b or a_eq_rf1_23_b ); +ucmp_aeqrf1_w: a_eq_rf1_v <= not( a_eq_rf1_45_b ); +ucmp_aeqrf1: a_eq_rf1_b <= not( a_eq_rf1_u and a_eq_rf1_v and rf1_a_cmp_en ); + +ucmp_aeqex1_x: a_eq_ex1_x(0 to 5) <= not( ex1_ad_buf(0 to 5) xor is1_ad_buf0(0 to 5) ); +ucmp_aeqex1_01: a_eq_ex1_01_b <= not( a_eq_ex1_x(0) and a_eq_ex1_x(1) ); +ucmp_aeqex1_23: a_eq_ex1_23_b <= not( a_eq_ex1_x(2) and a_eq_ex1_x(3) ); +ucmp_aeqex1_45: a_eq_ex1_45_b <= not( a_eq_ex1_x(4) and a_eq_ex1_x(5) ); +ucmp_aeqex1_u: a_eq_ex1_u <= not( a_eq_ex1_01_b or a_eq_ex1_23_b ); +ucmp_aeqex1_w: a_eq_ex1_v <= not( a_eq_ex1_45_b ); +ucmp_aeqex1: a_eq_ex1_b <= not( a_eq_ex1_u and a_eq_ex1_v and ex1_a_cmp_en ); + +ucmp_aeqex2_x: a_eq_ex2_x(0 to 5) <= not( ex2_ad_buf(0 to 5) xor is1_ad_buf0(0 to 5) ); +ucmp_aeqex2_01: a_eq_ex2_01_b <= not( a_eq_ex2_x(0) and a_eq_ex2_x(1) ); +ucmp_aeqex2_23: a_eq_ex2_23_b <= not( a_eq_ex2_x(2) and a_eq_ex2_x(3) ); +ucmp_aeqex2_45: a_eq_ex2_45_b <= not( a_eq_ex2_x(4) and a_eq_ex2_x(5) ); +ucmp_aeqex2_u: a_eq_ex2_u <= not( a_eq_ex2_01_b or a_eq_ex2_23_b ); +ucmp_aeqex2_w: a_eq_ex2_v <= not( a_eq_ex2_45_b ); +ucmp_aeqex2: a_eq_ex2_b <= not( a_eq_ex2_u and a_eq_ex2_v and ex2_a_cmp_en ); + +ucmp_aeqlm0_x: a_eq_lm0_x(0 to 5) <= not( lm0_ad_buf(0 to 5) xor is1_ad_buf1(0 to 5) ); +ucmp_aeqlm0_01: a_eq_lm0_01_b <= not( a_eq_lm0_x(0) and a_eq_lm0_x(1) ); +ucmp_aeqlm0_23: a_eq_lm0_23_b <= not( a_eq_lm0_x(2) and a_eq_lm0_x(3) ); +ucmp_aeqlm0_45: a_eq_lm0_45_b <= not( a_eq_lm0_x(4) and a_eq_lm0_x(5) ); +ucmp_aeqlm0_u: a_eq_lm0_u <= not( a_eq_lm0_01_b or a_eq_lm0_23_b ); +ucmp_aeqlm0_w: a_eq_lm0_v <= not( a_eq_lm0_45_b ); +ucmp_aeqlm0: a_eq_lm0_b <= not( a_eq_lm0_u and a_eq_lm0_v and lm0_a_cmp_en ); + +ucmp_aeqlm1_x: a_eq_lm1_x(0 to 5) <= not( lm1_ad_buf(0 to 5) xor is1_ad_buf1(0 to 5) ); +ucmp_aeqlm1_01: a_eq_lm1_01_b <= not( a_eq_lm1_x(0) and a_eq_lm1_x(1) ); +ucmp_aeqlm1_23: a_eq_lm1_23_b <= not( a_eq_lm1_x(2) and a_eq_lm1_x(3) ); +ucmp_aeqlm1_45: a_eq_lm1_45_b <= not( a_eq_lm1_x(4) and a_eq_lm1_x(5) ); +ucmp_aeqlm1_u: a_eq_lm1_u <= not( a_eq_lm1_01_b or a_eq_lm1_23_b ); +ucmp_aeqlm1_w: a_eq_lm1_v <= not( a_eq_lm1_45_b ); +ucmp_aeqlm1: a_eq_lm1_b <= not( a_eq_lm1_u and a_eq_lm1_v and lm1_a_cmp_en ); + +ucmp_aeqlm2_x: a_eq_lm2_x(0 to 5) <= not( lm2_ad_buf(0 to 5) xor is1_ad_buf1(0 to 5) ); +ucmp_aeqlm2_01: a_eq_lm2_01_b <= not( a_eq_lm2_x(0) and a_eq_lm2_x(1) ); +ucmp_aeqlm2_23: a_eq_lm2_23_b <= not( a_eq_lm2_x(2) and a_eq_lm2_x(3) ); +ucmp_aeqlm2_45: a_eq_lm2_45_b <= not( a_eq_lm2_x(4) and a_eq_lm2_x(5) ); +ucmp_aeqlm2_u: a_eq_lm2_u <= not( a_eq_lm2_01_b or a_eq_lm2_23_b ); +ucmp_aeqlm2_w: a_eq_lm2_v <= not( a_eq_lm2_45_b ); +ucmp_aeqlm2: a_eq_lm2_b <= not( a_eq_lm2_u and a_eq_lm2_v and lm2_a_cmp_en ); + +ucmp_aeqlm3_x: a_eq_lm3_x(0 to 5) <= not( lm3_ad_buf(0 to 5) xor is1_ad_buf1(0 to 5) ); +ucmp_aeqlm3_01: a_eq_lm3_01_b <= not( a_eq_lm3_x(0) and a_eq_lm3_x(1) ); +ucmp_aeqlm3_23: a_eq_lm3_23_b <= not( a_eq_lm3_x(2) and a_eq_lm3_x(3) ); +ucmp_aeqlm3_45: a_eq_lm3_45_b <= not( a_eq_lm3_x(4) and a_eq_lm3_x(5) ); +ucmp_aeqlm3_u: a_eq_lm3_u <= not( a_eq_lm3_01_b or a_eq_lm3_23_b ); +ucmp_aeqlm3_w: a_eq_lm3_v <= not( a_eq_lm3_45_b ); +ucmp_aeqlm3: a_eq_lm3_b <= not( a_eq_lm3_u and a_eq_lm3_v and lm3_a_cmp_en ); + +ucmp_aeqlm4_x: a_eq_lm4_x(0 to 5) <= not( lm4_ad_buf(0 to 5) xor is1_ad_buf2(0 to 5) ); +ucmp_aeqlm4_01: a_eq_lm4_01_b <= not( a_eq_lm4_x(0) and a_eq_lm4_x(1) ); +ucmp_aeqlm4_23: a_eq_lm4_23_b <= not( a_eq_lm4_x(2) and a_eq_lm4_x(3) ); +ucmp_aeqlm4_45: a_eq_lm4_45_b <= not( a_eq_lm4_x(4) and a_eq_lm4_x(5) ); +ucmp_aeqlm4_u: a_eq_lm4_u <= not( a_eq_lm4_01_b or a_eq_lm4_23_b ); +ucmp_aeqlm4_w: a_eq_lm4_v <= not( a_eq_lm4_45_b ); +ucmp_aeqlm4: a_eq_lm4_b <= not( a_eq_lm4_u and a_eq_lm4_v and lm4_a_cmp_en ); + +ucmp_aeqlm5_x: a_eq_lm5_x(0 to 5) <= not( lm5_ad_buf(0 to 5) xor is1_ad_buf2(0 to 5) ); +ucmp_aeqlm5_01: a_eq_lm5_01_b <= not( a_eq_lm5_x(0) and a_eq_lm5_x(1) ); +ucmp_aeqlm5_23: a_eq_lm5_23_b <= not( a_eq_lm5_x(2) and a_eq_lm5_x(3) ); +ucmp_aeqlm5_45: a_eq_lm5_45_b <= not( a_eq_lm5_x(4) and a_eq_lm5_x(5) ); +ucmp_aeqlm5_u: a_eq_lm5_u <= not( a_eq_lm5_01_b or a_eq_lm5_23_b ); +ucmp_aeqlm5_w: a_eq_lm5_v <= not( a_eq_lm5_45_b ); +ucmp_aeqlm5: a_eq_lm5_b <= not( a_eq_lm5_u and a_eq_lm5_v and lm5_a_cmp_en ); + +ucmp_aeqlm6_x: a_eq_lm6_x(0 to 5) <= not( lm6_ad_buf(0 to 5) xor is1_ad_buf2(0 to 5) ); +ucmp_aeqlm6_01: a_eq_lm6_01_b <= not( a_eq_lm6_x(0) and a_eq_lm6_x(1) ); +ucmp_aeqlm6_23: a_eq_lm6_23_b <= not( a_eq_lm6_x(2) and a_eq_lm6_x(3) ); +ucmp_aeqlm6_45: a_eq_lm6_45_b <= not( a_eq_lm6_x(4) and a_eq_lm6_x(5) ); +ucmp_aeqlm6_u: a_eq_lm6_u <= not( a_eq_lm6_01_b or a_eq_lm6_23_b ); +ucmp_aeqlm6_w: a_eq_lm6_v <= not( a_eq_lm6_45_b ); +ucmp_aeqlm6: a_eq_lm6_b <= not( a_eq_lm6_u and a_eq_lm6_v and lm6_a_cmp_en ); + +ucmp_aeqlm7_x: a_eq_lm7_x(0 to 5) <= not( lm7_ad_buf(0 to 5) xor is1_ad_buf2(0 to 5) ); +ucmp_aeqlm7_01: a_eq_lm7_01_b <= not( a_eq_lm7_x(0) and a_eq_lm7_x(1) ); +ucmp_aeqlm7_23: a_eq_lm7_23_b <= not( a_eq_lm7_x(2) and a_eq_lm7_x(3) ); +ucmp_aeqlm7_45: a_eq_lm7_45_b <= not( a_eq_lm7_x(4) and a_eq_lm7_x(5) ); +ucmp_aeqlm7_u: a_eq_lm7_u <= not( a_eq_lm7_01_b or a_eq_lm7_23_b ); +ucmp_aeqlm7_w: a_eq_lm7_v <= not( a_eq_lm7_45_b ); +ucmp_aeqlm7: a_eq_lm7_b <= not( a_eq_lm7_u and a_eq_lm7_v and lm7_a_cmp_en ); + + +-- or compares together + +ucmp_aor11: a_or_1_1 <= not( a_eq_lm0_b and a_eq_lm1_b ); +ucmp_aor12: a_or_1_2 <= not( a_eq_lm2_b and a_eq_lm3_b ); +ucmp_aor13: a_or_1_3 <= not( a_eq_lm4_b and a_eq_lm5_b ); +ucmp_aor14: a_or_1_4 <= not( a_eq_lm6_b and a_eq_lm7_b ); +ucmp_aor15: a_or_1_5 <= not( a_eq_ex2_b and a_eq_ex1_b ); +ucmp_aor16: a_or_1_6 <= not( a_eq_rf1_b and a_eq_rf0_b and a_eq_is2_b ); + +ucmp_aor21: a_or_2_1_b <= not( a_or_1_1 or a_or_1_2 ); +ucmp_aor22: a_or_2_2_b <= not( a_or_1_3 or a_or_1_4 ); +ucmp_aor23: a_or_2_3_b <= not( a_or_1_5 or a_or_1_6 ); + +ucmp_aor31: a_or_3_1 <= not( a_or_2_1_b and a_or_2_2_b and a_or_2_3_b ); + +ucmp_aor4: a_or_4_b <= not( a_group_en and a_or_3_1); + + + +-- compare enables + +a_group_en <= is1_v; + +lm0_a_cmp_en <= lm0_v; +lm1_a_cmp_en <= lm1_v; +lm2_a_cmp_en <= lm2_v; +lm3_a_cmp_en <= lm3_v; +lm4_a_cmp_en <= lm4_v; +lm5_a_cmp_en <= lm5_v; +lm6_a_cmp_en <= lm6_v; +lm7_a_cmp_en <= lm7_v; +is2_a_cmp_en <= is2_v; +rf0_a_cmp_en <= rf0_v; +rf1_a_cmp_en <= rf1_v; +ex1_a_cmp_en <= ex1_v; +ex2_a_cmp_en <= ex2_v; + +ad_hit_b <= a_or_4_b; + + +end iuq_fxu_dep_cmp; diff --git a/rel/src/vhdl/work/iuq_fxu_issue.vhdl b/rel/src/vhdl/work/iuq_fxu_issue.vhdl new file mode 100644 index 0000000..2b56b61 --- /dev/null +++ b/rel/src/vhdl/work/iuq_fxu_issue.vhdl @@ -0,0 +1,2209 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee, ibm; +use ieee.std_logic_1164.all; +use ibm.std_ulogic_unsigned.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +library support; +use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; +library work; +use work.iuq_pkg.all; + +entity iuq_fxu_issue is + generic(expand_type : integer := 2 ); +port(vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + pc_iu_sg_2 : in std_ulogic; + pc_iu_func_sl_thold_2 : in std_ulogic; + clkoff_b : in std_ulogic; + an_ac_scan_dis_dc_b : in std_ulogic; + tc_ac_ccflush_dc : in std_ulogic; + delay_lclkr : in std_ulogic; + mpw1_b : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + fiss_dbg_data : out std_ulogic_vector(0 to 87); + pc_iu_trace_bus_enable : in std_ulogic; + + pc_iu_event_bus_enable : in std_ulogic; + fiss_perf_event_t0 : out std_ulogic_vector(0 to 7); + fiss_perf_event_t1 : out std_ulogic_vector(0 to 7); + fiss_perf_event_t2 : out std_ulogic_vector(0 to 7); + fiss_perf_event_t3 : out std_ulogic_vector(0 to 7); + + xu_iu_need_hole : in std_ulogic; + xu_iu_xucr0_rel : in std_ulogic; + + an_ac_reld_data_vld : in std_ulogic; + an_ac_reld_core_tag : in std_ulogic_vector(1 to 4); + an_ac_reld_ditc : in std_ulogic; + an_ac_reld_data_coming : in std_ulogic; + an_ac_back_inv : in std_ulogic; + an_ac_back_inv_target : in std_ulogic; + + fiss_uc_is2_ucode_vld : out std_ulogic; + + + fdep_fiss_t0_is2_instr : in std_ulogic_vector(0 to 31); + fdep_fiss_t0_is2_ta_vld : in std_ulogic; + fdep_fiss_t0_is2_ta : in std_ulogic_vector(0 to 5); + fdep_fiss_t0_is2_s1_vld : in std_ulogic; + fdep_fiss_t0_is2_s1 : in std_ulogic_vector(0 to 5); + fdep_fiss_t0_is2_s2_vld : in std_ulogic; + fdep_fiss_t0_is2_s2 : in std_ulogic_vector(0 to 5); + fdep_fiss_t0_is2_s3_vld : in std_ulogic; + fdep_fiss_t0_is2_s3 : in std_ulogic_vector(0 to 5); + fdep_fiss_t0_is2_pred_update : in std_ulogic; + fdep_fiss_t0_is2_pred_taken_cnt : in std_ulogic_vector(0 to 1); + fdep_fiss_t0_is2_gshare : in std_ulogic_vector(0 to 3); + fdep_fiss_t0_is2_ifar : in eff_ifar; + fdep_fiss_t0_is2_error : in std_ulogic_vector(0 to 2); + fdep_fiss_t0_is2_axu_ld_or_st : in std_ulogic; + fdep_fiss_t0_is2_axu_store : in std_ulogic; + fdep_fiss_t0_is2_axu_ldst_indexed : in std_ulogic; + fdep_fiss_t0_is2_axu_ldst_tag : in std_ulogic_vector(0 to 8); + fdep_fiss_t0_is2_axu_ldst_size : in std_ulogic_vector(0 to 5); + fdep_fiss_t0_is2_axu_ldst_update : in std_ulogic; + fdep_fiss_t0_is2_axu_ldst_extpid : in std_ulogic; + fdep_fiss_t0_is2_axu_ldst_forcealign : in std_ulogic; + fdep_fiss_t0_is2_axu_ldst_forceexcept : in std_ulogic; + fdep_fiss_t0_is2_axu_mftgpr : in std_ulogic; + fdep_fiss_t0_is2_axu_mffgpr : in std_ulogic; + fdep_fiss_t0_is2_axu_movedp : in std_ulogic; + fdep_fiss_t0_is2_axu_instr_type : in std_ulogic_vector(0 to 2); + fdep_fiss_t0_is2_match : in std_ulogic; + fdep_fiss_t0_is2_2ucode : in std_ulogic; + fdep_fiss_t0_is2_2ucode_type : in std_ulogic; + fdep_fiss_t0_is2_hole_delay : in std_ulogic_vector(0 to 2); + fdep_fiss_t0_is2_to_ucode : in std_ulogic; + fdep_fiss_t0_is2_is_ucode : in std_ulogic; + fdep_fiss_t0_is2early_vld : in std_ulogic; + fdep_fiss_t0_is1_xu_dep_hit_b : in std_ulogic; + fdep_fiss_t1_is2_instr : in std_ulogic_vector(0 to 31); + fdep_fiss_t1_is2_ta_vld : in std_ulogic; + fdep_fiss_t1_is2_ta : in std_ulogic_vector(0 to 5); + fdep_fiss_t1_is2_s1_vld : in std_ulogic; + fdep_fiss_t1_is2_s1 : in std_ulogic_vector(0 to 5); + fdep_fiss_t1_is2_s2_vld : in std_ulogic; + fdep_fiss_t1_is2_s2 : in std_ulogic_vector(0 to 5); + fdep_fiss_t1_is2_s3_vld : in std_ulogic; + fdep_fiss_t1_is2_s3 : in std_ulogic_vector(0 to 5); + fdep_fiss_t1_is2_pred_update : in std_ulogic; + fdep_fiss_t1_is2_pred_taken_cnt : in std_ulogic_vector(0 to 1); + fdep_fiss_t1_is2_gshare : in std_ulogic_vector(0 to 3); + fdep_fiss_t1_is2_ifar : in eff_ifar; + fdep_fiss_t1_is2_error : in std_ulogic_vector(0 to 2); + fdep_fiss_t1_is2_axu_ld_or_st : in std_ulogic; + fdep_fiss_t1_is2_axu_store : in std_ulogic; + fdep_fiss_t1_is2_axu_ldst_indexed : in std_ulogic; + fdep_fiss_t1_is2_axu_ldst_tag : in std_ulogic_vector(0 to 8); + fdep_fiss_t1_is2_axu_ldst_size : in std_ulogic_vector(0 to 5); + fdep_fiss_t1_is2_axu_ldst_update : in std_ulogic; + fdep_fiss_t1_is2_axu_ldst_extpid : in std_ulogic; + fdep_fiss_t1_is2_axu_ldst_forcealign : in std_ulogic; + fdep_fiss_t1_is2_axu_ldst_forceexcept : in std_ulogic; + fdep_fiss_t1_is2_axu_mftgpr : in std_ulogic; + fdep_fiss_t1_is2_axu_mffgpr : in std_ulogic; + fdep_fiss_t1_is2_axu_movedp : in std_ulogic; + fdep_fiss_t1_is2_axu_instr_type : in std_ulogic_vector(0 to 2); + fdep_fiss_t1_is2_match : in std_ulogic; + fdep_fiss_t1_is2_2ucode : in std_ulogic; + fdep_fiss_t1_is2_2ucode_type : in std_ulogic; + fdep_fiss_t1_is2_hole_delay : in std_ulogic_vector(0 to 2); + fdep_fiss_t1_is2_to_ucode : in std_ulogic; + fdep_fiss_t1_is2_is_ucode : in std_ulogic; + fdep_fiss_t1_is2early_vld : in std_ulogic; + fdep_fiss_t1_is1_xu_dep_hit_b : in std_ulogic; + fdep_fiss_t2_is2_instr : in std_ulogic_vector(0 to 31); + fdep_fiss_t2_is2_ta_vld : in std_ulogic; + fdep_fiss_t2_is2_ta : in std_ulogic_vector(0 to 5); + fdep_fiss_t2_is2_s1_vld : in std_ulogic; + fdep_fiss_t2_is2_s1 : in std_ulogic_vector(0 to 5); + fdep_fiss_t2_is2_s2_vld : in std_ulogic; + fdep_fiss_t2_is2_s2 : in std_ulogic_vector(0 to 5); + fdep_fiss_t2_is2_s3_vld : in std_ulogic; + fdep_fiss_t2_is2_s3 : in std_ulogic_vector(0 to 5); + fdep_fiss_t2_is2_pred_update : in std_ulogic; + fdep_fiss_t2_is2_pred_taken_cnt : in std_ulogic_vector(0 to 1); + fdep_fiss_t2_is2_gshare : in std_ulogic_vector(0 to 3); + fdep_fiss_t2_is2_ifar : in eff_ifar; + fdep_fiss_t2_is2_error : in std_ulogic_vector(0 to 2); + fdep_fiss_t2_is2_axu_ld_or_st : in std_ulogic; + fdep_fiss_t2_is2_axu_store : in std_ulogic; + fdep_fiss_t2_is2_axu_ldst_indexed : in std_ulogic; + fdep_fiss_t2_is2_axu_ldst_tag : in std_ulogic_vector(0 to 8); + fdep_fiss_t2_is2_axu_ldst_size : in std_ulogic_vector(0 to 5); + fdep_fiss_t2_is2_axu_ldst_update : in std_ulogic; + fdep_fiss_t2_is2_axu_ldst_extpid : in std_ulogic; + fdep_fiss_t2_is2_axu_ldst_forcealign : in std_ulogic; + fdep_fiss_t2_is2_axu_ldst_forceexcept : in std_ulogic; + fdep_fiss_t2_is2_axu_mftgpr : in std_ulogic; + fdep_fiss_t2_is2_axu_mffgpr : in std_ulogic; + fdep_fiss_t2_is2_axu_movedp : in std_ulogic; + fdep_fiss_t2_is2_axu_instr_type : in std_ulogic_vector(0 to 2); + fdep_fiss_t2_is2_match : in std_ulogic; + fdep_fiss_t2_is2_2ucode : in std_ulogic; + fdep_fiss_t2_is2_2ucode_type : in std_ulogic; + fdep_fiss_t2_is2_hole_delay : in std_ulogic_vector(0 to 2); + fdep_fiss_t2_is2_to_ucode : in std_ulogic; + fdep_fiss_t2_is2_is_ucode : in std_ulogic; + fdep_fiss_t2_is2early_vld : in std_ulogic; + fdep_fiss_t2_is1_xu_dep_hit_b : in std_ulogic; + fdep_fiss_t3_is2_instr : in std_ulogic_vector(0 to 31); + fdep_fiss_t3_is2_ta_vld : in std_ulogic; + fdep_fiss_t3_is2_ta : in std_ulogic_vector(0 to 5); + fdep_fiss_t3_is2_s1_vld : in std_ulogic; + fdep_fiss_t3_is2_s1 : in std_ulogic_vector(0 to 5); + fdep_fiss_t3_is2_s2_vld : in std_ulogic; + fdep_fiss_t3_is2_s2 : in std_ulogic_vector(0 to 5); + fdep_fiss_t3_is2_s3_vld : in std_ulogic; + fdep_fiss_t3_is2_s3 : in std_ulogic_vector(0 to 5); + fdep_fiss_t3_is2_pred_update : in std_ulogic; + fdep_fiss_t3_is2_pred_taken_cnt : in std_ulogic_vector(0 to 1); + fdep_fiss_t3_is2_gshare : in std_ulogic_vector(0 to 3); + fdep_fiss_t3_is2_ifar : in eff_ifar; + fdep_fiss_t3_is2_error : in std_ulogic_vector(0 to 2); + fdep_fiss_t3_is2_axu_ld_or_st : in std_ulogic; + fdep_fiss_t3_is2_axu_store : in std_ulogic; + fdep_fiss_t3_is2_axu_ldst_indexed : in std_ulogic; + fdep_fiss_t3_is2_axu_ldst_tag : in std_ulogic_vector(0 to 8); + fdep_fiss_t3_is2_axu_ldst_size : in std_ulogic_vector(0 to 5); + fdep_fiss_t3_is2_axu_ldst_update : in std_ulogic; + fdep_fiss_t3_is2_axu_ldst_extpid : in std_ulogic; + fdep_fiss_t3_is2_axu_ldst_forcealign : in std_ulogic; + fdep_fiss_t3_is2_axu_ldst_forceexcept : in std_ulogic; + fdep_fiss_t3_is2_axu_mftgpr : in std_ulogic; + fdep_fiss_t3_is2_axu_mffgpr : in std_ulogic; + fdep_fiss_t3_is2_axu_movedp : in std_ulogic; + fdep_fiss_t3_is2_axu_instr_type : in std_ulogic_vector(0 to 2); + fdep_fiss_t3_is2_match : in std_ulogic; + fdep_fiss_t3_is2_2ucode : in std_ulogic; + fdep_fiss_t3_is2_2ucode_type : in std_ulogic; + fdep_fiss_t3_is2_hole_delay : in std_ulogic_vector(0 to 2); + fdep_fiss_t3_is2_to_ucode : in std_ulogic; + fdep_fiss_t3_is2_is_ucode : in std_ulogic; + fdep_fiss_t3_is2early_vld : in std_ulogic; + fdep_fiss_t3_is1_xu_dep_hit_b : in std_ulogic; + + fiss_fdep_is2_take0 : out std_ulogic; + fiss_fdep_is2_take1 : out std_ulogic; + fiss_fdep_is2_take2 : out std_ulogic; + fiss_fdep_is2_take3 : out std_ulogic; + + spr_issue_high_mask : in std_ulogic_vector(0 to 3); + spr_issue_med_mask : in std_ulogic_vector(0 to 3); + spr_fiss_count0_max : in std_ulogic_vector(0 to 5); + spr_fiss_count1_max : in std_ulogic_vector(0 to 5); + spr_fiss_count2_max : in std_ulogic_vector(0 to 5); + spr_fiss_count3_max : in std_ulogic_vector(0 to 5); + + spr_fiss_pri_rand : in std_ulogic_vector(0 to 4); + spr_fiss_pri_rand_always : in std_ulogic; + spr_fiss_pri_rand_flush : in std_ulogic; + + iu_au_hi_pri_mask : out std_ulogic_vector(0 to 3); + iu_au_md_pri_mask : out std_ulogic_vector(0 to 3); + i_afi_is2_take_t : in std_ulogic_vector(0 to 3); + i_afd_is2_t0_instr_v : in std_ulogic; + i_afd_is2_t1_instr_v : in std_ulogic; + i_afd_is2_t2_instr_v : in std_ulogic; + i_afd_is2_t3_instr_v : in std_ulogic; + i_axu_is1_dep_hit_t0_b : in std_ulogic; + i_axu_is1_dep_hit_t1_b : in std_ulogic; + i_axu_is1_dep_hit_t2_b : in std_ulogic; + i_axu_is1_dep_hit_t3_b : in std_ulogic; + + xu_iu_is2_flush_tid : in std_ulogic_vector(0 to 3); + xu_iu_rf0_flush_tid : in std_ulogic_vector(0 to 3); + xu_iu_rf1_flush_tid : in std_ulogic_vector(0 to 3); + xu_iu_ex1_flush_tid : in std_ulogic_vector(0 to 3); + xu_iu_ex2_flush_tid : in std_ulogic_vector(0 to 3); + xu_iu_ex3_flush_tid : in std_ulogic_vector(0 to 3); + xu_iu_ex4_flush_tid : in std_ulogic_vector(0 to 3); + xu_iu_ex5_flush_tid : in std_ulogic_vector(0 to 3); + xu_iu_ex5_ppc_cpl : in std_ulogic_vector(0 to 3); + + iu_xu_is2_vld : out std_ulogic; + iu_xu_is2_tid : out std_ulogic_vector(0 to 3); + iu_xu_is2_instr : out std_ulogic_vector(0 to 31); + iu_xu_is2_ta_vld : out std_ulogic; + iu_xu_is2_ta : out std_ulogic_vector(0 to 5); + iu_xu_is2_s1_vld : out std_ulogic; + iu_xu_is2_s1 : out std_ulogic_vector(0 to 5); + iu_xu_is2_s2_vld : out std_ulogic; + iu_xu_is2_s2 : out std_ulogic_vector(0 to 5); + iu_xu_is2_s3_vld : out std_ulogic; + iu_xu_is2_s3 : out std_ulogic_vector(0 to 5); + iu_xu_is2_pred_update : out std_ulogic; + iu_xu_is2_pred_taken_cnt : out std_ulogic_vector(0 to 1); + iu_xu_is2_gshare : out std_ulogic_vector(0 to 3); + iu_xu_is2_ifar : out eff_ifar; + iu_xu_is2_error : out std_ulogic_vector(0 to 2); + iu_xu_is2_is_ucode : out std_ulogic; + iu_xu_is2_axu_ld_or_st : out std_ulogic; + iu_xu_is2_axu_store : out std_ulogic; + iu_xu_is2_axu_ldst_indexed : out std_ulogic; + iu_xu_is2_axu_ldst_tag : out std_ulogic_vector(0 to 8); + iu_xu_is2_axu_ldst_size : out std_ulogic_vector(0 to 5); + iu_xu_is2_axu_ldst_update : out std_ulogic; + iu_xu_is2_axu_ldst_extpid : out std_ulogic; + iu_xu_is2_axu_ldst_forcealign : out std_ulogic; + iu_xu_is2_axu_ldst_forceexcept : out std_ulogic; + iu_xu_is2_axu_mftgpr : out std_ulogic; + iu_xu_is2_axu_mffgpr : out std_ulogic; + iu_xu_is2_axu_movedp : out std_ulogic; + iu_xu_is2_axu_instr_type : out std_ulogic_vector(0 to 2); + iu_xu_is2_match : out std_ulogic; + fiss_uc_is2_2ucode : out std_ulogic; + fiss_uc_is2_2ucode_type : out std_ulogic; + iu_fu_rf0_str_val : out std_ulogic; + iu_fu_rf0_ldst_val : out std_ulogic; + iu_fu_rf0_ldst_tid : out std_ulogic_vector(0 to 1); + iu_fu_rf0_ldst_tag : out std_ulogic_vector(0 to 8)); +-- synopsys translate_off +-- synopsys translate_on +end iuq_fxu_issue; +ARCHITECTURE IUQ_FXU_ISSUE + OF IUQ_FXU_ISSUE + IS +-- scan chain connenctions +constant uc_flush_tid_offset : natural := 0; +constant xu_iu_need_hole_offset : natural := uc_flush_tid_offset + 4; +constant xu_iu_xucr0_rel_offset : natural := xu_iu_need_hole_offset + 1; +constant an_ac_back_inv_offset : natural := xu_iu_xucr0_rel_offset + 1; +constant an_ac_back_inv_target_offset : natural := an_ac_back_inv_offset + 1; +constant gap_l2_rel_hole_dly1_offset : natural := an_ac_back_inv_target_offset + 1; +constant gap_l2_rel_hole_dly2_offset : natural := gap_l2_rel_hole_dly1_offset + 1; +constant gap_l2_tag_dly1_offset : natural := gap_l2_rel_hole_dly2_offset + 1; +constant gap_l2_tag_dly2_offset : natural := gap_l2_tag_dly1_offset + 3; +constant low_pri_rf0_offset : natural := gap_l2_tag_dly2_offset + 3; +constant low_pri_rf1_offset : natural := low_pri_rf0_offset + 4; +constant low_pri_ex1_offset : natural := low_pri_rf1_offset + 4; +constant low_pri_ex2_offset : natural := low_pri_ex1_offset + 4; +constant low_pri_ex3_offset : natural := low_pri_ex2_offset + 4; +constant low_pri_ex4_offset : natural := low_pri_ex3_offset + 4; +constant low_pri_ex5_offset : natural := low_pri_ex4_offset + 4; +constant low_pri_ex6_offset : natural := low_pri_ex5_offset + 4; +constant xu_iu_ex6_ppc_cpl_offset: natural := low_pri_ex6_offset + 4; +constant low_pri_counter0_offset: natural := xu_iu_ex6_ppc_cpl_offset + 4; +constant low_pri_counter1_offset: natural := low_pri_counter0_offset + 8; +constant low_pri_counter2_offset: natural := low_pri_counter1_offset + 8; +constant low_pri_counter3_offset: natural := low_pri_counter2_offset + 8; +constant low_pri_max0_offset : natural := low_pri_counter3_offset + 8; +constant low_pri_max1_offset : natural := low_pri_max0_offset + 6; +constant low_pri_max2_offset : natural := low_pri_max1_offset + 6; +constant low_pri_max3_offset : natural := low_pri_max2_offset + 6; +constant high_pri_mask_offset : natural := low_pri_max3_offset + 6; +constant med_pri_mask_offset : natural := high_pri_mask_offset + 4; +constant spr_high_mask_offset : natural := med_pri_mask_offset + 4; +constant spr_med_mask_offset : natural := spr_high_mask_offset + 4; +constant hole_delay0_offset : natural := spr_med_mask_offset + 4; +constant hole_delay1_offset : natural := hole_delay0_offset + 2; +constant hole_delay2_offset : natural := hole_delay1_offset + 2; +constant hole_delay3_offset : natural := hole_delay2_offset + 2; +constant is2_vld_offset : natural := hole_delay3_offset + 2; +constant perf_event_offset : natural := is2_vld_offset + 4; +constant fiss_dbg_data_offset : natural := perf_event_offset + 32; +constant rf0_str_val_offset : natural := fiss_dbg_data_offset + 44; +constant rf0_ldst_val_offset : natural := rf0_str_val_offset + 1; +constant rf0_ldst_tid_offset : natural := rf0_ldst_val_offset + 1; +constant rf0_ldst_tag_offset : natural := rf0_ldst_tid_offset + 2; +constant rf0_took_offset : natural := rf0_ldst_tag_offset + 9; +constant spare_offset : natural := rf0_took_offset + 12; +constant trace_bus_enable_offset : natural := spare_offset + 4; +constant event_bus_enable_offset : natural := trace_bus_enable_offset + 1; +constant scan_right : natural := event_bus_enable_offset + 1 - 1; +signal act_dis : std_ulogic; +signal d_mode : std_ulogic; +signal mpw2_b : std_ulogic; +signal spare_l2 : std_ulogic_vector(0 to 3); +signal trace_bus_enable_d : std_ulogic; +signal trace_bus_enable_q : std_ulogic; +signal event_bus_enable_d : std_ulogic; +signal event_bus_enable_q : std_ulogic; +-- signals for hooking up scanchains +signal siv : std_ulogic_vector(0 to scan_right); +signal sov : std_ulogic_vector(0 to scan_right); +signal tiup : std_ulogic; +signal pc_iu_func_sl_thold_1 : std_ulogic; +signal pc_iu_func_sl_thold_0 : std_ulogic; +signal pc_iu_func_sl_thold_0_b : std_ulogic; +signal pc_iu_sg_1 : std_ulogic; +signal pc_iu_sg_0 : std_ulogic; +signal forcee : std_ulogic; +signal xu_iu_need_hole_d : std_ulogic; +signal xu_iu_need_hole_l2 : std_ulogic; +signal xu_iu_xucr0_rel_d : std_ulogic; +signal xu_iu_xucr0_rel_l2 : std_ulogic; +signal an_ac_back_inv_d : std_ulogic; +signal an_ac_back_inv_l2 : std_ulogic; +signal an_ac_back_inv_target_d : std_ulogic; +signal an_ac_back_inv_target_l2 : std_ulogic; +signal gap_l2_rel_hole_dly1_d : std_ulogic; +signal gap_l2_rel_hole_dly1_l2 : std_ulogic; +signal gap_l2_rel_hole_dly2_d : std_ulogic; +signal gap_l2_rel_hole_dly2_l2 : std_ulogic; +signal gap_l2_tag_dly1_d : std_ulogic_vector(2 to 4); +signal gap_l2_tag_dly1_l2 : std_ulogic_vector(2 to 4); +signal gap_l2_tag_dly2_d : std_ulogic_vector(2 to 4); +signal gap_l2_tag_dly2_l2 : std_ulogic_vector(2 to 4); +signal need_hole : std_ulogic; +signal gap_l2_rel_hole : std_ulogic; +signal dcache_rel_hole : std_ulogic; +signal dcache_rel_tag_2nd_beat : std_ulogic; +signal dcache_binv_hole : std_ulogic; +------------------------------------------------------------------------- +-- is2 early indicators +------------------------------------------------------------------------- +signal is2_vld_d : std_ulogic_vector(0 to 3); +signal hole_delay0_d : std_ulogic_vector(0 to 1); +signal hole_delay1_d : std_ulogic_vector(0 to 1); +signal hole_delay2_d : std_ulogic_vector(0 to 1); +signal hole_delay3_d : std_ulogic_vector(0 to 1); +signal is2_vld_l2 : std_ulogic_vector(0 to 3); +signal hole_delay0_l2 : std_ulogic_vector(0 to 1); +signal hole_delay1_l2 : std_ulogic_vector(0 to 1); +signal hole_delay2_l2 : std_ulogic_vector(0 to 1); +signal hole_delay3_l2 : std_ulogic_vector(0 to 1); +signal hole0 : std_ulogic; +signal hole1 : std_ulogic; +signal hole2 : std_ulogic; +signal hole3 : std_ulogic; +signal hole0_b : std_ulogic; +signal hole1_b : std_ulogic; +signal hole2_b : std_ulogic; +signal hole3_b : std_ulogic; +------------------------------------------------------------------------- +-- priority latch signals +------------------------------------------------------------------------- +signal low_pri_rf0_d : std_ulogic_vector(0 to 3); +signal low_pri_rf1_d : std_ulogic_vector(0 to 3); +signal low_pri_ex1_d : std_ulogic_vector(0 to 3); +signal low_pri_ex2_d : std_ulogic_vector(0 to 3); +signal low_pri_ex3_d : std_ulogic_vector(0 to 3); +signal low_pri_ex4_d : std_ulogic_vector(0 to 3); +signal low_pri_ex5_d : std_ulogic_vector(0 to 3); +signal low_pri_ex6_d : std_ulogic_vector(0 to 3); +signal xu_iu_ex6_ppc_cpl_d : std_ulogic_vector(0 to 3); +signal low_pri_counter0_d : std_ulogic_vector(0 to 7); +signal low_pri_counter1_d : std_ulogic_vector(0 to 7); +signal low_pri_counter2_d : std_ulogic_vector(0 to 7); +signal low_pri_counter3_d : std_ulogic_vector(0 to 7); +signal low_pri_max0_d : std_ulogic_vector(0 to 5); +signal low_pri_max1_d : std_ulogic_vector(0 to 5); +signal low_pri_max2_d : std_ulogic_vector(0 to 5); +signal low_pri_max3_d : std_ulogic_vector(0 to 5); +signal high_pri_mask_d : std_ulogic_vector(0 to 3); +signal med_pri_mask_d : std_ulogic_vector(0 to 3); +signal spr_high_mask_d : std_ulogic_vector(0 to 3); +signal spr_med_mask_d : std_ulogic_vector(0 to 3); +signal fiss_dbg_data_d : std_ulogic_vector(44 to 87); +signal low_pri_rf0_l2 : std_ulogic_vector(0 to 3); +signal low_pri_rf1_l2 : std_ulogic_vector(0 to 3); +signal low_pri_ex1_l2 : std_ulogic_vector(0 to 3); +signal low_pri_ex2_l2 : std_ulogic_vector(0 to 3); +signal low_pri_ex3_l2 : std_ulogic_vector(0 to 3); +signal low_pri_ex4_l2 : std_ulogic_vector(0 to 3); +signal low_pri_ex5_l2 : std_ulogic_vector(0 to 3); +signal low_pri_ex6_l2 : std_ulogic_vector(0 to 3); +signal xu_iu_ex6_ppc_cpl_l2 : std_ulogic_vector(0 to 3); +signal low_pri_counter0_l2 : std_ulogic_vector(0 to 7); +signal low_pri_counter1_l2 : std_ulogic_vector(0 to 7); +signal low_pri_counter2_l2 : std_ulogic_vector(0 to 7); +signal low_pri_counter3_l2 : std_ulogic_vector(0 to 7); +signal low_pri_max0_l2 : std_ulogic_vector(0 to 5); +signal low_pri_max1_l2 : std_ulogic_vector(0 to 5); +signal low_pri_max2_l2 : std_ulogic_vector(0 to 5); +signal low_pri_max3_l2 : std_ulogic_vector(0 to 5); +signal high_pri_mask_l2 : std_ulogic_vector(0 to 3); +signal med_pri_mask_l2 : std_ulogic_vector(0 to 3); +signal spr_high_mask_l2 : std_ulogic_vector(0 to 3); +signal spr_med_mask_l2 : std_ulogic_vector(0 to 3); +signal fiss_dbg_data_l2 : std_ulogic_vector(44 to 87); +signal low_pri_counter0_act : std_ulogic; +signal low_pri_counter1_act : std_ulogic; +signal low_pri_counter2_act : std_ulogic; +signal low_pri_counter3_act : std_ulogic; +signal low_pri_rf1_act : std_ulogic; +signal low_pri_ex1_act : std_ulogic; +signal low_pri_ex2_act : std_ulogic; +signal low_pri_ex3_act : std_ulogic; +signal low_pri_ex4_act : std_ulogic; +signal low_pri_ex5_act : std_ulogic; +signal low_pri_ex6_act : std_ulogic; +signal high_pri_mask_din : std_ulogic_vector(0 to 3); +signal med_pri_mask_din : std_ulogic_vector(0 to 3); +signal low_pri_en : std_ulogic_vector(0 to 3); +signal low_pri_val : std_ulogic_vector(0 to 3); +signal pri_rand : std_ulogic_vector(0 to 5); +-- signals used for selecting next thread +signal high_priority_valids : std_ulogic_vector(0 to 3); +signal med_priority_valids : std_ulogic_vector(0 to 3); +signal n_thread : std_ulogic_vector(0 to 3); +------ +signal uc_flush_tid_d : std_ulogic_vector(0 to 3); +signal uc_flush_tid_l2 : std_ulogic_vector(0 to 3); +signal int_is2_vld : std_ulogic; +signal iss_is2_vld : std_ulogic; +signal int_is2_to_ucode : std_ulogic; +signal is1_dep_hit : std_ulogic_vector(0 to 3); +signal is2_stall : std_ulogic_vector(0 to 3); +signal perf_event_d : std_ulogic_vector(0 to 31); +signal perf_event_l2 : std_ulogic_vector(0 to 31); +signal iu_xu_is2_axu_ldst_tag_int : std_ulogic_vector(0 to 8); +signal iu_xu_is2_axu_store_int : std_ulogic; +signal iu_xu_is2_axu_ld_or_st_int : std_ulogic; +signal iu_xu_is2_instr_int : std_ulogic_vector(0 to 31); +signal iu_xu_is2_vld_int : std_ulogic; +signal iu_xu_is2_tid_int : std_ulogic_vector(0 to 3); +signal iu_xu_is2_error_int : std_ulogic_vector(0 to 2); +signal iu_xu_is2_pred_update_int : std_ulogic; +signal iu_xu_is2_pred_taken_cnt_int : std_ulogic_vector(0 to 1); +signal fiss_uc_is2_ucode_vld_int : std_ulogic; +signal rf0_str_val_d : std_ulogic; +signal rf0_str_val_l2 : std_ulogic; +signal rf0_ldst_val_d : std_ulogic; +signal rf0_ldst_val_l2 : std_ulogic; +signal rf0_ldst_tid_d : std_ulogic_vector(0 to 1); +signal rf0_ldst_tid_l2 : std_ulogic_vector(0 to 1); +signal rf0_ldst_tag_d : std_ulogic_vector(0 to 8); +signal rf0_ldst_tag_l2 : std_ulogic_vector(0 to 8); +signal rf0_ldst_act : std_ulogic; +signal next_tid : std_ulogic_vector(0 to 3); +signal hi_did3no0_d : std_ulogic; +signal hi_did3no1_d : std_ulogic; +signal hi_did3no2_d : std_ulogic; +signal hi_did2no0_d : std_ulogic; +signal hi_did2no1_d : std_ulogic; +signal hi_did1no0_d : std_ulogic; +signal md_did3no0_d : std_ulogic; +signal md_did3no1_d : std_ulogic; +signal md_did3no2_d : std_ulogic; +signal md_did2no0_d : std_ulogic; +signal md_did2no1_d : std_ulogic; +signal md_did1no0_d : std_ulogic; +--priority map signals +signal hi_n230, hi_n231, hi_n232 : std_ulogic; +signal hi_n220, hi_n221, hi_n210 : std_ulogic; +signal md_n230, md_n231, md_n232 : std_ulogic; +signal md_n220, md_n221, md_n210 : std_ulogic; +signal medpri_v, medpri_v_b, highpri_v, highpri_v_b : std_ulogic_vector(0 to 3); +signal medpri_v_b0, highpri_v_b0 : std_ulogic_vector(0 to 3); +signal hi_did0no1, hi_did0no2, hi_did0no3 : std_ulogic; +signal hi_did1no0, hi_did1no2, hi_did1no3 : std_ulogic; +signal hi_did2no1, hi_did2no0, hi_did2no3 : std_ulogic; +signal hi_did3no1, hi_did3no2, hi_did3no0 : std_ulogic; +signal md_did0no1, md_did0no2, md_did0no3 : std_ulogic; +signal md_did1no0, md_did1no2, md_did1no3 : std_ulogic; +signal md_did2no1, md_did2no0, md_did2no3 : std_ulogic; +signal md_did3no1, md_did3no2, md_did3no0 : std_ulogic; +signal hi_sel, hi_sel_b, md_sel, md_sel_b, hi_later, md_later : std_ulogic_vector(0 to 3); +signal hi_did3no0_din : std_ulogic; +signal hi_did3no1_din : std_ulogic; +signal hi_did3no2_din : std_ulogic; +signal hi_did2no0_din : std_ulogic; +signal hi_did2no1_din : std_ulogic; +signal hi_did1no0_din : std_ulogic; +signal md_did3no0_din : std_ulogic; +signal md_did3no1_din : std_ulogic; +signal md_did3no2_din : std_ulogic; +signal md_did2no0_din : std_ulogic; +signal md_did2no1_din : std_ulogic; +signal md_did1no0_din : std_ulogic; +signal issselhi_b, issselmd_b : std_ulogic_vector(0 to 3); +signal no_hi_v,no_hi_v_n01, no_hi_v_n23 : std_ulogic; +signal hi_l30, hi_l31, hi_l32 : std_ulogic; +signal hi_l23, hi_l20, hi_l21 : std_ulogic; +signal hi_l12, hi_l13, hi_l10 : std_ulogic; +signal hi_l01, hi_l02, hi_l03 : std_ulogic; +signal md_l30, md_l31, md_l32 : std_ulogic; +signal md_l23, md_l20, md_l21 : std_ulogic; +signal md_l12, md_l13, md_l10 : std_ulogic; +signal md_l01, md_l02, md_l03 : std_ulogic; +signal take, take_b : std_ulogic_vector(0 to 3); +signal no_hi_v_b : std_ulogic; +------------------------------------------------------------------------- +-- Pipe blockers +------------------------------------------------------------------------- + BEGIN --@@ START OF EXECUTABLE CODE FOR IUQ_FXU_ISSUE + +tiup <= '1'; +act_dis <= '0'; +d_mode <= '0'; +mpw2_b <= '1'; +------------------------------------------------- +-- pervasive +------------------------------------------------- +perv_2to1_reg: tri_plat + generic map (width => 2, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_iu_func_sl_thold_2, + din(1) => pc_iu_sg_2, + q(0) => pc_iu_func_sl_thold_1, + q(1) => pc_iu_sg_1); +perv_1to0_reg: tri_plat + generic map (width => 2, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_iu_func_sl_thold_1, + din(1) => pc_iu_sg_1, + q(0) => pc_iu_func_sl_thold_0, + q(1) => pc_iu_sg_0); +perv_lcbor: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_b, + thold => pc_iu_func_sl_thold_0, + sg => pc_iu_sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => pc_iu_func_sl_thold_0_b); +----------------------------------------------------------------------- +-- latch definition +----------------------------------------------------------------------- +uc_flush_tid_latch: tri_rlmreg_p + generic map (width => uc_flush_tid_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(uc_flush_tid_offset to uc_flush_tid_offset + uc_flush_tid_l2'length-1), + scout => sov(uc_flush_tid_offset to uc_flush_tid_offset + uc_flush_tid_l2'length-1), + din => uc_flush_tid_d, + dout => uc_flush_tid_l2); +xu_iu_need_hole_latch: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_iu_need_hole_offset), + scout => sov(xu_iu_need_hole_offset), + din => xu_iu_need_hole_d, + dout => xu_iu_need_hole_l2); +xu_iu_xucr0_rel_latch: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_iu_xucr0_rel_offset), + scout => sov(xu_iu_xucr0_rel_offset), + din => xu_iu_xucr0_rel_d, + dout => xu_iu_xucr0_rel_l2); +an_ac_back_inv_latch: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(an_ac_back_inv_offset), + scout => sov(an_ac_back_inv_offset), + din => an_ac_back_inv_d, + dout => an_ac_back_inv_l2); +an_ac_back_inv_target_latch: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(an_ac_back_inv_target_offset), + scout => sov(an_ac_back_inv_target_offset), + din => an_ac_back_inv_target_d, + dout => an_ac_back_inv_target_l2); +gap_l2_rel_hole_dly1_latch: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(gap_l2_rel_hole_dly1_offset), + scout => sov(gap_l2_rel_hole_dly1_offset), + din => gap_l2_rel_hole_dly1_d, + dout => gap_l2_rel_hole_dly1_l2); +gap_l2_rel_hole_dly2_latch: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(gap_l2_rel_hole_dly2_offset), + scout => sov(gap_l2_rel_hole_dly2_offset), + din => gap_l2_rel_hole_dly2_d, + dout => gap_l2_rel_hole_dly2_l2); +gap_l2_tag_dly1_latch: tri_rlmreg_p + generic map (width => gap_l2_tag_dly1_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(gap_l2_tag_dly1_offset to gap_l2_tag_dly1_offset + gap_l2_tag_dly1_l2'length-1), + scout => sov(gap_l2_tag_dly1_offset to gap_l2_tag_dly1_offset + gap_l2_tag_dly1_l2'length-1), + din => gap_l2_tag_dly1_d, + dout => gap_l2_tag_dly1_l2); +gap_l2_tag_dly2_latch: tri_rlmreg_p + generic map (width => gap_l2_tag_dly2_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(gap_l2_tag_dly2_offset to gap_l2_tag_dly2_offset + gap_l2_tag_dly2_l2'length-1), + scout => sov(gap_l2_tag_dly2_offset to gap_l2_tag_dly2_offset + gap_l2_tag_dly2_l2'length-1), + din => gap_l2_tag_dly2_d, + dout => gap_l2_tag_dly2_l2); +is2_vld: tri_rlmreg_p + generic map (width => is2_vld_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(is2_vld_offset to is2_vld_offset + is2_vld_l2'length-1), + scout => sov(is2_vld_offset to is2_vld_offset + is2_vld_l2'length-1), + din => is2_vld_d, + dout => is2_vld_l2); +hole_delay0: tri_rlmreg_p + generic map (width => hole_delay0_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(hole_delay0_offset to hole_delay0_offset + hole_delay0_l2'length-1), + scout => sov(hole_delay0_offset to hole_delay0_offset + hole_delay0_l2'length-1), + din => hole_delay0_d, + dout => hole_delay0_l2); +hole_delay1: tri_rlmreg_p + generic map (width => hole_delay1_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(hole_delay1_offset to hole_delay1_offset + hole_delay1_l2'length-1), + scout => sov(hole_delay1_offset to hole_delay1_offset + hole_delay1_l2'length-1), + din => hole_delay1_d, + dout => hole_delay1_l2); +hole_delay2: tri_rlmreg_p + generic map (width => hole_delay2_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(hole_delay2_offset to hole_delay2_offset + hole_delay2_l2'length-1), + scout => sov(hole_delay2_offset to hole_delay2_offset + hole_delay2_l2'length-1), + din => hole_delay2_d, + dout => hole_delay2_l2); +hole_delay3: tri_rlmreg_p + generic map (width => hole_delay3_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(hole_delay3_offset to hole_delay3_offset + hole_delay3_l2'length-1), + scout => sov(hole_delay3_offset to hole_delay3_offset + hole_delay3_l2'length-1), + din => hole_delay3_d, + dout => hole_delay3_l2); +med_pri_mask: tri_rlmreg_p + generic map (width => med_pri_mask_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(med_pri_mask_offset to med_pri_mask_offset + med_pri_mask_l2'length-1), + scout => sov(med_pri_mask_offset to med_pri_mask_offset + med_pri_mask_l2'length-1), + din => med_pri_mask_d, + dout => med_pri_mask_l2); +high_pri_mask: tri_rlmreg_p + generic map (width => high_pri_mask_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(high_pri_mask_offset to high_pri_mask_offset + high_pri_mask_l2'length-1), + scout => sov(high_pri_mask_offset to high_pri_mask_offset + high_pri_mask_l2'length-1), + din => high_pri_mask_d, + dout => high_pri_mask_l2); +spr_high_mask: tri_rlmreg_p + generic map (width => spr_high_mask_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(spr_high_mask_offset to spr_high_mask_offset + spr_high_mask_l2'length-1), + scout => sov(spr_high_mask_offset to spr_high_mask_offset + spr_high_mask_l2'length-1), + din => spr_high_mask_d, + dout => spr_high_mask_l2); +spr_med_mask: tri_rlmreg_p + generic map (width => spr_med_mask_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(spr_med_mask_offset to spr_med_mask_offset + spr_med_mask_l2'length-1), + scout => sov(spr_med_mask_offset to spr_med_mask_offset + spr_med_mask_l2'length-1), + din => spr_med_mask_d, + dout => spr_med_mask_l2); +low_pri_max0: tri_rlmreg_p + generic map (width => low_pri_max0_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(low_pri_max0_offset to low_pri_max0_offset + low_pri_max0_l2'length-1), + scout => sov(low_pri_max0_offset to low_pri_max0_offset + low_pri_max0_l2'length-1), + din => low_pri_max0_d, + dout => low_pri_max0_l2); +low_pri_max1: tri_rlmreg_p + generic map (width => low_pri_max1_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(low_pri_max1_offset to low_pri_max1_offset + low_pri_max1_l2'length-1), + scout => sov(low_pri_max1_offset to low_pri_max1_offset + low_pri_max1_l2'length-1), + din => low_pri_max1_d, + dout => low_pri_max1_l2); +low_pri_max2: tri_rlmreg_p + generic map (width => low_pri_max2_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(low_pri_max2_offset to low_pri_max2_offset + low_pri_max2_l2'length-1), + scout => sov(low_pri_max2_offset to low_pri_max2_offset + low_pri_max2_l2'length-1), + din => low_pri_max2_d, + dout => low_pri_max2_l2); +low_pri_max3: tri_rlmreg_p + generic map (width => low_pri_max3_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(low_pri_max3_offset to low_pri_max3_offset + low_pri_max3_l2'length-1), + scout => sov(low_pri_max3_offset to low_pri_max3_offset + low_pri_max3_l2'length-1), + din => low_pri_max3_d, + dout => low_pri_max3_l2); +low_pri_counter0: tri_rlmreg_p + generic map (width => low_pri_counter0_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => low_pri_counter0_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(low_pri_counter0_offset to low_pri_counter0_offset + low_pri_counter0_l2'length-1), + scout => sov(low_pri_counter0_offset to low_pri_counter0_offset + low_pri_counter0_l2'length-1), + din => low_pri_counter0_d, + dout => low_pri_counter0_l2); +low_pri_counter1: tri_rlmreg_p + generic map (width => low_pri_counter1_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => low_pri_counter1_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(low_pri_counter1_offset to low_pri_counter1_offset + low_pri_counter1_l2'length-1), + scout => sov(low_pri_counter1_offset to low_pri_counter1_offset + low_pri_counter1_l2'length-1), + din => low_pri_counter1_d, + dout => low_pri_counter1_l2); +low_pri_counter2: tri_rlmreg_p + generic map (width => low_pri_counter2_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => low_pri_counter2_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(low_pri_counter2_offset to low_pri_counter2_offset + low_pri_counter2_l2'length-1), + scout => sov(low_pri_counter2_offset to low_pri_counter2_offset + low_pri_counter2_l2'length-1), + din => low_pri_counter2_d, + dout => low_pri_counter2_l2); +low_pri_counter3: tri_rlmreg_p + generic map (width => low_pri_counter3_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => low_pri_counter3_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(low_pri_counter3_offset to low_pri_counter3_offset + low_pri_counter3_l2'length-1), + scout => sov(low_pri_counter3_offset to low_pri_counter3_offset + low_pri_counter3_l2'length-1), + din => low_pri_counter3_d, + dout => low_pri_counter3_l2); +low_pri_rf0: tri_rlmreg_p + generic map (width => low_pri_rf0_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(low_pri_rf0_offset to low_pri_rf0_offset + low_pri_rf0_l2'length-1), + scout => sov(low_pri_rf0_offset to low_pri_rf0_offset + low_pri_rf0_l2'length-1), + din => low_pri_rf0_d, + dout => low_pri_rf0_l2); +low_pri_rf1: tri_rlmreg_p + generic map (width => low_pri_rf1_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => low_pri_rf1_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(low_pri_rf1_offset to low_pri_rf1_offset + low_pri_rf1_l2'length-1), + scout => sov(low_pri_rf1_offset to low_pri_rf1_offset + low_pri_rf1_l2'length-1), + din => low_pri_rf1_d, + dout => low_pri_rf1_l2); +low_pri_ex1: tri_rlmreg_p + generic map (width => low_pri_ex1_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => low_pri_ex1_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(low_pri_ex1_offset to low_pri_ex1_offset + low_pri_ex1_l2'length-1), + scout => sov(low_pri_ex1_offset to low_pri_ex1_offset + low_pri_ex1_l2'length-1), + din => low_pri_ex1_d, + dout => low_pri_ex1_l2); +low_pri_ex2: tri_rlmreg_p + generic map (width => low_pri_ex2_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => low_pri_ex2_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(low_pri_ex2_offset to low_pri_ex2_offset + low_pri_ex2_l2'length-1), + scout => sov(low_pri_ex2_offset to low_pri_ex2_offset + low_pri_ex2_l2'length-1), + din => low_pri_ex2_d, + dout => low_pri_ex2_l2); +low_pri_ex3: tri_rlmreg_p + generic map (width => low_pri_ex3_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => low_pri_ex3_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(low_pri_ex3_offset to low_pri_ex3_offset + low_pri_ex3_l2'length-1), + scout => sov(low_pri_ex3_offset to low_pri_ex3_offset + low_pri_ex3_l2'length-1), + din => low_pri_ex3_d, + dout => low_pri_ex3_l2); +low_pri_ex4: tri_rlmreg_p + generic map (width => low_pri_ex4_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => low_pri_ex4_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(low_pri_ex4_offset to low_pri_ex4_offset + low_pri_ex4_l2'length-1), + scout => sov(low_pri_ex4_offset to low_pri_ex4_offset + low_pri_ex4_l2'length-1), + din => low_pri_ex4_d, + dout => low_pri_ex4_l2); +low_pri_ex5: tri_rlmreg_p + generic map (width => low_pri_ex5_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => low_pri_ex5_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(low_pri_ex5_offset to low_pri_ex5_offset + low_pri_ex5_l2'length-1), + scout => sov(low_pri_ex5_offset to low_pri_ex5_offset + low_pri_ex5_l2'length-1), + din => low_pri_ex5_d, + dout => low_pri_ex5_l2); +low_pri_ex6: tri_rlmreg_p + generic map (width => low_pri_ex6_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => low_pri_ex6_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(low_pri_ex6_offset to low_pri_ex6_offset + low_pri_ex6_l2'length-1), + scout => sov(low_pri_ex6_offset to low_pri_ex6_offset + low_pri_ex6_l2'length-1), + din => low_pri_ex6_d, + dout => low_pri_ex6_l2); +xu_iu_ex6_ppc_cpl_reg: tri_rlmreg_p + generic map (width => xu_iu_ex6_ppc_cpl_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_iu_ex6_ppc_cpl_offset to xu_iu_ex6_ppc_cpl_offset + xu_iu_ex6_ppc_cpl_l2'length-1), + scout => sov(xu_iu_ex6_ppc_cpl_offset to xu_iu_ex6_ppc_cpl_offset + xu_iu_ex6_ppc_cpl_l2'length-1), + din => xu_iu_ex6_ppc_cpl_d, + dout => xu_iu_ex6_ppc_cpl_l2); +event_bus_enable_d <= pc_iu_event_bus_enable; +event_enable_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(event_bus_enable_offset), + scout => sov(event_bus_enable_offset), + din => event_bus_enable_d, + dout => event_bus_enable_q); +trace_bus_enable_d <= pc_iu_trace_bus_enable; +trace_enable_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(trace_bus_enable_offset), + scout => sov(trace_bus_enable_offset), + din => trace_bus_enable_d, + dout => trace_bus_enable_q); +perf_event: tri_rlmreg_p + generic map (width => perf_event_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => event_bus_enable_q, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(perf_event_offset to perf_event_offset + perf_event_l2'length-1), + scout => sov(perf_event_offset to perf_event_offset + perf_event_l2'length-1), + din => perf_event_d, + dout => perf_event_l2); +fiss_dbg_data_latch: tri_rlmreg_p + generic map (width => fiss_dbg_data_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => trace_bus_enable_q, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(fiss_dbg_data_offset to fiss_dbg_data_offset + fiss_dbg_data_l2'length-1), + scout => sov(fiss_dbg_data_offset to fiss_dbg_data_offset + fiss_dbg_data_l2'length-1), + din => fiss_dbg_data_d, + dout => fiss_dbg_data_l2); +spare_latch: tri_rlmreg_p + generic map (width => spare_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(spare_offset to spare_offset + spare_l2'length-1), + scout => sov(spare_offset to spare_offset + spare_l2'length-1), + din => spare_l2, + dout => spare_l2); +rf0_str_val: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(rf0_str_val_offset), + scout => sov(rf0_str_val_offset), + din => rf0_str_val_d, + dout => rf0_str_val_l2); +rf0_ldst_val: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(rf0_ldst_val_offset), + scout => sov(rf0_ldst_val_offset), + din => rf0_ldst_val_d, + dout => rf0_ldst_val_l2); +rf0_ldst_tid: tri_rlmreg_p + generic map (width => rf0_ldst_tid_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf0_ldst_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(rf0_ldst_tid_offset to rf0_ldst_tid_offset + rf0_ldst_tid_l2'length-1), + scout => sov(rf0_ldst_tid_offset to rf0_ldst_tid_offset + rf0_ldst_tid_l2'length-1), + din => rf0_ldst_tid_d, + dout => rf0_ldst_tid_l2); +rf0_ldst_tag: tri_rlmreg_p + generic map (width => rf0_ldst_tag_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf0_ldst_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(rf0_ldst_tag_offset to rf0_ldst_tag_offset + rf0_ldst_tag_l2'length-1), + scout => sov(rf0_ldst_tag_offset to rf0_ldst_tag_offset + rf0_ldst_tag_l2'length-1), + din => rf0_ldst_tag_d, + dout => rf0_ldst_tag_l2); +--added for priority mapping +rf0_took_latch: tri_rlmreg_p + generic map (init => 65, expand_type => expand_type, width => 12) + port map ( + nclk => nclk, + act => tiup, + vd => vdd, + gd => gnd, + forcee => forcee, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(rf0_took_offset to rf0_took_offset + 12-1), + scout => sov(rf0_took_offset to rf0_took_offset + 12-1), + din(00) => hi_did3no0_d, + din(01) => hi_did3no1_d, + din(02) => hi_did3no2_d, + din(03) => hi_did2no0_d, + din(04) => hi_did2no1_d, + din(05) => hi_did1no0_d, + din(06) => md_did3no0_d, + din(07) => md_did3no1_d, + din(08) => md_did3no2_d, + din(09) => md_did2no0_d, + din(10) => md_did2no1_d, + din(11) => md_did1no0_d, + dout(00) => hi_did3no0, + dout(01) => hi_did3no1, + dout(02) => hi_did3no2, + dout(03) => hi_did2no0, + dout(04) => hi_did2no1, + dout(05) => hi_did1no0, + dout(06) => md_did3no0, + dout(07) => md_did3no1, + dout(08) => md_did3no2, + dout(09) => md_did2no0, + dout(10) => md_did2no1, + dout(11) => md_did1no0 + ); +hi_did3no0_d <= pri_rand(0) when (spr_fiss_pri_rand_always or (spr_fiss_pri_rand_flush and or_reduce(xu_iu_is2_flush_tid(0 to 3)))) = '1' else hi_did3no0_din; +hi_did3no1_d <= pri_rand(1) when (spr_fiss_pri_rand_always or (spr_fiss_pri_rand_flush and or_reduce(xu_iu_is2_flush_tid(0 to 3)))) = '1' else hi_did3no1_din; +hi_did3no2_d <= pri_rand(2) when (spr_fiss_pri_rand_always or (spr_fiss_pri_rand_flush and or_reduce(xu_iu_is2_flush_tid(0 to 3)))) = '1' else hi_did3no2_din; +hi_did2no0_d <= pri_rand(3) when (spr_fiss_pri_rand_always or (spr_fiss_pri_rand_flush and or_reduce(xu_iu_is2_flush_tid(0 to 3)))) = '1' else hi_did2no0_din; +hi_did2no1_d <= pri_rand(4) when (spr_fiss_pri_rand_always or (spr_fiss_pri_rand_flush and or_reduce(xu_iu_is2_flush_tid(0 to 3)))) = '1' else hi_did2no1_din; +hi_did1no0_d <= pri_rand(5) when (spr_fiss_pri_rand_always or (spr_fiss_pri_rand_flush and or_reduce(xu_iu_is2_flush_tid(0 to 3)))) = '1' else hi_did1no0_din; +md_did3no0_d <= pri_rand(0) when (spr_fiss_pri_rand_always or (spr_fiss_pri_rand_flush and or_reduce(xu_iu_is2_flush_tid(0 to 3)))) = '1' else md_did3no0_din; +md_did3no1_d <= pri_rand(1) when (spr_fiss_pri_rand_always or (spr_fiss_pri_rand_flush and or_reduce(xu_iu_is2_flush_tid(0 to 3)))) = '1' else md_did3no1_din; +md_did3no2_d <= pri_rand(2) when (spr_fiss_pri_rand_always or (spr_fiss_pri_rand_flush and or_reduce(xu_iu_is2_flush_tid(0 to 3)))) = '1' else md_did3no2_din; +md_did2no0_d <= pri_rand(3) when (spr_fiss_pri_rand_always or (spr_fiss_pri_rand_flush and or_reduce(xu_iu_is2_flush_tid(0 to 3)))) = '1' else md_did2no0_din; +md_did2no1_d <= pri_rand(4) when (spr_fiss_pri_rand_always or (spr_fiss_pri_rand_flush and or_reduce(xu_iu_is2_flush_tid(0 to 3)))) = '1' else md_did2no1_din; +md_did1no0_d <= pri_rand(5) when (spr_fiss_pri_rand_always or (spr_fiss_pri_rand_flush and or_reduce(xu_iu_is2_flush_tid(0 to 3)))) = '1' else md_did1no0_din; +pri_rand(0 TO 5) <= "001000" when spr_fiss_pri_rand(0 to 4) = "00000" else + "100111" when spr_fiss_pri_rand(0 to 4) = "00001" else + "110111" when spr_fiss_pri_rand(0 to 4) = "00010" else + "000001" when spr_fiss_pri_rand(0 to 4) = "00011" else + "000110" when spr_fiss_pri_rand(0 to 4) = "00100" else + "001001" when spr_fiss_pri_rand(0 to 4) = "00101" else + "011000" when spr_fiss_pri_rand(0 to 4) = "00110" else + "111101" when spr_fiss_pri_rand(0 to 4) = "00111" else + "100101" when spr_fiss_pri_rand(0 to 4) = "01000" else + "010110" when spr_fiss_pri_rand(0 to 4) = "01001" else + "101101" when spr_fiss_pri_rand(0 to 4) = "01010" else + "111110" when spr_fiss_pri_rand(0 to 4) = "01011" else + "110110" when spr_fiss_pri_rand(0 to 4) = "01100" else + "101001" when spr_fiss_pri_rand(0 to 4) = "01101" else + "000000" when spr_fiss_pri_rand(0 to 4) = "01110" else + "111010" when spr_fiss_pri_rand(0 to 4) = "01111" else + "000111" when spr_fiss_pri_rand(0 to 4) = "10000" else + "111001" when spr_fiss_pri_rand(0 to 4) = "10001" else + "111000" when spr_fiss_pri_rand(0 to 4) = "10010" else + "011010" when spr_fiss_pri_rand(0 to 4) = "10011" else + "111111" when spr_fiss_pri_rand(0 to 4) = "10100" else + "010010" when spr_fiss_pri_rand(0 to 4) = "10101" else + "000010" when spr_fiss_pri_rand(0 to 4) = "10110" else + "000101" when spr_fiss_pri_rand(0 to 4) = "10111" else + "111111" when spr_fiss_pri_rand(0 to 4) = "11000" else + "000000" when spr_fiss_pri_rand(0 to 4) = "11001" else + "011010" when spr_fiss_pri_rand(0 to 4) = "11010" else + "100101" when spr_fiss_pri_rand(0 to 4) = "11011" else + "001001" when spr_fiss_pri_rand(0 to 4) = "11100" else + "110110" when spr_fiss_pri_rand(0 to 4) = "11101" else + "000111" when spr_fiss_pri_rand(0 to 4) = "11110" else + "111000" ; +----------------------------------------------------------------------- +-- hole delays for multiplier +----------------------------------------------------------------------- +hole0_nor2: hole0 <= not (hole0_b or xu_iu_is2_flush_tid(0)); +hole0_b <= not (((n_thread(0) and fdep_fiss_t0_is2_hole_delay(0)) or hole_delay0_l2(0)) and not uc_flush_tid_l2(0)); +hole_delay0_d(0) <= ((n_thread(0) and fdep_fiss_t0_is2_hole_delay(1)) or hole_delay0_l2(1)) and not uc_flush_tid_l2(0) and not xu_iu_is2_flush_tid(0); +hole_delay0_d(1) <= (n_thread(0) and fdep_fiss_t0_is2_hole_delay(2)) and not uc_flush_tid_l2(0) and not xu_iu_is2_flush_tid(0); +hole1_nor2: hole1 <= not (hole1_b or xu_iu_is2_flush_tid(1)); +hole1_b <= not (((n_thread(1) and fdep_fiss_t1_is2_hole_delay(0)) or hole_delay1_l2(0)) and not uc_flush_tid_l2(1)); +hole_delay1_d(0) <= ((n_thread(1) and fdep_fiss_t1_is2_hole_delay(1)) or hole_delay1_l2(1)) and not uc_flush_tid_l2(1) and not xu_iu_is2_flush_tid(1); +hole_delay1_d(1) <= (n_thread(1) and fdep_fiss_t1_is2_hole_delay(2)) and not uc_flush_tid_l2(1) and not xu_iu_is2_flush_tid(1); +hole2_nor2: hole2 <= not (hole2_b or xu_iu_is2_flush_tid(2)); +hole2_b <= not (((n_thread(2) and fdep_fiss_t2_is2_hole_delay(0)) or hole_delay2_l2(0)) and not uc_flush_tid_l2(2)); +hole_delay2_d(0) <= ((n_thread(2) and fdep_fiss_t2_is2_hole_delay(1)) or hole_delay2_l2(1)) and not uc_flush_tid_l2(2) and not xu_iu_is2_flush_tid(2); +hole_delay2_d(1) <= (n_thread(2) and fdep_fiss_t2_is2_hole_delay(2)) and not uc_flush_tid_l2(2) and not xu_iu_is2_flush_tid(2); +hole3_nor2: hole3 <= not (hole3_b or xu_iu_is2_flush_tid(3)); +hole3_b <= not (((n_thread(3) and fdep_fiss_t3_is2_hole_delay(0)) or hole_delay3_l2(0)) and not uc_flush_tid_l2(3)); +hole_delay3_d(0) <= ((n_thread(3) and fdep_fiss_t3_is2_hole_delay(1)) or hole_delay3_l2(1)) and not uc_flush_tid_l2(3) and not xu_iu_is2_flush_tid(3); +hole_delay3_d(1) <= (n_thread(3) and fdep_fiss_t3_is2_hole_delay(2)) and not uc_flush_tid_l2(3) and not xu_iu_is2_flush_tid(3); +----------------------------------------------------------------------- +-- early indicators +----------------------------------------------------------------------- +is1_dep_hit(0) <= not(fdep_fiss_t0_is1_xu_dep_hit_b) or not(i_axu_is1_dep_hit_t0_b); +is1_dep_hit(1) <= not(fdep_fiss_t1_is1_xu_dep_hit_b) or not(i_axu_is1_dep_hit_t1_b); +is1_dep_hit(2) <= not(fdep_fiss_t2_is1_xu_dep_hit_b) or not(i_axu_is1_dep_hit_t2_b); +is1_dep_hit(3) <= not(fdep_fiss_t3_is1_xu_dep_hit_b) or not(i_axu_is1_dep_hit_t3_b); +is2_vld_d(0) <= fdep_fiss_t0_is2early_vld and not is1_dep_hit(0) and not xu_iu_is2_flush_tid(0) and not uc_flush_tid_l2(0) when is2_stall(0) = '0' else + is2_vld_l2(0) and not xu_iu_is2_flush_tid(0) and not uc_flush_tid_l2(0); +is2_vld_d(1) <= fdep_fiss_t1_is2early_vld and not is1_dep_hit(1) and not xu_iu_is2_flush_tid(1) and not uc_flush_tid_l2(1) when is2_stall(1) = '0' else + is2_vld_l2(1) and not xu_iu_is2_flush_tid(1) and not uc_flush_tid_l2(1); +is2_vld_d(2) <= fdep_fiss_t2_is2early_vld and not is1_dep_hit(2) and not xu_iu_is2_flush_tid(2) and not uc_flush_tid_l2(2) when is2_stall(2) = '0' else + is2_vld_l2(2) and not xu_iu_is2_flush_tid(2) and not uc_flush_tid_l2(2); +is2_vld_d(3) <= fdep_fiss_t3_is2early_vld and not is1_dep_hit(3) and not xu_iu_is2_flush_tid(3) and not uc_flush_tid_l2(3) when is2_stall(3) = '0' else + is2_vld_l2(3) and not xu_iu_is2_flush_tid(3) and not uc_flush_tid_l2(3); +is2_stall(0) <= (not next_tid(0) and is2_vld_l2(0)) or (not i_afi_is2_take_t(0) and i_afd_is2_t0_instr_v); +is2_stall(1) <= (not next_tid(1) and is2_vld_l2(1)) or (not i_afi_is2_take_t(1) and i_afd_is2_t1_instr_v); +is2_stall(2) <= (not next_tid(2) and is2_vld_l2(2)) or (not i_afi_is2_take_t(2) and i_afd_is2_t2_instr_v); +is2_stall(3) <= (not next_tid(3) and is2_vld_l2(3)) or (not i_afi_is2_take_t(3) and i_afd_is2_t3_instr_v); +high_priority_valids <= high_pri_mask_l2; +med_priority_valids <= med_pri_mask_l2; +---- round robin high priority select +--?TABLE select_high LISTING(final) OPTIMIZE PARMS(ON-SET, OFF-SET); +--*INPUTS*======================*OUTPUTS*=============* +--| | | +--| high_pri_last_l2 | next_high_valid | +--| | high_priority_valids | | next_high_tid | +--| | | | | | | +--| | | | | | | +--| | | | | | | +--| 0123 0123 | | 0123 | +--*TYPE*========================+=====================+ +--| PPPP PPPP | P PPPP | +--*TERMS*=======================+=====================+ +--| 1000 0000 | 0 ---- | +--| 1000 -1-- | 1 0100 | +--| 1000 -01- | 1 0010 | +--| 1000 -001 | 1 0001 | +--| 1000 1000 | 1 1000 | +--| 0100 0000 | 0 ---- | +--| 0100 --1- | 1 0010 | +--| 0100 --01 | 1 0001 | +--| 0100 1-00 | 1 1000 | +--| 0100 0100 | 1 0100 | +--| 0010 0000 | 0 ---- | +--| 0010 ---1 | 1 0001 | +--| 0010 1--0 | 1 1000 | +--| 0010 01-0 | 1 0100 | +--| 0010 0010 | 1 0010 | +--| 0001 0000 | 0 ---- | +--| 0001 1--- | 1 1000 | +--| 0001 01-- | 1 0100 | +--| 0001 001- | 1 0010 | +--| 0001 0001 | 1 0001 | +--*END*=========================+=====================+ +--?TABLE END select_high; +---- round robin low priority select +--?TABLE select_low LISTING(final) OPTIMIZE PARMS(ON-SET, OFF-SET); +--*INPUTS*======================*OUTPUTS*=============* +--| | | +--| low_pri_last_l2 | next_low_valid | +--| | low_priority_valids | | next_low_tid | +--| | | | | | | +--| | | | | | | +--| | | | | | | +--| 0123 0123 | | 0123 | +--*TYPE*========================+=====================+ +--| PPPP PPPP | P PPPP | +--*TERMS*=======================+=====================+ +--| 1000 0000 | 0 ---- | +--| 1000 -1-- | 1 0100 | +--| 1000 -01- | 1 0010 | +--| 1000 -001 | 1 0001 | +--| 1000 1000 | 1 1000 | +--| 0100 0000 | 0 ---- | +--| 0100 --1- | 1 0010 | +--| 0100 --01 | 1 0001 | +--| 0100 1-00 | 1 1000 | +--| 0100 0100 | 1 0100 | +--| 0010 0000 | 0 ---- | +--| 0010 ---1 | 1 0001 | +--| 0010 1--0 | 1 1000 | +--| 0010 01-0 | 1 0100 | +--| 0010 0010 | 1 0010 | +--| 0001 0000 | 0 ---- | +--| 0001 1--- | 1 1000 | +--| 0001 01-- | 1 0100 | +--| 0001 001- | 1 0010 | +--| 0001 0001 | 1 0001 | +--*END*=========================+=====================+ +--?TABLE END select_low; +--?TABLE select_pri LISTING(final) OPTIMIZE PARMS(ON-SET, OFF-SET); +--*INPUTS*======================================================*OUTPUTS*===============* +--| | | +--| low_pri_en | | +--| | low_pri_last_l2 high_pri_last_l2 | next_low_valid | +--| | | low_priority_valids | high_priority_valids | | next_high_valid | +--| | | | | | | | | next_tid | +--| | | | | | | | | | | +--| | | | | | | | | | | +--| | 0123 0123 0123 0123 | | | 0123 | +--*TYPE*========================================================+=======================+ +--| S PPPP PPPP PPPP PPPP | P P SSSS | +--*TERMS*=======================================================+=======================+ +--| - ---- 0000 ---- 0000 | 0 0 0000 | +--| 1 ---- 0000 1000 -1-- | 0 1 0100 | +--| 1 ---- 0000 1000 -01- | 0 1 0010 | +--| 1 ---- 0000 1000 -001 | 0 1 0001 | +--| 1 ---- 0000 1000 1000 | 0 1 1000 | +--| 1 ---- 0000 0100 --1- | 0 1 0010 | +--| 1 ---- 0000 0100 --01 | 0 1 0001 | +--| 1 ---- 0000 0100 1-00 | 0 1 1000 | +--| 1 ---- 0000 0100 0100 | 0 1 0100 | +--| 1 ---- 0000 0010 ---1 | 0 1 0001 | +--| 1 ---- 0000 0010 1--0 | 0 1 1000 | +--| 1 ---- 0000 0010 01-0 | 0 1 0100 | +--| 1 ---- 0000 0010 0010 | 0 1 0010 | +--| 1 ---- 0000 0001 1--- | 0 1 1000 | +--| 1 ---- 0000 0001 01-- | 0 1 0100 | +--| 1 ---- 0000 0001 001- | 0 1 0010 | +--| 1 ---- 0000 0001 0001 | 0 1 0001 | +--| 1 1000 -1-- ---- ---- | 1 0 0100 | +--| 1 1000 -01- ---- ---- | 1 0 0010 | +--| 1 1000 -001 ---- ---- | 1 0 0001 | +--| 1 1000 1000 ---- ---- | 1 0 1000 | +--| 1 0100 --1- ---- ---- | 1 0 0010 | +--| 1 0100 --01 ---- ---- | 1 0 0001 | +--| 1 0100 1-00 ---- ---- | 1 0 1000 | +--| 1 0100 0100 ---- ---- | 1 0 0100 | +--| 1 0010 ---1 ---- ---- | 1 0 0001 | +--| 1 0010 1--0 ---- ---- | 1 0 1000 | +--| 1 0010 01-0 ---- ---- | 1 0 0100 | +--| 1 0010 0010 ---- ---- | 1 0 0010 | +--| 1 0001 1--- ---- ---- | 1 0 1000 | +--| 1 0001 01-- ---- ---- | 1 0 0100 | +--| 1 0001 001- ---- ---- | 1 0 0010 | +--| 1 0001 0001 ---- ---- | 1 0 0001 | +--| 0 1000 -1-- ---- 0000 | 1 0 0100 | +--| 0 1000 -01- ---- 0000 | 1 0 0010 | +--| 0 1000 -001 ---- 0000 | 1 0 0001 | +--| 0 1000 1000 ---- 0000 | 1 0 1000 | +--| 0 0100 --1- ---- 0000 | 1 0 0010 | +--| 0 0100 --01 ---- 0000 | 1 0 0001 | +--| 0 0100 1-00 ---- 0000 | 1 0 1000 | +--| 0 0100 0100 ---- 0000 | 1 0 0100 | +--| 0 0010 ---1 ---- 0000 | 1 0 0001 | +--| 0 0010 1--0 ---- 0000 | 1 0 1000 | +--| 0 0010 01-0 ---- 0000 | 1 0 0100 | +--| 0 0010 0010 ---- 0000 | 1 0 0010 | +--| 0 0001 1--- ---- 0000 | 1 0 1000 | +--| 0 0001 01-- ---- 0000 | 1 0 0100 | +--| 0 0001 001- ---- 0000 | 1 0 0010 | +--| 0 0001 0001 ---- 0000 | 1 0 0001 | +--| 0 ---- ---- 1000 -1-- | 0 1 0100 | +--| 0 ---- ---- 1000 -01- | 0 1 0010 | +--| 0 ---- ---- 1000 -001 | 0 1 0001 | +--| 0 ---- ---- 1000 1000 | 0 1 1000 | +--| 0 ---- ---- 0100 --1- | 0 1 0010 | +--| 0 ---- ---- 0100 --01 | 0 1 0001 | +--| 0 ---- ---- 0100 1-00 | 0 1 1000 | +--| 0 ---- ---- 0100 0100 | 0 1 0100 | +--| 0 ---- ---- 0010 ---1 | 0 1 0001 | +--| 0 ---- ---- 0010 1--0 | 0 1 1000 | +--| 0 ---- ---- 0010 01-0 | 0 1 0100 | +--| 0 ---- ---- 0010 0010 | 0 1 0010 | +--| 0 ---- ---- 0001 1--- | 0 1 1000 | +--| 0 ---- ---- 0001 01-- | 0 1 0100 | +--| 0 ---- ---- 0001 001- | 0 1 0010 | +--| 0 ---- ---- 0001 0001 | 0 1 0001 | +--*END*=========================================================+=======================+ +--?TABLE END select_pri; +--?TABLE select_pri LISTING(final) OPTIMIZE PARMS(ON-SET, OFF-SET); +--*INPUTS*=====================================================*OUTPUTS*==============* +--| | | +--| | | +--| med_pri_last_l2 high_pri_last_l2 | next_med_valid | +--| | med_priority_valids | high_priority_valids | | next_high_valid | +--| | | | | | | | next_tid | +--| | | | | | | | | | +--| | | | | | | | | | +--| 0123 0123 0123 0123 | | | 0123 | +--*TYPE*=======================================================+======================+ +--| PPPP PPPP PPPP PPPP | P P SSSS | +--*TERMS*======================================================+======================+ +--| ---- 0000 ---- 0000 | 0 0 0000 | +--| 1000 -1-- ---- 0000 | 1 0 0100 | +--| 1000 -01- ---- 0000 | 1 0 0010 | +--| 1000 -001 ---- 0000 | 1 0 0001 | +--| 1000 1000 ---- 0000 | 1 0 1000 | +--| 0100 --1- ---- 0000 | 1 0 0010 | +--| 0100 --01 ---- 0000 | 1 0 0001 | +--| 0100 1-00 ---- 0000 | 1 0 1000 | +--| 0100 0100 ---- 0000 | 1 0 0100 | +--| 0010 ---1 ---- 0000 | 1 0 0001 | +--| 0010 1--0 ---- 0000 | 1 0 1000 | +--| 0010 01-0 ---- 0000 | 1 0 0100 | +--| 0010 0010 ---- 0000 | 1 0 0010 | +--| 0001 1--- ---- 0000 | 1 0 1000 | +--| 0001 01-- ---- 0000 | 1 0 0100 | +--| 0001 001- ---- 0000 | 1 0 0010 | +--| 0001 0001 ---- 0000 | 1 0 0001 | +--| ---- ---- 1000 -1-- | 0 1 0100 | +--| ---- ---- 1000 -01- | 0 1 0010 | +--| ---- ---- 1000 -001 | 0 1 0001 | +--| ---- ---- 1000 1000 | 0 1 1000 | +--| ---- ---- 0100 --1- | 0 1 0010 | +--| ---- ---- 0100 --01 | 0 1 0001 | +--| ---- ---- 0100 1-00 | 0 1 1000 | +--| ---- ---- 0100 0100 | 0 1 0100 | +--| ---- ---- 0010 ---1 | 0 1 0001 | +--| ---- ---- 0010 1--0 | 0 1 1000 | +--| ---- ---- 0010 01-0 | 0 1 0100 | +--| ---- ---- 0010 0010 | 0 1 0010 | +--| ---- ---- 0001 1--- | 0 1 1000 | +--| ---- ---- 0001 01-- | 0 1 0100 | +--| ---- ---- 0001 001- | 0 1 0010 | +--| ---- ---- 0001 0001 | 0 1 0001 | +--*END*========================================================+======================+ +--?TABLE END select_pri; +--?TABLE select_pri LISTING(final) OPTIMIZE PARMS(ON-SET, OFF-SET); +--*INPUTS*=====================================================*OUTPUTS*===========* +--| | | +--| | | +--| med_pri_last_l2 high_pri_last_l2 | | +--| | med_priority_valids | high_priority_valids | | +--| | | | | | next_tid | +--| | | | | | | | +--| | | | | | | | +--| 0123 0123 0123 0123 | 0123 | +--*TYPE*=======================================================+===================+ +--| PPPP PPPP PPPP PPPP | SSSS | +--*TERMS*======================================================+===================+ +--| ---- 0000 ---- 0000 | 0000 | +--| 1000 -1-- ---- 0000 | 0100 | +--| 1000 -01- ---- 0000 | 0010 | +--| 1000 -001 ---- 0000 | 0001 | +--| 1000 1000 ---- 0000 | 1000 | +--| 0100 --1- ---- 0000 | 0010 | +--| 0100 --01 ---- 0000 | 0001 | +--| 0100 1-00 ---- 0000 | 1000 | +--| 0100 0100 ---- 0000 | 0100 | +--| 0010 ---1 ---- 0000 | 0001 | +--| 0010 1--0 ---- 0000 | 1000 | +--| 0010 01-0 ---- 0000 | 0100 | +--| 0010 0010 ---- 0000 | 0010 | +--| 0001 1--- ---- 0000 | 1000 | +--| 0001 01-- ---- 0000 | 0100 | +--| 0001 001- ---- 0000 | 0010 | +--| 0001 0001 ---- 0000 | 0001 | +--| ---- ---- 1000 -1-- | 0100 | +--| ---- ---- 1000 -01- | 0010 | +--| ---- ---- 1000 -001 | 0001 | +--| ---- ---- 1000 1000 | 1000 | +--| ---- ---- 0100 --1- | 0010 | +--| ---- ---- 0100 --01 | 0001 | +--| ---- ---- 0100 1-00 | 1000 | +--| ---- ---- 0100 0100 | 0100 | +--| ---- ---- 0010 ---1 | 0001 | +--| ---- ---- 0010 1--0 | 1000 | +--| ---- ---- 0010 01-0 | 0100 | +--| ---- ---- 0010 0010 | 0010 | +--| ---- ---- 0001 1--- | 1000 | +--| ---- ---- 0001 01-- | 0100 | +--| ---- ---- 0001 001- | 0010 | +--| ---- ---- 0001 0001 | 0001 | +--*END*========================================================+===================+ +--?TABLE END select_pri; +--replaced priority table with mapped books +highpri_v_b0 <= not high_priority_valids; +medpri_v_b0 <= not med_priority_valids; +-- selection priority among high priority threads only +highpri0v_inv: highpri_v(0) <= not highpri_v_b0(0); +highpri1v_inv: highpri_v(1) <= not highpri_v_b0(1); +highpri2v_inv: highpri_v(2) <= not highpri_v_b0(2); +highpri3v_inv: highpri_v(3) <= not highpri_v_b0(3); +highpri0vb_inv: highpri_v_b(0) <= not highpri_v(0); +highpri1vb_inv: highpri_v_b(1) <= not highpri_v(1); +highpri2vb_inv: highpri_v_b(2) <= not highpri_v(2); +highpri3vb_inv: highpri_v_b(3) <= not highpri_v(3); +hi_sel_nor23: hi_sel(3) <= not (highpri_v_b(3) or hi_later(3)); +hi_sel_nand33: hi_later(3) <= not (hi_l30 and hi_l31 and hi_l32); +hi_sel_nand230: hi_l30 <= not (hi_did3no0 and highpri_v(0)); +hi_sel_nand231: hi_l31 <= not (hi_did3no1 and highpri_v(1)); +hi_sel_nand232: hi_l32 <= not (hi_did3no2 and highpri_v(2)); +hi_sel_nor22: hi_sel(2) <= not (highpri_v_b(2) or hi_later(2)); +hi_sel_nand32: hi_later(2) <= not (hi_l23 and hi_l20 and hi_l21); +hi_sel_nand223: hi_l23 <= not (hi_did2no3 and highpri_v(3)); +hi_sel_nand220: hi_l20 <= not (hi_did2no0 and highpri_v(0)); +hi_sel_nand221: hi_l21 <= not (hi_did2no1 and highpri_v(1)); +hi_sel_nor21: hi_sel(1) <= not (highpri_v_b(1) or hi_later(1)); +hi_sel_nand31: hi_later(1) <= not (hi_l12 and hi_l13 and hi_l10); +hi_sel_nand212: hi_l12 <= not (hi_did1no2 and highpri_v(2)); +hi_sel_nand213: hi_l13 <= not (hi_did1no3 and highpri_v(3)); +hi_sel_nand210: hi_l10 <= not (hi_did1no0 and highpri_v(0)); +hi_sel_nor20: hi_sel(0) <= not (highpri_v_b(0) or hi_later(0)); +hi_sel_nand30: hi_later(0) <= not (hi_l01 and hi_l02 and hi_l03); +hi_sel_nand201: hi_l01 <= not (hi_did0no1 and highpri_v(1)); +hi_sel_nand202: hi_l02 <= not (hi_did0no2 and highpri_v(2)); +hi_sel_nand203: hi_l03 <= not (hi_did0no3 and highpri_v(3)); +-- selection priority among med priority threads only +medpri0v_inv: medpri_v(0) <= not medpri_v_b0(0); +medpri1v_inv: medpri_v(1) <= not medpri_v_b0(1); +medpri2v_inv: medpri_v(2) <= not medpri_v_b0(2); +medpri3v_inv: medpri_v(3) <= not medpri_v_b0(3); +medpri0vb_inv: medpri_v_b(0) <= not medpri_v(0); +medpri1vb_inv: medpri_v_b(1) <= not medpri_v(1); +medpri2vb_inv: medpri_v_b(2) <= not medpri_v(2); +medpri3vb_inv: medpri_v_b(3) <= not medpri_v(3); +md_sel_nor23: md_sel(3) <= not (medpri_v_b(3) or md_later(3)); +md_sel_nand33: md_later(3) <= not (md_l30 and md_l31 and md_l32); +md_sel_nand230: md_l30 <= not (md_did3no0 and medpri_v(0)); +md_sel_nand231: md_l31 <= not (md_did3no1 and medpri_v(1)); +md_sel_nand232: md_l32 <= not (md_did3no2 and medpri_v(2)); +md_sel_nor22: md_sel(2) <= not (medpri_v_b(2) or md_later(2)); +md_sel_nand32: md_later(2) <= not (md_l23 and md_l20 and md_l21); +md_sel_nand223: md_l23 <= not (md_did2no3 and medpri_v(3)); +md_sel_nand220: md_l20 <= not (md_did2no0 and medpri_v(0)); +md_sel_nand221: md_l21 <= not (md_did2no1 and medpri_v(1)); +md_sel_nor21: md_sel(1) <= not (medpri_v_b(1) or md_later(1)); +md_sel_nand31: md_later(1) <= not (md_l12 and md_l13 and md_l10); +md_sel_nand212: md_l12 <= not (md_did1no2 and medpri_v(2)); +md_sel_nand213: md_l13 <= not (md_did1no3 and medpri_v(3)); +md_sel_nand210: md_l10 <= not (md_did1no0 and medpri_v(0)); +md_sel_nor20: md_sel(0) <= not (medpri_v_b(0) or md_later(0)); +md_sel_nand30: md_later(0) <= not (md_l01 and md_l02 and md_l03); +md_sel_nand201: md_l01 <= not (md_did0no1 and medpri_v(1)); +md_sel_nand202: md_l02 <= not (md_did0no2 and medpri_v(2)); +md_sel_nand203: md_l03 <= not (md_did0no3 and medpri_v(3)); +-- reorder high +hi_sel_inv0: hi_sel_b(0) <= not hi_sel(0); +hi_sel_inv1: hi_sel_b(1) <= not hi_sel(1); +hi_sel_inv2: hi_sel_b(2) <= not hi_sel(2); +hi_sel_inv3: hi_sel_b(3) <= not hi_sel(3); +hi_reordf_nand230: hi_did3no0_din <= not (hi_sel_b(3) and hi_n230); +hi_reordf_nand231: hi_did3no1_din <= not (hi_sel_b(3) and hi_n231); +hi_reordf_nand232: hi_did3no2_din <= not (hi_sel_b(3) and hi_n232); +hi_reord_nand230: hi_n230 <= not (hi_sel_b(0) and hi_did3no0); +hi_reord_nand231: hi_n231 <= not (hi_sel_b(1) and hi_did3no1); +hi_reord_nand232: hi_n232 <= not (hi_sel_b(2) and hi_did3no2); +hi_reordf_nand220: hi_did2no0_din <= not(hi_sel_b(2) and hi_n220); +hi_reord_nand220: hi_n220 <= not(hi_sel_b(0) and hi_did2no0); +hi_reordf_nand221: hi_did2no1_din <= not(hi_sel_b(2) and hi_n221); +hi_reord_nand221: hi_n221 <= not(hi_sel_b(1) and hi_did2no1); +hi_reord_inv23: hi_did2no3 <= not hi_did3no2; +hi_reordf_nand210: hi_did1no0_din <= not(hi_sel_b(1) and hi_n210); +hi_reord_nand210: hi_n210 <= not(hi_sel_b(0) and hi_did1no0); +hi_reord_inv12: hi_did1no2 <= not hi_did2no1; +hi_reord_inv13: hi_did1no3 <= not hi_did3no1; +hi_reord_inv01: hi_did0no1 <= not hi_did1no0; +hi_reord_inv02: hi_did0no2 <= not hi_did2no0; +hi_reord_inv03: hi_did0no3 <= not hi_did3no0; +-- reorder med +md_sel_inv0: md_sel_b(0) <= not md_sel(0); +md_sel_inv1: md_sel_b(1) <= not md_sel(1); +md_sel_inv2: md_sel_b(2) <= not md_sel(2); +md_sel_inv3: md_sel_b(3) <= not md_sel(3); +md_reordf_nand230: md_did3no0_din <= not (md_sel_b(3) and md_n230); +md_reordf_nand231: md_did3no1_din <= not (md_sel_b(3) and md_n231); +md_reordf_nand232: md_did3no2_din <= not (md_sel_b(3) and md_n232); +md_reord_nand230: md_n230 <= not (md_sel_b(0) and md_did3no0); +md_reord_nand231: md_n231 <= not (md_sel_b(1) and md_did3no1); +md_reord_nand232: md_n232 <= not (md_sel_b(2) and md_did3no2); +md_reordf_nand220: md_did2no0_din <= not(md_sel_b(2) and md_n220); +md_reord_nand220: md_n220 <= not(md_sel_b(0) and md_did2no0); +md_reordf_nand221: md_did2no1_din <= not(md_sel_b(2) and md_n221); +md_reord_nand221: md_n221 <= not(md_sel_b(1) and md_did2no1); +md_reord_inv23: md_did2no3 <= not md_did3no2; +md_reordf_nand210: md_did1no0_din <= not(md_sel_b(1) and md_n210); +md_reord_nand210: md_n210 <= not(md_sel_b(0) and md_did1no0); +md_reord_inv12: md_did1no2 <= not md_did2no1; +md_reord_inv13: md_did1no3 <= not md_did3no1; +md_reord_inv01: md_did0no1 <= not md_did1no0; +md_reord_inv02: md_did0no2 <= not md_did2no0; +md_reord_inv03: md_did0no3 <= not md_did3no0; +--issue select +nohi_nor21: no_hi_v_n01 <= not (highpri_v(0) or highpri_v(1)); +nohi_nor22: no_hi_v_n23 <= not (highpri_v(2) or highpri_v(3)); +nohi_nand2: no_hi_v_b <= not (no_hi_v_n01 and no_hi_v_n23); +nohi_inv: no_hi_v <= not (no_hi_v_b); +isssel0_inv: issselhi_b(0) <= not (hi_sel(0)); +isssel1_inv: issselhi_b(1) <= not (hi_sel(1)); +isssel2_inv: issselhi_b(2) <= not (hi_sel(2)); +isssel3_inv: issselhi_b(3) <= not (hi_sel(3)); +isssel0_bnand2: issselmd_b(0) <= not (md_sel(0) and no_hi_v); +isssel1_bnand2: issselmd_b(1) <= not (md_sel(1) and no_hi_v); +isssel2_bnand2: issselmd_b(2) <= not (md_sel(2) and no_hi_v); +isssel3_bnand2: issselmd_b(3) <= not (md_sel(3) and no_hi_v); +isssel0_fnand2: take(0) <= not (issselhi_b(0) and issselmd_b(0)); +isssel1_fnand2: take(1) <= not (issselhi_b(1) and issselmd_b(1)); +isssel2_fnand2: take(2) <= not (issselhi_b(2) and issselmd_b(2)); +isssel3_fnand2: take(3) <= not (issselhi_b(3) and issselmd_b(3)); +nexttid0_fnand2: next_tid(0) <= not (issselhi_b(0) and issselmd_b(0)); +nexttid1_fnand2: next_tid(1) <= not (issselhi_b(1) and issselmd_b(1)); +nexttid2_fnand2: next_tid(2) <= not (issselhi_b(2) and issselmd_b(2)); +nexttid3_fnand2: next_tid(3) <= not (issselhi_b(3) and issselmd_b(3)); +take0_rp1_inv: take_b(0) <= not(take(0)); +take1_rp1_inv: take_b(1) <= not(take(1)); +take2_rp1_inv: take_b(2) <= not(take(2)); +take3_rp1_inv: take_b(3) <= not(take(3)); +take0_rp2_inv: fiss_fdep_is2_take0 <= not(take_b(0)); +take1_rp2_inv: fiss_fdep_is2_take1 <= not(take_b(1)); +take2_rp2_inv: fiss_fdep_is2_take2 <= not(take_b(2)); +take3_rp2_inv: fiss_fdep_is2_take3 <= not(take_b(3)); +-- end of mapping section +xu_iu_ex6_ppc_cpl_d <= xu_iu_ex5_ppc_cpl; +low_pri_en(0) <= low_pri_counter0_l2(0 to 5) = low_pri_max0_l2(0 to 5) and not (next_tid(0) = '1' or i_afi_is2_take_t(0) = '1') and not low_pri_val(0); +low_pri_en(1) <= low_pri_counter1_l2(0 to 5) = low_pri_max1_l2(0 to 5) and not (next_tid(1) = '1' or i_afi_is2_take_t(1) = '1') and not low_pri_val(1); +low_pri_en(2) <= low_pri_counter2_l2(0 to 5) = low_pri_max2_l2(0 to 5) and not (next_tid(2) = '1' or i_afi_is2_take_t(2) = '1') and not low_pri_val(2); +low_pri_en(3) <= low_pri_counter3_l2(0 to 5) = low_pri_max3_l2(0 to 5) and not (next_tid(3) = '1' or i_afi_is2_take_t(3) = '1') and not low_pri_val(3); +low_pri_counter0_d(0 TO 7) <= "00000000" when xu_iu_ex6_ppc_cpl_l2(0) = '1' else + low_pri_counter0_l2 + 1; +low_pri_counter1_d(0 TO 7) <= "00000000" when xu_iu_ex6_ppc_cpl_l2(1) = '1' else + low_pri_counter1_l2 + 1; +low_pri_counter2_d(0 TO 7) <= "00000000" when xu_iu_ex6_ppc_cpl_l2(2) = '1' else + low_pri_counter2_l2 + 1; +low_pri_counter3_d(0 TO 7) <= "00000000" when xu_iu_ex6_ppc_cpl_l2(3) = '1' else + low_pri_counter3_l2 + 1; +low_pri_counter0_act <= (xu_iu_ex6_ppc_cpl_l2(0) = '1') or (low_pri_counter0_l2(0 to 5) /= low_pri_max0_l2(0 to 5)); +low_pri_counter1_act <= (xu_iu_ex6_ppc_cpl_l2(1) = '1') or (low_pri_counter1_l2(0 to 5) /= low_pri_max1_l2(0 to 5)); +low_pri_counter2_act <= (xu_iu_ex6_ppc_cpl_l2(2) = '1') or (low_pri_counter2_l2(0 to 5) /= low_pri_max2_l2(0 to 5)); +low_pri_counter3_act <= (xu_iu_ex6_ppc_cpl_l2(3) = '1') or (low_pri_counter3_l2(0 to 5) /= low_pri_max3_l2(0 to 5)); +low_pri_rf0_d(0 TO 3) <= (next_tid(0 to 3) or i_afi_is2_take_t(0 to 3)) and not xu_iu_is2_flush_tid(0 to 3); +low_pri_rf1_d(0 TO 3) <= low_pri_rf0_l2(0 to 3) and not xu_iu_rf0_flush_tid(0 to 3); +low_pri_ex1_d(0 TO 3) <= low_pri_rf1_l2(0 to 3) and not xu_iu_rf1_flush_tid(0 to 3); +low_pri_ex2_d(0 TO 3) <= low_pri_ex1_l2(0 to 3) and not xu_iu_ex1_flush_tid(0 to 3); +low_pri_ex3_d(0 TO 3) <= low_pri_ex2_l2(0 to 3) and not xu_iu_ex2_flush_tid(0 to 3); +low_pri_ex4_d(0 TO 3) <= low_pri_ex3_l2(0 to 3) and not xu_iu_ex3_flush_tid(0 to 3); +low_pri_ex5_d(0 TO 3) <= low_pri_ex4_l2(0 to 3) and not xu_iu_ex4_flush_tid(0 to 3); +low_pri_ex6_d(0 TO 3) <= low_pri_ex5_l2(0 to 3) and not xu_iu_ex5_flush_tid(0 to 3); +low_pri_rf1_act <= or_reduce(low_pri_rf0_l2(0 to 3)) or or_reduce(low_pri_rf1_l2(0 to 3)); +low_pri_ex1_act <= or_reduce(low_pri_rf1_l2(0 to 3)) or or_reduce(low_pri_ex1_l2(0 to 3)); +low_pri_ex2_act <= or_reduce(low_pri_ex1_l2(0 to 3)) or or_reduce(low_pri_ex2_l2(0 to 3)); +low_pri_ex3_act <= or_reduce(low_pri_ex2_l2(0 to 3)) or or_reduce(low_pri_ex3_l2(0 to 3)); +low_pri_ex4_act <= or_reduce(low_pri_ex3_l2(0 to 3)) or or_reduce(low_pri_ex4_l2(0 to 3)); +low_pri_ex5_act <= or_reduce(low_pri_ex4_l2(0 to 3)) or or_reduce(low_pri_ex5_l2(0 to 3)); +low_pri_ex6_act <= or_reduce(low_pri_ex5_l2(0 to 3)) or or_reduce(low_pri_ex6_l2(0 to 3)); +low_pri_val(0 TO 3) <= low_pri_rf0_l2(0 to 3) or + low_pri_rf1_l2(0 to 3) or + low_pri_ex1_l2(0 to 3) or + low_pri_ex2_l2(0 to 3) or + low_pri_ex3_l2(0 to 3) or + low_pri_ex4_l2(0 to 3) or + low_pri_ex5_l2(0 to 3) or + low_pri_ex6_l2(0 to 3) ; +----------------------------------------------------------------------- +-- need hole +----------------------------------------------------------------------- +xu_iu_need_hole_d <= xu_iu_need_hole; +xu_iu_xucr0_rel_d <= xu_iu_xucr0_rel; +an_ac_back_inv_d <= an_ac_back_inv; +an_ac_back_inv_target_d <= an_ac_back_inv_target; +gap_l2_rel_hole <= an_ac_reld_data_vld and not an_ac_reld_core_tag(1) and not an_ac_reld_ditc and not dcache_rel_tag_2nd_beat; +gap_l2_rel_hole_dly1_d <= gap_l2_rel_hole; +gap_l2_rel_hole_dly2_d <= gap_l2_rel_hole_dly1_l2; +gap_l2_tag_dly1_d <= an_ac_reld_core_tag(2 to 4); +gap_l2_tag_dly2_d <= gap_l2_tag_dly1_l2; +dcache_rel_tag_2nd_beat <= (gap_l2_tag_dly2_l2(2 to 4) = an_ac_reld_core_tag(2 to 4)) and gap_l2_rel_hole_dly2_l2; +dcache_rel_hole <= (gap_l2_rel_hole and not xu_iu_xucr0_rel_l2) or + (an_ac_reld_data_coming and xu_iu_xucr0_rel_l2); +dcache_binv_hole <= an_ac_back_inv_l2 and an_ac_back_inv_target_l2; +need_hole <= dcache_binv_hole or dcache_rel_hole or xu_iu_need_hole_l2; +----------------------------------------------------------------------- +-- SPR settings +----------------------------------------------------------------------- +high_pri_mask_din <= spr_high_mask_l2 or low_pri_en; +med_pri_mask_din <= spr_med_mask_l2 and not low_pri_en; +high_pri_mask_d <= gate(is2_vld_d and high_pri_mask_din, not (hole0 or hole1 or hole2 or hole3 or need_hole)); +med_pri_mask_d <= gate(is2_vld_d and med_pri_mask_din, not (hole0 or hole1 or hole2 or hole3 or need_hole)); +iu_au_hi_pri_mask <= high_pri_mask_din; +iu_au_md_pri_mask <= med_pri_mask_din; +low_pri_max0_d <= spr_fiss_count0_max; +low_pri_max1_d <= spr_fiss_count1_max; +low_pri_max2_d <= spr_fiss_count2_max; +low_pri_max3_d <= spr_fiss_count3_max; +spr_high_mask_d <= spr_issue_high_mask; +spr_med_mask_d <= spr_issue_med_mask; +----------------------------------------------------------------------- +-- issue muxing +----------------------------------------------------------------------- +n_thread <= next_tid; +-- change all to proper 1-hot muxes +int_is2_vld <= (not xu_iu_is2_flush_tid(0) and not uc_flush_tid_l2(0) and n_thread(0)) or + (not xu_iu_is2_flush_tid(1) and not uc_flush_tid_l2(1) and n_thread(1)) or + (not xu_iu_is2_flush_tid(2) and not uc_flush_tid_l2(2) and n_thread(2)) or + (not xu_iu_is2_flush_tid(3) and not uc_flush_tid_l2(3) and n_thread(3)) ; +iss_is2_vld <= (not uc_flush_tid_l2(0) and n_thread(0)) or + (not uc_flush_tid_l2(1) and n_thread(1)) or + (not uc_flush_tid_l2(2) and n_thread(2)) or + (not uc_flush_tid_l2(3) and n_thread(3)) ; +iu_xu_is2_instr_int <= gate(fdep_fiss_t0_is2_instr, n_thread(0)) or + gate(fdep_fiss_t1_is2_instr, n_thread(1)) or + gate(fdep_fiss_t2_is2_instr, n_thread(2)) or + gate(fdep_fiss_t3_is2_instr, n_thread(3)) ; +--xu is using these as standalone valids, so they should only propogate for a valid issue +iu_xu_is2_ta_vld <= (fdep_fiss_t0_is2_ta_vld and not fdep_fiss_t0_is2_to_ucode and not uc_flush_tid_l2(0) and n_thread(0)) or + (fdep_fiss_t1_is2_ta_vld and not fdep_fiss_t1_is2_to_ucode and not uc_flush_tid_l2(1) and n_thread(1)) or + (fdep_fiss_t2_is2_ta_vld and not fdep_fiss_t2_is2_to_ucode and not uc_flush_tid_l2(2) and n_thread(2)) or + (fdep_fiss_t3_is2_ta_vld and not fdep_fiss_t3_is2_to_ucode and not uc_flush_tid_l2(3) and n_thread(3)) ; +iu_xu_is2_ta <= gate(fdep_fiss_t0_is2_ta, n_thread(0)) or + gate(fdep_fiss_t1_is2_ta, n_thread(1)) or + gate(fdep_fiss_t2_is2_ta, n_thread(2)) or + gate(fdep_fiss_t3_is2_ta, n_thread(3)) ; +--xu is using these as standalone valids, so they should only propogate for a valid issue +iu_xu_is2_s1_vld <= (fdep_fiss_t0_is2_s1_vld and not uc_flush_tid_l2(0) and n_thread(0)) or + (fdep_fiss_t1_is2_s1_vld and not uc_flush_tid_l2(1) and n_thread(1)) or + (fdep_fiss_t2_is2_s1_vld and not uc_flush_tid_l2(2) and n_thread(2)) or + (fdep_fiss_t3_is2_s1_vld and not uc_flush_tid_l2(3) and n_thread(3)) ; +iu_xu_is2_s1 <= gate(fdep_fiss_t0_is2_s1, n_thread(0)) or + gate(fdep_fiss_t1_is2_s1, n_thread(1)) or + gate(fdep_fiss_t2_is2_s1, n_thread(2)) or + gate(fdep_fiss_t3_is2_s1, n_thread(3)) ; +--xu is using these as standalone valids, so they should only propogate for a valid issue +iu_xu_is2_s2_vld <= (fdep_fiss_t0_is2_s2_vld and not uc_flush_tid_l2(0) and n_thread(0)) or + (fdep_fiss_t1_is2_s2_vld and not uc_flush_tid_l2(1) and n_thread(1)) or + (fdep_fiss_t2_is2_s2_vld and not uc_flush_tid_l2(2) and n_thread(2)) or + (fdep_fiss_t3_is2_s2_vld and not uc_flush_tid_l2(3) and n_thread(3)) ; +iu_xu_is2_s2 <= gate(fdep_fiss_t0_is2_s2, n_thread(0)) or + gate(fdep_fiss_t1_is2_s2, n_thread(1)) or + gate(fdep_fiss_t2_is2_s2, n_thread(2)) or + gate(fdep_fiss_t3_is2_s2, n_thread(3)) ; +--xu is using these as standalone valids, so they should only propogate for a valid issue +iu_xu_is2_s3_vld <= (fdep_fiss_t0_is2_s3_vld and not uc_flush_tid_l2(0) and n_thread(0)) or + (fdep_fiss_t1_is2_s3_vld and not uc_flush_tid_l2(1) and n_thread(1)) or + (fdep_fiss_t2_is2_s3_vld and not uc_flush_tid_l2(2) and n_thread(2)) or + (fdep_fiss_t3_is2_s3_vld and not uc_flush_tid_l2(3) and n_thread(3)) ; +iu_xu_is2_s3 <= gate(fdep_fiss_t0_is2_s3, n_thread(0)) or + gate(fdep_fiss_t1_is2_s3, n_thread(1)) or + gate(fdep_fiss_t2_is2_s3, n_thread(2)) or + gate(fdep_fiss_t3_is2_s3, n_thread(3)) ; +iu_xu_is2_pred_update_int <= (fdep_fiss_t0_is2_pred_update and n_thread(0)) or + (fdep_fiss_t1_is2_pred_update and n_thread(1)) or + (fdep_fiss_t2_is2_pred_update and n_thread(2)) or + (fdep_fiss_t3_is2_pred_update and n_thread(3)) ; +iu_xu_is2_pred_update <= iu_xu_is2_pred_update_int; +iu_xu_is2_pred_taken_cnt_int <= gate(fdep_fiss_t0_is2_pred_taken_cnt, n_thread(0)) or + gate(fdep_fiss_t1_is2_pred_taken_cnt, n_thread(1)) or + gate(fdep_fiss_t2_is2_pred_taken_cnt, n_thread(2)) or + gate(fdep_fiss_t3_is2_pred_taken_cnt, n_thread(3)) ; +iu_xu_is2_pred_taken_cnt <= iu_xu_is2_pred_taken_cnt_int; +iu_xu_is2_gshare <= gate(fdep_fiss_t0_is2_gshare, n_thread(0)) or + gate(fdep_fiss_t1_is2_gshare, n_thread(1)) or + gate(fdep_fiss_t2_is2_gshare, n_thread(2)) or + gate(fdep_fiss_t3_is2_gshare, n_thread(3)) ; +iu_xu_is2_ifar <= gate(fdep_fiss_t0_is2_ifar, n_thread(0)) or + gate(fdep_fiss_t1_is2_ifar, n_thread(1)) or + gate(fdep_fiss_t2_is2_ifar, n_thread(2)) or + gate(fdep_fiss_t3_is2_ifar, n_thread(3)) ; +iu_xu_is2_error_int <= gate(fdep_fiss_t0_is2_error, n_thread(0)) or + gate(fdep_fiss_t1_is2_error, n_thread(1)) or + gate(fdep_fiss_t2_is2_error, n_thread(2)) or + gate(fdep_fiss_t3_is2_error, n_thread(3)) ; +iu_xu_is2_error <= iu_xu_is2_error_int; +int_is2_to_ucode <= (fdep_fiss_t0_is2_to_ucode and n_thread(0)) or + (fdep_fiss_t1_is2_to_ucode and n_thread(1)) or + (fdep_fiss_t2_is2_to_ucode and n_thread(2)) or + (fdep_fiss_t3_is2_to_ucode and n_thread(3)) ; +iu_xu_is2_is_ucode <= (fdep_fiss_t0_is2_is_ucode and n_thread(0)) or + (fdep_fiss_t1_is2_is_ucode and n_thread(1)) or + (fdep_fiss_t2_is2_is_ucode and n_thread(2)) or + (fdep_fiss_t3_is2_is_ucode and n_thread(3)) ; +iu_xu_is2_axu_ld_or_st_int <= (fdep_fiss_t0_is2_axu_ld_or_st and n_thread(0)) or + (fdep_fiss_t1_is2_axu_ld_or_st and n_thread(1)) or + (fdep_fiss_t2_is2_axu_ld_or_st and n_thread(2)) or + (fdep_fiss_t3_is2_axu_ld_or_st and n_thread(3)) ; +iu_xu_is2_axu_store_int <= (fdep_fiss_t0_is2_axu_store and n_thread(0)) or + (fdep_fiss_t1_is2_axu_store and n_thread(1)) or + (fdep_fiss_t2_is2_axu_store and n_thread(2)) or + (fdep_fiss_t3_is2_axu_store and n_thread(3)) ; +iu_xu_is2_axu_ldst_indexed <= (fdep_fiss_t0_is2_axu_ldst_indexed and n_thread(0)) or + (fdep_fiss_t1_is2_axu_ldst_indexed and n_thread(1)) or + (fdep_fiss_t2_is2_axu_ldst_indexed and n_thread(2)) or + (fdep_fiss_t3_is2_axu_ldst_indexed and n_thread(3)) ; +iu_xu_is2_axu_ldst_tag_int <= gate(fdep_fiss_t0_is2_axu_ldst_tag, n_thread(0)) or + gate(fdep_fiss_t1_is2_axu_ldst_tag, n_thread(1)) or + gate(fdep_fiss_t2_is2_axu_ldst_tag, n_thread(2)) or + gate(fdep_fiss_t3_is2_axu_ldst_tag, n_thread(3)) ; +iu_xu_is2_axu_ldst_size <= gate(fdep_fiss_t0_is2_axu_ldst_size, n_thread(0)) or + gate(fdep_fiss_t1_is2_axu_ldst_size, n_thread(1)) or + gate(fdep_fiss_t2_is2_axu_ldst_size, n_thread(2)) or + gate(fdep_fiss_t3_is2_axu_ldst_size, n_thread(3)) ; +iu_xu_is2_axu_ldst_update <= (fdep_fiss_t0_is2_axu_ldst_update and n_thread(0)) or + (fdep_fiss_t1_is2_axu_ldst_update and n_thread(1)) or + (fdep_fiss_t2_is2_axu_ldst_update and n_thread(2)) or + (fdep_fiss_t3_is2_axu_ldst_update and n_thread(3)) ; +iu_xu_is2_axu_ldst_extpid <= (fdep_fiss_t0_is2_axu_ldst_extpid and n_thread(0)) or + (fdep_fiss_t1_is2_axu_ldst_extpid and n_thread(1)) or + (fdep_fiss_t2_is2_axu_ldst_extpid and n_thread(2)) or + (fdep_fiss_t3_is2_axu_ldst_extpid and n_thread(3)) ; +iu_xu_is2_axu_ldst_forcealign <= (fdep_fiss_t0_is2_axu_ldst_forcealign and n_thread(0)) or + (fdep_fiss_t1_is2_axu_ldst_forcealign and n_thread(1)) or + (fdep_fiss_t2_is2_axu_ldst_forcealign and n_thread(2)) or + (fdep_fiss_t3_is2_axu_ldst_forcealign and n_thread(3)) ; +iu_xu_is2_axu_ldst_forceexcept <= (fdep_fiss_t0_is2_axu_ldst_forceexcept and n_thread(0)) or + (fdep_fiss_t1_is2_axu_ldst_forceexcept and n_thread(1)) or + (fdep_fiss_t2_is2_axu_ldst_forceexcept and n_thread(2)) or + (fdep_fiss_t3_is2_axu_ldst_forceexcept and n_thread(3)) ; +iu_xu_is2_axu_mftgpr <= (fdep_fiss_t0_is2_axu_mftgpr and n_thread(0)) or + (fdep_fiss_t1_is2_axu_mftgpr and n_thread(1)) or + (fdep_fiss_t2_is2_axu_mftgpr and n_thread(2)) or + (fdep_fiss_t3_is2_axu_mftgpr and n_thread(3)) ; +iu_xu_is2_axu_mffgpr <= (fdep_fiss_t0_is2_axu_mffgpr and n_thread(0)) or + (fdep_fiss_t1_is2_axu_mffgpr and n_thread(1)) or + (fdep_fiss_t2_is2_axu_mffgpr and n_thread(2)) or + (fdep_fiss_t3_is2_axu_mffgpr and n_thread(3)) ; +iu_xu_is2_axu_movedp <= (fdep_fiss_t0_is2_axu_movedp and n_thread(0)) or + (fdep_fiss_t1_is2_axu_movedp and n_thread(1)) or + (fdep_fiss_t2_is2_axu_movedp and n_thread(2)) or + (fdep_fiss_t3_is2_axu_movedp and n_thread(3)) ; +iu_xu_is2_axu_instr_type <= gate(fdep_fiss_t0_is2_axu_instr_type, n_thread(0)) or + gate(fdep_fiss_t1_is2_axu_instr_type, n_thread(1)) or + gate(fdep_fiss_t2_is2_axu_instr_type, n_thread(2)) or + gate(fdep_fiss_t3_is2_axu_instr_type, n_thread(3)) ; +iu_xu_is2_match <= (fdep_fiss_t0_is2_match and n_thread(0)) or + (fdep_fiss_t1_is2_match and n_thread(1)) or + (fdep_fiss_t2_is2_match and n_thread(2)) or + (fdep_fiss_t3_is2_match and n_thread(3)) ; +fiss_uc_is2_2ucode <= (fdep_fiss_t0_is2_2ucode and n_thread(0)) or + (fdep_fiss_t1_is2_2ucode and n_thread(1)) or + (fdep_fiss_t2_is2_2ucode and n_thread(2)) or + (fdep_fiss_t3_is2_2ucode and n_thread(3)) ; +fiss_uc_is2_2ucode_type <= (fdep_fiss_t0_is2_2ucode_type and n_thread(0)) or + (fdep_fiss_t1_is2_2ucode_type and n_thread(1)) or + (fdep_fiss_t2_is2_2ucode_type and n_thread(2)) or + (fdep_fiss_t3_is2_2ucode_type and n_thread(3)) ; +--make local version of uc_flush for timing. from iuq_uc.vhdl: +uc_flush_tid_d(0) <= n_thread(0) and fdep_fiss_t0_is2_to_ucode and not xu_iu_is2_flush_tid(0) and not uc_flush_tid_l2(0); +uc_flush_tid_d(1) <= n_thread(1) and fdep_fiss_t1_is2_to_ucode and not xu_iu_is2_flush_tid(1) and not uc_flush_tid_l2(1); +uc_flush_tid_d(2) <= n_thread(2) and fdep_fiss_t2_is2_to_ucode and not xu_iu_is2_flush_tid(2) and not uc_flush_tid_l2(2); +uc_flush_tid_d(3) <= n_thread(3) and fdep_fiss_t3_is2_to_ucode and not xu_iu_is2_flush_tid(3) and not uc_flush_tid_l2(3); +iu_xu_is2_vld_int <= iss_is2_vld and not int_is2_to_ucode; +iu_xu_is2_tid_int <= n_thread; +iu_xu_is2_vld <= iu_xu_is2_vld_int; +iu_xu_is2_tid <= iu_xu_is2_tid_int; +fiss_uc_is2_ucode_vld_int <= iss_is2_vld and int_is2_to_ucode; +fiss_uc_is2_ucode_vld <= fiss_uc_is2_ucode_vld_int; +iu_xu_is2_axu_store <= iu_xu_is2_axu_store_int; +iu_xu_is2_axu_ld_or_st <= iu_xu_is2_axu_ld_or_st_int; +iu_xu_is2_instr <= iu_xu_is2_instr_int; +iu_xu_is2_axu_ldst_tag <= iu_xu_is2_axu_ldst_tag_int; +rf0_str_val_d <= iu_xu_is2_axu_store_int; +rf0_ldst_val_d <= iu_xu_is2_axu_ld_or_st_int and int_is2_vld and not int_is2_to_ucode; +rf0_ldst_tid_d <= gate("11", n_thread(3)) or + gate("10", n_thread(2)) or + gate("01", n_thread(1)) ; +rf0_ldst_tag_d <= iu_xu_is2_axu_ldst_tag_int; +rf0_ldst_act <= iss_is2_vld; +iu_fu_rf0_str_val <= rf0_str_val_l2; +iu_fu_rf0_ldst_val <= rf0_ldst_val_l2; +iu_fu_rf0_ldst_tid <= rf0_ldst_tid_l2; +iu_fu_rf0_ldst_tag <= rf0_ldst_tag_l2; +----------------------------------------------------------------------- +-- Perf +----------------------------------------------------------------------- +perf_event_d(0) <= i_afi_is2_take_t(0) and n_thread(0); +perf_event_d(1) <= i_afi_is2_take_t(1) and n_thread(1); +perf_event_d(2) <= i_afi_is2_take_t(2) and n_thread(2); +perf_event_d(3) <= i_afi_is2_take_t(3) and n_thread(3); +perf_event_d(4) <= not i_afi_is2_take_t(0) and i_afd_is2_t0_instr_v; +perf_event_d(5) <= not i_afi_is2_take_t(1) and i_afd_is2_t1_instr_v; +perf_event_d(6) <= not i_afi_is2_take_t(2) and i_afd_is2_t2_instr_v; +perf_event_d(7) <= not i_afi_is2_take_t(3) and i_afd_is2_t3_instr_v; +perf_event_d(8) <= not next_tid(0) and is2_vld_l2(0); +perf_event_d(9) <= not next_tid(1) and is2_vld_l2(1); +perf_event_d(10) <= not next_tid(2) and is2_vld_l2(2); +perf_event_d(11) <= not next_tid(3) and is2_vld_l2(3); +perf_event_d(12) <= i_afi_is2_take_t(0); +perf_event_d(13) <= i_afi_is2_take_t(1); +perf_event_d(14) <= i_afi_is2_take_t(2); +perf_event_d(15) <= i_afi_is2_take_t(3); +perf_event_d(16) <= n_thread(0); +perf_event_d(17) <= n_thread(1); +perf_event_d(18) <= n_thread(2); +perf_event_d(19) <= n_thread(3); +perf_event_d(20) <= i_afi_is2_take_t(0) or n_thread(0); +perf_event_d(21) <= i_afi_is2_take_t(1) or n_thread(1); +perf_event_d(22) <= i_afi_is2_take_t(2) or n_thread(2); +perf_event_d(23) <= i_afi_is2_take_t(3) or n_thread(3); +perf_event_d(24) <= n_thread(0) and fdep_fiss_t0_is2_match; +perf_event_d(25) <= n_thread(1) and fdep_fiss_t1_is2_match; +perf_event_d(26) <= n_thread(2) and fdep_fiss_t2_is2_match; +perf_event_d(27) <= n_thread(3) and fdep_fiss_t3_is2_match; +--ppc dispatch +--is_ucode drops for last instruction of ucode routine, so ucode instructions are counted exactly one time +perf_event_d(28) <= i_afi_is2_take_t(0) or (n_thread(0) and not fdep_fiss_t0_is2_to_ucode and not fdep_fiss_t0_is2_is_ucode); +perf_event_d(29) <= i_afi_is2_take_t(1) or (n_thread(1) and not fdep_fiss_t1_is2_to_ucode and not fdep_fiss_t1_is2_is_ucode); +perf_event_d(30) <= i_afi_is2_take_t(2) or (n_thread(2) and not fdep_fiss_t2_is2_to_ucode and not fdep_fiss_t2_is2_is_ucode); +perf_event_d(31) <= i_afi_is2_take_t(3) or (n_thread(3) and not fdep_fiss_t3_is2_to_ucode and not fdep_fiss_t3_is2_is_ucode); +fiss_perf_event_t0(0 TO 7) <= perf_event_l2(0) & + perf_event_l2(4) & + perf_event_l2(8) & + perf_event_l2(12) & + perf_event_l2(16) & + perf_event_l2(20) & + perf_event_l2(24) & + perf_event_l2(28); +fiss_perf_event_t1(0 TO 7) <= perf_event_l2(1) & + perf_event_l2(5) & + perf_event_l2(9) & + perf_event_l2(13) & + perf_event_l2(17) & + perf_event_l2(21) & + perf_event_l2(25) & + perf_event_l2(29); +fiss_perf_event_t2(0 TO 7) <= perf_event_l2(2) & + perf_event_l2(6) & + perf_event_l2(10) & + perf_event_l2(14) & + perf_event_l2(18) & + perf_event_l2(22) & + perf_event_l2(26) & + perf_event_l2(30); +fiss_perf_event_t3(0 TO 7) <= perf_event_l2(3) & + perf_event_l2(7) & + perf_event_l2(11) & + perf_event_l2(15) & + perf_event_l2(19) & + perf_event_l2(23) & + perf_event_l2(27) & + perf_event_l2(31); +----------------------------------------------------------------------- +-- Debug +----------------------------------------------------------------------- +fiss_dbg_data(0 TO 3) <= high_pri_mask_l2(0 to 3); +fiss_dbg_data(4 TO 7) <= med_pri_mask_l2(0 to 3); +fiss_dbg_data(8) <= hi_did3no0; +fiss_dbg_data(9) <= hi_did3no1; +fiss_dbg_data(10) <= hi_did3no2; +fiss_dbg_data(11) <= hi_did2no0; +fiss_dbg_data(12) <= hi_did2no1; +fiss_dbg_data(13) <= hi_did1no0; +fiss_dbg_data(14) <= md_did3no0; +fiss_dbg_data(15) <= md_did3no1; +fiss_dbg_data(16) <= md_did3no2; +fiss_dbg_data(17) <= md_did2no0; +fiss_dbg_data(18) <= md_did2no1; +fiss_dbg_data(19) <= md_did1no0; +fiss_dbg_data(20 TO 25) <= low_pri_counter0_l2(0 to 5); +fiss_dbg_data(26 TO 31) <= low_pri_counter1_l2(0 to 5); +fiss_dbg_data(32 TO 37) <= low_pri_counter2_l2(0 to 5); +fiss_dbg_data(38 TO 43) <= low_pri_counter3_l2(0 to 5); +fiss_dbg_data_d(44) <= iu_xu_is2_vld_int; +fiss_dbg_data_d(45) <= fiss_uc_is2_ucode_vld_int; +fiss_dbg_data_d(46 TO 49) <= iu_xu_is2_tid_int(0 to 3); +fiss_dbg_data_d(50 TO 81) <= iu_xu_is2_instr_int(0 to 31); +fiss_dbg_data_d(82) <= iu_xu_is2_pred_update_int; +fiss_dbg_data_d(83 TO 84) <= iu_xu_is2_pred_taken_cnt_int(0 to 1); +fiss_dbg_data_d(85 TO 87) <= iu_xu_is2_error_int(0 to 2); +fiss_dbg_data(44 TO 87) <= fiss_dbg_data_l2(44 to 87); +----------------------------------------------------------------------- +-- scan +----------------------------------------------------------------------- +siv(0 TO scan_right) <= sov(1 to scan_right) & scan_in; +scan_out <= sov(0) and an_ac_scan_dis_dc_b; +END IUQ_FXU_ISSUE; diff --git a/rel/src/vhdl/work/iuq_ib_buff.vhdl b/rel/src/vhdl/work/iuq_ib_buff.vhdl new file mode 100644 index 0000000..93cd9e8 --- /dev/null +++ b/rel/src/vhdl/work/iuq_ib_buff.vhdl @@ -0,0 +1,1162 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +--******************************************************************** +--* +--* TITLE: Instruction Buffer +--* +--* NAME: iuq_ib_buff.vhdl +--* +--********************************************************************* + +library ieee; use ieee.std_logic_1164.all; +library ibm; use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; +library support; +use support.power_logic_pkg.all; +library tri; use tri.tri_latches_pkg.all; +library work; use work.iuq_pkg.all; + +entity iuq_ib_buff is + generic(ibuff_data_width : integer := 50; + ibuff_ifar_width : integer := 22; + uc_ifar : integer := 21; + expand_type : integer := 2 ); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + pc_iu_sg_2 : in std_ulogic; + pc_iu_func_sl_thold_2 : in std_ulogic; + clkoff_b : in std_ulogic; + an_ac_scan_dis_dc_b : in std_ulogic; + tc_ac_ccflush_dc : in std_ulogic; + delay_lclkr : in std_ulogic; + mpw1_b : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + spr_dec_mask_pt_in : in std_ulogic_vector(0 to 31); + spr_dec_mask_pt_out : out std_ulogic_vector(0 to 31); + fdep_dbg_data_pt_in : in std_ulogic_vector(0 to 21); + fdep_dbg_data_pt_out : out std_ulogic_vector(0 to 21); + fdep_perf_event_pt_in : in std_ulogic_vector(0 to 11); + fdep_perf_event_pt_out : out std_ulogic_vector(0 to 11); + + pc_iu_trace_bus_enable : in std_ulogic; + pc_iu_event_bus_enable : in std_ulogic; + ib_dbg_data : out std_ulogic_vector(0 to 15); + ib_perf_event : out std_ulogic_vector(0 to 1); + + xu_iu_ib1_flush : in std_ulogic; + uc_flush : in std_ulogic; + + fdec_ibuf_stall : in std_ulogic; + + ib_ic_empty : out std_ulogic; + ib_ic_below_water : out std_ulogic; + + -- BP interface + bp_ib_iu4_ifar : in EFF_IFAR; + bp_ib_iu4_val : in std_ulogic_vector(0 to 3); + bp_ib_iu3_0_instr : in std_ulogic_vector(0 to 31); + bp_ib_iu4_0_instr : in std_ulogic_vector(32 to 43); + bp_ib_iu4_1_instr : in std_ulogic_vector(0 to 43); + bp_ib_iu4_2_instr : in std_ulogic_vector(0 to 43); + bp_ib_iu4_3_instr : in std_ulogic_vector(0 to 43); + + -- UC interface + uc_ib_iu4_ifar : in std_ulogic_vector(62-uc_ifar to 61); + uc_ib_iu4_val : in std_ulogic; + uc_ib_iu4_instr : in std_ulogic_vector(0 to 36); + + -- RAM interface + rm_ib_iu4_val : in std_ulogic; + rm_ib_iu4_force_ram : in std_ulogic; + rm_ib_iu4_instr : in std_ulogic_vector(0 to 35); + + ib_ic_iu5_redirect_tid : out std_ulogic; + + iu_au_ib1_valid : out std_ulogic; + iu_au_ib1_ifar : out EFF_IFAR; + iu_au_ib1_data : out std_ulogic_vector(0 to ibuff_data_width-1) +); + -- synopsys translate_off + -- synopsys translate_on +end iuq_ib_buff; + + +architecture iuq_ib_buff of iuq_ib_buff is + +constant command_width_full : integer := (ibuff_data_width+EFF_IFAR'length); +constant command_width_lite : integer := (ibuff_data_width+ibuff_ifar_width); + +constant bp_ib_iu4_0_instr_offset : natural := 0; +constant buffer1_valid_offset : natural := bp_ib_iu4_0_instr_offset + 32; +constant buffer2_valid_offset : natural := buffer1_valid_offset + 1; +constant buffer3_valid_offset : natural := buffer2_valid_offset + 1; +constant buffer4_valid_offset : natural := buffer3_valid_offset + 1; +constant buffer5_valid_offset : natural := buffer4_valid_offset + 1; +constant buffer6_valid_offset : natural := buffer5_valid_offset + 1; +constant buffer7_valid_offset : natural := buffer6_valid_offset + 1; +constant buffer1_data_offset : natural := buffer7_valid_offset + 1; +constant buffer2_data_offset : natural := buffer1_data_offset + command_width_lite; +constant buffer3_data_offset : natural := buffer2_data_offset + command_width_lite; +constant buffer4_data_offset : natural := buffer3_data_offset + command_width_lite; +constant buffer5_data_offset : natural := buffer4_data_offset + command_width_lite; +constant buffer6_data_offset : natural := buffer5_data_offset + command_width_lite; +constant buffer7_data_offset : natural := buffer6_data_offset + command_width_lite; +constant stall_buffer_data_offset : natural := buffer7_data_offset + command_width_lite; +constant buffer_ifar_offset : natural := stall_buffer_data_offset + command_width_full; +constant redirect_offset : natural := buffer_ifar_offset + (EFF_IFAR'length-ibuff_ifar_width); +constant stall_offset : natural := redirect_offset + 1; +constant buff1_sel_offset : natural := stall_offset + 3; +constant perf_event_offset : natural := buff1_sel_offset + 5; +constant ib_dbg_data_offset : natural := perf_event_offset + 2; +constant spare_offset : natural := ib_dbg_data_offset + 6; +constant trace_bus_enable_offset : natural := spare_offset + 8; +constant event_bus_enable_offset : natural := trace_bus_enable_offset + 1; +constant scan_right : natural := event_bus_enable_offset + 1 - 1; + +signal spare_l2 : std_ulogic_vector(0 to 7); + +signal ib_iu4_val : std_ulogic_vector(0 to 3); +signal ib_iu4_ifar : EFF_IFAR; +signal rm_iu4_0_instr : std_ulogic_vector(0 to ibuff_data_width-1); +signal uc_iu4_0_instr : std_ulogic_vector(0 to ibuff_data_width-1); +signal bp_iu4_0_instr : std_ulogic_vector(0 to ibuff_data_width-1); +signal ib_iu4_0_instr : std_ulogic_vector(0 to ibuff_data_width-1); +signal ib_iu4_1_instr : std_ulogic_vector(0 to ibuff_data_width-1); +signal ib_iu4_2_instr : std_ulogic_vector(0 to ibuff_data_width-1); +signal ib_iu4_3_instr : std_ulogic_vector(0 to ibuff_data_width-1); + +signal bp_ib_iu4_0_instr_d : std_ulogic_vector(0 to 31); +signal bp_ib_iu4_0_instr_l2 : std_ulogic_vector(0 to 31); +signal iu4_act : std_ulogic; + +signal uc_ib_iu4_ifar_int : EFF_IFAR; + +-- Latch signals +signal buffer1_valid_d : std_ulogic; +signal buffer1_valid_l2 : std_ulogic; +signal buffer2_valid_d : std_ulogic; +signal buffer2_valid_l2 : std_ulogic; +signal buffer3_valid_d : std_ulogic; +signal buffer3_valid_l2 : std_ulogic; +signal buffer4_valid_d : std_ulogic; +signal buffer4_valid_l2 : std_ulogic; +signal buffer5_valid_d : std_ulogic; +signal buffer5_valid_l2 : std_ulogic; +signal buffer6_valid_d : std_ulogic; +signal buffer6_valid_l2 : std_ulogic; +signal buffer7_valid_d : std_ulogic; +signal buffer7_valid_l2 : std_ulogic; + +signal buffer1_data_d : std_ulogic_vector(0 to command_width_lite-1); +signal buffer1_data_l2 : std_ulogic_vector(0 to command_width_lite-1); +signal buffer2_data_d : std_ulogic_vector(0 to command_width_lite-1); +signal buffer2_data_l2 : std_ulogic_vector(0 to command_width_lite-1); +signal buffer3_data_d : std_ulogic_vector(0 to command_width_lite-1); +signal buffer3_data_l2 : std_ulogic_vector(0 to command_width_lite-1); +signal buffer4_data_d : std_ulogic_vector(0 to command_width_lite-1); +signal buffer4_data_l2 : std_ulogic_vector(0 to command_width_lite-1); +signal buffer5_data_d : std_ulogic_vector(0 to command_width_lite-1); +signal buffer5_data_l2 : std_ulogic_vector(0 to command_width_lite-1); +signal buffer6_data_d : std_ulogic_vector(0 to command_width_lite-1); +signal buffer6_data_l2 : std_ulogic_vector(0 to command_width_lite-1); +signal buffer7_data_d : std_ulogic_vector(0 to command_width_lite-1); +signal buffer7_data_l2 : std_ulogic_vector(0 to command_width_lite-1); + +signal buffer_data : std_ulogic_vector(0 to command_width_full-1); +signal stall_buffer_data_d : std_ulogic_vector(0 to command_width_full-1); +signal stall_buffer_data_l2 : std_ulogic_vector(0 to command_width_full-1); +signal stall_d : std_ulogic_vector(0 to 2); +signal stall_l2 : std_ulogic_vector(0 to 2); +signal buff1_sel_d : std_ulogic_vector(0 to 4); +signal buff1_sel_l2 : std_ulogic_vector(0 to 4); + +signal buffer1_data : std_ulogic_vector(0 to command_width_full-1); +signal buffer_ifar_d : std_ulogic_vector(EFF_IFAR'left to EFF_IFAR'right-ibuff_ifar_width); +signal buffer_ifar_l2 : std_ulogic_vector(EFF_IFAR'left to EFF_IFAR'right-ibuff_ifar_width); +signal buffer_ifar_update : std_ulogic; +signal buffer_ifar_match : std_ulogic; +signal buffer_ifar_match_uc : std_ulogic; +signal redirect_d : std_ulogic; +signal redirect_l2 : std_ulogic; + +-- Logic signals +signal pc_ext_1 : std_ulogic_vector(60 to 61); +signal pc_ext_2 : std_ulogic_vector(60 to 61); +signal pc_ext_3 : std_ulogic_vector(60 to 61); + +signal stall_buffer_act : std_ulogic; +signal buffer1_data_act : std_ulogic; +signal buffer2_data_act : std_ulogic; +signal buffer3_data_act : std_ulogic; +signal buffer4_data_act : std_ulogic; +signal buffer5_data_act : std_ulogic; +signal buffer6_data_act : std_ulogic; +signal buffer7_data_act : std_ulogic; + +signal valid_out : std_ulogic; +signal data_out : std_ulogic_vector(0 to command_width_full-1); + +-- Pervasive +signal pc_iu_func_sl_thold_1 : std_ulogic; +signal pc_iu_func_sl_thold_0 : std_ulogic; +signal pc_iu_func_sl_thold_0_b : std_ulogic; +signal pc_iu_sg_1 : std_ulogic; +signal pc_iu_sg_0 : std_ulogic; +signal forcee : std_ulogic; + +signal siv : std_ulogic_vector(0 to scan_right); +signal sov : std_ulogic_vector(0 to scan_right); + +signal tiup : std_ulogic; + +signal valid_in : std_ulogic_vector(0 to 3); +signal valid_in_uc : std_ulogic; +signal valid_fast : std_ulogic; +signal valid_slow : std_ulogic; + +signal perf_event_d : std_ulogic_vector(0 to 1); +signal perf_event_l2 : std_ulogic_vector(0 to 1); + +signal ib_dbg_data_d : std_ulogic_vector(0 to 5); +signal ib_dbg_data_l2 : std_ulogic_vector(0 to 5); + +signal trace_bus_enable_d : std_ulogic; +signal trace_bus_enable_q : std_ulogic; +signal event_bus_enable_d : std_ulogic; +signal event_bus_enable_q : std_ulogic; + +signal act_dis : std_ulogic; +signal d_mode : std_ulogic; +signal mpw2_b : std_ulogic; + +begin + + +----------------------------------------------------------------------- +-- Logic +----------------------------------------------------------------------- +tiup <= '1'; + + +act_dis <= '0'; +d_mode <= '0'; +mpw2_b <= '1'; + + +---------------------------------------- +-- passthrough +---------------------------------------- +spr_dec_mask_pt_out <= spr_dec_mask_pt_in; +fdep_dbg_data_pt_out <= fdep_dbg_data_pt_in; +fdep_perf_event_pt_out <= fdep_perf_event_pt_in; + + + +---------------------------------------- +-- ibuff instruction source muxing +---------------------------------------- + + +ib_iu4_val(0) <= rm_ib_iu4_val or uc_ib_iu4_val or bp_ib_iu4_val(0); + +ib_iu4_val(1 to 3) <= bp_ib_iu4_val(1 to 3); + +uc_ib_iu4_ifar_int(62-uc_ifar to 61) <= uc_ib_iu4_ifar; +uc_ib_iu4_ifar_int(EFF_IFAR'left to 61-uc_ifar) <= (others => '0'); + + +ib_iu4_ifar <= gate(uc_ib_iu4_ifar_int, uc_ib_iu4_val) or + gate(bp_ib_iu4_ifar , bp_ib_iu4_val(0)); + + +bp_ib_iu4_0_instr_d <= bp_ib_iu3_0_instr; + +rm_iu4_0_instr(0 to 49) <= rm_ib_iu4_instr(0 to 35) & "000000000" & rm_ib_iu4_force_ram & "0000"; +uc_iu4_0_instr(0 to 49) <= uc_ib_iu4_instr(0 to 35) & "000000" & uc_ib_iu4_instr(36) & "0000000"; +bp_iu4_0_instr(0 to 49) <= bp_ib_iu4_0_instr_l2(0 to 31) & "0000" & bp_ib_iu4_0_instr(32 to 37) & '0' & bp_ib_iu4_0_instr(38 to 39) & '0' & bp_ib_iu4_0_instr(40 to 43); + +ib_iu4_0_instr(0 to 49) <= gate(rm_iu4_0_instr(0 to 49), rm_ib_iu4_val) or + gate(uc_iu4_0_instr(0 to 49), uc_ib_iu4_val) or + gate(bp_iu4_0_instr(0 to 49), bp_ib_iu4_val(0)); + +ib_iu4_1_instr(0 to 49) <= bp_ib_iu4_1_instr(0 to 31) & "0000" & bp_ib_iu4_1_instr(32 to 37) & '0' & bp_ib_iu4_1_instr(38 to 39) & '0' & bp_ib_iu4_1_instr(40 to 43); +ib_iu4_2_instr(0 to 49) <= bp_ib_iu4_2_instr(0 to 31) & "0000" & bp_ib_iu4_2_instr(32 to 37) & '0' & bp_ib_iu4_2_instr(38 to 39) & '0' & bp_ib_iu4_2_instr(40 to 43); +ib_iu4_3_instr(0 to 49) <= bp_ib_iu4_3_instr(0 to 31) & "0000" & bp_ib_iu4_3_instr(32 to 37) & '0' & bp_ib_iu4_3_instr(38 to 39) & '0' & bp_ib_iu4_3_instr(40 to 43); + + +valid_slow <= (rm_ib_iu4_val or uc_ib_iu4_val) and not redirect_l2; +valid_fast <= bp_ib_iu4_val(0) and not redirect_l2; + +---------------------------------------- +-- ibuff +---------------------------------------- +valid_in(0 to 3) <= gate(ib_iu4_val(0 to 3), not redirect_l2); +valid_in_uc <= uc_ib_iu4_val and not redirect_l2; + +-- Calculate last 2 bits of address for instr1-3 +with ib_iu4_ifar(60 to 61) select +pc_ext_1 <= "11" when "10", + "10" when "01", + "01" when others; +pc_ext_2 <= '1' & ib_iu4_ifar(61); +pc_ext_3 <= "11"; + + +buffer_ifar_d <= ib_iu4_ifar(EFF_IFAR'left to EFF_IFAR'right-ibuff_ifar_width) when buffer_ifar_update='1' else buffer_ifar_l2; + +-- Check for incoming valids and set new buffer entries +check_vals:process(xu_iu_ib1_flush, uc_flush, valid_in, ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to EFF_IFAR'right), ib_iu4_0_instr, + pc_ext_1, pc_ext_2, pc_ext_3, stall_l2(0), + buffer1_valid_l2, buffer2_valid_l2, buffer3_valid_l2, + buffer4_valid_l2, buffer5_valid_l2, buffer6_valid_l2, buffer7_valid_l2, + buffer1_data_l2, buffer2_data_l2, buffer3_data_l2, + buffer4_data_l2, buffer5_data_l2, buffer6_data_l2, buffer7_data_l2, + ib_iu4_1_instr, ib_iu4_2_instr, ib_iu4_3_instr, buffer_ifar_match, buffer_ifar_match_uc, valid_fast, valid_slow, valid_in_uc, uc_iu4_0_instr) begin + + -- default values + buffer1_valid_d <= buffer1_valid_l2; + buffer2_valid_d <= buffer2_valid_l2; + buffer3_valid_d <= buffer3_valid_l2; + buffer4_valid_d <= buffer4_valid_l2; + buffer5_valid_d <= buffer5_valid_l2; + buffer6_valid_d <= buffer6_valid_l2; + buffer7_valid_d <= buffer7_valid_l2; + + buffer1_data_d <= buffer1_data_l2; + buffer2_data_d <= buffer2_data_l2; + buffer3_data_d <= buffer3_data_l2; + buffer4_data_d <= buffer4_data_l2; + buffer5_data_d <= buffer5_data_l2; + buffer6_data_d <= buffer6_data_l2; + buffer7_data_d <= buffer7_data_l2; + + buffer_ifar_update <= '0'; + + if (stall_l2(0) = '1') then + if(buffer1_valid_l2 = '0') then + buffer1_valid_d <= valid_in(0); + buffer_ifar_update <= valid_in(0); + buffer2_valid_d <= valid_in(1); + buffer3_valid_d <= valid_in(2); + buffer4_valid_d <= valid_in(3); + buffer1_data_d <= ib_iu4_0_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to EFF_IFAR'right); + buffer2_data_d <= ib_iu4_1_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to 59) & pc_ext_1; + buffer3_data_d <= ib_iu4_2_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to 59) & pc_ext_2; + buffer4_data_d <= ib_iu4_3_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to 59) & pc_ext_3; + end if; + + if(buffer1_valid_l2 = '1' and buffer2_valid_l2 = '0' and buffer_ifar_match = '1') then + buffer2_valid_d <= valid_in(0); + buffer3_valid_d <= valid_in(1); + buffer4_valid_d <= valid_in(2); + buffer5_valid_d <= valid_in(3); + end if; + if(buffer1_valid_l2 = '1' and buffer2_valid_l2 = '0') then + buffer2_data_d <= ib_iu4_0_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to EFF_IFAR'right); + buffer3_data_d <= ib_iu4_1_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to 59) & pc_ext_1; + buffer4_data_d <= ib_iu4_2_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to 59) & pc_ext_2; + buffer5_data_d <= ib_iu4_3_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to 59) & pc_ext_3; + end if; + + if(buffer2_valid_l2 = '1' and buffer3_valid_l2 = '0' and buffer_ifar_match = '1') then + buffer3_valid_d <= valid_in(0); + buffer4_valid_d <= valid_in(1); + buffer5_valid_d <= valid_in(2); + buffer6_valid_d <= valid_in(3); + end if; + if(buffer2_valid_l2 = '1' and buffer3_valid_l2 = '0' ) then + buffer3_data_d <= ib_iu4_0_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to EFF_IFAR'right); + buffer4_data_d <= ib_iu4_1_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to 59) & pc_ext_1; + buffer5_data_d <= ib_iu4_2_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to 59) & pc_ext_2; + buffer6_data_d <= ib_iu4_3_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to 59) & pc_ext_3; + end if; + + if(buffer3_valid_l2 = '1' and buffer4_valid_l2 = '0' and buffer_ifar_match = '1') then + buffer4_valid_d <= valid_in(0); + buffer5_valid_d <= valid_in(1); + buffer6_valid_d <= valid_in(2); + buffer7_valid_d <= valid_in(3); + end if; + if(buffer3_valid_l2 = '1' and buffer4_valid_l2 = '0') then + buffer4_data_d <= ib_iu4_0_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to EFF_IFAR'right); + buffer5_data_d <= ib_iu4_1_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to 59) & pc_ext_1; + buffer6_data_d <= ib_iu4_2_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to 59) & pc_ext_2; + buffer7_data_d <= ib_iu4_3_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to 59) & pc_ext_3; + end if; + + --added for ucode + if(buffer4_valid_l2 = '1' and buffer5_valid_l2 = '0' and buffer_ifar_match_uc = '1') then + buffer5_valid_d <= valid_in_uc; + end if; + if(buffer4_valid_l2 = '1' and buffer5_valid_l2 = '0') then + buffer5_data_d <= uc_iu4_0_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to EFF_IFAR'right); + end if; + + if(buffer5_valid_l2 = '1' and buffer6_valid_l2 = '0' and buffer_ifar_match_uc = '1') then + buffer6_valid_d <= valid_in_uc; + end if; + if(buffer5_valid_l2 = '1' and buffer6_valid_l2 = '0') then + buffer6_data_d <= uc_iu4_0_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to EFF_IFAR'right); + end if; + + + else -- stall_l2 = 0 + buffer1_data_d <= buffer2_data_l2; + buffer2_data_d <= buffer3_data_l2; + buffer3_data_d <= buffer4_data_l2; + buffer4_data_d <= buffer5_data_l2; + buffer5_data_d <= buffer6_data_l2; + buffer6_data_d <= buffer7_data_l2; + + buffer1_valid_d <= buffer2_valid_l2; + buffer2_valid_d <= buffer3_valid_l2; + buffer3_valid_d <= buffer4_valid_l2; + buffer4_valid_d <= buffer5_valid_l2; + buffer5_valid_d <= buffer6_valid_l2; + buffer6_valid_d <= buffer7_valid_l2; + buffer7_valid_d <= '0'; + + if(buffer1_valid_l2 = '0' and valid_fast = '1') then + buffer_ifar_update <= valid_in(0); + buffer1_valid_d <= valid_in(1); + buffer2_valid_d <= valid_in(2); + buffer3_valid_d <= valid_in(3); + buffer1_data_d <= ib_iu4_1_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to 59) & pc_ext_1; + buffer2_data_d <= ib_iu4_2_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to 59) & pc_ext_2; + buffer3_data_d <= ib_iu4_3_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to 59) & pc_ext_3; + end if; + + if((buffer1_valid_l2 = '1' and buffer2_valid_l2 = '0') or (buffer1_valid_l2 = '0' and valid_slow = '1')) then + buffer1_valid_d <= valid_in(0); + buffer_ifar_update <= valid_in(0); + buffer2_valid_d <= valid_in(1); + buffer3_valid_d <= valid_in(2); + buffer4_valid_d <= valid_in(3); + buffer1_data_d <= ib_iu4_0_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to EFF_IFAR'right); + buffer2_data_d <= ib_iu4_1_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to 59) & pc_ext_1; + buffer3_data_d <= ib_iu4_2_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to 59) & pc_ext_2; + buffer4_data_d <= ib_iu4_3_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to 59) & pc_ext_3; + end if; + + if(buffer2_valid_l2 = '1' and buffer3_valid_l2 = '0' and buffer_ifar_match = '1') then + buffer2_valid_d <= valid_in(0); + buffer3_valid_d <= valid_in(1); + buffer4_valid_d <= valid_in(2); + buffer5_valid_d <= valid_in(3); + end if; + if(buffer2_valid_l2 = '1' and buffer3_valid_l2 = '0') then + buffer2_data_d <= ib_iu4_0_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to EFF_IFAR'right); + buffer3_data_d <= ib_iu4_1_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to 59) & pc_ext_1; + buffer4_data_d <= ib_iu4_2_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to 59) & pc_ext_2; + buffer5_data_d <= ib_iu4_3_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to 59) & pc_ext_3; + end if; + + if(buffer3_valid_l2 = '1' and buffer4_valid_l2 = '0' and buffer_ifar_match = '1') then + buffer3_valid_d <= valid_in(0); + buffer4_valid_d <= valid_in(1); + buffer5_valid_d <= valid_in(2); + buffer6_valid_d <= valid_in(3); + end if; + if(buffer3_valid_l2 = '1' and buffer4_valid_l2 = '0' ) then + buffer3_data_d <= ib_iu4_0_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to EFF_IFAR'right); + buffer4_data_d <= ib_iu4_1_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to 59) & pc_ext_1; + buffer5_data_d <= ib_iu4_2_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to 59) & pc_ext_2; + buffer6_data_d <= ib_iu4_3_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to 59) & pc_ext_3; + end if; + + if(buffer4_valid_l2 = '1' and buffer5_valid_l2 = '0' and buffer_ifar_match_uc = '1') then + buffer4_valid_d <= valid_in_uc; + end if; + if(buffer4_valid_l2 = '1' and buffer5_valid_l2 = '0' ) then + buffer4_data_d <= uc_iu4_0_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to EFF_IFAR'right); + end if; + + if(buffer5_valid_l2 = '1' and buffer6_valid_l2 = '0' and buffer_ifar_match_uc = '1') then + buffer5_valid_d <= valid_in_uc; + end if; + if(buffer5_valid_l2 = '1' and buffer6_valid_l2 = '0' ) then + buffer5_data_d <= uc_iu4_0_instr & ib_iu4_ifar(EFF_IFAR'right+1-ibuff_ifar_width to EFF_IFAR'right); + end if; + + end if; + + if(xu_iu_ib1_flush = '1' or uc_flush = '1') then + buffer1_valid_d <= '0'; + buffer2_valid_d <= '0'; + buffer3_valid_d <= '0'; + buffer4_valid_d <= '0'; + buffer5_valid_d <= '0'; + buffer6_valid_d <= '0'; + buffer7_valid_d <= '0'; + end if; + +end process; + +--added for clock gating +buffer1_data_act <= not (stall_l2(0) and buffer1_valid_l2); +buffer2_data_act <= not (stall_l2(0) and buffer2_valid_l2); +buffer3_data_act <= not (stall_l2(0) and buffer3_valid_l2); +buffer4_data_act <= not (stall_l2(0) and buffer4_valid_l2); +buffer5_data_act <= not (stall_l2(0) and buffer5_valid_l2); +buffer6_data_act <= not (stall_l2(0) and buffer6_valid_l2); +buffer7_data_act <= not (stall_l2(0) and buffer7_valid_l2); + + + +ib_ic_empty <= not (buffer1_valid_l2 or stall_l2(0)); +ib_ic_below_water <= (not buffer4_valid_l2) or (not buffer5_valid_l2 and not stall_l2(0)); +--duplicate for iu4_act...incoming pipeline will only contain valid data when buffer is below water and able to accept it +iu4_act <= (not buffer4_valid_l2) or (not buffer5_valid_l2 and not stall_l2(0)); + +-- reconstruct buffer1_data +buffer1_data <= buffer1_data_l2(0 to ibuff_data_width-1) & + buffer_ifar_l2(EFF_IFAR'left to EFF_IFAR'right-ibuff_ifar_width) & + buffer1_data_l2(ibuff_data_width to command_width_lite-1); + +gen_uc_match1: if (ibuff_ifar_width < uc_ifar) generate +begin +-- generate flush based on stored ifar +buffer_ifar_match <= '1' when buffer_ifar_l2(EFF_IFAR'left to EFF_IFAR'right-ibuff_ifar_width) = ib_iu4_ifar(EFF_IFAR'left to EFF_IFAR'right-ibuff_ifar_width) else + '0'; +buffer_ifar_match_uc <= buffer_ifar_match; --for ucode-only buffer fill +end generate; + +gen_uc_match0: if (ibuff_ifar_width >= uc_ifar) generate +begin +--assume address match on ucode/ram issued instructions for timing +buffer_ifar_match <= (not bp_ib_iu4_val(0)) or + (buffer_ifar_l2(EFF_IFAR'left to EFF_IFAR'right-ibuff_ifar_width) = bp_ib_iu4_ifar(EFF_IFAR'left to EFF_IFAR'right-ibuff_ifar_width)); +buffer_ifar_match_uc <= '1'; --for ucode-only buffer fill +end generate; + +redirect_d <= valid_in(0) and not xu_iu_ib1_flush and not uc_flush and not buffer_ifar_match and not buffer_ifar_update; + +ib_ic_iu5_redirect_tid <= redirect_l2; + + +--move stall latch to decode +stall_d(0) <= fdec_ibuf_stall; +stall_d(1) <= fdec_ibuf_stall; +stall_d(2) <= fdec_ibuf_stall; + +stall_buffer_data_d <= + buffer1_data when buffer1_valid_l2 = '1' else + ib_iu4_0_instr & ib_iu4_ifar; + + + +buff1_sel_d(0) <= buffer1_valid_d; +buff1_sel_d(1) <= buffer1_valid_d; +buff1_sel_d(2) <= buffer1_valid_d; +buff1_sel_d(3) <= buffer1_valid_d; +buff1_sel_d(4) <= buffer1_valid_d; + + +-- Instruction output +valid_out <= (buffer1_valid_l2 or valid_fast or stall_l2(0)); + +buffer_data(0 to 7) <= buffer1_data(0 to 7) when buff1_sel_l2(1) = '1' else + bp_iu4_0_instr(0 to 7); + +buffer_data(8 to 15) <= buffer1_data(8 to 15) when buff1_sel_l2(2) = '1' else + bp_iu4_0_instr(8 to 15); + +buffer_data(16 to 23) <= buffer1_data(16 to 23) when buff1_sel_l2(3) = '1' else + bp_iu4_0_instr(16 to 23); + +buffer_data(24 to 31) <= buffer1_data(24 to 31) when buff1_sel_l2(4) = '1' else + bp_iu4_0_instr(24 to 31); + +buffer_data(32 to command_width_full-1) <= buffer1_data(32 to command_width_full-1) when buff1_sel_l2(0) = '1' else + (bp_iu4_0_instr(32 to 49) & bp_ib_iu4_ifar); + + +data_out(0 to 15) <= stall_buffer_data_l2(0 to 15) when stall_L2(1) = '1' else + buffer_data(0 to 15); + +data_out(16 to 31) <= stall_buffer_data_l2(16 to 31) when stall_L2(2) = '1' else + buffer_data(16 to 31); + +data_out(32 to command_width_full-1) <= stall_buffer_data_l2(32 to command_width_full-1) when stall_L2(0) = '1' else + buffer_data(32 to command_width_full-1); + +iu_au_ib1_valid <= valid_out; + +iu_au_ib1_data <= data_out(0 to ibuff_data_width-1); + +iu_au_ib1_ifar <= data_out(ibuff_data_width to command_width_full-1); + + +----------------------------------------------------------------------- +-- Perf +----------------------------------------------------------------------- + +perf_event_d(0) <= not (buffer1_valid_l2 or stall_l2(0)); +perf_event_d(1) <= redirect_l2; + +ib_perf_event(0) <= perf_event_l2(0); -- ibuf empty +ib_perf_event(1) <= perf_event_l2(1); -- ibuf flush + +----------------------------------------------------------------------- +-- Debug +----------------------------------------------------------------------- + + +ib_dbg_data_d(0 to 3) <= bp_ib_iu4_val(0 to 3); +ib_dbg_data_d(4) <= rm_ib_iu4_val; +ib_dbg_data_d(5) <= uc_ib_iu4_val; + +ib_dbg_data(0 to 5) <= ib_dbg_data_l2(0 to 5); +ib_dbg_data(6) <= redirect_l2; +ib_dbg_data(7) <= (not buffer4_valid_l2) or (not buffer5_valid_l2 and not stall_l2(0)); --below water +ib_dbg_data(8) <= stall_l2(0); +ib_dbg_data(9) <= buffer1_valid_l2; +ib_dbg_data(10) <= buffer2_valid_l2; +ib_dbg_data(11) <= buffer3_valid_l2; +ib_dbg_data(12) <= buffer4_valid_l2; +ib_dbg_data(13) <= buffer5_valid_l2; +ib_dbg_data(14) <= buffer6_valid_l2; +ib_dbg_data(15) <= buffer7_valid_l2; + +----------------------------------------------------------------------- +-- Latches +----------------------------------------------------------------------- +bp_ib_iu4_0_instr_latch: tri_rlmreg_p + generic map (width => bp_ib_iu4_0_instr_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu4_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(bp_ib_iu4_0_instr_offset to bp_ib_iu4_0_instr_offset+bp_ib_iu4_0_instr_l2'length-1), + scout => sov(bp_ib_iu4_0_instr_offset to bp_ib_iu4_0_instr_offset+bp_ib_iu4_0_instr_l2'length-1), + din => bp_ib_iu4_0_instr_d(0 to bp_ib_iu4_0_instr_l2'length-1), + dout => bp_ib_iu4_0_instr_l2(0 to bp_ib_iu4_0_instr_l2'length-1) ); + +buffer1_data_latch: tri_rlmreg_p + generic map (width => buffer1_data_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => buffer1_data_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(buffer1_data_offset to buffer1_data_offset+buffer1_data_l2'length-1), + scout => sov(buffer1_data_offset to buffer1_data_offset+buffer1_data_l2'length-1), + din => buffer1_data_d(0 to command_width_lite-1), + dout => buffer1_data_l2(0 to command_width_lite-1) ); + +buffer2_data_latch: tri_rlmreg_p + generic map (width => buffer2_data_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => buffer2_data_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(buffer2_data_offset to buffer2_data_offset+buffer2_data_l2'length-1), + scout => sov(buffer2_data_offset to buffer2_data_offset+buffer2_data_l2'length-1), + din => buffer2_data_d(0 to command_width_lite-1), + dout => buffer2_data_l2(0 to command_width_lite-1) ); + +buffer3_data_latch: tri_rlmreg_p + generic map (width => buffer3_data_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => buffer3_data_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(buffer3_data_offset to buffer3_data_offset+buffer3_data_l2'length-1), + scout => sov(buffer3_data_offset to buffer3_data_offset+buffer3_data_l2'length-1), + din => buffer3_data_d(0 to command_width_lite-1), + dout => buffer3_data_l2(0 to command_width_lite-1) ); + +buffer4_data_latch: tri_rlmreg_p + generic map (width => buffer4_data_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => buffer4_data_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(buffer4_data_offset to buffer4_data_offset+buffer4_data_l2'length-1), + scout => sov(buffer4_data_offset to buffer4_data_offset+buffer4_data_l2'length-1), + din => buffer4_data_d(0 to command_width_lite-1), + dout => buffer4_data_l2(0 to command_width_lite-1) ); + +buffer5_data_latch: tri_rlmreg_p + generic map (width => buffer5_data_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => buffer5_data_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(buffer5_data_offset to buffer5_data_offset+buffer5_data_l2'length-1), + scout => sov(buffer5_data_offset to buffer5_data_offset+buffer5_data_l2'length-1), + din => buffer5_data_d(0 to command_width_lite-1), + dout => buffer5_data_l2(0 to command_width_lite-1) ); + +buffer6_data_latch: tri_rlmreg_p + generic map (width => buffer6_data_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => buffer6_data_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(buffer6_data_offset to buffer6_data_offset+buffer6_data_l2'length-1), + scout => sov(buffer6_data_offset to buffer6_data_offset+buffer6_data_l2'length-1), + din => buffer6_data_d(0 to command_width_lite-1), + dout => buffer6_data_l2(0 to command_width_lite-1) ); + +buffer7_data_latch: tri_rlmreg_p + generic map (width => buffer7_data_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => buffer7_data_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(buffer7_data_offset to buffer7_data_offset+buffer7_data_l2'length-1), + scout => sov(buffer7_data_offset to buffer7_data_offset+buffer7_data_l2'length-1), + din => buffer7_data_d(0 to command_width_lite-1), + dout => buffer7_data_l2(0 to command_width_lite-1) ); + +buffer1_valid_latch: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(buffer1_valid_offset), + scout => sov(buffer1_valid_offset), + din => buffer1_valid_d, + dout => buffer1_valid_l2 ); + +buffer2_valid_latch: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(buffer2_valid_offset), + scout => sov(buffer2_valid_offset), + din => buffer2_valid_d, + dout => buffer2_valid_l2 ); + +buffer3_valid_latch: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(buffer3_valid_offset), + scout => sov(buffer3_valid_offset), + din => buffer3_valid_d, + dout => buffer3_valid_l2 ); + +buffer4_valid_latch: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(buffer4_valid_offset), + scout => sov(buffer4_valid_offset), + din => buffer4_valid_d, + dout => buffer4_valid_l2 ); + +buffer5_valid_latch: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(buffer5_valid_offset), + scout => sov(buffer5_valid_offset), + din => buffer5_valid_d, + dout => buffer5_valid_l2 ); + +buffer6_valid_latch: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(buffer6_valid_offset), + scout => sov(buffer6_valid_offset), + din => buffer6_valid_d, + dout => buffer6_valid_l2 ); + +buffer7_valid_latch: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(buffer7_valid_offset), + scout => sov(buffer7_valid_offset), + din => buffer7_valid_d, + dout => buffer7_valid_l2 ); + +stall_buffer_act <= not stall_l2(0); +stall_buffer_data_latch: tri_rlmreg_p + generic map (width => stall_buffer_data_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => stall_buffer_act, --tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(stall_buffer_data_offset to stall_buffer_data_offset+stall_buffer_data_l2'length-1), + scout => sov(stall_buffer_data_offset to stall_buffer_data_offset+stall_buffer_data_l2'length-1), + din => stall_buffer_data_d(0 to command_width_full-1), + dout => stall_buffer_data_l2(0 to command_width_full-1) ); + +stall_latch: tri_rlmreg_p + generic map (width => stall_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(stall_offset to stall_offset+stall_l2'length-1), + scout => sov(stall_offset to stall_offset+stall_l2'length-1), + din => stall_d(0 to 2), + dout => stall_l2(0 to 2) ); + +buffer_ifar_latch: tri_rlmreg_p + generic map (width => buffer_ifar_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => valid_in(0), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(buffer_ifar_offset to buffer_ifar_offset+buffer_ifar_l2'length-1), + scout => sov(buffer_ifar_offset to buffer_ifar_offset+buffer_ifar_l2'length-1), + din => buffer_ifar_d, + dout => buffer_ifar_l2 ); + +redirect_latch: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(redirect_offset), + scout => sov(redirect_offset), + din => redirect_d, + dout => redirect_l2 ); + + + + +buff1_sel_latch: tri_rlmreg_p + generic map (width => buff1_sel_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(buff1_sel_offset to buff1_sel_offset+buff1_sel_l2'length-1), + scout => sov(buff1_sel_offset to buff1_sel_offset+buff1_sel_l2'length-1), + din => buff1_sel_d(0 to 4), + dout => buff1_sel_l2(0 to 4) ); + + +event_bus_enable_d <= pc_iu_event_bus_enable; + +event_enable_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(event_bus_enable_offset), + scout => sov(event_bus_enable_offset), + din => event_bus_enable_d, + dout => event_bus_enable_q); + +trace_bus_enable_d <= pc_iu_trace_bus_enable; + +trace_enable_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(trace_bus_enable_offset), + scout => sov(trace_bus_enable_offset), + din => trace_bus_enable_d, + dout => trace_bus_enable_q); + +perf_event_latch: tri_rlmreg_p + generic map (width => perf_event_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => event_bus_enable_q, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + + scin => siv(perf_event_offset to perf_event_offset+perf_event_l2'length-1), + scout => sov(perf_event_offset to perf_event_offset+perf_event_l2'length-1), + din => perf_event_d(0 to 1), + dout => perf_event_l2(0 to 1) ); + +ib_dbg_data_latch: tri_rlmreg_p + generic map (width => ib_dbg_data_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => trace_bus_enable_q, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + + scin => siv(ib_dbg_data_offset to ib_dbg_data_offset+ib_dbg_data_l2'length-1), + scout => sov(ib_dbg_data_offset to ib_dbg_data_offset+ib_dbg_data_l2'length-1), + din => ib_dbg_data_d, + dout => ib_dbg_data_l2 ); + +spare_latch: tri_rlmreg_p + generic map (width => spare_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(spare_offset to spare_offset + spare_l2'length-1), + scout => sov(spare_offset to spare_offset + spare_l2'length-1), + din => spare_l2, + dout => spare_l2); + +------------------------------------------------- +-- pervasive +------------------------------------------------- + +perv_2to1_reg: tri_plat + generic map (width => 2, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_iu_func_sl_thold_2, + din(1) => pc_iu_sg_2, + q(0) => pc_iu_func_sl_thold_1, + q(1) => pc_iu_sg_1); + +perv_1to0_reg: tri_plat + generic map (width => 2, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_iu_func_sl_thold_1, + din(1) => pc_iu_sg_1, + q(0) => pc_iu_func_sl_thold_0, + q(1) => pc_iu_sg_0); + +perv_lcbor: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_b, + thold => pc_iu_func_sl_thold_0, + sg => pc_iu_sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => pc_iu_func_sl_thold_0_b); + + + + +----------------------------------------------------------------------- +-- Scan +----------------------------------------------------------------------- +siv(0 to scan_right) <= sov(1 to scan_right) & scan_in; +scan_out <= sov(0) and an_ac_scan_dis_dc_b; + + +end iuq_ib_buff; diff --git a/rel/src/vhdl/work/iuq_ib_buff_wrap.vhdl b/rel/src/vhdl/work/iuq_ib_buff_wrap.vhdl new file mode 100644 index 0000000..b92a9d4 --- /dev/null +++ b/rel/src/vhdl/work/iuq_ib_buff_wrap.vhdl @@ -0,0 +1,367 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +--******************************************************************** +--* +--* TITLE: Instruction buffer wrapper +--* +--* NAME: iuq_ib_buff_wrap.vhdl +--* +--********************************************************************* + +library ieee; +use ieee.std_logic_1164.all; +library support; +use support.power_logic_pkg.all; +library work; +use work.iuq_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity iuq_ib_buff_wrap is + generic(expand_type : integer := 2; + uc_ifar : integer := 21); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + pc_iu_func_sl_thold_2 : in std_ulogic_vector(0 to 3); + pc_iu_sg_2 : in std_ulogic_vector(0 to 3); + clkoff_b : in std_ulogic_vector(0 to 3); + an_ac_scan_dis_dc_b : in std_ulogic_vector(0 to 3); + tc_ac_ccflush_dc : in std_ulogic; + delay_lclkr : in std_ulogic_vector(5 to 8); + mpw1_b : in std_ulogic_vector(5 to 8); + iuq_b0_scan_in : in std_ulogic; + iuq_b0_scan_out : out std_ulogic; + iuq_b1_scan_in : in std_ulogic; + iuq_b1_scan_out : out std_ulogic; + iuq_b2_scan_in : in std_ulogic; + iuq_b2_scan_out : out std_ulogic; + iuq_b3_scan_in : in std_ulogic; + iuq_b3_scan_out : out std_ulogic; + + spr_dec_mask_pt_in_t0 : in std_ulogic_vector(0 to 31); + spr_dec_mask_pt_in_t1 : in std_ulogic_vector(0 to 31); + spr_dec_mask_pt_in_t2 : in std_ulogic_vector(0 to 31); + spr_dec_mask_pt_in_t3 : in std_ulogic_vector(0 to 31); + spr_dec_mask_pt_out_t0 : out std_ulogic_vector(0 to 31); + spr_dec_mask_pt_out_t1 : out std_ulogic_vector(0 to 31); + spr_dec_mask_pt_out_t2 : out std_ulogic_vector(0 to 31); + spr_dec_mask_pt_out_t3 : out std_ulogic_vector(0 to 31); + fdep_dbg_data_pt_in : in std_ulogic_vector(0 to 87); + fdep_dbg_data_pt_out : out std_ulogic_vector(0 to 87); + fdep_perf_event_pt_in_t0 : in std_ulogic_vector(0 to 11); + fdep_perf_event_pt_in_t1 : in std_ulogic_vector(0 to 11); + fdep_perf_event_pt_in_t2 : in std_ulogic_vector(0 to 11); + fdep_perf_event_pt_in_t3 : in std_ulogic_vector(0 to 11); + fdep_perf_event_pt_out_t0 : out std_ulogic_vector(0 to 11); + fdep_perf_event_pt_out_t1 : out std_ulogic_vector(0 to 11); + fdep_perf_event_pt_out_t2 : out std_ulogic_vector(0 to 11); + fdep_perf_event_pt_out_t3 : out std_ulogic_vector(0 to 11); + + pc_iu_trace_bus_enable : in std_ulogic; + pc_iu_event_bus_enable : in std_ulogic; + ib_dbg_data : out std_ulogic_vector(0 to 63); + ib_perf_event_t0 : out std_ulogic_vector(0 to 1); + ib_perf_event_t1 : out std_ulogic_vector(0 to 1); + ib_perf_event_t2 : out std_ulogic_vector(0 to 1); + ib_perf_event_t3 : out std_ulogic_vector(0 to 1); + xu_iu_flush : in std_ulogic_vector(0 to 3); + uc_flush_tid : in std_ulogic_vector(0 to 3); + fdec_ibuf_stall_t0 : in std_ulogic; + fdec_ibuf_stall_t1 : in std_ulogic; + fdec_ibuf_stall_t2 : in std_ulogic; + fdec_ibuf_stall_t3 : in std_ulogic; + ib_ic_below_water : out std_ulogic_vector(0 to 3); + ib_ic_empty : out std_ulogic_vector(0 to 3); + bp_ib_iu4_t0_val : in std_ulogic_vector(0 to 3); + bp_ib_iu4_t1_val : in std_ulogic_vector(0 to 3); + bp_ib_iu4_t2_val : in std_ulogic_vector(0 to 3); + bp_ib_iu4_t3_val : in std_ulogic_vector(0 to 3); + bp_ib_iu4_ifar_t0 : in EFF_IFAR; + bp_ib_iu3_0_instr_t0 : in std_ulogic_vector(0 to 31); + bp_ib_iu4_0_instr_t0 : in std_ulogic_vector(32 to 43); + bp_ib_iu4_1_instr_t0 : in std_ulogic_vector(0 to 43); + bp_ib_iu4_2_instr_t0 : in std_ulogic_vector(0 to 43); + bp_ib_iu4_3_instr_t0 : in std_ulogic_vector(0 to 43); + bp_ib_iu4_ifar_t1 : in EFF_IFAR; + bp_ib_iu3_0_instr_t1 : in std_ulogic_vector(0 to 31); + bp_ib_iu4_0_instr_t1 : in std_ulogic_vector(32 to 43); + bp_ib_iu4_1_instr_t1 : in std_ulogic_vector(0 to 43); + bp_ib_iu4_2_instr_t1 : in std_ulogic_vector(0 to 43); + bp_ib_iu4_3_instr_t1 : in std_ulogic_vector(0 to 43); + bp_ib_iu4_ifar_t2 : in EFF_IFAR; + bp_ib_iu3_0_instr_t2 : in std_ulogic_vector(0 to 31); + bp_ib_iu4_0_instr_t2 : in std_ulogic_vector(32 to 43); + bp_ib_iu4_1_instr_t2 : in std_ulogic_vector(0 to 43); + bp_ib_iu4_2_instr_t2 : in std_ulogic_vector(0 to 43); + bp_ib_iu4_3_instr_t2 : in std_ulogic_vector(0 to 43); + bp_ib_iu4_ifar_t3 : in EFF_IFAR; + bp_ib_iu3_0_instr_t3 : in std_ulogic_vector(0 to 31); + bp_ib_iu4_0_instr_t3 : in std_ulogic_vector(32 to 43); + bp_ib_iu4_1_instr_t3 : in std_ulogic_vector(0 to 43); + bp_ib_iu4_2_instr_t3 : in std_ulogic_vector(0 to 43); + bp_ib_iu4_3_instr_t3 : in std_ulogic_vector(0 to 43); + uc_ib_iu4_val : in std_ulogic_vector(0 to 3); + uc_ib_iu4_ifar_t0 : in std_ulogic_vector(62-uc_ifar to 61); + uc_ib_iu4_instr_t0 : in std_ulogic_vector(0 to 36); + uc_ib_iu4_ifar_t1 : in std_ulogic_vector(62-uc_ifar to 61); + uc_ib_iu4_instr_t1 : in std_ulogic_vector(0 to 36); + uc_ib_iu4_ifar_t2 : in std_ulogic_vector(62-uc_ifar to 61); + uc_ib_iu4_instr_t2 : in std_ulogic_vector(0 to 36); + uc_ib_iu4_ifar_t3 : in std_ulogic_vector(62-uc_ifar to 61); + uc_ib_iu4_instr_t3 : in std_ulogic_vector(0 to 36); + rm_ib_iu4_val : in std_ulogic_vector(0 to 3); + rm_ib_iu4_force_ram_t0 : in std_ulogic; + rm_ib_iu4_instr_t0 : in std_ulogic_vector(0 to 35); + rm_ib_iu4_force_ram_t1 : in std_ulogic; + rm_ib_iu4_instr_t1 : in std_ulogic_vector(0 to 35); + rm_ib_iu4_force_ram_t2 : in std_ulogic; + rm_ib_iu4_instr_t2 : in std_ulogic_vector(0 to 35); + rm_ib_iu4_force_ram_t3 : in std_ulogic; + rm_ib_iu4_instr_t3 : in std_ulogic_vector(0 to 35); + ib_ic_iu5_redirect_tid : out std_ulogic_vector(0 to 3); + iu_au_ib1_instr_vld_t0 : out std_ulogic; + iu_au_ib1_instr_vld_t1 : out std_ulogic; + iu_au_ib1_instr_vld_t2 : out std_ulogic; + iu_au_ib1_instr_vld_t3 : out std_ulogic; + iu_au_ib1_ifar_t0 : out EFF_IFAR; + iu_au_ib1_ifar_t1 : out EFF_IFAR; + iu_au_ib1_ifar_t2 : out EFF_IFAR; + iu_au_ib1_ifar_t3 : out EFF_IFAR; + iu_au_ib1_data_t0 : out std_ulogic_vector(0 to 49); + iu_au_ib1_data_t1 : out std_ulogic_vector(0 to 49); + iu_au_ib1_data_t2 : out std_ulogic_vector(0 to 49); + iu_au_ib1_data_t3 : out std_ulogic_vector(0 to 49) +); +end iuq_ib_buff_wrap; +architecture iuq_ib_buff_wrap of iuq_ib_buff_wrap is +begin +ibuff0 : entity work.iuq_ib_buff +generic map( + uc_ifar => uc_ifar, + expand_type => expand_type ) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_iu_func_sl_thold_2 => pc_iu_func_sl_thold_2(0), + pc_iu_sg_2 => pc_iu_sg_2(0), + clkoff_b => clkoff_b(0), + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b(0), + tc_ac_ccflush_dc => tc_ac_ccflush_dc, + delay_lclkr => delay_lclkr(5+0), + mpw1_b => mpw1_b(5+0), + scan_in => iuq_b0_scan_in, + scan_out => iuq_b0_scan_out, + spr_dec_mask_pt_in => spr_dec_mask_pt_in_t0, + spr_dec_mask_pt_out => spr_dec_mask_pt_out_t0, + fdep_dbg_data_pt_in => fdep_dbg_data_pt_in(22*0 to 22*0+21), + fdep_dbg_data_pt_out => fdep_dbg_data_pt_out(22*0 to 22*0+21), + fdep_perf_event_pt_in => fdep_perf_event_pt_in_t0, + fdep_perf_event_pt_out => fdep_perf_event_pt_out_t0, + pc_iu_trace_bus_enable => pc_iu_trace_bus_enable, + pc_iu_event_bus_enable => pc_iu_event_bus_enable, + ib_dbg_data => ib_dbg_data(16*0 to 16*0+15), + ib_perf_event => ib_perf_event_t0, + xu_iu_ib1_flush => xu_iu_flush(0), + uc_flush => uc_flush_tid(0), + fdec_ibuf_stall => fdec_ibuf_stall_t0, + ib_ic_below_water => ib_ic_below_water(0), + ib_ic_empty => ib_ic_empty(0), + bp_ib_iu4_ifar => bp_ib_iu4_ifar_t0, + bp_ib_iu4_val => bp_ib_iu4_t0_val, + bp_ib_iu3_0_instr => bp_ib_iu3_0_instr_t0, + bp_ib_iu4_0_instr => bp_ib_iu4_0_instr_t0, + bp_ib_iu4_1_instr => bp_ib_iu4_1_instr_t0, + bp_ib_iu4_2_instr => bp_ib_iu4_2_instr_t0, + bp_ib_iu4_3_instr => bp_ib_iu4_3_instr_t0, + uc_ib_iu4_ifar => uc_ib_iu4_ifar_t0, + uc_ib_iu4_val => uc_ib_iu4_val(0), + uc_ib_iu4_instr => uc_ib_iu4_instr_t0, + rm_ib_iu4_val => rm_ib_iu4_val(0), + rm_ib_iu4_force_ram => rm_ib_iu4_force_ram_t0, + rm_ib_iu4_instr => rm_ib_iu4_instr_t0, + ib_ic_iu5_redirect_tid => ib_ic_iu5_redirect_tid(0), + iu_au_ib1_valid => iu_au_ib1_instr_vld_t0, + iu_au_ib1_ifar => iu_au_ib1_ifar_t0, + iu_au_ib1_data => iu_au_ib1_data_t0 +); +ibuff1 : entity work.iuq_ib_buff +generic map( + uc_ifar => uc_ifar, + expand_type => expand_type ) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_iu_func_sl_thold_2 => pc_iu_func_sl_thold_2(1), + pc_iu_sg_2 => pc_iu_sg_2(1), + clkoff_b => clkoff_b(1), + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b(1), + tc_ac_ccflush_dc => tc_ac_ccflush_dc, + delay_lclkr => delay_lclkr(5+1), + mpw1_b => mpw1_b(5+1), + scan_in => iuq_b1_scan_in, + scan_out => iuq_b1_scan_out, + spr_dec_mask_pt_in => spr_dec_mask_pt_in_t1, + spr_dec_mask_pt_out => spr_dec_mask_pt_out_t1, + fdep_dbg_data_pt_in => fdep_dbg_data_pt_in(22*1 to 22*1+21), + fdep_dbg_data_pt_out => fdep_dbg_data_pt_out(22*1 to 22*1+21), + fdep_perf_event_pt_in => fdep_perf_event_pt_in_t1, + fdep_perf_event_pt_out => fdep_perf_event_pt_out_t1, + pc_iu_trace_bus_enable => pc_iu_trace_bus_enable, + pc_iu_event_bus_enable => pc_iu_event_bus_enable, + ib_dbg_data => ib_dbg_data(16*1 to 16*1+15), + ib_perf_event => ib_perf_event_t1, + xu_iu_ib1_flush => xu_iu_flush(1), + uc_flush => uc_flush_tid(1), + fdec_ibuf_stall => fdec_ibuf_stall_t1, + ib_ic_below_water => ib_ic_below_water(1), + ib_ic_empty => ib_ic_empty(1), + bp_ib_iu4_ifar => bp_ib_iu4_ifar_t1, + bp_ib_iu4_val => bp_ib_iu4_t1_val, + bp_ib_iu3_0_instr => bp_ib_iu3_0_instr_t1, + bp_ib_iu4_0_instr => bp_ib_iu4_0_instr_t1, + bp_ib_iu4_1_instr => bp_ib_iu4_1_instr_t1, + bp_ib_iu4_2_instr => bp_ib_iu4_2_instr_t1, + bp_ib_iu4_3_instr => bp_ib_iu4_3_instr_t1, + uc_ib_iu4_ifar => uc_ib_iu4_ifar_t1, + uc_ib_iu4_val => uc_ib_iu4_val(1), + uc_ib_iu4_instr => uc_ib_iu4_instr_t1, + rm_ib_iu4_val => rm_ib_iu4_val(1), + rm_ib_iu4_force_ram => rm_ib_iu4_force_ram_t1, + rm_ib_iu4_instr => rm_ib_iu4_instr_t1, + ib_ic_iu5_redirect_tid => ib_ic_iu5_redirect_tid(1), + iu_au_ib1_valid => iu_au_ib1_instr_vld_t1, + iu_au_ib1_ifar => iu_au_ib1_ifar_t1, + iu_au_ib1_data => iu_au_ib1_data_t1 +); +ibuff2 : entity work.iuq_ib_buff +generic map( + uc_ifar => uc_ifar, + expand_type => expand_type ) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_iu_func_sl_thold_2 => pc_iu_func_sl_thold_2(2), + pc_iu_sg_2 => pc_iu_sg_2(2), + clkoff_b => clkoff_b(2), + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b(2), + tc_ac_ccflush_dc => tc_ac_ccflush_dc, + delay_lclkr => delay_lclkr(5+2), + mpw1_b => mpw1_b(5+2), + scan_in => iuq_b2_scan_in, + scan_out => iuq_b2_scan_out, + spr_dec_mask_pt_in => spr_dec_mask_pt_in_t2, + spr_dec_mask_pt_out => spr_dec_mask_pt_out_t2, + fdep_dbg_data_pt_in => fdep_dbg_data_pt_in(22*2 to 22*2+21), + fdep_dbg_data_pt_out => fdep_dbg_data_pt_out(22*2 to 22*2+21), + fdep_perf_event_pt_in => fdep_perf_event_pt_in_t2, + fdep_perf_event_pt_out => fdep_perf_event_pt_out_t2, + pc_iu_trace_bus_enable => pc_iu_trace_bus_enable, + pc_iu_event_bus_enable => pc_iu_event_bus_enable, + ib_dbg_data => ib_dbg_data(16*2 to 16*2+15), + ib_perf_event => ib_perf_event_t2, + xu_iu_ib1_flush => xu_iu_flush(2), + uc_flush => uc_flush_tid(2), + fdec_ibuf_stall => fdec_ibuf_stall_t2, + ib_ic_below_water => ib_ic_below_water(2), + ib_ic_empty => ib_ic_empty(2), + bp_ib_iu4_ifar => bp_ib_iu4_ifar_t2, + bp_ib_iu4_val => bp_ib_iu4_t2_val, + bp_ib_iu3_0_instr => bp_ib_iu3_0_instr_t2, + bp_ib_iu4_0_instr => bp_ib_iu4_0_instr_t2, + bp_ib_iu4_1_instr => bp_ib_iu4_1_instr_t2, + bp_ib_iu4_2_instr => bp_ib_iu4_2_instr_t2, + bp_ib_iu4_3_instr => bp_ib_iu4_3_instr_t2, + uc_ib_iu4_ifar => uc_ib_iu4_ifar_t2, + uc_ib_iu4_val => uc_ib_iu4_val(2), + uc_ib_iu4_instr => uc_ib_iu4_instr_t2, + rm_ib_iu4_val => rm_ib_iu4_val(2), + rm_ib_iu4_force_ram => rm_ib_iu4_force_ram_t2, + rm_ib_iu4_instr => rm_ib_iu4_instr_t2, + ib_ic_iu5_redirect_tid => ib_ic_iu5_redirect_tid(2), + iu_au_ib1_valid => iu_au_ib1_instr_vld_t2, + iu_au_ib1_ifar => iu_au_ib1_ifar_t2, + iu_au_ib1_data => iu_au_ib1_data_t2 +); +ibuff3 : entity work.iuq_ib_buff +generic map( + uc_ifar => uc_ifar, + expand_type => expand_type ) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_iu_func_sl_thold_2 => pc_iu_func_sl_thold_2(3), + pc_iu_sg_2 => pc_iu_sg_2(3), + clkoff_b => clkoff_b(3), + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b(3), + tc_ac_ccflush_dc => tc_ac_ccflush_dc, + delay_lclkr => delay_lclkr(5+3), + mpw1_b => mpw1_b(5+3), + scan_in => iuq_b3_scan_in, + scan_out => iuq_b3_scan_out, + spr_dec_mask_pt_in => spr_dec_mask_pt_in_t3, + spr_dec_mask_pt_out => spr_dec_mask_pt_out_t3, + fdep_dbg_data_pt_in => fdep_dbg_data_pt_in(22*3 to 22*3+21), + fdep_dbg_data_pt_out => fdep_dbg_data_pt_out(22*3 to 22*3+21), + fdep_perf_event_pt_in => fdep_perf_event_pt_in_t3, + fdep_perf_event_pt_out => fdep_perf_event_pt_out_t3, + pc_iu_trace_bus_enable => pc_iu_trace_bus_enable, + pc_iu_event_bus_enable => pc_iu_event_bus_enable, + ib_dbg_data => ib_dbg_data(16*3 to 16*3+15), + ib_perf_event => ib_perf_event_t3, + xu_iu_ib1_flush => xu_iu_flush(3), + uc_flush => uc_flush_tid(3), + fdec_ibuf_stall => fdec_ibuf_stall_t3, + ib_ic_below_water => ib_ic_below_water(3), + ib_ic_empty => ib_ic_empty(3), + bp_ib_iu4_ifar => bp_ib_iu4_ifar_t3, + bp_ib_iu4_val => bp_ib_iu4_t3_val, + bp_ib_iu3_0_instr => bp_ib_iu3_0_instr_t3, + bp_ib_iu4_0_instr => bp_ib_iu4_0_instr_t3, + bp_ib_iu4_1_instr => bp_ib_iu4_1_instr_t3, + bp_ib_iu4_2_instr => bp_ib_iu4_2_instr_t3, + bp_ib_iu4_3_instr => bp_ib_iu4_3_instr_t3, + uc_ib_iu4_ifar => uc_ib_iu4_ifar_t3, + uc_ib_iu4_val => uc_ib_iu4_val(3), + uc_ib_iu4_instr => uc_ib_iu4_instr_t3, + rm_ib_iu4_val => rm_ib_iu4_val(3), + rm_ib_iu4_force_ram => rm_ib_iu4_force_ram_t3, + rm_ib_iu4_instr => rm_ib_iu4_instr_t3, + ib_ic_iu5_redirect_tid => ib_ic_iu5_redirect_tid(3), + iu_au_ib1_valid => iu_au_ib1_instr_vld_t3, + iu_au_ib1_ifar => iu_au_ib1_ifar_t3, + iu_au_ib1_data => iu_au_ib1_data_t3 +); +end iuq_ib_buff_wrap; diff --git a/rel/src/vhdl/work/iuq_ic.vhdl b/rel/src/vhdl/work/iuq_ic.vhdl new file mode 100644 index 0000000..77143a0 --- /dev/null +++ b/rel/src/vhdl/work/iuq_ic.vhdl @@ -0,0 +1,1374 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +--******************************************************************** +--* +--* TITLE: Instruction Cache +--* +--* NAME: iuq_ic.vhdl +--* +--********************************************************************* + +library ieee; +use ieee.std_logic_1164.all; +library support; +use support.power_logic_pkg.all; +library clib; +library tri; +use tri.tri_latches_pkg.all; +library work; +use work.iuq_pkg.all; + +entity iuq_ic is + generic(regmode : integer := 6; + bcfg_epn_0to15 : integer := 0; + bcfg_epn_16to31 : integer := 0; + bcfg_epn_32to47 : integer := (2**16)-1; + bcfg_epn_48to51 : integer := (2**4)-1; + bcfg_rpn_22to31 : integer := (2**10)-1; + bcfg_rpn_32to47 : integer := (2**16)-1; + bcfg_rpn_48to51 : integer := (2**4)-1; + expand_type : integer := 2 ); +port( + vcs : inout power_logic; + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + + tc_ac_ccflush_dc : in std_ulogic; + an_ac_scan_dis_dc_b : in std_ulogic; + an_ac_scan_diag_dc : in std_ulogic; + + pc_iu_func_sl_thold_2 : in std_ulogic; + pc_iu_func_slp_sl_thold_2 : in std_ulogic; + pc_iu_time_sl_thold_2 : in std_ulogic; + pc_iu_abst_sl_thold_2 : in std_ulogic; + pc_iu_abst_slp_sl_thold_2 : in std_ulogic; + pc_iu_repr_sl_thold_2 : in std_ulogic; + pc_iu_cfg_slp_sl_thold_2 : in std_ulogic; + pc_iu_regf_slp_sl_thold_2 : in std_ulogic; + pc_iu_ary_nsl_thold_2 : in std_ulogic; + pc_iu_ary_slp_nsl_thold_2 : in std_ulogic; + pc_iu_func_slp_nsl_thold_2 : in std_ulogic; + pc_iu_bolt_sl_thold_2 : in std_ulogic; + pc_iu_sg_2 : in std_ulogic; + pc_iu_fce_2 : in std_ulogic; + clkoff_b : in std_ulogic; + delay_lclkr : in std_ulogic_vector(0 to 1); + mpw1_b : in std_ulogic_vector(0 to 1); + g8t_clkoff_b : in std_ulogic; + g8t_d_mode : in std_ulogic; + g8t_delay_lclkr : in std_ulogic_vector(0 to 4); + g8t_mpw1_b : in std_ulogic_vector(0 to 4); + g8t_mpw2_b : in std_ulogic; + g6t_clkoff_b : in std_ulogic; + g6t_d_mode : in std_ulogic; + g6t_delay_lclkr : in std_ulogic_vector(0 to 3); + g6t_mpw1_b : in std_ulogic_vector(0 to 4); + g6t_mpw2_b : in std_ulogic; + cam_clkoff_b : in std_ulogic; + cam_d_mode : in std_ulogic; + cam_delay_lclkr : in std_ulogic_vector(0 to 4); + cam_mpw1_b : in std_ulogic_vector(0 to 4); + cam_mpw2_b : in std_ulogic; + + func_scan_in : in std_ulogic_vector(0 to 4); + func_scan_out : out std_ulogic_vector(0 to 4); + ac_ccfg_scan_in : in std_ulogic; + ac_ccfg_scan_out : out std_ulogic; + time_scan_in : in std_ulogic; + time_scan_out : out std_ulogic; + repr_scan_in : in std_ulogic; + repr_scan_out : out std_ulogic; + abst_scan_in : in std_ulogic_vector(0 to 2); + abst_scan_out : out std_ulogic_vector(0 to 2); + regf_scan_in : in std_ulogic_vector(0 to 4); + regf_scan_out : out std_ulogic_vector(0 to 4); + + uc_dbg_data : in std_ulogic_vector(0 to 87); + + pc_iu_trace_bus_enable : in std_ulogic; + pc_iu_debug_mux_ctrls : in std_ulogic_vector(0 to 15); + + debug_data_in : in std_ulogic_vector(0 to 87); + trace_triggers_in : in std_ulogic_vector(0 to 11); + + debug_data_out : out std_ulogic_vector(0 to 87); + trace_triggers_out : out std_ulogic_vector(0 to 11); + + pc_iu_event_bus_enable : in std_ulogic; + + ic_perf_event_t0 : out std_ulogic_vector(0 to 6); + ic_perf_event_t1 : out std_ulogic_vector(0 to 6); + ic_perf_event_t2 : out std_ulogic_vector(0 to 6); + ic_perf_event_t3 : out std_ulogic_vector(0 to 6); + ic_perf_event : out std_ulogic_vector(0 to 1); + + iu_pc_err_icache_parity : out std_ulogic; + iu_pc_err_icachedir_parity : out std_ulogic; + iu_pc_err_icachedir_multihit : out std_ulogic; + + pc_iu_inj_icache_parity : in std_ulogic; + pc_iu_inj_icachedir_parity : in std_ulogic; + pc_iu_inj_icachedir_multihit : in std_ulogic; + + pc_iu_abist_g8t_wenb : in std_ulogic; + pc_iu_abist_g8t1p_renb_0 : in std_ulogic; + pc_iu_abist_di_0 : in std_ulogic_vector(0 to 3); + pc_iu_abist_g8t_bw_1 : in std_ulogic; + pc_iu_abist_g8t_bw_0 : in std_ulogic; + pc_iu_abist_waddr_0 : in std_ulogic_vector(4 to 9); + pc_iu_abist_raddr_0 : in std_ulogic_vector(2 to 9); + pc_iu_abist_ena_dc : in std_ulogic; + pc_iu_abist_wl64_comp_ena : in std_ulogic; + pc_iu_abist_raw_dc_b : in std_ulogic; + pc_iu_abist_g8t_dcomp : in std_ulogic_vector(0 to 3); + pc_iu_abist_g6t_bw : in std_ulogic_vector(0 to 1); + pc_iu_abist_di_g6t_2r : in std_ulogic_vector(0 to 3); + pc_iu_abist_wl256_comp_ena : in std_ulogic; + pc_iu_abist_dcomp_g6t_2r : in std_ulogic_vector(0 to 3); + pc_iu_abist_g6t_r_wb : in std_ulogic; + an_ac_lbist_ary_wrt_thru_dc: in std_ulogic; + an_ac_lbist_en_dc : in std_ulogic; + an_ac_atpg_en_dc : in std_ulogic; + an_ac_grffence_en_dc : in std_ulogic; + + pc_iu_bo_enable_3 : in std_ulogic; + pc_iu_bo_reset : in std_ulogic; + pc_iu_bo_unload : in std_ulogic; + pc_iu_bo_repair : in std_ulogic; + pc_iu_bo_shdata : in std_ulogic; + pc_iu_bo_select : in std_ulogic_vector(0 to 3); + iu_pc_bo_fail : out std_ulogic_vector(0 to 3); + iu_pc_bo_diagout : out std_ulogic_vector(0 to 3); + + pc_iu_init_reset : in std_ulogic; + + xu_iu_rf1_val : in std_ulogic_vector(0 to 3); + xu_iu_rf1_is_eratre : in std_ulogic; + xu_iu_rf1_is_eratwe : in std_ulogic; + xu_iu_rf1_is_eratsx : in std_ulogic; + xu_iu_rf1_is_eratilx : in std_ulogic; + xu_iu_ex1_is_isync : in std_ulogic; + xu_iu_ex1_is_csync : in std_ulogic; + xu_iu_rf1_ws : in std_ulogic_vector(0 to 1); + xu_iu_rf1_t : in std_ulogic_vector(0 to 2); + xu_iu_ex1_rs_is : in std_ulogic_vector(0 to 8); + xu_iu_ex1_ra_entry : in std_ulogic_vector(0 to 3); + + xu_iu_ex1_rb : in std_ulogic_vector(64-(2**regmode) to 51); + xu_rf1_flush : in std_ulogic_vector(0 to 3); + xu_ex1_flush : in std_ulogic_vector(0 to 3); + xu_ex2_flush : in std_ulogic_vector(0 to 3); + xu_ex3_flush : in std_ulogic_vector(0 to 3); + xu_ex4_flush : in std_ulogic_vector(0 to 3); + xu_ex5_flush : in std_ulogic_vector(0 to 3); + xu_iu_ex4_rs_data : in std_ulogic_vector(64-(2**regmode) to 63); + xu_iu_msr_hv : in std_ulogic_vector(0 to 3); + xu_iu_msr_pr : in std_ulogic_vector(0 to 3); + xu_iu_msr_is : in std_ulogic_vector(0 to 3); + xu_iu_hid_mmu_mode : in std_ulogic; + xu_iu_spr_ccr2_ifratsc : in std_ulogic_vector(0 to 8); + xu_iu_spr_ccr2_ifrat : in std_ulogic; + xu_iu_xucr4_mmu_mchk : in std_ulogic; + iu_xu_ex4_data : out std_ulogic_vector(64-(2**regmode) to 63); + iu_xu_ierat_ex3_par_err : out std_ulogic_vector(0 to 3); + iu_xu_ierat_ex4_par_err : out std_ulogic_vector(0 to 3); + iu_xu_ierat_ex2_flush_req : out std_ulogic_vector(0 to 3); + + iu_mm_ierat_req : out std_ulogic; + iu_mm_ierat_epn : out std_ulogic_vector(0 to 51); + iu_mm_ierat_thdid : out std_ulogic_vector(0 to 3); + iu_mm_ierat_state : out std_ulogic_vector(0 to 3); + iu_mm_ierat_tid : out std_ulogic_vector(0 to 13); + iu_mm_ierat_flush : out std_ulogic_vector(0 to 3); + + mm_iu_ierat_rel_val : in std_ulogic_vector(0 to 4); + mm_iu_ierat_rel_data : in std_ulogic_vector(0 to 131); + + mm_iu_ierat_pid0 : in std_ulogic_vector(0 to 13); + mm_iu_ierat_pid1 : in std_ulogic_vector(0 to 13); + mm_iu_ierat_pid2 : in std_ulogic_vector(0 to 13); + mm_iu_ierat_pid3 : in std_ulogic_vector(0 to 13); + mm_iu_ierat_mmucr0_0 : in std_ulogic_vector(0 to 19); + mm_iu_ierat_mmucr0_1 : in std_ulogic_vector(0 to 19); + mm_iu_ierat_mmucr0_2 : in std_ulogic_vector(0 to 19); + mm_iu_ierat_mmucr0_3 : in std_ulogic_vector(0 to 19); + iu_mm_ierat_mmucr0 : out std_ulogic_vector(0 to 17); + iu_mm_ierat_mmucr0_we : out std_ulogic_vector(0 to 3); + mm_iu_ierat_mmucr1 : in std_ulogic_vector(0 to 8); + iu_mm_ierat_mmucr1 : out std_ulogic_vector(0 to 3); + iu_mm_ierat_mmucr1_we : out std_ulogic; + + mm_iu_ierat_snoop_coming : in std_ulogic; + mm_iu_ierat_snoop_val : in std_ulogic; + mm_iu_ierat_snoop_attr : in std_ulogic_vector(0 to 25); + mm_iu_ierat_snoop_vpn : in std_ulogic_vector(EFF_IFAR'left to 51); + iu_mm_ierat_snoop_ack : out std_ulogic; + + iu_mm_lmq_empty : out std_ulogic; + + ac_an_power_managed : in std_ulogic; + + xu_iu_run_thread : in std_ulogic_vector(0 to 3); + + xu_iu_flush : in std_ulogic_vector(0 to 3); + xu_iu_iu0_flush_ifar0 : in EFF_IFAR; + xu_iu_iu0_flush_ifar1 : in EFF_IFAR; + xu_iu_iu0_flush_ifar2 : in EFF_IFAR; + xu_iu_iu0_flush_ifar3 : in EFF_IFAR; + xu_iu_flush_2ucode : in std_ulogic_vector(0 to 3); + xu_iu_flush_2ucode_type : in std_ulogic_vector(0 to 3); + + xu_iu_msr_cm : in std_ulogic_vector(0 to 3); + + xu_iu_ex6_icbi_val : in std_ulogic_vector(0 to 3); + xu_iu_ex6_icbi_addr : in std_ulogic_vector(REAL_IFAR'left to 57); + + xu_iu_ici : in std_ulogic; + + spr_ic_cls : in std_ulogic; + spr_ic_clockgate_dis : in std_ulogic_vector(0 to 1); + spr_ic_icbi_ack_en : in std_ulogic; + spr_ic_bp_config : in std_ulogic_vector(0 to 3); + + spr_ic_idir_read : in std_ulogic; + spr_ic_idir_way : in std_ulogic_vector(0 to 1); + spr_ic_idir_row : in std_ulogic_vector(52 to 57); + spr_ic_pri_rand : in std_ulogic_vector(0 to 4); + spr_ic_pri_rand_always : in std_ulogic; + spr_ic_pri_rand_flush : in std_ulogic; + + ic_spr_idir_done : out std_ulogic; + ic_spr_idir_lru : out std_ulogic_vector(0 to 2); + ic_spr_idir_parity : out std_ulogic_vector(0 to 3); + ic_spr_idir_endian : out std_ulogic; + ic_spr_idir_valid : out std_ulogic; + ic_spr_idir_tag : out std_ulogic_vector(0 to 29); + + iu_xu_request : out std_ulogic; + iu_xu_thread : out std_ulogic_vector(0 to 3); + iu_xu_ra : out std_ulogic_vector(REAL_IFAR'left to 59); + iu_xu_wimge : out std_ulogic_vector(0 to 4); + iu_xu_userdef : out std_ulogic_vector(0 to 3); + + an_ac_reld_data_vld : in std_ulogic; + an_ac_reld_core_tag : in std_ulogic_vector(0 to 4); + an_ac_reld_qw : in std_ulogic_vector(57 to 59); + an_ac_reld_data : in std_ulogic_vector(0 to 127); + an_ac_reld_ecc_err : in std_ulogic; + an_ac_reld_ecc_err_ue : in std_ulogic; + + an_ac_back_inv : in std_ulogic; + an_ac_back_inv_addr : in std_ulogic_vector(REAL_IFAR'left to 57); + an_ac_back_inv_target : in std_ulogic; + + an_ac_icbi_ack : in std_ulogic; + an_ac_icbi_ack_thread : in std_ulogic_vector(0 to 1); + + bp_ib_iu4_ifar : in EFF_IFAR; + + bp_ic_iu5_hold_tid : in std_ulogic_vector(0 to 3); + bp_ic_iu5_redirect_tid : in std_ulogic_vector(0 to 3); + bp_ic_iu5_redirect_ifar : in EFF_IFAR; + + ic_bp_iu1_val : out std_ulogic; + ic_bp_iu1_tid : out std_ulogic_vector(0 to 3); + ic_bp_iu1_ifar : out std_ulogic_vector(52 to 59); + + ic_bp_iu3_val : out std_ulogic_vector(0 to 3); + ic_bp_iu3_tid : out std_ulogic_vector(0 to 3); + ic_bp_iu3_ifar : out EFF_IFAR; + ic_bp_iu3_2ucode : out std_ulogic; + ic_bp_iu3_2ucode_type : out std_ulogic; + ic_bp_iu3_error : out std_ulogic_vector(0 to 2); + ic_bp_iu3_flush : out std_ulogic; + + ic_bp_iu3_0_instr : out std_ulogic_vector(0 to 35); + ic_bp_iu3_1_instr : out std_ulogic_vector(0 to 35); + ic_bp_iu3_2_instr : out std_ulogic_vector(0 to 35); + ic_bp_iu3_3_instr : out std_ulogic_vector(0 to 35); + + ib_ic_empty : in std_ulogic_vector(0 to 3); + ib_ic_below_water : in std_ulogic_vector(0 to 3); + ib_ic_iu5_redirect_tid : in std_ulogic_vector(0 to 3); + + ic_fdep_load_quiesce : out std_ulogic_vector(0 to 3); + ic_fdep_icbi_ack : out std_ulogic_vector(0 to 3); + + uc_flush_tid : in std_ulogic_vector(0 to 3); + uc_ic_hold_thread : in std_ulogic_vector(0 to 3) + +); +-- synopsys translate_off +-- synopsys translate_on +end iuq_ic; +architecture iuq_ic of iuq_ic is +constant epn_width : integer := 52-EFF_IFAR'left; +constant rpn_width : integer := 52-REAL_IFAR'left; +constant rs_data_width : integer := 2**regmode; +constant data_out_width : integer := 2**regmode; +constant trigger_data_out_offset: natural := 0; +constant trace_data_out_offset : natural := trigger_data_out_offset + 12; +constant event_bus_enable_offset: natural := trace_data_out_offset + 88; +constant trace_bus_enable_offset: natural := event_bus_enable_offset + 1; +constant debug_mux_ctrls_offset : natural := trace_bus_enable_offset + 1; +constant scan_right : natural := debug_mux_ctrls_offset + 16-1; +signal iu_ierat_iu0_val : std_ulogic; +signal iu_ierat_iu0_thdid : std_ulogic_vector(0 to 3); +signal iu_ierat_iu0_ifar : std_ulogic_vector(0 to 51); +signal iu_ierat_iu0_flush : std_ulogic_vector(0 to 3); +signal iu_ierat_iu1_flush : std_ulogic_vector(0 to 3); +signal iu_ierat_iu1_back_inv : std_ulogic; +signal iu_ierat_ium1_back_inv : std_ulogic; +signal ierat_iu_iu2_rpn : std_ulogic_vector(22 to 51); +signal ierat_iu_iu2_wimge : std_ulogic_vector(0 to 4); +signal ierat_iu_iu2_u : std_ulogic_vector(0 to 3); +signal ierat_iu_iu2_error : std_ulogic_vector(0 to 2); +signal ierat_iu_iu2_miss : std_ulogic; +signal ierat_iu_iu2_multihit : std_ulogic; +signal ierat_iu_iu2_isi : std_ulogic; +signal ierat_iu_hold_req : std_ulogic_vector(0 to 3); +signal ierat_iu_iu2_flush_req : std_ulogic_vector(0 to 3); +signal ics_icd_dir_rd_act : std_ulogic; +signal ics_icd_data_rd_act : std_ulogic; +signal ics_icd_iu0_valid : std_ulogic; +signal ics_icd_iu0_tid : std_ulogic_vector(0 to 3); +signal ics_icd_iu0_ifar : EFF_IFAR; +signal ics_icd_iu0_inval : std_ulogic; +signal ics_icd_iu0_2ucode : std_ulogic; +signal ics_icd_iu0_2ucode_type : std_ulogic; +signal ics_icd_iu0_spr_idir_read: std_ulogic; +signal icd_ics_iu1_valid : std_ulogic; +signal icd_ics_iu1_tid : std_ulogic_vector(0 to 3); +signal icd_ics_iu1_ifar : EFF_IFAR; +signal icd_ics_iu1_2ucode : std_ulogic; +signal icd_ics_iu1_2ucode_type : std_ulogic; +signal ics_icd_all_flush_prev : std_ulogic_vector(0 to 3); +signal ics_icd_iu1_flush_tid : std_ulogic_vector(0 to 3); +signal ics_icd_iu2_flush_tid : std_ulogic_vector(0 to 3); +signal icd_ics_iu2_miss_flush_prev : std_ulogic_vector(0 to 3); +signal icd_ics_iu2_ifar_eff : EFF_IFAR; +signal icd_ics_iu2_2ucode : std_ulogic; +signal icd_ics_iu2_2ucode_type : std_ulogic; +signal icd_ics_iu3_parity_flush : std_ulogic_vector(0 to 3); +signal icd_ics_iu3_ifar : EFF_IFAR; +signal icd_ics_iu3_2ucode : std_ulogic; +signal icd_ics_iu3_2ucode_type : std_ulogic; +signal icm_ics_iu0_preload_val : std_ulogic; +signal icm_ics_iu0_preload_tid : std_ulogic_vector(0 to 3); +signal icm_ics_iu0_preload_ifar : std_ulogic_vector(52 to 59); +signal icm_ics_hold_thread : std_ulogic_vector(0 to 3); +signal icm_ics_hold_thread_dbg : std_ulogic_vector(0 to 3); +signal icm_ics_hold_iu0 : std_ulogic; +signal icm_ics_ecc_block_iu0 : std_ulogic_vector(0 to 3); +signal icm_ics_load_tid : std_ulogic_vector(0 to 3); +signal icm_ics_iu1_ecc_flush : std_ulogic; +signal icm_ics_iu2_miss_match_prev : std_ulogic; +signal ics_icm_iu2_flush_tid : std_ulogic_vector(0 to 3); +signal ics_icm_iu3_flush_tid : std_ulogic_vector(0 to 3); +signal ics_icm_iu0_ifar0 : std_ulogic_vector(46 to 52); +signal ics_icm_iu0_ifar1 : std_ulogic_vector(46 to 52); +signal ics_icm_iu0_ifar2 : std_ulogic_vector(46 to 52); +signal ics_icm_iu0_ifar3 : std_ulogic_vector(46 to 52); +signal ics_icm_iu0_inval : std_ulogic; +signal ics_icm_iu0_inval_addr : std_ulogic_vector(52 to 57); +signal icm_icd_lru_addr : std_ulogic_vector(52 to 57); +signal icm_icd_dir_inval : std_ulogic; +signal icm_icd_dir_val : std_ulogic; +signal icm_icd_data_write : std_ulogic; +signal icm_icd_reload_addr : std_ulogic_vector(52 to 59); +signal icm_icd_reload_data : std_ulogic_vector(0 to 161); +signal icm_icd_reload_way : std_ulogic_vector(0 to 3); +signal icm_icd_load_tid : std_ulogic_vector(0 to 3); +signal icm_icd_load_addr : EFF_IFAR; +signal icm_icd_load_2ucode : std_ulogic; +signal icm_icd_load_2ucode_type : std_ulogic; +signal icm_icd_dir_write : std_ulogic; +signal icm_icd_dir_write_addr : std_ulogic_vector(REAL_IFAR'left to 57); +signal icm_icd_dir_write_endian : std_ulogic; +signal icm_icd_dir_write_way : std_ulogic_vector(0 to 3); +signal icm_icd_lru_write : std_ulogic; +signal icm_icd_lru_write_addr : std_ulogic_vector(52 to 57); +signal icm_icd_lru_write_way : std_ulogic_vector(0 to 3); +signal icm_icd_ecc_inval : std_ulogic; +signal icm_icd_ecc_addr : std_ulogic_vector(52 to 57); +signal icm_icd_ecc_way : std_ulogic_vector(0 to 3); +signal icm_icd_iu3_ecc_fp_cancel: std_ulogic; +signal icm_icd_iu3_ecc_err : std_ulogic; +signal icm_icd_any_reld_r2 : std_ulogic; +signal icm_icd_any_checkecc : std_ulogic; +signal icd_icm_miss : std_ulogic; +signal icd_icm_tid : std_ulogic_vector(0 to 3); +signal icd_icm_addr_real : REAL_IFAR; +signal icd_icm_addr_eff : std_ulogic_vector(EFF_IFAR'left to 51); +signal icd_icm_wimge : std_ulogic_vector(0 to 4); +signal icd_icm_userdef : std_ulogic_vector(0 to 3); +signal icd_icm_2ucode : std_ulogic; +signal icd_icm_2ucode_type : std_ulogic; +signal icd_icm_iu3_erat_err : std_ulogic; +signal icd_icm_iu2_inval : std_ulogic; +signal icd_icm_ici : std_ulogic; +signal icd_icm_any_iu2_valid : std_ulogic; +signal icd_icm_row_lru : std_ulogic_vector(0 to 2); +signal icd_icm_row_val : std_ulogic_vector(0 to 3); +signal int_ic_bp_iu3_val : std_ulogic_vector(0 to 3); +signal int_ic_bp_iu3_0_instr : std_ulogic_vector(0 to 35); +signal int_ic_bp_iu3_1_instr : std_ulogic_vector(0 to 35); +signal int_ic_bp_iu3_2_instr : std_ulogic_vector(0 to 35); +signal int_ic_bp_iu3_3_instr : std_ulogic_vector(0 to 35); +signal trigger_data_out_d : std_ulogic_vector(0 to 11); +signal trigger_data_out_q : std_ulogic_vector(0 to 11); +signal trace_data_out_d : std_ulogic_vector(0 to 87); +signal trace_data_out_q : std_ulogic_vector(0 to 87); +signal sel_dbg_data : std_ulogic_vector(0 to 87); +signal dir_dbg_data0 : std_ulogic_vector(0 to 87); +signal dir_dbg_data1 : std_ulogic_vector(0 to 87); +signal dir_dbg_data2 : std_ulogic_vector(0 to 43); +signal dir_dbg_trigger0 : std_ulogic_vector(0 to 7); +signal dir_dbg_trigger1 : std_ulogic_vector(0 to 11); +signal miss_dbg_data0 : std_ulogic_vector(0 to 87); +signal miss_dbg_data1 : std_ulogic_vector(0 to 87); +signal miss_dbg_data2 : std_ulogic_vector(0 to 43); +signal miss_dbg_trigger : std_ulogic_vector(0 to 11); +signal iu3_dbg_data : std_ulogic_vector(0 to 87); +signal ierat_iu_debug_group0 : std_ulogic_vector(0 to 87); +signal ierat_iu_debug_group1 : std_ulogic_vector(0 to 87); +signal ierat_iu_debug_group2 : std_ulogic_vector(0 to 87); +signal ierat_iu_debug_group3 : std_ulogic_vector(0 to 87); +signal dbg_group0 : std_ulogic_vector(0 to 87); +signal dbg_group1 : std_ulogic_vector(0 to 87); +signal dbg_group2 : std_ulogic_vector(0 to 87); +signal dbg_group3 : std_ulogic_vector(0 to 87); +signal dbg_group4 : std_ulogic_vector(0 to 87); +signal dbg_group5 : std_ulogic_vector(0 to 87); +signal dbg_group6 : std_ulogic_vector(0 to 87); +signal dbg_group7 : std_ulogic_vector(0 to 87); +signal dbg_group8 : std_ulogic_vector(0 to 87); +signal dbg_group9 : std_ulogic_vector(0 to 87); +signal dbg_group10 : std_ulogic_vector(0 to 87); +signal dbg_group11 : std_ulogic_vector(0 to 87); +signal dbg_group12 : std_ulogic_vector(0 to 87); +signal dbg_group13 : std_ulogic_vector(0 to 87); +signal dbg_group14 : std_ulogic_vector(0 to 87); +signal dbg_group15 : std_ulogic_vector(0 to 87); +signal trg_group0 : std_ulogic_vector(0 to 11); +signal trg_group1 : std_ulogic_vector(0 to 11); +signal trg_group2 : std_ulogic_vector(0 to 11); +signal trg_group3 : std_ulogic_vector(0 to 11); +signal pc_iu_func_sl_thold_1 : std_ulogic; +signal pc_iu_func_sl_thold_0 : std_ulogic; +signal pc_iu_func_sl_thold_0_b : std_ulogic; +signal pc_iu_func_slp_sl_thold_1: std_ulogic; +signal pc_iu_func_slp_sl_thold_0: std_ulogic; +signal pc_iu_func_slp_sl_thold_0_b : std_ulogic; +signal pc_iu_time_sl_thold_1 : std_ulogic; +signal pc_iu_time_sl_thold_0 : std_ulogic; +signal pc_iu_abst_sl_thold_1 : std_ulogic; +signal pc_iu_abst_sl_thold_0 : std_ulogic; +signal pc_iu_abst_sl_thold_0_b : std_ulogic; +signal pc_iu_abst_slp_sl_thold_1: std_ulogic; +signal pc_iu_abst_slp_sl_thold_0: std_ulogic; +signal pc_iu_repr_sl_thold_1 : std_ulogic; +signal pc_iu_repr_sl_thold_0 : std_ulogic; +signal pc_iu_ary_nsl_thold_1 : std_ulogic; +signal pc_iu_ary_nsl_thold_0 : std_ulogic; +signal pc_iu_ary_slp_nsl_thold_1: std_ulogic; +signal pc_iu_ary_slp_nsl_thold_0: std_ulogic; +signal pc_iu_regf_slp_sl_thold_1: std_ulogic; +signal pc_iu_regf_slp_sl_thold_0: std_ulogic; +signal regf_slat_slp_sl_thold_0_b: std_ulogic; +signal pc_iu_bolt_sl_thold_1 : std_ulogic; +signal pc_iu_bolt_sl_thold_0 : std_ulogic; +signal pc_iu_sg_1 : std_ulogic; +signal pc_iu_sg_0 : std_ulogic; +signal forcee : std_ulogic; +signal funcslp_force : std_ulogic; +signal abst_force : std_ulogic; +signal pc_iu_bo_enable_2 : std_ulogic; +signal ierat_func_scan_in : std_ulogic_vector(0 to 1); +signal sel_func_scan_in : std_ulogic; +signal dir_func_scan_in : std_ulogic_vector(0 to 1); +signal miss_func_scan_in : std_ulogic; +signal ierat_func_scan_out : std_ulogic_vector(0 to 1); +signal sel_func_scan_out : std_ulogic; +signal dir_func_scan_out : std_ulogic_vector(0 to 1); +signal miss_func_scan_out : std_ulogic; +signal siv : std_ulogic_vector(0 to scan_right); +signal sov : std_ulogic_vector(0 to scan_right); +signal tsiv : std_ulogic_vector(0 to 1); +signal tsov : std_ulogic_vector(0 to 1); +signal func_scan_in_cam : std_ulogic; +signal func_scan_out_cam : std_ulogic; +signal regf_scan_out_cam : std_ulogic_vector(0 to 4); +signal ac_ccfg_scan_out_int : std_ulogic; +signal event_bus_enable_d : std_ulogic; +signal event_bus_enable_q : std_ulogic; +signal trace_bus_enable_d : std_ulogic; +signal trace_bus_enable_q : std_ulogic; +signal debug_mux_ctrls_d : std_ulogic_vector(0 to 15); +signal debug_mux_ctrls_q : std_ulogic_vector(0 to 15); +signal tiup : std_ulogic; +signal act_dis : std_ulogic; +signal d_mode : std_ulogic; +signal mpw2_b : std_ulogic; +signal g6t_act_dis : std_ulogic; +signal cam_act_dis : std_ulogic; +begin +tiup <= '1'; +act_dis <= '0'; +d_mode <= '0'; +mpw2_b <= '1'; +g6t_act_dis <= '0'; +cam_act_dis <= '0'; +iuq_ic_ierat0 : entity work.iuq_ic_ierat +generic map(thdid_width => 4, + epn_width => epn_width, + rpn_width => rpn_width, + bcfg_epn_0to15 => bcfg_epn_0to15, + bcfg_epn_16to31 => bcfg_epn_16to31, + bcfg_epn_32to47 => bcfg_epn_32to47, + bcfg_epn_48to51 => bcfg_epn_48to51, + bcfg_rpn_22to31 => bcfg_rpn_22to31, + bcfg_rpn_32to47 => bcfg_rpn_32to47, + bcfg_rpn_48to51 => bcfg_rpn_48to51, + rs_data_width => rs_data_width, + data_out_width => data_out_width, + expand_type => expand_type) +port map( + gnd => gnd, + vdd => vdd, + vcs => vcs, + nclk => nclk, + pc_iu_init_reset => pc_iu_init_reset, + tc_ccflush_dc => tc_ac_ccflush_dc, + tc_scan_dis_dc_b => an_ac_scan_dis_dc_b, + tc_scan_diag_dc => an_ac_scan_diag_dc, + tc_lbist_en_dc => an_ac_lbist_en_dc, + an_ac_atpg_en_dc => an_ac_atpg_en_dc, + an_ac_grffence_en_dc => an_ac_grffence_en_dc, + + lcb_d_mode_dc => d_mode, + lcb_clkoff_dc_b => clkoff_b, + lcb_act_dis_dc => act_dis, + lcb_mpw1_dc_b => mpw1_b, + lcb_mpw2_dc_b => mpw2_b, + lcb_delay_lclkr_dc => delay_lclkr, + pc_iu_func_sl_thold_2 => pc_iu_func_sl_thold_2, + pc_iu_func_slp_sl_thold_2 => pc_iu_func_slp_sl_thold_2, + pc_iu_func_slp_nsl_thold_2 => pc_iu_func_slp_nsl_thold_2, + pc_iu_cfg_slp_sl_thold_2 => pc_iu_cfg_slp_sl_thold_2, + pc_iu_regf_slp_sl_thold_2 => pc_iu_regf_slp_sl_thold_2, + pc_iu_time_sl_thold_2 => pc_iu_time_sl_thold_2, + pc_iu_sg_2 => pc_iu_sg_2, + pc_iu_fce_2 => pc_iu_fce_2, + + cam_clkoff_b => cam_clkoff_b, + cam_act_dis => cam_act_dis, + cam_d_mode => cam_d_mode, + cam_delay_lclkr => cam_delay_lclkr, + cam_mpw1_b => cam_mpw1_b, + cam_mpw2_b => cam_mpw2_b, + ac_func_scan_in => ierat_func_scan_in, + ac_func_scan_out => ierat_func_scan_out, + ac_ccfg_scan_in => ac_ccfg_scan_in, + ac_ccfg_scan_out => ac_ccfg_scan_out_int, + func_scan_in_cam => func_scan_in_cam, + func_scan_out_cam => func_scan_out_cam, + time_scan_in => tsiv(0), + time_scan_out => tsov(0), + regf_scan_in => regf_scan_in, + regf_scan_out => regf_scan_out_cam, + iu_ierat_iu0_val => iu_ierat_iu0_val, + iu_ierat_iu0_thdid => iu_ierat_iu0_thdid, + iu_ierat_iu0_ifar => iu_ierat_iu0_ifar, + iu_ierat_iu0_flush => iu_ierat_iu0_flush, + iu_ierat_iu1_flush => iu_ierat_iu1_flush, + iu_ierat_iu1_back_inv => iu_ierat_iu1_back_inv, + iu_ierat_ium1_back_inv => iu_ierat_ium1_back_inv, + spr_ic_clockgate_dis => spr_ic_clockgate_dis(1), + ierat_iu_iu2_rpn => ierat_iu_iu2_rpn, + ierat_iu_iu2_wimge => ierat_iu_iu2_wimge, + ierat_iu_iu2_u => ierat_iu_iu2_u, + ierat_iu_iu2_error => ierat_iu_iu2_error, + ierat_iu_iu2_miss => ierat_iu_iu2_miss, + ierat_iu_iu2_multihit => ierat_iu_iu2_multihit, + ierat_iu_iu2_isi => ierat_iu_iu2_isi, + xu_iu_rf1_val => xu_iu_rf1_val, + xu_iu_rf1_is_eratre => xu_iu_rf1_is_eratre, + xu_iu_rf1_is_eratwe => xu_iu_rf1_is_eratwe, + xu_iu_rf1_is_eratsx => xu_iu_rf1_is_eratsx, + xu_iu_rf1_is_eratilx => xu_iu_rf1_is_eratilx, + xu_iu_ex1_is_isync => xu_iu_ex1_is_isync, + xu_iu_ex1_is_csync => xu_iu_ex1_is_csync, + xu_iu_rf1_ws => xu_iu_rf1_ws, + xu_iu_rf1_t => xu_iu_rf1_t, + xu_iu_ex1_rs_is => xu_iu_ex1_rs_is, + xu_iu_ex1_ra_entry => xu_iu_ex1_ra_entry, + xu_iu_ex1_rb => xu_iu_ex1_rb, + xu_iu_flush => xu_iu_flush, + xu_rf1_flush => xu_rf1_flush, + xu_ex1_flush => xu_ex1_flush, + xu_ex2_flush => xu_ex2_flush, + xu_ex3_flush => xu_ex3_flush, + xu_ex4_flush => xu_ex4_flush, + xu_ex5_flush => xu_ex5_flush, + xu_iu_ex4_rs_data => xu_iu_ex4_rs_data, + xu_iu_msr_hv => xu_iu_msr_hv, + xu_iu_msr_pr => xu_iu_msr_pr, + xu_iu_msr_is => xu_iu_msr_is, + xu_iu_msr_cm => xu_iu_msr_cm, + xu_iu_hid_mmu_mode => xu_iu_hid_mmu_mode, + xu_iu_spr_ccr2_ifrat => xu_iu_spr_ccr2_ifrat, + xu_iu_spr_ccr2_ifratsc => xu_iu_spr_ccr2_ifratsc, + xu_iu_xucr4_mmu_mchk => xu_iu_xucr4_mmu_mchk, + ierat_iu_hold_req => ierat_iu_hold_req, + ierat_iu_iu2_flush_req => ierat_iu_iu2_flush_req, + iu_xu_ex4_data => iu_xu_ex4_data, + iu_xu_ierat_ex3_par_err => iu_xu_ierat_ex3_par_err, + iu_xu_ierat_ex4_par_err => iu_xu_ierat_ex4_par_err, + iu_xu_ierat_ex2_flush_req => iu_xu_ierat_ex2_flush_req, + iu_mm_ierat_req => iu_mm_ierat_req, + iu_mm_ierat_thdid => iu_mm_ierat_thdid, + iu_mm_ierat_state => iu_mm_ierat_state, + iu_mm_ierat_tid => iu_mm_ierat_tid, + iu_mm_ierat_flush => iu_mm_ierat_flush, + mm_iu_ierat_rel_val => mm_iu_ierat_rel_val, + mm_iu_ierat_rel_data => mm_iu_ierat_rel_data, + mm_iu_ierat_pid0 => mm_iu_ierat_pid0, + mm_iu_ierat_pid1 => mm_iu_ierat_pid1, + mm_iu_ierat_pid2 => mm_iu_ierat_pid2, + mm_iu_ierat_pid3 => mm_iu_ierat_pid3, + mm_iu_ierat_mmucr0_0 => mm_iu_ierat_mmucr0_0, + mm_iu_ierat_mmucr0_1 => mm_iu_ierat_mmucr0_1, + mm_iu_ierat_mmucr0_2 => mm_iu_ierat_mmucr0_2, + mm_iu_ierat_mmucr0_3 => mm_iu_ierat_mmucr0_3, + iu_mm_ierat_mmucr0 => iu_mm_ierat_mmucr0, + iu_mm_ierat_mmucr0_we => iu_mm_ierat_mmucr0_we, + mm_iu_ierat_mmucr1 => mm_iu_ierat_mmucr1, + iu_mm_ierat_mmucr1 => iu_mm_ierat_mmucr1, + iu_mm_ierat_mmucr1_we => iu_mm_ierat_mmucr1_we, + mm_iu_ierat_snoop_coming => mm_iu_ierat_snoop_coming, + mm_iu_ierat_snoop_val => mm_iu_ierat_snoop_val, + mm_iu_ierat_snoop_attr => mm_iu_ierat_snoop_attr, + mm_iu_ierat_snoop_vpn => mm_iu_ierat_snoop_vpn, + iu_mm_ierat_snoop_ack => iu_mm_ierat_snoop_ack, + pc_iu_trace_bus_enable => pc_iu_trace_bus_enable, + ierat_iu_debug_group0 => ierat_iu_debug_group0, + ierat_iu_debug_group1 => ierat_iu_debug_group1, + ierat_iu_debug_group2 => ierat_iu_debug_group2, + ierat_iu_debug_group3 => ierat_iu_debug_group3 +); +iuq_ic_select0 : entity work.iuq_ic_select +generic map(expand_type => expand_type) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_iu_func_sl_thold_0_b => pc_iu_func_sl_thold_0_b, + pc_iu_func_slp_sl_thold_0_b => pc_iu_func_slp_sl_thold_0_b, + pc_iu_sg_0 => pc_iu_sg_0, + forcee => forcee, + funcslp_force => funcslp_force, + d_mode => d_mode, + delay_lclkr => delay_lclkr(0), + mpw1_b => mpw1_b(0), + mpw2_b => mpw2_b, + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b, + func_scan_in => sel_func_scan_in, + func_scan_out => sel_func_scan_out, + ac_an_power_managed => ac_an_power_managed, + xu_iu_run_thread => xu_iu_run_thread, + xu_iu_flush => xu_iu_flush, + xu_iu_iu0_flush_ifar0 => xu_iu_iu0_flush_ifar0, + xu_iu_iu0_flush_ifar1 => xu_iu_iu0_flush_ifar1, + xu_iu_iu0_flush_ifar2 => xu_iu_iu0_flush_ifar2, + xu_iu_iu0_flush_ifar3 => xu_iu_iu0_flush_ifar3, + xu_iu_flush_2ucode => xu_iu_flush_2ucode, + xu_iu_flush_2ucode_type => xu_iu_flush_2ucode_type, + xu_iu_msr_cm => xu_iu_msr_cm, + xu_iu_ex6_icbi_val => xu_iu_ex6_icbi_val, + xu_iu_ex6_icbi_addr => xu_iu_ex6_icbi_addr, + an_ac_back_inv => an_ac_back_inv, + an_ac_back_inv_addr => an_ac_back_inv_addr, + an_ac_back_inv_target => an_ac_back_inv_target, + an_ac_icbi_ack => an_ac_icbi_ack, + an_ac_icbi_ack_thread => an_ac_icbi_ack_thread, + spr_ic_clockgate_dis => spr_ic_clockgate_dis(0), + spr_ic_icbi_ack_en => spr_ic_icbi_ack_en, + spr_ic_idir_read => spr_ic_idir_read, + spr_ic_idir_row => spr_ic_idir_row, + spr_ic_pri_rand => spr_ic_pri_rand, + spr_ic_pri_rand_always => spr_ic_pri_rand_always, + spr_ic_pri_rand_flush => spr_ic_pri_rand_flush, + ic_perf_event_t0 => ic_perf_event_t0(2 to 3), + ic_perf_event_t1 => ic_perf_event_t1(2 to 3), + ic_perf_event_t2 => ic_perf_event_t2(2 to 3), + ic_perf_event_t3 => ic_perf_event_t3(2 to 3), + iu_ierat_iu0_val => iu_ierat_iu0_val, + iu_ierat_iu0_thdid => iu_ierat_iu0_thdid, + iu_ierat_iu0_ifar => iu_ierat_iu0_ifar, + iu_ierat_iu0_flush => iu_ierat_iu0_flush, + iu_ierat_iu1_flush => iu_ierat_iu1_flush, + iu_ierat_ium1_back_inv => iu_ierat_ium1_back_inv, + ierat_iu_hold_req => ierat_iu_hold_req, + ierat_iu_iu2_flush_req => ierat_iu_iu2_flush_req, + ierat_iu_iu2_miss => ierat_iu_iu2_miss, + icm_ics_iu0_preload_val => icm_ics_iu0_preload_val, + icm_ics_iu0_preload_tid => icm_ics_iu0_preload_tid, + icm_ics_iu0_preload_ifar => icm_ics_iu0_preload_ifar, + icm_ics_hold_thread => icm_ics_hold_thread, + icm_ics_hold_thread_dbg => icm_ics_hold_thread_dbg, + icm_ics_hold_iu0 => icm_ics_hold_iu0, + icm_ics_ecc_block_iu0 => icm_ics_ecc_block_iu0, + icm_ics_load_tid => icm_ics_load_tid, + icm_ics_iu1_ecc_flush => icm_ics_iu1_ecc_flush, + icm_ics_iu2_miss_match_prev=> icm_ics_iu2_miss_match_prev, + ics_icm_iu2_flush_tid => ics_icm_iu2_flush_tid, + ics_icm_iu3_flush_tid => ics_icm_iu3_flush_tid, + ics_icm_iu0_ifar0 => ics_icm_iu0_ifar0, + ics_icm_iu0_ifar1 => ics_icm_iu0_ifar1, + ics_icm_iu0_ifar2 => ics_icm_iu0_ifar2, + ics_icm_iu0_ifar3 => ics_icm_iu0_ifar3, + ics_icm_iu0_inval => ics_icm_iu0_inval, + ics_icm_iu0_inval_addr => ics_icm_iu0_inval_addr, + ics_icd_dir_rd_act => ics_icd_dir_rd_act, + ics_icd_data_rd_act => ics_icd_data_rd_act, + ics_icd_iu0_valid => ics_icd_iu0_valid, + ics_icd_iu0_tid => ics_icd_iu0_tid, + ics_icd_iu0_ifar => ics_icd_iu0_ifar, + ics_icd_iu0_inval => ics_icd_iu0_inval, + ics_icd_iu0_2ucode => ics_icd_iu0_2ucode, + ics_icd_iu0_2ucode_type => ics_icd_iu0_2ucode_type, + ics_icd_iu0_spr_idir_read => ics_icd_iu0_spr_idir_read, + icd_ics_iu1_valid => icd_ics_iu1_valid, + icd_ics_iu1_tid => icd_ics_iu1_tid, + icd_ics_iu1_ifar => icd_ics_iu1_ifar, + icd_ics_iu1_2ucode => icd_ics_iu1_2ucode, + icd_ics_iu1_2ucode_type => icd_ics_iu1_2ucode_type, + ics_icd_all_flush_prev => ics_icd_all_flush_prev, + ics_icd_iu1_flush_tid => ics_icd_iu1_flush_tid, + ics_icd_iu2_flush_tid => ics_icd_iu2_flush_tid, + icd_ics_iu2_miss_flush_prev=> icd_ics_iu2_miss_flush_prev, + icd_ics_iu2_ifar_eff => icd_ics_iu2_ifar_eff, + icd_ics_iu2_2ucode => icd_ics_iu2_2ucode, + icd_ics_iu2_2ucode_type => icd_ics_iu2_2ucode_type, + icd_ics_iu3_parity_flush => icd_ics_iu3_parity_flush, + icd_ics_iu3_ifar => icd_ics_iu3_ifar, + icd_ics_iu3_2ucode => icd_ics_iu3_2ucode, + icd_ics_iu3_2ucode_type => icd_ics_iu3_2ucode_type, + ic_bp_iu1_val => ic_bp_iu1_val, + ic_bp_iu1_tid => ic_bp_iu1_tid, + ic_bp_iu1_ifar => ic_bp_iu1_ifar, + bp_ib_iu4_ifar => bp_ib_iu4_ifar, + bp_ic_iu5_hold_tid => bp_ic_iu5_hold_tid, + bp_ic_iu5_redirect_tid => bp_ic_iu5_redirect_tid, + bp_ic_iu5_redirect_ifar => bp_ic_iu5_redirect_ifar, + ib_ic_empty => ib_ic_empty, + ib_ic_below_water => ib_ic_below_water, + ib_ic_iu5_redirect_tid => ib_ic_iu5_redirect_tid, + ic_fdep_icbi_ack => ic_fdep_icbi_ack, + uc_flush_tid => uc_flush_tid, + uc_ic_hold_thread => uc_ic_hold_thread, + event_bus_enable => event_bus_enable_q, + sel_dbg_data => sel_dbg_data +); +iuq_ic_dir0 : entity work.iuq_ic_dir +generic map(expand_type => expand_type) +port map( + vcs => vcs, + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_iu_func_sl_thold_0_b => pc_iu_func_sl_thold_0_b, + pc_iu_func_slp_sl_thold_0_b => pc_iu_func_slp_sl_thold_0_b, + pc_iu_time_sl_thold_0 => pc_iu_time_sl_thold_0, + pc_iu_repr_sl_thold_0 => pc_iu_repr_sl_thold_0, + pc_iu_abst_sl_thold_0 => pc_iu_abst_sl_thold_0, + pc_iu_abst_sl_thold_0_b => pc_iu_abst_sl_thold_0_b, + pc_iu_abst_slp_sl_thold_0 => pc_iu_abst_slp_sl_thold_0, + pc_iu_ary_nsl_thold_0 => pc_iu_ary_nsl_thold_0, + pc_iu_ary_slp_nsl_thold_0 => pc_iu_ary_slp_nsl_thold_0, + pc_iu_bolt_sl_thold_0 => pc_iu_bolt_sl_thold_0, + pc_iu_sg_0 => pc_iu_sg_0, + pc_iu_sg_1 => pc_iu_sg_1, + forcee => forcee, + funcslp_force => funcslp_force, + abst_force => abst_force, + d_mode => d_mode, + delay_lclkr => delay_lclkr(0), + mpw1_b => mpw1_b(0), + mpw2_b => mpw2_b, + clkoff_b => clkoff_b, + act_dis => act_dis, + g8t_clkoff_b => g8t_clkoff_b, + g8t_d_mode => g8t_d_mode, + g8t_delay_lclkr => g8t_delay_lclkr, + g8t_mpw1_b => g8t_mpw1_b, + g8t_mpw2_b => g8t_mpw2_b, + g6t_clkoff_b => g6t_clkoff_b, + g6t_act_dis => g6t_act_dis, + g6t_d_mode => g6t_d_mode, + g6t_delay_lclkr => g6t_delay_lclkr, + g6t_mpw1_b => g6t_mpw1_b, + g6t_mpw2_b => g6t_mpw2_b, + tc_ac_ccflush_dc => tc_ac_ccflush_dc, + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b, + an_ac_scan_diag_dc => an_ac_scan_diag_dc, + func_scan_in => dir_func_scan_in, + time_scan_in => tsiv(1), + repr_scan_in => repr_scan_in, + abst_scan_in => abst_scan_in, + func_scan_out => dir_func_scan_out, + time_scan_out => tsov(1), + repr_scan_out => repr_scan_out, + abst_scan_out => abst_scan_out, + spr_ic_cls => spr_ic_cls, + spr_ic_clockgate_dis => spr_ic_clockgate_dis(0), + spr_ic_idir_way => spr_ic_idir_way, + ic_spr_idir_done => ic_spr_idir_done, + ic_spr_idir_lru => ic_spr_idir_lru, + ic_spr_idir_parity => ic_spr_idir_parity, + ic_spr_idir_endian => ic_spr_idir_endian, + ic_spr_idir_valid => ic_spr_idir_valid, + ic_spr_idir_tag => ic_spr_idir_tag, + ic_perf_event_t0 => ic_perf_event_t0(4 to 6), + ic_perf_event_t1 => ic_perf_event_t1(4 to 6), + ic_perf_event_t2 => ic_perf_event_t2(4 to 6), + ic_perf_event_t3 => ic_perf_event_t3(4 to 6), + ic_perf_event => ic_perf_event, + iu_pc_err_icache_parity => iu_pc_err_icache_parity, + iu_pc_err_icachedir_parity => iu_pc_err_icachedir_parity, + iu_pc_err_icachedir_multihit => iu_pc_err_icachedir_multihit, + pc_iu_inj_icache_parity => pc_iu_inj_icache_parity, + pc_iu_inj_icachedir_parity => pc_iu_inj_icachedir_parity, + pc_iu_inj_icachedir_multihit => pc_iu_inj_icachedir_multihit, + pc_iu_abist_g8t_wenb => pc_iu_abist_g8t_wenb, + pc_iu_abist_g8t1p_renb_0 => pc_iu_abist_g8t1p_renb_0, + pc_iu_abist_di_0 => pc_iu_abist_di_0, + pc_iu_abist_g8t_bw_1 => pc_iu_abist_g8t_bw_1, + pc_iu_abist_g8t_bw_0 => pc_iu_abist_g8t_bw_0, + pc_iu_abist_waddr_0 => pc_iu_abist_waddr_0, + pc_iu_abist_raddr_0 => pc_iu_abist_raddr_0, + pc_iu_abist_ena_dc => pc_iu_abist_ena_dc, + pc_iu_abist_wl64_comp_ena => pc_iu_abist_wl64_comp_ena, + pc_iu_abist_raw_dc_b => pc_iu_abist_raw_dc_b, + pc_iu_abist_g8t_dcomp => pc_iu_abist_g8t_dcomp, + pc_iu_abist_g6t_bw => pc_iu_abist_g6t_bw, + pc_iu_abist_di_g6t_2r => pc_iu_abist_di_g6t_2r, + pc_iu_abist_wl256_comp_ena => pc_iu_abist_wl256_comp_ena, + pc_iu_abist_dcomp_g6t_2r => pc_iu_abist_dcomp_g6t_2r, + pc_iu_abist_g6t_r_wb => pc_iu_abist_g6t_r_wb, + an_ac_lbist_ary_wrt_thru_dc=> an_ac_lbist_ary_wrt_thru_dc, + pc_iu_bo_enable_2 => pc_iu_bo_enable_2, + pc_iu_bo_reset => pc_iu_bo_reset, + pc_iu_bo_unload => pc_iu_bo_unload, + pc_iu_bo_repair => pc_iu_bo_repair, + pc_iu_bo_shdata => pc_iu_bo_shdata, + pc_iu_bo_select => pc_iu_bo_select, + iu_pc_bo_fail => iu_pc_bo_fail, + iu_pc_bo_diagout => iu_pc_bo_diagout, + xu_iu_ici => xu_iu_ici, + iu_mm_ierat_epn => iu_mm_ierat_epn, + iu_ierat_iu1_back_inv => iu_ierat_iu1_back_inv, + ierat_iu_iu2_rpn => ierat_iu_iu2_rpn, + ierat_iu_iu2_wimge => ierat_iu_iu2_wimge, + ierat_iu_iu2_u => ierat_iu_iu2_u, + ierat_iu_iu2_error => ierat_iu_iu2_error, + ierat_iu_iu2_miss => ierat_iu_iu2_miss, + ierat_iu_iu2_multihit => ierat_iu_iu2_multihit, + ierat_iu_iu2_isi => ierat_iu_iu2_isi, + ics_icd_dir_rd_act => ics_icd_dir_rd_act, + ics_icd_data_rd_act => ics_icd_data_rd_act, + ics_icd_iu0_valid => ics_icd_iu0_valid, + ics_icd_iu0_tid => ics_icd_iu0_tid, + ics_icd_iu0_ifar => ics_icd_iu0_ifar, + ics_icd_iu0_inval => ics_icd_iu0_inval, + ics_icd_iu0_2ucode => ics_icd_iu0_2ucode, + ics_icd_iu0_2ucode_type => ics_icd_iu0_2ucode_type, + ics_icd_iu0_spr_idir_read => ics_icd_iu0_spr_idir_read, + icd_ics_iu1_valid => icd_ics_iu1_valid, + icd_ics_iu1_tid => icd_ics_iu1_tid, + icd_ics_iu1_ifar => icd_ics_iu1_ifar, + icd_ics_iu1_2ucode => icd_ics_iu1_2ucode, + icd_ics_iu1_2ucode_type => icd_ics_iu1_2ucode_type, + ics_icd_all_flush_prev => ics_icd_all_flush_prev, + ics_icd_iu1_flush_tid => ics_icd_iu1_flush_tid, + ics_icd_iu2_flush_tid => ics_icd_iu2_flush_tid, + icd_ics_iu2_miss_flush_prev=> icd_ics_iu2_miss_flush_prev, + icd_ics_iu2_ifar_eff => icd_ics_iu2_ifar_eff, + icd_ics_iu2_2ucode => icd_ics_iu2_2ucode, + icd_ics_iu2_2ucode_type => icd_ics_iu2_2ucode_type, + icd_ics_iu3_parity_flush => icd_ics_iu3_parity_flush, + icd_ics_iu3_ifar => icd_ics_iu3_ifar, + icd_ics_iu3_2ucode => icd_ics_iu3_2ucode, + icd_ics_iu3_2ucode_type => icd_ics_iu3_2ucode_type, + icm_icd_lru_addr => icm_icd_lru_addr, + icm_icd_dir_inval => icm_icd_dir_inval, + icm_icd_dir_val => icm_icd_dir_val, + icm_icd_data_write => icm_icd_data_write, + icm_icd_reload_addr => icm_icd_reload_addr, + icm_icd_reload_data => icm_icd_reload_data, + icm_icd_reload_way => icm_icd_reload_way, + icm_icd_load_tid => icm_icd_load_tid, + icm_icd_load_addr => icm_icd_load_addr, + icm_icd_load_2ucode => icm_icd_load_2ucode, + icm_icd_load_2ucode_type => icm_icd_load_2ucode_type, + icm_icd_dir_write => icm_icd_dir_write, + icm_icd_dir_write_addr => icm_icd_dir_write_addr, + icm_icd_dir_write_endian => icm_icd_dir_write_endian, + icm_icd_dir_write_way => icm_icd_dir_write_way, + icm_icd_lru_write => icm_icd_lru_write, + icm_icd_lru_write_addr => icm_icd_lru_write_addr, + icm_icd_lru_write_way => icm_icd_lru_write_way, + icm_icd_ecc_inval => icm_icd_ecc_inval, + icm_icd_ecc_addr => icm_icd_ecc_addr, + icm_icd_ecc_way => icm_icd_ecc_way, + icm_icd_iu3_ecc_fp_cancel => icm_icd_iu3_ecc_fp_cancel, + icm_icd_iu3_ecc_err => icm_icd_iu3_ecc_err, + icm_icd_any_reld_r2 => icm_icd_any_reld_r2, + icm_icd_any_checkecc => icm_icd_any_checkecc, + icd_icm_miss => icd_icm_miss, + icd_icm_tid => icd_icm_tid, + icd_icm_addr_real => icd_icm_addr_real, + icd_icm_addr_eff => icd_icm_addr_eff, + icd_icm_wimge => icd_icm_wimge, + icd_icm_userdef => icd_icm_userdef, + icd_icm_2ucode => icd_icm_2ucode, + icd_icm_2ucode_type => icd_icm_2ucode_type, + icd_icm_iu3_erat_err => icd_icm_iu3_erat_err, + icd_icm_iu2_inval => icd_icm_iu2_inval, + icd_icm_ici => icd_icm_ici, + icd_icm_any_iu2_valid => icd_icm_any_iu2_valid, + icd_icm_row_lru => icd_icm_row_lru, + icd_icm_row_val => icd_icm_row_val, + ic_bp_iu3_val => int_ic_bp_iu3_val, + ic_bp_iu3_tid => ic_bp_iu3_tid, + ic_bp_iu3_ifar => ic_bp_iu3_ifar, + ic_bp_iu3_2ucode => ic_bp_iu3_2ucode, + ic_bp_iu3_2ucode_type => ic_bp_iu3_2ucode_type, + ic_bp_iu3_error => ic_bp_iu3_error, + ic_bp_iu3_flush => ic_bp_iu3_flush, + ic_bp_iu3_0_instr => int_ic_bp_iu3_0_instr, + ic_bp_iu3_1_instr => int_ic_bp_iu3_1_instr, + ic_bp_iu3_2_instr => int_ic_bp_iu3_2_instr, + ic_bp_iu3_3_instr => int_ic_bp_iu3_3_instr, + event_bus_enable => event_bus_enable_q, + trace_bus_enable => trace_bus_enable_q, + dir_dbg_data0 => dir_dbg_data0, + dir_dbg_data1 => dir_dbg_data1, + dir_dbg_data2 => dir_dbg_data2, + dir_dbg_trigger0 => dir_dbg_trigger0, + dir_dbg_trigger1 => dir_dbg_trigger1 +); +ic_bp_iu3_val <= int_ic_bp_iu3_val; +ic_bp_iu3_0_instr <= int_ic_bp_iu3_0_instr; +ic_bp_iu3_1_instr <= int_ic_bp_iu3_1_instr; +ic_bp_iu3_2_instr <= int_ic_bp_iu3_2_instr; +ic_bp_iu3_3_instr <= int_ic_bp_iu3_3_instr; +iuq_ic_miss0 : entity work.iuq_ic_miss +generic map(expand_type => expand_type) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_iu_func_sl_thold_0_b => pc_iu_func_sl_thold_0_b, + pc_iu_sg_0 => pc_iu_sg_0, + forcee => forcee, + d_mode => d_mode, + delay_lclkr => delay_lclkr(0), + mpw1_b => mpw1_b(0), + mpw2_b => mpw2_b, + scan_in => miss_func_scan_in, + scan_out => miss_func_scan_out, + xu_iu_flush => xu_iu_flush, + bp_ic_iu5_redirect_tid => bp_ic_iu5_redirect_tid, + ics_icm_iu0_ifar0 => ics_icm_iu0_ifar0, + ics_icm_iu0_ifar1 => ics_icm_iu0_ifar1, + ics_icm_iu0_ifar2 => ics_icm_iu0_ifar2, + ics_icm_iu0_ifar3 => ics_icm_iu0_ifar3, + ics_icm_iu0_inval => ics_icm_iu0_inval, + ics_icm_iu0_inval_addr => ics_icm_iu0_inval_addr, + ics_icm_iu2_flush_tid => ics_icm_iu2_flush_tid, + ics_icm_iu3_flush_tid => ics_icm_iu3_flush_tid, + icm_ics_hold_thread => icm_ics_hold_thread, + icm_ics_hold_thread_dbg => icm_ics_hold_thread_dbg, + icm_ics_hold_iu0 => icm_ics_hold_iu0, + icm_ics_ecc_block_iu0 => icm_ics_ecc_block_iu0, + icm_ics_load_tid => icm_ics_load_tid, + icm_ics_iu1_ecc_flush => icm_ics_iu1_ecc_flush, + icm_ics_iu2_miss_match_prev => icm_ics_iu2_miss_match_prev, + icm_ics_iu0_preload_val => icm_ics_iu0_preload_val, + icm_ics_iu0_preload_tid => icm_ics_iu0_preload_tid, + icm_ics_iu0_preload_ifar => icm_ics_iu0_preload_ifar, + icm_icd_lru_addr => icm_icd_lru_addr, + icm_icd_dir_inval => icm_icd_dir_inval, + icm_icd_dir_val => icm_icd_dir_val, + icm_icd_data_write => icm_icd_data_write, + icm_icd_reload_addr => icm_icd_reload_addr, + icm_icd_reload_data => icm_icd_reload_data, + icm_icd_reload_way => icm_icd_reload_way, + icm_icd_load_tid => icm_icd_load_tid, + icm_icd_load_addr => icm_icd_load_addr, + icm_icd_load_2ucode => icm_icd_load_2ucode, + icm_icd_load_2ucode_type => icm_icd_load_2ucode_type, + icm_icd_dir_write => icm_icd_dir_write, + icm_icd_dir_write_addr => icm_icd_dir_write_addr, + icm_icd_dir_write_endian => icm_icd_dir_write_endian, + icm_icd_dir_write_way => icm_icd_dir_write_way, + icm_icd_lru_write => icm_icd_lru_write, + icm_icd_lru_write_addr => icm_icd_lru_write_addr, + icm_icd_lru_write_way => icm_icd_lru_write_way, + icm_icd_ecc_inval => icm_icd_ecc_inval, + icm_icd_ecc_addr => icm_icd_ecc_addr, + icm_icd_ecc_way => icm_icd_ecc_way, + icm_icd_iu3_ecc_fp_cancel => icm_icd_iu3_ecc_fp_cancel, + icm_icd_iu3_ecc_err => icm_icd_iu3_ecc_err, + icm_icd_any_reld_r2 => icm_icd_any_reld_r2, + icm_icd_any_checkecc => icm_icd_any_checkecc, + icd_icm_miss => icd_icm_miss, + icd_icm_tid => icd_icm_tid, + icd_icm_addr_real => icd_icm_addr_real, + icd_icm_addr_eff => icd_icm_addr_eff, + icd_icm_wimge => icd_icm_wimge, + icd_icm_userdef => icd_icm_userdef, + icd_icm_2ucode => icd_icm_2ucode, + icd_icm_2ucode_type => icd_icm_2ucode_type, + icd_icm_iu3_erat_err => icd_icm_iu3_erat_err, + icd_icm_iu2_inval => icd_icm_iu2_inval, + icd_icm_ici => icd_icm_ici, + icd_icm_any_iu2_valid => icd_icm_any_iu2_valid, + icd_icm_row_lru => icd_icm_row_lru, + icd_icm_row_val => icd_icm_row_val, + ic_fdep_load_quiesce => ic_fdep_load_quiesce, + iu_mm_lmq_empty => iu_mm_lmq_empty, + ic_perf_event_t0 => ic_perf_event_t0(0 to 1), + ic_perf_event_t1 => ic_perf_event_t1(0 to 1), + ic_perf_event_t2 => ic_perf_event_t2(0 to 1), + ic_perf_event_t3 => ic_perf_event_t3(0 to 1), + an_ac_reld_data_vld => an_ac_reld_data_vld, + an_ac_reld_core_tag => an_ac_reld_core_tag, + an_ac_reld_qw => an_ac_reld_qw, + an_ac_reld_data => an_ac_reld_data, + an_ac_reld_ecc_err => an_ac_reld_ecc_err, + an_ac_reld_ecc_err_ue => an_ac_reld_ecc_err_ue, + spr_ic_bp_config => spr_ic_bp_config, + spr_ic_cls => spr_ic_cls, + spr_ic_clockgate_dis => spr_ic_clockgate_dis(0), + iu_xu_request => iu_xu_request, + iu_xu_thread => iu_xu_thread, + iu_xu_ra => iu_xu_ra, + iu_xu_wimge => iu_xu_wimge, + iu_xu_userdef => iu_xu_userdef, + event_bus_enable => event_bus_enable_q, + trace_bus_enable => trace_bus_enable_q, + miss_dbg_data0 => miss_dbg_data0, + miss_dbg_data1 => miss_dbg_data1, + miss_dbg_data2 => miss_dbg_data2, + miss_dbg_trigger => miss_dbg_trigger +); +------------------------------------------------- +-- Debug +------------------------------------------------- +iu3_dbg_data(0 to 21) <= int_ic_bp_iu3_val(0) & int_ic_bp_iu3_0_instr(0 to 5) & int_ic_bp_iu3_0_instr(21 to 31) & int_ic_bp_iu3_0_instr(32 to 35); +iu3_dbg_data(22 to 43) <= int_ic_bp_iu3_val(1) & int_ic_bp_iu3_1_instr(0 to 5) & int_ic_bp_iu3_1_instr(21 to 31) & int_ic_bp_iu3_1_instr(32 to 35); +iu3_dbg_data(44 to 65) <= int_ic_bp_iu3_val(2) & int_ic_bp_iu3_2_instr(0 to 5) & int_ic_bp_iu3_2_instr(21 to 31) & int_ic_bp_iu3_2_instr(32 to 35); +iu3_dbg_data(66 to 87) <= int_ic_bp_iu3_val(3) & int_ic_bp_iu3_3_instr(0 to 5) & int_ic_bp_iu3_3_instr(21 to 31) & int_ic_bp_iu3_3_instr(32 to 35); +dbg_group0 <= sel_dbg_data; +dbg_group1 <= dir_dbg_data0; +dbg_group2 <= dir_dbg_data1; +dbg_group3 <= dir_dbg_data2 & miss_dbg_data2; +dbg_group4 <= miss_dbg_data0; +dbg_group5 <= miss_dbg_data1; +dbg_group6 <= iu3_dbg_data; +dbg_group7 <= uc_dbg_data; +dbg_group8 <= ierat_iu_debug_group0; +dbg_group9 <= ierat_iu_debug_group1; +dbg_group10 <= ierat_iu_debug_group2; +dbg_group11 <= ierat_iu_debug_group3; +dbg_group12 <= (others => '0'); +dbg_group13 <= (others => '0'); +dbg_group14 <= (others => '0'); +dbg_group15 <= (others => '0'); +trg_group0 <= sel_dbg_data(65 to 66) & + dir_dbg_trigger0 & + miss_dbg_trigger(10) & miss_dbg_trigger(7); +trg_group1 <= dir_dbg_trigger1; +trg_group2 <= miss_dbg_trigger; +trg_group3 <= (others => '0'); +dbg_mux0: entity clib.c_debug_mux16 + port map( + vd => vdd, + gd => gnd, + + select_bits => debug_mux_ctrls_q, + trace_data_in => debug_data_in, + trigger_data_in => trace_triggers_in, + + dbg_group0 => dbg_group0, + dbg_group1 => dbg_group1, + dbg_group2 => dbg_group2, + dbg_group3 => dbg_group3, + dbg_group4 => dbg_group4, + dbg_group5 => dbg_group5, + dbg_group6 => dbg_group6, + dbg_group7 => dbg_group7, + dbg_group8 => dbg_group8, + dbg_group9 => dbg_group9, + dbg_group10 => dbg_group10, + dbg_group11 => dbg_group11, + dbg_group12 => dbg_group12, + dbg_group13 => dbg_group13, + dbg_group14 => dbg_group14, + dbg_group15 => dbg_group15, + + trg_group0 => trg_group0, + trg_group1 => trg_group1, + trg_group2 => trg_group2, + trg_group3 => trg_group3, + + trace_data_out => trace_data_out_d, + trigger_data_out=> trigger_data_out_d +); +trace_triggers_out <= trigger_data_out_q; +debug_data_out <= trace_data_out_q; +----------------------------------------------------------------------- +-- Debug & Performance Latches +----------------------------------------------------------------------- +event_bus_enable_d <= pc_iu_event_bus_enable; +trace_bus_enable_d <= pc_iu_trace_bus_enable; +debug_mux_ctrls_d <= pc_iu_debug_mux_ctrls; +event_bus_enable_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr(0), + mpw1_b => mpw1_b(0), + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(event_bus_enable_offset), + scout => sov(event_bus_enable_offset), + din => event_bus_enable_d, + dout => event_bus_enable_q); +trace_enable_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr(0), + mpw1_b => mpw1_b(0), + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(trace_bus_enable_offset), + scout => sov(trace_bus_enable_offset), + din => trace_bus_enable_d, + dout => trace_bus_enable_q); +debug_mux_ctrls_reg: tri_rlmreg_p + generic map (width => debug_mux_ctrls_q'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => trace_bus_enable_q, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr(0), + mpw1_b => mpw1_b(0), + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(debug_mux_ctrls_offset to debug_mux_ctrls_offset + debug_mux_ctrls_q'length-1), + scout => sov(debug_mux_ctrls_offset to debug_mux_ctrls_offset + debug_mux_ctrls_q'length-1), + din => debug_mux_ctrls_d, + dout => debug_mux_ctrls_q); +dbg_trigger_data_reg: tri_rlmreg_p + generic map (width => trigger_data_out_q'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => trace_bus_enable_q, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr(0), + mpw1_b => mpw1_b(0), + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(trigger_data_out_offset to trigger_data_out_offset + trigger_data_out_q'length-1), + scout => sov(trigger_data_out_offset to trigger_data_out_offset + trigger_data_out_q'length-1), + din => trigger_data_out_d, + dout => trigger_data_out_q); +dbg_trace_data_reg: tri_rlmreg_p + generic map (width => trace_data_out_q'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => trace_bus_enable_q, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr(0), + mpw1_b => mpw1_b(0), + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(trace_data_out_offset to trace_data_out_offset + trace_data_out_q'length-1), + scout => sov(trace_data_out_offset to trace_data_out_offset + trace_data_out_q'length-1), + din => trace_data_out_d, + dout => trace_data_out_q); +------------------------------------------------- +-- pervasive +------------------------------------------------- +perv_3to2_reg: tri_plat + generic map (width => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_iu_bo_enable_3, + q(0) => pc_iu_bo_enable_2); +perv_2to1_reg: tri_plat + generic map (width => 11, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_iu_func_sl_thold_2, + din(1) => pc_iu_func_slp_sl_thold_2, + din(2) => pc_iu_time_sl_thold_2, + din(3) => pc_iu_repr_sl_thold_2, + din(4) => pc_iu_abst_sl_thold_2, + din(5) => pc_iu_abst_slp_sl_thold_2, + din(6) => pc_iu_ary_nsl_thold_2, + din(7) => pc_iu_ary_slp_nsl_thold_2, + din(8) => pc_iu_regf_slp_sl_thold_2, + din(9) => pc_iu_bolt_sl_thold_2, + din(10) => pc_iu_sg_2, + q(0) => pc_iu_func_sl_thold_1, + q(1) => pc_iu_func_slp_sl_thold_1, + q(2) => pc_iu_time_sl_thold_1, + q(3) => pc_iu_repr_sl_thold_1, + q(4) => pc_iu_abst_sl_thold_1, + q(5) => pc_iu_abst_slp_sl_thold_1, + q(6) => pc_iu_ary_nsl_thold_1, + q(7) => pc_iu_ary_slp_nsl_thold_1, + q(8) => pc_iu_regf_slp_sl_thold_1, + q(9) => pc_iu_bolt_sl_thold_1, + q(10) => pc_iu_sg_1); +perv_1to0_reg: tri_plat + generic map (width => 11, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_iu_func_sl_thold_1, + din(1) => pc_iu_func_slp_sl_thold_1, + din(2) => pc_iu_time_sl_thold_1, + din(3) => pc_iu_repr_sl_thold_1, + din(4) => pc_iu_abst_sl_thold_1, + din(5) => pc_iu_abst_slp_sl_thold_1, + din(6) => pc_iu_ary_nsl_thold_1, + din(7) => pc_iu_ary_slp_nsl_thold_1, + din(8) => pc_iu_regf_slp_sl_thold_1, + din(9) => pc_iu_bolt_sl_thold_1, + din(10) => pc_iu_sg_1, + q(0) => pc_iu_func_sl_thold_0, + q(1) => pc_iu_func_slp_sl_thold_0, + q(2) => pc_iu_time_sl_thold_0, + q(3) => pc_iu_repr_sl_thold_0, + q(4) => pc_iu_abst_sl_thold_0, + q(5) => pc_iu_abst_slp_sl_thold_0, + q(6) => pc_iu_ary_nsl_thold_0, + q(7) => pc_iu_ary_slp_nsl_thold_0, + q(8) => pc_iu_regf_slp_sl_thold_0, + q(9) => pc_iu_bolt_sl_thold_0, + q(10) => pc_iu_sg_0); +perv_lcbor: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_b, + thold => pc_iu_func_sl_thold_0, + sg => pc_iu_sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => pc_iu_func_sl_thold_0_b); +func_slp_lcbor: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_b, + thold => pc_iu_func_slp_sl_thold_0, + sg => pc_iu_sg_0, + act_dis => act_dis, + forcee => funcslp_force, + thold_b => pc_iu_func_slp_sl_thold_0_b); +abst_lcbor: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_b, + thold => pc_iu_abst_sl_thold_0, + sg => pc_iu_sg_0, + act_dis => act_dis, + forcee => abst_force, + thold_b => pc_iu_abst_sl_thold_0_b); +----------------------------------------------------------------------- +-- Scan +----------------------------------------------------------------------- +ierat_func_scan_in(0) <= func_scan_in(0); +func_scan_out(0) <= ierat_func_scan_out(0) and an_ac_scan_dis_dc_b; +siv(0 to scan_right) <= sov(1 to scan_right) & func_scan_in(1); +func_scan_in_cam <= sov(0); +sel_func_scan_in <= func_scan_out_cam; +func_scan_out(1) <= sel_func_scan_out and an_ac_scan_dis_dc_b; +dir_func_scan_in(1) <= func_scan_in(2); +func_scan_out(2) <= dir_func_scan_out(1) and an_ac_scan_dis_dc_b; +miss_func_scan_in <= func_scan_in(3); +ierat_func_scan_in(1) <= miss_func_scan_out; +func_scan_out(3) <= ierat_func_scan_out(1) and an_ac_scan_dis_dc_b; +dir_func_scan_in(0) <= func_scan_in(4); +func_scan_out(4) <= dir_func_scan_out(0) and an_ac_scan_dis_dc_b; +ac_ccfg_scan_out <= ac_ccfg_scan_out_int and an_ac_scan_dis_dc_b; +tsiv <= time_scan_in & tsov(0); +time_scan_out <= tsov(1) and an_ac_scan_dis_dc_b; +regf_slat_slp_sl_thold_0_b <= not pc_iu_regf_slp_sl_thold_0; +regf_scan_latch: entity tri.tri_regs + generic map (width => 5, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + forcee => pc_iu_sg_0, + thold_b => regf_slat_slp_sl_thold_0_b, + delay_lclkr => delay_lclkr(0), + scin => regf_scan_out_cam, + scout => regf_scan_out, + dout => open ); +end iuq_ic; diff --git a/rel/src/vhdl/work/iuq_ic_dir.vhdl b/rel/src/vhdl/work/iuq_ic_dir.vhdl new file mode 100644 index 0000000..a05a68f --- /dev/null +++ b/rel/src/vhdl/work/iuq_ic_dir.vhdl @@ -0,0 +1,6959 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +--******************************************************************** +--* +--* TITLE: Instruction Cache Directory +--* +--* NAME: iuq_ic_dir.vhdl +--* +--********************************************************************* +library ieee,ibm,support,tri,work; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ibm.std_ulogic_unsigned.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use support.power_logic_pkg.all; +use tri.tri_latches_pkg.all; +use work.iuq_pkg.all; + +entity iuq_ic_dir is +generic(expand_type : integer := 2); +port( + vcs : inout power_logic; + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + pc_iu_func_sl_thold_0_b : in std_ulogic; + pc_iu_func_slp_sl_thold_0_b: in std_ulogic; + pc_iu_time_sl_thold_0 : in std_ulogic; + pc_iu_repr_sl_thold_0 : in std_ulogic; + pc_iu_abst_sl_thold_0 : in std_ulogic; + pc_iu_abst_sl_thold_0_b : in std_ulogic; + pc_iu_abst_slp_sl_thold_0 : in std_ulogic; + pc_iu_ary_nsl_thold_0 : in std_ulogic; + pc_iu_ary_slp_nsl_thold_0 : in std_ulogic; + pc_iu_bolt_sl_thold_0 : in std_ulogic; + pc_iu_sg_0 : in std_ulogic; + pc_iu_sg_1 : in std_ulogic; + forcee : in std_ulogic; + funcslp_force : in std_ulogic; + abst_force : in std_ulogic; + + d_mode : in std_ulogic; + delay_lclkr : in std_ulogic; + mpw1_b : in std_ulogic; + mpw2_b : in std_ulogic; + clkoff_b : in std_ulogic; + act_dis : in std_ulogic; + + g8t_clkoff_b : in std_ulogic; + g8t_d_mode : in std_ulogic; + g8t_delay_lclkr : in std_ulogic_vector(0 to 4); + g8t_mpw1_b : in std_ulogic_vector(0 to 4); + g8t_mpw2_b : in std_ulogic; + + g6t_clkoff_b : in std_ulogic; + g6t_act_dis : in std_ulogic; + g6t_d_mode : in std_ulogic; + g6t_delay_lclkr : in std_ulogic_vector(0 to 3); + g6t_mpw1_b : in std_ulogic_vector(0 to 4); + g6t_mpw2_b : in std_ulogic; + + tc_ac_ccflush_dc : in std_ulogic; + an_ac_scan_dis_dc_b : in std_ulogic; + an_ac_scan_diag_dc : in std_ulogic; + func_scan_in : in std_ulogic_vector(0 to 1); + time_scan_in : in std_ulogic; + repr_scan_in : in std_ulogic; + abst_scan_in : in std_ulogic_vector(0 to 2); + func_scan_out : out std_ulogic_vector(0 to 1); + time_scan_out : out std_ulogic; + repr_scan_out : out std_ulogic; + abst_scan_out : out std_ulogic_vector(0 to 2); + + spr_ic_cls : in std_ulogic; + spr_ic_clockgate_dis : in std_ulogic; + + spr_ic_idir_way : in std_ulogic_vector(0 to 1); + ic_spr_idir_done : out std_ulogic; + ic_spr_idir_lru : out std_ulogic_vector(0 to 2); + ic_spr_idir_parity : out std_ulogic_vector(0 to 3); + ic_spr_idir_endian : out std_ulogic; + ic_spr_idir_valid : out std_ulogic; + ic_spr_idir_tag : out std_ulogic_vector(0 to 29); + + ic_perf_event_t0 : out std_ulogic_vector(4 to 6); + ic_perf_event_t1 : out std_ulogic_vector(4 to 6); + ic_perf_event_t2 : out std_ulogic_vector(4 to 6); + ic_perf_event_t3 : out std_ulogic_vector(4 to 6); + ic_perf_event : out std_ulogic_vector(0 to 1); + + iu_pc_err_icache_parity : out std_ulogic; + iu_pc_err_icachedir_parity : out std_ulogic; + iu_pc_err_icachedir_multihit : out std_ulogic; + + pc_iu_inj_icache_parity : in std_ulogic; + pc_iu_inj_icachedir_parity : in std_ulogic; + pc_iu_inj_icachedir_multihit : in std_ulogic; + + pc_iu_abist_g8t_wenb : in std_ulogic; + pc_iu_abist_g8t1p_renb_0 : in std_ulogic; + pc_iu_abist_di_0 : in std_ulogic_vector(0 to 3); + pc_iu_abist_g8t_bw_1 : in std_ulogic; + pc_iu_abist_g8t_bw_0 : in std_ulogic; + pc_iu_abist_waddr_0 : in std_ulogic_vector(4 to 9); + pc_iu_abist_raddr_0 : in std_ulogic_vector(2 to 9); + pc_iu_abist_ena_dc : in std_ulogic; + pc_iu_abist_wl64_comp_ena : in std_ulogic; + pc_iu_abist_raw_dc_b : in std_ulogic; + pc_iu_abist_g8t_dcomp : in std_ulogic_vector(0 to 3); + pc_iu_abist_g6t_bw : in std_ulogic_vector(0 to 1); + pc_iu_abist_di_g6t_2r : in std_ulogic_vector(0 to 3); + pc_iu_abist_wl256_comp_ena : in std_ulogic; + pc_iu_abist_dcomp_g6t_2r : in std_ulogic_vector(0 to 3); + pc_iu_abist_g6t_r_wb : in std_ulogic; + an_ac_lbist_ary_wrt_thru_dc: in std_ulogic; + + pc_iu_bo_enable_2 : in std_ulogic; + pc_iu_bo_reset : in std_ulogic; + pc_iu_bo_unload : in std_ulogic; + pc_iu_bo_repair : in std_ulogic; + pc_iu_bo_shdata : in std_ulogic; + pc_iu_bo_select : in std_ulogic_vector(0 to 3); + iu_pc_bo_fail : out std_ulogic_vector(0 to 3); + iu_pc_bo_diagout : out std_ulogic_vector(0 to 3); + + xu_iu_ici : in std_ulogic; + + iu_mm_ierat_epn : out std_ulogic_vector(0 to 51); + + iu_ierat_iu1_back_inv : out std_ulogic; + + ierat_iu_iu2_rpn : in std_ulogic_vector(REAL_IFAR'left to 51); + ierat_iu_iu2_wimge : in std_ulogic_vector(0 to 4); + ierat_iu_iu2_u : in std_ulogic_vector(0 to 3); + ierat_iu_iu2_error : in std_ulogic_vector(0 to 2); + ierat_iu_iu2_miss : in std_ulogic; + ierat_iu_iu2_multihit : in std_ulogic; + ierat_iu_iu2_isi : in std_ulogic; + + ics_icd_dir_rd_act : in std_ulogic; + ics_icd_data_rd_act : in std_ulogic; + ics_icd_iu0_valid : in std_ulogic; + ics_icd_iu0_tid : in std_ulogic_vector(0 to 3); + ics_icd_iu0_ifar : in EFF_IFAR; + ics_icd_iu0_inval : in std_ulogic; + ics_icd_iu0_2ucode : in std_ulogic; + ics_icd_iu0_2ucode_type : in std_ulogic; + ics_icd_iu0_spr_idir_read : in std_ulogic; + + icd_ics_iu1_valid : out std_ulogic; + icd_ics_iu1_tid : out std_ulogic_vector(0 to 3); + icd_ics_iu1_ifar : out EFF_IFAR; + icd_ics_iu1_2ucode : out std_ulogic; + icd_ics_iu1_2ucode_type : out std_ulogic; + + ics_icd_all_flush_prev : in std_ulogic_vector(0 to 3); + ics_icd_iu1_flush_tid : in std_ulogic_vector(0 to 3); + ics_icd_iu2_flush_tid : in std_ulogic_vector(0 to 3); + icd_ics_iu2_miss_flush_prev: out std_ulogic_vector(0 to 3); + icd_ics_iu2_ifar_eff : out EFF_IFAR; + icd_ics_iu2_2ucode : out std_ulogic; + icd_ics_iu2_2ucode_type : out std_ulogic; + icd_ics_iu3_parity_flush : out std_ulogic_vector(0 to 3); + icd_ics_iu3_ifar : out EFF_IFAR; + icd_ics_iu3_2ucode : out std_ulogic; + icd_ics_iu3_2ucode_type : out std_ulogic; + + icm_icd_lru_addr : in std_ulogic_vector(52 to 57); + icm_icd_dir_inval : in std_ulogic; + icm_icd_dir_val : in std_ulogic; + icm_icd_data_write : in std_ulogic; + icm_icd_reload_addr : in std_ulogic_vector(52 to 59); + icm_icd_reload_data : in std_ulogic_vector(0 to 161); + icm_icd_reload_way : in std_ulogic_vector(0 to 3); + icm_icd_load_tid : in std_ulogic_vector(0 to 3); + icm_icd_load_addr : in EFF_IFAR; + icm_icd_load_2ucode : in std_ulogic; + icm_icd_load_2ucode_type : in std_ulogic; + icm_icd_dir_write : in std_ulogic; + icm_icd_dir_write_addr : in std_ulogic_vector(REAL_IFAR'left to 57); + icm_icd_dir_write_endian : in std_ulogic; + icm_icd_dir_write_way : in std_ulogic_vector(0 to 3); + icm_icd_lru_write : in std_ulogic; + icm_icd_lru_write_addr : in std_ulogic_vector(52 to 57); + icm_icd_lru_write_way : in std_ulogic_vector(0 to 3); + icm_icd_ecc_inval : in std_ulogic; + icm_icd_ecc_addr : in std_ulogic_vector(52 to 57); + icm_icd_ecc_way : in std_ulogic_vector(0 to 3); + icm_icd_iu3_ecc_fp_cancel : in std_ulogic; + icm_icd_iu3_ecc_err : in std_ulogic; + icm_icd_any_reld_r2 : in std_ulogic; + icm_icd_any_checkecc : in std_ulogic; + + icd_icm_miss : out std_ulogic; + icd_icm_tid : out std_ulogic_vector(0 to 3); + icd_icm_addr_real : out REAL_IFAR; + icd_icm_addr_eff : out std_ulogic_vector(EFF_IFAR'left to 51); + icd_icm_wimge : out std_ulogic_vector(0 to 4); + icd_icm_userdef : out std_ulogic_vector(0 to 3); + icd_icm_2ucode : out std_ulogic; + icd_icm_2ucode_type : out std_ulogic; + icd_icm_iu3_erat_err : out std_ulogic; + icd_icm_iu2_inval : out std_ulogic; + icd_icm_ici : out std_ulogic; + icd_icm_any_iu2_valid : out std_ulogic; + + icd_icm_row_lru : out std_ulogic_vector(0 to 2); + icd_icm_row_val : out std_ulogic_vector(0 to 3); + + ic_bp_iu3_val : out std_ulogic_vector(0 to 3); + ic_bp_iu3_tid : out std_ulogic_vector(0 to 3); + ic_bp_iu3_ifar : out EFF_IFAR; + ic_bp_iu3_2ucode : out std_ulogic; + ic_bp_iu3_2ucode_type : out std_ulogic; + ic_bp_iu3_error : out std_ulogic_vector(0 to 2); + ic_bp_iu3_flush : out std_ulogic; + + ic_bp_iu3_0_instr : out std_ulogic_vector(0 to 35); + ic_bp_iu3_1_instr : out std_ulogic_vector(0 to 35); + ic_bp_iu3_2_instr : out std_ulogic_vector(0 to 35); + ic_bp_iu3_3_instr : out std_ulogic_vector(0 to 35); + + event_bus_enable : in std_ulogic; + + trace_bus_enable : in std_ulogic; + dir_dbg_data0 : out std_ulogic_vector(0 to 87); + dir_dbg_data1 : out std_ulogic_vector(0 to 87); + dir_dbg_data2 : out std_ulogic_vector(0 to 43); + dir_dbg_trigger0 : out std_ulogic_vector(0 to 7); + dir_dbg_trigger1 : out std_ulogic_vector(0 to 11) +); +-- synopsys translate_off +-- synopsys translate_on +end iuq_ic_dir; +ARCHITECTURE IUQ_IC_DIR + OF IUQ_IC_DIR + IS +constant ways : natural := 4; +constant dir_ext_bits : natural := 8 - ((52-REAL_IFAR'left+1) mod 8); +constant dir_parity_width : natural := (52-REAL_IFAR'left+1+dir_ext_bits)/8; +constant dir_array_way_width : natural := 36; +constant dir_way_width : natural := 52-REAL_IFAR'left+1+dir_parity_width; +-- Chain 0 +constant dbg_dir_write_offset : natural := 0; +constant dbg_dir_rd_act_offset : natural := dbg_dir_write_offset + 1; +constant dbg_iu2_lru_rd_update_offset : natural := dbg_dir_rd_act_offset + 1; +constant dbg_iu2_rd_way_tag_hit_offset : natural := dbg_iu2_lru_rd_update_offset + 1; +constant dbg_iu2_rd_way_hit_offset : natural := dbg_iu2_rd_way_tag_hit_offset + 4; +constant dbg_load_iu2_offset : natural := dbg_iu2_rd_way_hit_offset + 4; +constant iu1_valid_offset : natural := dbg_load_iu2_offset + 1; +constant spare_a_offset : natural := iu1_valid_offset + 1; +constant iu1_tid_offset : natural := spare_a_offset + 8; +constant iu1_ifar_offset : natural := iu1_tid_offset + 4; +constant iu1_inval_offset : natural := iu1_ifar_offset + EFF_IFAR'length; +constant iu1_2ucode_offset : natural := iu1_inval_offset + 1; +constant iu1_2ucode_type_offset : natural := iu1_2ucode_offset + 1; +constant iu2_valid_offset : natural := iu1_2ucode_type_offset + 1; +constant iu2_tid_offset : natural := iu2_valid_offset + 1; +constant iu2_ifar_eff_offset : natural := iu2_tid_offset + 4; +constant iu2_2ucode_offset : natural := iu2_ifar_eff_offset + EFF_IFAR'length; +constant iu2_2ucode_type_offset : natural := iu2_2ucode_offset + 1; +constant iu2_inval_offset : natural := iu2_2ucode_type_offset + 1; +constant iu2_dir_rd_val_offset : natural := iu2_inval_offset + 1; +constant iu3_instr_valid_offset : natural := iu2_dir_rd_val_offset + 4; +constant iu3_tid_offset : natural := iu3_instr_valid_offset + 4; +constant iu3_ifar_offset : natural := iu3_tid_offset + 4; +constant iu3_ifar_dec_offset : natural := iu3_ifar_offset + EFF_IFAR'length; +constant iu3_2ucode_offset : natural := iu3_ifar_dec_offset + 4; +constant iu3_2ucode_type_offset : natural := iu3_2ucode_offset + 1; +constant iu3_erat_err_offset : natural := iu3_2ucode_type_offset + 1; +constant iu3_instr_offset : natural := iu3_erat_err_offset + 3; +constant iu3_dir_parity_err_way_offset : natural := iu3_instr_offset + 1; +constant iu3_data_parity_err_way_offset : natural := iu3_dir_parity_err_way_offset + 4; +constant iu3_parity_needs_flush_offset : natural := iu3_data_parity_err_way_offset + 4; +constant iu3_rd_parity_err_offset : natural := iu3_parity_needs_flush_offset + 4; +constant iu3_rd_miss_offset : natural := iu3_rd_parity_err_offset + 1; +constant err_icache_parity_offset : natural := iu3_rd_miss_offset + 1; +constant err_icachedir_parity_offset : natural := err_icache_parity_offset + 1; +constant iu3_multihit_err_way_offset : natural := err_icachedir_parity_offset + 1; +constant iu3_multihit_flush_offset : natural := iu3_multihit_err_way_offset + 4; +constant iu3_parity_tag_offset : natural := iu3_multihit_flush_offset + 1; +constant spare_slp_offset : natural := iu3_parity_tag_offset + 6; +constant perf_instr_count_t0_offset : natural := spare_slp_offset + 16; +constant perf_instr_count_t1_offset : natural := perf_instr_count_t0_offset + 2; +constant perf_instr_count_t2_offset : natural := perf_instr_count_t1_offset + 2; +constant perf_instr_count_t3_offset : natural := perf_instr_count_t2_offset + 2; +constant perf_event_t0_offset : natural := perf_instr_count_t3_offset + 2; +constant perf_event_t1_offset : natural := perf_event_t0_offset + 3; +constant perf_event_t2_offset : natural := perf_event_t1_offset + 3; +constant perf_event_t3_offset : natural := perf_event_t2_offset + 3; +constant perf_event_offset : natural := perf_event_t3_offset + 3; +constant spr_ic_cls_offset : natural := perf_event_offset + 2; +constant spr_ic_idir_way_offset : natural := spr_ic_cls_offset + 1; +constant spare_b_offset : natural := spr_ic_idir_way_offset + 2; +constant iu1_spr_idir_read_offset : natural := spare_b_offset + 8; +constant iu2_spr_idir_read_offset : natural := iu1_spr_idir_read_offset + 1; +constant iu2_spr_idir_lru_offset : natural := iu2_spr_idir_read_offset + 1; +constant scan0_right : natural := iu2_spr_idir_lru_offset + 3 - 1; +-- Chain 1 +constant scan1_left : natural := scan0_right + 1; +constant iu2_dir_dataout_offset : natural := scan1_left; +constant iu2_dir_dataout_0_par_offset : natural := iu2_dir_dataout_offset + 1; +constant iu2_dir_dataout_1_par_offset : natural := iu2_dir_dataout_0_par_offset + dir_parity_width; +constant iu2_dir_dataout_2_par_offset : natural := iu2_dir_dataout_1_par_offset + dir_parity_width; +constant iu2_dir_dataout_3_par_offset : natural := iu2_dir_dataout_2_par_offset + dir_parity_width; +constant iu2_data_dataout_offset : natural := iu2_dir_dataout_3_par_offset + dir_parity_width; +constant xu_iu_ici_offset : natural := iu2_data_dataout_offset + 162*ways; +constant dir_row0_val_offset : natural := xu_iu_ici_offset + 1; +constant dir_row1_val_offset : natural := dir_row0_val_offset + 4; +constant dir_row2_val_offset : natural := dir_row1_val_offset + 4; +constant dir_row3_val_offset : natural := dir_row2_val_offset + 4; +constant dir_row4_val_offset : natural := dir_row3_val_offset + 4; +constant dir_row5_val_offset : natural := dir_row4_val_offset + 4; +constant dir_row6_val_offset : natural := dir_row5_val_offset + 4; +constant dir_row7_val_offset : natural := dir_row6_val_offset + 4; +constant dir_row8_val_offset : natural := dir_row7_val_offset + 4; +constant dir_row9_val_offset : natural := dir_row8_val_offset + 4; +constant dir_row10_val_offset : natural := dir_row9_val_offset + 4; +constant dir_row11_val_offset : natural := dir_row10_val_offset + 4; +constant dir_row12_val_offset : natural := dir_row11_val_offset + 4; +constant dir_row13_val_offset : natural := dir_row12_val_offset + 4; +constant dir_row14_val_offset : natural := dir_row13_val_offset + 4; +constant dir_row15_val_offset : natural := dir_row14_val_offset + 4; +constant dir_row16_val_offset : natural := dir_row15_val_offset + 4; +constant dir_row17_val_offset : natural := dir_row16_val_offset + 4; +constant dir_row18_val_offset : natural := dir_row17_val_offset + 4; +constant dir_row19_val_offset : natural := dir_row18_val_offset + 4; +constant dir_row20_val_offset : natural := dir_row19_val_offset + 4; +constant dir_row21_val_offset : natural := dir_row20_val_offset + 4; +constant dir_row22_val_offset : natural := dir_row21_val_offset + 4; +constant dir_row23_val_offset : natural := dir_row22_val_offset + 4; +constant dir_row24_val_offset : natural := dir_row23_val_offset + 4; +constant dir_row25_val_offset : natural := dir_row24_val_offset + 4; +constant dir_row26_val_offset : natural := dir_row25_val_offset + 4; +constant dir_row27_val_offset : natural := dir_row26_val_offset + 4; +constant dir_row28_val_offset : natural := dir_row27_val_offset + 4; +constant dir_row29_val_offset : natural := dir_row28_val_offset + 4; +constant dir_row30_val_offset : natural := dir_row29_val_offset + 4; +constant dir_row31_val_offset : natural := dir_row30_val_offset + 4; +constant dir_row32_val_offset : natural := dir_row31_val_offset + 4; +constant dir_row33_val_offset : natural := dir_row32_val_offset + 4; +constant dir_row34_val_offset : natural := dir_row33_val_offset + 4; +constant dir_row35_val_offset : natural := dir_row34_val_offset + 4; +constant dir_row36_val_offset : natural := dir_row35_val_offset + 4; +constant dir_row37_val_offset : natural := dir_row36_val_offset + 4; +constant dir_row38_val_offset : natural := dir_row37_val_offset + 4; +constant dir_row39_val_offset : natural := dir_row38_val_offset + 4; +constant dir_row40_val_offset : natural := dir_row39_val_offset + 4; +constant dir_row41_val_offset : natural := dir_row40_val_offset + 4; +constant dir_row42_val_offset : natural := dir_row41_val_offset + 4; +constant dir_row43_val_offset : natural := dir_row42_val_offset + 4; +constant dir_row44_val_offset : natural := dir_row43_val_offset + 4; +constant dir_row45_val_offset : natural := dir_row44_val_offset + 4; +constant dir_row46_val_offset : natural := dir_row45_val_offset + 4; +constant dir_row47_val_offset : natural := dir_row46_val_offset + 4; +constant dir_row48_val_offset : natural := dir_row47_val_offset + 4; +constant dir_row49_val_offset : natural := dir_row48_val_offset + 4; +constant dir_row50_val_offset : natural := dir_row49_val_offset + 4; +constant dir_row51_val_offset : natural := dir_row50_val_offset + 4; +constant dir_row52_val_offset : natural := dir_row51_val_offset + 4; +constant dir_row53_val_offset : natural := dir_row52_val_offset + 4; +constant dir_row54_val_offset : natural := dir_row53_val_offset + 4; +constant dir_row55_val_offset : natural := dir_row54_val_offset + 4; +constant dir_row56_val_offset : natural := dir_row55_val_offset + 4; +constant dir_row57_val_offset : natural := dir_row56_val_offset + 4; +constant dir_row58_val_offset : natural := dir_row57_val_offset + 4; +constant dir_row59_val_offset : natural := dir_row58_val_offset + 4; +constant dir_row60_val_offset : natural := dir_row59_val_offset + 4; +constant dir_row61_val_offset : natural := dir_row60_val_offset + 4; +constant dir_row62_val_offset : natural := dir_row61_val_offset + 4; +constant dir_row63_val_offset : natural := dir_row62_val_offset + 4; +constant dir_row0_lru_offset : natural := dir_row63_val_offset + 4; +constant dir_row1_lru_offset : natural := dir_row0_lru_offset + 3; +constant dir_row2_lru_offset : natural := dir_row1_lru_offset + 3; +constant dir_row3_lru_offset : natural := dir_row2_lru_offset + 3; +constant dir_row4_lru_offset : natural := dir_row3_lru_offset + 3; +constant dir_row5_lru_offset : natural := dir_row4_lru_offset + 3; +constant dir_row6_lru_offset : natural := dir_row5_lru_offset + 3; +constant dir_row7_lru_offset : natural := dir_row6_lru_offset + 3; +constant dir_row8_lru_offset : natural := dir_row7_lru_offset + 3; +constant dir_row9_lru_offset : natural := dir_row8_lru_offset + 3; +constant dir_row10_lru_offset : natural := dir_row9_lru_offset + 3; +constant dir_row11_lru_offset : natural := dir_row10_lru_offset + 3; +constant dir_row12_lru_offset : natural := dir_row11_lru_offset + 3; +constant dir_row13_lru_offset : natural := dir_row12_lru_offset + 3; +constant dir_row14_lru_offset : natural := dir_row13_lru_offset + 3; +constant dir_row15_lru_offset : natural := dir_row14_lru_offset + 3; +constant dir_row16_lru_offset : natural := dir_row15_lru_offset + 3; +constant dir_row17_lru_offset : natural := dir_row16_lru_offset + 3; +constant dir_row18_lru_offset : natural := dir_row17_lru_offset + 3; +constant dir_row19_lru_offset : natural := dir_row18_lru_offset + 3; +constant dir_row20_lru_offset : natural := dir_row19_lru_offset + 3; +constant dir_row21_lru_offset : natural := dir_row20_lru_offset + 3; +constant dir_row22_lru_offset : natural := dir_row21_lru_offset + 3; +constant dir_row23_lru_offset : natural := dir_row22_lru_offset + 3; +constant dir_row24_lru_offset : natural := dir_row23_lru_offset + 3; +constant dir_row25_lru_offset : natural := dir_row24_lru_offset + 3; +constant dir_row26_lru_offset : natural := dir_row25_lru_offset + 3; +constant dir_row27_lru_offset : natural := dir_row26_lru_offset + 3; +constant dir_row28_lru_offset : natural := dir_row27_lru_offset + 3; +constant dir_row29_lru_offset : natural := dir_row28_lru_offset + 3; +constant dir_row30_lru_offset : natural := dir_row29_lru_offset + 3; +constant dir_row31_lru_offset : natural := dir_row30_lru_offset + 3; +constant dir_row32_lru_offset : natural := dir_row31_lru_offset + 3; +constant dir_row33_lru_offset : natural := dir_row32_lru_offset + 3; +constant dir_row34_lru_offset : natural := dir_row33_lru_offset + 3; +constant dir_row35_lru_offset : natural := dir_row34_lru_offset + 3; +constant dir_row36_lru_offset : natural := dir_row35_lru_offset + 3; +constant dir_row37_lru_offset : natural := dir_row36_lru_offset + 3; +constant dir_row38_lru_offset : natural := dir_row37_lru_offset + 3; +constant dir_row39_lru_offset : natural := dir_row38_lru_offset + 3; +constant dir_row40_lru_offset : natural := dir_row39_lru_offset + 3; +constant dir_row41_lru_offset : natural := dir_row40_lru_offset + 3; +constant dir_row42_lru_offset : natural := dir_row41_lru_offset + 3; +constant dir_row43_lru_offset : natural := dir_row42_lru_offset + 3; +constant dir_row44_lru_offset : natural := dir_row43_lru_offset + 3; +constant dir_row45_lru_offset : natural := dir_row44_lru_offset + 3; +constant dir_row46_lru_offset : natural := dir_row45_lru_offset + 3; +constant dir_row47_lru_offset : natural := dir_row46_lru_offset + 3; +constant dir_row48_lru_offset : natural := dir_row47_lru_offset + 3; +constant dir_row49_lru_offset : natural := dir_row48_lru_offset + 3; +constant dir_row50_lru_offset : natural := dir_row49_lru_offset + 3; +constant dir_row51_lru_offset : natural := dir_row50_lru_offset + 3; +constant dir_row52_lru_offset : natural := dir_row51_lru_offset + 3; +constant dir_row53_lru_offset : natural := dir_row52_lru_offset + 3; +constant dir_row54_lru_offset : natural := dir_row53_lru_offset + 3; +constant dir_row55_lru_offset : natural := dir_row54_lru_offset + 3; +constant dir_row56_lru_offset : natural := dir_row55_lru_offset + 3; +constant dir_row57_lru_offset : natural := dir_row56_lru_offset + 3; +constant dir_row58_lru_offset : natural := dir_row57_lru_offset + 3; +constant dir_row59_lru_offset : natural := dir_row58_lru_offset + 3; +constant dir_row60_lru_offset : natural := dir_row59_lru_offset + 3; +constant dir_row61_lru_offset : natural := dir_row60_lru_offset + 3; +constant dir_row62_lru_offset : natural := dir_row61_lru_offset + 3; +constant dir_row63_lru_offset : natural := dir_row62_lru_offset + 3; +constant scan_right : natural := dir_row63_lru_offset + 3 - 1; +subtype s2 is std_ulogic_vector(0 to 1); +subtype s3 is std_ulogic_vector(0 to 2); +subtype s6 is std_ulogic_vector(0 to 5); +subtype s11 is std_ulogic_vector(0 to 10); +signal ZEROS : std_ulogic_vector(6 to 35); +signal tidn : std_ulogic; +signal tiup : std_ulogic; +-- Latch inputs +-- IU1 pipeline +signal iu1_valid_d : std_ulogic; +signal iu1_valid_l2 : std_ulogic; +signal iu1_tid_d : std_ulogic_vector(0 to 3); +signal iu1_tid_l2 : std_ulogic_vector(0 to 3); +signal iu1_ifar_d : EFF_IFAR; +signal iu1_ifar_l2 : EFF_IFAR; +signal iu1_inval_d : std_ulogic; +signal iu1_inval_l2 : std_ulogic; +signal iu1_2ucode_d : std_ulogic; +signal iu1_2ucode_l2 : std_ulogic; +signal iu1_2ucode_type_d : std_ulogic; +signal iu1_2ucode_type_l2 : std_ulogic; +-- IU2 pipeline +signal iu2_valid_d : std_ulogic; +signal iu2_valid_l2 : std_ulogic; +signal iu2_tid_d : std_ulogic_vector(0 to 3); +signal iu2_tid_l2 : std_ulogic_vector(0 to 3); +signal iu2_ifar_eff_d : EFF_IFAR; +signal iu2_ifar_eff_l2 : EFF_IFAR; +signal iu2_2ucode_d : std_ulogic; +signal iu2_2ucode_l2 : std_ulogic; +signal iu2_2ucode_type_d : std_ulogic; +signal iu2_2ucode_type_l2 : std_ulogic; +signal iu2_inval_d : std_ulogic; +signal iu2_inval_l2 : std_ulogic; +signal iu2_dir_rd_val_d : std_ulogic_vector(0 to 3); +signal iu2_dir_rd_val_l2 : std_ulogic_vector(0 to 3); +signal iu2_dir_dataout_0_d : std_ulogic_vector(22 to 52); +signal iu2_dir_dataout_0_noncmp : std_ulogic_vector(22 to 52); +signal iu2_dir_dataout_1_d : std_ulogic_vector(22 to 52); +signal iu2_dir_dataout_1_noncmp : std_ulogic_vector(22 to 52); +signal iu2_dir_dataout_2_d : std_ulogic_vector(22 to 52); +signal iu2_dir_dataout_2_noncmp : std_ulogic_vector(22 to 52); +signal iu2_dir_dataout_3_d : std_ulogic_vector(22 to 52); +signal iu2_dir_dataout_3_noncmp : std_ulogic_vector(22 to 52); +signal iu2_dir_dataout_0_par_d : std_ulogic_vector(0 to dir_parity_width-1); +signal iu2_dir_dataout_0_par_l2 : std_ulogic_vector(0 to dir_parity_width-1); +signal iu2_dir_dataout_1_par_d : std_ulogic_vector(0 to dir_parity_width-1); +signal iu2_dir_dataout_1_par_l2 : std_ulogic_vector(0 to dir_parity_width-1); +signal iu2_dir_dataout_2_par_d : std_ulogic_vector(0 to dir_parity_width-1); +signal iu2_dir_dataout_2_par_l2 : std_ulogic_vector(0 to dir_parity_width-1); +signal iu2_dir_dataout_3_par_d : std_ulogic_vector(0 to dir_parity_width-1); +signal iu2_dir_dataout_3_par_l2 : std_ulogic_vector(0 to dir_parity_width-1); +signal iu2_data_dataout_d : std_ulogic_vector(0 to 162*ways-1); +signal iu2_data_dataout_l2 : std_ulogic_vector(0 to 162*ways-1); +signal xu_iu_ici_d : std_ulogic; +signal xu_iu_ici_l2 : std_ulogic; +-- Dir val & LRU +signal dir_row0_val_d : std_ulogic_vector(0 to 3); +signal dir_row0_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row0_lru_d : std_ulogic_vector(0 to 2); +signal dir_row0_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row1_val_d : std_ulogic_vector(0 to 3); +signal dir_row1_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row1_lru_d : std_ulogic_vector(0 to 2); +signal dir_row1_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row2_val_d : std_ulogic_vector(0 to 3); +signal dir_row2_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row2_lru_d : std_ulogic_vector(0 to 2); +signal dir_row2_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row3_val_d : std_ulogic_vector(0 to 3); +signal dir_row3_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row3_lru_d : std_ulogic_vector(0 to 2); +signal dir_row3_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row4_val_d : std_ulogic_vector(0 to 3); +signal dir_row4_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row4_lru_d : std_ulogic_vector(0 to 2); +signal dir_row4_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row5_val_d : std_ulogic_vector(0 to 3); +signal dir_row5_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row5_lru_d : std_ulogic_vector(0 to 2); +signal dir_row5_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row6_val_d : std_ulogic_vector(0 to 3); +signal dir_row6_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row6_lru_d : std_ulogic_vector(0 to 2); +signal dir_row6_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row7_val_d : std_ulogic_vector(0 to 3); +signal dir_row7_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row7_lru_d : std_ulogic_vector(0 to 2); +signal dir_row7_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row8_val_d : std_ulogic_vector(0 to 3); +signal dir_row8_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row8_lru_d : std_ulogic_vector(0 to 2); +signal dir_row8_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row9_val_d : std_ulogic_vector(0 to 3); +signal dir_row9_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row9_lru_d : std_ulogic_vector(0 to 2); +signal dir_row9_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row10_val_d : std_ulogic_vector(0 to 3); +signal dir_row10_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row10_lru_d : std_ulogic_vector(0 to 2); +signal dir_row10_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row11_val_d : std_ulogic_vector(0 to 3); +signal dir_row11_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row11_lru_d : std_ulogic_vector(0 to 2); +signal dir_row11_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row12_val_d : std_ulogic_vector(0 to 3); +signal dir_row12_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row12_lru_d : std_ulogic_vector(0 to 2); +signal dir_row12_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row13_val_d : std_ulogic_vector(0 to 3); +signal dir_row13_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row13_lru_d : std_ulogic_vector(0 to 2); +signal dir_row13_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row14_val_d : std_ulogic_vector(0 to 3); +signal dir_row14_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row14_lru_d : std_ulogic_vector(0 to 2); +signal dir_row14_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row15_val_d : std_ulogic_vector(0 to 3); +signal dir_row15_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row15_lru_d : std_ulogic_vector(0 to 2); +signal dir_row15_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row16_val_d : std_ulogic_vector(0 to 3); +signal dir_row16_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row16_lru_d : std_ulogic_vector(0 to 2); +signal dir_row16_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row17_val_d : std_ulogic_vector(0 to 3); +signal dir_row17_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row17_lru_d : std_ulogic_vector(0 to 2); +signal dir_row17_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row18_val_d : std_ulogic_vector(0 to 3); +signal dir_row18_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row18_lru_d : std_ulogic_vector(0 to 2); +signal dir_row18_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row19_val_d : std_ulogic_vector(0 to 3); +signal dir_row19_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row19_lru_d : std_ulogic_vector(0 to 2); +signal dir_row19_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row20_val_d : std_ulogic_vector(0 to 3); +signal dir_row20_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row20_lru_d : std_ulogic_vector(0 to 2); +signal dir_row20_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row21_val_d : std_ulogic_vector(0 to 3); +signal dir_row21_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row21_lru_d : std_ulogic_vector(0 to 2); +signal dir_row21_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row22_val_d : std_ulogic_vector(0 to 3); +signal dir_row22_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row22_lru_d : std_ulogic_vector(0 to 2); +signal dir_row22_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row23_val_d : std_ulogic_vector(0 to 3); +signal dir_row23_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row23_lru_d : std_ulogic_vector(0 to 2); +signal dir_row23_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row24_val_d : std_ulogic_vector(0 to 3); +signal dir_row24_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row24_lru_d : std_ulogic_vector(0 to 2); +signal dir_row24_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row25_val_d : std_ulogic_vector(0 to 3); +signal dir_row25_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row25_lru_d : std_ulogic_vector(0 to 2); +signal dir_row25_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row26_val_d : std_ulogic_vector(0 to 3); +signal dir_row26_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row26_lru_d : std_ulogic_vector(0 to 2); +signal dir_row26_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row27_val_d : std_ulogic_vector(0 to 3); +signal dir_row27_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row27_lru_d : std_ulogic_vector(0 to 2); +signal dir_row27_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row28_val_d : std_ulogic_vector(0 to 3); +signal dir_row28_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row28_lru_d : std_ulogic_vector(0 to 2); +signal dir_row28_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row29_val_d : std_ulogic_vector(0 to 3); +signal dir_row29_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row29_lru_d : std_ulogic_vector(0 to 2); +signal dir_row29_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row30_val_d : std_ulogic_vector(0 to 3); +signal dir_row30_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row30_lru_d : std_ulogic_vector(0 to 2); +signal dir_row30_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row31_val_d : std_ulogic_vector(0 to 3); +signal dir_row31_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row31_lru_d : std_ulogic_vector(0 to 2); +signal dir_row31_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row32_val_d : std_ulogic_vector(0 to 3); +signal dir_row32_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row32_lru_d : std_ulogic_vector(0 to 2); +signal dir_row32_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row33_val_d : std_ulogic_vector(0 to 3); +signal dir_row33_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row33_lru_d : std_ulogic_vector(0 to 2); +signal dir_row33_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row34_val_d : std_ulogic_vector(0 to 3); +signal dir_row34_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row34_lru_d : std_ulogic_vector(0 to 2); +signal dir_row34_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row35_val_d : std_ulogic_vector(0 to 3); +signal dir_row35_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row35_lru_d : std_ulogic_vector(0 to 2); +signal dir_row35_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row36_val_d : std_ulogic_vector(0 to 3); +signal dir_row36_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row36_lru_d : std_ulogic_vector(0 to 2); +signal dir_row36_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row37_val_d : std_ulogic_vector(0 to 3); +signal dir_row37_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row37_lru_d : std_ulogic_vector(0 to 2); +signal dir_row37_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row38_val_d : std_ulogic_vector(0 to 3); +signal dir_row38_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row38_lru_d : std_ulogic_vector(0 to 2); +signal dir_row38_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row39_val_d : std_ulogic_vector(0 to 3); +signal dir_row39_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row39_lru_d : std_ulogic_vector(0 to 2); +signal dir_row39_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row40_val_d : std_ulogic_vector(0 to 3); +signal dir_row40_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row40_lru_d : std_ulogic_vector(0 to 2); +signal dir_row40_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row41_val_d : std_ulogic_vector(0 to 3); +signal dir_row41_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row41_lru_d : std_ulogic_vector(0 to 2); +signal dir_row41_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row42_val_d : std_ulogic_vector(0 to 3); +signal dir_row42_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row42_lru_d : std_ulogic_vector(0 to 2); +signal dir_row42_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row43_val_d : std_ulogic_vector(0 to 3); +signal dir_row43_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row43_lru_d : std_ulogic_vector(0 to 2); +signal dir_row43_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row44_val_d : std_ulogic_vector(0 to 3); +signal dir_row44_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row44_lru_d : std_ulogic_vector(0 to 2); +signal dir_row44_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row45_val_d : std_ulogic_vector(0 to 3); +signal dir_row45_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row45_lru_d : std_ulogic_vector(0 to 2); +signal dir_row45_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row46_val_d : std_ulogic_vector(0 to 3); +signal dir_row46_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row46_lru_d : std_ulogic_vector(0 to 2); +signal dir_row46_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row47_val_d : std_ulogic_vector(0 to 3); +signal dir_row47_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row47_lru_d : std_ulogic_vector(0 to 2); +signal dir_row47_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row48_val_d : std_ulogic_vector(0 to 3); +signal dir_row48_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row48_lru_d : std_ulogic_vector(0 to 2); +signal dir_row48_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row49_val_d : std_ulogic_vector(0 to 3); +signal dir_row49_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row49_lru_d : std_ulogic_vector(0 to 2); +signal dir_row49_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row50_val_d : std_ulogic_vector(0 to 3); +signal dir_row50_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row50_lru_d : std_ulogic_vector(0 to 2); +signal dir_row50_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row51_val_d : std_ulogic_vector(0 to 3); +signal dir_row51_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row51_lru_d : std_ulogic_vector(0 to 2); +signal dir_row51_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row52_val_d : std_ulogic_vector(0 to 3); +signal dir_row52_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row52_lru_d : std_ulogic_vector(0 to 2); +signal dir_row52_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row53_val_d : std_ulogic_vector(0 to 3); +signal dir_row53_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row53_lru_d : std_ulogic_vector(0 to 2); +signal dir_row53_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row54_val_d : std_ulogic_vector(0 to 3); +signal dir_row54_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row54_lru_d : std_ulogic_vector(0 to 2); +signal dir_row54_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row55_val_d : std_ulogic_vector(0 to 3); +signal dir_row55_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row55_lru_d : std_ulogic_vector(0 to 2); +signal dir_row55_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row56_val_d : std_ulogic_vector(0 to 3); +signal dir_row56_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row56_lru_d : std_ulogic_vector(0 to 2); +signal dir_row56_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row57_val_d : std_ulogic_vector(0 to 3); +signal dir_row57_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row57_lru_d : std_ulogic_vector(0 to 2); +signal dir_row57_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row58_val_d : std_ulogic_vector(0 to 3); +signal dir_row58_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row58_lru_d : std_ulogic_vector(0 to 2); +signal dir_row58_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row59_val_d : std_ulogic_vector(0 to 3); +signal dir_row59_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row59_lru_d : std_ulogic_vector(0 to 2); +signal dir_row59_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row60_val_d : std_ulogic_vector(0 to 3); +signal dir_row60_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row60_lru_d : std_ulogic_vector(0 to 2); +signal dir_row60_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row61_val_d : std_ulogic_vector(0 to 3); +signal dir_row61_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row61_lru_d : std_ulogic_vector(0 to 2); +signal dir_row61_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row62_val_d : std_ulogic_vector(0 to 3); +signal dir_row62_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row62_lru_d : std_ulogic_vector(0 to 2); +signal dir_row62_lru_l2 : std_ulogic_vector(0 to 2); +signal dir_row63_val_d : std_ulogic_vector(0 to 3); +signal dir_row63_val_l2 : std_ulogic_vector(0 to 3); +signal dir_row63_lru_d : std_ulogic_vector(0 to 2); +signal dir_row63_lru_l2 : std_ulogic_vector(0 to 2); +-- IU3 pipeline +signal iu3_instr_valid_d : std_ulogic_vector(0 to 3); +signal iu3_instr_valid_l2 : std_ulogic_vector(0 to 3); +signal iu3_tid_d : std_ulogic_vector(0 to 3); +signal iu3_tid_l2 : std_ulogic_vector(0 to 3); +signal iu3_ifar_d : EFF_IFAR; +signal iu3_ifar_l2 : EFF_IFAR; +signal iu3_ifar_dec_d : std_ulogic_vector(0 to 3); +signal iu3_ifar_dec_l2 : std_ulogic_vector(0 to 3); +signal iu3_2ucode_d : std_ulogic; +signal iu3_2ucode_l2 : std_ulogic; +signal iu3_2ucode_type_d : std_ulogic; +signal iu3_2ucode_type_l2 : std_ulogic; +signal iu3_erat_err_d : std_ulogic_vector(0 to 2); +signal iu3_erat_err_l2 : std_ulogic_vector(0 to 2); +signal iu3_dir_parity_err_way_d : std_ulogic_vector(0 to 3); +signal iu3_dir_parity_err_way_l2 : std_ulogic_vector(0 to 3); +signal iu3_data_parity_err_way_d : std_ulogic_vector(0 to 3); +signal iu3_data_parity_err_way_l2: std_ulogic_vector(0 to 3); +signal iu3_parity_tag_d : std_ulogic_vector(52 to 57); +signal iu3_parity_tag_l2 : std_ulogic_vector(52 to 57); +signal iu3_parity_needs_flush_d : std_ulogic_vector(0 to 3); +signal iu3_parity_needs_flush_l2 : std_ulogic_vector(0 to 3); +signal iu3_parity_needs_flush : std_ulogic; +signal iu3_parity_flush_tid : std_ulogic_vector(0 to 3); +signal iu3_parity_flush : std_ulogic; +signal iu3_rd_parity_err_d : std_ulogic; +signal iu3_rd_parity_err_l2 : std_ulogic; +signal iu3_rd_miss_d : std_ulogic; +signal iu3_rd_miss_l2 : std_ulogic; +signal err_icache_parity_d : std_ulogic; +signal err_icache_parity_l2 : std_ulogic; +signal err_icachedir_parity_d : std_ulogic; +signal err_icachedir_parity_l2 : std_ulogic; +signal iu3_multihit_err_way_d : std_ulogic_vector(0 to 3); +signal iu3_multihit_err_way_l2 : std_ulogic_vector(0 to 3); +signal iu3_multihit_flush_d : std_ulogic; +signal iu3_multihit_flush_l2 : std_ulogic; +signal perf_instr_count_t0_d : std_ulogic_vector(0 to 1); +signal perf_instr_count_t0_l2 : std_ulogic_vector(0 to 1); +signal perf_instr_count_t1_d : std_ulogic_vector(0 to 1); +signal perf_instr_count_t1_l2 : std_ulogic_vector(0 to 1); +signal perf_instr_count_t2_d : std_ulogic_vector(0 to 1); +signal perf_instr_count_t2_l2 : std_ulogic_vector(0 to 1); +signal perf_instr_count_t3_d : std_ulogic_vector(0 to 1); +signal perf_instr_count_t3_l2 : std_ulogic_vector(0 to 1); +signal perf_event_t0_d : std_ulogic_vector(4 to 6); +signal perf_event_t0_l2 : std_ulogic_vector(4 to 6); +signal perf_event_t1_d : std_ulogic_vector(4 to 6); +signal perf_event_t1_l2 : std_ulogic_vector(4 to 6); +signal perf_event_t2_d : std_ulogic_vector(4 to 6); +signal perf_event_t2_l2 : std_ulogic_vector(4 to 6); +signal perf_event_t3_d : std_ulogic_vector(4 to 6); +signal perf_event_t3_l2 : std_ulogic_vector(4 to 6); +signal perf_event_d : std_ulogic_vector(0 to 1); +signal perf_event_l2 : std_ulogic_vector(0 to 1); +signal spr_ic_cls_d : std_ulogic; +signal spr_ic_cls_l2 : std_ulogic; +signal spr_ic_idir_way_d : std_ulogic_vector(0 to 1); +signal spr_ic_idir_way_l2 : std_ulogic_vector(0 to 1); +signal iu1_spr_idir_read_d : std_ulogic; +signal iu1_spr_idir_read_l2 : std_ulogic; +signal iu2_spr_idir_read_d : std_ulogic; +signal iu2_spr_idir_read_l2 : std_ulogic; +signal iu2_spr_idir_lru_d : std_ulogic_vector(0 to 2); +signal iu2_spr_idir_lru_l2 : std_ulogic_vector(0 to 2); +signal dbg_dir_write_d : std_ulogic; +signal dbg_dir_write_l2 : std_ulogic; +signal dbg_dir_rd_act_d : std_ulogic; +signal dbg_dir_rd_act_l2 : std_ulogic; +signal dbg_iu2_lru_rd_update_d : std_ulogic; +signal dbg_iu2_lru_rd_update_l2 : std_ulogic; +signal dbg_iu2_rd_way_tag_hit_d : std_ulogic_vector(0 to 3); +signal dbg_iu2_rd_way_tag_hit_l2 : std_ulogic_vector(0 to 3); +signal dbg_iu2_rd_way_hit_d : std_ulogic_vector(0 to 3); +signal dbg_iu2_rd_way_hit_l2 : std_ulogic_vector(0 to 3); +signal dbg_load_iu2_d : std_ulogic; +signal dbg_load_iu2_l2 : std_ulogic; +signal spare_slp_l2 : std_ulogic_vector(0 to 15); +signal spare_l2 : std_ulogic_vector(0 to 15); +-- IFAR +signal iu2_ci : std_ulogic; +signal iu2_endian : std_ulogic; +-- IDIR +signal dir_rd_act : std_ulogic; +signal dir_write : std_ulogic; +signal dir_way : std_ulogic_vector(0 to ways-1); +signal dir_wr_addr : std_ulogic_vector(0 to 5); +signal dir_rd_addr : std_ulogic_vector(0 to 5); +signal ext_dir_datain : std_ulogic_vector(0 to dir_parity_width*8-1); +signal dir_parity_in : std_ulogic_vector(0 to dir_parity_width-1); +signal way_datain : std_ulogic_vector(0 to dir_array_way_width-1); +signal way_datain_rev : std_ulogic_vector(0 to dir_array_way_width-1); +signal dir_datain_rev : std_ulogic_vector(0 to dir_array_way_width*ways-1); +signal dir_dataout_rev : std_ulogic_vector(0 to dir_array_way_width*ways-1); +signal dir_dataout : std_ulogic_vector(0 to dir_array_way_width*ways-1); +signal dir_dataout_act : std_ulogic; +signal iu1_ifar_cacheline : std_ulogic_vector(0 to 5); +signal dir_rd_val : std_ulogic_vector(0 to 3); +-- IDATA +signal data_write : std_ulogic; +signal data_way : std_ulogic_vector(0 to ways-1); +signal data_addr : std_ulogic_vector(0 to 7); +signal data_parity_in : std_ulogic_vector(0 to 17); +signal data_datain : std_ulogic_vector(0 to 161); +signal data_dataout : std_ulogic_vector(0 to 162*ways-1); +signal data_dataout_inj : std_ulogic_vector(0 to 162*ways-1); +-- Compare +signal ierat_iu_iu2_rpn_noncmp : std_ulogic_vector(22 to 51); +signal iu2_rd_way_tag_hit : std_ulogic_vector(0 to 3); +signal iu2_rd_way_hit : std_ulogic_vector(0 to 3); +signal iu2_rd_way_hit_insmux_b : std_ulogic_vector(0 to 3); +signal iu2_dir_miss : std_ulogic; +signal iu2_valid : std_ulogic; +signal dir_row_lru_even_act : std_ulogic; +signal dir_row_lru_odd_act : std_ulogic; +signal iu2_erat_err_lite : std_ulogic; +signal iu2_lru_rd_update : std_ulogic; +signal dir_row0_lru_read : std_ulogic_vector(0 to 2); +signal dir_row0_lru_write : std_ulogic_vector(0 to 2); +signal dir_row1_lru_read : std_ulogic_vector(0 to 2); +signal dir_row1_lru_write : std_ulogic_vector(0 to 2); +signal dir_row2_lru_read : std_ulogic_vector(0 to 2); +signal dir_row2_lru_write : std_ulogic_vector(0 to 2); +signal dir_row3_lru_read : std_ulogic_vector(0 to 2); +signal dir_row3_lru_write : std_ulogic_vector(0 to 2); +signal dir_row4_lru_read : std_ulogic_vector(0 to 2); +signal dir_row4_lru_write : std_ulogic_vector(0 to 2); +signal dir_row5_lru_read : std_ulogic_vector(0 to 2); +signal dir_row5_lru_write : std_ulogic_vector(0 to 2); +signal dir_row6_lru_read : std_ulogic_vector(0 to 2); +signal dir_row6_lru_write : std_ulogic_vector(0 to 2); +signal dir_row7_lru_read : std_ulogic_vector(0 to 2); +signal dir_row7_lru_write : std_ulogic_vector(0 to 2); +signal dir_row8_lru_read : std_ulogic_vector(0 to 2); +signal dir_row8_lru_write : std_ulogic_vector(0 to 2); +signal dir_row9_lru_read : std_ulogic_vector(0 to 2); +signal dir_row9_lru_write : std_ulogic_vector(0 to 2); +signal dir_row10_lru_read : std_ulogic_vector(0 to 2); +signal dir_row10_lru_write : std_ulogic_vector(0 to 2); +signal dir_row11_lru_read : std_ulogic_vector(0 to 2); +signal dir_row11_lru_write : std_ulogic_vector(0 to 2); +signal dir_row12_lru_read : std_ulogic_vector(0 to 2); +signal dir_row12_lru_write : std_ulogic_vector(0 to 2); +signal dir_row13_lru_read : std_ulogic_vector(0 to 2); +signal dir_row13_lru_write : std_ulogic_vector(0 to 2); +signal dir_row14_lru_read : std_ulogic_vector(0 to 2); +signal dir_row14_lru_write : std_ulogic_vector(0 to 2); +signal dir_row15_lru_read : std_ulogic_vector(0 to 2); +signal dir_row15_lru_write : std_ulogic_vector(0 to 2); +signal dir_row16_lru_read : std_ulogic_vector(0 to 2); +signal dir_row16_lru_write : std_ulogic_vector(0 to 2); +signal dir_row17_lru_read : std_ulogic_vector(0 to 2); +signal dir_row17_lru_write : std_ulogic_vector(0 to 2); +signal dir_row18_lru_read : std_ulogic_vector(0 to 2); +signal dir_row18_lru_write : std_ulogic_vector(0 to 2); +signal dir_row19_lru_read : std_ulogic_vector(0 to 2); +signal dir_row19_lru_write : std_ulogic_vector(0 to 2); +signal dir_row20_lru_read : std_ulogic_vector(0 to 2); +signal dir_row20_lru_write : std_ulogic_vector(0 to 2); +signal dir_row21_lru_read : std_ulogic_vector(0 to 2); +signal dir_row21_lru_write : std_ulogic_vector(0 to 2); +signal dir_row22_lru_read : std_ulogic_vector(0 to 2); +signal dir_row22_lru_write : std_ulogic_vector(0 to 2); +signal dir_row23_lru_read : std_ulogic_vector(0 to 2); +signal dir_row23_lru_write : std_ulogic_vector(0 to 2); +signal dir_row24_lru_read : std_ulogic_vector(0 to 2); +signal dir_row24_lru_write : std_ulogic_vector(0 to 2); +signal dir_row25_lru_read : std_ulogic_vector(0 to 2); +signal dir_row25_lru_write : std_ulogic_vector(0 to 2); +signal dir_row26_lru_read : std_ulogic_vector(0 to 2); +signal dir_row26_lru_write : std_ulogic_vector(0 to 2); +signal dir_row27_lru_read : std_ulogic_vector(0 to 2); +signal dir_row27_lru_write : std_ulogic_vector(0 to 2); +signal dir_row28_lru_read : std_ulogic_vector(0 to 2); +signal dir_row28_lru_write : std_ulogic_vector(0 to 2); +signal dir_row29_lru_read : std_ulogic_vector(0 to 2); +signal dir_row29_lru_write : std_ulogic_vector(0 to 2); +signal dir_row30_lru_read : std_ulogic_vector(0 to 2); +signal dir_row30_lru_write : std_ulogic_vector(0 to 2); +signal dir_row31_lru_read : std_ulogic_vector(0 to 2); +signal dir_row31_lru_write : std_ulogic_vector(0 to 2); +signal dir_row32_lru_read : std_ulogic_vector(0 to 2); +signal dir_row32_lru_write : std_ulogic_vector(0 to 2); +signal dir_row33_lru_read : std_ulogic_vector(0 to 2); +signal dir_row33_lru_write : std_ulogic_vector(0 to 2); +signal dir_row34_lru_read : std_ulogic_vector(0 to 2); +signal dir_row34_lru_write : std_ulogic_vector(0 to 2); +signal dir_row35_lru_read : std_ulogic_vector(0 to 2); +signal dir_row35_lru_write : std_ulogic_vector(0 to 2); +signal dir_row36_lru_read : std_ulogic_vector(0 to 2); +signal dir_row36_lru_write : std_ulogic_vector(0 to 2); +signal dir_row37_lru_read : std_ulogic_vector(0 to 2); +signal dir_row37_lru_write : std_ulogic_vector(0 to 2); +signal dir_row38_lru_read : std_ulogic_vector(0 to 2); +signal dir_row38_lru_write : std_ulogic_vector(0 to 2); +signal dir_row39_lru_read : std_ulogic_vector(0 to 2); +signal dir_row39_lru_write : std_ulogic_vector(0 to 2); +signal dir_row40_lru_read : std_ulogic_vector(0 to 2); +signal dir_row40_lru_write : std_ulogic_vector(0 to 2); +signal dir_row41_lru_read : std_ulogic_vector(0 to 2); +signal dir_row41_lru_write : std_ulogic_vector(0 to 2); +signal dir_row42_lru_read : std_ulogic_vector(0 to 2); +signal dir_row42_lru_write : std_ulogic_vector(0 to 2); +signal dir_row43_lru_read : std_ulogic_vector(0 to 2); +signal dir_row43_lru_write : std_ulogic_vector(0 to 2); +signal dir_row44_lru_read : std_ulogic_vector(0 to 2); +signal dir_row44_lru_write : std_ulogic_vector(0 to 2); +signal dir_row45_lru_read : std_ulogic_vector(0 to 2); +signal dir_row45_lru_write : std_ulogic_vector(0 to 2); +signal dir_row46_lru_read : std_ulogic_vector(0 to 2); +signal dir_row46_lru_write : std_ulogic_vector(0 to 2); +signal dir_row47_lru_read : std_ulogic_vector(0 to 2); +signal dir_row47_lru_write : std_ulogic_vector(0 to 2); +signal dir_row48_lru_read : std_ulogic_vector(0 to 2); +signal dir_row48_lru_write : std_ulogic_vector(0 to 2); +signal dir_row49_lru_read : std_ulogic_vector(0 to 2); +signal dir_row49_lru_write : std_ulogic_vector(0 to 2); +signal dir_row50_lru_read : std_ulogic_vector(0 to 2); +signal dir_row50_lru_write : std_ulogic_vector(0 to 2); +signal dir_row51_lru_read : std_ulogic_vector(0 to 2); +signal dir_row51_lru_write : std_ulogic_vector(0 to 2); +signal dir_row52_lru_read : std_ulogic_vector(0 to 2); +signal dir_row52_lru_write : std_ulogic_vector(0 to 2); +signal dir_row53_lru_read : std_ulogic_vector(0 to 2); +signal dir_row53_lru_write : std_ulogic_vector(0 to 2); +signal dir_row54_lru_read : std_ulogic_vector(0 to 2); +signal dir_row54_lru_write : std_ulogic_vector(0 to 2); +signal dir_row55_lru_read : std_ulogic_vector(0 to 2); +signal dir_row55_lru_write : std_ulogic_vector(0 to 2); +signal dir_row56_lru_read : std_ulogic_vector(0 to 2); +signal dir_row56_lru_write : std_ulogic_vector(0 to 2); +signal dir_row57_lru_read : std_ulogic_vector(0 to 2); +signal dir_row57_lru_write : std_ulogic_vector(0 to 2); +signal dir_row58_lru_read : std_ulogic_vector(0 to 2); +signal dir_row58_lru_write : std_ulogic_vector(0 to 2); +signal dir_row59_lru_read : std_ulogic_vector(0 to 2); +signal dir_row59_lru_write : std_ulogic_vector(0 to 2); +signal dir_row60_lru_read : std_ulogic_vector(0 to 2); +signal dir_row60_lru_write : std_ulogic_vector(0 to 2); +signal dir_row61_lru_read : std_ulogic_vector(0 to 2); +signal dir_row61_lru_write : std_ulogic_vector(0 to 2); +signal dir_row62_lru_read : std_ulogic_vector(0 to 2); +signal dir_row62_lru_write : std_ulogic_vector(0 to 2); +signal dir_row63_lru_read : std_ulogic_vector(0 to 2); +signal dir_row63_lru_write : std_ulogic_vector(0 to 2); +signal iu2_ifar_eff_cacheline : std_ulogic_vector(0 to 5); +signal iu3_parity_tag_cacheline : std_ulogic_vector(0 to 5); +signal reload_cacheline : std_ulogic_vector(0 to 5); +signal ecc_inval_cacheline : std_ulogic_vector(0 to 5); +signal lru_write_cacheline : std_ulogic_vector(0 to 5); +signal iu3_any_parity_err_way : std_ulogic_vector(0 to 3); +signal dir_row0_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row0_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row0_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row1_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row1_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row1_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row2_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row2_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row2_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row3_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row3_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row3_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row4_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row4_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row4_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row5_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row5_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row5_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row6_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row6_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row6_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row7_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row7_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row7_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row8_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row8_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row8_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row9_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row9_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row9_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row10_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row10_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row10_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row11_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row11_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row11_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row12_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row12_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row12_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row13_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row13_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row13_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row14_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row14_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row14_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row15_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row15_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row15_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row16_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row16_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row16_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row17_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row17_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row17_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row18_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row18_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row18_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row19_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row19_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row19_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row20_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row20_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row20_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row21_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row21_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row21_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row22_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row22_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row22_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row23_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row23_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row23_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row24_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row24_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row24_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row25_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row25_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row25_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row26_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row26_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row26_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row27_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row27_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row27_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row28_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row28_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row28_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row29_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row29_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row29_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row30_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row30_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row30_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row31_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row31_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row31_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row32_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row32_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row32_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row33_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row33_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row33_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row34_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row34_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row34_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row35_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row35_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row35_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row36_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row36_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row36_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row37_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row37_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row37_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row38_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row38_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row38_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row39_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row39_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row39_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row40_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row40_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row40_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row41_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row41_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row41_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row42_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row42_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row42_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row43_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row43_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row43_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row44_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row44_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row44_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row45_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row45_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row45_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row46_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row46_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row46_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row47_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row47_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row47_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row48_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row48_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row48_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row49_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row49_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row49_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row50_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row50_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row50_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row51_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row51_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row51_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row52_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row52_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row52_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row53_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row53_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row53_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row54_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row54_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row54_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row55_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row55_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row55_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row56_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row56_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row56_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row57_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row57_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row57_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row58_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row58_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row58_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row59_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row59_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row59_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row60_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row60_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row60_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row61_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row61_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row61_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row62_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row62_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row62_val_d_part2_b : std_ulogic_vector(0 to 3); +signal dir_row63_val_d_part1 : std_ulogic_vector(0 to 3); +signal dir_row63_val_d_part2a : std_ulogic_vector(0 to 3); +signal dir_row63_val_d_part2_b : std_ulogic_vector(0 to 3); +-- synopsys translate_off +-- synopsys translate_on +signal dir_row_val_even_act : std_ulogic; +signal dir_row_val_odd_act : std_ulogic; +-- Check multihit +signal iu2_multihit_err : std_ulogic; +signal iu3_multihit_err : std_ulogic; +signal iu2_pc_inj_icachedir_multihit : std_ulogic; +-- Check parity +signal ext_dir_dataout0 : std_ulogic_vector(0 to dir_parity_width*8-1); +signal gen_dir_parity_out0 : std_ulogic_vector(0 to dir_parity_width-1); +signal dir_parity_err_byte0 : std_ulogic_vector(0 to dir_parity_width-1); +signal ext_dir_dataout1 : std_ulogic_vector(0 to dir_parity_width*8-1); +signal gen_dir_parity_out1 : std_ulogic_vector(0 to dir_parity_width-1); +signal dir_parity_err_byte1 : std_ulogic_vector(0 to dir_parity_width-1); +signal ext_dir_dataout2 : std_ulogic_vector(0 to dir_parity_width*8-1); +signal gen_dir_parity_out2 : std_ulogic_vector(0 to dir_parity_width-1); +signal dir_parity_err_byte2 : std_ulogic_vector(0 to dir_parity_width-1); +signal ext_dir_dataout3 : std_ulogic_vector(0 to dir_parity_width*8-1); +signal gen_dir_parity_out3 : std_ulogic_vector(0 to dir_parity_width-1); +signal dir_parity_err_byte3 : std_ulogic_vector(0 to dir_parity_width-1); +signal dir_parity_err_way : std_ulogic_vector(0 to 3); +signal dir_parity_err : std_ulogic; +signal iu2_rd_parity_err : std_ulogic; +signal data_parity_out0 : std_ulogic_vector(0 to 17); +signal gen_data_parity_out0 : std_ulogic_vector(0 to 17); +signal data_parity_err_byte0 : std_ulogic_vector(0 to 17); +signal data_parity_out1 : std_ulogic_vector(0 to 17); +signal gen_data_parity_out1 : std_ulogic_vector(0 to 17); +signal data_parity_err_byte1 : std_ulogic_vector(0 to 17); +signal data_parity_out2 : std_ulogic_vector(0 to 17); +signal gen_data_parity_out2 : std_ulogic_vector(0 to 17); +signal data_parity_err_byte2 : std_ulogic_vector(0 to 17); +signal data_parity_out3 : std_ulogic_vector(0 to 17); +signal gen_data_parity_out3 : std_ulogic_vector(0 to 17); +signal data_parity_err_byte3 : std_ulogic_vector(0 to 17); +signal data_parity_err : std_ulogic; +signal iu3_parity_act : std_ulogic; +-- Update Valid Bit +signal lru_select : std_ulogic_vector(0 to 5); +signal return_lru : std_ulogic_vector(0 to 2); +signal return_val : std_ulogic_vector(0 to 3); +-- IU2 +signal iu2_rd_miss : std_ulogic; +signal iu3_rd_miss : std_ulogic; +signal iu2_miss_flush_prev : std_ulogic_vector(0 to 3); +signal load_iu2 : std_ulogic; +signal iu3_act : std_ulogic; +signal iu3_valid_next : std_ulogic; +signal iu2_erat_err : std_ulogic_vector(0 to 2); +signal iu2_data_dataout_0 : std_ulogic_vector(0 to 143); +signal iu2_data_dataout_1 : std_ulogic_vector(0 to 143); +signal iu2_data_dataout_2 : std_ulogic_vector(0 to 143); +signal iu2_data_dataout_3 : std_ulogic_vector(0 to 143); +signal iu3_instr0_buf : std_ulogic_vector(0 to 35); +signal iu3_instr1_buf : std_ulogic_vector(0 to 35); +signal iu3_instr2_buf : std_ulogic_vector(0 to 35); +signal iu3_instr3_buf : std_ulogic_vector(0 to 35); +signal iu2_ifar_dec : std_ulogic_vector(0 to 3); +-- IU3 +signal uc_illegal : std_ulogic; +signal xnop : std_ulogic_vector(0 to 35); +signal int_ic_bp_iu3_error : std_ulogic_vector(0 to 2); +signal iu3_0_instr_rot : std_ulogic_vector(0 to 35); +signal iu3_1_instr_rot : std_ulogic_vector(0 to 35); +signal iu3_2_instr_rot : std_ulogic_vector(0 to 35); +signal iu3_3_instr_rot : std_ulogic_vector(0 to 35); +signal int_ic_bp_iu3_flush : std_ulogic; +-- Performance Events +signal iu2_instr_count : std_ulogic_vector(0 to 2); +signal perf_instr_count_t0_new: std_ulogic_vector(0 to 2); +signal perf_instr_count_t1_new: std_ulogic_vector(0 to 2); +signal perf_instr_count_t2_new: std_ulogic_vector(0 to 2); +signal perf_instr_count_t3_new: std_ulogic_vector(0 to 2); +-- abist +signal stage_abist_g8t_wenb : std_ulogic; +signal stage_abist_g8t1p_renb_0 : std_ulogic; +signal stage_abist_di_0 : std_ulogic_vector(0 to 3); +signal stage_abist_g8t_bw_1 : std_ulogic; +signal stage_abist_g8t_bw_0 : std_ulogic; +signal stage_abist_waddr_0 : std_ulogic_vector(4 to 9); +signal stage_abist_raddr_0 : std_ulogic_vector(2 to 9); +signal stage_abist_wl64_comp_ena : std_ulogic; +signal stage_abist_g8t_dcomp : std_ulogic_vector(0 to 3); +signal stage_abist_g6t_bw : std_ulogic_vector(0 to 1); +signal stage_abist_di_g6t_2r : std_ulogic_vector(0 to 3); +signal stage_abist_wl256_comp_ena : std_ulogic; +signal stage_abist_dcomp_g6t_2r : std_ulogic_vector(0 to 3); +signal stage_abist_g6t_r_wb : std_ulogic; +-- scan +signal siv : std_ulogic_vector(0 to scan_right); +signal sov : std_ulogic_vector(0 to scan_right); +signal abst_siv : std_ulogic_vector(0 to 42); +signal abst_sov : std_ulogic_vector(0 to 42); +signal time_siv : std_ulogic_vector(0 to 2); +signal time_sov : std_ulogic_vector(0 to 2); +signal repr_siv : std_ulogic_vector(0 to 2); +signal repr_sov : std_ulogic_vector(0 to 2); +signal repr_slat_sl_thold_0_b : std_ulogic; +signal time_slat_sl_thold_0_b : std_ulogic; +-- synopsys translate_off +-- synopsys translate_on + BEGIN --@@ START OF EXECUTABLE CODE FOR IUQ_IC_DIR + +tidn <= '0'; +tiup <= '1'; +ZEROS <= (others => '0'); +spr_ic_cls_d <= spr_ic_cls; +spr_ic_idir_way_d <= spr_ic_idir_way; +xu_iu_ici_d <= xu_iu_ici; +----------------------------------------------------------------------- +-- IU1 Latches +----------------------------------------------------------------------- +iu1_valid_d <= ics_icd_iu0_valid; +iu1_tid_d <= ics_icd_iu0_tid; +iu1_ifar_d <= ics_icd_iu0_ifar; +iu1_inval_d <= ics_icd_iu0_inval; +iu1_2ucode_d <= ics_icd_iu0_2ucode; +iu1_2ucode_type_d <= ics_icd_iu0_2ucode_type; +iu1_spr_idir_read_d <= ics_icd_iu0_spr_idir_read; +icd_ics_iu1_valid <= iu1_valid_l2; +icd_ics_iu1_tid <= iu1_tid_l2; +icd_ics_iu1_ifar <= iu1_ifar_l2; +icd_ics_iu1_2ucode <= iu1_2ucode_l2; +icd_ics_iu1_2ucode_type <= iu1_2ucode_type_l2; +iu_ierat_iu1_back_inv <= iu1_inval_l2; +----------------------------------------------------------------------- +-- ERAT Output +----------------------------------------------------------------------- +iu2_ci <= ierat_iu_iu2_wimge(1); +iu2_endian <= ierat_iu_iu2_wimge(4); +iu2_ifar_eff_d <= iu1_ifar_l2; +----------------------------------------------------------------------- +-- Access IDIR, Valid, & LRU +----------------------------------------------------------------------- +dir_rd_act <= ics_icd_dir_rd_act; +dir_write <= icm_icd_dir_write; +dir_way <= icm_icd_dir_write_way; +dir_wr_addr <= icm_icd_dir_write_addr(52 to 56) & (icm_icd_dir_write_addr(57) and not spr_ic_cls_l2); +dir_rd_addr <= ics_icd_iu0_ifar(52 to 56) & + (ics_icd_iu0_ifar(57) and not (spr_ic_cls_l2 and not ics_icd_iu0_spr_idir_read)); +calc_ext_dir_data: for i in ext_dir_datain'range generate +begin + R0:if(i < 52-REAL_IFAR'left) generate begin ext_dir_datain(i) <= icm_icd_dir_write_addr(REAL_IFAR'left+i); +end generate; +R1:if(i = 52-REAL_IFAR'left) generate +begin ext_dir_datain(i) <= icm_icd_dir_write_endian; +end generate; +R2:if(i > 52-REAL_IFAR'left) generate +begin ext_dir_datain(i) <= '0'; +end generate; +end generate; +gen_dir_parity: for i in dir_parity_in'range generate +begin + dir_parity_in(i) <= xor_reduce( ext_dir_datain(i*8 to i*8+7) ); +end generate; +way_datain(0 TO 52-REAL_IFAR'left-1) <= icm_icd_dir_write_addr(REAL_IFAR'left to 51); +way_datain(52-REAL_IFAR'left) <= icm_icd_dir_write_endian; +way_datain(52-REAL_IFAR'left+1 TO 52-REAL_IFAR'left+1+dir_parity_width-1) <= dir_parity_in; +ext: if (dir_way_width < way_datain'length) generate +way_datain(52-REAL_IFAR'left+1+dir_parity_width TO way_datain'right) <= (others => '0'); +end generate; +-- Reverse bit ordering to get rid of wiring bowtie +way_datain_rev <= reverse(way_datain); +dir_datain_rev <= way_datain_rev & way_datain_rev & way_datain_rev & way_datain_rev; +-- Only need 35 bits per way - array has extra bits +-- 0:29 - tag, 30 - endianness, 31:34 - parity +idir: entity tri.tri_64x36_4w_1r1w(tri_64x36_4w_1r1w) + generic map ( expand_type => expand_type ) + port map( + gnd => gnd, + vdd => vdd, + vcs => vcs, + nclk => nclk, + rd_act => dir_rd_act, + wr_act => dir_write, + sg_0 => pc_iu_sg_0, + abst_sl_thold_0 => pc_iu_abst_slp_sl_thold_0, + ary_nsl_thold_0 => pc_iu_ary_slp_nsl_thold_0, + time_sl_thold_0 => pc_iu_time_sl_thold_0, + repr_sl_thold_0 => pc_iu_repr_sl_thold_0, + clkoff_dc_b => g8t_clkoff_b, + ccflush_dc => tc_ac_ccflush_dc, + scan_dis_dc_b => an_ac_scan_dis_dc_b, + scan_diag_dc => an_ac_scan_diag_dc, + d_mode_dc => g8t_d_mode, + mpw1_dc_b => g8t_mpw1_b, + mpw2_dc_b => g8t_mpw2_b, + delay_lclkr_dc => g8t_delay_lclkr, + wr_abst_act => stage_abist_g8t_wenb, + rd0_abst_act => stage_abist_g8t1p_renb_0, + abist_di => stage_abist_di_0, + abist_bw_odd => stage_abist_g8t_bw_1, + abist_bw_even => stage_abist_g8t_bw_0, + abist_wr_adr => stage_abist_waddr_0(4 to 9), + abist_rd0_adr => stage_abist_raddr_0(4 to 9), + tc_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc, + abist_ena_1 => pc_iu_abist_ena_dc, + abist_g8t_rd0_comp_ena => stage_abist_wl64_comp_ena, + abist_raw_dc_b => pc_iu_abist_raw_dc_b, + obs0_abist_cmp => stage_abist_g8t_dcomp, + abst_scan_in(0) => abst_siv(0), + abst_scan_in(1) => abst_siv(2), + time_scan_in => time_siv(0), + repr_scan_in => repr_siv(0), + abst_scan_out(0) => abst_sov(0), + abst_scan_out(1) => abst_sov(2), + time_scan_out => time_sov(0), + repr_scan_out => repr_sov(0), + lcb_bolt_sl_thold_0 => pc_iu_bolt_sl_thold_0, + pc_bo_enable_2 => pc_iu_bo_enable_2, + pc_bo_reset => pc_iu_bo_reset, + pc_bo_unload => pc_iu_bo_unload, + pc_bo_repair => pc_iu_bo_repair, + pc_bo_shdata => pc_iu_bo_shdata, + pc_bo_select => pc_iu_bo_select(0 to 1), + bo_pc_failout => iu_pc_bo_fail(0 to 1), + bo_pc_diagloop => iu_pc_bo_diagout(0 to 1), + tri_lcb_mpw1_dc_b => mpw1_b, + tri_lcb_mpw2_dc_b => mpw2_b, + tri_lcb_delay_lclkr_dc => delay_lclkr, + tri_lcb_clkoff_dc_b => clkoff_b, + tri_lcb_act_dis_dc => act_dis, + wr_way => dir_way, + wr_addr => dir_wr_addr, + data_in => dir_datain_rev, + rd_addr => dir_rd_addr, + data_out => dir_dataout_rev +); +dir_dataout(0 TO dir_array_way_width-1) <= reverse(dir_dataout_rev( 0 to dir_array_way_width-1)); +dir_dataout(dir_array_way_width TO 2*dir_array_way_width-1) <= reverse(dir_dataout_rev( dir_array_way_width to 2*dir_array_way_width-1)); +dir_dataout(2*dir_array_way_width TO 3*dir_array_way_width-1) <= reverse(dir_dataout_rev(2*dir_array_way_width to 3*dir_array_way_width-1)); +dir_dataout(3*dir_array_way_width TO 4*dir_array_way_width-1) <= reverse(dir_dataout_rev(3*dir_array_way_width to 4*dir_array_way_width-1)); +dir_dataout_act <= iu1_valid_l2 or iu1_inval_l2 or iu1_spr_idir_read_l2; +iu2_dir_dataout_0_d(REAL_IFAR'left) <= dir_dataout(0) xor pc_iu_inj_icachedir_parity; +iu2_dir_dataout_0_d(REAL_IFAR'left+1 TO iu2_dir_dataout_0_d'right) <= dir_dataout( 1 to dir_way_width-dir_parity_width-1); +iu2_dir_dataout_1_d(REAL_IFAR'left TO iu2_dir_dataout_1_d'right) <= dir_dataout( dir_array_way_width to dir_array_way_width+dir_way_width-dir_parity_width-1); +iu2_dir_dataout_2_d(REAL_IFAR'left TO iu2_dir_dataout_1_d'right) <= dir_dataout(2*dir_array_way_width to 2*dir_array_way_width+dir_way_width-dir_parity_width-1); +iu2_dir_dataout_3_d(REAL_IFAR'left TO iu2_dir_dataout_1_d'right) <= dir_dataout(3*dir_array_way_width to 3*dir_array_way_width+dir_way_width-dir_parity_width-1); +ext_iu2_dir_dataout: if (REAL_IFAR'left > 22) generate +begin + iu2_dir_dataout_0_d(22 TO REAL_IFAR'left-1) <= (others => '0'); +iu2_dir_dataout_1_d(22 TO REAL_IFAR'left-1) <= (others => '0'); +iu2_dir_dataout_2_d(22 TO REAL_IFAR'left-1) <= (others => '0'); +iu2_dir_dataout_3_d(22 TO REAL_IFAR'left-1) <= (others => '0'); +end generate; +-- Parity +iu2_dir_dataout_0_par_d <= dir_dataout( dir_way_width-dir_parity_width to dir_way_width-1); +iu2_dir_dataout_1_par_d <= dir_dataout( dir_array_way_width+dir_way_width-dir_parity_width to dir_array_way_width+dir_way_width-1); +iu2_dir_dataout_2_par_d <= dir_dataout(2*dir_array_way_width+dir_way_width-dir_parity_width to 2*dir_array_way_width+dir_way_width-1); +iu2_dir_dataout_3_par_d <= dir_dataout(3*dir_array_way_width+dir_way_width-dir_parity_width to 3*dir_array_way_width+dir_way_width-1); +-- Muxing the val for directory access +iu1_ifar_cacheline <= iu1_ifar_l2(52 to 56) & + (iu1_ifar_l2(57) and not (spr_ic_cls_l2 and not iu1_spr_idir_read_l2)); +with iu1_ifar_cacheline select +dir_rd_val <= dir_row0_val_l2 when "000000", + dir_row1_val_l2 when "000001", + dir_row2_val_l2 when "000010", + dir_row3_val_l2 when "000011", + dir_row4_val_l2 when "000100", + dir_row5_val_l2 when "000101", + dir_row6_val_l2 when "000110", + dir_row7_val_l2 when "000111", + dir_row8_val_l2 when "001000", + dir_row9_val_l2 when "001001", + dir_row10_val_l2 when "001010", + dir_row11_val_l2 when "001011", + dir_row12_val_l2 when "001100", + dir_row13_val_l2 when "001101", + dir_row14_val_l2 when "001110", + dir_row15_val_l2 when "001111", + dir_row16_val_l2 when "010000", + dir_row17_val_l2 when "010001", + dir_row18_val_l2 when "010010", + dir_row19_val_l2 when "010011", + dir_row20_val_l2 when "010100", + dir_row21_val_l2 when "010101", + dir_row22_val_l2 when "010110", + dir_row23_val_l2 when "010111", + dir_row24_val_l2 when "011000", + dir_row25_val_l2 when "011001", + dir_row26_val_l2 when "011010", + dir_row27_val_l2 when "011011", + dir_row28_val_l2 when "011100", + dir_row29_val_l2 when "011101", + dir_row30_val_l2 when "011110", + dir_row31_val_l2 when "011111", + dir_row32_val_l2 when "100000", + dir_row33_val_l2 when "100001", + dir_row34_val_l2 when "100010", + dir_row35_val_l2 when "100011", + dir_row36_val_l2 when "100100", + dir_row37_val_l2 when "100101", + dir_row38_val_l2 when "100110", + dir_row39_val_l2 when "100111", + dir_row40_val_l2 when "101000", + dir_row41_val_l2 when "101001", + dir_row42_val_l2 when "101010", + dir_row43_val_l2 when "101011", + dir_row44_val_l2 when "101100", + dir_row45_val_l2 when "101101", + dir_row46_val_l2 when "101110", + dir_row47_val_l2 when "101111", + dir_row48_val_l2 when "110000", + dir_row49_val_l2 when "110001", + dir_row50_val_l2 when "110010", + dir_row51_val_l2 when "110011", + dir_row52_val_l2 when "110100", + dir_row53_val_l2 when "110101", + dir_row54_val_l2 when "110110", + dir_row55_val_l2 when "110111", + dir_row56_val_l2 when "111000", + dir_row57_val_l2 when "111001", + dir_row58_val_l2 when "111010", + dir_row59_val_l2 when "111011", + dir_row60_val_l2 when "111100", + dir_row61_val_l2 when "111101", + dir_row62_val_l2 when "111110", + dir_row63_val_l2 when "111111", + "0000" when others; +iu2_dir_rd_val_d <= dir_rd_val; +with spr_ic_idir_way_l2 select +ic_spr_idir_valid <= iu2_dir_rd_val_l2(0) when "00", + iu2_dir_rd_val_l2(1) when "01", + iu2_dir_rd_val_l2(2) when "10", + iu2_dir_rd_val_l2(3) when others; + WITH s6'(iu1_ifar_l2(52 to 57)) SELECT iu2_spr_idir_lru_d <= dir_row0_lru_l2 when "000000", + dir_row1_lru_l2 when "000001", + dir_row2_lru_l2 when "000010", + dir_row3_lru_l2 when "000011", + dir_row4_lru_l2 when "000100", + dir_row5_lru_l2 when "000101", + dir_row6_lru_l2 when "000110", + dir_row7_lru_l2 when "000111", + dir_row8_lru_l2 when "001000", + dir_row9_lru_l2 when "001001", + dir_row10_lru_l2 when "001010", + dir_row11_lru_l2 when "001011", + dir_row12_lru_l2 when "001100", + dir_row13_lru_l2 when "001101", + dir_row14_lru_l2 when "001110", + dir_row15_lru_l2 when "001111", + dir_row16_lru_l2 when "010000", + dir_row17_lru_l2 when "010001", + dir_row18_lru_l2 when "010010", + dir_row19_lru_l2 when "010011", + dir_row20_lru_l2 when "010100", + dir_row21_lru_l2 when "010101", + dir_row22_lru_l2 when "010110", + dir_row23_lru_l2 when "010111", + dir_row24_lru_l2 when "011000", + dir_row25_lru_l2 when "011001", + dir_row26_lru_l2 when "011010", + dir_row27_lru_l2 when "011011", + dir_row28_lru_l2 when "011100", + dir_row29_lru_l2 when "011101", + dir_row30_lru_l2 when "011110", + dir_row31_lru_l2 when "011111", + dir_row32_lru_l2 when "100000", + dir_row33_lru_l2 when "100001", + dir_row34_lru_l2 when "100010", + dir_row35_lru_l2 when "100011", + dir_row36_lru_l2 when "100100", + dir_row37_lru_l2 when "100101", + dir_row38_lru_l2 when "100110", + dir_row39_lru_l2 when "100111", + dir_row40_lru_l2 when "101000", + dir_row41_lru_l2 when "101001", + dir_row42_lru_l2 when "101010", + dir_row43_lru_l2 when "101011", + dir_row44_lru_l2 when "101100", + dir_row45_lru_l2 when "101101", + dir_row46_lru_l2 when "101110", + dir_row47_lru_l2 when "101111", + dir_row48_lru_l2 when "110000", + dir_row49_lru_l2 when "110001", + dir_row50_lru_l2 when "110010", + dir_row51_lru_l2 when "110011", + dir_row52_lru_l2 when "110100", + dir_row53_lru_l2 when "110101", + dir_row54_lru_l2 when "110110", + dir_row55_lru_l2 when "110111", + dir_row56_lru_l2 when "111000", + dir_row57_lru_l2 when "111001", + dir_row58_lru_l2 when "111010", + dir_row59_lru_l2 when "111011", + dir_row60_lru_l2 when "111100", + dir_row61_lru_l2 when "111101", + dir_row62_lru_l2 when "111110", + dir_row63_lru_l2 when others; +ic_spr_idir_lru <= iu2_spr_idir_lru_l2; +with spr_ic_idir_way_l2 select +ic_spr_idir_tag <= iu2_dir_dataout_0_noncmp(22 to 51) when "00", + iu2_dir_dataout_1_noncmp(22 to 51) when "01", + iu2_dir_dataout_2_noncmp(22 to 51) when "10", + iu2_dir_dataout_3_noncmp(22 to 51) when others; +with spr_ic_idir_way_l2 select +ic_spr_idir_endian <= iu2_dir_dataout_0_noncmp(52) when "00", + iu2_dir_dataout_1_noncmp(52) when "01", + iu2_dir_dataout_2_noncmp(52) when "10", + iu2_dir_dataout_3_noncmp(52) when others; +with spr_ic_idir_way_l2 select +ic_spr_idir_parity(0 to dir_parity_width-1) <= iu2_dir_dataout_0_par_l2 when "00", + iu2_dir_dataout_1_par_l2 when "01", + iu2_dir_dataout_2_par_l2 when "10", + iu2_dir_dataout_3_par_l2 when others; +ext_spr_parity: if (dir_parity_width < 4) generate +begin ic_spr_idir_parity(dir_parity_width TO 3) <= (others => '0'); +end generate; +ic_spr_idir_done <= iu2_spr_idir_read_l2; +----------------------------------------------------------------------- +-- Access IData +----------------------------------------------------------------------- +data_write <= icm_icd_data_write; +data_way <= icm_icd_reload_way; +data_addr <= icm_icd_reload_addr(52 to 59) when data_write = '1' + else ics_icd_iu0_ifar(52 to 59); +data_parity_in <= icm_icd_reload_data(144 to 161); +data_datain <= icm_icd_reload_data(0 to 143) & data_parity_in; +idata: entity tri.tri_256x162_4w_0(tri_256x162_4w_0) + generic map ( expand_type => expand_type ) + port map( + gnd => gnd, + vdd => vdd, + vcs => vcs, + nclk => nclk, + ccflush_dc => tc_ac_ccflush_dc, + lcb_clkoff_dc_b => g6t_clkoff_b, + lcb_d_mode_dc => g6t_d_mode, + lcb_act_dis_dc => g6t_act_dis, + lcb_ary_nsl_thold_0 => pc_iu_ary_nsl_thold_0, + lcb_sg_1 => pc_iu_sg_1, + lcb_abst_sl_thold_0 => pc_iu_abst_sl_thold_0, + scan_diag_dc => an_ac_scan_diag_dc, + scan_dis_dc_b => an_ac_scan_dis_dc_b, + abst_scan_in(0) => abst_siv(1), + abst_scan_in(1) => abst_siv(3), + abst_scan_out(0) => abst_sov(1), + abst_scan_out(1) => abst_sov(3), + lcb_delay_lclkr_np_dc => g6t_delay_lclkr(0), + ctrl_lcb_delay_lclkr_np_dc => g6t_delay_lclkr(1), + dibw_lcb_delay_lclkr_np_dc => g6t_delay_lclkr(2), + ctrl_lcb_mpw1_np_dc_b => g6t_mpw1_b(0), + dibw_lcb_mpw1_np_dc_b => g6t_mpw1_b(1), + lcb_mpw1_pp_dc_b => g6t_mpw1_b(2), + lcb_mpw1_2_pp_dc_b => g6t_mpw1_b(3), + aodo_lcb_delay_lclkr_dc => g6t_delay_lclkr(3), + aodo_lcb_mpw1_dc_b => g6t_mpw1_b(4), + aodo_lcb_mpw2_dc_b => g6t_mpw2_b, + lcb_time_sg_0 => pc_iu_sg_0, + lcb_time_sl_thold_0 => pc_iu_time_sl_thold_0, + time_scan_in => time_siv(1), + time_scan_out => time_sov(1), + bitw_abist => stage_abist_g6t_bw, + lcb_repr_sl_thold_0 => pc_iu_repr_sl_thold_0, + lcb_repr_sg_0 => pc_iu_sg_0, + repr_scan_in => repr_siv(1), + repr_scan_out => repr_sov(1), + tc_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc, + abist_en_1 => pc_iu_abist_ena_dc, + din_abist => stage_abist_di_g6t_2r, + abist_cmp_en => stage_abist_wl256_comp_ena, + abist_raw_b_dc => pc_iu_abist_raw_dc_b, + data_cmp_abist => stage_abist_dcomp_g6t_2r, + addr_abist => stage_abist_raddr_0(2 to 9), + r_wb_abist => stage_abist_g6t_r_wb, + write_thru_en_dc => tidn, + lcb_bolt_sl_thold_0 => pc_iu_bolt_sl_thold_0, + pc_bo_enable_2 => pc_iu_bo_enable_2, + pc_bo_reset => pc_iu_bo_reset, + pc_bo_unload => pc_iu_bo_unload, + pc_bo_repair => pc_iu_bo_repair, + pc_bo_shdata => pc_iu_bo_shdata, + pc_bo_select => pc_iu_bo_select(2 to 3), + bo_pc_failout => iu_pc_bo_fail(2 to 3), + bo_pc_diagloop => iu_pc_bo_diagout(2 to 3), + tri_lcb_mpw1_dc_b => mpw1_b, + tri_lcb_mpw2_dc_b => mpw2_b, + tri_lcb_delay_lclkr_dc => delay_lclkr, + tri_lcb_clkoff_dc_b => clkoff_b, + tri_lcb_act_dis_dc => act_dis, + read_act => ics_icd_data_rd_act, + write_enable => data_write, + write_way => data_way, + addr => data_addr, + data_in => data_datain, + data_out => data_dataout +); +iu2_data_dataout_d <= data_dataout; +data_dataout_inj(0) <= iu2_data_dataout_l2(0) xor pc_iu_inj_icache_parity; +data_dataout_inj(1 TO data_dataout'right) <= iu2_data_dataout_l2(1 to data_dataout'right); +dircmp: entity work.iuq_ic_dir_cmp(iuq_ic_dir_cmp) + generic map ( expand_type => expand_type ) + port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + forcee => funcslp_force, + sg_0 => pc_iu_sg_0, + thold_0_b => pc_iu_func_slp_sl_thold_0_b, + scan_in => siv(iu2_dir_dataout_offset), + scan_out => sov(iu2_dir_dataout_offset), + dir_dataout_act => dir_dataout_act , + iu2_endian => iu2_endian , + ierat_iu_iu2_rpn(22 to 51) => ierat_iu_iu2_rpn(22 to 51) , + iu2_dir_dataout_0_d(22 to 52) => iu2_dir_dataout_0_d(22 to 52) , + iu2_dir_dataout_1_d(22 to 52) => iu2_dir_dataout_1_d(22 to 52) , + iu2_dir_dataout_2_d(22 to 52) => iu2_dir_dataout_2_d(22 to 52) , + iu2_dir_dataout_3_d(22 to 52) => iu2_dir_dataout_3_d(22 to 52) , + ierat_iu_iu2_rpn_noncmp(22 to 51) => ierat_iu_iu2_rpn_noncmp(22 to 51) , + iu2_dir_dataout_0_noncmp(22 to 52) => iu2_dir_dataout_0_noncmp(22 to 52) , + iu2_dir_dataout_1_noncmp(22 to 52) => iu2_dir_dataout_1_noncmp(22 to 52) , + iu2_dir_dataout_2_noncmp(22 to 52) => iu2_dir_dataout_2_noncmp(22 to 52) , + iu2_dir_dataout_3_noncmp(22 to 52) => iu2_dir_dataout_3_noncmp(22 to 52) , + iu2_dir_rd_val(0 to 3) => iu2_dir_rd_val_l2(0 to 3) , + iu2_rd_way_tag_hit(0 to 3) => iu2_rd_way_tag_hit(0 to 3) , + iu2_rd_way_hit(0 to 3) => iu2_rd_way_hit(0 to 3) , + iu2_rd_way_hit_insmux_b(0 to 3) => iu2_rd_way_hit_insmux_b(0 to 3) ); +iu2_dir_miss <= not or_reduce(iu2_rd_way_hit); +iu2_valid_d <= iu1_valid_l2 and or_reduce(iu1_tid_l2 and not ics_icd_iu1_flush_tid and not ics_icd_all_flush_prev); +iu2_valid <= iu2_valid_l2 and or_reduce(iu2_tid_l2 and not ics_icd_all_flush_prev and not iu2_miss_flush_prev); +iu2_tid_d <= iu1_tid_l2; +iu2_2ucode_d <= iu1_2ucode_l2; +iu2_2ucode_type_d <= iu1_2ucode_type_l2; +iu2_inval_d <= iu1_inval_l2; +iu2_spr_idir_read_d <= iu1_spr_idir_read_l2; +----------------------------------------------------------------------- +-- Check Multihit +----------------------------------------------------------------------- +-- Set if more than 1 way matches (not 0000, 0001, 0010, 0100, 1000) +iu2_multihit_err <= (iu2_valid or iu2_inval_l2 or iu2_spr_idir_read_l2) and + not (( iu2_rd_way_hit(0 to 2) = "000") or + ((iu2_rd_way_hit(0 to 1) & iu2_rd_way_hit(3)) = "000") or + ((iu2_rd_way_hit(0) & iu2_rd_way_hit(2 to 3)) = "000") or + ( iu2_rd_way_hit(1 to 3) = "000")); +iu2_pc_inj_icachedir_multihit <= (iu2_valid or iu2_inval_l2 or iu2_spr_idir_read_l2) and pc_iu_inj_icachedir_multihit and not iu2_dir_miss; +iu3_multihit_err_way_d <= gate_and(iu2_multihit_err, iu2_rd_way_hit) or + (iu2_pc_inj_icachedir_multihit & iu2_pc_inj_icachedir_multihit & iu2_pc_inj_icachedir_multihit & iu2_pc_inj_icachedir_multihit); +iu3_multihit_err <= or_reduce(iu3_multihit_err_way_l2); +iu3_multihit_flush_d <= (iu2_multihit_err or (pc_iu_inj_icachedir_multihit and not iu2_dir_miss)) and (iu2_valid and or_reduce(iu2_tid_l2 and not ics_icd_iu2_flush_tid) and not iu2_ci); +err_icachedir_multihit: tri_direct_err_rpt + generic map (width => 1, expand_type => expand_type) + port map ( + vd => vdd, + gd => gnd, + err_in(0) => iu3_multihit_err, + err_out(0) => iu_pc_err_icachedir_multihit + ); +----------------------------------------------------------------------- +-- Check Parity +----------------------------------------------------------------------- +calc_ext_dir_dataout0: for i in ext_dir_datain'range generate +begin + R0:if(i < 52-REAL_IFAR'left+1) generate begin ext_dir_dataout0(i) <= iu2_dir_dataout_0_noncmp(REAL_IFAR'left+i); +end generate; +R1:if(i >= 52-REAL_IFAR'left+1) generate +begin ext_dir_dataout0(i) <= '0'; +end generate; +end generate; +chk_dir_parity0: for i in dir_parity_in'range generate +begin + gen_dir_parity_out0(i) <= xor_reduce( ext_dir_dataout0(i*8 to i*8+7) ); +end generate; +dir_parity_err_byte0 <= iu2_dir_dataout_0_par_l2 xor gen_dir_parity_out0; +dir_parity_err_way(0) <= or_reduce(dir_parity_err_byte0) and iu2_dir_rd_val_l2(0) and (iu2_valid or iu2_inval_l2 or iu2_spr_idir_read_l2); +calc_ext_dir_dataout1: for i in ext_dir_datain'range generate +begin + R0:if(i < 52-REAL_IFAR'left+1) generate begin ext_dir_dataout1(i) <= iu2_dir_dataout_1_noncmp(REAL_IFAR'left+i); +end generate; +R1:if(i >= 52-REAL_IFAR'left+1) generate +begin ext_dir_dataout1(i) <= '0'; +end generate; +end generate; +chk_dir_parity1: for i in dir_parity_in'range generate +begin + gen_dir_parity_out1(i) <= xor_reduce( ext_dir_dataout1(i*8 to i*8+7) ); +end generate; +dir_parity_err_byte1 <= iu2_dir_dataout_1_par_l2 xor gen_dir_parity_out1; +dir_parity_err_way(1) <= or_reduce(dir_parity_err_byte1) and iu2_dir_rd_val_l2(1) and (iu2_valid or iu2_inval_l2 or iu2_spr_idir_read_l2); +calc_ext_dir_dataout2: for i in ext_dir_datain'range generate +begin + R0:if(i < 52-REAL_IFAR'left+1) generate begin ext_dir_dataout2(i) <= iu2_dir_dataout_2_noncmp(REAL_IFAR'left+i); +end generate; +R1:if(i >= 52-REAL_IFAR'left+1) generate +begin ext_dir_dataout2(i) <= '0'; +end generate; +end generate; +chk_dir_parity2: for i in dir_parity_in'range generate +begin + gen_dir_parity_out2(i) <= xor_reduce( ext_dir_dataout2(i*8 to i*8+7) ); +end generate; +dir_parity_err_byte2 <= iu2_dir_dataout_2_par_l2 xor gen_dir_parity_out2; +dir_parity_err_way(2) <= or_reduce(dir_parity_err_byte2) and iu2_dir_rd_val_l2(2) and (iu2_valid or iu2_inval_l2 or iu2_spr_idir_read_l2); +calc_ext_dir_dataout3: for i in ext_dir_datain'range generate +begin + R0:if(i < 52-REAL_IFAR'left+1) generate begin ext_dir_dataout3(i) <= iu2_dir_dataout_3_noncmp(REAL_IFAR'left+i); +end generate; +R1:if(i >= 52-REAL_IFAR'left+1) generate +begin ext_dir_dataout3(i) <= '0'; +end generate; +end generate; +chk_dir_parity3: for i in dir_parity_in'range generate +begin + gen_dir_parity_out3(i) <= xor_reduce( ext_dir_dataout3(i*8 to i*8+7) ); +end generate; +dir_parity_err_byte3 <= iu2_dir_dataout_3_par_l2 xor gen_dir_parity_out3; +dir_parity_err_way(3) <= or_reduce(dir_parity_err_byte3) and iu2_dir_rd_val_l2(3) and (iu2_valid or iu2_inval_l2 or iu2_spr_idir_read_l2); +iu3_dir_parity_err_way_d <= dir_parity_err_way; +dir_parity_err <= or_reduce(dir_parity_err_way); +iu2_rd_parity_err <= or_reduce(dir_parity_err_way and iu2_rd_way_hit); +err_icachedir_parity_d <= dir_parity_err; +err_icachedir_parity: tri_direct_err_rpt + generic map (width => 1, expand_type => expand_type) + port map ( + vd => vdd, + gd => gnd, + err_in(0) => err_icachedir_parity_l2, + err_out(0) => iu_pc_err_icachedir_parity + ); +--Data +data_parity_out0 <= data_dataout_inj(144 to 144+data_parity_in'length-1); +chk_data_parity0: for i in data_parity_in'range generate +begin + gen_data_parity_out0(i) <= xor_reduce( data_dataout_inj(0+i*8 to 0+i*8+7) ); +end generate; +data_parity_err_byte0 <= data_parity_out0 xor gen_data_parity_out0; +iu3_data_parity_err_way_d(0) <= or_reduce(data_parity_err_byte0) and iu2_dir_rd_val_l2(0) and iu2_valid_l2; +data_parity_out1 <= data_dataout_inj(306 to 306+data_parity_in'length-1); +chk_data_parity1: for i in data_parity_in'range generate +begin + gen_data_parity_out1(i) <= xor_reduce( data_dataout_inj(162+i*8 to 162+i*8+7) ); +end generate; +data_parity_err_byte1 <= data_parity_out1 xor gen_data_parity_out1; +iu3_data_parity_err_way_d(1) <= or_reduce(data_parity_err_byte1) and iu2_dir_rd_val_l2(1) and iu2_valid_l2; +data_parity_out2 <= data_dataout_inj(468 to 468+data_parity_in'length-1); +chk_data_parity2: for i in data_parity_in'range generate +begin + gen_data_parity_out2(i) <= xor_reduce( data_dataout_inj(324+i*8 to 324+i*8+7) ); +end generate; +data_parity_err_byte2 <= data_parity_out2 xor gen_data_parity_out2; +iu3_data_parity_err_way_d(2) <= or_reduce(data_parity_err_byte2) and iu2_dir_rd_val_l2(2) and iu2_valid_l2; +data_parity_out3 <= data_dataout_inj(630 to 630+data_parity_in'length-1); +chk_data_parity3: for i in data_parity_in'range generate +begin + gen_data_parity_out3(i) <= xor_reduce( data_dataout_inj(486+i*8 to 486+i*8+7) ); +end generate; +data_parity_err_byte3 <= data_parity_out3 xor gen_data_parity_out3; +iu3_data_parity_err_way_d(3) <= or_reduce(data_parity_err_byte3) and iu2_dir_rd_val_l2(3) and iu2_valid_l2; +data_parity_err <= or_reduce(iu3_data_parity_err_way_l2); +err_icache_parity_d <= data_parity_err; +err_icache_parity: tri_direct_err_rpt + generic map (width => 1, expand_type => expand_type) + port map ( + vd => vdd, + gd => gnd, + err_in(0) => err_icache_parity_l2, + err_out(0) => iu_pc_err_icache_parity + ); +iu3_parity_needs_flush_d <= gate_and(iu2_valid and or_reduce(iu2_tid_l2 and not ics_icd_iu2_flush_tid) and not iu2_ci, iu2_rd_way_hit); +iu3_parity_needs_flush <= or_reduce(iu3_data_parity_err_way_l2 and iu3_parity_needs_flush_l2); +iu3_parity_flush_tid(0) <= iu3_tid_l2(0) and not ics_icd_all_flush_prev(0) and not iu3_erat_err_l2(0); +iu3_parity_flush_tid(1) <= iu3_tid_l2(1) and not ics_icd_all_flush_prev(1) and not iu3_erat_err_l2(0); +iu3_parity_flush_tid(2) <= iu3_tid_l2(2) and not ics_icd_all_flush_prev(2) and not iu3_erat_err_l2(0); +iu3_parity_flush_tid(3) <= iu3_tid_l2(3) and not ics_icd_all_flush_prev(3) and not iu3_erat_err_l2(0); +iu3_parity_flush <= (iu3_parity_needs_flush or iu3_rd_parity_err_l2 or iu3_multihit_flush_l2); +icd_ics_iu3_parity_flush <= gate_and(iu3_parity_flush, iu3_parity_flush_tid); +iu3_parity_tag_d <= iu2_ifar_eff_l2(52 to 57); +iu3_parity_act <= spr_ic_clockgate_dis or + (iu2_valid or iu2_inval_l2 or iu2_spr_idir_read_l2) or or_reduce(iu3_any_parity_err_way); +----------------------------------------------------------------------- +-- Update LRU +----------------------------------------------------------------------- +-- update LRU in IU2 on read hit or icm_icd_lru_write +dir_row0_lru_d <= dir_row0_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "000000")) = '1' + else dir_row0_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "000000") = '1' + else dir_row0_lru_l2; +dir_row1_lru_d <= dir_row1_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "000001")) = '1' + else dir_row1_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "000001") = '1' + else dir_row1_lru_l2; +dir_row2_lru_d <= dir_row2_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "000010")) = '1' + else dir_row2_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "000010") = '1' + else dir_row2_lru_l2; +dir_row3_lru_d <= dir_row3_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "000011")) = '1' + else dir_row3_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "000011") = '1' + else dir_row3_lru_l2; +dir_row4_lru_d <= dir_row4_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "000100")) = '1' + else dir_row4_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "000100") = '1' + else dir_row4_lru_l2; +dir_row5_lru_d <= dir_row5_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "000101")) = '1' + else dir_row5_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "000101") = '1' + else dir_row5_lru_l2; +dir_row6_lru_d <= dir_row6_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "000110")) = '1' + else dir_row6_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "000110") = '1' + else dir_row6_lru_l2; +dir_row7_lru_d <= dir_row7_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "000111")) = '1' + else dir_row7_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "000111") = '1' + else dir_row7_lru_l2; +dir_row8_lru_d <= dir_row8_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "001000")) = '1' + else dir_row8_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "001000") = '1' + else dir_row8_lru_l2; +dir_row9_lru_d <= dir_row9_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "001001")) = '1' + else dir_row9_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "001001") = '1' + else dir_row9_lru_l2; +dir_row10_lru_d <= dir_row10_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "001010")) = '1' + else dir_row10_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "001010") = '1' + else dir_row10_lru_l2; +dir_row11_lru_d <= dir_row11_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "001011")) = '1' + else dir_row11_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "001011") = '1' + else dir_row11_lru_l2; +dir_row12_lru_d <= dir_row12_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "001100")) = '1' + else dir_row12_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "001100") = '1' + else dir_row12_lru_l2; +dir_row13_lru_d <= dir_row13_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "001101")) = '1' + else dir_row13_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "001101") = '1' + else dir_row13_lru_l2; +dir_row14_lru_d <= dir_row14_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "001110")) = '1' + else dir_row14_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "001110") = '1' + else dir_row14_lru_l2; +dir_row15_lru_d <= dir_row15_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "001111")) = '1' + else dir_row15_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "001111") = '1' + else dir_row15_lru_l2; +dir_row16_lru_d <= dir_row16_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "010000")) = '1' + else dir_row16_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "010000") = '1' + else dir_row16_lru_l2; +dir_row17_lru_d <= dir_row17_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "010001")) = '1' + else dir_row17_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "010001") = '1' + else dir_row17_lru_l2; +dir_row18_lru_d <= dir_row18_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "010010")) = '1' + else dir_row18_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "010010") = '1' + else dir_row18_lru_l2; +dir_row19_lru_d <= dir_row19_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "010011")) = '1' + else dir_row19_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "010011") = '1' + else dir_row19_lru_l2; +dir_row20_lru_d <= dir_row20_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "010100")) = '1' + else dir_row20_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "010100") = '1' + else dir_row20_lru_l2; +dir_row21_lru_d <= dir_row21_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "010101")) = '1' + else dir_row21_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "010101") = '1' + else dir_row21_lru_l2; +dir_row22_lru_d <= dir_row22_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "010110")) = '1' + else dir_row22_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "010110") = '1' + else dir_row22_lru_l2; +dir_row23_lru_d <= dir_row23_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "010111")) = '1' + else dir_row23_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "010111") = '1' + else dir_row23_lru_l2; +dir_row24_lru_d <= dir_row24_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "011000")) = '1' + else dir_row24_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "011000") = '1' + else dir_row24_lru_l2; +dir_row25_lru_d <= dir_row25_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "011001")) = '1' + else dir_row25_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "011001") = '1' + else dir_row25_lru_l2; +dir_row26_lru_d <= dir_row26_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "011010")) = '1' + else dir_row26_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "011010") = '1' + else dir_row26_lru_l2; +dir_row27_lru_d <= dir_row27_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "011011")) = '1' + else dir_row27_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "011011") = '1' + else dir_row27_lru_l2; +dir_row28_lru_d <= dir_row28_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "011100")) = '1' + else dir_row28_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "011100") = '1' + else dir_row28_lru_l2; +dir_row29_lru_d <= dir_row29_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "011101")) = '1' + else dir_row29_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "011101") = '1' + else dir_row29_lru_l2; +dir_row30_lru_d <= dir_row30_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "011110")) = '1' + else dir_row30_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "011110") = '1' + else dir_row30_lru_l2; +dir_row31_lru_d <= dir_row31_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "011111")) = '1' + else dir_row31_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "011111") = '1' + else dir_row31_lru_l2; +dir_row32_lru_d <= dir_row32_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "100000")) = '1' + else dir_row32_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "100000") = '1' + else dir_row32_lru_l2; +dir_row33_lru_d <= dir_row33_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "100001")) = '1' + else dir_row33_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "100001") = '1' + else dir_row33_lru_l2; +dir_row34_lru_d <= dir_row34_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "100010")) = '1' + else dir_row34_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "100010") = '1' + else dir_row34_lru_l2; +dir_row35_lru_d <= dir_row35_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "100011")) = '1' + else dir_row35_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "100011") = '1' + else dir_row35_lru_l2; +dir_row36_lru_d <= dir_row36_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "100100")) = '1' + else dir_row36_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "100100") = '1' + else dir_row36_lru_l2; +dir_row37_lru_d <= dir_row37_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "100101")) = '1' + else dir_row37_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "100101") = '1' + else dir_row37_lru_l2; +dir_row38_lru_d <= dir_row38_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "100110")) = '1' + else dir_row38_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "100110") = '1' + else dir_row38_lru_l2; +dir_row39_lru_d <= dir_row39_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "100111")) = '1' + else dir_row39_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "100111") = '1' + else dir_row39_lru_l2; +dir_row40_lru_d <= dir_row40_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "101000")) = '1' + else dir_row40_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "101000") = '1' + else dir_row40_lru_l2; +dir_row41_lru_d <= dir_row41_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "101001")) = '1' + else dir_row41_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "101001") = '1' + else dir_row41_lru_l2; +dir_row42_lru_d <= dir_row42_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "101010")) = '1' + else dir_row42_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "101010") = '1' + else dir_row42_lru_l2; +dir_row43_lru_d <= dir_row43_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "101011")) = '1' + else dir_row43_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "101011") = '1' + else dir_row43_lru_l2; +dir_row44_lru_d <= dir_row44_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "101100")) = '1' + else dir_row44_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "101100") = '1' + else dir_row44_lru_l2; +dir_row45_lru_d <= dir_row45_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "101101")) = '1' + else dir_row45_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "101101") = '1' + else dir_row45_lru_l2; +dir_row46_lru_d <= dir_row46_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "101110")) = '1' + else dir_row46_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "101110") = '1' + else dir_row46_lru_l2; +dir_row47_lru_d <= dir_row47_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "101111")) = '1' + else dir_row47_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "101111") = '1' + else dir_row47_lru_l2; +dir_row48_lru_d <= dir_row48_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "110000")) = '1' + else dir_row48_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "110000") = '1' + else dir_row48_lru_l2; +dir_row49_lru_d <= dir_row49_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "110001")) = '1' + else dir_row49_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "110001") = '1' + else dir_row49_lru_l2; +dir_row50_lru_d <= dir_row50_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "110010")) = '1' + else dir_row50_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "110010") = '1' + else dir_row50_lru_l2; +dir_row51_lru_d <= dir_row51_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "110011")) = '1' + else dir_row51_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "110011") = '1' + else dir_row51_lru_l2; +dir_row52_lru_d <= dir_row52_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "110100")) = '1' + else dir_row52_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "110100") = '1' + else dir_row52_lru_l2; +dir_row53_lru_d <= dir_row53_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "110101")) = '1' + else dir_row53_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "110101") = '1' + else dir_row53_lru_l2; +dir_row54_lru_d <= dir_row54_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "110110")) = '1' + else dir_row54_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "110110") = '1' + else dir_row54_lru_l2; +dir_row55_lru_d <= dir_row55_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "110111")) = '1' + else dir_row55_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "110111") = '1' + else dir_row55_lru_l2; +dir_row56_lru_d <= dir_row56_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "111000")) = '1' + else dir_row56_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "111000") = '1' + else dir_row56_lru_l2; +dir_row57_lru_d <= dir_row57_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "111001")) = '1' + else dir_row57_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "111001") = '1' + else dir_row57_lru_l2; +dir_row58_lru_d <= dir_row58_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "111010")) = '1' + else dir_row58_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "111010") = '1' + else dir_row58_lru_l2; +dir_row59_lru_d <= dir_row59_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "111011")) = '1' + else dir_row59_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "111011") = '1' + else dir_row59_lru_l2; +dir_row60_lru_d <= dir_row60_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "111100")) = '1' + else dir_row60_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "111100") = '1' + else dir_row60_lru_l2; +dir_row61_lru_d <= dir_row61_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "111101")) = '1' + else dir_row61_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "111101") = '1' + else dir_row61_lru_l2; +dir_row62_lru_d <= dir_row62_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "111110")) = '1' + else dir_row62_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "111110") = '1' + else dir_row62_lru_l2; +dir_row63_lru_d <= dir_row63_lru_write when (icm_icd_lru_write and (lru_write_cacheline(0 to 5) = "111111")) = '1' + else dir_row63_lru_read when (iu2_lru_rd_update and iu2_ifar_eff_cacheline(0 to 5) = "111111") = '1' + else dir_row63_lru_l2; +dir_row_lru_even_act <= (icm_icd_lru_write and lru_write_cacheline(5) = '0') or + (iu2_valid_l2 and iu2_ifar_eff_cacheline(5) = '0'); +dir_row_lru_odd_act <= (icm_icd_lru_write and lru_write_cacheline(5) = '1') or + (iu2_valid_l2 and iu2_ifar_eff_cacheline(5) = '1'); +-- All erat errors except for erat parity error, for timing +iu2_erat_err_lite <= ierat_iu_iu2_miss or ierat_iu_iu2_multihit or ierat_iu_iu2_isi; +iu2_lru_rd_update <= iu2_valid and not iu2_erat_err_lite and or_reduce(iu2_rd_way_hit(0 to 3)); +dir_row0_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row0_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row0_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row0_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row0_lru_l2(1) & '0')); +dir_row1_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row1_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row1_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row1_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row1_lru_l2(1) & '0')); +dir_row2_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row2_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row2_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row2_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row2_lru_l2(1) & '0')); +dir_row3_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row3_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row3_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row3_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row3_lru_l2(1) & '0')); +dir_row4_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row4_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row4_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row4_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row4_lru_l2(1) & '0')); +dir_row5_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row5_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row5_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row5_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row5_lru_l2(1) & '0')); +dir_row6_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row6_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row6_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row6_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row6_lru_l2(1) & '0')); +dir_row7_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row7_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row7_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row7_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row7_lru_l2(1) & '0')); +dir_row8_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row8_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row8_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row8_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row8_lru_l2(1) & '0')); +dir_row9_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row9_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row9_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row9_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row9_lru_l2(1) & '0')); +dir_row10_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row10_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row10_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row10_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row10_lru_l2(1) & '0')); +dir_row11_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row11_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row11_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row11_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row11_lru_l2(1) & '0')); +dir_row12_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row12_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row12_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row12_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row12_lru_l2(1) & '0')); +dir_row13_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row13_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row13_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row13_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row13_lru_l2(1) & '0')); +dir_row14_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row14_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row14_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row14_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row14_lru_l2(1) & '0')); +dir_row15_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row15_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row15_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row15_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row15_lru_l2(1) & '0')); +dir_row16_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row16_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row16_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row16_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row16_lru_l2(1) & '0')); +dir_row17_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row17_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row17_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row17_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row17_lru_l2(1) & '0')); +dir_row18_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row18_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row18_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row18_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row18_lru_l2(1) & '0')); +dir_row19_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row19_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row19_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row19_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row19_lru_l2(1) & '0')); +dir_row20_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row20_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row20_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row20_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row20_lru_l2(1) & '0')); +dir_row21_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row21_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row21_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row21_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row21_lru_l2(1) & '0')); +dir_row22_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row22_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row22_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row22_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row22_lru_l2(1) & '0')); +dir_row23_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row23_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row23_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row23_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row23_lru_l2(1) & '0')); +dir_row24_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row24_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row24_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row24_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row24_lru_l2(1) & '0')); +dir_row25_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row25_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row25_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row25_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row25_lru_l2(1) & '0')); +dir_row26_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row26_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row26_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row26_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row26_lru_l2(1) & '0')); +dir_row27_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row27_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row27_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row27_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row27_lru_l2(1) & '0')); +dir_row28_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row28_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row28_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row28_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row28_lru_l2(1) & '0')); +dir_row29_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row29_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row29_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row29_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row29_lru_l2(1) & '0')); +dir_row30_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row30_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row30_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row30_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row30_lru_l2(1) & '0')); +dir_row31_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row31_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row31_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row31_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row31_lru_l2(1) & '0')); +dir_row32_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row32_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row32_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row32_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row32_lru_l2(1) & '0')); +dir_row33_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row33_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row33_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row33_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row33_lru_l2(1) & '0')); +dir_row34_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row34_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row34_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row34_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row34_lru_l2(1) & '0')); +dir_row35_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row35_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row35_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row35_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row35_lru_l2(1) & '0')); +dir_row36_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row36_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row36_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row36_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row36_lru_l2(1) & '0')); +dir_row37_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row37_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row37_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row37_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row37_lru_l2(1) & '0')); +dir_row38_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row38_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row38_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row38_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row38_lru_l2(1) & '0')); +dir_row39_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row39_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row39_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row39_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row39_lru_l2(1) & '0')); +dir_row40_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row40_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row40_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row40_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row40_lru_l2(1) & '0')); +dir_row41_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row41_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row41_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row41_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row41_lru_l2(1) & '0')); +dir_row42_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row42_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row42_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row42_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row42_lru_l2(1) & '0')); +dir_row43_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row43_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row43_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row43_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row43_lru_l2(1) & '0')); +dir_row44_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row44_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row44_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row44_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row44_lru_l2(1) & '0')); +dir_row45_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row45_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row45_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row45_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row45_lru_l2(1) & '0')); +dir_row46_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row46_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row46_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row46_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row46_lru_l2(1) & '0')); +dir_row47_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row47_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row47_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row47_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row47_lru_l2(1) & '0')); +dir_row48_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row48_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row48_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row48_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row48_lru_l2(1) & '0')); +dir_row49_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row49_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row49_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row49_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row49_lru_l2(1) & '0')); +dir_row50_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row50_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row50_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row50_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row50_lru_l2(1) & '0')); +dir_row51_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row51_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row51_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row51_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row51_lru_l2(1) & '0')); +dir_row52_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row52_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row52_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row52_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row52_lru_l2(1) & '0')); +dir_row53_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row53_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row53_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row53_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row53_lru_l2(1) & '0')); +dir_row54_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row54_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row54_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row54_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row54_lru_l2(1) & '0')); +dir_row55_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row55_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row55_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row55_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row55_lru_l2(1) & '0')); +dir_row56_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row56_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row56_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row56_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row56_lru_l2(1) & '0')); +dir_row57_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row57_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row57_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row57_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row57_lru_l2(1) & '0')); +dir_row58_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row58_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row58_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row58_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row58_lru_l2(1) & '0')); +dir_row59_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row59_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row59_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row59_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row59_lru_l2(1) & '0')); +dir_row60_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row60_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row60_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row60_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row60_lru_l2(1) & '0')); +dir_row61_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row61_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row61_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row61_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row61_lru_l2(1) & '0')); +dir_row62_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row62_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row62_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row62_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row62_lru_l2(1) & '0')); +dir_row63_lru_read <= gate_and(iu2_rd_way_hit(0), ("11" & dir_row63_lru_l2(2))) or + gate_and(iu2_rd_way_hit(1), ("10" & dir_row63_lru_l2(2))) or + gate_and(iu2_rd_way_hit(2), ('0' & dir_row63_lru_l2(1) & '1')) or + gate_and(iu2_rd_way_hit(3), ('0' & dir_row63_lru_l2(1) & '0')); +dir_row0_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row0_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row0_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row0_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row0_lru_l2(1) & '0')); +dir_row1_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row1_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row1_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row1_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row1_lru_l2(1) & '0')); +dir_row2_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row2_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row2_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row2_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row2_lru_l2(1) & '0')); +dir_row3_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row3_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row3_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row3_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row3_lru_l2(1) & '0')); +dir_row4_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row4_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row4_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row4_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row4_lru_l2(1) & '0')); +dir_row5_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row5_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row5_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row5_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row5_lru_l2(1) & '0')); +dir_row6_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row6_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row6_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row6_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row6_lru_l2(1) & '0')); +dir_row7_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row7_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row7_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row7_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row7_lru_l2(1) & '0')); +dir_row8_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row8_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row8_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row8_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row8_lru_l2(1) & '0')); +dir_row9_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row9_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row9_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row9_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row9_lru_l2(1) & '0')); +dir_row10_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row10_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row10_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row10_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row10_lru_l2(1) & '0')); +dir_row11_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row11_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row11_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row11_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row11_lru_l2(1) & '0')); +dir_row12_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row12_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row12_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row12_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row12_lru_l2(1) & '0')); +dir_row13_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row13_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row13_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row13_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row13_lru_l2(1) & '0')); +dir_row14_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row14_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row14_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row14_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row14_lru_l2(1) & '0')); +dir_row15_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row15_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row15_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row15_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row15_lru_l2(1) & '0')); +dir_row16_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row16_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row16_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row16_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row16_lru_l2(1) & '0')); +dir_row17_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row17_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row17_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row17_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row17_lru_l2(1) & '0')); +dir_row18_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row18_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row18_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row18_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row18_lru_l2(1) & '0')); +dir_row19_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row19_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row19_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row19_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row19_lru_l2(1) & '0')); +dir_row20_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row20_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row20_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row20_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row20_lru_l2(1) & '0')); +dir_row21_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row21_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row21_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row21_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row21_lru_l2(1) & '0')); +dir_row22_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row22_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row22_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row22_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row22_lru_l2(1) & '0')); +dir_row23_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row23_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row23_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row23_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row23_lru_l2(1) & '0')); +dir_row24_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row24_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row24_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row24_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row24_lru_l2(1) & '0')); +dir_row25_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row25_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row25_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row25_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row25_lru_l2(1) & '0')); +dir_row26_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row26_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row26_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row26_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row26_lru_l2(1) & '0')); +dir_row27_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row27_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row27_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row27_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row27_lru_l2(1) & '0')); +dir_row28_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row28_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row28_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row28_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row28_lru_l2(1) & '0')); +dir_row29_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row29_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row29_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row29_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row29_lru_l2(1) & '0')); +dir_row30_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row30_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row30_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row30_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row30_lru_l2(1) & '0')); +dir_row31_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row31_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row31_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row31_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row31_lru_l2(1) & '0')); +dir_row32_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row32_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row32_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row32_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row32_lru_l2(1) & '0')); +dir_row33_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row33_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row33_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row33_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row33_lru_l2(1) & '0')); +dir_row34_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row34_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row34_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row34_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row34_lru_l2(1) & '0')); +dir_row35_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row35_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row35_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row35_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row35_lru_l2(1) & '0')); +dir_row36_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row36_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row36_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row36_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row36_lru_l2(1) & '0')); +dir_row37_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row37_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row37_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row37_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row37_lru_l2(1) & '0')); +dir_row38_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row38_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row38_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row38_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row38_lru_l2(1) & '0')); +dir_row39_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row39_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row39_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row39_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row39_lru_l2(1) & '0')); +dir_row40_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row40_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row40_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row40_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row40_lru_l2(1) & '0')); +dir_row41_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row41_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row41_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row41_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row41_lru_l2(1) & '0')); +dir_row42_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row42_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row42_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row42_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row42_lru_l2(1) & '0')); +dir_row43_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row43_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row43_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row43_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row43_lru_l2(1) & '0')); +dir_row44_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row44_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row44_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row44_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row44_lru_l2(1) & '0')); +dir_row45_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row45_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row45_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row45_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row45_lru_l2(1) & '0')); +dir_row46_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row46_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row46_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row46_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row46_lru_l2(1) & '0')); +dir_row47_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row47_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row47_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row47_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row47_lru_l2(1) & '0')); +dir_row48_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row48_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row48_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row48_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row48_lru_l2(1) & '0')); +dir_row49_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row49_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row49_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row49_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row49_lru_l2(1) & '0')); +dir_row50_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row50_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row50_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row50_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row50_lru_l2(1) & '0')); +dir_row51_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row51_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row51_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row51_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row51_lru_l2(1) & '0')); +dir_row52_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row52_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row52_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row52_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row52_lru_l2(1) & '0')); +dir_row53_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row53_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row53_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row53_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row53_lru_l2(1) & '0')); +dir_row54_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row54_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row54_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row54_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row54_lru_l2(1) & '0')); +dir_row55_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row55_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row55_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row55_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row55_lru_l2(1) & '0')); +dir_row56_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row56_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row56_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row56_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row56_lru_l2(1) & '0')); +dir_row57_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row57_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row57_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row57_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row57_lru_l2(1) & '0')); +dir_row58_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row58_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row58_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row58_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row58_lru_l2(1) & '0')); +dir_row59_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row59_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row59_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row59_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row59_lru_l2(1) & '0')); +dir_row60_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row60_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row60_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row60_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row60_lru_l2(1) & '0')); +dir_row61_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row61_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row61_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row61_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row61_lru_l2(1) & '0')); +dir_row62_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row62_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row62_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row62_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row62_lru_l2(1) & '0')); +dir_row63_lru_write <= gate_and(icm_icd_lru_write_way(0), ("11" & dir_row63_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(1), ("10" & dir_row63_lru_l2(2))) or + gate_and(icm_icd_lru_write_way(2), ('0' & dir_row63_lru_l2(1) & '1')) or + gate_and(icm_icd_lru_write_way(3), ('0' & dir_row63_lru_l2(1) & '0')); +----------------------------------------------------------------------- +-- Update Valid Bits +----------------------------------------------------------------------- +-- For 128B cacheline mode, use even dir rows +iu2_ifar_eff_cacheline <= iu2_ifar_eff_l2(52 to 56) & + (iu2_ifar_eff_l2(57) and not (spr_ic_cls_l2 and not iu2_spr_idir_read_l2)); +iu3_parity_tag_cacheline <= iu3_parity_tag_l2(52 to 56) & (iu3_parity_tag_l2(57) and not spr_ic_cls_l2); +reload_cacheline <= icm_icd_reload_addr(52 to 56) & (icm_icd_reload_addr(57) and not spr_ic_cls_l2); +ecc_inval_cacheline <= icm_icd_ecc_addr(52 to 56) & (icm_icd_ecc_addr(57) and not spr_ic_cls_l2); +lru_write_cacheline <= icm_icd_lru_write_addr(52 to 56) & (icm_icd_lru_write_addr(57) and not spr_ic_cls_l2); +iu3_any_parity_err_way <= iu3_dir_parity_err_way_l2 or iu3_multihit_err_way_l2 or iu3_data_parity_err_way_l2; +dir_row0_val_d_part1 <= + ((dir_row0_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "000000"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "000000"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "000000"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "000000"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row0_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "000000"), dir_row0_val_l2); +dir_row0_val_d_part2_b <= not(dir_row0_val_d_part2a and iu2_rd_way_tag_hit); +dir_row0_val_d <= dir_row0_val_d_part1 and dir_row0_val_d_part2_b; +dir_row1_val_d_part1 <= + ((dir_row1_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "000001"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "000001"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "000001"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "000001"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row1_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "000001"), dir_row1_val_l2); +dir_row1_val_d_part2_b <= not(dir_row1_val_d_part2a and iu2_rd_way_tag_hit); +dir_row1_val_d <= dir_row1_val_d_part1 and dir_row1_val_d_part2_b; +dir_row2_val_d_part1 <= + ((dir_row2_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "000010"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "000010"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "000010"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "000010"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row2_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "000010"), dir_row2_val_l2); +dir_row2_val_d_part2_b <= not(dir_row2_val_d_part2a and iu2_rd_way_tag_hit); +dir_row2_val_d <= dir_row2_val_d_part1 and dir_row2_val_d_part2_b; +dir_row3_val_d_part1 <= + ((dir_row3_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "000011"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "000011"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "000011"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "000011"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row3_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "000011"), dir_row3_val_l2); +dir_row3_val_d_part2_b <= not(dir_row3_val_d_part2a and iu2_rd_way_tag_hit); +dir_row3_val_d <= dir_row3_val_d_part1 and dir_row3_val_d_part2_b; +dir_row4_val_d_part1 <= + ((dir_row4_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "000100"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "000100"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "000100"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "000100"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row4_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "000100"), dir_row4_val_l2); +dir_row4_val_d_part2_b <= not(dir_row4_val_d_part2a and iu2_rd_way_tag_hit); +dir_row4_val_d <= dir_row4_val_d_part1 and dir_row4_val_d_part2_b; +dir_row5_val_d_part1 <= + ((dir_row5_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "000101"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "000101"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "000101"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "000101"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row5_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "000101"), dir_row5_val_l2); +dir_row5_val_d_part2_b <= not(dir_row5_val_d_part2a and iu2_rd_way_tag_hit); +dir_row5_val_d <= dir_row5_val_d_part1 and dir_row5_val_d_part2_b; +dir_row6_val_d_part1 <= + ((dir_row6_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "000110"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "000110"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "000110"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "000110"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row6_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "000110"), dir_row6_val_l2); +dir_row6_val_d_part2_b <= not(dir_row6_val_d_part2a and iu2_rd_way_tag_hit); +dir_row6_val_d <= dir_row6_val_d_part1 and dir_row6_val_d_part2_b; +dir_row7_val_d_part1 <= + ((dir_row7_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "000111"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "000111"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "000111"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "000111"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row7_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "000111"), dir_row7_val_l2); +dir_row7_val_d_part2_b <= not(dir_row7_val_d_part2a and iu2_rd_way_tag_hit); +dir_row7_val_d <= dir_row7_val_d_part1 and dir_row7_val_d_part2_b; +dir_row8_val_d_part1 <= + ((dir_row8_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "001000"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "001000"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "001000"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "001000"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row8_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "001000"), dir_row8_val_l2); +dir_row8_val_d_part2_b <= not(dir_row8_val_d_part2a and iu2_rd_way_tag_hit); +dir_row8_val_d <= dir_row8_val_d_part1 and dir_row8_val_d_part2_b; +dir_row9_val_d_part1 <= + ((dir_row9_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "001001"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "001001"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "001001"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "001001"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row9_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "001001"), dir_row9_val_l2); +dir_row9_val_d_part2_b <= not(dir_row9_val_d_part2a and iu2_rd_way_tag_hit); +dir_row9_val_d <= dir_row9_val_d_part1 and dir_row9_val_d_part2_b; +dir_row10_val_d_part1 <= + ((dir_row10_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "001010"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "001010"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "001010"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "001010"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row10_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "001010"), dir_row10_val_l2); +dir_row10_val_d_part2_b <= not(dir_row10_val_d_part2a and iu2_rd_way_tag_hit); +dir_row10_val_d <= dir_row10_val_d_part1 and dir_row10_val_d_part2_b; +dir_row11_val_d_part1 <= + ((dir_row11_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "001011"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "001011"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "001011"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "001011"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row11_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "001011"), dir_row11_val_l2); +dir_row11_val_d_part2_b <= not(dir_row11_val_d_part2a and iu2_rd_way_tag_hit); +dir_row11_val_d <= dir_row11_val_d_part1 and dir_row11_val_d_part2_b; +dir_row12_val_d_part1 <= + ((dir_row12_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "001100"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "001100"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "001100"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "001100"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row12_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "001100"), dir_row12_val_l2); +dir_row12_val_d_part2_b <= not(dir_row12_val_d_part2a and iu2_rd_way_tag_hit); +dir_row12_val_d <= dir_row12_val_d_part1 and dir_row12_val_d_part2_b; +dir_row13_val_d_part1 <= + ((dir_row13_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "001101"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "001101"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "001101"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "001101"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row13_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "001101"), dir_row13_val_l2); +dir_row13_val_d_part2_b <= not(dir_row13_val_d_part2a and iu2_rd_way_tag_hit); +dir_row13_val_d <= dir_row13_val_d_part1 and dir_row13_val_d_part2_b; +dir_row14_val_d_part1 <= + ((dir_row14_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "001110"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "001110"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "001110"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "001110"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row14_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "001110"), dir_row14_val_l2); +dir_row14_val_d_part2_b <= not(dir_row14_val_d_part2a and iu2_rd_way_tag_hit); +dir_row14_val_d <= dir_row14_val_d_part1 and dir_row14_val_d_part2_b; +dir_row15_val_d_part1 <= + ((dir_row15_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "001111"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "001111"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "001111"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "001111"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row15_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "001111"), dir_row15_val_l2); +dir_row15_val_d_part2_b <= not(dir_row15_val_d_part2a and iu2_rd_way_tag_hit); +dir_row15_val_d <= dir_row15_val_d_part1 and dir_row15_val_d_part2_b; +dir_row16_val_d_part1 <= + ((dir_row16_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "010000"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "010000"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "010000"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "010000"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row16_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "010000"), dir_row16_val_l2); +dir_row16_val_d_part2_b <= not(dir_row16_val_d_part2a and iu2_rd_way_tag_hit); +dir_row16_val_d <= dir_row16_val_d_part1 and dir_row16_val_d_part2_b; +dir_row17_val_d_part1 <= + ((dir_row17_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "010001"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "010001"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "010001"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "010001"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row17_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "010001"), dir_row17_val_l2); +dir_row17_val_d_part2_b <= not(dir_row17_val_d_part2a and iu2_rd_way_tag_hit); +dir_row17_val_d <= dir_row17_val_d_part1 and dir_row17_val_d_part2_b; +dir_row18_val_d_part1 <= + ((dir_row18_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "010010"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "010010"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "010010"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "010010"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row18_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "010010"), dir_row18_val_l2); +dir_row18_val_d_part2_b <= not(dir_row18_val_d_part2a and iu2_rd_way_tag_hit); +dir_row18_val_d <= dir_row18_val_d_part1 and dir_row18_val_d_part2_b; +dir_row19_val_d_part1 <= + ((dir_row19_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "010011"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "010011"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "010011"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "010011"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row19_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "010011"), dir_row19_val_l2); +dir_row19_val_d_part2_b <= not(dir_row19_val_d_part2a and iu2_rd_way_tag_hit); +dir_row19_val_d <= dir_row19_val_d_part1 and dir_row19_val_d_part2_b; +dir_row20_val_d_part1 <= + ((dir_row20_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "010100"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "010100"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "010100"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "010100"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row20_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "010100"), dir_row20_val_l2); +dir_row20_val_d_part2_b <= not(dir_row20_val_d_part2a and iu2_rd_way_tag_hit); +dir_row20_val_d <= dir_row20_val_d_part1 and dir_row20_val_d_part2_b; +dir_row21_val_d_part1 <= + ((dir_row21_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "010101"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "010101"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "010101"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "010101"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row21_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "010101"), dir_row21_val_l2); +dir_row21_val_d_part2_b <= not(dir_row21_val_d_part2a and iu2_rd_way_tag_hit); +dir_row21_val_d <= dir_row21_val_d_part1 and dir_row21_val_d_part2_b; +dir_row22_val_d_part1 <= + ((dir_row22_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "010110"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "010110"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "010110"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "010110"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row22_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "010110"), dir_row22_val_l2); +dir_row22_val_d_part2_b <= not(dir_row22_val_d_part2a and iu2_rd_way_tag_hit); +dir_row22_val_d <= dir_row22_val_d_part1 and dir_row22_val_d_part2_b; +dir_row23_val_d_part1 <= + ((dir_row23_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "010111"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "010111"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "010111"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "010111"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row23_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "010111"), dir_row23_val_l2); +dir_row23_val_d_part2_b <= not(dir_row23_val_d_part2a and iu2_rd_way_tag_hit); +dir_row23_val_d <= dir_row23_val_d_part1 and dir_row23_val_d_part2_b; +dir_row24_val_d_part1 <= + ((dir_row24_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "011000"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "011000"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "011000"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "011000"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row24_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "011000"), dir_row24_val_l2); +dir_row24_val_d_part2_b <= not(dir_row24_val_d_part2a and iu2_rd_way_tag_hit); +dir_row24_val_d <= dir_row24_val_d_part1 and dir_row24_val_d_part2_b; +dir_row25_val_d_part1 <= + ((dir_row25_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "011001"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "011001"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "011001"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "011001"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row25_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "011001"), dir_row25_val_l2); +dir_row25_val_d_part2_b <= not(dir_row25_val_d_part2a and iu2_rd_way_tag_hit); +dir_row25_val_d <= dir_row25_val_d_part1 and dir_row25_val_d_part2_b; +dir_row26_val_d_part1 <= + ((dir_row26_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "011010"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "011010"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "011010"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "011010"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row26_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "011010"), dir_row26_val_l2); +dir_row26_val_d_part2_b <= not(dir_row26_val_d_part2a and iu2_rd_way_tag_hit); +dir_row26_val_d <= dir_row26_val_d_part1 and dir_row26_val_d_part2_b; +dir_row27_val_d_part1 <= + ((dir_row27_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "011011"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "011011"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "011011"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "011011"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row27_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "011011"), dir_row27_val_l2); +dir_row27_val_d_part2_b <= not(dir_row27_val_d_part2a and iu2_rd_way_tag_hit); +dir_row27_val_d <= dir_row27_val_d_part1 and dir_row27_val_d_part2_b; +dir_row28_val_d_part1 <= + ((dir_row28_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "011100"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "011100"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "011100"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "011100"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row28_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "011100"), dir_row28_val_l2); +dir_row28_val_d_part2_b <= not(dir_row28_val_d_part2a and iu2_rd_way_tag_hit); +dir_row28_val_d <= dir_row28_val_d_part1 and dir_row28_val_d_part2_b; +dir_row29_val_d_part1 <= + ((dir_row29_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "011101"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "011101"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "011101"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "011101"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row29_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "011101"), dir_row29_val_l2); +dir_row29_val_d_part2_b <= not(dir_row29_val_d_part2a and iu2_rd_way_tag_hit); +dir_row29_val_d <= dir_row29_val_d_part1 and dir_row29_val_d_part2_b; +dir_row30_val_d_part1 <= + ((dir_row30_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "011110"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "011110"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "011110"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "011110"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row30_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "011110"), dir_row30_val_l2); +dir_row30_val_d_part2_b <= not(dir_row30_val_d_part2a and iu2_rd_way_tag_hit); +dir_row30_val_d <= dir_row30_val_d_part1 and dir_row30_val_d_part2_b; +dir_row31_val_d_part1 <= + ((dir_row31_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "011111"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "011111"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "011111"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "011111"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row31_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "011111"), dir_row31_val_l2); +dir_row31_val_d_part2_b <= not(dir_row31_val_d_part2a and iu2_rd_way_tag_hit); +dir_row31_val_d <= dir_row31_val_d_part1 and dir_row31_val_d_part2_b; +dir_row32_val_d_part1 <= + ((dir_row32_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "100000"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "100000"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "100000"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "100000"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row32_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "100000"), dir_row32_val_l2); +dir_row32_val_d_part2_b <= not(dir_row32_val_d_part2a and iu2_rd_way_tag_hit); +dir_row32_val_d <= dir_row32_val_d_part1 and dir_row32_val_d_part2_b; +dir_row33_val_d_part1 <= + ((dir_row33_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "100001"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "100001"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "100001"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "100001"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row33_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "100001"), dir_row33_val_l2); +dir_row33_val_d_part2_b <= not(dir_row33_val_d_part2a and iu2_rd_way_tag_hit); +dir_row33_val_d <= dir_row33_val_d_part1 and dir_row33_val_d_part2_b; +dir_row34_val_d_part1 <= + ((dir_row34_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "100010"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "100010"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "100010"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "100010"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row34_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "100010"), dir_row34_val_l2); +dir_row34_val_d_part2_b <= not(dir_row34_val_d_part2a and iu2_rd_way_tag_hit); +dir_row34_val_d <= dir_row34_val_d_part1 and dir_row34_val_d_part2_b; +dir_row35_val_d_part1 <= + ((dir_row35_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "100011"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "100011"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "100011"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "100011"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row35_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "100011"), dir_row35_val_l2); +dir_row35_val_d_part2_b <= not(dir_row35_val_d_part2a and iu2_rd_way_tag_hit); +dir_row35_val_d <= dir_row35_val_d_part1 and dir_row35_val_d_part2_b; +dir_row36_val_d_part1 <= + ((dir_row36_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "100100"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "100100"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "100100"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "100100"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row36_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "100100"), dir_row36_val_l2); +dir_row36_val_d_part2_b <= not(dir_row36_val_d_part2a and iu2_rd_way_tag_hit); +dir_row36_val_d <= dir_row36_val_d_part1 and dir_row36_val_d_part2_b; +dir_row37_val_d_part1 <= + ((dir_row37_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "100101"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "100101"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "100101"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "100101"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row37_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "100101"), dir_row37_val_l2); +dir_row37_val_d_part2_b <= not(dir_row37_val_d_part2a and iu2_rd_way_tag_hit); +dir_row37_val_d <= dir_row37_val_d_part1 and dir_row37_val_d_part2_b; +dir_row38_val_d_part1 <= + ((dir_row38_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "100110"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "100110"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "100110"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "100110"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row38_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "100110"), dir_row38_val_l2); +dir_row38_val_d_part2_b <= not(dir_row38_val_d_part2a and iu2_rd_way_tag_hit); +dir_row38_val_d <= dir_row38_val_d_part1 and dir_row38_val_d_part2_b; +dir_row39_val_d_part1 <= + ((dir_row39_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "100111"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "100111"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "100111"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "100111"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row39_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "100111"), dir_row39_val_l2); +dir_row39_val_d_part2_b <= not(dir_row39_val_d_part2a and iu2_rd_way_tag_hit); +dir_row39_val_d <= dir_row39_val_d_part1 and dir_row39_val_d_part2_b; +dir_row40_val_d_part1 <= + ((dir_row40_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "101000"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "101000"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "101000"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "101000"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row40_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "101000"), dir_row40_val_l2); +dir_row40_val_d_part2_b <= not(dir_row40_val_d_part2a and iu2_rd_way_tag_hit); +dir_row40_val_d <= dir_row40_val_d_part1 and dir_row40_val_d_part2_b; +dir_row41_val_d_part1 <= + ((dir_row41_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "101001"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "101001"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "101001"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "101001"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row41_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "101001"), dir_row41_val_l2); +dir_row41_val_d_part2_b <= not(dir_row41_val_d_part2a and iu2_rd_way_tag_hit); +dir_row41_val_d <= dir_row41_val_d_part1 and dir_row41_val_d_part2_b; +dir_row42_val_d_part1 <= + ((dir_row42_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "101010"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "101010"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "101010"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "101010"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row42_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "101010"), dir_row42_val_l2); +dir_row42_val_d_part2_b <= not(dir_row42_val_d_part2a and iu2_rd_way_tag_hit); +dir_row42_val_d <= dir_row42_val_d_part1 and dir_row42_val_d_part2_b; +dir_row43_val_d_part1 <= + ((dir_row43_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "101011"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "101011"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "101011"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "101011"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row43_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "101011"), dir_row43_val_l2); +dir_row43_val_d_part2_b <= not(dir_row43_val_d_part2a and iu2_rd_way_tag_hit); +dir_row43_val_d <= dir_row43_val_d_part1 and dir_row43_val_d_part2_b; +dir_row44_val_d_part1 <= + ((dir_row44_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "101100"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "101100"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "101100"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "101100"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row44_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "101100"), dir_row44_val_l2); +dir_row44_val_d_part2_b <= not(dir_row44_val_d_part2a and iu2_rd_way_tag_hit); +dir_row44_val_d <= dir_row44_val_d_part1 and dir_row44_val_d_part2_b; +dir_row45_val_d_part1 <= + ((dir_row45_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "101101"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "101101"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "101101"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "101101"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row45_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "101101"), dir_row45_val_l2); +dir_row45_val_d_part2_b <= not(dir_row45_val_d_part2a and iu2_rd_way_tag_hit); +dir_row45_val_d <= dir_row45_val_d_part1 and dir_row45_val_d_part2_b; +dir_row46_val_d_part1 <= + ((dir_row46_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "101110"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "101110"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "101110"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "101110"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row46_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "101110"), dir_row46_val_l2); +dir_row46_val_d_part2_b <= not(dir_row46_val_d_part2a and iu2_rd_way_tag_hit); +dir_row46_val_d <= dir_row46_val_d_part1 and dir_row46_val_d_part2_b; +dir_row47_val_d_part1 <= + ((dir_row47_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "101111"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "101111"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "101111"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "101111"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row47_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "101111"), dir_row47_val_l2); +dir_row47_val_d_part2_b <= not(dir_row47_val_d_part2a and iu2_rd_way_tag_hit); +dir_row47_val_d <= dir_row47_val_d_part1 and dir_row47_val_d_part2_b; +dir_row48_val_d_part1 <= + ((dir_row48_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "110000"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "110000"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "110000"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "110000"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row48_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "110000"), dir_row48_val_l2); +dir_row48_val_d_part2_b <= not(dir_row48_val_d_part2a and iu2_rd_way_tag_hit); +dir_row48_val_d <= dir_row48_val_d_part1 and dir_row48_val_d_part2_b; +dir_row49_val_d_part1 <= + ((dir_row49_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "110001"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "110001"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "110001"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "110001"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row49_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "110001"), dir_row49_val_l2); +dir_row49_val_d_part2_b <= not(dir_row49_val_d_part2a and iu2_rd_way_tag_hit); +dir_row49_val_d <= dir_row49_val_d_part1 and dir_row49_val_d_part2_b; +dir_row50_val_d_part1 <= + ((dir_row50_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "110010"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "110010"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "110010"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "110010"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row50_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "110010"), dir_row50_val_l2); +dir_row50_val_d_part2_b <= not(dir_row50_val_d_part2a and iu2_rd_way_tag_hit); +dir_row50_val_d <= dir_row50_val_d_part1 and dir_row50_val_d_part2_b; +dir_row51_val_d_part1 <= + ((dir_row51_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "110011"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "110011"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "110011"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "110011"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row51_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "110011"), dir_row51_val_l2); +dir_row51_val_d_part2_b <= not(dir_row51_val_d_part2a and iu2_rd_way_tag_hit); +dir_row51_val_d <= dir_row51_val_d_part1 and dir_row51_val_d_part2_b; +dir_row52_val_d_part1 <= + ((dir_row52_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "110100"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "110100"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "110100"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "110100"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row52_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "110100"), dir_row52_val_l2); +dir_row52_val_d_part2_b <= not(dir_row52_val_d_part2a and iu2_rd_way_tag_hit); +dir_row52_val_d <= dir_row52_val_d_part1 and dir_row52_val_d_part2_b; +dir_row53_val_d_part1 <= + ((dir_row53_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "110101"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "110101"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "110101"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "110101"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row53_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "110101"), dir_row53_val_l2); +dir_row53_val_d_part2_b <= not(dir_row53_val_d_part2a and iu2_rd_way_tag_hit); +dir_row53_val_d <= dir_row53_val_d_part1 and dir_row53_val_d_part2_b; +dir_row54_val_d_part1 <= + ((dir_row54_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "110110"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "110110"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "110110"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "110110"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row54_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "110110"), dir_row54_val_l2); +dir_row54_val_d_part2_b <= not(dir_row54_val_d_part2a and iu2_rd_way_tag_hit); +dir_row54_val_d <= dir_row54_val_d_part1 and dir_row54_val_d_part2_b; +dir_row55_val_d_part1 <= + ((dir_row55_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "110111"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "110111"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "110111"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "110111"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row55_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "110111"), dir_row55_val_l2); +dir_row55_val_d_part2_b <= not(dir_row55_val_d_part2a and iu2_rd_way_tag_hit); +dir_row55_val_d <= dir_row55_val_d_part1 and dir_row55_val_d_part2_b; +dir_row56_val_d_part1 <= + ((dir_row56_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "111000"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "111000"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "111000"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "111000"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row56_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "111000"), dir_row56_val_l2); +dir_row56_val_d_part2_b <= not(dir_row56_val_d_part2a and iu2_rd_way_tag_hit); +dir_row56_val_d <= dir_row56_val_d_part1 and dir_row56_val_d_part2_b; +dir_row57_val_d_part1 <= + ((dir_row57_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "111001"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "111001"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "111001"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "111001"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row57_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "111001"), dir_row57_val_l2); +dir_row57_val_d_part2_b <= not(dir_row57_val_d_part2a and iu2_rd_way_tag_hit); +dir_row57_val_d <= dir_row57_val_d_part1 and dir_row57_val_d_part2_b; +dir_row58_val_d_part1 <= + ((dir_row58_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "111010"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "111010"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "111010"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "111010"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row58_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "111010"), dir_row58_val_l2); +dir_row58_val_d_part2_b <= not(dir_row58_val_d_part2a and iu2_rd_way_tag_hit); +dir_row58_val_d <= dir_row58_val_d_part1 and dir_row58_val_d_part2_b; +dir_row59_val_d_part1 <= + ((dir_row59_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "111011"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "111011"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "111011"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "111011"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row59_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "111011"), dir_row59_val_l2); +dir_row59_val_d_part2_b <= not(dir_row59_val_d_part2a and iu2_rd_way_tag_hit); +dir_row59_val_d <= dir_row59_val_d_part1 and dir_row59_val_d_part2_b; +dir_row60_val_d_part1 <= + ((dir_row60_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "111100"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "111100"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "111100"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "111100"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row60_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "111100"), dir_row60_val_l2); +dir_row60_val_d_part2_b <= not(dir_row60_val_d_part2a and iu2_rd_way_tag_hit); +dir_row60_val_d <= dir_row60_val_d_part1 and dir_row60_val_d_part2_b; +dir_row61_val_d_part1 <= + ((dir_row61_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "111101"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "111101"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "111101"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "111101"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row61_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "111101"), dir_row61_val_l2); +dir_row61_val_d_part2_b <= not(dir_row61_val_d_part2a and iu2_rd_way_tag_hit); +dir_row61_val_d <= dir_row61_val_d_part1 and dir_row61_val_d_part2_b; +dir_row62_val_d_part1 <= + ((dir_row62_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "111110"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "111110"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "111110"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "111110"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row62_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "111110"), dir_row62_val_l2); +dir_row62_val_d_part2_b <= not(dir_row62_val_d_part2a and iu2_rd_way_tag_hit); +dir_row62_val_d <= dir_row62_val_d_part1 and dir_row62_val_d_part2_b; +dir_row63_val_d_part1 <= + ((dir_row63_val_l2 + and not (gate_and((iu3_parity_tag_cacheline = "111111"), iu3_any_parity_err_way)) ) + or (gate_and((icm_icd_dir_val and reload_cacheline = "111111"), icm_icd_reload_way))) + and not (gate_and((icm_icd_dir_inval and reload_cacheline = "111111"), icm_icd_reload_way)) + and not (gate_and((icm_icd_ecc_inval and ecc_inval_cacheline = "111111"), icm_icd_ecc_way)) + and not (xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2 & xu_iu_ici_l2); +dir_row63_val_d_part2a <= gate_and(iu2_inval_l2 and (iu2_ifar_eff_cacheline = "111111"), dir_row63_val_l2); +dir_row63_val_d_part2_b <= not(dir_row63_val_d_part2a and iu2_rd_way_tag_hit); +dir_row63_val_d <= dir_row63_val_d_part1 and dir_row63_val_d_part2_b; +dir_row_val_even_act <= xu_iu_ici_l2 or + (or_reduce(iu3_any_parity_err_way) and (iu3_parity_tag_cacheline(5) = '0')) or + (icm_icd_any_reld_r2 and (reload_cacheline(5) = '0')) or + (icm_icd_any_checkecc and (ecc_inval_cacheline(5) = '0')) or + (iu2_inval_l2 and (iu2_ifar_eff_cacheline(5) = '0')); +dir_row_val_odd_act <= xu_iu_ici_l2 or + (or_reduce(iu3_any_parity_err_way) and (iu3_parity_tag_cacheline(5) = '1')) or + (icm_icd_any_reld_r2 and (reload_cacheline(5) = '1')) or + (icm_icd_any_checkecc and (ecc_inval_cacheline(5) = '1')) or + (iu2_inval_l2 and (iu2_ifar_eff_cacheline(5) = '1')); +lru_select <= icm_icd_lru_addr(52 to 56) & (icm_icd_lru_addr(57) and not spr_ic_cls_l2); +-- ic miss latches the location for data write to prevent data from moving around in Data cache +with lru_select select +return_lru <= dir_row0_lru_l2 when "000000", + dir_row1_lru_l2 when "000001", + dir_row2_lru_l2 when "000010", + dir_row3_lru_l2 when "000011", + dir_row4_lru_l2 when "000100", + dir_row5_lru_l2 when "000101", + dir_row6_lru_l2 when "000110", + dir_row7_lru_l2 when "000111", + dir_row8_lru_l2 when "001000", + dir_row9_lru_l2 when "001001", + dir_row10_lru_l2 when "001010", + dir_row11_lru_l2 when "001011", + dir_row12_lru_l2 when "001100", + dir_row13_lru_l2 when "001101", + dir_row14_lru_l2 when "001110", + dir_row15_lru_l2 when "001111", + dir_row16_lru_l2 when "010000", + dir_row17_lru_l2 when "010001", + dir_row18_lru_l2 when "010010", + dir_row19_lru_l2 when "010011", + dir_row20_lru_l2 when "010100", + dir_row21_lru_l2 when "010101", + dir_row22_lru_l2 when "010110", + dir_row23_lru_l2 when "010111", + dir_row24_lru_l2 when "011000", + dir_row25_lru_l2 when "011001", + dir_row26_lru_l2 when "011010", + dir_row27_lru_l2 when "011011", + dir_row28_lru_l2 when "011100", + dir_row29_lru_l2 when "011101", + dir_row30_lru_l2 when "011110", + dir_row31_lru_l2 when "011111", + dir_row32_lru_l2 when "100000", + dir_row33_lru_l2 when "100001", + dir_row34_lru_l2 when "100010", + dir_row35_lru_l2 when "100011", + dir_row36_lru_l2 when "100100", + dir_row37_lru_l2 when "100101", + dir_row38_lru_l2 when "100110", + dir_row39_lru_l2 when "100111", + dir_row40_lru_l2 when "101000", + dir_row41_lru_l2 when "101001", + dir_row42_lru_l2 when "101010", + dir_row43_lru_l2 when "101011", + dir_row44_lru_l2 when "101100", + dir_row45_lru_l2 when "101101", + dir_row46_lru_l2 when "101110", + dir_row47_lru_l2 when "101111", + dir_row48_lru_l2 when "110000", + dir_row49_lru_l2 when "110001", + dir_row50_lru_l2 when "110010", + dir_row51_lru_l2 when "110011", + dir_row52_lru_l2 when "110100", + dir_row53_lru_l2 when "110101", + dir_row54_lru_l2 when "110110", + dir_row55_lru_l2 when "110111", + dir_row56_lru_l2 when "111000", + dir_row57_lru_l2 when "111001", + dir_row58_lru_l2 when "111010", + dir_row59_lru_l2 when "111011", + dir_row60_lru_l2 when "111100", + dir_row61_lru_l2 when "111101", + dir_row62_lru_l2 when "111110", + dir_row63_lru_l2 when others; +icd_icm_row_lru <= return_lru; +with lru_select select +return_val <= dir_row0_val_l2 when "000000", + dir_row1_val_l2 when "000001", + dir_row2_val_l2 when "000010", + dir_row3_val_l2 when "000011", + dir_row4_val_l2 when "000100", + dir_row5_val_l2 when "000101", + dir_row6_val_l2 when "000110", + dir_row7_val_l2 when "000111", + dir_row8_val_l2 when "001000", + dir_row9_val_l2 when "001001", + dir_row10_val_l2 when "001010", + dir_row11_val_l2 when "001011", + dir_row12_val_l2 when "001100", + dir_row13_val_l2 when "001101", + dir_row14_val_l2 when "001110", + dir_row15_val_l2 when "001111", + dir_row16_val_l2 when "010000", + dir_row17_val_l2 when "010001", + dir_row18_val_l2 when "010010", + dir_row19_val_l2 when "010011", + dir_row20_val_l2 when "010100", + dir_row21_val_l2 when "010101", + dir_row22_val_l2 when "010110", + dir_row23_val_l2 when "010111", + dir_row24_val_l2 when "011000", + dir_row25_val_l2 when "011001", + dir_row26_val_l2 when "011010", + dir_row27_val_l2 when "011011", + dir_row28_val_l2 when "011100", + dir_row29_val_l2 when "011101", + dir_row30_val_l2 when "011110", + dir_row31_val_l2 when "011111", + dir_row32_val_l2 when "100000", + dir_row33_val_l2 when "100001", + dir_row34_val_l2 when "100010", + dir_row35_val_l2 when "100011", + dir_row36_val_l2 when "100100", + dir_row37_val_l2 when "100101", + dir_row38_val_l2 when "100110", + dir_row39_val_l2 when "100111", + dir_row40_val_l2 when "101000", + dir_row41_val_l2 when "101001", + dir_row42_val_l2 when "101010", + dir_row43_val_l2 when "101011", + dir_row44_val_l2 when "101100", + dir_row45_val_l2 when "101101", + dir_row46_val_l2 when "101110", + dir_row47_val_l2 when "101111", + dir_row48_val_l2 when "110000", + dir_row49_val_l2 when "110001", + dir_row50_val_l2 when "110010", + dir_row51_val_l2 when "110011", + dir_row52_val_l2 when "110100", + dir_row53_val_l2 when "110101", + dir_row54_val_l2 when "110110", + dir_row55_val_l2 when "110111", + dir_row56_val_l2 when "111000", + dir_row57_val_l2 when "111001", + dir_row58_val_l2 when "111010", + dir_row59_val_l2 when "111011", + dir_row60_val_l2 when "111100", + dir_row61_val_l2 when "111101", + dir_row62_val_l2 when "111110", + dir_row63_val_l2 when others; +icd_icm_row_val <= return_val; +----------------------------------------------------------------------- +-- IU2 +----------------------------------------------------------------------- +-- IU2 Output +mm_epn: for i in 0 to 51 generate +begin + R0:if(i < EFF_IFAR'left) generate begin iu_mm_ierat_epn(i) <= '0'; +end generate; +R1:if(i >= EFF_IFAR'left) generate +begin iu_mm_ierat_epn(i) <= iu2_ifar_eff_l2(i); +end generate; +end generate; +-- Handle Miss +iu2_rd_miss <= iu2_valid and (iu2_dir_miss or iu2_ci); +iu3_rd_parity_err_d <= iu2_valid and iu2_rd_parity_err and or_reduce(iu2_tid_l2 and not ics_icd_iu2_flush_tid) and not iu2_ci; +iu3_rd_miss_d <= iu2_rd_miss and not or_reduce(iu2_tid_l2 and ics_icd_iu2_flush_tid); +iu3_rd_miss <= iu3_rd_miss_l2 and not iu3_erat_err_l2(0); +iu2_miss_flush_prev <= gate_and(iu3_rd_miss, iu3_tid_l2) and not ics_icd_all_flush_prev; +icd_icm_miss <= iu2_rd_miss; +icd_icm_tid <= iu2_tid_l2; +icd_icm_addr_real <= ierat_iu_iu2_rpn_noncmp(REAL_IFAR'left to 51) & iu2_ifar_eff_l2(52 to 61); +icd_icm_addr_eff <= iu2_ifar_eff_l2(EFF_IFAR'left to 51); +icd_icm_wimge <= ierat_iu_iu2_wimge; +icd_icm_userdef <= ierat_iu_iu2_u; +icd_icm_2ucode <= iu2_2ucode_l2; +icd_icm_2ucode_type <= iu2_2ucode_type_l2; +icd_icm_iu2_inval <= iu2_inval_l2; +icd_icm_ici <= xu_iu_ici_l2; +icd_icm_any_iu2_valid <= iu2_valid; +icd_ics_iu2_miss_flush_prev <= iu2_miss_flush_prev; +icd_ics_iu2_ifar_eff <= iu2_ifar_eff_l2; +icd_ics_iu2_2ucode <= iu2_2ucode_l2; +icd_ics_iu2_2ucode_type <= iu2_2ucode_type_l2; +load_iu2 <= or_reduce(icm_icd_load_tid); +iu3_act <= iu2_valid or load_iu2; +iu3_valid_next <= (iu2_valid and or_reduce(iu2_tid_l2 and not ics_icd_iu2_flush_tid)) or + or_reduce(icm_icd_load_tid); + WITH s3'(iu3_valid_next & iu3_ifar_d(60 to 61)) SELECT iu3_instr_valid_d(0 TO 3) <= "1111" when "100", + "1110" when "101", + "1100" when "110", + "1000" when "111", + "0000" when others; +with load_iu2 select +iu3_tid_d <= iu2_tid_l2 when '0', + icm_icd_load_tid when others; +with load_iu2 select +iu3_ifar_d <= iu2_ifar_eff_l2 when '0', + icm_icd_load_addr when others; +iu3_2ucode_d <= icm_icd_load_2ucode when load_iu2 = '1' + else iu2_2ucode_l2; +with load_iu2 select +iu3_2ucode_type_d <= iu2_2ucode_type_l2 when '0', + icm_icd_load_2ucode_type when others; +iu2_erat_err <= (ierat_iu_iu2_error(0) and not load_iu2) & + (ierat_iu_iu2_error(1) and not load_iu2) & + (ierat_iu_iu2_error(2) and not load_iu2); +iu3_erat_err_d <= iu2_erat_err; +-- Mux data from cache +iu2_data_dataout_0 <= iu2_data_dataout_l2( 0 to 143); +iu2_data_dataout_1 <= iu2_data_dataout_l2(162 to 305); +iu2_data_dataout_2 <= iu2_data_dataout_l2(324 to 467); +iu2_data_dataout_3 <= iu2_data_dataout_l2(486 to 629); +insmux : entity work.iuq_ic_insmux + generic map( expand_type=> expand_type) + port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + forcee => forcee, + sg_0 => pc_iu_sg_0, + thold_0_b => pc_iu_func_sl_thold_0_b, + scan_in => siv(iu3_instr_offset), + scan_out => sov(iu3_instr_offset), + inslat_act => iu3_act, + iu2_rd_way_hit_b => iu2_rd_way_hit_insmux_b, + load_iu2 => load_iu2, + icm_icd_reload_data => icm_icd_reload_data(0 to 143), + iu2_data_dataout_0 => iu2_data_dataout_0, + iu2_data_dataout_1 => iu2_data_dataout_1, + iu2_data_dataout_2 => iu2_data_dataout_2, + iu2_data_dataout_3 => iu2_data_dataout_3, + iu3_instr0_buf => iu3_instr0_buf, + iu3_instr1_buf => iu3_instr1_buf, + iu3_instr2_buf => iu3_instr2_buf, + iu3_instr3_buf => iu3_instr3_buf +); + WITH s3'(iu2_erat_err(0) & iu3_ifar_d(60 to 61)) SELECT iu2_ifar_dec(0 TO 3) <= "1000" when "000", + "0100" when "001", + "0010" when "010", + "0001" when "011", + "0000" when others; +iu3_ifar_dec_d <= iu2_ifar_dec; +----------------------------------------------------------------------- +-- IU3 +----------------------------------------------------------------------- +-- Force 2ucode to 0 if branch instructions or no-op. No other +-- instructions are legal when dynamically changing code. +-- Note: This signal does not include all non-ucode ops - just the ones +-- that will cause problems with flush_2ucode. +uc_illegal <= iu3_0_instr_rot(32) or + (iu3_0_instr_rot(0 to 5) = "011000"); +ic_bp_iu3_val <= iu3_instr_valid_l2; +ic_bp_iu3_tid <= iu3_tid_l2; +ic_bp_iu3_ifar <= iu3_ifar_l2; +ic_bp_iu3_2ucode <= iu3_2ucode_l2 and not uc_illegal and not iu3_erat_err_l2(0); +ic_bp_iu3_2ucode_type <= iu3_2ucode_type_l2; +int_ic_bp_iu3_error(0) <= iu3_erat_err_l2(0); +int_ic_bp_iu3_error(1) <= iu3_erat_err_l2(1) or (icm_icd_iu3_ecc_err and not iu3_erat_err_l2(0)); +int_ic_bp_iu3_error(2) <= iu3_erat_err_l2(2); +ic_bp_iu3_error <= int_ic_bp_iu3_error; +icd_icm_iu3_erat_err <= iu3_erat_err_l2(0); +xnop <= "011010" & ZEROS(6 to 35); +iu3_0_instr_rot <= gate(xnop, iu3_erat_err_l2(0)) or + gate(iu3_instr0_buf, iu3_ifar_dec_l2(0)) or + gate(iu3_instr1_buf, iu3_ifar_dec_l2(1)) or + gate(iu3_instr2_buf, iu3_ifar_dec_l2(2)) or + gate(iu3_instr3_buf, iu3_ifar_dec_l2(3)) ; +iu3_1_instr_rot <= gate(xnop, iu3_erat_err_l2(0)) or + gate(iu3_instr1_buf, iu3_ifar_dec_l2(0)) or + gate(iu3_instr2_buf, iu3_ifar_dec_l2(1)) or + gate(iu3_instr3_buf, iu3_ifar_dec_l2(2)) ; +iu3_2_instr_rot <= gate(xnop, iu3_erat_err_l2(0)) or + gate(iu3_instr2_buf, iu3_ifar_dec_l2(0)) or + gate(iu3_instr3_buf, iu3_ifar_dec_l2(1)) ; +iu3_3_instr_rot <= xnop when iu3_erat_err_l2(0) = '1' + else iu3_instr3_buf; +ic_bp_iu3_0_instr <= iu3_0_instr_rot; +ic_bp_iu3_1_instr <= iu3_1_instr_rot; +ic_bp_iu3_2_instr <= iu3_2_instr_rot; +ic_bp_iu3_3_instr <= iu3_3_instr_rot; +int_ic_bp_iu3_flush <= icm_icd_iu3_ecc_fp_cancel or (iu3_parity_flush and not iu3_erat_err_l2(0)) or + iu3_rd_miss or or_reduce(iu3_tid_l2 and ics_icd_all_flush_prev); +ic_bp_iu3_flush <= int_ic_bp_iu3_flush; +icd_ics_iu3_ifar <= iu3_ifar_l2; +icd_ics_iu3_2ucode <= iu3_2ucode_l2; +icd_ics_iu3_2ucode_type <= iu3_2ucode_type_l2; +----------------------------------------------------------------------- +-- Performance Events +----------------------------------------------------------------------- +-- IERAT Miss +-- - IU2 ierat miss +perf_event_t0_d(4) <= iu2_valid and iu2_tid_l2(0) and ierat_iu_iu2_miss; +perf_event_t1_d(4) <= iu2_valid and iu2_tid_l2(1) and ierat_iu_iu2_miss; +perf_event_t2_d(4) <= iu2_valid and iu2_tid_l2(2) and ierat_iu_iu2_miss; +perf_event_t3_d(4) <= iu2_valid and iu2_tid_l2(3) and ierat_iu_iu2_miss; +-- I-Cache Fetch +-- - Number of times ICache is read for instruction +perf_event_t0_d(5) <= iu2_valid and iu2_tid_l2(0); +perf_event_t1_d(5) <= iu2_valid and iu2_tid_l2(1); +perf_event_t2_d(5) <= iu2_valid and iu2_tid_l2(2); +perf_event_t3_d(5) <= iu2_valid and iu2_tid_l2(3); +-- Instructions Fetched +-- - Number of instructions fetched, divided by 4. + WITH s2'(iu2_ifar_eff_l2(60 to 61)) SELECT iu2_instr_count <= "100" when "00", + "011" when "01", + "010" when "10", + "001" when others; +perf_instr_count_t0_new(0 TO 2) <= std_ulogic_vector( + unsigned('0' & perf_instr_count_t0_l2) + unsigned(iu2_instr_count) ); +perf_instr_count_t0_d(0 TO 1) <= perf_instr_count_t0_new(1 to 2) when (iu2_valid and iu2_tid_l2(0)) = '1' + else perf_instr_count_t0_l2; +perf_event_t0_d(6) <= iu2_valid and iu2_tid_l2(0) and perf_instr_count_t0_new(0); +perf_instr_count_t1_new(0 TO 2) <= std_ulogic_vector( + unsigned('0' & perf_instr_count_t1_l2) + unsigned(iu2_instr_count) ); +perf_instr_count_t1_d(0 TO 1) <= perf_instr_count_t1_new(1 to 2) when (iu2_valid and iu2_tid_l2(1)) = '1' + else perf_instr_count_t1_l2; +perf_event_t1_d(6) <= iu2_valid and iu2_tid_l2(1) and perf_instr_count_t1_new(0); +perf_instr_count_t2_new(0 TO 2) <= std_ulogic_vector( + unsigned('0' & perf_instr_count_t2_l2) + unsigned(iu2_instr_count) ); +perf_instr_count_t2_d(0 TO 1) <= perf_instr_count_t2_new(1 to 2) when (iu2_valid and iu2_tid_l2(2)) = '1' + else perf_instr_count_t2_l2; +perf_event_t2_d(6) <= iu2_valid and iu2_tid_l2(2) and perf_instr_count_t2_new(0); +perf_instr_count_t3_new(0 TO 2) <= std_ulogic_vector( + unsigned('0' & perf_instr_count_t3_l2) + unsigned(iu2_instr_count) ); +perf_instr_count_t3_d(0 TO 1) <= perf_instr_count_t3_new(1 to 2) when (iu2_valid and iu2_tid_l2(3)) = '1' + else perf_instr_count_t3_l2; +perf_event_t3_d(6) <= iu2_valid and iu2_tid_l2(3) and perf_instr_count_t3_new(0); +-- Events not per thread +-- L2 Back Invalidates I-Cache +perf_event_d(0) <= iu2_inval_l2; +-- L2 Back Invalidates I-Cache - Hits +perf_event_d(1) <= iu2_inval_l2 and or_reduce(iu2_rd_way_tag_hit and iu2_dir_rd_val_l2); +ic_perf_event_t0 <= perf_event_t0_l2; +ic_perf_event_t1 <= perf_event_t1_l2; +ic_perf_event_t2 <= perf_event_t2_l2; +ic_perf_event_t3 <= perf_event_t3_l2; +ic_perf_event <= perf_event_l2; +----------------------------------------------------------------------- +-- Debug Bus +----------------------------------------------------------------------- +dbg_dir_write_d <= dir_write; +dbg_dir_rd_act_d <= dir_rd_act; +dbg_iu2_lru_rd_update_d <= iu2_lru_rd_update; +dbg_iu2_rd_way_tag_hit_d <= iu2_rd_way_tag_hit; +dbg_iu2_rd_way_hit_d <= iu2_rd_way_hit; +dbg_load_iu2_d <= load_iu2; +dir_dbg_data0(0 TO 10) <= data_datain(21 to 31); +dir_dbg_data0(11 TO 21) <= iu2_data_dataout_l2(21 to 31); +dir_dbg_data0(22) <= dbg_dir_write_l2; +dir_dbg_data0(23) <= data_write; +dir_dbg_data0(24 TO 31) <= icm_icd_reload_addr(52 to 59); +dir_dbg_data0(32 TO 35) <= icm_icd_reload_way(0 to 3); +dir_dbg_data0(36) <= dbg_dir_rd_act_l2; +dir_dbg_data0(37) <= icm_icd_dir_write_endian; +dir_dbg_data0(38 TO 43) <= iu2_ifar_eff_l2(52 to 57); +dir_dbg_data0(44 TO 47) <= iu2_dir_rd_val_l2; +dir_dbg_data0(48 TO 51) <= dbg_iu2_rd_way_tag_hit_l2; +dir_dbg_data0(52 TO 55) <= iu3_dir_parity_err_way_l2; +dir_dbg_data0(56 TO 59) <= iu3_multihit_err_way_l2; +dir_dbg_data0(60 TO 63) <= iu3_data_parity_err_way_l2; +dir_dbg_data0(64) <= xu_iu_ici_l2; +dir_dbg_data0(65) <= iu2_inval_l2; +dir_dbg_data0(66) <= icm_icd_dir_val; +dir_dbg_data0(67) <= icm_icd_dir_inval; +dir_dbg_data0(68) <= icm_icd_ecc_inval; +dir_dbg_data0(69) <= icm_icd_lru_write; +dir_dbg_data0(70) <= dbg_iu2_lru_rd_update_l2; +dir_dbg_data0(71 TO 73) <= iu2_spr_idir_lru_l2; +dir_dbg_data0(74 TO 79) <= icm_icd_lru_write_addr(52 to 57); +dir_dbg_data0(80 TO 83) <= icm_icd_lru_write_way; +dir_dbg_data0(84) <= perf_event_t0_d(5); +dir_dbg_data0(85) <= perf_event_t1_d(5); +dir_dbg_data0(86) <= perf_event_t2_d(5); +dir_dbg_data0(87) <= perf_event_t3_d(5); +dbg1: if (EFF_IFAR'left > 0 )generate +begin dir_dbg_data1(0 TO EFF_IFAR'left-1) <= (others => '0'); +end generate; +dir_dbg_data1(EFF_IFAR'left TO 61) <= iu3_ifar_l2; +dir_dbg_data1(62 TO 67) <= iu3_0_instr_rot(0 to 5); +dir_dbg_data1(68 TO 71) <= iu3_instr_valid_l2; +dir_dbg_data1(72 TO 75) <= iu3_tid_l2; +dir_dbg_data1(76) <= int_ic_bp_iu3_flush; +dir_dbg_data1(77 TO 79) <= int_ic_bp_iu3_error; +dir_dbg_data1(80 TO 83) <= ics_icd_all_flush_prev; +dir_dbg_data1(84) <= dbg_load_iu2_l2; +dir_dbg_data1(85) <= uc_illegal; +dir_dbg_data1(86) <= iu3_2ucode_l2; +dir_dbg_data1(87) <= iu3_2ucode_type_l2; +dir_dbg_data2(0) <= iu2_valid; +dir_dbg_data2(1 TO 3) <= iu3_erat_err_l2; +dir_dbg_data2(4 TO 7) <= iu2_tid_l2; +dir_dbg_data2(8 TO 11) <= dbg_iu2_rd_way_hit_l2; +dir_dbg_data2(12) <= iu2_ci; +dir_dbg_data2(13) <= iu2_endian; +dir_dbg_data2(14 TO 43) <= ierat_iu_iu2_rpn_noncmp; +dir_dbg_trigger0(0) <= iu1_valid_l2; +dir_dbg_trigger0(1) <= iu1_inval_l2; +dir_dbg_trigger0(2 TO 5) <= iu1_tid_l2; +dir_dbg_trigger0(6) <= iu3_rd_miss_l2; +dir_dbg_trigger0(7) <= iu3_instr_valid_l2(0); +dir_dbg_trigger1(0 TO 9) <= iu2_ifar_eff_l2(52 to 61); +dir_dbg_trigger1(10) <= iu2_valid_l2; +dir_dbg_trigger1(11) <= iu2_inval_l2; +----------------------------------------------------------------------- +-- Latches +----------------------------------------------------------------------- +-- IU1 +iu1_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu1_valid_offset), + scout => sov(iu1_valid_offset), + din => iu1_valid_d, + dout => iu1_valid_l2); +iu1_tid_latch: tri_rlmreg_p + generic map (width => iu1_tid_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_rd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu1_tid_offset to iu1_tid_offset + iu1_tid_l2'length-1), + scout => sov(iu1_tid_offset to iu1_tid_offset + iu1_tid_l2'length-1), + din => iu1_tid_d, + dout => iu1_tid_l2); +-- Note: Technically, only need REAL_IFAR range during sleep mode +iu1_ifar_latch: tri_rlmreg_p + generic map (width => iu1_ifar_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_rd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu1_ifar_offset to iu1_ifar_offset + iu1_ifar_l2'length-1), + scout => sov(iu1_ifar_offset to iu1_ifar_offset + iu1_ifar_l2'length-1), + din => iu1_ifar_d, + dout => iu1_ifar_l2); +iu1_inval_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu1_inval_offset), + scout => sov(iu1_inval_offset), + din => iu1_inval_d, + dout => iu1_inval_l2); +iu1_2ucode_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_rd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu1_2ucode_offset), + scout => sov(iu1_2ucode_offset), + din => iu1_2ucode_d, + dout => iu1_2ucode_l2); +iu1_2ucode_type_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_rd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu1_2ucode_type_offset), + scout => sov(iu1_2ucode_type_offset), + din => iu1_2ucode_type_d, + dout => iu1_2ucode_type_l2); +-- IU2 +iu2_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu2_valid_offset), + scout => sov(iu2_valid_offset), + din => iu2_valid_d, + dout => iu2_valid_l2); +iu2_tid_latch: tri_rlmreg_p + generic map (width => iu2_tid_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu1_valid_l2, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu2_tid_offset to iu2_tid_offset + iu2_tid_l2'length-1), + scout => sov(iu2_tid_offset to iu2_tid_offset + iu2_tid_l2'length-1), + din => iu2_tid_d, + dout => iu2_tid_l2); +iu2_ifar_eff_latch: tri_rlmreg_p + generic map (width => 52-EFF_IFAR'left, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_dataout_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu2_ifar_eff_offset to iu2_ifar_eff_offset + 52-EFF_IFAR'left-1), + scout => sov(iu2_ifar_eff_offset to iu2_ifar_eff_offset + 52-EFF_IFAR'left-1), + din => iu2_ifar_eff_d(EFF_IFAR'left to 51), + dout => iu2_ifar_eff_l2(EFF_IFAR'left to 51)); +-- Only need 52:57 in sleep mode +iu2_ifar_eff_slp_latch: tri_rlmreg_p + generic map (width => 10, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_dataout_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu2_ifar_eff_offset+52 to iu2_ifar_eff_offset + iu2_ifar_eff_l2'length-1), + scout => sov(iu2_ifar_eff_offset+52 to iu2_ifar_eff_offset + iu2_ifar_eff_l2'length-1), + din => iu2_ifar_eff_d(52 to 61), + dout => iu2_ifar_eff_l2(52 to 61)); +iu2_2ucode_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu1_valid_l2, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu2_2ucode_offset), + scout => sov(iu2_2ucode_offset), + din => iu2_2ucode_d, + dout => iu2_2ucode_l2); +iu2_2ucode_type_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu1_valid_l2, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu2_2ucode_type_offset), + scout => sov(iu2_2ucode_type_offset), + din => iu2_2ucode_type_d, + dout => iu2_2ucode_type_l2); +iu2_inval_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu2_inval_offset), + scout => sov(iu2_inval_offset), + din => iu2_inval_d, + dout => iu2_inval_l2); +iu2_dir_rd_val_latch: tri_rlmreg_p + generic map (width => iu2_dir_rd_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_dataout_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu2_dir_rd_val_offset to iu2_dir_rd_val_offset + iu2_dir_rd_val_l2'length-1), + scout => sov(iu2_dir_rd_val_offset to iu2_dir_rd_val_offset + iu2_dir_rd_val_l2'length-1), + din => iu2_dir_rd_val_d, + dout => iu2_dir_rd_val_l2); +iu2_dir_dataout_0_par_latch: tri_rlmreg_p + generic map (width => iu2_dir_dataout_0_par_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_dataout_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu2_dir_dataout_0_par_offset to iu2_dir_dataout_0_par_offset + iu2_dir_dataout_0_par_l2'length-1), + scout => sov(iu2_dir_dataout_0_par_offset to iu2_dir_dataout_0_par_offset + iu2_dir_dataout_0_par_l2'length-1), + din => iu2_dir_dataout_0_par_d, + dout => iu2_dir_dataout_0_par_l2); +iu2_dir_dataout_1_par_latch: tri_rlmreg_p + generic map (width => iu2_dir_dataout_1_par_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_dataout_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu2_dir_dataout_1_par_offset to iu2_dir_dataout_1_par_offset + iu2_dir_dataout_1_par_l2'length-1), + scout => sov(iu2_dir_dataout_1_par_offset to iu2_dir_dataout_1_par_offset + iu2_dir_dataout_1_par_l2'length-1), + din => iu2_dir_dataout_1_par_d, + dout => iu2_dir_dataout_1_par_l2); +iu2_dir_dataout_2_par_latch: tri_rlmreg_p + generic map (width => iu2_dir_dataout_2_par_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_dataout_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu2_dir_dataout_2_par_offset to iu2_dir_dataout_2_par_offset + iu2_dir_dataout_2_par_l2'length-1), + scout => sov(iu2_dir_dataout_2_par_offset to iu2_dir_dataout_2_par_offset + iu2_dir_dataout_2_par_l2'length-1), + din => iu2_dir_dataout_2_par_d, + dout => iu2_dir_dataout_2_par_l2); +iu2_dir_dataout_3_par_latch: tri_rlmreg_p + generic map (width => iu2_dir_dataout_3_par_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_dataout_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu2_dir_dataout_3_par_offset to iu2_dir_dataout_3_par_offset + iu2_dir_dataout_3_par_l2'length-1), + scout => sov(iu2_dir_dataout_3_par_offset to iu2_dir_dataout_3_par_offset + iu2_dir_dataout_3_par_l2'length-1), + din => iu2_dir_dataout_3_par_d, + dout => iu2_dir_dataout_3_par_l2); +iu2_data_dataout_latch: tri_rlmreg_p + generic map (width => iu2_data_dataout_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu1_valid_l2, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu2_data_dataout_offset to iu2_data_dataout_offset + iu2_data_dataout_l2'length-1), + scout => sov(iu2_data_dataout_offset to iu2_data_dataout_offset + iu2_data_dataout_l2'length-1), + din => iu2_data_dataout_d, + dout => iu2_data_dataout_l2); +xu_iu_ici_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_iu_ici_offset), + scout => sov(xu_iu_ici_offset), + din => xu_iu_ici_d, + dout => xu_iu_ici_l2); +-- Dir +-- even & odd rows use separate acts for power savings in 128B cacheline mode +dir_row0_val_latch: tri_rlmreg_p + generic map (width => dir_row0_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row0_val_offset to dir_row0_val_offset + dir_row0_val_l2'length-1), + scout => sov(dir_row0_val_offset to dir_row0_val_offset + dir_row0_val_l2'length-1), + din => dir_row0_val_d, + dout => dir_row0_val_l2); +dir_row2_val_latch: tri_rlmreg_p + generic map (width => dir_row2_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row2_val_offset to dir_row2_val_offset + dir_row2_val_l2'length-1), + scout => sov(dir_row2_val_offset to dir_row2_val_offset + dir_row2_val_l2'length-1), + din => dir_row2_val_d, + dout => dir_row2_val_l2); +dir_row4_val_latch: tri_rlmreg_p + generic map (width => dir_row4_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row4_val_offset to dir_row4_val_offset + dir_row4_val_l2'length-1), + scout => sov(dir_row4_val_offset to dir_row4_val_offset + dir_row4_val_l2'length-1), + din => dir_row4_val_d, + dout => dir_row4_val_l2); +dir_row6_val_latch: tri_rlmreg_p + generic map (width => dir_row6_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row6_val_offset to dir_row6_val_offset + dir_row6_val_l2'length-1), + scout => sov(dir_row6_val_offset to dir_row6_val_offset + dir_row6_val_l2'length-1), + din => dir_row6_val_d, + dout => dir_row6_val_l2); +dir_row8_val_latch: tri_rlmreg_p + generic map (width => dir_row8_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row8_val_offset to dir_row8_val_offset + dir_row8_val_l2'length-1), + scout => sov(dir_row8_val_offset to dir_row8_val_offset + dir_row8_val_l2'length-1), + din => dir_row8_val_d, + dout => dir_row8_val_l2); +dir_row10_val_latch: tri_rlmreg_p + generic map (width => dir_row10_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row10_val_offset to dir_row10_val_offset + dir_row10_val_l2'length-1), + scout => sov(dir_row10_val_offset to dir_row10_val_offset + dir_row10_val_l2'length-1), + din => dir_row10_val_d, + dout => dir_row10_val_l2); +dir_row12_val_latch: tri_rlmreg_p + generic map (width => dir_row12_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row12_val_offset to dir_row12_val_offset + dir_row12_val_l2'length-1), + scout => sov(dir_row12_val_offset to dir_row12_val_offset + dir_row12_val_l2'length-1), + din => dir_row12_val_d, + dout => dir_row12_val_l2); +dir_row14_val_latch: tri_rlmreg_p + generic map (width => dir_row14_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row14_val_offset to dir_row14_val_offset + dir_row14_val_l2'length-1), + scout => sov(dir_row14_val_offset to dir_row14_val_offset + dir_row14_val_l2'length-1), + din => dir_row14_val_d, + dout => dir_row14_val_l2); +dir_row16_val_latch: tri_rlmreg_p + generic map (width => dir_row16_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row16_val_offset to dir_row16_val_offset + dir_row16_val_l2'length-1), + scout => sov(dir_row16_val_offset to dir_row16_val_offset + dir_row16_val_l2'length-1), + din => dir_row16_val_d, + dout => dir_row16_val_l2); +dir_row18_val_latch: tri_rlmreg_p + generic map (width => dir_row18_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row18_val_offset to dir_row18_val_offset + dir_row18_val_l2'length-1), + scout => sov(dir_row18_val_offset to dir_row18_val_offset + dir_row18_val_l2'length-1), + din => dir_row18_val_d, + dout => dir_row18_val_l2); +dir_row20_val_latch: tri_rlmreg_p + generic map (width => dir_row20_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row20_val_offset to dir_row20_val_offset + dir_row20_val_l2'length-1), + scout => sov(dir_row20_val_offset to dir_row20_val_offset + dir_row20_val_l2'length-1), + din => dir_row20_val_d, + dout => dir_row20_val_l2); +dir_row22_val_latch: tri_rlmreg_p + generic map (width => dir_row22_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row22_val_offset to dir_row22_val_offset + dir_row22_val_l2'length-1), + scout => sov(dir_row22_val_offset to dir_row22_val_offset + dir_row22_val_l2'length-1), + din => dir_row22_val_d, + dout => dir_row22_val_l2); +dir_row24_val_latch: tri_rlmreg_p + generic map (width => dir_row24_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row24_val_offset to dir_row24_val_offset + dir_row24_val_l2'length-1), + scout => sov(dir_row24_val_offset to dir_row24_val_offset + dir_row24_val_l2'length-1), + din => dir_row24_val_d, + dout => dir_row24_val_l2); +dir_row26_val_latch: tri_rlmreg_p + generic map (width => dir_row26_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row26_val_offset to dir_row26_val_offset + dir_row26_val_l2'length-1), + scout => sov(dir_row26_val_offset to dir_row26_val_offset + dir_row26_val_l2'length-1), + din => dir_row26_val_d, + dout => dir_row26_val_l2); +dir_row28_val_latch: tri_rlmreg_p + generic map (width => dir_row28_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row28_val_offset to dir_row28_val_offset + dir_row28_val_l2'length-1), + scout => sov(dir_row28_val_offset to dir_row28_val_offset + dir_row28_val_l2'length-1), + din => dir_row28_val_d, + dout => dir_row28_val_l2); +dir_row30_val_latch: tri_rlmreg_p + generic map (width => dir_row30_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row30_val_offset to dir_row30_val_offset + dir_row30_val_l2'length-1), + scout => sov(dir_row30_val_offset to dir_row30_val_offset + dir_row30_val_l2'length-1), + din => dir_row30_val_d, + dout => dir_row30_val_l2); +dir_row32_val_latch: tri_rlmreg_p + generic map (width => dir_row32_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row32_val_offset to dir_row32_val_offset + dir_row32_val_l2'length-1), + scout => sov(dir_row32_val_offset to dir_row32_val_offset + dir_row32_val_l2'length-1), + din => dir_row32_val_d, + dout => dir_row32_val_l2); +dir_row34_val_latch: tri_rlmreg_p + generic map (width => dir_row34_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row34_val_offset to dir_row34_val_offset + dir_row34_val_l2'length-1), + scout => sov(dir_row34_val_offset to dir_row34_val_offset + dir_row34_val_l2'length-1), + din => dir_row34_val_d, + dout => dir_row34_val_l2); +dir_row36_val_latch: tri_rlmreg_p + generic map (width => dir_row36_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row36_val_offset to dir_row36_val_offset + dir_row36_val_l2'length-1), + scout => sov(dir_row36_val_offset to dir_row36_val_offset + dir_row36_val_l2'length-1), + din => dir_row36_val_d, + dout => dir_row36_val_l2); +dir_row38_val_latch: tri_rlmreg_p + generic map (width => dir_row38_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row38_val_offset to dir_row38_val_offset + dir_row38_val_l2'length-1), + scout => sov(dir_row38_val_offset to dir_row38_val_offset + dir_row38_val_l2'length-1), + din => dir_row38_val_d, + dout => dir_row38_val_l2); +dir_row40_val_latch: tri_rlmreg_p + generic map (width => dir_row40_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row40_val_offset to dir_row40_val_offset + dir_row40_val_l2'length-1), + scout => sov(dir_row40_val_offset to dir_row40_val_offset + dir_row40_val_l2'length-1), + din => dir_row40_val_d, + dout => dir_row40_val_l2); +dir_row42_val_latch: tri_rlmreg_p + generic map (width => dir_row42_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row42_val_offset to dir_row42_val_offset + dir_row42_val_l2'length-1), + scout => sov(dir_row42_val_offset to dir_row42_val_offset + dir_row42_val_l2'length-1), + din => dir_row42_val_d, + dout => dir_row42_val_l2); +dir_row44_val_latch: tri_rlmreg_p + generic map (width => dir_row44_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row44_val_offset to dir_row44_val_offset + dir_row44_val_l2'length-1), + scout => sov(dir_row44_val_offset to dir_row44_val_offset + dir_row44_val_l2'length-1), + din => dir_row44_val_d, + dout => dir_row44_val_l2); +dir_row46_val_latch: tri_rlmreg_p + generic map (width => dir_row46_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row46_val_offset to dir_row46_val_offset + dir_row46_val_l2'length-1), + scout => sov(dir_row46_val_offset to dir_row46_val_offset + dir_row46_val_l2'length-1), + din => dir_row46_val_d, + dout => dir_row46_val_l2); +dir_row48_val_latch: tri_rlmreg_p + generic map (width => dir_row48_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row48_val_offset to dir_row48_val_offset + dir_row48_val_l2'length-1), + scout => sov(dir_row48_val_offset to dir_row48_val_offset + dir_row48_val_l2'length-1), + din => dir_row48_val_d, + dout => dir_row48_val_l2); +dir_row50_val_latch: tri_rlmreg_p + generic map (width => dir_row50_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row50_val_offset to dir_row50_val_offset + dir_row50_val_l2'length-1), + scout => sov(dir_row50_val_offset to dir_row50_val_offset + dir_row50_val_l2'length-1), + din => dir_row50_val_d, + dout => dir_row50_val_l2); +dir_row52_val_latch: tri_rlmreg_p + generic map (width => dir_row52_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row52_val_offset to dir_row52_val_offset + dir_row52_val_l2'length-1), + scout => sov(dir_row52_val_offset to dir_row52_val_offset + dir_row52_val_l2'length-1), + din => dir_row52_val_d, + dout => dir_row52_val_l2); +dir_row54_val_latch: tri_rlmreg_p + generic map (width => dir_row54_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row54_val_offset to dir_row54_val_offset + dir_row54_val_l2'length-1), + scout => sov(dir_row54_val_offset to dir_row54_val_offset + dir_row54_val_l2'length-1), + din => dir_row54_val_d, + dout => dir_row54_val_l2); +dir_row56_val_latch: tri_rlmreg_p + generic map (width => dir_row56_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row56_val_offset to dir_row56_val_offset + dir_row56_val_l2'length-1), + scout => sov(dir_row56_val_offset to dir_row56_val_offset + dir_row56_val_l2'length-1), + din => dir_row56_val_d, + dout => dir_row56_val_l2); +dir_row58_val_latch: tri_rlmreg_p + generic map (width => dir_row58_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row58_val_offset to dir_row58_val_offset + dir_row58_val_l2'length-1), + scout => sov(dir_row58_val_offset to dir_row58_val_offset + dir_row58_val_l2'length-1), + din => dir_row58_val_d, + dout => dir_row58_val_l2); +dir_row60_val_latch: tri_rlmreg_p + generic map (width => dir_row60_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row60_val_offset to dir_row60_val_offset + dir_row60_val_l2'length-1), + scout => sov(dir_row60_val_offset to dir_row60_val_offset + dir_row60_val_l2'length-1), + din => dir_row60_val_d, + dout => dir_row60_val_l2); +dir_row62_val_latch: tri_rlmreg_p + generic map (width => dir_row62_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_even_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row62_val_offset to dir_row62_val_offset + dir_row62_val_l2'length-1), + scout => sov(dir_row62_val_offset to dir_row62_val_offset + dir_row62_val_l2'length-1), + din => dir_row62_val_d, + dout => dir_row62_val_l2); +dir_row0_lru_latch: tri_rlmreg_p + generic map (width => dir_row0_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row0_lru_offset to dir_row0_lru_offset + dir_row0_lru_l2'length-1), + scout => sov(dir_row0_lru_offset to dir_row0_lru_offset + dir_row0_lru_l2'length-1), + din => dir_row0_lru_d, + dout => dir_row0_lru_l2); +dir_row2_lru_latch: tri_rlmreg_p + generic map (width => dir_row2_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row2_lru_offset to dir_row2_lru_offset + dir_row2_lru_l2'length-1), + scout => sov(dir_row2_lru_offset to dir_row2_lru_offset + dir_row2_lru_l2'length-1), + din => dir_row2_lru_d, + dout => dir_row2_lru_l2); +dir_row4_lru_latch: tri_rlmreg_p + generic map (width => dir_row4_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row4_lru_offset to dir_row4_lru_offset + dir_row4_lru_l2'length-1), + scout => sov(dir_row4_lru_offset to dir_row4_lru_offset + dir_row4_lru_l2'length-1), + din => dir_row4_lru_d, + dout => dir_row4_lru_l2); +dir_row6_lru_latch: tri_rlmreg_p + generic map (width => dir_row6_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row6_lru_offset to dir_row6_lru_offset + dir_row6_lru_l2'length-1), + scout => sov(dir_row6_lru_offset to dir_row6_lru_offset + dir_row6_lru_l2'length-1), + din => dir_row6_lru_d, + dout => dir_row6_lru_l2); +dir_row8_lru_latch: tri_rlmreg_p + generic map (width => dir_row8_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row8_lru_offset to dir_row8_lru_offset + dir_row8_lru_l2'length-1), + scout => sov(dir_row8_lru_offset to dir_row8_lru_offset + dir_row8_lru_l2'length-1), + din => dir_row8_lru_d, + dout => dir_row8_lru_l2); +dir_row10_lru_latch: tri_rlmreg_p + generic map (width => dir_row10_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row10_lru_offset to dir_row10_lru_offset + dir_row10_lru_l2'length-1), + scout => sov(dir_row10_lru_offset to dir_row10_lru_offset + dir_row10_lru_l2'length-1), + din => dir_row10_lru_d, + dout => dir_row10_lru_l2); +dir_row12_lru_latch: tri_rlmreg_p + generic map (width => dir_row12_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row12_lru_offset to dir_row12_lru_offset + dir_row12_lru_l2'length-1), + scout => sov(dir_row12_lru_offset to dir_row12_lru_offset + dir_row12_lru_l2'length-1), + din => dir_row12_lru_d, + dout => dir_row12_lru_l2); +dir_row14_lru_latch: tri_rlmreg_p + generic map (width => dir_row14_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row14_lru_offset to dir_row14_lru_offset + dir_row14_lru_l2'length-1), + scout => sov(dir_row14_lru_offset to dir_row14_lru_offset + dir_row14_lru_l2'length-1), + din => dir_row14_lru_d, + dout => dir_row14_lru_l2); +dir_row16_lru_latch: tri_rlmreg_p + generic map (width => dir_row16_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row16_lru_offset to dir_row16_lru_offset + dir_row16_lru_l2'length-1), + scout => sov(dir_row16_lru_offset to dir_row16_lru_offset + dir_row16_lru_l2'length-1), + din => dir_row16_lru_d, + dout => dir_row16_lru_l2); +dir_row18_lru_latch: tri_rlmreg_p + generic map (width => dir_row18_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row18_lru_offset to dir_row18_lru_offset + dir_row18_lru_l2'length-1), + scout => sov(dir_row18_lru_offset to dir_row18_lru_offset + dir_row18_lru_l2'length-1), + din => dir_row18_lru_d, + dout => dir_row18_lru_l2); +dir_row20_lru_latch: tri_rlmreg_p + generic map (width => dir_row20_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row20_lru_offset to dir_row20_lru_offset + dir_row20_lru_l2'length-1), + scout => sov(dir_row20_lru_offset to dir_row20_lru_offset + dir_row20_lru_l2'length-1), + din => dir_row20_lru_d, + dout => dir_row20_lru_l2); +dir_row22_lru_latch: tri_rlmreg_p + generic map (width => dir_row22_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row22_lru_offset to dir_row22_lru_offset + dir_row22_lru_l2'length-1), + scout => sov(dir_row22_lru_offset to dir_row22_lru_offset + dir_row22_lru_l2'length-1), + din => dir_row22_lru_d, + dout => dir_row22_lru_l2); +dir_row24_lru_latch: tri_rlmreg_p + generic map (width => dir_row24_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row24_lru_offset to dir_row24_lru_offset + dir_row24_lru_l2'length-1), + scout => sov(dir_row24_lru_offset to dir_row24_lru_offset + dir_row24_lru_l2'length-1), + din => dir_row24_lru_d, + dout => dir_row24_lru_l2); +dir_row26_lru_latch: tri_rlmreg_p + generic map (width => dir_row26_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row26_lru_offset to dir_row26_lru_offset + dir_row26_lru_l2'length-1), + scout => sov(dir_row26_lru_offset to dir_row26_lru_offset + dir_row26_lru_l2'length-1), + din => dir_row26_lru_d, + dout => dir_row26_lru_l2); +dir_row28_lru_latch: tri_rlmreg_p + generic map (width => dir_row28_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row28_lru_offset to dir_row28_lru_offset + dir_row28_lru_l2'length-1), + scout => sov(dir_row28_lru_offset to dir_row28_lru_offset + dir_row28_lru_l2'length-1), + din => dir_row28_lru_d, + dout => dir_row28_lru_l2); +dir_row30_lru_latch: tri_rlmreg_p + generic map (width => dir_row30_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row30_lru_offset to dir_row30_lru_offset + dir_row30_lru_l2'length-1), + scout => sov(dir_row30_lru_offset to dir_row30_lru_offset + dir_row30_lru_l2'length-1), + din => dir_row30_lru_d, + dout => dir_row30_lru_l2); +dir_row32_lru_latch: tri_rlmreg_p + generic map (width => dir_row32_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row32_lru_offset to dir_row32_lru_offset + dir_row32_lru_l2'length-1), + scout => sov(dir_row32_lru_offset to dir_row32_lru_offset + dir_row32_lru_l2'length-1), + din => dir_row32_lru_d, + dout => dir_row32_lru_l2); +dir_row34_lru_latch: tri_rlmreg_p + generic map (width => dir_row34_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row34_lru_offset to dir_row34_lru_offset + dir_row34_lru_l2'length-1), + scout => sov(dir_row34_lru_offset to dir_row34_lru_offset + dir_row34_lru_l2'length-1), + din => dir_row34_lru_d, + dout => dir_row34_lru_l2); +dir_row36_lru_latch: tri_rlmreg_p + generic map (width => dir_row36_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row36_lru_offset to dir_row36_lru_offset + dir_row36_lru_l2'length-1), + scout => sov(dir_row36_lru_offset to dir_row36_lru_offset + dir_row36_lru_l2'length-1), + din => dir_row36_lru_d, + dout => dir_row36_lru_l2); +dir_row38_lru_latch: tri_rlmreg_p + generic map (width => dir_row38_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row38_lru_offset to dir_row38_lru_offset + dir_row38_lru_l2'length-1), + scout => sov(dir_row38_lru_offset to dir_row38_lru_offset + dir_row38_lru_l2'length-1), + din => dir_row38_lru_d, + dout => dir_row38_lru_l2); +dir_row40_lru_latch: tri_rlmreg_p + generic map (width => dir_row40_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row40_lru_offset to dir_row40_lru_offset + dir_row40_lru_l2'length-1), + scout => sov(dir_row40_lru_offset to dir_row40_lru_offset + dir_row40_lru_l2'length-1), + din => dir_row40_lru_d, + dout => dir_row40_lru_l2); +dir_row42_lru_latch: tri_rlmreg_p + generic map (width => dir_row42_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row42_lru_offset to dir_row42_lru_offset + dir_row42_lru_l2'length-1), + scout => sov(dir_row42_lru_offset to dir_row42_lru_offset + dir_row42_lru_l2'length-1), + din => dir_row42_lru_d, + dout => dir_row42_lru_l2); +dir_row44_lru_latch: tri_rlmreg_p + generic map (width => dir_row44_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row44_lru_offset to dir_row44_lru_offset + dir_row44_lru_l2'length-1), + scout => sov(dir_row44_lru_offset to dir_row44_lru_offset + dir_row44_lru_l2'length-1), + din => dir_row44_lru_d, + dout => dir_row44_lru_l2); +dir_row46_lru_latch: tri_rlmreg_p + generic map (width => dir_row46_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row46_lru_offset to dir_row46_lru_offset + dir_row46_lru_l2'length-1), + scout => sov(dir_row46_lru_offset to dir_row46_lru_offset + dir_row46_lru_l2'length-1), + din => dir_row46_lru_d, + dout => dir_row46_lru_l2); +dir_row48_lru_latch: tri_rlmreg_p + generic map (width => dir_row48_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row48_lru_offset to dir_row48_lru_offset + dir_row48_lru_l2'length-1), + scout => sov(dir_row48_lru_offset to dir_row48_lru_offset + dir_row48_lru_l2'length-1), + din => dir_row48_lru_d, + dout => dir_row48_lru_l2); +dir_row50_lru_latch: tri_rlmreg_p + generic map (width => dir_row50_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row50_lru_offset to dir_row50_lru_offset + dir_row50_lru_l2'length-1), + scout => sov(dir_row50_lru_offset to dir_row50_lru_offset + dir_row50_lru_l2'length-1), + din => dir_row50_lru_d, + dout => dir_row50_lru_l2); +dir_row52_lru_latch: tri_rlmreg_p + generic map (width => dir_row52_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row52_lru_offset to dir_row52_lru_offset + dir_row52_lru_l2'length-1), + scout => sov(dir_row52_lru_offset to dir_row52_lru_offset + dir_row52_lru_l2'length-1), + din => dir_row52_lru_d, + dout => dir_row52_lru_l2); +dir_row54_lru_latch: tri_rlmreg_p + generic map (width => dir_row54_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row54_lru_offset to dir_row54_lru_offset + dir_row54_lru_l2'length-1), + scout => sov(dir_row54_lru_offset to dir_row54_lru_offset + dir_row54_lru_l2'length-1), + din => dir_row54_lru_d, + dout => dir_row54_lru_l2); +dir_row56_lru_latch: tri_rlmreg_p + generic map (width => dir_row56_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row56_lru_offset to dir_row56_lru_offset + dir_row56_lru_l2'length-1), + scout => sov(dir_row56_lru_offset to dir_row56_lru_offset + dir_row56_lru_l2'length-1), + din => dir_row56_lru_d, + dout => dir_row56_lru_l2); +dir_row58_lru_latch: tri_rlmreg_p + generic map (width => dir_row58_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row58_lru_offset to dir_row58_lru_offset + dir_row58_lru_l2'length-1), + scout => sov(dir_row58_lru_offset to dir_row58_lru_offset + dir_row58_lru_l2'length-1), + din => dir_row58_lru_d, + dout => dir_row58_lru_l2); +dir_row60_lru_latch: tri_rlmreg_p + generic map (width => dir_row60_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row60_lru_offset to dir_row60_lru_offset + dir_row60_lru_l2'length-1), + scout => sov(dir_row60_lru_offset to dir_row60_lru_offset + dir_row60_lru_l2'length-1), + din => dir_row60_lru_d, + dout => dir_row60_lru_l2); +dir_row62_lru_latch: tri_rlmreg_p + generic map (width => dir_row62_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_even_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row62_lru_offset to dir_row62_lru_offset + dir_row62_lru_l2'length-1), + scout => sov(dir_row62_lru_offset to dir_row62_lru_offset + dir_row62_lru_l2'length-1), + din => dir_row62_lru_d, + dout => dir_row62_lru_l2); +dir_row1_val_latch: tri_rlmreg_p + generic map (width => dir_row1_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row1_val_offset to dir_row1_val_offset + dir_row1_val_l2'length-1), + scout => sov(dir_row1_val_offset to dir_row1_val_offset + dir_row1_val_l2'length-1), + din => dir_row1_val_d, + dout => dir_row1_val_l2); +dir_row3_val_latch: tri_rlmreg_p + generic map (width => dir_row3_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row3_val_offset to dir_row3_val_offset + dir_row3_val_l2'length-1), + scout => sov(dir_row3_val_offset to dir_row3_val_offset + dir_row3_val_l2'length-1), + din => dir_row3_val_d, + dout => dir_row3_val_l2); +dir_row5_val_latch: tri_rlmreg_p + generic map (width => dir_row5_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row5_val_offset to dir_row5_val_offset + dir_row5_val_l2'length-1), + scout => sov(dir_row5_val_offset to dir_row5_val_offset + dir_row5_val_l2'length-1), + din => dir_row5_val_d, + dout => dir_row5_val_l2); +dir_row7_val_latch: tri_rlmreg_p + generic map (width => dir_row7_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row7_val_offset to dir_row7_val_offset + dir_row7_val_l2'length-1), + scout => sov(dir_row7_val_offset to dir_row7_val_offset + dir_row7_val_l2'length-1), + din => dir_row7_val_d, + dout => dir_row7_val_l2); +dir_row9_val_latch: tri_rlmreg_p + generic map (width => dir_row9_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row9_val_offset to dir_row9_val_offset + dir_row9_val_l2'length-1), + scout => sov(dir_row9_val_offset to dir_row9_val_offset + dir_row9_val_l2'length-1), + din => dir_row9_val_d, + dout => dir_row9_val_l2); +dir_row11_val_latch: tri_rlmreg_p + generic map (width => dir_row11_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row11_val_offset to dir_row11_val_offset + dir_row11_val_l2'length-1), + scout => sov(dir_row11_val_offset to dir_row11_val_offset + dir_row11_val_l2'length-1), + din => dir_row11_val_d, + dout => dir_row11_val_l2); +dir_row13_val_latch: tri_rlmreg_p + generic map (width => dir_row13_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row13_val_offset to dir_row13_val_offset + dir_row13_val_l2'length-1), + scout => sov(dir_row13_val_offset to dir_row13_val_offset + dir_row13_val_l2'length-1), + din => dir_row13_val_d, + dout => dir_row13_val_l2); +dir_row15_val_latch: tri_rlmreg_p + generic map (width => dir_row15_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row15_val_offset to dir_row15_val_offset + dir_row15_val_l2'length-1), + scout => sov(dir_row15_val_offset to dir_row15_val_offset + dir_row15_val_l2'length-1), + din => dir_row15_val_d, + dout => dir_row15_val_l2); +dir_row17_val_latch: tri_rlmreg_p + generic map (width => dir_row17_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row17_val_offset to dir_row17_val_offset + dir_row17_val_l2'length-1), + scout => sov(dir_row17_val_offset to dir_row17_val_offset + dir_row17_val_l2'length-1), + din => dir_row17_val_d, + dout => dir_row17_val_l2); +dir_row19_val_latch: tri_rlmreg_p + generic map (width => dir_row19_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row19_val_offset to dir_row19_val_offset + dir_row19_val_l2'length-1), + scout => sov(dir_row19_val_offset to dir_row19_val_offset + dir_row19_val_l2'length-1), + din => dir_row19_val_d, + dout => dir_row19_val_l2); +dir_row21_val_latch: tri_rlmreg_p + generic map (width => dir_row21_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row21_val_offset to dir_row21_val_offset + dir_row21_val_l2'length-1), + scout => sov(dir_row21_val_offset to dir_row21_val_offset + dir_row21_val_l2'length-1), + din => dir_row21_val_d, + dout => dir_row21_val_l2); +dir_row23_val_latch: tri_rlmreg_p + generic map (width => dir_row23_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row23_val_offset to dir_row23_val_offset + dir_row23_val_l2'length-1), + scout => sov(dir_row23_val_offset to dir_row23_val_offset + dir_row23_val_l2'length-1), + din => dir_row23_val_d, + dout => dir_row23_val_l2); +dir_row25_val_latch: tri_rlmreg_p + generic map (width => dir_row25_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row25_val_offset to dir_row25_val_offset + dir_row25_val_l2'length-1), + scout => sov(dir_row25_val_offset to dir_row25_val_offset + dir_row25_val_l2'length-1), + din => dir_row25_val_d, + dout => dir_row25_val_l2); +dir_row27_val_latch: tri_rlmreg_p + generic map (width => dir_row27_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row27_val_offset to dir_row27_val_offset + dir_row27_val_l2'length-1), + scout => sov(dir_row27_val_offset to dir_row27_val_offset + dir_row27_val_l2'length-1), + din => dir_row27_val_d, + dout => dir_row27_val_l2); +dir_row29_val_latch: tri_rlmreg_p + generic map (width => dir_row29_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row29_val_offset to dir_row29_val_offset + dir_row29_val_l2'length-1), + scout => sov(dir_row29_val_offset to dir_row29_val_offset + dir_row29_val_l2'length-1), + din => dir_row29_val_d, + dout => dir_row29_val_l2); +dir_row31_val_latch: tri_rlmreg_p + generic map (width => dir_row31_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row31_val_offset to dir_row31_val_offset + dir_row31_val_l2'length-1), + scout => sov(dir_row31_val_offset to dir_row31_val_offset + dir_row31_val_l2'length-1), + din => dir_row31_val_d, + dout => dir_row31_val_l2); +dir_row33_val_latch: tri_rlmreg_p + generic map (width => dir_row33_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row33_val_offset to dir_row33_val_offset + dir_row33_val_l2'length-1), + scout => sov(dir_row33_val_offset to dir_row33_val_offset + dir_row33_val_l2'length-1), + din => dir_row33_val_d, + dout => dir_row33_val_l2); +dir_row35_val_latch: tri_rlmreg_p + generic map (width => dir_row35_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row35_val_offset to dir_row35_val_offset + dir_row35_val_l2'length-1), + scout => sov(dir_row35_val_offset to dir_row35_val_offset + dir_row35_val_l2'length-1), + din => dir_row35_val_d, + dout => dir_row35_val_l2); +dir_row37_val_latch: tri_rlmreg_p + generic map (width => dir_row37_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row37_val_offset to dir_row37_val_offset + dir_row37_val_l2'length-1), + scout => sov(dir_row37_val_offset to dir_row37_val_offset + dir_row37_val_l2'length-1), + din => dir_row37_val_d, + dout => dir_row37_val_l2); +dir_row39_val_latch: tri_rlmreg_p + generic map (width => dir_row39_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row39_val_offset to dir_row39_val_offset + dir_row39_val_l2'length-1), + scout => sov(dir_row39_val_offset to dir_row39_val_offset + dir_row39_val_l2'length-1), + din => dir_row39_val_d, + dout => dir_row39_val_l2); +dir_row41_val_latch: tri_rlmreg_p + generic map (width => dir_row41_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row41_val_offset to dir_row41_val_offset + dir_row41_val_l2'length-1), + scout => sov(dir_row41_val_offset to dir_row41_val_offset + dir_row41_val_l2'length-1), + din => dir_row41_val_d, + dout => dir_row41_val_l2); +dir_row43_val_latch: tri_rlmreg_p + generic map (width => dir_row43_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row43_val_offset to dir_row43_val_offset + dir_row43_val_l2'length-1), + scout => sov(dir_row43_val_offset to dir_row43_val_offset + dir_row43_val_l2'length-1), + din => dir_row43_val_d, + dout => dir_row43_val_l2); +dir_row45_val_latch: tri_rlmreg_p + generic map (width => dir_row45_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row45_val_offset to dir_row45_val_offset + dir_row45_val_l2'length-1), + scout => sov(dir_row45_val_offset to dir_row45_val_offset + dir_row45_val_l2'length-1), + din => dir_row45_val_d, + dout => dir_row45_val_l2); +dir_row47_val_latch: tri_rlmreg_p + generic map (width => dir_row47_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row47_val_offset to dir_row47_val_offset + dir_row47_val_l2'length-1), + scout => sov(dir_row47_val_offset to dir_row47_val_offset + dir_row47_val_l2'length-1), + din => dir_row47_val_d, + dout => dir_row47_val_l2); +dir_row49_val_latch: tri_rlmreg_p + generic map (width => dir_row49_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row49_val_offset to dir_row49_val_offset + dir_row49_val_l2'length-1), + scout => sov(dir_row49_val_offset to dir_row49_val_offset + dir_row49_val_l2'length-1), + din => dir_row49_val_d, + dout => dir_row49_val_l2); +dir_row51_val_latch: tri_rlmreg_p + generic map (width => dir_row51_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row51_val_offset to dir_row51_val_offset + dir_row51_val_l2'length-1), + scout => sov(dir_row51_val_offset to dir_row51_val_offset + dir_row51_val_l2'length-1), + din => dir_row51_val_d, + dout => dir_row51_val_l2); +dir_row53_val_latch: tri_rlmreg_p + generic map (width => dir_row53_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row53_val_offset to dir_row53_val_offset + dir_row53_val_l2'length-1), + scout => sov(dir_row53_val_offset to dir_row53_val_offset + dir_row53_val_l2'length-1), + din => dir_row53_val_d, + dout => dir_row53_val_l2); +dir_row55_val_latch: tri_rlmreg_p + generic map (width => dir_row55_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row55_val_offset to dir_row55_val_offset + dir_row55_val_l2'length-1), + scout => sov(dir_row55_val_offset to dir_row55_val_offset + dir_row55_val_l2'length-1), + din => dir_row55_val_d, + dout => dir_row55_val_l2); +dir_row57_val_latch: tri_rlmreg_p + generic map (width => dir_row57_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row57_val_offset to dir_row57_val_offset + dir_row57_val_l2'length-1), + scout => sov(dir_row57_val_offset to dir_row57_val_offset + dir_row57_val_l2'length-1), + din => dir_row57_val_d, + dout => dir_row57_val_l2); +dir_row59_val_latch: tri_rlmreg_p + generic map (width => dir_row59_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row59_val_offset to dir_row59_val_offset + dir_row59_val_l2'length-1), + scout => sov(dir_row59_val_offset to dir_row59_val_offset + dir_row59_val_l2'length-1), + din => dir_row59_val_d, + dout => dir_row59_val_l2); +dir_row61_val_latch: tri_rlmreg_p + generic map (width => dir_row61_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row61_val_offset to dir_row61_val_offset + dir_row61_val_l2'length-1), + scout => sov(dir_row61_val_offset to dir_row61_val_offset + dir_row61_val_l2'length-1), + din => dir_row61_val_d, + dout => dir_row61_val_l2); +dir_row63_val_latch: tri_rlmreg_p + generic map (width => dir_row63_val_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_val_odd_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row63_val_offset to dir_row63_val_offset + dir_row63_val_l2'length-1), + scout => sov(dir_row63_val_offset to dir_row63_val_offset + dir_row63_val_l2'length-1), + din => dir_row63_val_d, + dout => dir_row63_val_l2); +dir_row1_lru_latch: tri_rlmreg_p + generic map (width => dir_row1_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row1_lru_offset to dir_row1_lru_offset + dir_row1_lru_l2'length-1), + scout => sov(dir_row1_lru_offset to dir_row1_lru_offset + dir_row1_lru_l2'length-1), + din => dir_row1_lru_d, + dout => dir_row1_lru_l2); +dir_row3_lru_latch: tri_rlmreg_p + generic map (width => dir_row3_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row3_lru_offset to dir_row3_lru_offset + dir_row3_lru_l2'length-1), + scout => sov(dir_row3_lru_offset to dir_row3_lru_offset + dir_row3_lru_l2'length-1), + din => dir_row3_lru_d, + dout => dir_row3_lru_l2); +dir_row5_lru_latch: tri_rlmreg_p + generic map (width => dir_row5_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row5_lru_offset to dir_row5_lru_offset + dir_row5_lru_l2'length-1), + scout => sov(dir_row5_lru_offset to dir_row5_lru_offset + dir_row5_lru_l2'length-1), + din => dir_row5_lru_d, + dout => dir_row5_lru_l2); +dir_row7_lru_latch: tri_rlmreg_p + generic map (width => dir_row7_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row7_lru_offset to dir_row7_lru_offset + dir_row7_lru_l2'length-1), + scout => sov(dir_row7_lru_offset to dir_row7_lru_offset + dir_row7_lru_l2'length-1), + din => dir_row7_lru_d, + dout => dir_row7_lru_l2); +dir_row9_lru_latch: tri_rlmreg_p + generic map (width => dir_row9_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row9_lru_offset to dir_row9_lru_offset + dir_row9_lru_l2'length-1), + scout => sov(dir_row9_lru_offset to dir_row9_lru_offset + dir_row9_lru_l2'length-1), + din => dir_row9_lru_d, + dout => dir_row9_lru_l2); +dir_row11_lru_latch: tri_rlmreg_p + generic map (width => dir_row11_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row11_lru_offset to dir_row11_lru_offset + dir_row11_lru_l2'length-1), + scout => sov(dir_row11_lru_offset to dir_row11_lru_offset + dir_row11_lru_l2'length-1), + din => dir_row11_lru_d, + dout => dir_row11_lru_l2); +dir_row13_lru_latch: tri_rlmreg_p + generic map (width => dir_row13_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row13_lru_offset to dir_row13_lru_offset + dir_row13_lru_l2'length-1), + scout => sov(dir_row13_lru_offset to dir_row13_lru_offset + dir_row13_lru_l2'length-1), + din => dir_row13_lru_d, + dout => dir_row13_lru_l2); +dir_row15_lru_latch: tri_rlmreg_p + generic map (width => dir_row15_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row15_lru_offset to dir_row15_lru_offset + dir_row15_lru_l2'length-1), + scout => sov(dir_row15_lru_offset to dir_row15_lru_offset + dir_row15_lru_l2'length-1), + din => dir_row15_lru_d, + dout => dir_row15_lru_l2); +dir_row17_lru_latch: tri_rlmreg_p + generic map (width => dir_row17_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row17_lru_offset to dir_row17_lru_offset + dir_row17_lru_l2'length-1), + scout => sov(dir_row17_lru_offset to dir_row17_lru_offset + dir_row17_lru_l2'length-1), + din => dir_row17_lru_d, + dout => dir_row17_lru_l2); +dir_row19_lru_latch: tri_rlmreg_p + generic map (width => dir_row19_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row19_lru_offset to dir_row19_lru_offset + dir_row19_lru_l2'length-1), + scout => sov(dir_row19_lru_offset to dir_row19_lru_offset + dir_row19_lru_l2'length-1), + din => dir_row19_lru_d, + dout => dir_row19_lru_l2); +dir_row21_lru_latch: tri_rlmreg_p + generic map (width => dir_row21_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row21_lru_offset to dir_row21_lru_offset + dir_row21_lru_l2'length-1), + scout => sov(dir_row21_lru_offset to dir_row21_lru_offset + dir_row21_lru_l2'length-1), + din => dir_row21_lru_d, + dout => dir_row21_lru_l2); +dir_row23_lru_latch: tri_rlmreg_p + generic map (width => dir_row23_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row23_lru_offset to dir_row23_lru_offset + dir_row23_lru_l2'length-1), + scout => sov(dir_row23_lru_offset to dir_row23_lru_offset + dir_row23_lru_l2'length-1), + din => dir_row23_lru_d, + dout => dir_row23_lru_l2); +dir_row25_lru_latch: tri_rlmreg_p + generic map (width => dir_row25_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row25_lru_offset to dir_row25_lru_offset + dir_row25_lru_l2'length-1), + scout => sov(dir_row25_lru_offset to dir_row25_lru_offset + dir_row25_lru_l2'length-1), + din => dir_row25_lru_d, + dout => dir_row25_lru_l2); +dir_row27_lru_latch: tri_rlmreg_p + generic map (width => dir_row27_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row27_lru_offset to dir_row27_lru_offset + dir_row27_lru_l2'length-1), + scout => sov(dir_row27_lru_offset to dir_row27_lru_offset + dir_row27_lru_l2'length-1), + din => dir_row27_lru_d, + dout => dir_row27_lru_l2); +dir_row29_lru_latch: tri_rlmreg_p + generic map (width => dir_row29_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row29_lru_offset to dir_row29_lru_offset + dir_row29_lru_l2'length-1), + scout => sov(dir_row29_lru_offset to dir_row29_lru_offset + dir_row29_lru_l2'length-1), + din => dir_row29_lru_d, + dout => dir_row29_lru_l2); +dir_row31_lru_latch: tri_rlmreg_p + generic map (width => dir_row31_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row31_lru_offset to dir_row31_lru_offset + dir_row31_lru_l2'length-1), + scout => sov(dir_row31_lru_offset to dir_row31_lru_offset + dir_row31_lru_l2'length-1), + din => dir_row31_lru_d, + dout => dir_row31_lru_l2); +dir_row33_lru_latch: tri_rlmreg_p + generic map (width => dir_row33_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row33_lru_offset to dir_row33_lru_offset + dir_row33_lru_l2'length-1), + scout => sov(dir_row33_lru_offset to dir_row33_lru_offset + dir_row33_lru_l2'length-1), + din => dir_row33_lru_d, + dout => dir_row33_lru_l2); +dir_row35_lru_latch: tri_rlmreg_p + generic map (width => dir_row35_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row35_lru_offset to dir_row35_lru_offset + dir_row35_lru_l2'length-1), + scout => sov(dir_row35_lru_offset to dir_row35_lru_offset + dir_row35_lru_l2'length-1), + din => dir_row35_lru_d, + dout => dir_row35_lru_l2); +dir_row37_lru_latch: tri_rlmreg_p + generic map (width => dir_row37_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row37_lru_offset to dir_row37_lru_offset + dir_row37_lru_l2'length-1), + scout => sov(dir_row37_lru_offset to dir_row37_lru_offset + dir_row37_lru_l2'length-1), + din => dir_row37_lru_d, + dout => dir_row37_lru_l2); +dir_row39_lru_latch: tri_rlmreg_p + generic map (width => dir_row39_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row39_lru_offset to dir_row39_lru_offset + dir_row39_lru_l2'length-1), + scout => sov(dir_row39_lru_offset to dir_row39_lru_offset + dir_row39_lru_l2'length-1), + din => dir_row39_lru_d, + dout => dir_row39_lru_l2); +dir_row41_lru_latch: tri_rlmreg_p + generic map (width => dir_row41_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row41_lru_offset to dir_row41_lru_offset + dir_row41_lru_l2'length-1), + scout => sov(dir_row41_lru_offset to dir_row41_lru_offset + dir_row41_lru_l2'length-1), + din => dir_row41_lru_d, + dout => dir_row41_lru_l2); +dir_row43_lru_latch: tri_rlmreg_p + generic map (width => dir_row43_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row43_lru_offset to dir_row43_lru_offset + dir_row43_lru_l2'length-1), + scout => sov(dir_row43_lru_offset to dir_row43_lru_offset + dir_row43_lru_l2'length-1), + din => dir_row43_lru_d, + dout => dir_row43_lru_l2); +dir_row45_lru_latch: tri_rlmreg_p + generic map (width => dir_row45_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row45_lru_offset to dir_row45_lru_offset + dir_row45_lru_l2'length-1), + scout => sov(dir_row45_lru_offset to dir_row45_lru_offset + dir_row45_lru_l2'length-1), + din => dir_row45_lru_d, + dout => dir_row45_lru_l2); +dir_row47_lru_latch: tri_rlmreg_p + generic map (width => dir_row47_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row47_lru_offset to dir_row47_lru_offset + dir_row47_lru_l2'length-1), + scout => sov(dir_row47_lru_offset to dir_row47_lru_offset + dir_row47_lru_l2'length-1), + din => dir_row47_lru_d, + dout => dir_row47_lru_l2); +dir_row49_lru_latch: tri_rlmreg_p + generic map (width => dir_row49_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row49_lru_offset to dir_row49_lru_offset + dir_row49_lru_l2'length-1), + scout => sov(dir_row49_lru_offset to dir_row49_lru_offset + dir_row49_lru_l2'length-1), + din => dir_row49_lru_d, + dout => dir_row49_lru_l2); +dir_row51_lru_latch: tri_rlmreg_p + generic map (width => dir_row51_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row51_lru_offset to dir_row51_lru_offset + dir_row51_lru_l2'length-1), + scout => sov(dir_row51_lru_offset to dir_row51_lru_offset + dir_row51_lru_l2'length-1), + din => dir_row51_lru_d, + dout => dir_row51_lru_l2); +dir_row53_lru_latch: tri_rlmreg_p + generic map (width => dir_row53_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row53_lru_offset to dir_row53_lru_offset + dir_row53_lru_l2'length-1), + scout => sov(dir_row53_lru_offset to dir_row53_lru_offset + dir_row53_lru_l2'length-1), + din => dir_row53_lru_d, + dout => dir_row53_lru_l2); +dir_row55_lru_latch: tri_rlmreg_p + generic map (width => dir_row55_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row55_lru_offset to dir_row55_lru_offset + dir_row55_lru_l2'length-1), + scout => sov(dir_row55_lru_offset to dir_row55_lru_offset + dir_row55_lru_l2'length-1), + din => dir_row55_lru_d, + dout => dir_row55_lru_l2); +dir_row57_lru_latch: tri_rlmreg_p + generic map (width => dir_row57_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row57_lru_offset to dir_row57_lru_offset + dir_row57_lru_l2'length-1), + scout => sov(dir_row57_lru_offset to dir_row57_lru_offset + dir_row57_lru_l2'length-1), + din => dir_row57_lru_d, + dout => dir_row57_lru_l2); +dir_row59_lru_latch: tri_rlmreg_p + generic map (width => dir_row59_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row59_lru_offset to dir_row59_lru_offset + dir_row59_lru_l2'length-1), + scout => sov(dir_row59_lru_offset to dir_row59_lru_offset + dir_row59_lru_l2'length-1), + din => dir_row59_lru_d, + dout => dir_row59_lru_l2); +dir_row61_lru_latch: tri_rlmreg_p + generic map (width => dir_row61_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row61_lru_offset to dir_row61_lru_offset + dir_row61_lru_l2'length-1), + scout => sov(dir_row61_lru_offset to dir_row61_lru_offset + dir_row61_lru_l2'length-1), + din => dir_row61_lru_d, + dout => dir_row61_lru_l2); +dir_row63_lru_latch: tri_rlmreg_p + generic map (width => dir_row63_lru_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_row_lru_odd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dir_row63_lru_offset to dir_row63_lru_offset + dir_row63_lru_l2'length-1), + scout => sov(dir_row63_lru_offset to dir_row63_lru_offset + dir_row63_lru_l2'length-1), + din => dir_row63_lru_d, + dout => dir_row63_lru_l2); +-- IU3 +iu3_instr_valid_latch: tri_rlmreg_p + generic map (width => iu3_instr_valid_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu3_instr_valid_offset to iu3_instr_valid_offset + iu3_instr_valid_l2'length-1), + scout => sov(iu3_instr_valid_offset to iu3_instr_valid_offset + iu3_instr_valid_l2'length-1), + din => iu3_instr_valid_d, + dout => iu3_instr_valid_l2); +iu3_tid_latch: tri_rlmreg_p + generic map (width => iu3_tid_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu3_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu3_tid_offset to iu3_tid_offset + iu3_tid_l2'length-1), + scout => sov(iu3_tid_offset to iu3_tid_offset + iu3_tid_l2'length-1), + din => iu3_tid_d, + dout => iu3_tid_l2); +iu3_ifar_latch: tri_rlmreg_p + generic map (width => iu3_ifar_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu3_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu3_ifar_offset to iu3_ifar_offset + iu3_ifar_l2'length-1), + scout => sov(iu3_ifar_offset to iu3_ifar_offset + iu3_ifar_l2'length-1), + din => iu3_ifar_d, + dout => iu3_ifar_l2); +iu3_ifar_dec_latch: tri_rlmreg_p + generic map (width => iu3_ifar_dec_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu3_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu3_ifar_dec_offset to iu3_ifar_dec_offset + iu3_ifar_dec_l2'length-1), + scout => sov(iu3_ifar_dec_offset to iu3_ifar_dec_offset + iu3_ifar_dec_l2'length-1), + din => iu3_ifar_dec_d, + dout => iu3_ifar_dec_l2); +iu3_2ucode_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu3_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu3_2ucode_offset), + scout => sov(iu3_2ucode_offset), + din => iu3_2ucode_d, + dout => iu3_2ucode_l2); +iu3_2ucode_type_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu3_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu3_2ucode_type_offset), + scout => sov(iu3_2ucode_type_offset), + din => iu3_2ucode_type_d, + dout => iu3_2ucode_type_l2); +iu3_erat_err_latch: tri_rlmreg_p + generic map (width => iu3_erat_err_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu3_erat_err_offset to iu3_erat_err_offset + iu3_erat_err_l2'length-1), + scout => sov(iu3_erat_err_offset to iu3_erat_err_offset + iu3_erat_err_l2'length-1), + din => iu3_erat_err_d, + dout => iu3_erat_err_l2); +iu3_dir_parity_err_way_latch: tri_rlmreg_p + generic map (width => iu3_dir_parity_err_way_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu3_parity_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu3_dir_parity_err_way_offset to iu3_dir_parity_err_way_offset + iu3_dir_parity_err_way_l2'length-1), + scout => sov(iu3_dir_parity_err_way_offset to iu3_dir_parity_err_way_offset + iu3_dir_parity_err_way_l2'length-1), + din => iu3_dir_parity_err_way_d, + dout => iu3_dir_parity_err_way_l2); +iu3_data_parity_err_way_latch: tri_rlmreg_p + generic map (width => iu3_data_parity_err_way_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu3_parity_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu3_data_parity_err_way_offset to iu3_data_parity_err_way_offset + iu3_data_parity_err_way_l2'length-1), + scout => sov(iu3_data_parity_err_way_offset to iu3_data_parity_err_way_offset + iu3_data_parity_err_way_l2'length-1), + din => iu3_data_parity_err_way_d, + dout => iu3_data_parity_err_way_l2); +iu3_parity_needs_flush_latch: tri_rlmreg_p + generic map (width => iu3_parity_needs_flush_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu3_parity_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu3_parity_needs_flush_offset to iu3_parity_needs_flush_offset + iu3_parity_needs_flush_l2'length-1), + scout => sov(iu3_parity_needs_flush_offset to iu3_parity_needs_flush_offset + iu3_parity_needs_flush_l2'length-1), + din => iu3_parity_needs_flush_d, + dout => iu3_parity_needs_flush_l2); +iu3_parity_tag_latch: tri_rlmreg_p + generic map (width => iu3_parity_tag_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu3_parity_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu3_parity_tag_offset to iu3_parity_tag_offset + iu3_parity_tag_l2'length-1), + scout => sov(iu3_parity_tag_offset to iu3_parity_tag_offset + iu3_parity_tag_l2'length-1), + din => iu3_parity_tag_d, + dout => iu3_parity_tag_l2); +iu3_rd_parity_err_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu3_parity_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu3_rd_parity_err_offset), + scout => sov(iu3_rd_parity_err_offset), + din => iu3_rd_parity_err_d, + dout => iu3_rd_parity_err_l2); +iu3_rd_miss_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu3_rd_miss_offset), + scout => sov(iu3_rd_miss_offset), + din => iu3_rd_miss_d, + dout => iu3_rd_miss_l2); +err_icache_parity_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(err_icache_parity_offset), + scout => sov(err_icache_parity_offset), + din => err_icache_parity_d, + dout => err_icache_parity_l2); +err_icachedir_parity_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu3_parity_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(err_icachedir_parity_offset), + scout => sov(err_icachedir_parity_offset), + din => err_icachedir_parity_d, + dout => err_icachedir_parity_l2); +iu3_multihit_err_way_latch: tri_rlmreg_p + generic map (width => iu3_multihit_err_way_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu3_parity_act, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu3_multihit_err_way_offset to iu3_multihit_err_way_offset + iu3_multihit_err_way_l2'length-1), + scout => sov(iu3_multihit_err_way_offset to iu3_multihit_err_way_offset + iu3_multihit_err_way_l2'length-1), + din => iu3_multihit_err_way_d, + dout => iu3_multihit_err_way_l2); +iu3_multihit_flush_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu3_parity_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu3_multihit_flush_offset), + scout => sov(iu3_multihit_flush_offset), + din => iu3_multihit_flush_d, + dout => iu3_multihit_flush_l2); +perf_instr_count_t0_latch: tri_rlmreg_p + generic map (width => perf_instr_count_t0_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu3_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(perf_instr_count_t0_offset to perf_instr_count_t0_offset + perf_instr_count_t0_l2'length-1), + scout => sov(perf_instr_count_t0_offset to perf_instr_count_t0_offset + perf_instr_count_t0_l2'length-1), + din => perf_instr_count_t0_d, + dout => perf_instr_count_t0_l2); +perf_instr_count_t1_latch: tri_rlmreg_p + generic map (width => perf_instr_count_t1_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu3_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(perf_instr_count_t1_offset to perf_instr_count_t1_offset + perf_instr_count_t1_l2'length-1), + scout => sov(perf_instr_count_t1_offset to perf_instr_count_t1_offset + perf_instr_count_t1_l2'length-1), + din => perf_instr_count_t1_d, + dout => perf_instr_count_t1_l2); +perf_instr_count_t2_latch: tri_rlmreg_p + generic map (width => perf_instr_count_t2_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu3_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(perf_instr_count_t2_offset to perf_instr_count_t2_offset + perf_instr_count_t2_l2'length-1), + scout => sov(perf_instr_count_t2_offset to perf_instr_count_t2_offset + perf_instr_count_t2_l2'length-1), + din => perf_instr_count_t2_d, + dout => perf_instr_count_t2_l2); +perf_instr_count_t3_latch: tri_rlmreg_p + generic map (width => perf_instr_count_t3_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu3_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(perf_instr_count_t3_offset to perf_instr_count_t3_offset + perf_instr_count_t3_l2'length-1), + scout => sov(perf_instr_count_t3_offset to perf_instr_count_t3_offset + perf_instr_count_t3_l2'length-1), + din => perf_instr_count_t3_d, + dout => perf_instr_count_t3_l2); +perf_event_t0_latch: tri_rlmreg_p + generic map (width => perf_event_t0_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => event_bus_enable, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(perf_event_t0_offset to perf_event_t0_offset + perf_event_t0_l2'length-1), + scout => sov(perf_event_t0_offset to perf_event_t0_offset + perf_event_t0_l2'length-1), + din => perf_event_t0_d, + dout => perf_event_t0_l2); +perf_event_t1_latch: tri_rlmreg_p + generic map (width => perf_event_t1_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => event_bus_enable, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(perf_event_t1_offset to perf_event_t1_offset + perf_event_t1_l2'length-1), + scout => sov(perf_event_t1_offset to perf_event_t1_offset + perf_event_t1_l2'length-1), + din => perf_event_t1_d, + dout => perf_event_t1_l2); +perf_event_t2_latch: tri_rlmreg_p + generic map (width => perf_event_t2_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => event_bus_enable, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(perf_event_t2_offset to perf_event_t2_offset + perf_event_t2_l2'length-1), + scout => sov(perf_event_t2_offset to perf_event_t2_offset + perf_event_t2_l2'length-1), + din => perf_event_t2_d, + dout => perf_event_t2_l2); +perf_event_t3_latch: tri_rlmreg_p + generic map (width => perf_event_t3_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => event_bus_enable, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(perf_event_t3_offset to perf_event_t3_offset + perf_event_t3_l2'length-1), + scout => sov(perf_event_t3_offset to perf_event_t3_offset + perf_event_t3_l2'length-1), + din => perf_event_t3_d, + dout => perf_event_t3_l2); +perf_event_latch: tri_rlmreg_p + generic map (width => perf_event_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => event_bus_enable, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(perf_event_offset to perf_event_offset + perf_event_l2'length-1), + scout => sov(perf_event_offset to perf_event_offset + perf_event_l2'length-1), + din => perf_event_d, + dout => perf_event_l2); +spr_ic_cls_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(spr_ic_cls_offset), + scout => sov(spr_ic_cls_offset), + din => spr_ic_cls_d, + dout => spr_ic_cls_l2); +spr_ic_idir_way_latch: tri_rlmreg_p + generic map (width => spr_ic_idir_way_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_dataout_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(spr_ic_idir_way_offset to spr_ic_idir_way_offset + spr_ic_idir_way_l2'length-1), + scout => sov(spr_ic_idir_way_offset to spr_ic_idir_way_offset + spr_ic_idir_way_l2'length-1), + din => spr_ic_idir_way_d, + dout => spr_ic_idir_way_l2); +iu1_spr_idir_read_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu1_spr_idir_read_offset), + scout => sov(iu1_spr_idir_read_offset), + din => iu1_spr_idir_read_d, + dout => iu1_spr_idir_read_l2); +iu2_spr_idir_read_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu2_spr_idir_read_offset), + scout => sov(iu2_spr_idir_read_offset), + din => iu2_spr_idir_read_d, + dout => iu2_spr_idir_read_l2); +iu2_spr_idir_lru_latch: tri_rlmreg_p + generic map (width => iu2_spr_idir_lru_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_dataout_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu2_spr_idir_lru_offset to iu2_spr_idir_lru_offset + iu2_spr_idir_lru_l2'length-1), + scout => sov(iu2_spr_idir_lru_offset to iu2_spr_idir_lru_offset + iu2_spr_idir_lru_l2'length-1), + din => iu2_spr_idir_lru_d, + dout => iu2_spr_idir_lru_l2); +dbg_dir_write_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => trace_bus_enable, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dbg_dir_write_offset), + scout => sov(dbg_dir_write_offset), + din => dbg_dir_write_d, + dout => dbg_dir_write_l2); +dbg_dir_rd_act_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => trace_bus_enable, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dbg_dir_rd_act_offset), + scout => sov(dbg_dir_rd_act_offset), + din => dbg_dir_rd_act_d, + dout => dbg_dir_rd_act_l2); +dbg_iu2_lru_rd_update_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => trace_bus_enable, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dbg_iu2_lru_rd_update_offset), + scout => sov(dbg_iu2_lru_rd_update_offset), + din => dbg_iu2_lru_rd_update_d, + dout => dbg_iu2_lru_rd_update_l2); +dbg_iu2_rd_way_tag_hit_latch: tri_rlmreg_p + generic map (width => dbg_iu2_rd_way_tag_hit_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => trace_bus_enable, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dbg_iu2_rd_way_tag_hit_offset to dbg_iu2_rd_way_tag_hit_offset + dbg_iu2_rd_way_tag_hit_l2'length-1), + scout => sov(dbg_iu2_rd_way_tag_hit_offset to dbg_iu2_rd_way_tag_hit_offset + dbg_iu2_rd_way_tag_hit_l2'length-1), + din => dbg_iu2_rd_way_tag_hit_d, + dout => dbg_iu2_rd_way_tag_hit_l2); +dbg_iu2_rd_way_hit_latch: tri_rlmreg_p + generic map (width => dbg_iu2_rd_way_hit_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => trace_bus_enable, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dbg_iu2_rd_way_hit_offset to dbg_iu2_rd_way_hit_offset + dbg_iu2_rd_way_hit_l2'length-1), + scout => sov(dbg_iu2_rd_way_hit_offset to dbg_iu2_rd_way_hit_offset + dbg_iu2_rd_way_hit_l2'length-1), + din => dbg_iu2_rd_way_hit_d, + dout => dbg_iu2_rd_way_hit_l2); +dbg_load_iu2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => trace_bus_enable, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(dbg_load_iu2_offset), + scout => sov(dbg_load_iu2_offset), + din => dbg_load_iu2_d, + dout => dbg_load_iu2_l2); +spare_slp_latch: tri_rlmreg_p + generic map (width => spare_slp_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(spare_slp_offset to spare_slp_offset + spare_slp_l2'length-1), + scout => sov(spare_slp_offset to spare_slp_offset + spare_slp_l2'length-1), + din => spare_slp_l2, + dout => spare_slp_l2); +spare_a_latch: tri_rlmreg_p + generic map (width => 8, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(spare_a_offset to spare_a_offset + 7), + scout => sov(spare_a_offset to spare_a_offset + 7), + din => spare_l2(0 to 7), + dout => spare_l2(0 to 7)); +spare_b_latch: tri_rlmreg_p + generic map (width => 8, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(spare_b_offset to spare_b_offset + 7), + scout => sov(spare_b_offset to spare_b_offset + 7), + din => spare_l2(8 to 15), + dout => spare_l2(8 to 15)); +----------------------------------------------------------------------- +-- abist latches +----------------------------------------------------------------------- +ab_reg: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 39, needs_sreset => 0) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => pc_iu_abist_ena_dc, + thold_b => pc_iu_abst_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => abst_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => abst_siv(4 to 42), + scout => abst_sov(4 to 42), + din ( 0 ) => pc_iu_abist_g8t_wenb, + din ( 1 ) => pc_iu_abist_g8t1p_renb_0, + din ( 2 to 5) => pc_iu_abist_di_0, + din ( 6 ) => pc_iu_abist_g8t_bw_1, + din ( 7 ) => pc_iu_abist_g8t_bw_0, + din ( 8 to 13) => pc_iu_abist_waddr_0, + din (14 ) => pc_iu_abist_wl64_comp_ena, + din (15 to 18) => pc_iu_abist_g8t_dcomp, + din (19 to 26) => pc_iu_abist_raddr_0, + din (27 to 28) => pc_iu_abist_g6t_bw, + din (29 to 32) => pc_iu_abist_di_g6t_2r, + din (33 ) => pc_iu_abist_wl256_comp_ena, + din (34 to 37) => pc_iu_abist_dcomp_g6t_2r, + din (38 ) => pc_iu_abist_g6t_r_wb, + dout( 0 ) => stage_abist_g8t_wenb, + dout( 1 ) => stage_abist_g8t1p_renb_0, + dout( 2 to 5 ) => stage_abist_di_0, + dout( 6 ) => stage_abist_g8t_bw_1, + dout( 7 ) => stage_abist_g8t_bw_0, + dout( 8 to 13) => stage_abist_waddr_0, + dout(14 ) => stage_abist_wl64_comp_ena, + dout(15 to 18) => stage_abist_g8t_dcomp, + dout(19 to 26) => stage_abist_raddr_0, + dout(27 to 28) => stage_abist_g6t_bw, + dout(29 to 32) => stage_abist_di_g6t_2r, + dout(33 ) => stage_abist_wl256_comp_ena, + dout(34 to 37) => stage_abist_dcomp_g6t_2r, + dout(38 ) => stage_abist_g6t_r_wb); +----------------------------------------------------------------------- +-- Scan +----------------------------------------------------------------------- +repr_slat_sl_thold_0_b <= not pc_iu_repr_sl_thold_0; +time_slat_sl_thold_0_b <= not pc_iu_time_sl_thold_0; +repr_scan_latch: entity tri.tri_regs + generic map (width => 2, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + forcee => pc_iu_sg_0, + thold_b => repr_slat_sl_thold_0_b, + delay_lclkr => delay_lclkr, + scin(0) => repr_scan_in, + scin(1) => repr_siv(2), + scout(0) => repr_siv(0), + scout(1) => repr_sov(2), + dout => open ); +time_scan_latch: entity tri.tri_regs + generic map (width => 1, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + forcee => pc_iu_sg_0, + thold_b => time_slat_sl_thold_0_b, + delay_lclkr => delay_lclkr, + scin(0) => time_siv(2), + scout(0) => time_sov(2), + dout => open ); +siv(0 TO scan0_right) <= sov(1 to scan0_right) & func_scan_in(0); +func_scan_out(0) <= sov(0) and an_ac_scan_dis_dc_b; +siv(scan1_left TO scan_right) <= sov(scan1_left+1 to scan_right) & func_scan_in(1); +func_scan_out(1) <= sov(scan1_left) and an_ac_scan_dis_dc_b; +-- Chain 0: WAY01 IDIR & IDATA +abst_siv(0 TO 1) <= abst_sov(1) & abst_scan_in(0); +abst_scan_out(0) <= abst_sov(0) and an_ac_scan_dis_dc_b; +-- Chain 1: WAY23 IDIR & IDATA +abst_siv(2 TO 3) <= abst_sov(3) & abst_scan_in(1); +abst_scan_out(1) <= abst_sov(2) and an_ac_scan_dis_dc_b; +-- Chain 2: AB_REG - tack on to BHT's scan chain +abst_siv(4 TO abst_siv'right) <= abst_sov(5 to abst_sov'right) & abst_scan_in(2); +abst_scan_out(2) <= abst_sov(4) and an_ac_scan_dis_dc_b; +time_siv <= time_scan_in & time_sov(0 to 1); +time_scan_out <= time_sov(2) and an_ac_scan_dis_dc_b; +repr_siv(1 TO 2) <= repr_sov(0 to 1); +repr_scan_out <= repr_sov(2) and an_ac_scan_dis_dc_b; +END IUQ_IC_DIR; diff --git a/rel/src/vhdl/work/iuq_ic_dir_cmp.vhdl b/rel/src/vhdl/work/iuq_ic_dir_cmp.vhdl new file mode 100644 index 0000000..331d8a1 --- /dev/null +++ b/rel/src/vhdl/work/iuq_ic_dir_cmp.vhdl @@ -0,0 +1,276 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + +entity iuq_ic_dir_cmp is +generic( expand_type: integer := 2 ); -- 0 - ibm tech, 1 - other ); +port( + vdd :inout power_logic; + gnd :inout power_logic; + nclk :in clk_logic; + delay_lclkr :in std_ulogic;-- LCB input + mpw1_b :in std_ulogic;-- LCB input + mpw2_b :in std_ulogic;-- LCB input + forcee :in std_ulogic;-- LCB input + sg_0 :in std_ulogic;-- LCB input + thold_0_b :in std_ulogic;-- LCB input + scan_in :in std_ulogic;--perv + scan_out :out std_ulogic;--perv + + dir_dataout_act :in std_ulogic; --act + + iu2_endian :in std_ulogic ;--LE + ierat_iu_iu2_rpn :in std_ulogic_vector(22 to 51) ;--erat + iu2_dir_dataout_0_d :in std_ulogic_vector(22 to 52) ;--directory + iu2_dir_dataout_1_d :in std_ulogic_vector(22 to 52) ;--directory + iu2_dir_dataout_2_d :in std_ulogic_vector(22 to 52) ;--directory + iu2_dir_dataout_3_d :in std_ulogic_vector(22 to 52) ;--directory + + ierat_iu_iu2_rpn_noncmp :out std_ulogic_vector(22 to 51) ;-- for noncritical uses of rpn + iu2_dir_dataout_0_noncmp :out std_ulogic_vector(22 to 52) ;-- for spr mux + iu2_dir_dataout_1_noncmp :out std_ulogic_vector(22 to 52) ;-- for spr mux + iu2_dir_dataout_2_noncmp :out std_ulogic_vector(22 to 52) ;-- for spr mux + iu2_dir_dataout_3_noncmp :out std_ulogic_vector(22 to 52) ;-- for spr mux + + iu2_dir_rd_val :in std_ulogic_vector(0 to 3) ; + iu2_rd_way_tag_hit :out std_ulogic_vector(0 to 3) ;-- excludes LE + + iu2_rd_way_hit :out std_ulogic_vector(0 to 3) ;-- includes LE --2009jun22 + iu2_rd_way_hit_insmux_b :out std_ulogic_vector(0 to 3) -- includes LE --2009jun22 +); + +-- synopsys translate_off + + +-- synopsys translate_on + +end iuq_ic_dir_cmp; -- ENTITY + +architecture iuq_ic_dir_cmp of iuq_ic_dir_cmp is + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal dir_lclk :clk_logic; + signal dir_d1clk :std_ulogic; + signal dir_d2clk :std_ulogic; + + signal iu2_dir_dataout_0_l2_b , dir0_q , dir0_si, dir0_so , dir0_slow_b :std_ulogic_vector(0 to 30) ; + signal iu2_dir_dataout_1_l2_b , dir1_q , dir1_si, dir1_so , dir1_slow_b :std_ulogic_vector(0 to 30) ; + signal iu2_dir_dataout_2_l2_b , dir2_q , dir2_si, dir2_so , dir2_slow_b :std_ulogic_vector(0 to 30) ; + signal iu2_dir_dataout_3_l2_b , dir3_q , dir3_si, dir3_so , dir3_slow_b :std_ulogic_vector(0 to 30) ; + signal dir_eq_b :std_ulogic_vector(0 to 3); + + signal dir_val_le_b, le_cmp :std_ulogic_vector(0 to 3) ; +-- synopsys translate_off + +-- synopsys translate_on + + + signal erat_i1_b :std_ulogic_vector(0 to 29) ; +-- synopsys translate_off +-- synopsys translate_on + + + +-- synopsys translate_off +-- synopsys translate_on + + + signal iu2_rd_way_hit_0 :std_ulogic_vector(0 to 3) ; + signal iu2_rd_way_hit_1x_b :std_ulogic_vector(0 to 3) ; + signal iu2_rd_way_hit_1y_b :std_ulogic_vector(0 to 3) ; + signal iu2_rd_way_hit_2x :std_ulogic_vector(0 to 3) ; +-- synopsys translate_off +-- synopsys translate_on + +begin + +-- ################################################################ +-- # inverters from latches +-- ################################################################ + + u_dir0_q: dir0_q(0 to 30) <= not( iu2_dir_dataout_0_l2_b(0 to 30) ); + u_dir1_q: dir1_q(0 to 30) <= not( iu2_dir_dataout_1_l2_b(0 to 30) ); + u_dir2_q: dir2_q(0 to 30) <= not( iu2_dir_dataout_2_l2_b(0 to 30) ); + u_dir3_q: dir3_q(0 to 30) <= not( iu2_dir_dataout_3_l2_b(0 to 30) ); + + u_dir0_slowi: dir0_slow_b(0 to 30) <= not( dir0_q(0 to 30) );-- tiny + u_dir1_slowi: dir1_slow_b(0 to 30) <= not( dir1_q(0 to 30) );-- tiny + u_dir2_slowi: dir2_slow_b(0 to 30) <= not( dir2_q(0 to 30) );-- tiny + u_dir3_slowi: dir3_slow_b(0 to 30) <= not( dir3_q(0 to 30) );-- tiny + + iu2_dir_dataout_0_noncmp(22 to 52) <= not dir0_slow_b(0 to 30) ;--output-- buffered off + iu2_dir_dataout_1_noncmp(22 to 52) <= not dir1_slow_b(0 to 30) ;--output-- buffered off + iu2_dir_dataout_2_noncmp(22 to 52) <= not dir2_slow_b(0 to 30) ;--output-- buffered off + iu2_dir_dataout_3_noncmp(22 to 52) <= not dir3_slow_b(0 to 30) ;--output-- buffered off + + u_erat_i1: erat_i1_b(0 to 29) <= not( ierat_iu_iu2_rpn(22 to 51) ); + + + ierat_iu_iu2_rpn_noncmp(22 to 51) <= ierat_iu_iu2_rpn(22 to 51); + +-- ################################################################ +-- # directory compares against erat +-- ################################################################ + + cmp0: entity work.iuq_ic_dir_cmp30(iuq_ic_dir_cmp30) port map( + d0_b(0 to 29) => erat_i1_b (0 to 29) ,--i--iuq_ic_dir_cmp30(dir0cmp) + d1 (0 to 29) => dir0_q (0 to 29) ,--i--iuq_ic_dir_cmp30(dir0cmp) + eq_b => dir_eq_b(0) );--o--iuq_ic_dir_cmp30(dir0cmp) + + cmp1: entity work.iuq_ic_dir_cmp30(iuq_ic_dir_cmp30) port map( + d0_b(0 to 29) => erat_i1_b (0 to 29) ,--i--iuq_ic_dir_cmp30(dir1cmp) + d1 (0 to 29) => dir1_q (0 to 29) ,--i--iuq_ic_dir_cmp30(dir1cmp) + eq_b => dir_eq_b(1) );--o--iuq_ic_dir_cmp30(dir1cmp) + + cmp2: entity work.iuq_ic_dir_cmp30(iuq_ic_dir_cmp30) port map( + d0_b(0 to 29) => erat_i1_b (0 to 29) ,--i--iuq_ic_dir_cmp30(dir2cmp) + d1 (0 to 29) => dir2_q (0 to 29) ,--i--iuq_ic_dir_cmp30(dir2cmp) + eq_b => dir_eq_b(2) );--o--iuq_ic_dir_cmp30(dir2cmp) + + cmp3: entity work.iuq_ic_dir_cmp30(iuq_ic_dir_cmp30) port map( + d0_b(0 to 29) => erat_i1_b (0 to 29) ,--i--iuq_ic_dir_cmp30(dir3cmp) + d1 (0 to 29) => dir3_q (0 to 29) ,--i--iuq_ic_dir_cmp30(dir3cmp) + eq_b => dir_eq_b(3) );--o--iuq_ic_dir_cmp30(dir3cmp) + + + + u_match30: iu2_rd_way_tag_hit(0 to 3) <= not( dir_eq_b(0 to 3) ); + u_match31: iu2_rd_way_hit_0(0 to 3) <= not( dir_eq_b(0 to 3) or dir_val_le_b(0 to 3) ); + + u_match31_1x: iu2_rd_way_hit_1x_b (0 to 3) <= not( iu2_rd_way_hit_0(0 to 3) ) ; --x11 --2009jun22 + u_match31_1y: iu2_rd_way_hit_1y_b (0 to 3) <= not( iu2_rd_way_hit_0(0 to 3) ) ; --x11 --2009jun22 + + u_match31_2x: iu2_rd_way_hit_2x (0 to 3) <= not( iu2_rd_way_hit_1x_b(0 to 3) ) ; --x13 --2009jun22 + iu2_rd_way_hit (0 to 3) <= not( iu2_rd_way_hit_1y_b(0 to 3) );--unsized --output-- --2009jun22 + + u_match31_3x: iu2_rd_way_hit_insmux_b(0 to 3) <= not( iu2_rd_way_hit_2x (0 to 3) ) ; --x13 --output-- --2009jun22 + + + + + dir_val_le_b(0 to 3) <= not( iu2_dir_rd_val(0 to 3) and le_cmp(0 to 3) ); -- not sized, not placed + + le_cmp(0) <= ( dir0_q(30) xnor iu2_endian );-- not sized, not placed + le_cmp(1) <= ( dir1_q(30) xnor iu2_endian );-- not sized, not placed + le_cmp(2) <= ( dir2_q(30) xnor iu2_endian );-- not sized, not placed + le_cmp(3) <= ( dir3_q(30) xnor iu2_endian );-- not sized, not placed + + +-- ################################################################ +-- # Latches +-- ################################################################ + + iu2_dir_dataout_0_lat: entity tri.tri_inv_nlats generic map (width => 31, btr=> "NLI0001_X2_A12TH", needs_sreset => 0, expand_type => expand_type) port map ( + VD => vdd , + GD => gnd , + LCLK => dir_lclk , + D1CLK => dir_d1clk , + D2CLK => dir_d2clk , + SCANIN => dir0_si , + SCANOUT => dir0_so , + D => iu2_dir_dataout_0_d(22 to 52) , + QB => iu2_dir_dataout_0_l2_b(0 to 30) ); + + iu2_dir_dataout_1_lat: entity tri.tri_inv_nlats generic map (width => 31, btr=> "NLI0001_X2_A12TH", needs_sreset => 0, expand_type => expand_type) port map ( + VD => vdd , + GD => gnd , + LCLK => dir_lclk , + D1CLK => dir_d1clk , + D2CLK => dir_d2clk , + SCANIN => dir1_si , + SCANOUT => dir1_so , + D => iu2_dir_dataout_1_d(22 to 52) , + QB => iu2_dir_dataout_1_l2_b(0 to 30) ); + + iu2_dir_dataout_2_lat: entity tri.tri_inv_nlats generic map (width => 31, btr=> "NLI0001_X2_A12TH", needs_sreset => 0, expand_type => expand_type) port map ( + VD => vdd , + GD => gnd , + LCLK => dir_lclk , + D1CLK => dir_d1clk , + D2CLK => dir_d2clk , + SCANIN => dir2_si , + SCANOUT => dir2_so , + D => iu2_dir_dataout_2_d(22 to 52) , + QB => iu2_dir_dataout_2_l2_b(0 to 30) ); + + iu2_dir_dataout_3_lat: entity tri.tri_inv_nlats generic map (width => 31, btr=> "NLI0001_X2_A12TH", needs_sreset => 0, expand_type => expand_type) port map ( + VD => vdd , + GD => gnd , + LCLK => dir_lclk , + D1CLK => dir_d1clk , + D2CLK => dir_d2clk , + SCANIN => dir3_si , + SCANOUT => dir3_so , + D => iu2_dir_dataout_3_d(22 to 52) , + QB => iu2_dir_dataout_3_l2_b(0 to 30) ); + + + dir0_si(0 to 30) <= scan_in & dir0_so(0 to 29); + dir1_si(0 to 30) <= dir1_so(1 to 30) & dir0_so(30); + dir2_si(0 to 30) <= dir1_so(0) & dir2_so(0 to 29) ; + dir3_si(0 to 30) <= dir3_so(1 to 30) & dir2_so(30) ; + scan_out <= dir3_so(0) ; + +-- ############################################################### +-- # LCBs +-- ############################################################### + + dir_lcb : tri_lcbnd generic map (expand_type => expand_type) port map( + nclk => nclk ,--in + vd => vdd ,--inout + gd => gnd ,--inout + act => dir_dataout_act ,--in + delay_lclkr => delay_lclkr ,--in + mpw1_b => mpw1_b ,--in + mpw2_b => mpw2_b ,--in + forcee => forcee,--in + sg => sg_0 ,--in + thold_b => thold_0_b ,--in + d1clk => dir_d1clk ,--out + d2clk => dir_d2clk ,--out + lclk => dir_lclk );--out + + +--=############################################################### + + + +end; -- iuq_ic_dir_cmp ARCHITECTURE diff --git a/rel/src/vhdl/work/iuq_ic_dir_cmp30.vhdl b/rel/src/vhdl/work/iuq_ic_dir_cmp30.vhdl new file mode 100644 index 0000000..9b4bc44 --- /dev/null +++ b/rel/src/vhdl/work/iuq_ic_dir_cmp30.vhdl @@ -0,0 +1,127 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +-- ################################################################### +-- ## Address decoder +-- ################################################################### + + +LIBRARY ieee; USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY ibm; + USE ibm.std_ulogic_support.all; + USE ibm.std_ulogic_unsigned.all; + USE ibm.std_ulogic_function_support.all; +LIBRARY support; + USE support.power_logic_pkg.all; +LIBRARY tri; USE tri.tri_latches_pkg.all; + + +entity iuq_ic_dir_cmp30 is +generic( expand_type: integer := 2 ); -- 0 - ibm tech, 1 - other ); +port( + d0_b :in std_ulogic_vector(0 to 29); + d1 :in std_ulogic_vector(0 to 29); + eq_b :out std_ulogic +); + +-- synopsys translate_off + +-- synopsys translate_on + + + +end iuq_ic_dir_cmp30; -- ENTITY + +architecture iuq_ic_dir_cmp30 of iuq_ic_dir_cmp30 is + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal eq01 :std_ulogic_vector(0 to 29) ; +-- synopsys translate_off +-- synopsys translate_on + + signal eq02_b : std_ulogic_vector(0 to 14); + signal eq04 : std_ulogic_vector(0 to 7); + signal eq08_b : std_ulogic_vector(0 to 3); + signal eq16 : std_ulogic_vector(0 to 1); + +-- synopsys translate_off + + + + + + +-- synopsys translate_on + + +begin + + + u_eq01: eq01(0 to 29) <= ( d0_b(0 to 29) xor d1(0 to 29) ); --x1 + + + u_00_eq02: eq02_b( 0) <= not( eq01 ( 0) and eq01 ( 1) ); --lv1 x1 + u_02_eq02: eq02_b( 1) <= not( eq01 ( 2) and eq01 ( 3) ); --lv1 x1 + u_04_eq02: eq02_b( 2) <= not( eq01 ( 4) and eq01 ( 5) ); --lv1 x1 + u_06_eq02: eq02_b( 3) <= not( eq01 ( 6) and eq01 ( 7) ); --lv1 x1 + u_08_eq02: eq02_b( 4) <= not( eq01 ( 8) and eq01 ( 9) ); --lv1 x1 + u_10_eq02: eq02_b( 5) <= not( eq01 (10) and eq01 (11) ); --lv1 x1 + u_12_eq02: eq02_b( 6) <= not( eq01 (12) and eq01 (13) ); --lv1 x1 + u_14_eq02: eq02_b( 7) <= not( eq01 (14) and eq01 (15) ); --lv1 x1 + u_16_eq02: eq02_b( 8) <= not( eq01 (16) and eq01 (17) ); --lv1 x1 + u_18_eq02: eq02_b( 9) <= not( eq01 (18) and eq01 (19) ); --lv1 x1 + u_20_eq02: eq02_b(10) <= not( eq01 (20) and eq01 (21) ); --lv1 x1 + u_22_eq02: eq02_b(11) <= not( eq01 (22) and eq01 (23) ); --lv1 x1 + u_24_eq02: eq02_b(12) <= not( eq01 (24) and eq01 (25) ); --lv1 x1 + u_26_eq02: eq02_b(13) <= not( eq01 (26) and eq01 (27) ); --lv1 x1 + u_28_eq02: eq02_b(14) <= not( eq01 (28) and eq01 (29) ); --lv1 x1 + + u_01_eq04: eq04 ( 0) <= not( eq02_b( 0) or eq02_b( 1) ); --lv2 x2 + u_05_eq04: eq04 ( 1) <= not( eq02_b( 2) or eq02_b( 3) ); --lv2 x2 + u_09_eq04: eq04 ( 2) <= not( eq02_b( 4) or eq02_b( 5) ); --lv2 x2 + u_13_eq04: eq04 ( 3) <= not( eq02_b( 6) or eq02_b( 7) ); --lv2 x2 + u_17_eq04: eq04 ( 4) <= not( eq02_b( 8) or eq02_b( 9) ); --lv2 x2 + u_21_eq04: eq04 ( 5) <= not( eq02_b(10) or eq02_b(11) ); --lv2 x2 + u_25_eq04: eq04 ( 6) <= not( eq02_b(12) or eq02_b(13) ); --lv2 x2 + u_29_eq04: eq04 ( 7) <= not( eq02_b(14) ); --lv2 x2 + + u_03_eq08: eq08_b( 0) <= not( eq04 ( 0) and eq04 ( 1) ); --lv3 x4 r + u_11_eq08: eq08_b( 1) <= not( eq04 ( 2) and eq04 ( 3) ); --lv3 x4 r + u_19_eq08: eq08_b( 2) <= not( eq04 ( 4) and eq04 ( 5) ); --lv3 x4 r + u_27_eq08: eq08_b( 3) <= not( eq04 ( 6) and eq04 ( 7) ); --lv3 x4 r + + u_07_eq16: eq16 ( 0) <= not( eq08_b( 0) or eq08_b( 1) ); --lv4 x6 r + u_23_eq16: eq16 ( 1) <= not( eq08_b( 2) or eq08_b( 3) ); --lv4 x6 r + + u_15_eq32: eq_b <= not( eq16 ( 0) and eq16 ( 1) ); --lv5 x8 r --output + +end; -- iuq_ic_dir_cmp30 ARCHITECTURE diff --git a/rel/src/vhdl/work/iuq_ic_ierat.vhdl b/rel/src/vhdl/work/iuq_ic_ierat.vhdl new file mode 100644 index 0000000..931b2a9 --- /dev/null +++ b/rel/src/vhdl/work/iuq_ic_ierat.vhdl @@ -0,0 +1,6951 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +--******************************************************************** +--* TITLE: Instruction Effective to Real Address Translation +--* NAME: iuq_ic_ierat.vhdl +--********************************************************************* +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library ibm; +use ibm.std_ulogic_unsigned.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_support.all; +library support; +use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity iuq_ic_ierat is + generic(thdid_width : integer := 4; + ttype_width : integer := 6; + state_width : integer := 4; + pid_width : integer := 14; + pid_width_erat : integer := 8; + extclass_width : integer := 2; + tlbsel_width : integer := 2; + epn_width : integer := 52; + vpn_width : integer := 61; + rpn_width : integer := 30; + ws_width : integer := 2; + rs_is_width : integer := 9; + ra_entry_width : integer := 4; + rs_data_width : integer := 64; + data_out_width : integer := 64; + error_width : integer := 3; + cam_data_width : natural := 84; + array_data_width : natural := 68; + num_entry : natural := 16; + num_entry_log2 : natural := 4; + por_seq_width : integer := 3; + watermark_width : integer := 4; + eptr_width : integer := 4; + lru_width : integer := 15; + bcfg_width : integer := 123; + bcfg_epn_0to15 : integer := 0; + bcfg_epn_16to31 : integer := 0; + bcfg_epn_32to47 : integer := (2**16)-1; + bcfg_epn_48to51 : integer := (2**4)-1; + bcfg_rpn_22to31 : integer := (2**10)-1; + bcfg_rpn_32to47 : integer := (2**16)-1; + bcfg_rpn_48to51 : integer := (2**4)-1; + bcfg_rpn2_32to47 : integer := 0; + bcfg_rpn2_48to51 : integer := 0; + bcfg_attr : integer := 0; + check_parity : integer := 1; + expand_type : integer := 2 ); +port( + gnd : inout power_logic; + vdd : inout power_logic; + vcs : inout power_logic; + nclk : in clk_logic; + pc_iu_init_reset : in std_ulogic; + +tc_ccflush_dc : in std_ulogic; +tc_scan_dis_dc_b : in std_ulogic; +tc_scan_diag_dc : in std_ulogic; +tc_lbist_en_dc : in std_ulogic; +an_ac_atpg_en_dc : in std_ulogic; +an_ac_grffence_en_dc : in std_ulogic; +lcb_d_mode_dc : in std_ulogic; +lcb_clkoff_dc_b : in std_ulogic; +lcb_act_dis_dc : in std_ulogic; +lcb_mpw1_dc_b : in std_ulogic_vector(0 to 1); +lcb_mpw2_dc_b : in std_ulogic; +lcb_delay_lclkr_dc : in std_ulogic_vector(0 to 1); +pc_iu_func_sl_thold_2 : in std_ulogic; +pc_iu_func_slp_sl_thold_2 : in std_ulogic; +pc_iu_func_slp_nsl_thold_2 : in std_ulogic; +pc_iu_cfg_slp_sl_thold_2 : in std_ulogic; +pc_iu_regf_slp_sl_thold_2 : in std_ulogic; +pc_iu_time_sl_thold_2 : in std_ulogic; +pc_iu_sg_2 : in std_ulogic; +pc_iu_fce_2 : in std_ulogic; +cam_clkoff_b : in std_ulogic; +cam_act_dis : in std_ulogic; +cam_d_mode : in std_ulogic; +cam_delay_lclkr : in std_ulogic_vector(0 to 4); +cam_mpw1_b : in std_ulogic_vector(0 to 4); +cam_mpw2_b : in std_ulogic; +ac_func_scan_in : in std_ulogic_vector(0 to 1); +ac_func_scan_out : out std_ulogic_vector(0 to 1); +ac_ccfg_scan_in : in std_ulogic; +ac_ccfg_scan_out : out std_ulogic; +func_scan_in_cam : in std_ulogic; +func_scan_out_cam : out std_ulogic; +time_scan_in : in std_ulogic; +time_scan_out : out std_ulogic; +regf_scan_in : in std_ulogic_vector(0 to 4); +regf_scan_out : out std_ulogic_vector(0 to 4); +iu_ierat_iu0_val : in std_ulogic; +iu_ierat_iu0_thdid : in std_ulogic_vector(0 to thdid_width-1); +iu_ierat_iu0_ifar : in std_ulogic_vector(0 to 51); +iu_ierat_iu0_flush : in std_ulogic_vector(0 to thdid_width-1); +iu_ierat_iu1_flush : in std_ulogic_vector(0 to thdid_width-1); +iu_ierat_iu1_back_inv : in std_ulogic; +iu_ierat_ium1_back_inv : in std_ulogic; +spr_ic_clockgate_dis : in std_ulogic; +ierat_iu_iu2_rpn : out std_ulogic_vector(22 to 51); +ierat_iu_iu2_wimge : out std_ulogic_vector(0 to 4); +ierat_iu_iu2_u : out std_ulogic_vector(0 to 3); +ierat_iu_iu2_error : out std_ulogic_vector(0 to 2); +ierat_iu_iu2_miss : out std_ulogic; +ierat_iu_iu2_multihit : out std_ulogic; +ierat_iu_iu2_isi : out std_ulogic; +xu_iu_rf1_val : in std_ulogic_vector(0 to thdid_width-1); +xu_iu_rf1_is_eratre : in std_ulogic; +xu_iu_rf1_is_eratwe : in std_ulogic; +xu_iu_rf1_is_eratsx : in std_ulogic; +xu_iu_rf1_is_eratilx : in std_ulogic; +xu_iu_ex1_is_isync : in std_ulogic; +xu_iu_ex1_is_csync : in std_ulogic; +xu_iu_rf1_ws : in std_ulogic_vector(0 to ws_width-1); +xu_iu_rf1_t : in std_ulogic_vector(0 to 2); +xu_iu_ex1_rs_is : in std_ulogic_vector(0 to rs_is_width-1); +xu_iu_ex1_ra_entry : in std_ulogic_vector(0 to ra_entry_width-1); +xu_iu_ex1_rb : in std_ulogic_vector(64-rs_data_width to 51); +xu_iu_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_rf1_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_ex1_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_ex2_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_ex3_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_ex4_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_ex5_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_iu_ex4_rs_data : in std_ulogic_vector(64-rs_data_width to 63); +xu_iu_msr_hv : in std_ulogic_vector(0 to thdid_width-1); +xu_iu_msr_pr : in std_ulogic_vector(0 to thdid_width-1); +xu_iu_msr_is : in std_ulogic_vector(0 to thdid_width-1); +xu_iu_msr_cm : in std_ulogic_vector(0 to thdid_width-1); +xu_iu_hid_mmu_mode : in std_ulogic; +xu_iu_spr_ccr2_ifrat : in std_ulogic; +xu_iu_spr_ccr2_ifratsc : in std_ulogic_vector(0 to 8); +xu_iu_xucr4_mmu_mchk : in std_ulogic; +ierat_iu_hold_req : out std_ulogic_vector(0 to thdid_width-1); +ierat_iu_iu2_flush_req : out std_ulogic_vector(0 to thdid_width-1); +iu_xu_ex4_data : out std_ulogic_vector(64-data_out_width to 63); +iu_xu_ierat_ex3_par_err : out std_ulogic_vector(0 to thdid_width-1); +iu_xu_ierat_ex4_par_err : out std_ulogic_vector(0 to thdid_width-1); +iu_xu_ierat_ex2_flush_req : out std_ulogic_vector(0 to thdid_width-1); +iu_mm_ierat_req : out std_ulogic; +iu_mm_ierat_thdid : out std_ulogic_vector(0 to thdid_width-1); +iu_mm_ierat_state : out std_ulogic_vector(0 to state_width-1); +iu_mm_ierat_tid : out std_ulogic_vector(0 to pid_width-1); +iu_mm_ierat_flush : out std_ulogic_vector(0 to thdid_width-1); +mm_iu_ierat_rel_val : in std_ulogic_vector(0 to 4); +mm_iu_ierat_rel_data : in std_ulogic_vector(0 to 131); +mm_iu_ierat_pid0 : in std_ulogic_vector(0 to pid_width-1); +mm_iu_ierat_pid1 : in std_ulogic_vector(0 to pid_width-1); +mm_iu_ierat_pid2 : in std_ulogic_vector(0 to pid_width-1); +mm_iu_ierat_pid3 : in std_ulogic_vector(0 to pid_width-1); +mm_iu_ierat_mmucr0_0 : in std_ulogic_vector(0 to 19); +mm_iu_ierat_mmucr0_1 : in std_ulogic_vector(0 to 19); +mm_iu_ierat_mmucr0_2 : in std_ulogic_vector(0 to 19); +mm_iu_ierat_mmucr0_3 : in std_ulogic_vector(0 to 19); +iu_mm_ierat_mmucr0 : out std_ulogic_vector(0 to 17); +iu_mm_ierat_mmucr0_we : out std_ulogic_vector(0 to 3); +mm_iu_ierat_mmucr1 : in std_ulogic_vector(0 to 8); +iu_mm_ierat_mmucr1 : out std_ulogic_vector(0 to 3); +iu_mm_ierat_mmucr1_we : out std_ulogic; +mm_iu_ierat_snoop_coming : in std_ulogic; +mm_iu_ierat_snoop_val : in std_ulogic; +mm_iu_ierat_snoop_attr : in std_ulogic_vector(0 to 25); +mm_iu_ierat_snoop_vpn : in std_ulogic_vector(52-epn_width to 51); +iu_mm_ierat_snoop_ack : out std_ulogic; +pc_iu_trace_bus_enable : in std_ulogic; +ierat_iu_debug_group0 : out std_ulogic_vector(0 to 87); +ierat_iu_debug_group1 : out std_ulogic_vector(0 to 87); +ierat_iu_debug_group2 : out std_ulogic_vector(0 to 87); +ierat_iu_debug_group3 : out std_ulogic_vector(0 to 87) + +); +end iuq_ic_ierat; +ARCHITECTURE IUQ_IC_IERAT + OF IUQ_IC_IERAT + IS +--@@ Signal Declarations +SIGNAL CAM_MASK_BITS_PT : STD_ULOGIC_VECTOR(1 TO 19) := +(OTHERS=> 'U'); +SIGNAL IU1_FIRST_HIT_ENTRY_PT : STD_ULOGIC_VECTOR(1 TO 15) := +(OTHERS=> 'U'); +SIGNAL IU1_MULTIHIT_B_PT : STD_ULOGIC_VECTOR(1 TO 16) := +(OTHERS=> 'U'); +SIGNAL LRU_RMT_VEC_PT : STD_ULOGIC_VECTOR(1 TO 17) := +(OTHERS=> 'U'); +SIGNAL LRU_SET_RESET_VEC_PT : STD_ULOGIC_VECTOR(1 TO 80) := +(OTHERS=> 'U'); +SIGNAL LRU_WATERMARK_MASK_PT : STD_ULOGIC_VECTOR(1 TO 15) := +(OTHERS=> 'U'); +SIGNAL LRU_WAY_ENCODE_PT : STD_ULOGIC_VECTOR(1 TO 15) := +(OTHERS=> 'U'); +---------------------------- +-- components +---------------------------- +-- Instruction ERAT CAM/Array, 16-entry +component tri_cam_16x143_1r1w1c + generic (expand_type : integer := 2); + port ( + gnd : inout power_logic; + vdd : inout power_logic; + vcs : inout power_logic; + nclk : in clk_logic; + tc_ccflush_dc : in std_ulogic; + tc_scan_dis_dc_b : in std_ulogic; + tc_scan_diag_dc : in std_ulogic; + tc_lbist_en_dc : in std_ulogic; + an_ac_atpg_en_dc : in std_ulogic; + + lcb_d_mode_dc : in std_ulogic; + lcb_clkoff_dc_b : in std_ulogic; + lcb_act_dis_dc : in std_ulogic; + lcb_mpw1_dc_b : in std_ulogic_vector(0 to 3); + lcb_mpw2_dc_b : in std_ulogic; + lcb_delay_lclkr_dc : in std_ulogic_vector(0 to 3); + + pc_sg_2 : in std_ulogic; + pc_func_slp_sl_thold_2 : in std_ulogic; + pc_func_slp_nsl_thold_2 : in std_ulogic; + pc_regf_slp_sl_thold_2 : in std_ulogic; + pc_time_sl_thold_2 : in std_ulogic; + pc_fce_2 : in std_ulogic; + + func_scan_in : in std_ulogic; + func_scan_out : out std_ulogic; + regfile_scan_in : in std_ulogic_vector(0 to 4); + regfile_scan_out : out std_ulogic_vector(0 to 4); + time_scan_in : in std_ulogic; + time_scan_out : out std_ulogic; + + + rd_val : in std_ulogic; + rd_val_late : in std_ulogic; + rw_entry : in std_ulogic_vector(0 to 3); + + wr_array_data : in std_ulogic_vector(0 to array_data_width-1); + wr_cam_data : in std_ulogic_vector(0 to cam_data_width-1); + wr_array_val : in std_ulogic_vector(0 to 1); + wr_cam_val : in std_ulogic_vector(0 to 1); + wr_val_early : in std_ulogic; + + comp_request : in std_ulogic; + comp_addr : in std_ulogic_vector(0 to 51); + addr_enable : in std_ulogic_vector(0 to 1); + comp_pgsize : in std_ulogic_vector(0 to 2); + pgsize_enable : in std_ulogic; + comp_class : in std_ulogic_vector(0 to 1); + class_enable : in std_ulogic_vector(0 to 2); + comp_extclass : in std_ulogic_vector(0 to 1); + extclass_enable : in std_ulogic_vector(0 to 1); + comp_state : in std_ulogic_vector(0 to 1); + state_enable : in std_ulogic_vector(0 to 1); + comp_thdid : in std_ulogic_vector(0 to 3); + thdid_enable : in std_ulogic_vector(0 to 1); + comp_pid : in std_ulogic_vector(0 to 7); + pid_enable : in std_ulogic; + comp_invalidate : in std_ulogic; + flash_invalidate : in std_ulogic; + + array_cmp_data : out std_ulogic_vector(0 to array_data_width-1); + rd_array_data : out std_ulogic_vector(0 to array_data_width-1); + + cam_cmp_data : out std_ulogic_vector(0 to cam_data_width-1); + cam_hit : out std_ulogic; + cam_hit_entry : out std_ulogic_vector(0 to 3); + entry_match : out std_ulogic_vector(0 to 15); + entry_valid : out std_ulogic_vector(0 to 15); + rd_cam_data : out std_ulogic_vector(0 to cam_data_width-1); + +----- new ports for IO plus ----------------------- + bypass_mux_enab_np1 : in std_ulogic; + bypass_attr_np1 : in std_ulogic_vector(0 to 20); + attr_np2 : out std_ulogic_vector(0 to 20); + rpn_np2 : out std_ulogic_vector(22 to 51) + + ); +END component; +---------------------------- +-- constants +---------------------------- +constant MMU_Mode_Value : std_ulogic := '0'; +constant TlbSel_Tlb : std_ulogic_vector(0 to 1) := "00"; +constant TlbSel_IErat : std_ulogic_vector(0 to 1) := "10"; +constant TlbSel_DErat : std_ulogic_vector(0 to 1) := "11"; +constant CAM_PgSize_1GB : std_ulogic_vector(0 to 2) := "110"; +constant CAM_PgSize_16MB : std_ulogic_vector(0 to 2) := "111"; +constant CAM_PgSize_1MB : std_ulogic_vector(0 to 2) := "101"; +constant CAM_PgSize_64KB : std_ulogic_vector(0 to 2) := "011"; +constant CAM_PgSize_4KB : std_ulogic_vector(0 to 2) := "001"; +constant WS0_PgSize_1GB : std_ulogic_vector(0 to 3) := "1010"; +constant WS0_PgSize_16MB : std_ulogic_vector(0 to 3) := "0111"; +constant WS0_PgSize_1MB : std_ulogic_vector(0 to 3) := "0101"; +constant WS0_PgSize_64KB : std_ulogic_vector(0 to 3) := "0011"; +constant WS0_PgSize_4KB : std_ulogic_vector(0 to 3) := "0001"; +constant eratpos_epn : natural := 0; +constant eratpos_x : natural := 52; +constant eratpos_size : natural := 53; +constant eratpos_v : natural := 56; +constant eratpos_thdid : natural := 57; +constant eratpos_class : natural := 61; +constant eratpos_extclass : natural := 63; +constant eratpos_wren : natural := 65; +constant eratpos_rpnrsvd : natural := 66; +constant eratpos_rpn : natural := 70; +constant eratpos_r : natural := 100; +constant eratpos_c : natural := 101; +constant eratpos_relsoon : natural := 102; +constant eratpos_wlc : natural := 103; +constant eratpos_resvattr : natural := 105; +constant eratpos_vf : natural := 106; +constant eratpos_ubits : natural := 107; +constant eratpos_wimge : natural := 111; +constant eratpos_usxwr : natural := 116; +constant eratpos_gs : natural := 122; +constant eratpos_ts : natural := 123; +constant eratpos_tid : natural := 124; +constant PorSeq_Idle : std_ulogic_vector(0 to 2) := "000"; +constant PorSeq_Stg1 : std_ulogic_vector(0 to 2) := "001"; +constant PorSeq_Stg2 : std_ulogic_vector(0 to 2) := "011"; +constant PorSeq_Stg3 : std_ulogic_vector(0 to 2) := "010"; +constant PorSeq_Stg4 : std_ulogic_vector(0 to 2) := "110"; +constant PorSeq_Stg5 : std_ulogic_vector(0 to 2) := "100"; +constant PorSeq_Stg6 : std_ulogic_vector(0 to 2) := "101"; +constant PorSeq_Stg7 : std_ulogic_vector(0 to 2) := "111"; +constant Por_Wr_Entry_Num1 : std_ulogic_vector(0 to num_entry_log2-1) := "1110"; +constant Por_Wr_Entry_Num2 : std_ulogic_vector(0 to num_entry_log2-1) := "1111"; +-- wr_cam_data +-- 0:51 - EPN +-- 52 - X +-- 53:55 - SIZE +-- 56 - V +-- 57:60 - ThdID +-- 61:62 - Class +-- 63:64 - ExtClass | TID_NZ +-- 65 - TGS +-- 66 - TS +-- 67:74 - TID +-- 75:78 - epn_cmpmasks: 34_39, 40_43, 44_47, 48_51 +-- 79:82 - xbit_cmpmasks: 34_51, 40_51, 44_51, 48_51 +-- 83 - parity for 75:82 +constant Por_Wr_Cam_Data1 : std_ulogic_vector(0 to 83) := "0000000000000000000000000000000011111111111111111111" & + '0' & "001" & '1' & "1111" & "00" & "00" & "00" & "00000000" & "11110000" & '0'; +constant Por_Wr_Cam_Data2 : std_ulogic_vector(0 to 83) := "0000000000000000000000000000000000000000000000000000" & + '0' & "001" & '1' & "1111" & "00" & "10" & "00" & "00000000" & "11110000" & '0'; +-- 16x143 version, 42b RA +-- wr_array_data +-- 0:29 - RPN +-- 30:31 - R,C +-- 32:33 - WLC +-- 34 - ResvAttr +-- 35 - VF +-- 36:39 - U0-U3 +-- 40:44 - WIMGE +-- 45:46 - UX,SX +-- 47:48 - UW,SW +-- 49:50 - UR,SR +-- 51:60 - CAM parity +-- 61:67 - Array parity +constant Por_Wr_Array_Data1 : std_ulogic_vector(0 to 67) := "111111111111111111111111111111" & + "00" & "0000" & "0000" & "01010" & "01" & "00" & "01" & "0000001000" & "0000000"; +constant Por_Wr_Array_Data2 : std_ulogic_vector(0 to 67) := "000000000000000000000000000000" & + "00" & "0000" & "0000" & "01010" & "01" & "00" & "01" & "0000001010" & "0000000"; +constant ex1_valid_offset : natural := 0; +constant ex1_ttype_offset : natural := ex1_valid_offset + thdid_width; +constant ex1_ws_offset : natural := ex1_ttype_offset + ttype_width+1; +constant ex1_rs_is_offset : natural := ex1_ws_offset + ws_width; +constant ex1_ra_entry_offset : natural := ex1_rs_is_offset + rs_is_width; +constant ex1_state_offset : natural := ex1_ra_entry_offset + ra_entry_width; +constant ex1_pid_offset : natural := ex1_state_offset + state_width; +constant ex1_extclass_offset : natural := ex1_pid_offset + pid_width; +constant ex1_tlbsel_offset : natural := ex1_extclass_offset + extclass_width; +constant ex2_valid_offset : natural := ex1_tlbsel_offset + tlbsel_width; +constant ex2_ttype_offset : natural := ex2_valid_offset + thdid_width; +constant ex2_ws_offset : natural := ex2_ttype_offset + ttype_width; +constant ex2_rs_is_offset : natural := ex2_ws_offset + ws_width; +constant ex2_ra_entry_offset : natural := ex2_rs_is_offset + rs_is_width; +constant ex2_state_offset : natural := ex2_ra_entry_offset + ra_entry_width; +constant ex2_pid_offset : natural := ex2_state_offset + state_width; +constant ex2_extclass_offset : natural := ex2_pid_offset + pid_width; +constant ex2_tlbsel_offset : natural := ex2_extclass_offset + extclass_width; +constant ex3_valid_offset : natural := ex2_tlbsel_offset + tlbsel_width; +constant ex3_ttype_offset : natural := ex3_valid_offset + thdid_width; +constant ex3_ws_offset : natural := ex3_ttype_offset + ttype_width; +constant ex3_rs_is_offset : natural := ex3_ws_offset + ws_width; +constant ex3_ra_entry_offset : natural := ex3_rs_is_offset + rs_is_width; +constant ex3_state_offset : natural := ex3_ra_entry_offset + ra_entry_width; +constant ex3_pid_offset : natural := ex3_state_offset + state_width; +constant ex3_extclass_offset : natural := ex3_pid_offset + pid_width; +constant ex3_tlbsel_offset : natural := ex3_extclass_offset + extclass_width; +constant ex3_eratsx_data_offset : natural := ex3_tlbsel_offset + tlbsel_width; +constant ex4_valid_offset : natural := ex3_eratsx_data_offset + 2 + num_entry_log2; +constant ex4_ttype_offset : natural := ex4_valid_offset + thdid_width; +constant ex4_ws_offset : natural := ex4_ttype_offset + ttype_width; +constant ex4_rs_is_offset : natural := ex4_ws_offset + ws_width; +constant ex4_ra_entry_offset : natural := ex4_rs_is_offset + rs_is_width; +constant ex4_state_offset : natural := ex4_ra_entry_offset + ra_entry_width; +constant ex4_pid_offset : natural := ex4_state_offset + state_width; +constant ex4_extclass_offset : natural := ex4_pid_offset + pid_width; +constant ex4_tlbsel_offset : natural := ex4_extclass_offset + extclass_width; +constant ex4_data_out_offset : natural := ex4_tlbsel_offset + tlbsel_width; +constant ex5_valid_offset : natural := ex4_data_out_offset + data_out_width; +constant ex5_ttype_offset : natural := ex5_valid_offset + thdid_width; +constant ex5_ws_offset : natural := ex5_ttype_offset + ttype_width; +constant ex5_rs_is_offset : natural := ex5_ws_offset + ws_width; +constant ex5_ra_entry_offset : natural := ex5_rs_is_offset + rs_is_width; +constant ex5_state_offset : natural := ex5_ra_entry_offset + ra_entry_width; +constant ex5_pid_offset : natural := ex5_state_offset + state_width; +constant ex5_extclass_offset : natural := ex5_pid_offset + pid_width; +constant ex5_tlbsel_offset : natural := ex5_extclass_offset + extclass_width; +constant ex5_data_in_offset : natural := ex5_tlbsel_offset + tlbsel_width; +constant ex6_valid_offset : natural := ex5_data_in_offset + rs_data_width; +constant ex6_ttype_offset : natural := ex6_valid_offset + thdid_width; +constant ex6_ws_offset : natural := ex6_ttype_offset + ttype_width; +constant ex6_rs_is_offset : natural := ex6_ws_offset + ws_width; +constant ex6_ra_entry_offset : natural := ex6_rs_is_offset + rs_is_width; +constant ex6_state_offset : natural := ex6_ra_entry_offset + ra_entry_width; +constant ex6_pid_offset : natural := ex6_state_offset + state_width; +constant ex6_extclass_offset : natural := ex6_pid_offset + pid_width; +constant ex6_tlbsel_offset : natural := ex6_extclass_offset + extclass_width; +constant ex6_data_in_offset : natural := ex6_tlbsel_offset + tlbsel_width; +constant iu1_flush_enab_offset : natural := ex6_data_in_offset + rs_data_width; +constant iu2_n_flush_req_offset : natural := iu1_flush_enab_offset + 1; +constant hold_req_offset : natural := iu2_n_flush_req_offset + thdid_width; +constant tlb_miss_offset : natural := hold_req_offset + thdid_width; +constant tlb_req_inprogress_offset : natural := tlb_miss_offset + thdid_width; +constant iu1_valid_offset : natural := tlb_req_inprogress_offset + thdid_width; +constant iu1_state_offset : natural := iu1_valid_offset + thdid_width; +constant iu1_pid_offset : natural := iu1_state_offset + state_width; +constant iu2_valid_offset : natural := iu1_pid_offset + pid_width; +constant iu2_state_offset : natural := iu2_valid_offset + thdid_width; +constant iu2_pid_offset : natural := iu2_state_offset + state_width; +constant iu2_miss_offset : natural := iu2_pid_offset + pid_width; +constant iu2_multihit_offset : natural := iu2_miss_offset + 2; +constant iu2_parerr_offset : natural := iu2_multihit_offset + 2; +constant iu2_isi_offset : natural := iu2_parerr_offset + 2; +constant iu2_tlbreq_offset : natural := iu2_isi_offset + 6; +constant iu2_multihit_b_pt_offset : natural := iu2_tlbreq_offset + 1; +constant iu2_first_hit_entry_pt_offset : natural := iu2_multihit_b_pt_offset + num_entry; +constant iu2_cam_cmp_data_offset : natural := iu2_first_hit_entry_pt_offset + num_entry-1; +constant iu2_array_cmp_data_offset : natural := iu2_cam_cmp_data_offset + cam_data_width; +constant ex4_rd_cam_data_offset : natural := iu2_array_cmp_data_offset + array_data_width; +constant ex4_rd_array_data_offset : natural := ex4_rd_cam_data_offset + cam_data_width; +constant ex3_parerr_offset : natural := ex4_rd_array_data_offset + array_data_width; +constant ex4_parerr_offset : natural := ex3_parerr_offset + thdid_width + 1; +constant ex4_ieen_offset : natural := ex4_parerr_offset + thdid_width + 2; +constant ex5_ieen_offset : natural := ex4_ieen_offset + thdid_width + num_entry_log2; +constant ex6_ieen_offset : natural := ex5_ieen_offset + thdid_width + num_entry_log2; +constant mmucr1_offset : natural := ex6_ieen_offset + 1 + num_entry_log2; +constant rpn_holdreg0_offset : natural := mmucr1_offset + 9; +constant rpn_holdreg1_offset : natural := rpn_holdreg0_offset + 64; +constant rpn_holdreg2_offset : natural := rpn_holdreg1_offset + 64; +constant rpn_holdreg3_offset : natural := rpn_holdreg2_offset + 64; +constant entry_valid_offset : natural := rpn_holdreg3_offset + 64; +constant entry_match_offset : natural := entry_valid_offset + 16; +constant watermark_offset : natural := entry_match_offset + 16; +constant eptr_offset : natural := watermark_offset + watermark_width; +constant lru_offset : natural := eptr_offset + eptr_width; +constant lru_update_event_offset : natural := lru_offset + lru_width; +constant lru_debug_offset : natural := lru_update_event_offset + 9; +constant scan_right_0 : natural := lru_debug_offset + 24 -1; +-- NOTE: scan_right_0 is maxed out! use scan_right_1 chain for new additions! +constant snoop_val_offset : natural := 0; +constant spare_a_offset : natural := snoop_val_offset + 3; +constant snoop_attr_offset : natural := spare_a_offset + 16; +constant snoop_addr_offset : natural := snoop_attr_offset + 26; +constant spare_b_offset : natural := snoop_addr_offset + epn_width; +constant por_seq_offset : natural := spare_b_offset + 16; +constant tlb_rel_val_offset : natural := por_seq_offset + 3; +constant tlb_rel_data_offset : natural := tlb_rel_val_offset + thdid_width + 1; +constant iu_mm_ierat_flush_offset : natural := tlb_rel_data_offset + 132; +constant iu_xu_ierat_ex2_flush_offset : natural := iu_mm_ierat_flush_offset + thdid_width; +constant ccr2_frat_paranoia_offset : natural := iu_xu_ierat_ex2_flush_offset + thdid_width; +constant ccr2_notlb_offset : natural := ccr2_frat_paranoia_offset + 10; +constant xucr4_mmu_mchk_offset : natural := ccr2_notlb_offset + 1; +constant mchk_flash_inv_offset : natural := xucr4_mmu_mchk_offset + 1; +constant ex7_valid_offset : natural := mchk_flash_inv_offset + 4; +constant ex7_ttype_offset : natural := ex7_valid_offset + thdid_width; +constant ex7_tlbsel_offset : natural := ex7_ttype_offset + ttype_width; +constant iu1_debug_offset : natural := ex7_tlbsel_offset + 2; +constant iu2_debug_offset : natural := iu1_debug_offset + 11; +constant iu1_stg_act_offset : natural := iu2_debug_offset + 17; +constant iu2_stg_act_offset : natural := iu1_stg_act_offset + 1; +constant iu3_stg_act_offset : natural := iu2_stg_act_offset + 1; +constant iu4_stg_act_offset : natural := iu3_stg_act_offset + 1; +constant ex1_stg_act_offset : natural := iu4_stg_act_offset + 1; +constant ex2_stg_act_offset : natural := ex1_stg_act_offset + 1; +constant ex3_stg_act_offset : natural := ex2_stg_act_offset + 1; +constant ex4_stg_act_offset : natural := ex3_stg_act_offset + 1; +constant ex5_stg_act_offset : natural := ex4_stg_act_offset + 1; +constant ex6_stg_act_offset : natural := ex5_stg_act_offset + 1; +constant ex7_stg_act_offset : natural := ex6_stg_act_offset + 1; +constant tlb_rel_act_offset : natural := ex7_stg_act_offset + 1; +constant snoop_act_offset : natural := tlb_rel_act_offset + 1; +constant trace_bus_enable_offset : natural := snoop_act_offset + 1; +constant an_ac_grffence_en_dc_offset : natural := trace_bus_enable_offset + 1; +constant scan_right_1 : natural := an_ac_grffence_en_dc_offset + 1 -1; +constant bcfg_offset : natural := 0; +constant boot_scan_right : natural := bcfg_offset + bcfg_width - 1; +---------------------------- +-- signals +---------------------------- +-- Latch signals +signal ex1_valid_d, ex1_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal ex1_ttype_d, ex1_ttype_q : std_ulogic_vector(0 to ttype_width); +signal ex1_ws_d, ex1_ws_q : std_ulogic_vector(0 to ws_width-1); +signal ex1_rs_is_d, ex1_rs_is_q : std_ulogic_vector(0 to rs_is_width-1); +signal ex1_ra_entry_d, ex1_ra_entry_q : std_ulogic_vector(0 to ra_entry_width-1); +signal ex1_state_d, ex1_state_q : std_ulogic_vector(0 to state_width-1); +signal ex1_pid_d, ex1_pid_q : std_ulogic_vector(0 to pid_width-1); +signal ex1_extclass_d, ex1_extclass_q : std_ulogic_vector(0 to extclass_width-1); +signal ex1_tlbsel_d, ex1_tlbsel_q : std_ulogic_vector(0 to tlbsel_width-1); +signal ex2_valid_d, ex2_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal ex2_ttype_d, ex2_ttype_q : std_ulogic_vector(0 to ttype_width-1); +signal ex2_ws_d, ex2_ws_q : std_ulogic_vector(0 to ws_width-1); +signal ex2_rs_is_d, ex2_rs_is_q : std_ulogic_vector(0 to rs_is_width-1); +signal ex2_ra_entry_d, ex2_ra_entry_q : std_ulogic_vector(0 to ra_entry_width-1); +signal ex2_state_d, ex2_state_q : std_ulogic_vector(0 to state_width-1); +signal ex2_pid_d, ex2_pid_q : std_ulogic_vector(0 to pid_width-1); +signal ex2_extclass_d, ex2_extclass_q : std_ulogic_vector(0 to extclass_width-1); +signal ex2_tlbsel_d, ex2_tlbsel_q : std_ulogic_vector(0 to tlbsel_width-1); +signal ex3_valid_d, ex3_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal ex3_ttype_d, ex3_ttype_q : std_ulogic_vector(0 to ttype_width-1); +signal ex3_ws_d, ex3_ws_q : std_ulogic_vector(0 to ws_width-1); +signal ex3_rs_is_d, ex3_rs_is_q : std_ulogic_vector(0 to rs_is_width-1); +signal ex3_ra_entry_d, ex3_ra_entry_q : std_ulogic_vector(0 to ra_entry_width-1); +signal ex3_state_d, ex3_state_q : std_ulogic_vector(0 to state_width-1); +signal ex3_pid_d, ex3_pid_q : std_ulogic_vector(0 to pid_width-1); +signal ex3_extclass_d, ex3_extclass_q : std_ulogic_vector(0 to extclass_width-1); +signal ex3_tlbsel_d, ex3_tlbsel_q : std_ulogic_vector(0 to tlbsel_width-1); +signal ex3_eratsx_data_d, ex3_eratsx_data_q : std_ulogic_vector(0 to 2+num_entry_log2-1); +signal ex4_valid_d, ex4_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal ex4_ttype_d, ex4_ttype_q : std_ulogic_vector(0 to ttype_width-1); +signal ex4_ws_d, ex4_ws_q : std_ulogic_vector(0 to ws_width-1); +signal ex4_rs_is_d, ex4_rs_is_q : std_ulogic_vector(0 to rs_is_width-1); +signal ex4_ra_entry_d, ex4_ra_entry_q : std_ulogic_vector(0 to ra_entry_width-1); +signal ex4_state_d, ex4_state_q : std_ulogic_vector(0 to state_width-1); +signal ex4_pid_d, ex4_pid_q : std_ulogic_vector(0 to pid_width-1); +signal ex4_extclass_d, ex4_extclass_q : std_ulogic_vector(0 to extclass_width-1); +signal ex4_tlbsel_d, ex4_tlbsel_q : std_ulogic_vector(0 to tlbsel_width-1); +signal ex4_data_out_d, ex4_data_out_q : std_ulogic_vector(64-data_out_width to 63); +signal ex5_valid_d, ex5_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal ex5_ttype_d, ex5_ttype_q : std_ulogic_vector(0 to ttype_width-1); +signal ex5_ws_d, ex5_ws_q : std_ulogic_vector(0 to ws_width-1); +signal ex5_rs_is_d, ex5_rs_is_q : std_ulogic_vector(0 to rs_is_width-1); +signal ex5_ra_entry_d, ex5_ra_entry_q : std_ulogic_vector(0 to ra_entry_width-1); +signal ex5_state_d, ex5_state_q : std_ulogic_vector(0 to state_width-1); +signal ex5_pid_d, ex5_pid_q : std_ulogic_vector(0 to pid_width-1); +signal ex5_extclass_d, ex5_extclass_q : std_ulogic_vector(0 to extclass_width-1); +signal ex5_tlbsel_d, ex5_tlbsel_q : std_ulogic_vector(0 to tlbsel_width-1); +signal ex5_data_in_d, ex5_data_in_q : std_ulogic_vector(64-rs_data_width to 63); +signal ex6_valid_d, ex6_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal ex6_ttype_d, ex6_ttype_q : std_ulogic_vector(0 to ttype_width-1); +signal ex6_ws_d, ex6_ws_q : std_ulogic_vector(0 to ws_width-1); +signal ex6_rs_is_d, ex6_rs_is_q : std_ulogic_vector(0 to rs_is_width-1); +signal ex6_ra_entry_d, ex6_ra_entry_q : std_ulogic_vector(0 to ra_entry_width-1); +signal ex6_state_d, ex6_state_q : std_ulogic_vector(0 to state_width-1); +signal ex6_pid_d, ex6_pid_q : std_ulogic_vector(0 to pid_width-1); +signal ex6_extclass_d, ex6_extclass_q : std_ulogic_vector(0 to extclass_width-1); +signal ex6_tlbsel_d, ex6_tlbsel_q : std_ulogic_vector(0 to tlbsel_width-1); +signal ex6_data_in_d, ex6_data_in_q : std_ulogic_vector(64-rs_data_width to 63); +signal ex7_valid_d, ex7_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal ex7_ttype_d, ex7_ttype_q : std_ulogic_vector(0 to ttype_width-1); +signal ex7_tlbsel_d, ex7_tlbsel_q : std_ulogic_vector(0 to tlbsel_width-1); +signal iu1_valid_d, iu1_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal iu1_state_d, iu1_state_q : std_ulogic_vector(0 to state_width-1); +signal iu1_pid_d, iu1_pid_q : std_ulogic_vector(0 to pid_width-1); +signal iu2_valid_d, iu2_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal iu2_state_d, iu2_state_q : std_ulogic_vector(0 to state_width-1); +signal iu2_pid_d, iu2_pid_q : std_ulogic_vector(0 to pid_width-1); +signal iu1_flush_enab_d, iu1_flush_enab_q : std_ulogic; +signal iu2_n_flush_req_d, iu2_n_flush_req_q : std_ulogic_vector(0 to thdid_width-1); +signal hold_req_d, hold_req_q : std_ulogic_vector(0 to thdid_width-1); +signal tlb_miss_d, tlb_miss_q : std_ulogic_vector(0 to thdid_width-1); +signal tlb_req_inprogress_d, tlb_req_inprogress_q : std_ulogic_vector(0 to thdid_width-1); +signal iu2_tlbreq_d, iu2_tlbreq_q : std_ulogic; +signal iu2_miss_d, iu2_miss_q : std_ulogic_vector(0 to 1); +signal iu2_multihit_d, iu2_multihit_q : std_ulogic_vector(0 to 1); +signal iu2_parerr_d, iu2_parerr_q : std_ulogic_vector(0 to 1); +signal iu2_isi_d, iu2_isi_q : std_ulogic_vector(0 to 5); +signal iu1_debug_d, iu1_debug_q : std_ulogic_vector(0 to 10); +signal iu2_debug_d, iu2_debug_q : std_ulogic_vector(0 to 16); +signal iu2_multihit_b_pt_d, iu2_multihit_b_pt_q : std_ulogic_vector(1 to num_entry); +signal iu2_first_hit_entry_pt_d, iu2_first_hit_entry_pt_q : std_ulogic_vector(1 to num_entry-1); +signal iu2_cam_cmp_data_d, iu2_cam_cmp_data_q : std_ulogic_vector(0 to cam_data_width-1); +signal iu2_array_cmp_data_d, iu2_array_cmp_data_q : std_ulogic_vector(0 to array_data_width-1); +signal ex4_rd_cam_data_d, ex4_rd_cam_data_q : std_ulogic_vector(0 to cam_data_width-1); +signal ex4_rd_array_data_d, ex4_rd_array_data_q : std_ulogic_vector(0 to array_data_width-1); +signal por_seq_d, por_seq_q : std_ulogic_vector(0 to 2); +signal ex3_parerr_d, ex3_parerr_q : std_ulogic_vector(0 to thdid_width); +signal ex4_parerr_d, ex4_parerr_q : std_ulogic_vector(0 to thdid_width+1); +signal ex4_ieen_d, ex4_ieen_q : std_ulogic_vector(0 to thdid_width+num_entry_log2-1); +signal ex5_ieen_d, ex5_ieen_q : std_ulogic_vector(0 to thdid_width+num_entry_log2-1); +signal ex6_ieen_d, ex6_ieen_q : std_ulogic_vector(0 to num_entry_log2); +signal mmucr1_d, mmucr1_q : std_ulogic_vector(0 to 8); +signal rpn_holdreg0_d, rpn_holdreg0_q : std_ulogic_vector(0 to 63); +signal rpn_holdreg1_d, rpn_holdreg1_q : std_ulogic_vector(0 to 63); +signal rpn_holdreg2_d, rpn_holdreg2_q : std_ulogic_vector(0 to 63); +signal rpn_holdreg3_d, rpn_holdreg3_q : std_ulogic_vector(0 to 63); +signal watermark_d, watermark_q : std_ulogic_vector(0 to watermark_width-1); +signal eptr_d, eptr_q : std_ulogic_vector(0 to eptr_width-1); +signal lru_d, lru_q : std_ulogic_vector(1 to lru_width); +signal lru_update_event_d, lru_update_event_q : std_ulogic_vector(0 to 8); +signal lru_debug_d, lru_debug_q : std_ulogic_vector(0 to 23); +signal snoop_val_d, snoop_val_q : std_ulogic_vector(0 to 2); +signal snoop_attr_d, snoop_attr_q : std_ulogic_vector(0 to 25); +signal snoop_addr_d, snoop_addr_q : std_ulogic_vector(52-epn_width to 51); +signal tlb_rel_val_d, tlb_rel_val_q : std_ulogic_vector(0 to 4); +signal tlb_rel_data_d, tlb_rel_data_q : std_ulogic_vector(0 to 131); +signal iu_mm_ierat_flush_d, iu_mm_ierat_flush_q : std_ulogic_vector(0 to thdid_width-1); +signal iu_xu_ierat_ex2_flush_d, iu_xu_ierat_ex2_flush_q : std_ulogic_vector(0 to thdid_width-1); +signal ccr2_frat_paranoia_d, ccr2_frat_paranoia_q : std_ulogic_vector(0 to 9); +signal ccr2_notlb_q, xucr4_mmu_mchk_q : std_ulogic; +signal mchk_flash_inv_d, mchk_flash_inv_q : std_ulogic_vector(0 to 3); +signal mchk_flash_inv_enab : std_ulogic; +signal spare_q : std_ulogic_vector(0 to 31); +signal bcfg_q, bcfg_q_b : std_ulogic_vector(0 to bcfg_width-1); +-- logic signals +signal iu2_isi_sig : std_ulogic; +signal iu2_miss_sig : std_ulogic; +signal iu2_parerr_sig : std_ulogic; +signal iu2_multihit_sig : std_ulogic; +signal iu1_multihit : std_ulogic; +signal iu1_multihit_b : std_ulogic; +signal iu1_first_hit_entry : std_ulogic_vector(0 to num_entry_log2-1); +signal iu2_first_hit_entry : std_ulogic_vector(0 to num_entry_log2-1); +signal iu2_multihit_enab : std_ulogic; +signal por_wr_cam_val : std_ulogic_vector(0 to 1); +signal por_wr_array_val : std_ulogic_vector(0 to 1); +signal por_wr_cam_data : std_ulogic_vector(0 to cam_data_width-1); +signal por_wr_array_data : std_ulogic_vector(0 to array_data_width-1); +signal por_wr_entry : std_ulogic_vector(0 to num_entry_log2-1); +signal por_hold_req : std_ulogic_vector(0 to thdid_width-1); +signal lru_way_encode : std_ulogic_vector(0 to num_entry_log2-1); +signal lru_rmt_vec : std_ulogic_vector(0 to lru_width); +signal lru_reset_vec, lru_set_vec : std_ulogic_vector(1 to lru_width); +signal lru_op_vec, lru_vp_vec : std_ulogic_vector(1 to lru_width); +signal lru_eff : std_ulogic_vector(1 to lru_width); +signal lru_watermark_mask : std_ulogic_vector(0 to lru_width); +signal entry_valid_watermarked : std_ulogic_vector(0 to lru_width); +signal eptr_p1 : std_ulogic_vector(0 to eptr_width-1); +signal ex1_ieratre, ex1_ieratwe, ex1_ieratsx : std_ulogic; +signal ex3_parerr_enab : std_ulogic; +signal ex4_parerr_enab : std_ulogic; +signal ex3_ieratwe, ex4_ieratwe, ex5_ieratwe, ex6_ieratwe, ex7_ieratwe : std_ulogic; +signal ex6_ieratwe_ws3 : std_ulogic; +signal iu2_cmp_data_calc_par : std_ulogic_vector(50 to 67); +-- synopsys translate_off +-- synopsys translate_on +signal iu2_cmp_data_parerr_epn : std_ulogic; +signal iu2_cmp_data_parerr_rpn : std_ulogic; +signal ex4_rd_data_calc_par : std_ulogic_vector(50 to 67); +signal ex4_rd_data_parerr_epn : std_ulogic; +signal ex4_rd_data_parerr_rpn : std_ulogic; +-- synopsys translate_off +-- synopsys translate_on +signal unused_dc : std_ulogic_vector(0 to 29); +-- synopsys translate_off +-- synopsys translate_on +signal mmucr0_gs_vec : std_ulogic_vector(0 to thdid_width-1); +signal mmucr0_ts_vec : std_ulogic_vector(0 to thdid_width-1); +signal tlb_rel_cmpmask : std_ulogic_vector(0 to 3); +signal tlb_rel_xbitmask : std_ulogic_vector(0 to 3); +signal tlb_rel_maskpar : std_ulogic; +signal ex6_data_cmpmask : std_ulogic_vector(0 to 3); +signal ex6_data_xbitmask : std_ulogic_vector(0 to 3); +signal ex6_data_maskpar : std_ulogic; +signal comp_addr_mux1 : std_ulogic_vector(0 to 51); +signal comp_addr_mux1_sel : std_ulogic; +signal lru_way_is_written : std_ulogic; +signal lru_way_is_hit_entry : std_ulogic; +-- Added for timing changes +signal ex1_pid_0, ex1_pid_1 : std_ulogic_vector(0 to pid_width-1); +-- CAM/Array signals +-- Read Port +signal rd_val : std_ulogic; +signal rw_entry : std_ulogic_vector(0 to 3); +-- Write Port +signal wr_array_par : std_ulogic_vector(51 to 67); +signal wr_array_data_nopar : std_ulogic_vector(0 to array_data_width-1-10-7); +signal wr_array_data : std_ulogic_vector(0 to array_data_width-1); +signal wr_cam_data : std_ulogic_vector(0 to cam_data_width-1); +signal wr_array_val : std_ulogic_vector(0 to 1); +signal wr_cam_val : std_ulogic_vector(0 to 1); +signal wr_val_early : std_ulogic; +-- CAM Port +signal comp_request : std_ulogic; +signal comp_addr : std_ulogic_vector(0 to 51); +signal addr_enable : std_ulogic_vector(0 to 1); +signal comp_pgsize : std_ulogic_vector(0 to 2); +signal pgsize_enable : std_ulogic; +signal comp_class : std_ulogic_vector(0 to 1); +signal class_enable : std_ulogic_vector(0 to 2); +signal comp_extclass : std_ulogic_vector(0 to 1); +signal extclass_enable : std_ulogic_vector(0 to 1); +signal comp_state : std_ulogic_vector(0 to 1); +signal state_enable : std_ulogic_vector(0 to 1); +signal comp_thdid : std_ulogic_vector(0 to 3); +signal thdid_enable : std_ulogic_vector(0 to 1); +signal comp_pid : std_ulogic_vector(0 to 7); +signal pid_enable : std_ulogic; +signal comp_invalidate : std_ulogic; +signal flash_invalidate : std_ulogic; +-- Array Outputs +signal array_cmp_data : std_ulogic_vector(0 to array_data_width-1); +signal rd_array_data : std_ulogic_vector(0 to array_data_width-1); +-- CAM Outputs +signal cam_cmp_data : std_ulogic_vector(0 to cam_data_width-1); +signal cam_hit : std_ulogic; +signal cam_hit_entry : std_ulogic_vector(0 to 3); +signal entry_match, entry_match_q : std_ulogic_vector(0 to 15); +signal entry_valid, entry_valid_q : std_ulogic_vector(0 to 15); +signal rd_cam_data : std_ulogic_vector(0 to cam_data_width-1); +-- synopsys translate_off +-- synopsys translate_on +signal cam_pgsize : std_ulogic_vector(0 to 2); +signal ws0_pgsize : std_ulogic_vector(0 to 3); +-- new cam _np2 signals +signal bypass_mux_enab_np1 : std_ulogic; +signal bypass_attr_np1 : std_ulogic_vector(0 to 20); +signal attr_np2 : std_ulogic_vector(0 to 20); +signal rpn_np2 : std_ulogic_vector(22 to 51); +-- Pervasive +signal pc_sg_1 : std_ulogic; +signal pc_sg_0 : std_ulogic; +signal pc_func_sl_thold_1 : std_ulogic; +signal pc_func_sl_thold_0 : std_ulogic; +signal pc_func_sl_thold_0_b : std_ulogic; +signal pc_func_slp_sl_thold_1 : std_ulogic; +signal pc_func_slp_sl_thold_0 : std_ulogic; +signal pc_func_slp_sl_thold_0_b : std_ulogic; +signal pc_func_sl_force : std_ulogic; +signal pc_func_slp_sl_force : std_ulogic; +signal pc_cfg_slp_sl_thold_1 : std_ulogic; +signal pc_cfg_slp_sl_thold_0 : std_ulogic; +signal pc_cfg_slp_sl_thold_0_b : std_ulogic; +signal pc_cfg_slp_sl_force : std_ulogic; +signal lcb_dclk : std_ulogic; +signal lcb_lclk : clk_logic; +signal init_alias : std_ulogic; +-- Clock Gating +signal iu1_stg_act_d, iu1_stg_act_q :std_ulogic; +signal iu2_stg_act_d, iu2_stg_act_q :std_ulogic; +signal iu3_stg_act_d, iu3_stg_act_q :std_ulogic; +signal iu4_stg_act_d, iu4_stg_act_q :std_ulogic; +signal ex1_stg_act_d, ex1_stg_act_q :std_ulogic; +signal ex2_stg_act_d, ex2_stg_act_q :std_ulogic; +signal ex3_stg_act_d, ex3_stg_act_q :std_ulogic; +signal ex4_stg_act_d, ex4_stg_act_q :std_ulogic; +signal ex5_stg_act_d, ex5_stg_act_q :std_ulogic; +signal ex6_stg_act_d, ex6_stg_act_q :std_ulogic; +signal ex7_stg_act_d, ex7_stg_act_q :std_ulogic; +signal iu1_cmp_data_act, iu1_grffence_act, iu1_or_iu2_grffence_act, iu2_to_iu4_grffence_act :std_ulogic; +signal ex3_rd_data_act, ex3_data_out_act :std_ulogic; +signal ex2_grffence_act, ex3_grffence_act :std_ulogic; +signal an_ac_grffence_en_dc_q, trace_bus_enable_q :std_ulogic; +signal entry_valid_act, entry_match_act :std_ulogic; +signal not_grffence_act, notlb_grffence_act :std_ulogic; +signal tlb_rel_act_d, tlb_rel_act_q, tlb_rel_act :std_ulogic; +signal snoop_act_q :std_ulogic; +signal lru_update_act, debug_grffence_act, eratsx_data_act :std_ulogic; +signal siv_0 : std_ulogic_vector(0 to scan_right_0); +signal sov_0 : std_ulogic_vector(0 to scan_right_0); +signal siv_1 : std_ulogic_vector(0 to scan_right_1); +signal sov_1 : std_ulogic_vector(0 to scan_right_1); +signal bsiv : std_ulogic_vector(0 to boot_scan_right); +signal bsov : std_ulogic_vector(0 to boot_scan_right); +signal tiup : std_ulogic; + BEGIN --@@ START OF EXECUTABLE CODE FOR IUQ_IC_IERAT + +----------------------------------------------------------------------- +-- ACT Generation +----------------------------------------------------------------------- +iu1_stg_act_d <= comp_request or spr_ic_clockgate_dis; +iu2_stg_act_d <= iu1_stg_act_q; +iu3_stg_act_d <= iu2_stg_act_q; +iu4_stg_act_d <= iu3_stg_act_q; +ex1_stg_act_d <= or_reduce(xu_iu_rf1_val) or spr_ic_clockgate_dis; +ex2_stg_act_d <= ex1_stg_act_q; +ex3_stg_act_d <= ex2_stg_act_q; +ex4_stg_act_d <= ex3_stg_act_q; +ex5_stg_act_d <= ex4_stg_act_q; +ex6_stg_act_d <= ex5_stg_act_q; +ex7_stg_act_d <= ex6_stg_act_q; +iu1_cmp_data_act <= iu1_stg_act_q and not(an_ac_grffence_en_dc); +iu1_grffence_act <= iu1_stg_act_q and not(an_ac_grffence_en_dc); +iu1_or_iu2_grffence_act <= (iu1_stg_act_q or iu2_stg_act_q) and not(an_ac_grffence_en_dc); +iu2_to_iu4_grffence_act <= (iu2_stg_act_q or iu3_stg_act_q or iu4_stg_act_q) and not(an_ac_grffence_en_dc); +ex2_grffence_act <= ex2_stg_act_q and not(an_ac_grffence_en_dc); +ex3_rd_data_act <= ex3_stg_act_q and not(an_ac_grffence_en_dc); +ex3_data_out_act <= ex3_stg_act_q and not(an_ac_grffence_en_dc); +ex3_grffence_act <= ex3_stg_act_q and not(an_ac_grffence_en_dc); +entry_valid_act <= not an_ac_grffence_en_dc; +entry_match_act <= not an_ac_grffence_en_dc; +not_grffence_act <= not an_ac_grffence_en_dc; +lru_update_act <= ex6_stg_act_q or ex7_stg_act_q or lru_update_event_q(4) or lru_update_event_q(8) or flash_invalidate or ex6_ieratwe_ws3; +notlb_grffence_act <= (not(ccr2_notlb_q) or spr_ic_clockgate_dis) and not(an_ac_grffence_en_dc); +debug_grffence_act <= trace_bus_enable_q and not(an_ac_grffence_en_dc); +eratsx_data_act <= (iu1_stg_act_q or ex2_stg_act_q) and not(an_ac_grffence_en_dc); +----------------------------------------------------------------------- +-- Logic +----------------------------------------------------------------------- +tiup <= '1'; +init_alias <= pc_iu_init_reset; +-- timing latches for the reloads +tlb_rel_val_d <= mm_iu_ierat_rel_val; +tlb_rel_data_d <= mm_iu_ierat_rel_data; +tlb_rel_act_d <= mm_iu_ierat_rel_data(eratpos_relsoon); +tlb_rel_act <= (tlb_rel_act_q and not(ccr2_notlb_q)); +-- timing latches for the ifrat delusional paranoia real mode +ccr2_frat_paranoia_d(0 TO 8) <= xu_iu_spr_ccr2_ifratsc; +ccr2_frat_paranoia_d(9) <= xu_iu_spr_ccr2_ifrat; +-------------------------------------------------- +ex1_valid_d <= xu_iu_rf1_val and not(xu_rf1_flush); +ex1_ttype_d(0 TO ttype_width-3) <= xu_iu_rf1_is_eratre & xu_iu_rf1_is_eratwe & xu_iu_rf1_is_eratsx & xu_iu_rf1_is_eratilx; +ex1_ttype_d(ttype_width-2 TO ttype_width) <= xu_iu_rf1_t; +ex1_ws_d <= xu_iu_rf1_ws; +ex1_rs_is_d <= (others => '0'); +ex1_ra_entry_d <= (others => '0'); +-- state: 0:pr 1:hs 2:ds 3:cm +ex1_state_d(0) <= or_reduce(xu_iu_msr_pr and xu_iu_rf1_val); +ex1_state_d(1) <= (or_reduce(xu_iu_msr_hv and xu_iu_rf1_val) and not xu_iu_rf1_is_eratsx) or + (or_reduce(mmucr0_gs_vec and xu_iu_rf1_val) and xu_iu_rf1_is_eratsx); +ex1_state_d(2) <= (or_reduce(xu_iu_msr_is and xu_iu_rf1_val) and not xu_iu_rf1_is_eratsx) or + (or_reduce(mmucr0_ts_vec and xu_iu_rf1_val) and xu_iu_rf1_is_eratsx); +ex1_state_d(3) <= or_reduce(xu_iu_msr_cm and xu_iu_rf1_val); +mmucr0_gs_vec <= mm_iu_ierat_mmucr0_0(2) & mm_iu_ierat_mmucr0_1(2) & mm_iu_ierat_mmucr0_2(2) & mm_iu_ierat_mmucr0_3(2); +mmucr0_ts_vec <= mm_iu_ierat_mmucr0_0(3) & mm_iu_ierat_mmucr0_1(3) & mm_iu_ierat_mmucr0_2(3) & mm_iu_ierat_mmucr0_3(3); +ex1_extclass_d <= mm_iu_ierat_mmucr0_1(0 to 1) when xu_iu_rf1_val(1)='1' + else mm_iu_ierat_mmucr0_2(0 to 1) when xu_iu_rf1_val(2)='1' + else mm_iu_ierat_mmucr0_3(0 to 1) when xu_iu_rf1_val(3)='1' + else mm_iu_ierat_mmucr0_0(0 to 1); +ex1_tlbsel_d <= mm_iu_ierat_mmucr0_1(4 to 5) when xu_iu_rf1_val(1)='1' + else mm_iu_ierat_mmucr0_2(4 to 5) when xu_iu_rf1_val(2)='1' + else mm_iu_ierat_mmucr0_3(4 to 5) when xu_iu_rf1_val(3)='1' + else mm_iu_ierat_mmucr0_0(4 to 5); +ex1_pid_d <= gate_and((xu_iu_rf1_is_eratsx='1'), ex1_pid_0) or gate_and((xu_iu_rf1_is_eratsx='0'), ex1_pid_1); +ex1_pid_0 <= gate_and((xu_iu_rf1_val(0)='1'),mm_iu_ierat_mmucr0_0(6 to 19)) or + gate_and((xu_iu_rf1_val(1)='1'),mm_iu_ierat_mmucr0_1(6 to 19)) or + gate_and((xu_iu_rf1_val(2)='1'),mm_iu_ierat_mmucr0_2(6 to 19)) or + gate_and((xu_iu_rf1_val(3)='1'),mm_iu_ierat_mmucr0_3(6 to 19)); +ex1_pid_1 <= gate_and((xu_iu_rf1_val(0)='1'),mm_iu_ierat_pid0) or + gate_and((xu_iu_rf1_val(1)='1'),mm_iu_ierat_pid1) or + gate_and((xu_iu_rf1_val(2)='1'),mm_iu_ierat_pid2) or + gate_and((xu_iu_rf1_val(3)='1'),mm_iu_ierat_pid3); +ex1_ieratre <= or_reduce(ex1_valid_q) and ex1_ttype_q(0) and ex1_tlbsel_q(0) and not ex1_tlbsel_q(1); +ex1_ieratwe <= or_reduce(ex1_valid_q) and ex1_ttype_q(1) and ex1_tlbsel_q(0) and not ex1_tlbsel_q(1); +ex1_ieratsx <= or_reduce(ex1_valid_q) and ex1_ttype_q(2) and ex1_tlbsel_q(0) and not ex1_tlbsel_q(1); +-------------------------------------------------- +ex2_valid_d <= ex1_valid_q and not(xu_ex1_flush); +ex2_ttype_d(0 TO ttype_width-3) <= ex1_ttype_q(0 to ttype_width-3); +ex2_ttype_d(ttype_width-2 TO ttype_width-1) <= xu_iu_ex1_is_csync & xu_iu_ex1_is_isync; +ex2_ws_d <= ex1_ws_q; +ex2_rs_is_d <= xu_iu_ex1_rs_is; +ex2_ra_entry_d <= xu_iu_ex1_ra_entry; +ex2_state_d <= ex1_state_q; +ex2_pid_d <= ex1_pid_q; +ex2_extclass_d <= ex1_extclass_q; +ex2_tlbsel_d <= ex1_tlbsel_q; +-------------------------------------------------- +ex3_valid_d <= ex2_valid_q and not(xu_ex2_flush); +ex3_ttype_d <= ex2_ttype_q; +ex3_ws_d <= ex2_ws_q; +ex3_rs_is_d <= ex2_rs_is_q; +ex3_ra_entry_d <= iu1_first_hit_entry when ex2_ttype_q(2 to 3)/="00" else ex2_ra_entry_q; +ex3_tlbsel_d <= ex2_tlbsel_q; +ex3_extclass_d <= ex2_extclass_q; +-- state: 0:pr 1:hs 2:ds 3:cm +ex3_state_d <= ex2_state_q; +ex3_pid_d <= ex2_pid_q; +ex3_ieratwe <= or_reduce(ex3_valid_q) and ex3_ttype_q(1) and ex3_tlbsel_q(0) and not ex3_tlbsel_q(1); +-------------------------------------------------- +ex4_valid_d <= ex3_valid_q and not(xu_ex3_flush); +ex4_ttype_d <= ex3_ttype_q; +ex4_ws_d <= ex3_ws_q; +ex4_rs_is_d <= ex3_rs_is_q; +ex4_ra_entry_d <= ex3_ra_entry_q; +ex4_tlbsel_d <= ex3_tlbsel_q; +-- muxes for eratre and sending mmucr0 ExtClass,State,TID +ex4_extclass_d <= rd_cam_data(63 to 64) when (ex3_valid_q/="0000" and ex3_ttype_q(0)='1' and ex3_ws_q="00") + else ex3_extclass_q; +-- state: 0:pr 1:hs 2:ds 3:cm +ex4_state_d <= ex3_state_q(0) & rd_cam_data(65 to 66) & ex3_state_q(3) when (ex3_valid_q/="0000" and ex3_ttype_q(0)='1' and ex3_ws_q="00") + else ex3_state_q; +ex4_pid_d <= rd_cam_data(61 to 62) & rd_cam_data(57 to 60) & rd_cam_data(67 to 74) + when (ex3_valid_q/="0000" and ex3_ttype_q(0)='1' and ex3_ws_q="00") + else ex3_pid_q; +ex4_ieratwe <= or_reduce(ex4_valid_q) and ex4_ttype_q(1) and ex4_tlbsel_q(0) and not ex4_tlbsel_q(1); +-------------------------------------------------- +ex5_valid_d <= ex4_valid_q and not(xu_ex4_flush); +ex5_ws_d <= ex4_ws_q; +ex5_rs_is_d <= ex4_rs_is_q; +ex5_ra_entry_d <= ex4_ra_entry_q; +-- ttype <= 0:eratre & 1:eratwe & 2:eratsx & 3:eratilx & 4:csync & 5:isync; +ex5_ttype_d(0 TO 5) <= ex4_ttype_q(0 to 5); +-- mmucr0: 0:1-ECL|TID_NZ, 2:3-tgs/ts, 4:5-tlbsel, 6:19-tid, +ex5_extclass_d <= ex4_extclass_q; +-- state: 0:pr 1:hs 2:ds 3:cm +ex5_state_d <= ex4_state_q; +ex5_pid_d <= ex4_pid_q; +ex5_tlbsel_d <= ex4_tlbsel_q; +ex5_data_in_d <= xu_iu_ex4_rs_data; +ex5_ieratwe <= or_reduce(ex5_valid_q) and ex5_ttype_q(1) and ex5_tlbsel_q(0) and not ex5_tlbsel_q(1); +-------------------------------------------------- +ex6_valid_d <= ex5_valid_q and not(xu_ex5_flush); +ex6_ws_d <= ex5_ws_q; +ex6_rs_is_d <= ex5_rs_is_q; +ex6_ra_entry_d <= ex5_ra_entry_q; +-- ttype <= 0:eratre & 1:eratwe & 2:eratsx & 3:eratilx & 4:csync & 5:isync; +ex6_ttype_d(0 TO 3) <= ex5_ttype_q(0 to 3); +-- mmucr1_q: 0-IRRE, 1-REE, 2-CEE, 3-csync, 4-isync, 5:6-IPEI, 7:8-ICTID/ITTID +ex6_ttype_d(4) <= '1' when (ex5_ttype_q(4)='1' and mmucr1_q(3)='0' and ccr2_notlb_q=MMU_Mode_Value) + else '0'; +ex6_ttype_d(5) <= '1' when (ex5_ttype_q(5)='1' and mmucr1_q(4)='0' and ccr2_notlb_q=MMU_Mode_Value) + else '0'; +-- mmucr0: 0:1-ECL|TID_NZ, 2:3-tgs/ts, 4:5-tlbsel, 6:19-tid, +ex6_extclass_d <= mm_iu_ierat_mmucr0_0(0 to 1) + when (ex5_valid_q="1000" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else mm_iu_ierat_mmucr0_1(0 to 1) + when (ex5_valid_q="0100" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else mm_iu_ierat_mmucr0_2(0 to 1) + when (ex5_valid_q="0010" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else mm_iu_ierat_mmucr0_3(0 to 1) + when (ex5_valid_q="0001" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else ex5_extclass_q; +-- state: 0:pr 1:hs 2:ds 3:cm +ex6_state_d <= xu_iu_msr_pr(0) & mm_iu_ierat_mmucr0_0(2 to 3) & xu_iu_msr_cm(0) + when (ex5_valid_q="1000" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else xu_iu_msr_pr(1) & mm_iu_ierat_mmucr0_1(2 to 3) & xu_iu_msr_cm(1) + when (ex5_valid_q="0100" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else xu_iu_msr_pr(2) & mm_iu_ierat_mmucr0_2(2 to 3) & xu_iu_msr_cm(2) + when (ex5_valid_q="0010" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else xu_iu_msr_pr(3) & mm_iu_ierat_mmucr0_3(2 to 3) & xu_iu_msr_cm(3) + when (ex5_valid_q="0001" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else ex5_state_q; +ex6_pid_d <= mm_iu_ierat_mmucr0_0(6 to 19) + when (ex5_valid_q="1000" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else mm_iu_ierat_mmucr0_1(6 to 19) + when (ex5_valid_q="0100" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else mm_iu_ierat_mmucr0_2(6 to 19) + when (ex5_valid_q="0010" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else mm_iu_ierat_mmucr0_3(6 to 19) + when (ex5_valid_q="0001" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else ex5_pid_q; +ex6_tlbsel_d <= mm_iu_ierat_mmucr0_0(4 to 5) + when (ex5_valid_q="1000" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else mm_iu_ierat_mmucr0_1(4 to 5) + when (ex5_valid_q="0100" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else mm_iu_ierat_mmucr0_2(4 to 5) + when (ex5_valid_q="0010" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else mm_iu_ierat_mmucr0_3(4 to 5) + when (ex5_valid_q="0001" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else ex5_tlbsel_q; +ex6_data_in_d <= ex5_data_in_q; +ex6_ieratwe <= or_reduce(ex6_valid_q) and ex6_ttype_q(1) and ex6_tlbsel_q(0) and not ex6_tlbsel_q(1); +-------------------------------------------------- +-- for flushing +ex7_valid_d <= ex6_valid_q; +ex7_ttype_d <= ex6_ttype_q; +ex7_tlbsel_d <= ex6_tlbsel_q; +ex7_ieratwe <= or_reduce(ex7_valid_q) and ex7_ttype_q(1) and ex7_tlbsel_q(0) and not ex7_tlbsel_q(1); +-- adding local iu2 flush request for timing +iu1_valid_d <= iu_ierat_iu0_thdid and (0 to thdid_width-1 => iu_ierat_iu0_val) and not(iu_ierat_iu0_flush) and not(xu_iu_flush) and not(iu2_n_flush_req_q); +-- state: 0:pr 1:hs 2:ds 3:cm +iu1_state_d(0) <= or_reduce(xu_iu_msr_pr and iu_ierat_iu0_thdid); +iu1_state_d(1) <= or_reduce(xu_iu_msr_hv and iu_ierat_iu0_thdid); +iu1_state_d(2) <= or_reduce(xu_iu_msr_is and iu_ierat_iu0_thdid); +iu1_state_d(3) <= or_reduce(xu_iu_msr_cm and iu_ierat_iu0_thdid); +iu1_pid_d <= ( mm_iu_ierat_pid0 and (0 to pid_width-1 => iu_ierat_iu0_thdid(0)) ) or + ( mm_iu_ierat_pid1 and (0 to pid_width-1 => iu_ierat_iu0_thdid(1)) ) or + ( mm_iu_ierat_pid2 and (0 to pid_width-1 => iu_ierat_iu0_thdid(2)) ) or + ( mm_iu_ierat_pid3 and (0 to pid_width-1 => iu_ierat_iu0_thdid(3)) ); +-- adding local iu2 flush request for timing +iu2_valid_d <= iu1_valid_q and not(iu_ierat_iu1_flush) and not(xu_iu_flush) and not(iu2_n_flush_req_q); +iu2_state_d <= iu1_state_q; +iu2_pid_d <= iu1_pid_q; +iu_mm_ierat_flush_d <= iu_ierat_iu1_flush; +mmucr1_d <= mm_iu_ierat_mmucr1; +-- TIMING FIXES 2009/03/27 +MQQ1:IU1_MULTIHIT_B_PT(1) <= + Eq(( ENTRY_MATCH(1) & ENTRY_MATCH(2) & + ENTRY_MATCH(3) & ENTRY_MATCH(4) & + ENTRY_MATCH(5) & ENTRY_MATCH(6) & + ENTRY_MATCH(7) & ENTRY_MATCH(8) & + ENTRY_MATCH(9) & ENTRY_MATCH(10) & + ENTRY_MATCH(11) & ENTRY_MATCH(12) & + ENTRY_MATCH(13) & ENTRY_MATCH(14) & + ENTRY_MATCH(15) ) , STD_ULOGIC_VECTOR'("000000000000000")); +MQQ2:IU1_MULTIHIT_B_PT(2) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(2) & + ENTRY_MATCH(3) & ENTRY_MATCH(4) & + ENTRY_MATCH(5) & ENTRY_MATCH(6) & + ENTRY_MATCH(7) & ENTRY_MATCH(8) & + ENTRY_MATCH(9) & ENTRY_MATCH(10) & + ENTRY_MATCH(11) & ENTRY_MATCH(12) & + ENTRY_MATCH(13) & ENTRY_MATCH(14) & + ENTRY_MATCH(15) ) , STD_ULOGIC_VECTOR'("000000000000000")); +MQQ3:IU1_MULTIHIT_B_PT(3) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(3) & ENTRY_MATCH(4) & + ENTRY_MATCH(5) & ENTRY_MATCH(6) & + ENTRY_MATCH(7) & ENTRY_MATCH(8) & + ENTRY_MATCH(9) & ENTRY_MATCH(10) & + ENTRY_MATCH(11) & ENTRY_MATCH(12) & + ENTRY_MATCH(13) & ENTRY_MATCH(14) & + ENTRY_MATCH(15) ) , STD_ULOGIC_VECTOR'("000000000000000")); +MQQ4:IU1_MULTIHIT_B_PT(4) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(4) & + ENTRY_MATCH(5) & ENTRY_MATCH(6) & + ENTRY_MATCH(7) & ENTRY_MATCH(8) & + ENTRY_MATCH(9) & ENTRY_MATCH(10) & + ENTRY_MATCH(11) & ENTRY_MATCH(12) & + ENTRY_MATCH(13) & ENTRY_MATCH(14) & + ENTRY_MATCH(15) ) , STD_ULOGIC_VECTOR'("000000000000000")); +MQQ5:IU1_MULTIHIT_B_PT(5) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(5) & ENTRY_MATCH(6) & + ENTRY_MATCH(7) & ENTRY_MATCH(8) & + ENTRY_MATCH(9) & ENTRY_MATCH(10) & + ENTRY_MATCH(11) & ENTRY_MATCH(12) & + ENTRY_MATCH(13) & ENTRY_MATCH(14) & + ENTRY_MATCH(15) ) , STD_ULOGIC_VECTOR'("000000000000000")); +MQQ6:IU1_MULTIHIT_B_PT(6) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(6) & + ENTRY_MATCH(7) & ENTRY_MATCH(8) & + ENTRY_MATCH(9) & ENTRY_MATCH(10) & + ENTRY_MATCH(11) & ENTRY_MATCH(12) & + ENTRY_MATCH(13) & ENTRY_MATCH(14) & + ENTRY_MATCH(15) ) , STD_ULOGIC_VECTOR'("000000000000000")); +MQQ7:IU1_MULTIHIT_B_PT(7) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(7) & ENTRY_MATCH(8) & + ENTRY_MATCH(9) & ENTRY_MATCH(10) & + ENTRY_MATCH(11) & ENTRY_MATCH(12) & + ENTRY_MATCH(13) & ENTRY_MATCH(14) & + ENTRY_MATCH(15) ) , STD_ULOGIC_VECTOR'("000000000000000")); +MQQ8:IU1_MULTIHIT_B_PT(8) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(8) & + ENTRY_MATCH(9) & ENTRY_MATCH(10) & + ENTRY_MATCH(11) & ENTRY_MATCH(12) & + ENTRY_MATCH(13) & ENTRY_MATCH(14) & + ENTRY_MATCH(15) ) , STD_ULOGIC_VECTOR'("000000000000000")); +MQQ9:IU1_MULTIHIT_B_PT(9) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(9) & ENTRY_MATCH(10) & + ENTRY_MATCH(11) & ENTRY_MATCH(12) & + ENTRY_MATCH(13) & ENTRY_MATCH(14) & + ENTRY_MATCH(15) ) , STD_ULOGIC_VECTOR'("000000000000000")); +MQQ10:IU1_MULTIHIT_B_PT(10) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(10) & + ENTRY_MATCH(11) & ENTRY_MATCH(12) & + ENTRY_MATCH(13) & ENTRY_MATCH(14) & + ENTRY_MATCH(15) ) , STD_ULOGIC_VECTOR'("000000000000000")); +MQQ11:IU1_MULTIHIT_B_PT(11) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(11) & ENTRY_MATCH(12) & + ENTRY_MATCH(13) & ENTRY_MATCH(14) & + ENTRY_MATCH(15) ) , STD_ULOGIC_VECTOR'("000000000000000")); +MQQ12:IU1_MULTIHIT_B_PT(12) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(12) & + ENTRY_MATCH(13) & ENTRY_MATCH(14) & + ENTRY_MATCH(15) ) , STD_ULOGIC_VECTOR'("000000000000000")); +MQQ13:IU1_MULTIHIT_B_PT(13) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(13) & ENTRY_MATCH(14) & + ENTRY_MATCH(15) ) , STD_ULOGIC_VECTOR'("000000000000000")); +MQQ14:IU1_MULTIHIT_B_PT(14) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(14) & + ENTRY_MATCH(15) ) , STD_ULOGIC_VECTOR'("000000000000000")); +MQQ15:IU1_MULTIHIT_B_PT(15) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(15) ) , STD_ULOGIC_VECTOR'("000000000000000")); +MQQ16:IU1_MULTIHIT_B_PT(16) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) ) , STD_ULOGIC_VECTOR'("000000000000000")); +-- Table IU1_MULTIHIT_B Signal Assignments for Outputs +MQQ17:IU1_MULTIHIT_B <= + (IU1_MULTIHIT_B_PT(1) OR IU1_MULTIHIT_B_PT(2) + OR IU1_MULTIHIT_B_PT(3) OR IU1_MULTIHIT_B_PT(4) + OR IU1_MULTIHIT_B_PT(5) OR IU1_MULTIHIT_B_PT(6) + OR IU1_MULTIHIT_B_PT(7) OR IU1_MULTIHIT_B_PT(8) + OR IU1_MULTIHIT_B_PT(9) OR IU1_MULTIHIT_B_PT(10) + OR IU1_MULTIHIT_B_PT(11) OR IU1_MULTIHIT_B_PT(12) + OR IU1_MULTIHIT_B_PT(13) OR IU1_MULTIHIT_B_PT(14) + OR IU1_MULTIHIT_B_PT(15) OR IU1_MULTIHIT_B_PT(16) + ); + +iu1_multihit <= not iu1_multihit_b; +iu2_multihit_b_pt_d <= iu1_multihit_b_pt; +iu2_multihit_enab <= not or_reduce(iu2_multihit_b_pt_q); +-- Encoder for the iu1 phase first hit entry number +-- +-- Final Table Listing +-- *INPUTS*==============*OUTPUTS*==============* +-- | | | +-- | entry_match | iu1_first_hit_entry | +-- | | | | | +-- | | | | | +-- | | | | | +-- | | 111111 | | | +-- | 0123456789012345 | 0123 | +-- *TYPE*================+======================+ +-- | PPPPPPPPPPPPPPPP | PPPP | +-- *POLARITY*----------->| ++++ | +-- *PHASE*-------------->| TTTT | +-- *OPTIMIZE*----------->| AAAA | +-- *TERMS*===============+======================+ +-- 1 | 0000000000000001 | 1111 | +-- 2 | 000000000000001- | 111. | +-- 3 | 00000000000001-- | 11.1 | +-- 4 | 0000000000001--- | 11.. | +-- 5 | 000000000001---- | 1.11 | +-- 6 | 00000000001----- | 1.1. | +-- 7 | 0000000001------ | 1..1 | +-- 8 | 000000001------- | 1... | +-- 9 | 00000001-------- | .111 | +-- 10 | 0000001--------- | .11. | +-- 11 | 000001---------- | .1.1 | +-- 12 | 00001----------- | .1.. | +-- 13 | 0001------------ | ..11 | +-- 14 | 001------------- | ..1. | +-- 15 | 01-------------- | ...1 | +-- *============================================* +-- +-- Table IU1_FIRST_HIT_ENTRY Signal Assignments for Product Terms +MQQ18:IU1_FIRST_HIT_ENTRY_PT(1) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) + ) , STD_ULOGIC_VECTOR'("0000000000000001")); +MQQ19:IU1_FIRST_HIT_ENTRY_PT(2) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) ) , STD_ULOGIC_VECTOR'("000000000000001")); +MQQ20:IU1_FIRST_HIT_ENTRY_PT(3) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) + ) , STD_ULOGIC_VECTOR'("00000000000001")); +MQQ21:IU1_FIRST_HIT_ENTRY_PT(4) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) ) , STD_ULOGIC_VECTOR'("0000000000001")); +MQQ22:IU1_FIRST_HIT_ENTRY_PT(5) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) + ) , STD_ULOGIC_VECTOR'("000000000001")); +MQQ23:IU1_FIRST_HIT_ENTRY_PT(6) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) ) , STD_ULOGIC_VECTOR'("00000000001")); +MQQ24:IU1_FIRST_HIT_ENTRY_PT(7) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) + ) , STD_ULOGIC_VECTOR'("0000000001")); +MQQ25:IU1_FIRST_HIT_ENTRY_PT(8) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) ) , STD_ULOGIC_VECTOR'("000000001")); +MQQ26:IU1_FIRST_HIT_ENTRY_PT(9) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) + ) , STD_ULOGIC_VECTOR'("00000001")); +MQQ27:IU1_FIRST_HIT_ENTRY_PT(10) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) ) , STD_ULOGIC_VECTOR'("0000001")); +MQQ28:IU1_FIRST_HIT_ENTRY_PT(11) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) + ) , STD_ULOGIC_VECTOR'("000001")); +MQQ29:IU1_FIRST_HIT_ENTRY_PT(12) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) ) , STD_ULOGIC_VECTOR'("00001")); +MQQ30:IU1_FIRST_HIT_ENTRY_PT(13) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) + ) , STD_ULOGIC_VECTOR'("0001")); +MQQ31:IU1_FIRST_HIT_ENTRY_PT(14) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) ) , STD_ULOGIC_VECTOR'("001")); +MQQ32:IU1_FIRST_HIT_ENTRY_PT(15) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) + ) , STD_ULOGIC_VECTOR'("01")); +-- Table IU1_FIRST_HIT_ENTRY Signal Assignments for Outputs +MQQ33:IU1_FIRST_HIT_ENTRY(0) <= + (IU1_FIRST_HIT_ENTRY_PT(1) OR IU1_FIRST_HIT_ENTRY_PT(2) + OR IU1_FIRST_HIT_ENTRY_PT(3) OR IU1_FIRST_HIT_ENTRY_PT(4) + OR IU1_FIRST_HIT_ENTRY_PT(5) OR IU1_FIRST_HIT_ENTRY_PT(6) + OR IU1_FIRST_HIT_ENTRY_PT(7) OR IU1_FIRST_HIT_ENTRY_PT(8) + ); +MQQ34:IU1_FIRST_HIT_ENTRY(1) <= + (IU1_FIRST_HIT_ENTRY_PT(1) OR IU1_FIRST_HIT_ENTRY_PT(2) + OR IU1_FIRST_HIT_ENTRY_PT(3) OR IU1_FIRST_HIT_ENTRY_PT(4) + OR IU1_FIRST_HIT_ENTRY_PT(9) OR IU1_FIRST_HIT_ENTRY_PT(10) + OR IU1_FIRST_HIT_ENTRY_PT(11) OR IU1_FIRST_HIT_ENTRY_PT(12) + ); +MQQ35:IU1_FIRST_HIT_ENTRY(2) <= + (IU1_FIRST_HIT_ENTRY_PT(1) OR IU1_FIRST_HIT_ENTRY_PT(2) + OR IU1_FIRST_HIT_ENTRY_PT(5) OR IU1_FIRST_HIT_ENTRY_PT(6) + OR IU1_FIRST_HIT_ENTRY_PT(9) OR IU1_FIRST_HIT_ENTRY_PT(10) + OR IU1_FIRST_HIT_ENTRY_PT(13) OR IU1_FIRST_HIT_ENTRY_PT(14) + ); +MQQ36:IU1_FIRST_HIT_ENTRY(3) <= + (IU1_FIRST_HIT_ENTRY_PT(1) OR IU1_FIRST_HIT_ENTRY_PT(3) + OR IU1_FIRST_HIT_ENTRY_PT(5) OR IU1_FIRST_HIT_ENTRY_PT(7) + OR IU1_FIRST_HIT_ENTRY_PT(9) OR IU1_FIRST_HIT_ENTRY_PT(11) + OR IU1_FIRST_HIT_ENTRY_PT(13) OR IU1_FIRST_HIT_ENTRY_PT(15) + ); + +iu2_first_hit_entry_pt_d <= iu1_first_hit_entry_pt; +iu2_first_hit_entry(0) <= + (iu2_first_hit_entry_pt_q(1) or iu2_first_hit_entry_pt_q(2) + or iu2_first_hit_entry_pt_q(3) or iu2_first_hit_entry_pt_q(4) + or iu2_first_hit_entry_pt_q(5) or iu2_first_hit_entry_pt_q(6) + or iu2_first_hit_entry_pt_q(7) or iu2_first_hit_entry_pt_q(8)); +iu2_first_hit_entry(1) <= + (iu2_first_hit_entry_pt_q(1) or iu2_first_hit_entry_pt_q(2) + or iu2_first_hit_entry_pt_q(3) or iu2_first_hit_entry_pt_q(4) + or iu2_first_hit_entry_pt_q(9) or iu2_first_hit_entry_pt_q(10) + or iu2_first_hit_entry_pt_q(11) or iu2_first_hit_entry_pt_q(12)); +iu2_first_hit_entry(2) <= + (iu2_first_hit_entry_pt_q(1) or iu2_first_hit_entry_pt_q(2) + or iu2_first_hit_entry_pt_q(5) or iu2_first_hit_entry_pt_q(6) + or iu2_first_hit_entry_pt_q(9) or iu2_first_hit_entry_pt_q(10) + or iu2_first_hit_entry_pt_q(13) or iu2_first_hit_entry_pt_q(14)); +iu2_first_hit_entry(3) <= + (iu2_first_hit_entry_pt_q(1) or iu2_first_hit_entry_pt_q(3) + or iu2_first_hit_entry_pt_q(5) or iu2_first_hit_entry_pt_q(7) + or iu2_first_hit_entry_pt_q(9) or iu2_first_hit_entry_pt_q(11) + or iu2_first_hit_entry_pt_q(13) or iu2_first_hit_entry_pt_q(15)); +iu2_cam_cmp_data_d <= cam_cmp_data; +iu2_array_cmp_data_d <= array_cmp_data; +-- cam translate, search applied in iu0 or ex1 -> cam_cmp_data in iu1 or ex2 +-- cam read applied in ex2 -> rd_cam_data in ex3 +iu2_miss_d(0) <= ( or_reduce(iu1_valid_q and not(iu_ierat_iu1_flush) and not(xu_iu_flush) and not(iu2_n_flush_req_q)) and + not iu1_flush_enab_q and not ccr2_frat_paranoia_q(9) ); +iu2_miss_d(1) <= not cam_hit; +iu2_miss_sig <= iu2_miss_q(0) and iu2_miss_q(1); +iu2_multihit_d(0) <= ( cam_hit and iu1_multihit and + or_reduce(iu1_valid_q and not(iu_ierat_iu1_flush) and not(xu_iu_flush) and not(iu2_n_flush_req_q)) and + not iu1_flush_enab_q and not ccr2_frat_paranoia_q(9) ); +iu2_multihit_d(1) <= iu1_multihit; +iu2_multihit_sig <= iu2_multihit_q(0) and iu2_multihit_q(1); +iu2_parerr_d(0) <= ( cam_hit and iu1_multihit_b and + or_reduce(iu1_valid_q and not(iu_ierat_iu1_flush) and not(xu_iu_flush) and not(iu2_n_flush_req_q)) and + not iu1_flush_enab_q and not ccr2_frat_paranoia_q(9) ); +iu2_parerr_d(1) <= ( cam_hit and iu1_multihit_b and + or_reduce(iu1_valid_q and not(iu_ierat_iu1_flush) and not(xu_iu_flush) and not(iu2_n_flush_req_q)) and + not iu1_flush_enab_q and not ccr2_frat_paranoia_q(9) ); +iu2_parerr_sig <= (iu2_parerr_q(0) and iu2_cmp_data_parerr_epn) or + (iu2_parerr_q(1) and iu2_cmp_data_parerr_rpn); +-- 16x143 version, 42b RA +-- wr_array_data +-- 0:29 - RPN +-- 30:31 - R,C +-- 32:33 - WLC +-- 34 - ResvAttr +-- 35 - VF +-- 36:39 - U0-U3 +-- 40:44 - WIMGE +-- 45:46 - UX,SX +-- 47:48 - UW,SW +-- 49:50 - UR,SR +-- 51:60 - CAM parity +-- 61:67 - Array parity +-- mmucr1_q: 0-IRRE, 1-REE, 2-CEE, 3-csync, 4-isync, 5:6-IPEI, 7:8-ICTID/ITTID +-- state: 0:pr 1:hs 2:ds 3:cm +iu2_isi_d(0) <= ( or_reduce(iu1_valid_q and not(iu_ierat_iu1_flush) and not(xu_iu_flush) and not(iu2_n_flush_req_q)) + and not iu1_flush_enab_q and iu1_state_q(0) and not ccr2_frat_paranoia_q(9) ); +iu2_isi_d(2) <= ( or_reduce(iu1_valid_q and not(iu_ierat_iu1_flush) and not(xu_iu_flush) and not(iu2_n_flush_req_q)) + and not iu1_flush_enab_q and not iu1_state_q(0) and not ccr2_frat_paranoia_q(9) ); +iu2_isi_d(4) <= ( or_reduce(iu1_valid_q and not(iu_ierat_iu1_flush) and not(xu_iu_flush) and not(iu2_n_flush_req_q)) + and not iu1_flush_enab_q and mmucr1_q(1) and not ccr2_frat_paranoia_q(9) ); +iu2_isi_d(1) <= not array_cmp_data(45); +iu2_isi_d(3) <= not array_cmp_data(46); +iu2_isi_d(5) <= not array_cmp_data(30); +iu2_isi_sig <= (iu2_isi_q(0) and iu2_isi_q(1)) or + (iu2_isi_q(2) and iu2_isi_q(3)) or + (iu2_isi_q(4) and iu2_isi_q(5)); +ex3_eratsx_data_d <= iu1_multihit & cam_hit & iu1_first_hit_entry; +ex3_parerr_d(0 TO thdid_width-1) <= ex2_valid_q and not(xu_ex2_flush); +ex3_parerr_d(thdid_width) <= ( cam_hit and iu1_multihit_b and ex2_ttype_q(2) and ex2_tlbsel_q(0) and not(ex2_tlbsel_q(1)) + and not(ex3_ieratwe or ex4_ieratwe or ex5_ieratwe or ex6_ieratwe or ex7_ieratwe) + and or_reduce(ex2_valid_q and not(xu_ex2_flush)) ); +ex3_parerr_enab <= ex3_parerr_q(thdid_width) and iu2_cmp_data_parerr_epn; +ex4_rd_array_data_d <= rd_array_data; +ex4_rd_cam_data_d <= rd_cam_data; +ex4_parerr_d(0 TO thdid_width-1) <= ex3_valid_q and not(xu_ex3_flush); +ex4_parerr_d(thdid_width) <= (ex3_ttype_q(0) and not ex3_ws_q(0) and not ex3_ws_q(1) and ex3_tlbsel_q(0) and not ex3_tlbsel_q(1) + and not(ex4_ieratwe or ex5_ieratwe or ex6_ieratwe)); +ex4_parerr_d(thdid_width+1) <= (ex3_ttype_q(0) and xor_reduce(ex3_ws_q) and ex3_tlbsel_q(0) and not ex3_tlbsel_q(1) + and not(ex4_ieratwe or ex5_ieratwe or ex6_ieratwe)); +ex4_parerr_enab <= (ex4_parerr_q(thdid_width) and ex4_rd_data_parerr_epn) or + (ex4_parerr_q(thdid_width+1) and ex4_rd_data_parerr_rpn); +ex4_ieen_d(0 TO thdid_width-1) <= (ex3_parerr_q(0 to thdid_width-1) and (0 to thdid_width-1 => ex3_parerr_enab) and not(xu_ex3_flush)) + when (ex3_ttype_q(2)='1' ) + else (iu2_valid_q and not iu2_n_flush_req_q) + when (iu2_multihit_sig='1' or iu2_parerr_sig='1') + else (others => '0'); +ex4_ieen_d(thdid_width TO thdid_width+num_entry_log2-1) <= ex3_eratsx_data_q(2 to 2+num_entry_log2-1) + when (ex3_ttype_q(2)='1') + else ex3_ra_entry_q + when (ex3_ttype_q(0)='1' and ex3_ws_q="00" and ex3_tlbsel_q=TlbSel_IErat) + else ex3_ra_entry_q + when (ex3_ttype_q(0)='1' and (ex3_ws_q="01" or ex3_ws_q="10") and ex3_tlbsel_q=TlbSel_IErat) + else ex3_eratsx_data_q(2 to 2+num_entry_log2-1) + when (iu2_multihit_sig='1' or iu2_parerr_sig='1') + else (others => '0'); +ex5_ieen_d(0 TO thdid_width-1) <= (ex4_ieen_q(0 to thdid_width-1) and not(xu_ex4_flush)) or + (ex4_parerr_q(0 to thdid_width-1) and (0 to thdid_width-1 => ex4_parerr_enab) and not(xu_ex4_flush)); +ex5_ieen_d(thdid_width TO thdid_width+num_entry_log2-1) <= ex4_ieen_q(thdid_width to thdid_width+num_entry_log2-1); +ex6_ieen_d <= or_reduce(ex5_ieen_q(0 to thdid_width-1)) & + ex5_ieen_q(thdid_width to thdid_width+num_entry_log2-1); +-- This function is controlled by XUCR4.MMU_MCHK and CCR2.NOTLB bits. +mchk_flash_inv_d(0) <= or_reduce(iu2_valid_q and not(xu_iu_flush) and not(iu2_n_flush_req_q)); +mchk_flash_inv_d(1) <= iu2_parerr_sig; +mchk_flash_inv_d(2) <= iu2_multihit_sig; +mchk_flash_inv_d(3) <= mchk_flash_inv_enab; +mchk_flash_inv_enab <= mchk_flash_inv_q(0) and (mchk_flash_inv_q(1) or mchk_flash_inv_q(2)) and not(ccr2_notlb_q) and not(xucr4_mmu_mchk_q); +iu1_flush_enab_d <= '1' when (tlb_rel_val_q(0 to 3)/="0000" and tlb_rel_val_q(4)='1') + else '1' when snoop_val_q(0 to 1)="11" + else '1' when (ex1_valid_q/="0000" and ex1_ttype_q(2)='1' and ex1_tlbsel_q=TlbSel_IErat) + else '1' when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_ws_q="00" and ex6_tlbsel_q=TlbSel_IErat) + else '1' when ((ex6_valid_q/="0000" and ex6_ttype_q(4 to 5)/="00") or mchk_flash_inv_enab='1' or mchk_flash_inv_q(3)='1') + else '0'; +iu2_n_flush_req_d <= (iu1_valid_q and not(iu_ierat_iu1_flush) and not(xu_iu_flush) and not(iu2_n_flush_req_q)) + when iu1_flush_enab_q='1' + else (iu1_valid_q and not(iu_ierat_iu1_flush) and not(xu_iu_flush) and not(iu2_n_flush_req_q) and not(tlb_miss_q)) + when (cam_hit='0' and ccr2_notlb_q=MMU_Mode_Value and ccr2_frat_paranoia_q(9)='0') + else (others => '0'); +-- adding frat paranoia for ra=ea +hold_req_d(0) <= '1' when por_hold_req(0)='1' + else '0' when ccr2_frat_paranoia_q(9)='1' + else '0' when (xu_iu_flush(0)='1' or iu_ierat_iu1_flush(0)='1') + else '0' when (tlb_rel_val_q(0)='1' and ccr2_notlb_q=MMU_Mode_Value) + else '1' when (cam_hit='0' and iu1_valid_q(0)='1' + and iu_ierat_iu1_flush(0)='0' and xu_iu_flush(0)='0' and iu1_flush_enab_q='0' + and iu2_n_flush_req_q(0)='0' and tlb_miss_q(0)='0' and ccr2_notlb_q=MMU_Mode_Value) + else '1' when (iu1_valid_q(0)='1' and iu_ierat_iu1_flush(0)='0' and xu_iu_flush(0)='0' and iu1_flush_enab_q='0' + and iu2_n_flush_req_q(0)='0' and tlb_miss_q(0)='1' and ccr2_notlb_q=MMU_Mode_Value) + else hold_req_q(0); +hold_req_d(1) <= '1' when por_hold_req(1)='1' + else '0' when ccr2_frat_paranoia_q(9)='1' + else '0' when (xu_iu_flush(1)='1' or iu_ierat_iu1_flush(1)='1') + else '0' when (tlb_rel_val_q(1)='1' and ccr2_notlb_q=MMU_Mode_Value) + else '1' when (cam_hit='0' and iu1_valid_q(1)='1' + and iu_ierat_iu1_flush(1)='0' and xu_iu_flush(1)='0' and iu1_flush_enab_q='0' + and iu2_n_flush_req_q(1)='0' and tlb_miss_q(1)='0' and ccr2_notlb_q=MMU_Mode_Value) + else '1' when (iu1_valid_q(1)='1' and iu_ierat_iu1_flush(1)='0' and xu_iu_flush(1)='0' and iu1_flush_enab_q='0' + and iu2_n_flush_req_q(1)='0' and tlb_miss_q(1)='1' and ccr2_notlb_q=MMU_Mode_Value) + else hold_req_q(1); +hold_req_d(2) <= '1' when por_hold_req(2)='1' + else '0' when ccr2_frat_paranoia_q(9)='1' + else '0' when (xu_iu_flush(2)='1' or iu_ierat_iu1_flush(2)='1') + else '0' when (tlb_rel_val_q(2)='1' and ccr2_notlb_q=MMU_Mode_Value) + else '1' when (cam_hit='0' and iu1_valid_q(2)='1' + and iu_ierat_iu1_flush(2)='0' and xu_iu_flush(2)='0' and iu1_flush_enab_q='0' + and iu2_n_flush_req_q(2)='0' and tlb_miss_q(2)='0' and ccr2_notlb_q=MMU_Mode_Value) + else '1' when (iu1_valid_q(2)='1' and iu_ierat_iu1_flush(2)='0' and xu_iu_flush(2)='0' and iu1_flush_enab_q='0' + and iu2_n_flush_req_q(2)='0' and tlb_miss_q(2)='1' and ccr2_notlb_q=MMU_Mode_Value) + else hold_req_q(2); +hold_req_d(3) <= '1' when por_hold_req(3)='1' + else '0' when ccr2_frat_paranoia_q(9)='1' + else '0' when (xu_iu_flush(3)='1' or iu_ierat_iu1_flush(3)='1') + else '0' when (tlb_rel_val_q(3)='1' and ccr2_notlb_q=MMU_Mode_Value) + else '1' when (cam_hit='0' and iu1_valid_q(3)='1' + and iu_ierat_iu1_flush(3)='0' and xu_iu_flush(3)='0' and iu1_flush_enab_q='0' + and iu2_n_flush_req_q(3)='0' and tlb_miss_q(3)='0' and ccr2_notlb_q=MMU_Mode_Value) + else '1' when (iu1_valid_q(3)='1' and iu_ierat_iu1_flush(3)='0' and xu_iu_flush(3)='0' and iu1_flush_enab_q='0' + and iu2_n_flush_req_q(3)='0' and tlb_miss_q(3)='1' and ccr2_notlb_q=MMU_Mode_Value) + else hold_req_q(3); +-- latch tlb missed response +-- adding frat paranoia for ra=ea +tlb_miss_d(0) <= '0' when (ccr2_notlb_q/=MMU_Mode_Value or por_seq_q/=PorSeq_Idle or ccr2_frat_paranoia_q(9)='1') + else '0' when xu_iu_flush(0)='1' + else hold_req_q(0) when (tlb_miss_q(0)='0' and tlb_rel_val_q(0)='1' and tlb_rel_val_q(4)='0') + else tlb_miss_q(0); +tlb_miss_d(1) <= '0' when (ccr2_notlb_q/=MMU_Mode_Value or por_seq_q/=PorSeq_Idle or ccr2_frat_paranoia_q(9)='1') + else '0' when xu_iu_flush(1)='1' + else hold_req_q(1) when (tlb_miss_q(1)='0' and tlb_rel_val_q(1)='1' and tlb_rel_val_q(4)='0') + else tlb_miss_q(1); +tlb_miss_d(2) <= '0' when (ccr2_notlb_q/=MMU_Mode_Value or por_seq_q/=PorSeq_Idle or ccr2_frat_paranoia_q(9)='1') + else '0' when xu_iu_flush(2)='1' + else hold_req_q(2) when (tlb_miss_q(2)='0' and tlb_rel_val_q(2)='1' and tlb_rel_val_q(4)='0') + else tlb_miss_q(2); +tlb_miss_d(3) <= '0' when (ccr2_notlb_q/=MMU_Mode_Value or por_seq_q/=PorSeq_Idle or ccr2_frat_paranoia_q(9)='1') + else '0' when xu_iu_flush(3)='1' + else hold_req_q(3) when (tlb_miss_q(3)='0' and tlb_rel_val_q(3)='1' and tlb_rel_val_q(4)='0') + else tlb_miss_q(3); +-- latch tlb request is in progress for act pin on cam +tlb_req_inprogress_d(0) <= '0' when (ccr2_frat_paranoia_q(9)='1' or por_hold_req(0)='1' or ccr2_notlb_q/=MMU_Mode_Value or tlb_rel_val_q(0)='1') + else '0' when (xu_iu_flush(0)='0' and iu2_valid_q(0)='1' and hold_req_q(0)='0') + else '1' when (iu2_tlbreq_q='1' and iu2_valid_q(0)='1' and ccr2_notlb_q=MMU_Mode_Value) + else tlb_req_inprogress_q(0); +tlb_req_inprogress_d(1) <= '0' when (ccr2_frat_paranoia_q(9)='1' or por_hold_req(1)='1' or ccr2_notlb_q/=MMU_Mode_Value or tlb_rel_val_q(1)='1') + else '0' when (xu_iu_flush(1)='0' and iu2_valid_q(1)='1' and hold_req_q(1)='0') + else '1' when (iu2_tlbreq_q='1' and iu2_valid_q(1)='1' and ccr2_notlb_q=MMU_Mode_Value) + else tlb_req_inprogress_q(1); +tlb_req_inprogress_d(2) <= '0' when (ccr2_frat_paranoia_q(9)='1' or por_hold_req(2)='1' or ccr2_notlb_q/=MMU_Mode_Value or tlb_rel_val_q(2)='1') + else '0' when (xu_iu_flush(2)='0' and iu2_valid_q(2)='1' and hold_req_q(2)='0') + else '1' when (iu2_tlbreq_q='1' and iu2_valid_q(2)='1' and ccr2_notlb_q=MMU_Mode_Value) + else tlb_req_inprogress_q(2); +tlb_req_inprogress_d(3) <= '0' when (ccr2_frat_paranoia_q(9)='1' or por_hold_req(3)='1' or ccr2_notlb_q/=MMU_Mode_Value or tlb_rel_val_q(3)='1') + else '0' when (xu_iu_flush(3)='0' and iu2_valid_q(3)='1' and hold_req_q(3)='0') + else '1' when (iu2_tlbreq_q='1' and iu2_valid_q(3)='1' and ccr2_notlb_q=MMU_Mode_Value) + else tlb_req_inprogress_q(3); +iu2_tlbreq_d <= '1' when (cam_hit='0' and iu1_flush_enab_q='0' and ccr2_notlb_q=MMU_Mode_Value and ccr2_frat_paranoia_q(9)='0' and + (iu1_valid_q and not(iu_ierat_iu1_flush) and not(xu_iu_flush) and not(iu2_n_flush_req_q) and not(tlb_miss_q) and not(hold_req_q))/="0000") + else '0'; +snoop_val_d(0) <= mm_iu_ierat_snoop_val when snoop_val_q(0)='0' + else '0' when (tlb_rel_val_q(4)='0' and snoop_val_q(1)='1') + else snoop_val_q(0); +snoop_val_d(1) <= not iu_ierat_ium1_back_inv; +snoop_val_d(2) <= '0' when (tlb_rel_val_q(4)='1' or snoop_val_q(1)='0') + else snoop_val_q(0); +snoop_attr_d <= mm_iu_ierat_snoop_attr when snoop_val_q(0)='0' + else snoop_attr_q; +snoop_addr_d <= mm_iu_ierat_snoop_vpn when snoop_val_q(0)='0' + else snoop_addr_q; +iu_mm_ierat_snoop_ack <= snoop_val_q(2); +gen64_holdreg: if rs_data_width = 64 generate +rpn_holdreg0_d(0 TO 19) <= ex6_data_in_q(0 to 19) when (ex6_valid_q(0)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='1') + else ex6_data_in_q(32 to 51) when (ex6_valid_q(0)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='0') + else rpn_holdreg0_q(0 to 19); +rpn_holdreg0_d(20 TO 31) <= ex6_data_in_q(20 to 31) when (ex6_valid_q(0)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='1') + else ex6_data_in_q(52 to 63) when (ex6_valid_q(0)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='0') + else rpn_holdreg0_q(20 to 31); +rpn_holdreg0_d(32 TO 51) <= ex6_data_in_q(32 to 51) when (ex6_valid_q(0)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='1') + else ex6_data_in_q(32 to 51) when (ex6_valid_q(0)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='0') + else rpn_holdreg0_q(32 to 51); +rpn_holdreg0_d(52 TO 63) <= ex6_data_in_q(52 to 63) when (ex6_valid_q(0)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='1') + else ex6_data_in_q(52 to 63) when (ex6_valid_q(0)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='0') + else rpn_holdreg0_q(52 to 63); +rpn_holdreg1_d(0 TO 19) <= ex6_data_in_q(0 to 19) when (ex6_valid_q(1)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='1') + else ex6_data_in_q(32 to 51) when (ex6_valid_q(1)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='0') + else rpn_holdreg1_q(0 to 19); +rpn_holdreg1_d(20 TO 31) <= ex6_data_in_q(20 to 31) when (ex6_valid_q(1)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='1') + else ex6_data_in_q(52 to 63) when (ex6_valid_q(1)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='0') + else rpn_holdreg1_q(20 to 31); +rpn_holdreg1_d(32 TO 51) <= ex6_data_in_q(32 to 51) when (ex6_valid_q(1)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='1') + else ex6_data_in_q(32 to 51) when (ex6_valid_q(1)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='0') + else rpn_holdreg1_q(32 to 51); +rpn_holdreg1_d(52 TO 63) <= ex6_data_in_q(52 to 63) when (ex6_valid_q(1)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='1') + else ex6_data_in_q(52 to 63) when (ex6_valid_q(1)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='0') + else rpn_holdreg1_q(52 to 63); +rpn_holdreg2_d(0 TO 19) <= ex6_data_in_q(0 to 19) when (ex6_valid_q(2)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='1') + else ex6_data_in_q(32 to 51) when (ex6_valid_q(2)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='0') + else rpn_holdreg2_q(0 to 19); +rpn_holdreg2_d(20 TO 31) <= ex6_data_in_q(20 to 31) when (ex6_valid_q(2)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='1') + else ex6_data_in_q(52 to 63) when (ex6_valid_q(2)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='0') + else rpn_holdreg2_q(20 to 31); +rpn_holdreg2_d(32 TO 51) <= ex6_data_in_q(32 to 51) when (ex6_valid_q(2)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='1') + else ex6_data_in_q(32 to 51) when (ex6_valid_q(2)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='0') + else rpn_holdreg2_q(32 to 51); +rpn_holdreg2_d(52 TO 63) <= ex6_data_in_q(52 to 63) when (ex6_valid_q(2)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='1') + else ex6_data_in_q(52 to 63) when (ex6_valid_q(2)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='0') + else rpn_holdreg2_q(52 to 63); +rpn_holdreg3_d(0 TO 19) <= ex6_data_in_q(0 to 19) when (ex6_valid_q(3)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='1') + else ex6_data_in_q(32 to 51) when (ex6_valid_q(3)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='0') + else rpn_holdreg3_q(0 to 19); +rpn_holdreg3_d(20 TO 31) <= ex6_data_in_q(20 to 31) when (ex6_valid_q(3)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='1') + else ex6_data_in_q(52 to 63) when (ex6_valid_q(3)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='0') + else rpn_holdreg3_q(20 to 31); +rpn_holdreg3_d(32 TO 51) <= ex6_data_in_q(32 to 51) when (ex6_valid_q(3)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='1') + else ex6_data_in_q(32 to 51) when (ex6_valid_q(3)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='0') + else rpn_holdreg3_q(32 to 51); +rpn_holdreg3_d(52 TO 63) <= ex6_data_in_q(52 to 63) when (ex6_valid_q(3)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='1') + else ex6_data_in_q(52 to 63) when (ex6_valid_q(3)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_IErat and ex6_state_q(3)='0') + else rpn_holdreg3_q(52 to 63); +end generate gen64_holdreg; +gen32_holdreg: if rs_data_width = 32 generate +rpn_holdreg0_d(32 TO 51) <= ex6_data_in_q(32 to 51) when (ex6_valid_q(0)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat) + else rpn_holdreg0_q(32 to 51); +rpn_holdreg0_d(20 TO 31) <= ex6_data_in_q(52 to 63) when (ex6_valid_q(0)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat) + else rpn_holdreg0_q(20 to 31); +rpn_holdreg0_d(52 TO 63) <= ex6_data_in_q(52 to 63) when (ex6_valid_q(0)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_IErat) + else rpn_holdreg0_q(52 to 63); +rpn_holdreg0_d(0 TO 19) <= ex6_data_in_q(32 to 51) when (ex6_valid_q(0)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_IErat) + else rpn_holdreg0_q(0 to 19); +rpn_holdreg1_d(32 TO 51) <= ex6_data_in_q(32 to 51) when (ex6_valid_q(1)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat) + else rpn_holdreg1_q(32 to 51); +rpn_holdreg1_d(20 TO 31) <= ex6_data_in_q(52 to 63) when (ex6_valid_q(1)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat) + else rpn_holdreg1_q(20 to 31); +rpn_holdreg1_d(52 TO 63) <= ex6_data_in_q(52 to 63) when (ex6_valid_q(1)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_IErat) + else rpn_holdreg1_q(52 to 63); +rpn_holdreg1_d(0 TO 19) <= ex6_data_in_q(32 to 51) when (ex6_valid_q(1)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_IErat) + else rpn_holdreg1_q(0 to 19); +rpn_holdreg2_d(32 TO 51) <= ex6_data_in_q(32 to 51) when (ex6_valid_q(2)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat) + else rpn_holdreg2_q(32 to 51); +rpn_holdreg2_d(20 TO 31) <= ex6_data_in_q(52 to 63) when (ex6_valid_q(2)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat) + else rpn_holdreg2_q(20 to 31); +rpn_holdreg2_d(52 TO 63) <= ex6_data_in_q(52 to 63) when (ex6_valid_q(2)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_IErat) + else rpn_holdreg2_q(52 to 63); +rpn_holdreg2_d(0 TO 19) <= ex6_data_in_q(32 to 51) when (ex6_valid_q(2)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_IErat) + else rpn_holdreg2_q(0 to 19); +rpn_holdreg3_d(32 TO 51) <= ex6_data_in_q(32 to 51) when (ex6_valid_q(3)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat) + else rpn_holdreg3_q(32 to 51); +rpn_holdreg3_d(20 TO 31) <= ex6_data_in_q(52 to 63) when (ex6_valid_q(3)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_IErat) + else rpn_holdreg3_q(20 to 31); +rpn_holdreg3_d(52 TO 63) <= ex6_data_in_q(52 to 63) when (ex6_valid_q(3)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_IErat) + else rpn_holdreg3_q(52 to 63); +rpn_holdreg3_d(0 TO 19) <= ex6_data_in_q(32 to 51) when (ex6_valid_q(3)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_IErat) + else rpn_holdreg3_q(0 to 19); +end generate gen32_holdreg; +ex6_ieratwe_ws3 <= or_reduce(ex6_valid_q) and ex6_ttype_q(1) and Eq(ex6_ws_q,"11") and Eq(ex6_tlbsel_q,TlbSel_IErat); +watermark_d <= ex6_data_in_q(64-watermark_width to 63) when ex6_ieratwe_ws3='1' + else watermark_q; +-- mmucr1_q: 0-IRRE, 1-REE, 2-CEE, 3-csync, 4-isync, 5:6-IPEI, 7:8-ICTID/ITTID +-- entry pointer for round-robin mode +eptr_d <= (others => '0') when (ex6_ieratwe_ws3='1' and mmucr1_q(0)='1') + else (others => '0') when (eptr_q="1111" or eptr_q=watermark_q) and + ( (ex6_valid_q /= "0000" and ex6_ttype_q(1)='1' and ex6_ws_q="00" and + ex6_tlbsel_q=TlbSel_IErat and mmucr1_q(0)='1') or + (tlb_rel_val_q(0 to 3)/="0000" and tlb_rel_val_q(4)='1' and + tlb_rel_data_q(eratpos_wren)='1' and mmucr1_q(0)='1') ) + else eptr_p1 when ( (ex6_valid_q /= "0000" and ex6_ttype_q(1)='1' and ex6_ws_q="00" and + ex6_tlbsel_q=TlbSel_IErat and mmucr1_q(0)='1') or + (tlb_rel_val_q(0 to 3)/="0000" and tlb_rel_val_q(4)='1' and + tlb_rel_data_q(eratpos_wren)='1' and mmucr1_q(0)='1') ) + else eptr_q; +eptr_p1 <= "0001" when eptr_q="0000" + else "0010" when eptr_q="0001" + else "0011" when eptr_q="0010" + else "0100" when eptr_q="0011" + else "0101" when eptr_q="0100" + else "0110" when eptr_q="0101" + else "0111" when eptr_q="0110" + else "1000" when eptr_q="0111" + else "1001" when eptr_q="1000" + else "1010" when eptr_q="1001" + else "1011" when eptr_q="1010" + else "1100" when eptr_q="1011" + else "1101" when eptr_q="1100" + else "1110" when eptr_q="1101" + else "1111" when eptr_q="1110" + else "0000"; +lru_way_is_written <= Eq(lru_way_encode, ex6_ra_entry_q); +lru_way_is_hit_entry <= Eq(lru_way_encode, iu1_first_hit_entry); +-- lru_update_event +-- 0: tlb reload +-- 1: invalidate snoop +-- 2: csync or isync enabled +-- 3: eratwe WS=0 +-- 4: fetch hit +-- 5: iu2 cam write type events +-- 6: iu2 cam invalidate type events +-- 7: iu2 cam translation type events +-- 8: iu2, superset of non-translation events +lru_update_event_d(0) <= ( tlb_rel_data_q(eratpos_wren) and or_reduce(tlb_rel_val_q(0 to 3)) and tlb_rel_val_q(4) ); +lru_update_event_d(1) <= ( snoop_val_q(0) and snoop_val_q(1) ); +lru_update_event_d(2) <= ( or_reduce(ex6_valid_q) and (ex6_ttype_q(4) or ex6_ttype_q(5)) ); +lru_update_event_d(3) <= ( or_reduce(ex6_valid_q) and ex6_ttype_q(1) and not ex6_ws_q(0) and not ex6_ws_q(1) + and ex6_tlbsel_q(0) and not ex6_tlbsel_q(1) and lru_way_is_written ); +lru_update_event_d(4) <= ( or_reduce(iu1_valid_q and not(iu_ierat_iu1_flush) and not(xu_iu_flush) and not(iu2_n_flush_req_q)) + and not iu1_flush_enab_q and cam_hit and lru_way_is_hit_entry ); +lru_update_event_d(5) <= lru_update_event_q(0) or lru_update_event_q(3); +lru_update_event_d(6) <= lru_update_event_q(1) or lru_update_event_q(2); +lru_update_event_d(7) <= ( or_reduce(iu1_valid_q and not(iu_ierat_iu1_flush) and not(xu_iu_flush) and not(iu2_n_flush_req_q)) + and not iu1_flush_enab_q and cam_hit and lru_way_is_hit_entry ); +lru_update_event_d(8) <= lru_update_event_q(0) or lru_update_event_q(1) or lru_update_event_q(2) or lru_update_event_q(3); +-- LRU next state.. update bits for which override is zero (Op=0) +-- effective LRU is what is used to choose entry to update +-- lru new value is valid 2 clocks after reload, invalidate, eratwe, or fetch hit +lru_d(1) <= '0' when ((ex6_ieratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(1)='1' and mmucr1_q(0)='0' and lru_op_vec(1)='0' and ccr2_frat_paranoia_q(9)='0' and + (lru_update_event_q(8)='1' or (lru_update_event_q(4) and not(iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig))='1') + else '1' when lru_set_vec(1)='1' and mmucr1_q(0)='0' and lru_op_vec(1)='0' and ccr2_frat_paranoia_q(9)='0' and + (lru_update_event_q(8)='1' or (lru_update_event_q(4) and not(iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig))='1') + else lru_q(1); +lru_eff(1) <= (lru_vp_vec(1) and lru_op_vec(1)) or (lru_q(1) and not lru_op_vec(1)); +lru_d(2) <= '0' when ((ex6_ieratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(2)='1' and mmucr1_q(0)='0' and lru_op_vec(2)='0' and ccr2_frat_paranoia_q(9)='0' and + (lru_update_event_q(8)='1' or (lru_update_event_q(4) and not(iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig))='1') + else '1' when lru_set_vec(2)='1' and mmucr1_q(0)='0' and lru_op_vec(2)='0' and ccr2_frat_paranoia_q(9)='0' and + (lru_update_event_q(8)='1' or (lru_update_event_q(4) and not(iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig))='1') + else lru_q(2); +lru_eff(2) <= (lru_vp_vec(2) and lru_op_vec(2)) or (lru_q(2) and not lru_op_vec(2)); +lru_d(3) <= '0' when ((ex6_ieratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(3)='1' and mmucr1_q(0)='0' and lru_op_vec(3)='0' and ccr2_frat_paranoia_q(9)='0' and + (lru_update_event_q(8)='1' or (lru_update_event_q(4) and not(iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig))='1') + else '1' when lru_set_vec(3)='1' and mmucr1_q(0)='0' and lru_op_vec(3)='0' and ccr2_frat_paranoia_q(9)='0' and + (lru_update_event_q(8)='1' or (lru_update_event_q(4) and not(iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig))='1') + else lru_q(3); +lru_eff(3) <= (lru_vp_vec(3) and lru_op_vec(3)) or (lru_q(3) and not lru_op_vec(3)); +lru_d(4) <= '0' when ((ex6_ieratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(4)='1' and mmucr1_q(0)='0' and lru_op_vec(4)='0' and ccr2_frat_paranoia_q(9)='0' and + (lru_update_event_q(8)='1' or (lru_update_event_q(4) and not(iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig))='1') + else '1' when lru_set_vec(4)='1' and mmucr1_q(0)='0' and lru_op_vec(4)='0' and ccr2_frat_paranoia_q(9)='0' and + (lru_update_event_q(8)='1' or (lru_update_event_q(4) and not(iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig))='1') + else lru_q(4); +lru_eff(4) <= (lru_vp_vec(4) and lru_op_vec(4)) or (lru_q(4) and not lru_op_vec(4)); +lru_d(5) <= '0' when ((ex6_ieratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(5)='1' and mmucr1_q(0)='0' and lru_op_vec(5)='0' and ccr2_frat_paranoia_q(9)='0' and + (lru_update_event_q(8)='1' or (lru_update_event_q(4) and not(iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig))='1') + else '1' when lru_set_vec(5)='1' and mmucr1_q(0)='0' and lru_op_vec(5)='0' and ccr2_frat_paranoia_q(9)='0' and + (lru_update_event_q(8)='1' or (lru_update_event_q(4) and not(iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig))='1') + else lru_q(5); +lru_eff(5) <= (lru_vp_vec(5) and lru_op_vec(5)) or (lru_q(5) and not lru_op_vec(5)); +lru_d(6) <= '0' when ((ex6_ieratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(6)='1' and mmucr1_q(0)='0' and lru_op_vec(6)='0' and ccr2_frat_paranoia_q(9)='0' and + (lru_update_event_q(8)='1' or (lru_update_event_q(4) and not(iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig))='1') + else '1' when lru_set_vec(6)='1' and mmucr1_q(0)='0' and lru_op_vec(6)='0' and ccr2_frat_paranoia_q(9)='0' and + (lru_update_event_q(8)='1' or (lru_update_event_q(4) and not(iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig))='1') + else lru_q(6); +lru_eff(6) <= (lru_vp_vec(6) and lru_op_vec(6)) or (lru_q(6) and not lru_op_vec(6)); +lru_d(7) <= '0' when ((ex6_ieratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(7)='1' and mmucr1_q(0)='0' and lru_op_vec(7)='0' and ccr2_frat_paranoia_q(9)='0' and + (lru_update_event_q(8)='1' or (lru_update_event_q(4) and not(iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig))='1') + else '1' when lru_set_vec(7)='1' and mmucr1_q(0)='0' and lru_op_vec(7)='0' and ccr2_frat_paranoia_q(9)='0' and + (lru_update_event_q(8)='1' or (lru_update_event_q(4) and not(iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig))='1') + else lru_q(7); +lru_eff(7) <= (lru_vp_vec(7) and lru_op_vec(7)) or (lru_q(7) and not lru_op_vec(7)); +lru_d(8) <= '0' when ((ex6_ieratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(8)='1' and mmucr1_q(0)='0' and lru_op_vec(8)='0' and ccr2_frat_paranoia_q(9)='0' and + (lru_update_event_q(8)='1' or (lru_update_event_q(4) and not(iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig))='1') + else '1' when lru_set_vec(8)='1' and mmucr1_q(0)='0' and lru_op_vec(8)='0' and ccr2_frat_paranoia_q(9)='0' and + (lru_update_event_q(8)='1' or (lru_update_event_q(4) and not(iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig))='1') + else lru_q(8); +lru_eff(8) <= (lru_vp_vec(8) and lru_op_vec(8)) or (lru_q(8) and not lru_op_vec(8)); +lru_d(9) <= '0' when ((ex6_ieratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(9)='1' and mmucr1_q(0)='0' and lru_op_vec(9)='0' and ccr2_frat_paranoia_q(9)='0' and + (lru_update_event_q(8)='1' or (lru_update_event_q(4) and not(iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig))='1') + else '1' when lru_set_vec(9)='1' and mmucr1_q(0)='0' and lru_op_vec(9)='0' and ccr2_frat_paranoia_q(9)='0' and + (lru_update_event_q(8)='1' or (lru_update_event_q(4) and not(iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig))='1') + else lru_q(9); +lru_eff(9) <= (lru_vp_vec(9) and lru_op_vec(9)) or (lru_q(9) and not lru_op_vec(9)); +lru_d(10) <= '0' when ((ex6_ieratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(10)='1' and mmucr1_q(0)='0' and lru_op_vec(10)='0' and ccr2_frat_paranoia_q(9)='0' and + (lru_update_event_q(8)='1' or (lru_update_event_q(4) and not(iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig))='1') + else '1' when lru_set_vec(10)='1' and mmucr1_q(0)='0' and lru_op_vec(10)='0' and ccr2_frat_paranoia_q(9)='0' and + (lru_update_event_q(8)='1' or (lru_update_event_q(4) and not(iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig))='1') + else lru_q(10); +lru_eff(10) <= (lru_vp_vec(10) and lru_op_vec(10)) or (lru_q(10) and not lru_op_vec(10)); +lru_d(11) <= '0' when ((ex6_ieratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(11)='1' and mmucr1_q(0)='0' and lru_op_vec(11)='0' and ccr2_frat_paranoia_q(9)='0' and + (lru_update_event_q(8)='1' or (lru_update_event_q(4) and not(iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig))='1') + else '1' when lru_set_vec(11)='1' and mmucr1_q(0)='0' and lru_op_vec(11)='0' and ccr2_frat_paranoia_q(9)='0' and + (lru_update_event_q(8)='1' or (lru_update_event_q(4) and not(iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig))='1') + else lru_q(11); +lru_eff(11) <= (lru_vp_vec(11) and lru_op_vec(11)) or (lru_q(11) and not lru_op_vec(11)); +lru_d(12) <= '0' when ((ex6_ieratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(12)='1' and mmucr1_q(0)='0' and lru_op_vec(12)='0' and ccr2_frat_paranoia_q(9)='0' and + (lru_update_event_q(8)='1' or (lru_update_event_q(4) and not(iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig))='1') + else '1' when lru_set_vec(12)='1' and mmucr1_q(0)='0' and lru_op_vec(12)='0' and ccr2_frat_paranoia_q(9)='0' and + (lru_update_event_q(8)='1' or (lru_update_event_q(4) and not(iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig))='1') + else lru_q(12); +lru_eff(12) <= (lru_vp_vec(12) and lru_op_vec(12)) or (lru_q(12) and not lru_op_vec(12)); +lru_d(13) <= '0' when ((ex6_ieratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(13)='1' and mmucr1_q(0)='0' and lru_op_vec(13)='0' and ccr2_frat_paranoia_q(9)='0' and + (lru_update_event_q(8)='1' or (lru_update_event_q(4) and not(iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig))='1') + else '1' when lru_set_vec(13)='1' and mmucr1_q(0)='0' and lru_op_vec(13)='0' and ccr2_frat_paranoia_q(9)='0' and + (lru_update_event_q(8)='1' or (lru_update_event_q(4) and not(iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig))='1') + else lru_q(13); +lru_eff(13) <= (lru_vp_vec(13) and lru_op_vec(13)) or (lru_q(13) and not lru_op_vec(13)); +lru_d(14) <= '0' when ((ex6_ieratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(14)='1' and mmucr1_q(0)='0' and lru_op_vec(14)='0' and ccr2_frat_paranoia_q(9)='0' and + (lru_update_event_q(8)='1' or (lru_update_event_q(4) and not(iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig))='1') + else '1' when lru_set_vec(14)='1' and mmucr1_q(0)='0' and lru_op_vec(14)='0' and ccr2_frat_paranoia_q(9)='0' and + (lru_update_event_q(8)='1' or (lru_update_event_q(4) and not(iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig))='1') + else lru_q(14); +lru_eff(14) <= (lru_vp_vec(14) and lru_op_vec(14)) or (lru_q(14) and not lru_op_vec(14)); +lru_d(15) <= '0' when ((ex6_ieratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(15)='1' and mmucr1_q(0)='0' and lru_op_vec(15)='0' and ccr2_frat_paranoia_q(9)='0' and + (lru_update_event_q(8)='1' or (lru_update_event_q(4) and not(iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig))='1') + else '1' when lru_set_vec(15)='1' and mmucr1_q(0)='0' and lru_op_vec(15)='0' and ccr2_frat_paranoia_q(9)='0' and + (lru_update_event_q(8)='1' or (lru_update_event_q(4) and not(iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig))='1') + else lru_q(15); +lru_eff(15) <= (lru_vp_vec(15) and lru_op_vec(15)) or (lru_q(15) and not lru_op_vec(15)); +-- RMT override enable: Op= OR(all RMT entries below and left of p) XOR OR(all RMT entries below and right of p) +lru_op_vec(1) <= (lru_rmt_vec(0) or lru_rmt_vec(1) or lru_rmt_vec(2) or lru_rmt_vec(3) or + lru_rmt_vec(4) or lru_rmt_vec(5) or lru_rmt_vec(6) or lru_rmt_vec(7)) xor + (lru_rmt_vec(8) or lru_rmt_vec(9) or lru_rmt_vec(10) or lru_rmt_vec(11) or + lru_rmt_vec(12) or lru_rmt_vec(13) or lru_rmt_vec(14) or lru_rmt_vec(15)); +lru_op_vec(2) <= (lru_rmt_vec(0) or lru_rmt_vec(1) or lru_rmt_vec(2) or lru_rmt_vec(3)) xor + (lru_rmt_vec(4) or lru_rmt_vec(5) or lru_rmt_vec(6) or lru_rmt_vec(7)); +lru_op_vec(3) <= (lru_rmt_vec(8) or lru_rmt_vec(9) or lru_rmt_vec(10) or lru_rmt_vec(11)) xor + (lru_rmt_vec(12) or lru_rmt_vec(13) or lru_rmt_vec(14) or lru_rmt_vec(15)); +lru_op_vec(4) <= (lru_rmt_vec(0) or lru_rmt_vec(1)) xor (lru_rmt_vec(2) or lru_rmt_vec(3)); +lru_op_vec(5) <= (lru_rmt_vec(4) or lru_rmt_vec(5)) xor (lru_rmt_vec(6) or lru_rmt_vec(7)); +lru_op_vec(6) <= (lru_rmt_vec(8) or lru_rmt_vec(9)) xor (lru_rmt_vec(10) or lru_rmt_vec(11)); +lru_op_vec(7) <= (lru_rmt_vec(12) or lru_rmt_vec(13)) xor (lru_rmt_vec(14) or lru_rmt_vec(15)); +lru_op_vec(8) <= lru_rmt_vec(0) xor lru_rmt_vec(1); +lru_op_vec(9) <= lru_rmt_vec(2) xor lru_rmt_vec(3); +lru_op_vec(10) <= lru_rmt_vec(4) xor lru_rmt_vec(5); +lru_op_vec(11) <= lru_rmt_vec(6) xor lru_rmt_vec(7); +lru_op_vec(12) <= lru_rmt_vec(8) xor lru_rmt_vec(9); +lru_op_vec(13) <= lru_rmt_vec(10) xor lru_rmt_vec(11); +lru_op_vec(14) <= lru_rmt_vec(12) xor lru_rmt_vec(13); +lru_op_vec(15) <= lru_rmt_vec(14) xor lru_rmt_vec(15); +-- RMT override value: Vp= OR(all RMT entries below and right of p) +lru_vp_vec(1) <= (lru_rmt_vec(8) or lru_rmt_vec(9) or lru_rmt_vec(10) or lru_rmt_vec(11) or + lru_rmt_vec(12) or lru_rmt_vec(13) or lru_rmt_vec(14) or lru_rmt_vec(15)); +lru_vp_vec(2) <= (lru_rmt_vec(4) or lru_rmt_vec(5) or lru_rmt_vec(6) or lru_rmt_vec(7)); +lru_vp_vec(3) <= (lru_rmt_vec(12) or lru_rmt_vec(13) or lru_rmt_vec(14) or lru_rmt_vec(15)); +lru_vp_vec(4) <= (lru_rmt_vec(2) or lru_rmt_vec(3)); +lru_vp_vec(5) <= (lru_rmt_vec(6) or lru_rmt_vec(7)); +lru_vp_vec(6) <= (lru_rmt_vec(10) or lru_rmt_vec(11)); +lru_vp_vec(7) <= (lru_rmt_vec(14) or lru_rmt_vec(15)); +lru_vp_vec(8) <= lru_rmt_vec(1); +lru_vp_vec(9) <= lru_rmt_vec(3); +lru_vp_vec(10) <= lru_rmt_vec(5); +lru_vp_vec(11) <= lru_rmt_vec(7); +lru_vp_vec(12) <= lru_rmt_vec(9); +lru_vp_vec(13) <= lru_rmt_vec(11); +lru_vp_vec(14) <= lru_rmt_vec(13); +lru_vp_vec(15) <= lru_rmt_vec(15); +-- mmucr1_q: 0-IRRE, 1-REE, 2-CEE, 3-csync, 4-isync, 5:6-IPEI, 7:8-ICTID/ITTID +-- Encoder for the LRU watermark psuedo-RMT +-- +-- Final Table Listing +-- *INPUTS*==================*OUTPUTS*============* +-- | | | +-- | mmucr1_q | lru_rmt_vec | +-- | | watermark_q | | | +-- | | | | | | +-- | | | | | | +-- | | | | | 111111 | +-- | 012345678 0123 | 0123456789012345 | +-- *TYPE*====================+====================+ +-- | PPPPPPPPP PPPP | PPPPPPPPPPPPPPPP | +-- *POLARITY*--------------->| ++++++++++++++++ | +-- *PHASE*------------------>| TTTTTTTTTTTTTTTT | +-- *OPTIMIZE*--------------->| AAAAAAAAAAAAAAAA | +-- *TERMS*===================+====================+ +-- 1 | --------- 1111 | ...............1 | +-- 2 | --------- -111 | .......1........ | +-- 3 | --------- 1-11 | ...........1.... | +-- 4 | --------- --11 | ...1............ | +-- 5 | --------- 11-1 | .............1.. | +-- 6 | --------- -1-1 | .....1.......... | +-- 7 | --------- 1--1 | .........1...... | +-- 8 | --------- ---1 | .1.............. | +-- 9 | --------- 111- | .............11. | +-- 10 | --------- -11- | .....11......... | +-- 11 | --------- 1-1- | .........11..... | +-- 12 | --------- --1- | .11............. | +-- 13 | --------- 11-- | .........1111... | +-- 14 | --------- -1-- | .1111........... | +-- 15 | --------- 1--- | .11111111....... | +-- 16 | 1-------- ---- | .111111111111111 | +-- 17 | --------- ---- | 1............... | +-- *==============================================* +-- +-- Table LRU_RMT_VEC Signal Assignments for Product Terms +MQQ37:LRU_RMT_VEC_PT(1) <= + Eq(( WATERMARK_Q(0) & WATERMARK_Q(1) & + WATERMARK_Q(2) & WATERMARK_Q(3) + ) , STD_ULOGIC_VECTOR'("1111")); +MQQ38:LRU_RMT_VEC_PT(2) <= + Eq(( WATERMARK_Q(1) & WATERMARK_Q(2) & + WATERMARK_Q(3) ) , STD_ULOGIC_VECTOR'("111")); +MQQ39:LRU_RMT_VEC_PT(3) <= + Eq(( WATERMARK_Q(0) & WATERMARK_Q(2) & + WATERMARK_Q(3) ) , STD_ULOGIC_VECTOR'("111")); +MQQ40:LRU_RMT_VEC_PT(4) <= + Eq(( WATERMARK_Q(2) & WATERMARK_Q(3) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ41:LRU_RMT_VEC_PT(5) <= + Eq(( WATERMARK_Q(0) & WATERMARK_Q(1) & + WATERMARK_Q(3) ) , STD_ULOGIC_VECTOR'("111")); +MQQ42:LRU_RMT_VEC_PT(6) <= + Eq(( WATERMARK_Q(1) & WATERMARK_Q(3) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ43:LRU_RMT_VEC_PT(7) <= + Eq(( WATERMARK_Q(0) & WATERMARK_Q(3) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ44:LRU_RMT_VEC_PT(8) <= + Eq(( WATERMARK_Q(3) ) , STD_ULOGIC'('1')); +MQQ45:LRU_RMT_VEC_PT(9) <= + Eq(( WATERMARK_Q(0) & WATERMARK_Q(1) & + WATERMARK_Q(2) ) , STD_ULOGIC_VECTOR'("111")); +MQQ46:LRU_RMT_VEC_PT(10) <= + Eq(( WATERMARK_Q(1) & WATERMARK_Q(2) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ47:LRU_RMT_VEC_PT(11) <= + Eq(( WATERMARK_Q(0) & WATERMARK_Q(2) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ48:LRU_RMT_VEC_PT(12) <= + Eq(( WATERMARK_Q(2) ) , STD_ULOGIC'('1')); +MQQ49:LRU_RMT_VEC_PT(13) <= + Eq(( WATERMARK_Q(0) & WATERMARK_Q(1) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ50:LRU_RMT_VEC_PT(14) <= + Eq(( WATERMARK_Q(1) ) , STD_ULOGIC'('1')); +MQQ51:LRU_RMT_VEC_PT(15) <= + Eq(( WATERMARK_Q(0) ) , STD_ULOGIC'('1')); +MQQ52:LRU_RMT_VEC_PT(16) <= + Eq(( MMUCR1_Q(0) ) , STD_ULOGIC'('1')); +MQQ53:LRU_RMT_VEC_PT(17) <= + '1'; +-- Table LRU_RMT_VEC Signal Assignments for Outputs +MQQ54:LRU_RMT_VEC(0) <= + (LRU_RMT_VEC_PT(17)); +MQQ55:LRU_RMT_VEC(1) <= + (LRU_RMT_VEC_PT(8) OR LRU_RMT_VEC_PT(12) + OR LRU_RMT_VEC_PT(14) OR LRU_RMT_VEC_PT(15) + OR LRU_RMT_VEC_PT(16)); +MQQ56:LRU_RMT_VEC(2) <= + (LRU_RMT_VEC_PT(12) OR LRU_RMT_VEC_PT(14) + OR LRU_RMT_VEC_PT(15) OR LRU_RMT_VEC_PT(16) + ); +MQQ57:LRU_RMT_VEC(3) <= + (LRU_RMT_VEC_PT(4) OR LRU_RMT_VEC_PT(14) + OR LRU_RMT_VEC_PT(15) OR LRU_RMT_VEC_PT(16) + ); +MQQ58:LRU_RMT_VEC(4) <= + (LRU_RMT_VEC_PT(14) OR LRU_RMT_VEC_PT(15) + OR LRU_RMT_VEC_PT(16)); +MQQ59:LRU_RMT_VEC(5) <= + (LRU_RMT_VEC_PT(6) OR LRU_RMT_VEC_PT(10) + OR LRU_RMT_VEC_PT(15) OR LRU_RMT_VEC_PT(16) + ); +MQQ60:LRU_RMT_VEC(6) <= + (LRU_RMT_VEC_PT(10) OR LRU_RMT_VEC_PT(15) + OR LRU_RMT_VEC_PT(16)); +MQQ61:LRU_RMT_VEC(7) <= + (LRU_RMT_VEC_PT(2) OR LRU_RMT_VEC_PT(15) + OR LRU_RMT_VEC_PT(16)); +MQQ62:LRU_RMT_VEC(8) <= + (LRU_RMT_VEC_PT(15) OR LRU_RMT_VEC_PT(16) + ); +MQQ63:LRU_RMT_VEC(9) <= + (LRU_RMT_VEC_PT(7) OR LRU_RMT_VEC_PT(11) + OR LRU_RMT_VEC_PT(13) OR LRU_RMT_VEC_PT(16) + ); +MQQ64:LRU_RMT_VEC(10) <= + (LRU_RMT_VEC_PT(11) OR LRU_RMT_VEC_PT(13) + OR LRU_RMT_VEC_PT(16)); +MQQ65:LRU_RMT_VEC(11) <= + (LRU_RMT_VEC_PT(3) OR LRU_RMT_VEC_PT(13) + OR LRU_RMT_VEC_PT(16)); +MQQ66:LRU_RMT_VEC(12) <= + (LRU_RMT_VEC_PT(13) OR LRU_RMT_VEC_PT(16) + ); +MQQ67:LRU_RMT_VEC(13) <= + (LRU_RMT_VEC_PT(5) OR LRU_RMT_VEC_PT(9) + OR LRU_RMT_VEC_PT(16)); +MQQ68:LRU_RMT_VEC(14) <= + (LRU_RMT_VEC_PT(9) OR LRU_RMT_VEC_PT(16) + ); +MQQ69:LRU_RMT_VEC(15) <= + (LRU_RMT_VEC_PT(1) OR LRU_RMT_VEC_PT(16) + ); + +-- +-- Final Table Listing +-- *INPUTS*==================*OUTPUTS*===============* +-- | | | +-- | mmucr1_q | lru_watermark_mask | +-- | | watermark_q | | | +-- | | | | | | +-- | | | | | | +-- | | | | | 111111 | +-- | 012345678 0123 | 0123456789012345 | +-- *TYPE*====================+=======================+ +-- | PPPPPPPPP PPPP | PPPPPPPPPPPPPPPP | +-- *POLARITY*--------------->| ++++++++++++++++ | +-- *PHASE*------------------>| TTTTTTTTTTTTTTTT | +-- *OPTIMIZE*--------------->| AAAAAAAAAAAAAAAA | +-- *TERMS*===================+=======================+ +-- 1 | --------- 0000 | .1.............. | +-- 2 | --------- -000 | .........1...... | +-- 3 | --------- 0-00 | .....1.......... | +-- 4 | --------- --00 | .............1.. | +-- 5 | --------- 00-0 | ...1............ | +-- 6 | --------- -0-0 | ...........1.... | +-- 7 | --------- 0--0 | .......1........ | +-- 8 | --------- ---0 | ...............1 | +-- 9 | --------- 000- | ..11............ | +-- 10 | --------- -00- | ..........11.... | +-- 11 | --------- 0-0- | ......11........ | +-- 12 | --------- --0- | ..............11 | +-- 13 | --------- 00-- | ....1111........ | +-- 14 | --------- -0-- | ............1111 | +-- 15 | --------- 0--- | ........11111111 | +-- *=================================================* +-- +-- Table LRU_WATERMARK_MASK Signal Assignments for Product Terms +MQQ70:LRU_WATERMARK_MASK_PT(1) <= + Eq(( WATERMARK_Q(0) & WATERMARK_Q(1) & + WATERMARK_Q(2) & WATERMARK_Q(3) + ) , STD_ULOGIC_VECTOR'("0000")); +MQQ71:LRU_WATERMARK_MASK_PT(2) <= + Eq(( WATERMARK_Q(1) & WATERMARK_Q(2) & + WATERMARK_Q(3) ) , STD_ULOGIC_VECTOR'("000")); +MQQ72:LRU_WATERMARK_MASK_PT(3) <= + Eq(( WATERMARK_Q(0) & WATERMARK_Q(2) & + WATERMARK_Q(3) ) , STD_ULOGIC_VECTOR'("000")); +MQQ73:LRU_WATERMARK_MASK_PT(4) <= + Eq(( WATERMARK_Q(2) & WATERMARK_Q(3) + ) , STD_ULOGIC_VECTOR'("00")); +MQQ74:LRU_WATERMARK_MASK_PT(5) <= + Eq(( WATERMARK_Q(0) & WATERMARK_Q(1) & + WATERMARK_Q(3) ) , STD_ULOGIC_VECTOR'("000")); +MQQ75:LRU_WATERMARK_MASK_PT(6) <= + Eq(( WATERMARK_Q(1) & WATERMARK_Q(3) + ) , STD_ULOGIC_VECTOR'("00")); +MQQ76:LRU_WATERMARK_MASK_PT(7) <= + Eq(( WATERMARK_Q(0) & WATERMARK_Q(3) + ) , STD_ULOGIC_VECTOR'("00")); +MQQ77:LRU_WATERMARK_MASK_PT(8) <= + Eq(( WATERMARK_Q(3) ) , STD_ULOGIC'('0')); +MQQ78:LRU_WATERMARK_MASK_PT(9) <= + Eq(( WATERMARK_Q(0) & WATERMARK_Q(1) & + WATERMARK_Q(2) ) , STD_ULOGIC_VECTOR'("000")); +MQQ79:LRU_WATERMARK_MASK_PT(10) <= + Eq(( WATERMARK_Q(1) & WATERMARK_Q(2) + ) , STD_ULOGIC_VECTOR'("00")); +MQQ80:LRU_WATERMARK_MASK_PT(11) <= + Eq(( WATERMARK_Q(0) & WATERMARK_Q(2) + ) , STD_ULOGIC_VECTOR'("00")); +MQQ81:LRU_WATERMARK_MASK_PT(12) <= + Eq(( WATERMARK_Q(2) ) , STD_ULOGIC'('0')); +MQQ82:LRU_WATERMARK_MASK_PT(13) <= + Eq(( WATERMARK_Q(0) & WATERMARK_Q(1) + ) , STD_ULOGIC_VECTOR'("00")); +MQQ83:LRU_WATERMARK_MASK_PT(14) <= + Eq(( WATERMARK_Q(1) ) , STD_ULOGIC'('0')); +MQQ84:LRU_WATERMARK_MASK_PT(15) <= + Eq(( WATERMARK_Q(0) ) , STD_ULOGIC'('0')); +-- Table LRU_WATERMARK_MASK Signal Assignments for Outputs +MQQ85:LRU_WATERMARK_MASK(0) <= + ('0'); +MQQ86:LRU_WATERMARK_MASK(1) <= + (LRU_WATERMARK_MASK_PT(1)); +MQQ87:LRU_WATERMARK_MASK(2) <= + (LRU_WATERMARK_MASK_PT(9)); +MQQ88:LRU_WATERMARK_MASK(3) <= + (LRU_WATERMARK_MASK_PT(5) OR LRU_WATERMARK_MASK_PT(9) + ); +MQQ89:LRU_WATERMARK_MASK(4) <= + (LRU_WATERMARK_MASK_PT(13)); +MQQ90:LRU_WATERMARK_MASK(5) <= + (LRU_WATERMARK_MASK_PT(3) OR LRU_WATERMARK_MASK_PT(13) + ); +MQQ91:LRU_WATERMARK_MASK(6) <= + (LRU_WATERMARK_MASK_PT(11) OR LRU_WATERMARK_MASK_PT(13) + ); +MQQ92:LRU_WATERMARK_MASK(7) <= + (LRU_WATERMARK_MASK_PT(7) OR LRU_WATERMARK_MASK_PT(11) + OR LRU_WATERMARK_MASK_PT(13)); +MQQ93:LRU_WATERMARK_MASK(8) <= + (LRU_WATERMARK_MASK_PT(15)); +MQQ94:LRU_WATERMARK_MASK(9) <= + (LRU_WATERMARK_MASK_PT(2) OR LRU_WATERMARK_MASK_PT(15) + ); +MQQ95:LRU_WATERMARK_MASK(10) <= + (LRU_WATERMARK_MASK_PT(10) OR LRU_WATERMARK_MASK_PT(15) + ); +MQQ96:LRU_WATERMARK_MASK(11) <= + (LRU_WATERMARK_MASK_PT(6) OR LRU_WATERMARK_MASK_PT(10) + OR LRU_WATERMARK_MASK_PT(15)); +MQQ97:LRU_WATERMARK_MASK(12) <= + (LRU_WATERMARK_MASK_PT(14) OR LRU_WATERMARK_MASK_PT(15) + ); +MQQ98:LRU_WATERMARK_MASK(13) <= + (LRU_WATERMARK_MASK_PT(4) OR LRU_WATERMARK_MASK_PT(14) + OR LRU_WATERMARK_MASK_PT(15)); +MQQ99:LRU_WATERMARK_MASK(14) <= + (LRU_WATERMARK_MASK_PT(12) OR LRU_WATERMARK_MASK_PT(14) + OR LRU_WATERMARK_MASK_PT(15)); +MQQ100:LRU_WATERMARK_MASK(15) <= + (LRU_WATERMARK_MASK_PT(8) OR LRU_WATERMARK_MASK_PT(12) + OR LRU_WATERMARK_MASK_PT(14) OR LRU_WATERMARK_MASK_PT(15) + ); + +entry_valid_watermarked <= entry_valid_q or lru_watermark_mask; +-- lru_update_event +-- 0: tlb reload +-- 1: invalidate snoop +-- 2: csync or isync enabled +-- 3: eratwe WS=0 +-- 4: fetch hit +-- 5: iu2 cam write type events +-- 6: iu2 cam invalidate type events +-- 7: iu2 cam translation type events +-- 8: superset, ex2 +-- 9: superset, delayed to ex3 +-- logic for the LRU reset and set bit vectors +-- ?TABLE lru_set_reset_vec LISTING(final) OPTIMIZE PARMS(ON-SET, OFF-SET); +-- +-- Final Table Listing +-- *INPUTS*======================================================*OUTPUTS*===========================* +-- | | | +-- | lru_update_event_q | lru_reset_vec | +-- | | entry_valid_watermarked | | lru_set_vec | +-- | | | lru_q | | | | +-- | | | | entry_match_q | | | | +-- | | | | | | | | | +-- | | | 111111 | 111111 | 111111 | | 111111 | 111111 | +-- | 012345678 0123456789012345 123456789012345 0123456789012345 | 123456789012345 123456789012345 | +-- *TYPE*========================================================+===================================+ +-- | PPPPPPPPP PPPPPPPPPPPPPPPP PPPPPPPPPPPPPPP PPPPPPPPPPPPPPPP | PPPPPPPPPPPPPPP PPPPPPPPPPPPPPP | +-- *POLARITY*--------------------------------------------------->| +++++++++++++++ +++++++++++++++ | +-- *PHASE*------------------------------------------------------>| TTTTTTTTTTTTTTT TTTTTTTTTTTTTTT | +-- *OPTIMIZE*--------------------------------------------------->| AAAAAAAAAAAAAAA BBBBBBBBBBBBBBB | +-- *TERMS*=======================================================+===================================+ +-- 1 | -----001- 1111111111111111 --------------- 0000000000000001 | 1.1...1.......1 ............... | +-- 2 | -----001- 1111111111111111 --------------- 000000000000001- | 1.1...1........ ............... | +-- 3 | -----001- 111111111111111- --------------- 000000000000001- | ............... ..............1 | +-- 4 | -----001- 1111111111111111 --------------- 00000000000001-- | 1.1..........1. ............... | +-- 5 | -----001- 11111111111111-- --------------- 000000000000-1-- | ............... ......1........ | +-- 6 | -----001- 1111111111111111 --------------- 0000000000001--- | 1.1............ ......1......1. | +-- 7 | -----001- 1111111111111111 --------------- 000000000001---- | 1....1......1.. ............... | +-- 8 | -----001- 111111111111---- --------------- 00000000---1---- | ............... ..1............ | +-- 9 | -----001- 1111111111111111 --------------- 00000000001----- | 1....1......... ..1.........1.. | +-- 10 | -----001- 1111111111111111 --------------- 0000000001------ | 1..........1... ............... | +-- 11 | -----001- 1111111111111111 --------------- 00000000-1------ | ............... ..1..1......... | +-- 12 | -----001- 1111111111111111 --------------- 000000001------- | ............... ..1..1.....1... | +-- 13 | -----001- --------11111111 --------------- 000000001------- | 1.............. ............... | +-- 14 | -----001- 1111111111111111 --------------- 00000001-------- | .1..1.....1.... ............... | +-- 15 | -----001- 11111111-------- --------------- -------1-------- | ............... 1.............. | +-- 16 | -----001- 1111111111111111 --------------- 0000001--------- | .1..1.......... 1.........1.... | +-- 17 | -----001- 1111111111111111 --------------- 000001---------- | .1.......1..... ............... | +-- 18 | -----001- 1111111111111111 --------------- 0000-1---------- | ............... 1...1.......... | +-- 19 | -----001- 1111111111111111 --------------- 00001----------- | ............... 1...1....1..... | +-- 20 | -----001- ----111111111111 --------------- 00001----------- | .1............. ............... | +-- 21 | -----001- 1111111111111111 --------------- 0001------------ | ...1....1...... ............... | +-- 22 | -----001- 1111111111111111 --------------- ---1------------ | ............... 11............. | +-- 23 | -----001- 1111111111111111 --------------- 001------------- | ............... 11......1...... | +-- 24 | -----001- --11111111111111 --------------- 001------------- | ...1........... ............... | +-- 25 | -----001- -111111111111111 --------------- 01-------------- | .......1....... ............... | +-- 26 | -----001- 1111111111111111 --------------- -1-------------- | ............... 11.1........... | +-- 27 | -----001- 1111111111111111 --------------- 1--------------- | ............... 11.1...1....... | +-- 28 | -----1--- 111111111111111- 1-1---1-------0 ---------------- | ............... ..............1 | +-- 29 | -----1--- 11111111111111-1 1-1---1-------1 ---------------- | ..............1 ............... | +-- 30 | -----1--- 1111111111111-11 1-1---0------0- ---------------- | ............... .............1. | +-- 31 | -----1--- 111111111111-111 1-1---0------1- ---------------- | .............1. ............... | +-- 32 | -----1--- 11111111111-1111 1-0--1------0-- ---------------- | ............... ............1.. | +-- 33 | -----1--- 1111111111-11111 1-0--1------1-- ---------------- | ............1.. ............... | +-- 34 | -----1--- 111111111-111111 1-0--0-----0--- ---------------- | ............... ...........1... | +-- 35 | -----1--- 11111111-1111111 1-0--0-----1--- ---------------- | ...........1... ............... | +-- 36 | -----1--- 1111111-11111111 01--1-----0---- ---------------- | ............... ..........1.... | +-- 37 | -----1--- 111111-111111111 01--1-----1---- ---------------- | ..........1.... ............... | +-- 38 | -----1--- 11111-1111111111 01--0----0----- ---------------- | ............... .........1..... | +-- 39 | -----1--- 1111-11111111111 01--0----1----- ---------------- | .........1..... ............... | +-- 40 | -----1--- 111-111111111111 00-1----0------ ---------------- | ............... ........1...... | +-- 41 | -----1--- 11-1111111111111 00-1----1------ ---------------- | ........1...... ............... | +-- 42 | -----1--- 1-11111111111111 00-0---0------- ---------------- | ............... .......1....... | +-- 43 | -----1--- -111111111111111 00-0---1------- ---------------- | .......1....... ............... | +-- 44 | -----1--- 11111111111111-- 1-1---0-------- ---------------- | ............... ......1........ | +-- 45 | -----1--- 111111111111--11 1-1---1-------- ---------------- | ......1........ ............... | +-- 46 | -----1--- 1111111111--1111 1-0--0--------- ---------------- | ............... .....1......... | +-- 47 | -----1--- 11111111--111111 1-0--1--------- ---------------- | .....1......... ............... | +-- 48 | -----1--- 111111--11111111 01--0---------- ---------------- | ............... ....1.......... | +-- 49 | -----1--- 1111--1111111111 01--1---------- ---------------- | ....1.......... ............... | +-- 50 | -----1--- 11--111111111111 00-0----------- ---------------- | ............... ...1........... | +-- 51 | -----1--- --11111111111111 00-1----------- ---------------- | ...1........... ............... | +-- 52 | -----1--- 111111111111---- 1-0------------ ---------------- | ............... ..1............ | +-- 53 | -----1--- 11111111----1111 1-1------------ ---------------- | ..1............ ............... | +-- 54 | -----1--- 1111----11111111 00------------- ---------------- | ............... .1............. | +-- 55 | -----1--- ----111111111111 01------------- ---------------- | .1............. ............... | +-- 56 | -----1--- 11111111-------- 0-------------- ---------------- | ............... 1.............. | +-- 57 | -----1--- --------11111111 1-------------- ---------------- | 1.............. ............... | +-- 58 | --------- 1111111111111110 --------------- ---------------- | ............... 1.1...1.......1 | +-- 59 | --------- 111111111111110- --------------- ---------------- | ..............1 1.1...1........ | +-- 60 | --------- 11111111111110-- --------------- ---------------- | ............... 1.1..........1. | +-- 61 | --------- 111111111111-0-- --------------- ---------------- | ......1........ ............... | +-- 62 | --------- 1111111111110--- --------------- ---------------- | ......1......1. 1.1............ | +-- 63 | --------- 111111111110---- --------------- ---------------- | ............... 1....1......1.. | +-- 64 | --------- 11111111---0---- --------------- ---------------- | ..1............ ............... | +-- 65 | --------- 11111111110----- --------------- ---------------- | ..1.........1.. 1....1......... | +-- 66 | --------- 1111111110------ --------------- ---------------- | ............... 1..........1... | +-- 67 | --------- 11111111-0------ --------------- ---------------- | ..1..1......... ............... | +-- 68 | --------- 111111110------- --------------- ---------------- | ..1..1.....1... 1.............. | +-- 69 | --------- 11111110-------- --------------- ---------------- | ............... .1..1.....1.... | +-- 70 | --------- -------0-------- --------------- ---------------- | 1.............. ............... | +-- 71 | --------- 1111110--------- --------------- ---------------- | 1.........1.... .1..1.......... | +-- 72 | --------- 111110---------- --------------- ---------------- | ............... .1.......1..... | +-- 73 | --------- 1111-0---------- --------------- ---------------- | 1...1.......... ............... | +-- 74 | --------- 11110----------- --------------- ---------------- | 1...1....1..... .1............. | +-- 75 | --------- 1110------------ --------------- ---------------- | ............... ...1....1...... | +-- 76 | --------- ---0------------ --------------- ---------------- | 11............. ............... | +-- 77 | --------- 110------------- --------------- ---------------- | 11......1...... ...1........... | +-- 78 | --------- 10-------------- --------------- ---------------- | ............... .......1....... | +-- 79 | --------- -0-------------- --------------- ---------------- | 11.1........... ............... | +-- 80 | --------- 0--------------- --------------- ---------------- | 11.1...1....... ............... | +-- *=================================================================================================* +-- +-- Table LRU_SET_RESET_VEC Signal Assignments for Product Terms +MQQ101:LRU_SET_RESET_VEC_PT(1) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) & + ENTRY_MATCH_Q(13) & ENTRY_MATCH_Q(14) & + ENTRY_MATCH_Q(15) ) , STD_ULOGIC_VECTOR'("00111111111111111110000000000000001")); +MQQ102:LRU_SET_RESET_VEC_PT(2) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) & + ENTRY_MATCH_Q(13) & ENTRY_MATCH_Q(14) + ) , STD_ULOGIC_VECTOR'("0011111111111111111000000000000001")); +MQQ103:LRU_SET_RESET_VEC_PT(3) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_MATCH_Q(0) & ENTRY_MATCH_Q(1) & + ENTRY_MATCH_Q(2) & ENTRY_MATCH_Q(3) & + ENTRY_MATCH_Q(4) & ENTRY_MATCH_Q(5) & + ENTRY_MATCH_Q(6) & ENTRY_MATCH_Q(7) & + ENTRY_MATCH_Q(8) & ENTRY_MATCH_Q(9) & + ENTRY_MATCH_Q(10) & ENTRY_MATCH_Q(11) & + ENTRY_MATCH_Q(12) & ENTRY_MATCH_Q(13) & + ENTRY_MATCH_Q(14) ) , STD_ULOGIC_VECTOR'("001111111111111111000000000000001")); +MQQ104:LRU_SET_RESET_VEC_PT(4) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) & + ENTRY_MATCH_Q(13) ) , STD_ULOGIC_VECTOR'("001111111111111111100000000000001")); +MQQ105:LRU_SET_RESET_VEC_PT(5) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(13) + ) , STD_ULOGIC_VECTOR'("001111111111111110000000000001")); +MQQ106:LRU_SET_RESET_VEC_PT(6) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) + ) , STD_ULOGIC_VECTOR'("00111111111111111110000000000001")); +MQQ107:LRU_SET_RESET_VEC_PT(7) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) ) , STD_ULOGIC_VECTOR'("0011111111111111111000000000001")); +MQQ108:LRU_SET_RESET_VEC_PT(8) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(11) + ) , STD_ULOGIC_VECTOR'("001111111111111000000001")); +MQQ109:LRU_SET_RESET_VEC_PT(9) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) + ) , STD_ULOGIC_VECTOR'("001111111111111111100000000001")); +MQQ110:LRU_SET_RESET_VEC_PT(10) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) ) , STD_ULOGIC_VECTOR'("00111111111111111110000000001")); +MQQ111:LRU_SET_RESET_VEC_PT(11) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(9) + ) , STD_ULOGIC_VECTOR'("0011111111111111111000000001")); +MQQ112:LRU_SET_RESET_VEC_PT(12) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) + ) , STD_ULOGIC_VECTOR'("0011111111111111111000000001")); +MQQ113:LRU_SET_RESET_VEC_PT(13) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) + ) , STD_ULOGIC_VECTOR'("00111111111000000001")); +MQQ114:LRU_SET_RESET_VEC_PT(14) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) ) , STD_ULOGIC_VECTOR'("001111111111111111100000001")); +MQQ115:LRU_SET_RESET_VEC_PT(15) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_MATCH_Q(7) + ) , STD_ULOGIC_VECTOR'("001111111111")); +MQQ116:LRU_SET_RESET_VEC_PT(16) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) + ) , STD_ULOGIC_VECTOR'("00111111111111111110000001")); +MQQ117:LRU_SET_RESET_VEC_PT(17) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) ) , STD_ULOGIC_VECTOR'("0011111111111111111000001")); +MQQ118:LRU_SET_RESET_VEC_PT(18) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(5) + ) , STD_ULOGIC_VECTOR'("001111111111111111100001")); +MQQ119:LRU_SET_RESET_VEC_PT(19) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) + ) , STD_ULOGIC_VECTOR'("001111111111111111100001")); +MQQ120:LRU_SET_RESET_VEC_PT(20) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) + ) , STD_ULOGIC_VECTOR'("00111111111111100001")); +MQQ121:LRU_SET_RESET_VEC_PT(21) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) ) , STD_ULOGIC_VECTOR'("00111111111111111110001")); +MQQ122:LRU_SET_RESET_VEC_PT(22) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_MATCH_Q(3) + ) , STD_ULOGIC_VECTOR'("00111111111111111111")); +MQQ123:LRU_SET_RESET_VEC_PT(23) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) + ) , STD_ULOGIC_VECTOR'("0011111111111111111001")); +MQQ124:LRU_SET_RESET_VEC_PT(24) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) + ) , STD_ULOGIC_VECTOR'("00111111111111111001")); +MQQ125:LRU_SET_RESET_VEC_PT(25) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_MATCH_Q(0) & ENTRY_MATCH_Q(1) + ) , STD_ULOGIC_VECTOR'("00111111111111111101")); +MQQ126:LRU_SET_RESET_VEC_PT(26) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_MATCH_Q(1) + ) , STD_ULOGIC_VECTOR'("00111111111111111111")); +MQQ127:LRU_SET_RESET_VEC_PT(27) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_MATCH_Q(0) + ) , STD_ULOGIC_VECTOR'("00111111111111111111")); +MQQ128:LRU_SET_RESET_VEC_PT(28) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + LRU_Q(1) & LRU_Q(3) & + LRU_Q(7) & LRU_Q(15) + ) , STD_ULOGIC_VECTOR'("11111111111111111110")); +MQQ129:LRU_SET_RESET_VEC_PT(29) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(15) & + LRU_Q(1) & LRU_Q(3) & + LRU_Q(7) & LRU_Q(15) + ) , STD_ULOGIC_VECTOR'("11111111111111111111")); +MQQ130:LRU_SET_RESET_VEC_PT(30) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + LRU_Q(1) & LRU_Q(3) & + LRU_Q(7) & LRU_Q(14) + ) , STD_ULOGIC_VECTOR'("11111111111111111100")); +MQQ131:LRU_SET_RESET_VEC_PT(31) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + LRU_Q(1) & LRU_Q(3) & + LRU_Q(7) & LRU_Q(14) + ) , STD_ULOGIC_VECTOR'("11111111111111111101")); +MQQ132:LRU_SET_RESET_VEC_PT(32) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + LRU_Q(1) & LRU_Q(3) & + LRU_Q(6) & LRU_Q(13) + ) , STD_ULOGIC_VECTOR'("11111111111111111010")); +MQQ133:LRU_SET_RESET_VEC_PT(33) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + LRU_Q(1) & LRU_Q(3) & + LRU_Q(6) & LRU_Q(13) + ) , STD_ULOGIC_VECTOR'("11111111111111111011")); +MQQ134:LRU_SET_RESET_VEC_PT(34) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + LRU_Q(1) & LRU_Q(3) & + LRU_Q(6) & LRU_Q(12) + ) , STD_ULOGIC_VECTOR'("11111111111111111000")); +MQQ135:LRU_SET_RESET_VEC_PT(35) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + LRU_Q(1) & LRU_Q(3) & + LRU_Q(6) & LRU_Q(12) + ) , STD_ULOGIC_VECTOR'("11111111111111111001")); +MQQ136:LRU_SET_RESET_VEC_PT(36) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + LRU_Q(1) & LRU_Q(2) & + LRU_Q(5) & LRU_Q(11) + ) , STD_ULOGIC_VECTOR'("11111111111111110110")); +MQQ137:LRU_SET_RESET_VEC_PT(37) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + LRU_Q(1) & LRU_Q(2) & + LRU_Q(5) & LRU_Q(11) + ) , STD_ULOGIC_VECTOR'("11111111111111110111")); +MQQ138:LRU_SET_RESET_VEC_PT(38) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + LRU_Q(1) & LRU_Q(2) & + LRU_Q(5) & LRU_Q(10) + ) , STD_ULOGIC_VECTOR'("11111111111111110100")); +MQQ139:LRU_SET_RESET_VEC_PT(39) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + LRU_Q(1) & LRU_Q(2) & + LRU_Q(5) & LRU_Q(10) + ) , STD_ULOGIC_VECTOR'("11111111111111110101")); +MQQ140:LRU_SET_RESET_VEC_PT(40) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + LRU_Q(1) & LRU_Q(2) & + LRU_Q(4) & LRU_Q(9) + ) , STD_ULOGIC_VECTOR'("11111111111111110010")); +MQQ141:LRU_SET_RESET_VEC_PT(41) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + LRU_Q(1) & LRU_Q(2) & + LRU_Q(4) & LRU_Q(9) + ) , STD_ULOGIC_VECTOR'("11111111111111110011")); +MQQ142:LRU_SET_RESET_VEC_PT(42) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + LRU_Q(1) & LRU_Q(2) & + LRU_Q(4) & LRU_Q(8) + ) , STD_ULOGIC_VECTOR'("11111111111111110000")); +MQQ143:LRU_SET_RESET_VEC_PT(43) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + LRU_Q(1) & LRU_Q(2) & + LRU_Q(4) & LRU_Q(8) + ) , STD_ULOGIC_VECTOR'("11111111111111110001")); +MQQ144:LRU_SET_RESET_VEC_PT(44) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & LRU_Q(1) & + LRU_Q(3) & LRU_Q(7) + ) , STD_ULOGIC_VECTOR'("111111111111111110")); +MQQ145:LRU_SET_RESET_VEC_PT(45) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & LRU_Q(1) & + LRU_Q(3) & LRU_Q(7) + ) , STD_ULOGIC_VECTOR'("111111111111111111")); +MQQ146:LRU_SET_RESET_VEC_PT(46) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & LRU_Q(1) & + LRU_Q(3) & LRU_Q(6) + ) , STD_ULOGIC_VECTOR'("111111111111111100")); +MQQ147:LRU_SET_RESET_VEC_PT(47) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & LRU_Q(1) & + LRU_Q(3) & LRU_Q(6) + ) , STD_ULOGIC_VECTOR'("111111111111111101")); +MQQ148:LRU_SET_RESET_VEC_PT(48) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & LRU_Q(1) & + LRU_Q(2) & LRU_Q(5) + ) , STD_ULOGIC_VECTOR'("111111111111111010")); +MQQ149:LRU_SET_RESET_VEC_PT(49) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & LRU_Q(1) & + LRU_Q(2) & LRU_Q(5) + ) , STD_ULOGIC_VECTOR'("111111111111111011")); +MQQ150:LRU_SET_RESET_VEC_PT(50) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & LRU_Q(1) & + LRU_Q(2) & LRU_Q(4) + ) , STD_ULOGIC_VECTOR'("111111111111111000")); +MQQ151:LRU_SET_RESET_VEC_PT(51) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & LRU_Q(1) & + LRU_Q(2) & LRU_Q(4) + ) , STD_ULOGIC_VECTOR'("111111111111111001")); +MQQ152:LRU_SET_RESET_VEC_PT(52) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & LRU_Q(1) & + LRU_Q(3) ) , STD_ULOGIC_VECTOR'("111111111111110")); +MQQ153:LRU_SET_RESET_VEC_PT(53) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & LRU_Q(1) & + LRU_Q(3) ) , STD_ULOGIC_VECTOR'("111111111111111")); +MQQ154:LRU_SET_RESET_VEC_PT(54) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & LRU_Q(1) & + LRU_Q(2) ) , STD_ULOGIC_VECTOR'("111111111111100")); +MQQ155:LRU_SET_RESET_VEC_PT(55) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & LRU_Q(1) & + LRU_Q(2) ) , STD_ULOGIC_VECTOR'("111111111111101")); +MQQ156:LRU_SET_RESET_VEC_PT(56) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & LRU_Q(1) + ) , STD_ULOGIC_VECTOR'("1111111110")); +MQQ157:LRU_SET_RESET_VEC_PT(57) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & LRU_Q(1) + ) , STD_ULOGIC_VECTOR'("1111111111")); +MQQ158:LRU_SET_RESET_VEC_PT(58) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) + ) , STD_ULOGIC_VECTOR'("1111111111111110")); +MQQ159:LRU_SET_RESET_VEC_PT(59) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) ) , STD_ULOGIC_VECTOR'("111111111111110")); +MQQ160:LRU_SET_RESET_VEC_PT(60) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) + ) , STD_ULOGIC_VECTOR'("11111111111110")); +MQQ161:LRU_SET_RESET_VEC_PT(61) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(13) ) , STD_ULOGIC_VECTOR'("1111111111110")); +MQQ162:LRU_SET_RESET_VEC_PT(62) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) ) , STD_ULOGIC_VECTOR'("1111111111110")); +MQQ163:LRU_SET_RESET_VEC_PT(63) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) + ) , STD_ULOGIC_VECTOR'("111111111110")); +MQQ164:LRU_SET_RESET_VEC_PT(64) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(11) ) , STD_ULOGIC_VECTOR'("111111110")); +MQQ165:LRU_SET_RESET_VEC_PT(65) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) ) , STD_ULOGIC_VECTOR'("11111111110")); +MQQ166:LRU_SET_RESET_VEC_PT(66) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) + ) , STD_ULOGIC_VECTOR'("1111111110")); +MQQ167:LRU_SET_RESET_VEC_PT(67) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(9) ) , STD_ULOGIC_VECTOR'("111111110")); +MQQ168:LRU_SET_RESET_VEC_PT(68) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) ) , STD_ULOGIC_VECTOR'("111111110")); +MQQ169:LRU_SET_RESET_VEC_PT(69) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) + ) , STD_ULOGIC_VECTOR'("11111110")); +MQQ170:LRU_SET_RESET_VEC_PT(70) <= + Eq(( ENTRY_VALID_WATERMARKED(7) ) , STD_ULOGIC'('0')); +MQQ171:LRU_SET_RESET_VEC_PT(71) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) ) , STD_ULOGIC_VECTOR'("1111110")); +MQQ172:LRU_SET_RESET_VEC_PT(72) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) + ) , STD_ULOGIC_VECTOR'("111110")); +MQQ173:LRU_SET_RESET_VEC_PT(73) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(5) ) , STD_ULOGIC_VECTOR'("11110")); +MQQ174:LRU_SET_RESET_VEC_PT(74) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) ) , STD_ULOGIC_VECTOR'("11110")); +MQQ175:LRU_SET_RESET_VEC_PT(75) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) + ) , STD_ULOGIC_VECTOR'("1110")); +MQQ176:LRU_SET_RESET_VEC_PT(76) <= + Eq(( ENTRY_VALID_WATERMARKED(3) ) , STD_ULOGIC'('0')); +MQQ177:LRU_SET_RESET_VEC_PT(77) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) ) , STD_ULOGIC_VECTOR'("110")); +MQQ178:LRU_SET_RESET_VEC_PT(78) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) + ) , STD_ULOGIC_VECTOR'("10")); +MQQ179:LRU_SET_RESET_VEC_PT(79) <= + Eq(( ENTRY_VALID_WATERMARKED(1) ) , STD_ULOGIC'('0')); +MQQ180:LRU_SET_RESET_VEC_PT(80) <= + Eq(( ENTRY_VALID_WATERMARKED(0) ) , STD_ULOGIC'('0')); +-- Table LRU_SET_RESET_VEC Signal Assignments for Outputs +MQQ181:LRU_RESET_VEC(1) <= + (LRU_SET_RESET_VEC_PT(1) OR LRU_SET_RESET_VEC_PT(2) + OR LRU_SET_RESET_VEC_PT(4) OR LRU_SET_RESET_VEC_PT(6) + OR LRU_SET_RESET_VEC_PT(7) OR LRU_SET_RESET_VEC_PT(9) + OR LRU_SET_RESET_VEC_PT(10) OR LRU_SET_RESET_VEC_PT(13) + OR LRU_SET_RESET_VEC_PT(57) OR LRU_SET_RESET_VEC_PT(70) + OR LRU_SET_RESET_VEC_PT(71) OR LRU_SET_RESET_VEC_PT(73) + OR LRU_SET_RESET_VEC_PT(74) OR LRU_SET_RESET_VEC_PT(76) + OR LRU_SET_RESET_VEC_PT(77) OR LRU_SET_RESET_VEC_PT(79) + OR LRU_SET_RESET_VEC_PT(80)); +MQQ182:LRU_RESET_VEC(2) <= + (LRU_SET_RESET_VEC_PT(14) OR LRU_SET_RESET_VEC_PT(16) + OR LRU_SET_RESET_VEC_PT(17) OR LRU_SET_RESET_VEC_PT(20) + OR LRU_SET_RESET_VEC_PT(55) OR LRU_SET_RESET_VEC_PT(76) + OR LRU_SET_RESET_VEC_PT(77) OR LRU_SET_RESET_VEC_PT(79) + OR LRU_SET_RESET_VEC_PT(80)); +MQQ183:LRU_RESET_VEC(3) <= + (LRU_SET_RESET_VEC_PT(1) OR LRU_SET_RESET_VEC_PT(2) + OR LRU_SET_RESET_VEC_PT(4) OR LRU_SET_RESET_VEC_PT(6) + OR LRU_SET_RESET_VEC_PT(53) OR LRU_SET_RESET_VEC_PT(64) + OR LRU_SET_RESET_VEC_PT(65) OR LRU_SET_RESET_VEC_PT(67) + OR LRU_SET_RESET_VEC_PT(68)); +MQQ184:LRU_RESET_VEC(4) <= + (LRU_SET_RESET_VEC_PT(21) OR LRU_SET_RESET_VEC_PT(24) + OR LRU_SET_RESET_VEC_PT(51) OR LRU_SET_RESET_VEC_PT(79) + OR LRU_SET_RESET_VEC_PT(80)); +MQQ185:LRU_RESET_VEC(5) <= + (LRU_SET_RESET_VEC_PT(14) OR LRU_SET_RESET_VEC_PT(16) + OR LRU_SET_RESET_VEC_PT(49) OR LRU_SET_RESET_VEC_PT(73) + OR LRU_SET_RESET_VEC_PT(74)); +MQQ186:LRU_RESET_VEC(6) <= + (LRU_SET_RESET_VEC_PT(7) OR LRU_SET_RESET_VEC_PT(9) + OR LRU_SET_RESET_VEC_PT(47) OR LRU_SET_RESET_VEC_PT(67) + OR LRU_SET_RESET_VEC_PT(68)); +MQQ187:LRU_RESET_VEC(7) <= + (LRU_SET_RESET_VEC_PT(1) OR LRU_SET_RESET_VEC_PT(2) + OR LRU_SET_RESET_VEC_PT(45) OR LRU_SET_RESET_VEC_PT(61) + OR LRU_SET_RESET_VEC_PT(62)); +MQQ188:LRU_RESET_VEC(8) <= + (LRU_SET_RESET_VEC_PT(25) OR LRU_SET_RESET_VEC_PT(43) + OR LRU_SET_RESET_VEC_PT(80)); +MQQ189:LRU_RESET_VEC(9) <= + (LRU_SET_RESET_VEC_PT(21) OR LRU_SET_RESET_VEC_PT(41) + OR LRU_SET_RESET_VEC_PT(77)); +MQQ190:LRU_RESET_VEC(10) <= + (LRU_SET_RESET_VEC_PT(17) OR LRU_SET_RESET_VEC_PT(39) + OR LRU_SET_RESET_VEC_PT(74)); +MQQ191:LRU_RESET_VEC(11) <= + (LRU_SET_RESET_VEC_PT(14) OR LRU_SET_RESET_VEC_PT(37) + OR LRU_SET_RESET_VEC_PT(71)); +MQQ192:LRU_RESET_VEC(12) <= + (LRU_SET_RESET_VEC_PT(10) OR LRU_SET_RESET_VEC_PT(35) + OR LRU_SET_RESET_VEC_PT(68)); +MQQ193:LRU_RESET_VEC(13) <= + (LRU_SET_RESET_VEC_PT(7) OR LRU_SET_RESET_VEC_PT(33) + OR LRU_SET_RESET_VEC_PT(65)); +MQQ194:LRU_RESET_VEC(14) <= + (LRU_SET_RESET_VEC_PT(4) OR LRU_SET_RESET_VEC_PT(31) + OR LRU_SET_RESET_VEC_PT(62)); +MQQ195:LRU_RESET_VEC(15) <= + (LRU_SET_RESET_VEC_PT(1) OR LRU_SET_RESET_VEC_PT(29) + OR LRU_SET_RESET_VEC_PT(59)); +MQQ196:LRU_SET_VEC(1) <= + (LRU_SET_RESET_VEC_PT(15) OR LRU_SET_RESET_VEC_PT(16) + OR LRU_SET_RESET_VEC_PT(18) OR LRU_SET_RESET_VEC_PT(19) + OR LRU_SET_RESET_VEC_PT(22) OR LRU_SET_RESET_VEC_PT(23) + OR LRU_SET_RESET_VEC_PT(26) OR LRU_SET_RESET_VEC_PT(27) + OR LRU_SET_RESET_VEC_PT(56) OR LRU_SET_RESET_VEC_PT(58) + OR LRU_SET_RESET_VEC_PT(59) OR LRU_SET_RESET_VEC_PT(60) + OR LRU_SET_RESET_VEC_PT(62) OR LRU_SET_RESET_VEC_PT(63) + OR LRU_SET_RESET_VEC_PT(65) OR LRU_SET_RESET_VEC_PT(66) + OR LRU_SET_RESET_VEC_PT(68)); +MQQ197:LRU_SET_VEC(2) <= + (LRU_SET_RESET_VEC_PT(22) OR LRU_SET_RESET_VEC_PT(23) + OR LRU_SET_RESET_VEC_PT(26) OR LRU_SET_RESET_VEC_PT(27) + OR LRU_SET_RESET_VEC_PT(54) OR LRU_SET_RESET_VEC_PT(69) + OR LRU_SET_RESET_VEC_PT(71) OR LRU_SET_RESET_VEC_PT(72) + OR LRU_SET_RESET_VEC_PT(74)); +MQQ198:LRU_SET_VEC(3) <= + (LRU_SET_RESET_VEC_PT(8) OR LRU_SET_RESET_VEC_PT(9) + OR LRU_SET_RESET_VEC_PT(11) OR LRU_SET_RESET_VEC_PT(12) + OR LRU_SET_RESET_VEC_PT(52) OR LRU_SET_RESET_VEC_PT(58) + OR LRU_SET_RESET_VEC_PT(59) OR LRU_SET_RESET_VEC_PT(60) + OR LRU_SET_RESET_VEC_PT(62)); +MQQ199:LRU_SET_VEC(4) <= + (LRU_SET_RESET_VEC_PT(26) OR LRU_SET_RESET_VEC_PT(27) + OR LRU_SET_RESET_VEC_PT(50) OR LRU_SET_RESET_VEC_PT(75) + OR LRU_SET_RESET_VEC_PT(77)); +MQQ200:LRU_SET_VEC(5) <= + (LRU_SET_RESET_VEC_PT(18) OR LRU_SET_RESET_VEC_PT(19) + OR LRU_SET_RESET_VEC_PT(48) OR LRU_SET_RESET_VEC_PT(69) + OR LRU_SET_RESET_VEC_PT(71)); +MQQ201:LRU_SET_VEC(6) <= + (LRU_SET_RESET_VEC_PT(11) OR LRU_SET_RESET_VEC_PT(12) + OR LRU_SET_RESET_VEC_PT(46) OR LRU_SET_RESET_VEC_PT(63) + OR LRU_SET_RESET_VEC_PT(65)); +MQQ202:LRU_SET_VEC(7) <= + (LRU_SET_RESET_VEC_PT(5) OR LRU_SET_RESET_VEC_PT(6) + OR LRU_SET_RESET_VEC_PT(44) OR LRU_SET_RESET_VEC_PT(58) + OR LRU_SET_RESET_VEC_PT(59)); +MQQ203:LRU_SET_VEC(8) <= + (LRU_SET_RESET_VEC_PT(27) OR LRU_SET_RESET_VEC_PT(42) + OR LRU_SET_RESET_VEC_PT(78)); +MQQ204:LRU_SET_VEC(9) <= + (LRU_SET_RESET_VEC_PT(23) OR LRU_SET_RESET_VEC_PT(40) + OR LRU_SET_RESET_VEC_PT(75)); +MQQ205:LRU_SET_VEC(10) <= + (LRU_SET_RESET_VEC_PT(19) OR LRU_SET_RESET_VEC_PT(38) + OR LRU_SET_RESET_VEC_PT(72)); +MQQ206:LRU_SET_VEC(11) <= + (LRU_SET_RESET_VEC_PT(16) OR LRU_SET_RESET_VEC_PT(36) + OR LRU_SET_RESET_VEC_PT(69)); +MQQ207:LRU_SET_VEC(12) <= + (LRU_SET_RESET_VEC_PT(12) OR LRU_SET_RESET_VEC_PT(34) + OR LRU_SET_RESET_VEC_PT(66)); +MQQ208:LRU_SET_VEC(13) <= + (LRU_SET_RESET_VEC_PT(9) OR LRU_SET_RESET_VEC_PT(32) + OR LRU_SET_RESET_VEC_PT(63)); +MQQ209:LRU_SET_VEC(14) <= + (LRU_SET_RESET_VEC_PT(6) OR LRU_SET_RESET_VEC_PT(30) + OR LRU_SET_RESET_VEC_PT(60)); +MQQ210:LRU_SET_VEC(15) <= + (LRU_SET_RESET_VEC_PT(3) OR LRU_SET_RESET_VEC_PT(28) + OR LRU_SET_RESET_VEC_PT(58)); + +-- Encoder for the LRU selected entry +-- +-- Final Table Listing +-- *INPUTS*==========================*OUTPUTS*==========* +-- | | | +-- | mmucr1_q | lru_way_encode | +-- | | lru_eff | | | +-- | | | | | | +-- | | | | | | +-- | | | 111111 | | | +-- | 012345678 123456789012345 | 0123 | +-- *TYPE*============================+==================+ +-- | PPPPPPPPP PPPPPPPPPPPPPPP | PPPP | +-- *POLARITY*----------------------->| ++++ | +-- *PHASE*-------------------------->| TTTT | +-- *OPTIMIZE*----------------------->| AAAA | +-- *TERMS*===========================+==================+ +-- 1 | --------- 1-1---1-------1 | ...1 | +-- 2 | --------- 1-1---0------1- | ...1 | +-- 3 | --------- 1-0--1------1-- | ...1 | +-- 4 | --------- 1-0--0-----1--- | ...1 | +-- 5 | --------- 01--1-----1---- | ...1 | +-- 6 | --------- 01--0----1----- | ...1 | +-- 7 | --------- 00-1----1------ | ...1 | +-- 8 | --------- 00-0---1------- | ...1 | +-- 9 | --------- 1-1---1-------- | ..1. | +-- 10 | --------- 1-0--1--------- | ..1. | +-- 11 | --------- 01--1---------- | ..1. | +-- 12 | --------- 00-1----------- | ..1. | +-- 13 | --------- 1-1------------ | .1.. | +-- 14 | --------- 01------------- | .1.. | +-- 15 | --------- 1-------------- | 1... | +-- *====================================================* +-- +-- Table LRU_WAY_ENCODE Signal Assignments for Product Terms +MQQ211:LRU_WAY_ENCODE_PT(1) <= + Eq(( LRU_EFF(1) & LRU_EFF(3) & + LRU_EFF(7) & LRU_EFF(15) + ) , STD_ULOGIC_VECTOR'("1111")); +MQQ212:LRU_WAY_ENCODE_PT(2) <= + Eq(( LRU_EFF(1) & LRU_EFF(3) & + LRU_EFF(7) & LRU_EFF(14) + ) , STD_ULOGIC_VECTOR'("1101")); +MQQ213:LRU_WAY_ENCODE_PT(3) <= + Eq(( LRU_EFF(1) & LRU_EFF(3) & + LRU_EFF(6) & LRU_EFF(13) + ) , STD_ULOGIC_VECTOR'("1011")); +MQQ214:LRU_WAY_ENCODE_PT(4) <= + Eq(( LRU_EFF(1) & LRU_EFF(3) & + LRU_EFF(6) & LRU_EFF(12) + ) , STD_ULOGIC_VECTOR'("1001")); +MQQ215:LRU_WAY_ENCODE_PT(5) <= + Eq(( LRU_EFF(1) & LRU_EFF(2) & + LRU_EFF(5) & LRU_EFF(11) + ) , STD_ULOGIC_VECTOR'("0111")); +MQQ216:LRU_WAY_ENCODE_PT(6) <= + Eq(( LRU_EFF(1) & LRU_EFF(2) & + LRU_EFF(5) & LRU_EFF(10) + ) , STD_ULOGIC_VECTOR'("0101")); +MQQ217:LRU_WAY_ENCODE_PT(7) <= + Eq(( LRU_EFF(1) & LRU_EFF(2) & + LRU_EFF(4) & LRU_EFF(9) + ) , STD_ULOGIC_VECTOR'("0011")); +MQQ218:LRU_WAY_ENCODE_PT(8) <= + Eq(( LRU_EFF(1) & LRU_EFF(2) & + LRU_EFF(4) & LRU_EFF(8) + ) , STD_ULOGIC_VECTOR'("0001")); +MQQ219:LRU_WAY_ENCODE_PT(9) <= + Eq(( LRU_EFF(1) & LRU_EFF(3) & + LRU_EFF(7) ) , STD_ULOGIC_VECTOR'("111")); +MQQ220:LRU_WAY_ENCODE_PT(10) <= + Eq(( LRU_EFF(1) & LRU_EFF(3) & + LRU_EFF(6) ) , STD_ULOGIC_VECTOR'("101")); +MQQ221:LRU_WAY_ENCODE_PT(11) <= + Eq(( LRU_EFF(1) & LRU_EFF(2) & + LRU_EFF(5) ) , STD_ULOGIC_VECTOR'("011")); +MQQ222:LRU_WAY_ENCODE_PT(12) <= + Eq(( LRU_EFF(1) & LRU_EFF(2) & + LRU_EFF(4) ) , STD_ULOGIC_VECTOR'("001")); +MQQ223:LRU_WAY_ENCODE_PT(13) <= + Eq(( LRU_EFF(1) & LRU_EFF(3) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ224:LRU_WAY_ENCODE_PT(14) <= + Eq(( LRU_EFF(1) & LRU_EFF(2) + ) , STD_ULOGIC_VECTOR'("01")); +MQQ225:LRU_WAY_ENCODE_PT(15) <= + Eq(( LRU_EFF(1) ) , STD_ULOGIC'('1')); +-- Table LRU_WAY_ENCODE Signal Assignments for Outputs +MQQ226:LRU_WAY_ENCODE(0) <= + (LRU_WAY_ENCODE_PT(15)); +MQQ227:LRU_WAY_ENCODE(1) <= + (LRU_WAY_ENCODE_PT(13) OR LRU_WAY_ENCODE_PT(14) + ); +MQQ228:LRU_WAY_ENCODE(2) <= + (LRU_WAY_ENCODE_PT(9) OR LRU_WAY_ENCODE_PT(10) + OR LRU_WAY_ENCODE_PT(11) OR LRU_WAY_ENCODE_PT(12) + ); +MQQ229:LRU_WAY_ENCODE(3) <= + (LRU_WAY_ENCODE_PT(1) OR LRU_WAY_ENCODE_PT(2) + OR LRU_WAY_ENCODE_PT(3) OR LRU_WAY_ENCODE_PT(4) + OR LRU_WAY_ENCODE_PT(5) OR LRU_WAY_ENCODE_PT(6) + OR LRU_WAY_ENCODE_PT(7) OR LRU_WAY_ENCODE_PT(8) + ); + +-- power-on reset sequencer to load initial erat entries +Por_Sequencer: PROCESS (por_seq_q, init_alias, bcfg_q(0 to 106)) +BEGIN +por_wr_cam_val <= (others => '0'); +por_wr_array_val <= (others => '0'); +por_wr_cam_data <= (others => '0'); +por_wr_array_data <= (others => '0'); +por_wr_entry <= (others => '0'); +CASE por_seq_q IS + WHEN PorSeq_Idle => + por_wr_cam_val <= (others => '0'); por_wr_array_val <= (others => '0'); + por_hold_req <= (others => init_alias); + + if init_alias ='1' then + por_seq_d <= PorSeq_Stg1; + else + por_seq_d <= PorSeq_Idle; + end if; + WHEN PorSeq_Stg1 => + por_wr_cam_val <= (others => '0'); por_wr_array_val <= (others => '0'); + por_seq_d <= PorSeq_Stg2; por_hold_req <= (others => '1'); + + WHEN PorSeq_Stg2 => + por_wr_cam_val <= (others => '1'); por_wr_array_val <= (others => '1'); + por_wr_entry <= Por_Wr_Entry_Num1; + por_wr_cam_data <= bcfg_q(0 to 51) & Por_Wr_Cam_Data1(52 to 83); +-- 16x143 version, 42b RA +-- wr_array_data +-- 0:29 - RPN +-- 30:31 - R,C +-- 32:33 - WLC +-- 34 - ResvAttr +-- 35 - VF +-- 36:39 - U0-U3 +-- 40:44 - WIMGE +-- 45:46 - UX,SX +-- 47:48 - UW,SW +-- 49:50 - UR,SR +-- 51:60 - CAM parity +-- 61:67 - Array parity + por_wr_array_data <= bcfg_q(52 to 81) & Por_Wr_Array_Data1(30 to 35) & bcfg_q(82 to 85) & + Por_Wr_Array_Data1(40 to 43) & bcfg_q(86) & Por_Wr_Array_Data1(45 to 67); + por_hold_req <= (others => '1'); + por_seq_d <= PorSeq_Stg3; + + WHEN PorSeq_Stg3 => + por_wr_cam_val <= (others => '0'); por_wr_array_val <= (others => '0'); + por_hold_req <= (others => '1'); + por_seq_d <= PorSeq_Stg4; + + WHEN PorSeq_Stg4 => + por_wr_cam_val <= (others => '1'); por_wr_array_val <= (others => '1'); + por_wr_entry <= Por_Wr_Entry_Num2; + por_wr_cam_data <= Por_Wr_Cam_Data2; + por_wr_array_data <= bcfg_q(52 to 61) & bcfg_q(87 to 106) & Por_Wr_Array_Data2(30 to 35) & bcfg_q(82 to 85) & + Por_Wr_Array_Data2(40 to 43) & bcfg_q(86) & Por_Wr_Array_Data2(45 to 67); + por_hold_req <= (others => '1'); + por_seq_d <= PorSeq_Stg5; + + WHEN PorSeq_Stg5 => + por_wr_cam_val <= (others => '0'); por_wr_array_val <= (others => '0'); + por_hold_req <= (others => '1'); + por_seq_d <= PorSeq_Stg6; + + WHEN PorSeq_Stg6 => + por_wr_cam_val <= (others => '0'); por_wr_array_val <= (others => '0'); + por_hold_req <= (others => '0'); + por_seq_d <= PorSeq_Stg7; + + WHEN PorSeq_Stg7 => + por_wr_cam_val <= (others => '0'); por_wr_array_val <= (others => '0'); + por_hold_req <= (others => '0'); + + if init_alias ='0' then + por_seq_d <= PorSeq_Idle; + else + por_seq_d <= PorSeq_Stg7; + end if; + + WHEN OTHERS => + por_seq_d <= PorSeq_Idle; + END CASE; +END PROCESS Por_Sequencer; +-- page size 4b to 3b swizzles for cam write +cam_pgsize(0 TO 2) <= (CAM_PgSize_1GB and (0 to 2 => Eq(ex6_data_in_q(56 to 59),WS0_PgSize_1GB))) + or (CAM_PgSize_16MB and (0 to 2 => Eq(ex6_data_in_q(56 to 59),WS0_PgSize_16MB))) + or (CAM_PgSize_1MB and (0 to 2 => Eq(ex6_data_in_q(56 to 59),WS0_PgSize_1MB))) + or (CAM_PgSize_64KB and (0 to 2 => Eq(ex6_data_in_q(56 to 59),WS0_PgSize_64KB))) + or (CAM_PgSize_4KB and (0 to 2 => not(Eq(ex6_data_in_q(56 to 59),WS0_PgSize_1GB) or + Eq(ex6_data_in_q(56 to 59),WS0_PgSize_16MB) or + Eq(ex6_data_in_q(56 to 59),WS0_PgSize_1MB) or + Eq(ex6_data_in_q(56 to 59),WS0_PgSize_64KB)))); +-- page size 3b to 4b swizzles for cam read +ws0_pgsize(0 TO 3) <= (WS0_PgSize_1GB and (0 to 3 => Eq(rd_cam_data(53 to 55),CAM_PgSize_1GB))) + or (WS0_PgSize_16MB and (0 to 3 => Eq(rd_cam_data(53 to 55),CAM_PgSize_16MB))) + or (WS0_PgSize_1MB and (0 to 3 => Eq(rd_cam_data(53 to 55),CAM_PgSize_1MB))) + or (WS0_PgSize_64KB and (0 to 3 => Eq(rd_cam_data(53 to 55),CAM_PgSize_64KB))) + or (WS0_PgSize_4KB and (0 to 3 => Eq(rd_cam_data(53 to 55),CAM_PgSize_4KB))); +-- CAM control signal assignments +-- ttype: eratre & eratwe & eratsx & erativax; +-- mmucr1_q: 0-IRRE, 1-REE, 2-CEE, 3-csync, 4-isync, 5:6-IPEI, 7:8-ICTID/ITTID +rd_val <= or_reduce(ex2_valid_q) and ex2_ttype_q(0) and Eq(ex2_tlbsel_q, TlbSel_IErat); +rw_entry <= ( por_wr_entry and (0 to 3 => or_reduce(por_seq_q)) ) + or ( eptr_q and (0 to 3 => (or_reduce(tlb_rel_val_q(0 to 3)) and tlb_rel_val_q(4) and mmucr1_q(0))) ) + or ( lru_way_encode and (0 to 3 => (or_reduce(tlb_rel_val_q(0 to 3)) and tlb_rel_val_q(4) and not mmucr1_q(0))) ) + or ( eptr_q and (0 to 3 => (or_reduce(ex6_valid_q) and ex6_ttype_q(1) and Eq(ex6_tlbsel_q, TlbSel_IErat) and not tlb_rel_val_q(4) and mmucr1_q(0))) ) + or ( ex6_ra_entry_q and (0 to 3 => (or_reduce(ex6_valid_q) and ex6_ttype_q(1) and Eq(ex6_tlbsel_q, TlbSel_IErat) and not tlb_rel_val_q(4) and not mmucr1_q(0))) ) + or ( ex2_ra_entry_q and (0 to 3 => (or_reduce(ex2_valid_q) and ex2_ttype_q(0) and not(or_reduce(ex6_valid_q) and ex6_ttype_q(1) and Eq(ex6_tlbsel_q, TlbSel_IErat)) and not tlb_rel_val_q(4))) ); +-- Write Port +wr_cam_val <= por_wr_cam_val when por_seq_q/=PorSeq_Idle + else (others => '0') when (ex6_valid_q/="0000" and ex6_ttype_q(4 to 5)/="00") + else (others => tlb_rel_data_q(eratpos_wren)) when (tlb_rel_val_q(0 to 3)/="0000" and tlb_rel_val_q(4)='1') + else (others => '1') when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' and ex6_ws_q="00" and ex6_tlbsel_q=TlbSel_IErat) + else (others => '0'); +-- write port act pin +wr_val_early <= or_reduce(por_seq_q) or + or_reduce(tlb_req_inprogress_q) or + (or_reduce(ex5_valid_q) and ex5_ttype_q(1) and Eq(ex5_ws_q,"00") and Eq(ex5_tlbsel_q,TlbSel_IErat)) or + (or_reduce(ex6_valid_q) and ex6_ttype_q(1) and Eq(ex6_ws_q,"00") and Eq(ex6_tlbsel_q,TlbSel_IErat)); +-- tlb_low_data +-- 0:51 - EPN +-- 52:55 - SIZE (4b) +-- 56:59 - ThdID +-- 60:61 - Class +-- 62 - ExtClass +-- 63 - TID_NZ +-- 64:65 - reserved (2b) +-- 66:73 - 8b for LPID +-- 74:83 - parity 10bits +-- wr_ws0_data (LO) +-- 0:51 - EPN +-- 52:53 - Class +-- 54 - V +-- 55 - X +-- 56:59 - SIZE +-- 60:63 - ThdID +-- wr_cam_data +-- 0:51 - EPN +-- 52 - X +-- 53:55 - SIZE +-- 56 - V +-- 57:60 - ThdID +-- 61:62 - Class +-- 63:64 - ExtClass | TID_NZ +-- 65 - TGS +-- 66 - TS +-- 67:74 - TID +-- 75:78 - epn_cmpmasks: 34_39, 40_43, 44_47, 48_51 +-- 79:82 - xbit_cmpmasks: 34_51, 40_51, 44_51, 48_51 +-- 83 - parity for 75:82 +----------- this is what the erat expects on reload bus +-- 0:51 - EPN +-- 52 - X +-- 53:55 - SIZE +-- 56 - V +-- 57:60 - ThdID +-- 61:62 - Class +-- 63:64 - ExtClass | TID_NZ +-- 65 - write enable +-- 0:3 66:69 - reserved RPN +-- 4:33 70:99 - RPN +-- 34:35 100:101 - R,C +-- 36 102 - reserved +-- 37:38 103:104 - WLC +-- 39 105 - ResvAttr +-- 40 106 - VF +-- 41:44 107:110 - U0-U3 +-- 45:49 111:115 - WIMGE +-- 50:51 116:117 - UX,SX +-- 52:53 118:119 - UW,SW +-- 54:55 120:121 - UR,SR +-- 56 122 - GS +-- 57 123 - TS +-- 58:65 124:131 - TID lsbs +gen64_wr_cam_data: if rs_data_width = 64 generate +wr_cam_data <= por_wr_cam_data when por_seq_q/=PorSeq_Idle + else (tlb_rel_data_q(0 to 64) & tlb_rel_data_q(122 to 131) & + tlb_rel_cmpmask(0 to 3) & tlb_rel_xbitmask(0 to 3) & tlb_rel_maskpar ) + when (tlb_rel_val_q(0 to 3)/="0000" and tlb_rel_val_q(4)='1') + else ( (ex6_data_in_q(0 to 31) and (0 to 31 => ex6_state_q(3))) & ex6_data_in_q(32 to 51) & ex6_data_in_q(55) & + cam_pgsize(0 to 2) & ex6_data_in_q(54) & ex6_data_in_q(60 to 63) & ex6_data_in_q(52 to 53) & + ex6_extclass_q & ex6_state_q(1 to 2) & ex6_pid_q(pid_width-8 to pid_width-1) & + ex6_data_cmpmask(0 to 3) & ex6_data_xbitmask(0 to 3) & ex6_data_maskpar ) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' and ex6_ws_q="00") + else (others => '0'); +end generate gen64_wr_cam_data; +gen32_wr_cam_data: if rs_data_width = 32 generate +wr_cam_data <= por_wr_cam_data when por_seq_q/=PorSeq_Idle + else (tlb_rel_data_q(0 to 64) & tlb_rel_data_q(122 to 131) & + tlb_rel_cmpmask(0 to 3) & tlb_rel_xbitmask(0 to 3) & tlb_rel_maskpar ) + when (tlb_rel_val_q(0 to 3)/="0000" and tlb_rel_val_q(4)='1') + else ((0 to 31 => '0') & ex6_data_in_q(32 to 51) & ex6_data_in_q(55) & cam_pgsize(0 to 2) & ex6_data_in_q(54) & + ex6_data_in_q(60 to 63) & ex6_data_in_q(52 to 53) & + ex6_extclass_q & ex6_state_q(1 to 2) & ex6_pid_q(pid_width-8 to pid_width-1) & + ex6_data_cmpmask(0 to 3) & ex6_data_xbitmask(0 to 3) & ex6_data_maskpar ) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' and ex6_ws_q="00") + else (others => '0'); +end generate gen32_wr_cam_data; +-- cmpmask(0) (1) (2) (3) xbitmask(0) (1) (2) (3) +-- xbit pgsize 34_39 40_43 44_47 48_51 34_39 40_43 44_47 48_51 size +-- 0 001 1 1 1 1 0 0 0 0 4K +-- 0 011 1 1 1 0 0 0 0 0 64K +-- 0 101 1 1 0 0 0 0 0 0 1M +-- 0 111 1 0 0 0 0 0 0 0 16M +-- 0 110 0 0 0 0 0 0 0 0 1G +-- 1 001 1 1 1 1 0 0 0 0 4K +-- 1 011 1 1 1 0 0 0 0 1 64K +-- 1 101 1 1 0 0 0 0 1 0 1M +-- 1 111 1 0 0 0 0 1 0 0 16M +-- 1 110 0 0 0 0 1 0 0 0 1G +-- Encoder for the cam compare mask bits write data +-- +-- Final Table Listing +-- *INPUTS*==================*OUTPUTS*===================================* +-- | | | +-- | tlb_rel_data_q | tlb_rel_cmpmask | +-- | | ex6_data_in_q | | tlb_rel_xbitmask | +-- | | | | | | tlb_rel_maskpar | +-- | | | | | | | ex6_data_cmpmask | +-- | | | | | | | | ex6_data_xbitmask | +-- | | | | | | | | | ex6_data_maskpar | +-- | | | | | | | | | | | +-- | 5555 55555 | | | | | | | | +-- | 2345 56789 | 0123 0123 | 0123 0123 | | +-- *TYPE*====================+===========================================+ +-- | PPPP PPPPP | PPPP PPPP P PPPP PPPP P | +-- *POLARITY*--------------->| ++++ ++++ + ++++ ++++ + | +-- *PHASE*------------------>| TTTT TTTT T TTTT TTTT T | +-- *OPTIMIZE*--------------->| AAAA AAAA A AAAA AAAA A | +-- *TERMS*===================+===========================================+ +-- 1 | ---- 11010 | .... .... . .... 1... 1 | +-- 2 | ---- -0--0 | .... .... . 1111 .... . | +-- 3 | ---- 10101 | .... .... . .... ..1. 1 | +-- 4 | ---- 10011 | .... .... . 1... ...1 . | +-- 5 | ---- 10111 | .... .... . 1... .1.. . | +-- 6 | ---- 00-11 | .... .... . 1... .... 1 | +-- 7 | ---- -1--1 | .... .... . 1111 .... . | +-- 8 | ---- --00- | .... .... . ..11 .... . | +-- 9 | ---- ---0- | .... .... . 11.. .... . | +-- 10 | ---- -00-- | .... .... . .11. .... . | +-- 11 | ---- -11-- | .... .... . 1111 .... . | +-- 12 | 1--0 ----- | .... 1... 1 .... .... . | +-- 13 | 1111 ----- | 1... .1.. . .... .... . | +-- 14 | 0-11 ----- | 1... .... 1 .... .... . | +-- 15 | -00- ----- | ...1 .... . .... .... . | +-- 16 | 110- ----- | .... ..1. 1 .... .... . | +-- 17 | --0- ----- | 11.. .... . .... .... . | +-- 18 | 101- ----- | 1... ...1 . .... .... . | +-- 19 | -0-- ----- | .11. .... . .... .... . | +-- *=====================================================================* +-- +-- Table CAM_MASK_BITS Signal Assignments for Product Terms +MQQ230:CAM_MASK_BITS_PT(1) <= + Eq(( EX6_DATA_IN_Q(55) & EX6_DATA_IN_Q(56) & + EX6_DATA_IN_Q(57) & EX6_DATA_IN_Q(58) & + EX6_DATA_IN_Q(59) ) , STD_ULOGIC_VECTOR'("11010")); +MQQ231:CAM_MASK_BITS_PT(2) <= + Eq(( EX6_DATA_IN_Q(56) & EX6_DATA_IN_Q(59) + ) , STD_ULOGIC_VECTOR'("00")); +MQQ232:CAM_MASK_BITS_PT(3) <= + Eq(( EX6_DATA_IN_Q(55) & EX6_DATA_IN_Q(56) & + EX6_DATA_IN_Q(57) & EX6_DATA_IN_Q(58) & + EX6_DATA_IN_Q(59) ) , STD_ULOGIC_VECTOR'("10101")); +MQQ233:CAM_MASK_BITS_PT(4) <= + Eq(( EX6_DATA_IN_Q(55) & EX6_DATA_IN_Q(56) & + EX6_DATA_IN_Q(57) & EX6_DATA_IN_Q(58) & + EX6_DATA_IN_Q(59) ) , STD_ULOGIC_VECTOR'("10011")); +MQQ234:CAM_MASK_BITS_PT(5) <= + Eq(( EX6_DATA_IN_Q(55) & EX6_DATA_IN_Q(56) & + EX6_DATA_IN_Q(57) & EX6_DATA_IN_Q(58) & + EX6_DATA_IN_Q(59) ) , STD_ULOGIC_VECTOR'("10111")); +MQQ235:CAM_MASK_BITS_PT(6) <= + Eq(( EX6_DATA_IN_Q(55) & EX6_DATA_IN_Q(56) & + EX6_DATA_IN_Q(58) & EX6_DATA_IN_Q(59) + ) , STD_ULOGIC_VECTOR'("0011")); +MQQ236:CAM_MASK_BITS_PT(7) <= + Eq(( EX6_DATA_IN_Q(56) & EX6_DATA_IN_Q(59) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ237:CAM_MASK_BITS_PT(8) <= + Eq(( EX6_DATA_IN_Q(57) & EX6_DATA_IN_Q(58) + ) , STD_ULOGIC_VECTOR'("00")); +MQQ238:CAM_MASK_BITS_PT(9) <= + Eq(( EX6_DATA_IN_Q(58) ) , STD_ULOGIC'('0')); +MQQ239:CAM_MASK_BITS_PT(10) <= + Eq(( EX6_DATA_IN_Q(56) & EX6_DATA_IN_Q(57) + ) , STD_ULOGIC_VECTOR'("00")); +MQQ240:CAM_MASK_BITS_PT(11) <= + Eq(( EX6_DATA_IN_Q(56) & EX6_DATA_IN_Q(57) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ241:CAM_MASK_BITS_PT(12) <= + Eq(( TLB_REL_DATA_Q(52) & TLB_REL_DATA_Q(55) + ) , STD_ULOGIC_VECTOR'("10")); +MQQ242:CAM_MASK_BITS_PT(13) <= + Eq(( TLB_REL_DATA_Q(52) & TLB_REL_DATA_Q(53) & + TLB_REL_DATA_Q(54) & TLB_REL_DATA_Q(55) + ) , STD_ULOGIC_VECTOR'("1111")); +MQQ243:CAM_MASK_BITS_PT(14) <= + Eq(( TLB_REL_DATA_Q(52) & TLB_REL_DATA_Q(54) & + TLB_REL_DATA_Q(55) ) , STD_ULOGIC_VECTOR'("011")); +MQQ244:CAM_MASK_BITS_PT(15) <= + Eq(( TLB_REL_DATA_Q(53) & TLB_REL_DATA_Q(54) + ) , STD_ULOGIC_VECTOR'("00")); +MQQ245:CAM_MASK_BITS_PT(16) <= + Eq(( TLB_REL_DATA_Q(52) & TLB_REL_DATA_Q(53) & + TLB_REL_DATA_Q(54) ) , STD_ULOGIC_VECTOR'("110")); +MQQ246:CAM_MASK_BITS_PT(17) <= + Eq(( TLB_REL_DATA_Q(54) ) , STD_ULOGIC'('0')); +MQQ247:CAM_MASK_BITS_PT(18) <= + Eq(( TLB_REL_DATA_Q(52) & TLB_REL_DATA_Q(53) & + TLB_REL_DATA_Q(54) ) , STD_ULOGIC_VECTOR'("101")); +MQQ248:CAM_MASK_BITS_PT(19) <= + Eq(( TLB_REL_DATA_Q(53) ) , STD_ULOGIC'('0')); +-- Table CAM_MASK_BITS Signal Assignments for Outputs +MQQ249:TLB_REL_CMPMASK(0) <= + (CAM_MASK_BITS_PT(13) OR CAM_MASK_BITS_PT(14) + OR CAM_MASK_BITS_PT(17) OR CAM_MASK_BITS_PT(18) + ); +MQQ250:TLB_REL_CMPMASK(1) <= + (CAM_MASK_BITS_PT(17) OR CAM_MASK_BITS_PT(19) + ); +MQQ251:TLB_REL_CMPMASK(2) <= + (CAM_MASK_BITS_PT(19)); +MQQ252:TLB_REL_CMPMASK(3) <= + (CAM_MASK_BITS_PT(15)); +MQQ253:TLB_REL_XBITMASK(0) <= + (CAM_MASK_BITS_PT(12)); +MQQ254:TLB_REL_XBITMASK(1) <= + (CAM_MASK_BITS_PT(13)); +MQQ255:TLB_REL_XBITMASK(2) <= + (CAM_MASK_BITS_PT(16)); +MQQ256:TLB_REL_XBITMASK(3) <= + (CAM_MASK_BITS_PT(18)); +MQQ257:TLB_REL_MASKPAR <= + (CAM_MASK_BITS_PT(12) OR CAM_MASK_BITS_PT(14) + OR CAM_MASK_BITS_PT(16)); +MQQ258:EX6_DATA_CMPMASK(0) <= + (CAM_MASK_BITS_PT(2) OR CAM_MASK_BITS_PT(4) + OR CAM_MASK_BITS_PT(5) OR CAM_MASK_BITS_PT(6) + OR CAM_MASK_BITS_PT(7) OR CAM_MASK_BITS_PT(9) + OR CAM_MASK_BITS_PT(11)); +MQQ259:EX6_DATA_CMPMASK(1) <= + (CAM_MASK_BITS_PT(2) OR CAM_MASK_BITS_PT(7) + OR CAM_MASK_BITS_PT(9) OR CAM_MASK_BITS_PT(10) + OR CAM_MASK_BITS_PT(11)); +MQQ260:EX6_DATA_CMPMASK(2) <= + (CAM_MASK_BITS_PT(2) OR CAM_MASK_BITS_PT(7) + OR CAM_MASK_BITS_PT(8) OR CAM_MASK_BITS_PT(10) + OR CAM_MASK_BITS_PT(11)); +MQQ261:EX6_DATA_CMPMASK(3) <= + (CAM_MASK_BITS_PT(2) OR CAM_MASK_BITS_PT(7) + OR CAM_MASK_BITS_PT(8) OR CAM_MASK_BITS_PT(11) + ); +MQQ262:EX6_DATA_XBITMASK(0) <= + (CAM_MASK_BITS_PT(1)); +MQQ263:EX6_DATA_XBITMASK(1) <= + (CAM_MASK_BITS_PT(5)); +MQQ264:EX6_DATA_XBITMASK(2) <= + (CAM_MASK_BITS_PT(3)); +MQQ265:EX6_DATA_XBITMASK(3) <= + (CAM_MASK_BITS_PT(4)); +MQQ266:EX6_DATA_MASKPAR <= + (CAM_MASK_BITS_PT(1) OR CAM_MASK_BITS_PT(3) + OR CAM_MASK_BITS_PT(6)); + +wr_array_val <= por_wr_array_val when por_seq_q/=PorSeq_Idle + else (others => '0') when (ex6_valid_q/="0000" and ex6_ttype_q(4 to 5)/="00") + else (others => tlb_rel_data_q(eratpos_wren)) + when (tlb_rel_val_q(0 to 3)/="0000" and tlb_rel_val_q(4)='1') + else (others => '1') when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_ws_q="00" and ex6_tlbsel_q=TlbSel_IErat) + else (others => '0'); +-- tlb_high_data +-- 84 - 0 - X-bit +-- 85:87 - 1:3 - reserved (3b) +-- 88:117 - 4:33 - RPN (30b) +-- 118:119 - 34:35 - R,C +-- 120:121 - 36:37 - WLC (2b) +-- 122 - 38 - ResvAttr +-- 123 - 39 - VF +-- 124 - 40 - IND +-- 125:128 - 41:44 - U0-U3 +-- 129:133 - 45:49 - WIMGE +-- 134:136 - 50:52 - UX,UW,UR +-- 137:139 - 53:55 - SX,SW,SR +-- 140 - 56 - GS +-- 141 - 57 - TS +-- 142:143 - 58:59 - reserved (2b) +-- 144:149 - 60:65 - 6b TID msbs +-- 150:157 - 66:73 - 8b TID lsbs +-- 158:167 - 74:83 - parity 10bits +-- 16x143 version, 42b RA +-- wr_array_data +-- 0:29 - RPN +-- 30:31 - R,C +-- 32:33 - WLC +-- 34 - ResvAttr +-- 35 - VF +-- 36:39 - U0-U3 +-- 40:44 - WIMGE +-- 45:46 - UX,SX +-- 47:48 - UW,SW +-- 49:50 - UR,SR +-- 51:60 - CAM parity +-- 61:67 - Array parity +-- wr_ws1_data (HI) +-- 0:7 - unused +-- 8:9 - WLC +-- 10 - ResvAttr +-- 11 - unused +-- 12:15 - U0-U3 +-- 16:17 - R,C +-- 18:21 - unused +-- 22:51 - RPN +-- 52:56 - WIMGE +-- 57 - VF (not supported in ierat) +-- 58:59 - UX,SX +-- 60:61 - UW,SW +-- 62:63 - UR,SR +wr_array_data_nopar <= por_wr_array_data(0 to 50) when por_seq_q/=PorSeq_Idle + else (tlb_rel_data_q(70 to 101) & tlb_rel_data_q(103 to 121)) + when (tlb_rel_val_q(0 to 3)/="0000" and tlb_rel_val_q(4)='1') + else (rpn_holdreg0_q(22 to 51) & rpn_holdreg0_q(16 to 17) & rpn_holdreg0_q(8 to 10) & '0' & + rpn_holdreg0_q(12 to 15) & rpn_holdreg0_q(52 to 56) & rpn_holdreg0_q(58 to 63)) + when (ex6_valid_q(0)='1' and ex6_ttype_q(1)='1' and ex6_ws_q="00") + else (rpn_holdreg1_q(22 to 51) & rpn_holdreg1_q(16 to 17) & rpn_holdreg1_q(8 to 10) & '0' & + rpn_holdreg1_q(12 to 15) & rpn_holdreg1_q(52 to 56) & rpn_holdreg1_q(58 to 63)) + when (ex6_valid_q(1)='1' and ex6_ttype_q(1)='1' and ex6_ws_q="00") + else (rpn_holdreg2_q(22 to 51) & rpn_holdreg2_q(16 to 17) & rpn_holdreg2_q(8 to 10) & '0' & + rpn_holdreg2_q(12 to 15) & rpn_holdreg2_q(52 to 56) & rpn_holdreg2_q(58 to 63)) + when (ex6_valid_q(2)='1' and ex6_ttype_q(1)='1' and ex6_ws_q="00") + else (rpn_holdreg3_q(22 to 51) & rpn_holdreg3_q(16 to 17) & rpn_holdreg3_q(8 to 10) & '0' & + rpn_holdreg3_q(12 to 15) & rpn_holdreg3_q(52 to 56) & rpn_holdreg3_q(58 to 63)) + when (ex6_valid_q(3)='1' and ex6_ttype_q(1)='1' and ex6_ws_q="00") + else (others => '0'); +-- PARITY DEF's +wr_array_par(51) <= xor_reduce(wr_cam_data(0 to 7)); +wr_array_par(52) <= xor_reduce(wr_cam_data(8 to 15)); +wr_array_par(53) <= xor_reduce(wr_cam_data(16 to 23)); +wr_array_par(54) <= xor_reduce(wr_cam_data(24 to 31)); +wr_array_par(55) <= xor_reduce(wr_cam_data(32 to 39)); +wr_array_par(56) <= xor_reduce(wr_cam_data(40 to 47)); +wr_array_par(57) <= xor_reduce(wr_cam_data(48 to 55)); +wr_array_par(58) <= xor_reduce(wr_cam_data(57 to 62)); +wr_array_par(59) <= xor_reduce(wr_cam_data(63 to 66)); +wr_array_par(60) <= xor_reduce(wr_cam_data(67 to 74)); +wr_array_par(61) <= xor_reduce(wr_array_data_nopar(0 to 5)); +wr_array_par(62) <= xor_reduce(wr_array_data_nopar(6 to 13)); +wr_array_par(63) <= xor_reduce(wr_array_data_nopar(14 to 21)); +wr_array_par(64) <= xor_reduce(wr_array_data_nopar(22 to 29)); +wr_array_par(65) <= xor_reduce(wr_array_data_nopar(30 to 37)); +wr_array_par(66) <= xor_reduce(wr_array_data_nopar(38 to 44)); +wr_array_par(67) <= xor_reduce(wr_array_data_nopar(45 to 50)); +wr_array_data(0 TO 50) <= wr_array_data_nopar; +wr_array_data(51 TO 67) <= (wr_array_par(51 to 60) & wr_array_par(61 to 67)) + when ((tlb_rel_val_q(0 to 3)/="0000" and tlb_rel_val_q(4)='1') or + por_seq_q/=PorSeq_Idle) + else ((wr_array_par(51) xor mmucr1_q(5)) & wr_array_par(52 to 60) & + (wr_array_par(61) xor mmucr1_q(6)) & wr_array_par(62 to 67)) + when (ex6_valid_q(0 to 3)/="0000" and ex6_ttype_q(1)='1' and ex6_ws_q="00") + else (others => '0'); +-- Parity Checking +unused_dc(22) <= lcb_delay_lclkr_dc(1) or lcb_mpw1_dc_b(1); +iu2_cmp_data_calc_par(50) <= xor_reduce(iu2_cam_cmp_data_q(75 to 82)); +iu2_cmp_data_calc_par(51) <= xor_reduce(iu2_cam_cmp_data_q(0 to 7)); +iu2_cmp_data_calc_par(52) <= xor_reduce(iu2_cam_cmp_data_q(8 to 15)); +iu2_cmp_data_calc_par(53) <= xor_reduce(iu2_cam_cmp_data_q(16 to 23)); +iu2_cmp_data_calc_par(54) <= xor_reduce(iu2_cam_cmp_data_q(24 to 31)); +iu2_cmp_data_calc_par(55) <= xor_reduce(iu2_cam_cmp_data_q(32 to 39)); +iu2_cmp_data_calc_par(56) <= xor_reduce(iu2_cam_cmp_data_q(40 to 47)); +iu2_cmp_data_calc_par(57) <= xor_reduce(iu2_cam_cmp_data_q(48 to 55)); +iu2_cmp_data_calc_par(58) <= xor_reduce(iu2_cam_cmp_data_q(57 to 62)); +iu2_cmp_data_calc_par(59) <= xor_reduce(iu2_cam_cmp_data_q(63 to 66)); +iu2_cmp_data_calc_par(60) <= xor_reduce(iu2_cam_cmp_data_q(67 to 74)); +iu2_cmp_data_calc_par(61) <= xor_reduce(iu2_array_cmp_data_q(0 to 5)); +iu2_cmp_data_calc_par(62) <= xor_reduce(iu2_array_cmp_data_q(6 to 13)); +iu2_cmp_data_calc_par(63) <= xor_reduce(iu2_array_cmp_data_q(14 to 21)); +iu2_cmp_data_calc_par(64) <= xor_reduce(iu2_array_cmp_data_q(22 to 29)); +iu2_cmp_data_calc_par(65) <= xor_reduce(iu2_array_cmp_data_q(30 to 37)); +iu2_cmp_data_calc_par(66) <= xor_reduce(iu2_array_cmp_data_q(38 to 44)); +iu2_cmp_data_calc_par(67) <= xor_reduce(iu2_array_cmp_data_q(45 to 50)); +ex4_rd_data_calc_par(50) <= xor_reduce(ex4_rd_cam_data_q(75 to 82)); +ex4_rd_data_calc_par(51) <= xor_reduce(ex4_rd_cam_data_q(0 to 7)); +ex4_rd_data_calc_par(52) <= xor_reduce(ex4_rd_cam_data_q(8 to 15)); +ex4_rd_data_calc_par(53) <= xor_reduce(ex4_rd_cam_data_q(16 to 23)); +ex4_rd_data_calc_par(54) <= xor_reduce(ex4_rd_cam_data_q(24 to 31)); +ex4_rd_data_calc_par(55) <= xor_reduce(ex4_rd_cam_data_q(32 to 39)); +ex4_rd_data_calc_par(56) <= xor_reduce(ex4_rd_cam_data_q(40 to 47)); +ex4_rd_data_calc_par(57) <= xor_reduce(ex4_rd_cam_data_q(48 to 55)); +ex4_rd_data_calc_par(58) <= xor_reduce(ex4_rd_cam_data_q(57 to 62)); +ex4_rd_data_calc_par(59) <= xor_reduce(ex4_rd_cam_data_q(63 to 66)); +ex4_rd_data_calc_par(60) <= xor_reduce(ex4_rd_cam_data_q(67 to 74)); +ex4_rd_data_calc_par(61) <= xor_reduce(ex4_rd_array_data_q(0 to 5)); +ex4_rd_data_calc_par(62) <= xor_reduce(ex4_rd_array_data_q(6 to 13)); +ex4_rd_data_calc_par(63) <= xor_reduce(ex4_rd_array_data_q(14 to 21)); +ex4_rd_data_calc_par(64) <= xor_reduce(ex4_rd_array_data_q(22 to 29)); +ex4_rd_data_calc_par(65) <= xor_reduce(ex4_rd_array_data_q(30 to 37)); +ex4_rd_data_calc_par(66) <= xor_reduce(ex4_rd_array_data_q(38 to 44)); +ex4_rd_data_calc_par(67) <= xor_reduce(ex4_rd_array_data_q(45 to 50)); +parerr_gen0: if check_parity = 0 generate +iu2_cmp_data_parerr_epn <= '0'; +iu2_cmp_data_parerr_rpn <= '0'; +end generate parerr_gen0; +parerr_gen1: if check_parity = 1 generate +iu2_cmp_data_parerr_epn <= or_reduce(iu2_cmp_data_calc_par(50 to 60) xor (iu2_cam_cmp_data_q(83) & iu2_array_cmp_data_q(51 to 60))); +iu2_cmp_data_parerr_rpn <= or_reduce(iu2_cmp_data_calc_par(61 to 67) xor iu2_array_cmp_data_q(61 to 67)); +end generate parerr_gen1; +parerr_gen2: if check_parity = 0 generate +ex4_rd_data_parerr_epn <= '0'; +ex4_rd_data_parerr_rpn <= '0'; +end generate parerr_gen2; +parerr_gen3: if check_parity = 1 generate +ex4_rd_data_parerr_epn <= or_reduce(ex4_rd_data_calc_par(50 to 60) xor (ex4_rd_cam_data_q(83) & ex4_rd_array_data_q(51 to 60))); +ex4_rd_data_parerr_rpn <= or_reduce(ex4_rd_data_calc_par(61 to 67) xor ex4_rd_array_data_q(61 to 67)); +end generate parerr_gen3; +-- end of parity checking +-- CAM Port +flash_invalidate <= Eq(por_seq_q,PorSeq_Stg1) or mchk_flash_inv_enab; +comp_invalidate <= '1' when (ex6_valid_q/="0000" and ex6_ttype_q(4 to 5)/="00") + else '0' when (tlb_rel_val_q(0 to 3)/="0000" and tlb_rel_val_q(4)='1') + else '1' when snoop_val_q(0 to 1)="11" + else '0'; +comp_request <= ( or_reduce(ex6_valid_q) and or_reduce(ex6_ttype_q(4 to 5)) ) + or ( snoop_val_q(0) and snoop_val_q(1) and not(or_reduce(tlb_rel_val_q(0 to 3)) and tlb_rel_val_q(4)) ) + or ( ex1_ieratsx ) + or ( iu_ierat_iu0_val ); +gen64_comp_addr: if rs_data_width = 64 generate +comp_addr_mux1 <= ( snoop_addr_q and (52-epn_width to 51 => (snoop_val_q(0) and snoop_val_q(1))) ) + or ( xu_iu_ex1_rb and (64-rs_data_width to 51 => (not(snoop_val_q(0) and snoop_val_q(1)) and ex1_ieratsx)) ); +comp_addr_mux1_sel <= (snoop_val_q(0) and snoop_val_q(1)) or (ex1_ieratsx and snoop_val_q(1)); +comp_addr <= ( comp_addr_mux1 and (52-epn_width to 51 => comp_addr_mux1_sel) ) or + ( iu_ierat_iu0_ifar and (52-epn_width to 51 => not comp_addr_mux1_sel) ); +end generate gen64_comp_addr; +iu_xu_ierat_ex2_flush_d <= ( ex1_valid_q and not(xu_ex1_flush) and (0 to 3 => (ex1_ieratsx and not snoop_val_q(1))) ) + or ( ex1_valid_q and not(xu_ex1_flush) and (0 to 3 => ((ex1_ieratre or ex1_ieratwe or ex1_ieratsx) and tlb_rel_data_q(eratpos_relsoon))) ); +iu_xu_ierat_ex2_flush_req <= iu_xu_ierat_ex2_flush_q; +gen32_comp_addr: if rs_data_width = 32 generate +comp_addr_mux1 <= ( ((0 to 31 => '0') & snoop_addr_q) and (52-epn_width to 51 => (snoop_val_q(0) and snoop_val_q(1))) ) + or ( ((0 to 31 => '0') & xu_iu_ex1_rb) and (64-rs_data_width to 51 => (not(snoop_val_q(0) and snoop_val_q(1)) and ex1_ieratsx)) ); +comp_addr_mux1_sel <= (snoop_val_q(0) and snoop_val_q(1)) or ex1_ieratsx; +comp_addr <= ( comp_addr_mux1 and (0 to 51 => comp_addr_mux1_sel) ) + or ( ((0 to 31 => '0') & iu_ierat_iu0_ifar(32 to 51)) and (0 to 51 => not comp_addr_mux1_sel) ); +end generate gen32_comp_addr; +-- ex1_rs_is(0 to 9) from erativax instr. +-- RS(55) -> ex1_rs_is(0) -> snoop_attr(0) -> Local +-- RS(56:57) -> ex1_rs_is(1:2) -> snoop_attr(0:1) -> IS +-- RS(58:59) -> ex1_rs_is(3:4) -> snoop_attr(2:3) -> Class +-- n/a -> n/a -> snoop_attr(4:5) -> State +-- n/a -> n/a -> snoop_attr(6:13) -> TID(6:13) +-- RS(60:63) -> ex1_rs_is(5:8) -> snoop_attr(14:17) -> Size +-- n/a -> n/a -> snoop_attr(20:25) -> TID(0:5) +-- snoop_attr: +-- 0 -> Local +-- 1:3 -> IS/Class: 0=all, 1=tid, 2=gs, 3=epn, 4=class0, 5=class1, 6=class2, 7=class3 +-- 4:5 -> GS/TS +-- 6:13 -> TID(6:13) +-- 14:17 -> Size +-- 18 -> reserved for tlb, extclass_enable(0) for erats +-- 19 -> mmucsr0.tlb0fi for tlb, or TID_NZ for erats +-- 20:25 -> TID(0:5) +addr_enable(0) <= not(or_reduce(ex6_valid_q) and or_reduce(ex6_ttype_q(4 to 5))) and + ( (snoop_val_q(0) and snoop_val_q(1) and not snoop_attr_q(1) and snoop_attr_q(2) and snoop_attr_q(3)) + or (or_reduce(ex1_valid_q) and ex1_ttype_q(2) and ex1_tlbsel_q(0) and not ex1_tlbsel_q(1) and not(snoop_val_q(0) and snoop_val_q(1))) + or (iu_ierat_iu0_val and not(snoop_val_q(0) and snoop_val_q(1))) ); +addr_enable(1) <= not(or_reduce(ex6_valid_q) and or_reduce(ex6_ttype_q(4 to 5))) and + ( (snoop_val_q(0) and snoop_val_q(1) and snoop_attr_q(0) and not snoop_attr_q(1) and snoop_attr_q(2) and snoop_attr_q(3)) + or (or_reduce(ex1_valid_q) and ex1_ttype_q(2) and ex1_tlbsel_q(0) and not ex1_tlbsel_q(1) and not(snoop_val_q(0) and snoop_val_q(1))) + or (iu_ierat_iu0_val and not(snoop_val_q(0) and snoop_val_q(1))) ); +comp_pgsize <= CAM_PgSize_1GB when snoop_attr_q(14 to 17)=WS0_PgSize_1GB + else CAM_PgSize_16MB when snoop_attr_q(14 to 17)=WS0_PgSize_16MB + else CAM_PgSize_1MB when snoop_attr_q(14 to 17)=WS0_PgSize_1MB + else CAM_PgSize_64KB when snoop_attr_q(14 to 17)=WS0_PgSize_64KB + else CAM_PgSize_4KB; +pgsize_enable <= '0' when (ex6_valid_q/="0000" and ex6_ttype_q(4 to 5)/="00") + else '1' when (snoop_val_q(0 to 1)="11" and snoop_attr_q(0 to 3)="0011") + else '0'; +-- mmucr1_q: 0-IRRE, 1-REE, 2-CEE, 3-csync, 4-isync, 5:6-IPEI, 7:8-ICTID/ITTID +comp_class <= ( snoop_attr_q(20 to 21) and (0 to 1 => (snoop_val_q(0) and snoop_val_q(1) and mmucr1_q(7))) ) + or ( snoop_attr_q(2 to 3) and (0 to 1 => (snoop_val_q(0) and snoop_val_q(1) and not mmucr1_q(7))) ) + or ( ex1_pid_q(pid_width-14 to pid_width-13) and (0 to 1 => (not(snoop_val_q(0) and snoop_val_q(1)) and mmucr1_q(7) and ex1_ieratsx)) ) + or ( iu1_pid_d(pid_width-14 to pid_width-13) and (0 to 1 => (not(snoop_val_q(0) and snoop_val_q(1)) and mmucr1_q(7) and not(ex1_ieratsx))) ); +class_enable(0) <= '0' when (mmucr1_q(7)='1') + else '0' when (ex6_valid_q/="0000" and ex6_ttype_q(4 to 5)/="00") + else '1' when (snoop_val_q(0 to 1)="11" and snoop_attr_q(1)='1') + else '0'; +class_enable(1) <= '0' when (mmucr1_q(7)='1') + else '0' when (ex6_valid_q/="0000" and ex6_ttype_q(4 to 5)/="00") + else '1' when (snoop_val_q(0 to 1)="11" and snoop_attr_q(1)='1') + else '0'; +class_enable(2) <= '0' when (mmucr1_q(7)='0') + else pid_enable; +-- snoop_attr: +-- 0 -> Local +-- 1:3 -> IS/Class: 0=all, 1=tid, 2=gs, 3=epn, 4=class0, 5=class1, 6=class2, 7=class3 +-- 4:5 -> GS/TS +-- 6:13 -> TID(6:13) +-- 14:17 -> Size +-- 18 -> reserved for tlb, extclass_enable(0) for erats +-- 19 -> mmucsr0.tlb0fi for tlb, or TID_NZ for erats +-- 20:25 -> TID(0:5) +--comp_extclass <= (others => '0'); -- std_ulogic_vector(0 to 1); +--extclass_enable <= 10 when (ex6_valid_q/= 0000 and ex6_ttype_q(4 to 5)/= 00 ) -- csync or isync enabled +-- else 10 when (snoop_val_q(0 to 1)= 11 ) -- any invalidate snoop +-- else 00 ; -- std_ulogic; +comp_extclass(0) <= '0'; +comp_extclass(1) <= snoop_attr_q(19); +extclass_enable(0) <= ( or_reduce(ex6_valid_q) and or_reduce(ex6_ttype_q(4 to 5)) ) + or ( snoop_val_q(0) and snoop_val_q(1) and snoop_attr_q(18) ); +extclass_enable(1) <= ( snoop_val_q(0) and snoop_val_q(1) and not snoop_attr_q(1) and snoop_attr_q(3) ); +-- state: 0:pr 1:gs 2:is 3:cm +-- cam state bits are 0:HS, 1:AS +comp_state <= ( snoop_attr_q(4 to 5) and (0 to 1 => (snoop_val_q(0) and snoop_val_q(1) and not snoop_attr_q(1) and snoop_attr_q(2))) ) + or ( ex1_state_q(1 to 2) and (0 to 1 => (not(snoop_val_q(0) and snoop_val_q(1)) and ex1_ieratsx)) ) + or ( iu1_state_d(1 to 2) and (0 to 1 => (not(snoop_val_q(0) and snoop_val_q(1)) and not ex1_ieratsx)) ) ; +state_enable(0) <= not(or_reduce(ex6_valid_q) and or_reduce(ex6_ttype_q(4 to 5))) and + ( (snoop_val_q(0) and snoop_val_q(1) and not snoop_attr_q(1) and snoop_attr_q(2) ) + or (or_reduce(ex1_valid_q) and ex1_ttype_q(2) and ex1_tlbsel_q(0) and not ex1_tlbsel_q(1) and not(snoop_val_q(0) and snoop_val_q(1))) + or (iu_ierat_iu0_val and not(snoop_val_q(0) and snoop_val_q(1))) ); +state_enable(1) <= not(or_reduce(ex6_valid_q) and or_reduce(ex6_ttype_q(4 to 5))) and + ( (snoop_val_q(0) and snoop_val_q(1) and not snoop_attr_q(1) and snoop_attr_q(2) and snoop_attr_q(3)) + or (or_reduce(ex1_valid_q) and ex1_ttype_q(2) and ex1_tlbsel_q(0) and not ex1_tlbsel_q(1) and not(snoop_val_q(0) and snoop_val_q(1))) + or (iu_ierat_iu0_val and not(snoop_val_q(0) and snoop_val_q(1))) ); +comp_thdid <= ( snoop_attr_q(22 to 25) and (0 to 3 => (mmucr1_q(8) and snoop_val_q(0) and snoop_val_q(1))) ) + or ( ex1_pid_q(pid_width-12 to pid_width-9) and (0 to 3 => (mmucr1_q(8) and not(snoop_val_q(0) and snoop_val_q(1)) and ex1_ieratsx)) ) + or ( iu1_pid_d(pid_width-12 to pid_width-9) and (0 to 3 => (mmucr1_q(8) and not(snoop_val_q(0) and snoop_val_q(1)) and not ex1_ieratsx)) ) + or ( 0 to 3 => (snoop_val_q(0) and snoop_val_q(1) and not mmucr1_q(8)) ) + or ( ex1_valid_q and (0 to 3 => (ex1_ttype_q(2) and ex1_tlbsel_q(0) and not ex1_tlbsel_q(1) and not(snoop_val_q(0) and snoop_val_q(1)) and not mmucr1_q(8))) ) + or ( iu_ierat_iu0_thdid and (0 to 3 => ((not or_reduce(ex1_valid_q) or not ex1_ttype_q(2) or not Eq(ex1_tlbsel_q,TlbSel_IErat)) + and not(snoop_val_q(0) and snoop_val_q(1)) and not mmucr1_q(8))) ); +thdid_enable(0) <= ( (iu_ierat_iu0_val or (or_reduce(ex1_valid_q) and ex1_ttype_q(2) and ex1_tlbsel_q(0) and not ex1_tlbsel_q(1))) and + (not mmucr1_q(8) and not(snoop_val_q(0) and snoop_val_q(1)) and not(or_reduce(ex6_valid_q) and or_reduce(ex6_ttype_q(4 to 5)))) ); +thdid_enable(1) <= pid_enable and mmucr1_q(8); +comp_pid <= ( snoop_attr_q(6 to 13) and (0 to 7 => (snoop_val_q(0) and snoop_val_q(1))) ) + or ( ex1_pid_q(pid_width-8 to pid_width-1) and + (0 to 7 => (or_reduce(ex1_valid_q) and ex1_ttype_q(2) and ex1_tlbsel_q(0) and not ex1_tlbsel_q(1) and not(snoop_val_q(0) and snoop_val_q(1)))) ) + or ( iu1_pid_d(pid_width-8 to pid_width-1) and + (0 to 7 => (not(or_reduce(ex1_valid_q) and ex1_ttype_q(2) and ex1_tlbsel_q(0) and not ex1_tlbsel_q(1)) and not(snoop_val_q(0) and snoop_val_q(1)))) ); +pid_enable <= not(or_reduce(ex6_valid_q) and or_reduce(ex6_ttype_q(4 to 5))) and + ( (snoop_val_q(0) and snoop_val_q(1) and not snoop_attr_q(1) and snoop_attr_q(3)) + or (or_reduce(ex1_valid_q) and ex1_ttype_q(2) and ex1_tlbsel_q(0) and not ex1_tlbsel_q(1) and not(snoop_val_q(0) and snoop_val_q(1))) + or (iu_ierat_iu0_val and not(snoop_val_q(0) and snoop_val_q(1))) ); +-- wr_cam_data +-- 0:51 - EPN +-- 52 - X +-- 53:55 - SIZE +-- 56 - V +-- 57:60 - ThdID +-- 61:62 - Class +-- 63:64 - ExtClass | TID_NZ +-- 65 - TGS +-- 66 - TS +-- 67:74 - TID +-- 75:78 - epn_cmpmasks: 34_39, 40_43, 44_47, 48_51 +-- 79:82 - xbit_cmpmasks: 34_51, 40_51, 44_51, 48_51 +-- 83 - parity for 75:82 +-- 16x143 version, 42b RA +-- wr_array_data +-- 0:29 - RPN +-- 30:31 - R,C +-- 32:33 - WLC +-- 34 - ResvAttr +-- 35 - VF +-- 36:39 - U0-U3 +-- 40:44 - WIMGE +-- 45:46 - UX,SX +-- 47:48 - UW,SW +-- 49:50 - UR,SR +-- 51:60 - CAM parity +-- 61:67 - Array parity +-- wr_ws0_data (LO) +-- 0:51 - EPN +-- 52:53 - Class +-- 54 - V +-- 55 - X +-- 56:59 - SIZE +-- 60:63 - ThdID +-- CAM.ExtClass - MMUCR ExtClass +-- CAM.TS - MMUCR TS +-- CAM.TID - MMUCR TID +-- wr_ws1_data (HI) +-- 0:7 - unused +-- 8:9 - WLC +-- 10 - ResvAttr +-- 11 - unused +-- 12:15 - U0-U3 +-- 16:17 - R,C +-- 18:21 - unused +-- 22:51 - RPN +-- 52:56 - WIMGE +-- 57 - VF (not supported in ierat) +-- 58:59 - UX,SX +-- 60:61 - UW,SW +-- 62:63 - UR,SR +-- EPN Class V +-- X SIZE ThdID +-- Unused ResvAttr U0-U3 R,C +-- RPN WIMGE Unused UX,UW,UR,SX,SW,SR +gen64_data_out: if data_out_width = 64 generate +ex4_data_out_d <= ( ((0 to 31 => '0') & rd_cam_data(32 to 51) & rd_cam_data(61 to 62) & rd_cam_data(56) & + rd_cam_data(52) & ws0_pgsize(0 to 3) & rd_cam_data(57 to 60)) + and (64-data_out_width to 63 => (or_reduce(ex3_valid_q) and ex3_ttype_q(0) and not ex3_ws_q(0) and not ex3_ws_q(1) and not ex3_state_q(3))) ) + or ( ((0 to 31 => '0') & rd_array_data(10 to 29) & "00" & rd_array_data(0 to 9)) + and (64-data_out_width to 63 => (or_reduce(ex3_valid_q) and ex3_ttype_q(0) and not ex3_ws_q(0) and ex3_ws_q(1) and not ex3_state_q(3))) ) + or ( ((0 to 31 => '0') & "00000000" & rd_array_data(32 to 34) & '0' & rd_array_data(36 to 39) & rd_array_data(30 to 31) & + "00" & rd_array_data(40 to 44) & '0' & rd_array_data(45 to 50)) + and (64-data_out_width to 63 => (or_reduce(ex3_valid_q) and ex3_ttype_q(0) and ex3_ws_q(0) and not ex3_ws_q(1) and not ex3_state_q(3))) ) + or ( (rd_cam_data(0 to 51) & rd_cam_data(61 to 62) & rd_cam_data(56) & + rd_cam_data(52) & ws0_pgsize(0 to 3) & rd_cam_data(57 to 60)) + and (64-data_out_width to 63 => (or_reduce(ex3_valid_q) and ex3_ttype_q(0) and not ex3_ws_q(0) and not ex3_ws_q(1) and ex3_state_q(3))) ) + or ( ("00000000" & rd_array_data(32 to 34) & '0' & rd_array_data(36 to 39) & rd_array_data(30 to 31) & + "0000" & rd_array_data(0 to 29) & rd_array_data(40 to 44) & '0' & rd_array_data(45 to 50)) + and (64-data_out_width to 63 => (or_reduce(ex3_valid_q) and ex3_ttype_q(0) and not ex3_ws_q(0) and ex3_ws_q(1) and ex3_state_q(3))) ) + or ( ((0 to 47-watermark_width => '0') & (watermark_q and (48-watermark_width to 47 => bcfg_q(107))) & (48 to 63-eptr_width => '0') & eptr_q) + and (64-data_out_width to 63 => (or_reduce(ex3_valid_q) and ex3_ttype_q(0) and ex3_ws_q(0) and ex3_ws_q(1) and mmucr1_q(0))) ) + or ( ((0 to 47-watermark_width => '0') & (watermark_q and (48-watermark_width to 47 => bcfg_q(107))) & (48 to 63-num_entry_log2 => '0') & lru_way_encode) + and (64-data_out_width to 63 => (or_reduce(ex3_valid_q) and ex3_ttype_q(0) and ex3_ws_q(0) and ex3_ws_q(1) and not mmucr1_q(0))) ) + or ( ((0 to 49 => '0') & ex3_eratsx_data_q(0 to 1) & (52 to 59 => '0') & ex3_eratsx_data_q(2 to 2+num_entry_log2-1)) + and (64-data_out_width to 63 => (or_reduce(ex3_valid_q) and ex3_ttype_q(2))) ); +end generate gen64_data_out; +gen32_data_out: if data_out_width = 32 generate +ex4_data_out_d <= ( (rd_cam_data(32 to 51) & rd_cam_data(61 to 62) & rd_cam_data(56) & + rd_cam_data(52) & ws0_pgsize(0 to 3) & rd_cam_data(57 to 60)) + and (64-data_out_width to 63 => (or_reduce(ex3_valid_q) and ex3_ttype_q(0) and not ex3_ws_q(0) and not ex3_ws_q(1))) ) + or ( (rd_array_data(10 to 29) & "00" & rd_array_data(0 to 9)) + and (64-data_out_width to 63 => (or_reduce(ex3_valid_q) and ex3_ttype_q(0) and not ex3_ws_q(0) and ex3_ws_q(1))) ) + or ( ("00000000" & rd_array_data(32 to 34) & '0' & rd_array_data(36 to 39) & rd_array_data(30 to 31) & + "00" & rd_array_data(40 to 44) & rd_array_data(35) & rd_array_data(45 to 50)) + and (64-data_out_width to 63 => (or_reduce(ex3_valid_q) and ex3_ttype_q(0) and ex3_ws_q(0) and not ex3_ws_q(1))) ) + or ( ((32 to 47-watermark_width => '0') & (watermark_q and (48-watermark_width to 47 => bcfg_q(107))) & (48 to 63-eptr_width => '0') & eptr_q) + and (64-data_out_width to 63 => (or_reduce(ex3_valid_q) and ex3_ttype_q(0) and ex3_ws_q(0) and ex3_ws_q(1) and mmucr1_q(0))) ) + or ( ((32 to 47-watermark_width => '0') & (watermark_q and (48-watermark_width to 47 => bcfg_q(107))) & (48 to 63-num_entry_log2 => '0') & lru_way_encode) + and (64-data_out_width to 63 => (or_reduce(ex3_valid_q) and ex3_ttype_q(0) and ex3_ws_q(0) and ex3_ws_q(1) and not mmucr1_q(0))) ) + or ( ((32 to 49 => '0') & ex3_eratsx_data_q(0 to 1) & (52 to 59 => '0') & ex3_eratsx_data_q(2 to 2+num_entry_log2-1)) + and (64-data_out_width to 63 => (or_reduce(ex3_valid_q) and ex3_ttype_q(2))) ); +end generate gen32_data_out; +-- ERAT outputs +-- pass thru ifar offset bits depending on page size from cam entry +-- wr_cam_data(75) (76) (77) (78) (79) (80) (81) (82) +-- cmpmask(0) (1) (2) (3) xbitmask(0) (1) (2) (3) +-- xbit pgsize 34_39 40_43 44_47 48_51 34_39 40_43 44_47 48_51 size +-- 0 001 1 1 1 1 0 0 0 0 4K +-- 0 011 1 1 1 0 0 0 0 0 64K +-- 0 101 1 1 0 0 0 0 0 0 1M +-- 0 111 1 0 0 0 0 0 0 0 16M +-- 0 110 0 0 0 0 0 0 0 0 1G +-- new cam _np2 bypass attributes (bit numbering per array) +-- 30:31 - R,C +-- 32:33 - WLC +-- 34 - ResvAttr +-- 35 - VF +-- 36:39 - U0-U3 +-- 40:44 - WIMGE +-- 45:46 - UX,SX +-- 47:48 - UW,SW +-- 49:50 - UR,SR +bypass_mux_enab_np1 <= (ccr2_frat_paranoia_q(9) or iu_ierat_iu1_back_inv or an_ac_grffence_en_dc); +bypass_attr_np1(0 TO 5) <= (others => '0'); +bypass_attr_np1(6 TO 9) <= ccr2_frat_paranoia_q(5 to 8); +bypass_attr_np1(10 TO 14) <= ccr2_frat_paranoia_q(0 to 4); +bypass_attr_np1(15 TO 20) <= "111111"; +ierat_iu_iu2_error(0) <= iu2_miss_sig or iu2_multihit_sig or iu2_parerr_sig or iu2_isi_sig; +ierat_iu_iu2_error(1) <= iu2_miss_sig or iu2_multihit_sig; +ierat_iu_iu2_error(2) <= iu2_miss_sig or iu2_parerr_sig; +ierat_iu_iu2_miss <= iu2_miss_sig; +ierat_iu_iu2_multihit <= iu2_multihit_sig; +ierat_iu_iu2_isi <= iu2_isi_sig; +ierat_iu_hold_req <= hold_req_q; +ierat_iu_iu2_flush_req <= iu2_n_flush_req_q; +iu_xu_ex4_data <= ex4_data_out_q; +iu_mm_ierat_req <= iu2_tlbreq_q; +iu_mm_ierat_thdid <= iu2_valid_q; +iu_mm_ierat_state <= iu2_state_q; +iu_mm_ierat_tid <= iu2_pid_q; +iu_mm_ierat_flush <= iu_mm_ierat_flush_q; +iu_mm_ierat_mmucr0 <= ex6_extclass_q & ex6_state_q(1 to 2) & ex6_pid_q; +iu_mm_ierat_mmucr0_we <= ex6_valid_q when (ex6_ttype_q(0)='1' and ex6_ws_q="00" and ex6_tlbsel_q=TlbSel_IErat) + else (others => '0'); +iu_mm_ierat_mmucr1 <= ex6_ieen_q(1 to num_entry_log2); +iu_mm_ierat_mmucr1_we <= ex6_ieen_q(0); +iu_xu_ierat_ex3_par_err <= ex3_parerr_q(0 to thdid_width-1) and (0 to thdid_width-1 => ex3_parerr_enab); +iu_xu_ierat_ex4_par_err <= ex4_parerr_q(0 to thdid_width-1) and (0 to thdid_width-1 => ex4_parerr_enab); +-- NOTE: example parity generation/checks in iuq_ic_dir.vhdl or xuq_lsu_dc_arr.vhdl. +----------------------------------------------------------------------- +-- CAM Instantiation +----------------------------------------------------------------------- +ierat_cam: entity tri.tri_cam_16x143_1r1w1c + generic map (expand_type => expand_type) + port map ( + gnd => gnd, + vdd => vdd, + vcs => vcs, + nclk => nclk, + + + tc_ccflush_dc => tc_ccflush_dc, + tc_scan_dis_dc_b => tc_scan_dis_dc_b, + tc_scan_diag_dc => tc_scan_diag_dc, + tc_lbist_en_dc => tc_lbist_en_dc, + an_ac_atpg_en_dc => an_ac_atpg_en_dc, + + + lcb_d_mode_dc => cam_d_mode, + lcb_clkoff_dc_b => cam_clkoff_b, + lcb_act_dis_dc => cam_act_dis, + lcb_mpw1_dc_b => cam_mpw1_b(0 to 3), + lcb_mpw2_dc_b => cam_mpw2_b, + lcb_delay_lclkr_dc => cam_delay_lclkr(0 to 3), + + pc_sg_2 => pc_iu_sg_2, + pc_func_slp_sl_thold_2 => pc_iu_func_slp_sl_thold_2, + pc_func_slp_nsl_thold_2 => pc_iu_func_slp_nsl_thold_2, + pc_regf_slp_sl_thold_2 => pc_iu_regf_slp_sl_thold_2, + pc_time_sl_thold_2 => pc_iu_time_sl_thold_2, + pc_fce_2 => pc_iu_fce_2, + + func_scan_in => func_scan_in_cam, + func_scan_out => func_scan_out_cam, + regfile_scan_in => regf_scan_in, + regfile_scan_out => regf_scan_out, + time_scan_in => time_scan_in, + time_scan_out => time_scan_out, + + rd_val => rd_val, + rd_val_late => tiup, + rw_entry => rw_entry, + + wr_array_data => wr_array_data, + wr_cam_data => wr_cam_data, + wr_array_val => wr_array_val, + wr_cam_val => wr_cam_val, + wr_val_early => wr_val_early, + + comp_request => comp_request, + comp_addr => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + comp_class => comp_class, + class_enable => class_enable, + comp_extclass => comp_extclass, + extclass_enable => extclass_enable, + comp_state => comp_state, + state_enable => state_enable, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + comp_pid => comp_pid, + pid_enable => pid_enable, + comp_invalidate => comp_invalidate, + flash_invalidate => flash_invalidate, + + array_cmp_data => array_cmp_data, + rd_array_data => rd_array_data, + + cam_cmp_data => cam_cmp_data, + cam_hit => cam_hit, + cam_hit_entry => cam_hit_entry, + entry_match => entry_match, + entry_valid => entry_valid, + rd_cam_data => rd_cam_data, + + +----- new ports for IO plus ----------------------- +bypass_mux_enab_np1 => bypass_mux_enab_np1, + bypass_attr_np1 => bypass_attr_np1, + attr_np2 => attr_np2, + rpn_np2 => rpn_np2 + + ); +-- bypass attributes (bit numbering per array) +-- 30:31 - R,C +-- 32:33 - WLC +-- 34 - ResvAttr +-- 35 - VF +-- 36:39 - U0-U3 +-- 40:44 - WIMGE +-- 45:46 - UX,SX +-- 47:48 - UW,SW +-- 49:50 - UR,SR +ierat_iu_iu2_rpn <= rpn_np2; +ierat_iu_iu2_wimge <= attr_np2(10 to 14); +ierat_iu_iu2_u <= attr_np2(6 to 9); +-- debug bus outputs +iu1_debug_d(0) <= comp_request; +iu1_debug_d(1) <= comp_invalidate; +iu1_debug_d(2) <= ( or_reduce(ex6_valid_q) and or_reduce(ex6_ttype_q(4 to 5)) ); +iu1_debug_d(3) <= '0'; +iu1_debug_d(4) <= ( snoop_val_q(0) and snoop_val_q(1) and not(or_reduce(tlb_rel_val_q(0 to 3)) and tlb_rel_val_q(4)) ); +iu1_debug_d(5) <= ( ex1_ieratsx ); +iu1_debug_d(6) <= ( iu_ierat_iu0_val ); +iu1_debug_d(7) <= ( or_reduce(tlb_rel_val_q(0 to 3)) and tlb_rel_val_q(4) ); +iu1_debug_d(8) <= ( or_reduce(tlb_rel_val_q(0 to 3)) ); +iu1_debug_d(9) <= ( snoop_val_q(0) and snoop_val_q(1) ); +iu1_debug_d(10) <= '0'; +iu2_debug_d(0 TO 10) <= iu1_debug_q(0 to 10); +iu2_debug_d(11 TO 15) <= '0' & iu1_first_hit_entry; +iu2_debug_d(16) <= iu1_multihit; +lru_debug_d(0) <= ( tlb_rel_data_q(eratpos_wren) and or_reduce(tlb_rel_val_q(0 to 3)) and tlb_rel_val_q(4) ); +lru_debug_d(1) <= ( snoop_val_q(0) and snoop_val_q(1) ); +lru_debug_d(2) <= ( or_reduce(ex6_valid_q) and (ex6_ttype_q(4) or ex6_ttype_q(5)) ); +lru_debug_d(3) <= ( or_reduce(ex6_valid_q) and ex6_ttype_q(1) and not ex6_ws_q(0) and not ex6_ws_q(1) + and ex6_tlbsel_q(0) and not ex6_tlbsel_q(1) and lru_way_is_written ); +lru_debug_d(4) <= ( or_reduce(iu1_valid_q and not(iu_ierat_iu1_flush) and not(xu_iu_flush) and not(iu2_n_flush_req_q)) + and not iu1_flush_enab_q and cam_hit and lru_way_is_hit_entry ); +lru_debug_d(5 TO 19) <= lru_eff; +lru_debug_d(20 TO 23) <= lru_way_encode; +ierat_iu_debug_group0(0 TO 83) <= iu2_cam_cmp_data_q(0 to 83); +ierat_iu_debug_group0(84) <= ex3_eratsx_data_q(1); +ierat_iu_debug_group0(85) <= iu2_debug_q(0); +ierat_iu_debug_group0(86) <= iu2_debug_q(1); +ierat_iu_debug_group0(87) <= iu2_debug_q(9); +ierat_iu_debug_group1(0 TO 67) <= iu2_array_cmp_data_q(0 to 67); +ierat_iu_debug_group1(68) <= ex3_eratsx_data_q(1); +ierat_iu_debug_group1(69) <= iu2_debug_q(16); +ierat_iu_debug_group1(70 TO 74) <= iu2_debug_q(11 to 15); +ierat_iu_debug_group1(75) <= iu2_debug_q(0); +ierat_iu_debug_group1(76) <= iu2_debug_q(1); +ierat_iu_debug_group1(77) <= iu2_debug_q(2); +ierat_iu_debug_group1(78) <= iu2_debug_q(3); +ierat_iu_debug_group1(79) <= iu2_debug_q(4); +ierat_iu_debug_group1(80) <= iu2_debug_q(5); +ierat_iu_debug_group1(81) <= iu2_debug_q(6); +ierat_iu_debug_group1(82) <= iu2_debug_q(7); +ierat_iu_debug_group1(83) <= iu2_debug_q(8); +ierat_iu_debug_group1(84) <= iu2_debug_q(9); +ierat_iu_debug_group1(85) <= iu2_debug_q(10); +ierat_iu_debug_group1(86) <= '0'; +ierat_iu_debug_group1(87) <= lru_update_event_q(7) or lru_update_event_q(8); +ierat_iu_debug_group2(0 TO 15) <= entry_valid_q(0 to 15); +ierat_iu_debug_group2(16 TO 31) <= entry_match_q(0 to 15); +ierat_iu_debug_group2(32 TO 47) <= '0' & lru_q(1 to 15); +ierat_iu_debug_group2(48 TO 63) <= '0' & lru_debug_q(5 to 19); +ierat_iu_debug_group2(64 TO 73) <= lru_update_event_q(0 to 8) & iu2_debug_q(16); +ierat_iu_debug_group2(74 TO 78) <= '0' & lru_debug_q(20 to 23); +ierat_iu_debug_group2(79 TO 83) <= '0' & watermark_q(0 to 3); +ierat_iu_debug_group2(84) <= ex3_eratsx_data_q(1); +ierat_iu_debug_group2(85) <= iu2_debug_q(0); +ierat_iu_debug_group2(86) <= iu2_debug_q(1); +ierat_iu_debug_group2(87) <= iu2_debug_q(9); +ierat_iu_debug_group3(0) <= ex3_eratsx_data_q(1); +ierat_iu_debug_group3(1) <= iu2_debug_q(0); +ierat_iu_debug_group3(2) <= iu2_debug_q(1); +ierat_iu_debug_group3(3) <= iu2_debug_q(9); +ierat_iu_debug_group3(4 TO 8) <= iu2_debug_q(11 to 15); +ierat_iu_debug_group3(9) <= lru_update_event_q(7) or lru_update_event_q(8); +ierat_iu_debug_group3(10 TO 14) <= lru_debug_q(0 to 4); +ierat_iu_debug_group3(15 TO 19) <= '0' & watermark_q(0 to 3); +ierat_iu_debug_group3(20 TO 35) <= entry_valid_q(0 to 15); +ierat_iu_debug_group3(36 TO 51) <= entry_match_q(0 to 15); +ierat_iu_debug_group3(52 TO 67) <= '0' & lru_q(1 to 15); +ierat_iu_debug_group3(68 TO 83) <= '0' & lru_debug_q(5 to 19); +ierat_iu_debug_group3(84 TO 87) <= lru_debug_q(20 to 23); +-- unused spare signal assignments +unused_dc(0) <= mmucr1_q(2); +unused_dc(1) <= iu2_multihit_enab and or_reduce(iu2_first_hit_entry); +unused_dc(2) <= or_reduce(ex6_ttype_q(2 to 3)) and ex6_state_q(0); +unused_dc(3) <= or_reduce(tlb_rel_data_q(eratpos_rpnrsvd to eratpos_rpnrsvd+3)); +unused_dc(4) <= iu2_cam_cmp_data_q(56) or ex4_rd_cam_data_q(56); +unused_dc(5) <= or_reduce(attr_np2(0 to 5)); +unused_dc(6) <= or_reduce(attr_np2(15 to 20)); +unused_dc(7) <= or_reduce(cam_hit_entry); +unused_dc(8) <= or_reduce(bcfg_q_b(0 to 15)); +unused_dc(9) <= or_reduce(bcfg_q_b(16 to 31)); +unused_dc(10) <= or_reduce(bcfg_q_b(32 to 47)); +unused_dc(11) <= or_reduce(bcfg_q_b(48 to 51)); +unused_dc(12) <= or_reduce(bcfg_q_b(52 to 61)); +unused_dc(13) <= or_reduce(bcfg_q_b(62 to 77)); +unused_dc(14) <= or_reduce(bcfg_q_b(78 to 81)); +unused_dc(15) <= or_reduce(bcfg_q_b(82 to 86)); +unused_dc(16) <= or_reduce(ex1_ra_entry_q); +unused_dc(17) <= or_reduce(ex1_rs_is_q); +unused_dc(18) <= or_reduce(ex6_rs_is_q); +unused_dc(19) <= pc_func_sl_thold_0_b or pc_func_sl_force; +unused_dc(20) <= cam_mpw1_b(4) or cam_delay_lclkr(4); +unused_dc(21) <= or_reduce(ex1_ttype_q(ttype_width-2 to ttype_width)); +-- bit 22 used elsewhere +unused_dc(23) <= ex7_ttype_q(0); +unused_dc(24) <= or_reduce(ex7_ttype_q(2 TO 5)); +unused_dc(25) <= or_reduce(por_wr_array_data(51 to 67)); +unused_dc(26) <= or_reduce(bcfg_q_b(87 to 102)); +unused_dc(27) <= or_reduce(bcfg_q_b(103 to 106)); +unused_dc(28) <= or_reduce(bcfg_q(108 to 122)); +unused_dc(29) <= or_reduce(bcfg_q_b(107 to 122)); +----------------------------------------------------------------------- +-- Latches +----------------------------------------------------------------------- +ex1_valid_latch: tri_rlmreg_p + generic map (width => ex1_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex1_valid_offset to ex1_valid_offset+ex1_valid_q'length-1), + scout => sov_0(ex1_valid_offset to ex1_valid_offset+ex1_valid_q'length-1), + din => ex1_valid_d(0 to thdid_width-1), + dout => ex1_valid_q(0 to thdid_width-1) ); +ex1_ttype_latch: tri_rlmreg_p + generic map (width => ex1_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex1_ttype_offset to ex1_ttype_offset+ex1_ttype_q'length-1), + scout => sov_0(ex1_ttype_offset to ex1_ttype_offset+ex1_ttype_q'length-1), + din => ex1_ttype_d, + dout => ex1_ttype_q ); +ex1_ws_latch: tri_rlmreg_p + generic map (width => ex1_ws_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex1_ws_offset to ex1_ws_offset+ex1_ws_q'length-1), + scout => sov_0(ex1_ws_offset to ex1_ws_offset+ex1_ws_q'length-1), + din => ex1_ws_d(0 to ws_width-1), + dout => ex1_ws_q(0 to ws_width-1) ); +ex1_rs_is_latch: tri_rlmreg_p + generic map (width => ex1_rs_is_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex1_rs_is_offset to ex1_rs_is_offset+ex1_rs_is_q'length-1), + scout => sov_0(ex1_rs_is_offset to ex1_rs_is_offset+ex1_rs_is_q'length-1), + din => ex1_rs_is_d(0 to rs_is_width-1), + dout => ex1_rs_is_q(0 to rs_is_width-1) ); +ex1_ra_entry_latch: tri_rlmreg_p + generic map (width => ex1_ra_entry_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex1_ra_entry_offset to ex1_ra_entry_offset+ex1_ra_entry_q'length-1), + scout => sov_0(ex1_ra_entry_offset to ex1_ra_entry_offset+ex1_ra_entry_q'length-1), + din => ex1_ra_entry_d(0 to ra_entry_width-1), + dout => ex1_ra_entry_q(0 to ra_entry_width-1) ); +ex1_state_latch: tri_rlmreg_p + generic map (width => ex1_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex1_state_offset to ex1_state_offset+ex1_state_q'length-1), + scout => sov_0(ex1_state_offset to ex1_state_offset+ex1_state_q'length-1), + din => ex1_state_d(0 to state_width-1), + dout => ex1_state_q(0 to state_width-1) ); +ex1_pid_latch: tri_rlmreg_p + generic map (width => ex1_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex1_pid_offset to ex1_pid_offset+ex1_pid_q'length-1), + scout => sov_0(ex1_pid_offset to ex1_pid_offset+ex1_pid_q'length-1), + din => ex1_pid_d, + dout => ex1_pid_q ); +ex1_extclass_latch: tri_rlmreg_p + generic map (width => ex1_extclass_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex1_extclass_offset to ex1_extclass_offset+ex1_extclass_q'length-1), + scout => sov_0(ex1_extclass_offset to ex1_extclass_offset+ex1_extclass_q'length-1), + din => ex1_extclass_d(0 to extclass_width-1), + dout => ex1_extclass_q(0 to extclass_width-1) ); +ex1_tlbsel_latch: tri_rlmreg_p + generic map (width => ex1_tlbsel_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex1_tlbsel_offset to ex1_tlbsel_offset+ex1_tlbsel_q'length-1), + scout => sov_0(ex1_tlbsel_offset to ex1_tlbsel_offset+ex1_tlbsel_q'length-1), + din => ex1_tlbsel_d(0 to tlbsel_width-1), + dout => ex1_tlbsel_q(0 to tlbsel_width-1) ); +------------------------------------------------------------------------------- +ex2_valid_latch: tri_rlmreg_p + generic map (width => ex2_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex2_valid_offset to ex2_valid_offset+ex2_valid_q'length-1), + scout => sov_0(ex2_valid_offset to ex2_valid_offset+ex2_valid_q'length-1), + din => ex2_valid_d(0 to thdid_width-1), + dout => ex2_valid_q(0 to thdid_width-1) ); +ex2_ttype_latch: tri_rlmreg_p + generic map (width => ex2_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex2_ttype_offset to ex2_ttype_offset+ex2_ttype_q'length-1), + scout => sov_0(ex2_ttype_offset to ex2_ttype_offset+ex2_ttype_q'length-1), + din => ex2_ttype_d(0 to ttype_width-1), + dout => ex2_ttype_q(0 to ttype_width-1) ); +ex2_ws_latch: tri_rlmreg_p + generic map (width => ex2_ws_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex2_ws_offset to ex2_ws_offset+ex2_ws_q'length-1), + scout => sov_0(ex2_ws_offset to ex2_ws_offset+ex2_ws_q'length-1), + din => ex2_ws_d(0 to ws_width-1), + dout => ex2_ws_q(0 to ws_width-1) ); +ex2_rs_is_latch: tri_rlmreg_p + generic map (width => ex2_rs_is_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex2_rs_is_offset to ex2_rs_is_offset+ex2_rs_is_q'length-1), + scout => sov_0(ex2_rs_is_offset to ex2_rs_is_offset+ex2_rs_is_q'length-1), + din => ex2_rs_is_d(0 to rs_is_width-1), + dout => ex2_rs_is_q(0 to rs_is_width-1) ); +ex2_ra_entry_latch: tri_rlmreg_p + generic map (width => ex2_ra_entry_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex2_ra_entry_offset to ex2_ra_entry_offset+ex2_ra_entry_q'length-1), + scout => sov_0(ex2_ra_entry_offset to ex2_ra_entry_offset+ex2_ra_entry_q'length-1), + din => ex2_ra_entry_d(0 to ra_entry_width-1), + dout => ex2_ra_entry_q(0 to ra_entry_width-1) ); +ex2_state_latch: tri_rlmreg_p + generic map (width => ex2_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex2_state_offset to ex2_state_offset+ex2_state_q'length-1), + scout => sov_0(ex2_state_offset to ex2_state_offset+ex2_state_q'length-1), + din => ex2_state_d(0 to state_width-1), + dout => ex2_state_q(0 to state_width-1) ); +ex2_pid_latch: tri_rlmreg_p + generic map (width => ex2_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex2_pid_offset to ex2_pid_offset+ex2_pid_q'length-1), + scout => sov_0(ex2_pid_offset to ex2_pid_offset+ex2_pid_q'length-1), + din => ex2_pid_d, + dout => ex2_pid_q ); +ex2_extclass_latch: tri_rlmreg_p + generic map (width => ex2_extclass_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex2_extclass_offset to ex2_extclass_offset+ex2_extclass_q'length-1), + scout => sov_0(ex2_extclass_offset to ex2_extclass_offset+ex2_extclass_q'length-1), + din => ex2_extclass_d(0 to extclass_width-1), + dout => ex2_extclass_q(0 to extclass_width-1) ); +ex2_tlbsel_latch: tri_rlmreg_p + generic map (width => ex2_tlbsel_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex2_tlbsel_offset to ex2_tlbsel_offset+ex2_tlbsel_q'length-1), + scout => sov_0(ex2_tlbsel_offset to ex2_tlbsel_offset+ex2_tlbsel_q'length-1), + din => ex2_tlbsel_d(0 to tlbsel_width-1), + dout => ex2_tlbsel_q(0 to tlbsel_width-1) ); +------------------------------------------------------------------------------- +ex3_valid_latch: tri_rlmreg_p + generic map (width => ex3_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_valid_offset to ex3_valid_offset+ex3_valid_q'length-1), + scout => sov_0(ex3_valid_offset to ex3_valid_offset+ex3_valid_q'length-1), + din => ex3_valid_d(0 to thdid_width-1), + dout => ex3_valid_q(0 to thdid_width-1) ); +ex3_ttype_latch: tri_rlmreg_p + generic map (width => ex3_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_ttype_offset to ex3_ttype_offset+ex3_ttype_q'length-1), + scout => sov_0(ex3_ttype_offset to ex3_ttype_offset+ex3_ttype_q'length-1), + din => ex3_ttype_d(0 to ttype_width-1), + dout => ex3_ttype_q(0 to ttype_width-1) ); +ex3_ws_latch: tri_rlmreg_p + generic map (width => ex3_ws_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_ws_offset to ex3_ws_offset+ex3_ws_q'length-1), + scout => sov_0(ex3_ws_offset to ex3_ws_offset+ex3_ws_q'length-1), + din => ex3_ws_d(0 to ws_width-1), + dout => ex3_ws_q(0 to ws_width-1) ); +ex3_rs_is_latch: tri_rlmreg_p + generic map (width => ex3_rs_is_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_rs_is_offset to ex3_rs_is_offset+ex3_rs_is_q'length-1), + scout => sov_0(ex3_rs_is_offset to ex3_rs_is_offset+ex3_rs_is_q'length-1), + din => ex3_rs_is_d(0 to rs_is_width-1), + dout => ex3_rs_is_q(0 to rs_is_width-1) ); +ex3_ra_entry_latch: tri_rlmreg_p + generic map (width => ex3_ra_entry_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_ra_entry_offset to ex3_ra_entry_offset+ex3_ra_entry_q'length-1), + scout => sov_0(ex3_ra_entry_offset to ex3_ra_entry_offset+ex3_ra_entry_q'length-1), + din => ex3_ra_entry_d(0 to ra_entry_width-1), + dout => ex3_ra_entry_q(0 to ra_entry_width-1) ); +ex3_state_latch: tri_rlmreg_p + generic map (width => ex3_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_state_offset to ex3_state_offset+ex3_state_q'length-1), + scout => sov_0(ex3_state_offset to ex3_state_offset+ex3_state_q'length-1), + din => ex3_state_d(0 to state_width-1), + dout => ex3_state_q(0 to state_width-1) ); +ex3_pid_latch: tri_rlmreg_p + generic map (width => ex3_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_pid_offset to ex3_pid_offset+ex3_pid_q'length-1), + scout => sov_0(ex3_pid_offset to ex3_pid_offset+ex3_pid_q'length-1), + din => ex3_pid_d, + dout => ex3_pid_q ); +ex3_extclass_latch: tri_rlmreg_p + generic map (width => ex3_extclass_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_extclass_offset to ex3_extclass_offset+ex3_extclass_q'length-1), + scout => sov_0(ex3_extclass_offset to ex3_extclass_offset+ex3_extclass_q'length-1), + din => ex3_extclass_d(0 to extclass_width-1), + dout => ex3_extclass_q(0 to extclass_width-1) ); +ex3_tlbsel_latch: tri_rlmreg_p + generic map (width => ex3_tlbsel_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_tlbsel_offset to ex3_tlbsel_offset+ex3_tlbsel_q'length-1), + scout => sov_0(ex3_tlbsel_offset to ex3_tlbsel_offset+ex3_tlbsel_q'length-1), + din => ex3_tlbsel_d(0 to tlbsel_width-1), + dout => ex3_tlbsel_q(0 to tlbsel_width-1) ); +ex3_eratsx_data_latch: tri_rlmreg_p + generic map (width => ex3_eratsx_data_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => eratsx_data_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_eratsx_data_offset to ex3_eratsx_data_offset+ex3_eratsx_data_q'length-1), + scout => sov_0(ex3_eratsx_data_offset to ex3_eratsx_data_offset+ex3_eratsx_data_q'length-1), + din => ex3_eratsx_data_d(0 to 2+num_entry_log2-1), + dout => ex3_eratsx_data_q(0 to 2+num_entry_log2-1) ); +------------------------------------------------------------------------------- +ex4_valid_latch: tri_rlmreg_p + generic map (width => ex4_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex4_valid_offset to ex4_valid_offset+ex4_valid_q'length-1), + scout => sov_0(ex4_valid_offset to ex4_valid_offset+ex4_valid_q'length-1), + din => ex4_valid_d(0 to thdid_width-1), + dout => ex4_valid_q(0 to thdid_width-1) ); +ex4_ttype_latch: tri_rlmreg_p + generic map (width => ex4_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex4_ttype_offset to ex4_ttype_offset+ex4_ttype_q'length-1), + scout => sov_0(ex4_ttype_offset to ex4_ttype_offset+ex4_ttype_q'length-1), + din => ex4_ttype_d(0 to ttype_width-1), + dout => ex4_ttype_q(0 to ttype_width-1) ); +ex4_ws_latch: tri_rlmreg_p + generic map (width => ex4_ws_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex4_ws_offset to ex4_ws_offset+ex4_ws_q'length-1), + scout => sov_0(ex4_ws_offset to ex4_ws_offset+ex4_ws_q'length-1), + din => ex4_ws_d(0 to ws_width-1), + dout => ex4_ws_q(0 to ws_width-1) ); +ex4_rs_is_latch: tri_rlmreg_p + generic map (width => ex4_rs_is_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex4_rs_is_offset to ex4_rs_is_offset+ex4_rs_is_q'length-1), + scout => sov_0(ex4_rs_is_offset to ex4_rs_is_offset+ex4_rs_is_q'length-1), + din => ex4_rs_is_d(0 to rs_is_width-1), + dout => ex4_rs_is_q(0 to rs_is_width-1) ); +ex4_ra_entry_latch: tri_rlmreg_p + generic map (width => ex4_ra_entry_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex4_ra_entry_offset to ex4_ra_entry_offset+ex4_ra_entry_q'length-1), + scout => sov_0(ex4_ra_entry_offset to ex4_ra_entry_offset+ex4_ra_entry_q'length-1), + din => ex4_ra_entry_d(0 to ra_entry_width-1), + dout => ex4_ra_entry_q(0 to ra_entry_width-1) ); +ex4_state_latch: tri_rlmreg_p + generic map (width => ex4_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex4_state_offset to ex4_state_offset+ex4_state_q'length-1), + scout => sov_0(ex4_state_offset to ex4_state_offset+ex4_state_q'length-1), + din => ex4_state_d(0 to state_width-1), + dout => ex4_state_q(0 to state_width-1) ); +ex4_pid_latch: tri_rlmreg_p + generic map (width => ex4_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex4_pid_offset to ex4_pid_offset+ex4_pid_q'length-1), + scout => sov_0(ex4_pid_offset to ex4_pid_offset+ex4_pid_q'length-1), + din => ex4_pid_d, + dout => ex4_pid_q ); +ex4_extclass_latch: tri_rlmreg_p + generic map (width => ex4_extclass_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex4_extclass_offset to ex4_extclass_offset+ex4_extclass_q'length-1), + scout => sov_0(ex4_extclass_offset to ex4_extclass_offset+ex4_extclass_q'length-1), + din => ex4_extclass_d(0 to extclass_width-1), + dout => ex4_extclass_q(0 to extclass_width-1) ); +ex4_tlbsel_latch: tri_rlmreg_p + generic map (width => ex4_tlbsel_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex4_tlbsel_offset to ex4_tlbsel_offset+ex4_tlbsel_q'length-1), + scout => sov_0(ex4_tlbsel_offset to ex4_tlbsel_offset+ex4_tlbsel_q'length-1), + din => ex4_tlbsel_d(0 to tlbsel_width-1), + dout => ex4_tlbsel_q(0 to tlbsel_width-1) ); +-------------------------------------------------- +ex4_data_out_latch: tri_rlmreg_p + generic map (width => ex4_data_out_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_data_out_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex4_data_out_offset to ex4_data_out_offset+ex4_data_out_q'length-1), + scout => sov_0(ex4_data_out_offset to ex4_data_out_offset+ex4_data_out_q'length-1), + din => ex4_data_out_d(64-data_out_width to 63), + dout => ex4_data_out_q(64-data_out_width to 63) ); +------------------------------------------------------------------------------- +ex5_valid_latch: tri_rlmreg_p + generic map (width => ex5_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex5_valid_offset to ex5_valid_offset+ex5_valid_q'length-1), + scout => sov_0(ex5_valid_offset to ex5_valid_offset+ex5_valid_q'length-1), + din => ex5_valid_d(0 to thdid_width-1), + dout => ex5_valid_q(0 to thdid_width-1) ); +ex5_ttype_latch: tri_rlmreg_p + generic map (width => ex5_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex5_ttype_offset to ex5_ttype_offset+ex5_ttype_q'length-1), + scout => sov_0(ex5_ttype_offset to ex5_ttype_offset+ex5_ttype_q'length-1), + din => ex5_ttype_d(0 to ttype_width-1), + dout => ex5_ttype_q(0 to ttype_width-1) ); +ex5_ws_latch: tri_rlmreg_p + generic map (width => ex5_ws_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex5_ws_offset to ex5_ws_offset+ex5_ws_q'length-1), + scout => sov_0(ex5_ws_offset to ex5_ws_offset+ex5_ws_q'length-1), + din => ex5_ws_d(0 to ws_width-1), + dout => ex5_ws_q(0 to ws_width-1) ); +ex5_rs_is_latch: tri_rlmreg_p + generic map (width => ex5_rs_is_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex5_rs_is_offset to ex5_rs_is_offset+ex5_rs_is_q'length-1), + scout => sov_0(ex5_rs_is_offset to ex5_rs_is_offset+ex5_rs_is_q'length-1), + din => ex5_rs_is_d(0 to rs_is_width-1), + dout => ex5_rs_is_q(0 to rs_is_width-1) ); +ex5_ra_entry_latch: tri_rlmreg_p + generic map (width => ex5_ra_entry_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex5_ra_entry_offset to ex5_ra_entry_offset+ex5_ra_entry_q'length-1), + scout => sov_0(ex5_ra_entry_offset to ex5_ra_entry_offset+ex5_ra_entry_q'length-1), + din => ex5_ra_entry_d(0 to ra_entry_width-1), + dout => ex5_ra_entry_q(0 to ra_entry_width-1) ); +ex5_state_latch: tri_rlmreg_p + generic map (width => ex5_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex5_state_offset to ex5_state_offset+ex5_state_q'length-1), + scout => sov_0(ex5_state_offset to ex5_state_offset+ex5_state_q'length-1), + din => ex5_state_d(0 to state_width-1), + dout => ex5_state_q(0 to state_width-1) ); +ex5_pid_latch: tri_rlmreg_p + generic map (width => ex5_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex5_pid_offset to ex5_pid_offset+ex5_pid_q'length-1), + scout => sov_0(ex5_pid_offset to ex5_pid_offset+ex5_pid_q'length-1), + din => ex5_pid_d, + dout => ex5_pid_q ); +ex5_extclass_latch: tri_rlmreg_p + generic map (width => ex5_extclass_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex5_extclass_offset to ex5_extclass_offset+ex5_extclass_q'length-1), + scout => sov_0(ex5_extclass_offset to ex5_extclass_offset+ex5_extclass_q'length-1), + din => ex5_extclass_d(0 to extclass_width-1), + dout => ex5_extclass_q(0 to extclass_width-1) ); +ex5_tlbsel_latch: tri_rlmreg_p + generic map (width => ex5_tlbsel_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex5_tlbsel_offset to ex5_tlbsel_offset+ex5_tlbsel_q'length-1), + scout => sov_0(ex5_tlbsel_offset to ex5_tlbsel_offset+ex5_tlbsel_q'length-1), + din => ex5_tlbsel_d(0 to tlbsel_width-1), + dout => ex5_tlbsel_q(0 to tlbsel_width-1) ); +-------------------------------------------------- +ex5_data_in_latch: tri_rlmreg_p + generic map (width => ex5_data_in_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex5_data_in_offset to ex5_data_in_offset+ex5_data_in_q'length-1), + scout => sov_0(ex5_data_in_offset to ex5_data_in_offset+ex5_data_in_q'length-1), + din => ex5_data_in_d(64-rs_data_width to 63), + dout => ex5_data_in_q(64-rs_data_width to 63) ); +------------------------------------------------------------------------------- +ex6_valid_latch: tri_rlmreg_p + generic map (width => ex6_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex6_valid_offset to ex6_valid_offset+ex6_valid_q'length-1), + scout => sov_0(ex6_valid_offset to ex6_valid_offset+ex6_valid_q'length-1), + din => ex6_valid_d(0 to thdid_width-1), + dout => ex6_valid_q(0 to thdid_width-1) ); +ex6_ttype_latch: tri_rlmreg_p + generic map (width => ex6_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex6_ttype_offset to ex6_ttype_offset+ex6_ttype_q'length-1), + scout => sov_0(ex6_ttype_offset to ex6_ttype_offset+ex6_ttype_q'length-1), + din => ex6_ttype_d(0 to ttype_width-1), + dout => ex6_ttype_q(0 to ttype_width-1) ); +ex6_ws_latch: tri_rlmreg_p + generic map (width => ex6_ws_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex5_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex6_ws_offset to ex6_ws_offset+ex6_ws_q'length-1), + scout => sov_0(ex6_ws_offset to ex6_ws_offset+ex6_ws_q'length-1), + din => ex6_ws_d(0 to ws_width-1), + dout => ex6_ws_q(0 to ws_width-1) ); +ex6_rs_is_latch: tri_rlmreg_p + generic map (width => ex6_rs_is_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex5_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex6_rs_is_offset to ex6_rs_is_offset+ex6_rs_is_q'length-1), + scout => sov_0(ex6_rs_is_offset to ex6_rs_is_offset+ex6_rs_is_q'length-1), + din => ex6_rs_is_d(0 to rs_is_width-1), + dout => ex6_rs_is_q(0 to rs_is_width-1) ); +ex6_ra_entry_latch: tri_rlmreg_p + generic map (width => ex6_ra_entry_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex5_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex6_ra_entry_offset to ex6_ra_entry_offset+ex6_ra_entry_q'length-1), + scout => sov_0(ex6_ra_entry_offset to ex6_ra_entry_offset+ex6_ra_entry_q'length-1), + din => ex6_ra_entry_d(0 to ra_entry_width-1), + dout => ex6_ra_entry_q(0 to ra_entry_width-1) ); +ex6_state_latch: tri_rlmreg_p + generic map (width => ex6_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex5_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex6_state_offset to ex6_state_offset+ex6_state_q'length-1), + scout => sov_0(ex6_state_offset to ex6_state_offset+ex6_state_q'length-1), + din => ex6_state_d(0 to state_width-1), + dout => ex6_state_q(0 to state_width-1) ); +ex6_pid_latch: tri_rlmreg_p + generic map (width => ex6_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex5_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex6_pid_offset to ex6_pid_offset+ex6_pid_q'length-1), + scout => sov_0(ex6_pid_offset to ex6_pid_offset+ex6_pid_q'length-1), + din => ex6_pid_d, + dout => ex6_pid_q ); +ex6_extclass_latch: tri_rlmreg_p + generic map (width => ex6_extclass_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex5_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex6_extclass_offset to ex6_extclass_offset+ex6_extclass_q'length-1), + scout => sov_0(ex6_extclass_offset to ex6_extclass_offset+ex6_extclass_q'length-1), + din => ex6_extclass_d(0 to extclass_width-1), + dout => ex6_extclass_q(0 to extclass_width-1) ); +ex6_tlbsel_latch: tri_rlmreg_p + generic map (width => ex6_tlbsel_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex5_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex6_tlbsel_offset to ex6_tlbsel_offset+ex6_tlbsel_q'length-1), + scout => sov_0(ex6_tlbsel_offset to ex6_tlbsel_offset+ex6_tlbsel_q'length-1), + din => ex6_tlbsel_d(0 to tlbsel_width-1), + dout => ex6_tlbsel_q(0 to tlbsel_width-1) ); +-------------------------------------------------- +ex6_data_in_latch: tri_rlmreg_p + generic map (width => ex6_data_in_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex5_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex6_data_in_offset to ex6_data_in_offset+ex6_data_in_q'length-1), + scout => sov_0(ex6_data_in_offset to ex6_data_in_offset+ex6_data_in_q'length-1), + din => ex6_data_in_d(64-rs_data_width to 63), + dout => ex6_data_in_q(64-rs_data_width to 63) ); +-------------------------------------------------- +ex7_valid_latch: tri_rlmreg_p + generic map (width => ex7_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ex7_valid_offset to ex7_valid_offset+ex7_valid_q'length-1), + scout => sov_1(ex7_valid_offset to ex7_valid_offset+ex7_valid_q'length-1), + din => ex7_valid_d(0 to thdid_width-1), + dout => ex7_valid_q(0 to thdid_width-1) ); +ex7_ttype_latch: tri_rlmreg_p + generic map (width => ex7_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ex7_ttype_offset to ex7_ttype_offset+ex7_ttype_q'length-1), + scout => sov_1(ex7_ttype_offset to ex7_ttype_offset+ex7_ttype_q'length-1), + din => ex7_ttype_d(0 to ttype_width-1), + dout => ex7_ttype_q(0 to ttype_width-1) ); +ex7_tlbsel_latch: tri_rlmreg_p + generic map (width => ex7_tlbsel_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex6_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ex7_tlbsel_offset to ex7_tlbsel_offset+ex7_tlbsel_q'length-1), + scout => sov_1(ex7_tlbsel_offset to ex7_tlbsel_offset+ex7_tlbsel_q'length-1), + din => ex7_tlbsel_d(0 to tlbsel_width-1), + dout => ex7_tlbsel_q(0 to tlbsel_width-1) ); +iu1_flush_enab_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(iu1_flush_enab_offset), + scout => sov_0(iu1_flush_enab_offset), + din => iu1_flush_enab_d, + dout => iu1_flush_enab_q); +iu2_n_flush_req_latch: tri_rlmreg_p + generic map (width => iu2_n_flush_req_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu1_or_iu2_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(iu2_n_flush_req_offset to iu2_n_flush_req_offset+iu2_n_flush_req_q'length-1), + scout => sov_0(iu2_n_flush_req_offset to iu2_n_flush_req_offset+iu2_n_flush_req_q'length-1), + din => iu2_n_flush_req_d(0 to thdid_width-1), + dout => iu2_n_flush_req_q(0 to thdid_width-1) ); +hold_req_latch: tri_rlmreg_p + generic map (width => hold_req_q'length, init => 15, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => not_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(hold_req_offset to hold_req_offset+hold_req_q'length-1), + scout => sov_0(hold_req_offset to hold_req_offset+hold_req_q'length-1), + din => hold_req_d(0 to thdid_width-1), + dout => hold_req_q(0 to thdid_width-1) ); +tlb_miss_latch: tri_rlmreg_p + generic map (width => tlb_miss_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_miss_offset to tlb_miss_offset+tlb_miss_q'length-1), + scout => sov_0(tlb_miss_offset to tlb_miss_offset+tlb_miss_q'length-1), + din => tlb_miss_d(0 to thdid_width-1), + dout => tlb_miss_q(0 to thdid_width-1) ); +tlb_req_inprogress_latch: tri_rlmreg_p + generic map (width => tlb_req_inprogress_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_req_inprogress_offset to tlb_req_inprogress_offset+tlb_req_inprogress_q'length-1), + scout => sov_0(tlb_req_inprogress_offset to tlb_req_inprogress_offset+tlb_req_inprogress_q'length-1), + din => tlb_req_inprogress_d(0 to thdid_width-1), + dout => tlb_req_inprogress_q(0 to thdid_width-1) ); +iu1_valid_latch: tri_rlmreg_p + generic map (width => iu1_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(iu1_valid_offset to iu1_valid_offset+iu1_valid_q'length-1), + scout => sov_0(iu1_valid_offset to iu1_valid_offset+iu1_valid_q'length-1), + din => iu1_valid_d(0 to thdid_width-1), + dout => iu1_valid_q(0 to thdid_width-1) ); +iu1_state_latch: tri_rlmreg_p + generic map (width => iu1_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(iu1_state_offset to iu1_state_offset+iu1_state_q'length-1), + scout => sov_0(iu1_state_offset to iu1_state_offset+iu1_state_q'length-1), + din => iu1_state_d(0 to state_width-1), + dout => iu1_state_q(0 to state_width-1) ); +iu1_pid_latch: tri_rlmreg_p + generic map (width => iu1_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(iu1_pid_offset to iu1_pid_offset+iu1_pid_q'length-1), + scout => sov_0(iu1_pid_offset to iu1_pid_offset+iu1_pid_q'length-1), + din => iu1_pid_d, + dout => iu1_pid_q ); +iu2_valid_latch: tri_rlmreg_p + generic map (width => iu2_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(iu2_valid_offset to iu2_valid_offset+iu2_valid_q'length-1), + scout => sov_0(iu2_valid_offset to iu2_valid_offset+iu2_valid_q'length-1), + din => iu2_valid_d(0 to thdid_width-1), + dout => iu2_valid_q(0 to thdid_width-1) ); +iu2_state_latch: tri_rlmreg_p + generic map (width => iu2_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu1_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(iu2_state_offset to iu2_state_offset+iu2_state_q'length-1), + scout => sov_0(iu2_state_offset to iu2_state_offset+iu2_state_q'length-1), + din => iu2_state_d(0 to state_width-1), + dout => iu2_state_q(0 to state_width-1) ); +iu2_pid_latch: tri_rlmreg_p + generic map (width => iu2_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu1_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(iu2_pid_offset to iu2_pid_offset+iu2_pid_q'length-1), + scout => sov_0(iu2_pid_offset to iu2_pid_offset+iu2_pid_q'length-1), + din => iu2_pid_d, + dout => iu2_pid_q ); +iu2_miss_latch: tri_rlmreg_p + generic map (width => iu2_miss_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu1_or_iu2_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(iu2_miss_offset to iu2_miss_offset+iu2_miss_q'length-1), + scout => sov_0(iu2_miss_offset to iu2_miss_offset+iu2_miss_q'length-1), + din => iu2_miss_d, + dout => iu2_miss_q ); +iu2_multihit_latch: tri_rlmreg_p + generic map (width => iu2_multihit_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu1_or_iu2_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(iu2_multihit_offset to iu2_multihit_offset+iu2_multihit_q'length-1), + scout => sov_0(iu2_multihit_offset to iu2_multihit_offset+iu2_multihit_q'length-1), + din => iu2_multihit_d, + dout => iu2_multihit_q ); +iu2_parerr_latch: tri_rlmreg_p + generic map (width => iu2_parerr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu1_or_iu2_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(iu2_parerr_offset to iu2_parerr_offset+iu2_parerr_q'length-1), + scout => sov_0(iu2_parerr_offset to iu2_parerr_offset+iu2_parerr_q'length-1), + din => iu2_parerr_d, + dout => iu2_parerr_q ); +iu2_isi_latch: tri_rlmreg_p + generic map (width => iu2_isi_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => not_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(iu2_isi_offset to iu2_isi_offset+iu2_isi_q'length-1), + scout => sov_0(iu2_isi_offset to iu2_isi_offset+iu2_isi_q'length-1), + din => iu2_isi_d, + dout => iu2_isi_q ); +iu2_tlbreq_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => notlb_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(iu2_tlbreq_offset), + scout => sov_0(iu2_tlbreq_offset), + din => iu2_tlbreq_d, + dout => iu2_tlbreq_q); +iu2_multihit_b_pt_latch: tri_rlmreg_p + generic map (width => iu2_multihit_b_pt_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu1_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(iu2_multihit_b_pt_offset to iu2_multihit_b_pt_offset+iu2_multihit_b_pt_q'length-1), + scout => sov_0(iu2_multihit_b_pt_offset to iu2_multihit_b_pt_offset+iu2_multihit_b_pt_q'length-1), + din => iu2_multihit_b_pt_d, + dout => iu2_multihit_b_pt_q ); +iu2_first_hit_entry_pt_latch: tri_rlmreg_p + generic map (width => iu2_first_hit_entry_pt_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu1_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(iu2_first_hit_entry_pt_offset to iu2_first_hit_entry_pt_offset+iu2_first_hit_entry_pt_q'length-1), + scout => sov_0(iu2_first_hit_entry_pt_offset to iu2_first_hit_entry_pt_offset+iu2_first_hit_entry_pt_q'length-1), + din => iu2_first_hit_entry_pt_d, + dout => iu2_first_hit_entry_pt_q ); +iu2_cam_cmp_data_latch: tri_rlmreg_p + generic map (width => iu2_cam_cmp_data_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu1_cmp_data_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(iu2_cam_cmp_data_offset to iu2_cam_cmp_data_offset+iu2_cam_cmp_data_q'length-1), + scout => sov_0(iu2_cam_cmp_data_offset to iu2_cam_cmp_data_offset+iu2_cam_cmp_data_q'length-1), + din => iu2_cam_cmp_data_d(0 to cam_data_width-1), + dout => iu2_cam_cmp_data_q(0 to cam_data_width-1)); +iu2_array_cmp_data_latch: tri_rlmreg_p + generic map (width => iu2_array_cmp_data_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu1_cmp_data_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(iu2_array_cmp_data_offset to iu2_array_cmp_data_offset+iu2_array_cmp_data_q'length-1), + scout => sov_0(iu2_array_cmp_data_offset to iu2_array_cmp_data_offset+iu2_array_cmp_data_q'length-1), + din => iu2_array_cmp_data_d(0 to array_data_width-1), + dout => iu2_array_cmp_data_q(0 to array_data_width-1)); +ex4_rd_cam_data_latch: tri_rlmreg_p + generic map (width => ex4_rd_cam_data_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_rd_data_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex4_rd_cam_data_offset to ex4_rd_cam_data_offset+ex4_rd_cam_data_q'length-1), + scout => sov_0(ex4_rd_cam_data_offset to ex4_rd_cam_data_offset+ex4_rd_cam_data_q'length-1), + din => ex4_rd_cam_data_d(0 to cam_data_width-1), + dout => ex4_rd_cam_data_q(0 to cam_data_width-1)); +ex4_rd_array_data_latch: tri_rlmreg_p + generic map (width => ex4_rd_array_data_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_rd_data_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex4_rd_array_data_offset to ex4_rd_array_data_offset+ex4_rd_array_data_q'length-1), + scout => sov_0(ex4_rd_array_data_offset to ex4_rd_array_data_offset+ex4_rd_array_data_q'length-1), + din => ex4_rd_array_data_d(0 to array_data_width-1), + dout => ex4_rd_array_data_q(0 to array_data_width-1)); +ex3_parerr_latch: tri_rlmreg_p + generic map (width => ex3_parerr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => not_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_parerr_offset to ex3_parerr_offset+ex3_parerr_q'length-1), + scout => sov_0(ex3_parerr_offset to ex3_parerr_offset+ex3_parerr_q'length-1), + din => ex3_parerr_d, + dout => ex3_parerr_q ); +ex4_parerr_latch: tri_rlmreg_p + generic map (width => ex4_parerr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex4_parerr_offset to ex4_parerr_offset+ex4_parerr_q'length-1), + scout => sov_0(ex4_parerr_offset to ex4_parerr_offset+ex4_parerr_q'length-1), + din => ex4_parerr_d, + dout => ex4_parerr_q ); +ex4_ieen_latch: tri_rlmreg_p + generic map (width => ex4_ieen_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex4_ieen_offset to ex4_ieen_offset+ex4_ieen_q'length-1), + scout => sov_0(ex4_ieen_offset to ex4_ieen_offset+ex4_ieen_q'length-1), + din => ex4_ieen_d(0 to ex4_ieen_d'length-1), + dout => ex4_ieen_q(0 to ex4_ieen_q'length-1)); +ex5_ieen_latch: tri_rlmreg_p + generic map (width => ex5_ieen_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex5_ieen_offset to ex5_ieen_offset+ex5_ieen_q'length-1), + scout => sov_0(ex5_ieen_offset to ex5_ieen_offset+ex5_ieen_q'length-1), + din => ex5_ieen_d(0 to ex5_ieen_d'length-1), + dout => ex5_ieen_q(0 to ex5_ieen_q'length-1)); +ex6_ieen_latch: tri_rlmreg_p + generic map (width => ex6_ieen_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex6_ieen_offset to ex6_ieen_offset+ex6_ieen_q'length-1), + scout => sov_0(ex6_ieen_offset to ex6_ieen_offset+ex6_ieen_q'length-1), + din => ex6_ieen_d(0 to ex6_ieen_d'length-1), + dout => ex6_ieen_q(0 to ex6_ieen_q'length-1)); +mmucr1_latch: tri_rlmreg_p + generic map (width => mmucr1_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(mmucr1_offset to mmucr1_offset+mmucr1_q'length-1), + scout => sov_0(mmucr1_offset to mmucr1_offset+mmucr1_q'length-1), + din => mmucr1_d, + dout => mmucr1_q ); +rpn_holdreg0_latch: tri_rlmreg_p + generic map (width => rpn_holdreg0_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex6_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(rpn_holdreg0_offset to rpn_holdreg0_offset+rpn_holdreg0_q'length-1), + scout => sov_0(rpn_holdreg0_offset to rpn_holdreg0_offset+rpn_holdreg0_q'length-1), + din => rpn_holdreg0_d(0 to 63), + dout => rpn_holdreg0_q(0 to 63) ); +rpn_holdreg1_latch: tri_rlmreg_p + generic map (width => rpn_holdreg1_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex6_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(rpn_holdreg1_offset to rpn_holdreg1_offset+rpn_holdreg1_q'length-1), + scout => sov_0(rpn_holdreg1_offset to rpn_holdreg1_offset+rpn_holdreg1_q'length-1), + din => rpn_holdreg1_d(0 to 63), + dout => rpn_holdreg1_q(0 to 63) ); +rpn_holdreg2_latch: tri_rlmreg_p + generic map (width => rpn_holdreg2_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex6_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(rpn_holdreg2_offset to rpn_holdreg2_offset+rpn_holdreg2_q'length-1), + scout => sov_0(rpn_holdreg2_offset to rpn_holdreg2_offset+rpn_holdreg2_q'length-1), + din => rpn_holdreg2_d(0 to 63), + dout => rpn_holdreg2_q(0 to 63) ); +rpn_holdreg3_latch: tri_rlmreg_p + generic map (width => rpn_holdreg3_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex6_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(rpn_holdreg3_offset to rpn_holdreg3_offset+rpn_holdreg3_q'length-1), + scout => sov_0(rpn_holdreg3_offset to rpn_holdreg3_offset+rpn_holdreg3_q'length-1), + din => rpn_holdreg3_d(0 to 63), + dout => rpn_holdreg3_q(0 to 63) ); +entry_valid_latch: tri_rlmreg_p + generic map (width => entry_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => entry_valid_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(entry_valid_offset to entry_valid_offset+entry_valid_q'length-1), + scout => sov_0(entry_valid_offset to entry_valid_offset+entry_valid_q'length-1), + din => entry_valid, + dout => entry_valid_q ); +entry_match_latch: tri_rlmreg_p + generic map (width => entry_match_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => entry_match_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(entry_match_offset to entry_match_offset+entry_match_q'length-1), + scout => sov_0(entry_match_offset to entry_match_offset+entry_match_q'length-1), + din => entry_match, + dout => entry_match_q ); +watermark_latch: tri_rlmreg_p + generic map (width => watermark_q'length, init => 13, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex6_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(watermark_offset to watermark_offset+watermark_q'length-1), + scout => sov_0(watermark_offset to watermark_offset+watermark_q'length-1), + din => watermark_d(0 to watermark_width-1), + dout => watermark_q(0 to watermark_width-1) ); +eptr_latch: tri_rlmreg_p + generic map (width => eptr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => mmucr1_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(eptr_offset to eptr_offset+eptr_q'length-1), + scout => sov_0(eptr_offset to eptr_offset+eptr_q'length-1), + din => eptr_d(0 to eptr_width-1), + dout => eptr_q(0 to eptr_width-1) ); +lru_latch: tri_rlmreg_p + generic map (width => lru_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lru_update_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(lru_offset to lru_offset+lru_q'length-1), + scout => sov_0(lru_offset to lru_offset+lru_q'length-1), + din => lru_d(1 to lru_width), + dout => lru_q(1 to lru_width) ); +lru_update_event_latch: tri_rlmreg_p + generic map (width => lru_update_event_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => not_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(lru_update_event_offset to lru_update_event_offset+lru_update_event_q'length-1), + scout => sov_0(lru_update_event_offset to lru_update_event_offset+lru_update_event_q'length-1), + din => lru_update_event_d, + dout => lru_update_event_q ); +lru_debug_latch: tri_rlmreg_p + generic map (width => lru_debug_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => debug_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(lru_debug_offset to lru_debug_offset+lru_debug_q'length-1), + scout => sov_0(lru_debug_offset to lru_debug_offset+lru_debug_q'length-1), + din => lru_debug_d, + dout => lru_debug_q ); +snoop_val_latch: tri_rlmreg_p + generic map (width => snoop_val_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(snoop_val_offset to snoop_val_offset+snoop_val_q'length-1), + scout => sov_1(snoop_val_offset to snoop_val_offset+snoop_val_q'length-1), + din => snoop_val_d, + dout => snoop_val_q ); +snoop_attr_latch: tri_rlmreg_p + generic map (width => snoop_attr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => snoop_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(snoop_attr_offset to snoop_attr_offset+snoop_attr_q'length-1), + scout => sov_1(snoop_attr_offset to snoop_attr_offset+snoop_attr_q'length-1), + din => snoop_attr_d, + dout => snoop_attr_q ); +snoop_addr_latch: tri_rlmreg_p + generic map (width => snoop_addr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => snoop_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(snoop_addr_offset to snoop_addr_offset+snoop_addr_q'length-1), + scout => sov_1(snoop_addr_offset to snoop_addr_offset+snoop_addr_q'length-1), + din => snoop_addr_d(52-epn_width to 51), + dout => snoop_addr_q(52-epn_width to 51) ); +por_seq_latch: tri_rlmreg_p + generic map (width => por_seq_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(por_seq_offset to por_seq_offset+por_seq_q'length-1), + scout => sov_1(por_seq_offset to por_seq_offset+por_seq_q'length-1), + din => por_seq_d(0 to por_seq_width-1), + dout => por_seq_q(0 to por_seq_width-1) ); +-- timing latches for reloads +tlb_rel_val_latch: tri_rlmreg_p + generic map (width => tlb_rel_val_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(tlb_rel_val_offset to tlb_rel_val_offset+tlb_rel_val_q'length-1), + scout => sov_1(tlb_rel_val_offset to tlb_rel_val_offset+tlb_rel_val_q'length-1), + din => tlb_rel_val_d, + dout => tlb_rel_val_q ); +tlb_rel_data_latch: tri_rlmreg_p + generic map (width => tlb_rel_data_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_rel_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(tlb_rel_data_offset to tlb_rel_data_offset+tlb_rel_data_q'length-1), + scout => sov_1(tlb_rel_data_offset to tlb_rel_data_offset+tlb_rel_data_q'length-1), + din => tlb_rel_data_d, + dout => tlb_rel_data_q ); +iu_mm_ierat_flush_latch: tri_rlmreg_p + generic map (width => iu_mm_ierat_flush_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(iu_mm_ierat_flush_offset to iu_mm_ierat_flush_offset+iu_mm_ierat_flush_q'length-1), + scout => sov_1(iu_mm_ierat_flush_offset to iu_mm_ierat_flush_offset+iu_mm_ierat_flush_q'length-1), + din => iu_mm_ierat_flush_d(0 to thdid_width-1), + dout => iu_mm_ierat_flush_q(0 to thdid_width-1) ); +iu_xu_ierat_ex2_flush_latch: tri_rlmreg_p + generic map (width => iu_xu_ierat_ex2_flush_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(iu_xu_ierat_ex2_flush_offset to iu_xu_ierat_ex2_flush_offset+iu_xu_ierat_ex2_flush_q'length-1), + scout => sov_1(iu_xu_ierat_ex2_flush_offset to iu_xu_ierat_ex2_flush_offset+iu_xu_ierat_ex2_flush_q'length-1), + din => iu_xu_ierat_ex2_flush_d(0 to thdid_width-1), + dout => iu_xu_ierat_ex2_flush_q(0 to thdid_width-1) ); +ccr2_frat_paranoia_latch: tri_rlmreg_p + generic map (width => ccr2_frat_paranoia_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ccr2_frat_paranoia_offset to ccr2_frat_paranoia_offset+ccr2_frat_paranoia_q'length-1), + scout => sov_1(ccr2_frat_paranoia_offset to ccr2_frat_paranoia_offset+ccr2_frat_paranoia_q'length-1), + din => ccr2_frat_paranoia_d, + dout => ccr2_frat_paranoia_q ); +ccr2_notlb_latch: tri_rlmlatch_p + generic map (init => 1, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ccr2_notlb_offset), + scout => sov_1(ccr2_notlb_offset), + din => xu_iu_hid_mmu_mode, + dout => ccr2_notlb_q); +mchk_flash_inv_latch: tri_rlmreg_p + generic map (width => mchk_flash_inv_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu2_to_iu4_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mchk_flash_inv_offset to mchk_flash_inv_offset+mchk_flash_inv_q'length-1), + scout => sov_1(mchk_flash_inv_offset to mchk_flash_inv_offset+mchk_flash_inv_q'length-1), + din => mchk_flash_inv_d, + dout => mchk_flash_inv_q ); +xucr4_mmu_mchk_latch: tri_rlmlatch_p + generic map (init => 1, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(xucr4_mmu_mchk_offset), + scout => sov_1(xucr4_mmu_mchk_offset), + din => xu_iu_xucr4_mmu_mchk, + dout => xucr4_mmu_mchk_q); +iu1_debug_latch: tri_rlmreg_p + generic map (width => iu1_debug_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => trace_bus_enable_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(iu1_debug_offset to iu1_debug_offset+iu1_debug_q'length-1), + scout => sov_1(iu1_debug_offset to iu1_debug_offset+iu1_debug_q'length-1), + din => iu1_debug_d, + dout => iu1_debug_q); +iu2_debug_latch: tri_rlmreg_p + generic map (width => iu2_debug_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => debug_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(iu2_debug_offset to iu2_debug_offset+iu2_debug_q'length-1), + scout => sov_1(iu2_debug_offset to iu2_debug_offset+iu2_debug_q'length-1), + din => iu2_debug_d, + dout => iu2_debug_q); +iu1_stg_act_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(iu1_stg_act_offset), + scout => sov_1(iu1_stg_act_offset), + din => iu1_stg_act_d, + dout => iu1_stg_act_q); +iu2_stg_act_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(iu2_stg_act_offset), + scout => sov_1(iu2_stg_act_offset), + din => iu2_stg_act_d, + dout => iu2_stg_act_q); +iu3_stg_act_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(iu3_stg_act_offset), + scout => sov_1(iu3_stg_act_offset), + din => iu3_stg_act_d, + dout => iu3_stg_act_q); +iu4_stg_act_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(iu4_stg_act_offset), + scout => sov_1(iu4_stg_act_offset), + din => iu4_stg_act_d, + dout => iu4_stg_act_q); +ex1_stg_act_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ex1_stg_act_offset), + scout => sov_1(ex1_stg_act_offset), + din => ex1_stg_act_d, + dout => ex1_stg_act_q); +ex2_stg_act_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ex2_stg_act_offset), + scout => sov_1(ex2_stg_act_offset), + din => ex2_stg_act_d, + dout => ex2_stg_act_q); +ex3_stg_act_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ex3_stg_act_offset), + scout => sov_1(ex3_stg_act_offset), + din => ex3_stg_act_d, + dout => ex3_stg_act_q); +ex4_stg_act_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ex4_stg_act_offset), + scout => sov_1(ex4_stg_act_offset), + din => ex4_stg_act_d, + dout => ex4_stg_act_q); +ex5_stg_act_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ex5_stg_act_offset), + scout => sov_1(ex5_stg_act_offset), + din => ex5_stg_act_d, + dout => ex5_stg_act_q); +ex6_stg_act_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ex6_stg_act_offset), + scout => sov_1(ex6_stg_act_offset), + din => ex6_stg_act_d, + dout => ex6_stg_act_q); +ex7_stg_act_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ex7_stg_act_offset), + scout => sov_1(ex7_stg_act_offset), + din => ex7_stg_act_d, + dout => ex7_stg_act_q); +tlb_rel_act_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(tlb_rel_act_offset), + scout => sov_1(tlb_rel_act_offset), + din => tlb_rel_act_d, + dout => tlb_rel_act_q); +snoop_act_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(snoop_act_offset), + scout => sov_1(snoop_act_offset), + din => mm_iu_ierat_snoop_coming, + dout => snoop_act_q); +-- for debug trace bus latch act +trace_bus_enable_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(trace_bus_enable_offset), + scout => sov_1(trace_bus_enable_offset), + din => pc_iu_trace_bus_enable, + dout => trace_bus_enable_q); +an_ac_grffence_en_dc_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(an_ac_grffence_en_dc_offset), + scout => sov_1(an_ac_grffence_en_dc_offset), + din => an_ac_grffence_en_dc_q, + dout => an_ac_grffence_en_dc_q); +spare_a_latch: tri_rlmreg_p + generic map (width => 16, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spare_a_offset to spare_a_offset+15), + scout => sov_1(spare_a_offset to spare_a_offset+15), + din => spare_q(0 to 15), + dout => spare_q(0 to 15) ); +spare_b_latch: tri_rlmreg_p + generic map (width => 16, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spare_b_offset to spare_b_offset+15), + scout => sov_1(spare_b_offset to spare_b_offset+15), + din => spare_q(16 to 31), + dout => spare_q(16 to 31) ); +-------------------------------------------------- +-- scan only latches for boot config +-------------------------------------------------- +mpg_bcfg_gen: if expand_type /= 1 generate +bcfg_epn_0to15_latch: tri_slat_scan + generic map (width => 16, init => std_ulogic_vector( to_unsigned( bcfg_epn_0to15, 16 ) ), + reset_inverts_scan => true, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + dclk => lcb_dclk, + lclk => lcb_lclk, + scan_in => bsiv(bcfg_offset to bcfg_offset+15), + scan_out => bsov(bcfg_offset to bcfg_offset+15), + q => bcfg_q(0 to 15), + q_b => bcfg_q_b(0 to 15) ); +bcfg_epn_16to31_latch: tri_slat_scan + generic map (width => 16, init => std_ulogic_vector( to_unsigned( bcfg_epn_16to31, 16 ) ), + reset_inverts_scan => true, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + dclk => lcb_dclk, + lclk => lcb_lclk, + scan_in => bsiv(bcfg_offset+16 to bcfg_offset+31), + scan_out => bsov(bcfg_offset+16 to bcfg_offset+31), + q => bcfg_q(16 to 31), + q_b => bcfg_q_b(16 to 31) ); +bcfg_epn_32to47_latch: tri_slat_scan + generic map (width => 16, init => std_ulogic_vector( to_unsigned( bcfg_epn_32to47, 16 ) ), + reset_inverts_scan => true, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + dclk => lcb_dclk, + lclk => lcb_lclk, + scan_in => bsiv(bcfg_offset+32 to bcfg_offset+47), + scan_out => bsov(bcfg_offset+32 to bcfg_offset+47), + q => bcfg_q(32 to 47), + q_b => bcfg_q_b(32 to 47) ); +bcfg_epn_48to51_latch: tri_slat_scan + generic map (width => 4, init => std_ulogic_vector( to_unsigned( bcfg_epn_48to51, 4 ) ), + reset_inverts_scan => true, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + dclk => lcb_dclk, + lclk => lcb_lclk, + scan_in => bsiv(bcfg_offset+48 to bcfg_offset+51), + scan_out => bsov(bcfg_offset+48 to bcfg_offset+51), + q => bcfg_q(48 to 51), + q_b => bcfg_q_b(48 to 51) ); +bcfg_rpn_22to31_latch: tri_slat_scan + generic map (width => 10, init => std_ulogic_vector( to_unsigned( bcfg_rpn_22to31, 10 ) ), + reset_inverts_scan => true, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + dclk => lcb_dclk, + lclk => lcb_lclk, + scan_in => bsiv(bcfg_offset+52 to bcfg_offset+61), + scan_out => bsov(bcfg_offset+52 to bcfg_offset+61), + q => bcfg_q(52 to 61), + q_b => bcfg_q_b(52 to 61) ); +bcfg_rpn_32to47_latch: tri_slat_scan + generic map (width => 16, init => std_ulogic_vector( to_unsigned( bcfg_rpn_32to47, 16 ) ), + reset_inverts_scan => true, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + dclk => lcb_dclk, + lclk => lcb_lclk, + scan_in => bsiv(bcfg_offset+62 to bcfg_offset+77), + scan_out => bsov(bcfg_offset+62 to bcfg_offset+77), + q => bcfg_q(62 to 77), + q_b => bcfg_q_b(62 to 77) ); +bcfg_rpn_48to51_latch: tri_slat_scan + generic map (width => 4, init => std_ulogic_vector( to_unsigned( bcfg_rpn_48to51, 4 ) ), + reset_inverts_scan => true, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + dclk => lcb_dclk, + lclk => lcb_lclk, + scan_in => bsiv(bcfg_offset+78 to bcfg_offset+81), + scan_out => bsov(bcfg_offset+78 to bcfg_offset+81), + q => bcfg_q(78 to 81), + q_b => bcfg_q_b(78 to 81) ); +bcfg_attr_latch: tri_slat_scan + generic map (width => 5, init => std_ulogic_vector( to_unsigned( bcfg_attr, 5 ) ), + reset_inverts_scan => true, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + dclk => lcb_dclk, + lclk => lcb_lclk, + scan_in => bsiv(bcfg_offset+82 to bcfg_offset+86), + scan_out => bsov(bcfg_offset+82 to bcfg_offset+86), + q => bcfg_q(82 to 86), + q_b => bcfg_q_b(82 to 86) ); +bcfg_rpn2_32to47_latch: tri_slat_scan + generic map (width => 16, init => std_ulogic_vector( to_unsigned( bcfg_rpn2_32to47, 16 ) ), + reset_inverts_scan => true, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + dclk => lcb_dclk, + lclk => lcb_lclk, + scan_in => bsiv(bcfg_offset+87 to bcfg_offset+102), + scan_out => bsov(bcfg_offset+87 to bcfg_offset+102), + q => bcfg_q(87 to 102), + q_b => bcfg_q_b(87 to 102) ); +bcfg_rpn2_48to51_latch: tri_slat_scan + generic map (width => 4, init => std_ulogic_vector( to_unsigned( bcfg_rpn2_48to51, 4 ) ), + reset_inverts_scan => true, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + dclk => lcb_dclk, + lclk => lcb_lclk, + scan_in => bsiv(bcfg_offset+103 to bcfg_offset+106), + scan_out => bsov(bcfg_offset+103 to bcfg_offset+106), + q => bcfg_q(103 to 106), + q_b => bcfg_q_b(103 to 106) ); +bcfg_spare_latch: tri_slat_scan + generic map (width => 16, init => std_ulogic_vector( to_unsigned( 0, 16 ) ), + reset_inverts_scan => true, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + dclk => lcb_dclk, + lclk => lcb_lclk, + scan_in => bsiv(bcfg_offset+107 to bcfg_offset+122), + scan_out => bsov(bcfg_offset+107 to bcfg_offset+122), + q => bcfg_q(107 to 122), + q_b => bcfg_q_b(107 to 122) ); +end generate mpg_bcfg_gen; +fpga_bcfg_gen: if expand_type = 1 generate +bcfg_epn_0to15_latch: tri_rlmreg_p + generic map (width => 16, init => bcfg_epn_0to15, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(0 to 15), + scout => bsov(0 to 15), + din => bcfg_q(0 to 15), + dout => bcfg_q(0 to 15) ); +bcfg_epn_16to31_latch: tri_rlmreg_p + generic map (width => 16, init => bcfg_epn_16to31, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(16 to 31), + scout => bsov(16 to 31), + din => bcfg_q(16 to 31), + dout => bcfg_q(16 to 31) ); +bcfg_epn_32to47_latch: tri_rlmreg_p + generic map (width => 16, init => bcfg_epn_32to47, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(32 to 47), + scout => bsov(32 to 47), + din => bcfg_q(32 to 47), + dout => bcfg_q(32 to 47) ); +bcfg_epn_48to51_latch: tri_rlmreg_p + generic map (width => 4, init => bcfg_epn_48to51, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(48 to 51), + scout => bsov(48 to 51), + din => bcfg_q(48 to 51), + dout => bcfg_q(48 to 51) ); +bcfg_rpn_22to31_latch: tri_rlmreg_p + generic map (width => 10, init => bcfg_rpn_22to31, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(52 to 61), + scout => bsov(52 to 61), + din => bcfg_q(52 to 61), + dout => bcfg_q(52 to 61) ); +bcfg_rpn_32to47_latch: tri_rlmreg_p + generic map (width => 16, init => bcfg_rpn_32to47, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(62 to 77), + scout => bsov(62 to 77), + din => bcfg_q(62 to 77), + dout => bcfg_q(62 to 77) ); +bcfg_rpn_48to51_latch: tri_rlmreg_p + generic map (width => 4, init => bcfg_rpn_48to51, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(78 to 81), + scout => bsov(78 to 81), + din => bcfg_q(78 to 81), + dout => bcfg_q(78 to 81) ); +bcfg_attr_latch: tri_rlmreg_p + generic map (width => 5, init => bcfg_attr, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(82 to 86), + scout => bsov(82 to 86), + din => bcfg_q(82 to 86), + dout => bcfg_q(82 to 86) ); +bcfg_rpn2_32to47_latch: tri_rlmreg_p + generic map (width => 16, init => bcfg_rpn2_32to47, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(87 to 102), + scout => bsov(87 to 102), + din => bcfg_q(87 to 102), + dout => bcfg_q(87 to 102) ); +bcfg_rpn2_48to51_latch: tri_rlmreg_p + generic map (width => 4, init => bcfg_rpn2_48to51, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(103 to 106), + scout => bsov(103 to 106), + din => bcfg_q(103 to 106), + dout => bcfg_q(103 to 106) ); +bcfg_spare_latch: tri_rlmreg_p + generic map (width => 16, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(107 to 122), + scout => bsov(107 to 122), + din => bcfg_q(107 to 122), + dout => bcfg_q(107 to 122) ); +end generate fpga_bcfg_gen; +-------------------------------------------------- +-- thold/sg latches +-------------------------------------------------- +perv_2to1_reg: tri_plat + generic map (width => 4, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ccflush_dc, + din(0) => pc_iu_func_sl_thold_2, + din(1) => pc_iu_func_slp_sl_thold_2, + din(2) => pc_iu_cfg_slp_sl_thold_2, + din(3) => pc_iu_sg_2, + q(0) => pc_func_sl_thold_1, + q(1) => pc_func_slp_sl_thold_1, + q(2) => pc_cfg_slp_sl_thold_1, + q(3) => pc_sg_1); +perv_1to0_reg: tri_plat + generic map (width => 4, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ccflush_dc, + din(0) => pc_func_sl_thold_1, + din(1) => pc_func_slp_sl_thold_1, + din(2) => pc_cfg_slp_sl_thold_1, + din(3) => pc_sg_1, + q(0) => pc_func_sl_thold_0, + q(1) => pc_func_slp_sl_thold_0, + q(2) => pc_cfg_slp_sl_thold_0, + q(3) => pc_sg_0); +perv_lcbor_func_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b, + thold => pc_func_sl_thold_0, + sg => pc_sg_0, + act_dis => lcb_act_dis_dc, + forcee => pc_func_sl_force, + thold_b => pc_func_sl_thold_0_b); +perv_lcbor_func_slp_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b, + thold => pc_func_slp_sl_thold_0, + sg => pc_sg_0, + act_dis => lcb_act_dis_dc, + forcee => pc_func_slp_sl_force, + thold_b => pc_func_slp_sl_thold_0_b); +mpg_bcfg_lcb_gen: if expand_type /= 1 generate +-------------------------------------------------- +-- local clock buffer for boot config +-------------------------------------------------- +bcfg_lcb: tri_lcbs + generic map (expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + delay_lclkr => lcb_delay_lclkr_dc(0), + nclk => nclk, + forcee => pc_cfg_slp_sl_force, + thold_b => pc_cfg_slp_sl_thold_0_b, + dclk => lcb_dclk, + lclk => lcb_lclk ); +-- these terms in the absence of another lcbor component +-- that drives the thold_b and force into the bcfg_lcb for slat's +pc_cfg_slp_sl_thold_0_b <= NOT pc_cfg_slp_sl_thold_0; +pc_cfg_slp_sl_force <= pc_sg_0; +end generate mpg_bcfg_lcb_gen; +fpga_bcfg_lcb_gen: if expand_type = 1 generate +perv_lcbor_cfg_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b, + thold => pc_cfg_slp_sl_thold_0, + sg => pc_sg_0, + act_dis => lcb_act_dis_dc, + forcee => pc_cfg_slp_sl_force, + thold_b => pc_cfg_slp_sl_thold_0_b); +end generate fpga_bcfg_lcb_gen; +----------------------------------------------------------------------- +-- Scan +----------------------------------------------------------------------- +siv_0(0 TO scan_right_0) <= sov_0(1 to scan_right_0) & ac_func_scan_in(0); +ac_func_scan_out(0) <= sov_0(0); +siv_1(0 TO scan_right_1) <= sov_1(1 to scan_right_1) & ac_func_scan_in(1); +ac_func_scan_out(1) <= sov_1(0); +bsiv(0 TO boot_scan_right) <= bsov(1 to boot_scan_right) & ac_ccfg_scan_in; +ac_ccfg_scan_out <= bsov(0); +END IUQ_IC_IERAT; diff --git a/rel/src/vhdl/work/iuq_ic_insmux.vhdl b/rel/src/vhdl/work/iuq_ic_insmux.vhdl new file mode 100644 index 0000000..5464658 --- /dev/null +++ b/rel/src/vhdl/work/iuq_ic_insmux.vhdl @@ -0,0 +1,415 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: IU INSTRUCTION MUX Logic +--***************************************************************************** + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + +entity iuq_ic_insmux is +generic( expand_type: integer := 2 ); -- 0 - ibm tech, 1 - other ); +port( + vdd :inout power_logic; + gnd :inout power_logic; + nclk :in clk_logic; + delay_lclkr :in std_ulogic;-- LCB input + mpw1_b :in std_ulogic;-- LCB input + mpw2_b :in std_ulogic;-- LCB input + forcee :in std_ulogic;-- LCB input + sg_0 :in std_ulogic;-- LCB input + thold_0_b :in std_ulogic;-- LCB input + scan_in :in std_ulogic;-- perv + scan_out :out std_ulogic;-- perv + inslat_act :in std_ulogic;-- ACT + + iu2_rd_way_hit_b :in std_ulogic_vector(0 to 3); --select ... after long net + load_iu2 :in std_ulogic ; --select + + icm_icd_reload_data :in std_ulogic_vector(0 to 143);-- + iu2_data_dataout_0 :in std_ulogic_vector(0 to 143);-- iu2_data_dataout_l2 000:143 + iu2_data_dataout_1 :in std_ulogic_vector(0 to 143);-- iu2_data_dataout_l2 162:305 + iu2_data_dataout_2 :in std_ulogic_vector(0 to 143);-- iu2_data_dataout_l2 324:467 + iu2_data_dataout_3 :in std_ulogic_vector(0 to 143);-- iu2_data_dataout_l2 586:629 + + iu3_instr0_buf :out std_ulogic_vector(0 to 35) ;-- buffer after latch + iu3_instr1_buf :out std_ulogic_vector(0 to 35) ;-- buffer after latch + iu3_instr2_buf :out std_ulogic_vector(0 to 35) ;-- buffer after latch + iu3_instr3_buf :out std_ulogic_vector(0 to 35) -- buffer after latch +); + +-- synopsys translate_off + + + +-- synopsys translate_on + + +end iuq_ic_insmux; -- ENTITY + +architecture iuq_ic_insmux of iuq_ic_insmux is + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal inslat_lclk :clk_logic; + signal inslat_d1clk :std_ulogic; + signal inslat_d2clk :std_ulogic; + + signal iu3_instr0_si, iu3_instr0_so, iu3_instr0_l2_b, iu3_instr0_d1, iu3_instr0_d2 :std_ulogic_vector(0 to 35); + signal iu3_instr1_si, iu3_instr1_so, iu3_instr1_l2_b, iu3_instr1_d1, iu3_instr1_d2 :std_ulogic_vector(0 to 35); + signal iu3_instr2_si, iu3_instr2_so, iu3_instr2_l2_b, iu3_instr2_d1, iu3_instr2_d2 :std_ulogic_vector(0 to 35); + signal iu3_instr3_si, iu3_instr3_so, iu3_instr3_l2_b, iu3_instr3_d1, iu3_instr3_d2 :std_ulogic_vector(0 to 35); + signal iu3_instr0_oth_b, iu3_instr1_oth_b, iu3_instr2_oth_b, iu3_instr3_oth_b :std_ulogic_vector(0 to 35); + signal iu3_instr0_dx0_b, iu3_instr0_dx1_b, iu3_instr0_dx2_b, iu3_instr0_dx3_b :std_ulogic_vector(0 to 35); + signal iu3_instr1_dx0_b, iu3_instr1_dx1_b, iu3_instr1_dx2_b, iu3_instr1_dx3_b :std_ulogic_vector(0 to 35); + signal iu3_instr2_dx0_b, iu3_instr2_dx1_b, iu3_instr2_dx2_b, iu3_instr2_dx3_b :std_ulogic_vector(0 to 35); + signal iu3_instr3_dx0_b, iu3_instr3_dx1_b, iu3_instr3_dx2_b, iu3_instr3_dx3_b :std_ulogic_vector(0 to 35); + + +-- synopsys translate_off + + + + + + + + +-- synopsys translate_on + + + + + signal hit0_en0, hit0_en1, hit0_en2, hit0_en3 :std_ulogic_vector(0 to 35); + signal hit1_en0, hit1_en1, hit1_en2, hit1_en3 :std_ulogic_vector(0 to 35); + signal hit2_en0, hit2_en1, hit2_en2, hit2_en3 :std_ulogic_vector(0 to 35); + signal hit3_en0, hit3_en1, hit3_en2, hit3_en3 :std_ulogic_vector(0 to 35); + signal cached_enable :std_ulogic; + + signal hit0, hit1, hit2, hit3 :std_ulogic; +-- synopsys translate_off +-- synopsys translate_on + signal hit0_en_b, hit1_en_b, hit2_en_b, hit3_en_b :std_ulogic_vector(0 to 3); +-- synopsys translate_off +-- synopsys translate_on + signal hit0_en , hit1_en , hit2_en , hit3_en :std_ulogic_vector(0 to 7); +-- synopsys translate_off + + + + + + + +-- synopsys translate_on + + + +begin + +-- +-- assume: (1) selects other than rd_way_hit are not timing critical +-- (2) data is not timing critical +-- + + + + + +-- ################################################################ +-- # select repower +-- ################################################################ + + cached_enable <= not load_iu2 ; -- not timing critical + + -- level 1 -- + u_hit0_i1: hit0 <= not( iu2_rd_way_hit_b(0) ); -- x16 + u_hit1_i1: hit1 <= not( iu2_rd_way_hit_b(1) ); -- x16 + u_hit2_i1: hit2 <= not( iu2_rd_way_hit_b(2) ); -- x16 + u_hit3_i1: hit3 <= not( iu2_rd_way_hit_b(3) ); -- x16 + + -- level 2 -- + u_hit0_a2_cp0: hit0_en_b(0) <= not( hit0 and cached_enable) ; --x8 + u_hit0_a2_cp1: hit0_en_b(1) <= not( hit0 and cached_enable) ; --x8 + u_hit0_a2_cp2: hit0_en_b(2) <= not( hit0 and cached_enable) ; --x8 + u_hit0_a2_cp3: hit0_en_b(3) <= not( hit0 and cached_enable) ; --x8 + + u_hit1_a2_cp0: hit1_en_b(0) <= not( hit1 and cached_enable) ; --x8 + u_hit1_a2_cp1: hit1_en_b(1) <= not( hit1 and cached_enable) ; --x8 + u_hit1_a2_cp2: hit1_en_b(2) <= not( hit1 and cached_enable) ; --x8 + u_hit1_a2_cp3: hit1_en_b(3) <= not( hit1 and cached_enable) ; --x8 + + u_hit2_a2_cp0: hit2_en_b(0) <= not( hit2 and cached_enable) ; --x8 + u_hit2_a2_cp1: hit2_en_b(1) <= not( hit2 and cached_enable) ; --x8 + u_hit2_a2_cp2: hit2_en_b(2) <= not( hit2 and cached_enable) ; --x8 + u_hit2_a2_cp3: hit2_en_b(3) <= not( hit2 and cached_enable) ; --x8 + + u_hit3_a2_cp0: hit3_en_b(0) <= not( hit3 and cached_enable) ; --x8 + u_hit3_a2_cp1: hit3_en_b(1) <= not( hit3 and cached_enable) ; --x8 + u_hit3_a2_cp2: hit3_en_b(2) <= not( hit3 and cached_enable) ; --x8 + u_hit3_a2_cp3: hit3_en_b(3) <= not( hit3 and cached_enable) ; --x8 + + + -- level 3 -- + u_hit0_i2_cp0: hit0_en(0) <= not( hit0_en_b(0) ) ; -- x16 + u_hit0_i2_cp1: hit0_en(1) <= not( hit0_en_b(0) ) ; -- x16 + u_hit0_i2_cp2: hit0_en(2) <= not( hit0_en_b(1) ) ; -- x16 + u_hit0_i2_cp3: hit0_en(3) <= not( hit0_en_b(1) ) ; -- x16 + u_hit0_i2_cp4: hit0_en(4) <= not( hit0_en_b(2) ) ; -- x16 + u_hit0_i2_cp5: hit0_en(5) <= not( hit0_en_b(2) ) ; -- x16 + u_hit0_i2_cp6: hit0_en(6) <= not( hit0_en_b(3) ) ; -- x16 + u_hit0_i2_cp7: hit0_en(7) <= not( hit0_en_b(3) ) ; -- x16 + + u_hit1_i2_cp0: hit1_en(0) <= not( hit1_en_b(0) ) ; -- x16 + u_hit1_i2_cp1: hit1_en(1) <= not( hit1_en_b(0) ) ; -- x16 + u_hit1_i2_cp2: hit1_en(2) <= not( hit1_en_b(1) ) ; -- x16 + u_hit1_i2_cp3: hit1_en(3) <= not( hit1_en_b(1) ) ; -- x16 + u_hit1_i2_cp4: hit1_en(4) <= not( hit1_en_b(2) ) ; -- x16 + u_hit1_i2_cp5: hit1_en(5) <= not( hit1_en_b(2) ) ; -- x16 + u_hit1_i2_cp6: hit1_en(6) <= not( hit1_en_b(3) ) ; -- x16 + u_hit1_i2_cp7: hit1_en(7) <= not( hit1_en_b(3) ) ; -- x16 + + u_hit2_i2_cp0: hit2_en(0) <= not( hit2_en_b(0) ) ; -- x16 + u_hit2_i2_cp1: hit2_en(1) <= not( hit2_en_b(0) ) ; -- x16 + u_hit2_i2_cp2: hit2_en(2) <= not( hit2_en_b(1) ) ; -- x16 + u_hit2_i2_cp3: hit2_en(3) <= not( hit2_en_b(1) ) ; -- x16 + u_hit2_i2_cp4: hit2_en(4) <= not( hit2_en_b(2) ) ; -- x16 + u_hit2_i2_cp5: hit2_en(5) <= not( hit2_en_b(2) ) ; -- x16 + u_hit2_i2_cp6: hit2_en(6) <= not( hit2_en_b(3) ) ; -- x16 + u_hit2_i2_cp7: hit2_en(7) <= not( hit2_en_b(3) ) ; -- x16 + + u_hit3_i2_cp0: hit3_en(0) <= not( hit3_en_b(0) ) ; -- x16 + u_hit3_i2_cp1: hit3_en(1) <= not( hit3_en_b(0) ) ; -- x16 + u_hit3_i2_cp2: hit3_en(2) <= not( hit3_en_b(1) ) ; -- x16 + u_hit3_i2_cp3: hit3_en(3) <= not( hit3_en_b(1) ) ; -- x16 + u_hit3_i2_cp4: hit3_en(4) <= not( hit3_en_b(2) ) ; -- x16 + u_hit3_i2_cp5: hit3_en(5) <= not( hit3_en_b(2) ) ; -- x16 + u_hit3_i2_cp6: hit3_en(6) <= not( hit3_en_b(3) ) ; -- x16 + u_hit3_i2_cp7: hit3_en(7) <= not( hit3_en_b(3) ) ; -- x16 + + + -- rename to vector (no logic here) + + + hit0_en0( 0 to 17) <= ( 0 to 17 => hit0_en(0) ); + hit0_en0(18 to 35) <= (18 to 35 => hit0_en(1) ); + hit0_en1( 0 to 17) <= ( 0 to 17 => hit0_en(2) ); + hit0_en1(18 to 35) <= (18 to 35 => hit0_en(3) ); + hit0_en2( 0 to 17) <= ( 0 to 17 => hit0_en(4) ); + hit0_en2(18 to 35) <= (18 to 35 => hit0_en(5) ); + hit0_en3( 0 to 17) <= ( 0 to 17 => hit0_en(6) ); + hit0_en3(18 to 35) <= (18 to 35 => hit0_en(7) ); + + hit1_en0( 0 to 17) <= ( 0 to 17 => hit1_en(0) ); + hit1_en0(18 to 35) <= (18 to 35 => hit1_en(1) ); + hit1_en1( 0 to 17) <= ( 0 to 17 => hit1_en(2) ); + hit1_en1(18 to 35) <= (18 to 35 => hit1_en(3) ); + hit1_en2( 0 to 17) <= ( 0 to 17 => hit1_en(4) ); + hit1_en2(18 to 35) <= (18 to 35 => hit1_en(5) ); + hit1_en3( 0 to 17) <= ( 0 to 17 => hit1_en(6) ); + hit1_en3(18 to 35) <= (18 to 35 => hit1_en(7) ); + + hit2_en0( 0 to 17) <= ( 0 to 17 => hit2_en(0) ); + hit2_en0(18 to 35) <= (18 to 35 => hit2_en(1) ); + hit2_en1( 0 to 17) <= ( 0 to 17 => hit2_en(2) ); + hit2_en1(18 to 35) <= (18 to 35 => hit2_en(3) ); + hit2_en2( 0 to 17) <= ( 0 to 17 => hit2_en(4) ); + hit2_en2(18 to 35) <= (18 to 35 => hit2_en(5) ); + hit2_en3( 0 to 17) <= ( 0 to 17 => hit2_en(6) ); + hit2_en3(18 to 35) <= (18 to 35 => hit2_en(7) ); + + hit3_en0( 0 to 17) <= ( 0 to 17 => hit3_en(0) ); + hit3_en0(18 to 35) <= (18 to 35 => hit3_en(1) ); + hit3_en1( 0 to 17) <= ( 0 to 17 => hit3_en(2) ); + hit3_en1(18 to 35) <= (18 to 35 => hit3_en(3) ); + hit3_en2( 0 to 17) <= ( 0 to 17 => hit3_en(4) ); + hit3_en2(18 to 35) <= (18 to 35 => hit3_en(5) ); + hit3_en3( 0 to 17) <= ( 0 to 17 => hit3_en(6) ); + hit3_en3(18 to 35) <= (18 to 35 => hit3_en(7) ); + + +-- ################################################################ +-- # data muxing (critical select) (0:35 , 36:71 , 72:107, 108:143) +-- ################################################################ + + + u_iu3_instr0_dx0: iu3_instr0_dx0_b( 0 to 35) <= not( hit0_en0(0 to 35) and iu2_data_dataout_0( 0 to 35) ) ; + u_iu3_instr0_dx1: iu3_instr0_dx1_b( 0 to 35) <= not( hit1_en0(0 to 35) and iu2_data_dataout_1( 0 to 35) ) ; + u_iu3_instr0_dx2: iu3_instr0_dx2_b( 0 to 35) <= not( hit2_en0(0 to 35) and iu2_data_dataout_2( 0 to 35) ) ; + u_iu3_instr0_dx3: iu3_instr0_dx3_b( 0 to 35) <= not( hit3_en0(0 to 35) and iu2_data_dataout_3( 0 to 35) ) ; + + u_iu3_instr1_dx0: iu3_instr1_dx0_b( 0 to 35) <= not( hit0_en1(0 to 35) and iu2_data_dataout_0( 36 to 71) ) ; + u_iu3_instr1_dx1: iu3_instr1_dx1_b( 0 to 35) <= not( hit1_en1(0 to 35) and iu2_data_dataout_1( 36 to 71) ) ; + u_iu3_instr1_dx2: iu3_instr1_dx2_b( 0 to 35) <= not( hit2_en1(0 to 35) and iu2_data_dataout_2( 36 to 71) ) ; + u_iu3_instr1_dx3: iu3_instr1_dx3_b( 0 to 35) <= not( hit3_en1(0 to 35) and iu2_data_dataout_3( 36 to 71) ) ; + + u_iu3_instr2_dx0: iu3_instr2_dx0_b( 0 to 35) <= not( hit0_en2(0 to 35) and iu2_data_dataout_0( 72 to 107) ) ; + u_iu3_instr2_dx1: iu3_instr2_dx1_b( 0 to 35) <= not( hit1_en2(0 to 35) and iu2_data_dataout_1( 72 to 107) ) ; + u_iu3_instr2_dx2: iu3_instr2_dx2_b( 0 to 35) <= not( hit2_en2(0 to 35) and iu2_data_dataout_2( 72 to 107) ) ; + u_iu3_instr2_dx3: iu3_instr2_dx3_b( 0 to 35) <= not( hit3_en2(0 to 35) and iu2_data_dataout_3( 72 to 107) ) ; + + u_iu3_instr3_dx0: iu3_instr3_dx0_b( 0 to 35) <= not( hit0_en3(0 to 35) and iu2_data_dataout_0(108 to 143) ) ; + u_iu3_instr3_dx1: iu3_instr3_dx1_b( 0 to 35) <= not( hit1_en3(0 to 35) and iu2_data_dataout_1(108 to 143) ) ; + u_iu3_instr3_dx2: iu3_instr3_dx2_b( 0 to 35) <= not( hit2_en3(0 to 35) and iu2_data_dataout_2(108 to 143) ) ; + u_iu3_instr3_dx3: iu3_instr3_dx3_b( 0 to 35) <= not( hit3_en3(0 to 35) and iu2_data_dataout_3(108 to 143) ) ; + + + + u_iu3_instr0_d1: iu3_instr0_d1(0 to 35) <= not( iu3_instr0_dx0_b(0 to 35) and iu3_instr0_dx1_b(0 to 35) and iu3_instr0_oth_b(0 to 35) ); + u_iu3_instr0_d2: iu3_instr0_d2(0 to 35) <= not( iu3_instr0_dx2_b(0 to 35) and iu3_instr0_dx3_b(0 to 35) ); + + u_iu3_instr1_d1: iu3_instr1_d1(0 to 35) <= not( iu3_instr1_dx0_b(0 to 35) and iu3_instr1_dx1_b(0 to 35) and iu3_instr1_oth_b(0 to 35) ); + u_iu3_instr1_d2: iu3_instr1_d2(0 to 35) <= not( iu3_instr1_dx2_b(0 to 35) and iu3_instr1_dx3_b(0 to 35) ); + + u_iu3_instr2_d1: iu3_instr2_d1(0 to 35) <= not( iu3_instr2_dx0_b(0 to 35) and iu3_instr2_dx1_b(0 to 35) and iu3_instr2_oth_b(0 to 35) ); + u_iu3_instr2_d2: iu3_instr2_d2(0 to 35) <= not( iu3_instr2_dx2_b(0 to 35) and iu3_instr2_dx3_b(0 to 35) ); + + u_iu3_instr3_d1: iu3_instr3_d1(0 to 35) <= not( iu3_instr3_dx0_b(0 to 35) and iu3_instr3_dx1_b(0 to 35) and iu3_instr3_oth_b(0 to 35) ); + u_iu3_instr3_d2: iu3_instr3_d2(0 to 35) <= not( iu3_instr3_dx2_b(0 to 35) and iu3_instr3_dx3_b(0 to 35) ); + + + +-- ################################################################ +-- # the "other" data muxing (0:35 , 36:71 , 72:107, 108:143) +-- ################################################################ + + iu3_instr0_oth_b(0 to 35) <= not( -- no_mod (not mapped) + icm_icd_reload_data( 0 to 35) and (0 to 35=> load_iu2 ) ); + + iu3_instr1_oth_b(0 to 35) <= not( -- no_mod (not mapped) + icm_icd_reload_data( 36 to 71) and (0 to 35=> load_iu2 ) ); + + iu3_instr2_oth_b(0 to 35) <= not( -- no_mod (not mapped) + icm_icd_reload_data( 72 to 107) and (0 to 35=> load_iu2 ) ); + + iu3_instr3_oth_b(0 to 35) <= not( -- no_mod (not mapped) + icm_icd_reload_data(108 to 143) and (0 to 35=> load_iu2 ) ); + + +-- ################################################################ +-- # Latches +-- ################################################################ + + + iu3_instr0_lat: entity tri.tri_nor2_nlats generic map (width => 36, btr=> "NLO0001_X2_A12TH", needs_sreset => 0, expand_type => expand_type) port map ( + VD => vdd , + GD => gnd , + LCLK => inslat_lclk , + D1CLK => inslat_d1clk , + D2CLK => inslat_d2clk , + SCANIN => iu3_instr0_si , + SCANOUT => iu3_instr0_so , + A1 => iu3_instr0_d1 (0 to 35) , + A2 => iu3_instr0_d2 (0 to 35) , + QB => iu3_instr0_l2_b(0 to 35) ); + + iu3_instr1_lat: entity tri.tri_nor2_nlats generic map (width => 36, btr=> "NLO0001_X2_A12TH", needs_sreset => 0, expand_type => expand_type) port map ( + VD => vdd , + GD => gnd , + LCLK => inslat_lclk , + D1CLK => inslat_d1clk , + D2CLK => inslat_d2clk , + SCANIN => iu3_instr1_si , + SCANOUT => iu3_instr1_so , + A1 => iu3_instr1_d1 (0 to 35) , + A2 => iu3_instr1_d2 (0 to 35) , + QB => iu3_instr1_l2_b(0 to 35) ); + + iu3_instr2_lat: entity tri.tri_nor2_nlats generic map (width => 36, btr=> "NLO0001_X2_A12TH", needs_sreset => 0, expand_type => expand_type) port map ( + VD => vdd , + GD => gnd , + LCLK => inslat_lclk , + D1CLK => inslat_d1clk , + D2CLK => inslat_d2clk , + SCANIN => iu3_instr2_si , + SCANOUT => iu3_instr2_so , + A1 => iu3_instr2_d1 (0 to 35) , + A2 => iu3_instr2_d2 (0 to 35) , + QB => iu3_instr2_l2_b(0 to 35) ); + + iu3_instr3_lat: entity tri.tri_nor2_nlats generic map (width => 36, btr=> "NLO0001_X2_A12TH", needs_sreset => 0, expand_type => expand_type) port map ( + VD => vdd , + GD => gnd , + LCLK => inslat_lclk , + D1CLK => inslat_d1clk , + D2CLK => inslat_d2clk , + SCANIN => iu3_instr3_si , + SCANOUT => iu3_instr3_so , + A1 => iu3_instr3_d1 (0 to 35) , + A2 => iu3_instr3_d2 (0 to 35) , + QB => iu3_instr3_l2_b(0 to 35) ); + + + u_iu3_instr0_inv: iu3_instr0_buf <= not( iu3_instr0_l2_b ); --output-- --x6 + u_iu3_instr1_inv: iu3_instr1_buf <= not( iu3_instr1_l2_b ); --output-- --x6 + u_iu3_instr2_inv: iu3_instr2_buf <= not( iu3_instr2_l2_b ); --output-- --x6 + u_iu3_instr3_inv: iu3_instr3_buf <= not( iu3_instr3_l2_b ); --output-- --x6 + + + + + -- serpentine scan string -- + iu3_instr0_si(0 to 35) <= scan_in & iu3_instr0_so(0 to 34); + iu3_instr1_si(0 to 35) <= iu3_instr1_so(1 to 35) & iu3_instr0_so(35); + iu3_instr2_si(0 to 35) <= iu3_instr1_so(0) & iu3_instr2_so(0 to 34) ; + iu3_instr3_si(0 to 35) <= iu3_instr3_so(1 to 35) & iu3_instr2_so(35) ; + scan_out <= iu3_instr3_so(0) ; + +-- ############################################################### +-- # LCBs +-- ############################################################### + + inslat_lcb : tri_lcbnd generic map (expand_type => expand_type) port map( + nclk => nclk ,--in + vd => vdd ,--inout + gd => gnd ,--inout + act => inslat_act ,--in + delay_lclkr => delay_lclkr ,--in + mpw1_b => mpw1_b ,--in + mpw2_b => mpw2_b ,--in + forcee => forcee,--in + sg => sg_0 ,--in + thold_b => thold_0_b ,--in + d1clk => inslat_d1clk ,--out + d2clk => inslat_d2clk ,--out + lclk => inslat_lclk );--out + + +--=############################################################### + + +end; -- iuq_ic_insmux ARCHITECTURE diff --git a/rel/src/vhdl/work/iuq_ic_miss.vhdl b/rel/src/vhdl/work/iuq_ic_miss.vhdl new file mode 100644 index 0000000..8ee407e --- /dev/null +++ b/rel/src/vhdl/work/iuq_ic_miss.vhdl @@ -0,0 +1,4735 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +--******************************************************************** +--* +--* TITLE: +--* +--* NAME: iuq_ic_miss.vhdl +--* +--********************************************************************* + +library ieee,ibm,support,tri,work; +use ieee.std_logic_1164.all; +use ibm.std_ulogic_unsigned.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use support.power_logic_pkg.all; +use tri.tri_latches_pkg.all; +use work.iuq_pkg.all; +entity iuq_ic_miss is + generic(expand_type : integer := 2); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + pc_iu_func_sl_thold_0_b : in std_ulogic; + pc_iu_sg_0 : in std_ulogic; + forcee : in std_ulogic; + d_mode : in std_ulogic; + delay_lclkr : in std_ulogic; + mpw1_b : in std_ulogic; + mpw2_b : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + xu_iu_flush : in std_ulogic_vector(0 to 3); + bp_ic_iu5_redirect_tid : in std_ulogic_vector(0 to 3); + + ics_icm_iu0_ifar0 : in std_ulogic_vector(46 to 52); + ics_icm_iu0_ifar1 : in std_ulogic_vector(46 to 52); + ics_icm_iu0_ifar2 : in std_ulogic_vector(46 to 52); + ics_icm_iu0_ifar3 : in std_ulogic_vector(46 to 52); + + ics_icm_iu0_inval : in std_ulogic; + ics_icm_iu0_inval_addr : in std_ulogic_vector(52 to 57); + + ics_icm_iu2_flush_tid : in std_ulogic_vector(0 to 3); + ics_icm_iu3_flush_tid : in std_ulogic_vector(0 to 3); + icm_ics_hold_thread : out std_ulogic_vector(0 to 3); + icm_ics_hold_thread_dbg : out std_ulogic_vector(0 to 3); + icm_ics_hold_iu0 : out std_ulogic; + icm_ics_ecc_block_iu0 : out std_ulogic_vector(0 to 3); + icm_ics_load_tid : out std_ulogic_vector(0 to 3); + icm_ics_iu1_ecc_flush : out std_ulogic; + icm_ics_iu2_miss_match_prev : out std_ulogic; + + icm_ics_iu0_preload_val : out std_ulogic; + icm_ics_iu0_preload_tid : out std_ulogic_vector(0 to 3); + icm_ics_iu0_preload_ifar : out std_ulogic_vector(52 to 59); + + icm_icd_lru_addr : out std_ulogic_vector(52 to 57); + icm_icd_dir_inval : out std_ulogic; + icm_icd_dir_val : out std_ulogic; + icm_icd_data_write : out std_ulogic; + icm_icd_reload_addr : out std_ulogic_vector(52 to 59); + icm_icd_reload_data : out std_ulogic_vector(0 to 161); + icm_icd_reload_way : out std_ulogic_vector(0 to 3); + icm_icd_load_tid : out std_ulogic_vector(0 to 3); + icm_icd_load_addr : out EFF_IFAR; + icm_icd_load_2ucode : out std_ulogic; + icm_icd_load_2ucode_type : out std_ulogic; + icm_icd_dir_write : out std_ulogic; + icm_icd_dir_write_addr : out std_ulogic_vector(REAL_IFAR'left to 57); + icm_icd_dir_write_endian : out std_ulogic; + icm_icd_dir_write_way : out std_ulogic_vector(0 to 3); + icm_icd_lru_write : out std_ulogic; + icm_icd_lru_write_addr : out std_ulogic_vector(52 to 57); + icm_icd_lru_write_way : out std_ulogic_vector(0 to 3); + icm_icd_ecc_inval : out std_ulogic; + icm_icd_ecc_addr : out std_ulogic_vector(52 to 57); + icm_icd_ecc_way : out std_ulogic_vector(0 to 3); + icm_icd_iu3_ecc_fp_cancel : out std_ulogic; + icm_icd_iu3_ecc_err : out std_ulogic; + icm_icd_any_reld_r2 : out std_ulogic; + icm_icd_any_checkecc : out std_ulogic; + + icd_icm_miss : in std_ulogic; + icd_icm_tid : in std_ulogic_vector(0 to 3); + icd_icm_addr_real : in REAL_IFAR; + icd_icm_addr_eff : in std_ulogic_vector(EFF_IFAR'left to 51); + icd_icm_wimge : in std_ulogic_vector(0 to 4); + icd_icm_userdef : in std_ulogic_vector(0 to 3); + icd_icm_2ucode : in std_ulogic; + icd_icm_2ucode_type : in std_ulogic; + icd_icm_iu3_erat_err : in std_ulogic; + icd_icm_iu2_inval : in std_ulogic; + icd_icm_ici : in std_ulogic; + icd_icm_any_iu2_valid : in std_ulogic; + + icd_icm_row_lru : in std_ulogic_vector(0 to 2); + icd_icm_row_val : in std_ulogic_vector(0 to 3); + + ic_fdep_load_quiesce : out std_ulogic_vector(0 to 3); + + iu_mm_lmq_empty : out std_ulogic; + + ic_perf_event_t0 : out std_ulogic_vector(0 to 1); + ic_perf_event_t1 : out std_ulogic_vector(0 to 1); + ic_perf_event_t2 : out std_ulogic_vector(0 to 1); + ic_perf_event_t3 : out std_ulogic_vector(0 to 1); + + an_ac_reld_data_vld : in std_ulogic; + an_ac_reld_core_tag : in std_ulogic_vector(0 to 4); + an_ac_reld_qw : in std_ulogic_vector(57 to 59); + an_ac_reld_data : in std_ulogic_vector(0 to 127); + an_ac_reld_ecc_err : in std_ulogic; + an_ac_reld_ecc_err_ue : in std_ulogic; + + spr_ic_cls : in std_ulogic; + spr_ic_clockgate_dis : in std_ulogic; + spr_ic_bp_config : in std_ulogic_vector(0 to 3); + + iu_xu_request : out std_ulogic; + iu_xu_thread : out std_ulogic_vector(0 to 3); + iu_xu_ra : out std_ulogic_vector(REAL_IFAR'left to 59); + iu_xu_wimge : out std_ulogic_vector(0 to 4); + iu_xu_userdef : out std_ulogic_vector(0 to 3); + + event_bus_enable : in std_ulogic; + trace_bus_enable : in std_ulogic; + miss_dbg_data0 : out std_ulogic_vector(0 to 87); + miss_dbg_data1 : out std_ulogic_vector(0 to 87); + miss_dbg_data2 : out std_ulogic_vector(0 to 43); + miss_dbg_trigger : out std_ulogic_vector(0 to 11) +); +-- synopsys translate_off +-- synopsys translate_on +end iuq_ic_miss; +ARCHITECTURE IUQ_IC_MISS + OF IUQ_IC_MISS + IS +--@@ Signal Declarations +SIGNAL IU2_SM_0_PT : STD_ULOGIC_VECTOR(1 TO 49) := +(OTHERS=> 'U'); +SIGNAL IU2_SM_1_PT : STD_ULOGIC_VECTOR(1 TO 49) := +(OTHERS=> 'U'); +SIGNAL IU2_SM_2_PT : STD_ULOGIC_VECTOR(1 TO 49) := +(OTHERS=> 'U'); +SIGNAL IU2_SM_3_PT : STD_ULOGIC_VECTOR(1 TO 49) := +(OTHERS=> 'U'); +SIGNAL SELECT_LRU_WAY_PT : STD_ULOGIC_VECTOR(1 TO 24) := +(OTHERS=> 'U'); +component iuq_bd is +port( + instruction : in std_ulogic_vector(0 to 31); + branch_decode : out std_ulogic_vector(0 to 3); + + bp_bc_en : in std_ulogic; + bp_bclr_en : in std_ulogic; + bp_bcctr_en : in std_ulogic; + bp_sw_en : in std_ulogic +); +end component; +constant spr_ic_cls_offset : natural := 0; +constant bp_config_offset : natural := spr_ic_cls_offset + 1; +constant spare_offset : natural := bp_config_offset + 4; +constant an_ac_reld_data_vld_offset : natural := spare_offset + 16; +constant an_ac_reld_core_tag_offset : natural := an_ac_reld_data_vld_offset + 1; +constant an_ac_reld_qw_offset : natural := an_ac_reld_core_tag_offset + 5; +constant an_ac_reld_data_offset : natural := an_ac_reld_qw_offset + 3; +constant an_ac_reld_ecc_err_offset : natural := an_ac_reld_data_offset + 128; +constant an_ac_reld_ecc_err_ue_offset : natural := an_ac_reld_ecc_err_offset + 1; +constant reld_r1_tid_offset : natural := an_ac_reld_ecc_err_ue_offset + 1; +constant reld_r1_qw_offset : natural := reld_r1_tid_offset + 4; +constant reld_r2_tid_offset : natural := reld_r1_qw_offset + 3; +constant reld_r2_qw_offset : natural := reld_r2_tid_offset + 4; +constant r2_crit_qw_offset : natural := reld_r2_qw_offset + 3; +constant reld_r3_tid_offset : natural := r2_crit_qw_offset + 1; +constant r3_loaded_offset : natural := reld_r3_tid_offset + 4; +constant r3_need_back_inval_offset : natural := r3_loaded_offset + 1; +constant row_lru_offset : natural := r3_need_back_inval_offset + 1; +constant row_val_offset : natural := row_lru_offset + 3; +constant request_offset : natural := row_val_offset + 4; +constant req_thread_offset : natural := request_offset + 1; +constant req_ra_offset : natural := req_thread_offset + 4; +constant req_wimge_offset : natural := req_ra_offset + 60-REAL_IFAR'left; +constant req_userdef_offset : natural := req_wimge_offset + 5; +constant iu3_miss_match_offset : natural := req_userdef_offset + 4; +constant miss_tid0_sm_offset : natural := iu3_miss_match_offset + 1; +constant miss_flush_occurred0_offset : natural := miss_tid0_sm_offset + 20; +constant miss_flushed0_offset : natural := miss_flush_occurred0_offset + 1; +constant miss_inval0_offset : natural := miss_flushed0_offset + 1; +constant miss_block_fp0_offset : natural := miss_inval0_offset + 1; +constant miss_ecc_err0_offset : natural := miss_block_fp0_offset + 1; +constant miss_ecc_err_ue0_offset : natural := miss_ecc_err0_offset + 1; +constant miss_wrote_dir0_offset : natural := miss_ecc_err_ue0_offset + 1; +constant miss_need_hold0_offset : natural := miss_wrote_dir0_offset + 1; +constant miss_addr0_real_offset : natural := miss_need_hold0_offset + 1; +constant miss_addr0_eff_offset : natural := miss_addr0_real_offset + REAL_IFAR'length; +constant miss_ci0_offset : natural := miss_addr0_eff_offset + EFF_IFAR'length - 10; +constant miss_endian0_offset : natural := miss_ci0_offset + 1; +constant miss_2ucode0_offset : natural := miss_endian0_offset + 1; +constant miss_2ucode0_type_offset : natural := miss_2ucode0_offset + 1; +constant miss_way0_offset : natural := miss_2ucode0_type_offset + 1; +constant perf_event_t0_offset : natural := miss_way0_offset + 4; +constant miss_tid1_sm_offset : natural := perf_event_t0_offset + 2; +constant miss_flush_occurred1_offset : natural := miss_tid1_sm_offset + 20; +constant miss_flushed1_offset : natural := miss_flush_occurred1_offset + 1; +constant miss_inval1_offset : natural := miss_flushed1_offset + 1; +constant miss_block_fp1_offset : natural := miss_inval1_offset + 1; +constant miss_ecc_err1_offset : natural := miss_block_fp1_offset + 1; +constant miss_ecc_err_ue1_offset : natural := miss_ecc_err1_offset + 1; +constant miss_wrote_dir1_offset : natural := miss_ecc_err_ue1_offset + 1; +constant miss_need_hold1_offset : natural := miss_wrote_dir1_offset + 1; +constant miss_addr1_real_offset : natural := miss_need_hold1_offset + 1; +constant miss_addr1_eff_offset : natural := miss_addr1_real_offset + REAL_IFAR'length; +constant miss_ci1_offset : natural := miss_addr1_eff_offset + EFF_IFAR'length - 10; +constant miss_endian1_offset : natural := miss_ci1_offset + 1; +constant miss_2ucode1_offset : natural := miss_endian1_offset + 1; +constant miss_2ucode1_type_offset : natural := miss_2ucode1_offset + 1; +constant miss_way1_offset : natural := miss_2ucode1_type_offset + 1; +constant perf_event_t1_offset : natural := miss_way1_offset + 4; +constant miss_tid2_sm_offset : natural := perf_event_t1_offset + 2; +constant miss_flush_occurred2_offset : natural := miss_tid2_sm_offset + 20; +constant miss_flushed2_offset : natural := miss_flush_occurred2_offset + 1; +constant miss_inval2_offset : natural := miss_flushed2_offset + 1; +constant miss_block_fp2_offset : natural := miss_inval2_offset + 1; +constant miss_ecc_err2_offset : natural := miss_block_fp2_offset + 1; +constant miss_ecc_err_ue2_offset : natural := miss_ecc_err2_offset + 1; +constant miss_wrote_dir2_offset : natural := miss_ecc_err_ue2_offset + 1; +constant miss_need_hold2_offset : natural := miss_wrote_dir2_offset + 1; +constant miss_addr2_real_offset : natural := miss_need_hold2_offset + 1; +constant miss_addr2_eff_offset : natural := miss_addr2_real_offset + REAL_IFAR'length; +constant miss_ci2_offset : natural := miss_addr2_eff_offset + EFF_IFAR'length - 10; +constant miss_endian2_offset : natural := miss_ci2_offset + 1; +constant miss_2ucode2_offset : natural := miss_endian2_offset + 1; +constant miss_2ucode2_type_offset : natural := miss_2ucode2_offset + 1; +constant miss_way2_offset : natural := miss_2ucode2_type_offset + 1; +constant perf_event_t2_offset : natural := miss_way2_offset + 4; +constant miss_tid3_sm_offset : natural := perf_event_t2_offset + 2; +constant miss_flush_occurred3_offset : natural := miss_tid3_sm_offset + 20; +constant miss_flushed3_offset : natural := miss_flush_occurred3_offset + 1; +constant miss_inval3_offset : natural := miss_flushed3_offset + 1; +constant miss_block_fp3_offset : natural := miss_inval3_offset + 1; +constant miss_ecc_err3_offset : natural := miss_block_fp3_offset + 1; +constant miss_ecc_err_ue3_offset : natural := miss_ecc_err3_offset + 1; +constant miss_wrote_dir3_offset : natural := miss_ecc_err_ue3_offset + 1; +constant miss_need_hold3_offset : natural := miss_wrote_dir3_offset + 1; +constant miss_addr3_real_offset : natural := miss_need_hold3_offset + 1; +constant miss_addr3_eff_offset : natural := miss_addr3_real_offset + REAL_IFAR'length; +constant miss_ci3_offset : natural := miss_addr3_eff_offset + EFF_IFAR'length - 10; +constant miss_endian3_offset : natural := miss_ci3_offset + 1; +constant miss_2ucode3_offset : natural := miss_endian3_offset + 1; +constant miss_2ucode3_type_offset : natural := miss_2ucode3_offset + 1; +constant miss_way3_offset : natural := miss_2ucode3_type_offset + 1; +constant perf_event_t3_offset : natural := miss_way3_offset + 4; +constant lru_write_next_cycle_offset : natural := perf_event_t3_offset + 2; +constant lru_write_offset : natural := lru_write_next_cycle_offset + 4; +constant miss_dbg_data1_offset : natural := lru_write_offset + 4; +constant scan_right : natural := miss_dbg_data1_offset + 9 - 1; +subtype s2 is std_ulogic_vector(0 to 1); +subtype s5 is std_ulogic_vector(0 to 4); +-- Latch definition begin +signal spr_ic_cls_d : std_ulogic; +signal bp_config_d : std_ulogic_vector(0 to 3); +signal an_ac_reld_data_vld_d : std_ulogic; +signal an_ac_reld_core_tag_d : std_ulogic_vector(0 to 4); +signal an_ac_reld_qw_d : std_ulogic_vector(57 to 59); +signal an_ac_reld_data_d : std_ulogic_vector(0 to 127); +signal an_ac_reld_ecc_err_d : std_ulogic; +signal an_ac_reld_ecc_err_ue_d : std_ulogic; +signal reld_r1_tid_d : std_ulogic_vector(0 to 3); +signal reld_r1_qw_d : std_ulogic_vector(0 to 2); +signal reld_r2_tid_d : std_ulogic_vector(0 to 3); +signal reld_r2_qw_d : std_ulogic_vector(0 to 2); +signal r2_crit_qw_d : std_ulogic; +signal reld_r3_tid_d : std_ulogic_vector(0 to 3); +signal r3_loaded_d : std_ulogic; +signal r3_need_back_inval_d : std_ulogic; +signal row_lru_d : std_ulogic_vector(0 to 2); +signal row_val_d : std_ulogic_vector(0 to 3); +signal request_d : std_ulogic; +signal req_thread_d : std_ulogic_vector(0 to 3); +signal req_ra_d : std_ulogic_vector(REAL_IFAR'left to 59); +signal req_wimge_d : std_ulogic_vector(0 to 4); +signal req_userdef_d : std_ulogic_vector(0 to 3); +signal iu3_miss_match_d : std_ulogic; +signal miss_tid0_sm_d : std_ulogic_vector(0 to 19); +signal miss_flush_occurred0_d : std_ulogic; +signal miss_flushed0_d : std_ulogic; +signal miss_inval0_d : std_ulogic; +signal miss_block_fp0_d : std_ulogic; +signal miss_ecc_err0_d : std_ulogic; +signal miss_ecc_err_ue0_d : std_ulogic; +signal miss_wrote_dir0_d : std_ulogic; +signal miss_need_hold0_d : std_ulogic; +signal miss_addr0_real_d : REAL_IFAR; +signal miss_addr0_eff_d : std_ulogic_vector(EFF_IFAR'left to 51); +signal miss_ci0_d : std_ulogic; +signal miss_endian0_d : std_ulogic; +signal miss_2ucode0_d : std_ulogic; +signal miss_2ucode0_type_d : std_ulogic; +signal miss_way0_d : std_ulogic_vector(0 to 3); +signal perf_event_t0_d : std_ulogic_vector(0 to 1); +signal miss_tid1_sm_d : std_ulogic_vector(0 to 19); +signal miss_flush_occurred1_d : std_ulogic; +signal miss_flushed1_d : std_ulogic; +signal miss_inval1_d : std_ulogic; +signal miss_block_fp1_d : std_ulogic; +signal miss_ecc_err1_d : std_ulogic; +signal miss_ecc_err_ue1_d : std_ulogic; +signal miss_wrote_dir1_d : std_ulogic; +signal miss_need_hold1_d : std_ulogic; +signal miss_addr1_real_d : REAL_IFAR; +signal miss_addr1_eff_d : std_ulogic_vector(EFF_IFAR'left to 51); +signal miss_ci1_d : std_ulogic; +signal miss_endian1_d : std_ulogic; +signal miss_2ucode1_d : std_ulogic; +signal miss_2ucode1_type_d : std_ulogic; +signal miss_way1_d : std_ulogic_vector(0 to 3); +signal perf_event_t1_d : std_ulogic_vector(0 to 1); +signal miss_tid2_sm_d : std_ulogic_vector(0 to 19); +signal miss_flush_occurred2_d : std_ulogic; +signal miss_flushed2_d : std_ulogic; +signal miss_inval2_d : std_ulogic; +signal miss_block_fp2_d : std_ulogic; +signal miss_ecc_err2_d : std_ulogic; +signal miss_ecc_err_ue2_d : std_ulogic; +signal miss_wrote_dir2_d : std_ulogic; +signal miss_need_hold2_d : std_ulogic; +signal miss_addr2_real_d : REAL_IFAR; +signal miss_addr2_eff_d : std_ulogic_vector(EFF_IFAR'left to 51); +signal miss_ci2_d : std_ulogic; +signal miss_endian2_d : std_ulogic; +signal miss_2ucode2_d : std_ulogic; +signal miss_2ucode2_type_d : std_ulogic; +signal miss_way2_d : std_ulogic_vector(0 to 3); +signal perf_event_t2_d : std_ulogic_vector(0 to 1); +signal miss_tid3_sm_d : std_ulogic_vector(0 to 19); +signal miss_flush_occurred3_d : std_ulogic; +signal miss_flushed3_d : std_ulogic; +signal miss_inval3_d : std_ulogic; +signal miss_block_fp3_d : std_ulogic; +signal miss_ecc_err3_d : std_ulogic; +signal miss_ecc_err_ue3_d : std_ulogic; +signal miss_wrote_dir3_d : std_ulogic; +signal miss_need_hold3_d : std_ulogic; +signal miss_addr3_real_d : REAL_IFAR; +signal miss_addr3_eff_d : std_ulogic_vector(EFF_IFAR'left to 51); +signal miss_ci3_d : std_ulogic; +signal miss_endian3_d : std_ulogic; +signal miss_2ucode3_d : std_ulogic; +signal miss_2ucode3_type_d : std_ulogic; +signal miss_way3_d : std_ulogic_vector(0 to 3); +signal perf_event_t3_d : std_ulogic_vector(0 to 1); +signal lru_write_next_cycle_d : std_ulogic_vector(0 to 3); +signal lru_write_d : std_ulogic_vector(0 to 3); +signal spr_ic_cls_l2 : std_ulogic; +signal bp_config_l2 : std_ulogic_vector(0 to 3); +signal an_ac_reld_data_vld_l2 : std_ulogic; +signal an_ac_reld_core_tag_l2 : std_ulogic_vector(0 to 4); +signal an_ac_reld_qw_l2 : std_ulogic_vector(57 to 59); +signal an_ac_reld_data_l2 : std_ulogic_vector(0 to 127); +signal an_ac_reld_ecc_err_l2 : std_ulogic; +signal an_ac_reld_ecc_err_ue_l2 : std_ulogic; +signal reld_r1_tid_l2 : std_ulogic_vector(0 to 3); +signal reld_r1_qw_l2 : std_ulogic_vector(0 to 2); +signal reld_r2_tid_l2 : std_ulogic_vector(0 to 3); +signal reld_r2_qw_l2 : std_ulogic_vector(0 to 2); +signal r2_crit_qw_l2 : std_ulogic; +signal reld_r3_tid_l2 : std_ulogic_vector(0 to 3); +signal r3_loaded_l2 : std_ulogic; +signal r3_need_back_inval_l2 : std_ulogic; +signal row_lru_l2 : std_ulogic_vector(0 to 2); +signal row_val_l2 : std_ulogic_vector(0 to 3); +signal request_l2 : std_ulogic; +signal req_thread_l2 : std_ulogic_vector(0 to 3); +signal req_ra_l2 : std_ulogic_vector(REAL_IFAR'left to 59); +signal req_wimge_l2 : std_ulogic_vector(0 to 4); +signal req_userdef_l2 : std_ulogic_vector(0 to 3); +signal iu3_miss_match_l2 : std_ulogic; +signal miss_tid0_sm_l2 : std_ulogic_vector(0 to 19); +signal miss_flush_occurred0_l2 : std_ulogic; +signal miss_flushed0_l2 : std_ulogic; +signal miss_inval0_l2 : std_ulogic; +signal miss_block_fp0_l2 : std_ulogic; +signal miss_ecc_err0_l2 : std_ulogic; +signal miss_ecc_err_ue0_l2 : std_ulogic; +signal miss_wrote_dir0_l2 : std_ulogic; +signal miss_need_hold0_l2 : std_ulogic; +signal miss_addr0_real_l2 : REAL_IFAR; +signal miss_addr0_eff_l2 : std_ulogic_vector(EFF_IFAR'left to 51); +signal miss_ci0_l2 : std_ulogic; +signal miss_endian0_l2 : std_ulogic; +signal miss_2ucode0_l2 : std_ulogic; +signal miss_2ucode0_type_l2 : std_ulogic; +signal miss_way0_l2 : std_ulogic_vector(0 to 3); +signal perf_event_t0_l2 : std_ulogic_vector(0 to 1); +signal miss_tid1_sm_l2 : std_ulogic_vector(0 to 19); +signal miss_flush_occurred1_l2 : std_ulogic; +signal miss_flushed1_l2 : std_ulogic; +signal miss_inval1_l2 : std_ulogic; +signal miss_block_fp1_l2 : std_ulogic; +signal miss_ecc_err1_l2 : std_ulogic; +signal miss_ecc_err_ue1_l2 : std_ulogic; +signal miss_wrote_dir1_l2 : std_ulogic; +signal miss_need_hold1_l2 : std_ulogic; +signal miss_addr1_real_l2 : REAL_IFAR; +signal miss_addr1_eff_l2 : std_ulogic_vector(EFF_IFAR'left to 51); +signal miss_ci1_l2 : std_ulogic; +signal miss_endian1_l2 : std_ulogic; +signal miss_2ucode1_l2 : std_ulogic; +signal miss_2ucode1_type_l2 : std_ulogic; +signal miss_way1_l2 : std_ulogic_vector(0 to 3); +signal perf_event_t1_l2 : std_ulogic_vector(0 to 1); +signal miss_tid2_sm_l2 : std_ulogic_vector(0 to 19); +signal miss_flush_occurred2_l2 : std_ulogic; +signal miss_flushed2_l2 : std_ulogic; +signal miss_inval2_l2 : std_ulogic; +signal miss_block_fp2_l2 : std_ulogic; +signal miss_ecc_err2_l2 : std_ulogic; +signal miss_ecc_err_ue2_l2 : std_ulogic; +signal miss_wrote_dir2_l2 : std_ulogic; +signal miss_need_hold2_l2 : std_ulogic; +signal miss_addr2_real_l2 : REAL_IFAR; +signal miss_addr2_eff_l2 : std_ulogic_vector(EFF_IFAR'left to 51); +signal miss_ci2_l2 : std_ulogic; +signal miss_endian2_l2 : std_ulogic; +signal miss_2ucode2_l2 : std_ulogic; +signal miss_2ucode2_type_l2 : std_ulogic; +signal miss_way2_l2 : std_ulogic_vector(0 to 3); +signal perf_event_t2_l2 : std_ulogic_vector(0 to 1); +signal miss_tid3_sm_l2 : std_ulogic_vector(0 to 19); +signal miss_flush_occurred3_l2 : std_ulogic; +signal miss_flushed3_l2 : std_ulogic; +signal miss_inval3_l2 : std_ulogic; +signal miss_block_fp3_l2 : std_ulogic; +signal miss_ecc_err3_l2 : std_ulogic; +signal miss_ecc_err_ue3_l2 : std_ulogic; +signal miss_wrote_dir3_l2 : std_ulogic; +signal miss_need_hold3_l2 : std_ulogic; +signal miss_addr3_real_l2 : REAL_IFAR; +signal miss_addr3_eff_l2 : std_ulogic_vector(EFF_IFAR'left to 51); +signal miss_ci3_l2 : std_ulogic; +signal miss_endian3_l2 : std_ulogic; +signal miss_2ucode3_l2 : std_ulogic; +signal miss_2ucode3_type_l2 : std_ulogic; +signal miss_way3_l2 : std_ulogic_vector(0 to 3); +signal perf_event_t3_l2 : std_ulogic_vector(0 to 1); +signal lru_write_next_cycle_l2 : std_ulogic_vector(0 to 3); +signal lru_write_l2 : std_ulogic_vector(0 to 3); +signal spare_l2 : std_ulogic_vector(0 to 15); +signal miss_dbg_data1_d : std_ulogic_vector(51 to 59); +signal miss_dbg_data1_l2 : std_ulogic_vector(51 to 59); +-- Latch definition end +-- Act control; only needed for power reduction +signal default_reld_act : std_ulogic; +signal reld_r2_act : std_ulogic; +signal miss_act : std_ulogic_vector(0 to 3); +-- reload pipeline +signal reld_r0_vld : std_ulogic; +signal reld_r0_tid_plain: std_ulogic_vector(0 to 3); +signal reld_r1_vld : std_ulogic; +signal load_quiesce : std_ulogic_vector(0 to 3); +signal set_flush_occurred : std_ulogic_vector(0 to 3); +signal flush_addr_outside_range : std_ulogic_vector(0 to 3); +-- this signal sets the miss_flushed state bit +signal set_flushed : std_ulogic_vector(0 to 3); +signal inval_equal : std_ulogic_vector(0 to 3); +signal set_invalidated : std_ulogic_vector(0 to 3); +signal reset_state : std_ulogic_vector(0 to 3); +signal sent_fp : std_ulogic_vector(0 to 3); +signal set_block_fp : std_ulogic_vector(0 to 3); +-- this signal will check incoming addr against current valid addresses +signal addr_equal : std_ulogic_vector(0 to 3); +signal addr_match : std_ulogic; +signal miss_thread_is_idle : std_ulogic; +signal release_sm : std_ulogic; +signal release_sm_hold : std_ulogic_vector(0 to 3); +-- IU0 inval +signal iu0_inval_match : std_ulogic_vector(0 to 3); +signal miss_wrote_dir_v : std_ulogic_vector(0 to 3); +-- or these together to get iu_xu_request +signal request_tid : std_ulogic_vector(0 to 3); +signal erat_err : std_ulogic_vector(0 to 3); +-- fastpath +signal preload_r0_tid : std_ulogic_vector(0 to 3); +signal preload_hold_iu0 : std_ulogic; +signal load_tid : std_ulogic_vector(0 to 3); +signal r2_load_addr : EFF_IFAR; +signal r2_load_2ucode : std_ulogic; +signal r2_load_2ucode_type : std_ulogic; +signal load_tid_no_block: std_ulogic_vector(0 to 3); +-- this signal indicates critical quadword is in r0, r1 +signal r0_crit_qw : std_ulogic_vector(0 to 3); +signal r1_crit_qw : std_ulogic_vector(0 to 3); +-- lru +signal lru_write_hit : std_ulogic; +signal hit_lru : std_ulogic_vector(0 to 2); +signal select_lru : std_ulogic_vector(0 to 3); +signal r0_addr : std_ulogic_vector(52 to 59); +signal lru_valid : std_ulogic_vector(0 to 3); +signal r1_addr : std_ulogic_vector(52 to 57); +signal row_match : std_ulogic_vector(0 to 3); +signal row_match_way : std_ulogic_vector(0 to 3); +signal val_or_match : std_ulogic_vector(0 to 3); +signal next_lru_way : std_ulogic_vector(0 to 3); +signal next_way : std_ulogic_vector(0 to 3); +-- this signal is set by each state machine and or them together to final holds +signal hold_tid : std_ulogic_vector(0 to 3); +signal hold_iu0 : std_ulogic; +signal dir_inval : std_ulogic; +-- or these together to get icm_icd_* +signal write_dir_inval : std_ulogic_vector(0 to 3); +signal write_dir_val : std_ulogic_vector(0 to 3); +signal data_write : std_ulogic_vector(0 to 3); +signal dir_write : std_ulogic_vector(0 to 3); +signal dir_write_no_block : std_ulogic_vector(0 to 3); +--signal reload_addr : std_ulogic_vector(52 to 57); +signal reload_way : std_ulogic_vector(0 to 3); +signal reload_endian : std_ulogic; +signal swap_endian_data : std_ulogic_vector(0 to 127); +signal branch_decode0 : std_ulogic_vector(0 to 3); +signal swap_branch_decode0 : std_ulogic_vector(0 to 3); +signal branch_decode1 : std_ulogic_vector(0 to 3); +signal swap_branch_decode1 : std_ulogic_vector(0 to 3); +signal branch_decode2 : std_ulogic_vector(0 to 3); +signal swap_branch_decode2 : std_ulogic_vector(0 to 3); +signal branch_decode3 : std_ulogic_vector(0 to 3); +signal swap_branch_decode3 : std_ulogic_vector(0 to 3); +signal instr_data : std_ulogic_vector(0 to 143); +signal swap_data : std_ulogic_vector(0 to 143); +signal data_parity_in : std_ulogic_vector(0 to 17); +signal swap_parity_in : std_ulogic_vector(0 to 17); +signal r2_real_addr : std_ulogic_vector(REAL_IFAR'left to 57); +signal lru_write : std_ulogic_vector(0 to 3); +signal lru_write_addr : std_ulogic_vector(52 to 57); +signal lru_write_way : std_ulogic_vector(0 to 3); +signal r3_addr : std_ulogic_vector(52 to 57); +signal r3_way : std_ulogic_vector(0 to 3); +-- ECC Error handling +signal new_ecc_err : std_ulogic_vector(0 to 3); +signal new_ecc_err_ue : std_ulogic_vector(0 to 3); +signal ecc_err : std_ulogic_vector(0 to 3); +signal ecc_err_ue : std_ulogic_vector(0 to 3); +signal ecc_inval : std_ulogic_vector(0 to 3); +signal ecc_block_iu0 : std_ulogic_vector(0 to 3); +signal ecc_fp : std_ulogic; +signal siv : std_ulogic_vector(0 to scan_right); +signal sov : std_ulogic_vector(0 to scan_right); +signal tiup : std_ulogic; + BEGIN --@@ START OF EXECUTABLE CODE FOR IUQ_IC_MISS + +tiup <= '1'; +----------------------------------------------------------------------- +-- Latch Inputs, Reload pipeline +----------------------------------------------------------------------- +default_reld_act <= spr_ic_clockgate_dis or + not miss_tid0_sm_l2(0) or not miss_tid1_sm_l2(0) or not miss_tid2_sm_l2(0) or not miss_tid3_sm_l2(0); +reld_r2_act <= spr_ic_clockgate_dis or reld_r1_vld; +bp_config_d <= spr_ic_bp_config; +spr_ic_cls_d <= spr_ic_cls; +-- d-2 (r0) +an_ac_reld_data_vld_d <= an_ac_reld_data_vld; +an_ac_reld_core_tag_d <= an_ac_reld_core_tag; +an_ac_reld_qw_d <= an_ac_reld_qw; +-- d-1 (r1) +-- Core_tag(0:2) specifies unit (IU is 010 ); Core_tag(3:4) is encoded Thread ID +reld_r0_vld <= an_ac_reld_data_vld_l2 and (an_ac_reld_core_tag_l2(0 to 2) = "010"); + WITH s2'(an_ac_reld_core_tag_l2(3 to 4)) SELECT reld_r0_tid_plain <= "1000" when "00", + "0100" when "01", + "0010" when "10", + "0001" when others; +reld_r1_tid_d <= gate_and(reld_r0_vld, reld_r0_tid_plain); +reld_r1_qw_d <= an_ac_reld_qw_l2; +reld_r1_vld <= or_reduce(reld_r1_tid_l2); +-- d (r2) +-- Use reld_r1_vld as act to gate clock +an_ac_reld_data_d <= an_ac_reld_data; +reld_r2_tid_d <= reld_r1_tid_l2; +reld_r2_qw_d <= reld_r1_qw_l2; +-- d+1 (r3) +reld_r3_tid_d <= reld_r2_tid_l2; +an_ac_reld_ecc_err_d <= an_ac_reld_ecc_err; +an_ac_reld_ecc_err_ue_d <= an_ac_reld_ecc_err_ue; +----------------------------------------------------------------------- +-- State Machine +----------------------------------------------------------------------- +-- Example State Ordering for cacheable reloads +-- 64B Cacheline, No Gaps : (1)(3)(4)(5)(6)(11) - Wait 0, Data0, Data1, Data2, Data3, CheckECC +-- 64B Cacheline, Always Gaps: (1)(3)(8)(4)(9)(5)(10)(6)(11) - Wait 0, Data0, Wait1, Data1, Wait2, Data2, Wait3, Data3, CheckECC +-- 128B Cacheline, No Gaps : (1)(3)(4)(5)(12)(13)(14)(15)(6)(11) - Wait 0, Data0, Data1, Data2, Data3_128B, Data4_128B, Data5_128B, Data6_128B, Data3/7, CheckECC +-- 128B Cacheline, Always Gaps: (1)(3)(8)(4)(9)(5)(16)(12)(17)(13)(18)(14)(19)(15)(10)(6)(11) +-- - Wait 0, Data0, Wait1, Data1, Wait2, Data2, Wait3_128B, Data3_128B, Wait4_128B, Data4_128B, Wait5_128B, Data5_128B, Wait6_128B, Data6_128B, Data3/7, CheckECC +-- +-- Final Table Listing +-- *INPUTS*================================================*OUTPUTS*======================================================* +-- | | | +-- | icd_icm_miss | miss_tid0_sm_d | +-- | | icd_icm_tid(0) | | | +-- | | | icd_icm_wimge(1) | | reset_state(0) | -- WIMGE(1): Cache Inhibit +-- | | | | erat_err(0) | | | | +-- | | | | | miss_ci0_l2 | | | request_tid(0) | +-- | | | | | | reld_r1_tid_l2(0) | | | | write_dir_inval(0) | +-- | | | | | | | r2_crit_qw_l2 | | | | | write_dir_val(0) | +-- | | | | | | | | ecc_err(0) | | | | | | | +-- | | | | | | | | | ecc_err_ue(0) | | | | | | | +-- | | | | | | | | | | | | | | | | | +-- | | | | | | | | | | spr_ic_cls_l2 | | | | | | | +-- | | | | | | | | | | | addr_match | | | | | | | +-- | | | | | | | | | | | | ics_icm_iu2_flush_tid(0) | | | | | | hold_tid(0) | -- this hold 1 tid and gates iu2 +-- | | | | | | | | | | | | | release_sm | | | | | | | | +-- | | | | | | | | | | | | | | miss_flushed0_l2 | | | | | | | | +-- | | | | | | | | | | | | | | | miss_inval0_l2 | | | | | | | | +-- | | | | | | | | | | | | | | | | miss_tid0_sm_l2 | | | | | | | | +-- | | | | | | | | | | | | | | | | | | | | | | | | | +-- | | | | | | | | | | | | | | | | | | | | | | | | data_write(0) | +-- | | | | | | | | | | | | | | | | | | | | | | | | | dir_write(0) | +-- | | | | | | | | | | | | | | | | | | | | | | | | | | | +-- | | | | | | | | | | | | | | | | | | | | | | | | | | load_tid(0) | +-- | | | | | | | | | | | | | | | | | | | | | | | | | | | | +-- | | | | | | | | | | | | | | | | | | | | | | | | | | | release_sm_hold(0)| +-- | | | | | | | | | | | | | | | | | | | | | | | | | | | | | +-- | | | | | | | | | | | | | | | | | | | | | | | | | | | | | +-- | | | | | | | | | | | | | | | | | 1111111111 | | 1111111111 | | | | | | | | | | +-- | | | | | | | | | | | | | | | | 01234567890123456789 | 01234567890123456789 | | | | | | | | | | +-- *TYPE*==================================================+==============================================================+ +-- | P P P P P P P P P P P P P P P PPPPPPPPPPPPPPPPPPPP | PPPPPPPPPPPPPPPPPPPP P P P P P P P P P | +-- *POLARITY*--------------------------------------------->| ++++++++++++++++++++ + + + + + + + + + | +-- *PHASE*------------------------------------------------>| TTTTTTTTTTTTTTTTTTTT T T T T T T T T T | +-- *OPTIMIZE*--------------------------------------------->| AAAAAAAAAAAAAAAAAAAA A A A A B A A A A | +-- *TERMS*=================================================+==============================================================+ +-- 1 | - - - - - - - - - - - 1 - - - -0-00000000000000000 | 1................... . . . . . . . . . | +-- 2 | - - - - - - - - - - - - - - - 000000--000000000000 | ...........1........ . . . . . . . . 1 | +-- 3 | - - - - - 0 - - - - - - - - - 0000-0000-0000000000 | .........1.......... . . . . . . . . . | +-- 4 | - - - - - 1 - - - - - - - - - 0000-0-00-0000000000 | .....1.............. . . . . . . . . . | +-- 5 | - - - - - - - - - - - - - 0 0 000---000000----0000 | .................... . . . . . 1 1 . . | +-- 6 | - - - - - - 1 - - - - - - 0 - 000-----0000----0000 | .................... . . . . . . . 1 . | +-- 7 | - - - - - 0 - - - - - - - - - 000000000000-0000-00 | .................1.. . . . . . . . . . | +-- 8 | - - - - - 1 - - - - - - - - - 000000-00000-0000-00 | .............1...... . . . . . . . . . | +-- 9 | - - - - - 0 - - - - - - - - - 00000000000000-0000- | ...................1 . . . . . . . . . | +-- 10 | - - - - - 1 - - - - - - - - - 000000-0000000-0000- | ...............1.... . . . . . . . . . | +-- 11 | - - - - - - - - - - - - - - - ------------------1- | ..............1..... . . . . . . . . . | +-- 12 | - - - - - - - - - - - - - - - ----------------1--- | ............1....... . . . . . . . . . | +-- 13 | - - - - - 0 - - - - - - - - - ---------------1---- | ..........1......... . . . . . . . . . | +-- 14 | - - - - - 1 - - - - - - - - - ---------------1---- | ......1............. . . . . . . . . . | +-- 15 | - - - - - 0 - - - - - - - - - -------------1------ | ..................1. . . . . . . . . . | +-- 16 | - - - - - 1 - - - - - - - - - -------------1------ | ..............1..... . . . . . . . . . | +-- 17 | - - - - - - - - - - - - - - - 000---00---0-------- | .................... . . . . 1 . . . . | +-- 18 | - - - 0 - - - - - - - - - - - 0-----00---0-------- | .................... . . . . 1 . . . . | +-- 19 | - - - - - - - 0 - - - - - - - -----------1-------- | 1................... 1 . . . . . . . 1 | +-- 20 | - - - - - - - 1 - - - - - - - -----------1-------- | .1.................. . . . . . . . . . | +-- 21 | - - - - - - - - - - - - - - - ----------1--------- | ......1............. . . . . . . . . . | +-- 22 | - - - - - - - - - - - - - - - --------1----------- | ....1............... . . . . . . . . . | +-- 23 | - - - - - - - 1 - - - - - - - 000----0------------ | .................... . . . . 1 . . . . | +-- 24 | - - - - - - - - - - - - - 0 - -------1------------ | .................... . . . . . . . 1 . | +-- 25 | - - - - - - - 0 0 - - - - 0 0 ------1------------- | .................... . . . 1 . . . . . | +-- 26 | - - - - - - - - - - - - - 0 0 ------1------------- | .................... . . . . . 1 . . . | +-- 27 | - - - - - - - - - - - - - - 1 ------1------------- | .................... . . . . 1 . . . . | +-- 28 | - - - - - - - - - - - - - 1 - ------1------------- | .................... . . . . 1 . . . . | +-- 29 | - - - - - - - - 1 - - - - - - ------1------------- | .................... . . . . 1 . . . . | +-- 30 | - - - - - 0 - - - 0 - - - - - -----1-------------- | ..........1......... . . . . . . . . . | +-- 31 | - - - - - 1 - - - 0 - - - - - -----1-------------- | ......1............. . . . . . . . . . | +-- 32 | - - - - - 0 - - - 1 - - - - - -----1-------------- | ................1... . . . . . . . . . | +-- 33 | - - - - - 1 - - - 1 - - - - - -----1-------------- | ............1....... . . . . . . . . . | +-- 34 | - - - - - - - - - - - - - 0 0 ---1---------------- | .................... . . 1 . . . . . . | +-- 35 | - - - - - 0 - - - - - - - - - ---1---------------- | ........1........... . . . . . . . . . | +-- 36 | - - - - - 1 - - - - - - - - - ---1---------------- | ....1............... . . . . . . . . . | +-- 37 | - - - 0 - - - - - - - 0 0 - - --1----------------- | ..1................. . . . . . . . . . | +-- 38 | - - - - - - - - - - - - 1 - - --1----------------- | 1................... . . . . . . . . . | +-- 39 | - - - 1 - - - - - - - - - - - --1----------------- | 1................... . . . . . . . . . | +-- 40 | - - - 0 - 0 - - - - - - - - - -1------------------ | .1.................. . . . . . . . . . | +-- 41 | - - - 0 0 1 - - - - - - - - - -1------------------ | ...1................ . . . . . . . . . | +-- 42 | - - - 0 1 1 - - - - - - - - - -1------------------ | .......1............ . . . . . . . . . | +-- 43 | - - - 1 - - - - - - - - - - - -1------------------ | 1................... 1 . . . . . . . 1 | +-- 44 | 1 1 0 - - - - - - - 1 0 0 - - 1------------------- | ..1................. . . . . . . . . . | +-- 45 | - - 0 - - - - - - - 1 - 1 - - 1------------------- | 1................... . . . . . . . . . | +-- 46 | 1 1 - - - - - - - - 0 0 - - - 1------------------- | .1.................. . 1 . . . . . . . | +-- 47 | 1 1 1 - - - - - - - - 0 - - - 1------------------- | .1.................. . 1 . . . . . . . | +-- 48 | - 0 - - - - - - - - - - - - - 1------------------- | 1................... . . . . . . . . . | +-- 49 | 0 - - - - - - - - - - - - - - 1------------------- | 1................... . . . . . . . . . | +-- *======================================================================================================================* +-- +-- Table IU2_SM_0 Signal Assignments for Product Terms +MQQ1:IU2_SM_0_PT(1) <= + Eq(( ICS_ICM_IU2_FLUSH_TID(0) & MISS_TID0_SM_L2(1) & + MISS_TID0_SM_L2(3) & MISS_TID0_SM_L2(4) & + MISS_TID0_SM_L2(5) & MISS_TID0_SM_L2(6) & + MISS_TID0_SM_L2(7) & MISS_TID0_SM_L2(8) & + MISS_TID0_SM_L2(9) & MISS_TID0_SM_L2(10) & + MISS_TID0_SM_L2(11) & MISS_TID0_SM_L2(12) & + MISS_TID0_SM_L2(13) & MISS_TID0_SM_L2(14) & + MISS_TID0_SM_L2(15) & MISS_TID0_SM_L2(16) & + MISS_TID0_SM_L2(17) & MISS_TID0_SM_L2(18) & + MISS_TID0_SM_L2(19) ) , STD_ULOGIC_VECTOR'("1000000000000000000")); +MQQ2:IU2_SM_0_PT(2) <= + Eq(( MISS_TID0_SM_L2(0) & MISS_TID0_SM_L2(1) & + MISS_TID0_SM_L2(2) & MISS_TID0_SM_L2(3) & + MISS_TID0_SM_L2(4) & MISS_TID0_SM_L2(5) & + MISS_TID0_SM_L2(8) & MISS_TID0_SM_L2(9) & + MISS_TID0_SM_L2(10) & MISS_TID0_SM_L2(11) & + MISS_TID0_SM_L2(12) & MISS_TID0_SM_L2(13) & + MISS_TID0_SM_L2(14) & MISS_TID0_SM_L2(15) & + MISS_TID0_SM_L2(16) & MISS_TID0_SM_L2(17) & + MISS_TID0_SM_L2(18) & MISS_TID0_SM_L2(19) + ) , STD_ULOGIC_VECTOR'("000000000000000000")); +MQQ3:IU2_SM_0_PT(3) <= + Eq(( RELD_R1_TID_L2(0) & MISS_TID0_SM_L2(0) & + MISS_TID0_SM_L2(1) & MISS_TID0_SM_L2(2) & + MISS_TID0_SM_L2(3) & MISS_TID0_SM_L2(5) & + MISS_TID0_SM_L2(6) & MISS_TID0_SM_L2(7) & + MISS_TID0_SM_L2(8) & MISS_TID0_SM_L2(10) & + MISS_TID0_SM_L2(11) & MISS_TID0_SM_L2(12) & + MISS_TID0_SM_L2(13) & MISS_TID0_SM_L2(14) & + MISS_TID0_SM_L2(15) & MISS_TID0_SM_L2(16) & + MISS_TID0_SM_L2(17) & MISS_TID0_SM_L2(18) & + MISS_TID0_SM_L2(19) ) , STD_ULOGIC_VECTOR'("0000000000000000000")); +MQQ4:IU2_SM_0_PT(4) <= + Eq(( RELD_R1_TID_L2(0) & MISS_TID0_SM_L2(0) & + MISS_TID0_SM_L2(1) & MISS_TID0_SM_L2(2) & + MISS_TID0_SM_L2(3) & MISS_TID0_SM_L2(5) & + MISS_TID0_SM_L2(7) & MISS_TID0_SM_L2(8) & + MISS_TID0_SM_L2(10) & MISS_TID0_SM_L2(11) & + MISS_TID0_SM_L2(12) & MISS_TID0_SM_L2(13) & + MISS_TID0_SM_L2(14) & MISS_TID0_SM_L2(15) & + MISS_TID0_SM_L2(16) & MISS_TID0_SM_L2(17) & + MISS_TID0_SM_L2(18) & MISS_TID0_SM_L2(19) + ) , STD_ULOGIC_VECTOR'("100000000000000000")); +MQQ5:IU2_SM_0_PT(5) <= + Eq(( MISS_FLUSHED0_L2 & MISS_INVAL0_L2 & + MISS_TID0_SM_L2(0) & MISS_TID0_SM_L2(1) & + MISS_TID0_SM_L2(2) & MISS_TID0_SM_L2(6) & + MISS_TID0_SM_L2(7) & MISS_TID0_SM_L2(8) & + MISS_TID0_SM_L2(9) & MISS_TID0_SM_L2(10) & + MISS_TID0_SM_L2(11) & MISS_TID0_SM_L2(16) & + MISS_TID0_SM_L2(17) & MISS_TID0_SM_L2(18) & + MISS_TID0_SM_L2(19) ) , STD_ULOGIC_VECTOR'("000000000000000")); +MQQ6:IU2_SM_0_PT(6) <= + Eq(( R2_CRIT_QW_L2 & MISS_FLUSHED0_L2 & + MISS_TID0_SM_L2(0) & MISS_TID0_SM_L2(1) & + MISS_TID0_SM_L2(2) & MISS_TID0_SM_L2(8) & + MISS_TID0_SM_L2(9) & MISS_TID0_SM_L2(10) & + MISS_TID0_SM_L2(11) & MISS_TID0_SM_L2(16) & + MISS_TID0_SM_L2(17) & MISS_TID0_SM_L2(18) & + MISS_TID0_SM_L2(19) ) , STD_ULOGIC_VECTOR'("1000000000000")); +MQQ7:IU2_SM_0_PT(7) <= + Eq(( RELD_R1_TID_L2(0) & MISS_TID0_SM_L2(0) & + MISS_TID0_SM_L2(1) & MISS_TID0_SM_L2(2) & + MISS_TID0_SM_L2(3) & MISS_TID0_SM_L2(4) & + MISS_TID0_SM_L2(5) & MISS_TID0_SM_L2(6) & + MISS_TID0_SM_L2(7) & MISS_TID0_SM_L2(8) & + MISS_TID0_SM_L2(9) & MISS_TID0_SM_L2(10) & + MISS_TID0_SM_L2(11) & MISS_TID0_SM_L2(13) & + MISS_TID0_SM_L2(14) & MISS_TID0_SM_L2(15) & + MISS_TID0_SM_L2(16) & MISS_TID0_SM_L2(18) & + MISS_TID0_SM_L2(19) ) , STD_ULOGIC_VECTOR'("0000000000000000000")); +MQQ8:IU2_SM_0_PT(8) <= + Eq(( RELD_R1_TID_L2(0) & MISS_TID0_SM_L2(0) & + MISS_TID0_SM_L2(1) & MISS_TID0_SM_L2(2) & + MISS_TID0_SM_L2(3) & MISS_TID0_SM_L2(4) & + MISS_TID0_SM_L2(5) & MISS_TID0_SM_L2(7) & + MISS_TID0_SM_L2(8) & MISS_TID0_SM_L2(9) & + MISS_TID0_SM_L2(10) & MISS_TID0_SM_L2(11) & + MISS_TID0_SM_L2(13) & MISS_TID0_SM_L2(14) & + MISS_TID0_SM_L2(15) & MISS_TID0_SM_L2(16) & + MISS_TID0_SM_L2(18) & MISS_TID0_SM_L2(19) + ) , STD_ULOGIC_VECTOR'("100000000000000000")); +MQQ9:IU2_SM_0_PT(9) <= + Eq(( RELD_R1_TID_L2(0) & MISS_TID0_SM_L2(0) & + MISS_TID0_SM_L2(1) & MISS_TID0_SM_L2(2) & + MISS_TID0_SM_L2(3) & MISS_TID0_SM_L2(4) & + MISS_TID0_SM_L2(5) & MISS_TID0_SM_L2(6) & + MISS_TID0_SM_L2(7) & MISS_TID0_SM_L2(8) & + MISS_TID0_SM_L2(9) & MISS_TID0_SM_L2(10) & + MISS_TID0_SM_L2(11) & MISS_TID0_SM_L2(12) & + MISS_TID0_SM_L2(13) & MISS_TID0_SM_L2(15) & + MISS_TID0_SM_L2(16) & MISS_TID0_SM_L2(17) & + MISS_TID0_SM_L2(18) ) , STD_ULOGIC_VECTOR'("0000000000000000000")); +MQQ10:IU2_SM_0_PT(10) <= + Eq(( RELD_R1_TID_L2(0) & MISS_TID0_SM_L2(0) & + MISS_TID0_SM_L2(1) & MISS_TID0_SM_L2(2) & + MISS_TID0_SM_L2(3) & MISS_TID0_SM_L2(4) & + MISS_TID0_SM_L2(5) & MISS_TID0_SM_L2(7) & + MISS_TID0_SM_L2(8) & MISS_TID0_SM_L2(9) & + MISS_TID0_SM_L2(10) & MISS_TID0_SM_L2(11) & + MISS_TID0_SM_L2(12) & MISS_TID0_SM_L2(13) & + MISS_TID0_SM_L2(15) & MISS_TID0_SM_L2(16) & + MISS_TID0_SM_L2(17) & MISS_TID0_SM_L2(18) + ) , STD_ULOGIC_VECTOR'("100000000000000000")); +MQQ11:IU2_SM_0_PT(11) <= + Eq(( MISS_TID0_SM_L2(18) ) , STD_ULOGIC'('1')); +MQQ12:IU2_SM_0_PT(12) <= + Eq(( MISS_TID0_SM_L2(16) ) , STD_ULOGIC'('1')); +MQQ13:IU2_SM_0_PT(13) <= + Eq(( RELD_R1_TID_L2(0) & MISS_TID0_SM_L2(15) + ) , STD_ULOGIC_VECTOR'("01")); +MQQ14:IU2_SM_0_PT(14) <= + Eq(( RELD_R1_TID_L2(0) & MISS_TID0_SM_L2(15) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ15:IU2_SM_0_PT(15) <= + Eq(( RELD_R1_TID_L2(0) & MISS_TID0_SM_L2(13) + ) , STD_ULOGIC_VECTOR'("01")); +MQQ16:IU2_SM_0_PT(16) <= + Eq(( RELD_R1_TID_L2(0) & MISS_TID0_SM_L2(13) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ17:IU2_SM_0_PT(17) <= + Eq(( MISS_TID0_SM_L2(0) & MISS_TID0_SM_L2(1) & + MISS_TID0_SM_L2(2) & MISS_TID0_SM_L2(6) & + MISS_TID0_SM_L2(7) & MISS_TID0_SM_L2(11) + ) , STD_ULOGIC_VECTOR'("000000")); +MQQ18:IU2_SM_0_PT(18) <= + Eq(( ERAT_ERR(0) & MISS_TID0_SM_L2(0) & + MISS_TID0_SM_L2(6) & MISS_TID0_SM_L2(7) & + MISS_TID0_SM_L2(11) ) , STD_ULOGIC_VECTOR'("00000")); +MQQ19:IU2_SM_0_PT(19) <= + Eq(( ECC_ERR(0) & MISS_TID0_SM_L2(11) + ) , STD_ULOGIC_VECTOR'("01")); +MQQ20:IU2_SM_0_PT(20) <= + Eq(( ECC_ERR(0) & MISS_TID0_SM_L2(11) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ21:IU2_SM_0_PT(21) <= + Eq(( MISS_TID0_SM_L2(10) ) , STD_ULOGIC'('1')); +MQQ22:IU2_SM_0_PT(22) <= + Eq(( MISS_TID0_SM_L2(8) ) , STD_ULOGIC'('1')); +MQQ23:IU2_SM_0_PT(23) <= + Eq(( ECC_ERR(0) & MISS_TID0_SM_L2(0) & + MISS_TID0_SM_L2(1) & MISS_TID0_SM_L2(2) & + MISS_TID0_SM_L2(7) ) , STD_ULOGIC_VECTOR'("10000")); +MQQ24:IU2_SM_0_PT(24) <= + Eq(( MISS_FLUSHED0_L2 & MISS_TID0_SM_L2(7) + ) , STD_ULOGIC_VECTOR'("01")); +MQQ25:IU2_SM_0_PT(25) <= + Eq(( ECC_ERR(0) & ECC_ERR_UE(0) & + MISS_FLUSHED0_L2 & MISS_INVAL0_L2 & + MISS_TID0_SM_L2(6) ) , STD_ULOGIC_VECTOR'("00001")); +MQQ26:IU2_SM_0_PT(26) <= + Eq(( MISS_FLUSHED0_L2 & MISS_INVAL0_L2 & + MISS_TID0_SM_L2(6) ) , STD_ULOGIC_VECTOR'("001")); +MQQ27:IU2_SM_0_PT(27) <= + Eq(( MISS_INVAL0_L2 & MISS_TID0_SM_L2(6) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ28:IU2_SM_0_PT(28) <= + Eq(( MISS_FLUSHED0_L2 & MISS_TID0_SM_L2(6) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ29:IU2_SM_0_PT(29) <= + Eq(( ECC_ERR_UE(0) & MISS_TID0_SM_L2(6) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ30:IU2_SM_0_PT(30) <= + Eq(( RELD_R1_TID_L2(0) & SPR_IC_CLS_L2 & + MISS_TID0_SM_L2(5) ) , STD_ULOGIC_VECTOR'("001")); +MQQ31:IU2_SM_0_PT(31) <= + Eq(( RELD_R1_TID_L2(0) & SPR_IC_CLS_L2 & + MISS_TID0_SM_L2(5) ) , STD_ULOGIC_VECTOR'("101")); +MQQ32:IU2_SM_0_PT(32) <= + Eq(( RELD_R1_TID_L2(0) & SPR_IC_CLS_L2 & + MISS_TID0_SM_L2(5) ) , STD_ULOGIC_VECTOR'("011")); +MQQ33:IU2_SM_0_PT(33) <= + Eq(( RELD_R1_TID_L2(0) & SPR_IC_CLS_L2 & + MISS_TID0_SM_L2(5) ) , STD_ULOGIC_VECTOR'("111")); +MQQ34:IU2_SM_0_PT(34) <= + Eq(( MISS_FLUSHED0_L2 & MISS_INVAL0_L2 & + MISS_TID0_SM_L2(3) ) , STD_ULOGIC_VECTOR'("001")); +MQQ35:IU2_SM_0_PT(35) <= + Eq(( RELD_R1_TID_L2(0) & MISS_TID0_SM_L2(3) + ) , STD_ULOGIC_VECTOR'("01")); +MQQ36:IU2_SM_0_PT(36) <= + Eq(( RELD_R1_TID_L2(0) & MISS_TID0_SM_L2(3) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ37:IU2_SM_0_PT(37) <= + Eq(( ERAT_ERR(0) & ICS_ICM_IU2_FLUSH_TID(0) & + RELEASE_SM & MISS_TID0_SM_L2(2) + ) , STD_ULOGIC_VECTOR'("0001")); +MQQ38:IU2_SM_0_PT(38) <= + Eq(( RELEASE_SM & MISS_TID0_SM_L2(2) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ39:IU2_SM_0_PT(39) <= + Eq(( ERAT_ERR(0) & MISS_TID0_SM_L2(2) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ40:IU2_SM_0_PT(40) <= + Eq(( ERAT_ERR(0) & RELD_R1_TID_L2(0) & + MISS_TID0_SM_L2(1) ) , STD_ULOGIC_VECTOR'("001")); +MQQ41:IU2_SM_0_PT(41) <= + Eq(( ERAT_ERR(0) & MISS_CI0_L2 & + RELD_R1_TID_L2(0) & MISS_TID0_SM_L2(1) + ) , STD_ULOGIC_VECTOR'("0011")); +MQQ42:IU2_SM_0_PT(42) <= + Eq(( ERAT_ERR(0) & MISS_CI0_L2 & + RELD_R1_TID_L2(0) & MISS_TID0_SM_L2(1) + ) , STD_ULOGIC_VECTOR'("0111")); +MQQ43:IU2_SM_0_PT(43) <= + Eq(( ERAT_ERR(0) & MISS_TID0_SM_L2(1) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ44:IU2_SM_0_PT(44) <= + Eq(( ICD_ICM_MISS & ICD_ICM_TID(0) & + ICD_ICM_WIMGE(1) & ADDR_MATCH & + ICS_ICM_IU2_FLUSH_TID(0) & RELEASE_SM & + MISS_TID0_SM_L2(0) ) , STD_ULOGIC_VECTOR'("1101001")); +MQQ45:IU2_SM_0_PT(45) <= + Eq(( ICD_ICM_WIMGE(1) & ADDR_MATCH & + RELEASE_SM & MISS_TID0_SM_L2(0) + ) , STD_ULOGIC_VECTOR'("0111")); +MQQ46:IU2_SM_0_PT(46) <= + Eq(( ICD_ICM_MISS & ICD_ICM_TID(0) & + ADDR_MATCH & ICS_ICM_IU2_FLUSH_TID(0) & + MISS_TID0_SM_L2(0) ) , STD_ULOGIC_VECTOR'("11001")); +MQQ47:IU2_SM_0_PT(47) <= + Eq(( ICD_ICM_MISS & ICD_ICM_TID(0) & + ICD_ICM_WIMGE(1) & ICS_ICM_IU2_FLUSH_TID(0) & + MISS_TID0_SM_L2(0) ) , STD_ULOGIC_VECTOR'("11101")); +MQQ48:IU2_SM_0_PT(48) <= + Eq(( ICD_ICM_TID(0) & MISS_TID0_SM_L2(0) + ) , STD_ULOGIC_VECTOR'("01")); +MQQ49:IU2_SM_0_PT(49) <= + Eq(( ICD_ICM_MISS & MISS_TID0_SM_L2(0) + ) , STD_ULOGIC_VECTOR'("01")); +-- Table IU2_SM_0 Signal Assignments for Outputs +MQQ50:MISS_TID0_SM_D(0) <= + (IU2_SM_0_PT(1) OR IU2_SM_0_PT(19) + OR IU2_SM_0_PT(38) OR IU2_SM_0_PT(39) + OR IU2_SM_0_PT(43) OR IU2_SM_0_PT(45) + OR IU2_SM_0_PT(48) OR IU2_SM_0_PT(49) + ); +MQQ51:MISS_TID0_SM_D(1) <= + (IU2_SM_0_PT(20) OR IU2_SM_0_PT(40) + OR IU2_SM_0_PT(46) OR IU2_SM_0_PT(47) + ); +MQQ52:MISS_TID0_SM_D(2) <= + (IU2_SM_0_PT(37) OR IU2_SM_0_PT(44) + ); +MQQ53:MISS_TID0_SM_D(3) <= + (IU2_SM_0_PT(41)); +MQQ54:MISS_TID0_SM_D(4) <= + (IU2_SM_0_PT(22) OR IU2_SM_0_PT(36) + ); +MQQ55:MISS_TID0_SM_D(5) <= + (IU2_SM_0_PT(4)); +MQQ56:MISS_TID0_SM_D(6) <= + (IU2_SM_0_PT(14) OR IU2_SM_0_PT(21) + OR IU2_SM_0_PT(31)); +MQQ57:MISS_TID0_SM_D(7) <= + (IU2_SM_0_PT(42)); +MQQ58:MISS_TID0_SM_D(8) <= + (IU2_SM_0_PT(35)); +MQQ59:MISS_TID0_SM_D(9) <= + (IU2_SM_0_PT(3)); +MQQ60:MISS_TID0_SM_D(10) <= + (IU2_SM_0_PT(13) OR IU2_SM_0_PT(30) + ); +MQQ61:MISS_TID0_SM_D(11) <= + (IU2_SM_0_PT(2)); +MQQ62:MISS_TID0_SM_D(12) <= + (IU2_SM_0_PT(12) OR IU2_SM_0_PT(33) + ); +MQQ63:MISS_TID0_SM_D(13) <= + (IU2_SM_0_PT(8)); +MQQ64:MISS_TID0_SM_D(14) <= + (IU2_SM_0_PT(11) OR IU2_SM_0_PT(16) + ); +MQQ65:MISS_TID0_SM_D(15) <= + (IU2_SM_0_PT(10)); +MQQ66:MISS_TID0_SM_D(16) <= + (IU2_SM_0_PT(32)); +MQQ67:MISS_TID0_SM_D(17) <= + (IU2_SM_0_PT(7)); +MQQ68:MISS_TID0_SM_D(18) <= + (IU2_SM_0_PT(15)); +MQQ69:MISS_TID0_SM_D(19) <= + (IU2_SM_0_PT(9)); +MQQ70:RESET_STATE(0) <= + (IU2_SM_0_PT(19) OR IU2_SM_0_PT(43) + ); +MQQ71:REQUEST_TID(0) <= + (IU2_SM_0_PT(46) OR IU2_SM_0_PT(47) + ); + +MQQ72:WRITE_DIR_INVAL(0) <= + (IU2_SM_0_PT(34)); +MQQ73:WRITE_DIR_VAL(0) <= + (IU2_SM_0_PT(25)); +MQQ74:HOLD_TID(0) <= + (IU2_SM_0_PT(17) OR IU2_SM_0_PT(18) + OR IU2_SM_0_PT(23) OR IU2_SM_0_PT(27) + OR IU2_SM_0_PT(28) OR IU2_SM_0_PT(29) + ); +MQQ75:DATA_WRITE(0) <= + (IU2_SM_0_PT(5) OR IU2_SM_0_PT(26) + ); +MQQ76:DIR_WRITE(0) <= + (IU2_SM_0_PT(5)); +MQQ77:LOAD_TID(0) <= + (IU2_SM_0_PT(6) OR IU2_SM_0_PT(24) + ); +MQQ78:RELEASE_SM_HOLD(0) <= + (IU2_SM_0_PT(2) OR IU2_SM_0_PT(19) + OR IU2_SM_0_PT(43)); + +-- +-- Final Table Listing +-- *INPUTS*================================================*OUTPUTS*======================================================* +-- | | | +-- | icd_icm_miss | miss_tid1_sm_d | +-- | | icd_icm_tid(1) | | | +-- | | | icd_icm_wimge(1) | | reset_state(1) | -- WIMGE(1): Cache Inhibit +-- | | | | erat_err(1) | | | | +-- | | | | | miss_ci1_l2 | | | request_tid(1) | +-- | | | | | | reld_r1_tid_l2(1) | | | | write_dir_inval(1) | +-- | | | | | | | r2_crit_qw_l2 | | | | | write_dir_val(1) | +-- | | | | | | | | ecc_err(1) | | | | | | | +-- | | | | | | | | | ecc_err_ue(1) | | | | | | | +-- | | | | | | | | | | | | | | | | | +-- | | | | | | | | | | spr_ic_cls_l2 | | | | | | | +-- | | | | | | | | | | | addr_match | | | | | | | +-- | | | | | | | | | | | | ics_icm_iu2_flush_tid(1) | | | | | | hold_tid(1) | -- this hold 1 tid and gates iu2 +-- | | | | | | | | | | | | | release_sm | | | | | | | | +-- | | | | | | | | | | | | | | miss_flushed1_l2 | | | | | | | | +-- | | | | | | | | | | | | | | | miss_inval1_l2 | | | | | | | | +-- | | | | | | | | | | | | | | | | miss_tid1_sm_l2 | | | | | | | | +-- | | | | | | | | | | | | | | | | | | | | | | | | | +-- | | | | | | | | | | | | | | | | | | | | | | | | data_write(1) | +-- | | | | | | | | | | | | | | | | | | | | | | | | | dir_write(1) | +-- | | | | | | | | | | | | | | | | | | | | | | | | | | | +-- | | | | | | | | | | | | | | | | | | | | | | | | | | load_tid(1) | +-- | | | | | | | | | | | | | | | | | | | | | | | | | | | | +-- | | | | | | | | | | | | | | | | | | | | | | | | | | | release_sm_hold(1)| +-- | | | | | | | | | | | | | | | | | | | | | | | | | | | | | +-- | | | | | | | | | | | | | | | | | | | | | | | | | | | | | +-- | | | | | | | | | | | | | | | | | 1111111111 | | 1111111111 | | | | | | | | | | +-- | | | | | | | | | | | | | | | | 01234567890123456789 | 01234567890123456789 | | | | | | | | | | +-- *TYPE*==================================================+==============================================================+ +-- | P P P P P P P P P P P P P P P PPPPPPPPPPPPPPPPPPPP | PPPPPPPPPPPPPPPPPPPP P P P P P P P P P | +-- *POLARITY*--------------------------------------------->| ++++++++++++++++++++ + + + + + + + + + | +-- *PHASE*------------------------------------------------>| TTTTTTTTTTTTTTTTTTTT T T T T T T T T T | +-- *OPTIMIZE*--------------------------------------------->| AAAAAAAAAAAAAAAAAAAA A A A A B A A A A | +-- *TERMS*=================================================+==============================================================+ +-- 1 | - - - - - - - - - - - 1 - - - -0-00000000000000000 | 1................... . . . . . . . . . | +-- 2 | - - - - - - - - - - - - - - - 000000--000000000000 | ...........1........ . . . . . . . . 1 | +-- 3 | - - - - - 0 - - - - - - - - - 0000-0000-0000000000 | .........1.......... . . . . . . . . . | +-- 4 | - - - - - 1 - - - - - - - - - 0000-0-00-0000000000 | .....1.............. . . . . . . . . . | +-- 5 | - - - - - - - - - - - - - 0 0 000---000000----0000 | .................... . . . . . 1 1 . . | +-- 6 | - - - - - - 1 - - - - - - 0 - 000-----0000----0000 | .................... . . . . . . . 1 . | +-- 7 | - - - - - 0 - - - - - - - - - 000000000000-0000-00 | .................1.. . . . . . . . . . | +-- 8 | - - - - - 1 - - - - - - - - - 000000-00000-0000-00 | .............1...... . . . . . . . . . | +-- 9 | - - - - - 0 - - - - - - - - - 00000000000000-0000- | ...................1 . . . . . . . . . | +-- 10 | - - - - - 1 - - - - - - - - - 000000-0000000-0000- | ...............1.... . . . . . . . . . | +-- 11 | - - - - - - - - - - - - - - - ------------------1- | ..............1..... . . . . . . . . . | +-- 12 | - - - - - - - - - - - - - - - ----------------1--- | ............1....... . . . . . . . . . | +-- 13 | - - - - - 0 - - - - - - - - - ---------------1---- | ..........1......... . . . . . . . . . | +-- 14 | - - - - - 1 - - - - - - - - - ---------------1---- | ......1............. . . . . . . . . . | +-- 15 | - - - - - 0 - - - - - - - - - -------------1------ | ..................1. . . . . . . . . . | +-- 16 | - - - - - 1 - - - - - - - - - -------------1------ | ..............1..... . . . . . . . . . | +-- 17 | - - - - - - - - - - - - - - - 000---00---0-------- | .................... . . . . 1 . . . . | +-- 18 | - - - 0 - - - - - - - - - - - 0-----00---0-------- | .................... . . . . 1 . . . . | +-- 19 | - - - - - - - 0 - - - - - - - -----------1-------- | 1................... 1 . . . . . . . 1 | +-- 20 | - - - - - - - 1 - - - - - - - -----------1-------- | .1.................. . . . . . . . . . | +-- 21 | - - - - - - - - - - - - - - - ----------1--------- | ......1............. . . . . . . . . . | +-- 22 | - - - - - - - - - - - - - - - --------1----------- | ....1............... . . . . . . . . . | +-- 23 | - - - - - - - 1 - - - - - - - 000----0------------ | .................... . . . . 1 . . . . | +-- 24 | - - - - - - - - - - - - - 0 - -------1------------ | .................... . . . . . . . 1 . | +-- 25 | - - - - - - - 0 0 - - - - 0 0 ------1------------- | .................... . . . 1 . . . . . | +-- 26 | - - - - - - - - - - - - - 0 0 ------1------------- | .................... . . . . . 1 . . . | +-- 27 | - - - - - - - - - - - - - - 1 ------1------------- | .................... . . . . 1 . . . . | +-- 28 | - - - - - - - - - - - - - 1 - ------1------------- | .................... . . . . 1 . . . . | +-- 29 | - - - - - - - - 1 - - - - - - ------1------------- | .................... . . . . 1 . . . . | +-- 30 | - - - - - 0 - - - 0 - - - - - -----1-------------- | ..........1......... . . . . . . . . . | +-- 31 | - - - - - 1 - - - 0 - - - - - -----1-------------- | ......1............. . . . . . . . . . | +-- 32 | - - - - - 0 - - - 1 - - - - - -----1-------------- | ................1... . . . . . . . . . | +-- 33 | - - - - - 1 - - - 1 - - - - - -----1-------------- | ............1....... . . . . . . . . . | +-- 34 | - - - - - - - - - - - - - 0 0 ---1---------------- | .................... . . 1 . . . . . . | +-- 35 | - - - - - 0 - - - - - - - - - ---1---------------- | ........1........... . . . . . . . . . | +-- 36 | - - - - - 1 - - - - - - - - - ---1---------------- | ....1............... . . . . . . . . . | +-- 37 | - - - 0 - - - - - - - 0 0 - - --1----------------- | ..1................. . . . . . . . . . | +-- 38 | - - - - - - - - - - - - 1 - - --1----------------- | 1................... . . . . . . . . . | +-- 39 | - - - 1 - - - - - - - - - - - --1----------------- | 1................... . . . . . . . . . | +-- 40 | - - - 0 - 0 - - - - - - - - - -1------------------ | .1.................. . . . . . . . . . | +-- 41 | - - - 0 0 1 - - - - - - - - - -1------------------ | ...1................ . . . . . . . . . | +-- 42 | - - - 0 1 1 - - - - - - - - - -1------------------ | .......1............ . . . . . . . . . | +-- 43 | - - - 1 - - - - - - - - - - - -1------------------ | 1................... 1 . . . . . . . 1 | +-- 44 | 1 1 0 - - - - - - - 1 0 0 - - 1------------------- | ..1................. . . . . . . . . . | +-- 45 | - - 0 - - - - - - - 1 - 1 - - 1------------------- | 1................... . . . . . . . . . | +-- 46 | 1 1 - - - - - - - - 0 0 - - - 1------------------- | .1.................. . 1 . . . . . . . | +-- 47 | 1 1 1 - - - - - - - - 0 - - - 1------------------- | .1.................. . 1 . . . . . . . | +-- 48 | - 0 - - - - - - - - - - - - - 1------------------- | 1................... . . . . . . . . . | +-- 49 | 0 - - - - - - - - - - - - - - 1------------------- | 1................... . . . . . . . . . | +-- *======================================================================================================================* +-- +-- Table IU2_SM_1 Signal Assignments for Product Terms +MQQ79:IU2_SM_1_PT(1) <= + Eq(( ICS_ICM_IU2_FLUSH_TID(1) & MISS_TID1_SM_L2(1) & + MISS_TID1_SM_L2(3) & MISS_TID1_SM_L2(4) & + MISS_TID1_SM_L2(5) & MISS_TID1_SM_L2(6) & + MISS_TID1_SM_L2(7) & MISS_TID1_SM_L2(8) & + MISS_TID1_SM_L2(9) & MISS_TID1_SM_L2(10) & + MISS_TID1_SM_L2(11) & MISS_TID1_SM_L2(12) & + MISS_TID1_SM_L2(13) & MISS_TID1_SM_L2(14) & + MISS_TID1_SM_L2(15) & MISS_TID1_SM_L2(16) & + MISS_TID1_SM_L2(17) & MISS_TID1_SM_L2(18) & + MISS_TID1_SM_L2(19) ) , STD_ULOGIC_VECTOR'("1000000000000000000")); +MQQ80:IU2_SM_1_PT(2) <= + Eq(( MISS_TID1_SM_L2(0) & MISS_TID1_SM_L2(1) & + MISS_TID1_SM_L2(2) & MISS_TID1_SM_L2(3) & + MISS_TID1_SM_L2(4) & MISS_TID1_SM_L2(5) & + MISS_TID1_SM_L2(8) & MISS_TID1_SM_L2(9) & + MISS_TID1_SM_L2(10) & MISS_TID1_SM_L2(11) & + MISS_TID1_SM_L2(12) & MISS_TID1_SM_L2(13) & + MISS_TID1_SM_L2(14) & MISS_TID1_SM_L2(15) & + MISS_TID1_SM_L2(16) & MISS_TID1_SM_L2(17) & + MISS_TID1_SM_L2(18) & MISS_TID1_SM_L2(19) + ) , STD_ULOGIC_VECTOR'("000000000000000000")); +MQQ81:IU2_SM_1_PT(3) <= + Eq(( RELD_R1_TID_L2(1) & MISS_TID1_SM_L2(0) & + MISS_TID1_SM_L2(1) & MISS_TID1_SM_L2(2) & + MISS_TID1_SM_L2(3) & MISS_TID1_SM_L2(5) & + MISS_TID1_SM_L2(6) & MISS_TID1_SM_L2(7) & + MISS_TID1_SM_L2(8) & MISS_TID1_SM_L2(10) & + MISS_TID1_SM_L2(11) & MISS_TID1_SM_L2(12) & + MISS_TID1_SM_L2(13) & MISS_TID1_SM_L2(14) & + MISS_TID1_SM_L2(15) & MISS_TID1_SM_L2(16) & + MISS_TID1_SM_L2(17) & MISS_TID1_SM_L2(18) & + MISS_TID1_SM_L2(19) ) , STD_ULOGIC_VECTOR'("0000000000000000000")); +MQQ82:IU2_SM_1_PT(4) <= + Eq(( RELD_R1_TID_L2(1) & MISS_TID1_SM_L2(0) & + MISS_TID1_SM_L2(1) & MISS_TID1_SM_L2(2) & + MISS_TID1_SM_L2(3) & MISS_TID1_SM_L2(5) & + MISS_TID1_SM_L2(7) & MISS_TID1_SM_L2(8) & + MISS_TID1_SM_L2(10) & MISS_TID1_SM_L2(11) & + MISS_TID1_SM_L2(12) & MISS_TID1_SM_L2(13) & + MISS_TID1_SM_L2(14) & MISS_TID1_SM_L2(15) & + MISS_TID1_SM_L2(16) & MISS_TID1_SM_L2(17) & + MISS_TID1_SM_L2(18) & MISS_TID1_SM_L2(19) + ) , STD_ULOGIC_VECTOR'("100000000000000000")); +MQQ83:IU2_SM_1_PT(5) <= + Eq(( MISS_FLUSHED1_L2 & MISS_INVAL1_L2 & + MISS_TID1_SM_L2(0) & MISS_TID1_SM_L2(1) & + MISS_TID1_SM_L2(2) & MISS_TID1_SM_L2(6) & + MISS_TID1_SM_L2(7) & MISS_TID1_SM_L2(8) & + MISS_TID1_SM_L2(9) & MISS_TID1_SM_L2(10) & + MISS_TID1_SM_L2(11) & MISS_TID1_SM_L2(16) & + MISS_TID1_SM_L2(17) & MISS_TID1_SM_L2(18) & + MISS_TID1_SM_L2(19) ) , STD_ULOGIC_VECTOR'("000000000000000")); +MQQ84:IU2_SM_1_PT(6) <= + Eq(( R2_CRIT_QW_L2 & MISS_FLUSHED1_L2 & + MISS_TID1_SM_L2(0) & MISS_TID1_SM_L2(1) & + MISS_TID1_SM_L2(2) & MISS_TID1_SM_L2(8) & + MISS_TID1_SM_L2(9) & MISS_TID1_SM_L2(10) & + MISS_TID1_SM_L2(11) & MISS_TID1_SM_L2(16) & + MISS_TID1_SM_L2(17) & MISS_TID1_SM_L2(18) & + MISS_TID1_SM_L2(19) ) , STD_ULOGIC_VECTOR'("1000000000000")); +MQQ85:IU2_SM_1_PT(7) <= + Eq(( RELD_R1_TID_L2(1) & MISS_TID1_SM_L2(0) & + MISS_TID1_SM_L2(1) & MISS_TID1_SM_L2(2) & + MISS_TID1_SM_L2(3) & MISS_TID1_SM_L2(4) & + MISS_TID1_SM_L2(5) & MISS_TID1_SM_L2(6) & + MISS_TID1_SM_L2(7) & MISS_TID1_SM_L2(8) & + MISS_TID1_SM_L2(9) & MISS_TID1_SM_L2(10) & + MISS_TID1_SM_L2(11) & MISS_TID1_SM_L2(13) & + MISS_TID1_SM_L2(14) & MISS_TID1_SM_L2(15) & + MISS_TID1_SM_L2(16) & MISS_TID1_SM_L2(18) & + MISS_TID1_SM_L2(19) ) , STD_ULOGIC_VECTOR'("0000000000000000000")); +MQQ86:IU2_SM_1_PT(8) <= + Eq(( RELD_R1_TID_L2(1) & MISS_TID1_SM_L2(0) & + MISS_TID1_SM_L2(1) & MISS_TID1_SM_L2(2) & + MISS_TID1_SM_L2(3) & MISS_TID1_SM_L2(4) & + MISS_TID1_SM_L2(5) & MISS_TID1_SM_L2(7) & + MISS_TID1_SM_L2(8) & MISS_TID1_SM_L2(9) & + MISS_TID1_SM_L2(10) & MISS_TID1_SM_L2(11) & + MISS_TID1_SM_L2(13) & MISS_TID1_SM_L2(14) & + MISS_TID1_SM_L2(15) & MISS_TID1_SM_L2(16) & + MISS_TID1_SM_L2(18) & MISS_TID1_SM_L2(19) + ) , STD_ULOGIC_VECTOR'("100000000000000000")); +MQQ87:IU2_SM_1_PT(9) <= + Eq(( RELD_R1_TID_L2(1) & MISS_TID1_SM_L2(0) & + MISS_TID1_SM_L2(1) & MISS_TID1_SM_L2(2) & + MISS_TID1_SM_L2(3) & MISS_TID1_SM_L2(4) & + MISS_TID1_SM_L2(5) & MISS_TID1_SM_L2(6) & + MISS_TID1_SM_L2(7) & MISS_TID1_SM_L2(8) & + MISS_TID1_SM_L2(9) & MISS_TID1_SM_L2(10) & + MISS_TID1_SM_L2(11) & MISS_TID1_SM_L2(12) & + MISS_TID1_SM_L2(13) & MISS_TID1_SM_L2(15) & + MISS_TID1_SM_L2(16) & MISS_TID1_SM_L2(17) & + MISS_TID1_SM_L2(18) ) , STD_ULOGIC_VECTOR'("0000000000000000000")); +MQQ88:IU2_SM_1_PT(10) <= + Eq(( RELD_R1_TID_L2(1) & MISS_TID1_SM_L2(0) & + MISS_TID1_SM_L2(1) & MISS_TID1_SM_L2(2) & + MISS_TID1_SM_L2(3) & MISS_TID1_SM_L2(4) & + MISS_TID1_SM_L2(5) & MISS_TID1_SM_L2(7) & + MISS_TID1_SM_L2(8) & MISS_TID1_SM_L2(9) & + MISS_TID1_SM_L2(10) & MISS_TID1_SM_L2(11) & + MISS_TID1_SM_L2(12) & MISS_TID1_SM_L2(13) & + MISS_TID1_SM_L2(15) & MISS_TID1_SM_L2(16) & + MISS_TID1_SM_L2(17) & MISS_TID1_SM_L2(18) + ) , STD_ULOGIC_VECTOR'("100000000000000000")); +MQQ89:IU2_SM_1_PT(11) <= + Eq(( MISS_TID1_SM_L2(18) ) , STD_ULOGIC'('1')); +MQQ90:IU2_SM_1_PT(12) <= + Eq(( MISS_TID1_SM_L2(16) ) , STD_ULOGIC'('1')); +MQQ91:IU2_SM_1_PT(13) <= + Eq(( RELD_R1_TID_L2(1) & MISS_TID1_SM_L2(15) + ) , STD_ULOGIC_VECTOR'("01")); +MQQ92:IU2_SM_1_PT(14) <= + Eq(( RELD_R1_TID_L2(1) & MISS_TID1_SM_L2(15) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ93:IU2_SM_1_PT(15) <= + Eq(( RELD_R1_TID_L2(1) & MISS_TID1_SM_L2(13) + ) , STD_ULOGIC_VECTOR'("01")); +MQQ94:IU2_SM_1_PT(16) <= + Eq(( RELD_R1_TID_L2(1) & MISS_TID1_SM_L2(13) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ95:IU2_SM_1_PT(17) <= + Eq(( MISS_TID1_SM_L2(0) & MISS_TID1_SM_L2(1) & + MISS_TID1_SM_L2(2) & MISS_TID1_SM_L2(6) & + MISS_TID1_SM_L2(7) & MISS_TID1_SM_L2(11) + ) , STD_ULOGIC_VECTOR'("000000")); +MQQ96:IU2_SM_1_PT(18) <= + Eq(( ERAT_ERR(1) & MISS_TID1_SM_L2(0) & + MISS_TID1_SM_L2(6) & MISS_TID1_SM_L2(7) & + MISS_TID1_SM_L2(11) ) , STD_ULOGIC_VECTOR'("00000")); +MQQ97:IU2_SM_1_PT(19) <= + Eq(( ECC_ERR(1) & MISS_TID1_SM_L2(11) + ) , STD_ULOGIC_VECTOR'("01")); +MQQ98:IU2_SM_1_PT(20) <= + Eq(( ECC_ERR(1) & MISS_TID1_SM_L2(11) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ99:IU2_SM_1_PT(21) <= + Eq(( MISS_TID1_SM_L2(10) ) , STD_ULOGIC'('1')); +MQQ100:IU2_SM_1_PT(22) <= + Eq(( MISS_TID1_SM_L2(8) ) , STD_ULOGIC'('1')); +MQQ101:IU2_SM_1_PT(23) <= + Eq(( ECC_ERR(1) & MISS_TID1_SM_L2(0) & + MISS_TID1_SM_L2(1) & MISS_TID1_SM_L2(2) & + MISS_TID1_SM_L2(7) ) , STD_ULOGIC_VECTOR'("10000")); +MQQ102:IU2_SM_1_PT(24) <= + Eq(( MISS_FLUSHED1_L2 & MISS_TID1_SM_L2(7) + ) , STD_ULOGIC_VECTOR'("01")); +MQQ103:IU2_SM_1_PT(25) <= + Eq(( ECC_ERR(1) & ECC_ERR_UE(1) & + MISS_FLUSHED1_L2 & MISS_INVAL1_L2 & + MISS_TID1_SM_L2(6) ) , STD_ULOGIC_VECTOR'("00001")); +MQQ104:IU2_SM_1_PT(26) <= + Eq(( MISS_FLUSHED1_L2 & MISS_INVAL1_L2 & + MISS_TID1_SM_L2(6) ) , STD_ULOGIC_VECTOR'("001")); +MQQ105:IU2_SM_1_PT(27) <= + Eq(( MISS_INVAL1_L2 & MISS_TID1_SM_L2(6) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ106:IU2_SM_1_PT(28) <= + Eq(( MISS_FLUSHED1_L2 & MISS_TID1_SM_L2(6) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ107:IU2_SM_1_PT(29) <= + Eq(( ECC_ERR_UE(1) & MISS_TID1_SM_L2(6) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ108:IU2_SM_1_PT(30) <= + Eq(( RELD_R1_TID_L2(1) & SPR_IC_CLS_L2 & + MISS_TID1_SM_L2(5) ) , STD_ULOGIC_VECTOR'("001")); +MQQ109:IU2_SM_1_PT(31) <= + Eq(( RELD_R1_TID_L2(1) & SPR_IC_CLS_L2 & + MISS_TID1_SM_L2(5) ) , STD_ULOGIC_VECTOR'("101")); +MQQ110:IU2_SM_1_PT(32) <= + Eq(( RELD_R1_TID_L2(1) & SPR_IC_CLS_L2 & + MISS_TID1_SM_L2(5) ) , STD_ULOGIC_VECTOR'("011")); +MQQ111:IU2_SM_1_PT(33) <= + Eq(( RELD_R1_TID_L2(1) & SPR_IC_CLS_L2 & + MISS_TID1_SM_L2(5) ) , STD_ULOGIC_VECTOR'("111")); +MQQ112:IU2_SM_1_PT(34) <= + Eq(( MISS_FLUSHED1_L2 & MISS_INVAL1_L2 & + MISS_TID1_SM_L2(3) ) , STD_ULOGIC_VECTOR'("001")); +MQQ113:IU2_SM_1_PT(35) <= + Eq(( RELD_R1_TID_L2(1) & MISS_TID1_SM_L2(3) + ) , STD_ULOGIC_VECTOR'("01")); +MQQ114:IU2_SM_1_PT(36) <= + Eq(( RELD_R1_TID_L2(1) & MISS_TID1_SM_L2(3) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ115:IU2_SM_1_PT(37) <= + Eq(( ERAT_ERR(1) & ICS_ICM_IU2_FLUSH_TID(1) & + RELEASE_SM & MISS_TID1_SM_L2(2) + ) , STD_ULOGIC_VECTOR'("0001")); +MQQ116:IU2_SM_1_PT(38) <= + Eq(( RELEASE_SM & MISS_TID1_SM_L2(2) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ117:IU2_SM_1_PT(39) <= + Eq(( ERAT_ERR(1) & MISS_TID1_SM_L2(2) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ118:IU2_SM_1_PT(40) <= + Eq(( ERAT_ERR(1) & RELD_R1_TID_L2(1) & + MISS_TID1_SM_L2(1) ) , STD_ULOGIC_VECTOR'("001")); +MQQ119:IU2_SM_1_PT(41) <= + Eq(( ERAT_ERR(1) & MISS_CI1_L2 & + RELD_R1_TID_L2(1) & MISS_TID1_SM_L2(1) + ) , STD_ULOGIC_VECTOR'("0011")); +MQQ120:IU2_SM_1_PT(42) <= + Eq(( ERAT_ERR(1) & MISS_CI1_L2 & + RELD_R1_TID_L2(1) & MISS_TID1_SM_L2(1) + ) , STD_ULOGIC_VECTOR'("0111")); +MQQ121:IU2_SM_1_PT(43) <= + Eq(( ERAT_ERR(1) & MISS_TID1_SM_L2(1) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ122:IU2_SM_1_PT(44) <= + Eq(( ICD_ICM_MISS & ICD_ICM_TID(1) & + ICD_ICM_WIMGE(1) & ADDR_MATCH & + ICS_ICM_IU2_FLUSH_TID(1) & RELEASE_SM & + MISS_TID1_SM_L2(0) ) , STD_ULOGIC_VECTOR'("1101001")); +MQQ123:IU2_SM_1_PT(45) <= + Eq(( ICD_ICM_WIMGE(1) & ADDR_MATCH & + RELEASE_SM & MISS_TID1_SM_L2(0) + ) , STD_ULOGIC_VECTOR'("0111")); +MQQ124:IU2_SM_1_PT(46) <= + Eq(( ICD_ICM_MISS & ICD_ICM_TID(1) & + ADDR_MATCH & ICS_ICM_IU2_FLUSH_TID(1) & + MISS_TID1_SM_L2(0) ) , STD_ULOGIC_VECTOR'("11001")); +MQQ125:IU2_SM_1_PT(47) <= + Eq(( ICD_ICM_MISS & ICD_ICM_TID(1) & + ICD_ICM_WIMGE(1) & ICS_ICM_IU2_FLUSH_TID(1) & + MISS_TID1_SM_L2(0) ) , STD_ULOGIC_VECTOR'("11101")); +MQQ126:IU2_SM_1_PT(48) <= + Eq(( ICD_ICM_TID(1) & MISS_TID1_SM_L2(0) + ) , STD_ULOGIC_VECTOR'("01")); +MQQ127:IU2_SM_1_PT(49) <= + Eq(( ICD_ICM_MISS & MISS_TID1_SM_L2(0) + ) , STD_ULOGIC_VECTOR'("01")); +-- Table IU2_SM_1 Signal Assignments for Outputs +MQQ128:MISS_TID1_SM_D(0) <= + (IU2_SM_1_PT(1) OR IU2_SM_1_PT(19) + OR IU2_SM_1_PT(38) OR IU2_SM_1_PT(39) + OR IU2_SM_1_PT(43) OR IU2_SM_1_PT(45) + OR IU2_SM_1_PT(48) OR IU2_SM_1_PT(49) + ); +MQQ129:MISS_TID1_SM_D(1) <= + (IU2_SM_1_PT(20) OR IU2_SM_1_PT(40) + OR IU2_SM_1_PT(46) OR IU2_SM_1_PT(47) + ); +MQQ130:MISS_TID1_SM_D(2) <= + (IU2_SM_1_PT(37) OR IU2_SM_1_PT(44) + ); +MQQ131:MISS_TID1_SM_D(3) <= + (IU2_SM_1_PT(41)); +MQQ132:MISS_TID1_SM_D(4) <= + (IU2_SM_1_PT(22) OR IU2_SM_1_PT(36) + ); +MQQ133:MISS_TID1_SM_D(5) <= + (IU2_SM_1_PT(4)); +MQQ134:MISS_TID1_SM_D(6) <= + (IU2_SM_1_PT(14) OR IU2_SM_1_PT(21) + OR IU2_SM_1_PT(31)); +MQQ135:MISS_TID1_SM_D(7) <= + (IU2_SM_1_PT(42)); +MQQ136:MISS_TID1_SM_D(8) <= + (IU2_SM_1_PT(35)); +MQQ137:MISS_TID1_SM_D(9) <= + (IU2_SM_1_PT(3)); +MQQ138:MISS_TID1_SM_D(10) <= + (IU2_SM_1_PT(13) OR IU2_SM_1_PT(30) + ); +MQQ139:MISS_TID1_SM_D(11) <= + (IU2_SM_1_PT(2)); +MQQ140:MISS_TID1_SM_D(12) <= + (IU2_SM_1_PT(12) OR IU2_SM_1_PT(33) + ); +MQQ141:MISS_TID1_SM_D(13) <= + (IU2_SM_1_PT(8)); +MQQ142:MISS_TID1_SM_D(14) <= + (IU2_SM_1_PT(11) OR IU2_SM_1_PT(16) + ); +MQQ143:MISS_TID1_SM_D(15) <= + (IU2_SM_1_PT(10)); +MQQ144:MISS_TID1_SM_D(16) <= + (IU2_SM_1_PT(32)); +MQQ145:MISS_TID1_SM_D(17) <= + (IU2_SM_1_PT(7)); +MQQ146:MISS_TID1_SM_D(18) <= + (IU2_SM_1_PT(15)); +MQQ147:MISS_TID1_SM_D(19) <= + (IU2_SM_1_PT(9)); +MQQ148:RESET_STATE(1) <= + (IU2_SM_1_PT(19) OR IU2_SM_1_PT(43) + ); +MQQ149:REQUEST_TID(1) <= + (IU2_SM_1_PT(46) OR IU2_SM_1_PT(47) + ); +MQQ150:WRITE_DIR_INVAL(1) <= + (IU2_SM_1_PT(34)); +MQQ151:WRITE_DIR_VAL(1) <= + (IU2_SM_1_PT(25)); +MQQ152:HOLD_TID(1) <= + (IU2_SM_1_PT(17) OR IU2_SM_1_PT(18) + OR IU2_SM_1_PT(23) OR IU2_SM_1_PT(27) + OR IU2_SM_1_PT(28) OR IU2_SM_1_PT(29) + ); +MQQ153:DATA_WRITE(1) <= + (IU2_SM_1_PT(5) OR IU2_SM_1_PT(26) + ); +MQQ154:DIR_WRITE(1) <= + (IU2_SM_1_PT(5)); +MQQ155:LOAD_TID(1) <= + (IU2_SM_1_PT(6) OR IU2_SM_1_PT(24) + ); +MQQ156:RELEASE_SM_HOLD(1) <= + (IU2_SM_1_PT(2) OR IU2_SM_1_PT(19) + OR IU2_SM_1_PT(43)); + +-- +-- Final Table Listing +-- *INPUTS*================================================*OUTPUTS*======================================================* +-- | | | +-- | icd_icm_miss | miss_tid2_sm_d | +-- | | icd_icm_tid(2) | | | +-- | | | icd_icm_wimge(1) | | reset_state(2) | -- WIMGE(1): Cache Inhibit +-- | | | | erat_err(2) | | | | +-- | | | | | miss_ci2_l2 | | | request_tid(2) | +-- | | | | | | reld_r1_tid_l2(2) | | | | write_dir_inval(2) | +-- | | | | | | | r2_crit_qw_l2 | | | | | write_dir_val(2) | +-- | | | | | | | | ecc_err(2) | | | | | | | +-- | | | | | | | | | ecc_err_ue(2) | | | | | | | +-- | | | | | | | | | | | | | | | | | +-- | | | | | | | | | | spr_ic_cls_l2 | | | | | | | +-- | | | | | | | | | | | addr_match | | | | | | | +-- | | | | | | | | | | | | ics_icm_iu2_flush_tid(2) | | | | | | hold_tid(2) | -- this hold 1 tid and gates iu2 +-- | | | | | | | | | | | | | release_sm | | | | | | | | +-- | | | | | | | | | | | | | | miss_flushed2_l2 | | | | | | | | +-- | | | | | | | | | | | | | | | miss_inval2_l2 | | | | | | | | +-- | | | | | | | | | | | | | | | | miss_tid2_sm_l2 | | | | | | | | +-- | | | | | | | | | | | | | | | | | | | | | | | | | +-- | | | | | | | | | | | | | | | | | | | | | | | | data_write(2) | +-- | | | | | | | | | | | | | | | | | | | | | | | | | dir_write(2) | +-- | | | | | | | | | | | | | | | | | | | | | | | | | | | +-- | | | | | | | | | | | | | | | | | | | | | | | | | | load_tid(2) | +-- | | | | | | | | | | | | | | | | | | | | | | | | | | | | +-- | | | | | | | | | | | | | | | | | | | | | | | | | | | release_sm_hold(2)| +-- | | | | | | | | | | | | | | | | | | | | | | | | | | | | | +-- | | | | | | | | | | | | | | | | | | | | | | | | | | | | | +-- | | | | | | | | | | | | | | | | | 1111111111 | | 1111111111 | | | | | | | | | | +-- | | | | | | | | | | | | | | | | 01234567890123456789 | 01234567890123456789 | | | | | | | | | | +-- *TYPE*==================================================+==============================================================+ +-- | P P P P P P P P P P P P P P P PPPPPPPPPPPPPPPPPPPP | PPPPPPPPPPPPPPPPPPPP P P P P P P P P P | +-- *POLARITY*--------------------------------------------->| ++++++++++++++++++++ + + + + + + + + + | +-- *PHASE*------------------------------------------------>| TTTTTTTTTTTTTTTTTTTT T T T T T T T T T | +-- *OPTIMIZE*--------------------------------------------->| AAAAAAAAAAAAAAAAAAAA A A A A B A A A A | +-- *TERMS*=================================================+==============================================================+ +-- 1 | - - - - - - - - - - - 1 - - - -0-00000000000000000 | 1................... . . . . . . . . . | +-- 2 | - - - - - - - - - - - - - - - 000000--000000000000 | ...........1........ . . . . . . . . 1 | +-- 3 | - - - - - 0 - - - - - - - - - 0000-0000-0000000000 | .........1.......... . . . . . . . . . | +-- 4 | - - - - - 1 - - - - - - - - - 0000-0-00-0000000000 | .....1.............. . . . . . . . . . | +-- 5 | - - - - - - - - - - - - - 0 0 000---000000----0000 | .................... . . . . . 1 1 . . | +-- 6 | - - - - - - 1 - - - - - - 0 - 000-----0000----0000 | .................... . . . . . . . 1 . | +-- 7 | - - - - - 0 - - - - - - - - - 000000000000-0000-00 | .................1.. . . . . . . . . . | +-- 8 | - - - - - 1 - - - - - - - - - 000000-00000-0000-00 | .............1...... . . . . . . . . . | +-- 9 | - - - - - 0 - - - - - - - - - 00000000000000-0000- | ...................1 . . . . . . . . . | +-- 10 | - - - - - 1 - - - - - - - - - 000000-0000000-0000- | ...............1.... . . . . . . . . . | +-- 11 | - - - - - - - - - - - - - - - ------------------1- | ..............1..... . . . . . . . . . | +-- 12 | - - - - - - - - - - - - - - - ----------------1--- | ............1....... . . . . . . . . . | +-- 13 | - - - - - 0 - - - - - - - - - ---------------1---- | ..........1......... . . . . . . . . . | +-- 14 | - - - - - 1 - - - - - - - - - ---------------1---- | ......1............. . . . . . . . . . | +-- 15 | - - - - - 0 - - - - - - - - - -------------1------ | ..................1. . . . . . . . . . | +-- 16 | - - - - - 1 - - - - - - - - - -------------1------ | ..............1..... . . . . . . . . . | +-- 17 | - - - - - - - - - - - - - - - 000---00---0-------- | .................... . . . . 1 . . . . | +-- 18 | - - - 0 - - - - - - - - - - - 0-----00---0-------- | .................... . . . . 1 . . . . | +-- 19 | - - - - - - - 0 - - - - - - - -----------1-------- | 1................... 1 . . . . . . . 1 | +-- 20 | - - - - - - - 1 - - - - - - - -----------1-------- | .1.................. . . . . . . . . . | +-- 21 | - - - - - - - - - - - - - - - ----------1--------- | ......1............. . . . . . . . . . | +-- 22 | - - - - - - - - - - - - - - - --------1----------- | ....1............... . . . . . . . . . | +-- 23 | - - - - - - - 1 - - - - - - - 000----0------------ | .................... . . . . 1 . . . . | +-- 24 | - - - - - - - - - - - - - 0 - -------1------------ | .................... . . . . . . . 1 . | +-- 25 | - - - - - - - 0 0 - - - - 0 0 ------1------------- | .................... . . . 1 . . . . . | +-- 26 | - - - - - - - - - - - - - 0 0 ------1------------- | .................... . . . . . 1 . . . | +-- 27 | - - - - - - - - - - - - - - 1 ------1------------- | .................... . . . . 1 . . . . | +-- 28 | - - - - - - - - - - - - - 1 - ------1------------- | .................... . . . . 1 . . . . | +-- 29 | - - - - - - - - 1 - - - - - - ------1------------- | .................... . . . . 1 . . . . | +-- 30 | - - - - - 0 - - - 0 - - - - - -----1-------------- | ..........1......... . . . . . . . . . | +-- 31 | - - - - - 1 - - - 0 - - - - - -----1-------------- | ......1............. . . . . . . . . . | +-- 32 | - - - - - 0 - - - 1 - - - - - -----1-------------- | ................1... . . . . . . . . . | +-- 33 | - - - - - 1 - - - 1 - - - - - -----1-------------- | ............1....... . . . . . . . . . | +-- 34 | - - - - - - - - - - - - - 0 0 ---1---------------- | .................... . . 1 . . . . . . | +-- 35 | - - - - - 0 - - - - - - - - - ---1---------------- | ........1........... . . . . . . . . . | +-- 36 | - - - - - 1 - - - - - - - - - ---1---------------- | ....1............... . . . . . . . . . | +-- 37 | - - - 0 - - - - - - - 0 0 - - --1----------------- | ..1................. . . . . . . . . . | +-- 38 | - - - - - - - - - - - - 1 - - --1----------------- | 1................... . . . . . . . . . | +-- 39 | - - - 1 - - - - - - - - - - - --1----------------- | 1................... . . . . . . . . . | +-- 40 | - - - 0 - 0 - - - - - - - - - -1------------------ | .1.................. . . . . . . . . . | +-- 41 | - - - 0 0 1 - - - - - - - - - -1------------------ | ...1................ . . . . . . . . . | +-- 42 | - - - 0 1 1 - - - - - - - - - -1------------------ | .......1............ . . . . . . . . . | +-- 43 | - - - 1 - - - - - - - - - - - -1------------------ | 1................... 1 . . . . . . . 1 | +-- 44 | 1 1 0 - - - - - - - 1 0 0 - - 1------------------- | ..1................. . . . . . . . . . | +-- 45 | - - 0 - - - - - - - 1 - 1 - - 1------------------- | 1................... . . . . . . . . . | +-- 46 | 1 1 - - - - - - - - 0 0 - - - 1------------------- | .1.................. . 1 . . . . . . . | +-- 47 | 1 1 1 - - - - - - - - 0 - - - 1------------------- | .1.................. . 1 . . . . . . . | +-- 48 | - 0 - - - - - - - - - - - - - 1------------------- | 1................... . . . . . . . . . | +-- 49 | 0 - - - - - - - - - - - - - - 1------------------- | 1................... . . . . . . . . . | +-- *======================================================================================================================* +-- +-- Table IU2_SM_2 Signal Assignments for Product Terms +MQQ157:IU2_SM_2_PT(1) <= + Eq(( ICS_ICM_IU2_FLUSH_TID(2) & MISS_TID2_SM_L2(1) & + MISS_TID2_SM_L2(3) & MISS_TID2_SM_L2(4) & + MISS_TID2_SM_L2(5) & MISS_TID2_SM_L2(6) & + MISS_TID2_SM_L2(7) & MISS_TID2_SM_L2(8) & + MISS_TID2_SM_L2(9) & MISS_TID2_SM_L2(10) & + MISS_TID2_SM_L2(11) & MISS_TID2_SM_L2(12) & + MISS_TID2_SM_L2(13) & MISS_TID2_SM_L2(14) & + MISS_TID2_SM_L2(15) & MISS_TID2_SM_L2(16) & + MISS_TID2_SM_L2(17) & MISS_TID2_SM_L2(18) & + MISS_TID2_SM_L2(19) ) , STD_ULOGIC_VECTOR'("1000000000000000000")); +MQQ158:IU2_SM_2_PT(2) <= + Eq(( MISS_TID2_SM_L2(0) & MISS_TID2_SM_L2(1) & + MISS_TID2_SM_L2(2) & MISS_TID2_SM_L2(3) & + MISS_TID2_SM_L2(4) & MISS_TID2_SM_L2(5) & + MISS_TID2_SM_L2(8) & MISS_TID2_SM_L2(9) & + MISS_TID2_SM_L2(10) & MISS_TID2_SM_L2(11) & + MISS_TID2_SM_L2(12) & MISS_TID2_SM_L2(13) & + MISS_TID2_SM_L2(14) & MISS_TID2_SM_L2(15) & + MISS_TID2_SM_L2(16) & MISS_TID2_SM_L2(17) & + MISS_TID2_SM_L2(18) & MISS_TID2_SM_L2(19) + ) , STD_ULOGIC_VECTOR'("000000000000000000")); +MQQ159:IU2_SM_2_PT(3) <= + Eq(( RELD_R1_TID_L2(2) & MISS_TID2_SM_L2(0) & + MISS_TID2_SM_L2(1) & MISS_TID2_SM_L2(2) & + MISS_TID2_SM_L2(3) & MISS_TID2_SM_L2(5) & + MISS_TID2_SM_L2(6) & MISS_TID2_SM_L2(7) & + MISS_TID2_SM_L2(8) & MISS_TID2_SM_L2(10) & + MISS_TID2_SM_L2(11) & MISS_TID2_SM_L2(12) & + MISS_TID2_SM_L2(13) & MISS_TID2_SM_L2(14) & + MISS_TID2_SM_L2(15) & MISS_TID2_SM_L2(16) & + MISS_TID2_SM_L2(17) & MISS_TID2_SM_L2(18) & + MISS_TID2_SM_L2(19) ) , STD_ULOGIC_VECTOR'("0000000000000000000")); +MQQ160:IU2_SM_2_PT(4) <= + Eq(( RELD_R1_TID_L2(2) & MISS_TID2_SM_L2(0) & + MISS_TID2_SM_L2(1) & MISS_TID2_SM_L2(2) & + MISS_TID2_SM_L2(3) & MISS_TID2_SM_L2(5) & + MISS_TID2_SM_L2(7) & MISS_TID2_SM_L2(8) & + MISS_TID2_SM_L2(10) & MISS_TID2_SM_L2(11) & + MISS_TID2_SM_L2(12) & MISS_TID2_SM_L2(13) & + MISS_TID2_SM_L2(14) & MISS_TID2_SM_L2(15) & + MISS_TID2_SM_L2(16) & MISS_TID2_SM_L2(17) & + MISS_TID2_SM_L2(18) & MISS_TID2_SM_L2(19) + ) , STD_ULOGIC_VECTOR'("100000000000000000")); +MQQ161:IU2_SM_2_PT(5) <= + Eq(( MISS_FLUSHED2_L2 & MISS_INVAL2_L2 & + MISS_TID2_SM_L2(0) & MISS_TID2_SM_L2(1) & + MISS_TID2_SM_L2(2) & MISS_TID2_SM_L2(6) & + MISS_TID2_SM_L2(7) & MISS_TID2_SM_L2(8) & + MISS_TID2_SM_L2(9) & MISS_TID2_SM_L2(10) & + MISS_TID2_SM_L2(11) & MISS_TID2_SM_L2(16) & + MISS_TID2_SM_L2(17) & MISS_TID2_SM_L2(18) & + MISS_TID2_SM_L2(19) ) , STD_ULOGIC_VECTOR'("000000000000000")); +MQQ162:IU2_SM_2_PT(6) <= + Eq(( R2_CRIT_QW_L2 & MISS_FLUSHED2_L2 & + MISS_TID2_SM_L2(0) & MISS_TID2_SM_L2(1) & + MISS_TID2_SM_L2(2) & MISS_TID2_SM_L2(8) & + MISS_TID2_SM_L2(9) & MISS_TID2_SM_L2(10) & + MISS_TID2_SM_L2(11) & MISS_TID2_SM_L2(16) & + MISS_TID2_SM_L2(17) & MISS_TID2_SM_L2(18) & + MISS_TID2_SM_L2(19) ) , STD_ULOGIC_VECTOR'("1000000000000")); +MQQ163:IU2_SM_2_PT(7) <= + Eq(( RELD_R1_TID_L2(2) & MISS_TID2_SM_L2(0) & + MISS_TID2_SM_L2(1) & MISS_TID2_SM_L2(2) & + MISS_TID2_SM_L2(3) & MISS_TID2_SM_L2(4) & + MISS_TID2_SM_L2(5) & MISS_TID2_SM_L2(6) & + MISS_TID2_SM_L2(7) & MISS_TID2_SM_L2(8) & + MISS_TID2_SM_L2(9) & MISS_TID2_SM_L2(10) & + MISS_TID2_SM_L2(11) & MISS_TID2_SM_L2(13) & + MISS_TID2_SM_L2(14) & MISS_TID2_SM_L2(15) & + MISS_TID2_SM_L2(16) & MISS_TID2_SM_L2(18) & + MISS_TID2_SM_L2(19) ) , STD_ULOGIC_VECTOR'("0000000000000000000")); +MQQ164:IU2_SM_2_PT(8) <= + Eq(( RELD_R1_TID_L2(2) & MISS_TID2_SM_L2(0) & + MISS_TID2_SM_L2(1) & MISS_TID2_SM_L2(2) & + MISS_TID2_SM_L2(3) & MISS_TID2_SM_L2(4) & + MISS_TID2_SM_L2(5) & MISS_TID2_SM_L2(7) & + MISS_TID2_SM_L2(8) & MISS_TID2_SM_L2(9) & + MISS_TID2_SM_L2(10) & MISS_TID2_SM_L2(11) & + MISS_TID2_SM_L2(13) & MISS_TID2_SM_L2(14) & + MISS_TID2_SM_L2(15) & MISS_TID2_SM_L2(16) & + MISS_TID2_SM_L2(18) & MISS_TID2_SM_L2(19) + ) , STD_ULOGIC_VECTOR'("100000000000000000")); +MQQ165:IU2_SM_2_PT(9) <= + Eq(( RELD_R1_TID_L2(2) & MISS_TID2_SM_L2(0) & + MISS_TID2_SM_L2(1) & MISS_TID2_SM_L2(2) & + MISS_TID2_SM_L2(3) & MISS_TID2_SM_L2(4) & + MISS_TID2_SM_L2(5) & MISS_TID2_SM_L2(6) & + MISS_TID2_SM_L2(7) & MISS_TID2_SM_L2(8) & + MISS_TID2_SM_L2(9) & MISS_TID2_SM_L2(10) & + MISS_TID2_SM_L2(11) & MISS_TID2_SM_L2(12) & + MISS_TID2_SM_L2(13) & MISS_TID2_SM_L2(15) & + MISS_TID2_SM_L2(16) & MISS_TID2_SM_L2(17) & + MISS_TID2_SM_L2(18) ) , STD_ULOGIC_VECTOR'("0000000000000000000")); +MQQ166:IU2_SM_2_PT(10) <= + Eq(( RELD_R1_TID_L2(2) & MISS_TID2_SM_L2(0) & + MISS_TID2_SM_L2(1) & MISS_TID2_SM_L2(2) & + MISS_TID2_SM_L2(3) & MISS_TID2_SM_L2(4) & + MISS_TID2_SM_L2(5) & MISS_TID2_SM_L2(7) & + MISS_TID2_SM_L2(8) & MISS_TID2_SM_L2(9) & + MISS_TID2_SM_L2(10) & MISS_TID2_SM_L2(11) & + MISS_TID2_SM_L2(12) & MISS_TID2_SM_L2(13) & + MISS_TID2_SM_L2(15) & MISS_TID2_SM_L2(16) & + MISS_TID2_SM_L2(17) & MISS_TID2_SM_L2(18) + ) , STD_ULOGIC_VECTOR'("100000000000000000")); +MQQ167:IU2_SM_2_PT(11) <= + Eq(( MISS_TID2_SM_L2(18) ) , STD_ULOGIC'('1')); +MQQ168:IU2_SM_2_PT(12) <= + Eq(( MISS_TID2_SM_L2(16) ) , STD_ULOGIC'('1')); +MQQ169:IU2_SM_2_PT(13) <= + Eq(( RELD_R1_TID_L2(2) & MISS_TID2_SM_L2(15) + ) , STD_ULOGIC_VECTOR'("01")); +MQQ170:IU2_SM_2_PT(14) <= + Eq(( RELD_R1_TID_L2(2) & MISS_TID2_SM_L2(15) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ171:IU2_SM_2_PT(15) <= + Eq(( RELD_R1_TID_L2(2) & MISS_TID2_SM_L2(13) + ) , STD_ULOGIC_VECTOR'("01")); +MQQ172:IU2_SM_2_PT(16) <= + Eq(( RELD_R1_TID_L2(2) & MISS_TID2_SM_L2(13) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ173:IU2_SM_2_PT(17) <= + Eq(( MISS_TID2_SM_L2(0) & MISS_TID2_SM_L2(1) & + MISS_TID2_SM_L2(2) & MISS_TID2_SM_L2(6) & + MISS_TID2_SM_L2(7) & MISS_TID2_SM_L2(11) + ) , STD_ULOGIC_VECTOR'("000000")); +MQQ174:IU2_SM_2_PT(18) <= + Eq(( ERAT_ERR(2) & MISS_TID2_SM_L2(0) & + MISS_TID2_SM_L2(6) & MISS_TID2_SM_L2(7) & + MISS_TID2_SM_L2(11) ) , STD_ULOGIC_VECTOR'("00000")); +MQQ175:IU2_SM_2_PT(19) <= + Eq(( ECC_ERR(2) & MISS_TID2_SM_L2(11) + ) , STD_ULOGIC_VECTOR'("01")); +MQQ176:IU2_SM_2_PT(20) <= + Eq(( ECC_ERR(2) & MISS_TID2_SM_L2(11) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ177:IU2_SM_2_PT(21) <= + Eq(( MISS_TID2_SM_L2(10) ) , STD_ULOGIC'('1')); +MQQ178:IU2_SM_2_PT(22) <= + Eq(( MISS_TID2_SM_L2(8) ) , STD_ULOGIC'('1')); +MQQ179:IU2_SM_2_PT(23) <= + Eq(( ECC_ERR(2) & MISS_TID2_SM_L2(0) & + MISS_TID2_SM_L2(1) & MISS_TID2_SM_L2(2) & + MISS_TID2_SM_L2(7) ) , STD_ULOGIC_VECTOR'("10000")); +MQQ180:IU2_SM_2_PT(24) <= + Eq(( MISS_FLUSHED2_L2 & MISS_TID2_SM_L2(7) + ) , STD_ULOGIC_VECTOR'("01")); +MQQ181:IU2_SM_2_PT(25) <= + Eq(( ECC_ERR(2) & ECC_ERR_UE(2) & + MISS_FLUSHED2_L2 & MISS_INVAL2_L2 & + MISS_TID2_SM_L2(6) ) , STD_ULOGIC_VECTOR'("00001")); +MQQ182:IU2_SM_2_PT(26) <= + Eq(( MISS_FLUSHED2_L2 & MISS_INVAL2_L2 & + MISS_TID2_SM_L2(6) ) , STD_ULOGIC_VECTOR'("001")); +MQQ183:IU2_SM_2_PT(27) <= + Eq(( MISS_INVAL2_L2 & MISS_TID2_SM_L2(6) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ184:IU2_SM_2_PT(28) <= + Eq(( MISS_FLUSHED2_L2 & MISS_TID2_SM_L2(6) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ185:IU2_SM_2_PT(29) <= + Eq(( ECC_ERR_UE(2) & MISS_TID2_SM_L2(6) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ186:IU2_SM_2_PT(30) <= + Eq(( RELD_R1_TID_L2(2) & SPR_IC_CLS_L2 & + MISS_TID2_SM_L2(5) ) , STD_ULOGIC_VECTOR'("001")); +MQQ187:IU2_SM_2_PT(31) <= + Eq(( RELD_R1_TID_L2(2) & SPR_IC_CLS_L2 & + MISS_TID2_SM_L2(5) ) , STD_ULOGIC_VECTOR'("101")); +MQQ188:IU2_SM_2_PT(32) <= + Eq(( RELD_R1_TID_L2(2) & SPR_IC_CLS_L2 & + MISS_TID2_SM_L2(5) ) , STD_ULOGIC_VECTOR'("011")); +MQQ189:IU2_SM_2_PT(33) <= + Eq(( RELD_R1_TID_L2(2) & SPR_IC_CLS_L2 & + MISS_TID2_SM_L2(5) ) , STD_ULOGIC_VECTOR'("111")); +MQQ190:IU2_SM_2_PT(34) <= + Eq(( MISS_FLUSHED2_L2 & MISS_INVAL2_L2 & + MISS_TID2_SM_L2(3) ) , STD_ULOGIC_VECTOR'("001")); +MQQ191:IU2_SM_2_PT(35) <= + Eq(( RELD_R1_TID_L2(2) & MISS_TID2_SM_L2(3) + ) , STD_ULOGIC_VECTOR'("01")); +MQQ192:IU2_SM_2_PT(36) <= + Eq(( RELD_R1_TID_L2(2) & MISS_TID2_SM_L2(3) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ193:IU2_SM_2_PT(37) <= + Eq(( ERAT_ERR(2) & ICS_ICM_IU2_FLUSH_TID(2) & + RELEASE_SM & MISS_TID2_SM_L2(2) + ) , STD_ULOGIC_VECTOR'("0001")); +MQQ194:IU2_SM_2_PT(38) <= + Eq(( RELEASE_SM & MISS_TID2_SM_L2(2) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ195:IU2_SM_2_PT(39) <= + Eq(( ERAT_ERR(2) & MISS_TID2_SM_L2(2) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ196:IU2_SM_2_PT(40) <= + Eq(( ERAT_ERR(2) & RELD_R1_TID_L2(2) & + MISS_TID2_SM_L2(1) ) , STD_ULOGIC_VECTOR'("001")); +MQQ197:IU2_SM_2_PT(41) <= + Eq(( ERAT_ERR(2) & MISS_CI2_L2 & + RELD_R1_TID_L2(2) & MISS_TID2_SM_L2(1) + ) , STD_ULOGIC_VECTOR'("0011")); +MQQ198:IU2_SM_2_PT(42) <= + Eq(( ERAT_ERR(2) & MISS_CI2_L2 & + RELD_R1_TID_L2(2) & MISS_TID2_SM_L2(1) + ) , STD_ULOGIC_VECTOR'("0111")); +MQQ199:IU2_SM_2_PT(43) <= + Eq(( ERAT_ERR(2) & MISS_TID2_SM_L2(1) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ200:IU2_SM_2_PT(44) <= + Eq(( ICD_ICM_MISS & ICD_ICM_TID(2) & + ICD_ICM_WIMGE(1) & ADDR_MATCH & + ICS_ICM_IU2_FLUSH_TID(2) & RELEASE_SM & + MISS_TID2_SM_L2(0) ) , STD_ULOGIC_VECTOR'("1101001")); +MQQ201:IU2_SM_2_PT(45) <= + Eq(( ICD_ICM_WIMGE(1) & ADDR_MATCH & + RELEASE_SM & MISS_TID2_SM_L2(0) + ) , STD_ULOGIC_VECTOR'("0111")); +MQQ202:IU2_SM_2_PT(46) <= + Eq(( ICD_ICM_MISS & ICD_ICM_TID(2) & + ADDR_MATCH & ICS_ICM_IU2_FLUSH_TID(2) & + MISS_TID2_SM_L2(0) ) , STD_ULOGIC_VECTOR'("11001")); +MQQ203:IU2_SM_2_PT(47) <= + Eq(( ICD_ICM_MISS & ICD_ICM_TID(2) & + ICD_ICM_WIMGE(1) & ICS_ICM_IU2_FLUSH_TID(2) & + MISS_TID2_SM_L2(0) ) , STD_ULOGIC_VECTOR'("11101")); +MQQ204:IU2_SM_2_PT(48) <= + Eq(( ICD_ICM_TID(2) & MISS_TID2_SM_L2(0) + ) , STD_ULOGIC_VECTOR'("01")); +MQQ205:IU2_SM_2_PT(49) <= + Eq(( ICD_ICM_MISS & MISS_TID2_SM_L2(0) + ) , STD_ULOGIC_VECTOR'("01")); +-- Table IU2_SM_2 Signal Assignments for Outputs +MQQ206:MISS_TID2_SM_D(0) <= + (IU2_SM_2_PT(1) OR IU2_SM_2_PT(19) + OR IU2_SM_2_PT(38) OR IU2_SM_2_PT(39) + OR IU2_SM_2_PT(43) OR IU2_SM_2_PT(45) + OR IU2_SM_2_PT(48) OR IU2_SM_2_PT(49) + ); +MQQ207:MISS_TID2_SM_D(1) <= + (IU2_SM_2_PT(20) OR IU2_SM_2_PT(40) + OR IU2_SM_2_PT(46) OR IU2_SM_2_PT(47) + ); +MQQ208:MISS_TID2_SM_D(2) <= + (IU2_SM_2_PT(37) OR IU2_SM_2_PT(44) + ); +MQQ209:MISS_TID2_SM_D(3) <= + (IU2_SM_2_PT(41)); +MQQ210:MISS_TID2_SM_D(4) <= + (IU2_SM_2_PT(22) OR IU2_SM_2_PT(36) + ); +MQQ211:MISS_TID2_SM_D(5) <= + (IU2_SM_2_PT(4)); +MQQ212:MISS_TID2_SM_D(6) <= + (IU2_SM_2_PT(14) OR IU2_SM_2_PT(21) + OR IU2_SM_2_PT(31)); +MQQ213:MISS_TID2_SM_D(7) <= + (IU2_SM_2_PT(42)); +MQQ214:MISS_TID2_SM_D(8) <= + (IU2_SM_2_PT(35)); +MQQ215:MISS_TID2_SM_D(9) <= + (IU2_SM_2_PT(3)); +MQQ216:MISS_TID2_SM_D(10) <= + (IU2_SM_2_PT(13) OR IU2_SM_2_PT(30) + ); +MQQ217:MISS_TID2_SM_D(11) <= + (IU2_SM_2_PT(2)); +MQQ218:MISS_TID2_SM_D(12) <= + (IU2_SM_2_PT(12) OR IU2_SM_2_PT(33) + ); +MQQ219:MISS_TID2_SM_D(13) <= + (IU2_SM_2_PT(8)); +MQQ220:MISS_TID2_SM_D(14) <= + (IU2_SM_2_PT(11) OR IU2_SM_2_PT(16) + ); +MQQ221:MISS_TID2_SM_D(15) <= + (IU2_SM_2_PT(10)); +MQQ222:MISS_TID2_SM_D(16) <= + (IU2_SM_2_PT(32)); +MQQ223:MISS_TID2_SM_D(17) <= + (IU2_SM_2_PT(7)); +MQQ224:MISS_TID2_SM_D(18) <= + (IU2_SM_2_PT(15)); +MQQ225:MISS_TID2_SM_D(19) <= + (IU2_SM_2_PT(9)); +MQQ226:RESET_STATE(2) <= + (IU2_SM_2_PT(19) OR IU2_SM_2_PT(43) + ); +MQQ227:REQUEST_TID(2) <= + (IU2_SM_2_PT(46) OR IU2_SM_2_PT(47) + ); +MQQ228:WRITE_DIR_INVAL(2) <= + (IU2_SM_2_PT(34)); +MQQ229:WRITE_DIR_VAL(2) <= + (IU2_SM_2_PT(25)); +MQQ230:HOLD_TID(2) <= + (IU2_SM_2_PT(17) OR IU2_SM_2_PT(18) + OR IU2_SM_2_PT(23) OR IU2_SM_2_PT(27) + OR IU2_SM_2_PT(28) OR IU2_SM_2_PT(29) + ); +MQQ231:DATA_WRITE(2) <= + (IU2_SM_2_PT(5) OR IU2_SM_2_PT(26) + ); +MQQ232:DIR_WRITE(2) <= + (IU2_SM_2_PT(5)); +MQQ233:LOAD_TID(2) <= + (IU2_SM_2_PT(6) OR IU2_SM_2_PT(24) + ); +MQQ234:RELEASE_SM_HOLD(2) <= + (IU2_SM_2_PT(2) OR IU2_SM_2_PT(19) + OR IU2_SM_2_PT(43)); + +-- +-- Final Table Listing +-- *INPUTS*================================================*OUTPUTS*======================================================* +-- | | | +-- | icd_icm_miss | miss_tid3_sm_d | +-- | | icd_icm_tid(3) | | | +-- | | | icd_icm_wimge(1) | | reset_state(3) | -- WIMGE(1): Cache Inhibit +-- | | | | erat_err(3) | | | | +-- | | | | | miss_ci3_l2 | | | request_tid(3) | +-- | | | | | | reld_r1_tid_l2(3) | | | | write_dir_inval(3) | +-- | | | | | | | r2_crit_qw_l2 | | | | | write_dir_val(3) | +-- | | | | | | | | ecc_err(3) | | | | | | | +-- | | | | | | | | | ecc_err_ue(3) | | | | | | | +-- | | | | | | | | | | | | | | | | | +-- | | | | | | | | | | spr_ic_cls_l2 | | | | | | | +-- | | | | | | | | | | | addr_match | | | | | | | +-- | | | | | | | | | | | | ics_icm_iu2_flush_tid(3) | | | | | | hold_tid(3) | -- this hold 1 tid and gates iu2 +-- | | | | | | | | | | | | | release_sm | | | | | | | | +-- | | | | | | | | | | | | | | miss_flushed3_l2 | | | | | | | | +-- | | | | | | | | | | | | | | | miss_inval3_l2 | | | | | | | | +-- | | | | | | | | | | | | | | | | miss_tid3_sm_l2 | | | | | | | | +-- | | | | | | | | | | | | | | | | | | | | | | | | | +-- | | | | | | | | | | | | | | | | | | | | | | | | data_write(3) | +-- | | | | | | | | | | | | | | | | | | | | | | | | | dir_write(3) | +-- | | | | | | | | | | | | | | | | | | | | | | | | | | | +-- | | | | | | | | | | | | | | | | | | | | | | | | | | load_tid(3) | +-- | | | | | | | | | | | | | | | | | | | | | | | | | | | | +-- | | | | | | | | | | | | | | | | | | | | | | | | | | | release_sm_hold(3)| +-- | | | | | | | | | | | | | | | | | | | | | | | | | | | | | +-- | | | | | | | | | | | | | | | | | | | | | | | | | | | | | +-- | | | | | | | | | | | | | | | | | 1111111111 | | 1111111111 | | | | | | | | | | +-- | | | | | | | | | | | | | | | | 01234567890123456789 | 01234567890123456789 | | | | | | | | | | +-- *TYPE*==================================================+==============================================================+ +-- | P P P P P P P P P P P P P P P PPPPPPPPPPPPPPPPPPPP | PPPPPPPPPPPPPPPPPPPP P P P P P P P P P | +-- *POLARITY*--------------------------------------------->| ++++++++++++++++++++ + + + + + + + + + | +-- *PHASE*------------------------------------------------>| TTTTTTTTTTTTTTTTTTTT T T T T T T T T T | +-- *OPTIMIZE*--------------------------------------------->| AAAAAAAAAAAAAAAAAAAA A A A A B A A A A | +-- *TERMS*=================================================+==============================================================+ +-- 1 | - - - - - - - - - - - 1 - - - -0-00000000000000000 | 1................... . . . . . . . . . | +-- 2 | - - - - - - - - - - - - - - - 000000--000000000000 | ...........1........ . . . . . . . . 1 | +-- 3 | - - - - - 0 - - - - - - - - - 0000-0000-0000000000 | .........1.......... . . . . . . . . . | +-- 4 | - - - - - 1 - - - - - - - - - 0000-0-00-0000000000 | .....1.............. . . . . . . . . . | +-- 5 | - - - - - - - - - - - - - 0 0 000---000000----0000 | .................... . . . . . 1 1 . . | +-- 6 | - - - - - - 1 - - - - - - 0 - 000-----0000----0000 | .................... . . . . . . . 1 . | +-- 7 | - - - - - 0 - - - - - - - - - 000000000000-0000-00 | .................1.. . . . . . . . . . | +-- 8 | - - - - - 1 - - - - - - - - - 000000-00000-0000-00 | .............1...... . . . . . . . . . | +-- 9 | - - - - - 0 - - - - - - - - - 00000000000000-0000- | ...................1 . . . . . . . . . | +-- 10 | - - - - - 1 - - - - - - - - - 000000-0000000-0000- | ...............1.... . . . . . . . . . | +-- 11 | - - - - - - - - - - - - - - - ------------------1- | ..............1..... . . . . . . . . . | +-- 12 | - - - - - - - - - - - - - - - ----------------1--- | ............1....... . . . . . . . . . | +-- 13 | - - - - - 0 - - - - - - - - - ---------------1---- | ..........1......... . . . . . . . . . | +-- 14 | - - - - - 1 - - - - - - - - - ---------------1---- | ......1............. . . . . . . . . . | +-- 15 | - - - - - 0 - - - - - - - - - -------------1------ | ..................1. . . . . . . . . . | +-- 16 | - - - - - 1 - - - - - - - - - -------------1------ | ..............1..... . . . . . . . . . | +-- 17 | - - - - - - - - - - - - - - - 000---00---0-------- | .................... . . . . 1 . . . . | +-- 18 | - - - 0 - - - - - - - - - - - 0-----00---0-------- | .................... . . . . 1 . . . . | +-- 19 | - - - - - - - 0 - - - - - - - -----------1-------- | 1................... 1 . . . . . . . 1 | +-- 20 | - - - - - - - 1 - - - - - - - -----------1-------- | .1.................. . . . . . . . . . | +-- 21 | - - - - - - - - - - - - - - - ----------1--------- | ......1............. . . . . . . . . . | +-- 22 | - - - - - - - - - - - - - - - --------1----------- | ....1............... . . . . . . . . . | +-- 23 | - - - - - - - 1 - - - - - - - 000----0------------ | .................... . . . . 1 . . . . | +-- 24 | - - - - - - - - - - - - - 0 - -------1------------ | .................... . . . . . . . 1 . | +-- 25 | - - - - - - - 0 0 - - - - 0 0 ------1------------- | .................... . . . 1 . . . . . | +-- 26 | - - - - - - - - - - - - - 0 0 ------1------------- | .................... . . . . . 1 . . . | +-- 27 | - - - - - - - - - - - - - - 1 ------1------------- | .................... . . . . 1 . . . . | +-- 28 | - - - - - - - - - - - - - 1 - ------1------------- | .................... . . . . 1 . . . . | +-- 29 | - - - - - - - - 1 - - - - - - ------1------------- | .................... . . . . 1 . . . . | +-- 30 | - - - - - 0 - - - 0 - - - - - -----1-------------- | ..........1......... . . . . . . . . . | +-- 31 | - - - - - 1 - - - 0 - - - - - -----1-------------- | ......1............. . . . . . . . . . | +-- 32 | - - - - - 0 - - - 1 - - - - - -----1-------------- | ................1... . . . . . . . . . | +-- 33 | - - - - - 1 - - - 1 - - - - - -----1-------------- | ............1....... . . . . . . . . . | +-- 34 | - - - - - - - - - - - - - 0 0 ---1---------------- | .................... . . 1 . . . . . . | +-- 35 | - - - - - 0 - - - - - - - - - ---1---------------- | ........1........... . . . . . . . . . | +-- 36 | - - - - - 1 - - - - - - - - - ---1---------------- | ....1............... . . . . . . . . . | +-- 37 | - - - 0 - - - - - - - 0 0 - - --1----------------- | ..1................. . . . . . . . . . | +-- 38 | - - - - - - - - - - - - 1 - - --1----------------- | 1................... . . . . . . . . . | +-- 39 | - - - 1 - - - - - - - - - - - --1----------------- | 1................... . . . . . . . . . | +-- 40 | - - - 0 - 0 - - - - - - - - - -1------------------ | .1.................. . . . . . . . . . | +-- 41 | - - - 0 0 1 - - - - - - - - - -1------------------ | ...1................ . . . . . . . . . | +-- 42 | - - - 0 1 1 - - - - - - - - - -1------------------ | .......1............ . . . . . . . . . | +-- 43 | - - - 1 - - - - - - - - - - - -1------------------ | 1................... 1 . . . . . . . 1 | +-- 44 | 1 1 0 - - - - - - - 1 0 0 - - 1------------------- | ..1................. . . . . . . . . . | +-- 45 | - - 0 - - - - - - - 1 - 1 - - 1------------------- | 1................... . . . . . . . . . | +-- 46 | 1 1 - - - - - - - - 0 0 - - - 1------------------- | .1.................. . 1 . . . . . . . | +-- 47 | 1 1 1 - - - - - - - - 0 - - - 1------------------- | .1.................. . 1 . . . . . . . | +-- 48 | - 0 - - - - - - - - - - - - - 1------------------- | 1................... . . . . . . . . . | +-- 49 | 0 - - - - - - - - - - - - - - 1------------------- | 1................... . . . . . . . . . | +-- *======================================================================================================================* +-- +-- Table IU2_SM_3 Signal Assignments for Product Terms +MQQ235:IU2_SM_3_PT(1) <= + Eq(( ICS_ICM_IU2_FLUSH_TID(3) & MISS_TID3_SM_L2(1) & + MISS_TID3_SM_L2(3) & MISS_TID3_SM_L2(4) & + MISS_TID3_SM_L2(5) & MISS_TID3_SM_L2(6) & + MISS_TID3_SM_L2(7) & MISS_TID3_SM_L2(8) & + MISS_TID3_SM_L2(9) & MISS_TID3_SM_L2(10) & + MISS_TID3_SM_L2(11) & MISS_TID3_SM_L2(12) & + MISS_TID3_SM_L2(13) & MISS_TID3_SM_L2(14) & + MISS_TID3_SM_L2(15) & MISS_TID3_SM_L2(16) & + MISS_TID3_SM_L2(17) & MISS_TID3_SM_L2(18) & + MISS_TID3_SM_L2(19) ) , STD_ULOGIC_VECTOR'("1000000000000000000")); +MQQ236:IU2_SM_3_PT(2) <= + Eq(( MISS_TID3_SM_L2(0) & MISS_TID3_SM_L2(1) & + MISS_TID3_SM_L2(2) & MISS_TID3_SM_L2(3) & + MISS_TID3_SM_L2(4) & MISS_TID3_SM_L2(5) & + MISS_TID3_SM_L2(8) & MISS_TID3_SM_L2(9) & + MISS_TID3_SM_L2(10) & MISS_TID3_SM_L2(11) & + MISS_TID3_SM_L2(12) & MISS_TID3_SM_L2(13) & + MISS_TID3_SM_L2(14) & MISS_TID3_SM_L2(15) & + MISS_TID3_SM_L2(16) & MISS_TID3_SM_L2(17) & + MISS_TID3_SM_L2(18) & MISS_TID3_SM_L2(19) + ) , STD_ULOGIC_VECTOR'("000000000000000000")); +MQQ237:IU2_SM_3_PT(3) <= + Eq(( RELD_R1_TID_L2(3) & MISS_TID3_SM_L2(0) & + MISS_TID3_SM_L2(1) & MISS_TID3_SM_L2(2) & + MISS_TID3_SM_L2(3) & MISS_TID3_SM_L2(5) & + MISS_TID3_SM_L2(6) & MISS_TID3_SM_L2(7) & + MISS_TID3_SM_L2(8) & MISS_TID3_SM_L2(10) & + MISS_TID3_SM_L2(11) & MISS_TID3_SM_L2(12) & + MISS_TID3_SM_L2(13) & MISS_TID3_SM_L2(14) & + MISS_TID3_SM_L2(15) & MISS_TID3_SM_L2(16) & + MISS_TID3_SM_L2(17) & MISS_TID3_SM_L2(18) & + MISS_TID3_SM_L2(19) ) , STD_ULOGIC_VECTOR'("0000000000000000000")); +MQQ238:IU2_SM_3_PT(4) <= + Eq(( RELD_R1_TID_L2(3) & MISS_TID3_SM_L2(0) & + MISS_TID3_SM_L2(1) & MISS_TID3_SM_L2(2) & + MISS_TID3_SM_L2(3) & MISS_TID3_SM_L2(5) & + MISS_TID3_SM_L2(7) & MISS_TID3_SM_L2(8) & + MISS_TID3_SM_L2(10) & MISS_TID3_SM_L2(11) & + MISS_TID3_SM_L2(12) & MISS_TID3_SM_L2(13) & + MISS_TID3_SM_L2(14) & MISS_TID3_SM_L2(15) & + MISS_TID3_SM_L2(16) & MISS_TID3_SM_L2(17) & + MISS_TID3_SM_L2(18) & MISS_TID3_SM_L2(19) + ) , STD_ULOGIC_VECTOR'("100000000000000000")); +MQQ239:IU2_SM_3_PT(5) <= + Eq(( MISS_FLUSHED3_L2 & MISS_INVAL3_L2 & + MISS_TID3_SM_L2(0) & MISS_TID3_SM_L2(1) & + MISS_TID3_SM_L2(2) & MISS_TID3_SM_L2(6) & + MISS_TID3_SM_L2(7) & MISS_TID3_SM_L2(8) & + MISS_TID3_SM_L2(9) & MISS_TID3_SM_L2(10) & + MISS_TID3_SM_L2(11) & MISS_TID3_SM_L2(16) & + MISS_TID3_SM_L2(17) & MISS_TID3_SM_L2(18) & + MISS_TID3_SM_L2(19) ) , STD_ULOGIC_VECTOR'("000000000000000")); +MQQ240:IU2_SM_3_PT(6) <= + Eq(( R2_CRIT_QW_L2 & MISS_FLUSHED3_L2 & + MISS_TID3_SM_L2(0) & MISS_TID3_SM_L2(1) & + MISS_TID3_SM_L2(2) & MISS_TID3_SM_L2(8) & + MISS_TID3_SM_L2(9) & MISS_TID3_SM_L2(10) & + MISS_TID3_SM_L2(11) & MISS_TID3_SM_L2(16) & + MISS_TID3_SM_L2(17) & MISS_TID3_SM_L2(18) & + MISS_TID3_SM_L2(19) ) , STD_ULOGIC_VECTOR'("1000000000000")); +MQQ241:IU2_SM_3_PT(7) <= + Eq(( RELD_R1_TID_L2(3) & MISS_TID3_SM_L2(0) & + MISS_TID3_SM_L2(1) & MISS_TID3_SM_L2(2) & + MISS_TID3_SM_L2(3) & MISS_TID3_SM_L2(4) & + MISS_TID3_SM_L2(5) & MISS_TID3_SM_L2(6) & + MISS_TID3_SM_L2(7) & MISS_TID3_SM_L2(8) & + MISS_TID3_SM_L2(9) & MISS_TID3_SM_L2(10) & + MISS_TID3_SM_L2(11) & MISS_TID3_SM_L2(13) & + MISS_TID3_SM_L2(14) & MISS_TID3_SM_L2(15) & + MISS_TID3_SM_L2(16) & MISS_TID3_SM_L2(18) & + MISS_TID3_SM_L2(19) ) , STD_ULOGIC_VECTOR'("0000000000000000000")); +MQQ242:IU2_SM_3_PT(8) <= + Eq(( RELD_R1_TID_L2(3) & MISS_TID3_SM_L2(0) & + MISS_TID3_SM_L2(1) & MISS_TID3_SM_L2(2) & + MISS_TID3_SM_L2(3) & MISS_TID3_SM_L2(4) & + MISS_TID3_SM_L2(5) & MISS_TID3_SM_L2(7) & + MISS_TID3_SM_L2(8) & MISS_TID3_SM_L2(9) & + MISS_TID3_SM_L2(10) & MISS_TID3_SM_L2(11) & + MISS_TID3_SM_L2(13) & MISS_TID3_SM_L2(14) & + MISS_TID3_SM_L2(15) & MISS_TID3_SM_L2(16) & + MISS_TID3_SM_L2(18) & MISS_TID3_SM_L2(19) + ) , STD_ULOGIC_VECTOR'("100000000000000000")); +MQQ243:IU2_SM_3_PT(9) <= + Eq(( RELD_R1_TID_L2(3) & MISS_TID3_SM_L2(0) & + MISS_TID3_SM_L2(1) & MISS_TID3_SM_L2(2) & + MISS_TID3_SM_L2(3) & MISS_TID3_SM_L2(4) & + MISS_TID3_SM_L2(5) & MISS_TID3_SM_L2(6) & + MISS_TID3_SM_L2(7) & MISS_TID3_SM_L2(8) & + MISS_TID3_SM_L2(9) & MISS_TID3_SM_L2(10) & + MISS_TID3_SM_L2(11) & MISS_TID3_SM_L2(12) & + MISS_TID3_SM_L2(13) & MISS_TID3_SM_L2(15) & + MISS_TID3_SM_L2(16) & MISS_TID3_SM_L2(17) & + MISS_TID3_SM_L2(18) ) , STD_ULOGIC_VECTOR'("0000000000000000000")); +MQQ244:IU2_SM_3_PT(10) <= + Eq(( RELD_R1_TID_L2(3) & MISS_TID3_SM_L2(0) & + MISS_TID3_SM_L2(1) & MISS_TID3_SM_L2(2) & + MISS_TID3_SM_L2(3) & MISS_TID3_SM_L2(4) & + MISS_TID3_SM_L2(5) & MISS_TID3_SM_L2(7) & + MISS_TID3_SM_L2(8) & MISS_TID3_SM_L2(9) & + MISS_TID3_SM_L2(10) & MISS_TID3_SM_L2(11) & + MISS_TID3_SM_L2(12) & MISS_TID3_SM_L2(13) & + MISS_TID3_SM_L2(15) & MISS_TID3_SM_L2(16) & + MISS_TID3_SM_L2(17) & MISS_TID3_SM_L2(18) + ) , STD_ULOGIC_VECTOR'("100000000000000000")); +MQQ245:IU2_SM_3_PT(11) <= + Eq(( MISS_TID3_SM_L2(18) ) , STD_ULOGIC'('1')); +MQQ246:IU2_SM_3_PT(12) <= + Eq(( MISS_TID3_SM_L2(16) ) , STD_ULOGIC'('1')); +MQQ247:IU2_SM_3_PT(13) <= + Eq(( RELD_R1_TID_L2(3) & MISS_TID3_SM_L2(15) + ) , STD_ULOGIC_VECTOR'("01")); +MQQ248:IU2_SM_3_PT(14) <= + Eq(( RELD_R1_TID_L2(3) & MISS_TID3_SM_L2(15) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ249:IU2_SM_3_PT(15) <= + Eq(( RELD_R1_TID_L2(3) & MISS_TID3_SM_L2(13) + ) , STD_ULOGIC_VECTOR'("01")); +MQQ250:IU2_SM_3_PT(16) <= + Eq(( RELD_R1_TID_L2(3) & MISS_TID3_SM_L2(13) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ251:IU2_SM_3_PT(17) <= + Eq(( MISS_TID3_SM_L2(0) & MISS_TID3_SM_L2(1) & + MISS_TID3_SM_L2(2) & MISS_TID3_SM_L2(6) & + MISS_TID3_SM_L2(7) & MISS_TID3_SM_L2(11) + ) , STD_ULOGIC_VECTOR'("000000")); +MQQ252:IU2_SM_3_PT(18) <= + Eq(( ERAT_ERR(3) & MISS_TID3_SM_L2(0) & + MISS_TID3_SM_L2(6) & MISS_TID3_SM_L2(7) & + MISS_TID3_SM_L2(11) ) , STD_ULOGIC_VECTOR'("00000")); +MQQ253:IU2_SM_3_PT(19) <= + Eq(( ECC_ERR(3) & MISS_TID3_SM_L2(11) + ) , STD_ULOGIC_VECTOR'("01")); +MQQ254:IU2_SM_3_PT(20) <= + Eq(( ECC_ERR(3) & MISS_TID3_SM_L2(11) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ255:IU2_SM_3_PT(21) <= + Eq(( MISS_TID3_SM_L2(10) ) , STD_ULOGIC'('1')); +MQQ256:IU2_SM_3_PT(22) <= + Eq(( MISS_TID3_SM_L2(8) ) , STD_ULOGIC'('1')); +MQQ257:IU2_SM_3_PT(23) <= + Eq(( ECC_ERR(3) & MISS_TID3_SM_L2(0) & + MISS_TID3_SM_L2(1) & MISS_TID3_SM_L2(2) & + MISS_TID3_SM_L2(7) ) , STD_ULOGIC_VECTOR'("10000")); +MQQ258:IU2_SM_3_PT(24) <= + Eq(( MISS_FLUSHED3_L2 & MISS_TID3_SM_L2(7) + ) , STD_ULOGIC_VECTOR'("01")); +MQQ259:IU2_SM_3_PT(25) <= + Eq(( ECC_ERR(3) & ECC_ERR_UE(3) & + MISS_FLUSHED3_L2 & MISS_INVAL3_L2 & + MISS_TID3_SM_L2(6) ) , STD_ULOGIC_VECTOR'("00001")); +MQQ260:IU2_SM_3_PT(26) <= + Eq(( MISS_FLUSHED3_L2 & MISS_INVAL3_L2 & + MISS_TID3_SM_L2(6) ) , STD_ULOGIC_VECTOR'("001")); +MQQ261:IU2_SM_3_PT(27) <= + Eq(( MISS_INVAL3_L2 & MISS_TID3_SM_L2(6) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ262:IU2_SM_3_PT(28) <= + Eq(( MISS_FLUSHED3_L2 & MISS_TID3_SM_L2(6) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ263:IU2_SM_3_PT(29) <= + Eq(( ECC_ERR_UE(3) & MISS_TID3_SM_L2(6) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ264:IU2_SM_3_PT(30) <= + Eq(( RELD_R1_TID_L2(3) & SPR_IC_CLS_L2 & + MISS_TID3_SM_L2(5) ) , STD_ULOGIC_VECTOR'("001")); +MQQ265:IU2_SM_3_PT(31) <= + Eq(( RELD_R1_TID_L2(3) & SPR_IC_CLS_L2 & + MISS_TID3_SM_L2(5) ) , STD_ULOGIC_VECTOR'("101")); +MQQ266:IU2_SM_3_PT(32) <= + Eq(( RELD_R1_TID_L2(3) & SPR_IC_CLS_L2 & + MISS_TID3_SM_L2(5) ) , STD_ULOGIC_VECTOR'("011")); +MQQ267:IU2_SM_3_PT(33) <= + Eq(( RELD_R1_TID_L2(3) & SPR_IC_CLS_L2 & + MISS_TID3_SM_L2(5) ) , STD_ULOGIC_VECTOR'("111")); +MQQ268:IU2_SM_3_PT(34) <= + Eq(( MISS_FLUSHED3_L2 & MISS_INVAL3_L2 & + MISS_TID3_SM_L2(3) ) , STD_ULOGIC_VECTOR'("001")); +MQQ269:IU2_SM_3_PT(35) <= + Eq(( RELD_R1_TID_L2(3) & MISS_TID3_SM_L2(3) + ) , STD_ULOGIC_VECTOR'("01")); +MQQ270:IU2_SM_3_PT(36) <= + Eq(( RELD_R1_TID_L2(3) & MISS_TID3_SM_L2(3) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ271:IU2_SM_3_PT(37) <= + Eq(( ERAT_ERR(3) & ICS_ICM_IU2_FLUSH_TID(3) & + RELEASE_SM & MISS_TID3_SM_L2(2) + ) , STD_ULOGIC_VECTOR'("0001")); +MQQ272:IU2_SM_3_PT(38) <= + Eq(( RELEASE_SM & MISS_TID3_SM_L2(2) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ273:IU2_SM_3_PT(39) <= + Eq(( ERAT_ERR(3) & MISS_TID3_SM_L2(2) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ274:IU2_SM_3_PT(40) <= + Eq(( ERAT_ERR(3) & RELD_R1_TID_L2(3) & + MISS_TID3_SM_L2(1) ) , STD_ULOGIC_VECTOR'("001")); +MQQ275:IU2_SM_3_PT(41) <= + Eq(( ERAT_ERR(3) & MISS_CI3_L2 & + RELD_R1_TID_L2(3) & MISS_TID3_SM_L2(1) + ) , STD_ULOGIC_VECTOR'("0011")); +MQQ276:IU2_SM_3_PT(42) <= + Eq(( ERAT_ERR(3) & MISS_CI3_L2 & + RELD_R1_TID_L2(3) & MISS_TID3_SM_L2(1) + ) , STD_ULOGIC_VECTOR'("0111")); +MQQ277:IU2_SM_3_PT(43) <= + Eq(( ERAT_ERR(3) & MISS_TID3_SM_L2(1) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ278:IU2_SM_3_PT(44) <= + Eq(( ICD_ICM_MISS & ICD_ICM_TID(3) & + ICD_ICM_WIMGE(1) & ADDR_MATCH & + ICS_ICM_IU2_FLUSH_TID(3) & RELEASE_SM & + MISS_TID3_SM_L2(0) ) , STD_ULOGIC_VECTOR'("1101001")); +MQQ279:IU2_SM_3_PT(45) <= + Eq(( ICD_ICM_WIMGE(1) & ADDR_MATCH & + RELEASE_SM & MISS_TID3_SM_L2(0) + ) , STD_ULOGIC_VECTOR'("0111")); +MQQ280:IU2_SM_3_PT(46) <= + Eq(( ICD_ICM_MISS & ICD_ICM_TID(3) & + ADDR_MATCH & ICS_ICM_IU2_FLUSH_TID(3) & + MISS_TID3_SM_L2(0) ) , STD_ULOGIC_VECTOR'("11001")); +MQQ281:IU2_SM_3_PT(47) <= + Eq(( ICD_ICM_MISS & ICD_ICM_TID(3) & + ICD_ICM_WIMGE(1) & ICS_ICM_IU2_FLUSH_TID(3) & + MISS_TID3_SM_L2(0) ) , STD_ULOGIC_VECTOR'("11101")); +MQQ282:IU2_SM_3_PT(48) <= + Eq(( ICD_ICM_TID(3) & MISS_TID3_SM_L2(0) + ) , STD_ULOGIC_VECTOR'("01")); +MQQ283:IU2_SM_3_PT(49) <= + Eq(( ICD_ICM_MISS & MISS_TID3_SM_L2(0) + ) , STD_ULOGIC_VECTOR'("01")); +-- Table IU2_SM_3 Signal Assignments for Outputs +MQQ284:MISS_TID3_SM_D(0) <= + (IU2_SM_3_PT(1) OR IU2_SM_3_PT(19) + OR IU2_SM_3_PT(38) OR IU2_SM_3_PT(39) + OR IU2_SM_3_PT(43) OR IU2_SM_3_PT(45) + OR IU2_SM_3_PT(48) OR IU2_SM_3_PT(49) + ); +MQQ285:MISS_TID3_SM_D(1) <= + (IU2_SM_3_PT(20) OR IU2_SM_3_PT(40) + OR IU2_SM_3_PT(46) OR IU2_SM_3_PT(47) + ); +MQQ286:MISS_TID3_SM_D(2) <= + (IU2_SM_3_PT(37) OR IU2_SM_3_PT(44) + ); +MQQ287:MISS_TID3_SM_D(3) <= + (IU2_SM_3_PT(41)); +MQQ288:MISS_TID3_SM_D(4) <= + (IU2_SM_3_PT(22) OR IU2_SM_3_PT(36) + ); +MQQ289:MISS_TID3_SM_D(5) <= + (IU2_SM_3_PT(4)); +MQQ290:MISS_TID3_SM_D(6) <= + (IU2_SM_3_PT(14) OR IU2_SM_3_PT(21) + OR IU2_SM_3_PT(31)); +MQQ291:MISS_TID3_SM_D(7) <= + (IU2_SM_3_PT(42)); +MQQ292:MISS_TID3_SM_D(8) <= + (IU2_SM_3_PT(35)); +MQQ293:MISS_TID3_SM_D(9) <= + (IU2_SM_3_PT(3)); +MQQ294:MISS_TID3_SM_D(10) <= + (IU2_SM_3_PT(13) OR IU2_SM_3_PT(30) + ); +MQQ295:MISS_TID3_SM_D(11) <= + (IU2_SM_3_PT(2)); +MQQ296:MISS_TID3_SM_D(12) <= + (IU2_SM_3_PT(12) OR IU2_SM_3_PT(33) + ); +MQQ297:MISS_TID3_SM_D(13) <= + (IU2_SM_3_PT(8)); +MQQ298:MISS_TID3_SM_D(14) <= + (IU2_SM_3_PT(11) OR IU2_SM_3_PT(16) + ); +MQQ299:MISS_TID3_SM_D(15) <= + (IU2_SM_3_PT(10)); +MQQ300:MISS_TID3_SM_D(16) <= + (IU2_SM_3_PT(32)); +MQQ301:MISS_TID3_SM_D(17) <= + (IU2_SM_3_PT(7)); +MQQ302:MISS_TID3_SM_D(18) <= + (IU2_SM_3_PT(15)); +MQQ303:MISS_TID3_SM_D(19) <= + (IU2_SM_3_PT(9)); +MQQ304:RESET_STATE(3) <= + (IU2_SM_3_PT(19) OR IU2_SM_3_PT(43) + ); +MQQ305:REQUEST_TID(3) <= + (IU2_SM_3_PT(46) OR IU2_SM_3_PT(47) + ); +MQQ306:WRITE_DIR_INVAL(3) <= + (IU2_SM_3_PT(34)); +MQQ307:WRITE_DIR_VAL(3) <= + (IU2_SM_3_PT(25)); +MQQ308:HOLD_TID(3) <= + (IU2_SM_3_PT(17) OR IU2_SM_3_PT(18) + OR IU2_SM_3_PT(23) OR IU2_SM_3_PT(27) + OR IU2_SM_3_PT(28) OR IU2_SM_3_PT(29) + ); +MQQ309:DATA_WRITE(3) <= + (IU2_SM_3_PT(5) OR IU2_SM_3_PT(26) + ); +MQQ310:DIR_WRITE(3) <= + (IU2_SM_3_PT(5)); +MQQ311:LOAD_TID(3) <= + (IU2_SM_3_PT(6) OR IU2_SM_3_PT(24) + ); +MQQ312:RELEASE_SM_HOLD(3) <= + (IU2_SM_3_PT(2) OR IU2_SM_3_PT(19) + OR IU2_SM_3_PT(43)); + +load_quiesce(0) <= miss_tid0_sm_l2(0); +load_quiesce(1) <= miss_tid1_sm_l2(0); +load_quiesce(2) <= miss_tid2_sm_l2(0); +load_quiesce(3) <= miss_tid3_sm_l2(0); +ic_fdep_load_quiesce <= load_quiesce; +iu_mm_lmq_empty <= and_reduce(load_quiesce); +miss_act(0) <= miss_tid0_sm_l2(0) and icd_icm_any_iu2_valid and icd_icm_tid(0); +miss_addr0_real_d <= icd_icm_addr_real; +miss_addr0_eff_d <= icd_icm_addr_eff; +miss_ci0_d <= icd_icm_wimge(1); +miss_endian0_d <= icd_icm_wimge(4); +miss_2ucode0_d <= icd_icm_2ucode; +miss_2ucode0_type_d <= icd_icm_2ucode_type; +-- State-related latches +-- Any XU or BP flush occurred +set_flush_occurred(0) <= (xu_iu_flush(0) or bp_ic_iu5_redirect_tid(0)) and not miss_tid0_sm_l2(0) and not miss_tid0_sm_l2(2); +miss_flush_occurred0_d <= '0' when reset_state(0) = '1' + else '1' when set_flush_occurred(0) = '1' + else miss_flush_occurred0_l2; +-- Flushed before entering Data0 - don't load ICache if flushed outside range +flush_addr_outside_range(0) <= ics_icm_iu0_ifar0 /= (miss_addr0_eff_l2(46 to 51) & miss_addr0_real_l2(52)); +set_flushed(0) <= miss_flush_occurred0_l2 and flush_addr_outside_range(0) and reld_r1_tid_l2(0) and (miss_tid0_sm_l2(1) or miss_tid0_sm_l2(11)); +miss_flushed0_d <= '0' when reset_state(0) = '1' + else '1' when set_flushed(0) = '1' + else miss_flushed0_l2; +inval_equal(0) <= icd_icm_iu2_inval and addr_equal(0); +set_invalidated(0) <= (inval_equal(0) or icd_icm_ici) and not miss_tid0_sm_l2(0) and not miss_tid0_sm_l2(2) and not miss_ci0_l2; +miss_inval0_d <= '0' when reset_state(0) = '1' + else '1' when set_invalidated(0) = '1' + else miss_inval0_l2; +sent_fp(0) <= reld_r3_tid_l2(0) and r3_loaded_l2 and not (an_ac_reld_ecc_err_l2 and not an_ac_reld_ecc_err_ue_l2); +set_block_fp(0) <= sent_fp(0) or + (ics_icm_iu3_flush_tid(0) and not (miss_tid0_sm_l2(0) or miss_tid0_sm_l2(2))); +miss_block_fp0_d <= '0' when reset_state(0) = '1' + else '1' when set_block_fp(0) = '1' + else miss_block_fp0_l2; +miss_ecc_err0_d <= '0' when (reset_state(0) or miss_tid0_sm_d(3) or miss_tid0_sm_d(7)) = '1' + else '1' when (new_ecc_err(0) and not miss_tid0_sm_l2(3) and not miss_tid0_sm_l2(7))= '1' + else miss_ecc_err0_l2; +miss_ecc_err_ue0_d <= '0' when (reset_state(0) or miss_tid0_sm_d(3) or miss_tid0_sm_d(7)) = '1' + else an_ac_reld_ecc_err_ue_l2 when new_ecc_err_ue(0) = '1' + else miss_ecc_err_ue0_l2; +miss_act(1) <= miss_tid1_sm_l2(0) and icd_icm_any_iu2_valid and icd_icm_tid(1); +miss_addr1_real_d <= icd_icm_addr_real; +miss_addr1_eff_d <= icd_icm_addr_eff; +miss_ci1_d <= icd_icm_wimge(1); +miss_endian1_d <= icd_icm_wimge(4); +miss_2ucode1_d <= icd_icm_2ucode; +miss_2ucode1_type_d <= icd_icm_2ucode_type; +-- State-related latches +-- Any XU or BP flush occurred +set_flush_occurred(1) <= (xu_iu_flush(1) or bp_ic_iu5_redirect_tid(1)) and not miss_tid1_sm_l2(0) and not miss_tid1_sm_l2(2); +miss_flush_occurred1_d <= '0' when reset_state(1) = '1' + else '1' when set_flush_occurred(1) = '1' + else miss_flush_occurred1_l2; +-- Flushed before entering Data0 - don't load ICache if flushed outside range +flush_addr_outside_range(1) <= ics_icm_iu0_ifar1 /= (miss_addr1_eff_l2(46 to 51) & miss_addr1_real_l2(52)); +set_flushed(1) <= miss_flush_occurred1_l2 and flush_addr_outside_range(1) and reld_r1_tid_l2(1) and (miss_tid1_sm_l2(1) or miss_tid1_sm_l2(11)); +miss_flushed1_d <= '0' when reset_state(1) = '1' + else '1' when set_flushed(1) = '1' + else miss_flushed1_l2; +inval_equal(1) <= icd_icm_iu2_inval and addr_equal(1); +set_invalidated(1) <= (inval_equal(1) or icd_icm_ici) and not miss_tid1_sm_l2(0) and not miss_tid1_sm_l2(2) and not miss_ci1_l2; +miss_inval1_d <= '0' when reset_state(1) = '1' + else '1' when set_invalidated(1) = '1' + else miss_inval1_l2; +sent_fp(1) <= reld_r3_tid_l2(1) and r3_loaded_l2 and not (an_ac_reld_ecc_err_l2 and not an_ac_reld_ecc_err_ue_l2); +set_block_fp(1) <= sent_fp(1) or + (ics_icm_iu3_flush_tid(1) and not (miss_tid1_sm_l2(0) or miss_tid1_sm_l2(2))); +miss_block_fp1_d <= '0' when reset_state(1) = '1' + else '1' when set_block_fp(1) = '1' + else miss_block_fp1_l2; +miss_ecc_err1_d <= '0' when (reset_state(1) or miss_tid1_sm_d(3) or miss_tid1_sm_d(7)) = '1' + else '1' when (new_ecc_err(1) and not miss_tid1_sm_l2(3) and not miss_tid1_sm_l2(7))= '1' + else miss_ecc_err1_l2; +miss_ecc_err_ue1_d <= '0' when (reset_state(1) or miss_tid1_sm_d(3) or miss_tid1_sm_d(7)) = '1' + else an_ac_reld_ecc_err_ue_l2 when new_ecc_err_ue(1) = '1' + else miss_ecc_err_ue1_l2; +miss_act(2) <= miss_tid2_sm_l2(0) and icd_icm_any_iu2_valid and icd_icm_tid(2); +miss_addr2_real_d <= icd_icm_addr_real; +miss_addr2_eff_d <= icd_icm_addr_eff; +miss_ci2_d <= icd_icm_wimge(1); +miss_endian2_d <= icd_icm_wimge(4); +miss_2ucode2_d <= icd_icm_2ucode; +miss_2ucode2_type_d <= icd_icm_2ucode_type; +-- State-related latches +-- Any XU or BP flush occurred +set_flush_occurred(2) <= (xu_iu_flush(2) or bp_ic_iu5_redirect_tid(2)) and not miss_tid2_sm_l2(0) and not miss_tid2_sm_l2(2); +miss_flush_occurred2_d <= '0' when reset_state(2) = '1' + else '1' when set_flush_occurred(2) = '1' + else miss_flush_occurred2_l2; +-- Flushed before entering Data0 - don't load ICache if flushed outside range +flush_addr_outside_range(2) <= ics_icm_iu0_ifar2 /= (miss_addr2_eff_l2(46 to 51) & miss_addr2_real_l2(52)); +set_flushed(2) <= miss_flush_occurred2_l2 and flush_addr_outside_range(2) and reld_r1_tid_l2(2) and (miss_tid2_sm_l2(1) or miss_tid2_sm_l2(11)); +miss_flushed2_d <= '0' when reset_state(2) = '1' + else '1' when set_flushed(2) = '1' + else miss_flushed2_l2; +inval_equal(2) <= icd_icm_iu2_inval and addr_equal(2); +set_invalidated(2) <= (inval_equal(2) or icd_icm_ici) and not miss_tid2_sm_l2(0) and not miss_tid2_sm_l2(2) and not miss_ci2_l2; +miss_inval2_d <= '0' when reset_state(2) = '1' + else '1' when set_invalidated(2) = '1' + else miss_inval2_l2; +sent_fp(2) <= reld_r3_tid_l2(2) and r3_loaded_l2 and not (an_ac_reld_ecc_err_l2 and not an_ac_reld_ecc_err_ue_l2); +set_block_fp(2) <= sent_fp(2) or + (ics_icm_iu3_flush_tid(2) and not (miss_tid2_sm_l2(0) or miss_tid2_sm_l2(2))); +miss_block_fp2_d <= '0' when reset_state(2) = '1' + else '1' when set_block_fp(2) = '1' + else miss_block_fp2_l2; +miss_ecc_err2_d <= '0' when (reset_state(2) or miss_tid2_sm_d(3) or miss_tid2_sm_d(7)) = '1' + else '1' when (new_ecc_err(2) and not miss_tid2_sm_l2(3) and not miss_tid2_sm_l2(7))= '1' + else miss_ecc_err2_l2; +miss_ecc_err_ue2_d <= '0' when (reset_state(2) or miss_tid2_sm_d(3) or miss_tid2_sm_d(7)) = '1' + else an_ac_reld_ecc_err_ue_l2 when new_ecc_err_ue(2) = '1' + else miss_ecc_err_ue2_l2; +miss_act(3) <= miss_tid3_sm_l2(0) and icd_icm_any_iu2_valid and icd_icm_tid(3); +miss_addr3_real_d <= icd_icm_addr_real; +miss_addr3_eff_d <= icd_icm_addr_eff; +miss_ci3_d <= icd_icm_wimge(1); +miss_endian3_d <= icd_icm_wimge(4); +miss_2ucode3_d <= icd_icm_2ucode; +miss_2ucode3_type_d <= icd_icm_2ucode_type; +-- State-related latches +-- Any XU or BP flush occurred +set_flush_occurred(3) <= (xu_iu_flush(3) or bp_ic_iu5_redirect_tid(3)) and not miss_tid3_sm_l2(0) and not miss_tid3_sm_l2(2); +miss_flush_occurred3_d <= '0' when reset_state(3) = '1' + else '1' when set_flush_occurred(3) = '1' + else miss_flush_occurred3_l2; +-- Flushed before entering Data0 - don't load ICache if flushed outside range +flush_addr_outside_range(3) <= ics_icm_iu0_ifar3 /= (miss_addr3_eff_l2(46 to 51) & miss_addr3_real_l2(52)); +set_flushed(3) <= miss_flush_occurred3_l2 and flush_addr_outside_range(3) and reld_r1_tid_l2(3) and (miss_tid3_sm_l2(1) or miss_tid3_sm_l2(11)); +miss_flushed3_d <= '0' when reset_state(3) = '1' + else '1' when set_flushed(3) = '1' + else miss_flushed3_l2; +inval_equal(3) <= icd_icm_iu2_inval and addr_equal(3); +set_invalidated(3) <= (inval_equal(3) or icd_icm_ici) and not miss_tid3_sm_l2(0) and not miss_tid3_sm_l2(2) and not miss_ci3_l2; +miss_inval3_d <= '0' when reset_state(3) = '1' + else '1' when set_invalidated(3) = '1' + else miss_inval3_l2; +sent_fp(3) <= reld_r3_tid_l2(3) and r3_loaded_l2 and not (an_ac_reld_ecc_err_l2 and not an_ac_reld_ecc_err_ue_l2); +set_block_fp(3) <= sent_fp(3) or + (ics_icm_iu3_flush_tid(3) and not (miss_tid3_sm_l2(0) or miss_tid3_sm_l2(2))); +miss_block_fp3_d <= '0' when reset_state(3) = '1' + else '1' when set_block_fp(3) = '1' + else miss_block_fp3_l2; +miss_ecc_err3_d <= '0' when (reset_state(3) or miss_tid3_sm_d(3) or miss_tid3_sm_d(7)) = '1' + else '1' when (new_ecc_err(3) and not miss_tid3_sm_l2(3) and not miss_tid3_sm_l2(7))= '1' + else miss_ecc_err3_l2; +miss_ecc_err_ue3_d <= '0' when (reset_state(3) or miss_tid3_sm_d(3) or miss_tid3_sm_d(7)) = '1' + else an_ac_reld_ecc_err_ue_l2 when new_ecc_err_ue(3) = '1' + else miss_ecc_err_ue3_l2; +addr_equal(0) <= (icd_icm_addr_real(REAL_IFAR'left to 56) = miss_addr0_real_l2(REAL_IFAR'left to 56)) and + (spr_ic_cls_l2 or (icd_icm_addr_real(57) = miss_addr0_real_l2(57))); +addr_equal(1) <= (icd_icm_addr_real(REAL_IFAR'left to 56) = miss_addr1_real_l2(REAL_IFAR'left to 56)) and + (spr_ic_cls_l2 or (icd_icm_addr_real(57) = miss_addr1_real_l2(57))); +addr_equal(2) <= (icd_icm_addr_real(REAL_IFAR'left to 56) = miss_addr2_real_l2(REAL_IFAR'left to 56)) and + (spr_ic_cls_l2 or (icd_icm_addr_real(57) = miss_addr2_real_l2(57))); +addr_equal(3) <= (icd_icm_addr_real(REAL_IFAR'left to 56) = miss_addr3_real_l2(REAL_IFAR'left to 56)) and + (spr_ic_cls_l2 or (icd_icm_addr_real(57) = miss_addr3_real_l2(57))); +addr_match <= + (addr_equal(0) and not miss_tid0_sm_l2(0) and not miss_ci0_l2) or + (addr_equal(1) and not miss_tid1_sm_l2(0) and not miss_ci1_l2) or + (addr_equal(2) and not miss_tid2_sm_l2(0) and not miss_ci2_l2) or + (addr_equal(3) and not miss_tid3_sm_l2(0) and not miss_ci3_l2); +miss_thread_is_idle <= (miss_tid0_sm_l2(0) and icd_icm_tid(0)) or + (miss_tid1_sm_l2(0) and icd_icm_tid(1)) or + (miss_tid2_sm_l2(0) and icd_icm_tid(2)) or + (miss_tid3_sm_l2(0) and icd_icm_tid(3)) ; +-- When '1', flushes go back to current miss ifar +iu3_miss_match_d <= (addr_match and not icd_icm_wimge(1)) when miss_thread_is_idle = '1' + else (not miss_thread_is_idle); +icm_ics_iu2_miss_match_prev <= iu3_miss_match_l2; +release_sm <= or_reduce( release_sm_hold(0 to 3) ); +-- Detect write through collision with invalidate read +iu0_inval_match(0) <= ics_icm_iu0_inval and (ics_icm_iu0_inval_addr(52 to 56) = miss_addr0_real_l2(52 to 56)) and + (spr_ic_cls_l2 or (ics_icm_iu0_inval_addr(57) = miss_addr0_real_l2(57))); +miss_wrote_dir0_d <= '0' when reset_state(0) = '1' + else (dir_write_no_block(0) or miss_wrote_dir0_l2); +miss_wrote_dir_v(0) <= miss_wrote_dir0_l2; +iu0_inval_match(1) <= ics_icm_iu0_inval and (ics_icm_iu0_inval_addr(52 to 56) = miss_addr1_real_l2(52 to 56)) and + (spr_ic_cls_l2 or (ics_icm_iu0_inval_addr(57) = miss_addr1_real_l2(57))); +miss_wrote_dir1_d <= '0' when reset_state(1) = '1' + else (dir_write_no_block(1) or miss_wrote_dir1_l2); +miss_wrote_dir_v(1) <= miss_wrote_dir1_l2; +iu0_inval_match(2) <= ics_icm_iu0_inval and (ics_icm_iu0_inval_addr(52 to 56) = miss_addr2_real_l2(52 to 56)) and + (spr_ic_cls_l2 or (ics_icm_iu0_inval_addr(57) = miss_addr2_real_l2(57))); +miss_wrote_dir2_d <= '0' when reset_state(2) = '1' + else (dir_write_no_block(2) or miss_wrote_dir2_l2); +miss_wrote_dir_v(2) <= miss_wrote_dir2_l2; +iu0_inval_match(3) <= ics_icm_iu0_inval and (ics_icm_iu0_inval_addr(52 to 56) = miss_addr3_real_l2(52 to 56)) and + (spr_ic_cls_l2 or (ics_icm_iu0_inval_addr(57) = miss_addr3_real_l2(57))); +miss_wrote_dir3_d <= '0' when reset_state(3) = '1' + else (dir_write_no_block(3) or miss_wrote_dir3_l2); +miss_wrote_dir_v(3) <= miss_wrote_dir3_l2; +miss_need_hold0_d <= '0' when ics_icm_iu3_flush_tid(0) = '1' + else '1' when (icd_icm_miss and icd_icm_tid(0)) = '1' + else miss_need_hold0_l2; +miss_need_hold1_d <= '0' when ics_icm_iu3_flush_tid(1) = '1' + else '1' when (icd_icm_miss and icd_icm_tid(1)) = '1' + else miss_need_hold1_l2; +miss_need_hold2_d <= '0' when ics_icm_iu3_flush_tid(2) = '1' + else '1' when (icd_icm_miss and icd_icm_tid(2)) = '1' + else miss_need_hold2_l2; +miss_need_hold3_d <= '0' when ics_icm_iu3_flush_tid(3) = '1' + else '1' when (icd_icm_miss and icd_icm_tid(3)) = '1' + else miss_need_hold3_l2; +----------------------------------------------------------------------- +-- Send request +----------------------------------------------------------------------- +request_d <= or_reduce( request_tid(0 to 3) ); +req_thread_d <= icd_icm_tid; +req_ra_d <= icd_icm_addr_real(REAL_IFAR'left to 59); +req_wimge_d <= icd_icm_wimge; +req_userdef_d <= icd_icm_userdef; +iu_xu_request <= request_l2 and not icd_icm_iu3_erat_err; +iu_xu_thread <= req_thread_l2; +iu_xu_ra <= req_ra_l2; +iu_xu_wimge <= req_wimge_l2; +iu_xu_userdef <= req_userdef_l2; +erat_err <= gate_and( (request_l2 and icd_icm_iu3_erat_err), req_thread_l2 ); +----------------------------------------------------------------------- +-- fastpath-related signals +----------------------------------------------------------------------- +-- for first beat of data: create hole in IU0 so we can fastpath data into IU2 +preload_r0_tid(0) <= r0_crit_qw(0) and reld_r0_tid_plain(0) and not miss_block_fp0_l2; +preload_r0_tid(1) <= r0_crit_qw(1) and reld_r0_tid_plain(1) and not miss_block_fp1_l2; +preload_r0_tid(2) <= r0_crit_qw(2) and reld_r0_tid_plain(2) and not miss_block_fp2_l2; +preload_r0_tid(3) <= r0_crit_qw(3) and reld_r0_tid_plain(3) and not miss_block_fp3_l2; +preload_hold_iu0 <= reld_r0_vld and or_reduce(preload_r0_tid); +-- Used for BP & LRU +r0_addr <= + gate_and(reld_r0_tid_plain(0), miss_addr0_real_l2(52 to 59)) or + gate_and(reld_r0_tid_plain(1), miss_addr1_real_l2(52 to 59)) or + gate_and(reld_r0_tid_plain(2), miss_addr2_real_l2(52 to 59)) or + gate_and(reld_r0_tid_plain(3), miss_addr3_real_l2(52 to 59)); +icm_ics_iu0_preload_val <= preload_hold_iu0; +icm_ics_iu0_preload_tid <= reld_r0_tid_plain; +icm_ics_iu0_preload_ifar <= r0_addr(52 to 59); +-- load_tid only happens in r2, so can use reld_r2_tid_l2 to select address instead of load_tid +r2_load_addr <= +gate_and(reld_r2_tid_l2(0),(miss_addr0_eff_l2 & miss_addr0_real_l2(52 to 61))) or +gate_and(reld_r2_tid_l2(1),(miss_addr1_eff_l2 & miss_addr1_real_l2(52 to 61))) or +gate_and(reld_r2_tid_l2(2),(miss_addr2_eff_l2 & miss_addr2_real_l2(52 to 61))) or +gate_and(reld_r2_tid_l2(3),(miss_addr3_eff_l2 & miss_addr3_real_l2(52 to 61))); +r2_load_2ucode <= +(reld_r2_tid_l2(0) and miss_2ucode0_l2) or +(reld_r2_tid_l2(1) and miss_2ucode1_l2) or +(reld_r2_tid_l2(2) and miss_2ucode2_l2) or +(reld_r2_tid_l2(3) and miss_2ucode3_l2); +r2_load_2ucode_type <= +(reld_r2_tid_l2(0) and miss_2ucode0_type_l2) or +(reld_r2_tid_l2(1) and miss_2ucode1_type_l2) or +(reld_r2_tid_l2(2) and miss_2ucode2_type_l2) or +(reld_r2_tid_l2(3) and miss_2ucode3_type_l2); +load_tid_no_block(0) <= load_tid(0) and not miss_block_fp0_l2; +load_tid_no_block(1) <= load_tid(1) and not miss_block_fp1_l2; +load_tid_no_block(2) <= load_tid(2) and not miss_block_fp2_l2; +load_tid_no_block(3) <= load_tid(3) and not miss_block_fp3_l2; +icm_ics_load_tid <= load_tid_no_block; +icm_icd_load_tid <= load_tid_no_block; +icm_icd_load_addr <= r2_load_addr; +icm_icd_load_2ucode <= r2_load_2ucode; +icm_icd_load_2ucode_type <= r2_load_2ucode_type; +r3_loaded_d <= or_reduce( load_tid_no_block ); +----------------------------------------------------------------------- +-- Critical Quadword +----------------------------------------------------------------------- +-- Note: Could latch reld_crit_qw signal from L2, but we need addr (60:61), so might as well keep whole address +r0_crit_qw(0) <= an_ac_reld_qw_l2(58 to 59) = miss_addr0_real_l2(58 to 59) when spr_ic_cls_l2 = '0' + else an_ac_reld_qw_l2(57 to 59) = miss_addr0_real_l2(57 to 59); +r1_crit_qw(0) <= reld_r1_qw_l2(1 to 2) = miss_addr0_real_l2(58 to 59) when spr_ic_cls_l2 = '0' + else reld_r1_qw_l2(0 to 2) = miss_addr0_real_l2(57 to 59); +r0_crit_qw(1) <= an_ac_reld_qw_l2(58 to 59) = miss_addr1_real_l2(58 to 59) when spr_ic_cls_l2 = '0' + else an_ac_reld_qw_l2(57 to 59) = miss_addr1_real_l2(57 to 59); +r1_crit_qw(1) <= reld_r1_qw_l2(1 to 2) = miss_addr1_real_l2(58 to 59) when spr_ic_cls_l2 = '0' + else reld_r1_qw_l2(0 to 2) = miss_addr1_real_l2(57 to 59); +r0_crit_qw(2) <= an_ac_reld_qw_l2(58 to 59) = miss_addr2_real_l2(58 to 59) when spr_ic_cls_l2 = '0' + else an_ac_reld_qw_l2(57 to 59) = miss_addr2_real_l2(57 to 59); +r1_crit_qw(2) <= reld_r1_qw_l2(1 to 2) = miss_addr2_real_l2(58 to 59) when spr_ic_cls_l2 = '0' + else reld_r1_qw_l2(0 to 2) = miss_addr2_real_l2(57 to 59); +r0_crit_qw(3) <= an_ac_reld_qw_l2(58 to 59) = miss_addr3_real_l2(58 to 59) when spr_ic_cls_l2 = '0' + else an_ac_reld_qw_l2(57 to 59) = miss_addr3_real_l2(57 to 59); +r1_crit_qw(3) <= reld_r1_qw_l2(1 to 2) = miss_addr3_real_l2(58 to 59) when spr_ic_cls_l2 = '0' + else reld_r1_qw_l2(0 to 2) = miss_addr3_real_l2(57 to 59); +r2_crit_qw_d <= or_reduce(r1_crit_qw and reld_r1_tid_l2); +----------------------------------------------------------------------- +-- Get LRU +----------------------------------------------------------------------- +-- read lru in r0 for timing, and use in r1 +icm_icd_lru_addr <= r0_addr(52 to 57); +lru_write_hit <= or_reduce(lru_write) and (r0_addr(52 to 56) = lru_write_addr(52 to 56)) and + (spr_ic_cls_l2 or (r0_addr(57) = lru_write_addr(57))); +row_val_d <= icd_icm_row_val; +hit_lru <= gate_and(lru_write_way(0), ("11" & icd_icm_row_lru(2))) or + gate_and(lru_write_way(1), ("10" & icd_icm_row_lru(2))) or + gate_and(lru_write_way(2), ('0' & icd_icm_row_lru(1) & '1')) or + gate_and(lru_write_way(3), ('0' & icd_icm_row_lru(1) & '0')); +row_lru_d <= icd_icm_row_lru when lru_write_hit = '0' + else hit_lru; +-- Select_lru in r1, read lru out of dir in r0 & latch +select_lru(0) <= not miss_ci0_l2 and reld_r1_tid_l2(0) and miss_tid0_sm_l2(1); +select_lru(1) <= not miss_ci1_l2 and reld_r1_tid_l2(1) and miss_tid1_sm_l2(1); +select_lru(2) <= not miss_ci2_l2 and reld_r1_tid_l2(2) and miss_tid2_sm_l2(1); +select_lru(3) <= not miss_ci3_l2 and reld_r1_tid_l2(3) and miss_tid3_sm_l2(1); +-- lru/way is valid in Data0-3, Wait1-3, CheckECC +lru_valid(0) <= not (miss_tid0_sm_l2(0) or miss_tid0_sm_l2(1) or miss_tid0_sm_l2(2) or miss_flushed0_l2 or miss_inval0_l2 or miss_ci0_l2); +lru_valid(1) <= not (miss_tid1_sm_l2(0) or miss_tid1_sm_l2(1) or miss_tid1_sm_l2(2) or miss_flushed1_l2 or miss_inval1_l2 or miss_ci1_l2); +lru_valid(2) <= not (miss_tid2_sm_l2(0) or miss_tid2_sm_l2(1) or miss_tid2_sm_l2(2) or miss_flushed2_l2 or miss_inval2_l2 or miss_ci2_l2); +lru_valid(3) <= not (miss_tid3_sm_l2(0) or miss_tid3_sm_l2(1) or miss_tid3_sm_l2(2) or miss_flushed3_l2 or miss_inval3_l2 or miss_ci3_l2); +r1_addr <= + gate_and(reld_r1_tid_l2(0), miss_addr0_real_l2(52 to 57)) or + gate_and(reld_r1_tid_l2(1), miss_addr1_real_l2(52 to 57)) or + gate_and(reld_r1_tid_l2(2), miss_addr2_real_l2(52 to 57)) or + gate_and(reld_r1_tid_l2(3), miss_addr3_real_l2(52 to 57)); +-- check if any other thread is writing into this spot in the cache +row_match(0) <= lru_valid(0) and (r1_addr(52 to 56) = miss_addr0_real_l2(52 to 56)) and + (spr_ic_cls_l2 or (r1_addr(57) = miss_addr0_real_l2(57))); +row_match(1) <= lru_valid(1) and (r1_addr(52 to 56) = miss_addr1_real_l2(52 to 56)) and + (spr_ic_cls_l2 or (r1_addr(57) = miss_addr1_real_l2(57))); +row_match(2) <= lru_valid(2) and (r1_addr(52 to 56) = miss_addr2_real_l2(52 to 56)) and + (spr_ic_cls_l2 or (r1_addr(57) = miss_addr2_real_l2(57))); +row_match(3) <= lru_valid(3) and (r1_addr(52 to 56) = miss_addr3_real_l2(52 to 56)) and + (spr_ic_cls_l2 or (r1_addr(57) = miss_addr3_real_l2(57))); +row_match_way <= + gate_and(row_match(0), miss_way0_l2) or + gate_and(row_match(1), miss_way1_l2) or + gate_and(row_match(2), miss_way2_l2) or + gate_and(row_match(3), miss_way3_l2); +val_or_match <= row_val_l2 or row_match_way; +-- Could have all 4 threads going to same row +-- +-- Final Table Listing +-- *INPUTS*=================*OUTPUTS*======* +-- | | | +-- | row_lru_l2 | | +-- | | row_match_way | | +-- | | | | next_lru_way | +-- | | | | | | +-- | | | | | | +-- | 012 0123 | 0123 | +-- *TYPE*===================+==============+ +-- | PPP PPPP | PPPP | +-- *POLARITY*-------------->| ++++ | +-- *PHASE*----------------->| TTTT | +-- *TERMS*==================+==============+ +-- 1 | 0-1 01-1 | 1... | +-- 2 | 0-0 011- | 1... | +-- 3 | 0-1 10-1 | .1.. | +-- 4 | 0-0 101- | .1.. | +-- 5 | 11- -101 | ..1. | +-- 6 | 10- 1-01 | ..1. | +-- 7 | 11- -110 | ...1 | +-- 8 | 10- 1-10 | ...1 | +-- 9 | 11- -111 | 1... | +-- 10 | 10- 1-11 | .1.. | +-- 11 | 0-1 11-1 | ..1. | +-- 12 | 0-0 111- | ...1 | +-- 13 | -01 0--1 | 1... | +-- 14 | -00 0-1- | 1... | +-- 15 | -11 -0-1 | .1.. | +-- 16 | -10 -01- | .1.. | +-- 17 | -10 -10- | ..1. | +-- 18 | -00 1-0- | ..1. | +-- 19 | -11 -1-0 | ...1 | +-- 20 | -01 1--0 | ...1 | +-- 21 | 00- 0--- | 1... | +-- 22 | 01- -0-- | .1.. | +-- 23 | 1-0 --0- | ..1. | +-- 24 | 1-1 ---0 | ...1 | +-- *=======================================* +-- +-- Table SELECT_LRU_WAY Signal Assignments for Product Terms +MQQ313:SELECT_LRU_WAY_PT(1) <= + Eq(( ROW_LRU_L2(0) & ROW_LRU_L2(2) & + ROW_MATCH_WAY(0) & ROW_MATCH_WAY(1) & + ROW_MATCH_WAY(3) ) , STD_ULOGIC_VECTOR'("01011")); +MQQ314:SELECT_LRU_WAY_PT(2) <= + Eq(( ROW_LRU_L2(0) & ROW_LRU_L2(2) & + ROW_MATCH_WAY(0) & ROW_MATCH_WAY(1) & + ROW_MATCH_WAY(2) ) , STD_ULOGIC_VECTOR'("00011")); +MQQ315:SELECT_LRU_WAY_PT(3) <= + Eq(( ROW_LRU_L2(0) & ROW_LRU_L2(2) & + ROW_MATCH_WAY(0) & ROW_MATCH_WAY(1) & + ROW_MATCH_WAY(3) ) , STD_ULOGIC_VECTOR'("01101")); +MQQ316:SELECT_LRU_WAY_PT(4) <= + Eq(( ROW_LRU_L2(0) & ROW_LRU_L2(2) & + ROW_MATCH_WAY(0) & ROW_MATCH_WAY(1) & + ROW_MATCH_WAY(2) ) , STD_ULOGIC_VECTOR'("00101")); +MQQ317:SELECT_LRU_WAY_PT(5) <= + Eq(( ROW_LRU_L2(0) & ROW_LRU_L2(1) & + ROW_MATCH_WAY(1) & ROW_MATCH_WAY(2) & + ROW_MATCH_WAY(3) ) , STD_ULOGIC_VECTOR'("11101")); +MQQ318:SELECT_LRU_WAY_PT(6) <= + Eq(( ROW_LRU_L2(0) & ROW_LRU_L2(1) & + ROW_MATCH_WAY(0) & ROW_MATCH_WAY(2) & + ROW_MATCH_WAY(3) ) , STD_ULOGIC_VECTOR'("10101")); +MQQ319:SELECT_LRU_WAY_PT(7) <= + Eq(( ROW_LRU_L2(0) & ROW_LRU_L2(1) & + ROW_MATCH_WAY(1) & ROW_MATCH_WAY(2) & + ROW_MATCH_WAY(3) ) , STD_ULOGIC_VECTOR'("11110")); +MQQ320:SELECT_LRU_WAY_PT(8) <= + Eq(( ROW_LRU_L2(0) & ROW_LRU_L2(1) & + ROW_MATCH_WAY(0) & ROW_MATCH_WAY(2) & + ROW_MATCH_WAY(3) ) , STD_ULOGIC_VECTOR'("10110")); +MQQ321:SELECT_LRU_WAY_PT(9) <= + Eq(( ROW_LRU_L2(0) & ROW_LRU_L2(1) & + ROW_MATCH_WAY(1) & ROW_MATCH_WAY(2) & + ROW_MATCH_WAY(3) ) , STD_ULOGIC_VECTOR'("11111")); +MQQ322:SELECT_LRU_WAY_PT(10) <= + Eq(( ROW_LRU_L2(0) & ROW_LRU_L2(1) & + ROW_MATCH_WAY(0) & ROW_MATCH_WAY(2) & + ROW_MATCH_WAY(3) ) , STD_ULOGIC_VECTOR'("10111")); +MQQ323:SELECT_LRU_WAY_PT(11) <= + Eq(( ROW_LRU_L2(0) & ROW_LRU_L2(2) & + ROW_MATCH_WAY(0) & ROW_MATCH_WAY(1) & + ROW_MATCH_WAY(3) ) , STD_ULOGIC_VECTOR'("01111")); +MQQ324:SELECT_LRU_WAY_PT(12) <= + Eq(( ROW_LRU_L2(0) & ROW_LRU_L2(2) & + ROW_MATCH_WAY(0) & ROW_MATCH_WAY(1) & + ROW_MATCH_WAY(2) ) , STD_ULOGIC_VECTOR'("00111")); +MQQ325:SELECT_LRU_WAY_PT(13) <= + Eq(( ROW_LRU_L2(1) & ROW_LRU_L2(2) & + ROW_MATCH_WAY(0) & ROW_MATCH_WAY(3) + ) , STD_ULOGIC_VECTOR'("0101")); +MQQ326:SELECT_LRU_WAY_PT(14) <= + Eq(( ROW_LRU_L2(1) & ROW_LRU_L2(2) & + ROW_MATCH_WAY(0) & ROW_MATCH_WAY(2) + ) , STD_ULOGIC_VECTOR'("0001")); +MQQ327:SELECT_LRU_WAY_PT(15) <= + Eq(( ROW_LRU_L2(1) & ROW_LRU_L2(2) & + ROW_MATCH_WAY(1) & ROW_MATCH_WAY(3) + ) , STD_ULOGIC_VECTOR'("1101")); +MQQ328:SELECT_LRU_WAY_PT(16) <= + Eq(( ROW_LRU_L2(1) & ROW_LRU_L2(2) & + ROW_MATCH_WAY(1) & ROW_MATCH_WAY(2) + ) , STD_ULOGIC_VECTOR'("1001")); +MQQ329:SELECT_LRU_WAY_PT(17) <= + Eq(( ROW_LRU_L2(1) & ROW_LRU_L2(2) & + ROW_MATCH_WAY(1) & ROW_MATCH_WAY(2) + ) , STD_ULOGIC_VECTOR'("1010")); +MQQ330:SELECT_LRU_WAY_PT(18) <= + Eq(( ROW_LRU_L2(1) & ROW_LRU_L2(2) & + ROW_MATCH_WAY(0) & ROW_MATCH_WAY(2) + ) , STD_ULOGIC_VECTOR'("0010")); +MQQ331:SELECT_LRU_WAY_PT(19) <= + Eq(( ROW_LRU_L2(1) & ROW_LRU_L2(2) & + ROW_MATCH_WAY(1) & ROW_MATCH_WAY(3) + ) , STD_ULOGIC_VECTOR'("1110")); +MQQ332:SELECT_LRU_WAY_PT(20) <= + Eq(( ROW_LRU_L2(1) & ROW_LRU_L2(2) & + ROW_MATCH_WAY(0) & ROW_MATCH_WAY(3) + ) , STD_ULOGIC_VECTOR'("0110")); +MQQ333:SELECT_LRU_WAY_PT(21) <= + Eq(( ROW_LRU_L2(0) & ROW_LRU_L2(1) & + ROW_MATCH_WAY(0) ) , STD_ULOGIC_VECTOR'("000")); +MQQ334:SELECT_LRU_WAY_PT(22) <= + Eq(( ROW_LRU_L2(0) & ROW_LRU_L2(1) & + ROW_MATCH_WAY(1) ) , STD_ULOGIC_VECTOR'("010")); +MQQ335:SELECT_LRU_WAY_PT(23) <= + Eq(( ROW_LRU_L2(0) & ROW_LRU_L2(2) & + ROW_MATCH_WAY(2) ) , STD_ULOGIC_VECTOR'("100")); +MQQ336:SELECT_LRU_WAY_PT(24) <= + Eq(( ROW_LRU_L2(0) & ROW_LRU_L2(2) & + ROW_MATCH_WAY(3) ) , STD_ULOGIC_VECTOR'("110")); +-- Table SELECT_LRU_WAY Signal Assignments for Outputs +MQQ337:NEXT_LRU_WAY(0) <= + (SELECT_LRU_WAY_PT(1) OR SELECT_LRU_WAY_PT(2) + OR SELECT_LRU_WAY_PT(9) OR SELECT_LRU_WAY_PT(13) + OR SELECT_LRU_WAY_PT(14) OR SELECT_LRU_WAY_PT(21) + ); +MQQ338:NEXT_LRU_WAY(1) <= + (SELECT_LRU_WAY_PT(3) OR SELECT_LRU_WAY_PT(4) + OR SELECT_LRU_WAY_PT(10) OR SELECT_LRU_WAY_PT(15) + OR SELECT_LRU_WAY_PT(16) OR SELECT_LRU_WAY_PT(22) + ); +MQQ339:NEXT_LRU_WAY(2) <= + (SELECT_LRU_WAY_PT(5) OR SELECT_LRU_WAY_PT(6) + OR SELECT_LRU_WAY_PT(11) OR SELECT_LRU_WAY_PT(17) + OR SELECT_LRU_WAY_PT(18) OR SELECT_LRU_WAY_PT(23) + ); +MQQ340:NEXT_LRU_WAY(3) <= + (SELECT_LRU_WAY_PT(7) OR SELECT_LRU_WAY_PT(8) + OR SELECT_LRU_WAY_PT(12) OR SELECT_LRU_WAY_PT(19) + OR SELECT_LRU_WAY_PT(20) OR SELECT_LRU_WAY_PT(24) + ); + +next_way(0) <= (val_or_match(0) = '0') or (next_lru_way(0) and (val_or_match(0 to 3) = "1111")); +next_way(1) <= (val_or_match(0 to 1) = "10") or (next_lru_way(1) and (val_or_match(0 to 3) = "1111")); +next_way(2) <= (val_or_match(0 to 2) = "110") or (next_lru_way(2) and (val_or_match(0 to 3) = "1111")); +next_way(3) <= (val_or_match(0 to 3) = "1110") or (next_lru_way(3) and (val_or_match(0 to 3) = "1111")); +miss_way0_d <= next_way when select_lru(0) = '1' + else miss_way0_l2; +miss_way1_d <= next_way when select_lru(1) = '1' + else miss_way1_l2; +miss_way2_d <= next_way when select_lru(2) = '1' + else miss_way2_l2; +miss_way3_d <= next_way when select_lru(3) = '1' + else miss_way3_l2; +----------------------------------------------------------------------- +-- setting output signals +----------------------------------------------------------------------- +icm_ics_hold_thread(0) <= hold_tid(0) and miss_need_hold0_l2 and not ics_icm_iu3_flush_tid(0); +icm_ics_hold_thread_dbg(0) <= hold_tid(0) and miss_need_hold0_l2; +icm_ics_hold_thread(1) <= hold_tid(1) and miss_need_hold1_l2 and not ics_icm_iu3_flush_tid(1); +icm_ics_hold_thread_dbg(1) <= hold_tid(1) and miss_need_hold1_l2; +icm_ics_hold_thread(2) <= hold_tid(2) and miss_need_hold2_l2 and not ics_icm_iu3_flush_tid(2); +icm_ics_hold_thread_dbg(2) <= hold_tid(2) and miss_need_hold2_l2; +icm_ics_hold_thread(3) <= hold_tid(3) and miss_need_hold3_l2 and not ics_icm_iu3_flush_tid(3); +icm_ics_hold_thread_dbg(3) <= hold_tid(3) and miss_need_hold3_l2; +-- Use miss_flushed_d, since we don't set until r1 +hold_iu0 <= or_reduce( data_write(0 to 3) ) or + preload_hold_iu0; +icm_ics_hold_iu0 <= hold_iu0; +icm_icd_data_write <= or_reduce( data_write(0 to 3) ); +dir_inval <= or_reduce( write_dir_inval(0 to 3) ); +icm_icd_dir_inval <= dir_inval; +icm_icd_dir_val <= or_reduce( (write_dir_val(0 to 3) and miss_wrote_dir_v) ); +r3_need_back_inval_d <= or_reduce(inval_equal and write_dir_val and miss_wrote_dir_v); +icm_icd_reload_addr <= (r2_load_addr(52 to 57) & reld_r2_qw_l2(1 to 2)) when spr_ic_cls_l2 = '0' + else (r2_load_addr(52 to 56) & reld_r2_qw_l2(0 to 2)); +reload_way <= gate_and(reld_r2_tid_l2(0), miss_way0_l2) or + gate_and(reld_r2_tid_l2(1), miss_way1_l2) or + gate_and(reld_r2_tid_l2(2), miss_way2_l2) or + gate_and(reld_r2_tid_l2(3), miss_way3_l2); +icm_icd_reload_way <= reload_way; +-- Check which endian +reload_endian <= (reld_r2_tid_l2(0) and miss_endian0_l2) or + (reld_r2_tid_l2(1) and miss_endian1_l2) or + (reld_r2_tid_l2(2) and miss_endian2_l2) or + (reld_r2_tid_l2(3) and miss_endian3_l2); +swap_endian_data <= + an_ac_reld_data_l2(24 to 31) & an_ac_reld_data_l2(16 to 23) & an_ac_reld_data_l2(8 to 15) & an_ac_reld_data_l2(0 to 7) & + an_ac_reld_data_l2(56 to 63) & an_ac_reld_data_l2(48 to 55) & an_ac_reld_data_l2(40 to 47) & an_ac_reld_data_l2(32 to 39) & + an_ac_reld_data_l2(88 to 95) & an_ac_reld_data_l2(80 to 87) & an_ac_reld_data_l2(72 to 79) & an_ac_reld_data_l2(64 to 71) & + an_ac_reld_data_l2(120 to 127) & an_ac_reld_data_l2(112 to 119) & an_ac_reld_data_l2(104 to 111) & an_ac_reld_data_l2(96 to 103); +-- Branch Decode +br_decode0 : iuq_bd + port map( + instruction => an_ac_reld_data_l2(0 to 31), + branch_decode => branch_decode0(0 to 3), + bp_bc_en => bp_config_l2(0), + bp_bclr_en => bp_config_l2(1), + bp_bcctr_en => bp_config_l2(2), + bp_sw_en => bp_config_l2(3) + ); +br_decode1 : iuq_bd + port map( + instruction => an_ac_reld_data_l2(32 to 63), + branch_decode => branch_decode1(0 to 3), + bp_bc_en => bp_config_l2(0), + bp_bclr_en => bp_config_l2(1), + bp_bcctr_en => bp_config_l2(2), + bp_sw_en => bp_config_l2(3) + ); +br_decode2 : iuq_bd + port map( + instruction => an_ac_reld_data_l2(64 to 95), + branch_decode => branch_decode2(0 to 3), + bp_bc_en => bp_config_l2(0), + bp_bclr_en => bp_config_l2(1), + bp_bcctr_en => bp_config_l2(2), + bp_sw_en => bp_config_l2(3) + ); +br_decode3 : iuq_bd + port map( + instruction => an_ac_reld_data_l2(96 to 127), + branch_decode => branch_decode3(0 to 3), + bp_bc_en => bp_config_l2(0), + bp_bclr_en => bp_config_l2(1), + bp_bcctr_en => bp_config_l2(2), + bp_sw_en => bp_config_l2(3) + ); +swap_br_decode0 : iuq_bd + port map( + instruction => swap_endian_data(0 to 31), + branch_decode => swap_branch_decode0(0 to 3), + bp_bc_en => bp_config_l2(0), + bp_bclr_en => bp_config_l2(1), + bp_bcctr_en => bp_config_l2(2), + bp_sw_en => bp_config_l2(3) + ); +swap_br_decode1 : iuq_bd + port map( + instruction => swap_endian_data(32 to 63), + branch_decode => swap_branch_decode1(0 to 3), + bp_bc_en => bp_config_l2(0), + bp_bclr_en => bp_config_l2(1), + bp_bcctr_en => bp_config_l2(2), + bp_sw_en => bp_config_l2(3) + ); +swap_br_decode2 : iuq_bd + port map( + instruction => swap_endian_data(64 to 95), + branch_decode => swap_branch_decode2(0 to 3), + bp_bc_en => bp_config_l2(0), + bp_bclr_en => bp_config_l2(1), + bp_bcctr_en => bp_config_l2(2), + bp_sw_en => bp_config_l2(3) + ); +swap_br_decode3 : iuq_bd + port map( + instruction => swap_endian_data(96 to 127), + branch_decode => swap_branch_decode3(0 to 3), + bp_bc_en => bp_config_l2(0), + bp_bclr_en => bp_config_l2(1), + bp_bcctr_en => bp_config_l2(2), + bp_sw_en => bp_config_l2(3) + ); +instr_data <= an_ac_reld_data_l2( 0 to 31) & branch_decode0(0 to 3) & + an_ac_reld_data_l2( 32 to 63) & branch_decode1(0 to 3) & + an_ac_reld_data_l2( 64 to 95) & branch_decode2(0 to 3) & + an_ac_reld_data_l2( 96 to 127) & branch_decode3(0 to 3); +swap_data <= swap_endian_data( 0 to 31) & swap_branch_decode0(0 to 3) & + swap_endian_data( 32 to 63) & swap_branch_decode1(0 to 3) & + swap_endian_data( 64 to 95) & swap_branch_decode2(0 to 3) & + swap_endian_data( 96 to 127) & swap_branch_decode3(0 to 3); +gen_data_parity: for i in 0 to 17 generate +begin + data_parity_in(i) <= xor_reduce( instr_data(i*8 to i*8+7) ); +swap_parity_in(i) <= xor_reduce( swap_data(i*8 to i*8+7) ); +end generate; +with reload_endian select +icm_icd_reload_data <= instr_data & data_parity_in when '0', + swap_data & swap_parity_in when others; +dir_write_no_block <= dir_write and not iu0_inval_match; +icm_icd_dir_write <= or_reduce(dir_write_no_block); +icm_icd_dir_write_addr <= r2_real_addr; +icm_icd_dir_write_endian <= reload_endian; +icm_icd_dir_write_way <= reload_way; +-- Dir Write moved to r2 +r2_real_addr <= + gate_and(reld_r2_tid_l2(0), miss_addr0_real_l2(REAL_IFAR'left to 57)) or + gate_and(reld_r2_tid_l2(1), miss_addr1_real_l2(REAL_IFAR'left to 57)) or + gate_and(reld_r2_tid_l2(2), miss_addr2_real_l2(REAL_IFAR'left to 57)) or + gate_and(reld_r2_tid_l2(3), miss_addr3_real_l2(REAL_IFAR'left to 57)); +-- LRU Write: Occurs 2 cycles after Data 2 data_write (64B mode) or Data6 (128B mode) +lru_write_next_cycle_d(0) <= data_write(0) and ((miss_tid0_sm_l2(5) and spr_ic_cls_l2 = '0') or + (miss_tid0_sm_l2(15) and spr_ic_cls_l2 = '1')); +lru_write_d(0) <= lru_write_next_cycle_l2(0); +lru_write(0) <= lru_write_l2(0) and not miss_inval0_l2 and (miss_tid0_sm_l2(6) or miss_tid0_sm_l2(11)); +lru_write_next_cycle_d(1) <= data_write(1) and ((miss_tid1_sm_l2(5) and spr_ic_cls_l2 = '0') or + (miss_tid1_sm_l2(15) and spr_ic_cls_l2 = '1')); +lru_write_d(1) <= lru_write_next_cycle_l2(1); +lru_write(1) <= lru_write_l2(1) and not miss_inval1_l2 and (miss_tid1_sm_l2(6) or miss_tid1_sm_l2(11)); +lru_write_next_cycle_d(2) <= data_write(2) and ((miss_tid2_sm_l2(5) and spr_ic_cls_l2 = '0') or + (miss_tid2_sm_l2(15) and spr_ic_cls_l2 = '1')); +lru_write_d(2) <= lru_write_next_cycle_l2(2); +lru_write(2) <= lru_write_l2(2) and not miss_inval2_l2 and (miss_tid2_sm_l2(6) or miss_tid2_sm_l2(11)); +lru_write_next_cycle_d(3) <= data_write(3) and ((miss_tid3_sm_l2(5) and spr_ic_cls_l2 = '0') or + (miss_tid3_sm_l2(15) and spr_ic_cls_l2 = '1')); +lru_write_d(3) <= lru_write_next_cycle_l2(3); +lru_write(3) <= lru_write_l2(3) and not miss_inval3_l2 and (miss_tid3_sm_l2(6) or miss_tid3_sm_l2(11)); +icm_icd_lru_write <= or_reduce( lru_write ); +lru_write_addr <= gate_and(lru_write_l2(0), miss_addr0_real_l2(52 to 57)) or + gate_and(lru_write_l2(1), miss_addr1_real_l2(52 to 57)) or + gate_and(lru_write_l2(2), miss_addr2_real_l2(52 to 57)) or + gate_and(lru_write_l2(3), miss_addr3_real_l2(52 to 57)); +lru_write_way <= gate_and(lru_write_l2(0), miss_way0_l2) or + gate_and(lru_write_l2(1), miss_way1_l2) or + gate_and(lru_write_l2(2), miss_way2_l2) or + gate_and(lru_write_l2(3), miss_way3_l2); +icm_icd_lru_write_addr <= lru_write_addr; +icm_icd_lru_write_way <= lru_write_way; +-- For act's in idir +icm_icd_any_reld_r2 <= or_reduce(reld_r2_tid_l2); +icm_icd_any_checkecc <= miss_tid0_sm_l2(11) or miss_tid1_sm_l2(11) or miss_tid2_sm_l2(11) or miss_tid3_sm_l2(11); +----------------------------------------------------------------------- +-- ECC Error handling +----------------------------------------------------------------------- +new_ecc_err <= gate_and(an_ac_reld_ecc_err_l2, reld_r3_tid_l2); +new_ecc_err_ue <= gate_and(an_ac_reld_ecc_err_ue_l2, reld_r3_tid_l2); +ecc_err(0) <= new_ecc_err(0) or miss_ecc_err0_l2; +ecc_err_ue(0) <= new_ecc_err_ue(0) or miss_ecc_err_ue0_l2; +ecc_inval(0) <= (an_ac_reld_ecc_err_l2 or an_ac_reld_ecc_err_ue_l2) and + miss_tid0_sm_l2(11) and not miss_ci0_l2 and not miss_flushed0_l2 and not miss_inval0_l2; +ecc_block_iu0(0) <= an_ac_reld_ecc_err_l2 and miss_tid0_sm_l2(11) and miss_need_hold0_l2; +ecc_err(1) <= new_ecc_err(1) or miss_ecc_err1_l2; +ecc_err_ue(1) <= new_ecc_err_ue(1) or miss_ecc_err_ue1_l2; +ecc_inval(1) <= (an_ac_reld_ecc_err_l2 or an_ac_reld_ecc_err_ue_l2) and + miss_tid1_sm_l2(11) and not miss_ci1_l2 and not miss_flushed1_l2 and not miss_inval1_l2; +ecc_block_iu0(1) <= an_ac_reld_ecc_err_l2 and miss_tid1_sm_l2(11) and miss_need_hold1_l2; +ecc_err(2) <= new_ecc_err(2) or miss_ecc_err2_l2; +ecc_err_ue(2) <= new_ecc_err_ue(2) or miss_ecc_err_ue2_l2; +ecc_inval(2) <= (an_ac_reld_ecc_err_l2 or an_ac_reld_ecc_err_ue_l2) and + miss_tid2_sm_l2(11) and not miss_ci2_l2 and not miss_flushed2_l2 and not miss_inval2_l2; +ecc_block_iu0(2) <= an_ac_reld_ecc_err_l2 and miss_tid2_sm_l2(11) and miss_need_hold2_l2; +ecc_err(3) <= new_ecc_err(3) or miss_ecc_err3_l2; +ecc_err_ue(3) <= new_ecc_err_ue(3) or miss_ecc_err_ue3_l2; +ecc_inval(3) <= (an_ac_reld_ecc_err_l2 or an_ac_reld_ecc_err_ue_l2) and + miss_tid3_sm_l2(11) and not miss_ci3_l2 and not miss_flushed3_l2 and not miss_inval3_l2; +ecc_block_iu0(3) <= an_ac_reld_ecc_err_l2 and miss_tid3_sm_l2(11) and miss_need_hold3_l2; +icm_ics_ecc_block_iu0 <= ecc_block_iu0; +-- CheckECC stage +-- Non-CI: If last beat of data has bad ECC, invalidate cache & flush IU1 +-- Back inval in Check ECC state +icm_icd_ecc_inval <= or_reduce(ecc_inval) or r3_need_back_inval_l2; +r3_addr <= + gate_and(reld_r3_tid_l2(0), miss_addr0_real_l2(52 to 57)) or + gate_and(reld_r3_tid_l2(1), miss_addr1_real_l2(52 to 57)) or + gate_and(reld_r3_tid_l2(2), miss_addr2_real_l2(52 to 57)) or + gate_and(reld_r3_tid_l2(3), miss_addr3_real_l2(52 to 57)); +icm_icd_ecc_addr <= r3_addr(52 to 57); +r3_way <= gate_and(reld_r3_tid_l2(0), miss_way0_l2) or + gate_and(reld_r3_tid_l2(1), miss_way1_l2) or + gate_and(reld_r3_tid_l2(2), miss_way2_l2) or + gate_and(reld_r3_tid_l2(3), miss_way3_l2); +icm_icd_ecc_way <= r3_way; +-- Flush everything in iu1 to prevent using bad data +icm_ics_iu1_ecc_flush <= or_reduce(ecc_inval); +-- CI/Critical QW: Invalidate IU3 or set error bit +ecc_fp <= r3_loaded_l2 and an_ac_reld_ecc_err_l2; +icm_icd_iu3_ecc_fp_cancel <= ecc_fp and not an_ac_reld_ecc_err_ue_l2; +icm_icd_iu3_ecc_err <= r3_loaded_l2 and an_ac_reld_ecc_err_ue_l2; +----------------------------------------------------------------------- +-- Performance Events +----------------------------------------------------------------------- +-- IL1 Miss Cycles +-- - not CI, not Idle, not WaitMiss, & not (CheckECC & done) +perf_event_t0_d(0) <= not miss_ci0_l2 and not miss_tid0_sm_l2(0) and not miss_tid0_sm_l2(2) and + not (miss_tid0_sm_l2(11) and (ecc_err_ue(0) or not ecc_err(0))) and + not erat_err(0); +perf_event_t1_d(0) <= not miss_ci1_l2 and not miss_tid1_sm_l2(0) and not miss_tid1_sm_l2(2) and + not (miss_tid1_sm_l2(11) and (ecc_err_ue(1) or not ecc_err(1))) and + not erat_err(1); +perf_event_t2_d(0) <= not miss_ci2_l2 and not miss_tid2_sm_l2(0) and not miss_tid2_sm_l2(2) and + not (miss_tid2_sm_l2(11) and (ecc_err_ue(2) or not ecc_err(2))) and + not erat_err(2); +perf_event_t3_d(0) <= not miss_ci3_l2 and not miss_tid3_sm_l2(0) and not miss_tid3_sm_l2(2) and + not (miss_tid3_sm_l2(11) and (ecc_err_ue(3) or not ecc_err(3))) and + not erat_err(3); +-- IL1 Reload Dropped +-- - not CI, flushed, & returning to Idle (release_sm_hold and not miss_tid_sm_d(11) is a more timing-friendly way of saying this) +perf_event_t0_d(1) <= not miss_ci0_l2 and miss_flushed0_l2 and (release_sm_hold(0) and not miss_tid0_sm_d(11)); +perf_event_t1_d(1) <= not miss_ci1_l2 and miss_flushed1_l2 and (release_sm_hold(1) and not miss_tid1_sm_d(11)); +perf_event_t2_d(1) <= not miss_ci2_l2 and miss_flushed2_l2 and (release_sm_hold(2) and not miss_tid2_sm_d(11)); +perf_event_t3_d(1) <= not miss_ci3_l2 and miss_flushed3_l2 and (release_sm_hold(3) and not miss_tid3_sm_d(11)); +ic_perf_event_t0 <= perf_event_t0_l2; +ic_perf_event_t1 <= perf_event_t1_l2; +ic_perf_event_t2 <= perf_event_t2_l2; +ic_perf_event_t3 <= perf_event_t3_l2; +----------------------------------------------------------------------- +-- Debug Bus +----------------------------------------------------------------------- +miss_dbg_data0(0 TO 21) <= miss_tid0_sm_l2(0 to 11) & + miss_flush_occurred0_l2 & miss_flushed0_l2 & miss_inval0_l2 & miss_block_fp0_l2 & + miss_ecc_err0_l2 & miss_ecc_err_ue0_l2 & miss_wrote_dir0_l2 & miss_need_hold0_l2 & + reld_r2_tid_l2(0) & load_tid_no_block(0); +miss_dbg_data0(22 TO 43) <= miss_tid1_sm_l2(0 to 11) & + miss_flush_occurred1_l2 & miss_flushed1_l2 & miss_inval1_l2 & miss_block_fp1_l2 & + miss_ecc_err1_l2 & miss_ecc_err_ue1_l2 & miss_wrote_dir1_l2 & miss_need_hold1_l2 & + reld_r2_tid_l2(1) & load_tid_no_block(1); +miss_dbg_data0(44 TO 65) <= miss_tid2_sm_l2(0 to 11) & + miss_flush_occurred2_l2 & miss_flushed2_l2 & miss_inval2_l2 & miss_block_fp2_l2 & + miss_ecc_err2_l2 & miss_ecc_err_ue2_l2 & miss_wrote_dir2_l2 & miss_need_hold2_l2 & + reld_r2_tid_l2(2) & load_tid_no_block(2); +miss_dbg_data0(66 TO 87) <= miss_tid3_sm_l2(0 to 11) & + miss_flush_occurred3_l2 & miss_flushed3_l2 & miss_inval3_l2 & miss_block_fp3_l2 & + miss_ecc_err3_l2 & miss_ecc_err_ue3_l2 & miss_wrote_dir3_l2 & miss_need_hold3_l2 & + reld_r2_tid_l2(3) & load_tid_no_block(3); +miss_dbg_data1(0 TO 11) <= miss_tid0_sm_l2(0 to 11); +miss_dbg_data1(12 TO 23) <= miss_tid1_sm_l2(0 to 11); +miss_dbg_data1(24) <= miss_tid2_sm_l2(0); +miss_dbg_data1(25) <= miss_tid3_sm_l2(0); +miss_dbg_data1(26 TO 35) <= r2_load_addr(52 to 61); +miss_dbg_data1(36 TO 39) <= row_val_l2; +miss_dbg_data1_d(51) <= lru_write_hit; +miss_dbg_data1(40) <= miss_dbg_data1_l2(51); +miss_dbg_data1(41 TO 43) <= row_lru_l2; +miss_dbg_data1(44 TO 47) <= select_lru; +miss_dbg_data1(48 TO 51) <= lru_valid; +miss_dbg_data1_d(52 TO 55) <= row_match_way; +miss_dbg_data1_d(56 TO 59) <= next_way; +miss_dbg_data1(52 TO 59) <= miss_dbg_data1_l2(52 to 59); +miss_dbg_data1(60 TO 63) <= perf_event_t0_l2(1) & perf_event_t1_l2(1) & perf_event_t2_l2(1) & perf_event_t3_l2(1); +miss_dbg_data1(64 TO 67) <= data_write; +miss_dbg_data1(68 TO 71) <= miss_inval0_l2 & miss_inval1_l2 & miss_inval2_l2 & miss_inval3_l2; +miss_dbg_data1(72) <= icd_icm_iu2_inval; +miss_dbg_data1(73) <= r2_load_2ucode; +miss_dbg_data1(74) <= dir_inval; +miss_dbg_data1(75) <= r3_need_back_inval_l2; +miss_dbg_data1(76 TO 79) <= write_dir_val; +miss_dbg_data1(80 TO 83) <= load_tid_no_block; +miss_dbg_data1(84 TO 87) <= reld_r2_tid_l2; +miss_dbg_data2(0 TO 9) <= icd_icm_addr_real(52 to 61); +miss_dbg_data2(10 TO 13) <= miss_tid0_sm_l2(0) & miss_tid1_sm_l2(0) & miss_tid2_sm_l2(0) & miss_tid3_sm_l2(0); +miss_dbg_data2(14 TO 17) <= req_thread_l2; +miss_dbg_data2(18) <= request_l2; +miss_dbg_data2(19 TO 27) <= req_wimge_l2 & req_userdef_l2; +miss_dbg_data2(28) <= iu3_miss_match_l2; +miss_dbg_data2(29) <= preload_hold_iu0; +miss_dbg_data2(30) <= dir_inval; +miss_dbg_data2(31) <= r3_need_back_inval_l2; +miss_dbg_data2(32 TO 35) <= write_dir_val; +miss_dbg_data2(36 TO 39) <= load_tid_no_block; +miss_dbg_data2(40 TO 43) <= reld_r2_tid_l2; +miss_dbg_trigger(0 TO 5) <= req_ra_l2(52 to 57); +miss_dbg_trigger(6) <= request_l2; +miss_dbg_trigger(7) <= reld_r0_vld; +miss_dbg_trigger(8 TO 9) <= an_ac_reld_core_tag_l2(3 to 4); +miss_dbg_trigger(10) <= an_ac_reld_ecc_err_l2; +miss_dbg_trigger(11) <= an_ac_reld_ecc_err_ue_l2; +----------------------------------------------------------------------- +-- Latches +----------------------------------------------------------------------- +spr_ic_cls_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(spr_ic_cls_offset), + scout => sov(spr_ic_cls_offset), + din => spr_ic_cls_d, + dout => spr_ic_cls_l2); +bp_config_latch: tri_rlmreg_p + generic map (width => bp_config_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(bp_config_offset to bp_config_offset + bp_config_l2'length-1), + scout => sov(bp_config_offset to bp_config_offset + bp_config_l2'length-1), + din => bp_config_d, + dout => bp_config_l2 ); +an_ac_reld_data_vld_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(an_ac_reld_data_vld_offset), + scout => sov(an_ac_reld_data_vld_offset), + din => an_ac_reld_data_vld_d, + dout => an_ac_reld_data_vld_l2 ); +an_ac_reld_core_tag_latch: tri_rlmreg_p + generic map (width => an_ac_reld_core_tag_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(an_ac_reld_core_tag_offset to an_ac_reld_core_tag_offset + an_ac_reld_core_tag_l2'length-1), + scout => sov(an_ac_reld_core_tag_offset to an_ac_reld_core_tag_offset + an_ac_reld_core_tag_l2'length-1), + din => an_ac_reld_core_tag_d, + dout => an_ac_reld_core_tag_l2); +an_ac_reld_qw_latch: tri_rlmreg_p + generic map (width => an_ac_reld_qw_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(an_ac_reld_qw_offset to an_ac_reld_qw_offset + an_ac_reld_qw_l2'length-1), + scout => sov(an_ac_reld_qw_offset to an_ac_reld_qw_offset + an_ac_reld_qw_l2'length-1), + din => an_ac_reld_qw_d, + dout => an_ac_reld_qw_l2); +reld_r1_tid_latch: tri_rlmreg_p + generic map (width => reld_r1_tid_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(reld_r1_tid_offset to reld_r1_tid_offset + reld_r1_tid_l2'length-1), + scout => sov(reld_r1_tid_offset to reld_r1_tid_offset + reld_r1_tid_l2'length-1), + din => reld_r1_tid_d, + dout => reld_r1_tid_l2); +reld_r1_qw_latch: tri_rlmreg_p + generic map (width => reld_r1_qw_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(reld_r1_qw_offset to reld_r1_qw_offset + reld_r1_qw_l2'length-1), + scout => sov(reld_r1_qw_offset to reld_r1_qw_offset + reld_r1_qw_l2'length-1), + din => reld_r1_qw_d, + dout => reld_r1_qw_l2); +an_ac_reld_data_latch: tri_rlmreg_p + generic map (width => an_ac_reld_data_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => reld_r2_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(an_ac_reld_data_offset to an_ac_reld_data_offset + an_ac_reld_data_l2'length-1), + scout => sov(an_ac_reld_data_offset to an_ac_reld_data_offset + an_ac_reld_data_l2'length-1), + din => an_ac_reld_data_d, + dout => an_ac_reld_data_l2); +reld_r2_tid_latch: tri_rlmreg_p + generic map (width => reld_r2_tid_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(reld_r2_tid_offset to reld_r2_tid_offset + reld_r2_tid_l2'length-1), + scout => sov(reld_r2_tid_offset to reld_r2_tid_offset + reld_r2_tid_l2'length-1), + din => reld_r2_tid_d, + dout => reld_r2_tid_l2); +reld_r2_qw_latch: tri_rlmreg_p + generic map (width => reld_r2_qw_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => reld_r2_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(reld_r2_qw_offset to reld_r2_qw_offset + reld_r2_qw_l2'length-1), + scout => sov(reld_r2_qw_offset to reld_r2_qw_offset + reld_r2_qw_l2'length-1), + din => reld_r2_qw_d, + dout => reld_r2_qw_l2); +r2_crit_qw_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(r2_crit_qw_offset), + scout => sov(r2_crit_qw_offset), + din => r2_crit_qw_d, + dout => r2_crit_qw_l2 ); +reld_r3_tid_latch: tri_rlmreg_p + generic map (width => reld_r3_tid_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(reld_r3_tid_offset to reld_r3_tid_offset + reld_r3_tid_l2'length-1), + scout => sov(reld_r3_tid_offset to reld_r3_tid_offset + reld_r3_tid_l2'length-1), + din => reld_r3_tid_d, + dout => reld_r3_tid_l2); +r3_loaded_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(r3_loaded_offset), + scout => sov(r3_loaded_offset), + din => r3_loaded_d, + dout => r3_loaded_l2 ); +r3_need_back_inval_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(r3_need_back_inval_offset), + scout => sov(r3_need_back_inval_offset), + din => r3_need_back_inval_d, + dout => r3_need_back_inval_l2 ); +row_lru_latch: tri_rlmreg_p + generic map (width => row_lru_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(row_lru_offset to row_lru_offset + row_lru_l2'length-1), + scout => sov(row_lru_offset to row_lru_offset + row_lru_l2'length-1), + din => row_lru_d, + dout => row_lru_l2); +row_val_latch: tri_rlmreg_p + generic map (width => row_val_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(row_val_offset to row_val_offset + row_val_l2'length-1), + scout => sov(row_val_offset to row_val_offset + row_val_l2'length-1), + din => row_val_d, + dout => row_val_l2); +an_ac_reld_ecc_err_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(an_ac_reld_ecc_err_offset), + scout => sov(an_ac_reld_ecc_err_offset), + din => an_ac_reld_ecc_err_d, + dout => an_ac_reld_ecc_err_l2 ); +an_ac_reld_ecc_err_ue_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(an_ac_reld_ecc_err_ue_offset), + scout => sov(an_ac_reld_ecc_err_ue_offset), + din => an_ac_reld_ecc_err_ue_d, + dout => an_ac_reld_ecc_err_ue_l2 ); +request_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(request_offset), + scout => sov(request_offset), + din => request_d, + dout => request_l2 ); +req_thread_latch: tri_rlmreg_p + generic map (width => req_thread_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => icd_icm_any_iu2_valid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(req_thread_offset to req_thread_offset + req_thread_l2'length-1), + scout => sov(req_thread_offset to req_thread_offset + req_thread_l2'length-1), + din => req_thread_d, + dout => req_thread_l2); +req_ra_latch: tri_rlmreg_p + generic map (width => req_ra_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => icd_icm_any_iu2_valid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(req_ra_offset to req_ra_offset + req_ra_l2'length-1), + scout => sov(req_ra_offset to req_ra_offset + req_ra_l2'length-1), + din => req_ra_d, + dout => req_ra_l2); +req_wimge_latch: tri_rlmreg_p + generic map (width => req_wimge_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => icd_icm_any_iu2_valid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(req_wimge_offset to req_wimge_offset + req_wimge_l2'length-1), + scout => sov(req_wimge_offset to req_wimge_offset + req_wimge_l2'length-1), + din => req_wimge_d, + dout => req_wimge_l2); +req_userdef_latch: tri_rlmreg_p + generic map (width => req_userdef_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => icd_icm_any_iu2_valid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(req_userdef_offset to req_userdef_offset + req_userdef_l2'length-1), + scout => sov(req_userdef_offset to req_userdef_offset + req_userdef_l2'length-1), + din => req_userdef_d, + dout => req_userdef_l2); +iu3_miss_match_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu3_miss_match_offset), + scout => sov(iu3_miss_match_offset), + din => iu3_miss_match_d, + dout => iu3_miss_match_l2 ); +miss_tid0_sm_a_latch: tri_rlmreg_p + generic map (width => 3, init => 2**(3-1), needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_tid0_sm_offset to miss_tid0_sm_offset + 2), + scout => sov(miss_tid0_sm_offset to miss_tid0_sm_offset + 2), + din => miss_tid0_sm_d(0 to 2), + dout => miss_tid0_sm_l2(0 to 2)); +miss_tid1_sm_a_latch: tri_rlmreg_p + generic map (width => 3, init => 2**(3-1), needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_tid1_sm_offset to miss_tid1_sm_offset + 2), + scout => sov(miss_tid1_sm_offset to miss_tid1_sm_offset + 2), + din => miss_tid1_sm_d(0 to 2), + dout => miss_tid1_sm_l2(0 to 2)); +miss_tid2_sm_a_latch: tri_rlmreg_p + generic map (width => 3, init => 2**(3-1), needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_tid2_sm_offset to miss_tid2_sm_offset + 2), + scout => sov(miss_tid2_sm_offset to miss_tid2_sm_offset + 2), + din => miss_tid2_sm_d(0 to 2), + dout => miss_tid2_sm_l2(0 to 2)); +miss_tid3_sm_a_latch: tri_rlmreg_p + generic map (width => 3, init => 2**(3-1), needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_tid3_sm_offset to miss_tid3_sm_offset + 2), + scout => sov(miss_tid3_sm_offset to miss_tid3_sm_offset + 2), + din => miss_tid3_sm_d(0 to 2), + dout => miss_tid3_sm_l2(0 to 2)); +miss_tid0_sm_b_latch: tri_rlmreg_p + generic map (width => miss_tid0_sm_l2'length-3, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_tid0_sm_offset+3 to miss_tid0_sm_offset + miss_tid0_sm_l2'length-1), + scout => sov(miss_tid0_sm_offset+3 to miss_tid0_sm_offset + miss_tid0_sm_l2'length-1), + din => miss_tid0_sm_d(3 to miss_tid0_sm_l2'length-1), + dout => miss_tid0_sm_l2(3 to miss_tid0_sm_l2'length-1)); +miss_tid1_sm_b_latch: tri_rlmreg_p + generic map (width => miss_tid1_sm_l2'length-3, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_tid1_sm_offset+3 to miss_tid1_sm_offset + miss_tid1_sm_l2'length-1), + scout => sov(miss_tid1_sm_offset+3 to miss_tid1_sm_offset + miss_tid1_sm_l2'length-1), + din => miss_tid1_sm_d(3 to miss_tid1_sm_l2'length-1), + dout => miss_tid1_sm_l2(3 to miss_tid1_sm_l2'length-1)); +miss_tid2_sm_b_latch: tri_rlmreg_p + generic map (width => miss_tid2_sm_l2'length-3, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_tid2_sm_offset+3 to miss_tid2_sm_offset + miss_tid2_sm_l2'length-1), + scout => sov(miss_tid2_sm_offset+3 to miss_tid2_sm_offset + miss_tid2_sm_l2'length-1), + din => miss_tid2_sm_d(3 to miss_tid2_sm_l2'length-1), + dout => miss_tid2_sm_l2(3 to miss_tid2_sm_l2'length-1)); +miss_tid3_sm_b_latch: tri_rlmreg_p + generic map (width => miss_tid3_sm_l2'length-3, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_tid3_sm_offset+3 to miss_tid3_sm_offset + miss_tid3_sm_l2'length-1), + scout => sov(miss_tid3_sm_offset+3 to miss_tid3_sm_offset + miss_tid3_sm_l2'length-1), + din => miss_tid3_sm_d(3 to miss_tid3_sm_l2'length-1), + dout => miss_tid3_sm_l2(3 to miss_tid3_sm_l2'length-1)); +miss_flush_occurred0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_flush_occurred0_offset), + scout => sov(miss_flush_occurred0_offset), + din => miss_flush_occurred0_d, + dout => miss_flush_occurred0_l2 ); +miss_flush_occurred1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_flush_occurred1_offset), + scout => sov(miss_flush_occurred1_offset), + din => miss_flush_occurred1_d, + dout => miss_flush_occurred1_l2 ); +miss_flush_occurred2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_flush_occurred2_offset), + scout => sov(miss_flush_occurred2_offset), + din => miss_flush_occurred2_d, + dout => miss_flush_occurred2_l2 ); +miss_flush_occurred3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_flush_occurred3_offset), + scout => sov(miss_flush_occurred3_offset), + din => miss_flush_occurred3_d, + dout => miss_flush_occurred3_l2 ); +miss_flushed0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_flushed0_offset), + scout => sov(miss_flushed0_offset), + din => miss_flushed0_d, + dout => miss_flushed0_l2 ); +miss_flushed1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_flushed1_offset), + scout => sov(miss_flushed1_offset), + din => miss_flushed1_d, + dout => miss_flushed1_l2 ); +miss_flushed2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_flushed2_offset), + scout => sov(miss_flushed2_offset), + din => miss_flushed2_d, + dout => miss_flushed2_l2 ); +miss_flushed3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_flushed3_offset), + scout => sov(miss_flushed3_offset), + din => miss_flushed3_d, + dout => miss_flushed3_l2 ); +miss_inval0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_inval0_offset), + scout => sov(miss_inval0_offset), + din => miss_inval0_d, + dout => miss_inval0_l2 ); +miss_inval1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_inval1_offset), + scout => sov(miss_inval1_offset), + din => miss_inval1_d, + dout => miss_inval1_l2 ); +miss_inval2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_inval2_offset), + scout => sov(miss_inval2_offset), + din => miss_inval2_d, + dout => miss_inval2_l2 ); +miss_inval3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_inval3_offset), + scout => sov(miss_inval3_offset), + din => miss_inval3_d, + dout => miss_inval3_l2 ); +miss_block_fp0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_block_fp0_offset), + scout => sov(miss_block_fp0_offset), + din => miss_block_fp0_d, + dout => miss_block_fp0_l2 ); +miss_block_fp1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_block_fp1_offset), + scout => sov(miss_block_fp1_offset), + din => miss_block_fp1_d, + dout => miss_block_fp1_l2 ); +miss_block_fp2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_block_fp2_offset), + scout => sov(miss_block_fp2_offset), + din => miss_block_fp2_d, + dout => miss_block_fp2_l2 ); +miss_block_fp3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_block_fp3_offset), + scout => sov(miss_block_fp3_offset), + din => miss_block_fp3_d, + dout => miss_block_fp3_l2 ); +miss_ecc_err0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_ecc_err0_offset), + scout => sov(miss_ecc_err0_offset), + din => miss_ecc_err0_d, + dout => miss_ecc_err0_l2 ); +miss_ecc_err1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_ecc_err1_offset), + scout => sov(miss_ecc_err1_offset), + din => miss_ecc_err1_d, + dout => miss_ecc_err1_l2 ); +miss_ecc_err2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_ecc_err2_offset), + scout => sov(miss_ecc_err2_offset), + din => miss_ecc_err2_d, + dout => miss_ecc_err2_l2 ); +miss_ecc_err3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_ecc_err3_offset), + scout => sov(miss_ecc_err3_offset), + din => miss_ecc_err3_d, + dout => miss_ecc_err3_l2 ); +miss_ecc_err_ue0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_ecc_err_ue0_offset), + scout => sov(miss_ecc_err_ue0_offset), + din => miss_ecc_err_ue0_d, + dout => miss_ecc_err_ue0_l2 ); +miss_ecc_err_ue1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_ecc_err_ue1_offset), + scout => sov(miss_ecc_err_ue1_offset), + din => miss_ecc_err_ue1_d, + dout => miss_ecc_err_ue1_l2 ); +miss_ecc_err_ue2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_ecc_err_ue2_offset), + scout => sov(miss_ecc_err_ue2_offset), + din => miss_ecc_err_ue2_d, + dout => miss_ecc_err_ue2_l2 ); +miss_ecc_err_ue3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_ecc_err_ue3_offset), + scout => sov(miss_ecc_err_ue3_offset), + din => miss_ecc_err_ue3_d, + dout => miss_ecc_err_ue3_l2 ); +miss_wrote_dir0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_wrote_dir0_offset), + scout => sov(miss_wrote_dir0_offset), + din => miss_wrote_dir0_d, + dout => miss_wrote_dir0_l2 ); +miss_wrote_dir1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_wrote_dir1_offset), + scout => sov(miss_wrote_dir1_offset), + din => miss_wrote_dir1_d, + dout => miss_wrote_dir1_l2 ); +miss_wrote_dir2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_wrote_dir2_offset), + scout => sov(miss_wrote_dir2_offset), + din => miss_wrote_dir2_d, + dout => miss_wrote_dir2_l2 ); +miss_wrote_dir3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_wrote_dir3_offset), + scout => sov(miss_wrote_dir3_offset), + din => miss_wrote_dir3_d, + dout => miss_wrote_dir3_l2 ); +miss_need_hold0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_need_hold0_offset), + scout => sov(miss_need_hold0_offset), + din => miss_need_hold0_d, + dout => miss_need_hold0_l2 ); +miss_need_hold1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_need_hold1_offset), + scout => sov(miss_need_hold1_offset), + din => miss_need_hold1_d, + dout => miss_need_hold1_l2 ); +miss_need_hold2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_need_hold2_offset), + scout => sov(miss_need_hold2_offset), + din => miss_need_hold2_d, + dout => miss_need_hold2_l2 ); +miss_need_hold3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_need_hold3_offset), + scout => sov(miss_need_hold3_offset), + din => miss_need_hold3_d, + dout => miss_need_hold3_l2 ); +miss_addr0_real_latch: tri_rlmreg_p + generic map (width => miss_addr0_real_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => miss_act(0), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_addr0_real_offset to miss_addr0_real_offset + miss_addr0_real_l2'length-1), + scout => sov(miss_addr0_real_offset to miss_addr0_real_offset + miss_addr0_real_l2'length-1), + din => miss_addr0_real_d, + dout => miss_addr0_real_l2); +miss_addr1_real_latch: tri_rlmreg_p + generic map (width => miss_addr1_real_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => miss_act(1), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_addr1_real_offset to miss_addr1_real_offset + miss_addr1_real_l2'length-1), + scout => sov(miss_addr1_real_offset to miss_addr1_real_offset + miss_addr1_real_l2'length-1), + din => miss_addr1_real_d, + dout => miss_addr1_real_l2); +miss_addr2_real_latch: tri_rlmreg_p + generic map (width => miss_addr2_real_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => miss_act(2), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_addr2_real_offset to miss_addr2_real_offset + miss_addr2_real_l2'length-1), + scout => sov(miss_addr2_real_offset to miss_addr2_real_offset + miss_addr2_real_l2'length-1), + din => miss_addr2_real_d, + dout => miss_addr2_real_l2); +miss_addr3_real_latch: tri_rlmreg_p + generic map (width => miss_addr3_real_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => miss_act(3), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_addr3_real_offset to miss_addr3_real_offset + miss_addr3_real_l2'length-1), + scout => sov(miss_addr3_real_offset to miss_addr3_real_offset + miss_addr3_real_l2'length-1), + din => miss_addr3_real_d, + dout => miss_addr3_real_l2); +miss_addr0_eff_latch: tri_rlmreg_p + generic map (width => miss_addr0_eff_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => miss_act(0), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_addr0_eff_offset to miss_addr0_eff_offset + miss_addr0_eff_l2'length-1), + scout => sov(miss_addr0_eff_offset to miss_addr0_eff_offset + miss_addr0_eff_l2'length-1), + din => miss_addr0_eff_d, + dout => miss_addr0_eff_l2); +miss_addr1_eff_latch: tri_rlmreg_p + generic map (width => miss_addr1_eff_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => miss_act(1), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_addr1_eff_offset to miss_addr1_eff_offset + miss_addr1_eff_l2'length-1), + scout => sov(miss_addr1_eff_offset to miss_addr1_eff_offset + miss_addr1_eff_l2'length-1), + din => miss_addr1_eff_d, + dout => miss_addr1_eff_l2); +miss_addr2_eff_latch: tri_rlmreg_p + generic map (width => miss_addr2_eff_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => miss_act(2), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_addr2_eff_offset to miss_addr2_eff_offset + miss_addr2_eff_l2'length-1), + scout => sov(miss_addr2_eff_offset to miss_addr2_eff_offset + miss_addr2_eff_l2'length-1), + din => miss_addr2_eff_d, + dout => miss_addr2_eff_l2); +miss_addr3_eff_latch: tri_rlmreg_p + generic map (width => miss_addr3_eff_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => miss_act(3), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_addr3_eff_offset to miss_addr3_eff_offset + miss_addr3_eff_l2'length-1), + scout => sov(miss_addr3_eff_offset to miss_addr3_eff_offset + miss_addr3_eff_l2'length-1), + din => miss_addr3_eff_d, + dout => miss_addr3_eff_l2); +miss_ci0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => miss_act(0), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_ci0_offset), + scout => sov(miss_ci0_offset), + din => miss_ci0_d, + dout => miss_ci0_l2 ); +miss_ci1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => miss_act(1), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_ci1_offset), + scout => sov(miss_ci1_offset), + din => miss_ci1_d, + dout => miss_ci1_l2 ); +miss_ci2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => miss_act(2), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_ci2_offset), + scout => sov(miss_ci2_offset), + din => miss_ci2_d, + dout => miss_ci2_l2 ); +miss_ci3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => miss_act(3), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_ci3_offset), + scout => sov(miss_ci3_offset), + din => miss_ci3_d, + dout => miss_ci3_l2 ); +miss_endian0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => miss_act(0), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_endian0_offset), + scout => sov(miss_endian0_offset), + din => miss_endian0_d, + dout => miss_endian0_l2 ); +miss_endian1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => miss_act(1), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_endian1_offset), + scout => sov(miss_endian1_offset), + din => miss_endian1_d, + dout => miss_endian1_l2 ); +miss_endian2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => miss_act(2), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_endian2_offset), + scout => sov(miss_endian2_offset), + din => miss_endian2_d, + dout => miss_endian2_l2 ); +miss_endian3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => miss_act(3), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_endian3_offset), + scout => sov(miss_endian3_offset), + din => miss_endian3_d, + dout => miss_endian3_l2 ); +miss_2ucode0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => miss_act(0), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_2ucode0_offset), + scout => sov(miss_2ucode0_offset), + din => miss_2ucode0_d, + dout => miss_2ucode0_l2 ); +miss_2ucode1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => miss_act(1), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_2ucode1_offset), + scout => sov(miss_2ucode1_offset), + din => miss_2ucode1_d, + dout => miss_2ucode1_l2 ); +miss_2ucode2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => miss_act(2), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_2ucode2_offset), + scout => sov(miss_2ucode2_offset), + din => miss_2ucode2_d, + dout => miss_2ucode2_l2 ); +miss_2ucode3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => miss_act(3), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_2ucode3_offset), + scout => sov(miss_2ucode3_offset), + din => miss_2ucode3_d, + dout => miss_2ucode3_l2 ); +miss_2ucode0_type_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => miss_act(0), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_2ucode0_type_offset), + scout => sov(miss_2ucode0_type_offset), + din => miss_2ucode0_type_d, + dout => miss_2ucode0_type_l2 ); +miss_2ucode1_type_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => miss_act(1), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_2ucode1_type_offset), + scout => sov(miss_2ucode1_type_offset), + din => miss_2ucode1_type_d, + dout => miss_2ucode1_type_l2 ); +miss_2ucode2_type_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => miss_act(2), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_2ucode2_type_offset), + scout => sov(miss_2ucode2_type_offset), + din => miss_2ucode2_type_d, + dout => miss_2ucode2_type_l2 ); +miss_2ucode3_type_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => miss_act(3), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_2ucode3_type_offset), + scout => sov(miss_2ucode3_type_offset), + din => miss_2ucode3_type_d, + dout => miss_2ucode3_type_l2 ); +miss_way0_latch: tri_rlmreg_p + generic map (width => miss_way0_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => reld_r2_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_way0_offset to miss_way0_offset + miss_way0_l2'length-1), + scout => sov(miss_way0_offset to miss_way0_offset + miss_way0_l2'length-1), + din => miss_way0_d, + dout => miss_way0_l2); +miss_way1_latch: tri_rlmreg_p + generic map (width => miss_way1_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => reld_r2_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_way1_offset to miss_way1_offset + miss_way1_l2'length-1), + scout => sov(miss_way1_offset to miss_way1_offset + miss_way1_l2'length-1), + din => miss_way1_d, + dout => miss_way1_l2); +miss_way2_latch: tri_rlmreg_p + generic map (width => miss_way2_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => reld_r2_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_way2_offset to miss_way2_offset + miss_way2_l2'length-1), + scout => sov(miss_way2_offset to miss_way2_offset + miss_way2_l2'length-1), + din => miss_way2_d, + dout => miss_way2_l2); +miss_way3_latch: tri_rlmreg_p + generic map (width => miss_way3_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => reld_r2_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_way3_offset to miss_way3_offset + miss_way3_l2'length-1), + scout => sov(miss_way3_offset to miss_way3_offset + miss_way3_l2'length-1), + din => miss_way3_d, + dout => miss_way3_l2); +perf_event_t0_latch: tri_rlmreg_p + generic map (width => perf_event_t0_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => event_bus_enable, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(perf_event_t0_offset to perf_event_t0_offset + perf_event_t0_l2'length-1), + scout => sov(perf_event_t0_offset to perf_event_t0_offset + perf_event_t0_l2'length-1), + din => perf_event_t0_d, + dout => perf_event_t0_l2); +perf_event_t1_latch: tri_rlmreg_p + generic map (width => perf_event_t1_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => event_bus_enable, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(perf_event_t1_offset to perf_event_t1_offset + perf_event_t1_l2'length-1), + scout => sov(perf_event_t1_offset to perf_event_t1_offset + perf_event_t1_l2'length-1), + din => perf_event_t1_d, + dout => perf_event_t1_l2); +perf_event_t2_latch: tri_rlmreg_p + generic map (width => perf_event_t2_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => event_bus_enable, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(perf_event_t2_offset to perf_event_t2_offset + perf_event_t2_l2'length-1), + scout => sov(perf_event_t2_offset to perf_event_t2_offset + perf_event_t2_l2'length-1), + din => perf_event_t2_d, + dout => perf_event_t2_l2); +perf_event_t3_latch: tri_rlmreg_p + generic map (width => perf_event_t3_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => event_bus_enable, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(perf_event_t3_offset to perf_event_t3_offset + perf_event_t3_l2'length-1), + scout => sov(perf_event_t3_offset to perf_event_t3_offset + perf_event_t3_l2'length-1), + din => perf_event_t3_d, + dout => perf_event_t3_l2); +lru_write_next_cycle_latch: tri_rlmreg_p + generic map (width => lru_write_next_cycle_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(lru_write_next_cycle_offset to lru_write_next_cycle_offset + lru_write_next_cycle_l2'length-1), + scout => sov(lru_write_next_cycle_offset to lru_write_next_cycle_offset + lru_write_next_cycle_l2'length-1), + din => lru_write_next_cycle_d, + dout => lru_write_next_cycle_l2); +lru_write_latch: tri_rlmreg_p + generic map (width => lru_write_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => default_reld_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(lru_write_offset to lru_write_offset + lru_write_l2'length-1), + scout => sov(lru_write_offset to lru_write_offset + lru_write_l2'length-1), + din => lru_write_d, + dout => lru_write_l2); +miss_dbg_data1_latch: tri_rlmreg_p + generic map (width => miss_dbg_data1_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => trace_bus_enable, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(miss_dbg_data1_offset to miss_dbg_data1_offset + miss_dbg_data1_l2'length-1), + scout => sov(miss_dbg_data1_offset to miss_dbg_data1_offset + miss_dbg_data1_l2'length-1), + din => miss_dbg_data1_d, + dout => miss_dbg_data1_l2); +spare_latch: tri_rlmreg_p + generic map (width => spare_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(spare_offset to spare_offset + spare_l2'length-1), + scout => sov(spare_offset to spare_offset + spare_l2'length-1), + din => spare_l2, + dout => spare_l2); +----------------------------------------------------------------------- +-- Scan +----------------------------------------------------------------------- +siv(0 TO scan_right) <= sov(1 to scan_right) & scan_in; +scan_out <= sov(0); +END IUQ_IC_MISS; diff --git a/rel/src/vhdl/work/iuq_ic_select.vhdl b/rel/src/vhdl/work/iuq_ic_select.vhdl new file mode 100644 index 0000000..e55726c --- /dev/null +++ b/rel/src/vhdl/work/iuq_ic_select.vhdl @@ -0,0 +1,2072 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +--******************************************************************** +--* +--* TITLE: Instruction Select +--* +--* NAME: iuq_ic_select.vhdl +--* +--********************************************************************* +library ieee,ibm,support,tri,work; +use ieee.std_logic_1164.all; +use ibm.std_ulogic_unsigned.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use support.power_logic_pkg.all; +use tri.tri_latches_pkg.all; +use work.iuq_pkg.all; + +entity iuq_ic_select is +generic(expand_type : integer := 2); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + pc_iu_func_sl_thold_0_b : in std_ulogic; + pc_iu_func_slp_sl_thold_0_b: in std_ulogic; + pc_iu_sg_0 : in std_ulogic; + forcee : in std_ulogic; + funcslp_force : in std_ulogic; + d_mode : in std_ulogic; + delay_lclkr : in std_ulogic; + mpw1_b : in std_ulogic; + mpw2_b : in std_ulogic; + an_ac_scan_dis_dc_b : in std_ulogic; + func_scan_in : in std_ulogic; + func_scan_out : out std_ulogic; + + ac_an_power_managed : in std_ulogic; + + xu_iu_run_thread : in std_ulogic_vector(0 to 3); + + xu_iu_flush : in std_ulogic_vector(0 to 3); + xu_iu_iu0_flush_ifar0 : in EFF_IFAR; + xu_iu_iu0_flush_ifar1 : in EFF_IFAR; + xu_iu_iu0_flush_ifar2 : in EFF_IFAR; + xu_iu_iu0_flush_ifar3 : in EFF_IFAR; + xu_iu_flush_2ucode : in std_ulogic_vector(0 to 3); + xu_iu_flush_2ucode_type : in std_ulogic_vector(0 to 3); + + xu_iu_msr_cm : in std_ulogic_vector(0 to 3); + + xu_iu_ex6_icbi_val : in std_ulogic_vector(0 to 3); + xu_iu_ex6_icbi_addr : in std_ulogic_vector(REAL_IFAR'left to 57); + + an_ac_back_inv : in std_ulogic; + an_ac_back_inv_addr : in std_ulogic_vector(REAL_IFAR'left to 57); + an_ac_back_inv_target : in std_ulogic; + + an_ac_icbi_ack : in std_ulogic; + an_ac_icbi_ack_thread : in std_ulogic_vector(0 to 1); + + spr_ic_clockgate_dis : in std_ulogic; + spr_ic_icbi_ack_en : in std_ulogic; + + spr_ic_idir_read : in std_ulogic; + spr_ic_idir_row : in std_ulogic_vector(52 to 57); + + spr_ic_pri_rand : in std_ulogic_vector(0 to 4); + spr_ic_pri_rand_always : in std_ulogic; + spr_ic_pri_rand_flush : in std_ulogic; + + ic_perf_event_t0 : out std_ulogic_vector(2 to 3); + ic_perf_event_t1 : out std_ulogic_vector(2 to 3); + ic_perf_event_t2 : out std_ulogic_vector(2 to 3); + ic_perf_event_t3 : out std_ulogic_vector(2 to 3); + + iu_ierat_iu0_val : out std_ulogic; + iu_ierat_iu0_thdid : out std_ulogic_vector(0 to 3); + iu_ierat_iu0_ifar : out std_ulogic_vector(0 to 51); + iu_ierat_iu0_flush : out std_ulogic_vector(0 to 3); + iu_ierat_iu1_flush : out std_ulogic_vector(0 to 3); + iu_ierat_ium1_back_inv : out std_ulogic; + ierat_iu_hold_req : in std_ulogic_vector(0 to 3); + ierat_iu_iu2_flush_req : in std_ulogic_vector(0 to 3); + ierat_iu_iu2_miss : in std_ulogic; + + icm_ics_iu0_preload_val : in std_ulogic; + icm_ics_iu0_preload_tid : in std_ulogic_vector(0 to 3); + icm_ics_iu0_preload_ifar : in std_ulogic_vector(52 to 59); + + icm_ics_hold_thread : in std_ulogic_vector(0 to 3); + icm_ics_hold_thread_dbg : in std_ulogic_vector(0 to 3); + icm_ics_hold_iu0 : in std_ulogic; + icm_ics_ecc_block_iu0 : in std_ulogic_vector(0 to 3); + icm_ics_load_tid : in std_ulogic_vector(0 to 3); + icm_ics_iu1_ecc_flush : in std_ulogic; + icm_ics_iu2_miss_match_prev: in std_ulogic; + + ics_icm_iu2_flush_tid : out std_ulogic_vector(0 to 3); + ics_icm_iu3_flush_tid : out std_ulogic_vector(0 to 3); + + ics_icm_iu0_ifar0 : out std_ulogic_vector(46 to 52); + ics_icm_iu0_ifar1 : out std_ulogic_vector(46 to 52); + ics_icm_iu0_ifar2 : out std_ulogic_vector(46 to 52); + ics_icm_iu0_ifar3 : out std_ulogic_vector(46 to 52); + + ics_icm_iu0_inval : out std_ulogic; + ics_icm_iu0_inval_addr : out std_ulogic_vector(52 to 57); + + ics_icd_dir_rd_act : out std_ulogic; + ics_icd_data_rd_act : out std_ulogic; + ics_icd_iu0_valid : out std_ulogic; + ics_icd_iu0_tid : out std_ulogic_vector(0 to 3); + ics_icd_iu0_ifar : out EFF_IFAR; + ics_icd_iu0_inval : out std_ulogic; + ics_icd_iu0_2ucode : out std_ulogic; + ics_icd_iu0_2ucode_type : out std_ulogic; + ics_icd_iu0_spr_idir_read : out std_ulogic; + + icd_ics_iu1_valid : in std_ulogic; + icd_ics_iu1_tid : in std_ulogic_vector(0 to 3); + icd_ics_iu1_ifar : in EFF_IFAR; + icd_ics_iu1_2ucode : in std_ulogic; + icd_ics_iu1_2ucode_type : in std_ulogic; + + ics_icd_all_flush_prev : out std_ulogic_vector(0 to 3); + ics_icd_iu1_flush_tid : out std_ulogic_vector(0 to 3); + ics_icd_iu2_flush_tid : out std_ulogic_vector(0 to 3); + icd_ics_iu2_miss_flush_prev: in std_ulogic_vector(0 to 3); + icd_ics_iu2_ifar_eff : in EFF_IFAR; + icd_ics_iu2_2ucode : in std_ulogic; + icd_ics_iu2_2ucode_type : in std_ulogic; + icd_ics_iu3_parity_flush : in std_ulogic_vector(0 to 3); + icd_ics_iu3_ifar : in EFF_IFAR; + icd_ics_iu3_2ucode : in std_ulogic; + icd_ics_iu3_2ucode_type : in std_ulogic; + + ic_bp_iu1_val : out std_ulogic; + ic_bp_iu1_tid : out std_ulogic_vector(0 to 3); + ic_bp_iu1_ifar : out std_ulogic_vector(52 to 59); + + bp_ib_iu4_ifar : in EFF_IFAR; + + bp_ic_iu5_hold_tid : in std_ulogic_vector(0 to 3); + bp_ic_iu5_redirect_tid : in std_ulogic_vector(0 to 3); + bp_ic_iu5_redirect_ifar : in EFF_IFAR; + + ib_ic_empty : in std_ulogic_vector(0 to 3); + ib_ic_below_water : in std_ulogic_vector(0 to 3); + ib_ic_iu5_redirect_tid : in std_ulogic_vector(0 to 3); + + ic_fdep_icbi_ack : out std_ulogic_vector(0 to 3); + + uc_flush_tid : in std_ulogic_vector(0 to 3); + uc_ic_hold_thread : in std_ulogic_vector(0 to 3); + + event_bus_enable : in std_ulogic; + sel_dbg_data : out std_ulogic_vector(0 to 87) +); +-- synopsys translate_off +-- synopsys translate_on +end iuq_ic_select; +ARCHITECTURE IUQ_IC_SELECT + OF IUQ_IC_SELECT + IS +constant an_ac_back_inv_offset : natural := 0; +constant an_ac_back_inv_target_offset : natural := an_ac_back_inv_offset + 1; +constant an_ac_back_inv_addr_offset : natural := an_ac_back_inv_target_offset + 1; +constant back_inv_offset : natural := an_ac_back_inv_addr_offset + REAL_IFAR'length - 4; +constant back_inv_clone_offset : natural := back_inv_offset + 1; +constant an_ac_icbi_ack_offset : natural := back_inv_clone_offset + 1; +constant an_ac_icbi_ack_thread_offset : natural := an_ac_icbi_ack_offset + 1; +constant xu_icbi_buffer0_val_tid_offset : natural := an_ac_icbi_ack_thread_offset + 2; +constant xu_icbi_buffer0_addr_offset : natural := xu_icbi_buffer0_val_tid_offset + 4; +constant xu_icbi_buffer1_val_tid_offset : natural := xu_icbi_buffer0_addr_offset + REAL_IFAR'length - 4; +constant xu_icbi_buffer1_addr_offset : natural := xu_icbi_buffer1_val_tid_offset + 4; +constant xu_icbi_buffer2_val_tid_offset : natural := xu_icbi_buffer1_addr_offset + REAL_IFAR'length - 4; +constant xu_icbi_buffer2_addr_offset : natural := xu_icbi_buffer2_val_tid_offset + 4; +constant xu_icbi_buffer3_val_tid_offset : natural := xu_icbi_buffer2_addr_offset + REAL_IFAR'length - 4; +constant xu_icbi_buffer3_addr_offset : natural := xu_icbi_buffer3_val_tid_offset + 4; +constant xu_iu_run_thread_offset : natural := xu_icbi_buffer3_addr_offset + REAL_IFAR'length - 4; +constant all_stages_flush_prev_offset : natural := xu_iu_run_thread_offset + 4; +constant spare_offset : natural := all_stages_flush_prev_offset + 4; +constant iu0_ifar0_offset : natural := spare_offset + 12; +constant iu0_ifar1_offset : natural := iu0_ifar0_offset + EFF_IFAR'length; +constant iu0_ifar2_offset : natural := iu0_ifar1_offset + EFF_IFAR'length; +constant iu0_ifar3_offset : natural := iu0_ifar2_offset + EFF_IFAR'length; +constant iu0_2ucode_offset : natural := iu0_ifar3_offset + EFF_IFAR'length; +constant iu0_2ucode_type_offset : natural := iu0_2ucode_offset + 4; +constant iu0_high_sent1_offset : natural := iu0_2ucode_type_offset + 4; +constant iu0_high_sent2_offset : natural := iu0_high_sent1_offset + 4; +constant iu0_high_sent3_offset : natural := iu0_high_sent2_offset + 4; +constant iu0_high_sent4_offset : natural := iu0_high_sent3_offset + 4; +constant high_mask_offset : natural := iu0_high_sent4_offset + 4; +constant iu0_low_sent1_offset : natural := high_mask_offset + 4; +constant iu0_low_sent2_offset : natural := iu0_low_sent1_offset + 4; +constant iu0_low_sent3_offset : natural := iu0_low_sent2_offset + 4; +constant iu0_low_sent4_offset : natural := iu0_low_sent3_offset + 4; +constant low_mask_offset : natural := iu0_low_sent4_offset + 4; +constant iu1_bp_val_offset : natural := low_mask_offset + 4; +constant iu1_bp_ifar_offset : natural := iu1_bp_val_offset + 1; +constant iu5_ifar_offset : natural := iu1_bp_ifar_offset + 8; +constant perf_event_t0_offset : natural := iu5_ifar_offset + EFF_IFAR'length; +constant perf_event_t1_offset : natural := perf_event_t0_offset + 2; +constant perf_event_t2_offset : natural := perf_event_t1_offset + 2; +constant perf_event_t3_offset : natural := perf_event_t2_offset + 2; +constant pri_took_offset : natural := perf_event_t3_offset + 2; +constant spr_ic_icbi_ack_en_offset : natural := pri_took_offset + 12; +constant spr_idir_read_offset : natural := spr_ic_icbi_ack_en_offset + 1; +constant spr_idir_row_offset : natural := spr_idir_read_offset + 1; +constant xu_iu_flush_offset : natural := spr_idir_row_offset + 6; +constant scan_right : natural := xu_iu_flush_offset + 4 - 1; +subtype s3 is std_ulogic_vector(0 to 2); +signal tiup : std_ulogic; +-- Latches +signal an_ac_back_inv_d : std_ulogic; +signal an_ac_back_inv_l2 : std_ulogic; +signal an_ac_back_inv_target_d : std_ulogic; +signal an_ac_back_inv_target_l2 : std_ulogic; +signal an_ac_back_inv_addr_d : std_ulogic_vector(REAL_IFAR'left to 57); +signal an_ac_back_inv_addr_l2 : std_ulogic_vector(REAL_IFAR'left to 57); +signal back_inv_d : std_ulogic; +signal back_inv_l2 : std_ulogic; +signal back_inv_l2_clone : std_ulogic; +signal an_ac_icbi_ack_d : std_ulogic; +signal an_ac_icbi_ack_l2 : std_ulogic; +signal an_ac_icbi_ack_thread_d : std_ulogic_vector(0 to 1); +signal an_ac_icbi_ack_thread_l2 : std_ulogic_vector(0 to 1); +signal xu_icbi_buffer0_val_tid_d : std_ulogic_vector(0 to 3); +signal xu_icbi_buffer0_val_tid_l2 : std_ulogic_vector(0 to 3); +signal xu_icbi_buffer1_val_tid_d : std_ulogic_vector(0 to 3); +signal xu_icbi_buffer1_val_tid_l2 : std_ulogic_vector(0 to 3); +signal xu_icbi_buffer2_val_tid_d : std_ulogic_vector(0 to 3); +signal xu_icbi_buffer2_val_tid_l2 : std_ulogic_vector(0 to 3); +signal xu_icbi_buffer3_val_tid_d : std_ulogic_vector(0 to 3); +signal xu_icbi_buffer3_val_tid_l2 : std_ulogic_vector(0 to 3); +signal xu_icbi_buffer0_addr_d : std_ulogic_vector(REAL_IFAR'left to 57); +signal xu_icbi_buffer0_addr_l2 : std_ulogic_vector(REAL_IFAR'left to 57); +signal xu_icbi_buffer1_addr_d : std_ulogic_vector(REAL_IFAR'left to 57); +signal xu_icbi_buffer1_addr_l2 : std_ulogic_vector(REAL_IFAR'left to 57); +signal xu_icbi_buffer2_addr_d : std_ulogic_vector(REAL_IFAR'left to 57); +signal xu_icbi_buffer2_addr_l2 : std_ulogic_vector(REAL_IFAR'left to 57); +signal xu_icbi_buffer3_addr_d : std_ulogic_vector(REAL_IFAR'left to 57); +signal xu_icbi_buffer3_addr_l2 : std_ulogic_vector(REAL_IFAR'left to 57); +signal xu_iu_run_thread_d : std_ulogic_vector(0 to 3); +signal xu_iu_run_thread_l2 : std_ulogic_vector(0 to 3); +signal iu5_ifar_d : EFF_IFAR; +signal iu5_ifar_l2 : EFF_IFAR; +signal all_stages_flush_prev_d : std_ulogic_vector(0 to 3); +signal all_stages_flush_prev_l2 : std_ulogic_vector(0 to 3); +-- Current IFARs for each of the threads +signal iu0_ifar0_d : EFF_IFAR; +signal iu0_ifar0_l2 : EFF_IFAR; +signal iu0_ifar1_d : EFF_IFAR; +signal iu0_ifar1_l2 : EFF_IFAR; +signal iu0_ifar2_d : EFF_IFAR; +signal iu0_ifar2_l2 : EFF_IFAR; +signal iu0_ifar3_d : EFF_IFAR; +signal iu0_ifar3_l2 : EFF_IFAR; +signal iu0_2ucode_d : std_ulogic_vector(0 to 3); +signal iu0_2ucode_l2 : std_ulogic_vector(0 to 3); +signal iu0_2ucode_type_d : std_ulogic_vector(0 to 3); +signal iu0_2ucode_type_l2 : std_ulogic_vector(0 to 3); +-- Used to keep track of the commands in flight to IB +signal iu0_high_sent1_d : std_ulogic_vector(0 to 3); +signal iu0_high_sent1_l2 : std_ulogic_vector(0 to 3); +signal iu0_low_sent1_d : std_ulogic_vector(0 to 3); +signal iu0_low_sent1_l2 : std_ulogic_vector(0 to 3); +signal iu0_high_sent2_d : std_ulogic_vector(0 to 3); +signal iu0_high_sent2_l2 : std_ulogic_vector(0 to 3); +signal iu0_low_sent2_d : std_ulogic_vector(0 to 3); +signal iu0_low_sent2_l2 : std_ulogic_vector(0 to 3); +signal iu0_high_sent3_d : std_ulogic_vector(0 to 3); +signal iu0_high_sent3_l2 : std_ulogic_vector(0 to 3); +signal iu0_low_sent3_d : std_ulogic_vector(0 to 3); +signal iu0_low_sent3_l2 : std_ulogic_vector(0 to 3); +signal iu0_high_sent4_d : std_ulogic_vector(0 to 3); +signal iu0_high_sent4_l2 : std_ulogic_vector(0 to 3); +signal iu0_low_sent4_d : std_ulogic_vector(0 to 3); +signal iu0_low_sent4_l2 : std_ulogic_vector(0 to 3); +signal high_mask_d : std_ulogic_vector(0 to 3); +signal high_mask_l2 : std_ulogic_vector(0 to 3); +signal low_mask_d : std_ulogic_vector(0 to 3); +signal low_mask_l2 : std_ulogic_vector(0 to 3); +-- Latches for BP output +signal iu1_bp_val_d : std_ulogic; +signal iu1_bp_val_l2 : std_ulogic; +signal iu1_bp_tid_d : std_ulogic_vector(0 to 3); +signal iu1_bp_ifar_d : std_ulogic_vector(52 to 59); +signal iu1_bp_ifar_l2 : std_ulogic_vector(52 to 59); +signal perf_event_t0_d : std_ulogic_vector(2 to 3); +signal perf_event_t0_l2 : std_ulogic_vector(2 to 3); +signal perf_event_t1_d : std_ulogic_vector(2 to 3); +signal perf_event_t1_l2 : std_ulogic_vector(2 to 3); +signal perf_event_t2_d : std_ulogic_vector(2 to 3); +signal perf_event_t2_l2 : std_ulogic_vector(2 to 3); +signal perf_event_t3_d : std_ulogic_vector(2 to 3); +signal perf_event_t3_l2 : std_ulogic_vector(2 to 3); +signal spr_ic_icbi_ack_en_l2 : std_ulogic; +signal spr_idir_read_d : std_ulogic; +signal spr_idir_read_l2 : std_ulogic; +signal spr_idir_row_d : std_ulogic_vector(52 to 57); +signal spr_idir_row_l2 : std_ulogic_vector(52 to 57); +signal xu_iu_flush_l2 : std_ulogic_vector(0 to 3); +signal spare_l2 : std_ulogic_vector(0 to 11); +signal back_inv : std_ulogic; +signal iu5_act : std_ulogic; +signal iu0_high_act : std_ulogic; +signal iu0_low_act : std_ulogic; +-- XU ICBI Buffers +signal xu_icbi_buffer0_act : std_ulogic; +signal xu_icbi_buffer123_act : std_ulogic; +signal xu_icbi_buffer_val : std_ulogic_vector(0 to 3); +signal l2_icbi_ack : std_ulogic_vector(0 to 3); +signal block_spr_idir_read : std_ulogic; +signal iu0_spr_idir_read : std_ulogic; +-- IU0 +signal iu1_icm_flush_tid : std_ulogic_vector(0 to 3); +signal hold_iu0_v : std_ulogic_vector(0 to 3); +signal iu0_hold_ecc : std_ulogic; +signal iu0_hold_ecc_v : std_ulogic_vector(0 to 3); +signal all_stages_flush_tid : std_ulogic_vector(0 to 3); +signal iu0_flush_tid : std_ulogic_vector(0 to 3); +signal iu1_flush_tid : std_ulogic_vector(0 to 3); +signal iu2_flush_tid : std_ulogic_vector(0 to 3); +signal iu3_flush_tid : std_ulogic_vector(0 to 3); +signal hold_thread_pre_iu0 : std_ulogic_vector(0 to 3); +signal hold_thread_iu0 : std_ulogic_vector(0 to 3); +signal next_high_valid : std_ulogic; +signal next_low_valid : std_ulogic; +signal next_tid : std_ulogic_vector(0 to 3); +signal iu0_ifar0_early : EFF_IFAR; +signal iu0_ifar1_early : EFF_IFAR; +signal iu0_ifar2_early : EFF_IFAR; +signal iu0_ifar3_early : EFF_IFAR; +signal iu0_ifar0_pre_cm : EFF_IFAR; +signal iu0_ifar1_pre_cm : EFF_IFAR; +signal iu0_ifar2_pre_cm : EFF_IFAR; +signal iu0_ifar3_pre_cm : EFF_IFAR; +signal iu0_2ucode_early : std_ulogic_vector(0 to 3); +signal iu0_2ucode_type_early : std_ulogic_vector(0 to 3); +signal iu0_early_valid : std_ulogic; +signal iu0_valid : std_ulogic; +signal iu0_high_sentall4 : std_ulogic_vector(0 to 3); +signal iu0_low_sentall4 : std_ulogic_vector(0 to 3); +signal back_inv_addr_ext : std_ulogic_vector(EFF_IFAR'left to 57); +signal xu_icbi_addr_ext : std_ulogic_vector(EFF_IFAR'left to 57); +signal iu0_inval : std_ulogic; +signal iu0_ifar0_or_back_inv_addr: EFF_IFAR; +signal select_iu0_ifar0 : std_ulogic; +signal iu0_ifar : EFF_IFAR; +signal iu0_2ucode : std_ulogic; +signal iu0_2ucode_type : std_ulogic; +signal iu1_bp_act : std_ulogic; +-- scan +signal siv : std_ulogic_vector(0 to scan_right); +signal sov : std_ulogic_vector(0 to scan_right); +-- synopsys translate_off +-- synopsys translate_on +signal hi_did3no0_d : std_ulogic; +signal hi_did3no1_d : std_ulogic; +signal hi_did3no2_d : std_ulogic; +signal hi_did2no0_d : std_ulogic; +signal hi_did2no1_d : std_ulogic; +signal hi_did1no0_d : std_ulogic; +signal md_did3no0_d : std_ulogic; +signal md_did3no1_d : std_ulogic; +signal md_did3no2_d : std_ulogic; +signal md_did2no0_d : std_ulogic; +signal md_did2no1_d : std_ulogic; +signal md_did1no0_d : std_ulogic; +--priority map signals +signal hi_n230, hi_n231, hi_n232 : std_ulogic; +signal hi_n220, hi_n221, hi_n210 : std_ulogic; +signal md_n230, md_n231, md_n232 : std_ulogic; +signal md_n220, md_n221, md_n210 : std_ulogic; +signal medpri_v, medpri_v_b, highpri_v, highpri_v_b : std_ulogic_vector(0 to 3); +signal medpri_v_b0, highpri_v_b0 : std_ulogic_vector(0 to 3); +signal hi_did0no1, hi_did0no2, hi_did0no3 : std_ulogic; +signal hi_did1no0, hi_did1no2, hi_did1no3 : std_ulogic; +signal hi_did2no1, hi_did2no0, hi_did2no3 : std_ulogic; +signal hi_did3no1, hi_did3no2, hi_did3no0 : std_ulogic; +signal md_did0no1, md_did0no2, md_did0no3 : std_ulogic; +signal md_did1no0, md_did1no2, md_did1no3 : std_ulogic; +signal md_did2no1, md_did2no0, md_did2no3 : std_ulogic; +signal md_did3no1, md_did3no2, md_did3no0 : std_ulogic; +signal hi_sel, hi_sel_b, md_sel, md_sel_b, hi_later, md_later : std_ulogic_vector(0 to 3); +signal hi_did3no0_din : std_ulogic; +signal hi_did3no1_din : std_ulogic; +signal hi_did3no2_din : std_ulogic; +signal hi_did2no0_din : std_ulogic; +signal hi_did2no1_din : std_ulogic; +signal hi_did1no0_din : std_ulogic; +signal md_did3no0_din : std_ulogic; +signal md_did3no1_din : std_ulogic; +signal md_did3no2_din : std_ulogic; +signal md_did2no0_din : std_ulogic; +signal md_did2no1_din : std_ulogic; +signal md_did1no0_din : std_ulogic; +signal issselhi_b, issselmd_b : std_ulogic_vector(0 to 3); +signal no_hi_v,no_hi_v_n01, no_hi_v_n23 : std_ulogic; +signal hi_l30, hi_l31, hi_l32 : std_ulogic; +signal hi_l23, hi_l20, hi_l21 : std_ulogic; +signal hi_l12, hi_l13, hi_l10 : std_ulogic; +signal hi_l01, hi_l02, hi_l03 : std_ulogic; +signal md_l30, md_l31, md_l32 : std_ulogic; +signal md_l23, md_l20, md_l21 : std_ulogic; +signal md_l12, md_l13, md_l10 : std_ulogic; +signal md_l01, md_l02, md_l03 : std_ulogic; +signal no_hi_v_b : std_ulogic; +signal pri_rand : std_ulogic_vector(0 to 5); +-- synopsys translate_off +-- synopsys translate_on + BEGIN --@@ START OF EXECUTABLE CODE FOR IUQ_IC_SELECT + +tiup <= '1'; +----------------------------------------------------------------------- +-- Latch Inputs +----------------------------------------------------------------------- +xu_iu_run_thread_d <= xu_iu_run_thread; +iu5_ifar_d <= bp_ib_iu4_ifar; +iu5_act <= spr_ic_clockgate_dis or or_reduce(iu0_high_sent4_l2) or or_reduce(iu0_low_sent4_l2); +an_ac_back_inv_d <= an_ac_back_inv; +an_ac_back_inv_target_d <= an_ac_back_inv_target; +an_ac_back_inv_addr_d <= an_ac_back_inv_addr; +back_inv <= an_ac_back_inv_l2 and an_ac_back_inv_target_l2; +back_inv_d <= back_inv; +iu_ierat_ium1_back_inv <= back_inv or (or_reduce(xu_icbi_buffer0_val_tid_d)); +an_ac_icbi_ack_d <= an_ac_icbi_ack; +an_ac_icbi_ack_thread_d <= an_ac_icbi_ack_thread; +iu0_high_act <= spr_ic_clockgate_dis or + or_reduce(high_mask_l2 or iu0_high_sent1_l2 or iu0_high_sent2_l2 or + iu0_high_sent3_l2 or iu0_high_sent4_l2); +iu0_low_act <= spr_ic_clockgate_dis or + or_reduce((low_mask_l2 and not high_mask_l2) or iu0_low_sent1_l2 or iu0_low_sent2_l2 or + iu0_low_sent3_l2 or iu0_low_sent4_l2 or icm_ics_load_tid); +----------------------------------------------------------------------- +-- XU ICBI Buffers +----------------------------------------------------------------------- +-- New: Use buffer0_act to hold buffer0 during feedback case (buffer_val(0) and back_inv_l2) +-- Don't need to change other buffers unless buffer0 is blocked by back_inv_l2, or one of upper buffers already has a valid entry +--xu_icbi_buffer_act <= xu_icbi_buffer_val(0); +xu_icbi_buffer123_act <= (xu_icbi_buffer_val(0) and back_inv_l2) or xu_icbi_buffer_val(1); +xu_icbi_buffer0_act <= not (xu_icbi_buffer_val(0) and back_inv_l2); +xu_icbi_buffer_val(0) <= or_reduce(xu_icbi_buffer0_val_tid_l2); +xu_icbi_buffer_val(1) <= or_reduce(xu_icbi_buffer1_val_tid_l2); +xu_icbi_buffer_val(2) <= or_reduce(xu_icbi_buffer2_val_tid_l2); +xu_icbi_buffer_val(3) <= or_reduce(xu_icbi_buffer3_val_tid_l2); +xu_icbi_buffer0_val_tid_d <= xu_icbi_buffer0_val_tid_l2 when (xu_icbi_buffer_val(0) and back_inv_l2) = '1' + else xu_icbi_buffer1_val_tid_l2 when (xu_icbi_buffer_val(1) and not back_inv_l2) = '1' + else xu_iu_ex6_icbi_val; +xu_icbi_buffer1_val_tid_d <= xu_iu_ex6_icbi_val when ((xu_icbi_buffer_val(0) and not xu_icbi_buffer_val(1) and back_inv_l2) or + (xu_icbi_buffer_val(1) and not xu_icbi_buffer_val(2) and not back_inv_l2)) = '1' + else xu_icbi_buffer2_val_tid_l2 when (xu_icbi_buffer_val(2) and not back_inv_l2) = '1' + else xu_icbi_buffer1_val_tid_l2; +xu_icbi_buffer2_val_tid_d <= xu_iu_ex6_icbi_val when ((xu_icbi_buffer_val(1) and not xu_icbi_buffer_val(2) and back_inv_l2) or + (xu_icbi_buffer_val(2) and not xu_icbi_buffer_val(3) and not back_inv_l2)) = '1' + else xu_icbi_buffer3_val_tid_l2 when (xu_icbi_buffer_val(3) and not back_inv_l2) = '1' + else xu_icbi_buffer2_val_tid_l2; +xu_icbi_buffer3_val_tid_d <= xu_iu_ex6_icbi_val when (xu_icbi_buffer_val(2) and not xu_icbi_buffer_val(3) and back_inv_l2) = '1' + else xu_icbi_buffer3_val_tid_l2 when back_inv_l2 = '1' + else "0000"; +-- Feedback path is now covered by act pin +xu_icbi_buffer0_addr_d <= + xu_icbi_buffer1_addr_l2 when (xu_icbi_buffer_val(1) and not back_inv_l2) = '1' + else xu_iu_ex6_icbi_addr; +xu_icbi_buffer1_addr_d <= xu_iu_ex6_icbi_addr when ((xu_icbi_buffer_val(0) and not xu_icbi_buffer_val(1) and back_inv_l2) or + (xu_icbi_buffer_val(1) and not xu_icbi_buffer_val(2) and not back_inv_l2)) = '1' + else xu_icbi_buffer2_addr_l2 when (xu_icbi_buffer_val(2) and not back_inv_l2) = '1' + else xu_icbi_buffer1_addr_l2; +xu_icbi_buffer2_addr_d <= xu_iu_ex6_icbi_addr when ((xu_icbi_buffer_val(1) and not xu_icbi_buffer_val(2) and back_inv_l2) or + (xu_icbi_buffer_val(2) and not xu_icbi_buffer_val(3) and not back_inv_l2)) = '1' + else xu_icbi_buffer3_addr_l2 when (xu_icbi_buffer_val(3) and not back_inv_l2) = '1' + else xu_icbi_buffer2_addr_l2; +xu_icbi_buffer3_addr_d <= xu_iu_ex6_icbi_addr when (xu_icbi_buffer_val(2) and not xu_icbi_buffer_val(3) and back_inv_l2) = '1' + else xu_icbi_buffer3_addr_l2; + WITH s3'(an_ac_icbi_ack_l2 & an_ac_icbi_ack_thread_l2(0 to 1)) SELECT l2_icbi_ack <= "1000" when "100", + "0100" when "101", + "0010" when "110", + "0001" when "111", + "0000" when others; +ic_fdep_icbi_ack <= l2_icbi_ack when spr_ic_icbi_ack_en_l2 = '1' + else "0000" when back_inv_l2 = '1' + else xu_icbi_buffer0_val_tid_l2; +----------------------------------------------------------------------- +-- SPR IDir Read +----------------------------------------------------------------------- +block_spr_idir_read <= iu0_inval or icm_ics_hold_iu0; +spr_idir_read_d <= spr_ic_idir_read or + (spr_idir_read_l2 and block_spr_idir_read); +spr_idir_row_d <= spr_ic_idir_row; +iu0_spr_idir_read <= spr_idir_read_l2 and not block_spr_idir_read; +ics_icd_iu0_spr_idir_read <= iu0_spr_idir_read; +----------------------------------------------------------------------- +-- IU0 +----------------------------------------------------------------------- +iu1_icm_flush_tid <= (gate_and( (icd_ics_iu1_valid and icm_ics_iu1_ecc_flush) , icd_ics_iu1_tid)) and not all_stages_flush_prev_l2; +hold_iu0_v <= ( 0 to 3 => icm_ics_hold_iu0); +iu0_hold_ecc <= icm_ics_iu1_ecc_flush; +iu0_hold_ecc_v <= ( 0 to 3 => icm_ics_iu1_ecc_flush); +iu_ierat_iu0_flush <= uc_flush_tid or ib_ic_iu5_redirect_tid or bp_ic_iu5_redirect_tid or + icd_ics_iu3_parity_flush or icd_ics_iu2_miss_flush_prev or iu1_icm_flush_tid or + hold_thread_iu0 or hold_iu0_v or iu0_hold_ecc_v; +iu_ierat_iu1_flush <= uc_flush_tid or ib_ic_iu5_redirect_tid or bp_ic_iu5_redirect_tid or + icd_ics_iu3_parity_flush or icd_ics_iu2_miss_flush_prev or iu1_icm_flush_tid; +all_stages_flush_tid <= xu_iu_flush or uc_flush_tid or ib_ic_iu5_redirect_tid or bp_ic_iu5_redirect_tid; +all_stages_flush_prev_d <= all_stages_flush_tid; +iu0_flush_tid <= icd_ics_iu3_parity_flush or ierat_iu_iu2_flush_req or icd_ics_iu2_miss_flush_prev or iu1_icm_flush_tid; +iu1_flush_tid <= icd_ics_iu3_parity_flush or ierat_iu_iu2_flush_req or icd_ics_iu2_miss_flush_prev or iu1_icm_flush_tid; +iu2_flush_tid(0) <= icd_ics_iu3_parity_flush(0) or (ierat_iu_iu2_flush_req(0) and not ierat_iu_iu2_miss); +iu2_flush_tid(1) <= icd_ics_iu3_parity_flush(1) or (ierat_iu_iu2_flush_req(1) and not ierat_iu_iu2_miss); +iu2_flush_tid(2) <= icd_ics_iu3_parity_flush(2) or (ierat_iu_iu2_flush_req(2) and not ierat_iu_iu2_miss); +iu2_flush_tid(3) <= icd_ics_iu3_parity_flush(3) or (ierat_iu_iu2_flush_req(3) and not ierat_iu_iu2_miss); +iu3_flush_tid <= icd_ics_iu3_parity_flush; +ics_icd_all_flush_prev <= all_stages_flush_prev_l2; +ics_icd_iu1_flush_tid <= iu1_flush_tid; +ics_icd_iu2_flush_tid <= iu2_flush_tid; +ics_icm_iu2_flush_tid <= iu2_flush_tid or all_stages_flush_tid; +ics_icm_iu3_flush_tid <= all_stages_flush_tid; +-- Look at uc_flush pre_iu0 to avoid timing problems in hold_thread_iu0. +-- BP hold occurs same cycle as BP redirect, so don't need to check again in iu0 +-- hold_thread_iu0 conditions need to be checked both pre_iu0 & in iu0. +hold_thread_pre_iu0(0) <= uc_ic_hold_thread(0) or uc_flush_tid(0) or + (bp_ic_iu5_hold_tid(0) and not xu_iu_flush(0)) or + icm_ics_hold_thread(0); +hold_thread_pre_iu0(1) <= uc_ic_hold_thread(1) or uc_flush_tid(1) or + (bp_ic_iu5_hold_tid(1) and not xu_iu_flush(1)) or + icm_ics_hold_thread(1); +hold_thread_pre_iu0(2) <= uc_ic_hold_thread(2) or uc_flush_tid(2) or + (bp_ic_iu5_hold_tid(2) and not xu_iu_flush(2)) or + icm_ics_hold_thread(2); +hold_thread_pre_iu0(3) <= uc_ic_hold_thread(3) or uc_flush_tid(3) or + (bp_ic_iu5_hold_tid(3) and not xu_iu_flush(3)) or + icm_ics_hold_thread(3); +hold_thread_iu0(0) <= not(xu_iu_run_thread_l2(0)) or ac_an_power_managed or ierat_iu_hold_req(0) or icm_ics_ecc_block_iu0(0); +hold_thread_iu0(1) <= not(xu_iu_run_thread_l2(1)) or ac_an_power_managed or ierat_iu_hold_req(1) or icm_ics_ecc_block_iu0(1); +hold_thread_iu0(2) <= not(xu_iu_run_thread_l2(2)) or ac_an_power_managed or ierat_iu_hold_req(2) or icm_ics_ecc_block_iu0(2); +hold_thread_iu0(3) <= not(xu_iu_run_thread_l2(3)) or ac_an_power_managed or ierat_iu_hold_req(3) or icm_ics_ecc_block_iu0(3); +high_mask_d(0) <= ((ib_ic_empty(0) and not iu0_high_sentall4(0)) or xu_iu_flush(0)) + and not hold_thread_pre_iu0(0) and not hold_thread_iu0(0) and not back_inv and not (or_reduce(xu_icbi_buffer0_val_tid_d)) and not spr_idir_read_d; +high_mask_d(1) <= ((ib_ic_empty(1) and not iu0_high_sentall4(1)) or xu_iu_flush(1)) + and not hold_thread_pre_iu0(1) and not hold_thread_iu0(1) and not back_inv and not (or_reduce(xu_icbi_buffer0_val_tid_d)) and not spr_idir_read_d; +high_mask_d(2) <= ((ib_ic_empty(2) and not iu0_high_sentall4(2)) or xu_iu_flush(2)) + and not hold_thread_pre_iu0(2) and not hold_thread_iu0(2) and not back_inv and not (or_reduce(xu_icbi_buffer0_val_tid_d)) and not spr_idir_read_d; +high_mask_d(3) <= ((ib_ic_empty(3) and not iu0_high_sentall4(3)) or xu_iu_flush(3)) + and not hold_thread_pre_iu0(3) and not hold_thread_iu0(3) and not back_inv and not (or_reduce(xu_icbi_buffer0_val_tid_d)) and not spr_idir_read_d; +low_mask_d(0) <= ib_ic_below_water(0) and not iu0_low_sentall4(0) and + (ib_ic_empty(0) or not iu0_high_sentall4(0)) and + not hold_thread_pre_iu0(0) and not hold_thread_iu0(0) and not back_inv and not (or_reduce(xu_icbi_buffer0_val_tid_d)) and not spr_idir_read_d; +low_mask_d(1) <= ib_ic_below_water(1) and not iu0_low_sentall4(1) and + (ib_ic_empty(1) or not iu0_high_sentall4(1)) and + not hold_thread_pre_iu0(1) and not hold_thread_iu0(1) and not back_inv and not (or_reduce(xu_icbi_buffer0_val_tid_d)) and not spr_idir_read_d; +low_mask_d(2) <= ib_ic_below_water(2) and not iu0_low_sentall4(2) and + (ib_ic_empty(2) or not iu0_high_sentall4(2)) and + not hold_thread_pre_iu0(2) and not hold_thread_iu0(2) and not back_inv and not (or_reduce(xu_icbi_buffer0_val_tid_d)) and not spr_idir_read_d; +low_mask_d(3) <= ib_ic_below_water(3) and not iu0_low_sentall4(3) and + (ib_ic_empty(3) or not iu0_high_sentall4(3)) and + not hold_thread_pre_iu0(3) and not hold_thread_iu0(3) and not back_inv and not (or_reduce(xu_icbi_buffer0_val_tid_d)) and not spr_idir_read_d; +---- Round robin q for selecting the next thread +--?TABLE select_next LISTING(final) OPTIMIZE PARMS(ON-SET, OFF-SET); +--*INPUTS*==============================*OUTPUTS*===============* +--| | | +--| iu0_last_tid_high_l2 | next_high_valid | +--| | high_mask_l2 | | next_low_valid | +--| | | | | | next_tid | +--| | | iu0_last_tid_low_l2 | | | | | +--| | | | low_mask_l2 | | | | | +--| | | | | | | | | | +--| | | | | | | | | | +--| 0123 0123 0123 0123 | | | 0123 | +--*TYPE*================================+=======================+ +--| PPPP PPPP PPPP PPPP | P P PPPP | +--*OPTIMIZE*--------------------------->| A A BBBB | +--*TERMS*===============================+=======================+ +--| 1000 -1-- ---- ---- | 1 0 0100 | +--| 1000 -01- ---- ---- | 1 0 0010 | +--| 1000 -001 ---- ---- | 1 0 0001 | +--| 1000 1000 ---- ---- | 1 0 1000 | +--| 0100 --1- ---- ---- | 1 0 0010 | +--| 0100 --01 ---- ---- | 1 0 0001 | +--| 0100 1-00 ---- ---- | 1 0 1000 | +--| 0100 0100 ---- ---- | 1 0 0100 | +--| 0010 ---1 ---- ---- | 1 0 0001 | +--| 0010 1--0 ---- ---- | 1 0 1000 | +--| 0010 01-0 ---- ---- | 1 0 0100 | +--| 0010 0010 ---- ---- | 1 0 0010 | +--| 0001 1--- ---- ---- | 1 0 1000 | +--| 0001 01-- ---- ---- | 1 0 0100 | +--| 0001 001- ---- ---- | 1 0 0010 | +--| 0001 0001 ---- ---- | 1 0 0001 | +--| ---- 0000 1000 -1-- | 0 1 0100 | +--| ---- 0000 1000 -01- | 0 1 0010 | +--| ---- 0000 1000 -001 | 0 1 0001 | +--| ---- 0000 1000 1000 | 0 1 1000 | +--| ---- 0000 0100 --1- | 0 1 0010 | +--| ---- 0000 0100 --01 | 0 1 0001 | +--| ---- 0000 0100 1-00 | 0 1 1000 | +--| ---- 0000 0100 0100 | 0 1 0100 | +--| ---- 0000 0010 ---1 | 0 1 0001 | +--| ---- 0000 0010 1--0 | 0 1 1000 | +--| ---- 0000 0010 01-0 | 0 1 0100 | +--| ---- 0000 0010 0010 | 0 1 0010 | +--| ---- 0000 0001 1--- | 0 1 1000 | +--| ---- 0000 0001 01-- | 0 1 0100 | +--| ---- 0000 0001 001- | 0 1 0010 | +--| ---- 0000 0001 0001 | 0 1 0001 | +--| ---- 0000 ---- 0000 | 0 0 ---- | +--*END*=================================+=======================+ +--?TABLE END select_next; +next_low_valid <= or_reduce(low_mask_l2) and not or_reduce(high_mask_l2); +next_high_valid <= or_reduce(high_mask_l2); +highpri_v_b0 <= not high_mask_l2; +medpri_v_b0 <= not low_mask_l2; +highpri0v_inv: highpri_v(0) <= not highpri_v_b0(0); +highpri1v_inv: highpri_v(1) <= not highpri_v_b0(1); +highpri2v_inv: highpri_v(2) <= not highpri_v_b0(2); +highpri3v_inv: highpri_v(3) <= not highpri_v_b0(3); +highpri0vb_inv: highpri_v_b(0) <= not highpri_v(0); +highpri1vb_inv: highpri_v_b(1) <= not highpri_v(1); +highpri2vb_inv: highpri_v_b(2) <= not highpri_v(2); +highpri3vb_inv: highpri_v_b(3) <= not highpri_v(3); +hi_sel_nor23: hi_sel(3) <= not (highpri_v_b(3) or hi_later(3)); +hi_sel_nand33: hi_later(3) <= not (hi_l30 and hi_l31 and hi_l32); +hi_sel_nand230: hi_l30 <= not (hi_did3no0 and highpri_v(0)); +hi_sel_nand231: hi_l31 <= not (hi_did3no1 and highpri_v(1)); +hi_sel_nand232: hi_l32 <= not (hi_did3no2 and highpri_v(2)); +hi_sel_nor22: hi_sel(2) <= not (highpri_v_b(2) or hi_later(2)); +hi_sel_nand32: hi_later(2) <= not (hi_l23 and hi_l20 and hi_l21); +hi_sel_nand223: hi_l23 <= not (hi_did2no3 and highpri_v(3)); +hi_sel_nand220: hi_l20 <= not (hi_did2no0 and highpri_v(0)); +hi_sel_nand221: hi_l21 <= not (hi_did2no1 and highpri_v(1)); +hi_sel_nor21: hi_sel(1) <= not (highpri_v_b(1) or hi_later(1)); +hi_sel_nand31: hi_later(1) <= not (hi_l12 and hi_l13 and hi_l10); +hi_sel_nand212: hi_l12 <= not (hi_did1no2 and highpri_v(2)); +hi_sel_nand213: hi_l13 <= not (hi_did1no3 and highpri_v(3)); +hi_sel_nand210: hi_l10 <= not (hi_did1no0 and highpri_v(0)); +hi_sel_nor20: hi_sel(0) <= not (highpri_v_b(0) or hi_later(0)); +hi_sel_nand30: hi_later(0) <= not (hi_l01 and hi_l02 and hi_l03); +hi_sel_nand201: hi_l01 <= not (hi_did0no1 and highpri_v(1)); +hi_sel_nand202: hi_l02 <= not (hi_did0no2 and highpri_v(2)); +hi_sel_nand203: hi_l03 <= not (hi_did0no3 and highpri_v(3)); +medpri0v_inv: medpri_v(0) <= not medpri_v_b0(0); +medpri1v_inv: medpri_v(1) <= not medpri_v_b0(1); +medpri2v_inv: medpri_v(2) <= not medpri_v_b0(2); +medpri3v_inv: medpri_v(3) <= not medpri_v_b0(3); +medpri0vb_inv: medpri_v_b(0) <= not medpri_v(0); +medpri1vb_inv: medpri_v_b(1) <= not medpri_v(1); +medpri2vb_inv: medpri_v_b(2) <= not medpri_v(2); +medpri3vb_inv: medpri_v_b(3) <= not medpri_v(3); +md_sel_nor23: md_sel(3) <= not (medpri_v_b(3) or md_later(3)); +md_sel_nand33: md_later(3) <= not (md_l30 and md_l31 and md_l32); +md_sel_nand230: md_l30 <= not (md_did3no0 and medpri_v(0)); +md_sel_nand231: md_l31 <= not (md_did3no1 and medpri_v(1)); +md_sel_nand232: md_l32 <= not (md_did3no2 and medpri_v(2)); +md_sel_nor22: md_sel(2) <= not (medpri_v_b(2) or md_later(2)); +md_sel_nand32: md_later(2) <= not (md_l23 and md_l20 and md_l21); +md_sel_nand223: md_l23 <= not (md_did2no3 and medpri_v(3)); +md_sel_nand220: md_l20 <= not (md_did2no0 and medpri_v(0)); +md_sel_nand221: md_l21 <= not (md_did2no1 and medpri_v(1)); +md_sel_nor21: md_sel(1) <= not (medpri_v_b(1) or md_later(1)); +md_sel_nand31: md_later(1) <= not (md_l12 and md_l13 and md_l10); +md_sel_nand212: md_l12 <= not (md_did1no2 and medpri_v(2)); +md_sel_nand213: md_l13 <= not (md_did1no3 and medpri_v(3)); +md_sel_nand210: md_l10 <= not (md_did1no0 and medpri_v(0)); +md_sel_nor20: md_sel(0) <= not (medpri_v_b(0) or md_later(0)); +md_sel_nand30: md_later(0) <= not (md_l01 and md_l02 and md_l03); +md_sel_nand201: md_l01 <= not (md_did0no1 and medpri_v(1)); +md_sel_nand202: md_l02 <= not (md_did0no2 and medpri_v(2)); +md_sel_nand203: md_l03 <= not (md_did0no3 and medpri_v(3)); +-- reorder high +hi_sel_inv0: hi_sel_b(0) <= not hi_sel(0); +hi_sel_inv1: hi_sel_b(1) <= not hi_sel(1); +hi_sel_inv2: hi_sel_b(2) <= not hi_sel(2); +hi_sel_inv3: hi_sel_b(3) <= not hi_sel(3); +hi_reordf_nand230: hi_did3no0_din <= not (hi_sel_b(3) and hi_n230); +hi_reordf_nand231: hi_did3no1_din <= not (hi_sel_b(3) and hi_n231); +hi_reordf_nand232: hi_did3no2_din <= not (hi_sel_b(3) and hi_n232); +hi_reord_nand230: hi_n230 <= not (hi_sel_b(0) and hi_did3no0); +hi_reord_nand231: hi_n231 <= not (hi_sel_b(1) and hi_did3no1); +hi_reord_nand232: hi_n232 <= not (hi_sel_b(2) and hi_did3no2); +hi_reordf_nand220: hi_did2no0_din <= not(hi_sel_b(2) and hi_n220); +hi_reord_nand220: hi_n220 <= not(hi_sel_b(0) and hi_did2no0); +hi_reordf_nand221: hi_did2no1_din <= not(hi_sel_b(2) and hi_n221); +hi_reord_nand221: hi_n221 <= not(hi_sel_b(1) and hi_did2no1); +hi_reord_inv23: hi_did2no3 <= not hi_did3no2; +hi_reordf_nand210: hi_did1no0_din <= not(hi_sel_b(1) and hi_n210); +hi_reord_nand210: hi_n210 <= not(hi_sel_b(0) and hi_did1no0); +hi_reord_inv12: hi_did1no2 <= not hi_did2no1; +hi_reord_inv13: hi_did1no3 <= not hi_did3no1; +hi_reord_inv01: hi_did0no1 <= not hi_did1no0; +hi_reord_inv02: hi_did0no2 <= not hi_did2no0; +hi_reord_inv03: hi_did0no3 <= not hi_did3no0; +-- reorder med +md_sel_inv0: md_sel_b(0) <= not md_sel(0); +md_sel_inv1: md_sel_b(1) <= not md_sel(1); +md_sel_inv2: md_sel_b(2) <= not md_sel(2); +md_sel_inv3: md_sel_b(3) <= not md_sel(3); +md_reordf_nand230: md_did3no0_din <= not (md_sel_b(3) and md_n230); +md_reordf_nand231: md_did3no1_din <= not (md_sel_b(3) and md_n231); +md_reordf_nand232: md_did3no2_din <= not (md_sel_b(3) and md_n232); +md_reord_nand230: md_n230 <= not (md_sel_b(0) and md_did3no0); +md_reord_nand231: md_n231 <= not (md_sel_b(1) and md_did3no1); +md_reord_nand232: md_n232 <= not (md_sel_b(2) and md_did3no2); +md_reordf_nand220: md_did2no0_din <= not(md_sel_b(2) and md_n220); +md_reord_nand220: md_n220 <= not(md_sel_b(0) and md_did2no0); +md_reordf_nand221: md_did2no1_din <= not(md_sel_b(2) and md_n221); +md_reord_nand221: md_n221 <= not(md_sel_b(1) and md_did2no1); +md_reord_inv23: md_did2no3 <= not md_did3no2; +md_reordf_nand210: md_did1no0_din <= not(md_sel_b(1) and md_n210); +md_reord_nand210: md_n210 <= not(md_sel_b(0) and md_did1no0); +md_reord_inv12: md_did1no2 <= not md_did2no1; +md_reord_inv13: md_did1no3 <= not md_did3no1; +md_reord_inv01: md_did0no1 <= not md_did1no0; +md_reord_inv02: md_did0no2 <= not md_did2no0; +md_reord_inv03: md_did0no3 <= not md_did3no0; +--issue select +nohi_nor21: no_hi_v_n01 <= not (highpri_v(0) or highpri_v(1)); +nohi_nor22: no_hi_v_n23 <= not (highpri_v(2) or highpri_v(3)); +nohi_nand2: no_hi_v_b <= not (no_hi_v_n01 and no_hi_v_n23); +nohi_inv: no_hi_v <= not (no_hi_v_b); +isssel0_inv: issselhi_b(0) <= not (hi_sel(0)); +isssel1_inv: issselhi_b(1) <= not (hi_sel(1)); +isssel2_inv: issselhi_b(2) <= not (hi_sel(2)); +isssel3_inv: issselhi_b(3) <= not (hi_sel(3)); +isssel0_bnand2: issselmd_b(0) <= not (md_sel(0) and no_hi_v); +isssel1_bnand2: issselmd_b(1) <= not (md_sel(1) and no_hi_v); +isssel2_bnand2: issselmd_b(2) <= not (md_sel(2) and no_hi_v); +isssel3_bnand2: issselmd_b(3) <= not (md_sel(3) and no_hi_v); +nexttid0_fnand2: next_tid(0) <= not (issselhi_b(0) and issselmd_b(0)); +nexttid1_fnand2: next_tid(1) <= not (issselhi_b(1) and issselmd_b(1)); +nexttid2_fnand2: next_tid(2) <= not (issselhi_b(2) and issselmd_b(2)); +nexttid3_fnand2: next_tid(3) <= not (issselhi_b(3) and issselmd_b(3)); +-- end of mapping section +iu0_ifar_early_proc: process( + ib_ic_iu5_redirect_tid, iu5_ifar_l2, + bp_ic_iu5_redirect_tid, bp_ic_iu5_redirect_ifar, + icd_ics_iu3_parity_flush, icd_ics_iu3_ifar, icd_ics_iu3_2ucode, icd_ics_iu3_2ucode_type, + ierat_iu_iu2_flush_req, icd_ics_iu2_2ucode, icd_ics_iu2_2ucode_type, + icd_ics_iu2_miss_flush_prev, icd_ics_iu2_ifar_eff, icm_ics_iu2_miss_match_prev, + iu1_icm_flush_tid, icd_ics_iu1_ifar, icd_ics_iu1_2ucode, icd_ics_iu1_2ucode_type, + icm_ics_hold_iu0, hold_thread_iu0, iu0_hold_ecc, + next_tid, iu0_2ucode_l2, iu0_2ucode_type_l2, + iu0_ifar0_l2, iu0_ifar1_l2, iu0_ifar2_l2, iu0_ifar3_l2 ) +begin +if (ib_ic_iu5_redirect_tid(0) = '1') then +iu0_ifar0_early <= iu5_ifar_l2; +iu0_2ucode_early(0) <= '0'; +iu0_2ucode_type_early(0) <= '0'; +elsif (bp_ic_iu5_redirect_tid(0) = '1') then +iu0_ifar0_early <= bp_ic_iu5_redirect_ifar; +iu0_2ucode_early(0) <= '0'; +iu0_2ucode_type_early(0) <= '0'; +elsif ((icd_ics_iu3_parity_flush(0) or + (icd_ics_iu2_miss_flush_prev(0) and icm_ics_iu2_miss_match_prev)) = '1') then +iu0_ifar0_early <= icd_ics_iu3_ifar; +iu0_2ucode_early(0) <= icd_ics_iu3_2ucode; +iu0_2ucode_type_early(0) <= icd_ics_iu3_2ucode_type; +elsif (icd_ics_iu2_miss_flush_prev(0) = '1') then +iu0_ifar0_early <= (icd_ics_iu3_ifar(EFF_IFAR'left to 59) + 1) & "00"; +iu0_2ucode_early(0) <= '0'; +iu0_2ucode_type_early(0) <= '0'; +elsif (ierat_iu_iu2_flush_req(0) = '1') then +iu0_ifar0_early <= icd_ics_iu2_ifar_eff; +iu0_2ucode_early(0) <= icd_ics_iu2_2ucode; +iu0_2ucode_type_early(0) <= icd_ics_iu2_2ucode_type; +elsif (iu1_icm_flush_tid(0) = '1') then +iu0_ifar0_early <= icd_ics_iu1_ifar; +iu0_2ucode_early(0) <= icd_ics_iu1_2ucode; +iu0_2ucode_type_early(0) <= icd_ics_iu1_2ucode_type; +elsif ((next_tid(0) and not icm_ics_hold_iu0 and not hold_thread_iu0(0) and not iu0_hold_ecc) = '1') then +iu0_ifar0_early <= (iu0_ifar0_l2(EFF_IFAR'left to 59) + 1) & "00"; +iu0_2ucode_early(0) <= '0'; +iu0_2ucode_type_early(0) <= '0'; +else +iu0_ifar0_early <= iu0_ifar0_l2; +iu0_2ucode_early(0) <= iu0_2ucode_l2(0); +iu0_2ucode_type_early(0) <= iu0_2ucode_type_l2(0); +end if; +if (ib_ic_iu5_redirect_tid(1) = '1') then +iu0_ifar1_early <= iu5_ifar_l2; +iu0_2ucode_early(1) <= '0'; +iu0_2ucode_type_early(1) <= '0'; +elsif (bp_ic_iu5_redirect_tid(1) = '1') then +iu0_ifar1_early <= bp_ic_iu5_redirect_ifar; +iu0_2ucode_early(1) <= '0'; +iu0_2ucode_type_early(1) <= '0'; +elsif ((icd_ics_iu3_parity_flush(1) or + (icd_ics_iu2_miss_flush_prev(1) and icm_ics_iu2_miss_match_prev)) = '1') then +iu0_ifar1_early <= icd_ics_iu3_ifar; +iu0_2ucode_early(1) <= icd_ics_iu3_2ucode; +iu0_2ucode_type_early(1) <= icd_ics_iu3_2ucode_type; +elsif (icd_ics_iu2_miss_flush_prev(1) = '1') then +iu0_ifar1_early <= (icd_ics_iu3_ifar(EFF_IFAR'left to 59) + 1) & "00"; +iu0_2ucode_early(1) <= '0'; +iu0_2ucode_type_early(1) <= '0'; +elsif (ierat_iu_iu2_flush_req(1) = '1') then +iu0_ifar1_early <= icd_ics_iu2_ifar_eff; +iu0_2ucode_early(1) <= icd_ics_iu2_2ucode; +iu0_2ucode_type_early(1) <= icd_ics_iu2_2ucode_type; +elsif (iu1_icm_flush_tid(1) = '1') then +iu0_ifar1_early <= icd_ics_iu1_ifar; +iu0_2ucode_early(1) <= icd_ics_iu1_2ucode; +iu0_2ucode_type_early(1) <= icd_ics_iu1_2ucode_type; +elsif ((next_tid(1) and not icm_ics_hold_iu0 and not hold_thread_iu0(1) and not iu0_hold_ecc) = '1') then +iu0_ifar1_early <= (iu0_ifar1_l2(EFF_IFAR'left to 59) + 1) & "00"; +iu0_2ucode_early(1) <= '0'; +iu0_2ucode_type_early(1) <= '0'; +else +iu0_ifar1_early <= iu0_ifar1_l2; +iu0_2ucode_early(1) <= iu0_2ucode_l2(1); +iu0_2ucode_type_early(1) <= iu0_2ucode_type_l2(1); +end if; +if (ib_ic_iu5_redirect_tid(2) = '1') then +iu0_ifar2_early <= iu5_ifar_l2; +iu0_2ucode_early(2) <= '0'; +iu0_2ucode_type_early(2) <= '0'; +elsif (bp_ic_iu5_redirect_tid(2) = '1') then +iu0_ifar2_early <= bp_ic_iu5_redirect_ifar; +iu0_2ucode_early(2) <= '0'; +iu0_2ucode_type_early(2) <= '0'; +elsif ((icd_ics_iu3_parity_flush(2) or + (icd_ics_iu2_miss_flush_prev(2) and icm_ics_iu2_miss_match_prev)) = '1') then +iu0_ifar2_early <= icd_ics_iu3_ifar; +iu0_2ucode_early(2) <= icd_ics_iu3_2ucode; +iu0_2ucode_type_early(2) <= icd_ics_iu3_2ucode_type; +elsif (icd_ics_iu2_miss_flush_prev(2) = '1') then +iu0_ifar2_early <= (icd_ics_iu3_ifar(EFF_IFAR'left to 59) + 1) & "00"; +iu0_2ucode_early(2) <= '0'; +iu0_2ucode_type_early(2) <= '0'; +elsif (ierat_iu_iu2_flush_req(2) = '1') then +iu0_ifar2_early <= icd_ics_iu2_ifar_eff; +iu0_2ucode_early(2) <= icd_ics_iu2_2ucode; +iu0_2ucode_type_early(2) <= icd_ics_iu2_2ucode_type; +elsif (iu1_icm_flush_tid(2) = '1') then +iu0_ifar2_early <= icd_ics_iu1_ifar; +iu0_2ucode_early(2) <= icd_ics_iu1_2ucode; +iu0_2ucode_type_early(2) <= icd_ics_iu1_2ucode_type; +elsif ((next_tid(2) and not icm_ics_hold_iu0 and not hold_thread_iu0(2) and not iu0_hold_ecc) = '1') then +iu0_ifar2_early <= (iu0_ifar2_l2(EFF_IFAR'left to 59) + 1) & "00"; +iu0_2ucode_early(2) <= '0'; +iu0_2ucode_type_early(2) <= '0'; +else +iu0_ifar2_early <= iu0_ifar2_l2; +iu0_2ucode_early(2) <= iu0_2ucode_l2(2); +iu0_2ucode_type_early(2) <= iu0_2ucode_type_l2(2); +end if; +if (ib_ic_iu5_redirect_tid(3) = '1') then +iu0_ifar3_early <= iu5_ifar_l2; +iu0_2ucode_early(3) <= '0'; +iu0_2ucode_type_early(3) <= '0'; +elsif (bp_ic_iu5_redirect_tid(3) = '1') then +iu0_ifar3_early <= bp_ic_iu5_redirect_ifar; +iu0_2ucode_early(3) <= '0'; +iu0_2ucode_type_early(3) <= '0'; +elsif ((icd_ics_iu3_parity_flush(3) or + (icd_ics_iu2_miss_flush_prev(3) and icm_ics_iu2_miss_match_prev)) = '1') then +iu0_ifar3_early <= icd_ics_iu3_ifar; +iu0_2ucode_early(3) <= icd_ics_iu3_2ucode; +iu0_2ucode_type_early(3) <= icd_ics_iu3_2ucode_type; +elsif (icd_ics_iu2_miss_flush_prev(3) = '1') then +iu0_ifar3_early <= (icd_ics_iu3_ifar(EFF_IFAR'left to 59) + 1) & "00"; +iu0_2ucode_early(3) <= '0'; +iu0_2ucode_type_early(3) <= '0'; +elsif (ierat_iu_iu2_flush_req(3) = '1') then +iu0_ifar3_early <= icd_ics_iu2_ifar_eff; +iu0_2ucode_early(3) <= icd_ics_iu2_2ucode; +iu0_2ucode_type_early(3) <= icd_ics_iu2_2ucode_type; +elsif (iu1_icm_flush_tid(3) = '1') then +iu0_ifar3_early <= icd_ics_iu1_ifar; +iu0_2ucode_early(3) <= icd_ics_iu1_2ucode; +iu0_2ucode_type_early(3) <= icd_ics_iu1_2ucode_type; +elsif ((next_tid(3) and not icm_ics_hold_iu0 and not hold_thread_iu0(3) and not iu0_hold_ecc) = '1') then +iu0_ifar3_early <= (iu0_ifar3_l2(EFF_IFAR'left to 59) + 1) & "00"; +iu0_2ucode_early(3) <= '0'; +iu0_2ucode_type_early(3) <= '0'; +else +iu0_ifar3_early <= iu0_ifar3_l2; +iu0_2ucode_early(3) <= iu0_2ucode_l2(3); +iu0_2ucode_type_early(3) <= iu0_2ucode_type_l2(3); +end if; +end process; +iu0_ifar0_mux: +iu0_ifar0_pre_cm <= xu_iu_iu0_flush_ifar0 when xu_iu_flush(0) = '1' + else iu0_ifar0_early; +-- Zero out ifar(0:31) when xu_iu_msr_cm(0) = '0' +iu0_ifar0: for i in EFF_IFAR'left to EFF_IFAR'right generate +begin + R0:if(i < 32) generate begin iu0_ifar0_d(i) <= iu0_ifar0_pre_cm(i) and xu_iu_msr_cm(0); +end generate; +R1:if(i >= 32) generate +begin iu0_ifar0_d(i) <= iu0_ifar0_pre_cm(i); +end generate; +end generate; +iu0_2ucode0_mux: +iu0_2ucode_d(0) <= xu_iu_flush_2ucode(0) when xu_iu_flush(0) = '1' + else iu0_2ucode_early(0); +iu0_2ucode_type0_mux: +iu0_2ucode_type_d(0) <= xu_iu_flush_2ucode_type(0) when xu_iu_flush(0) = '1' + else iu0_2ucode_type_early(0); +iu0_ifar1_mux: +iu0_ifar1_pre_cm <= xu_iu_iu0_flush_ifar1 when xu_iu_flush(1) = '1' + else iu0_ifar1_early; +-- Zero out ifar(0:31) when xu_iu_msr_cm(1) = '0' +iu0_ifar1: for i in EFF_IFAR'left to EFF_IFAR'right generate +begin + R0:if(i < 32) generate begin iu0_ifar1_d(i) <= iu0_ifar1_pre_cm(i) and xu_iu_msr_cm(1); +end generate; +R1:if(i >= 32) generate +begin iu0_ifar1_d(i) <= iu0_ifar1_pre_cm(i); +end generate; +end generate; +iu0_2ucode1_mux: +iu0_2ucode_d(1) <= xu_iu_flush_2ucode(1) when xu_iu_flush(1) = '1' + else iu0_2ucode_early(1); +iu0_2ucode_type1_mux: +iu0_2ucode_type_d(1) <= xu_iu_flush_2ucode_type(1) when xu_iu_flush(1) = '1' + else iu0_2ucode_type_early(1); +iu0_ifar2_mux: +iu0_ifar2_pre_cm <= xu_iu_iu0_flush_ifar2 when xu_iu_flush(2) = '1' + else iu0_ifar2_early; +-- Zero out ifar(0:31) when xu_iu_msr_cm(2) = '0' +iu0_ifar2: for i in EFF_IFAR'left to EFF_IFAR'right generate +begin + R0:if(i < 32) generate begin iu0_ifar2_d(i) <= iu0_ifar2_pre_cm(i) and xu_iu_msr_cm(2); +end generate; +R1:if(i >= 32) generate +begin iu0_ifar2_d(i) <= iu0_ifar2_pre_cm(i); +end generate; +end generate; +iu0_2ucode2_mux: +iu0_2ucode_d(2) <= xu_iu_flush_2ucode(2) when xu_iu_flush(2) = '1' + else iu0_2ucode_early(2); +iu0_2ucode_type2_mux: +iu0_2ucode_type_d(2) <= xu_iu_flush_2ucode_type(2) when xu_iu_flush(2) = '1' + else iu0_2ucode_type_early(2); +iu0_ifar3_mux: +iu0_ifar3_pre_cm <= xu_iu_iu0_flush_ifar3 when xu_iu_flush(3) = '1' + else iu0_ifar3_early; +-- Zero out ifar(0:31) when xu_iu_msr_cm(3) = '0' +iu0_ifar3: for i in EFF_IFAR'left to EFF_IFAR'right generate +begin + R0:if(i < 32) generate begin iu0_ifar3_d(i) <= iu0_ifar3_pre_cm(i) and xu_iu_msr_cm(3); +end generate; +R1:if(i >= 32) generate +begin iu0_ifar3_d(i) <= iu0_ifar3_pre_cm(i); +end generate; +end generate; +iu0_2ucode3_mux: +iu0_2ucode_d(3) <= xu_iu_flush_2ucode(3) when xu_iu_flush(3) = '1' + else iu0_2ucode_early(3); +iu0_2ucode_type3_mux: +iu0_2ucode_type_d(3) <= xu_iu_flush_2ucode_type(3) when xu_iu_flush(3) = '1' + else iu0_2ucode_type_early(3); +ics_icm_iu0_ifar0 <= iu0_ifar0_l2(46 to 52); +ics_icm_iu0_ifar1 <= iu0_ifar1_l2(46 to 52); +ics_icm_iu0_ifar2 <= iu0_ifar2_l2(46 to 52); +ics_icm_iu0_ifar3 <= iu0_ifar3_l2(46 to 52); +iu0_early_valid <= next_high_valid or next_low_valid; +iu0_valid <= iu0_early_valid and not icm_ics_hold_iu0 and not iu0_hold_ecc and not or_reduce((iu0_flush_tid or hold_thread_iu0) and next_tid); +ics_icd_iu0_valid <= iu0_valid; +ics_icd_iu0_tid <= next_tid; +last_sent_proc: process(next_high_valid, next_low_valid, next_tid, icm_ics_hold_iu0, hold_thread_iu0, + iu0_flush_tid, iu0_hold_ecc ) +begin +iu0_high_sent1_d <= "0000"; +iu0_low_sent1_d <= "0000"; +if(next_high_valid = '1' and (icm_ics_hold_iu0 = '0' and iu0_hold_ecc = '0' and (or_reduce(hold_thread_iu0 and next_tid)) = '0')) then +iu0_high_sent1_d <= next_tid and not iu0_flush_tid; +elsif (next_low_valid = '1' and (icm_ics_hold_iu0 = '0' and iu0_hold_ecc = '0' and (or_reduce(hold_thread_iu0 and next_tid)) = '0')) then +iu0_low_sent1_d <= next_tid and not iu0_flush_tid; +end if; +end process; +iu0_high_sent2_d <= iu0_high_sent1_l2 and not iu1_flush_tid and not all_stages_flush_prev_l2; +iu0_low_sent2_d <= iu0_low_sent1_l2 and not iu1_flush_tid and not all_stages_flush_prev_l2; +iu0_high_sent3_d <= iu0_high_sent2_l2 and not iu2_flush_tid and not icd_ics_iu2_miss_flush_prev and not all_stages_flush_prev_l2; +iu0_low_sent3_d <= ((iu0_low_sent2_l2 and not iu2_flush_tid and not icd_ics_iu2_miss_flush_prev) or icm_ics_load_tid) and not all_stages_flush_prev_l2; +iu0_high_sent4_d <= iu0_high_sent3_l2 and not iu3_flush_tid and not icd_ics_iu2_miss_flush_prev and not all_stages_flush_prev_l2; +iu0_low_sent4_d <= iu0_low_sent3_l2 and not iu3_flush_tid and not icd_ics_iu2_miss_flush_prev and not all_stages_flush_prev_l2; +iu0_high_sentall4 <= not bp_ic_iu5_redirect_tid and not ib_ic_iu5_redirect_tid and + (iu0_high_sent1_d or + (((iu0_high_sent1_l2 and not iu1_flush_tid) or + (iu0_high_sent2_l2 and not (iu2_flush_tid or icd_ics_iu2_miss_flush_prev)) or + (iu0_high_sent3_l2 and not (iu3_flush_tid or icd_ics_iu2_miss_flush_prev)) or + (iu0_high_sent4_l2)) and not all_stages_flush_prev_l2)); +iu0_low_sentall4 <= not bp_ic_iu5_redirect_tid and not ib_ic_iu5_redirect_tid and + (iu0_low_sent1_d or + (((iu0_low_sent1_l2 and not iu1_flush_tid) or + (iu0_low_sent2_l2 and not (iu2_flush_tid or icd_ics_iu2_miss_flush_prev)) or + (icm_ics_load_tid and not iu3_flush_tid) or + (iu0_low_sent3_l2 and not (iu3_flush_tid or icd_ics_iu2_miss_flush_prev)) or + (iu0_low_sent4_l2)) and not all_stages_flush_prev_l2)); +R0: if (EFF_IFAR'left < REAL_IFAR'left) generate +begin + back_inv_addr_ext(EFF_IFAR'left TO REAL_IFAR'left-1) <= (others => '0'); +end generate; +back_inv_addr_ext(REAL_IFAR'left TO 57) <= an_ac_back_inv_addr_l2; +R1: if (EFF_IFAR'left < REAL_IFAR'left) generate +begin + xu_icbi_addr_ext(EFF_IFAR'left TO REAL_IFAR'left-1) <= (others => '0'); +end generate; +xu_icbi_addr_ext(REAL_IFAR'left TO 57) <= xu_icbi_buffer0_addr_l2; +iu0_inval <= back_inv_l2 or xu_icbi_buffer_val(0); +ics_icd_iu0_inval <= iu0_inval; +ics_icm_iu0_inval <= iu0_inval; +ics_icm_iu0_inval_addr <= an_ac_back_inv_addr_l2(52 to 57) when back_inv_l2_clone = '1' + else xu_icbi_buffer0_addr_l2(52 to 57); +-- Mux back inv address while waiting for thread select, for timing +iu0_ifar0_or_back_inv_addr(EFF_IFAR'left TO 51) <= + back_inv_addr_ext(EFF_IFAR'left to 51) when back_inv_l2 = '1' + else xu_icbi_addr_ext(EFF_IFAR'left to 51) when xu_icbi_buffer_val(0) = '1' + else iu0_ifar0_l2(EFF_IFAR'left to 51); +iu0_ifar0_or_back_inv_addr(52 TO 57) <= + back_inv_addr_ext(52 to 57) when back_inv_l2 = '1' + else xu_icbi_addr_ext(52 to 57) when xu_icbi_buffer_val(0) = '1' + else spr_idir_row_l2(52 to 57) when spr_idir_read_l2 = '1' + else iu0_ifar0_l2(52 to 57); +iu0_ifar0_or_back_inv_addr(58 TO 61) <= iu0_ifar0_l2(58 to 61); +select_iu0_ifar0 <= next_tid(0) or iu0_inval or spr_idir_read_l2; +iu0_ifar <= + gate_and( select_iu0_ifar0, iu0_ifar0_or_back_inv_addr) or + gate_and( next_tid(1), iu0_ifar1_l2) or + gate_and( next_tid(2), iu0_ifar2_l2) or + gate_and( next_tid(3), iu0_ifar3_l2); +ics_icd_iu0_ifar <= iu0_ifar; +iu0_2ucode <= or_reduce(next_tid and iu0_2ucode_l2); +iu0_2ucode_type <= or_reduce(next_tid and iu0_2ucode_type_l2); +ics_icd_iu0_2ucode <= iu0_2ucode; +ics_icd_iu0_2ucode_type <= iu0_2ucode_type; +----------------------------------------------------------------------- +-- IU1 BP +----------------------------------------------------------------------- +iu1_bp_val_d <= icm_ics_iu0_preload_val or iu0_valid; +iu1_bp_tid_d <= icm_ics_iu0_preload_tid when icm_ics_iu0_preload_val = '1' + else next_tid; +iu1_bp_ifar_d <= icm_ics_iu0_preload_ifar when icm_ics_iu0_preload_val = '1' + else iu0_ifar(52 to 59); +iu1_bp_act <= spr_ic_clockgate_dis or + icm_ics_iu0_preload_val or (iu0_early_valid and not icm_ics_hold_iu0 and not iu0_hold_ecc); +ic_bp_iu1_val <= iu1_bp_val_l2; +ic_bp_iu1_tid <= iu1_bp_tid_d; +ic_bp_iu1_ifar <= iu1_bp_ifar_l2(52 to 59); +----------------------------------------------------------------------- +-- Access ERAT +----------------------------------------------------------------------- +iu_ierat_iu0_val <= iu0_early_valid; +iu_ierat_iu0_thdid <= next_tid; +ierat_ifar: for i in 0 to 51 generate +begin + R0:if(i < EFF_IFAR'left) generate begin iu_ierat_iu0_ifar(i) <= '0'; +end generate; +R1:if(i >= EFF_IFAR'left) generate +begin iu_ierat_iu0_ifar(i) <= iu0_ifar(i); +end generate; +end generate; +----------------------------------------------------------------------- +-- Access IDIR +----------------------------------------------------------------------- +ics_icd_dir_rd_act <= (iu0_early_valid and not icm_ics_hold_iu0 and not iu0_hold_ecc) or back_inv_l2 or xu_icbi_buffer_val(0) or + spr_idir_read_l2; +ics_icd_data_rd_act <= iu0_early_valid; +----------------------------------------------------------------------- +-- Performance Events +----------------------------------------------------------------------- +-- Reload Collisions +-- - (high_mask or low_mask) and miss_iu0_hold +perf_event_t0_d(2) <= (high_mask_l2(0) or low_mask_l2(0)) and icm_ics_hold_iu0; +perf_event_t1_d(2) <= (high_mask_l2(1) or low_mask_l2(1)) and icm_ics_hold_iu0; +perf_event_t2_d(2) <= (high_mask_l2(2) or low_mask_l2(2)) and icm_ics_hold_iu0; +perf_event_t3_d(2) <= (high_mask_l2(3) or low_mask_l2(3)) and icm_ics_hold_iu0; +-- IU0 Redirected +-- - any flush condition +perf_event_t0_d(3) <= all_stages_flush_tid(0) or iu0_flush_tid(0); +perf_event_t1_d(3) <= all_stages_flush_tid(1) or iu0_flush_tid(1); +perf_event_t2_d(3) <= all_stages_flush_tid(2) or iu0_flush_tid(2); +perf_event_t3_d(3) <= all_stages_flush_tid(3) or iu0_flush_tid(3); +ic_perf_event_t0 <= perf_event_t0_l2; +ic_perf_event_t1 <= perf_event_t1_l2; +ic_perf_event_t2 <= perf_event_t2_l2; +ic_perf_event_t3 <= perf_event_t3_l2; +----------------------------------------------------------------------- +-- Debug Bus +----------------------------------------------------------------------- +sel_dbg_data(0 TO 6) <= xu_iu_flush_l2(0) & uc_flush_tid(0) & ib_ic_iu5_redirect_tid(0) & + bp_ic_iu5_redirect_tid(0) & icd_ics_iu3_parity_flush(0) & icd_ics_iu2_miss_flush_prev(0) & ierat_iu_iu2_flush_req(0); +sel_dbg_data(8 TO 14) <= xu_iu_flush_l2(1) & uc_flush_tid(1) & ib_ic_iu5_redirect_tid(1) & + bp_ic_iu5_redirect_tid(1) & icd_ics_iu3_parity_flush(1) & icd_ics_iu2_miss_flush_prev(1) & ierat_iu_iu2_flush_req(1); +sel_dbg_data(16 TO 22) <= xu_iu_flush_l2(2) & uc_flush_tid(2) & ib_ic_iu5_redirect_tid(2) & + bp_ic_iu5_redirect_tid(2) & icd_ics_iu3_parity_flush(2) & icd_ics_iu2_miss_flush_prev(2) & ierat_iu_iu2_flush_req(2); +sel_dbg_data(24 TO 30) <= xu_iu_flush_l2(3) & uc_flush_tid(3) & ib_ic_iu5_redirect_tid(3) & + bp_ic_iu5_redirect_tid(3) & icd_ics_iu3_parity_flush(3) & icd_ics_iu2_miss_flush_prev(3) & ierat_iu_iu2_flush_req(3); +sel_dbg_data(7) <= icm_ics_iu1_ecc_flush; +sel_dbg_data(15) <= icm_ics_iu2_miss_match_prev; +sel_dbg_data(23) <= ierat_iu_iu2_miss; +sel_dbg_data(31) <= icd_ics_iu1_valid; +sel_dbg_data(32 TO 35) <= icd_ics_iu1_tid; +sel_dbg_data(36 TO 39) <= ib_ic_empty; +sel_dbg_data(40 TO 43) <= ib_ic_below_water; +--pri took +sel_dbg_data(44 TO 49) <= hi_did3no0 & hi_did3no1 & hi_did3no2 & hi_did2no0 & hi_did2no1 & hi_did1no0; +sel_dbg_data(50 TO 55) <= md_did3no0 & md_did3no1 & md_did3no2 & md_did2no0 & md_did2no1 & md_did1no0; +sel_dbg_data(56 TO 59) <= high_mask_l2; +sel_dbg_data(60 TO 63) <= low_mask_l2; +sel_dbg_data(64) <= spr_idir_read_l2; +sel_dbg_data(65) <= xu_icbi_buffer_val(0); +sel_dbg_data(66) <= back_inv_l2; +sel_dbg_data(67) <= icm_ics_hold_iu0; +sel_dbg_data(68 TO 72) <= xu_iu_run_thread_l2(0) & uc_ic_hold_thread(0) & + bp_ic_iu5_hold_tid(0) & icm_ics_hold_thread_dbg(0) & ierat_iu_hold_req(0); +sel_dbg_data(73 TO 77) <= xu_iu_run_thread_l2(1) & uc_ic_hold_thread(1) & + bp_ic_iu5_hold_tid(1) & icm_ics_hold_thread_dbg(1) & ierat_iu_hold_req(1); +sel_dbg_data(78 TO 82) <= xu_iu_run_thread_l2(2) & uc_ic_hold_thread(2) & + bp_ic_iu5_hold_tid(2) & icm_ics_hold_thread_dbg(2) & ierat_iu_hold_req(2); +sel_dbg_data(83 TO 87) <= xu_iu_run_thread_l2(3) & uc_ic_hold_thread(3) & + bp_ic_iu5_hold_tid(3) & icm_ics_hold_thread_dbg(3) & ierat_iu_hold_req(3); +----------------------------------------------------------------------- +-- Latches +----------------------------------------------------------------------- +an_ac_back_inv_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(an_ac_back_inv_offset), + scout => sov(an_ac_back_inv_offset), + din => an_ac_back_inv_d, + dout => an_ac_back_inv_l2); +an_ac_back_inv_target_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(an_ac_back_inv_target_offset), + scout => sov(an_ac_back_inv_target_offset), + din => an_ac_back_inv_target_d, + dout => an_ac_back_inv_target_l2); +an_ac_back_inv_addr_latch: tri_rlmreg_p + generic map (width => an_ac_back_inv_addr_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => back_inv, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(an_ac_back_inv_addr_offset to an_ac_back_inv_addr_offset + an_ac_back_inv_addr_l2'length-1), + scout => sov(an_ac_back_inv_addr_offset to an_ac_back_inv_addr_offset + an_ac_back_inv_addr_l2'length-1), + din => an_ac_back_inv_addr_d, + dout => an_ac_back_inv_addr_l2); +back_inv_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(back_inv_offset), + scout => sov(back_inv_offset), + din => back_inv_d, + dout => back_inv_l2); +back_inv_clone_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_slp_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => funcslp_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(back_inv_clone_offset), + scout => sov(back_inv_clone_offset), + din => back_inv_d, + dout => back_inv_l2_clone); +an_ac_icbi_ack_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(an_ac_icbi_ack_offset), + scout => sov(an_ac_icbi_ack_offset), + din => an_ac_icbi_ack_d, + dout => an_ac_icbi_ack_l2); +an_ac_icbi_ack_thread_latch: tri_rlmreg_p + generic map (width => an_ac_icbi_ack_thread_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(an_ac_icbi_ack_thread_offset to an_ac_icbi_ack_thread_offset + an_ac_icbi_ack_thread_l2'length-1), + scout => sov(an_ac_icbi_ack_thread_offset to an_ac_icbi_ack_thread_offset + an_ac_icbi_ack_thread_l2'length-1), + din => an_ac_icbi_ack_thread_d, + dout => an_ac_icbi_ack_thread_l2); +xu_icbi_buffer0_val_tid_latch: tri_rlmreg_p + generic map (width => xu_icbi_buffer0_val_tid_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_icbi_buffer0_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_icbi_buffer0_val_tid_offset to xu_icbi_buffer0_val_tid_offset + xu_icbi_buffer0_val_tid_l2'length-1), + scout => sov(xu_icbi_buffer0_val_tid_offset to xu_icbi_buffer0_val_tid_offset + xu_icbi_buffer0_val_tid_l2'length-1), + din => xu_icbi_buffer0_val_tid_d, + dout => xu_icbi_buffer0_val_tid_l2); +xu_icbi_buffer1_val_tid_latch: tri_rlmreg_p + generic map (width => xu_icbi_buffer1_val_tid_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_icbi_buffer123_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_icbi_buffer1_val_tid_offset to xu_icbi_buffer1_val_tid_offset + xu_icbi_buffer1_val_tid_l2'length-1), + scout => sov(xu_icbi_buffer1_val_tid_offset to xu_icbi_buffer1_val_tid_offset + xu_icbi_buffer1_val_tid_l2'length-1), + din => xu_icbi_buffer1_val_tid_d, + dout => xu_icbi_buffer1_val_tid_l2); +xu_icbi_buffer2_val_tid_latch: tri_rlmreg_p + generic map (width => xu_icbi_buffer2_val_tid_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_icbi_buffer123_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_icbi_buffer2_val_tid_offset to xu_icbi_buffer2_val_tid_offset + xu_icbi_buffer2_val_tid_l2'length-1), + scout => sov(xu_icbi_buffer2_val_tid_offset to xu_icbi_buffer2_val_tid_offset + xu_icbi_buffer2_val_tid_l2'length-1), + din => xu_icbi_buffer2_val_tid_d, + dout => xu_icbi_buffer2_val_tid_l2); +xu_icbi_buffer3_val_tid_latch: tri_rlmreg_p + generic map (width => xu_icbi_buffer3_val_tid_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_icbi_buffer123_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_icbi_buffer3_val_tid_offset to xu_icbi_buffer3_val_tid_offset + xu_icbi_buffer3_val_tid_l2'length-1), + scout => sov(xu_icbi_buffer3_val_tid_offset to xu_icbi_buffer3_val_tid_offset + xu_icbi_buffer3_val_tid_l2'length-1), + din => xu_icbi_buffer3_val_tid_d, + dout => xu_icbi_buffer3_val_tid_l2); +xu_icbi_buffer0_addr_latch: tri_rlmreg_p + generic map (width => xu_icbi_buffer0_addr_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_icbi_buffer0_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_icbi_buffer0_addr_offset to xu_icbi_buffer0_addr_offset + xu_icbi_buffer0_addr_l2'length-1), + scout => sov(xu_icbi_buffer0_addr_offset to xu_icbi_buffer0_addr_offset + xu_icbi_buffer0_addr_l2'length-1), + din => xu_icbi_buffer0_addr_d, + dout => xu_icbi_buffer0_addr_l2); +xu_icbi_buffer1_addr_latch: tri_rlmreg_p + generic map (width => xu_icbi_buffer1_addr_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_icbi_buffer123_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_icbi_buffer1_addr_offset to xu_icbi_buffer1_addr_offset + xu_icbi_buffer1_addr_l2'length-1), + scout => sov(xu_icbi_buffer1_addr_offset to xu_icbi_buffer1_addr_offset + xu_icbi_buffer1_addr_l2'length-1), + din => xu_icbi_buffer1_addr_d, + dout => xu_icbi_buffer1_addr_l2); +xu_icbi_buffer2_addr_latch: tri_rlmreg_p + generic map (width => xu_icbi_buffer2_addr_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_icbi_buffer123_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_icbi_buffer2_addr_offset to xu_icbi_buffer2_addr_offset + xu_icbi_buffer2_addr_l2'length-1), + scout => sov(xu_icbi_buffer2_addr_offset to xu_icbi_buffer2_addr_offset + xu_icbi_buffer2_addr_l2'length-1), + din => xu_icbi_buffer2_addr_d, + dout => xu_icbi_buffer2_addr_l2); +xu_icbi_buffer3_addr_latch: tri_rlmreg_p + generic map (width => xu_icbi_buffer3_addr_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_icbi_buffer123_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_icbi_buffer3_addr_offset to xu_icbi_buffer3_addr_offset + xu_icbi_buffer3_addr_l2'length-1), + scout => sov(xu_icbi_buffer3_addr_offset to xu_icbi_buffer3_addr_offset + xu_icbi_buffer3_addr_l2'length-1), + din => xu_icbi_buffer3_addr_d, + dout => xu_icbi_buffer3_addr_l2); +xu_iu_run_thread_latch: tri_rlmreg_p + generic map (width => xu_iu_run_thread_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_iu_run_thread_offset to xu_iu_run_thread_offset + xu_iu_run_thread_l2'length-1), + scout => sov(xu_iu_run_thread_offset to xu_iu_run_thread_offset + xu_iu_run_thread_l2'length-1), + din => xu_iu_run_thread_d, + dout => xu_iu_run_thread_l2); +all_stages_flush_prev_latch: tri_rlmreg_p + generic map (width => all_stages_flush_prev_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(all_stages_flush_prev_offset to all_stages_flush_prev_offset + all_stages_flush_prev_l2'length-1), + scout => sov(all_stages_flush_prev_offset to all_stages_flush_prev_offset + all_stages_flush_prev_l2'length-1), + din => all_stages_flush_prev_d, + dout => all_stages_flush_prev_l2); +-- IU0 +-- split up ifar latches - rlmreg can only init 31 bits at a time +iu0_ifar0a_latch: tri_rlmreg_p + generic map (width => EFF_IFAR'length/2, init => ((2**(EFF_IFAR'length/2 - 1)-1)*2+1), needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu0_ifar0_offset to iu0_ifar0_offset + (EFF_IFAR'length/2)-1), + scout => sov(iu0_ifar0_offset to iu0_ifar0_offset + (EFF_IFAR'length/2)-1), + din => iu0_ifar0_d(EFF_IFAR'left to EFF_IFAR'left+(EFF_IFAR'length/2)-1), + dout => iu0_ifar0_l2(EFF_IFAR'left to EFF_IFAR'left+(EFF_IFAR'length/2)-1)); +iu0_ifar0b_latch: tri_rlmreg_p + generic map (width => (EFF_IFAR'length - (EFF_IFAR'length/2)), init => ((2**(EFF_IFAR'length-(EFF_IFAR'length/2) - 1)-1)*2+1), needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu0_ifar0_offset + (EFF_IFAR'length/2) to iu0_ifar0_offset + iu0_ifar0_l2'length-1), + scout => sov(iu0_ifar0_offset + (EFF_IFAR'length/2) to iu0_ifar0_offset + iu0_ifar0_l2'length-1), + din => iu0_ifar0_d(EFF_IFAR'left+(EFF_IFAR'length/2) to EFF_IFAR'right), + dout => iu0_ifar0_l2(EFF_IFAR'left+(EFF_IFAR'length/2) to EFF_IFAR'right)); +iu0_ifar1a_latch: tri_rlmreg_p + generic map (width => EFF_IFAR'length/2, init => ((2**(EFF_IFAR'length/2 - 1)-1)*2+1), needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu0_ifar1_offset to iu0_ifar1_offset + (EFF_IFAR'length/2)-1), + scout => sov(iu0_ifar1_offset to iu0_ifar1_offset + (EFF_IFAR'length/2)-1), + din => iu0_ifar1_d(EFF_IFAR'left to EFF_IFAR'left+(EFF_IFAR'length/2)-1), + dout => iu0_ifar1_l2(EFF_IFAR'left to EFF_IFAR'left+(EFF_IFAR'length/2)-1)); +iu0_ifar1b_latch: tri_rlmreg_p + generic map (width => (EFF_IFAR'length - (EFF_IFAR'length/2)), init => ((2**(EFF_IFAR'length-(EFF_IFAR'length/2) - 1)-1)*2+1), needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu0_ifar1_offset + (EFF_IFAR'length/2) to iu0_ifar1_offset + iu0_ifar1_l2'length-1), + scout => sov(iu0_ifar1_offset + (EFF_IFAR'length/2) to iu0_ifar1_offset + iu0_ifar1_l2'length-1), + din => iu0_ifar1_d(EFF_IFAR'left+(EFF_IFAR'length/2) to EFF_IFAR'right), + dout => iu0_ifar1_l2(EFF_IFAR'left+(EFF_IFAR'length/2) to EFF_IFAR'right)); +iu0_ifar2a_latch: tri_rlmreg_p + generic map (width => EFF_IFAR'length/2, init => ((2**(EFF_IFAR'length/2 - 1)-1)*2+1), needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu0_ifar2_offset to iu0_ifar2_offset + (EFF_IFAR'length/2)-1), + scout => sov(iu0_ifar2_offset to iu0_ifar2_offset + (EFF_IFAR'length/2)-1), + din => iu0_ifar2_d(EFF_IFAR'left to EFF_IFAR'left+(EFF_IFAR'length/2)-1), + dout => iu0_ifar2_l2(EFF_IFAR'left to EFF_IFAR'left+(EFF_IFAR'length/2)-1)); +iu0_ifar2b_latch: tri_rlmreg_p + generic map (width => (EFF_IFAR'length - (EFF_IFAR'length/2)), init => ((2**(EFF_IFAR'length-(EFF_IFAR'length/2) - 1)-1)*2+1), needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu0_ifar2_offset + (EFF_IFAR'length/2) to iu0_ifar2_offset + iu0_ifar2_l2'length-1), + scout => sov(iu0_ifar2_offset + (EFF_IFAR'length/2) to iu0_ifar2_offset + iu0_ifar2_l2'length-1), + din => iu0_ifar2_d(EFF_IFAR'left+(EFF_IFAR'length/2) to EFF_IFAR'right), + dout => iu0_ifar2_l2(EFF_IFAR'left+(EFF_IFAR'length/2) to EFF_IFAR'right)); +iu0_ifar3a_latch: tri_rlmreg_p + generic map (width => EFF_IFAR'length/2, init => ((2**(EFF_IFAR'length/2 - 1)-1)*2+1), needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu0_ifar3_offset to iu0_ifar3_offset + (EFF_IFAR'length/2)-1), + scout => sov(iu0_ifar3_offset to iu0_ifar3_offset + (EFF_IFAR'length/2)-1), + din => iu0_ifar3_d(EFF_IFAR'left to EFF_IFAR'left+(EFF_IFAR'length/2)-1), + dout => iu0_ifar3_l2(EFF_IFAR'left to EFF_IFAR'left+(EFF_IFAR'length/2)-1)); +iu0_ifar3b_latch: tri_rlmreg_p + generic map (width => (EFF_IFAR'length - (EFF_IFAR'length/2)), init => ((2**(EFF_IFAR'length-(EFF_IFAR'length/2) - 1)-1)*2+1), needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu0_ifar3_offset + (EFF_IFAR'length/2) to iu0_ifar3_offset + iu0_ifar3_l2'length-1), + scout => sov(iu0_ifar3_offset + (EFF_IFAR'length/2) to iu0_ifar3_offset + iu0_ifar3_l2'length-1), + din => iu0_ifar3_d(EFF_IFAR'left+(EFF_IFAR'length/2) to EFF_IFAR'right), + dout => iu0_ifar3_l2(EFF_IFAR'left+(EFF_IFAR'length/2) to EFF_IFAR'right)); +iu0_2ucode_latch: tri_rlmreg_p + generic map (width => iu0_2ucode_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu0_2ucode_offset to iu0_2ucode_offset + iu0_2ucode_l2'length-1), + scout => sov(iu0_2ucode_offset to iu0_2ucode_offset + iu0_2ucode_l2'length-1), + din => iu0_2ucode_d, + dout => iu0_2ucode_l2); +iu0_2ucode_type_latch: tri_rlmreg_p + generic map (width => iu0_2ucode_type_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu0_2ucode_type_offset to iu0_2ucode_type_offset + iu0_2ucode_type_l2'length-1), + scout => sov(iu0_2ucode_type_offset to iu0_2ucode_type_offset + iu0_2ucode_type_l2'length-1), + din => iu0_2ucode_type_d, + dout => iu0_2ucode_type_l2); +iu0_high_sent1_latch: tri_rlmreg_p + generic map (width => iu0_high_sent1_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu0_high_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu0_high_sent1_offset to iu0_high_sent1_offset + iu0_high_sent1_l2'length-1), + scout => sov(iu0_high_sent1_offset to iu0_high_sent1_offset + iu0_high_sent1_l2'length-1), + din => iu0_high_sent1_d, + dout => iu0_high_sent1_l2); +iu0_high_sent2_latch: tri_rlmreg_p + generic map (width => iu0_high_sent2_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu0_high_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu0_high_sent2_offset to iu0_high_sent2_offset + iu0_high_sent2_l2'length-1), + scout => sov(iu0_high_sent2_offset to iu0_high_sent2_offset + iu0_high_sent2_l2'length-1), + din => iu0_high_sent2_d, + dout => iu0_high_sent2_l2); +iu0_high_sent3_latch: tri_rlmreg_p + generic map (width => iu0_high_sent3_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu0_high_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu0_high_sent3_offset to iu0_high_sent3_offset + iu0_high_sent3_l2'length-1), + scout => sov(iu0_high_sent3_offset to iu0_high_sent3_offset + iu0_high_sent3_l2'length-1), + din => iu0_high_sent3_d, + dout => iu0_high_sent3_l2); +iu0_high_sent4_latch: tri_rlmreg_p + generic map (width => iu0_high_sent4_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu0_high_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu0_high_sent4_offset to iu0_high_sent4_offset + iu0_high_sent4_l2'length-1), + scout => sov(iu0_high_sent4_offset to iu0_high_sent4_offset + iu0_high_sent4_l2'length-1), + din => iu0_high_sent4_d, + dout => iu0_high_sent4_l2); +iu0_low_sent1_latch: tri_rlmreg_p + generic map (width => iu0_low_sent1_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu0_low_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu0_low_sent1_offset to iu0_low_sent1_offset + iu0_low_sent1_l2'length-1), + scout => sov(iu0_low_sent1_offset to iu0_low_sent1_offset + iu0_low_sent1_l2'length-1), + din => iu0_low_sent1_d, + dout => iu0_low_sent1_l2); +iu0_low_sent2_latch: tri_rlmreg_p + generic map (width => iu0_low_sent2_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu0_low_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu0_low_sent2_offset to iu0_low_sent2_offset + iu0_low_sent2_l2'length-1), + scout => sov(iu0_low_sent2_offset to iu0_low_sent2_offset + iu0_low_sent2_l2'length-1), + din => iu0_low_sent2_d, + dout => iu0_low_sent2_l2); +iu0_low_sent3_latch: tri_rlmreg_p + generic map (width => iu0_low_sent3_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu0_low_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu0_low_sent3_offset to iu0_low_sent3_offset + iu0_low_sent3_l2'length-1), + scout => sov(iu0_low_sent3_offset to iu0_low_sent3_offset + iu0_low_sent3_l2'length-1), + din => iu0_low_sent3_d, + dout => iu0_low_sent3_l2); +iu0_low_sent4_latch: tri_rlmreg_p + generic map (width => iu0_low_sent4_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu0_low_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu0_low_sent4_offset to iu0_low_sent4_offset + iu0_low_sent4_l2'length-1), + scout => sov(iu0_low_sent4_offset to iu0_low_sent4_offset + iu0_low_sent4_l2'length-1), + din => iu0_low_sent4_d, + dout => iu0_low_sent4_l2); +high_mask_latch: tri_rlmreg_p + generic map (width => high_mask_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(high_mask_offset to high_mask_offset + high_mask_l2'length-1), + scout => sov(high_mask_offset to high_mask_offset + high_mask_l2'length-1), + din => high_mask_d, + dout => high_mask_l2); +low_mask_latch: tri_rlmreg_p + generic map (width => low_mask_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(low_mask_offset to low_mask_offset + low_mask_l2'length-1), + scout => sov(low_mask_offset to low_mask_offset + low_mask_l2'length-1), + din => low_mask_d, + dout => low_mask_l2); +iu1_bp_val_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu1_bp_val_offset), + scout => sov(iu1_bp_val_offset), + din => iu1_bp_val_d, + dout => iu1_bp_val_l2); +iu1_bp_ifar_latch: tri_rlmreg_p + generic map (width => iu1_bp_ifar_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu1_bp_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu1_bp_ifar_offset to iu1_bp_ifar_offset + iu1_bp_ifar_l2'length-1), + scout => sov(iu1_bp_ifar_offset to iu1_bp_ifar_offset + iu1_bp_ifar_l2'length-1), + din => iu1_bp_ifar_d, + dout => iu1_bp_ifar_l2); +iu5_ifar_latch: tri_rlmreg_p + generic map (width => iu5_ifar_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu5_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu5_ifar_offset to iu5_ifar_offset + iu5_ifar_l2'length-1), + scout => sov(iu5_ifar_offset to iu5_ifar_offset + iu5_ifar_l2'length-1), + din => iu5_ifar_d, + dout => iu5_ifar_l2); +perf_event_t0_latch: tri_rlmreg_p + generic map (width => perf_event_t0_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => event_bus_enable, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(perf_event_t0_offset to perf_event_t0_offset + perf_event_t0_l2'length-1), + scout => sov(perf_event_t0_offset to perf_event_t0_offset + perf_event_t0_l2'length-1), + din => perf_event_t0_d, + dout => perf_event_t0_l2); +perf_event_t1_latch: tri_rlmreg_p + generic map (width => perf_event_t1_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => event_bus_enable, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(perf_event_t1_offset to perf_event_t1_offset + perf_event_t1_l2'length-1), + scout => sov(perf_event_t1_offset to perf_event_t1_offset + perf_event_t1_l2'length-1), + din => perf_event_t1_d, + dout => perf_event_t1_l2); +perf_event_t2_latch: tri_rlmreg_p + generic map (width => perf_event_t2_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => event_bus_enable, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(perf_event_t2_offset to perf_event_t2_offset + perf_event_t2_l2'length-1), + scout => sov(perf_event_t2_offset to perf_event_t2_offset + perf_event_t2_l2'length-1), + din => perf_event_t2_d, + dout => perf_event_t2_l2); +perf_event_t3_latch: tri_rlmreg_p + generic map (width => perf_event_t3_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => event_bus_enable, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(perf_event_t3_offset to perf_event_t3_offset + perf_event_t3_l2'length-1), + scout => sov(perf_event_t3_offset to perf_event_t3_offset + perf_event_t3_l2'length-1), + din => perf_event_t3_d, + dout => perf_event_t3_l2); +pri_took_latch: tri_rlmreg_p + generic map (init => 65, expand_type => expand_type, width => 12) + port map ( + vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(pri_took_offset to pri_took_offset + 12-1), + scout => sov(pri_took_offset to pri_took_offset + 12-1), + din(00) => hi_did3no0_d, + din(01) => hi_did3no1_d, + din(02) => hi_did3no2_d, + din(03) => hi_did2no0_d, + din(04) => hi_did2no1_d, + din(05) => hi_did1no0_d, + din(06) => md_did3no0_d, + din(07) => md_did3no1_d, + din(08) => md_did3no2_d, + din(09) => md_did2no0_d, + din(10) => md_did2no1_d, + din(11) => md_did1no0_d, + dout(00) => hi_did3no0, + dout(01) => hi_did3no1, + dout(02) => hi_did3no2, + dout(03) => hi_did2no0, + dout(04) => hi_did2no1, + dout(05) => hi_did1no0, + dout(06) => md_did3no0, + dout(07) => md_did3no1, + dout(08) => md_did3no2, + dout(09) => md_did2no0, + dout(10) => md_did2no1, + dout(11) => md_did1no0 + ); +hi_did3no0_d <= pri_rand(0) when (spr_ic_pri_rand_always or (spr_ic_pri_rand_flush and or_reduce(xu_iu_flush_l2(0 to 3)))) = '1' else hi_did3no0_din; +hi_did3no1_d <= pri_rand(1) when (spr_ic_pri_rand_always or (spr_ic_pri_rand_flush and or_reduce(xu_iu_flush_l2(0 to 3)))) = '1' else hi_did3no1_din; +hi_did3no2_d <= pri_rand(2) when (spr_ic_pri_rand_always or (spr_ic_pri_rand_flush and or_reduce(xu_iu_flush_l2(0 to 3)))) = '1' else hi_did3no2_din; +hi_did2no0_d <= pri_rand(3) when (spr_ic_pri_rand_always or (spr_ic_pri_rand_flush and or_reduce(xu_iu_flush_l2(0 to 3)))) = '1' else hi_did2no0_din; +hi_did2no1_d <= pri_rand(4) when (spr_ic_pri_rand_always or (spr_ic_pri_rand_flush and or_reduce(xu_iu_flush_l2(0 to 3)))) = '1' else hi_did2no1_din; +hi_did1no0_d <= pri_rand(5) when (spr_ic_pri_rand_always or (spr_ic_pri_rand_flush and or_reduce(xu_iu_flush_l2(0 to 3)))) = '1' else hi_did1no0_din; +md_did3no0_d <= pri_rand(0) when (spr_ic_pri_rand_always or (spr_ic_pri_rand_flush and or_reduce(xu_iu_flush_l2(0 to 3)))) = '1' else md_did3no0_din; +md_did3no1_d <= pri_rand(1) when (spr_ic_pri_rand_always or (spr_ic_pri_rand_flush and or_reduce(xu_iu_flush_l2(0 to 3)))) = '1' else md_did3no1_din; +md_did3no2_d <= pri_rand(2) when (spr_ic_pri_rand_always or (spr_ic_pri_rand_flush and or_reduce(xu_iu_flush_l2(0 to 3)))) = '1' else md_did3no2_din; +md_did2no0_d <= pri_rand(3) when (spr_ic_pri_rand_always or (spr_ic_pri_rand_flush and or_reduce(xu_iu_flush_l2(0 to 3)))) = '1' else md_did2no0_din; +md_did2no1_d <= pri_rand(4) when (spr_ic_pri_rand_always or (spr_ic_pri_rand_flush and or_reduce(xu_iu_flush_l2(0 to 3)))) = '1' else md_did2no1_din; +md_did1no0_d <= pri_rand(5) when (spr_ic_pri_rand_always or (spr_ic_pri_rand_flush and or_reduce(xu_iu_flush_l2(0 to 3)))) = '1' else md_did1no0_din; +pri_rand(0 TO 5) <= "001000" when spr_ic_pri_rand(0 to 4) = "00000" else + "100111" when spr_ic_pri_rand(0 to 4) = "00001" else + "110111" when spr_ic_pri_rand(0 to 4) = "00010" else + "000001" when spr_ic_pri_rand(0 to 4) = "00011" else + "000110" when spr_ic_pri_rand(0 to 4) = "00100" else + "001001" when spr_ic_pri_rand(0 to 4) = "00101" else + "011000" when spr_ic_pri_rand(0 to 4) = "00110" else + "111101" when spr_ic_pri_rand(0 to 4) = "00111" else + "100101" when spr_ic_pri_rand(0 to 4) = "01000" else + "010110" when spr_ic_pri_rand(0 to 4) = "01001" else + "101101" when spr_ic_pri_rand(0 to 4) = "01010" else + "111110" when spr_ic_pri_rand(0 to 4) = "01011" else + "110110" when spr_ic_pri_rand(0 to 4) = "01100" else + "101001" when spr_ic_pri_rand(0 to 4) = "01101" else + "000000" when spr_ic_pri_rand(0 to 4) = "01110" else + "111010" when spr_ic_pri_rand(0 to 4) = "01111" else + "000111" when spr_ic_pri_rand(0 to 4) = "10000" else + "111001" when spr_ic_pri_rand(0 to 4) = "10001" else + "111000" when spr_ic_pri_rand(0 to 4) = "10010" else + "011010" when spr_ic_pri_rand(0 to 4) = "10011" else + "111111" when spr_ic_pri_rand(0 to 4) = "10100" else + "010010" when spr_ic_pri_rand(0 to 4) = "10101" else + "000010" when spr_ic_pri_rand(0 to 4) = "10110" else + "000101" when spr_ic_pri_rand(0 to 4) = "10111" else + "111111" when spr_ic_pri_rand(0 to 4) = "11000" else + "000000" when spr_ic_pri_rand(0 to 4) = "11001" else + "011010" when spr_ic_pri_rand(0 to 4) = "11010" else + "100101" when spr_ic_pri_rand(0 to 4) = "11011" else + "001001" when spr_ic_pri_rand(0 to 4) = "11100" else + "110110" when spr_ic_pri_rand(0 to 4) = "11101" else + "000111" when spr_ic_pri_rand(0 to 4) = "11110" else + "111000" ; +spr_ic_icbi_ack_en_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(spr_ic_icbi_ack_en_offset), + scout => sov(spr_ic_icbi_ack_en_offset), + din => spr_ic_icbi_ack_en, + dout => spr_ic_icbi_ack_en_l2); +spr_idir_read_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(spr_idir_read_offset), + scout => sov(spr_idir_read_offset), + din => spr_idir_read_d, + dout => spr_idir_read_l2); +spr_idir_row_latch: tri_rlmreg_p + generic map (width => spr_idir_row_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(spr_idir_row_offset to spr_idir_row_offset + spr_idir_row_l2'length-1), + scout => sov(spr_idir_row_offset to spr_idir_row_offset + spr_idir_row_l2'length-1), + din => spr_idir_row_d, + dout => spr_idir_row_l2); +xu_iu_flush_latch: tri_rlmreg_p + generic map (width => xu_iu_flush_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_iu_flush_offset to xu_iu_flush_offset + xu_iu_flush_l2'length-1), + scout => sov(xu_iu_flush_offset to xu_iu_flush_offset + xu_iu_flush_l2'length-1), + din => xu_iu_flush, + dout => xu_iu_flush_l2); +-- Note: ic_dir has spares with slp thold, if needed +spare_latch: tri_rlmreg_p + generic map (width => spare_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(spare_offset to spare_offset + spare_l2'length-1), + scout => sov(spare_offset to spare_offset + spare_l2'length-1), + din => spare_l2, + dout => spare_l2); +----------------------------------------------------------------------- +-- Scan +----------------------------------------------------------------------- +siv(0 TO scan_right) <= sov(1 to scan_right) & func_scan_in; +func_scan_out <= sov(0) and an_ac_scan_dis_dc_b; +END IUQ_IC_SELECT; diff --git a/rel/src/vhdl/work/iuq_ifetch.vhdl b/rel/src/vhdl/work/iuq_ifetch.vhdl new file mode 100644 index 0000000..3f13aa6 --- /dev/null +++ b/rel/src/vhdl/work/iuq_ifetch.vhdl @@ -0,0 +1,1968 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +--******************************************************************** +--* +--* TITLE: Instruction Fetch RLM +--* +--* NAME: iuq_ifetch.vhdl +--* +--********************************************************************* +library ieee; +use ieee.std_logic_1164.all; +library support; +use support.power_logic_pkg.all; +library work; +use work.iuq_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity iuq_ifetch is + generic(expand_type : integer := 2; + a2mode : integer := 1; + regmode : integer := 6; + threads : integer := 4; + ucode_mode : integer := 1; + bcfg_epn_0to15 : integer := 0; + bcfg_epn_16to31 : integer := 0; + bcfg_epn_32to47 : integer := (2**16)-1; + bcfg_epn_48to51 : integer := (2**4)-1; + bcfg_rpn_22to31 : integer := (2**10)-1; + bcfg_rpn_32to47 : integer := (2**16)-1; + bcfg_rpn_48to51 : integer := (2**4)-1; + uc_ifar : integer := 21); +port( + vcs : inout power_logic; + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + + tc_ac_ccflush_dc : in std_ulogic; + an_ac_scan_dis_dc_b : in std_ulogic; + an_ac_scan_diag_dc : in std_ulogic; + + pc_iu_gptr_sl_thold_4 : in std_ulogic; + pc_iu_time_sl_thold_4 : in std_ulogic; + pc_iu_repr_sl_thold_4 : in std_ulogic; + pc_iu_abst_sl_thold_4 : in std_ulogic; + pc_iu_abst_slp_sl_thold_4 : in std_ulogic; + pc_iu_bolt_sl_thold_4 : in std_ulogic; + pc_iu_regf_slp_sl_thold_4 : in std_ulogic; + pc_iu_func_sl_thold_4 : in std_ulogic; + pc_iu_func_slp_sl_thold_4 : in std_ulogic; + pc_iu_cfg_sl_thold_4 : in std_ulogic; + pc_iu_cfg_slp_sl_thold_4 : in std_ulogic; + pc_iu_func_nsl_thold_4 : in std_ulogic; + pc_iu_func_slp_nsl_thold_4 : in std_ulogic; + pc_iu_ary_nsl_thold_4 : in std_ulogic; + pc_iu_ary_slp_nsl_thold_4 : in std_ulogic; + pc_iu_sg_4 : in std_ulogic; + pc_iu_fce_4 : in std_ulogic; + + pc_iu_abist_dcomp_g6t_2r : in std_ulogic_vector(0 to 3); + pc_iu_abist_di_0 : in std_ulogic_vector(0 to 3); + pc_iu_abist_di_g6t_2r : in std_ulogic_vector(0 to 3); + pc_iu_abist_ena_dc : in std_ulogic; + pc_iu_abist_g6t_bw : in std_ulogic_vector(0 to 1); + pc_iu_abist_g6t_r_wb : in std_ulogic; + pc_iu_abist_g8t1p_renb_0 : in std_ulogic; + pc_iu_abist_g8t_bw_0 : in std_ulogic; + pc_iu_abist_g8t_bw_1 : in std_ulogic; + pc_iu_abist_g8t_dcomp : in std_ulogic_vector(0 to 3); + pc_iu_abist_g8t_wenb : in std_ulogic; + pc_iu_abist_raddr_0 : in std_ulogic_vector(2 to 9); + pc_iu_abist_raw_dc_b : in std_ulogic; + pc_iu_abist_waddr_0 : in std_ulogic_vector(3 to 9); + pc_iu_abist_wl256_comp_ena : in std_ulogic; + pc_iu_abist_wl64_comp_ena : in std_ulogic; + pc_iu_abist_wl128_comp_ena : in std_ulogic; + an_ac_lbist_ary_wrt_thru_dc: in std_ulogic; + an_ac_lbist_en_dc : in std_ulogic; + an_ac_atpg_en_dc : in std_ulogic; + an_ac_grffence_en_dc : in std_ulogic; + + pc_iu_bo_enable_4 : in std_ulogic; + pc_iu_bo_reset : in std_ulogic; + pc_iu_bo_unload : in std_ulogic; + pc_iu_bo_repair : in std_ulogic; + pc_iu_bo_shdata : in std_ulogic; + pc_iu_bo_select : in std_ulogic_vector(0 to 4); + iu_pc_bo_fail : out std_ulogic_vector(0 to 4); + iu_pc_bo_diagout : out std_ulogic_vector(0 to 4); + + iu_pc_err_icache_parity : out std_ulogic; + iu_pc_err_icachedir_parity : out std_ulogic; + iu_pc_err_icachedir_multihit : out std_ulogic; + + iu_pc_err_ucode_illegal : out std_ulogic_vector(0 to 3); + + pc_iu_inj_icache_parity : in std_ulogic; + pc_iu_inj_icachedir_parity : in std_ulogic; + pc_iu_inj_icachedir_multihit : in std_ulogic; + + pc_iu_trace_bus_enable : in std_ulogic; + pc_iu_debug_mux1_ctrls : in std_ulogic_vector(0 to 15); + pc_iu_debug_mux2_ctrls : in std_ulogic_vector(0 to 15); + debug_data_in : in std_ulogic_vector(0 to 87); + trace_triggers_in : in std_ulogic_vector(0 to 11); + debug_data_out : out std_ulogic_vector(0 to 87); + trace_triggers_out : out std_ulogic_vector(0 to 11); + pc_iu_event_mux_ctrls : in std_ulogic_vector(0 to 47); + pc_iu_event_count_mode : in std_ulogic_vector(0 to 2); + pc_iu_event_bus_enable : in std_ulogic; + iu_pc_event_data : out std_ulogic_vector(0 to 7); + + pc_iu_init_reset : in std_ulogic; + + gptr_scan_in : in std_ulogic; + time_scan_in : in std_ulogic; + repr_scan_in : in std_ulogic; + abst_scan_in : in std_ulogic_vector(0 to 2); + func_scan_in : in std_ulogic_vector(0 to 13); + ccfg_scan_in : in std_ulogic; + bcfg_scan_in : in std_ulogic; + dcfg_scan_in : in std_ulogic; + regf_scan_in : in std_ulogic_vector(0 to 4); + + gptr_scan_out : out std_ulogic; + time_scan_out : out std_ulogic; + repr_scan_out : out std_ulogic; + abst_scan_out : out std_ulogic_vector(0 to 2); + func_scan_out : out std_ulogic_vector(0 to 13); + ccfg_scan_out : out std_ulogic; + bcfg_scan_out : out std_ulogic; + dcfg_scan_out : out std_ulogic; + regf_scan_out : out std_ulogic_vector(0 to 4); + + + iuq_mi_scan_out : out std_ulogic_vector(0 to 1); + iuq_bp_scan_out : out std_ulogic; + + slowspr_val_in : in std_ulogic; + slowspr_rw_in : in std_ulogic; + slowspr_etid_in : in std_ulogic_vector(0 to 1); + slowspr_addr_in : in std_ulogic_vector(0 to 9); + slowspr_data_in : in std_ulogic_vector(64-(2**regmode) to 63); + slowspr_done_in : in std_ulogic; + + slowspr_val_out : out std_ulogic; + slowspr_rw_out : out std_ulogic; + slowspr_etid_out : out std_ulogic_vector(0 to 1); + slowspr_addr_out : out std_ulogic_vector(0 to 9); + slowspr_data_out : out std_ulogic_vector(64-(2**regmode) to 63); + slowspr_done_out : out std_ulogic; + + xu_iu_run_thread : in std_ulogic_vector(0 to 3); + xu_iu_flush : in std_ulogic_vector(0 to 3); + xu_iu_iu0_flush_ifar0 : in EFF_IFAR; + xu_iu_iu0_flush_ifar1 : in EFF_IFAR; + xu_iu_iu0_flush_ifar2 : in EFF_IFAR; + xu_iu_iu0_flush_ifar3 : in EFF_IFAR; + xu_iu_flush_2ucode : in std_ulogic_vector(0 to 3); + xu_iu_flush_2ucode_type : in std_ulogic_vector(0 to 3); + xu_iu_msr_cm : in std_ulogic_vector(0 to threads-1); + xu_iu_ex6_icbi_val : in std_ulogic_vector(0 to threads-1); + xu_iu_ex6_icbi_addr : in std_ulogic_vector(REAL_IFAR'left to 57); + xu_iu_ici : in std_ulogic; + iu_xu_request : out std_ulogic; + iu_xu_thread : out std_ulogic_vector(0 to 3); + iu_xu_ra : out std_ulogic_vector(REAL_IFAR'left to 59); + iu_xu_wimge : out std_ulogic_vector(0 to 4); + iu_xu_userdef : out std_ulogic_vector(0 to 3); + + an_ac_reld_data_vld : in std_ulogic; + an_ac_reld_core_tag : in std_ulogic_vector(0 to 4); + an_ac_reld_qw : in std_ulogic_vector(57 to 59); + an_ac_reld_data : in std_ulogic_vector(0 to 127); + an_ac_reld_ecc_err : in std_ulogic; + an_ac_reld_ecc_err_ue : in std_ulogic; + an_ac_back_inv : in std_ulogic; + an_ac_back_inv_addr : in std_ulogic_vector(REAL_IFAR'left to 63); + an_ac_back_inv_target_iiu_a: in std_ulogic_vector(0 to 1); + an_ac_back_inv_target_iiu_b: in std_ulogic_vector(3 to 4); + an_ac_icbi_ack : in std_ulogic; + an_ac_icbi_ack_thread : in std_ulogic_vector(0 to 1); + + iu_mm_ierat_req : out std_ulogic; + iu_mm_ierat_epn : out std_ulogic_vector(0 to 51); + iu_mm_ierat_thdid : out std_ulogic_vector(0 to 3); + iu_mm_ierat_state : out std_ulogic_vector(0 to 3); + iu_mm_ierat_tid : out std_ulogic_vector(0 to 13); + iu_mm_ierat_flush : out std_ulogic_vector(0 to 3); + mm_iu_ierat_rel_val : in std_ulogic_vector(0 to 4); + mm_iu_ierat_rel_data : in std_ulogic_vector(0 to 131); + mm_iu_ierat_snoop_coming : in std_ulogic; + mm_iu_ierat_snoop_val : in std_ulogic; + mm_iu_ierat_snoop_attr : in std_ulogic_vector(0 to 25); + mm_iu_ierat_snoop_vpn : in std_ulogic_vector(EFF_IFAR'left to 51); + iu_mm_ierat_snoop_ack : out std_ulogic; + mm_iu_ierat_pid0 : in std_ulogic_vector(0 to 13); + mm_iu_ierat_pid1 : in std_ulogic_vector(0 to 13); + mm_iu_ierat_pid2 : in std_ulogic_vector(0 to 13); + mm_iu_ierat_pid3 : in std_ulogic_vector(0 to 13); + mm_iu_ierat_mmucr0_0 : in std_ulogic_vector(0 to 19); + mm_iu_ierat_mmucr0_1 : in std_ulogic_vector(0 to 19); + mm_iu_ierat_mmucr0_2 : in std_ulogic_vector(0 to 19); + mm_iu_ierat_mmucr0_3 : in std_ulogic_vector(0 to 19); + iu_mm_ierat_mmucr0 : out std_ulogic_vector(0 to 17); + iu_mm_ierat_mmucr0_we : out std_ulogic_vector(0 to 3); + mm_iu_ierat_mmucr1 : in std_ulogic_vector(0 to 8); + iu_mm_ierat_mmucr1 : out std_ulogic_vector(0 to 3); + iu_mm_ierat_mmucr1_we : out std_ulogic; + iu_mm_lmq_empty : out std_ulogic; + + xu_iu_ex1_rb : in std_ulogic_vector(64-(2**regmode) to 51); + xu_rf1_flush : in std_ulogic_vector(0 to 3); + xu_ex1_flush : in std_ulogic_vector(0 to 3); + xu_ex2_flush : in std_ulogic_vector(0 to 3); + xu_ex3_flush : in std_ulogic_vector(0 to 3); + xu_ex4_flush : in std_ulogic_vector(0 to 3); + xu_ex5_flush : in std_ulogic_vector(0 to 3); + xu_iu_ex4_rs_data : in std_ulogic_vector(64-(2**regmode) to 63); + xu_iu_hid_mmu_mode : in std_ulogic; + xu_iu_msr_hv : in std_ulogic_vector(0 to threads-1); + xu_iu_msr_is : in std_ulogic_vector(0 to threads-1); + xu_iu_msr_pr : in std_ulogic_vector(0 to threads-1); + xu_iu_spr_ccr2_ifratsc : in std_ulogic_vector(0 to 8); + xu_iu_spr_ccr2_ifrat : in std_ulogic; + xu_iu_xucr4_mmu_mchk : in std_ulogic; + xu_iu_rf1_val : in std_ulogic_vector(0 to 3); + xu_iu_rf1_is_eratre : in std_ulogic; + xu_iu_rf1_is_eratsx : in std_ulogic; + xu_iu_rf1_is_eratwe : in std_ulogic; + xu_iu_rf1_is_eratilx : in std_ulogic; + xu_iu_ex1_is_isync : in std_ulogic; + xu_iu_ex1_is_csync : in std_ulogic; + xu_iu_rf1_ws : in std_ulogic_vector(0 to 1); + xu_iu_rf1_t : in std_ulogic_vector(0 to 2); + xu_iu_ex1_ra_entry : in std_ulogic_vector(8 to 11); + xu_iu_ex1_rs_is : in std_ulogic_vector(0 to 8); + iu_xu_ex4_tlb_data : out std_ulogic_vector(64-(2**regmode) to 63); + iu_xu_ierat_ex3_par_err : out std_ulogic_vector(0 to threads-1); + iu_xu_ierat_ex4_par_err : out std_ulogic_vector(0 to threads-1); + iu_xu_ierat_ex2_flush_req : out std_ulogic_vector(0 to threads-1); + + xu_iu_ex5_ifar : in EFF_IFAR; + xu_iu_ex5_tid : in std_ulogic_vector(0 to 3); + xu_iu_ex5_val : in std_ulogic; + xu_iu_ex5_br_update : in std_ulogic; + xu_iu_ex5_br_hist : in std_ulogic_vector(0 to 1); + xu_iu_ex5_br_taken : in std_ulogic; + xu_iu_ex5_bclr : in std_ulogic; + xu_iu_ex5_getNIA : in std_ulogic; + xu_iu_ex5_lk : in std_ulogic; + xu_iu_ex5_bh : in std_ulogic_vector(0 to 1); + xu_iu_ex5_gshare : in std_ulogic_vector(0 to 3); + + pc_iu_ram_instr : in std_ulogic_vector(0 to 31); + pc_iu_ram_instr_ext : in std_ulogic_vector(0 to 3); + pc_iu_ram_force_cmplt : in std_ulogic; + xu_iu_ram_issue : in std_ulogic_vector(0 to 3); + + xu_iu_ex6_pri : in std_ulogic_vector(0 to 2); + xu_iu_ex6_pri_val : in std_ulogic_vector(0 to 3); + xu_iu_raise_iss_pri : in std_ulogic_vector(0 to 3); + xu_iu_msr_gs : in std_ulogic_vector(0 to 3); + + xu_iu_ucode_restart : in std_ulogic_vector(0 to 3); + xu_iu_spr_xer0 : in std_ulogic_vector(57 to 63); + xu_iu_spr_xer1 : in std_ulogic_vector(57 to 63); + xu_iu_spr_xer2 : in std_ulogic_vector(57 to 63); + xu_iu_spr_xer3 : in std_ulogic_vector(57 to 63); + xu_iu_uc_flush_ifar0 : in std_ulogic_vector(62-uc_ifar to 61); + xu_iu_uc_flush_ifar1 : in std_ulogic_vector(62-uc_ifar to 61); + xu_iu_uc_flush_ifar2 : in std_ulogic_vector(62-uc_ifar to 61); + xu_iu_uc_flush_ifar3 : in std_ulogic_vector(62-uc_ifar to 61); + + rtim_sl_thold_7 : in std_ulogic; + func_sl_thold_7 : in std_ulogic; + func_nsl_thold_7 : in std_ulogic; + ary_nsl_thold_7 : in std_ulogic; + sg_7 : in std_ulogic; + fce_7 : in std_ulogic; + rtim_sl_thold_6 : out std_ulogic; + func_sl_thold_6 : out std_ulogic; + func_nsl_thold_6 : out std_ulogic; + ary_nsl_thold_6 : out std_ulogic; + sg_6 : out std_ulogic; + fce_6 : out std_ulogic; + an_ac_scom_dch : in std_ulogic; + an_ac_scom_cch : in std_ulogic; + an_ac_checkstop : in std_ulogic; + an_ac_debug_stop : in std_ulogic; + an_ac_pm_thread_stop : in std_ulogic_vector(0 to 3); + an_ac_reset_1_complete : in std_ulogic; + an_ac_reset_2_complete : in std_ulogic; + an_ac_reset_3_complete : in std_ulogic; + an_ac_reset_wd_complete : in std_ulogic; + an_ac_abist_start_test : in std_ulogic; + ac_rp_trace_to_perfcntr : in std_ulogic_vector(0 to 7); + rp_pc_scom_dch_q : out std_ulogic; + rp_pc_scom_cch_q : out std_ulogic; + rp_pc_checkstop_q : out std_ulogic; + rp_pc_debug_stop_q : out std_ulogic; + rp_pc_pm_thread_stop_q : out std_ulogic_vector(0 to 3); + rp_pc_reset_1_complete_q : out std_ulogic; + rp_pc_reset_2_complete_q : out std_ulogic; + rp_pc_reset_3_complete_q : out std_ulogic; + rp_pc_reset_wd_complete_q : out std_ulogic; + rp_pc_abist_start_test_q : out std_ulogic; + rp_pc_trace_to_perfcntr_q : out std_ulogic_vector(0 to 7); + pc_rp_scom_dch : in std_ulogic; + pc_rp_scom_cch : in std_ulogic; + pc_rp_special_attn : in std_ulogic_vector(0 to 3); + pc_rp_checkstop : in std_ulogic_vector(0 to 2); + pc_rp_local_checkstop : in std_ulogic_vector(0 to 2); + pc_rp_recov_err : in std_ulogic_vector(0 to 2); + pc_rp_trace_error : in std_ulogic; + pc_rp_event_bus_enable : in std_ulogic; + pc_rp_event_bus : in std_ulogic_vector(0 to 7); + pc_rp_fu_bypass_events : in std_ulogic_vector(0 to 7); + pc_rp_iu_bypass_events : in std_ulogic_vector(0 to 7); + pc_rp_mm_bypass_events : in std_ulogic_vector(0 to 7); + pc_rp_lsu_bypass_events : in std_ulogic_vector(0 to 7); + pc_rp_pm_thread_running : in std_ulogic_vector(0 to 3); + pc_rp_power_managed : in std_ulogic; + pc_rp_rvwinkle_mode : in std_ulogic; + ac_an_scom_dch_q : out std_ulogic; + ac_an_scom_cch_q : out std_ulogic; + ac_an_special_attn_q : out std_ulogic_vector(0 to 3); + ac_an_checkstop_q : out std_ulogic_vector(0 to 2); + ac_an_local_checkstop_q : out std_ulogic_vector(0 to 2); + ac_an_recov_err_q : out std_ulogic_vector(0 to 2); + ac_an_trace_error_q : out std_ulogic; + rp_mm_event_bus_enable_q : out std_ulogic; + ac_an_event_bus_q : out std_ulogic_vector(0 to 7); + ac_an_fu_bypass_events_q : out std_ulogic_vector(0 to 7); + ac_an_iu_bypass_events_q : out std_ulogic_vector(0 to 7); + ac_an_mm_bypass_events_q : out std_ulogic_vector(0 to 7); + ac_an_lsu_bypass_events_q : out std_ulogic_vector(0 to 7); + ac_an_pm_thread_running_q : out std_ulogic_vector(0 to 3); + ac_an_power_managed_q : out std_ulogic; + ac_an_rvwinkle_mode_q : out std_ulogic; + + pc_func_scan_in : in std_ulogic_vector(0 to 1); + pc_func_scan_in_q : out std_ulogic_vector(0 to 1); + pc_func_scan_out : in std_ulogic; + pc_func_scan_out_q : out std_ulogic; + pc_bcfg_scan_in : in std_ulogic; + pc_bcfg_scan_in_q : out std_ulogic; + pc_dcfg_scan_in : in std_ulogic; + pc_dcfg_scan_in_q : out std_ulogic; + pc_bcfg_scan_out : in std_ulogic; + pc_bcfg_scan_out_q : out std_ulogic; + pc_ccfg_scan_out : in std_ulogic; + pc_ccfg_scan_out_q : out std_ulogic; + pc_dcfg_scan_out : in std_ulogic; + pc_dcfg_scan_out_q : out std_ulogic; + fu_abst_scan_in : in std_ulogic; + fu_abst_scan_in_q : out std_ulogic; + fu_abst_scan_out : in std_ulogic; + fu_abst_scan_out_q : out std_ulogic; + fu_ccfg_scan_out : in std_ulogic; + fu_ccfg_scan_out_q : out std_ulogic; + fu_bcfg_scan_out : in std_ulogic; + fu_bcfg_scan_out_q : out std_ulogic; + fu_dcfg_scan_out : in std_ulogic; + fu_dcfg_scan_out_q : out std_ulogic; + fu_func_scan_in : in std_ulogic_vector(0 to 3); + fu_func_scan_in_q : out std_ulogic_vector(0 to 3); + fu_func_scan_out : in std_ulogic_vector(0 to 3); + fu_func_scan_out_q : out std_ulogic_vector(0 to 3); + bx_abst_scan_in : in std_ulogic; + bx_abst_scan_in_q : out std_ulogic; + bx_abst_scan_out : in std_ulogic; + bx_abst_scan_out_q : out std_ulogic; + bx_func_scan_in : in std_ulogic_vector(0 to 1); + bx_func_scan_in_q : out std_ulogic_vector(0 to 1); + bx_func_scan_out : in std_ulogic_vector(0 to 1); + bx_func_scan_out_q : out std_ulogic_vector(0 to 1); + iu_func_scan_in_q : out std_ulogic_vector(0 to 4); + iu_func_scan_out : in std_ulogic_vector(0 to 7); + spare_func_scan_in : in std_ulogic_vector(0 to 3); + spare_func_scan_out_q : out std_ulogic_vector(0 to 3); + rp_abst_scan_in : in std_ulogic; + rp_func_scan_in : in std_ulogic; + rp_abst_scan_out : out std_ulogic; + rp_func_scan_out : out std_ulogic; + + bg_an_ac_func_scan_sn : in std_ulogic_vector(60 to 69); + bg_an_ac_abst_scan_sn : in std_ulogic_vector(10 to 11); + bg_an_ac_func_scan_sn_q : out std_ulogic_vector(60 to 69); + bg_an_ac_abst_scan_sn_q : out std_ulogic_vector(10 to 11); + + bg_ac_an_func_scan_ns : in std_ulogic_vector(60 to 69); + bg_ac_an_abst_scan_ns : in std_ulogic_vector(10 to 11); + bg_ac_an_func_scan_ns_q : out std_ulogic_vector(60 to 69); + bg_ac_an_abst_scan_ns_q : out std_ulogic_vector(10 to 11); + + bg_pc_l1p_abist_di_0 : in std_ulogic_vector(0 to 3); + bg_pc_l1p_abist_g8t1p_renb_0 : in std_ulogic; + bg_pc_l1p_abist_g8t_bw_0 : in std_ulogic; + bg_pc_l1p_abist_g8t_bw_1 : in std_ulogic; + bg_pc_l1p_abist_g8t_dcomp : in std_ulogic_vector(0 to 3); + bg_pc_l1p_abist_g8t_wenb : in std_ulogic; + bg_pc_l1p_abist_raddr_0 : in std_ulogic_vector(0 to 9); + bg_pc_l1p_abist_waddr_0 : in std_ulogic_vector(0 to 9); + bg_pc_l1p_abist_wl128_comp_ena : in std_ulogic; + bg_pc_l1p_abist_wl32_comp_ena : in std_ulogic; + bg_pc_l1p_abist_di_0_q : out std_ulogic_vector(0 to 3); + bg_pc_l1p_abist_g8t1p_renb_0_q : out std_ulogic; + bg_pc_l1p_abist_g8t_bw_0_q : out std_ulogic; + bg_pc_l1p_abist_g8t_bw_1_q : out std_ulogic; + bg_pc_l1p_abist_g8t_dcomp_q: out std_ulogic_vector(0 to 3); + bg_pc_l1p_abist_g8t_wenb_q : out std_ulogic; + bg_pc_l1p_abist_raddr_0_q : out std_ulogic_vector(0 to 9); + bg_pc_l1p_abist_waddr_0_q : out std_ulogic_vector(0 to 9); + bg_pc_l1p_abist_wl128_comp_ena_q : out std_ulogic; + bg_pc_l1p_abist_wl32_comp_ena_q : out std_ulogic; + + bg_pc_l1p_gptr_sl_thold_3 : in std_ulogic; + bg_pc_l1p_time_sl_thold_3 : in std_ulogic; + bg_pc_l1p_repr_sl_thold_3 : in std_ulogic; + bg_pc_l1p_abst_sl_thold_3 : in std_ulogic; + bg_pc_l1p_func_sl_thold_3 : in std_ulogic_vector(0 to 1); + bg_pc_l1p_func_slp_sl_thold_3 : in std_ulogic; + bg_pc_l1p_bolt_sl_thold_3 : in std_ulogic; + bg_pc_l1p_ary_nsl_thold_3 : in std_ulogic; + bg_pc_l1p_sg_3 : in std_ulogic_vector(0 to 1); + bg_pc_l1p_fce_3 : in std_ulogic; + bg_pc_l1p_bo_enable_3 : in std_ulogic; + bg_pc_l1p_gptr_sl_thold_2 : out std_ulogic; + bg_pc_l1p_time_sl_thold_2 : out std_ulogic; + bg_pc_l1p_repr_sl_thold_2 : out std_ulogic; + bg_pc_l1p_abst_sl_thold_2 : out std_ulogic; + bg_pc_l1p_func_sl_thold_2 : out std_ulogic_vector(0 to 1); + bg_pc_l1p_func_slp_sl_thold_2 : out std_ulogic; + bg_pc_l1p_bolt_sl_thold_2 : out std_ulogic; + bg_pc_l1p_ary_nsl_thold_2 : out std_ulogic; + bg_pc_l1p_sg_2 : out std_ulogic_vector(0 to 1); + bg_pc_l1p_fce_2 : out std_ulogic; + bg_pc_l1p_bo_enable_2 : out std_ulogic; + + + bg_pc_bo_unload_iiu : in std_ulogic; + bg_pc_bo_load_iiu : in std_ulogic; + bg_pc_bo_repair_iiu : in std_ulogic; + bg_pc_bo_reset_iiu : in std_ulogic; + bg_pc_bo_shdata_iiu : in std_ulogic; + bg_pc_bo_select_iiu : in std_ulogic_vector(0 to 10); + bg_pc_l1p_ccflush_dc_iiu : in std_ulogic; + bg_pc_l1p_abist_ena_dc_iiu : in std_ulogic; + bg_pc_l1p_abist_raw_dc_b_iiu : in std_ulogic; + + bg_pc_bo_unload_oiu : out std_ulogic; + bg_pc_bo_load_oiu : out std_ulogic; + bg_pc_bo_repair_oiu : out std_ulogic; + bg_pc_bo_reset_oiu : out std_ulogic; + bg_pc_bo_shdata_oiu : out std_ulogic; + bg_pc_bo_select_oiu : out std_ulogic_vector(0 to 10); + bg_pc_l1p_ccflush_dc_oiu : out std_ulogic; + bg_pc_l1p_abist_ena_dc_oiu : out std_ulogic; + bg_pc_l1p_abist_raw_dc_b_oiu : out std_ulogic; + + ac_an_abist_done_dc_iiu : in std_ulogic; + ac_an_psro_ringsig_iiu : in std_ulogic; + mm_pc_bo_fail_iiu : in std_ulogic_vector(0 to 4); + mm_pc_bo_diagout_iiu : in std_ulogic_vector(0 to 4); + mm_pc_event_data_iiu : in std_ulogic_vector(0 to 7); + + ac_an_abist_done_dc_oiu : out std_ulogic; + ac_an_psro_ringsig_oiu : out std_ulogic; + mm_pc_bo_fail_oiu : out std_ulogic_vector(0 to 4); + mm_pc_bo_diagout_oiu : out std_ulogic_vector(0 to 4); + mm_pc_event_data_oiu : out std_ulogic_vector(0 to 7); + + bg_pc_bo_fail_iiu : in std_ulogic_vector(0 to 10); + bg_pc_bo_diagout_iiu : in std_ulogic_vector(0 to 10); + + bg_pc_bo_fail_oiu : out std_ulogic_vector(0 to 10); + bg_pc_bo_diagout_oiu : out std_ulogic_vector(0 to 10); + + an_ac_abist_mode_dc_iiu : in std_ulogic; + an_ac_ccenable_dc_iiu : in std_ulogic; + an_ac_ccflush_dc_iiu : in std_ulogic; + an_ac_gsd_test_enable_dc_iiu : in std_ulogic; + an_ac_gsd_test_acmode_dc_iiu : in std_ulogic; + an_ac_lbist_ip_dc_iiu : in std_ulogic; + an_ac_lbist_ac_mode_dc_iiu : in std_ulogic; + an_ac_malf_alert_iiu : in std_ulogic; + an_ac_psro_enable_dc_iiu : in std_ulogic_vector(0 to 2); + an_ac_scan_type_dc_iiu : in std_ulogic_vector(0 to 8); + an_ac_scom_sat_id_iiu : in std_ulogic_vector(0 to 3); + + pc_mm_abist_dcomp_g6t_2r_iiu : in std_ulogic_vector(0 to 3); + pc_mm_abist_di_g6t_2r_iiu : in std_ulogic_vector(0 to 3); + pc_mm_abist_di_0_iiu : in std_ulogic_vector(0 to 3); + pc_mm_abist_ena_dc_iiu : in std_ulogic; + pc_mm_abist_g6t_r_wb_iiu : in std_ulogic; + pc_mm_abist_g8t_bw_0_iiu : in std_ulogic; + pc_mm_abist_g8t_bw_1_iiu : in std_ulogic; + pc_mm_abist_g8t_dcomp_iiu : in std_ulogic_vector(0 to 3); + pc_mm_abist_g8t_wenb_iiu : in std_ulogic; + pc_mm_abist_g8t1p_renb_0_iiu : in std_ulogic; + pc_mm_abist_raddr_0_iiu : in std_ulogic_vector(0 to 9); + pc_mm_abist_raw_dc_b_iiu : in std_ulogic; + pc_mm_abist_waddr_0_iiu : in std_ulogic_vector(0 to 9); + pc_mm_abist_wl128_comp_ena_iiu : in std_ulogic; + pc_mm_bo_enable_4_iiu : in std_ulogic; + pc_mm_bo_repair_iiu : in std_ulogic; + pc_mm_bo_reset_iiu : in std_ulogic; + pc_mm_bo_select_iiu : in std_ulogic_vector(0 to 4); + pc_mm_bo_shdata_iiu : in std_ulogic; + pc_mm_bo_unload_iiu : in std_ulogic; + pc_mm_ccflush_dc_iiu : in std_ulogic; + pc_mm_debug_mux1_ctrls_iiu : in std_ulogic_vector(0 to 15); + pc_mm_event_count_mode_iiu : in std_ulogic_vector(0 to 2); + pc_mm_event_mux_ctrls_iiu : in std_ulogic_vector(0 to 39); + pc_mm_trace_bus_enable_iiu : in std_ulogic; + + an_ac_abist_mode_dc_oiu : out std_ulogic; + an_ac_ccenable_dc_oiu : out std_ulogic; + an_ac_ccflush_dc_oiu : out std_ulogic; + an_ac_gsd_test_enable_dc_oiu : out std_ulogic; + an_ac_gsd_test_acmode_dc_oiu : out std_ulogic; + an_ac_lbist_ip_dc_oiu : out std_ulogic; + an_ac_lbist_ac_mode_dc_oiu : out std_ulogic; + an_ac_malf_alert_oiu : out std_ulogic; + an_ac_psro_enable_dc_oiu : out std_ulogic_vector(0 to 2); + an_ac_scan_type_dc_oiu : out std_ulogic_vector(0 to 8); + an_ac_scom_sat_id_oiu : out std_ulogic_vector(0 to 3); + + pc_mm_abist_dcomp_g6t_2r_oiu : out std_ulogic_vector(0 to 3); + pc_mm_abist_di_g6t_2r_oiu : out std_ulogic_vector(0 to 3); + pc_mm_abist_di_0_oiu : out std_ulogic_vector(0 to 3); + pc_mm_abist_ena_dc_oiu : out std_ulogic; + pc_mm_abist_g6t_r_wb_oiu : out std_ulogic; + pc_mm_abist_g8t_bw_0_oiu : out std_ulogic; + pc_mm_abist_g8t_bw_1_oiu : out std_ulogic; + pc_mm_abist_g8t_dcomp_oiu : out std_ulogic_vector(0 to 3); + pc_mm_abist_g8t_wenb_oiu : out std_ulogic; + pc_mm_abist_g8t1p_renb_0_oiu : out std_ulogic; + pc_mm_abist_raddr_0_oiu : out std_ulogic_vector(0 to 9); + pc_mm_abist_raw_dc_b_oiu : out std_ulogic; + pc_mm_abist_waddr_0_oiu : out std_ulogic_vector(0 to 9); + pc_mm_abist_wl128_comp_ena_oiu : out std_ulogic; + pc_mm_abst_sl_thold_3_oiu : out std_ulogic; + pc_mm_abst_slp_sl_thold_3_oiu : out std_ulogic; + pc_mm_ary_nsl_thold_3_oiu : out std_ulogic; + pc_mm_ary_slp_nsl_thold_3_oiu : out std_ulogic; + pc_mm_bo_enable_3_oiu : out std_ulogic; + pc_mm_bo_repair_oiu : out std_ulogic; + pc_mm_bo_reset_oiu : out std_ulogic; + pc_mm_bo_select_oiu : out std_ulogic_vector(0 to 4); + pc_mm_bo_shdata_oiu : out std_ulogic; + pc_mm_bo_unload_oiu : out std_ulogic; + pc_mm_bolt_sl_thold_3_oiu : out std_ulogic; + pc_mm_ccflush_dc_oiu : out std_ulogic; + pc_mm_cfg_sl_thold_3_oiu : out std_ulogic; + pc_mm_cfg_slp_sl_thold_3_oiu : out std_ulogic; + pc_mm_debug_mux1_ctrls_oiu : out std_ulogic_vector(0 to 15); + pc_mm_event_count_mode_oiu : out std_ulogic_vector(0 to 2); + pc_mm_event_mux_ctrls_oiu : out std_ulogic_vector(0 to 39); + pc_mm_fce_3_oiu : out std_ulogic; + pc_mm_func_nsl_thold_3_oiu : out std_ulogic; + pc_mm_func_sl_thold_3_oiu : out std_ulogic_vector(0 to 1); + pc_mm_func_slp_nsl_thold_3_oiu : out std_ulogic; + pc_mm_func_slp_sl_thold_3_oiu : out std_ulogic_vector(0 to 1); + pc_mm_gptr_sl_thold_3_oiu : out std_ulogic; + pc_mm_repr_sl_thold_3_oiu : out std_ulogic; + pc_mm_sg_3_oiu : out std_ulogic_vector(0 to 1); + pc_mm_time_sl_thold_3_oiu : out std_ulogic; + pc_mm_trace_bus_enable_oiu : out std_ulogic; + + an_ac_back_inv_oiu : out std_ulogic; + an_ac_back_inv_addr_oiu : out std_ulogic_vector(REAL_IFAR'left to 63); + an_ac_back_inv_target_bit1_oiu : out std_ulogic; + an_ac_back_inv_target_bit3_oiu : out std_ulogic; + an_ac_back_inv_target_bit4_oiu : out std_ulogic; + an_ac_atpg_en_dc_oiu : out std_ulogic; + an_ac_lbist_ary_wrt_thru_dc_oiu : out std_ulogic; + an_ac_lbist_en_dc_oiu : out std_ulogic; + an_ac_scan_diag_dc_oiu : out std_ulogic; + an_ac_scan_dis_dc_b_oiu : out std_ulogic; + an_ac_grffence_en_dc_oiu : out std_ulogic; + + an_ac_sync_ack : in std_ulogic_vector(0 to 3); + mm_iu_barrier_done : in std_ulogic_vector(0 to 3); + + an_ac_scan_dis_dc_b_oif : out std_ulogic_vector(0 to 3); + an_ac_back_inv_oif : out std_ulogic; + an_ac_back_inv_target_oif : out std_ulogic_vector(1 to 1); + an_ac_sync_ack_oif : out std_ulogic_vector(0 to 3); + mm_iu_barrier_done_oif : out std_ulogic_vector(0 to 3); + + pc_iu_sg_2 : out std_ulogic_vector(0 to 3); + pc_iu_func_sl_thold_2 : out std_ulogic_vector(0 to 3); + + clkoff_b : out std_ulogic_vector(0 to 3); + delay_lclkr : out std_ulogic_vector(5 to 14); + mpw1_b : out std_ulogic_vector(5 to 14); + + fiss_dbg_data : in std_ulogic_vector(0 to 87); + fdep_dbg_data : in std_ulogic_vector(0 to 87); + ib_dbg_data : in std_ulogic_vector(0 to 63); + fu_iss_dbg_data : in std_ulogic_vector(0 to 23); + axu_dbg_data_t0 : in std_ulogic_vector(0 to 37); + axu_dbg_data_t1 : in std_ulogic_vector(0 to 37); + axu_dbg_data_t2 : in std_ulogic_vector(0 to 37); + axu_dbg_data_t3 : in std_ulogic_vector(0 to 37); + + ib_perf_event_t0 : in std_ulogic_vector(0 to 1); + ib_perf_event_t1 : in std_ulogic_vector(0 to 1); + ib_perf_event_t2 : in std_ulogic_vector(0 to 1); + ib_perf_event_t3 : in std_ulogic_vector(0 to 1); + fdep_perf_event_t0 : in std_ulogic_vector(0 to 11); + fdep_perf_event_t1 : in std_ulogic_vector(0 to 11); + fdep_perf_event_t2 : in std_ulogic_vector(0 to 11); + fdep_perf_event_t3 : in std_ulogic_vector(0 to 11); + fiss_perf_event_t0 : in std_ulogic_vector(0 to 7); + fiss_perf_event_t1 : in std_ulogic_vector(0 to 7); + fiss_perf_event_t2 : in std_ulogic_vector(0 to 7); + fiss_perf_event_t3 : in std_ulogic_vector(0 to 7); + + ib_ic_empty : in std_ulogic_vector(0 to 3); + ib_ic_below_water : in std_ulogic_vector(0 to 3); + ib_ic_iu5_redirect_tid : in std_ulogic_vector(0 to 3); + + bp_ib_iu4_t0_val : out std_ulogic_vector(0 to 3); + bp_ib_iu4_t1_val : out std_ulogic_vector(0 to 3); + bp_ib_iu4_t2_val : out std_ulogic_vector(0 to 3); + bp_ib_iu4_t3_val : out std_ulogic_vector(0 to 3); + bp_ib_iu4_ifar_t0 : out EFF_IFAR; + bp_ib_iu3_0_instr_t0 : out std_ulogic_vector(0 to 31); + bp_ib_iu4_0_instr_t0 : out std_ulogic_vector(32 to 43); + bp_ib_iu4_1_instr_t0 : out std_ulogic_vector(0 to 43); + bp_ib_iu4_2_instr_t0 : out std_ulogic_vector(0 to 43); + bp_ib_iu4_3_instr_t0 : out std_ulogic_vector(0 to 43); + bp_ib_iu4_ifar_t1 : out EFF_IFAR; + bp_ib_iu3_0_instr_t1 : out std_ulogic_vector(0 to 31); + bp_ib_iu4_0_instr_t1 : out std_ulogic_vector(32 to 43); + bp_ib_iu4_1_instr_t1 : out std_ulogic_vector(0 to 43); + bp_ib_iu4_2_instr_t1 : out std_ulogic_vector(0 to 43); + bp_ib_iu4_3_instr_t1 : out std_ulogic_vector(0 to 43); + bp_ib_iu4_ifar_t2 : out EFF_IFAR; + bp_ib_iu3_0_instr_t2 : out std_ulogic_vector(0 to 31); + bp_ib_iu4_0_instr_t2 : out std_ulogic_vector(32 to 43); + bp_ib_iu4_1_instr_t2 : out std_ulogic_vector(0 to 43); + bp_ib_iu4_2_instr_t2 : out std_ulogic_vector(0 to 43); + bp_ib_iu4_3_instr_t2 : out std_ulogic_vector(0 to 43); + bp_ib_iu4_ifar_t3 : out EFF_IFAR; + bp_ib_iu3_0_instr_t3 : out std_ulogic_vector(0 to 31); + bp_ib_iu4_0_instr_t3 : out std_ulogic_vector(32 to 43); + bp_ib_iu4_1_instr_t3 : out std_ulogic_vector(0 to 43); + bp_ib_iu4_2_instr_t3 : out std_ulogic_vector(0 to 43); + bp_ib_iu4_3_instr_t3 : out std_ulogic_vector(0 to 43); + + uc_ib_iu4_val : out std_ulogic_vector(0 to 3); + uc_ib_iu4_ifar_t0 : out std_ulogic_vector(62-uc_ifar to 61); + uc_ib_iu4_instr_t0 : out std_ulogic_vector(0 to 36); + uc_ib_iu4_ifar_t1 : out std_ulogic_vector(62-uc_ifar to 61); + uc_ib_iu4_instr_t1 : out std_ulogic_vector(0 to 36); + uc_ib_iu4_ifar_t2 : out std_ulogic_vector(62-uc_ifar to 61); + uc_ib_iu4_instr_t2 : out std_ulogic_vector(0 to 36); + uc_ib_iu4_ifar_t3 : out std_ulogic_vector(62-uc_ifar to 61); + uc_ib_iu4_instr_t3 : out std_ulogic_vector(0 to 36); + + rm_ib_iu4_val : out std_ulogic_vector(0 to 3); + rm_ib_iu4_force_ram_t0 : out std_ulogic; + rm_ib_iu4_instr_t0 : out std_ulogic_vector(0 to 35); + rm_ib_iu4_force_ram_t1 : out std_ulogic; + rm_ib_iu4_instr_t1 : out std_ulogic_vector(0 to 35); + rm_ib_iu4_force_ram_t2 : out std_ulogic; + rm_ib_iu4_instr_t2 : out std_ulogic_vector(0 to 35); + rm_ib_iu4_force_ram_t3 : out std_ulogic; + rm_ib_iu4_instr_t3 : out std_ulogic_vector(0 to 35); + + iu_au_config_iucr_t0 : out std_ulogic_vector(0 to 7); + iu_au_config_iucr_t1 : out std_ulogic_vector(0 to 7); + iu_au_config_iucr_t2 : out std_ulogic_vector(0 to 7); + iu_au_config_iucr_t3 : out std_ulogic_vector(0 to 7); + + spr_issue_high_mask : out std_ulogic_vector(0 to 3); + spr_issue_med_mask : out std_ulogic_vector(0 to 3); + spr_fiss_count0_max : out std_ulogic_vector(0 to 5); + spr_fiss_count1_max : out std_ulogic_vector(0 to 5); + spr_fiss_count2_max : out std_ulogic_vector(0 to 5); + spr_fiss_count3_max : out std_ulogic_vector(0 to 5); + spr_fiss_pri_rand : out std_ulogic_vector(0 to 4); + spr_fiss_pri_rand_always : out std_ulogic; + spr_fiss_pri_rand_flush : out std_ulogic; + spr_dec_mask_t0 : out std_ulogic_vector(0 to 31); + spr_dec_mask_t1 : out std_ulogic_vector(0 to 31); + spr_dec_mask_t2 : out std_ulogic_vector(0 to 31); + spr_dec_mask_t3 : out std_ulogic_vector(0 to 31); + spr_dec_match_t0 : out std_ulogic_vector(0 to 31); + spr_dec_match_t1 : out std_ulogic_vector(0 to 31); + spr_dec_match_t2 : out std_ulogic_vector(0 to 31); + spr_dec_match_t3 : out std_ulogic_vector(0 to 31); + spr_fdep_ll_hold_t0 : out std_ulogic; + spr_fdep_ll_hold_t1 : out std_ulogic; + spr_fdep_ll_hold_t2 : out std_ulogic; + spr_fdep_ll_hold_t3 : out std_ulogic; + + ic_fdep_load_quiesce : out std_ulogic_vector(0 to 3); + ic_fdep_icbi_ack : out std_ulogic_vector(0 to 3); + + fiss_uc_is2_ucode_vld : in std_ulogic; + fiss_uc_is2_tid : in std_ulogic_vector(0 to 3); + fiss_uc_is2_instr : in std_ulogic_vector(0 to 31); + fiss_uc_is2_2ucode : in std_ulogic; + fiss_uc_is2_2ucode_type : in std_ulogic; + + uc_flush_tid : out std_ulogic_vector(0 to 3) + +); +-- synopsys translate_off +-- synopsys translate_on +end iuq_ifetch; +architecture iuq_ifetch of iuq_ifetch is +signal int_clkoff_b : std_ulogic_vector(0 to 2); +signal int_delay_lclkr : std_ulogic_vector(1 to 14); +signal int_mpw1_b : std_ulogic_vector(1 to 14); +signal g8t_clkoff_b : std_ulogic; +signal g8t_d_mode : std_ulogic; +signal g8t_delay_lclkr : std_ulogic_vector(0 to 4); +signal g8t_mpw1_b : std_ulogic_vector(0 to 4); +signal g8t_mpw2_b : std_ulogic; +signal g6t_clkoff_b : std_ulogic; +signal g6t_d_mode : std_ulogic; +signal g6t_delay_lclkr : std_ulogic_vector(0 to 3); +signal g6t_mpw1_b : std_ulogic_vector(0 to 4); +signal g6t_mpw2_b : std_ulogic; +signal cam_clkoff_b : std_ulogic; +signal cam_d_mode : std_ulogic; +signal cam_delay_lclkr : std_ulogic_vector(0 to 4); +signal cam_mpw1_b : std_ulogic_vector(0 to 4); +signal cam_mpw2_b : std_ulogic; +signal int_pc_iu_sg_2 : std_ulogic_vector(0 to 3); +signal pc_iu_fce_2 : std_ulogic; +signal int_pc_iu_func_sl_thold_2 : std_ulogic_vector(0 to 3); +signal pc_iu_func_slp_sl_thold_2: std_ulogic; +signal pc_iu_regf_slp_sl_thold_2: std_ulogic; +signal pc_iu_time_sl_thold_2 : std_ulogic; +signal pc_iu_repr_sl_thold_2 : std_ulogic; +signal pc_iu_abst_sl_thold_2 : std_ulogic; +signal pc_iu_abst_slp_sl_thold_2: std_ulogic; +signal pc_iu_cfg_slp_sl_thold_2 : std_ulogic; +signal pc_iu_ary_nsl_thold_2 : std_ulogic; +signal pc_iu_ary_slp_nsl_thold_2: std_ulogic; +signal pc_iu_func_slp_nsl_thold_2 : std_ulogic; +signal pc_iu_bolt_sl_thold_2 : std_ulogic; +signal ac_an_power_managed_q_int : std_ulogic; +signal pc_iu_bo_enable_3 : std_ulogic; +signal pc_iu_gptr_sl_thold_3 : std_ulogic; +signal pc_iu_time_sl_thold_3 : std_ulogic; +signal pc_iu_repr_sl_thold_3 : std_ulogic; +signal pc_iu_abst_sl_thold_3 : std_ulogic; +signal pc_iu_abst_slp_sl_thold_3 : std_ulogic; +signal pc_iu_bolt_sl_thold_3 : std_ulogic; +signal pc_iu_regf_slp_sl_thold_3 : std_ulogic; +signal pc_iu_func_sl_thold_3 : std_ulogic_vector(0 to 3); +signal pc_iu_func_slp_sl_thold_3 : std_ulogic; +signal pc_iu_cfg_sl_thold_3 : std_ulogic; +signal pc_iu_cfg_slp_sl_thold_3 : std_ulogic; +signal pc_iu_func_slp_nsl_thold_3 : std_ulogic; +signal pc_iu_ary_nsl_thold_3 : std_ulogic; +signal pc_iu_ary_slp_nsl_thold_3 : std_ulogic; +signal pc_iu_sg_3 : std_ulogic_vector(0 to 3); +signal pc_iu_fce_3 : std_ulogic; +signal pc_mm_gptr_sl_thold_3 : std_ulogic; +signal pc_mm_time_sl_thold_3 : std_ulogic; +signal pc_mm_repr_sl_thold_3 : std_ulogic; +signal pc_mm_abst_sl_thold_3 : std_ulogic; +signal pc_mm_abst_slp_sl_thold_3 : std_ulogic; +signal pc_mm_bolt_sl_thold_3 : std_ulogic; +signal pc_mm_func_sl_thold_3 : std_ulogic_vector(0 to 1); +signal pc_mm_func_slp_sl_thold_3 : std_ulogic_vector(0 to 1); +signal pc_mm_cfg_sl_thold_3 : std_ulogic; +signal pc_mm_cfg_slp_sl_thold_3 : std_ulogic; +signal pc_mm_func_nsl_thold_3 : std_ulogic; +signal pc_mm_func_slp_nsl_thold_3 : std_ulogic; +signal pc_mm_ary_nsl_thold_3 : std_ulogic; +signal pc_mm_ary_slp_nsl_thold_3 : std_ulogic; +signal pc_mm_sg_3 : std_ulogic_vector(0 to 1); +signal pc_mm_fce_3 : std_ulogic; +-- IC_BP +signal ic_bp_iu1_val : std_ulogic; +signal ic_bp_iu1_tid : std_ulogic_vector(0 to 3); +signal ic_bp_iu1_ifar : std_ulogic_vector(52 to 59); +signal ic_bp_iu3_val : std_ulogic_vector(0 to 3); +signal ic_bp_iu3_tid : std_ulogic_vector(0 to 3); +signal ic_bp_iu3_ifar : EFF_IFAR; +signal ic_bp_iu3_2ucode : std_ulogic; +signal ic_bp_iu3_2ucode_type : std_ulogic; +signal ic_bp_iu3_error : std_ulogic_vector(0 to 2); +signal ic_bp_iu3_0_instr : std_ulogic_vector(0 to 35); +signal ic_bp_iu3_1_instr : std_ulogic_vector(0 to 35); +signal ic_bp_iu3_2_instr : std_ulogic_vector(0 to 35); +signal ic_bp_iu3_3_instr : std_ulogic_vector(0 to 35); +signal ic_bp_iu3_flush : std_ulogic; +-- BP +signal iu3_0_bh_rd_data : std_ulogic_vector(0 to 1); +signal iu3_1_bh_rd_data : std_ulogic_vector(0 to 1); +signal iu3_2_bh_rd_data : std_ulogic_vector(0 to 1); +signal iu3_3_bh_rd_data : std_ulogic_vector(0 to 1); +signal iu1_bh_rd_addr : std_ulogic_vector(0 to 7); +signal iu1_bh_rd_act : std_ulogic; +signal ex6_bh_wr_data : std_ulogic_vector(0 to 1); +signal ex6_bh_wr_addr : std_ulogic_vector(0 to 7); +signal ex6_bh_wr_act : std_ulogic_vector(0 to 3); +signal int_bp_ib_iu4_ifar : EFF_IFAR; +signal bp_ic_iu5_hold_tid : std_ulogic_vector(0 to 3); +signal bp_ic_iu5_redirect_tid : std_ulogic_vector(0 to 3); +signal bp_ic_iu5_redirect_ifar : EFF_IFAR; +-- UC +signal int_uc_flush_tid : std_ulogic_vector(0 to 3); +signal uc_ic_hold_thread : std_ulogic_vector(0 to 3); +-- SPR +signal spr_ic_icbi_ack_en : std_ulogic; +signal spr_ic_cls : std_ulogic; +signal spr_ic_clockgate_dis : std_ulogic_vector(0 to 1); +signal spr_ic_bp_config : std_ulogic_vector(0 to 3); +signal spr_ic_idir_read : std_ulogic; +signal spr_ic_idir_way : std_ulogic_vector(0 to 1); +signal spr_ic_idir_row : std_ulogic_vector(52 to 57); +signal ic_spr_idir_done : std_ulogic; +signal ic_spr_idir_lru : std_ulogic_vector(0 to 2); +signal ic_spr_idir_parity : std_ulogic_vector(0 to 3); +signal ic_spr_idir_endian : std_ulogic; +signal ic_spr_idir_valid : std_ulogic; +signal ic_spr_idir_tag : std_ulogic_vector(0 to 29); +signal spr_bp_config : std_ulogic_vector(0 to 3); +signal spr_bp_gshare_mask : std_ulogic_vector(0 to 3); +signal spr_ic_pri_rand : std_ulogic_vector(0 to 4); +signal spr_ic_pri_rand_always : std_ulogic; +signal spr_ic_pri_rand_flush : std_ulogic; +signal iuq_mi_scan_in : std_ulogic_vector(0 to 1); +signal iuq_mi_gptr_scan_in : std_ulogic; +signal iuq_mi_gptr_scan_out : std_ulogic; +signal iuq_mi_repr_scan_in : std_ulogic; +signal iuq_mi_repr_scan_out : std_ulogic; +signal iuq_mi_time_scan_in : std_ulogic; +signal iuq_mi_time_scan_out : std_ulogic; +signal iuq_mi_ccfg_scan_in : std_ulogic; +signal iuq_mi_ccfg_scan_out : std_ulogic; +signal iuq_mi_bcfg_scan_in : std_ulogic; +signal iuq_mi_bcfg_scan_out : std_ulogic; +signal iuq_mi_dcfg_scan_in : std_ulogic; +signal iuq_mi_dcfg_scan_out : std_ulogic; +signal iuq_mi_abst_scan_in : std_ulogic; +signal iuq_ic_ccfg_scan_in : std_ulogic; +signal iuq_ic_ccfg_scan_out : std_ulogic; +signal rp_gptr_scan_in : std_ulogic; +signal rp_gptr_scan_out : std_ulogic; +signal iuq_ic_scan_in : std_ulogic_vector(0 to 4); +signal iuq_ic_scan_out : std_ulogic_vector(0 to 4); +signal iuq_ic_repr_scan_in : std_ulogic; +signal iuq_ic_repr_scan_out : std_ulogic; +signal iuq_ic_time_scan_in : std_ulogic; +signal iuq_ic_time_scan_out : std_ulogic; +signal iuq_ic_abst_scan_out : std_ulogic_vector(2 to 2); +signal iuq_bp_scan_in : std_ulogic_vector(0 to 1); +signal int_iuq_bp_scan_out : std_ulogic_vector(0 to 1); +signal iuq_uc_scan_in : std_ulogic; +signal iuq_uc_scan_out : std_ulogic; +--repower +signal iu_func_scan_in : std_ulogic_vector(0 to 8); +signal int_iu_func_scan_in_q : std_ulogic_vector(0 to 8); +signal int_iu_func_scan_out : std_ulogic_vector(0 to 9); +signal iu_func_scan_out_q : std_ulogic_vector(0 to 9); +signal bcfg_scan_in_q : std_ulogic; +signal spare_func_scan_in_q : std_ulogic_vector(0 to 3); +--perf +signal ic_perf_event_t0 : std_ulogic_vector(0 to 6); +signal ic_perf_event_t1 : std_ulogic_vector(0 to 6); +signal ic_perf_event_t2 : std_ulogic_vector(0 to 6); +signal ic_perf_event_t3 : std_ulogic_vector(0 to 6); +signal ic_perf_event : std_ulogic_vector(0 to 1); +--debug groups (misc) +signal bp_dbg_data0 : std_ulogic_vector(0 to 87); +signal bp_dbg_data1 : std_ulogic_vector(0 to 87); +--debug groups (ic) +signal uc_dbg_data : std_ulogic_vector(0 to 87); +signal dbg_debug_data_out : std_ulogic_vector(0 to 87); +signal dbg_trace_triggers_out : std_ulogic_vector(0 to 11); +-- fanout +signal bp_ib_iu3_0_instr : std_ulogic_vector(0 to 31); +signal bp_ib_iu4_0_instr : std_ulogic_vector(32 to 43); +signal bp_ib_iu4_1_instr : std_ulogic_vector(0 to 43); +signal bp_ib_iu4_2_instr : std_ulogic_vector(0 to 43); +signal bp_ib_iu4_3_instr : std_ulogic_vector(0 to 43); +signal uc_ib_iu4_ifar : std_ulogic_vector(62-uc_ifar to 61); +signal uc_ib_iu4_instr : std_ulogic_vector(0 to 36); +signal rm_ib_iu4_force_ram : std_ulogic; +signal rm_ib_iu4_instr : std_ulogic_vector(0 to 35); +signal spr_dec_mask : std_ulogic_vector(0 to 31); +signal spr_dec_match : std_ulogic_vector(0 to 31); +signal spr_fdep_ll_hold : std_ulogic; +-- Special Buffering for PSRO Sensor +signal ac_an_psro_ringsig_i1_b : std_ulogic; +signal ac_an_psro_ringsig_i2 : std_ulogic; +signal ac_an_psro_ringsig_i3_b : std_ulogic; +signal ac_an_psro_ringsig_i4 : std_ulogic; +signal ac_an_psro_ringsig_i5_b : std_ulogic; +-- synopsys translate_off +-- synopsys translate_on +begin +------------------------------------------ +pc_iu_sg_2(0 to 2) <= int_pc_iu_sg_2(1 to 3); +pc_iu_sg_2(3) <= int_pc_iu_sg_2(3); +pc_iu_func_sl_thold_2(0 to 2) <= int_pc_iu_func_sl_thold_2(1 to 3); +pc_iu_func_sl_thold_2(3) <= int_pc_iu_func_sl_thold_2(3); +clkoff_b(0) <= int_clkoff_b(1); +clkoff_b(1) <= int_clkoff_b(1); +clkoff_b(2) <= int_clkoff_b(2); +clkoff_b(3) <= int_clkoff_b(2); +delay_lclkr(5 to 14) <= int_delay_lclkr(5 to 14); +mpw1_b(5 to 14) <= int_mpw1_b(5 to 14); +uc_flush_tid <= int_uc_flush_tid; +iuq_bp_scan_out <= int_iuq_bp_scan_out(0); +ac_an_power_managed_q <= ac_an_power_managed_q_int; +-- fanout +bp_ib_iu4_ifar_t0 <= int_bp_ib_iu4_ifar; +bp_ib_iu3_0_instr_t0 <= bp_ib_iu3_0_instr; +bp_ib_iu4_0_instr_t0 <= bp_ib_iu4_0_instr; +bp_ib_iu4_1_instr_t0 <= bp_ib_iu4_1_instr; +bp_ib_iu4_2_instr_t0 <= bp_ib_iu4_2_instr; +bp_ib_iu4_3_instr_t0 <= bp_ib_iu4_3_instr; +uc_ib_iu4_ifar_t0 <= uc_ib_iu4_ifar; +uc_ib_iu4_instr_t0 <= uc_ib_iu4_instr; +rm_ib_iu4_force_ram_t0 <= rm_ib_iu4_force_ram; +rm_ib_iu4_instr_t0 <= rm_ib_iu4_instr; +spr_dec_mask_t0 <= spr_dec_mask; +spr_dec_match_t0 <= spr_dec_match; +spr_fdep_ll_hold_t0 <= spr_fdep_ll_hold; +bp_ib_iu4_ifar_t1 <= int_bp_ib_iu4_ifar; +bp_ib_iu3_0_instr_t1 <= bp_ib_iu3_0_instr; +bp_ib_iu4_0_instr_t1 <= bp_ib_iu4_0_instr; +bp_ib_iu4_1_instr_t1 <= bp_ib_iu4_1_instr; +bp_ib_iu4_2_instr_t1 <= bp_ib_iu4_2_instr; +bp_ib_iu4_3_instr_t1 <= bp_ib_iu4_3_instr; +uc_ib_iu4_ifar_t1 <= uc_ib_iu4_ifar; +uc_ib_iu4_instr_t1 <= uc_ib_iu4_instr; +rm_ib_iu4_force_ram_t1 <= rm_ib_iu4_force_ram; +rm_ib_iu4_instr_t1 <= rm_ib_iu4_instr; +spr_dec_mask_t1 <= spr_dec_mask; +spr_dec_match_t1 <= spr_dec_match; +spr_fdep_ll_hold_t1 <= spr_fdep_ll_hold; +bp_ib_iu4_ifar_t2 <= int_bp_ib_iu4_ifar; +bp_ib_iu3_0_instr_t2 <= bp_ib_iu3_0_instr; +bp_ib_iu4_0_instr_t2 <= bp_ib_iu4_0_instr; +bp_ib_iu4_1_instr_t2 <= bp_ib_iu4_1_instr; +bp_ib_iu4_2_instr_t2 <= bp_ib_iu4_2_instr; +bp_ib_iu4_3_instr_t2 <= bp_ib_iu4_3_instr; +uc_ib_iu4_ifar_t2 <= uc_ib_iu4_ifar; +uc_ib_iu4_instr_t2 <= uc_ib_iu4_instr; +rm_ib_iu4_force_ram_t2 <= rm_ib_iu4_force_ram; +rm_ib_iu4_instr_t2 <= rm_ib_iu4_instr; +spr_dec_mask_t2 <= spr_dec_mask; +spr_dec_match_t2 <= spr_dec_match; +spr_fdep_ll_hold_t2 <= spr_fdep_ll_hold; +bp_ib_iu4_ifar_t3 <= int_bp_ib_iu4_ifar; +bp_ib_iu3_0_instr_t3 <= bp_ib_iu3_0_instr; +bp_ib_iu4_0_instr_t3 <= bp_ib_iu4_0_instr; +bp_ib_iu4_1_instr_t3 <= bp_ib_iu4_1_instr; +bp_ib_iu4_2_instr_t3 <= bp_ib_iu4_2_instr; +bp_ib_iu4_3_instr_t3 <= bp_ib_iu4_3_instr; +uc_ib_iu4_ifar_t3 <= uc_ib_iu4_ifar; +uc_ib_iu4_instr_t3 <= uc_ib_iu4_instr; +rm_ib_iu4_force_ram_t3 <= rm_ib_iu4_force_ram; +rm_ib_iu4_instr_t3 <= rm_ib_iu4_instr; +spr_dec_mask_t3 <= spr_dec_mask; +spr_dec_match_t3 <= spr_dec_match; +spr_fdep_ll_hold_t3 <= spr_fdep_ll_hold; +iuq_misc0 : entity work.iuq_misc +generic map(regmode => regmode, + a2mode => a2mode, + expand_type => expand_type) +port map ( + vdd => vdd, + gnd => gnd, + vcs => vcs, + nclk => nclk, + pc_iu_sg_3 => pc_iu_sg_3, + pc_iu_func_sl_thold_3 => pc_iu_func_sl_thold_3, + pc_iu_func_slp_sl_thold_3 => pc_iu_func_slp_sl_thold_3, + pc_iu_gptr_sl_thold_3 => pc_iu_gptr_sl_thold_3, + pc_iu_time_sl_thold_3 => pc_iu_time_sl_thold_3, + pc_iu_repr_sl_thold_3 => pc_iu_repr_sl_thold_3, + pc_iu_abst_sl_thold_3 => pc_iu_abst_sl_thold_3, + pc_iu_abst_slp_sl_thold_3 => pc_iu_abst_slp_sl_thold_3, + pc_iu_cfg_sl_thold_3 => pc_iu_cfg_sl_thold_3, + pc_iu_cfg_slp_sl_thold_3 => pc_iu_cfg_slp_sl_thold_3, + pc_iu_regf_slp_sl_thold_3 => pc_iu_regf_slp_sl_thold_3, + pc_iu_ary_nsl_thold_3 => pc_iu_ary_nsl_thold_3, + pc_iu_ary_slp_nsl_thold_3 => pc_iu_ary_slp_nsl_thold_3, + pc_iu_func_slp_nsl_thold_3 => pc_iu_func_slp_nsl_thold_3, + pc_iu_bolt_sl_thold_3 => pc_iu_bolt_sl_thold_3, + pc_iu_fce_3 => pc_iu_fce_3, + tc_ac_ccflush_dc => tc_ac_ccflush_dc, + scan_diag_dc => an_ac_scan_diag_dc, + pc_iu_sg_2 => int_pc_iu_sg_2, + pc_iu_func_sl_thold_2 => int_pc_iu_func_sl_thold_2, + pc_iu_func_slp_sl_thold_2 => pc_iu_func_slp_sl_thold_2, + pc_iu_time_sl_thold_2 => pc_iu_time_sl_thold_2, + pc_iu_repr_sl_thold_2 => pc_iu_repr_sl_thold_2, + pc_iu_abst_sl_thold_2 => pc_iu_abst_sl_thold_2, + pc_iu_abst_slp_sl_thold_2 => pc_iu_abst_slp_sl_thold_2, + pc_iu_cfg_slp_sl_thold_2 => pc_iu_cfg_slp_sl_thold_2, + pc_iu_regf_slp_sl_thold_2 => pc_iu_regf_slp_sl_thold_2, + pc_iu_ary_nsl_thold_2 => pc_iu_ary_nsl_thold_2, + pc_iu_ary_slp_nsl_thold_2 => pc_iu_ary_slp_nsl_thold_2, + pc_iu_func_slp_nsl_thold_2 => pc_iu_func_slp_nsl_thold_2, + pc_iu_bolt_sl_thold_2 => pc_iu_bolt_sl_thold_2, + pc_iu_fce_2 => pc_iu_fce_2, + clkoff_b => int_clkoff_b, + +delay_lclkr => int_delay_lclkr, + mpw1_b => int_mpw1_b, + +g8t_clkoff_b => g8t_clkoff_b, + g8t_d_mode => g8t_d_mode, + g8t_delay_lclkr => g8t_delay_lclkr, + g8t_mpw1_b => g8t_mpw1_b, + g8t_mpw2_b => g8t_mpw2_b, + g6t_clkoff_b => g6t_clkoff_b, + +g6t_d_mode => g6t_d_mode, + g6t_delay_lclkr => g6t_delay_lclkr, + g6t_mpw1_b => g6t_mpw1_b, + g6t_mpw2_b => g6t_mpw2_b, + cam_clkoff_b => cam_clkoff_b, + +cam_d_mode => cam_d_mode, + cam_delay_lclkr => cam_delay_lclkr, + cam_mpw1_b => cam_mpw1_b, + cam_mpw2_b => cam_mpw2_b, + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b, + func_scan_in => iuq_mi_scan_in, + gptr_scan_in => iuq_mi_gptr_scan_in, + time_scan_in => iuq_mi_time_scan_in, + abst_scan_in => iuq_mi_abst_scan_in, + repr_scan_in => iuq_mi_repr_scan_in, + ccfg_scan_in => iuq_mi_ccfg_scan_in, + bcfg_scan_in => iuq_mi_bcfg_scan_in, + dcfg_scan_in => iuq_mi_dcfg_scan_in, + func_scan_out => iuq_mi_scan_out, + gptr_scan_out => iuq_mi_gptr_scan_out, + time_scan_out => iuq_mi_time_scan_out, + abst_scan_out => abst_scan_out(2), + repr_scan_out => iuq_mi_repr_scan_out, + ccfg_scan_out => iuq_mi_ccfg_scan_out, + bcfg_scan_out => iuq_mi_bcfg_scan_out, + dcfg_scan_out => iuq_mi_dcfg_scan_out, + pc_iu_abist_di_0 => pc_iu_abist_di_0, + pc_iu_abist_g8t_bw_1 => pc_iu_abist_g8t_bw_1, + pc_iu_abist_g8t_bw_0 => pc_iu_abist_g8t_bw_0, + pc_iu_abist_waddr_0 => pc_iu_abist_waddr_0(3 to 9), + pc_iu_abist_g8t_wenb => pc_iu_abist_g8t_wenb, + pc_iu_abist_raddr_0 => pc_iu_abist_raddr_0(3 to 9), + pc_iu_abist_g8t1p_renb_0 => pc_iu_abist_g8t1p_renb_0, + an_ac_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc, + pc_iu_abist_ena_dc => pc_iu_abist_ena_dc, + pc_iu_abist_wl128_comp_ena => pc_iu_abist_wl128_comp_ena, + pc_iu_abist_raw_dc_b => pc_iu_abist_raw_dc_b, + pc_iu_abist_g8t_dcomp => pc_iu_abist_g8t_dcomp, + pc_iu_bo_enable_3 => pc_iu_bo_enable_3, + pc_iu_bo_reset => pc_iu_bo_reset, + pc_iu_bo_unload => pc_iu_bo_unload, + pc_iu_bo_repair => pc_iu_bo_repair, + pc_iu_bo_shdata => pc_iu_bo_shdata, + pc_iu_bo_select => pc_iu_bo_select(4), + iu_pc_bo_fail => iu_pc_bo_fail(4), + iu_pc_bo_diagout => iu_pc_bo_diagout(4), + r_act => iu1_bh_rd_act, + w_act => ex6_bh_wr_act, + r_addr => iu1_bh_rd_addr, + w_addr => ex6_bh_wr_addr, + data_in => ex6_bh_wr_data, + data_out0 => iu3_0_bh_rd_data, + data_out1 => iu3_1_bh_rd_data, + data_out2 => iu3_2_bh_rd_data, + data_out3 => iu3_3_bh_rd_data, + pc_iu_ram_instr => pc_iu_ram_instr, + pc_iu_ram_instr_ext => pc_iu_ram_instr_ext, + pc_iu_ram_force_cmplt => pc_iu_ram_force_cmplt, + xu_iu_ram_issue => xu_iu_ram_issue, + rm_ib_iu4_val => rm_ib_iu4_val, + rm_ib_iu4_force_ram => rm_ib_iu4_force_ram, + rm_ib_iu4_instr => rm_ib_iu4_instr, + slowspr_val_in => slowspr_val_in, + slowspr_rw_in => slowspr_rw_in, + slowspr_etid_in => slowspr_etid_in, + slowspr_addr_in => slowspr_addr_in, + slowspr_data_in => slowspr_data_in, + slowspr_done_in => slowspr_done_in, + slowspr_val_out => slowspr_val_out, + slowspr_rw_out => slowspr_rw_out, + slowspr_etid_out => slowspr_etid_out, + slowspr_addr_out => slowspr_addr_out, + slowspr_data_out => slowspr_data_out, + slowspr_done_out => slowspr_done_out, + spr_ic_idir_read => spr_ic_idir_read, + spr_ic_idir_way => spr_ic_idir_way, + spr_ic_idir_row => spr_ic_idir_row, + ic_spr_idir_done => ic_spr_idir_done, + ic_spr_idir_lru => ic_spr_idir_lru, + ic_spr_idir_parity => ic_spr_idir_parity, + ic_spr_idir_endian => ic_spr_idir_endian, + ic_spr_idir_valid => ic_spr_idir_valid, + ic_spr_idir_tag => ic_spr_idir_tag, + spr_ic_cls => spr_ic_cls, + spr_ic_clockgate_dis => spr_ic_clockgate_dis, + spr_ic_icbi_ack_en => spr_ic_icbi_ack_en, + spr_ic_bp_config => spr_ic_bp_config, + spr_bp_config => spr_bp_config, + spr_bp_gshare_mask => spr_bp_gshare_mask, + spr_issue_high_mask => spr_issue_high_mask, + spr_issue_med_mask => spr_issue_med_mask, + spr_fiss_count0_max => spr_fiss_count0_max, + spr_fiss_count1_max => spr_fiss_count1_max, + spr_fiss_count2_max => spr_fiss_count2_max, + spr_fiss_count3_max => spr_fiss_count3_max, + spr_ic_pri_rand => spr_ic_pri_rand, + spr_ic_pri_rand_always => spr_ic_pri_rand_always, + spr_ic_pri_rand_flush => spr_ic_pri_rand_flush, + spr_fiss_pri_rand => spr_fiss_pri_rand, + spr_fiss_pri_rand_always => spr_fiss_pri_rand_always, + spr_fiss_pri_rand_flush => spr_fiss_pri_rand_flush, + spr_dec_mask => spr_dec_mask, + spr_dec_match => spr_dec_match, + spr_fdep_ll_hold => spr_fdep_ll_hold, + xu_iu_run_thread => xu_iu_run_thread, + iu_au_config_iucr_t0 => iu_au_config_iucr_t0, + iu_au_config_iucr_t1 => iu_au_config_iucr_t1, + iu_au_config_iucr_t2 => iu_au_config_iucr_t2, + iu_au_config_iucr_t3 => iu_au_config_iucr_t3, + xu_iu_ex6_pri => xu_iu_ex6_pri, + xu_iu_ex6_pri_val => xu_iu_ex6_pri_val, + xu_iu_raise_iss_pri => xu_iu_raise_iss_pri, + xu_iu_msr_gs => xu_iu_msr_gs, + xu_iu_msr_pr => xu_iu_msr_pr, + pc_iu_trace_bus_enable => pc_iu_trace_bus_enable, + pc_iu_debug_mux_ctrls => pc_iu_debug_mux1_ctrls, + debug_data_in => debug_data_in, + trace_triggers_in => trace_triggers_in, + debug_data_out => dbg_debug_data_out, + trace_triggers_out => dbg_trace_triggers_out, + fiss_dbg_data => fiss_dbg_data, + fdep_dbg_data => fdep_dbg_data, + ib_dbg_data => ib_dbg_data, + bp_dbg_data0 => bp_dbg_data0, + bp_dbg_data1 => bp_dbg_data1, + fu_iss_dbg_data => fu_iss_dbg_data, + axu_dbg_data_t0 => axu_dbg_data_t0, + axu_dbg_data_t1 => axu_dbg_data_t1, + axu_dbg_data_t2 => axu_dbg_data_t2, + axu_dbg_data_t3 => axu_dbg_data_t3, + ic_perf_event_t0 => ic_perf_event_t0, + ic_perf_event_t1 => ic_perf_event_t1, + ic_perf_event_t2 => ic_perf_event_t2, + ic_perf_event_t3 => ic_perf_event_t3, + ic_perf_event => ic_perf_event, + ib_perf_event_t0 => ib_perf_event_t0, + ib_perf_event_t1 => ib_perf_event_t1, + ib_perf_event_t2 => ib_perf_event_t2, + ib_perf_event_t3 => ib_perf_event_t3, + fdep_perf_event_t0 => fdep_perf_event_t0, + fdep_perf_event_t1 => fdep_perf_event_t1, + fdep_perf_event_t2 => fdep_perf_event_t2, + fdep_perf_event_t3 => fdep_perf_event_t3, + fiss_perf_event_t0 => fiss_perf_event_t0, + fiss_perf_event_t1 => fiss_perf_event_t1, + fiss_perf_event_t2 => fiss_perf_event_t2, + fiss_perf_event_t3 => fiss_perf_event_t3, + pc_iu_event_mux_ctrls => pc_iu_event_mux_ctrls, + pc_iu_event_count_mode => pc_iu_event_count_mode, + pc_iu_event_bus_enable => pc_iu_event_bus_enable, + iu_pc_event_data => iu_pc_event_data + +); +iuq_ic0 : entity work.iuq_ic +generic map(regmode => regmode, + bcfg_epn_0to15 => bcfg_epn_0to15, + bcfg_epn_16to31 => bcfg_epn_16to31, + bcfg_epn_32to47 => bcfg_epn_32to47, + bcfg_epn_48to51 => bcfg_epn_48to51, + bcfg_rpn_22to31 => bcfg_rpn_22to31, + bcfg_rpn_32to47 => bcfg_rpn_32to47, + bcfg_rpn_48to51 => bcfg_rpn_48to51, + expand_type => expand_type) +port map( + vcs => vcs, + vdd => vdd, + gnd => gnd, + nclk => nclk, + tc_ac_ccflush_dc => tc_ac_ccflush_dc, + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b, + an_ac_scan_diag_dc => an_ac_scan_diag_dc, + pc_iu_func_sl_thold_2 => int_pc_iu_func_sl_thold_2(0), + pc_iu_func_slp_sl_thold_2 => pc_iu_func_slp_sl_thold_2, + pc_iu_time_sl_thold_2 => pc_iu_time_sl_thold_2, + pc_iu_repr_sl_thold_2 => pc_iu_repr_sl_thold_2, + pc_iu_abst_sl_thold_2 => pc_iu_abst_sl_thold_2, + pc_iu_abst_slp_sl_thold_2 => pc_iu_abst_slp_sl_thold_2, + pc_iu_cfg_slp_sl_thold_2 => pc_iu_cfg_slp_sl_thold_2, + pc_iu_regf_slp_sl_thold_2 => pc_iu_regf_slp_sl_thold_2, + pc_iu_ary_nsl_thold_2 => pc_iu_ary_nsl_thold_2, + pc_iu_ary_slp_nsl_thold_2 => pc_iu_ary_slp_nsl_thold_2, + pc_iu_func_slp_nsl_thold_2 => pc_iu_func_slp_nsl_thold_2, + pc_iu_bolt_sl_thold_2 => pc_iu_bolt_sl_thold_2, + pc_iu_sg_2 => int_pc_iu_sg_2(0), + pc_iu_fce_2 => pc_iu_fce_2, + clkoff_b => int_clkoff_b(0), + delay_lclkr(0) => int_delay_lclkr(1), + delay_lclkr(1) => int_delay_lclkr(4), + mpw1_b(0) => int_mpw1_b(1), + mpw1_b(1) => int_mpw1_b(4), + g8t_clkoff_b => g8t_clkoff_b, + g8t_d_mode => g8t_d_mode, + g8t_delay_lclkr => g8t_delay_lclkr, + g8t_mpw1_b => g8t_mpw1_b, + g8t_mpw2_b => g8t_mpw2_b, + g6t_clkoff_b => g6t_clkoff_b, + g6t_d_mode => g6t_d_mode, + g6t_delay_lclkr => g6t_delay_lclkr, + g6t_mpw1_b => g6t_mpw1_b, + g6t_mpw2_b => g6t_mpw2_b, + cam_clkoff_b => cam_clkoff_b, + cam_d_mode => cam_d_mode, + cam_delay_lclkr => cam_delay_lclkr, + cam_mpw1_b => cam_mpw1_b, + cam_mpw2_b => cam_mpw2_b, + func_scan_in => iuq_ic_scan_in, + func_scan_out => iuq_ic_scan_out, + ac_ccfg_scan_in => iuq_ic_ccfg_scan_in, + ac_ccfg_scan_out => iuq_ic_ccfg_scan_out, + time_scan_in => iuq_ic_time_scan_in, + time_scan_out => iuq_ic_time_scan_out, + repr_scan_in => iuq_ic_repr_scan_in, + repr_scan_out => iuq_ic_repr_scan_out, + abst_scan_in => abst_scan_in(0 to 2), + abst_scan_out(0 to 1) => abst_scan_out(0 to 1), + abst_scan_out(2) => iuq_ic_abst_scan_out(2), + regf_scan_in => regf_scan_in, + regf_scan_out => regf_scan_out, + uc_dbg_data => uc_dbg_data, + pc_iu_trace_bus_enable => pc_iu_trace_bus_enable, + pc_iu_debug_mux_ctrls => pc_iu_debug_mux2_ctrls, + debug_data_in => dbg_debug_data_out, + trace_triggers_in => dbg_trace_triggers_out, + debug_data_out => debug_data_out, + trace_triggers_out => trace_triggers_out, + pc_iu_event_bus_enable => pc_iu_event_bus_enable, + ic_perf_event_t0 => ic_perf_event_t0, + ic_perf_event_t1 => ic_perf_event_t1, + ic_perf_event_t2 => ic_perf_event_t2, + ic_perf_event_t3 => ic_perf_event_t3, + ic_perf_event => ic_perf_event, + iu_pc_err_icache_parity => iu_pc_err_icache_parity, + iu_pc_err_icachedir_parity => iu_pc_err_icachedir_parity, + iu_pc_err_icachedir_multihit => iu_pc_err_icachedir_multihit, + pc_iu_inj_icache_parity => pc_iu_inj_icache_parity, + pc_iu_inj_icachedir_parity => pc_iu_inj_icachedir_parity, + pc_iu_inj_icachedir_multihit => pc_iu_inj_icachedir_multihit, + pc_iu_abist_g8t_wenb => pc_iu_abist_g8t_wenb, + pc_iu_abist_g8t1p_renb_0 => pc_iu_abist_g8t1p_renb_0, + pc_iu_abist_di_0 => pc_iu_abist_di_0, + pc_iu_abist_g8t_bw_1 => pc_iu_abist_g8t_bw_1, + pc_iu_abist_g8t_bw_0 => pc_iu_abist_g8t_bw_0, + pc_iu_abist_waddr_0 => pc_iu_abist_waddr_0(4 to 9), + pc_iu_abist_raddr_0 => pc_iu_abist_raddr_0(2 to 9), + pc_iu_abist_ena_dc => pc_iu_abist_ena_dc, + pc_iu_abist_wl64_comp_ena => pc_iu_abist_wl64_comp_ena, + pc_iu_abist_raw_dc_b => pc_iu_abist_raw_dc_b, + pc_iu_abist_g8t_dcomp => pc_iu_abist_g8t_dcomp, + pc_iu_abist_g6t_bw => pc_iu_abist_g6t_bw, + pc_iu_abist_di_g6t_2r => pc_iu_abist_di_g6t_2r, + pc_iu_abist_wl256_comp_ena => pc_iu_abist_wl256_comp_ena, + pc_iu_abist_dcomp_g6t_2r => pc_iu_abist_dcomp_g6t_2r, + pc_iu_abist_g6t_r_wb => pc_iu_abist_g6t_r_wb, + an_ac_lbist_ary_wrt_thru_dc=> an_ac_lbist_ary_wrt_thru_dc, + an_ac_lbist_en_dc => an_ac_lbist_en_dc, + an_ac_atpg_en_dc => an_ac_atpg_en_dc, + an_ac_grffence_en_dc => an_ac_grffence_en_dc, + pc_iu_bo_enable_3 => pc_iu_bo_enable_3, + pc_iu_bo_reset => pc_iu_bo_reset, + pc_iu_bo_unload => pc_iu_bo_unload, + pc_iu_bo_repair => pc_iu_bo_repair, + pc_iu_bo_shdata => pc_iu_bo_shdata, + pc_iu_bo_select => pc_iu_bo_select(0 to 3), + iu_pc_bo_fail => iu_pc_bo_fail(0 to 3), + iu_pc_bo_diagout => iu_pc_bo_diagout(0 to 3), + pc_iu_init_reset => pc_iu_init_reset, + xu_iu_rf1_val => xu_iu_rf1_val, + xu_iu_rf1_is_eratre => xu_iu_rf1_is_eratre, + xu_iu_rf1_is_eratwe => xu_iu_rf1_is_eratwe, + xu_iu_rf1_is_eratsx => xu_iu_rf1_is_eratsx, + xu_iu_rf1_is_eratilx => xu_iu_rf1_is_eratilx, + xu_iu_ex1_is_isync => xu_iu_ex1_is_isync, + xu_iu_ex1_is_csync => xu_iu_ex1_is_csync, + xu_iu_rf1_ws => xu_iu_rf1_ws, + xu_iu_rf1_t => xu_iu_rf1_t, + xu_iu_ex1_rs_is => xu_iu_ex1_rs_is, + xu_iu_ex1_ra_entry => xu_iu_ex1_ra_entry(8 to 11), + xu_iu_ex1_rb => xu_iu_ex1_rb, + xu_rf1_flush => xu_rf1_flush, + xu_ex1_flush => xu_ex1_flush, + xu_ex2_flush => xu_ex2_flush, + xu_ex3_flush => xu_ex3_flush, + xu_ex4_flush => xu_ex4_flush, + xu_ex5_flush => xu_ex5_flush, + xu_iu_ex4_rs_data => xu_iu_ex4_rs_data, + xu_iu_msr_hv => xu_iu_msr_hv, + xu_iu_msr_is => xu_iu_msr_is, + xu_iu_msr_pr => xu_iu_msr_pr, + xu_iu_hid_mmu_mode => xu_iu_hid_mmu_mode, + xu_iu_spr_ccr2_ifratsc => xu_iu_spr_ccr2_ifratsc, + xu_iu_spr_ccr2_ifrat => xu_iu_spr_ccr2_ifrat, + xu_iu_xucr4_mmu_mchk => xu_iu_xucr4_mmu_mchk, + iu_xu_ex4_data => iu_xu_ex4_tlb_data, + iu_xu_ierat_ex3_par_err => iu_xu_ierat_ex3_par_err, + iu_xu_ierat_ex4_par_err => iu_xu_ierat_ex4_par_err, + iu_xu_ierat_ex2_flush_req => iu_xu_ierat_ex2_flush_req, + iu_mm_ierat_req => iu_mm_ierat_req, + iu_mm_ierat_epn => iu_mm_ierat_epn, + iu_mm_ierat_thdid => iu_mm_ierat_thdid, + iu_mm_ierat_state => iu_mm_ierat_state, + iu_mm_ierat_tid => iu_mm_ierat_tid, + iu_mm_ierat_flush => iu_mm_ierat_flush, + mm_iu_ierat_rel_val => mm_iu_ierat_rel_val, + mm_iu_ierat_rel_data => mm_iu_ierat_rel_data, + mm_iu_ierat_pid0 => mm_iu_ierat_pid0, + mm_iu_ierat_pid1 => mm_iu_ierat_pid1, + mm_iu_ierat_pid2 => mm_iu_ierat_pid2, + mm_iu_ierat_pid3 => mm_iu_ierat_pid3, + mm_iu_ierat_mmucr0_0 => mm_iu_ierat_mmucr0_0, + mm_iu_ierat_mmucr0_1 => mm_iu_ierat_mmucr0_1, + mm_iu_ierat_mmucr0_2 => mm_iu_ierat_mmucr0_2, + mm_iu_ierat_mmucr0_3 => mm_iu_ierat_mmucr0_3, + iu_mm_ierat_mmucr0 => iu_mm_ierat_mmucr0, + iu_mm_ierat_mmucr0_we => iu_mm_ierat_mmucr0_we, + mm_iu_ierat_mmucr1 => mm_iu_ierat_mmucr1, + iu_mm_ierat_mmucr1 => iu_mm_ierat_mmucr1, + iu_mm_ierat_mmucr1_we => iu_mm_ierat_mmucr1_we, + mm_iu_ierat_snoop_coming => mm_iu_ierat_snoop_coming, + mm_iu_ierat_snoop_val => mm_iu_ierat_snoop_val, + mm_iu_ierat_snoop_attr => mm_iu_ierat_snoop_attr, + mm_iu_ierat_snoop_vpn => mm_iu_ierat_snoop_vpn, + iu_mm_ierat_snoop_ack => iu_mm_ierat_snoop_ack, + iu_mm_lmq_empty => iu_mm_lmq_empty, + ac_an_power_managed => ac_an_power_managed_q_int, + xu_iu_run_thread => xu_iu_run_thread, + xu_iu_flush => xu_iu_flush, + xu_iu_iu0_flush_ifar0 => xu_iu_iu0_flush_ifar0, + xu_iu_iu0_flush_ifar1 => xu_iu_iu0_flush_ifar1, + xu_iu_iu0_flush_ifar2 => xu_iu_iu0_flush_ifar2, + xu_iu_iu0_flush_ifar3 => xu_iu_iu0_flush_ifar3, + xu_iu_flush_2ucode => xu_iu_flush_2ucode, + xu_iu_flush_2ucode_type => xu_iu_flush_2ucode_type, + xu_iu_msr_cm => xu_iu_msr_cm, + xu_iu_ex6_icbi_val => xu_iu_ex6_icbi_val, + xu_iu_ex6_icbi_addr => xu_iu_ex6_icbi_addr, + xu_iu_ici => xu_iu_ici, + spr_ic_cls => spr_ic_cls, + spr_ic_clockgate_dis => spr_ic_clockgate_dis, + spr_ic_icbi_ack_en => spr_ic_icbi_ack_en, + spr_ic_bp_config => spr_ic_bp_config, + spr_ic_idir_read => spr_ic_idir_read, + spr_ic_idir_way => spr_ic_idir_way, + spr_ic_idir_row => spr_ic_idir_row, + spr_ic_pri_rand => spr_ic_pri_rand, + spr_ic_pri_rand_always => spr_ic_pri_rand_always, + spr_ic_pri_rand_flush => spr_ic_pri_rand_flush, + ic_spr_idir_done => ic_spr_idir_done, + ic_spr_idir_lru => ic_spr_idir_lru, + ic_spr_idir_parity => ic_spr_idir_parity, + ic_spr_idir_endian => ic_spr_idir_endian, + ic_spr_idir_valid => ic_spr_idir_valid, + ic_spr_idir_tag => ic_spr_idir_tag, + iu_xu_request => iu_xu_request, + iu_xu_thread => iu_xu_thread, + iu_xu_ra => iu_xu_ra, + iu_xu_wimge => iu_xu_wimge, + iu_xu_userdef => iu_xu_userdef, + an_ac_reld_data_vld => an_ac_reld_data_vld, + an_ac_reld_core_tag => an_ac_reld_core_tag, + an_ac_reld_qw => an_ac_reld_qw, + an_ac_reld_data => an_ac_reld_data, + an_ac_reld_ecc_err => an_ac_reld_ecc_err, + an_ac_reld_ecc_err_ue => an_ac_reld_ecc_err_ue, + an_ac_back_inv => an_ac_back_inv, + an_ac_back_inv_addr => an_ac_back_inv_addr(REAL_IFAR'left to 57), + an_ac_back_inv_target => an_ac_back_inv_target_iiu_a(0), + an_ac_icbi_ack => an_ac_icbi_ack, + an_ac_icbi_ack_thread => an_ac_icbi_ack_thread, + bp_ib_iu4_ifar => int_bp_ib_iu4_ifar, + bp_ic_iu5_hold_tid => bp_ic_iu5_hold_tid, + bp_ic_iu5_redirect_tid => bp_ic_iu5_redirect_tid, + bp_ic_iu5_redirect_ifar => bp_ic_iu5_redirect_ifar, + ic_bp_iu1_val => ic_bp_iu1_val, + ic_bp_iu1_tid => ic_bp_iu1_tid, + ic_bp_iu1_ifar => ic_bp_iu1_ifar, + ic_bp_iu3_val => ic_bp_iu3_val, + ic_bp_iu3_tid => ic_bp_iu3_tid, + ic_bp_iu3_ifar => ic_bp_iu3_ifar, + ic_bp_iu3_2ucode => ic_bp_iu3_2ucode, + ic_bp_iu3_2ucode_type => ic_bp_iu3_2ucode_type, + ic_bp_iu3_error => ic_bp_iu3_error, + ic_bp_iu3_flush => ic_bp_iu3_flush, + ic_bp_iu3_0_instr => ic_bp_iu3_0_instr, + ic_bp_iu3_1_instr => ic_bp_iu3_1_instr, + ic_bp_iu3_2_instr => ic_bp_iu3_2_instr, + ic_bp_iu3_3_instr => ic_bp_iu3_3_instr, + ib_ic_empty => ib_ic_empty, + ib_ic_below_water => ib_ic_below_water, + ib_ic_iu5_redirect_tid => ib_ic_iu5_redirect_tid, + ic_fdep_load_quiesce => ic_fdep_load_quiesce, + ic_fdep_icbi_ack => ic_fdep_icbi_ack, + uc_flush_tid => int_uc_flush_tid, + uc_ic_hold_thread => uc_ic_hold_thread +); +iuq_bp0 : entity work.iuq_bp +generic map(expand_type => expand_type) +port map( + bp_dbg_data0 => bp_dbg_data0, + bp_dbg_data1 => bp_dbg_data1, + iu3_0_bh_rd_data => iu3_0_bh_rd_data, + iu3_1_bh_rd_data => iu3_1_bh_rd_data, + iu3_2_bh_rd_data => iu3_2_bh_rd_data, + iu3_3_bh_rd_data => iu3_3_bh_rd_data, + iu1_bh_rd_addr => iu1_bh_rd_addr, + iu1_bh_rd_act => iu1_bh_rd_act, + ex6_bh_wr_data => ex6_bh_wr_data, + ex6_bh_wr_addr => ex6_bh_wr_addr, + ex6_bh_wr_act => ex6_bh_wr_act, + ic_bp_iu1_val => ic_bp_iu1_val, + ic_bp_iu1_tid => ic_bp_iu1_tid, + ic_bp_iu1_ifar => ic_bp_iu1_ifar, + ic_bp_iu3_val => ic_bp_iu3_val, + ic_bp_iu3_tid => ic_bp_iu3_tid, + ic_bp_iu3_ifar => ic_bp_iu3_ifar, + ic_bp_iu3_error => ic_bp_iu3_error, + ic_bp_iu3_2ucode => ic_bp_iu3_2ucode, + ic_bp_iu3_2ucode_type => ic_bp_iu3_2ucode_type, + ic_bp_iu3_flush => ic_bp_iu3_flush, + ic_bp_iu3_0_instr => ic_bp_iu3_0_instr, + ic_bp_iu3_1_instr => ic_bp_iu3_1_instr, + ic_bp_iu3_2_instr => ic_bp_iu3_2_instr, + ic_bp_iu3_3_instr => ic_bp_iu3_3_instr, + bp_ib_iu4_t0_val => bp_ib_iu4_t0_val, + bp_ib_iu4_t1_val => bp_ib_iu4_t1_val, + bp_ib_iu4_t2_val => bp_ib_iu4_t2_val, + bp_ib_iu4_t3_val => bp_ib_iu4_t3_val, + bp_ib_iu4_ifar => int_bp_ib_iu4_ifar, + bp_ib_iu3_0_instr => bp_ib_iu3_0_instr, + bp_ib_iu4_0_instr => bp_ib_iu4_0_instr, + bp_ib_iu4_1_instr => bp_ib_iu4_1_instr, + bp_ib_iu4_2_instr => bp_ib_iu4_2_instr, + bp_ib_iu4_3_instr => bp_ib_iu4_3_instr, + bp_ic_iu5_hold_tid => bp_ic_iu5_hold_tid, + bp_ic_iu5_redirect_tid => bp_ic_iu5_redirect_tid, + bp_ic_iu5_redirect_ifar => bp_ic_iu5_redirect_ifar, + xu_iu_ex5_ifar => xu_iu_ex5_ifar, + xu_iu_ex5_tid => xu_iu_ex5_tid, + xu_iu_ex5_val => xu_iu_ex5_val, + xu_iu_ex5_br_update => xu_iu_ex5_br_update, + xu_iu_ex5_br_hist => xu_iu_ex5_br_hist, + xu_iu_ex5_br_taken => xu_iu_ex5_br_taken, + xu_iu_ex5_bclr => xu_iu_ex5_bclr, + xu_iu_ex5_getNIA => xu_iu_ex5_getNIA, + xu_iu_ex5_lk => xu_iu_ex5_lk, + xu_iu_ex5_bh => xu_iu_ex5_bh, + xu_iu_ex5_gshare => xu_iu_ex5_gshare, + xu_iu_iu3_flush_tid => xu_iu_flush, + xu_iu_iu4_flush_tid => xu_iu_flush, + xu_iu_iu5_flush_tid => xu_iu_flush, + xu_iu_ex5_flush_tid => xu_ex5_flush, + ib_ic_iu5_redirect_tid => ib_ic_iu5_redirect_tid, + uc_flush_tid => int_uc_flush_tid, + spr_bp_config => spr_bp_config, + spr_bp_gshare_mask => spr_bp_gshare_mask, + vdd => vdd, + gnd => gnd, + nclk => nclk, + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b, + pc_iu_sg_2 => int_pc_iu_sg_2(0), + pc_iu_func_sl_thold_2 => int_pc_iu_func_sl_thold_2(0), + clkoff_b => int_clkoff_b(0), + +tc_ac_ccflush_dc => tc_ac_ccflush_dc, + +delay_lclkr => int_delay_lclkr(2), + mpw1_b => int_mpw1_b(2), + +scan_in => iuq_bp_scan_in(0 to 1), + scan_out => int_iuq_bp_scan_out(0 to 1) +); +u0: if ucode_mode = 0 generate +begin + iuq_uc_scan_out <= iuq_uc_scan_in; +int_uc_flush_tid <= (others => '0'); +uc_ib_iu4_val <= (others => '0'); +uc_ib_iu4_ifar <= (others => '0'); +uc_ib_iu4_instr <= (others => '0'); +uc_ic_hold_thread <= (others => '0'); +iu_pc_err_ucode_illegal <= (others => '0'); +end generate u0; +u1: if ucode_mode = 1 generate +begin +iuq_uc0 : entity work.iuq_uc +generic map(uc_ifar => uc_ifar, + regmode => regmode, + expand_type => expand_type) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_iu_func_sl_thold_2 => int_pc_iu_func_sl_thold_2(0), + pc_iu_sg_2 => int_pc_iu_sg_2(0), + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b, + tc_ac_ccflush_dc => tc_ac_ccflush_dc, + clkoff_b => int_clkoff_b(0), + delay_lclkr => int_delay_lclkr(3), + mpw1_b => int_mpw1_b(3), + scan_in => iuq_uc_scan_in, + scan_out => iuq_uc_scan_out, + spr_ic_clockgate_dis => spr_ic_clockgate_dis(0), + iu_pc_err_ucode_illegal => iu_pc_err_ucode_illegal, + xu_iu_spr_xer0 => xu_iu_spr_xer0, + xu_iu_spr_xer1 => xu_iu_spr_xer1, + xu_iu_spr_xer2 => xu_iu_spr_xer2, + xu_iu_spr_xer3 => xu_iu_spr_xer3, + xu_iu_flush => xu_iu_flush, + xu_iu_ucode_restart => xu_iu_ucode_restart, + xu_iu_uc_flush_ifar0 => xu_iu_uc_flush_ifar0, + xu_iu_uc_flush_ifar1 => xu_iu_uc_flush_ifar1, + xu_iu_uc_flush_ifar2 => xu_iu_uc_flush_ifar2, + xu_iu_uc_flush_ifar3 => xu_iu_uc_flush_ifar3, + uc_flush_tid => int_uc_flush_tid, + fiss_uc_is2_ucode_vld => fiss_uc_is2_ucode_vld, + fiss_uc_is2_tid => fiss_uc_is2_tid, + fiss_uc_is2_instr => fiss_uc_is2_instr, + fiss_uc_is2_2ucode => fiss_uc_is2_2ucode, + fiss_uc_is2_2ucode_type => fiss_uc_is2_2ucode_type, + ib_uc_buff0_avail => ib_ic_below_water(0), + ib_uc_buff1_avail => ib_ic_below_water(1), + ib_uc_buff2_avail => ib_ic_below_water(2), + ib_uc_buff3_avail => ib_ic_below_water(3), + uc_ib_iu4_valid_tid => uc_ib_iu4_val, + uc_ib_iu4_ifar => uc_ib_iu4_ifar(62-uc_ifar to 61), + uc_ib_iu4_instr => uc_ib_iu4_instr(0 to 31), + uc_ib_iu4_is_ucode => uc_ib_iu4_instr(36), + uc_ib_iu4_ext => uc_ib_iu4_instr(32 to 35), + uc_ic_hold_thread => uc_ic_hold_thread, + pc_iu_trace_bus_enable => pc_iu_trace_bus_enable, + uc_dbg_data => uc_dbg_data +); +end generate u1; +iuq_rp0 : entity work.iuq_rp +generic map(expand_type => expand_type) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + scan_diag_dc => an_ac_scan_diag_dc, + scan_dis_dc_b => an_ac_scan_dis_dc_b, + an_ac_ccflush_dc => tc_ac_ccflush_dc, + rtim_sl_thold_7 => rtim_sl_thold_7, + func_sl_thold_7 => func_sl_thold_7, + func_nsl_thold_7 => func_nsl_thold_7, + ary_nsl_thold_7 => ary_nsl_thold_7, + sg_7 => sg_7, + fce_7 => fce_7, + rtim_sl_thold_6 => rtim_sl_thold_6, + func_sl_thold_6 => func_sl_thold_6, + func_nsl_thold_6 => func_nsl_thold_6, + ary_nsl_thold_6 => ary_nsl_thold_6, + sg_6 => sg_6, + fce_6 => fce_6, + an_ac_scom_dch => an_ac_scom_dch, + an_ac_scom_cch => an_ac_scom_cch, + an_ac_checkstop => an_ac_checkstop, + an_ac_debug_stop => an_ac_debug_stop, + an_ac_pm_thread_stop => an_ac_pm_thread_stop, + an_ac_reset_1_complete => an_ac_reset_1_complete, + an_ac_reset_2_complete => an_ac_reset_2_complete, + an_ac_reset_3_complete => an_ac_reset_3_complete, + an_ac_reset_wd_complete => an_ac_reset_wd_complete, + an_ac_abist_start_test => an_ac_abist_start_test, + ac_rp_trace_to_perfcntr => ac_rp_trace_to_perfcntr, + rp_pc_scom_dch_q => rp_pc_scom_dch_q, + rp_pc_scom_cch_q => rp_pc_scom_cch_q, + rp_pc_checkstop_q => rp_pc_checkstop_q, + rp_pc_debug_stop_q => rp_pc_debug_stop_q, + rp_pc_pm_thread_stop_q => rp_pc_pm_thread_stop_q, + rp_pc_reset_1_complete_q => rp_pc_reset_1_complete_q, + rp_pc_reset_2_complete_q => rp_pc_reset_2_complete_q, + rp_pc_reset_3_complete_q => rp_pc_reset_3_complete_q, + rp_pc_reset_wd_complete_q => rp_pc_reset_wd_complete_q, + rp_pc_abist_start_test_q => rp_pc_abist_start_test_q, + rp_pc_trace_to_perfcntr_q => rp_pc_trace_to_perfcntr_q, + pc_rp_scom_dch => pc_rp_scom_dch, + pc_rp_scom_cch => pc_rp_scom_cch, + pc_rp_special_attn => pc_rp_special_attn, + pc_rp_checkstop => pc_rp_checkstop, + pc_rp_local_checkstop => pc_rp_local_checkstop, + pc_rp_recov_err => pc_rp_recov_err, + pc_rp_trace_error => pc_rp_trace_error, + pc_rp_event_bus_enable => pc_rp_event_bus_enable, + pc_rp_event_bus => pc_rp_event_bus, + pc_rp_fu_bypass_events => pc_rp_fu_bypass_events, + pc_rp_iu_bypass_events => pc_rp_iu_bypass_events, + pc_rp_mm_bypass_events => pc_rp_mm_bypass_events, + pc_rp_lsu_bypass_events => pc_rp_lsu_bypass_events, + pc_rp_pm_thread_running => pc_rp_pm_thread_running, + pc_rp_power_managed => pc_rp_power_managed, + pc_rp_rvwinkle_mode => pc_rp_rvwinkle_mode, + ac_an_scom_dch_q => ac_an_scom_dch_q, + ac_an_scom_cch_q => ac_an_scom_cch_q, + ac_an_special_attn_q => ac_an_special_attn_q, + ac_an_checkstop_q => ac_an_checkstop_q, + ac_an_local_checkstop_q => ac_an_local_checkstop_q, + ac_an_recov_err_q => ac_an_recov_err_q, + ac_an_trace_error_q => ac_an_trace_error_q, + rp_mm_event_bus_enable_q => rp_mm_event_bus_enable_q, + ac_an_event_bus_q => ac_an_event_bus_q, + ac_an_fu_bypass_events_q => ac_an_fu_bypass_events_q, + ac_an_iu_bypass_events_q => ac_an_iu_bypass_events_q, + ac_an_mm_bypass_events_q => ac_an_mm_bypass_events_q, + ac_an_lsu_bypass_events_q => ac_an_lsu_bypass_events_q, + ac_an_pm_thread_running_q => ac_an_pm_thread_running_q, + ac_an_power_managed_q => ac_an_power_managed_q_int, + ac_an_rvwinkle_mode_q => ac_an_rvwinkle_mode_q, + pc_func_scan_in => pc_func_scan_in, + pc_func_scan_in_q => pc_func_scan_in_q, + pc_func_scan_out => pc_func_scan_out, + pc_func_scan_out_q => pc_func_scan_out_q, + pc_bcfg_scan_in => pc_bcfg_scan_in, + pc_bcfg_scan_in_q => pc_bcfg_scan_in_q, + pc_dcfg_scan_in => pc_dcfg_scan_in, + pc_dcfg_scan_in_q => pc_dcfg_scan_in_q, + pc_bcfg_scan_out => pc_bcfg_scan_out, + pc_bcfg_scan_out_q => pc_bcfg_scan_out_q, + pc_ccfg_scan_out => pc_ccfg_scan_out, + pc_ccfg_scan_out_q => pc_ccfg_scan_out_q, + pc_dcfg_scan_out => pc_dcfg_scan_out, + pc_dcfg_scan_out_q => pc_dcfg_scan_out_q, + fu_abst_scan_in => fu_abst_scan_in, + fu_abst_scan_in_q => fu_abst_scan_in_q, + fu_abst_scan_out => fu_abst_scan_out, + fu_abst_scan_out_q => fu_abst_scan_out_q, + fu_ccfg_scan_out => fu_ccfg_scan_out, + fu_ccfg_scan_out_q => fu_ccfg_scan_out_q, + fu_bcfg_scan_out => fu_bcfg_scan_out, + fu_bcfg_scan_out_q => fu_bcfg_scan_out_q, + fu_dcfg_scan_out => fu_dcfg_scan_out, + fu_dcfg_scan_out_q => fu_dcfg_scan_out_q, + fu_func_scan_in => fu_func_scan_in, + fu_func_scan_in_q => fu_func_scan_in_q, + fu_func_scan_out => fu_func_scan_out, + fu_func_scan_out_q => fu_func_scan_out_q, + bx_abst_scan_in => bx_abst_scan_in, + bx_abst_scan_in_q => bx_abst_scan_in_q, + bx_abst_scan_out => bx_abst_scan_out, + bx_abst_scan_out_q => bx_abst_scan_out_q, + bx_func_scan_in => bx_func_scan_in, + bx_func_scan_in_q => bx_func_scan_in_q, + bx_func_scan_out => bx_func_scan_out, + bx_func_scan_out_q => bx_func_scan_out_q, + iu_func_scan_in => iu_func_scan_in, + iu_func_scan_in_q => int_iu_func_scan_in_q, + iu_func_scan_out => int_iu_func_scan_out, + iu_func_scan_out_q => iu_func_scan_out_q, + iu_bcfg_scan_in => bcfg_scan_in, + iu_bcfg_scan_in_q => bcfg_scan_in_q, + spare_func_scan_in => spare_func_scan_in, + spare_func_scan_in_q => spare_func_scan_in_q, + spare_func_scan_out => spare_func_scan_in_q, + spare_func_scan_out_q => spare_func_scan_out_q, + bg_an_ac_func_scan_sn => bg_an_ac_func_scan_sn, + bg_an_ac_abst_scan_sn => bg_an_ac_abst_scan_sn, + bg_an_ac_func_scan_sn_q => bg_an_ac_func_scan_sn_q, + bg_an_ac_abst_scan_sn_q => bg_an_ac_abst_scan_sn_q, + bg_ac_an_func_scan_ns => bg_ac_an_func_scan_ns, + bg_ac_an_abst_scan_ns => bg_ac_an_abst_scan_ns, + bg_ac_an_func_scan_ns_q => bg_ac_an_func_scan_ns_q, + bg_ac_an_abst_scan_ns_q => bg_ac_an_abst_scan_ns_q, + bg_pc_l1p_abist_di_0 => bg_pc_l1p_abist_di_0, + bg_pc_l1p_abist_g8t1p_renb_0 => bg_pc_l1p_abist_g8t1p_renb_0, + bg_pc_l1p_abist_g8t_bw_0 => bg_pc_l1p_abist_g8t_bw_0, + bg_pc_l1p_abist_g8t_bw_1 => bg_pc_l1p_abist_g8t_bw_1, + bg_pc_l1p_abist_g8t_dcomp => bg_pc_l1p_abist_g8t_dcomp, + bg_pc_l1p_abist_g8t_wenb => bg_pc_l1p_abist_g8t_wenb, + bg_pc_l1p_abist_raddr_0 => bg_pc_l1p_abist_raddr_0, + bg_pc_l1p_abist_waddr_0 => bg_pc_l1p_abist_waddr_0, + bg_pc_l1p_abist_wl128_comp_ena => bg_pc_l1p_abist_wl128_comp_ena, + bg_pc_l1p_abist_wl32_comp_ena => bg_pc_l1p_abist_wl32_comp_ena, + bg_pc_l1p_abist_di_0_q => bg_pc_l1p_abist_di_0_q, + bg_pc_l1p_abist_g8t1p_renb_0_q => bg_pc_l1p_abist_g8t1p_renb_0_q, + bg_pc_l1p_abist_g8t_bw_0_q => bg_pc_l1p_abist_g8t_bw_0_q, + bg_pc_l1p_abist_g8t_bw_1_q => bg_pc_l1p_abist_g8t_bw_1_q, + bg_pc_l1p_abist_g8t_dcomp_q=> bg_pc_l1p_abist_g8t_dcomp_q, + bg_pc_l1p_abist_g8t_wenb_q => bg_pc_l1p_abist_g8t_wenb_q, + bg_pc_l1p_abist_raddr_0_q => bg_pc_l1p_abist_raddr_0_q, + bg_pc_l1p_abist_waddr_0_q => bg_pc_l1p_abist_waddr_0_q, + bg_pc_l1p_abist_wl128_comp_ena_q => bg_pc_l1p_abist_wl128_comp_ena_q, + bg_pc_l1p_abist_wl32_comp_ena_q => bg_pc_l1p_abist_wl32_comp_ena_q, + bg_pc_l1p_gptr_sl_thold_3 => bg_pc_l1p_gptr_sl_thold_3, + bg_pc_l1p_time_sl_thold_3 => bg_pc_l1p_time_sl_thold_3, + bg_pc_l1p_repr_sl_thold_3 => bg_pc_l1p_repr_sl_thold_3, + bg_pc_l1p_abst_sl_thold_3 => bg_pc_l1p_abst_sl_thold_3, + bg_pc_l1p_func_sl_thold_3 => bg_pc_l1p_func_sl_thold_3, + bg_pc_l1p_func_slp_sl_thold_3 => bg_pc_l1p_func_slp_sl_thold_3, + bg_pc_l1p_bolt_sl_thold_3 => bg_pc_l1p_bolt_sl_thold_3, + bg_pc_l1p_ary_nsl_thold_3 => bg_pc_l1p_ary_nsl_thold_3, + bg_pc_l1p_sg_3 => bg_pc_l1p_sg_3, + bg_pc_l1p_fce_3 => bg_pc_l1p_fce_3, + bg_pc_l1p_bo_enable_3 => bg_pc_l1p_bo_enable_3, + bg_pc_l1p_gptr_sl_thold_2 => bg_pc_l1p_gptr_sl_thold_2, + bg_pc_l1p_time_sl_thold_2 => bg_pc_l1p_time_sl_thold_2, + bg_pc_l1p_repr_sl_thold_2 => bg_pc_l1p_repr_sl_thold_2, + bg_pc_l1p_abst_sl_thold_2 => bg_pc_l1p_abst_sl_thold_2, + bg_pc_l1p_func_sl_thold_2 => bg_pc_l1p_func_sl_thold_2, + bg_pc_l1p_func_slp_sl_thold_2 => bg_pc_l1p_func_slp_sl_thold_2, + bg_pc_l1p_bolt_sl_thold_2 => bg_pc_l1p_bolt_sl_thold_2, + bg_pc_l1p_ary_nsl_thold_2 => bg_pc_l1p_ary_nsl_thold_2, + bg_pc_l1p_sg_2 => bg_pc_l1p_sg_2, + bg_pc_l1p_fce_2 => bg_pc_l1p_fce_2, + bg_pc_l1p_bo_enable_2 => bg_pc_l1p_bo_enable_2, + pc_mm_bo_enable_4 => pc_mm_bo_enable_4_iiu, + pc_iu_bo_enable_4 => pc_iu_bo_enable_4, + pc_mm_bo_enable_3 => pc_mm_bo_enable_3_oiu, + pc_iu_bo_enable_3 => pc_iu_bo_enable_3, + pc_iu_gptr_sl_thold_4 => pc_iu_gptr_sl_thold_4, + pc_iu_time_sl_thold_4 => pc_iu_time_sl_thold_4, + pc_iu_repr_sl_thold_4 => pc_iu_repr_sl_thold_4, + pc_iu_abst_sl_thold_4 => pc_iu_abst_sl_thold_4, + pc_iu_abst_slp_sl_thold_4 => pc_iu_abst_slp_sl_thold_4, + pc_iu_bolt_sl_thold_4 => pc_iu_bolt_sl_thold_4, + pc_iu_regf_slp_sl_thold_4 => pc_iu_regf_slp_sl_thold_4, + pc_iu_func_sl_thold_4 => pc_iu_func_sl_thold_4, + pc_iu_func_slp_sl_thold_4 => pc_iu_func_slp_sl_thold_4, + pc_iu_cfg_sl_thold_4 => pc_iu_cfg_sl_thold_4, + pc_iu_cfg_slp_sl_thold_4 => pc_iu_cfg_slp_sl_thold_4, + pc_iu_func_nsl_thold_4 => pc_iu_func_nsl_thold_4, + pc_iu_func_slp_nsl_thold_4 => pc_iu_func_slp_nsl_thold_4, + pc_iu_ary_nsl_thold_4 => pc_iu_ary_nsl_thold_4, + pc_iu_ary_slp_nsl_thold_4 => pc_iu_ary_slp_nsl_thold_4, + pc_iu_sg_4 => pc_iu_sg_4, + pc_iu_fce_4 => pc_iu_fce_4, + pc_iu_gptr_sl_thold_3 => pc_iu_gptr_sl_thold_3, + pc_iu_time_sl_thold_3 => pc_iu_time_sl_thold_3, + pc_iu_repr_sl_thold_3 => pc_iu_repr_sl_thold_3, + pc_iu_abst_sl_thold_3 => pc_iu_abst_sl_thold_3, + pc_iu_abst_slp_sl_thold_3 => pc_iu_abst_slp_sl_thold_3, + pc_iu_bolt_sl_thold_3 => pc_iu_bolt_sl_thold_3, + pc_iu_regf_slp_sl_thold_3 => pc_iu_regf_slp_sl_thold_3, + pc_iu_func_sl_thold_3 => pc_iu_func_sl_thold_3, + pc_iu_func_slp_sl_thold_3 => pc_iu_func_slp_sl_thold_3, + pc_iu_cfg_sl_thold_3 => pc_iu_cfg_sl_thold_3, + pc_iu_cfg_slp_sl_thold_3 => pc_iu_cfg_slp_sl_thold_3, + pc_iu_func_slp_nsl_thold_3 => pc_iu_func_slp_nsl_thold_3, + pc_iu_ary_nsl_thold_3 => pc_iu_ary_nsl_thold_3, + pc_iu_ary_slp_nsl_thold_3 => pc_iu_ary_slp_nsl_thold_3, + pc_iu_sg_3 => pc_iu_sg_3, + pc_iu_fce_3 => pc_iu_fce_3, + pc_mm_gptr_sl_thold_3 => pc_mm_gptr_sl_thold_3, + pc_mm_time_sl_thold_3 => pc_mm_time_sl_thold_3, + pc_mm_repr_sl_thold_3 => pc_mm_repr_sl_thold_3, + pc_mm_abst_sl_thold_3 => pc_mm_abst_sl_thold_3, + pc_mm_abst_slp_sl_thold_3 => pc_mm_abst_slp_sl_thold_3, + pc_mm_bolt_sl_thold_3 => pc_mm_bolt_sl_thold_3, + pc_mm_func_sl_thold_3 => pc_mm_func_sl_thold_3, + pc_mm_func_slp_sl_thold_3 => pc_mm_func_slp_sl_thold_3, + pc_mm_cfg_sl_thold_3 => pc_mm_cfg_sl_thold_3, + pc_mm_cfg_slp_sl_thold_3 => pc_mm_cfg_slp_sl_thold_3, + pc_mm_func_nsl_thold_3 => pc_mm_func_nsl_thold_3, + pc_mm_func_slp_nsl_thold_3 => pc_mm_func_slp_nsl_thold_3, + pc_mm_ary_nsl_thold_3 => pc_mm_ary_nsl_thold_3, + pc_mm_ary_slp_nsl_thold_3 => pc_mm_ary_slp_nsl_thold_3, + pc_mm_sg_3 => pc_mm_sg_3, + pc_mm_fce_3 => pc_mm_fce_3, + sg_2 => int_pc_iu_sg_2(0), + func_sl_thold_2 => int_pc_iu_func_sl_thold_2(0), + func_slp_sl_thold_2 => pc_iu_func_slp_sl_thold_2, + abst_sl_thold_2 => pc_iu_abst_sl_thold_2, + abst_scan_in => rp_abst_scan_in, + func_scan_in => rp_func_scan_in, + gptr_scan_in => rp_gptr_scan_in, + abst_scan_out => rp_abst_scan_out, + func_scan_out => rp_func_scan_out, + gptr_scan_out => rp_gptr_scan_out +); +-- Pass thru signals +bg_pc_bo_unload_oiu <= bg_pc_bo_unload_iiu; +bg_pc_bo_load_oiu <= bg_pc_bo_load_iiu; +bg_pc_bo_repair_oiu <= bg_pc_bo_repair_iiu; +bg_pc_bo_reset_oiu <= bg_pc_bo_reset_iiu; +bg_pc_bo_shdata_oiu <= bg_pc_bo_shdata_iiu; +bg_pc_bo_select_oiu <= bg_pc_bo_select_iiu; +bg_pc_l1p_ccflush_dc_oiu <= bg_pc_l1p_ccflush_dc_iiu; +bg_pc_l1p_abist_ena_dc_oiu <= bg_pc_l1p_abist_ena_dc_iiu; +bg_pc_l1p_abist_raw_dc_b_oiu <= bg_pc_l1p_abist_raw_dc_b_iiu; +ac_an_abist_done_dc_oiu <= ac_an_abist_done_dc_iiu; +u_psro_rsig_i1: ac_an_psro_ringsig_i1_b <= not ac_an_psro_ringsig_iiu; +u_psro_rsig_i2: ac_an_psro_ringsig_i2 <= not ac_an_psro_ringsig_i1_b; +u_psro_rsig_i3: ac_an_psro_ringsig_i3_b <= not ac_an_psro_ringsig_i2; +u_psro_rsig_i4: ac_an_psro_ringsig_i4 <= not ac_an_psro_ringsig_i3_b; +u_psro_rsig_i5: ac_an_psro_ringsig_i5_b <= not ac_an_psro_ringsig_i4; +u_psro_rsig_i6: ac_an_psro_ringsig_oiu <= not ac_an_psro_ringsig_i5_b; +mm_pc_bo_fail_oiu <= mm_pc_bo_fail_iiu; +mm_pc_bo_diagout_oiu <= mm_pc_bo_diagout_iiu; +mm_pc_event_data_oiu <= mm_pc_event_data_iiu; +bg_pc_bo_fail_oiu <= bg_pc_bo_fail_iiu; +bg_pc_bo_diagout_oiu <= bg_pc_bo_diagout_iiu; +an_ac_abist_mode_dc_oiu <= an_ac_abist_mode_dc_iiu; +an_ac_ccenable_dc_oiu <= an_ac_ccenable_dc_iiu; +an_ac_ccflush_dc_oiu <= an_ac_ccflush_dc_iiu; +an_ac_gsd_test_enable_dc_oiu <= an_ac_gsd_test_enable_dc_iiu; +an_ac_gsd_test_acmode_dc_oiu <= an_ac_gsd_test_acmode_dc_iiu; +an_ac_lbist_ip_dc_oiu <= an_ac_lbist_ip_dc_iiu; +an_ac_lbist_ac_mode_dc_oiu <= an_ac_lbist_ac_mode_dc_iiu; +an_ac_malf_alert_oiu <= an_ac_malf_alert_iiu; +an_ac_psro_enable_dc_oiu <= an_ac_psro_enable_dc_iiu; +an_ac_scan_type_dc_oiu <= an_ac_scan_type_dc_iiu; +an_ac_scom_sat_id_oiu <= an_ac_scom_sat_id_iiu; +pc_mm_abist_dcomp_g6t_2r_oiu <= pc_mm_abist_dcomp_g6t_2r_iiu; +pc_mm_abist_di_g6t_2r_oiu <= pc_mm_abist_di_g6t_2r_iiu; +pc_mm_abist_di_0_oiu <= pc_mm_abist_di_0_iiu; +pc_mm_abist_ena_dc_oiu <= pc_mm_abist_ena_dc_iiu; +pc_mm_abist_g6t_r_wb_oiu <= pc_mm_abist_g6t_r_wb_iiu; +pc_mm_abist_g8t_bw_0_oiu <= pc_mm_abist_g8t_bw_0_iiu; +pc_mm_abist_g8t_bw_1_oiu <= pc_mm_abist_g8t_bw_1_iiu; +pc_mm_abist_g8t_dcomp_oiu <= pc_mm_abist_g8t_dcomp_iiu; +pc_mm_abist_g8t_wenb_oiu <= pc_mm_abist_g8t_wenb_iiu; +pc_mm_abist_g8t1p_renb_0_oiu <= pc_mm_abist_g8t1p_renb_0_iiu; +pc_mm_abist_raddr_0_oiu <= pc_mm_abist_raddr_0_iiu; +pc_mm_abist_raw_dc_b_oiu <= pc_mm_abist_raw_dc_b_iiu; +pc_mm_abist_waddr_0_oiu <= pc_mm_abist_waddr_0_iiu; +pc_mm_abist_wl128_comp_ena_oiu <= pc_mm_abist_wl128_comp_ena_iiu; +pc_mm_bo_repair_oiu <= pc_mm_bo_repair_iiu; +pc_mm_bo_reset_oiu <= pc_mm_bo_reset_iiu; +pc_mm_bo_select_oiu <= pc_mm_bo_select_iiu; +pc_mm_bo_shdata_oiu <= pc_mm_bo_shdata_iiu; +pc_mm_bo_unload_oiu <= pc_mm_bo_unload_iiu; +pc_mm_ccflush_dc_oiu <= pc_mm_ccflush_dc_iiu; +pc_mm_debug_mux1_ctrls_oiu <= pc_mm_debug_mux1_ctrls_iiu; +pc_mm_event_count_mode_oiu <= pc_mm_event_count_mode_iiu; +pc_mm_event_mux_ctrls_oiu <= pc_mm_event_mux_ctrls_iiu; +pc_mm_trace_bus_enable_oiu <= pc_mm_trace_bus_enable_iiu; +pc_mm_gptr_sl_thold_3_oiu <= pc_mm_gptr_sl_thold_3; +pc_mm_time_sl_thold_3_oiu <= pc_mm_time_sl_thold_3; +pc_mm_repr_sl_thold_3_oiu <= pc_mm_repr_sl_thold_3; +pc_mm_abst_sl_thold_3_oiu <= pc_mm_abst_sl_thold_3; +pc_mm_abst_slp_sl_thold_3_oiu <= pc_mm_abst_slp_sl_thold_3; +pc_mm_bolt_sl_thold_3_oiu <= pc_mm_bolt_sl_thold_3; +pc_mm_func_sl_thold_3_oiu <= pc_mm_func_sl_thold_3; +pc_mm_func_slp_sl_thold_3_oiu <= pc_mm_func_slp_sl_thold_3; +pc_mm_cfg_sl_thold_3_oiu <= pc_mm_cfg_sl_thold_3; +pc_mm_cfg_slp_sl_thold_3_oiu <= pc_mm_cfg_slp_sl_thold_3; +pc_mm_func_nsl_thold_3_oiu <= pc_mm_func_nsl_thold_3; +pc_mm_func_slp_nsl_thold_3_oiu <= pc_mm_func_slp_nsl_thold_3; +pc_mm_ary_nsl_thold_3_oiu <= pc_mm_ary_nsl_thold_3; +pc_mm_ary_slp_nsl_thold_3_oiu <= pc_mm_ary_slp_nsl_thold_3; +pc_mm_sg_3_oiu <= pc_mm_sg_3; +pc_mm_fce_3_oiu <= pc_mm_fce_3; +an_ac_back_inv_oiu <= an_ac_back_inv; +an_ac_back_inv_addr_oiu <= an_ac_back_inv_addr; +an_ac_back_inv_target_bit1_oiu <= an_ac_back_inv_target_iiu_a(1); +an_ac_back_inv_target_bit3_oiu <= an_ac_back_inv_target_iiu_b(3); +an_ac_back_inv_target_bit4_oiu <= an_ac_back_inv_target_iiu_b(4); +an_ac_atpg_en_dc_oiu <= an_ac_atpg_en_dc; +an_ac_lbist_ary_wrt_thru_dc_oiu <= an_ac_lbist_ary_wrt_thru_dc; +an_ac_lbist_en_dc_oiu <= an_ac_lbist_en_dc; +an_ac_scan_diag_dc_oiu <= an_ac_scan_diag_dc; +an_ac_scan_dis_dc_b_oiu <= an_ac_scan_dis_dc_b; +an_ac_grffence_en_dc_oiu <= an_ac_grffence_en_dc; +an_ac_scan_dis_dc_b_oif(0) <= an_ac_scan_dis_dc_b; +an_ac_scan_dis_dc_b_oif(1) <= an_ac_scan_dis_dc_b; +an_ac_scan_dis_dc_b_oif(2) <= an_ac_scan_dis_dc_b; +an_ac_scan_dis_dc_b_oif(3) <= an_ac_scan_dis_dc_b; +an_ac_back_inv_oif <= an_ac_back_inv; +an_ac_back_inv_target_oif(1) <= an_ac_back_inv_target_iiu_a(1); +an_ac_sync_ack_oif <= an_ac_sync_ack; +mm_iu_barrier_done_oif <= mm_iu_barrier_done; +--------------------------------------- +-- scan chains +--------------------------------------- +--1130 +iuq_ic_scan_in(0) <= func_scan_in(0); +func_scan_out(0) <= iuq_ic_scan_out(0); +--1046 +iuq_ic_scan_in(1) <= func_scan_in(1); +func_scan_out(1) <= iuq_ic_scan_out(1); +--1240 +iuq_ic_scan_in(2) <= func_scan_in(2); +func_scan_out(2) <= iuq_ic_scan_out(2); +iu_func_scan_in(0) <= func_scan_in(3); +iuq_bp_scan_in(1) <= int_iu_func_scan_in_q(0); +int_iu_func_scan_out(0) <= int_iuq_bp_scan_out(1); +int_iu_func_scan_out(1 to 8) <= iu_func_scan_out; +func_scan_out(3 to 11) <= iu_func_scan_out_q(0 to 8); +--1167 +iu_func_scan_in(1) <= func_scan_in(4); +iuq_bp_scan_in(0) <= int_iu_func_scan_in_q(1); +iu_func_scan_in(2) <= func_scan_in(5); +iuq_mi_scan_in(0) <= int_iu_func_scan_in_q(2); +iu_func_scan_in(3) <= func_scan_in(6); +iu_func_scan_in_q(0) <= int_iu_func_scan_in_q(3); +iu_func_scan_in(4) <= func_scan_in(7); +iuq_mi_scan_in(1) <= int_iu_func_scan_in_q(4); +iu_func_scan_in(5 to 8) <= func_scan_in(8 to 11); +iu_func_scan_in_q(1 to 4) <= int_iu_func_scan_in_q(5 to 8); +iuq_ic_scan_in(3) <= func_scan_in(12); +func_scan_out(12) <= iuq_ic_scan_out(3); +-- 1035 +iuq_ic_scan_in(4) <= func_scan_in(13); +iuq_uc_scan_in <= iuq_ic_scan_out(4); +int_iu_func_scan_out(9) <= iuq_uc_scan_out; +func_scan_out(13) <= iu_func_scan_out_q(9); +iuq_ic_time_scan_in <= time_scan_in; +iuq_mi_time_scan_in <= iuq_ic_time_scan_out; +time_scan_out <= iuq_mi_time_scan_out; +iuq_ic_repr_scan_in <= repr_scan_in; +iuq_mi_repr_scan_in <= iuq_ic_repr_scan_out; +repr_scan_out <= iuq_mi_repr_scan_out; +iuq_mi_abst_scan_in <= iuq_ic_abst_scan_out(2); +rp_gptr_scan_in <= gptr_scan_in; +iuq_mi_gptr_scan_in <= rp_gptr_scan_out; +gptr_scan_out <= iuq_mi_gptr_scan_out; +iuq_mi_ccfg_scan_in <= ccfg_scan_in; +iuq_ic_ccfg_scan_in <= iuq_mi_ccfg_scan_out; +ccfg_scan_out <= iuq_ic_ccfg_scan_out; +iuq_mi_bcfg_scan_in <= bcfg_scan_in_q; +bcfg_scan_out <= iuq_mi_bcfg_scan_out; +iuq_mi_dcfg_scan_in <= dcfg_scan_in; +dcfg_scan_out <= iuq_mi_dcfg_scan_out; +end iuq_ifetch; + + diff --git a/rel/src/vhdl/work/iuq_misc.vhdl b/rel/src/vhdl/work/iuq_misc.vhdl new file mode 100644 index 0000000..7730db4 --- /dev/null +++ b/rel/src/vhdl/work/iuq_misc.vhdl @@ -0,0 +1,739 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; +use ieee.std_logic_1164.all; + +library ibm; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; + +library support; +use support.power_logic_pkg.all; + +library tri; +use tri.tri_latches_pkg.all; + +library work; +use work.iuq_pkg.all; + +entity iuq_misc is +generic(regmode : integer := 6; + a2mode : integer := 1; + expand_type : integer := 2 ); -- 0 = ibm umbra, 1 = xilinx, 2 = ibm mpg +port( + vdd : inout power_logic; + gnd : inout power_logic; + vcs : inout power_logic; + nclk : in clk_logic; + pc_iu_sg_3 : in std_ulogic_vector(0 to 3); + pc_iu_func_sl_thold_3 : in std_ulogic_vector(0 to 3); + pc_iu_func_slp_sl_thold_3 : in std_ulogic; + pc_iu_gptr_sl_thold_3 : in std_ulogic; + pc_iu_time_sl_thold_3 : in std_ulogic; + pc_iu_repr_sl_thold_3 : in std_ulogic; + pc_iu_abst_sl_thold_3 : in std_ulogic; + pc_iu_abst_slp_sl_thold_3 : in std_ulogic; + pc_iu_cfg_sl_thold_3 : in std_ulogic; + pc_iu_cfg_slp_sl_thold_3 : in std_ulogic; + pc_iu_regf_slp_sl_thold_3 : in std_ulogic; + pc_iu_ary_nsl_thold_3 : in std_ulogic; + pc_iu_ary_slp_nsl_thold_3 : in std_ulogic; + pc_iu_func_slp_nsl_thold_3 : in std_ulogic; + pc_iu_bolt_sl_thold_3 : in std_ulogic; + pc_iu_fce_3 : in std_ulogic; + tc_ac_ccflush_dc : in std_ulogic; + scan_diag_dc : in std_ulogic; + pc_iu_sg_2 : out std_ulogic_vector(0 to 3); + pc_iu_func_sl_thold_2 : out std_ulogic_vector(0 to 3); + pc_iu_func_slp_sl_thold_2 : out std_ulogic; + pc_iu_time_sl_thold_2 : out std_ulogic; + pc_iu_repr_sl_thold_2 : out std_ulogic; + pc_iu_abst_sl_thold_2 : out std_ulogic; + pc_iu_abst_slp_sl_thold_2 : out std_ulogic; + pc_iu_cfg_slp_sl_thold_2 : out std_ulogic; + pc_iu_regf_slp_sl_thold_2 : out std_ulogic; + pc_iu_ary_nsl_thold_2 : out std_ulogic; + pc_iu_ary_slp_nsl_thold_2 : out std_ulogic; + pc_iu_func_slp_nsl_thold_2 : out std_ulogic; + pc_iu_bolt_sl_thold_2 : out std_ulogic; + pc_iu_fce_2 : out std_ulogic; + + clkoff_b : out std_ulogic_vector(0 to 2); + delay_lclkr : out std_ulogic_vector(1 to 14); + mpw1_b : out std_ulogic_vector(1 to 14); + + g8t_clkoff_b : out std_ulogic; + g8t_d_mode : out std_ulogic; + g8t_delay_lclkr : out std_ulogic_vector(0 to 4); + g8t_mpw1_b : out std_ulogic_vector(0 to 4); + g8t_mpw2_b : out std_ulogic; + + g6t_clkoff_b : out std_ulogic; + g6t_d_mode : out std_ulogic; + g6t_delay_lclkr : out std_ulogic_vector(0 to 3); + g6t_mpw1_b : out std_ulogic_vector(0 to 4); + g6t_mpw2_b : out std_ulogic; + + cam_clkoff_b : out std_ulogic; + cam_d_mode : out std_ulogic; + cam_delay_lclkr : out std_ulogic_vector(0 to 4); + cam_mpw1_b : out std_ulogic_vector(0 to 4); + cam_mpw2_b : out std_ulogic; + + an_ac_scan_dis_dc_b : in std_ulogic; + func_scan_in : in std_ulogic_vector(0 to 1); + gptr_scan_in : in std_ulogic; + time_scan_in : in std_ulogic; + abst_scan_in : in std_ulogic; + repr_scan_in : in std_ulogic; + ccfg_scan_in : in std_ulogic; + bcfg_scan_in : in std_ulogic; + dcfg_scan_in : in std_ulogic; + func_scan_out : out std_ulogic_vector(0 to 1); + gptr_scan_out : out std_ulogic; + time_scan_out : out std_ulogic; + abst_scan_out : out std_ulogic; + repr_scan_out : out std_ulogic; + ccfg_scan_out : out std_ulogic; + bcfg_scan_out : out std_ulogic; + dcfg_scan_out : out std_ulogic; + + pc_iu_abist_di_0 : in std_ulogic_vector(0 to 3); + pc_iu_abist_g8t_bw_1 : in std_ulogic; + pc_iu_abist_g8t_bw_0 : in std_ulogic; + pc_iu_abist_waddr_0 : in std_ulogic_vector(3 to 9); + pc_iu_abist_g8t_wenb : in std_ulogic; + pc_iu_abist_raddr_0 : in std_ulogic_vector(3 to 9); + pc_iu_abist_g8t1p_renb_0 : in std_ulogic; + an_ac_lbist_ary_wrt_thru_dc: in std_ulogic; + pc_iu_abist_ena_dc : in std_ulogic; + pc_iu_abist_wl128_comp_ena : in std_ulogic; + pc_iu_abist_raw_dc_b : in std_ulogic; + pc_iu_abist_g8t_dcomp : in std_ulogic_vector(0 to 3); + + pc_iu_bo_enable_3 : in std_ulogic; + pc_iu_bo_reset : in std_ulogic; + pc_iu_bo_unload : in std_ulogic; + pc_iu_bo_repair : in std_ulogic; + pc_iu_bo_shdata : in std_ulogic; + pc_iu_bo_select : in std_ulogic; + iu_pc_bo_fail : out std_ulogic; + iu_pc_bo_diagout : out std_ulogic; + + -- bht + r_act : in std_ulogic; + w_act : in std_ulogic_vector(0 to 3); + r_addr : in std_ulogic_vector(0 to 7); + w_addr : in std_ulogic_vector(0 to 7); + data_in : in std_ulogic_vector(0 to 1); + data_out0 : out std_ulogic_vector(0 to 1); + data_out1 : out std_ulogic_vector(0 to 1); + data_out2 : out std_ulogic_vector(0 to 1); + data_out3 : out std_ulogic_vector(0 to 1); + + pc_iu_ram_instr : in std_ulogic_vector(0 to 31); + pc_iu_ram_instr_ext : in std_ulogic_vector(0 to 3); + pc_iu_ram_force_cmplt : in std_ulogic; + xu_iu_ram_issue : in std_ulogic_vector(0 to 3); + rm_ib_iu4_val : out std_ulogic_vector(0 to 3); + rm_ib_iu4_force_ram : out std_ulogic; + rm_ib_iu4_instr : out std_ulogic_vector(0 to 35); + + -- spr + slowspr_val_in : in std_ulogic; + slowspr_rw_in : in std_ulogic; + slowspr_etid_in : in std_ulogic_vector(0 to 1); + slowspr_addr_in : in std_ulogic_vector(0 to 9); + slowspr_data_in : in std_ulogic_vector(64-(2**regmode) to 63); + slowspr_done_in : in std_ulogic; + slowspr_val_out : out std_ulogic; + slowspr_rw_out : out std_ulogic; + slowspr_etid_out : out std_ulogic_vector(0 to 1); + slowspr_addr_out : out std_ulogic_vector(0 to 9); + slowspr_data_out : out std_ulogic_vector(64-(2**regmode) to 63); + slowspr_done_out : out std_ulogic; + spr_ic_idir_read : out std_ulogic; + spr_ic_idir_way : out std_ulogic_vector(0 to 1); + spr_ic_idir_row : out std_ulogic_vector(52 to 57); + ic_spr_idir_done : in std_ulogic; + ic_spr_idir_lru : in std_ulogic_vector(0 to 2); + ic_spr_idir_parity : in std_ulogic_vector(0 to 3); + ic_spr_idir_endian : in std_ulogic; + ic_spr_idir_valid : in std_ulogic; + ic_spr_idir_tag : in std_ulogic_vector(0 to 29); + spr_ic_icbi_ack_en : out std_ulogic; + spr_ic_cls : out std_ulogic; + spr_ic_clockgate_dis : out std_ulogic_vector(0 to 1); + spr_ic_bp_config : out std_ulogic_vector(0 to 3); + spr_bp_config : out std_ulogic_vector(0 to 3); + spr_bp_gshare_mask : out std_ulogic_vector(0 to 3); + spr_dec_mask : out std_ulogic_vector(0 to 31); + spr_dec_match : out std_ulogic_vector(0 to 31); + iu_au_config_iucr_t0 : out std_ulogic_vector(0 to 7); + iu_au_config_iucr_t1 : out std_ulogic_vector(0 to 7); + iu_au_config_iucr_t2 : out std_ulogic_vector(0 to 7); + iu_au_config_iucr_t3 : out std_ulogic_vector(0 to 7); + spr_issue_high_mask : out std_ulogic_vector(0 to 3); + spr_issue_med_mask : out std_ulogic_vector(0 to 3); + spr_fiss_count0_max : out std_ulogic_vector(0 to 5); + spr_fiss_count1_max : out std_ulogic_vector(0 to 5); + spr_fiss_count2_max : out std_ulogic_vector(0 to 5); + spr_fiss_count3_max : out std_ulogic_vector(0 to 5); + spr_ic_pri_rand : out std_ulogic_vector(0 to 4); + spr_ic_pri_rand_always : out std_ulogic; + spr_ic_pri_rand_flush : out std_ulogic; + spr_fiss_pri_rand : out std_ulogic_vector(0 to 4); + spr_fiss_pri_rand_always : out std_ulogic; + spr_fiss_pri_rand_flush : out std_ulogic; + spr_fdep_ll_hold : out std_ulogic; + xu_iu_run_thread : in std_ulogic_vector(0 to 3); + xu_iu_ex6_pri : in std_ulogic_vector(0 to 2); + xu_iu_ex6_pri_val : in std_ulogic_vector(0 to 3); + xu_iu_raise_iss_pri : in std_ulogic_vector(0 to 3); + xu_iu_msr_gs : in std_ulogic_vector(0 to 3); + xu_iu_msr_pr : in std_ulogic_vector(0 to 3); + + --dbg + pc_iu_trace_bus_enable : in std_ulogic; + pc_iu_debug_mux_ctrls : in std_ulogic_vector(0 to 15); + debug_data_in : in std_ulogic_vector(0 to 87); + trace_triggers_in : in std_ulogic_vector(0 to 11); + debug_data_out : out std_ulogic_vector(0 to 87); + trace_triggers_out : out std_ulogic_vector(0 to 11); + + fiss_dbg_data : in std_ulogic_vector(0 to 87); + fdep_dbg_data : in std_ulogic_vector(0 to 87); + ib_dbg_data : in std_ulogic_vector(0 to 63); + bp_dbg_data0 : in std_ulogic_vector(0 to 87); + bp_dbg_data1 : in std_ulogic_vector(0 to 87); + fu_iss_dbg_data : in std_ulogic_vector(0 to 23); + axu_dbg_data_t0 : in std_ulogic_vector(0 to 37); + axu_dbg_data_t1 : in std_ulogic_vector(0 to 37); + axu_dbg_data_t2 : in std_ulogic_vector(0 to 37); + axu_dbg_data_t3 : in std_ulogic_vector(0 to 37); + + + --perf + ic_perf_event_t0 : in std_ulogic_vector(0 to 6); + ic_perf_event_t1 : in std_ulogic_vector(0 to 6); + ic_perf_event_t2 : in std_ulogic_vector(0 to 6); + ic_perf_event_t3 : in std_ulogic_vector(0 to 6); + ic_perf_event : in std_ulogic_vector(0 to 1); + ib_perf_event_t0 : in std_ulogic_vector(0 to 1); + ib_perf_event_t1 : in std_ulogic_vector(0 to 1); + ib_perf_event_t2 : in std_ulogic_vector(0 to 1); + ib_perf_event_t3 : in std_ulogic_vector(0 to 1); + fdep_perf_event_t0 : in std_ulogic_vector(0 to 11); + fdep_perf_event_t1 : in std_ulogic_vector(0 to 11); + fdep_perf_event_t2 : in std_ulogic_vector(0 to 11); + fdep_perf_event_t3 : in std_ulogic_vector(0 to 11); + fiss_perf_event_t0 : in std_ulogic_vector(0 to 7); + fiss_perf_event_t1 : in std_ulogic_vector(0 to 7); + fiss_perf_event_t2 : in std_ulogic_vector(0 to 7); + fiss_perf_event_t3 : in std_ulogic_vector(0 to 7); + pc_iu_event_mux_ctrls : in std_ulogic_vector(0 to 47); + pc_iu_event_count_mode : in std_ulogic_vector(0 to 2); + pc_iu_event_bus_enable : in std_ulogic; + iu_pc_event_data : out std_ulogic_vector(0 to 7) +); + +-- synopsys translate_off + + +-- synopsys translate_on + +end iuq_misc; +---- +architecture iuq_misc of iuq_misc is + +signal iuq_pv_gptr_scan_in : std_ulogic; +signal iuq_pv_gptr_scan_out : std_ulogic; + +signal iuq_bh_scan_in : std_ulogic; +signal iuq_bh_scan_out : std_ulogic; +signal iuq_rm_scan_in : std_ulogic; +signal iuq_rm_scan_out : std_ulogic; +signal iuq_sp_scan_in : std_ulogic; +signal iuq_sp_scan_out : std_ulogic; +signal iuq_pf_scan_in : std_ulogic; +signal iuq_pf_scan_out : std_ulogic; +signal iuq_db_scan_in : std_ulogic; +signal iuq_db_scan_out : std_ulogic; + +signal iuq_bh_repr_scan_in : std_ulogic; +signal iuq_bh_repr_scan_out : std_ulogic; +signal iuq_bh_time_scan_in : std_ulogic; +signal iuq_bh_time_scan_out : std_ulogic; +signal iuq_bh_abst_scan_in : std_ulogic; +signal iuq_bh_abst_scan_out : std_ulogic; + +signal iuq_sp_ccfg_scan_in : std_ulogic; +signal iuq_sp_ccfg_scan_out : std_ulogic; +signal iuq_sp_bcfg_scan_in : std_ulogic; +signal iuq_sp_bcfg_scan_out : std_ulogic; +signal iuq_sp_dcfg_scan_in : std_ulogic; +signal iuq_sp_dcfg_scan_out : std_ulogic; + + +signal int_pc_iu_sg_2 : std_ulogic_vector(0 to 3); +signal int_pc_iu_func_sl_thold_2 : std_ulogic_vector(0 to 3); +signal int_pc_iu_func_slp_sl_thold_2 : std_ulogic; +signal int_pc_iu_time_sl_thold_2 : std_ulogic; +signal int_pc_iu_repr_sl_thold_2 : std_ulogic; +signal int_pc_iu_abst_sl_thold_2 : std_ulogic; +signal int_pc_iu_cfg_sl_thold_2 : std_ulogic; +signal int_pc_iu_cfg_slp_sl_thold_2 : std_ulogic; +signal int_pc_iu_regf_slp_sl_thold_2 : std_ulogic; +signal int_pc_iu_ary_nsl_thold_2 : std_ulogic; +signal int_pc_iu_bolt_sl_thold_2 : std_ulogic; +signal pc_iu_bo_enable_2 : std_ulogic; +signal int_clkoff_b : std_ulogic_vector(0 to 2); +signal int_act_dis : std_ulogic_vector(0 to 2); +signal int_d_mode : std_ulogic_vector(0 to 2); +signal int_delay_lclkr : std_ulogic_vector(0 to 14); +signal int_mpw1_b : std_ulogic_vector(0 to 14); +signal int_mpw2_b : std_ulogic_vector(0 to 2); +signal bht_g8t_clkoff_b : std_ulogic; +signal bht_g8t_d_mode : std_ulogic; +signal bht_g8t_delay_lclkr : std_ulogic_vector(0 to 4); +signal bht_g8t_mpw1_b : std_ulogic_vector(0 to 4); +signal bht_g8t_mpw2_b : std_ulogic; + +signal bht_dbg_data : std_ulogic_vector(0 to 31); +signal data_out0_int : std_ulogic_vector(0 to 1); +signal data_out1_int : std_ulogic_vector(0 to 1); +signal data_out2_int : std_ulogic_vector(0 to 1); +signal data_out3_int : std_ulogic_vector(0 to 1); + + +-- synopsys translate_off +-- synopsys translate_on + + +begin + + + +pc_iu_sg_2 <= int_pc_iu_sg_2; +pc_iu_func_sl_thold_2 <= int_pc_iu_func_sl_thold_2; +pc_iu_func_slp_sl_thold_2<= int_pc_iu_func_slp_sl_thold_2; +pc_iu_time_sl_thold_2 <= int_pc_iu_time_sl_thold_2; +pc_iu_repr_sl_thold_2 <= int_pc_iu_repr_sl_thold_2; +pc_iu_abst_sl_thold_2 <= int_pc_iu_abst_sl_thold_2; +pc_iu_cfg_slp_sl_thold_2 <= int_pc_iu_cfg_slp_sl_thold_2; +pc_iu_regf_slp_sl_thold_2 <= int_pc_iu_regf_slp_sl_thold_2; +pc_iu_ary_nsl_thold_2 <= int_pc_iu_ary_nsl_thold_2; +pc_iu_bolt_sl_thold_2 <= int_pc_iu_bolt_sl_thold_2; +clkoff_b <= int_clkoff_b; +delay_lclkr(1 to 14) <= int_delay_lclkr(1 to 14); +mpw1_b(1 to 14) <= int_mpw1_b(1 to 14); + + + +iuq_perv0 : entity work.iuq_perv +generic map (expand_type => expand_type) +port map ( + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_iu_sg_3 => pc_iu_sg_3, + pc_iu_func_sl_thold_3 => pc_iu_func_sl_thold_3, + pc_iu_func_slp_sl_thold_3 => pc_iu_func_slp_sl_thold_3, + pc_iu_gptr_sl_thold_3 => pc_iu_gptr_sl_thold_3, + pc_iu_time_sl_thold_3 => pc_iu_time_sl_thold_3, + pc_iu_repr_sl_thold_3 => pc_iu_repr_sl_thold_3, + pc_iu_abst_sl_thold_3 => pc_iu_abst_sl_thold_3, + pc_iu_abst_slp_sl_thold_3 => pc_iu_abst_slp_sl_thold_3, + pc_iu_cfg_sl_thold_3 => pc_iu_cfg_sl_thold_3, + pc_iu_cfg_slp_sl_thold_3 => pc_iu_cfg_slp_sl_thold_3, + pc_iu_regf_slp_sl_thold_3 => pc_iu_regf_slp_sl_thold_3, + pc_iu_ary_nsl_thold_3 => pc_iu_ary_nsl_thold_3, + pc_iu_ary_slp_nsl_thold_3 => pc_iu_ary_slp_nsl_thold_3, + pc_iu_func_slp_nsl_thold_3 => pc_iu_func_slp_nsl_thold_3, + pc_iu_bolt_sl_thold_3 => pc_iu_bolt_sl_thold_3, + pc_iu_bo_enable_3 => pc_iu_bo_enable_3, + pc_iu_fce_3 => pc_iu_fce_3, + tc_ac_ccflush_dc => tc_ac_ccflush_dc, + scan_diag_dc => scan_diag_dc, + pc_iu_sg_2 => int_pc_iu_sg_2, + pc_iu_func_sl_thold_2 => int_pc_iu_func_sl_thold_2, + pc_iu_func_slp_sl_thold_2=> int_pc_iu_func_slp_sl_thold_2, + pc_iu_time_sl_thold_2 => int_pc_iu_time_sl_thold_2, + pc_iu_repr_sl_thold_2 => int_pc_iu_repr_sl_thold_2, + pc_iu_abst_sl_thold_2 => int_pc_iu_abst_sl_thold_2, + pc_iu_abst_slp_sl_thold_2 => pc_iu_abst_slp_sl_thold_2, + pc_iu_cfg_sl_thold_2 => int_pc_iu_cfg_sl_thold_2, + pc_iu_cfg_slp_sl_thold_2 => int_pc_iu_cfg_slp_sl_thold_2, + pc_iu_regf_slp_sl_thold_2 => int_pc_iu_regf_slp_sl_thold_2, + pc_iu_ary_nsl_thold_2 => int_pc_iu_ary_nsl_thold_2, + pc_iu_ary_slp_nsl_thold_2 => pc_iu_ary_slp_nsl_thold_2, + pc_iu_func_slp_nsl_thold_2 => pc_iu_func_slp_nsl_thold_2, + pc_iu_bolt_sl_thold_2 => int_pc_iu_bolt_sl_thold_2, + pc_iu_bo_enable_2 => pc_iu_bo_enable_2, + pc_iu_fce_2 => pc_iu_fce_2, + clkoff_b => int_clkoff_b, + act_dis => int_act_dis, + d_mode => int_d_mode, + delay_lclkr => int_delay_lclkr, + mpw1_b => int_mpw1_b, + mpw2_b => int_mpw2_b, + bht_g8t_clkoff_b => bht_g8t_clkoff_b, + bht_g8t_d_mode => bht_g8t_d_mode, + bht_g8t_delay_lclkr => bht_g8t_delay_lclkr, + bht_g8t_mpw1_b => bht_g8t_mpw1_b, + bht_g8t_mpw2_b => bht_g8t_mpw2_b, + g8t_clkoff_b => g8t_clkoff_b, + g8t_d_mode => g8t_d_mode, + g8t_delay_lclkr => g8t_delay_lclkr, + g8t_mpw1_b => g8t_mpw1_b, + g8t_mpw2_b => g8t_mpw2_b, + g6t_clkoff_b => g6t_clkoff_b, + g6t_d_mode => g6t_d_mode, + g6t_delay_lclkr => g6t_delay_lclkr, + g6t_mpw1_b => g6t_mpw1_b, + g6t_mpw2_b => g6t_mpw2_b, + cam_clkoff_b => cam_clkoff_b, + cam_d_mode => cam_d_mode, + cam_delay_lclkr => cam_delay_lclkr, + cam_mpw1_b => cam_mpw1_b, + cam_mpw2_b => cam_mpw2_b, + gptr_scan_in => iuq_pv_gptr_scan_in, + gptr_scan_out => iuq_pv_gptr_scan_out); + + +bht: entity tri.tri_bht + generic map ( expand_type => expand_type ) + port map( + gnd => gnd, + vdd => vdd, + vcs => vcs, + nclk => nclk, + pc_iu_func_sl_thold_2 => int_pc_iu_func_sl_thold_2(0), + pc_iu_sg_2 => int_pc_iu_sg_2(3), + pc_iu_time_sl_thold_2 => int_pc_iu_time_sl_thold_2, + pc_iu_abst_sl_thold_2 => int_pc_iu_abst_sl_thold_2, + pc_iu_ary_nsl_thold_2 => int_pc_iu_ary_nsl_thold_2, + pc_iu_repr_sl_thold_2 => int_pc_iu_repr_sl_thold_2, + pc_iu_bolt_sl_thold_2 => int_pc_iu_bolt_sl_thold_2, + tc_ac_ccflush_dc => tc_ac_ccflush_dc, + tc_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b, + clkoff_b => int_clkoff_b(0), + scan_diag_dc => scan_diag_dc, + act_dis => int_act_dis(0), + d_mode => int_d_mode(0), + delay_lclkr => int_delay_lclkr(0), + mpw1_b => int_mpw1_b(0), + mpw2_b => int_mpw2_b(0), + g8t_clkoff_b => bht_g8t_clkoff_b, + g8t_d_mode => bht_g8t_d_mode, + g8t_delay_lclkr => bht_g8t_delay_lclkr, + g8t_mpw1_b => bht_g8t_mpw1_b, + g8t_mpw2_b => bht_g8t_mpw2_b, + func_scan_in => iuq_bh_scan_in, + time_scan_in => iuq_bh_time_scan_in, + abst_scan_in => iuq_bh_abst_scan_in, + repr_scan_in => iuq_bh_repr_scan_in, + func_scan_out => iuq_bh_scan_out, + time_scan_out => iuq_bh_time_scan_out, + abst_scan_out => iuq_bh_abst_scan_out, + repr_scan_out => iuq_bh_repr_scan_out, + pc_iu_abist_di_0 => pc_iu_abist_di_0, + pc_iu_abist_g8t_bw_1 => pc_iu_abist_g8t_bw_1, + pc_iu_abist_g8t_bw_0 => pc_iu_abist_g8t_bw_0, + pc_iu_abist_waddr_0 => pc_iu_abist_waddr_0(3 to 9), + pc_iu_abist_g8t_wenb => pc_iu_abist_g8t_wenb, + pc_iu_abist_raddr_0 => pc_iu_abist_raddr_0(3 to 9), + pc_iu_abist_g8t1p_renb_0 => pc_iu_abist_g8t1p_renb_0, + an_ac_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc, + pc_iu_abist_ena_dc => pc_iu_abist_ena_dc, + pc_iu_abist_wl128_comp_ena => pc_iu_abist_wl128_comp_ena, + pc_iu_abist_raw_dc_b => pc_iu_abist_raw_dc_b, + pc_iu_abist_g8t_dcomp => pc_iu_abist_g8t_dcomp, + pc_iu_bo_enable_2 => pc_iu_bo_enable_2, + pc_iu_bo_reset => pc_iu_bo_reset, + pc_iu_bo_unload => pc_iu_bo_unload, + pc_iu_bo_repair => pc_iu_bo_repair, + pc_iu_bo_shdata => pc_iu_bo_shdata, + pc_iu_bo_select => pc_iu_bo_select, + iu_pc_bo_fail => iu_pc_bo_fail, + iu_pc_bo_diagout => iu_pc_bo_diagout, + r_act => r_act, + w_act => w_act, + r_addr => r_addr, + w_addr => w_addr, + data_in => data_in, + data_out0 => data_out0_int, + data_out1 => data_out1_int, + data_out2 => data_out2_int, + data_out3 => data_out3_int +); + +data_out0 <= data_out0_int; +data_out1 <= data_out1_int; +data_out2 <= data_out2_int; +data_out3 <= data_out3_int; + +iuq_ram0 : entity work.iuq_ram +generic map ( expand_type => expand_type ) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_iu_func_sl_thold_2 => int_pc_iu_func_sl_thold_2(0), + pc_iu_sg_2 => int_pc_iu_sg_2(3), + clkoff_b => int_clkoff_b(0), + act_dis => int_act_dis(0), + tc_ac_ccflush_dc => tc_ac_ccflush_dc, + d_mode => int_d_mode(0), + delay_lclkr => int_delay_lclkr(0), + mpw1_b => int_mpw1_b(0), + mpw2_b => int_mpw2_b(0), + scan_in => iuq_rm_scan_in, --siv(3), + scan_out => iuq_rm_scan_out, --sov(3), + pc_iu_ram_instr => pc_iu_ram_instr, + pc_iu_ram_instr_ext => pc_iu_ram_instr_ext, + pc_iu_ram_force_cmplt => pc_iu_ram_force_cmplt, + xu_iu_ram_issue => xu_iu_ram_issue, + rm_ib_iu4_val => rm_ib_iu4_val, + rm_ib_iu4_force_ram => rm_ib_iu4_force_ram, + rm_ib_iu4_instr => rm_ib_iu4_instr +); + +iuq_spr : entity work.iuq_spr +generic map(regmode => regmode, + a2mode => a2mode, + expand_type => expand_type) +port map( + slowspr_val_in => slowspr_val_in, + slowspr_rw_in => slowspr_rw_in, + slowspr_etid_in => slowspr_etid_in, + slowspr_addr_in => slowspr_addr_in, + slowspr_data_in => slowspr_data_in, + slowspr_done_in => slowspr_done_in, + slowspr_val_out => slowspr_val_out, + slowspr_rw_out => slowspr_rw_out, + slowspr_etid_out => slowspr_etid_out, + slowspr_addr_out => slowspr_addr_out, + slowspr_data_out => slowspr_data_out, + slowspr_done_out => slowspr_done_out, + spr_ic_idir_read => spr_ic_idir_read, + spr_ic_idir_way => spr_ic_idir_way, + spr_ic_idir_row => spr_ic_idir_row, + ic_spr_idir_done => ic_spr_idir_done, + ic_spr_idir_lru => ic_spr_idir_lru, + ic_spr_idir_parity => ic_spr_idir_parity, + ic_spr_idir_endian => ic_spr_idir_endian, + ic_spr_idir_valid => ic_spr_idir_valid, + ic_spr_idir_tag => ic_spr_idir_tag, + spr_ic_icbi_ack_en => spr_ic_icbi_ack_en, + spr_ic_cls => spr_ic_cls, + spr_ic_clockgate_dis => spr_ic_clockgate_dis, + spr_ic_bp_config => spr_ic_bp_config, + spr_bp_config => spr_bp_config, + spr_bp_gshare_mask => spr_bp_gshare_mask, + spr_issue_high_mask => spr_issue_high_mask, + spr_issue_med_mask => spr_issue_med_mask, + spr_fiss_count0_max => spr_fiss_count0_max, + spr_fiss_count1_max => spr_fiss_count1_max, + spr_fiss_count2_max => spr_fiss_count2_max, + spr_fiss_count3_max => spr_fiss_count3_max, + spr_ic_pri_rand => spr_ic_pri_rand, + spr_ic_pri_rand_always => spr_ic_pri_rand_always, + spr_ic_pri_rand_flush => spr_ic_pri_rand_flush, + spr_fiss_pri_rand => spr_fiss_pri_rand, + spr_fiss_pri_rand_always => spr_fiss_pri_rand_always, + spr_fiss_pri_rand_flush => spr_fiss_pri_rand_flush, + spr_dec_mask => spr_dec_mask, + spr_dec_match => spr_dec_match, + spr_fdep_ll_hold => spr_fdep_ll_hold, + xu_iu_run_thread => xu_iu_run_thread, + iu_au_config_iucr_t0 => iu_au_config_iucr_t0, + iu_au_config_iucr_t1 => iu_au_config_iucr_t1, + iu_au_config_iucr_t2 => iu_au_config_iucr_t2, + iu_au_config_iucr_t3 => iu_au_config_iucr_t3, + xu_iu_ex6_pri => xu_iu_ex6_pri, + xu_iu_ex6_pri_val => xu_iu_ex6_pri_val, + xu_iu_raise_iss_pri => xu_iu_raise_iss_pri, + xu_iu_msr_gs => xu_iu_msr_gs, + xu_iu_msr_pr => xu_iu_msr_pr, + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_iu_sg_2 => int_pc_iu_sg_2(3), + pc_iu_func_sl_thold_2 => int_pc_iu_func_sl_thold_2(0), + pc_iu_cfg_sl_thold_2 => int_pc_iu_cfg_sl_thold_2, + clkoff_b => int_clkoff_b(0), + act_dis => int_act_dis(0), + tc_ac_ccflush_dc => tc_ac_ccflush_dc, + d_mode => int_d_mode(0), + delay_lclkr => int_delay_lclkr(0), + mpw1_b => int_mpw1_b(0), + mpw2_b => int_mpw2_b(0), + ccfg_scan_in => iuq_sp_ccfg_scan_in, + ccfg_scan_out => iuq_sp_ccfg_scan_out, + bcfg_scan_in => iuq_sp_bcfg_scan_in, + bcfg_scan_out => iuq_sp_bcfg_scan_out, + dcfg_scan_in => iuq_sp_dcfg_scan_in, + dcfg_scan_out => iuq_sp_dcfg_scan_out, + scan_in => iuq_sp_scan_in, --siv(10), + scan_out => iuq_sp_scan_out --sov(10) +); + +iuq_perf0 : entity work.iuq_perf +generic map(expand_type => expand_type) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_iu_func_sl_thold_2 => int_pc_iu_func_sl_thold_2(0), + pc_iu_sg_2 => int_pc_iu_sg_2(3), + clkoff_b => int_clkoff_b(0), + act_dis => int_act_dis(0), + tc_ac_ccflush_dc => tc_ac_ccflush_dc, + d_mode => int_d_mode(0), + delay_lclkr => int_delay_lclkr(0), + mpw1_b => int_mpw1_b(0), + mpw2_b => int_mpw2_b(0), + scan_in => iuq_pf_scan_in, + scan_out => iuq_pf_scan_out, + + xu_iu_msr_gs => xu_iu_msr_gs, + xu_iu_msr_pr => xu_iu_msr_pr, + + ic_perf_event_t0 => ic_perf_event_t0, + ic_perf_event_t1 => ic_perf_event_t1, + ic_perf_event_t2 => ic_perf_event_t2, + ic_perf_event_t3 => ic_perf_event_t3, + ic_perf_event => ic_perf_event, + + ib_perf_event_t0 => ib_perf_event_t0, + ib_perf_event_t1 => ib_perf_event_t1, + ib_perf_event_t2 => ib_perf_event_t2, + ib_perf_event_t3 => ib_perf_event_t3, + + fdep_perf_event_t0 => fdep_perf_event_t0, + fdep_perf_event_t1 => fdep_perf_event_t1, + fdep_perf_event_t2 => fdep_perf_event_t2, + fdep_perf_event_t3 => fdep_perf_event_t3, + + fiss_perf_event_t0 => fiss_perf_event_t0, + fiss_perf_event_t1 => fiss_perf_event_t1, + fiss_perf_event_t2 => fiss_perf_event_t2, + fiss_perf_event_t3 => fiss_perf_event_t3, + + pc_iu_event_mux_ctrls => pc_iu_event_mux_ctrls, + pc_iu_event_count_mode => pc_iu_event_count_mode, + pc_iu_event_bus_enable => pc_iu_event_bus_enable, + + iu_pc_event_data => iu_pc_event_data +); + +bht_dbg_data(0 to 7) <= r_addr(0 to 7); +bht_dbg_data(8 to 15) <= data_out0_int(0 to 1) & data_out1_int(0 to 1) & data_out2_int(0 to 1) & data_out3_int(0 to 1); +bht_dbg_data(16 to 23) <= w_addr(0 to 7); +bht_dbg_data(24 to 25) <= data_in(0 to 1); +bht_dbg_data(26 to 27) <= '0' & r_act; +bht_dbg_data(28 to 31) <= w_act(0 to 3); + + +iuq_dbg0 : entity work.iuq_dbg +generic map(expand_type => expand_type) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_iu_func_slp_sl_thold_2 => int_pc_iu_func_slp_sl_thold_2, + pc_iu_sg_2 => int_pc_iu_sg_2(3), + clkoff_b => int_clkoff_b(0), + act_dis => int_act_dis(0), + tc_ac_ccflush_dc => tc_ac_ccflush_dc, + d_mode => int_d_mode(0), + delay_lclkr => int_delay_lclkr(0), + mpw1_b => int_mpw1_b(0), + mpw2_b => int_mpw2_b(0), + scan_in => iuq_db_scan_in, + scan_out => iuq_db_scan_out, + fiss_dbg_data => fiss_dbg_data, + fdep_dbg_data => fdep_dbg_data, + ib_dbg_data => ib_dbg_data, + bp_dbg_data0 => bp_dbg_data0, + bp_dbg_data1 => bp_dbg_data1, + fu_iss_dbg_data => fu_iss_dbg_data, + axu_dbg_data_t0 => axu_dbg_data_t0, + axu_dbg_data_t1 => axu_dbg_data_t1, + axu_dbg_data_t2 => axu_dbg_data_t2, + axu_dbg_data_t3 => axu_dbg_data_t3, + bht_dbg_data => bht_dbg_data, + pc_iu_trace_bus_enable => pc_iu_trace_bus_enable, + pc_iu_debug_mux_ctrls => pc_iu_debug_mux_ctrls, + debug_data_in => debug_data_in, + trace_triggers_in => trace_triggers_in, + debug_data_out => debug_data_out, + trace_triggers_out => trace_triggers_out +); + + + + +------------------------------------------------- +-- scan +------------------------------------------------- + +iuq_pf_scan_in <= func_scan_in(0); +iuq_sp_scan_in <= iuq_pf_scan_out; +iuq_bh_scan_in <= iuq_sp_scan_out; +func_scan_out(0) <= iuq_bh_scan_out and an_ac_scan_dis_dc_b; + +iuq_db_scan_in <= func_scan_in(1); +iuq_rm_scan_in <= iuq_db_scan_out; +func_scan_out(1) <= iuq_rm_scan_out and an_ac_scan_dis_dc_b; + +iuq_bh_time_scan_in <= time_scan_in; +time_scan_out <= iuq_bh_time_scan_out and an_ac_scan_dis_dc_b; + +iuq_sp_ccfg_scan_in <= ccfg_scan_in; +iuq_sp_bcfg_scan_in <= bcfg_scan_in; +iuq_sp_dcfg_scan_in <= dcfg_scan_in; +iuq_pv_gptr_scan_in <= gptr_scan_in; +iuq_bh_abst_scan_in <= abst_scan_in; +iuq_bh_repr_scan_in <= repr_scan_in; + +ccfg_scan_out <= iuq_sp_ccfg_scan_out and an_ac_scan_dis_dc_b; +bcfg_scan_out <= iuq_sp_bcfg_scan_out and an_ac_scan_dis_dc_b; +dcfg_scan_out <= iuq_sp_dcfg_scan_out and an_ac_scan_dis_dc_b; +gptr_scan_out <= iuq_pv_gptr_scan_out and an_ac_scan_dis_dc_b; +abst_scan_out <= iuq_bh_abst_scan_out and an_ac_scan_dis_dc_b; +repr_scan_out <= iuq_bh_repr_scan_out and an_ac_scan_dis_dc_b; + + + +end iuq_misc; diff --git a/rel/src/vhdl/work/iuq_perf.vhdl b/rel/src/vhdl/work/iuq_perf.vhdl new file mode 100644 index 0000000..a9e8d7b --- /dev/null +++ b/rel/src/vhdl/work/iuq_perf.vhdl @@ -0,0 +1,420 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +--******************************************************************** +--* +--* TITLE: Performance event mux +--* +--* NAME: iuq_perf.vhdl +--* +--********************************************************************* + + +library ieee; +use ieee.std_logic_1164.all; + +library ibm,clib; +use ibm.std_ulogic_unsigned.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; + +library support; +use support.power_logic_pkg.all; + +library tri; +use tri.tri_latches_pkg.all; + +library work; +use work.iuq_pkg.all; + +entity iuq_perf is +generic(expand_type : integer := 2 ); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + pc_iu_func_sl_thold_2 : in std_ulogic; + pc_iu_sg_2 : in std_ulogic; + clkoff_b : in std_ulogic; + act_dis : in std_ulogic; + tc_ac_ccflush_dc : in std_ulogic; + d_mode : in std_ulogic; + delay_lclkr : in std_ulogic; + mpw1_b : in std_ulogic; + mpw2_b : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + xu_iu_msr_gs : in std_ulogic_vector(0 to 3); + xu_iu_msr_pr : in std_ulogic_vector(0 to 3); + + ic_perf_event_t0 : in std_ulogic_vector(0 to 6); + ic_perf_event_t1 : in std_ulogic_vector(0 to 6); + ic_perf_event_t2 : in std_ulogic_vector(0 to 6); + ic_perf_event_t3 : in std_ulogic_vector(0 to 6); + ic_perf_event : in std_ulogic_vector(0 to 1); + + ib_perf_event_t0 : in std_ulogic_vector(0 to 1); + ib_perf_event_t1 : in std_ulogic_vector(0 to 1); + ib_perf_event_t2 : in std_ulogic_vector(0 to 1); + ib_perf_event_t3 : in std_ulogic_vector(0 to 1); + + fdep_perf_event_t0 : in std_ulogic_vector(0 to 11); + fdep_perf_event_t1 : in std_ulogic_vector(0 to 11); + fdep_perf_event_t2 : in std_ulogic_vector(0 to 11); + fdep_perf_event_t3 : in std_ulogic_vector(0 to 11); + + fiss_perf_event_t0 : in std_ulogic_vector(0 to 7); + fiss_perf_event_t1 : in std_ulogic_vector(0 to 7); + fiss_perf_event_t2 : in std_ulogic_vector(0 to 7); + fiss_perf_event_t3 : in std_ulogic_vector(0 to 7); + + pc_iu_event_mux_ctrls : in std_ulogic_vector(0 to 47); + pc_iu_event_count_mode : in std_ulogic_vector(0 to 2); + pc_iu_event_bus_enable : in std_ulogic; + + iu_pc_event_data : out std_ulogic_vector(0 to 7) + +); + -- synopsys translate_off + + + -- synopsys translate_on +end iuq_perf; + + +architecture iuq_perf of iuq_perf is + +constant event_data_offset : natural := 0; +constant event_count_mode_offset: natural := event_data_offset + 8; +constant xu_iu_msr_gs_offset : natural := event_count_mode_offset + 3; +constant xu_iu_msr_pr_offset : natural := xu_iu_msr_gs_offset + 4; +constant event_bus_enable_offset: natural := xu_iu_msr_pr_offset + 4; +constant event_mux_ctrls_offset : natural := event_bus_enable_offset + 1; +constant scan_right : natural := event_mux_ctrls_offset + 48-1; + +signal event_data_d : std_ulogic_vector(0 to 7); +signal event_data_q : std_ulogic_vector(0 to 7); + +signal t0_events : std_ulogic_vector(0 to 31); +signal t1_events : std_ulogic_vector(0 to 31); +signal t2_events : std_ulogic_vector(0 to 31); +signal t3_events : std_ulogic_vector(0 to 31); + +signal xu_iu_msr_gs_d : std_ulogic_vector(0 to 3); +signal xu_iu_msr_gs_q : std_ulogic_vector(0 to 3); +signal xu_iu_msr_pr_d : std_ulogic_vector(0 to 3); +signal xu_iu_msr_pr_q : std_ulogic_vector(0 to 3); +signal event_count_mode_d : std_ulogic_vector(0 to 2); +signal event_count_mode_q : std_ulogic_vector(0 to 2); + +signal event_en : std_ulogic_vector(0 to 3); + +signal siv : std_ulogic_vector(0 to scan_right); +signal sov : std_ulogic_vector(0 to scan_right); + +signal tiup : std_ulogic; + +signal pc_iu_func_sl_thold_1 : std_ulogic; +signal pc_iu_func_sl_thold_0 : std_ulogic; +signal pc_iu_func_sl_thold_0_b : std_ulogic; +signal pc_iu_sg_1 : std_ulogic; +signal pc_iu_sg_0 : std_ulogic; +signal forcee : std_ulogic; + +signal event_bus_enable_d : std_ulogic; +signal event_bus_enable_q : std_ulogic; +signal event_mux_ctrls_d : std_ulogic_vector(0 to 47); +signal event_mux_ctrls_q : std_ulogic_vector(0 to 47); + +begin + +----------------------------------------------------------------------- +-- Logic +----------------------------------------------------------------------- + +tiup <= '1'; + +---------------------------------------------------- +-- t* event list +---------------------------------------------------- +-- 0 IL1 miss cycles +-- 1 IL1 reloads dropped +-- 2 reload collisions +-- 3 iu0 redirect +-- 4 ierat miss +-- 5 icache fetch +-- 6 instructions fetched +-- 7 reserved +-- 8 l2 back invalidates icache +-- 9 l2 back invalidates icache hits +-- 10 ibuff empty +-- 11 ibuff flush +-- 12 is1 stall +-- 13 is2 stall +-- 14 barrier stall +-- 15 slowspr stall +----- +-- 16 raw dep hit +-- 17 waw dep hit +-- 18 sync dep hit +-- 19 spr dep hit +-- 20 axu dep hit +-- 21 fxu dep hit +-- 22 axu/fxu dep hit +-- 23 reserved +-- 24 2 instr issue +-- 25 axu priority loss +-- 26 fxu priority loss +-- 27 axu issue +-- 28 fxu issue +-- 29 total issue +-- 30 instruction match issue +-- 31 reserved +---------------------------------------------------- + +xu_iu_msr_gs_d <= xu_iu_msr_gs; +xu_iu_msr_pr_d <= xu_iu_msr_pr; +event_count_mode_d <= pc_iu_event_count_mode; + + +event_en(0 to 3) <= gate( xu_iu_msr_pr_q(0 to 3) , event_count_mode_q(0)) or -- User + gate(not xu_iu_msr_pr_q(0 to 3) and xu_iu_msr_gs_q(0 to 3), event_count_mode_q(1)) or -- Guest Supervisor + gate(not xu_iu_msr_pr_q(0 to 3) and not xu_iu_msr_gs_q(0 to 3), event_count_mode_q(2)); -- Hypervisor + + +t0_events(0 to 31) <= gate( + ic_perf_event_t0(0 to 6) & '0' & + ic_perf_event(0 to 1) & + ib_perf_event_t0(0 to 1) & + fdep_perf_event_t0(0 to 11) & + fiss_perf_event_t0(0 to 7), + event_en(0)); + +t1_events(0 to 31) <= gate( + ic_perf_event_t1(0 to 6) & '0' & + ic_perf_event(0 to 1) & + ib_perf_event_t1(0 to 1) & + fdep_perf_event_t1(0 to 11) & + fiss_perf_event_t1(0 to 7), + event_en(1)); + +t2_events(0 to 31) <= gate( + ic_perf_event_t2(0 to 6) & '0' & + ic_perf_event(0 to 1) & + ib_perf_event_t2(0 to 1) & + fdep_perf_event_t2(0 to 11) & + fiss_perf_event_t2(0 to 7), + event_en(2)); + +t3_events(0 to 31) <= gate( + ic_perf_event_t3(0 to 6) & '0' & + ic_perf_event(0 to 1) & + ib_perf_event_t3(0 to 1) & + fdep_perf_event_t3(0 to 11) & + fiss_perf_event_t3(0 to 7), + event_en(3)); + + +event_mux1: entity clib.c_event_mux + generic map ( events_in => 128 ) + port map(vd => vdd, + gd => gnd, + + t0_events => t0_events(0 to 31), + t1_events => t1_events(0 to 31), + t2_events => t2_events(0 to 31), + t3_events => t3_events(0 to 31), + + select_bits => event_mux_ctrls_q(0 to 47), + event_bits => event_data_d(0 to 7) +); + + +iu_pc_event_data <= event_data_q(0 to 7); + + +----------------------------------------------------------------------- +-- Latches +----------------------------------------------------------------------- +event_bus_enable_d <= pc_iu_event_bus_enable; +event_mux_ctrls_d <= pc_iu_event_mux_ctrls; + +event_enable_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(event_bus_enable_offset), + scout => sov(event_bus_enable_offset), + din => event_bus_enable_d, + dout => event_bus_enable_q); + +event_mux_ctrls_reg: tri_rlmreg_p + generic map (width => event_mux_ctrls_q'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => event_bus_enable_q, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(event_mux_ctrls_offset to event_mux_ctrls_offset + event_mux_ctrls_q'length-1), + scout => sov(event_mux_ctrls_offset to event_mux_ctrls_offset + event_mux_ctrls_q'length-1), + din => event_mux_ctrls_d, + dout => event_mux_ctrls_q); + +event_data_reg: tri_rlmreg_p + generic map (width => event_data_q'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => event_bus_enable_q, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(event_data_offset to event_data_offset + event_data_q'length-1), + scout => sov(event_data_offset to event_data_offset + event_data_q'length-1), + din => event_data_d, + dout => event_data_q); + +event_count_mode_reg: tri_rlmreg_p + generic map (width => event_count_mode_q'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => event_bus_enable_q, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(event_count_mode_offset to event_count_mode_offset + event_count_mode_q'length-1), + scout => sov(event_count_mode_offset to event_count_mode_offset + event_count_mode_q'length-1), + din => event_count_mode_d, + dout => event_count_mode_q); + +xu_iu_msr_gs_reg: tri_rlmreg_p + generic map (width => xu_iu_msr_gs_q'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => event_bus_enable_q, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_iu_msr_gs_offset to xu_iu_msr_gs_offset + xu_iu_msr_gs_q'length-1), + scout => sov(xu_iu_msr_gs_offset to xu_iu_msr_gs_offset + xu_iu_msr_gs_q'length-1), + din => xu_iu_msr_gs_d, + dout => xu_iu_msr_gs_q); + +xu_iu_msr_pr_reg: tri_rlmreg_p + generic map (width => xu_iu_msr_pr_q'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => event_bus_enable_q, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_iu_msr_pr_offset to xu_iu_msr_pr_offset + xu_iu_msr_pr_q'length-1), + scout => sov(xu_iu_msr_pr_offset to xu_iu_msr_pr_offset + xu_iu_msr_pr_q'length-1), + din => xu_iu_msr_pr_d, + dout => xu_iu_msr_pr_q); + + +------------------------------------------------- +-- pervasive +------------------------------------------------- + +perv_2to1_reg: tri_plat + generic map (width => 2, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_iu_func_sl_thold_2, + din(1) => pc_iu_sg_2, + q(0) => pc_iu_func_sl_thold_1, + q(1) => pc_iu_sg_1); + +perv_1to0_reg: tri_plat + generic map (width => 2, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_iu_func_sl_thold_1, + din(1) => pc_iu_sg_1, + q(0) => pc_iu_func_sl_thold_0, + q(1) => pc_iu_sg_0); + +perv_lcbor: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_b, + thold => pc_iu_func_sl_thold_0, + sg => pc_iu_sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => pc_iu_func_sl_thold_0_b); + +----------------------------------------------------------------------- +-- Scan +----------------------------------------------------------------------- +siv(0 to scan_right) <= sov(1 to scan_right) & scan_in; +scan_out <= sov(0); + + +end iuq_perf; diff --git a/rel/src/vhdl/work/iuq_perv.vhdl b/rel/src/vhdl/work/iuq_perv.vhdl new file mode 100644 index 0000000..50a1223 --- /dev/null +++ b/rel/src/vhdl/work/iuq_perv.vhdl @@ -0,0 +1,354 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + + +library ieee; +use ieee.std_logic_1164.all; + +library ibm; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; + +library support; +use support.power_logic_pkg.all; + +library tri; +use tri.tri_latches_pkg.all; + +entity iuq_perv is +generic(expand_type : integer := 2 ); -- 0 = ibm umbra, 1 = xilinx, 2 = ibm mpg +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + pc_iu_sg_3 : in std_ulogic_vector(0 to 3); + pc_iu_func_sl_thold_3 : in std_ulogic_vector(0 to 3); + pc_iu_func_slp_sl_thold_3 : in std_ulogic; + pc_iu_gptr_sl_thold_3 : in std_ulogic; + pc_iu_time_sl_thold_3 : in std_ulogic; + pc_iu_repr_sl_thold_3 : in std_ulogic; + pc_iu_abst_sl_thold_3 : in std_ulogic; + pc_iu_abst_slp_sl_thold_3 : in std_ulogic; + pc_iu_cfg_sl_thold_3 : in std_ulogic; + pc_iu_cfg_slp_sl_thold_3 : in std_ulogic; + pc_iu_regf_slp_sl_thold_3 : in std_ulogic; + pc_iu_ary_nsl_thold_3 : in std_ulogic; + pc_iu_ary_slp_nsl_thold_3 : in std_ulogic; + pc_iu_func_slp_nsl_thold_3 : in std_ulogic; + pc_iu_bolt_sl_thold_3 : in std_ulogic; + pc_iu_bo_enable_3 : in std_ulogic; + pc_iu_fce_3 : in std_ulogic; + tc_ac_ccflush_dc : in std_ulogic; + scan_diag_dc : in std_ulogic; + pc_iu_sg_2 : out std_ulogic_vector(0 to 3); + pc_iu_func_sl_thold_2 : out std_ulogic_vector(0 to 3); + pc_iu_func_slp_sl_thold_2 : out std_ulogic; + pc_iu_time_sl_thold_2 : out std_ulogic; + pc_iu_repr_sl_thold_2 : out std_ulogic; + pc_iu_abst_sl_thold_2 : out std_ulogic; + pc_iu_abst_slp_sl_thold_2 : out std_ulogic; + pc_iu_cfg_sl_thold_2 : out std_ulogic; + pc_iu_cfg_slp_sl_thold_2 : out std_ulogic; + pc_iu_regf_slp_sl_thold_2 : out std_ulogic; + pc_iu_ary_nsl_thold_2 : out std_ulogic; + pc_iu_ary_slp_nsl_thold_2 : out std_ulogic; + pc_iu_func_slp_nsl_thold_2 : out std_ulogic; + pc_iu_bolt_sl_thold_2 : out std_ulogic; + pc_iu_bo_enable_2 : out std_ulogic; + pc_iu_fce_2 : out std_ulogic; + clkoff_b : out std_ulogic_vector(0 to 2); + act_dis : out std_ulogic_vector(0 to 2); + d_mode : out std_ulogic_vector(0 to 2); + delay_lclkr : out std_ulogic_vector(0 to 14); + mpw1_b : out std_ulogic_vector(0 to 14); + mpw2_b : out std_ulogic_vector(0 to 2); + bht_g8t_clkoff_b : out std_ulogic; + bht_g8t_d_mode : out std_ulogic; + bht_g8t_delay_lclkr : out std_ulogic_vector(0 to 4); + bht_g8t_mpw1_b : out std_ulogic_vector(0 to 4); + bht_g8t_mpw2_b : out std_ulogic; + g8t_clkoff_b : out std_ulogic; + g8t_d_mode : out std_ulogic; + g8t_delay_lclkr : out std_ulogic_vector(0 to 4); + g8t_mpw1_b : out std_ulogic_vector(0 to 4); + g8t_mpw2_b : out std_ulogic; + g6t_clkoff_b : out std_ulogic; + g6t_d_mode : out std_ulogic; + g6t_delay_lclkr : out std_ulogic_vector(0 to 3); + g6t_mpw1_b : out std_ulogic_vector(0 to 4); + g6t_mpw2_b : out std_ulogic; + cam_clkoff_b : out std_ulogic; + cam_d_mode : out std_ulogic; + cam_delay_lclkr : out std_ulogic_vector(0 to 4); + cam_mpw1_b : out std_ulogic_vector(0 to 4); + cam_mpw2_b : out std_ulogic; + gptr_scan_in : in std_ulogic; + gptr_scan_out : out std_ulogic +); + +-- synopsys translate_off + + +-- synopsys translate_on + +end iuq_perv; +architecture iuq_perv of iuq_perv is + +signal pc_iu_gptr_sl_thold_2_int : std_ulogic; +signal pc_iu_time_sl_thold_2_int : std_ulogic; +signal pc_iu_sg_2_int : std_ulogic_vector(0 to 3); + +signal pc_iu_gptr_sl_thold_1 : std_ulogic; +signal pc_iu_sg_1 : std_ulogic; +signal pc_iu_gptr_sl_thold_0 : std_ulogic; +signal pc_iu_sg_0 : std_ulogic; + +signal int_g6t_delay_lclkr : std_ulogic_vector(0 to 4); +signal unused : std_ulogic; +-- synopsys translate_off +-- synopsys translate_on + + +signal gptr_siv : std_ulogic_vector(0 to 6); +signal gptr_sov : std_ulogic_vector(0 to 6); + +begin + +perv_3to2_reg: tri_plat + generic map (width => 23, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0 to 3) => pc_iu_func_sl_thold_3(0 to 3), + din(4) => pc_iu_gptr_sl_thold_3, + din(5) => pc_iu_time_sl_thold_3, + din(6) => pc_iu_repr_sl_thold_3, + din(7) => pc_iu_abst_sl_thold_3, + din(8) => pc_iu_ary_nsl_thold_3, + din(9 to 12) => pc_iu_sg_3(0 to 3), + din(13) => pc_iu_fce_3, + din(14) => pc_iu_cfg_slp_sl_thold_3, + din(15) => pc_iu_cfg_sl_thold_3, + din(16) => pc_iu_regf_slp_sl_thold_3, + din(17) => pc_iu_func_slp_sl_thold_3, + din(18) => pc_iu_ary_slp_nsl_thold_3, + din(19) => pc_iu_abst_slp_sl_thold_3, + din(20) => pc_iu_func_slp_nsl_thold_3, + din(21) => pc_iu_bolt_sl_thold_3, + din(22) => pc_iu_bo_enable_3, + q(0 to 3) => pc_iu_func_sl_thold_2(0 to 3), + q(4) => pc_iu_gptr_sl_thold_2_int, + q(5) => pc_iu_time_sl_thold_2_int, + q(6) => pc_iu_repr_sl_thold_2, + q(7) => pc_iu_abst_sl_thold_2, + q(8) => pc_iu_ary_nsl_thold_2, + q(9 to 12) => pc_iu_sg_2_int(0 to 3), + q(13) => pc_iu_fce_2, + q(14) => pc_iu_cfg_slp_sl_thold_2, + q(15) => pc_iu_cfg_sl_thold_2, + q(16) => pc_iu_regf_slp_sl_thold_2, + q(17) => pc_iu_func_slp_sl_thold_2, + q(18) => pc_iu_ary_slp_nsl_thold_2, + q(19) => pc_iu_abst_slp_sl_thold_2, + q(20) => pc_iu_func_slp_nsl_thold_2, + q(21) => pc_iu_bolt_sl_thold_2, + q(22) => pc_iu_bo_enable_2); + +pc_iu_time_sl_thold_2 <= pc_iu_time_sl_thold_2_int; +pc_iu_sg_2 <= pc_iu_sg_2_int; + +perv_2to1_reg: tri_plat + generic map (width => 2, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_iu_gptr_sl_thold_2_int, + din(1) => pc_iu_sg_2_int(0), + q(0) => pc_iu_gptr_sl_thold_1, + q(1) => pc_iu_sg_1); + +perv_1to0_reg: tri_plat + generic map (width => 2, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_iu_gptr_sl_thold_1, + din(1) => pc_iu_sg_1, + q(0) => pc_iu_gptr_sl_thold_0, + q(1) => pc_iu_sg_0); + + +perv_lcbcntl0: tri_lcbcntl_mac + generic map (expand_type => expand_type) + port map ( + vdd => vdd, + gnd => gnd, + sg => pc_iu_sg_0, + nclk => nclk, + scan_in => gptr_siv(0), + scan_diag_dc => scan_diag_dc, + thold => pc_iu_gptr_sl_thold_0, + clkoff_dc_b => clkoff_b(0), + delay_lclkr_dc => delay_lclkr(0 to 4), + act_dis_dc => open, + d_mode_dc => d_mode(0), + mpw1_dc_b => mpw1_b(0 to 4), + mpw2_dc_b => mpw2_b(0), + scan_out => gptr_sov(0)); + +perv_lcbcntl1: tri_lcbcntl_mac + generic map (expand_type => expand_type) + port map ( + vdd => vdd, + gnd => gnd, + sg => pc_iu_sg_0, + nclk => nclk, + scan_in => gptr_siv(1), + scan_diag_dc => scan_diag_dc, + thold => pc_iu_gptr_sl_thold_0, + clkoff_dc_b => clkoff_b(1), + delay_lclkr_dc => delay_lclkr(5 to 9), + act_dis_dc => open, + d_mode_dc => d_mode(1), + mpw1_dc_b => mpw1_b(5 to 9), + mpw2_dc_b => mpw2_b(1), + scan_out => gptr_sov(1)); + + +perv_lcbcntl2: tri_lcbcntl_mac + generic map (expand_type => expand_type) + port map ( + vdd => vdd, + gnd => gnd, + sg => pc_iu_sg_0, + nclk => nclk, + scan_in => gptr_siv(2), + scan_diag_dc => scan_diag_dc, + thold => pc_iu_gptr_sl_thold_0, + clkoff_dc_b => clkoff_b(2), + delay_lclkr_dc => delay_lclkr(10 to 14), + act_dis_dc => open, + d_mode_dc => d_mode(2), + mpw1_dc_b => mpw1_b(10 to 14), + mpw2_dc_b => mpw2_b(2), + scan_out => gptr_sov(2)); + + +perv_lcbcntl_g8t_bht: tri_lcbcntl_array_mac + generic map (expand_type => expand_type) + port map ( + vdd => vdd, + gnd => gnd, + sg => pc_iu_sg_0, + nclk => nclk, + scan_in => gptr_siv(3), + scan_diag_dc => scan_diag_dc, + thold => pc_iu_gptr_sl_thold_0, + clkoff_dc_b => bht_g8t_clkoff_b, + delay_lclkr_dc => bht_g8t_delay_lclkr(0 to 4), + act_dis_dc => open, + d_mode_dc => bht_g8t_d_mode, + mpw1_dc_b => bht_g8t_mpw1_b(0 to 4), + mpw2_dc_b => bht_g8t_mpw2_b, + scan_out => gptr_sov(3)); + +perv_lcbcntl_g8t: tri_lcbcntl_array_mac + generic map (expand_type => expand_type) + port map ( + vdd => vdd, + gnd => gnd, + sg => pc_iu_sg_0, + nclk => nclk, + scan_in => gptr_siv(4), + scan_diag_dc => scan_diag_dc, + thold => pc_iu_gptr_sl_thold_0, + clkoff_dc_b => g8t_clkoff_b, + delay_lclkr_dc => g8t_delay_lclkr(0 to 4), + act_dis_dc => open, + d_mode_dc => g8t_d_mode, + mpw1_dc_b => g8t_mpw1_b(0 to 4), + mpw2_dc_b => g8t_mpw2_b, + scan_out => gptr_sov(4)); + +perv_lcbcntl_g6t: tri_lcbcntl_array_mac + generic map (expand_type => expand_type) + port map ( + vdd => vdd, + gnd => gnd, + sg => pc_iu_sg_0, + nclk => nclk, + scan_in => gptr_siv(5), + scan_diag_dc => scan_diag_dc, + thold => pc_iu_gptr_sl_thold_0, + clkoff_dc_b => g6t_clkoff_b, + delay_lclkr_dc => int_g6t_delay_lclkr, + act_dis_dc => open, + d_mode_dc => g6t_d_mode, + mpw1_dc_b => g6t_mpw1_b(0 to 4), + mpw2_dc_b => g6t_mpw2_b, + scan_out => gptr_sov(5)); + +perv_lcbcntl_cam: tri_lcbcntl_array_mac + generic map (expand_type => expand_type) + port map ( + vdd => vdd, + gnd => gnd, + sg => pc_iu_sg_0, + nclk => nclk, + scan_in => gptr_siv(6), + scan_diag_dc => scan_diag_dc, + thold => pc_iu_gptr_sl_thold_0, + clkoff_dc_b => cam_clkoff_b, + delay_lclkr_dc => cam_delay_lclkr(0 to 4), + act_dis_dc => open, + d_mode_dc => cam_d_mode, + mpw1_dc_b => cam_mpw1_b(0 to 4), + mpw2_dc_b => cam_mpw2_b, + scan_out => gptr_sov(6)); + +g6t_delay_lclkr <= int_g6t_delay_lclkr(0 to 3); +unused <= int_g6t_delay_lclkr(4); + +--never disable act pins, they are used functionally +act_dis(0 to 2) <= "000"; + +----------------------------------------------------------------------- +-- Scan +----------------------------------------------------------------------- + +gptr_siv(0 to 6) <= gptr_sov(1 to 6) & gptr_scan_in; +gptr_scan_out <= gptr_sov(0); + + +end iuq_perv; diff --git a/rel/src/vhdl/work/iuq_pkg.vhdl b/rel/src/vhdl/work/iuq_pkg.vhdl new file mode 100644 index 0000000..d412ea0 --- /dev/null +++ b/rel/src/vhdl/work/iuq_pkg.vhdl @@ -0,0 +1,433 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +library ieee; +use ieee.std_logic_1164.all; + +package iuq_pkg is + subtype EFF_IFAR is std_ulogic_vector( 0 to 61); + subtype REAL_IFAR is std_ulogic_vector(22 to 61); + subtype EFF_DATA_ADD is std_ulogic_vector( 0 to 61); + subtype REAL_DATA_ADD is std_ulogic_vector(18 to 61); + + function ib(x : std_ulogic) return boolean; + + -- all functions assume to logic vector strand direction + function barrel_left(a : std_ulogic_vector; s : std_ulogic_vector) return std_ulogic_vector; + function barrel_right(a : std_ulogic_vector; s : std_ulogic_vector) return std_ulogic_vector; + function pri_enc(a : std_ulogic_vector) return std_ulogic_vector; + function shift_left(a : std_ulogic_vector; s : std_ulogic_vector) return std_ulogic_vector; + function shift_right(a : std_ulogic_vector; s : std_ulogic_vector) return std_ulogic_vector; + function mask_left(a : std_ulogic_vector ) return std_ulogic_vector; + function mask_right(a : std_ulogic_vector ) return std_ulogic_vector; + + function shift_leftx1B(a : std_ulogic_vector; s: std_ulogic_vector) return std_ulogic_vector; + function shift_rightx1B(a : std_ulogic_vector; s: std_ulogic_vector) return std_ulogic_vector; + + procedure zeros(signal x : out std_ulogic); + procedure zeros(signal x : out std_ulogic_vector); + + function encode_4to2( a : std_ulogic_vector(0 to 3) ) return std_ulogic_vector; + function encode_8to3( a : std_ulogic_vector(0 to 7) ) return std_ulogic_vector; + function encode_16to4(a : std_ulogic_vector(0 to 15)) return std_ulogic_vector; + + -- Instruction type definition + type PPC_INSTR is record + vld : std_ulogic; + instr : std_ulogic_vector(0 to 31); + + ta : std_ulogic_vector(0 to 6); + ta_vld : std_ulogic; + ta_typ : std_ulogic_vector(0 to 1); + + s1 : std_ulogic_vector(0 to 6); + s1_vld : std_ulogic; + s1_typ : std_ulogic_vector(0 to 1); + + s2 : std_ulogic_vector(0 to 6); + s2_vld : std_ulogic; + s2_typ : std_ulogic_vector(0 to 1); + + s3 : std_ulogic_vector(0 to 6); + s3_vld : std_ulogic; + s3_typ : std_ulogic_vector(0 to 1); + + isFxuIssue : std_ulogic; + isVsuIssue : std_ulogic; + + --EX2_exit : std_ulogic; + EX4_exit : std_ulogic; + EX7_exit : std_ulogic; + + isLWARX : std_ulogic; + isSTWCX : std_ulogic; + is_vcrs : std_ulogic; + + pred_update : std_ulogic; + pred_taken_cnt : std_ulogic_vector(0 to 1); + + isINVALID_OP : std_ulogic; + isATTN : std_ulogic; + + UpdatesLR : std_ulogic; + UpdatesCR : std_ulogic; + UpdatesCTR : std_ulogic; + UsesLR : std_ulogic; + UsesCR : std_ulogic; + UsesCTR : std_ulogic; + + is_st : std_ulogic; + is_ld : std_ulogic; + ibat_err : std_ulogic; + + tid : std_ulogic_vector(0 to 3); + + ifar : EFF_IFAR; + bta : EFF_IFAR; + + end record; + + function TO_STLV ( x : PPC_INSTR ) return std_ulogic_vector; + function TO_PPCI ( x : std_ulogic_vector(0 to 97+2*EFF_IFAR'length) ) return PPC_INSTR; + + +end iuq_pkg; + +package body iuq_pkg is + + function ib(x : std_ulogic) return boolean + is + begin + return(x = '1'); + end ib; + + + -- These functions all assume TO direction logic + function barrel_left(a : std_ulogic_vector; s : std_ulogic_vector) return std_ulogic_vector + is + variable result : std_ulogic_vector(a'left to a'right); + variable i : integer := 0; + begin + + result := a; + for i in s'left to s'right loop + if s(i) = '1' then + exit; + end if; + result := result(result'left+1 to result'right)&result(result'left); + end loop; + + return( result ); + end barrel_left; + + function barrel_right(a : std_ulogic_vector; s : std_ulogic_vector) return std_ulogic_vector + is + variable result : std_ulogic_vector(a'left to a'right); + begin + + result := a; + for i in a'left to a'right loop + if s(i) = '1' then + exit; + end if; + result := result(result'right) & result(result'left to result'right-1); + end loop; + + return( result ); + end barrel_right; + + + function pri_enc(a : std_ulogic_vector) return std_ulogic_vector + is + variable result : std_ulogic_vector(a'left to a'right); + begin + result := (others => '0'); + + for i in a'left to a'right loop + if a(i) = '1' then + result(i) := '1'; + exit; + end if; + end loop; + + return( result ); + end pri_enc; + + function shift_left(a : std_ulogic_vector; s : std_ulogic_vector) return std_ulogic_vector is + variable result : std_ulogic_vector(a'left to a'right); + begin + result := a; + for i in s'left to s'right loop + if s(i) = '1' then + exit; + end if; + result := result( result'left+1 to result'right)&'0'; + end loop; + return(result); + end shift_left; + + function shift_right(a : std_ulogic_vector; s : std_ulogic_vector) return std_ulogic_vector is + variable result : std_ulogic_vector(a'left to a'right); + begin + result := a; + for i in s'left to s'right loop + if s(i) = '1' then + exit; + end if; + result := '0'&result(result'left to result'right-1); + end loop; + return(result); + end shift_right; + + function mask_left(a : std_ulogic_vector ) return std_ulogic_vector is + variable result : std_ulogic_vector(a'left to a'right); + variable flag : integer := 0; + begin + for i in a'right downto a'left loop + if ((a(i) = '1') or (flag = 1)) then + result(i) := '1'; + flag := 1; + else + result(i) := a(i); + end if; + end loop; + return( result ); + end mask_left; + + function mask_right(a : std_ulogic_vector ) return std_ulogic_vector is + variable result : std_ulogic_vector(a'left to a'right); + variable flag : integer := 0; + begin + for i in a'left to a'right loop + if ((a(i) = '1') or (flag = 1)) then + result(i) := '1'; + flag := 1; + else + result(i) := a(i); + end if; + end loop; + return( result ); + end mask_right; + + function encode_4to2( a : std_ulogic_vector(0 to 3) ) return std_ulogic_vector is + variable result : std_ulogic_vector(0 to 1); + begin + case a is + when "1000" => result := "00"; + when "0100" => result := "01"; + when "0010" => result := "10"; + when "0001" => result := "11"; + when others => result := "00"; + end case; + return(result); + end encode_4to2; + + function encode_8to3( a : std_ulogic_vector(0 to 7) ) return std_ulogic_vector is + variable result : std_ulogic_vector(0 to 2); + begin + case a is + when "10000000" => result := "000"; + when "01000000" => result := "001"; + when "00100000" => result := "010"; + when "00010000" => result := "011"; + when "00001000" => result := "100"; + when "00000100" => result := "101"; + when "00000010" => result := "110"; + when "00000001" => result := "111"; + when others => result := "000"; + end case; + return(result); + end encode_8to3; + + function encode_16to4(a : std_ulogic_vector(0 to 15)) return std_ulogic_vector is + variable result : std_ulogic_vector(0 to 3); + begin + case a is + when "1000000000000000" => result := "0000"; + when "0100000000000000" => result := "0001"; + when "0010000000000000" => result := "0010"; + when "0001000000000000" => result := "0011"; + when "0000100000000000" => result := "0100"; + when "0000010000000000" => result := "0101"; + when "0000001000000000" => result := "0110"; + when "0000000100000000" => result := "0111"; + when "0000000010000000" => result := "1000"; + when "0000000001000000" => result := "1001"; + when "0000000000100000" => result := "1010"; + when "0000000000010000" => result := "1011"; + when "0000000000001000" => result := "1100"; + when "0000000000000100" => result := "1101"; + when "0000000000000010" => result := "1110"; + when "0000000000000001" => result := "1111"; + when others => result := "0000"; + end case; + return(result); + end encode_16to4; + + -- you better make sure that a and result are multiples of 1B with s being a strand representing the number of bytes to shift + function shift_leftx1B(a : std_ulogic_vector; s: std_ulogic_vector) return std_ulogic_vector is + variable result : std_ulogic_vector(a'left to a'right); + begin + result := a; + for i in s'left to s'right loop + if s(i) = '1' then + exit; + end if; + result := result( result'left+8 to result'right)&"00000000"; + end loop; + return(result); + end shift_leftx1B; + + function shift_rightx1B(a : std_ulogic_vector; s: std_ulogic_vector) return std_ulogic_vector is + variable result : std_ulogic_vector(a'left to a'right); + begin + result := a; + for i in s'left to s'right loop + if s(i) = '1' then + exit; + end if; + result := "00000000"&result(result'left to result'right-8); + end loop; + return(result); + end shift_rightx1B; + + + -------------------------------------------------------------------- + --- PPC_INSTR manipulation + -------------------------------------------------------------------- + + + -- x bit TID + function TO_STLV ( x : PPC_INSTR ) return std_ulogic_vector + is + variable result : std_ulogic_vector(0 to 97+2*EFF_IFAR'length); + begin + result := x.vld & + x.instr & + x.ta & + x.ta_vld & + x.ta_typ & + x.s1 & + x.s1_vld & + x.s1_typ & + x.s2 & + x.s2_vld & + x.s2_typ & + x.s3 & + x.s3_vld & + x.s3_typ & + x.isFxuIssue & + x.isVsuIssue & + x.EX4_exit & + x.EX7_exit & + x.isLWARX & + x.isSTWCX & + x.is_vcrs & + x.pred_update & + x.pred_taken_cnt & + x.isINVALID_OP & + x.isATTN & + x.UpdatesLR & + x.UpdatesCR & + x.UpdatesCTR & + x.UsesLR & + x.UsesCR & + x.UsesCTR & + x.is_st & + x.is_ld & + x.ibat_err & + x.tid & + x.ifar & + x.bta + ; + + return result; + end TO_STLV; + + -- x bit TID + function TO_PPCI ( x : std_ulogic_vector(0 to 97+2*EFF_IFAR'length) ) return PPC_INSTR is + variable result : PPC_INSTR; + begin + + result.vld := x(0); + result.instr := x(1 to 32); + result.ta := x(33 to 39); + result.ta_vld := x(40); + result.ta_typ := x(41 to 42); + result.s1 := x(43 to 49); + result.s1_vld := x(50); + result.s1_typ := x(51 to 52); + result.s2 := x(53 to 59); + result.s2_vld := x(60); + result.s2_typ := x(61 to 62); + result.s3 := x(63 to 69); + result.s3_vld := x(70); + result.s3_typ := x(71 to 72); + result.isFxuIssue := x(73); + result.isVsuIssue := x(74); + result.EX4_exit := x(75); + result.EX7_exit := x(76); + result.isLWARX := x(77); + result.isSTWCX := x(78); + result.is_vcrs := x(79); + result.pred_update := x(80); + result.pred_taken_cnt := x(81 to 82); + result.isINVALID_OP := x(83); + result.isATTN := x(84); + result.UpdatesLR := x(85); + result.UpdatesCR := x(86); + result.UpdatesCTR := x(87); + result.UsesLR := x(88); + result.UsesCR := x(89); + result.UsesCTR := x(90); + result.is_st := x(91); + result.is_ld := x(92); + result.ibat_err := x(93); + result.tid := x(94 to 97); + result.ifar := x(98 to 97+EFF_IFAR'length); + result.bta := x(98+EFF_IFAR'length to 97+2*EFF_IFAR'length); + + return result; + end TO_PPCI; + +procedure zeros(signal x : out std_ulogic) + is + begin + x <= '0'; + end zeros; + +procedure zeros(signal x : out std_ulogic_vector) + is + begin + for i in x'range loop + x(i) <= '0'; + end loop; + end zeros; + + +end iuq_pkg; diff --git a/rel/src/vhdl/work/iuq_ram.vhdl b/rel/src/vhdl/work/iuq_ram.vhdl new file mode 100644 index 0000000..4fa77f3 --- /dev/null +++ b/rel/src/vhdl/work/iuq_ram.vhdl @@ -0,0 +1,276 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + + +library ieee; +use ieee.std_logic_1164.all; + +library ibm; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; + +library support; +use support.power_logic_pkg.all; + +library tri; +use tri.tri_latches_pkg.all; + +library work; +use work.iuq_pkg.all; + +entity iuq_ram is +generic(expand_type : integer := 2 ); -- 0 = ibm umbra, 1 = xilinx, 2 = ibm mpg +port( + pc_iu_ram_instr : in std_ulogic_vector(0 to 31); + pc_iu_ram_instr_ext : in std_ulogic_vector(0 to 3); + pc_iu_ram_force_cmplt : in std_ulogic; + + xu_iu_ram_issue : in std_ulogic_vector(0 to 3); + + rm_ib_iu4_val : out std_ulogic_vector(0 to 3); + rm_ib_iu4_force_ram : out std_ulogic; + rm_ib_iu4_instr : out std_ulogic_vector(0 to 35); + + --pervasive + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + pc_iu_sg_2 : in std_ulogic; + pc_iu_func_sl_thold_2 : in std_ulogic; + clkoff_b : in std_ulogic; + act_dis : in std_ulogic; + tc_ac_ccflush_dc : in std_ulogic; + d_mode : in std_ulogic; + delay_lclkr : in std_ulogic; + mpw1_b : in std_ulogic; + mpw2_b : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic + +); + +-- synopsys translate_off + + +-- synopsys translate_on + +end iuq_ram; +---- +architecture iuq_ram of iuq_ram is + +---------------------------- +-- constants +---------------------------- + +--scan chain +constant ram_val_offset : natural := 0; +constant ram_iss_offset : natural := ram_val_offset + 4; +constant ram_instr_offset : natural := ram_iss_offset + 4; +constant ram_force_offset : natural := ram_instr_offset + 36; +constant scan_right : natural := ram_force_offset + 1-1; + +---------------------------- +-- signals +---------------------------- + +signal tiup : std_ulogic; + +signal ram_valid : std_ulogic; + +signal ram_iss_d : std_ulogic_vector(0 to 3); +signal ram_iss_q : std_ulogic_vector(0 to 3); +signal ram_val_d : std_ulogic_vector(0 to 3); +signal ram_val_q : std_ulogic_vector(0 to 3); +signal ram_instr_d : std_ulogic_vector(0 to 35); +signal ram_instr_q : std_ulogic_vector(0 to 35); +signal ram_force_d : std_ulogic; +signal ram_force_q : std_ulogic; + +signal pc_iu_func_sl_thold_1 : std_ulogic; +signal pc_iu_func_sl_thold_0 : std_ulogic; +signal pc_iu_func_sl_thold_0_b : std_ulogic; +signal pc_iu_sg_1 : std_ulogic; +signal pc_iu_sg_0 : std_ulogic; +signal forcee : std_ulogic; + +signal siv : std_ulogic_vector(0 to scan_right); +signal sov : std_ulogic_vector(0 to scan_right); + +begin + +tiup <= '1'; + +------------------------------------------------- +-- logic +------------------------------------------------- + + + + +ram_iss_d <= xu_iu_ram_issue; +ram_val_d <= ram_iss_q and not ram_iss_d; --detect falling edge of ram issue +ram_valid <= or_reduce(ram_iss_q); + + +ram_instr_d <= pc_iu_ram_instr & pc_iu_ram_instr_ext; +ram_force_d <= pc_iu_ram_force_cmplt; + +------------------------------------------------- +-- outputs +------------------------------------------------- + +rm_ib_iu4_val <= ram_val_q; +rm_ib_iu4_instr <= ram_instr_q; +rm_ib_iu4_force_ram <= ram_force_q; + +------------------------------------------------- +-- latches +------------------------------------------------- + +ram_iss_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(ram_iss_offset to ram_iss_offset+3), + scout => sov(ram_iss_offset to ram_iss_offset+3), + din => ram_iss_d(0 to 3), + dout => ram_iss_q(0 to 3)); + +ram_val_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(ram_val_offset to ram_val_offset+3), + scout => sov(ram_val_offset to ram_val_offset+3), + din => ram_val_d(0 to 3), + dout => ram_val_q(0 to 3)); + + +ram_instr_reg: tri_rlmreg_p + generic map (width => 36, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ram_valid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(ram_instr_offset to ram_instr_offset+35), + scout => sov(ram_instr_offset to ram_instr_offset+35), + din => ram_instr_d(0 to 35), + dout => ram_instr_q(0 to 35)); + +ram_force_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ram_valid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(ram_force_offset), + scout => sov(ram_force_offset), + din => ram_force_d, + dout => ram_force_q); + + +------------------------------------------------- +-- pervasive +------------------------------------------------- + +perv_2to1_reg: tri_plat + generic map (width => 2, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_iu_func_sl_thold_2, + din(1) => pc_iu_sg_2, + q(0) => pc_iu_func_sl_thold_1, + q(1) => pc_iu_sg_1); + +perv_1to0_reg: tri_plat + generic map (width => 2, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_iu_func_sl_thold_1, + din(1) => pc_iu_sg_1, + q(0) => pc_iu_func_sl_thold_0, + q(1) => pc_iu_sg_0); + +perv_lcbor: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_b, + thold => pc_iu_func_sl_thold_0, + sg => pc_iu_sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => pc_iu_func_sl_thold_0_b); + + +------------------------------------------------- +-- scan +------------------------------------------------- + +siv(0 to scan_right) <= scan_in & sov(0 to scan_right-1); +scan_out <= sov(scan_right); + + +end iuq_ram; diff --git a/rel/src/vhdl/work/iuq_rp.vhdl b/rel/src/vhdl/work/iuq_rp.vhdl new file mode 100644 index 0000000..19513a9 --- /dev/null +++ b/rel/src/vhdl/work/iuq_rp.vhdl @@ -0,0 +1,1021 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +--******************************************************************** +--* +--* TITLE: Instruction Unit Repower +--* +--* NAME: iuq_rp.vhdl +--* +--********************************************************************* + + +library ieee; +use ieee.std_logic_1164.all; + +library ibm; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; + +library support; +use support.power_logic_pkg.all; + +library tri; +use tri.tri_latches_pkg.all; + +entity iuq_rp is +generic(expand_type : integer := 2 ); -- 0 = ibm umbra, 1 = xilinx, 2 = ibm mpg +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + scan_diag_dc : in std_ulogic; + scan_dis_dc_b : in std_ulogic; + -- node thold+clock controls going to pcq + an_ac_ccflush_dc : in std_ulogic; + rtim_sl_thold_7 : in std_ulogic; + func_sl_thold_7 : in std_ulogic; + func_nsl_thold_7 : in std_ulogic; + ary_nsl_thold_7 : in std_ulogic; + sg_7 : in std_ulogic; + fce_7 : in std_ulogic; + rtim_sl_thold_6 : out std_ulogic; + func_sl_thold_6 : out std_ulogic; + func_nsl_thold_6 : out std_ulogic; + ary_nsl_thold_6 : out std_ulogic; + sg_6 : out std_ulogic; + fce_6 : out std_ulogic; + -- node inputs going to pcq + an_ac_scom_dch : in std_ulogic; + an_ac_scom_cch : in std_ulogic; + an_ac_checkstop : in std_ulogic; + an_ac_debug_stop : in std_ulogic; + an_ac_pm_thread_stop : in std_ulogic_vector(0 to 3); + an_ac_reset_1_complete : in std_ulogic; + an_ac_reset_2_complete : in std_ulogic; + an_ac_reset_3_complete : in std_ulogic; + an_ac_reset_wd_complete : in std_ulogic; + an_ac_abist_start_test : in std_ulogic; + ac_rp_trace_to_perfcntr : in std_ulogic_vector(0 to 7); + rp_pc_scom_dch_q : out std_ulogic; + rp_pc_scom_cch_q : out std_ulogic; + rp_pc_checkstop_q : out std_ulogic; + rp_pc_debug_stop_q : out std_ulogic; + rp_pc_pm_thread_stop_q : out std_ulogic_vector(0 to 3); + rp_pc_reset_1_complete_q : out std_ulogic; + rp_pc_reset_2_complete_q : out std_ulogic; + rp_pc_reset_3_complete_q : out std_ulogic; + rp_pc_reset_wd_complete_q : out std_ulogic; + rp_pc_abist_start_test_q : out std_ulogic; + rp_pc_trace_to_perfcntr_q : out std_ulogic_vector(0 to 7); + -- pcq outputs going to node + pc_rp_scom_dch : in std_ulogic; + pc_rp_scom_cch : in std_ulogic; + pc_rp_special_attn : in std_ulogic_vector(0 to 3); + pc_rp_checkstop : in std_ulogic_vector(0 to 2); + pc_rp_local_checkstop : in std_ulogic_vector(0 to 2); + pc_rp_recov_err : in std_ulogic_vector(0 to 2); + pc_rp_trace_error : in std_ulogic; + pc_rp_event_bus_enable : in std_ulogic; + pc_rp_event_bus : in std_ulogic_vector(0 to 7); + pc_rp_fu_bypass_events : in std_ulogic_vector(0 to 7); + pc_rp_iu_bypass_events : in std_ulogic_vector(0 to 7); + pc_rp_mm_bypass_events : in std_ulogic_vector(0 to 7); + pc_rp_lsu_bypass_events : in std_ulogic_vector(0 to 7); + pc_rp_pm_thread_running : in std_ulogic_vector(0 to 3); + pc_rp_power_managed : in std_ulogic; + pc_rp_rvwinkle_mode : in std_ulogic; + ac_an_scom_dch_q : out std_ulogic; + ac_an_scom_cch_q : out std_ulogic; + ac_an_special_attn_q : out std_ulogic_vector(0 to 3); + ac_an_checkstop_q : out std_ulogic_vector(0 to 2); + ac_an_local_checkstop_q : out std_ulogic_vector(0 to 2); + ac_an_recov_err_q : out std_ulogic_vector(0 to 2); + ac_an_trace_error_q : out std_ulogic; + rp_mm_event_bus_enable_q : out std_ulogic; + ac_an_event_bus_q : out std_ulogic_vector(0 to 7); + ac_an_fu_bypass_events_q : out std_ulogic_vector(0 to 7); + ac_an_iu_bypass_events_q : out std_ulogic_vector(0 to 7); + ac_an_mm_bypass_events_q : out std_ulogic_vector(0 to 7); + ac_an_lsu_bypass_events_q : out std_ulogic_vector(0 to 7); + ac_an_pm_thread_running_q : out std_ulogic_vector(0 to 3); + ac_an_power_managed_q : out std_ulogic; + ac_an_rvwinkle_mode_q : out std_ulogic; + + + + -- scan_in/out signals being repowered + pc_func_scan_in : in std_ulogic_vector(0 to 1); + pc_func_scan_in_q : out std_ulogic_vector(0 to 1); + pc_func_scan_out : in std_ulogic; + pc_func_scan_out_q : out std_ulogic; + pc_bcfg_scan_in : in std_ulogic; + pc_bcfg_scan_in_q : out std_ulogic; + pc_dcfg_scan_in : in std_ulogic; + pc_dcfg_scan_in_q : out std_ulogic; + pc_bcfg_scan_out : in std_ulogic; + pc_bcfg_scan_out_q : out std_ulogic; + pc_ccfg_scan_out : in std_ulogic; + pc_ccfg_scan_out_q : out std_ulogic; + pc_dcfg_scan_out : in std_ulogic; + pc_dcfg_scan_out_q : out std_ulogic; + -- + fu_abst_scan_in : in std_ulogic; + fu_abst_scan_in_q : out std_ulogic; + fu_abst_scan_out : in std_ulogic; + fu_abst_scan_out_q : out std_ulogic; + fu_ccfg_scan_out : in std_ulogic; + fu_ccfg_scan_out_q : out std_ulogic; + fu_bcfg_scan_out : in std_ulogic; + fu_bcfg_scan_out_q : out std_ulogic; + fu_dcfg_scan_out : in std_ulogic; + fu_dcfg_scan_out_q : out std_ulogic; + fu_func_scan_in : in std_ulogic_vector(0 to 3); + fu_func_scan_in_q : out std_ulogic_vector(0 to 3); + fu_func_scan_out : in std_ulogic_vector(0 to 3); + fu_func_scan_out_q : out std_ulogic_vector(0 to 3); + -- + bx_abst_scan_in : in std_ulogic; + bx_abst_scan_in_q : out std_ulogic; + bx_abst_scan_out : in std_ulogic; + bx_abst_scan_out_q : out std_ulogic; + bx_func_scan_in : in std_ulogic_vector(0 to 1); + bx_func_scan_in_q : out std_ulogic_vector(0 to 1); + bx_func_scan_out : in std_ulogic_vector(0 to 1); + bx_func_scan_out_q : out std_ulogic_vector(0 to 1); + -- + iu_func_scan_in : in std_ulogic_vector(0 to 8); + iu_func_scan_in_q : out std_ulogic_vector(0 to 8); + iu_func_scan_out : in std_ulogic_vector(0 to 9); + iu_func_scan_out_q : out std_ulogic_vector(0 to 9); + iu_bcfg_scan_in : in std_ulogic; + iu_bcfg_scan_in_q : out std_ulogic; + -- + spare_func_scan_in : in std_ulogic_vector(0 to 3); + spare_func_scan_in_q : out std_ulogic_vector(0 to 3); + spare_func_scan_out : in std_ulogic_vector(0 to 3); + spare_func_scan_out_q : out std_ulogic_vector(0 to 3); + + -- BG repower + bg_an_ac_func_scan_sn : in std_ulogic_vector(60 to 69); + bg_an_ac_abst_scan_sn : in std_ulogic_vector(10 to 11); + bg_an_ac_func_scan_sn_q : out std_ulogic_vector(60 to 69); + bg_an_ac_abst_scan_sn_q : out std_ulogic_vector(10 to 11); + + bg_ac_an_func_scan_ns : in std_ulogic_vector(60 to 69); + bg_ac_an_abst_scan_ns : in std_ulogic_vector(10 to 11); + bg_ac_an_func_scan_ns_q : out std_ulogic_vector(60 to 69); + bg_ac_an_abst_scan_ns_q : out std_ulogic_vector(10 to 11); + + bg_pc_l1p_abist_di_0 : in std_ulogic_vector(0 to 3); + bg_pc_l1p_abist_g8t1p_renb_0 : in std_ulogic; + bg_pc_l1p_abist_g8t_bw_0 : in std_ulogic; + bg_pc_l1p_abist_g8t_bw_1 : in std_ulogic; + bg_pc_l1p_abist_g8t_dcomp : in std_ulogic_vector(0 to 3); + bg_pc_l1p_abist_g8t_wenb : in std_ulogic; + bg_pc_l1p_abist_raddr_0 : in std_ulogic_vector(0 to 9); + bg_pc_l1p_abist_waddr_0 : in std_ulogic_vector(0 to 9); + bg_pc_l1p_abist_wl128_comp_ena : in std_ulogic; + bg_pc_l1p_abist_wl32_comp_ena : in std_ulogic; + bg_pc_l1p_abist_di_0_q : out std_ulogic_vector(0 to 3); + bg_pc_l1p_abist_g8t1p_renb_0_q : out std_ulogic; + bg_pc_l1p_abist_g8t_bw_0_q : out std_ulogic; + bg_pc_l1p_abist_g8t_bw_1_q : out std_ulogic; + bg_pc_l1p_abist_g8t_dcomp_q: out std_ulogic_vector(0 to 3); + bg_pc_l1p_abist_g8t_wenb_q : out std_ulogic; + bg_pc_l1p_abist_raddr_0_q : out std_ulogic_vector(0 to 9); + bg_pc_l1p_abist_waddr_0_q : out std_ulogic_vector(0 to 9); + bg_pc_l1p_abist_wl128_comp_ena_q : out std_ulogic; + bg_pc_l1p_abist_wl32_comp_ena_q : out std_ulogic; + + bg_pc_l1p_gptr_sl_thold_3 : in std_ulogic; + bg_pc_l1p_time_sl_thold_3 : in std_ulogic; + bg_pc_l1p_repr_sl_thold_3 : in std_ulogic; + bg_pc_l1p_abst_sl_thold_3 : in std_ulogic; + bg_pc_l1p_func_sl_thold_3 : in std_ulogic_vector(0 to 1); + bg_pc_l1p_func_slp_sl_thold_3 : in std_ulogic; + bg_pc_l1p_bolt_sl_thold_3 : in std_ulogic; + bg_pc_l1p_ary_nsl_thold_3 : in std_ulogic; + bg_pc_l1p_sg_3 : in std_ulogic_vector(0 to 1); + bg_pc_l1p_fce_3 : in std_ulogic; + bg_pc_l1p_bo_enable_3 : in std_ulogic; + bg_pc_l1p_gptr_sl_thold_2 : out std_ulogic; + bg_pc_l1p_time_sl_thold_2 : out std_ulogic; + bg_pc_l1p_repr_sl_thold_2 : out std_ulogic; + bg_pc_l1p_abst_sl_thold_2 : out std_ulogic; + bg_pc_l1p_func_sl_thold_2 : out std_ulogic_vector(0 to 1); + bg_pc_l1p_func_slp_sl_thold_2 : out std_ulogic; + bg_pc_l1p_bolt_sl_thold_2 : out std_ulogic; + bg_pc_l1p_ary_nsl_thold_2 : out std_ulogic; + bg_pc_l1p_sg_2 : out std_ulogic_vector(0 to 1); + bg_pc_l1p_fce_2 : out std_ulogic; + bg_pc_l1p_bo_enable_2 : out std_ulogic; + + -- Misc bolton signals + pc_mm_bo_enable_4 : in std_ulogic; + pc_iu_bo_enable_4 : in std_ulogic; + pc_mm_bo_enable_3 : out std_ulogic; + pc_iu_bo_enable_3 : out std_ulogic; + -- IU+MMU thold/sg/fce 4to3 PLAT staging + pc_iu_gptr_sl_thold_4 : in std_ulogic; + pc_iu_time_sl_thold_4 : in std_ulogic; + pc_iu_repr_sl_thold_4 : in std_ulogic; + pc_iu_abst_sl_thold_4 : in std_ulogic; + pc_iu_abst_slp_sl_thold_4 : in std_ulogic; + pc_iu_bolt_sl_thold_4 : in std_ulogic; + pc_iu_regf_slp_sl_thold_4 : in std_ulogic; + pc_iu_func_sl_thold_4 : in std_ulogic; + pc_iu_func_slp_sl_thold_4 : in std_ulogic; + pc_iu_cfg_sl_thold_4 : in std_ulogic; + pc_iu_cfg_slp_sl_thold_4 : in std_ulogic; + pc_iu_func_nsl_thold_4 : in std_ulogic; + pc_iu_func_slp_nsl_thold_4 : in std_ulogic; + pc_iu_ary_nsl_thold_4 : in std_ulogic; + pc_iu_ary_slp_nsl_thold_4 : in std_ulogic; + pc_iu_sg_4 : in std_ulogic; + pc_iu_fce_4 : in std_ulogic; + pc_iu_gptr_sl_thold_3 : out std_ulogic; + pc_iu_time_sl_thold_3 : out std_ulogic; + pc_iu_repr_sl_thold_3 : out std_ulogic; + pc_iu_abst_sl_thold_3 : out std_ulogic; + pc_iu_abst_slp_sl_thold_3 : out std_ulogic; + pc_iu_bolt_sl_thold_3 : out std_ulogic; + pc_iu_regf_slp_sl_thold_3 : out std_ulogic; + pc_iu_func_sl_thold_3 : out std_ulogic_vector(0 to 3); + pc_iu_func_slp_sl_thold_3 : out std_ulogic; + pc_iu_cfg_sl_thold_3 : out std_ulogic; + pc_iu_cfg_slp_sl_thold_3 : out std_ulogic; + pc_iu_func_slp_nsl_thold_3 : out std_ulogic; + pc_iu_ary_nsl_thold_3 : out std_ulogic; + pc_iu_ary_slp_nsl_thold_3 : out std_ulogic; + pc_iu_sg_3 : out std_ulogic_vector(0 to 3); + pc_iu_fce_3 : out std_ulogic; + pc_mm_gptr_sl_thold_3 : out std_ulogic; + pc_mm_time_sl_thold_3 : out std_ulogic; + pc_mm_repr_sl_thold_3 : out std_ulogic; + pc_mm_abst_sl_thold_3 : out std_ulogic; + pc_mm_abst_slp_sl_thold_3 : out std_ulogic; + pc_mm_bolt_sl_thold_3 : out std_ulogic; + pc_mm_func_sl_thold_3 : out std_ulogic_vector(0 to 1); + pc_mm_func_slp_sl_thold_3 : out std_ulogic_vector(0 to 1); + pc_mm_cfg_sl_thold_3 : out std_ulogic; + pc_mm_cfg_slp_sl_thold_3 : out std_ulogic; + pc_mm_func_nsl_thold_3 : out std_ulogic; + pc_mm_func_slp_nsl_thold_3 : out std_ulogic; + pc_mm_ary_nsl_thold_3 : out std_ulogic; + pc_mm_ary_slp_nsl_thold_3 : out std_ulogic; + pc_mm_sg_3 : out std_ulogic_vector(0 to 1); + pc_mm_fce_3 : out std_ulogic; + + -- tholds and scan chains + sg_2 : in std_ulogic; + func_sl_thold_2 : in std_ulogic; + func_slp_sl_thold_2 : in std_ulogic; + abst_sl_thold_2 : in std_ulogic; + abst_scan_in : in std_ulogic; + func_scan_in : in std_ulogic; + gptr_scan_in : in std_ulogic; + abst_scan_out : out std_ulogic; + func_scan_out : out std_ulogic; + gptr_scan_out : out std_ulogic +); + +-- synopsys translate_off + + +-- synopsys translate_on + +end iuq_rp; +---- +architecture iuq_rp of iuq_rp is + +-- ABIST Scan Ring +constant abst_size : positive := 1; +constant abst_bg_size : positive := 34; +-- start of abist scan chain ordering +constant abst_offset : natural := 0; +constant abst_bg_offset : natural := abst_offset + abst_size; +constant abst_right : natural := abst_bg_offset + abst_bg_size - 1; +-- end of abist scan chain ordering + +-- FUNC Scan Ring +constant perf_size : positive := 40; +constant func1_size : positive := 12; +constant func2_size : positive := 31; +-- start of func scan chain ordering +constant perf_offset : natural := 0; +constant func1_offset : natural := perf_offset + perf_size; +constant func2_offset : natural := func1_offset + func1_size; +constant func_right : natural := func2_offset + func2_size - 1; +-- end of func scan chain ordering + +signal abst_siv, abst_sov : std_ulogic_vector(0 to abst_right); +signal func_siv, func_sov : std_ulogic_vector(0 to func_right); + +signal slat_force : std_ulogic; +signal func_slat_thold_b : std_ulogic; +signal func_slat_d2clk : std_ulogic; +signal func_slat_lclk : clk_logic; +signal abst_slat_thold_b : std_ulogic; +signal abst_slat_d2clk : std_ulogic; +signal abst_slat_lclk : clk_logic; +signal cfg_slat_thold_b : std_ulogic; +signal cfg_slat_d2clk : std_ulogic; +signal cfg_slat_lclk : clk_logic; + +signal gptr_sl_thold_3_int : std_ulogic; +signal cfg_sl_thold_3_int : std_ulogic; +signal gptr_sl_thold_2 : std_ulogic; +signal cfg_sl_thold_2 : std_ulogic; +signal sg_1 : std_ulogic; +signal func_sl_thold_1 : std_ulogic; +signal func_slp_sl_thold_1 : std_ulogic; +signal gptr_sl_thold_1 : std_ulogic; +signal abst_sl_thold_1 : std_ulogic; +signal cfg_sl_thold_1 : std_ulogic; +signal sg_0 : std_ulogic; +signal func_sl_thold_0 : std_ulogic; +signal func_sl_thold_0_b : std_ulogic; +signal force_func : std_ulogic; +signal func_slp_sl_thold_0 : std_ulogic; +signal func_slp_sl_thold_0_b : std_ulogic; +signal force_func_slp : std_ulogic; +signal gptr_sl_thold_0 : std_ulogic; +signal abst_sl_thold_0 : std_ulogic; +signal abst_sl_thold_0_b : std_ulogic; +signal force_abst : std_ulogic; +signal cfg_sl_thold_0 : std_ulogic; + +signal clkoff_b : std_ulogic; +signal act_dis : std_ulogic; +signal d_mode : std_ulogic; +signal delay_lclkr : std_ulogic_vector(0 to 4); +signal mpw1_b : std_ulogic_vector(0 to 4); +signal mpw2_b : std_ulogic; + +signal event_bus_enable_int : std_ulogic; +signal unused : std_ulogic; + +-- synopsys translate_off +-- synopsys translate_on + +begin + +-- Outputs +rp_mm_event_bus_enable_q <= event_bus_enable_int; +pc_iu_gptr_sl_thold_3 <= gptr_sl_thold_3_int; +pc_iu_cfg_sl_thold_3 <= cfg_sl_thold_3_int; + + + +-- ---------------------------------- +perv_3to2_reg: tri_plat + generic map (width => 2, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => an_ac_ccflush_dc, + din(0) => gptr_sl_thold_3_int, + din(1) => cfg_sl_thold_3_int, + q(0) => gptr_sl_thold_2, + q(1) => cfg_sl_thold_2); + +perv_2to1_reg: tri_plat + generic map (width => 6, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => an_ac_ccflush_dc, + din(0) => func_sl_thold_2, + din(1) => func_slp_sl_thold_2, + din(2) => gptr_sl_thold_2, + din(3) => abst_sl_thold_2, + din(4) => cfg_sl_thold_2, + din(5) => sg_2, + q(0) => func_sl_thold_1, + q(1) => func_slp_sl_thold_1, + q(2) => gptr_sl_thold_1, + q(3) => abst_sl_thold_1, + q(4) => cfg_sl_thold_1, + q(5) => sg_1); + +perv_1to0_reg: tri_plat + generic map (width => 6, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => an_ac_ccflush_dc, + din(0) => func_sl_thold_1, + din(1) => func_slp_sl_thold_1, + din(2) => gptr_sl_thold_1, + din(3) => abst_sl_thold_1, + din(4) => cfg_sl_thold_1, + din(5) => sg_1, + q(0) => func_sl_thold_0, + q(1) => func_slp_sl_thold_0, + q(2) => gptr_sl_thold_0, + q(3) => abst_sl_thold_0, + q(4) => cfg_sl_thold_0, + q(5) => sg_0); + + +perv_lcbcntl: tri_lcbcntl_mac + generic map (expand_type => expand_type) + port map ( + vdd => vdd, + gnd => gnd, + sg => sg_0, + nclk => nclk, + scan_in => gptr_scan_in, + scan_diag_dc => scan_diag_dc, + thold => gptr_sl_thold_0, + clkoff_dc_b => clkoff_b, + delay_lclkr_dc => delay_lclkr(0 to 4), + act_dis_dc => act_dis, + d_mode_dc => d_mode, + mpw1_dc_b => mpw1_b(0 to 4), + mpw2_dc_b => mpw2_b, + scan_out => gptr_scan_out); + +unused <= or_reduce(delay_lclkr(1 to 4) & + d_mode & + mpw1_b(1 to 4) ); + +abst_lcbor: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_b, + thold => abst_sl_thold_0, + sg => sg_0, + act_dis => act_dis, + forcee => force_abst, + thold_b => abst_sl_thold_0_b); + +func_lcbor: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_b, + thold => func_sl_thold_0, + sg => sg_0, + act_dis => act_dis, + forcee => force_func, + thold_b => func_sl_thold_0_b); + +func_slp_lcbor: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_b, + thold => func_slp_sl_thold_0, + sg => sg_0, + act_dis => act_dis, + forcee => force_func_slp, + thold_b => func_slp_sl_thold_0_b); + + +-- LCBs for scan only staging latches +slat_force <= sg_0; +func_slat_thold_b <= NOT func_sl_thold_0; +abst_slat_thold_b <= NOT abst_sl_thold_0; +cfg_slat_thold_b <= NOT cfg_sl_thold_0; + +lcbs_func: tri_lcbs + generic map (expand_type => expand_type ) + port map ( + vd => vdd, + gd => gnd, + delay_lclkr => delay_lclkr(0), + nclk => nclk, + forcee => slat_force, + thold_b => func_slat_thold_b, + dclk => func_slat_d2clk, + lclk => func_slat_lclk ); + +lcbs_abst: tri_lcbs + generic map (expand_type => expand_type ) + port map ( + vd => vdd, + gd => gnd, + delay_lclkr => delay_lclkr(0), + nclk => nclk, + forcee => slat_force, + thold_b => abst_slat_thold_b, + dclk => abst_slat_d2clk, + lclk => abst_slat_lclk ); + +lcbs_cfg: tri_lcbs + generic map (expand_type => expand_type ) + port map ( + vd => vdd, + gd => gnd, + delay_lclkr => delay_lclkr(0), + nclk => nclk, + forcee => slat_force, + thold_b => cfg_slat_thold_b, + dclk => cfg_slat_d2clk, + lclk => cfg_slat_lclk ); + +-- Stages pcq clock control inputs +pcq_lvl7to6: tri_plat + generic map( width => 6, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => an_ac_ccflush_dc, + din( 0) => rtim_sl_thold_7, + din( 1) => func_sl_thold_7, + din( 2) => func_nsl_thold_7, + din( 3) => ary_nsl_thold_7, + din( 4) => sg_7, + din( 5) => fce_7, + q( 0) => rtim_sl_thold_6, + q( 1) => func_sl_thold_6, + q( 2) => func_nsl_thold_6, + q( 3) => ary_nsl_thold_6, + q( 4) => sg_6, + q( 5) => fce_6 + ); + + +-- Stages bg clock control inputs +bg_lvl3to2: tri_plat + generic map( width => 13, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => an_ac_ccflush_dc, + din( 0) => bg_pc_l1p_gptr_sl_thold_3, + din( 1) => bg_pc_l1p_time_sl_thold_3, + din( 2) => bg_pc_l1p_repr_sl_thold_3, + din( 3) => bg_pc_l1p_abst_sl_thold_3, + din( 4) => bg_pc_l1p_func_sl_thold_3(0), + din( 5) => bg_pc_l1p_func_sl_thold_3(1), + din( 6) => bg_pc_l1p_func_slp_sl_thold_3, + din( 7) => bg_pc_l1p_bolt_sl_thold_3, + din( 8) => bg_pc_l1p_ary_nsl_thold_3, + din( 9) => bg_pc_l1p_sg_3(0), + din(10) => bg_pc_l1p_sg_3(1), + din(11) => bg_pc_l1p_fce_3, + din(12) => bg_pc_l1p_bo_enable_3, + q( 0) => bg_pc_l1p_gptr_sl_thold_2, + q( 1) => bg_pc_l1p_time_sl_thold_2, + q( 2) => bg_pc_l1p_repr_sl_thold_2, + q( 3) => bg_pc_l1p_abst_sl_thold_2, + q( 4) => bg_pc_l1p_func_sl_thold_2(0), + q( 5) => bg_pc_l1p_func_sl_thold_2(1), + q( 6) => bg_pc_l1p_func_slp_sl_thold_2, + q( 7) => bg_pc_l1p_bolt_sl_thold_2, + q( 8) => bg_pc_l1p_ary_nsl_thold_2, + q( 9) => bg_pc_l1p_sg_2(0), + q(10) => bg_pc_l1p_sg_2(1), + q(11) => bg_pc_l1p_fce_2, + q(12) => bg_pc_l1p_bo_enable_2 + ); +-- Staging latches for scan_in/out signals on abist rings +fu_abst_stg: tri_slat_scan + generic map (width => 2, init => "00", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => abst_slat_d2clk, + lclk => abst_slat_lclk, + scan_in(0) => fu_abst_scan_in, + scan_in(1) => fu_abst_scan_out, + scan_out(0) => fu_abst_scan_in_q, + scan_out(1) => fu_abst_scan_out_q ); + +bx_abst_stg: tri_slat_scan + generic map (width => 2, init => "00", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => abst_slat_d2clk, + lclk => abst_slat_lclk, + scan_in(0) => bx_abst_scan_in, + scan_in(1) => bx_abst_scan_out, + scan_out(0) => bx_abst_scan_in_q, + scan_out(1) => bx_abst_scan_out_q ); + +bg_abst_stg: tri_slat_scan + generic map (width => 4, init => "0000", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => abst_slat_d2clk, + lclk => abst_slat_lclk, + scan_in(0 to 1) => bg_an_ac_abst_scan_sn(10 to 11), + scan_in(2 to 3) => bg_ac_an_abst_scan_ns(10 to 11), + scan_out(0 to 1) => bg_an_ac_abst_scan_sn_q(10 to 11), + scan_out(2 to 3) => bg_ac_an_abst_scan_ns_q(10 to 11) ); + +-- Staging latches for scan_in/out signals on func rings +pc_func_stg: tri_slat_scan + generic map (width => 3, init => "000", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => func_slat_d2clk, + lclk => func_slat_lclk, + scan_in(0 to 1) => pc_func_scan_in(0 to 1), + scan_in(2) => pc_func_scan_out, + scan_out(0 to 1)=> pc_func_scan_in_q(0 to 1), + scan_out(2) => pc_func_scan_out_q ); + +fu_func_stg: tri_slat_scan + generic map (width => 8, init => "00000000", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => func_slat_d2clk, + lclk => func_slat_lclk, + scan_in(0 to 3) => fu_func_scan_in(0 to 3), + scan_in(4 to 7) => fu_func_scan_out(0 to 3), + scan_out(0 to 3) => fu_func_scan_in_q(0 to 3), + scan_out(4 to 7) => fu_func_scan_out_q(0 to 3) ); + +bx_func_stg: tri_slat_scan + generic map (width => 4, init => "0000", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => func_slat_d2clk, + lclk => func_slat_lclk, + scan_in(0 to 1) => bx_func_scan_in(0 to 1), + scan_in(2 to 3) => bx_func_scan_out(0 to 1), + scan_out(0 to 1) => bx_func_scan_in_q(0 to 1), + scan_out(2 to 3) => bx_func_scan_out_q(0 to 1) ); + +iu_func_stg: tri_slat_scan + generic map (width => 19, init => "0000000000000000000", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => func_slat_d2clk, + lclk => func_slat_lclk, + scan_in(0 to 8) => iu_func_scan_in(0 to 8), + scan_in(9 to 18) => iu_func_scan_out(0 to 9), + scan_out(0 to 8) => iu_func_scan_in_q(0 to 8), + scan_out(9 to 18) => iu_func_scan_out_q(0 to 9) ); + +spare_func_stg: tri_slat_scan + generic map (width => 8, init => "00000000", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => func_slat_d2clk, + lclk => func_slat_lclk, + scan_in(0 to 3) => spare_func_scan_in(0 to 3), + scan_in(4 to 7) => spare_func_scan_out(0 to 3), + scan_out(0 to 3) => spare_func_scan_in_q(0 to 3), + scan_out(4 to 7) => spare_func_scan_out_q(0 to 3) ); + +bg_func_stg: tri_slat_scan + generic map (width => 20, init => "00000000000000000000", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => func_slat_d2clk, + lclk => func_slat_lclk, + scan_in(0 to 9) => bg_an_ac_func_scan_sn(60 to 69), + scan_in(10 to 19) => bg_ac_an_func_scan_ns(60 to 69), + scan_out(0 to 9) => bg_an_ac_func_scan_sn_q(60 to 69), + scan_out(10 to 19)=> bg_ac_an_func_scan_ns_q(60 to 69) ); + +-- Staging latches for scan_in/out signals on config rings +pc_cfg_stg: tri_slat_scan + generic map (width => 5, init => "00000", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => cfg_slat_d2clk, + lclk => cfg_slat_lclk, + scan_in(0) => pc_bcfg_scan_in, + scan_in(1) => pc_dcfg_scan_in, + scan_in(2) => pc_bcfg_scan_out, + scan_in(3) => pc_ccfg_scan_out, + scan_in(4) => pc_dcfg_scan_out, + scan_out(0) => pc_bcfg_scan_in_q, + scan_out(1) => pc_dcfg_scan_in_q, + scan_out(2) => pc_bcfg_scan_out_q, + scan_out(3) => pc_ccfg_scan_out_q, + scan_out(4) => pc_dcfg_scan_out_q ); + +fu_cfg_stg: tri_slat_scan + generic map (width => 3, init => "000", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => cfg_slat_d2clk, + lclk => cfg_slat_lclk, + scan_in(0) => fu_bcfg_scan_out, + scan_in(1) => fu_ccfg_scan_out, + scan_in(2) => fu_dcfg_scan_out, + scan_out(0) => fu_bcfg_scan_out_q, + scan_out(1) => fu_ccfg_scan_out_q, + scan_out(2) => fu_dcfg_scan_out_q ); + +iu_cfg_stg: tri_slat_scan + generic map (width => 1, init => "0", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => cfg_slat_d2clk, + lclk => cfg_slat_lclk, + scan_in(0) => iu_bcfg_scan_in, + scan_out(0) => iu_bcfg_scan_in_q ); + +-- Misc staging latches on abist ring +abist_staging: tri_rlmreg_p + generic map (width => abst_size, init => 0, expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + nclk => nclk, + act => '1', + thold_b => abst_sl_thold_0_b, + sg => sg_0, + forcee => force_abst, + delay_lclkr => delay_lclkr(0), + mpw1_b => mpw1_b(0), + mpw2_b => mpw2_b, + scin => abst_siv(abst_offset to abst_offset + abst_size-1), + scout => abst_sov(abst_offset to abst_offset + abst_size-1), + din(0) => an_ac_abist_start_test, + dout(0) => rp_pc_abist_start_test_q ); + +abist_bg_staging: tri_rlmreg_p + generic map (width => abst_bg_size, init => 0, expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + nclk => nclk, + act => '1', + thold_b => abst_sl_thold_0_b, + sg => sg_0, + forcee => force_abst, + delay_lclkr => delay_lclkr(0), + mpw1_b => mpw1_b(0), + mpw2_b => mpw2_b, + scin => abst_siv(abst_bg_offset to abst_bg_offset + abst_bg_size-1), + scout => abst_sov(abst_bg_offset to abst_bg_offset + abst_bg_size-1), + din( 0 to 3) => bg_pc_l1p_abist_di_0, + din( 4) => bg_pc_l1p_abist_g8t1p_renb_0, + din( 5) => bg_pc_l1p_abist_g8t_bw_0, + din( 6) => bg_pc_l1p_abist_g8t_bw_1, + din( 7 to 10) => bg_pc_l1p_abist_g8t_dcomp, + din(11) => bg_pc_l1p_abist_g8t_wenb, + din(12 to 21) => bg_pc_l1p_abist_raddr_0, + din(22 to 31) => bg_pc_l1p_abist_waddr_0, + din(32) => bg_pc_l1p_abist_wl128_comp_ena, + din(33) => bg_pc_l1p_abist_wl32_comp_ena, + dout( 0 to 3) => bg_pc_l1p_abist_di_0_q, + dout( 4) => bg_pc_l1p_abist_g8t1p_renb_0_q, + dout( 5) => bg_pc_l1p_abist_g8t_bw_0_q, + dout( 6) => bg_pc_l1p_abist_g8t_bw_1_q, + dout( 7 to 10) => bg_pc_l1p_abist_g8t_dcomp_q, + dout(11) => bg_pc_l1p_abist_g8t_wenb_q, + dout(12 to 21) => bg_pc_l1p_abist_raddr_0_q, + dout(22 to 31) => bg_pc_l1p_abist_waddr_0_q, + dout(32) => bg_pc_l1p_abist_wl128_comp_ena_q, + dout(33) => bg_pc_l1p_abist_wl32_comp_ena_q ); + +-- Misc staging latches on func ring +perf_staging: tri_rlmreg_p + generic map (width => perf_size, init => 0, expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + nclk => nclk, + act => event_bus_enable_int, + thold_b => func_sl_thold_0_b, + sg => sg_0, + forcee => force_func, + delay_lclkr => delay_lclkr(0), + mpw1_b => mpw1_b(0), + mpw2_b => mpw2_b, + scin => func_siv(perf_offset to perf_offset + perf_size-1), + scout => func_sov(perf_offset to perf_offset + perf_size-1), + din(0 to 7) => pc_rp_event_bus, + din(8 to 15) => pc_rp_fu_bypass_events, + din(16 to 23) => pc_rp_iu_bypass_events, + din(24 to 31) => pc_rp_mm_bypass_events, + din(32 to 39) => pc_rp_lsu_bypass_events, + + dout(0 to 7) => ac_an_event_bus_q, + dout(8 to 15) => ac_an_fu_bypass_events_q, + dout(16 to 23) => ac_an_iu_bypass_events_q, + dout(24 to 31) => ac_an_mm_bypass_events_q, + dout(32 to 39) => ac_an_lsu_bypass_events_q ); + + +func_staging: tri_rlmreg_p + generic map (width => func1_size, init => 0, expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + nclk => nclk, + act => '1', + thold_b => func_sl_thold_0_b, + sg => sg_0, + forcee => force_func, + delay_lclkr => delay_lclkr(0), + mpw1_b => mpw1_b(0), + mpw2_b => mpw2_b, + scin => func_siv(func1_offset to func1_offset + func1_size-1), + scout => func_sov(func1_offset to func1_offset + func1_size-1), + din(0) => an_ac_reset_1_complete, + din(1) => an_ac_reset_2_complete, + din(2) => an_ac_reset_3_complete, + din(3) => an_ac_reset_wd_complete, + din(4 to 11)=> ac_rp_trace_to_perfcntr, + + dout(0) => rp_pc_reset_1_complete_q, + dout(1) => rp_pc_reset_2_complete_q, + dout(2) => rp_pc_reset_3_complete_q, + dout(3) => rp_pc_reset_wd_complete_q, + dout(4 to 11)=> rp_pc_trace_to_perfcntr_q ); + +func_slp_staging: tri_rlmreg_p + generic map (width => func2_size, init => 0, expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + nclk => nclk, + act => '1', + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + forcee => force_func_slp, + delay_lclkr => delay_lclkr(0), + mpw1_b => mpw1_b(0), + mpw2_b => mpw2_b, + scin => func_siv(func2_offset to func2_offset + func2_size-1), + scout => func_sov(func2_offset to func2_offset + func2_size-1), + din(0) => an_ac_scom_dch, + din(1) => an_ac_scom_cch, + din(2) => an_ac_checkstop, + din(3) => an_ac_debug_stop, + din(4 to 7) => an_ac_pm_thread_stop, + din(8) => pc_rp_scom_dch, + din(9) => pc_rp_scom_cch, + din(10 to 13) => pc_rp_special_attn, + din(14 to 16) => pc_rp_checkstop, + din(17 to 19) => pc_rp_local_checkstop, + din(20 to 22) => pc_rp_recov_err, + din(23 to 26) => pc_rp_pm_thread_running, + din(27) => pc_rp_power_managed, + din(28) => pc_rp_rvwinkle_mode, + din(29) => pc_rp_event_bus_enable, + din(30) => pc_rp_trace_error, + + dout(0) => rp_pc_scom_dch_q, + dout(1) => rp_pc_scom_cch_q, + dout(2) => rp_pc_checkstop_q, + dout(3) => rp_pc_debug_stop_q, + dout(4 to 7) => rp_pc_pm_thread_stop_q, + dout(8) => ac_an_scom_dch_q, + dout(9) => ac_an_scom_cch_q, + dout(10 to 13) => ac_an_special_attn_q, + dout(14 to 16) => ac_an_checkstop_q, + dout(17 to 19) => ac_an_local_checkstop_q, + dout(20 to 22) => ac_an_recov_err_q, + dout(23 to 26) => ac_an_pm_thread_running_q, + dout(27) => ac_an_power_managed_q, + dout(28) => ac_an_rvwinkle_mode_q, + dout(29) => event_bus_enable_int, + dout(30) => ac_an_trace_error_q ); + + +-- Misc bolton signals +iu_bo_enab_4_3: tri_plat + generic map (width => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => an_ac_ccflush_dc, + din(0) => pc_iu_bo_enable_4, + q(0) => pc_iu_bo_enable_3); + +mm_bo_enab_4_3: tri_plat + generic map (width => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => an_ac_ccflush_dc, + din(0) => pc_mm_bo_enable_4, + q(0) => pc_mm_bo_enable_3 ); + +-- IU+MMU thold/sg/fce 4to3 PLAT staging +iu_thold_stg4to3: tri_plat + generic map( width => 22, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => an_ac_ccflush_dc, + din( 0) => pc_iu_gptr_sl_thold_4, + din( 1) => pc_iu_time_sl_thold_4, + din( 2) => pc_iu_repr_sl_thold_4, + din( 3) => pc_iu_abst_sl_thold_4, + din( 4) => pc_iu_abst_slp_sl_thold_4, + din( 5) => pc_iu_bolt_sl_thold_4, + din( 6) => pc_iu_regf_slp_sl_thold_4, + din( 7) => pc_iu_func_sl_thold_4, + din( 8) => pc_iu_func_sl_thold_4, + din( 9) => pc_iu_func_sl_thold_4, + din(10) => pc_iu_func_sl_thold_4, + din(11) => pc_iu_func_slp_sl_thold_4, + din(12) => pc_iu_cfg_sl_thold_4, + din(13) => pc_iu_cfg_slp_sl_thold_4, + din(14) => pc_iu_func_slp_nsl_thold_4, + din(15) => pc_iu_ary_nsl_thold_4, + din(16) => pc_iu_ary_slp_nsl_thold_4, + din(17) => pc_iu_sg_4, + din(18) => pc_iu_sg_4, + din(19) => pc_iu_sg_4, + din(20) => pc_iu_sg_4, + din(21) => pc_iu_fce_4, + q( 0) => gptr_sl_thold_3_int, + q( 1) => pc_iu_time_sl_thold_3, + q( 2) => pc_iu_repr_sl_thold_3, + q( 3) => pc_iu_abst_sl_thold_3, + q( 4) => pc_iu_abst_slp_sl_thold_3, + q( 5) => pc_iu_bolt_sl_thold_3, + q( 6) => pc_iu_regf_slp_sl_thold_3, + q( 7) => pc_iu_func_sl_thold_3(0), + q( 8) => pc_iu_func_sl_thold_3(1), + q( 9) => pc_iu_func_sl_thold_3(2), + q(10) => pc_iu_func_sl_thold_3(3), + q(11) => pc_iu_func_slp_sl_thold_3, + q(12) => cfg_sl_thold_3_int, + q(13) => pc_iu_cfg_slp_sl_thold_3, + q(14) => pc_iu_func_slp_nsl_thold_3, + q(15) => pc_iu_ary_nsl_thold_3, + q(16) => pc_iu_ary_slp_nsl_thold_3, + q(17) => pc_iu_sg_3(0), + q(18) => pc_iu_sg_3(1), + q(19) => pc_iu_sg_3(2), + q(20) => pc_iu_sg_3(3), + q(21) => pc_iu_fce_3 + ); + + +mm_thold_stg4to3: tri_plat + generic map( width => 19, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => an_ac_ccflush_dc, + din( 0) => pc_iu_gptr_sl_thold_4, + din( 1) => pc_iu_time_sl_thold_4, + din( 2) => pc_iu_repr_sl_thold_4, + din( 3) => pc_iu_abst_sl_thold_4, + din( 4) => pc_iu_abst_slp_sl_thold_4, + din( 5) => pc_iu_bolt_sl_thold_4, + din( 6) => pc_iu_func_sl_thold_4, + din( 7) => pc_iu_func_sl_thold_4, + din( 8) => pc_iu_func_slp_sl_thold_4, + din( 9) => pc_iu_func_slp_sl_thold_4, + din(10) => pc_iu_cfg_sl_thold_4, + din(11) => pc_iu_cfg_slp_sl_thold_4, + din(12) => pc_iu_func_nsl_thold_4, + din(13) => pc_iu_func_slp_nsl_thold_4, + din(14) => pc_iu_ary_nsl_thold_4, + din(15) => pc_iu_ary_slp_nsl_thold_4, + din(16) => pc_iu_sg_4, + din(17) => pc_iu_sg_4, + din(18) => pc_iu_fce_4, + q( 0) => pc_mm_gptr_sl_thold_3, + q( 1) => pc_mm_time_sl_thold_3, + q( 2) => pc_mm_repr_sl_thold_3, + q( 3) => pc_mm_abst_sl_thold_3, + q( 4) => pc_mm_abst_slp_sl_thold_3, + q( 5) => pc_mm_bolt_sl_thold_3, + q( 6) => pc_mm_func_sl_thold_3(0), + q( 7) => pc_mm_func_sl_thold_3(1), + q( 8) => pc_mm_func_slp_sl_thold_3(0), + q( 9) => pc_mm_func_slp_sl_thold_3(1), + q(10) => pc_mm_cfg_sl_thold_3, + q(11) => pc_mm_cfg_slp_sl_thold_3, + q(12) => pc_mm_func_nsl_thold_3, + q(13) => pc_mm_func_slp_nsl_thold_3, + q(14) => pc_mm_ary_nsl_thold_3, + q(15) => pc_mm_ary_slp_nsl_thold_3, + q(16) => pc_mm_sg_3(0), + q(17) => pc_mm_sg_3(1), + q(18) => pc_mm_fce_3 + ); + +-- Scan Ring Connections +-- abist ring +abst_siv(0 TO abst_right) <= abst_scan_in & abst_sov(0 to abst_right-1); +abst_scan_out <= abst_sov(abst_right) and scan_dis_dc_b; + +--func ring +func_siv(0 TO func_right) <= func_scan_in & func_sov(0 to func_right-1); +func_scan_out <= func_sov(func_right) and scan_dis_dc_b; + +end iuq_rp; diff --git a/rel/src/vhdl/work/iuq_slice.vhdl b/rel/src/vhdl/work/iuq_slice.vhdl new file mode 100644 index 0000000..039690a --- /dev/null +++ b/rel/src/vhdl/work/iuq_slice.vhdl @@ -0,0 +1,842 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +--******************************************************************** +--* +--* TITLE: Instruction Unit +--* +--* NAME: iuq_slice.vhdl +--* +--********************************************************************* +library ieee; +use ieee.std_logic_1164.all; +library ibm; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; +library support; +use support.power_logic_pkg.all; +library work; +use work.iuq_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity iuq_slice is + generic(expand_type : integer := 2; + regmode : integer := 6; + a2mode : integer := 1; + lmq_entries : integer := 8); +port( + slice_id : in std_ulogic_vector(0 to 1); + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + pc_iu_sg_2 : in std_ulogic; + pc_iu_func_sl_thold_2 : in std_ulogic; + clkoff_b : in std_ulogic; + an_ac_scan_dis_dc_b : in std_ulogic; + tc_ac_ccflush_dc : in std_ulogic; + delay_lclkr : in std_ulogic; + mpw1_b : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + + pc_iu_trace_bus_enable : in std_ulogic; + pc_iu_event_bus_enable : in std_ulogic; + fdep_dbg_data : out std_ulogic_vector(0 to 21); + fdep_perf_event : out std_ulogic_vector(0 to 11); + + pc_iu_ram_mode : in std_ulogic; + pc_iu_ram_thread : in std_ulogic_vector(0 to 1); + + spr_dec_mask : in std_ulogic_vector(0 to 31); + spr_dec_match : in std_ulogic_vector(0 to 31); + iu_au_config_iucr : in std_ulogic_vector(0 to 7); + iu_au_config_iucr_pt : out std_ulogic_vector(2 to 4); + spr_fdep_ll_hold : in std_ulogic; + + + uc_flush : in std_ulogic; + xu_iu_flush : in std_ulogic; + xu_iu_rf1_flush : in std_ulogic; + xu_iu_ex1_flush : in std_ulogic; + xu_iu_ex2_flush : in std_ulogic; + xu_iu_ex3_flush : in std_ulogic; + xu_iu_ex4_flush : in std_ulogic; + xu_iu_ex5_flush : in std_ulogic; + + iu_au_ib1_instr_vld : in std_ulogic; + iu_au_ib1_ifar : in EFF_IFAR; + iu_au_ib1_data : in std_ulogic_vector(0 to 49); + + + fdec_ibuf_stall : out std_ulogic; + + +xu_iu_ucode_restart : in std_ulogic; +xu_iu_slowspr_done : in std_ulogic; +xu_iu_multdiv_done : in std_ulogic; +xu_iu_ex4_loadmiss_vld : in std_ulogic; +xu_iu_ex4_loadmiss_qentry : in std_ulogic_vector(0 to lmq_entries-1); +xu_iu_ex4_loadmiss_target : in std_ulogic_vector(0 to 8); +xu_iu_ex4_loadmiss_target_type : in std_ulogic_vector(0 to 1); +xu_iu_ex5_loadmiss_vld : in std_ulogic; +xu_iu_ex5_loadmiss_qentry : in std_ulogic_vector(0 to lmq_entries-1); +xu_iu_ex5_loadmiss_target : in std_ulogic_vector(1 to 6); +xu_iu_ex5_loadmiss_target_type : in std_ulogic_vector(0 to 0); +xu_iu_complete_vld : in std_ulogic; +xu_iu_complete_qentry : in std_ulogic_vector(0 to lmq_entries-1); +xu_iu_complete_target_type : in std_ulogic_vector(0 to 1); +xu_iu_single_instr_mode : in std_ulogic; +ic_fdep_load_quiesce : in std_ulogic; +iu_xu_quiesce : out std_ulogic; +xu_iu_membar_tid : in std_ulogic; +xu_iu_set_barr_tid : in std_ulogic; +xu_iu_larx_done_tid : in std_ulogic; +an_ac_sync_ack : in std_ulogic; +an_ac_stcx_complete : in std_ulogic; +ic_fdep_icbi_ack : in std_ulogic; +mm_iu_barrier_done : in std_ulogic; +xu_iu_spr_ccr2_en_dcr : in std_ulogic; +fiss_fdep_is2_take : in std_ulogic; +fdep_fiss_is2_instr : out std_ulogic_vector(0 to 31); +fdep_fiss_is2_ta_vld : out std_ulogic; +fdep_fiss_is2_ta : out std_ulogic_vector(0 to 5); +fdep_fiss_is2_s1_vld : out std_ulogic; +fdep_fiss_is2_s1 : out std_ulogic_vector(0 to 5); +fdep_fiss_is2_s2_vld : out std_ulogic; +fdep_fiss_is2_s2 : out std_ulogic_vector(0 to 5); +fdep_fiss_is2_s3_vld : out std_ulogic; +fdep_fiss_is2_s3 : out std_ulogic_vector(0 to 5); +fdep_fiss_is2_pred_update : out std_ulogic; +fdep_fiss_is2_pred_taken_cnt : out std_ulogic_vector(0 to 1); +fdep_fiss_is2_gshare : out std_ulogic_vector(0 to 3); +fdep_fiss_is2_ifar : out eff_ifar; +fdep_fiss_is2_error : out std_ulogic_vector(0 to 2); +fdep_fiss_is2_axu_ld_or_st : out std_ulogic; +fdep_fiss_is2_axu_store : out std_ulogic; +fdep_fiss_is2_axu_ldst_indexed : out std_ulogic; +fdep_fiss_is2_axu_ldst_tag : out std_ulogic_vector(0 to 8); +fdep_fiss_is2_axu_ldst_size : out std_ulogic_vector(0 to 5); +fdep_fiss_is2_axu_ldst_update : out std_ulogic; +fdep_fiss_is2_axu_ldst_extpid : out std_ulogic; +fdep_fiss_is2_axu_ldst_forcealign : out std_ulogic; +fdep_fiss_is2_axu_ldst_forceexcept : out std_ulogic; +fdep_fiss_is2_axu_mftgpr : out std_ulogic; +fdep_fiss_is2_axu_mffgpr : out std_ulogic; +fdep_fiss_is2_axu_movedp : out std_ulogic; +fdep_fiss_is2_axu_instr_type : out std_ulogic_vector(0 to 2); +fdep_fiss_is2_match : out std_ulogic; +fdep_fiss_is2_2ucode : out std_ulogic; +fdep_fiss_is2_2ucode_type : out std_ulogic; +fdep_fiss_is2early_vld : out std_ulogic; +fdep_fiss_is1_xu_dep_hit_b : out std_ulogic; +fdep_fiss_is2_hole_delay : out std_ulogic_vector(0 to 2); +fdep_fiss_is2_to_ucode : out std_ulogic; +fdep_fiss_is2_is_ucode : out std_ulogic; +fu_iu_uc_special : in std_ulogic; +iu_fu_ex2_n_flush : out std_ulogic; +i_afi_is2_take : in std_ulogic; +i_axu_is1_early_v : out std_ulogic; +i_axu_is1_dep_hit_b : out std_ulogic; +i_axu_is2_instr_match : out std_ulogic; +i_axu_is2_instr_v : out std_ulogic; +i_axu_is2_fra : out std_ulogic_vector(0 to 6); +i_axu_is2_frb : out std_ulogic_vector(0 to 6); +i_axu_is2_frc : out std_ulogic_vector(0 to 6); +i_axu_is2_frt : out std_ulogic_vector(0 to 6); +i_axu_is2_fra_v : out std_ulogic; +i_axu_is2_frb_v : out std_ulogic; +i_axu_is2_frc_v : out std_ulogic; +i_afd_is2_is_ucode : out std_ulogic; +i_afd_ignore_flush_is2 : out std_ulogic; +i_afd_in_ucode_mode_or1d_b : out std_ulogic; +ifdp_is2_est_bubble3 : out std_ulogic; +ifdp_is2_bypsel : out std_ulogic_vector(0 to 5); +axu_dbg_data : out std_ulogic_vector(00 to 37) + ); +-- synopsys translate_off +-- synopsys translate_on +end iuq_slice; +architecture iuq_slice of iuq_slice is +constant ibuff_data_width : integer := 42; +-- scan chain 0 +constant scan_dec : natural := 0; +constant scan_dep : natural := 1; +constant scan_axu_dec : natural := 2; +constant scan_axu_dep : natural := 3; +constant scan_right : natural := 3; +signal au_iu_is0_to_ucode : std_ulogic; +signal au_iu_is0_ucode_only : std_ulogic; +-- flush +signal ib1_flush : std_ulogic; +signal is1_flush : std_ulogic; +signal is2_flush : std_ulogic; +signal rf0_flush : std_ulogic; +-- ib signals +signal iu_au_ib1_instr0 : std_ulogic_vector(0 to 31); +signal iu_au_ib1_instr0_pred_vld : std_ulogic; +signal iu_au_ib1_instr0_ucode_ext : std_ulogic_vector(0 to 3); +signal iu_au_ib1_instr0_pred_taken_cnt : std_ulogic_vector(0 to 1); +signal iu_au_ib1_instr0_error : std_ulogic_vector(0 to 2); +signal iu_au_ib1_instr0_is_ucode : std_ulogic; +signal iu_au_ib1_instr0_2ucode : std_ulogic; +signal iu_au_ib1_instr0_2ucode_type : std_ulogic; +signal iu_au_ib1_instr0_force_ram : std_ulogic; +signal iu_au_ib1_instr0_gshare : std_ulogic_vector(0 to 3); +-- is signals +signal iu_au_is1_cr_user_v : std_ulogic; +signal iu_au_is0_cr_setter : std_ulogic; +signal i_afd_is1_cr_setter : std_ulogic; +-- fdec signals +signal fdec_fdep_is1_vld : std_ulogic; +signal fdec_fdep_is1_instr : std_ulogic_vector(0 to 31); +signal fdec_fdep_is1_ta_vld : std_ulogic; +signal fdec_fdep_is1_ta : std_ulogic_vector(0 to 5); +signal fdec_fdep_is1_s1_vld : std_ulogic; +signal fdec_fdep_is1_s1 : std_ulogic_vector(0 to 5); +signal fdec_fdep_is1_s2_vld : std_ulogic; +signal fdec_fdep_is1_s2 : std_ulogic_vector(0 to 5); +signal fdec_fdep_is1_s3_vld : std_ulogic; +signal fdec_fdep_is1_s3 : std_ulogic_vector(0 to 5); +signal fdec_fdep_is1_pred_update : std_ulogic; +signal fdec_fdep_is1_pred_taken_cnt : std_ulogic_vector(0 to 1); +signal fdec_fdep_is1_gshare : std_ulogic_vector(0 to 3); +signal fdec_fdep_is1_UpdatesLR : std_ulogic; +signal fdec_fdep_is1_UpdatesCR : std_ulogic; +signal fdec_fdep_is1_UpdatesCTR : std_ulogic; +signal fdec_fdep_is1_UpdatesXER : std_ulogic; +signal fdec_fdep_is1_UpdatesMSR : std_ulogic; +signal fdec_fdep_is1_UpdatesSPR : std_ulogic; +signal fdec_fdep_is1_UsesLR : std_ulogic; +signal fdec_fdep_is1_UsesCR : std_ulogic; +signal fdec_fdep_is1_UsesCTR : std_ulogic; +signal fdec_fdep_is1_UsesXER : std_ulogic; +signal fdec_fdep_is1_UsesMSR : std_ulogic; +signal fdec_fdep_is1_UsesSPR : std_ulogic; +signal fdec_fdep_is1_hole_delay : std_ulogic_vector(0 to 2); +signal fdec_fdep_is1_ld_vld : std_ulogic; +signal fdec_fdep_is1_to_ucode : std_ulogic; +signal fdec_fdep_is1_is_ucode : std_ulogic; +signal fdec_fdep_is1_ifar : EFF_IFAR; +signal fdec_fdep_is1_error : std_ulogic_vector(0 to 2); +signal fdec_fdep_is1_complete : std_ulogic_vector(0 to 4); +signal fdec_fdep_is1_axu_ld_or_st : std_ulogic; +signal fdec_fdep_is1_axu_store : std_ulogic; +signal fdec_fdep_is1_axu_ldst_indexed : std_ulogic; +signal fdec_fdep_is1_axu_ldst_tag : std_ulogic_vector(0 to 8); +signal fdec_fdep_is1_axu_ldst_size : std_ulogic_vector(0 to 5); +signal fdec_fdep_is1_axu_ldst_update : std_ulogic; +signal fdec_fdep_is1_axu_ldst_extpid : std_ulogic; +signal fdec_fdep_is1_axu_ldst_forcealign: std_ulogic; +signal fdec_fdep_is1_axu_ldst_forceexcept: std_ulogic; +signal fdec_fdep_is1_axu_mftgpr : std_ulogic; +signal fdec_fdep_is1_axu_mffgpr : std_ulogic; +signal fdec_fdep_is1_axu_movedp : std_ulogic; +signal fdec_fdep_is1_axu_instr_type : std_ulogic_vector(0 to 2); +signal fdec_fdep_is1_match : std_ulogic; +signal fdec_fdep_is1_2ucode : std_ulogic; +signal fdec_fdep_is1_2ucode_type : std_ulogic; +signal fdec_fdep_is1_force_ram : std_ulogic; +signal iu_au_is2_stall : std_ulogic; +signal iu_au_is1_stall_int : std_ulogic; +-- This is a barrier operation that will stop axu issue +signal iu_au_is1_hold : std_ulogic; +signal fdep_fdec_buff_stall : std_ulogic; +signal fdep_fdec_weak_stall : std_ulogic; +-- axu dec signals +signal au_iu_ib1_store : std_ulogic; +signal au_iu_ib1_ldst_size : std_ulogic_vector(0 to 5); +signal au_iu_ib1_ldst_tag : std_ulogic_vector(0 to 8); +signal au_iu_ib1_ldst_ra_v : std_ulogic; +signal au_iu_ib1_ldst_ra : std_ulogic_vector(0 to 6); +signal au_iu_ib1_ldst_rb_v : std_ulogic; +signal au_iu_ib1_ldst_rb : std_ulogic_vector(0 to 6); +signal au_iu_ib1_ldst_dimm : std_ulogic_vector(0 to 15); +signal au_iu_ib1_ldst_indexed : std_ulogic; +signal au_iu_ib1_ldst_update : std_ulogic; +signal au_iu_ib1_ldst_extpid : std_ulogic; +signal au_iu_ib1_ldst_forcealign : std_ulogic; +signal au_iu_ib1_ldst_forceexcept : std_ulogic; +signal au_iu_ib1_mftgpr : std_ulogic; +signal au_iu_ib1_mffgpr : std_ulogic; +signal au_iu_ib1_movedp : std_ulogic; +signal au_iu_ib1_instr_type : std_ulogic_vector(0 to 2); +signal au_iu_ib1_ldst : std_ulogic; +signal au_iu_ib1_ldst_v : std_ulogic; +signal au_iu_i_dec_b : std_ulogic; +signal i_afd_is1_fra_v : std_ulogic; +signal i_afd_is1_frb_v : std_ulogic; +signal i_afd_is1_frc_v : std_ulogic; +signal i_afd_is1_frt_v : std_ulogic; +signal i_afd_is1_prebubble1 : std_ulogic; +signal i_afd_is1_est_bubble3 : std_ulogic; +signal i_afd_is1_cr_writer : std_ulogic; +signal i_afd_is1_fra : std_ulogic_vector(0 to 6); +signal i_afd_is1_frb : std_ulogic_vector(0 to 6); +signal i_afd_is1_frc : std_ulogic_vector(0 to 6); +signal i_afd_is1_frt : std_ulogic_vector(0 to 6); +signal i_afd_is1_instr_v : std_ulogic; +signal i_afd_is1_instr_ldst_v : std_ulogic; +signal i_afd_is1_instr_ld_v : std_ulogic; +signal i_afd_is1_is_ucode : std_ulogic; +signal i_afd_is1_to_ucode : std_ulogic; +signal i_afd_ignore_flush_is1_int : std_ulogic; +signal i_afd_config_iucr : std_ulogic_vector(1 to 7); +signal i_afd_in_ucode_mode_or1d : std_ulogic; +signal i_afd_is1_fra_buf : std_ulogic_vector(1 to 6); +signal i_afd_is1_frb_buf : std_ulogic_vector(1 to 6); +signal i_afd_is1_frc_buf : std_ulogic_vector(1 to 6); +signal i_afd_is1_frt_buf : std_ulogic_vector(1 to 6); +signal i_afd_is1_divsqrt : std_ulogic; +signal i_afd_is1_stall_rep : std_ulogic; +signal i_afd_is1_instr_sto_v : std_ulogic; +-- axu dep signals +signal au_iu_is1_dep_hit : std_ulogic; +signal au_iu_is1_dep_hit_b : std_ulogic; +signal au_iu_is2_axubusy : std_ulogic; +signal au_iu_issue_stall : std_ulogic; +signal ifdp_ex5_fmul_uc_complete : std_ulogic; +signal i_afd_fmul_uc_is1 : std_ulogic; +signal pc_au_ram_mode : std_ulogic; +signal pc_au_ram_thread_v : std_ulogic; +signal fu_dec_debug : std_ulogic_vector(0 to 13); +signal fu_dep_debug : std_ulogic_vector(0 to 23); +-- scan signals +signal siv : std_ulogic_vector(0 to scan_right); +signal sov : std_ulogic_vector(0 to scan_right); +signal pc_iu_func_sl_thold_1 : std_ulogic; +signal pc_iu_func_sl_thold_0 : std_ulogic; +signal pc_iu_func_sl_thold_0_b : std_ulogic; +signal pc_iu_sg_1 : std_ulogic; +signal pc_iu_sg_0 : std_ulogic; +signal forcee : std_ulogic; +signal act_dis : std_ulogic; +signal d_mode : std_ulogic; +signal mpw2_b : std_ulogic; +begin +act_dis <= '0'; +d_mode <= '0'; +mpw2_b <= '1'; +--pass through +iu_au_config_iucr_pt(2 to 4) <= iu_au_config_iucr(2 to 3) & iu_au_config_iucr(5); +---------------------------------------- +-- ibuff instruction source muxing +---------------------------------------- +iu_au_ib1_instr0(0 to 31) <= iu_au_ib1_data(0 to 31); +iu_au_ib1_instr0_ucode_ext(0 to 3) <= iu_au_ib1_data(32 to 35); +iu_au_ib1_instr0_pred_taken_cnt(0 to 1) <= iu_au_ib1_data(36 to 37); +iu_au_ib1_instr0_pred_vld <= iu_au_ib1_data(38); +iu_au_ib1_instr0_error <= iu_au_ib1_data(39 to 41); +iu_au_ib1_instr0_is_ucode <= iu_au_ib1_data(42); +iu_au_ib1_instr0_2ucode <= iu_au_ib1_data(43); +iu_au_ib1_instr0_2ucode_type <= iu_au_ib1_data(44); +iu_au_ib1_instr0_force_ram <= iu_au_ib1_data(45); +iu_au_ib1_instr0_gshare <= iu_au_ib1_data(46 to 49); +ib1_flush <= xu_iu_flush or uc_flush; +is1_flush <= xu_iu_flush or uc_flush; +is2_flush <= xu_iu_flush or uc_flush; +rf0_flush <= xu_iu_flush or uc_flush; +i_axu_is1_dep_hit_b <= au_iu_is1_dep_hit_b; +pc_au_ram_mode <= pc_iu_ram_mode; +pc_au_ram_thread_v <= pc_iu_ram_thread(0 to 1) = slice_id(0 to 1); +iu_fxu_decode0 : entity work.iuq_fxu_decode +generic map(a2mode => a2mode, + regmode => regmode, + expand_type => expand_type) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_iu_func_sl_thold_0_b => pc_iu_func_sl_thold_0_b, + pc_iu_sg_0 => pc_iu_sg_0, + forcee => forcee, + d_mode => d_mode, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + scan_in => siv(scan_dec), + scan_out => sov(scan_dec), + pc_au_ram_mode => pc_au_ram_mode, + pc_au_ram_thread_v => pc_au_ram_thread_v, + spr_dec_mask => spr_dec_mask, + spr_dec_match => spr_dec_match, + fdep_fdec_buff_stall => fdep_fdec_buff_stall, + fdep_fdec_weak_stall => fdep_fdec_weak_stall, + au_iu_i_dec_b => au_iu_i_dec_b, + iu_au_is1_cr_user_v => iu_au_is1_cr_user_v, + iu_au_is0_cr_setter => iu_au_is0_cr_setter, + au_iu_ib1_ldst => au_iu_ib1_ldst, + au_iu_ib1_ldst_v => au_iu_ib1_ldst_v, + au_iu_ib1_store => au_iu_ib1_store, + au_iu_ib1_ldst_size => au_iu_ib1_ldst_size, + au_iu_ib1_ldst_tag => au_iu_ib1_ldst_tag, + au_iu_ib1_ldst_ra => au_iu_ib1_ldst_ra, + au_iu_ib1_ldst_ra_v => au_iu_ib1_ldst_ra_v, + au_iu_ib1_ldst_rb => au_iu_ib1_ldst_rb, + au_iu_ib1_ldst_rb_v => au_iu_ib1_ldst_rb_v, + au_iu_ib1_ldst_dimm => au_iu_ib1_ldst_dimm, + au_iu_ib1_ldst_indexed => au_iu_ib1_ldst_indexed, + au_iu_ib1_ldst_update => au_iu_ib1_ldst_update, + au_iu_ib1_ldst_extpid => au_iu_ib1_ldst_extpid, + au_iu_ib1_ldst_forcealign => au_iu_ib1_ldst_forcealign, + au_iu_ib1_ldst_forceexcept => au_iu_ib1_ldst_forceexcept, + au_iu_ib1_mftgpr => au_iu_ib1_mftgpr, + au_iu_ib1_mffgpr => au_iu_ib1_mffgpr, + au_iu_ib1_movedp => au_iu_ib1_movedp, + au_iu_ib1_instr_type => au_iu_ib1_instr_type, + iu_au_ib1_instr_vld => iu_au_ib1_instr_vld, + iu_au_ib1_ifar => iu_au_ib1_ifar, + iu_au_ib1_instr => iu_au_ib1_instr0, + iu_au_ib1_instr_ucode_ext => iu_au_ib1_instr0_ucode_ext, + iu_au_ib1_instr_pred_vld => iu_au_ib1_instr0_pred_vld, + iu_au_ib1_instr_pred_taken_cnt => iu_au_ib1_instr0_pred_taken_cnt, + iu_au_ib1_instr_gshare => iu_au_ib1_instr0_gshare, + iu_au_ib1_instr_error => iu_au_ib1_instr0_error, + iu_au_ib1_instr_is_ucode => iu_au_ib1_instr0_is_ucode, + iu_au_ib1_instr_2ucode => iu_au_ib1_instr0_2ucode, + iu_au_ib1_instr_2ucode_type => iu_au_ib1_instr0_2ucode_type, + iu_au_ib1_instr_force_ram => iu_au_ib1_instr0_force_ram, + au_iu_is0_to_ucode => au_iu_is0_to_ucode, + au_iu_is0_ucode_only => au_iu_is0_ucode_only, + iu_au_is1_stall => iu_au_is1_stall_int, + xu_iu_ib1_flush => ib1_flush, + fdec_ibuf_stall => fdec_ibuf_stall, + fdec_fdep_is1_vld => fdec_fdep_is1_vld, + fdec_fdep_is1_instr => fdec_fdep_is1_instr, + fdec_fdep_is1_ta_vld => fdec_fdep_is1_ta_vld, + fdec_fdep_is1_ta => fdec_fdep_is1_ta, + fdec_fdep_is1_s1_vld => fdec_fdep_is1_s1_vld, + fdec_fdep_is1_s1 => fdec_fdep_is1_s1, + fdec_fdep_is1_s2_vld => fdec_fdep_is1_s2_vld, + fdec_fdep_is1_s2 => fdec_fdep_is1_s2, + fdec_fdep_is1_s3_vld => fdec_fdep_is1_s3_vld, + fdec_fdep_is1_s3 => fdec_fdep_is1_s3, + fdec_fdep_is1_pred_update => fdec_fdep_is1_pred_update, + fdec_fdep_is1_pred_taken_cnt => fdec_fdep_is1_pred_taken_cnt, + fdec_fdep_is1_gshare => fdec_fdep_is1_gshare, + fdec_fdep_is1_UpdatesLR => fdec_fdep_is1_UpdatesLR, + fdec_fdep_is1_UpdatesCR => fdec_fdep_is1_UpdatesCR, + fdec_fdep_is1_UpdatesCTR => fdec_fdep_is1_UpdatesCTR, + fdec_fdep_is1_UpdatesXER => fdec_fdep_is1_UpdatesXER, + fdec_fdep_is1_UpdatesMSR => fdec_fdep_is1_UpdatesMSR, + fdec_fdep_is1_UpdatesSPR => fdec_fdep_is1_UpdatesSPR, + fdec_fdep_is1_UsesLR => fdec_fdep_is1_UsesLR, + fdec_fdep_is1_UsesCR => fdec_fdep_is1_UsesCR, + fdec_fdep_is1_UsesCTR => fdec_fdep_is1_UsesCTR, + fdec_fdep_is1_UsesXER => fdec_fdep_is1_UsesXER, + fdec_fdep_is1_UsesMSR => fdec_fdep_is1_UsesMSR, + fdec_fdep_is1_UsesSPR => fdec_fdep_is1_UsesSPR, + fdec_fdep_is1_hole_delay => fdec_fdep_is1_hole_delay, + fdec_fdep_is1_ld_vld => fdec_fdep_is1_ld_vld, + fdec_fdep_is1_to_ucode => fdec_fdep_is1_to_ucode, + fdec_fdep_is1_is_ucode => fdec_fdep_is1_is_ucode, + fdec_fdep_is1_ifar => fdec_fdep_is1_ifar, + fdec_fdep_is1_error => fdec_fdep_is1_error, + fdec_fdep_is1_complete => fdec_fdep_is1_complete, + fdec_fdep_is1_axu_ld_or_st => fdec_fdep_is1_axu_ld_or_st, + fdec_fdep_is1_axu_store => fdec_fdep_is1_axu_store, + fdec_fdep_is1_axu_ldst_size => fdec_fdep_is1_axu_ldst_size, + fdec_fdep_is1_axu_ldst_tag => fdec_fdep_is1_axu_ldst_tag, + +fdec_fdep_is1_axu_ldst_indexed => fdec_fdep_is1_axu_ldst_indexed, + fdec_fdep_is1_axu_ldst_update => fdec_fdep_is1_axu_ldst_update, + fdec_fdep_is1_axu_ldst_extpid => fdec_fdep_is1_axu_ldst_extpid, + fdec_fdep_is1_axu_ldst_forcealign => fdec_fdep_is1_axu_ldst_forcealign, + fdec_fdep_is1_axu_ldst_forceexcept => fdec_fdep_is1_axu_ldst_forceexcept, + fdec_fdep_is1_axu_mftgpr => fdec_fdep_is1_axu_mftgpr, + fdec_fdep_is1_axu_mffgpr => fdec_fdep_is1_axu_mffgpr, + fdec_fdep_is1_axu_movedp => fdec_fdep_is1_axu_movedp, + fdec_fdep_is1_axu_instr_type => fdec_fdep_is1_axu_instr_type, + fdec_fdep_is1_2ucode => fdec_fdep_is1_2ucode, + fdec_fdep_is1_2ucode_type => fdec_fdep_is1_2ucode_type, + fdec_fdep_is1_force_ram => fdec_fdep_is1_force_ram, + fdec_fdep_is1_match => fdec_fdep_is1_match +); +iu_fxu_dep0 : entity work.iuq_fxu_dep +generic map(expand_type => expand_type, + regmode => regmode, + lmq_entries => lmq_entries) +port map(vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_iu_func_sl_thold_0_b => pc_iu_func_sl_thold_0_b, + pc_iu_sg_0 => pc_iu_sg_0, + forcee => forcee, + d_mode => d_mode, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + scan_in => siv(scan_dep), + scan_out => sov(scan_dep), + pc_iu_trace_bus_enable => pc_iu_trace_bus_enable, + pc_iu_event_bus_enable => pc_iu_event_bus_enable, + fdep_dbg_data => fdep_dbg_data, + fdep_perf_event => fdep_perf_event, + fdep_fdec_buff_stall => fdep_fdec_buff_stall, + fdep_fdec_weak_stall => fdep_fdec_weak_stall, + fdec_fdep_is1_vld => fdec_fdep_is1_vld, + fdec_fdep_is1_instr => fdec_fdep_is1_instr, + fdec_fdep_is1_ta_vld => fdec_fdep_is1_ta_vld, + fdec_fdep_is1_ta => fdec_fdep_is1_ta, + fdec_fdep_is1_s1_vld => fdec_fdep_is1_s1_vld, + fdec_fdep_is1_s1 => fdec_fdep_is1_s1, + fdec_fdep_is1_s2_vld => fdec_fdep_is1_s2_vld, + fdec_fdep_is1_s2 => fdec_fdep_is1_s2, + fdec_fdep_is1_s3_vld => fdec_fdep_is1_s3_vld, + fdec_fdep_is1_s3 => fdec_fdep_is1_s3, + fdec_fdep_is1_pred_update => fdec_fdep_is1_pred_update, + fdec_fdep_is1_pred_taken_cnt => fdec_fdep_is1_pred_taken_cnt, + fdec_fdep_is1_gshare => fdec_fdep_is1_gshare, + fdec_fdep_is1_UpdatesLR => fdec_fdep_is1_UpdatesLR, + fdec_fdep_is1_UpdatesCR => fdec_fdep_is1_UpdatesCR, + fdec_fdep_is1_UpdatesCTR => fdec_fdep_is1_UpdatesCTR, + fdec_fdep_is1_UpdatesXER => fdec_fdep_is1_UpdatesXER, + fdec_fdep_is1_UpdatesMSR => fdec_fdep_is1_UpdatesMSR, + fdec_fdep_is1_UpdatesSPR => fdec_fdep_is1_UpdatesSPR, + fdec_fdep_is1_UsesLR => fdec_fdep_is1_UsesLR, + fdec_fdep_is1_UsesCR => fdec_fdep_is1_UsesCR, + fdec_fdep_is1_UsesCTR => fdec_fdep_is1_UsesCTR, + fdec_fdep_is1_UsesXER => fdec_fdep_is1_UsesXER, + fdec_fdep_is1_UsesMSR => fdec_fdep_is1_UsesMSR, + fdec_fdep_is1_UsesSPR => fdec_fdep_is1_UsesSPR, + fdec_fdep_is1_hole_delay => fdec_fdep_is1_hole_delay, + fdec_fdep_is1_ld_vld => fdec_fdep_is1_ld_vld, + fdec_fdep_is1_to_ucode => fdec_fdep_is1_to_ucode, + fdec_fdep_is1_is_ucode => fdec_fdep_is1_is_ucode, + fdec_fdep_is1_ifar => fdec_fdep_is1_ifar, + fdec_fdep_is1_error => fdec_fdep_is1_error, + fdec_fdep_is1_complete => fdec_fdep_is1_complete, + fdec_fdep_is1_axu_ld_or_st => fdec_fdep_is1_axu_ld_or_st, + fdec_fdep_is1_axu_store => fdec_fdep_is1_axu_store, + fdec_fdep_is1_axu_ldst_size => fdec_fdep_is1_axu_ldst_size, + fdec_fdep_is1_axu_ldst_tag => fdec_fdep_is1_axu_ldst_tag, + +fdec_fdep_is1_axu_ldst_indexed => fdec_fdep_is1_axu_ldst_indexed, + fdec_fdep_is1_axu_ldst_update => fdec_fdep_is1_axu_ldst_update, + fdec_fdep_is1_axu_ldst_extpid => fdec_fdep_is1_axu_ldst_extpid, + fdec_fdep_is1_axu_ldst_forcealign => fdec_fdep_is1_axu_ldst_forcealign, + fdec_fdep_is1_axu_ldst_forceexcept => fdec_fdep_is1_axu_ldst_forceexcept, + fdec_fdep_is1_axu_mftgpr => fdec_fdep_is1_axu_mftgpr, + fdec_fdep_is1_axu_mffgpr => fdec_fdep_is1_axu_mffgpr, + fdec_fdep_is1_axu_movedp => fdec_fdep_is1_axu_movedp, + fdec_fdep_is1_axu_instr_type => fdec_fdep_is1_axu_instr_type, + fdec_fdep_is1_match => fdec_fdep_is1_match, + fdec_fdep_is1_2ucode => fdec_fdep_is1_2ucode, + fdec_fdep_is1_2ucode_type => fdec_fdep_is1_2ucode_type, + fdec_fdep_is1_force_ram => fdec_fdep_is1_force_ram, + fdep_fiss_is2_instr => fdep_fiss_is2_instr, + fdep_fiss_is2_ta_vld => fdep_fiss_is2_ta_vld, + fdep_fiss_is2_ta => fdep_fiss_is2_ta, + fdep_fiss_is2_s1_vld => fdep_fiss_is2_s1_vld, + fdep_fiss_is2_s1 => fdep_fiss_is2_s1, + fdep_fiss_is2_s2_vld => fdep_fiss_is2_s2_vld, + fdep_fiss_is2_s2 => fdep_fiss_is2_s2, + fdep_fiss_is2_s3_vld => fdep_fiss_is2_s3_vld, + fdep_fiss_is2_s3 => fdep_fiss_is2_s3, + fdep_fiss_is2_pred_update => fdep_fiss_is2_pred_update, + fdep_fiss_is2_pred_taken_cnt => fdep_fiss_is2_pred_taken_cnt, + fdep_fiss_is2_gshare => fdep_fiss_is2_gshare, + fdep_fiss_is2_ifar => fdep_fiss_is2_ifar, + fdep_fiss_is2_error => fdep_fiss_is2_error, + fdep_fiss_is2_axu_ld_or_st => fdep_fiss_is2_axu_ld_or_st, + fdep_fiss_is2_axu_store => fdep_fiss_is2_axu_store, + fdep_fiss_is2_axu_ldst_size => fdep_fiss_is2_axu_ldst_size, + fdep_fiss_is2_axu_ldst_tag => fdep_fiss_is2_axu_ldst_tag, + +fdep_fiss_is2_axu_ldst_indexed => fdep_fiss_is2_axu_ldst_indexed, + fdep_fiss_is2_axu_ldst_update => fdep_fiss_is2_axu_ldst_update, + fdep_fiss_is2_axu_ldst_extpid => fdep_fiss_is2_axu_ldst_extpid, + fdep_fiss_is2_axu_ldst_forcealign => fdep_fiss_is2_axu_ldst_forcealign, + fdep_fiss_is2_axu_ldst_forceexcept => fdep_fiss_is2_axu_ldst_forceexcept, + fdep_fiss_is2_axu_mftgpr => fdep_fiss_is2_axu_mftgpr, + fdep_fiss_is2_axu_mffgpr => fdep_fiss_is2_axu_mffgpr, + fdep_fiss_is2_axu_movedp => fdep_fiss_is2_axu_movedp, + fdep_fiss_is2_axu_instr_type => fdep_fiss_is2_axu_instr_type, + fdep_fiss_is2_match => fdep_fiss_is2_match, + fdep_fiss_is2_2ucode => fdep_fiss_is2_2ucode, + fdep_fiss_is2_2ucode_type => fdep_fiss_is2_2ucode_type, + fdep_fiss_is2early_vld => fdep_fiss_is2early_vld, + fdep_fiss_is1_xu_dep_hit_b => fdep_fiss_is1_xu_dep_hit_b, + fdep_fiss_is2_hole_delay => fdep_fiss_is2_hole_delay, + fdep_fiss_is2_to_ucode => fdep_fiss_is2_to_ucode, + fdep_fiss_is2_is_ucode => fdep_fiss_is2_is_ucode, + fiss_fdep_is2_take => fiss_fdep_is2_take, + i_afd_is1_instr_v => i_afd_is1_instr_v, + au_iu_issue_stall => au_iu_issue_stall, + iu_au_is2_stall => iu_au_is2_stall, + au_iu_is1_dep_hit => au_iu_is1_dep_hit, + au_iu_is1_dep_hit_b => au_iu_is1_dep_hit_b, + au_iu_is2_axubusy => au_iu_is2_axubusy, + iu_au_is1_hold => iu_au_is1_hold, + iu_au_is1_stall => iu_au_is1_stall_int, + xu_iu_slowspr_done => xu_iu_slowspr_done, + xu_iu_multdiv_done => xu_iu_multdiv_done, + xu_iu_loadmiss_vld => xu_iu_ex5_loadmiss_vld, + xu_iu_loadmiss_qentry => xu_iu_ex5_loadmiss_qentry, + xu_iu_loadmiss_target => xu_iu_ex5_loadmiss_target(1 to 6), + xu_iu_loadmiss_target_type => xu_iu_ex5_loadmiss_target_type(0), + xu_iu_complete_vld => xu_iu_complete_vld, + xu_iu_complete_qentry => xu_iu_complete_qentry, + xu_iu_complete_target_type => xu_iu_complete_target_type(0), + ic_fdep_load_quiesce => ic_fdep_load_quiesce, + iu_xu_quiesce => iu_xu_quiesce, + xu_iu_membar_tid => xu_iu_membar_tid, + xu_iu_set_barr_tid => xu_iu_set_barr_tid, + xu_iu_larx_done_tid => xu_iu_larx_done_tid, + an_ac_sync_ack => an_ac_sync_ack, + ic_fdep_icbi_ack => ic_fdep_icbi_ack, + an_ac_stcx_complete => an_ac_stcx_complete, + mm_iu_barrier_done => mm_iu_barrier_done, + spr_fdep_ll_hold => spr_fdep_ll_hold, + xu_iu_spr_ccr2_en_dcr => xu_iu_spr_ccr2_en_dcr, + xu_iu_is1_flush => is1_flush, + xu_iu_is2_flush => is2_flush, + xu_iu_rf0_flush => rf0_flush, + xu_iu_rf1_flush => xu_iu_rf1_flush, + xu_iu_ex1_flush => xu_iu_ex1_flush, + xu_iu_ex2_flush => xu_iu_ex2_flush, + xu_iu_ex3_flush => xu_iu_ex3_flush, + xu_iu_ex4_flush => xu_iu_ex4_flush, + xu_iu_ex5_flush => xu_iu_ex5_flush, + xu_iu_single_instr_mode => xu_iu_single_instr_mode); +dec0: entity work.iuq_axu_fu_dec +generic map(expand_type => expand_type) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + i_dec_si => siv(scan_axu_dec), + i_dec_so => sov(scan_axu_dec), + pc_iu_func_sl_thold_0_b => pc_iu_func_sl_thold_0_b, + pc_iu_sg_0 => pc_iu_sg_0, + forcee => forcee, + d_mode => d_mode, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + pc_au_ram_mode => pc_au_ram_mode, + pc_au_ram_thread_v => pc_au_ram_thread_v, + iu_au_ucode_restart => xu_iu_ucode_restart, + ifdp_ex5_fmul_uc_complete => ifdp_ex5_fmul_uc_complete, + i_afd_fmul_uc_is1 => i_afd_fmul_uc_is1, + iu_au_config_iucr => iu_au_config_iucr, + iu_au_is0_instr_v => iu_au_ib1_instr_vld, + iu_au_is0_instr => iu_au_ib1_instr0, + iu_au_is0_ucode_ext => iu_au_ib1_instr0_ucode_ext, + iu_au_is0_cr_setter => iu_au_is0_cr_setter, + iu_au_is1_stall => iu_au_is1_stall_int, + iu_au_is0_flush => ib1_flush, + iu_au_is1_flush => is1_flush, + au_iu_is0_i_dec_b => au_iu_i_dec_b, + au_iu_is0_to_ucode => au_iu_is0_to_ucode, + au_iu_is0_ucode_only => au_iu_is0_ucode_only, + iu_au_is0_is_ucode => iu_au_ib1_instr0_is_ucode, + iu_au_is0_2ucode => iu_au_ib1_instr0_2ucode, + au_iu_is0_ldst => au_iu_ib1_ldst, + au_iu_is0_ldst_v => au_iu_ib1_ldst_v, + au_iu_is0_st_v => au_iu_ib1_store, + au_iu_is0_ldst_size => au_iu_ib1_ldst_size, + au_iu_is0_ldst_tag => au_iu_ib1_ldst_tag, + au_iu_is0_ldst_ra => au_iu_ib1_ldst_ra, + au_iu_is0_ldst_ra_v => au_iu_ib1_ldst_ra_v, + au_iu_is0_ldst_rb => au_iu_ib1_ldst_rb, + au_iu_is0_ldst_rb_v => au_iu_ib1_ldst_rb_v, + au_iu_is0_ldst_dimm => au_iu_ib1_ldst_dimm, + au_iu_is0_ldst_indexed => au_iu_ib1_ldst_indexed, + au_iu_is0_ldst_update => au_iu_ib1_ldst_update, + au_iu_is0_ldst_extpid => au_iu_ib1_ldst_extpid, + au_iu_is0_ldst_forcealign => au_iu_ib1_ldst_forcealign, + au_iu_is0_ldst_forceexcept => au_iu_ib1_ldst_forceexcept, + au_iu_is0_mftgpr => au_iu_ib1_mftgpr, + au_iu_is0_mffgpr => au_iu_ib1_mffgpr, + au_iu_is0_movedp => au_iu_ib1_movedp, + au_iu_is0_instr_type => au_iu_ib1_instr_type, + i_afd_is1_cr_setter => i_afd_is1_cr_setter, + i_afd_is1_is_ucode => i_afd_is1_is_ucode, + i_afd_is1_to_ucode => i_afd_is1_to_ucode, + i_afd_is1_fra_v => i_afd_is1_fra_v, + i_afd_is1_frb_v => i_afd_is1_frb_v, + i_afd_is1_frc_v => i_afd_is1_frc_v, + i_afd_is1_frt_v => i_afd_is1_frt_v, + i_afd_is1_prebubble1 => i_afd_is1_prebubble1, + i_afd_is1_est_bubble3 => i_afd_is1_est_bubble3, + i_afd_is1_cr_writer => i_afd_is1_cr_writer, + i_afd_is1_fra => i_afd_is1_fra, + i_afd_is1_frb => i_afd_is1_frb, + i_afd_is1_frc => i_afd_is1_frc, + i_afd_is1_frt => i_afd_is1_frt, + i_afd_is1_instr_v => i_afd_is1_instr_v, + i_afd_is1_instr_ldst_v => i_afd_is1_instr_ldst_v, + i_afd_is1_instr_ld_v => i_afd_is1_instr_ld_v, + i_afd_ignore_flush_is1 => i_afd_ignore_flush_is1_int, + i_afd_in_ucode_mode_or1d => i_afd_in_ucode_mode_or1d, + i_afd_is1_fra_buf => i_afd_is1_fra_buf, + i_afd_is1_frb_buf => i_afd_is1_frb_buf, + i_afd_is1_frc_buf => i_afd_is1_frc_buf, + i_afd_is1_frt_buf => i_afd_is1_frt_buf, + i_afd_is1_divsqrt => i_afd_is1_divsqrt, + i_afd_is1_stall_rep => i_afd_is1_stall_rep, + i_afd_is1_instr_sto_v => i_afd_is1_instr_sto_v, + i_afd_config_iucr => i_afd_config_iucr, + fu_dec_debug => fu_dec_debug + ); +dep0: entity work.iuq_axu_fu_dep +generic map(expand_type => expand_type, + lmq_entries => lmq_entries) +port map ( + vdd => vdd, + gnd => gnd, + nclk => nclk, + i_dep_si => siv(scan_axu_dep), + i_dep_so => sov(scan_axu_dep), + pc_iu_func_sl_thold_0_b => pc_iu_func_sl_thold_0_b, + pc_iu_sg_0 => pc_iu_sg_0, + forcee => forcee, + d_mode => d_mode, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + ifdp_ex5_fmul_uc_complete => ifdp_ex5_fmul_uc_complete, + i_afd_fmul_uc_is1 => i_afd_fmul_uc_is1, + iu_fu_ex2_n_flush => iu_fu_ex2_n_flush, + fu_iu_uc_special => fu_iu_uc_special, + i_afd_is1_cr_setter => i_afd_is1_cr_setter, + i_afd_is1_is_ucode => i_afd_is1_is_ucode, + i_afd_is1_to_ucode => i_afd_is1_to_ucode, + i_afd_is2_is_ucode => i_afd_is2_is_ucode, + i_afd_is1_instr_v => i_afd_is1_instr_v, + i_afd_is1_instr => fdec_fdep_is1_instr(26 to 31), + i_afd_is1_fra_v => i_afd_is1_fra_v, + i_afd_is1_frb_v => i_afd_is1_frb_v, + i_afd_is1_frc_v => i_afd_is1_frc_v, + i_afd_is1_frt_v => i_afd_is1_frt_v, + i_afd_is1_prebubble1 => i_afd_is1_prebubble1, + i_afd_is1_est_bubble3 => i_afd_is1_est_bubble3, + iu_au_is1_cr_user_v => iu_au_is1_cr_user_v, + i_afd_is1_cr_writer => i_afd_is1_cr_writer, + i_afd_is1_fra => i_afd_is1_fra, + i_afd_is1_frb => i_afd_is1_frb, + i_afd_is1_frc => i_afd_is1_frc, + i_afd_is1_frt => i_afd_is1_frt, + i_afd_is1_ifar => fdec_fdep_is1_ifar(56 to 61), + i_afd_is1_instr_ldst_v => i_afd_is1_instr_ldst_v, + i_afd_is1_instr_ld_v => i_afd_is1_instr_ld_v, + i_afi_is2_take => i_afi_is2_take, + xu_au_loadmiss_vld => xu_iu_ex4_loadmiss_vld, + xu_au_loadmiss_qentry => xu_iu_ex4_loadmiss_qentry, + xu_au_loadmiss_target => xu_iu_ex4_loadmiss_target, + xu_au_loadmiss_target_type => xu_iu_ex4_loadmiss_target_type, + xu_au_loadmiss_complete_vld => xu_iu_complete_vld, + xu_au_loadmiss_complete_qentry => xu_iu_complete_qentry, + xu_au_loadmiss_complete_type => xu_iu_complete_target_type, + iu_au_is1_hold => iu_au_is1_hold, + iu_au_is1_instr_match => fdec_fdep_is1_match, + iu_au_is2_stall => iu_au_is2_stall, + xu_iu_is2_flush => xu_iu_flush, + iu_au_is1_flush => is1_flush, + iu_au_is2_flush => is2_flush, + iu_au_rf0_flush => xu_iu_flush, + iu_au_rf1_flush => xu_iu_rf1_flush, + iu_au_ex1_flush => xu_iu_ex1_flush, + iu_au_ex2_flush => xu_iu_ex2_flush, + iu_au_ex3_flush => xu_iu_ex3_flush, + iu_au_ex4_flush => xu_iu_ex4_flush, + iu_au_ex5_flush => xu_iu_ex5_flush, + au_iu_is1_dep_hit => au_iu_is1_dep_hit, + au_iu_is2_issue_stall => au_iu_issue_stall, + i_axu_is2_instr_v => i_axu_is2_instr_v, + i_axu_is1_early_v => i_axu_is1_early_v, + au_iu_is1_dep_hit_b => au_iu_is1_dep_hit_b, + i_axu_is2_instr_match => i_axu_is2_instr_match, + + i_axu_is2_fra => i_axu_is2_fra, + i_axu_is2_frb => i_axu_is2_frb, + i_axu_is2_frc => i_axu_is2_frc, + i_axu_is2_frt => i_axu_is2_frt, + i_axu_is2_fra_v => i_axu_is2_fra_v, + i_axu_is2_frb_v => i_axu_is2_frb_v, + i_axu_is2_frc_v => i_axu_is2_frc_v, + ifdp_is2_est_bubble3 => ifdp_is2_est_bubble3, + ifdp_is2_bypsel => ifdp_is2_bypsel, + i_afd_ignore_flush_is1 => i_afd_ignore_flush_is1_int, + i_afd_ignore_flush_is2 => i_afd_ignore_flush_is2, + au_iu_is2_axubusy => au_iu_is2_axubusy, + i_afd_in_ucode_mode_or1d => i_afd_in_ucode_mode_or1d, + i_afd_in_ucode_mode_or1d_b => i_afd_in_ucode_mode_or1d_b, + i_afd_is1_fra_buf => i_afd_is1_fra_buf, + i_afd_is1_frb_buf => i_afd_is1_frb_buf, + i_afd_is1_frc_buf => i_afd_is1_frc_buf, + i_afd_is1_frt_buf => i_afd_is1_frt_buf, + i_afd_is1_divsqrt => i_afd_is1_divsqrt, + i_afd_is1_stall_rep => i_afd_is1_stall_rep, + i_afd_is1_instr_sto_v => i_afd_is1_instr_sto_v, + i_afd_config_iucr => i_afd_config_iucr, + fu_dep_debug => fu_dep_debug + ); +------------------------------------------------- +-- debug bus +------------------------------------------------- +axu_dbg_data(0 to 37) <= fu_dec_debug(0 to 13) & fu_dep_debug(0 to 23); +------------------------------------------------- +-- pervasive +------------------------------------------------- +perv_2to1_reg: tri_plat + generic map (width => 2, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_iu_func_sl_thold_2, + din(1) => pc_iu_sg_2, + q(0) => pc_iu_func_sl_thold_1, + q(1) => pc_iu_sg_1); +perv_1to0_reg: tri_plat + generic map (width => 2, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_iu_func_sl_thold_1, + din(1) => pc_iu_sg_1, + q(0) => pc_iu_func_sl_thold_0, + q(1) => pc_iu_sg_0); +perv_lcbor: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_b, + thold => pc_iu_func_sl_thold_0, + sg => pc_iu_sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => pc_iu_func_sl_thold_0_b); +siv <= scan_in & sov(0 to scan_right-1); +scan_out <= sov(scan_right) and an_ac_scan_dis_dc_b; +end iuq_slice; diff --git a/rel/src/vhdl/work/iuq_slice_wrap.vhdl b/rel/src/vhdl/work/iuq_slice_wrap.vhdl new file mode 100644 index 0000000..9d67ffc --- /dev/null +++ b/rel/src/vhdl/work/iuq_slice_wrap.vhdl @@ -0,0 +1,1325 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +--******************************************************************** +--* +--* TITLE: Instruction slice wrapper +--* +--* NAME: iuq_slice_wrap.vhdl +--* +--********************************************************************* + +library ieee; +use ieee.std_logic_1164.all; +library support; +use support.power_logic_pkg.all; +library work; +use work.iuq_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity iuq_slice_wrap is + generic(expand_type : integer := 2; + fpr_addr_width : integer := 5; + regmode : integer := 6; + a2mode : integer := 1; + lmq_entries : integer := 8); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + pc_iu_func_sl_thold_2 : in std_ulogic_vector(0 to 3); + pc_iu_sg_2 : in std_ulogic_vector(0 to 3); + clkoff_b : in std_ulogic_vector(0 to 3); + an_ac_scan_dis_dc_b : in std_ulogic_vector(0 to 3); + tc_ac_ccflush_dc : in std_ulogic; + delay_lclkr : in std_ulogic_vector(9 to 14); + mpw1_b : in std_ulogic_vector(9 to 14); + + iuq_s0_scan_in : in std_ulogic; + iuq_s0_scan_out : out std_ulogic; + iuq_s1_scan_in : in std_ulogic; + iuq_s1_scan_out : out std_ulogic; + iuq_s2_scan_in : in std_ulogic; + iuq_s2_scan_out : out std_ulogic; + iuq_s3_scan_in : in std_ulogic; + iuq_s3_scan_out : out std_ulogic; + pc_iu_ram_mode : in std_ulogic; + pc_iu_ram_thread : in std_ulogic_vector(0 to 1); + pc_iu_trace_bus_enable : in std_ulogic; + pc_iu_event_bus_enable : in std_ulogic; + fdep_dbg_data : out std_ulogic_vector(0 to 87); + fdep_perf_event_t0 : out std_ulogic_vector(0 to 11); + fdep_perf_event_t1 : out std_ulogic_vector(0 to 11); + fdep_perf_event_t2 : out std_ulogic_vector(0 to 11); + fdep_perf_event_t3 : out std_ulogic_vector(0 to 11); + iu_au_config_iucr_t0 : in std_ulogic_vector(0 to 7); + iu_au_config_iucr_t1 : in std_ulogic_vector(0 to 7); + iu_au_config_iucr_t2 : in std_ulogic_vector(0 to 7); + iu_au_config_iucr_t3 : in std_ulogic_vector(0 to 7); + spr_dec_mask_t0 : in std_ulogic_vector(0 to 31); + spr_dec_mask_t1 : in std_ulogic_vector(0 to 31); + spr_dec_mask_t2 : in std_ulogic_vector(0 to 31); + spr_dec_mask_t3 : in std_ulogic_vector(0 to 31); + spr_dec_match_t0 : in std_ulogic_vector(0 to 31); + spr_dec_match_t1 : in std_ulogic_vector(0 to 31); + spr_dec_match_t2 : in std_ulogic_vector(0 to 31); + spr_dec_match_t3 : in std_ulogic_vector(0 to 31); + uc_flush_tid : in std_ulogic_vector(0 to 3); + xu_iu_flush : in std_ulogic_vector(0 to 3); + xu_rf1_flush : in std_ulogic_vector(0 to 3); + xu_ex1_flush : in std_ulogic_vector(0 to 3); + xu_ex2_flush : in std_ulogic_vector(0 to 3); + xu_ex3_flush : in std_ulogic_vector(0 to 3); + xu_ex4_flush : in std_ulogic_vector(0 to 3); + xu_ex5_flush : in std_ulogic_vector(0 to 3); + fdec_ibuf_stall_t0 : out std_ulogic; + fdec_ibuf_stall_t1 : out std_ulogic; + fdec_ibuf_stall_t2 : out std_ulogic; + fdec_ibuf_stall_t3 : out std_ulogic; + iu_au_ib1_instr_vld_t0 : in std_ulogic; + iu_au_ib1_instr_vld_t1 : in std_ulogic; + iu_au_ib1_instr_vld_t2 : in std_ulogic; + iu_au_ib1_instr_vld_t3 : in std_ulogic; + iu_au_ib1_ifar_t0 : in EFF_IFAR; + iu_au_ib1_ifar_t1 : in EFF_IFAR; + iu_au_ib1_ifar_t2 : in EFF_IFAR; + iu_au_ib1_ifar_t3 : in EFF_IFAR; + iu_au_ib1_data_t0 : in std_ulogic_vector(0 to 49); + iu_au_ib1_data_t1 : in std_ulogic_vector(0 to 49); + iu_au_ib1_data_t2 : in std_ulogic_vector(0 to 49); + iu_au_ib1_data_t3 : in std_ulogic_vector(0 to 49); + xu_iu_ucode_restart : in std_ulogic_vector(0 to 3); + xu_iu_slowspr_done : in std_ulogic_vector(0 to 3); + xu_iu_multdiv_done : in std_ulogic_vector(0 to 3); + xu_iu_ex4_loadmiss_tid : in std_ulogic_vector(0 to 3); + xu_iu_ex4_loadmiss_qentry : in std_ulogic_vector(0 to lmq_entries-1); + xu_iu_ex4_loadmiss_target : in std_ulogic_vector(0 to 8); + xu_iu_ex4_loadmiss_target_type : in std_ulogic_vector(0 to 1); + xu_iu_ex5_loadmiss_tid : in std_ulogic_vector(0 to 3); + xu_iu_ex5_loadmiss_qentry : in std_ulogic_vector(0 to lmq_entries-1); + xu_iu_ex5_loadmiss_target : in std_ulogic_vector(1 to 6); + xu_iu_ex5_loadmiss_target_type : in std_ulogic_vector(0 to 0); + xu_iu_complete_tid : in std_ulogic_vector(0 to 3); + xu_iu_complete_qentry : in std_ulogic_vector(0 to lmq_entries-1); + xu_iu_complete_target_type : in std_ulogic_vector(0 to 1); + ic_fdep_load_quiesce : in std_ulogic_vector(0 to 3); + iu_xu_quiesce : out std_ulogic_vector(0 to 3); + xu_iu_membar_tid : in std_ulogic_vector(0 to 3); + xu_iu_set_barr_tid : in std_ulogic_vector(0 to 3); + xu_iu_larx_done_tid : in std_ulogic_vector(0 to 3); + an_ac_sync_ack : in std_ulogic_vector(0 to 3); + ic_fdep_icbi_ack : in std_ulogic_vector(0 to 3); + an_ac_stcx_complete : in std_ulogic_vector(0 to 3); + mm_iu_barrier_done : in std_ulogic_vector(0 to 3); + spr_fdep_ll_hold_t0 : in std_ulogic; + spr_fdep_ll_hold_t1 : in std_ulogic; + spr_fdep_ll_hold_t2 : in std_ulogic; + spr_fdep_ll_hold_t3 : in std_ulogic; + xu_iu_spr_ccr2_en_dcr : in std_ulogic; + xu_iu_single_instr_mode : in std_ulogic_vector(0 to 3); + fu_iu_uc_special : in std_ulogic_vector(0 to 3); + iu_fu_ex2_n_flush : out std_ulogic_vector(0 to 3); + axu_dbg_data_t0 : out std_ulogic_vector(0 to 37); + axu_dbg_data_t1 : out std_ulogic_vector(0 to 37); + axu_dbg_data_t2 : out std_ulogic_vector(0 to 37); + axu_dbg_data_t3 : out std_ulogic_vector(0 to 37); + + iuq_fi_scan_in : in std_ulogic; + iuq_fi_scan_out : out std_ulogic; + fiss_dbg_data : out std_ulogic_vector(0 to 87); + fiss_perf_event_t0 : out std_ulogic_vector(0 to 7); + fiss_perf_event_t1 : out std_ulogic_vector(0 to 7); + fiss_perf_event_t2 : out std_ulogic_vector(0 to 7); + fiss_perf_event_t3 : out std_ulogic_vector(0 to 7); + xu_iu_need_hole : in std_ulogic; + xu_iu_xucr0_rel : in std_ulogic; + an_ac_reld_data_vld_clone : in std_ulogic; + an_ac_reld_core_tag_clone : in std_ulogic_vector(1 to 4); + an_ac_reld_ditc_clone : in std_ulogic; + an_ac_reld_data_coming_clone : in std_ulogic; + an_ac_back_inv : in std_ulogic; + an_ac_back_inv_target : in std_ulogic_vector(1 to 1); + fiss_uc_is2_ucode_vld : out std_ulogic; + spr_issue_high_mask : in std_ulogic_vector(0 to 3); + spr_issue_med_mask : in std_ulogic_vector(0 to 3); + spr_fiss_count0_max : in std_ulogic_vector(0 to 5); + spr_fiss_count1_max : in std_ulogic_vector(0 to 5); + spr_fiss_count2_max : in std_ulogic_vector(0 to 5); + spr_fiss_count3_max : in std_ulogic_vector(0 to 5); + spr_fiss_pri_rand : in std_ulogic_vector(0 to 4); + spr_fiss_pri_rand_always : in std_ulogic; + spr_fiss_pri_rand_flush : in std_ulogic; + xu_iu_ex5_ppc_cpl : in std_ulogic_vector(0 to 3); + iu_xu_is2_vld_internal : out std_ulogic; + iu_xu_is2_tid_internal : out std_ulogic_vector(0 to 3); + iu_xu_is2_instr_internal : out std_ulogic_vector(0 to 31); + iu_xu_is2_ta_vld : out std_ulogic; + iu_xu_is2_ta : out std_ulogic_vector(0 to 5); + iu_xu_is2_s1_vld : out std_ulogic; + iu_xu_is2_s1 : out std_ulogic_vector(0 to 5); + iu_xu_is2_s2_vld : out std_ulogic; + iu_xu_is2_s2 : out std_ulogic_vector(0 to 5); + iu_xu_is2_s3_vld : out std_ulogic; + iu_xu_is2_s3 : out std_ulogic_vector(0 to 5); + iu_xu_is2_pred_update_internal : out std_ulogic; + iu_xu_is2_pred_taken_cnt_internal : out std_ulogic_vector(0 to 1); + iu_xu_is2_gshare : out std_ulogic_vector(0 to 3); + iu_xu_is2_ifar_internal : out eff_ifar; + iu_xu_is2_error_internal : out std_ulogic_vector(0 to 2); + iu_xu_is2_is_ucode : out std_ulogic; + iu_xu_is2_axu_ld_or_st : out std_ulogic; + iu_xu_is2_axu_store_internal : out std_ulogic; + iu_xu_is2_axu_ldst_indexed : out std_ulogic; + iu_xu_is2_axu_ldst_tag : out std_ulogic_vector(0 to 8); + iu_xu_is2_axu_ldst_size : out std_ulogic_vector(0 to 5); + iu_xu_is2_axu_ldst_update : out std_ulogic; + iu_xu_is2_axu_ldst_extpid : out std_ulogic; + iu_xu_is2_axu_ldst_forcealign : out std_ulogic; + iu_xu_is2_axu_ldst_forceexcept : out std_ulogic; + iu_xu_is2_axu_mftgpr : out std_ulogic; + iu_xu_is2_axu_mffgpr : out std_ulogic; + iu_xu_is2_axu_movedp : out std_ulogic; + iu_xu_is2_axu_instr_type : out std_ulogic_vector(0 to 2); + iu_xu_is2_match : out std_ulogic; + fiss_uc_is2_2ucode : out std_ulogic; + fiss_uc_is2_2ucode_type : out std_ulogic; + iu_fu_rf0_str_val : out std_ulogic; + iu_fu_rf0_ldst_val : out std_ulogic; + iu_fu_rf0_ldst_tid : out std_ulogic_vector(0 to 1); + iu_fu_rf0_ldst_tag : out std_ulogic_vector(0 to 8); + + iuq_ai_scan_in : in std_ulogic; + iuq_ai_scan_out : out std_ulogic; + iu_fu_is2_tid_decode : out std_ulogic_vector(0 to 3); + iu_fu_rf0_instr_match : out std_ulogic; + iu_fu_rf0_instr : out std_ulogic_vector(0 to 31); + iu_fu_rf0_instr_v : out std_ulogic; + iu_fu_rf0_is_ucode : out std_ulogic; + iu_fu_rf0_fra : out std_ulogic_vector(0 to 6); + iu_fu_rf0_frb : out std_ulogic_vector(0 to 6); + iu_fu_rf0_frc : out std_ulogic_vector(0 to 6); + iu_fu_rf0_frt : out std_ulogic_vector(0 to 6); + iu_fu_rf0_fra_v : out std_ulogic; + iu_fu_rf0_frb_v : out std_ulogic; + iu_fu_rf0_frc_v : out std_ulogic; + iu_fu_rf0_ucfmul : out std_ulogic; + fu_iss_dbg_data : out std_ulogic_vector(0 to 23); + iu_fu_rf0_tid : out std_ulogic_vector(0 to 1); + iu_fu_rf0_bypsel : out std_ulogic_vector(0 to 5); + iu_fu_rf0_ifar : out EFF_IFAR + +); +end iuq_slice_wrap; +architecture iuq_slice_wrap of iuq_slice_wrap is +-- FXU Issue +signal fiss_fdep_is2_take0 : std_ulogic; +signal fdep_fiss_t0_is2_instr : std_ulogic_vector(0 to 31); +signal fdep_fiss_t0_is2_ta_vld : std_ulogic; +signal fdep_fiss_t0_is2_ta : std_ulogic_vector(0 to 5); +signal fdep_fiss_t0_is2_s1_vld : std_ulogic; +signal fdep_fiss_t0_is2_s1 : std_ulogic_vector(0 to 5); +signal fdep_fiss_t0_is2_s2_vld : std_ulogic; +signal fdep_fiss_t0_is2_s2 : std_ulogic_vector(0 to 5); +signal fdep_fiss_t0_is2_s3_vld : std_ulogic; +signal fdep_fiss_t0_is2_s3 : std_ulogic_vector(0 to 5); +signal fdep_fiss_t0_is2_pred_update : std_ulogic; +signal fdep_fiss_t0_is2_pred_taken_cnt : std_ulogic_vector(0 to 1); +signal fdep_fiss_t0_is2_gshare : std_ulogic_vector(0 to 3); +signal fdep_fiss_t0_is2_ifar : eff_ifar; +signal fdep_fiss_t0_is2_error : std_ulogic_vector(0 to 2); +signal fdep_fiss_t0_is2_axu_ld_or_st : std_ulogic; +signal fdep_fiss_t0_is2_axu_store : std_ulogic; +signal fdep_fiss_t0_is2_axu_ldst_size : std_ulogic_vector(0 to 5); +signal fdep_fiss_t0_is2_axu_ldst_tag : std_ulogic_vector(0 to 8); +signal fdep_fiss_t0_is2_axu_ldst_indexed : std_ulogic; +signal fdep_fiss_t0_is2_axu_ldst_update : std_ulogic; +signal fdep_fiss_t0_is2_axu_ldst_extpid : std_ulogic; +signal fdep_fiss_t0_is2_axu_ldst_forcealign : std_ulogic; +signal fdep_fiss_t0_is2_axu_ldst_forceexcept : std_ulogic; +signal fdep_fiss_t0_is2_axu_mftgpr : std_ulogic; +signal fdep_fiss_t0_is2_axu_mffgpr : std_ulogic; +signal fdep_fiss_t0_is2_axu_movedp : std_ulogic; +signal fdep_fiss_t0_is2_axu_instr_type : std_ulogic_vector(0 to 2); +signal fdep_fiss_t0_is2_match : std_ulogic; +signal fdep_fiss_t0_is2_2ucode : std_ulogic; +signal fdep_fiss_t0_is2_2ucode_type : std_ulogic; +signal fdep_fiss_t0_is2early_vld : std_ulogic; +signal fdep_fiss_t0_is1_xu_dep_hit_b : std_ulogic; +signal fdep_fiss_t0_is2_hole_delay : std_ulogic_vector(0 to 2); +signal fdep_fiss_t0_is2_to_ucode : std_ulogic; +signal fdep_fiss_t0_is2_is_ucode : std_ulogic; +signal fiss_fdep_is2_take1 : std_ulogic; +signal fdep_fiss_t1_is2_instr : std_ulogic_vector(0 to 31); +signal fdep_fiss_t1_is2_ta_vld : std_ulogic; +signal fdep_fiss_t1_is2_ta : std_ulogic_vector(0 to 5); +signal fdep_fiss_t1_is2_s1_vld : std_ulogic; +signal fdep_fiss_t1_is2_s1 : std_ulogic_vector(0 to 5); +signal fdep_fiss_t1_is2_s2_vld : std_ulogic; +signal fdep_fiss_t1_is2_s2 : std_ulogic_vector(0 to 5); +signal fdep_fiss_t1_is2_s3_vld : std_ulogic; +signal fdep_fiss_t1_is2_s3 : std_ulogic_vector(0 to 5); +signal fdep_fiss_t1_is2_pred_update : std_ulogic; +signal fdep_fiss_t1_is2_pred_taken_cnt : std_ulogic_vector(0 to 1); +signal fdep_fiss_t1_is2_gshare : std_ulogic_vector(0 to 3); +signal fdep_fiss_t1_is2_ifar : eff_ifar; +signal fdep_fiss_t1_is2_error : std_ulogic_vector(0 to 2); +signal fdep_fiss_t1_is2_axu_ld_or_st : std_ulogic; +signal fdep_fiss_t1_is2_axu_store : std_ulogic; +signal fdep_fiss_t1_is2_axu_ldst_size : std_ulogic_vector(0 to 5); +signal fdep_fiss_t1_is2_axu_ldst_tag : std_ulogic_vector(0 to 8); +signal fdep_fiss_t1_is2_axu_ldst_indexed : std_ulogic; +signal fdep_fiss_t1_is2_axu_ldst_update : std_ulogic; +signal fdep_fiss_t1_is2_axu_ldst_extpid : std_ulogic; +signal fdep_fiss_t1_is2_axu_ldst_forcealign : std_ulogic; +signal fdep_fiss_t1_is2_axu_ldst_forceexcept : std_ulogic; +signal fdep_fiss_t1_is2_axu_mftgpr : std_ulogic; +signal fdep_fiss_t1_is2_axu_mffgpr : std_ulogic; +signal fdep_fiss_t1_is2_axu_movedp : std_ulogic; +signal fdep_fiss_t1_is2_axu_instr_type : std_ulogic_vector(0 to 2); +signal fdep_fiss_t1_is2_match : std_ulogic; +signal fdep_fiss_t1_is2_2ucode : std_ulogic; +signal fdep_fiss_t1_is2_2ucode_type : std_ulogic; +signal fdep_fiss_t1_is2early_vld : std_ulogic; +signal fdep_fiss_t1_is1_xu_dep_hit_b : std_ulogic; +signal fdep_fiss_t1_is2_hole_delay : std_ulogic_vector(0 to 2); +signal fdep_fiss_t1_is2_to_ucode : std_ulogic; +signal fdep_fiss_t1_is2_is_ucode : std_ulogic; +signal fiss_fdep_is2_take2 : std_ulogic; +signal fdep_fiss_t2_is2_instr : std_ulogic_vector(0 to 31); +signal fdep_fiss_t2_is2_ta_vld : std_ulogic; +signal fdep_fiss_t2_is2_ta : std_ulogic_vector(0 to 5); +signal fdep_fiss_t2_is2_s1_vld : std_ulogic; +signal fdep_fiss_t2_is2_s1 : std_ulogic_vector(0 to 5); +signal fdep_fiss_t2_is2_s2_vld : std_ulogic; +signal fdep_fiss_t2_is2_s2 : std_ulogic_vector(0 to 5); +signal fdep_fiss_t2_is2_s3_vld : std_ulogic; +signal fdep_fiss_t2_is2_s3 : std_ulogic_vector(0 to 5); +signal fdep_fiss_t2_is2_pred_update : std_ulogic; +signal fdep_fiss_t2_is2_pred_taken_cnt : std_ulogic_vector(0 to 1); +signal fdep_fiss_t2_is2_gshare : std_ulogic_vector(0 to 3); +signal fdep_fiss_t2_is2_ifar : eff_ifar; +signal fdep_fiss_t2_is2_error : std_ulogic_vector(0 to 2); +signal fdep_fiss_t2_is2_axu_ld_or_st : std_ulogic; +signal fdep_fiss_t2_is2_axu_store : std_ulogic; +signal fdep_fiss_t2_is2_axu_ldst_size : std_ulogic_vector(0 to 5); +signal fdep_fiss_t2_is2_axu_ldst_tag : std_ulogic_vector(0 to 8); +signal fdep_fiss_t2_is2_axu_ldst_indexed : std_ulogic; +signal fdep_fiss_t2_is2_axu_ldst_update : std_ulogic; +signal fdep_fiss_t2_is2_axu_ldst_extpid : std_ulogic; +signal fdep_fiss_t2_is2_axu_ldst_forcealign : std_ulogic; +signal fdep_fiss_t2_is2_axu_ldst_forceexcept : std_ulogic; +signal fdep_fiss_t2_is2_axu_mftgpr : std_ulogic; +signal fdep_fiss_t2_is2_axu_mffgpr : std_ulogic; +signal fdep_fiss_t2_is2_axu_movedp : std_ulogic; +signal fdep_fiss_t2_is2_axu_instr_type : std_ulogic_vector(0 to 2); +signal fdep_fiss_t2_is2_match : std_ulogic; +signal fdep_fiss_t2_is2_2ucode : std_ulogic; +signal fdep_fiss_t2_is2_2ucode_type : std_ulogic; +signal fdep_fiss_t2_is2early_vld : std_ulogic; +signal fdep_fiss_t2_is1_xu_dep_hit_b : std_ulogic; +signal fdep_fiss_t2_is2_hole_delay : std_ulogic_vector(0 to 2); +signal fdep_fiss_t2_is2_to_ucode : std_ulogic; +signal fdep_fiss_t2_is2_is_ucode : std_ulogic; +signal fiss_fdep_is2_take3 : std_ulogic; +signal fdep_fiss_t3_is2_instr : std_ulogic_vector(0 to 31); +signal fdep_fiss_t3_is2_ta_vld : std_ulogic; +signal fdep_fiss_t3_is2_ta : std_ulogic_vector(0 to 5); +signal fdep_fiss_t3_is2_s1_vld : std_ulogic; +signal fdep_fiss_t3_is2_s1 : std_ulogic_vector(0 to 5); +signal fdep_fiss_t3_is2_s2_vld : std_ulogic; +signal fdep_fiss_t3_is2_s2 : std_ulogic_vector(0 to 5); +signal fdep_fiss_t3_is2_s3_vld : std_ulogic; +signal fdep_fiss_t3_is2_s3 : std_ulogic_vector(0 to 5); +signal fdep_fiss_t3_is2_pred_update : std_ulogic; +signal fdep_fiss_t3_is2_pred_taken_cnt : std_ulogic_vector(0 to 1); +signal fdep_fiss_t3_is2_gshare : std_ulogic_vector(0 to 3); +signal fdep_fiss_t3_is2_ifar : eff_ifar; +signal fdep_fiss_t3_is2_error : std_ulogic_vector(0 to 2); +signal fdep_fiss_t3_is2_axu_ld_or_st : std_ulogic; +signal fdep_fiss_t3_is2_axu_store : std_ulogic; +signal fdep_fiss_t3_is2_axu_ldst_size : std_ulogic_vector(0 to 5); +signal fdep_fiss_t3_is2_axu_ldst_tag : std_ulogic_vector(0 to 8); +signal fdep_fiss_t3_is2_axu_ldst_indexed : std_ulogic; +signal fdep_fiss_t3_is2_axu_ldst_update : std_ulogic; +signal fdep_fiss_t3_is2_axu_ldst_extpid : std_ulogic; +signal fdep_fiss_t3_is2_axu_ldst_forcealign : std_ulogic; +signal fdep_fiss_t3_is2_axu_ldst_forceexcept : std_ulogic; +signal fdep_fiss_t3_is2_axu_mftgpr : std_ulogic; +signal fdep_fiss_t3_is2_axu_mffgpr : std_ulogic; +signal fdep_fiss_t3_is2_axu_movedp : std_ulogic; +signal fdep_fiss_t3_is2_axu_instr_type : std_ulogic_vector(0 to 2); +signal fdep_fiss_t3_is2_match : std_ulogic; +signal fdep_fiss_t3_is2_2ucode : std_ulogic; +signal fdep_fiss_t3_is2_2ucode_type : std_ulogic; +signal fdep_fiss_t3_is2early_vld : std_ulogic; +signal fdep_fiss_t3_is1_xu_dep_hit_b : std_ulogic; +signal fdep_fiss_t3_is2_hole_delay : std_ulogic_vector(0 to 2); +signal fdep_fiss_t3_is2_to_ucode : std_ulogic; +signal fdep_fiss_t3_is2_is_ucode : std_ulogic; +-- AXU Issue +signal i_afi_is2_take_t : std_ulogic_vector(0 to 3); +signal i_axu_is1_dep_hit_t0_b : std_ulogic; +signal i_axu_is2_instr_match_t0 : std_ulogic; +signal i_afd_is2_t0_instr_v : std_ulogic; +signal i_axu_is1_early_v_t0 : std_ulogic; +signal i_afd_is2_fra_t0 : std_ulogic_vector(0 to 6); +signal i_afd_is2_frb_t0 : std_ulogic_vector(0 to 6); +signal i_afd_is2_frc_t0 : std_ulogic_vector(0 to 6); +signal i_afd_is2_frt_t0 : std_ulogic_vector(0 to 6); +signal i_afd_is2_fra_v_t0 : std_ulogic; +signal i_afd_is2_frb_v_t0 : std_ulogic; +signal i_afd_is2_frc_v_t0 : std_ulogic; +signal ifdp_is2_est_bubble3_t0 : std_ulogic; +signal i_afd_is2_is_ucode_t0 : std_ulogic; +signal i_afd_ignore_flush_is2_t0 : std_ulogic; +signal i_afd_in_ucode_mode_or1d_b_t0 : std_ulogic; +signal i_axu_is1_dep_hit_t1_b : std_ulogic; +signal i_axu_is2_instr_match_t1 : std_ulogic; +signal i_afd_is2_t1_instr_v : std_ulogic; +signal i_axu_is1_early_v_t1 : std_ulogic; +signal i_afd_is2_fra_t1 : std_ulogic_vector(0 to 6); +signal i_afd_is2_frb_t1 : std_ulogic_vector(0 to 6); +signal i_afd_is2_frc_t1 : std_ulogic_vector(0 to 6); +signal i_afd_is2_frt_t1 : std_ulogic_vector(0 to 6); +signal i_afd_is2_fra_v_t1 : std_ulogic; +signal i_afd_is2_frb_v_t1 : std_ulogic; +signal i_afd_is2_frc_v_t1 : std_ulogic; +signal ifdp_is2_est_bubble3_t1 : std_ulogic; +signal i_afd_is2_is_ucode_t1 : std_ulogic; +signal i_afd_ignore_flush_is2_t1 : std_ulogic; +signal i_afd_in_ucode_mode_or1d_b_t1 : std_ulogic; +signal i_axu_is1_dep_hit_t2_b : std_ulogic; +signal i_axu_is2_instr_match_t2 : std_ulogic; +signal i_afd_is2_t2_instr_v : std_ulogic; +signal i_axu_is1_early_v_t2 : std_ulogic; +signal i_afd_is2_fra_t2 : std_ulogic_vector(0 to 6); +signal i_afd_is2_frb_t2 : std_ulogic_vector(0 to 6); +signal i_afd_is2_frc_t2 : std_ulogic_vector(0 to 6); +signal i_afd_is2_frt_t2 : std_ulogic_vector(0 to 6); +signal i_afd_is2_fra_v_t2 : std_ulogic; +signal i_afd_is2_frb_v_t2 : std_ulogic; +signal i_afd_is2_frc_v_t2 : std_ulogic; +signal ifdp_is2_est_bubble3_t2 : std_ulogic; +signal i_afd_is2_is_ucode_t2 : std_ulogic; +signal i_afd_ignore_flush_is2_t2 : std_ulogic; +signal i_afd_in_ucode_mode_or1d_b_t2 : std_ulogic; +signal i_axu_is1_dep_hit_t3_b : std_ulogic; +signal i_axu_is2_instr_match_t3 : std_ulogic; +signal i_afd_is2_t3_instr_v : std_ulogic; +signal i_axu_is1_early_v_t3 : std_ulogic; +signal i_afd_is2_fra_t3 : std_ulogic_vector(0 to 6); +signal i_afd_is2_frb_t3 : std_ulogic_vector(0 to 6); +signal i_afd_is2_frc_t3 : std_ulogic_vector(0 to 6); +signal i_afd_is2_frt_t3 : std_ulogic_vector(0 to 6); +signal i_afd_is2_fra_v_t3 : std_ulogic; +signal i_afd_is2_frb_v_t3 : std_ulogic; +signal i_afd_is2_frc_v_t3 : std_ulogic; +signal ifdp_is2_est_bubble3_t3 : std_ulogic; +signal i_afd_is2_is_ucode_t3 : std_ulogic; +signal i_afd_ignore_flush_is2_t3 : std_ulogic; +signal i_afd_in_ucode_mode_or1d_b_t3 : std_ulogic; +signal i_afd_is2_bypsel_t0 : std_ulogic_vector(0 to 5); +signal i_afd_is2_bypsel_t1 : std_ulogic_vector(0 to 5); +signal i_afd_is2_bypsel_t2 : std_ulogic_vector(0 to 5); +signal i_afd_is2_bypsel_t3 : std_ulogic_vector(0 to 5); +signal iu_au_hi_pri_mask : std_ulogic_vector(0 to 3); +signal iu_au_md_pri_mask : std_ulogic_vector(0 to 3); +signal slice_id0 : std_ulogic_vector(0 to 1); +signal slice_id1 : std_ulogic_vector(0 to 1); +signal slice_id2 : std_ulogic_vector(0 to 1); +signal slice_id3 : std_ulogic_vector(0 to 1); +signal iu_au_config_iucr_pt_t0 : std_ulogic_vector(2 to 4); +signal iu_au_config_iucr_pt_t1 : std_ulogic_vector(2 to 4); +signal iu_au_config_iucr_pt_t2 : std_ulogic_vector(2 to 4); +signal iu_au_config_iucr_pt_t3 : std_ulogic_vector(2 to 4); +begin +iuq_slice0 : entity work.iuq_slice +generic map(expand_type => expand_type, + regmode => regmode, + a2mode => a2mode, + lmq_entries => lmq_entries) +port map( + slice_id => slice_id0, + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_iu_func_sl_thold_2 => pc_iu_func_sl_thold_2(0), + pc_iu_sg_2 => pc_iu_sg_2(0), + clkoff_b => clkoff_b(0), + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b(0), + tc_ac_ccflush_dc => tc_ac_ccflush_dc, + delay_lclkr => delay_lclkr(10+0), + mpw1_b => mpw1_b(10+0), + scan_in => iuq_s0_scan_in, + scan_out => iuq_s0_scan_out, + pc_iu_ram_mode => pc_iu_ram_mode, + pc_iu_ram_thread => pc_iu_ram_thread, + pc_iu_trace_bus_enable => pc_iu_trace_bus_enable, + pc_iu_event_bus_enable => pc_iu_event_bus_enable, + fdep_dbg_data => fdep_dbg_data(22*0 to 22*0+21), + fdep_perf_event => fdep_perf_event_t0, + iu_au_config_iucr => iu_au_config_iucr_t0, + iu_au_config_iucr_pt => iu_au_config_iucr_pt_t0, + spr_dec_mask => spr_dec_mask_t0, + spr_dec_match => spr_dec_match_t0, + uc_flush => uc_flush_tid(0), + xu_iu_flush => xu_iu_flush(0), + xu_iu_rf1_flush => xu_rf1_flush(0), + xu_iu_ex1_flush => xu_ex1_flush(0), + xu_iu_ex2_flush => xu_ex2_flush(0), + xu_iu_ex3_flush => xu_ex3_flush(0), + xu_iu_ex4_flush => xu_ex4_flush(0), + xu_iu_ex5_flush => xu_ex5_flush(0), + fdec_ibuf_stall => fdec_ibuf_stall_t0, + iu_au_ib1_instr_vld => iu_au_ib1_instr_vld_t0, + iu_au_ib1_ifar => iu_au_ib1_ifar_t0, + iu_au_ib1_data => iu_au_ib1_data_t0, + xu_iu_ucode_restart => xu_iu_ucode_restart(0), + xu_iu_slowspr_done => xu_iu_slowspr_done(0), + xu_iu_multdiv_done => xu_iu_multdiv_done(0), + xu_iu_ex4_loadmiss_vld => xu_iu_ex4_loadmiss_tid(0), + xu_iu_ex4_loadmiss_qentry => xu_iu_ex4_loadmiss_qentry, + xu_iu_ex4_loadmiss_target => xu_iu_ex4_loadmiss_target, + xu_iu_ex4_loadmiss_target_type => xu_iu_ex4_loadmiss_target_type, + xu_iu_ex5_loadmiss_vld => xu_iu_ex5_loadmiss_tid(0), + xu_iu_ex5_loadmiss_qentry => xu_iu_ex5_loadmiss_qentry, + xu_iu_ex5_loadmiss_target => xu_iu_ex5_loadmiss_target(1 to 6), + xu_iu_ex5_loadmiss_target_type => xu_iu_ex5_loadmiss_target_type(0 to 0), + xu_iu_complete_vld => xu_iu_complete_tid(0), + xu_iu_complete_qentry => xu_iu_complete_qentry, + xu_iu_complete_target_type => xu_iu_complete_target_type, + ic_fdep_load_quiesce => ic_fdep_load_quiesce(0), + iu_xu_quiesce => iu_xu_quiesce(0), + xu_iu_membar_tid => xu_iu_membar_tid(0), + xu_iu_set_barr_tid => xu_iu_set_barr_tid(0), + xu_iu_larx_done_tid => xu_iu_larx_done_tid(0), + an_ac_sync_ack => an_ac_sync_ack(0), + ic_fdep_icbi_ack => ic_fdep_icbi_ack(0), + an_ac_stcx_complete => an_ac_stcx_complete(0), + mm_iu_barrier_done => mm_iu_barrier_done(0), + spr_fdep_ll_hold => spr_fdep_ll_hold_t0, + xu_iu_spr_ccr2_en_dcr => xu_iu_spr_ccr2_en_dcr, + xu_iu_single_instr_mode => xu_iu_single_instr_mode(0), + fiss_fdep_is2_take => fiss_fdep_is2_take0, + fdep_fiss_is2_instr => fdep_fiss_t0_is2_instr, + fdep_fiss_is2_ta_vld => fdep_fiss_t0_is2_ta_vld, + fdep_fiss_is2_ta => fdep_fiss_t0_is2_ta, + fdep_fiss_is2_s1_vld => fdep_fiss_t0_is2_s1_vld, + fdep_fiss_is2_s1 => fdep_fiss_t0_is2_s1, + fdep_fiss_is2_s2_vld => fdep_fiss_t0_is2_s2_vld, + fdep_fiss_is2_s2 => fdep_fiss_t0_is2_s2, + fdep_fiss_is2_s3_vld => fdep_fiss_t0_is2_s3_vld, + fdep_fiss_is2_s3 => fdep_fiss_t0_is2_s3, + fdep_fiss_is2_pred_update => fdep_fiss_t0_is2_pred_update, + fdep_fiss_is2_pred_taken_cnt => fdep_fiss_t0_is2_pred_taken_cnt, + fdep_fiss_is2_gshare => fdep_fiss_t0_is2_gshare, + fdep_fiss_is2_ifar => fdep_fiss_t0_is2_ifar, + fdep_fiss_is2_error => fdep_fiss_t0_is2_error, + fdep_fiss_is2_axu_ld_or_st => fdep_fiss_t0_is2_axu_ld_or_st, + fdep_fiss_is2_axu_store => fdep_fiss_t0_is2_axu_store, + fdep_fiss_is2_axu_ldst_size => fdep_fiss_t0_is2_axu_ldst_size, + fdep_fiss_is2_axu_ldst_tag => fdep_fiss_t0_is2_axu_ldst_tag, + fdep_fiss_is2_axu_ldst_indexed => fdep_fiss_t0_is2_axu_ldst_indexed, + fdep_fiss_is2_axu_ldst_update => fdep_fiss_t0_is2_axu_ldst_update, + fdep_fiss_is2_axu_ldst_extpid => fdep_fiss_t0_is2_axu_ldst_extpid, + fdep_fiss_is2_axu_ldst_forcealign => fdep_fiss_t0_is2_axu_ldst_forcealign, + fdep_fiss_is2_axu_ldst_forceexcept => fdep_fiss_t0_is2_axu_ldst_forceexcept, + fdep_fiss_is2_axu_mftgpr => fdep_fiss_t0_is2_axu_mftgpr, + fdep_fiss_is2_axu_mffgpr => fdep_fiss_t0_is2_axu_mffgpr, + fdep_fiss_is2_axu_movedp => fdep_fiss_t0_is2_axu_movedp, + fdep_fiss_is2_axu_instr_type => fdep_fiss_t0_is2_axu_instr_type, + fdep_fiss_is2_match => fdep_fiss_t0_is2_match, + fdep_fiss_is2_2ucode => fdep_fiss_t0_is2_2ucode, + fdep_fiss_is2_2ucode_type => fdep_fiss_t0_is2_2ucode_type, + fdep_fiss_is2early_vld => fdep_fiss_t0_is2early_vld, + fdep_fiss_is1_xu_dep_hit_b => fdep_fiss_t0_is1_xu_dep_hit_b, + fdep_fiss_is2_hole_delay => fdep_fiss_t0_is2_hole_delay, + fdep_fiss_is2_to_ucode => fdep_fiss_t0_is2_to_ucode, + fdep_fiss_is2_is_ucode => fdep_fiss_t0_is2_is_ucode, + fu_iu_uc_special => fu_iu_uc_special(0), + iu_fu_ex2_n_flush => iu_fu_ex2_n_flush(0), + i_afi_is2_take => i_afi_is2_take_t(0), + i_axu_is1_dep_hit_b => i_axu_is1_dep_hit_t0_b, + i_axu_is2_instr_v => i_afd_is2_t0_instr_v, + i_axu_is1_early_v => i_axu_is1_early_v_t0, + i_axu_is2_instr_match => i_axu_is2_instr_match_t0, + i_axu_is2_fra => i_afd_is2_fra_t0, + i_axu_is2_frb => i_afd_is2_frb_t0, + i_axu_is2_frc => i_afd_is2_frc_t0, + i_axu_is2_frt => i_afd_is2_frt_t0, + i_axu_is2_fra_v => i_afd_is2_fra_v_t0, + i_axu_is2_frb_v => i_afd_is2_frb_v_t0, + i_axu_is2_frc_v => i_afd_is2_frc_v_t0, + i_afd_is2_is_ucode => i_afd_is2_is_ucode_t0, + i_afd_ignore_flush_is2 => i_afd_ignore_flush_is2_t0, + i_afd_in_ucode_mode_or1d_b => i_afd_in_ucode_mode_or1d_b_t0, + ifdp_is2_est_bubble3 => ifdp_is2_est_bubble3_t0, + ifdp_is2_bypsel => i_afd_is2_bypsel_t0, + axu_dbg_data => axu_dbg_data_t0 +); +iuq_slice1 : entity work.iuq_slice +generic map(expand_type => expand_type, + regmode => regmode, + a2mode => a2mode, + lmq_entries => lmq_entries) +port map( + slice_id => slice_id1, + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_iu_func_sl_thold_2 => pc_iu_func_sl_thold_2(1), + pc_iu_sg_2 => pc_iu_sg_2(1), + clkoff_b => clkoff_b(1), + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b(1), + tc_ac_ccflush_dc => tc_ac_ccflush_dc, + delay_lclkr => delay_lclkr(10+1), + mpw1_b => mpw1_b(10+1), + scan_in => iuq_s1_scan_in, + scan_out => iuq_s1_scan_out, + pc_iu_ram_mode => pc_iu_ram_mode, + pc_iu_ram_thread => pc_iu_ram_thread, + pc_iu_trace_bus_enable => pc_iu_trace_bus_enable, + pc_iu_event_bus_enable => pc_iu_event_bus_enable, + fdep_dbg_data => fdep_dbg_data(22*1 to 22*1+21), + fdep_perf_event => fdep_perf_event_t1, + iu_au_config_iucr => iu_au_config_iucr_t1, + iu_au_config_iucr_pt => iu_au_config_iucr_pt_t1, + spr_dec_mask => spr_dec_mask_t1, + spr_dec_match => spr_dec_match_t1, + uc_flush => uc_flush_tid(1), + xu_iu_flush => xu_iu_flush(1), + xu_iu_rf1_flush => xu_rf1_flush(1), + xu_iu_ex1_flush => xu_ex1_flush(1), + xu_iu_ex2_flush => xu_ex2_flush(1), + xu_iu_ex3_flush => xu_ex3_flush(1), + xu_iu_ex4_flush => xu_ex4_flush(1), + xu_iu_ex5_flush => xu_ex5_flush(1), + fdec_ibuf_stall => fdec_ibuf_stall_t1, + iu_au_ib1_instr_vld => iu_au_ib1_instr_vld_t1, + iu_au_ib1_ifar => iu_au_ib1_ifar_t1, + iu_au_ib1_data => iu_au_ib1_data_t1, + xu_iu_ucode_restart => xu_iu_ucode_restart(1), + xu_iu_slowspr_done => xu_iu_slowspr_done(1), + xu_iu_multdiv_done => xu_iu_multdiv_done(1), + xu_iu_ex4_loadmiss_vld => xu_iu_ex4_loadmiss_tid(1), + xu_iu_ex4_loadmiss_qentry => xu_iu_ex4_loadmiss_qentry, + xu_iu_ex4_loadmiss_target => xu_iu_ex4_loadmiss_target, + xu_iu_ex4_loadmiss_target_type => xu_iu_ex4_loadmiss_target_type, + xu_iu_ex5_loadmiss_vld => xu_iu_ex5_loadmiss_tid(1), + xu_iu_ex5_loadmiss_qentry => xu_iu_ex5_loadmiss_qentry, + xu_iu_ex5_loadmiss_target => xu_iu_ex5_loadmiss_target(1 to 6), + xu_iu_ex5_loadmiss_target_type => xu_iu_ex5_loadmiss_target_type(0 to 0), + xu_iu_complete_vld => xu_iu_complete_tid(1), + xu_iu_complete_qentry => xu_iu_complete_qentry, + xu_iu_complete_target_type => xu_iu_complete_target_type, + ic_fdep_load_quiesce => ic_fdep_load_quiesce(1), + iu_xu_quiesce => iu_xu_quiesce(1), + xu_iu_membar_tid => xu_iu_membar_tid(1), + xu_iu_set_barr_tid => xu_iu_set_barr_tid(1), + xu_iu_larx_done_tid => xu_iu_larx_done_tid(1), + an_ac_sync_ack => an_ac_sync_ack(1), + ic_fdep_icbi_ack => ic_fdep_icbi_ack(1), + an_ac_stcx_complete => an_ac_stcx_complete(1), + mm_iu_barrier_done => mm_iu_barrier_done(1), + spr_fdep_ll_hold => spr_fdep_ll_hold_t1, + xu_iu_spr_ccr2_en_dcr => xu_iu_spr_ccr2_en_dcr, + xu_iu_single_instr_mode => xu_iu_single_instr_mode(1), + fiss_fdep_is2_take => fiss_fdep_is2_take1, + fdep_fiss_is2_instr => fdep_fiss_t1_is2_instr, + fdep_fiss_is2_ta_vld => fdep_fiss_t1_is2_ta_vld, + fdep_fiss_is2_ta => fdep_fiss_t1_is2_ta, + fdep_fiss_is2_s1_vld => fdep_fiss_t1_is2_s1_vld, + fdep_fiss_is2_s1 => fdep_fiss_t1_is2_s1, + fdep_fiss_is2_s2_vld => fdep_fiss_t1_is2_s2_vld, + fdep_fiss_is2_s2 => fdep_fiss_t1_is2_s2, + fdep_fiss_is2_s3_vld => fdep_fiss_t1_is2_s3_vld, + fdep_fiss_is2_s3 => fdep_fiss_t1_is2_s3, + fdep_fiss_is2_pred_update => fdep_fiss_t1_is2_pred_update, + fdep_fiss_is2_pred_taken_cnt => fdep_fiss_t1_is2_pred_taken_cnt, + fdep_fiss_is2_gshare => fdep_fiss_t1_is2_gshare, + fdep_fiss_is2_ifar => fdep_fiss_t1_is2_ifar, + fdep_fiss_is2_error => fdep_fiss_t1_is2_error, + fdep_fiss_is2_axu_ld_or_st => fdep_fiss_t1_is2_axu_ld_or_st, + fdep_fiss_is2_axu_store => fdep_fiss_t1_is2_axu_store, + fdep_fiss_is2_axu_ldst_size => fdep_fiss_t1_is2_axu_ldst_size, + fdep_fiss_is2_axu_ldst_tag => fdep_fiss_t1_is2_axu_ldst_tag, + fdep_fiss_is2_axu_ldst_indexed => fdep_fiss_t1_is2_axu_ldst_indexed, + fdep_fiss_is2_axu_ldst_update => fdep_fiss_t1_is2_axu_ldst_update, + fdep_fiss_is2_axu_ldst_extpid => fdep_fiss_t1_is2_axu_ldst_extpid, + fdep_fiss_is2_axu_ldst_forcealign => fdep_fiss_t1_is2_axu_ldst_forcealign, + fdep_fiss_is2_axu_ldst_forceexcept => fdep_fiss_t1_is2_axu_ldst_forceexcept, + fdep_fiss_is2_axu_mftgpr => fdep_fiss_t1_is2_axu_mftgpr, + fdep_fiss_is2_axu_mffgpr => fdep_fiss_t1_is2_axu_mffgpr, + fdep_fiss_is2_axu_movedp => fdep_fiss_t1_is2_axu_movedp, + fdep_fiss_is2_axu_instr_type => fdep_fiss_t1_is2_axu_instr_type, + fdep_fiss_is2_match => fdep_fiss_t1_is2_match, + fdep_fiss_is2_2ucode => fdep_fiss_t1_is2_2ucode, + fdep_fiss_is2_2ucode_type => fdep_fiss_t1_is2_2ucode_type, + fdep_fiss_is2early_vld => fdep_fiss_t1_is2early_vld, + fdep_fiss_is1_xu_dep_hit_b => fdep_fiss_t1_is1_xu_dep_hit_b, + fdep_fiss_is2_hole_delay => fdep_fiss_t1_is2_hole_delay, + fdep_fiss_is2_to_ucode => fdep_fiss_t1_is2_to_ucode, + fdep_fiss_is2_is_ucode => fdep_fiss_t1_is2_is_ucode, + fu_iu_uc_special => fu_iu_uc_special(1), + iu_fu_ex2_n_flush => iu_fu_ex2_n_flush(1), + i_afi_is2_take => i_afi_is2_take_t(1), + i_axu_is1_dep_hit_b => i_axu_is1_dep_hit_t1_b, + i_axu_is2_instr_v => i_afd_is2_t1_instr_v, + i_axu_is1_early_v => i_axu_is1_early_v_t1, + i_axu_is2_instr_match => i_axu_is2_instr_match_t1, + i_axu_is2_fra => i_afd_is2_fra_t1, + i_axu_is2_frb => i_afd_is2_frb_t1, + i_axu_is2_frc => i_afd_is2_frc_t1, + i_axu_is2_frt => i_afd_is2_frt_t1, + i_axu_is2_fra_v => i_afd_is2_fra_v_t1, + i_axu_is2_frb_v => i_afd_is2_frb_v_t1, + i_axu_is2_frc_v => i_afd_is2_frc_v_t1, + i_afd_is2_is_ucode => i_afd_is2_is_ucode_t1, + i_afd_ignore_flush_is2 => i_afd_ignore_flush_is2_t1, + i_afd_in_ucode_mode_or1d_b => i_afd_in_ucode_mode_or1d_b_t1, + ifdp_is2_est_bubble3 => ifdp_is2_est_bubble3_t1, + ifdp_is2_bypsel => i_afd_is2_bypsel_t1, + axu_dbg_data => axu_dbg_data_t1 +); +iuq_slice2 : entity work.iuq_slice +generic map(expand_type => expand_type, + regmode => regmode, + a2mode => a2mode, + lmq_entries => lmq_entries) +port map( + slice_id => slice_id2, + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_iu_func_sl_thold_2 => pc_iu_func_sl_thold_2(2), + pc_iu_sg_2 => pc_iu_sg_2(2), + clkoff_b => clkoff_b(2), + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b(2), + tc_ac_ccflush_dc => tc_ac_ccflush_dc, + delay_lclkr => delay_lclkr(10+2), + mpw1_b => mpw1_b(10+2), + scan_in => iuq_s2_scan_in, + scan_out => iuq_s2_scan_out, + pc_iu_ram_mode => pc_iu_ram_mode, + pc_iu_ram_thread => pc_iu_ram_thread, + pc_iu_trace_bus_enable => pc_iu_trace_bus_enable, + pc_iu_event_bus_enable => pc_iu_event_bus_enable, + fdep_dbg_data => fdep_dbg_data(22*2 to 22*2+21), + fdep_perf_event => fdep_perf_event_t2, + iu_au_config_iucr => iu_au_config_iucr_t2, + iu_au_config_iucr_pt => iu_au_config_iucr_pt_t2, + spr_dec_mask => spr_dec_mask_t2, + spr_dec_match => spr_dec_match_t2, + uc_flush => uc_flush_tid(2), + xu_iu_flush => xu_iu_flush(2), + xu_iu_rf1_flush => xu_rf1_flush(2), + xu_iu_ex1_flush => xu_ex1_flush(2), + xu_iu_ex2_flush => xu_ex2_flush(2), + xu_iu_ex3_flush => xu_ex3_flush(2), + xu_iu_ex4_flush => xu_ex4_flush(2), + xu_iu_ex5_flush => xu_ex5_flush(2), + fdec_ibuf_stall => fdec_ibuf_stall_t2, + iu_au_ib1_instr_vld => iu_au_ib1_instr_vld_t2, + iu_au_ib1_ifar => iu_au_ib1_ifar_t2, + iu_au_ib1_data => iu_au_ib1_data_t2, + xu_iu_ucode_restart => xu_iu_ucode_restart(2), + xu_iu_slowspr_done => xu_iu_slowspr_done(2), + xu_iu_multdiv_done => xu_iu_multdiv_done(2), + xu_iu_ex4_loadmiss_vld => xu_iu_ex4_loadmiss_tid(2), + xu_iu_ex4_loadmiss_qentry => xu_iu_ex4_loadmiss_qentry, + xu_iu_ex4_loadmiss_target => xu_iu_ex4_loadmiss_target, + xu_iu_ex4_loadmiss_target_type => xu_iu_ex4_loadmiss_target_type, + xu_iu_ex5_loadmiss_vld => xu_iu_ex5_loadmiss_tid(2), + xu_iu_ex5_loadmiss_qentry => xu_iu_ex5_loadmiss_qentry, + xu_iu_ex5_loadmiss_target => xu_iu_ex5_loadmiss_target(1 to 6), + xu_iu_ex5_loadmiss_target_type => xu_iu_ex5_loadmiss_target_type(0 to 0), + xu_iu_complete_vld => xu_iu_complete_tid(2), + xu_iu_complete_qentry => xu_iu_complete_qentry, + xu_iu_complete_target_type => xu_iu_complete_target_type, + ic_fdep_load_quiesce => ic_fdep_load_quiesce(2), + iu_xu_quiesce => iu_xu_quiesce(2), + xu_iu_membar_tid => xu_iu_membar_tid(2), + xu_iu_set_barr_tid => xu_iu_set_barr_tid(2), + xu_iu_larx_done_tid => xu_iu_larx_done_tid(2), + an_ac_sync_ack => an_ac_sync_ack(2), + ic_fdep_icbi_ack => ic_fdep_icbi_ack(2), + an_ac_stcx_complete => an_ac_stcx_complete(2), + mm_iu_barrier_done => mm_iu_barrier_done(2), + spr_fdep_ll_hold => spr_fdep_ll_hold_t2, + xu_iu_spr_ccr2_en_dcr => xu_iu_spr_ccr2_en_dcr, + xu_iu_single_instr_mode => xu_iu_single_instr_mode(2), + fiss_fdep_is2_take => fiss_fdep_is2_take2, + fdep_fiss_is2_instr => fdep_fiss_t2_is2_instr, + fdep_fiss_is2_ta_vld => fdep_fiss_t2_is2_ta_vld, + fdep_fiss_is2_ta => fdep_fiss_t2_is2_ta, + fdep_fiss_is2_s1_vld => fdep_fiss_t2_is2_s1_vld, + fdep_fiss_is2_s1 => fdep_fiss_t2_is2_s1, + fdep_fiss_is2_s2_vld => fdep_fiss_t2_is2_s2_vld, + fdep_fiss_is2_s2 => fdep_fiss_t2_is2_s2, + fdep_fiss_is2_s3_vld => fdep_fiss_t2_is2_s3_vld, + fdep_fiss_is2_s3 => fdep_fiss_t2_is2_s3, + fdep_fiss_is2_pred_update => fdep_fiss_t2_is2_pred_update, + fdep_fiss_is2_pred_taken_cnt => fdep_fiss_t2_is2_pred_taken_cnt, + fdep_fiss_is2_gshare => fdep_fiss_t2_is2_gshare, + fdep_fiss_is2_ifar => fdep_fiss_t2_is2_ifar, + fdep_fiss_is2_error => fdep_fiss_t2_is2_error, + fdep_fiss_is2_axu_ld_or_st => fdep_fiss_t2_is2_axu_ld_or_st, + fdep_fiss_is2_axu_store => fdep_fiss_t2_is2_axu_store, + fdep_fiss_is2_axu_ldst_size => fdep_fiss_t2_is2_axu_ldst_size, + fdep_fiss_is2_axu_ldst_tag => fdep_fiss_t2_is2_axu_ldst_tag, + fdep_fiss_is2_axu_ldst_indexed => fdep_fiss_t2_is2_axu_ldst_indexed, + fdep_fiss_is2_axu_ldst_update => fdep_fiss_t2_is2_axu_ldst_update, + fdep_fiss_is2_axu_ldst_extpid => fdep_fiss_t2_is2_axu_ldst_extpid, + fdep_fiss_is2_axu_ldst_forcealign => fdep_fiss_t2_is2_axu_ldst_forcealign, + fdep_fiss_is2_axu_ldst_forceexcept => fdep_fiss_t2_is2_axu_ldst_forceexcept, + fdep_fiss_is2_axu_mftgpr => fdep_fiss_t2_is2_axu_mftgpr, + fdep_fiss_is2_axu_mffgpr => fdep_fiss_t2_is2_axu_mffgpr, + fdep_fiss_is2_axu_movedp => fdep_fiss_t2_is2_axu_movedp, + fdep_fiss_is2_axu_instr_type => fdep_fiss_t2_is2_axu_instr_type, + fdep_fiss_is2_match => fdep_fiss_t2_is2_match, + fdep_fiss_is2_2ucode => fdep_fiss_t2_is2_2ucode, + fdep_fiss_is2_2ucode_type => fdep_fiss_t2_is2_2ucode_type, + fdep_fiss_is2early_vld => fdep_fiss_t2_is2early_vld, + fdep_fiss_is1_xu_dep_hit_b => fdep_fiss_t2_is1_xu_dep_hit_b, + fdep_fiss_is2_hole_delay => fdep_fiss_t2_is2_hole_delay, + fdep_fiss_is2_to_ucode => fdep_fiss_t2_is2_to_ucode, + fdep_fiss_is2_is_ucode => fdep_fiss_t2_is2_is_ucode, + fu_iu_uc_special => fu_iu_uc_special(2), + iu_fu_ex2_n_flush => iu_fu_ex2_n_flush(2), + i_afi_is2_take => i_afi_is2_take_t(2), + i_axu_is1_dep_hit_b => i_axu_is1_dep_hit_t2_b, + i_axu_is2_instr_v => i_afd_is2_t2_instr_v, + i_axu_is1_early_v => i_axu_is1_early_v_t2, + i_axu_is2_instr_match => i_axu_is2_instr_match_t2, + i_axu_is2_fra => i_afd_is2_fra_t2, + i_axu_is2_frb => i_afd_is2_frb_t2, + i_axu_is2_frc => i_afd_is2_frc_t2, + i_axu_is2_frt => i_afd_is2_frt_t2, + i_axu_is2_fra_v => i_afd_is2_fra_v_t2, + i_axu_is2_frb_v => i_afd_is2_frb_v_t2, + i_axu_is2_frc_v => i_afd_is2_frc_v_t2, + i_afd_is2_is_ucode => i_afd_is2_is_ucode_t2, + i_afd_ignore_flush_is2 => i_afd_ignore_flush_is2_t2, + i_afd_in_ucode_mode_or1d_b => i_afd_in_ucode_mode_or1d_b_t2, + ifdp_is2_est_bubble3 => ifdp_is2_est_bubble3_t2, + ifdp_is2_bypsel => i_afd_is2_bypsel_t2, + axu_dbg_data => axu_dbg_data_t2 +); +iuq_slice3 : entity work.iuq_slice +generic map(expand_type => expand_type, + regmode => regmode, + a2mode => a2mode, + lmq_entries => lmq_entries) +port map( + slice_id => slice_id3, + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_iu_func_sl_thold_2 => pc_iu_func_sl_thold_2(3), + pc_iu_sg_2 => pc_iu_sg_2(3), + clkoff_b => clkoff_b(3), + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b(3), + tc_ac_ccflush_dc => tc_ac_ccflush_dc, + delay_lclkr => delay_lclkr(10+3), + mpw1_b => mpw1_b(10+3), + scan_in => iuq_s3_scan_in, + scan_out => iuq_s3_scan_out, + pc_iu_ram_mode => pc_iu_ram_mode, + pc_iu_ram_thread => pc_iu_ram_thread, + pc_iu_trace_bus_enable => pc_iu_trace_bus_enable, + pc_iu_event_bus_enable => pc_iu_event_bus_enable, + fdep_dbg_data => fdep_dbg_data(22*3 to 22*3+21), + fdep_perf_event => fdep_perf_event_t3, + iu_au_config_iucr => iu_au_config_iucr_t3, + iu_au_config_iucr_pt => iu_au_config_iucr_pt_t3, + spr_dec_mask => spr_dec_mask_t3, + spr_dec_match => spr_dec_match_t3, + uc_flush => uc_flush_tid(3), + xu_iu_flush => xu_iu_flush(3), + xu_iu_rf1_flush => xu_rf1_flush(3), + xu_iu_ex1_flush => xu_ex1_flush(3), + xu_iu_ex2_flush => xu_ex2_flush(3), + xu_iu_ex3_flush => xu_ex3_flush(3), + xu_iu_ex4_flush => xu_ex4_flush(3), + xu_iu_ex5_flush => xu_ex5_flush(3), + fdec_ibuf_stall => fdec_ibuf_stall_t3, + iu_au_ib1_instr_vld => iu_au_ib1_instr_vld_t3, + iu_au_ib1_ifar => iu_au_ib1_ifar_t3, + iu_au_ib1_data => iu_au_ib1_data_t3, + xu_iu_ucode_restart => xu_iu_ucode_restart(3), + xu_iu_slowspr_done => xu_iu_slowspr_done(3), + xu_iu_multdiv_done => xu_iu_multdiv_done(3), + xu_iu_ex4_loadmiss_vld => xu_iu_ex4_loadmiss_tid(3), + xu_iu_ex4_loadmiss_qentry => xu_iu_ex4_loadmiss_qentry, + xu_iu_ex4_loadmiss_target => xu_iu_ex4_loadmiss_target, + xu_iu_ex4_loadmiss_target_type => xu_iu_ex4_loadmiss_target_type, + xu_iu_ex5_loadmiss_vld => xu_iu_ex5_loadmiss_tid(3), + xu_iu_ex5_loadmiss_qentry => xu_iu_ex5_loadmiss_qentry, + xu_iu_ex5_loadmiss_target => xu_iu_ex5_loadmiss_target(1 to 6), + xu_iu_ex5_loadmiss_target_type => xu_iu_ex5_loadmiss_target_type(0 to 0), + xu_iu_complete_vld => xu_iu_complete_tid(3), + xu_iu_complete_qentry => xu_iu_complete_qentry, + xu_iu_complete_target_type => xu_iu_complete_target_type, + ic_fdep_load_quiesce => ic_fdep_load_quiesce(3), + iu_xu_quiesce => iu_xu_quiesce(3), + xu_iu_membar_tid => xu_iu_membar_tid(3), + xu_iu_set_barr_tid => xu_iu_set_barr_tid(3), + xu_iu_larx_done_tid => xu_iu_larx_done_tid(3), + an_ac_sync_ack => an_ac_sync_ack(3), + ic_fdep_icbi_ack => ic_fdep_icbi_ack(3), + an_ac_stcx_complete => an_ac_stcx_complete(3), + mm_iu_barrier_done => mm_iu_barrier_done(3), + spr_fdep_ll_hold => spr_fdep_ll_hold_t3, + xu_iu_spr_ccr2_en_dcr => xu_iu_spr_ccr2_en_dcr, + xu_iu_single_instr_mode => xu_iu_single_instr_mode(3), + fiss_fdep_is2_take => fiss_fdep_is2_take3, + fdep_fiss_is2_instr => fdep_fiss_t3_is2_instr, + fdep_fiss_is2_ta_vld => fdep_fiss_t3_is2_ta_vld, + fdep_fiss_is2_ta => fdep_fiss_t3_is2_ta, + fdep_fiss_is2_s1_vld => fdep_fiss_t3_is2_s1_vld, + fdep_fiss_is2_s1 => fdep_fiss_t3_is2_s1, + fdep_fiss_is2_s2_vld => fdep_fiss_t3_is2_s2_vld, + fdep_fiss_is2_s2 => fdep_fiss_t3_is2_s2, + fdep_fiss_is2_s3_vld => fdep_fiss_t3_is2_s3_vld, + fdep_fiss_is2_s3 => fdep_fiss_t3_is2_s3, + fdep_fiss_is2_pred_update => fdep_fiss_t3_is2_pred_update, + fdep_fiss_is2_pred_taken_cnt => fdep_fiss_t3_is2_pred_taken_cnt, + fdep_fiss_is2_gshare => fdep_fiss_t3_is2_gshare, + fdep_fiss_is2_ifar => fdep_fiss_t3_is2_ifar, + fdep_fiss_is2_error => fdep_fiss_t3_is2_error, + fdep_fiss_is2_axu_ld_or_st => fdep_fiss_t3_is2_axu_ld_or_st, + fdep_fiss_is2_axu_store => fdep_fiss_t3_is2_axu_store, + fdep_fiss_is2_axu_ldst_size => fdep_fiss_t3_is2_axu_ldst_size, + fdep_fiss_is2_axu_ldst_tag => fdep_fiss_t3_is2_axu_ldst_tag, + fdep_fiss_is2_axu_ldst_indexed => fdep_fiss_t3_is2_axu_ldst_indexed, + fdep_fiss_is2_axu_ldst_update => fdep_fiss_t3_is2_axu_ldst_update, + fdep_fiss_is2_axu_ldst_extpid => fdep_fiss_t3_is2_axu_ldst_extpid, + fdep_fiss_is2_axu_ldst_forcealign => fdep_fiss_t3_is2_axu_ldst_forcealign, + fdep_fiss_is2_axu_ldst_forceexcept => fdep_fiss_t3_is2_axu_ldst_forceexcept, + fdep_fiss_is2_axu_mftgpr => fdep_fiss_t3_is2_axu_mftgpr, + fdep_fiss_is2_axu_mffgpr => fdep_fiss_t3_is2_axu_mffgpr, + fdep_fiss_is2_axu_movedp => fdep_fiss_t3_is2_axu_movedp, + fdep_fiss_is2_axu_instr_type => fdep_fiss_t3_is2_axu_instr_type, + fdep_fiss_is2_match => fdep_fiss_t3_is2_match, + fdep_fiss_is2_2ucode => fdep_fiss_t3_is2_2ucode, + fdep_fiss_is2_2ucode_type => fdep_fiss_t3_is2_2ucode_type, + fdep_fiss_is2early_vld => fdep_fiss_t3_is2early_vld, + fdep_fiss_is1_xu_dep_hit_b => fdep_fiss_t3_is1_xu_dep_hit_b, + fdep_fiss_is2_hole_delay => fdep_fiss_t3_is2_hole_delay, + fdep_fiss_is2_to_ucode => fdep_fiss_t3_is2_to_ucode, + fdep_fiss_is2_is_ucode => fdep_fiss_t3_is2_is_ucode, + fu_iu_uc_special => fu_iu_uc_special(3), + iu_fu_ex2_n_flush => iu_fu_ex2_n_flush(3), + i_afi_is2_take => i_afi_is2_take_t(3), + i_axu_is1_dep_hit_b => i_axu_is1_dep_hit_t3_b, + i_axu_is2_instr_v => i_afd_is2_t3_instr_v, + i_axu_is1_early_v => i_axu_is1_early_v_t3, + i_axu_is2_instr_match => i_axu_is2_instr_match_t3, + i_axu_is2_fra => i_afd_is2_fra_t3, + i_axu_is2_frb => i_afd_is2_frb_t3, + i_axu_is2_frc => i_afd_is2_frc_t3, + i_axu_is2_frt => i_afd_is2_frt_t3, + i_axu_is2_fra_v => i_afd_is2_fra_v_t3, + i_axu_is2_frb_v => i_afd_is2_frb_v_t3, + i_axu_is2_frc_v => i_afd_is2_frc_v_t3, + i_afd_is2_is_ucode => i_afd_is2_is_ucode_t3, + i_afd_ignore_flush_is2 => i_afd_ignore_flush_is2_t3, + i_afd_in_ucode_mode_or1d_b => i_afd_in_ucode_mode_or1d_b_t3, + ifdp_is2_est_bubble3 => ifdp_is2_est_bubble3_t3, + ifdp_is2_bypsel => i_afd_is2_bypsel_t3, + axu_dbg_data => axu_dbg_data_t3 +); +slice_id0(0 to 1) <= "00"; +slice_id1(0 to 1) <= "01"; +slice_id2(0 to 1) <= "10"; +slice_id3(0 to 1) <= "11"; +iuq_fxu_issue0 : entity work.iuq_fxu_issue +generic map(expand_type => expand_type) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_iu_func_sl_thold_2 => pc_iu_func_sl_thold_2(1), + pc_iu_sg_2 => pc_iu_sg_2(1), + clkoff_b => clkoff_b(1), + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b(1), + tc_ac_ccflush_dc => tc_ac_ccflush_dc, + delay_lclkr => delay_lclkr(9), + mpw1_b => mpw1_b(9), + scan_in => iuq_fi_scan_in, + scan_out => iuq_fi_scan_out, + fiss_dbg_data => fiss_dbg_data, + pc_iu_trace_bus_enable => pc_iu_trace_bus_enable, + pc_iu_event_bus_enable => pc_iu_event_bus_enable, + fiss_perf_event_t0 => fiss_perf_event_t0, + fiss_perf_event_t1 => fiss_perf_event_t1, + fiss_perf_event_t2 => fiss_perf_event_t2, + fiss_perf_event_t3 => fiss_perf_event_t3, + xu_iu_need_hole => xu_iu_need_hole, + xu_iu_xucr0_rel => xu_iu_xucr0_rel, + an_ac_reld_data_vld => an_ac_reld_data_vld_clone, + an_ac_reld_core_tag => an_ac_reld_core_tag_clone(1 to 4), + an_ac_reld_ditc => an_ac_reld_ditc_clone, + an_ac_reld_data_coming => an_ac_reld_data_coming_clone, + an_ac_back_inv => an_ac_back_inv, + an_ac_back_inv_target => an_ac_back_inv_target(1), + fiss_uc_is2_ucode_vld => fiss_uc_is2_ucode_vld, + fdep_fiss_t0_is2_instr => fdep_fiss_t0_is2_instr, + fdep_fiss_t0_is2_ta_vld => fdep_fiss_t0_is2_ta_vld, + fdep_fiss_t0_is2_ta => fdep_fiss_t0_is2_ta, + fdep_fiss_t0_is2_s1_vld => fdep_fiss_t0_is2_s1_vld, + fdep_fiss_t0_is2_s1 => fdep_fiss_t0_is2_s1, + fdep_fiss_t0_is2_s2_vld => fdep_fiss_t0_is2_s2_vld, + fdep_fiss_t0_is2_s2 => fdep_fiss_t0_is2_s2, + fdep_fiss_t0_is2_s3_vld => fdep_fiss_t0_is2_s3_vld, + fdep_fiss_t0_is2_s3 => fdep_fiss_t0_is2_s3, + fdep_fiss_t0_is2_pred_update => fdep_fiss_t0_is2_pred_update, + fdep_fiss_t0_is2_pred_taken_cnt => fdep_fiss_t0_is2_pred_taken_cnt, + fdep_fiss_t0_is2_gshare => fdep_fiss_t0_is2_gshare, + fdep_fiss_t0_is2_ifar => fdep_fiss_t0_is2_ifar, + fdep_fiss_t0_is2_error => fdep_fiss_t0_is2_error, + fdep_fiss_t0_is2_axu_ld_or_st => fdep_fiss_t0_is2_axu_ld_or_st, + fdep_fiss_t0_is2_axu_store => fdep_fiss_t0_is2_axu_store, + fdep_fiss_t0_is2_axu_ldst_size => fdep_fiss_t0_is2_axu_ldst_size, + fdep_fiss_t0_is2_axu_ldst_tag => fdep_fiss_t0_is2_axu_ldst_tag, + fdep_fiss_t0_is2_axu_ldst_indexed=> fdep_fiss_t0_is2_axu_ldst_indexed, + fdep_fiss_t0_is2_axu_ldst_update => fdep_fiss_t0_is2_axu_ldst_update, + fdep_fiss_t0_is2_axu_ldst_extpid => fdep_fiss_t0_is2_axu_ldst_extpid, + fdep_fiss_t0_is2_axu_ldst_forcealign => fdep_fiss_t0_is2_axu_ldst_forcealign, + fdep_fiss_t0_is2_axu_ldst_forceexcept => fdep_fiss_t0_is2_axu_ldst_forceexcept, + fdep_fiss_t0_is2_axu_mftgpr => fdep_fiss_t0_is2_axu_mftgpr, + fdep_fiss_t0_is2_axu_mffgpr => fdep_fiss_t0_is2_axu_mffgpr, + fdep_fiss_t0_is2_axu_movedp => fdep_fiss_t0_is2_axu_movedp, + fdep_fiss_t0_is2_axu_instr_type => fdep_fiss_t0_is2_axu_instr_type, + fdep_fiss_t0_is2_match => fdep_fiss_t0_is2_match, + fdep_fiss_t0_is2_2ucode => fdep_fiss_t0_is2_2ucode, + fdep_fiss_t0_is2_2ucode_type => fdep_fiss_t0_is2_2ucode_type, + fdep_fiss_t0_is2_hole_delay => fdep_fiss_t0_is2_hole_delay, + fdep_fiss_t0_is2_to_ucode => fdep_fiss_t0_is2_to_ucode, + fdep_fiss_t0_is2_is_ucode => fdep_fiss_t0_is2_is_ucode, + fdep_fiss_t0_is2early_vld => fdep_fiss_t0_is2early_vld, + fdep_fiss_t0_is1_xu_dep_hit_b => fdep_fiss_t0_is1_xu_dep_hit_b, + fdep_fiss_t1_is2_instr => fdep_fiss_t1_is2_instr, + fdep_fiss_t1_is2_ta_vld => fdep_fiss_t1_is2_ta_vld, + fdep_fiss_t1_is2_ta => fdep_fiss_t1_is2_ta, + fdep_fiss_t1_is2_s1_vld => fdep_fiss_t1_is2_s1_vld, + fdep_fiss_t1_is2_s1 => fdep_fiss_t1_is2_s1, + fdep_fiss_t1_is2_s2_vld => fdep_fiss_t1_is2_s2_vld, + fdep_fiss_t1_is2_s2 => fdep_fiss_t1_is2_s2, + fdep_fiss_t1_is2_s3_vld => fdep_fiss_t1_is2_s3_vld, + fdep_fiss_t1_is2_s3 => fdep_fiss_t1_is2_s3, + fdep_fiss_t1_is2_pred_update => fdep_fiss_t1_is2_pred_update, + fdep_fiss_t1_is2_pred_taken_cnt => fdep_fiss_t1_is2_pred_taken_cnt, + fdep_fiss_t1_is2_gshare => fdep_fiss_t1_is2_gshare, + fdep_fiss_t1_is2_ifar => fdep_fiss_t1_is2_ifar, + fdep_fiss_t1_is2_error => fdep_fiss_t1_is2_error, + fdep_fiss_t1_is2_axu_ld_or_st => fdep_fiss_t1_is2_axu_ld_or_st, + fdep_fiss_t1_is2_axu_store => fdep_fiss_t1_is2_axu_store, + fdep_fiss_t1_is2_axu_ldst_size => fdep_fiss_t1_is2_axu_ldst_size, + fdep_fiss_t1_is2_axu_ldst_tag => fdep_fiss_t1_is2_axu_ldst_tag, + fdep_fiss_t1_is2_axu_ldst_indexed=> fdep_fiss_t1_is2_axu_ldst_indexed, + fdep_fiss_t1_is2_axu_ldst_update => fdep_fiss_t1_is2_axu_ldst_update, + fdep_fiss_t1_is2_axu_ldst_extpid => fdep_fiss_t1_is2_axu_ldst_extpid, + fdep_fiss_t1_is2_axu_ldst_forcealign => fdep_fiss_t1_is2_axu_ldst_forcealign, + fdep_fiss_t1_is2_axu_ldst_forceexcept => fdep_fiss_t1_is2_axu_ldst_forceexcept, + fdep_fiss_t1_is2_axu_mftgpr => fdep_fiss_t1_is2_axu_mftgpr, + fdep_fiss_t1_is2_axu_mffgpr => fdep_fiss_t1_is2_axu_mffgpr, + fdep_fiss_t1_is2_axu_movedp => fdep_fiss_t1_is2_axu_movedp, + fdep_fiss_t1_is2_axu_instr_type => fdep_fiss_t1_is2_axu_instr_type, + fdep_fiss_t1_is2_match => fdep_fiss_t1_is2_match, + fdep_fiss_t1_is2_2ucode => fdep_fiss_t1_is2_2ucode, + fdep_fiss_t1_is2_2ucode_type => fdep_fiss_t1_is2_2ucode_type, + fdep_fiss_t1_is2_hole_delay => fdep_fiss_t1_is2_hole_delay, + fdep_fiss_t1_is2_to_ucode => fdep_fiss_t1_is2_to_ucode, + fdep_fiss_t1_is2_is_ucode => fdep_fiss_t1_is2_is_ucode, + fdep_fiss_t1_is2early_vld => fdep_fiss_t1_is2early_vld, + fdep_fiss_t1_is1_xu_dep_hit_b => fdep_fiss_t1_is1_xu_dep_hit_b, + fdep_fiss_t2_is2_instr => fdep_fiss_t2_is2_instr, + fdep_fiss_t2_is2_ta_vld => fdep_fiss_t2_is2_ta_vld, + fdep_fiss_t2_is2_ta => fdep_fiss_t2_is2_ta, + fdep_fiss_t2_is2_s1_vld => fdep_fiss_t2_is2_s1_vld, + fdep_fiss_t2_is2_s1 => fdep_fiss_t2_is2_s1, + fdep_fiss_t2_is2_s2_vld => fdep_fiss_t2_is2_s2_vld, + fdep_fiss_t2_is2_s2 => fdep_fiss_t2_is2_s2, + fdep_fiss_t2_is2_s3_vld => fdep_fiss_t2_is2_s3_vld, + fdep_fiss_t2_is2_s3 => fdep_fiss_t2_is2_s3, + fdep_fiss_t2_is2_pred_update => fdep_fiss_t2_is2_pred_update, + fdep_fiss_t2_is2_pred_taken_cnt => fdep_fiss_t2_is2_pred_taken_cnt, + fdep_fiss_t2_is2_gshare => fdep_fiss_t2_is2_gshare, + fdep_fiss_t2_is2_ifar => fdep_fiss_t2_is2_ifar, + fdep_fiss_t2_is2_error => fdep_fiss_t2_is2_error, + fdep_fiss_t2_is2_axu_ld_or_st => fdep_fiss_t2_is2_axu_ld_or_st, + fdep_fiss_t2_is2_axu_store => fdep_fiss_t2_is2_axu_store, + fdep_fiss_t2_is2_axu_ldst_size => fdep_fiss_t2_is2_axu_ldst_size, + fdep_fiss_t2_is2_axu_ldst_tag => fdep_fiss_t2_is2_axu_ldst_tag, + fdep_fiss_t2_is2_axu_ldst_indexed=> fdep_fiss_t2_is2_axu_ldst_indexed, + fdep_fiss_t2_is2_axu_ldst_update => fdep_fiss_t2_is2_axu_ldst_update, + fdep_fiss_t2_is2_axu_ldst_extpid => fdep_fiss_t2_is2_axu_ldst_extpid, + fdep_fiss_t2_is2_axu_ldst_forcealign => fdep_fiss_t2_is2_axu_ldst_forcealign, + fdep_fiss_t2_is2_axu_ldst_forceexcept => fdep_fiss_t2_is2_axu_ldst_forceexcept, + fdep_fiss_t2_is2_axu_mftgpr => fdep_fiss_t2_is2_axu_mftgpr, + fdep_fiss_t2_is2_axu_mffgpr => fdep_fiss_t2_is2_axu_mffgpr, + fdep_fiss_t2_is2_axu_movedp => fdep_fiss_t2_is2_axu_movedp, + fdep_fiss_t2_is2_axu_instr_type => fdep_fiss_t2_is2_axu_instr_type, + fdep_fiss_t2_is2_match => fdep_fiss_t2_is2_match, + fdep_fiss_t2_is2_2ucode => fdep_fiss_t2_is2_2ucode, + fdep_fiss_t2_is2_2ucode_type => fdep_fiss_t2_is2_2ucode_type, + fdep_fiss_t2_is2_hole_delay => fdep_fiss_t2_is2_hole_delay, + fdep_fiss_t2_is2_to_ucode => fdep_fiss_t2_is2_to_ucode, + fdep_fiss_t2_is2_is_ucode => fdep_fiss_t2_is2_is_ucode, + fdep_fiss_t2_is2early_vld => fdep_fiss_t2_is2early_vld, + fdep_fiss_t2_is1_xu_dep_hit_b => fdep_fiss_t2_is1_xu_dep_hit_b, + fdep_fiss_t3_is2_instr => fdep_fiss_t3_is2_instr, + fdep_fiss_t3_is2_ta_vld => fdep_fiss_t3_is2_ta_vld, + fdep_fiss_t3_is2_ta => fdep_fiss_t3_is2_ta, + fdep_fiss_t3_is2_s1_vld => fdep_fiss_t3_is2_s1_vld, + fdep_fiss_t3_is2_s1 => fdep_fiss_t3_is2_s1, + fdep_fiss_t3_is2_s2_vld => fdep_fiss_t3_is2_s2_vld, + fdep_fiss_t3_is2_s2 => fdep_fiss_t3_is2_s2, + fdep_fiss_t3_is2_s3_vld => fdep_fiss_t3_is2_s3_vld, + fdep_fiss_t3_is2_s3 => fdep_fiss_t3_is2_s3, + fdep_fiss_t3_is2_pred_update => fdep_fiss_t3_is2_pred_update, + fdep_fiss_t3_is2_pred_taken_cnt => fdep_fiss_t3_is2_pred_taken_cnt, + fdep_fiss_t3_is2_gshare => fdep_fiss_t3_is2_gshare, + fdep_fiss_t3_is2_ifar => fdep_fiss_t3_is2_ifar, + fdep_fiss_t3_is2_error => fdep_fiss_t3_is2_error, + fdep_fiss_t3_is2_axu_ld_or_st => fdep_fiss_t3_is2_axu_ld_or_st, + fdep_fiss_t3_is2_axu_store => fdep_fiss_t3_is2_axu_store, + fdep_fiss_t3_is2_axu_ldst_size => fdep_fiss_t3_is2_axu_ldst_size, + fdep_fiss_t3_is2_axu_ldst_tag => fdep_fiss_t3_is2_axu_ldst_tag, + fdep_fiss_t3_is2_axu_ldst_indexed=> fdep_fiss_t3_is2_axu_ldst_indexed, + fdep_fiss_t3_is2_axu_ldst_update => fdep_fiss_t3_is2_axu_ldst_update, + fdep_fiss_t3_is2_axu_ldst_extpid => fdep_fiss_t3_is2_axu_ldst_extpid, + fdep_fiss_t3_is2_axu_ldst_forcealign => fdep_fiss_t3_is2_axu_ldst_forcealign, + fdep_fiss_t3_is2_axu_ldst_forceexcept => fdep_fiss_t3_is2_axu_ldst_forceexcept, + fdep_fiss_t3_is2_axu_mftgpr => fdep_fiss_t3_is2_axu_mftgpr, + fdep_fiss_t3_is2_axu_mffgpr => fdep_fiss_t3_is2_axu_mffgpr, + fdep_fiss_t3_is2_axu_movedp => fdep_fiss_t3_is2_axu_movedp, + fdep_fiss_t3_is2_axu_instr_type => fdep_fiss_t3_is2_axu_instr_type, + fdep_fiss_t3_is2_match => fdep_fiss_t3_is2_match, + fdep_fiss_t3_is2_2ucode => fdep_fiss_t3_is2_2ucode, + fdep_fiss_t3_is2_2ucode_type => fdep_fiss_t3_is2_2ucode_type, + fdep_fiss_t3_is2_hole_delay => fdep_fiss_t3_is2_hole_delay, + fdep_fiss_t3_is2_to_ucode => fdep_fiss_t3_is2_to_ucode, + fdep_fiss_t3_is2_is_ucode => fdep_fiss_t3_is2_is_ucode, + fdep_fiss_t3_is2early_vld => fdep_fiss_t3_is2early_vld, + fdep_fiss_t3_is1_xu_dep_hit_b => fdep_fiss_t3_is1_xu_dep_hit_b, + fiss_fdep_is2_take0 => fiss_fdep_is2_take0, + fiss_fdep_is2_take1 => fiss_fdep_is2_take1, + fiss_fdep_is2_take2 => fiss_fdep_is2_take2, + fiss_fdep_is2_take3 => fiss_fdep_is2_take3, + spr_issue_high_mask => spr_issue_high_mask, + spr_issue_med_mask => spr_issue_med_mask, + spr_fiss_count0_max => spr_fiss_count0_max, + spr_fiss_count1_max => spr_fiss_count1_max, + spr_fiss_count2_max => spr_fiss_count2_max, + spr_fiss_count3_max => spr_fiss_count3_max, + spr_fiss_pri_rand => spr_fiss_pri_rand, + spr_fiss_pri_rand_always => spr_fiss_pri_rand_always, + spr_fiss_pri_rand_flush => spr_fiss_pri_rand_flush, + iu_au_hi_pri_mask => iu_au_hi_pri_mask, + iu_au_md_pri_mask => iu_au_md_pri_mask, + i_afi_is2_take_t => i_afi_is2_take_t, + i_afd_is2_t0_instr_v => i_afd_is2_t0_instr_v, + i_afd_is2_t1_instr_v => i_afd_is2_t1_instr_v, + i_afd_is2_t2_instr_v => i_afd_is2_t2_instr_v, + i_afd_is2_t3_instr_v => i_afd_is2_t3_instr_v, + i_axu_is1_dep_hit_t0_b => i_axu_is1_dep_hit_t0_b, + i_axu_is1_dep_hit_t1_b => i_axu_is1_dep_hit_t1_b, + i_axu_is1_dep_hit_t2_b => i_axu_is1_dep_hit_t2_b, + i_axu_is1_dep_hit_t3_b => i_axu_is1_dep_hit_t3_b, + xu_iu_is2_flush_tid => xu_iu_flush, + xu_iu_rf0_flush_tid => xu_iu_flush, + xu_iu_rf1_flush_tid => xu_rf1_flush, + xu_iu_ex1_flush_tid => xu_ex1_flush, + xu_iu_ex2_flush_tid => xu_ex2_flush, + xu_iu_ex3_flush_tid => xu_ex3_flush, + xu_iu_ex4_flush_tid => xu_ex4_flush, + xu_iu_ex5_flush_tid => xu_ex5_flush, + xu_iu_ex5_ppc_cpl => xu_iu_ex5_ppc_cpl, + iu_xu_is2_vld => iu_xu_is2_vld_internal, + iu_xu_is2_tid => iu_xu_is2_tid_internal, + iu_xu_is2_instr => iu_xu_is2_instr_internal, + iu_xu_is2_ta_vld => iu_xu_is2_ta_vld, + iu_xu_is2_ta => iu_xu_is2_ta, + iu_xu_is2_s1_vld => iu_xu_is2_s1_vld, + iu_xu_is2_s1 => iu_xu_is2_s1, + iu_xu_is2_s2_vld => iu_xu_is2_s2_vld, + iu_xu_is2_s2 => iu_xu_is2_s2, + iu_xu_is2_s3_vld => iu_xu_is2_s3_vld, + iu_xu_is2_s3 => iu_xu_is2_s3, + iu_xu_is2_pred_update => iu_xu_is2_pred_update_internal, + iu_xu_is2_pred_taken_cnt => iu_xu_is2_pred_taken_cnt_internal, + iu_xu_is2_gshare => iu_xu_is2_gshare, + iu_xu_is2_ifar => iu_xu_is2_ifar_internal, + iu_xu_is2_error => iu_xu_is2_error_internal, + iu_xu_is2_is_ucode => iu_xu_is2_is_ucode, + iu_xu_is2_match => iu_xu_is2_match, + fiss_uc_is2_2ucode => fiss_uc_is2_2ucode, + fiss_uc_is2_2ucode_type => fiss_uc_is2_2ucode_type, + iu_xu_is2_axu_ldst_update => iu_xu_is2_axu_ldst_update, + iu_xu_is2_axu_ldst_extpid => iu_xu_is2_axu_ldst_extpid, + iu_xu_is2_axu_ldst_forcealign => iu_xu_is2_axu_ldst_forcealign, + iu_xu_is2_axu_ldst_forceexcept => iu_xu_is2_axu_ldst_forceexcept, + iu_xu_is2_axu_mftgpr => iu_xu_is2_axu_mftgpr, + iu_xu_is2_axu_mffgpr => iu_xu_is2_axu_mffgpr, + iu_xu_is2_axu_movedp => iu_xu_is2_axu_movedp, + iu_xu_is2_axu_instr_type => iu_xu_is2_axu_instr_type, + iu_xu_is2_axu_ld_or_st => iu_xu_is2_axu_ld_or_st, + iu_xu_is2_axu_store => iu_xu_is2_axu_store_internal, + iu_xu_is2_axu_ldst_size => iu_xu_is2_axu_ldst_size, + iu_xu_is2_axu_ldst_tag => iu_xu_is2_axu_ldst_tag, + iu_xu_is2_axu_ldst_indexed => iu_xu_is2_axu_ldst_indexed, + iu_fu_rf0_str_val => iu_fu_rf0_str_val, + iu_fu_rf0_ldst_val => iu_fu_rf0_ldst_val, + iu_fu_rf0_ldst_tid => iu_fu_rf0_ldst_tid, + iu_fu_rf0_ldst_tag => iu_fu_rf0_ldst_tag +); +iuq_axu_fu_iss0 : entity work.iuq_axu_fu_iss +generic map(expand_type => expand_type, + fpr_addr_width => fpr_addr_width) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + i_iss_si => iuq_ai_scan_in, + i_iss_so => iuq_ai_scan_out, + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b(2), + pc_iu_func_sl_thold_2 => pc_iu_func_sl_thold_2(2), + pc_iu_sg_2 => pc_iu_sg_2(2), + clkoff_b => clkoff_b(2), + tc_ac_ccflush_dc => tc_ac_ccflush_dc, + delay_lclkr => delay_lclkr(14), + mpw1_b => mpw1_b(14), + iu_au_is1_flush => xu_iu_flush, + xu_iu_is2_flush => xu_iu_flush, + uc_flush => uc_flush_tid, + i_afd_config_iucr_t0 => iu_au_config_iucr_pt_t0(2 to 4), + i_afd_config_iucr_t1 => iu_au_config_iucr_pt_t1(2 to 4), + i_afd_config_iucr_t2 => iu_au_config_iucr_pt_t2(2 to 4), + i_afd_config_iucr_t3 => iu_au_config_iucr_pt_t3(2 to 4), + i_afd_in_ucode_mode_or1d_b_t0 => i_afd_in_ucode_mode_or1d_b_t0, + i_afd_in_ucode_mode_or1d_b_t1 => i_afd_in_ucode_mode_or1d_b_t1, + i_afd_in_ucode_mode_or1d_b_t2 => i_afd_in_ucode_mode_or1d_b_t2, + i_afd_in_ucode_mode_or1d_b_t3 => i_afd_in_ucode_mode_or1d_b_t3, + i_axu_is2_instr_match_t0 => i_axu_is2_instr_match_t0, + i_axu_is2_instr_match_t1 => i_axu_is2_instr_match_t1, + i_axu_is2_instr_match_t2 => i_axu_is2_instr_match_t2, + i_axu_is2_instr_match_t3 => i_axu_is2_instr_match_t3, + i_afd_is2_is_ucode_t0 => i_afd_is2_is_ucode_t0, + i_afd_is2_is_ucode_t1 => i_afd_is2_is_ucode_t1, + i_afd_is2_is_ucode_t2 => i_afd_is2_is_ucode_t2, + i_afd_is2_is_ucode_t3 => i_afd_is2_is_ucode_t3, + i_afd_ignore_flush_is2_t0 => i_afd_ignore_flush_is2_t0, + i_afd_ignore_flush_is2_t1 => i_afd_ignore_flush_is2_t1, + i_afd_ignore_flush_is2_t2 => i_afd_ignore_flush_is2_t2, + i_afd_ignore_flush_is2_t3 => i_afd_ignore_flush_is2_t3, + i_afd_is2_t0_instr_v => i_afd_is2_t0_instr_v, + i_afd_is2_t1_instr_v => i_afd_is2_t1_instr_v, + i_afd_is2_t2_instr_v => i_afd_is2_t2_instr_v, + i_afd_is2_t3_instr_v => i_afd_is2_t3_instr_v, + i_axu_is1_early_v_t0 => i_axu_is1_early_v_t0, + i_axu_is1_early_v_t1 => i_axu_is1_early_v_t1, + i_axu_is1_early_v_t2 => i_axu_is1_early_v_t2, + i_axu_is1_early_v_t3 => i_axu_is1_early_v_t3, + i_afd_is2_t0_instr => fdep_fiss_t0_is2_instr, + i_afd_is2_t1_instr => fdep_fiss_t1_is2_instr, + i_afd_is2_t2_instr => fdep_fiss_t2_is2_instr, + i_afd_is2_t3_instr => fdep_fiss_t3_is2_instr, + i_afd_is2_fra_t0 => i_afd_is2_fra_t0, + i_afd_is2_fra_t1 => i_afd_is2_fra_t1, + i_afd_is2_fra_t2 => i_afd_is2_fra_t2, + i_afd_is2_fra_t3 => i_afd_is2_fra_t3, + i_afd_is2_frb_t0 => i_afd_is2_frb_t0, + i_afd_is2_frb_t1 => i_afd_is2_frb_t1, + i_afd_is2_frb_t2 => i_afd_is2_frb_t2, + i_afd_is2_frb_t3 => i_afd_is2_frb_t3, + i_afd_is2_frc_t0 => i_afd_is2_frc_t0, + i_afd_is2_frc_t1 => i_afd_is2_frc_t1, + i_afd_is2_frc_t2 => i_afd_is2_frc_t2, + i_afd_is2_frc_t3 => i_afd_is2_frc_t3, + i_afd_is2_frt_t0 => i_afd_is2_frt_t0, + i_afd_is2_frt_t1 => i_afd_is2_frt_t1, + i_afd_is2_frt_t2 => i_afd_is2_frt_t2, + i_afd_is2_frt_t3 => i_afd_is2_frt_t3, + i_afd_is2_fra_v_t0 => i_afd_is2_fra_v_t0, + i_afd_is2_fra_v_t1 => i_afd_is2_fra_v_t1, + i_afd_is2_fra_v_t2 => i_afd_is2_fra_v_t2, + i_afd_is2_fra_v_t3 => i_afd_is2_fra_v_t3, + i_afd_is2_frb_v_t0 => i_afd_is2_frb_v_t0, + i_afd_is2_frb_v_t1 => i_afd_is2_frb_v_t1, + i_afd_is2_frb_v_t2 => i_afd_is2_frb_v_t2, + i_afd_is2_frb_v_t3 => i_afd_is2_frb_v_t3, + i_afd_is2_frc_v_t0 => i_afd_is2_frc_v_t0, + i_afd_is2_frc_v_t1 => i_afd_is2_frc_v_t1, + i_afd_is2_frc_v_t2 => i_afd_is2_frc_v_t2, + i_afd_is2_frc_v_t3 => i_afd_is2_frc_v_t3, + i_afd_is2_bypsel_t0 => i_afd_is2_bypsel_t0, + i_afd_is2_bypsel_t1 => i_afd_is2_bypsel_t1, + i_afd_is2_bypsel_t2 => i_afd_is2_bypsel_t2, + i_afd_is2_bypsel_t3 => i_afd_is2_bypsel_t3, + i_afd_is2_ifar_t0 => fdep_fiss_t0_is2_ifar, + i_afd_is2_ifar_t1 => fdep_fiss_t1_is2_ifar, + i_afd_is2_ifar_t2 => fdep_fiss_t2_is2_ifar, + i_afd_is2_ifar_t3 => fdep_fiss_t3_is2_ifar, + ifdp_is2_est_bubble3_t0 => ifdp_is2_est_bubble3_t0, + ifdp_is2_est_bubble3_t1 => ifdp_is2_est_bubble3_t1, + ifdp_is2_est_bubble3_t2 => ifdp_is2_est_bubble3_t2, + ifdp_is2_est_bubble3_t3 => ifdp_is2_est_bubble3_t3, + iu_au_hi_pri_mask => iu_au_hi_pri_mask, + iu_au_md_pri_mask => iu_au_md_pri_mask, + spr_fiss_pri_rand => spr_fiss_pri_rand, + spr_fiss_pri_rand_always => spr_fiss_pri_rand_always, + spr_fiss_pri_rand_flush => spr_fiss_pri_rand_flush, + iu_is2_take_t => i_afi_is2_take_t, + i_axu_is1_dep_hit_t0_b => i_axu_is1_dep_hit_t0_b, + i_axu_is1_dep_hit_t1_b => i_axu_is1_dep_hit_t1_b, + i_axu_is1_dep_hit_t2_b => i_axu_is1_dep_hit_t2_b, + i_axu_is1_dep_hit_t3_b => i_axu_is1_dep_hit_t3_b, + iu_fu_is2_tid_decode => iu_fu_is2_tid_decode, + iu_fu_rf0_ucfmul => iu_fu_rf0_ucfmul, + iu_fu_rf0_instr_match => iu_fu_rf0_instr_match, + iu_fu_rf0_is_ucode => iu_fu_rf0_is_ucode, + iu_fu_rf0_instr => iu_fu_rf0_instr, + iu_fu_rf0_instr_v => iu_fu_rf0_instr_v, + iu_fu_rf0_fra => iu_fu_rf0_fra, + iu_fu_rf0_frb => iu_fu_rf0_frb, + iu_fu_rf0_frc => iu_fu_rf0_frc, + iu_fu_rf0_frt => iu_fu_rf0_frt, + iu_fu_rf0_fra_v => iu_fu_rf0_fra_v, + iu_fu_rf0_frb_v => iu_fu_rf0_frb_v, + iu_fu_rf0_frc_v => iu_fu_rf0_frc_v, + iu_fu_rf0_tid => iu_fu_rf0_tid, + iu_fu_rf0_bypsel => iu_fu_rf0_bypsel, + iu_fu_rf0_ifar => iu_fu_rf0_ifar, + fu_iss_debug => fu_iss_dbg_data +); +end iuq_slice_wrap; diff --git a/rel/src/vhdl/work/iuq_spr.vhdl b/rel/src/vhdl/work/iuq_spr.vhdl new file mode 100644 index 0000000..3eba6af --- /dev/null +++ b/rel/src/vhdl/work/iuq_spr.vhdl @@ -0,0 +1,1795 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; +use ieee.std_logic_1164.all; + +library ibm; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; + +library support; +use support.power_logic_pkg.all; + +library tri; +use tri.tri_latches_pkg.all; + +library work; +use work.iuq_pkg.all; + +entity iuq_spr is +generic(regmode : integer := 6; + a2mode : integer := 1; + expand_type : integer := 2 ); -- 0 = ibm umbra, 1 = xilinx, 2 = ibm mpg +port( + vdd : inout power_logic; + gnd : inout power_logic; + + -- inputs from mm + slowspr_val_in : in std_ulogic; + slowspr_rw_in : in std_ulogic; + slowspr_etid_in : in std_ulogic_vector(0 to 1); + slowspr_addr_in : in std_ulogic_vector(0 to 9); + slowspr_data_in : in std_ulogic_vector(64-(2**regmode) to 63); + slowspr_done_in : in std_ulogic; + + -- outputs to pervasive + slowspr_val_out : out std_ulogic; + slowspr_rw_out : out std_ulogic; + slowspr_etid_out : out std_ulogic_vector(0 to 1); + slowspr_addr_out : out std_ulogic_vector(0 to 9); + slowspr_data_out : out std_ulogic_vector(64-(2**regmode) to 63); + slowspr_done_out : out std_ulogic; + + spr_ic_idir_read : out std_ulogic; + spr_ic_idir_way : out std_ulogic_vector(0 to 1); + spr_ic_idir_row : out std_ulogic_vector(52 to 57); + ic_spr_idir_done : in std_ulogic; + ic_spr_idir_lru : in std_ulogic_vector(0 to 2); + ic_spr_idir_parity : in std_ulogic_vector(0 to 3); + ic_spr_idir_endian : in std_ulogic; + ic_spr_idir_valid : in std_ulogic; + ic_spr_idir_tag : in std_ulogic_vector(0 to 29); + + spr_ic_icbi_ack_en : out std_ulogic; + spr_ic_cls : out std_ulogic; + spr_ic_clockgate_dis : out std_ulogic_vector(0 to 1); + + -- Signals for branch prediction enable + spr_ic_bp_config : out std_ulogic_vector(0 to 3); + spr_bp_config : out std_ulogic_vector(0 to 3); + spr_bp_gshare_mask : out std_ulogic_vector(0 to 3); + + -- decoder match/mask + spr_dec_mask : out std_ulogic_vector(0 to 31); + spr_dec_match : out std_ulogic_vector(0 to 31); + + --axu config + iu_au_config_iucr_t0 : out std_ulogic_vector(0 to 7); + iu_au_config_iucr_t1 : out std_ulogic_vector(0 to 7); + iu_au_config_iucr_t2 : out std_ulogic_vector(0 to 7); + iu_au_config_iucr_t3 : out std_ulogic_vector(0 to 7); + + + -- Need to add in all erat signals + + -- XU issue priority + spr_issue_high_mask : out std_ulogic_vector(0 to 3); + spr_issue_med_mask : out std_ulogic_vector(0 to 3); + spr_fiss_count0_max : out std_ulogic_vector(0 to 5); + spr_fiss_count1_max : out std_ulogic_vector(0 to 5); + spr_fiss_count2_max : out std_ulogic_vector(0 to 5); + spr_fiss_count3_max : out std_ulogic_vector(0 to 5); + + spr_ic_pri_rand : out std_ulogic_vector(0 to 4); + spr_ic_pri_rand_always : out std_ulogic; + spr_ic_pri_rand_flush : out std_ulogic; + + spr_fiss_pri_rand : out std_ulogic_vector(0 to 4); + spr_fiss_pri_rand_always : out std_ulogic; + spr_fiss_pri_rand_flush : out std_ulogic; + + spr_fdep_ll_hold : out std_ulogic; + + + xu_iu_run_thread : in std_ulogic_vector(0 to 3); + + xu_iu_ex6_pri : in std_ulogic_vector(0 to 2); + xu_iu_ex6_pri_val : in std_ulogic_vector(0 to 3); + + xu_iu_raise_iss_pri : in std_ulogic_vector(0 to 3); + xu_iu_msr_gs : in std_ulogic_vector(0 to 3); + xu_iu_msr_pr : in std_ulogic_vector(0 to 3); + + --pervasive + nclk : in clk_logic; + pc_iu_sg_2 : in std_ulogic; + pc_iu_func_sl_thold_2 : in std_ulogic; + pc_iu_cfg_sl_thold_2 : in std_ulogic; + clkoff_b : in std_ulogic; + act_dis : in std_ulogic; + tc_ac_ccflush_dc : in std_ulogic; + d_mode : in std_ulogic; + delay_lclkr : in std_ulogic; + mpw1_b : in std_ulogic; + mpw2_b : in std_ulogic; + ccfg_scan_in : in std_ulogic; + ccfg_scan_out : out std_ulogic; + bcfg_scan_in : in std_ulogic; + bcfg_scan_out : out std_ulogic; + dcfg_scan_in : in std_ulogic; + dcfg_scan_out : out std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic +); + +-- synopsys translate_off + + +-- synopsys translate_on + +end iuq_spr; +---- +architecture iuq_spr of iuq_spr is + +---------------------------- +-- constants +---------------------------- + +--scan chain +constant ll_trig_rnd_offset : natural := 0; +constant ll_trig_cnt_offset : natural := ll_trig_rnd_offset + 14; +constant ll_hold_cnt_offset : natural := ll_trig_cnt_offset + 18; +constant xu_iu_run_thread_offset : natural := ll_hold_cnt_offset + 10; +constant xu_iu_ex6_pri_offset : natural := xu_iu_run_thread_offset + 4; +constant xu_iu_ex6_pri_val_offset : natural := xu_iu_ex6_pri_offset + 3; +constant xu_iu_raise_iss_pri_offset : natural := xu_iu_ex6_pri_val_offset + 4; +constant xu_iu_msr_gs_offset : natural := xu_iu_raise_iss_pri_offset + 4; +constant xu_iu_msr_pr_offset : natural := xu_iu_msr_gs_offset + 4; +constant slowspr_val_offset : natural := xu_iu_msr_pr_offset + 4; +constant slowspr_rw_offset : natural := slowspr_val_offset + 1; +constant slowspr_etid_offset : natural := slowspr_rw_offset + 1; +constant slowspr_addr_offset : natural := slowspr_etid_offset + 2; +constant slowspr_data_offset : natural := slowspr_addr_offset + 10; +constant slowspr_done_offset : natural := slowspr_data_offset + 2**regmode; +constant iu_slowspr_val_offset : natural := slowspr_done_offset + 1; +constant iu_slowspr_rw_offset : natural := iu_slowspr_val_offset + 1; +constant iu_slowspr_etid_offset : natural := iu_slowspr_rw_offset + 1; +constant iu_slowspr_addr_offset : natural := iu_slowspr_etid_offset + 2; +constant iu_slowspr_data_offset : natural := iu_slowspr_addr_offset + 10; +constant iu_slowspr_done_offset : natural := iu_slowspr_data_offset + 2**regmode; +constant immr0_offset : natural := iu_slowspr_done_offset + 1; +constant imr0_offset : natural := immr0_offset + 32; +constant iulfsr_offset : natural := imr0_offset + 32; +constant iudbg0_offset : natural := iulfsr_offset + 32; +constant iudbg1_offset : natural := iudbg0_offset + 8; +constant iudbg2_offset : natural := iudbg1_offset + 11; +constant iudbg0_exec_offset : natural := iudbg2_offset + 30; +constant iudbg0_done_offset : natural := iudbg0_exec_offset + 1; +constant spare_offset : natural := iudbg0_done_offset + 1; +constant scan_right : natural := spare_offset + 4 - 1; + +constant iullcr_offset : natural := 0; +constant iucr0_offset : natural := iullcr_offset + 18; +constant iucr1_t0_offset : natural := iucr0_offset + 16; +constant iucr1_t1_offset : natural := iucr1_t0_offset + 14; +constant iucr1_t2_offset : natural := iucr1_t1_offset + 14; +constant iucr1_t3_offset : natural := iucr1_t2_offset + 14; +constant iucr2_t0_offset : natural := iucr1_t3_offset + 14; +constant iucr2_t1_offset : natural := iucr2_t0_offset + 8; +constant iucr2_t2_offset : natural := iucr2_t1_offset + 8; +constant iucr2_t3_offset : natural := iucr2_t2_offset + 8; +constant ppr32_t0_offset : natural := iucr2_t3_offset + 8; +constant ppr32_t1_offset : natural := ppr32_t0_offset + 3; +constant ppr32_t2_offset : natural := ppr32_t1_offset + 3; +constant ppr32_t3_offset : natural := ppr32_t2_offset + 3; +constant ccfg_spare_offset : natural := ppr32_t3_offset + 3; +constant ccfg_scan_right : natural := ccfg_spare_offset + 8 - 1; + + + +constant IMMR0_MASK : std_ulogic_vector(32 to 63) := "11111111111111111111111111111111"; +constant IMR0_MASK : std_ulogic_vector(32 to 63) := "11111111111111111111111111111111"; +constant IULFSR_MASK : std_ulogic_vector(32 to 63) := "11111111111111111111111111111111"; +constant IUDBG0_MASK : std_ulogic_vector(32 to 63) := "00000000000000000011111111000011"; +constant IUDBG1_MASK : std_ulogic_vector(32 to 63) := "00000000000000000000011111111001"; +constant IUDBG2_MASK : std_ulogic_vector(32 to 63) := "00111111111111111111111111111111"; +constant IULLCR_MASK : std_ulogic_vector(32 to 63) := "00000000000000111100001111110001"; +constant IUCR0_MASK : std_ulogic_vector(32 to 63) := "00000000000000001111111111111111"; +constant IUCR1_MASK : std_ulogic_vector(32 to 63) := "00000000000000000011000000111111"; +constant IUCR2_MASK : std_ulogic_vector(32 to 63) := "11111111000000000000000000000000"; +constant PPR32_MASK : std_ulogic_vector(32 to 63) := "00000000000111000000000000000000"; + + +---------------------------- +-- signals +---------------------------- +signal spare_l2 : std_ulogic_vector(0 to 3); +signal ccfg_spare_l2 : std_ulogic_vector(0 to 7); + +signal xu_iu_run_thread_d : std_ulogic_vector(0 to 3); +signal xu_iu_run_thread_l2 : std_ulogic_vector(0 to 3); +signal xu_iu_ex6_pri_d : std_ulogic_vector(0 to 2); +signal xu_iu_ex6_pri_l2 : std_ulogic_vector(0 to 2); +signal xu_iu_ex6_pri_val_d : std_ulogic_vector(0 to 3); +signal xu_iu_ex6_pri_val_l2 : std_ulogic_vector(0 to 3); +signal xu_iu_raise_iss_pri_d : std_ulogic_vector(0 to 3); +signal xu_iu_raise_iss_pri_l2 : std_ulogic_vector(0 to 3); +signal xu_iu_msr_gs_d : std_ulogic_vector(0 to 3); +signal xu_iu_msr_gs_l2 : std_ulogic_vector(0 to 3); +signal xu_iu_msr_pr_d : std_ulogic_vector(0 to 3); +signal xu_iu_msr_pr_l2 : std_ulogic_vector(0 to 3); + +signal slowspr_val_d : std_ulogic; +signal slowspr_val_l2 : std_ulogic; +signal slowspr_rw_d : std_ulogic; +signal slowspr_rw_l2 : std_ulogic; +signal slowspr_etid_d : std_ulogic_vector(0 to 1); +signal slowspr_etid_l2 : std_ulogic_vector(0 to 1); +signal slowspr_addr_d : std_ulogic_vector(0 to 9); +signal slowspr_addr_l2 : std_ulogic_vector(0 to 9); +signal slowspr_data_d : std_ulogic_vector(64-(2**regmode) to 63); +signal slowspr_data_l2 : std_ulogic_vector(64-(2**regmode) to 63); +signal slowspr_done_d : std_ulogic; +signal slowspr_done_l2 : std_ulogic; + +signal iu_slowspr_val_d : std_ulogic; +signal iu_slowspr_val_l2 : std_ulogic; +signal iu_slowspr_rw_d : std_ulogic; +signal iu_slowspr_rw_l2 : std_ulogic; +signal iu_slowspr_etid_d : std_ulogic_vector(0 to 1); +signal iu_slowspr_etid_l2 : std_ulogic_vector(0 to 1); +signal iu_slowspr_addr_d : std_ulogic_vector(0 to 9); +signal iu_slowspr_addr_l2 : std_ulogic_vector(0 to 9); +signal iu_slowspr_data_d : std_ulogic_vector(64-(2**regmode) to 63); +signal iu_slowspr_data_l2 : std_ulogic_vector(64-(2**regmode) to 63); +signal iu_slowspr_done_d : std_ulogic; +signal iu_slowspr_done_l2 : std_ulogic; + +signal iu_slowspr_done : std_ulogic; +signal iu_slowspr_data : std_ulogic_vector(64-(2**regmode) to 63); + +signal immr0_sel : std_ulogic; +signal immr0_wren : std_ulogic; +signal immr0_rden : std_ulogic; +signal immr0_d : std_ulogic_vector(32 to 63); +signal immr0_l2 : std_ulogic_vector(32 to 63); + +signal imr0_sel : std_ulogic; +signal imr0_wren : std_ulogic; +signal imr0_rden : std_ulogic; +signal imr0_d : std_ulogic_vector(32 to 63); +signal imr0_l2 : std_ulogic_vector(32 to 63); + +signal iulfsr_sel : std_ulogic; +signal iulfsr_wren : std_ulogic; +signal iulfsr_rden : std_ulogic; +signal iulfsr_d : std_ulogic_vector(32 to 63); +signal iulfsr_l2 : std_ulogic_vector(32 to 63); +signal iulfsr : std_ulogic_vector(1 to 28); +signal iulfsr_act : std_ulogic; + +signal iudbg0_sel : std_ulogic; +signal iudbg0_wren : std_ulogic; +signal iudbg0_rden : std_ulogic; +signal iudbg0_d : std_ulogic_vector(50 to 57); +signal iudbg0_l2 : std_ulogic_vector(50 to 57); +signal iudbg0 : std_ulogic_vector(32 to 63); + +signal iudbg0_exec_wren : std_ulogic; +signal iudbg0_exec_d : std_ulogic; +signal iudbg0_exec_l2 : std_ulogic; +signal iudbg0_done_wren : std_ulogic; +signal iudbg0_done_d : std_ulogic; +signal iudbg0_done_l2 : std_ulogic; + +signal iudbg1_sel : std_ulogic; +signal iudbg1_wren : std_ulogic; +signal iudbg1_rden : std_ulogic; +signal iudbg1_d : std_ulogic_vector(53 to 63); +signal iudbg1_l2 : std_ulogic_vector(53 to 63); +signal iudbg1 : std_ulogic_vector(32 to 63); + +signal iudbg2_sel : std_ulogic; +signal iudbg2_wren : std_ulogic; +signal iudbg2_rden : std_ulogic; +signal iudbg2_d : std_ulogic_vector(34 to 63); +signal iudbg2_l2 : std_ulogic_vector(34 to 63); +signal iudbg2 : std_ulogic_vector(32 to 63); + +signal iullcr_sel : std_ulogic; +signal iullcr_wren : std_ulogic; +signal iullcr_rden : std_ulogic; +signal iullcr_d : std_ulogic_vector(46 to 63); +signal iullcr_l2 : std_ulogic_vector(46 to 63); +signal iullcr : std_ulogic_vector(32 to 63); + +signal iucr0_sel : std_ulogic; +signal iucr0_wren : std_ulogic; +signal iucr0_rden : std_ulogic; +signal iucr0_d : std_ulogic_vector(48 to 63); +signal iucr0_l2 : std_ulogic_vector(48 to 63); +signal iucr0 : std_ulogic_vector(32 to 63); + +signal iucr1_t0_sel : std_ulogic; +signal iucr1_t0_wren : std_ulogic; +signal iucr1_t0_rden : std_ulogic; +signal iucr1_t0_d : std_ulogic_vector(50 to 63); +signal iucr1_t0_l2 : std_ulogic_vector(50 to 63); +signal iucr1_t0 : std_ulogic_vector(32 to 63); + +signal iucr1_t1_sel : std_ulogic; +signal iucr1_t1_wren : std_ulogic; +signal iucr1_t1_rden : std_ulogic; +signal iucr1_t1_d : std_ulogic_vector(50 to 63); +signal iucr1_t1_l2 : std_ulogic_vector(50 to 63); +signal iucr1_t1 : std_ulogic_vector(32 to 63); + +signal iucr1_t2_sel : std_ulogic; +signal iucr1_t2_wren : std_ulogic; +signal iucr1_t2_rden : std_ulogic; +signal iucr1_t2_d : std_ulogic_vector(50 to 63); +signal iucr1_t2_l2 : std_ulogic_vector(50 to 63); +signal iucr1_t2 : std_ulogic_vector(32 to 63); + +signal iucr1_t3_sel : std_ulogic; +signal iucr1_t3_wren : std_ulogic; +signal iucr1_t3_rden : std_ulogic; +signal iucr1_t3_d : std_ulogic_vector(50 to 63); +signal iucr1_t3_l2 : std_ulogic_vector(50 to 63); +signal iucr1_t3 : std_ulogic_vector(32 to 63); + +signal iucr2_t0_sel : std_ulogic; +signal iucr2_t0_wren : std_ulogic; +signal iucr2_t0_rden : std_ulogic; +signal iucr2_t0_d : std_ulogic_vector(32 to 39); +signal iucr2_t0_l2 : std_ulogic_vector(32 to 39); +signal iucr2_t0 : std_ulogic_vector(32 to 63); + +signal iucr2_t1_sel : std_ulogic; +signal iucr2_t1_wren : std_ulogic; +signal iucr2_t1_rden : std_ulogic; +signal iucr2_t1_d : std_ulogic_vector(32 to 39); +signal iucr2_t1_l2 : std_ulogic_vector(32 to 39); +signal iucr2_t1 : std_ulogic_vector(32 to 63); + +signal iucr2_t2_sel : std_ulogic; +signal iucr2_t2_wren : std_ulogic; +signal iucr2_t2_rden : std_ulogic; +signal iucr2_t2_d : std_ulogic_vector(32 to 39); +signal iucr2_t2_l2 : std_ulogic_vector(32 to 39); +signal iucr2_t2 : std_ulogic_vector(32 to 63); + +signal iucr2_t3_sel : std_ulogic; +signal iucr2_t3_wren : std_ulogic; +signal iucr2_t3_rden : std_ulogic; +signal iucr2_t3_d : std_ulogic_vector(32 to 39); +signal iucr2_t3_l2 : std_ulogic_vector(32 to 39); +signal iucr2_t3 : std_ulogic_vector(32 to 63); + +signal ppr32_t0_sel : std_ulogic; +signal ppr32_t0_wren : std_ulogic; +signal ppr32_t0_rden : std_ulogic; +signal ppr32_t0_d : std_ulogic_vector(43 to 45); +signal ppr32_t0_l2 : std_ulogic_vector(43 to 45); +signal ppr32_t0 : std_ulogic_vector(32 to 63); + +signal ppr32_t1_sel : std_ulogic; +signal ppr32_t1_wren : std_ulogic; +signal ppr32_t1_rden : std_ulogic; +signal ppr32_t1_d : std_ulogic_vector(43 to 45); +signal ppr32_t1_l2 : std_ulogic_vector(43 to 45); +signal ppr32_t1 : std_ulogic_vector(32 to 63); + +signal ppr32_t2_sel : std_ulogic; +signal ppr32_t2_wren : std_ulogic; +signal ppr32_t2_rden : std_ulogic; +signal ppr32_t2_d : std_ulogic_vector(43 to 45); +signal ppr32_t2_l2 : std_ulogic_vector(43 to 45); +signal ppr32_t2 : std_ulogic_vector(32 to 63); + +signal ppr32_t3_sel : std_ulogic; +signal ppr32_t3_wren : std_ulogic; +signal ppr32_t3_rden : std_ulogic; +signal ppr32_t3_d : std_ulogic_vector(43 to 45); +signal ppr32_t3_l2 : std_ulogic_vector(43 to 45); +signal ppr32_t3 : std_ulogic_vector(32 to 63); + + + + + +signal lo_pri : std_ulogic_vector(0 to 3); +signal hi_pri : std_ulogic_vector(0 to 3); + + +signal priv_mode : std_ulogic_vector(0 to 3); +signal hypv_mode : std_ulogic_vector(0 to 3); + + +signal hi_pri_level_t0 : std_ulogic_vector(0 to 1); +signal hi_pri_level_t1 : std_ulogic_vector(0 to 1); +signal hi_pri_level_t2 : std_ulogic_vector(0 to 1); +signal hi_pri_level_t3 : std_ulogic_vector(0 to 1); + + +signal iull_en : std_ulogic; +signal ll_trig_dly : std_ulogic_vector(0 to 17); +signal ll_hold_dly : std_ulogic_vector(0 to 9); + +signal ll_trig_rnd_act : std_ulogic; +signal ll_trig_rnd_d : std_ulogic_vector(4 to 17); +signal ll_trig_rnd_l2 : std_ulogic_vector(4 to 17); + +signal ll_trig_cnt_act : std_ulogic; +signal ll_trig_cnt_d : std_ulogic_vector(0 to 17); +signal ll_trig_cnt_l2 : std_ulogic_vector(0 to 17); + +signal ll_hold_cnt_act : std_ulogic; +signal ll_hold_cnt_d : std_ulogic_vector(0 to 9); +signal ll_hold_cnt_l2 : std_ulogic_vector(0 to 9); + +signal ll_rand : std_ulogic; +signal ll_trig : std_ulogic; +signal ll_hold : std_ulogic; + + +-- pervasive signals +signal tiup : std_ulogic; + +signal pc_iu_cfg_sl_thold_1 : std_ulogic; +signal pc_iu_cfg_sl_thold_0 : std_ulogic; +signal pc_iu_cfg_sl_thold_0_b : std_ulogic; +signal pc_iu_func_sl_thold_1 : std_ulogic; +signal pc_iu_func_sl_thold_0 : std_ulogic; +signal pc_iu_func_sl_thold_0_b : std_ulogic; +signal pc_iu_sg_1 : std_ulogic; +signal pc_iu_sg_0 : std_ulogic; +signal forcee : std_ulogic; +signal cfg_force : std_ulogic; +signal dclk : std_ulogic; +signal lclk : clk_logic; + +signal siv : std_ulogic_vector(0 to scan_right); +signal sov : std_ulogic_vector(0 to scan_right); + +signal ccfg_siv : std_ulogic_vector(0 to ccfg_scan_right); +signal ccfg_sov : std_ulogic_vector(0 to ccfg_scan_right); + +begin + + +tiup <= '1'; + + +------------------------------------------------- +-- latches +------------------------------------------------- + +ll_trig_rnd_reg: tri_rlmreg_p + generic map (width => ll_trig_rnd_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ll_trig_rnd_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(ll_trig_rnd_offset to ll_trig_rnd_offset + ll_trig_rnd_l2'length-1), + scout => sov(ll_trig_rnd_offset to ll_trig_rnd_offset + ll_trig_rnd_l2'length-1), + din => ll_trig_rnd_d, + dout => ll_trig_rnd_l2); + +ll_trig_cnt_reg: tri_rlmreg_p + generic map (width => ll_trig_cnt_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ll_trig_cnt_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(ll_trig_cnt_offset to ll_trig_cnt_offset + ll_trig_cnt_l2'length-1), + scout => sov(ll_trig_cnt_offset to ll_trig_cnt_offset + ll_trig_cnt_l2'length-1), + din => ll_trig_cnt_d, + dout => ll_trig_cnt_l2); + +ll_hold_cnt_reg: tri_rlmreg_p + generic map (width => ll_hold_cnt_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ll_hold_cnt_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(ll_hold_cnt_offset to ll_hold_cnt_offset + ll_hold_cnt_l2'length-1), + scout => sov(ll_hold_cnt_offset to ll_hold_cnt_offset + ll_hold_cnt_l2'length-1), + din => ll_hold_cnt_d, + dout => ll_hold_cnt_l2); + +xu_iu_run_thread_reg: tri_rlmreg_p + generic map (width => xu_iu_run_thread_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_iu_run_thread_offset to xu_iu_run_thread_offset + xu_iu_run_thread_l2'length-1), + scout => sov(xu_iu_run_thread_offset to xu_iu_run_thread_offset + xu_iu_run_thread_l2'length-1), + din => xu_iu_run_thread_d, + dout => xu_iu_run_thread_l2); + +xu_iu_ex6_pri_reg: tri_rlmreg_p + generic map (width => xu_iu_ex6_pri_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_iu_ex6_pri_offset to xu_iu_ex6_pri_offset + xu_iu_ex6_pri_l2'length-1), + scout => sov(xu_iu_ex6_pri_offset to xu_iu_ex6_pri_offset + xu_iu_ex6_pri_l2'length-1), + din => xu_iu_ex6_pri_d, + dout => xu_iu_ex6_pri_l2); + +xu_iu_ex6_pri_val_reg: tri_rlmreg_p + generic map (width => xu_iu_ex6_pri_val_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_iu_ex6_pri_val_offset to xu_iu_ex6_pri_val_offset + xu_iu_ex6_pri_val_l2'length-1), + scout => sov(xu_iu_ex6_pri_val_offset to xu_iu_ex6_pri_val_offset + xu_iu_ex6_pri_val_l2'length-1), + din => xu_iu_ex6_pri_val_d, + dout => xu_iu_ex6_pri_val_l2); + +xu_iu_raise_iss_pri_reg: tri_rlmreg_p + generic map (width => xu_iu_raise_iss_pri_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_iu_raise_iss_pri_offset to xu_iu_raise_iss_pri_offset + xu_iu_raise_iss_pri_l2'length-1), + scout => sov(xu_iu_raise_iss_pri_offset to xu_iu_raise_iss_pri_offset + xu_iu_raise_iss_pri_l2'length-1), + din => xu_iu_raise_iss_pri_d, + dout => xu_iu_raise_iss_pri_l2); + +xu_iu_msr_gs_reg: tri_rlmreg_p + generic map (width => xu_iu_msr_gs_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_iu_msr_gs_offset to xu_iu_msr_gs_offset + xu_iu_msr_gs_l2'length-1), + scout => sov(xu_iu_msr_gs_offset to xu_iu_msr_gs_offset + xu_iu_msr_gs_l2'length-1), + din => xu_iu_msr_gs_d, + dout => xu_iu_msr_gs_l2); + +xu_iu_msr_pr_reg: tri_rlmreg_p + generic map (width => xu_iu_msr_pr_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_iu_msr_pr_offset to xu_iu_msr_pr_offset + xu_iu_msr_pr_l2'length-1), + scout => sov(xu_iu_msr_pr_offset to xu_iu_msr_pr_offset + xu_iu_msr_pr_l2'length-1), + din => xu_iu_msr_pr_d, + dout => xu_iu_msr_pr_l2); + +slowspr_val_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(slowspr_val_offset), + scout => sov(slowspr_val_offset), + din => slowspr_val_d, + dout => slowspr_val_l2); + +slowspr_rw_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(slowspr_rw_offset), + scout => sov(slowspr_rw_offset), + din => slowspr_rw_d, + dout => slowspr_rw_l2); + +slowspr_etid_reg: tri_rlmreg_p + generic map (width => slowspr_etid_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(slowspr_etid_offset to slowspr_etid_offset + slowspr_etid_l2'length-1), + scout => sov(slowspr_etid_offset to slowspr_etid_offset + slowspr_etid_l2'length-1), + din => slowspr_etid_d, + dout => slowspr_etid_l2); + +slowspr_addr_reg: tri_rlmreg_p + generic map (width => slowspr_addr_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(slowspr_addr_offset to slowspr_addr_offset + slowspr_addr_l2'length-1), + scout => sov(slowspr_addr_offset to slowspr_addr_offset + slowspr_addr_l2'length-1), + din => slowspr_addr_d, + dout => slowspr_addr_l2); + +slowspr_data_reg: tri_rlmreg_p + generic map (width => slowspr_data_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(slowspr_data_offset to slowspr_data_offset + slowspr_data_l2'length-1), + scout => sov(slowspr_data_offset to slowspr_data_offset + slowspr_data_l2'length-1), + din => slowspr_data_d, + dout => slowspr_data_l2); + +slowspr_done_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(slowspr_done_offset), + scout => sov(slowspr_done_offset), + din => slowspr_done_d, + dout => slowspr_done_l2); + +iu_slowspr_val_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu_slowspr_val_offset), + scout => sov(iu_slowspr_val_offset), + din => iu_slowspr_val_d, + dout => iu_slowspr_val_l2); + +iu_slowspr_rw_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu_slowspr_val_d, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu_slowspr_rw_offset), + scout => sov(iu_slowspr_rw_offset), + din => iu_slowspr_rw_d, + dout => iu_slowspr_rw_l2); + +iu_slowspr_etid_reg: tri_rlmreg_p + generic map (width => iu_slowspr_etid_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu_slowspr_val_d, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu_slowspr_etid_offset to iu_slowspr_etid_offset + iu_slowspr_etid_l2'length-1), + scout => sov(iu_slowspr_etid_offset to iu_slowspr_etid_offset + iu_slowspr_etid_l2'length-1), + din => iu_slowspr_etid_d, + dout => iu_slowspr_etid_l2); + +iu_slowspr_addr_reg: tri_rlmreg_p + generic map (width => iu_slowspr_addr_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu_slowspr_val_d, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu_slowspr_addr_offset to iu_slowspr_addr_offset + iu_slowspr_addr_l2'length-1), + scout => sov(iu_slowspr_addr_offset to iu_slowspr_addr_offset + iu_slowspr_addr_l2'length-1), + din => iu_slowspr_addr_d, + dout => iu_slowspr_addr_l2); + +iu_slowspr_data_reg: tri_rlmreg_p + generic map (width => iu_slowspr_data_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu_slowspr_val_d, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu_slowspr_data_offset to iu_slowspr_data_offset + iu_slowspr_data_l2'length-1), + scout => sov(iu_slowspr_data_offset to iu_slowspr_data_offset + iu_slowspr_data_l2'length-1), + din => iu_slowspr_data_d, + dout => iu_slowspr_data_l2); + +iu_slowspr_done_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu_slowspr_val_d, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu_slowspr_done_offset), + scout => sov(iu_slowspr_done_offset), + din => iu_slowspr_done_d, + dout => iu_slowspr_done_l2); + +immr0a_reg: tri_ser_rlmreg_p + generic map (width => 16, init => 65535, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => immr0_wren, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(immr0_offset to immr0_offset + 16-1), + scout => sov(immr0_offset to immr0_offset + 16-1), + din => immr0_d(32 to 47), + dout => immr0_l2(32 to 47)); + +immr0b_reg: tri_ser_rlmreg_p + generic map (width => 16, init => 65535, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => immr0_wren, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(immr0_offset + 16 to immr0_offset + immr0_l2'length-1), + scout => sov(immr0_offset + 16 to immr0_offset + immr0_l2'length-1), + din => immr0_d(48 to 63), + dout => immr0_l2(48 to 63)); + +imr0_reg: tri_ser_rlmreg_p + generic map (width => imr0_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => imr0_wren, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(imr0_offset to imr0_offset + imr0_l2'length-1), + scout => sov(imr0_offset to imr0_offset + imr0_l2'length-1), + din => imr0_d, + dout => imr0_l2); + +iulfsr_reg: tri_ser_rlmreg_p + generic map (width => iulfsr_l2'length, init => 26, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iulfsr_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iulfsr_offset to iulfsr_offset + iulfsr_l2'length-1), + scout => sov(iulfsr_offset to iulfsr_offset + iulfsr_l2'length-1), + din => iulfsr_d, + dout => iulfsr_l2); + +iudbg0_reg: tri_ser_rlmreg_p + generic map (width => iudbg0_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iudbg0_wren, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iudbg0_offset to iudbg0_offset + iudbg0_l2'length-1), + scout => sov(iudbg0_offset to iudbg0_offset + iudbg0_l2'length-1), + din => iudbg0_d, + dout => iudbg0_l2); + +iudbg0_done_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iudbg0_done_wren, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iudbg0_done_offset), + scout => sov(iudbg0_done_offset), + din => iudbg0_done_d, + dout => iudbg0_done_l2); + +iudbg0_exec_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iudbg0_exec_wren, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iudbg0_exec_offset), + scout => sov(iudbg0_exec_offset), + din => iudbg0_exec_d, + dout => iudbg0_exec_l2); + +iudbg1_reg: tri_ser_rlmreg_p + generic map (width => iudbg1_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iudbg1_wren, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iudbg1_offset to iudbg1_offset + iudbg1_l2'length-1), + scout => sov(iudbg1_offset to iudbg1_offset + iudbg1_l2'length-1), + din => iudbg1_d, + dout => iudbg1_l2); + +iudbg2_reg: tri_ser_rlmreg_p + generic map (width => iudbg2_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iudbg2_wren, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iudbg2_offset to iudbg2_offset + iudbg2_l2'length-1), + scout => sov(iudbg2_offset to iudbg2_offset + iudbg2_l2'length-1), + din => iudbg2_d, + dout => iudbg2_l2); + +spare_latch: tri_rlmreg_p + generic map (width => spare_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(spare_offset to spare_offset + spare_l2'length-1), + scout => sov(spare_offset to spare_offset + spare_l2'length-1), + din => spare_l2, + dout => spare_l2); + + +iullcr_reg: tri_ser_rlmreg_p --init 0x00020040 + generic map (width => iullcr_l2'length, init => 131136, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iullcr_wren, + thold_b => pc_iu_cfg_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => cfg_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => ccfg_siv(iullcr_offset to iullcr_offset + iullcr_l2'length-1), + scout => ccfg_sov(iullcr_offset to iullcr_offset + iullcr_l2'length-1), + din => iullcr_d, + dout => iullcr_l2); + +iucr0_reg: tri_ser_rlmreg_p --init 0x000010FA + generic map (width => iucr0_l2'length, init => 4346, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iucr0_wren, + thold_b => pc_iu_cfg_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => cfg_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => ccfg_siv(iucr0_offset to iucr0_offset + iucr0_l2'length-1), + scout => ccfg_sov(iucr0_offset to iucr0_offset + iucr0_l2'length-1), + din => iucr0_d, + dout => iucr0_l2); + +iucr1_t0_reg: tri_ser_rlmreg_p --init 0x00001000 + generic map (width => iucr1_t0_l2'length, init => 4096, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iucr1_t0_wren, + thold_b => pc_iu_cfg_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => cfg_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => ccfg_siv(iucr1_t0_offset to iucr1_t0_offset + iucr1_t0_l2'length-1), + scout => ccfg_sov(iucr1_t0_offset to iucr1_t0_offset + iucr1_t0_l2'length-1), + din => iucr1_t0_d, + dout => iucr1_t0_l2); + +iucr1_t1_reg: tri_ser_rlmreg_p --init 0x00001000 + generic map (width => iucr1_t1_l2'length, init => 4096, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iucr1_t1_wren, + thold_b => pc_iu_cfg_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => cfg_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => ccfg_siv(iucr1_t1_offset to iucr1_t1_offset + iucr1_t1_l2'length-1), + scout => ccfg_sov(iucr1_t1_offset to iucr1_t1_offset + iucr1_t1_l2'length-1), + din => iucr1_t1_d, + dout => iucr1_t1_l2); + +iucr1_t2_reg: tri_ser_rlmreg_p --init 0x00001000 + generic map (width => iucr1_t2_l2'length, init => 4096, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iucr1_t2_wren, + thold_b => pc_iu_cfg_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => cfg_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => ccfg_siv(iucr1_t2_offset to iucr1_t2_offset + iucr1_t2_l2'length-1), + scout => ccfg_sov(iucr1_t2_offset to iucr1_t2_offset + iucr1_t2_l2'length-1), + din => iucr1_t2_d, + dout => iucr1_t2_l2); + +iucr1_t3_reg: tri_ser_rlmreg_p --init 0x00001000 + generic map (width => iucr1_t3_l2'length, init => 4096, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iucr1_t3_wren, + thold_b => pc_iu_cfg_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => cfg_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => ccfg_siv(iucr1_t3_offset to iucr1_t3_offset + iucr1_t3_l2'length-1), + scout => ccfg_sov(iucr1_t3_offset to iucr1_t3_offset + iucr1_t3_l2'length-1), + din => iucr1_t3_d, + dout => iucr1_t3_l2); + +iucr2_t0_reg: tri_ser_rlmreg_p --init 0x00000000 + generic map (width => iucr2_t0_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iucr2_t0_wren, + thold_b => pc_iu_cfg_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => cfg_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => ccfg_siv(iucr2_t0_offset to iucr2_t0_offset + iucr2_t0_l2'length-1), + scout => ccfg_sov(iucr2_t0_offset to iucr2_t0_offset + iucr2_t0_l2'length-1), + din => iucr2_t0_d, + dout => iucr2_t0_l2); + +iucr2_t1_reg: tri_ser_rlmreg_p --init 0x00000000 + generic map (width => iucr2_t1_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iucr2_t1_wren, + thold_b => pc_iu_cfg_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => cfg_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => ccfg_siv(iucr2_t1_offset to iucr2_t1_offset + iucr2_t1_l2'length-1), + scout => ccfg_sov(iucr2_t1_offset to iucr2_t1_offset + iucr2_t1_l2'length-1), + din => iucr2_t1_d, + dout => iucr2_t1_l2); + +iucr2_t2_reg: tri_ser_rlmreg_p --init 0x00000000 + generic map (width => iucr2_t2_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iucr2_t2_wren, + thold_b => pc_iu_cfg_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => cfg_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => ccfg_siv(iucr2_t2_offset to iucr2_t2_offset + iucr2_t2_l2'length-1), + scout => ccfg_sov(iucr2_t2_offset to iucr2_t2_offset + iucr2_t2_l2'length-1), + din => iucr2_t2_d, + dout => iucr2_t2_l2); + +iucr2_t3_reg: tri_ser_rlmreg_p --init 0x00000000 + generic map (width => iucr2_t3_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iucr2_t3_wren, + thold_b => pc_iu_cfg_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => cfg_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => ccfg_siv(iucr2_t3_offset to iucr2_t3_offset + iucr2_t3_l2'length-1), + scout => ccfg_sov(iucr2_t3_offset to iucr2_t3_offset + iucr2_t3_l2'length-1), + din => iucr2_t3_d, + dout => iucr2_t3_l2); + +ppr32_t0_reg: tri_ser_rlmreg_p --init 0x000c0000 + generic map (width => ppr32_t0_l2'length, init => 3, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ppr32_t0_wren, + thold_b => pc_iu_cfg_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => cfg_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => ccfg_siv(ppr32_t0_offset to ppr32_t0_offset + ppr32_t0_l2'length-1), + scout => ccfg_sov(ppr32_t0_offset to ppr32_t0_offset + ppr32_t0_l2'length-1), + din => ppr32_t0_d, + dout => ppr32_t0_l2); + +ppr32_t1_reg: tri_ser_rlmreg_p --init 0x000c0000 + generic map (width => ppr32_t1_l2'length, init => 3, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ppr32_t1_wren, + thold_b => pc_iu_cfg_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => cfg_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => ccfg_siv(ppr32_t1_offset to ppr32_t1_offset + ppr32_t1_l2'length-1), + scout => ccfg_sov(ppr32_t1_offset to ppr32_t1_offset + ppr32_t1_l2'length-1), + din => ppr32_t1_d, + dout => ppr32_t1_l2); + +ppr32_t2_reg: tri_ser_rlmreg_p --init 0x000c0000 + generic map (width => ppr32_t2_l2'length, init => 3, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ppr32_t2_wren, + thold_b => pc_iu_cfg_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => cfg_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => ccfg_siv(ppr32_t2_offset to ppr32_t2_offset + ppr32_t2_l2'length-1), + scout => ccfg_sov(ppr32_t2_offset to ppr32_t2_offset + ppr32_t2_l2'length-1), + din => ppr32_t2_d, + dout => ppr32_t2_l2); + +ppr32_t3_reg: tri_ser_rlmreg_p --init 0x000c0000 + generic map (width => ppr32_t3_l2'length, init => 3, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ppr32_t3_wren, + thold_b => pc_iu_cfg_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => cfg_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => ccfg_siv(ppr32_t3_offset to ppr32_t3_offset + ppr32_t3_l2'length-1), + scout => ccfg_sov(ppr32_t3_offset to ppr32_t3_offset + ppr32_t3_l2'length-1), + din => ppr32_t3_d, + dout => ppr32_t3_l2); + +ccfg_spare_latch: tri_rlmreg_p + generic map (width => ccfg_spare_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_cfg_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => cfg_force, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => ccfg_siv(ccfg_spare_offset to ccfg_spare_offset + ccfg_spare_l2'length-1), + scout => ccfg_sov(ccfg_spare_offset to ccfg_spare_offset + ccfg_spare_l2'length-1), + din => ccfg_spare_l2, + dout => ccfg_spare_l2); + + +------------------------------------------------- +-- inputs +------------------------------------------------- +xu_iu_run_thread_d <= xu_iu_run_thread; +xu_iu_ex6_pri_d <= xu_iu_ex6_pri; +xu_iu_ex6_pri_val_d <= xu_iu_ex6_pri_val; +xu_iu_raise_iss_pri_d <= xu_iu_raise_iss_pri; +xu_iu_msr_gs_d <= xu_iu_msr_gs; +xu_iu_msr_pr_d <= xu_iu_msr_pr; + +slowspr_val_d <= slowspr_val_in; +slowspr_rw_d <= slowspr_rw_in; +slowspr_etid_d <= slowspr_etid_in; +slowspr_addr_d <= slowspr_addr_in; +slowspr_data_d <= slowspr_data_in; +slowspr_done_d <= slowspr_done_in; + +------------------------------------------------- +-- outputs +------------------------------------------------- +iu_slowspr_val_d <= slowspr_val_l2; +iu_slowspr_rw_d <= slowspr_rw_l2; +iu_slowspr_etid_d <= slowspr_etid_l2; +iu_slowspr_addr_d <= slowspr_addr_l2; +iu_slowspr_data_d <= slowspr_data_l2 or iu_slowspr_data; +iu_slowspr_done_d <= slowspr_done_l2 or iu_slowspr_done; + +slowspr_val_out <= iu_slowspr_val_l2; +slowspr_rw_out <= iu_slowspr_rw_l2; +slowspr_etid_out <= iu_slowspr_etid_l2; +slowspr_addr_out <= iu_slowspr_addr_l2; +slowspr_data_out <= iu_slowspr_data_l2; +slowspr_done_out <= iu_slowspr_done_l2; + + +spr_dec_mask(0 to 31) <= immr0_l2(32 to 63); +spr_dec_match(0 to 31) <= imr0_l2(32 to 63); + +spr_ic_pri_rand <= iulfsr_l2(58) & iulfsr_l2(51) & iulfsr_l2(45) & iulfsr_l2(40) & iulfsr_l2(36); +spr_ic_pri_rand_flush <= iulfsr_l2(60); +spr_ic_pri_rand_always <= iulfsr_l2(61); + +spr_fiss_pri_rand <= iulfsr_l2(32) & iulfsr_l2(35) & iulfsr_l2(39) & iulfsr_l2(44) & iulfsr_l2(50); +spr_fiss_pri_rand_flush <= iulfsr_l2(62); +spr_fiss_pri_rand_always<= iulfsr_l2(63) or ll_hold; + + +spr_ic_clockgate_dis <= iucr0_l2(48 to 49); +spr_ic_cls <= iucr0_l2(50); +spr_ic_icbi_ack_en <= iucr0_l2(51); + +spr_bp_gshare_mask <= "0000" when iucr0_l2(52 to 55) = "0000" else + "1000" when iucr0_l2(52 to 55) = "0001" else + "1100" when iucr0_l2(52 to 55) = "0010" else + "1110" when iucr0_l2(52 to 55) = "0011" else + "1111" ; + +spr_ic_bp_config <= iucr0_l2(56 to 59); +spr_bp_config <= iucr0_l2(60 to 63); + +iu_au_config_iucr_t0 <= iucr2_t0_l2(32 to 39); +iu_au_config_iucr_t1 <= iucr2_t1_l2(32 to 39); +iu_au_config_iucr_t2 <= iucr2_t2_l2(32 to 39); +iu_au_config_iucr_t3 <= iucr2_t3_l2(32 to 39); + +spr_issue_high_mask(0 to 3) <= hi_pri(0 to 3); +spr_issue_med_mask(0 to 3) <= not hi_pri(0 to 3) and not lo_pri(0 to 3); + +spr_fiss_count0_max <= iucr1_t0_l2(58 to 63); +spr_fiss_count1_max <= iucr1_t1_l2(58 to 63); +spr_fiss_count2_max <= iucr1_t2_l2(58 to 63); +spr_fiss_count3_max <= iucr1_t3_l2(58 to 63); + +hi_pri_level_t0 <= iucr1_t0_l2(50 to 51); +hi_pri_level_t1 <= iucr1_t1_l2(50 to 51); +hi_pri_level_t2 <= iucr1_t2_l2(50 to 51); +hi_pri_level_t3 <= iucr1_t3_l2(50 to 51); + +spr_ic_idir_read <= iudbg0_exec_l2; +spr_ic_idir_way <= iudbg0_l2(50 to 51); +spr_ic_idir_row <= iudbg0_l2(52 to 57); + +------------------------------------------------- +-- livelock hold +------------------------------------------------- +iull_en <= iullcr_l2(63); + +ll_trig_dly(0 to 3) <= "0001" when iullcr_l2(46 to 49) = "0000" else iullcr_l2(46 to 49); +ll_trig_dly(4 to 17) <= ll_trig_rnd_l2(4 to 17); + +ll_hold_dly(0 to 5) <= iullcr_l2(54 to 59); +ll_hold_dly(6 to 9) <= "0000"; + +ll_trig_rnd_act <= iull_en and ll_rand; +ll_trig_rnd_d(4 to 17) <= iulfsr_l2(32) & iulfsr_l2(33) & iulfsr_l2(35) & iulfsr_l2(36) & + iulfsr_l2(38) & iulfsr_l2(39) & iulfsr_l2(41) & iulfsr_l2(42) & + iulfsr_l2(44) & iulfsr_l2(45) & iulfsr_l2(47) & iulfsr_l2(48) & + iulfsr_l2(50) & iulfsr_l2(51); + +ll_trig_cnt_act <= iull_en and not ll_hold; +ll_trig_cnt_d(0 to 17) <= "000000000000000000" when ll_trig_cnt_l2(0 to 17) = ll_trig_dly(0 to 17) else ll_trig_cnt_l2(0 to 17) + 1; +ll_trig <= ll_trig_cnt_l2(0 to 17) = ll_trig_dly(0 to 17); +ll_rand <= ll_trig_cnt_l2(0 to 3) /= ll_trig_dly(0 to 3); + +ll_hold_cnt_act <= iull_en and (ll_hold or ll_trig); +ll_hold_cnt_d(0 to 9) <= "0000000000" when ll_hold_cnt_l2(0 to 9) = ll_hold_dly(0 to 9) else ll_hold_cnt_l2(0 to 9) + 1; +ll_hold <= iull_en and or_reduce(ll_hold_cnt_l2(0 to 9)); + +spr_fdep_ll_hold <= ll_hold; + +------------------------------------------------- +-- register select +------------------------------------------------- + +immr0_sel <= slowspr_val_l2 and slowspr_addr_l2 = "1101110001"; --881 +imr0_sel <= slowspr_val_l2 and slowspr_addr_l2 = "1101110000"; --880 +iulfsr_sel <= slowspr_val_l2 and slowspr_addr_l2 = "1101111011"; --891 +iudbg0_sel <= slowspr_val_l2 and slowspr_addr_l2 = "1101111000"; --888 +iudbg1_sel <= slowspr_val_l2 and slowspr_addr_l2 = "1101111001"; --889 +iudbg2_sel <= slowspr_val_l2 and slowspr_addr_l2 = "1101111010"; --890 +iullcr_sel <= slowspr_val_l2 and slowspr_addr_l2 = "1101111100"; --892 +iucr0_sel <= slowspr_val_l2 and slowspr_addr_l2 = "1111110011"; --1011 +iucr1_t0_sel <= slowspr_val_l2 and slowspr_addr_l2 = "1101110011" and slowspr_etid_l2 = "00"; --883,t0 +iucr1_t1_sel <= slowspr_val_l2 and slowspr_addr_l2 = "1101110011" and slowspr_etid_l2 = "01"; --883,t1 +iucr1_t2_sel <= slowspr_val_l2 and slowspr_addr_l2 = "1101110011" and slowspr_etid_l2 = "10"; --883,t2 +iucr1_t3_sel <= slowspr_val_l2 and slowspr_addr_l2 = "1101110011" and slowspr_etid_l2 = "11"; --883,t3 +iucr2_t0_sel <= slowspr_val_l2 and slowspr_addr_l2 = "1101110100" and slowspr_etid_l2 = "00"; --884,t0 +iucr2_t1_sel <= slowspr_val_l2 and slowspr_addr_l2 = "1101110100" and slowspr_etid_l2 = "01"; --884,t1 +iucr2_t2_sel <= slowspr_val_l2 and slowspr_addr_l2 = "1101110100" and slowspr_etid_l2 = "10"; --884,t2 +iucr2_t3_sel <= slowspr_val_l2 and slowspr_addr_l2 = "1101110100" and slowspr_etid_l2 = "11"; --884,t3 +ppr32_t0_sel <= slowspr_val_l2 and slowspr_addr_l2 = "1110000010" and slowspr_etid_l2 = "00"; --898,t0 +ppr32_t1_sel <= slowspr_val_l2 and slowspr_addr_l2 = "1110000010" and slowspr_etid_l2 = "01"; --898,t1 +ppr32_t2_sel <= slowspr_val_l2 and slowspr_addr_l2 = "1110000010" and slowspr_etid_l2 = "10"; --898,t2 +ppr32_t3_sel <= slowspr_val_l2 and slowspr_addr_l2 = "1110000010" and slowspr_etid_l2 = "11"; --898,t3 + +iu_slowspr_done <= immr0_sel or imr0_sel or iulfsr_sel or iullcr_sel or iucr0_sel or + iudbg0_sel or iudbg1_sel or iudbg2_sel or + iucr1_t0_sel or iucr1_t1_sel or iucr1_t2_sel or iucr1_t3_sel or + iucr2_t0_sel or iucr2_t1_sel or iucr2_t2_sel or iucr2_t3_sel or + ppr32_t0_sel or ppr32_t1_sel or ppr32_t2_sel or ppr32_t3_sel; + + +------------------------------------------------- +-- set priority levels +------------------------------------------------- + +priv_mode(0 to 3) <= not xu_iu_msr_pr_l2(0 to 3); +hypv_mode(0 to 3) <= not xu_iu_msr_pr_l2(0 to 3) and not xu_iu_msr_gs_l2(0 to 3); + + + +lo_pri(0) <= not xu_iu_raise_iss_pri_l2(0) and + (ppr32_t0_l2(43 to 45) = "000" or + ppr32_t0_l2(43 to 45) = "001" or + ppr32_t0_l2(43 to 45) = "010" ); + +lo_pri(1) <= not xu_iu_raise_iss_pri_l2(1) and + (ppr32_t1_l2(43 to 45) = "000" or + ppr32_t1_l2(43 to 45) = "001" or + ppr32_t1_l2(43 to 45) = "010" ); + +lo_pri(2) <= not xu_iu_raise_iss_pri_l2(2) and + (ppr32_t2_l2(43 to 45) = "000" or + ppr32_t2_l2(43 to 45) = "001" or + ppr32_t2_l2(43 to 45) = "010" ); + +lo_pri(3) <= not xu_iu_raise_iss_pri_l2(3) and + (ppr32_t3_l2(43 to 45) = "000" or + ppr32_t3_l2(43 to 45) = "001" or + ppr32_t3_l2(43 to 45) = "010" ); + + +hi_pri(0) <=(ppr32_t0_l2(43 to 45) = "100" and hi_pri_level_t0(0 to 1) = "00") or + (ppr32_t0_l2(43 to 45) = "101" and (hi_pri_level_t0(0 to 1) = "00" or hi_pri_level_t0(0 to 1) = "01")) or + (ppr32_t0_l2(43 to 45) = "110" and (hi_pri_level_t0(0 to 1) = "00" or hi_pri_level_t0(0 to 1) = "01" or hi_pri_level_t0(0 to 1) = "10")) or + ppr32_t0_l2(43 to 45) = "111" ; + +hi_pri(1) <=(ppr32_t1_l2(43 to 45) = "100" and hi_pri_level_t1(0 to 1) = "00") or + (ppr32_t1_l2(43 to 45) = "101" and (hi_pri_level_t1(0 to 1) = "00" or hi_pri_level_t1(0 to 1) = "01")) or + (ppr32_t1_l2(43 to 45) = "110" and (hi_pri_level_t1(0 to 1) = "00" or hi_pri_level_t1(0 to 1) = "01" or hi_pri_level_t1(0 to 1) = "10")) or + ppr32_t1_l2(43 to 45) = "111" ; + +hi_pri(2) <=(ppr32_t2_l2(43 to 45) = "100" and hi_pri_level_t2(0 to 1) = "00") or + (ppr32_t2_l2(43 to 45) = "101" and (hi_pri_level_t2(0 to 1) = "00" or hi_pri_level_t2(0 to 1) = "01")) or + (ppr32_t2_l2(43 to 45) = "110" and (hi_pri_level_t2(0 to 1) = "00" or hi_pri_level_t2(0 to 1) = "01" or hi_pri_level_t2(0 to 1) = "10")) or + ppr32_t2_l2(43 to 45) = "111" ; + +hi_pri(3) <=(ppr32_t3_l2(43 to 45) = "100" and hi_pri_level_t3(0 to 1) = "00") or + (ppr32_t3_l2(43 to 45) = "101" and (hi_pri_level_t3(0 to 1) = "00" or hi_pri_level_t3(0 to 1) = "01")) or + (ppr32_t3_l2(43 to 45) = "110" and (hi_pri_level_t3(0 to 1) = "00" or hi_pri_level_t3(0 to 1) = "01" or hi_pri_level_t3(0 to 1) = "10")) or + ppr32_t3_l2(43 to 45) = "111" ; + + + + +------------------------------------------------- +-- register write +------------------------------------------------- + +iudbg0_exec_wren <= iudbg0_wren or iudbg0_exec_L2; +iudbg0_done_wren <= iudbg0_wren or ic_spr_idir_done; + +iudbg1_wren <= ic_spr_idir_done; +iudbg2_wren <= ic_spr_idir_done; + +immr0_wren <= immr0_sel and slowspr_rw_l2 = '0'; +imr0_wren <= imr0_sel and slowspr_rw_l2 = '0'; +iulfsr_wren <= iulfsr_sel and slowspr_rw_l2 = '0'; +iudbg0_wren <= iudbg0_sel and slowspr_rw_l2 = '0'; +iullcr_wren <= iullcr_sel and slowspr_rw_l2 = '0'; +iucr0_wren <= iucr0_sel and slowspr_rw_l2 = '0'; +iucr1_t0_wren <= iucr1_t0_sel and slowspr_rw_l2 = '0'; +iucr1_t1_wren <= iucr1_t1_sel and slowspr_rw_l2 = '0'; +iucr1_t2_wren <= iucr1_t2_sel and slowspr_rw_l2 = '0'; +iucr1_t3_wren <= iucr1_t3_sel and slowspr_rw_l2 = '0'; +iucr2_t0_wren <= iucr2_t0_sel and slowspr_rw_l2 = '0'; +iucr2_t1_wren <= iucr2_t1_sel and slowspr_rw_l2 = '0'; +iucr2_t2_wren <= iucr2_t2_sel and slowspr_rw_l2 = '0'; +iucr2_t3_wren <= iucr2_t3_sel and slowspr_rw_l2 = '0'; + + + +ppr32_t0_wren <= ((ppr32_t0_sel and slowspr_rw_l2 = '0') or xu_iu_ex6_pri_val_l2(0)) and + ((ppr32_t0_d(43 to 45) = "001" and priv_mode(0)) or + (ppr32_t0_d(43 to 45) = "010" ) or + (ppr32_t0_d(43 to 45) = "011" ) or + (ppr32_t0_d(43 to 45) = "100" ) or + (ppr32_t0_d(43 to 45) = "101" and priv_mode(0)) or + (ppr32_t0_d(43 to 45) = "110" and priv_mode(0)) or + (ppr32_t0_d(43 to 45) = "111" and hypv_mode(0)) ); + +ppr32_t1_wren <= ((ppr32_t1_sel and slowspr_rw_l2 = '0') or xu_iu_ex6_pri_val_l2(1)) and + ((ppr32_t1_d(43 to 45) = "001" and priv_mode(1)) or + (ppr32_t1_d(43 to 45) = "010" ) or + (ppr32_t1_d(43 to 45) = "011" ) or + (ppr32_t1_d(43 to 45) = "100" ) or + (ppr32_t1_d(43 to 45) = "101" and priv_mode(1)) or + (ppr32_t1_d(43 to 45) = "110" and priv_mode(1)) or + (ppr32_t1_d(43 to 45) = "111" and hypv_mode(1)) ); + +ppr32_t2_wren <= ((ppr32_t2_sel and slowspr_rw_l2 = '0') or xu_iu_ex6_pri_val_l2(2)) and + ((ppr32_t2_d(43 to 45) = "001" and priv_mode(2)) or + (ppr32_t2_d(43 to 45) = "010" ) or + (ppr32_t2_d(43 to 45) = "011" ) or + (ppr32_t2_d(43 to 45) = "100" ) or + (ppr32_t2_d(43 to 45) = "101" and priv_mode(2)) or + (ppr32_t2_d(43 to 45) = "110" and priv_mode(2)) or + (ppr32_t2_d(43 to 45) = "111" and hypv_mode(2)) ); + +ppr32_t3_wren <= ((ppr32_t3_sel and slowspr_rw_l2 = '0') or xu_iu_ex6_pri_val_l2(3)) and + ((ppr32_t3_d(43 to 45) = "001" and priv_mode(3)) or + (ppr32_t3_d(43 to 45) = "010" ) or + (ppr32_t3_d(43 to 45) = "011" ) or + (ppr32_t3_d(43 to 45) = "100" ) or + (ppr32_t3_d(43 to 45) = "101" and priv_mode(3)) or + (ppr32_t3_d(43 to 45) = "110" and priv_mode(3)) or + (ppr32_t3_d(43 to 45) = "111" and hypv_mode(3)) ); + + + + +iudbg0_exec_d <= IUDBG0_MASK(62) and slowspr_data_l2(62) when iudbg0_wren = '1' else '0'; +iudbg0_done_d <= IUDBG0_MASK(63) and slowspr_data_l2(63) when iudbg0_wren = '1' else ic_spr_idir_done; + +iudbg1_d <= IUDBG1_MASK(53 to 63) and (ic_spr_idir_lru(0 to 2) & ic_spr_idir_parity(0 to 3) & ic_spr_idir_endian & "00" & ic_spr_idir_valid); +iudbg2_d <= IUDBG2_MASK(34 to 63) and ic_spr_idir_tag(0 to 29); + +immr0_d <= IMMR0_MASK and slowspr_data_l2(32 to 63); +imr0_d <= IMR0_MASK and slowspr_data_l2(32 to 63); + + +iulfsr(1 to 28) <= iulfsr_l2(32 to 59); +iulfsr_d <= IULFSR_MASK and slowspr_data_l2(32 to 63) when iulfsr_wren = '1' else + (iulfsr(28) xor iulfsr(27) xor iulfsr(26) xor iulfsr(25) xor iulfsr(24) xor iulfsr(8)) & iulfsr(1 to 27) & iulfsr_l2(60 to 63); +iulfsr_act <= iulfsr_wren or or_reduce(xu_iu_run_thread_l2(0 to 3)); + +iudbg0_d <= IUDBG0_MASK(50 to 57) and slowspr_data_l2(50 to 57); +iullcr_d <= IULLCR_MASK(46 to 63) and slowspr_data_l2(46 to 63); +iucr0_d <= IUCR0_MASK(48 to 63) and (slowspr_data_l2(48 to 49) & iucr0_L2(50) & slowspr_data_l2(51 to 63)); + +iucr1_t0_d <= IUCR1_MASK(50 to 63) and slowspr_data_l2(50 to 63); +iucr1_t1_d <= IUCR1_MASK(50 to 63) and slowspr_data_l2(50 to 63); +iucr1_t2_d <= IUCR1_MASK(50 to 63) and slowspr_data_l2(50 to 63); +iucr1_t3_d <= IUCR1_MASK(50 to 63) and slowspr_data_l2(50 to 63); + +iucr2_t0_d <= IUCR2_MASK(32 to 39) and slowspr_data_l2(32 to 39); +iucr2_t1_d <= IUCR2_MASK(32 to 39) and slowspr_data_l2(32 to 39); +iucr2_t2_d <= IUCR2_MASK(32 to 39) and slowspr_data_l2(32 to 39); +iucr2_t3_d <= IUCR2_MASK(32 to 39) and slowspr_data_l2(32 to 39); + + + +ppr32_t0_d <= PPR32_MASK(43 to 45) and xu_iu_ex6_pri_l2(0 to 2) when xu_iu_ex6_pri_val_l2(0) = '1' else + PPR32_MASK(43 to 45) and slowspr_data_l2(43 to 45); +ppr32_t1_d <= PPR32_MASK(43 to 45) and xu_iu_ex6_pri_l2(0 to 2) when xu_iu_ex6_pri_val_l2(1) = '1' else + PPR32_MASK(43 to 45) and slowspr_data_l2(43 to 45); +ppr32_t2_d <= PPR32_MASK(43 to 45) and xu_iu_ex6_pri_l2(0 to 2) when xu_iu_ex6_pri_val_l2(2) = '1' else + PPR32_MASK(43 to 45) and slowspr_data_l2(43 to 45); +ppr32_t3_d <= PPR32_MASK(43 to 45) and xu_iu_ex6_pri_l2(0 to 2) when xu_iu_ex6_pri_val_l2(3) = '1' else + PPR32_MASK(43 to 45) and slowspr_data_l2(43 to 45); + +------------------------------------------------- +-- register read +------------------------------------------------- + +immr0_rden <= immr0_sel and slowspr_rw_l2 = '1'; +imr0_rden <= imr0_sel and slowspr_rw_l2 = '1'; +iulfsr_rden <= iulfsr_sel and slowspr_rw_l2 = '1'; +iudbg0_rden <= iudbg0_sel and slowspr_rw_l2 = '1'; +iudbg1_rden <= iudbg1_sel and slowspr_rw_l2 = '1'; +iudbg2_rden <= iudbg2_sel and slowspr_rw_l2 = '1'; +iullcr_rden <= iullcr_sel and slowspr_rw_l2 = '1'; +iucr0_rden <= iucr0_sel and slowspr_rw_l2 = '1'; +iucr1_t0_rden <= iucr1_t0_sel and slowspr_rw_l2 = '1'; +iucr1_t1_rden <= iucr1_t1_sel and slowspr_rw_l2 = '1'; +iucr1_t2_rden <= iucr1_t2_sel and slowspr_rw_l2 = '1'; +iucr1_t3_rden <= iucr1_t3_sel and slowspr_rw_l2 = '1'; +iucr2_t0_rden <= iucr2_t0_sel and slowspr_rw_l2 = '1'; +iucr2_t1_rden <= iucr2_t1_sel and slowspr_rw_l2 = '1'; +iucr2_t2_rden <= iucr2_t2_sel and slowspr_rw_l2 = '1'; +iucr2_t3_rden <= iucr2_t3_sel and slowspr_rw_l2 = '1'; +ppr32_t0_rden <= ppr32_t0_sel and slowspr_rw_l2 = '1'; +ppr32_t1_rden <= ppr32_t1_sel and slowspr_rw_l2 = '1'; +ppr32_t2_rden <= ppr32_t2_sel and slowspr_rw_l2 = '1'; +ppr32_t3_rden <= ppr32_t3_sel and slowspr_rw_l2 = '1'; + +r64: if (regmode > 5) generate begin +iu_slowspr_data(0 to 31) <= (others => '0'); +end generate; +iu_slowspr_data(32 to 63) <= immr0_L2 when immr0_rden = '1' else + imr0_L2 when imr0_rden = '1' else + iulfsr_L2 when iulfsr_rden = '1' else + iudbg0 when iudbg0_rden = '1' else + iudbg1 when iudbg1_rden = '1' else + iudbg2 when iudbg2_rden = '1' else + iullcr when iullcr_rden = '1' else + iucr0 when iucr0_rden = '1' else + iucr1_t0 when iucr1_t0_rden = '1' else + iucr1_t1 when iucr1_t1_rden = '1' else + iucr1_t2 when iucr1_t2_rden = '1' else + iucr1_t3 when iucr1_t3_rden = '1' else + iucr2_t0 when iucr2_t0_rden = '1' else + iucr2_t1 when iucr2_t1_rden = '1' else + iucr2_t2 when iucr2_t2_rden = '1' else + iucr2_t3 when iucr2_t3_rden = '1' else + ppr32_t0 when ppr32_t0_rden = '1' else + ppr32_t1 when ppr32_t1_rden = '1' else + ppr32_t2 when ppr32_t2_rden = '1' else + ppr32_t3 when ppr32_t3_rden = '1' else + (others => '0'); + + +iudbg0(32 to 63) <= IUDBG0_MASK(32 to 49) & iudbg0_L2(50 to 57) & IUDBG0_MASK(58 to 61) & iudbg0_exec_L2 & iudbg0_done_L2; +iudbg1(32 to 63) <= IUDBG1_MASK(32 to 52) & iudbg1_L2(53 to 63); +iudbg2(32 to 63) <= IUDBG2_MASK(32 to 33) & iudbg2_L2(34 to 63); + +iullcr(32 to 63) <= IULLCR_MASK(32 to 45) & iullcr_L2(46 to 63); +iucr0(32 to 63) <= IUCR0_MASK(32 to 47) & iucr0_L2(48 to 63); + +iucr1_t0(32 to 63) <= IUCR1_MASK(32 to 49) & iucr1_t0_L2(50 to 63); +iucr1_t1(32 to 63) <= IUCR1_MASK(32 to 49) & iucr1_t1_L2(50 to 63); +iucr1_t2(32 to 63) <= IUCR1_MASK(32 to 49) & iucr1_t2_L2(50 to 63); +iucr1_t3(32 to 63) <= IUCR1_MASK(32 to 49) & iucr1_t3_L2(50 to 63); + +iucr2_t0(32 to 63) <= iucr2_t0_L2(32 to 39) & IUCR2_MASK(40 to 63); +iucr2_t1(32 to 63) <= iucr2_t1_L2(32 to 39) & IUCR2_MASK(40 to 63); +iucr2_t2(32 to 63) <= iucr2_t2_L2(32 to 39) & IUCR2_MASK(40 to 63); +iucr2_t3(32 to 63) <= iucr2_t3_L2(32 to 39) & IUCR2_MASK(40 to 63); + +ppr32_t0(32 to 63) <= PPR32_MASK(32 to 42) & ppr32_t0_L2(43 to 45) & PPR32_MASK(46 to 63); +ppr32_t1(32 to 63) <= PPR32_MASK(32 to 42) & ppr32_t1_L2(43 to 45) & PPR32_MASK(46 to 63); +ppr32_t2(32 to 63) <= PPR32_MASK(32 to 42) & ppr32_t2_L2(43 to 45) & PPR32_MASK(46 to 63); +ppr32_t3(32 to 63) <= PPR32_MASK(32 to 42) & ppr32_t3_L2(43 to 45) & PPR32_MASK(46 to 63); + + + + +------------------------------------------------- +-- pervasive +------------------------------------------------- + +perv_2to1_reg: tri_plat + generic map (width => 3, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_iu_func_sl_thold_2, + din(1) => pc_iu_sg_2, + din(2) => pc_iu_cfg_sl_thold_2, + q(0) => pc_iu_func_sl_thold_1, + q(1) => pc_iu_sg_1, + q(2) => pc_iu_cfg_sl_thold_1); + +perv_1to0_reg: tri_plat + generic map (width => 3, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_iu_func_sl_thold_1, + din(1) => pc_iu_sg_1, + din(2) => pc_iu_cfg_sl_thold_1, + q(0) => pc_iu_func_sl_thold_0, + q(1) => pc_iu_sg_0, + q(2) => pc_iu_cfg_sl_thold_0); + +perv_lcbor: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_b, + thold => pc_iu_func_sl_thold_0, + sg => pc_iu_sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => pc_iu_func_sl_thold_0_b); + +cfg_perv_lcbor: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_b, + thold => pc_iu_cfg_sl_thold_0, + sg => pc_iu_sg_0, + act_dis => act_dis, + forcee => cfg_force, + thold_b => pc_iu_cfg_sl_thold_0_b); + + +------------------------------------------------- +-- dummy latches for unused scan chains +------------------------------------------------- + +slat_lcb: tri_lcbs + generic map (expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + delay_lclkr => delay_lclkr, + nclk => nclk, + forcee => cfg_force, + thold_b => pc_iu_cfg_sl_thold_0_b, + dclk => dclk, + lclk => lclk ); + +repower_latch: tri_slat_scan + generic map (width => 2, init => "00", expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + dclk => dclk, + lclk => lclk, + scan_in(0) => bcfg_scan_in, + scan_in(1) => dcfg_scan_in, + scan_out(0) => bcfg_scan_out, + scan_out(1) => dcfg_scan_out, + q => open, + q_b => open); + + + + + +------------------------------------------------- +-- scan +------------------------------------------------- + +siv(0 to scan_right) <= scan_in & sov(0 to scan_right-1); +scan_out <= sov(scan_right); + +ccfg_siv(0 to ccfg_scan_right) <= ccfg_scan_in & ccfg_sov(0 to ccfg_scan_right-1); +ccfg_scan_out <= ccfg_sov(ccfg_scan_right); + +end iuq_spr; diff --git a/rel/src/vhdl/work/iuq_uc.vhdl b/rel/src/vhdl/work/iuq_uc.vhdl new file mode 100644 index 0000000..cee0186 --- /dev/null +++ b/rel/src/vhdl/work/iuq_uc.vhdl @@ -0,0 +1,2416 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +--******************************************************************** +--* +--* TITLE: IU Microcode +--* +--* NAME: iuq_uc.vhdl +--* +--********************************************************************* + +library ieee,ibm,support,tri,work; +use ieee.std_logic_1164.all; +use ibm.std_ulogic_unsigned.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use support.power_logic_pkg.all; +use tri.tri_latches_pkg.all; +use work.iuq_pkg.all; + +entity iuq_uc is + generic(ucode_width : integer := 71; + uc_ifar : integer := 21; + regmode : integer := 6; + expand_type : integer := 2); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + pc_iu_func_sl_thold_2 : in std_ulogic; + pc_iu_sg_2 : in std_ulogic; + an_ac_scan_dis_dc_b : in std_ulogic; + tc_ac_ccflush_dc : in std_ulogic; + clkoff_b : in std_ulogic; + delay_lclkr : in std_ulogic; + mpw1_b : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + spr_ic_clockgate_dis : in std_ulogic; + + iu_pc_err_ucode_illegal : out std_ulogic_vector(0 to 3); + + xu_iu_spr_xer0 : in std_ulogic_vector(57 to 63); + xu_iu_spr_xer1 : in std_ulogic_vector(57 to 63); + xu_iu_spr_xer2 : in std_ulogic_vector(57 to 63); + xu_iu_spr_xer3 : in std_ulogic_vector(57 to 63); + + + xu_iu_flush : in std_ulogic_vector(0 to 3); + xu_iu_ucode_restart : in std_ulogic_vector(0 to 3); + xu_iu_uc_flush_ifar0 : in std_ulogic_vector(62-uc_ifar to 61); + xu_iu_uc_flush_ifar1 : in std_ulogic_vector(62-uc_ifar to 61); + xu_iu_uc_flush_ifar2 : in std_ulogic_vector(62-uc_ifar to 61); + xu_iu_uc_flush_ifar3 : in std_ulogic_vector(62-uc_ifar to 61); + + uc_flush_tid : out std_ulogic_vector(0 to 3); + + fiss_uc_is2_ucode_vld : in std_ulogic; + fiss_uc_is2_tid : in std_ulogic_vector(0 to 3); + fiss_uc_is2_instr : in std_ulogic_vector(0 to 31); + fiss_uc_is2_2ucode : in std_ulogic; + fiss_uc_is2_2ucode_type : in std_ulogic; + + ib_uc_buff0_avail : in std_ulogic; + ib_uc_buff1_avail : in std_ulogic; + ib_uc_buff2_avail : in std_ulogic; + ib_uc_buff3_avail : in std_ulogic; + + uc_ib_iu4_valid_tid : out std_ulogic_vector(0 to 3); + uc_ib_iu4_ifar : out std_ulogic_vector(62-uc_ifar to 61); + uc_ib_iu4_instr : out std_ulogic_vector(0 to 31); + uc_ib_iu4_is_ucode : out std_ulogic; + uc_ib_iu4_ext : out std_ulogic_vector(0 to 3); + + uc_ic_hold_thread : out std_ulogic_vector(0 to 3); + + pc_iu_trace_bus_enable : in std_ulogic; + uc_dbg_data : out std_ulogic_vector(0 to 87) + +); +-- synopsys translate_off +-- synopsys translate_on +end iuq_uc; +ARCHITECTURE IUQ_UC + OF IUQ_UC + IS +--@@ Signal Declarations +SIGNAL GET_ADDRESS_PT : STD_ULOGIC_VECTOR(1 TO 96) := +(OTHERS=> 'U'); +SIGNAL ROM_ISSUE_TABLE_PT : STD_ULOGIC_VECTOR(1 TO 16) := +(OTHERS=> 'U'); +SIGNAL force_ep : STD_ULOGIC := +'U'; +SIGNAL late_end : STD_ULOGIC := +'U'; +SIGNAL romtoken_L2 : STD_ULOGIC_VECTOR(0 TO 3) := +"UUUU"; +SIGNAL romtoken_d : STD_ULOGIC_VECTOR(0 TO 3) := +"UUUU"; +SIGNAL start_addr : STD_ULOGIC_VECTOR(0 TO 9) := +"UUUUUUUUUU"; +SIGNAL uc_legal : STD_ULOGIC := +'U'; +SIGNAL vld_fast : STD_ULOGIC_VECTOR(0 TO 3) := +"UUUU"; +SIGNAL xer_type : STD_ULOGIC := +'U'; +constant xu_iu_flush_offset : natural := 0; +constant xu_iu_ucode_restart_offset : natural := xu_iu_flush_offset + 4; +constant xu_iu_uc_flush_ifar0_offset : natural := xu_iu_ucode_restart_offset + 4; +constant xu_iu_uc_flush_ifar1_offset : natural := xu_iu_uc_flush_ifar0_offset + uc_ifar; +constant xu_iu_uc_flush_ifar2_offset : natural := xu_iu_uc_flush_ifar1_offset + uc_ifar; +constant xu_iu_uc_flush_ifar3_offset : natural := xu_iu_uc_flush_ifar2_offset + uc_ifar; +constant iu_pc_err_ucode_illegal_offset : natural := xu_iu_uc_flush_ifar3_offset + uc_ifar; +constant ib_uc_buff_avail_offset : natural := iu_pc_err_ucode_illegal_offset + 4; +constant fiss_uc_is2_ucode_vld_offset : natural := ib_uc_buff_avail_offset + 4; +constant fiss_uc_is2_tid_offset : natural := fiss_uc_is2_ucode_vld_offset + 1; +constant fiss_uc_is2_instr_offset : natural := fiss_uc_is2_tid_offset + 4; +constant fiss_uc_is2_2ucode_offset : natural := fiss_uc_is2_instr_offset + 32; +constant fiss_uc_is2_2ucode_type_offset : natural := fiss_uc_is2_2ucode_offset + 1; +constant romtoken_offset : natural := fiss_uc_is2_2ucode_type_offset + 1; +constant romvalid_offset : natural := romtoken_offset + 4; +constant rom_data_late_offset : natural := romvalid_offset + 4; +constant iu4_valid_tid_offset : natural := rom_data_late_offset + 32; +constant iu4_data_tid_offset : natural := iu4_valid_tid_offset + 4; +constant iu4_ifar_offset : natural := iu4_data_tid_offset + 4; +constant iu4_is_ucode_offset : natural := iu4_ifar_offset + uc_ifar; +constant iu4_ext_offset : natural := iu4_is_ucode_offset + 1; +constant iu5_valid_tid_offset : natural := iu4_ext_offset + 4; +constant iu5_ifar_offset : natural := iu5_valid_tid_offset + 4; +constant uc_dbg_data_offset : natural := iu5_ifar_offset + uc_ifar; +constant spare_offset : natural := uc_dbg_data_offset + 16; +constant trace_bus_enable_offset: natural := spare_offset + 12; +constant scan_right : natural := trace_bus_enable_offset + 1 - 1; +signal trace_bus_enable_d : std_ulogic; +signal trace_bus_enable_q : std_ulogic; +-- Latches +signal iu_pc_err_ucode_illegal_d : std_ulogic_vector(0 to 3); +signal iu_pc_err_ucode_illegal_l2 : std_ulogic_vector(0 to 3); +signal fiss_uc_is2_ucode_vld_d : std_ulogic; +signal fiss_uc_is2_tid_d : std_ulogic_vector(0 to 3); +signal fiss_uc_is2_instr_d : std_ulogic_vector(0 to 31); +signal fiss_uc_is2_2ucode_d : std_ulogic; +signal fiss_uc_is2_2ucode_type_d: std_ulogic; +signal fiss_uc_is2_ucode_vld_l2 : std_ulogic; +signal fiss_uc_is2_tid_l2 : std_ulogic_vector(0 to 3); +signal fiss_uc_is2_instr_l2 : std_ulogic_vector(0 to 31); +signal fiss_uc_is2_2ucode_l2 : std_ulogic; +signal fiss_uc_is2_2ucode_type_l2 : std_ulogic; +signal romvalid_d : std_ulogic_vector(0 to 3); +signal romvalid_l2 : std_ulogic_vector(0 to 3); +signal xu_iu_flush_d : std_ulogic_vector(0 to 3); +signal xu_iu_flush_l2 : std_ulogic_vector(0 to 3); +signal xu_iu_ucode_restart_d : std_ulogic_vector(0 to 3); +signal xu_iu_ucode_restart_l2 : std_ulogic_vector(0 to 3); +signal xu_iu_uc_flush_ifar0_d : std_ulogic_vector(62-uc_ifar to 61); +signal xu_iu_uc_flush_ifar0_l2 : std_ulogic_vector(62-uc_ifar to 61); +signal xu_iu_uc_flush_ifar1_d : std_ulogic_vector(62-uc_ifar to 61); +signal xu_iu_uc_flush_ifar1_l2 : std_ulogic_vector(62-uc_ifar to 61); +signal xu_iu_uc_flush_ifar2_d : std_ulogic_vector(62-uc_ifar to 61); +signal xu_iu_uc_flush_ifar2_l2 : std_ulogic_vector(62-uc_ifar to 61); +signal xu_iu_uc_flush_ifar3_d : std_ulogic_vector(62-uc_ifar to 61); +signal xu_iu_uc_flush_ifar3_l2 : std_ulogic_vector(62-uc_ifar to 61); +signal iu4_valid_tid_d : std_ulogic_vector(0 to 3); +signal iu4_data_tid_d : std_ulogic_vector(0 to 3); +signal iu4_ifar_d : std_ulogic_vector(62-uc_ifar to 61); +signal iu4_is_ucode_d : std_ulogic; +signal iu4_ext_d : std_ulogic_vector(0 to 3); +signal iu4_valid_tid_l2 : std_ulogic_vector(0 to 3); +signal iu4_data_tid_l2 : std_ulogic_vector(0 to 3); +signal iu4_ifar_l2 : std_ulogic_vector(62-uc_ifar to 61); +signal iu4_instr_l2 : std_ulogic_vector(0 to 31); +signal iu4_is_ucode_l2 : std_ulogic; +signal iu4_ext_l2 : std_ulogic_vector(0 to 3); +signal iu5_ifar_l2 : std_ulogic_vector(62-uc_ifar to 61); +signal ib_uc_buff_avail_d : std_ulogic_vector(0 to 3); +signal ib_uc_buff_avail_l2 : std_ulogic_vector(0 to 3); +signal spare_l2 : std_ulogic_vector(0 to 11); +signal load_command : std_ulogic_vector(0 to 3); +signal early_end : std_ulogic; +signal new_cond : std_ulogic; +signal rom_ra0 : std_ulogic_vector(0 to 9); +signal ucode_ifar0 : std_ulogic_vector(62-uc_ifar to 61); +signal ucode_instr0 : std_ulogic_vector(0 to 31); +signal ucode_is_ucode0: std_ulogic; +signal ucode_ext0 : std_ulogic_vector(0 to 3); +signal rom_ra1 : std_ulogic_vector(0 to 9); +signal ucode_ifar1 : std_ulogic_vector(62-uc_ifar to 61); +signal ucode_instr1 : std_ulogic_vector(0 to 31); +signal ucode_is_ucode1: std_ulogic; +signal ucode_ext1 : std_ulogic_vector(0 to 3); +signal rom_ra2 : std_ulogic_vector(0 to 9); +signal ucode_ifar2 : std_ulogic_vector(62-uc_ifar to 61); +signal ucode_instr2 : std_ulogic_vector(0 to 31); +signal ucode_is_ucode2: std_ulogic; +signal ucode_ext2 : std_ulogic_vector(0 to 3); +signal rom_ra3 : std_ulogic_vector(0 to 9); +signal ucode_ifar3 : std_ulogic_vector(62-uc_ifar to 61); +signal ucode_instr3 : std_ulogic_vector(0 to 31); +signal ucode_is_ucode3: std_ulogic; +signal ucode_ext3 : std_ulogic_vector(0 to 3); +signal ucode_valid : std_ulogic_vector(0 to 3); +signal uc_control_dbg_data0 : std_ulogic_vector(0 to 3); +signal uc_control_dbg_data1 : std_ulogic_vector(0 to 3); +signal uc_control_dbg_data2 : std_ulogic_vector(0 to 3); +signal uc_control_dbg_data3 : std_ulogic_vector(0 to 3); +signal uc_act : std_ulogic_vector(0 to 3); +signal uc_any_act : std_ulogic; +signal rom_act : std_ulogic; +signal rom_addr : std_ulogic_vector(0 to 9); +signal rom_data_tid : std_ulogic_vector(0 to 3); +signal data_valid : std_ulogic_vector(0 to 3); +signal rom_data : std_ulogic_vector(0 to ucode_width-1); +signal rom_data_late_d : std_ulogic_vector(0 to 31); +signal rom_data_late_l2 : std_ulogic_vector(0 to 31); +signal iu4_stage_act : std_ulogic; +signal ib_flush : std_ulogic_vector(0 to 3); +signal vld_mask : std_ulogic_vector(0 to 3); +signal pc_iu_func_sl_thold_1 : std_ulogic; +signal pc_iu_func_sl_thold_0 : std_ulogic; +signal pc_iu_func_sl_thold_0_b : std_ulogic; +signal pc_iu_sg_1 : std_ulogic; +signal pc_iu_sg_0 : std_ulogic; +signal forcee : std_ulogic; +signal siv : std_ulogic_vector(0 to scan_right+5); +signal sov : std_ulogic_vector(0 to scan_right+5); +signal tiup : std_ulogic; +signal act_dis : std_ulogic; +signal d_mode : std_ulogic; +signal mpw2_b : std_ulogic; +signal uc_dbg_data_d : std_ulogic_vector(44 to 59); +signal uc_dbg_data_l2 : std_ulogic_vector(44 to 59); +-- synopsys translate_off +-- synopsys translate_on + BEGIN --@@ START OF EXECUTABLE CODE FOR IUQ_UC + +tiup <= '1'; +act_dis <= '0'; +d_mode <= '0'; +mpw2_b <= '1'; +----------------------------------------------------------------------- +-- latch inputs +----------------------------------------------------------------------- +fiss_uc_is2_ucode_vld_d <= fiss_uc_is2_ucode_vld; +fiss_uc_is2_tid_d <= fiss_uc_is2_tid and not xu_iu_flush; +fiss_uc_is2_instr_d <= fiss_uc_is2_instr; +fiss_uc_is2_2ucode_d <= fiss_uc_is2_2ucode; +fiss_uc_is2_2ucode_type_d <= fiss_uc_is2_2ucode_type; +----------------------------------------------------------------------- +-- select thread +----------------------------------------------------------------------- +load_command <= gate_and(fiss_uc_is2_ucode_vld_l2, fiss_uc_is2_tid_l2); +-- output +uc_flush_tid <= gate_and(fiss_uc_is2_ucode_vld_l2, fiss_uc_is2_tid_l2); +early_end <= not late_end; +-- If '1', will skip lines with skip_cond bit set +new_cond <= not fiss_uc_is2_2ucode_type_l2; +----------------------------------------------------------------------- +-- look up address +----------------------------------------------------------------------- +-- +-- Final Table Listing +-- *INPUTS*===========================================*OUTPUTS*==================* +-- | | | +-- | fiss_uc_is2_instr_l2 | start_addr | +-- | | fiss_uc_is2_instr_l2 | | | +-- | | | fiss_uc_is2_2ucode_l2 | | xer_type | +-- | | | | fiss_uc_is2_2ucode_type_l2 | | | late_end | # For update form, etc. +-- | | | | | | | | | force_ep | +-- | | | | | | | | | | uc_legal| +-- | | 22222222233 | | | | | | | | | +-- | 012345 12345678901 | | | 0123456789 | | | | | +-- *TYPE*=============================================+==========================+ +-- | PPPPPP PPPPPPPPPPP P P | SSSSSSSSSS S S S S | +-- *POLARITY*---------------------------------------->| ++++++++++ + + + + | +-- *PHASE*------------------------------------------->| TTTTTTTTTT T T T T | +-- *TERMS*============================================+==========================+ +-- 1 | 011111 10-1011111- - - | .......... . . 1 . | +-- 2 | 011111 0000111010- - - | .....111.. . . . . | +-- 3 | 011111 1000010101- - - | .....1..11 1 . . . | +-- 4 | 011111 0101110101- 1 - | ...1..11.. . 1 . 1 | +-- 5 | -11111 01-1111010- - - | .....11... . . . . | +-- 6 | 011111 1000000000- - - | .11.1..... . 1 . 1 | +-- 7 | 000-00 11-1001110- - - | 111.1111.. . 1 . 1 | +-- 8 | 011111 0000110101- 1 - | ...11..1.. . 1 . 1 | +-- 9 | 011111 1110010110- - - | ...111.1.. . . . . | +-- 10 | -11111 0111111010- - - | .1..1..... . 1 . 1 | +-- 11 | 011111 00-00111-1- - - | .......... . . 1 . | +-- 12 | 011111 1010-10111- - - | ......1..1 . . . . | +-- 13 | 011111 0--0011111- - - | .......... . . 1 . | +-- 14 | 011111 0101-10111- - - | .....1.1.. . . . . | +-- 15 | 011111 1000-10111- - - | .......11. . . . . | +-- 16 | 011111 0101010101- - - | ...1..11.. . . . 1 | +-- 17 | 011111 0101110101- 0 - | 1....111.. . 1 . 1 | +-- 18 | -11111 0000110101- 0 - | 1...1..... . 1 . 1 | +-- 19 | 011111 0010011010- - - | .1.11..... . 1 . 1 | +-- 20 | 011111 1000010100- - - | ...11..1.. . . . 1 | +-- 21 | 011111 010-110111- 1 - | ......1.11 . 1 . 1 | +-- 22 | 011111 0000110111- 1 - | ....11.1.. . 1 . 1 | +-- 23 | 011111 0000110111- 0 - | 1....11... . 1 . 1 | +-- 24 | 011111 010-110111- 0 - | 1....1.... . 1 . 1 | +-- 25 | -11111 0-01111010- - - | .1........ . 1 . 1 | +-- 26 | 011111 0000-11010- - - | ..11...... . 1 . 1 | +-- 27 | 011111 0010111010- - - | .1.1.11... . 1 . 1 | +-- 28 | 011111 10-1-10111- - - | ....1..... . . . . | +-- 29 | 011111 10--110111- - - | .......... . 1 . . | +-- 30 | 011111 1010010110- - - | ..1..1.11. . . . 1 | +-- 31 | 011111 0011111100- - - | .1.11.1... . 1 . 1 | +-- 32 | 011111 1000010110- - - | ....11.1.. . . . 1 | +-- 33 | 011111 11-0010110- - - | ......1.11 . . . 1 | +-- 34 | 011111 011001-111- - - | ...111.1.. . . . . | +-- 35 | 011111 1010010100- - - | ..1.1.11.1 . . . 1 | +-- 36 | 011111 010-010111- - - | ......1.11 . . . 1 | +-- 37 | 111111 0010000000- - - | 111.11.1.1 . 1 . 1 | +-- 38 | 011111 1011010101- - - | 1..1.1.1.. . 1 . 1 | +-- 39 | 011111 0001110111- - - | 1.....11.. . 1 . 1 | +-- 40 | 011111 000001-101- - - | ...11..1.. . . . 1 | +-- 41 | 011111 0010110111- - - | ..1..1.11. . 1 . 1 | +-- 42 | 011111 1010010101- - - | 1..11..1.. 1 1 . 1 | +-- 43 | 111111 1011000111- - - | 111.111... . 1 . 1 | +-- 44 | 011111 0010110101- - - | ..1.1.11.1 . 1 . 1 | +-- 45 | 011111 001001-111- - - | ..1..1.11. . . . 1 | +-- 46 | 111111 00-0100000- - - | 111.111... . 1 . 1 | +-- 47 | 011111 000001-111- - - | ....11.1.. . . . 1 | +-- 48 | 011111 01-001-111- - - | ......1.11 . . . 1 | +-- 49 | 011111 101101-111- - - | 11.11...1. . . . 1 | +-- 50 | 011111 1101010111- - - | 1.111.1... . 1 . 1 | +-- 51 | 100001 ----------- 0 - | .......1.. . . . . | +-- 52 | 111111 0000-00000- - - | 111.111... . 1 . 1 | +-- 53 | 011111 100101-111- - - | 11..1.1... . . . 1 | +-- 54 | 011111 001001-101- - - | ..1.1.11.1 . . . 1 | +-- 55 | 011111 1111010111- - - | 11..11.11. . 1 . 1 | +-- 56 | 011111 1101110111- - - | 1.1111..11 . 1 . 1 | +-- 57 | 011111 101--10111- - - | 11.1....1. . . . 1 | +-- 58 | 011111 100--10111- - - | 11....1... . . . 1 | +-- 59 | 011111 0110110111- - - | ...1111111 . 1 . 1 | +-- 60 | -11111 100-010101- - - | 1...1.1... . 1 . 1 | +-- 61 | 10000- ----------- 1 - | ....1.1... . . . . | +-- 62 | 11-010 ---------01 0 - | 1.....1... . . . 1 | +-- 63 | 10-001 ----------- 0 - | 1.......1. . . . . | +-- 64 | 111-11 11-10-1110- - - | 111.111... . 1 . 1 | +-- 65 | 11-011 -----1--10- - - | .....1.... . . . . | +-- 66 | 100000 ----------- - - | ....1.1... . . . 1 | +-- 67 | 111-10 ---------01 - - | .......... . 1 . . | +-- 68 | 101011 ----------- 0 - | 1......1.. . . . . | +-- 69 | 111010 ---------10 - - | ...1...... . 1 . 1 | +-- 70 | 10101- ----------- 1 - | .....1.1.. . . . . | +-- 71 | 111010 ---------00 - - | ...1.11... . . . 1 | +-- 72 | 000-00 -----0-0-1- - - | 111.111... . 1 . 1 | +-- 73 | 101010 ----------- - - | .....1.1.. . . . . | +-- 74 | 111010 ---------0- 1 - | ...1.11... . . . 1 | +-- 75 | 111-11 -----1-1-0- - - | ....1..... . . . . | +-- 76 | 000-00 -----11--0- - - | 111.111... . 1 . 1 | +-- 77 | 000-00 -----111--- - - | 111.111... . 1 . 1 | +-- 78 | 000-00 -----1-10-- - - | 111.111... . 1 . 1 | +-- 79 | 10010- ----------- - - | ..1...1.1. . . . 1 | +-- 80 | 11001- ----------- - - | .....11..1 . . . . | +-- 81 | 111110 ---------0- - - | ..1.1....1 . . . 1 | +-- 82 | 110--1 ----------- - - | .......... . 1 . . | +-- 83 | 101--1 ----------- - - | .......... . 1 . . | +-- 84 | 1-0-01 ----------- - - | .......... . 1 . 1 | +-- 85 | 10110- ----------- - - | ...111.1.. . . . . | +-- 86 | 101110 ----------- - - | 1...1..1.. . 1 . . | +-- 87 | 101111 ----------- - - | 1..1.1.... . . . . | +-- 88 | 111-11 -----10-10- - - | 1111...... . 1 . 1 | +-- 89 | 11011- ----------- - - | .....1.11. . . . . | +-- 90 | 1-0011 ----------- - - | 1......... . 1 . 1 | +-- 91 | 1100-- ----------- - - | 11......1. . . . 1 | +-- 92 | 101--- ----------- - - | .......... . . . 1 | +-- 93 | 1101-- ----------- - - | 11.1...... . . . 1 | +-- 94 | 111-11 -----11--0- - - | 111.111... . 1 . 1 | +-- 95 | 111-11 -----111--- - - | 111.111... . 1 . 1 | +-- 96 | 111-11 -----1-10-- - - | 111.111... . 1 . 1 | +-- *=============================================================================* +-- +-- Table GET_ADDRESS Signal Assignments for Product Terms +MQQ1:GET_ADDRESS_PT(1) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(24) & FISS_UC_IS2_INSTR_L2(25) & + FISS_UC_IS2_INSTR_L2(26) & FISS_UC_IS2_INSTR_L2(27) & + FISS_UC_IS2_INSTR_L2(28) & FISS_UC_IS2_INSTR_L2(29) & + FISS_UC_IS2_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("011111101011111")); +MQQ2:GET_ADDRESS_PT(2) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("0111110000111010")); +MQQ3:GET_ADDRESS_PT(3) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("0111111000010101")); +MQQ4:GET_ADDRESS_PT(4) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) & + FISS_UC_IS2_2UCODE_L2 ) , STD_ULOGIC_VECTOR'("01111101011101011")); +MQQ5:GET_ADDRESS_PT(5) <= + Eq(( FISS_UC_IS2_INSTR_L2(1) & FISS_UC_IS2_INSTR_L2(2) & + FISS_UC_IS2_INSTR_L2(3) & FISS_UC_IS2_INSTR_L2(4) & + FISS_UC_IS2_INSTR_L2(5) & FISS_UC_IS2_INSTR_L2(21) & + FISS_UC_IS2_INSTR_L2(22) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("11111011111010")); +MQQ6:GET_ADDRESS_PT(6) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("0111111000000000")); +MQQ7:GET_ADDRESS_PT(7) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(4) & + FISS_UC_IS2_INSTR_L2(5) & FISS_UC_IS2_INSTR_L2(21) & + FISS_UC_IS2_INSTR_L2(22) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("00000111001110")); +MQQ8:GET_ADDRESS_PT(8) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) & + FISS_UC_IS2_2UCODE_L2 ) , STD_ULOGIC_VECTOR'("01111100001101011")); +MQQ9:GET_ADDRESS_PT(9) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("0111111110010110")); +MQQ10:GET_ADDRESS_PT(10) <= + Eq(( FISS_UC_IS2_INSTR_L2(1) & FISS_UC_IS2_INSTR_L2(2) & + FISS_UC_IS2_INSTR_L2(3) & FISS_UC_IS2_INSTR_L2(4) & + FISS_UC_IS2_INSTR_L2(5) & FISS_UC_IS2_INSTR_L2(21) & + FISS_UC_IS2_INSTR_L2(22) & FISS_UC_IS2_INSTR_L2(23) & + FISS_UC_IS2_INSTR_L2(24) & FISS_UC_IS2_INSTR_L2(25) & + FISS_UC_IS2_INSTR_L2(26) & FISS_UC_IS2_INSTR_L2(27) & + FISS_UC_IS2_INSTR_L2(28) & FISS_UC_IS2_INSTR_L2(29) & + FISS_UC_IS2_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("111110111111010")); +MQQ11:GET_ADDRESS_PT(11) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(24) & FISS_UC_IS2_INSTR_L2(25) & + FISS_UC_IS2_INSTR_L2(26) & FISS_UC_IS2_INSTR_L2(27) & + FISS_UC_IS2_INSTR_L2(28) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("01111100001111")); +MQQ12:GET_ADDRESS_PT(12) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(26) & FISS_UC_IS2_INSTR_L2(27) & + FISS_UC_IS2_INSTR_L2(28) & FISS_UC_IS2_INSTR_L2(29) & + FISS_UC_IS2_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("011111101010111")); +MQQ13:GET_ADDRESS_PT(13) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("01111100011111")); +MQQ14:GET_ADDRESS_PT(14) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(26) & FISS_UC_IS2_INSTR_L2(27) & + FISS_UC_IS2_INSTR_L2(28) & FISS_UC_IS2_INSTR_L2(29) & + FISS_UC_IS2_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("011111010110111")); +MQQ15:GET_ADDRESS_PT(15) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(26) & FISS_UC_IS2_INSTR_L2(27) & + FISS_UC_IS2_INSTR_L2(28) & FISS_UC_IS2_INSTR_L2(29) & + FISS_UC_IS2_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("011111100010111")); +MQQ16:GET_ADDRESS_PT(16) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("0111110101010101")); +MQQ17:GET_ADDRESS_PT(17) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) & + FISS_UC_IS2_2UCODE_L2 ) , STD_ULOGIC_VECTOR'("01111101011101010")); +MQQ18:GET_ADDRESS_PT(18) <= + Eq(( FISS_UC_IS2_INSTR_L2(1) & FISS_UC_IS2_INSTR_L2(2) & + FISS_UC_IS2_INSTR_L2(3) & FISS_UC_IS2_INSTR_L2(4) & + FISS_UC_IS2_INSTR_L2(5) & FISS_UC_IS2_INSTR_L2(21) & + FISS_UC_IS2_INSTR_L2(22) & FISS_UC_IS2_INSTR_L2(23) & + FISS_UC_IS2_INSTR_L2(24) & FISS_UC_IS2_INSTR_L2(25) & + FISS_UC_IS2_INSTR_L2(26) & FISS_UC_IS2_INSTR_L2(27) & + FISS_UC_IS2_INSTR_L2(28) & FISS_UC_IS2_INSTR_L2(29) & + FISS_UC_IS2_INSTR_L2(30) & FISS_UC_IS2_2UCODE_L2 + ) , STD_ULOGIC_VECTOR'("1111100001101010")); +MQQ19:GET_ADDRESS_PT(19) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("0111110010011010")); +MQQ20:GET_ADDRESS_PT(20) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("0111111000010100")); +MQQ21:GET_ADDRESS_PT(21) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(25) & + FISS_UC_IS2_INSTR_L2(26) & FISS_UC_IS2_INSTR_L2(27) & + FISS_UC_IS2_INSTR_L2(28) & FISS_UC_IS2_INSTR_L2(29) & + FISS_UC_IS2_INSTR_L2(30) & FISS_UC_IS2_2UCODE_L2 + ) , STD_ULOGIC_VECTOR'("0111110101101111")); +MQQ22:GET_ADDRESS_PT(22) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) & + FISS_UC_IS2_2UCODE_L2 ) , STD_ULOGIC_VECTOR'("01111100001101111")); +MQQ23:GET_ADDRESS_PT(23) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) & + FISS_UC_IS2_2UCODE_L2 ) , STD_ULOGIC_VECTOR'("01111100001101110")); +MQQ24:GET_ADDRESS_PT(24) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(25) & + FISS_UC_IS2_INSTR_L2(26) & FISS_UC_IS2_INSTR_L2(27) & + FISS_UC_IS2_INSTR_L2(28) & FISS_UC_IS2_INSTR_L2(29) & + FISS_UC_IS2_INSTR_L2(30) & FISS_UC_IS2_2UCODE_L2 + ) , STD_ULOGIC_VECTOR'("0111110101101110")); +MQQ25:GET_ADDRESS_PT(25) <= + Eq(( FISS_UC_IS2_INSTR_L2(1) & FISS_UC_IS2_INSTR_L2(2) & + FISS_UC_IS2_INSTR_L2(3) & FISS_UC_IS2_INSTR_L2(4) & + FISS_UC_IS2_INSTR_L2(5) & FISS_UC_IS2_INSTR_L2(21) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("11111001111010")); +MQQ26:GET_ADDRESS_PT(26) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(26) & FISS_UC_IS2_INSTR_L2(27) & + FISS_UC_IS2_INSTR_L2(28) & FISS_UC_IS2_INSTR_L2(29) & + FISS_UC_IS2_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("011111000011010")); +MQQ27:GET_ADDRESS_PT(27) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("0111110010111010")); +MQQ28:GET_ADDRESS_PT(28) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(24) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("01111110110111")); +MQQ29:GET_ADDRESS_PT(29) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("01111110110111")); +MQQ30:GET_ADDRESS_PT(30) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("0111111010010110")); +MQQ31:GET_ADDRESS_PT(31) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("0111110011111100")); +MQQ32:GET_ADDRESS_PT(32) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("0111111000010110")); +MQQ33:GET_ADDRESS_PT(33) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(24) & FISS_UC_IS2_INSTR_L2(25) & + FISS_UC_IS2_INSTR_L2(26) & FISS_UC_IS2_INSTR_L2(27) & + FISS_UC_IS2_INSTR_L2(28) & FISS_UC_IS2_INSTR_L2(29) & + FISS_UC_IS2_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("011111110010110")); +MQQ34:GET_ADDRESS_PT(34) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(28) & FISS_UC_IS2_INSTR_L2(29) & + FISS_UC_IS2_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("011111011001111")); +MQQ35:GET_ADDRESS_PT(35) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("0111111010010100")); +MQQ36:GET_ADDRESS_PT(36) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(25) & + FISS_UC_IS2_INSTR_L2(26) & FISS_UC_IS2_INSTR_L2(27) & + FISS_UC_IS2_INSTR_L2(28) & FISS_UC_IS2_INSTR_L2(29) & + FISS_UC_IS2_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("011111010010111")); +MQQ37:GET_ADDRESS_PT(37) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("1111110010000000")); +MQQ38:GET_ADDRESS_PT(38) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("0111111011010101")); +MQQ39:GET_ADDRESS_PT(39) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("0111110001110111")); +MQQ40:GET_ADDRESS_PT(40) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(28) & FISS_UC_IS2_INSTR_L2(29) & + FISS_UC_IS2_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("011111000001101")); +MQQ41:GET_ADDRESS_PT(41) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("0111110010110111")); +MQQ42:GET_ADDRESS_PT(42) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("0111111010010101")); +MQQ43:GET_ADDRESS_PT(43) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("1111111011000111")); +MQQ44:GET_ADDRESS_PT(44) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("0111110010110101")); +MQQ45:GET_ADDRESS_PT(45) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(28) & FISS_UC_IS2_INSTR_L2(29) & + FISS_UC_IS2_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("011111001001111")); +MQQ46:GET_ADDRESS_PT(46) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(24) & FISS_UC_IS2_INSTR_L2(25) & + FISS_UC_IS2_INSTR_L2(26) & FISS_UC_IS2_INSTR_L2(27) & + FISS_UC_IS2_INSTR_L2(28) & FISS_UC_IS2_INSTR_L2(29) & + FISS_UC_IS2_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("111111000100000")); +MQQ47:GET_ADDRESS_PT(47) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(28) & FISS_UC_IS2_INSTR_L2(29) & + FISS_UC_IS2_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("011111000001111")); +MQQ48:GET_ADDRESS_PT(48) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(24) & FISS_UC_IS2_INSTR_L2(25) & + FISS_UC_IS2_INSTR_L2(26) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("01111101001111")); +MQQ49:GET_ADDRESS_PT(49) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(28) & FISS_UC_IS2_INSTR_L2(29) & + FISS_UC_IS2_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("011111101101111")); +MQQ50:GET_ADDRESS_PT(50) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("0111111101010111")); +MQQ51:GET_ADDRESS_PT(51) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_2UCODE_L2 ) , STD_ULOGIC_VECTOR'("1000010")); +MQQ52:GET_ADDRESS_PT(52) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(26) & FISS_UC_IS2_INSTR_L2(27) & + FISS_UC_IS2_INSTR_L2(28) & FISS_UC_IS2_INSTR_L2(29) & + FISS_UC_IS2_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("111111000000000")); +MQQ53:GET_ADDRESS_PT(53) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(28) & FISS_UC_IS2_INSTR_L2(29) & + FISS_UC_IS2_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("011111100101111")); +MQQ54:GET_ADDRESS_PT(54) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(28) & FISS_UC_IS2_INSTR_L2(29) & + FISS_UC_IS2_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("011111001001101")); +MQQ55:GET_ADDRESS_PT(55) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("0111111111010111")); +MQQ56:GET_ADDRESS_PT(56) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("0111111101110111")); +MQQ57:GET_ADDRESS_PT(57) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("01111110110111")); +MQQ58:GET_ADDRESS_PT(58) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("01111110010111")); +MQQ59:GET_ADDRESS_PT(59) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(21) & FISS_UC_IS2_INSTR_L2(22) & + FISS_UC_IS2_INSTR_L2(23) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("0111110110110111")); +MQQ60:GET_ADDRESS_PT(60) <= + Eq(( FISS_UC_IS2_INSTR_L2(1) & FISS_UC_IS2_INSTR_L2(2) & + FISS_UC_IS2_INSTR_L2(3) & FISS_UC_IS2_INSTR_L2(4) & + FISS_UC_IS2_INSTR_L2(5) & FISS_UC_IS2_INSTR_L2(21) & + FISS_UC_IS2_INSTR_L2(22) & FISS_UC_IS2_INSTR_L2(23) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("11111100010101")); +MQQ61:GET_ADDRESS_PT(61) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_2UCODE_L2 + ) , STD_ULOGIC_VECTOR'("100001")); +MQQ62:GET_ADDRESS_PT(62) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(3) & FISS_UC_IS2_INSTR_L2(4) & + FISS_UC_IS2_INSTR_L2(5) & FISS_UC_IS2_INSTR_L2(30) & + FISS_UC_IS2_INSTR_L2(31) & FISS_UC_IS2_2UCODE_L2 + ) , STD_ULOGIC_VECTOR'("11010010")); +MQQ63:GET_ADDRESS_PT(63) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(3) & FISS_UC_IS2_INSTR_L2(4) & + FISS_UC_IS2_INSTR_L2(5) & FISS_UC_IS2_2UCODE_L2 + ) , STD_ULOGIC_VECTOR'("100010")); +MQQ64:GET_ADDRESS_PT(64) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(4) & + FISS_UC_IS2_INSTR_L2(5) & FISS_UC_IS2_INSTR_L2(21) & + FISS_UC_IS2_INSTR_L2(22) & FISS_UC_IS2_INSTR_L2(24) & + FISS_UC_IS2_INSTR_L2(25) & FISS_UC_IS2_INSTR_L2(27) & + FISS_UC_IS2_INSTR_L2(28) & FISS_UC_IS2_INSTR_L2(29) & + FISS_UC_IS2_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("1111111101110")); +MQQ65:GET_ADDRESS_PT(65) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(3) & FISS_UC_IS2_INSTR_L2(4) & + FISS_UC_IS2_INSTR_L2(5) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(29) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("11011110")); +MQQ66:GET_ADDRESS_PT(66) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) + ) , STD_ULOGIC_VECTOR'("100000")); +MQQ67:GET_ADDRESS_PT(67) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(4) & + FISS_UC_IS2_INSTR_L2(5) & FISS_UC_IS2_INSTR_L2(30) & + FISS_UC_IS2_INSTR_L2(31) ) , STD_ULOGIC_VECTOR'("1111001")); +MQQ68:GET_ADDRESS_PT(68) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_2UCODE_L2 ) , STD_ULOGIC_VECTOR'("1010110")); +MQQ69:GET_ADDRESS_PT(69) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(30) & FISS_UC_IS2_INSTR_L2(31) + ) , STD_ULOGIC_VECTOR'("11101010")); +MQQ70:GET_ADDRESS_PT(70) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_2UCODE_L2 + ) , STD_ULOGIC_VECTOR'("101011")); +MQQ71:GET_ADDRESS_PT(71) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(30) & FISS_UC_IS2_INSTR_L2(31) + ) , STD_ULOGIC_VECTOR'("11101000")); +MQQ72:GET_ADDRESS_PT(72) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(4) & + FISS_UC_IS2_INSTR_L2(5) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(28) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("00000001")); +MQQ73:GET_ADDRESS_PT(73) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) + ) , STD_ULOGIC_VECTOR'("101010")); +MQQ74:GET_ADDRESS_PT(74) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(30) & FISS_UC_IS2_2UCODE_L2 + ) , STD_ULOGIC_VECTOR'("11101001")); +MQQ75:GET_ADDRESS_PT(75) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(4) & + FISS_UC_IS2_INSTR_L2(5) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(28) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("11111110")); +MQQ76:GET_ADDRESS_PT(76) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(4) & + FISS_UC_IS2_INSTR_L2(5) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("00000110")); +MQQ77:GET_ADDRESS_PT(77) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(4) & + FISS_UC_IS2_INSTR_L2(5) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) + ) , STD_ULOGIC_VECTOR'("00000111")); +MQQ78:GET_ADDRESS_PT(78) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(4) & + FISS_UC_IS2_INSTR_L2(5) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(28) & FISS_UC_IS2_INSTR_L2(29) + ) , STD_ULOGIC_VECTOR'("00000110")); +MQQ79:GET_ADDRESS_PT(79) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) ) , STD_ULOGIC_VECTOR'("10010")); +MQQ80:GET_ADDRESS_PT(80) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) ) , STD_ULOGIC_VECTOR'("11001")); +MQQ81:GET_ADDRESS_PT(81) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) & + FISS_UC_IS2_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("1111100")); +MQQ82:GET_ADDRESS_PT(82) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(5) + ) , STD_ULOGIC_VECTOR'("1101")); +MQQ83:GET_ADDRESS_PT(83) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(5) + ) , STD_ULOGIC_VECTOR'("1011")); +MQQ84:GET_ADDRESS_PT(84) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(2) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) + ) , STD_ULOGIC_VECTOR'("1001")); +MQQ85:GET_ADDRESS_PT(85) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) ) , STD_ULOGIC_VECTOR'("10110")); +MQQ86:GET_ADDRESS_PT(86) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) + ) , STD_ULOGIC_VECTOR'("101110")); +MQQ87:GET_ADDRESS_PT(87) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) & FISS_UC_IS2_INSTR_L2(5) + ) , STD_ULOGIC_VECTOR'("101111")); +MQQ88:GET_ADDRESS_PT(88) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(4) & + FISS_UC_IS2_INSTR_L2(5) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(29) & + FISS_UC_IS2_INSTR_L2(30) ) , STD_ULOGIC_VECTOR'("111111010")); +MQQ89:GET_ADDRESS_PT(89) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) & + FISS_UC_IS2_INSTR_L2(4) ) , STD_ULOGIC_VECTOR'("11011")); +MQQ90:GET_ADDRESS_PT(90) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(2) & + FISS_UC_IS2_INSTR_L2(3) & FISS_UC_IS2_INSTR_L2(4) & + FISS_UC_IS2_INSTR_L2(5) ) , STD_ULOGIC_VECTOR'("10011")); +MQQ91:GET_ADDRESS_PT(91) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) + ) , STD_ULOGIC_VECTOR'("1100")); +MQQ92:GET_ADDRESS_PT(92) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) ) , STD_ULOGIC_VECTOR'("101")); +MQQ93:GET_ADDRESS_PT(93) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(3) + ) , STD_ULOGIC_VECTOR'("1101")); +MQQ94:GET_ADDRESS_PT(94) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(4) & + FISS_UC_IS2_INSTR_L2(5) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(30) + ) , STD_ULOGIC_VECTOR'("11111110")); +MQQ95:GET_ADDRESS_PT(95) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(4) & + FISS_UC_IS2_INSTR_L2(5) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(27) & FISS_UC_IS2_INSTR_L2(28) + ) , STD_ULOGIC_VECTOR'("11111111")); +MQQ96:GET_ADDRESS_PT(96) <= + Eq(( FISS_UC_IS2_INSTR_L2(0) & FISS_UC_IS2_INSTR_L2(1) & + FISS_UC_IS2_INSTR_L2(2) & FISS_UC_IS2_INSTR_L2(4) & + FISS_UC_IS2_INSTR_L2(5) & FISS_UC_IS2_INSTR_L2(26) & + FISS_UC_IS2_INSTR_L2(28) & FISS_UC_IS2_INSTR_L2(29) + ) , STD_ULOGIC_VECTOR'("11111110")); +-- Table GET_ADDRESS Signal Assignments for Outputs +MQQ97:START_ADDR(0) <= + (GET_ADDRESS_PT(7) OR GET_ADDRESS_PT(17) + OR GET_ADDRESS_PT(18) OR GET_ADDRESS_PT(23) + OR GET_ADDRESS_PT(24) OR GET_ADDRESS_PT(37) + OR GET_ADDRESS_PT(38) OR GET_ADDRESS_PT(39) + OR GET_ADDRESS_PT(42) OR GET_ADDRESS_PT(43) + OR GET_ADDRESS_PT(46) OR GET_ADDRESS_PT(49) + OR GET_ADDRESS_PT(50) OR GET_ADDRESS_PT(52) + OR GET_ADDRESS_PT(53) OR GET_ADDRESS_PT(55) + OR GET_ADDRESS_PT(56) OR GET_ADDRESS_PT(57) + OR GET_ADDRESS_PT(58) OR GET_ADDRESS_PT(60) + OR GET_ADDRESS_PT(62) OR GET_ADDRESS_PT(63) + OR GET_ADDRESS_PT(64) OR GET_ADDRESS_PT(68) + OR GET_ADDRESS_PT(72) OR GET_ADDRESS_PT(76) + OR GET_ADDRESS_PT(77) OR GET_ADDRESS_PT(78) + OR GET_ADDRESS_PT(86) OR GET_ADDRESS_PT(87) + OR GET_ADDRESS_PT(88) OR GET_ADDRESS_PT(90) + OR GET_ADDRESS_PT(91) OR GET_ADDRESS_PT(93) + OR GET_ADDRESS_PT(94) OR GET_ADDRESS_PT(95) + OR GET_ADDRESS_PT(96)); +MQQ98:START_ADDR(1) <= + (GET_ADDRESS_PT(6) OR GET_ADDRESS_PT(7) + OR GET_ADDRESS_PT(10) OR GET_ADDRESS_PT(19) + OR GET_ADDRESS_PT(25) OR GET_ADDRESS_PT(27) + OR GET_ADDRESS_PT(31) OR GET_ADDRESS_PT(37) + OR GET_ADDRESS_PT(43) OR GET_ADDRESS_PT(46) + OR GET_ADDRESS_PT(49) OR GET_ADDRESS_PT(52) + OR GET_ADDRESS_PT(53) OR GET_ADDRESS_PT(55) + OR GET_ADDRESS_PT(57) OR GET_ADDRESS_PT(58) + OR GET_ADDRESS_PT(64) OR GET_ADDRESS_PT(72) + OR GET_ADDRESS_PT(76) OR GET_ADDRESS_PT(77) + OR GET_ADDRESS_PT(78) OR GET_ADDRESS_PT(88) + OR GET_ADDRESS_PT(91) OR GET_ADDRESS_PT(93) + OR GET_ADDRESS_PT(94) OR GET_ADDRESS_PT(95) + OR GET_ADDRESS_PT(96)); +MQQ99:START_ADDR(2) <= + (GET_ADDRESS_PT(6) OR GET_ADDRESS_PT(7) + OR GET_ADDRESS_PT(26) OR GET_ADDRESS_PT(30) + OR GET_ADDRESS_PT(35) OR GET_ADDRESS_PT(37) + OR GET_ADDRESS_PT(41) OR GET_ADDRESS_PT(43) + OR GET_ADDRESS_PT(44) OR GET_ADDRESS_PT(45) + OR GET_ADDRESS_PT(46) OR GET_ADDRESS_PT(50) + OR GET_ADDRESS_PT(52) OR GET_ADDRESS_PT(54) + OR GET_ADDRESS_PT(56) OR GET_ADDRESS_PT(64) + OR GET_ADDRESS_PT(72) OR GET_ADDRESS_PT(76) + OR GET_ADDRESS_PT(77) OR GET_ADDRESS_PT(78) + OR GET_ADDRESS_PT(79) OR GET_ADDRESS_PT(81) + OR GET_ADDRESS_PT(88) OR GET_ADDRESS_PT(94) + OR GET_ADDRESS_PT(95) OR GET_ADDRESS_PT(96) + ); +MQQ100:START_ADDR(3) <= + (GET_ADDRESS_PT(4) OR GET_ADDRESS_PT(8) + OR GET_ADDRESS_PT(9) OR GET_ADDRESS_PT(16) + OR GET_ADDRESS_PT(19) OR GET_ADDRESS_PT(20) + OR GET_ADDRESS_PT(26) OR GET_ADDRESS_PT(27) + OR GET_ADDRESS_PT(31) OR GET_ADDRESS_PT(34) + OR GET_ADDRESS_PT(38) OR GET_ADDRESS_PT(40) + OR GET_ADDRESS_PT(42) OR GET_ADDRESS_PT(49) + OR GET_ADDRESS_PT(50) OR GET_ADDRESS_PT(56) + OR GET_ADDRESS_PT(57) OR GET_ADDRESS_PT(59) + OR GET_ADDRESS_PT(69) OR GET_ADDRESS_PT(71) + OR GET_ADDRESS_PT(74) OR GET_ADDRESS_PT(85) + OR GET_ADDRESS_PT(87) OR GET_ADDRESS_PT(88) + OR GET_ADDRESS_PT(93)); +MQQ101:START_ADDR(4) <= + (GET_ADDRESS_PT(6) OR GET_ADDRESS_PT(7) + OR GET_ADDRESS_PT(8) OR GET_ADDRESS_PT(9) + OR GET_ADDRESS_PT(10) OR GET_ADDRESS_PT(18) + OR GET_ADDRESS_PT(19) OR GET_ADDRESS_PT(20) + OR GET_ADDRESS_PT(22) OR GET_ADDRESS_PT(28) + OR GET_ADDRESS_PT(31) OR GET_ADDRESS_PT(32) + OR GET_ADDRESS_PT(34) OR GET_ADDRESS_PT(35) + OR GET_ADDRESS_PT(37) OR GET_ADDRESS_PT(40) + OR GET_ADDRESS_PT(42) OR GET_ADDRESS_PT(43) + OR GET_ADDRESS_PT(44) OR GET_ADDRESS_PT(46) + OR GET_ADDRESS_PT(47) OR GET_ADDRESS_PT(49) + OR GET_ADDRESS_PT(50) OR GET_ADDRESS_PT(52) + OR GET_ADDRESS_PT(53) OR GET_ADDRESS_PT(54) + OR GET_ADDRESS_PT(55) OR GET_ADDRESS_PT(56) + OR GET_ADDRESS_PT(59) OR GET_ADDRESS_PT(60) + OR GET_ADDRESS_PT(61) OR GET_ADDRESS_PT(64) + OR GET_ADDRESS_PT(66) OR GET_ADDRESS_PT(72) + OR GET_ADDRESS_PT(75) OR GET_ADDRESS_PT(76) + OR GET_ADDRESS_PT(77) OR GET_ADDRESS_PT(78) + OR GET_ADDRESS_PT(81) OR GET_ADDRESS_PT(85) + OR GET_ADDRESS_PT(86) OR GET_ADDRESS_PT(94) + OR GET_ADDRESS_PT(95) OR GET_ADDRESS_PT(96) + ); +MQQ102:START_ADDR(5) <= + (GET_ADDRESS_PT(2) OR GET_ADDRESS_PT(3) + OR GET_ADDRESS_PT(5) OR GET_ADDRESS_PT(7) + OR GET_ADDRESS_PT(9) OR GET_ADDRESS_PT(14) + OR GET_ADDRESS_PT(17) OR GET_ADDRESS_PT(22) + OR GET_ADDRESS_PT(23) OR GET_ADDRESS_PT(24) + OR GET_ADDRESS_PT(27) OR GET_ADDRESS_PT(30) + OR GET_ADDRESS_PT(32) OR GET_ADDRESS_PT(34) + OR GET_ADDRESS_PT(37) OR GET_ADDRESS_PT(38) + OR GET_ADDRESS_PT(41) OR GET_ADDRESS_PT(43) + OR GET_ADDRESS_PT(45) OR GET_ADDRESS_PT(46) + OR GET_ADDRESS_PT(47) OR GET_ADDRESS_PT(52) + OR GET_ADDRESS_PT(55) OR GET_ADDRESS_PT(56) + OR GET_ADDRESS_PT(59) OR GET_ADDRESS_PT(64) + OR GET_ADDRESS_PT(65) OR GET_ADDRESS_PT(70) + OR GET_ADDRESS_PT(71) OR GET_ADDRESS_PT(72) + OR GET_ADDRESS_PT(73) OR GET_ADDRESS_PT(74) + OR GET_ADDRESS_PT(76) OR GET_ADDRESS_PT(77) + OR GET_ADDRESS_PT(78) OR GET_ADDRESS_PT(80) + OR GET_ADDRESS_PT(85) OR GET_ADDRESS_PT(87) + OR GET_ADDRESS_PT(89) OR GET_ADDRESS_PT(94) + OR GET_ADDRESS_PT(95) OR GET_ADDRESS_PT(96) + ); +MQQ103:START_ADDR(6) <= + (GET_ADDRESS_PT(2) OR GET_ADDRESS_PT(4) + OR GET_ADDRESS_PT(5) OR GET_ADDRESS_PT(7) + OR GET_ADDRESS_PT(12) OR GET_ADDRESS_PT(16) + OR GET_ADDRESS_PT(17) OR GET_ADDRESS_PT(21) + OR GET_ADDRESS_PT(23) OR GET_ADDRESS_PT(27) + OR GET_ADDRESS_PT(31) OR GET_ADDRESS_PT(33) + OR GET_ADDRESS_PT(35) OR GET_ADDRESS_PT(36) + OR GET_ADDRESS_PT(39) OR GET_ADDRESS_PT(43) + OR GET_ADDRESS_PT(44) OR GET_ADDRESS_PT(46) + OR GET_ADDRESS_PT(48) OR GET_ADDRESS_PT(50) + OR GET_ADDRESS_PT(52) OR GET_ADDRESS_PT(53) + OR GET_ADDRESS_PT(54) OR GET_ADDRESS_PT(58) + OR GET_ADDRESS_PT(59) OR GET_ADDRESS_PT(60) + OR GET_ADDRESS_PT(61) OR GET_ADDRESS_PT(62) + OR GET_ADDRESS_PT(64) OR GET_ADDRESS_PT(66) + OR GET_ADDRESS_PT(71) OR GET_ADDRESS_PT(72) + OR GET_ADDRESS_PT(74) OR GET_ADDRESS_PT(76) + OR GET_ADDRESS_PT(77) OR GET_ADDRESS_PT(78) + OR GET_ADDRESS_PT(79) OR GET_ADDRESS_PT(80) + OR GET_ADDRESS_PT(94) OR GET_ADDRESS_PT(95) + OR GET_ADDRESS_PT(96)); +MQQ104:START_ADDR(7) <= + (GET_ADDRESS_PT(2) OR GET_ADDRESS_PT(4) + OR GET_ADDRESS_PT(7) OR GET_ADDRESS_PT(8) + OR GET_ADDRESS_PT(9) OR GET_ADDRESS_PT(14) + OR GET_ADDRESS_PT(15) OR GET_ADDRESS_PT(16) + OR GET_ADDRESS_PT(17) OR GET_ADDRESS_PT(20) + OR GET_ADDRESS_PT(22) OR GET_ADDRESS_PT(30) + OR GET_ADDRESS_PT(32) OR GET_ADDRESS_PT(34) + OR GET_ADDRESS_PT(35) OR GET_ADDRESS_PT(37) + OR GET_ADDRESS_PT(38) OR GET_ADDRESS_PT(39) + OR GET_ADDRESS_PT(40) OR GET_ADDRESS_PT(41) + OR GET_ADDRESS_PT(42) OR GET_ADDRESS_PT(44) + OR GET_ADDRESS_PT(45) OR GET_ADDRESS_PT(47) + OR GET_ADDRESS_PT(51) OR GET_ADDRESS_PT(54) + OR GET_ADDRESS_PT(55) OR GET_ADDRESS_PT(59) + OR GET_ADDRESS_PT(68) OR GET_ADDRESS_PT(70) + OR GET_ADDRESS_PT(73) OR GET_ADDRESS_PT(85) + OR GET_ADDRESS_PT(86) OR GET_ADDRESS_PT(89) + ); +MQQ105:START_ADDR(8) <= + (GET_ADDRESS_PT(3) OR GET_ADDRESS_PT(15) + OR GET_ADDRESS_PT(21) OR GET_ADDRESS_PT(30) + OR GET_ADDRESS_PT(33) OR GET_ADDRESS_PT(36) + OR GET_ADDRESS_PT(41) OR GET_ADDRESS_PT(45) + OR GET_ADDRESS_PT(48) OR GET_ADDRESS_PT(49) + OR GET_ADDRESS_PT(55) OR GET_ADDRESS_PT(56) + OR GET_ADDRESS_PT(57) OR GET_ADDRESS_PT(59) + OR GET_ADDRESS_PT(63) OR GET_ADDRESS_PT(79) + OR GET_ADDRESS_PT(89) OR GET_ADDRESS_PT(91) + ); +MQQ106:START_ADDR(9) <= + (GET_ADDRESS_PT(3) OR GET_ADDRESS_PT(12) + OR GET_ADDRESS_PT(21) OR GET_ADDRESS_PT(33) + OR GET_ADDRESS_PT(35) OR GET_ADDRESS_PT(36) + OR GET_ADDRESS_PT(37) OR GET_ADDRESS_PT(44) + OR GET_ADDRESS_PT(48) OR GET_ADDRESS_PT(54) + OR GET_ADDRESS_PT(56) OR GET_ADDRESS_PT(59) + OR GET_ADDRESS_PT(80) OR GET_ADDRESS_PT(81) + ); +MQQ107:XER_TYPE <= + (GET_ADDRESS_PT(3) OR GET_ADDRESS_PT(42) + ); +MQQ108:LATE_END <= + (GET_ADDRESS_PT(4) OR GET_ADDRESS_PT(6) + OR GET_ADDRESS_PT(7) OR GET_ADDRESS_PT(8) + OR GET_ADDRESS_PT(10) OR GET_ADDRESS_PT(17) + OR GET_ADDRESS_PT(18) OR GET_ADDRESS_PT(19) + OR GET_ADDRESS_PT(21) OR GET_ADDRESS_PT(22) + OR GET_ADDRESS_PT(23) OR GET_ADDRESS_PT(24) + OR GET_ADDRESS_PT(25) OR GET_ADDRESS_PT(26) + OR GET_ADDRESS_PT(27) OR GET_ADDRESS_PT(29) + OR GET_ADDRESS_PT(31) OR GET_ADDRESS_PT(37) + OR GET_ADDRESS_PT(38) OR GET_ADDRESS_PT(39) + OR GET_ADDRESS_PT(41) OR GET_ADDRESS_PT(42) + OR GET_ADDRESS_PT(43) OR GET_ADDRESS_PT(44) + OR GET_ADDRESS_PT(46) OR GET_ADDRESS_PT(50) + OR GET_ADDRESS_PT(52) OR GET_ADDRESS_PT(55) + OR GET_ADDRESS_PT(56) OR GET_ADDRESS_PT(59) + OR GET_ADDRESS_PT(60) OR GET_ADDRESS_PT(64) + OR GET_ADDRESS_PT(67) OR GET_ADDRESS_PT(69) + OR GET_ADDRESS_PT(72) OR GET_ADDRESS_PT(76) + OR GET_ADDRESS_PT(77) OR GET_ADDRESS_PT(78) + OR GET_ADDRESS_PT(82) OR GET_ADDRESS_PT(83) + OR GET_ADDRESS_PT(84) OR GET_ADDRESS_PT(86) + OR GET_ADDRESS_PT(88) OR GET_ADDRESS_PT(90) + OR GET_ADDRESS_PT(94) OR GET_ADDRESS_PT(95) + OR GET_ADDRESS_PT(96)); +MQQ109:FORCE_EP <= + (GET_ADDRESS_PT(1) OR GET_ADDRESS_PT(11) + OR GET_ADDRESS_PT(13)); +MQQ110:UC_LEGAL <= + (GET_ADDRESS_PT(4) OR GET_ADDRESS_PT(6) + OR GET_ADDRESS_PT(7) OR GET_ADDRESS_PT(8) + OR GET_ADDRESS_PT(10) OR GET_ADDRESS_PT(16) + OR GET_ADDRESS_PT(17) OR GET_ADDRESS_PT(18) + OR GET_ADDRESS_PT(19) OR GET_ADDRESS_PT(20) + OR GET_ADDRESS_PT(21) OR GET_ADDRESS_PT(22) + OR GET_ADDRESS_PT(23) OR GET_ADDRESS_PT(24) + OR GET_ADDRESS_PT(25) OR GET_ADDRESS_PT(26) + OR GET_ADDRESS_PT(27) OR GET_ADDRESS_PT(30) + OR GET_ADDRESS_PT(31) OR GET_ADDRESS_PT(32) + OR GET_ADDRESS_PT(33) OR GET_ADDRESS_PT(35) + OR GET_ADDRESS_PT(36) OR GET_ADDRESS_PT(37) + OR GET_ADDRESS_PT(38) OR GET_ADDRESS_PT(39) + OR GET_ADDRESS_PT(40) OR GET_ADDRESS_PT(41) + OR GET_ADDRESS_PT(42) OR GET_ADDRESS_PT(43) + OR GET_ADDRESS_PT(44) OR GET_ADDRESS_PT(45) + OR GET_ADDRESS_PT(46) OR GET_ADDRESS_PT(47) + OR GET_ADDRESS_PT(48) OR GET_ADDRESS_PT(49) + OR GET_ADDRESS_PT(50) OR GET_ADDRESS_PT(52) + OR GET_ADDRESS_PT(53) OR GET_ADDRESS_PT(54) + OR GET_ADDRESS_PT(55) OR GET_ADDRESS_PT(56) + OR GET_ADDRESS_PT(57) OR GET_ADDRESS_PT(58) + OR GET_ADDRESS_PT(59) OR GET_ADDRESS_PT(60) + OR GET_ADDRESS_PT(62) OR GET_ADDRESS_PT(64) + OR GET_ADDRESS_PT(66) OR GET_ADDRESS_PT(69) + OR GET_ADDRESS_PT(71) OR GET_ADDRESS_PT(72) + OR GET_ADDRESS_PT(74) OR GET_ADDRESS_PT(76) + OR GET_ADDRESS_PT(77) OR GET_ADDRESS_PT(78) + OR GET_ADDRESS_PT(79) OR GET_ADDRESS_PT(81) + OR GET_ADDRESS_PT(84) OR GET_ADDRESS_PT(88) + OR GET_ADDRESS_PT(90) OR GET_ADDRESS_PT(91) + OR GET_ADDRESS_PT(92) OR GET_ADDRESS_PT(93) + OR GET_ADDRESS_PT(94) OR GET_ADDRESS_PT(95) + OR GET_ADDRESS_PT(96)); + +----------------------------------------------------------------------- +-- illegal op +----------------------------------------------------------------------- +iu_pc_err_ucode_illegal_d <= gate_and(fiss_uc_is2_ucode_vld_l2 and not uc_legal, fiss_uc_is2_tid_l2); +err_ucode_illegal: tri_direct_err_rpt + generic map (width => 4, expand_type => expand_type) + port map ( + vd => vdd, + gd => gnd, + err_in => iu_pc_err_ucode_illegal_L2, + err_out => iu_pc_err_ucode_illegal); +----------------------------------------------------------------------- +-- create instruction +----------------------------------------------------------------------- +xu_iu_flush_d <= xu_iu_flush; +xu_iu_ucode_restart_d <= xu_iu_ucode_restart; +xu_iu_uc_flush_ifar0_d <= xu_iu_uc_flush_ifar0; +xu_iu_uc_flush_ifar1_d <= xu_iu_uc_flush_ifar1; +xu_iu_uc_flush_ifar2_d <= xu_iu_uc_flush_ifar2; +xu_iu_uc_flush_ifar3_d <= xu_iu_uc_flush_ifar3; +uc_control0 : entity work.iuq_uc_control + generic map( ucode_width => ucode_width, + expand_type => expand_type) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_iu_func_sl_thold_0_b => pc_iu_func_sl_thold_0_b, + pc_iu_sg_0 => pc_iu_sg_0, + forcee => forcee, + d_mode => d_mode, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + scan_in => siv(scan_right + 1), + scan_out => sov(scan_right + 1), + spr_ic_clockgate_dis => spr_ic_clockgate_dis, + xu_iu_spr_xer => xu_iu_spr_xer0, + flush => xu_iu_flush_l2(0), + restart => xu_iu_ucode_restart_l2(0), + flush_ifar => xu_iu_uc_flush_ifar0_l2, + ib_flush => ib_flush(0), + ib_flush_ifar => iu5_ifar_l2, + buff_avail => ib_uc_buff0_avail, + load_command => load_command(0), + new_instr => fiss_uc_is2_instr_l2, + start_addr => start_addr, + xer_type => xer_type, + early_end => early_end, + force_ep => force_ep, + new_cond => new_cond, + uc_act_thread => uc_act(0), + vld_fast => vld_fast(0), + ra_valid => vld_mask(0), + rom_ra => rom_ra0, + data_valid => data_valid(0), + rom_data => rom_data(32 to ucode_width-1), + rom_data_late => rom_data_late_l2(0 to 31), + ucode_valid => ucode_valid(0), + ucode_ifar => ucode_ifar0, + ucode_instruction => ucode_instr0, + is_ucode => ucode_is_ucode0, + extRT => ucode_ext0(0), + extS1 => ucode_ext0(1), + extS2 => ucode_ext0(2), + extS3 => ucode_ext0(3), + hold_thread => uc_ic_hold_thread(0), + uc_control_dbg_data => uc_control_dbg_data0 +); +uc_control1 : entity work.iuq_uc_control + generic map( ucode_width => ucode_width, + expand_type => expand_type) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_iu_func_sl_thold_0_b => pc_iu_func_sl_thold_0_b, + pc_iu_sg_0 => pc_iu_sg_0, + forcee => forcee, + d_mode => d_mode, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + scan_in => siv(scan_right + 2), + scan_out => sov(scan_right + 2), + spr_ic_clockgate_dis => spr_ic_clockgate_dis, + xu_iu_spr_xer => xu_iu_spr_xer1, + flush => xu_iu_flush_l2(1), + restart => xu_iu_ucode_restart_l2(1), + flush_ifar => xu_iu_uc_flush_ifar1_l2, + ib_flush => ib_flush(1), + ib_flush_ifar => iu5_ifar_l2, + buff_avail => ib_uc_buff1_avail, + load_command => load_command(1), + new_instr => fiss_uc_is2_instr_l2, + start_addr => start_addr, + xer_type => xer_type, + early_end => early_end, + force_ep => force_ep, + new_cond => new_cond, + uc_act_thread => uc_act(1), + vld_fast => vld_fast(1), + ra_valid => vld_mask(1), + rom_ra => rom_ra1, + data_valid => data_valid(1), + rom_data => rom_data(32 to ucode_width-1), + rom_data_late => rom_data_late_l2(0 to 31), + ucode_valid => ucode_valid(1), + ucode_ifar => ucode_ifar1, + ucode_instruction => ucode_instr1, + is_ucode => ucode_is_ucode1, + extRT => ucode_ext1(0), + extS1 => ucode_ext1(1), + extS2 => ucode_ext1(2), + extS3 => ucode_ext1(3), + hold_thread => uc_ic_hold_thread(1), + uc_control_dbg_data => uc_control_dbg_data1 +); +uc_control2 : entity work.iuq_uc_control + generic map( ucode_width => ucode_width, + expand_type => expand_type) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_iu_func_sl_thold_0_b => pc_iu_func_sl_thold_0_b, + pc_iu_sg_0 => pc_iu_sg_0, + forcee => forcee, + d_mode => d_mode, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + scan_in => siv(scan_right + 3), + scan_out => sov(scan_right + 3), + spr_ic_clockgate_dis => spr_ic_clockgate_dis, + xu_iu_spr_xer => xu_iu_spr_xer2, + flush => xu_iu_flush_l2(2), + restart => xu_iu_ucode_restart_l2(2), + flush_ifar => xu_iu_uc_flush_ifar2_l2, + ib_flush => ib_flush(2), + ib_flush_ifar => iu5_ifar_l2, + buff_avail => ib_uc_buff2_avail, + load_command => load_command(2), + new_instr => fiss_uc_is2_instr_l2, + start_addr => start_addr, + xer_type => xer_type, + early_end => early_end, + force_ep => force_ep, + new_cond => new_cond, + uc_act_thread => uc_act(2), + vld_fast => vld_fast(2), + ra_valid => vld_mask(2), + rom_ra => rom_ra2, + data_valid => data_valid(2), + rom_data => rom_data(32 to ucode_width-1), + rom_data_late => rom_data_late_l2(0 to 31), + ucode_valid => ucode_valid(2), + ucode_ifar => ucode_ifar2, + ucode_instruction => ucode_instr2, + is_ucode => ucode_is_ucode2, + extRT => ucode_ext2(0), + extS1 => ucode_ext2(1), + extS2 => ucode_ext2(2), + extS3 => ucode_ext2(3), + hold_thread => uc_ic_hold_thread(2), + uc_control_dbg_data => uc_control_dbg_data2 +); +uc_control3 : entity work.iuq_uc_control + generic map( ucode_width => ucode_width, + expand_type => expand_type) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_iu_func_sl_thold_0_b => pc_iu_func_sl_thold_0_b, + pc_iu_sg_0 => pc_iu_sg_0, + forcee => forcee, + d_mode => d_mode, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + scan_in => siv(scan_right + 4), + scan_out => sov(scan_right + 4), + spr_ic_clockgate_dis => spr_ic_clockgate_dis, + xu_iu_spr_xer => xu_iu_spr_xer3, + flush => xu_iu_flush_l2(3), + restart => xu_iu_ucode_restart_l2(3), + flush_ifar => xu_iu_uc_flush_ifar3_l2, + ib_flush => ib_flush(3), + ib_flush_ifar => iu5_ifar_l2, + buff_avail => ib_uc_buff3_avail, + load_command => load_command(3), + new_instr => fiss_uc_is2_instr_l2, + start_addr => start_addr, + xer_type => xer_type, + early_end => early_end, + force_ep => force_ep, + new_cond => new_cond, + uc_act_thread => uc_act(3), + vld_fast => vld_fast(3), + ra_valid => vld_mask(3), + rom_ra => rom_ra3, + data_valid => data_valid(3), + rom_data => rom_data(32 to ucode_width-1), + rom_data_late => rom_data_late_l2(0 to 31), + ucode_valid => ucode_valid(3), + ucode_ifar => ucode_ifar3, + ucode_instruction => ucode_instr3, + is_ucode => ucode_is_ucode3, + extRT => ucode_ext3(0), + extS1 => ucode_ext3(1), + extS2 => ucode_ext3(2), + extS3 => ucode_ext3(3), + hold_thread => uc_ic_hold_thread(3), + uc_control_dbg_data => uc_control_dbg_data3 +); +----------------------------------------------------------------------- +-- ROM Priority +----------------------------------------------------------------------- +-- ?TABLE rom_issue_table LISTING(final) OPTIMIZE PARMS(ON-SET, OFF-SET); +-- *INPUTS*=====++===========*OUTPUTS*==========* +-- | | | +-- | romtoken_L2 | | +-- | | vld_mask | romtoken_d | +-- | | | | | | +-- | | | | | | +-- | | | | | | +-- | | | | | | +-- | | | | | | +-- | 01 0123 | 01 | +-- *TYPE*=====++=============+==================+ +-- | SS SSSS | SS | +-- *TERMS*==++===============+==================+ +-- | 00 0000 | 00 | +-- | 00 .001 | 11 | +-- | 00 .01. | 10 | +-- | 00 .1.. | 01 | +-- | 00 1000 | 00 | +-- | | | +-- | 01 0000 | 01 | +-- | 01 ..01 | 11 | +-- | 01 ..1. | 10 | +-- | 01 0100 | 01 | +-- | 01 1.00 | 00 | +-- | | | +-- | 10 0000 | 10 | +-- | 10 ...1 | 11 | +-- | 10 0010 | 10 | +-- | 10 01.0 | 01 | +-- | 10 1..0 | 00 | +-- | | | +-- | 11 0000 | 11 | +-- | 11 0001 | 11 | +-- | 11 001. | 10 | +-- | 11 01.. | 01 | +-- | 11 1... | 00 | +-- | | | +-- *END*=====================+==================+ +-- ?TABLE END rom_issue_table; +-- +-- Final Table Listing +-- *INPUTS*====================*OUTPUTS*==========* +-- | | | +-- | romtoken_L2 | | +-- | | vld_fast | romtoken_d | +-- | | | | | | +-- | | | | | | +-- | | | | | | +-- | | | | | | +-- | | | | | | +-- | 0123 0123 | 0123 | +-- *TYPE*======================+==================+ +-- | SSSS SSSS | SSSS | +-- *POLARITY*----------------->| ++++ | +-- *PHASE*-------------------->| TTTT | +-- *TERMS*=====================+==================+ +-- 1 | ---1 01-- | .1.. | +-- 2 | --1- 1--0 | 1... | +-- 3 | --00 -01- | ..1. | +-- 4 | -1-- 0-00 | .1.. | +-- 5 | 1--- -001 | ...1 | +-- 6 | --1- 00-0 | ..1. | +-- 7 | ---1 000- | ...1 | +-- 8 | 1--- -000 | 1... | +-- 9 | -1-- --01 | ...1 | +-- 10 | 0--- 1-00 | 1... | +-- 11 | -0-- 01-0 | .1.. | +-- 12 | --0- 001- | ..1. | +-- 13 | -1-- --1- | ..1. | +-- 14 | ---1 1--- | 1... | +-- 15 | 1--- -1-- | .1.. | +-- 16 | --1- ---1 | ...1 | +-- *==============================================* +-- +-- Table ROM_ISSUE_TABLE Signal Assignments for Product Terms +MQQ111:ROM_ISSUE_TABLE_PT(1) <= + Eq(( ROMTOKEN_L2(3) & VLD_FAST(0) & + VLD_FAST(1) ) , STD_ULOGIC_VECTOR'("101")); +MQQ112:ROM_ISSUE_TABLE_PT(2) <= + Eq(( ROMTOKEN_L2(2) & VLD_FAST(0) & + VLD_FAST(3) ) , STD_ULOGIC_VECTOR'("110")); +MQQ113:ROM_ISSUE_TABLE_PT(3) <= + Eq(( ROMTOKEN_L2(2) & ROMTOKEN_L2(3) & + VLD_FAST(1) & VLD_FAST(2) + ) , STD_ULOGIC_VECTOR'("0001")); +MQQ114:ROM_ISSUE_TABLE_PT(4) <= + Eq(( ROMTOKEN_L2(1) & VLD_FAST(0) & + VLD_FAST(2) & VLD_FAST(3) + ) , STD_ULOGIC_VECTOR'("1000")); +MQQ115:ROM_ISSUE_TABLE_PT(5) <= + Eq(( ROMTOKEN_L2(0) & VLD_FAST(1) & + VLD_FAST(2) & VLD_FAST(3) + ) , STD_ULOGIC_VECTOR'("1001")); +MQQ116:ROM_ISSUE_TABLE_PT(6) <= + Eq(( ROMTOKEN_L2(2) & VLD_FAST(0) & + VLD_FAST(1) & VLD_FAST(3) + ) , STD_ULOGIC_VECTOR'("1000")); +MQQ117:ROM_ISSUE_TABLE_PT(7) <= + Eq(( ROMTOKEN_L2(3) & VLD_FAST(0) & + VLD_FAST(1) & VLD_FAST(2) + ) , STD_ULOGIC_VECTOR'("1000")); +MQQ118:ROM_ISSUE_TABLE_PT(8) <= + Eq(( ROMTOKEN_L2(0) & VLD_FAST(1) & + VLD_FAST(2) & VLD_FAST(3) + ) , STD_ULOGIC_VECTOR'("1000")); +MQQ119:ROM_ISSUE_TABLE_PT(9) <= + Eq(( ROMTOKEN_L2(1) & VLD_FAST(2) & + VLD_FAST(3) ) , STD_ULOGIC_VECTOR'("101")); +MQQ120:ROM_ISSUE_TABLE_PT(10) <= + Eq(( ROMTOKEN_L2(0) & VLD_FAST(0) & + VLD_FAST(2) & VLD_FAST(3) + ) , STD_ULOGIC_VECTOR'("0100")); +MQQ121:ROM_ISSUE_TABLE_PT(11) <= + Eq(( ROMTOKEN_L2(1) & VLD_FAST(0) & + VLD_FAST(1) & VLD_FAST(3) + ) , STD_ULOGIC_VECTOR'("0010")); +MQQ122:ROM_ISSUE_TABLE_PT(12) <= + Eq(( ROMTOKEN_L2(2) & VLD_FAST(0) & + VLD_FAST(1) & VLD_FAST(2) + ) , STD_ULOGIC_VECTOR'("0001")); +MQQ123:ROM_ISSUE_TABLE_PT(13) <= + Eq(( ROMTOKEN_L2(1) & VLD_FAST(2) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ124:ROM_ISSUE_TABLE_PT(14) <= + Eq(( ROMTOKEN_L2(3) & VLD_FAST(0) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ125:ROM_ISSUE_TABLE_PT(15) <= + Eq(( ROMTOKEN_L2(0) & VLD_FAST(1) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ126:ROM_ISSUE_TABLE_PT(16) <= + Eq(( ROMTOKEN_L2(2) & VLD_FAST(3) + ) , STD_ULOGIC_VECTOR'("11")); +-- Table ROM_ISSUE_TABLE Signal Assignments for Outputs +MQQ127:ROMTOKEN_D(0) <= + (ROM_ISSUE_TABLE_PT(2) OR ROM_ISSUE_TABLE_PT(8) + OR ROM_ISSUE_TABLE_PT(10) OR ROM_ISSUE_TABLE_PT(14) + ); +MQQ128:ROMTOKEN_D(1) <= + (ROM_ISSUE_TABLE_PT(1) OR ROM_ISSUE_TABLE_PT(4) + OR ROM_ISSUE_TABLE_PT(11) OR ROM_ISSUE_TABLE_PT(15) + ); +MQQ129:ROMTOKEN_D(2) <= + (ROM_ISSUE_TABLE_PT(3) OR ROM_ISSUE_TABLE_PT(6) + OR ROM_ISSUE_TABLE_PT(12) OR ROM_ISSUE_TABLE_PT(13) + ); +MQQ130:ROMTOKEN_D(3) <= + (ROM_ISSUE_TABLE_PT(5) OR ROM_ISSUE_TABLE_PT(7) + OR ROM_ISSUE_TABLE_PT(9) OR ROM_ISSUE_TABLE_PT(16) + ); + +romvalid_d <= vld_mask; +rom_addr <= gate_and(romtoken_d(0), rom_ra0) or + gate_and(romtoken_d(1), rom_ra1) or + gate_and(romtoken_d(2), rom_ra2) or + gate_and(romtoken_d(3), rom_ra3) ; +uc_any_act <= or_reduce(uc_act); +rom_act <= uc_any_act; +rom_data_tid <= romtoken_L2; +data_valid <= romvalid_l2 and rom_data_tid; +----------------------------------------------------------------------- +-- ROM Lookup +----------------------------------------------------------------------- +uc_rom: entity work.iuq_uc_rom + generic map( ucode_width => ucode_width, + regmode => regmode, + expand_type => expand_type) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_iu_func_sl_thold_0_b => pc_iu_func_sl_thold_0_b, + pc_iu_sg_0 => pc_iu_sg_0, + forcee => forcee, + d_mode => d_mode, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + scan_in => siv(scan_right + 5), + scan_out => sov(scan_right + 5), + rom_act => rom_act, + rom_addr => rom_addr, + rom_data => rom_data +); +rom_data_late_d <= rom_data(0 to 31); +----------------------------------------------------------------------- +-- Staging latches +----------------------------------------------------------------------- +iu4_stage_act <= or_reduce(data_valid); +iu4_valid_tid_d <= ucode_valid and not xu_iu_flush_d; +iu4_is_ucode_d <= gate_and(rom_data_tid(0), ucode_is_ucode0) or + gate_and(rom_data_tid(1), ucode_is_ucode1) or + gate_and(rom_data_tid(2), ucode_is_ucode2) or + gate_and(rom_data_tid(3), ucode_is_ucode3) ; +iu4_ifar_d <= gate_and(rom_data_tid(0), ucode_ifar0) or + gate_and(rom_data_tid(1), ucode_ifar1) or + gate_and(rom_data_tid(2), ucode_ifar2) or + gate_and(rom_data_tid(3), ucode_ifar3) ; +iu4_ext_d <= gate_and(rom_data_tid(0), ucode_ext0) or + gate_and(rom_data_tid(1), ucode_ext1) or + gate_and(rom_data_tid(2), ucode_ext2) or + gate_and(rom_data_tid(3), ucode_ext3) ; +--late data +iu4_data_tid_d <= rom_data_tid; +iu4_instr_l2 <= gate_and(iu4_data_tid_l2(0), ucode_instr0) or + gate_and(iu4_data_tid_l2(1), ucode_instr1) or + gate_and(iu4_data_tid_l2(2), ucode_instr2) or + gate_and(iu4_data_tid_l2(3), ucode_instr3) ; +uc_ib_iu4_valid_tid <= iu4_valid_tid_l2; +uc_ib_iu4_ifar <= iu4_ifar_l2; +uc_ib_iu4_instr <= iu4_instr_l2; +uc_ib_iu4_is_ucode <= iu4_is_ucode_l2; +uc_ib_iu4_ext <= iu4_ext_l2; +----------------------------------------------------------------------- +-- IB Buffer Flush +----------------------------------------------------------------------- +-- Only need to flush if ucode uses more ifar bits than kept in each buffer +ib_flush <= "0000"; +iu5_ifar_l2 <= (others => '0'); +sov(iu5_valid_tid_offset TO iu5_valid_tid_offset+4-1) <= + siv(iu5_valid_tid_offset to iu5_valid_tid_offset + 4 - 1); +sov(iu5_ifar_offset TO iu5_ifar_offset+iu5_ifar_l2'length-1) <= + siv(iu5_ifar_offset to iu5_ifar_offset + iu5_ifar_l2'length-1); +----------------------------------------------------------------------- +-- Debug +----------------------------------------------------------------------- +ib_uc_buff_avail_d <= ib_uc_buff0_avail & ib_uc_buff1_avail & ib_uc_buff2_avail & ib_uc_buff3_avail; +uc_dbg_data(0 TO 3) <= uc_control_dbg_data0; +uc_dbg_data(4 TO 7) <= uc_control_dbg_data1; +uc_dbg_data(8 TO 11) <= uc_control_dbg_data2; +uc_dbg_data(12 TO 15) <= uc_control_dbg_data3; +uc_dbg_data(16 TO 19) <= xu_iu_flush_l2; +uc_dbg_data(20 TO 23) <= ib_uc_buff_avail_l2; +uc_dbg_data(24) <= fiss_uc_is2_ucode_vld_l2; +uc_dbg_data(25) <= fiss_uc_is2_2ucode_l2; +uc_dbg_data(26) <= fiss_uc_is2_2ucode_type_l2; +uc_dbg_data(27 TO 43) <= fiss_uc_is2_instr_l2(0 to 5) & fiss_uc_is2_instr_l2(21 to 31); +uc_dbg_data_d(44 TO 59) <= iu4_instr_l2(0 to 15); +uc_dbg_data(44 TO 59) <= uc_dbg_data_l2(44 to 59); +uc_dbg_data(60 TO 63) <= iu4_ext_l2; +uc_dbg_data(64 TO 65) <= iu4_ifar_l2(41 to 42); +uc_dbg_data(66 TO 73) <= iu4_ifar_l2(54 to 61); +uc_dbg_data(74) <= iu4_ifar_l2(48); +uc_dbg_data(75 TO 79) <= iu4_ifar_l2(43 to 47); +uc_dbg_data(80 TO 83) <= iu4_valid_tid_l2; +uc_dbg_data(84 TO 87) <= romtoken_l2; +----------------------------------------------------------------------- +-- Latches +----------------------------------------------------------------------- +iu_pc_err_ucode_illegal_0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => uc_act(0), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu_pc_err_ucode_illegal_offset + 0), + scout => sov(iu_pc_err_ucode_illegal_offset + 0), + din => iu_pc_err_ucode_illegal_d(0), + dout => iu_pc_err_ucode_illegal_l2(0)); +iu_pc_err_ucode_illegal_1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => uc_act(1), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu_pc_err_ucode_illegal_offset + 1), + scout => sov(iu_pc_err_ucode_illegal_offset + 1), + din => iu_pc_err_ucode_illegal_d(1), + dout => iu_pc_err_ucode_illegal_l2(1)); +iu_pc_err_ucode_illegal_2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => uc_act(2), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu_pc_err_ucode_illegal_offset + 2), + scout => sov(iu_pc_err_ucode_illegal_offset + 2), + din => iu_pc_err_ucode_illegal_d(2), + dout => iu_pc_err_ucode_illegal_l2(2)); +iu_pc_err_ucode_illegal_3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => uc_act(3), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu_pc_err_ucode_illegal_offset + 3), + scout => sov(iu_pc_err_ucode_illegal_offset + 3), + din => iu_pc_err_ucode_illegal_d(3), + dout => iu_pc_err_ucode_illegal_l2(3)); +-- For Debug only +ib_uc_buff_avail_latch: tri_rlmreg_p + generic map (width => ib_uc_buff_avail_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => trace_bus_enable_q, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(ib_uc_buff_avail_offset to ib_uc_buff_avail_offset + ib_uc_buff_avail_l2'length-1), + scout => sov(ib_uc_buff_avail_offset to ib_uc_buff_avail_offset + ib_uc_buff_avail_l2'length-1), + din => ib_uc_buff_avail_d, + dout => ib_uc_buff_avail_l2); +xu_iu_flush_latch: tri_rlmreg_p + generic map (width => xu_iu_flush_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_iu_flush_offset to xu_iu_flush_offset + xu_iu_flush_l2'length-1), + scout => sov(xu_iu_flush_offset to xu_iu_flush_offset + xu_iu_flush_l2'length-1), + din => xu_iu_flush_d, + dout => xu_iu_flush_l2); +xu_iu_ucode_restart_latch: tri_rlmreg_p + generic map (width => xu_iu_ucode_restart_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_iu_ucode_restart_offset to xu_iu_ucode_restart_offset + xu_iu_ucode_restart_l2'length-1), + scout => sov(xu_iu_ucode_restart_offset to xu_iu_ucode_restart_offset + xu_iu_ucode_restart_l2'length-1), + din => xu_iu_ucode_restart_d, + dout => xu_iu_ucode_restart_l2); +xu_iu_uc_flush_ifar0_latch: tri_rlmreg_p + generic map (width => xu_iu_uc_flush_ifar0_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => uc_act(0), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_iu_uc_flush_ifar0_offset to xu_iu_uc_flush_ifar0_offset + xu_iu_uc_flush_ifar0_l2'length-1), + scout => sov(xu_iu_uc_flush_ifar0_offset to xu_iu_uc_flush_ifar0_offset + xu_iu_uc_flush_ifar0_l2'length-1), + din => xu_iu_uc_flush_ifar0_d, + dout => xu_iu_uc_flush_ifar0_l2); +xu_iu_uc_flush_ifar1_latch: tri_rlmreg_p + generic map (width => xu_iu_uc_flush_ifar1_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => uc_act(1), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_iu_uc_flush_ifar1_offset to xu_iu_uc_flush_ifar1_offset + xu_iu_uc_flush_ifar1_l2'length-1), + scout => sov(xu_iu_uc_flush_ifar1_offset to xu_iu_uc_flush_ifar1_offset + xu_iu_uc_flush_ifar1_l2'length-1), + din => xu_iu_uc_flush_ifar1_d, + dout => xu_iu_uc_flush_ifar1_l2); +xu_iu_uc_flush_ifar2_latch: tri_rlmreg_p + generic map (width => xu_iu_uc_flush_ifar2_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => uc_act(2), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_iu_uc_flush_ifar2_offset to xu_iu_uc_flush_ifar2_offset + xu_iu_uc_flush_ifar2_l2'length-1), + scout => sov(xu_iu_uc_flush_ifar2_offset to xu_iu_uc_flush_ifar2_offset + xu_iu_uc_flush_ifar2_l2'length-1), + din => xu_iu_uc_flush_ifar2_d, + dout => xu_iu_uc_flush_ifar2_l2); +xu_iu_uc_flush_ifar3_latch: tri_rlmreg_p + generic map (width => xu_iu_uc_flush_ifar3_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => uc_act(3), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_iu_uc_flush_ifar3_offset to xu_iu_uc_flush_ifar3_offset + xu_iu_uc_flush_ifar3_l2'length-1), + scout => sov(xu_iu_uc_flush_ifar3_offset to xu_iu_uc_flush_ifar3_offset + xu_iu_uc_flush_ifar3_l2'length-1), + din => xu_iu_uc_flush_ifar3_d, + dout => xu_iu_uc_flush_ifar3_l2); +-- Input staging latches +fiss_uc_is2_ucode_vld_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(fiss_uc_is2_ucode_vld_offset), + scout => sov(fiss_uc_is2_ucode_vld_offset), + din => fiss_uc_is2_ucode_vld_d, + dout => fiss_uc_is2_ucode_vld_l2); +fiss_uc_is2_tid_latch: tri_rlmreg_p + generic map (width => fiss_uc_is2_tid_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(fiss_uc_is2_tid_offset to fiss_uc_is2_tid_offset + fiss_uc_is2_tid_l2'length-1), + scout => sov(fiss_uc_is2_tid_offset to fiss_uc_is2_tid_offset + fiss_uc_is2_tid_l2'length-1), + din => fiss_uc_is2_tid_d, + dout => fiss_uc_is2_tid_l2); +fiss_uc_is2_instr_latch: tri_rlmreg_p + generic map (width => fiss_uc_is2_instr_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(fiss_uc_is2_instr_offset to fiss_uc_is2_instr_offset + fiss_uc_is2_instr_l2'length-1), + scout => sov(fiss_uc_is2_instr_offset to fiss_uc_is2_instr_offset + fiss_uc_is2_instr_l2'length-1), + din => fiss_uc_is2_instr_d, + dout => fiss_uc_is2_instr_l2); +fiss_uc_is2_2ucode_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(fiss_uc_is2_2ucode_offset), + scout => sov(fiss_uc_is2_2ucode_offset), + din => fiss_uc_is2_2ucode_d, + dout => fiss_uc_is2_2ucode_l2); +fiss_uc_is2_2ucode_type_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(fiss_uc_is2_2ucode_type_offset), + scout => sov(fiss_uc_is2_2ucode_type_offset), + din => fiss_uc_is2_2ucode_type_d, + dout => fiss_uc_is2_2ucode_type_l2); +-- ROM priority +romtoken_latch: tri_rlmreg_p + generic map (width => romtoken_l2'length, init => 8, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => uc_any_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(romtoken_offset to romtoken_offset + romtoken_l2'length-1), + scout => sov(romtoken_offset to romtoken_offset + romtoken_l2'length-1), + din => romtoken_d, + dout => romtoken_l2); +romvalid_latch: tri_rlmreg_p + generic map (width => romvalid_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => uc_any_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(romvalid_offset to romvalid_offset + romvalid_l2'length-1), + scout => sov(romvalid_offset to romvalid_offset + romvalid_l2'length-1), + din => romvalid_d, + dout => romvalid_l2); +rom_data_late_latch: tri_rlmreg_p + generic map (width => rom_data_late_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu4_stage_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(rom_data_late_offset to rom_data_late_offset + rom_data_late_l2'length-1), + scout => sov(rom_data_late_offset to rom_data_late_offset + rom_data_late_l2'length-1), + din => rom_data_late_d, + dout => rom_data_late_l2); +-- Staging latches +iu4_valid_tid_0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => uc_act(0), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu4_valid_tid_offset+0), + scout => sov(iu4_valid_tid_offset+0), + din => iu4_valid_tid_d(0), + dout => iu4_valid_tid_l2(0)); +iu4_valid_tid_1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => uc_act(1), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu4_valid_tid_offset+1), + scout => sov(iu4_valid_tid_offset+1), + din => iu4_valid_tid_d(1), + dout => iu4_valid_tid_l2(1)); +iu4_valid_tid_2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => uc_act(2), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu4_valid_tid_offset+2), + scout => sov(iu4_valid_tid_offset+2), + din => iu4_valid_tid_d(2), + dout => iu4_valid_tid_l2(2)); +iu4_valid_tid_3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => uc_act(3), + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu4_valid_tid_offset+3), + scout => sov(iu4_valid_tid_offset+3), + din => iu4_valid_tid_d(3), + dout => iu4_valid_tid_l2(3)); +iu4_data_tid_latch: tri_rlmreg_p + generic map (width => iu4_data_tid_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu4_stage_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu4_data_tid_offset to iu4_data_tid_offset + iu4_data_tid_l2'length-1), + scout => sov(iu4_data_tid_offset to iu4_data_tid_offset + iu4_data_tid_l2'length-1), + din => iu4_data_tid_d, + dout => iu4_data_tid_l2); +iu4_ifar_latch: tri_rlmreg_p + generic map (width => iu4_ifar_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu4_stage_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu4_ifar_offset to iu4_ifar_offset + iu4_ifar_l2'length-1), + scout => sov(iu4_ifar_offset to iu4_ifar_offset + iu4_ifar_l2'length-1), + din => iu4_ifar_d, + dout => iu4_ifar_l2); +iu4_is_ucode_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu4_stage_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu4_is_ucode_offset), + scout => sov(iu4_is_ucode_offset), + din => iu4_is_ucode_d, + dout => iu4_is_ucode_l2); +iu4_ext_latch: tri_rlmreg_p + generic map (width => iu4_ext_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iu4_stage_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(iu4_ext_offset to iu4_ext_offset + iu4_ext_l2'length-1), + scout => sov(iu4_ext_offset to iu4_ext_offset + iu4_ext_l2'length-1), + din => iu4_ext_d, + dout => iu4_ext_l2); +trace_bus_enable_d <= pc_iu_trace_bus_enable; +trace_enable_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(trace_bus_enable_offset), + scout => sov(trace_bus_enable_offset), + din => trace_bus_enable_d, + dout => trace_bus_enable_q); +uc_dbg_data_latch: tri_rlmreg_p + generic map (width => uc_dbg_data_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => trace_bus_enable_q, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(uc_dbg_data_offset to uc_dbg_data_offset + uc_dbg_data_l2'length-1), + scout => sov(uc_dbg_data_offset to uc_dbg_data_offset + uc_dbg_data_l2'length-1), + din => uc_dbg_data_d, + dout => uc_dbg_data_l2); +spare_latch: tri_rlmreg_p + generic map (width => spare_l2'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(spare_offset to spare_offset + spare_l2'length-1), + scout => sov(spare_offset to spare_offset + spare_l2'length-1), + din => spare_l2, + dout => spare_l2); +----------------------------------------------------------------------- +-- pervasive thold/sg latches +----------------------------------------------------------------------- +perv_2to1_reg: tri_plat + generic map (width => 2, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_iu_func_sl_thold_2, + din(1) => pc_iu_sg_2, + q(0) => pc_iu_func_sl_thold_1, + q(1) => pc_iu_sg_1); +perv_1to0_reg: tri_plat + generic map (width => 2, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_iu_func_sl_thold_1, + din(1) => pc_iu_sg_1, + q(0) => pc_iu_func_sl_thold_0, + q(1) => pc_iu_sg_0); +perv_lcbor: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_b, + thold => pc_iu_func_sl_thold_0, + sg => pc_iu_sg_0, + act_dis => act_dis, + forcee => forcee, + thold_b => pc_iu_func_sl_thold_0_b); +----------------------------------------------------------------------- +-- Scan +----------------------------------------------------------------------- +siv(0 TO scan_right+5) <= sov(1 to scan_right+5) & scan_in; +scan_out <= sov(0) and an_ac_scan_dis_dc_b; +END IUQ_UC; diff --git a/rel/src/vhdl/work/iuq_uc_control.vhdl b/rel/src/vhdl/work/iuq_uc_control.vhdl new file mode 100644 index 0000000..f215275 --- /dev/null +++ b/rel/src/vhdl/work/iuq_uc_control.vhdl @@ -0,0 +1,831 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +--******************************************************************** +--* +--* TITLE: Microcode Control +--* +--* NAME: iuq_uc_control.vhdl +--* +--********************************************************************* + +library ieee,ibm,support,tri,work; +use ieee.std_logic_1164.all; +use ibm.std_ulogic_unsigned.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use support.power_logic_pkg.all; +use tri.tri_latches_pkg.all; +use work.iuq_pkg.all; + + +entity iuq_uc_control is + generic(ucode_width : integer := 71; + expand_type : integer := 2); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + pc_iu_func_sl_thold_0_b : in std_ulogic; + pc_iu_sg_0 : in std_ulogic; + forcee : in std_ulogic; + d_mode : in std_ulogic; + delay_lclkr : in std_ulogic; + mpw1_b : in std_ulogic; + mpw2_b : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + spr_ic_clockgate_dis : in std_ulogic; + xu_iu_spr_xer : in std_ulogic_vector(57 to 63); + flush : in std_ulogic; + restart : in std_ulogic; + flush_ifar : in std_ulogic_vector(41 to 61); -- ucode-style address & state to flush to + ib_flush : in std_ulogic; + ib_flush_ifar : in std_ulogic_vector(41 to 61); -- ucode-style address & state to flush to + buff_avail : in std_ulogic; + load_command : in std_ulogic; + new_instr : in std_ulogic_vector(0 to 31); + start_addr : in std_ulogic_vector(0 to 9); + xer_type : in std_ulogic; -- instruction uses XER: need to wait until XER guaranteed valid + early_end : in std_ulogic; + force_ep : in std_ulogic; + new_cond : in std_ulogic; -- If '1', will skip lines with skip_cond bit set + + uc_act_thread : out std_ulogic; + vld_fast : out std_ulogic; + + ra_valid : out std_ulogic; + rom_ra : out std_ulogic_vector(0 to 9); -- read address + + data_valid : in std_ulogic; + rom_data : in std_ulogic_vector(32 to ucode_width-1); + rom_data_late : in std_ulogic_vector(0 to 31); + + ucode_valid : out std_ulogic; + ucode_ifar : out std_ulogic_vector(41 to 61); + ucode_instruction : out std_ulogic_vector(0 to 31); + is_uCode : out std_ulogic; + extRT : out std_ulogic; + extS1 : out std_ulogic; + extS2 : out std_ulogic; + extS3 : out std_ulogic; + + hold_thread : out std_ulogic; + + uc_control_dbg_data : out std_ulogic_vector(0 to 3) +); +-- synopsys translate_off + + + +-- synopsys translate_on + +end iuq_uc_control; + + +architecture iuq_uc_control of iuq_uc_control is + +constant xu_iu_spr_xer_offset : natural := 0; +constant bubble_offset : natural := xu_iu_spr_xer_offset + 7; +constant valid_offset : natural := bubble_offset + 1; +constant instr_offset : natural := valid_offset + 1; +constant instr_late_offset : natural := instr_offset + 32; +constant sel_late_offset : natural := instr_late_offset + 15; +constant early_end_offset : natural := sel_late_offset + 11; +constant cond_offset : natural := early_end_offset + 1; +constant rom_addr_offset : natural := cond_offset + 1; +constant inloop_offset : natural := rom_addr_offset + 10; +constant count_offset : natural := inloop_offset + 1; +constant skip_zero_offset : natural := count_offset + 5; +constant skip_to_np1_offset : natural := skip_zero_offset + 1; +constant skip_cond_offset : natural := skip_to_np1_offset + 1; +constant skip_offset : natural := skip_cond_offset + 1; +constant wait_offset : natural := skip_offset + 1; +constant force_ep_offset : natural := wait_offset + 1; +constant ep_force_late_offset : natural := force_ep_offset + 1; +constant scan_right : natural := ep_force_late_offset + 1 - 1; + +subtype s3 is std_ulogic_vector(0 to 2); + +signal bubble_fast : std_ulogic; +signal valid_fast : std_ulogic; + +-- Latches +signal xu_iu_spr_xer_d : std_ulogic_vector(57 to 63); +signal bubble_d : std_ulogic; +signal valid_d : std_ulogic; +signal instr_d : std_ulogic_vector(0 to 31); +signal early_end_d : std_ulogic; +signal cond_d : std_ulogic; +signal rom_addr_d : std_ulogic_vector(0 to 9); +signal inLoop_d : std_ulogic; +signal count_d : std_ulogic_vector(0 to 4); +signal skip_zero_d : std_ulogic; +signal skip_to_np1_d : std_ulogic; +signal skip_cond_d : std_ulogic; +signal skip_d : std_ulogic; +signal wait_d : std_ulogic; + +signal xu_iu_spr_xer_l2 : std_ulogic_vector(57 to 63); +signal bubble_l2 : std_ulogic; +signal valid_l2 : std_ulogic; +signal instr_l2 : std_ulogic_vector(0 to 31); +signal early_end_l2 : std_ulogic; +signal cond_l2 : std_ulogic; +signal rom_addr_l2 : std_ulogic_vector(0 to 9); +signal inLoop_l2 : std_ulogic; +signal count_l2 : std_ulogic_vector(0 to 4); +signal skip_zero_l2 : std_ulogic; +signal skip_to_np1_l2 : std_ulogic; +signal skip_cond_l2 : std_ulogic; +signal skip_l2 : std_ulogic; +signal wait_l2 : std_ulogic; + +signal force_ep_d : std_ulogic; +signal force_ep_l2 : std_ulogic; + + +signal new_command : std_ulogic; +signal uC_flush : std_ulogic; --flush to uCode +signal uc_act : std_ulogic; + +-- +signal template_code : std_ulogic_vector(0 to 31); +signal uc_end : std_ulogic; +signal uc_end_early : std_ulogic; +signal loop_begin : std_ulogic; +signal loop_end : std_ulogic; +signal loop_end_rom : std_ulogic; +signal count_src : std_ulogic_vector(0 to 2); +signal sel0_5 : std_ulogic; +signal sel6_10 : std_ulogic_vector(0 to 1); +signal sel11_15 : std_ulogic_vector(0 to 1); +signal sel16_20 : std_ulogic_vector(0 to 1); +signal sel21_25 : std_ulogic_vector(0 to 1); +signal sel26_30 : std_ulogic; +signal sel31 : std_ulogic; +signal cr_bf2fxm : std_ulogic; -- for mtocrf +signal skip_cond : std_ulogic; +signal skip_zero : std_ulogic; +signal loop_addr : std_ulogic_vector(0 to 9); +signal loop_init : std_ulogic_vector(0 to 2); +signal ep_instr : std_ulogic; + +signal ucode_end : std_ulogic; +signal fxm : std_ulogic_vector(0 to 7); + +--timing fixes +signal sel0_5_late : std_ulogic; +signal sel6_10_late : std_ulogic_vector(0 to 1); +signal sel11_15_late : std_ulogic_vector(0 to 1); +signal sel16_20_late : std_ulogic_vector(0 to 1); +signal sel21_25_late : std_ulogic_vector(0 to 1); +signal sel26_30_late : std_ulogic; +signal sel31_late : std_ulogic; + +signal sel_late_d : std_ulogic_vector(0 to 10); +signal sel_late_l2 : std_ulogic_vector(0 to 10); +signal ep_force_late_d : std_ulogic; +signal ep_force_late_l2 : std_ulogic; +signal instr_late_d : std_ulogic_vector(6 to 20); +signal instr_late_l2 : std_ulogic_vector(6 to 20); + + +-- control +signal last_loop : std_ulogic; +signal loopback_part1 : std_ulogic; +signal loopback : std_ulogic; +signal inc_RT : std_ulogic; + +signal NB_dec : std_ulogic_vector(0 to 4); +signal NB_comp : std_ulogic_vector(0 to 1); +signal XER_dec_z : std_ulogic_vector(0 to 6); +signal XER_low : std_ulogic_vector(0 to 2); +signal XER_comp : std_ulogic_vector(0 to 1); +signal count_init : std_ulogic_vector(0 to 4); +signal skip : std_ulogic; + + +signal siv : std_ulogic_vector(0 to scan_right); +signal sov : std_ulogic_vector(0 to scan_right); + +begin + + + +----------------------------------------------------------------------- +-- load new command +----------------------------------------------------------------------- +new_command <= load_command and not bubble_l2; -- guard against back-to-back uCode instructions from Issue +uC_flush <= flush and not restart and (valid_l2 or wait_l2); + +uc_act <= load_command or valid_l2 or wait_l2 or spr_ic_clockgate_dis; +uc_act_thread <= uc_act; + +bubble_d <= not flush and new_command; + +valid_d <= (new_command and not flush) or + (valid_l2 and not (ucode_end and data_valid) and not flush) or + uC_flush or + (ib_flush and not flush); + + +bubble_fast <= bubble_d; + +valid_fast <= (new_command and not flush) or + (valid_l2 and not flush) or + uC_flush or + (ib_flush and not flush); + + +-- RT +instr_d(0 to 5) <= new_instr(0 to 5) when new_command = '1' + else instr_l2(0 to 5); + +instr_d(6 to 10) <= flush_ifar(49 to 53) when flush = '1' + else ib_flush_ifar(49 to 53) when ib_flush = '1' + else new_instr(6 to 10) when new_command = '1' + else instr_l2(6 to 10) + 1 when inc_RT = '1' + else instr_l2(6 to 10); + +instr_d(11 to 31) <= new_instr(11 to 31) when new_command = '1' + else instr_l2(11 to 31); + +early_end_d <= early_end when new_command = '1' + else early_end_l2; + +cond_d <= new_cond when new_command = '1' + else cond_l2; + +force_ep_d <= force_ep when new_command = '1' + else force_ep_l2; + +rom_addr_d <= flush_ifar(41 to 42) & flush_ifar(54 to 61) when flush = '1' + else ib_flush_ifar(41 to 42) & ib_flush_ifar(54 to 61) when ib_flush = '1' + else start_addr when new_command = '1' + else loop_addr when loopback = '1' + else rom_addr_l2(0 to 1) & (rom_addr_l2(2 to 9) + 1) when data_valid = '1' + else rom_addr_l2; + +rom_ra <= rom_addr_d; + +ra_valid <= valid_d and not bubble_d and buff_avail; +vld_fast <= valid_fast and not bubble_fast and buff_avail; + +uc_end <= rom_data(32); +uc_end_early <= rom_data(33); +loop_begin <= rom_data(34); +loop_end <= rom_data(35) and inLoop_l2; +loop_end_rom <= rom_data(35); -- for timing fix. Must check inLoop_l2 wherever this is used. +count_src <= rom_data(36 to 38); -- 00: NB(3:4), 01: "000" & 2's comp NB(3:4), 10: mult of 4 & XER(62:63), 11: 2's comp XER(62:63), 100: RT(inverted), 101: NB(0:2) - word mode, 110: XER(57:61) - word mode, 111: loop_init +extRT <= rom_data(39); +extS1 <= rom_data(40); +extS2 <= rom_data(41); +extS3 <= rom_data(42); +sel0_5 <= rom_data(43); +sel6_10 <= rom_data(44 to 45); +sel11_15 <= rom_data(46 to 47); +sel16_20 <= rom_data(48 to 49); +sel21_25 <= rom_data(50 to 51); +sel26_30 <= rom_data(52); +sel31 <= rom_data(53); +cr_bf2fxm <= rom_data(54); +skip_cond <= rom_data(55); +skip_zero <= rom_data(56); -- For when XER = 0 & to help with NB coding +loop_addr <= rom_data(57 to 66); -- Note: Could latch loop_begin address instead of keeping in ROM +loop_init <= rom_data(67 to 69); +ep_instr <= rom_data(70); + + +template_code(0 to 26) <= rom_data_late(0 to 26); +template_code(27) <= rom_data_late(27) or ep_force_late_l2; +template_code(28 to 31) <= rom_data_late(28 to 31); + +sel_late_d(0) <= sel0_5; +sel_late_d(1 to 2) <= sel6_10; +sel_late_d(3 to 4) <= sel11_15; +sel_late_d(5 to 6) <= sel16_20; +sel_late_d(7 to 8) <= sel21_25; +sel_late_d(9) <= sel26_30; +sel_late_d(10) <= sel31; + +sel0_5_late <= sel_late_l2(0); +sel6_10_late <= sel_late_l2(1 to 2); +sel11_15_late <= sel_late_l2(3 to 4); +sel16_20_late <= sel_late_l2(5 to 6); +sel21_25_late <= sel_late_l2(7 to 8); +sel26_30_late <= sel_late_l2(9); +sel31_late <= sel_late_l2(10); + +ep_force_late_d <= ep_instr and force_ep_l2; + +ucode_end <= uc_end or (uc_end_early and early_end_l2); + +with s3'(instr_l2(6 to 8)) select +fxm <= "10000000" when "000", + "01000000" when "001", + "00100000" when "010", + "00010000" when "011", + "00001000" when "100", + "00000100" when "101", + "00000010" when "110", + "00000001" when others; + +-- instr_l2(0:5) & (21:31) never change while processing command +instr_late_d( 6 to 10) <= instr_l2( 6 to 10); +instr_late_d(11 to 20) <= instr_l2(11 to 20) when cr_bf2fxm = '0' else ('1' & fxm(0 to 7) & '0'); + + + +with sel0_5_late select +ucode_instruction(0 to 5) <= template_code(0 to 5) when '0', + instr_l2(0 to 5) when others; + +with sel6_10_late select +ucode_instruction(6 to 10) <= template_code(6 to 10) when "00", + instr_late_l2(6 to 10) when "01", + instr_late_l2(11 to 15) when "10", + instr_late_l2(16 to 20) when others; + + +with sel11_15_late select +ucode_instruction(11 to 15) <= template_code(11 to 15) when "00", + instr_late_l2(11 to 15) when "01", + instr_late_l2(16 to 20) when "10", + instr_late_l2(6 to 10) when others; + +with sel16_20_late select +ucode_instruction(16 to 20) <= template_code(16 to 20) when "00", + instr_late_l2(16 to 20) when "01", + instr_late_l2(6 to 10) when "10", + instr_late_l2(11 to 15) when others; + +with sel21_25_late select +ucode_instruction(21 to 25) <= template_code(21 to 25) when "00", + instr_l2(21 to 25) when "01", + instr_late_l2(16 to 20) when others; + +with sel26_30_late select +ucode_instruction(26 to 30) <= template_code(26 to 30) when '0', + instr_l2(26 to 30) when others; + +with sel31_late select +ucode_instruction(31) <= template_code(31) when '0', + instr_l2(31) when others; + +ucode_valid <= data_valid and not flush and not ib_flush and not skip; +is_ucode <= not ucode_end; -- is_ucode signal must drop for the last instruction + + +ucode_ifar(41 to 61) <= rom_addr_l2(0 to 1) & count_l2 & inLoop_l2 & instr_l2(6 to 10) & rom_addr_l2(2 to 9); + + +----------------------------------------------------------------------- +-- control, state machines +----------------------------------------------------------------------- +-- Assumptions: +-- No Nested Loops +-- All Loops must have at least 2 instructions +-- New ucode instructions will be held off until XU flushes IU (to next instruction) on this thread +-- If loop_end is skip_c, the instruction before loop_end must also be skip_c +inLoop_d <= flush_ifar(48) when uC_flush = '1' + else '0' when flush = '1' -- clear for non-uCode flush + else ib_flush_ifar(48) when ib_flush = '1' + else (((data_valid and loop_begin) or inLoop_l2) and not ((data_valid and loop_end) and last_loop) and valid_l2 and not bubble_l2); + +last_loop <= (count_l2 = "00000") or (skip_zero_l2 and count_l2 = "00001") or skip_cond_l2; + +loopback_part1 <= data_valid and inLoop_l2 and not last_loop; +loopback <= loopback_part1 and loop_end_rom; + +inc_RT <= data_valid and loop_end and not (skip_zero_l2 and count_l2 = "00000") and + count_src(0) and not (count_src = "111"); -- load/store multiple & string op word loops + + + +NB_dec <= instr_l2(16 to 20) - 1; +NB_comp(0) <= instr_l2(19) xor instr_l2(20); +NB_comp(1) <= instr_l2(20); + + +xu_iu_spr_xer_d <= xu_iu_spr_xer; + +XER_dec_z <= "0000000" when xu_iu_spr_xer_l2(57 to 63) = "0000000" + else xu_iu_spr_xer_l2(57 to 63) - 1; +XER_low <= "100" when XER_dec_z(5 to 6) = "11" + else '0' & xu_iu_spr_xer_l2(62 to 63); +XER_comp(0) <= xu_iu_spr_xer_l2(62) xor xu_iu_spr_xer_l2(63); +XER_comp(1) <= xu_iu_spr_xer_l2(63); + +with count_src select +count_init <= "000" & NB_dec(3 to 4) when "000", + "000" & NB_comp(0 to 1) when "001", + "00" & XER_low when "010", + "000" & XER_comp(0 to 1) when "011", + not (instr_l2(6 to 10)) when "100", + "00" & NB_dec(0 to 2) when "101", + XER_dec_z(0 to 4) when "110", + "00" & loop_init when others; + + +-- How many cycles is XER bubble? XER is available in EX6. XER has been latched, moving to 7 bubbles +-- Dependency is now checking XER dependencies, so we do not need extra delay for xer_type +count_d <= flush_ifar(43 to 47) when flush = '1' + else ib_flush_ifar(43 to 47) when ib_flush = '1' + else "00000" when new_command = '1' -- 1 cycle bubble + else count_init when (data_valid and loop_begin and not inLoop_l2) = '1' + else count_l2 - 1 when ((data_valid and loop_end) = '1') + else count_l2; + + +skip_zero_d <= '0' when (flush or ib_flush or (data_valid and loop_end) or new_command) = '1' + else skip_zero when (data_valid and loop_begin) = '1' + else skip_zero_l2; + +-- Now flush is always np1 flush +skip_to_np1_d <= not restart when flush = '1' + else '0' when data_valid = '1' + else skip_to_np1_l2; + +skip_cond_d <= '0' when (flush or ib_flush or new_command) = '1' + else (skip_cond and cond_l2) when data_valid = '1' + else skip_cond_l2; + +skip <= (((skip_zero and loop_begin) or skip_zero_l2) and (count_l2 = "00000") and inLoop_l2) or + ( (skip_zero and loop_begin) and count_init = "00000" and not inLoop_l2) or + (skip_cond and cond_l2) or + skip_to_np1_l2; + +skip_d <= skip; -- Latch is just for trace bus + +wait_d <= ((valid_l2 and ucode_end and data_valid) or + wait_l2) + and not flush and not ib_flush; -- Either flushing back to uCode instruction, or XU is flushing to next command + + +hold_thread <= valid_l2 or wait_l2; + +-- Debug +uc_control_dbg_data <= bubble_l2 & valid_l2 & wait_l2 & skip_l2; + +----------------------------------------------------------------------- +-- Latches +----------------------------------------------------------------------- + +xu_iu_spr_xer_latch: tri_rlmreg_p + generic map (width => xu_iu_spr_xer_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => uc_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(xu_iu_spr_xer_offset to xu_iu_spr_xer_offset + xu_iu_spr_xer_l2'length-1), + scout => sov(xu_iu_spr_xer_offset to xu_iu_spr_xer_offset + xu_iu_spr_xer_l2'length-1), + din => xu_iu_spr_xer_d, + dout => xu_iu_spr_xer_l2); + +bubble_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => uc_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(bubble_offset), + scout => sov(bubble_offset), + din => bubble_d, + dout => bubble_l2); + +valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => uc_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(valid_offset), + scout => sov(valid_offset), + din => valid_d, + dout => valid_l2); + +instr_latch: tri_rlmreg_p + generic map (width => instr_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => uc_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(instr_offset to instr_offset + instr_l2'length-1), + scout => sov(instr_offset to instr_offset + instr_l2'length-1), + din => instr_d, + dout => instr_l2); + +instr_late_latch: tri_rlmreg_p + generic map (width => instr_late_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => data_valid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(instr_late_offset to instr_late_offset + instr_late_l2'length-1), + scout => sov(instr_late_offset to instr_late_offset + instr_late_l2'length-1), + din => instr_late_d, + dout => instr_late_l2); + +sel_late_latch: tri_rlmreg_p + generic map (width => sel_late_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => data_valid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(sel_late_offset to sel_late_offset + sel_late_l2'length-1), + scout => sov(sel_late_offset to sel_late_offset + sel_late_l2'length-1), + din => sel_late_d, + dout => sel_late_l2); + +early_end_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => uc_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(early_end_offset), + scout => sov(early_end_offset), + din => early_end_d, + dout => early_end_l2); + +cond_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => uc_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(cond_offset), + scout => sov(cond_offset), + din => cond_d, + dout => cond_l2); + +rom_addr_latch: tri_rlmreg_p + generic map (width => rom_addr_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => uc_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(rom_addr_offset to rom_addr_offset + rom_addr_l2'length-1), + scout => sov(rom_addr_offset to rom_addr_offset + rom_addr_l2'length-1), + din => rom_addr_d, + dout => rom_addr_l2); + +count_latch: tri_rlmreg_p + generic map (width => count_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => uc_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(count_offset to count_offset + count_l2'length-1), + scout => sov(count_offset to count_offset + count_l2'length-1), + din => count_d, + dout => count_l2); + +inloop_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => uc_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(inloop_offset), + scout => sov(inloop_offset), + din => inloop_d, + dout => inloop_l2); + +skip_zero_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => uc_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(skip_zero_offset), + scout => sov(skip_zero_offset), + din => skip_zero_d, + dout => skip_zero_l2); + +skip_to_np1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => uc_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(skip_to_np1_offset), + scout => sov(skip_to_np1_offset), + din => skip_to_np1_d, + dout => skip_to_np1_l2); + +skip_cond_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => uc_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(skip_cond_offset), + scout => sov(skip_cond_offset), + din => skip_cond_d, + dout => skip_cond_l2); + +skip_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => uc_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(skip_offset), + scout => sov(skip_offset), + din => skip_d, + dout => skip_l2); + +wait_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => uc_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(wait_offset), + scout => sov(wait_offset), + din => wait_d, + dout => wait_l2); + +force_ep_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => uc_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(force_ep_offset), + scout => sov(force_ep_offset), + din => force_ep_d, + dout => force_ep_l2); + +ep_force_late_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => data_valid, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(ep_force_late_offset), + scout => sov(ep_force_late_offset), + din => ep_force_late_d, + dout => ep_force_late_l2); + +----------------------------------------------------------------------- +-- Scan +----------------------------------------------------------------------- +siv(0 to scan_right) <= sov(1 to scan_right) & scan_in; +scan_out <= sov(0); + +end iuq_uc_control; diff --git a/rel/src/vhdl/work/iuq_uc_rom.vhdl b/rel/src/vhdl/work/iuq_uc_rom.vhdl new file mode 100644 index 0000000..e68fac4 --- /dev/null +++ b/rel/src/vhdl/work/iuq_uc_rom.vhdl @@ -0,0 +1,18171 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +--******************************************************************** +--* +--* TITLE: IU Microcode Code +--* +--* NAME: iuq_uc_rom.vhdl +--* +--********************************************************************* + +library ieee,ibm,support,tri; +use ieee.std_logic_1164.all; +use ibm.std_ulogic_unsigned.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use support.power_logic_pkg.all; +use tri.tri_latches_pkg.all; + +entity iuq_uc_rom is + generic(ucode_width : integer := 71; + regmode : integer := 6; + expand_type : integer := 2); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + pc_iu_func_sl_thold_0_b : in std_ulogic; + pc_iu_sg_0 : in std_ulogic; + forcee : in std_ulogic; + d_mode : in std_ulogic; + delay_lclkr : in std_ulogic; + mpw1_b : in std_ulogic; + mpw2_b : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + rom_act : in std_ulogic; + rom_addr : in std_ulogic_vector(0 to 9); + rom_data : out std_ulogic_vector(0 to ucode_width-1) +); +-- synopsys translate_off +-- synopsys translate_on +end iuq_uc_rom; +ARCHITECTURE IUQ_UC_ROM + OF IUQ_UC_ROM + IS +--@@ Signal Declarations +SIGNAL ROM32_INSTR_PT : STD_ULOGIC_VECTOR(1 TO 893) := +(OTHERS=> 'U'); +SIGNAL ROM64_INSTR_PT : STD_ULOGIC_VECTOR(1 TO 890) := +(OTHERS=> 'U'); +SIGNAL count_src : STD_ULOGIC_VECTOR(0 TO 2) := +"UUU"; +SIGNAL cr_bf2fxm : STD_ULOGIC := +'U'; +SIGNAL ep : STD_ULOGIC := +'U'; +SIGNAL extRT : STD_ULOGIC := +'U'; +SIGNAL extS1 : STD_ULOGIC := +'U'; +SIGNAL extS2 : STD_ULOGIC := +'U'; +SIGNAL extS3 : STD_ULOGIC := +'U'; +SIGNAL loop_addr : STD_ULOGIC_VECTOR(0 TO 9) := +"UUUUUUUUUU"; +SIGNAL loop_begin : STD_ULOGIC := +'U'; +SIGNAL loop_end : STD_ULOGIC := +'U'; +SIGNAL loop_init : STD_ULOGIC_VECTOR(0 TO 2) := +"UUU"; +SIGNAL sel0_5 : STD_ULOGIC := +'U'; +SIGNAL sel11_15 : STD_ULOGIC_VECTOR(0 TO 1) := +"UU"; +SIGNAL sel16_20 : STD_ULOGIC_VECTOR(0 TO 1) := +"UU"; +SIGNAL sel21_25 : STD_ULOGIC_VECTOR(0 TO 1) := +"UU"; +SIGNAL sel26_30 : STD_ULOGIC := +'U'; +SIGNAL sel31 : STD_ULOGIC := +'U'; +SIGNAL sel6_10 : STD_ULOGIC_VECTOR(0 TO 1) := +"UU"; +SIGNAL skip_cond : STD_ULOGIC := +'U'; +SIGNAL skip_zero : STD_ULOGIC := +'U'; +SIGNAL template : STD_ULOGIC_VECTOR(0 TO 31) := +"UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU"; +SIGNAL ucode_end : STD_ULOGIC := +'U'; +SIGNAL ucode_end_early : STD_ULOGIC := +'U'; +constant rom_addr_offset : natural := 0; +constant scan_right : natural := rom_addr_offset + 10 - 1; +-- Latches +signal rom_addr_d : std_ulogic_vector(0 to 9); +signal rom_addr_l2 : std_ulogic_vector(0 to 9); +signal siv : std_ulogic_vector(0 to scan_right); +signal sov : std_ulogic_vector(0 to scan_right); +signal rom_unused : std_ulogic; +-- synopsys translate_off +-- synopsys translate_on + BEGIN --@@ START OF EXECUTABLE CODE FOR IUQ_UC_ROM + +--64-bit core +c64: if (regmode = 6) generate +begin + + +-- When expanded, ROM_INSTR_PT needs more bits for 32-bit generate than 64-bit. +-- This gets rid of sourceless/sinkless warnings in 64-bit mode. +ROM32_INSTR_PT <= (others => '0'); +rom_unused <= or_reduce(ROM32_INSTR_PT); +-- +-- Final Table Listing +-- *INPUTS*========*OUTPUTS*===============================================================================================* +-- | | | +-- | rom_addr_l2 | template ucode_end | +-- | | | | | ucode_end_early | +-- | | | | | | loop_begin | +-- | | | | | | | loop_end | +-- | | | | | | | | count_src | -- Can DC if not (loop_begin or loop_end) +-- | | | | | | | | | | +-- | | | | | | | | | extRT | +-- | | | | | | | | | | extS1 | +-- | | | | | | | | | | | extS2 | +-- | | | | | | | | | | | | extS3 | +-- | | | | | | | | | | | | | | +-- | | | | | | | | | | | | | sel0_5 | +-- | | | | | | | | | | | | | | sel6_10 | +-- | | | | | | | | | | | | | | | sel11_15 | +-- | | | | | | | | | | | | | | | | sel16_20 | +-- | | | | | | | | | | | | | | | | | sel21_25 | +-- | | | | | | | | | | | | | | | | | | sel26_30 | +-- | | | | | | | | | | | | | | | | | | | sel31 | +-- | | | | | | | | | | | | | | | | | | | | | +-- | | | | | | | | | | | | | | | | | | | | cr_bf2fxm | +-- | | | | | | | | | | | | | | | | | | | | | skip_cond | +-- | | | | | | | | | | | | | | | | | | | | | | skip_zero | -- Can DC if loop_begin not set +-- | | | | | | | | | | | | | | | | | | | | | | | loop_addr | -- Can DC if loop_end not set +-- | | | | | | | | | | | | | | | | | | | | | | | | loop_init | -- 1 less than # of times to loop; Can DC if not loop_begin or not count_src=111 +-- | | | | | | | | | | | | | | | | | | | | | | | | | ep | +-- | | | | 1111111111222222222233 | | | | | | | | | | | | | | | | | | | | | | | +-- | 0123456789 | 01234567890123456789012345678901 | | | | 012 | | | | | 01 01 01 01 | | | | | 0123456789 012 | | +-- *TYPE*==========+=======================================================================================================+ +-- | PPPPPPPPPP | SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS S S S S SSS S S S S S SS SS SS SS S S S S S SSSSSSSSSS SSS S | +-- *POLARITY*----->| ++++++++++++++++++++++++++++++++ + + + + +++ + + + + + ++ ++ ++ ++ + + + + + ++++++++++ +++ + | +-- *PHASE*-------->| TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT T T T T TTT T T T T T TT TT TT TT T T T T T TTTTTTTTTT TTT T | +-- *OPTIMIZE*----->| AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA B B B B CCC X X X X X XX XX XX XX X X X X X XXXXXXXXXX XYX X | +-- *TERMS*=========+=======================================================================================================+ +-- 1 | -100000000 | ................................ . . . . ... . . . . . .1 .. .. .. . . . . . .......... ... . | +-- 2 | -1-0000000 | .1111........................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 3 | 0-11000000 | ................................ . . . . ... . . . . . .1 .. .. .. . . . . . .......... ... . | +-- 4 | 10-1000000 | .1...1....1.............1.1.111. . . . . ... 1 1 . . . .. .. .1 .. . . . . . .......... ... . | +-- 5 | 000-000000 | ..111...........111111111111111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 6 | 110-000000 | .11111....1..........1.1111111.. . . . . ... 1 . . . . .. .. 1. .. . . . . . .......... ... . | +-- 7 | 011-000000 | .....1...11...1...........11.11. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 8 | -0-0100000 | .1...1................1....1.1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 9 | 0001100000 | .1.1.....1.....1.....11...11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 10 | 01-1100000 | .1111...........1....1........1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 11 | -01-100000 | .1.1.1...1....1......11.1.11.1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 12 | -000-00000 | ................................ . . . . ... . . . . . .. .. .1 .. . . . . . .......... ... . | +-- 13 | 11-0-00000 | .........1....1.....1.11.1...... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 14 | 0001010000 | .11111....1.............1.1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 15 | 0-11010000 | .11111...11...11...1..1....1.1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 16 | 10-1010000 | ................................ . . . . ... . . . . . .. .. .1 .1 1 1 . . . .......... ... . | +-- 17 | 0000110000 | .1.1......1...1.11..........111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 18 | 01-0110000 | .11111.............11.1....1.1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 19 | ---0110000 | ................................ . . . . ... 1 1 . . . .. .. .. .. . . . . . .......... ... . | +-- 20 | 0-11110000 | ..111.....1.....1111............ . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 21 | 01-1110000 | .1.1.1........1.1111111..111..1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 22 | 110-110000 | .1.1.....1.....1.....11...11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 23 | 0000-10000 | ................................ . . . . ... . . 1 . . .. .. .. .. . . . 1 . .......... ... . | +-- 24 | 1101-10000 | ................................ . . . . ... 1 . . . . .. .1 .. .. . . . . . .......... ... . | +-- 25 | 011--10000 | .1111....1....1....1.111.11..1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 26 | 11-00-0000 | ................................ . . 1 . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 27 | 00010-0000 | ................................ . . . . ... 1 . 1 . . .. .1 .. .. . . . . . .......... ... . | +-- 28 | 10-01-0000 | ..111........................1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 29 | 11011-0000 | 1..11....1...................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 30 | 011-1-0000 | ......................1.1.1..... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 31 | 1-1-1-0000 | .............................1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 32 | 00--1-0000 | ................................ . . . . ... . 1 . . . .. .. .. .. . . . . . .......... ... . | +-- 33 | 1001--0000 | ..111..........................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 34 | 101---0000 | .1.1......1...1.11..........1.1. . . . . ... . 1 . . . .. .. .. .. . . . 1 . .......... ... . | +-- 35 | 111---0000 | 1..111..............1.....11.... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 36 | --10001000 | .1111....1....1.....1111111..... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 37 | 10-1001000 | ................................ . . . . ... . . . . . .. 11 .. .. . . . . . ....1111.. ... . | +-- 38 | 110-001000 | .1.1.1...1....1..1........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 39 | -01-001000 | ..111.....1.....11111111........ . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 40 | 11-0101000 | ................................ . . . . ... . . . . . 11 .. .1 .. . . . . . .......... ... . | +-- 41 | 0001101000 | .11111....1.............1.1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 42 | 0-11101000 | .11111...11...1....11....1.1.... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 43 | 01-1101000 | .1111............1...11...1..... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 44 | 000-101000 | ................................ . . . . ... . . 1 . . .. .1 .. .. . . . . . .......... ... 1 | +-- 45 | 111-101000 | 1..111...11........11...1.111.1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 46 | 0000-01000 | ................................ . . . . ... . . . . . .. .. .1 .1 1 1 . . . .......... ... . | +-- 47 | -11--01000 | ................................ . . . . ... 1 1 1 1 . .. .. .. .. . . . . . .......... ... . | +-- 48 | 0001011000 | ................................ . . . . ... 1 . . . . .. .1 .1 .1 1 . . . . .......... ... . | +-- 49 | 0-11011000 | .1.1.1..........11111......1.1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 50 | 0--1011000 | ..........................1...1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 51 | 00-0111000 | .1...1....1.............1.1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 52 | 110-111000 | .1.1.1....1...1...........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 53 | 0-1-111000 | .11111...11...11...1..1....1.1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 54 | 0100-11000 | ................................ . . . . ... . . . . . .1 .. .. .. . . . . . .......... ... . | +-- 55 | 1101-11000 | .1.......1....1.11............1. . . 1 . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 56 | 101--11000 | .11111...1....1.....1.11.1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 57 | 011--11000 | .....1....1....1...1..11.1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 58 | -0100-1000 | .........1...........1....1..... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 59 | -0001-1000 | ................................ . . . . ... . . . . . .. .1 .. .. . . . . . .......... ... 1 | +-- 60 | 00-01-1000 | ..111..........................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 61 | 10011-1000 | .1.1.1...1....1..1........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 62 | 11011-1000 | ................................ . . . . ... . . . . . .. .1 .. .. . . . . . .......... ... . | +-- 63 | 000000-000 | ................................ . . . . ... 1 . . . . .. .1 .. .1 1 1 . . . .......... ... . | +-- 64 | -01000-000 | .1.1.1........1.1...........111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 65 | 10-000-000 | 1...1........................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 66 | ---010-000 | ..111........................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 67 | 01-110-000 | ................................ . . . . ... . . . . . .1 .. .. .. . . . . . .......... ... . | +-- 68 | 11-0-0-000 | .1...1....................111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 69 | 101--0-000 | .11111....................111... . . . . ... 1 . . . . 11 .. .1 .. . . . . . .......... ... . | +-- 70 | 000001-000 | .1.1.1...1....1..1...1....1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 71 | 0-1011-000 | .1.1.....1.....1.....11...11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 72 | -------000 | ................................ . . . . 1.. . . . . . .. .. .. .. . . . . . .......... ... . | +-- 73 | 0100000100 | .11111....1...1....1..11.1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 74 | 0001000100 | 1...1.....1..................... . . . . ... 1 1 . . . .. .. .1 .1 1 1 . . . .......... ... . | +-- 75 | 1101000100 | .1.1......1...1.1...........111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 76 | 0-11000100 | ...1.................11...1..11. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 77 | 01-1000100 | .1111.........111111....1.....1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 78 | 011-000100 | .1111............1...11...1...1. . . . . ... . . . . . .1 .. .. .. . . . . . .......... ... . | +-- 79 | 10--000100 | ..1.1..........................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 80 | 0100100100 | ...11.........111111....1.....1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 81 | 11-0100100 | ................................ . . . . ... . 1 . . . .. .. .. .. . . . 1 . .......... ... . | +-- 82 | 0001100100 | .11111....................111... . . . . ... . . . . . 11 .. .1 .. . . . . . .......... ... . | +-- 83 | 0-11100100 | .1.1.1.........11....1....11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 84 | 1-1-100100 | 1..111...11...1....1......111.1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 85 | 10--100100 | ................................ . . . . ... . . . . . .. .1 .. .. . . . . . .......... ... . | +-- 86 | 0000-00100 | .1.1.1...1....1..1...1....1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 87 | 10-0-00100 | ................................ . . . . ... . . . . . .. .. .1 .1 1 1 . . . .......... ... . | +-- 88 | 1101-00100 | ................................ . . . . ... . . 1 . . .. .. .. .. . . . 1 . .......... ... . | +-- 89 | 0100010100 | .1111.........11111....1......1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 90 | 11-0010100 | .1.1.1...1....1..1........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 91 | 0001010100 | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . 1 . .......... ... . | +-- 92 | 01-1010100 | .1111.........11..........1...1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 93 | -01-010100 | .1.1.1...1....1......1111.1111.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 94 | --1-010100 | ................................ . . . . ... . 1 . 1 . .. .. .. .. . . . . . .......... ... . | +-- 95 | 0000110100 | .11111....................111... . . . . ... 1 . . . . 11 .. .1 .. . . . . . .......... ... . | +-- 96 | 01-0110100 | .1111.........111....1........1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 97 | 01-1110100 | .1111....1....1...11.11..11..1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 98 | 110-110100 | ..111.....1.....1111111111111..1 . . . . ... 1 . . . . .. .1 .. .. . . . . . .......... ... . | +-- 99 | 0001-10100 | .1.1......1...1.11..........111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 100 | 1101-10100 | .1...1...1.............11.1.111. . . . . ... . 1 . 1 . .. .. .1 .. . . . . . .......... ... . | +-- 101 | 011--10100 | .11111.............1..11.1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 102 | -0100-0100 | .1.1.1...1....1..1........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 103 | 10-01-0100 | ...............................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 104 | 11011-0100 | .1111....1....1.11............1. . . 1 . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 105 | 101---0100 | .1...1...1..............1.1.111. . . . . ... . . . . . .. .1 .. .. . . . . . .......... ... . | +-- 106 | 0100001100 | .1111.........111111....1.....1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 107 | 0001001100 | ................................ . . . . ... 1 . . . . 11 .. .1 .. . . . . . .......... ... . | +-- 108 | -001001100 | .11111....................111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 109 | --11001100 | .11111.............1......11.... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 110 | 01-1001100 | .1111.........111.1....1......1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 111 | -1-1001100 | .................1.............. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 112 | 00-0101100 | 1...1.....1..................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 113 | 10-0101100 | .1.1......1...1.1.....1....1111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 114 | 01-0101100 | ...11.........11111....1......1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 115 | 11-0101100 | ...1.1..................1.1.111. . . . . ... . . . . . .. .1 .. .. . . . . . .......... ... 1 | +-- 116 | 01-1101100 | .11111...11....1..........11.11. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 117 | 0-1-101100 | .1.1.1....1...1.1....1....11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 118 | 011--01100 | .1.1.1........1.1111111..111..1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 119 | 11-0011100 | 1...1....1...................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 120 | --11011100 | ................................ . . . . ... 1 . . . . .1 .. .. .. . . . . . .......... ... . | +-- 121 | 01-1011100 | ...............111....1.......1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 122 | -1-1111100 | ..........1....1................ . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 123 | 100-111100 | ................................ . . . . ... 1 . . . . .. .1 .. .. . . . . . .......... ... . | +-- 124 | 110-111100 | .11111...1.............11.1.111. . . 1 . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 125 | 0-1-111100 | ..........1...1..........1..1... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 126 | 11--111100 | ................................ . . . . ... . . . . . .. .. .1 .. . . . . . .......... ... . | +-- 127 | 0000-11100 | .1.1......1...1.11..........111. . . . . ... . . . . . .. .. .. .. . . . 1 . .......... ... . | +-- 128 | 0100-11100 | .....1....1...1....1..11.1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 129 | 0001-11100 | 1...1.....1..................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 130 | 11-1-11100 | ................................ . . . . ... 1 . . . . .. .1 .. .. . . . . . .......... ... . | +-- 131 | 0-0--11100 | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . . . .......... ... . | +-- 132 | 011--11100 | .....1...11...1...........11.11. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 133 | 10-00-1100 | ...1.1................1....1.1.. . . . . ... 1 . . . . .. .1 .1 .. . . . . . .......... ... . | +-- 134 | -1110-1100 | 1........................1..11.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 135 | 1-1-0-1100 | ................................ . . . . ... 1 . . 1 . .. 1. 11 .. . . . . . .......... ... . | +-- 136 | 00011-1100 | .1.1.....1.....1.....11...11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 137 | 1-011-1100 | .1...1...1.............11.1.111. . . . . ... . 1 . . . .. .. .1 .. . . . . . .......... ... 1 | +-- 138 | -01-00-100 | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . . . .......... ... . | +-- 139 | 11-010-100 | ....1.....1...1................. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 140 | 101--0-100 | .11111....1.............1.1.111. . . . . ... 1 . 1 . . .. .1 .. .. . . . . . .......... ... . | +-- 141 | 000001-100 | ................................ . . . . ... 1 . . . . .. .1 .1 .1 1 1 . . . .......... ... . | +-- 142 | 00-001-100 | ..111..........................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 143 | 1-1-01-100 | 1...11...11.............11111.1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 144 | -00111-100 | .1.1.1...1....1..1........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 145 | 0-1111-100 | .11111.............1......11.... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 146 | 10-0-1-100 | ..111........................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 147 | 11-0000-00 | ..111..........................1 . . 1 . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 148 | -010100-00 | .1.1.....1.....1.....11...11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 149 | ---0100-00 | ................................ . . . 1 ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 150 | -010010-00 | ..111..........................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 151 | 10--010-00 | ..111........................... . . . . ... 1 . . . . .. .1 .. .. . . . . . .......... ... . | +-- 152 | --1---0-00 | ................................ . . . . ... 1 . 1 . . .. .. .. .. . . . . . .......... ... . | +-- 153 | 0000001-00 | .11111....1.............1.1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 154 | -010001-00 | .........1...........1....1..... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 155 | 10-1001-00 | ...111...1....1.....1.11.1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 156 | ----001-00 | ................................ . . . 1 ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 157 | 01-1111-00 | .....1.............1..11.1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 158 | 11-1111-00 | 1...11.........1........111111.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 159 | -11-111-00 | ................................ . . . . ... 1 1 . 1 . .. .. .1 .. . . . . . .......... ... . | +-- 160 | 1001-11-00 | 1..11....1.....................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 161 | 01---11-00 | .1111........................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 162 | 011-1-1-00 | .1...1.........1....1.11.1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 163 | --0-10--00 | ................................ . . . . ... 1 . . 1 . .. .. .. .. . . . . . ......1... ... . | +-- 164 | 10-001--00 | .1.1.1................1....1.1.. . . . . ... 1 . . . . .. .1 .1 .. . . . . . .......... ... . | +-- 165 | --10-1--00 | ................................ . . . . ... . 1 . . . .. .. .. .. . . . . . .......... ... . | +-- 166 | 1101-1--00 | ..111........................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 167 | 0-1-1---00 | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . . . .......... ... . | +-- 168 | 0100000010 | ..1111....1....1.1.1.1.1.1.1.1.1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 169 | 1101000010 | .1.1.1....1...1...........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 170 | 0-11000010 | .1...1.........1........11.1.... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 171 | 10-1000010 | .1.1......1...1.1.....1....1111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 172 | 011-000010 | .1111....1....1...1..11.111..1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 173 | 11-0100010 | .1111.....1....1.1.............. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 174 | 0-11100010 | ..111....11...11..........1..... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 175 | 01-1100010 | .1111..........111....1.......1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 176 | 0000-00010 | 1...1....1.....................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 177 | 1-1--00010 | 1..111...1................11..1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 178 | -0---00010 | ................................ . . . . ... . . 1 . . .. .. .. .. . . . . . .......... ... . | +-- 179 | -010010010 | 1..11....1...................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 180 | 00-1110010 | .1.1.1...1....1......111.1111.1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 181 | 01-1110010 | ...111...11...1...........11.11. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 182 | 110-110010 | ...11..............1.1...1.1.... . . . . ... . . 1 . . .1 .. .. .. . . . . . .......... ... . | +-- 183 | -11-110010 | 1..111...11...............11..1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 184 | 0100-10010 | .1111.....1...1......11111...11. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 185 | 11-0-10010 | .1...1....1.............1.1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 186 | 0001-10010 | .1.1.1...1....1..1........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 187 | 1101-10010 | ..111..........................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 188 | 011--10010 | .1111...........11...11...1...1. . . . . ... . . . . . .1 .. .. .. . . . . . .......... ... . | +-- 189 | 11-00-0010 | ................................ . . . . ... 1 . 1 . . .. .1 .. .. . . . . . .......... ... . | +-- 190 | 1--00-0010 | ..1............................. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 191 | 0-110-0010 | ..111.....1.....11.............. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 192 | 1-1-0-0010 | ................................ . . . . ... 1 . . 1 . .. .1 .. .. . . . . . .......... ... . | +-- 193 | 00011-0010 | .11.1....1...................... . . . . ... . 1 . . . .. 11 .. .. . . . . . .......... ... . | +-- 194 | 11011-0010 | ...111....1..........1.11111111. . . . . ... . . . . . .. .. 1. .. . . . . . .......... ... . | +-- 195 | 1--11-0010 | .11............................. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 196 | 011-1-0010 | .1...1........1.....1.1..1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 197 | 111-1-0010 | ................................ . . . . ... . . . . . .. .. .. 1. . . . . . .......... ... . | +-- 198 | 101---0010 | ................................ 1 . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 199 | 1--0001010 | .1.1......1...1.11..........111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 200 | 1101001010 | ................................ 1 . . . ... . . . . . 1. .1 .1 .1 1 1 . . . .......... ... . | +-- 201 | 00-1001010 | .1.1.1...1....1......111..111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 202 | 0-0-001010 | .1111.....1...1......11111...11. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 203 | 011-001010 | .11111....1....1...1..11.1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 204 | 10--001010 | .....1....1.............1.1.111. . . . . ... . . . . . .. .. .1 .. . . . . . .......... ... . | +-- 205 | 0-11101010 | .11111.............1.1....11.... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 206 | 01-1101010 | .11111.............1..11.1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 207 | 110-101010 | ..111..........................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 208 | 0001-01010 | .1111....1....1.11............1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 209 | 1-01-01010 | ..111..........................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 210 | 000--01010 | ................................ . . 1 . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 211 | 11-0011010 | ...111.........1......1....1.1.. . . . . ... . 1 1 . . 1. .. .. .. . . . . . .......... ... . | +-- 212 | 1--0011010 | ................................ 1 . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 213 | --11011010 | .........11...11..............1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 214 | 01-1011010 | .1.............11....1........1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 215 | -0-0111010 | .1.1.1...1....1..1........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 216 | 01-1111010 | .1111....1....1.....1111111..... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 217 | 1-0-111010 | .1.1......1...1.1...........111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 218 | 0-1-111010 | .1.1.1.........11..1..111.11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 219 | 0100-11010 | ..1111....1....1.1.1.1.1.1.1.1.1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 220 | -010-11010 | ................................ . . . . ... 1 . . . . .. .1 .. .. . . . . . .......... ... . | +-- 221 | 1001-11010 | 1..11....1....................1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 222 | 1101-11010 | .1.1.....1.....1.....11...11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 223 | 011--11010 | .1.1.1........1.1111111..111..1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 224 | 00010-1010 | ...............................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 225 | -0101-1010 | 1..11....1...................... . . . . ... . 1 . 1 . .. .. .1 .1 1 . . . . .......... ... . | +-- 226 | 10-01-1010 | .1.1.1...1....1.11........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 227 | -0-1--1010 | ................................ . . . . ... 1 1 . . . .. .. .. .. . . . . . .......... ... . | +-- 228 | 000100-010 | ..111..........................1 . . 1 . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 229 | 01-100-010 | .1111.....1...1......11111...11. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 230 | 010010-010 | .1111.....1...1......11111...11. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 231 | 101--0-010 | ..111..........................1 . . 1 . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 232 | 000001-010 | ................................ . . . . ... . 1 . . . .. 11 .. .. . . . . . .......... ... . | +-- 233 | 1-1-01-010 | 1..111....................11..1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 234 | --1011-010 | ................................ . . . . ... 1 . . . . .. .1 .. .. . . . . . .......... ... . | +-- 235 | --01-1-010 | ................................ . . . . ... 1 1 . 1 . .. .. .. .. . . . . . 1....1.... 1.. . | +-- 236 | 0100000110 | ...............1...11........... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 237 | 11-0000110 | 1...1.....1..................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 238 | 0001000110 | .1.1.1...1....1..1........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 239 | 1101000110 | ................................ . . 1 . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 240 | --11000110 | ..111....11...11...........1.... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 241 | 10-1000110 | .1...1....1.............1.1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 242 | 11-1000110 | 1..11....1...................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 243 | 010-000110 | .11111...1................111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 244 | 011-000110 | .1...1.............1..11.1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 245 | 0000100110 | ...1.1...1...........111..11.1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 246 | 0001100110 | ................................ . . 1 . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 247 | 0-01100110 | ..111..........................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 248 | 0000-00110 | ................................ . . . . ... . . . . . .. 1. .. .. . . . . . .......... ... . | +-- 249 | 0100-00110 | ...1.1...1................111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 250 | -010-00110 | ................................ . . . . ... 1 . . . . .. .1 .. .. . . . . . .......... ... . | +-- 251 | 10-1-00110 | ................................ . . . . ... . . . 1 . .. .. .1 .. . . . . . .......... ... . | +-- 252 | 11-0010110 | .1.1......1...1.11..........111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 253 | 0001010110 | ..111.....1.....11111111111111.1 . . . . ... 1 . . . . .. .1 .. .. . . . . . .......... ... . | +-- 254 | 0-11010110 | .11111.............1......11.... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 255 | -000110110 | ................................ . . 1 . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 256 | --01110110 | ................................ . . . . ... . . . . . .1 .. .. .. . . . . . .......... ... . | +-- 257 | 01-1110110 | .1111...........11...11...1..... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 258 | 110-110110 | .11111....1..........1.11.111.1. . . . . ... 1 . . . . .. .. 1. .. . . . . . .......... ... . | +-- 259 | 1001-10110 | 1..11....1...................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 260 | 1101-10110 | .11111....1..........1.11111111. . . . . ... . . . . . .. .. 1. .. . . . . . .......... ... . | +-- 261 | 011--10110 | .1111....1....1.....1111111..... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 262 | 1-1-0-0110 | .........1.........11...1....... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 263 | 10011-0110 | .1...1...1.............11.1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 264 | 0-111-0110 | .1.1.1....1...1.1....1....11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 265 | -100001110 | .11111...1................111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 266 | -010001110 | ................................ . . . . ... 1 . . . . .. .1 .1 .1 1 1 . . . .......... ... . | +-- 267 | 11-0001110 | ................................ . . . . ... 1 . . . . 11 .. .1 .. . . . . . .......... ... . | +-- 268 | 0-11001110 | .1.1.1....1...1.1....1....11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 269 | 01-1001110 | .11111.............1......111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 270 | 0000101110 | .1.1.1...1....1..1........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 271 | 10-0101110 | .1.1......1...1..1...1....1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 272 | 0-11101110 | ...1.1....1...11...1..1....1.1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 273 | -1-1101110 | .1111.....1....1..11111...1..1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 274 | 11--101110 | ...11....1....1.11............1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 275 | 1101-01110 | .1.1.....1....1.1....1....1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 276 | 011--01110 | .1...1...11...1...........11.11. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 277 | 11-0011110 | .1111....1....1..1...1.1111..1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 278 | --11011110 | .....1....1....1........11.1.... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 279 | -01-011110 | ................................ . . . . ... 1 1 . 1 . .. .. .1 .. . . . . . .......... ... 1 | +-- 280 | -1-1111110 | .1.1.1........1.1111111..111..1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 281 | -0--111110 | ..111..........................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 282 | 11--111110 | .1.1.1...1....1..1........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 283 | 0000-11110 | ..........1.....11111111111111.. . . . . ... 1 . . . . .. .1 .. .. . . . . . .......... ... . | +-- 284 | 0100-11110 | .11111...1.....1...11.....111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 285 | -010-11110 | .1...1...1.............11.1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 286 | 0001-11110 | .1.......1....1.11............1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 287 | 10-1-11110 | .1.1.1........1..1........1111.. . . . . ... . . . . . .1 .. .. .. . . . . . .......... ... . | +-- 288 | 11-1-11110 | ..111..........................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 289 | -1---11110 | ................................ . . . . ... . 1 . . . .. .. .. .. . . . . . 11..1111.. ... . | +-- 290 | 01-01-1110 | ...111.............1......111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 291 | 00011-1110 | ................................ . . . . ... . 1 . . . .. 11 .. .. . . . . . .......... ... . | +-- 292 | 00-11-1110 | .11.1....1...................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 293 | 1--11-1110 | .1.1.1...1....1..1........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 294 | 111-10-110 | 1..111........11........111111.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 295 | --10-0-110 | ..111........................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 296 | 000001-110 | 1..............................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 297 | 0-1011-110 | .1...1...1.............11.1.111. . . . . ... . 1 . 1 . .. .. .1 .. . . . . . .......... ... 1 | +-- 298 | -00111-110 | .1.1..........1......11...11111. . . . . ... . . 1 . . .. .. .. .. . . . 1 . .......... ... . | +-- 299 | 11011--110 | .1.1.....1.....1.....11...11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 300 | -1111--110 | ................................ . . . . ... 1 1 . 1 . .. .. .1 .. . . . . . .......... ... . | +-- 301 | 10--1--110 | ................................ . . . . ... 1 1 . . . .. .. .. .. . . . . 1 1...1..1.1 ... . | +-- 302 | 101----110 | .1.1.1...1....1..1........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 303 | -010000-10 | ................................ . . . . ... 1 . . . . .. .1 .. .. . . . . . .......... ... . | +-- 304 | 0000110-10 | ..111..........................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 305 | 10-0110-10 | .1.1.1...1....1..1........1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 306 | 100-110-10 | ................................ . . 1 . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 307 | --101-0-10 | ..111........................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 308 | 0000001-10 | .1...1.............11...1.1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 309 | 000-001-10 | ..111..........................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 310 | 11-0101-10 | ................................ . . 1 . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 311 | 111-101-10 | 1..111...1....11........111111.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 312 | 0000011-10 | .....1...............111..11.1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 313 | 00--011-10 | ..111........................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 314 | -001111-10 | ...............................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 315 | 101--11-10 | .1.1.....1....1.1....1....1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 316 | 00010-1-10 | ................................ . . 1 . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 317 | -0-100--10 | ................................ . . . . ... 1 1 . . . .. .. .. .. . . . . . 1..1..11.1 ... . | +-- 318 | 01---0--10 | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . . . .......... ... . | +-- 319 | 1-0111--10 | ...111...1.............11.1.111. . . . . ... . . . . . .. .. .1 .. . . . . 1 .......... ... . | +-- 320 | 00000---10 | ....1....1...................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 321 | 1--00000-0 | ................................ . . . . ... . . . . . .. .. .1 .1 1 1 . . . .......... ... . | +-- 322 | -0101000-0 | .1.......1....1.11............1. . . 1 . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 323 | 10-0-000-0 | ................................ . . . . ... . . . . . .. .1 .. .. . . . . . .......... ... . | +-- 324 | 10-10100-0 | ..111........................1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 325 | 01-10100-0 | .11111.............11.1....1.1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 326 | -01-0100-0 | ................................ . . . . ... . 1 . 1 . .. .. .. .. . . . . . .......... ... . | +-- 327 | 11-00-00-0 | ..111..........................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 328 | 1-011-00-0 | ................................ . . . . ... 1 1 . . . .. .. .. .. . . . . . 1..11..1.1 ... . | +-- 329 | -0-00010-0 | .................1.............. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 330 | 11-00010-0 | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . 1 . .......... ... . | +-- 331 | 000-0010-0 | .1.1......1...1.11..........111. . . . . ... 1 1 1 . . .. .. .. .. . . . 1 . .......... ... . | +-- 332 | 0000-010-0 | ..111..........................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 333 | 1--00110-0 | .11............................. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 334 | 0-010110-0 | ..111........................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 335 | 110-1110-0 | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . 1 . .......... ... . | +-- 336 | 10-000-0-0 | ................................ . . . . ... . . . . . .1 .. .1 .. . . . . . .......... ... . | +-- 337 | --110001-0 | ................................ . . . . ... 1 1 1 1 . .. .. .. .. . . . . . .......... ... . | +-- 338 | -10-0001-0 | ................................ . . . . ... 1 1 . 1 . .. .. .. .. . . . . . .......... ... . | +-- 339 | 1-1-0001-0 | 1..111....1..............1111.1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 340 | 10-01001-0 | ..111........................1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 341 | 01-11001-0 | ..111....1.....................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 342 | 10-1-001-0 | ..111........................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 343 | -0100101-0 | .................1.............. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 344 | 11-00101-0 | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . 1 . .......... ... . | +-- 345 | 11-0-011-0 | .11............................. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 346 | 1--11111-0 | ................................ . . . . ... . . 1 . . .1 .. .. .. . . . . . .......... ... . | +-- 347 | 10-1-111-0 | ..............................1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 348 | 101--111-0 | ...111.............1.1..11111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 349 | 0-101-11-0 | .1.......1....1.11............1. . . 1 . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 350 | -1111-11-0 | 1..111.........1..........1...1. . . . . ... . 1 1 1 . .1 .. .. .. . 1 . . . .......... ... . | +-- 351 | -1-010-1-0 | .11............................. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 352 | -01011-1-0 | ..111..........................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 353 | 011-1--1-0 | ...111.........1....1.11.1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 354 | 10-0000--0 | 1............................... . . . . ... . . . . . .1 .1 .1 .1 1 1 . . . .......... ... . | +-- 355 | -110110--0 | 1....1...1................1..... . . . . ... 1 . . . . .. .. 11 .. . . . . . .......... ... . | +-- 356 | 0000001--0 | ................................ . . . . ... 1 . 1 . . .. .1 .. .. . . . . . .......... ... 1 | +-- 357 | 10--001--0 | .11............................. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 358 | 1-1-011--0 | 1...11.........1..........1...1. . . . . ... . 1 1 1 . .1 .. .. .. . 1 . . . .......... ... . | +-- 359 | -001111--0 | 1..11....1...................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 360 | 10-00-1--0 | ....1........................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 361 | -100000001 | ..111.....1......1.1.1.1.1.1.1.1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 362 | 0001000001 | 1...1....1...................... . . . . ... . . . . . .. .. .1 .1 1 1 . . . .......... ... . | +-- 363 | 0-11000001 | ...............11....1.......... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 364 | 110-000001 | .1.1.1....1...1..1........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 365 | 011-000001 | .1111....1....1.....1111111..... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 366 | 0-11100001 | .11111...11...1.........11.1.... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 367 | 1-1-100001 | 1....1....1...............11..1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 368 | 0000-00001 | 1...1.....1..................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 369 | 11-0-00001 | .1111....1....1.11............1. . . 1 . ... . . . . . .. .. .. .. . . . 1 . .......... 1.. . | +-- 370 | 01-0010001 | .....1.........1................ . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 371 | 01-1010001 | .1111.........111....1........1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 372 | 000-010001 | .11111...1....1.....1.11.1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 373 | -000110001 | ................................ . . . . ... . 1 1 . . .. 11 .. .. . . . . . 1...1.1..1 ... . | +-- 374 | 01-0110001 | ..111.....1...............111111 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 375 | 00-1110001 | .1.1.1....1...1.1....1....11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 376 | -00-110001 | ................................ . 1 . 1 ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 377 | 110-110001 | .11.1.....1...1................. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 378 | -11-110001 | 1..111....................11..1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 379 | 1101-10001 | .11111...1.............11.1.111. . . 1 . ... . 1 . 1 . .. .. .1 .. . . . . . .......... ... . | +-- 380 | 10-1-10001 | ................................ . . . . ... . . 1 . . .1 .. .. .. . . . . . .......... ... . | +-- 381 | 011--10001 | .1111.....1........1..11.1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 382 | 1-1--10001 | .........1...................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 383 | 11-00-0001 | .1.1.1...1....1..1........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 384 | 1-1-0-0001 | 1..111....1...............1111.. . . . . ... 1 . 1 1 . .. 1. .. .. . . . . . .......... ... . | +-- 385 | 10011-0001 | .1.1.1...1....1..1........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 386 | 11011-0001 | ................................ 1 . . . ... . . . . . 1. .1 .. .. . . . . . .......... ... . | +-- 387 | 101---0001 | ...................1.1..11...... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 388 | --10001001 | .1111....1....1....11111..1..1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 389 | 11-1001001 | 1..11....1...................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 390 | ---1001001 | ................................ . 1 . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 391 | -01-001001 | .1.1.1....1...1.1....1....11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 392 | -000101001 | 1...1....1...................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 393 | -0-0101001 | ................................ . . . . ... 1 1 . . . .. .. .. .. . . . . 1 ..1......1 ... . | +-- 394 | 11-0101001 | .11111...1..............1.1.111. . . . . ... 1 . 1 . . .. .1 .. .. . . . . . .......... ... 1 | +-- 395 | 0001101001 | .11111...1....1.....1.11.1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 396 | 0-11101001 | ..111....11...11...........1.... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 397 | 01-1101001 | .1.1.1........1.1111111..111..1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 398 | 11-1101001 | ................................ . . . . ... 1 1 . 1 . .. .. .1 .. . . . . . .......... 1.. 1 | +-- 399 | 0100-01001 | .....1.........1................ . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 400 | 0----01001 | ................................ . . . . ... . 1 1 . . .. .. .. .. . . . . . ....1..11. ... . | +-- 401 | 11-0011001 | ..111.....1.....11111111111111.1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 402 | 0001011001 | 1...1....1...................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 403 | 01-1111001 | .11111...11...1...........11.11. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 404 | 1-0-111001 | .1.1.....1....1.1....1....1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 405 | 0000-11001 | .11111...1....1.....1.11.1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 406 | 0100-11001 | ..111.....1......1.1.1.1.1.1.1.1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 407 | --10-11001 | ................................ . . . . ... . . . . . .1 .. .. .. . . . . . .......... ... . | +-- 408 | 1101-11001 | .1111.....1....1.1.............. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 409 | 0-11-11001 | .11111.............1......11.... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 410 | 101--11001 | .1.1.1...1....1..1........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 411 | 10-01-1001 | ................................ . . 1 . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 412 | 11011-1001 | ................................ . . 1 . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 413 | 1-011-1001 | .11111...1.............11.1.111. . . . . ... . . . 1 . .. .. .1 .. . . . . . .......... ... . | +-- 414 | -01000-001 | .1.1..........1......11...11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 415 | 11-000-001 | .1.1.....1....1.1....1....1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 416 | 01-100-001 | .....1.........1................ . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 417 | 01-010-001 | .....1.........1................ . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 418 | 101--0-001 | .11111...1..............1.1.111. . . . . ... 1 . 1 . . .. .1 .. .. . . . . . .......... ... . | +-- 419 | 0-1101-001 | .11111.............1......11.... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 420 | 0-1011-001 | .1111.....1...1..1.............. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 421 | 00--11-001 | ................................ . . . . ... . 1 . . . .. .. .. .. . . . . . ....11.11. ... . | +-- 422 | 0100000101 | .1111.........1111111....1....1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 423 | 1101000101 | ................................ . . . . ... 1 . . . . .. .1 .1 .1 1 1 . . . .......... ... . | +-- 424 | 10-1000101 | .1.1......1...1..1...1....1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 425 | 01-1000101 | .11111...1.....1...11.....111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 426 | 000-000101 | .11111...1....1.....1.11.1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 427 | 011-000101 | .1.1.1........1.1111111..111..1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 428 | 1-1-000101 | 1..111..................1.1111.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 429 | 0100100101 | .11111...1.....1...11.....111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 430 | 11-0100101 | .11111.............1.1..1111111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 431 | 1--0100101 | ................................ . . . . ... . . . . . .1 .. .. .. . . . . . .......... ... . | +-- 432 | 0001100101 | .1...1..................1.1.111. . . . . ... . . 1 . . .. .1 .. .. . . . . . .......... ... 1 | +-- 433 | 0-11100101 | .1...1.........1........11.1.... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 434 | 01-1100101 | .1.......1....1......11111...11. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 435 | 1-1-100101 | 1....1...1.....1....1.....111.1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 436 | 10--100101 | ................................ . . 1 . ... . . . . . .1 .. .. .. . . . . 1 .......... ... . | +-- 437 | 11-0010101 | .1.1.....1....1.1....1....1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 438 | 0001010101 | .11111...1...........1111.11.1.. . . . . ... . 1 . . . .. 11 .. .. . . . . . .......... ... . | +-- 439 | -101010101 | .11111.............11.1....1.1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 440 | -01-010101 | .11111...11...11...1..1....1.1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 441 | 0000110101 | ...1.1..................1.1.111. . . . . ... 1 . 1 . . .. .1 .. .. . . . . . .......... ... 1 | +-- 442 | 01-1110101 | ..........1....1................ . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 443 | 110-110101 | .11111.........1......1....1.1.. 1 . . . ... . . . . . 1. .. .. .. . . . . . .......... ... . | +-- 444 | 1101-10101 | ................................ 1 . . . ... . . . . . 1. .1 .1 .. . . . . . .......... ... . | +-- 445 | 011--10101 | .11111...11...1...........11.11. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 446 | -0100-0101 | .11111...1.............11.1.111. . . . . ... . 1 . 1 . .. .. .1 .. . . . . . .......... ... 1 | +-- 447 | 1-1-0-0101 | ................................ . . . . ... 1 . . 1 . .. 1. 11 .. . . . . . .......... ... . | +-- 448 | 0-111-0101 | ..111.....1.....11.............. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 449 | --1-1-0101 | ................................ . . . . ... 1 1 . . . .. .. .. .. . . . . . ..1.11..11 ... . | +-- 450 | 101---0101 | ................................ . . 1 . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 451 | 0100001101 | .11111...1.....1...11.....111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 452 | 11-0001101 | ................................ 1 . . . ... . . . . . 1. .1 .1 .1 1 1 . . . .......... ... . | +-- 453 | 0001001101 | .11111...1..............1.1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 454 | 01-1001101 | .11111.............11.1....1.1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 455 | 01-0101101 | .11111.............11.1....1.1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 456 | 11-0101101 | .11111...1....1.....1.11.1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 457 | 0-11101101 | .1.1.1...1....1......111..111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 458 | 01-1101101 | .1111.....1....1....1111111..... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 459 | -010-01101 | ................................ . . . . ... . . . . . .1 .. .. .. . . . . . .......... ... . | +-- 460 | 011--01101 | .11111.............1..11.1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 461 | --11011101 | ...............1..........1...1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 462 | 11--011101 | ................................ . . 1 . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 463 | -1-1111101 | .1111................11...1...1. . . . . ... . . . . . .1 .. .. .. . . . . . .......... ... . | +-- 464 | 1-0-111101 | ..111..........................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 465 | 0000-11101 | ................................ . . . . ... . 1 . . . .. 11 .. .. . . . . . .......... ... . | +-- 466 | 0100-11101 | .1111.........1111111....1....1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 467 | 0001-11101 | .11111...1....1.....1.11.1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 468 | 1001-11101 | ..111........................1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 469 | -0-1-11101 | ................................ . . . 1 ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 470 | 11-1-11101 | 1..11....1...................... . . . . ... . . . . . .. .. .1 .1 1 1 . . . .......... ... . | +-- 471 | 11-00-1101 | ..111..........................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 472 | 0-1100-101 | ..111.....1.....1111............ . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 473 | 000010-101 | .11111...1....1.....1.11.1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 474 | 000110-101 | ..111....1.....1................ . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 475 | 101--0-101 | .11111...1....1.....1.11.1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 476 | 01---0-101 | ................................ . . . . ... 1 1 . . . .. .. .. .. . . . . . .......... ... . | +-- 477 | -00001-101 | 1...1.....1..................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 478 | -01001-101 | .1.1.1...1....1..1........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 479 | -1001--101 | ................................ . . . . ... . 1 1 . . .. .. .. .. . . . . . 11..1...1. ... . | +-- 480 | 11011--101 | .1........1....1.1.............. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 481 | 011-1--101 | .1.1.1....1.....11....1...11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 482 | 11-0000-01 | .1.1.1...1....1..1........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 483 | -010100-01 | .1111.....1...1..1.............. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 484 | 10-1100-01 | .1.1.1........1..1........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 485 | -010010-01 | .1.1.1...1....1..1........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 486 | 0--0010-01 | ................................ . . . . ... 1 1 . . . .. .. .. .. . . . . . ..1...1111 ... . | +-- 487 | 10-1010-01 | ................................ . . 1 . ... 1 . . . . .1 .. .. .. . . . . 1 .......... ... . | +-- 488 | 10-0110-01 | ...1.1........1.....1.11.1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 489 | 0001110-01 | ................................ . . . . ... . . . . . .. .. .. .. . . . 1 . .......... ... . | +-- 490 | 01-1110-01 | .11111.............1..11.1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 491 | 0000001-01 | ..111....11....................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 492 | 0001001-01 | ................................ . . . . ... . . . . . .. .1 .. .. . . . . . .......... ... . | +-- 493 | 10-1001-01 | .1.1.1...1....1..1........1.111. . . 1 . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 494 | -1-0-01-01 | ................................ . . . 1 ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 495 | -001111-01 | .1.1.1...1....1..1........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 496 | 100-111-01 | .....1..................1.1.111. . . 1 . ... 1 . . . . .. .. .1 .. . . . . 1 .......... ... . | +-- 497 | 011--11-01 | .1111................11...1..... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 498 | -0101-1-01 | .1111....1....1..1.............. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 499 | -00011--01 | .11.1....1...................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 500 | 00000---01 | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . . . .......... ... . | +-- 501 | -0011---01 | ................................ . . . . ... 1 . . . . .. .. .. .. . . . . . ...1...... ... . | +-- 502 | 0-------01 | ................................ . . . 1 ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 503 | 0100000011 | .1111.....1...1......11111...11. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 504 | -010000011 | .1...1...1.............11.1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 505 | 1101000011 | .1.1.....1....1.1....1....1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 506 | 011-000011 | .11111....1....1...1..11.1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 507 | 1-1-000011 | .........11.........1....1..1... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 508 | -010100011 | .1111.....1....1.1.............. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 509 | 1--0100011 | .1.1.....1.....1.....11...11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 510 | 0-11100011 | .11111.............1.1....11.11. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 511 | 0000-00011 | .1.1......1...1..1...1....1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 512 | 10-1-00011 | .1...1....1.............1.1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 513 | 10---00011 | ................................ . . . . ... . . . . . .. .. .1 .. . . . . . .......... ... . | +-- 514 | --00010011 | .11..1................1....1.... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 515 | -010010011 | ................................ . . . . ... . . . . . .. .. .. .1 1 . . . . .......... ... . | +-- 516 | -0-0010011 | ..111........................1.. 1 . . . ... . . 1 . . 1. .1 .. .. . . . . . .......... ... . | +-- 517 | 1--0010011 | ...11....1....1.....1..1.11.1... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 518 | 10--010011 | ................................ 1 . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 519 | 00-1110011 | .11111...11...11...1..1....1.1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 520 | 01-1110011 | ...11....1....1.....1111111..... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 521 | 0001-10011 | .1.1.....1....1.1....1....1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 522 | 1101-10011 | .1.1.1...1....1..1........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 523 | 011--10011 | .1.1.1........1.1111111..111..1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 524 | -0100-0011 | ................................ . . . . ... . . . 1 . .. .1 .1 .. . . . . . .......... ... 1 | +-- 525 | 0-110-0011 | .1.1.1....1...1.1....1....11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 526 | 11--0-0011 | ................................ . . . . ... 1 1 1 1 . .. .. .. .. . . . . . 11...1.... ... . | +-- 527 | 10-01-0011 | 1...1.....1..................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 528 | 00011-0011 | ................................ 1 . . . ... . . . . . 1. .1 .1 .1 1 . . . . .......... ... . | +-- 529 | 101---0011 | ................................ . . . . ... . . . . . 11 .. .1 .. . . . . . .......... ... . | +-- 530 | 1--0001011 | .1...1.............1.1..111111.. . . . . ... . . 1 . . .1 .. .. .. . . . . . .......... ... . | +-- 531 | 1101001011 | .1...1....1..........1.1111111.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 532 | 00-1001011 | .11111...11...11...1..1....1.1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 533 | 11-1001011 | ................................ . . . . ... . . . . . .. .. 1. .. . . . . . .......... ... . | +-- 534 | 0000101011 | .1.1.1...1....1..1........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 535 | 11-0101011 | .1.......1....1..1...1.1111..1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 536 | -001101011 | .1...............1.............. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 537 | 01-1101011 | .1............11................ . . . . ... . . . . . 1. .. .. .. . . . . . .......... ... . | +-- 538 | 0-1-101011 | ..111.....1.....11111111........ . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 539 | 0100-01011 | .1...1....1...1....1..11.1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 540 | 011--01011 | .1..............1....11...1...1. . . . . ... . . . . . .1 .. .. .. . . . . . .......... ... . | +-- 541 | 1--0011011 | ................................ . . . . ... . . . . . .. .. .1 .1 1 1 . . . .......... ... . | +-- 542 | --11011011 | .11111........1....11....1.1.... 1 . . . ... . . 1 . . 1. .. .. .. . 1 . . . .......... ... . | +-- 543 | 0---011011 | ................................ . . . . ... . 1 . . . .. .. .. .. . . . . . .......... ... . | +-- 544 | -1-1111011 | .1.......1....1...1.111.1.1..1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 545 | 0100-11011 | .1........1...1......11111...11. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 546 | -010-11011 | .11111...1.............11.1.111. . . 1 . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 547 | 11-0-11011 | ................................ . . . . ... 1 . . . . .. .1 .. .. . . . . . .......... ... . | +-- 548 | 11-1-11011 | .1........1...1..1.............. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 549 | 00010-1011 | .1111....1....1..1...1.1111..1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 550 | --101-1011 | ................................ 1 . . . ... . . . . . 1. .1 .1 .1 1 . . . . .......... ... . | +-- 551 | -1----1011 | ..111........................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 552 | 000100-011 | .1.1.1...1....1..1........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 553 | 01-100-011 | .11111....1...1....1..11.1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 554 | 010010-011 | .11111....1...1....1..11.1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 555 | 10-110-011 | .1.1.1...1....1..1........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 556 | -00001-011 | ................................ 1 . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 557 | 1-1-01-011 | 1...11....1.............11111.1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 558 | 000011-011 | .1.1.....1....1.1....1....1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 559 | --1011-011 | .11111...1.............11.1.111. . . 1 . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 560 | 000111-011 | ................................ 1 . . . ... . . . . . 1. .1 .1 .1 1 1 . . . .......... ... . | +-- 561 | -010-1-011 | ................................ . . . . ... . . . 1 . .. .. .1 .. . 1 . . . .......... ... 1 | +-- 562 | 00011--011 | ..111.....1....1................ . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 563 | 011-1--011 | .1.1.1....1.....111....1..11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 564 | 111-1--011 | 1..111.........1....1...1.1111.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 565 | -1-1---011 | ................................ . . . 1 ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 566 | -010000111 | .11111................1....1.1.. . . . . ... . 1 . . . 1. .. .1 .. . . . . . .......... ... . | +-- 567 | -0-0000111 | ................................ 1 . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 568 | 11-0000111 | .1...1...1....1.....1.11.1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 569 | 0001000111 | .1.1.....1....1.1....1....1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 570 | 0-11000111 | .11111.............1.1....11.... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 571 | 011-000111 | .11111...11...1...........11.11. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 572 | -010100111 | 1..11....1...................... . . 1 . ... . . . 1 . .. .. .1 .1 1 . . . . .......... 1.. . | +-- 573 | 11-0100111 | ................................ . . . . ... . . . . . 1. .1 .1 .1 1 1 . . . .......... ... . | +-- 574 | 1--0100111 | ................................ 1 . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 575 | 0001100111 | .1111....1....1..1...1.1111..1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 576 | 0-11100111 | .1.1.1...1....1......11.1111.11. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 577 | 01-1100111 | .1...1.............1......111... 1 . . . ... . 1 1 . . .. .1 .. .. . . . . . .......... ... . | +-- 578 | -000-00111 | ................................ 1 . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 579 | 0-00010111 | .1.1......1...1..1...1....1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 580 | 1--0010111 | .11111.............1.1..111111.. . . . . ... . . 1 . . .1 .. .. .. . . . . . .......... ... . | +-- 581 | 0-01010111 | .11111.........1......1....1.1.. 1 . . . ... . 1 1 . . 1. .. .. .. . . . . . .......... ... . | +-- 582 | 0-11010111 | .1.1.1.........11..1..111.11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 583 | 110-110111 | .1.1.1....1...1..1........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 584 | 010--10111 | .1.1.1........1.1111111..111..1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 585 | 01000-0111 | ...1.1.........1.........1.1.... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 586 | 01-10-0111 | .11111..............1.1....1.1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 587 | 01001-0111 | ...1.1..............1.1....1.1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 588 | -000001111 | .1.1......1...1..1...1....1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 589 | 0100001111 | .11111..............1.1....1.1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 590 | -010001111 | 1..11....1...................... . . 1 . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 591 | 1--0001111 | .1...1...1..............1.1.111. . . . . ... 1 . 1 . . .. .1 .. .. . . . . . .......... ... . | +-- 592 | --11001111 | .1.1.1...1....1......111.1111.1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 593 | 10--001111 | .11.1....1...................... 1 . . . ... . 1 . . . .. 11 .. .. . . . . . .......... ... . | +-- 594 | 0---001111 | ................................ . . . . ... 1 1 . 1 . .. .. .. .. . . . . . .......... ... . | +-- 595 | 0000101111 | .1.1.....1....1.1....1....1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 596 | 01-0101111 | .1111.........1111....1.......1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 597 | 0001101111 | ..111.....1.....1111111111111..1 . . . . ... 1 . . . . .. .1 .. .. . . . . . .......... ... . | +-- 598 | -1-1101111 | .1111...........1....11...1..... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 599 | 11--101111 | .1........1....1.1.............. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 600 | 11-1-01111 | .1.1......1...1.1...........111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 601 | -0-0011111 | ..111........................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 602 | 1--0011111 | 1...1.....1..................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 603 | 0-01011111 | .1111.....1....1.1.............. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 604 | 00-0111111 | .11111.........1......1....1.1.. 1 . . . ... . 1 1 . . 1. .. .. .. . . . . . .......... ... . | +-- 605 | -0-1111111 | ................................ . . . . ... . . . . . .1 .. .. .. . . . . . .......... ... . | +-- 606 | 11--111111 | .11111...1.............11.1.111. 1 . . . ... . . . . . .. .. .1 .. . . . . . .......... ... . | +-- 607 | --10-11111 | .1...1................1....1.1.. 1 . . . ... . . . . . 1. .1 .1 .. . . . . . .......... ... . | +-- 608 | 10-0-11111 | .1.1.1...1....1.11........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 609 | --11-11111 | ..........1...1...........1...1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 610 | 10-1-11111 | 1..11....1...................... . . 1 . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 611 | 01-1-11111 | .11111.............1..11.1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 612 | 11-1-11111 | .1111....1....1..1.............. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 613 | 01-10-1111 | .1111.........1111....1.......1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 614 | --101-1111 | .1111.....1....1.1.............. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 615 | 1-011-1111 | .11111...1.............11.1.111. . . . . ... . . . . . .. .. .1 .. . . . . . .......... ... . | +-- 616 | 0-111-1111 | .11111.............1......11.... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 617 | -11---1111 | .1111....1....1.....1111111..... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 618 | 1-1---1111 | .1.1.....1....1.1....1....1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 619 | 111-10-111 | 1....1....1........11...1.111.1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 620 | 11-0-0-111 | ..111........................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 621 | 0-1011-111 | ................................ . . . . ... . . . . . 1. .1 .1 .. . . . . . .......... ... . | +-- 622 | --1011-111 | ................................ 1 . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 623 | 0-1111-111 | .1.1.....1....1......1.11.1.1... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 624 | -10-11-111 | ................................ . . . . ... 1 1 . . . .. .. .. .. . . . . . .......... ... . | +-- 625 | 0-1-11-111 | .....1................1....1.1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 626 | 0100-1-111 | .11111.........1.........1.1.... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 627 | 101--1-111 | .11111....1.............1.1.111. . . . . ... . . 1 . . .. .1 .. .. . . . . . .......... ... . | +-- 628 | 011--1-111 | .1111....1....1.....11111.1..1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 629 | 011-1--111 | .1.1.1....1.....1....1....11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 630 | -1--000-11 | ................................ . . . . ... 1 1 . 1 . .. .. .. .. . . . . . .......... ... . | +-- 631 | --1-100-11 | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . . . .......... ... . | +-- 632 | 01-1010-11 | ..111.....1..............1111111 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 633 | 0000110-11 | .1.1.1...1....1..1........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 634 | 0001110-11 | ................................ . . . . ... . . . . . .. .1 .1 .1 1 1 . . . .......... ... . | +-- 635 | -001110-11 | ..111..........................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 636 | 0100-10-11 | ...111....1...1....1..11.1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 637 | 11011-0-11 | .1........1...1..1.............. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 638 | -1-0--0-11 | ................................ . . . 1 ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 639 | 0001001-11 | .1.1.1...1....1..1........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 640 | 01-1101-11 | ................................ . . . . ... 1 . . . . .1 .. .. .. . . . . . .......... ... . | +-- 641 | 10-0-01-11 | ....1.....1....................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 642 | 0-1-111-11 | .1.1.1....1...1.11111....111111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 643 | -11--11-11 | .1...1.............1..11.1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 644 | 1-1--11-11 | .1.1......1...1.11..........111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 645 | -1110-1-11 | .........1..............1....... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 646 | 11011-1-11 | .1.......1....1..1.............. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 647 | -1-1--1-11 | ................................ . . . 1 ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 648 | 11-111--11 | ................................ . . . . ... . . . . . .. .. .1 .. . . . . . .......... ... . | +-- 649 | -11-11--11 | ..............1..........1...... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 650 | -1--11--11 | ................................ . 1 . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 651 | 10---1--11 | ................................ . . . . ... 1 . . . . .. .. .. .. . . . . . .......1.. ... . | +-- 652 | 1-10----11 | ................................ . . . . ... . 1 1 . 1 .1 .. .. .1 1 1 . . . .......... ... . | +-- 653 | 11-00000-1 | 1...1....1...................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 654 | 10--0000-1 | ..111..........................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 655 | 01-11000-1 | .1...1....1...........1..1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 656 | ---11000-1 | ................................ . . . 1 ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 657 | 10-10100-1 | 1..1............................ . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 658 | 10--0100-1 | ................................ . . . . ... . . . . . .1 .. .. .. . . . . . .......... ... . | +-- 659 | 00011-00-1 | ..111....1.....1................ . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 660 | 101---00-1 | .11111....................111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 661 | -0000010-1 | ................................ . . . . ... . . . . . 1. .. .1 .. . . . . . .......... ... . | +-- 662 | -0100010-1 | ................................ . . . . ... . . . . . .. .. .. .. . . . 1 . .......... ... . | +-- 663 | 00010010-1 | .11111...1...........1111.11.1.. 1 . . . ... . . . . . .. 1. .. .. . . . . . .......... ... . | +-- 664 | 111-1010-1 | 1..111.........1.........11111.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 665 | 11-00110-1 | ................................ . . . . ... 1 . . . . .. .1 .. .. . . . . . .......... ... . | +-- 666 | 1001-110-1 | .1.1.1...1....1..1........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 667 | 101--110-1 | ................................ . . . . ... . . . . . .. .. .. .. . . . 1 . .......... ... . | +-- 668 | 10-000-0-1 | ..111........................... 1 . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 669 | --0100-0-1 | ................................ . . . . ... . 1 . . . .. .. .. .. . . . . . .......... ... . | +-- 670 | 1--100-0-1 | ................................ . . . . ... 1 . . 1 . .. .. .. .. . . . . . .......... ... . | +-- 671 | 0-0010-0-1 | ................................ . . . . ... 1 1 . . . .. .. .. .. . . . . . .......... ... . | +-- 672 | -00101-0-1 | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . . . ...1..111. ... . | +-- 673 | 0-1-11-0-1 | ................................ . . . . ... 1 1 . . . .. .. .. .. . . . . . .......... 1.. . | +-- 674 | -1-00001-1 | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . . . 11.....1.. ... . | +-- 675 | 11010001-1 | ..111..........................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 676 | --1-0001-1 | ................................ . 1 . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 677 | -0100101-1 | ................................ . . . . ... . . . . . .. .. .. .. . . . 1 . .......... ... . | +-- 678 | 10-10101-1 | .1.1.1...1....1..1........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 679 | 100-1101-1 | .11............................. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 680 | 1-0-1101-1 | ................................ . . . 1 ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 681 | 0100-101-1 | .11111.............11.1....1.1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 682 | 1101-101-1 | .1111.....1...1..1.............. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 683 | 0--10-01-1 | ................................ . 1 . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 684 | 11010011-1 | ................................ . . . . ... . . . . . .. .. .. .. . . . 1 . .......... ... . | +-- 685 | 10-01011-1 | ....1.....1...................1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 686 | -----011-1 | ................................ . . . . ..1 . . . . . .. .. .. .. . . . . . .......... ... . | +-- 687 | 10-00111-1 | .11...........................1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 688 | ---10111-1 | ................................ . . . . ... 1 1 . . . .. .. .. .. . . . . . ...1.1.... ... . | +-- 689 | ---01111-1 | ................................ . 1 . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 690 | 1--11111-1 | ................................ 1 . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 691 | 0-1-1111-1 | ..111....11...11..............1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 692 | 1-0--111-1 | ................................ . . . . ... . 1 . 1 . .. .. .. .. . . . . . 1......1.1 1.. . | +-- 693 | -11--111-1 | .........1....1.....1..111...... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 694 | 10-00-11-1 | 1...1........................... . . . . ... . 1 . . . .1 .. .. .. . . . . . .......... ... . | +-- 695 | -1110-11-1 | 1..111.........1..........1...1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 696 | 0-0-0-11-1 | ................................ . . . . ... 1 . 1 . . .. .. .. .. . . . . . ......1.1. ... . | +-- 697 | 1-1-0-11-1 | ................................ . . . . ... . 1 1 1 . .1 .. .. .. . 1 . . . .......... ... . | +-- 698 | 11011-11-1 | .....1................1....1.1.. . . . . ... . . . . . 1. .1 .1 .. . . . . . .......... ... . | +-- 699 | 11-11-11-1 | ................................ 1 . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 700 | -011-0-1-1 | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . . . 1.111.1.1. ... . | +-- 701 | 1-1--0-1-1 | ................................ . . . 1 ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 702 | 1-1-01-1-1 | 1...11...................11111.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 703 | 0-1011-1-1 | .1111....1....1..1.............. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 704 | 1-0111-1-1 | ................................ 1 . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 705 | 11-111-1-1 | .........1..............1....... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 706 | 10-0000--1 | ...11........................... 1 . . . ... . . . . . 1. .1 .1 .1 1 1 . . . .......... ... . | +-- 707 | 0--1000--1 | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . . . ...1....1. ... . | +-- 708 | 10-0100--1 | ................................ . . . . ... . 1 . . . .1 .. .. .. . . . . . .......... ... . | +-- 709 | -1-1100--1 | ..111........................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 710 | -1-0010--1 | ................................ . . . . ... . 1 . . . .. .. .. .. . . . . . .......... ... . | +-- 711 | 10-00-0--1 | ..1............................. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 712 | -1111-0--1 | ................................ . . . . ... 1 1 . 1 . .. .. .. .. . . . . . .......... ... . | +-- 713 | 01-1011--1 | .11111....1...........1..1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 714 | 1-1-011--1 | ................................ 1 . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 715 | 11-1111--1 | ................................ . . . . ... . 1 1 1 . .1 .. .. .. . 1 . . . .......... ... . | +-- 716 | -11-111--1 | 1...11.........1..........1...1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 717 | 011-1-1--1 | .1111.....1............1..1..... . . . . ... . . . . . .. .1 .1 .. . . 1 . . .......... ... . | +-- 718 | 1-10--1--1 | ................................ 1 . . . ... . . 1 . 1 .1 .1 .. .1 1 1 . . . .......... ... . | +-- 719 | 10-010---1 | 1............................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 720 | 10-001---1 | 1............................... . . . . ... . 1 . . . .1 .. .. .. . . . . . .......... ... . | +-- 721 | 1-10-----1 | 1..111....1.........1.....1..... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 722 | 0-1100000- | .1.1.1....................11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 723 | 01-100000- | ..111.....1.......11..11..11..11 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 724 | 010010000- | ..111.....1.......11..11..11..11 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 725 | 000110000- | ................................ . . . . ... . 1 1 . . .. .. .. .. . . . 1 . ...1.1.11. ... . | +-- 726 | 01-110000- | ................................ . . . . ... . . . . . .1 .. .. .. . . . . . .......... ... . | +-- 727 | -010-0000- | ................................ . . . . ... 1 . . . . .1 .. .. .. . . . . . .......... ... . | +-- 728 | 010001000- | ..111.....1.........1111....1111 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 729 | 11011-000- | ................................ . . . . ... . . . . . .. .. .1 .1 1 1 . . . .......... ... . | +-- 730 | 1--11-000- | ................................ . 1 . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 731 | 011-1-000- | .1.1.1.........1.............11. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 732 | 11-0--000- | ................................ . . . . ... 1 1 . . . .. .. .. .. . . . . . 11.....1.. ... . | +-- 733 | 0-0000100- | ..111.....1.......11..11..11..11 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 734 | -0-000100- | ................................ . . . . ... . . . . . .. .1 .. .1 1 . . . . .......... ... . | +-- 735 | 01-100100- | ..111.....1.........1111....1111 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 736 | 1-1-00100- | 1..111....1........1....11111.1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 737 | --1-00100- | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . . . .......... ... . | +-- 738 | 010010100- | ..111.....1.........1111....1111 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 739 | 0-1101100- | ..........1...1..........1..1... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 740 | 01-101100- | ................................ . . . . ... . . . . . .1 .. .. .. . . . . . .......... ... . | +-- 741 | 100-11100- | .11.1....1...................... 1 . . . ... . 1 . . . .. 1. .. .. . . . . . .......... ... . | +-- 742 | 1--0-1100- | ................................ . 1 . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 743 | -011-1100- | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . . . 1.1111.1.1 ... . | +-- 744 | -0100-100- | .1.1..........1.1...........111. . . . . ... 1 . 1 . . .. .. .. .. . . . 1 . .......... ... . | +-- 745 | -01000-00- | ................................ . . . . ... . . 1 . . .. .. .. .. . . . 1 . .......... ... . | +-- 746 | 11-000-00- | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . 1 . .......... ... . | +-- 747 | 000001-00- | ................................ . . . . ... 1 1 . . . .. .. .. .. . . . 1 . .......... ... . | +-- 748 | 0-1011-00- | ................................ . . . . ... . . . . . .. .. .. .. . . . 1 . ..1.1.111. ... . | +-- 749 | 0--111-00- | ................................ . . . . ... . 1 . 1 . .. .. .. .. . . . . . .......... ... . | +-- 750 | 110-11-00- | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . 1 . ....1.1.1. ... . | +-- 751 | --1-11-00- | ................................ . . . 1 ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 752 | ---0---00- | ................................ . . . . 1.1 . . . . . .. .. .. .. . . . . . .......... ... . | +-- 753 | 0-1100010- | .1...1...1....1.........11.1.... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 754 | 00-010010- | ................................ . . . . ... . . 1 . . .. .. .. .. . . . 1 . ..1.1...1. ... . | +-- 755 | 0000-0010- | ................................ . . . . ... 1 1 . . . .. .. .. .. . . . 1 . .......... ... . | +-- 756 | 11-001010- | ................................ . . . . ... 1 . 1 . . .. .. .. .. . . . 1 . .......... ... . | +-- 757 | -1-1-1010- | ................................ . 1 . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 758 | -1111-010- | ................................ . . . . ... . 1 1 1 . .. .. .. .. . . . . . .......... ... . | +-- 759 | 101---010- | ..111..........................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 760 | 1--000110- | ................................ . 1 . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 761 | 110100110- | .1.1.1....1...1...........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 762 | -00-10110- | ................................ . . . . ... . 1 . . . .. .. .. .. . . . . . ....1...1. ... . | +-- 763 | 01---0110- | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . . . .......... ... . | +-- 764 | 0--001110- | ................................ . . . . ... 1 1 . . . .. .. .. .. . . . . . ..1..11.11 ... . | +-- 765 | 00011-110- | ................................ . . . . ... . . 1 . . .. .. .. .. . . . 1 . ...1...... ... . | +-- 766 | 10011-110- | ..111..........................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 767 | 10-100-10- | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . . . ...1..1... ... . | +-- 768 | ----01-10- | ................................ . . . . 1.1 . . . . . .. .. .. .. . . . . . .......... ... . | +-- 769 | 000111-10- | .1.1.1........1.1...........111. . . . . ... . . . . . .1 .. .. .. . . . . . .......... ... . | +-- 770 | 11-111-10- | 1...11....1........11...1.111.1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 771 | 01-0-1-10- | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . . . .......... ... . | +-- 772 | -1-0-00-0- | ................................ . . . . ... . . 1 . . .. .. .. .. . . . . . .....1...1 ... . | +-- 773 | -110110-0- | ................................ . . . . ... . . . . . .. .. .1 .. . . . . . .......... ... . | +-- 774 | 01-1-10-0- | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . . . .......... ... . | +-- 775 | 0-0-1-0-0- | ................................ . . . 1 ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 776 | -010001-0- | .1.1..........1.1...........111. . . . . ... 1 . 1 . . .. .. .. .. . . . 1 . .......... ... . | +-- 777 | 1101001-0- | ................................ . . . . ... 1 1 . . . .. .. .. .. . . . . . 11.1...11. ... . | +-- 778 | 10-10-1-0- | ................................ . . . . ... . 1 1 1 . .. .. .. .. . . . . 1 1........1 ... . | +-- 779 | --0111--0- | ................................ . . . 1 ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 780 | 0-111---0- | ................................ . . . . ... 1 1 . . . .. .. .. .. . . . . . .......... ... . | +-- 781 | -01000001- | ..111..........................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 782 | 110100001- | ................................ . . . . ... 1 1 . . . .. .. .. .. . . . 1 . .......... ... . | +-- 783 | -01010001- | ................................ . . . . ... 1 1 . . . .. .. .. .. . . . 1 . .......... 1.1 . | +-- 784 | 11-010001- | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . 1 . 11..1....1 ... . | +-- 785 | 10--10001- | ................................ 1 . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 786 | 0-00-0001- | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . . . .......... ... . | +-- 787 | -0-1-0001- | ................................ . 1 . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 788 | -0-001001- | ................................ . 1 . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 789 | -0--01001- | ................................ . . . 1 ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 790 | 000-11001- | ................................ 1 . . . ... . . . . . 1. .1 .1 .1 1 1 . . . .......... ... . | +-- 791 | -1--11001- | .11............................. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 792 | 0001-1001- | ................................ . . . . ... . . . . . .. .. .. .. . . . 1 . .......... ... . | +-- 793 | -1-11-001- | ................................ . . . . ... 1 1 . . . .. .. .. .. . . . . . .......... ... . | +-- 794 | -00100101- | ..111..........................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 795 | 0001-0101- | ................................ . . . . ... 1 1 . . . .. .. .. .. . . . 1 . .......... 1.. . | +-- 796 | 00-011101- | ................................ . . . . ... . 1 . . . .. .. .. .. . . . 1 . .......... ... . | +-- 797 | 100-11101- | ..111....1...................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 798 | 1-1-0-101- | 1..111...................11111.. . . . . ... 1 . . 1 . .. 1. 11 .. . . . . . .......... ... . | +-- 799 | -1--0-101- | ................................ . . . 1 ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 800 | --1-1-101- | ................................ . 1 . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 801 | -00001-01- | .11.1........................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 802 | 0-0001-01- | ................................ . 1 . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 803 | ---111-01- | ................................ . 1 . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 804 | 000100011- | ................................ . . . . ... . . . . . .. .. .. .. . . . 1 . .......... ... . | +-- 805 | 01-110011- | ..............1................. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 806 | 0000-0011- | ................................ . . . . ... . 1 . . . .. .1 .. .. . . . . . .......... ... . | +-- 807 | -000-0011- | ................................ . 1 . 1 ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 808 | 0-00-0011- | .11.1........................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 809 | 10-1-0011- | ..111..........................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 810 | -0-1-0011- | ................................ . . . . ... 1 1 . . . .. .. .. .. . . . . . .......... 1.. . | +-- 811 | 01-101011- | .11111..............1.....111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 812 | 0000-1011- | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . . . .......... ... . | +-- 813 | 0100-1011- | .11111.............1......111... 1 . . . ... . . 1 . . .. .1 .. .. . . . . . .......... ... . | +-- 814 | -1-01-011- | ................................ . 1 . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 815 | -1--1-011- | ................................ . . . 1 ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 816 | 1---00111- | ................................ . . . 1 ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 817 | 00-010111- | ................................ . . . . ... . 1 . . . .. .. .. .. . . . 1 . .......... 1.1 . | +-- 818 | ---110111- | ................................ . 1 . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 819 | 11--10111- | ................................ . . . . ... . . . . . .. .. .. .. . . . 1 . .......... ... . | +-- 820 | 1101-0111- | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . 1 . .......... ... . | +-- 821 | 000101111- | ................................ . . . . ... 1 1 . . . .. .. .. .. . . . 1 . .......... 1.. . | +-- 822 | 01-101111- | .1111................111111..... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 823 | --1-11111- | .....1........1....11....1.1.... 1 . . . ... . 1 1 . . 1. .. .. .. . 1 . . . .......... ... . | +-- 824 | -11--1111- | .11111....1........1..11.1111... 1 . . . ... . . . . . .. .1 .. .. . . . . . .......... ... . | +-- 825 | --1--1111- | ................................ . 1 . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 826 | -111--111- | ................................ 1 . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 827 | 101--0-11- | ................................ . . . . ... . . . . . .. .. .. .. . . . 1 . .......... ... . | +-- 828 | 01-101-11- | ................................ 1 . . . ... . 1 1 . . .. .1 .. .. . . . . . .......... ... . | +-- 829 | 1-1-01-11- | ................................ . . . . ... . . . . . .. 1. 11 .. . . . . . .......... ... . | +-- 830 | --1-11-11- | ................................ . 1 . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 831 | ---0-1-11- | ................................ . . . . ..1 . . . . . .. .. .. .. . . . . . .......... ... . | +-- 832 | -111-1-11- | 1...11.........1.........11111.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 833 | 1--1-1-11- | ................................ . . . . ... 1 . . 1 . .. .. .. .. . . . . . .1....1... ... . | +-- 834 | 1-1-000-1- | 1..111.........1..........11..1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 835 | 10-0110-1- | ................................ . . . . ... 1 1 . . . .. .. .. .. . . . . . .......... ... . | +-- 836 | 1-01-10-1- | ................................ . . . . ... . 1 . . . .. .. .. .. . . . . . ...1.....1 ... . | +-- 837 | 1-0-101-1- | ................................ . . . . ... 1 1 . 1 . .. .. .. .. . . . . . 11.11.1..1 1.. . | +-- 838 | 111-101-1- | ................................ . . . . ... 1 1 . 1 . .. .. .1 .. . . . . . .......... ... . | +-- 839 | -----01-1- | ................................ . . . . .11 . . . . . .. .. .. .. . . . . . .......... ... . | +-- 840 | -000011-1- | ................................ . . . . ... . . . . . .. .1 .. .. . . . . . .......... ... . | +-- 841 | 11-1111-1- | ................................ 1 . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 842 | 101--11-1- | ................................ . . . . ... . 1 1 . . .. .. .. .. . . . 1 . .......... ... . | +-- 843 | 01---11-1- | ................................ . . . . ... . 1 1 . . .. .. .. .. . . . . . .......... ... . | +-- 844 | 10-00-1-1- | ................................ 1 . . . ... . 1 . . . .. .1 .. .. . . . . . .......... ... . | +-- 845 | -1101-1-1- | ................................ 1 . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 846 | 011-1-1-1- | .11111...1.....1......111.1..11. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 847 | -00010--1- | ................................ . . . . ... . 1 . . . .. .. .. .. . . . . . .......... ... . | +-- 848 | -011-0--1- | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . . . .......... ... . | +-- 849 | 10-001--1- | .11.1........................... 1 . . . ... . 1 . . . .. .1 .. .. . . . . . .......... ... . | +-- 850 | -1--11--1- | ................................ . . . 1 ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 851 | 0100----1- | ................................ . . . . ... . 1 . . . .. .. .. .. . . . . . .......... ... . | +-- 852 | 10-01000-- | .11.1........................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 853 | -110-000-- | ................................ . . . . ... . 1 . . . .. .. .. .. . . . . . .......... ... . | +-- 854 | 00011100-- | .11111.........1......1....1.1.. 1 . . . ... . . 1 . . 1. .. .. .. . . . . . .......... ... . | +-- 855 | 00000010-- | .11111....................111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 856 | -0100010-- | .1.1.1........1...........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 857 | 00-00010-- | ................................ . . . . ... 1 . . . . .1 .. .. .. . . . . . .......... ... . | +-- 858 | --101110-- | 1..111....1...............1..... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 859 | 1101-110-- | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . 1 . .1.1..1... 1.1 . | +-- 860 | 0-001-10-- | ................................ . . . . ... 1 . 1 . . .. .. .. .. . . . . . .......... ... . | +-- 861 | 100110-0-- | ................................ . . . . ... . 1 . . . .. .. .. .. . . . . . 1....11111 ... . | +-- 862 | -1--11-0-- | ................................ . . . 1 ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 863 | 01-----0-- | ................................ . . . . ... 1 . 1 . . .. .. .. .. . . . . . .......... ... . | +-- 864 | -0100101-- | .1.1.1........1...........11111. . . . . ... 1 . . . . .1 .. .. .. . . . . . .......... ... . | +-- 865 | -1100101-- | ................................ . . . . ... 1 1 . . . .. .. .. .. . . . . . .......... ... . | +-- 866 | 100-1101-- | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . . . 1...11..1. ... . | +-- 867 | 11011-01-- | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . 1 . 11.11..1.. 1.1 . | +-- 868 | ---01011-- | ................................ . . . . ... 1 . 1 . . .. .. .. .. . . . . . ......1... ... . | +-- 869 | --110111-- | .1111........................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 870 | -0011111-- | .1.1.1........1.11........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 871 | -100-111-- | ................................ . . . . ... 1 1 . 1 . .. .. .. .. . . . . . .......... ... . | +-- 872 | 1-1--111-- | .11............................. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 873 | -1101-11-- | 1...11....1...............1..... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 874 | -1-11-11-- | ................................ . 1 . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 875 | 0--11-11-- | ................................ . . . 1 ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 876 | ----10-1-- | ................................ . . . . 1.. . . . . . .. .. .. .. . . . . . .......... ... . | +-- 877 | 0100-0-1-- | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . . . .......... ... . | +-- 878 | --0111-1-- | ................................ . . . . ... 1 . . . . .. .. .. .. . . . . . ...1...... ... . | +-- 879 | ---11--1-- | ................................ . . . . .1. . . . . . .. .. .. .. . . . . . .......... ... . | +-- 880 | 0-11-10--- | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . . . .......... ... . | +-- 881 | ----0-0--- | ................................ . . . . 1.. . . . . . .. .. .. .. . . . . . .......... ... . | +-- 882 | ----111--- | ................................ . . . . 11. . . . . . .. .. .. .. . . . . . .......... ... . | +-- 883 | 11011-1--- | ..111........................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 884 | ----00---- | ................................ . . . . .1. . . . . . .. .. .. .. . . . . . .......... ... . | +-- 885 | ---111---- | ................................ . . . . .1. . . . . . .. .. .. .. . . . . . .......... ... . | +-- 886 | 111------- | .11............................. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 887 | --1------- | ................................ . . . . 1.1 . . . . . .. .. .. .. . . . . . .......... ... . | +-- 888 | -1-------- | ................................ . . . . 111 . . . . . .. .. .. .. . . . . . .......... ... . | +-- 889 | 0--------- | ................................ . . . . 111 . . . . . .. .. .. .. . . . . . .......... ... . | +-- 890 | ---------- | ................................ . . . . ... . . . . . .. .. .. .. . . . . . .......... .1. . | +-- *=======================================================================================================================* +-- +-- Table ROM64_INSTR Signal Assignments for Product Terms +MQQ1:ROM64_INSTR_PT(1) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("100000000")); +MQQ2:ROM64_INSTR_PT(2) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10000000")); +MQQ3:ROM64_INSTR_PT(3) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011000000")); +MQQ4:ROM64_INSTR_PT(4) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("101000000")); +MQQ5:ROM64_INSTR_PT(5) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000000000")); +MQQ6:ROM64_INSTR_PT(6) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110000000")); +MQQ7:ROM64_INSTR_PT(7) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011000000")); +MQQ8:ROM64_INSTR_PT(8) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00100000")); +MQQ9:ROM64_INSTR_PT(9) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001100000")); +MQQ10:ROM64_INSTR_PT(10) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011100000")); +MQQ11:ROM64_INSTR_PT(11) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01100000")); +MQQ12:ROM64_INSTR_PT(12) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00000000")); +MQQ13:ROM64_INSTR_PT(13) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11000000")); +MQQ14:ROM64_INSTR_PT(14) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001010000")); +MQQ15:ROM64_INSTR_PT(15) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011010000")); +MQQ16:ROM64_INSTR_PT(16) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("101010000")); +MQQ17:ROM64_INSTR_PT(17) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0000110000")); +MQQ18:ROM64_INSTR_PT(18) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010110000")); +MQQ19:ROM64_INSTR_PT(19) <= + Eq(( ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0110000")); +MQQ20:ROM64_INSTR_PT(20) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011110000")); +MQQ21:ROM64_INSTR_PT(21) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011110000")); +MQQ22:ROM64_INSTR_PT(22) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110000")); +MQQ23:ROM64_INSTR_PT(23) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000010000")); +MQQ24:ROM64_INSTR_PT(24) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110000")); +MQQ25:ROM64_INSTR_PT(25) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110000")); +MQQ26:ROM64_INSTR_PT(26) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11000000")); +MQQ27:ROM64_INSTR_PT(27) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000100000")); +MQQ28:ROM64_INSTR_PT(28) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10010000")); +MQQ29:ROM64_INSTR_PT(29) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110000")); +MQQ30:ROM64_INSTR_PT(30) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110000")); +MQQ31:ROM64_INSTR_PT(31) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1110000")); +MQQ32:ROM64_INSTR_PT(32) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0010000")); +MQQ33:ROM64_INSTR_PT(33) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10010000")); +MQQ34:ROM64_INSTR_PT(34) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1010000")); +MQQ35:ROM64_INSTR_PT(35) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1110000")); +MQQ36:ROM64_INSTR_PT(36) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10001000")); +MQQ37:ROM64_INSTR_PT(37) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("101001000")); +MQQ38:ROM64_INSTR_PT(38) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110001000")); +MQQ39:ROM64_INSTR_PT(39) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01001000")); +MQQ40:ROM64_INSTR_PT(40) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110101000")); +MQQ41:ROM64_INSTR_PT(41) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001101000")); +MQQ42:ROM64_INSTR_PT(42) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011101000")); +MQQ43:ROM64_INSTR_PT(43) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011101000")); +MQQ44:ROM64_INSTR_PT(44) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000101000")); +MQQ45:ROM64_INSTR_PT(45) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("111101000")); +MQQ46:ROM64_INSTR_PT(46) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000001000")); +MQQ47:ROM64_INSTR_PT(47) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1101000")); +MQQ48:ROM64_INSTR_PT(48) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001011000")); +MQQ49:ROM64_INSTR_PT(49) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011011000")); +MQQ50:ROM64_INSTR_PT(50) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01011000")); +MQQ51:ROM64_INSTR_PT(51) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000111000")); +MQQ52:ROM64_INSTR_PT(52) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110111000")); +MQQ53:ROM64_INSTR_PT(53) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01111000")); +MQQ54:ROM64_INSTR_PT(54) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010011000")); +MQQ55:ROM64_INSTR_PT(55) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110111000")); +MQQ56:ROM64_INSTR_PT(56) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10111000")); +MQQ57:ROM64_INSTR_PT(57) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01111000")); +MQQ58:ROM64_INSTR_PT(58) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01001000")); +MQQ59:ROM64_INSTR_PT(59) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00011000")); +MQQ60:ROM64_INSTR_PT(60) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00011000")); +MQQ61:ROM64_INSTR_PT(61) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("100111000")); +MQQ62:ROM64_INSTR_PT(62) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110111000")); +MQQ63:ROM64_INSTR_PT(63) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000000000")); +MQQ64:ROM64_INSTR_PT(64) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01000000")); +MQQ65:ROM64_INSTR_PT(65) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10000000")); +MQQ66:ROM64_INSTR_PT(66) <= + Eq(( ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("010000")); +MQQ67:ROM64_INSTR_PT(67) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110000")); +MQQ68:ROM64_INSTR_PT(68) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1100000")); +MQQ69:ROM64_INSTR_PT(69) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1010000")); +MQQ70:ROM64_INSTR_PT(70) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000001000")); +MQQ71:ROM64_INSTR_PT(71) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01011000")); +MQQ72:ROM64_INSTR_PT(72) <= + Eq(( ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000")); +MQQ73:ROM64_INSTR_PT(73) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0100000100")); +MQQ74:ROM64_INSTR_PT(74) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001000100")); +MQQ75:ROM64_INSTR_PT(75) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("1101000100")); +MQQ76:ROM64_INSTR_PT(76) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011000100")); +MQQ77:ROM64_INSTR_PT(77) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011000100")); +MQQ78:ROM64_INSTR_PT(78) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011000100")); +MQQ79:ROM64_INSTR_PT(79) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10000100")); +MQQ80:ROM64_INSTR_PT(80) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0100100100")); +MQQ81:ROM64_INSTR_PT(81) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110100100")); +MQQ82:ROM64_INSTR_PT(82) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001100100")); +MQQ83:ROM64_INSTR_PT(83) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011100100")); +MQQ84:ROM64_INSTR_PT(84) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11100100")); +MQQ85:ROM64_INSTR_PT(85) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10100100")); +MQQ86:ROM64_INSTR_PT(86) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000000100")); +MQQ87:ROM64_INSTR_PT(87) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10000100")); +MQQ88:ROM64_INSTR_PT(88) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110100100")); +MQQ89:ROM64_INSTR_PT(89) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0100010100")); +MQQ90:ROM64_INSTR_PT(90) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110010100")); +MQQ91:ROM64_INSTR_PT(91) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001010100")); +MQQ92:ROM64_INSTR_PT(92) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011010100")); +MQQ93:ROM64_INSTR_PT(93) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01010100")); +MQQ94:ROM64_INSTR_PT(94) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1010100")); +MQQ95:ROM64_INSTR_PT(95) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0000110100")); +MQQ96:ROM64_INSTR_PT(96) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010110100")); +MQQ97:ROM64_INSTR_PT(97) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011110100")); +MQQ98:ROM64_INSTR_PT(98) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110100")); +MQQ99:ROM64_INSTR_PT(99) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000110100")); +MQQ100:ROM64_INSTR_PT(100) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110100")); +MQQ101:ROM64_INSTR_PT(101) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110100")); +MQQ102:ROM64_INSTR_PT(102) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01000100")); +MQQ103:ROM64_INSTR_PT(103) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10010100")); +MQQ104:ROM64_INSTR_PT(104) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110100")); +MQQ105:ROM64_INSTR_PT(105) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1010100")); +MQQ106:ROM64_INSTR_PT(106) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0100001100")); +MQQ107:ROM64_INSTR_PT(107) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001001100")); +MQQ108:ROM64_INSTR_PT(108) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("001001100")); +MQQ109:ROM64_INSTR_PT(109) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11001100")); +MQQ110:ROM64_INSTR_PT(110) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011001100")); +MQQ111:ROM64_INSTR_PT(111) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11001100")); +MQQ112:ROM64_INSTR_PT(112) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000101100")); +MQQ113:ROM64_INSTR_PT(113) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("100101100")); +MQQ114:ROM64_INSTR_PT(114) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010101100")); +MQQ115:ROM64_INSTR_PT(115) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110101100")); +MQQ116:ROM64_INSTR_PT(116) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011101100")); +MQQ117:ROM64_INSTR_PT(117) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01101100")); +MQQ118:ROM64_INSTR_PT(118) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01101100")); +MQQ119:ROM64_INSTR_PT(119) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110011100")); +MQQ120:ROM64_INSTR_PT(120) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11011100")); +MQQ121:ROM64_INSTR_PT(121) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011011100")); +MQQ122:ROM64_INSTR_PT(122) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11111100")); +MQQ123:ROM64_INSTR_PT(123) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("100111100")); +MQQ124:ROM64_INSTR_PT(124) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110111100")); +MQQ125:ROM64_INSTR_PT(125) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01111100")); +MQQ126:ROM64_INSTR_PT(126) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11111100")); +MQQ127:ROM64_INSTR_PT(127) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000011100")); +MQQ128:ROM64_INSTR_PT(128) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010011100")); +MQQ129:ROM64_INSTR_PT(129) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000111100")); +MQQ130:ROM64_INSTR_PT(130) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11111100")); +MQQ131:ROM64_INSTR_PT(131) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0011100")); +MQQ132:ROM64_INSTR_PT(132) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01111100")); +MQQ133:ROM64_INSTR_PT(133) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10001100")); +MQQ134:ROM64_INSTR_PT(134) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11101100")); +MQQ135:ROM64_INSTR_PT(135) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1101100")); +MQQ136:ROM64_INSTR_PT(136) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000111100")); +MQQ137:ROM64_INSTR_PT(137) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10111100")); +MQQ138:ROM64_INSTR_PT(138) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0100100")); +MQQ139:ROM64_INSTR_PT(139) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11010100")); +MQQ140:ROM64_INSTR_PT(140) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1010100")); +MQQ141:ROM64_INSTR_PT(141) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000001100")); +MQQ142:ROM64_INSTR_PT(142) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00001100")); +MQQ143:ROM64_INSTR_PT(143) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1101100")); +MQQ144:ROM64_INSTR_PT(144) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00111100")); +MQQ145:ROM64_INSTR_PT(145) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01111100")); +MQQ146:ROM64_INSTR_PT(146) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1001100")); +MQQ147:ROM64_INSTR_PT(147) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11000000")); +MQQ148:ROM64_INSTR_PT(148) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01010000")); +MQQ149:ROM64_INSTR_PT(149) <= + Eq(( ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("010000")); +MQQ150:ROM64_INSTR_PT(150) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01001000")); +MQQ151:ROM64_INSTR_PT(151) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1001000")); +MQQ152:ROM64_INSTR_PT(152) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("1000")); +MQQ153:ROM64_INSTR_PT(153) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000000100")); +MQQ154:ROM64_INSTR_PT(154) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01000100")); +MQQ155:ROM64_INSTR_PT(155) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10100100")); +MQQ156:ROM64_INSTR_PT(156) <= + Eq(( ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("00100")); +MQQ157:ROM64_INSTR_PT(157) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01111100")); +MQQ158:ROM64_INSTR_PT(158) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11111100")); +MQQ159:ROM64_INSTR_PT(159) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1111100")); +MQQ160:ROM64_INSTR_PT(160) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10011100")); +MQQ161:ROM64_INSTR_PT(161) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("011100")); +MQQ162:ROM64_INSTR_PT(162) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0111100")); +MQQ163:ROM64_INSTR_PT(163) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("01000")); +MQQ164:ROM64_INSTR_PT(164) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1000100")); +MQQ165:ROM64_INSTR_PT(165) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("10100")); +MQQ166:ROM64_INSTR_PT(166) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1101100")); +MQQ167:ROM64_INSTR_PT(167) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("01100")); +MQQ168:ROM64_INSTR_PT(168) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0100000010")); +MQQ169:ROM64_INSTR_PT(169) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("1101000010")); +MQQ170:ROM64_INSTR_PT(170) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011000010")); +MQQ171:ROM64_INSTR_PT(171) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("101000010")); +MQQ172:ROM64_INSTR_PT(172) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011000010")); +MQQ173:ROM64_INSTR_PT(173) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110100010")); +MQQ174:ROM64_INSTR_PT(174) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011100010")); +MQQ175:ROM64_INSTR_PT(175) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011100010")); +MQQ176:ROM64_INSTR_PT(176) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000000010")); +MQQ177:ROM64_INSTR_PT(177) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1100010")); +MQQ178:ROM64_INSTR_PT(178) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("000010")); +MQQ179:ROM64_INSTR_PT(179) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010010010")); +MQQ180:ROM64_INSTR_PT(180) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("001110010")); +MQQ181:ROM64_INSTR_PT(181) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011110010")); +MQQ182:ROM64_INSTR_PT(182) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110010")); +MQQ183:ROM64_INSTR_PT(183) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11110010")); +MQQ184:ROM64_INSTR_PT(184) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010010010")); +MQQ185:ROM64_INSTR_PT(185) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11010010")); +MQQ186:ROM64_INSTR_PT(186) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000110010")); +MQQ187:ROM64_INSTR_PT(187) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110010")); +MQQ188:ROM64_INSTR_PT(188) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110010")); +MQQ189:ROM64_INSTR_PT(189) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11000010")); +MQQ190:ROM64_INSTR_PT(190) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1000010")); +MQQ191:ROM64_INSTR_PT(191) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01100010")); +MQQ192:ROM64_INSTR_PT(192) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1100010")); +MQQ193:ROM64_INSTR_PT(193) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000110010")); +MQQ194:ROM64_INSTR_PT(194) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110010")); +MQQ195:ROM64_INSTR_PT(195) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1110010")); +MQQ196:ROM64_INSTR_PT(196) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110010")); +MQQ197:ROM64_INSTR_PT(197) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11110010")); +MQQ198:ROM64_INSTR_PT(198) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1010010")); +MQQ199:ROM64_INSTR_PT(199) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10001010")); +MQQ200:ROM64_INSTR_PT(200) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("1101001010")); +MQQ201:ROM64_INSTR_PT(201) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("001001010")); +MQQ202:ROM64_INSTR_PT(202) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00001010")); +MQQ203:ROM64_INSTR_PT(203) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011001010")); +MQQ204:ROM64_INSTR_PT(204) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10001010")); +MQQ205:ROM64_INSTR_PT(205) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011101010")); +MQQ206:ROM64_INSTR_PT(206) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011101010")); +MQQ207:ROM64_INSTR_PT(207) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110101010")); +MQQ208:ROM64_INSTR_PT(208) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000101010")); +MQQ209:ROM64_INSTR_PT(209) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10101010")); +MQQ210:ROM64_INSTR_PT(210) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00001010")); +MQQ211:ROM64_INSTR_PT(211) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110011010")); +MQQ212:ROM64_INSTR_PT(212) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10011010")); +MQQ213:ROM64_INSTR_PT(213) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11011010")); +MQQ214:ROM64_INSTR_PT(214) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011011010")); +MQQ215:ROM64_INSTR_PT(215) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00111010")); +MQQ216:ROM64_INSTR_PT(216) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011111010")); +MQQ217:ROM64_INSTR_PT(217) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10111010")); +MQQ218:ROM64_INSTR_PT(218) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01111010")); +MQQ219:ROM64_INSTR_PT(219) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010011010")); +MQQ220:ROM64_INSTR_PT(220) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01011010")); +MQQ221:ROM64_INSTR_PT(221) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("100111010")); +MQQ222:ROM64_INSTR_PT(222) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110111010")); +MQQ223:ROM64_INSTR_PT(223) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01111010")); +MQQ224:ROM64_INSTR_PT(224) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000101010")); +MQQ225:ROM64_INSTR_PT(225) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01011010")); +MQQ226:ROM64_INSTR_PT(226) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10011010")); +MQQ227:ROM64_INSTR_PT(227) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("011010")); +MQQ228:ROM64_INSTR_PT(228) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000100010")); +MQQ229:ROM64_INSTR_PT(229) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01100010")); +MQQ230:ROM64_INSTR_PT(230) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010010010")); +MQQ231:ROM64_INSTR_PT(231) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1010010")); +MQQ232:ROM64_INSTR_PT(232) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000001010")); +MQQ233:ROM64_INSTR_PT(233) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1101010")); +MQQ234:ROM64_INSTR_PT(234) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011010")); +MQQ235:ROM64_INSTR_PT(235) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("011010")); +MQQ236:ROM64_INSTR_PT(236) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0100000110")); +MQQ237:ROM64_INSTR_PT(237) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110000110")); +MQQ238:ROM64_INSTR_PT(238) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001000110")); +MQQ239:ROM64_INSTR_PT(239) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("1101000110")); +MQQ240:ROM64_INSTR_PT(240) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11000110")); +MQQ241:ROM64_INSTR_PT(241) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("101000110")); +MQQ242:ROM64_INSTR_PT(242) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("111000110")); +MQQ243:ROM64_INSTR_PT(243) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010000110")); +MQQ244:ROM64_INSTR_PT(244) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011000110")); +MQQ245:ROM64_INSTR_PT(245) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0000100110")); +MQQ246:ROM64_INSTR_PT(246) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001100110")); +MQQ247:ROM64_INSTR_PT(247) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("001100110")); +MQQ248:ROM64_INSTR_PT(248) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000000110")); +MQQ249:ROM64_INSTR_PT(249) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010000110")); +MQQ250:ROM64_INSTR_PT(250) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01000110")); +MQQ251:ROM64_INSTR_PT(251) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10100110")); +MQQ252:ROM64_INSTR_PT(252) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110010110")); +MQQ253:ROM64_INSTR_PT(253) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001010110")); +MQQ254:ROM64_INSTR_PT(254) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011010110")); +MQQ255:ROM64_INSTR_PT(255) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000110110")); +MQQ256:ROM64_INSTR_PT(256) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110110")); +MQQ257:ROM64_INSTR_PT(257) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011110110")); +MQQ258:ROM64_INSTR_PT(258) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110110")); +MQQ259:ROM64_INSTR_PT(259) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("100110110")); +MQQ260:ROM64_INSTR_PT(260) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110110")); +MQQ261:ROM64_INSTR_PT(261) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110110")); +MQQ262:ROM64_INSTR_PT(262) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1100110")); +MQQ263:ROM64_INSTR_PT(263) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("100110110")); +MQQ264:ROM64_INSTR_PT(264) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110110")); +MQQ265:ROM64_INSTR_PT(265) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("100001110")); +MQQ266:ROM64_INSTR_PT(266) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010001110")); +MQQ267:ROM64_INSTR_PT(267) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110001110")); +MQQ268:ROM64_INSTR_PT(268) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011001110")); +MQQ269:ROM64_INSTR_PT(269) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011001110")); +MQQ270:ROM64_INSTR_PT(270) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0000101110")); +MQQ271:ROM64_INSTR_PT(271) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("100101110")); +MQQ272:ROM64_INSTR_PT(272) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011101110")); +MQQ273:ROM64_INSTR_PT(273) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11101110")); +MQQ274:ROM64_INSTR_PT(274) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11101110")); +MQQ275:ROM64_INSTR_PT(275) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110101110")); +MQQ276:ROM64_INSTR_PT(276) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01101110")); +MQQ277:ROM64_INSTR_PT(277) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110011110")); +MQQ278:ROM64_INSTR_PT(278) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11011110")); +MQQ279:ROM64_INSTR_PT(279) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01011110")); +MQQ280:ROM64_INSTR_PT(280) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11111110")); +MQQ281:ROM64_INSTR_PT(281) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0111110")); +MQQ282:ROM64_INSTR_PT(282) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11111110")); +MQQ283:ROM64_INSTR_PT(283) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000011110")); +MQQ284:ROM64_INSTR_PT(284) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010011110")); +MQQ285:ROM64_INSTR_PT(285) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01011110")); +MQQ286:ROM64_INSTR_PT(286) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000111110")); +MQQ287:ROM64_INSTR_PT(287) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10111110")); +MQQ288:ROM64_INSTR_PT(288) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11111110")); +MQQ289:ROM64_INSTR_PT(289) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("111110")); +MQQ290:ROM64_INSTR_PT(290) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01011110")); +MQQ291:ROM64_INSTR_PT(291) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000111110")); +MQQ292:ROM64_INSTR_PT(292) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00111110")); +MQQ293:ROM64_INSTR_PT(293) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1111110")); +MQQ294:ROM64_INSTR_PT(294) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11110110")); +MQQ295:ROM64_INSTR_PT(295) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("100110")); +MQQ296:ROM64_INSTR_PT(296) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000001110")); +MQQ297:ROM64_INSTR_PT(297) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01011110")); +MQQ298:ROM64_INSTR_PT(298) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00111110")); +MQQ299:ROM64_INSTR_PT(299) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11011110")); +MQQ300:ROM64_INSTR_PT(300) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1111110")); +MQQ301:ROM64_INSTR_PT(301) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("101110")); +MQQ302:ROM64_INSTR_PT(302) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("101110")); +MQQ303:ROM64_INSTR_PT(303) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01000010")); +MQQ304:ROM64_INSTR_PT(304) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000011010")); +MQQ305:ROM64_INSTR_PT(305) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10011010")); +MQQ306:ROM64_INSTR_PT(306) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10011010")); +MQQ307:ROM64_INSTR_PT(307) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("101010")); +MQQ308:ROM64_INSTR_PT(308) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000000110")); +MQQ309:ROM64_INSTR_PT(309) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00000110")); +MQQ310:ROM64_INSTR_PT(310) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11010110")); +MQQ311:ROM64_INSTR_PT(311) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11110110")); +MQQ312:ROM64_INSTR_PT(312) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000001110")); +MQQ313:ROM64_INSTR_PT(313) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0001110")); +MQQ314:ROM64_INSTR_PT(314) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00111110")); +MQQ315:ROM64_INSTR_PT(315) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011110")); +MQQ316:ROM64_INSTR_PT(316) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00010110")); +MQQ317:ROM64_INSTR_PT(317) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("010010")); +MQQ318:ROM64_INSTR_PT(318) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("01010")); +MQQ319:ROM64_INSTR_PT(319) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011110")); +MQQ320:ROM64_INSTR_PT(320) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0000010")); +MQQ321:ROM64_INSTR_PT(321) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1000000")); +MQQ322:ROM64_INSTR_PT(322) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01010000")); +MQQ323:ROM64_INSTR_PT(323) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1000000")); +MQQ324:ROM64_INSTR_PT(324) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10101000")); +MQQ325:ROM64_INSTR_PT(325) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01101000")); +MQQ326:ROM64_INSTR_PT(326) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0101000")); +MQQ327:ROM64_INSTR_PT(327) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1100000")); +MQQ328:ROM64_INSTR_PT(328) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011000")); +MQQ329:ROM64_INSTR_PT(329) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0000100")); +MQQ330:ROM64_INSTR_PT(330) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11000100")); +MQQ331:ROM64_INSTR_PT(331) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00000100")); +MQQ332:ROM64_INSTR_PT(332) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00000100")); +MQQ333:ROM64_INSTR_PT(333) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1001100")); +MQQ334:ROM64_INSTR_PT(334) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00101100")); +MQQ335:ROM64_INSTR_PT(335) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11011100")); +MQQ336:ROM64_INSTR_PT(336) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1000000")); +MQQ337:ROM64_INSTR_PT(337) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1100010")); +MQQ338:ROM64_INSTR_PT(338) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1000010")); +MQQ339:ROM64_INSTR_PT(339) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1100010")); +MQQ340:ROM64_INSTR_PT(340) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10010010")); +MQQ341:ROM64_INSTR_PT(341) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110010")); +MQQ342:ROM64_INSTR_PT(342) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1010010")); +MQQ343:ROM64_INSTR_PT(343) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01001010")); +MQQ344:ROM64_INSTR_PT(344) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11001010")); +MQQ345:ROM64_INSTR_PT(345) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1100110")); +MQQ346:ROM64_INSTR_PT(346) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1111110")); +MQQ347:ROM64_INSTR_PT(347) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011110")); +MQQ348:ROM64_INSTR_PT(348) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011110")); +MQQ349:ROM64_INSTR_PT(349) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0101110")); +MQQ350:ROM64_INSTR_PT(350) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1111110")); +MQQ351:ROM64_INSTR_PT(351) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("101010")); +MQQ352:ROM64_INSTR_PT(352) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0101110")); +MQQ353:ROM64_INSTR_PT(353) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("011110")); +MQQ354:ROM64_INSTR_PT(354) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1000000")); +MQQ355:ROM64_INSTR_PT(355) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1101100")); +MQQ356:ROM64_INSTR_PT(356) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00000010")); +MQQ357:ROM64_INSTR_PT(357) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("100010")); +MQQ358:ROM64_INSTR_PT(358) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("110110")); +MQQ359:ROM64_INSTR_PT(359) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0011110")); +MQQ360:ROM64_INSTR_PT(360) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("100010")); +MQQ361:ROM64_INSTR_PT(361) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("100000001")); +MQQ362:ROM64_INSTR_PT(362) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001000001")); +MQQ363:ROM64_INSTR_PT(363) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011000001")); +MQQ364:ROM64_INSTR_PT(364) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110000001")); +MQQ365:ROM64_INSTR_PT(365) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011000001")); +MQQ366:ROM64_INSTR_PT(366) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011100001")); +MQQ367:ROM64_INSTR_PT(367) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11100001")); +MQQ368:ROM64_INSTR_PT(368) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000000001")); +MQQ369:ROM64_INSTR_PT(369) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11000001")); +MQQ370:ROM64_INSTR_PT(370) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010010001")); +MQQ371:ROM64_INSTR_PT(371) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011010001")); +MQQ372:ROM64_INSTR_PT(372) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000010001")); +MQQ373:ROM64_INSTR_PT(373) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000110001")); +MQQ374:ROM64_INSTR_PT(374) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010110001")); +MQQ375:ROM64_INSTR_PT(375) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("001110001")); +MQQ376:ROM64_INSTR_PT(376) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00110001")); +MQQ377:ROM64_INSTR_PT(377) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110001")); +MQQ378:ROM64_INSTR_PT(378) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11110001")); +MQQ379:ROM64_INSTR_PT(379) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110001")); +MQQ380:ROM64_INSTR_PT(380) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10110001")); +MQQ381:ROM64_INSTR_PT(381) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110001")); +MQQ382:ROM64_INSTR_PT(382) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1110001")); +MQQ383:ROM64_INSTR_PT(383) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11000001")); +MQQ384:ROM64_INSTR_PT(384) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1100001")); +MQQ385:ROM64_INSTR_PT(385) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("100110001")); +MQQ386:ROM64_INSTR_PT(386) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110001")); +MQQ387:ROM64_INSTR_PT(387) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1010001")); +MQQ388:ROM64_INSTR_PT(388) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10001001")); +MQQ389:ROM64_INSTR_PT(389) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("111001001")); +MQQ390:ROM64_INSTR_PT(390) <= + Eq(( ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1001001")); +MQQ391:ROM64_INSTR_PT(391) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01001001")); +MQQ392:ROM64_INSTR_PT(392) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000101001")); +MQQ393:ROM64_INSTR_PT(393) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00101001")); +MQQ394:ROM64_INSTR_PT(394) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110101001")); +MQQ395:ROM64_INSTR_PT(395) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001101001")); +MQQ396:ROM64_INSTR_PT(396) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011101001")); +MQQ397:ROM64_INSTR_PT(397) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011101001")); +MQQ398:ROM64_INSTR_PT(398) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("111101001")); +MQQ399:ROM64_INSTR_PT(399) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010001001")); +MQQ400:ROM64_INSTR_PT(400) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("001001")); +MQQ401:ROM64_INSTR_PT(401) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110011001")); +MQQ402:ROM64_INSTR_PT(402) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001011001")); +MQQ403:ROM64_INSTR_PT(403) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011111001")); +MQQ404:ROM64_INSTR_PT(404) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10111001")); +MQQ405:ROM64_INSTR_PT(405) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000011001")); +MQQ406:ROM64_INSTR_PT(406) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010011001")); +MQQ407:ROM64_INSTR_PT(407) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011001")); +MQQ408:ROM64_INSTR_PT(408) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110111001")); +MQQ409:ROM64_INSTR_PT(409) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01111001")); +MQQ410:ROM64_INSTR_PT(410) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10111001")); +MQQ411:ROM64_INSTR_PT(411) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10011001")); +MQQ412:ROM64_INSTR_PT(412) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110111001")); +MQQ413:ROM64_INSTR_PT(413) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10111001")); +MQQ414:ROM64_INSTR_PT(414) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01000001")); +MQQ415:ROM64_INSTR_PT(415) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11000001")); +MQQ416:ROM64_INSTR_PT(416) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01100001")); +MQQ417:ROM64_INSTR_PT(417) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01010001")); +MQQ418:ROM64_INSTR_PT(418) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1010001")); +MQQ419:ROM64_INSTR_PT(419) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01101001")); +MQQ420:ROM64_INSTR_PT(420) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01011001")); +MQQ421:ROM64_INSTR_PT(421) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0011001")); +MQQ422:ROM64_INSTR_PT(422) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0100000101")); +MQQ423:ROM64_INSTR_PT(423) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("1101000101")); +MQQ424:ROM64_INSTR_PT(424) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("101000101")); +MQQ425:ROM64_INSTR_PT(425) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011000101")); +MQQ426:ROM64_INSTR_PT(426) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000000101")); +MQQ427:ROM64_INSTR_PT(427) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011000101")); +MQQ428:ROM64_INSTR_PT(428) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11000101")); +MQQ429:ROM64_INSTR_PT(429) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0100100101")); +MQQ430:ROM64_INSTR_PT(430) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110100101")); +MQQ431:ROM64_INSTR_PT(431) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10100101")); +MQQ432:ROM64_INSTR_PT(432) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001100101")); +MQQ433:ROM64_INSTR_PT(433) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011100101")); +MQQ434:ROM64_INSTR_PT(434) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011100101")); +MQQ435:ROM64_INSTR_PT(435) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11100101")); +MQQ436:ROM64_INSTR_PT(436) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10100101")); +MQQ437:ROM64_INSTR_PT(437) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110010101")); +MQQ438:ROM64_INSTR_PT(438) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001010101")); +MQQ439:ROM64_INSTR_PT(439) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("101010101")); +MQQ440:ROM64_INSTR_PT(440) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01010101")); +MQQ441:ROM64_INSTR_PT(441) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0000110101")); +MQQ442:ROM64_INSTR_PT(442) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011110101")); +MQQ443:ROM64_INSTR_PT(443) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110101")); +MQQ444:ROM64_INSTR_PT(444) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110101")); +MQQ445:ROM64_INSTR_PT(445) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110101")); +MQQ446:ROM64_INSTR_PT(446) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01000101")); +MQQ447:ROM64_INSTR_PT(447) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1100101")); +MQQ448:ROM64_INSTR_PT(448) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110101")); +MQQ449:ROM64_INSTR_PT(449) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("110101")); +MQQ450:ROM64_INSTR_PT(450) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1010101")); +MQQ451:ROM64_INSTR_PT(451) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0100001101")); +MQQ452:ROM64_INSTR_PT(452) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110001101")); +MQQ453:ROM64_INSTR_PT(453) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001001101")); +MQQ454:ROM64_INSTR_PT(454) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011001101")); +MQQ455:ROM64_INSTR_PT(455) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010101101")); +MQQ456:ROM64_INSTR_PT(456) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110101101")); +MQQ457:ROM64_INSTR_PT(457) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011101101")); +MQQ458:ROM64_INSTR_PT(458) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011101101")); +MQQ459:ROM64_INSTR_PT(459) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01001101")); +MQQ460:ROM64_INSTR_PT(460) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01101101")); +MQQ461:ROM64_INSTR_PT(461) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11011101")); +MQQ462:ROM64_INSTR_PT(462) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11011101")); +MQQ463:ROM64_INSTR_PT(463) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11111101")); +MQQ464:ROM64_INSTR_PT(464) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10111101")); +MQQ465:ROM64_INSTR_PT(465) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000011101")); +MQQ466:ROM64_INSTR_PT(466) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010011101")); +MQQ467:ROM64_INSTR_PT(467) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000111101")); +MQQ468:ROM64_INSTR_PT(468) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("100111101")); +MQQ469:ROM64_INSTR_PT(469) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0111101")); +MQQ470:ROM64_INSTR_PT(470) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11111101")); +MQQ471:ROM64_INSTR_PT(471) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11001101")); +MQQ472:ROM64_INSTR_PT(472) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01100101")); +MQQ473:ROM64_INSTR_PT(473) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000010101")); +MQQ474:ROM64_INSTR_PT(474) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000110101")); +MQQ475:ROM64_INSTR_PT(475) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1010101")); +MQQ476:ROM64_INSTR_PT(476) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("010101")); +MQQ477:ROM64_INSTR_PT(477) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00001101")); +MQQ478:ROM64_INSTR_PT(478) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01001101")); +MQQ479:ROM64_INSTR_PT(479) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1001101")); +MQQ480:ROM64_INSTR_PT(480) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11011101")); +MQQ481:ROM64_INSTR_PT(481) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0111101")); +MQQ482:ROM64_INSTR_PT(482) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11000001")); +MQQ483:ROM64_INSTR_PT(483) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01010001")); +MQQ484:ROM64_INSTR_PT(484) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10110001")); +MQQ485:ROM64_INSTR_PT(485) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01001001")); +MQQ486:ROM64_INSTR_PT(486) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0001001")); +MQQ487:ROM64_INSTR_PT(487) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10101001")); +MQQ488:ROM64_INSTR_PT(488) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10011001")); +MQQ489:ROM64_INSTR_PT(489) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000111001")); +MQQ490:ROM64_INSTR_PT(490) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01111001")); +MQQ491:ROM64_INSTR_PT(491) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000000101")); +MQQ492:ROM64_INSTR_PT(492) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000100101")); +MQQ493:ROM64_INSTR_PT(493) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10100101")); +MQQ494:ROM64_INSTR_PT(494) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("100101")); +MQQ495:ROM64_INSTR_PT(495) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00111101")); +MQQ496:ROM64_INSTR_PT(496) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10011101")); +MQQ497:ROM64_INSTR_PT(497) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0111101")); +MQQ498:ROM64_INSTR_PT(498) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0101101")); +MQQ499:ROM64_INSTR_PT(499) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0001101")); +MQQ500:ROM64_INSTR_PT(500) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0000001")); +MQQ501:ROM64_INSTR_PT(501) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("001101")); +MQQ502:ROM64_INSTR_PT(502) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("001")); +MQQ503:ROM64_INSTR_PT(503) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0100000011")); +MQQ504:ROM64_INSTR_PT(504) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010000011")); +MQQ505:ROM64_INSTR_PT(505) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("1101000011")); +MQQ506:ROM64_INSTR_PT(506) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011000011")); +MQQ507:ROM64_INSTR_PT(507) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11000011")); +MQQ508:ROM64_INSTR_PT(508) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010100011")); +MQQ509:ROM64_INSTR_PT(509) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10100011")); +MQQ510:ROM64_INSTR_PT(510) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011100011")); +MQQ511:ROM64_INSTR_PT(511) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000000011")); +MQQ512:ROM64_INSTR_PT(512) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10100011")); +MQQ513:ROM64_INSTR_PT(513) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1000011")); +MQQ514:ROM64_INSTR_PT(514) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00010011")); +MQQ515:ROM64_INSTR_PT(515) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010010011")); +MQQ516:ROM64_INSTR_PT(516) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00010011")); +MQQ517:ROM64_INSTR_PT(517) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10010011")); +MQQ518:ROM64_INSTR_PT(518) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10010011")); +MQQ519:ROM64_INSTR_PT(519) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("001110011")); +MQQ520:ROM64_INSTR_PT(520) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011110011")); +MQQ521:ROM64_INSTR_PT(521) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000110011")); +MQQ522:ROM64_INSTR_PT(522) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110011")); +MQQ523:ROM64_INSTR_PT(523) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110011")); +MQQ524:ROM64_INSTR_PT(524) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01000011")); +MQQ525:ROM64_INSTR_PT(525) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01100011")); +MQQ526:ROM64_INSTR_PT(526) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1100011")); +MQQ527:ROM64_INSTR_PT(527) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10010011")); +MQQ528:ROM64_INSTR_PT(528) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000110011")); +MQQ529:ROM64_INSTR_PT(529) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1010011")); +MQQ530:ROM64_INSTR_PT(530) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10001011")); +MQQ531:ROM64_INSTR_PT(531) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("1101001011")); +MQQ532:ROM64_INSTR_PT(532) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("001001011")); +MQQ533:ROM64_INSTR_PT(533) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("111001011")); +MQQ534:ROM64_INSTR_PT(534) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0000101011")); +MQQ535:ROM64_INSTR_PT(535) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110101011")); +MQQ536:ROM64_INSTR_PT(536) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("001101011")); +MQQ537:ROM64_INSTR_PT(537) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011101011")); +MQQ538:ROM64_INSTR_PT(538) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01101011")); +MQQ539:ROM64_INSTR_PT(539) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010001011")); +MQQ540:ROM64_INSTR_PT(540) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01101011")); +MQQ541:ROM64_INSTR_PT(541) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10011011")); +MQQ542:ROM64_INSTR_PT(542) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11011011")); +MQQ543:ROM64_INSTR_PT(543) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0011011")); +MQQ544:ROM64_INSTR_PT(544) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11111011")); +MQQ545:ROM64_INSTR_PT(545) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010011011")); +MQQ546:ROM64_INSTR_PT(546) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01011011")); +MQQ547:ROM64_INSTR_PT(547) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11011011")); +MQQ548:ROM64_INSTR_PT(548) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11111011")); +MQQ549:ROM64_INSTR_PT(549) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000101011")); +MQQ550:ROM64_INSTR_PT(550) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011011")); +MQQ551:ROM64_INSTR_PT(551) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("11011")); +MQQ552:ROM64_INSTR_PT(552) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000100011")); +MQQ553:ROM64_INSTR_PT(553) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01100011")); +MQQ554:ROM64_INSTR_PT(554) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010010011")); +MQQ555:ROM64_INSTR_PT(555) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10110011")); +MQQ556:ROM64_INSTR_PT(556) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00001011")); +MQQ557:ROM64_INSTR_PT(557) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1101011")); +MQQ558:ROM64_INSTR_PT(558) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000011011")); +MQQ559:ROM64_INSTR_PT(559) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011011")); +MQQ560:ROM64_INSTR_PT(560) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000111011")); +MQQ561:ROM64_INSTR_PT(561) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0101011")); +MQQ562:ROM64_INSTR_PT(562) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00011011")); +MQQ563:ROM64_INSTR_PT(563) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0111011")); +MQQ564:ROM64_INSTR_PT(564) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1111011")); +MQQ565:ROM64_INSTR_PT(565) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("11011")); +MQQ566:ROM64_INSTR_PT(566) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010000111")); +MQQ567:ROM64_INSTR_PT(567) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00000111")); +MQQ568:ROM64_INSTR_PT(568) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110000111")); +MQQ569:ROM64_INSTR_PT(569) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001000111")); +MQQ570:ROM64_INSTR_PT(570) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011000111")); +MQQ571:ROM64_INSTR_PT(571) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011000111")); +MQQ572:ROM64_INSTR_PT(572) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010100111")); +MQQ573:ROM64_INSTR_PT(573) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110100111")); +MQQ574:ROM64_INSTR_PT(574) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10100111")); +MQQ575:ROM64_INSTR_PT(575) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001100111")); +MQQ576:ROM64_INSTR_PT(576) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011100111")); +MQQ577:ROM64_INSTR_PT(577) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011100111")); +MQQ578:ROM64_INSTR_PT(578) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00000111")); +MQQ579:ROM64_INSTR_PT(579) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000010111")); +MQQ580:ROM64_INSTR_PT(580) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10010111")); +MQQ581:ROM64_INSTR_PT(581) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("001010111")); +MQQ582:ROM64_INSTR_PT(582) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011010111")); +MQQ583:ROM64_INSTR_PT(583) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110111")); +MQQ584:ROM64_INSTR_PT(584) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01010111")); +MQQ585:ROM64_INSTR_PT(585) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010000111")); +MQQ586:ROM64_INSTR_PT(586) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01100111")); +MQQ587:ROM64_INSTR_PT(587) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010010111")); +MQQ588:ROM64_INSTR_PT(588) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000001111")); +MQQ589:ROM64_INSTR_PT(589) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0100001111")); +MQQ590:ROM64_INSTR_PT(590) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010001111")); +MQQ591:ROM64_INSTR_PT(591) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10001111")); +MQQ592:ROM64_INSTR_PT(592) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11001111")); +MQQ593:ROM64_INSTR_PT(593) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10001111")); +MQQ594:ROM64_INSTR_PT(594) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0001111")); +MQQ595:ROM64_INSTR_PT(595) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0000101111")); +MQQ596:ROM64_INSTR_PT(596) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010101111")); +MQQ597:ROM64_INSTR_PT(597) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001101111")); +MQQ598:ROM64_INSTR_PT(598) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11101111")); +MQQ599:ROM64_INSTR_PT(599) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11101111")); +MQQ600:ROM64_INSTR_PT(600) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11101111")); +MQQ601:ROM64_INSTR_PT(601) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00011111")); +MQQ602:ROM64_INSTR_PT(602) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10011111")); +MQQ603:ROM64_INSTR_PT(603) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("001011111")); +MQQ604:ROM64_INSTR_PT(604) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000111111")); +MQQ605:ROM64_INSTR_PT(605) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01111111")); +MQQ606:ROM64_INSTR_PT(606) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11111111")); +MQQ607:ROM64_INSTR_PT(607) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011111")); +MQQ608:ROM64_INSTR_PT(608) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10011111")); +MQQ609:ROM64_INSTR_PT(609) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1111111")); +MQQ610:ROM64_INSTR_PT(610) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10111111")); +MQQ611:ROM64_INSTR_PT(611) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01111111")); +MQQ612:ROM64_INSTR_PT(612) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11111111")); +MQQ613:ROM64_INSTR_PT(613) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01101111")); +MQQ614:ROM64_INSTR_PT(614) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011111")); +MQQ615:ROM64_INSTR_PT(615) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10111111")); +MQQ616:ROM64_INSTR_PT(616) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01111111")); +MQQ617:ROM64_INSTR_PT(617) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("111111")); +MQQ618:ROM64_INSTR_PT(618) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("111111")); +MQQ619:ROM64_INSTR_PT(619) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11110111")); +MQQ620:ROM64_INSTR_PT(620) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1100111")); +MQQ621:ROM64_INSTR_PT(621) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01011111")); +MQQ622:ROM64_INSTR_PT(622) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011111")); +MQQ623:ROM64_INSTR_PT(623) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01111111")); +MQQ624:ROM64_INSTR_PT(624) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011111")); +MQQ625:ROM64_INSTR_PT(625) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0111111")); +MQQ626:ROM64_INSTR_PT(626) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01001111")); +MQQ627:ROM64_INSTR_PT(627) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011111")); +MQQ628:ROM64_INSTR_PT(628) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0111111")); +MQQ629:ROM64_INSTR_PT(629) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0111111")); +MQQ630:ROM64_INSTR_PT(630) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("100011")); +MQQ631:ROM64_INSTR_PT(631) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("110011")); +MQQ632:ROM64_INSTR_PT(632) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01101011")); +MQQ633:ROM64_INSTR_PT(633) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000011011")); +MQQ634:ROM64_INSTR_PT(634) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000111011")); +MQQ635:ROM64_INSTR_PT(635) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00111011")); +MQQ636:ROM64_INSTR_PT(636) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01001011")); +MQQ637:ROM64_INSTR_PT(637) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11011011")); +MQQ638:ROM64_INSTR_PT(638) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("10011")); +MQQ639:ROM64_INSTR_PT(639) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000100111")); +MQQ640:ROM64_INSTR_PT(640) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110111")); +MQQ641:ROM64_INSTR_PT(641) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1000111")); +MQQ642:ROM64_INSTR_PT(642) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0111111")); +MQQ643:ROM64_INSTR_PT(643) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("111111")); +MQQ644:ROM64_INSTR_PT(644) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("111111")); +MQQ645:ROM64_INSTR_PT(645) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1110111")); +MQQ646:ROM64_INSTR_PT(646) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11011111")); +MQQ647:ROM64_INSTR_PT(647) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("11111")); +MQQ648:ROM64_INSTR_PT(648) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1111111")); +MQQ649:ROM64_INSTR_PT(649) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("111111")); +MQQ650:ROM64_INSTR_PT(650) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("11111")); +MQQ651:ROM64_INSTR_PT(651) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("10111")); +MQQ652:ROM64_INSTR_PT(652) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("11011")); +MQQ653:ROM64_INSTR_PT(653) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11000001")); +MQQ654:ROM64_INSTR_PT(654) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1000001")); +MQQ655:ROM64_INSTR_PT(655) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110001")); +MQQ656:ROM64_INSTR_PT(656) <= + Eq(( ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("110001")); +MQQ657:ROM64_INSTR_PT(657) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10101001")); +MQQ658:ROM64_INSTR_PT(658) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1001001")); +MQQ659:ROM64_INSTR_PT(659) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00011001")); +MQQ660:ROM64_INSTR_PT(660) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("101001")); +MQQ661:ROM64_INSTR_PT(661) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00000101")); +MQQ662:ROM64_INSTR_PT(662) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01000101")); +MQQ663:ROM64_INSTR_PT(663) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000100101")); +MQQ664:ROM64_INSTR_PT(664) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11110101")); +MQQ665:ROM64_INSTR_PT(665) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11001101")); +MQQ666:ROM64_INSTR_PT(666) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10011101")); +MQQ667:ROM64_INSTR_PT(667) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011101")); +MQQ668:ROM64_INSTR_PT(668) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1000001")); +MQQ669:ROM64_INSTR_PT(669) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("010001")); +MQQ670:ROM64_INSTR_PT(670) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("110001")); +MQQ671:ROM64_INSTR_PT(671) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0001001")); +MQQ672:ROM64_INSTR_PT(672) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0010101")); +MQQ673:ROM64_INSTR_PT(673) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("011101")); +MQQ674:ROM64_INSTR_PT(674) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1000011")); +MQQ675:ROM64_INSTR_PT(675) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110100011")); +MQQ676:ROM64_INSTR_PT(676) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("100011")); +MQQ677:ROM64_INSTR_PT(677) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01001011")); +MQQ678:ROM64_INSTR_PT(678) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10101011")); +MQQ679:ROM64_INSTR_PT(679) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10011011")); +MQQ680:ROM64_INSTR_PT(680) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011011")); +MQQ681:ROM64_INSTR_PT(681) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01001011")); +MQQ682:ROM64_INSTR_PT(682) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11011011")); +MQQ683:ROM64_INSTR_PT(683) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("010011")); +MQQ684:ROM64_INSTR_PT(684) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110100111")); +MQQ685:ROM64_INSTR_PT(685) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10010111")); +MQQ686:ROM64_INSTR_PT(686) <= + Eq(( ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0111")); +MQQ687:ROM64_INSTR_PT(687) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10001111")); +MQQ688:ROM64_INSTR_PT(688) <= + Eq(( ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("101111")); +MQQ689:ROM64_INSTR_PT(689) <= + Eq(( ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("011111")); +MQQ690:ROM64_INSTR_PT(690) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1111111")); +MQQ691:ROM64_INSTR_PT(691) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0111111")); +MQQ692:ROM64_INSTR_PT(692) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("101111")); +MQQ693:ROM64_INSTR_PT(693) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("111111")); +MQQ694:ROM64_INSTR_PT(694) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1000111")); +MQQ695:ROM64_INSTR_PT(695) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1110111")); +MQQ696:ROM64_INSTR_PT(696) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("000111")); +MQQ697:ROM64_INSTR_PT(697) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("110111")); +MQQ698:ROM64_INSTR_PT(698) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11011111")); +MQQ699:ROM64_INSTR_PT(699) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1111111")); +MQQ700:ROM64_INSTR_PT(700) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("011011")); +MQQ701:ROM64_INSTR_PT(701) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("11011")); +MQQ702:ROM64_INSTR_PT(702) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("110111")); +MQQ703:ROM64_INSTR_PT(703) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0101111")); +MQQ704:ROM64_INSTR_PT(704) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011111")); +MQQ705:ROM64_INSTR_PT(705) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1111111")); +MQQ706:ROM64_INSTR_PT(706) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1000001")); +MQQ707:ROM64_INSTR_PT(707) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("010001")); +MQQ708:ROM64_INSTR_PT(708) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1001001")); +MQQ709:ROM64_INSTR_PT(709) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("111001")); +MQQ710:ROM64_INSTR_PT(710) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("100101")); +MQQ711:ROM64_INSTR_PT(711) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("100001")); +MQQ712:ROM64_INSTR_PT(712) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("111101")); +MQQ713:ROM64_INSTR_PT(713) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0110111")); +MQQ714:ROM64_INSTR_PT(714) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("110111")); +MQQ715:ROM64_INSTR_PT(715) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1111111")); +MQQ716:ROM64_INSTR_PT(716) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("111111")); +MQQ717:ROM64_INSTR_PT(717) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("011111")); +MQQ718:ROM64_INSTR_PT(718) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("11011")); +MQQ719:ROM64_INSTR_PT(719) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("100101")); +MQQ720:ROM64_INSTR_PT(720) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("100011")); +MQQ721:ROM64_INSTR_PT(721) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("1101")); +MQQ722:ROM64_INSTR_PT(722) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("01100000")); +MQQ723:ROM64_INSTR_PT(723) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("01100000")); +MQQ724:ROM64_INSTR_PT(724) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("010010000")); +MQQ725:ROM64_INSTR_PT(725) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("000110000")); +MQQ726:ROM64_INSTR_PT(726) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("01110000")); +MQQ727:ROM64_INSTR_PT(727) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0100000")); +MQQ728:ROM64_INSTR_PT(728) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("010001000")); +MQQ729:ROM64_INSTR_PT(729) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("11011000")); +MQQ730:ROM64_INSTR_PT(730) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("111000")); +MQQ731:ROM64_INSTR_PT(731) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0111000")); +MQQ732:ROM64_INSTR_PT(732) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("110000")); +MQQ733:ROM64_INSTR_PT(733) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("00000100")); +MQQ734:ROM64_INSTR_PT(734) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0000100")); +MQQ735:ROM64_INSTR_PT(735) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("01100100")); +MQQ736:ROM64_INSTR_PT(736) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1100100")); +MQQ737:ROM64_INSTR_PT(737) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("100100")); +MQQ738:ROM64_INSTR_PT(738) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("010010100")); +MQQ739:ROM64_INSTR_PT(739) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("01101100")); +MQQ740:ROM64_INSTR_PT(740) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("01101100")); +MQQ741:ROM64_INSTR_PT(741) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("10011100")); +MQQ742:ROM64_INSTR_PT(742) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("101100")); +MQQ743:ROM64_INSTR_PT(743) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0111100")); +MQQ744:ROM64_INSTR_PT(744) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0100100")); +MQQ745:ROM64_INSTR_PT(745) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0100000")); +MQQ746:ROM64_INSTR_PT(746) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1100000")); +MQQ747:ROM64_INSTR_PT(747) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("00000100")); +MQQ748:ROM64_INSTR_PT(748) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0101100")); +MQQ749:ROM64_INSTR_PT(749) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("011100")); +MQQ750:ROM64_INSTR_PT(750) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1101100")); +MQQ751:ROM64_INSTR_PT(751) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("11100")); +MQQ752:ROM64_INSTR_PT(752) <= + Eq(( ROM_ADDR_L2(3) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("000")); +MQQ753:ROM64_INSTR_PT(753) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("01100010")); +MQQ754:ROM64_INSTR_PT(754) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("00010010")); +MQQ755:ROM64_INSTR_PT(755) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("00000010")); +MQQ756:ROM64_INSTR_PT(756) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("11001010")); +MQQ757:ROM64_INSTR_PT(757) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("111010")); +MQQ758:ROM64_INSTR_PT(758) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1111010")); +MQQ759:ROM64_INSTR_PT(759) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("101010")); +MQQ760:ROM64_INSTR_PT(760) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1000110")); +MQQ761:ROM64_INSTR_PT(761) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("110100110")); +MQQ762:ROM64_INSTR_PT(762) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0010110")); +MQQ763:ROM64_INSTR_PT(763) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("010110")); +MQQ764:ROM64_INSTR_PT(764) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0001110")); +MQQ765:ROM64_INSTR_PT(765) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("00011110")); +MQQ766:ROM64_INSTR_PT(766) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("10011110")); +MQQ767:ROM64_INSTR_PT(767) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1010010")); +MQQ768:ROM64_INSTR_PT(768) <= + Eq(( ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("0110")); +MQQ769:ROM64_INSTR_PT(769) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("00011110")); +MQQ770:ROM64_INSTR_PT(770) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1111110")); +MQQ771:ROM64_INSTR_PT(771) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("010110")); +MQQ772:ROM64_INSTR_PT(772) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("10000")); +MQQ773:ROM64_INSTR_PT(773) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1101100")); +MQQ774:ROM64_INSTR_PT(774) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("011100")); +MQQ775:ROM64_INSTR_PT(775) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("00100")); +MQQ776:ROM64_INSTR_PT(776) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0100010")); +MQQ777:ROM64_INSTR_PT(777) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("11010010")); +MQQ778:ROM64_INSTR_PT(778) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("101010")); +MQQ779:ROM64_INSTR_PT(779) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("01110")); +MQQ780:ROM64_INSTR_PT(780) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("01110")); +MQQ781:ROM64_INSTR_PT(781) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("01000001")); +MQQ782:ROM64_INSTR_PT(782) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("110100001")); +MQQ783:ROM64_INSTR_PT(783) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("01010001")); +MQQ784:ROM64_INSTR_PT(784) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("11010001")); +MQQ785:ROM64_INSTR_PT(785) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1010001")); +MQQ786:ROM64_INSTR_PT(786) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0000001")); +MQQ787:ROM64_INSTR_PT(787) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("010001")); +MQQ788:ROM64_INSTR_PT(788) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0001001")); +MQQ789:ROM64_INSTR_PT(789) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("001001")); +MQQ790:ROM64_INSTR_PT(790) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("00011001")); +MQQ791:ROM64_INSTR_PT(791) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("111001")); +MQQ792:ROM64_INSTR_PT(792) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("00011001")); +MQQ793:ROM64_INSTR_PT(793) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("111001")); +MQQ794:ROM64_INSTR_PT(794) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("00100101")); +MQQ795:ROM64_INSTR_PT(795) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("00010101")); +MQQ796:ROM64_INSTR_PT(796) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("00011101")); +MQQ797:ROM64_INSTR_PT(797) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("10011101")); +MQQ798:ROM64_INSTR_PT(798) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("110101")); +MQQ799:ROM64_INSTR_PT(799) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("10101")); +MQQ800:ROM64_INSTR_PT(800) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("11101")); +MQQ801:ROM64_INSTR_PT(801) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0000101")); +MQQ802:ROM64_INSTR_PT(802) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0000101")); +MQQ803:ROM64_INSTR_PT(803) <= + Eq(( ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("11101")); +MQQ804:ROM64_INSTR_PT(804) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("000100011")); +MQQ805:ROM64_INSTR_PT(805) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("01110011")); +MQQ806:ROM64_INSTR_PT(806) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("00000011")); +MQQ807:ROM64_INSTR_PT(807) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0000011")); +MQQ808:ROM64_INSTR_PT(808) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0000011")); +MQQ809:ROM64_INSTR_PT(809) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1010011")); +MQQ810:ROM64_INSTR_PT(810) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("010011")); +MQQ811:ROM64_INSTR_PT(811) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("01101011")); +MQQ812:ROM64_INSTR_PT(812) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("00001011")); +MQQ813:ROM64_INSTR_PT(813) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("01001011")); +MQQ814:ROM64_INSTR_PT(814) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("101011")); +MQQ815:ROM64_INSTR_PT(815) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("11011")); +MQQ816:ROM64_INSTR_PT(816) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("100111")); +MQQ817:ROM64_INSTR_PT(817) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("00010111")); +MQQ818:ROM64_INSTR_PT(818) <= + Eq(( ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("110111")); +MQQ819:ROM64_INSTR_PT(819) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1110111")); +MQQ820:ROM64_INSTR_PT(820) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("11010111")); +MQQ821:ROM64_INSTR_PT(821) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("000101111")); +MQQ822:ROM64_INSTR_PT(822) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("01101111")); +MQQ823:ROM64_INSTR_PT(823) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("111111")); +MQQ824:ROM64_INSTR_PT(824) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("111111")); +MQQ825:ROM64_INSTR_PT(825) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("11111")); +MQQ826:ROM64_INSTR_PT(826) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("111111")); +MQQ827:ROM64_INSTR_PT(827) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("101011")); +MQQ828:ROM64_INSTR_PT(828) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0110111")); +MQQ829:ROM64_INSTR_PT(829) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("110111")); +MQQ830:ROM64_INSTR_PT(830) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("11111")); +MQQ831:ROM64_INSTR_PT(831) <= + Eq(( ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("0111")); +MQQ832:ROM64_INSTR_PT(832) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("111111")); +MQQ833:ROM64_INSTR_PT(833) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("11111")); +MQQ834:ROM64_INSTR_PT(834) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("110001")); +MQQ835:ROM64_INSTR_PT(835) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1001101")); +MQQ836:ROM64_INSTR_PT(836) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("101101")); +MQQ837:ROM64_INSTR_PT(837) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("101011")); +MQQ838:ROM64_INSTR_PT(838) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1111011")); +MQQ839:ROM64_INSTR_PT(839) <= + Eq(( ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("011")); +MQQ840:ROM64_INSTR_PT(840) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0000111")); +MQQ841:ROM64_INSTR_PT(841) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1111111")); +MQQ842:ROM64_INSTR_PT(842) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("101111")); +MQQ843:ROM64_INSTR_PT(843) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("01111")); +MQQ844:ROM64_INSTR_PT(844) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("100011")); +MQQ845:ROM64_INSTR_PT(845) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("110111")); +MQQ846:ROM64_INSTR_PT(846) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("011111")); +MQQ847:ROM64_INSTR_PT(847) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("000101")); +MQQ848:ROM64_INSTR_PT(848) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("01101")); +MQQ849:ROM64_INSTR_PT(849) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("100011")); +MQQ850:ROM64_INSTR_PT(850) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("1111")); +MQQ851:ROM64_INSTR_PT(851) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("01001")); +MQQ852:ROM64_INSTR_PT(852) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("1001000")); +MQQ853:ROM64_INSTR_PT(853) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) + ) , STD_ULOGIC_VECTOR'("110000")); +MQQ854:ROM64_INSTR_PT(854) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) + ) , STD_ULOGIC_VECTOR'("00011100")); +MQQ855:ROM64_INSTR_PT(855) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) + ) , STD_ULOGIC_VECTOR'("00000010")); +MQQ856:ROM64_INSTR_PT(856) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("0100010")); +MQQ857:ROM64_INSTR_PT(857) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("0000010")); +MQQ858:ROM64_INSTR_PT(858) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) + ) , STD_ULOGIC_VECTOR'("101110")); +MQQ859:ROM64_INSTR_PT(859) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("1101110")); +MQQ860:ROM64_INSTR_PT(860) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) + ) , STD_ULOGIC_VECTOR'("000110")); +MQQ861:ROM64_INSTR_PT(861) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("1001100")); +MQQ862:ROM64_INSTR_PT(862) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) + ) , STD_ULOGIC_VECTOR'("1110")); +MQQ863:ROM64_INSTR_PT(863) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("010")); +MQQ864:ROM64_INSTR_PT(864) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("0100101")); +MQQ865:ROM64_INSTR_PT(865) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("1100101")); +MQQ866:ROM64_INSTR_PT(866) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("1001101")); +MQQ867:ROM64_INSTR_PT(867) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("1101101")); +MQQ868:ROM64_INSTR_PT(868) <= + Eq(( ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("01011")); +MQQ869:ROM64_INSTR_PT(869) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) + ) , STD_ULOGIC_VECTOR'("110111")); +MQQ870:ROM64_INSTR_PT(870) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("0011111")); +MQQ871:ROM64_INSTR_PT(871) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) + ) , STD_ULOGIC_VECTOR'("100111")); +MQQ872:ROM64_INSTR_PT(872) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("11111")); +MQQ873:ROM64_INSTR_PT(873) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) + ) , STD_ULOGIC_VECTOR'("110111")); +MQQ874:ROM64_INSTR_PT(874) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("11111")); +MQQ875:ROM64_INSTR_PT(875) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("01111")); +MQQ876:ROM64_INSTR_PT(876) <= + Eq(( ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("101")); +MQQ877:ROM64_INSTR_PT(877) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) + ) , STD_ULOGIC_VECTOR'("010001")); +MQQ878:ROM64_INSTR_PT(878) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("01111")); +MQQ879:ROM64_INSTR_PT(879) <= + Eq(( ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("111")); +MQQ880:ROM64_INSTR_PT(880) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) ) , STD_ULOGIC_VECTOR'("01110")); +MQQ881:ROM64_INSTR_PT(881) <= + Eq(( ROM_ADDR_L2(4) & ROM_ADDR_L2(6) + ) , STD_ULOGIC_VECTOR'("00")); +MQQ882:ROM64_INSTR_PT(882) <= + Eq(( ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) ) , STD_ULOGIC_VECTOR'("111")); +MQQ883:ROM64_INSTR_PT(883) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) + ) , STD_ULOGIC_VECTOR'("110111")); +MQQ884:ROM64_INSTR_PT(884) <= + Eq(( ROM_ADDR_L2(4) & ROM_ADDR_L2(5) + ) , STD_ULOGIC_VECTOR'("00")); +MQQ885:ROM64_INSTR_PT(885) <= + Eq(( ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) ) , STD_ULOGIC_VECTOR'("111")); +MQQ886:ROM64_INSTR_PT(886) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) ) , STD_ULOGIC_VECTOR'("111")); +MQQ887:ROM64_INSTR_PT(887) <= + Eq(( ROM_ADDR_L2(2) ) , STD_ULOGIC'('1')); +MQQ888:ROM64_INSTR_PT(888) <= + Eq(( ROM_ADDR_L2(1) ) , STD_ULOGIC'('1')); +MQQ889:ROM64_INSTR_PT(889) <= + Eq(( ROM_ADDR_L2(0) ) , STD_ULOGIC'('0')); +MQQ890:ROM64_INSTR_PT(890) <= + '1'; +-- Table ROM64_INSTR Signal Assignments for Outputs +MQQ891:TEMPLATE(0) <= + (ROM64_INSTR_PT(29) OR ROM64_INSTR_PT(35) + OR ROM64_INSTR_PT(45) OR ROM64_INSTR_PT(65) + OR ROM64_INSTR_PT(74) OR ROM64_INSTR_PT(84) + OR ROM64_INSTR_PT(112) OR ROM64_INSTR_PT(119) + OR ROM64_INSTR_PT(129) OR ROM64_INSTR_PT(134) + OR ROM64_INSTR_PT(143) OR ROM64_INSTR_PT(158) + OR ROM64_INSTR_PT(160) OR ROM64_INSTR_PT(176) + OR ROM64_INSTR_PT(177) OR ROM64_INSTR_PT(179) + OR ROM64_INSTR_PT(183) OR ROM64_INSTR_PT(221) + OR ROM64_INSTR_PT(225) OR ROM64_INSTR_PT(233) + OR ROM64_INSTR_PT(237) OR ROM64_INSTR_PT(242) + OR ROM64_INSTR_PT(259) OR ROM64_INSTR_PT(294) + OR ROM64_INSTR_PT(296) OR ROM64_INSTR_PT(311) + OR ROM64_INSTR_PT(339) OR ROM64_INSTR_PT(350) + OR ROM64_INSTR_PT(354) OR ROM64_INSTR_PT(355) + OR ROM64_INSTR_PT(358) OR ROM64_INSTR_PT(359) + OR ROM64_INSTR_PT(362) OR ROM64_INSTR_PT(367) + OR ROM64_INSTR_PT(368) OR ROM64_INSTR_PT(378) + OR ROM64_INSTR_PT(384) OR ROM64_INSTR_PT(389) + OR ROM64_INSTR_PT(392) OR ROM64_INSTR_PT(402) + OR ROM64_INSTR_PT(428) OR ROM64_INSTR_PT(435) + OR ROM64_INSTR_PT(470) OR ROM64_INSTR_PT(477) + OR ROM64_INSTR_PT(527) OR ROM64_INSTR_PT(557) + OR ROM64_INSTR_PT(564) OR ROM64_INSTR_PT(572) + OR ROM64_INSTR_PT(590) OR ROM64_INSTR_PT(602) + OR ROM64_INSTR_PT(610) OR ROM64_INSTR_PT(619) + OR ROM64_INSTR_PT(653) OR ROM64_INSTR_PT(657) + OR ROM64_INSTR_PT(664) OR ROM64_INSTR_PT(694) + OR ROM64_INSTR_PT(695) OR ROM64_INSTR_PT(702) + OR ROM64_INSTR_PT(716) OR ROM64_INSTR_PT(719) + OR ROM64_INSTR_PT(720) OR ROM64_INSTR_PT(721) + OR ROM64_INSTR_PT(736) OR ROM64_INSTR_PT(770) + OR ROM64_INSTR_PT(798) OR ROM64_INSTR_PT(832) + OR ROM64_INSTR_PT(834) OR ROM64_INSTR_PT(858) + OR ROM64_INSTR_PT(873)); +MQQ892:TEMPLATE(1) <= + (ROM64_INSTR_PT(2) OR ROM64_INSTR_PT(4) + OR ROM64_INSTR_PT(6) OR ROM64_INSTR_PT(8) + OR ROM64_INSTR_PT(9) OR ROM64_INSTR_PT(10) + OR ROM64_INSTR_PT(11) OR ROM64_INSTR_PT(14) + OR ROM64_INSTR_PT(15) OR ROM64_INSTR_PT(17) + OR ROM64_INSTR_PT(18) OR ROM64_INSTR_PT(21) + OR ROM64_INSTR_PT(22) OR ROM64_INSTR_PT(25) + OR ROM64_INSTR_PT(34) OR ROM64_INSTR_PT(36) + OR ROM64_INSTR_PT(38) OR ROM64_INSTR_PT(41) + OR ROM64_INSTR_PT(42) OR ROM64_INSTR_PT(43) + OR ROM64_INSTR_PT(49) OR ROM64_INSTR_PT(51) + OR ROM64_INSTR_PT(52) OR ROM64_INSTR_PT(53) + OR ROM64_INSTR_PT(55) OR ROM64_INSTR_PT(56) + OR ROM64_INSTR_PT(61) OR ROM64_INSTR_PT(64) + OR ROM64_INSTR_PT(68) OR ROM64_INSTR_PT(69) + OR ROM64_INSTR_PT(70) OR ROM64_INSTR_PT(71) + OR ROM64_INSTR_PT(73) OR ROM64_INSTR_PT(75) + OR ROM64_INSTR_PT(77) OR ROM64_INSTR_PT(78) + OR ROM64_INSTR_PT(82) OR ROM64_INSTR_PT(83) + OR ROM64_INSTR_PT(86) OR ROM64_INSTR_PT(89) + OR ROM64_INSTR_PT(90) OR ROM64_INSTR_PT(92) + OR ROM64_INSTR_PT(93) OR ROM64_INSTR_PT(95) + OR ROM64_INSTR_PT(96) OR ROM64_INSTR_PT(97) + OR ROM64_INSTR_PT(99) OR ROM64_INSTR_PT(100) + OR ROM64_INSTR_PT(101) OR ROM64_INSTR_PT(102) + OR ROM64_INSTR_PT(104) OR ROM64_INSTR_PT(105) + OR ROM64_INSTR_PT(106) OR ROM64_INSTR_PT(108) + OR ROM64_INSTR_PT(109) OR ROM64_INSTR_PT(110) + OR ROM64_INSTR_PT(113) OR ROM64_INSTR_PT(116) + OR ROM64_INSTR_PT(117) OR ROM64_INSTR_PT(118) + OR ROM64_INSTR_PT(124) OR ROM64_INSTR_PT(127) + OR ROM64_INSTR_PT(136) OR ROM64_INSTR_PT(137) + OR ROM64_INSTR_PT(140) OR ROM64_INSTR_PT(144) + OR ROM64_INSTR_PT(145) OR ROM64_INSTR_PT(148) + OR ROM64_INSTR_PT(153) OR ROM64_INSTR_PT(161) + OR ROM64_INSTR_PT(162) OR ROM64_INSTR_PT(164) + OR ROM64_INSTR_PT(169) OR ROM64_INSTR_PT(170) + OR ROM64_INSTR_PT(171) OR ROM64_INSTR_PT(172) + OR ROM64_INSTR_PT(173) OR ROM64_INSTR_PT(175) + OR ROM64_INSTR_PT(180) OR ROM64_INSTR_PT(184) + OR ROM64_INSTR_PT(185) OR ROM64_INSTR_PT(186) + OR ROM64_INSTR_PT(188) OR ROM64_INSTR_PT(193) + OR ROM64_INSTR_PT(195) OR ROM64_INSTR_PT(196) + OR ROM64_INSTR_PT(199) OR ROM64_INSTR_PT(201) + OR ROM64_INSTR_PT(202) OR ROM64_INSTR_PT(203) + OR ROM64_INSTR_PT(205) OR ROM64_INSTR_PT(206) + OR ROM64_INSTR_PT(208) OR ROM64_INSTR_PT(214) + OR ROM64_INSTR_PT(215) OR ROM64_INSTR_PT(216) + OR ROM64_INSTR_PT(217) OR ROM64_INSTR_PT(218) + OR ROM64_INSTR_PT(222) OR ROM64_INSTR_PT(223) + OR ROM64_INSTR_PT(226) OR ROM64_INSTR_PT(229) + OR ROM64_INSTR_PT(230) OR ROM64_INSTR_PT(238) + OR ROM64_INSTR_PT(241) OR ROM64_INSTR_PT(243) + OR ROM64_INSTR_PT(244) OR ROM64_INSTR_PT(252) + OR ROM64_INSTR_PT(254) OR ROM64_INSTR_PT(257) + OR ROM64_INSTR_PT(258) OR ROM64_INSTR_PT(260) + OR ROM64_INSTR_PT(261) OR ROM64_INSTR_PT(263) + OR ROM64_INSTR_PT(264) OR ROM64_INSTR_PT(265) + OR ROM64_INSTR_PT(268) OR ROM64_INSTR_PT(269) + OR ROM64_INSTR_PT(270) OR ROM64_INSTR_PT(271) + OR ROM64_INSTR_PT(273) OR ROM64_INSTR_PT(275) + OR ROM64_INSTR_PT(276) OR ROM64_INSTR_PT(277) + OR ROM64_INSTR_PT(280) OR ROM64_INSTR_PT(282) + OR ROM64_INSTR_PT(284) OR ROM64_INSTR_PT(285) + OR ROM64_INSTR_PT(286) OR ROM64_INSTR_PT(287) + OR ROM64_INSTR_PT(292) OR ROM64_INSTR_PT(293) + OR ROM64_INSTR_PT(297) OR ROM64_INSTR_PT(298) + OR ROM64_INSTR_PT(299) OR ROM64_INSTR_PT(302) + OR ROM64_INSTR_PT(305) OR ROM64_INSTR_PT(308) + OR ROM64_INSTR_PT(315) OR ROM64_INSTR_PT(322) + OR ROM64_INSTR_PT(325) OR ROM64_INSTR_PT(331) + OR ROM64_INSTR_PT(333) OR ROM64_INSTR_PT(345) + OR ROM64_INSTR_PT(349) OR ROM64_INSTR_PT(351) + OR ROM64_INSTR_PT(357) OR ROM64_INSTR_PT(364) + OR ROM64_INSTR_PT(365) OR ROM64_INSTR_PT(366) + OR ROM64_INSTR_PT(369) OR ROM64_INSTR_PT(371) + OR ROM64_INSTR_PT(372) OR ROM64_INSTR_PT(375) + OR ROM64_INSTR_PT(377) OR ROM64_INSTR_PT(379) + OR ROM64_INSTR_PT(381) OR ROM64_INSTR_PT(383) + OR ROM64_INSTR_PT(385) OR ROM64_INSTR_PT(388) + OR ROM64_INSTR_PT(391) OR ROM64_INSTR_PT(394) + OR ROM64_INSTR_PT(395) OR ROM64_INSTR_PT(397) + OR ROM64_INSTR_PT(403) OR ROM64_INSTR_PT(404) + OR ROM64_INSTR_PT(405) OR ROM64_INSTR_PT(408) + OR ROM64_INSTR_PT(409) OR ROM64_INSTR_PT(410) + OR ROM64_INSTR_PT(413) OR ROM64_INSTR_PT(414) + OR ROM64_INSTR_PT(415) OR ROM64_INSTR_PT(418) + OR ROM64_INSTR_PT(419) OR ROM64_INSTR_PT(420) + OR ROM64_INSTR_PT(422) OR ROM64_INSTR_PT(424) + OR ROM64_INSTR_PT(425) OR ROM64_INSTR_PT(426) + OR ROM64_INSTR_PT(427) OR ROM64_INSTR_PT(429) + OR ROM64_INSTR_PT(430) OR ROM64_INSTR_PT(432) + OR ROM64_INSTR_PT(433) OR ROM64_INSTR_PT(434) + OR ROM64_INSTR_PT(437) OR ROM64_INSTR_PT(438) + OR ROM64_INSTR_PT(439) OR ROM64_INSTR_PT(440) + OR ROM64_INSTR_PT(443) OR ROM64_INSTR_PT(445) + OR ROM64_INSTR_PT(446) OR ROM64_INSTR_PT(451) + OR ROM64_INSTR_PT(453) OR ROM64_INSTR_PT(454) + OR ROM64_INSTR_PT(455) OR ROM64_INSTR_PT(456) + OR ROM64_INSTR_PT(457) OR ROM64_INSTR_PT(458) + OR ROM64_INSTR_PT(460) OR ROM64_INSTR_PT(463) + OR ROM64_INSTR_PT(466) OR ROM64_INSTR_PT(467) + OR ROM64_INSTR_PT(473) OR ROM64_INSTR_PT(475) + OR ROM64_INSTR_PT(478) OR ROM64_INSTR_PT(480) + OR ROM64_INSTR_PT(481) OR ROM64_INSTR_PT(482) + OR ROM64_INSTR_PT(483) OR ROM64_INSTR_PT(484) + OR ROM64_INSTR_PT(485) OR ROM64_INSTR_PT(490) + OR ROM64_INSTR_PT(493) OR ROM64_INSTR_PT(495) + OR ROM64_INSTR_PT(497) OR ROM64_INSTR_PT(498) + OR ROM64_INSTR_PT(499) OR ROM64_INSTR_PT(503) + OR ROM64_INSTR_PT(504) OR ROM64_INSTR_PT(505) + OR ROM64_INSTR_PT(506) OR ROM64_INSTR_PT(508) + OR ROM64_INSTR_PT(509) OR ROM64_INSTR_PT(510) + OR ROM64_INSTR_PT(511) OR ROM64_INSTR_PT(512) + OR ROM64_INSTR_PT(514) OR ROM64_INSTR_PT(519) + OR ROM64_INSTR_PT(521) OR ROM64_INSTR_PT(522) + OR ROM64_INSTR_PT(523) OR ROM64_INSTR_PT(525) + OR ROM64_INSTR_PT(530) OR ROM64_INSTR_PT(531) + OR ROM64_INSTR_PT(532) OR ROM64_INSTR_PT(534) + OR ROM64_INSTR_PT(535) OR ROM64_INSTR_PT(536) + OR ROM64_INSTR_PT(537) OR ROM64_INSTR_PT(539) + OR ROM64_INSTR_PT(540) OR ROM64_INSTR_PT(542) + OR ROM64_INSTR_PT(544) OR ROM64_INSTR_PT(545) + OR ROM64_INSTR_PT(546) OR ROM64_INSTR_PT(548) + OR ROM64_INSTR_PT(549) OR ROM64_INSTR_PT(552) + OR ROM64_INSTR_PT(553) OR ROM64_INSTR_PT(554) + OR ROM64_INSTR_PT(555) OR ROM64_INSTR_PT(558) + OR ROM64_INSTR_PT(559) OR ROM64_INSTR_PT(563) + OR ROM64_INSTR_PT(566) OR ROM64_INSTR_PT(568) + OR ROM64_INSTR_PT(569) OR ROM64_INSTR_PT(570) + OR ROM64_INSTR_PT(571) OR ROM64_INSTR_PT(575) + OR ROM64_INSTR_PT(576) OR ROM64_INSTR_PT(577) + OR ROM64_INSTR_PT(579) OR ROM64_INSTR_PT(580) + OR ROM64_INSTR_PT(581) OR ROM64_INSTR_PT(582) + OR ROM64_INSTR_PT(583) OR ROM64_INSTR_PT(584) + OR ROM64_INSTR_PT(586) OR ROM64_INSTR_PT(588) + OR ROM64_INSTR_PT(589) OR ROM64_INSTR_PT(591) + OR ROM64_INSTR_PT(592) OR ROM64_INSTR_PT(593) + OR ROM64_INSTR_PT(595) OR ROM64_INSTR_PT(596) + OR ROM64_INSTR_PT(598) OR ROM64_INSTR_PT(599) + OR ROM64_INSTR_PT(600) OR ROM64_INSTR_PT(603) + OR ROM64_INSTR_PT(604) OR ROM64_INSTR_PT(606) + OR ROM64_INSTR_PT(607) OR ROM64_INSTR_PT(608) + OR ROM64_INSTR_PT(611) OR ROM64_INSTR_PT(612) + OR ROM64_INSTR_PT(613) OR ROM64_INSTR_PT(614) + OR ROM64_INSTR_PT(615) OR ROM64_INSTR_PT(616) + OR ROM64_INSTR_PT(617) OR ROM64_INSTR_PT(618) + OR ROM64_INSTR_PT(623) OR ROM64_INSTR_PT(626) + OR ROM64_INSTR_PT(627) OR ROM64_INSTR_PT(628) + OR ROM64_INSTR_PT(629) OR ROM64_INSTR_PT(633) + OR ROM64_INSTR_PT(637) OR ROM64_INSTR_PT(639) + OR ROM64_INSTR_PT(642) OR ROM64_INSTR_PT(643) + OR ROM64_INSTR_PT(644) OR ROM64_INSTR_PT(646) + OR ROM64_INSTR_PT(655) OR ROM64_INSTR_PT(660) + OR ROM64_INSTR_PT(663) OR ROM64_INSTR_PT(666) + OR ROM64_INSTR_PT(678) OR ROM64_INSTR_PT(679) + OR ROM64_INSTR_PT(681) OR ROM64_INSTR_PT(682) + OR ROM64_INSTR_PT(687) OR ROM64_INSTR_PT(703) + OR ROM64_INSTR_PT(713) OR ROM64_INSTR_PT(717) + OR ROM64_INSTR_PT(722) OR ROM64_INSTR_PT(731) + OR ROM64_INSTR_PT(741) OR ROM64_INSTR_PT(744) + OR ROM64_INSTR_PT(753) OR ROM64_INSTR_PT(761) + OR ROM64_INSTR_PT(769) OR ROM64_INSTR_PT(776) + OR ROM64_INSTR_PT(791) OR ROM64_INSTR_PT(801) + OR ROM64_INSTR_PT(808) OR ROM64_INSTR_PT(811) + OR ROM64_INSTR_PT(813) OR ROM64_INSTR_PT(822) + OR ROM64_INSTR_PT(824) OR ROM64_INSTR_PT(846) + OR ROM64_INSTR_PT(849) OR ROM64_INSTR_PT(852) + OR ROM64_INSTR_PT(854) OR ROM64_INSTR_PT(855) + OR ROM64_INSTR_PT(856) OR ROM64_INSTR_PT(864) + OR ROM64_INSTR_PT(869) OR ROM64_INSTR_PT(870) + OR ROM64_INSTR_PT(872) OR ROM64_INSTR_PT(886) + ); +MQQ893:TEMPLATE(2) <= + (ROM64_INSTR_PT(2) OR ROM64_INSTR_PT(5) + OR ROM64_INSTR_PT(6) OR ROM64_INSTR_PT(10) + OR ROM64_INSTR_PT(14) OR ROM64_INSTR_PT(15) + OR ROM64_INSTR_PT(18) OR ROM64_INSTR_PT(20) + OR ROM64_INSTR_PT(25) OR ROM64_INSTR_PT(28) + OR ROM64_INSTR_PT(33) OR ROM64_INSTR_PT(36) + OR ROM64_INSTR_PT(39) OR ROM64_INSTR_PT(41) + OR ROM64_INSTR_PT(42) OR ROM64_INSTR_PT(43) + OR ROM64_INSTR_PT(53) OR ROM64_INSTR_PT(56) + OR ROM64_INSTR_PT(60) OR ROM64_INSTR_PT(66) + OR ROM64_INSTR_PT(69) OR ROM64_INSTR_PT(73) + OR ROM64_INSTR_PT(77) OR ROM64_INSTR_PT(78) + OR ROM64_INSTR_PT(79) OR ROM64_INSTR_PT(82) + OR ROM64_INSTR_PT(89) OR ROM64_INSTR_PT(92) + OR ROM64_INSTR_PT(95) OR ROM64_INSTR_PT(96) + OR ROM64_INSTR_PT(97) OR ROM64_INSTR_PT(98) + OR ROM64_INSTR_PT(101) OR ROM64_INSTR_PT(104) + OR ROM64_INSTR_PT(106) OR ROM64_INSTR_PT(108) + OR ROM64_INSTR_PT(109) OR ROM64_INSTR_PT(110) + OR ROM64_INSTR_PT(116) OR ROM64_INSTR_PT(124) + OR ROM64_INSTR_PT(140) OR ROM64_INSTR_PT(142) + OR ROM64_INSTR_PT(145) OR ROM64_INSTR_PT(146) + OR ROM64_INSTR_PT(147) OR ROM64_INSTR_PT(150) + OR ROM64_INSTR_PT(151) OR ROM64_INSTR_PT(153) + OR ROM64_INSTR_PT(161) OR ROM64_INSTR_PT(166) + OR ROM64_INSTR_PT(168) OR ROM64_INSTR_PT(172) + OR ROM64_INSTR_PT(173) OR ROM64_INSTR_PT(174) + OR ROM64_INSTR_PT(175) OR ROM64_INSTR_PT(184) + OR ROM64_INSTR_PT(187) OR ROM64_INSTR_PT(188) + OR ROM64_INSTR_PT(190) OR ROM64_INSTR_PT(191) + OR ROM64_INSTR_PT(193) OR ROM64_INSTR_PT(195) + OR ROM64_INSTR_PT(202) OR ROM64_INSTR_PT(203) + OR ROM64_INSTR_PT(205) OR ROM64_INSTR_PT(206) + OR ROM64_INSTR_PT(207) OR ROM64_INSTR_PT(208) + OR ROM64_INSTR_PT(209) OR ROM64_INSTR_PT(216) + OR ROM64_INSTR_PT(219) OR ROM64_INSTR_PT(228) + OR ROM64_INSTR_PT(229) OR ROM64_INSTR_PT(230) + OR ROM64_INSTR_PT(231) OR ROM64_INSTR_PT(240) + OR ROM64_INSTR_PT(243) OR ROM64_INSTR_PT(247) + OR ROM64_INSTR_PT(253) OR ROM64_INSTR_PT(254) + OR ROM64_INSTR_PT(257) OR ROM64_INSTR_PT(258) + OR ROM64_INSTR_PT(260) OR ROM64_INSTR_PT(261) + OR ROM64_INSTR_PT(265) OR ROM64_INSTR_PT(269) + OR ROM64_INSTR_PT(273) OR ROM64_INSTR_PT(277) + OR ROM64_INSTR_PT(281) OR ROM64_INSTR_PT(284) + OR ROM64_INSTR_PT(288) OR ROM64_INSTR_PT(292) + OR ROM64_INSTR_PT(295) OR ROM64_INSTR_PT(304) + OR ROM64_INSTR_PT(307) OR ROM64_INSTR_PT(309) + OR ROM64_INSTR_PT(313) OR ROM64_INSTR_PT(324) + OR ROM64_INSTR_PT(325) OR ROM64_INSTR_PT(327) + OR ROM64_INSTR_PT(332) OR ROM64_INSTR_PT(333) + OR ROM64_INSTR_PT(334) OR ROM64_INSTR_PT(340) + OR ROM64_INSTR_PT(341) OR ROM64_INSTR_PT(342) + OR ROM64_INSTR_PT(345) OR ROM64_INSTR_PT(351) + OR ROM64_INSTR_PT(352) OR ROM64_INSTR_PT(357) + OR ROM64_INSTR_PT(361) OR ROM64_INSTR_PT(365) + OR ROM64_INSTR_PT(366) OR ROM64_INSTR_PT(369) + OR ROM64_INSTR_PT(371) OR ROM64_INSTR_PT(372) + OR ROM64_INSTR_PT(374) OR ROM64_INSTR_PT(377) + OR ROM64_INSTR_PT(379) OR ROM64_INSTR_PT(381) + OR ROM64_INSTR_PT(388) OR ROM64_INSTR_PT(394) + OR ROM64_INSTR_PT(395) OR ROM64_INSTR_PT(396) + OR ROM64_INSTR_PT(401) OR ROM64_INSTR_PT(403) + OR ROM64_INSTR_PT(405) OR ROM64_INSTR_PT(406) + OR ROM64_INSTR_PT(408) OR ROM64_INSTR_PT(409) + OR ROM64_INSTR_PT(413) OR ROM64_INSTR_PT(418) + OR ROM64_INSTR_PT(419) OR ROM64_INSTR_PT(420) + OR ROM64_INSTR_PT(422) OR ROM64_INSTR_PT(425) + OR ROM64_INSTR_PT(426) OR ROM64_INSTR_PT(429) + OR ROM64_INSTR_PT(430) OR ROM64_INSTR_PT(438) + OR ROM64_INSTR_PT(439) OR ROM64_INSTR_PT(440) + OR ROM64_INSTR_PT(443) OR ROM64_INSTR_PT(445) + OR ROM64_INSTR_PT(446) OR ROM64_INSTR_PT(448) + OR ROM64_INSTR_PT(451) OR ROM64_INSTR_PT(453) + OR ROM64_INSTR_PT(454) OR ROM64_INSTR_PT(455) + OR ROM64_INSTR_PT(456) OR ROM64_INSTR_PT(458) + OR ROM64_INSTR_PT(460) OR ROM64_INSTR_PT(463) + OR ROM64_INSTR_PT(464) OR ROM64_INSTR_PT(466) + OR ROM64_INSTR_PT(467) OR ROM64_INSTR_PT(468) + OR ROM64_INSTR_PT(471) OR ROM64_INSTR_PT(472) + OR ROM64_INSTR_PT(473) OR ROM64_INSTR_PT(474) + OR ROM64_INSTR_PT(475) OR ROM64_INSTR_PT(483) + OR ROM64_INSTR_PT(490) OR ROM64_INSTR_PT(491) + OR ROM64_INSTR_PT(497) OR ROM64_INSTR_PT(498) + OR ROM64_INSTR_PT(499) OR ROM64_INSTR_PT(503) + OR ROM64_INSTR_PT(506) OR ROM64_INSTR_PT(508) + OR ROM64_INSTR_PT(510) OR ROM64_INSTR_PT(514) + OR ROM64_INSTR_PT(516) OR ROM64_INSTR_PT(519) + OR ROM64_INSTR_PT(532) OR ROM64_INSTR_PT(538) + OR ROM64_INSTR_PT(542) OR ROM64_INSTR_PT(546) + OR ROM64_INSTR_PT(549) OR ROM64_INSTR_PT(551) + OR ROM64_INSTR_PT(553) OR ROM64_INSTR_PT(554) + OR ROM64_INSTR_PT(559) OR ROM64_INSTR_PT(562) + OR ROM64_INSTR_PT(566) OR ROM64_INSTR_PT(570) + OR ROM64_INSTR_PT(571) OR ROM64_INSTR_PT(575) + OR ROM64_INSTR_PT(580) OR ROM64_INSTR_PT(581) + OR ROM64_INSTR_PT(586) OR ROM64_INSTR_PT(589) + OR ROM64_INSTR_PT(593) OR ROM64_INSTR_PT(596) + OR ROM64_INSTR_PT(597) OR ROM64_INSTR_PT(598) + OR ROM64_INSTR_PT(601) OR ROM64_INSTR_PT(603) + OR ROM64_INSTR_PT(604) OR ROM64_INSTR_PT(606) + OR ROM64_INSTR_PT(611) OR ROM64_INSTR_PT(612) + OR ROM64_INSTR_PT(613) OR ROM64_INSTR_PT(614) + OR ROM64_INSTR_PT(615) OR ROM64_INSTR_PT(616) + OR ROM64_INSTR_PT(617) OR ROM64_INSTR_PT(620) + OR ROM64_INSTR_PT(626) OR ROM64_INSTR_PT(627) + OR ROM64_INSTR_PT(628) OR ROM64_INSTR_PT(632) + OR ROM64_INSTR_PT(635) OR ROM64_INSTR_PT(654) + OR ROM64_INSTR_PT(659) OR ROM64_INSTR_PT(660) + OR ROM64_INSTR_PT(663) OR ROM64_INSTR_PT(668) + OR ROM64_INSTR_PT(675) OR ROM64_INSTR_PT(679) + OR ROM64_INSTR_PT(681) OR ROM64_INSTR_PT(682) + OR ROM64_INSTR_PT(687) OR ROM64_INSTR_PT(691) + OR ROM64_INSTR_PT(703) OR ROM64_INSTR_PT(709) + OR ROM64_INSTR_PT(711) OR ROM64_INSTR_PT(713) + OR ROM64_INSTR_PT(717) OR ROM64_INSTR_PT(723) + OR ROM64_INSTR_PT(724) OR ROM64_INSTR_PT(728) + OR ROM64_INSTR_PT(733) OR ROM64_INSTR_PT(735) + OR ROM64_INSTR_PT(738) OR ROM64_INSTR_PT(741) + OR ROM64_INSTR_PT(759) OR ROM64_INSTR_PT(766) + OR ROM64_INSTR_PT(781) OR ROM64_INSTR_PT(791) + OR ROM64_INSTR_PT(794) OR ROM64_INSTR_PT(797) + OR ROM64_INSTR_PT(801) OR ROM64_INSTR_PT(808) + OR ROM64_INSTR_PT(809) OR ROM64_INSTR_PT(811) + OR ROM64_INSTR_PT(813) OR ROM64_INSTR_PT(822) + OR ROM64_INSTR_PT(824) OR ROM64_INSTR_PT(846) + OR ROM64_INSTR_PT(849) OR ROM64_INSTR_PT(852) + OR ROM64_INSTR_PT(854) OR ROM64_INSTR_PT(855) + OR ROM64_INSTR_PT(869) OR ROM64_INSTR_PT(872) + OR ROM64_INSTR_PT(883) OR ROM64_INSTR_PT(886) + ); +MQQ894:TEMPLATE(3) <= + (ROM64_INSTR_PT(2) OR ROM64_INSTR_PT(5) + OR ROM64_INSTR_PT(6) OR ROM64_INSTR_PT(9) + OR ROM64_INSTR_PT(10) OR ROM64_INSTR_PT(11) + OR ROM64_INSTR_PT(14) OR ROM64_INSTR_PT(15) + OR ROM64_INSTR_PT(17) OR ROM64_INSTR_PT(18) + OR ROM64_INSTR_PT(20) OR ROM64_INSTR_PT(21) + OR ROM64_INSTR_PT(22) OR ROM64_INSTR_PT(25) + OR ROM64_INSTR_PT(28) OR ROM64_INSTR_PT(29) + OR ROM64_INSTR_PT(33) OR ROM64_INSTR_PT(34) + OR ROM64_INSTR_PT(35) OR ROM64_INSTR_PT(36) + OR ROM64_INSTR_PT(38) OR ROM64_INSTR_PT(39) + OR ROM64_INSTR_PT(41) OR ROM64_INSTR_PT(42) + OR ROM64_INSTR_PT(43) OR ROM64_INSTR_PT(45) + OR ROM64_INSTR_PT(49) OR ROM64_INSTR_PT(52) + OR ROM64_INSTR_PT(53) OR ROM64_INSTR_PT(56) + OR ROM64_INSTR_PT(60) OR ROM64_INSTR_PT(61) + OR ROM64_INSTR_PT(64) OR ROM64_INSTR_PT(66) + OR ROM64_INSTR_PT(69) OR ROM64_INSTR_PT(70) + OR ROM64_INSTR_PT(71) OR ROM64_INSTR_PT(73) + OR ROM64_INSTR_PT(75) OR ROM64_INSTR_PT(76) + OR ROM64_INSTR_PT(77) OR ROM64_INSTR_PT(78) + OR ROM64_INSTR_PT(80) OR ROM64_INSTR_PT(82) + OR ROM64_INSTR_PT(83) OR ROM64_INSTR_PT(84) + OR ROM64_INSTR_PT(86) OR ROM64_INSTR_PT(89) + OR ROM64_INSTR_PT(90) OR ROM64_INSTR_PT(92) + OR ROM64_INSTR_PT(93) OR ROM64_INSTR_PT(95) + OR ROM64_INSTR_PT(96) OR ROM64_INSTR_PT(97) + OR ROM64_INSTR_PT(98) OR ROM64_INSTR_PT(99) + OR ROM64_INSTR_PT(101) OR ROM64_INSTR_PT(102) + OR ROM64_INSTR_PT(104) OR ROM64_INSTR_PT(106) + OR ROM64_INSTR_PT(108) OR ROM64_INSTR_PT(109) + OR ROM64_INSTR_PT(110) OR ROM64_INSTR_PT(113) + OR ROM64_INSTR_PT(114) OR ROM64_INSTR_PT(115) + OR ROM64_INSTR_PT(116) OR ROM64_INSTR_PT(117) + OR ROM64_INSTR_PT(118) OR ROM64_INSTR_PT(124) + OR ROM64_INSTR_PT(127) OR ROM64_INSTR_PT(133) + OR ROM64_INSTR_PT(136) OR ROM64_INSTR_PT(140) + OR ROM64_INSTR_PT(142) OR ROM64_INSTR_PT(144) + OR ROM64_INSTR_PT(145) OR ROM64_INSTR_PT(146) + OR ROM64_INSTR_PT(147) OR ROM64_INSTR_PT(148) + OR ROM64_INSTR_PT(150) OR ROM64_INSTR_PT(151) + OR ROM64_INSTR_PT(153) OR ROM64_INSTR_PT(155) + OR ROM64_INSTR_PT(160) OR ROM64_INSTR_PT(161) + OR ROM64_INSTR_PT(164) OR ROM64_INSTR_PT(166) + OR ROM64_INSTR_PT(168) OR ROM64_INSTR_PT(169) + OR ROM64_INSTR_PT(171) OR ROM64_INSTR_PT(172) + OR ROM64_INSTR_PT(173) OR ROM64_INSTR_PT(174) + OR ROM64_INSTR_PT(175) OR ROM64_INSTR_PT(177) + OR ROM64_INSTR_PT(179) OR ROM64_INSTR_PT(180) + OR ROM64_INSTR_PT(181) OR ROM64_INSTR_PT(182) + OR ROM64_INSTR_PT(183) OR ROM64_INSTR_PT(184) + OR ROM64_INSTR_PT(186) OR ROM64_INSTR_PT(187) + OR ROM64_INSTR_PT(188) OR ROM64_INSTR_PT(191) + OR ROM64_INSTR_PT(194) OR ROM64_INSTR_PT(199) + OR ROM64_INSTR_PT(201) OR ROM64_INSTR_PT(202) + OR ROM64_INSTR_PT(203) OR ROM64_INSTR_PT(205) + OR ROM64_INSTR_PT(206) OR ROM64_INSTR_PT(207) + OR ROM64_INSTR_PT(208) OR ROM64_INSTR_PT(209) + OR ROM64_INSTR_PT(211) OR ROM64_INSTR_PT(215) + OR ROM64_INSTR_PT(216) OR ROM64_INSTR_PT(217) + OR ROM64_INSTR_PT(218) OR ROM64_INSTR_PT(219) + OR ROM64_INSTR_PT(221) OR ROM64_INSTR_PT(222) + OR ROM64_INSTR_PT(223) OR ROM64_INSTR_PT(225) + OR ROM64_INSTR_PT(226) OR ROM64_INSTR_PT(228) + OR ROM64_INSTR_PT(229) OR ROM64_INSTR_PT(230) + OR ROM64_INSTR_PT(231) OR ROM64_INSTR_PT(233) + OR ROM64_INSTR_PT(238) OR ROM64_INSTR_PT(240) + OR ROM64_INSTR_PT(242) OR ROM64_INSTR_PT(243) + OR ROM64_INSTR_PT(245) OR ROM64_INSTR_PT(247) + OR ROM64_INSTR_PT(249) OR ROM64_INSTR_PT(252) + OR ROM64_INSTR_PT(253) OR ROM64_INSTR_PT(254) + OR ROM64_INSTR_PT(257) OR ROM64_INSTR_PT(258) + OR ROM64_INSTR_PT(259) OR ROM64_INSTR_PT(260) + OR ROM64_INSTR_PT(261) OR ROM64_INSTR_PT(264) + OR ROM64_INSTR_PT(265) OR ROM64_INSTR_PT(268) + OR ROM64_INSTR_PT(269) OR ROM64_INSTR_PT(270) + OR ROM64_INSTR_PT(271) OR ROM64_INSTR_PT(272) + OR ROM64_INSTR_PT(273) OR ROM64_INSTR_PT(274) + OR ROM64_INSTR_PT(275) OR ROM64_INSTR_PT(277) + OR ROM64_INSTR_PT(280) OR ROM64_INSTR_PT(281) + OR ROM64_INSTR_PT(282) OR ROM64_INSTR_PT(284) + OR ROM64_INSTR_PT(287) OR ROM64_INSTR_PT(288) + OR ROM64_INSTR_PT(290) OR ROM64_INSTR_PT(293) + OR ROM64_INSTR_PT(294) OR ROM64_INSTR_PT(295) + OR ROM64_INSTR_PT(298) OR ROM64_INSTR_PT(299) + OR ROM64_INSTR_PT(302) OR ROM64_INSTR_PT(304) + OR ROM64_INSTR_PT(305) OR ROM64_INSTR_PT(307) + OR ROM64_INSTR_PT(309) OR ROM64_INSTR_PT(311) + OR ROM64_INSTR_PT(313) OR ROM64_INSTR_PT(315) + OR ROM64_INSTR_PT(319) OR ROM64_INSTR_PT(324) + OR ROM64_INSTR_PT(325) OR ROM64_INSTR_PT(327) + OR ROM64_INSTR_PT(331) OR ROM64_INSTR_PT(332) + OR ROM64_INSTR_PT(334) OR ROM64_INSTR_PT(339) + OR ROM64_INSTR_PT(340) OR ROM64_INSTR_PT(341) + OR ROM64_INSTR_PT(342) OR ROM64_INSTR_PT(348) + OR ROM64_INSTR_PT(350) OR ROM64_INSTR_PT(352) + OR ROM64_INSTR_PT(353) OR ROM64_INSTR_PT(359) + OR ROM64_INSTR_PT(361) OR ROM64_INSTR_PT(364) + OR ROM64_INSTR_PT(365) OR ROM64_INSTR_PT(366) + OR ROM64_INSTR_PT(369) OR ROM64_INSTR_PT(371) + OR ROM64_INSTR_PT(372) OR ROM64_INSTR_PT(374) + OR ROM64_INSTR_PT(375) OR ROM64_INSTR_PT(378) + OR ROM64_INSTR_PT(379) OR ROM64_INSTR_PT(381) + OR ROM64_INSTR_PT(383) OR ROM64_INSTR_PT(384) + OR ROM64_INSTR_PT(385) OR ROM64_INSTR_PT(388) + OR ROM64_INSTR_PT(389) OR ROM64_INSTR_PT(391) + OR ROM64_INSTR_PT(394) OR ROM64_INSTR_PT(395) + OR ROM64_INSTR_PT(396) OR ROM64_INSTR_PT(397) + OR ROM64_INSTR_PT(401) OR ROM64_INSTR_PT(403) + OR ROM64_INSTR_PT(404) OR ROM64_INSTR_PT(405) + OR ROM64_INSTR_PT(406) OR ROM64_INSTR_PT(408) + OR ROM64_INSTR_PT(409) OR ROM64_INSTR_PT(410) + OR ROM64_INSTR_PT(413) OR ROM64_INSTR_PT(414) + OR ROM64_INSTR_PT(415) OR ROM64_INSTR_PT(418) + OR ROM64_INSTR_PT(419) OR ROM64_INSTR_PT(420) + OR ROM64_INSTR_PT(422) OR ROM64_INSTR_PT(424) + OR ROM64_INSTR_PT(425) OR ROM64_INSTR_PT(426) + OR ROM64_INSTR_PT(427) OR ROM64_INSTR_PT(428) + OR ROM64_INSTR_PT(429) OR ROM64_INSTR_PT(430) + OR ROM64_INSTR_PT(437) OR ROM64_INSTR_PT(438) + OR ROM64_INSTR_PT(439) OR ROM64_INSTR_PT(440) + OR ROM64_INSTR_PT(441) OR ROM64_INSTR_PT(443) + OR ROM64_INSTR_PT(445) OR ROM64_INSTR_PT(446) + OR ROM64_INSTR_PT(448) OR ROM64_INSTR_PT(451) + OR ROM64_INSTR_PT(453) OR ROM64_INSTR_PT(454) + OR ROM64_INSTR_PT(455) OR ROM64_INSTR_PT(456) + OR ROM64_INSTR_PT(457) OR ROM64_INSTR_PT(458) + OR ROM64_INSTR_PT(460) OR ROM64_INSTR_PT(463) + OR ROM64_INSTR_PT(464) OR ROM64_INSTR_PT(466) + OR ROM64_INSTR_PT(467) OR ROM64_INSTR_PT(468) + OR ROM64_INSTR_PT(470) OR ROM64_INSTR_PT(471) + OR ROM64_INSTR_PT(472) OR ROM64_INSTR_PT(473) + OR ROM64_INSTR_PT(474) OR ROM64_INSTR_PT(475) + OR ROM64_INSTR_PT(478) OR ROM64_INSTR_PT(481) + OR ROM64_INSTR_PT(482) OR ROM64_INSTR_PT(483) + OR ROM64_INSTR_PT(484) OR ROM64_INSTR_PT(485) + OR ROM64_INSTR_PT(488) OR ROM64_INSTR_PT(490) + OR ROM64_INSTR_PT(491) OR ROM64_INSTR_PT(493) + OR ROM64_INSTR_PT(495) OR ROM64_INSTR_PT(497) + OR ROM64_INSTR_PT(498) OR ROM64_INSTR_PT(503) + OR ROM64_INSTR_PT(505) OR ROM64_INSTR_PT(506) + OR ROM64_INSTR_PT(508) OR ROM64_INSTR_PT(509) + OR ROM64_INSTR_PT(510) OR ROM64_INSTR_PT(511) + OR ROM64_INSTR_PT(516) OR ROM64_INSTR_PT(517) + OR ROM64_INSTR_PT(519) OR ROM64_INSTR_PT(520) + OR ROM64_INSTR_PT(521) OR ROM64_INSTR_PT(522) + OR ROM64_INSTR_PT(523) OR ROM64_INSTR_PT(525) + OR ROM64_INSTR_PT(532) OR ROM64_INSTR_PT(534) + OR ROM64_INSTR_PT(538) OR ROM64_INSTR_PT(542) + OR ROM64_INSTR_PT(546) OR ROM64_INSTR_PT(549) + OR ROM64_INSTR_PT(551) OR ROM64_INSTR_PT(552) + OR ROM64_INSTR_PT(553) OR ROM64_INSTR_PT(554) + OR ROM64_INSTR_PT(555) OR ROM64_INSTR_PT(558) + OR ROM64_INSTR_PT(559) OR ROM64_INSTR_PT(562) + OR ROM64_INSTR_PT(563) OR ROM64_INSTR_PT(564) + OR ROM64_INSTR_PT(566) OR ROM64_INSTR_PT(569) + OR ROM64_INSTR_PT(570) OR ROM64_INSTR_PT(571) + OR ROM64_INSTR_PT(572) OR ROM64_INSTR_PT(575) + OR ROM64_INSTR_PT(576) OR ROM64_INSTR_PT(579) + OR ROM64_INSTR_PT(580) OR ROM64_INSTR_PT(581) + OR ROM64_INSTR_PT(582) OR ROM64_INSTR_PT(583) + OR ROM64_INSTR_PT(584) OR ROM64_INSTR_PT(585) + OR ROM64_INSTR_PT(586) OR ROM64_INSTR_PT(587) + OR ROM64_INSTR_PT(588) OR ROM64_INSTR_PT(589) + OR ROM64_INSTR_PT(590) OR ROM64_INSTR_PT(592) + OR ROM64_INSTR_PT(595) OR ROM64_INSTR_PT(596) + OR ROM64_INSTR_PT(597) OR ROM64_INSTR_PT(598) + OR ROM64_INSTR_PT(600) OR ROM64_INSTR_PT(601) + OR ROM64_INSTR_PT(603) OR ROM64_INSTR_PT(604) + OR ROM64_INSTR_PT(606) OR ROM64_INSTR_PT(608) + OR ROM64_INSTR_PT(610) OR ROM64_INSTR_PT(611) + OR ROM64_INSTR_PT(612) OR ROM64_INSTR_PT(613) + OR ROM64_INSTR_PT(614) OR ROM64_INSTR_PT(615) + OR ROM64_INSTR_PT(616) OR ROM64_INSTR_PT(617) + OR ROM64_INSTR_PT(618) OR ROM64_INSTR_PT(620) + OR ROM64_INSTR_PT(623) OR ROM64_INSTR_PT(626) + OR ROM64_INSTR_PT(627) OR ROM64_INSTR_PT(628) + OR ROM64_INSTR_PT(629) OR ROM64_INSTR_PT(632) + OR ROM64_INSTR_PT(633) OR ROM64_INSTR_PT(635) + OR ROM64_INSTR_PT(636) OR ROM64_INSTR_PT(639) + OR ROM64_INSTR_PT(642) OR ROM64_INSTR_PT(644) + OR ROM64_INSTR_PT(654) OR ROM64_INSTR_PT(657) + OR ROM64_INSTR_PT(659) OR ROM64_INSTR_PT(660) + OR ROM64_INSTR_PT(663) OR ROM64_INSTR_PT(664) + OR ROM64_INSTR_PT(666) OR ROM64_INSTR_PT(668) + OR ROM64_INSTR_PT(675) OR ROM64_INSTR_PT(678) + OR ROM64_INSTR_PT(681) OR ROM64_INSTR_PT(682) + OR ROM64_INSTR_PT(691) OR ROM64_INSTR_PT(695) + OR ROM64_INSTR_PT(703) OR ROM64_INSTR_PT(706) + OR ROM64_INSTR_PT(709) OR ROM64_INSTR_PT(713) + OR ROM64_INSTR_PT(717) OR ROM64_INSTR_PT(721) + OR ROM64_INSTR_PT(722) OR ROM64_INSTR_PT(723) + OR ROM64_INSTR_PT(724) OR ROM64_INSTR_PT(728) + OR ROM64_INSTR_PT(731) OR ROM64_INSTR_PT(733) + OR ROM64_INSTR_PT(735) OR ROM64_INSTR_PT(736) + OR ROM64_INSTR_PT(738) OR ROM64_INSTR_PT(744) + OR ROM64_INSTR_PT(759) OR ROM64_INSTR_PT(761) + OR ROM64_INSTR_PT(766) OR ROM64_INSTR_PT(769) + OR ROM64_INSTR_PT(776) OR ROM64_INSTR_PT(781) + OR ROM64_INSTR_PT(794) OR ROM64_INSTR_PT(797) + OR ROM64_INSTR_PT(798) OR ROM64_INSTR_PT(809) + OR ROM64_INSTR_PT(811) OR ROM64_INSTR_PT(813) + OR ROM64_INSTR_PT(822) OR ROM64_INSTR_PT(824) + OR ROM64_INSTR_PT(834) OR ROM64_INSTR_PT(846) + OR ROM64_INSTR_PT(854) OR ROM64_INSTR_PT(855) + OR ROM64_INSTR_PT(856) OR ROM64_INSTR_PT(858) + OR ROM64_INSTR_PT(864) OR ROM64_INSTR_PT(869) + OR ROM64_INSTR_PT(870) OR ROM64_INSTR_PT(883) + ); +MQQ895:TEMPLATE(4) <= + (ROM64_INSTR_PT(2) OR ROM64_INSTR_PT(5) + OR ROM64_INSTR_PT(6) OR ROM64_INSTR_PT(10) + OR ROM64_INSTR_PT(14) OR ROM64_INSTR_PT(15) + OR ROM64_INSTR_PT(18) OR ROM64_INSTR_PT(20) + OR ROM64_INSTR_PT(25) OR ROM64_INSTR_PT(28) + OR ROM64_INSTR_PT(29) OR ROM64_INSTR_PT(33) + OR ROM64_INSTR_PT(35) OR ROM64_INSTR_PT(36) + OR ROM64_INSTR_PT(39) OR ROM64_INSTR_PT(41) + OR ROM64_INSTR_PT(42) OR ROM64_INSTR_PT(43) + OR ROM64_INSTR_PT(45) OR ROM64_INSTR_PT(53) + OR ROM64_INSTR_PT(56) OR ROM64_INSTR_PT(60) + OR ROM64_INSTR_PT(65) OR ROM64_INSTR_PT(66) + OR ROM64_INSTR_PT(69) OR ROM64_INSTR_PT(73) + OR ROM64_INSTR_PT(74) OR ROM64_INSTR_PT(77) + OR ROM64_INSTR_PT(78) OR ROM64_INSTR_PT(79) + OR ROM64_INSTR_PT(80) OR ROM64_INSTR_PT(82) + OR ROM64_INSTR_PT(84) OR ROM64_INSTR_PT(89) + OR ROM64_INSTR_PT(92) OR ROM64_INSTR_PT(95) + OR ROM64_INSTR_PT(96) OR ROM64_INSTR_PT(97) + OR ROM64_INSTR_PT(98) OR ROM64_INSTR_PT(101) + OR ROM64_INSTR_PT(104) OR ROM64_INSTR_PT(106) + OR ROM64_INSTR_PT(108) OR ROM64_INSTR_PT(109) + OR ROM64_INSTR_PT(110) OR ROM64_INSTR_PT(112) + OR ROM64_INSTR_PT(114) OR ROM64_INSTR_PT(116) + OR ROM64_INSTR_PT(119) OR ROM64_INSTR_PT(124) + OR ROM64_INSTR_PT(129) OR ROM64_INSTR_PT(139) + OR ROM64_INSTR_PT(140) OR ROM64_INSTR_PT(142) + OR ROM64_INSTR_PT(143) OR ROM64_INSTR_PT(145) + OR ROM64_INSTR_PT(146) OR ROM64_INSTR_PT(147) + OR ROM64_INSTR_PT(150) OR ROM64_INSTR_PT(151) + OR ROM64_INSTR_PT(153) OR ROM64_INSTR_PT(155) + OR ROM64_INSTR_PT(158) OR ROM64_INSTR_PT(160) + OR ROM64_INSTR_PT(161) OR ROM64_INSTR_PT(166) + OR ROM64_INSTR_PT(168) OR ROM64_INSTR_PT(172) + OR ROM64_INSTR_PT(173) OR ROM64_INSTR_PT(174) + OR ROM64_INSTR_PT(175) OR ROM64_INSTR_PT(176) + OR ROM64_INSTR_PT(177) OR ROM64_INSTR_PT(179) + OR ROM64_INSTR_PT(181) OR ROM64_INSTR_PT(182) + OR ROM64_INSTR_PT(183) OR ROM64_INSTR_PT(184) + OR ROM64_INSTR_PT(187) OR ROM64_INSTR_PT(188) + OR ROM64_INSTR_PT(191) OR ROM64_INSTR_PT(193) + OR ROM64_INSTR_PT(194) OR ROM64_INSTR_PT(202) + OR ROM64_INSTR_PT(203) OR ROM64_INSTR_PT(205) + OR ROM64_INSTR_PT(206) OR ROM64_INSTR_PT(207) + OR ROM64_INSTR_PT(208) OR ROM64_INSTR_PT(209) + OR ROM64_INSTR_PT(211) OR ROM64_INSTR_PT(216) + OR ROM64_INSTR_PT(219) OR ROM64_INSTR_PT(221) + OR ROM64_INSTR_PT(225) OR ROM64_INSTR_PT(228) + OR ROM64_INSTR_PT(229) OR ROM64_INSTR_PT(230) + OR ROM64_INSTR_PT(231) OR ROM64_INSTR_PT(233) + OR ROM64_INSTR_PT(237) OR ROM64_INSTR_PT(240) + OR ROM64_INSTR_PT(242) OR ROM64_INSTR_PT(243) + OR ROM64_INSTR_PT(247) OR ROM64_INSTR_PT(253) + OR ROM64_INSTR_PT(254) OR ROM64_INSTR_PT(257) + OR ROM64_INSTR_PT(258) OR ROM64_INSTR_PT(259) + OR ROM64_INSTR_PT(260) OR ROM64_INSTR_PT(261) + OR ROM64_INSTR_PT(265) OR ROM64_INSTR_PT(269) + OR ROM64_INSTR_PT(273) OR ROM64_INSTR_PT(274) + OR ROM64_INSTR_PT(277) OR ROM64_INSTR_PT(281) + OR ROM64_INSTR_PT(284) OR ROM64_INSTR_PT(288) + OR ROM64_INSTR_PT(290) OR ROM64_INSTR_PT(292) + OR ROM64_INSTR_PT(294) OR ROM64_INSTR_PT(295) + OR ROM64_INSTR_PT(304) OR ROM64_INSTR_PT(307) + OR ROM64_INSTR_PT(309) OR ROM64_INSTR_PT(311) + OR ROM64_INSTR_PT(313) OR ROM64_INSTR_PT(319) + OR ROM64_INSTR_PT(320) OR ROM64_INSTR_PT(324) + OR ROM64_INSTR_PT(325) OR ROM64_INSTR_PT(327) + OR ROM64_INSTR_PT(332) OR ROM64_INSTR_PT(334) + OR ROM64_INSTR_PT(339) OR ROM64_INSTR_PT(340) + OR ROM64_INSTR_PT(341) OR ROM64_INSTR_PT(342) + OR ROM64_INSTR_PT(348) OR ROM64_INSTR_PT(350) + OR ROM64_INSTR_PT(352) OR ROM64_INSTR_PT(353) + OR ROM64_INSTR_PT(358) OR ROM64_INSTR_PT(359) + OR ROM64_INSTR_PT(360) OR ROM64_INSTR_PT(361) + OR ROM64_INSTR_PT(362) OR ROM64_INSTR_PT(365) + OR ROM64_INSTR_PT(366) OR ROM64_INSTR_PT(368) + OR ROM64_INSTR_PT(369) OR ROM64_INSTR_PT(371) + OR ROM64_INSTR_PT(372) OR ROM64_INSTR_PT(374) + OR ROM64_INSTR_PT(377) OR ROM64_INSTR_PT(378) + OR ROM64_INSTR_PT(379) OR ROM64_INSTR_PT(381) + OR ROM64_INSTR_PT(384) OR ROM64_INSTR_PT(388) + OR ROM64_INSTR_PT(389) OR ROM64_INSTR_PT(392) + OR ROM64_INSTR_PT(394) OR ROM64_INSTR_PT(395) + OR ROM64_INSTR_PT(396) OR ROM64_INSTR_PT(401) + OR ROM64_INSTR_PT(402) OR ROM64_INSTR_PT(403) + OR ROM64_INSTR_PT(405) OR ROM64_INSTR_PT(406) + OR ROM64_INSTR_PT(408) OR ROM64_INSTR_PT(409) + OR ROM64_INSTR_PT(413) OR ROM64_INSTR_PT(418) + OR ROM64_INSTR_PT(419) OR ROM64_INSTR_PT(420) + OR ROM64_INSTR_PT(422) OR ROM64_INSTR_PT(425) + OR ROM64_INSTR_PT(426) OR ROM64_INSTR_PT(428) + OR ROM64_INSTR_PT(429) OR ROM64_INSTR_PT(430) + OR ROM64_INSTR_PT(438) OR ROM64_INSTR_PT(439) + OR ROM64_INSTR_PT(440) OR ROM64_INSTR_PT(443) + OR ROM64_INSTR_PT(445) OR ROM64_INSTR_PT(446) + OR ROM64_INSTR_PT(448) OR ROM64_INSTR_PT(451) + OR ROM64_INSTR_PT(453) OR ROM64_INSTR_PT(454) + OR ROM64_INSTR_PT(455) OR ROM64_INSTR_PT(456) + OR ROM64_INSTR_PT(458) OR ROM64_INSTR_PT(460) + OR ROM64_INSTR_PT(463) OR ROM64_INSTR_PT(464) + OR ROM64_INSTR_PT(466) OR ROM64_INSTR_PT(467) + OR ROM64_INSTR_PT(468) OR ROM64_INSTR_PT(470) + OR ROM64_INSTR_PT(471) OR ROM64_INSTR_PT(472) + OR ROM64_INSTR_PT(473) OR ROM64_INSTR_PT(474) + OR ROM64_INSTR_PT(475) OR ROM64_INSTR_PT(477) + OR ROM64_INSTR_PT(483) OR ROM64_INSTR_PT(490) + OR ROM64_INSTR_PT(491) OR ROM64_INSTR_PT(497) + OR ROM64_INSTR_PT(498) OR ROM64_INSTR_PT(499) + OR ROM64_INSTR_PT(503) OR ROM64_INSTR_PT(506) + OR ROM64_INSTR_PT(508) OR ROM64_INSTR_PT(510) + OR ROM64_INSTR_PT(516) OR ROM64_INSTR_PT(517) + OR ROM64_INSTR_PT(519) OR ROM64_INSTR_PT(520) + OR ROM64_INSTR_PT(527) OR ROM64_INSTR_PT(532) + OR ROM64_INSTR_PT(538) OR ROM64_INSTR_PT(542) + OR ROM64_INSTR_PT(546) OR ROM64_INSTR_PT(549) + OR ROM64_INSTR_PT(551) OR ROM64_INSTR_PT(553) + OR ROM64_INSTR_PT(554) OR ROM64_INSTR_PT(557) + OR ROM64_INSTR_PT(559) OR ROM64_INSTR_PT(562) + OR ROM64_INSTR_PT(564) OR ROM64_INSTR_PT(566) + OR ROM64_INSTR_PT(570) OR ROM64_INSTR_PT(571) + OR ROM64_INSTR_PT(572) OR ROM64_INSTR_PT(575) + OR ROM64_INSTR_PT(580) OR ROM64_INSTR_PT(581) + OR ROM64_INSTR_PT(586) OR ROM64_INSTR_PT(589) + OR ROM64_INSTR_PT(590) OR ROM64_INSTR_PT(593) + OR ROM64_INSTR_PT(596) OR ROM64_INSTR_PT(597) + OR ROM64_INSTR_PT(598) OR ROM64_INSTR_PT(601) + OR ROM64_INSTR_PT(602) OR ROM64_INSTR_PT(603) + OR ROM64_INSTR_PT(604) OR ROM64_INSTR_PT(606) + OR ROM64_INSTR_PT(610) OR ROM64_INSTR_PT(611) + OR ROM64_INSTR_PT(612) OR ROM64_INSTR_PT(613) + OR ROM64_INSTR_PT(614) OR ROM64_INSTR_PT(615) + OR ROM64_INSTR_PT(616) OR ROM64_INSTR_PT(617) + OR ROM64_INSTR_PT(620) OR ROM64_INSTR_PT(626) + OR ROM64_INSTR_PT(627) OR ROM64_INSTR_PT(628) + OR ROM64_INSTR_PT(632) OR ROM64_INSTR_PT(635) + OR ROM64_INSTR_PT(636) OR ROM64_INSTR_PT(641) + OR ROM64_INSTR_PT(653) OR ROM64_INSTR_PT(654) + OR ROM64_INSTR_PT(659) OR ROM64_INSTR_PT(660) + OR ROM64_INSTR_PT(663) OR ROM64_INSTR_PT(664) + OR ROM64_INSTR_PT(668) OR ROM64_INSTR_PT(675) + OR ROM64_INSTR_PT(681) OR ROM64_INSTR_PT(682) + OR ROM64_INSTR_PT(685) OR ROM64_INSTR_PT(691) + OR ROM64_INSTR_PT(694) OR ROM64_INSTR_PT(695) + OR ROM64_INSTR_PT(702) OR ROM64_INSTR_PT(703) + OR ROM64_INSTR_PT(706) OR ROM64_INSTR_PT(709) + OR ROM64_INSTR_PT(713) OR ROM64_INSTR_PT(716) + OR ROM64_INSTR_PT(717) OR ROM64_INSTR_PT(721) + OR ROM64_INSTR_PT(723) OR ROM64_INSTR_PT(724) + OR ROM64_INSTR_PT(728) OR ROM64_INSTR_PT(733) + OR ROM64_INSTR_PT(735) OR ROM64_INSTR_PT(736) + OR ROM64_INSTR_PT(738) OR ROM64_INSTR_PT(741) + OR ROM64_INSTR_PT(759) OR ROM64_INSTR_PT(766) + OR ROM64_INSTR_PT(770) OR ROM64_INSTR_PT(781) + OR ROM64_INSTR_PT(794) OR ROM64_INSTR_PT(797) + OR ROM64_INSTR_PT(798) OR ROM64_INSTR_PT(801) + OR ROM64_INSTR_PT(808) OR ROM64_INSTR_PT(809) + OR ROM64_INSTR_PT(811) OR ROM64_INSTR_PT(813) + OR ROM64_INSTR_PT(822) OR ROM64_INSTR_PT(824) + OR ROM64_INSTR_PT(832) OR ROM64_INSTR_PT(834) + OR ROM64_INSTR_PT(846) OR ROM64_INSTR_PT(849) + OR ROM64_INSTR_PT(852) OR ROM64_INSTR_PT(854) + OR ROM64_INSTR_PT(855) OR ROM64_INSTR_PT(858) + OR ROM64_INSTR_PT(869) OR ROM64_INSTR_PT(873) + OR ROM64_INSTR_PT(883)); +MQQ896:TEMPLATE(5) <= + (ROM64_INSTR_PT(4) OR ROM64_INSTR_PT(6) + OR ROM64_INSTR_PT(7) OR ROM64_INSTR_PT(8) + OR ROM64_INSTR_PT(11) OR ROM64_INSTR_PT(14) + OR ROM64_INSTR_PT(15) OR ROM64_INSTR_PT(18) + OR ROM64_INSTR_PT(21) OR ROM64_INSTR_PT(35) + OR ROM64_INSTR_PT(38) OR ROM64_INSTR_PT(41) + OR ROM64_INSTR_PT(42) OR ROM64_INSTR_PT(45) + OR ROM64_INSTR_PT(49) OR ROM64_INSTR_PT(51) + OR ROM64_INSTR_PT(52) OR ROM64_INSTR_PT(53) + OR ROM64_INSTR_PT(56) OR ROM64_INSTR_PT(57) + OR ROM64_INSTR_PT(61) OR ROM64_INSTR_PT(64) + OR ROM64_INSTR_PT(68) OR ROM64_INSTR_PT(69) + OR ROM64_INSTR_PT(70) OR ROM64_INSTR_PT(73) + OR ROM64_INSTR_PT(82) OR ROM64_INSTR_PT(83) + OR ROM64_INSTR_PT(84) OR ROM64_INSTR_PT(86) + OR ROM64_INSTR_PT(90) OR ROM64_INSTR_PT(93) + OR ROM64_INSTR_PT(95) OR ROM64_INSTR_PT(100) + OR ROM64_INSTR_PT(101) OR ROM64_INSTR_PT(102) + OR ROM64_INSTR_PT(105) OR ROM64_INSTR_PT(108) + OR ROM64_INSTR_PT(109) OR ROM64_INSTR_PT(115) + OR ROM64_INSTR_PT(116) OR ROM64_INSTR_PT(117) + OR ROM64_INSTR_PT(118) OR ROM64_INSTR_PT(124) + OR ROM64_INSTR_PT(128) OR ROM64_INSTR_PT(132) + OR ROM64_INSTR_PT(133) OR ROM64_INSTR_PT(137) + OR ROM64_INSTR_PT(140) OR ROM64_INSTR_PT(143) + OR ROM64_INSTR_PT(144) OR ROM64_INSTR_PT(145) + OR ROM64_INSTR_PT(153) OR ROM64_INSTR_PT(155) + OR ROM64_INSTR_PT(157) OR ROM64_INSTR_PT(158) + OR ROM64_INSTR_PT(162) OR ROM64_INSTR_PT(164) + OR ROM64_INSTR_PT(168) OR ROM64_INSTR_PT(169) + OR ROM64_INSTR_PT(170) OR ROM64_INSTR_PT(177) + OR ROM64_INSTR_PT(180) OR ROM64_INSTR_PT(181) + OR ROM64_INSTR_PT(183) OR ROM64_INSTR_PT(185) + OR ROM64_INSTR_PT(186) OR ROM64_INSTR_PT(194) + OR ROM64_INSTR_PT(196) OR ROM64_INSTR_PT(201) + OR ROM64_INSTR_PT(203) OR ROM64_INSTR_PT(204) + OR ROM64_INSTR_PT(205) OR ROM64_INSTR_PT(206) + OR ROM64_INSTR_PT(211) OR ROM64_INSTR_PT(215) + OR ROM64_INSTR_PT(218) OR ROM64_INSTR_PT(219) + OR ROM64_INSTR_PT(223) OR ROM64_INSTR_PT(226) + OR ROM64_INSTR_PT(233) OR ROM64_INSTR_PT(238) + OR ROM64_INSTR_PT(241) OR ROM64_INSTR_PT(243) + OR ROM64_INSTR_PT(244) OR ROM64_INSTR_PT(245) + OR ROM64_INSTR_PT(249) OR ROM64_INSTR_PT(254) + OR ROM64_INSTR_PT(258) OR ROM64_INSTR_PT(260) + OR ROM64_INSTR_PT(263) OR ROM64_INSTR_PT(264) + OR ROM64_INSTR_PT(265) OR ROM64_INSTR_PT(268) + OR ROM64_INSTR_PT(269) OR ROM64_INSTR_PT(270) + OR ROM64_INSTR_PT(272) OR ROM64_INSTR_PT(276) + OR ROM64_INSTR_PT(278) OR ROM64_INSTR_PT(280) + OR ROM64_INSTR_PT(282) OR ROM64_INSTR_PT(284) + OR ROM64_INSTR_PT(285) OR ROM64_INSTR_PT(287) + OR ROM64_INSTR_PT(290) OR ROM64_INSTR_PT(293) + OR ROM64_INSTR_PT(294) OR ROM64_INSTR_PT(297) + OR ROM64_INSTR_PT(302) OR ROM64_INSTR_PT(305) + OR ROM64_INSTR_PT(308) OR ROM64_INSTR_PT(311) + OR ROM64_INSTR_PT(312) OR ROM64_INSTR_PT(319) + OR ROM64_INSTR_PT(325) OR ROM64_INSTR_PT(339) + OR ROM64_INSTR_PT(348) OR ROM64_INSTR_PT(350) + OR ROM64_INSTR_PT(353) OR ROM64_INSTR_PT(355) + OR ROM64_INSTR_PT(358) OR ROM64_INSTR_PT(364) + OR ROM64_INSTR_PT(366) OR ROM64_INSTR_PT(367) + OR ROM64_INSTR_PT(370) OR ROM64_INSTR_PT(372) + OR ROM64_INSTR_PT(375) OR ROM64_INSTR_PT(378) + OR ROM64_INSTR_PT(379) OR ROM64_INSTR_PT(383) + OR ROM64_INSTR_PT(384) OR ROM64_INSTR_PT(385) + OR ROM64_INSTR_PT(391) OR ROM64_INSTR_PT(394) + OR ROM64_INSTR_PT(395) OR ROM64_INSTR_PT(397) + OR ROM64_INSTR_PT(399) OR ROM64_INSTR_PT(403) + OR ROM64_INSTR_PT(405) OR ROM64_INSTR_PT(409) + OR ROM64_INSTR_PT(410) OR ROM64_INSTR_PT(413) + OR ROM64_INSTR_PT(416) OR ROM64_INSTR_PT(417) + OR ROM64_INSTR_PT(418) OR ROM64_INSTR_PT(419) + OR ROM64_INSTR_PT(425) OR ROM64_INSTR_PT(426) + OR ROM64_INSTR_PT(427) OR ROM64_INSTR_PT(428) + OR ROM64_INSTR_PT(429) OR ROM64_INSTR_PT(430) + OR ROM64_INSTR_PT(432) OR ROM64_INSTR_PT(433) + OR ROM64_INSTR_PT(435) OR ROM64_INSTR_PT(438) + OR ROM64_INSTR_PT(439) OR ROM64_INSTR_PT(440) + OR ROM64_INSTR_PT(441) OR ROM64_INSTR_PT(443) + OR ROM64_INSTR_PT(445) OR ROM64_INSTR_PT(446) + OR ROM64_INSTR_PT(451) OR ROM64_INSTR_PT(453) + OR ROM64_INSTR_PT(454) OR ROM64_INSTR_PT(455) + OR ROM64_INSTR_PT(456) OR ROM64_INSTR_PT(457) + OR ROM64_INSTR_PT(460) OR ROM64_INSTR_PT(467) + OR ROM64_INSTR_PT(473) OR ROM64_INSTR_PT(475) + OR ROM64_INSTR_PT(478) OR ROM64_INSTR_PT(481) + OR ROM64_INSTR_PT(482) OR ROM64_INSTR_PT(484) + OR ROM64_INSTR_PT(485) OR ROM64_INSTR_PT(488) + OR ROM64_INSTR_PT(490) OR ROM64_INSTR_PT(493) + OR ROM64_INSTR_PT(495) OR ROM64_INSTR_PT(496) + OR ROM64_INSTR_PT(504) OR ROM64_INSTR_PT(506) + OR ROM64_INSTR_PT(510) OR ROM64_INSTR_PT(512) + OR ROM64_INSTR_PT(514) OR ROM64_INSTR_PT(519) + OR ROM64_INSTR_PT(522) OR ROM64_INSTR_PT(523) + OR ROM64_INSTR_PT(525) OR ROM64_INSTR_PT(530) + OR ROM64_INSTR_PT(531) OR ROM64_INSTR_PT(532) + OR ROM64_INSTR_PT(534) OR ROM64_INSTR_PT(539) + OR ROM64_INSTR_PT(542) OR ROM64_INSTR_PT(546) + OR ROM64_INSTR_PT(552) OR ROM64_INSTR_PT(553) + OR ROM64_INSTR_PT(554) OR ROM64_INSTR_PT(555) + OR ROM64_INSTR_PT(557) OR ROM64_INSTR_PT(559) + OR ROM64_INSTR_PT(563) OR ROM64_INSTR_PT(564) + OR ROM64_INSTR_PT(566) OR ROM64_INSTR_PT(568) + OR ROM64_INSTR_PT(570) OR ROM64_INSTR_PT(571) + OR ROM64_INSTR_PT(576) OR ROM64_INSTR_PT(577) + OR ROM64_INSTR_PT(580) OR ROM64_INSTR_PT(581) + OR ROM64_INSTR_PT(582) OR ROM64_INSTR_PT(583) + OR ROM64_INSTR_PT(584) OR ROM64_INSTR_PT(585) + OR ROM64_INSTR_PT(586) OR ROM64_INSTR_PT(587) + OR ROM64_INSTR_PT(589) OR ROM64_INSTR_PT(591) + OR ROM64_INSTR_PT(592) OR ROM64_INSTR_PT(604) + OR ROM64_INSTR_PT(606) OR ROM64_INSTR_PT(607) + OR ROM64_INSTR_PT(608) OR ROM64_INSTR_PT(611) + OR ROM64_INSTR_PT(615) OR ROM64_INSTR_PT(616) + OR ROM64_INSTR_PT(619) OR ROM64_INSTR_PT(625) + OR ROM64_INSTR_PT(626) OR ROM64_INSTR_PT(627) + OR ROM64_INSTR_PT(629) OR ROM64_INSTR_PT(633) + OR ROM64_INSTR_PT(636) OR ROM64_INSTR_PT(639) + OR ROM64_INSTR_PT(642) OR ROM64_INSTR_PT(643) + OR ROM64_INSTR_PT(655) OR ROM64_INSTR_PT(660) + OR ROM64_INSTR_PT(663) OR ROM64_INSTR_PT(664) + OR ROM64_INSTR_PT(666) OR ROM64_INSTR_PT(678) + OR ROM64_INSTR_PT(681) OR ROM64_INSTR_PT(695) + OR ROM64_INSTR_PT(698) OR ROM64_INSTR_PT(702) + OR ROM64_INSTR_PT(713) OR ROM64_INSTR_PT(716) + OR ROM64_INSTR_PT(721) OR ROM64_INSTR_PT(722) + OR ROM64_INSTR_PT(731) OR ROM64_INSTR_PT(736) + OR ROM64_INSTR_PT(753) OR ROM64_INSTR_PT(761) + OR ROM64_INSTR_PT(769) OR ROM64_INSTR_PT(770) + OR ROM64_INSTR_PT(798) OR ROM64_INSTR_PT(811) + OR ROM64_INSTR_PT(813) OR ROM64_INSTR_PT(823) + OR ROM64_INSTR_PT(824) OR ROM64_INSTR_PT(832) + OR ROM64_INSTR_PT(834) OR ROM64_INSTR_PT(846) + OR ROM64_INSTR_PT(854) OR ROM64_INSTR_PT(855) + OR ROM64_INSTR_PT(856) OR ROM64_INSTR_PT(858) + OR ROM64_INSTR_PT(864) OR ROM64_INSTR_PT(870) + OR ROM64_INSTR_PT(873)); +MQQ897:TEMPLATE(6) <= + ('0'); +MQQ898:TEMPLATE(7) <= + ('0'); +MQQ899:TEMPLATE(8) <= + ('0'); +MQQ900:TEMPLATE(9) <= + (ROM64_INSTR_PT(7) OR ROM64_INSTR_PT(9) + OR ROM64_INSTR_PT(11) OR ROM64_INSTR_PT(13) + OR ROM64_INSTR_PT(15) OR ROM64_INSTR_PT(22) + OR ROM64_INSTR_PT(25) OR ROM64_INSTR_PT(29) + OR ROM64_INSTR_PT(36) OR ROM64_INSTR_PT(38) + OR ROM64_INSTR_PT(42) OR ROM64_INSTR_PT(45) + OR ROM64_INSTR_PT(53) OR ROM64_INSTR_PT(55) + OR ROM64_INSTR_PT(56) OR ROM64_INSTR_PT(58) + OR ROM64_INSTR_PT(61) OR ROM64_INSTR_PT(70) + OR ROM64_INSTR_PT(71) OR ROM64_INSTR_PT(84) + OR ROM64_INSTR_PT(86) OR ROM64_INSTR_PT(90) + OR ROM64_INSTR_PT(93) OR ROM64_INSTR_PT(97) + OR ROM64_INSTR_PT(100) OR ROM64_INSTR_PT(102) + OR ROM64_INSTR_PT(104) OR ROM64_INSTR_PT(105) + OR ROM64_INSTR_PT(116) OR ROM64_INSTR_PT(119) + OR ROM64_INSTR_PT(124) OR ROM64_INSTR_PT(132) + OR ROM64_INSTR_PT(136) OR ROM64_INSTR_PT(137) + OR ROM64_INSTR_PT(143) OR ROM64_INSTR_PT(144) + OR ROM64_INSTR_PT(148) OR ROM64_INSTR_PT(154) + OR ROM64_INSTR_PT(155) OR ROM64_INSTR_PT(160) + OR ROM64_INSTR_PT(172) OR ROM64_INSTR_PT(174) + OR ROM64_INSTR_PT(176) OR ROM64_INSTR_PT(177) + OR ROM64_INSTR_PT(179) OR ROM64_INSTR_PT(180) + OR ROM64_INSTR_PT(181) OR ROM64_INSTR_PT(183) + OR ROM64_INSTR_PT(186) OR ROM64_INSTR_PT(193) + OR ROM64_INSTR_PT(201) OR ROM64_INSTR_PT(208) + OR ROM64_INSTR_PT(213) OR ROM64_INSTR_PT(215) + OR ROM64_INSTR_PT(216) OR ROM64_INSTR_PT(221) + OR ROM64_INSTR_PT(222) OR ROM64_INSTR_PT(225) + OR ROM64_INSTR_PT(226) OR ROM64_INSTR_PT(238) + OR ROM64_INSTR_PT(240) OR ROM64_INSTR_PT(242) + OR ROM64_INSTR_PT(243) OR ROM64_INSTR_PT(245) + OR ROM64_INSTR_PT(249) OR ROM64_INSTR_PT(259) + OR ROM64_INSTR_PT(261) OR ROM64_INSTR_PT(262) + OR ROM64_INSTR_PT(263) OR ROM64_INSTR_PT(265) + OR ROM64_INSTR_PT(270) OR ROM64_INSTR_PT(274) + OR ROM64_INSTR_PT(275) OR ROM64_INSTR_PT(276) + OR ROM64_INSTR_PT(277) OR ROM64_INSTR_PT(282) + OR ROM64_INSTR_PT(284) OR ROM64_INSTR_PT(285) + OR ROM64_INSTR_PT(286) OR ROM64_INSTR_PT(292) + OR ROM64_INSTR_PT(293) OR ROM64_INSTR_PT(297) + OR ROM64_INSTR_PT(299) OR ROM64_INSTR_PT(302) + OR ROM64_INSTR_PT(305) OR ROM64_INSTR_PT(311) + OR ROM64_INSTR_PT(315) OR ROM64_INSTR_PT(319) + OR ROM64_INSTR_PT(320) OR ROM64_INSTR_PT(322) + OR ROM64_INSTR_PT(341) OR ROM64_INSTR_PT(349) + OR ROM64_INSTR_PT(355) OR ROM64_INSTR_PT(359) + OR ROM64_INSTR_PT(362) OR ROM64_INSTR_PT(365) + OR ROM64_INSTR_PT(366) OR ROM64_INSTR_PT(369) + OR ROM64_INSTR_PT(372) OR ROM64_INSTR_PT(379) + OR ROM64_INSTR_PT(382) OR ROM64_INSTR_PT(383) + OR ROM64_INSTR_PT(385) OR ROM64_INSTR_PT(388) + OR ROM64_INSTR_PT(389) OR ROM64_INSTR_PT(392) + OR ROM64_INSTR_PT(394) OR ROM64_INSTR_PT(395) + OR ROM64_INSTR_PT(396) OR ROM64_INSTR_PT(402) + OR ROM64_INSTR_PT(403) OR ROM64_INSTR_PT(404) + OR ROM64_INSTR_PT(405) OR ROM64_INSTR_PT(410) + OR ROM64_INSTR_PT(413) OR ROM64_INSTR_PT(415) + OR ROM64_INSTR_PT(418) OR ROM64_INSTR_PT(425) + OR ROM64_INSTR_PT(426) OR ROM64_INSTR_PT(429) + OR ROM64_INSTR_PT(434) OR ROM64_INSTR_PT(435) + OR ROM64_INSTR_PT(437) OR ROM64_INSTR_PT(438) + OR ROM64_INSTR_PT(440) OR ROM64_INSTR_PT(445) + OR ROM64_INSTR_PT(446) OR ROM64_INSTR_PT(451) + OR ROM64_INSTR_PT(453) OR ROM64_INSTR_PT(456) + OR ROM64_INSTR_PT(457) OR ROM64_INSTR_PT(467) + OR ROM64_INSTR_PT(470) OR ROM64_INSTR_PT(473) + OR ROM64_INSTR_PT(474) OR ROM64_INSTR_PT(475) + OR ROM64_INSTR_PT(478) OR ROM64_INSTR_PT(482) + OR ROM64_INSTR_PT(485) OR ROM64_INSTR_PT(491) + OR ROM64_INSTR_PT(493) OR ROM64_INSTR_PT(495) + OR ROM64_INSTR_PT(498) OR ROM64_INSTR_PT(499) + OR ROM64_INSTR_PT(504) OR ROM64_INSTR_PT(505) + OR ROM64_INSTR_PT(507) OR ROM64_INSTR_PT(509) + OR ROM64_INSTR_PT(517) OR ROM64_INSTR_PT(519) + OR ROM64_INSTR_PT(520) OR ROM64_INSTR_PT(521) + OR ROM64_INSTR_PT(522) OR ROM64_INSTR_PT(532) + OR ROM64_INSTR_PT(534) OR ROM64_INSTR_PT(535) + OR ROM64_INSTR_PT(544) OR ROM64_INSTR_PT(546) + OR ROM64_INSTR_PT(549) OR ROM64_INSTR_PT(552) + OR ROM64_INSTR_PT(555) OR ROM64_INSTR_PT(558) + OR ROM64_INSTR_PT(559) OR ROM64_INSTR_PT(568) + OR ROM64_INSTR_PT(569) OR ROM64_INSTR_PT(571) + OR ROM64_INSTR_PT(572) OR ROM64_INSTR_PT(575) + OR ROM64_INSTR_PT(576) OR ROM64_INSTR_PT(590) + OR ROM64_INSTR_PT(591) OR ROM64_INSTR_PT(592) + OR ROM64_INSTR_PT(593) OR ROM64_INSTR_PT(595) + OR ROM64_INSTR_PT(606) OR ROM64_INSTR_PT(608) + OR ROM64_INSTR_PT(610) OR ROM64_INSTR_PT(612) + OR ROM64_INSTR_PT(615) OR ROM64_INSTR_PT(617) + OR ROM64_INSTR_PT(618) OR ROM64_INSTR_PT(623) + OR ROM64_INSTR_PT(628) OR ROM64_INSTR_PT(633) + OR ROM64_INSTR_PT(639) OR ROM64_INSTR_PT(645) + OR ROM64_INSTR_PT(646) OR ROM64_INSTR_PT(653) + OR ROM64_INSTR_PT(659) OR ROM64_INSTR_PT(663) + OR ROM64_INSTR_PT(666) OR ROM64_INSTR_PT(678) + OR ROM64_INSTR_PT(691) OR ROM64_INSTR_PT(693) + OR ROM64_INSTR_PT(703) OR ROM64_INSTR_PT(705) + OR ROM64_INSTR_PT(741) OR ROM64_INSTR_PT(753) + OR ROM64_INSTR_PT(797) OR ROM64_INSTR_PT(846) + ); +MQQ901:TEMPLATE(10) <= + (ROM64_INSTR_PT(4) OR ROM64_INSTR_PT(6) + OR ROM64_INSTR_PT(7) OR ROM64_INSTR_PT(14) + OR ROM64_INSTR_PT(15) OR ROM64_INSTR_PT(17) + OR ROM64_INSTR_PT(20) OR ROM64_INSTR_PT(34) + OR ROM64_INSTR_PT(39) OR ROM64_INSTR_PT(41) + OR ROM64_INSTR_PT(42) OR ROM64_INSTR_PT(45) + OR ROM64_INSTR_PT(51) OR ROM64_INSTR_PT(52) + OR ROM64_INSTR_PT(53) OR ROM64_INSTR_PT(57) + OR ROM64_INSTR_PT(73) OR ROM64_INSTR_PT(74) + OR ROM64_INSTR_PT(75) OR ROM64_INSTR_PT(84) + OR ROM64_INSTR_PT(98) OR ROM64_INSTR_PT(99) + OR ROM64_INSTR_PT(112) OR ROM64_INSTR_PT(113) + OR ROM64_INSTR_PT(116) OR ROM64_INSTR_PT(117) + OR ROM64_INSTR_PT(122) OR ROM64_INSTR_PT(125) + OR ROM64_INSTR_PT(127) OR ROM64_INSTR_PT(128) + OR ROM64_INSTR_PT(129) OR ROM64_INSTR_PT(132) + OR ROM64_INSTR_PT(139) OR ROM64_INSTR_PT(140) + OR ROM64_INSTR_PT(143) OR ROM64_INSTR_PT(153) + OR ROM64_INSTR_PT(168) OR ROM64_INSTR_PT(169) + OR ROM64_INSTR_PT(171) OR ROM64_INSTR_PT(173) + OR ROM64_INSTR_PT(174) OR ROM64_INSTR_PT(181) + OR ROM64_INSTR_PT(183) OR ROM64_INSTR_PT(184) + OR ROM64_INSTR_PT(185) OR ROM64_INSTR_PT(191) + OR ROM64_INSTR_PT(194) OR ROM64_INSTR_PT(199) + OR ROM64_INSTR_PT(202) OR ROM64_INSTR_PT(203) + OR ROM64_INSTR_PT(204) OR ROM64_INSTR_PT(213) + OR ROM64_INSTR_PT(217) OR ROM64_INSTR_PT(219) + OR ROM64_INSTR_PT(229) OR ROM64_INSTR_PT(230) + OR ROM64_INSTR_PT(237) OR ROM64_INSTR_PT(240) + OR ROM64_INSTR_PT(241) OR ROM64_INSTR_PT(252) + OR ROM64_INSTR_PT(253) OR ROM64_INSTR_PT(258) + OR ROM64_INSTR_PT(260) OR ROM64_INSTR_PT(264) + OR ROM64_INSTR_PT(268) OR ROM64_INSTR_PT(271) + OR ROM64_INSTR_PT(272) OR ROM64_INSTR_PT(273) + OR ROM64_INSTR_PT(276) OR ROM64_INSTR_PT(278) + OR ROM64_INSTR_PT(283) OR ROM64_INSTR_PT(331) + OR ROM64_INSTR_PT(339) OR ROM64_INSTR_PT(361) + OR ROM64_INSTR_PT(364) OR ROM64_INSTR_PT(366) + OR ROM64_INSTR_PT(367) OR ROM64_INSTR_PT(368) + OR ROM64_INSTR_PT(374) OR ROM64_INSTR_PT(375) + OR ROM64_INSTR_PT(377) OR ROM64_INSTR_PT(381) + OR ROM64_INSTR_PT(384) OR ROM64_INSTR_PT(391) + OR ROM64_INSTR_PT(396) OR ROM64_INSTR_PT(401) + OR ROM64_INSTR_PT(403) OR ROM64_INSTR_PT(406) + OR ROM64_INSTR_PT(408) OR ROM64_INSTR_PT(420) + OR ROM64_INSTR_PT(424) OR ROM64_INSTR_PT(440) + OR ROM64_INSTR_PT(442) OR ROM64_INSTR_PT(445) + OR ROM64_INSTR_PT(448) OR ROM64_INSTR_PT(458) + OR ROM64_INSTR_PT(472) OR ROM64_INSTR_PT(477) + OR ROM64_INSTR_PT(480) OR ROM64_INSTR_PT(481) + OR ROM64_INSTR_PT(483) OR ROM64_INSTR_PT(491) + OR ROM64_INSTR_PT(503) OR ROM64_INSTR_PT(506) + OR ROM64_INSTR_PT(507) OR ROM64_INSTR_PT(508) + OR ROM64_INSTR_PT(511) OR ROM64_INSTR_PT(512) + OR ROM64_INSTR_PT(519) OR ROM64_INSTR_PT(525) + OR ROM64_INSTR_PT(527) OR ROM64_INSTR_PT(531) + OR ROM64_INSTR_PT(532) OR ROM64_INSTR_PT(538) + OR ROM64_INSTR_PT(539) OR ROM64_INSTR_PT(545) + OR ROM64_INSTR_PT(548) OR ROM64_INSTR_PT(553) + OR ROM64_INSTR_PT(554) OR ROM64_INSTR_PT(557) + OR ROM64_INSTR_PT(562) OR ROM64_INSTR_PT(563) + OR ROM64_INSTR_PT(571) OR ROM64_INSTR_PT(579) + OR ROM64_INSTR_PT(583) OR ROM64_INSTR_PT(588) + OR ROM64_INSTR_PT(597) OR ROM64_INSTR_PT(599) + OR ROM64_INSTR_PT(600) OR ROM64_INSTR_PT(602) + OR ROM64_INSTR_PT(603) OR ROM64_INSTR_PT(609) + OR ROM64_INSTR_PT(614) OR ROM64_INSTR_PT(619) + OR ROM64_INSTR_PT(627) OR ROM64_INSTR_PT(629) + OR ROM64_INSTR_PT(632) OR ROM64_INSTR_PT(636) + OR ROM64_INSTR_PT(637) OR ROM64_INSTR_PT(641) + OR ROM64_INSTR_PT(642) OR ROM64_INSTR_PT(644) + OR ROM64_INSTR_PT(655) OR ROM64_INSTR_PT(682) + OR ROM64_INSTR_PT(685) OR ROM64_INSTR_PT(691) + OR ROM64_INSTR_PT(713) OR ROM64_INSTR_PT(717) + OR ROM64_INSTR_PT(721) OR ROM64_INSTR_PT(723) + OR ROM64_INSTR_PT(724) OR ROM64_INSTR_PT(728) + OR ROM64_INSTR_PT(733) OR ROM64_INSTR_PT(735) + OR ROM64_INSTR_PT(736) OR ROM64_INSTR_PT(738) + OR ROM64_INSTR_PT(739) OR ROM64_INSTR_PT(761) + OR ROM64_INSTR_PT(770) OR ROM64_INSTR_PT(824) + OR ROM64_INSTR_PT(858) OR ROM64_INSTR_PT(873) + ); +MQQ902:TEMPLATE(11) <= + ('0'); +MQQ903:TEMPLATE(12) <= + ('0'); +MQQ904:TEMPLATE(13) <= + ('0'); +MQQ905:TEMPLATE(14) <= + (ROM64_INSTR_PT(7) OR ROM64_INSTR_PT(11) + OR ROM64_INSTR_PT(13) OR ROM64_INSTR_PT(15) + OR ROM64_INSTR_PT(17) OR ROM64_INSTR_PT(21) + OR ROM64_INSTR_PT(25) OR ROM64_INSTR_PT(34) + OR ROM64_INSTR_PT(36) OR ROM64_INSTR_PT(38) + OR ROM64_INSTR_PT(42) OR ROM64_INSTR_PT(52) + OR ROM64_INSTR_PT(53) OR ROM64_INSTR_PT(55) + OR ROM64_INSTR_PT(56) OR ROM64_INSTR_PT(61) + OR ROM64_INSTR_PT(64) OR ROM64_INSTR_PT(70) + OR ROM64_INSTR_PT(73) OR ROM64_INSTR_PT(75) + OR ROM64_INSTR_PT(77) OR ROM64_INSTR_PT(80) + OR ROM64_INSTR_PT(84) OR ROM64_INSTR_PT(86) + OR ROM64_INSTR_PT(89) OR ROM64_INSTR_PT(90) + OR ROM64_INSTR_PT(92) OR ROM64_INSTR_PT(93) + OR ROM64_INSTR_PT(96) OR ROM64_INSTR_PT(97) + OR ROM64_INSTR_PT(99) OR ROM64_INSTR_PT(102) + OR ROM64_INSTR_PT(104) OR ROM64_INSTR_PT(106) + OR ROM64_INSTR_PT(110) OR ROM64_INSTR_PT(113) + OR ROM64_INSTR_PT(114) OR ROM64_INSTR_PT(117) + OR ROM64_INSTR_PT(118) OR ROM64_INSTR_PT(125) + OR ROM64_INSTR_PT(127) OR ROM64_INSTR_PT(128) + OR ROM64_INSTR_PT(132) OR ROM64_INSTR_PT(139) + OR ROM64_INSTR_PT(144) OR ROM64_INSTR_PT(155) + OR ROM64_INSTR_PT(169) OR ROM64_INSTR_PT(171) + OR ROM64_INSTR_PT(172) OR ROM64_INSTR_PT(174) + OR ROM64_INSTR_PT(180) OR ROM64_INSTR_PT(181) + OR ROM64_INSTR_PT(184) OR ROM64_INSTR_PT(186) + OR ROM64_INSTR_PT(196) OR ROM64_INSTR_PT(199) + OR ROM64_INSTR_PT(201) OR ROM64_INSTR_PT(202) + OR ROM64_INSTR_PT(208) OR ROM64_INSTR_PT(213) + OR ROM64_INSTR_PT(215) OR ROM64_INSTR_PT(216) + OR ROM64_INSTR_PT(217) OR ROM64_INSTR_PT(223) + OR ROM64_INSTR_PT(226) OR ROM64_INSTR_PT(229) + OR ROM64_INSTR_PT(230) OR ROM64_INSTR_PT(238) + OR ROM64_INSTR_PT(240) OR ROM64_INSTR_PT(252) + OR ROM64_INSTR_PT(261) OR ROM64_INSTR_PT(264) + OR ROM64_INSTR_PT(268) OR ROM64_INSTR_PT(270) + OR ROM64_INSTR_PT(271) OR ROM64_INSTR_PT(272) + OR ROM64_INSTR_PT(274) OR ROM64_INSTR_PT(275) + OR ROM64_INSTR_PT(276) OR ROM64_INSTR_PT(277) + OR ROM64_INSTR_PT(280) OR ROM64_INSTR_PT(282) + OR ROM64_INSTR_PT(286) OR ROM64_INSTR_PT(287) + OR ROM64_INSTR_PT(293) OR ROM64_INSTR_PT(294) + OR ROM64_INSTR_PT(298) OR ROM64_INSTR_PT(302) + OR ROM64_INSTR_PT(305) OR ROM64_INSTR_PT(311) + OR ROM64_INSTR_PT(315) OR ROM64_INSTR_PT(322) + OR ROM64_INSTR_PT(331) OR ROM64_INSTR_PT(349) + OR ROM64_INSTR_PT(364) OR ROM64_INSTR_PT(365) + OR ROM64_INSTR_PT(366) OR ROM64_INSTR_PT(369) + OR ROM64_INSTR_PT(371) OR ROM64_INSTR_PT(372) + OR ROM64_INSTR_PT(375) OR ROM64_INSTR_PT(377) + OR ROM64_INSTR_PT(383) OR ROM64_INSTR_PT(385) + OR ROM64_INSTR_PT(388) OR ROM64_INSTR_PT(391) + OR ROM64_INSTR_PT(395) OR ROM64_INSTR_PT(396) + OR ROM64_INSTR_PT(397) OR ROM64_INSTR_PT(403) + OR ROM64_INSTR_PT(404) OR ROM64_INSTR_PT(405) + OR ROM64_INSTR_PT(410) OR ROM64_INSTR_PT(414) + OR ROM64_INSTR_PT(415) OR ROM64_INSTR_PT(420) + OR ROM64_INSTR_PT(422) OR ROM64_INSTR_PT(424) + OR ROM64_INSTR_PT(426) OR ROM64_INSTR_PT(427) + OR ROM64_INSTR_PT(434) OR ROM64_INSTR_PT(437) + OR ROM64_INSTR_PT(440) OR ROM64_INSTR_PT(445) + OR ROM64_INSTR_PT(456) OR ROM64_INSTR_PT(457) + OR ROM64_INSTR_PT(466) OR ROM64_INSTR_PT(467) + OR ROM64_INSTR_PT(473) OR ROM64_INSTR_PT(475) + OR ROM64_INSTR_PT(478) OR ROM64_INSTR_PT(482) + OR ROM64_INSTR_PT(483) OR ROM64_INSTR_PT(484) + OR ROM64_INSTR_PT(485) OR ROM64_INSTR_PT(488) + OR ROM64_INSTR_PT(493) OR ROM64_INSTR_PT(495) + OR ROM64_INSTR_PT(498) OR ROM64_INSTR_PT(503) + OR ROM64_INSTR_PT(505) OR ROM64_INSTR_PT(511) + OR ROM64_INSTR_PT(517) OR ROM64_INSTR_PT(519) + OR ROM64_INSTR_PT(520) OR ROM64_INSTR_PT(521) + OR ROM64_INSTR_PT(522) OR ROM64_INSTR_PT(523) + OR ROM64_INSTR_PT(525) OR ROM64_INSTR_PT(532) + OR ROM64_INSTR_PT(534) OR ROM64_INSTR_PT(535) + OR ROM64_INSTR_PT(537) OR ROM64_INSTR_PT(539) + OR ROM64_INSTR_PT(542) OR ROM64_INSTR_PT(544) + OR ROM64_INSTR_PT(545) OR ROM64_INSTR_PT(548) + OR ROM64_INSTR_PT(549) OR ROM64_INSTR_PT(552) + OR ROM64_INSTR_PT(553) OR ROM64_INSTR_PT(554) + OR ROM64_INSTR_PT(555) OR ROM64_INSTR_PT(558) + OR ROM64_INSTR_PT(568) OR ROM64_INSTR_PT(569) + OR ROM64_INSTR_PT(571) OR ROM64_INSTR_PT(575) + OR ROM64_INSTR_PT(576) OR ROM64_INSTR_PT(579) + OR ROM64_INSTR_PT(583) OR ROM64_INSTR_PT(584) + OR ROM64_INSTR_PT(588) OR ROM64_INSTR_PT(592) + OR ROM64_INSTR_PT(595) OR ROM64_INSTR_PT(596) + OR ROM64_INSTR_PT(600) OR ROM64_INSTR_PT(608) + OR ROM64_INSTR_PT(609) OR ROM64_INSTR_PT(612) + OR ROM64_INSTR_PT(613) OR ROM64_INSTR_PT(617) + OR ROM64_INSTR_PT(618) OR ROM64_INSTR_PT(623) + OR ROM64_INSTR_PT(628) OR ROM64_INSTR_PT(633) + OR ROM64_INSTR_PT(636) OR ROM64_INSTR_PT(637) + OR ROM64_INSTR_PT(639) OR ROM64_INSTR_PT(642) + OR ROM64_INSTR_PT(644) OR ROM64_INSTR_PT(646) + OR ROM64_INSTR_PT(649) OR ROM64_INSTR_PT(666) + OR ROM64_INSTR_PT(678) OR ROM64_INSTR_PT(682) + OR ROM64_INSTR_PT(691) OR ROM64_INSTR_PT(693) + OR ROM64_INSTR_PT(703) OR ROM64_INSTR_PT(739) + OR ROM64_INSTR_PT(744) OR ROM64_INSTR_PT(753) + OR ROM64_INSTR_PT(761) OR ROM64_INSTR_PT(769) + OR ROM64_INSTR_PT(776) OR ROM64_INSTR_PT(805) + OR ROM64_INSTR_PT(823) OR ROM64_INSTR_PT(856) + OR ROM64_INSTR_PT(864) OR ROM64_INSTR_PT(870) + ); +MQQ906:TEMPLATE(15) <= + (ROM64_INSTR_PT(9) OR ROM64_INSTR_PT(15) + OR ROM64_INSTR_PT(22) OR ROM64_INSTR_PT(53) + OR ROM64_INSTR_PT(57) OR ROM64_INSTR_PT(71) + OR ROM64_INSTR_PT(77) OR ROM64_INSTR_PT(80) + OR ROM64_INSTR_PT(83) OR ROM64_INSTR_PT(89) + OR ROM64_INSTR_PT(92) OR ROM64_INSTR_PT(96) + OR ROM64_INSTR_PT(106) OR ROM64_INSTR_PT(110) + OR ROM64_INSTR_PT(114) OR ROM64_INSTR_PT(116) + OR ROM64_INSTR_PT(121) OR ROM64_INSTR_PT(122) + OR ROM64_INSTR_PT(136) OR ROM64_INSTR_PT(148) + OR ROM64_INSTR_PT(158) OR ROM64_INSTR_PT(162) + OR ROM64_INSTR_PT(168) OR ROM64_INSTR_PT(170) + OR ROM64_INSTR_PT(173) OR ROM64_INSTR_PT(174) + OR ROM64_INSTR_PT(175) OR ROM64_INSTR_PT(203) + OR ROM64_INSTR_PT(211) OR ROM64_INSTR_PT(213) + OR ROM64_INSTR_PT(214) OR ROM64_INSTR_PT(218) + OR ROM64_INSTR_PT(219) OR ROM64_INSTR_PT(222) + OR ROM64_INSTR_PT(236) OR ROM64_INSTR_PT(240) + OR ROM64_INSTR_PT(272) OR ROM64_INSTR_PT(273) + OR ROM64_INSTR_PT(278) OR ROM64_INSTR_PT(284) + OR ROM64_INSTR_PT(294) OR ROM64_INSTR_PT(299) + OR ROM64_INSTR_PT(311) OR ROM64_INSTR_PT(350) + OR ROM64_INSTR_PT(353) OR ROM64_INSTR_PT(358) + OR ROM64_INSTR_PT(363) OR ROM64_INSTR_PT(370) + OR ROM64_INSTR_PT(371) OR ROM64_INSTR_PT(396) + OR ROM64_INSTR_PT(399) OR ROM64_INSTR_PT(408) + OR ROM64_INSTR_PT(416) OR ROM64_INSTR_PT(417) + OR ROM64_INSTR_PT(422) OR ROM64_INSTR_PT(425) + OR ROM64_INSTR_PT(429) OR ROM64_INSTR_PT(433) + OR ROM64_INSTR_PT(435) OR ROM64_INSTR_PT(440) + OR ROM64_INSTR_PT(442) OR ROM64_INSTR_PT(443) + OR ROM64_INSTR_PT(451) OR ROM64_INSTR_PT(458) + OR ROM64_INSTR_PT(461) OR ROM64_INSTR_PT(466) + OR ROM64_INSTR_PT(474) OR ROM64_INSTR_PT(480) + OR ROM64_INSTR_PT(506) OR ROM64_INSTR_PT(508) + OR ROM64_INSTR_PT(509) OR ROM64_INSTR_PT(519) + OR ROM64_INSTR_PT(532) OR ROM64_INSTR_PT(537) + OR ROM64_INSTR_PT(562) OR ROM64_INSTR_PT(564) + OR ROM64_INSTR_PT(581) OR ROM64_INSTR_PT(582) + OR ROM64_INSTR_PT(585) OR ROM64_INSTR_PT(596) + OR ROM64_INSTR_PT(599) OR ROM64_INSTR_PT(603) + OR ROM64_INSTR_PT(604) OR ROM64_INSTR_PT(613) + OR ROM64_INSTR_PT(614) OR ROM64_INSTR_PT(626) + OR ROM64_INSTR_PT(659) OR ROM64_INSTR_PT(664) + OR ROM64_INSTR_PT(691) OR ROM64_INSTR_PT(695) + OR ROM64_INSTR_PT(716) OR ROM64_INSTR_PT(731) + OR ROM64_INSTR_PT(832) OR ROM64_INSTR_PT(834) + OR ROM64_INSTR_PT(846) OR ROM64_INSTR_PT(854) + ); +MQQ907:TEMPLATE(16) <= + (ROM64_INSTR_PT(5) OR ROM64_INSTR_PT(10) + OR ROM64_INSTR_PT(17) OR ROM64_INSTR_PT(20) + OR ROM64_INSTR_PT(21) OR ROM64_INSTR_PT(34) + OR ROM64_INSTR_PT(39) OR ROM64_INSTR_PT(49) + OR ROM64_INSTR_PT(55) OR ROM64_INSTR_PT(64) + OR ROM64_INSTR_PT(75) OR ROM64_INSTR_PT(77) + OR ROM64_INSTR_PT(80) OR ROM64_INSTR_PT(83) + OR ROM64_INSTR_PT(89) OR ROM64_INSTR_PT(96) + OR ROM64_INSTR_PT(98) OR ROM64_INSTR_PT(99) + OR ROM64_INSTR_PT(104) OR ROM64_INSTR_PT(106) + OR ROM64_INSTR_PT(110) OR ROM64_INSTR_PT(113) + OR ROM64_INSTR_PT(114) OR ROM64_INSTR_PT(117) + OR ROM64_INSTR_PT(118) OR ROM64_INSTR_PT(121) + OR ROM64_INSTR_PT(127) OR ROM64_INSTR_PT(171) + OR ROM64_INSTR_PT(175) OR ROM64_INSTR_PT(188) + OR ROM64_INSTR_PT(191) OR ROM64_INSTR_PT(199) + OR ROM64_INSTR_PT(208) OR ROM64_INSTR_PT(214) + OR ROM64_INSTR_PT(217) OR ROM64_INSTR_PT(218) + OR ROM64_INSTR_PT(223) OR ROM64_INSTR_PT(226) + OR ROM64_INSTR_PT(252) OR ROM64_INSTR_PT(253) + OR ROM64_INSTR_PT(257) OR ROM64_INSTR_PT(264) + OR ROM64_INSTR_PT(268) OR ROM64_INSTR_PT(274) + OR ROM64_INSTR_PT(275) OR ROM64_INSTR_PT(280) + OR ROM64_INSTR_PT(283) OR ROM64_INSTR_PT(286) + OR ROM64_INSTR_PT(315) OR ROM64_INSTR_PT(322) + OR ROM64_INSTR_PT(331) OR ROM64_INSTR_PT(349) + OR ROM64_INSTR_PT(363) OR ROM64_INSTR_PT(369) + OR ROM64_INSTR_PT(371) OR ROM64_INSTR_PT(375) + OR ROM64_INSTR_PT(391) OR ROM64_INSTR_PT(397) + OR ROM64_INSTR_PT(401) OR ROM64_INSTR_PT(404) + OR ROM64_INSTR_PT(415) OR ROM64_INSTR_PT(422) + OR ROM64_INSTR_PT(427) OR ROM64_INSTR_PT(437) + OR ROM64_INSTR_PT(448) OR ROM64_INSTR_PT(466) + OR ROM64_INSTR_PT(472) OR ROM64_INSTR_PT(481) + OR ROM64_INSTR_PT(505) OR ROM64_INSTR_PT(521) + OR ROM64_INSTR_PT(523) OR ROM64_INSTR_PT(525) + OR ROM64_INSTR_PT(538) OR ROM64_INSTR_PT(540) + OR ROM64_INSTR_PT(558) OR ROM64_INSTR_PT(563) + OR ROM64_INSTR_PT(569) OR ROM64_INSTR_PT(582) + OR ROM64_INSTR_PT(584) OR ROM64_INSTR_PT(595) + OR ROM64_INSTR_PT(596) OR ROM64_INSTR_PT(597) + OR ROM64_INSTR_PT(598) OR ROM64_INSTR_PT(600) + OR ROM64_INSTR_PT(608) OR ROM64_INSTR_PT(613) + OR ROM64_INSTR_PT(618) OR ROM64_INSTR_PT(629) + OR ROM64_INSTR_PT(642) OR ROM64_INSTR_PT(644) + OR ROM64_INSTR_PT(744) OR ROM64_INSTR_PT(769) + OR ROM64_INSTR_PT(776) OR ROM64_INSTR_PT(870) + ); +MQQ908:TEMPLATE(17) <= + (ROM64_INSTR_PT(5) OR ROM64_INSTR_PT(17) + OR ROM64_INSTR_PT(20) OR ROM64_INSTR_PT(21) + OR ROM64_INSTR_PT(34) OR ROM64_INSTR_PT(38) + OR ROM64_INSTR_PT(39) OR ROM64_INSTR_PT(43) + OR ROM64_INSTR_PT(49) OR ROM64_INSTR_PT(55) + OR ROM64_INSTR_PT(61) OR ROM64_INSTR_PT(70) + OR ROM64_INSTR_PT(77) OR ROM64_INSTR_PT(78) + OR ROM64_INSTR_PT(80) OR ROM64_INSTR_PT(86) + OR ROM64_INSTR_PT(89) OR ROM64_INSTR_PT(90) + OR ROM64_INSTR_PT(98) OR ROM64_INSTR_PT(99) + OR ROM64_INSTR_PT(102) OR ROM64_INSTR_PT(104) + OR ROM64_INSTR_PT(106) OR ROM64_INSTR_PT(111) + OR ROM64_INSTR_PT(114) OR ROM64_INSTR_PT(118) + OR ROM64_INSTR_PT(121) OR ROM64_INSTR_PT(127) + OR ROM64_INSTR_PT(144) OR ROM64_INSTR_PT(168) + OR ROM64_INSTR_PT(173) OR ROM64_INSTR_PT(175) + OR ROM64_INSTR_PT(186) OR ROM64_INSTR_PT(188) + OR ROM64_INSTR_PT(191) OR ROM64_INSTR_PT(199) + OR ROM64_INSTR_PT(208) OR ROM64_INSTR_PT(215) + OR ROM64_INSTR_PT(219) OR ROM64_INSTR_PT(223) + OR ROM64_INSTR_PT(226) OR ROM64_INSTR_PT(238) + OR ROM64_INSTR_PT(252) OR ROM64_INSTR_PT(253) + OR ROM64_INSTR_PT(257) OR ROM64_INSTR_PT(270) + OR ROM64_INSTR_PT(271) OR ROM64_INSTR_PT(274) + OR ROM64_INSTR_PT(277) OR ROM64_INSTR_PT(280) + OR ROM64_INSTR_PT(282) OR ROM64_INSTR_PT(283) + OR ROM64_INSTR_PT(286) OR ROM64_INSTR_PT(287) + OR ROM64_INSTR_PT(293) OR ROM64_INSTR_PT(302) + OR ROM64_INSTR_PT(305) OR ROM64_INSTR_PT(322) + OR ROM64_INSTR_PT(329) OR ROM64_INSTR_PT(331) + OR ROM64_INSTR_PT(343) OR ROM64_INSTR_PT(349) + OR ROM64_INSTR_PT(361) OR ROM64_INSTR_PT(364) + OR ROM64_INSTR_PT(369) OR ROM64_INSTR_PT(383) + OR ROM64_INSTR_PT(385) OR ROM64_INSTR_PT(397) + OR ROM64_INSTR_PT(401) OR ROM64_INSTR_PT(406) + OR ROM64_INSTR_PT(408) OR ROM64_INSTR_PT(410) + OR ROM64_INSTR_PT(420) OR ROM64_INSTR_PT(422) + OR ROM64_INSTR_PT(424) OR ROM64_INSTR_PT(427) + OR ROM64_INSTR_PT(448) OR ROM64_INSTR_PT(466) + OR ROM64_INSTR_PT(472) OR ROM64_INSTR_PT(478) + OR ROM64_INSTR_PT(480) OR ROM64_INSTR_PT(481) + OR ROM64_INSTR_PT(482) OR ROM64_INSTR_PT(483) + OR ROM64_INSTR_PT(484) OR ROM64_INSTR_PT(485) + OR ROM64_INSTR_PT(493) OR ROM64_INSTR_PT(495) + OR ROM64_INSTR_PT(498) OR ROM64_INSTR_PT(508) + OR ROM64_INSTR_PT(511) OR ROM64_INSTR_PT(522) + OR ROM64_INSTR_PT(523) OR ROM64_INSTR_PT(534) + OR ROM64_INSTR_PT(535) OR ROM64_INSTR_PT(536) + OR ROM64_INSTR_PT(538) OR ROM64_INSTR_PT(548) + OR ROM64_INSTR_PT(549) OR ROM64_INSTR_PT(552) + OR ROM64_INSTR_PT(555) OR ROM64_INSTR_PT(563) + OR ROM64_INSTR_PT(575) OR ROM64_INSTR_PT(579) + OR ROM64_INSTR_PT(583) OR ROM64_INSTR_PT(584) + OR ROM64_INSTR_PT(588) OR ROM64_INSTR_PT(596) + OR ROM64_INSTR_PT(597) OR ROM64_INSTR_PT(599) + OR ROM64_INSTR_PT(603) OR ROM64_INSTR_PT(608) + OR ROM64_INSTR_PT(612) OR ROM64_INSTR_PT(613) + OR ROM64_INSTR_PT(614) OR ROM64_INSTR_PT(633) + OR ROM64_INSTR_PT(637) OR ROM64_INSTR_PT(639) + OR ROM64_INSTR_PT(642) OR ROM64_INSTR_PT(644) + OR ROM64_INSTR_PT(646) OR ROM64_INSTR_PT(666) + OR ROM64_INSTR_PT(678) OR ROM64_INSTR_PT(682) + OR ROM64_INSTR_PT(703) OR ROM64_INSTR_PT(870) + ); +MQQ909:TEMPLATE(18) <= + (ROM64_INSTR_PT(5) OR ROM64_INSTR_PT(20) + OR ROM64_INSTR_PT(21) OR ROM64_INSTR_PT(39) + OR ROM64_INSTR_PT(49) OR ROM64_INSTR_PT(77) + OR ROM64_INSTR_PT(80) OR ROM64_INSTR_PT(89) + OR ROM64_INSTR_PT(97) OR ROM64_INSTR_PT(98) + OR ROM64_INSTR_PT(106) OR ROM64_INSTR_PT(110) + OR ROM64_INSTR_PT(114) OR ROM64_INSTR_PT(118) + OR ROM64_INSTR_PT(172) OR ROM64_INSTR_PT(223) + OR ROM64_INSTR_PT(253) OR ROM64_INSTR_PT(273) + OR ROM64_INSTR_PT(280) OR ROM64_INSTR_PT(283) + OR ROM64_INSTR_PT(397) OR ROM64_INSTR_PT(401) + OR ROM64_INSTR_PT(422) OR ROM64_INSTR_PT(427) + OR ROM64_INSTR_PT(466) OR ROM64_INSTR_PT(472) + OR ROM64_INSTR_PT(523) OR ROM64_INSTR_PT(538) + OR ROM64_INSTR_PT(544) OR ROM64_INSTR_PT(563) + OR ROM64_INSTR_PT(584) OR ROM64_INSTR_PT(597) + OR ROM64_INSTR_PT(642) OR ROM64_INSTR_PT(723) + OR ROM64_INSTR_PT(724) OR ROM64_INSTR_PT(733) + ); +MQQ910:TEMPLATE(19) <= + (ROM64_INSTR_PT(5) OR ROM64_INSTR_PT(15) + OR ROM64_INSTR_PT(18) OR ROM64_INSTR_PT(20) + OR ROM64_INSTR_PT(21) OR ROM64_INSTR_PT(25) + OR ROM64_INSTR_PT(39) OR ROM64_INSTR_PT(42) + OR ROM64_INSTR_PT(45) OR ROM64_INSTR_PT(49) + OR ROM64_INSTR_PT(53) OR ROM64_INSTR_PT(57) + OR ROM64_INSTR_PT(73) OR ROM64_INSTR_PT(77) + OR ROM64_INSTR_PT(80) OR ROM64_INSTR_PT(84) + OR ROM64_INSTR_PT(97) OR ROM64_INSTR_PT(98) + OR ROM64_INSTR_PT(101) OR ROM64_INSTR_PT(106) + OR ROM64_INSTR_PT(109) OR ROM64_INSTR_PT(118) + OR ROM64_INSTR_PT(128) OR ROM64_INSTR_PT(145) + OR ROM64_INSTR_PT(157) OR ROM64_INSTR_PT(168) + OR ROM64_INSTR_PT(182) OR ROM64_INSTR_PT(203) + OR ROM64_INSTR_PT(205) OR ROM64_INSTR_PT(206) + OR ROM64_INSTR_PT(218) OR ROM64_INSTR_PT(219) + OR ROM64_INSTR_PT(223) OR ROM64_INSTR_PT(236) + OR ROM64_INSTR_PT(244) OR ROM64_INSTR_PT(253) + OR ROM64_INSTR_PT(254) OR ROM64_INSTR_PT(262) + OR ROM64_INSTR_PT(269) OR ROM64_INSTR_PT(272) + OR ROM64_INSTR_PT(273) OR ROM64_INSTR_PT(280) + OR ROM64_INSTR_PT(283) OR ROM64_INSTR_PT(284) + OR ROM64_INSTR_PT(290) OR ROM64_INSTR_PT(308) + OR ROM64_INSTR_PT(325) OR ROM64_INSTR_PT(348) + OR ROM64_INSTR_PT(361) OR ROM64_INSTR_PT(381) + OR ROM64_INSTR_PT(387) OR ROM64_INSTR_PT(388) + OR ROM64_INSTR_PT(397) OR ROM64_INSTR_PT(401) + OR ROM64_INSTR_PT(406) OR ROM64_INSTR_PT(409) + OR ROM64_INSTR_PT(419) OR ROM64_INSTR_PT(422) + OR ROM64_INSTR_PT(425) OR ROM64_INSTR_PT(427) + OR ROM64_INSTR_PT(429) OR ROM64_INSTR_PT(430) + OR ROM64_INSTR_PT(439) OR ROM64_INSTR_PT(440) + OR ROM64_INSTR_PT(451) OR ROM64_INSTR_PT(454) + OR ROM64_INSTR_PT(455) OR ROM64_INSTR_PT(460) + OR ROM64_INSTR_PT(466) OR ROM64_INSTR_PT(472) + OR ROM64_INSTR_PT(490) OR ROM64_INSTR_PT(506) + OR ROM64_INSTR_PT(510) OR ROM64_INSTR_PT(519) + OR ROM64_INSTR_PT(523) OR ROM64_INSTR_PT(530) + OR ROM64_INSTR_PT(532) OR ROM64_INSTR_PT(538) + OR ROM64_INSTR_PT(539) OR ROM64_INSTR_PT(542) + OR ROM64_INSTR_PT(553) OR ROM64_INSTR_PT(554) + OR ROM64_INSTR_PT(570) OR ROM64_INSTR_PT(577) + OR ROM64_INSTR_PT(580) OR ROM64_INSTR_PT(582) + OR ROM64_INSTR_PT(584) OR ROM64_INSTR_PT(597) + OR ROM64_INSTR_PT(611) OR ROM64_INSTR_PT(616) + OR ROM64_INSTR_PT(619) OR ROM64_INSTR_PT(636) + OR ROM64_INSTR_PT(642) OR ROM64_INSTR_PT(643) + OR ROM64_INSTR_PT(681) OR ROM64_INSTR_PT(723) + OR ROM64_INSTR_PT(724) OR ROM64_INSTR_PT(733) + OR ROM64_INSTR_PT(736) OR ROM64_INSTR_PT(770) + OR ROM64_INSTR_PT(813) OR ROM64_INSTR_PT(823) + OR ROM64_INSTR_PT(824)); +MQQ911:TEMPLATE(20) <= + (ROM64_INSTR_PT(5) OR ROM64_INSTR_PT(13) + OR ROM64_INSTR_PT(18) OR ROM64_INSTR_PT(21) + OR ROM64_INSTR_PT(35) OR ROM64_INSTR_PT(36) + OR ROM64_INSTR_PT(39) OR ROM64_INSTR_PT(42) + OR ROM64_INSTR_PT(45) OR ROM64_INSTR_PT(49) + OR ROM64_INSTR_PT(56) OR ROM64_INSTR_PT(98) + OR ROM64_INSTR_PT(118) OR ROM64_INSTR_PT(155) + OR ROM64_INSTR_PT(162) OR ROM64_INSTR_PT(196) + OR ROM64_INSTR_PT(216) OR ROM64_INSTR_PT(223) + OR ROM64_INSTR_PT(236) OR ROM64_INSTR_PT(253) + OR ROM64_INSTR_PT(261) OR ROM64_INSTR_PT(262) + OR ROM64_INSTR_PT(273) OR ROM64_INSTR_PT(280) + OR ROM64_INSTR_PT(283) OR ROM64_INSTR_PT(284) + OR ROM64_INSTR_PT(308) OR ROM64_INSTR_PT(325) + OR ROM64_INSTR_PT(353) OR ROM64_INSTR_PT(365) + OR ROM64_INSTR_PT(372) OR ROM64_INSTR_PT(388) + OR ROM64_INSTR_PT(395) OR ROM64_INSTR_PT(397) + OR ROM64_INSTR_PT(401) OR ROM64_INSTR_PT(405) + OR ROM64_INSTR_PT(422) OR ROM64_INSTR_PT(425) + OR ROM64_INSTR_PT(426) OR ROM64_INSTR_PT(427) + OR ROM64_INSTR_PT(429) OR ROM64_INSTR_PT(435) + OR ROM64_INSTR_PT(439) OR ROM64_INSTR_PT(451) + OR ROM64_INSTR_PT(454) OR ROM64_INSTR_PT(455) + OR ROM64_INSTR_PT(456) OR ROM64_INSTR_PT(458) + OR ROM64_INSTR_PT(466) OR ROM64_INSTR_PT(467) + OR ROM64_INSTR_PT(473) OR ROM64_INSTR_PT(475) + OR ROM64_INSTR_PT(488) OR ROM64_INSTR_PT(507) + OR ROM64_INSTR_PT(517) OR ROM64_INSTR_PT(520) + OR ROM64_INSTR_PT(523) OR ROM64_INSTR_PT(538) + OR ROM64_INSTR_PT(542) OR ROM64_INSTR_PT(544) + OR ROM64_INSTR_PT(564) OR ROM64_INSTR_PT(568) + OR ROM64_INSTR_PT(584) OR ROM64_INSTR_PT(586) + OR ROM64_INSTR_PT(587) OR ROM64_INSTR_PT(589) + OR ROM64_INSTR_PT(597) OR ROM64_INSTR_PT(617) + OR ROM64_INSTR_PT(619) OR ROM64_INSTR_PT(628) + OR ROM64_INSTR_PT(642) OR ROM64_INSTR_PT(681) + OR ROM64_INSTR_PT(693) OR ROM64_INSTR_PT(721) + OR ROM64_INSTR_PT(728) OR ROM64_INSTR_PT(735) + OR ROM64_INSTR_PT(738) OR ROM64_INSTR_PT(770) + OR ROM64_INSTR_PT(811) OR ROM64_INSTR_PT(823) + ); +MQQ912:TEMPLATE(21) <= + (ROM64_INSTR_PT(5) OR ROM64_INSTR_PT(6) + OR ROM64_INSTR_PT(9) OR ROM64_INSTR_PT(10) + OR ROM64_INSTR_PT(11) OR ROM64_INSTR_PT(21) + OR ROM64_INSTR_PT(22) OR ROM64_INSTR_PT(25) + OR ROM64_INSTR_PT(36) OR ROM64_INSTR_PT(39) + OR ROM64_INSTR_PT(43) OR ROM64_INSTR_PT(58) + OR ROM64_INSTR_PT(70) OR ROM64_INSTR_PT(71) + OR ROM64_INSTR_PT(76) OR ROM64_INSTR_PT(78) + OR ROM64_INSTR_PT(83) OR ROM64_INSTR_PT(86) + OR ROM64_INSTR_PT(93) OR ROM64_INSTR_PT(96) + OR ROM64_INSTR_PT(97) OR ROM64_INSTR_PT(98) + OR ROM64_INSTR_PT(117) OR ROM64_INSTR_PT(118) + OR ROM64_INSTR_PT(136) OR ROM64_INSTR_PT(148) + OR ROM64_INSTR_PT(154) OR ROM64_INSTR_PT(168) + OR ROM64_INSTR_PT(172) OR ROM64_INSTR_PT(180) + OR ROM64_INSTR_PT(182) OR ROM64_INSTR_PT(184) + OR ROM64_INSTR_PT(188) OR ROM64_INSTR_PT(194) + OR ROM64_INSTR_PT(201) OR ROM64_INSTR_PT(202) + OR ROM64_INSTR_PT(205) OR ROM64_INSTR_PT(214) + OR ROM64_INSTR_PT(216) OR ROM64_INSTR_PT(219) + OR ROM64_INSTR_PT(222) OR ROM64_INSTR_PT(223) + OR ROM64_INSTR_PT(229) OR ROM64_INSTR_PT(230) + OR ROM64_INSTR_PT(245) OR ROM64_INSTR_PT(253) + OR ROM64_INSTR_PT(257) OR ROM64_INSTR_PT(258) + OR ROM64_INSTR_PT(260) OR ROM64_INSTR_PT(261) + OR ROM64_INSTR_PT(264) OR ROM64_INSTR_PT(268) + OR ROM64_INSTR_PT(271) OR ROM64_INSTR_PT(273) + OR ROM64_INSTR_PT(275) OR ROM64_INSTR_PT(277) + OR ROM64_INSTR_PT(280) OR ROM64_INSTR_PT(283) + OR ROM64_INSTR_PT(298) OR ROM64_INSTR_PT(299) + OR ROM64_INSTR_PT(312) OR ROM64_INSTR_PT(315) + OR ROM64_INSTR_PT(348) OR ROM64_INSTR_PT(361) + OR ROM64_INSTR_PT(363) OR ROM64_INSTR_PT(365) + OR ROM64_INSTR_PT(371) OR ROM64_INSTR_PT(375) + OR ROM64_INSTR_PT(387) OR ROM64_INSTR_PT(388) + OR ROM64_INSTR_PT(391) OR ROM64_INSTR_PT(397) + OR ROM64_INSTR_PT(401) OR ROM64_INSTR_PT(404) + OR ROM64_INSTR_PT(406) OR ROM64_INSTR_PT(414) + OR ROM64_INSTR_PT(415) OR ROM64_INSTR_PT(424) + OR ROM64_INSTR_PT(427) OR ROM64_INSTR_PT(430) + OR ROM64_INSTR_PT(434) OR ROM64_INSTR_PT(437) + OR ROM64_INSTR_PT(438) OR ROM64_INSTR_PT(457) + OR ROM64_INSTR_PT(458) OR ROM64_INSTR_PT(463) + OR ROM64_INSTR_PT(497) OR ROM64_INSTR_PT(503) + OR ROM64_INSTR_PT(505) OR ROM64_INSTR_PT(509) + OR ROM64_INSTR_PT(510) OR ROM64_INSTR_PT(511) + OR ROM64_INSTR_PT(520) OR ROM64_INSTR_PT(521) + OR ROM64_INSTR_PT(523) OR ROM64_INSTR_PT(525) + OR ROM64_INSTR_PT(530) OR ROM64_INSTR_PT(531) + OR ROM64_INSTR_PT(535) OR ROM64_INSTR_PT(538) + OR ROM64_INSTR_PT(540) OR ROM64_INSTR_PT(544) + OR ROM64_INSTR_PT(545) OR ROM64_INSTR_PT(549) + OR ROM64_INSTR_PT(558) OR ROM64_INSTR_PT(569) + OR ROM64_INSTR_PT(570) OR ROM64_INSTR_PT(575) + OR ROM64_INSTR_PT(576) OR ROM64_INSTR_PT(579) + OR ROM64_INSTR_PT(580) OR ROM64_INSTR_PT(584) + OR ROM64_INSTR_PT(588) OR ROM64_INSTR_PT(592) + OR ROM64_INSTR_PT(595) OR ROM64_INSTR_PT(597) + OR ROM64_INSTR_PT(598) OR ROM64_INSTR_PT(617) + OR ROM64_INSTR_PT(618) OR ROM64_INSTR_PT(623) + OR ROM64_INSTR_PT(628) OR ROM64_INSTR_PT(629) + OR ROM64_INSTR_PT(663) OR ROM64_INSTR_PT(728) + OR ROM64_INSTR_PT(735) OR ROM64_INSTR_PT(738) + OR ROM64_INSTR_PT(822)); +MQQ913:TEMPLATE(22) <= + (ROM64_INSTR_PT(5) OR ROM64_INSTR_PT(8) + OR ROM64_INSTR_PT(9) OR ROM64_INSTR_PT(11) + OR ROM64_INSTR_PT(13) OR ROM64_INSTR_PT(15) + OR ROM64_INSTR_PT(18) OR ROM64_INSTR_PT(21) + OR ROM64_INSTR_PT(22) OR ROM64_INSTR_PT(25) + OR ROM64_INSTR_PT(30) OR ROM64_INSTR_PT(36) + OR ROM64_INSTR_PT(39) OR ROM64_INSTR_PT(43) + OR ROM64_INSTR_PT(53) OR ROM64_INSTR_PT(56) + OR ROM64_INSTR_PT(57) OR ROM64_INSTR_PT(71) + OR ROM64_INSTR_PT(73) OR ROM64_INSTR_PT(76) + OR ROM64_INSTR_PT(78) OR ROM64_INSTR_PT(93) + OR ROM64_INSTR_PT(97) OR ROM64_INSTR_PT(98) + OR ROM64_INSTR_PT(101) OR ROM64_INSTR_PT(113) + OR ROM64_INSTR_PT(118) OR ROM64_INSTR_PT(121) + OR ROM64_INSTR_PT(128) OR ROM64_INSTR_PT(133) + OR ROM64_INSTR_PT(136) OR ROM64_INSTR_PT(148) + OR ROM64_INSTR_PT(155) OR ROM64_INSTR_PT(157) + OR ROM64_INSTR_PT(162) OR ROM64_INSTR_PT(164) + OR ROM64_INSTR_PT(171) OR ROM64_INSTR_PT(172) + OR ROM64_INSTR_PT(175) OR ROM64_INSTR_PT(180) + OR ROM64_INSTR_PT(184) OR ROM64_INSTR_PT(188) + OR ROM64_INSTR_PT(196) OR ROM64_INSTR_PT(201) + OR ROM64_INSTR_PT(202) OR ROM64_INSTR_PT(203) + OR ROM64_INSTR_PT(206) OR ROM64_INSTR_PT(211) + OR ROM64_INSTR_PT(216) OR ROM64_INSTR_PT(218) + OR ROM64_INSTR_PT(222) OR ROM64_INSTR_PT(223) + OR ROM64_INSTR_PT(229) OR ROM64_INSTR_PT(230) + OR ROM64_INSTR_PT(244) OR ROM64_INSTR_PT(245) + OR ROM64_INSTR_PT(253) OR ROM64_INSTR_PT(257) + OR ROM64_INSTR_PT(261) OR ROM64_INSTR_PT(272) + OR ROM64_INSTR_PT(273) OR ROM64_INSTR_PT(280) + OR ROM64_INSTR_PT(283) OR ROM64_INSTR_PT(298) + OR ROM64_INSTR_PT(299) OR ROM64_INSTR_PT(312) + OR ROM64_INSTR_PT(325) OR ROM64_INSTR_PT(353) + OR ROM64_INSTR_PT(365) OR ROM64_INSTR_PT(372) + OR ROM64_INSTR_PT(381) OR ROM64_INSTR_PT(388) + OR ROM64_INSTR_PT(395) OR ROM64_INSTR_PT(397) + OR ROM64_INSTR_PT(401) OR ROM64_INSTR_PT(405) + OR ROM64_INSTR_PT(414) OR ROM64_INSTR_PT(426) + OR ROM64_INSTR_PT(427) OR ROM64_INSTR_PT(434) + OR ROM64_INSTR_PT(438) OR ROM64_INSTR_PT(439) + OR ROM64_INSTR_PT(440) OR ROM64_INSTR_PT(443) + OR ROM64_INSTR_PT(454) OR ROM64_INSTR_PT(455) + OR ROM64_INSTR_PT(456) OR ROM64_INSTR_PT(457) + OR ROM64_INSTR_PT(458) OR ROM64_INSTR_PT(460) + OR ROM64_INSTR_PT(463) OR ROM64_INSTR_PT(467) + OR ROM64_INSTR_PT(473) OR ROM64_INSTR_PT(475) + OR ROM64_INSTR_PT(481) OR ROM64_INSTR_PT(488) + OR ROM64_INSTR_PT(490) OR ROM64_INSTR_PT(497) + OR ROM64_INSTR_PT(503) OR ROM64_INSTR_PT(506) + OR ROM64_INSTR_PT(509) OR ROM64_INSTR_PT(514) + OR ROM64_INSTR_PT(519) OR ROM64_INSTR_PT(520) + OR ROM64_INSTR_PT(523) OR ROM64_INSTR_PT(532) + OR ROM64_INSTR_PT(538) OR ROM64_INSTR_PT(539) + OR ROM64_INSTR_PT(540) OR ROM64_INSTR_PT(544) + OR ROM64_INSTR_PT(545) OR ROM64_INSTR_PT(553) + OR ROM64_INSTR_PT(554) OR ROM64_INSTR_PT(566) + OR ROM64_INSTR_PT(568) OR ROM64_INSTR_PT(576) + OR ROM64_INSTR_PT(581) OR ROM64_INSTR_PT(582) + OR ROM64_INSTR_PT(584) OR ROM64_INSTR_PT(586) + OR ROM64_INSTR_PT(587) OR ROM64_INSTR_PT(589) + OR ROM64_INSTR_PT(592) OR ROM64_INSTR_PT(596) + OR ROM64_INSTR_PT(597) OR ROM64_INSTR_PT(598) + OR ROM64_INSTR_PT(604) OR ROM64_INSTR_PT(607) + OR ROM64_INSTR_PT(611) OR ROM64_INSTR_PT(613) + OR ROM64_INSTR_PT(617) OR ROM64_INSTR_PT(625) + OR ROM64_INSTR_PT(628) OR ROM64_INSTR_PT(636) + OR ROM64_INSTR_PT(643) OR ROM64_INSTR_PT(655) + OR ROM64_INSTR_PT(663) OR ROM64_INSTR_PT(681) + OR ROM64_INSTR_PT(698) OR ROM64_INSTR_PT(713) + OR ROM64_INSTR_PT(723) OR ROM64_INSTR_PT(724) + OR ROM64_INSTR_PT(728) OR ROM64_INSTR_PT(733) + OR ROM64_INSTR_PT(735) OR ROM64_INSTR_PT(738) + OR ROM64_INSTR_PT(822) OR ROM64_INSTR_PT(824) + OR ROM64_INSTR_PT(846) OR ROM64_INSTR_PT(854) + ); +MQQ914:TEMPLATE(23) <= + (ROM64_INSTR_PT(5) OR ROM64_INSTR_PT(6) + OR ROM64_INSTR_PT(13) OR ROM64_INSTR_PT(25) + OR ROM64_INSTR_PT(36) OR ROM64_INSTR_PT(39) + OR ROM64_INSTR_PT(56) OR ROM64_INSTR_PT(57) + OR ROM64_INSTR_PT(73) OR ROM64_INSTR_PT(89) + OR ROM64_INSTR_PT(93) OR ROM64_INSTR_PT(98) + OR ROM64_INSTR_PT(100) OR ROM64_INSTR_PT(101) + OR ROM64_INSTR_PT(110) OR ROM64_INSTR_PT(114) + OR ROM64_INSTR_PT(124) OR ROM64_INSTR_PT(128) + OR ROM64_INSTR_PT(137) OR ROM64_INSTR_PT(155) + OR ROM64_INSTR_PT(157) OR ROM64_INSTR_PT(162) + OR ROM64_INSTR_PT(168) OR ROM64_INSTR_PT(180) + OR ROM64_INSTR_PT(184) OR ROM64_INSTR_PT(194) + OR ROM64_INSTR_PT(201) OR ROM64_INSTR_PT(202) + OR ROM64_INSTR_PT(203) OR ROM64_INSTR_PT(206) + OR ROM64_INSTR_PT(216) OR ROM64_INSTR_PT(218) + OR ROM64_INSTR_PT(219) OR ROM64_INSTR_PT(229) + OR ROM64_INSTR_PT(230) OR ROM64_INSTR_PT(244) + OR ROM64_INSTR_PT(245) OR ROM64_INSTR_PT(253) + OR ROM64_INSTR_PT(258) OR ROM64_INSTR_PT(260) + OR ROM64_INSTR_PT(261) OR ROM64_INSTR_PT(263) + OR ROM64_INSTR_PT(277) OR ROM64_INSTR_PT(283) + OR ROM64_INSTR_PT(285) OR ROM64_INSTR_PT(297) + OR ROM64_INSTR_PT(312) OR ROM64_INSTR_PT(319) + OR ROM64_INSTR_PT(353) OR ROM64_INSTR_PT(361) + OR ROM64_INSTR_PT(365) OR ROM64_INSTR_PT(372) + OR ROM64_INSTR_PT(379) OR ROM64_INSTR_PT(381) + OR ROM64_INSTR_PT(388) OR ROM64_INSTR_PT(395) + OR ROM64_INSTR_PT(401) OR ROM64_INSTR_PT(405) + OR ROM64_INSTR_PT(406) OR ROM64_INSTR_PT(413) + OR ROM64_INSTR_PT(426) OR ROM64_INSTR_PT(434) + OR ROM64_INSTR_PT(438) OR ROM64_INSTR_PT(446) + OR ROM64_INSTR_PT(456) OR ROM64_INSTR_PT(457) + OR ROM64_INSTR_PT(458) OR ROM64_INSTR_PT(460) + OR ROM64_INSTR_PT(467) OR ROM64_INSTR_PT(473) + OR ROM64_INSTR_PT(475) OR ROM64_INSTR_PT(488) + OR ROM64_INSTR_PT(490) OR ROM64_INSTR_PT(503) + OR ROM64_INSTR_PT(504) OR ROM64_INSTR_PT(506) + OR ROM64_INSTR_PT(517) OR ROM64_INSTR_PT(520) + OR ROM64_INSTR_PT(531) OR ROM64_INSTR_PT(535) + OR ROM64_INSTR_PT(538) OR ROM64_INSTR_PT(539) + OR ROM64_INSTR_PT(545) OR ROM64_INSTR_PT(546) + OR ROM64_INSTR_PT(549) OR ROM64_INSTR_PT(553) + OR ROM64_INSTR_PT(554) OR ROM64_INSTR_PT(559) + OR ROM64_INSTR_PT(563) OR ROM64_INSTR_PT(568) + OR ROM64_INSTR_PT(575) OR ROM64_INSTR_PT(582) + OR ROM64_INSTR_PT(592) OR ROM64_INSTR_PT(597) + OR ROM64_INSTR_PT(606) OR ROM64_INSTR_PT(611) + OR ROM64_INSTR_PT(615) OR ROM64_INSTR_PT(617) + OR ROM64_INSTR_PT(623) OR ROM64_INSTR_PT(628) + OR ROM64_INSTR_PT(636) OR ROM64_INSTR_PT(643) + OR ROM64_INSTR_PT(663) OR ROM64_INSTR_PT(693) + OR ROM64_INSTR_PT(717) OR ROM64_INSTR_PT(723) + OR ROM64_INSTR_PT(724) OR ROM64_INSTR_PT(728) + OR ROM64_INSTR_PT(733) OR ROM64_INSTR_PT(735) + OR ROM64_INSTR_PT(738) OR ROM64_INSTR_PT(822) + OR ROM64_INSTR_PT(824) OR ROM64_INSTR_PT(846) + ); +MQQ915:TEMPLATE(24) <= + (ROM64_INSTR_PT(4) OR ROM64_INSTR_PT(5) + OR ROM64_INSTR_PT(6) OR ROM64_INSTR_PT(11) + OR ROM64_INSTR_PT(14) OR ROM64_INSTR_PT(30) + OR ROM64_INSTR_PT(36) OR ROM64_INSTR_PT(41) + OR ROM64_INSTR_PT(45) OR ROM64_INSTR_PT(51) + OR ROM64_INSTR_PT(77) OR ROM64_INSTR_PT(80) + OR ROM64_INSTR_PT(93) OR ROM64_INSTR_PT(98) + OR ROM64_INSTR_PT(100) OR ROM64_INSTR_PT(105) + OR ROM64_INSTR_PT(106) OR ROM64_INSTR_PT(115) + OR ROM64_INSTR_PT(124) OR ROM64_INSTR_PT(137) + OR ROM64_INSTR_PT(140) OR ROM64_INSTR_PT(143) + OR ROM64_INSTR_PT(153) OR ROM64_INSTR_PT(158) + OR ROM64_INSTR_PT(170) OR ROM64_INSTR_PT(172) + OR ROM64_INSTR_PT(184) OR ROM64_INSTR_PT(185) + OR ROM64_INSTR_PT(194) OR ROM64_INSTR_PT(202) + OR ROM64_INSTR_PT(204) OR ROM64_INSTR_PT(216) + OR ROM64_INSTR_PT(218) OR ROM64_INSTR_PT(229) + OR ROM64_INSTR_PT(230) OR ROM64_INSTR_PT(241) + OR ROM64_INSTR_PT(253) OR ROM64_INSTR_PT(258) + OR ROM64_INSTR_PT(260) OR ROM64_INSTR_PT(261) + OR ROM64_INSTR_PT(262) OR ROM64_INSTR_PT(263) + OR ROM64_INSTR_PT(277) OR ROM64_INSTR_PT(278) + OR ROM64_INSTR_PT(283) OR ROM64_INSTR_PT(285) + OR ROM64_INSTR_PT(294) OR ROM64_INSTR_PT(297) + OR ROM64_INSTR_PT(308) OR ROM64_INSTR_PT(311) + OR ROM64_INSTR_PT(319) OR ROM64_INSTR_PT(348) + OR ROM64_INSTR_PT(365) OR ROM64_INSTR_PT(366) + OR ROM64_INSTR_PT(379) OR ROM64_INSTR_PT(387) + OR ROM64_INSTR_PT(394) OR ROM64_INSTR_PT(401) + OR ROM64_INSTR_PT(413) OR ROM64_INSTR_PT(418) + OR ROM64_INSTR_PT(428) OR ROM64_INSTR_PT(430) + OR ROM64_INSTR_PT(432) OR ROM64_INSTR_PT(433) + OR ROM64_INSTR_PT(434) OR ROM64_INSTR_PT(438) + OR ROM64_INSTR_PT(441) OR ROM64_INSTR_PT(446) + OR ROM64_INSTR_PT(453) OR ROM64_INSTR_PT(458) + OR ROM64_INSTR_PT(496) OR ROM64_INSTR_PT(503) + OR ROM64_INSTR_PT(504) OR ROM64_INSTR_PT(512) + OR ROM64_INSTR_PT(520) OR ROM64_INSTR_PT(530) + OR ROM64_INSTR_PT(531) OR ROM64_INSTR_PT(535) + OR ROM64_INSTR_PT(544) OR ROM64_INSTR_PT(545) + OR ROM64_INSTR_PT(546) OR ROM64_INSTR_PT(549) + OR ROM64_INSTR_PT(557) OR ROM64_INSTR_PT(559) + OR ROM64_INSTR_PT(564) OR ROM64_INSTR_PT(575) + OR ROM64_INSTR_PT(576) OR ROM64_INSTR_PT(580) + OR ROM64_INSTR_PT(582) OR ROM64_INSTR_PT(591) + OR ROM64_INSTR_PT(597) OR ROM64_INSTR_PT(606) + OR ROM64_INSTR_PT(615) OR ROM64_INSTR_PT(617) + OR ROM64_INSTR_PT(619) OR ROM64_INSTR_PT(623) + OR ROM64_INSTR_PT(627) OR ROM64_INSTR_PT(628) + OR ROM64_INSTR_PT(645) OR ROM64_INSTR_PT(663) + OR ROM64_INSTR_PT(693) OR ROM64_INSTR_PT(705) + OR ROM64_INSTR_PT(736) OR ROM64_INSTR_PT(753) + OR ROM64_INSTR_PT(770) OR ROM64_INSTR_PT(822) + OR ROM64_INSTR_PT(846)); +MQQ916:TEMPLATE(25) <= + (ROM64_INSTR_PT(5) OR ROM64_INSTR_PT(6) + OR ROM64_INSTR_PT(13) OR ROM64_INSTR_PT(21) + OR ROM64_INSTR_PT(25) OR ROM64_INSTR_PT(36) + OR ROM64_INSTR_PT(42) OR ROM64_INSTR_PT(56) + OR ROM64_INSTR_PT(57) OR ROM64_INSTR_PT(73) + OR ROM64_INSTR_PT(97) OR ROM64_INSTR_PT(98) + OR ROM64_INSTR_PT(101) OR ROM64_INSTR_PT(118) + OR ROM64_INSTR_PT(125) OR ROM64_INSTR_PT(128) + OR ROM64_INSTR_PT(134) OR ROM64_INSTR_PT(143) + OR ROM64_INSTR_PT(155) OR ROM64_INSTR_PT(157) + OR ROM64_INSTR_PT(158) OR ROM64_INSTR_PT(162) + OR ROM64_INSTR_PT(168) OR ROM64_INSTR_PT(170) + OR ROM64_INSTR_PT(172) OR ROM64_INSTR_PT(180) + OR ROM64_INSTR_PT(182) OR ROM64_INSTR_PT(184) + OR ROM64_INSTR_PT(194) OR ROM64_INSTR_PT(196) + OR ROM64_INSTR_PT(202) OR ROM64_INSTR_PT(203) + OR ROM64_INSTR_PT(206) OR ROM64_INSTR_PT(216) + OR ROM64_INSTR_PT(219) OR ROM64_INSTR_PT(223) + OR ROM64_INSTR_PT(229) OR ROM64_INSTR_PT(230) + OR ROM64_INSTR_PT(244) OR ROM64_INSTR_PT(253) + OR ROM64_INSTR_PT(260) OR ROM64_INSTR_PT(261) + OR ROM64_INSTR_PT(277) OR ROM64_INSTR_PT(278) + OR ROM64_INSTR_PT(280) OR ROM64_INSTR_PT(283) + OR ROM64_INSTR_PT(294) OR ROM64_INSTR_PT(311) + OR ROM64_INSTR_PT(339) OR ROM64_INSTR_PT(348) + OR ROM64_INSTR_PT(353) OR ROM64_INSTR_PT(361) + OR ROM64_INSTR_PT(365) OR ROM64_INSTR_PT(366) + OR ROM64_INSTR_PT(372) OR ROM64_INSTR_PT(381) + OR ROM64_INSTR_PT(387) OR ROM64_INSTR_PT(395) + OR ROM64_INSTR_PT(397) OR ROM64_INSTR_PT(401) + OR ROM64_INSTR_PT(405) OR ROM64_INSTR_PT(406) + OR ROM64_INSTR_PT(422) OR ROM64_INSTR_PT(426) + OR ROM64_INSTR_PT(427) OR ROM64_INSTR_PT(430) + OR ROM64_INSTR_PT(433) OR ROM64_INSTR_PT(434) + OR ROM64_INSTR_PT(456) OR ROM64_INSTR_PT(458) + OR ROM64_INSTR_PT(460) OR ROM64_INSTR_PT(466) + OR ROM64_INSTR_PT(467) OR ROM64_INSTR_PT(473) + OR ROM64_INSTR_PT(475) OR ROM64_INSTR_PT(488) + OR ROM64_INSTR_PT(490) OR ROM64_INSTR_PT(503) + OR ROM64_INSTR_PT(506) OR ROM64_INSTR_PT(507) + OR ROM64_INSTR_PT(517) OR ROM64_INSTR_PT(520) + OR ROM64_INSTR_PT(523) OR ROM64_INSTR_PT(530) + OR ROM64_INSTR_PT(531) OR ROM64_INSTR_PT(535) + OR ROM64_INSTR_PT(539) OR ROM64_INSTR_PT(542) + OR ROM64_INSTR_PT(545) OR ROM64_INSTR_PT(549) + OR ROM64_INSTR_PT(553) OR ROM64_INSTR_PT(554) + OR ROM64_INSTR_PT(557) OR ROM64_INSTR_PT(568) + OR ROM64_INSTR_PT(575) OR ROM64_INSTR_PT(576) + OR ROM64_INSTR_PT(580) OR ROM64_INSTR_PT(584) + OR ROM64_INSTR_PT(585) OR ROM64_INSTR_PT(592) + OR ROM64_INSTR_PT(597) OR ROM64_INSTR_PT(611) + OR ROM64_INSTR_PT(617) OR ROM64_INSTR_PT(626) + OR ROM64_INSTR_PT(632) OR ROM64_INSTR_PT(636) + OR ROM64_INSTR_PT(642) OR ROM64_INSTR_PT(643) + OR ROM64_INSTR_PT(649) OR ROM64_INSTR_PT(655) + OR ROM64_INSTR_PT(664) OR ROM64_INSTR_PT(693) + OR ROM64_INSTR_PT(702) OR ROM64_INSTR_PT(713) + OR ROM64_INSTR_PT(736) OR ROM64_INSTR_PT(739) + OR ROM64_INSTR_PT(753) OR ROM64_INSTR_PT(798) + OR ROM64_INSTR_PT(822) OR ROM64_INSTR_PT(823) + OR ROM64_INSTR_PT(824) OR ROM64_INSTR_PT(832) + ); +MQQ917:TEMPLATE(26) <= + (ROM64_INSTR_PT(4) OR ROM64_INSTR_PT(5) + OR ROM64_INSTR_PT(6) OR ROM64_INSTR_PT(7) + OR ROM64_INSTR_PT(9) OR ROM64_INSTR_PT(11) + OR ROM64_INSTR_PT(14) OR ROM64_INSTR_PT(21) + OR ROM64_INSTR_PT(22) OR ROM64_INSTR_PT(25) + OR ROM64_INSTR_PT(30) OR ROM64_INSTR_PT(35) + OR ROM64_INSTR_PT(36) OR ROM64_INSTR_PT(38) + OR ROM64_INSTR_PT(41) OR ROM64_INSTR_PT(43) + OR ROM64_INSTR_PT(45) OR ROM64_INSTR_PT(50) + OR ROM64_INSTR_PT(51) OR ROM64_INSTR_PT(52) + OR ROM64_INSTR_PT(56) OR ROM64_INSTR_PT(57) + OR ROM64_INSTR_PT(58) OR ROM64_INSTR_PT(61) + OR ROM64_INSTR_PT(68) OR ROM64_INSTR_PT(69) + OR ROM64_INSTR_PT(70) OR ROM64_INSTR_PT(71) + OR ROM64_INSTR_PT(73) OR ROM64_INSTR_PT(76) + OR ROM64_INSTR_PT(78) OR ROM64_INSTR_PT(82) + OR ROM64_INSTR_PT(83) OR ROM64_INSTR_PT(84) + OR ROM64_INSTR_PT(86) OR ROM64_INSTR_PT(90) + OR ROM64_INSTR_PT(92) OR ROM64_INSTR_PT(93) + OR ROM64_INSTR_PT(95) OR ROM64_INSTR_PT(97) + OR ROM64_INSTR_PT(98) OR ROM64_INSTR_PT(100) + OR ROM64_INSTR_PT(101) OR ROM64_INSTR_PT(102) + OR ROM64_INSTR_PT(105) OR ROM64_INSTR_PT(108) + OR ROM64_INSTR_PT(109) OR ROM64_INSTR_PT(115) + OR ROM64_INSTR_PT(116) OR ROM64_INSTR_PT(117) + OR ROM64_INSTR_PT(118) OR ROM64_INSTR_PT(124) + OR ROM64_INSTR_PT(128) OR ROM64_INSTR_PT(132) + OR ROM64_INSTR_PT(136) OR ROM64_INSTR_PT(137) + OR ROM64_INSTR_PT(140) OR ROM64_INSTR_PT(143) + OR ROM64_INSTR_PT(144) OR ROM64_INSTR_PT(145) + OR ROM64_INSTR_PT(148) OR ROM64_INSTR_PT(153) + OR ROM64_INSTR_PT(154) OR ROM64_INSTR_PT(155) + OR ROM64_INSTR_PT(157) OR ROM64_INSTR_PT(158) + OR ROM64_INSTR_PT(162) OR ROM64_INSTR_PT(169) + OR ROM64_INSTR_PT(172) OR ROM64_INSTR_PT(174) + OR ROM64_INSTR_PT(177) OR ROM64_INSTR_PT(180) + OR ROM64_INSTR_PT(181) OR ROM64_INSTR_PT(183) + OR ROM64_INSTR_PT(185) OR ROM64_INSTR_PT(186) + OR ROM64_INSTR_PT(188) OR ROM64_INSTR_PT(194) + OR ROM64_INSTR_PT(196) OR ROM64_INSTR_PT(201) + OR ROM64_INSTR_PT(203) OR ROM64_INSTR_PT(204) + OR ROM64_INSTR_PT(205) OR ROM64_INSTR_PT(206) + OR ROM64_INSTR_PT(215) OR ROM64_INSTR_PT(216) + OR ROM64_INSTR_PT(218) OR ROM64_INSTR_PT(222) + OR ROM64_INSTR_PT(223) OR ROM64_INSTR_PT(226) + OR ROM64_INSTR_PT(233) OR ROM64_INSTR_PT(238) + OR ROM64_INSTR_PT(241) OR ROM64_INSTR_PT(243) + OR ROM64_INSTR_PT(244) OR ROM64_INSTR_PT(245) + OR ROM64_INSTR_PT(249) OR ROM64_INSTR_PT(253) + OR ROM64_INSTR_PT(254) OR ROM64_INSTR_PT(257) + OR ROM64_INSTR_PT(258) OR ROM64_INSTR_PT(260) + OR ROM64_INSTR_PT(261) OR ROM64_INSTR_PT(263) + OR ROM64_INSTR_PT(264) OR ROM64_INSTR_PT(265) + OR ROM64_INSTR_PT(268) OR ROM64_INSTR_PT(269) + OR ROM64_INSTR_PT(270) OR ROM64_INSTR_PT(271) + OR ROM64_INSTR_PT(273) OR ROM64_INSTR_PT(275) + OR ROM64_INSTR_PT(276) OR ROM64_INSTR_PT(277) + OR ROM64_INSTR_PT(280) OR ROM64_INSTR_PT(282) + OR ROM64_INSTR_PT(283) OR ROM64_INSTR_PT(284) + OR ROM64_INSTR_PT(285) OR ROM64_INSTR_PT(287) + OR ROM64_INSTR_PT(290) OR ROM64_INSTR_PT(293) + OR ROM64_INSTR_PT(294) OR ROM64_INSTR_PT(297) + OR ROM64_INSTR_PT(298) OR ROM64_INSTR_PT(299) + OR ROM64_INSTR_PT(302) OR ROM64_INSTR_PT(305) + OR ROM64_INSTR_PT(308) OR ROM64_INSTR_PT(311) + OR ROM64_INSTR_PT(312) OR ROM64_INSTR_PT(315) + OR ROM64_INSTR_PT(319) OR ROM64_INSTR_PT(339) + OR ROM64_INSTR_PT(348) OR ROM64_INSTR_PT(350) + OR ROM64_INSTR_PT(353) OR ROM64_INSTR_PT(355) + OR ROM64_INSTR_PT(358) OR ROM64_INSTR_PT(364) + OR ROM64_INSTR_PT(365) OR ROM64_INSTR_PT(367) + OR ROM64_INSTR_PT(372) OR ROM64_INSTR_PT(374) + OR ROM64_INSTR_PT(375) OR ROM64_INSTR_PT(378) + OR ROM64_INSTR_PT(379) OR ROM64_INSTR_PT(381) + OR ROM64_INSTR_PT(383) OR ROM64_INSTR_PT(384) + OR ROM64_INSTR_PT(385) OR ROM64_INSTR_PT(388) + OR ROM64_INSTR_PT(391) OR ROM64_INSTR_PT(394) + OR ROM64_INSTR_PT(395) OR ROM64_INSTR_PT(397) + OR ROM64_INSTR_PT(401) OR ROM64_INSTR_PT(403) + OR ROM64_INSTR_PT(404) OR ROM64_INSTR_PT(405) + OR ROM64_INSTR_PT(409) OR ROM64_INSTR_PT(410) + OR ROM64_INSTR_PT(413) OR ROM64_INSTR_PT(414) + OR ROM64_INSTR_PT(415) OR ROM64_INSTR_PT(418) + OR ROM64_INSTR_PT(419) OR ROM64_INSTR_PT(424) + OR ROM64_INSTR_PT(425) OR ROM64_INSTR_PT(426) + OR ROM64_INSTR_PT(427) OR ROM64_INSTR_PT(428) + OR ROM64_INSTR_PT(429) OR ROM64_INSTR_PT(430) + OR ROM64_INSTR_PT(432) OR ROM64_INSTR_PT(435) + OR ROM64_INSTR_PT(437) OR ROM64_INSTR_PT(438) + OR ROM64_INSTR_PT(441) OR ROM64_INSTR_PT(445) + OR ROM64_INSTR_PT(446) OR ROM64_INSTR_PT(451) + OR ROM64_INSTR_PT(453) OR ROM64_INSTR_PT(456) + OR ROM64_INSTR_PT(457) OR ROM64_INSTR_PT(458) + OR ROM64_INSTR_PT(460) OR ROM64_INSTR_PT(461) + OR ROM64_INSTR_PT(463) OR ROM64_INSTR_PT(467) + OR ROM64_INSTR_PT(473) OR ROM64_INSTR_PT(475) + OR ROM64_INSTR_PT(478) OR ROM64_INSTR_PT(481) + OR ROM64_INSTR_PT(482) OR ROM64_INSTR_PT(484) + OR ROM64_INSTR_PT(485) OR ROM64_INSTR_PT(488) + OR ROM64_INSTR_PT(490) OR ROM64_INSTR_PT(493) + OR ROM64_INSTR_PT(495) OR ROM64_INSTR_PT(496) + OR ROM64_INSTR_PT(497) OR ROM64_INSTR_PT(504) + OR ROM64_INSTR_PT(505) OR ROM64_INSTR_PT(506) + OR ROM64_INSTR_PT(509) OR ROM64_INSTR_PT(510) + OR ROM64_INSTR_PT(511) OR ROM64_INSTR_PT(512) + OR ROM64_INSTR_PT(517) OR ROM64_INSTR_PT(520) + OR ROM64_INSTR_PT(521) OR ROM64_INSTR_PT(522) + OR ROM64_INSTR_PT(523) OR ROM64_INSTR_PT(525) + OR ROM64_INSTR_PT(530) OR ROM64_INSTR_PT(531) + OR ROM64_INSTR_PT(534) OR ROM64_INSTR_PT(535) + OR ROM64_INSTR_PT(539) OR ROM64_INSTR_PT(540) + OR ROM64_INSTR_PT(544) OR ROM64_INSTR_PT(546) + OR ROM64_INSTR_PT(549) OR ROM64_INSTR_PT(552) + OR ROM64_INSTR_PT(553) OR ROM64_INSTR_PT(554) + OR ROM64_INSTR_PT(555) OR ROM64_INSTR_PT(557) + OR ROM64_INSTR_PT(558) OR ROM64_INSTR_PT(559) + OR ROM64_INSTR_PT(563) OR ROM64_INSTR_PT(564) + OR ROM64_INSTR_PT(568) OR ROM64_INSTR_PT(569) + OR ROM64_INSTR_PT(570) OR ROM64_INSTR_PT(571) + OR ROM64_INSTR_PT(575) OR ROM64_INSTR_PT(576) + OR ROM64_INSTR_PT(577) OR ROM64_INSTR_PT(579) + OR ROM64_INSTR_PT(580) OR ROM64_INSTR_PT(582) + OR ROM64_INSTR_PT(583) OR ROM64_INSTR_PT(584) + OR ROM64_INSTR_PT(588) OR ROM64_INSTR_PT(591) + OR ROM64_INSTR_PT(592) OR ROM64_INSTR_PT(595) + OR ROM64_INSTR_PT(597) OR ROM64_INSTR_PT(598) + OR ROM64_INSTR_PT(606) OR ROM64_INSTR_PT(608) + OR ROM64_INSTR_PT(609) OR ROM64_INSTR_PT(611) + OR ROM64_INSTR_PT(615) OR ROM64_INSTR_PT(616) + OR ROM64_INSTR_PT(617) OR ROM64_INSTR_PT(618) + OR ROM64_INSTR_PT(619) OR ROM64_INSTR_PT(623) + OR ROM64_INSTR_PT(627) OR ROM64_INSTR_PT(628) + OR ROM64_INSTR_PT(629) OR ROM64_INSTR_PT(632) + OR ROM64_INSTR_PT(633) OR ROM64_INSTR_PT(636) + OR ROM64_INSTR_PT(639) OR ROM64_INSTR_PT(642) + OR ROM64_INSTR_PT(643) OR ROM64_INSTR_PT(655) + OR ROM64_INSTR_PT(660) OR ROM64_INSTR_PT(663) + OR ROM64_INSTR_PT(664) OR ROM64_INSTR_PT(666) + OR ROM64_INSTR_PT(678) OR ROM64_INSTR_PT(695) + OR ROM64_INSTR_PT(702) OR ROM64_INSTR_PT(713) + OR ROM64_INSTR_PT(716) OR ROM64_INSTR_PT(717) + OR ROM64_INSTR_PT(721) OR ROM64_INSTR_PT(722) + OR ROM64_INSTR_PT(723) OR ROM64_INSTR_PT(724) + OR ROM64_INSTR_PT(733) OR ROM64_INSTR_PT(736) + OR ROM64_INSTR_PT(761) OR ROM64_INSTR_PT(770) + OR ROM64_INSTR_PT(798) OR ROM64_INSTR_PT(811) + OR ROM64_INSTR_PT(813) OR ROM64_INSTR_PT(822) + OR ROM64_INSTR_PT(824) OR ROM64_INSTR_PT(832) + OR ROM64_INSTR_PT(834) OR ROM64_INSTR_PT(846) + OR ROM64_INSTR_PT(855) OR ROM64_INSTR_PT(856) + OR ROM64_INSTR_PT(858) OR ROM64_INSTR_PT(864) + OR ROM64_INSTR_PT(870) OR ROM64_INSTR_PT(873) + ); +MQQ918:TEMPLATE(27) <= + (ROM64_INSTR_PT(5) OR ROM64_INSTR_PT(6) + OR ROM64_INSTR_PT(7) OR ROM64_INSTR_PT(8) + OR ROM64_INSTR_PT(9) OR ROM64_INSTR_PT(11) + OR ROM64_INSTR_PT(15) OR ROM64_INSTR_PT(18) + OR ROM64_INSTR_PT(21) OR ROM64_INSTR_PT(22) + OR ROM64_INSTR_PT(35) OR ROM64_INSTR_PT(38) + OR ROM64_INSTR_PT(42) OR ROM64_INSTR_PT(45) + OR ROM64_INSTR_PT(49) OR ROM64_INSTR_PT(52) + OR ROM64_INSTR_PT(53) OR ROM64_INSTR_PT(56) + OR ROM64_INSTR_PT(57) OR ROM64_INSTR_PT(61) + OR ROM64_INSTR_PT(68) OR ROM64_INSTR_PT(69) + OR ROM64_INSTR_PT(71) OR ROM64_INSTR_PT(73) + OR ROM64_INSTR_PT(82) OR ROM64_INSTR_PT(83) + OR ROM64_INSTR_PT(84) OR ROM64_INSTR_PT(90) + OR ROM64_INSTR_PT(93) OR ROM64_INSTR_PT(95) + OR ROM64_INSTR_PT(98) OR ROM64_INSTR_PT(101) + OR ROM64_INSTR_PT(102) OR ROM64_INSTR_PT(108) + OR ROM64_INSTR_PT(109) OR ROM64_INSTR_PT(113) + OR ROM64_INSTR_PT(116) OR ROM64_INSTR_PT(117) + OR ROM64_INSTR_PT(118) OR ROM64_INSTR_PT(128) + OR ROM64_INSTR_PT(132) OR ROM64_INSTR_PT(133) + OR ROM64_INSTR_PT(136) OR ROM64_INSTR_PT(143) + OR ROM64_INSTR_PT(144) OR ROM64_INSTR_PT(145) + OR ROM64_INSTR_PT(148) OR ROM64_INSTR_PT(155) + OR ROM64_INSTR_PT(157) OR ROM64_INSTR_PT(158) + OR ROM64_INSTR_PT(162) OR ROM64_INSTR_PT(164) + OR ROM64_INSTR_PT(168) OR ROM64_INSTR_PT(169) + OR ROM64_INSTR_PT(170) OR ROM64_INSTR_PT(171) + OR ROM64_INSTR_PT(177) OR ROM64_INSTR_PT(180) + OR ROM64_INSTR_PT(181) OR ROM64_INSTR_PT(182) + OR ROM64_INSTR_PT(183) OR ROM64_INSTR_PT(186) + OR ROM64_INSTR_PT(194) OR ROM64_INSTR_PT(196) + OR ROM64_INSTR_PT(201) OR ROM64_INSTR_PT(203) + OR ROM64_INSTR_PT(205) OR ROM64_INSTR_PT(206) + OR ROM64_INSTR_PT(211) OR ROM64_INSTR_PT(215) + OR ROM64_INSTR_PT(218) OR ROM64_INSTR_PT(219) + OR ROM64_INSTR_PT(222) OR ROM64_INSTR_PT(223) + OR ROM64_INSTR_PT(226) OR ROM64_INSTR_PT(233) + OR ROM64_INSTR_PT(238) OR ROM64_INSTR_PT(240) + OR ROM64_INSTR_PT(243) OR ROM64_INSTR_PT(244) + OR ROM64_INSTR_PT(245) OR ROM64_INSTR_PT(249) + OR ROM64_INSTR_PT(253) OR ROM64_INSTR_PT(254) + OR ROM64_INSTR_PT(258) OR ROM64_INSTR_PT(260) + OR ROM64_INSTR_PT(264) OR ROM64_INSTR_PT(265) + OR ROM64_INSTR_PT(268) OR ROM64_INSTR_PT(269) + OR ROM64_INSTR_PT(270) OR ROM64_INSTR_PT(272) + OR ROM64_INSTR_PT(276) OR ROM64_INSTR_PT(278) + OR ROM64_INSTR_PT(280) OR ROM64_INSTR_PT(282) + OR ROM64_INSTR_PT(283) OR ROM64_INSTR_PT(284) + OR ROM64_INSTR_PT(287) OR ROM64_INSTR_PT(290) + OR ROM64_INSTR_PT(293) OR ROM64_INSTR_PT(294) + OR ROM64_INSTR_PT(298) OR ROM64_INSTR_PT(299) + OR ROM64_INSTR_PT(302) OR ROM64_INSTR_PT(311) + OR ROM64_INSTR_PT(312) OR ROM64_INSTR_PT(325) + OR ROM64_INSTR_PT(339) OR ROM64_INSTR_PT(348) + OR ROM64_INSTR_PT(353) OR ROM64_INSTR_PT(361) + OR ROM64_INSTR_PT(364) OR ROM64_INSTR_PT(366) + OR ROM64_INSTR_PT(367) OR ROM64_INSTR_PT(372) + OR ROM64_INSTR_PT(374) OR ROM64_INSTR_PT(375) + OR ROM64_INSTR_PT(378) OR ROM64_INSTR_PT(381) + OR ROM64_INSTR_PT(383) OR ROM64_INSTR_PT(384) + OR ROM64_INSTR_PT(385) OR ROM64_INSTR_PT(391) + OR ROM64_INSTR_PT(395) OR ROM64_INSTR_PT(396) + OR ROM64_INSTR_PT(397) OR ROM64_INSTR_PT(401) + OR ROM64_INSTR_PT(403) OR ROM64_INSTR_PT(405) + OR ROM64_INSTR_PT(406) OR ROM64_INSTR_PT(409) + OR ROM64_INSTR_PT(410) OR ROM64_INSTR_PT(414) + OR ROM64_INSTR_PT(419) OR ROM64_INSTR_PT(425) + OR ROM64_INSTR_PT(426) OR ROM64_INSTR_PT(427) + OR ROM64_INSTR_PT(428) OR ROM64_INSTR_PT(429) + OR ROM64_INSTR_PT(430) OR ROM64_INSTR_PT(433) + OR ROM64_INSTR_PT(435) OR ROM64_INSTR_PT(438) + OR ROM64_INSTR_PT(439) OR ROM64_INSTR_PT(440) + OR ROM64_INSTR_PT(443) OR ROM64_INSTR_PT(445) + OR ROM64_INSTR_PT(451) OR ROM64_INSTR_PT(454) + OR ROM64_INSTR_PT(455) OR ROM64_INSTR_PT(456) + OR ROM64_INSTR_PT(457) OR ROM64_INSTR_PT(460) + OR ROM64_INSTR_PT(467) OR ROM64_INSTR_PT(473) + OR ROM64_INSTR_PT(475) OR ROM64_INSTR_PT(478) + OR ROM64_INSTR_PT(481) OR ROM64_INSTR_PT(482) + OR ROM64_INSTR_PT(484) OR ROM64_INSTR_PT(485) + OR ROM64_INSTR_PT(488) OR ROM64_INSTR_PT(490) + OR ROM64_INSTR_PT(495) OR ROM64_INSTR_PT(506) + OR ROM64_INSTR_PT(509) OR ROM64_INSTR_PT(510) + OR ROM64_INSTR_PT(514) OR ROM64_INSTR_PT(519) + OR ROM64_INSTR_PT(522) OR ROM64_INSTR_PT(523) + OR ROM64_INSTR_PT(525) OR ROM64_INSTR_PT(530) + OR ROM64_INSTR_PT(531) OR ROM64_INSTR_PT(532) + OR ROM64_INSTR_PT(534) OR ROM64_INSTR_PT(539) + OR ROM64_INSTR_PT(542) OR ROM64_INSTR_PT(552) + OR ROM64_INSTR_PT(553) OR ROM64_INSTR_PT(554) + OR ROM64_INSTR_PT(555) OR ROM64_INSTR_PT(557) + OR ROM64_INSTR_PT(563) OR ROM64_INSTR_PT(564) + OR ROM64_INSTR_PT(566) OR ROM64_INSTR_PT(568) + OR ROM64_INSTR_PT(570) OR ROM64_INSTR_PT(571) + OR ROM64_INSTR_PT(576) OR ROM64_INSTR_PT(577) + OR ROM64_INSTR_PT(580) OR ROM64_INSTR_PT(581) + OR ROM64_INSTR_PT(582) OR ROM64_INSTR_PT(583) + OR ROM64_INSTR_PT(584) OR ROM64_INSTR_PT(585) + OR ROM64_INSTR_PT(586) OR ROM64_INSTR_PT(587) + OR ROM64_INSTR_PT(589) OR ROM64_INSTR_PT(592) + OR ROM64_INSTR_PT(597) OR ROM64_INSTR_PT(604) + OR ROM64_INSTR_PT(607) OR ROM64_INSTR_PT(608) + OR ROM64_INSTR_PT(611) OR ROM64_INSTR_PT(616) + OR ROM64_INSTR_PT(619) OR ROM64_INSTR_PT(625) + OR ROM64_INSTR_PT(626) OR ROM64_INSTR_PT(629) + OR ROM64_INSTR_PT(632) OR ROM64_INSTR_PT(633) + OR ROM64_INSTR_PT(636) OR ROM64_INSTR_PT(639) + OR ROM64_INSTR_PT(642) OR ROM64_INSTR_PT(643) + OR ROM64_INSTR_PT(655) OR ROM64_INSTR_PT(660) + OR ROM64_INSTR_PT(663) OR ROM64_INSTR_PT(664) + OR ROM64_INSTR_PT(666) OR ROM64_INSTR_PT(678) + OR ROM64_INSTR_PT(681) OR ROM64_INSTR_PT(698) + OR ROM64_INSTR_PT(702) OR ROM64_INSTR_PT(713) + OR ROM64_INSTR_PT(722) OR ROM64_INSTR_PT(723) + OR ROM64_INSTR_PT(724) OR ROM64_INSTR_PT(733) + OR ROM64_INSTR_PT(736) OR ROM64_INSTR_PT(753) + OR ROM64_INSTR_PT(761) OR ROM64_INSTR_PT(770) + OR ROM64_INSTR_PT(798) OR ROM64_INSTR_PT(811) + OR ROM64_INSTR_PT(813) OR ROM64_INSTR_PT(823) + OR ROM64_INSTR_PT(824) OR ROM64_INSTR_PT(832) + OR ROM64_INSTR_PT(834) OR ROM64_INSTR_PT(854) + OR ROM64_INSTR_PT(855) OR ROM64_INSTR_PT(856) + OR ROM64_INSTR_PT(864) OR ROM64_INSTR_PT(870) + ); +MQQ919:TEMPLATE(28) <= + (ROM64_INSTR_PT(4) OR ROM64_INSTR_PT(5) + OR ROM64_INSTR_PT(6) OR ROM64_INSTR_PT(9) + OR ROM64_INSTR_PT(14) OR ROM64_INSTR_PT(17) + OR ROM64_INSTR_PT(22) OR ROM64_INSTR_PT(34) + OR ROM64_INSTR_PT(38) OR ROM64_INSTR_PT(41) + OR ROM64_INSTR_PT(45) OR ROM64_INSTR_PT(51) + OR ROM64_INSTR_PT(52) OR ROM64_INSTR_PT(56) + OR ROM64_INSTR_PT(57) OR ROM64_INSTR_PT(61) + OR ROM64_INSTR_PT(64) OR ROM64_INSTR_PT(68) + OR ROM64_INSTR_PT(69) OR ROM64_INSTR_PT(70) + OR ROM64_INSTR_PT(71) OR ROM64_INSTR_PT(73) + OR ROM64_INSTR_PT(75) OR ROM64_INSTR_PT(82) + OR ROM64_INSTR_PT(83) OR ROM64_INSTR_PT(84) + OR ROM64_INSTR_PT(86) OR ROM64_INSTR_PT(90) + OR ROM64_INSTR_PT(93) OR ROM64_INSTR_PT(95) + OR ROM64_INSTR_PT(98) OR ROM64_INSTR_PT(99) + OR ROM64_INSTR_PT(100) OR ROM64_INSTR_PT(101) + OR ROM64_INSTR_PT(102) OR ROM64_INSTR_PT(105) + OR ROM64_INSTR_PT(108) OR ROM64_INSTR_PT(113) + OR ROM64_INSTR_PT(115) OR ROM64_INSTR_PT(117) + OR ROM64_INSTR_PT(124) OR ROM64_INSTR_PT(125) + OR ROM64_INSTR_PT(127) OR ROM64_INSTR_PT(128) + OR ROM64_INSTR_PT(134) OR ROM64_INSTR_PT(136) + OR ROM64_INSTR_PT(137) OR ROM64_INSTR_PT(140) + OR ROM64_INSTR_PT(143) OR ROM64_INSTR_PT(144) + OR ROM64_INSTR_PT(148) OR ROM64_INSTR_PT(153) + OR ROM64_INSTR_PT(155) OR ROM64_INSTR_PT(157) + OR ROM64_INSTR_PT(158) OR ROM64_INSTR_PT(162) + OR ROM64_INSTR_PT(169) OR ROM64_INSTR_PT(171) + OR ROM64_INSTR_PT(180) OR ROM64_INSTR_PT(185) + OR ROM64_INSTR_PT(186) OR ROM64_INSTR_PT(194) + OR ROM64_INSTR_PT(196) OR ROM64_INSTR_PT(199) + OR ROM64_INSTR_PT(201) OR ROM64_INSTR_PT(203) + OR ROM64_INSTR_PT(204) OR ROM64_INSTR_PT(206) + OR ROM64_INSTR_PT(215) OR ROM64_INSTR_PT(217) + OR ROM64_INSTR_PT(218) OR ROM64_INSTR_PT(222) + OR ROM64_INSTR_PT(226) OR ROM64_INSTR_PT(238) + OR ROM64_INSTR_PT(241) OR ROM64_INSTR_PT(243) + OR ROM64_INSTR_PT(244) OR ROM64_INSTR_PT(249) + OR ROM64_INSTR_PT(252) OR ROM64_INSTR_PT(253) + OR ROM64_INSTR_PT(258) OR ROM64_INSTR_PT(260) + OR ROM64_INSTR_PT(263) OR ROM64_INSTR_PT(264) + OR ROM64_INSTR_PT(265) OR ROM64_INSTR_PT(268) + OR ROM64_INSTR_PT(269) OR ROM64_INSTR_PT(270) + OR ROM64_INSTR_PT(271) OR ROM64_INSTR_PT(275) + OR ROM64_INSTR_PT(282) OR ROM64_INSTR_PT(283) + OR ROM64_INSTR_PT(284) OR ROM64_INSTR_PT(285) + OR ROM64_INSTR_PT(287) OR ROM64_INSTR_PT(290) + OR ROM64_INSTR_PT(293) OR ROM64_INSTR_PT(294) + OR ROM64_INSTR_PT(297) OR ROM64_INSTR_PT(298) + OR ROM64_INSTR_PT(299) OR ROM64_INSTR_PT(302) + OR ROM64_INSTR_PT(305) OR ROM64_INSTR_PT(308) + OR ROM64_INSTR_PT(311) OR ROM64_INSTR_PT(315) + OR ROM64_INSTR_PT(319) OR ROM64_INSTR_PT(331) + OR ROM64_INSTR_PT(339) OR ROM64_INSTR_PT(348) + OR ROM64_INSTR_PT(353) OR ROM64_INSTR_PT(364) + OR ROM64_INSTR_PT(372) OR ROM64_INSTR_PT(374) + OR ROM64_INSTR_PT(375) OR ROM64_INSTR_PT(379) + OR ROM64_INSTR_PT(381) OR ROM64_INSTR_PT(383) + OR ROM64_INSTR_PT(384) OR ROM64_INSTR_PT(385) + OR ROM64_INSTR_PT(391) OR ROM64_INSTR_PT(394) + OR ROM64_INSTR_PT(395) OR ROM64_INSTR_PT(401) + OR ROM64_INSTR_PT(404) OR ROM64_INSTR_PT(405) + OR ROM64_INSTR_PT(410) OR ROM64_INSTR_PT(413) + OR ROM64_INSTR_PT(414) OR ROM64_INSTR_PT(415) + OR ROM64_INSTR_PT(418) OR ROM64_INSTR_PT(424) + OR ROM64_INSTR_PT(425) OR ROM64_INSTR_PT(426) + OR ROM64_INSTR_PT(428) OR ROM64_INSTR_PT(429) + OR ROM64_INSTR_PT(430) OR ROM64_INSTR_PT(432) + OR ROM64_INSTR_PT(435) OR ROM64_INSTR_PT(437) + OR ROM64_INSTR_PT(441) OR ROM64_INSTR_PT(446) + OR ROM64_INSTR_PT(451) OR ROM64_INSTR_PT(453) + OR ROM64_INSTR_PT(456) OR ROM64_INSTR_PT(457) + OR ROM64_INSTR_PT(460) OR ROM64_INSTR_PT(467) + OR ROM64_INSTR_PT(473) OR ROM64_INSTR_PT(475) + OR ROM64_INSTR_PT(478) OR ROM64_INSTR_PT(481) + OR ROM64_INSTR_PT(482) OR ROM64_INSTR_PT(484) + OR ROM64_INSTR_PT(485) OR ROM64_INSTR_PT(488) + OR ROM64_INSTR_PT(490) OR ROM64_INSTR_PT(493) + OR ROM64_INSTR_PT(495) OR ROM64_INSTR_PT(496) + OR ROM64_INSTR_PT(504) OR ROM64_INSTR_PT(505) + OR ROM64_INSTR_PT(506) OR ROM64_INSTR_PT(507) + OR ROM64_INSTR_PT(509) OR ROM64_INSTR_PT(511) + OR ROM64_INSTR_PT(512) OR ROM64_INSTR_PT(517) + OR ROM64_INSTR_PT(521) OR ROM64_INSTR_PT(522) + OR ROM64_INSTR_PT(525) OR ROM64_INSTR_PT(530) + OR ROM64_INSTR_PT(531) OR ROM64_INSTR_PT(534) + OR ROM64_INSTR_PT(539) OR ROM64_INSTR_PT(546) + OR ROM64_INSTR_PT(552) OR ROM64_INSTR_PT(553) + OR ROM64_INSTR_PT(554) OR ROM64_INSTR_PT(555) + OR ROM64_INSTR_PT(557) OR ROM64_INSTR_PT(558) + OR ROM64_INSTR_PT(559) OR ROM64_INSTR_PT(563) + OR ROM64_INSTR_PT(564) OR ROM64_INSTR_PT(568) + OR ROM64_INSTR_PT(569) OR ROM64_INSTR_PT(577) + OR ROM64_INSTR_PT(579) OR ROM64_INSTR_PT(580) + OR ROM64_INSTR_PT(582) OR ROM64_INSTR_PT(583) + OR ROM64_INSTR_PT(588) OR ROM64_INSTR_PT(591) + OR ROM64_INSTR_PT(592) OR ROM64_INSTR_PT(595) + OR ROM64_INSTR_PT(597) OR ROM64_INSTR_PT(600) + OR ROM64_INSTR_PT(606) OR ROM64_INSTR_PT(608) + OR ROM64_INSTR_PT(611) OR ROM64_INSTR_PT(615) + OR ROM64_INSTR_PT(618) OR ROM64_INSTR_PT(619) + OR ROM64_INSTR_PT(623) OR ROM64_INSTR_PT(627) + OR ROM64_INSTR_PT(629) OR ROM64_INSTR_PT(632) + OR ROM64_INSTR_PT(633) OR ROM64_INSTR_PT(636) + OR ROM64_INSTR_PT(639) OR ROM64_INSTR_PT(642) + OR ROM64_INSTR_PT(643) OR ROM64_INSTR_PT(644) + OR ROM64_INSTR_PT(655) OR ROM64_INSTR_PT(660) + OR ROM64_INSTR_PT(664) OR ROM64_INSTR_PT(666) + OR ROM64_INSTR_PT(678) OR ROM64_INSTR_PT(702) + OR ROM64_INSTR_PT(713) OR ROM64_INSTR_PT(722) + OR ROM64_INSTR_PT(728) OR ROM64_INSTR_PT(735) + OR ROM64_INSTR_PT(736) OR ROM64_INSTR_PT(738) + OR ROM64_INSTR_PT(739) OR ROM64_INSTR_PT(744) + OR ROM64_INSTR_PT(761) OR ROM64_INSTR_PT(769) + OR ROM64_INSTR_PT(770) OR ROM64_INSTR_PT(776) + OR ROM64_INSTR_PT(798) OR ROM64_INSTR_PT(811) + OR ROM64_INSTR_PT(813) OR ROM64_INSTR_PT(824) + OR ROM64_INSTR_PT(832) OR ROM64_INSTR_PT(855) + OR ROM64_INSTR_PT(856) OR ROM64_INSTR_PT(864) + OR ROM64_INSTR_PT(870)); +MQQ920:TEMPLATE(29) <= + (ROM64_INSTR_PT(4) OR ROM64_INSTR_PT(5) + OR ROM64_INSTR_PT(6) OR ROM64_INSTR_PT(7) + OR ROM64_INSTR_PT(8) OR ROM64_INSTR_PT(9) + OR ROM64_INSTR_PT(11) OR ROM64_INSTR_PT(14) + OR ROM64_INSTR_PT(15) OR ROM64_INSTR_PT(17) + OR ROM64_INSTR_PT(18) OR ROM64_INSTR_PT(22) + OR ROM64_INSTR_PT(25) OR ROM64_INSTR_PT(28) + OR ROM64_INSTR_PT(31) OR ROM64_INSTR_PT(38) + OR ROM64_INSTR_PT(41) OR ROM64_INSTR_PT(49) + OR ROM64_INSTR_PT(51) OR ROM64_INSTR_PT(52) + OR ROM64_INSTR_PT(53) OR ROM64_INSTR_PT(61) + OR ROM64_INSTR_PT(64) OR ROM64_INSTR_PT(70) + OR ROM64_INSTR_PT(71) OR ROM64_INSTR_PT(75) + OR ROM64_INSTR_PT(76) OR ROM64_INSTR_PT(83) + OR ROM64_INSTR_PT(86) OR ROM64_INSTR_PT(90) + OR ROM64_INSTR_PT(93) OR ROM64_INSTR_PT(97) + OR ROM64_INSTR_PT(99) OR ROM64_INSTR_PT(100) + OR ROM64_INSTR_PT(102) OR ROM64_INSTR_PT(105) + OR ROM64_INSTR_PT(113) OR ROM64_INSTR_PT(115) + OR ROM64_INSTR_PT(116) OR ROM64_INSTR_PT(117) + OR ROM64_INSTR_PT(124) OR ROM64_INSTR_PT(127) + OR ROM64_INSTR_PT(132) OR ROM64_INSTR_PT(133) + OR ROM64_INSTR_PT(134) OR ROM64_INSTR_PT(136) + OR ROM64_INSTR_PT(137) OR ROM64_INSTR_PT(140) + OR ROM64_INSTR_PT(144) OR ROM64_INSTR_PT(148) + OR ROM64_INSTR_PT(153) OR ROM64_INSTR_PT(158) + OR ROM64_INSTR_PT(164) OR ROM64_INSTR_PT(168) + OR ROM64_INSTR_PT(169) OR ROM64_INSTR_PT(171) + OR ROM64_INSTR_PT(172) OR ROM64_INSTR_PT(181) + OR ROM64_INSTR_PT(184) OR ROM64_INSTR_PT(185) + OR ROM64_INSTR_PT(186) OR ROM64_INSTR_PT(194) + OR ROM64_INSTR_PT(199) OR ROM64_INSTR_PT(202) + OR ROM64_INSTR_PT(204) OR ROM64_INSTR_PT(211) + OR ROM64_INSTR_PT(215) OR ROM64_INSTR_PT(217) + OR ROM64_INSTR_PT(218) OR ROM64_INSTR_PT(219) + OR ROM64_INSTR_PT(222) OR ROM64_INSTR_PT(226) + OR ROM64_INSTR_PT(229) OR ROM64_INSTR_PT(230) + OR ROM64_INSTR_PT(238) OR ROM64_INSTR_PT(241) + OR ROM64_INSTR_PT(245) OR ROM64_INSTR_PT(252) + OR ROM64_INSTR_PT(253) OR ROM64_INSTR_PT(260) + OR ROM64_INSTR_PT(263) OR ROM64_INSTR_PT(264) + OR ROM64_INSTR_PT(268) OR ROM64_INSTR_PT(270) + OR ROM64_INSTR_PT(271) OR ROM64_INSTR_PT(272) + OR ROM64_INSTR_PT(273) OR ROM64_INSTR_PT(275) + OR ROM64_INSTR_PT(276) OR ROM64_INSTR_PT(277) + OR ROM64_INSTR_PT(282) OR ROM64_INSTR_PT(283) + OR ROM64_INSTR_PT(285) OR ROM64_INSTR_PT(287) + OR ROM64_INSTR_PT(293) OR ROM64_INSTR_PT(294) + OR ROM64_INSTR_PT(297) OR ROM64_INSTR_PT(298) + OR ROM64_INSTR_PT(299) OR ROM64_INSTR_PT(302) + OR ROM64_INSTR_PT(305) OR ROM64_INSTR_PT(308) + OR ROM64_INSTR_PT(311) OR ROM64_INSTR_PT(312) + OR ROM64_INSTR_PT(315) OR ROM64_INSTR_PT(319) + OR ROM64_INSTR_PT(324) OR ROM64_INSTR_PT(325) + OR ROM64_INSTR_PT(331) OR ROM64_INSTR_PT(340) + OR ROM64_INSTR_PT(361) OR ROM64_INSTR_PT(364) + OR ROM64_INSTR_PT(374) OR ROM64_INSTR_PT(375) + OR ROM64_INSTR_PT(379) OR ROM64_INSTR_PT(383) + OR ROM64_INSTR_PT(384) OR ROM64_INSTR_PT(385) + OR ROM64_INSTR_PT(388) OR ROM64_INSTR_PT(391) + OR ROM64_INSTR_PT(394) OR ROM64_INSTR_PT(401) + OR ROM64_INSTR_PT(403) OR ROM64_INSTR_PT(404) + OR ROM64_INSTR_PT(406) OR ROM64_INSTR_PT(410) + OR ROM64_INSTR_PT(413) OR ROM64_INSTR_PT(414) + OR ROM64_INSTR_PT(415) OR ROM64_INSTR_PT(418) + OR ROM64_INSTR_PT(424) OR ROM64_INSTR_PT(428) + OR ROM64_INSTR_PT(430) OR ROM64_INSTR_PT(432) + OR ROM64_INSTR_PT(434) OR ROM64_INSTR_PT(437) + OR ROM64_INSTR_PT(438) OR ROM64_INSTR_PT(439) + OR ROM64_INSTR_PT(440) OR ROM64_INSTR_PT(441) + OR ROM64_INSTR_PT(443) OR ROM64_INSTR_PT(445) + OR ROM64_INSTR_PT(446) OR ROM64_INSTR_PT(453) + OR ROM64_INSTR_PT(454) OR ROM64_INSTR_PT(455) + OR ROM64_INSTR_PT(468) OR ROM64_INSTR_PT(478) + OR ROM64_INSTR_PT(481) OR ROM64_INSTR_PT(482) + OR ROM64_INSTR_PT(484) OR ROM64_INSTR_PT(485) + OR ROM64_INSTR_PT(493) OR ROM64_INSTR_PT(495) + OR ROM64_INSTR_PT(496) OR ROM64_INSTR_PT(503) + OR ROM64_INSTR_PT(504) OR ROM64_INSTR_PT(505) + OR ROM64_INSTR_PT(509) OR ROM64_INSTR_PT(510) + OR ROM64_INSTR_PT(511) OR ROM64_INSTR_PT(512) + OR ROM64_INSTR_PT(516) OR ROM64_INSTR_PT(519) + OR ROM64_INSTR_PT(521) OR ROM64_INSTR_PT(522) + OR ROM64_INSTR_PT(525) OR ROM64_INSTR_PT(530) + OR ROM64_INSTR_PT(531) OR ROM64_INSTR_PT(532) + OR ROM64_INSTR_PT(534) OR ROM64_INSTR_PT(535) + OR ROM64_INSTR_PT(544) OR ROM64_INSTR_PT(545) + OR ROM64_INSTR_PT(546) OR ROM64_INSTR_PT(549) + OR ROM64_INSTR_PT(552) OR ROM64_INSTR_PT(555) + OR ROM64_INSTR_PT(558) OR ROM64_INSTR_PT(559) + OR ROM64_INSTR_PT(563) OR ROM64_INSTR_PT(564) + OR ROM64_INSTR_PT(566) OR ROM64_INSTR_PT(569) + OR ROM64_INSTR_PT(571) OR ROM64_INSTR_PT(575) + OR ROM64_INSTR_PT(576) OR ROM64_INSTR_PT(579) + OR ROM64_INSTR_PT(580) OR ROM64_INSTR_PT(581) + OR ROM64_INSTR_PT(582) OR ROM64_INSTR_PT(583) + OR ROM64_INSTR_PT(586) OR ROM64_INSTR_PT(587) + OR ROM64_INSTR_PT(588) OR ROM64_INSTR_PT(589) + OR ROM64_INSTR_PT(591) OR ROM64_INSTR_PT(595) + OR ROM64_INSTR_PT(600) OR ROM64_INSTR_PT(604) + OR ROM64_INSTR_PT(606) OR ROM64_INSTR_PT(607) + OR ROM64_INSTR_PT(608) OR ROM64_INSTR_PT(615) + OR ROM64_INSTR_PT(618) OR ROM64_INSTR_PT(625) + OR ROM64_INSTR_PT(627) OR ROM64_INSTR_PT(628) + OR ROM64_INSTR_PT(629) OR ROM64_INSTR_PT(632) + OR ROM64_INSTR_PT(633) OR ROM64_INSTR_PT(639) + OR ROM64_INSTR_PT(642) OR ROM64_INSTR_PT(644) + OR ROM64_INSTR_PT(663) OR ROM64_INSTR_PT(664) + OR ROM64_INSTR_PT(666) OR ROM64_INSTR_PT(678) + OR ROM64_INSTR_PT(681) OR ROM64_INSTR_PT(698) + OR ROM64_INSTR_PT(702) OR ROM64_INSTR_PT(722) + OR ROM64_INSTR_PT(728) OR ROM64_INSTR_PT(731) + OR ROM64_INSTR_PT(735) OR ROM64_INSTR_PT(738) + OR ROM64_INSTR_PT(744) OR ROM64_INSTR_PT(761) + OR ROM64_INSTR_PT(769) OR ROM64_INSTR_PT(776) + OR ROM64_INSTR_PT(798) OR ROM64_INSTR_PT(832) + OR ROM64_INSTR_PT(846) OR ROM64_INSTR_PT(854) + OR ROM64_INSTR_PT(856) OR ROM64_INSTR_PT(864) + OR ROM64_INSTR_PT(870)); +MQQ921:TEMPLATE(30) <= + (ROM64_INSTR_PT(4) OR ROM64_INSTR_PT(5) + OR ROM64_INSTR_PT(7) OR ROM64_INSTR_PT(9) + OR ROM64_INSTR_PT(10) OR ROM64_INSTR_PT(14) + OR ROM64_INSTR_PT(17) OR ROM64_INSTR_PT(21) + OR ROM64_INSTR_PT(22) OR ROM64_INSTR_PT(34) + OR ROM64_INSTR_PT(38) OR ROM64_INSTR_PT(41) + OR ROM64_INSTR_PT(45) OR ROM64_INSTR_PT(50) + OR ROM64_INSTR_PT(51) OR ROM64_INSTR_PT(52) + OR ROM64_INSTR_PT(55) OR ROM64_INSTR_PT(61) + OR ROM64_INSTR_PT(64) OR ROM64_INSTR_PT(70) + OR ROM64_INSTR_PT(71) OR ROM64_INSTR_PT(75) + OR ROM64_INSTR_PT(76) OR ROM64_INSTR_PT(77) + OR ROM64_INSTR_PT(78) OR ROM64_INSTR_PT(80) + OR ROM64_INSTR_PT(83) OR ROM64_INSTR_PT(84) + OR ROM64_INSTR_PT(86) OR ROM64_INSTR_PT(89) + OR ROM64_INSTR_PT(90) OR ROM64_INSTR_PT(92) + OR ROM64_INSTR_PT(96) OR ROM64_INSTR_PT(99) + OR ROM64_INSTR_PT(100) OR ROM64_INSTR_PT(102) + OR ROM64_INSTR_PT(104) OR ROM64_INSTR_PT(105) + OR ROM64_INSTR_PT(106) OR ROM64_INSTR_PT(110) + OR ROM64_INSTR_PT(113) OR ROM64_INSTR_PT(114) + OR ROM64_INSTR_PT(115) OR ROM64_INSTR_PT(116) + OR ROM64_INSTR_PT(117) OR ROM64_INSTR_PT(118) + OR ROM64_INSTR_PT(121) OR ROM64_INSTR_PT(124) + OR ROM64_INSTR_PT(127) OR ROM64_INSTR_PT(132) + OR ROM64_INSTR_PT(136) OR ROM64_INSTR_PT(137) + OR ROM64_INSTR_PT(140) OR ROM64_INSTR_PT(143) + OR ROM64_INSTR_PT(144) OR ROM64_INSTR_PT(148) + OR ROM64_INSTR_PT(153) OR ROM64_INSTR_PT(169) + OR ROM64_INSTR_PT(171) OR ROM64_INSTR_PT(175) + OR ROM64_INSTR_PT(177) OR ROM64_INSTR_PT(180) + OR ROM64_INSTR_PT(181) OR ROM64_INSTR_PT(183) + OR ROM64_INSTR_PT(184) OR ROM64_INSTR_PT(185) + OR ROM64_INSTR_PT(186) OR ROM64_INSTR_PT(188) + OR ROM64_INSTR_PT(194) OR ROM64_INSTR_PT(199) + OR ROM64_INSTR_PT(202) OR ROM64_INSTR_PT(204) + OR ROM64_INSTR_PT(208) OR ROM64_INSTR_PT(213) + OR ROM64_INSTR_PT(214) OR ROM64_INSTR_PT(215) + OR ROM64_INSTR_PT(217) OR ROM64_INSTR_PT(218) + OR ROM64_INSTR_PT(221) OR ROM64_INSTR_PT(222) + OR ROM64_INSTR_PT(223) OR ROM64_INSTR_PT(226) + OR ROM64_INSTR_PT(229) OR ROM64_INSTR_PT(230) + OR ROM64_INSTR_PT(233) OR ROM64_INSTR_PT(238) + OR ROM64_INSTR_PT(241) OR ROM64_INSTR_PT(252) + OR ROM64_INSTR_PT(258) OR ROM64_INSTR_PT(260) + OR ROM64_INSTR_PT(263) OR ROM64_INSTR_PT(264) + OR ROM64_INSTR_PT(268) OR ROM64_INSTR_PT(270) + OR ROM64_INSTR_PT(271) OR ROM64_INSTR_PT(274) + OR ROM64_INSTR_PT(275) OR ROM64_INSTR_PT(276) + OR ROM64_INSTR_PT(280) OR ROM64_INSTR_PT(282) + OR ROM64_INSTR_PT(285) OR ROM64_INSTR_PT(286) + OR ROM64_INSTR_PT(293) OR ROM64_INSTR_PT(297) + OR ROM64_INSTR_PT(298) OR ROM64_INSTR_PT(299) + OR ROM64_INSTR_PT(302) OR ROM64_INSTR_PT(305) + OR ROM64_INSTR_PT(308) OR ROM64_INSTR_PT(315) + OR ROM64_INSTR_PT(319) OR ROM64_INSTR_PT(322) + OR ROM64_INSTR_PT(331) OR ROM64_INSTR_PT(339) + OR ROM64_INSTR_PT(347) OR ROM64_INSTR_PT(349) + OR ROM64_INSTR_PT(350) OR ROM64_INSTR_PT(358) + OR ROM64_INSTR_PT(364) OR ROM64_INSTR_PT(367) + OR ROM64_INSTR_PT(369) OR ROM64_INSTR_PT(371) + OR ROM64_INSTR_PT(374) OR ROM64_INSTR_PT(375) + OR ROM64_INSTR_PT(378) OR ROM64_INSTR_PT(379) + OR ROM64_INSTR_PT(383) OR ROM64_INSTR_PT(385) + OR ROM64_INSTR_PT(391) OR ROM64_INSTR_PT(394) + OR ROM64_INSTR_PT(397) OR ROM64_INSTR_PT(403) + OR ROM64_INSTR_PT(404) OR ROM64_INSTR_PT(410) + OR ROM64_INSTR_PT(413) OR ROM64_INSTR_PT(414) + OR ROM64_INSTR_PT(415) OR ROM64_INSTR_PT(418) + OR ROM64_INSTR_PT(422) OR ROM64_INSTR_PT(424) + OR ROM64_INSTR_PT(427) OR ROM64_INSTR_PT(430) + OR ROM64_INSTR_PT(432) OR ROM64_INSTR_PT(434) + OR ROM64_INSTR_PT(435) OR ROM64_INSTR_PT(437) + OR ROM64_INSTR_PT(441) OR ROM64_INSTR_PT(445) + OR ROM64_INSTR_PT(446) OR ROM64_INSTR_PT(453) + OR ROM64_INSTR_PT(461) OR ROM64_INSTR_PT(463) + OR ROM64_INSTR_PT(466) OR ROM64_INSTR_PT(478) + OR ROM64_INSTR_PT(481) OR ROM64_INSTR_PT(482) + OR ROM64_INSTR_PT(484) OR ROM64_INSTR_PT(485) + OR ROM64_INSTR_PT(493) OR ROM64_INSTR_PT(495) + OR ROM64_INSTR_PT(496) OR ROM64_INSTR_PT(503) + OR ROM64_INSTR_PT(504) OR ROM64_INSTR_PT(505) + OR ROM64_INSTR_PT(509) OR ROM64_INSTR_PT(510) + OR ROM64_INSTR_PT(511) OR ROM64_INSTR_PT(512) + OR ROM64_INSTR_PT(521) OR ROM64_INSTR_PT(522) + OR ROM64_INSTR_PT(523) OR ROM64_INSTR_PT(525) + OR ROM64_INSTR_PT(534) OR ROM64_INSTR_PT(540) + OR ROM64_INSTR_PT(545) OR ROM64_INSTR_PT(546) + OR ROM64_INSTR_PT(552) OR ROM64_INSTR_PT(555) + OR ROM64_INSTR_PT(557) OR ROM64_INSTR_PT(558) + OR ROM64_INSTR_PT(559) OR ROM64_INSTR_PT(563) + OR ROM64_INSTR_PT(569) OR ROM64_INSTR_PT(571) + OR ROM64_INSTR_PT(576) OR ROM64_INSTR_PT(579) + OR ROM64_INSTR_PT(582) OR ROM64_INSTR_PT(583) + OR ROM64_INSTR_PT(584) OR ROM64_INSTR_PT(588) + OR ROM64_INSTR_PT(591) OR ROM64_INSTR_PT(592) + OR ROM64_INSTR_PT(595) OR ROM64_INSTR_PT(596) + OR ROM64_INSTR_PT(600) OR ROM64_INSTR_PT(606) + OR ROM64_INSTR_PT(608) OR ROM64_INSTR_PT(609) + OR ROM64_INSTR_PT(613) OR ROM64_INSTR_PT(615) + OR ROM64_INSTR_PT(618) OR ROM64_INSTR_PT(619) + OR ROM64_INSTR_PT(627) OR ROM64_INSTR_PT(629) + OR ROM64_INSTR_PT(632) OR ROM64_INSTR_PT(633) + OR ROM64_INSTR_PT(639) OR ROM64_INSTR_PT(642) + OR ROM64_INSTR_PT(644) OR ROM64_INSTR_PT(666) + OR ROM64_INSTR_PT(678) OR ROM64_INSTR_PT(685) + OR ROM64_INSTR_PT(687) OR ROM64_INSTR_PT(691) + OR ROM64_INSTR_PT(695) OR ROM64_INSTR_PT(716) + OR ROM64_INSTR_PT(722) OR ROM64_INSTR_PT(723) + OR ROM64_INSTR_PT(724) OR ROM64_INSTR_PT(728) + OR ROM64_INSTR_PT(731) OR ROM64_INSTR_PT(733) + OR ROM64_INSTR_PT(735) OR ROM64_INSTR_PT(736) + OR ROM64_INSTR_PT(738) OR ROM64_INSTR_PT(744) + OR ROM64_INSTR_PT(761) OR ROM64_INSTR_PT(769) + OR ROM64_INSTR_PT(770) OR ROM64_INSTR_PT(776) + OR ROM64_INSTR_PT(834) OR ROM64_INSTR_PT(846) + OR ROM64_INSTR_PT(856) OR ROM64_INSTR_PT(864) + OR ROM64_INSTR_PT(870)); +MQQ922:TEMPLATE(31) <= + (ROM64_INSTR_PT(33) OR ROM64_INSTR_PT(60) + OR ROM64_INSTR_PT(79) OR ROM64_INSTR_PT(98) + OR ROM64_INSTR_PT(103) OR ROM64_INSTR_PT(142) + OR ROM64_INSTR_PT(147) OR ROM64_INSTR_PT(150) + OR ROM64_INSTR_PT(160) OR ROM64_INSTR_PT(168) + OR ROM64_INSTR_PT(176) OR ROM64_INSTR_PT(187) + OR ROM64_INSTR_PT(207) OR ROM64_INSTR_PT(209) + OR ROM64_INSTR_PT(219) OR ROM64_INSTR_PT(224) + OR ROM64_INSTR_PT(228) OR ROM64_INSTR_PT(231) + OR ROM64_INSTR_PT(247) OR ROM64_INSTR_PT(253) + OR ROM64_INSTR_PT(281) OR ROM64_INSTR_PT(288) + OR ROM64_INSTR_PT(296) OR ROM64_INSTR_PT(304) + OR ROM64_INSTR_PT(309) OR ROM64_INSTR_PT(314) + OR ROM64_INSTR_PT(327) OR ROM64_INSTR_PT(332) + OR ROM64_INSTR_PT(341) OR ROM64_INSTR_PT(352) + OR ROM64_INSTR_PT(361) OR ROM64_INSTR_PT(374) + OR ROM64_INSTR_PT(401) OR ROM64_INSTR_PT(406) + OR ROM64_INSTR_PT(464) OR ROM64_INSTR_PT(471) + OR ROM64_INSTR_PT(491) OR ROM64_INSTR_PT(597) + OR ROM64_INSTR_PT(632) OR ROM64_INSTR_PT(635) + OR ROM64_INSTR_PT(641) OR ROM64_INSTR_PT(654) + OR ROM64_INSTR_PT(675) OR ROM64_INSTR_PT(723) + OR ROM64_INSTR_PT(724) OR ROM64_INSTR_PT(728) + OR ROM64_INSTR_PT(733) OR ROM64_INSTR_PT(735) + OR ROM64_INSTR_PT(738) OR ROM64_INSTR_PT(759) + OR ROM64_INSTR_PT(766) OR ROM64_INSTR_PT(781) + OR ROM64_INSTR_PT(794) OR ROM64_INSTR_PT(809) + ); +MQQ923:UCODE_END <= + (ROM64_INSTR_PT(198) OR ROM64_INSTR_PT(200) + OR ROM64_INSTR_PT(212) OR ROM64_INSTR_PT(386) + OR ROM64_INSTR_PT(443) OR ROM64_INSTR_PT(444) + OR ROM64_INSTR_PT(452) OR ROM64_INSTR_PT(516) + OR ROM64_INSTR_PT(518) OR ROM64_INSTR_PT(528) + OR ROM64_INSTR_PT(542) OR ROM64_INSTR_PT(550) + OR ROM64_INSTR_PT(556) OR ROM64_INSTR_PT(560) + OR ROM64_INSTR_PT(567) OR ROM64_INSTR_PT(574) + OR ROM64_INSTR_PT(577) OR ROM64_INSTR_PT(578) + OR ROM64_INSTR_PT(581) OR ROM64_INSTR_PT(593) + OR ROM64_INSTR_PT(604) OR ROM64_INSTR_PT(606) + OR ROM64_INSTR_PT(607) OR ROM64_INSTR_PT(622) + OR ROM64_INSTR_PT(663) OR ROM64_INSTR_PT(668) + OR ROM64_INSTR_PT(690) OR ROM64_INSTR_PT(699) + OR ROM64_INSTR_PT(704) OR ROM64_INSTR_PT(706) + OR ROM64_INSTR_PT(714) OR ROM64_INSTR_PT(718) + OR ROM64_INSTR_PT(741) OR ROM64_INSTR_PT(785) + OR ROM64_INSTR_PT(790) OR ROM64_INSTR_PT(813) + OR ROM64_INSTR_PT(823) OR ROM64_INSTR_PT(824) + OR ROM64_INSTR_PT(826) OR ROM64_INSTR_PT(828) + OR ROM64_INSTR_PT(841) OR ROM64_INSTR_PT(844) + OR ROM64_INSTR_PT(845) OR ROM64_INSTR_PT(849) + OR ROM64_INSTR_PT(854)); +MQQ924:UCODE_END_EARLY <= + (ROM64_INSTR_PT(376) OR ROM64_INSTR_PT(390) + OR ROM64_INSTR_PT(650) OR ROM64_INSTR_PT(676) + OR ROM64_INSTR_PT(683) OR ROM64_INSTR_PT(689) + OR ROM64_INSTR_PT(730) OR ROM64_INSTR_PT(742) + OR ROM64_INSTR_PT(757) OR ROM64_INSTR_PT(760) + OR ROM64_INSTR_PT(787) OR ROM64_INSTR_PT(788) + OR ROM64_INSTR_PT(800) OR ROM64_INSTR_PT(802) + OR ROM64_INSTR_PT(803) OR ROM64_INSTR_PT(807) + OR ROM64_INSTR_PT(814) OR ROM64_INSTR_PT(818) + OR ROM64_INSTR_PT(825) OR ROM64_INSTR_PT(830) + OR ROM64_INSTR_PT(874)); +MQQ925:LOOP_BEGIN <= + (ROM64_INSTR_PT(26) OR ROM64_INSTR_PT(55) + OR ROM64_INSTR_PT(104) OR ROM64_INSTR_PT(124) + OR ROM64_INSTR_PT(147) OR ROM64_INSTR_PT(210) + OR ROM64_INSTR_PT(228) OR ROM64_INSTR_PT(231) + OR ROM64_INSTR_PT(239) OR ROM64_INSTR_PT(246) + OR ROM64_INSTR_PT(255) OR ROM64_INSTR_PT(306) + OR ROM64_INSTR_PT(310) OR ROM64_INSTR_PT(316) + OR ROM64_INSTR_PT(322) OR ROM64_INSTR_PT(349) + OR ROM64_INSTR_PT(369) OR ROM64_INSTR_PT(379) + OR ROM64_INSTR_PT(411) OR ROM64_INSTR_PT(412) + OR ROM64_INSTR_PT(436) OR ROM64_INSTR_PT(450) + OR ROM64_INSTR_PT(462) OR ROM64_INSTR_PT(487) + OR ROM64_INSTR_PT(493) OR ROM64_INSTR_PT(496) + OR ROM64_INSTR_PT(546) OR ROM64_INSTR_PT(559) + OR ROM64_INSTR_PT(572) OR ROM64_INSTR_PT(590) + OR ROM64_INSTR_PT(610)); +MQQ926:LOOP_END <= + (ROM64_INSTR_PT(149) OR ROM64_INSTR_PT(156) + OR ROM64_INSTR_PT(376) OR ROM64_INSTR_PT(469) + OR ROM64_INSTR_PT(494) OR ROM64_INSTR_PT(502) + OR ROM64_INSTR_PT(565) OR ROM64_INSTR_PT(638) + OR ROM64_INSTR_PT(647) OR ROM64_INSTR_PT(656) + OR ROM64_INSTR_PT(680) OR ROM64_INSTR_PT(701) + OR ROM64_INSTR_PT(751) OR ROM64_INSTR_PT(775) + OR ROM64_INSTR_PT(779) OR ROM64_INSTR_PT(789) + OR ROM64_INSTR_PT(799) OR ROM64_INSTR_PT(807) + OR ROM64_INSTR_PT(815) OR ROM64_INSTR_PT(816) + OR ROM64_INSTR_PT(850) OR ROM64_INSTR_PT(862) + OR ROM64_INSTR_PT(875)); +MQQ927:COUNT_SRC(0) <= + (ROM64_INSTR_PT(72) OR ROM64_INSTR_PT(752) + OR ROM64_INSTR_PT(768) OR ROM64_INSTR_PT(876) + OR ROM64_INSTR_PT(881) OR ROM64_INSTR_PT(882) + OR ROM64_INSTR_PT(887) OR ROM64_INSTR_PT(888) + OR ROM64_INSTR_PT(889)); +MQQ928:COUNT_SRC(1) <= + (ROM64_INSTR_PT(839) OR ROM64_INSTR_PT(879) + OR ROM64_INSTR_PT(882) OR ROM64_INSTR_PT(884) + OR ROM64_INSTR_PT(885) OR ROM64_INSTR_PT(888) + OR ROM64_INSTR_PT(889)); +MQQ929:COUNT_SRC(2) <= + (ROM64_INSTR_PT(686) OR ROM64_INSTR_PT(752) + OR ROM64_INSTR_PT(768) OR ROM64_INSTR_PT(831) + OR ROM64_INSTR_PT(839) OR ROM64_INSTR_PT(887) + OR ROM64_INSTR_PT(888) OR ROM64_INSTR_PT(889) + ); +MQQ930:EXTRT <= + (ROM64_INSTR_PT(4) OR ROM64_INSTR_PT(6) + OR ROM64_INSTR_PT(19) OR ROM64_INSTR_PT(24) + OR ROM64_INSTR_PT(27) OR ROM64_INSTR_PT(47) + OR ROM64_INSTR_PT(48) OR ROM64_INSTR_PT(63) + OR ROM64_INSTR_PT(69) OR ROM64_INSTR_PT(74) + OR ROM64_INSTR_PT(91) OR ROM64_INSTR_PT(95) + OR ROM64_INSTR_PT(98) OR ROM64_INSTR_PT(107) + OR ROM64_INSTR_PT(120) OR ROM64_INSTR_PT(123) + OR ROM64_INSTR_PT(130) OR ROM64_INSTR_PT(131) + OR ROM64_INSTR_PT(133) OR ROM64_INSTR_PT(135) + OR ROM64_INSTR_PT(138) OR ROM64_INSTR_PT(140) + OR ROM64_INSTR_PT(141) OR ROM64_INSTR_PT(151) + OR ROM64_INSTR_PT(152) OR ROM64_INSTR_PT(159) + OR ROM64_INSTR_PT(163) OR ROM64_INSTR_PT(164) + OR ROM64_INSTR_PT(167) OR ROM64_INSTR_PT(189) + OR ROM64_INSTR_PT(192) OR ROM64_INSTR_PT(220) + OR ROM64_INSTR_PT(227) OR ROM64_INSTR_PT(234) + OR ROM64_INSTR_PT(235) OR ROM64_INSTR_PT(250) + OR ROM64_INSTR_PT(253) OR ROM64_INSTR_PT(258) + OR ROM64_INSTR_PT(266) OR ROM64_INSTR_PT(267) + OR ROM64_INSTR_PT(279) OR ROM64_INSTR_PT(283) + OR ROM64_INSTR_PT(300) OR ROM64_INSTR_PT(301) + OR ROM64_INSTR_PT(303) OR ROM64_INSTR_PT(317) + OR ROM64_INSTR_PT(318) OR ROM64_INSTR_PT(328) + OR ROM64_INSTR_PT(330) OR ROM64_INSTR_PT(331) + OR ROM64_INSTR_PT(335) OR ROM64_INSTR_PT(337) + OR ROM64_INSTR_PT(338) OR ROM64_INSTR_PT(344) + OR ROM64_INSTR_PT(355) OR ROM64_INSTR_PT(356) + OR ROM64_INSTR_PT(384) OR ROM64_INSTR_PT(393) + OR ROM64_INSTR_PT(394) OR ROM64_INSTR_PT(398) + OR ROM64_INSTR_PT(418) OR ROM64_INSTR_PT(423) + OR ROM64_INSTR_PT(441) OR ROM64_INSTR_PT(447) + OR ROM64_INSTR_PT(449) OR ROM64_INSTR_PT(476) + OR ROM64_INSTR_PT(486) OR ROM64_INSTR_PT(487) + OR ROM64_INSTR_PT(496) OR ROM64_INSTR_PT(500) + OR ROM64_INSTR_PT(501) OR ROM64_INSTR_PT(526) + OR ROM64_INSTR_PT(547) OR ROM64_INSTR_PT(591) + OR ROM64_INSTR_PT(594) OR ROM64_INSTR_PT(597) + OR ROM64_INSTR_PT(624) OR ROM64_INSTR_PT(630) + OR ROM64_INSTR_PT(631) OR ROM64_INSTR_PT(640) + OR ROM64_INSTR_PT(651) OR ROM64_INSTR_PT(665) + OR ROM64_INSTR_PT(670) OR ROM64_INSTR_PT(671) + OR ROM64_INSTR_PT(672) OR ROM64_INSTR_PT(673) + OR ROM64_INSTR_PT(674) OR ROM64_INSTR_PT(688) + OR ROM64_INSTR_PT(696) OR ROM64_INSTR_PT(700) + OR ROM64_INSTR_PT(707) OR ROM64_INSTR_PT(712) + OR ROM64_INSTR_PT(727) OR ROM64_INSTR_PT(732) + OR ROM64_INSTR_PT(737) OR ROM64_INSTR_PT(743) + OR ROM64_INSTR_PT(744) OR ROM64_INSTR_PT(746) + OR ROM64_INSTR_PT(747) OR ROM64_INSTR_PT(750) + OR ROM64_INSTR_PT(755) OR ROM64_INSTR_PT(756) + OR ROM64_INSTR_PT(763) OR ROM64_INSTR_PT(764) + OR ROM64_INSTR_PT(767) OR ROM64_INSTR_PT(771) + OR ROM64_INSTR_PT(774) OR ROM64_INSTR_PT(776) + OR ROM64_INSTR_PT(777) OR ROM64_INSTR_PT(780) + OR ROM64_INSTR_PT(782) OR ROM64_INSTR_PT(783) + OR ROM64_INSTR_PT(784) OR ROM64_INSTR_PT(786) + OR ROM64_INSTR_PT(793) OR ROM64_INSTR_PT(795) + OR ROM64_INSTR_PT(798) OR ROM64_INSTR_PT(810) + OR ROM64_INSTR_PT(812) OR ROM64_INSTR_PT(820) + OR ROM64_INSTR_PT(821) OR ROM64_INSTR_PT(833) + OR ROM64_INSTR_PT(835) OR ROM64_INSTR_PT(837) + OR ROM64_INSTR_PT(838) OR ROM64_INSTR_PT(848) + OR ROM64_INSTR_PT(857) OR ROM64_INSTR_PT(859) + OR ROM64_INSTR_PT(860) OR ROM64_INSTR_PT(863) + OR ROM64_INSTR_PT(864) OR ROM64_INSTR_PT(865) + OR ROM64_INSTR_PT(866) OR ROM64_INSTR_PT(867) + OR ROM64_INSTR_PT(868) OR ROM64_INSTR_PT(871) + OR ROM64_INSTR_PT(877) OR ROM64_INSTR_PT(878) + OR ROM64_INSTR_PT(880)); +MQQ931:EXTS1 <= + (ROM64_INSTR_PT(4) OR ROM64_INSTR_PT(19) + OR ROM64_INSTR_PT(32) OR ROM64_INSTR_PT(34) + OR ROM64_INSTR_PT(47) OR ROM64_INSTR_PT(74) + OR ROM64_INSTR_PT(81) OR ROM64_INSTR_PT(91) + OR ROM64_INSTR_PT(94) OR ROM64_INSTR_PT(100) + OR ROM64_INSTR_PT(131) OR ROM64_INSTR_PT(137) + OR ROM64_INSTR_PT(138) OR ROM64_INSTR_PT(159) + OR ROM64_INSTR_PT(165) OR ROM64_INSTR_PT(167) + OR ROM64_INSTR_PT(193) OR ROM64_INSTR_PT(211) + OR ROM64_INSTR_PT(225) OR ROM64_INSTR_PT(227) + OR ROM64_INSTR_PT(232) OR ROM64_INSTR_PT(235) + OR ROM64_INSTR_PT(279) OR ROM64_INSTR_PT(289) + OR ROM64_INSTR_PT(291) OR ROM64_INSTR_PT(297) + OR ROM64_INSTR_PT(300) OR ROM64_INSTR_PT(301) + OR ROM64_INSTR_PT(317) OR ROM64_INSTR_PT(318) + OR ROM64_INSTR_PT(326) OR ROM64_INSTR_PT(328) + OR ROM64_INSTR_PT(330) OR ROM64_INSTR_PT(331) + OR ROM64_INSTR_PT(335) OR ROM64_INSTR_PT(337) + OR ROM64_INSTR_PT(338) OR ROM64_INSTR_PT(344) + OR ROM64_INSTR_PT(350) OR ROM64_INSTR_PT(358) + OR ROM64_INSTR_PT(373) OR ROM64_INSTR_PT(379) + OR ROM64_INSTR_PT(393) OR ROM64_INSTR_PT(398) + OR ROM64_INSTR_PT(400) OR ROM64_INSTR_PT(421) + OR ROM64_INSTR_PT(438) OR ROM64_INSTR_PT(446) + OR ROM64_INSTR_PT(449) OR ROM64_INSTR_PT(465) + OR ROM64_INSTR_PT(476) OR ROM64_INSTR_PT(479) + OR ROM64_INSTR_PT(486) OR ROM64_INSTR_PT(500) + OR ROM64_INSTR_PT(526) OR ROM64_INSTR_PT(543) + OR ROM64_INSTR_PT(566) OR ROM64_INSTR_PT(577) + OR ROM64_INSTR_PT(581) OR ROM64_INSTR_PT(593) + OR ROM64_INSTR_PT(594) OR ROM64_INSTR_PT(604) + OR ROM64_INSTR_PT(624) OR ROM64_INSTR_PT(630) + OR ROM64_INSTR_PT(631) OR ROM64_INSTR_PT(652) + OR ROM64_INSTR_PT(669) OR ROM64_INSTR_PT(671) + OR ROM64_INSTR_PT(672) OR ROM64_INSTR_PT(673) + OR ROM64_INSTR_PT(674) OR ROM64_INSTR_PT(688) + OR ROM64_INSTR_PT(692) OR ROM64_INSTR_PT(694) + OR ROM64_INSTR_PT(697) OR ROM64_INSTR_PT(700) + OR ROM64_INSTR_PT(707) OR ROM64_INSTR_PT(708) + OR ROM64_INSTR_PT(710) OR ROM64_INSTR_PT(712) + OR ROM64_INSTR_PT(715) OR ROM64_INSTR_PT(720) + OR ROM64_INSTR_PT(725) OR ROM64_INSTR_PT(732) + OR ROM64_INSTR_PT(737) OR ROM64_INSTR_PT(741) + OR ROM64_INSTR_PT(743) OR ROM64_INSTR_PT(746) + OR ROM64_INSTR_PT(747) OR ROM64_INSTR_PT(749) + OR ROM64_INSTR_PT(750) OR ROM64_INSTR_PT(755) + OR ROM64_INSTR_PT(758) OR ROM64_INSTR_PT(762) + OR ROM64_INSTR_PT(763) OR ROM64_INSTR_PT(764) + OR ROM64_INSTR_PT(767) OR ROM64_INSTR_PT(771) + OR ROM64_INSTR_PT(774) OR ROM64_INSTR_PT(777) + OR ROM64_INSTR_PT(778) OR ROM64_INSTR_PT(780) + OR ROM64_INSTR_PT(782) OR ROM64_INSTR_PT(783) + OR ROM64_INSTR_PT(784) OR ROM64_INSTR_PT(786) + OR ROM64_INSTR_PT(793) OR ROM64_INSTR_PT(795) + OR ROM64_INSTR_PT(796) OR ROM64_INSTR_PT(806) + OR ROM64_INSTR_PT(810) OR ROM64_INSTR_PT(812) + OR ROM64_INSTR_PT(817) OR ROM64_INSTR_PT(820) + OR ROM64_INSTR_PT(821) OR ROM64_INSTR_PT(823) + OR ROM64_INSTR_PT(828) OR ROM64_INSTR_PT(835) + OR ROM64_INSTR_PT(836) OR ROM64_INSTR_PT(837) + OR ROM64_INSTR_PT(838) OR ROM64_INSTR_PT(842) + OR ROM64_INSTR_PT(843) OR ROM64_INSTR_PT(844) + OR ROM64_INSTR_PT(847) OR ROM64_INSTR_PT(848) + OR ROM64_INSTR_PT(849) OR ROM64_INSTR_PT(851) + OR ROM64_INSTR_PT(853) OR ROM64_INSTR_PT(859) + OR ROM64_INSTR_PT(861) OR ROM64_INSTR_PT(865) + OR ROM64_INSTR_PT(866) OR ROM64_INSTR_PT(867) + OR ROM64_INSTR_PT(871) OR ROM64_INSTR_PT(877) + OR ROM64_INSTR_PT(880)); +MQQ932:EXTS2 <= + (ROM64_INSTR_PT(23) OR ROM64_INSTR_PT(27) + OR ROM64_INSTR_PT(44) OR ROM64_INSTR_PT(47) + OR ROM64_INSTR_PT(88) OR ROM64_INSTR_PT(91) + OR ROM64_INSTR_PT(131) OR ROM64_INSTR_PT(138) + OR ROM64_INSTR_PT(140) OR ROM64_INSTR_PT(152) + OR ROM64_INSTR_PT(167) OR ROM64_INSTR_PT(178) + OR ROM64_INSTR_PT(182) OR ROM64_INSTR_PT(189) + OR ROM64_INSTR_PT(211) OR ROM64_INSTR_PT(298) + OR ROM64_INSTR_PT(318) OR ROM64_INSTR_PT(330) + OR ROM64_INSTR_PT(331) OR ROM64_INSTR_PT(335) + OR ROM64_INSTR_PT(337) OR ROM64_INSTR_PT(344) + OR ROM64_INSTR_PT(346) OR ROM64_INSTR_PT(350) + OR ROM64_INSTR_PT(356) OR ROM64_INSTR_PT(358) + OR ROM64_INSTR_PT(373) OR ROM64_INSTR_PT(380) + OR ROM64_INSTR_PT(384) OR ROM64_INSTR_PT(394) + OR ROM64_INSTR_PT(400) OR ROM64_INSTR_PT(418) + OR ROM64_INSTR_PT(432) OR ROM64_INSTR_PT(441) + OR ROM64_INSTR_PT(479) OR ROM64_INSTR_PT(500) + OR ROM64_INSTR_PT(516) OR ROM64_INSTR_PT(526) + OR ROM64_INSTR_PT(530) OR ROM64_INSTR_PT(542) + OR ROM64_INSTR_PT(577) OR ROM64_INSTR_PT(580) + OR ROM64_INSTR_PT(581) OR ROM64_INSTR_PT(591) + OR ROM64_INSTR_PT(604) OR ROM64_INSTR_PT(627) + OR ROM64_INSTR_PT(631) OR ROM64_INSTR_PT(652) + OR ROM64_INSTR_PT(672) OR ROM64_INSTR_PT(674) + OR ROM64_INSTR_PT(696) OR ROM64_INSTR_PT(697) + OR ROM64_INSTR_PT(700) OR ROM64_INSTR_PT(707) + OR ROM64_INSTR_PT(715) OR ROM64_INSTR_PT(718) + OR ROM64_INSTR_PT(725) OR ROM64_INSTR_PT(737) + OR ROM64_INSTR_PT(743) OR ROM64_INSTR_PT(744) + OR ROM64_INSTR_PT(745) OR ROM64_INSTR_PT(746) + OR ROM64_INSTR_PT(750) OR ROM64_INSTR_PT(754) + OR ROM64_INSTR_PT(756) OR ROM64_INSTR_PT(758) + OR ROM64_INSTR_PT(763) OR ROM64_INSTR_PT(765) + OR ROM64_INSTR_PT(767) OR ROM64_INSTR_PT(771) + OR ROM64_INSTR_PT(772) OR ROM64_INSTR_PT(774) + OR ROM64_INSTR_PT(776) OR ROM64_INSTR_PT(778) + OR ROM64_INSTR_PT(784) OR ROM64_INSTR_PT(786) + OR ROM64_INSTR_PT(812) OR ROM64_INSTR_PT(813) + OR ROM64_INSTR_PT(820) OR ROM64_INSTR_PT(823) + OR ROM64_INSTR_PT(828) OR ROM64_INSTR_PT(842) + OR ROM64_INSTR_PT(843) OR ROM64_INSTR_PT(848) + OR ROM64_INSTR_PT(854) OR ROM64_INSTR_PT(859) + OR ROM64_INSTR_PT(860) OR ROM64_INSTR_PT(863) + OR ROM64_INSTR_PT(866) OR ROM64_INSTR_PT(867) + OR ROM64_INSTR_PT(868) OR ROM64_INSTR_PT(877) + OR ROM64_INSTR_PT(880)); +MQQ933:EXTS3 <= + (ROM64_INSTR_PT(47) OR ROM64_INSTR_PT(94) + OR ROM64_INSTR_PT(100) OR ROM64_INSTR_PT(135) + OR ROM64_INSTR_PT(159) OR ROM64_INSTR_PT(163) + OR ROM64_INSTR_PT(192) OR ROM64_INSTR_PT(225) + OR ROM64_INSTR_PT(235) OR ROM64_INSTR_PT(251) + OR ROM64_INSTR_PT(279) OR ROM64_INSTR_PT(297) + OR ROM64_INSTR_PT(300) OR ROM64_INSTR_PT(326) + OR ROM64_INSTR_PT(337) OR ROM64_INSTR_PT(338) + OR ROM64_INSTR_PT(350) OR ROM64_INSTR_PT(358) + OR ROM64_INSTR_PT(379) OR ROM64_INSTR_PT(384) + OR ROM64_INSTR_PT(398) OR ROM64_INSTR_PT(413) + OR ROM64_INSTR_PT(446) OR ROM64_INSTR_PT(447) + OR ROM64_INSTR_PT(524) OR ROM64_INSTR_PT(526) + OR ROM64_INSTR_PT(561) OR ROM64_INSTR_PT(572) + OR ROM64_INSTR_PT(594) OR ROM64_INSTR_PT(630) + OR ROM64_INSTR_PT(670) OR ROM64_INSTR_PT(692) + OR ROM64_INSTR_PT(697) OR ROM64_INSTR_PT(712) + OR ROM64_INSTR_PT(715) OR ROM64_INSTR_PT(749) + OR ROM64_INSTR_PT(758) OR ROM64_INSTR_PT(778) + OR ROM64_INSTR_PT(798) OR ROM64_INSTR_PT(833) + OR ROM64_INSTR_PT(837) OR ROM64_INSTR_PT(838) + OR ROM64_INSTR_PT(871)); +MQQ934:SEL0_5 <= + (ROM64_INSTR_PT(652) OR ROM64_INSTR_PT(718) + ); +MQQ935:SEL6_10(0) <= + (ROM64_INSTR_PT(40) OR ROM64_INSTR_PT(69) + OR ROM64_INSTR_PT(82) OR ROM64_INSTR_PT(95) + OR ROM64_INSTR_PT(107) OR ROM64_INSTR_PT(200) + OR ROM64_INSTR_PT(211) OR ROM64_INSTR_PT(267) + OR ROM64_INSTR_PT(386) OR ROM64_INSTR_PT(443) + OR ROM64_INSTR_PT(444) OR ROM64_INSTR_PT(452) + OR ROM64_INSTR_PT(516) OR ROM64_INSTR_PT(528) + OR ROM64_INSTR_PT(529) OR ROM64_INSTR_PT(537) + OR ROM64_INSTR_PT(542) OR ROM64_INSTR_PT(550) + OR ROM64_INSTR_PT(560) OR ROM64_INSTR_PT(566) + OR ROM64_INSTR_PT(573) OR ROM64_INSTR_PT(581) + OR ROM64_INSTR_PT(604) OR ROM64_INSTR_PT(607) + OR ROM64_INSTR_PT(621) OR ROM64_INSTR_PT(661) + OR ROM64_INSTR_PT(698) OR ROM64_INSTR_PT(706) + OR ROM64_INSTR_PT(790) OR ROM64_INSTR_PT(823) + OR ROM64_INSTR_PT(854)); +MQQ936:SEL6_10(1) <= + (ROM64_INSTR_PT(1) OR ROM64_INSTR_PT(3) + OR ROM64_INSTR_PT(40) OR ROM64_INSTR_PT(54) + OR ROM64_INSTR_PT(67) OR ROM64_INSTR_PT(69) + OR ROM64_INSTR_PT(78) OR ROM64_INSTR_PT(82) + OR ROM64_INSTR_PT(95) OR ROM64_INSTR_PT(107) + OR ROM64_INSTR_PT(120) OR ROM64_INSTR_PT(182) + OR ROM64_INSTR_PT(188) OR ROM64_INSTR_PT(256) + OR ROM64_INSTR_PT(267) OR ROM64_INSTR_PT(287) + OR ROM64_INSTR_PT(336) OR ROM64_INSTR_PT(346) + OR ROM64_INSTR_PT(350) OR ROM64_INSTR_PT(354) + OR ROM64_INSTR_PT(358) OR ROM64_INSTR_PT(380) + OR ROM64_INSTR_PT(407) OR ROM64_INSTR_PT(431) + OR ROM64_INSTR_PT(436) OR ROM64_INSTR_PT(459) + OR ROM64_INSTR_PT(463) OR ROM64_INSTR_PT(487) + OR ROM64_INSTR_PT(529) OR ROM64_INSTR_PT(530) + OR ROM64_INSTR_PT(540) OR ROM64_INSTR_PT(580) + OR ROM64_INSTR_PT(605) OR ROM64_INSTR_PT(640) + OR ROM64_INSTR_PT(652) OR ROM64_INSTR_PT(658) + OR ROM64_INSTR_PT(694) OR ROM64_INSTR_PT(697) + OR ROM64_INSTR_PT(708) OR ROM64_INSTR_PT(715) + OR ROM64_INSTR_PT(718) OR ROM64_INSTR_PT(720) + OR ROM64_INSTR_PT(726) OR ROM64_INSTR_PT(727) + OR ROM64_INSTR_PT(740) OR ROM64_INSTR_PT(769) + OR ROM64_INSTR_PT(857) OR ROM64_INSTR_PT(864) + ); +MQQ937:SEL11_15(0) <= + (ROM64_INSTR_PT(37) OR ROM64_INSTR_PT(135) + OR ROM64_INSTR_PT(193) OR ROM64_INSTR_PT(232) + OR ROM64_INSTR_PT(248) OR ROM64_INSTR_PT(291) + OR ROM64_INSTR_PT(373) OR ROM64_INSTR_PT(384) + OR ROM64_INSTR_PT(438) OR ROM64_INSTR_PT(447) + OR ROM64_INSTR_PT(465) OR ROM64_INSTR_PT(593) + OR ROM64_INSTR_PT(663) OR ROM64_INSTR_PT(741) + OR ROM64_INSTR_PT(798) OR ROM64_INSTR_PT(829) + ); +MQQ938:SEL11_15(1) <= + (ROM64_INSTR_PT(24) OR ROM64_INSTR_PT(27) + OR ROM64_INSTR_PT(37) OR ROM64_INSTR_PT(44) + OR ROM64_INSTR_PT(48) OR ROM64_INSTR_PT(59) + OR ROM64_INSTR_PT(62) OR ROM64_INSTR_PT(63) + OR ROM64_INSTR_PT(85) OR ROM64_INSTR_PT(98) + OR ROM64_INSTR_PT(105) OR ROM64_INSTR_PT(115) + OR ROM64_INSTR_PT(123) OR ROM64_INSTR_PT(130) + OR ROM64_INSTR_PT(133) OR ROM64_INSTR_PT(140) + OR ROM64_INSTR_PT(141) OR ROM64_INSTR_PT(151) + OR ROM64_INSTR_PT(164) OR ROM64_INSTR_PT(189) + OR ROM64_INSTR_PT(192) OR ROM64_INSTR_PT(193) + OR ROM64_INSTR_PT(200) OR ROM64_INSTR_PT(220) + OR ROM64_INSTR_PT(232) OR ROM64_INSTR_PT(234) + OR ROM64_INSTR_PT(250) OR ROM64_INSTR_PT(253) + OR ROM64_INSTR_PT(266) OR ROM64_INSTR_PT(283) + OR ROM64_INSTR_PT(291) OR ROM64_INSTR_PT(303) + OR ROM64_INSTR_PT(323) OR ROM64_INSTR_PT(354) + OR ROM64_INSTR_PT(356) OR ROM64_INSTR_PT(373) + OR ROM64_INSTR_PT(386) OR ROM64_INSTR_PT(394) + OR ROM64_INSTR_PT(418) OR ROM64_INSTR_PT(423) + OR ROM64_INSTR_PT(432) OR ROM64_INSTR_PT(438) + OR ROM64_INSTR_PT(441) OR ROM64_INSTR_PT(444) + OR ROM64_INSTR_PT(452) OR ROM64_INSTR_PT(465) + OR ROM64_INSTR_PT(492) OR ROM64_INSTR_PT(516) + OR ROM64_INSTR_PT(524) OR ROM64_INSTR_PT(528) + OR ROM64_INSTR_PT(547) OR ROM64_INSTR_PT(550) + OR ROM64_INSTR_PT(560) OR ROM64_INSTR_PT(573) + OR ROM64_INSTR_PT(577) OR ROM64_INSTR_PT(591) + OR ROM64_INSTR_PT(593) OR ROM64_INSTR_PT(597) + OR ROM64_INSTR_PT(607) OR ROM64_INSTR_PT(621) + OR ROM64_INSTR_PT(627) OR ROM64_INSTR_PT(634) + OR ROM64_INSTR_PT(665) OR ROM64_INSTR_PT(698) + OR ROM64_INSTR_PT(706) OR ROM64_INSTR_PT(717) + OR ROM64_INSTR_PT(718) OR ROM64_INSTR_PT(734) + OR ROM64_INSTR_PT(790) OR ROM64_INSTR_PT(806) + OR ROM64_INSTR_PT(813) OR ROM64_INSTR_PT(824) + OR ROM64_INSTR_PT(828) OR ROM64_INSTR_PT(840) + OR ROM64_INSTR_PT(844) OR ROM64_INSTR_PT(849) + ); +MQQ939:SEL16_20(0) <= + (ROM64_INSTR_PT(6) OR ROM64_INSTR_PT(135) + OR ROM64_INSTR_PT(194) OR ROM64_INSTR_PT(258) + OR ROM64_INSTR_PT(260) OR ROM64_INSTR_PT(355) + OR ROM64_INSTR_PT(447) OR ROM64_INSTR_PT(533) + OR ROM64_INSTR_PT(798) OR ROM64_INSTR_PT(829) + ); +MQQ940:SEL16_20(1) <= + (ROM64_INSTR_PT(4) OR ROM64_INSTR_PT(12) + OR ROM64_INSTR_PT(16) OR ROM64_INSTR_PT(40) + OR ROM64_INSTR_PT(46) OR ROM64_INSTR_PT(48) + OR ROM64_INSTR_PT(69) OR ROM64_INSTR_PT(74) + OR ROM64_INSTR_PT(82) OR ROM64_INSTR_PT(87) + OR ROM64_INSTR_PT(95) OR ROM64_INSTR_PT(100) + OR ROM64_INSTR_PT(107) OR ROM64_INSTR_PT(126) + OR ROM64_INSTR_PT(133) OR ROM64_INSTR_PT(135) + OR ROM64_INSTR_PT(137) OR ROM64_INSTR_PT(141) + OR ROM64_INSTR_PT(159) OR ROM64_INSTR_PT(164) + OR ROM64_INSTR_PT(200) OR ROM64_INSTR_PT(204) + OR ROM64_INSTR_PT(225) OR ROM64_INSTR_PT(251) + OR ROM64_INSTR_PT(266) OR ROM64_INSTR_PT(267) + OR ROM64_INSTR_PT(279) OR ROM64_INSTR_PT(297) + OR ROM64_INSTR_PT(300) OR ROM64_INSTR_PT(319) + OR ROM64_INSTR_PT(321) OR ROM64_INSTR_PT(336) + OR ROM64_INSTR_PT(354) OR ROM64_INSTR_PT(355) + OR ROM64_INSTR_PT(362) OR ROM64_INSTR_PT(379) + OR ROM64_INSTR_PT(398) OR ROM64_INSTR_PT(413) + OR ROM64_INSTR_PT(423) OR ROM64_INSTR_PT(444) + OR ROM64_INSTR_PT(446) OR ROM64_INSTR_PT(447) + OR ROM64_INSTR_PT(452) OR ROM64_INSTR_PT(470) + OR ROM64_INSTR_PT(496) OR ROM64_INSTR_PT(513) + OR ROM64_INSTR_PT(524) OR ROM64_INSTR_PT(528) + OR ROM64_INSTR_PT(529) OR ROM64_INSTR_PT(541) + OR ROM64_INSTR_PT(550) OR ROM64_INSTR_PT(560) + OR ROM64_INSTR_PT(561) OR ROM64_INSTR_PT(566) + OR ROM64_INSTR_PT(572) OR ROM64_INSTR_PT(573) + OR ROM64_INSTR_PT(606) OR ROM64_INSTR_PT(607) + OR ROM64_INSTR_PT(615) OR ROM64_INSTR_PT(621) + OR ROM64_INSTR_PT(634) OR ROM64_INSTR_PT(648) + OR ROM64_INSTR_PT(661) OR ROM64_INSTR_PT(698) + OR ROM64_INSTR_PT(706) OR ROM64_INSTR_PT(717) + OR ROM64_INSTR_PT(729) OR ROM64_INSTR_PT(773) + OR ROM64_INSTR_PT(790) OR ROM64_INSTR_PT(798) + OR ROM64_INSTR_PT(829) OR ROM64_INSTR_PT(838) + ); +MQQ941:SEL21_25(0) <= + (ROM64_INSTR_PT(197)); +MQQ942:SEL21_25(1) <= + (ROM64_INSTR_PT(16) OR ROM64_INSTR_PT(46) + OR ROM64_INSTR_PT(48) OR ROM64_INSTR_PT(63) + OR ROM64_INSTR_PT(74) OR ROM64_INSTR_PT(87) + OR ROM64_INSTR_PT(141) OR ROM64_INSTR_PT(200) + OR ROM64_INSTR_PT(225) OR ROM64_INSTR_PT(266) + OR ROM64_INSTR_PT(321) OR ROM64_INSTR_PT(354) + OR ROM64_INSTR_PT(362) OR ROM64_INSTR_PT(423) + OR ROM64_INSTR_PT(452) OR ROM64_INSTR_PT(470) + OR ROM64_INSTR_PT(515) OR ROM64_INSTR_PT(528) + OR ROM64_INSTR_PT(541) OR ROM64_INSTR_PT(550) + OR ROM64_INSTR_PT(560) OR ROM64_INSTR_PT(572) + OR ROM64_INSTR_PT(573) OR ROM64_INSTR_PT(634) + OR ROM64_INSTR_PT(652) OR ROM64_INSTR_PT(706) + OR ROM64_INSTR_PT(718) OR ROM64_INSTR_PT(729) + OR ROM64_INSTR_PT(734) OR ROM64_INSTR_PT(790) + ); +MQQ943:SEL26_30 <= + (ROM64_INSTR_PT(16) OR ROM64_INSTR_PT(46) + OR ROM64_INSTR_PT(48) OR ROM64_INSTR_PT(63) + OR ROM64_INSTR_PT(74) OR ROM64_INSTR_PT(87) + OR ROM64_INSTR_PT(141) OR ROM64_INSTR_PT(200) + OR ROM64_INSTR_PT(225) OR ROM64_INSTR_PT(266) + OR ROM64_INSTR_PT(321) OR ROM64_INSTR_PT(354) + OR ROM64_INSTR_PT(362) OR ROM64_INSTR_PT(423) + OR ROM64_INSTR_PT(452) OR ROM64_INSTR_PT(470) + OR ROM64_INSTR_PT(515) OR ROM64_INSTR_PT(528) + OR ROM64_INSTR_PT(541) OR ROM64_INSTR_PT(550) + OR ROM64_INSTR_PT(560) OR ROM64_INSTR_PT(572) + OR ROM64_INSTR_PT(573) OR ROM64_INSTR_PT(634) + OR ROM64_INSTR_PT(652) OR ROM64_INSTR_PT(706) + OR ROM64_INSTR_PT(718) OR ROM64_INSTR_PT(729) + OR ROM64_INSTR_PT(734) OR ROM64_INSTR_PT(790) + ); +MQQ944:SEL31 <= + (ROM64_INSTR_PT(16) OR ROM64_INSTR_PT(46) + OR ROM64_INSTR_PT(63) OR ROM64_INSTR_PT(74) + OR ROM64_INSTR_PT(87) OR ROM64_INSTR_PT(141) + OR ROM64_INSTR_PT(200) OR ROM64_INSTR_PT(266) + OR ROM64_INSTR_PT(321) OR ROM64_INSTR_PT(350) + OR ROM64_INSTR_PT(354) OR ROM64_INSTR_PT(358) + OR ROM64_INSTR_PT(362) OR ROM64_INSTR_PT(423) + OR ROM64_INSTR_PT(452) OR ROM64_INSTR_PT(470) + OR ROM64_INSTR_PT(541) OR ROM64_INSTR_PT(542) + OR ROM64_INSTR_PT(560) OR ROM64_INSTR_PT(561) + OR ROM64_INSTR_PT(573) OR ROM64_INSTR_PT(634) + OR ROM64_INSTR_PT(652) OR ROM64_INSTR_PT(697) + OR ROM64_INSTR_PT(706) OR ROM64_INSTR_PT(715) + OR ROM64_INSTR_PT(718) OR ROM64_INSTR_PT(729) + OR ROM64_INSTR_PT(790) OR ROM64_INSTR_PT(823) + ); +MQQ945:CR_BF2FXM <= + (ROM64_INSTR_PT(717)); +MQQ946:SKIP_COND <= + (ROM64_INSTR_PT(23) OR ROM64_INSTR_PT(34) + OR ROM64_INSTR_PT(81) OR ROM64_INSTR_PT(88) + OR ROM64_INSTR_PT(91) OR ROM64_INSTR_PT(127) + OR ROM64_INSTR_PT(298) OR ROM64_INSTR_PT(330) + OR ROM64_INSTR_PT(331) OR ROM64_INSTR_PT(335) + OR ROM64_INSTR_PT(344) OR ROM64_INSTR_PT(369) + OR ROM64_INSTR_PT(489) OR ROM64_INSTR_PT(662) + OR ROM64_INSTR_PT(667) OR ROM64_INSTR_PT(677) + OR ROM64_INSTR_PT(684) OR ROM64_INSTR_PT(725) + OR ROM64_INSTR_PT(744) OR ROM64_INSTR_PT(745) + OR ROM64_INSTR_PT(746) OR ROM64_INSTR_PT(747) + OR ROM64_INSTR_PT(748) OR ROM64_INSTR_PT(750) + OR ROM64_INSTR_PT(754) OR ROM64_INSTR_PT(755) + OR ROM64_INSTR_PT(756) OR ROM64_INSTR_PT(765) + OR ROM64_INSTR_PT(776) OR ROM64_INSTR_PT(782) + OR ROM64_INSTR_PT(783) OR ROM64_INSTR_PT(784) + OR ROM64_INSTR_PT(792) OR ROM64_INSTR_PT(795) + OR ROM64_INSTR_PT(796) OR ROM64_INSTR_PT(804) + OR ROM64_INSTR_PT(817) OR ROM64_INSTR_PT(819) + OR ROM64_INSTR_PT(820) OR ROM64_INSTR_PT(821) + OR ROM64_INSTR_PT(827) OR ROM64_INSTR_PT(842) + OR ROM64_INSTR_PT(859) OR ROM64_INSTR_PT(867) + ); +MQQ947:SKIP_ZERO <= + (ROM64_INSTR_PT(301) OR ROM64_INSTR_PT(319) + OR ROM64_INSTR_PT(393) OR ROM64_INSTR_PT(436) + OR ROM64_INSTR_PT(487) OR ROM64_INSTR_PT(496) + OR ROM64_INSTR_PT(778)); +MQQ948:LOOP_ADDR(0) <= + (ROM64_INSTR_PT(235) OR ROM64_INSTR_PT(289) + OR ROM64_INSTR_PT(301) OR ROM64_INSTR_PT(317) + OR ROM64_INSTR_PT(328) OR ROM64_INSTR_PT(373) + OR ROM64_INSTR_PT(479) OR ROM64_INSTR_PT(526) + OR ROM64_INSTR_PT(674) OR ROM64_INSTR_PT(692) + OR ROM64_INSTR_PT(700) OR ROM64_INSTR_PT(732) + OR ROM64_INSTR_PT(743) OR ROM64_INSTR_PT(777) + OR ROM64_INSTR_PT(778) OR ROM64_INSTR_PT(784) + OR ROM64_INSTR_PT(837) OR ROM64_INSTR_PT(861) + OR ROM64_INSTR_PT(866) OR ROM64_INSTR_PT(867) + ); +MQQ949:LOOP_ADDR(1) <= + (ROM64_INSTR_PT(289) OR ROM64_INSTR_PT(479) + OR ROM64_INSTR_PT(526) OR ROM64_INSTR_PT(674) + OR ROM64_INSTR_PT(732) OR ROM64_INSTR_PT(777) + OR ROM64_INSTR_PT(784) OR ROM64_INSTR_PT(833) + OR ROM64_INSTR_PT(837) OR ROM64_INSTR_PT(859) + OR ROM64_INSTR_PT(867)); +MQQ950:LOOP_ADDR(2) <= + (ROM64_INSTR_PT(393) OR ROM64_INSTR_PT(449) + OR ROM64_INSTR_PT(486) OR ROM64_INSTR_PT(700) + OR ROM64_INSTR_PT(743) OR ROM64_INSTR_PT(748) + OR ROM64_INSTR_PT(754) OR ROM64_INSTR_PT(764) + ); +MQQ951:LOOP_ADDR(3) <= + (ROM64_INSTR_PT(317) OR ROM64_INSTR_PT(328) + OR ROM64_INSTR_PT(501) OR ROM64_INSTR_PT(672) + OR ROM64_INSTR_PT(688) OR ROM64_INSTR_PT(700) + OR ROM64_INSTR_PT(707) OR ROM64_INSTR_PT(725) + OR ROM64_INSTR_PT(743) OR ROM64_INSTR_PT(765) + OR ROM64_INSTR_PT(767) OR ROM64_INSTR_PT(777) + OR ROM64_INSTR_PT(836) OR ROM64_INSTR_PT(837) + OR ROM64_INSTR_PT(859) OR ROM64_INSTR_PT(867) + OR ROM64_INSTR_PT(878)); +MQQ952:LOOP_ADDR(4) <= + (ROM64_INSTR_PT(37) OR ROM64_INSTR_PT(289) + OR ROM64_INSTR_PT(301) OR ROM64_INSTR_PT(328) + OR ROM64_INSTR_PT(373) OR ROM64_INSTR_PT(400) + OR ROM64_INSTR_PT(421) OR ROM64_INSTR_PT(449) + OR ROM64_INSTR_PT(479) OR ROM64_INSTR_PT(700) + OR ROM64_INSTR_PT(743) OR ROM64_INSTR_PT(748) + OR ROM64_INSTR_PT(750) OR ROM64_INSTR_PT(754) + OR ROM64_INSTR_PT(762) OR ROM64_INSTR_PT(784) + OR ROM64_INSTR_PT(837) OR ROM64_INSTR_PT(866) + OR ROM64_INSTR_PT(867)); +MQQ953:LOOP_ADDR(5) <= + (ROM64_INSTR_PT(37) OR ROM64_INSTR_PT(235) + OR ROM64_INSTR_PT(289) OR ROM64_INSTR_PT(421) + OR ROM64_INSTR_PT(449) OR ROM64_INSTR_PT(526) + OR ROM64_INSTR_PT(688) OR ROM64_INSTR_PT(725) + OR ROM64_INSTR_PT(743) OR ROM64_INSTR_PT(764) + OR ROM64_INSTR_PT(772) OR ROM64_INSTR_PT(861) + OR ROM64_INSTR_PT(866)); +MQQ954:LOOP_ADDR(6) <= + (ROM64_INSTR_PT(37) OR ROM64_INSTR_PT(163) + OR ROM64_INSTR_PT(289) OR ROM64_INSTR_PT(317) + OR ROM64_INSTR_PT(373) OR ROM64_INSTR_PT(486) + OR ROM64_INSTR_PT(672) OR ROM64_INSTR_PT(696) + OR ROM64_INSTR_PT(700) OR ROM64_INSTR_PT(748) + OR ROM64_INSTR_PT(750) OR ROM64_INSTR_PT(764) + OR ROM64_INSTR_PT(767) OR ROM64_INSTR_PT(833) + OR ROM64_INSTR_PT(837) OR ROM64_INSTR_PT(859) + OR ROM64_INSTR_PT(861) OR ROM64_INSTR_PT(868) + ); +MQQ955:LOOP_ADDR(7) <= + (ROM64_INSTR_PT(37) OR ROM64_INSTR_PT(289) + OR ROM64_INSTR_PT(301) OR ROM64_INSTR_PT(317) + OR ROM64_INSTR_PT(328) OR ROM64_INSTR_PT(400) + OR ROM64_INSTR_PT(421) OR ROM64_INSTR_PT(486) + OR ROM64_INSTR_PT(651) OR ROM64_INSTR_PT(672) + OR ROM64_INSTR_PT(674) OR ROM64_INSTR_PT(692) + OR ROM64_INSTR_PT(725) OR ROM64_INSTR_PT(732) + OR ROM64_INSTR_PT(743) OR ROM64_INSTR_PT(748) + OR ROM64_INSTR_PT(777) OR ROM64_INSTR_PT(861) + OR ROM64_INSTR_PT(867)); +MQQ956:LOOP_ADDR(8) <= + (ROM64_INSTR_PT(400) OR ROM64_INSTR_PT(421) + OR ROM64_INSTR_PT(449) OR ROM64_INSTR_PT(479) + OR ROM64_INSTR_PT(486) OR ROM64_INSTR_PT(672) + OR ROM64_INSTR_PT(696) OR ROM64_INSTR_PT(700) + OR ROM64_INSTR_PT(707) OR ROM64_INSTR_PT(725) + OR ROM64_INSTR_PT(748) OR ROM64_INSTR_PT(750) + OR ROM64_INSTR_PT(754) OR ROM64_INSTR_PT(762) + OR ROM64_INSTR_PT(764) OR ROM64_INSTR_PT(777) + OR ROM64_INSTR_PT(861) OR ROM64_INSTR_PT(866) + ); +MQQ957:LOOP_ADDR(9) <= + (ROM64_INSTR_PT(301) OR ROM64_INSTR_PT(317) + OR ROM64_INSTR_PT(328) OR ROM64_INSTR_PT(373) + OR ROM64_INSTR_PT(393) OR ROM64_INSTR_PT(449) + OR ROM64_INSTR_PT(486) OR ROM64_INSTR_PT(692) + OR ROM64_INSTR_PT(743) OR ROM64_INSTR_PT(764) + OR ROM64_INSTR_PT(772) OR ROM64_INSTR_PT(778) + OR ROM64_INSTR_PT(784) OR ROM64_INSTR_PT(836) + OR ROM64_INSTR_PT(837) OR ROM64_INSTR_PT(861) + ); +MQQ958:LOOP_INIT(0) <= + (ROM64_INSTR_PT(235) OR ROM64_INSTR_PT(369) + OR ROM64_INSTR_PT(398) OR ROM64_INSTR_PT(572) + OR ROM64_INSTR_PT(673) OR ROM64_INSTR_PT(692) + OR ROM64_INSTR_PT(783) OR ROM64_INSTR_PT(795) + OR ROM64_INSTR_PT(810) OR ROM64_INSTR_PT(817) + OR ROM64_INSTR_PT(821) OR ROM64_INSTR_PT(837) + OR ROM64_INSTR_PT(859) OR ROM64_INSTR_PT(867) + ); +MQQ959:LOOP_INIT(1) <= + (ROM64_INSTR_PT(890)); +MQQ960:LOOP_INIT(2) <= + (ROM64_INSTR_PT(783) OR ROM64_INSTR_PT(817) + OR ROM64_INSTR_PT(859) OR ROM64_INSTR_PT(867) + ); +MQQ961:EP <= + (ROM64_INSTR_PT(44) OR ROM64_INSTR_PT(59) + OR ROM64_INSTR_PT(115) OR ROM64_INSTR_PT(137) + OR ROM64_INSTR_PT(279) OR ROM64_INSTR_PT(297) + OR ROM64_INSTR_PT(356) OR ROM64_INSTR_PT(394) + OR ROM64_INSTR_PT(398) OR ROM64_INSTR_PT(432) + OR ROM64_INSTR_PT(441) OR ROM64_INSTR_PT(446) + OR ROM64_INSTR_PT(524) OR ROM64_INSTR_PT(561) + ); + +end generate; +--32-bit core +c32: if (regmode = 5) generate +begin + +ROM64_INSTR_PT <= (others => '0'); +rom_unused <= or_reduce(ROM64_INSTR_PT); +-- +-- Final Table Listing +-- *INPUTS*========*OUTPUTS*===============================================================================================* +-- | | | +-- | rom_addr_l2 | template ucode_end | +-- | | | | | ucode_end_early | +-- | | | | | | loop_begin | +-- | | | | | | | loop_end | +-- | | | | | | | | count_src | -- Can DC if not (loop_begin or loop_end) +-- | | | | | | | | | | +-- | | | | | | | | | extRT | +-- | | | | | | | | | | extS1 | +-- | | | | | | | | | | | extS2 | +-- | | | | | | | | | | | | extS3 | +-- | | | | | | | | | | | | | | +-- | | | | | | | | | | | | | sel0_5 | +-- | | | | | | | | | | | | | | sel6_10 | +-- | | | | | | | | | | | | | | | sel11_15 | +-- | | | | | | | | | | | | | | | | sel16_20 | +-- | | | | | | | | | | | | | | | | | sel21_25 | +-- | | | | | | | | | | | | | | | | | | sel26_30 | +-- | | | | | | | | | | | | | | | | | | | sel31 | +-- | | | | | | | | | | | | | | | | | | | | | +-- | | | | | | | | | | | | | | | | | | | | cr_bf2fxm | +-- | | | | | | | | | | | | | | | | | | | | | skip_cond | +-- | | | | | | | | | | | | | | | | | | | | | | skip_zero | -- Can DC if loop_begin not set +-- | | | | | | | | | | | | | | | | | | | | | | | loop_addr | -- Can DC if loop_end not set +-- | | | | | | | | | | | | | | | | | | | | | | | | loop_init | -- 1 less than # of times to loop; Can DC if not loop_end or not count_src=111 +-- | | | | | | | | | | | | | | | | | | | | | | | | | ep | +-- | | | | 1111111111222222222233 | | | | | | | | | | | | | | | | | | | | | | | +-- | 0123456789 | 01234567890123456789012345678901 | | | | 012 | | | | | 01 01 01 01 | | | | | 0123456789 012 | | +-- *TYPE*==========+=======================================================================================================+ +-- | PPPPPPPPPP | SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS S S S S SSS S S S S S SS SS SS SS S S S S S SSSSSSSSSS SSS S | +-- *POLARITY*----->| ++++++++++++++++++++++++++++++++ + + + + +++ + + + + + ++ ++ ++ ++ + + + + + ++++++++++ +++ + | +-- *PHASE*-------->| TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT T T T T TTT T T T T T TT TT TT TT T T T T T TTTTTTTTTT TTT T | +-- *OPTIMIZE*----->| AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA B B B B CCC X X X X X XX XX XX XX X X X X X XXXXXXXXXX XYX X | +-- *TERMS*=========+=======================================================================================================+ +-- 1 | -100000000 | ................................ . . . . ... . . . . . .1 .. .. .. . . . . . .......... ... . | +-- 2 | 0-11000000 | ................................ . . . . ... . . . . . .1 .. .. .. . . . . . .......... ... . | +-- 3 | 10-1000000 | .1...1....1.............1.1.111. . . . . ... 1 1 . . . .. .. .1 .. . . . . . .......... ... . | +-- 4 | 000-000000 | ..111...........111111111111111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 5 | 110-000000 | .11111....1..........1.1111111.. . . . . ... . . . . . .. .. 1. .. . . . . . .......... ... . | +-- 6 | 011-000000 | .11111...11...1...........11.11. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 7 | -0-0100000 | .11111................1....1.1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 8 | 0001100000 | .1.1.....1.....1.....11...11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 9 | 01-1100000 | .1.1.1..........1....1....11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 10 | -01-100000 | .1.1.1...1....1......11.1.11.1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 11 | -000-00000 | ................................ . . . . ... . . . . . .. .. .1 .. . . . . . .......... ... . | +-- 12 | 11-0-00000 | .....1...1....1.....1.11.1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 13 | 0001010000 | .11111....1.............1.1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 14 | 0-11010000 | .11111...11...11...1..1....1.1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 15 | 10-1010000 | ................................ . . . . ... . . . . . .. .. .1 .1 1 1 . . . .......... ... . | +-- 16 | 0-00110000 | .1.1......1...1.11..........111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 17 | -1-0110000 | .1.1.....1.....1.....11...11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 18 | 0-11110000 | ..111.....1.....1111............ . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 19 | 10--110000 | ................................ . . . . ... 1 1 . . . .. .. .. .. . . . . . 1..11..1.1 ... . | +-- 20 | 01--110000 | .1.1.1........1.1111111..111..1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 21 | 0000-10000 | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . 1 . .......... ... . | +-- 22 | 1101-10000 | ................................ . . . . ... . . . . . .. .1 .. .. . . . . . .......... ... . | +-- 23 | 011--10000 | .1111....1....1....1.111.11..1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 24 | 11-00-0000 | ................................ . . 1 . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 25 | 00010-0000 | ................................ . . . . ... 1 . 1 . . .. .1 .. .. . . . . . .......... ... . | +-- 26 | 01001-0000 | .1.1.1........111111....1.11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 27 | 10-01-0000 | ..111........................1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 28 | 11011-0000 | 1..11....1...................... . . . . ... . 1 . . . .. .. .1 .1 1 1 . . . .......... ... . | +-- 29 | 011-1-0000 | ..1.1.................1.1.1..... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 30 | 1-1-1-0000 | .............................1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 31 | 1001--0000 | ..111..........................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 32 | 101---0000 | .1.1......1...1.11..........1.1. . . . . ... . . . . . .. .. .. .. . . . 1 . .......... ... . | +-- 33 | 111---0000 | 1..111..............1.....11.... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 34 | 0-00001000 | ..............111111....1....... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 35 | --10001000 | .1111....1....1.....1111111..... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 36 | 10-1001000 | ................................ . . . . ... . 1 1 . . .. 11 .. .. . . . . . 1...1111.1 ... . | +-- 37 | 110-001000 | .1.1.1...1....1..1........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 38 | -01-001000 | ..111.....1.....11111111........ . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 39 | -100101000 | .11111.............1......111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 40 | 11-0101000 | ................................ . . . . ... 1 . . . . 11 .. .1 .. . . . . . .......... ... . | +-- 41 | 0001101000 | .11111....1.............1.1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 42 | 0-11101000 | .11111...11...1....11....1.1.... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 43 | 01-1101000 | .1111............1...11...1..... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 44 | 000-101000 | ................................ . . . . ... 1 . 1 . . .. .1 .. .. . . . . . .......... ... 1 | +-- 45 | 111-101000 | 1..111...11........11...1.111.1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 46 | 0000-01000 | ................................ . . . . ... . . . . . .. .. .1 .1 1 . . . . .......... ... . | +-- 47 | -11--01000 | ................................ . . . . ... 1 1 1 1 . .. .. .. .. . . . . . .......... ... . | +-- 48 | 0001011000 | ................................ . . . . ... . . . . . .. .1 .1 .1 1 . . . . .......... ... . | +-- 49 | 0-11011000 | .1.1.1..........11111.....11.11. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 50 | 01-1011000 | .1........................1...1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 51 | 00-0111000 | .1...1....1.............1.1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 52 | 110-111000 | .1.1.1....1...1...........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 53 | 0-1-111000 | .11111...11...11...1..1....1.1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 54 | 0100-11000 | ................................ . . . . ... . . . . . .1 .. .. .. . . . . . .......... ... . | +-- 55 | 1101-11000 | .1.......1....1.11............1. . . 1 . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 56 | 101--11000 | .11111...1....1.....1.11.1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 57 | 011--11000 | .11111....1....1...1..11.1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 58 | --1--11000 | ................................ . . . . ... . 1 . 1 . .. .. .. .. . . . . . 1.1111.1.1 ... . | +-- 59 | 01000-1000 | .1.1.1....................11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 60 | -0100-1000 | .........1...........1....1..... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 61 | 00001-1000 | ................................ . . . . ... . . . . . .. .1 .. .. . 1 . . . .......... ... 1 | +-- 62 | 00-01-1000 | ..111..........................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 63 | 10011-1000 | .1.1.1...1....1..1........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 64 | 11011-1000 | ................................ . . . . ... . . . . . .. .1 .. .. . . . . . .......... ... . | +-- 65 | 000000-000 | ................................ . . . . ... . . . . . .. .1 .. .1 1 1 . . . .......... ... . | +-- 66 | -10000-000 | .1.1.1....................11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 67 | -01000-000 | .1.1.1........1.1...........111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 68 | 10-000-000 | 1...1........................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 69 | 10-010-000 | ................................ . . . . ... 1 . . . . .. .1 .. .. . . . . . .......... ... . | +-- 70 | 1--010-000 | ..111........................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 71 | 01-110-000 | ................................ . . . . ... . . . . . .1 .. .. .. . . . . . .......... ... . | +-- 72 | 101--0-000 | .11111....................111... . . . . ... 1 . . . . 11 .. .1 .. . . . . . .......... ... . | +-- 73 | 000001-000 | .1.1.1...1....1..1...1....1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 74 | 0-1011-000 | .1.1.....1.....1.....11...11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 75 | -------000 | ................................ . . . . 1.. . . . . . .. .. .. .. . . . . . .......... ... . | +-- 76 | 0001000100 | 1...1.....1..................... . . . . ... . . . . . .. .. .1 .1 1 1 . . . .......... ... . | +-- 77 | 1101000100 | .1.1......1...1.1...........111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 78 | 0-11000100 | ...1.................11...1..11. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 79 | 01-1000100 | .1111.........111111....1.....1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 80 | 011-000100 | .1111............1...11...1...1. . . . . ... . . . . . .1 .. .. .. . . . . . .......... ... . | +-- 81 | 10--000100 | ..1.1..........................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 82 | 11-0100100 | ................................ . . . . ... 1 1 . . . .. .. .. .. . . . 1 . .......... ... . | +-- 83 | 0001100100 | .11111....................111... . . . . ... . . . . . 11 .. .1 .. . . . . . .......... ... . | +-- 84 | 0-11100100 | .1.1.1.........11....1....11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 85 | 1-1-100100 | 1..111...11...1....1......111.1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 86 | 10--100100 | ................................ . . . . ... . . . . . .. .1 .. .. . . . . . .......... ... . | +-- 87 | 0000-00100 | .1.1.1...1....1..1...1....1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 88 | 10-0-00100 | ................................ . . . . ... . . . . . .. .. .1 .1 1 1 . . . .......... ... . | +-- 89 | 1101-00100 | ................................ . . . . ... . . . . . .. .. .. .. . . . 1 . .......... ... . | +-- 90 | 11-0010100 | .1.1.1...1....1..1........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 91 | 0001010100 | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . 1 . .......... ... . | +-- 92 | 010-010100 | .1111.........11..........1...1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 93 | -01-010100 | .1.1.1...1....1......1111.1111.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 94 | 0-00110100 | ................................ . . . . ... 1 . . . . 11 .. .1 .. . . . . . .......... ... . | +-- 95 | -1-0110100 | ..111.....1.....1111111111111..1 . . . . ... 1 . . . . .. .1 .. .. . . . . . .......... ... . | +-- 96 | 000-110100 | .1...1....................11.... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 97 | 01--110100 | .1111....1....1...11.11..11..1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 98 | 0-00-10100 | ..111.......................1... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 99 | 0001-10100 | .1.1......1...1.11..........111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 100 | 1101-10100 | .1...1...1.............11.1.111. . . . . ... . 1 . . . .. .. .1 .. . . . . . .......... ... . | +-- 101 | 011--10100 | .11111.............1..11.1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 102 | 01000-0100 | .11111...1.....1...11.....111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 103 | -0100-0100 | .1.1.1...1....1..1........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 104 | 10-01-0100 | ...............................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 105 | 11011-0100 | .1111....1....1.11............1. . . 1 . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 106 | 101---0100 | .1...1...1..............1.1.111. . . . . ... . . . . . .. .1 .. .. . . . . . .......... ... . | +-- 107 | 111---0100 | ................................ . . . . ... . 1 . . . .. .. .. .. . . . . . .......... ... . | +-- 108 | 0001001100 | ................................ . . . . ... 1 . . . . 11 .. .1 .. . . . . . .......... ... . | +-- 109 | -001001100 | .11111....................111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 110 | --11001100 | .11111.............1......11.... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 111 | 01-1001100 | .1111.........111.1....1......1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 112 | -1-1001100 | .................1.............. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 113 | 00-0101100 | 1...1.....1..................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 114 | 10-0101100 | .1.1......1...1.1.....1....1111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 115 | 01-0101100 | .1.1.1........111....1....11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 116 | 11-0101100 | ...1.1..................1.1.111. . . . . ... 1 . 1 . . .. .1 .. .. . . . . . .......... ... 1 | +-- 117 | 01-1101100 | .11111...11....1..........11.11. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 118 | 0-1-101100 | .1.1.1....1...1.1....1....11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 119 | 011--01100 | .1.1.1........1.1111111..111..1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 120 | 11-0011100 | 1...1....1...................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 121 | --11011100 | ................................ . . . . ... 1 . . . . .1 .. .. .. . . . . . .......... ... . | +-- 122 | 01-1011100 | .1111..........111....1.......1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 123 | -1-1111100 | ..........1....1................ . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 124 | 110-111100 | .11111...1.............11.1.111. . . 1 . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 125 | 0-1-111100 | ..........1...1..........1..1... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 126 | 11--111100 | ................................ . . . . ... . . . 1 . .. .. .1 .. . . . . . .......... ... . | +-- 127 | 0000-11100 | .1.1......1...1.11..........111. . . . . ... . . . . . .. .. .. .. . . . 1 . .......... ... . | +-- 128 | 0001-11100 | 1...1.....1..................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 129 | 11-1-11100 | ................................ . . . . ... . . . . . .. .1 .. .. . . . . . .......... ... . | +-- 130 | 011--11100 | .11111...11...1...........11.11. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 131 | 10-00-1100 | ...1.1................1....1.1.. . . . . ... 1 . . . . .. .1 .1 .. . . . . . .......... ... . | +-- 132 | -1110-1100 | 1........................1..11.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 133 | 1-1-0-1100 | ................................ . . . . ... 1 . . 1 . .. 1. 11 .. . . . . . .......... ... . | +-- 134 | 00011-1100 | .1.1.....1.....1.....11...11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 135 | 1-011-1100 | .1...1...1.............11.1.111. . . . . ... . 1 . 1 . .. .. .1 .. . . . . . .......... ... 1 | +-- 136 | 0---1-1100 | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . . . ...11.1.1. ... . | +-- 137 | -01-00-100 | ................................ . . . . ... . 1 1 . . .. .. .. .. . . . . . .......... ... . | +-- 138 | 11-010-100 | ....1.....1...1................. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 139 | 101--0-100 | .11111....1.............1.1.111. . . . . ... 1 . 1 . . .. .1 .. .. . . . . . .......... ... . | +-- 140 | 000001-100 | ................................ . . . . ... . . . . . .. .1 .1 .1 1 1 . . . .......... ... . | +-- 141 | 010001-100 | .11111...1.....1...11.....111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 142 | 1-1-01-100 | 1...11...11.............11111.1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 143 | 01-011-100 | .....1....1...1....1..11.1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 144 | 0-1111-100 | .11111.............1......11.... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 145 | -010-1-100 | ..111..........................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 146 | 10-0-1-100 | ..111........................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 147 | 11-0000-00 | ..111..........................1 . . 1 . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 148 | -010100-00 | .1.1.....1.....1.....11...11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 149 | ---0100-00 | ................................ . . . 1 ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 150 | -010010-00 | ..111..........................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 151 | 10--010-00 | ..111........................... . . . . ... 1 . . . . .. .1 .. .. . . . . . .......... ... . | +-- 152 | --1---0-00 | ................................ . . . . ... 1 . 1 . . .. .. .. .. . . . . . .......... ... . | +-- 153 | 0000001-00 | .11111....1.............1.1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 154 | -010001-00 | .........1...........1....1..... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 155 | 10-1001-00 | ...111...1....1.....1.11.1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 156 | ----001-00 | ................................ . . . 1 ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 157 | 0-1--01-00 | ................................ . . . . ... . 1 . . . .. .. .. .. . . . . . .......... ... . | +-- 158 | 01-1111-00 | .11111.............1..11.1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 159 | 11-1111-00 | 1...11.........1........111111.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 160 | 100-111-00 | ................................ . . . . ... . . . . . .. .1 .. .. . . . . . .......... ... . | +-- 161 | -11-111-00 | ................................ . . . . ... 1 . . . . .. .. .1 .. . . . . . .......... ... . | +-- 162 | 1001-11-00 | 1..11....1.....................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 163 | 011-1-1-00 | .11111.........1....1.11.1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 164 | 10-001--00 | .1.1.1................1....1.1.. . . . . ... 1 . . . . .. .1 .1 .. . . . . . .......... ... . | +-- 165 | 01-011--00 | .1111........................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 166 | 1101-1--00 | ..111........................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 167 | 0-1-1---00 | ................................ . . . . ... . 1 1 . . .. .. .. .. . . . . . .......... ... . | +-- 168 | -101----00 | ................................ . . . . ... 1 . . 1 . .. .. .. .. . . . . . .......... 1.1 . | +-- 169 | 1101000010 | .1.1.1....1...1...........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 170 | 0-11000010 | .1...1.........1........11.1.... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 171 | 10-1000010 | .1.1......1...1.1.....1....1111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 172 | 011-000010 | .1111....1....1...1..11.111..1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 173 | 11-0100010 | ...11.....1....1.1.............. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 174 | 0-11100010 | ..111....11...11..........1..... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 175 | 0000-00010 | 1...1....1.....................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 176 | 1-1--00010 | 1..111...1................11..1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 177 | -010010010 | 1..11....1...................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 178 | -1-0110010 | ...11..............1.1...1.1.... . . . . ... . . 1 . . .1 .. .. .. . . . . . .......... ... . | +-- 179 | 00-1110010 | .1.1.1...1....1......111.1111.1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 180 | -11-110010 | 1..111...11...............11..1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 181 | 01--110010 | ...111...11...1...........11.11. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 182 | -110-10010 | ................................ . . . . ... . . . . . .1 .. .. .. . . . . . .......... ... . | +-- 183 | 11-0-10010 | .1...1....1.............1.1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 184 | 0001-10010 | .1.1.1...1....1..1........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 185 | 1101-10010 | ..111..........................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 186 | 011--10010 | .1111...........11...11...1...1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 187 | 01000-0010 | ..1111...1....1..1.1.1.1.1.1.1.1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 188 | 11-00-0010 | ................................ . . . . ... 1 . 1 . . .. .1 .. .. . . . . . .......... ... . | +-- 189 | 0-110-0010 | ..111.....1.....11.............. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 190 | 1-1-0-0010 | ................................ . . . . ... 1 . . 1 . .. .1 .. .. . . . . . .......... ... . | +-- 191 | -0--0-0010 | ................................ . . . . ... . . 1 . . .. .. .. .. . . . . . .........1 ... . | +-- 192 | 01001-0010 | .11111...1................111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 193 | 00011-0010 | .11.1....1...................... . . . . ... . 1 . . . .. 11 .. .. . . . . . .......... ... . | +-- 194 | 11011-0010 | ...111....1..........1.11111111. . . . . ... . . . . . .. .. 1. .. . . . . . .......... ... . | +-- 195 | 1--11-0010 | .11............................. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 196 | 011-1-0010 | .1...1........1.....1.1..1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 197 | 111-1-0010 | ................................ . . . . ... 1 1 . . . .. .. .. 1. . . . . . .......... ... . | +-- 198 | 101---0010 | ................................ 1 . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 199 | 0-00001010 | .11111...1................111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 200 | 1--0001010 | .1.1......1...1.11..........111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 201 | 1101001010 | ................................ 1 . . . ... . . . . . 1. .1 .1 .1 1 1 . . . .......... ... . | +-- 202 | 00-1001010 | .1.1.1...1....1......111..111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 203 | 011-001010 | .11111....1....1...1..11.1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 204 | 10--001010 | .....1....1.............1.1.111. . . . . ... . . . . . .. .. .1 .. . . . . . .......... ... . | +-- 205 | 0100101010 | .11111.............11.1....1.1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 206 | 0-11101010 | .11111.............1.1....11.... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 207 | 01-1101010 | .11111.............1..11.1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 208 | 110-101010 | ..111..........................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 209 | 0001-01010 | .1111....1....1.11............1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 210 | 1-01-01010 | ..111..........................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 211 | 000--01010 | ................................ . . 1 . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 212 | 11-0011010 | ...111.........1......1....1.1.. . . . . ... . 1 1 . . 1. .. .. .. . . . . . .......... ... . | +-- 213 | 1--0011010 | ................................ 1 . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 214 | --11011010 | .........11...11..............1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 215 | 01-1011010 | .1.............11....1........1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 216 | -0-0111010 | .1.1.1...1....1..1........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 217 | 1--0111010 | ................................ . . . . ... . . 1 . . .. .. .. .. . . . 1 . .......... ... . | +-- 218 | 01-1111010 | .1111....1....1.....1111111..... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 219 | 1-0-111010 | .1.1......1...1.1...........111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 220 | 0-1-111010 | .1.1.1.........11..1..111.11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 221 | -010-11010 | ................................ . . . . ... 1 . . . . .. .1 .. .. . . . . . .......... ... . | +-- 222 | 1001-11010 | 1..11....1....................1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 223 | 1101-11010 | .1.1.....1.....1.....11...11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 224 | 011--11010 | .1.1.1........1.1111111..111..1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 225 | 00010-1010 | ...............................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 226 | -0101-1010 | 1..11....1...................... . . . . ... . 1 . 1 . .. .. .1 .1 1 . . . . .......... ... . | +-- 227 | 10-01-1010 | .1.1.1...1....1.11........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 228 | 000100-010 | ..111..........................1 . . 1 . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 229 | 01-100-010 | .1111.....1...1......11111...11. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 230 | 101--0-010 | ..111..........................1 . . 1 . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 231 | 000001-010 | ................................ . . . . ... . 1 . . . .. 11 .. .. . . . . . .......... ... . | +-- 232 | 010001-010 | ..1111...1....1..1.1.1.1.1.1.1.1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 233 | 1-1-01-010 | 1..111....................11..1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 234 | --1011-010 | ................................ . . . . ... 1 . . . . .. .1 .. .. . . . . . .......... ... . | +-- 235 | 01-011-010 | ..1111....1....1.1.1.1.1.1.1.1.1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 236 | 0--1-1-010 | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . . . .......... 1.. . | +-- 237 | 11-0000110 | 1...1.....1..................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 238 | 0001000110 | .1.1.1...1....1..1........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 239 | 1101000110 | ................................ . . 1 . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 240 | --11000110 | ..111....11...11...........1.... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 241 | 10-1000110 | .1...1....1.............1.1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 242 | 11-1000110 | 1..11....1...................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 243 | 011-000110 | .1...1.............1..11.1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 244 | 0000100110 | ...1.1...1...........111..11.1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 245 | 0-01100110 | ..111..........................1 . . 1 . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 246 | 0000-00110 | ................................ . . . . ... . . . . . .. 1. .. .. . . . . . .......... ... . | +-- 247 | -010-00110 | ................................ . . . . ... 1 . . . . .. .1 .. .. . . . . . .......... ... . | +-- 248 | 10-1-00110 | ................................ . . . . ... . . . . . .. .. .1 .. . . . . . .......... ... . | +-- 249 | 01-1-00110 | .11111...1................111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 250 | 11-0010110 | .1.1......1...1.11..........111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 251 | 0001010110 | ..111.....1.....11111111111111.1 . . . . ... 1 . . . . .. .1 .. .. . . . . . .......... ... . | +-- 252 | 0-11010110 | .11111.............1......11.... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 253 | -000110110 | ................................ . . 1 . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 254 | 110-110110 | .11111....1..........1.11.111.1. . . . . ... . . . . . .. .. 1. .. . . . . . .......... ... . | +-- 255 | 1001-10110 | 1..11....1...................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 256 | 1101-10110 | .11111....1..........1.11111111. . . . . ... . . . . . .. .. 1. .. . . . . . .......... ... . | +-- 257 | 011--10110 | .1111....1....1.....1111111..... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 258 | 1-1-0-0110 | .........1.........11...1....... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 259 | 01001-0110 | .1.1.1........11111....1..11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 260 | 10011-0110 | .1...1...1.............11.1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 261 | 0-111-0110 | .1.1.1....1...1.1....1....11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 262 | 01-11-0110 | .1111...........11...11...1..... . . . . ... 1 . . . . .1 .. .. .. . . . . . .......... ... . | +-- 263 | 10-1--0110 | ................................ . . . . ... . 1 . 1 . .. .. .. .. . . . . . .......... ... . | +-- 264 | 0100001110 | .1.1.1........11111....1..11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 265 | -010001110 | ................................ . . . . ... 1 . . . . .. .1 .1 .1 1 1 . . . .......... ... . | +-- 266 | 11-0001110 | ...111....................111... . . . . ... 1 . . . . 11 .. .1 .. . . . . . .......... ... . | +-- 267 | 0-11001110 | .1.1.1....1...1.1....1....11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 268 | 01-1001110 | .11111.............1......111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 269 | 0000101110 | .1.1.1...1....1..1........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 270 | 10-0101110 | .1.1......1...1..1...1....1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 271 | 0-11101110 | ...1.1....1...11...1..1....1.1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 272 | 11--101110 | ...11....1....1.11............1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 273 | 1101-01110 | .1.1.....1....1.1....1....1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 274 | 011--01110 | .1...1...11...1...........11.11. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 275 | 11-0011110 | .1111....1....1..1...1.1111..1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 276 | --11011110 | .....1....1....1........11.1.... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 277 | -01-011110 | ................................ . . . . ... 1 1 . . . .. .. .1 .. . . . . . .......... ... 1 | +-- 278 | -1-1111110 | .1.1.1........1.1111111..111..1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 279 | -0--111110 | ..111..........................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 280 | 11--111110 | .1.1.1...1....1..1........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 281 | 0000-11110 | ..........1.....11111111111111.. . . . . ... 1 . . . . .. .1 .. .. . . . . . .......... ... . | +-- 282 | -010-11110 | .1...1...1.............11.1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 283 | 0001-11110 | .1.......1....1.11............1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 284 | 10-1-11110 | .1.1.1........1..1........1111.. . . . . ... 1 . . . . .1 .. .. .. . . . . . .......... ... . | +-- 285 | 11-1-11110 | ..111..........................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 286 | 00011-1110 | ................................ . . . . ... . 1 . . . .. 11 .. .. . . . . . .......... ... . | +-- 287 | 00-11-1110 | .11.1....1...................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 288 | 1--11-1110 | .1.1.1...1....1..1........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 289 | 01-110-110 | .1111.....1....1..11111...1..1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 290 | 111-10-110 | 1..111........11........111111.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 291 | --10-0-110 | ..111........................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 292 | 000001-110 | 1...1..........................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 293 | 0-1011-110 | .1...1...1.............11.1.111. . . . . ... . 1 . 1 . .. .. .1 .. . . . . . .......... ... 1 | +-- 294 | 01-011-110 | .11111...1.....1...11.....111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 295 | -00111-110 | .1.1..........1......11...11111. . . . . ... . . 1 . . .. .. .. .. . . . 1 . .......... ... . | +-- 296 | 110--1-110 | ................................ . . . . ... 1 1 . . . .. .. .. .. . . . . . .......... ... . | +-- 297 | 11011--110 | .1.1.....1.....1.....11...11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 298 | -1111--110 | ................................ . . . . ... . 1 . . . .. .. .1 .. . . . . . .......... ... . | +-- 299 | 101----110 | .1.1.1...1....1..1........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 300 | -010000-10 | ................................ . . . . ... 1 . . . . .. .1 .. .. . . . . . .......... ... . | +-- 301 | 01-1100-10 | .1.1.1.........111....1...11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 302 | 0-00110-10 | ..111..........................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 303 | 10-0110-10 | .1.1.1...1....1..1........1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 304 | 100-110-10 | ................................ . . 1 . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 305 | --101-0-10 | ..111........................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 306 | 0000001-10 | .1...1.............11...1.1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 307 | 000-001-10 | ..111..........................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 308 | 11-0101-10 | ................................ . . 1 . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 309 | 111-101-10 | 1..111...1....11........111111.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 310 | 0000011-10 | .....1...............111..11.1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 311 | 00--011-10 | ..111........................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 312 | -001111-10 | ...............................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 313 | 101--11-10 | .1.1.....1....1.1....1....1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 314 | 00010-1-10 | ................................ . . 1 . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 315 | 1-0-1-1-10 | ................................ . . . . ... 1 1 . . . .. .. .. .. . . . . . 11..111... 1.. . | +-- 316 | -0-100--10 | ................................ . . . . ... 1 1 . . . .. .. .. .. . . . . . 1..1..11.1 ... . | +-- 317 | 01-1-0--10 | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . . . .......... ... . | +-- 318 | 1-0111--10 | ...111...1.............11.1.111. . . . . ... . . . 1 . .. .. .1 .. . . . . 1 .......... ... . | +-- 319 | 00000---10 | .........1...................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 320 | 1--00000-0 | ................................ . . . . ... . . . . . .. .. .1 .1 1 1 . . . .......... ... . | +-- 321 | -0101000-0 | .1.......1....1.11............1. . . 1 . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 322 | 10-10100-0 | ..111........................1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 323 | 01-10100-0 | .11111.............11.1....1.1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 324 | -01-0100-0 | ................................ . . . . ... . 1 . . . .. .. .. .. . . . . . .......... ... . | +-- 325 | 11-00-00-0 | ..111..........................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 326 | -0-00010-0 | .................1.............. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 327 | 11-00010-0 | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . 1 . .......... ... . | +-- 328 | 000-0010-0 | .1.1......1...1.11..........111. . . . . ... 1 1 1 . . .. .. .. .. . . . 1 . .......... ... . | +-- 329 | 0000-010-0 | ..111..........................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 330 | 01-0-010-0 | ................................ . . . . ... . 1 1 . . .. .. .. .. . . . . . .......... ... . | +-- 331 | 1--00110-0 | .11............................. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 332 | 0-010110-0 | ..111........................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 333 | -0-1-110-0 | ................................ . . . . ... 1 . 1 1 . .. .. .. .. . . . . . .......... ... . | +-- 334 | 10-000-0-0 | ................................ . . . . ... . . . . . .1 .. .1 .. . . . . . .......... ... . | +-- 335 | 1-1-0001-0 | 1..111....1..............1111.1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 336 | 11--0001-0 | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . . . .......... ... . | +-- 337 | 10-01001-0 | ..111........................1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 338 | 01-11001-0 | ..111....1.....................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 339 | 10-1-001-0 | ..111........................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 340 | -0100101-0 | .................1.............. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 341 | 11-00101-0 | ................................ . . . . ... . . 1 . . .. .. .. .. . . . 1 . .......... ... . | +-- 342 | 11-0-011-0 | .11............................. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 343 | 10-1-111-0 | ..............................1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 344 | 101--111-0 | ...111.............1.1..11111... . . . . ... . . 1 . . .1 .. .. .. . . . . . .......... ... . | +-- 345 | 0-101-11-0 | .1.......1....1.11............1. . . 1 . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 346 | -1111-11-0 | 1..111.........1..........1...1. . . . . ... . 1 1 1 . .1 .. .. .. . 1 . . . .......... ... . | +-- 347 | 000111-1-0 | ................................ . . . . ... . . . . . .1 .. .. .. . . . . . .......... ... . | +-- 348 | 1-0111-1-0 | .1.1.1...1....1..1........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 349 | 10-01--1-0 | ................................ . . . . ... 1 . . . . .. .. .. .. . . . . 1 1...1..1.1 ... . | +-- 350 | 011-1--1-0 | .11111.........1....1.11.1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 351 | 10-0000--0 | 1............................... . . . . ... . . . . . .1 .1 .1 .1 1 1 . . . .......... ... . | +-- 352 | 11-0100--0 | .11............................. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 353 | -110110--0 | 1....1...1................1..... . . . . ... 1 . . . . .. .. 11 .. . . . . . .......... ... . | +-- 354 | 0000001--0 | ................................ . . . . ... 1 . 1 . . .. .1 .. .. . . . . . .......... ... 1 | +-- 355 | 10--001--0 | .11............................. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 356 | 1-1-011--0 | 1...11.........1..........1...1. . . . . ... . . 1 . . .1 .. .. .. . 1 . . . .......... ... . | +-- 357 | -001111--0 | 1..11....1...................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 358 | 10-00-1--0 | ....1........................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 359 | 0001000001 | 1...1....1...................... . . . . ... . . . . . .. .. .1 .1 1 1 . . . .......... ... . | +-- 360 | 0-11000001 | ...............11....1.......... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 361 | 110-000001 | .1.1.1....1...1..1........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 362 | 011-000001 | .1111....1....1.....1111111..... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 363 | 0-11100001 | .11111...11...1.........11.1.... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 364 | 1-1-100001 | 1....1....1...............11..1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 365 | 0000-00001 | 1...1.....1..................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 366 | 11-0-00001 | .1111....1....1.11............1. . . 1 . ... . . . . . .. .. .. .. . . . 1 . .......... 1.. . | +-- 367 | 000-010001 | .11111...1....1.....1.11.1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 368 | 010-010001 | .1111.........111....1........1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 369 | -000110001 | ................................ . . . . ... . 1 1 . . .. 11 .. .. . . . . . 1...1.1..1 ... . | +-- 370 | -1-0110001 | .11.1.....1...1................. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 371 | 00-1110001 | .1.1.1....1...1.1....1....11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 372 | -00-110001 | ................................ . 1 . 1 ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 373 | -11-110001 | 1..111....................11..1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 374 | 1101-10001 | .11111...1.............11.1.111. . . 1 . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 375 | 10-1-10001 | ................................ . . . . ... . . 1 . . .1 .. .. .. . . . . . .......... ... . | +-- 376 | 011--10001 | .11111....1....1...1..11.1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 377 | 1-1--10001 | .........1...................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 378 | 01000-0001 | ..111....1.......1.1.1.1.1.1.1.1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 379 | 11-00-0001 | .1.1.1...1....1..1........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 380 | --010-0001 | ................................ . . . . ... 1 1 . . . .. .. .. .. . . . . . ......11.. ... . | +-- 381 | 1-1-0-0001 | 1..111....1...............1111.. . . . . ... 1 . 1 1 . .. 1. .. .. . . . . . .......... ... . | +-- 382 | 01001-0001 | .11111...1.....1...11.....111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 383 | 10011-0001 | .1.1.1...1....1..1........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 384 | 11011-0001 | ................................ 1 . . . ... . . . . . 1. .1 .1 .1 1 1 . . . .......... ... . | +-- 385 | 101---0001 | ...................1.1..11...... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 386 | 0-00001001 | .11111...1.....1...11.....111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 387 | --10001001 | .1111....1....1....11111..1..1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 388 | 11-1001001 | 1..11....1...................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 389 | ---1001001 | ................................ . 1 . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 390 | -01-001001 | .1.1.1....1...1.1....1....11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 391 | -000101001 | 1...1....1...................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 392 | 0100101001 | .1.1.1........1111....1...11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 393 | 11-0101001 | ..111...................1....11. . . . . ... . . 1 . . .. .1 .. .. . . . . . .......... ... 1 | +-- 394 | 0001101001 | .11111...1....1.....1.11.1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 395 | 0-11101001 | ..111....11...11...........1.... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 396 | 01-1101001 | .1.1.1........1.1111111..111..1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 397 | 11-1101001 | ................................ . . . . ... 1 1 . 1 . .. .. .1 .. . . . . . .......... 1.. 1 | +-- 398 | 11-0011001 | ..111.....1.....11111111111111.1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 399 | 0001011001 | 1...1....1...................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 400 | 01-1111001 | .11111...11...1...........11.11. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 401 | 1-0-111001 | .1.1.....1....1.1....1....1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 402 | 0000-11001 | .11111...1....1.....1.11.1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 403 | --10-11001 | ................................ . . . . ... . . . . . .1 .. .. .. . . . . . .......... ... . | +-- 404 | 1101-11001 | .1111.....1....1.1.............. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 405 | 0-11-11001 | .11111.............1......11.... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 406 | 101--11001 | .1.1.1...1....1..1........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 407 | 10-01-1001 | ................................ . . 1 . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 408 | 11011-1001 | ................................ . . 1 . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 409 | 1-011-1001 | .11111...1.............11.1.111. . . . . ... . . . 1 . .. .. .1 .. . . . . . .......... ... . | +-- 410 | 00--1-1001 | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . . . ....1..11. ... . | +-- 411 | -01000-001 | .1.1..........1......11...11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 412 | 11-000-001 | .1.1.....1....1.1....1....1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 413 | 01-100-001 | .....1.........1................ . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 414 | -00-10-001 | ................................ . . . . ... . 1 . . . .. .. .. .. . . . . . ...1...11. ... . | +-- 415 | 101--0-001 | .11111...1..............1.1.111. . . . . ... 1 . 1 . . .. .1 .. .. . . . . . .......... ... . | +-- 416 | 010001-001 | ..111....1.......1.1.1.1.1.1.1.1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 417 | 0-1101-001 | .11111.............1......11.... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 418 | 0-1011-001 | .1111.....1...1..1.............. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 419 | 01-011-001 | ..111.....1......1.1.1.1.1.1.1.1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 420 | 1101000101 | ................................ . . . . ... 1 . . . . .. .1 .1 .1 1 1 . . . .......... ... . | +-- 421 | 10-1000101 | .1.1......1...1..1...1....1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 422 | 01-1000101 | .11111...1.....1...11.....111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 423 | 000-000101 | .11111...1....1.....1.11.1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 424 | 011-000101 | .1.1.1........1.1111111..111..1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 425 | 1-1-000101 | 1..111..................1.1111.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 426 | 11-0100101 | .11111.............1.1..1111111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 427 | 1--0100101 | ................................ . . . . ... . . . . . .1 .. .. .. . . . . . .......... ... . | +-- 428 | 0001100101 | .1...1..................1.1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 429 | 0-01100101 | ................................ . . . . ... . . 1 . . .. .1 .. .. . . . . . .......... ... 1 | +-- 430 | 0-11100101 | .1...1.........1........11.1.... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 431 | 1-1-100101 | 1....1...1.....1....1.....111.1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 432 | 10--100101 | ................................ . . 1 . ... . . . . . .1 .. .. .. . . . . 1 .......... ... . | +-- 433 | 11-0010101 | .1.1.....1....1.1....1....1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 434 | 0001010101 | .11111...1...........1111.11.1.. . . . . ... . . . . . .. 11 .. .. . . . . . .......... ... . | +-- 435 | -101010101 | .11111.............11.1....1.1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 436 | -01-010101 | .11111...11...11...1..1....1.1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 437 | 0-00110101 | ...1....................1.1.111. . . . . ... 1 . 1 . . .. .1 .. .. . . . . . .......... ... 1 | +-- 438 | 110-110101 | .11111.........1......1....1.1.. 1 . . . ... . 1 1 . . 1. .. .. .. . . . . . .......... ... . | +-- 439 | 01--110101 | ..........1....1................ . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 440 | 1101-10101 | ................................ 1 . . . ... . . . . . 1. .1 .. .. . . . . . .......... ... . | +-- 441 | 011--10101 | .11111...11...1...........11.11. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 442 | 01000-0101 | .11111.........1.........1.1.... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 443 | -0100-0101 | .11111...1.............11.1.111. . . . . ... . . . . . .. .. .1 .. . . . . . .......... ... 1 | +-- 444 | 1-1-0-0101 | ................................ . . . . ... . . . . . .. 1. 11 .. . . . . . .......... ... . | +-- 445 | 0-001-0101 | .....1........1................. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 446 | 0-111-0101 | ..111.....1.....11.............. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 447 | -1-11-0101 | ................................ . . . . ... . 1 1 . . .. .. .. .. . . . . . .......... ... . | +-- 448 | 101---0101 | ................................ . . 1 . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 449 | 0100001101 | .....1........1................. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 450 | 11-0001101 | ................................ 1 . . . ... . . . . . 1. .1 .1 .1 1 1 . . . .......... ... . | +-- 451 | 0001001101 | .11111...1..............1.1.111. . . . . ... 1 . 1 . . .. .1 .. .. . . . . . .......... ... . | +-- 452 | 01-1001101 | .11111.............11.1....1.1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 453 | 0-11101101 | .1.1.1...1....1......111..111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 454 | 01-1101101 | .1111.....1....1....1111111..... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 455 | -010-01101 | ................................ . . . . ... . . . . . .1 .. .. .. . . . . . .......... ... . | +-- 456 | 11-0-01101 | ..111.........1.....1.11.1.1.... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 457 | 10-1-01101 | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . . 1 1.111.1.1. ... . | +-- 458 | 011--01101 | .11111.............1..11.1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 459 | --11011101 | ...............1..........1...1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 460 | 11--011101 | ................................ . . 1 . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 461 | -1-1111101 | .1111................11...1...1. . . . . ... 1 . . . . .1 .. .. .. . . . . . .......... ... . | +-- 462 | 0000-11101 | ................................ . . . . ... . 1 . . . .. 11 .. .. . . . . . .......... ... . | +-- 463 | 11-0-11101 | ..111..........................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 464 | 0001-11101 | .11111...1....1.....1.11.1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 465 | 1001-11101 | ..111........................1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 466 | -0-1-11101 | ................................ . . . 1 ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 467 | 11-1-11101 | 1..11....1...................... . . . . ... . . . 1 . .. .. .1 .1 1 1 . . . .......... ... . | +-- 468 | 0-1100-101 | ..111.....1.....1111............ . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 469 | 000010-101 | .11111...1....1.....1.11.1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 470 | --0010-101 | ................................ . . . . ... . 1 1 . . .. .. .. .. . . . . . ....1.1.1. ... . | +-- 471 | 000110-101 | ..111....1.....1................ . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 472 | 101--0-101 | .11111...1....1.....1.11.1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 473 | -00001-101 | 1...1.....1..................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 474 | 010001-101 | .11111.........1.........1.1.... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 475 | -01001-101 | .1.1.1...1....1..1........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 476 | 01-011-101 | .1111.........1111111....1....1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 477 | 11011--101 | .1........1....1.1.............. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 478 | 011-1--101 | .1.1.1....1.....11....1...11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 479 | 11-0000-01 | .1.1.1...1....1..1........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 480 | -010100-01 | .1111.....1...1..1.............. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 481 | 10-1100-01 | .1.1.1........1..1........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 482 | -010010-01 | .1.1.1...1....1..1........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 483 | 10-1010-01 | ................................ . . 1 . ... 1 . . . . .1 .. .. .. . . . . 1 .......... ... . | +-- 484 | 10-0110-01 | ...1.1........1.....1.11.1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 485 | 0001110-01 | ................................ . . . . ... . . . . . .1 .. .. .. . . . 1 . .......... ... . | +-- 486 | 01--110-01 | .11111.............1..11.1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 487 | 1101-10-01 | ................................ . . . . ... . . . 1 . .. .. .1 .. . . . . . .......... ... . | +-- 488 | -01--10-01 | ................................ . . . . ... . 1 . . . .. .. .. .. . . . . . ........1. ... . | +-- 489 | 0000001-01 | ..111....11....................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 490 | 10-1001-01 | .1.1.1...1....1..1........1.111. . . 1 . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 491 | 11-0101-01 | .1...1...1................1.1... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 492 | -1-0-01-01 | ................................ . . . 1 ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 493 | 01---01-01 | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . . . .......... ... . | +-- 494 | -001111-01 | .1.1.1...1....1..1........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 495 | 100-111-01 | ...1.1..................1.1.111. . . 1 . ... . 1 . . . .. .. .1 .. . . . . . .......... ... . | +-- 496 | 011--11-01 | .1111................11...1..... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 497 | -0101-1-01 | .1111....1....1..1.............. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 498 | -00011--01 | .11.1....1...................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 499 | 00000---01 | ................................ . . . . ... . 1 . . . .. .. .. .. . . . . . .......... ... . | +-- 500 | 0-------01 | ................................ . . . 1 ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 501 | -010000011 | .1...1...1.............11.1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 502 | 1101000011 | .1.1.....1....1.1....1....1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 503 | 011-000011 | .11111....1....1...1..11.1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 504 | 1-1-000011 | .........11.........1....1..1... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 505 | -010100011 | .1111.....1....1.1.............. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 506 | 1--0100011 | .1.1.....1.....1.....11...11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 507 | 0-11100011 | .11111.............1.1....11.11. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 508 | 0000-00011 | .1.1......1...1..1...1....1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 509 | 10-1-00011 | .1...1....1.............1.1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 510 | 10---00011 | ................................ . . . . ... . . . . . .. .. .1 .. . . . . . .......... ... . | +-- 511 | -000010011 | .....1................1....1.1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 512 | -010010011 | ................................ . . . . ... . . . . . 1. .. .. .1 1 . . . . .......... ... . | +-- 513 | -0-0010011 | ..111........................... 1 . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 514 | 1--0010011 | .11111...1....1.....1.11.1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 515 | 10--010011 | ................................ 1 . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 516 | -101110011 | .........1..........11111.1..... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 517 | 00-1110011 | .11111...11...11...1..1....1.1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 518 | 0-00-10011 | ................................ . . . . ... . . 1 . . 1. .1 .. .. . . . . . .......... ... . | +-- 519 | 0001-10011 | .1.1.....1....1.1....1....1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 520 | 1101-10011 | .1.1.1...1....1..1........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 521 | 011--10011 | .1.1.1........1.1111111..111..1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 522 | 01000-0011 | .1.1.1........1111111....111111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 523 | -0100-0011 | ................................ . . . . ... . . . . . .. .1 .1 .. . . . . . .......... ... 1 | +-- 524 | 0-110-0011 | .1.1.1....1...1.1....1....11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 525 | ---10-0011 | ................................ . . . . ... 1 . . . . .. .. .. .. . . . . . .1.......1 ... . | +-- 526 | -11-0-0011 | ................................ . . . . ... . 1 1 1 . .. .. .. .. . . . . . .......... ... . | +-- 527 | 10-01-0011 | 1...1.....1..................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 528 | 00011-0011 | ................................ 1 . . . ... . . . . . 1. .1 .1 .1 1 . . . . .......... ... . | +-- 529 | 101---0011 | ................................ . . . . ... 1 . . . . 11 .. .1 .. . . . . . .......... ... . | +-- 530 | 1--0001011 | .1...1.............1.1..111111.. . . . . ... . . 1 . . .1 .. .. .. . . . . . .......... ... . | +-- 531 | 1101001011 | .1...1....1..........1.1111111.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 532 | 00-1001011 | .11111...11...11...1..1....1.1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 533 | 11-1001011 | ................................ . . . . ... 1 . . . . .. .. 1. .. . . . . . .......... ... . | +-- 534 | 0000101011 | .1.1.1...1....1..1........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 535 | 11-0101011 | .1.......1....1..1...1.1111..1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 536 | 01-1101011 | .1............11................ . . . . ... 1 . . . . 11 .. .. .. . . . . . .......... ... . | +-- 537 | 0-1-101011 | ..111.....1.....11111111........ . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 538 | 0001-01011 | .1........1....1.1.............. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 539 | 011--01011 | .1111...........1....11...1...1. . . . . ... . . . . . .1 .. .. .. . . . . . .......... ... . | +-- 540 | 1--0011011 | ................................ . . . . ... . . . . . .. .. .1 .1 1 1 . . . .......... ... . | +-- 541 | --11011011 | .11111........1....11....1.1.... 1 . . . ... . . . . . 1. .. .. .. . 1 . . . .......... ... . | +-- 542 | 0---011011 | ................................ . . . . ... . 1 . . . .. .. .. .. . . . . . .......... ... . | +-- 543 | -1-1111011 | .1.......1....1...1.111.1.1..1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 544 | -010-11011 | .11111...1.............11.1.111. . . 1 . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 545 | 11-0-11011 | ................................ . . . . ... . . . . . .. .1 .. .. . . . . . .......... ... . | +-- 546 | 11-1-11011 | .1........1...1..1.............. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 547 | 00010-1011 | .1111....1....1..1...1.1111..1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 548 | --101-1011 | ................................ 1 . . . ... . . . . . 1. .1 .1 .1 1 . . . . .......... ... . | +-- 549 | 11----1011 | ..111........................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 550 | 000100-011 | .1.1.1...1....1..1........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 551 | 01-100-011 | .11111....1...1....1..11.1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 552 | 10-110-011 | .1.1.1...1....1..1........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 553 | -00001-011 | ................................ 1 . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 554 | 010001-011 | .1.1.1........1111111....111111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 555 | 1-1-01-011 | 1...11....1.............11111.1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 556 | 000011-011 | .1.1.....1....1.1....1....1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 557 | --1011-011 | .11111...1.............11.1.111. . . 1 . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 558 | 01-011-011 | .1111.....1...1......11111...11. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 559 | 000111-011 | ................................ 1 . . . ... . . . . . 1. .1 .1 .1 1 1 . . . .......... ... . | +-- 560 | -010-1-011 | ................................ . . . . ... . . . . . .. .. .1 .. . 1 . . . .......... ... 1 | +-- 561 | 0-011--011 | ..111........................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 562 | 011-1--011 | .1.1.1....1.....111....1..11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 563 | 111-1--011 | 1..111.........1....1...1.1111.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 564 | -1-1---011 | ................................ . . . 1 ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 565 | --00000111 | ..............1................. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 566 | -010000111 | .11111................1....1.1.. . . . . ... . . . . . 1. .. .1 .. . . . . . .......... ... . | +-- 567 | -0-0000111 | ................................ 1 . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 568 | 0001000111 | .1.1.....1....1.1....1....1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 569 | 0-11000111 | .11111.............1.1....11.... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 570 | 011-000111 | .11111...11...1...........11.11. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 571 | -010100111 | 1..11....1...................... . . 1 . ... . . . . . .. .. .1 .1 1 . . . . .......... ... . | +-- 572 | 11-0100111 | ................................ . . . . ... . . . . . 1. .1 .1 .1 1 1 . . . .......... ... . | +-- 573 | 1--0100111 | ................................ 1 . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 574 | 0-01100111 | .1111....1....1..1...1.1111..1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 575 | 0-11100111 | .1.1.1...1....1......11.1111.11. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 576 | -000-00111 | ................................ 1 . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 577 | 11-0-00111 | ..111...............1.11.1.1.... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 578 | 0-00010111 | .1.1......1...1..1...1....1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 579 | 1--0010111 | .11111.............1.1..111111.. . . . . ... . . 1 . . .1 .. .. .. . . . . . .......... ... . | +-- 580 | 0-01010111 | .11111.........1......1....1.1.. 1 . . . ... . . . . . 1. .. .. .. . . . . . .......... ... . | +-- 581 | 0-11010111 | .1.1.1.........11..1..111.11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 582 | 110-110111 | .1.1.1....1...1..1........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 583 | 010--10111 | .1.1.1..........1111111...11..1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 584 | 01-10-0111 | .11111..............1.1....1.1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 585 | -000001111 | .1.1......1...1..1...1....1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 586 | -010001111 | 1..11....1...................... . . 1 . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 587 | 1--0001111 | ..111...................1....11. . . . . ... 1 . 1 . . .. .1 .. .. . . . . . .......... ... . | +-- 588 | --11001111 | .1.1.1...1....1......111.1111.1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 589 | 10--001111 | .11.1....1...................... 1 . . . ... . 1 . . . .. 11 .. .. . . . . . .......... ... . | +-- 590 | 0-00101111 | .1.1.....1....1.1....1....1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 591 | 0001101111 | ..111.....1.....1111111111111..1 . . . . ... 1 . . . . .. .1 .. .. . . . . . .......... ... . | +-- 592 | -1-1101111 | ................................ . . . . ... 1 . . . . .1 .. .. .. . . . . . .......... ... . | +-- 593 | 11--101111 | .1111.....1....1.1.............. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 594 | 0--0-01111 | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . . . .......... ... . | +-- 595 | 11-1-01111 | .1.1......1...1.1...........111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 596 | -0-0011111 | ..111........................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 597 | 1--0011111 | 1...1.....1..................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 598 | 0-01011111 | .1111.....1....1.1.............. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 599 | 00-0111111 | .11111.........1......1....1.1.. 1 . . . ... . 1 1 . . 1. .. .. .. . . . . . .......... ... . | +-- 600 | 11--111111 | .11111...1.............11.1.111. 1 . . . ... . . . . . .. .. .1 .. . . . . . .......... ... . | +-- 601 | --10-11111 | .1...1................1....1.1.. 1 . . . ... . . . . . 1. .1 .1 .. . . . . . .......... ... . | +-- 602 | 10-0-11111 | .1.1.1...1....1.11........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 603 | --11-11111 | ..........1...1...........1...1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 604 | 10-1-11111 | 1..11....1...................... . . 1 . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 605 | 01-1-11111 | .11111.............1..11.1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 606 | 11-1-11111 | .1111....1....1..1.............. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 607 | 01-10-1111 | .1111.........1111....1.......1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 608 | --101-1111 | .1111.....1....1.1.............. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 609 | 1-011-1111 | .11111...1.............11.1.111. . . . . ... . . . . . .. .. .1 .. . . . . . .......... ... . | +-- 610 | 0-111-1111 | .11111.............1......11.... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 611 | -11---1111 | .1111....1....1.....1111111..... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 612 | 1-1---1111 | .1.1.....1....1.1....1....1.111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 613 | 11-000-111 | .1...1...1................1.1... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 614 | 01-110-111 | .1111...........1....11...1..... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 615 | 111-10-111 | 1....1....1........11...1.111.1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 616 | 0100-0-111 | .....1.............1............ . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 617 | 010-01-111 | .....1........1................. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 618 | 0-1011-111 | ................................ . . . . ... . . . . . 1. .1 .1 .. . . . . . .......... ... . | +-- 619 | --1011-111 | ................................ 1 . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 620 | 01-011-111 | .11111.........1.........1.1.... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 621 | 0-1111-111 | .1.1.....1....1......1.11.1.1... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 622 | 0-1-11-111 | .....1................1....1.1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 623 | 1-01-1-111 | ................................ . . . . ... 1 1 . 1 . .. .. .. .. . . . . . 11.1.111.1 ... . | +-- 624 | 101--1-111 | .11111....1.............1.1.111. . . . . ... . . 1 . . .. .1 .. .. . . . . . .......... ... . | +-- 625 | 011--1-111 | .1111....1....1.....11111.1..1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 626 | 011-1--111 | .1.1.1....1.....1....1....11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 627 | -10-000-11 | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . . . 11.....1.. ... . | +-- 628 | ----100-11 | ................................ . . . . ... . . 1 . . .. .. .. .. . . . . . .......... ... . | +-- 629 | 010-010-11 | ..111.....1..............1111111 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 630 | 0-00110-11 | .1.1.1...1....1..1........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 631 | 0001110-11 | ................................ . . . . ... . . . . . .. .1 .1 .1 1 1 . . . .......... ... . | +-- 632 | -001110-11 | ..111..........................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 633 | -1-1110-11 | ..............1..........1...... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 634 | 01001-0-11 | .11111..............1.1....1.1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 635 | 11011-0-11 | .1........1...1..1.............. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 636 | 01--1-0-11 | ................................ . . . . ... 1 1 . . . .. .. .. .. . . . . . .......... ... . | +-- 637 | -1-0--0-11 | ................................ . . . 1 ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 638 | 0100001-11 | .11111..............1.1....1.1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 639 | 0001001-11 | .1.1.1...1....1..1........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 640 | 01-0101-11 | ..111....1................111111 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 641 | 10-0-01-11 | ....1.....1....................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 642 | 0-1-111-11 | .1.1.1....1...1.11111....111111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 643 | -11--11-11 | .11111.............1..11.1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 644 | 1-1--11-11 | .1.1......1...1.11..........111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 645 | 0-010-1-11 | ................................ . . . . ... 1 1 . . . .. .. .. .. . . . . . .......... ... . | +-- 646 | -1110-1-11 | .........1..............1....... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 647 | 11011-1-11 | .1.......1....1..1.............. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 648 | -1-1--1-11 | ................................ . . . 1 ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 649 | 11-111--11 | ................................ . . . . ... . . . . . .. .. .1 .. . . . . . .......... ... . | +-- 650 | -1--11--11 | ................................ . 1 . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 651 | 1-10----11 | ................................ . . . . ... . 1 1 . 1 .1 .. .. .1 1 1 . . . .......... ... . | +-- 652 | 11-00000-1 | 1...1....1...................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 653 | 10--0000-1 | ..111..........................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 654 | 01-11000-1 | .1...1....1...........1..1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 655 | ---11000-1 | ................................ . . . 1 ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 656 | -1-00100-1 | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . . . 11...1.... ... . | +-- 657 | 10-10100-1 | 1..1............................ . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 658 | 10--0100-1 | ................................ . . . . ... . . . . . .1 .. .. .. . . . . . .......... ... . | +-- 659 | 00011-00-1 | ..111....1.....1................ . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 660 | 101---00-1 | .11111....................111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 661 | -0000010-1 | ................................ . . . . ... . . . . . 1. .. .1 .. . . . . . .......... ... . | +-- 662 | -0100010-1 | ................................ . . . . ... . . . . . .. .. .. .. . . . 1 . .......... ... . | +-- 663 | 00010010-1 | .11111...1...........1111.11.1.. 1 . . . ... . . . . . .. 11 .. .. . . . . . .......... ... . | +-- 664 | 111-1010-1 | 1..111.........1.........11111.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 665 | 11-00110-1 | ................................ . . . . ... 1 . . . . .. .1 .. .. . . . . . .......... ... . | +-- 666 | 1001-110-1 | .1.1.1...1....1..1........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 667 | 101--110-1 | ................................ . . . . ... 1 1 . . . .. .. .. .. . . . 1 . .......... ... . | +-- 668 | 10-000-0-1 | ..111........................... 1 . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 669 | 0-1-11-0-1 | ................................ . . . . ... 1 1 . . . .. .. .. .. . . . . . .......... ... . | +-- 670 | -0-10--0-1 | ................................ . . . . ... . 1 . . . .. .. .. .. . . . . . .......... ... . | +-- 671 | 1001---0-1 | ................................ . . . . ... 1 . . . . .. .. .. .. . . . . 1 1....11..1 ... . | +-- 672 | 11010001-1 | ..111..........................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 673 | --1-0001-1 | ................................ . 1 . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 674 | 01-11001-1 | .1...1.............1......111... 1 . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 675 | 0--0-001-1 | ................................ . . . . ... . 1 . . . .. .. .. .. . . . . . .......... ... . | +-- 676 | -0100101-1 | ................................ . . . . ... . . . . . .. .. .. .. . . . 1 . .......... ... . | +-- 677 | 10-10101-1 | .1.1.1...1....1..1........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 678 | 100-1101-1 | .11............................. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 679 | 1-0-1101-1 | ................................ . . . 1 ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 680 | 1101-101-1 | .1111.....1...1..1.............. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 681 | 0--10-01-1 | ................................ . 1 . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 682 | 11010011-1 | ................................ . . . . ... . . . . . .. .. .. .. . . . 1 . .......... ... . | +-- 683 | 10-01011-1 | ....1.....1...................1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 684 | 01-01011-1 | .11111.............11.1....1.1.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 685 | 10-00111-1 | .11...........................1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 686 | -1--0111-1 | ................................ . . . . ... 1 1 . . . .. .. .. .. . . . . . .......... 1.. . | +-- 687 | ---01111-1 | ................................ . 1 . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 688 | 1--11111-1 | ................................ 1 . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 689 | 0-1-1111-1 | ..111....11...11..............1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 690 | -11--111-1 | .........1....1.....1..111...... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 691 | 10-00-11-1 | 1...1........................... . . . . ... . 1 . . . .1 .. .. .. . . . . . .......... ... . | +-- 692 | -1110-11-1 | 1..111.........1..........1...1. . . . . ... . 1 1 1 . .1 .. .. .. . 1 . . . .......... ... . | +-- 693 | 11011-11-1 | .....1................1....1.1.. . . . . ... . . . . . 1. .1 .1 .. . . . . . .......... ... . | +-- 694 | 11-11-11-1 | ................................ 1 . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 695 | ----00-1-1 | ................................ . . . . ..1 . . . . . .. .. .. .. . . . . . .......... ... . | +-- 696 | 1-1--0-1-1 | ................................ . . . 1 ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 697 | 1-1-01-1-1 | 1...11...................11111.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 698 | 0-1011-1-1 | .1111....1....1..1.............. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 699 | 1-0111-1-1 | ................................ 1 . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 700 | 11-111-1-1 | .........1..............1....... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 701 | 0-11---1-1 | ................................ . . . . ... 1 1 . . . .. .. .. .. . . . . . .......... ... . | +-- 702 | 10-0000--1 | ...11........................... 1 . . . ... . . . . . 1. .1 .1 .1 1 1 . . . .......... ... . | +-- 703 | 10-0100--1 | ................................ . . . . ... . . . . . .1 .. .. .. . . . . . .......... ... . | +-- 704 | -1-1100--1 | ..111........................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 705 | 10-00-0--1 | ..1............................. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 706 | 00-10-0--1 | ................................ . . . . ... . 1 1 . . .. .. .. .. . . . . . ...1....1. ... . | +-- 707 | -1111-0--1 | ................................ . . . . ... 1 1 . 1 . .. .. .. .. . . . . . .......... ... . | +-- 708 | 01-1011--1 | .11111....1...........1..1111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 709 | 1-1-011--1 | ................................ 1 . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 710 | 11-1111--1 | ................................ . . . . ... . 1 1 1 . .1 .. .. .. . 1 . . . .......... ... . | +-- 711 | -11-111--1 | 1...11.........1..........1...1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 712 | 1-001-1--1 | ................................ . . . . ... 1 . . . . .. .. .. .. . . . . 1 11........ ... . | +-- 713 | 011-1-1--1 | .11111....1............1..1..... . . . . ... . . . . . .. .1 .1 .. . . 1 . . .......... ... . | +-- 714 | 1-10--1--1 | ................................ 1 . . . ... . . 1 . 1 .1 .1 .. .1 1 1 . . . .......... ... . | +-- 715 | 10-010---1 | 1............................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 716 | 10-001---1 | 1............................... . . . . ... . 1 . . . .1 .. .. .. . . . . . .......... ... . | +-- 717 | 0-1-1----1 | ................................ . . . . ... . . . 1 . .. .. .. .. . . . . . ..1.1....1 1.. . | +-- 718 | 1-10-----1 | 1..111....1...1.....1.....1..... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 719 | 0-1100000- | .1.1.1....................11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 720 | 01-100000- | ..111.....1.......11..11..11..11 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 721 | -1-010000- | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . . . 11...111.1 ... . | +-- 722 | 000110000- | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . 1 . ...1.1111. ... . | +-- 723 | 01-110000- | ................................ . . . . ... 1 . 1 . . .1 .. .. .. . . . . . .......... ... . | +-- 724 | -010-0000- | ................................ . . . . ... . . . . . .1 .. .. .. . . . . . .......... ... . | +-- 725 | 1--11-000- | ................................ . 1 . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 726 | 011-1-000- | .1.1.1.........1.............11. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 727 | -0-000100- | ................................ . . . . ... . . . . . .. .1 .. .1 1 . . . . .......... ... . | +-- 728 | 01-100100- | ..111.....1.........1111....1111 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 729 | 1-1-00100- | 1..111....1........1....11111.1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 730 | 11--00100- | ................................ . . . . ... 1 1 1 1 . .. .. .. .. . . . . . 11.1...11. ... . | +-- 731 | 0-1101100- | ..........1...1..........1..1... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 732 | 01-101100- | ................................ . . . . ... . . . . . .1 .. .. .. . . . . . .......... ... . | +-- 733 | 100-11100- | .11.1....1...................... 1 . . . ... . 1 . . . .. 1. .. .. . . . . . .......... ... . | +-- 734 | 1--0-1100- | ................................ . 1 . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 735 | 0----1100- | ................................ . . . . ... 1 . 1 . . .. .. .. .. . . . . . .....1.... ... . | +-- 736 | -0100-100- | .1.1..........1.1...........111. . . . . ... . . . . . .. .. .. .. . . . 1 . .......... ... . | +-- 737 | -01000-00- | ................................ . . . . ... . . 1 . . .. .. .. .. . . . 1 . .......... ... . | +-- 738 | 11-000-00- | ................................ . . . . ... . . . . . .. .. .. .. . . . 1 . .......... ... . | +-- 739 | 000001-00- | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . 1 . .......... ... . | +-- 740 | 0-1011-00- | ................................ . . . . ... . . . . . .. .. .. .. . . . 1 . ..1.1.111. ... . | +-- 741 | 0--111-00- | ................................ . . . . ... . 1 . . . .. .. .. .. . . . . . .......... ... . | +-- 742 | 110-11-00- | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . 1 . 11..1.111. ... . | +-- 743 | --1-11-00- | ................................ . . . 1 ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 744 | ---0---00- | ................................ . . . . 1.1 . . . . . .. .. .. .. . . . . . .......... ... . | +-- 745 | 0-1100010- | .1...1...1....1.........11.1.... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 746 | 0-0-00010- | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . . . .......... ... . | +-- 747 | 00-010010- | ................................ . . . . ... . . . . . .. .. .. .. . . . 1 . ..1.1...1. ... . | +-- 748 | 0000-0010- | ................................ . . . . ... . . . . . .. .. .. .. . . . 1 . .......... ... . | +-- 749 | 11-001010- | ................................ . . . . ... . . 1 . . .. .. .. .. . . . 1 . .......... ... . | +-- 750 | -1-1-1010- | ................................ . 1 . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 751 | 01001-010- | ..111....1..........1111....1111 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 752 | 101---010- | ..111..........................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 753 | 010000110- | ..111....1..........1111....1111 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 754 | 1--000110- | ................................ . 1 . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 755 | 110100110- | .1.1.1....1...1...........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 756 | 0-0-01110- | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . . . ...1.11.1. ... . | +-- 757 | -100-1110- | ................................ . . . . ... 1 1 . . . .. .. .. .. . . . . . .......... ... . | +-- 758 | 00011-110- | ................................ . . . . ... 1 1 . . . .. .. .. .. . . . 1 . .......... ... . | +-- 759 | 10011-110- | ..111..........................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 760 | 10-100-10- | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . . . 1..1..1..1 ... . | +-- 761 | ----01-10- | ................................ . . . . 1.1 . . . . . .. .. .. .. . . . . . .......... ... . | +-- 762 | 000111-10- | .1.1.1........1.1...........111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 763 | 11-111-10- | 1...11....1........11...1.111.1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 764 | 0-10-1-10- | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . . . .....1.... ... . | +-- 765 | 0-1-010-0- | ................................ . . . . ... 1 1 . . . .. .. .. .. . . . . . .......1.. ... . | +-- 766 | -110110-0- | ................................ . . . . ... 1 . . . . .. .. .1 .. . . . . . .......... ... . | +-- 767 | 01-1-10-0- | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . . . .......... ... . | +-- 768 | 11-00-0-0- | ................................ . . . . ... 1 1 . . . .. .. .. .. . . . . . .......... ... . | +-- 769 | 0-0-1-0-0- | ................................ . . . 1 ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 770 | -010001-0- | .1.1..........1.1...........111. . . . . ... . . 1 . . .. .. .. .. . . . 1 . .......... ... . | +-- 771 | 1001-11-0- | ................................ . . . . ... 1 1 . 1 . .. .. .. .. . . . . . 1..1.1.1.1 ... . | +-- 772 | 0--0-0--0- | ................................ . . . . ... 1 . . . . .. .. .. .. . . . . . .......... ... . | +-- 773 | --0111--0- | ................................ . . . 1 ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 774 | -01000001- | ..111..........................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 775 | 110100001- | ................................ . . . . ... 1 1 . . . .. .. .. .. . . . 1 . .......... ... . | +-- 776 | -01010001- | ................................ . . . . ... 1 1 . . . .. .. .. .. . . . 1 . .......... 1.1 . | +-- 777 | 11-010001- | ................................ . . . . ... 1 1 . . . .. .. .. .. . . . 1 . 11..1....1 ... . | +-- 778 | 10--10001- | ................................ 1 . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 779 | 0-00-0001- | ................................ . . . . ... . 1 1 . . .. .. .. .. . . . . . .......... ... . | +-- 780 | 10-0-0001- | ................................ . . . . ... . . . . . .. .1 .. .. . . . . . .......... ... . | +-- 781 | -0-1-0001- | ................................ . 1 . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 782 | -0-001001- | ................................ . 1 . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 783 | -0--01001- | ................................ . . . 1 ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 784 | 000-11001- | ................................ 1 . . . ... . . . . . 1. .1 .1 .1 1 1 . . . .......... ... . | +-- 785 | -1--11001- | .11............................. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 786 | 0001-1001- | ................................ . . . . ... . . . . . .. .. .. .. . . . 1 . .......... ... . | +-- 787 | -00100101- | ..111..........................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 788 | 0001-0101- | ................................ . . . . ... 1 1 . . . .. .. .. .. . . . 1 . .......... 1.. . | +-- 789 | 00-011101- | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . 1 . .......... ... . | +-- 790 | 100-11101- | ..111....1...................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 791 | 01---1101- | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . . . .......... ... . | +-- 792 | 1-1-0-101- | 1..111...................11111.. . . . . ... 1 . . 1 . .. 1. 11 .. . . . . . .......... ... . | +-- 793 | -1--0-101- | ................................ . . . 1 ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 794 | --1-1-101- | ................................ . 1 . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 795 | -00001-01- | .11.1........................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 796 | 0-0001-01- | ................................ . 1 . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 797 | ---111-01- | ................................ . 1 . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 798 | 1-01-1-01- | ................................ . . . . ... 1 1 . . . .. .. .. .. . . . . . 1..1.1.... ... . | +-- 799 | 10-00--01- | ..1............................. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 800 | 000100011- | ................................ . . . . ... . . . . . .. .. .. .. . . . 1 . .......... ... . | +-- 801 | 0000-0011- | .11.1........................... . . . . ... . 1 . . . .. .1 .. .. . . . . . .......... ... . | +-- 802 | -000-0011- | ................................ . 1 . 1 ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 803 | 10-1-0011- | ..111..........................1 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 804 | ---1-0011- | ................................ . . . . ... 1 1 . 1 . .. .. .. .. . . . . . .......... ... . | +-- 805 | 010-01011- | .11111..............1.....111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 806 | 0-00-1011- | ................................ . . . . ... 1 1 . . . .. .. .. .. . . . . . .......... ... . | +-- 807 | 01000-011- | ..111....1........11..11..11..11 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 808 | -1-01-011- | ................................ . 1 . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 809 | -1--1-011- | ................................ . . . 1 ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 810 | 1---00111- | ................................ . . . 1 ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 811 | 00-010111- | ................................ . . . . ... 1 1 . . . .. .. .. .. . . . 1 . .......... 1.1 . | +-- 812 | 01-010111- | .11111.............1......111... 1 . . . ... . 1 1 . . .. .1 .. .. . . . . . .......... ... . | +-- 813 | ---110111- | ................................ . 1 . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 814 | 11--10111- | ................................ . . . . ... . . . . . .. .. .. .. . . . 1 . .......... ... . | +-- 815 | 1101-0111- | ................................ . . . . ... . . . . . .. .. .. .. . . . 1 . .......... ... . | +-- 816 | 000101111- | ................................ . . . . ... 1 1 . . . .. .. .. .. . . . 1 . .......... 1.. . | +-- 817 | 01-101111- | .1111................111111..... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 818 | --1-11111- | .....1........1....11....1.1.... 1 . . . ... . . . . . 1. .. .. .. . 1 . . . .......... ... . | +-- 819 | -11--1111- | .11111....1........1..11.1111... 1 . . . ... . . 1 . . .. .1 .. .. . . . . . .......... ... . | +-- 820 | --1--1111- | ................................ . 1 . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 821 | -111--111- | ................................ 1 . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 822 | 101--0-11- | ................................ . . . . ... . . 1 . . .. .. .. .. . . . 1 . .......... ... . | +-- 823 | 010001-11- | ..111....1........11..11..11..11 . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 824 | 01-101-11- | ................................ 1 . . . ... . 1 1 . . .. .1 .. .. . . . . . .......... ... . | +-- 825 | 1-1-01-11- | ................................ . . . . ... . . . . . .. 1. 11 .. . . . . . .......... ... . | +-- 826 | 1-0-11-11- | ................................ . . . . ... 1 1 . 1 . .. .. .. .. . . . . . .......1.. ... . | +-- 827 | --1-11-11- | ................................ . 1 . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 828 | ---0-1-11- | ................................ . . . . ..1 . . . . . .. .. .. .. . . . . . .......... ... . | +-- 829 | -111-1-11- | 1...11.........1.........11111.. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 830 | 011----11- | ................................ . . . . ... . 1 . . . .. .. .. .. . . . . . .......... ... . | +-- 831 | 1-1-000-1- | 1..111.........1..........11..1. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 832 | 01--100-1- | ................................ . . . . ... . 1 . . . .. .. .. .. . . . . . .......... ... . | +-- 833 | 10-0110-1- | ................................ . . . . ... 1 1 . . . .. .. .. .. . . . . . .......... ... . | +-- 834 | 01-0--0-1- | ................................ . . . . ... 1 . . . . .. .. .. .. . . . . . .......... ... . | +-- 835 | 010-001-1- | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . . . .......... ... . | +-- 836 | 111-101-1- | ................................ . . . . ... . . . . . .. .. .1 .. . . . . . .......... ... . | +-- 837 | 1---101-1- | ................................ . . . . ... 1 1 . 1 . .. .. .. .. . . . . . 11.11.1..1 ... . | +-- 838 | -----01-1- | ................................ . . . . .11 . . . . . .. .. .. .. . . . . . .......... ... . | +-- 839 | -000011-1- | ................................ . . . . ... . . . . . .. .1 .. .. . . . . . .......... ... . | +-- 840 | 11-1111-1- | ................................ 1 . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 841 | 01--111-1- | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . . . .......... ... . | +-- 842 | 101--11-1- | ................................ . . . . ... . 1 1 . . .. .. .. .. . . . 1 . .......... ... . | +-- 843 | 10-00-1-1- | ................................ 1 . . . ... . 1 . . . .. .1 .. .. . . . . . .......... ... . | +-- 844 | -1101-1-1- | ................................ 1 . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 845 | 011-1-1-1- | .11111...1.....1......111.1..11. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 846 | -00010--1- | ................................ . . . . ... . 1 . . . .. .. .. .. . . . . . .......... ... . | +-- 847 | 10-001--1- | .11.1........................... 1 . . . ... . 1 . . . .. .1 .. .. . . . . . .......... ... . | +-- 848 | -1--11--1- | ................................ . . . 1 ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 849 | 1-011---1- | ................................ . . . . ... 1 1 . . . .. .. .. .. . . . . . .......... ... . | +-- 850 | 0-11----1- | ................................ . . . . ... . 1 1 . . .. .. .. .. . . . . . .......... ... . | +-- 851 | 10-01000-- | .11.1........................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 852 | -110-000-- | ................................ . . . . ... . 1 . . . .. .. .. .. . . . . . .......... ... . | +-- 853 | 00011100-- | .11111.........1......1....1.1.. 1 . . . ... . . 1 . . 1. .. .. .. . . . . . .......... ... . | +-- 854 | 00000010-- | .11111....................111... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 855 | -0100010-- | .1.1.1........1...........11111. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 856 | 00-00010-- | ................................ . . . . ... 1 . . . . .1 .. .. .. . . . . . .......... ... . | +-- 857 | --101110-- | 1..111....1...............1..... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 858 | 1101-110-- | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . 1 . .1....1... ... . | +-- 859 | 100110-0-- | ................................ . . . . ... 1 1 . . . .. .. .. .. . . . . . .......... ... . | +-- 860 | 0-00-0-0-- | ................................ . . . . ... 1 . . . . .. .. .. .. . . . . . .......... ... . | +-- 861 | -1--11-0-- | ................................ . . . 1 ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 862 | -0100101-- | .1.1.1........1...........11111. . . . . ... 1 . . . . .1 .. .. .. . . . . . .......... ... . | +-- 863 | 100-1101-- | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . . . 1...11..1. ... . | +-- 864 | -0011-01-- | ................................ . . . . ... 1 . . . . .. .. .. .. . . . . . ...1...... 1.. . | +-- 865 | 11011-01-- | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . 1 . 11.11..1.. ... . | +-- 866 | --11--01-- | ................................ . . . . ... 1 . . 1 . .. .. .. .. . . . . . .......... ... . | +-- 867 | -1010011-- | ................................ . . . . ... 1 1 1 . . .. .. .. .. . . . . . .......... ... . | +-- 868 | 10-01011-- | ................................ . . . . ... . 1 1 . . .. .. .. .. . . . . . .......... ... . | +-- 869 | --110111-- | .1111........................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 870 | -0011111-- | .1.1.1........1.11........11111. . . . . ... 1 . . . . .1 .. .. .. . . . . . .......... ... . | +-- 871 | 1--11111-- | .11............................. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 872 | -1101-11-- | 1...11....1...............1..... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 873 | -1-11-11-- | ................................ . 1 . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 874 | 0--11-11-- | ................................ . . . 1 ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 875 | ---110-1-- | ................................ . . . . 11. . . . . . .. .. .. .. . . . . . .......... ... . | +-- 876 | 0-0001-1-- | ................................ . . . . ... 1 . 1 . . .. .. .. .. . . . . . .......... ... . | +-- 877 | 0000100--- | ................................ . . . . ... . 1 . . . .. .. .. .. . . . . . .......... ... . | +-- 878 | 0100-10--- | .11111.............1......111... 1 . . . ... . 1 1 . . .. .1 .. .. . . . . . .......... ... . | +-- 879 | ----0-0--- | ................................ . . . . 1.. . . . . . .. .. .. .. . . . . . .......... ... . | +-- 880 | ----111--- | ................................ . . . . 11. . . . . . .. .. .. .. . . . . . .......... ... . | +-- 881 | 11011-1--- | ..111........................... . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 882 | ----00---- | ................................ . . . . .1. . . . . . .. .. .. .. . . . . . .......... ... . | +-- 883 | ---0-0---- | ................................ . . . . 1.. . . . . . .. .. .. .. . . . . . .......... ... . | +-- 884 | 0-11-0---- | ................................ . . . . ... 1 . . . . .. .. .. .. . . . . . .......... ... . | +-- 885 | 011--0---- | ................................ . . . . ... 1 . 1 . . .. .. .. .. . . . . . .......... ... . | +-- 886 | ---111---- | ................................ . . . . .1. . . . . . .. .. .. .. . . . . . .......... ... . | +-- 887 | 0--00----- | ................................ . . . . ... . . . 1 . .. .. .. .. . . . . . ..1...1.11 ... . | +-- 888 | 0-111----- | ................................ . . . . ... . 1 . . . .. .. .. .. . . . . . .......... ... . | +-- 889 | 111------- | .11............................. . . . . ... . . . . . .. .. .. .. . . . . . .......... ... . | +-- 890 | --1------- | ................................ . . . . 1.1 . . . . . .. .. .. .. . . . . . .......... ... . | +-- 891 | -1-------- | ................................ . . . . 111 . . . . . .. .. .. .. . . . . . .......... ... . | +-- 892 | 0--------- | ................................ . . . . 111 . . . . . .. .. .. .. . . . . . .......... ... . | +-- 893 | ---------- | ................................ . . . . ... . . . . . .. .. .. .. . . . . . .......... .1. . | +-- *=======================================================================================================================* +-- +-- Table ROM32_INSTR Signal Assignments for Product Terms +MQQ962:ROM32_INSTR_PT(1) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("100000000")); +MQQ963:ROM32_INSTR_PT(2) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011000000")); +MQQ964:ROM32_INSTR_PT(3) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("101000000")); +MQQ965:ROM32_INSTR_PT(4) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000000000")); +MQQ966:ROM32_INSTR_PT(5) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110000000")); +MQQ967:ROM32_INSTR_PT(6) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011000000")); +MQQ968:ROM32_INSTR_PT(7) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00100000")); +MQQ969:ROM32_INSTR_PT(8) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001100000")); +MQQ970:ROM32_INSTR_PT(9) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011100000")); +MQQ971:ROM32_INSTR_PT(10) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01100000")); +MQQ972:ROM32_INSTR_PT(11) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00000000")); +MQQ973:ROM32_INSTR_PT(12) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11000000")); +MQQ974:ROM32_INSTR_PT(13) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001010000")); +MQQ975:ROM32_INSTR_PT(14) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011010000")); +MQQ976:ROM32_INSTR_PT(15) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("101010000")); +MQQ977:ROM32_INSTR_PT(16) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000110000")); +MQQ978:ROM32_INSTR_PT(17) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10110000")); +MQQ979:ROM32_INSTR_PT(18) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011110000")); +MQQ980:ROM32_INSTR_PT(19) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10110000")); +MQQ981:ROM32_INSTR_PT(20) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110000")); +MQQ982:ROM32_INSTR_PT(21) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000010000")); +MQQ983:ROM32_INSTR_PT(22) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110000")); +MQQ984:ROM32_INSTR_PT(23) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110000")); +MQQ985:ROM32_INSTR_PT(24) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11000000")); +MQQ986:ROM32_INSTR_PT(25) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000100000")); +MQQ987:ROM32_INSTR_PT(26) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010010000")); +MQQ988:ROM32_INSTR_PT(27) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10010000")); +MQQ989:ROM32_INSTR_PT(28) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110000")); +MQQ990:ROM32_INSTR_PT(29) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110000")); +MQQ991:ROM32_INSTR_PT(30) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1110000")); +MQQ992:ROM32_INSTR_PT(31) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10010000")); +MQQ993:ROM32_INSTR_PT(32) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1010000")); +MQQ994:ROM32_INSTR_PT(33) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1110000")); +MQQ995:ROM32_INSTR_PT(34) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000001000")); +MQQ996:ROM32_INSTR_PT(35) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10001000")); +MQQ997:ROM32_INSTR_PT(36) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("101001000")); +MQQ998:ROM32_INSTR_PT(37) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110001000")); +MQQ999:ROM32_INSTR_PT(38) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01001000")); +MQQ1000:ROM32_INSTR_PT(39) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("100101000")); +MQQ1001:ROM32_INSTR_PT(40) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110101000")); +MQQ1002:ROM32_INSTR_PT(41) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001101000")); +MQQ1003:ROM32_INSTR_PT(42) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011101000")); +MQQ1004:ROM32_INSTR_PT(43) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011101000")); +MQQ1005:ROM32_INSTR_PT(44) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000101000")); +MQQ1006:ROM32_INSTR_PT(45) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("111101000")); +MQQ1007:ROM32_INSTR_PT(46) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000001000")); +MQQ1008:ROM32_INSTR_PT(47) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1101000")); +MQQ1009:ROM32_INSTR_PT(48) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001011000")); +MQQ1010:ROM32_INSTR_PT(49) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011011000")); +MQQ1011:ROM32_INSTR_PT(50) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011011000")); +MQQ1012:ROM32_INSTR_PT(51) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000111000")); +MQQ1013:ROM32_INSTR_PT(52) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110111000")); +MQQ1014:ROM32_INSTR_PT(53) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01111000")); +MQQ1015:ROM32_INSTR_PT(54) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010011000")); +MQQ1016:ROM32_INSTR_PT(55) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110111000")); +MQQ1017:ROM32_INSTR_PT(56) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10111000")); +MQQ1018:ROM32_INSTR_PT(57) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01111000")); +MQQ1019:ROM32_INSTR_PT(58) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("111000")); +MQQ1020:ROM32_INSTR_PT(59) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010001000")); +MQQ1021:ROM32_INSTR_PT(60) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01001000")); +MQQ1022:ROM32_INSTR_PT(61) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000011000")); +MQQ1023:ROM32_INSTR_PT(62) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00011000")); +MQQ1024:ROM32_INSTR_PT(63) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("100111000")); +MQQ1025:ROM32_INSTR_PT(64) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110111000")); +MQQ1026:ROM32_INSTR_PT(65) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000000000")); +MQQ1027:ROM32_INSTR_PT(66) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10000000")); +MQQ1028:ROM32_INSTR_PT(67) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01000000")); +MQQ1029:ROM32_INSTR_PT(68) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10000000")); +MQQ1030:ROM32_INSTR_PT(69) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10010000")); +MQQ1031:ROM32_INSTR_PT(70) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1010000")); +MQQ1032:ROM32_INSTR_PT(71) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110000")); +MQQ1033:ROM32_INSTR_PT(72) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1010000")); +MQQ1034:ROM32_INSTR_PT(73) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000001000")); +MQQ1035:ROM32_INSTR_PT(74) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01011000")); +MQQ1036:ROM32_INSTR_PT(75) <= + Eq(( ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000")); +MQQ1037:ROM32_INSTR_PT(76) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001000100")); +MQQ1038:ROM32_INSTR_PT(77) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("1101000100")); +MQQ1039:ROM32_INSTR_PT(78) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011000100")); +MQQ1040:ROM32_INSTR_PT(79) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011000100")); +MQQ1041:ROM32_INSTR_PT(80) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011000100")); +MQQ1042:ROM32_INSTR_PT(81) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10000100")); +MQQ1043:ROM32_INSTR_PT(82) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110100100")); +MQQ1044:ROM32_INSTR_PT(83) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001100100")); +MQQ1045:ROM32_INSTR_PT(84) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011100100")); +MQQ1046:ROM32_INSTR_PT(85) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11100100")); +MQQ1047:ROM32_INSTR_PT(86) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10100100")); +MQQ1048:ROM32_INSTR_PT(87) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000000100")); +MQQ1049:ROM32_INSTR_PT(88) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10000100")); +MQQ1050:ROM32_INSTR_PT(89) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110100100")); +MQQ1051:ROM32_INSTR_PT(90) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110010100")); +MQQ1052:ROM32_INSTR_PT(91) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001010100")); +MQQ1053:ROM32_INSTR_PT(92) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010010100")); +MQQ1054:ROM32_INSTR_PT(93) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01010100")); +MQQ1055:ROM32_INSTR_PT(94) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000110100")); +MQQ1056:ROM32_INSTR_PT(95) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10110100")); +MQQ1057:ROM32_INSTR_PT(96) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000110100")); +MQQ1058:ROM32_INSTR_PT(97) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110100")); +MQQ1059:ROM32_INSTR_PT(98) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00010100")); +MQQ1060:ROM32_INSTR_PT(99) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000110100")); +MQQ1061:ROM32_INSTR_PT(100) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110100")); +MQQ1062:ROM32_INSTR_PT(101) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110100")); +MQQ1063:ROM32_INSTR_PT(102) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010000100")); +MQQ1064:ROM32_INSTR_PT(103) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01000100")); +MQQ1065:ROM32_INSTR_PT(104) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10010100")); +MQQ1066:ROM32_INSTR_PT(105) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110100")); +MQQ1067:ROM32_INSTR_PT(106) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1010100")); +MQQ1068:ROM32_INSTR_PT(107) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1110100")); +MQQ1069:ROM32_INSTR_PT(108) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001001100")); +MQQ1070:ROM32_INSTR_PT(109) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("001001100")); +MQQ1071:ROM32_INSTR_PT(110) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11001100")); +MQQ1072:ROM32_INSTR_PT(111) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011001100")); +MQQ1073:ROM32_INSTR_PT(112) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11001100")); +MQQ1074:ROM32_INSTR_PT(113) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000101100")); +MQQ1075:ROM32_INSTR_PT(114) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("100101100")); +MQQ1076:ROM32_INSTR_PT(115) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010101100")); +MQQ1077:ROM32_INSTR_PT(116) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110101100")); +MQQ1078:ROM32_INSTR_PT(117) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011101100")); +MQQ1079:ROM32_INSTR_PT(118) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01101100")); +MQQ1080:ROM32_INSTR_PT(119) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01101100")); +MQQ1081:ROM32_INSTR_PT(120) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110011100")); +MQQ1082:ROM32_INSTR_PT(121) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11011100")); +MQQ1083:ROM32_INSTR_PT(122) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011011100")); +MQQ1084:ROM32_INSTR_PT(123) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11111100")); +MQQ1085:ROM32_INSTR_PT(124) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110111100")); +MQQ1086:ROM32_INSTR_PT(125) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01111100")); +MQQ1087:ROM32_INSTR_PT(126) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11111100")); +MQQ1088:ROM32_INSTR_PT(127) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000011100")); +MQQ1089:ROM32_INSTR_PT(128) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000111100")); +MQQ1090:ROM32_INSTR_PT(129) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11111100")); +MQQ1091:ROM32_INSTR_PT(130) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01111100")); +MQQ1092:ROM32_INSTR_PT(131) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10001100")); +MQQ1093:ROM32_INSTR_PT(132) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11101100")); +MQQ1094:ROM32_INSTR_PT(133) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1101100")); +MQQ1095:ROM32_INSTR_PT(134) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000111100")); +MQQ1096:ROM32_INSTR_PT(135) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10111100")); +MQQ1097:ROM32_INSTR_PT(136) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("011100")); +MQQ1098:ROM32_INSTR_PT(137) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0100100")); +MQQ1099:ROM32_INSTR_PT(138) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11010100")); +MQQ1100:ROM32_INSTR_PT(139) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1010100")); +MQQ1101:ROM32_INSTR_PT(140) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000001100")); +MQQ1102:ROM32_INSTR_PT(141) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010001100")); +MQQ1103:ROM32_INSTR_PT(142) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1101100")); +MQQ1104:ROM32_INSTR_PT(143) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01011100")); +MQQ1105:ROM32_INSTR_PT(144) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01111100")); +MQQ1106:ROM32_INSTR_PT(145) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0101100")); +MQQ1107:ROM32_INSTR_PT(146) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1001100")); +MQQ1108:ROM32_INSTR_PT(147) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11000000")); +MQQ1109:ROM32_INSTR_PT(148) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01010000")); +MQQ1110:ROM32_INSTR_PT(149) <= + Eq(( ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("010000")); +MQQ1111:ROM32_INSTR_PT(150) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01001000")); +MQQ1112:ROM32_INSTR_PT(151) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1001000")); +MQQ1113:ROM32_INSTR_PT(152) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("1000")); +MQQ1114:ROM32_INSTR_PT(153) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000000100")); +MQQ1115:ROM32_INSTR_PT(154) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01000100")); +MQQ1116:ROM32_INSTR_PT(155) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10100100")); +MQQ1117:ROM32_INSTR_PT(156) <= + Eq(( ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("00100")); +MQQ1118:ROM32_INSTR_PT(157) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("010100")); +MQQ1119:ROM32_INSTR_PT(158) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01111100")); +MQQ1120:ROM32_INSTR_PT(159) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11111100")); +MQQ1121:ROM32_INSTR_PT(160) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10011100")); +MQQ1122:ROM32_INSTR_PT(161) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1111100")); +MQQ1123:ROM32_INSTR_PT(162) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10011100")); +MQQ1124:ROM32_INSTR_PT(163) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0111100")); +MQQ1125:ROM32_INSTR_PT(164) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1000100")); +MQQ1126:ROM32_INSTR_PT(165) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0101100")); +MQQ1127:ROM32_INSTR_PT(166) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1101100")); +MQQ1128:ROM32_INSTR_PT(167) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("01100")); +MQQ1129:ROM32_INSTR_PT(168) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("10100")); +MQQ1130:ROM32_INSTR_PT(169) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("1101000010")); +MQQ1131:ROM32_INSTR_PT(170) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011000010")); +MQQ1132:ROM32_INSTR_PT(171) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("101000010")); +MQQ1133:ROM32_INSTR_PT(172) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011000010")); +MQQ1134:ROM32_INSTR_PT(173) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110100010")); +MQQ1135:ROM32_INSTR_PT(174) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011100010")); +MQQ1136:ROM32_INSTR_PT(175) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000000010")); +MQQ1137:ROM32_INSTR_PT(176) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1100010")); +MQQ1138:ROM32_INSTR_PT(177) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010010010")); +MQQ1139:ROM32_INSTR_PT(178) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10110010")); +MQQ1140:ROM32_INSTR_PT(179) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("001110010")); +MQQ1141:ROM32_INSTR_PT(180) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11110010")); +MQQ1142:ROM32_INSTR_PT(181) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110010")); +MQQ1143:ROM32_INSTR_PT(182) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11010010")); +MQQ1144:ROM32_INSTR_PT(183) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11010010")); +MQQ1145:ROM32_INSTR_PT(184) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000110010")); +MQQ1146:ROM32_INSTR_PT(185) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110010")); +MQQ1147:ROM32_INSTR_PT(186) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110010")); +MQQ1148:ROM32_INSTR_PT(187) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010000010")); +MQQ1149:ROM32_INSTR_PT(188) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11000010")); +MQQ1150:ROM32_INSTR_PT(189) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01100010")); +MQQ1151:ROM32_INSTR_PT(190) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1100010")); +MQQ1152:ROM32_INSTR_PT(191) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("000010")); +MQQ1153:ROM32_INSTR_PT(192) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010010010")); +MQQ1154:ROM32_INSTR_PT(193) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000110010")); +MQQ1155:ROM32_INSTR_PT(194) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110010")); +MQQ1156:ROM32_INSTR_PT(195) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1110010")); +MQQ1157:ROM32_INSTR_PT(196) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110010")); +MQQ1158:ROM32_INSTR_PT(197) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11110010")); +MQQ1159:ROM32_INSTR_PT(198) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1010010")); +MQQ1160:ROM32_INSTR_PT(199) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000001010")); +MQQ1161:ROM32_INSTR_PT(200) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10001010")); +MQQ1162:ROM32_INSTR_PT(201) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("1101001010")); +MQQ1163:ROM32_INSTR_PT(202) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("001001010")); +MQQ1164:ROM32_INSTR_PT(203) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011001010")); +MQQ1165:ROM32_INSTR_PT(204) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10001010")); +MQQ1166:ROM32_INSTR_PT(205) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0100101010")); +MQQ1167:ROM32_INSTR_PT(206) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011101010")); +MQQ1168:ROM32_INSTR_PT(207) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011101010")); +MQQ1169:ROM32_INSTR_PT(208) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110101010")); +MQQ1170:ROM32_INSTR_PT(209) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000101010")); +MQQ1171:ROM32_INSTR_PT(210) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10101010")); +MQQ1172:ROM32_INSTR_PT(211) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00001010")); +MQQ1173:ROM32_INSTR_PT(212) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110011010")); +MQQ1174:ROM32_INSTR_PT(213) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10011010")); +MQQ1175:ROM32_INSTR_PT(214) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11011010")); +MQQ1176:ROM32_INSTR_PT(215) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011011010")); +MQQ1177:ROM32_INSTR_PT(216) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00111010")); +MQQ1178:ROM32_INSTR_PT(217) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10111010")); +MQQ1179:ROM32_INSTR_PT(218) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011111010")); +MQQ1180:ROM32_INSTR_PT(219) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10111010")); +MQQ1181:ROM32_INSTR_PT(220) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01111010")); +MQQ1182:ROM32_INSTR_PT(221) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01011010")); +MQQ1183:ROM32_INSTR_PT(222) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("100111010")); +MQQ1184:ROM32_INSTR_PT(223) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110111010")); +MQQ1185:ROM32_INSTR_PT(224) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01111010")); +MQQ1186:ROM32_INSTR_PT(225) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000101010")); +MQQ1187:ROM32_INSTR_PT(226) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01011010")); +MQQ1188:ROM32_INSTR_PT(227) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10011010")); +MQQ1189:ROM32_INSTR_PT(228) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000100010")); +MQQ1190:ROM32_INSTR_PT(229) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01100010")); +MQQ1191:ROM32_INSTR_PT(230) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1010010")); +MQQ1192:ROM32_INSTR_PT(231) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000001010")); +MQQ1193:ROM32_INSTR_PT(232) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010001010")); +MQQ1194:ROM32_INSTR_PT(233) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1101010")); +MQQ1195:ROM32_INSTR_PT(234) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011010")); +MQQ1196:ROM32_INSTR_PT(235) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01011010")); +MQQ1197:ROM32_INSTR_PT(236) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("011010")); +MQQ1198:ROM32_INSTR_PT(237) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110000110")); +MQQ1199:ROM32_INSTR_PT(238) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001000110")); +MQQ1200:ROM32_INSTR_PT(239) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("1101000110")); +MQQ1201:ROM32_INSTR_PT(240) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11000110")); +MQQ1202:ROM32_INSTR_PT(241) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("101000110")); +MQQ1203:ROM32_INSTR_PT(242) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("111000110")); +MQQ1204:ROM32_INSTR_PT(243) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011000110")); +MQQ1205:ROM32_INSTR_PT(244) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0000100110")); +MQQ1206:ROM32_INSTR_PT(245) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("001100110")); +MQQ1207:ROM32_INSTR_PT(246) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000000110")); +MQQ1208:ROM32_INSTR_PT(247) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01000110")); +MQQ1209:ROM32_INSTR_PT(248) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10100110")); +MQQ1210:ROM32_INSTR_PT(249) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01100110")); +MQQ1211:ROM32_INSTR_PT(250) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110010110")); +MQQ1212:ROM32_INSTR_PT(251) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001010110")); +MQQ1213:ROM32_INSTR_PT(252) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011010110")); +MQQ1214:ROM32_INSTR_PT(253) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000110110")); +MQQ1215:ROM32_INSTR_PT(254) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110110")); +MQQ1216:ROM32_INSTR_PT(255) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("100110110")); +MQQ1217:ROM32_INSTR_PT(256) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110110")); +MQQ1218:ROM32_INSTR_PT(257) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110110")); +MQQ1219:ROM32_INSTR_PT(258) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1100110")); +MQQ1220:ROM32_INSTR_PT(259) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010010110")); +MQQ1221:ROM32_INSTR_PT(260) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("100110110")); +MQQ1222:ROM32_INSTR_PT(261) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110110")); +MQQ1223:ROM32_INSTR_PT(262) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110110")); +MQQ1224:ROM32_INSTR_PT(263) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1010110")); +MQQ1225:ROM32_INSTR_PT(264) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0100001110")); +MQQ1226:ROM32_INSTR_PT(265) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010001110")); +MQQ1227:ROM32_INSTR_PT(266) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110001110")); +MQQ1228:ROM32_INSTR_PT(267) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011001110")); +MQQ1229:ROM32_INSTR_PT(268) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011001110")); +MQQ1230:ROM32_INSTR_PT(269) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0000101110")); +MQQ1231:ROM32_INSTR_PT(270) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("100101110")); +MQQ1232:ROM32_INSTR_PT(271) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011101110")); +MQQ1233:ROM32_INSTR_PT(272) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11101110")); +MQQ1234:ROM32_INSTR_PT(273) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110101110")); +MQQ1235:ROM32_INSTR_PT(274) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01101110")); +MQQ1236:ROM32_INSTR_PT(275) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110011110")); +MQQ1237:ROM32_INSTR_PT(276) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11011110")); +MQQ1238:ROM32_INSTR_PT(277) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01011110")); +MQQ1239:ROM32_INSTR_PT(278) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11111110")); +MQQ1240:ROM32_INSTR_PT(279) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0111110")); +MQQ1241:ROM32_INSTR_PT(280) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11111110")); +MQQ1242:ROM32_INSTR_PT(281) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000011110")); +MQQ1243:ROM32_INSTR_PT(282) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01011110")); +MQQ1244:ROM32_INSTR_PT(283) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000111110")); +MQQ1245:ROM32_INSTR_PT(284) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10111110")); +MQQ1246:ROM32_INSTR_PT(285) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11111110")); +MQQ1247:ROM32_INSTR_PT(286) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000111110")); +MQQ1248:ROM32_INSTR_PT(287) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00111110")); +MQQ1249:ROM32_INSTR_PT(288) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1111110")); +MQQ1250:ROM32_INSTR_PT(289) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110110")); +MQQ1251:ROM32_INSTR_PT(290) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11110110")); +MQQ1252:ROM32_INSTR_PT(291) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("100110")); +MQQ1253:ROM32_INSTR_PT(292) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000001110")); +MQQ1254:ROM32_INSTR_PT(293) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01011110")); +MQQ1255:ROM32_INSTR_PT(294) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01011110")); +MQQ1256:ROM32_INSTR_PT(295) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00111110")); +MQQ1257:ROM32_INSTR_PT(296) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1101110")); +MQQ1258:ROM32_INSTR_PT(297) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11011110")); +MQQ1259:ROM32_INSTR_PT(298) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1111110")); +MQQ1260:ROM32_INSTR_PT(299) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("101110")); +MQQ1261:ROM32_INSTR_PT(300) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01000010")); +MQQ1262:ROM32_INSTR_PT(301) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110010")); +MQQ1263:ROM32_INSTR_PT(302) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00011010")); +MQQ1264:ROM32_INSTR_PT(303) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10011010")); +MQQ1265:ROM32_INSTR_PT(304) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10011010")); +MQQ1266:ROM32_INSTR_PT(305) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("101010")); +MQQ1267:ROM32_INSTR_PT(306) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000000110")); +MQQ1268:ROM32_INSTR_PT(307) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00000110")); +MQQ1269:ROM32_INSTR_PT(308) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11010110")); +MQQ1270:ROM32_INSTR_PT(309) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11110110")); +MQQ1271:ROM32_INSTR_PT(310) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000001110")); +MQQ1272:ROM32_INSTR_PT(311) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0001110")); +MQQ1273:ROM32_INSTR_PT(312) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00111110")); +MQQ1274:ROM32_INSTR_PT(313) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011110")); +MQQ1275:ROM32_INSTR_PT(314) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00010110")); +MQQ1276:ROM32_INSTR_PT(315) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("101110")); +MQQ1277:ROM32_INSTR_PT(316) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("010010")); +MQQ1278:ROM32_INSTR_PT(317) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("011010")); +MQQ1279:ROM32_INSTR_PT(318) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011110")); +MQQ1280:ROM32_INSTR_PT(319) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0000010")); +MQQ1281:ROM32_INSTR_PT(320) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1000000")); +MQQ1282:ROM32_INSTR_PT(321) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01010000")); +MQQ1283:ROM32_INSTR_PT(322) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10101000")); +MQQ1284:ROM32_INSTR_PT(323) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01101000")); +MQQ1285:ROM32_INSTR_PT(324) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0101000")); +MQQ1286:ROM32_INSTR_PT(325) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1100000")); +MQQ1287:ROM32_INSTR_PT(326) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0000100")); +MQQ1288:ROM32_INSTR_PT(327) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11000100")); +MQQ1289:ROM32_INSTR_PT(328) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00000100")); +MQQ1290:ROM32_INSTR_PT(329) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00000100")); +MQQ1291:ROM32_INSTR_PT(330) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0100100")); +MQQ1292:ROM32_INSTR_PT(331) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1001100")); +MQQ1293:ROM32_INSTR_PT(332) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00101100")); +MQQ1294:ROM32_INSTR_PT(333) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("011100")); +MQQ1295:ROM32_INSTR_PT(334) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1000000")); +MQQ1296:ROM32_INSTR_PT(335) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1100010")); +MQQ1297:ROM32_INSTR_PT(336) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1100010")); +MQQ1298:ROM32_INSTR_PT(337) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10010010")); +MQQ1299:ROM32_INSTR_PT(338) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110010")); +MQQ1300:ROM32_INSTR_PT(339) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1010010")); +MQQ1301:ROM32_INSTR_PT(340) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01001010")); +MQQ1302:ROM32_INSTR_PT(341) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11001010")); +MQQ1303:ROM32_INSTR_PT(342) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1100110")); +MQQ1304:ROM32_INSTR_PT(343) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011110")); +MQQ1305:ROM32_INSTR_PT(344) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011110")); +MQQ1306:ROM32_INSTR_PT(345) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0101110")); +MQQ1307:ROM32_INSTR_PT(346) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1111110")); +MQQ1308:ROM32_INSTR_PT(347) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00011110")); +MQQ1309:ROM32_INSTR_PT(348) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011110")); +MQQ1310:ROM32_INSTR_PT(349) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("100110")); +MQQ1311:ROM32_INSTR_PT(350) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("011110")); +MQQ1312:ROM32_INSTR_PT(351) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1000000")); +MQQ1313:ROM32_INSTR_PT(352) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1101000")); +MQQ1314:ROM32_INSTR_PT(353) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1101100")); +MQQ1315:ROM32_INSTR_PT(354) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00000010")); +MQQ1316:ROM32_INSTR_PT(355) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("100010")); +MQQ1317:ROM32_INSTR_PT(356) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("110110")); +MQQ1318:ROM32_INSTR_PT(357) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0011110")); +MQQ1319:ROM32_INSTR_PT(358) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("100010")); +MQQ1320:ROM32_INSTR_PT(359) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001000001")); +MQQ1321:ROM32_INSTR_PT(360) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011000001")); +MQQ1322:ROM32_INSTR_PT(361) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110000001")); +MQQ1323:ROM32_INSTR_PT(362) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011000001")); +MQQ1324:ROM32_INSTR_PT(363) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011100001")); +MQQ1325:ROM32_INSTR_PT(364) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11100001")); +MQQ1326:ROM32_INSTR_PT(365) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000000001")); +MQQ1327:ROM32_INSTR_PT(366) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11000001")); +MQQ1328:ROM32_INSTR_PT(367) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000010001")); +MQQ1329:ROM32_INSTR_PT(368) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010010001")); +MQQ1330:ROM32_INSTR_PT(369) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000110001")); +MQQ1331:ROM32_INSTR_PT(370) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10110001")); +MQQ1332:ROM32_INSTR_PT(371) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("001110001")); +MQQ1333:ROM32_INSTR_PT(372) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00110001")); +MQQ1334:ROM32_INSTR_PT(373) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11110001")); +MQQ1335:ROM32_INSTR_PT(374) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110001")); +MQQ1336:ROM32_INSTR_PT(375) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10110001")); +MQQ1337:ROM32_INSTR_PT(376) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110001")); +MQQ1338:ROM32_INSTR_PT(377) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1110001")); +MQQ1339:ROM32_INSTR_PT(378) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010000001")); +MQQ1340:ROM32_INSTR_PT(379) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11000001")); +MQQ1341:ROM32_INSTR_PT(380) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0100001")); +MQQ1342:ROM32_INSTR_PT(381) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1100001")); +MQQ1343:ROM32_INSTR_PT(382) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010010001")); +MQQ1344:ROM32_INSTR_PT(383) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("100110001")); +MQQ1345:ROM32_INSTR_PT(384) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110001")); +MQQ1346:ROM32_INSTR_PT(385) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1010001")); +MQQ1347:ROM32_INSTR_PT(386) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000001001")); +MQQ1348:ROM32_INSTR_PT(387) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10001001")); +MQQ1349:ROM32_INSTR_PT(388) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("111001001")); +MQQ1350:ROM32_INSTR_PT(389) <= + Eq(( ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1001001")); +MQQ1351:ROM32_INSTR_PT(390) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01001001")); +MQQ1352:ROM32_INSTR_PT(391) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000101001")); +MQQ1353:ROM32_INSTR_PT(392) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0100101001")); +MQQ1354:ROM32_INSTR_PT(393) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110101001")); +MQQ1355:ROM32_INSTR_PT(394) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001101001")); +MQQ1356:ROM32_INSTR_PT(395) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011101001")); +MQQ1357:ROM32_INSTR_PT(396) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011101001")); +MQQ1358:ROM32_INSTR_PT(397) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("111101001")); +MQQ1359:ROM32_INSTR_PT(398) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110011001")); +MQQ1360:ROM32_INSTR_PT(399) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001011001")); +MQQ1361:ROM32_INSTR_PT(400) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011111001")); +MQQ1362:ROM32_INSTR_PT(401) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10111001")); +MQQ1363:ROM32_INSTR_PT(402) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000011001")); +MQQ1364:ROM32_INSTR_PT(403) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011001")); +MQQ1365:ROM32_INSTR_PT(404) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110111001")); +MQQ1366:ROM32_INSTR_PT(405) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01111001")); +MQQ1367:ROM32_INSTR_PT(406) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10111001")); +MQQ1368:ROM32_INSTR_PT(407) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10011001")); +MQQ1369:ROM32_INSTR_PT(408) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110111001")); +MQQ1370:ROM32_INSTR_PT(409) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10111001")); +MQQ1371:ROM32_INSTR_PT(410) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0011001")); +MQQ1372:ROM32_INSTR_PT(411) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01000001")); +MQQ1373:ROM32_INSTR_PT(412) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11000001")); +MQQ1374:ROM32_INSTR_PT(413) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01100001")); +MQQ1375:ROM32_INSTR_PT(414) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0010001")); +MQQ1376:ROM32_INSTR_PT(415) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1010001")); +MQQ1377:ROM32_INSTR_PT(416) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010001001")); +MQQ1378:ROM32_INSTR_PT(417) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01101001")); +MQQ1379:ROM32_INSTR_PT(418) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01011001")); +MQQ1380:ROM32_INSTR_PT(419) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01011001")); +MQQ1381:ROM32_INSTR_PT(420) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("1101000101")); +MQQ1382:ROM32_INSTR_PT(421) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("101000101")); +MQQ1383:ROM32_INSTR_PT(422) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011000101")); +MQQ1384:ROM32_INSTR_PT(423) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000000101")); +MQQ1385:ROM32_INSTR_PT(424) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011000101")); +MQQ1386:ROM32_INSTR_PT(425) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11000101")); +MQQ1387:ROM32_INSTR_PT(426) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110100101")); +MQQ1388:ROM32_INSTR_PT(427) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10100101")); +MQQ1389:ROM32_INSTR_PT(428) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001100101")); +MQQ1390:ROM32_INSTR_PT(429) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("001100101")); +MQQ1391:ROM32_INSTR_PT(430) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011100101")); +MQQ1392:ROM32_INSTR_PT(431) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11100101")); +MQQ1393:ROM32_INSTR_PT(432) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10100101")); +MQQ1394:ROM32_INSTR_PT(433) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110010101")); +MQQ1395:ROM32_INSTR_PT(434) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001010101")); +MQQ1396:ROM32_INSTR_PT(435) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("101010101")); +MQQ1397:ROM32_INSTR_PT(436) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01010101")); +MQQ1398:ROM32_INSTR_PT(437) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000110101")); +MQQ1399:ROM32_INSTR_PT(438) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110101")); +MQQ1400:ROM32_INSTR_PT(439) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110101")); +MQQ1401:ROM32_INSTR_PT(440) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110101")); +MQQ1402:ROM32_INSTR_PT(441) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110101")); +MQQ1403:ROM32_INSTR_PT(442) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010000101")); +MQQ1404:ROM32_INSTR_PT(443) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01000101")); +MQQ1405:ROM32_INSTR_PT(444) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1100101")); +MQQ1406:ROM32_INSTR_PT(445) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00010101")); +MQQ1407:ROM32_INSTR_PT(446) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110101")); +MQQ1408:ROM32_INSTR_PT(447) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1110101")); +MQQ1409:ROM32_INSTR_PT(448) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1010101")); +MQQ1410:ROM32_INSTR_PT(449) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0100001101")); +MQQ1411:ROM32_INSTR_PT(450) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110001101")); +MQQ1412:ROM32_INSTR_PT(451) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001001101")); +MQQ1413:ROM32_INSTR_PT(452) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011001101")); +MQQ1414:ROM32_INSTR_PT(453) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011101101")); +MQQ1415:ROM32_INSTR_PT(454) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011101101")); +MQQ1416:ROM32_INSTR_PT(455) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01001101")); +MQQ1417:ROM32_INSTR_PT(456) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11001101")); +MQQ1418:ROM32_INSTR_PT(457) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10101101")); +MQQ1419:ROM32_INSTR_PT(458) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01101101")); +MQQ1420:ROM32_INSTR_PT(459) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11011101")); +MQQ1421:ROM32_INSTR_PT(460) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11011101")); +MQQ1422:ROM32_INSTR_PT(461) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11111101")); +MQQ1423:ROM32_INSTR_PT(462) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000011101")); +MQQ1424:ROM32_INSTR_PT(463) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11011101")); +MQQ1425:ROM32_INSTR_PT(464) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000111101")); +MQQ1426:ROM32_INSTR_PT(465) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("100111101")); +MQQ1427:ROM32_INSTR_PT(466) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0111101")); +MQQ1428:ROM32_INSTR_PT(467) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11111101")); +MQQ1429:ROM32_INSTR_PT(468) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01100101")); +MQQ1430:ROM32_INSTR_PT(469) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000010101")); +MQQ1431:ROM32_INSTR_PT(470) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0010101")); +MQQ1432:ROM32_INSTR_PT(471) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000110101")); +MQQ1433:ROM32_INSTR_PT(472) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1010101")); +MQQ1434:ROM32_INSTR_PT(473) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00001101")); +MQQ1435:ROM32_INSTR_PT(474) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010001101")); +MQQ1436:ROM32_INSTR_PT(475) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01001101")); +MQQ1437:ROM32_INSTR_PT(476) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01011101")); +MQQ1438:ROM32_INSTR_PT(477) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11011101")); +MQQ1439:ROM32_INSTR_PT(478) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0111101")); +MQQ1440:ROM32_INSTR_PT(479) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11000001")); +MQQ1441:ROM32_INSTR_PT(480) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01010001")); +MQQ1442:ROM32_INSTR_PT(481) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10110001")); +MQQ1443:ROM32_INSTR_PT(482) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01001001")); +MQQ1444:ROM32_INSTR_PT(483) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10101001")); +MQQ1445:ROM32_INSTR_PT(484) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10011001")); +MQQ1446:ROM32_INSTR_PT(485) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000111001")); +MQQ1447:ROM32_INSTR_PT(486) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0111001")); +MQQ1448:ROM32_INSTR_PT(487) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11011001")); +MQQ1449:ROM32_INSTR_PT(488) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("011001")); +MQQ1450:ROM32_INSTR_PT(489) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000000101")); +MQQ1451:ROM32_INSTR_PT(490) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10100101")); +MQQ1452:ROM32_INSTR_PT(491) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11010101")); +MQQ1453:ROM32_INSTR_PT(492) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("100101")); +MQQ1454:ROM32_INSTR_PT(493) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("010101")); +MQQ1455:ROM32_INSTR_PT(494) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00111101")); +MQQ1456:ROM32_INSTR_PT(495) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10011101")); +MQQ1457:ROM32_INSTR_PT(496) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0111101")); +MQQ1458:ROM32_INSTR_PT(497) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0101101")); +MQQ1459:ROM32_INSTR_PT(498) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0001101")); +MQQ1460:ROM32_INSTR_PT(499) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0000001")); +MQQ1461:ROM32_INSTR_PT(500) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("001")); +MQQ1462:ROM32_INSTR_PT(501) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010000011")); +MQQ1463:ROM32_INSTR_PT(502) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("1101000011")); +MQQ1464:ROM32_INSTR_PT(503) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011000011")); +MQQ1465:ROM32_INSTR_PT(504) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11000011")); +MQQ1466:ROM32_INSTR_PT(505) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010100011")); +MQQ1467:ROM32_INSTR_PT(506) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10100011")); +MQQ1468:ROM32_INSTR_PT(507) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011100011")); +MQQ1469:ROM32_INSTR_PT(508) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000000011")); +MQQ1470:ROM32_INSTR_PT(509) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10100011")); +MQQ1471:ROM32_INSTR_PT(510) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1000011")); +MQQ1472:ROM32_INSTR_PT(511) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000010011")); +MQQ1473:ROM32_INSTR_PT(512) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010010011")); +MQQ1474:ROM32_INSTR_PT(513) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00010011")); +MQQ1475:ROM32_INSTR_PT(514) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10010011")); +MQQ1476:ROM32_INSTR_PT(515) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10010011")); +MQQ1477:ROM32_INSTR_PT(516) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("101110011")); +MQQ1478:ROM32_INSTR_PT(517) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("001110011")); +MQQ1479:ROM32_INSTR_PT(518) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00010011")); +MQQ1480:ROM32_INSTR_PT(519) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000110011")); +MQQ1481:ROM32_INSTR_PT(520) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110011")); +MQQ1482:ROM32_INSTR_PT(521) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110011")); +MQQ1483:ROM32_INSTR_PT(522) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010000011")); +MQQ1484:ROM32_INSTR_PT(523) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01000011")); +MQQ1485:ROM32_INSTR_PT(524) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01100011")); +MQQ1486:ROM32_INSTR_PT(525) <= + Eq(( ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("100011")); +MQQ1487:ROM32_INSTR_PT(526) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1100011")); +MQQ1488:ROM32_INSTR_PT(527) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10010011")); +MQQ1489:ROM32_INSTR_PT(528) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000110011")); +MQQ1490:ROM32_INSTR_PT(529) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1010011")); +MQQ1491:ROM32_INSTR_PT(530) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10001011")); +MQQ1492:ROM32_INSTR_PT(531) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("1101001011")); +MQQ1493:ROM32_INSTR_PT(532) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("001001011")); +MQQ1494:ROM32_INSTR_PT(533) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("111001011")); +MQQ1495:ROM32_INSTR_PT(534) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0000101011")); +MQQ1496:ROM32_INSTR_PT(535) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110101011")); +MQQ1497:ROM32_INSTR_PT(536) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011101011")); +MQQ1498:ROM32_INSTR_PT(537) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01101011")); +MQQ1499:ROM32_INSTR_PT(538) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000101011")); +MQQ1500:ROM32_INSTR_PT(539) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01101011")); +MQQ1501:ROM32_INSTR_PT(540) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10011011")); +MQQ1502:ROM32_INSTR_PT(541) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11011011")); +MQQ1503:ROM32_INSTR_PT(542) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0011011")); +MQQ1504:ROM32_INSTR_PT(543) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11111011")); +MQQ1505:ROM32_INSTR_PT(544) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01011011")); +MQQ1506:ROM32_INSTR_PT(545) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11011011")); +MQQ1507:ROM32_INSTR_PT(546) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11111011")); +MQQ1508:ROM32_INSTR_PT(547) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000101011")); +MQQ1509:ROM32_INSTR_PT(548) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011011")); +MQQ1510:ROM32_INSTR_PT(549) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("111011")); +MQQ1511:ROM32_INSTR_PT(550) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000100011")); +MQQ1512:ROM32_INSTR_PT(551) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01100011")); +MQQ1513:ROM32_INSTR_PT(552) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10110011")); +MQQ1514:ROM32_INSTR_PT(553) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00001011")); +MQQ1515:ROM32_INSTR_PT(554) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010001011")); +MQQ1516:ROM32_INSTR_PT(555) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1101011")); +MQQ1517:ROM32_INSTR_PT(556) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000011011")); +MQQ1518:ROM32_INSTR_PT(557) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011011")); +MQQ1519:ROM32_INSTR_PT(558) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01011011")); +MQQ1520:ROM32_INSTR_PT(559) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000111011")); +MQQ1521:ROM32_INSTR_PT(560) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0101011")); +MQQ1522:ROM32_INSTR_PT(561) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0011011")); +MQQ1523:ROM32_INSTR_PT(562) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0111011")); +MQQ1524:ROM32_INSTR_PT(563) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1111011")); +MQQ1525:ROM32_INSTR_PT(564) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("11011")); +MQQ1526:ROM32_INSTR_PT(565) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00000111")); +MQQ1527:ROM32_INSTR_PT(566) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010000111")); +MQQ1528:ROM32_INSTR_PT(567) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00000111")); +MQQ1529:ROM32_INSTR_PT(568) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001000111")); +MQQ1530:ROM32_INSTR_PT(569) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011000111")); +MQQ1531:ROM32_INSTR_PT(570) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011000111")); +MQQ1532:ROM32_INSTR_PT(571) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010100111")); +MQQ1533:ROM32_INSTR_PT(572) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110100111")); +MQQ1534:ROM32_INSTR_PT(573) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10100111")); +MQQ1535:ROM32_INSTR_PT(574) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("001100111")); +MQQ1536:ROM32_INSTR_PT(575) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011100111")); +MQQ1537:ROM32_INSTR_PT(576) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00000111")); +MQQ1538:ROM32_INSTR_PT(577) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11000111")); +MQQ1539:ROM32_INSTR_PT(578) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000010111")); +MQQ1540:ROM32_INSTR_PT(579) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10010111")); +MQQ1541:ROM32_INSTR_PT(580) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("001010111")); +MQQ1542:ROM32_INSTR_PT(581) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("011010111")); +MQQ1543:ROM32_INSTR_PT(582) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110110111")); +MQQ1544:ROM32_INSTR_PT(583) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01010111")); +MQQ1545:ROM32_INSTR_PT(584) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01100111")); +MQQ1546:ROM32_INSTR_PT(585) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000001111")); +MQQ1547:ROM32_INSTR_PT(586) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010001111")); +MQQ1548:ROM32_INSTR_PT(587) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10001111")); +MQQ1549:ROM32_INSTR_PT(588) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11001111")); +MQQ1550:ROM32_INSTR_PT(589) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10001111")); +MQQ1551:ROM32_INSTR_PT(590) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000101111")); +MQQ1552:ROM32_INSTR_PT(591) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0001101111")); +MQQ1553:ROM32_INSTR_PT(592) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11101111")); +MQQ1554:ROM32_INSTR_PT(593) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11101111")); +MQQ1555:ROM32_INSTR_PT(594) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0001111")); +MQQ1556:ROM32_INSTR_PT(595) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11101111")); +MQQ1557:ROM32_INSTR_PT(596) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00011111")); +MQQ1558:ROM32_INSTR_PT(597) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10011111")); +MQQ1559:ROM32_INSTR_PT(598) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("001011111")); +MQQ1560:ROM32_INSTR_PT(599) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000111111")); +MQQ1561:ROM32_INSTR_PT(600) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11111111")); +MQQ1562:ROM32_INSTR_PT(601) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011111")); +MQQ1563:ROM32_INSTR_PT(602) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10011111")); +MQQ1564:ROM32_INSTR_PT(603) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1111111")); +MQQ1565:ROM32_INSTR_PT(604) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10111111")); +MQQ1566:ROM32_INSTR_PT(605) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01111111")); +MQQ1567:ROM32_INSTR_PT(606) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11111111")); +MQQ1568:ROM32_INSTR_PT(607) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01101111")); +MQQ1569:ROM32_INSTR_PT(608) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011111")); +MQQ1570:ROM32_INSTR_PT(609) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10111111")); +MQQ1571:ROM32_INSTR_PT(610) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01111111")); +MQQ1572:ROM32_INSTR_PT(611) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("111111")); +MQQ1573:ROM32_INSTR_PT(612) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("111111")); +MQQ1574:ROM32_INSTR_PT(613) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11000111")); +MQQ1575:ROM32_INSTR_PT(614) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110111")); +MQQ1576:ROM32_INSTR_PT(615) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11110111")); +MQQ1577:ROM32_INSTR_PT(616) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01000111")); +MQQ1578:ROM32_INSTR_PT(617) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01001111")); +MQQ1579:ROM32_INSTR_PT(618) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01011111")); +MQQ1580:ROM32_INSTR_PT(619) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011111")); +MQQ1581:ROM32_INSTR_PT(620) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01011111")); +MQQ1582:ROM32_INSTR_PT(621) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01111111")); +MQQ1583:ROM32_INSTR_PT(622) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0111111")); +MQQ1584:ROM32_INSTR_PT(623) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011111")); +MQQ1585:ROM32_INSTR_PT(624) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011111")); +MQQ1586:ROM32_INSTR_PT(625) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0111111")); +MQQ1587:ROM32_INSTR_PT(626) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0111111")); +MQQ1588:ROM32_INSTR_PT(627) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1000011")); +MQQ1589:ROM32_INSTR_PT(628) <= + Eq(( ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("10011")); +MQQ1590:ROM32_INSTR_PT(629) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01001011")); +MQQ1591:ROM32_INSTR_PT(630) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00011011")); +MQQ1592:ROM32_INSTR_PT(631) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000111011")); +MQQ1593:ROM32_INSTR_PT(632) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00111011")); +MQQ1594:ROM32_INSTR_PT(633) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1111011")); +MQQ1595:ROM32_INSTR_PT(634) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01001011")); +MQQ1596:ROM32_INSTR_PT(635) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11011011")); +MQQ1597:ROM32_INSTR_PT(636) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("011011")); +MQQ1598:ROM32_INSTR_PT(637) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("10011")); +MQQ1599:ROM32_INSTR_PT(638) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("010000111")); +MQQ1600:ROM32_INSTR_PT(639) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000100111")); +MQQ1601:ROM32_INSTR_PT(640) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01010111")); +MQQ1602:ROM32_INSTR_PT(641) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1000111")); +MQQ1603:ROM32_INSTR_PT(642) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0111111")); +MQQ1604:ROM32_INSTR_PT(643) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("111111")); +MQQ1605:ROM32_INSTR_PT(644) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("111111")); +MQQ1606:ROM32_INSTR_PT(645) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0010111")); +MQQ1607:ROM32_INSTR_PT(646) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1110111")); +MQQ1608:ROM32_INSTR_PT(647) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11011111")); +MQQ1609:ROM32_INSTR_PT(648) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("11111")); +MQQ1610:ROM32_INSTR_PT(649) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1111111")); +MQQ1611:ROM32_INSTR_PT(650) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("11111")); +MQQ1612:ROM32_INSTR_PT(651) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(8) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("11011")); +MQQ1613:ROM32_INSTR_PT(652) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11000001")); +MQQ1614:ROM32_INSTR_PT(653) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1000001")); +MQQ1615:ROM32_INSTR_PT(654) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110001")); +MQQ1616:ROM32_INSTR_PT(655) <= + Eq(( ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("110001")); +MQQ1617:ROM32_INSTR_PT(656) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1001001")); +MQQ1618:ROM32_INSTR_PT(657) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10101001")); +MQQ1619:ROM32_INSTR_PT(658) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1001001")); +MQQ1620:ROM32_INSTR_PT(659) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00011001")); +MQQ1621:ROM32_INSTR_PT(660) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("101001")); +MQQ1622:ROM32_INSTR_PT(661) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("00000101")); +MQQ1623:ROM32_INSTR_PT(662) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01000101")); +MQQ1624:ROM32_INSTR_PT(663) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("000100101")); +MQQ1625:ROM32_INSTR_PT(664) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11110101")); +MQQ1626:ROM32_INSTR_PT(665) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11001101")); +MQQ1627:ROM32_INSTR_PT(666) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10011101")); +MQQ1628:ROM32_INSTR_PT(667) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011101")); +MQQ1629:ROM32_INSTR_PT(668) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1000001")); +MQQ1630:ROM32_INSTR_PT(669) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("011101")); +MQQ1631:ROM32_INSTR_PT(670) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("01001")); +MQQ1632:ROM32_INSTR_PT(671) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("100101")); +MQQ1633:ROM32_INSTR_PT(672) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110100011")); +MQQ1634:ROM32_INSTR_PT(673) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("100011")); +MQQ1635:ROM32_INSTR_PT(674) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01110011")); +MQQ1636:ROM32_INSTR_PT(675) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("000011")); +MQQ1637:ROM32_INSTR_PT(676) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01001011")); +MQQ1638:ROM32_INSTR_PT(677) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10101011")); +MQQ1639:ROM32_INSTR_PT(678) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10011011")); +MQQ1640:ROM32_INSTR_PT(679) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011011")); +MQQ1641:ROM32_INSTR_PT(680) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11011011")); +MQQ1642:ROM32_INSTR_PT(681) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("010011")); +MQQ1643:ROM32_INSTR_PT(682) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("110100111")); +MQQ1644:ROM32_INSTR_PT(683) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10010111")); +MQQ1645:ROM32_INSTR_PT(684) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("01010111")); +MQQ1646:ROM32_INSTR_PT(685) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("10001111")); +MQQ1647:ROM32_INSTR_PT(686) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("101111")); +MQQ1648:ROM32_INSTR_PT(687) <= + Eq(( ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("011111")); +MQQ1649:ROM32_INSTR_PT(688) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1111111")); +MQQ1650:ROM32_INSTR_PT(689) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0111111")); +MQQ1651:ROM32_INSTR_PT(690) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("111111")); +MQQ1652:ROM32_INSTR_PT(691) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1000111")); +MQQ1653:ROM32_INSTR_PT(692) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1110111")); +MQQ1654:ROM32_INSTR_PT(693) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("11011111")); +MQQ1655:ROM32_INSTR_PT(694) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1111111")); +MQQ1656:ROM32_INSTR_PT(695) <= + Eq(( ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0011")); +MQQ1657:ROM32_INSTR_PT(696) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("11011")); +MQQ1658:ROM32_INSTR_PT(697) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("110111")); +MQQ1659:ROM32_INSTR_PT(698) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0101111")); +MQQ1660:ROM32_INSTR_PT(699) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1011111")); +MQQ1661:ROM32_INSTR_PT(700) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1111111")); +MQQ1662:ROM32_INSTR_PT(701) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("01111")); +MQQ1663:ROM32_INSTR_PT(702) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1000001")); +MQQ1664:ROM32_INSTR_PT(703) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1001001")); +MQQ1665:ROM32_INSTR_PT(704) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("111001")); +MQQ1666:ROM32_INSTR_PT(705) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("100001")); +MQQ1667:ROM32_INSTR_PT(706) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("001001")); +MQQ1668:ROM32_INSTR_PT(707) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("111101")); +MQQ1669:ROM32_INSTR_PT(708) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("0110111")); +MQQ1670:ROM32_INSTR_PT(709) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("110111")); +MQQ1671:ROM32_INSTR_PT(710) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("1111111")); +MQQ1672:ROM32_INSTR_PT(711) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("111111")); +MQQ1673:ROM32_INSTR_PT(712) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("100111")); +MQQ1674:ROM32_INSTR_PT(713) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("011111")); +MQQ1675:ROM32_INSTR_PT(714) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(9) ) , STD_ULOGIC_VECTOR'("11011")); +MQQ1676:ROM32_INSTR_PT(715) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("100101")); +MQQ1677:ROM32_INSTR_PT(716) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("100011")); +MQQ1678:ROM32_INSTR_PT(717) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("0111")); +MQQ1679:ROM32_INSTR_PT(718) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(9) + ) , STD_ULOGIC_VECTOR'("1101")); +MQQ1680:ROM32_INSTR_PT(719) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("01100000")); +MQQ1681:ROM32_INSTR_PT(720) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("01100000")); +MQQ1682:ROM32_INSTR_PT(721) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1010000")); +MQQ1683:ROM32_INSTR_PT(722) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("000110000")); +MQQ1684:ROM32_INSTR_PT(723) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("01110000")); +MQQ1685:ROM32_INSTR_PT(724) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0100000")); +MQQ1686:ROM32_INSTR_PT(725) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("111000")); +MQQ1687:ROM32_INSTR_PT(726) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0111000")); +MQQ1688:ROM32_INSTR_PT(727) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0000100")); +MQQ1689:ROM32_INSTR_PT(728) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("01100100")); +MQQ1690:ROM32_INSTR_PT(729) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1100100")); +MQQ1691:ROM32_INSTR_PT(730) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1100100")); +MQQ1692:ROM32_INSTR_PT(731) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("01101100")); +MQQ1693:ROM32_INSTR_PT(732) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("01101100")); +MQQ1694:ROM32_INSTR_PT(733) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("10011100")); +MQQ1695:ROM32_INSTR_PT(734) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("101100")); +MQQ1696:ROM32_INSTR_PT(735) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("01100")); +MQQ1697:ROM32_INSTR_PT(736) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0100100")); +MQQ1698:ROM32_INSTR_PT(737) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0100000")); +MQQ1699:ROM32_INSTR_PT(738) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1100000")); +MQQ1700:ROM32_INSTR_PT(739) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("00000100")); +MQQ1701:ROM32_INSTR_PT(740) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0101100")); +MQQ1702:ROM32_INSTR_PT(741) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("011100")); +MQQ1703:ROM32_INSTR_PT(742) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1101100")); +MQQ1704:ROM32_INSTR_PT(743) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("11100")); +MQQ1705:ROM32_INSTR_PT(744) <= + Eq(( ROM_ADDR_L2(3) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("000")); +MQQ1706:ROM32_INSTR_PT(745) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("01100010")); +MQQ1707:ROM32_INSTR_PT(746) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0000010")); +MQQ1708:ROM32_INSTR_PT(747) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("00010010")); +MQQ1709:ROM32_INSTR_PT(748) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("00000010")); +MQQ1710:ROM32_INSTR_PT(749) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("11001010")); +MQQ1711:ROM32_INSTR_PT(750) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("111010")); +MQQ1712:ROM32_INSTR_PT(751) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("01001010")); +MQQ1713:ROM32_INSTR_PT(752) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("101010")); +MQQ1714:ROM32_INSTR_PT(753) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("010000110")); +MQQ1715:ROM32_INSTR_PT(754) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1000110")); +MQQ1716:ROM32_INSTR_PT(755) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("110100110")); +MQQ1717:ROM32_INSTR_PT(756) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0001110")); +MQQ1718:ROM32_INSTR_PT(757) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1001110")); +MQQ1719:ROM32_INSTR_PT(758) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("00011110")); +MQQ1720:ROM32_INSTR_PT(759) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("10011110")); +MQQ1721:ROM32_INSTR_PT(760) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1010010")); +MQQ1722:ROM32_INSTR_PT(761) <= + Eq(( ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("0110")); +MQQ1723:ROM32_INSTR_PT(762) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("00011110")); +MQQ1724:ROM32_INSTR_PT(763) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1111110")); +MQQ1725:ROM32_INSTR_PT(764) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("010110")); +MQQ1726:ROM32_INSTR_PT(765) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("010100")); +MQQ1727:ROM32_INSTR_PT(766) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1101100")); +MQQ1728:ROM32_INSTR_PT(767) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("011100")); +MQQ1729:ROM32_INSTR_PT(768) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("110000")); +MQQ1730:ROM32_INSTR_PT(769) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("00100")); +MQQ1731:ROM32_INSTR_PT(770) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0100010")); +MQQ1732:ROM32_INSTR_PT(771) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1001110")); +MQQ1733:ROM32_INSTR_PT(772) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("0000")); +MQQ1734:ROM32_INSTR_PT(773) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("01110")); +MQQ1735:ROM32_INSTR_PT(774) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("01000001")); +MQQ1736:ROM32_INSTR_PT(775) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("110100001")); +MQQ1737:ROM32_INSTR_PT(776) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("01010001")); +MQQ1738:ROM32_INSTR_PT(777) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("11010001")); +MQQ1739:ROM32_INSTR_PT(778) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1010001")); +MQQ1740:ROM32_INSTR_PT(779) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0000001")); +MQQ1741:ROM32_INSTR_PT(780) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1000001")); +MQQ1742:ROM32_INSTR_PT(781) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("010001")); +MQQ1743:ROM32_INSTR_PT(782) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0001001")); +MQQ1744:ROM32_INSTR_PT(783) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("001001")); +MQQ1745:ROM32_INSTR_PT(784) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("00011001")); +MQQ1746:ROM32_INSTR_PT(785) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("111001")); +MQQ1747:ROM32_INSTR_PT(786) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("00011001")); +MQQ1748:ROM32_INSTR_PT(787) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("00100101")); +MQQ1749:ROM32_INSTR_PT(788) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("00010101")); +MQQ1750:ROM32_INSTR_PT(789) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("00011101")); +MQQ1751:ROM32_INSTR_PT(790) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("10011101")); +MQQ1752:ROM32_INSTR_PT(791) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("011101")); +MQQ1753:ROM32_INSTR_PT(792) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("110101")); +MQQ1754:ROM32_INSTR_PT(793) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("10101")); +MQQ1755:ROM32_INSTR_PT(794) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("11101")); +MQQ1756:ROM32_INSTR_PT(795) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0000101")); +MQQ1757:ROM32_INSTR_PT(796) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0000101")); +MQQ1758:ROM32_INSTR_PT(797) <= + Eq(( ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("11101")); +MQQ1759:ROM32_INSTR_PT(798) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("101101")); +MQQ1760:ROM32_INSTR_PT(799) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("100001")); +MQQ1761:ROM32_INSTR_PT(800) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("000100011")); +MQQ1762:ROM32_INSTR_PT(801) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("00000011")); +MQQ1763:ROM32_INSTR_PT(802) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0000011")); +MQQ1764:ROM32_INSTR_PT(803) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1010011")); +MQQ1765:ROM32_INSTR_PT(804) <= + Eq(( ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("10011")); +MQQ1766:ROM32_INSTR_PT(805) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("01001011")); +MQQ1767:ROM32_INSTR_PT(806) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0001011")); +MQQ1768:ROM32_INSTR_PT(807) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("01000011")); +MQQ1769:ROM32_INSTR_PT(808) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("101011")); +MQQ1770:ROM32_INSTR_PT(809) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("11011")); +MQQ1771:ROM32_INSTR_PT(810) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("100111")); +MQQ1772:ROM32_INSTR_PT(811) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("00010111")); +MQQ1773:ROM32_INSTR_PT(812) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("01010111")); +MQQ1774:ROM32_INSTR_PT(813) <= + Eq(( ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("110111")); +MQQ1775:ROM32_INSTR_PT(814) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1110111")); +MQQ1776:ROM32_INSTR_PT(815) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("11010111")); +MQQ1777:ROM32_INSTR_PT(816) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("000101111")); +MQQ1778:ROM32_INSTR_PT(817) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("01101111")); +MQQ1779:ROM32_INSTR_PT(818) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("111111")); +MQQ1780:ROM32_INSTR_PT(819) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("111111")); +MQQ1781:ROM32_INSTR_PT(820) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("11111")); +MQQ1782:ROM32_INSTR_PT(821) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("111111")); +MQQ1783:ROM32_INSTR_PT(822) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("101011")); +MQQ1784:ROM32_INSTR_PT(823) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("01000111")); +MQQ1785:ROM32_INSTR_PT(824) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0110111")); +MQQ1786:ROM32_INSTR_PT(825) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("110111")); +MQQ1787:ROM32_INSTR_PT(826) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("101111")); +MQQ1788:ROM32_INSTR_PT(827) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("11111")); +MQQ1789:ROM32_INSTR_PT(828) <= + Eq(( ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("0111")); +MQQ1790:ROM32_INSTR_PT(829) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("111111")); +MQQ1791:ROM32_INSTR_PT(830) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(7) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("01111")); +MQQ1792:ROM32_INSTR_PT(831) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("110001")); +MQQ1793:ROM32_INSTR_PT(832) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("011001")); +MQQ1794:ROM32_INSTR_PT(833) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1001101")); +MQQ1795:ROM32_INSTR_PT(834) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("01001")); +MQQ1796:ROM32_INSTR_PT(835) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0100011")); +MQQ1797:ROM32_INSTR_PT(836) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1111011")); +MQQ1798:ROM32_INSTR_PT(837) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("11011")); +MQQ1799:ROM32_INSTR_PT(838) <= + Eq(( ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("011")); +MQQ1800:ROM32_INSTR_PT(839) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("0000111")); +MQQ1801:ROM32_INSTR_PT(840) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("1111111")); +MQQ1802:ROM32_INSTR_PT(841) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("011111")); +MQQ1803:ROM32_INSTR_PT(842) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("101111")); +MQQ1804:ROM32_INSTR_PT(843) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("100011")); +MQQ1805:ROM32_INSTR_PT(844) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("110111")); +MQQ1806:ROM32_INSTR_PT(845) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("011111")); +MQQ1807:ROM32_INSTR_PT(846) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("000101")); +MQQ1808:ROM32_INSTR_PT(847) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("100011")); +MQQ1809:ROM32_INSTR_PT(848) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("1111")); +MQQ1810:ROM32_INSTR_PT(849) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(8) ) , STD_ULOGIC_VECTOR'("10111")); +MQQ1811:ROM32_INSTR_PT(850) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(8) + ) , STD_ULOGIC_VECTOR'("0111")); +MQQ1812:ROM32_INSTR_PT(851) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("1001000")); +MQQ1813:ROM32_INSTR_PT(852) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) + ) , STD_ULOGIC_VECTOR'("110000")); +MQQ1814:ROM32_INSTR_PT(853) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) + ) , STD_ULOGIC_VECTOR'("00011100")); +MQQ1815:ROM32_INSTR_PT(854) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) + ) , STD_ULOGIC_VECTOR'("00000010")); +MQQ1816:ROM32_INSTR_PT(855) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("0100010")); +MQQ1817:ROM32_INSTR_PT(856) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("0000010")); +MQQ1818:ROM32_INSTR_PT(857) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) + ) , STD_ULOGIC_VECTOR'("101110")); +MQQ1819:ROM32_INSTR_PT(858) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("1101110")); +MQQ1820:ROM32_INSTR_PT(859) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("1001100")); +MQQ1821:ROM32_INSTR_PT(860) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("00000")); +MQQ1822:ROM32_INSTR_PT(861) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) + ) , STD_ULOGIC_VECTOR'("1110")); +MQQ1823:ROM32_INSTR_PT(862) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("0100101")); +MQQ1824:ROM32_INSTR_PT(863) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("1001101")); +MQQ1825:ROM32_INSTR_PT(864) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) + ) , STD_ULOGIC_VECTOR'("001101")); +MQQ1826:ROM32_INSTR_PT(865) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("1101101")); +MQQ1827:ROM32_INSTR_PT(866) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) + ) , STD_ULOGIC_VECTOR'("1101")); +MQQ1828:ROM32_INSTR_PT(867) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("1010011")); +MQQ1829:ROM32_INSTR_PT(868) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("1001011")); +MQQ1830:ROM32_INSTR_PT(869) <= + Eq(( ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) + ) , STD_ULOGIC_VECTOR'("110111")); +MQQ1831:ROM32_INSTR_PT(870) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("0011111")); +MQQ1832:ROM32_INSTR_PT(871) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) + ) , STD_ULOGIC_VECTOR'("111111")); +MQQ1833:ROM32_INSTR_PT(872) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(6) & ROM_ADDR_L2(7) + ) , STD_ULOGIC_VECTOR'("110111")); +MQQ1834:ROM32_INSTR_PT(873) <= + Eq(( ROM_ADDR_L2(1) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("11111")); +MQQ1835:ROM32_INSTR_PT(874) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) & + ROM_ADDR_L2(7) ) , STD_ULOGIC_VECTOR'("01111")); +MQQ1836:ROM32_INSTR_PT(875) <= + Eq(( ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) + ) , STD_ULOGIC_VECTOR'("1101")); +MQQ1837:ROM32_INSTR_PT(876) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(7) + ) , STD_ULOGIC_VECTOR'("000011")); +MQQ1838:ROM32_INSTR_PT(877) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) ) , STD_ULOGIC_VECTOR'("0000100")); +MQQ1839:ROM32_INSTR_PT(878) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(5) & ROM_ADDR_L2(6) + ) , STD_ULOGIC_VECTOR'("010010")); +MQQ1840:ROM32_INSTR_PT(879) <= + Eq(( ROM_ADDR_L2(4) & ROM_ADDR_L2(6) + ) , STD_ULOGIC_VECTOR'("00")); +MQQ1841:ROM32_INSTR_PT(880) <= + Eq(( ROM_ADDR_L2(4) & ROM_ADDR_L2(5) & + ROM_ADDR_L2(6) ) , STD_ULOGIC_VECTOR'("111")); +MQQ1842:ROM32_INSTR_PT(881) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) & ROM_ADDR_L2(6) + ) , STD_ULOGIC_VECTOR'("110111")); +MQQ1843:ROM32_INSTR_PT(882) <= + Eq(( ROM_ADDR_L2(4) & ROM_ADDR_L2(5) + ) , STD_ULOGIC_VECTOR'("00")); +MQQ1844:ROM32_INSTR_PT(883) <= + Eq(( ROM_ADDR_L2(3) & ROM_ADDR_L2(5) + ) , STD_ULOGIC_VECTOR'("00")); +MQQ1845:ROM32_INSTR_PT(884) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(5) + ) , STD_ULOGIC_VECTOR'("0110")); +MQQ1846:ROM32_INSTR_PT(885) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) & ROM_ADDR_L2(5) + ) , STD_ULOGIC_VECTOR'("0110")); +MQQ1847:ROM32_INSTR_PT(886) <= + Eq(( ROM_ADDR_L2(3) & ROM_ADDR_L2(4) & + ROM_ADDR_L2(5) ) , STD_ULOGIC_VECTOR'("111")); +MQQ1848:ROM32_INSTR_PT(887) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(3) & + ROM_ADDR_L2(4) ) , STD_ULOGIC_VECTOR'("000")); +MQQ1849:ROM32_INSTR_PT(888) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(2) & + ROM_ADDR_L2(3) & ROM_ADDR_L2(4) + ) , STD_ULOGIC_VECTOR'("0111")); +MQQ1850:ROM32_INSTR_PT(889) <= + Eq(( ROM_ADDR_L2(0) & ROM_ADDR_L2(1) & + ROM_ADDR_L2(2) ) , STD_ULOGIC_VECTOR'("111")); +MQQ1851:ROM32_INSTR_PT(890) <= + Eq(( ROM_ADDR_L2(2) ) , STD_ULOGIC'('1')); +MQQ1852:ROM32_INSTR_PT(891) <= + Eq(( ROM_ADDR_L2(1) ) , STD_ULOGIC'('1')); +MQQ1853:ROM32_INSTR_PT(892) <= + Eq(( ROM_ADDR_L2(0) ) , STD_ULOGIC'('0')); +MQQ1854:ROM32_INSTR_PT(893) <= + '1'; +-- Table ROM32_INSTR Signal Assignments for Outputs +MQQ1855:TEMPLATE(0) <= + (ROM32_INSTR_PT(28) OR ROM32_INSTR_PT(33) + OR ROM32_INSTR_PT(45) OR ROM32_INSTR_PT(68) + OR ROM32_INSTR_PT(76) OR ROM32_INSTR_PT(85) + OR ROM32_INSTR_PT(113) OR ROM32_INSTR_PT(120) + OR ROM32_INSTR_PT(128) OR ROM32_INSTR_PT(132) + OR ROM32_INSTR_PT(142) OR ROM32_INSTR_PT(159) + OR ROM32_INSTR_PT(162) OR ROM32_INSTR_PT(175) + OR ROM32_INSTR_PT(176) OR ROM32_INSTR_PT(177) + OR ROM32_INSTR_PT(180) OR ROM32_INSTR_PT(222) + OR ROM32_INSTR_PT(226) OR ROM32_INSTR_PT(233) + OR ROM32_INSTR_PT(237) OR ROM32_INSTR_PT(242) + OR ROM32_INSTR_PT(255) OR ROM32_INSTR_PT(290) + OR ROM32_INSTR_PT(292) OR ROM32_INSTR_PT(309) + OR ROM32_INSTR_PT(335) OR ROM32_INSTR_PT(346) + OR ROM32_INSTR_PT(351) OR ROM32_INSTR_PT(353) + OR ROM32_INSTR_PT(356) OR ROM32_INSTR_PT(357) + OR ROM32_INSTR_PT(359) OR ROM32_INSTR_PT(364) + OR ROM32_INSTR_PT(365) OR ROM32_INSTR_PT(373) + OR ROM32_INSTR_PT(381) OR ROM32_INSTR_PT(388) + OR ROM32_INSTR_PT(391) OR ROM32_INSTR_PT(399) + OR ROM32_INSTR_PT(425) OR ROM32_INSTR_PT(431) + OR ROM32_INSTR_PT(467) OR ROM32_INSTR_PT(473) + OR ROM32_INSTR_PT(527) OR ROM32_INSTR_PT(555) + OR ROM32_INSTR_PT(563) OR ROM32_INSTR_PT(571) + OR ROM32_INSTR_PT(586) OR ROM32_INSTR_PT(597) + OR ROM32_INSTR_PT(604) OR ROM32_INSTR_PT(615) + OR ROM32_INSTR_PT(652) OR ROM32_INSTR_PT(657) + OR ROM32_INSTR_PT(664) OR ROM32_INSTR_PT(691) + OR ROM32_INSTR_PT(692) OR ROM32_INSTR_PT(697) + OR ROM32_INSTR_PT(711) OR ROM32_INSTR_PT(715) + OR ROM32_INSTR_PT(716) OR ROM32_INSTR_PT(718) + OR ROM32_INSTR_PT(729) OR ROM32_INSTR_PT(763) + OR ROM32_INSTR_PT(792) OR ROM32_INSTR_PT(829) + OR ROM32_INSTR_PT(831) OR ROM32_INSTR_PT(857) + OR ROM32_INSTR_PT(872)); +MQQ1856:TEMPLATE(1) <= + (ROM32_INSTR_PT(3) OR ROM32_INSTR_PT(5) + OR ROM32_INSTR_PT(6) OR ROM32_INSTR_PT(7) + OR ROM32_INSTR_PT(8) OR ROM32_INSTR_PT(9) + OR ROM32_INSTR_PT(10) OR ROM32_INSTR_PT(13) + OR ROM32_INSTR_PT(14) OR ROM32_INSTR_PT(16) + OR ROM32_INSTR_PT(17) OR ROM32_INSTR_PT(20) + OR ROM32_INSTR_PT(23) OR ROM32_INSTR_PT(26) + OR ROM32_INSTR_PT(32) OR ROM32_INSTR_PT(35) + OR ROM32_INSTR_PT(37) OR ROM32_INSTR_PT(39) + OR ROM32_INSTR_PT(41) OR ROM32_INSTR_PT(42) + OR ROM32_INSTR_PT(43) OR ROM32_INSTR_PT(49) + OR ROM32_INSTR_PT(50) OR ROM32_INSTR_PT(51) + OR ROM32_INSTR_PT(52) OR ROM32_INSTR_PT(53) + OR ROM32_INSTR_PT(55) OR ROM32_INSTR_PT(56) + OR ROM32_INSTR_PT(57) OR ROM32_INSTR_PT(59) + OR ROM32_INSTR_PT(63) OR ROM32_INSTR_PT(66) + OR ROM32_INSTR_PT(67) OR ROM32_INSTR_PT(72) + OR ROM32_INSTR_PT(73) OR ROM32_INSTR_PT(74) + OR ROM32_INSTR_PT(77) OR ROM32_INSTR_PT(79) + OR ROM32_INSTR_PT(80) OR ROM32_INSTR_PT(83) + OR ROM32_INSTR_PT(84) OR ROM32_INSTR_PT(87) + OR ROM32_INSTR_PT(90) OR ROM32_INSTR_PT(92) + OR ROM32_INSTR_PT(93) OR ROM32_INSTR_PT(96) + OR ROM32_INSTR_PT(97) OR ROM32_INSTR_PT(99) + OR ROM32_INSTR_PT(100) OR ROM32_INSTR_PT(101) + OR ROM32_INSTR_PT(102) OR ROM32_INSTR_PT(103) + OR ROM32_INSTR_PT(105) OR ROM32_INSTR_PT(106) + OR ROM32_INSTR_PT(109) OR ROM32_INSTR_PT(110) + OR ROM32_INSTR_PT(111) OR ROM32_INSTR_PT(114) + OR ROM32_INSTR_PT(115) OR ROM32_INSTR_PT(117) + OR ROM32_INSTR_PT(118) OR ROM32_INSTR_PT(119) + OR ROM32_INSTR_PT(122) OR ROM32_INSTR_PT(124) + OR ROM32_INSTR_PT(127) OR ROM32_INSTR_PT(130) + OR ROM32_INSTR_PT(134) OR ROM32_INSTR_PT(135) + OR ROM32_INSTR_PT(139) OR ROM32_INSTR_PT(141) + OR ROM32_INSTR_PT(144) OR ROM32_INSTR_PT(148) + OR ROM32_INSTR_PT(153) OR ROM32_INSTR_PT(158) + OR ROM32_INSTR_PT(163) OR ROM32_INSTR_PT(164) + OR ROM32_INSTR_PT(165) OR ROM32_INSTR_PT(169) + OR ROM32_INSTR_PT(170) OR ROM32_INSTR_PT(171) + OR ROM32_INSTR_PT(172) OR ROM32_INSTR_PT(179) + OR ROM32_INSTR_PT(183) OR ROM32_INSTR_PT(184) + OR ROM32_INSTR_PT(186) OR ROM32_INSTR_PT(192) + OR ROM32_INSTR_PT(193) OR ROM32_INSTR_PT(195) + OR ROM32_INSTR_PT(196) OR ROM32_INSTR_PT(199) + OR ROM32_INSTR_PT(200) OR ROM32_INSTR_PT(202) + OR ROM32_INSTR_PT(203) OR ROM32_INSTR_PT(205) + OR ROM32_INSTR_PT(206) OR ROM32_INSTR_PT(207) + OR ROM32_INSTR_PT(209) OR ROM32_INSTR_PT(215) + OR ROM32_INSTR_PT(216) OR ROM32_INSTR_PT(218) + OR ROM32_INSTR_PT(219) OR ROM32_INSTR_PT(220) + OR ROM32_INSTR_PT(223) OR ROM32_INSTR_PT(224) + OR ROM32_INSTR_PT(227) OR ROM32_INSTR_PT(229) + OR ROM32_INSTR_PT(238) OR ROM32_INSTR_PT(241) + OR ROM32_INSTR_PT(243) OR ROM32_INSTR_PT(249) + OR ROM32_INSTR_PT(250) OR ROM32_INSTR_PT(252) + OR ROM32_INSTR_PT(254) OR ROM32_INSTR_PT(256) + OR ROM32_INSTR_PT(257) OR ROM32_INSTR_PT(259) + OR ROM32_INSTR_PT(260) OR ROM32_INSTR_PT(261) + OR ROM32_INSTR_PT(262) OR ROM32_INSTR_PT(264) + OR ROM32_INSTR_PT(267) OR ROM32_INSTR_PT(268) + OR ROM32_INSTR_PT(269) OR ROM32_INSTR_PT(270) + OR ROM32_INSTR_PT(273) OR ROM32_INSTR_PT(274) + OR ROM32_INSTR_PT(275) OR ROM32_INSTR_PT(278) + OR ROM32_INSTR_PT(280) OR ROM32_INSTR_PT(282) + OR ROM32_INSTR_PT(283) OR ROM32_INSTR_PT(284) + OR ROM32_INSTR_PT(287) OR ROM32_INSTR_PT(288) + OR ROM32_INSTR_PT(289) OR ROM32_INSTR_PT(293) + OR ROM32_INSTR_PT(294) OR ROM32_INSTR_PT(295) + OR ROM32_INSTR_PT(297) OR ROM32_INSTR_PT(299) + OR ROM32_INSTR_PT(301) OR ROM32_INSTR_PT(303) + OR ROM32_INSTR_PT(306) OR ROM32_INSTR_PT(313) + OR ROM32_INSTR_PT(321) OR ROM32_INSTR_PT(323) + OR ROM32_INSTR_PT(328) OR ROM32_INSTR_PT(331) + OR ROM32_INSTR_PT(342) OR ROM32_INSTR_PT(345) + OR ROM32_INSTR_PT(348) OR ROM32_INSTR_PT(350) + OR ROM32_INSTR_PT(352) OR ROM32_INSTR_PT(355) + OR ROM32_INSTR_PT(361) OR ROM32_INSTR_PT(362) + OR ROM32_INSTR_PT(363) OR ROM32_INSTR_PT(366) + OR ROM32_INSTR_PT(367) OR ROM32_INSTR_PT(368) + OR ROM32_INSTR_PT(370) OR ROM32_INSTR_PT(371) + OR ROM32_INSTR_PT(374) OR ROM32_INSTR_PT(376) + OR ROM32_INSTR_PT(379) OR ROM32_INSTR_PT(382) + OR ROM32_INSTR_PT(383) OR ROM32_INSTR_PT(386) + OR ROM32_INSTR_PT(387) OR ROM32_INSTR_PT(390) + OR ROM32_INSTR_PT(392) OR ROM32_INSTR_PT(394) + OR ROM32_INSTR_PT(396) OR ROM32_INSTR_PT(400) + OR ROM32_INSTR_PT(401) OR ROM32_INSTR_PT(402) + OR ROM32_INSTR_PT(404) OR ROM32_INSTR_PT(405) + OR ROM32_INSTR_PT(406) OR ROM32_INSTR_PT(409) + OR ROM32_INSTR_PT(411) OR ROM32_INSTR_PT(412) + OR ROM32_INSTR_PT(415) OR ROM32_INSTR_PT(417) + OR ROM32_INSTR_PT(418) OR ROM32_INSTR_PT(421) + OR ROM32_INSTR_PT(422) OR ROM32_INSTR_PT(423) + OR ROM32_INSTR_PT(424) OR ROM32_INSTR_PT(426) + OR ROM32_INSTR_PT(428) OR ROM32_INSTR_PT(430) + OR ROM32_INSTR_PT(433) OR ROM32_INSTR_PT(434) + OR ROM32_INSTR_PT(435) OR ROM32_INSTR_PT(436) + OR ROM32_INSTR_PT(438) OR ROM32_INSTR_PT(441) + OR ROM32_INSTR_PT(442) OR ROM32_INSTR_PT(443) + OR ROM32_INSTR_PT(451) OR ROM32_INSTR_PT(452) + OR ROM32_INSTR_PT(453) OR ROM32_INSTR_PT(454) + OR ROM32_INSTR_PT(458) OR ROM32_INSTR_PT(461) + OR ROM32_INSTR_PT(464) OR ROM32_INSTR_PT(469) + OR ROM32_INSTR_PT(472) OR ROM32_INSTR_PT(474) + OR ROM32_INSTR_PT(475) OR ROM32_INSTR_PT(476) + OR ROM32_INSTR_PT(477) OR ROM32_INSTR_PT(478) + OR ROM32_INSTR_PT(479) OR ROM32_INSTR_PT(480) + OR ROM32_INSTR_PT(481) OR ROM32_INSTR_PT(482) + OR ROM32_INSTR_PT(486) OR ROM32_INSTR_PT(490) + OR ROM32_INSTR_PT(491) OR ROM32_INSTR_PT(494) + OR ROM32_INSTR_PT(496) OR ROM32_INSTR_PT(497) + OR ROM32_INSTR_PT(498) OR ROM32_INSTR_PT(501) + OR ROM32_INSTR_PT(502) OR ROM32_INSTR_PT(503) + OR ROM32_INSTR_PT(505) OR ROM32_INSTR_PT(506) + OR ROM32_INSTR_PT(507) OR ROM32_INSTR_PT(508) + OR ROM32_INSTR_PT(509) OR ROM32_INSTR_PT(514) + OR ROM32_INSTR_PT(517) OR ROM32_INSTR_PT(519) + OR ROM32_INSTR_PT(520) OR ROM32_INSTR_PT(521) + OR ROM32_INSTR_PT(522) OR ROM32_INSTR_PT(524) + OR ROM32_INSTR_PT(530) OR ROM32_INSTR_PT(531) + OR ROM32_INSTR_PT(532) OR ROM32_INSTR_PT(534) + OR ROM32_INSTR_PT(535) OR ROM32_INSTR_PT(536) + OR ROM32_INSTR_PT(538) OR ROM32_INSTR_PT(539) + OR ROM32_INSTR_PT(541) OR ROM32_INSTR_PT(543) + OR ROM32_INSTR_PT(544) OR ROM32_INSTR_PT(546) + OR ROM32_INSTR_PT(547) OR ROM32_INSTR_PT(550) + OR ROM32_INSTR_PT(551) OR ROM32_INSTR_PT(552) + OR ROM32_INSTR_PT(554) OR ROM32_INSTR_PT(556) + OR ROM32_INSTR_PT(557) OR ROM32_INSTR_PT(558) + OR ROM32_INSTR_PT(562) OR ROM32_INSTR_PT(566) + OR ROM32_INSTR_PT(568) OR ROM32_INSTR_PT(569) + OR ROM32_INSTR_PT(570) OR ROM32_INSTR_PT(574) + OR ROM32_INSTR_PT(575) OR ROM32_INSTR_PT(578) + OR ROM32_INSTR_PT(579) OR ROM32_INSTR_PT(580) + OR ROM32_INSTR_PT(581) OR ROM32_INSTR_PT(582) + OR ROM32_INSTR_PT(583) OR ROM32_INSTR_PT(584) + OR ROM32_INSTR_PT(585) OR ROM32_INSTR_PT(588) + OR ROM32_INSTR_PT(589) OR ROM32_INSTR_PT(590) + OR ROM32_INSTR_PT(593) OR ROM32_INSTR_PT(595) + OR ROM32_INSTR_PT(598) OR ROM32_INSTR_PT(599) + OR ROM32_INSTR_PT(600) OR ROM32_INSTR_PT(601) + OR ROM32_INSTR_PT(602) OR ROM32_INSTR_PT(605) + OR ROM32_INSTR_PT(606) OR ROM32_INSTR_PT(607) + OR ROM32_INSTR_PT(608) OR ROM32_INSTR_PT(609) + OR ROM32_INSTR_PT(610) OR ROM32_INSTR_PT(611) + OR ROM32_INSTR_PT(612) OR ROM32_INSTR_PT(613) + OR ROM32_INSTR_PT(614) OR ROM32_INSTR_PT(620) + OR ROM32_INSTR_PT(621) OR ROM32_INSTR_PT(624) + OR ROM32_INSTR_PT(625) OR ROM32_INSTR_PT(626) + OR ROM32_INSTR_PT(630) OR ROM32_INSTR_PT(634) + OR ROM32_INSTR_PT(635) OR ROM32_INSTR_PT(638) + OR ROM32_INSTR_PT(639) OR ROM32_INSTR_PT(642) + OR ROM32_INSTR_PT(643) OR ROM32_INSTR_PT(644) + OR ROM32_INSTR_PT(647) OR ROM32_INSTR_PT(654) + OR ROM32_INSTR_PT(660) OR ROM32_INSTR_PT(663) + OR ROM32_INSTR_PT(666) OR ROM32_INSTR_PT(674) + OR ROM32_INSTR_PT(677) OR ROM32_INSTR_PT(678) + OR ROM32_INSTR_PT(680) OR ROM32_INSTR_PT(684) + OR ROM32_INSTR_PT(685) OR ROM32_INSTR_PT(698) + OR ROM32_INSTR_PT(708) OR ROM32_INSTR_PT(713) + OR ROM32_INSTR_PT(719) OR ROM32_INSTR_PT(726) + OR ROM32_INSTR_PT(733) OR ROM32_INSTR_PT(736) + OR ROM32_INSTR_PT(745) OR ROM32_INSTR_PT(755) + OR ROM32_INSTR_PT(762) OR ROM32_INSTR_PT(770) + OR ROM32_INSTR_PT(785) OR ROM32_INSTR_PT(795) + OR ROM32_INSTR_PT(801) OR ROM32_INSTR_PT(805) + OR ROM32_INSTR_PT(812) OR ROM32_INSTR_PT(817) + OR ROM32_INSTR_PT(819) OR ROM32_INSTR_PT(845) + OR ROM32_INSTR_PT(847) OR ROM32_INSTR_PT(851) + OR ROM32_INSTR_PT(853) OR ROM32_INSTR_PT(854) + OR ROM32_INSTR_PT(855) OR ROM32_INSTR_PT(862) + OR ROM32_INSTR_PT(869) OR ROM32_INSTR_PT(870) + OR ROM32_INSTR_PT(871) OR ROM32_INSTR_PT(878) + OR ROM32_INSTR_PT(889)); +MQQ1857:TEMPLATE(2) <= + (ROM32_INSTR_PT(4) OR ROM32_INSTR_PT(5) + OR ROM32_INSTR_PT(6) OR ROM32_INSTR_PT(7) + OR ROM32_INSTR_PT(13) OR ROM32_INSTR_PT(14) + OR ROM32_INSTR_PT(18) OR ROM32_INSTR_PT(23) + OR ROM32_INSTR_PT(27) OR ROM32_INSTR_PT(29) + OR ROM32_INSTR_PT(31) OR ROM32_INSTR_PT(35) + OR ROM32_INSTR_PT(38) OR ROM32_INSTR_PT(39) + OR ROM32_INSTR_PT(41) OR ROM32_INSTR_PT(42) + OR ROM32_INSTR_PT(43) OR ROM32_INSTR_PT(53) + OR ROM32_INSTR_PT(56) OR ROM32_INSTR_PT(57) + OR ROM32_INSTR_PT(62) OR ROM32_INSTR_PT(70) + OR ROM32_INSTR_PT(72) OR ROM32_INSTR_PT(79) + OR ROM32_INSTR_PT(80) OR ROM32_INSTR_PT(81) + OR ROM32_INSTR_PT(83) OR ROM32_INSTR_PT(92) + OR ROM32_INSTR_PT(95) OR ROM32_INSTR_PT(97) + OR ROM32_INSTR_PT(98) OR ROM32_INSTR_PT(101) + OR ROM32_INSTR_PT(102) OR ROM32_INSTR_PT(105) + OR ROM32_INSTR_PT(109) OR ROM32_INSTR_PT(110) + OR ROM32_INSTR_PT(111) OR ROM32_INSTR_PT(117) + OR ROM32_INSTR_PT(122) OR ROM32_INSTR_PT(124) + OR ROM32_INSTR_PT(130) OR ROM32_INSTR_PT(139) + OR ROM32_INSTR_PT(141) OR ROM32_INSTR_PT(144) + OR ROM32_INSTR_PT(145) OR ROM32_INSTR_PT(146) + OR ROM32_INSTR_PT(147) OR ROM32_INSTR_PT(150) + OR ROM32_INSTR_PT(151) OR ROM32_INSTR_PT(153) + OR ROM32_INSTR_PT(158) OR ROM32_INSTR_PT(163) + OR ROM32_INSTR_PT(165) OR ROM32_INSTR_PT(166) + OR ROM32_INSTR_PT(172) OR ROM32_INSTR_PT(174) + OR ROM32_INSTR_PT(185) OR ROM32_INSTR_PT(186) + OR ROM32_INSTR_PT(187) OR ROM32_INSTR_PT(189) + OR ROM32_INSTR_PT(192) OR ROM32_INSTR_PT(193) + OR ROM32_INSTR_PT(195) OR ROM32_INSTR_PT(199) + OR ROM32_INSTR_PT(203) OR ROM32_INSTR_PT(205) + OR ROM32_INSTR_PT(206) OR ROM32_INSTR_PT(207) + OR ROM32_INSTR_PT(208) OR ROM32_INSTR_PT(209) + OR ROM32_INSTR_PT(210) OR ROM32_INSTR_PT(218) + OR ROM32_INSTR_PT(228) OR ROM32_INSTR_PT(229) + OR ROM32_INSTR_PT(230) OR ROM32_INSTR_PT(232) + OR ROM32_INSTR_PT(235) OR ROM32_INSTR_PT(240) + OR ROM32_INSTR_PT(245) OR ROM32_INSTR_PT(249) + OR ROM32_INSTR_PT(251) OR ROM32_INSTR_PT(252) + OR ROM32_INSTR_PT(254) OR ROM32_INSTR_PT(256) + OR ROM32_INSTR_PT(257) OR ROM32_INSTR_PT(262) + OR ROM32_INSTR_PT(268) OR ROM32_INSTR_PT(275) + OR ROM32_INSTR_PT(279) OR ROM32_INSTR_PT(285) + OR ROM32_INSTR_PT(287) OR ROM32_INSTR_PT(289) + OR ROM32_INSTR_PT(291) OR ROM32_INSTR_PT(294) + OR ROM32_INSTR_PT(302) OR ROM32_INSTR_PT(305) + OR ROM32_INSTR_PT(307) OR ROM32_INSTR_PT(311) + OR ROM32_INSTR_PT(322) OR ROM32_INSTR_PT(323) + OR ROM32_INSTR_PT(325) OR ROM32_INSTR_PT(329) + OR ROM32_INSTR_PT(331) OR ROM32_INSTR_PT(332) + OR ROM32_INSTR_PT(337) OR ROM32_INSTR_PT(338) + OR ROM32_INSTR_PT(339) OR ROM32_INSTR_PT(342) + OR ROM32_INSTR_PT(350) OR ROM32_INSTR_PT(352) + OR ROM32_INSTR_PT(355) OR ROM32_INSTR_PT(362) + OR ROM32_INSTR_PT(363) OR ROM32_INSTR_PT(366) + OR ROM32_INSTR_PT(367) OR ROM32_INSTR_PT(368) + OR ROM32_INSTR_PT(370) OR ROM32_INSTR_PT(374) + OR ROM32_INSTR_PT(376) OR ROM32_INSTR_PT(378) + OR ROM32_INSTR_PT(382) OR ROM32_INSTR_PT(386) + OR ROM32_INSTR_PT(387) OR ROM32_INSTR_PT(393) + OR ROM32_INSTR_PT(394) OR ROM32_INSTR_PT(395) + OR ROM32_INSTR_PT(398) OR ROM32_INSTR_PT(400) + OR ROM32_INSTR_PT(402) OR ROM32_INSTR_PT(404) + OR ROM32_INSTR_PT(405) OR ROM32_INSTR_PT(409) + OR ROM32_INSTR_PT(415) OR ROM32_INSTR_PT(416) + OR ROM32_INSTR_PT(417) OR ROM32_INSTR_PT(418) + OR ROM32_INSTR_PT(419) OR ROM32_INSTR_PT(422) + OR ROM32_INSTR_PT(423) OR ROM32_INSTR_PT(426) + OR ROM32_INSTR_PT(434) OR ROM32_INSTR_PT(435) + OR ROM32_INSTR_PT(436) OR ROM32_INSTR_PT(438) + OR ROM32_INSTR_PT(441) OR ROM32_INSTR_PT(442) + OR ROM32_INSTR_PT(443) OR ROM32_INSTR_PT(446) + OR ROM32_INSTR_PT(451) OR ROM32_INSTR_PT(452) + OR ROM32_INSTR_PT(454) OR ROM32_INSTR_PT(456) + OR ROM32_INSTR_PT(458) OR ROM32_INSTR_PT(461) + OR ROM32_INSTR_PT(463) OR ROM32_INSTR_PT(464) + OR ROM32_INSTR_PT(465) OR ROM32_INSTR_PT(468) + OR ROM32_INSTR_PT(469) OR ROM32_INSTR_PT(471) + OR ROM32_INSTR_PT(472) OR ROM32_INSTR_PT(474) + OR ROM32_INSTR_PT(476) OR ROM32_INSTR_PT(480) + OR ROM32_INSTR_PT(486) OR ROM32_INSTR_PT(489) + OR ROM32_INSTR_PT(496) OR ROM32_INSTR_PT(497) + OR ROM32_INSTR_PT(498) OR ROM32_INSTR_PT(503) + OR ROM32_INSTR_PT(505) OR ROM32_INSTR_PT(507) + OR ROM32_INSTR_PT(513) OR ROM32_INSTR_PT(514) + OR ROM32_INSTR_PT(517) OR ROM32_INSTR_PT(532) + OR ROM32_INSTR_PT(537) OR ROM32_INSTR_PT(539) + OR ROM32_INSTR_PT(541) OR ROM32_INSTR_PT(544) + OR ROM32_INSTR_PT(547) OR ROM32_INSTR_PT(549) + OR ROM32_INSTR_PT(551) OR ROM32_INSTR_PT(557) + OR ROM32_INSTR_PT(558) OR ROM32_INSTR_PT(561) + OR ROM32_INSTR_PT(566) OR ROM32_INSTR_PT(569) + OR ROM32_INSTR_PT(570) OR ROM32_INSTR_PT(574) + OR ROM32_INSTR_PT(577) OR ROM32_INSTR_PT(579) + OR ROM32_INSTR_PT(580) OR ROM32_INSTR_PT(584) + OR ROM32_INSTR_PT(587) OR ROM32_INSTR_PT(589) + OR ROM32_INSTR_PT(591) OR ROM32_INSTR_PT(593) + OR ROM32_INSTR_PT(596) OR ROM32_INSTR_PT(598) + OR ROM32_INSTR_PT(599) OR ROM32_INSTR_PT(600) + OR ROM32_INSTR_PT(605) OR ROM32_INSTR_PT(606) + OR ROM32_INSTR_PT(607) OR ROM32_INSTR_PT(608) + OR ROM32_INSTR_PT(609) OR ROM32_INSTR_PT(610) + OR ROM32_INSTR_PT(611) OR ROM32_INSTR_PT(614) + OR ROM32_INSTR_PT(620) OR ROM32_INSTR_PT(624) + OR ROM32_INSTR_PT(625) OR ROM32_INSTR_PT(629) + OR ROM32_INSTR_PT(632) OR ROM32_INSTR_PT(634) + OR ROM32_INSTR_PT(638) OR ROM32_INSTR_PT(640) + OR ROM32_INSTR_PT(643) OR ROM32_INSTR_PT(653) + OR ROM32_INSTR_PT(659) OR ROM32_INSTR_PT(660) + OR ROM32_INSTR_PT(663) OR ROM32_INSTR_PT(668) + OR ROM32_INSTR_PT(672) OR ROM32_INSTR_PT(678) + OR ROM32_INSTR_PT(680) OR ROM32_INSTR_PT(684) + OR ROM32_INSTR_PT(685) OR ROM32_INSTR_PT(689) + OR ROM32_INSTR_PT(698) OR ROM32_INSTR_PT(704) + OR ROM32_INSTR_PT(705) OR ROM32_INSTR_PT(708) + OR ROM32_INSTR_PT(713) OR ROM32_INSTR_PT(720) + OR ROM32_INSTR_PT(728) OR ROM32_INSTR_PT(733) + OR ROM32_INSTR_PT(751) OR ROM32_INSTR_PT(752) + OR ROM32_INSTR_PT(753) OR ROM32_INSTR_PT(759) + OR ROM32_INSTR_PT(774) OR ROM32_INSTR_PT(785) + OR ROM32_INSTR_PT(787) OR ROM32_INSTR_PT(790) + OR ROM32_INSTR_PT(795) OR ROM32_INSTR_PT(799) + OR ROM32_INSTR_PT(801) OR ROM32_INSTR_PT(803) + OR ROM32_INSTR_PT(805) OR ROM32_INSTR_PT(807) + OR ROM32_INSTR_PT(812) OR ROM32_INSTR_PT(817) + OR ROM32_INSTR_PT(819) OR ROM32_INSTR_PT(823) + OR ROM32_INSTR_PT(845) OR ROM32_INSTR_PT(847) + OR ROM32_INSTR_PT(851) OR ROM32_INSTR_PT(853) + OR ROM32_INSTR_PT(854) OR ROM32_INSTR_PT(869) + OR ROM32_INSTR_PT(871) OR ROM32_INSTR_PT(878) + OR ROM32_INSTR_PT(881) OR ROM32_INSTR_PT(889) + ); +MQQ1858:TEMPLATE(3) <= + (ROM32_INSTR_PT(4) OR ROM32_INSTR_PT(5) + OR ROM32_INSTR_PT(6) OR ROM32_INSTR_PT(7) + OR ROM32_INSTR_PT(8) OR ROM32_INSTR_PT(9) + OR ROM32_INSTR_PT(10) OR ROM32_INSTR_PT(13) + OR ROM32_INSTR_PT(14) OR ROM32_INSTR_PT(16) + OR ROM32_INSTR_PT(17) OR ROM32_INSTR_PT(18) + OR ROM32_INSTR_PT(20) OR ROM32_INSTR_PT(23) + OR ROM32_INSTR_PT(26) OR ROM32_INSTR_PT(27) + OR ROM32_INSTR_PT(28) OR ROM32_INSTR_PT(31) + OR ROM32_INSTR_PT(32) OR ROM32_INSTR_PT(33) + OR ROM32_INSTR_PT(35) OR ROM32_INSTR_PT(37) + OR ROM32_INSTR_PT(38) OR ROM32_INSTR_PT(39) + OR ROM32_INSTR_PT(41) OR ROM32_INSTR_PT(42) + OR ROM32_INSTR_PT(43) OR ROM32_INSTR_PT(45) + OR ROM32_INSTR_PT(49) OR ROM32_INSTR_PT(52) + OR ROM32_INSTR_PT(53) OR ROM32_INSTR_PT(56) + OR ROM32_INSTR_PT(57) OR ROM32_INSTR_PT(59) + OR ROM32_INSTR_PT(62) OR ROM32_INSTR_PT(63) + OR ROM32_INSTR_PT(66) OR ROM32_INSTR_PT(67) + OR ROM32_INSTR_PT(70) OR ROM32_INSTR_PT(72) + OR ROM32_INSTR_PT(73) OR ROM32_INSTR_PT(74) + OR ROM32_INSTR_PT(77) OR ROM32_INSTR_PT(78) + OR ROM32_INSTR_PT(79) OR ROM32_INSTR_PT(80) + OR ROM32_INSTR_PT(83) OR ROM32_INSTR_PT(84) + OR ROM32_INSTR_PT(85) OR ROM32_INSTR_PT(87) + OR ROM32_INSTR_PT(90) OR ROM32_INSTR_PT(92) + OR ROM32_INSTR_PT(93) OR ROM32_INSTR_PT(95) + OR ROM32_INSTR_PT(97) OR ROM32_INSTR_PT(98) + OR ROM32_INSTR_PT(99) OR ROM32_INSTR_PT(101) + OR ROM32_INSTR_PT(102) OR ROM32_INSTR_PT(103) + OR ROM32_INSTR_PT(105) OR ROM32_INSTR_PT(109) + OR ROM32_INSTR_PT(110) OR ROM32_INSTR_PT(111) + OR ROM32_INSTR_PT(114) OR ROM32_INSTR_PT(115) + OR ROM32_INSTR_PT(116) OR ROM32_INSTR_PT(117) + OR ROM32_INSTR_PT(118) OR ROM32_INSTR_PT(119) + OR ROM32_INSTR_PT(122) OR ROM32_INSTR_PT(124) + OR ROM32_INSTR_PT(127) OR ROM32_INSTR_PT(130) + OR ROM32_INSTR_PT(131) OR ROM32_INSTR_PT(134) + OR ROM32_INSTR_PT(139) OR ROM32_INSTR_PT(141) + OR ROM32_INSTR_PT(144) OR ROM32_INSTR_PT(145) + OR ROM32_INSTR_PT(146) OR ROM32_INSTR_PT(147) + OR ROM32_INSTR_PT(148) OR ROM32_INSTR_PT(150) + OR ROM32_INSTR_PT(151) OR ROM32_INSTR_PT(153) + OR ROM32_INSTR_PT(155) OR ROM32_INSTR_PT(158) + OR ROM32_INSTR_PT(162) OR ROM32_INSTR_PT(163) + OR ROM32_INSTR_PT(164) OR ROM32_INSTR_PT(165) + OR ROM32_INSTR_PT(166) OR ROM32_INSTR_PT(169) + OR ROM32_INSTR_PT(171) OR ROM32_INSTR_PT(172) + OR ROM32_INSTR_PT(173) OR ROM32_INSTR_PT(174) + OR ROM32_INSTR_PT(176) OR ROM32_INSTR_PT(177) + OR ROM32_INSTR_PT(178) OR ROM32_INSTR_PT(179) + OR ROM32_INSTR_PT(180) OR ROM32_INSTR_PT(181) + OR ROM32_INSTR_PT(184) OR ROM32_INSTR_PT(185) + OR ROM32_INSTR_PT(186) OR ROM32_INSTR_PT(187) + OR ROM32_INSTR_PT(189) OR ROM32_INSTR_PT(192) + OR ROM32_INSTR_PT(194) OR ROM32_INSTR_PT(199) + OR ROM32_INSTR_PT(200) OR ROM32_INSTR_PT(202) + OR ROM32_INSTR_PT(203) OR ROM32_INSTR_PT(205) + OR ROM32_INSTR_PT(206) OR ROM32_INSTR_PT(207) + OR ROM32_INSTR_PT(208) OR ROM32_INSTR_PT(209) + OR ROM32_INSTR_PT(210) OR ROM32_INSTR_PT(212) + OR ROM32_INSTR_PT(216) OR ROM32_INSTR_PT(218) + OR ROM32_INSTR_PT(219) OR ROM32_INSTR_PT(220) + OR ROM32_INSTR_PT(222) OR ROM32_INSTR_PT(223) + OR ROM32_INSTR_PT(224) OR ROM32_INSTR_PT(226) + OR ROM32_INSTR_PT(227) OR ROM32_INSTR_PT(228) + OR ROM32_INSTR_PT(229) OR ROM32_INSTR_PT(230) + OR ROM32_INSTR_PT(232) OR ROM32_INSTR_PT(233) + OR ROM32_INSTR_PT(235) OR ROM32_INSTR_PT(238) + OR ROM32_INSTR_PT(240) OR ROM32_INSTR_PT(242) + OR ROM32_INSTR_PT(244) OR ROM32_INSTR_PT(245) + OR ROM32_INSTR_PT(249) OR ROM32_INSTR_PT(250) + OR ROM32_INSTR_PT(251) OR ROM32_INSTR_PT(252) + OR ROM32_INSTR_PT(254) OR ROM32_INSTR_PT(255) + OR ROM32_INSTR_PT(256) OR ROM32_INSTR_PT(257) + OR ROM32_INSTR_PT(259) OR ROM32_INSTR_PT(261) + OR ROM32_INSTR_PT(262) OR ROM32_INSTR_PT(264) + OR ROM32_INSTR_PT(266) OR ROM32_INSTR_PT(267) + OR ROM32_INSTR_PT(268) OR ROM32_INSTR_PT(269) + OR ROM32_INSTR_PT(270) OR ROM32_INSTR_PT(271) + OR ROM32_INSTR_PT(272) OR ROM32_INSTR_PT(273) + OR ROM32_INSTR_PT(275) OR ROM32_INSTR_PT(278) + OR ROM32_INSTR_PT(279) OR ROM32_INSTR_PT(280) + OR ROM32_INSTR_PT(284) OR ROM32_INSTR_PT(285) + OR ROM32_INSTR_PT(288) OR ROM32_INSTR_PT(289) + OR ROM32_INSTR_PT(290) OR ROM32_INSTR_PT(291) + OR ROM32_INSTR_PT(294) OR ROM32_INSTR_PT(295) + OR ROM32_INSTR_PT(297) OR ROM32_INSTR_PT(299) + OR ROM32_INSTR_PT(301) OR ROM32_INSTR_PT(302) + OR ROM32_INSTR_PT(303) OR ROM32_INSTR_PT(305) + OR ROM32_INSTR_PT(307) OR ROM32_INSTR_PT(309) + OR ROM32_INSTR_PT(311) OR ROM32_INSTR_PT(313) + OR ROM32_INSTR_PT(318) OR ROM32_INSTR_PT(322) + OR ROM32_INSTR_PT(323) OR ROM32_INSTR_PT(325) + OR ROM32_INSTR_PT(328) OR ROM32_INSTR_PT(329) + OR ROM32_INSTR_PT(332) OR ROM32_INSTR_PT(335) + OR ROM32_INSTR_PT(337) OR ROM32_INSTR_PT(338) + OR ROM32_INSTR_PT(339) OR ROM32_INSTR_PT(344) + OR ROM32_INSTR_PT(346) OR ROM32_INSTR_PT(348) + OR ROM32_INSTR_PT(350) OR ROM32_INSTR_PT(357) + OR ROM32_INSTR_PT(361) OR ROM32_INSTR_PT(362) + OR ROM32_INSTR_PT(363) OR ROM32_INSTR_PT(366) + OR ROM32_INSTR_PT(367) OR ROM32_INSTR_PT(368) + OR ROM32_INSTR_PT(371) OR ROM32_INSTR_PT(373) + OR ROM32_INSTR_PT(374) OR ROM32_INSTR_PT(376) + OR ROM32_INSTR_PT(378) OR ROM32_INSTR_PT(379) + OR ROM32_INSTR_PT(381) OR ROM32_INSTR_PT(382) + OR ROM32_INSTR_PT(383) OR ROM32_INSTR_PT(386) + OR ROM32_INSTR_PT(387) OR ROM32_INSTR_PT(388) + OR ROM32_INSTR_PT(390) OR ROM32_INSTR_PT(392) + OR ROM32_INSTR_PT(393) OR ROM32_INSTR_PT(394) + OR ROM32_INSTR_PT(395) OR ROM32_INSTR_PT(396) + OR ROM32_INSTR_PT(398) OR ROM32_INSTR_PT(400) + OR ROM32_INSTR_PT(401) OR ROM32_INSTR_PT(402) + OR ROM32_INSTR_PT(404) OR ROM32_INSTR_PT(405) + OR ROM32_INSTR_PT(406) OR ROM32_INSTR_PT(409) + OR ROM32_INSTR_PT(411) OR ROM32_INSTR_PT(412) + OR ROM32_INSTR_PT(415) OR ROM32_INSTR_PT(416) + OR ROM32_INSTR_PT(417) OR ROM32_INSTR_PT(418) + OR ROM32_INSTR_PT(419) OR ROM32_INSTR_PT(421) + OR ROM32_INSTR_PT(422) OR ROM32_INSTR_PT(423) + OR ROM32_INSTR_PT(424) OR ROM32_INSTR_PT(425) + OR ROM32_INSTR_PT(426) OR ROM32_INSTR_PT(433) + OR ROM32_INSTR_PT(434) OR ROM32_INSTR_PT(435) + OR ROM32_INSTR_PT(436) OR ROM32_INSTR_PT(437) + OR ROM32_INSTR_PT(438) OR ROM32_INSTR_PT(441) + OR ROM32_INSTR_PT(442) OR ROM32_INSTR_PT(443) + OR ROM32_INSTR_PT(446) OR ROM32_INSTR_PT(451) + OR ROM32_INSTR_PT(452) OR ROM32_INSTR_PT(453) + OR ROM32_INSTR_PT(454) OR ROM32_INSTR_PT(456) + OR ROM32_INSTR_PT(458) OR ROM32_INSTR_PT(461) + OR ROM32_INSTR_PT(463) OR ROM32_INSTR_PT(464) + OR ROM32_INSTR_PT(465) OR ROM32_INSTR_PT(467) + OR ROM32_INSTR_PT(468) OR ROM32_INSTR_PT(469) + OR ROM32_INSTR_PT(471) OR ROM32_INSTR_PT(472) + OR ROM32_INSTR_PT(474) OR ROM32_INSTR_PT(475) + OR ROM32_INSTR_PT(476) OR ROM32_INSTR_PT(478) + OR ROM32_INSTR_PT(479) OR ROM32_INSTR_PT(480) + OR ROM32_INSTR_PT(481) OR ROM32_INSTR_PT(482) + OR ROM32_INSTR_PT(484) OR ROM32_INSTR_PT(486) + OR ROM32_INSTR_PT(489) OR ROM32_INSTR_PT(490) + OR ROM32_INSTR_PT(494) OR ROM32_INSTR_PT(495) + OR ROM32_INSTR_PT(496) OR ROM32_INSTR_PT(497) + OR ROM32_INSTR_PT(502) OR ROM32_INSTR_PT(503) + OR ROM32_INSTR_PT(505) OR ROM32_INSTR_PT(506) + OR ROM32_INSTR_PT(507) OR ROM32_INSTR_PT(508) + OR ROM32_INSTR_PT(513) OR ROM32_INSTR_PT(514) + OR ROM32_INSTR_PT(517) OR ROM32_INSTR_PT(519) + OR ROM32_INSTR_PT(520) OR ROM32_INSTR_PT(521) + OR ROM32_INSTR_PT(522) OR ROM32_INSTR_PT(524) + OR ROM32_INSTR_PT(532) OR ROM32_INSTR_PT(534) + OR ROM32_INSTR_PT(537) OR ROM32_INSTR_PT(539) + OR ROM32_INSTR_PT(541) OR ROM32_INSTR_PT(544) + OR ROM32_INSTR_PT(547) OR ROM32_INSTR_PT(549) + OR ROM32_INSTR_PT(550) OR ROM32_INSTR_PT(551) + OR ROM32_INSTR_PT(552) OR ROM32_INSTR_PT(554) + OR ROM32_INSTR_PT(556) OR ROM32_INSTR_PT(557) + OR ROM32_INSTR_PT(558) OR ROM32_INSTR_PT(561) + OR ROM32_INSTR_PT(562) OR ROM32_INSTR_PT(563) + OR ROM32_INSTR_PT(566) OR ROM32_INSTR_PT(568) + OR ROM32_INSTR_PT(569) OR ROM32_INSTR_PT(570) + OR ROM32_INSTR_PT(571) OR ROM32_INSTR_PT(574) + OR ROM32_INSTR_PT(575) OR ROM32_INSTR_PT(577) + OR ROM32_INSTR_PT(578) OR ROM32_INSTR_PT(579) + OR ROM32_INSTR_PT(580) OR ROM32_INSTR_PT(581) + OR ROM32_INSTR_PT(582) OR ROM32_INSTR_PT(583) + OR ROM32_INSTR_PT(584) OR ROM32_INSTR_PT(585) + OR ROM32_INSTR_PT(586) OR ROM32_INSTR_PT(587) + OR ROM32_INSTR_PT(588) OR ROM32_INSTR_PT(590) + OR ROM32_INSTR_PT(591) OR ROM32_INSTR_PT(593) + OR ROM32_INSTR_PT(595) OR ROM32_INSTR_PT(596) + OR ROM32_INSTR_PT(598) OR ROM32_INSTR_PT(599) + OR ROM32_INSTR_PT(600) OR ROM32_INSTR_PT(602) + OR ROM32_INSTR_PT(604) OR ROM32_INSTR_PT(605) + OR ROM32_INSTR_PT(606) OR ROM32_INSTR_PT(607) + OR ROM32_INSTR_PT(608) OR ROM32_INSTR_PT(609) + OR ROM32_INSTR_PT(610) OR ROM32_INSTR_PT(611) + OR ROM32_INSTR_PT(612) OR ROM32_INSTR_PT(614) + OR ROM32_INSTR_PT(620) OR ROM32_INSTR_PT(621) + OR ROM32_INSTR_PT(624) OR ROM32_INSTR_PT(625) + OR ROM32_INSTR_PT(626) OR ROM32_INSTR_PT(629) + OR ROM32_INSTR_PT(630) OR ROM32_INSTR_PT(632) + OR ROM32_INSTR_PT(634) OR ROM32_INSTR_PT(638) + OR ROM32_INSTR_PT(639) OR ROM32_INSTR_PT(640) + OR ROM32_INSTR_PT(642) OR ROM32_INSTR_PT(643) + OR ROM32_INSTR_PT(644) OR ROM32_INSTR_PT(653) + OR ROM32_INSTR_PT(657) OR ROM32_INSTR_PT(659) + OR ROM32_INSTR_PT(660) OR ROM32_INSTR_PT(663) + OR ROM32_INSTR_PT(664) OR ROM32_INSTR_PT(666) + OR ROM32_INSTR_PT(668) OR ROM32_INSTR_PT(672) + OR ROM32_INSTR_PT(677) OR ROM32_INSTR_PT(680) + OR ROM32_INSTR_PT(684) OR ROM32_INSTR_PT(689) + OR ROM32_INSTR_PT(692) OR ROM32_INSTR_PT(698) + OR ROM32_INSTR_PT(702) OR ROM32_INSTR_PT(704) + OR ROM32_INSTR_PT(708) OR ROM32_INSTR_PT(713) + OR ROM32_INSTR_PT(718) OR ROM32_INSTR_PT(719) + OR ROM32_INSTR_PT(720) OR ROM32_INSTR_PT(726) + OR ROM32_INSTR_PT(728) OR ROM32_INSTR_PT(729) + OR ROM32_INSTR_PT(736) OR ROM32_INSTR_PT(751) + OR ROM32_INSTR_PT(752) OR ROM32_INSTR_PT(753) + OR ROM32_INSTR_PT(755) OR ROM32_INSTR_PT(759) + OR ROM32_INSTR_PT(762) OR ROM32_INSTR_PT(770) + OR ROM32_INSTR_PT(774) OR ROM32_INSTR_PT(787) + OR ROM32_INSTR_PT(790) OR ROM32_INSTR_PT(792) + OR ROM32_INSTR_PT(803) OR ROM32_INSTR_PT(805) + OR ROM32_INSTR_PT(807) OR ROM32_INSTR_PT(812) + OR ROM32_INSTR_PT(817) OR ROM32_INSTR_PT(819) + OR ROM32_INSTR_PT(823) OR ROM32_INSTR_PT(831) + OR ROM32_INSTR_PT(845) OR ROM32_INSTR_PT(853) + OR ROM32_INSTR_PT(854) OR ROM32_INSTR_PT(855) + OR ROM32_INSTR_PT(857) OR ROM32_INSTR_PT(862) + OR ROM32_INSTR_PT(869) OR ROM32_INSTR_PT(870) + OR ROM32_INSTR_PT(878) OR ROM32_INSTR_PT(881) + ); +MQQ1859:TEMPLATE(4) <= + (ROM32_INSTR_PT(4) OR ROM32_INSTR_PT(5) + OR ROM32_INSTR_PT(6) OR ROM32_INSTR_PT(7) + OR ROM32_INSTR_PT(13) OR ROM32_INSTR_PT(14) + OR ROM32_INSTR_PT(18) OR ROM32_INSTR_PT(23) + OR ROM32_INSTR_PT(27) OR ROM32_INSTR_PT(28) + OR ROM32_INSTR_PT(29) OR ROM32_INSTR_PT(31) + OR ROM32_INSTR_PT(33) OR ROM32_INSTR_PT(35) + OR ROM32_INSTR_PT(38) OR ROM32_INSTR_PT(39) + OR ROM32_INSTR_PT(41) OR ROM32_INSTR_PT(42) + OR ROM32_INSTR_PT(43) OR ROM32_INSTR_PT(45) + OR ROM32_INSTR_PT(53) OR ROM32_INSTR_PT(56) + OR ROM32_INSTR_PT(57) OR ROM32_INSTR_PT(62) + OR ROM32_INSTR_PT(68) OR ROM32_INSTR_PT(70) + OR ROM32_INSTR_PT(72) OR ROM32_INSTR_PT(76) + OR ROM32_INSTR_PT(79) OR ROM32_INSTR_PT(80) + OR ROM32_INSTR_PT(81) OR ROM32_INSTR_PT(83) + OR ROM32_INSTR_PT(85) OR ROM32_INSTR_PT(92) + OR ROM32_INSTR_PT(95) OR ROM32_INSTR_PT(97) + OR ROM32_INSTR_PT(98) OR ROM32_INSTR_PT(101) + OR ROM32_INSTR_PT(102) OR ROM32_INSTR_PT(105) + OR ROM32_INSTR_PT(109) OR ROM32_INSTR_PT(110) + OR ROM32_INSTR_PT(111) OR ROM32_INSTR_PT(113) + OR ROM32_INSTR_PT(117) OR ROM32_INSTR_PT(120) + OR ROM32_INSTR_PT(122) OR ROM32_INSTR_PT(124) + OR ROM32_INSTR_PT(128) OR ROM32_INSTR_PT(130) + OR ROM32_INSTR_PT(138) OR ROM32_INSTR_PT(139) + OR ROM32_INSTR_PT(141) OR ROM32_INSTR_PT(142) + OR ROM32_INSTR_PT(144) OR ROM32_INSTR_PT(145) + OR ROM32_INSTR_PT(146) OR ROM32_INSTR_PT(147) + OR ROM32_INSTR_PT(150) OR ROM32_INSTR_PT(151) + OR ROM32_INSTR_PT(153) OR ROM32_INSTR_PT(155) + OR ROM32_INSTR_PT(158) OR ROM32_INSTR_PT(159) + OR ROM32_INSTR_PT(162) OR ROM32_INSTR_PT(163) + OR ROM32_INSTR_PT(165) OR ROM32_INSTR_PT(166) + OR ROM32_INSTR_PT(172) OR ROM32_INSTR_PT(173) + OR ROM32_INSTR_PT(174) OR ROM32_INSTR_PT(175) + OR ROM32_INSTR_PT(176) OR ROM32_INSTR_PT(177) + OR ROM32_INSTR_PT(178) OR ROM32_INSTR_PT(180) + OR ROM32_INSTR_PT(181) OR ROM32_INSTR_PT(185) + OR ROM32_INSTR_PT(186) OR ROM32_INSTR_PT(187) + OR ROM32_INSTR_PT(189) OR ROM32_INSTR_PT(192) + OR ROM32_INSTR_PT(193) OR ROM32_INSTR_PT(194) + OR ROM32_INSTR_PT(199) OR ROM32_INSTR_PT(203) + OR ROM32_INSTR_PT(205) OR ROM32_INSTR_PT(206) + OR ROM32_INSTR_PT(207) OR ROM32_INSTR_PT(208) + OR ROM32_INSTR_PT(209) OR ROM32_INSTR_PT(210) + OR ROM32_INSTR_PT(212) OR ROM32_INSTR_PT(218) + OR ROM32_INSTR_PT(222) OR ROM32_INSTR_PT(226) + OR ROM32_INSTR_PT(228) OR ROM32_INSTR_PT(229) + OR ROM32_INSTR_PT(230) OR ROM32_INSTR_PT(232) + OR ROM32_INSTR_PT(233) OR ROM32_INSTR_PT(235) + OR ROM32_INSTR_PT(237) OR ROM32_INSTR_PT(240) + OR ROM32_INSTR_PT(242) OR ROM32_INSTR_PT(245) + OR ROM32_INSTR_PT(249) OR ROM32_INSTR_PT(251) + OR ROM32_INSTR_PT(252) OR ROM32_INSTR_PT(254) + OR ROM32_INSTR_PT(255) OR ROM32_INSTR_PT(256) + OR ROM32_INSTR_PT(257) OR ROM32_INSTR_PT(262) + OR ROM32_INSTR_PT(266) OR ROM32_INSTR_PT(268) + OR ROM32_INSTR_PT(272) OR ROM32_INSTR_PT(275) + OR ROM32_INSTR_PT(279) OR ROM32_INSTR_PT(285) + OR ROM32_INSTR_PT(287) OR ROM32_INSTR_PT(289) + OR ROM32_INSTR_PT(290) OR ROM32_INSTR_PT(291) + OR ROM32_INSTR_PT(292) OR ROM32_INSTR_PT(294) + OR ROM32_INSTR_PT(302) OR ROM32_INSTR_PT(305) + OR ROM32_INSTR_PT(307) OR ROM32_INSTR_PT(309) + OR ROM32_INSTR_PT(311) OR ROM32_INSTR_PT(318) + OR ROM32_INSTR_PT(322) OR ROM32_INSTR_PT(323) + OR ROM32_INSTR_PT(325) OR ROM32_INSTR_PT(329) + OR ROM32_INSTR_PT(332) OR ROM32_INSTR_PT(335) + OR ROM32_INSTR_PT(337) OR ROM32_INSTR_PT(338) + OR ROM32_INSTR_PT(339) OR ROM32_INSTR_PT(344) + OR ROM32_INSTR_PT(346) OR ROM32_INSTR_PT(350) + OR ROM32_INSTR_PT(356) OR ROM32_INSTR_PT(357) + OR ROM32_INSTR_PT(358) OR ROM32_INSTR_PT(359) + OR ROM32_INSTR_PT(362) OR ROM32_INSTR_PT(363) + OR ROM32_INSTR_PT(365) OR ROM32_INSTR_PT(366) + OR ROM32_INSTR_PT(367) OR ROM32_INSTR_PT(368) + OR ROM32_INSTR_PT(370) OR ROM32_INSTR_PT(373) + OR ROM32_INSTR_PT(374) OR ROM32_INSTR_PT(376) + OR ROM32_INSTR_PT(378) OR ROM32_INSTR_PT(381) + OR ROM32_INSTR_PT(382) OR ROM32_INSTR_PT(386) + OR ROM32_INSTR_PT(387) OR ROM32_INSTR_PT(388) + OR ROM32_INSTR_PT(391) OR ROM32_INSTR_PT(393) + OR ROM32_INSTR_PT(394) OR ROM32_INSTR_PT(395) + OR ROM32_INSTR_PT(398) OR ROM32_INSTR_PT(399) + OR ROM32_INSTR_PT(400) OR ROM32_INSTR_PT(402) + OR ROM32_INSTR_PT(404) OR ROM32_INSTR_PT(405) + OR ROM32_INSTR_PT(409) OR ROM32_INSTR_PT(415) + OR ROM32_INSTR_PT(416) OR ROM32_INSTR_PT(417) + OR ROM32_INSTR_PT(418) OR ROM32_INSTR_PT(419) + OR ROM32_INSTR_PT(422) OR ROM32_INSTR_PT(423) + OR ROM32_INSTR_PT(425) OR ROM32_INSTR_PT(426) + OR ROM32_INSTR_PT(434) OR ROM32_INSTR_PT(435) + OR ROM32_INSTR_PT(436) OR ROM32_INSTR_PT(438) + OR ROM32_INSTR_PT(441) OR ROM32_INSTR_PT(442) + OR ROM32_INSTR_PT(443) OR ROM32_INSTR_PT(446) + OR ROM32_INSTR_PT(451) OR ROM32_INSTR_PT(452) + OR ROM32_INSTR_PT(454) OR ROM32_INSTR_PT(456) + OR ROM32_INSTR_PT(458) OR ROM32_INSTR_PT(461) + OR ROM32_INSTR_PT(463) OR ROM32_INSTR_PT(464) + OR ROM32_INSTR_PT(465) OR ROM32_INSTR_PT(467) + OR ROM32_INSTR_PT(468) OR ROM32_INSTR_PT(469) + OR ROM32_INSTR_PT(471) OR ROM32_INSTR_PT(472) + OR ROM32_INSTR_PT(473) OR ROM32_INSTR_PT(474) + OR ROM32_INSTR_PT(476) OR ROM32_INSTR_PT(480) + OR ROM32_INSTR_PT(486) OR ROM32_INSTR_PT(489) + OR ROM32_INSTR_PT(496) OR ROM32_INSTR_PT(497) + OR ROM32_INSTR_PT(498) OR ROM32_INSTR_PT(503) + OR ROM32_INSTR_PT(505) OR ROM32_INSTR_PT(507) + OR ROM32_INSTR_PT(513) OR ROM32_INSTR_PT(514) + OR ROM32_INSTR_PT(517) OR ROM32_INSTR_PT(527) + OR ROM32_INSTR_PT(532) OR ROM32_INSTR_PT(537) + OR ROM32_INSTR_PT(539) OR ROM32_INSTR_PT(541) + OR ROM32_INSTR_PT(544) OR ROM32_INSTR_PT(547) + OR ROM32_INSTR_PT(549) OR ROM32_INSTR_PT(551) + OR ROM32_INSTR_PT(555) OR ROM32_INSTR_PT(557) + OR ROM32_INSTR_PT(558) OR ROM32_INSTR_PT(561) + OR ROM32_INSTR_PT(563) OR ROM32_INSTR_PT(566) + OR ROM32_INSTR_PT(569) OR ROM32_INSTR_PT(570) + OR ROM32_INSTR_PT(571) OR ROM32_INSTR_PT(574) + OR ROM32_INSTR_PT(577) OR ROM32_INSTR_PT(579) + OR ROM32_INSTR_PT(580) OR ROM32_INSTR_PT(584) + OR ROM32_INSTR_PT(586) OR ROM32_INSTR_PT(587) + OR ROM32_INSTR_PT(589) OR ROM32_INSTR_PT(591) + OR ROM32_INSTR_PT(593) OR ROM32_INSTR_PT(596) + OR ROM32_INSTR_PT(597) OR ROM32_INSTR_PT(598) + OR ROM32_INSTR_PT(599) OR ROM32_INSTR_PT(600) + OR ROM32_INSTR_PT(604) OR ROM32_INSTR_PT(605) + OR ROM32_INSTR_PT(606) OR ROM32_INSTR_PT(607) + OR ROM32_INSTR_PT(608) OR ROM32_INSTR_PT(609) + OR ROM32_INSTR_PT(610) OR ROM32_INSTR_PT(611) + OR ROM32_INSTR_PT(614) OR ROM32_INSTR_PT(620) + OR ROM32_INSTR_PT(624) OR ROM32_INSTR_PT(625) + OR ROM32_INSTR_PT(629) OR ROM32_INSTR_PT(632) + OR ROM32_INSTR_PT(634) OR ROM32_INSTR_PT(638) + OR ROM32_INSTR_PT(640) OR ROM32_INSTR_PT(641) + OR ROM32_INSTR_PT(643) OR ROM32_INSTR_PT(652) + OR ROM32_INSTR_PT(653) OR ROM32_INSTR_PT(659) + OR ROM32_INSTR_PT(660) OR ROM32_INSTR_PT(663) + OR ROM32_INSTR_PT(664) OR ROM32_INSTR_PT(668) + OR ROM32_INSTR_PT(672) OR ROM32_INSTR_PT(680) + OR ROM32_INSTR_PT(683) OR ROM32_INSTR_PT(684) + OR ROM32_INSTR_PT(689) OR ROM32_INSTR_PT(691) + OR ROM32_INSTR_PT(692) OR ROM32_INSTR_PT(697) + OR ROM32_INSTR_PT(698) OR ROM32_INSTR_PT(702) + OR ROM32_INSTR_PT(704) OR ROM32_INSTR_PT(708) + OR ROM32_INSTR_PT(711) OR ROM32_INSTR_PT(713) + OR ROM32_INSTR_PT(718) OR ROM32_INSTR_PT(720) + OR ROM32_INSTR_PT(728) OR ROM32_INSTR_PT(729) + OR ROM32_INSTR_PT(733) OR ROM32_INSTR_PT(751) + OR ROM32_INSTR_PT(752) OR ROM32_INSTR_PT(753) + OR ROM32_INSTR_PT(759) OR ROM32_INSTR_PT(763) + OR ROM32_INSTR_PT(774) OR ROM32_INSTR_PT(787) + OR ROM32_INSTR_PT(790) OR ROM32_INSTR_PT(792) + OR ROM32_INSTR_PT(795) OR ROM32_INSTR_PT(801) + OR ROM32_INSTR_PT(803) OR ROM32_INSTR_PT(805) + OR ROM32_INSTR_PT(807) OR ROM32_INSTR_PT(812) + OR ROM32_INSTR_PT(817) OR ROM32_INSTR_PT(819) + OR ROM32_INSTR_PT(823) OR ROM32_INSTR_PT(829) + OR ROM32_INSTR_PT(831) OR ROM32_INSTR_PT(845) + OR ROM32_INSTR_PT(847) OR ROM32_INSTR_PT(851) + OR ROM32_INSTR_PT(853) OR ROM32_INSTR_PT(854) + OR ROM32_INSTR_PT(857) OR ROM32_INSTR_PT(869) + OR ROM32_INSTR_PT(872) OR ROM32_INSTR_PT(878) + OR ROM32_INSTR_PT(881)); +MQQ1860:TEMPLATE(5) <= + (ROM32_INSTR_PT(3) OR ROM32_INSTR_PT(5) + OR ROM32_INSTR_PT(6) OR ROM32_INSTR_PT(7) + OR ROM32_INSTR_PT(9) OR ROM32_INSTR_PT(10) + OR ROM32_INSTR_PT(12) OR ROM32_INSTR_PT(13) + OR ROM32_INSTR_PT(14) OR ROM32_INSTR_PT(20) + OR ROM32_INSTR_PT(26) OR ROM32_INSTR_PT(33) + OR ROM32_INSTR_PT(37) OR ROM32_INSTR_PT(39) + OR ROM32_INSTR_PT(41) OR ROM32_INSTR_PT(42) + OR ROM32_INSTR_PT(45) OR ROM32_INSTR_PT(49) + OR ROM32_INSTR_PT(51) OR ROM32_INSTR_PT(52) + OR ROM32_INSTR_PT(53) OR ROM32_INSTR_PT(56) + OR ROM32_INSTR_PT(57) OR ROM32_INSTR_PT(59) + OR ROM32_INSTR_PT(63) OR ROM32_INSTR_PT(66) + OR ROM32_INSTR_PT(67) OR ROM32_INSTR_PT(72) + OR ROM32_INSTR_PT(73) OR ROM32_INSTR_PT(83) + OR ROM32_INSTR_PT(84) OR ROM32_INSTR_PT(85) + OR ROM32_INSTR_PT(87) OR ROM32_INSTR_PT(90) + OR ROM32_INSTR_PT(93) OR ROM32_INSTR_PT(96) + OR ROM32_INSTR_PT(100) OR ROM32_INSTR_PT(101) + OR ROM32_INSTR_PT(102) OR ROM32_INSTR_PT(103) + OR ROM32_INSTR_PT(106) OR ROM32_INSTR_PT(109) + OR ROM32_INSTR_PT(110) OR ROM32_INSTR_PT(115) + OR ROM32_INSTR_PT(116) OR ROM32_INSTR_PT(117) + OR ROM32_INSTR_PT(118) OR ROM32_INSTR_PT(119) + OR ROM32_INSTR_PT(124) OR ROM32_INSTR_PT(130) + OR ROM32_INSTR_PT(131) OR ROM32_INSTR_PT(135) + OR ROM32_INSTR_PT(139) OR ROM32_INSTR_PT(141) + OR ROM32_INSTR_PT(142) OR ROM32_INSTR_PT(143) + OR ROM32_INSTR_PT(144) OR ROM32_INSTR_PT(153) + OR ROM32_INSTR_PT(155) OR ROM32_INSTR_PT(158) + OR ROM32_INSTR_PT(159) OR ROM32_INSTR_PT(163) + OR ROM32_INSTR_PT(164) OR ROM32_INSTR_PT(169) + OR ROM32_INSTR_PT(170) OR ROM32_INSTR_PT(176) + OR ROM32_INSTR_PT(179) OR ROM32_INSTR_PT(180) + OR ROM32_INSTR_PT(181) OR ROM32_INSTR_PT(183) + OR ROM32_INSTR_PT(184) OR ROM32_INSTR_PT(187) + OR ROM32_INSTR_PT(192) OR ROM32_INSTR_PT(194) + OR ROM32_INSTR_PT(196) OR ROM32_INSTR_PT(199) + OR ROM32_INSTR_PT(202) OR ROM32_INSTR_PT(203) + OR ROM32_INSTR_PT(204) OR ROM32_INSTR_PT(205) + OR ROM32_INSTR_PT(206) OR ROM32_INSTR_PT(207) + OR ROM32_INSTR_PT(212) OR ROM32_INSTR_PT(216) + OR ROM32_INSTR_PT(220) OR ROM32_INSTR_PT(224) + OR ROM32_INSTR_PT(227) OR ROM32_INSTR_PT(232) + OR ROM32_INSTR_PT(233) OR ROM32_INSTR_PT(235) + OR ROM32_INSTR_PT(238) OR ROM32_INSTR_PT(241) + OR ROM32_INSTR_PT(243) OR ROM32_INSTR_PT(244) + OR ROM32_INSTR_PT(249) OR ROM32_INSTR_PT(252) + OR ROM32_INSTR_PT(254) OR ROM32_INSTR_PT(256) + OR ROM32_INSTR_PT(259) OR ROM32_INSTR_PT(260) + OR ROM32_INSTR_PT(261) OR ROM32_INSTR_PT(264) + OR ROM32_INSTR_PT(266) OR ROM32_INSTR_PT(267) + OR ROM32_INSTR_PT(268) OR ROM32_INSTR_PT(269) + OR ROM32_INSTR_PT(271) OR ROM32_INSTR_PT(274) + OR ROM32_INSTR_PT(276) OR ROM32_INSTR_PT(278) + OR ROM32_INSTR_PT(280) OR ROM32_INSTR_PT(282) + OR ROM32_INSTR_PT(284) OR ROM32_INSTR_PT(288) + OR ROM32_INSTR_PT(290) OR ROM32_INSTR_PT(293) + OR ROM32_INSTR_PT(294) OR ROM32_INSTR_PT(299) + OR ROM32_INSTR_PT(301) OR ROM32_INSTR_PT(303) + OR ROM32_INSTR_PT(306) OR ROM32_INSTR_PT(309) + OR ROM32_INSTR_PT(310) OR ROM32_INSTR_PT(318) + OR ROM32_INSTR_PT(323) OR ROM32_INSTR_PT(335) + OR ROM32_INSTR_PT(344) OR ROM32_INSTR_PT(346) + OR ROM32_INSTR_PT(348) OR ROM32_INSTR_PT(350) + OR ROM32_INSTR_PT(353) OR ROM32_INSTR_PT(356) + OR ROM32_INSTR_PT(361) OR ROM32_INSTR_PT(363) + OR ROM32_INSTR_PT(364) OR ROM32_INSTR_PT(367) + OR ROM32_INSTR_PT(371) OR ROM32_INSTR_PT(373) + OR ROM32_INSTR_PT(374) OR ROM32_INSTR_PT(376) + OR ROM32_INSTR_PT(379) OR ROM32_INSTR_PT(381) + OR ROM32_INSTR_PT(382) OR ROM32_INSTR_PT(383) + OR ROM32_INSTR_PT(386) OR ROM32_INSTR_PT(390) + OR ROM32_INSTR_PT(392) OR ROM32_INSTR_PT(394) + OR ROM32_INSTR_PT(396) OR ROM32_INSTR_PT(400) + OR ROM32_INSTR_PT(402) OR ROM32_INSTR_PT(405) + OR ROM32_INSTR_PT(406) OR ROM32_INSTR_PT(409) + OR ROM32_INSTR_PT(413) OR ROM32_INSTR_PT(415) + OR ROM32_INSTR_PT(417) OR ROM32_INSTR_PT(422) + OR ROM32_INSTR_PT(423) OR ROM32_INSTR_PT(424) + OR ROM32_INSTR_PT(425) OR ROM32_INSTR_PT(426) + OR ROM32_INSTR_PT(428) OR ROM32_INSTR_PT(430) + OR ROM32_INSTR_PT(431) OR ROM32_INSTR_PT(434) + OR ROM32_INSTR_PT(435) OR ROM32_INSTR_PT(436) + OR ROM32_INSTR_PT(438) OR ROM32_INSTR_PT(441) + OR ROM32_INSTR_PT(442) OR ROM32_INSTR_PT(443) + OR ROM32_INSTR_PT(445) OR ROM32_INSTR_PT(449) + OR ROM32_INSTR_PT(451) OR ROM32_INSTR_PT(452) + OR ROM32_INSTR_PT(453) OR ROM32_INSTR_PT(458) + OR ROM32_INSTR_PT(464) OR ROM32_INSTR_PT(469) + OR ROM32_INSTR_PT(472) OR ROM32_INSTR_PT(474) + OR ROM32_INSTR_PT(475) OR ROM32_INSTR_PT(478) + OR ROM32_INSTR_PT(479) OR ROM32_INSTR_PT(481) + OR ROM32_INSTR_PT(482) OR ROM32_INSTR_PT(484) + OR ROM32_INSTR_PT(486) OR ROM32_INSTR_PT(490) + OR ROM32_INSTR_PT(491) OR ROM32_INSTR_PT(494) + OR ROM32_INSTR_PT(495) OR ROM32_INSTR_PT(501) + OR ROM32_INSTR_PT(503) OR ROM32_INSTR_PT(507) + OR ROM32_INSTR_PT(509) OR ROM32_INSTR_PT(511) + OR ROM32_INSTR_PT(514) OR ROM32_INSTR_PT(517) + OR ROM32_INSTR_PT(520) OR ROM32_INSTR_PT(521) + OR ROM32_INSTR_PT(522) OR ROM32_INSTR_PT(524) + OR ROM32_INSTR_PT(530) OR ROM32_INSTR_PT(531) + OR ROM32_INSTR_PT(532) OR ROM32_INSTR_PT(534) + OR ROM32_INSTR_PT(541) OR ROM32_INSTR_PT(544) + OR ROM32_INSTR_PT(550) OR ROM32_INSTR_PT(551) + OR ROM32_INSTR_PT(552) OR ROM32_INSTR_PT(554) + OR ROM32_INSTR_PT(555) OR ROM32_INSTR_PT(557) + OR ROM32_INSTR_PT(562) OR ROM32_INSTR_PT(563) + OR ROM32_INSTR_PT(566) OR ROM32_INSTR_PT(569) + OR ROM32_INSTR_PT(570) OR ROM32_INSTR_PT(575) + OR ROM32_INSTR_PT(579) OR ROM32_INSTR_PT(580) + OR ROM32_INSTR_PT(581) OR ROM32_INSTR_PT(582) + OR ROM32_INSTR_PT(583) OR ROM32_INSTR_PT(584) + OR ROM32_INSTR_PT(588) OR ROM32_INSTR_PT(599) + OR ROM32_INSTR_PT(600) OR ROM32_INSTR_PT(601) + OR ROM32_INSTR_PT(602) OR ROM32_INSTR_PT(605) + OR ROM32_INSTR_PT(609) OR ROM32_INSTR_PT(610) + OR ROM32_INSTR_PT(613) OR ROM32_INSTR_PT(615) + OR ROM32_INSTR_PT(616) OR ROM32_INSTR_PT(617) + OR ROM32_INSTR_PT(620) OR ROM32_INSTR_PT(622) + OR ROM32_INSTR_PT(624) OR ROM32_INSTR_PT(626) + OR ROM32_INSTR_PT(630) OR ROM32_INSTR_PT(634) + OR ROM32_INSTR_PT(638) OR ROM32_INSTR_PT(639) + OR ROM32_INSTR_PT(642) OR ROM32_INSTR_PT(643) + OR ROM32_INSTR_PT(654) OR ROM32_INSTR_PT(660) + OR ROM32_INSTR_PT(663) OR ROM32_INSTR_PT(664) + OR ROM32_INSTR_PT(666) OR ROM32_INSTR_PT(674) + OR ROM32_INSTR_PT(677) OR ROM32_INSTR_PT(684) + OR ROM32_INSTR_PT(692) OR ROM32_INSTR_PT(693) + OR ROM32_INSTR_PT(697) OR ROM32_INSTR_PT(708) + OR ROM32_INSTR_PT(711) OR ROM32_INSTR_PT(713) + OR ROM32_INSTR_PT(718) OR ROM32_INSTR_PT(719) + OR ROM32_INSTR_PT(726) OR ROM32_INSTR_PT(729) + OR ROM32_INSTR_PT(745) OR ROM32_INSTR_PT(755) + OR ROM32_INSTR_PT(762) OR ROM32_INSTR_PT(763) + OR ROM32_INSTR_PT(792) OR ROM32_INSTR_PT(805) + OR ROM32_INSTR_PT(812) OR ROM32_INSTR_PT(818) + OR ROM32_INSTR_PT(819) OR ROM32_INSTR_PT(829) + OR ROM32_INSTR_PT(831) OR ROM32_INSTR_PT(845) + OR ROM32_INSTR_PT(853) OR ROM32_INSTR_PT(854) + OR ROM32_INSTR_PT(855) OR ROM32_INSTR_PT(857) + OR ROM32_INSTR_PT(862) OR ROM32_INSTR_PT(870) + OR ROM32_INSTR_PT(872) OR ROM32_INSTR_PT(878) + ); +MQQ1861:TEMPLATE(6) <= + ('0'); +MQQ1862:TEMPLATE(7) <= + ('0'); +MQQ1863:TEMPLATE(8) <= + ('0'); +MQQ1864:TEMPLATE(9) <= + (ROM32_INSTR_PT(6) OR ROM32_INSTR_PT(8) + OR ROM32_INSTR_PT(10) OR ROM32_INSTR_PT(12) + OR ROM32_INSTR_PT(14) OR ROM32_INSTR_PT(17) + OR ROM32_INSTR_PT(23) OR ROM32_INSTR_PT(28) + OR ROM32_INSTR_PT(35) OR ROM32_INSTR_PT(37) + OR ROM32_INSTR_PT(42) OR ROM32_INSTR_PT(45) + OR ROM32_INSTR_PT(53) OR ROM32_INSTR_PT(55) + OR ROM32_INSTR_PT(56) OR ROM32_INSTR_PT(60) + OR ROM32_INSTR_PT(63) OR ROM32_INSTR_PT(73) + OR ROM32_INSTR_PT(74) OR ROM32_INSTR_PT(85) + OR ROM32_INSTR_PT(87) OR ROM32_INSTR_PT(90) + OR ROM32_INSTR_PT(93) OR ROM32_INSTR_PT(97) + OR ROM32_INSTR_PT(100) OR ROM32_INSTR_PT(102) + OR ROM32_INSTR_PT(103) OR ROM32_INSTR_PT(105) + OR ROM32_INSTR_PT(106) OR ROM32_INSTR_PT(117) + OR ROM32_INSTR_PT(120) OR ROM32_INSTR_PT(124) + OR ROM32_INSTR_PT(130) OR ROM32_INSTR_PT(134) + OR ROM32_INSTR_PT(135) OR ROM32_INSTR_PT(141) + OR ROM32_INSTR_PT(142) OR ROM32_INSTR_PT(148) + OR ROM32_INSTR_PT(154) OR ROM32_INSTR_PT(155) + OR ROM32_INSTR_PT(162) OR ROM32_INSTR_PT(172) + OR ROM32_INSTR_PT(174) OR ROM32_INSTR_PT(175) + OR ROM32_INSTR_PT(176) OR ROM32_INSTR_PT(177) + OR ROM32_INSTR_PT(179) OR ROM32_INSTR_PT(180) + OR ROM32_INSTR_PT(181) OR ROM32_INSTR_PT(184) + OR ROM32_INSTR_PT(187) OR ROM32_INSTR_PT(192) + OR ROM32_INSTR_PT(193) OR ROM32_INSTR_PT(199) + OR ROM32_INSTR_PT(202) OR ROM32_INSTR_PT(209) + OR ROM32_INSTR_PT(214) OR ROM32_INSTR_PT(216) + OR ROM32_INSTR_PT(218) OR ROM32_INSTR_PT(222) + OR ROM32_INSTR_PT(223) OR ROM32_INSTR_PT(226) + OR ROM32_INSTR_PT(227) OR ROM32_INSTR_PT(232) + OR ROM32_INSTR_PT(238) OR ROM32_INSTR_PT(240) + OR ROM32_INSTR_PT(242) OR ROM32_INSTR_PT(244) + OR ROM32_INSTR_PT(249) OR ROM32_INSTR_PT(255) + OR ROM32_INSTR_PT(257) OR ROM32_INSTR_PT(258) + OR ROM32_INSTR_PT(260) OR ROM32_INSTR_PT(269) + OR ROM32_INSTR_PT(272) OR ROM32_INSTR_PT(273) + OR ROM32_INSTR_PT(274) OR ROM32_INSTR_PT(275) + OR ROM32_INSTR_PT(280) OR ROM32_INSTR_PT(282) + OR ROM32_INSTR_PT(283) OR ROM32_INSTR_PT(287) + OR ROM32_INSTR_PT(288) OR ROM32_INSTR_PT(293) + OR ROM32_INSTR_PT(294) OR ROM32_INSTR_PT(297) + OR ROM32_INSTR_PT(299) OR ROM32_INSTR_PT(303) + OR ROM32_INSTR_PT(309) OR ROM32_INSTR_PT(313) + OR ROM32_INSTR_PT(318) OR ROM32_INSTR_PT(319) + OR ROM32_INSTR_PT(321) OR ROM32_INSTR_PT(338) + OR ROM32_INSTR_PT(345) OR ROM32_INSTR_PT(348) + OR ROM32_INSTR_PT(353) OR ROM32_INSTR_PT(357) + OR ROM32_INSTR_PT(359) OR ROM32_INSTR_PT(362) + OR ROM32_INSTR_PT(363) OR ROM32_INSTR_PT(366) + OR ROM32_INSTR_PT(367) OR ROM32_INSTR_PT(374) + OR ROM32_INSTR_PT(377) OR ROM32_INSTR_PT(378) + OR ROM32_INSTR_PT(379) OR ROM32_INSTR_PT(382) + OR ROM32_INSTR_PT(383) OR ROM32_INSTR_PT(386) + OR ROM32_INSTR_PT(387) OR ROM32_INSTR_PT(388) + OR ROM32_INSTR_PT(391) OR ROM32_INSTR_PT(394) + OR ROM32_INSTR_PT(395) OR ROM32_INSTR_PT(399) + OR ROM32_INSTR_PT(400) OR ROM32_INSTR_PT(401) + OR ROM32_INSTR_PT(402) OR ROM32_INSTR_PT(406) + OR ROM32_INSTR_PT(409) OR ROM32_INSTR_PT(412) + OR ROM32_INSTR_PT(415) OR ROM32_INSTR_PT(416) + OR ROM32_INSTR_PT(422) OR ROM32_INSTR_PT(423) + OR ROM32_INSTR_PT(431) OR ROM32_INSTR_PT(433) + OR ROM32_INSTR_PT(434) OR ROM32_INSTR_PT(436) + OR ROM32_INSTR_PT(441) OR ROM32_INSTR_PT(443) + OR ROM32_INSTR_PT(451) OR ROM32_INSTR_PT(453) + OR ROM32_INSTR_PT(464) OR ROM32_INSTR_PT(467) + OR ROM32_INSTR_PT(469) OR ROM32_INSTR_PT(471) + OR ROM32_INSTR_PT(472) OR ROM32_INSTR_PT(475) + OR ROM32_INSTR_PT(479) OR ROM32_INSTR_PT(482) + OR ROM32_INSTR_PT(489) OR ROM32_INSTR_PT(490) + OR ROM32_INSTR_PT(491) OR ROM32_INSTR_PT(494) + OR ROM32_INSTR_PT(497) OR ROM32_INSTR_PT(498) + OR ROM32_INSTR_PT(501) OR ROM32_INSTR_PT(502) + OR ROM32_INSTR_PT(504) OR ROM32_INSTR_PT(506) + OR ROM32_INSTR_PT(514) OR ROM32_INSTR_PT(516) + OR ROM32_INSTR_PT(517) OR ROM32_INSTR_PT(519) + OR ROM32_INSTR_PT(520) OR ROM32_INSTR_PT(532) + OR ROM32_INSTR_PT(534) OR ROM32_INSTR_PT(535) + OR ROM32_INSTR_PT(543) OR ROM32_INSTR_PT(544) + OR ROM32_INSTR_PT(547) OR ROM32_INSTR_PT(550) + OR ROM32_INSTR_PT(552) OR ROM32_INSTR_PT(556) + OR ROM32_INSTR_PT(557) OR ROM32_INSTR_PT(568) + OR ROM32_INSTR_PT(570) OR ROM32_INSTR_PT(571) + OR ROM32_INSTR_PT(574) OR ROM32_INSTR_PT(575) + OR ROM32_INSTR_PT(586) OR ROM32_INSTR_PT(588) + OR ROM32_INSTR_PT(589) OR ROM32_INSTR_PT(590) + OR ROM32_INSTR_PT(600) OR ROM32_INSTR_PT(602) + OR ROM32_INSTR_PT(604) OR ROM32_INSTR_PT(606) + OR ROM32_INSTR_PT(609) OR ROM32_INSTR_PT(611) + OR ROM32_INSTR_PT(612) OR ROM32_INSTR_PT(613) + OR ROM32_INSTR_PT(621) OR ROM32_INSTR_PT(625) + OR ROM32_INSTR_PT(630) OR ROM32_INSTR_PT(639) + OR ROM32_INSTR_PT(640) OR ROM32_INSTR_PT(646) + OR ROM32_INSTR_PT(647) OR ROM32_INSTR_PT(652) + OR ROM32_INSTR_PT(659) OR ROM32_INSTR_PT(663) + OR ROM32_INSTR_PT(666) OR ROM32_INSTR_PT(677) + OR ROM32_INSTR_PT(689) OR ROM32_INSTR_PT(690) + OR ROM32_INSTR_PT(698) OR ROM32_INSTR_PT(700) + OR ROM32_INSTR_PT(733) OR ROM32_INSTR_PT(745) + OR ROM32_INSTR_PT(751) OR ROM32_INSTR_PT(753) + OR ROM32_INSTR_PT(790) OR ROM32_INSTR_PT(807) + OR ROM32_INSTR_PT(823) OR ROM32_INSTR_PT(845) + ); +MQQ1865:TEMPLATE(10) <= + (ROM32_INSTR_PT(3) OR ROM32_INSTR_PT(5) + OR ROM32_INSTR_PT(6) OR ROM32_INSTR_PT(13) + OR ROM32_INSTR_PT(14) OR ROM32_INSTR_PT(16) + OR ROM32_INSTR_PT(18) OR ROM32_INSTR_PT(32) + OR ROM32_INSTR_PT(38) OR ROM32_INSTR_PT(41) + OR ROM32_INSTR_PT(42) OR ROM32_INSTR_PT(45) + OR ROM32_INSTR_PT(51) OR ROM32_INSTR_PT(52) + OR ROM32_INSTR_PT(53) OR ROM32_INSTR_PT(57) + OR ROM32_INSTR_PT(76) OR ROM32_INSTR_PT(77) + OR ROM32_INSTR_PT(85) OR ROM32_INSTR_PT(95) + OR ROM32_INSTR_PT(99) OR ROM32_INSTR_PT(113) + OR ROM32_INSTR_PT(114) OR ROM32_INSTR_PT(117) + OR ROM32_INSTR_PT(118) OR ROM32_INSTR_PT(123) + OR ROM32_INSTR_PT(125) OR ROM32_INSTR_PT(127) + OR ROM32_INSTR_PT(128) OR ROM32_INSTR_PT(130) + OR ROM32_INSTR_PT(138) OR ROM32_INSTR_PT(139) + OR ROM32_INSTR_PT(142) OR ROM32_INSTR_PT(143) + OR ROM32_INSTR_PT(153) OR ROM32_INSTR_PT(169) + OR ROM32_INSTR_PT(171) OR ROM32_INSTR_PT(173) + OR ROM32_INSTR_PT(174) OR ROM32_INSTR_PT(180) + OR ROM32_INSTR_PT(181) OR ROM32_INSTR_PT(183) + OR ROM32_INSTR_PT(189) OR ROM32_INSTR_PT(194) + OR ROM32_INSTR_PT(200) OR ROM32_INSTR_PT(203) + OR ROM32_INSTR_PT(204) OR ROM32_INSTR_PT(214) + OR ROM32_INSTR_PT(219) OR ROM32_INSTR_PT(229) + OR ROM32_INSTR_PT(235) OR ROM32_INSTR_PT(237) + OR ROM32_INSTR_PT(240) OR ROM32_INSTR_PT(241) + OR ROM32_INSTR_PT(250) OR ROM32_INSTR_PT(251) + OR ROM32_INSTR_PT(254) OR ROM32_INSTR_PT(256) + OR ROM32_INSTR_PT(261) OR ROM32_INSTR_PT(267) + OR ROM32_INSTR_PT(270) OR ROM32_INSTR_PT(271) + OR ROM32_INSTR_PT(274) OR ROM32_INSTR_PT(276) + OR ROM32_INSTR_PT(281) OR ROM32_INSTR_PT(289) + OR ROM32_INSTR_PT(328) OR ROM32_INSTR_PT(335) + OR ROM32_INSTR_PT(361) OR ROM32_INSTR_PT(363) + OR ROM32_INSTR_PT(364) OR ROM32_INSTR_PT(365) + OR ROM32_INSTR_PT(370) OR ROM32_INSTR_PT(371) + OR ROM32_INSTR_PT(376) OR ROM32_INSTR_PT(381) + OR ROM32_INSTR_PT(390) OR ROM32_INSTR_PT(395) + OR ROM32_INSTR_PT(398) OR ROM32_INSTR_PT(400) + OR ROM32_INSTR_PT(404) OR ROM32_INSTR_PT(418) + OR ROM32_INSTR_PT(419) OR ROM32_INSTR_PT(421) + OR ROM32_INSTR_PT(436) OR ROM32_INSTR_PT(439) + OR ROM32_INSTR_PT(441) OR ROM32_INSTR_PT(446) + OR ROM32_INSTR_PT(454) OR ROM32_INSTR_PT(468) + OR ROM32_INSTR_PT(473) OR ROM32_INSTR_PT(477) + OR ROM32_INSTR_PT(478) OR ROM32_INSTR_PT(480) + OR ROM32_INSTR_PT(489) OR ROM32_INSTR_PT(503) + OR ROM32_INSTR_PT(504) OR ROM32_INSTR_PT(505) + OR ROM32_INSTR_PT(508) OR ROM32_INSTR_PT(509) + OR ROM32_INSTR_PT(517) OR ROM32_INSTR_PT(524) + OR ROM32_INSTR_PT(527) OR ROM32_INSTR_PT(531) + OR ROM32_INSTR_PT(532) OR ROM32_INSTR_PT(537) + OR ROM32_INSTR_PT(538) OR ROM32_INSTR_PT(546) + OR ROM32_INSTR_PT(551) OR ROM32_INSTR_PT(555) + OR ROM32_INSTR_PT(558) OR ROM32_INSTR_PT(562) + OR ROM32_INSTR_PT(570) OR ROM32_INSTR_PT(578) + OR ROM32_INSTR_PT(582) OR ROM32_INSTR_PT(585) + OR ROM32_INSTR_PT(591) OR ROM32_INSTR_PT(593) + OR ROM32_INSTR_PT(595) OR ROM32_INSTR_PT(597) + OR ROM32_INSTR_PT(598) OR ROM32_INSTR_PT(603) + OR ROM32_INSTR_PT(608) OR ROM32_INSTR_PT(615) + OR ROM32_INSTR_PT(624) OR ROM32_INSTR_PT(626) + OR ROM32_INSTR_PT(629) OR ROM32_INSTR_PT(635) + OR ROM32_INSTR_PT(641) OR ROM32_INSTR_PT(642) + OR ROM32_INSTR_PT(644) OR ROM32_INSTR_PT(654) + OR ROM32_INSTR_PT(680) OR ROM32_INSTR_PT(683) + OR ROM32_INSTR_PT(689) OR ROM32_INSTR_PT(708) + OR ROM32_INSTR_PT(713) OR ROM32_INSTR_PT(718) + OR ROM32_INSTR_PT(720) OR ROM32_INSTR_PT(728) + OR ROM32_INSTR_PT(729) OR ROM32_INSTR_PT(731) + OR ROM32_INSTR_PT(755) OR ROM32_INSTR_PT(763) + OR ROM32_INSTR_PT(819) OR ROM32_INSTR_PT(857) + OR ROM32_INSTR_PT(872)); +MQQ1866:TEMPLATE(11) <= + ('0'); +MQQ1867:TEMPLATE(12) <= + ('0'); +MQQ1868:TEMPLATE(13) <= + ('0'); +MQQ1869:TEMPLATE(14) <= + (ROM32_INSTR_PT(6) OR ROM32_INSTR_PT(10) + OR ROM32_INSTR_PT(12) OR ROM32_INSTR_PT(14) + OR ROM32_INSTR_PT(16) OR ROM32_INSTR_PT(20) + OR ROM32_INSTR_PT(23) OR ROM32_INSTR_PT(26) + OR ROM32_INSTR_PT(32) OR ROM32_INSTR_PT(34) + OR ROM32_INSTR_PT(35) OR ROM32_INSTR_PT(37) + OR ROM32_INSTR_PT(42) OR ROM32_INSTR_PT(52) + OR ROM32_INSTR_PT(53) OR ROM32_INSTR_PT(55) + OR ROM32_INSTR_PT(56) OR ROM32_INSTR_PT(63) + OR ROM32_INSTR_PT(67) OR ROM32_INSTR_PT(73) + OR ROM32_INSTR_PT(77) OR ROM32_INSTR_PT(79) + OR ROM32_INSTR_PT(85) OR ROM32_INSTR_PT(87) + OR ROM32_INSTR_PT(90) OR ROM32_INSTR_PT(92) + OR ROM32_INSTR_PT(93) OR ROM32_INSTR_PT(97) + OR ROM32_INSTR_PT(99) OR ROM32_INSTR_PT(103) + OR ROM32_INSTR_PT(105) OR ROM32_INSTR_PT(111) + OR ROM32_INSTR_PT(114) OR ROM32_INSTR_PT(115) + OR ROM32_INSTR_PT(118) OR ROM32_INSTR_PT(119) + OR ROM32_INSTR_PT(125) OR ROM32_INSTR_PT(127) + OR ROM32_INSTR_PT(130) OR ROM32_INSTR_PT(138) + OR ROM32_INSTR_PT(143) OR ROM32_INSTR_PT(155) + OR ROM32_INSTR_PT(169) OR ROM32_INSTR_PT(171) + OR ROM32_INSTR_PT(172) OR ROM32_INSTR_PT(174) + OR ROM32_INSTR_PT(179) OR ROM32_INSTR_PT(181) + OR ROM32_INSTR_PT(184) OR ROM32_INSTR_PT(187) + OR ROM32_INSTR_PT(196) OR ROM32_INSTR_PT(200) + OR ROM32_INSTR_PT(202) OR ROM32_INSTR_PT(209) + OR ROM32_INSTR_PT(214) OR ROM32_INSTR_PT(216) + OR ROM32_INSTR_PT(218) OR ROM32_INSTR_PT(219) + OR ROM32_INSTR_PT(224) OR ROM32_INSTR_PT(227) + OR ROM32_INSTR_PT(229) OR ROM32_INSTR_PT(232) + OR ROM32_INSTR_PT(238) OR ROM32_INSTR_PT(240) + OR ROM32_INSTR_PT(250) OR ROM32_INSTR_PT(257) + OR ROM32_INSTR_PT(259) OR ROM32_INSTR_PT(261) + OR ROM32_INSTR_PT(264) OR ROM32_INSTR_PT(267) + OR ROM32_INSTR_PT(269) OR ROM32_INSTR_PT(270) + OR ROM32_INSTR_PT(271) OR ROM32_INSTR_PT(272) + OR ROM32_INSTR_PT(273) OR ROM32_INSTR_PT(274) + OR ROM32_INSTR_PT(275) OR ROM32_INSTR_PT(278) + OR ROM32_INSTR_PT(280) OR ROM32_INSTR_PT(283) + OR ROM32_INSTR_PT(284) OR ROM32_INSTR_PT(288) + OR ROM32_INSTR_PT(290) OR ROM32_INSTR_PT(295) + OR ROM32_INSTR_PT(299) OR ROM32_INSTR_PT(303) + OR ROM32_INSTR_PT(309) OR ROM32_INSTR_PT(313) + OR ROM32_INSTR_PT(321) OR ROM32_INSTR_PT(328) + OR ROM32_INSTR_PT(345) OR ROM32_INSTR_PT(348) + OR ROM32_INSTR_PT(361) OR ROM32_INSTR_PT(362) + OR ROM32_INSTR_PT(363) OR ROM32_INSTR_PT(366) + OR ROM32_INSTR_PT(367) OR ROM32_INSTR_PT(368) + OR ROM32_INSTR_PT(370) OR ROM32_INSTR_PT(371) + OR ROM32_INSTR_PT(379) OR ROM32_INSTR_PT(383) + OR ROM32_INSTR_PT(387) OR ROM32_INSTR_PT(390) + OR ROM32_INSTR_PT(392) OR ROM32_INSTR_PT(394) + OR ROM32_INSTR_PT(395) OR ROM32_INSTR_PT(396) + OR ROM32_INSTR_PT(400) OR ROM32_INSTR_PT(401) + OR ROM32_INSTR_PT(402) OR ROM32_INSTR_PT(406) + OR ROM32_INSTR_PT(411) OR ROM32_INSTR_PT(412) + OR ROM32_INSTR_PT(418) OR ROM32_INSTR_PT(421) + OR ROM32_INSTR_PT(423) OR ROM32_INSTR_PT(424) + OR ROM32_INSTR_PT(433) OR ROM32_INSTR_PT(436) + OR ROM32_INSTR_PT(441) OR ROM32_INSTR_PT(445) + OR ROM32_INSTR_PT(449) OR ROM32_INSTR_PT(453) + OR ROM32_INSTR_PT(456) OR ROM32_INSTR_PT(464) + OR ROM32_INSTR_PT(469) OR ROM32_INSTR_PT(472) + OR ROM32_INSTR_PT(475) OR ROM32_INSTR_PT(476) + OR ROM32_INSTR_PT(479) OR ROM32_INSTR_PT(480) + OR ROM32_INSTR_PT(481) OR ROM32_INSTR_PT(482) + OR ROM32_INSTR_PT(484) OR ROM32_INSTR_PT(490) + OR ROM32_INSTR_PT(494) OR ROM32_INSTR_PT(497) + OR ROM32_INSTR_PT(502) OR ROM32_INSTR_PT(508) + OR ROM32_INSTR_PT(514) OR ROM32_INSTR_PT(517) + OR ROM32_INSTR_PT(519) OR ROM32_INSTR_PT(520) + OR ROM32_INSTR_PT(521) OR ROM32_INSTR_PT(522) + OR ROM32_INSTR_PT(524) OR ROM32_INSTR_PT(532) + OR ROM32_INSTR_PT(534) OR ROM32_INSTR_PT(535) + OR ROM32_INSTR_PT(536) OR ROM32_INSTR_PT(541) + OR ROM32_INSTR_PT(543) OR ROM32_INSTR_PT(546) + OR ROM32_INSTR_PT(547) OR ROM32_INSTR_PT(550) + OR ROM32_INSTR_PT(551) OR ROM32_INSTR_PT(552) + OR ROM32_INSTR_PT(554) OR ROM32_INSTR_PT(556) + OR ROM32_INSTR_PT(558) OR ROM32_INSTR_PT(565) + OR ROM32_INSTR_PT(568) OR ROM32_INSTR_PT(570) + OR ROM32_INSTR_PT(574) OR ROM32_INSTR_PT(575) + OR ROM32_INSTR_PT(578) OR ROM32_INSTR_PT(582) + OR ROM32_INSTR_PT(585) OR ROM32_INSTR_PT(588) + OR ROM32_INSTR_PT(590) OR ROM32_INSTR_PT(595) + OR ROM32_INSTR_PT(602) OR ROM32_INSTR_PT(603) + OR ROM32_INSTR_PT(606) OR ROM32_INSTR_PT(607) + OR ROM32_INSTR_PT(611) OR ROM32_INSTR_PT(612) + OR ROM32_INSTR_PT(617) OR ROM32_INSTR_PT(621) + OR ROM32_INSTR_PT(625) OR ROM32_INSTR_PT(630) + OR ROM32_INSTR_PT(633) OR ROM32_INSTR_PT(635) + OR ROM32_INSTR_PT(639) OR ROM32_INSTR_PT(642) + OR ROM32_INSTR_PT(644) OR ROM32_INSTR_PT(647) + OR ROM32_INSTR_PT(666) OR ROM32_INSTR_PT(677) + OR ROM32_INSTR_PT(680) OR ROM32_INSTR_PT(689) + OR ROM32_INSTR_PT(690) OR ROM32_INSTR_PT(698) + OR ROM32_INSTR_PT(718) OR ROM32_INSTR_PT(731) + OR ROM32_INSTR_PT(736) OR ROM32_INSTR_PT(745) + OR ROM32_INSTR_PT(755) OR ROM32_INSTR_PT(762) + OR ROM32_INSTR_PT(770) OR ROM32_INSTR_PT(818) + OR ROM32_INSTR_PT(855) OR ROM32_INSTR_PT(862) + OR ROM32_INSTR_PT(870)); +MQQ1870:TEMPLATE(15) <= + (ROM32_INSTR_PT(8) OR ROM32_INSTR_PT(14) + OR ROM32_INSTR_PT(17) OR ROM32_INSTR_PT(26) + OR ROM32_INSTR_PT(34) OR ROM32_INSTR_PT(53) + OR ROM32_INSTR_PT(57) OR ROM32_INSTR_PT(74) + OR ROM32_INSTR_PT(79) OR ROM32_INSTR_PT(84) + OR ROM32_INSTR_PT(92) OR ROM32_INSTR_PT(102) + OR ROM32_INSTR_PT(111) OR ROM32_INSTR_PT(115) + OR ROM32_INSTR_PT(117) OR ROM32_INSTR_PT(122) + OR ROM32_INSTR_PT(123) OR ROM32_INSTR_PT(134) + OR ROM32_INSTR_PT(141) OR ROM32_INSTR_PT(148) + OR ROM32_INSTR_PT(159) OR ROM32_INSTR_PT(163) + OR ROM32_INSTR_PT(170) OR ROM32_INSTR_PT(173) + OR ROM32_INSTR_PT(174) OR ROM32_INSTR_PT(203) + OR ROM32_INSTR_PT(212) OR ROM32_INSTR_PT(214) + OR ROM32_INSTR_PT(215) OR ROM32_INSTR_PT(220) + OR ROM32_INSTR_PT(223) OR ROM32_INSTR_PT(235) + OR ROM32_INSTR_PT(240) OR ROM32_INSTR_PT(259) + OR ROM32_INSTR_PT(264) OR ROM32_INSTR_PT(271) + OR ROM32_INSTR_PT(276) OR ROM32_INSTR_PT(289) + OR ROM32_INSTR_PT(290) OR ROM32_INSTR_PT(294) + OR ROM32_INSTR_PT(297) OR ROM32_INSTR_PT(301) + OR ROM32_INSTR_PT(309) OR ROM32_INSTR_PT(346) + OR ROM32_INSTR_PT(350) OR ROM32_INSTR_PT(356) + OR ROM32_INSTR_PT(360) OR ROM32_INSTR_PT(368) + OR ROM32_INSTR_PT(376) OR ROM32_INSTR_PT(382) + OR ROM32_INSTR_PT(386) OR ROM32_INSTR_PT(392) + OR ROM32_INSTR_PT(395) OR ROM32_INSTR_PT(404) + OR ROM32_INSTR_PT(413) OR ROM32_INSTR_PT(422) + OR ROM32_INSTR_PT(430) OR ROM32_INSTR_PT(431) + OR ROM32_INSTR_PT(436) OR ROM32_INSTR_PT(438) + OR ROM32_INSTR_PT(439) OR ROM32_INSTR_PT(442) + OR ROM32_INSTR_PT(454) OR ROM32_INSTR_PT(459) + OR ROM32_INSTR_PT(471) OR ROM32_INSTR_PT(474) + OR ROM32_INSTR_PT(476) OR ROM32_INSTR_PT(477) + OR ROM32_INSTR_PT(503) OR ROM32_INSTR_PT(505) + OR ROM32_INSTR_PT(506) OR ROM32_INSTR_PT(517) + OR ROM32_INSTR_PT(522) OR ROM32_INSTR_PT(532) + OR ROM32_INSTR_PT(536) OR ROM32_INSTR_PT(538) + OR ROM32_INSTR_PT(554) OR ROM32_INSTR_PT(563) + OR ROM32_INSTR_PT(580) OR ROM32_INSTR_PT(581) + OR ROM32_INSTR_PT(593) OR ROM32_INSTR_PT(598) + OR ROM32_INSTR_PT(599) OR ROM32_INSTR_PT(607) + OR ROM32_INSTR_PT(608) OR ROM32_INSTR_PT(620) + OR ROM32_INSTR_PT(659) OR ROM32_INSTR_PT(664) + OR ROM32_INSTR_PT(689) OR ROM32_INSTR_PT(692) + OR ROM32_INSTR_PT(711) OR ROM32_INSTR_PT(726) + OR ROM32_INSTR_PT(829) OR ROM32_INSTR_PT(831) + OR ROM32_INSTR_PT(845) OR ROM32_INSTR_PT(853) + ); +MQQ1871:TEMPLATE(16) <= + (ROM32_INSTR_PT(4) OR ROM32_INSTR_PT(9) + OR ROM32_INSTR_PT(16) OR ROM32_INSTR_PT(18) + OR ROM32_INSTR_PT(20) OR ROM32_INSTR_PT(26) + OR ROM32_INSTR_PT(32) OR ROM32_INSTR_PT(34) + OR ROM32_INSTR_PT(38) OR ROM32_INSTR_PT(49) + OR ROM32_INSTR_PT(55) OR ROM32_INSTR_PT(67) + OR ROM32_INSTR_PT(77) OR ROM32_INSTR_PT(79) + OR ROM32_INSTR_PT(84) OR ROM32_INSTR_PT(95) + OR ROM32_INSTR_PT(99) OR ROM32_INSTR_PT(105) + OR ROM32_INSTR_PT(111) OR ROM32_INSTR_PT(114) + OR ROM32_INSTR_PT(115) OR ROM32_INSTR_PT(118) + OR ROM32_INSTR_PT(119) OR ROM32_INSTR_PT(122) + OR ROM32_INSTR_PT(127) OR ROM32_INSTR_PT(171) + OR ROM32_INSTR_PT(186) OR ROM32_INSTR_PT(189) + OR ROM32_INSTR_PT(200) OR ROM32_INSTR_PT(209) + OR ROM32_INSTR_PT(215) OR ROM32_INSTR_PT(219) + OR ROM32_INSTR_PT(220) OR ROM32_INSTR_PT(224) + OR ROM32_INSTR_PT(227) OR ROM32_INSTR_PT(250) + OR ROM32_INSTR_PT(251) OR ROM32_INSTR_PT(259) + OR ROM32_INSTR_PT(261) OR ROM32_INSTR_PT(262) + OR ROM32_INSTR_PT(264) OR ROM32_INSTR_PT(267) + OR ROM32_INSTR_PT(272) OR ROM32_INSTR_PT(273) + OR ROM32_INSTR_PT(278) OR ROM32_INSTR_PT(281) + OR ROM32_INSTR_PT(283) OR ROM32_INSTR_PT(301) + OR ROM32_INSTR_PT(313) OR ROM32_INSTR_PT(321) + OR ROM32_INSTR_PT(328) OR ROM32_INSTR_PT(345) + OR ROM32_INSTR_PT(360) OR ROM32_INSTR_PT(366) + OR ROM32_INSTR_PT(368) OR ROM32_INSTR_PT(371) + OR ROM32_INSTR_PT(390) OR ROM32_INSTR_PT(392) + OR ROM32_INSTR_PT(396) OR ROM32_INSTR_PT(398) + OR ROM32_INSTR_PT(401) OR ROM32_INSTR_PT(412) + OR ROM32_INSTR_PT(424) OR ROM32_INSTR_PT(433) + OR ROM32_INSTR_PT(446) OR ROM32_INSTR_PT(468) + OR ROM32_INSTR_PT(476) OR ROM32_INSTR_PT(478) + OR ROM32_INSTR_PT(502) OR ROM32_INSTR_PT(519) + OR ROM32_INSTR_PT(521) OR ROM32_INSTR_PT(522) + OR ROM32_INSTR_PT(524) OR ROM32_INSTR_PT(537) + OR ROM32_INSTR_PT(539) OR ROM32_INSTR_PT(554) + OR ROM32_INSTR_PT(556) OR ROM32_INSTR_PT(562) + OR ROM32_INSTR_PT(568) OR ROM32_INSTR_PT(581) + OR ROM32_INSTR_PT(583) OR ROM32_INSTR_PT(590) + OR ROM32_INSTR_PT(591) OR ROM32_INSTR_PT(595) + OR ROM32_INSTR_PT(602) OR ROM32_INSTR_PT(607) + OR ROM32_INSTR_PT(612) OR ROM32_INSTR_PT(614) + OR ROM32_INSTR_PT(626) OR ROM32_INSTR_PT(642) + OR ROM32_INSTR_PT(644) OR ROM32_INSTR_PT(736) + OR ROM32_INSTR_PT(762) OR ROM32_INSTR_PT(770) + OR ROM32_INSTR_PT(870)); +MQQ1872:TEMPLATE(17) <= + (ROM32_INSTR_PT(4) OR ROM32_INSTR_PT(16) + OR ROM32_INSTR_PT(18) OR ROM32_INSTR_PT(20) + OR ROM32_INSTR_PT(26) OR ROM32_INSTR_PT(32) + OR ROM32_INSTR_PT(34) OR ROM32_INSTR_PT(37) + OR ROM32_INSTR_PT(38) OR ROM32_INSTR_PT(43) + OR ROM32_INSTR_PT(49) OR ROM32_INSTR_PT(55) + OR ROM32_INSTR_PT(63) OR ROM32_INSTR_PT(73) + OR ROM32_INSTR_PT(79) OR ROM32_INSTR_PT(80) + OR ROM32_INSTR_PT(87) OR ROM32_INSTR_PT(90) + OR ROM32_INSTR_PT(95) OR ROM32_INSTR_PT(99) + OR ROM32_INSTR_PT(103) OR ROM32_INSTR_PT(105) + OR ROM32_INSTR_PT(112) OR ROM32_INSTR_PT(119) + OR ROM32_INSTR_PT(122) OR ROM32_INSTR_PT(127) + OR ROM32_INSTR_PT(173) OR ROM32_INSTR_PT(184) + OR ROM32_INSTR_PT(186) OR ROM32_INSTR_PT(187) + OR ROM32_INSTR_PT(189) OR ROM32_INSTR_PT(200) + OR ROM32_INSTR_PT(209) OR ROM32_INSTR_PT(216) + OR ROM32_INSTR_PT(224) OR ROM32_INSTR_PT(227) + OR ROM32_INSTR_PT(232) OR ROM32_INSTR_PT(235) + OR ROM32_INSTR_PT(238) OR ROM32_INSTR_PT(250) + OR ROM32_INSTR_PT(251) OR ROM32_INSTR_PT(259) + OR ROM32_INSTR_PT(262) OR ROM32_INSTR_PT(264) + OR ROM32_INSTR_PT(269) OR ROM32_INSTR_PT(270) + OR ROM32_INSTR_PT(272) OR ROM32_INSTR_PT(275) + OR ROM32_INSTR_PT(278) OR ROM32_INSTR_PT(280) + OR ROM32_INSTR_PT(281) OR ROM32_INSTR_PT(283) + OR ROM32_INSTR_PT(284) OR ROM32_INSTR_PT(288) + OR ROM32_INSTR_PT(299) OR ROM32_INSTR_PT(301) + OR ROM32_INSTR_PT(303) OR ROM32_INSTR_PT(321) + OR ROM32_INSTR_PT(326) OR ROM32_INSTR_PT(328) + OR ROM32_INSTR_PT(340) OR ROM32_INSTR_PT(345) + OR ROM32_INSTR_PT(348) OR ROM32_INSTR_PT(361) + OR ROM32_INSTR_PT(366) OR ROM32_INSTR_PT(378) + OR ROM32_INSTR_PT(379) OR ROM32_INSTR_PT(383) + OR ROM32_INSTR_PT(392) OR ROM32_INSTR_PT(396) + OR ROM32_INSTR_PT(398) OR ROM32_INSTR_PT(404) + OR ROM32_INSTR_PT(406) OR ROM32_INSTR_PT(416) + OR ROM32_INSTR_PT(418) OR ROM32_INSTR_PT(419) + OR ROM32_INSTR_PT(421) OR ROM32_INSTR_PT(424) + OR ROM32_INSTR_PT(446) OR ROM32_INSTR_PT(468) + OR ROM32_INSTR_PT(475) OR ROM32_INSTR_PT(476) + OR ROM32_INSTR_PT(477) OR ROM32_INSTR_PT(478) + OR ROM32_INSTR_PT(479) OR ROM32_INSTR_PT(480) + OR ROM32_INSTR_PT(481) OR ROM32_INSTR_PT(482) + OR ROM32_INSTR_PT(490) OR ROM32_INSTR_PT(494) + OR ROM32_INSTR_PT(497) OR ROM32_INSTR_PT(505) + OR ROM32_INSTR_PT(508) OR ROM32_INSTR_PT(520) + OR ROM32_INSTR_PT(521) OR ROM32_INSTR_PT(522) + OR ROM32_INSTR_PT(534) OR ROM32_INSTR_PT(535) + OR ROM32_INSTR_PT(537) OR ROM32_INSTR_PT(538) + OR ROM32_INSTR_PT(546) OR ROM32_INSTR_PT(547) + OR ROM32_INSTR_PT(550) OR ROM32_INSTR_PT(552) + OR ROM32_INSTR_PT(554) OR ROM32_INSTR_PT(562) + OR ROM32_INSTR_PT(574) OR ROM32_INSTR_PT(578) + OR ROM32_INSTR_PT(582) OR ROM32_INSTR_PT(583) + OR ROM32_INSTR_PT(585) OR ROM32_INSTR_PT(591) + OR ROM32_INSTR_PT(593) OR ROM32_INSTR_PT(598) + OR ROM32_INSTR_PT(602) OR ROM32_INSTR_PT(606) + OR ROM32_INSTR_PT(607) OR ROM32_INSTR_PT(608) + OR ROM32_INSTR_PT(630) OR ROM32_INSTR_PT(635) + OR ROM32_INSTR_PT(639) OR ROM32_INSTR_PT(642) + OR ROM32_INSTR_PT(644) OR ROM32_INSTR_PT(647) + OR ROM32_INSTR_PT(666) OR ROM32_INSTR_PT(677) + OR ROM32_INSTR_PT(680) OR ROM32_INSTR_PT(698) + OR ROM32_INSTR_PT(870)); +MQQ1873:TEMPLATE(18) <= + (ROM32_INSTR_PT(4) OR ROM32_INSTR_PT(18) + OR ROM32_INSTR_PT(20) OR ROM32_INSTR_PT(26) + OR ROM32_INSTR_PT(34) OR ROM32_INSTR_PT(38) + OR ROM32_INSTR_PT(49) OR ROM32_INSTR_PT(79) + OR ROM32_INSTR_PT(95) OR ROM32_INSTR_PT(97) + OR ROM32_INSTR_PT(111) OR ROM32_INSTR_PT(119) + OR ROM32_INSTR_PT(172) OR ROM32_INSTR_PT(224) + OR ROM32_INSTR_PT(251) OR ROM32_INSTR_PT(259) + OR ROM32_INSTR_PT(264) OR ROM32_INSTR_PT(278) + OR ROM32_INSTR_PT(281) OR ROM32_INSTR_PT(289) + OR ROM32_INSTR_PT(396) OR ROM32_INSTR_PT(398) + OR ROM32_INSTR_PT(424) OR ROM32_INSTR_PT(468) + OR ROM32_INSTR_PT(476) OR ROM32_INSTR_PT(521) + OR ROM32_INSTR_PT(522) OR ROM32_INSTR_PT(537) + OR ROM32_INSTR_PT(543) OR ROM32_INSTR_PT(554) + OR ROM32_INSTR_PT(562) OR ROM32_INSTR_PT(583) + OR ROM32_INSTR_PT(591) OR ROM32_INSTR_PT(642) + OR ROM32_INSTR_PT(720) OR ROM32_INSTR_PT(807) + OR ROM32_INSTR_PT(823)); +MQQ1874:TEMPLATE(19) <= + (ROM32_INSTR_PT(4) OR ROM32_INSTR_PT(14) + OR ROM32_INSTR_PT(18) OR ROM32_INSTR_PT(20) + OR ROM32_INSTR_PT(23) OR ROM32_INSTR_PT(26) + OR ROM32_INSTR_PT(34) OR ROM32_INSTR_PT(38) + OR ROM32_INSTR_PT(39) OR ROM32_INSTR_PT(42) + OR ROM32_INSTR_PT(45) OR ROM32_INSTR_PT(49) + OR ROM32_INSTR_PT(53) OR ROM32_INSTR_PT(57) + OR ROM32_INSTR_PT(79) OR ROM32_INSTR_PT(85) + OR ROM32_INSTR_PT(95) OR ROM32_INSTR_PT(97) + OR ROM32_INSTR_PT(101) OR ROM32_INSTR_PT(102) + OR ROM32_INSTR_PT(110) OR ROM32_INSTR_PT(119) + OR ROM32_INSTR_PT(141) OR ROM32_INSTR_PT(143) + OR ROM32_INSTR_PT(144) OR ROM32_INSTR_PT(158) + OR ROM32_INSTR_PT(178) OR ROM32_INSTR_PT(187) + OR ROM32_INSTR_PT(203) OR ROM32_INSTR_PT(205) + OR ROM32_INSTR_PT(206) OR ROM32_INSTR_PT(207) + OR ROM32_INSTR_PT(220) OR ROM32_INSTR_PT(224) + OR ROM32_INSTR_PT(232) OR ROM32_INSTR_PT(235) + OR ROM32_INSTR_PT(243) OR ROM32_INSTR_PT(251) + OR ROM32_INSTR_PT(252) OR ROM32_INSTR_PT(258) + OR ROM32_INSTR_PT(268) OR ROM32_INSTR_PT(271) + OR ROM32_INSTR_PT(278) OR ROM32_INSTR_PT(281) + OR ROM32_INSTR_PT(289) OR ROM32_INSTR_PT(294) + OR ROM32_INSTR_PT(306) OR ROM32_INSTR_PT(323) + OR ROM32_INSTR_PT(344) OR ROM32_INSTR_PT(376) + OR ROM32_INSTR_PT(378) OR ROM32_INSTR_PT(382) + OR ROM32_INSTR_PT(385) OR ROM32_INSTR_PT(386) + OR ROM32_INSTR_PT(387) OR ROM32_INSTR_PT(396) + OR ROM32_INSTR_PT(398) OR ROM32_INSTR_PT(405) + OR ROM32_INSTR_PT(416) OR ROM32_INSTR_PT(417) + OR ROM32_INSTR_PT(419) OR ROM32_INSTR_PT(422) + OR ROM32_INSTR_PT(424) OR ROM32_INSTR_PT(426) + OR ROM32_INSTR_PT(435) OR ROM32_INSTR_PT(436) + OR ROM32_INSTR_PT(452) OR ROM32_INSTR_PT(458) + OR ROM32_INSTR_PT(468) OR ROM32_INSTR_PT(476) + OR ROM32_INSTR_PT(486) OR ROM32_INSTR_PT(503) + OR ROM32_INSTR_PT(507) OR ROM32_INSTR_PT(517) + OR ROM32_INSTR_PT(521) OR ROM32_INSTR_PT(522) + OR ROM32_INSTR_PT(530) OR ROM32_INSTR_PT(532) + OR ROM32_INSTR_PT(537) OR ROM32_INSTR_PT(541) + OR ROM32_INSTR_PT(551) OR ROM32_INSTR_PT(554) + OR ROM32_INSTR_PT(569) OR ROM32_INSTR_PT(579) + OR ROM32_INSTR_PT(581) OR ROM32_INSTR_PT(583) + OR ROM32_INSTR_PT(591) OR ROM32_INSTR_PT(605) + OR ROM32_INSTR_PT(610) OR ROM32_INSTR_PT(615) + OR ROM32_INSTR_PT(616) OR ROM32_INSTR_PT(642) + OR ROM32_INSTR_PT(643) OR ROM32_INSTR_PT(674) + OR ROM32_INSTR_PT(684) OR ROM32_INSTR_PT(720) + OR ROM32_INSTR_PT(729) OR ROM32_INSTR_PT(763) + OR ROM32_INSTR_PT(807) OR ROM32_INSTR_PT(812) + OR ROM32_INSTR_PT(818) OR ROM32_INSTR_PT(819) + OR ROM32_INSTR_PT(823) OR ROM32_INSTR_PT(878) + ); +MQQ1875:TEMPLATE(20) <= + (ROM32_INSTR_PT(4) OR ROM32_INSTR_PT(12) + OR ROM32_INSTR_PT(20) OR ROM32_INSTR_PT(33) + OR ROM32_INSTR_PT(35) OR ROM32_INSTR_PT(38) + OR ROM32_INSTR_PT(42) OR ROM32_INSTR_PT(45) + OR ROM32_INSTR_PT(49) OR ROM32_INSTR_PT(56) + OR ROM32_INSTR_PT(95) OR ROM32_INSTR_PT(102) + OR ROM32_INSTR_PT(119) OR ROM32_INSTR_PT(141) + OR ROM32_INSTR_PT(155) OR ROM32_INSTR_PT(163) + OR ROM32_INSTR_PT(196) OR ROM32_INSTR_PT(205) + OR ROM32_INSTR_PT(218) OR ROM32_INSTR_PT(224) + OR ROM32_INSTR_PT(251) OR ROM32_INSTR_PT(257) + OR ROM32_INSTR_PT(258) OR ROM32_INSTR_PT(278) + OR ROM32_INSTR_PT(281) OR ROM32_INSTR_PT(289) + OR ROM32_INSTR_PT(294) OR ROM32_INSTR_PT(306) + OR ROM32_INSTR_PT(323) OR ROM32_INSTR_PT(350) + OR ROM32_INSTR_PT(362) OR ROM32_INSTR_PT(367) + OR ROM32_INSTR_PT(382) OR ROM32_INSTR_PT(386) + OR ROM32_INSTR_PT(387) OR ROM32_INSTR_PT(394) + OR ROM32_INSTR_PT(396) OR ROM32_INSTR_PT(398) + OR ROM32_INSTR_PT(402) OR ROM32_INSTR_PT(422) + OR ROM32_INSTR_PT(423) OR ROM32_INSTR_PT(424) + OR ROM32_INSTR_PT(431) OR ROM32_INSTR_PT(435) + OR ROM32_INSTR_PT(452) OR ROM32_INSTR_PT(454) + OR ROM32_INSTR_PT(456) OR ROM32_INSTR_PT(464) + OR ROM32_INSTR_PT(469) OR ROM32_INSTR_PT(472) + OR ROM32_INSTR_PT(476) OR ROM32_INSTR_PT(484) + OR ROM32_INSTR_PT(504) OR ROM32_INSTR_PT(514) + OR ROM32_INSTR_PT(516) OR ROM32_INSTR_PT(521) + OR ROM32_INSTR_PT(522) OR ROM32_INSTR_PT(537) + OR ROM32_INSTR_PT(541) OR ROM32_INSTR_PT(543) + OR ROM32_INSTR_PT(554) OR ROM32_INSTR_PT(563) + OR ROM32_INSTR_PT(577) OR ROM32_INSTR_PT(583) + OR ROM32_INSTR_PT(584) OR ROM32_INSTR_PT(591) + OR ROM32_INSTR_PT(611) OR ROM32_INSTR_PT(615) + OR ROM32_INSTR_PT(625) OR ROM32_INSTR_PT(634) + OR ROM32_INSTR_PT(638) OR ROM32_INSTR_PT(642) + OR ROM32_INSTR_PT(684) OR ROM32_INSTR_PT(690) + OR ROM32_INSTR_PT(718) OR ROM32_INSTR_PT(728) + OR ROM32_INSTR_PT(751) OR ROM32_INSTR_PT(753) + OR ROM32_INSTR_PT(763) OR ROM32_INSTR_PT(805) + OR ROM32_INSTR_PT(818)); +MQQ1876:TEMPLATE(21) <= + (ROM32_INSTR_PT(4) OR ROM32_INSTR_PT(5) + OR ROM32_INSTR_PT(8) OR ROM32_INSTR_PT(9) + OR ROM32_INSTR_PT(10) OR ROM32_INSTR_PT(17) + OR ROM32_INSTR_PT(20) OR ROM32_INSTR_PT(23) + OR ROM32_INSTR_PT(35) OR ROM32_INSTR_PT(38) + OR ROM32_INSTR_PT(43) OR ROM32_INSTR_PT(60) + OR ROM32_INSTR_PT(73) OR ROM32_INSTR_PT(74) + OR ROM32_INSTR_PT(78) OR ROM32_INSTR_PT(80) + OR ROM32_INSTR_PT(84) OR ROM32_INSTR_PT(87) + OR ROM32_INSTR_PT(93) OR ROM32_INSTR_PT(95) + OR ROM32_INSTR_PT(97) OR ROM32_INSTR_PT(115) + OR ROM32_INSTR_PT(118) OR ROM32_INSTR_PT(119) + OR ROM32_INSTR_PT(134) OR ROM32_INSTR_PT(148) + OR ROM32_INSTR_PT(154) OR ROM32_INSTR_PT(172) + OR ROM32_INSTR_PT(178) OR ROM32_INSTR_PT(179) + OR ROM32_INSTR_PT(186) OR ROM32_INSTR_PT(187) + OR ROM32_INSTR_PT(194) OR ROM32_INSTR_PT(202) + OR ROM32_INSTR_PT(206) OR ROM32_INSTR_PT(215) + OR ROM32_INSTR_PT(218) OR ROM32_INSTR_PT(223) + OR ROM32_INSTR_PT(224) OR ROM32_INSTR_PT(229) + OR ROM32_INSTR_PT(232) OR ROM32_INSTR_PT(235) + OR ROM32_INSTR_PT(244) OR ROM32_INSTR_PT(251) + OR ROM32_INSTR_PT(254) OR ROM32_INSTR_PT(256) + OR ROM32_INSTR_PT(257) OR ROM32_INSTR_PT(261) + OR ROM32_INSTR_PT(262) OR ROM32_INSTR_PT(267) + OR ROM32_INSTR_PT(270) OR ROM32_INSTR_PT(273) + OR ROM32_INSTR_PT(275) OR ROM32_INSTR_PT(278) + OR ROM32_INSTR_PT(281) OR ROM32_INSTR_PT(289) + OR ROM32_INSTR_PT(295) OR ROM32_INSTR_PT(297) + OR ROM32_INSTR_PT(310) OR ROM32_INSTR_PT(313) + OR ROM32_INSTR_PT(344) OR ROM32_INSTR_PT(360) + OR ROM32_INSTR_PT(362) OR ROM32_INSTR_PT(368) + OR ROM32_INSTR_PT(371) OR ROM32_INSTR_PT(378) + OR ROM32_INSTR_PT(385) OR ROM32_INSTR_PT(387) + OR ROM32_INSTR_PT(390) OR ROM32_INSTR_PT(396) + OR ROM32_INSTR_PT(398) OR ROM32_INSTR_PT(401) + OR ROM32_INSTR_PT(411) OR ROM32_INSTR_PT(412) + OR ROM32_INSTR_PT(416) OR ROM32_INSTR_PT(419) + OR ROM32_INSTR_PT(421) OR ROM32_INSTR_PT(424) + OR ROM32_INSTR_PT(426) OR ROM32_INSTR_PT(433) + OR ROM32_INSTR_PT(434) OR ROM32_INSTR_PT(453) + OR ROM32_INSTR_PT(454) OR ROM32_INSTR_PT(461) + OR ROM32_INSTR_PT(496) OR ROM32_INSTR_PT(502) + OR ROM32_INSTR_PT(506) OR ROM32_INSTR_PT(507) + OR ROM32_INSTR_PT(508) OR ROM32_INSTR_PT(516) + OR ROM32_INSTR_PT(519) OR ROM32_INSTR_PT(521) + OR ROM32_INSTR_PT(524) OR ROM32_INSTR_PT(530) + OR ROM32_INSTR_PT(531) OR ROM32_INSTR_PT(535) + OR ROM32_INSTR_PT(537) OR ROM32_INSTR_PT(539) + OR ROM32_INSTR_PT(543) OR ROM32_INSTR_PT(547) + OR ROM32_INSTR_PT(556) OR ROM32_INSTR_PT(558) + OR ROM32_INSTR_PT(568) OR ROM32_INSTR_PT(569) + OR ROM32_INSTR_PT(574) OR ROM32_INSTR_PT(575) + OR ROM32_INSTR_PT(578) OR ROM32_INSTR_PT(579) + OR ROM32_INSTR_PT(583) OR ROM32_INSTR_PT(585) + OR ROM32_INSTR_PT(588) OR ROM32_INSTR_PT(590) + OR ROM32_INSTR_PT(591) OR ROM32_INSTR_PT(611) + OR ROM32_INSTR_PT(612) OR ROM32_INSTR_PT(614) + OR ROM32_INSTR_PT(621) OR ROM32_INSTR_PT(625) + OR ROM32_INSTR_PT(626) OR ROM32_INSTR_PT(663) + OR ROM32_INSTR_PT(728) OR ROM32_INSTR_PT(751) + OR ROM32_INSTR_PT(753) OR ROM32_INSTR_PT(817) + ); +MQQ1877:TEMPLATE(22) <= + (ROM32_INSTR_PT(4) OR ROM32_INSTR_PT(7) + OR ROM32_INSTR_PT(8) OR ROM32_INSTR_PT(10) + OR ROM32_INSTR_PT(12) OR ROM32_INSTR_PT(14) + OR ROM32_INSTR_PT(17) OR ROM32_INSTR_PT(20) + OR ROM32_INSTR_PT(23) OR ROM32_INSTR_PT(29) + OR ROM32_INSTR_PT(35) OR ROM32_INSTR_PT(38) + OR ROM32_INSTR_PT(43) OR ROM32_INSTR_PT(53) + OR ROM32_INSTR_PT(56) OR ROM32_INSTR_PT(57) + OR ROM32_INSTR_PT(74) OR ROM32_INSTR_PT(78) + OR ROM32_INSTR_PT(80) OR ROM32_INSTR_PT(93) + OR ROM32_INSTR_PT(95) OR ROM32_INSTR_PT(97) + OR ROM32_INSTR_PT(101) OR ROM32_INSTR_PT(114) + OR ROM32_INSTR_PT(119) OR ROM32_INSTR_PT(122) + OR ROM32_INSTR_PT(131) OR ROM32_INSTR_PT(134) + OR ROM32_INSTR_PT(143) OR ROM32_INSTR_PT(148) + OR ROM32_INSTR_PT(155) OR ROM32_INSTR_PT(158) + OR ROM32_INSTR_PT(163) OR ROM32_INSTR_PT(164) + OR ROM32_INSTR_PT(171) OR ROM32_INSTR_PT(172) + OR ROM32_INSTR_PT(179) OR ROM32_INSTR_PT(186) + OR ROM32_INSTR_PT(196) OR ROM32_INSTR_PT(202) + OR ROM32_INSTR_PT(203) OR ROM32_INSTR_PT(205) + OR ROM32_INSTR_PT(207) OR ROM32_INSTR_PT(212) + OR ROM32_INSTR_PT(218) OR ROM32_INSTR_PT(220) + OR ROM32_INSTR_PT(223) OR ROM32_INSTR_PT(224) + OR ROM32_INSTR_PT(229) OR ROM32_INSTR_PT(243) + OR ROM32_INSTR_PT(244) OR ROM32_INSTR_PT(251) + OR ROM32_INSTR_PT(257) OR ROM32_INSTR_PT(262) + OR ROM32_INSTR_PT(271) OR ROM32_INSTR_PT(278) + OR ROM32_INSTR_PT(281) OR ROM32_INSTR_PT(289) + OR ROM32_INSTR_PT(295) OR ROM32_INSTR_PT(297) + OR ROM32_INSTR_PT(301) OR ROM32_INSTR_PT(310) + OR ROM32_INSTR_PT(323) OR ROM32_INSTR_PT(350) + OR ROM32_INSTR_PT(362) OR ROM32_INSTR_PT(367) + OR ROM32_INSTR_PT(376) OR ROM32_INSTR_PT(387) + OR ROM32_INSTR_PT(392) OR ROM32_INSTR_PT(394) + OR ROM32_INSTR_PT(396) OR ROM32_INSTR_PT(398) + OR ROM32_INSTR_PT(402) OR ROM32_INSTR_PT(411) + OR ROM32_INSTR_PT(423) OR ROM32_INSTR_PT(424) + OR ROM32_INSTR_PT(434) OR ROM32_INSTR_PT(435) + OR ROM32_INSTR_PT(436) OR ROM32_INSTR_PT(438) + OR ROM32_INSTR_PT(452) OR ROM32_INSTR_PT(453) + OR ROM32_INSTR_PT(454) OR ROM32_INSTR_PT(456) + OR ROM32_INSTR_PT(458) OR ROM32_INSTR_PT(461) + OR ROM32_INSTR_PT(464) OR ROM32_INSTR_PT(469) + OR ROM32_INSTR_PT(472) OR ROM32_INSTR_PT(478) + OR ROM32_INSTR_PT(484) OR ROM32_INSTR_PT(486) + OR ROM32_INSTR_PT(496) OR ROM32_INSTR_PT(503) + OR ROM32_INSTR_PT(506) OR ROM32_INSTR_PT(511) + OR ROM32_INSTR_PT(514) OR ROM32_INSTR_PT(516) + OR ROM32_INSTR_PT(517) OR ROM32_INSTR_PT(521) + OR ROM32_INSTR_PT(532) OR ROM32_INSTR_PT(537) + OR ROM32_INSTR_PT(539) OR ROM32_INSTR_PT(543) + OR ROM32_INSTR_PT(551) OR ROM32_INSTR_PT(558) + OR ROM32_INSTR_PT(566) OR ROM32_INSTR_PT(575) + OR ROM32_INSTR_PT(577) OR ROM32_INSTR_PT(580) + OR ROM32_INSTR_PT(581) OR ROM32_INSTR_PT(583) + OR ROM32_INSTR_PT(584) OR ROM32_INSTR_PT(588) + OR ROM32_INSTR_PT(591) OR ROM32_INSTR_PT(599) + OR ROM32_INSTR_PT(601) OR ROM32_INSTR_PT(605) + OR ROM32_INSTR_PT(607) OR ROM32_INSTR_PT(611) + OR ROM32_INSTR_PT(614) OR ROM32_INSTR_PT(622) + OR ROM32_INSTR_PT(625) OR ROM32_INSTR_PT(634) + OR ROM32_INSTR_PT(638) OR ROM32_INSTR_PT(643) + OR ROM32_INSTR_PT(654) OR ROM32_INSTR_PT(663) + OR ROM32_INSTR_PT(684) OR ROM32_INSTR_PT(693) + OR ROM32_INSTR_PT(708) OR ROM32_INSTR_PT(720) + OR ROM32_INSTR_PT(728) OR ROM32_INSTR_PT(751) + OR ROM32_INSTR_PT(753) OR ROM32_INSTR_PT(807) + OR ROM32_INSTR_PT(817) OR ROM32_INSTR_PT(819) + OR ROM32_INSTR_PT(823) OR ROM32_INSTR_PT(845) + OR ROM32_INSTR_PT(853)); +MQQ1878:TEMPLATE(23) <= + (ROM32_INSTR_PT(4) OR ROM32_INSTR_PT(5) + OR ROM32_INSTR_PT(12) OR ROM32_INSTR_PT(23) + OR ROM32_INSTR_PT(35) OR ROM32_INSTR_PT(38) + OR ROM32_INSTR_PT(56) OR ROM32_INSTR_PT(57) + OR ROM32_INSTR_PT(93) OR ROM32_INSTR_PT(95) + OR ROM32_INSTR_PT(100) OR ROM32_INSTR_PT(101) + OR ROM32_INSTR_PT(111) OR ROM32_INSTR_PT(124) + OR ROM32_INSTR_PT(135) OR ROM32_INSTR_PT(143) + OR ROM32_INSTR_PT(155) OR ROM32_INSTR_PT(158) + OR ROM32_INSTR_PT(163) OR ROM32_INSTR_PT(179) + OR ROM32_INSTR_PT(187) OR ROM32_INSTR_PT(194) + OR ROM32_INSTR_PT(202) OR ROM32_INSTR_PT(203) + OR ROM32_INSTR_PT(207) OR ROM32_INSTR_PT(218) + OR ROM32_INSTR_PT(220) OR ROM32_INSTR_PT(229) + OR ROM32_INSTR_PT(232) OR ROM32_INSTR_PT(235) + OR ROM32_INSTR_PT(243) OR ROM32_INSTR_PT(244) + OR ROM32_INSTR_PT(251) OR ROM32_INSTR_PT(254) + OR ROM32_INSTR_PT(256) OR ROM32_INSTR_PT(257) + OR ROM32_INSTR_PT(259) OR ROM32_INSTR_PT(260) + OR ROM32_INSTR_PT(264) OR ROM32_INSTR_PT(275) + OR ROM32_INSTR_PT(281) OR ROM32_INSTR_PT(282) + OR ROM32_INSTR_PT(293) OR ROM32_INSTR_PT(310) + OR ROM32_INSTR_PT(318) OR ROM32_INSTR_PT(350) + OR ROM32_INSTR_PT(362) OR ROM32_INSTR_PT(367) + OR ROM32_INSTR_PT(374) OR ROM32_INSTR_PT(376) + OR ROM32_INSTR_PT(378) OR ROM32_INSTR_PT(387) + OR ROM32_INSTR_PT(394) OR ROM32_INSTR_PT(398) + OR ROM32_INSTR_PT(402) OR ROM32_INSTR_PT(409) + OR ROM32_INSTR_PT(416) OR ROM32_INSTR_PT(419) + OR ROM32_INSTR_PT(423) OR ROM32_INSTR_PT(434) + OR ROM32_INSTR_PT(443) OR ROM32_INSTR_PT(453) + OR ROM32_INSTR_PT(454) OR ROM32_INSTR_PT(456) + OR ROM32_INSTR_PT(458) OR ROM32_INSTR_PT(464) + OR ROM32_INSTR_PT(469) OR ROM32_INSTR_PT(472) + OR ROM32_INSTR_PT(484) OR ROM32_INSTR_PT(486) + OR ROM32_INSTR_PT(501) OR ROM32_INSTR_PT(503) + OR ROM32_INSTR_PT(514) OR ROM32_INSTR_PT(516) + OR ROM32_INSTR_PT(531) OR ROM32_INSTR_PT(535) + OR ROM32_INSTR_PT(537) OR ROM32_INSTR_PT(544) + OR ROM32_INSTR_PT(547) OR ROM32_INSTR_PT(551) + OR ROM32_INSTR_PT(557) OR ROM32_INSTR_PT(558) + OR ROM32_INSTR_PT(562) OR ROM32_INSTR_PT(574) + OR ROM32_INSTR_PT(577) OR ROM32_INSTR_PT(581) + OR ROM32_INSTR_PT(588) OR ROM32_INSTR_PT(591) + OR ROM32_INSTR_PT(600) OR ROM32_INSTR_PT(605) + OR ROM32_INSTR_PT(609) OR ROM32_INSTR_PT(611) + OR ROM32_INSTR_PT(621) OR ROM32_INSTR_PT(625) + OR ROM32_INSTR_PT(643) OR ROM32_INSTR_PT(663) + OR ROM32_INSTR_PT(690) OR ROM32_INSTR_PT(713) + OR ROM32_INSTR_PT(720) OR ROM32_INSTR_PT(728) + OR ROM32_INSTR_PT(751) OR ROM32_INSTR_PT(753) + OR ROM32_INSTR_PT(807) OR ROM32_INSTR_PT(817) + OR ROM32_INSTR_PT(819) OR ROM32_INSTR_PT(823) + OR ROM32_INSTR_PT(845)); +MQQ1879:TEMPLATE(24) <= + (ROM32_INSTR_PT(3) OR ROM32_INSTR_PT(4) + OR ROM32_INSTR_PT(5) OR ROM32_INSTR_PT(10) + OR ROM32_INSTR_PT(13) OR ROM32_INSTR_PT(26) + OR ROM32_INSTR_PT(29) OR ROM32_INSTR_PT(34) + OR ROM32_INSTR_PT(35) OR ROM32_INSTR_PT(41) + OR ROM32_INSTR_PT(45) OR ROM32_INSTR_PT(51) + OR ROM32_INSTR_PT(79) OR ROM32_INSTR_PT(93) + OR ROM32_INSTR_PT(95) OR ROM32_INSTR_PT(100) + OR ROM32_INSTR_PT(106) OR ROM32_INSTR_PT(116) + OR ROM32_INSTR_PT(124) OR ROM32_INSTR_PT(135) + OR ROM32_INSTR_PT(139) OR ROM32_INSTR_PT(142) + OR ROM32_INSTR_PT(153) OR ROM32_INSTR_PT(159) + OR ROM32_INSTR_PT(170) OR ROM32_INSTR_PT(172) + OR ROM32_INSTR_PT(183) OR ROM32_INSTR_PT(194) + OR ROM32_INSTR_PT(204) OR ROM32_INSTR_PT(218) + OR ROM32_INSTR_PT(220) OR ROM32_INSTR_PT(229) + OR ROM32_INSTR_PT(241) OR ROM32_INSTR_PT(251) + OR ROM32_INSTR_PT(254) OR ROM32_INSTR_PT(256) + OR ROM32_INSTR_PT(257) OR ROM32_INSTR_PT(258) + OR ROM32_INSTR_PT(260) OR ROM32_INSTR_PT(275) + OR ROM32_INSTR_PT(276) OR ROM32_INSTR_PT(281) + OR ROM32_INSTR_PT(282) OR ROM32_INSTR_PT(290) + OR ROM32_INSTR_PT(293) OR ROM32_INSTR_PT(306) + OR ROM32_INSTR_PT(309) OR ROM32_INSTR_PT(318) + OR ROM32_INSTR_PT(344) OR ROM32_INSTR_PT(362) + OR ROM32_INSTR_PT(363) OR ROM32_INSTR_PT(374) + OR ROM32_INSTR_PT(385) OR ROM32_INSTR_PT(393) + OR ROM32_INSTR_PT(398) OR ROM32_INSTR_PT(409) + OR ROM32_INSTR_PT(415) OR ROM32_INSTR_PT(425) + OR ROM32_INSTR_PT(426) OR ROM32_INSTR_PT(428) + OR ROM32_INSTR_PT(430) OR ROM32_INSTR_PT(434) + OR ROM32_INSTR_PT(437) OR ROM32_INSTR_PT(443) + OR ROM32_INSTR_PT(451) OR ROM32_INSTR_PT(454) + OR ROM32_INSTR_PT(495) OR ROM32_INSTR_PT(501) + OR ROM32_INSTR_PT(509) OR ROM32_INSTR_PT(516) + OR ROM32_INSTR_PT(530) OR ROM32_INSTR_PT(531) + OR ROM32_INSTR_PT(535) OR ROM32_INSTR_PT(543) + OR ROM32_INSTR_PT(544) OR ROM32_INSTR_PT(547) + OR ROM32_INSTR_PT(555) OR ROM32_INSTR_PT(557) + OR ROM32_INSTR_PT(558) OR ROM32_INSTR_PT(563) + OR ROM32_INSTR_PT(574) OR ROM32_INSTR_PT(575) + OR ROM32_INSTR_PT(579) OR ROM32_INSTR_PT(581) + OR ROM32_INSTR_PT(587) OR ROM32_INSTR_PT(591) + OR ROM32_INSTR_PT(600) OR ROM32_INSTR_PT(609) + OR ROM32_INSTR_PT(611) OR ROM32_INSTR_PT(615) + OR ROM32_INSTR_PT(621) OR ROM32_INSTR_PT(624) + OR ROM32_INSTR_PT(625) OR ROM32_INSTR_PT(646) + OR ROM32_INSTR_PT(663) OR ROM32_INSTR_PT(690) + OR ROM32_INSTR_PT(700) OR ROM32_INSTR_PT(729) + OR ROM32_INSTR_PT(745) OR ROM32_INSTR_PT(763) + OR ROM32_INSTR_PT(817) OR ROM32_INSTR_PT(845) + ); +MQQ1880:TEMPLATE(25) <= + (ROM32_INSTR_PT(4) OR ROM32_INSTR_PT(5) + OR ROM32_INSTR_PT(12) OR ROM32_INSTR_PT(20) + OR ROM32_INSTR_PT(23) OR ROM32_INSTR_PT(35) + OR ROM32_INSTR_PT(42) OR ROM32_INSTR_PT(56) + OR ROM32_INSTR_PT(57) OR ROM32_INSTR_PT(95) + OR ROM32_INSTR_PT(97) OR ROM32_INSTR_PT(101) + OR ROM32_INSTR_PT(119) OR ROM32_INSTR_PT(125) + OR ROM32_INSTR_PT(132) OR ROM32_INSTR_PT(142) + OR ROM32_INSTR_PT(143) OR ROM32_INSTR_PT(155) + OR ROM32_INSTR_PT(158) OR ROM32_INSTR_PT(159) + OR ROM32_INSTR_PT(163) OR ROM32_INSTR_PT(170) + OR ROM32_INSTR_PT(172) OR ROM32_INSTR_PT(178) + OR ROM32_INSTR_PT(179) OR ROM32_INSTR_PT(187) + OR ROM32_INSTR_PT(194) OR ROM32_INSTR_PT(196) + OR ROM32_INSTR_PT(203) OR ROM32_INSTR_PT(207) + OR ROM32_INSTR_PT(218) OR ROM32_INSTR_PT(224) + OR ROM32_INSTR_PT(229) OR ROM32_INSTR_PT(232) + OR ROM32_INSTR_PT(235) OR ROM32_INSTR_PT(243) + OR ROM32_INSTR_PT(251) OR ROM32_INSTR_PT(256) + OR ROM32_INSTR_PT(257) OR ROM32_INSTR_PT(275) + OR ROM32_INSTR_PT(276) OR ROM32_INSTR_PT(278) + OR ROM32_INSTR_PT(281) OR ROM32_INSTR_PT(290) + OR ROM32_INSTR_PT(309) OR ROM32_INSTR_PT(335) + OR ROM32_INSTR_PT(344) OR ROM32_INSTR_PT(350) + OR ROM32_INSTR_PT(362) OR ROM32_INSTR_PT(363) + OR ROM32_INSTR_PT(367) OR ROM32_INSTR_PT(376) + OR ROM32_INSTR_PT(378) OR ROM32_INSTR_PT(385) + OR ROM32_INSTR_PT(394) OR ROM32_INSTR_PT(396) + OR ROM32_INSTR_PT(398) OR ROM32_INSTR_PT(402) + OR ROM32_INSTR_PT(416) OR ROM32_INSTR_PT(419) + OR ROM32_INSTR_PT(423) OR ROM32_INSTR_PT(424) + OR ROM32_INSTR_PT(426) OR ROM32_INSTR_PT(430) + OR ROM32_INSTR_PT(442) OR ROM32_INSTR_PT(454) + OR ROM32_INSTR_PT(456) OR ROM32_INSTR_PT(458) + OR ROM32_INSTR_PT(464) OR ROM32_INSTR_PT(469) + OR ROM32_INSTR_PT(472) OR ROM32_INSTR_PT(474) + OR ROM32_INSTR_PT(476) OR ROM32_INSTR_PT(484) + OR ROM32_INSTR_PT(486) OR ROM32_INSTR_PT(503) + OR ROM32_INSTR_PT(504) OR ROM32_INSTR_PT(514) + OR ROM32_INSTR_PT(521) OR ROM32_INSTR_PT(522) + OR ROM32_INSTR_PT(530) OR ROM32_INSTR_PT(531) + OR ROM32_INSTR_PT(535) OR ROM32_INSTR_PT(541) + OR ROM32_INSTR_PT(547) OR ROM32_INSTR_PT(551) + OR ROM32_INSTR_PT(554) OR ROM32_INSTR_PT(555) + OR ROM32_INSTR_PT(558) OR ROM32_INSTR_PT(574) + OR ROM32_INSTR_PT(575) OR ROM32_INSTR_PT(577) + OR ROM32_INSTR_PT(579) OR ROM32_INSTR_PT(588) + OR ROM32_INSTR_PT(591) OR ROM32_INSTR_PT(605) + OR ROM32_INSTR_PT(611) OR ROM32_INSTR_PT(620) + OR ROM32_INSTR_PT(629) OR ROM32_INSTR_PT(633) + OR ROM32_INSTR_PT(642) OR ROM32_INSTR_PT(643) + OR ROM32_INSTR_PT(654) OR ROM32_INSTR_PT(664) + OR ROM32_INSTR_PT(690) OR ROM32_INSTR_PT(697) + OR ROM32_INSTR_PT(708) OR ROM32_INSTR_PT(729) + OR ROM32_INSTR_PT(731) OR ROM32_INSTR_PT(745) + OR ROM32_INSTR_PT(792) OR ROM32_INSTR_PT(817) + OR ROM32_INSTR_PT(818) OR ROM32_INSTR_PT(819) + OR ROM32_INSTR_PT(829)); +MQQ1881:TEMPLATE(26) <= + (ROM32_INSTR_PT(3) OR ROM32_INSTR_PT(4) + OR ROM32_INSTR_PT(5) OR ROM32_INSTR_PT(6) + OR ROM32_INSTR_PT(8) OR ROM32_INSTR_PT(9) + OR ROM32_INSTR_PT(10) OR ROM32_INSTR_PT(12) + OR ROM32_INSTR_PT(13) OR ROM32_INSTR_PT(17) + OR ROM32_INSTR_PT(20) OR ROM32_INSTR_PT(23) + OR ROM32_INSTR_PT(26) OR ROM32_INSTR_PT(29) + OR ROM32_INSTR_PT(33) OR ROM32_INSTR_PT(35) + OR ROM32_INSTR_PT(37) OR ROM32_INSTR_PT(39) + OR ROM32_INSTR_PT(41) OR ROM32_INSTR_PT(43) + OR ROM32_INSTR_PT(45) OR ROM32_INSTR_PT(49) + OR ROM32_INSTR_PT(50) OR ROM32_INSTR_PT(51) + OR ROM32_INSTR_PT(52) OR ROM32_INSTR_PT(56) + OR ROM32_INSTR_PT(57) OR ROM32_INSTR_PT(59) + OR ROM32_INSTR_PT(60) OR ROM32_INSTR_PT(63) + OR ROM32_INSTR_PT(66) OR ROM32_INSTR_PT(72) + OR ROM32_INSTR_PT(73) OR ROM32_INSTR_PT(74) + OR ROM32_INSTR_PT(78) OR ROM32_INSTR_PT(80) + OR ROM32_INSTR_PT(83) OR ROM32_INSTR_PT(84) + OR ROM32_INSTR_PT(85) OR ROM32_INSTR_PT(87) + OR ROM32_INSTR_PT(90) OR ROM32_INSTR_PT(92) + OR ROM32_INSTR_PT(93) OR ROM32_INSTR_PT(95) + OR ROM32_INSTR_PT(96) OR ROM32_INSTR_PT(97) + OR ROM32_INSTR_PT(100) OR ROM32_INSTR_PT(101) + OR ROM32_INSTR_PT(102) OR ROM32_INSTR_PT(103) + OR ROM32_INSTR_PT(106) OR ROM32_INSTR_PT(109) + OR ROM32_INSTR_PT(110) OR ROM32_INSTR_PT(115) + OR ROM32_INSTR_PT(116) OR ROM32_INSTR_PT(117) + OR ROM32_INSTR_PT(118) OR ROM32_INSTR_PT(119) + OR ROM32_INSTR_PT(124) OR ROM32_INSTR_PT(130) + OR ROM32_INSTR_PT(134) OR ROM32_INSTR_PT(135) + OR ROM32_INSTR_PT(139) OR ROM32_INSTR_PT(141) + OR ROM32_INSTR_PT(142) OR ROM32_INSTR_PT(143) + OR ROM32_INSTR_PT(144) OR ROM32_INSTR_PT(148) + OR ROM32_INSTR_PT(153) OR ROM32_INSTR_PT(154) + OR ROM32_INSTR_PT(155) OR ROM32_INSTR_PT(158) + OR ROM32_INSTR_PT(159) OR ROM32_INSTR_PT(163) + OR ROM32_INSTR_PT(169) OR ROM32_INSTR_PT(172) + OR ROM32_INSTR_PT(174) OR ROM32_INSTR_PT(176) + OR ROM32_INSTR_PT(179) OR ROM32_INSTR_PT(180) + OR ROM32_INSTR_PT(181) OR ROM32_INSTR_PT(183) + OR ROM32_INSTR_PT(184) OR ROM32_INSTR_PT(186) + OR ROM32_INSTR_PT(192) OR ROM32_INSTR_PT(194) + OR ROM32_INSTR_PT(196) OR ROM32_INSTR_PT(199) + OR ROM32_INSTR_PT(202) OR ROM32_INSTR_PT(203) + OR ROM32_INSTR_PT(204) OR ROM32_INSTR_PT(206) + OR ROM32_INSTR_PT(207) OR ROM32_INSTR_PT(216) + OR ROM32_INSTR_PT(218) OR ROM32_INSTR_PT(220) + OR ROM32_INSTR_PT(223) OR ROM32_INSTR_PT(224) + OR ROM32_INSTR_PT(227) OR ROM32_INSTR_PT(233) + OR ROM32_INSTR_PT(238) OR ROM32_INSTR_PT(241) + OR ROM32_INSTR_PT(243) OR ROM32_INSTR_PT(244) + OR ROM32_INSTR_PT(249) OR ROM32_INSTR_PT(251) + OR ROM32_INSTR_PT(252) OR ROM32_INSTR_PT(254) + OR ROM32_INSTR_PT(256) OR ROM32_INSTR_PT(257) + OR ROM32_INSTR_PT(259) OR ROM32_INSTR_PT(260) + OR ROM32_INSTR_PT(261) OR ROM32_INSTR_PT(262) + OR ROM32_INSTR_PT(264) OR ROM32_INSTR_PT(266) + OR ROM32_INSTR_PT(267) OR ROM32_INSTR_PT(268) + OR ROM32_INSTR_PT(269) OR ROM32_INSTR_PT(270) + OR ROM32_INSTR_PT(273) OR ROM32_INSTR_PT(274) + OR ROM32_INSTR_PT(275) OR ROM32_INSTR_PT(278) + OR ROM32_INSTR_PT(280) OR ROM32_INSTR_PT(281) + OR ROM32_INSTR_PT(282) OR ROM32_INSTR_PT(284) + OR ROM32_INSTR_PT(288) OR ROM32_INSTR_PT(289) + OR ROM32_INSTR_PT(290) OR ROM32_INSTR_PT(293) + OR ROM32_INSTR_PT(294) OR ROM32_INSTR_PT(295) + OR ROM32_INSTR_PT(297) OR ROM32_INSTR_PT(299) + OR ROM32_INSTR_PT(301) OR ROM32_INSTR_PT(303) + OR ROM32_INSTR_PT(306) OR ROM32_INSTR_PT(309) + OR ROM32_INSTR_PT(310) OR ROM32_INSTR_PT(313) + OR ROM32_INSTR_PT(318) OR ROM32_INSTR_PT(335) + OR ROM32_INSTR_PT(344) OR ROM32_INSTR_PT(346) + OR ROM32_INSTR_PT(348) OR ROM32_INSTR_PT(350) + OR ROM32_INSTR_PT(353) OR ROM32_INSTR_PT(356) + OR ROM32_INSTR_PT(361) OR ROM32_INSTR_PT(362) + OR ROM32_INSTR_PT(364) OR ROM32_INSTR_PT(367) + OR ROM32_INSTR_PT(371) OR ROM32_INSTR_PT(373) + OR ROM32_INSTR_PT(374) OR ROM32_INSTR_PT(376) + OR ROM32_INSTR_PT(379) OR ROM32_INSTR_PT(381) + OR ROM32_INSTR_PT(382) OR ROM32_INSTR_PT(383) + OR ROM32_INSTR_PT(386) OR ROM32_INSTR_PT(387) + OR ROM32_INSTR_PT(390) OR ROM32_INSTR_PT(392) + OR ROM32_INSTR_PT(394) OR ROM32_INSTR_PT(396) + OR ROM32_INSTR_PT(398) OR ROM32_INSTR_PT(400) + OR ROM32_INSTR_PT(401) OR ROM32_INSTR_PT(402) + OR ROM32_INSTR_PT(405) OR ROM32_INSTR_PT(406) + OR ROM32_INSTR_PT(409) OR ROM32_INSTR_PT(411) + OR ROM32_INSTR_PT(412) OR ROM32_INSTR_PT(415) + OR ROM32_INSTR_PT(417) OR ROM32_INSTR_PT(421) + OR ROM32_INSTR_PT(422) OR ROM32_INSTR_PT(423) + OR ROM32_INSTR_PT(424) OR ROM32_INSTR_PT(425) + OR ROM32_INSTR_PT(426) OR ROM32_INSTR_PT(428) + OR ROM32_INSTR_PT(431) OR ROM32_INSTR_PT(433) + OR ROM32_INSTR_PT(434) OR ROM32_INSTR_PT(437) + OR ROM32_INSTR_PT(441) OR ROM32_INSTR_PT(443) + OR ROM32_INSTR_PT(451) OR ROM32_INSTR_PT(453) + OR ROM32_INSTR_PT(454) OR ROM32_INSTR_PT(458) + OR ROM32_INSTR_PT(459) OR ROM32_INSTR_PT(461) + OR ROM32_INSTR_PT(464) OR ROM32_INSTR_PT(469) + OR ROM32_INSTR_PT(472) OR ROM32_INSTR_PT(475) + OR ROM32_INSTR_PT(478) OR ROM32_INSTR_PT(479) + OR ROM32_INSTR_PT(481) OR ROM32_INSTR_PT(482) + OR ROM32_INSTR_PT(484) OR ROM32_INSTR_PT(486) + OR ROM32_INSTR_PT(490) OR ROM32_INSTR_PT(491) + OR ROM32_INSTR_PT(494) OR ROM32_INSTR_PT(495) + OR ROM32_INSTR_PT(496) OR ROM32_INSTR_PT(501) + OR ROM32_INSTR_PT(502) OR ROM32_INSTR_PT(503) + OR ROM32_INSTR_PT(506) OR ROM32_INSTR_PT(507) + OR ROM32_INSTR_PT(508) OR ROM32_INSTR_PT(509) + OR ROM32_INSTR_PT(514) OR ROM32_INSTR_PT(516) + OR ROM32_INSTR_PT(519) OR ROM32_INSTR_PT(520) + OR ROM32_INSTR_PT(521) OR ROM32_INSTR_PT(522) + OR ROM32_INSTR_PT(524) OR ROM32_INSTR_PT(530) + OR ROM32_INSTR_PT(531) OR ROM32_INSTR_PT(534) + OR ROM32_INSTR_PT(535) OR ROM32_INSTR_PT(539) + OR ROM32_INSTR_PT(543) OR ROM32_INSTR_PT(544) + OR ROM32_INSTR_PT(547) OR ROM32_INSTR_PT(550) + OR ROM32_INSTR_PT(551) OR ROM32_INSTR_PT(552) + OR ROM32_INSTR_PT(554) OR ROM32_INSTR_PT(555) + OR ROM32_INSTR_PT(556) OR ROM32_INSTR_PT(557) + OR ROM32_INSTR_PT(562) OR ROM32_INSTR_PT(563) + OR ROM32_INSTR_PT(568) OR ROM32_INSTR_PT(569) + OR ROM32_INSTR_PT(570) OR ROM32_INSTR_PT(574) + OR ROM32_INSTR_PT(575) OR ROM32_INSTR_PT(578) + OR ROM32_INSTR_PT(579) OR ROM32_INSTR_PT(581) + OR ROM32_INSTR_PT(582) OR ROM32_INSTR_PT(583) + OR ROM32_INSTR_PT(585) OR ROM32_INSTR_PT(588) + OR ROM32_INSTR_PT(590) OR ROM32_INSTR_PT(591) + OR ROM32_INSTR_PT(600) OR ROM32_INSTR_PT(602) + OR ROM32_INSTR_PT(603) OR ROM32_INSTR_PT(605) + OR ROM32_INSTR_PT(609) OR ROM32_INSTR_PT(610) + OR ROM32_INSTR_PT(611) OR ROM32_INSTR_PT(612) + OR ROM32_INSTR_PT(613) OR ROM32_INSTR_PT(614) + OR ROM32_INSTR_PT(615) OR ROM32_INSTR_PT(621) + OR ROM32_INSTR_PT(624) OR ROM32_INSTR_PT(625) + OR ROM32_INSTR_PT(626) OR ROM32_INSTR_PT(629) + OR ROM32_INSTR_PT(630) OR ROM32_INSTR_PT(639) + OR ROM32_INSTR_PT(640) OR ROM32_INSTR_PT(642) + OR ROM32_INSTR_PT(643) OR ROM32_INSTR_PT(654) + OR ROM32_INSTR_PT(660) OR ROM32_INSTR_PT(663) + OR ROM32_INSTR_PT(664) OR ROM32_INSTR_PT(666) + OR ROM32_INSTR_PT(674) OR ROM32_INSTR_PT(677) + OR ROM32_INSTR_PT(692) OR ROM32_INSTR_PT(697) + OR ROM32_INSTR_PT(708) OR ROM32_INSTR_PT(711) + OR ROM32_INSTR_PT(713) OR ROM32_INSTR_PT(718) + OR ROM32_INSTR_PT(719) OR ROM32_INSTR_PT(720) + OR ROM32_INSTR_PT(729) OR ROM32_INSTR_PT(755) + OR ROM32_INSTR_PT(763) OR ROM32_INSTR_PT(792) + OR ROM32_INSTR_PT(805) OR ROM32_INSTR_PT(807) + OR ROM32_INSTR_PT(812) OR ROM32_INSTR_PT(817) + OR ROM32_INSTR_PT(819) OR ROM32_INSTR_PT(823) + OR ROM32_INSTR_PT(829) OR ROM32_INSTR_PT(831) + OR ROM32_INSTR_PT(845) OR ROM32_INSTR_PT(854) + OR ROM32_INSTR_PT(855) OR ROM32_INSTR_PT(857) + OR ROM32_INSTR_PT(862) OR ROM32_INSTR_PT(870) + OR ROM32_INSTR_PT(872) OR ROM32_INSTR_PT(878) + ); +MQQ1882:TEMPLATE(27) <= + (ROM32_INSTR_PT(4) OR ROM32_INSTR_PT(5) + OR ROM32_INSTR_PT(6) OR ROM32_INSTR_PT(7) + OR ROM32_INSTR_PT(8) OR ROM32_INSTR_PT(9) + OR ROM32_INSTR_PT(10) OR ROM32_INSTR_PT(12) + OR ROM32_INSTR_PT(14) OR ROM32_INSTR_PT(17) + OR ROM32_INSTR_PT(20) OR ROM32_INSTR_PT(26) + OR ROM32_INSTR_PT(33) OR ROM32_INSTR_PT(37) + OR ROM32_INSTR_PT(39) OR ROM32_INSTR_PT(42) + OR ROM32_INSTR_PT(45) OR ROM32_INSTR_PT(49) + OR ROM32_INSTR_PT(52) OR ROM32_INSTR_PT(53) + OR ROM32_INSTR_PT(56) OR ROM32_INSTR_PT(57) + OR ROM32_INSTR_PT(59) OR ROM32_INSTR_PT(63) + OR ROM32_INSTR_PT(66) OR ROM32_INSTR_PT(72) + OR ROM32_INSTR_PT(74) OR ROM32_INSTR_PT(83) + OR ROM32_INSTR_PT(84) OR ROM32_INSTR_PT(85) + OR ROM32_INSTR_PT(90) OR ROM32_INSTR_PT(93) + OR ROM32_INSTR_PT(95) OR ROM32_INSTR_PT(96) + OR ROM32_INSTR_PT(101) OR ROM32_INSTR_PT(102) + OR ROM32_INSTR_PT(103) OR ROM32_INSTR_PT(109) + OR ROM32_INSTR_PT(110) OR ROM32_INSTR_PT(114) + OR ROM32_INSTR_PT(115) OR ROM32_INSTR_PT(117) + OR ROM32_INSTR_PT(118) OR ROM32_INSTR_PT(119) + OR ROM32_INSTR_PT(130) OR ROM32_INSTR_PT(131) + OR ROM32_INSTR_PT(134) OR ROM32_INSTR_PT(141) + OR ROM32_INSTR_PT(142) OR ROM32_INSTR_PT(143) + OR ROM32_INSTR_PT(144) OR ROM32_INSTR_PT(148) + OR ROM32_INSTR_PT(155) OR ROM32_INSTR_PT(158) + OR ROM32_INSTR_PT(159) OR ROM32_INSTR_PT(163) + OR ROM32_INSTR_PT(164) OR ROM32_INSTR_PT(169) + OR ROM32_INSTR_PT(170) OR ROM32_INSTR_PT(171) + OR ROM32_INSTR_PT(176) OR ROM32_INSTR_PT(178) + OR ROM32_INSTR_PT(179) OR ROM32_INSTR_PT(180) + OR ROM32_INSTR_PT(181) OR ROM32_INSTR_PT(184) + OR ROM32_INSTR_PT(187) OR ROM32_INSTR_PT(192) + OR ROM32_INSTR_PT(194) OR ROM32_INSTR_PT(196) + OR ROM32_INSTR_PT(199) OR ROM32_INSTR_PT(202) + OR ROM32_INSTR_PT(203) OR ROM32_INSTR_PT(205) + OR ROM32_INSTR_PT(206) OR ROM32_INSTR_PT(207) + OR ROM32_INSTR_PT(212) OR ROM32_INSTR_PT(216) + OR ROM32_INSTR_PT(220) OR ROM32_INSTR_PT(223) + OR ROM32_INSTR_PT(224) OR ROM32_INSTR_PT(227) + OR ROM32_INSTR_PT(232) OR ROM32_INSTR_PT(233) + OR ROM32_INSTR_PT(235) OR ROM32_INSTR_PT(238) + OR ROM32_INSTR_PT(240) OR ROM32_INSTR_PT(243) + OR ROM32_INSTR_PT(244) OR ROM32_INSTR_PT(249) + OR ROM32_INSTR_PT(251) OR ROM32_INSTR_PT(252) + OR ROM32_INSTR_PT(254) OR ROM32_INSTR_PT(256) + OR ROM32_INSTR_PT(259) OR ROM32_INSTR_PT(261) + OR ROM32_INSTR_PT(264) OR ROM32_INSTR_PT(266) + OR ROM32_INSTR_PT(267) OR ROM32_INSTR_PT(268) + OR ROM32_INSTR_PT(269) OR ROM32_INSTR_PT(271) + OR ROM32_INSTR_PT(274) OR ROM32_INSTR_PT(276) + OR ROM32_INSTR_PT(278) OR ROM32_INSTR_PT(280) + OR ROM32_INSTR_PT(281) OR ROM32_INSTR_PT(284) + OR ROM32_INSTR_PT(288) OR ROM32_INSTR_PT(290) + OR ROM32_INSTR_PT(294) OR ROM32_INSTR_PT(295) + OR ROM32_INSTR_PT(297) OR ROM32_INSTR_PT(299) + OR ROM32_INSTR_PT(301) OR ROM32_INSTR_PT(309) + OR ROM32_INSTR_PT(310) OR ROM32_INSTR_PT(323) + OR ROM32_INSTR_PT(335) OR ROM32_INSTR_PT(344) + OR ROM32_INSTR_PT(348) OR ROM32_INSTR_PT(350) + OR ROM32_INSTR_PT(361) OR ROM32_INSTR_PT(363) + OR ROM32_INSTR_PT(364) OR ROM32_INSTR_PT(367) + OR ROM32_INSTR_PT(371) OR ROM32_INSTR_PT(373) + OR ROM32_INSTR_PT(376) OR ROM32_INSTR_PT(378) + OR ROM32_INSTR_PT(379) OR ROM32_INSTR_PT(381) + OR ROM32_INSTR_PT(382) OR ROM32_INSTR_PT(383) + OR ROM32_INSTR_PT(386) OR ROM32_INSTR_PT(390) + OR ROM32_INSTR_PT(392) OR ROM32_INSTR_PT(394) + OR ROM32_INSTR_PT(395) OR ROM32_INSTR_PT(396) + OR ROM32_INSTR_PT(398) OR ROM32_INSTR_PT(400) + OR ROM32_INSTR_PT(402) OR ROM32_INSTR_PT(405) + OR ROM32_INSTR_PT(406) OR ROM32_INSTR_PT(411) + OR ROM32_INSTR_PT(416) OR ROM32_INSTR_PT(417) + OR ROM32_INSTR_PT(419) OR ROM32_INSTR_PT(422) + OR ROM32_INSTR_PT(423) OR ROM32_INSTR_PT(424) + OR ROM32_INSTR_PT(425) OR ROM32_INSTR_PT(426) + OR ROM32_INSTR_PT(430) OR ROM32_INSTR_PT(431) + OR ROM32_INSTR_PT(434) OR ROM32_INSTR_PT(435) + OR ROM32_INSTR_PT(436) OR ROM32_INSTR_PT(438) + OR ROM32_INSTR_PT(441) OR ROM32_INSTR_PT(442) + OR ROM32_INSTR_PT(452) OR ROM32_INSTR_PT(453) + OR ROM32_INSTR_PT(456) OR ROM32_INSTR_PT(458) + OR ROM32_INSTR_PT(464) OR ROM32_INSTR_PT(469) + OR ROM32_INSTR_PT(472) OR ROM32_INSTR_PT(474) + OR ROM32_INSTR_PT(475) OR ROM32_INSTR_PT(478) + OR ROM32_INSTR_PT(479) OR ROM32_INSTR_PT(481) + OR ROM32_INSTR_PT(482) OR ROM32_INSTR_PT(484) + OR ROM32_INSTR_PT(486) OR ROM32_INSTR_PT(494) + OR ROM32_INSTR_PT(503) OR ROM32_INSTR_PT(506) + OR ROM32_INSTR_PT(507) OR ROM32_INSTR_PT(511) + OR ROM32_INSTR_PT(514) OR ROM32_INSTR_PT(517) + OR ROM32_INSTR_PT(520) OR ROM32_INSTR_PT(521) + OR ROM32_INSTR_PT(522) OR ROM32_INSTR_PT(524) + OR ROM32_INSTR_PT(530) OR ROM32_INSTR_PT(531) + OR ROM32_INSTR_PT(532) OR ROM32_INSTR_PT(534) + OR ROM32_INSTR_PT(541) OR ROM32_INSTR_PT(550) + OR ROM32_INSTR_PT(551) OR ROM32_INSTR_PT(552) + OR ROM32_INSTR_PT(554) OR ROM32_INSTR_PT(555) + OR ROM32_INSTR_PT(562) OR ROM32_INSTR_PT(563) + OR ROM32_INSTR_PT(566) OR ROM32_INSTR_PT(569) + OR ROM32_INSTR_PT(570) OR ROM32_INSTR_PT(575) + OR ROM32_INSTR_PT(577) OR ROM32_INSTR_PT(579) + OR ROM32_INSTR_PT(580) OR ROM32_INSTR_PT(581) + OR ROM32_INSTR_PT(582) OR ROM32_INSTR_PT(583) + OR ROM32_INSTR_PT(584) OR ROM32_INSTR_PT(588) + OR ROM32_INSTR_PT(591) OR ROM32_INSTR_PT(599) + OR ROM32_INSTR_PT(601) OR ROM32_INSTR_PT(602) + OR ROM32_INSTR_PT(605) OR ROM32_INSTR_PT(610) + OR ROM32_INSTR_PT(615) OR ROM32_INSTR_PT(620) + OR ROM32_INSTR_PT(622) OR ROM32_INSTR_PT(626) + OR ROM32_INSTR_PT(629) OR ROM32_INSTR_PT(630) + OR ROM32_INSTR_PT(634) OR ROM32_INSTR_PT(638) + OR ROM32_INSTR_PT(639) OR ROM32_INSTR_PT(640) + OR ROM32_INSTR_PT(642) OR ROM32_INSTR_PT(643) + OR ROM32_INSTR_PT(654) OR ROM32_INSTR_PT(660) + OR ROM32_INSTR_PT(663) OR ROM32_INSTR_PT(664) + OR ROM32_INSTR_PT(666) OR ROM32_INSTR_PT(674) + OR ROM32_INSTR_PT(677) OR ROM32_INSTR_PT(684) + OR ROM32_INSTR_PT(693) OR ROM32_INSTR_PT(697) + OR ROM32_INSTR_PT(708) OR ROM32_INSTR_PT(719) + OR ROM32_INSTR_PT(720) OR ROM32_INSTR_PT(729) + OR ROM32_INSTR_PT(745) OR ROM32_INSTR_PT(755) + OR ROM32_INSTR_PT(763) OR ROM32_INSTR_PT(792) + OR ROM32_INSTR_PT(805) OR ROM32_INSTR_PT(807) + OR ROM32_INSTR_PT(812) OR ROM32_INSTR_PT(818) + OR ROM32_INSTR_PT(819) OR ROM32_INSTR_PT(823) + OR ROM32_INSTR_PT(829) OR ROM32_INSTR_PT(831) + OR ROM32_INSTR_PT(853) OR ROM32_INSTR_PT(854) + OR ROM32_INSTR_PT(855) OR ROM32_INSTR_PT(862) + OR ROM32_INSTR_PT(870) OR ROM32_INSTR_PT(878) + ); +MQQ1883:TEMPLATE(28) <= + (ROM32_INSTR_PT(3) OR ROM32_INSTR_PT(4) + OR ROM32_INSTR_PT(5) OR ROM32_INSTR_PT(8) + OR ROM32_INSTR_PT(9) OR ROM32_INSTR_PT(12) + OR ROM32_INSTR_PT(13) OR ROM32_INSTR_PT(16) + OR ROM32_INSTR_PT(17) OR ROM32_INSTR_PT(26) + OR ROM32_INSTR_PT(32) OR ROM32_INSTR_PT(37) + OR ROM32_INSTR_PT(39) OR ROM32_INSTR_PT(41) + OR ROM32_INSTR_PT(45) OR ROM32_INSTR_PT(51) + OR ROM32_INSTR_PT(52) OR ROM32_INSTR_PT(56) + OR ROM32_INSTR_PT(57) OR ROM32_INSTR_PT(59) + OR ROM32_INSTR_PT(63) OR ROM32_INSTR_PT(66) + OR ROM32_INSTR_PT(67) OR ROM32_INSTR_PT(72) + OR ROM32_INSTR_PT(73) OR ROM32_INSTR_PT(74) + OR ROM32_INSTR_PT(77) OR ROM32_INSTR_PT(83) + OR ROM32_INSTR_PT(84) OR ROM32_INSTR_PT(85) + OR ROM32_INSTR_PT(87) OR ROM32_INSTR_PT(90) + OR ROM32_INSTR_PT(93) OR ROM32_INSTR_PT(95) + OR ROM32_INSTR_PT(98) OR ROM32_INSTR_PT(99) + OR ROM32_INSTR_PT(100) OR ROM32_INSTR_PT(101) + OR ROM32_INSTR_PT(102) OR ROM32_INSTR_PT(103) + OR ROM32_INSTR_PT(106) OR ROM32_INSTR_PT(109) + OR ROM32_INSTR_PT(114) OR ROM32_INSTR_PT(115) + OR ROM32_INSTR_PT(116) OR ROM32_INSTR_PT(118) + OR ROM32_INSTR_PT(124) OR ROM32_INSTR_PT(125) + OR ROM32_INSTR_PT(127) OR ROM32_INSTR_PT(132) + OR ROM32_INSTR_PT(134) OR ROM32_INSTR_PT(135) + OR ROM32_INSTR_PT(139) OR ROM32_INSTR_PT(141) + OR ROM32_INSTR_PT(142) OR ROM32_INSTR_PT(143) + OR ROM32_INSTR_PT(148) OR ROM32_INSTR_PT(153) + OR ROM32_INSTR_PT(155) OR ROM32_INSTR_PT(158) + OR ROM32_INSTR_PT(159) OR ROM32_INSTR_PT(163) + OR ROM32_INSTR_PT(169) OR ROM32_INSTR_PT(171) + OR ROM32_INSTR_PT(179) OR ROM32_INSTR_PT(183) + OR ROM32_INSTR_PT(184) OR ROM32_INSTR_PT(192) + OR ROM32_INSTR_PT(194) OR ROM32_INSTR_PT(196) + OR ROM32_INSTR_PT(199) OR ROM32_INSTR_PT(200) + OR ROM32_INSTR_PT(202) OR ROM32_INSTR_PT(203) + OR ROM32_INSTR_PT(204) OR ROM32_INSTR_PT(207) + OR ROM32_INSTR_PT(216) OR ROM32_INSTR_PT(219) + OR ROM32_INSTR_PT(220) OR ROM32_INSTR_PT(223) + OR ROM32_INSTR_PT(227) OR ROM32_INSTR_PT(238) + OR ROM32_INSTR_PT(241) OR ROM32_INSTR_PT(243) + OR ROM32_INSTR_PT(249) OR ROM32_INSTR_PT(250) + OR ROM32_INSTR_PT(251) OR ROM32_INSTR_PT(254) + OR ROM32_INSTR_PT(256) OR ROM32_INSTR_PT(259) + OR ROM32_INSTR_PT(260) OR ROM32_INSTR_PT(261) + OR ROM32_INSTR_PT(264) OR ROM32_INSTR_PT(266) + OR ROM32_INSTR_PT(267) OR ROM32_INSTR_PT(268) + OR ROM32_INSTR_PT(269) OR ROM32_INSTR_PT(270) + OR ROM32_INSTR_PT(273) OR ROM32_INSTR_PT(280) + OR ROM32_INSTR_PT(281) OR ROM32_INSTR_PT(282) + OR ROM32_INSTR_PT(284) OR ROM32_INSTR_PT(288) + OR ROM32_INSTR_PT(290) OR ROM32_INSTR_PT(293) + OR ROM32_INSTR_PT(294) OR ROM32_INSTR_PT(295) + OR ROM32_INSTR_PT(297) OR ROM32_INSTR_PT(299) + OR ROM32_INSTR_PT(301) OR ROM32_INSTR_PT(303) + OR ROM32_INSTR_PT(306) OR ROM32_INSTR_PT(309) + OR ROM32_INSTR_PT(313) OR ROM32_INSTR_PT(318) + OR ROM32_INSTR_PT(328) OR ROM32_INSTR_PT(335) + OR ROM32_INSTR_PT(344) OR ROM32_INSTR_PT(348) + OR ROM32_INSTR_PT(350) OR ROM32_INSTR_PT(361) + OR ROM32_INSTR_PT(367) OR ROM32_INSTR_PT(371) + OR ROM32_INSTR_PT(374) OR ROM32_INSTR_PT(376) + OR ROM32_INSTR_PT(379) OR ROM32_INSTR_PT(381) + OR ROM32_INSTR_PT(382) OR ROM32_INSTR_PT(383) + OR ROM32_INSTR_PT(386) OR ROM32_INSTR_PT(390) + OR ROM32_INSTR_PT(392) OR ROM32_INSTR_PT(394) + OR ROM32_INSTR_PT(398) OR ROM32_INSTR_PT(401) + OR ROM32_INSTR_PT(402) OR ROM32_INSTR_PT(406) + OR ROM32_INSTR_PT(409) OR ROM32_INSTR_PT(411) + OR ROM32_INSTR_PT(412) OR ROM32_INSTR_PT(415) + OR ROM32_INSTR_PT(421) OR ROM32_INSTR_PT(422) + OR ROM32_INSTR_PT(423) OR ROM32_INSTR_PT(425) + OR ROM32_INSTR_PT(426) OR ROM32_INSTR_PT(428) + OR ROM32_INSTR_PT(431) OR ROM32_INSTR_PT(433) + OR ROM32_INSTR_PT(437) OR ROM32_INSTR_PT(443) + OR ROM32_INSTR_PT(451) OR ROM32_INSTR_PT(453) + OR ROM32_INSTR_PT(458) OR ROM32_INSTR_PT(464) + OR ROM32_INSTR_PT(469) OR ROM32_INSTR_PT(472) + OR ROM32_INSTR_PT(475) OR ROM32_INSTR_PT(478) + OR ROM32_INSTR_PT(479) OR ROM32_INSTR_PT(481) + OR ROM32_INSTR_PT(482) OR ROM32_INSTR_PT(484) + OR ROM32_INSTR_PT(486) OR ROM32_INSTR_PT(490) + OR ROM32_INSTR_PT(491) OR ROM32_INSTR_PT(494) + OR ROM32_INSTR_PT(495) OR ROM32_INSTR_PT(501) + OR ROM32_INSTR_PT(502) OR ROM32_INSTR_PT(503) + OR ROM32_INSTR_PT(504) OR ROM32_INSTR_PT(506) + OR ROM32_INSTR_PT(508) OR ROM32_INSTR_PT(509) + OR ROM32_INSTR_PT(514) OR ROM32_INSTR_PT(519) + OR ROM32_INSTR_PT(520) OR ROM32_INSTR_PT(522) + OR ROM32_INSTR_PT(524) OR ROM32_INSTR_PT(530) + OR ROM32_INSTR_PT(531) OR ROM32_INSTR_PT(534) + OR ROM32_INSTR_PT(544) OR ROM32_INSTR_PT(550) + OR ROM32_INSTR_PT(551) OR ROM32_INSTR_PT(552) + OR ROM32_INSTR_PT(554) OR ROM32_INSTR_PT(555) + OR ROM32_INSTR_PT(556) OR ROM32_INSTR_PT(557) + OR ROM32_INSTR_PT(562) OR ROM32_INSTR_PT(563) + OR ROM32_INSTR_PT(568) OR ROM32_INSTR_PT(578) + OR ROM32_INSTR_PT(579) OR ROM32_INSTR_PT(581) + OR ROM32_INSTR_PT(582) OR ROM32_INSTR_PT(585) + OR ROM32_INSTR_PT(588) OR ROM32_INSTR_PT(590) + OR ROM32_INSTR_PT(591) OR ROM32_INSTR_PT(595) + OR ROM32_INSTR_PT(600) OR ROM32_INSTR_PT(602) + OR ROM32_INSTR_PT(605) OR ROM32_INSTR_PT(609) + OR ROM32_INSTR_PT(612) OR ROM32_INSTR_PT(613) + OR ROM32_INSTR_PT(615) OR ROM32_INSTR_PT(621) + OR ROM32_INSTR_PT(624) OR ROM32_INSTR_PT(626) + OR ROM32_INSTR_PT(629) OR ROM32_INSTR_PT(630) + OR ROM32_INSTR_PT(639) OR ROM32_INSTR_PT(640) + OR ROM32_INSTR_PT(642) OR ROM32_INSTR_PT(643) + OR ROM32_INSTR_PT(644) OR ROM32_INSTR_PT(654) + OR ROM32_INSTR_PT(660) OR ROM32_INSTR_PT(664) + OR ROM32_INSTR_PT(666) OR ROM32_INSTR_PT(674) + OR ROM32_INSTR_PT(677) OR ROM32_INSTR_PT(697) + OR ROM32_INSTR_PT(708) OR ROM32_INSTR_PT(719) + OR ROM32_INSTR_PT(728) OR ROM32_INSTR_PT(729) + OR ROM32_INSTR_PT(731) OR ROM32_INSTR_PT(736) + OR ROM32_INSTR_PT(751) OR ROM32_INSTR_PT(753) + OR ROM32_INSTR_PT(755) OR ROM32_INSTR_PT(762) + OR ROM32_INSTR_PT(763) OR ROM32_INSTR_PT(770) + OR ROM32_INSTR_PT(792) OR ROM32_INSTR_PT(805) + OR ROM32_INSTR_PT(812) OR ROM32_INSTR_PT(819) + OR ROM32_INSTR_PT(829) OR ROM32_INSTR_PT(854) + OR ROM32_INSTR_PT(855) OR ROM32_INSTR_PT(862) + OR ROM32_INSTR_PT(870) OR ROM32_INSTR_PT(878) + ); +MQQ1884:TEMPLATE(29) <= + (ROM32_INSTR_PT(3) OR ROM32_INSTR_PT(4) + OR ROM32_INSTR_PT(5) OR ROM32_INSTR_PT(6) + OR ROM32_INSTR_PT(7) OR ROM32_INSTR_PT(8) + OR ROM32_INSTR_PT(9) OR ROM32_INSTR_PT(10) + OR ROM32_INSTR_PT(13) OR ROM32_INSTR_PT(14) + OR ROM32_INSTR_PT(16) OR ROM32_INSTR_PT(17) + OR ROM32_INSTR_PT(23) OR ROM32_INSTR_PT(26) + OR ROM32_INSTR_PT(27) OR ROM32_INSTR_PT(30) + OR ROM32_INSTR_PT(37) OR ROM32_INSTR_PT(41) + OR ROM32_INSTR_PT(49) OR ROM32_INSTR_PT(51) + OR ROM32_INSTR_PT(52) OR ROM32_INSTR_PT(53) + OR ROM32_INSTR_PT(59) OR ROM32_INSTR_PT(63) + OR ROM32_INSTR_PT(66) OR ROM32_INSTR_PT(67) + OR ROM32_INSTR_PT(73) OR ROM32_INSTR_PT(74) + OR ROM32_INSTR_PT(77) OR ROM32_INSTR_PT(78) + OR ROM32_INSTR_PT(84) OR ROM32_INSTR_PT(87) + OR ROM32_INSTR_PT(90) OR ROM32_INSTR_PT(93) + OR ROM32_INSTR_PT(97) OR ROM32_INSTR_PT(99) + OR ROM32_INSTR_PT(100) OR ROM32_INSTR_PT(103) + OR ROM32_INSTR_PT(106) OR ROM32_INSTR_PT(114) + OR ROM32_INSTR_PT(115) OR ROM32_INSTR_PT(116) + OR ROM32_INSTR_PT(117) OR ROM32_INSTR_PT(118) + OR ROM32_INSTR_PT(124) OR ROM32_INSTR_PT(127) + OR ROM32_INSTR_PT(130) OR ROM32_INSTR_PT(131) + OR ROM32_INSTR_PT(132) OR ROM32_INSTR_PT(134) + OR ROM32_INSTR_PT(135) OR ROM32_INSTR_PT(139) + OR ROM32_INSTR_PT(148) OR ROM32_INSTR_PT(153) + OR ROM32_INSTR_PT(159) OR ROM32_INSTR_PT(164) + OR ROM32_INSTR_PT(169) OR ROM32_INSTR_PT(171) + OR ROM32_INSTR_PT(172) OR ROM32_INSTR_PT(181) + OR ROM32_INSTR_PT(183) OR ROM32_INSTR_PT(184) + OR ROM32_INSTR_PT(187) OR ROM32_INSTR_PT(194) + OR ROM32_INSTR_PT(200) OR ROM32_INSTR_PT(204) + OR ROM32_INSTR_PT(205) OR ROM32_INSTR_PT(212) + OR ROM32_INSTR_PT(216) OR ROM32_INSTR_PT(219) + OR ROM32_INSTR_PT(220) OR ROM32_INSTR_PT(223) + OR ROM32_INSTR_PT(227) OR ROM32_INSTR_PT(229) + OR ROM32_INSTR_PT(232) OR ROM32_INSTR_PT(235) + OR ROM32_INSTR_PT(238) OR ROM32_INSTR_PT(241) + OR ROM32_INSTR_PT(244) OR ROM32_INSTR_PT(250) + OR ROM32_INSTR_PT(251) OR ROM32_INSTR_PT(256) + OR ROM32_INSTR_PT(259) OR ROM32_INSTR_PT(260) + OR ROM32_INSTR_PT(261) OR ROM32_INSTR_PT(264) + OR ROM32_INSTR_PT(267) OR ROM32_INSTR_PT(269) + OR ROM32_INSTR_PT(270) OR ROM32_INSTR_PT(271) + OR ROM32_INSTR_PT(273) OR ROM32_INSTR_PT(274) + OR ROM32_INSTR_PT(275) OR ROM32_INSTR_PT(280) + OR ROM32_INSTR_PT(281) OR ROM32_INSTR_PT(282) + OR ROM32_INSTR_PT(284) OR ROM32_INSTR_PT(288) + OR ROM32_INSTR_PT(289) OR ROM32_INSTR_PT(290) + OR ROM32_INSTR_PT(293) OR ROM32_INSTR_PT(295) + OR ROM32_INSTR_PT(297) OR ROM32_INSTR_PT(299) + OR ROM32_INSTR_PT(301) OR ROM32_INSTR_PT(303) + OR ROM32_INSTR_PT(306) OR ROM32_INSTR_PT(309) + OR ROM32_INSTR_PT(310) OR ROM32_INSTR_PT(313) + OR ROM32_INSTR_PT(318) OR ROM32_INSTR_PT(322) + OR ROM32_INSTR_PT(323) OR ROM32_INSTR_PT(328) + OR ROM32_INSTR_PT(337) OR ROM32_INSTR_PT(348) + OR ROM32_INSTR_PT(361) OR ROM32_INSTR_PT(371) + OR ROM32_INSTR_PT(374) OR ROM32_INSTR_PT(378) + OR ROM32_INSTR_PT(379) OR ROM32_INSTR_PT(381) + OR ROM32_INSTR_PT(383) OR ROM32_INSTR_PT(387) + OR ROM32_INSTR_PT(390) OR ROM32_INSTR_PT(392) + OR ROM32_INSTR_PT(393) OR ROM32_INSTR_PT(398) + OR ROM32_INSTR_PT(400) OR ROM32_INSTR_PT(401) + OR ROM32_INSTR_PT(406) OR ROM32_INSTR_PT(409) + OR ROM32_INSTR_PT(411) OR ROM32_INSTR_PT(412) + OR ROM32_INSTR_PT(415) OR ROM32_INSTR_PT(416) + OR ROM32_INSTR_PT(419) OR ROM32_INSTR_PT(421) + OR ROM32_INSTR_PT(425) OR ROM32_INSTR_PT(426) + OR ROM32_INSTR_PT(428) OR ROM32_INSTR_PT(433) + OR ROM32_INSTR_PT(434) OR ROM32_INSTR_PT(435) + OR ROM32_INSTR_PT(436) OR ROM32_INSTR_PT(437) + OR ROM32_INSTR_PT(438) OR ROM32_INSTR_PT(441) + OR ROM32_INSTR_PT(443) OR ROM32_INSTR_PT(451) + OR ROM32_INSTR_PT(452) OR ROM32_INSTR_PT(465) + OR ROM32_INSTR_PT(475) OR ROM32_INSTR_PT(478) + OR ROM32_INSTR_PT(479) OR ROM32_INSTR_PT(481) + OR ROM32_INSTR_PT(482) OR ROM32_INSTR_PT(490) + OR ROM32_INSTR_PT(494) OR ROM32_INSTR_PT(495) + OR ROM32_INSTR_PT(501) OR ROM32_INSTR_PT(502) + OR ROM32_INSTR_PT(506) OR ROM32_INSTR_PT(507) + OR ROM32_INSTR_PT(508) OR ROM32_INSTR_PT(509) + OR ROM32_INSTR_PT(511) OR ROM32_INSTR_PT(517) + OR ROM32_INSTR_PT(519) OR ROM32_INSTR_PT(520) + OR ROM32_INSTR_PT(522) OR ROM32_INSTR_PT(524) + OR ROM32_INSTR_PT(530) OR ROM32_INSTR_PT(531) + OR ROM32_INSTR_PT(532) OR ROM32_INSTR_PT(534) + OR ROM32_INSTR_PT(535) OR ROM32_INSTR_PT(543) + OR ROM32_INSTR_PT(544) OR ROM32_INSTR_PT(547) + OR ROM32_INSTR_PT(550) OR ROM32_INSTR_PT(552) + OR ROM32_INSTR_PT(554) OR ROM32_INSTR_PT(556) + OR ROM32_INSTR_PT(557) OR ROM32_INSTR_PT(558) + OR ROM32_INSTR_PT(562) OR ROM32_INSTR_PT(563) + OR ROM32_INSTR_PT(566) OR ROM32_INSTR_PT(568) + OR ROM32_INSTR_PT(570) OR ROM32_INSTR_PT(574) + OR ROM32_INSTR_PT(575) OR ROM32_INSTR_PT(578) + OR ROM32_INSTR_PT(579) OR ROM32_INSTR_PT(580) + OR ROM32_INSTR_PT(581) OR ROM32_INSTR_PT(582) + OR ROM32_INSTR_PT(584) OR ROM32_INSTR_PT(585) + OR ROM32_INSTR_PT(587) OR ROM32_INSTR_PT(590) + OR ROM32_INSTR_PT(595) OR ROM32_INSTR_PT(599) + OR ROM32_INSTR_PT(600) OR ROM32_INSTR_PT(601) + OR ROM32_INSTR_PT(602) OR ROM32_INSTR_PT(609) + OR ROM32_INSTR_PT(612) OR ROM32_INSTR_PT(622) + OR ROM32_INSTR_PT(624) OR ROM32_INSTR_PT(625) + OR ROM32_INSTR_PT(626) OR ROM32_INSTR_PT(629) + OR ROM32_INSTR_PT(630) OR ROM32_INSTR_PT(634) + OR ROM32_INSTR_PT(638) OR ROM32_INSTR_PT(639) + OR ROM32_INSTR_PT(640) OR ROM32_INSTR_PT(642) + OR ROM32_INSTR_PT(644) OR ROM32_INSTR_PT(663) + OR ROM32_INSTR_PT(664) OR ROM32_INSTR_PT(666) + OR ROM32_INSTR_PT(677) OR ROM32_INSTR_PT(684) + OR ROM32_INSTR_PT(693) OR ROM32_INSTR_PT(697) + OR ROM32_INSTR_PT(719) OR ROM32_INSTR_PT(726) + OR ROM32_INSTR_PT(728) OR ROM32_INSTR_PT(736) + OR ROM32_INSTR_PT(751) OR ROM32_INSTR_PT(753) + OR ROM32_INSTR_PT(755) OR ROM32_INSTR_PT(762) + OR ROM32_INSTR_PT(770) OR ROM32_INSTR_PT(792) + OR ROM32_INSTR_PT(829) OR ROM32_INSTR_PT(845) + OR ROM32_INSTR_PT(853) OR ROM32_INSTR_PT(855) + OR ROM32_INSTR_PT(862) OR ROM32_INSTR_PT(870) + ); +MQQ1885:TEMPLATE(30) <= + (ROM32_INSTR_PT(3) OR ROM32_INSTR_PT(4) + OR ROM32_INSTR_PT(6) OR ROM32_INSTR_PT(8) + OR ROM32_INSTR_PT(9) OR ROM32_INSTR_PT(13) + OR ROM32_INSTR_PT(16) OR ROM32_INSTR_PT(17) + OR ROM32_INSTR_PT(20) OR ROM32_INSTR_PT(26) + OR ROM32_INSTR_PT(32) OR ROM32_INSTR_PT(37) + OR ROM32_INSTR_PT(41) OR ROM32_INSTR_PT(45) + OR ROM32_INSTR_PT(49) OR ROM32_INSTR_PT(50) + OR ROM32_INSTR_PT(51) OR ROM32_INSTR_PT(52) + OR ROM32_INSTR_PT(55) OR ROM32_INSTR_PT(59) + OR ROM32_INSTR_PT(63) OR ROM32_INSTR_PT(66) + OR ROM32_INSTR_PT(67) OR ROM32_INSTR_PT(73) + OR ROM32_INSTR_PT(74) OR ROM32_INSTR_PT(77) + OR ROM32_INSTR_PT(78) OR ROM32_INSTR_PT(79) + OR ROM32_INSTR_PT(80) OR ROM32_INSTR_PT(84) + OR ROM32_INSTR_PT(85) OR ROM32_INSTR_PT(87) + OR ROM32_INSTR_PT(90) OR ROM32_INSTR_PT(92) + OR ROM32_INSTR_PT(99) OR ROM32_INSTR_PT(100) + OR ROM32_INSTR_PT(103) OR ROM32_INSTR_PT(105) + OR ROM32_INSTR_PT(106) OR ROM32_INSTR_PT(111) + OR ROM32_INSTR_PT(114) OR ROM32_INSTR_PT(115) + OR ROM32_INSTR_PT(116) OR ROM32_INSTR_PT(117) + OR ROM32_INSTR_PT(118) OR ROM32_INSTR_PT(119) + OR ROM32_INSTR_PT(122) OR ROM32_INSTR_PT(124) + OR ROM32_INSTR_PT(127) OR ROM32_INSTR_PT(130) + OR ROM32_INSTR_PT(134) OR ROM32_INSTR_PT(135) + OR ROM32_INSTR_PT(139) OR ROM32_INSTR_PT(142) + OR ROM32_INSTR_PT(148) OR ROM32_INSTR_PT(153) + OR ROM32_INSTR_PT(169) OR ROM32_INSTR_PT(171) + OR ROM32_INSTR_PT(176) OR ROM32_INSTR_PT(179) + OR ROM32_INSTR_PT(180) OR ROM32_INSTR_PT(181) + OR ROM32_INSTR_PT(183) OR ROM32_INSTR_PT(184) + OR ROM32_INSTR_PT(186) OR ROM32_INSTR_PT(194) + OR ROM32_INSTR_PT(200) OR ROM32_INSTR_PT(204) + OR ROM32_INSTR_PT(209) OR ROM32_INSTR_PT(214) + OR ROM32_INSTR_PT(215) OR ROM32_INSTR_PT(216) + OR ROM32_INSTR_PT(219) OR ROM32_INSTR_PT(220) + OR ROM32_INSTR_PT(222) OR ROM32_INSTR_PT(223) + OR ROM32_INSTR_PT(224) OR ROM32_INSTR_PT(227) + OR ROM32_INSTR_PT(229) OR ROM32_INSTR_PT(233) + OR ROM32_INSTR_PT(238) OR ROM32_INSTR_PT(241) + OR ROM32_INSTR_PT(250) OR ROM32_INSTR_PT(254) + OR ROM32_INSTR_PT(256) OR ROM32_INSTR_PT(259) + OR ROM32_INSTR_PT(260) OR ROM32_INSTR_PT(261) + OR ROM32_INSTR_PT(264) OR ROM32_INSTR_PT(267) + OR ROM32_INSTR_PT(269) OR ROM32_INSTR_PT(270) + OR ROM32_INSTR_PT(272) OR ROM32_INSTR_PT(273) + OR ROM32_INSTR_PT(274) OR ROM32_INSTR_PT(278) + OR ROM32_INSTR_PT(280) OR ROM32_INSTR_PT(282) + OR ROM32_INSTR_PT(283) OR ROM32_INSTR_PT(288) + OR ROM32_INSTR_PT(293) OR ROM32_INSTR_PT(295) + OR ROM32_INSTR_PT(297) OR ROM32_INSTR_PT(299) + OR ROM32_INSTR_PT(301) OR ROM32_INSTR_PT(303) + OR ROM32_INSTR_PT(306) OR ROM32_INSTR_PT(313) + OR ROM32_INSTR_PT(318) OR ROM32_INSTR_PT(321) + OR ROM32_INSTR_PT(328) OR ROM32_INSTR_PT(335) + OR ROM32_INSTR_PT(343) OR ROM32_INSTR_PT(345) + OR ROM32_INSTR_PT(346) OR ROM32_INSTR_PT(348) + OR ROM32_INSTR_PT(356) OR ROM32_INSTR_PT(361) + OR ROM32_INSTR_PT(364) OR ROM32_INSTR_PT(366) + OR ROM32_INSTR_PT(368) OR ROM32_INSTR_PT(371) + OR ROM32_INSTR_PT(373) OR ROM32_INSTR_PT(374) + OR ROM32_INSTR_PT(379) OR ROM32_INSTR_PT(383) + OR ROM32_INSTR_PT(390) OR ROM32_INSTR_PT(392) + OR ROM32_INSTR_PT(393) OR ROM32_INSTR_PT(396) + OR ROM32_INSTR_PT(400) OR ROM32_INSTR_PT(401) + OR ROM32_INSTR_PT(406) OR ROM32_INSTR_PT(409) + OR ROM32_INSTR_PT(411) OR ROM32_INSTR_PT(412) + OR ROM32_INSTR_PT(415) OR ROM32_INSTR_PT(421) + OR ROM32_INSTR_PT(424) OR ROM32_INSTR_PT(426) + OR ROM32_INSTR_PT(428) OR ROM32_INSTR_PT(431) + OR ROM32_INSTR_PT(433) OR ROM32_INSTR_PT(437) + OR ROM32_INSTR_PT(441) OR ROM32_INSTR_PT(443) + OR ROM32_INSTR_PT(451) OR ROM32_INSTR_PT(459) + OR ROM32_INSTR_PT(461) OR ROM32_INSTR_PT(475) + OR ROM32_INSTR_PT(476) OR ROM32_INSTR_PT(478) + OR ROM32_INSTR_PT(479) OR ROM32_INSTR_PT(481) + OR ROM32_INSTR_PT(482) OR ROM32_INSTR_PT(490) + OR ROM32_INSTR_PT(494) OR ROM32_INSTR_PT(495) + OR ROM32_INSTR_PT(501) OR ROM32_INSTR_PT(502) + OR ROM32_INSTR_PT(506) OR ROM32_INSTR_PT(507) + OR ROM32_INSTR_PT(508) OR ROM32_INSTR_PT(509) + OR ROM32_INSTR_PT(519) OR ROM32_INSTR_PT(520) + OR ROM32_INSTR_PT(521) OR ROM32_INSTR_PT(522) + OR ROM32_INSTR_PT(524) OR ROM32_INSTR_PT(534) + OR ROM32_INSTR_PT(539) OR ROM32_INSTR_PT(544) + OR ROM32_INSTR_PT(550) OR ROM32_INSTR_PT(552) + OR ROM32_INSTR_PT(554) OR ROM32_INSTR_PT(555) + OR ROM32_INSTR_PT(556) OR ROM32_INSTR_PT(557) + OR ROM32_INSTR_PT(558) OR ROM32_INSTR_PT(562) + OR ROM32_INSTR_PT(568) OR ROM32_INSTR_PT(570) + OR ROM32_INSTR_PT(575) OR ROM32_INSTR_PT(578) + OR ROM32_INSTR_PT(581) OR ROM32_INSTR_PT(582) + OR ROM32_INSTR_PT(583) OR ROM32_INSTR_PT(585) + OR ROM32_INSTR_PT(587) OR ROM32_INSTR_PT(588) + OR ROM32_INSTR_PT(590) OR ROM32_INSTR_PT(595) + OR ROM32_INSTR_PT(600) OR ROM32_INSTR_PT(602) + OR ROM32_INSTR_PT(603) OR ROM32_INSTR_PT(607) + OR ROM32_INSTR_PT(609) OR ROM32_INSTR_PT(612) + OR ROM32_INSTR_PT(615) OR ROM32_INSTR_PT(624) + OR ROM32_INSTR_PT(626) OR ROM32_INSTR_PT(629) + OR ROM32_INSTR_PT(630) OR ROM32_INSTR_PT(639) + OR ROM32_INSTR_PT(640) OR ROM32_INSTR_PT(642) + OR ROM32_INSTR_PT(644) OR ROM32_INSTR_PT(666) + OR ROM32_INSTR_PT(677) OR ROM32_INSTR_PT(683) + OR ROM32_INSTR_PT(685) OR ROM32_INSTR_PT(689) + OR ROM32_INSTR_PT(692) OR ROM32_INSTR_PT(711) + OR ROM32_INSTR_PT(719) OR ROM32_INSTR_PT(720) + OR ROM32_INSTR_PT(726) OR ROM32_INSTR_PT(728) + OR ROM32_INSTR_PT(729) OR ROM32_INSTR_PT(736) + OR ROM32_INSTR_PT(751) OR ROM32_INSTR_PT(753) + OR ROM32_INSTR_PT(755) OR ROM32_INSTR_PT(762) + OR ROM32_INSTR_PT(763) OR ROM32_INSTR_PT(770) + OR ROM32_INSTR_PT(807) OR ROM32_INSTR_PT(823) + OR ROM32_INSTR_PT(831) OR ROM32_INSTR_PT(845) + OR ROM32_INSTR_PT(855) OR ROM32_INSTR_PT(862) + OR ROM32_INSTR_PT(870)); +MQQ1886:TEMPLATE(31) <= + (ROM32_INSTR_PT(31) OR ROM32_INSTR_PT(62) + OR ROM32_INSTR_PT(81) OR ROM32_INSTR_PT(95) + OR ROM32_INSTR_PT(104) OR ROM32_INSTR_PT(145) + OR ROM32_INSTR_PT(147) OR ROM32_INSTR_PT(150) + OR ROM32_INSTR_PT(162) OR ROM32_INSTR_PT(175) + OR ROM32_INSTR_PT(185) OR ROM32_INSTR_PT(187) + OR ROM32_INSTR_PT(208) OR ROM32_INSTR_PT(210) + OR ROM32_INSTR_PT(225) OR ROM32_INSTR_PT(228) + OR ROM32_INSTR_PT(230) OR ROM32_INSTR_PT(232) + OR ROM32_INSTR_PT(235) OR ROM32_INSTR_PT(245) + OR ROM32_INSTR_PT(251) OR ROM32_INSTR_PT(279) + OR ROM32_INSTR_PT(285) OR ROM32_INSTR_PT(292) + OR ROM32_INSTR_PT(302) OR ROM32_INSTR_PT(307) + OR ROM32_INSTR_PT(312) OR ROM32_INSTR_PT(325) + OR ROM32_INSTR_PT(329) OR ROM32_INSTR_PT(338) + OR ROM32_INSTR_PT(378) OR ROM32_INSTR_PT(398) + OR ROM32_INSTR_PT(416) OR ROM32_INSTR_PT(419) + OR ROM32_INSTR_PT(463) OR ROM32_INSTR_PT(489) + OR ROM32_INSTR_PT(591) OR ROM32_INSTR_PT(629) + OR ROM32_INSTR_PT(632) OR ROM32_INSTR_PT(640) + OR ROM32_INSTR_PT(641) OR ROM32_INSTR_PT(653) + OR ROM32_INSTR_PT(672) OR ROM32_INSTR_PT(720) + OR ROM32_INSTR_PT(728) OR ROM32_INSTR_PT(751) + OR ROM32_INSTR_PT(752) OR ROM32_INSTR_PT(753) + OR ROM32_INSTR_PT(759) OR ROM32_INSTR_PT(774) + OR ROM32_INSTR_PT(787) OR ROM32_INSTR_PT(803) + OR ROM32_INSTR_PT(807) OR ROM32_INSTR_PT(823) + ); +MQQ1887:UCODE_END <= + (ROM32_INSTR_PT(198) OR ROM32_INSTR_PT(201) + OR ROM32_INSTR_PT(213) OR ROM32_INSTR_PT(384) + OR ROM32_INSTR_PT(438) OR ROM32_INSTR_PT(440) + OR ROM32_INSTR_PT(450) OR ROM32_INSTR_PT(513) + OR ROM32_INSTR_PT(515) OR ROM32_INSTR_PT(528) + OR ROM32_INSTR_PT(541) OR ROM32_INSTR_PT(548) + OR ROM32_INSTR_PT(553) OR ROM32_INSTR_PT(559) + OR ROM32_INSTR_PT(567) OR ROM32_INSTR_PT(573) + OR ROM32_INSTR_PT(576) OR ROM32_INSTR_PT(580) + OR ROM32_INSTR_PT(589) OR ROM32_INSTR_PT(599) + OR ROM32_INSTR_PT(600) OR ROM32_INSTR_PT(601) + OR ROM32_INSTR_PT(619) OR ROM32_INSTR_PT(663) + OR ROM32_INSTR_PT(668) OR ROM32_INSTR_PT(674) + OR ROM32_INSTR_PT(688) OR ROM32_INSTR_PT(694) + OR ROM32_INSTR_PT(699) OR ROM32_INSTR_PT(702) + OR ROM32_INSTR_PT(709) OR ROM32_INSTR_PT(714) + OR ROM32_INSTR_PT(733) OR ROM32_INSTR_PT(778) + OR ROM32_INSTR_PT(784) OR ROM32_INSTR_PT(812) + OR ROM32_INSTR_PT(818) OR ROM32_INSTR_PT(819) + OR ROM32_INSTR_PT(821) OR ROM32_INSTR_PT(824) + OR ROM32_INSTR_PT(840) OR ROM32_INSTR_PT(843) + OR ROM32_INSTR_PT(844) OR ROM32_INSTR_PT(847) + OR ROM32_INSTR_PT(853) OR ROM32_INSTR_PT(878) + ); +MQQ1888:UCODE_END_EARLY <= + (ROM32_INSTR_PT(372) OR ROM32_INSTR_PT(389) + OR ROM32_INSTR_PT(650) OR ROM32_INSTR_PT(673) + OR ROM32_INSTR_PT(681) OR ROM32_INSTR_PT(687) + OR ROM32_INSTR_PT(725) OR ROM32_INSTR_PT(734) + OR ROM32_INSTR_PT(750) OR ROM32_INSTR_PT(754) + OR ROM32_INSTR_PT(781) OR ROM32_INSTR_PT(782) + OR ROM32_INSTR_PT(794) OR ROM32_INSTR_PT(796) + OR ROM32_INSTR_PT(797) OR ROM32_INSTR_PT(802) + OR ROM32_INSTR_PT(808) OR ROM32_INSTR_PT(813) + OR ROM32_INSTR_PT(820) OR ROM32_INSTR_PT(827) + OR ROM32_INSTR_PT(873)); +MQQ1889:LOOP_BEGIN <= + (ROM32_INSTR_PT(24) OR ROM32_INSTR_PT(55) + OR ROM32_INSTR_PT(105) OR ROM32_INSTR_PT(124) + OR ROM32_INSTR_PT(147) OR ROM32_INSTR_PT(211) + OR ROM32_INSTR_PT(228) OR ROM32_INSTR_PT(230) + OR ROM32_INSTR_PT(239) OR ROM32_INSTR_PT(245) + OR ROM32_INSTR_PT(253) OR ROM32_INSTR_PT(304) + OR ROM32_INSTR_PT(308) OR ROM32_INSTR_PT(314) + OR ROM32_INSTR_PT(321) OR ROM32_INSTR_PT(345) + OR ROM32_INSTR_PT(366) OR ROM32_INSTR_PT(374) + OR ROM32_INSTR_PT(407) OR ROM32_INSTR_PT(408) + OR ROM32_INSTR_PT(432) OR ROM32_INSTR_PT(448) + OR ROM32_INSTR_PT(460) OR ROM32_INSTR_PT(483) + OR ROM32_INSTR_PT(490) OR ROM32_INSTR_PT(495) + OR ROM32_INSTR_PT(544) OR ROM32_INSTR_PT(557) + OR ROM32_INSTR_PT(571) OR ROM32_INSTR_PT(586) + OR ROM32_INSTR_PT(604)); +MQQ1890:LOOP_END <= + (ROM32_INSTR_PT(149) OR ROM32_INSTR_PT(156) + OR ROM32_INSTR_PT(372) OR ROM32_INSTR_PT(466) + OR ROM32_INSTR_PT(492) OR ROM32_INSTR_PT(500) + OR ROM32_INSTR_PT(564) OR ROM32_INSTR_PT(637) + OR ROM32_INSTR_PT(648) OR ROM32_INSTR_PT(655) + OR ROM32_INSTR_PT(679) OR ROM32_INSTR_PT(696) + OR ROM32_INSTR_PT(743) OR ROM32_INSTR_PT(769) + OR ROM32_INSTR_PT(773) OR ROM32_INSTR_PT(783) + OR ROM32_INSTR_PT(793) OR ROM32_INSTR_PT(802) + OR ROM32_INSTR_PT(809) OR ROM32_INSTR_PT(810) + OR ROM32_INSTR_PT(848) OR ROM32_INSTR_PT(861) + OR ROM32_INSTR_PT(874)); +MQQ1891:COUNT_SRC(0) <= + (ROM32_INSTR_PT(75) OR ROM32_INSTR_PT(744) + OR ROM32_INSTR_PT(761) OR ROM32_INSTR_PT(875) + OR ROM32_INSTR_PT(879) OR ROM32_INSTR_PT(880) + OR ROM32_INSTR_PT(883) OR ROM32_INSTR_PT(890) + OR ROM32_INSTR_PT(891) OR ROM32_INSTR_PT(892) + ); +MQQ1892:COUNT_SRC(1) <= + (ROM32_INSTR_PT(838) OR ROM32_INSTR_PT(875) + OR ROM32_INSTR_PT(880) OR ROM32_INSTR_PT(882) + OR ROM32_INSTR_PT(886) OR ROM32_INSTR_PT(891) + OR ROM32_INSTR_PT(892)); +MQQ1893:COUNT_SRC(2) <= + (ROM32_INSTR_PT(695) OR ROM32_INSTR_PT(744) + OR ROM32_INSTR_PT(761) OR ROM32_INSTR_PT(828) + OR ROM32_INSTR_PT(838) OR ROM32_INSTR_PT(890) + OR ROM32_INSTR_PT(891) OR ROM32_INSTR_PT(892) + ); +MQQ1894:EXTRT <= + (ROM32_INSTR_PT(3) OR ROM32_INSTR_PT(19) + OR ROM32_INSTR_PT(21) OR ROM32_INSTR_PT(25) + OR ROM32_INSTR_PT(40) OR ROM32_INSTR_PT(44) + OR ROM32_INSTR_PT(47) OR ROM32_INSTR_PT(69) + OR ROM32_INSTR_PT(72) OR ROM32_INSTR_PT(82) + OR ROM32_INSTR_PT(91) OR ROM32_INSTR_PT(94) + OR ROM32_INSTR_PT(95) OR ROM32_INSTR_PT(108) + OR ROM32_INSTR_PT(116) OR ROM32_INSTR_PT(121) + OR ROM32_INSTR_PT(131) OR ROM32_INSTR_PT(133) + OR ROM32_INSTR_PT(136) OR ROM32_INSTR_PT(139) + OR ROM32_INSTR_PT(151) OR ROM32_INSTR_PT(152) + OR ROM32_INSTR_PT(161) OR ROM32_INSTR_PT(164) + OR ROM32_INSTR_PT(168) OR ROM32_INSTR_PT(188) + OR ROM32_INSTR_PT(190) OR ROM32_INSTR_PT(197) + OR ROM32_INSTR_PT(221) OR ROM32_INSTR_PT(234) + OR ROM32_INSTR_PT(236) OR ROM32_INSTR_PT(247) + OR ROM32_INSTR_PT(251) OR ROM32_INSTR_PT(262) + OR ROM32_INSTR_PT(265) OR ROM32_INSTR_PT(266) + OR ROM32_INSTR_PT(277) OR ROM32_INSTR_PT(281) + OR ROM32_INSTR_PT(284) OR ROM32_INSTR_PT(296) + OR ROM32_INSTR_PT(300) OR ROM32_INSTR_PT(315) + OR ROM32_INSTR_PT(316) OR ROM32_INSTR_PT(317) + OR ROM32_INSTR_PT(327) OR ROM32_INSTR_PT(328) + OR ROM32_INSTR_PT(333) OR ROM32_INSTR_PT(336) + OR ROM32_INSTR_PT(349) OR ROM32_INSTR_PT(353) + OR ROM32_INSTR_PT(354) OR ROM32_INSTR_PT(380) + OR ROM32_INSTR_PT(381) OR ROM32_INSTR_PT(397) + OR ROM32_INSTR_PT(410) OR ROM32_INSTR_PT(415) + OR ROM32_INSTR_PT(420) OR ROM32_INSTR_PT(437) + OR ROM32_INSTR_PT(451) OR ROM32_INSTR_PT(457) + OR ROM32_INSTR_PT(461) OR ROM32_INSTR_PT(483) + OR ROM32_INSTR_PT(493) OR ROM32_INSTR_PT(525) + OR ROM32_INSTR_PT(529) OR ROM32_INSTR_PT(533) + OR ROM32_INSTR_PT(536) OR ROM32_INSTR_PT(587) + OR ROM32_INSTR_PT(591) OR ROM32_INSTR_PT(592) + OR ROM32_INSTR_PT(594) OR ROM32_INSTR_PT(623) + OR ROM32_INSTR_PT(627) OR ROM32_INSTR_PT(636) + OR ROM32_INSTR_PT(645) OR ROM32_INSTR_PT(656) + OR ROM32_INSTR_PT(665) OR ROM32_INSTR_PT(667) + OR ROM32_INSTR_PT(669) OR ROM32_INSTR_PT(671) + OR ROM32_INSTR_PT(686) OR ROM32_INSTR_PT(701) + OR ROM32_INSTR_PT(707) OR ROM32_INSTR_PT(712) + OR ROM32_INSTR_PT(721) OR ROM32_INSTR_PT(722) + OR ROM32_INSTR_PT(723) OR ROM32_INSTR_PT(730) + OR ROM32_INSTR_PT(735) OR ROM32_INSTR_PT(739) + OR ROM32_INSTR_PT(742) OR ROM32_INSTR_PT(746) + OR ROM32_INSTR_PT(756) OR ROM32_INSTR_PT(757) + OR ROM32_INSTR_PT(758) OR ROM32_INSTR_PT(760) + OR ROM32_INSTR_PT(764) OR ROM32_INSTR_PT(765) + OR ROM32_INSTR_PT(766) OR ROM32_INSTR_PT(767) + OR ROM32_INSTR_PT(768) OR ROM32_INSTR_PT(771) + OR ROM32_INSTR_PT(772) OR ROM32_INSTR_PT(775) + OR ROM32_INSTR_PT(776) OR ROM32_INSTR_PT(777) + OR ROM32_INSTR_PT(788) OR ROM32_INSTR_PT(789) + OR ROM32_INSTR_PT(791) OR ROM32_INSTR_PT(792) + OR ROM32_INSTR_PT(798) OR ROM32_INSTR_PT(804) + OR ROM32_INSTR_PT(806) OR ROM32_INSTR_PT(811) + OR ROM32_INSTR_PT(816) OR ROM32_INSTR_PT(826) + OR ROM32_INSTR_PT(833) OR ROM32_INSTR_PT(834) + OR ROM32_INSTR_PT(835) OR ROM32_INSTR_PT(837) + OR ROM32_INSTR_PT(841) OR ROM32_INSTR_PT(849) + OR ROM32_INSTR_PT(856) OR ROM32_INSTR_PT(858) + OR ROM32_INSTR_PT(859) OR ROM32_INSTR_PT(860) + OR ROM32_INSTR_PT(862) OR ROM32_INSTR_PT(863) + OR ROM32_INSTR_PT(864) OR ROM32_INSTR_PT(865) + OR ROM32_INSTR_PT(866) OR ROM32_INSTR_PT(867) + OR ROM32_INSTR_PT(870) OR ROM32_INSTR_PT(876) + OR ROM32_INSTR_PT(884) OR ROM32_INSTR_PT(885) + ); +MQQ1895:EXTS1 <= + (ROM32_INSTR_PT(3) OR ROM32_INSTR_PT(19) + OR ROM32_INSTR_PT(21) OR ROM32_INSTR_PT(28) + OR ROM32_INSTR_PT(36) OR ROM32_INSTR_PT(47) + OR ROM32_INSTR_PT(58) OR ROM32_INSTR_PT(82) + OR ROM32_INSTR_PT(91) OR ROM32_INSTR_PT(100) + OR ROM32_INSTR_PT(107) OR ROM32_INSTR_PT(135) + OR ROM32_INSTR_PT(136) OR ROM32_INSTR_PT(137) + OR ROM32_INSTR_PT(157) OR ROM32_INSTR_PT(167) + OR ROM32_INSTR_PT(193) OR ROM32_INSTR_PT(197) + OR ROM32_INSTR_PT(212) OR ROM32_INSTR_PT(226) + OR ROM32_INSTR_PT(231) OR ROM32_INSTR_PT(236) + OR ROM32_INSTR_PT(263) OR ROM32_INSTR_PT(277) + OR ROM32_INSTR_PT(286) OR ROM32_INSTR_PT(293) + OR ROM32_INSTR_PT(296) OR ROM32_INSTR_PT(298) + OR ROM32_INSTR_PT(315) OR ROM32_INSTR_PT(316) + OR ROM32_INSTR_PT(317) OR ROM32_INSTR_PT(324) + OR ROM32_INSTR_PT(327) OR ROM32_INSTR_PT(328) + OR ROM32_INSTR_PT(330) OR ROM32_INSTR_PT(336) + OR ROM32_INSTR_PT(346) OR ROM32_INSTR_PT(369) + OR ROM32_INSTR_PT(380) OR ROM32_INSTR_PT(397) + OR ROM32_INSTR_PT(410) OR ROM32_INSTR_PT(414) + OR ROM32_INSTR_PT(438) OR ROM32_INSTR_PT(447) + OR ROM32_INSTR_PT(457) OR ROM32_INSTR_PT(462) + OR ROM32_INSTR_PT(470) OR ROM32_INSTR_PT(488) + OR ROM32_INSTR_PT(493) OR ROM32_INSTR_PT(495) + OR ROM32_INSTR_PT(499) OR ROM32_INSTR_PT(526) + OR ROM32_INSTR_PT(542) OR ROM32_INSTR_PT(589) + OR ROM32_INSTR_PT(594) OR ROM32_INSTR_PT(599) + OR ROM32_INSTR_PT(623) OR ROM32_INSTR_PT(627) + OR ROM32_INSTR_PT(636) OR ROM32_INSTR_PT(645) + OR ROM32_INSTR_PT(651) OR ROM32_INSTR_PT(656) + OR ROM32_INSTR_PT(667) OR ROM32_INSTR_PT(669) + OR ROM32_INSTR_PT(670) OR ROM32_INSTR_PT(675) + OR ROM32_INSTR_PT(686) OR ROM32_INSTR_PT(691) + OR ROM32_INSTR_PT(692) OR ROM32_INSTR_PT(701) + OR ROM32_INSTR_PT(706) OR ROM32_INSTR_PT(707) + OR ROM32_INSTR_PT(710) OR ROM32_INSTR_PT(716) + OR ROM32_INSTR_PT(721) OR ROM32_INSTR_PT(722) + OR ROM32_INSTR_PT(730) OR ROM32_INSTR_PT(733) + OR ROM32_INSTR_PT(739) OR ROM32_INSTR_PT(741) + OR ROM32_INSTR_PT(742) OR ROM32_INSTR_PT(746) + OR ROM32_INSTR_PT(756) OR ROM32_INSTR_PT(757) + OR ROM32_INSTR_PT(758) OR ROM32_INSTR_PT(760) + OR ROM32_INSTR_PT(764) OR ROM32_INSTR_PT(765) + OR ROM32_INSTR_PT(767) OR ROM32_INSTR_PT(768) + OR ROM32_INSTR_PT(771) OR ROM32_INSTR_PT(775) + OR ROM32_INSTR_PT(776) OR ROM32_INSTR_PT(777) + OR ROM32_INSTR_PT(779) OR ROM32_INSTR_PT(788) + OR ROM32_INSTR_PT(789) OR ROM32_INSTR_PT(791) + OR ROM32_INSTR_PT(798) OR ROM32_INSTR_PT(801) + OR ROM32_INSTR_PT(804) OR ROM32_INSTR_PT(806) + OR ROM32_INSTR_PT(811) OR ROM32_INSTR_PT(812) + OR ROM32_INSTR_PT(816) OR ROM32_INSTR_PT(824) + OR ROM32_INSTR_PT(826) OR ROM32_INSTR_PT(830) + OR ROM32_INSTR_PT(832) OR ROM32_INSTR_PT(833) + OR ROM32_INSTR_PT(835) OR ROM32_INSTR_PT(837) + OR ROM32_INSTR_PT(841) OR ROM32_INSTR_PT(842) + OR ROM32_INSTR_PT(843) OR ROM32_INSTR_PT(846) + OR ROM32_INSTR_PT(847) OR ROM32_INSTR_PT(849) + OR ROM32_INSTR_PT(850) OR ROM32_INSTR_PT(852) + OR ROM32_INSTR_PT(858) OR ROM32_INSTR_PT(859) + OR ROM32_INSTR_PT(863) OR ROM32_INSTR_PT(865) + OR ROM32_INSTR_PT(867) OR ROM32_INSTR_PT(868) + OR ROM32_INSTR_PT(877) OR ROM32_INSTR_PT(878) + OR ROM32_INSTR_PT(888)); +MQQ1896:EXTS2 <= + (ROM32_INSTR_PT(21) OR ROM32_INSTR_PT(25) + OR ROM32_INSTR_PT(36) OR ROM32_INSTR_PT(44) + OR ROM32_INSTR_PT(47) OR ROM32_INSTR_PT(91) + OR ROM32_INSTR_PT(116) OR ROM32_INSTR_PT(136) + OR ROM32_INSTR_PT(137) OR ROM32_INSTR_PT(139) + OR ROM32_INSTR_PT(152) OR ROM32_INSTR_PT(167) + OR ROM32_INSTR_PT(178) OR ROM32_INSTR_PT(188) + OR ROM32_INSTR_PT(191) OR ROM32_INSTR_PT(212) + OR ROM32_INSTR_PT(217) OR ROM32_INSTR_PT(236) + OR ROM32_INSTR_PT(295) OR ROM32_INSTR_PT(317) + OR ROM32_INSTR_PT(327) OR ROM32_INSTR_PT(328) + OR ROM32_INSTR_PT(330) OR ROM32_INSTR_PT(333) + OR ROM32_INSTR_PT(336) OR ROM32_INSTR_PT(341) + OR ROM32_INSTR_PT(344) OR ROM32_INSTR_PT(346) + OR ROM32_INSTR_PT(354) OR ROM32_INSTR_PT(356) + OR ROM32_INSTR_PT(369) OR ROM32_INSTR_PT(375) + OR ROM32_INSTR_PT(381) OR ROM32_INSTR_PT(393) + OR ROM32_INSTR_PT(410) OR ROM32_INSTR_PT(415) + OR ROM32_INSTR_PT(429) OR ROM32_INSTR_PT(437) + OR ROM32_INSTR_PT(438) OR ROM32_INSTR_PT(447) + OR ROM32_INSTR_PT(451) OR ROM32_INSTR_PT(457) + OR ROM32_INSTR_PT(470) OR ROM32_INSTR_PT(493) + OR ROM32_INSTR_PT(518) OR ROM32_INSTR_PT(526) + OR ROM32_INSTR_PT(530) OR ROM32_INSTR_PT(579) + OR ROM32_INSTR_PT(587) OR ROM32_INSTR_PT(594) + OR ROM32_INSTR_PT(599) OR ROM32_INSTR_PT(624) + OR ROM32_INSTR_PT(627) OR ROM32_INSTR_PT(628) + OR ROM32_INSTR_PT(651) OR ROM32_INSTR_PT(656) + OR ROM32_INSTR_PT(692) OR ROM32_INSTR_PT(706) + OR ROM32_INSTR_PT(710) OR ROM32_INSTR_PT(714) + OR ROM32_INSTR_PT(721) OR ROM32_INSTR_PT(722) + OR ROM32_INSTR_PT(723) OR ROM32_INSTR_PT(730) + OR ROM32_INSTR_PT(735) OR ROM32_INSTR_PT(737) + OR ROM32_INSTR_PT(739) OR ROM32_INSTR_PT(742) + OR ROM32_INSTR_PT(746) OR ROM32_INSTR_PT(749) + OR ROM32_INSTR_PT(756) OR ROM32_INSTR_PT(760) + OR ROM32_INSTR_PT(764) OR ROM32_INSTR_PT(767) + OR ROM32_INSTR_PT(770) OR ROM32_INSTR_PT(779) + OR ROM32_INSTR_PT(789) OR ROM32_INSTR_PT(791) + OR ROM32_INSTR_PT(812) OR ROM32_INSTR_PT(819) + OR ROM32_INSTR_PT(822) OR ROM32_INSTR_PT(824) + OR ROM32_INSTR_PT(835) OR ROM32_INSTR_PT(841) + OR ROM32_INSTR_PT(842) OR ROM32_INSTR_PT(850) + OR ROM32_INSTR_PT(853) OR ROM32_INSTR_PT(858) + OR ROM32_INSTR_PT(863) OR ROM32_INSTR_PT(865) + OR ROM32_INSTR_PT(867) OR ROM32_INSTR_PT(868) + OR ROM32_INSTR_PT(876) OR ROM32_INSTR_PT(878) + OR ROM32_INSTR_PT(885)); +MQQ1897:EXTS3 <= + (ROM32_INSTR_PT(47) OR ROM32_INSTR_PT(58) + OR ROM32_INSTR_PT(126) OR ROM32_INSTR_PT(133) + OR ROM32_INSTR_PT(135) OR ROM32_INSTR_PT(168) + OR ROM32_INSTR_PT(190) OR ROM32_INSTR_PT(226) + OR ROM32_INSTR_PT(263) OR ROM32_INSTR_PT(293) + OR ROM32_INSTR_PT(318) OR ROM32_INSTR_PT(333) + OR ROM32_INSTR_PT(346) OR ROM32_INSTR_PT(381) + OR ROM32_INSTR_PT(397) OR ROM32_INSTR_PT(409) + OR ROM32_INSTR_PT(467) OR ROM32_INSTR_PT(487) + OR ROM32_INSTR_PT(526) OR ROM32_INSTR_PT(623) + OR ROM32_INSTR_PT(692) OR ROM32_INSTR_PT(707) + OR ROM32_INSTR_PT(710) OR ROM32_INSTR_PT(717) + OR ROM32_INSTR_PT(730) OR ROM32_INSTR_PT(771) + OR ROM32_INSTR_PT(792) OR ROM32_INSTR_PT(804) + OR ROM32_INSTR_PT(826) OR ROM32_INSTR_PT(837) + OR ROM32_INSTR_PT(866) OR ROM32_INSTR_PT(887) + ); +MQQ1898:SEL0_5 <= + (ROM32_INSTR_PT(651) OR ROM32_INSTR_PT(714) + ); +MQQ1899:SEL6_10(0) <= + (ROM32_INSTR_PT(40) OR ROM32_INSTR_PT(72) + OR ROM32_INSTR_PT(83) OR ROM32_INSTR_PT(94) + OR ROM32_INSTR_PT(108) OR ROM32_INSTR_PT(201) + OR ROM32_INSTR_PT(212) OR ROM32_INSTR_PT(266) + OR ROM32_INSTR_PT(384) OR ROM32_INSTR_PT(438) + OR ROM32_INSTR_PT(440) OR ROM32_INSTR_PT(450) + OR ROM32_INSTR_PT(512) OR ROM32_INSTR_PT(518) + OR ROM32_INSTR_PT(528) OR ROM32_INSTR_PT(529) + OR ROM32_INSTR_PT(536) OR ROM32_INSTR_PT(541) + OR ROM32_INSTR_PT(548) OR ROM32_INSTR_PT(559) + OR ROM32_INSTR_PT(566) OR ROM32_INSTR_PT(572) + OR ROM32_INSTR_PT(580) OR ROM32_INSTR_PT(599) + OR ROM32_INSTR_PT(601) OR ROM32_INSTR_PT(618) + OR ROM32_INSTR_PT(661) OR ROM32_INSTR_PT(693) + OR ROM32_INSTR_PT(702) OR ROM32_INSTR_PT(784) + OR ROM32_INSTR_PT(818) OR ROM32_INSTR_PT(853) + ); +MQQ1900:SEL6_10(1) <= + (ROM32_INSTR_PT(1) OR ROM32_INSTR_PT(2) + OR ROM32_INSTR_PT(40) OR ROM32_INSTR_PT(54) + OR ROM32_INSTR_PT(71) OR ROM32_INSTR_PT(72) + OR ROM32_INSTR_PT(80) OR ROM32_INSTR_PT(83) + OR ROM32_INSTR_PT(94) OR ROM32_INSTR_PT(108) + OR ROM32_INSTR_PT(121) OR ROM32_INSTR_PT(178) + OR ROM32_INSTR_PT(182) OR ROM32_INSTR_PT(262) + OR ROM32_INSTR_PT(266) OR ROM32_INSTR_PT(284) + OR ROM32_INSTR_PT(334) OR ROM32_INSTR_PT(344) + OR ROM32_INSTR_PT(346) OR ROM32_INSTR_PT(347) + OR ROM32_INSTR_PT(351) OR ROM32_INSTR_PT(356) + OR ROM32_INSTR_PT(375) OR ROM32_INSTR_PT(403) + OR ROM32_INSTR_PT(427) OR ROM32_INSTR_PT(432) + OR ROM32_INSTR_PT(455) OR ROM32_INSTR_PT(461) + OR ROM32_INSTR_PT(483) OR ROM32_INSTR_PT(485) + OR ROM32_INSTR_PT(529) OR ROM32_INSTR_PT(530) + OR ROM32_INSTR_PT(536) OR ROM32_INSTR_PT(539) + OR ROM32_INSTR_PT(579) OR ROM32_INSTR_PT(592) + OR ROM32_INSTR_PT(651) OR ROM32_INSTR_PT(658) + OR ROM32_INSTR_PT(691) OR ROM32_INSTR_PT(692) + OR ROM32_INSTR_PT(703) OR ROM32_INSTR_PT(710) + OR ROM32_INSTR_PT(714) OR ROM32_INSTR_PT(716) + OR ROM32_INSTR_PT(723) OR ROM32_INSTR_PT(724) + OR ROM32_INSTR_PT(732) OR ROM32_INSTR_PT(856) + OR ROM32_INSTR_PT(862) OR ROM32_INSTR_PT(870) + ); +MQQ1901:SEL11_15(0) <= + (ROM32_INSTR_PT(36) OR ROM32_INSTR_PT(133) + OR ROM32_INSTR_PT(193) OR ROM32_INSTR_PT(231) + OR ROM32_INSTR_PT(246) OR ROM32_INSTR_PT(286) + OR ROM32_INSTR_PT(369) OR ROM32_INSTR_PT(381) + OR ROM32_INSTR_PT(434) OR ROM32_INSTR_PT(444) + OR ROM32_INSTR_PT(462) OR ROM32_INSTR_PT(589) + OR ROM32_INSTR_PT(663) OR ROM32_INSTR_PT(733) + OR ROM32_INSTR_PT(792) OR ROM32_INSTR_PT(825) + ); +MQQ1902:SEL11_15(1) <= + (ROM32_INSTR_PT(22) OR ROM32_INSTR_PT(25) + OR ROM32_INSTR_PT(36) OR ROM32_INSTR_PT(44) + OR ROM32_INSTR_PT(48) OR ROM32_INSTR_PT(61) + OR ROM32_INSTR_PT(64) OR ROM32_INSTR_PT(65) + OR ROM32_INSTR_PT(69) OR ROM32_INSTR_PT(86) + OR ROM32_INSTR_PT(95) OR ROM32_INSTR_PT(106) + OR ROM32_INSTR_PT(116) OR ROM32_INSTR_PT(129) + OR ROM32_INSTR_PT(131) OR ROM32_INSTR_PT(139) + OR ROM32_INSTR_PT(140) OR ROM32_INSTR_PT(151) + OR ROM32_INSTR_PT(160) OR ROM32_INSTR_PT(164) + OR ROM32_INSTR_PT(188) OR ROM32_INSTR_PT(190) + OR ROM32_INSTR_PT(193) OR ROM32_INSTR_PT(201) + OR ROM32_INSTR_PT(221) OR ROM32_INSTR_PT(231) + OR ROM32_INSTR_PT(234) OR ROM32_INSTR_PT(247) + OR ROM32_INSTR_PT(251) OR ROM32_INSTR_PT(265) + OR ROM32_INSTR_PT(281) OR ROM32_INSTR_PT(286) + OR ROM32_INSTR_PT(300) OR ROM32_INSTR_PT(351) + OR ROM32_INSTR_PT(354) OR ROM32_INSTR_PT(369) + OR ROM32_INSTR_PT(384) OR ROM32_INSTR_PT(393) + OR ROM32_INSTR_PT(415) OR ROM32_INSTR_PT(420) + OR ROM32_INSTR_PT(429) OR ROM32_INSTR_PT(434) + OR ROM32_INSTR_PT(437) OR ROM32_INSTR_PT(440) + OR ROM32_INSTR_PT(450) OR ROM32_INSTR_PT(451) + OR ROM32_INSTR_PT(462) OR ROM32_INSTR_PT(518) + OR ROM32_INSTR_PT(523) OR ROM32_INSTR_PT(528) + OR ROM32_INSTR_PT(545) OR ROM32_INSTR_PT(548) + OR ROM32_INSTR_PT(559) OR ROM32_INSTR_PT(572) + OR ROM32_INSTR_PT(587) OR ROM32_INSTR_PT(589) + OR ROM32_INSTR_PT(591) OR ROM32_INSTR_PT(601) + OR ROM32_INSTR_PT(618) OR ROM32_INSTR_PT(624) + OR ROM32_INSTR_PT(631) OR ROM32_INSTR_PT(663) + OR ROM32_INSTR_PT(665) OR ROM32_INSTR_PT(693) + OR ROM32_INSTR_PT(702) OR ROM32_INSTR_PT(713) + OR ROM32_INSTR_PT(714) OR ROM32_INSTR_PT(727) + OR ROM32_INSTR_PT(780) OR ROM32_INSTR_PT(784) + OR ROM32_INSTR_PT(801) OR ROM32_INSTR_PT(812) + OR ROM32_INSTR_PT(819) OR ROM32_INSTR_PT(824) + OR ROM32_INSTR_PT(839) OR ROM32_INSTR_PT(843) + OR ROM32_INSTR_PT(847) OR ROM32_INSTR_PT(878) + ); +MQQ1903:SEL16_20(0) <= + (ROM32_INSTR_PT(5) OR ROM32_INSTR_PT(133) + OR ROM32_INSTR_PT(194) OR ROM32_INSTR_PT(254) + OR ROM32_INSTR_PT(256) OR ROM32_INSTR_PT(353) + OR ROM32_INSTR_PT(444) OR ROM32_INSTR_PT(533) + OR ROM32_INSTR_PT(792) OR ROM32_INSTR_PT(825) + ); +MQQ1904:SEL16_20(1) <= + (ROM32_INSTR_PT(3) OR ROM32_INSTR_PT(11) + OR ROM32_INSTR_PT(15) OR ROM32_INSTR_PT(28) + OR ROM32_INSTR_PT(40) OR ROM32_INSTR_PT(46) + OR ROM32_INSTR_PT(48) OR ROM32_INSTR_PT(72) + OR ROM32_INSTR_PT(76) OR ROM32_INSTR_PT(83) + OR ROM32_INSTR_PT(88) OR ROM32_INSTR_PT(94) + OR ROM32_INSTR_PT(100) OR ROM32_INSTR_PT(108) + OR ROM32_INSTR_PT(126) OR ROM32_INSTR_PT(131) + OR ROM32_INSTR_PT(133) OR ROM32_INSTR_PT(135) + OR ROM32_INSTR_PT(140) OR ROM32_INSTR_PT(161) + OR ROM32_INSTR_PT(164) OR ROM32_INSTR_PT(201) + OR ROM32_INSTR_PT(204) OR ROM32_INSTR_PT(226) + OR ROM32_INSTR_PT(248) OR ROM32_INSTR_PT(265) + OR ROM32_INSTR_PT(266) OR ROM32_INSTR_PT(277) + OR ROM32_INSTR_PT(293) OR ROM32_INSTR_PT(298) + OR ROM32_INSTR_PT(318) OR ROM32_INSTR_PT(320) + OR ROM32_INSTR_PT(334) OR ROM32_INSTR_PT(351) + OR ROM32_INSTR_PT(353) OR ROM32_INSTR_PT(359) + OR ROM32_INSTR_PT(384) OR ROM32_INSTR_PT(397) + OR ROM32_INSTR_PT(409) OR ROM32_INSTR_PT(420) + OR ROM32_INSTR_PT(443) OR ROM32_INSTR_PT(444) + OR ROM32_INSTR_PT(450) OR ROM32_INSTR_PT(467) + OR ROM32_INSTR_PT(487) OR ROM32_INSTR_PT(495) + OR ROM32_INSTR_PT(510) OR ROM32_INSTR_PT(523) + OR ROM32_INSTR_PT(528) OR ROM32_INSTR_PT(529) + OR ROM32_INSTR_PT(540) OR ROM32_INSTR_PT(548) + OR ROM32_INSTR_PT(559) OR ROM32_INSTR_PT(560) + OR ROM32_INSTR_PT(566) OR ROM32_INSTR_PT(571) + OR ROM32_INSTR_PT(572) OR ROM32_INSTR_PT(600) + OR ROM32_INSTR_PT(601) OR ROM32_INSTR_PT(609) + OR ROM32_INSTR_PT(618) OR ROM32_INSTR_PT(631) + OR ROM32_INSTR_PT(649) OR ROM32_INSTR_PT(661) + OR ROM32_INSTR_PT(693) OR ROM32_INSTR_PT(702) + OR ROM32_INSTR_PT(713) OR ROM32_INSTR_PT(766) + OR ROM32_INSTR_PT(784) OR ROM32_INSTR_PT(792) + OR ROM32_INSTR_PT(825) OR ROM32_INSTR_PT(836) + ); +MQQ1905:SEL21_25(0) <= + (ROM32_INSTR_PT(197)); +MQQ1906:SEL21_25(1) <= + (ROM32_INSTR_PT(15) OR ROM32_INSTR_PT(28) + OR ROM32_INSTR_PT(46) OR ROM32_INSTR_PT(48) + OR ROM32_INSTR_PT(65) OR ROM32_INSTR_PT(76) + OR ROM32_INSTR_PT(88) OR ROM32_INSTR_PT(140) + OR ROM32_INSTR_PT(201) OR ROM32_INSTR_PT(226) + OR ROM32_INSTR_PT(265) OR ROM32_INSTR_PT(320) + OR ROM32_INSTR_PT(351) OR ROM32_INSTR_PT(359) + OR ROM32_INSTR_PT(384) OR ROM32_INSTR_PT(420) + OR ROM32_INSTR_PT(450) OR ROM32_INSTR_PT(467) + OR ROM32_INSTR_PT(512) OR ROM32_INSTR_PT(528) + OR ROM32_INSTR_PT(540) OR ROM32_INSTR_PT(548) + OR ROM32_INSTR_PT(559) OR ROM32_INSTR_PT(571) + OR ROM32_INSTR_PT(572) OR ROM32_INSTR_PT(631) + OR ROM32_INSTR_PT(651) OR ROM32_INSTR_PT(702) + OR ROM32_INSTR_PT(714) OR ROM32_INSTR_PT(727) + OR ROM32_INSTR_PT(784)); +MQQ1907:SEL26_30 <= + (ROM32_INSTR_PT(15) OR ROM32_INSTR_PT(28) + OR ROM32_INSTR_PT(46) OR ROM32_INSTR_PT(48) + OR ROM32_INSTR_PT(65) OR ROM32_INSTR_PT(76) + OR ROM32_INSTR_PT(88) OR ROM32_INSTR_PT(140) + OR ROM32_INSTR_PT(201) OR ROM32_INSTR_PT(226) + OR ROM32_INSTR_PT(265) OR ROM32_INSTR_PT(320) + OR ROM32_INSTR_PT(351) OR ROM32_INSTR_PT(359) + OR ROM32_INSTR_PT(384) OR ROM32_INSTR_PT(420) + OR ROM32_INSTR_PT(450) OR ROM32_INSTR_PT(467) + OR ROM32_INSTR_PT(512) OR ROM32_INSTR_PT(528) + OR ROM32_INSTR_PT(540) OR ROM32_INSTR_PT(548) + OR ROM32_INSTR_PT(559) OR ROM32_INSTR_PT(571) + OR ROM32_INSTR_PT(572) OR ROM32_INSTR_PT(631) + OR ROM32_INSTR_PT(651) OR ROM32_INSTR_PT(702) + OR ROM32_INSTR_PT(714) OR ROM32_INSTR_PT(727) + OR ROM32_INSTR_PT(784)); +MQQ1908:SEL31 <= + (ROM32_INSTR_PT(15) OR ROM32_INSTR_PT(28) + OR ROM32_INSTR_PT(61) OR ROM32_INSTR_PT(65) + OR ROM32_INSTR_PT(76) OR ROM32_INSTR_PT(88) + OR ROM32_INSTR_PT(140) OR ROM32_INSTR_PT(201) + OR ROM32_INSTR_PT(265) OR ROM32_INSTR_PT(320) + OR ROM32_INSTR_PT(346) OR ROM32_INSTR_PT(351) + OR ROM32_INSTR_PT(356) OR ROM32_INSTR_PT(359) + OR ROM32_INSTR_PT(384) OR ROM32_INSTR_PT(420) + OR ROM32_INSTR_PT(450) OR ROM32_INSTR_PT(467) + OR ROM32_INSTR_PT(540) OR ROM32_INSTR_PT(541) + OR ROM32_INSTR_PT(559) OR ROM32_INSTR_PT(560) + OR ROM32_INSTR_PT(572) OR ROM32_INSTR_PT(631) + OR ROM32_INSTR_PT(651) OR ROM32_INSTR_PT(692) + OR ROM32_INSTR_PT(702) OR ROM32_INSTR_PT(710) + OR ROM32_INSTR_PT(714) OR ROM32_INSTR_PT(784) + OR ROM32_INSTR_PT(818)); +MQQ1909:CR_BF2FXM <= + (ROM32_INSTR_PT(713)); +MQQ1910:SKIP_COND <= + (ROM32_INSTR_PT(21) OR ROM32_INSTR_PT(32) + OR ROM32_INSTR_PT(82) OR ROM32_INSTR_PT(89) + OR ROM32_INSTR_PT(91) OR ROM32_INSTR_PT(127) + OR ROM32_INSTR_PT(217) OR ROM32_INSTR_PT(295) + OR ROM32_INSTR_PT(327) OR ROM32_INSTR_PT(328) + OR ROM32_INSTR_PT(341) OR ROM32_INSTR_PT(366) + OR ROM32_INSTR_PT(485) OR ROM32_INSTR_PT(662) + OR ROM32_INSTR_PT(667) OR ROM32_INSTR_PT(676) + OR ROM32_INSTR_PT(682) OR ROM32_INSTR_PT(722) + OR ROM32_INSTR_PT(736) OR ROM32_INSTR_PT(737) + OR ROM32_INSTR_PT(738) OR ROM32_INSTR_PT(739) + OR ROM32_INSTR_PT(740) OR ROM32_INSTR_PT(742) + OR ROM32_INSTR_PT(747) OR ROM32_INSTR_PT(748) + OR ROM32_INSTR_PT(749) OR ROM32_INSTR_PT(758) + OR ROM32_INSTR_PT(770) OR ROM32_INSTR_PT(775) + OR ROM32_INSTR_PT(776) OR ROM32_INSTR_PT(777) + OR ROM32_INSTR_PT(786) OR ROM32_INSTR_PT(788) + OR ROM32_INSTR_PT(789) OR ROM32_INSTR_PT(800) + OR ROM32_INSTR_PT(811) OR ROM32_INSTR_PT(814) + OR ROM32_INSTR_PT(815) OR ROM32_INSTR_PT(816) + OR ROM32_INSTR_PT(822) OR ROM32_INSTR_PT(842) + OR ROM32_INSTR_PT(858) OR ROM32_INSTR_PT(865) + ); +MQQ1911:SKIP_ZERO <= + (ROM32_INSTR_PT(318) OR ROM32_INSTR_PT(349) + OR ROM32_INSTR_PT(432) OR ROM32_INSTR_PT(457) + OR ROM32_INSTR_PT(483) OR ROM32_INSTR_PT(671) + OR ROM32_INSTR_PT(712)); +MQQ1912:LOOP_ADDR(0) <= + (ROM32_INSTR_PT(19) OR ROM32_INSTR_PT(36) + OR ROM32_INSTR_PT(58) OR ROM32_INSTR_PT(315) + OR ROM32_INSTR_PT(316) OR ROM32_INSTR_PT(349) + OR ROM32_INSTR_PT(369) OR ROM32_INSTR_PT(457) + OR ROM32_INSTR_PT(623) OR ROM32_INSTR_PT(627) + OR ROM32_INSTR_PT(656) OR ROM32_INSTR_PT(671) + OR ROM32_INSTR_PT(712) OR ROM32_INSTR_PT(721) + OR ROM32_INSTR_PT(730) OR ROM32_INSTR_PT(742) + OR ROM32_INSTR_PT(760) OR ROM32_INSTR_PT(771) + OR ROM32_INSTR_PT(777) OR ROM32_INSTR_PT(798) + OR ROM32_INSTR_PT(837) OR ROM32_INSTR_PT(863) + OR ROM32_INSTR_PT(865)); +MQQ1913:LOOP_ADDR(1) <= + (ROM32_INSTR_PT(315) OR ROM32_INSTR_PT(525) + OR ROM32_INSTR_PT(623) OR ROM32_INSTR_PT(627) + OR ROM32_INSTR_PT(656) OR ROM32_INSTR_PT(712) + OR ROM32_INSTR_PT(721) OR ROM32_INSTR_PT(730) + OR ROM32_INSTR_PT(742) OR ROM32_INSTR_PT(777) + OR ROM32_INSTR_PT(837) OR ROM32_INSTR_PT(858) + OR ROM32_INSTR_PT(865)); +MQQ1914:LOOP_ADDR(2) <= + (ROM32_INSTR_PT(58) OR ROM32_INSTR_PT(457) + OR ROM32_INSTR_PT(717) OR ROM32_INSTR_PT(740) + OR ROM32_INSTR_PT(747) OR ROM32_INSTR_PT(887) + ); +MQQ1915:LOOP_ADDR(3) <= + (ROM32_INSTR_PT(19) OR ROM32_INSTR_PT(58) + OR ROM32_INSTR_PT(136) OR ROM32_INSTR_PT(316) + OR ROM32_INSTR_PT(414) OR ROM32_INSTR_PT(457) + OR ROM32_INSTR_PT(623) OR ROM32_INSTR_PT(706) + OR ROM32_INSTR_PT(722) OR ROM32_INSTR_PT(730) + OR ROM32_INSTR_PT(756) OR ROM32_INSTR_PT(760) + OR ROM32_INSTR_PT(771) OR ROM32_INSTR_PT(798) + OR ROM32_INSTR_PT(837) OR ROM32_INSTR_PT(864) + OR ROM32_INSTR_PT(865)); +MQQ1916:LOOP_ADDR(4) <= + (ROM32_INSTR_PT(19) OR ROM32_INSTR_PT(36) + OR ROM32_INSTR_PT(58) OR ROM32_INSTR_PT(136) + OR ROM32_INSTR_PT(315) OR ROM32_INSTR_PT(349) + OR ROM32_INSTR_PT(369) OR ROM32_INSTR_PT(410) + OR ROM32_INSTR_PT(457) OR ROM32_INSTR_PT(470) + OR ROM32_INSTR_PT(717) OR ROM32_INSTR_PT(740) + OR ROM32_INSTR_PT(742) OR ROM32_INSTR_PT(747) + OR ROM32_INSTR_PT(777) OR ROM32_INSTR_PT(837) + OR ROM32_INSTR_PT(863) OR ROM32_INSTR_PT(865) + ); +MQQ1917:LOOP_ADDR(5) <= + (ROM32_INSTR_PT(36) OR ROM32_INSTR_PT(58) + OR ROM32_INSTR_PT(315) OR ROM32_INSTR_PT(623) + OR ROM32_INSTR_PT(656) OR ROM32_INSTR_PT(671) + OR ROM32_INSTR_PT(721) OR ROM32_INSTR_PT(722) + OR ROM32_INSTR_PT(735) OR ROM32_INSTR_PT(756) + OR ROM32_INSTR_PT(764) OR ROM32_INSTR_PT(771) + OR ROM32_INSTR_PT(798) OR ROM32_INSTR_PT(863) + ); +MQQ1918:LOOP_ADDR(6) <= + (ROM32_INSTR_PT(36) OR ROM32_INSTR_PT(136) + OR ROM32_INSTR_PT(315) OR ROM32_INSTR_PT(316) + OR ROM32_INSTR_PT(369) OR ROM32_INSTR_PT(380) + OR ROM32_INSTR_PT(457) OR ROM32_INSTR_PT(470) + OR ROM32_INSTR_PT(623) OR ROM32_INSTR_PT(671) + OR ROM32_INSTR_PT(721) OR ROM32_INSTR_PT(722) + OR ROM32_INSTR_PT(740) OR ROM32_INSTR_PT(742) + OR ROM32_INSTR_PT(756) OR ROM32_INSTR_PT(760) + OR ROM32_INSTR_PT(837) OR ROM32_INSTR_PT(858) + OR ROM32_INSTR_PT(887)); +MQQ1919:LOOP_ADDR(7) <= + (ROM32_INSTR_PT(19) OR ROM32_INSTR_PT(36) + OR ROM32_INSTR_PT(58) OR ROM32_INSTR_PT(316) + OR ROM32_INSTR_PT(349) OR ROM32_INSTR_PT(380) + OR ROM32_INSTR_PT(410) OR ROM32_INSTR_PT(414) + OR ROM32_INSTR_PT(623) OR ROM32_INSTR_PT(627) + OR ROM32_INSTR_PT(721) OR ROM32_INSTR_PT(722) + OR ROM32_INSTR_PT(730) OR ROM32_INSTR_PT(740) + OR ROM32_INSTR_PT(742) OR ROM32_INSTR_PT(765) + OR ROM32_INSTR_PT(771) OR ROM32_INSTR_PT(826) + OR ROM32_INSTR_PT(865)); +MQQ1920:LOOP_ADDR(8) <= + (ROM32_INSTR_PT(136) OR ROM32_INSTR_PT(410) + OR ROM32_INSTR_PT(414) OR ROM32_INSTR_PT(457) + OR ROM32_INSTR_PT(470) OR ROM32_INSTR_PT(488) + OR ROM32_INSTR_PT(706) OR ROM32_INSTR_PT(722) + OR ROM32_INSTR_PT(730) OR ROM32_INSTR_PT(740) + OR ROM32_INSTR_PT(742) OR ROM32_INSTR_PT(747) + OR ROM32_INSTR_PT(756) OR ROM32_INSTR_PT(863) + OR ROM32_INSTR_PT(887)); +MQQ1921:LOOP_ADDR(9) <= + (ROM32_INSTR_PT(19) OR ROM32_INSTR_PT(36) + OR ROM32_INSTR_PT(58) OR ROM32_INSTR_PT(191) + OR ROM32_INSTR_PT(316) OR ROM32_INSTR_PT(349) + OR ROM32_INSTR_PT(369) OR ROM32_INSTR_PT(525) + OR ROM32_INSTR_PT(623) OR ROM32_INSTR_PT(671) + OR ROM32_INSTR_PT(717) OR ROM32_INSTR_PT(721) + OR ROM32_INSTR_PT(760) OR ROM32_INSTR_PT(771) + OR ROM32_INSTR_PT(777) OR ROM32_INSTR_PT(837) + OR ROM32_INSTR_PT(887)); +MQQ1922:LOOP_INIT(0) <= + (ROM32_INSTR_PT(168) OR ROM32_INSTR_PT(236) + OR ROM32_INSTR_PT(315) OR ROM32_INSTR_PT(366) + OR ROM32_INSTR_PT(397) OR ROM32_INSTR_PT(686) + OR ROM32_INSTR_PT(717) OR ROM32_INSTR_PT(776) + OR ROM32_INSTR_PT(788) OR ROM32_INSTR_PT(811) + OR ROM32_INSTR_PT(816) OR ROM32_INSTR_PT(864) + ); +MQQ1923:LOOP_INIT(1) <= + (ROM32_INSTR_PT(893)); +MQQ1924:LOOP_INIT(2) <= + (ROM32_INSTR_PT(168) OR ROM32_INSTR_PT(776) + OR ROM32_INSTR_PT(811)); +MQQ1925:EP <= + (ROM32_INSTR_PT(44) OR ROM32_INSTR_PT(61) + OR ROM32_INSTR_PT(116) OR ROM32_INSTR_PT(135) + OR ROM32_INSTR_PT(277) OR ROM32_INSTR_PT(293) + OR ROM32_INSTR_PT(354) OR ROM32_INSTR_PT(393) + OR ROM32_INSTR_PT(397) OR ROM32_INSTR_PT(429) + OR ROM32_INSTR_PT(437) OR ROM32_INSTR_PT(443) + OR ROM32_INSTR_PT(523) OR ROM32_INSTR_PT(560) + ); + +end generate; +rom_addr_d <= rom_addr; +rom_data <= template & ucode_end & ucode_end_early & loop_begin & loop_end & count_src & extRT & extS1 & extS2 & extS3 & + sel0_5 & sel6_10 & sel11_15 & sel16_20 & sel21_25 & sel26_30 & sel31 & cr_bf2fxm & skip_cond & skip_zero & loop_addr & loop_init & ep; +----------------------------------------------------------------------- +-- Latches +----------------------------------------------------------------------- +rom_addr_latch: tri_rlmreg_p + generic map (width => rom_addr_l2'length, init => 0, needs_sreset => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rom_act, + thold_b => pc_iu_func_sl_thold_0_b, + sg => pc_iu_sg_0, + forcee => forcee, + delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, + mpw2_b => mpw2_b, + d_mode => d_mode, + scin => siv(rom_addr_offset to rom_addr_offset + rom_addr_l2'length-1), + scout => sov(rom_addr_offset to rom_addr_offset + rom_addr_l2'length-1), + din => rom_addr_d, + dout => rom_addr_l2); +----------------------------------------------------------------------- +-- Scan +----------------------------------------------------------------------- +siv(0 TO scan_right) <= sov(1 to scan_right) & scan_in; +scan_out <= sov(0); +END IUQ_UC_ROM; diff --git a/rel/src/vhdl/work/mmq.vhdl b/rel/src/vhdl/work/mmq.vhdl new file mode 100644 index 0000000..1c8f6cd --- /dev/null +++ b/rel/src/vhdl/work/mmq.vhdl @@ -0,0 +1,4403 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; +use ieee.std_logic_1164.all; +library ibm; +use ibm.std_ulogic_unsigned.all; +use ibm.std_ulogic_function_support.all; +library support; +use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity mmq is + generic(thdid_width : integer := 4; + ttype_width : integer := 4; + state_width : integer := 4; + pid_width : integer := 14; + pid_width_erat : integer := 8; + lpid_width : integer := 8; + class_width : integer := 2; + extclass_width : integer := 2; + tlbsel_width : integer := 2; + epn_width : integer := 52; + req_epn_width : integer := 52; + vpn_width : integer := 61; + erat_cam_data_width : integer := 75; + erat_ary_data_width : integer := 73; + erat_rel_data_width : integer := 132; + ws_width : integer := 2; + rs_is_width : integer := 9; + ra_entry_width : integer := 12; + rs_data_width : integer := 64; + data_out_width : integer := 64; + error_width : integer := 3; + tlb_num_entry : natural := 512; + tlb_num_entry_log2 : natural := 9; + tlb_ways : natural := 4; + tlb_addr_width : natural := 7; + tlb_way_width : natural := 168; + tlb_word_width : natural := 84; + tlb_seq_width : integer := 6; + inv_seq_width : integer := 6; + por_seq_width : integer := 3; + watermark_width : integer := 4; + eptr_width : integer := 4; + lru_width : integer := 16; + mmucr0_width : integer := 20; + mmucr1_width : integer := 32; + mmucr2_width : integer := 32; + mmucr3_width : integer := 15; + spr_ctl_width : integer := 3; + spr_etid_width : integer := 2; + spr_addr_width : integer := 10; + spr_data_width : integer := 64; + debug_trace_width : integer := 88; + debug_event_width : integer := 16; + real_addr_width : integer := 42; + rpn_width : integer := 30; + pte_width : integer := 64; + lrat_num_entry_log2 : integer := 3; + tlb_tag_width : natural := 110; + mmq_spr_cswitch_0to3 : integer := 0; + mmq_tlb_cmp_cswitch_0to7 : integer := 0; + expand_tlb_type : integer := 2; + expand_type : integer := 2 ); +port( + vcs : inout power_logic; + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + +tc_ac_ccflush_dc : in std_ulogic; +tc_ac_scan_dis_dc_b : in std_ulogic; +tc_ac_scan_diag_dc : in std_ulogic; +tc_ac_lbist_en_dc : in std_ulogic; +pc_mm_gptr_sl_thold_3 : in std_ulogic; +pc_mm_time_sl_thold_3 : in std_ulogic; +pc_mm_repr_sl_thold_3 : in std_ulogic; +pc_mm_abst_sl_thold_3 : in std_ulogic; +pc_mm_abst_slp_sl_thold_3 : in std_ulogic; +pc_mm_func_sl_thold_3 : in std_ulogic_vector(0 to 1); +pc_mm_func_slp_sl_thold_3 : in std_ulogic_vector(0 to 1); +pc_mm_cfg_sl_thold_3 : in std_ulogic; +pc_mm_cfg_slp_sl_thold_3 : in std_ulogic; +pc_mm_func_nsl_thold_3 : in std_ulogic; +pc_mm_func_slp_nsl_thold_3 : in std_ulogic; +pc_mm_ary_nsl_thold_3 : in std_ulogic; +pc_mm_ary_slp_nsl_thold_3 : in std_ulogic; +pc_mm_sg_3 : in std_ulogic_vector(0 to 1); +pc_mm_fce_3 : in std_ulogic; +debug_bus_out : out std_ulogic_vector(0 to 87); +debug_bus_out_int : out std_ulogic_vector(0 to 7); +trace_triggers_out : out std_ulogic_vector(0 to 11); +debug_bus_in : in std_ulogic_vector(0 to 87); +trace_triggers_in : in std_ulogic_vector(0 to 11); +pc_mm_debug_mux1_ctrls : in std_ulogic_vector(0 to 15); +pc_mm_trace_bus_enable : in std_ulogic; +pc_mm_event_mux_ctrls : in std_ulogic_vector(0 to 39); +pc_mm_event_count_mode : in std_ulogic_vector(0 to 2); +rp_mm_event_bus_enable_q : in std_ulogic; +mm_pc_event_data : out std_ulogic_vector(0 to 7); +pc_mm_abist_dcomp_g6t_2r : in std_ulogic_vector(0 to 3); +pc_mm_abist_di_0 : in std_ulogic_vector(0 to 3); +pc_mm_abist_di_g6t_2r : in std_ulogic_vector(0 to 3); +pc_mm_abist_ena_dc : in std_ulogic; +pc_mm_abist_g6t_r_wb : in std_ulogic; +pc_mm_abist_g8t1p_renb_0 : in std_ulogic; +pc_mm_abist_g8t_bw_0 : in std_ulogic; +pc_mm_abist_g8t_bw_1 : in std_ulogic; +pc_mm_abist_g8t_dcomp : in std_ulogic_vector(0 to 3); +pc_mm_abist_g8t_wenb : in std_ulogic; +pc_mm_abist_raddr_0 : in std_ulogic_vector(0 to 9); +pc_mm_abist_raw_dc_b : in std_ulogic; +pc_mm_abist_waddr_0 : in std_ulogic_vector(0 to 9); +pc_mm_abist_wl128_comp_ena : in std_ulogic; +pc_mm_bolt_sl_thold_3 : in std_ulogic; +pc_mm_bo_enable_3 : in std_ulogic; +pc_mm_bo_reset : in std_ulogic; +pc_mm_bo_unload : in std_ulogic; +pc_mm_bo_repair : in std_ulogic; +pc_mm_bo_shdata : in std_ulogic; +pc_mm_bo_select : in std_ulogic_vector(0 to 4); +mm_pc_bo_fail : out std_ulogic_vector(0 to 4); +mm_pc_bo_diagout : out std_ulogic_vector(0 to 4); +iu_mm_ierat_req : in std_ulogic; +iu_mm_ierat_epn : in std_ulogic_vector(0 to 51); +iu_mm_ierat_thdid : in std_ulogic_vector(0 to thdid_width-1); +iu_mm_ierat_state : in std_ulogic_vector(0 to state_width-1); +iu_mm_ierat_tid : in std_ulogic_vector(0 to pid_width-1); +iu_mm_ierat_flush : in std_ulogic_vector(0 to thdid_width-1); +mm_iu_ierat_rel_val : out std_ulogic_vector(0 to 4); +mm_iu_ierat_rel_data : out std_ulogic_vector(0 to erat_rel_data_width-1); +mm_iu_ierat_snoop_coming : out std_ulogic; +mm_iu_ierat_snoop_val : out std_ulogic; +mm_iu_ierat_snoop_attr : out std_ulogic_vector(0 to 25); +mm_iu_ierat_snoop_vpn : out std_ulogic_vector(52-epn_width to 51); +iu_mm_ierat_snoop_ack : in std_ulogic; +mm_iu_ierat_pid0 : out std_ulogic_vector(0 to pid_width-1); +mm_iu_ierat_pid1 : out std_ulogic_vector(0 to pid_width-1); +mm_iu_ierat_pid2 : out std_ulogic_vector(0 to pid_width-1); +mm_iu_ierat_pid3 : out std_ulogic_vector(0 to pid_width-1); +mm_iu_ierat_mmucr0_0 : out std_ulogic_vector(0 to 19); +mm_iu_ierat_mmucr0_1 : out std_ulogic_vector(0 to 19); +mm_iu_ierat_mmucr0_2 : out std_ulogic_vector(0 to 19); +mm_iu_ierat_mmucr0_3 : out std_ulogic_vector(0 to 19); +iu_mm_ierat_mmucr0 : in std_ulogic_vector(0 to 17); +iu_mm_ierat_mmucr0_we : in std_ulogic_vector(0 to 3); +mm_iu_ierat_mmucr1 : out std_ulogic_vector(0 to 8); +iu_mm_ierat_mmucr1 : in std_ulogic_vector(0 to 3); +iu_mm_ierat_mmucr1_we : in std_ulogic; +xu_mm_derat_req : in std_ulogic; +xu_mm_derat_epn : in std_ulogic_vector(64-rs_data_width to 51); +xu_mm_derat_thdid : in std_ulogic_vector(0 to thdid_width-1); +xu_mm_derat_ttype : in std_ulogic_vector(0 to 1); +xu_mm_derat_state : in std_ulogic_vector(0 to state_width-1); +xu_mm_derat_lpid : in std_ulogic_vector(0 to lpid_width-1); +xu_mm_derat_tid : in std_ulogic_vector(0 to pid_width-1); +mm_xu_derat_rel_val : out std_ulogic_vector(0 to 4); +mm_xu_derat_rel_data : out std_ulogic_vector(0 to erat_rel_data_width-1); +mm_xu_derat_snoop_coming : out std_ulogic; +mm_xu_derat_snoop_val : out std_ulogic; +mm_xu_derat_snoop_attr : out std_ulogic_vector(0 to 25); +mm_xu_derat_snoop_vpn : out std_ulogic_vector(52-epn_width to 51); +xu_mm_derat_snoop_ack : in std_ulogic; +mm_xu_derat_pid0 : out std_ulogic_vector(0 to pid_width-1); +mm_xu_derat_pid1 : out std_ulogic_vector(0 to pid_width-1); +mm_xu_derat_pid2 : out std_ulogic_vector(0 to pid_width-1); +mm_xu_derat_pid3 : out std_ulogic_vector(0 to pid_width-1); +mm_xu_derat_mmucr0_0 : out std_ulogic_vector(0 to 19); +mm_xu_derat_mmucr0_1 : out std_ulogic_vector(0 to 19); +mm_xu_derat_mmucr0_2 : out std_ulogic_vector(0 to 19); +mm_xu_derat_mmucr0_3 : out std_ulogic_vector(0 to 19); +xu_mm_derat_mmucr0 : in std_ulogic_vector(0 to 17); +xu_mm_derat_mmucr0_we : in std_ulogic_vector(0 to 3); +mm_xu_derat_mmucr1 : out std_ulogic_vector(0 to 9); +xu_mm_derat_mmucr1 : in std_ulogic_vector(0 to 4); +xu_mm_derat_mmucr1_we : in std_ulogic; +xu_mm_rf1_val : in std_ulogic_vector(0 to 3); +xu_mm_rf1_is_tlbre : in std_ulogic; +xu_mm_rf1_is_tlbwe : in std_ulogic; +xu_mm_rf1_is_tlbsx : in std_ulogic; +xu_mm_rf1_is_tlbsxr : in std_ulogic; +xu_mm_rf1_is_tlbsrx : in std_ulogic; +xu_mm_rf1_is_tlbivax : in std_ulogic; +xu_mm_rf1_is_tlbilx : in std_ulogic; +xu_mm_rf1_is_erativax : in std_ulogic; +xu_mm_rf1_is_eratilx : in std_ulogic; +xu_mm_ex1_is_isync : in std_ulogic; +xu_mm_ex1_is_csync : in std_ulogic; +xu_mm_rf1_t : in std_ulogic_vector(0 to 2); +xu_mm_ex1_rs_is : in std_ulogic_vector(0 to 8); +xu_mm_ex2_eff_addr : in std_ulogic_vector(64-rs_data_width to 63); +xu_mm_msr_gs : in std_ulogic_vector(0 to thdid_width-1); +xu_mm_msr_pr : in std_ulogic_vector(0 to thdid_width-1); +xu_mm_msr_is : in std_ulogic_vector(0 to thdid_width-1); +xu_mm_msr_ds : in std_ulogic_vector(0 to thdid_width-1); +xu_mm_msr_cm : in std_ulogic_vector(0 to thdid_width-1); +xu_mm_spr_epcr_dmiuh : in std_ulogic_vector(0 to thdid_width-1); +xu_mm_spr_epcr_dgtmi : in std_ulogic_vector(0 to thdid_width-1); +xu_mm_hid_mmu_mode : in std_ulogic; +xu_mm_xucr4_mmu_mchk : in std_ulogic; +xu_mm_lmq_stq_empty : in std_ulogic; +iu_mm_lmq_empty : in std_ulogic; +xu_rf1_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_ex1_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_ex2_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_ex3_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_ex4_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_ex5_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_mm_ex4_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_mm_ex5_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_mm_ierat_miss : in std_ulogic_vector(0 to thdid_width-1); +xu_mm_ierat_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_mm_ex5_perf_dtlb : in std_ulogic_vector(0 to thdid_width-1); +xu_mm_ex5_perf_itlb : in std_ulogic_vector(0 to thdid_width-1); +mm_iu_barrier_done : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_eratmiss_done : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_cr0_eq : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_cr0_eq_valid : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_tlb_miss : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_lrat_miss : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_tlb_inelig : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_pt_fault : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_hv_priv : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_illeg_instr : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_esr_pt : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_esr_data : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_esr_epid : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_esr_st : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_quiesce : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_tlb_multihit_err : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_tlb_par_err : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_lru_par_err : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_local_snoop_reject : out std_ulogic_vector(0 to thdid_width-1); +xu_mm_hold_ack : in std_ulogic_vector(0 to thdid_width-1); +mm_xu_hold_req : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_hold_done : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_ex3_flush_req : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_lsu_req : out std_ulogic_vector(0 to 3); +mm_xu_lsu_ttype : out std_ulogic_vector(0 to 1); +mm_xu_lsu_wimge : out std_ulogic_vector(0 to 4); +mm_xu_lsu_u : out std_ulogic_vector(0 to 3); +mm_xu_lsu_addr : out std_ulogic_vector(64-real_addr_width to 63); +mm_xu_lsu_lpid : out std_ulogic_vector(0 to 7); +mm_xu_lsu_lpidr : out std_ulogic_vector(0 to 7); +mm_xu_lsu_gs : out std_ulogic; +mm_xu_lsu_ind : out std_ulogic; +mm_xu_lsu_lbit : out std_ulogic; +xu_mm_lsu_token :in std_ulogic; +slowspr_val_in : in std_ulogic; +slowspr_rw_in : in std_ulogic; +slowspr_etid_in : in std_ulogic_vector(0 to 1); +slowspr_addr_in : in std_ulogic_vector(0 to 9); +slowspr_data_in : in std_ulogic_vector(64-spr_data_width to 63); +slowspr_done_in : in std_ulogic; +slowspr_val_out : out std_ulogic; +slowspr_rw_out : out std_ulogic; +slowspr_etid_out : out std_ulogic_vector(0 to 1); +slowspr_addr_out : out std_ulogic_vector(0 to 9); +slowspr_data_out : out std_ulogic_vector(64-spr_data_width to 63); +slowspr_done_out : out std_ulogic; +gptr_scan_in :in std_ulogic; +time_scan_in :in std_ulogic; +repr_scan_in :in std_ulogic; +an_ac_abst_scan_in : in std_ulogic_vector(0 to 9); +an_ac_func_scan_in : in std_ulogic_vector(0 to 63); +an_ac_bcfg_scan_in : in std_ulogic_vector(0 to 4); +an_ac_dcfg_scan_in : in std_ulogic_vector(0 to 2); +ac_an_gptr_scan_out :out std_ulogic; +ac_an_time_scan_out :out std_ulogic; +ac_an_repr_scan_out :out std_ulogic; +bcfg_scan_out :out std_ulogic; +ccfg_scan_out :out std_ulogic; +dcfg_scan_out :out std_ulogic; +an_ac_back_inv : in std_ulogic; +an_ac_back_inv_target : in std_ulogic_vector(0 to 4); +an_ac_back_inv_addr : in std_ulogic_vector(64-real_addr_width to 63); +an_ac_back_inv_local : in std_ulogic; +an_ac_back_inv_lbit : in std_ulogic; +an_ac_back_inv_gs : in std_ulogic; +an_ac_back_inv_ind : in std_ulogic; +an_ac_back_inv_lpar_id : in std_ulogic_vector(0 to lpid_width-1); +ac_an_back_inv_reject : out std_ulogic; +ac_an_lpar_id : out std_ulogic_vector(0 to lpid_width-1); +an_ac_reld_core_tag : in std_ulogic_vector(0 to 4); +an_ac_reld_data : in std_ulogic_vector(0 to 127); +an_ac_reld_data_vld : in std_ulogic; +an_ac_reld_ecc_err : in std_ulogic; +an_ac_reld_ecc_err_ue : in std_ulogic; +an_ac_reld_qw : in std_ulogic_vector(57 to 59); +an_ac_reld_ditc : in std_ulogic; +an_ac_reld_crit_qw : in std_ulogic; +an_ac_reld_data_coming : in std_ulogic; +an_ac_reld_l1_dump : in std_ulogic; +an_ac_grffence_en_dc : in std_ulogic; +an_ac_stcx_complete : in std_ulogic_vector(0 to 3); +an_ac_abist_mode_dc : in std_ulogic; +an_ac_abist_start_test : in std_ulogic; +an_ac_atpg_en_dc : in std_ulogic; +an_ac_lbist_ary_wrt_thru_dc : in std_ulogic; +an_ac_ccflush_dc : in std_ulogic; +an_ac_reset_1_complete : in std_ulogic; +an_ac_reset_2_complete : in std_ulogic; +an_ac_reset_3_complete : in std_ulogic; +an_ac_reset_wd_complete : in std_ulogic; +an_ac_debug_stop : in std_ulogic; +an_ac_lbist_en_dc : in std_ulogic; +an_ac_pm_thread_stop : in std_ulogic_vector(0 to 3); +an_ac_regf_scan_in : in std_ulogic_vector(0 to 11); +an_ac_scan_diag_dc : in std_ulogic; +an_ac_scan_dis_dc_b : in std_ulogic; +an_ac_scom_cch : in std_ulogic; +an_ac_scom_dch : in std_ulogic; +an_ac_checkstop : in std_ulogic; +-- _omm suffix means output from mmu +an_ac_back_inv_omm : out std_ulogic; +an_ac_back_inv_addr_omm : out std_ulogic_vector(64-real_addr_width to 63); +an_ac_back_inv_target_omm_iua : out std_ulogic_vector(0 to 1); +an_ac_back_inv_target_omm_iub : out std_ulogic_vector(3 to 4); +an_ac_reld_core_tag_omm : out std_ulogic_vector(0 to 4); +an_ac_reld_data_omm : out std_ulogic_vector(0 to 127); +an_ac_reld_data_vld_omm : out std_ulogic; +an_ac_reld_ecc_err_omm : out std_ulogic; +an_ac_reld_ecc_err_ue_omm : out std_ulogic; +an_ac_reld_qw_omm : out std_ulogic_vector(57 to 59); +an_ac_reld_ditc_omm : out std_ulogic; +an_ac_reld_crit_qw_omm : out std_ulogic; +an_ac_reld_data_coming_omm : out std_ulogic; +an_ac_reld_l1_dump_omm : out std_ulogic; +an_ac_grffence_en_dc_omm : out std_ulogic; +an_ac_stcx_complete_omm : out std_ulogic_vector(0 to 3); +an_ac_abist_mode_dc_omm : out std_ulogic; +an_ac_abist_start_test_omm : out std_ulogic; +an_ac_abst_scan_in_omm_iu : out std_ulogic_vector(0 to 4); +an_ac_abst_scan_in_omm_xu : out std_ulogic_vector(7 to 9); +an_ac_atpg_en_dc_omm : out std_ulogic; +an_ac_bcfg_scan_in_omm_bit1 : out std_ulogic; +an_ac_bcfg_scan_in_omm_bit3 : out std_ulogic; +an_ac_bcfg_scan_in_omm_bit4 : out std_ulogic; +an_ac_lbist_ary_wrt_thru_dc_omm : out std_ulogic; +an_ac_ccflush_dc_omm : out std_ulogic; +an_ac_reset_1_complete_omm : out std_ulogic; +an_ac_reset_2_complete_omm : out std_ulogic; +an_ac_reset_3_complete_omm : out std_ulogic; +an_ac_reset_wd_complete_omm : out std_ulogic; +an_ac_dcfg_scan_in_omm : out std_ulogic_vector(1 to 2); +an_ac_debug_stop_omm : out std_ulogic; +an_ac_func_scan_in_omm_iua : out std_ulogic_vector(0 to 21); +an_ac_func_scan_in_omm_iub : out std_ulogic_vector(60 to 63); +an_ac_func_scan_in_omm_xu : out std_ulogic_vector(31 to 58); +an_ac_lbist_en_dc_omm : out std_ulogic; +an_ac_pm_thread_stop_omm : out std_ulogic_vector(0 to 3); +an_ac_regf_scan_in_omm : out std_ulogic_vector(0 to 11); +an_ac_scan_diag_dc_omm : out std_ulogic; +an_ac_scan_dis_dc_b_omm : out std_ulogic; +an_ac_scom_cch_omm : out std_ulogic; +an_ac_scom_dch_omm : out std_ulogic; +an_ac_checkstop_omm : out std_ulogic; +-- _imm prefix means input to mmu +ac_an_abst_scan_out_imm_iu : in std_ulogic_vector(0 to 4); +ac_an_abst_scan_out_imm_xu : in std_ulogic_vector(7 to 9); +ac_an_bcfg_scan_out_imm : in std_ulogic_vector(0 to 4); +ac_an_dcfg_scan_out_imm : in std_ulogic_vector(0 to 2); +ac_an_func_scan_out_imm_iua : in std_ulogic_vector(0 to 21); +ac_an_func_scan_out_imm_iub : in std_ulogic_vector(60 to 63); +ac_an_func_scan_out_imm_xu : in std_ulogic_vector(31 to 58); +ac_an_reld_ditc_pop_imm : in std_ulogic_vector(0 to 3); +ac_an_power_managed_imm : in std_ulogic; +ac_an_rvwinkle_mode_imm : in std_ulogic; +ac_an_fu_bypass_events_imm : in std_ulogic_vector(0 to 7); +ac_an_iu_bypass_events_imm : in std_ulogic_vector(0 to 7); +ac_an_mm_bypass_events_imm : in std_ulogic_vector(0 to 7); +ac_an_lsu_bypass_events_imm : in std_ulogic_vector(0 to 7); +ac_an_event_bus_imm : in std_ulogic_vector(0 to 7); +ac_an_pm_thread_running_imm : in std_ulogic_vector(0 to 3); +ac_an_recov_err_imm : in std_ulogic_vector(0 to 2); +ac_an_regf_scan_out_imm : in std_ulogic_vector(0 to 11); +ac_an_scom_cch_imm : in std_ulogic; +ac_an_scom_dch_imm : in std_ulogic; +ac_an_special_attn_imm : in std_ulogic_vector(0 to 3); +ac_an_checkstop_imm : in std_ulogic_vector(0 to 2); +ac_an_local_checkstop_imm : in std_ulogic_vector(0 to 2); +ac_an_trace_error_imm : in std_ulogic; +ac_an_abst_scan_out : out std_ulogic_vector(0 to 9); +ac_an_bcfg_scan_out : out std_ulogic_vector(0 to 4); +ac_an_dcfg_scan_out : out std_ulogic_vector(0 to 2); +ac_an_func_scan_out : out std_ulogic_vector(0 to 63); +ac_an_reld_ditc_pop : out std_ulogic_vector(0 to 3); +ac_an_power_managed : out std_ulogic; +ac_an_rvwinkle_mode : out std_ulogic; +ac_an_fu_bypass_events : out std_ulogic_vector(0 to 7); +ac_an_iu_bypass_events : out std_ulogic_vector(0 to 7); +ac_an_mm_bypass_events : out std_ulogic_vector(0 to 7); +ac_an_lsu_bypass_events : out std_ulogic_vector(0 to 7); +ac_an_event_bus : out std_ulogic_vector(0 to 7); +ac_an_pm_thread_running : out std_ulogic_vector(0 to 3); +ac_an_recov_err : out std_ulogic_vector(0 to 2); +ac_an_regf_scan_out : out std_ulogic_vector(0 to 11); +ac_an_scom_cch : out std_ulogic; +ac_an_scom_dch : out std_ulogic; +ac_an_special_attn : out std_ulogic_vector(0 to 3); +ac_an_checkstop : out std_ulogic_vector(0 to 2); +ac_an_local_checkstop : out std_ulogic_vector(0 to 2); +ac_an_trace_error : out std_ulogic; +an_ac_dcr_act : in std_ulogic; +an_ac_dcr_val : in std_ulogic; +an_ac_dcr_read : in std_ulogic; +an_ac_dcr_etid : in std_ulogic_vector(0 to 1); +an_ac_dcr_data : in std_ulogic_vector(64-spr_data_width to 63); +an_ac_dcr_done : in std_ulogic; +an_ac_crit_interrupt : in std_ulogic_vector(0 to thdid_width-1); +an_ac_ext_interrupt : in std_ulogic_vector(0 to thdid_width-1); +an_ac_flh2l2_gate : in std_ulogic; +an_ac_icbi_ack : in std_ulogic; +an_ac_icbi_ack_thread : in std_ulogic_vector(0 to 1); +an_ac_req_ld_pop : in std_ulogic; +an_ac_req_spare_ctrl_a1 : in std_ulogic_vector(0 to 3); +an_ac_req_st_gather : in std_ulogic; +an_ac_req_st_pop : in std_ulogic; +an_ac_req_st_pop_thrd : in std_ulogic_vector(0 to 2); +an_ac_reservation_vld : in std_ulogic_vector(0 to thdid_width-1); +an_ac_sleep_en : in std_ulogic_vector(0 to thdid_width-1); +an_ac_stcx_pass : in std_ulogic_vector(0 to 3); +an_ac_sync_ack : in std_ulogic_vector(0 to 3); +an_ac_ary_nsl_thold_7 : in std_ulogic; +an_ac_ccenable_dc : in std_ulogic; +an_ac_coreid : in std_ulogic_vector(0 to 7); +an_ac_external_mchk : in std_ulogic_vector(0 to 3); +an_ac_fce_7 : in std_ulogic; +an_ac_func_nsl_thold_7 : in std_ulogic; +an_ac_func_sl_thold_7 : in std_ulogic; +an_ac_gsd_test_enable_dc : in std_ulogic; +an_ac_gsd_test_acmode_dc : in std_ulogic; +an_ac_gptr_scan_in : in std_ulogic; +an_ac_hang_pulse : in std_ulogic_vector(0 to thdid_width-1); +an_ac_lbist_ac_mode_dc : in std_ulogic; +an_ac_lbist_ip_dc : in std_ulogic; +an_ac_malf_alert : in std_ulogic; +an_ac_perf_interrupt : in std_ulogic_vector(0 to thdid_width-1); +an_ac_psro_enable_dc : in std_ulogic_vector(0 to 2); +an_ac_repr_scan_in : in std_ulogic; +an_ac_rtim_sl_thold_7 : in std_ulogic; +an_ac_scan_type_dc : in std_ulogic_vector(0 to 8); +an_ac_scom_sat_id : in std_ulogic_vector(0 to 3); +an_ac_sg_7 : in std_ulogic; +an_ac_tb_update_enable : in std_ulogic; +an_ac_tb_update_pulse : in std_ulogic; +an_ac_time_scan_in : in std_ulogic; +an_ac_crit_interrupt_omm : out std_ulogic_vector(0 to thdid_width-1); +an_ac_ext_interrupt_omm : out std_ulogic_vector(0 to thdid_width-1); +an_ac_flh2l2_gate_omm : out std_ulogic; +an_ac_icbi_ack_omm : out std_ulogic; +an_ac_icbi_ack_thread_omm : out std_ulogic_vector(0 to 1); +an_ac_req_ld_pop_omm : out std_ulogic; +an_ac_req_spare_ctrl_a1_omm : out std_ulogic_vector(0 to 3); +an_ac_req_st_gather_omm : out std_ulogic; +an_ac_req_st_pop_omm : out std_ulogic; +an_ac_req_st_pop_thrd_omm : out std_ulogic_vector(0 to 2); +an_ac_reservation_vld_omm : out std_ulogic_vector(0 to thdid_width-1); +an_ac_sleep_en_omm : out std_ulogic_vector(0 to thdid_width-1); +an_ac_stcx_pass_omm : out std_ulogic_vector(0 to 3); +an_ac_sync_ack_omm : out std_ulogic_vector(0 to 3); +an_ac_ary_nsl_thold_7_omm : out std_ulogic; +an_ac_ccenable_dc_omm : out std_ulogic; +an_ac_coreid_omm : out std_ulogic_vector(0 to 7); +an_ac_external_mchk_omm : out std_ulogic_vector(0 to 3); +an_ac_fce_7_omm : out std_ulogic; +an_ac_func_nsl_thold_7_omm : out std_ulogic; +an_ac_func_sl_thold_7_omm : out std_ulogic; +an_ac_gsd_test_enable_dc_omm : out std_ulogic; +an_ac_gsd_test_acmode_dc_omm : out std_ulogic; +an_ac_gptr_scan_in_omm : out std_ulogic; +an_ac_hang_pulse_omm : out std_ulogic_vector(0 to thdid_width-1); +an_ac_lbist_ac_mode_dc_omm : out std_ulogic; +an_ac_lbist_ip_dc_omm : out std_ulogic; +an_ac_malf_alert_omm : out std_ulogic; +an_ac_perf_interrupt_omm : out std_ulogic_vector(0 to thdid_width-1); +an_ac_psro_enable_dc_omm : out std_ulogic_vector(0 to 2); +an_ac_repr_scan_in_omm : out std_ulogic; +an_ac_rtim_sl_thold_7_omm : out std_ulogic; +an_ac_scan_type_dc_omm : out std_ulogic_vector(0 to 8); +an_ac_scom_sat_id_omm : out std_ulogic_vector(0 to 3); +an_ac_sg_7_omm : out std_ulogic; +an_ac_tb_update_enable_omm : out std_ulogic; +an_ac_tb_update_pulse_omm : out std_ulogic; +an_ac_time_scan_in_omm : out std_ulogic; +ac_an_box_empty_imm : in std_ulogic_vector(0 to 3); +ac_an_machine_check_imm : in std_ulogic_vector(0 to thdid_width-1); +ac_an_req_imm : in std_ulogic; +ac_an_req_endian_imm : in std_ulogic; +ac_an_req_ld_core_tag_imm : in std_ulogic_vector(0 to 4); +ac_an_req_ld_xfr_len_imm : in std_ulogic_vector(0 to 2); +ac_an_req_pwr_token_imm : in std_ulogic; +ac_an_req_ra_imm : in std_ulogic_vector(64-real_addr_width to 63); +ac_an_req_spare_ctrl_a0_imm : in std_ulogic_vector(0 to 3); +ac_an_req_thread_imm : in std_ulogic_vector(0 to 2); +ac_an_req_ttype_imm : in std_ulogic_vector(0 to 5); +ac_an_req_user_defined_imm : in std_ulogic_vector(0 to 3); +ac_an_req_wimg_g_imm : in std_ulogic; +ac_an_req_wimg_i_imm : in std_ulogic; +ac_an_req_wimg_m_imm : in std_ulogic; +ac_an_req_wimg_w_imm : in std_ulogic; +ac_an_st_byte_enbl_imm : in std_ulogic_vector(0 to 31); +ac_an_st_data_imm : in std_ulogic_vector(0 to 255); +ac_an_st_data_pwr_token_imm : in std_ulogic; +ac_an_abist_done_dc_imm : in std_ulogic; +ac_an_debug_trigger_imm : in std_ulogic_vector(0 to thdid_width-1); +ac_an_psro_ringsig_imm : in std_ulogic; +ac_an_reset_1_request_imm : in std_ulogic; +ac_an_reset_2_request_imm : in std_ulogic; +ac_an_reset_3_request_imm : in std_ulogic; +ac_an_reset_wd_request_imm : in std_ulogic; +ac_an_box_empty : out std_ulogic_vector(0 to 3); +ac_an_machine_check : out std_ulogic_vector(0 to thdid_width-1); +ac_an_req : out std_ulogic; +ac_an_req_endian : out std_ulogic; +ac_an_req_ld_core_tag : out std_ulogic_vector(0 to 4); +ac_an_req_ld_xfr_len : out std_ulogic_vector(0 to 2); +ac_an_req_pwr_token : out std_ulogic; +ac_an_req_ra : out std_ulogic_vector(64-real_addr_width to 63); +ac_an_req_spare_ctrl_a0 : out std_ulogic_vector(0 to 3); +ac_an_req_thread : out std_ulogic_vector(0 to 2); +ac_an_req_ttype : out std_ulogic_vector(0 to 5); +ac_an_req_user_defined : out std_ulogic_vector(0 to 3); +ac_an_req_wimg_g : out std_ulogic; +ac_an_req_wimg_i : out std_ulogic; +ac_an_req_wimg_m : out std_ulogic; +ac_an_req_wimg_w : out std_ulogic; +ac_an_st_byte_enbl : out std_ulogic_vector(0 to 31); +ac_an_st_data : out std_ulogic_vector(0 to 255); +ac_an_st_data_pwr_token : out std_ulogic; +ac_an_abist_done_dc : out std_ulogic; +ac_an_debug_trigger : out std_ulogic_vector(0 to thdid_width-1); +ac_an_psro_ringsig : out std_ulogic; +ac_an_reset_1_request : out std_ulogic; +ac_an_reset_2_request : out std_ulogic; +ac_an_reset_3_request : out std_ulogic; +ac_an_reset_wd_request : out std_ulogic; +ac_an_dcr_act : out std_ulogic; +ac_an_dcr_val : out std_ulogic; +ac_an_dcr_read : out std_ulogic; +ac_an_dcr_user : out std_ulogic; +ac_an_dcr_etid : out std_ulogic_vector(0 to 1); +ac_an_dcr_addr : out std_ulogic_vector(11 to 20); +ac_an_dcr_data : out std_ulogic_vector(64-spr_data_width to 63); +-- Pass thru wires specifically for Bluegene, PC -> IU -> MMU -> L1P/TPB +bg_ac_an_func_scan_ns_imm : in std_ulogic_vector(60 to 69); +bg_ac_an_abst_scan_ns_imm : in std_ulogic_vector(10 to 11); +bg_ac_an_func_scan_ns : out std_ulogic_vector(60 to 69); +bg_ac_an_abst_scan_ns : out std_ulogic_vector(10 to 11); +bg_pc_l1p_abist_di_0_imm : in std_ulogic_vector(0 to 3); +bg_pc_l1p_abist_g8t1p_renb_0_imm : in std_ulogic; +bg_pc_l1p_abist_g8t_bw_0_imm : in std_ulogic; +bg_pc_l1p_abist_g8t_bw_1_imm : in std_ulogic; +bg_pc_l1p_abist_g8t_dcomp_imm : in std_ulogic_vector(0 to 3); +bg_pc_l1p_abist_g8t_wenb_imm : in std_ulogic; +bg_pc_l1p_abist_raddr_0_imm : in std_ulogic_vector(0 to 9); +bg_pc_l1p_abist_waddr_0_imm : in std_ulogic_vector(0 to 9); +bg_pc_l1p_abist_wl128_comp_ena_imm : in std_ulogic; +bg_pc_l1p_abist_wl32_comp_ena_imm : in std_ulogic; +bg_pc_l1p_abist_di_0 : out std_ulogic_vector(0 to 3); +bg_pc_l1p_abist_g8t1p_renb_0 : out std_ulogic; +bg_pc_l1p_abist_g8t_bw_0 : out std_ulogic; +bg_pc_l1p_abist_g8t_bw_1 : out std_ulogic; +bg_pc_l1p_abist_g8t_dcomp : out std_ulogic_vector(0 to 3); +bg_pc_l1p_abist_g8t_wenb : out std_ulogic; +bg_pc_l1p_abist_raddr_0 : out std_ulogic_vector(0 to 9); +bg_pc_l1p_abist_waddr_0 : out std_ulogic_vector(0 to 9); +bg_pc_l1p_abist_wl128_comp_ena : out std_ulogic; +bg_pc_l1p_abist_wl32_comp_ena : out std_ulogic; +bg_pc_l1p_gptr_sl_thold_2_imm : in std_ulogic; +bg_pc_l1p_time_sl_thold_2_imm : in std_ulogic; +bg_pc_l1p_repr_sl_thold_2_imm : in std_ulogic; +bg_pc_l1p_abst_sl_thold_2_imm : in std_ulogic; +bg_pc_l1p_func_sl_thold_2_imm : in std_ulogic_vector(0 to 1); +bg_pc_l1p_func_slp_sl_thold_2_imm : in std_ulogic; +bg_pc_l1p_bolt_sl_thold_2_imm : in std_ulogic; +bg_pc_l1p_ary_nsl_thold_2_imm : in std_ulogic; +bg_pc_l1p_sg_2_imm : in std_ulogic_vector(0 to 1); +bg_pc_l1p_fce_2_imm : in std_ulogic; +bg_pc_l1p_bo_enable_2_imm : in std_ulogic; +bg_pc_l1p_gptr_sl_thold_2 : out std_ulogic; +bg_pc_l1p_time_sl_thold_2 : out std_ulogic; +bg_pc_l1p_repr_sl_thold_2 : out std_ulogic; +bg_pc_l1p_abst_sl_thold_2 : out std_ulogic; +bg_pc_l1p_func_sl_thold_2 : out std_ulogic_vector(0 to 1); +bg_pc_l1p_func_slp_sl_thold_2 : out std_ulogic; +bg_pc_l1p_bolt_sl_thold_2 : out std_ulogic; +bg_pc_l1p_ary_nsl_thold_2 : out std_ulogic; +bg_pc_l1p_sg_2 : out std_ulogic_vector(0 to 1); +bg_pc_l1p_fce_2 : out std_ulogic; +bg_pc_l1p_bo_enable_2 : out std_ulogic; +bg_pc_bo_unload_imm : in std_ulogic; +bg_pc_bo_load_imm : in std_ulogic; +bg_pc_bo_repair_imm : in std_ulogic; +bg_pc_bo_reset_imm : in std_ulogic; +bg_pc_bo_shdata_imm : in std_ulogic; +bg_pc_bo_select_imm : in std_ulogic_vector(0 to 10); +bg_pc_l1p_ccflush_dc_imm : in std_ulogic; +bg_pc_l1p_abist_ena_dc_imm : in std_ulogic; +bg_pc_l1p_abist_raw_dc_b_imm : in std_ulogic; +bg_pc_bo_unload : out std_ulogic; +bg_pc_bo_load : out std_ulogic; +bg_pc_bo_repair : out std_ulogic; +bg_pc_bo_reset : out std_ulogic; +bg_pc_bo_shdata : out std_ulogic; +bg_pc_bo_select : out std_ulogic_vector(0 to 10); +bg_pc_l1p_ccflush_dc : out std_ulogic; +bg_pc_l1p_abist_ena_dc : out std_ulogic; +bg_pc_l1p_abist_raw_dc_b : out std_ulogic; +-- Pass thru wires specifically for Bluegene, L1P/TPB -> MMU -> IU -> PC +bg_an_ac_func_scan_sn : in std_ulogic_vector(60 to 69); +bg_an_ac_abst_scan_sn : in std_ulogic_vector(10 to 11); +bg_an_ac_func_scan_sn_omm : out std_ulogic_vector(60 to 69); +bg_an_ac_abst_scan_sn_omm : out std_ulogic_vector(10 to 11); +bg_pc_bo_fail : in std_ulogic_vector(0 to 10); +bg_pc_bo_diagout : in std_ulogic_vector(0 to 10); +bg_pc_bo_fail_omm : out std_ulogic_vector(0 to 10); +bg_pc_bo_diagout_omm : out std_ulogic_vector(0 to 10) +); +end mmq; +architecture mmq of mmq is +constant MMU_Mode_Value : std_ulogic := '0'; +constant TlbSel_Tlb : std_ulogic_vector(0 to 1) := "00"; +constant TlbSel_IErat : std_ulogic_vector(0 to 1) := "10"; +constant TlbSel_DErat : std_ulogic_vector(0 to 1) := "11"; +-- func scan bit 0 is mmq_inval (701), mmq_spr(0) non-mas (439) ~1140 +-- func scan bit 1 is mmq_spr(1) mas regs (1017) ~1017 +-- func scan bit 2 is tlb_req ~1196 +-- func scan bit 3 is tlb_ctl ~1101 +-- func scan bit 4 is tlb_cmp(0) ~1134 +-- func scan bit 5 is tlb_cmp(1) ~1134 +-- func scan bit 6 is tlb_lrat ~1059 +-- func scan bit 7 is tlb_htw(0) ~802 +-- func scan bit 8 is tlb_htw(1) ~663 +-- func scan bit 9 is tlb_cmp(2), perf (60), debug daisy chain (134) ~636 +constant mmq_inval_offset : natural := 0; +constant mmq_spr_offset_0 : natural := mmq_inval_offset + 1; +constant scan_right_0 : natural := mmq_spr_offset_0; +constant tlb_cmp2_offset : natural := 0; +constant mmq_perf_offset : natural := tlb_cmp2_offset + 1; +constant mmq_dbg_offset : natural := mmq_perf_offset + 1; +constant scan_right_1 : natural := mmq_dbg_offset; +constant mmq_spr_bcfg_offset : natural := 0; +constant boot_scan_right : natural := mmq_spr_bcfg_offset + 1 - 1; +-- local spr signals +signal pid0_sig : std_ulogic_vector(0 to pid_width-1); +signal pid1_sig : std_ulogic_vector(0 to pid_width-1); +signal pid2_sig : std_ulogic_vector(0 to pid_width-1); +signal pid3_sig : std_ulogic_vector(0 to pid_width-1); +signal mmucr0_0_sig : std_ulogic_vector(0 to mmucr0_width-1); +signal mmucr0_1_sig : std_ulogic_vector(0 to mmucr0_width-1); +signal mmucr0_2_sig : std_ulogic_vector(0 to mmucr0_width-1); +signal mmucr0_3_sig : std_ulogic_vector(0 to mmucr0_width-1); +signal mmucr1_sig : std_ulogic_vector(0 to mmucr1_width-1); +signal mmucr2_sig : std_ulogic_vector(0 to mmucr2_width-1); +signal mmucr3_0_sig : std_ulogic_vector(64-mmucr3_width to 63); +signal mmucr3_1_sig : std_ulogic_vector(64-mmucr3_width to 63); +signal mmucr3_2_sig : std_ulogic_vector(64-mmucr3_width to 63); +signal mmucr3_3_sig : std_ulogic_vector(64-mmucr3_width to 63); +signal lpidr_sig : std_ulogic_vector(0 to lpid_width-1); +signal ac_an_lpar_id_sig : std_ulogic_vector(0 to lpid_width-1); +signal mm_iu_ierat_rel_val_sig : std_ulogic_vector(0 to 4); +signal mm_iu_ierat_rel_data_sig : std_ulogic_vector(0 to erat_rel_data_width-1); +signal mm_xu_derat_rel_val_sig : std_ulogic_vector(0 to 4); +signal mm_xu_derat_rel_data_sig : std_ulogic_vector(0 to erat_rel_data_width-1); +signal mm_xu_hold_req_sig : std_ulogic_vector(0 to thdid_width-1); +signal mm_xu_hold_done_sig : std_ulogic_vector(0 to thdid_width-1); +signal tlb_cmp_ierat_dup_val_sig : std_ulogic_vector(0 to 6); +signal tlb_cmp_derat_dup_val_sig : std_ulogic_vector(0 to 6); +signal tlb_cmp_erat_dup_wait_sig : std_ulogic_vector(0 to 1); +signal tlb_ctl_ex2_flush_req_sig : std_ulogic_vector(0 to thdid_width-1); +signal tlb_ctl_ex2_illeg_instr_sig : std_ulogic_vector(0 to thdid_width-1); +signal tlb_ctl_barrier_done_sig : std_ulogic_vector(0 to thdid_width-1); +signal mm_iu_barrier_done_sig : std_ulogic_vector(0 to thdid_width-1); +signal mm_xu_ex3_flush_req_sig : std_ulogic_vector(0 to thdid_width-1); +signal mm_xu_quiesce_sig : std_ulogic_vector(0 to thdid_width-1); +signal mm_xu_eratmiss_done_sig : std_ulogic_vector(0 to thdid_width-1); +signal mm_xu_tlb_miss_sig : std_ulogic_vector(0 to thdid_width-1); +signal mm_xu_lrat_miss_sig : std_ulogic_vector(0 to thdid_width-1); +signal mm_xu_pt_fault_sig : std_ulogic_vector(0 to thdid_width-1); +signal mm_xu_hv_priv_sig : std_ulogic_vector(0 to thdid_width-1); +signal mm_xu_illeg_instr_sig : std_ulogic_vector(0 to thdid_width-1); +signal mm_xu_tlb_inelig_sig : std_ulogic_vector(0 to thdid_width-1); +signal mm_xu_esr_pt_sig : std_ulogic_vector(0 to thdid_width-1); +signal mm_xu_esr_data_sig : std_ulogic_vector(0 to thdid_width-1); +signal mm_xu_esr_epid_sig : std_ulogic_vector(0 to thdid_width-1); +signal mm_xu_esr_st_sig : std_ulogic_vector(0 to thdid_width-1); +signal mm_xu_cr0_eq_sig : std_ulogic_vector(0 to thdid_width-1); +signal mm_xu_cr0_eq_valid_sig : std_ulogic_vector(0 to thdid_width-1); +signal mm_xu_local_snoop_reject_sig : std_ulogic_vector(0 to thdid_width-1); +signal tlb_req_quiesce_sig : std_ulogic_vector(0 to thdid_width-1); +signal tlb_ctl_quiesce_sig : std_ulogic_vector(0 to thdid_width-1); +signal htw_quiesce_sig : std_ulogic_vector(0 to thdid_width-1); +signal xu_mm_ccr2_notlb_b : std_ulogic_vector(1 to 12); +signal xu_mm_epcr_dgtmi_sig : std_ulogic_vector(0 to thdid_width-1); +signal xu_mm_xucr4_mmu_mchk_q : std_ulogic; +-- Internal signals +signal lru_write : std_ulogic_vector(0 to lru_width-1); +signal lru_wr_addr : std_ulogic_vector(0 to tlb_addr_width-1); +signal lru_rd_addr : std_ulogic_vector(0 to tlb_addr_width-1); +signal lru_datain : std_ulogic_vector(0 to lru_width-1); +signal lru_dataout : std_ulogic_vector(0 to lru_width-1); +signal tlb_tag2_sig : std_ulogic_vector(0 to tlb_tag_width-1); +signal tlb_addr2_sig : std_ulogic_vector(0 to tlb_addr_width-1); +signal tlb_write : std_ulogic_vector(0 to tlb_ways-1); +signal tlb_addr : std_ulogic_vector(0 to tlb_addr_width-1); +signal tlb_dataina : std_ulogic_vector(0 to tlb_way_width-1); +signal tlb_datainb : std_ulogic_vector(0 to tlb_way_width-1); +signal tlb_dataout : std_ulogic_vector(0 to tlb_way_width*tlb_ways-1); +signal lru_tag4_dataout : std_ulogic_vector(0 to 15); +signal tlb_tag4_esel : std_ulogic_vector(0 to 2); +signal tlb_tag4_wq : std_ulogic_vector(0 to 1); +signal tlb_tag4_is : std_ulogic_vector(0 to 1); +signal tlb_tag4_gs : std_ulogic; +signal tlb_tag4_pr : std_ulogic; +signal tlb_tag4_hes : std_ulogic; +signal tlb_tag4_atsel : std_ulogic; +signal tlb_tag4_pt : std_ulogic; +signal tlb_tag4_cmp_hit : std_ulogic; +signal tlb_tag4_way_ind : std_ulogic; +signal tlb_tag4_ptereload : std_ulogic; +signal tlb_tag4_endflag : std_ulogic; +signal tlb_tag4_parerr : std_ulogic; +signal tlb_tag5_except : std_ulogic_vector(0 to thdid_width-1); +signal ptereload_req_pte_lat : std_ulogic_vector(0 to pte_width-1); +signal ex6_illeg_instr : std_ulogic_vector(0 to 1); +signal tlb_ctl_tag2_flush_sig : std_ulogic_vector(0 to thdid_width-1); +signal tlb_ctl_tag3_flush_sig : std_ulogic_vector(0 to thdid_width-1); +signal tlb_ctl_tag4_flush_sig : std_ulogic_vector(0 to thdid_width-1); +signal tlb_resv_match_vec_sig : std_ulogic_vector(0 to thdid_width-1); +signal tlb_ctl_ex3_valid_sig : std_ulogic_vector(0 to thdid_width-1); +signal tlb_ctl_ex3_ttype_sig : std_ulogic_vector(0 to 4); +signal ierat_req_taken : std_ulogic; +signal derat_req_taken : std_ulogic; +signal tlb_seq_ierat_req : std_ulogic; +signal tlb_seq_derat_req : std_ulogic; +signal tlb_seq_ierat_done : std_ulogic; +signal tlb_seq_derat_done : std_ulogic; +signal tlb_seq_idle : std_ulogic; +signal ierat_req_epn : std_ulogic_vector(0 to req_epn_width-1); +signal ierat_req_pid : std_ulogic_vector(0 to pid_width-1); +signal ierat_req_state : std_ulogic_vector(0 to state_width-1); +signal ierat_req_thdid : std_ulogic_vector(0 to thdid_width-1); +signal ierat_req_dup : std_ulogic_vector(0 to 1); +signal derat_req_epn : std_ulogic_vector(0 to req_epn_width-1); +signal derat_req_pid : std_ulogic_vector(0 to pid_width-1); +signal derat_req_lpid : std_ulogic_vector(0 to lpid_width-1); +signal derat_req_state : std_ulogic_vector(0 to state_width-1); +signal derat_req_ttype : std_ulogic_vector(0 to 1); +signal derat_req_thdid : std_ulogic_vector(0 to thdid_width-1); +signal derat_req_dup : std_ulogic_vector(0 to 1); +signal ptereload_req_valid : std_ulogic; +signal ptereload_req_tag : std_ulogic_vector(0 to tlb_tag_width-1); +signal ptereload_req_pte : std_ulogic_vector(0 to pte_width-1); +signal ptereload_req_taken : std_ulogic; +signal tlb_htw_req_valid : std_ulogic; +signal tlb_htw_req_tag : std_ulogic_vector(0 to tlb_tag_width-1); +signal tlb_htw_req_way : std_ulogic_vector(tlb_word_width to tlb_way_width-1); +signal htw_lsu_req_valid : std_ulogic; +signal htw_lsu_thdid : std_ulogic_vector(0 to thdid_width-1); +signal htw_dbg_lsu_thdid : std_ulogic_vector(0 to 1); +-- 0=tlbivax_op, 1=tlbi_complete, 2=mmu read with core_tag=01100, 3=mmu read with core_tag=01101 +signal htw_lsu_ttype : std_ulogic_vector(0 to 1); +signal htw_lsu_wimge : std_ulogic_vector(0 to 4); +signal htw_lsu_u : std_ulogic_vector(0 to 3); +signal htw_lsu_addr : std_ulogic_vector(64-real_addr_width to 63); +signal htw_lsu_req_taken : std_ulogic; +signal htw_req0_valid : std_ulogic; +signal htw_req0_thdid : std_ulogic_vector(0 to thdid_width-1); +signal htw_req0_type : std_ulogic_vector(0 to 1); +signal htw_req1_valid : std_ulogic; +signal htw_req1_thdid : std_ulogic_vector(0 to thdid_width-1); +signal htw_req1_type : std_ulogic_vector(0 to 1); +signal htw_req2_valid : std_ulogic; +signal htw_req2_thdid : std_ulogic_vector(0 to thdid_width-1); +signal htw_req2_type : std_ulogic_vector(0 to 1); +signal htw_req3_valid : std_ulogic; +signal htw_req3_thdid : std_ulogic_vector(0 to thdid_width-1); +signal htw_req3_type : std_ulogic_vector(0 to 1); +signal mm_xu_lsu_req_sig : std_ulogic_vector(0 to 3); +signal mm_xu_lsu_ttype_sig : std_ulogic_vector(0 to 1); +signal mm_xu_lsu_wimge_sig : std_ulogic_vector(0 to 4); +signal mm_xu_lsu_u_sig : std_ulogic_vector(0 to 3); +signal mm_xu_lsu_addr_sig : std_ulogic_vector(64-real_addr_width to 63); +signal mm_xu_lsu_lpid_sig : std_ulogic_vector(0 to 7); +signal mm_xu_lsu_gs_sig : std_ulogic; +signal mm_xu_lsu_ind_sig : std_ulogic; +signal mm_xu_lsu_lbit_sig : std_ulogic; +signal xu_mm_ex2_eff_addr_sig : std_ulogic_vector(64-rs_data_width to 63); +signal repr_scan_int : std_ulogic_vector(0 to 5); +signal time_scan_int : std_ulogic_vector(0 to 5); +signal abst_scan_int : std_ulogic_vector(0 to 6); +signal tlbwe_back_inv_valid_sig : std_ulogic; +signal tlbwe_back_inv_thdid_sig : std_ulogic_vector(0 to thdid_width-1); +signal tlbwe_back_inv_addr_sig : std_ulogic_vector(52-epn_width to 51); +signal tlbwe_back_inv_attr_sig : std_ulogic_vector(0 to 34); +signal tlbwe_back_inv_pending_sig : std_ulogic; +signal tlb_tag5_write : std_ulogic; +-- these are needed regardless of tlb existence +signal tlb_snoop_coming : std_ulogic; +signal tlb_snoop_val : std_ulogic; +signal tlb_snoop_attr : std_ulogic_vector(0 to 34); +signal tlb_snoop_vpn : std_ulogic_vector(52-epn_width to 51); +signal tlb_snoop_ack : std_ulogic; +signal mas0_0_atsel : std_ulogic; +signal mas0_0_esel : std_ulogic_vector(0 to 2); +signal mas0_0_hes : std_ulogic; +signal mas0_0_wq : std_ulogic_vector(0 to 1); +signal mas1_0_v : std_ulogic; +signal mas1_0_iprot : std_ulogic; +signal mas1_0_tid : std_ulogic_vector(0 to 13); +signal mas1_0_ind : std_ulogic; +signal mas1_0_ts : std_ulogic; +signal mas1_0_tsize : std_ulogic_vector(0 to 3); +signal mas2_0_epn : std_ulogic_vector(0 to 51); +signal mas2_0_wimge : std_ulogic_vector(0 to 4); +signal mas3_0_rpnl : std_ulogic_vector(32 to 52); +signal mas3_0_ubits : std_ulogic_vector(0 to 3); +signal mas3_0_usxwr : std_ulogic_vector(0 to 5); +signal mas5_0_sgs : std_ulogic; +signal mas5_0_slpid : std_ulogic_vector(0 to 7); +signal mas6_0_spid : std_ulogic_vector(0 to 13); +signal mas6_0_isize : std_ulogic_vector(0 to 3); +signal mas6_0_sind : std_ulogic; +signal mas6_0_sas : std_ulogic; +signal mas7_0_rpnu : std_ulogic_vector(22 to 31); +signal mas8_0_tgs : std_ulogic; +signal mas8_0_vf : std_ulogic; +signal mas8_0_tlpid : std_ulogic_vector(0 to 7); +signal mas0_1_atsel : std_ulogic; +signal mas0_1_esel : std_ulogic_vector(0 to 2); +signal mas0_1_hes : std_ulogic; +signal mas0_1_wq : std_ulogic_vector(0 to 1); +signal mas1_1_v : std_ulogic; +signal mas1_1_iprot : std_ulogic; +signal mas1_1_tid : std_ulogic_vector(0 to 13); +signal mas1_1_ind : std_ulogic; +signal mas1_1_ts : std_ulogic; +signal mas1_1_tsize : std_ulogic_vector(0 to 3); +signal mas2_1_epn : std_ulogic_vector(0 to 51); +signal mas2_1_wimge : std_ulogic_vector(0 to 4); +signal mas3_1_rpnl : std_ulogic_vector(32 to 52); +signal mas3_1_ubits : std_ulogic_vector(0 to 3); +signal mas3_1_usxwr : std_ulogic_vector(0 to 5); +signal mas5_1_sgs : std_ulogic; +signal mas5_1_slpid : std_ulogic_vector(0 to 7); +signal mas6_1_spid : std_ulogic_vector(0 to 13); +signal mas6_1_isize : std_ulogic_vector(0 to 3); +signal mas6_1_sind : std_ulogic; +signal mas6_1_sas : std_ulogic; +signal mas7_1_rpnu : std_ulogic_vector(22 to 31); +signal mas8_1_tgs : std_ulogic; +signal mas8_1_vf : std_ulogic; +signal mas8_1_tlpid : std_ulogic_vector(0 to 7); +signal mas0_2_atsel : std_ulogic; +signal mas0_2_esel : std_ulogic_vector(0 to 2); +signal mas0_2_hes : std_ulogic; +signal mas0_2_wq : std_ulogic_vector(0 to 1); +signal mas1_2_v : std_ulogic; +signal mas1_2_iprot : std_ulogic; +signal mas1_2_tid : std_ulogic_vector(0 to 13); +signal mas1_2_ind : std_ulogic; +signal mas1_2_ts : std_ulogic; +signal mas1_2_tsize : std_ulogic_vector(0 to 3); +signal mas2_2_epn : std_ulogic_vector(0 to 51); +signal mas2_2_wimge : std_ulogic_vector(0 to 4); +signal mas3_2_rpnl : std_ulogic_vector(32 to 52); +signal mas3_2_ubits : std_ulogic_vector(0 to 3); +signal mas3_2_usxwr : std_ulogic_vector(0 to 5); +signal mas5_2_sgs : std_ulogic; +signal mas5_2_slpid : std_ulogic_vector(0 to 7); +signal mas6_2_spid : std_ulogic_vector(0 to 13); +signal mas6_2_isize : std_ulogic_vector(0 to 3); +signal mas6_2_sind : std_ulogic; +signal mas6_2_sas : std_ulogic; +signal mas7_2_rpnu : std_ulogic_vector(22 to 31); +signal mas8_2_tgs : std_ulogic; +signal mas8_2_vf : std_ulogic; +signal mas8_2_tlpid : std_ulogic_vector(0 to 7); +signal mas0_3_atsel : std_ulogic; +signal mas0_3_esel : std_ulogic_vector(0 to 2); +signal mas0_3_hes : std_ulogic; +signal mas0_3_wq : std_ulogic_vector(0 to 1); +signal mas1_3_v : std_ulogic; +signal mas1_3_iprot : std_ulogic; +signal mas1_3_tid : std_ulogic_vector(0 to 13); +signal mas1_3_ind : std_ulogic; +signal mas1_3_ts : std_ulogic; +signal mas1_3_tsize : std_ulogic_vector(0 to 3); +signal mas2_3_epn : std_ulogic_vector(0 to 51); +signal mas2_3_wimge : std_ulogic_vector(0 to 4); +signal mas3_3_rpnl : std_ulogic_vector(32 to 52); +signal mas3_3_ubits : std_ulogic_vector(0 to 3); +signal mas3_3_usxwr : std_ulogic_vector(0 to 5); +signal mas5_3_sgs : std_ulogic; +signal mas5_3_slpid : std_ulogic_vector(0 to 7); +signal mas6_3_spid : std_ulogic_vector(0 to 13); +signal mas6_3_isize : std_ulogic_vector(0 to 3); +signal mas6_3_sind : std_ulogic; +signal mas6_3_sas : std_ulogic; +signal mas7_3_rpnu : std_ulogic_vector(22 to 31); +signal mas8_3_tgs : std_ulogic; +signal mas8_3_vf : std_ulogic; +signal mas8_3_tlpid : std_ulogic_vector(0 to 7); +signal mmucfg_lrat : std_ulogic; +signal mmucfg_twc : std_ulogic; +signal mmucsr0_tlb0fi : std_ulogic; +signal mmq_inval_tlb0fi_done : std_ulogic; +signal tlb0cfg_pt : std_ulogic; +signal tlb0cfg_ind : std_ulogic; +signal tlb0cfg_gtwe : std_ulogic; +signal tlb_mas0_esel : std_ulogic_vector(0 to 2); +signal tlb_mas1_v : std_ulogic; +signal tlb_mas1_iprot : std_ulogic; +signal tlb_mas1_tid : std_ulogic_vector(0 to pid_width-1); +signal tlb_mas1_tid_error : std_ulogic_vector(0 to pid_width-1); +signal tlb_mas1_ind : std_ulogic; +signal tlb_mas1_ts : std_ulogic; +signal tlb_mas1_ts_error : std_ulogic; +signal tlb_mas1_tsize : std_ulogic_vector(0 to 3); +signal tlb_mas2_epn : std_ulogic_vector(0 to 51); +signal tlb_mas2_epn_error : std_ulogic_vector(0 to 51); +signal tlb_mas2_wimge : std_ulogic_vector(0 to 4); +signal tlb_mas3_rpnl : std_ulogic_vector(32 to 51); +signal tlb_mas3_ubits : std_ulogic_vector(0 to 3); +signal tlb_mas3_usxwr : std_ulogic_vector(0 to 5); +signal tlb_mas6_spid : std_ulogic_vector(0 to pid_width-1); +signal tlb_mas6_isize : std_ulogic_vector(0 to 3); +signal tlb_mas6_sind : std_ulogic; +signal tlb_mas6_sas : std_ulogic; +signal tlb_mas7_rpnu : std_ulogic_vector(22 to 31); +signal tlb_mas8_tgs : std_ulogic; +signal tlb_mas8_vf : std_ulogic; +signal tlb_mas8_tlpid : std_ulogic_vector(0 to 7); +signal tlb_mmucr1_een : std_ulogic_vector(0 to 8); +signal tlb_mmucr1_we : std_ulogic; +signal tlb_mmucr3_thdid : std_ulogic_vector(0 to thdid_width-1); +signal tlb_mmucr3_resvattr : std_ulogic; +signal tlb_mmucr3_wlc : std_ulogic_vector(0 to 1); +signal tlb_mmucr3_class : std_ulogic_vector(0 to class_width-1); +signal tlb_mmucr3_extclass : std_ulogic_vector(0 to extclass_width-1); +signal tlb_mmucr3_rc : std_ulogic_vector(0 to 1); +signal tlb_mmucr3_x : std_ulogic; +signal tlb_mas_tlbre : std_ulogic; +signal tlb_mas_tlbsx_hit : std_ulogic; +signal tlb_mas_tlbsx_miss : std_ulogic; +signal tlb_mas_dtlb_error : std_ulogic; +signal tlb_mas_itlb_error : std_ulogic; +signal tlb_mas_thdid : std_ulogic_vector(0 to 3); +signal lrat_mas0_esel : std_ulogic_vector(0 to 2); +signal lrat_mas1_v : std_ulogic; +signal lrat_mas1_tsize : std_ulogic_vector(0 to 3); +signal lrat_mas2_epn : std_ulogic_vector(0 to 51); +signal lrat_mas3_rpnl : std_ulogic_vector(32 to 51); +signal lrat_mas7_rpnu : std_ulogic_vector(22 to 31); +signal lrat_mas8_tlpid : std_ulogic_vector(0 to lpid_width-1); +signal lrat_mmucr3_x : std_ulogic; +signal lrat_mas_tlbre : std_ulogic; +signal lrat_mas_tlbsx_hit : std_ulogic; +signal lrat_mas_tlbsx_miss : std_ulogic; +signal lrat_mas_thdid : std_ulogic_vector(0 to 3); +signal lrat_tag3_lpn : std_ulogic_vector(64-real_addr_width to 51); +signal lrat_tag3_rpn : std_ulogic_vector(64-real_addr_width to 51); +signal lrat_tag3_hit_status : std_ulogic_vector(0 to 3); +signal lrat_tag3_hit_entry : std_ulogic_vector(0 to lrat_num_entry_log2-1); +signal lrat_tag4_lpn : std_ulogic_vector(64-real_addr_width to 51); +signal lrat_tag4_rpn : std_ulogic_vector(64-real_addr_width to 51); +signal lrat_tag4_hit_status : std_ulogic_vector(0 to 3); +signal lrat_tag4_hit_entry : std_ulogic_vector(0 to lrat_num_entry_log2-1); +signal tlb_tag0_epn : std_ulogic_vector(52-epn_width to 51); +signal tlb_tag0_thdid : std_ulogic_vector(0 to thdid_width-1); +signal tlb_tag0_type : std_ulogic_vector(0 to 7); +signal tlb_tag0_lpid : std_ulogic_vector(0 to lpid_width-1); +signal tlb_tag0_atsel : std_ulogic; +signal tlb_tag0_size : std_ulogic_vector(0 to 3); +signal tlb_tag0_addr_cap : std_ulogic; +signal pte_tag0_lpn : std_ulogic_vector(64-real_addr_width to 51); +signal pte_tag0_lpid : std_ulogic_vector(0 to lpid_width-1); +signal tlb_lper_lpn : std_ulogic_vector(64-real_addr_width to 51); +signal tlb_lper_lps : std_ulogic_vector(60 to 63); +signal tlb_lper_we : std_ulogic_vector(0 to thdid_width-1); +signal ierat_req0_pid_sig : std_ulogic_vector(0 to pid_width-1); +signal ierat_req0_as_sig : std_ulogic; +signal ierat_req0_gs_sig : std_ulogic; +signal ierat_req0_epn_sig : std_ulogic_vector(0 to epn_width-1); +signal ierat_req0_thdid_sig : std_ulogic_vector(0 to thdid_width-1); +signal ierat_req0_valid_sig : std_ulogic; +signal ierat_req0_nonspec_sig : std_ulogic; +signal ierat_req1_pid_sig : std_ulogic_vector(0 to pid_width-1); +signal ierat_req1_as_sig : std_ulogic; +signal ierat_req1_gs_sig : std_ulogic; +signal ierat_req1_epn_sig : std_ulogic_vector(0 to epn_width-1); +signal ierat_req1_thdid_sig : std_ulogic_vector(0 to thdid_width-1); +signal ierat_req1_valid_sig : std_ulogic; +signal ierat_req1_nonspec_sig : std_ulogic; +signal ierat_req2_pid_sig : std_ulogic_vector(0 to pid_width-1); +signal ierat_req2_as_sig : std_ulogic; +signal ierat_req2_gs_sig : std_ulogic; +signal ierat_req2_epn_sig : std_ulogic_vector(0 to epn_width-1); +signal ierat_req2_thdid_sig : std_ulogic_vector(0 to thdid_width-1); +signal ierat_req2_valid_sig : std_ulogic; +signal ierat_req2_nonspec_sig : std_ulogic; +signal ierat_req3_pid_sig : std_ulogic_vector(0 to pid_width-1); +signal ierat_req3_as_sig : std_ulogic; +signal ierat_req3_gs_sig : std_ulogic; +signal ierat_req3_epn_sig : std_ulogic_vector(0 to epn_width-1); +signal ierat_req3_thdid_sig : std_ulogic_vector(0 to thdid_width-1); +signal ierat_req3_valid_sig : std_ulogic; +signal ierat_req3_nonspec_sig : std_ulogic; +signal ierat_iu4_pid_sig : std_ulogic_vector(0 to pid_width-1); +signal ierat_iu4_gs_sig : std_ulogic; +signal ierat_iu4_as_sig : std_ulogic; +signal ierat_iu4_epn_sig : std_ulogic_vector(0 to epn_width-1); +signal ierat_iu4_thdid_sig : std_ulogic_vector(0 to thdid_width-1); +signal ierat_iu4_valid_sig : std_ulogic; +signal derat_req0_lpid_sig : std_ulogic_vector(0 to lpid_width-1); +signal derat_req0_pid_sig : std_ulogic_vector(0 to pid_width-1); +signal derat_req0_as_sig : std_ulogic; +signal derat_req0_gs_sig : std_ulogic; +signal derat_req0_epn_sig : std_ulogic_vector(0 to epn_width-1); +signal derat_req0_thdid_sig : std_ulogic_vector(0 to thdid_width-1); +signal derat_req0_valid_sig : std_ulogic; +signal derat_req1_lpid_sig : std_ulogic_vector(0 to lpid_width-1); +signal derat_req1_pid_sig : std_ulogic_vector(0 to pid_width-1); +signal derat_req1_as_sig : std_ulogic; +signal derat_req1_gs_sig : std_ulogic; +signal derat_req1_epn_sig : std_ulogic_vector(0 to epn_width-1); +signal derat_req1_thdid_sig : std_ulogic_vector(0 to thdid_width-1); +signal derat_req1_valid_sig : std_ulogic; +signal derat_req2_lpid_sig : std_ulogic_vector(0 to lpid_width-1); +signal derat_req2_pid_sig : std_ulogic_vector(0 to pid_width-1); +signal derat_req2_as_sig : std_ulogic; +signal derat_req2_gs_sig : std_ulogic; +signal derat_req2_epn_sig : std_ulogic_vector(0 to epn_width-1); +signal derat_req2_thdid_sig : std_ulogic_vector(0 to thdid_width-1); +signal derat_req2_valid_sig : std_ulogic; +signal derat_req3_lpid_sig : std_ulogic_vector(0 to lpid_width-1); +signal derat_req3_pid_sig : std_ulogic_vector(0 to pid_width-1); +signal derat_req3_as_sig : std_ulogic; +signal derat_req3_gs_sig : std_ulogic; +signal derat_req3_epn_sig : std_ulogic_vector(0 to epn_width-1); +signal derat_req3_thdid_sig : std_ulogic_vector(0 to thdid_width-1); +signal derat_req3_valid_sig : std_ulogic; +signal derat_ex5_lpid_sig : std_ulogic_vector(0 to lpid_width-1); +signal derat_ex5_pid_sig : std_ulogic_vector(0 to pid_width-1); +signal derat_ex5_gs_sig : std_ulogic; +signal derat_ex5_as_sig : std_ulogic; +signal derat_ex5_epn_sig : std_ulogic_vector(0 to epn_width-1); +signal derat_ex5_thdid_sig : std_ulogic_vector(0 to thdid_width-1); +signal derat_ex5_valid_sig : std_ulogic; +signal tlb_cmp_perf_event_t0 : std_ulogic_vector(0 to 9); +signal tlb_cmp_perf_event_t1 : std_ulogic_vector(0 to 9); +signal tlb_cmp_perf_event_t2 : std_ulogic_vector(0 to 9); +signal tlb_cmp_perf_event_t3 : std_ulogic_vector(0 to 9); +signal tlb_cmp_perf_state : std_ulogic_vector(0 to 1); +signal tlb_cmp_perf_miss_direct : std_ulogic; +signal tlb_cmp_perf_hit_indirect : std_ulogic; +signal tlb_cmp_perf_hit_first_page : std_ulogic; +signal tlb_cmp_perf_ptereload_noexcep : std_ulogic; +signal tlb_cmp_perf_lrat_request : std_ulogic; +signal tlb_cmp_perf_lrat_miss : std_ulogic; +signal tlb_cmp_perf_pt_fault : std_ulogic; +signal tlb_cmp_perf_pt_inelig : std_ulogic; +signal tlb_ctl_perf_tlbwec_resv : std_ulogic; +signal tlb_ctl_perf_tlbwec_noresv : std_ulogic; +signal inval_perf_tlbilx : std_ulogic; +signal inval_perf_tlbivax : std_ulogic; +signal inval_perf_tlbivax_snoop : std_ulogic; +signal inval_perf_tlb_flush : std_ulogic; +----------- debug signals +signal spr_dbg_match_64b : std_ulogic; +signal spr_dbg_match_any_mmu : std_ulogic; +signal spr_dbg_match_any_mas : std_ulogic; +signal spr_dbg_match_pid : std_ulogic; +signal spr_dbg_match_lpidr : std_ulogic; +signal spr_dbg_match_mmucr0 : std_ulogic; +signal spr_dbg_match_mmucr1 : std_ulogic; +signal spr_dbg_match_mmucr2 : std_ulogic; +signal spr_dbg_match_mmucr3 : std_ulogic; +signal spr_dbg_match_mmucsr0 : std_ulogic; +signal spr_dbg_match_mmucfg : std_ulogic; +signal spr_dbg_match_tlb0cfg : std_ulogic; +signal spr_dbg_match_tlb0ps : std_ulogic; +signal spr_dbg_match_lratcfg : std_ulogic; +signal spr_dbg_match_lratps : std_ulogic; +signal spr_dbg_match_eptcfg : std_ulogic; +signal spr_dbg_match_lper : std_ulogic; +signal spr_dbg_match_lperu : std_ulogic; +signal spr_dbg_match_mas0 : std_ulogic; +signal spr_dbg_match_mas1 : std_ulogic; +signal spr_dbg_match_mas2 : std_ulogic; +signal spr_dbg_match_mas2u : std_ulogic; +signal spr_dbg_match_mas3 : std_ulogic; +signal spr_dbg_match_mas4 : std_ulogic; +signal spr_dbg_match_mas5 : std_ulogic; +signal spr_dbg_match_mas6 : std_ulogic; +signal spr_dbg_match_mas7 : std_ulogic; +signal spr_dbg_match_mas8 : std_ulogic; +signal spr_dbg_match_mas01_64b : std_ulogic; +signal spr_dbg_match_mas56_64b : std_ulogic; +signal spr_dbg_match_mas73_64b : std_ulogic; +signal spr_dbg_match_mas81_64b : std_ulogic; +signal spr_dbg_slowspr_val_int : std_ulogic; +signal spr_dbg_slowspr_rw_int : std_ulogic; +signal spr_dbg_slowspr_etid_int : std_ulogic_vector(0 to 1); +signal spr_dbg_slowspr_addr_int : std_ulogic_vector(0 to 9); +signal spr_dbg_slowspr_val_out : std_ulogic; +signal spr_dbg_slowspr_done_out : std_ulogic; +signal spr_dbg_slowspr_data_out : std_ulogic_vector(64-spr_data_width to 63); +signal inval_dbg_seq_q : std_ulogic_vector(0 to 4); +signal inval_dbg_seq_idle : std_ulogic; +signal inval_dbg_seq_snoop_inprogress : std_ulogic; +signal inval_dbg_seq_snoop_done : std_ulogic; +signal inval_dbg_seq_local_done : std_ulogic; +signal inval_dbg_seq_tlb0fi_done : std_ulogic; +signal inval_dbg_seq_tlbwe_snoop_done : std_ulogic; +signal inval_dbg_ex6_valid : std_ulogic; +signal inval_dbg_ex6_thdid : std_ulogic_vector(0 to 1); +signal inval_dbg_ex6_ttype : std_ulogic_vector(0 to 2); +signal inval_dbg_snoop_forme : std_ulogic; +signal inval_dbg_snoop_local_reject : std_ulogic; +signal inval_dbg_an_ac_back_inv_q : std_ulogic_vector(2 to 8); +signal inval_dbg_an_ac_back_inv_lpar_id_q : std_ulogic_vector(0 to 7); +signal inval_dbg_an_ac_back_inv_addr_q : std_ulogic_vector(22 to 63); +signal inval_dbg_snoop_valid_q : std_ulogic_vector(0 to 2); +signal inval_dbg_snoop_ack_q : std_ulogic_vector(0 to 2); +signal inval_dbg_snoop_attr_q : std_ulogic_vector(0 to 34); +signal inval_dbg_snoop_attr_tlb_spec_q : std_ulogic_vector(18 to 19); +signal inval_dbg_snoop_vpn_q : std_ulogic_vector(17 to 51); +signal inval_dbg_lsu_tokens_q : std_ulogic_vector(0 to 1); +signal tlb_req_dbg_ierat_iu5_valid_q : std_ulogic; +signal tlb_req_dbg_ierat_iu5_thdid : std_ulogic_vector(0 to 1); +signal tlb_req_dbg_ierat_iu5_state_q : std_ulogic_vector(0 to 3); +signal tlb_req_dbg_ierat_inptr_q : std_ulogic_vector(0 to 1); +signal tlb_req_dbg_ierat_outptr_q : std_ulogic_vector(0 to 1); +signal tlb_req_dbg_ierat_req_valid_q : std_ulogic_vector(0 to 3); +signal tlb_req_dbg_ierat_req_nonspec_q : std_ulogic_vector(0 to 3); +signal tlb_req_dbg_ierat_req_thdid : std_ulogic_vector(0 to 7); +signal tlb_req_dbg_ierat_req_dup_q : std_ulogic_vector(0 to 3); +signal tlb_req_dbg_derat_ex6_valid_q : std_ulogic; +signal tlb_req_dbg_derat_ex6_thdid : std_ulogic_vector(0 to 1); +signal tlb_req_dbg_derat_ex6_state_q : std_ulogic_vector(0 to 3); +signal tlb_req_dbg_derat_inptr_q : std_ulogic_vector(0 to 1); +signal tlb_req_dbg_derat_outptr_q : std_ulogic_vector(0 to 1); +signal tlb_req_dbg_derat_req_valid_q : std_ulogic_vector(0 to 3); +signal tlb_req_dbg_derat_req_thdid : std_ulogic_vector(0 to 7); +signal tlb_req_dbg_derat_req_ttype_q : std_ulogic_vector(0 to 7); +signal tlb_req_dbg_derat_req_dup_q : std_ulogic_vector(0 to 3); +signal tlb_ctl_dbg_seq_q : std_ulogic_vector(0 to 5); +signal tlb_ctl_dbg_seq_idle : std_ulogic; +signal tlb_ctl_dbg_seq_any_done_sig : std_ulogic; +signal tlb_ctl_dbg_seq_abort : std_ulogic; +signal tlb_ctl_dbg_any_tlb_req_sig : std_ulogic; +signal tlb_ctl_dbg_any_req_taken_sig : std_ulogic; +signal tlb_ctl_dbg_tag0_valid : std_ulogic; +signal tlb_ctl_dbg_tag0_thdid : std_ulogic_vector(0 to 1); +signal tlb_ctl_dbg_tag0_type : std_ulogic_vector(0 to 2); +signal tlb_ctl_dbg_tag0_wq : std_ulogic_vector(0 to 1); +signal tlb_ctl_dbg_tag0_gs : std_ulogic; +signal tlb_ctl_dbg_tag0_pr : std_ulogic; +signal tlb_ctl_dbg_tag0_atsel : std_ulogic; +signal tlb_ctl_dbg_tag5_tlb_write_q : std_ulogic_vector(0 to 3); +signal tlb_ctl_dbg_resv_valid : std_ulogic_vector(0 to 3); +signal tlb_ctl_dbg_set_resv : std_ulogic_vector(0 to 3); +signal tlb_ctl_dbg_resv_match_vec_q : std_ulogic_vector(0 to 3); +signal tlb_ctl_dbg_any_tag_flush_sig : std_ulogic; +signal tlb_ctl_dbg_resv0_tag0_lpid_match : std_ulogic; +signal tlb_ctl_dbg_resv0_tag0_pid_match : std_ulogic; +signal tlb_ctl_dbg_resv0_tag0_as_snoop_match : std_ulogic; +signal tlb_ctl_dbg_resv0_tag0_gs_snoop_match : std_ulogic; +signal tlb_ctl_dbg_resv0_tag0_as_tlbwe_match : std_ulogic; +signal tlb_ctl_dbg_resv0_tag0_gs_tlbwe_match : std_ulogic; +signal tlb_ctl_dbg_resv0_tag0_ind_match : std_ulogic; +signal tlb_ctl_dbg_resv0_tag0_epn_loc_match : std_ulogic; +signal tlb_ctl_dbg_resv0_tag0_epn_glob_match : std_ulogic; +signal tlb_ctl_dbg_resv0_tag0_class_match : std_ulogic; +signal tlb_ctl_dbg_resv1_tag0_lpid_match : std_ulogic; +signal tlb_ctl_dbg_resv1_tag0_pid_match : std_ulogic; +signal tlb_ctl_dbg_resv1_tag0_as_snoop_match : std_ulogic; +signal tlb_ctl_dbg_resv1_tag0_gs_snoop_match : std_ulogic; +signal tlb_ctl_dbg_resv1_tag0_as_tlbwe_match : std_ulogic; +signal tlb_ctl_dbg_resv1_tag0_gs_tlbwe_match : std_ulogic; +signal tlb_ctl_dbg_resv1_tag0_ind_match : std_ulogic; +signal tlb_ctl_dbg_resv1_tag0_epn_loc_match : std_ulogic; +signal tlb_ctl_dbg_resv1_tag0_epn_glob_match : std_ulogic; +signal tlb_ctl_dbg_resv1_tag0_class_match : std_ulogic; +signal tlb_ctl_dbg_resv2_tag0_lpid_match : std_ulogic; +signal tlb_ctl_dbg_resv2_tag0_pid_match : std_ulogic; +signal tlb_ctl_dbg_resv2_tag0_as_snoop_match : std_ulogic; +signal tlb_ctl_dbg_resv2_tag0_gs_snoop_match : std_ulogic; +signal tlb_ctl_dbg_resv2_tag0_as_tlbwe_match : std_ulogic; +signal tlb_ctl_dbg_resv2_tag0_gs_tlbwe_match : std_ulogic; +signal tlb_ctl_dbg_resv2_tag0_ind_match : std_ulogic; +signal tlb_ctl_dbg_resv2_tag0_epn_loc_match : std_ulogic; +signal tlb_ctl_dbg_resv2_tag0_epn_glob_match : std_ulogic; +signal tlb_ctl_dbg_resv2_tag0_class_match : std_ulogic; +signal tlb_ctl_dbg_resv3_tag0_lpid_match : std_ulogic; +signal tlb_ctl_dbg_resv3_tag0_pid_match : std_ulogic; +signal tlb_ctl_dbg_resv3_tag0_as_snoop_match : std_ulogic; +signal tlb_ctl_dbg_resv3_tag0_gs_snoop_match : std_ulogic; +signal tlb_ctl_dbg_resv3_tag0_as_tlbwe_match : std_ulogic; +signal tlb_ctl_dbg_resv3_tag0_gs_tlbwe_match : std_ulogic; +signal tlb_ctl_dbg_resv3_tag0_ind_match : std_ulogic; +signal tlb_ctl_dbg_resv3_tag0_epn_loc_match : std_ulogic; +signal tlb_ctl_dbg_resv3_tag0_epn_glob_match : std_ulogic; +signal tlb_ctl_dbg_resv3_tag0_class_match : std_ulogic; +signal tlb_ctl_dbg_clr_resv_q : std_ulogic_vector(0 to 3); +signal tlb_ctl_dbg_clr_resv_terms : std_ulogic_vector(0 to 3); +signal tlb_cmp_dbg_tag4 : std_ulogic_vector(0 to tlb_tag_width-1); +signal tlb_cmp_dbg_tag4_wayhit : std_ulogic_vector(0 to tlb_ways); +signal tlb_cmp_dbg_addr4 : std_ulogic_vector(0 to tlb_addr_width-1); +signal tlb_cmp_dbg_tag4_way : std_ulogic_vector(0 to tlb_way_width-1); +signal tlb_cmp_dbg_tag4_parerr : std_ulogic_vector(0 to 4); +signal tlb_cmp_dbg_tag4_lru_dataout_q : std_ulogic_vector(0 to lru_width-5); +signal tlb_cmp_dbg_tag5_tlb_datain_q : std_ulogic_vector(0 to tlb_way_width-1); +signal tlb_cmp_dbg_tag5_lru_datain_q : std_ulogic_vector(0 to lru_width-5); +signal tlb_cmp_dbg_tag5_lru_write : std_ulogic; +signal tlb_cmp_dbg_tag5_any_exception : std_ulogic; +signal tlb_cmp_dbg_tag5_except_type_q : std_ulogic_vector(0 to 3); +signal tlb_cmp_dbg_tag5_except_thdid_q : std_ulogic_vector(0 to 1); +signal tlb_cmp_dbg_tag5_erat_rel_val : std_ulogic_vector(0 to 9); +signal tlb_cmp_dbg_tag5_erat_rel_data : std_ulogic_vector(0 to 131); +signal tlb_cmp_dbg_erat_dup_q : std_ulogic_vector(0 to 19); +signal tlb_cmp_dbg_addr_enable : std_ulogic_vector(0 to 8); +signal tlb_cmp_dbg_pgsize_enable : std_ulogic; +signal tlb_cmp_dbg_class_enable : std_ulogic; +signal tlb_cmp_dbg_extclass_enable : std_ulogic_vector(0 to 1); +signal tlb_cmp_dbg_state_enable : std_ulogic_vector(0 to 1); +signal tlb_cmp_dbg_thdid_enable : std_ulogic; +signal tlb_cmp_dbg_pid_enable : std_ulogic; +signal tlb_cmp_dbg_lpid_enable : std_ulogic; +signal tlb_cmp_dbg_ind_enable : std_ulogic; +signal tlb_cmp_dbg_iprot_enable : std_ulogic; +signal tlb_cmp_dbg_way0_entry_v : std_ulogic; +signal tlb_cmp_dbg_way0_addr_match : std_ulogic; +signal tlb_cmp_dbg_way0_pgsize_match : std_ulogic; +signal tlb_cmp_dbg_way0_class_match : std_ulogic; +signal tlb_cmp_dbg_way0_extclass_match : std_ulogic; +signal tlb_cmp_dbg_way0_state_match : std_ulogic; +signal tlb_cmp_dbg_way0_thdid_match : std_ulogic; +signal tlb_cmp_dbg_way0_pid_match : std_ulogic; +signal tlb_cmp_dbg_way0_lpid_match : std_ulogic; +signal tlb_cmp_dbg_way0_ind_match : std_ulogic; +signal tlb_cmp_dbg_way0_iprot_match : std_ulogic; +signal tlb_cmp_dbg_way1_entry_v : std_ulogic; +signal tlb_cmp_dbg_way1_addr_match : std_ulogic; +signal tlb_cmp_dbg_way1_pgsize_match : std_ulogic; +signal tlb_cmp_dbg_way1_class_match : std_ulogic; +signal tlb_cmp_dbg_way1_extclass_match : std_ulogic; +signal tlb_cmp_dbg_way1_state_match : std_ulogic; +signal tlb_cmp_dbg_way1_thdid_match : std_ulogic; +signal tlb_cmp_dbg_way1_pid_match : std_ulogic; +signal tlb_cmp_dbg_way1_lpid_match : std_ulogic; +signal tlb_cmp_dbg_way1_ind_match : std_ulogic; +signal tlb_cmp_dbg_way1_iprot_match : std_ulogic; +signal tlb_cmp_dbg_way2_entry_v : std_ulogic; +signal tlb_cmp_dbg_way2_addr_match : std_ulogic; +signal tlb_cmp_dbg_way2_pgsize_match : std_ulogic; +signal tlb_cmp_dbg_way2_class_match : std_ulogic; +signal tlb_cmp_dbg_way2_extclass_match : std_ulogic; +signal tlb_cmp_dbg_way2_state_match : std_ulogic; +signal tlb_cmp_dbg_way2_thdid_match : std_ulogic; +signal tlb_cmp_dbg_way2_pid_match : std_ulogic; +signal tlb_cmp_dbg_way2_lpid_match : std_ulogic; +signal tlb_cmp_dbg_way2_ind_match : std_ulogic; +signal tlb_cmp_dbg_way2_iprot_match : std_ulogic; +signal tlb_cmp_dbg_way3_entry_v : std_ulogic; +signal tlb_cmp_dbg_way3_addr_match : std_ulogic; +signal tlb_cmp_dbg_way3_pgsize_match : std_ulogic; +signal tlb_cmp_dbg_way3_class_match : std_ulogic; +signal tlb_cmp_dbg_way3_extclass_match : std_ulogic; +signal tlb_cmp_dbg_way3_state_match : std_ulogic; +signal tlb_cmp_dbg_way3_thdid_match : std_ulogic; +signal tlb_cmp_dbg_way3_pid_match : std_ulogic; +signal tlb_cmp_dbg_way3_lpid_match : std_ulogic; +signal tlb_cmp_dbg_way3_ind_match : std_ulogic; +signal tlb_cmp_dbg_way3_iprot_match : std_ulogic; +signal lrat_dbg_tag1_addr_enable : std_ulogic; +signal lrat_dbg_tag2_matchline_q : std_ulogic_vector(0 to 7); +signal lrat_dbg_entry0_addr_match : std_ulogic; +signal lrat_dbg_entry0_lpid_match : std_ulogic; +signal lrat_dbg_entry0_entry_v : std_ulogic; +signal lrat_dbg_entry0_entry_x : std_ulogic; +signal lrat_dbg_entry0_size : std_ulogic_vector(0 to 3); +signal lrat_dbg_entry1_addr_match : std_ulogic; +signal lrat_dbg_entry1_lpid_match : std_ulogic; +signal lrat_dbg_entry1_entry_v : std_ulogic; +signal lrat_dbg_entry1_entry_x : std_ulogic; +signal lrat_dbg_entry1_size : std_ulogic_vector(0 to 3); +signal lrat_dbg_entry2_addr_match : std_ulogic; +signal lrat_dbg_entry2_lpid_match : std_ulogic; +signal lrat_dbg_entry2_entry_v : std_ulogic; +signal lrat_dbg_entry2_entry_x : std_ulogic; +signal lrat_dbg_entry2_size : std_ulogic_vector(0 to 3); +signal lrat_dbg_entry3_addr_match : std_ulogic; +signal lrat_dbg_entry3_lpid_match : std_ulogic; +signal lrat_dbg_entry3_entry_v : std_ulogic; +signal lrat_dbg_entry3_entry_x : std_ulogic; +signal lrat_dbg_entry3_size : std_ulogic_vector(0 to 3); +signal lrat_dbg_entry4_addr_match : std_ulogic; +signal lrat_dbg_entry4_lpid_match : std_ulogic; +signal lrat_dbg_entry4_entry_v : std_ulogic; +signal lrat_dbg_entry4_entry_x : std_ulogic; +signal lrat_dbg_entry4_size : std_ulogic_vector(0 to 3); +signal lrat_dbg_entry5_addr_match : std_ulogic; +signal lrat_dbg_entry5_lpid_match : std_ulogic; +signal lrat_dbg_entry5_entry_v : std_ulogic; +signal lrat_dbg_entry5_entry_x : std_ulogic; +signal lrat_dbg_entry5_size : std_ulogic_vector(0 to 3); +signal lrat_dbg_entry6_addr_match : std_ulogic; +signal lrat_dbg_entry6_lpid_match : std_ulogic; +signal lrat_dbg_entry6_entry_v : std_ulogic; +signal lrat_dbg_entry6_entry_x : std_ulogic; +signal lrat_dbg_entry6_size : std_ulogic_vector(0 to 3); +signal lrat_dbg_entry7_addr_match : std_ulogic; +signal lrat_dbg_entry7_lpid_match : std_ulogic; +signal lrat_dbg_entry7_entry_v : std_ulogic; +signal lrat_dbg_entry7_entry_x : std_ulogic; +signal lrat_dbg_entry7_size : std_ulogic_vector(0 to 3); +signal htw_dbg_seq_idle : std_ulogic; +signal htw_dbg_pte0_seq_idle : std_ulogic; +signal htw_dbg_pte1_seq_idle : std_ulogic; +signal htw_dbg_seq_q : std_ulogic_vector(0 to 1); +signal htw_dbg_inptr_q : std_ulogic_vector(0 to 1); +signal htw_dbg_pte0_seq_q : std_ulogic_vector(0 to 2); +signal htw_dbg_pte1_seq_q : std_ulogic_vector(0 to 2); +signal htw_dbg_ptereload_ptr_q : std_ulogic; +signal htw_dbg_lsuptr_q : std_ulogic_vector(0 to 1); +signal htw_dbg_req_valid_q : std_ulogic_vector(0 to 3); +signal htw_dbg_resv_valid_vec : std_ulogic_vector(0 to 3); +signal htw_dbg_tag4_clr_resv_q : std_ulogic_vector(0 to 3); +signal htw_dbg_tag4_clr_resv_terms : std_ulogic_vector(0 to 3); +signal htw_dbg_pte0_score_ptr_q : std_ulogic_vector(0 to 1); +signal htw_dbg_pte0_score_cl_offset_q : std_ulogic_vector(58 to 60); +signal htw_dbg_pte0_score_error_q : std_ulogic_vector(0 to 2); +signal htw_dbg_pte0_score_qwbeat_q : std_ulogic_vector(0 to 3); +signal htw_dbg_pte0_score_pending_q : std_ulogic; +signal htw_dbg_pte0_score_ibit_q : std_ulogic; +signal htw_dbg_pte0_score_dataval_q : std_ulogic; +signal htw_dbg_pte0_reld_for_me_tm1 : std_ulogic; +signal htw_dbg_pte1_score_ptr_q : std_ulogic_vector(0 to 1); +signal htw_dbg_pte1_score_cl_offset_q : std_ulogic_vector(58 to 60); +signal htw_dbg_pte1_score_error_q : std_ulogic_vector(0 to 2); +signal htw_dbg_pte1_score_qwbeat_q : std_ulogic_vector(0 to 3); +signal htw_dbg_pte1_score_pending_q : std_ulogic; +signal htw_dbg_pte1_score_ibit_q : std_ulogic; +signal htw_dbg_pte1_score_dataval_q : std_ulogic; +signal htw_dbg_pte1_reld_for_me_tm1 : std_ulogic; +-- power clock gating sigs +signal tlb_delayed_act : std_ulogic_vector(9 to 32); +signal unused_dc : std_ulogic_vector(0 to 70); +-- synopsys translate_off +-- synopsys translate_on +-- Pervasive +signal lcb_clkoff_dc_b : std_ulogic; +signal lcb_act_dis_dc : std_ulogic; +signal lcb_d_mode_dc : std_ulogic; +signal lcb_delay_lclkr_dc : std_ulogic_vector(0 to 4); +signal lcb_mpw1_dc_b : std_ulogic_vector(0 to 4); +signal lcb_mpw2_dc_b : std_ulogic; +signal g6t_gptr_lcb_clkoff_dc_b : std_ulogic; +signal g6t_gptr_lcb_act_dis_dc : std_ulogic; +signal g6t_gptr_lcb_d_mode_dc : std_ulogic; +signal g6t_gptr_lcb_delay_lclkr_dc : std_ulogic_vector(0 to 4); +signal g6t_gptr_lcb_mpw1_dc_b : std_ulogic_vector(0 to 4); +signal g6t_gptr_lcb_mpw2_dc_b : std_ulogic; +signal g8t_gptr_lcb_clkoff_dc_b : std_ulogic; +signal g8t_gptr_lcb_act_dis_dc : std_ulogic; +signal g8t_gptr_lcb_d_mode_dc : std_ulogic; +signal g8t_gptr_lcb_delay_lclkr_dc : std_ulogic_vector(0 to 4); +signal g8t_gptr_lcb_mpw1_dc_b : std_ulogic_vector(0 to 4); +signal g8t_gptr_lcb_mpw2_dc_b : std_ulogic; +signal pc_func_sl_thold_2 : std_ulogic_vector(0 to 1); +signal pc_func_slp_sl_thold_2 : std_ulogic_vector(0 to 1); +signal pc_func_slp_nsl_thold_2 : std_ulogic; +signal pc_fce_2 : std_ulogic; +signal pc_cfg_sl_thold_2 : std_ulogic; +signal pc_cfg_slp_sl_thold_2 : std_ulogic; +signal pc_sg_2 : std_ulogic_vector(0 to 1); +signal pc_sg_1 : std_ulogic_vector(0 to 1); +signal pc_sg_0 : std_ulogic_vector(0 to 1); +signal pc_func_sl_thold_0 : std_ulogic_vector(0 to 1); +signal pc_func_sl_thold_0_b : std_ulogic_vector(0 to 1); +signal pc_func_slp_sl_thold_0 : std_ulogic_vector(0 to 1); +signal pc_func_slp_sl_thold_0_b : std_ulogic_vector(0 to 1); +signal pc_abst_sl_thold_0 : std_ulogic; +signal pc_abst_slp_sl_thold_0 : std_ulogic; +signal pc_repr_sl_thold_0 : std_ulogic; +signal pc_time_sl_thold_0 : std_ulogic; +signal pc_ary_nsl_thold_0 : std_ulogic; +signal pc_ary_slp_nsl_thold_0 : std_ulogic; +signal pc_mm_bolt_sl_thold_0 : std_ulogic; +signal pc_mm_bo_enable_2 : std_ulogic; +signal pc_mm_abist_g8t_wenb_q : std_ulogic; +signal pc_mm_abist_g8t1p_renb_0_q : std_ulogic; +signal pc_mm_abist_di_0_q : std_ulogic_vector(0 to 3); +signal pc_mm_abist_g8t_bw_1_q : std_ulogic; +signal pc_mm_abist_g8t_bw_0_q : std_ulogic; +signal pc_mm_abist_waddr_0_q : std_ulogic_vector(0 to 9); +signal pc_mm_abist_raddr_0_q : std_ulogic_vector(0 to 9); +signal pc_mm_abist_wl128_comp_ena_q : std_ulogic; +signal pc_mm_abist_g8t_dcomp_q : std_ulogic_vector(0 to 3); +signal pc_mm_abist_dcomp_g6t_2r_q : std_ulogic_vector(0 to 3); +signal pc_mm_abist_di_g6t_2r_q : std_ulogic_vector(0 to 3); +signal pc_mm_abist_g6t_r_wb_q : std_ulogic; +signal time_scan_in_int : std_ulogic; +signal time_scan_out_int : std_ulogic; +signal func_scan_in_int : std_ulogic_vector(0 to 9); +signal func_scan_out_int : std_ulogic_vector(0 to 9); +signal repr_scan_in_int : std_ulogic; +signal repr_scan_out_int : std_ulogic; +signal abst_scan_in_int : std_ulogic_vector(0 to 1); +signal abst_scan_out_int : std_ulogic_vector(0 to 1); +signal bcfg_scan_in_int : std_ulogic; +signal bcfg_scan_out_int : std_ulogic; +signal ccfg_scan_in_int : std_ulogic; +signal ccfg_scan_out_int : std_ulogic; +signal dcfg_scan_in_int : std_ulogic; +signal dcfg_scan_out_int : std_ulogic; +signal siv_0 : std_ulogic_vector(0 to scan_right_0); +signal sov_0 : std_ulogic_vector(0 to scan_right_0); +signal siv_1 : std_ulogic_vector(0 to scan_right_1); +signal sov_1 : std_ulogic_vector(0 to scan_right_1); +signal bsiv : std_ulogic_vector(0 to boot_scan_right); +signal bsov : std_ulogic_vector(0 to boot_scan_right); +signal tidn : std_ulogic; +signal ac_an_psro_ringsig_b : std_ulogic; +begin +----------------------------------------------------------------------- +-- common stuff for tlb and erat-only modes +----------------------------------------------------------------------- +tidn <= '0'; +ac_an_lpar_id <= ac_an_lpar_id_sig; +mm_xu_lsu_lpidr <= lpidr_sig; +----------------------------------------------------------------------- +-- Invalidate Component Instantiation +----------------------------------------------------------------------- +mmq_inval: entity work.mmq_inval(mmq_inval) + generic map ( rs_data_width => rs_data_width, + epn_width => epn_width, + real_addr_width => real_addr_width, + lpid_width => lpid_width, + expand_type => expand_type ) + port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + tc_ccflush_dc => tc_ac_ccflush_dc, + tc_scan_dis_dc_b => tc_ac_scan_dis_dc_b, + tc_scan_diag_dc => tc_ac_scan_diag_dc, + tc_lbist_en_dc => tc_ac_lbist_en_dc, + + lcb_d_mode_dc => lcb_d_mode_dc, + lcb_clkoff_dc_b => lcb_clkoff_dc_b, + lcb_act_dis_dc => lcb_act_dis_dc, + lcb_mpw1_dc_b => lcb_mpw1_dc_b, + lcb_mpw2_dc_b => lcb_mpw2_dc_b, + lcb_delay_lclkr_dc => lcb_delay_lclkr_dc, + + ac_func_scan_in => siv_0(mmq_inval_offset), + ac_func_scan_out => sov_0(mmq_inval_offset), + + pc_sg_2 => pc_sg_2(0), + pc_func_sl_thold_2 => pc_func_sl_thold_2(0), + pc_func_slp_sl_thold_2 => pc_func_slp_sl_thold_2(0), + pc_func_slp_nsl_thold_2 => pc_func_slp_nsl_thold_2, + pc_fce_2 => pc_fce_2, + mmucr2_act_override => mmucr2_sig(7), + xu_mm_ccr2_notlb => xu_mm_hid_mmu_mode, + xu_mm_ccr2_notlb_b => xu_mm_ccr2_notlb_b, + + mm_iu_ierat_snoop_coming => mm_iu_ierat_snoop_coming, + mm_iu_ierat_snoop_val => mm_iu_ierat_snoop_val, + mm_iu_ierat_snoop_attr => mm_iu_ierat_snoop_attr, + mm_iu_ierat_snoop_vpn => mm_iu_ierat_snoop_vpn, + iu_mm_ierat_snoop_ack => iu_mm_ierat_snoop_ack, + + mm_xu_derat_snoop_coming => mm_xu_derat_snoop_coming, + mm_xu_derat_snoop_val => mm_xu_derat_snoop_val, + mm_xu_derat_snoop_attr => mm_xu_derat_snoop_attr, + mm_xu_derat_snoop_vpn => mm_xu_derat_snoop_vpn, + xu_mm_derat_snoop_ack => xu_mm_derat_snoop_ack, + + tlb_snoop_coming => tlb_snoop_coming, + tlb_snoop_val => tlb_snoop_val, + tlb_snoop_attr => tlb_snoop_attr, + tlb_snoop_vpn => tlb_snoop_vpn, + tlb_snoop_ack => tlb_snoop_ack, + + tlb_ctl_barrier_done => tlb_ctl_barrier_done_sig, + tlb_ctl_ex2_flush_req => tlb_ctl_ex2_flush_req_sig, + tlb_ctl_ex2_illeg_instr => tlb_ctl_ex2_illeg_instr_sig, + tlb_ctl_quiesce => tlb_ctl_quiesce_sig, + tlb_req_quiesce => tlb_req_quiesce_sig, + + mm_iu_barrier_done => mm_iu_barrier_done_sig, + mm_xu_ex3_flush_req => mm_xu_ex3_flush_req_sig, + mm_xu_illeg_instr => mm_xu_illeg_instr_sig, + mm_xu_local_snoop_reject => mm_xu_local_snoop_reject_sig, + + an_ac_back_inv => an_ac_back_inv, + an_ac_back_inv_target => an_ac_back_inv_target(2), + an_ac_back_inv_local => an_ac_back_inv_local, + an_ac_back_inv_lbit => an_ac_back_inv_lbit, + an_ac_back_inv_gs => an_ac_back_inv_gs, + an_ac_back_inv_ind => an_ac_back_inv_ind, + an_ac_back_inv_addr => an_ac_back_inv_addr, + an_ac_back_inv_lpar_id => an_ac_back_inv_lpar_id, + ac_an_back_inv_reject => ac_an_back_inv_reject, + ac_an_power_managed => ac_an_power_managed_imm, + mmucr0_0 => mmucr0_0_sig(2 to 19), + mmucr0_1 => mmucr0_1_sig(2 to 19), + mmucr0_2 => mmucr0_2_sig(2 to 19), + mmucr0_3 => mmucr0_3_sig(2 to 19), + mmucr1 => mmucr1_sig(12 to 19), + mmucr1_csinv => mmucr1_sig(4 to 5), + lpidr => lpidr_sig, + + mas5_0_sgs => mas5_0_sgs, + mas5_0_slpid => mas5_0_slpid, + mas6_0_spid => mas6_0_spid, + mas6_0_isize => mas6_0_isize, + mas6_0_sind => mas6_0_sind, + mas6_0_sas => mas6_0_sas, + mas5_1_sgs => mas5_1_sgs, + mas5_1_slpid => mas5_1_slpid, + mas6_1_spid => mas6_1_spid, + mas6_1_isize => mas6_1_isize, + mas6_1_sind => mas6_1_sind, + mas6_1_sas => mas6_1_sas, + mas5_2_sgs => mas5_2_sgs, + mas5_2_slpid => mas5_2_slpid, + mas6_2_spid => mas6_2_spid, + mas6_2_isize => mas6_2_isize, + mas6_2_sind => mas6_2_sind, + mas6_2_sas => mas6_2_sas, + mas5_3_sgs => mas5_3_sgs, + mas5_3_slpid => mas5_3_slpid, + mas6_3_spid => mas6_3_spid, + mas6_3_isize => mas6_3_isize, + mas6_3_sind => mas6_3_sind, + mas6_3_sas => mas6_3_sas, + mmucsr0_tlb0fi => mmucsr0_tlb0fi, + mmq_inval_tlb0fi_done => mmq_inval_tlb0fi_done, + + + xu_mm_rf1_val => xu_mm_rf1_val, + xu_mm_rf1_is_tlbivax => xu_mm_rf1_is_tlbivax, + xu_mm_rf1_is_tlbilx => xu_mm_rf1_is_tlbilx, + xu_mm_rf1_is_erativax => xu_mm_rf1_is_erativax, + xu_mm_rf1_is_eratilx => xu_mm_rf1_is_eratilx, + xu_mm_ex1_rs_is => xu_mm_ex1_rs_is, + xu_mm_ex1_is_isync => xu_mm_ex1_is_isync, + xu_mm_ex1_is_csync => xu_mm_ex1_is_csync, + xu_mm_ex2_eff_addr => xu_mm_ex2_eff_addr_sig, + xu_mm_rf1_t => xu_mm_rf1_t, + xu_mm_msr_gs => xu_mm_msr_gs, + xu_mm_msr_pr => xu_mm_msr_pr, + xu_mm_spr_epcr_dgtmi => xu_mm_spr_epcr_dgtmi, + xu_mm_epcr_dgtmi => xu_mm_epcr_dgtmi_sig, + xu_rf1_flush => xu_rf1_flush, + xu_ex1_flush => xu_ex1_flush, + xu_ex2_flush => xu_ex2_flush, + xu_ex3_flush => xu_ex3_flush, + xu_ex4_flush => xu_ex4_flush, + xu_ex5_flush => xu_ex5_flush, + xu_mm_lmq_stq_empty => xu_mm_lmq_stq_empty, + iu_mm_lmq_empty => iu_mm_lmq_empty, + mm_xu_hold_req => mm_xu_hold_req_sig, + xu_mm_hold_ack => xu_mm_hold_ack, + mm_xu_hold_done => mm_xu_hold_done_sig, + mm_xu_quiesce => mm_xu_quiesce_sig, + inval_perf_tlbilx => inval_perf_tlbilx, + inval_perf_tlbivax => inval_perf_tlbivax, + inval_perf_tlbivax_snoop => inval_perf_tlbivax_snoop, + inval_perf_tlb_flush => inval_perf_tlb_flush, + + htw_lsu_req_valid => htw_lsu_req_valid, + htw_lsu_thdid => htw_lsu_thdid, + htw_lsu_ttype => htw_lsu_ttype, + htw_lsu_wimge => htw_lsu_wimge, + htw_lsu_u => htw_lsu_u, + htw_lsu_addr => htw_lsu_addr, + htw_lsu_req_taken => htw_lsu_req_taken, + htw_quiesce => htw_quiesce_sig, + + tlbwe_back_inv_valid => tlbwe_back_inv_valid_sig, + tlbwe_back_inv_thdid => tlbwe_back_inv_thdid_sig, + tlbwe_back_inv_addr => tlbwe_back_inv_addr_sig, + tlbwe_back_inv_attr => tlbwe_back_inv_attr_sig, + tlbwe_back_inv_pending => tlbwe_back_inv_pending_sig, + tlb_tag5_write => tlb_tag5_write, + + mm_xu_lsu_req => mm_xu_lsu_req_sig, + mm_xu_lsu_ttype => mm_xu_lsu_ttype_sig, + mm_xu_lsu_wimge => mm_xu_lsu_wimge_sig, + mm_xu_lsu_u => mm_xu_lsu_u_sig, + mm_xu_lsu_addr => mm_xu_lsu_addr_sig, + mm_xu_lsu_lpid => mm_xu_lsu_lpid_sig, + mm_xu_lsu_gs => mm_xu_lsu_gs_sig, + mm_xu_lsu_ind => mm_xu_lsu_ind_sig, + mm_xu_lsu_lbit => mm_xu_lsu_lbit_sig, + xu_mm_lsu_token => xu_mm_lsu_token, + + inval_dbg_seq_q => inval_dbg_seq_q, + inval_dbg_seq_idle => inval_dbg_seq_idle, + inval_dbg_seq_snoop_inprogress => inval_dbg_seq_snoop_inprogress, + inval_dbg_seq_snoop_done => inval_dbg_seq_snoop_done, + inval_dbg_seq_local_done => inval_dbg_seq_local_done, + inval_dbg_seq_tlb0fi_done => inval_dbg_seq_tlb0fi_done, + inval_dbg_seq_tlbwe_snoop_done => inval_dbg_seq_tlbwe_snoop_done, + inval_dbg_ex6_valid => inval_dbg_ex6_valid, + inval_dbg_ex6_thdid => inval_dbg_ex6_thdid, + inval_dbg_ex6_ttype => inval_dbg_ex6_ttype, + inval_dbg_snoop_forme => inval_dbg_snoop_forme, + inval_dbg_snoop_local_reject => inval_dbg_snoop_local_reject, + inval_dbg_an_ac_back_inv_q => inval_dbg_an_ac_back_inv_q, + inval_dbg_an_ac_back_inv_lpar_id_q => inval_dbg_an_ac_back_inv_lpar_id_q, + inval_dbg_an_ac_back_inv_addr_q => inval_dbg_an_ac_back_inv_addr_q, + inval_dbg_snoop_valid_q => inval_dbg_snoop_valid_q, + inval_dbg_snoop_ack_q => inval_dbg_snoop_ack_q, + inval_dbg_snoop_attr_q => inval_dbg_snoop_attr_q, + inval_dbg_snoop_attr_tlb_spec_q => inval_dbg_snoop_attr_tlb_spec_q, + inval_dbg_snoop_vpn_q => inval_dbg_snoop_vpn_q, + inval_dbg_lsu_tokens_q => inval_dbg_lsu_tokens_q +); +-- End of mmq_inval component instantiation +----------------------------------------------------------------------- +-- Special Purpose Register Component Instantiation +----------------------------------------------------------------------- +mmq_spr: entity work.mmq_spr(mmq_spr) + generic map ( spr_data_width => spr_data_width, + expand_tlb_type => expand_tlb_type, + lpid_width => lpid_width, + real_addr_width => real_addr_width, + mmq_spr_cswitch_0to3 => mmq_spr_cswitch_0to3, + expand_type => expand_type ) + port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + tc_ccflush_dc => tc_ac_ccflush_dc, + tc_scan_dis_dc_b => tc_ac_scan_dis_dc_b, + tc_scan_diag_dc => tc_ac_scan_diag_dc, + tc_lbist_en_dc => tc_ac_lbist_en_dc, + + lcb_d_mode_dc => lcb_d_mode_dc, + lcb_clkoff_dc_b => lcb_clkoff_dc_b, + lcb_act_dis_dc => lcb_act_dis_dc, + lcb_mpw1_dc_b => lcb_mpw1_dc_b, + lcb_mpw2_dc_b => lcb_mpw2_dc_b, + lcb_delay_lclkr_dc => lcb_delay_lclkr_dc, + + ac_func_scan_in(0) => siv_0(mmq_spr_offset_0), + ac_func_scan_in(1) => func_scan_in_int(1), + ac_func_scan_out(0) => sov_0(mmq_spr_offset_0), + ac_func_scan_out(1) => func_scan_out_int(1), + ac_bcfg_scan_in => bsiv(mmq_spr_bcfg_offset), + ac_bcfg_scan_out => bsov(mmq_spr_bcfg_offset), + + +pc_sg_2 => pc_sg_2(0), + pc_func_sl_thold_2 => pc_func_sl_thold_2(0), + pc_func_slp_sl_thold_2 => pc_func_slp_sl_thold_2(0), + pc_func_slp_nsl_thold_2 => pc_func_slp_nsl_thold_2, + pc_cfg_sl_thold_2 => pc_cfg_sl_thold_2, + pc_cfg_slp_sl_thold_2 => pc_cfg_slp_sl_thold_2, + pc_fce_2 => pc_fce_2, + xu_mm_ccr2_notlb_b => xu_mm_ccr2_notlb_b(1), + mmucr2_act_override => mmucr2_sig(5 to 6), + + tlb_delayed_act => tlb_delayed_act(29 to 32), + + mm_iu_ierat_pid0 => mm_iu_ierat_pid0, + mm_iu_ierat_pid1 => mm_iu_ierat_pid1, + mm_iu_ierat_pid2 => mm_iu_ierat_pid2, + mm_iu_ierat_pid3 => mm_iu_ierat_pid3, + mm_iu_ierat_mmucr0_0 => mm_iu_ierat_mmucr0_0, + mm_iu_ierat_mmucr0_1 => mm_iu_ierat_mmucr0_1, + mm_iu_ierat_mmucr0_2 => mm_iu_ierat_mmucr0_2, + mm_iu_ierat_mmucr0_3 => mm_iu_ierat_mmucr0_3, + iu_mm_ierat_mmucr0 => iu_mm_ierat_mmucr0, + iu_mm_ierat_mmucr0_we => iu_mm_ierat_mmucr0_we, + mm_iu_ierat_mmucr1 => mm_iu_ierat_mmucr1, + iu_mm_ierat_mmucr1 => iu_mm_ierat_mmucr1, + iu_mm_ierat_mmucr1_we => iu_mm_ierat_mmucr1_we, + + mm_xu_derat_pid0 => mm_xu_derat_pid0, + mm_xu_derat_pid1 => mm_xu_derat_pid1, + mm_xu_derat_pid2 => mm_xu_derat_pid2, + mm_xu_derat_pid3 => mm_xu_derat_pid3, + mm_xu_derat_mmucr0_0 => mm_xu_derat_mmucr0_0, + mm_xu_derat_mmucr0_1 => mm_xu_derat_mmucr0_1, + mm_xu_derat_mmucr0_2 => mm_xu_derat_mmucr0_2, + mm_xu_derat_mmucr0_3 => mm_xu_derat_mmucr0_3, + xu_mm_derat_mmucr0 => xu_mm_derat_mmucr0, + xu_mm_derat_mmucr0_we => xu_mm_derat_mmucr0_we, + mm_xu_derat_mmucr1 => mm_xu_derat_mmucr1, + xu_mm_derat_mmucr1 => xu_mm_derat_mmucr1, + xu_mm_derat_mmucr1_we => xu_mm_derat_mmucr1_we, + + pid0 => pid0_sig, + pid1 => pid1_sig, + pid2 => pid2_sig, + pid3 => pid3_sig, + mmucr0_0 => mmucr0_0_sig, + mmucr0_1 => mmucr0_1_sig, + mmucr0_2 => mmucr0_2_sig, + mmucr0_3 => mmucr0_3_sig, + mmucr1 => mmucr1_sig, + mmucr2 => mmucr2_sig, + mmucr3_0 => mmucr3_0_sig, + mmucr3_1 => mmucr3_1_sig, + mmucr3_2 => mmucr3_2_sig, + mmucr3_3 => mmucr3_3_sig, + mmucfg_lrat => mmucfg_lrat, + mmucfg_twc => mmucfg_twc, + tlb0cfg_pt => tlb0cfg_pt, + tlb0cfg_ind => tlb0cfg_ind, + tlb0cfg_gtwe => tlb0cfg_gtwe, + mas0_0_atsel => mas0_0_atsel, + mas0_0_esel => mas0_0_esel, + mas0_0_hes => mas0_0_hes, + mas0_0_wq => mas0_0_wq, + mas1_0_v => mas1_0_v, + mas1_0_iprot => mas1_0_iprot, + mas1_0_tid => mas1_0_tid, + mas1_0_ind => mas1_0_ind, + mas1_0_ts => mas1_0_ts, + mas1_0_tsize => mas1_0_tsize, + mas2_0_epn => mas2_0_epn, + mas2_0_wimge => mas2_0_wimge, + mas3_0_rpnl => mas3_0_rpnl, + mas3_0_ubits => mas3_0_ubits, + mas3_0_usxwr => mas3_0_usxwr, + mas5_0_sgs => mas5_0_sgs, + mas5_0_slpid => mas5_0_slpid, + mas6_0_spid => mas6_0_spid, + mas6_0_isize => mas6_0_isize, + mas6_0_sind => mas6_0_sind, + mas6_0_sas => mas6_0_sas, + mas7_0_rpnu => mas7_0_rpnu, + mas8_0_tgs => mas8_0_tgs, + mas8_0_vf => mas8_0_vf, + mas8_0_tlpid => mas8_0_tlpid, + mas0_1_atsel => mas0_1_atsel, + mas0_1_esel => mas0_1_esel, + mas0_1_hes => mas0_1_hes, + mas0_1_wq => mas0_1_wq, + mas1_1_v => mas1_1_v, + mas1_1_iprot => mas1_1_iprot, + mas1_1_tid => mas1_1_tid, + mas1_1_ind => mas1_1_ind, + mas1_1_ts => mas1_1_ts, + mas1_1_tsize => mas1_1_tsize, + mas2_1_epn => mas2_1_epn, + mas2_1_wimge => mas2_1_wimge, + mas3_1_rpnl => mas3_1_rpnl, + mas3_1_ubits => mas3_1_ubits, + mas3_1_usxwr => mas3_1_usxwr, + mas5_1_sgs => mas5_1_sgs, + mas5_1_slpid => mas5_1_slpid, + mas6_1_spid => mas6_1_spid, + mas6_1_isize => mas6_1_isize, + mas6_1_sind => mas6_1_sind, + mas6_1_sas => mas6_1_sas, + mas7_1_rpnu => mas7_1_rpnu, + mas8_1_tgs => mas8_1_tgs, + mas8_1_vf => mas8_1_vf, + mas8_1_tlpid => mas8_1_tlpid, + mas0_2_atsel => mas0_2_atsel, + mas0_2_esel => mas0_2_esel, + mas0_2_hes => mas0_2_hes, + mas0_2_wq => mas0_2_wq, + mas1_2_v => mas1_2_v, + mas1_2_iprot => mas1_2_iprot, + mas1_2_tid => mas1_2_tid, + mas1_2_ind => mas1_2_ind, + mas1_2_ts => mas1_2_ts, + mas1_2_tsize => mas1_2_tsize, + mas2_2_epn => mas2_2_epn, + mas2_2_wimge => mas2_2_wimge, + mas3_2_rpnl => mas3_2_rpnl, + mas3_2_ubits => mas3_2_ubits, + mas3_2_usxwr => mas3_2_usxwr, + mas5_2_sgs => mas5_2_sgs, + mas5_2_slpid => mas5_2_slpid, + mas6_2_spid => mas6_2_spid, + mas6_2_isize => mas6_2_isize, + mas6_2_sind => mas6_2_sind, + mas6_2_sas => mas6_2_sas, + mas7_2_rpnu => mas7_2_rpnu, + mas8_2_tgs => mas8_2_tgs, + mas8_2_vf => mas8_2_vf, + mas8_2_tlpid => mas8_2_tlpid, + mas0_3_atsel => mas0_3_atsel, + mas0_3_esel => mas0_3_esel, + mas0_3_hes => mas0_3_hes, + mas0_3_wq => mas0_3_wq, + mas1_3_v => mas1_3_v, + mas1_3_iprot => mas1_3_iprot, + mas1_3_tid => mas1_3_tid, + mas1_3_ind => mas1_3_ind, + mas1_3_ts => mas1_3_ts, + mas1_3_tsize => mas1_3_tsize, + mas2_3_epn => mas2_3_epn, + mas2_3_wimge => mas2_3_wimge, + mas3_3_rpnl => mas3_3_rpnl, + mas3_3_ubits => mas3_3_ubits, + mas3_3_usxwr => mas3_3_usxwr, + mas5_3_sgs => mas5_3_sgs, + mas5_3_slpid => mas5_3_slpid, + mas6_3_spid => mas6_3_spid, + mas6_3_isize => mas6_3_isize, + mas6_3_sind => mas6_3_sind, + mas6_3_sas => mas6_3_sas, + mas7_3_rpnu => mas7_3_rpnu, + mas8_3_tgs => mas8_3_tgs, + mas8_3_vf => mas8_3_vf, + mas8_3_tlpid => mas8_3_tlpid, + tlb_mas0_esel => tlb_mas0_esel, + tlb_mas1_v => tlb_mas1_v, + tlb_mas1_iprot => tlb_mas1_iprot, + tlb_mas1_tid => tlb_mas1_tid, + tlb_mas1_tid_error => tlb_mas1_tid_error, + tlb_mas1_ind => tlb_mas1_ind, + tlb_mas1_ts => tlb_mas1_ts, + tlb_mas1_ts_error => tlb_mas1_ts_error, + tlb_mas1_tsize => tlb_mas1_tsize, + tlb_mas2_epn => tlb_mas2_epn, + tlb_mas2_epn_error => tlb_mas2_epn_error, + tlb_mas2_wimge => tlb_mas2_wimge, + tlb_mas3_rpnl => tlb_mas3_rpnl, + tlb_mas3_ubits => tlb_mas3_ubits, + tlb_mas3_usxwr => tlb_mas3_usxwr, + tlb_mas6_spid => tlb_mas6_spid, + tlb_mas6_isize => tlb_mas6_isize, + tlb_mas6_sind => tlb_mas6_sind, + tlb_mas6_sas => tlb_mas6_sas, + tlb_mas7_rpnu => tlb_mas7_rpnu, + tlb_mas8_tgs => tlb_mas8_tgs, + tlb_mas8_vf => tlb_mas8_vf, + tlb_mas8_tlpid => tlb_mas8_tlpid, + + tlb_mmucr1_een => tlb_mmucr1_een, + tlb_mmucr1_we => tlb_mmucr1_we, + tlb_mmucr3_thdid => tlb_mmucr3_thdid, + tlb_mmucr3_resvattr => tlb_mmucr3_resvattr, + tlb_mmucr3_wlc => tlb_mmucr3_wlc, + tlb_mmucr3_class => tlb_mmucr3_class, + tlb_mmucr3_extclass => tlb_mmucr3_extclass, + tlb_mmucr3_rc => tlb_mmucr3_rc, + tlb_mmucr3_x => tlb_mmucr3_x, + tlb_mas_tlbre => tlb_mas_tlbre, + tlb_mas_tlbsx_hit => tlb_mas_tlbsx_hit, + tlb_mas_tlbsx_miss => tlb_mas_tlbsx_miss, + tlb_mas_dtlb_error => tlb_mas_dtlb_error, + tlb_mas_itlb_error => tlb_mas_itlb_error, + tlb_mas_thdid => tlb_mas_thdid, + + mmucsr0_tlb0fi => mmucsr0_tlb0fi, + mmq_inval_tlb0fi_done => mmq_inval_tlb0fi_done, + + lrat_mmucr3_x => lrat_mmucr3_x, + lrat_mas0_esel => lrat_mas0_esel, + lrat_mas1_v => lrat_mas1_v, + lrat_mas1_tsize => lrat_mas1_tsize, + lrat_mas2_epn => lrat_mas2_epn, + lrat_mas3_rpnl => lrat_mas3_rpnl, + lrat_mas7_rpnu => lrat_mas7_rpnu, + lrat_mas8_tlpid => lrat_mas8_tlpid, + lrat_mas_tlbre => lrat_mas_tlbre, + lrat_mas_tlbsx_hit => lrat_mas_tlbsx_hit, + lrat_mas_tlbsx_miss => lrat_mas_tlbsx_miss, + lrat_mas_thdid => lrat_mas_thdid, + lrat_tag4_hit_entry => lrat_tag4_hit_entry, + + tlb_lper_lpn => tlb_lper_lpn, + tlb_lper_lps => tlb_lper_lps, + tlb_lper_we => tlb_lper_we, + + lpidr => lpidr_sig, + ac_an_lpar_id => ac_an_lpar_id_sig, + + spr_dbg_match_64b => spr_dbg_match_64b, + spr_dbg_match_any_mmu => spr_dbg_match_any_mmu, + spr_dbg_match_any_mas => spr_dbg_match_any_mas, + spr_dbg_match_pid => spr_dbg_match_pid, + spr_dbg_match_lpidr => spr_dbg_match_lpidr, + spr_dbg_match_mmucr0 => spr_dbg_match_mmucr0, + spr_dbg_match_mmucr1 => spr_dbg_match_mmucr1, + spr_dbg_match_mmucr2 => spr_dbg_match_mmucr2, + spr_dbg_match_mmucr3 => spr_dbg_match_mmucr3, + + spr_dbg_match_mmucsr0 => spr_dbg_match_mmucsr0, + spr_dbg_match_mmucfg => spr_dbg_match_mmucfg, + spr_dbg_match_tlb0cfg => spr_dbg_match_tlb0cfg, + spr_dbg_match_tlb0ps => spr_dbg_match_tlb0ps, + spr_dbg_match_lratcfg => spr_dbg_match_lratcfg, + spr_dbg_match_lratps => spr_dbg_match_lratps, + spr_dbg_match_eptcfg => spr_dbg_match_eptcfg, + spr_dbg_match_lper => spr_dbg_match_lper, + spr_dbg_match_lperu => spr_dbg_match_lperu, + + spr_dbg_match_mas0 => spr_dbg_match_mas0, + spr_dbg_match_mas1 => spr_dbg_match_mas1, + spr_dbg_match_mas2 => spr_dbg_match_mas2, + spr_dbg_match_mas2u => spr_dbg_match_mas2u, + spr_dbg_match_mas3 => spr_dbg_match_mas3, + spr_dbg_match_mas4 => spr_dbg_match_mas4, + spr_dbg_match_mas5 => spr_dbg_match_mas5, + spr_dbg_match_mas6 => spr_dbg_match_mas6, + spr_dbg_match_mas7 => spr_dbg_match_mas7, + spr_dbg_match_mas8 => spr_dbg_match_mas8, + spr_dbg_match_mas01_64b => spr_dbg_match_mas01_64b, + spr_dbg_match_mas56_64b => spr_dbg_match_mas56_64b, + spr_dbg_match_mas73_64b => spr_dbg_match_mas73_64b, + spr_dbg_match_mas81_64b => spr_dbg_match_mas81_64b, + + spr_dbg_slowspr_val_int => spr_dbg_slowspr_val_int, + spr_dbg_slowspr_rw_int => spr_dbg_slowspr_rw_int, + spr_dbg_slowspr_etid_int => spr_dbg_slowspr_etid_int, + spr_dbg_slowspr_addr_int => spr_dbg_slowspr_addr_int, + spr_dbg_slowspr_val_out => spr_dbg_slowspr_val_out, + spr_dbg_slowspr_done_out => spr_dbg_slowspr_done_out, + spr_dbg_slowspr_data_out => spr_dbg_slowspr_data_out, + + xu_mm_slowspr_val => slowspr_val_in, + xu_mm_slowspr_rw => slowspr_rw_in, + xu_mm_slowspr_etid => slowspr_etid_in, + xu_mm_slowspr_addr => slowspr_addr_in, + xu_mm_slowspr_data => slowspr_data_in, + xu_mm_slowspr_done => slowspr_done_in, + + mm_iu_slowspr_val => slowspr_val_out, + mm_iu_slowspr_rw => slowspr_rw_out, + mm_iu_slowspr_etid => slowspr_etid_out, + mm_iu_slowspr_addr => slowspr_addr_out, + mm_iu_slowspr_data => slowspr_data_out, + mm_iu_slowspr_done => slowspr_done_out + +); +-- End of mmq_spr component instantiation +----------------------------------------------------------------------- +-- Debug Trace component instantiation +----------------------------------------------------------------------- +mmq_dbg: entity work.mmq_dbg(mmq_dbg) + generic map ( tlb_tag_width => tlb_tag_width, + expand_type => expand_type ) + port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_func_slp_sl_thold_2 => pc_func_slp_sl_thold_2(0), + pc_func_slp_nsl_thold_2 => pc_func_slp_nsl_thold_2, + pc_sg_2 => pc_sg_2(0), + pc_fce_2 => pc_fce_2, + tc_ac_ccflush_dc => tc_ac_ccflush_dc, + lcb_clkoff_dc_b => lcb_clkoff_dc_b, + lcb_act_dis_dc => lcb_act_dis_dc, + lcb_d_mode_dc => lcb_d_mode_dc, + lcb_delay_lclkr_dc => lcb_delay_lclkr_dc(0), + lcb_mpw1_dc_b => lcb_mpw1_dc_b(0), + lcb_mpw2_dc_b => lcb_mpw2_dc_b, + scan_in => siv_1(mmq_dbg_offset), + scan_out => sov_1(mmq_dbg_offset), + + mmucr2 => mmucr2_sig(8 to 11), + pc_mm_trace_bus_enable => pc_mm_trace_bus_enable, + pc_mm_debug_mux1_ctrls => pc_mm_debug_mux1_ctrls, + + debug_bus_in => debug_bus_in, + trace_triggers_in => trace_triggers_in, + + debug_bus_out => debug_bus_out, + debug_bus_out_int => debug_bus_out_int, + trace_triggers_out => trace_triggers_out, + + spr_dbg_match_64b => spr_dbg_match_64b, + spr_dbg_match_any_mmu => spr_dbg_match_any_mmu, + spr_dbg_match_any_mas => spr_dbg_match_any_mas, + spr_dbg_match_pid => spr_dbg_match_pid, + spr_dbg_match_lpidr => spr_dbg_match_lpidr, + spr_dbg_match_mmucr0 => spr_dbg_match_mmucr0, + spr_dbg_match_mmucr1 => spr_dbg_match_mmucr1, + spr_dbg_match_mmucr2 => spr_dbg_match_mmucr2, + spr_dbg_match_mmucr3 => spr_dbg_match_mmucr3, + + spr_dbg_match_mmucsr0 => spr_dbg_match_mmucsr0, + spr_dbg_match_mmucfg => spr_dbg_match_mmucfg, + spr_dbg_match_tlb0cfg => spr_dbg_match_tlb0cfg, + spr_dbg_match_tlb0ps => spr_dbg_match_tlb0ps, + spr_dbg_match_lratcfg => spr_dbg_match_lratcfg, + spr_dbg_match_lratps => spr_dbg_match_lratps, + spr_dbg_match_eptcfg => spr_dbg_match_eptcfg, + spr_dbg_match_lper => spr_dbg_match_lper, + spr_dbg_match_lperu => spr_dbg_match_lperu, + + spr_dbg_match_mas0 => spr_dbg_match_mas0, + spr_dbg_match_mas1 => spr_dbg_match_mas1, + spr_dbg_match_mas2 => spr_dbg_match_mas2, + spr_dbg_match_mas2u => spr_dbg_match_mas2u, + spr_dbg_match_mas3 => spr_dbg_match_mas3, + spr_dbg_match_mas4 => spr_dbg_match_mas4, + spr_dbg_match_mas5 => spr_dbg_match_mas5, + spr_dbg_match_mas6 => spr_dbg_match_mas6, + spr_dbg_match_mas7 => spr_dbg_match_mas7, + spr_dbg_match_mas8 => spr_dbg_match_mas8, + spr_dbg_match_mas01_64b => spr_dbg_match_mas01_64b, + spr_dbg_match_mas56_64b => spr_dbg_match_mas56_64b, + spr_dbg_match_mas73_64b => spr_dbg_match_mas73_64b, + spr_dbg_match_mas81_64b => spr_dbg_match_mas81_64b, + + spr_dbg_slowspr_val_int => spr_dbg_slowspr_val_int, + spr_dbg_slowspr_rw_int => spr_dbg_slowspr_rw_int, + spr_dbg_slowspr_etid_int => spr_dbg_slowspr_etid_int, + spr_dbg_slowspr_addr_int => spr_dbg_slowspr_addr_int, + spr_dbg_slowspr_val_out => spr_dbg_slowspr_val_out, + spr_dbg_slowspr_done_out => spr_dbg_slowspr_done_out, + spr_dbg_slowspr_data_out => spr_dbg_slowspr_data_out, + inval_dbg_seq_q => inval_dbg_seq_q, + inval_dbg_seq_idle => inval_dbg_seq_idle, + inval_dbg_seq_snoop_inprogress => inval_dbg_seq_snoop_inprogress, + inval_dbg_seq_snoop_done => inval_dbg_seq_snoop_done, + inval_dbg_seq_local_done => inval_dbg_seq_local_done, + inval_dbg_seq_tlb0fi_done => inval_dbg_seq_tlb0fi_done, + inval_dbg_seq_tlbwe_snoop_done => inval_dbg_seq_tlbwe_snoop_done, + inval_dbg_ex6_valid => inval_dbg_ex6_valid, + inval_dbg_ex6_thdid => inval_dbg_ex6_thdid, + inval_dbg_ex6_ttype => inval_dbg_ex6_ttype, + inval_dbg_snoop_forme => inval_dbg_snoop_forme, + inval_dbg_snoop_local_reject => inval_dbg_snoop_local_reject, + inval_dbg_an_ac_back_inv_q => inval_dbg_an_ac_back_inv_q, + inval_dbg_an_ac_back_inv_lpar_id_q => inval_dbg_an_ac_back_inv_lpar_id_q, + inval_dbg_an_ac_back_inv_addr_q => inval_dbg_an_ac_back_inv_addr_q, + inval_dbg_snoop_valid_q => inval_dbg_snoop_valid_q, + inval_dbg_snoop_ack_q => inval_dbg_snoop_ack_q, + inval_dbg_snoop_attr_q => inval_dbg_snoop_attr_q, + inval_dbg_snoop_attr_tlb_spec_q => inval_dbg_snoop_attr_tlb_spec_q, + inval_dbg_snoop_vpn_q => inval_dbg_snoop_vpn_q, + inval_dbg_lsu_tokens_q => inval_dbg_lsu_tokens_q, + tlb_req_dbg_ierat_iu5_valid_q => tlb_req_dbg_ierat_iu5_valid_q, + tlb_req_dbg_ierat_iu5_thdid => tlb_req_dbg_ierat_iu5_thdid, + tlb_req_dbg_ierat_iu5_state_q => tlb_req_dbg_ierat_iu5_state_q, + tlb_req_dbg_ierat_inptr_q => tlb_req_dbg_ierat_inptr_q, + tlb_req_dbg_ierat_outptr_q => tlb_req_dbg_ierat_outptr_q, + tlb_req_dbg_ierat_req_valid_q => tlb_req_dbg_ierat_req_valid_q, + tlb_req_dbg_ierat_req_nonspec_q => tlb_req_dbg_ierat_req_nonspec_q, + tlb_req_dbg_ierat_req_thdid => tlb_req_dbg_ierat_req_thdid, + tlb_req_dbg_ierat_req_dup_q => tlb_req_dbg_ierat_req_dup_q, + tlb_req_dbg_derat_ex6_valid_q => tlb_req_dbg_derat_ex6_valid_q, + tlb_req_dbg_derat_ex6_thdid => tlb_req_dbg_derat_ex6_thdid, + tlb_req_dbg_derat_ex6_state_q => tlb_req_dbg_derat_ex6_state_q, + tlb_req_dbg_derat_inptr_q => tlb_req_dbg_derat_inptr_q, + tlb_req_dbg_derat_outptr_q => tlb_req_dbg_derat_outptr_q, + tlb_req_dbg_derat_req_valid_q => tlb_req_dbg_derat_req_valid_q, + tlb_req_dbg_derat_req_thdid => tlb_req_dbg_derat_req_thdid, + tlb_req_dbg_derat_req_ttype_q => tlb_req_dbg_derat_req_ttype_q, + tlb_req_dbg_derat_req_dup_q => tlb_req_dbg_derat_req_dup_q, + + tlb_ctl_dbg_seq_q => tlb_ctl_dbg_seq_q, + tlb_ctl_dbg_seq_idle => tlb_ctl_dbg_seq_idle, + tlb_ctl_dbg_seq_any_done_sig => tlb_ctl_dbg_seq_any_done_sig, + tlb_ctl_dbg_seq_abort => tlb_ctl_dbg_seq_abort, + tlb_ctl_dbg_any_tlb_req_sig => tlb_ctl_dbg_any_tlb_req_sig, + tlb_ctl_dbg_any_req_taken_sig => tlb_ctl_dbg_any_req_taken_sig, + tlb_ctl_dbg_tag0_valid => tlb_ctl_dbg_tag0_valid, + tlb_ctl_dbg_tag0_thdid => tlb_ctl_dbg_tag0_thdid, + tlb_ctl_dbg_tag0_type => tlb_ctl_dbg_tag0_type, + tlb_ctl_dbg_tag0_wq => tlb_ctl_dbg_tag0_wq, + tlb_ctl_dbg_tag0_gs => tlb_ctl_dbg_tag0_gs, + tlb_ctl_dbg_tag0_pr => tlb_ctl_dbg_tag0_pr, + tlb_ctl_dbg_tag0_atsel => tlb_ctl_dbg_tag0_atsel, + tlb_ctl_dbg_tag5_tlb_write_q => tlb_ctl_dbg_tag5_tlb_write_q, + tlb_ctl_dbg_resv_valid => tlb_ctl_dbg_resv_valid, + tlb_ctl_dbg_set_resv => tlb_ctl_dbg_set_resv, + tlb_ctl_dbg_resv_match_vec_q => tlb_ctl_dbg_resv_match_vec_q, + tlb_ctl_dbg_any_tag_flush_sig => tlb_ctl_dbg_any_tag_flush_sig, + tlb_ctl_dbg_resv0_tag0_lpid_match => tlb_ctl_dbg_resv0_tag0_lpid_match, + tlb_ctl_dbg_resv0_tag0_pid_match => tlb_ctl_dbg_resv0_tag0_pid_match, + tlb_ctl_dbg_resv0_tag0_as_snoop_match => tlb_ctl_dbg_resv0_tag0_as_snoop_match, + tlb_ctl_dbg_resv0_tag0_gs_snoop_match => tlb_ctl_dbg_resv0_tag0_gs_snoop_match, + tlb_ctl_dbg_resv0_tag0_as_tlbwe_match => tlb_ctl_dbg_resv0_tag0_as_tlbwe_match, + tlb_ctl_dbg_resv0_tag0_gs_tlbwe_match => tlb_ctl_dbg_resv0_tag0_gs_tlbwe_match, + tlb_ctl_dbg_resv0_tag0_ind_match => tlb_ctl_dbg_resv0_tag0_ind_match, + tlb_ctl_dbg_resv0_tag0_epn_loc_match => tlb_ctl_dbg_resv0_tag0_epn_loc_match, + tlb_ctl_dbg_resv0_tag0_epn_glob_match => tlb_ctl_dbg_resv0_tag0_epn_glob_match, + tlb_ctl_dbg_resv0_tag0_class_match => tlb_ctl_dbg_resv0_tag0_class_match, + tlb_ctl_dbg_resv1_tag0_lpid_match => tlb_ctl_dbg_resv1_tag0_lpid_match, + tlb_ctl_dbg_resv1_tag0_pid_match => tlb_ctl_dbg_resv1_tag0_pid_match, + tlb_ctl_dbg_resv1_tag0_as_snoop_match => tlb_ctl_dbg_resv1_tag0_as_snoop_match, + tlb_ctl_dbg_resv1_tag0_gs_snoop_match => tlb_ctl_dbg_resv1_tag0_gs_snoop_match, + tlb_ctl_dbg_resv1_tag0_as_tlbwe_match => tlb_ctl_dbg_resv1_tag0_as_tlbwe_match, + tlb_ctl_dbg_resv1_tag0_gs_tlbwe_match => tlb_ctl_dbg_resv1_tag0_gs_tlbwe_match, + tlb_ctl_dbg_resv1_tag0_ind_match => tlb_ctl_dbg_resv1_tag0_ind_match, + tlb_ctl_dbg_resv1_tag0_epn_loc_match => tlb_ctl_dbg_resv1_tag0_epn_loc_match, + tlb_ctl_dbg_resv1_tag0_epn_glob_match => tlb_ctl_dbg_resv1_tag0_epn_glob_match, + tlb_ctl_dbg_resv1_tag0_class_match => tlb_ctl_dbg_resv1_tag0_class_match , + tlb_ctl_dbg_resv2_tag0_lpid_match => tlb_ctl_dbg_resv2_tag0_lpid_match, + tlb_ctl_dbg_resv2_tag0_pid_match => tlb_ctl_dbg_resv2_tag0_pid_match, + tlb_ctl_dbg_resv2_tag0_as_snoop_match => tlb_ctl_dbg_resv2_tag0_as_snoop_match, + tlb_ctl_dbg_resv2_tag0_gs_snoop_match => tlb_ctl_dbg_resv2_tag0_gs_snoop_match, + tlb_ctl_dbg_resv2_tag0_as_tlbwe_match => tlb_ctl_dbg_resv2_tag0_as_tlbwe_match, + tlb_ctl_dbg_resv2_tag0_gs_tlbwe_match => tlb_ctl_dbg_resv2_tag0_gs_tlbwe_match, + tlb_ctl_dbg_resv2_tag0_ind_match => tlb_ctl_dbg_resv2_tag0_ind_match, + tlb_ctl_dbg_resv2_tag0_epn_loc_match => tlb_ctl_dbg_resv2_tag0_epn_loc_match, + tlb_ctl_dbg_resv2_tag0_epn_glob_match => tlb_ctl_dbg_resv2_tag0_epn_glob_match, + tlb_ctl_dbg_resv2_tag0_class_match => tlb_ctl_dbg_resv2_tag0_class_match, + tlb_ctl_dbg_resv3_tag0_lpid_match => tlb_ctl_dbg_resv3_tag0_lpid_match, + tlb_ctl_dbg_resv3_tag0_pid_match => tlb_ctl_dbg_resv3_tag0_pid_match, + tlb_ctl_dbg_resv3_tag0_as_snoop_match => tlb_ctl_dbg_resv3_tag0_as_snoop_match, + tlb_ctl_dbg_resv3_tag0_gs_snoop_match => tlb_ctl_dbg_resv3_tag0_gs_snoop_match, + tlb_ctl_dbg_resv3_tag0_as_tlbwe_match => tlb_ctl_dbg_resv3_tag0_as_tlbwe_match, + tlb_ctl_dbg_resv3_tag0_gs_tlbwe_match => tlb_ctl_dbg_resv3_tag0_gs_tlbwe_match, + tlb_ctl_dbg_resv3_tag0_ind_match => tlb_ctl_dbg_resv3_tag0_ind_match, + tlb_ctl_dbg_resv3_tag0_epn_loc_match => tlb_ctl_dbg_resv3_tag0_epn_loc_match, + tlb_ctl_dbg_resv3_tag0_epn_glob_match => tlb_ctl_dbg_resv3_tag0_epn_glob_match, + tlb_ctl_dbg_resv3_tag0_class_match => tlb_ctl_dbg_resv3_tag0_class_match, + tlb_ctl_dbg_clr_resv_q => tlb_ctl_dbg_clr_resv_q, + tlb_ctl_dbg_clr_resv_terms => tlb_ctl_dbg_clr_resv_terms, + tlb_cmp_dbg_tag4 => tlb_cmp_dbg_tag4, + tlb_cmp_dbg_tag4_wayhit => tlb_cmp_dbg_tag4_wayhit, + tlb_cmp_dbg_addr4 => tlb_cmp_dbg_addr4, + tlb_cmp_dbg_tag4_way => tlb_cmp_dbg_tag4_way, + tlb_cmp_dbg_tag4_parerr => tlb_cmp_dbg_tag4_parerr, + tlb_cmp_dbg_tag4_lru_dataout_q => tlb_cmp_dbg_tag4_lru_dataout_q, + tlb_cmp_dbg_tag5_tlb_datain_q => tlb_cmp_dbg_tag5_tlb_datain_q, + tlb_cmp_dbg_tag5_lru_datain_q => tlb_cmp_dbg_tag5_lru_datain_q, + tlb_cmp_dbg_tag5_lru_write => tlb_cmp_dbg_tag5_lru_write, + tlb_cmp_dbg_tag5_any_exception => tlb_cmp_dbg_tag5_any_exception, + tlb_cmp_dbg_tag5_except_type_q => tlb_cmp_dbg_tag5_except_type_q, + tlb_cmp_dbg_tag5_except_thdid_q => tlb_cmp_dbg_tag5_except_thdid_q, + tlb_cmp_dbg_tag5_erat_rel_val => tlb_cmp_dbg_tag5_erat_rel_val, + tlb_cmp_dbg_tag5_erat_rel_data => tlb_cmp_dbg_tag5_erat_rel_data, + tlb_cmp_dbg_erat_dup_q => tlb_cmp_dbg_erat_dup_q, + tlb_cmp_dbg_addr_enable => tlb_cmp_dbg_addr_enable, + tlb_cmp_dbg_pgsize_enable => tlb_cmp_dbg_pgsize_enable, + tlb_cmp_dbg_class_enable => tlb_cmp_dbg_class_enable, + tlb_cmp_dbg_extclass_enable => tlb_cmp_dbg_extclass_enable, + tlb_cmp_dbg_state_enable => tlb_cmp_dbg_state_enable, + tlb_cmp_dbg_thdid_enable => tlb_cmp_dbg_thdid_enable, + tlb_cmp_dbg_pid_enable => tlb_cmp_dbg_pid_enable, + tlb_cmp_dbg_lpid_enable => tlb_cmp_dbg_lpid_enable, + tlb_cmp_dbg_ind_enable => tlb_cmp_dbg_ind_enable, + tlb_cmp_dbg_iprot_enable => tlb_cmp_dbg_iprot_enable, + tlb_cmp_dbg_way0_entry_v => tlb_cmp_dbg_way0_entry_v, + tlb_cmp_dbg_way0_addr_match => tlb_cmp_dbg_way0_addr_match, + tlb_cmp_dbg_way0_pgsize_match => tlb_cmp_dbg_way0_pgsize_match, + tlb_cmp_dbg_way0_class_match => tlb_cmp_dbg_way0_class_match, + tlb_cmp_dbg_way0_extclass_match => tlb_cmp_dbg_way0_extclass_match, + tlb_cmp_dbg_way0_state_match => tlb_cmp_dbg_way0_state_match, + tlb_cmp_dbg_way0_thdid_match => tlb_cmp_dbg_way0_thdid_match, + tlb_cmp_dbg_way0_pid_match => tlb_cmp_dbg_way0_pid_match, + tlb_cmp_dbg_way0_lpid_match => tlb_cmp_dbg_way0_lpid_match, + tlb_cmp_dbg_way0_ind_match => tlb_cmp_dbg_way0_ind_match, + tlb_cmp_dbg_way0_iprot_match => tlb_cmp_dbg_way0_iprot_match, + tlb_cmp_dbg_way1_entry_v => tlb_cmp_dbg_way1_entry_v, + tlb_cmp_dbg_way1_addr_match => tlb_cmp_dbg_way1_addr_match, + tlb_cmp_dbg_way1_pgsize_match => tlb_cmp_dbg_way1_pgsize_match, + tlb_cmp_dbg_way1_class_match => tlb_cmp_dbg_way1_class_match, + tlb_cmp_dbg_way1_extclass_match => tlb_cmp_dbg_way1_extclass_match, + tlb_cmp_dbg_way1_state_match => tlb_cmp_dbg_way1_state_match, + tlb_cmp_dbg_way1_thdid_match => tlb_cmp_dbg_way1_thdid_match, + tlb_cmp_dbg_way1_pid_match => tlb_cmp_dbg_way1_pid_match, + tlb_cmp_dbg_way1_lpid_match => tlb_cmp_dbg_way1_lpid_match, + tlb_cmp_dbg_way1_ind_match => tlb_cmp_dbg_way1_ind_match, + tlb_cmp_dbg_way1_iprot_match => tlb_cmp_dbg_way1_iprot_match, + tlb_cmp_dbg_way2_entry_v => tlb_cmp_dbg_way2_entry_v, + tlb_cmp_dbg_way2_addr_match => tlb_cmp_dbg_way2_addr_match, + tlb_cmp_dbg_way2_pgsize_match => tlb_cmp_dbg_way2_pgsize_match, + tlb_cmp_dbg_way2_class_match => tlb_cmp_dbg_way2_class_match, + tlb_cmp_dbg_way2_extclass_match => tlb_cmp_dbg_way2_extclass_match, + tlb_cmp_dbg_way2_state_match => tlb_cmp_dbg_way2_state_match, + tlb_cmp_dbg_way2_thdid_match => tlb_cmp_dbg_way2_thdid_match, + tlb_cmp_dbg_way2_pid_match => tlb_cmp_dbg_way2_pid_match, + tlb_cmp_dbg_way2_lpid_match => tlb_cmp_dbg_way2_lpid_match, + tlb_cmp_dbg_way2_ind_match => tlb_cmp_dbg_way2_ind_match, + tlb_cmp_dbg_way2_iprot_match => tlb_cmp_dbg_way2_iprot_match, + tlb_cmp_dbg_way3_entry_v => tlb_cmp_dbg_way3_entry_v, + tlb_cmp_dbg_way3_addr_match => tlb_cmp_dbg_way3_addr_match, + tlb_cmp_dbg_way3_pgsize_match => tlb_cmp_dbg_way3_pgsize_match, + tlb_cmp_dbg_way3_class_match => tlb_cmp_dbg_way3_class_match, + tlb_cmp_dbg_way3_extclass_match => tlb_cmp_dbg_way3_extclass_match, + tlb_cmp_dbg_way3_state_match => tlb_cmp_dbg_way3_state_match, + tlb_cmp_dbg_way3_thdid_match => tlb_cmp_dbg_way3_thdid_match, + tlb_cmp_dbg_way3_pid_match => tlb_cmp_dbg_way3_pid_match, + tlb_cmp_dbg_way3_lpid_match => tlb_cmp_dbg_way3_lpid_match, + tlb_cmp_dbg_way3_ind_match => tlb_cmp_dbg_way3_ind_match, + tlb_cmp_dbg_way3_iprot_match => tlb_cmp_dbg_way3_iprot_match, + + lrat_dbg_tag1_addr_enable => lrat_dbg_tag1_addr_enable, + lrat_dbg_tag2_matchline_q => lrat_dbg_tag2_matchline_q, + lrat_dbg_entry0_addr_match => lrat_dbg_entry0_addr_match, + lrat_dbg_entry0_lpid_match => lrat_dbg_entry0_lpid_match, + lrat_dbg_entry0_entry_v => lrat_dbg_entry0_entry_v, + lrat_dbg_entry0_entry_x => lrat_dbg_entry0_entry_x, + lrat_dbg_entry0_size => lrat_dbg_entry0_size, + lrat_dbg_entry1_addr_match => lrat_dbg_entry1_addr_match, + lrat_dbg_entry1_lpid_match => lrat_dbg_entry1_lpid_match, + lrat_dbg_entry1_entry_v => lrat_dbg_entry1_entry_v, + lrat_dbg_entry1_entry_x => lrat_dbg_entry1_entry_x, + lrat_dbg_entry1_size => lrat_dbg_entry1_size, + lrat_dbg_entry2_addr_match => lrat_dbg_entry2_addr_match, + lrat_dbg_entry2_lpid_match => lrat_dbg_entry2_lpid_match, + lrat_dbg_entry2_entry_v => lrat_dbg_entry2_entry_v, + lrat_dbg_entry2_entry_x => lrat_dbg_entry2_entry_x, + lrat_dbg_entry2_size => lrat_dbg_entry2_size, + lrat_dbg_entry3_addr_match => lrat_dbg_entry3_addr_match, + lrat_dbg_entry3_lpid_match => lrat_dbg_entry3_lpid_match, + lrat_dbg_entry3_entry_v => lrat_dbg_entry3_entry_v, + lrat_dbg_entry3_entry_x => lrat_dbg_entry3_entry_x, + lrat_dbg_entry3_size => lrat_dbg_entry3_size, + lrat_dbg_entry4_addr_match => lrat_dbg_entry4_addr_match, + lrat_dbg_entry4_lpid_match => lrat_dbg_entry4_lpid_match, + lrat_dbg_entry4_entry_v => lrat_dbg_entry4_entry_v, + lrat_dbg_entry4_entry_x => lrat_dbg_entry4_entry_x, + lrat_dbg_entry4_size => lrat_dbg_entry4_size, + lrat_dbg_entry5_addr_match => lrat_dbg_entry5_addr_match, + lrat_dbg_entry5_lpid_match => lrat_dbg_entry5_lpid_match, + lrat_dbg_entry5_entry_v => lrat_dbg_entry5_entry_v, + lrat_dbg_entry5_entry_x => lrat_dbg_entry5_entry_x, + lrat_dbg_entry5_size => lrat_dbg_entry5_size, + lrat_dbg_entry6_addr_match => lrat_dbg_entry6_addr_match, + lrat_dbg_entry6_lpid_match => lrat_dbg_entry6_lpid_match, + lrat_dbg_entry6_entry_v => lrat_dbg_entry6_entry_v, + lrat_dbg_entry6_entry_x => lrat_dbg_entry6_entry_x, + lrat_dbg_entry6_size => lrat_dbg_entry6_size, + lrat_dbg_entry7_addr_match => lrat_dbg_entry7_addr_match, + lrat_dbg_entry7_lpid_match => lrat_dbg_entry7_lpid_match, + lrat_dbg_entry7_entry_v => lrat_dbg_entry7_entry_v, + lrat_dbg_entry7_entry_x => lrat_dbg_entry7_entry_x, + lrat_dbg_entry7_size => lrat_dbg_entry7_size, + htw_dbg_seq_idle => htw_dbg_seq_idle, + htw_dbg_pte0_seq_idle => htw_dbg_pte0_seq_idle, + htw_dbg_pte1_seq_idle => htw_dbg_pte1_seq_idle, + htw_dbg_seq_q => htw_dbg_seq_q, + htw_dbg_inptr_q => htw_dbg_inptr_q, + htw_dbg_pte0_seq_q => htw_dbg_pte0_seq_q, + htw_dbg_pte1_seq_q => htw_dbg_pte1_seq_q, + htw_dbg_ptereload_ptr_q => htw_dbg_ptereload_ptr_q, + htw_dbg_lsuptr_q => htw_dbg_lsuptr_q, + htw_dbg_req_valid_q => htw_dbg_req_valid_q, + htw_dbg_resv_valid_vec => htw_dbg_resv_valid_vec, + htw_dbg_tag4_clr_resv_q => htw_dbg_tag4_clr_resv_q, + htw_dbg_tag4_clr_resv_terms => htw_dbg_tag4_clr_resv_terms, + htw_dbg_pte0_score_ptr_q => htw_dbg_pte0_score_ptr_q, + htw_dbg_pte0_score_cl_offset_q => htw_dbg_pte0_score_cl_offset_q, + htw_dbg_pte0_score_error_q => htw_dbg_pte0_score_error_q, + htw_dbg_pte0_score_qwbeat_q => htw_dbg_pte0_score_qwbeat_q, + htw_dbg_pte0_score_pending_q => htw_dbg_pte0_score_pending_q, + htw_dbg_pte0_score_ibit_q => htw_dbg_pte0_score_ibit_q, + htw_dbg_pte0_score_dataval_q => htw_dbg_pte0_score_dataval_q, + htw_dbg_pte0_reld_for_me_tm1 => htw_dbg_pte0_reld_for_me_tm1, + htw_dbg_pte1_score_ptr_q => htw_dbg_pte1_score_ptr_q, + htw_dbg_pte1_score_cl_offset_q => htw_dbg_pte1_score_cl_offset_q, + htw_dbg_pte1_score_error_q => htw_dbg_pte1_score_error_q, + htw_dbg_pte1_score_qwbeat_q => htw_dbg_pte1_score_qwbeat_q, + htw_dbg_pte1_score_pending_q => htw_dbg_pte1_score_pending_q, + htw_dbg_pte1_score_ibit_q => htw_dbg_pte1_score_ibit_q, + htw_dbg_pte1_score_dataval_q => htw_dbg_pte1_score_dataval_q, + htw_dbg_pte1_reld_for_me_tm1 => htw_dbg_pte1_reld_for_me_tm1, + + mm_xu_lsu_req => mm_xu_lsu_req_sig, + mm_xu_lsu_ttype => mm_xu_lsu_ttype_sig, + mm_xu_lsu_wimge => mm_xu_lsu_wimge_sig, + mm_xu_lsu_u => mm_xu_lsu_u_sig, + mm_xu_lsu_addr => mm_xu_lsu_addr_sig, + mm_xu_lsu_lpid => mm_xu_lsu_lpid_sig, + mm_xu_lsu_gs => mm_xu_lsu_gs_sig, + mm_xu_lsu_ind => mm_xu_lsu_ind_sig, + mm_xu_lsu_lbit => mm_xu_lsu_lbit_sig, + xu_mm_lsu_token => xu_mm_lsu_token, + tlb_mas_tlbre => tlb_mas_tlbre, + tlb_mas_tlbsx_hit => tlb_mas_tlbsx_hit, + tlb_mas_tlbsx_miss => tlb_mas_tlbsx_miss, + tlb_mas_dtlb_error => tlb_mas_dtlb_error, + tlb_mas_itlb_error => tlb_mas_itlb_error, + tlb_mas_thdid => tlb_mas_thdid, + lrat_mas_tlbre => lrat_mas_tlbre, + lrat_mas_tlbsx_hit => lrat_mas_tlbsx_hit, + lrat_mas_tlbsx_miss => lrat_mas_tlbsx_miss, + lrat_mas_thdid => lrat_mas_thdid, + lrat_tag3_hit_status => lrat_tag3_hit_status, + lrat_tag3_hit_entry => lrat_tag3_hit_entry, + + tlb_seq_ierat_req => tlb_seq_ierat_req, + tlb_seq_derat_req => tlb_seq_derat_req, + mm_xu_hold_req => mm_xu_hold_req_sig, + xu_mm_hold_ack => xu_mm_hold_ack, + mm_xu_hold_done => mm_xu_hold_done_sig, + mmucsr0_tlb0fi => mmucsr0_tlb0fi, + tlbwe_back_inv_valid => tlbwe_back_inv_valid_sig, + tlbwe_back_inv_attr => tlbwe_back_inv_attr_sig(18 to 19), + xu_mm_lmq_stq_empty => xu_mm_lmq_stq_empty, + iu_mm_lmq_empty => iu_mm_lmq_empty, + mm_xu_eratmiss_done => mm_xu_eratmiss_done_sig, + mm_iu_barrier_done => mm_iu_barrier_done_sig, + mm_xu_ex3_flush_req => mm_xu_ex3_flush_req_sig, + mm_xu_illeg_instr => mm_xu_illeg_instr_sig, + lrat_tag4_hit_status => lrat_tag4_hit_status, + lrat_tag4_hit_entry => lrat_tag4_hit_entry, + mm_xu_cr0_eq => mm_xu_cr0_eq_sig, + mm_xu_cr0_eq_valid => mm_xu_cr0_eq_valid_sig, + tlb_htw_req_valid => tlb_htw_req_valid, + htw_lsu_req_valid => htw_lsu_req_valid, + htw_dbg_lsu_thdid => htw_dbg_lsu_thdid, + htw_lsu_ttype => htw_lsu_ttype, + htw_lsu_addr => htw_lsu_addr, + ptereload_req_taken => ptereload_req_taken, + ptereload_req_pte => ptereload_req_pte +); +-- End of mmq_dbg component instantiation +----------------------------------------------------------------------- +-- Performance Event component instantiation +----------------------------------------------------------------------- +mmq_perf: entity work.mmq_perf(mmq_perf) + generic map ( expand_type => expand_type ) + port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_func_sl_thold_2 => pc_func_sl_thold_2(0), + pc_func_slp_nsl_thold_2 => pc_func_slp_nsl_thold_2, + pc_sg_2 => pc_sg_2(0), + pc_fce_2 => pc_fce_2, + tc_ac_ccflush_dc => tc_ac_ccflush_dc, + lcb_clkoff_dc_b => lcb_clkoff_dc_b, + lcb_act_dis_dc => lcb_act_dis_dc, + lcb_d_mode_dc => lcb_d_mode_dc, + lcb_delay_lclkr_dc => lcb_delay_lclkr_dc(0), + lcb_mpw1_dc_b => lcb_mpw1_dc_b(0), + lcb_mpw2_dc_b => lcb_mpw2_dc_b, + scan_in => siv_1(mmq_perf_offset), + scan_out => sov_1(mmq_perf_offset), + + xu_mm_msr_gs => xu_mm_msr_gs, + xu_mm_msr_pr => xu_mm_msr_pr, + xu_mm_ccr2_notlb_b => xu_mm_ccr2_notlb_b(2), + + +-- count event inputs +xu_mm_ex5_perf_dtlb => xu_mm_ex5_perf_dtlb, + xu_mm_ex5_perf_itlb => xu_mm_ex5_perf_itlb, + + tlb_cmp_perf_event_t0 => tlb_cmp_perf_event_t0, + tlb_cmp_perf_event_t1 => tlb_cmp_perf_event_t1, + tlb_cmp_perf_event_t2 => tlb_cmp_perf_event_t2, + tlb_cmp_perf_event_t3 => tlb_cmp_perf_event_t3, + tlb_cmp_perf_state => tlb_cmp_perf_state, + + derat_req0_thdid => derat_req0_thdid_sig, + derat_req0_valid => derat_req0_valid_sig, + derat_req1_thdid => derat_req1_thdid_sig, + derat_req1_valid => derat_req1_valid_sig, + derat_req2_thdid => derat_req2_thdid_sig, + derat_req2_valid => derat_req2_valid_sig, + derat_req3_thdid => derat_req3_thdid_sig, + derat_req3_valid => derat_req3_valid_sig, + ierat_req0_thdid => ierat_req0_thdid_sig, + ierat_req0_valid => ierat_req0_valid_sig, + ierat_req0_nonspec => ierat_req0_nonspec_sig, + ierat_req1_thdid => ierat_req1_thdid_sig, + ierat_req1_valid => ierat_req1_valid_sig, + ierat_req1_nonspec => ierat_req1_nonspec_sig, + ierat_req2_thdid => ierat_req2_thdid_sig, + ierat_req2_valid => ierat_req2_valid_sig, + ierat_req2_nonspec => ierat_req2_nonspec_sig, + ierat_req3_thdid => ierat_req3_thdid_sig, + ierat_req3_valid => ierat_req3_valid_sig, + ierat_req3_nonspec => ierat_req3_nonspec_sig, + ierat_req_taken => ierat_req_taken, + derat_req_taken => derat_req_taken, + + tlb_tag0_thdid => tlb_tag0_thdid, + tlb_tag0_type => tlb_tag0_type(0 to 1), + tlb_seq_idle => tlb_seq_idle, + + inval_perf_tlbilx => inval_perf_tlbilx, + inval_perf_tlbivax => inval_perf_tlbivax, + inval_perf_tlbivax_snoop => inval_perf_tlbivax_snoop, + inval_perf_tlb_flush => inval_perf_tlb_flush, + + htw_req0_valid => htw_req0_valid, + htw_req0_thdid => htw_req0_thdid, + htw_req0_type => htw_req0_type, + htw_req1_valid => htw_req1_valid, + htw_req1_thdid => htw_req1_thdid, + htw_req1_type => htw_req1_type, + htw_req2_valid => htw_req2_valid, + htw_req2_thdid => htw_req2_thdid, + htw_req2_type => htw_req2_type, + htw_req3_valid => htw_req3_valid, + htw_req3_thdid => htw_req3_thdid, + htw_req3_type => htw_req3_type, + + tlb_cmp_perf_miss_direct => tlb_cmp_perf_miss_direct, + tlb_cmp_perf_hit_indirect => tlb_cmp_perf_hit_indirect, + tlb_cmp_perf_hit_first_page => tlb_cmp_perf_hit_first_page, + tlb_cmp_perf_ptereload_noexcep => tlb_cmp_perf_ptereload_noexcep, + tlb_cmp_perf_lrat_request => tlb_cmp_perf_lrat_request, + tlb_cmp_perf_lrat_miss => tlb_cmp_perf_lrat_miss, + tlb_cmp_perf_pt_fault => tlb_cmp_perf_pt_fault, + tlb_cmp_perf_pt_inelig => tlb_cmp_perf_pt_inelig, + tlb_ctl_perf_tlbwec_resv => tlb_ctl_perf_tlbwec_resv, + tlb_ctl_perf_tlbwec_noresv => tlb_ctl_perf_tlbwec_noresv, + + +-- control inputs +pc_mm_event_mux_ctrls => pc_mm_event_mux_ctrls(0 to 39), + pc_mm_event_count_mode => pc_mm_event_count_mode(0 to 2), + rp_mm_event_bus_enable_q => rp_mm_event_bus_enable_q, + mm_pc_event_data => mm_pc_event_data(0 to 7) +); +-- End of mmq_perf component instantiation +----------------------------------------------------------------------- +-- Pervasive and LCB Control Component Instantiation +----------------------------------------------------------------------- +mmq_perv : entity work.mmq_perv(mmq_perv) +generic map (expand_type => expand_type) +port map ( + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_mm_sg_3 => pc_mm_sg_3, + pc_mm_func_sl_thold_3 => pc_mm_func_sl_thold_3, + pc_mm_func_slp_sl_thold_3 => pc_mm_func_slp_sl_thold_3, + pc_mm_gptr_sl_thold_3 => pc_mm_gptr_sl_thold_3, + pc_mm_fce_3 => pc_mm_fce_3, + pc_mm_time_sl_thold_3 => pc_mm_time_sl_thold_3, + pc_mm_repr_sl_thold_3 => pc_mm_repr_sl_thold_3, + pc_mm_abst_sl_thold_3 => pc_mm_abst_sl_thold_3, + pc_mm_abst_slp_sl_thold_3 => pc_mm_abst_slp_sl_thold_3, + pc_mm_cfg_sl_thold_3 => pc_mm_cfg_sl_thold_3, + pc_mm_cfg_slp_sl_thold_3 => pc_mm_cfg_slp_sl_thold_3, + pc_mm_func_nsl_thold_3 => pc_mm_func_nsl_thold_3, + pc_mm_func_slp_nsl_thold_3 => pc_mm_func_slp_nsl_thold_3, + pc_mm_ary_nsl_thold_3 => pc_mm_ary_nsl_thold_3, + pc_mm_ary_slp_nsl_thold_3 => pc_mm_ary_slp_nsl_thold_3, + tc_ac_ccflush_dc => tc_ac_ccflush_dc, + tc_scan_diag_dc => tc_ac_scan_diag_dc, + tc_ac_scan_dis_dc_b => tc_ac_scan_dis_dc_b, + + pc_sg_0 => pc_sg_0, + pc_sg_1 => pc_sg_1, + pc_sg_2 => pc_sg_2, + pc_func_sl_thold_2 => pc_func_sl_thold_2, + pc_func_slp_sl_thold_2 => pc_func_slp_sl_thold_2, + pc_func_slp_nsl_thold_2 => pc_func_slp_nsl_thold_2, + pc_cfg_sl_thold_2 => pc_cfg_sl_thold_2, + pc_cfg_slp_sl_thold_2 => pc_cfg_slp_sl_thold_2, + pc_fce_2 => pc_fce_2, + pc_time_sl_thold_0 => pc_time_sl_thold_0, + pc_repr_sl_thold_0 => pc_repr_sl_thold_0, + pc_abst_sl_thold_0 => pc_abst_sl_thold_0, + pc_abst_slp_sl_thold_0 => pc_abst_slp_sl_thold_0, + pc_ary_nsl_thold_0 => pc_ary_nsl_thold_0, + pc_ary_slp_nsl_thold_0 => pc_ary_slp_nsl_thold_0, + pc_func_sl_thold_0 => pc_func_sl_thold_0, + pc_func_sl_thold_0_b => pc_func_sl_thold_0_b, + pc_func_slp_sl_thold_0 => pc_func_slp_sl_thold_0, + pc_func_slp_sl_thold_0_b => pc_func_slp_sl_thold_0_b, + lcb_clkoff_dc_b => lcb_clkoff_dc_b, + lcb_act_dis_dc => lcb_act_dis_dc, + lcb_d_mode_dc => lcb_d_mode_dc, + lcb_delay_lclkr_dc => lcb_delay_lclkr_dc, + lcb_mpw1_dc_b => lcb_mpw1_dc_b, + lcb_mpw2_dc_b => lcb_mpw2_dc_b, + g8t_gptr_lcb_clkoff_dc_b => g8t_gptr_lcb_clkoff_dc_b, + g8t_gptr_lcb_act_dis_dc => g8t_gptr_lcb_act_dis_dc, + g8t_gptr_lcb_d_mode_dc => g8t_gptr_lcb_d_mode_dc, + g8t_gptr_lcb_delay_lclkr_dc => g8t_gptr_lcb_delay_lclkr_dc, + g8t_gptr_lcb_mpw1_dc_b => g8t_gptr_lcb_mpw1_dc_b, + g8t_gptr_lcb_mpw2_dc_b => g8t_gptr_lcb_mpw2_dc_b, + g6t_gptr_lcb_clkoff_dc_b => g6t_gptr_lcb_clkoff_dc_b, + g6t_gptr_lcb_act_dis_dc => g6t_gptr_lcb_act_dis_dc, + g6t_gptr_lcb_d_mode_dc => g6t_gptr_lcb_d_mode_dc, + g6t_gptr_lcb_delay_lclkr_dc => g6t_gptr_lcb_delay_lclkr_dc, + g6t_gptr_lcb_mpw1_dc_b => g6t_gptr_lcb_mpw1_dc_b, + g6t_gptr_lcb_mpw2_dc_b => g6t_gptr_lcb_mpw2_dc_b, + + pc_mm_abist_dcomp_g6t_2r => pc_mm_abist_dcomp_g6t_2r, + pc_mm_abist_di_0 => pc_mm_abist_di_0, + pc_mm_abist_di_g6t_2r => pc_mm_abist_di_g6t_2r, + pc_mm_abist_ena_dc => pc_mm_abist_ena_dc, + pc_mm_abist_g6t_r_wb => pc_mm_abist_g6t_r_wb, + pc_mm_abist_g8t1p_renb_0 => pc_mm_abist_g8t1p_renb_0, + pc_mm_abist_g8t_bw_0 => pc_mm_abist_g8t_bw_0, + pc_mm_abist_g8t_bw_1 => pc_mm_abist_g8t_bw_1, + pc_mm_abist_g8t_dcomp => pc_mm_abist_g8t_dcomp, + pc_mm_abist_g8t_wenb => pc_mm_abist_g8t_wenb, + pc_mm_abist_raddr_0 => pc_mm_abist_raddr_0, + pc_mm_abist_waddr_0 => pc_mm_abist_waddr_0, + pc_mm_abist_wl128_comp_ena => pc_mm_abist_wl128_comp_ena, + + pc_mm_abist_g8t_wenb_q => pc_mm_abist_g8t_wenb_q, + pc_mm_abist_g8t1p_renb_0_q => pc_mm_abist_g8t1p_renb_0_q, + pc_mm_abist_di_0_q => pc_mm_abist_di_0_q, + pc_mm_abist_g8t_bw_1_q => pc_mm_abist_g8t_bw_1_q, + pc_mm_abist_g8t_bw_0_q => pc_mm_abist_g8t_bw_0_q, + pc_mm_abist_waddr_0_q => pc_mm_abist_waddr_0_q, + pc_mm_abist_raddr_0_q => pc_mm_abist_raddr_0_q, + pc_mm_abist_wl128_comp_ena_q => pc_mm_abist_wl128_comp_ena_q, + pc_mm_abist_g8t_dcomp_q => pc_mm_abist_g8t_dcomp_q, + pc_mm_abist_dcomp_g6t_2r_q => pc_mm_abist_dcomp_g6t_2r_q, + pc_mm_abist_di_g6t_2r_q => pc_mm_abist_di_g6t_2r_q, + pc_mm_abist_g6t_r_wb_q => pc_mm_abist_g6t_r_wb_q, + + pc_mm_bolt_sl_thold_3 => pc_mm_bolt_sl_thold_3, + pc_mm_bo_enable_3 => pc_mm_bo_enable_3, + pc_mm_bolt_sl_thold_0 => pc_mm_bolt_sl_thold_0, + pc_mm_bo_enable_2 => pc_mm_bo_enable_2, + + gptr_scan_in => gptr_scan_in, + gptr_scan_out => ac_an_gptr_scan_out, + + time_scan_in => time_scan_in, + time_scan_in_int => time_scan_in_int, + time_scan_out_int => time_scan_out_int, + time_scan_out => ac_an_time_scan_out, + + func_scan_in(0 to 8) => an_ac_func_scan_in(22 to 30), + func_scan_in(9) => an_ac_func_scan_in(59), + func_scan_in_int => func_scan_in_int, + func_scan_out_int => func_scan_out_int, + func_scan_out(0 to 8) => ac_an_func_scan_out(22 to 30), + func_scan_out(9) => ac_an_func_scan_out(59), + + repr_scan_in => repr_scan_in, + repr_scan_in_int => repr_scan_in_int, + repr_scan_out_int => repr_scan_out_int, + repr_scan_out => ac_an_repr_scan_out, + + abst_scan_in => an_ac_abst_scan_in(5 to 6), + abst_scan_in_int => abst_scan_in_int, + abst_scan_out_int => abst_scan_out_int, + abst_scan_out => ac_an_abst_scan_out(5 to 6), + + bcfg_scan_in => an_ac_bcfg_scan_in(2), + bcfg_scan_in_int => bcfg_scan_in_int, + bcfg_scan_out_int => bcfg_scan_out_int, + bcfg_scan_out => bcfg_scan_out, + + ccfg_scan_in => an_ac_bcfg_scan_in(0), + ccfg_scan_in_int => ccfg_scan_in_int, + ccfg_scan_out_int => ccfg_scan_out_int, + ccfg_scan_out => ccfg_scan_out, + + dcfg_scan_in => an_ac_dcfg_scan_in(0), + dcfg_scan_in_int => dcfg_scan_in_int, + dcfg_scan_out_int => dcfg_scan_out_int, + dcfg_scan_out => dcfg_scan_out + ); +----------------------------------------------------------------------- +-- output assignments +----------------------------------------------------------------------- +-- tie off undriven ports when tlb components are not present +-- keep this here for schmucks that like to control TLB existence with generics +eratonly_tieoffs_gen: if expand_tlb_type = 0 generate +mm_iu_ierat_rel_val_sig <= (others => '0'); +mm_iu_ierat_rel_data_sig <= (others => '0'); +mm_xu_derat_rel_val_sig <= (others => '0'); +mm_xu_derat_rel_data_sig <= (others => '0'); +tlb_cmp_ierat_dup_val_sig <= (others => '0'); +tlb_cmp_derat_dup_val_sig <= (others => '0'); +tlb_cmp_erat_dup_wait_sig <= (others => '0'); +tlb_ctl_barrier_done_sig <= (others => '0'); +tlb_ctl_ex2_flush_req_sig <= (others => '0'); +tlb_ctl_ex2_illeg_instr_sig <= (others => '0'); +tlb_req_quiesce_sig <= (others => '1'); +tlb_ctl_quiesce_sig <= (others => '1'); +htw_quiesce_sig <= (others => '1'); +-- missing perf count signals +tlb_cmp_perf_event_t0 <= (others => '0'); +tlb_cmp_perf_event_t1 <= (others => '0'); +tlb_cmp_perf_event_t2 <= (others => '0'); +tlb_cmp_perf_event_t3 <= (others => '0'); +tlb_cmp_perf_state <= (others => '0'); +derat_req0_thdid_sig <= (others => '0'); +derat_req0_valid_sig <= '0'; +derat_req1_thdid_sig <= (others => '0'); +derat_req1_valid_sig <= '0'; +derat_req2_thdid_sig <= (others => '0'); +derat_req2_valid_sig <= '0'; +derat_req3_thdid_sig <= (others => '0'); +derat_req3_valid_sig <= '0'; +ierat_req0_thdid_sig <= (others => '0'); +ierat_req0_valid_sig <= '0'; +ierat_req0_nonspec_sig <= '0'; +ierat_req1_thdid_sig <= (others => '0'); +ierat_req1_valid_sig <= '0'; +ierat_req1_nonspec_sig <= '0'; +ierat_req2_thdid_sig <= (others => '0'); +ierat_req2_valid_sig <= '0'; +ierat_req2_nonspec_sig <= '0'; +ierat_req3_thdid_sig <= (others => '0'); +ierat_req3_valid_sig <= '0'; +ierat_req3_nonspec_sig <= '0'; +tlb_tag0_thdid <= (others => '0'); +tlb_tag0_type <= (others => '0'); +tlb_seq_idle <= '0'; +htw_req0_valid <= '0'; +htw_req0_thdid <= (others => '0'); +htw_req0_type <= (others => '0'); +htw_req1_valid <= '0'; +htw_req1_thdid <= (others => '0'); +htw_req1_type <= (others => '0'); +htw_req2_valid <= '0'; +htw_req2_thdid <= (others => '0'); +htw_req2_type <= (others => '0'); +htw_req3_valid <= '0'; +htw_req3_thdid <= (others => '0'); +htw_req3_type <= (others => '0'); +tlb_cmp_perf_miss_direct <= '0'; +tlb_cmp_perf_hit_indirect <= '0'; +tlb_cmp_perf_hit_first_page <= '0'; +tlb_cmp_perf_ptereload_noexcep <= '0'; +tlb_cmp_perf_lrat_request <= '0'; +tlb_cmp_perf_lrat_miss <= '0'; +tlb_cmp_perf_pt_fault <= '0'; +tlb_cmp_perf_pt_inelig <= '0'; +tlb_ctl_perf_tlbwec_resv <= '0'; +tlb_ctl_perf_tlbwec_noresv <= '0'; +-- missing debug signals +tlb_cmp_dbg_tag4 <= (others => '0'); +tlb_cmp_dbg_tag4_wayhit <= (others => '0'); +tlb_cmp_dbg_addr4 <= (others => '0'); +tlb_cmp_dbg_tag4_way <= (others => '0'); +mm_xu_eratmiss_done_sig <= (others => '0'); +mm_xu_tlb_miss_sig <= (others => '0'); +mm_xu_lrat_miss_sig <= (others => '0'); +mm_xu_tlb_inelig_sig <= (others => '0'); +mm_xu_pt_fault_sig <= (others => '0'); +mm_xu_hv_priv_sig <= (others => '0'); +mm_xu_cr0_eq_sig <= (others => '0'); +mm_xu_cr0_eq_valid_sig <= (others => '0'); +mm_xu_esr_pt_sig <= (others => '0'); +mm_xu_esr_data_sig <= (others => '0'); +mm_xu_esr_epid_sig <= (others => '0'); +mm_xu_esr_st_sig <= (others => '0'); +mm_xu_tlb_multihit_err <= (others => '0'); +mm_xu_tlb_par_err <= (others => '0'); +mm_xu_lru_par_err <= (others => '0'); +tlb_snoop_ack <= '0'; +end generate eratonly_tieoffs_gen; +mm_iu_ierat_rel_val <= mm_iu_ierat_rel_val_sig; +mm_iu_ierat_rel_data <= mm_iu_ierat_rel_data_sig; +mm_xu_derat_rel_val <= mm_xu_derat_rel_val_sig; +mm_xu_derat_rel_data <= mm_xu_derat_rel_data_sig; +mm_xu_hold_req <= mm_xu_hold_req_sig; +mm_xu_hold_done <= mm_xu_hold_done_sig; +mm_iu_barrier_done <= mm_iu_barrier_done_sig; +mm_xu_eratmiss_done <= mm_xu_eratmiss_done_sig; +mm_xu_tlb_miss <= mm_xu_tlb_miss_sig; +mm_xu_lrat_miss <= mm_xu_lrat_miss_sig; +mm_xu_tlb_inelig <= mm_xu_tlb_inelig_sig; +mm_xu_pt_fault <= mm_xu_pt_fault_sig; +mm_xu_hv_priv <= mm_xu_hv_priv_sig; +mm_xu_illeg_instr <= mm_xu_illeg_instr_sig; +mm_xu_esr_pt <= mm_xu_esr_pt_sig; +mm_xu_esr_data <= mm_xu_esr_data_sig; +mm_xu_esr_epid <= mm_xu_esr_epid_sig; +mm_xu_esr_st <= mm_xu_esr_st_sig; +mm_xu_cr0_eq <= mm_xu_cr0_eq_sig; +mm_xu_cr0_eq_valid <= mm_xu_cr0_eq_valid_sig; +mm_xu_quiesce <= mm_xu_quiesce_sig; +mm_xu_local_snoop_reject <= mm_xu_local_snoop_reject_sig; +mm_xu_ex3_flush_req <= mm_xu_ex3_flush_req_sig; +mm_xu_lsu_req <= mm_xu_lsu_req_sig; +mm_xu_lsu_ttype <= mm_xu_lsu_ttype_sig; +mm_xu_lsu_wimge <= mm_xu_lsu_wimge_sig; +mm_xu_lsu_u <= mm_xu_lsu_u_sig; +mm_xu_lsu_addr <= mm_xu_lsu_addr_sig; +mm_xu_lsu_lpid <= mm_xu_lsu_lpid_sig; +mm_xu_lsu_gs <= mm_xu_lsu_gs_sig; +mm_xu_lsu_ind <= mm_xu_lsu_ind_sig; +mm_xu_lsu_lbit <= mm_xu_lsu_lbit_sig; +-------------------- glorp1: end of common stuff for both erat-only and tlb ------------- +tlb_gen_logic: if expand_tlb_type > 0 generate +----------------------------------------------------------------------- +-- Start of TLB logic +----------------------------------------------------------------------- +----------------------------------------------------------------------- +-- TLB Request Queue Component Instantiation +----------------------------------------------------------------------- +mmq_tlb_req: entity work.mmq_tlb_req(mmq_tlb_req) + generic map ( pid_width => pid_width, + pid_width_erat => pid_width_erat, + lpid_width => lpid_width, + req_epn_width => req_epn_width, + rs_data_width => rs_data_width, + expand_type => expand_type ) + port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + tc_ccflush_dc => tc_ac_ccflush_dc, + tc_scan_dis_dc_b => tc_ac_scan_dis_dc_b, + tc_scan_diag_dc => tc_ac_scan_diag_dc, + tc_lbist_en_dc => tc_ac_lbist_en_dc, + + lcb_d_mode_dc => lcb_d_mode_dc, + lcb_clkoff_dc_b => lcb_clkoff_dc_b, + lcb_act_dis_dc => lcb_act_dis_dc, + lcb_mpw1_dc_b => lcb_mpw1_dc_b, + lcb_mpw2_dc_b => lcb_mpw2_dc_b, + lcb_delay_lclkr_dc => lcb_delay_lclkr_dc, + + ac_func_scan_in => func_scan_in_int(2), + ac_func_scan_out => func_scan_out_int(2), + + pc_sg_2 => pc_sg_2(1), + pc_func_sl_thold_2 => pc_func_sl_thold_2(1), + pc_func_slp_sl_thold_2 => pc_func_slp_sl_thold_2(1), + pid0 => pid0_sig, + pid1 => pid1_sig, + pid2 => pid2_sig, + pid3 => pid3_sig, + lpidr => lpidr_sig, + xu_mm_ccr2_notlb_b => xu_mm_ccr2_notlb_b(3), + mmucr2_act_override => mmucr2_sig(0), + iu_mm_ierat_req => iu_mm_ierat_req, + iu_mm_ierat_epn => iu_mm_ierat_epn, + iu_mm_ierat_thdid => iu_mm_ierat_thdid, + iu_mm_ierat_state => iu_mm_ierat_state, + iu_mm_ierat_tid => iu_mm_ierat_tid, + iu_mm_ierat_flush => iu_mm_ierat_flush, + + xu_mm_derat_req => xu_mm_derat_req, + xu_mm_derat_epn => xu_mm_derat_epn, + xu_mm_derat_thdid => xu_mm_derat_thdid, + xu_mm_derat_ttype => xu_mm_derat_ttype, + xu_mm_derat_state => xu_mm_derat_state, + xu_mm_derat_tid => xu_mm_derat_tid, + xu_mm_derat_lpid => xu_mm_derat_lpid, + + ierat_req0_pid => ierat_req0_pid_sig, + ierat_req0_as => ierat_req0_as_sig, + ierat_req0_gs => ierat_req0_gs_sig, + ierat_req0_epn => ierat_req0_epn_sig, + ierat_req0_thdid => ierat_req0_thdid_sig, + ierat_req0_valid => ierat_req0_valid_sig, + ierat_req0_nonspec => ierat_req0_nonspec_sig, + ierat_req1_pid => ierat_req1_pid_sig, + ierat_req1_as => ierat_req1_as_sig, + ierat_req1_gs => ierat_req1_gs_sig, + ierat_req1_epn => ierat_req1_epn_sig, + ierat_req1_thdid => ierat_req1_thdid_sig, + ierat_req1_valid => ierat_req1_valid_sig, + ierat_req1_nonspec => ierat_req1_nonspec_sig, + ierat_req2_pid => ierat_req2_pid_sig, + ierat_req2_as => ierat_req2_as_sig, + ierat_req2_gs => ierat_req2_gs_sig, + ierat_req2_epn => ierat_req2_epn_sig, + ierat_req2_thdid => ierat_req2_thdid_sig, + ierat_req2_valid => ierat_req2_valid_sig, + ierat_req2_nonspec => ierat_req2_nonspec_sig, + ierat_req3_pid => ierat_req3_pid_sig, + ierat_req3_as => ierat_req3_as_sig, + ierat_req3_gs => ierat_req3_gs_sig, + ierat_req3_epn => ierat_req3_epn_sig, + ierat_req3_thdid => ierat_req3_thdid_sig, + ierat_req3_valid => ierat_req3_valid_sig, + ierat_req3_nonspec => ierat_req3_nonspec_sig, + ierat_iu4_pid => ierat_iu4_pid_sig, + ierat_iu4_gs => ierat_iu4_gs_sig, + ierat_iu4_as => ierat_iu4_as_sig, + ierat_iu4_epn => ierat_iu4_epn_sig, + ierat_iu4_thdid => ierat_iu4_thdid_sig, + ierat_iu4_valid => ierat_iu4_valid_sig, + + derat_req0_lpid => derat_req0_lpid_sig, + derat_req0_pid => derat_req0_pid_sig, + derat_req0_as => derat_req0_as_sig, + derat_req0_gs => derat_req0_gs_sig, + derat_req0_epn => derat_req0_epn_sig, + derat_req0_thdid => derat_req0_thdid_sig, + derat_req0_valid => derat_req0_valid_sig, + derat_req1_lpid => derat_req1_lpid_sig, + derat_req1_pid => derat_req1_pid_sig, + derat_req1_as => derat_req1_as_sig, + derat_req1_gs => derat_req1_gs_sig, + derat_req1_epn => derat_req1_epn_sig, + derat_req1_thdid => derat_req1_thdid_sig, + derat_req1_valid => derat_req1_valid_sig, + derat_req2_lpid => derat_req2_lpid_sig, + derat_req2_pid => derat_req2_pid_sig, + derat_req2_as => derat_req2_as_sig, + derat_req2_gs => derat_req2_gs_sig, + derat_req2_epn => derat_req2_epn_sig, + derat_req2_thdid => derat_req2_thdid_sig, + derat_req2_valid => derat_req2_valid_sig, + derat_req3_lpid => derat_req3_lpid_sig, + derat_req3_pid => derat_req3_pid_sig, + derat_req3_as => derat_req3_as_sig, + derat_req3_gs => derat_req3_gs_sig, + derat_req3_epn => derat_req3_epn_sig, + derat_req3_thdid => derat_req3_thdid_sig, + derat_req3_valid => derat_req3_valid_sig, + derat_ex5_lpid => derat_ex5_lpid_sig, + derat_ex5_pid => derat_ex5_pid_sig, + derat_ex5_gs => derat_ex5_gs_sig, + derat_ex5_as => derat_ex5_as_sig, + derat_ex5_epn => derat_ex5_epn_sig, + derat_ex5_thdid => derat_ex5_thdid_sig, + derat_ex5_valid => derat_ex5_valid_sig, + + xu_ex3_flush => xu_ex3_flush, + xu_mm_ex4_flush => xu_mm_ex4_flush, + xu_mm_ex5_flush => xu_mm_ex5_flush, + xu_mm_ierat_flush => xu_mm_ierat_flush, + xu_mm_ierat_miss => xu_mm_ierat_miss, + + mm_xu_eratmiss_done => mm_xu_eratmiss_done_sig, + mm_xu_tlb_miss => mm_xu_tlb_miss_sig, + + tlb_cmp_ierat_dup_val => tlb_cmp_ierat_dup_val_sig, + tlb_cmp_derat_dup_val => tlb_cmp_derat_dup_val_sig, + + tlb_seq_ierat_req => tlb_seq_ierat_req, + tlb_seq_derat_req => tlb_seq_derat_req, + tlb_seq_ierat_done => tlb_seq_ierat_done, + tlb_seq_derat_done => tlb_seq_derat_done, + ierat_req_taken => ierat_req_taken, + derat_req_taken => derat_req_taken, + ierat_req_epn => ierat_req_epn, + ierat_req_pid => ierat_req_pid, + ierat_req_state => ierat_req_state, + ierat_req_thdid => ierat_req_thdid, + ierat_req_dup => ierat_req_dup, + derat_req_epn => derat_req_epn, + derat_req_pid => derat_req_pid, + derat_req_lpid => derat_req_lpid, + derat_req_state => derat_req_state, + derat_req_ttype => derat_req_ttype, + derat_req_thdid => derat_req_thdid, + derat_req_dup => derat_req_dup, + + tlb_req_quiesce => tlb_req_quiesce_sig, + + tlb_req_dbg_ierat_iu5_valid_q => tlb_req_dbg_ierat_iu5_valid_q, + tlb_req_dbg_ierat_iu5_thdid => tlb_req_dbg_ierat_iu5_thdid, + tlb_req_dbg_ierat_iu5_state_q => tlb_req_dbg_ierat_iu5_state_q, + tlb_req_dbg_ierat_inptr_q => tlb_req_dbg_ierat_inptr_q, + tlb_req_dbg_ierat_outptr_q => tlb_req_dbg_ierat_outptr_q, + tlb_req_dbg_ierat_req_valid_q => tlb_req_dbg_ierat_req_valid_q, + tlb_req_dbg_ierat_req_nonspec_q => tlb_req_dbg_ierat_req_nonspec_q, + tlb_req_dbg_ierat_req_thdid => tlb_req_dbg_ierat_req_thdid, + tlb_req_dbg_ierat_req_dup_q => tlb_req_dbg_ierat_req_dup_q, + tlb_req_dbg_derat_ex6_valid_q => tlb_req_dbg_derat_ex6_valid_q, + tlb_req_dbg_derat_ex6_thdid => tlb_req_dbg_derat_ex6_thdid, + tlb_req_dbg_derat_ex6_state_q => tlb_req_dbg_derat_ex6_state_q, + tlb_req_dbg_derat_inptr_q => tlb_req_dbg_derat_inptr_q, + tlb_req_dbg_derat_outptr_q => tlb_req_dbg_derat_outptr_q, + tlb_req_dbg_derat_req_valid_q => tlb_req_dbg_derat_req_valid_q, + tlb_req_dbg_derat_req_thdid => tlb_req_dbg_derat_req_thdid, + tlb_req_dbg_derat_req_ttype_q => tlb_req_dbg_derat_req_ttype_q, + tlb_req_dbg_derat_req_dup_q => tlb_req_dbg_derat_req_dup_q +); +-- End of mmq_tlb_req component instantiation +----------------------------------------------------------------------- +-- TLB Control Logic Component Instantiation +----------------------------------------------------------------------- +mmq_tlb_ctl: entity work.mmq_tlb_ctl(mmq_tlb_ctl) + generic map ( epn_width => epn_width, + pid_width => pid_width, + real_addr_width => real_addr_width, + rs_data_width => rs_data_width, + data_out_width => data_out_width, + tlb_tag_width => tlb_tag_width, + expand_type => expand_type ) + port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + tc_ccflush_dc => tc_ac_ccflush_dc, + tc_scan_dis_dc_b => tc_ac_scan_dis_dc_b, + tc_scan_diag_dc => tc_ac_scan_diag_dc, + tc_lbist_en_dc => tc_ac_lbist_en_dc, + + lcb_d_mode_dc => lcb_d_mode_dc, + lcb_clkoff_dc_b => lcb_clkoff_dc_b, + lcb_act_dis_dc => lcb_act_dis_dc, + lcb_mpw1_dc_b => lcb_mpw1_dc_b, + lcb_mpw2_dc_b => lcb_mpw2_dc_b, + lcb_delay_lclkr_dc => lcb_delay_lclkr_dc, + + ac_func_scan_in => func_scan_in_int(3), + ac_func_scan_out => func_scan_out_int(3), + + pc_sg_2 => pc_sg_2(1), + pc_func_sl_thold_2 => pc_func_sl_thold_2(1), + pc_func_slp_sl_thold_2 => pc_func_slp_sl_thold_2(1), + pc_func_slp_nsl_thold_2 => pc_func_slp_nsl_thold_2, + pc_fce_2 => pc_fce_2, + xu_mm_rf1_val => xu_mm_rf1_val, + xu_mm_rf1_is_tlbre => xu_mm_rf1_is_tlbre, + xu_mm_rf1_is_tlbwe => xu_mm_rf1_is_tlbwe, + xu_mm_rf1_is_tlbsx => xu_mm_rf1_is_tlbsx, + xu_mm_rf1_is_tlbsxr => xu_mm_rf1_is_tlbsxr, + xu_mm_rf1_is_tlbsrx => xu_mm_rf1_is_tlbsrx, + xu_mm_ex2_epn => xu_mm_ex2_eff_addr_sig(64-rs_data_width to 51), + + xu_mm_msr_gs => xu_mm_msr_gs, + xu_mm_msr_pr => xu_mm_msr_pr, + xu_mm_msr_is => xu_mm_msr_is, + xu_mm_msr_ds => xu_mm_msr_ds, + xu_mm_msr_cm => xu_mm_msr_cm, + + xu_mm_ccr2_notlb_b => xu_mm_ccr2_notlb_b(4), + xu_mm_epcr_dgtmi => xu_mm_epcr_dgtmi_sig, + xu_mm_xucr4_mmu_mchk => xu_mm_xucr4_mmu_mchk, + xu_mm_xucr4_mmu_mchk_q => xu_mm_xucr4_mmu_mchk_q, + xu_rf1_flush => xu_rf1_flush, + xu_ex1_flush => xu_ex1_flush, + xu_ex2_flush => xu_ex2_flush, + xu_ex3_flush => xu_ex3_flush, + xu_ex4_flush => xu_ex4_flush, + xu_ex5_flush => xu_ex5_flush, + + tlb_ctl_ex3_valid => tlb_ctl_ex3_valid_sig, + tlb_ctl_ex3_ttype => tlb_ctl_ex3_ttype_sig, + + tlb_ctl_tag2_flush => tlb_ctl_tag2_flush_sig, + tlb_ctl_tag3_flush => tlb_ctl_tag3_flush_sig, + tlb_ctl_tag4_flush => tlb_ctl_tag4_flush_sig, + tlb_resv_match_vec => tlb_resv_match_vec_sig, + tlb_ctl_barrier_done => tlb_ctl_barrier_done_sig, + tlb_ctl_ex2_flush_req => tlb_ctl_ex2_flush_req_sig, + tlb_ctl_ex2_illeg_instr => tlb_ctl_ex2_illeg_instr_sig, + tlb_ctl_quiesce => tlb_ctl_quiesce_sig, + ex6_illeg_instr => ex6_illeg_instr, + + mm_xu_eratmiss_done => mm_xu_eratmiss_done_sig, + mm_xu_tlb_miss => mm_xu_tlb_miss_sig, + mm_xu_tlb_inelig => mm_xu_tlb_inelig_sig, + + tlbwe_back_inv_pending => tlbwe_back_inv_pending_sig, + pid0 => pid0_sig, + pid1 => pid1_sig, + pid2 => pid2_sig, + pid3 => pid3_sig, + mmucr1_tlbi_msb => mmucr1_sig(18), + mmucr1_tlbwe_binv => mmucr1_sig(17), + mmucr2 => mmucr2_sig, + mmucr3_0 => mmucr3_0_sig, + mmucr3_1 => mmucr3_1_sig, + mmucr3_2 => mmucr3_2_sig, + mmucr3_3 => mmucr3_3_sig, + lpidr => lpidr_sig, + mmucfg_lrat => mmucfg_lrat, + mmucfg_twc => mmucfg_twc, + mmucsr0_tlb0fi => mmucsr0_tlb0fi, + tlb0cfg_pt => tlb0cfg_pt, + tlb0cfg_ind => tlb0cfg_ind, + tlb0cfg_gtwe => tlb0cfg_gtwe, + + mas0_0_atsel => mas0_0_atsel, + mas0_0_esel => mas0_0_esel, + mas0_0_hes => mas0_0_hes, + mas0_0_wq => mas0_0_wq, + mas1_0_v => mas1_0_v, + mas1_0_iprot => mas1_0_iprot, + mas1_0_tid => mas1_0_tid, + mas1_0_ind => mas1_0_ind, + mas1_0_ts => mas1_0_ts, + mas1_0_tsize => mas1_0_tsize, + mas2_0_epn => mas2_0_epn, + mas2_0_wimge => mas2_0_wimge, + mas3_0_usxwr => mas3_0_usxwr(0 to 3), + mas5_0_sgs => mas5_0_sgs, + mas5_0_slpid => mas5_0_slpid, + mas6_0_spid => mas6_0_spid, + mas6_0_sind => mas6_0_sind, + mas6_0_sas => mas6_0_sas, + mas8_0_tgs => mas8_0_tgs, + mas8_0_tlpid => mas8_0_tlpid, + mas0_1_atsel => mas0_1_atsel, + mas0_1_esel => mas0_1_esel, + mas0_1_hes => mas0_1_hes, + mas0_1_wq => mas0_1_wq, + mas1_1_v => mas1_1_v, + mas1_1_iprot => mas1_1_iprot, + mas1_1_tid => mas1_1_tid, + mas1_1_ind => mas1_1_ind, + mas1_1_ts => mas1_1_ts, + mas1_1_tsize => mas1_1_tsize, + mas2_1_epn => mas2_1_epn, + mas2_1_wimge => mas2_1_wimge, + mas3_1_usxwr => mas3_1_usxwr(0 to 3), + mas5_1_sgs => mas5_1_sgs, + mas5_1_slpid => mas5_1_slpid, + mas6_1_spid => mas6_1_spid, + mas6_1_sind => mas6_1_sind, + mas6_1_sas => mas6_1_sas, + mas8_1_tgs => mas8_1_tgs, + mas8_1_tlpid => mas8_1_tlpid, + mas0_2_atsel => mas0_2_atsel, + mas0_2_esel => mas0_2_esel, + mas0_2_hes => mas0_2_hes, + mas0_2_wq => mas0_2_wq, + mas1_2_v => mas1_2_v, + mas1_2_iprot => mas1_2_iprot, + mas1_2_tid => mas1_2_tid, + mas1_2_ind => mas1_2_ind, + mas1_2_ts => mas1_2_ts, + mas1_2_tsize => mas1_2_tsize, + mas2_2_epn => mas2_2_epn, + mas2_2_wimge => mas2_2_wimge, + mas3_2_usxwr => mas3_2_usxwr(0 to 3), + mas5_2_sgs => mas5_2_sgs, + mas5_2_slpid => mas5_2_slpid, + mas6_2_spid => mas6_2_spid, + mas6_2_sind => mas6_2_sind, + mas6_2_sas => mas6_2_sas, + mas8_2_tgs => mas8_2_tgs, + mas8_2_tlpid => mas8_2_tlpid, + mas0_3_atsel => mas0_3_atsel, + mas0_3_esel => mas0_3_esel, + mas0_3_hes => mas0_3_hes, + mas0_3_wq => mas0_3_wq, + mas1_3_v => mas1_3_v, + mas1_3_iprot => mas1_3_iprot, + mas1_3_tid => mas1_3_tid, + mas1_3_ind => mas1_3_ind, + mas1_3_ts => mas1_3_ts, + mas1_3_tsize => mas1_3_tsize, + mas2_3_epn => mas2_3_epn, + mas2_3_wimge => mas2_3_wimge, + mas3_3_usxwr => mas3_3_usxwr(0 to 3), + mas5_3_sgs => mas5_3_sgs, + mas5_3_slpid => mas5_3_slpid, + mas6_3_spid => mas6_3_spid, + mas6_3_sind => mas6_3_sind, + mas6_3_sas => mas6_3_sas, + mas8_3_tgs => mas8_3_tgs, + mas8_3_tlpid => mas8_3_tlpid, + + tlb_seq_ierat_req => tlb_seq_ierat_req, + tlb_seq_derat_req => tlb_seq_derat_req, + tlb_seq_ierat_done => tlb_seq_ierat_done, + tlb_seq_derat_done => tlb_seq_derat_done, + tlb_seq_idle => tlb_seq_idle, + ierat_req_taken => ierat_req_taken, + derat_req_taken => derat_req_taken, + ierat_req_epn => ierat_req_epn, + ierat_req_pid => ierat_req_pid, + ierat_req_state => ierat_req_state, + ierat_req_thdid => ierat_req_thdid, + ierat_req_dup => ierat_req_dup, + derat_req_epn => derat_req_epn, + derat_req_pid => derat_req_pid, + derat_req_lpid => derat_req_lpid, + derat_req_state => derat_req_state, + derat_req_ttype => derat_req_ttype, + derat_req_thdid => derat_req_thdid, + derat_req_dup => derat_req_dup, + ptereload_req_valid => ptereload_req_valid, + ptereload_req_tag => ptereload_req_tag, + ptereload_req_pte => ptereload_req_pte, + ptereload_req_taken => ptereload_req_taken, + + tlb_snoop_coming => tlb_snoop_coming, + tlb_snoop_val => tlb_snoop_val, + tlb_snoop_attr => tlb_snoop_attr, + tlb_snoop_vpn => tlb_snoop_vpn, + tlb_snoop_ack => tlb_snoop_ack, + + lru_rd_addr => lru_rd_addr, + lru_tag4_dataout => lru_tag4_dataout, + tlb_tag4_esel => tlb_tag4_esel, + tlb_tag4_wq => tlb_tag4_wq, + tlb_tag4_is => tlb_tag4_is, + tlb_tag4_gs => tlb_tag4_gs, + tlb_tag4_pr => tlb_tag4_pr, + tlb_tag4_hes => tlb_tag4_hes, + tlb_tag4_atsel => tlb_tag4_atsel, + tlb_tag4_pt => tlb_tag4_pt, + tlb_tag4_cmp_hit => tlb_tag4_cmp_hit, + tlb_tag4_way_ind => tlb_tag4_way_ind, + tlb_tag4_ptereload => tlb_tag4_ptereload, + tlb_tag4_endflag => tlb_tag4_endflag, + tlb_tag4_parerr => tlb_tag4_parerr, + tlb_tag5_except => tlb_tag5_except, + tlb_cmp_erat_dup_wait => tlb_cmp_erat_dup_wait_sig, + + tlb_tag0_epn => tlb_tag0_epn, + tlb_tag0_thdid => tlb_tag0_thdid, + tlb_tag0_type => tlb_tag0_type, + tlb_tag0_lpid => tlb_tag0_lpid, + tlb_tag0_atsel => tlb_tag0_atsel, + tlb_tag0_size => tlb_tag0_size, + tlb_tag0_addr_cap => tlb_tag0_addr_cap, + + tlb_tag2 => tlb_tag2_sig, + tlb_addr2 => tlb_addr2_sig, + + tlb_ctl_perf_tlbwec_resv => tlb_ctl_perf_tlbwec_resv, + tlb_ctl_perf_tlbwec_noresv => tlb_ctl_perf_tlbwec_noresv, + + lrat_tag4_hit_status => lrat_tag4_hit_status, + + tlb_lper_lpn => tlb_lper_lpn, + tlb_lper_lps => tlb_lper_lps, + tlb_lper_we => tlb_lper_we, + + ptereload_req_pte_lat => ptereload_req_pte_lat, + pte_tag0_lpn => pte_tag0_lpn(64-real_addr_width to 51), + pte_tag0_lpid => pte_tag0_lpid, + + tlb_write => tlb_write, + tlb_addr => tlb_addr, + tlb_tag5_write => tlb_tag5_write, + tlb_delayed_act => tlb_delayed_act, + + tlb_ctl_dbg_seq_q => tlb_ctl_dbg_seq_q, + tlb_ctl_dbg_seq_idle => tlb_ctl_dbg_seq_idle, + tlb_ctl_dbg_seq_any_done_sig => tlb_ctl_dbg_seq_any_done_sig, + tlb_ctl_dbg_seq_abort => tlb_ctl_dbg_seq_abort, + tlb_ctl_dbg_any_tlb_req_sig => tlb_ctl_dbg_any_tlb_req_sig, + tlb_ctl_dbg_any_req_taken_sig => tlb_ctl_dbg_any_req_taken_sig, + tlb_ctl_dbg_tag0_valid => tlb_ctl_dbg_tag0_valid, + tlb_ctl_dbg_tag0_thdid => tlb_ctl_dbg_tag0_thdid, + tlb_ctl_dbg_tag0_type => tlb_ctl_dbg_tag0_type, + tlb_ctl_dbg_tag0_wq => tlb_ctl_dbg_tag0_wq, + tlb_ctl_dbg_tag0_gs => tlb_ctl_dbg_tag0_gs, + tlb_ctl_dbg_tag0_pr => tlb_ctl_dbg_tag0_pr, + tlb_ctl_dbg_tag0_atsel => tlb_ctl_dbg_tag0_atsel, + tlb_ctl_dbg_tag5_tlb_write_q => tlb_ctl_dbg_tag5_tlb_write_q, + tlb_ctl_dbg_resv_valid => tlb_ctl_dbg_resv_valid, + tlb_ctl_dbg_set_resv => tlb_ctl_dbg_set_resv, + tlb_ctl_dbg_resv_match_vec_q => tlb_ctl_dbg_resv_match_vec_q, + tlb_ctl_dbg_any_tag_flush_sig => tlb_ctl_dbg_any_tag_flush_sig, + tlb_ctl_dbg_resv0_tag0_lpid_match => tlb_ctl_dbg_resv0_tag0_lpid_match, + tlb_ctl_dbg_resv0_tag0_pid_match => tlb_ctl_dbg_resv0_tag0_pid_match, + tlb_ctl_dbg_resv0_tag0_as_snoop_match => tlb_ctl_dbg_resv0_tag0_as_snoop_match, + tlb_ctl_dbg_resv0_tag0_gs_snoop_match => tlb_ctl_dbg_resv0_tag0_gs_snoop_match, + tlb_ctl_dbg_resv0_tag0_as_tlbwe_match => tlb_ctl_dbg_resv0_tag0_as_tlbwe_match, + tlb_ctl_dbg_resv0_tag0_gs_tlbwe_match => tlb_ctl_dbg_resv0_tag0_gs_tlbwe_match, + tlb_ctl_dbg_resv0_tag0_ind_match => tlb_ctl_dbg_resv0_tag0_ind_match, + tlb_ctl_dbg_resv0_tag0_epn_loc_match => tlb_ctl_dbg_resv0_tag0_epn_loc_match, + tlb_ctl_dbg_resv0_tag0_epn_glob_match => tlb_ctl_dbg_resv0_tag0_epn_glob_match, + tlb_ctl_dbg_resv0_tag0_class_match => tlb_ctl_dbg_resv0_tag0_class_match, + tlb_ctl_dbg_resv1_tag0_lpid_match => tlb_ctl_dbg_resv1_tag0_lpid_match, + tlb_ctl_dbg_resv1_tag0_pid_match => tlb_ctl_dbg_resv1_tag0_pid_match, + tlb_ctl_dbg_resv1_tag0_as_snoop_match => tlb_ctl_dbg_resv1_tag0_as_snoop_match, + tlb_ctl_dbg_resv1_tag0_gs_snoop_match => tlb_ctl_dbg_resv1_tag0_gs_snoop_match, + tlb_ctl_dbg_resv1_tag0_as_tlbwe_match => tlb_ctl_dbg_resv1_tag0_as_tlbwe_match, + tlb_ctl_dbg_resv1_tag0_gs_tlbwe_match => tlb_ctl_dbg_resv1_tag0_gs_tlbwe_match, + tlb_ctl_dbg_resv1_tag0_ind_match => tlb_ctl_dbg_resv1_tag0_ind_match, + tlb_ctl_dbg_resv1_tag0_epn_loc_match => tlb_ctl_dbg_resv1_tag0_epn_loc_match, + tlb_ctl_dbg_resv1_tag0_epn_glob_match => tlb_ctl_dbg_resv1_tag0_epn_glob_match, + tlb_ctl_dbg_resv1_tag0_class_match => tlb_ctl_dbg_resv1_tag0_class_match , + tlb_ctl_dbg_resv2_tag0_lpid_match => tlb_ctl_dbg_resv2_tag0_lpid_match, + tlb_ctl_dbg_resv2_tag0_pid_match => tlb_ctl_dbg_resv2_tag0_pid_match, + tlb_ctl_dbg_resv2_tag0_as_snoop_match => tlb_ctl_dbg_resv2_tag0_as_snoop_match, + tlb_ctl_dbg_resv2_tag0_gs_snoop_match => tlb_ctl_dbg_resv2_tag0_gs_snoop_match, + tlb_ctl_dbg_resv2_tag0_as_tlbwe_match => tlb_ctl_dbg_resv2_tag0_as_tlbwe_match, + tlb_ctl_dbg_resv2_tag0_gs_tlbwe_match => tlb_ctl_dbg_resv2_tag0_gs_tlbwe_match, + tlb_ctl_dbg_resv2_tag0_ind_match => tlb_ctl_dbg_resv2_tag0_ind_match, + tlb_ctl_dbg_resv2_tag0_epn_loc_match => tlb_ctl_dbg_resv2_tag0_epn_loc_match, + tlb_ctl_dbg_resv2_tag0_epn_glob_match => tlb_ctl_dbg_resv2_tag0_epn_glob_match, + tlb_ctl_dbg_resv2_tag0_class_match => tlb_ctl_dbg_resv2_tag0_class_match, + tlb_ctl_dbg_resv3_tag0_lpid_match => tlb_ctl_dbg_resv3_tag0_lpid_match, + tlb_ctl_dbg_resv3_tag0_pid_match => tlb_ctl_dbg_resv3_tag0_pid_match, + tlb_ctl_dbg_resv3_tag0_as_snoop_match => tlb_ctl_dbg_resv3_tag0_as_snoop_match, + tlb_ctl_dbg_resv3_tag0_gs_snoop_match => tlb_ctl_dbg_resv3_tag0_gs_snoop_match, + tlb_ctl_dbg_resv3_tag0_as_tlbwe_match => tlb_ctl_dbg_resv3_tag0_as_tlbwe_match, + tlb_ctl_dbg_resv3_tag0_gs_tlbwe_match => tlb_ctl_dbg_resv3_tag0_gs_tlbwe_match, + tlb_ctl_dbg_resv3_tag0_ind_match => tlb_ctl_dbg_resv3_tag0_ind_match, + tlb_ctl_dbg_resv3_tag0_epn_loc_match => tlb_ctl_dbg_resv3_tag0_epn_loc_match, + tlb_ctl_dbg_resv3_tag0_epn_glob_match => tlb_ctl_dbg_resv3_tag0_epn_glob_match, + tlb_ctl_dbg_resv3_tag0_class_match => tlb_ctl_dbg_resv3_tag0_class_match, + tlb_ctl_dbg_clr_resv_q => tlb_ctl_dbg_clr_resv_q, + tlb_ctl_dbg_clr_resv_terms => tlb_ctl_dbg_clr_resv_terms +); +-- End of mmq_tlb_ctl component instantiation +----------------------------------------------------------------------- +-- TLB Compare Logic Component Instantiation +----------------------------------------------------------------------- +mmq_tlb_cmp: entity work.mmq_tlb_cmp(mmq_tlb_cmp) + generic map ( epn_width => epn_width, + pid_width => pid_width, + pid_width_erat => pid_width_erat, + tlb_tag_width => tlb_tag_width, + mmq_tlb_cmp_cswitch_0to7 => mmq_tlb_cmp_cswitch_0to7, + expand_type => expand_type ) + port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + tc_ccflush_dc => tc_ac_ccflush_dc, + tc_scan_dis_dc_b => tc_ac_scan_dis_dc_b, + tc_scan_diag_dc => tc_ac_scan_diag_dc, + tc_lbist_en_dc => tc_ac_lbist_en_dc, + + lcb_d_mode_dc => lcb_d_mode_dc, + lcb_clkoff_dc_b => lcb_clkoff_dc_b, + lcb_act_dis_dc => lcb_act_dis_dc, + lcb_mpw1_dc_b => lcb_mpw1_dc_b, + lcb_mpw2_dc_b => lcb_mpw2_dc_b, + lcb_delay_lclkr_dc => lcb_delay_lclkr_dc, + + ac_func_scan_in(0) => func_scan_in_int(4), + ac_func_scan_in(1) => func_scan_in_int(5), + ac_func_scan_in(2) => siv_1(tlb_cmp2_offset), + ac_func_scan_out(0) => func_scan_out_int(4), + ac_func_scan_out(1) => func_scan_out_int(5), + ac_func_scan_out(2) => sov_1(tlb_cmp2_offset), + + pc_sg_2 => pc_sg_2(1), + pc_func_sl_thold_2 => pc_func_sl_thold_2(1), + pc_func_slp_sl_thold_2 => pc_func_slp_sl_thold_2(1), + pc_func_slp_nsl_thold_2 => pc_func_slp_nsl_thold_2, + pc_fce_2 => pc_fce_2, + xu_mm_ccr2_notlb_b => xu_mm_ccr2_notlb_b(5), + xu_mm_spr_epcr_dmiuh => xu_mm_spr_epcr_dmiuh, + xu_mm_epcr_dgtmi => xu_mm_epcr_dgtmi_sig, + xu_mm_msr_gs => xu_mm_msr_gs, + xu_mm_msr_pr => xu_mm_msr_pr, + xu_mm_xucr4_mmu_mchk_q => xu_mm_xucr4_mmu_mchk_q, + lpidr => lpidr_sig, + mmucr1 => mmucr1_sig(10 to 18), + mmucr3_0 => mmucr3_0_sig, + mmucr3_1 => mmucr3_1_sig, + mmucr3_2 => mmucr3_2_sig, + mmucr3_3 => mmucr3_3_sig, + mm_iu_ierat_rel_val => mm_iu_ierat_rel_val_sig, + mm_iu_ierat_rel_data => mm_iu_ierat_rel_data_sig, + + mm_xu_derat_rel_val => mm_xu_derat_rel_val_sig, + mm_xu_derat_rel_data => mm_xu_derat_rel_data_sig, + tlb_cmp_ierat_dup_val => tlb_cmp_ierat_dup_val_sig, + tlb_cmp_derat_dup_val => tlb_cmp_derat_dup_val_sig, + tlb_cmp_erat_dup_wait => tlb_cmp_erat_dup_wait_sig, + ierat_req0_pid => ierat_req0_pid_sig, + ierat_req0_as => ierat_req0_as_sig, + ierat_req0_gs => ierat_req0_gs_sig, + ierat_req0_epn => ierat_req0_epn_sig, + ierat_req0_thdid => ierat_req0_thdid_sig, + ierat_req0_valid => ierat_req0_valid_sig, + ierat_req0_nonspec => ierat_req0_nonspec_sig, + ierat_req1_pid => ierat_req1_pid_sig, + ierat_req1_as => ierat_req1_as_sig, + ierat_req1_gs => ierat_req1_gs_sig, + ierat_req1_epn => ierat_req1_epn_sig, + ierat_req1_thdid => ierat_req1_thdid_sig, + ierat_req1_valid => ierat_req1_valid_sig, + ierat_req1_nonspec => ierat_req1_nonspec_sig, + ierat_req2_pid => ierat_req2_pid_sig, + ierat_req2_as => ierat_req2_as_sig, + ierat_req2_gs => ierat_req2_gs_sig, + ierat_req2_epn => ierat_req2_epn_sig, + ierat_req2_thdid => ierat_req2_thdid_sig, + ierat_req2_valid => ierat_req2_valid_sig, + ierat_req2_nonspec => ierat_req2_nonspec_sig, + ierat_req3_pid => ierat_req3_pid_sig, + ierat_req3_as => ierat_req3_as_sig, + ierat_req3_gs => ierat_req3_gs_sig, + ierat_req3_epn => ierat_req3_epn_sig, + ierat_req3_thdid => ierat_req3_thdid_sig, + ierat_req3_valid => ierat_req3_valid_sig, + ierat_req3_nonspec => ierat_req3_nonspec_sig, + ierat_iu4_pid => ierat_iu4_pid_sig, + ierat_iu4_gs => ierat_iu4_gs_sig, + ierat_iu4_as => ierat_iu4_as_sig, + ierat_iu4_epn => ierat_iu4_epn_sig, + ierat_iu4_thdid => ierat_iu4_thdid_sig, + ierat_iu4_valid => ierat_iu4_valid_sig, + + derat_req0_lpid => derat_req0_lpid_sig, + derat_req0_pid => derat_req0_pid_sig, + derat_req0_as => derat_req0_as_sig, + derat_req0_gs => derat_req0_gs_sig, + derat_req0_epn => derat_req0_epn_sig, + derat_req0_thdid => derat_req0_thdid_sig, + derat_req0_valid => derat_req0_valid_sig, + derat_req1_lpid => derat_req1_lpid_sig, + derat_req1_pid => derat_req1_pid_sig, + derat_req1_as => derat_req1_as_sig, + derat_req1_gs => derat_req1_gs_sig, + derat_req1_epn => derat_req1_epn_sig, + derat_req1_thdid => derat_req1_thdid_sig, + derat_req1_valid => derat_req1_valid_sig, + derat_req2_lpid => derat_req2_lpid_sig, + derat_req2_pid => derat_req2_pid_sig, + derat_req2_as => derat_req2_as_sig, + derat_req2_gs => derat_req2_gs_sig, + derat_req2_epn => derat_req2_epn_sig, + derat_req2_thdid => derat_req2_thdid_sig, + derat_req2_valid => derat_req2_valid_sig, + derat_req3_lpid => derat_req3_lpid_sig, + derat_req3_pid => derat_req3_pid_sig, + derat_req3_as => derat_req3_as_sig, + derat_req3_gs => derat_req3_gs_sig, + derat_req3_epn => derat_req3_epn_sig, + derat_req3_thdid => derat_req3_thdid_sig, + derat_req3_valid => derat_req3_valid_sig, + derat_ex5_lpid => derat_ex5_lpid_sig, + derat_ex5_pid => derat_ex5_pid_sig, + derat_ex5_gs => derat_ex5_gs_sig, + derat_ex5_as => derat_ex5_as_sig, + derat_ex5_epn => derat_ex5_epn_sig, + derat_ex5_thdid => derat_ex5_thdid_sig, + derat_ex5_valid => derat_ex5_valid_sig, + + tlb_tag2 => tlb_tag2_sig, + tlb_addr2 => tlb_addr2_sig, + ex6_illeg_instr => ex6_illeg_instr, + + ierat_req_taken => ierat_req_taken, + derat_req_taken => derat_req_taken, + ptereload_req_taken => ptereload_req_taken, + tlb_tag0_type => tlb_tag0_type(0 to 1), + + lru_dataout => lru_dataout(0 to 15), + tlb_dataout => tlb_dataout, + tlb_dataina => tlb_dataina, + tlb_datainb => tlb_datainb, + lru_write => lru_write(0 to 15), + lru_wr_addr => lru_wr_addr, + lru_datain => lru_datain(0 to 15), + lru_tag4_dataout => lru_tag4_dataout, + tlb_tag4_esel => tlb_tag4_esel, + tlb_tag4_wq => tlb_tag4_wq, + tlb_tag4_is => tlb_tag4_is, + tlb_tag4_gs => tlb_tag4_gs, + tlb_tag4_pr => tlb_tag4_pr, + tlb_tag4_hes => tlb_tag4_hes, + tlb_tag4_atsel => tlb_tag4_atsel, + tlb_tag4_pt => tlb_tag4_pt, + tlb_tag4_cmp_hit => tlb_tag4_cmp_hit, + tlb_tag4_way_ind => tlb_tag4_way_ind, + tlb_tag4_ptereload => tlb_tag4_ptereload, + tlb_tag4_endflag => tlb_tag4_endflag, + tlb_tag4_parerr => tlb_tag4_parerr, + tlb_tag5_except => tlb_tag5_except, + + mmucfg_twc => mmucfg_twc, + mmucfg_lrat => mmucfg_lrat, + tlb0cfg_pt => tlb0cfg_pt, + tlb0cfg_gtwe => tlb0cfg_gtwe, + tlb0cfg_ind => tlb0cfg_ind, + + mas2_0_wimge => mas2_0_wimge, + mas3_0_rpnl => mas3_0_rpnl, + mas3_0_ubits => mas3_0_ubits, + mas3_0_usxwr => mas3_0_usxwr, + mas7_0_rpnu => mas7_0_rpnu, + mas8_0_vf => mas8_0_vf, + mas2_1_wimge => mas2_1_wimge, + mas3_1_rpnl => mas3_1_rpnl, + mas3_1_ubits => mas3_1_ubits, + mas3_1_usxwr => mas3_1_usxwr, + mas7_1_rpnu => mas7_1_rpnu, + mas8_1_vf => mas8_1_vf, + mas2_2_wimge => mas2_2_wimge, + mas3_2_rpnl => mas3_2_rpnl, + mas3_2_ubits => mas3_2_ubits, + mas3_2_usxwr => mas3_2_usxwr, + mas7_2_rpnu => mas7_2_rpnu, + mas8_2_vf => mas8_2_vf, + mas2_3_wimge => mas2_3_wimge, + mas3_3_rpnl => mas3_3_rpnl, + mas3_3_ubits => mas3_3_ubits, + mas3_3_usxwr => mas3_3_usxwr, + mas7_3_rpnu => mas7_3_rpnu, + mas8_3_vf => mas8_3_vf, + + tlb_mas0_esel => tlb_mas0_esel, + tlb_mas1_v => tlb_mas1_v, + tlb_mas1_iprot => tlb_mas1_iprot, + tlb_mas1_tid => tlb_mas1_tid, + tlb_mas1_tid_error => tlb_mas1_tid_error, + tlb_mas1_ind => tlb_mas1_ind, + tlb_mas1_ts => tlb_mas1_ts, + tlb_mas1_ts_error => tlb_mas1_ts_error, + tlb_mas1_tsize => tlb_mas1_tsize, + tlb_mas2_epn => tlb_mas2_epn, + tlb_mas2_epn_error => tlb_mas2_epn_error, + tlb_mas2_wimge => tlb_mas2_wimge, + tlb_mas3_rpnl => tlb_mas3_rpnl, + tlb_mas3_ubits => tlb_mas3_ubits, + tlb_mas3_usxwr => tlb_mas3_usxwr, + tlb_mas6_spid => tlb_mas6_spid, + tlb_mas6_isize => tlb_mas6_isize, + tlb_mas6_sind => tlb_mas6_sind, + tlb_mas6_sas => tlb_mas6_sas, + tlb_mas7_rpnu => tlb_mas7_rpnu, + tlb_mas8_tgs => tlb_mas8_tgs, + tlb_mas8_vf => tlb_mas8_vf, + tlb_mas8_tlpid => tlb_mas8_tlpid, + + tlb_mmucr1_een => tlb_mmucr1_een, + tlb_mmucr1_we => tlb_mmucr1_we, + tlb_mmucr3_thdid => tlb_mmucr3_thdid, + tlb_mmucr3_resvattr => tlb_mmucr3_resvattr, + tlb_mmucr3_wlc => tlb_mmucr3_wlc, + tlb_mmucr3_class => tlb_mmucr3_class, + tlb_mmucr3_extclass => tlb_mmucr3_extclass, + tlb_mmucr3_rc => tlb_mmucr3_rc, + tlb_mmucr3_x => tlb_mmucr3_x, + tlb_mas_tlbre => tlb_mas_tlbre, + tlb_mas_tlbsx_hit => tlb_mas_tlbsx_hit, + tlb_mas_tlbsx_miss => tlb_mas_tlbsx_miss, + tlb_mas_dtlb_error => tlb_mas_dtlb_error, + tlb_mas_itlb_error => tlb_mas_itlb_error, + tlb_mas_thdid => tlb_mas_thdid, + lrat_tag3_lpn => lrat_tag3_lpn, + lrat_tag3_rpn => lrat_tag3_rpn, + lrat_tag3_hit_status => lrat_tag3_hit_status, + lrat_tag3_hit_entry => lrat_tag3_hit_entry, + lrat_tag4_lpn => lrat_tag4_lpn, + lrat_tag4_rpn => lrat_tag4_rpn, + lrat_tag4_hit_status => lrat_tag4_hit_status, + lrat_tag4_hit_entry => lrat_tag4_hit_entry, + + tlb_htw_req_valid => tlb_htw_req_valid, + tlb_htw_req_tag => tlb_htw_req_tag, + tlb_htw_req_way => tlb_htw_req_way, + + tlbwe_back_inv_valid => tlbwe_back_inv_valid_sig, + tlbwe_back_inv_thdid => tlbwe_back_inv_thdid_sig, + tlbwe_back_inv_addr => tlbwe_back_inv_addr_sig, + tlbwe_back_inv_attr => tlbwe_back_inv_attr_sig, + + ptereload_req_pte_lat => ptereload_req_pte_lat, + + tlb_ctl_tag2_flush => tlb_ctl_tag2_flush_sig, + tlb_ctl_tag3_flush => tlb_ctl_tag3_flush_sig, + tlb_ctl_tag4_flush => tlb_ctl_tag4_flush_sig, + tlb_resv_match_vec => tlb_resv_match_vec_sig, + + mm_xu_eratmiss_done => mm_xu_eratmiss_done_sig, + mm_xu_tlb_miss => mm_xu_tlb_miss_sig, + mm_xu_tlb_inelig => mm_xu_tlb_inelig_sig, + + mm_xu_lrat_miss => mm_xu_lrat_miss_sig, + mm_xu_pt_fault => mm_xu_pt_fault_sig, + mm_xu_hv_priv => mm_xu_hv_priv_sig, + + mm_xu_esr_pt => mm_xu_esr_pt_sig, + mm_xu_esr_data => mm_xu_esr_data_sig, + mm_xu_esr_epid => mm_xu_esr_epid_sig, + mm_xu_esr_st => mm_xu_esr_st_sig, + + mm_xu_cr0_eq => mm_xu_cr0_eq_sig, + mm_xu_cr0_eq_valid => mm_xu_cr0_eq_valid_sig, + + mm_xu_tlb_multihit_err => mm_xu_tlb_multihit_err, + mm_xu_tlb_par_err => mm_xu_tlb_par_err, + mm_xu_lru_par_err => mm_xu_lru_par_err, + + tlb_delayed_act => tlb_delayed_act(9 to 16), + + tlb_cmp_perf_event_t0 => tlb_cmp_perf_event_t0, + tlb_cmp_perf_event_t1 => tlb_cmp_perf_event_t1, + tlb_cmp_perf_event_t2 => tlb_cmp_perf_event_t2, + tlb_cmp_perf_event_t3 => tlb_cmp_perf_event_t3, + tlb_cmp_perf_state => tlb_cmp_perf_state, + + tlb_cmp_perf_miss_direct => tlb_cmp_perf_miss_direct, + tlb_cmp_perf_hit_indirect => tlb_cmp_perf_hit_indirect, + tlb_cmp_perf_hit_first_page => tlb_cmp_perf_hit_first_page, + tlb_cmp_perf_ptereload_noexcep => tlb_cmp_perf_ptereload_noexcep, + tlb_cmp_perf_lrat_request => tlb_cmp_perf_lrat_request, + tlb_cmp_perf_lrat_miss => tlb_cmp_perf_lrat_miss, + tlb_cmp_perf_pt_fault => tlb_cmp_perf_pt_fault, + tlb_cmp_perf_pt_inelig => tlb_cmp_perf_pt_inelig, + + tlb_cmp_dbg_tag4 => tlb_cmp_dbg_tag4, + tlb_cmp_dbg_tag4_wayhit => tlb_cmp_dbg_tag4_wayhit, + tlb_cmp_dbg_addr4 => tlb_cmp_dbg_addr4, + tlb_cmp_dbg_tag4_way => tlb_cmp_dbg_tag4_way, + tlb_cmp_dbg_tag4_parerr => tlb_cmp_dbg_tag4_parerr, + tlb_cmp_dbg_tag4_lru_dataout_q => tlb_cmp_dbg_tag4_lru_dataout_q, + tlb_cmp_dbg_tag5_tlb_datain_q => tlb_cmp_dbg_tag5_tlb_datain_q, + tlb_cmp_dbg_tag5_lru_datain_q => tlb_cmp_dbg_tag5_lru_datain_q, + tlb_cmp_dbg_tag5_lru_write => tlb_cmp_dbg_tag5_lru_write, + tlb_cmp_dbg_tag5_any_exception => tlb_cmp_dbg_tag5_any_exception, + tlb_cmp_dbg_tag5_except_type_q => tlb_cmp_dbg_tag5_except_type_q, + tlb_cmp_dbg_tag5_except_thdid_q => tlb_cmp_dbg_tag5_except_thdid_q, + tlb_cmp_dbg_tag5_erat_rel_val => tlb_cmp_dbg_tag5_erat_rel_val, + tlb_cmp_dbg_tag5_erat_rel_data => tlb_cmp_dbg_tag5_erat_rel_data, + tlb_cmp_dbg_erat_dup_q => tlb_cmp_dbg_erat_dup_q, + tlb_cmp_dbg_addr_enable => tlb_cmp_dbg_addr_enable, + tlb_cmp_dbg_pgsize_enable => tlb_cmp_dbg_pgsize_enable, + tlb_cmp_dbg_class_enable => tlb_cmp_dbg_class_enable, + tlb_cmp_dbg_extclass_enable => tlb_cmp_dbg_extclass_enable, + tlb_cmp_dbg_state_enable => tlb_cmp_dbg_state_enable, + tlb_cmp_dbg_thdid_enable => tlb_cmp_dbg_thdid_enable, + tlb_cmp_dbg_pid_enable => tlb_cmp_dbg_pid_enable, + tlb_cmp_dbg_lpid_enable => tlb_cmp_dbg_lpid_enable, + tlb_cmp_dbg_ind_enable => tlb_cmp_dbg_ind_enable, + tlb_cmp_dbg_iprot_enable => tlb_cmp_dbg_iprot_enable, + tlb_cmp_dbg_way0_entry_v => tlb_cmp_dbg_way0_entry_v, + tlb_cmp_dbg_way0_addr_match => tlb_cmp_dbg_way0_addr_match, + tlb_cmp_dbg_way0_pgsize_match => tlb_cmp_dbg_way0_pgsize_match, + tlb_cmp_dbg_way0_class_match => tlb_cmp_dbg_way0_class_match, + tlb_cmp_dbg_way0_extclass_match => tlb_cmp_dbg_way0_extclass_match, + tlb_cmp_dbg_way0_state_match => tlb_cmp_dbg_way0_state_match, + tlb_cmp_dbg_way0_thdid_match => tlb_cmp_dbg_way0_thdid_match, + tlb_cmp_dbg_way0_pid_match => tlb_cmp_dbg_way0_pid_match, + tlb_cmp_dbg_way0_lpid_match => tlb_cmp_dbg_way0_lpid_match, + tlb_cmp_dbg_way0_ind_match => tlb_cmp_dbg_way0_ind_match, + tlb_cmp_dbg_way0_iprot_match => tlb_cmp_dbg_way0_iprot_match, + tlb_cmp_dbg_way1_entry_v => tlb_cmp_dbg_way1_entry_v, + tlb_cmp_dbg_way1_addr_match => tlb_cmp_dbg_way1_addr_match, + tlb_cmp_dbg_way1_pgsize_match => tlb_cmp_dbg_way1_pgsize_match, + tlb_cmp_dbg_way1_class_match => tlb_cmp_dbg_way1_class_match, + tlb_cmp_dbg_way1_extclass_match => tlb_cmp_dbg_way1_extclass_match, + tlb_cmp_dbg_way1_state_match => tlb_cmp_dbg_way1_state_match, + tlb_cmp_dbg_way1_thdid_match => tlb_cmp_dbg_way1_thdid_match, + tlb_cmp_dbg_way1_pid_match => tlb_cmp_dbg_way1_pid_match, + tlb_cmp_dbg_way1_lpid_match => tlb_cmp_dbg_way1_lpid_match, + tlb_cmp_dbg_way1_ind_match => tlb_cmp_dbg_way1_ind_match, + tlb_cmp_dbg_way1_iprot_match => tlb_cmp_dbg_way1_iprot_match, + tlb_cmp_dbg_way2_entry_v => tlb_cmp_dbg_way2_entry_v, + tlb_cmp_dbg_way2_addr_match => tlb_cmp_dbg_way2_addr_match, + tlb_cmp_dbg_way2_pgsize_match => tlb_cmp_dbg_way2_pgsize_match, + tlb_cmp_dbg_way2_class_match => tlb_cmp_dbg_way2_class_match, + tlb_cmp_dbg_way2_extclass_match => tlb_cmp_dbg_way2_extclass_match, + tlb_cmp_dbg_way2_state_match => tlb_cmp_dbg_way2_state_match, + tlb_cmp_dbg_way2_thdid_match => tlb_cmp_dbg_way2_thdid_match, + tlb_cmp_dbg_way2_pid_match => tlb_cmp_dbg_way2_pid_match, + tlb_cmp_dbg_way2_lpid_match => tlb_cmp_dbg_way2_lpid_match, + tlb_cmp_dbg_way2_ind_match => tlb_cmp_dbg_way2_ind_match, + tlb_cmp_dbg_way2_iprot_match => tlb_cmp_dbg_way2_iprot_match, + tlb_cmp_dbg_way3_entry_v => tlb_cmp_dbg_way3_entry_v, + tlb_cmp_dbg_way3_addr_match => tlb_cmp_dbg_way3_addr_match, + tlb_cmp_dbg_way3_pgsize_match => tlb_cmp_dbg_way3_pgsize_match, + tlb_cmp_dbg_way3_class_match => tlb_cmp_dbg_way3_class_match, + tlb_cmp_dbg_way3_extclass_match => tlb_cmp_dbg_way3_extclass_match, + tlb_cmp_dbg_way3_state_match => tlb_cmp_dbg_way3_state_match, + tlb_cmp_dbg_way3_thdid_match => tlb_cmp_dbg_way3_thdid_match, + tlb_cmp_dbg_way3_pid_match => tlb_cmp_dbg_way3_pid_match, + tlb_cmp_dbg_way3_lpid_match => tlb_cmp_dbg_way3_lpid_match, + tlb_cmp_dbg_way3_ind_match => tlb_cmp_dbg_way3_ind_match, + tlb_cmp_dbg_way3_iprot_match => tlb_cmp_dbg_way3_iprot_match + +); +-- End of mmq_tlb_cmp component instantiation +-- End of mmq_tlb_cmp component instantiation +mmq_tlb_lrat: entity work.mmq_tlb_lrat(mmq_tlb_lrat) + generic map ( epn_width => epn_width, + spr_data_width => spr_data_width, + real_addr_width => real_addr_width, + rpn_width => rpn_width, + lpid_width => lpid_width, + expand_type => expand_type ) + port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + tc_ccflush_dc => tc_ac_ccflush_dc, + tc_scan_dis_dc_b => tc_ac_scan_dis_dc_b, + tc_scan_diag_dc => tc_ac_scan_diag_dc, + tc_lbist_en_dc => tc_ac_lbist_en_dc, + + lcb_d_mode_dc => lcb_d_mode_dc, + lcb_clkoff_dc_b => lcb_clkoff_dc_b, + lcb_act_dis_dc => lcb_act_dis_dc, + lcb_mpw1_dc_b => lcb_mpw1_dc_b, + lcb_mpw2_dc_b => lcb_mpw2_dc_b, + lcb_delay_lclkr_dc => lcb_delay_lclkr_dc, + + ac_func_scan_in => func_scan_in_int(6), + ac_func_scan_out => func_scan_out_int(6), + + pc_sg_2 => pc_sg_2(1), + pc_func_sl_thold_2 => pc_func_sl_thold_2(1), + pc_func_slp_sl_thold_2 => pc_func_slp_sl_thold_2(1), + + xu_mm_ccr2_notlb_b => xu_mm_ccr2_notlb_b(6), + tlb_delayed_act => tlb_delayed_act(20 to 23), + mmucr2_act_override => mmucr2_sig(3), + + tlb_ctl_ex3_valid => tlb_ctl_ex3_valid_sig, + tlb_ctl_ex3_ttype => tlb_ctl_ex3_ttype_sig, + xu_ex3_flush => xu_ex3_flush, + xu_ex4_flush => xu_ex4_flush, + xu_ex5_flush => xu_ex5_flush, + tlb_tag0_epn => tlb_tag0_epn(64-real_addr_width to 51), + tlb_tag0_thdid => tlb_tag0_thdid, + tlb_tag0_type => tlb_tag0_type, + tlb_tag0_lpid => tlb_tag0_lpid, + tlb_tag0_atsel => tlb_tag0_atsel, + tlb_tag0_size => tlb_tag0_size, + tlb_tag0_addr_cap => tlb_tag0_addr_cap, + ex6_illeg_instr => ex6_illeg_instr, + + pte_tag0_lpn => pte_tag0_lpn(64-real_addr_width to 51), + pte_tag0_lpid => pte_tag0_lpid, + mas0_0_atsel => mas0_0_atsel, + mas0_0_esel => mas0_0_esel, + mas0_0_hes => mas0_0_hes, + mas0_0_wq => mas0_0_wq, + mas1_0_v => mas1_0_v, + mas1_0_tsize => mas1_0_tsize, + mas2_0_epn => mas2_0_epn(64-real_addr_width to 51), + mas7_0_rpnu => mas7_0_rpnu, + mas3_0_rpnl => mas3_0_rpnl(32 to 51), + mas8_0_tlpid => mas8_0_tlpid, + mmucr3_0_x => mmucr3_0_sig(49), + mas0_1_atsel => mas0_1_atsel, + mas0_1_esel => mas0_1_esel, + mas0_1_hes => mas0_1_hes, + mas0_1_wq => mas0_1_wq, + mas1_1_v => mas1_1_v, + mas1_1_tsize => mas1_1_tsize, + mas2_1_epn => mas2_1_epn(64-real_addr_width to 51), + mas7_1_rpnu => mas7_1_rpnu, + mas3_1_rpnl => mas3_1_rpnl(32 to 51), + mas8_1_tlpid => mas8_1_tlpid, + mmucr3_1_x => mmucr3_1_sig(49), + mas0_2_atsel => mas0_2_atsel, + mas0_2_esel => mas0_2_esel, + mas0_2_hes => mas0_2_hes, + mas0_2_wq => mas0_2_wq, + mas1_2_v => mas1_2_v, + mas1_2_tsize => mas1_2_tsize, + mas2_2_epn => mas2_2_epn(64-real_addr_width to 51), + mas7_2_rpnu => mas7_2_rpnu, + mas3_2_rpnl => mas3_2_rpnl(32 to 51), + mas8_2_tlpid => mas8_2_tlpid, + mmucr3_2_x => mmucr3_2_sig(49), + mas0_3_atsel => mas0_3_atsel, + mas0_3_esel => mas0_3_esel, + mas0_3_hes => mas0_3_hes, + mas0_3_wq => mas0_3_wq, + mas1_3_v => mas1_3_v, + mas1_3_tsize => mas1_3_tsize, + mas2_3_epn => mas2_3_epn(64-real_addr_width to 51), + mas7_3_rpnu => mas7_3_rpnu, + mas3_3_rpnl => mas3_3_rpnl(32 to 51), + mas8_3_tlpid => mas8_3_tlpid, + mmucr3_3_x => mmucr3_3_sig(49), + + lrat_mmucr3_x => lrat_mmucr3_x, + lrat_mas0_esel => lrat_mas0_esel, + lrat_mas1_v => lrat_mas1_v, + lrat_mas1_tsize => lrat_mas1_tsize, + lrat_mas2_epn => lrat_mas2_epn, + lrat_mas3_rpnl => lrat_mas3_rpnl, + lrat_mas7_rpnu => lrat_mas7_rpnu, + lrat_mas8_tlpid => lrat_mas8_tlpid, + lrat_mas_tlbre => lrat_mas_tlbre, + lrat_mas_tlbsx_hit => lrat_mas_tlbsx_hit, + lrat_mas_tlbsx_miss => lrat_mas_tlbsx_miss, + lrat_mas_thdid => lrat_mas_thdid, + + lrat_tag3_lpn => lrat_tag3_lpn, + lrat_tag3_rpn => lrat_tag3_rpn, + lrat_tag3_hit_status => lrat_tag3_hit_status, + lrat_tag3_hit_entry => lrat_tag3_hit_entry, + lrat_tag4_lpn => lrat_tag4_lpn, + lrat_tag4_rpn => lrat_tag4_rpn, + lrat_tag4_hit_status => lrat_tag4_hit_status, + lrat_tag4_hit_entry => lrat_tag4_hit_entry, + + lrat_dbg_tag1_addr_enable => lrat_dbg_tag1_addr_enable, + lrat_dbg_tag2_matchline_q => lrat_dbg_tag2_matchline_q, + lrat_dbg_entry0_addr_match => lrat_dbg_entry0_addr_match, + lrat_dbg_entry0_lpid_match => lrat_dbg_entry0_lpid_match, + lrat_dbg_entry0_entry_v => lrat_dbg_entry0_entry_v, + lrat_dbg_entry0_entry_x => lrat_dbg_entry0_entry_x, + lrat_dbg_entry0_size => lrat_dbg_entry0_size, + lrat_dbg_entry1_addr_match => lrat_dbg_entry1_addr_match, + lrat_dbg_entry1_lpid_match => lrat_dbg_entry1_lpid_match, + lrat_dbg_entry1_entry_v => lrat_dbg_entry1_entry_v, + lrat_dbg_entry1_entry_x => lrat_dbg_entry1_entry_x, + lrat_dbg_entry1_size => lrat_dbg_entry1_size, + lrat_dbg_entry2_addr_match => lrat_dbg_entry2_addr_match, + lrat_dbg_entry2_lpid_match => lrat_dbg_entry2_lpid_match, + lrat_dbg_entry2_entry_v => lrat_dbg_entry2_entry_v, + lrat_dbg_entry2_entry_x => lrat_dbg_entry2_entry_x, + lrat_dbg_entry2_size => lrat_dbg_entry2_size, + lrat_dbg_entry3_addr_match => lrat_dbg_entry3_addr_match, + lrat_dbg_entry3_lpid_match => lrat_dbg_entry3_lpid_match, + lrat_dbg_entry3_entry_v => lrat_dbg_entry3_entry_v, + lrat_dbg_entry3_entry_x => lrat_dbg_entry3_entry_x, + lrat_dbg_entry3_size => lrat_dbg_entry3_size, + lrat_dbg_entry4_addr_match => lrat_dbg_entry4_addr_match, + lrat_dbg_entry4_lpid_match => lrat_dbg_entry4_lpid_match, + lrat_dbg_entry4_entry_v => lrat_dbg_entry4_entry_v, + lrat_dbg_entry4_entry_x => lrat_dbg_entry4_entry_x, + lrat_dbg_entry4_size => lrat_dbg_entry4_size, + lrat_dbg_entry5_addr_match => lrat_dbg_entry5_addr_match, + lrat_dbg_entry5_lpid_match => lrat_dbg_entry5_lpid_match, + lrat_dbg_entry5_entry_v => lrat_dbg_entry5_entry_v, + lrat_dbg_entry5_entry_x => lrat_dbg_entry5_entry_x, + lrat_dbg_entry5_size => lrat_dbg_entry5_size, + lrat_dbg_entry6_addr_match => lrat_dbg_entry6_addr_match, + lrat_dbg_entry6_lpid_match => lrat_dbg_entry6_lpid_match, + lrat_dbg_entry6_entry_v => lrat_dbg_entry6_entry_v, + lrat_dbg_entry6_entry_x => lrat_dbg_entry6_entry_x, + lrat_dbg_entry6_size => lrat_dbg_entry6_size, + lrat_dbg_entry7_addr_match => lrat_dbg_entry7_addr_match, + lrat_dbg_entry7_lpid_match => lrat_dbg_entry7_lpid_match, + lrat_dbg_entry7_entry_v => lrat_dbg_entry7_entry_v, + lrat_dbg_entry7_entry_x => lrat_dbg_entry7_entry_x, + lrat_dbg_entry7_size => lrat_dbg_entry7_size +); +-- End of mmq_tlb_lrat component instantiation +mmq_htw: entity work.mmq_htw(mmq_htw) + generic map ( thdid_width => thdid_width, + pid_width => pid_width, + lpid_width => lpid_width, + epn_width => epn_width, + real_addr_width => real_addr_width, + rpn_width => rpn_width, + tlb_way_width => tlb_way_width, + tlb_word_width => tlb_word_width, + tlb_tag_width => tlb_tag_width, + pte_width => pte_width, + expand_type => expand_type ) + port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + tc_ccflush_dc => tc_ac_ccflush_dc, + tc_scan_dis_dc_b => tc_ac_scan_dis_dc_b, + tc_scan_diag_dc => tc_ac_scan_diag_dc, + tc_lbist_en_dc => tc_ac_lbist_en_dc, + + lcb_d_mode_dc => lcb_d_mode_dc, + lcb_clkoff_dc_b => lcb_clkoff_dc_b, + lcb_act_dis_dc => lcb_act_dis_dc, + lcb_mpw1_dc_b => lcb_mpw1_dc_b, + lcb_mpw2_dc_b => lcb_mpw2_dc_b, + lcb_delay_lclkr_dc => lcb_delay_lclkr_dc, + + ac_func_scan_in(0 to 1) => func_scan_in_int(7 to 8), + ac_func_scan_out(0 to 1) => func_scan_out_int(7 to 8), + + pc_sg_2 => pc_sg_2(1), + pc_func_sl_thold_2 => pc_func_sl_thold_2(1), + pc_func_slp_sl_thold_2 => pc_func_slp_sl_thold_2(1), + + xu_mm_ccr2_notlb_b => xu_mm_ccr2_notlb_b(7), + + tlb_delayed_act => tlb_delayed_act(24 to 28), + mmucr2_act_override => mmucr2_sig(4), + + tlb_ctl_tag2_flush => tlb_ctl_tag2_flush_sig, + tlb_ctl_tag3_flush => tlb_ctl_tag3_flush_sig, + tlb_ctl_tag4_flush => tlb_ctl_tag4_flush_sig, + + tlb_tag2 => tlb_tag2_sig, + tlb_tag5_except => tlb_tag5_except, + + tlb_htw_req_valid => tlb_htw_req_valid, + tlb_htw_req_tag => tlb_htw_req_tag, + tlb_htw_req_way => tlb_htw_req_way, + htw_lsu_req_valid => htw_lsu_req_valid, + htw_lsu_thdid => htw_lsu_thdid, + htw_dbg_lsu_thdid => htw_dbg_lsu_thdid, + htw_lsu_ttype => htw_lsu_ttype, + htw_lsu_wimge => htw_lsu_wimge, + htw_lsu_u => htw_lsu_u, + htw_lsu_addr => htw_lsu_addr, + htw_lsu_req_taken => htw_lsu_req_taken, + htw_quiesce => htw_quiesce_sig, + + htw_req0_valid => htw_req0_valid, + htw_req0_thdid => htw_req0_thdid, + htw_req0_type => htw_req0_type, + htw_req1_valid => htw_req1_valid, + htw_req1_thdid => htw_req1_thdid, + htw_req1_type => htw_req1_type, + htw_req2_valid => htw_req2_valid, + htw_req2_thdid => htw_req2_thdid, + htw_req2_type => htw_req2_type, + htw_req3_valid => htw_req3_valid, + htw_req3_thdid => htw_req3_thdid, + htw_req3_type => htw_req3_type, + ptereload_req_valid => ptereload_req_valid, + ptereload_req_tag => ptereload_req_tag, + ptereload_req_pte => ptereload_req_pte, + ptereload_req_taken => ptereload_req_taken, + an_ac_reld_core_tag => an_ac_reld_core_tag, + an_ac_reld_data => an_ac_reld_data, + an_ac_reld_data_vld => an_ac_reld_data_vld, + an_ac_reld_ecc_err => an_ac_reld_ecc_err, + an_ac_reld_ecc_err_ue => an_ac_reld_ecc_err_ue, + an_ac_reld_qw => an_ac_reld_qw(58 to 59), + an_ac_reld_ditc => an_ac_reld_ditc, + an_ac_reld_crit_qw => an_ac_reld_crit_qw, + + htw_dbg_seq_idle => htw_dbg_seq_idle, + htw_dbg_pte0_seq_idle => htw_dbg_pte0_seq_idle, + htw_dbg_pte1_seq_idle => htw_dbg_pte1_seq_idle, + htw_dbg_seq_q => htw_dbg_seq_q, + htw_dbg_inptr_q => htw_dbg_inptr_q, + htw_dbg_pte0_seq_q => htw_dbg_pte0_seq_q, + htw_dbg_pte1_seq_q => htw_dbg_pte1_seq_q, + htw_dbg_ptereload_ptr_q => htw_dbg_ptereload_ptr_q, + htw_dbg_lsuptr_q => htw_dbg_lsuptr_q, + htw_dbg_req_valid_q => htw_dbg_req_valid_q, + htw_dbg_resv_valid_vec => htw_dbg_resv_valid_vec, + htw_dbg_tag4_clr_resv_q => htw_dbg_tag4_clr_resv_q, + htw_dbg_tag4_clr_resv_terms => htw_dbg_tag4_clr_resv_terms, + htw_dbg_pte0_score_ptr_q => htw_dbg_pte0_score_ptr_q, + htw_dbg_pte0_score_cl_offset_q => htw_dbg_pte0_score_cl_offset_q, + htw_dbg_pte0_score_error_q => htw_dbg_pte0_score_error_q, + htw_dbg_pte0_score_qwbeat_q => htw_dbg_pte0_score_qwbeat_q, + htw_dbg_pte0_score_pending_q => htw_dbg_pte0_score_pending_q, + htw_dbg_pte0_score_ibit_q => htw_dbg_pte0_score_ibit_q, + htw_dbg_pte0_score_dataval_q => htw_dbg_pte0_score_dataval_q, + htw_dbg_pte0_reld_for_me_tm1 => htw_dbg_pte0_reld_for_me_tm1, + htw_dbg_pte1_score_ptr_q => htw_dbg_pte1_score_ptr_q, + htw_dbg_pte1_score_cl_offset_q => htw_dbg_pte1_score_cl_offset_q, + htw_dbg_pte1_score_error_q => htw_dbg_pte1_score_error_q, + htw_dbg_pte1_score_qwbeat_q => htw_dbg_pte1_score_qwbeat_q, + htw_dbg_pte1_score_pending_q => htw_dbg_pte1_score_pending_q, + htw_dbg_pte1_score_ibit_q => htw_dbg_pte1_score_ibit_q, + htw_dbg_pte1_score_dataval_q => htw_dbg_pte1_score_dataval_q, + htw_dbg_pte1_reld_for_me_tm1 => htw_dbg_pte1_reld_for_me_tm1 + + ); +-- End of mmq_htw component instantiation +end generate tlb_gen_logic; +tlb_gen_noarrays: if expand_tlb_type = 1 generate +tlb_dataout(0 to tlb_way_width-1) <= tlb_dataina; +tlb_dataout(tlb_way_width to 2*tlb_way_width-1) <= tlb_dataina; +tlb_dataout(2*tlb_way_width to 3*tlb_way_width-1) <= tlb_dataina; +tlb_dataout(3*tlb_way_width to 4*tlb_way_width-1) <= tlb_dataina; +lru_dataout <= lru_datain; +time_scan_int(1 to 5) <= (others => '0'); +repr_scan_int(1 to 5) <= (others => '0'); +abst_scan_int(1 to 6) <= (others => '0'); +end generate tlb_gen_noarrays; +tlb_gen_instance: if expand_tlb_type = 2 generate +----------------------------------------------------------------------- +-- TLB Instantiation +----------------------------------------------------------------------- +tlb_array0: entity tri.tri_128x168_1w_0(tri_128x168_1w_0) + generic map ( expand_type => expand_type ) + port map( + gnd => gnd, + vdd => vdd, + vcs => vcs, + nclk => nclk, + act => tlb_delayed_act(17), + ccflush_dc => tc_ac_ccflush_dc, + scan_dis_dc_b => tc_ac_scan_dis_dc_b, + scan_diag_dc => tc_ac_scan_diag_dc, + repr_scan_in => repr_scan_int(0), + time_scan_in => time_scan_int(0), + abst_scan_in => abst_scan_int(0), + repr_scan_out => repr_scan_int(1), + time_scan_out => time_scan_int(1), + abst_scan_out => abst_scan_int(1), + lcb_d_mode_dc => g6t_gptr_lcb_d_mode_dc, + lcb_clkoff_dc_b => g6t_gptr_lcb_clkoff_dc_b, + lcb_act_dis_dc => g6t_gptr_lcb_act_dis_dc, + lcb_mpw1_dc_b => g6t_gptr_lcb_mpw1_dc_b, + lcb_mpw2_dc_b => g6t_gptr_lcb_mpw2_dc_b, + lcb_delay_lclkr_dc => g6t_gptr_lcb_delay_lclkr_dc, + + tri_lcb_mpw1_dc_b => lcb_mpw1_dc_b(0), + tri_lcb_mpw2_dc_b => lcb_mpw2_dc_b, + tri_lcb_delay_lclkr_dc => lcb_delay_lclkr_dc(0), + tri_lcb_clkoff_dc_b => lcb_clkoff_dc_b, + tri_lcb_act_dis_dc => lcb_act_dis_dc, + + lcb_sg_1 => pc_sg_1(0), + lcb_time_sg_0 => pc_sg_0(0), + lcb_repr_sg_0 => pc_sg_0(0), + lcb_abst_sl_thold_0 => pc_abst_sl_thold_0, + lcb_repr_sl_thold_0 => pc_repr_sl_thold_0, + lcb_time_sl_thold_0 => pc_time_sl_thold_0, + lcb_ary_nsl_thold_0 => pc_ary_slp_nsl_thold_0, + tc_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc, + abist_en_1 => pc_mm_abist_ena_dc, + din_abist => pc_mm_abist_di_g6t_2r_q, + abist_cmp_en => pc_mm_abist_wl128_comp_ena_q, + abist_raw_b_dc => pc_mm_abist_raw_dc_b, + data_cmp_abist => pc_mm_abist_dcomp_g6t_2r_q, + addr_abist => pc_mm_abist_raddr_0_q(3 to 9), + r_wb_abist => pc_mm_abist_g6t_r_wb_q, + lcb_bolt_sl_thold_0 => pc_mm_bolt_sl_thold_0, + pc_bo_enable_2 => pc_mm_bo_enable_2, + pc_bo_reset => pc_mm_bo_reset, + pc_bo_unload => pc_mm_bo_unload, + pc_bo_repair => pc_mm_bo_repair, + pc_bo_shdata => pc_mm_bo_shdata, + pc_bo_select => pc_mm_bo_select(0), + bo_pc_failout => mm_pc_bo_fail(0), + bo_pc_diagloop => mm_pc_bo_diagout(0), + + write_enable => tlb_write(0), + addr => tlb_addr, + data_in => tlb_dataina, + data_out => tlb_dataout(0 to tlb_way_width-1) +); +tlb_array1: entity tri.tri_128x168_1w_0(tri_128x168_1w_0) + generic map ( expand_type => expand_type ) + port map( + gnd => gnd, + vdd => vdd, + vcs => vcs, + nclk => nclk, + act => tlb_delayed_act(17), + + ccflush_dc => tc_ac_ccflush_dc, + scan_dis_dc_b => tc_ac_scan_dis_dc_b, + scan_diag_dc => tc_ac_scan_diag_dc, + repr_scan_in => repr_scan_int(1), + time_scan_in => time_scan_int(1), + abst_scan_in => abst_scan_int(1), + repr_scan_out => repr_scan_int(2), + time_scan_out => time_scan_int(2), + abst_scan_out => abst_scan_int(2), + lcb_d_mode_dc => g6t_gptr_lcb_d_mode_dc, + lcb_clkoff_dc_b => g6t_gptr_lcb_clkoff_dc_b, + lcb_act_dis_dc => g6t_gptr_lcb_act_dis_dc, + lcb_mpw1_dc_b => g6t_gptr_lcb_mpw1_dc_b, + lcb_mpw2_dc_b => g6t_gptr_lcb_mpw2_dc_b, + lcb_delay_lclkr_dc => g6t_gptr_lcb_delay_lclkr_dc, + + tri_lcb_mpw1_dc_b => lcb_mpw1_dc_b(0), + tri_lcb_mpw2_dc_b => lcb_mpw2_dc_b, + tri_lcb_delay_lclkr_dc => lcb_delay_lclkr_dc(0), + tri_lcb_clkoff_dc_b => lcb_clkoff_dc_b, + tri_lcb_act_dis_dc => lcb_act_dis_dc, + + lcb_sg_1 => pc_sg_1(0), + lcb_time_sg_0 => pc_sg_0(0), + lcb_repr_sg_0 => pc_sg_0(0), + lcb_abst_sl_thold_0 => pc_abst_sl_thold_0, + lcb_repr_sl_thold_0 => pc_repr_sl_thold_0, + lcb_time_sl_thold_0 => pc_time_sl_thold_0, + lcb_ary_nsl_thold_0 => pc_ary_slp_nsl_thold_0, + tc_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc, + abist_en_1 => pc_mm_abist_ena_dc, + din_abist => pc_mm_abist_di_g6t_2r_q, + abist_cmp_en => pc_mm_abist_wl128_comp_ena_q, + abist_raw_b_dc => pc_mm_abist_raw_dc_b, + data_cmp_abist => pc_mm_abist_dcomp_g6t_2r_q, + addr_abist => pc_mm_abist_raddr_0_q(3 to 9), + r_wb_abist => pc_mm_abist_g6t_r_wb_q, + lcb_bolt_sl_thold_0 => pc_mm_bolt_sl_thold_0, + pc_bo_enable_2 => pc_mm_bo_enable_2, + pc_bo_reset => pc_mm_bo_reset, + pc_bo_unload => pc_mm_bo_unload, + pc_bo_repair => pc_mm_bo_repair, + pc_bo_shdata => pc_mm_bo_shdata, + pc_bo_select => pc_mm_bo_select(1), + bo_pc_failout => mm_pc_bo_fail(1), + bo_pc_diagloop => mm_pc_bo_diagout(1), + + write_enable => tlb_write(1), + addr => tlb_addr, + data_in => tlb_dataina, + data_out => tlb_dataout(tlb_way_width to 2*tlb_way_width-1) +); +tlb_array2: entity tri.tri_128x168_1w_0(tri_128x168_1w_0) + generic map ( expand_type => expand_type ) + port map( + gnd => gnd, + vdd => vdd, + vcs => vcs, + nclk => nclk, + act => tlb_delayed_act(18), + ccflush_dc => tc_ac_ccflush_dc, + scan_dis_dc_b => tc_ac_scan_dis_dc_b, + scan_diag_dc => tc_ac_scan_diag_dc, + repr_scan_in => repr_scan_int(2), + time_scan_in => time_scan_int(2), + abst_scan_in => abst_scan_int(3), + repr_scan_out => repr_scan_int(3), + time_scan_out => time_scan_int(3), + abst_scan_out => abst_scan_int(4), + lcb_d_mode_dc => g6t_gptr_lcb_d_mode_dc, + lcb_clkoff_dc_b => g6t_gptr_lcb_clkoff_dc_b, + lcb_act_dis_dc => g6t_gptr_lcb_act_dis_dc, + lcb_mpw1_dc_b => g6t_gptr_lcb_mpw1_dc_b, + lcb_mpw2_dc_b => g6t_gptr_lcb_mpw2_dc_b, + lcb_delay_lclkr_dc => g6t_gptr_lcb_delay_lclkr_dc, + + tri_lcb_mpw1_dc_b => lcb_mpw1_dc_b(0), + tri_lcb_mpw2_dc_b => lcb_mpw2_dc_b, + tri_lcb_delay_lclkr_dc => lcb_delay_lclkr_dc(0), + tri_lcb_clkoff_dc_b => lcb_clkoff_dc_b, + tri_lcb_act_dis_dc => lcb_act_dis_dc, + + lcb_sg_1 => pc_sg_1(1), + lcb_time_sg_0 => pc_sg_0(1), + lcb_repr_sg_0 => pc_sg_0(1), + lcb_abst_sl_thold_0 => pc_abst_sl_thold_0, + lcb_repr_sl_thold_0 => pc_repr_sl_thold_0, + lcb_time_sl_thold_0 => pc_time_sl_thold_0, + lcb_ary_nsl_thold_0 => pc_ary_slp_nsl_thold_0, + tc_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc, + abist_en_1 => pc_mm_abist_ena_dc, + din_abist => pc_mm_abist_di_g6t_2r_q, + abist_cmp_en => pc_mm_abist_wl128_comp_ena_q, + abist_raw_b_dc => pc_mm_abist_raw_dc_b, + data_cmp_abist => pc_mm_abist_dcomp_g6t_2r_q, + addr_abist => pc_mm_abist_raddr_0_q(3 to 9), + r_wb_abist => pc_mm_abist_g6t_r_wb_q, + lcb_bolt_sl_thold_0 => pc_mm_bolt_sl_thold_0, + pc_bo_enable_2 => pc_mm_bo_enable_2, + pc_bo_reset => pc_mm_bo_reset, + pc_bo_unload => pc_mm_bo_unload, + pc_bo_repair => pc_mm_bo_repair, + pc_bo_shdata => pc_mm_bo_shdata, + pc_bo_select => pc_mm_bo_select(2), + bo_pc_failout => mm_pc_bo_fail(2), + bo_pc_diagloop => mm_pc_bo_diagout(2), + + write_enable => tlb_write(2), + addr => tlb_addr, + data_in => tlb_datainb, + data_out => tlb_dataout(2*tlb_way_width to 3*tlb_way_width-1) +); +tlb_array3: entity tri.tri_128x168_1w_0(tri_128x168_1w_0) + generic map ( expand_type => expand_type ) + port map( + gnd => gnd, + vdd => vdd, + vcs => vcs, + nclk => nclk, + act => tlb_delayed_act(18), + + ccflush_dc => tc_ac_ccflush_dc, + scan_dis_dc_b => tc_ac_scan_dis_dc_b, + scan_diag_dc => tc_ac_scan_diag_dc, + repr_scan_in => repr_scan_int(3), + time_scan_in => time_scan_int(3), + abst_scan_in => abst_scan_int(4), + repr_scan_out => repr_scan_int(4), + time_scan_out => time_scan_int(4), + abst_scan_out => abst_scan_int(5), + lcb_d_mode_dc => g6t_gptr_lcb_d_mode_dc, + lcb_clkoff_dc_b => g6t_gptr_lcb_clkoff_dc_b, + lcb_act_dis_dc => g6t_gptr_lcb_act_dis_dc, + lcb_mpw1_dc_b => g6t_gptr_lcb_mpw1_dc_b, + lcb_mpw2_dc_b => g6t_gptr_lcb_mpw2_dc_b, + lcb_delay_lclkr_dc => g6t_gptr_lcb_delay_lclkr_dc, + + tri_lcb_mpw1_dc_b => lcb_mpw1_dc_b(0), + tri_lcb_mpw2_dc_b => lcb_mpw2_dc_b, + tri_lcb_delay_lclkr_dc => lcb_delay_lclkr_dc(0), + tri_lcb_clkoff_dc_b => lcb_clkoff_dc_b, + tri_lcb_act_dis_dc => lcb_act_dis_dc, + + lcb_sg_1 => pc_sg_1(1), + lcb_time_sg_0 => pc_sg_0(1), + lcb_repr_sg_0 => pc_sg_0(1), + lcb_abst_sl_thold_0 => pc_abst_sl_thold_0, + lcb_repr_sl_thold_0 => pc_repr_sl_thold_0, + lcb_time_sl_thold_0 => pc_time_sl_thold_0, + lcb_ary_nsl_thold_0 => pc_ary_slp_nsl_thold_0, + tc_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc, + abist_en_1 => pc_mm_abist_ena_dc, + din_abist => pc_mm_abist_di_g6t_2r_q, + abist_cmp_en => pc_mm_abist_wl128_comp_ena_q, + abist_raw_b_dc => pc_mm_abist_raw_dc_b, + data_cmp_abist => pc_mm_abist_dcomp_g6t_2r_q, + addr_abist => pc_mm_abist_raddr_0_q(3 to 9), + r_wb_abist => pc_mm_abist_g6t_r_wb_q, + lcb_bolt_sl_thold_0 => pc_mm_bolt_sl_thold_0, + pc_bo_enable_2 => pc_mm_bo_enable_2, + pc_bo_reset => pc_mm_bo_reset, + pc_bo_unload => pc_mm_bo_unload, + pc_bo_repair => pc_mm_bo_repair, + pc_bo_shdata => pc_mm_bo_shdata, + pc_bo_select => pc_mm_bo_select(3), + bo_pc_failout => mm_pc_bo_fail(3), + bo_pc_diagloop => mm_pc_bo_diagout(3), + + write_enable => tlb_write(3), + addr => tlb_addr, + data_in => tlb_datainb, + data_out => tlb_dataout(3*tlb_way_width to 4*tlb_way_width-1) +); +----------------------------------------------------------------------- +-- LRU Instantiation +----------------------------------------------------------------------- +lru_array0: entity tri.tri_128x16_1r1w_1(tri_128x16_1r1w_1) + generic map ( expand_type => expand_type ) + port map( + gnd => gnd, + vdd => vdd, + vcs => vcs, + nclk => nclk, + rd_act => tlb_delayed_act(19), + wr_act => tlb_delayed_act(19), + + lcb_d_mode_dc => g8t_gptr_lcb_d_mode_dc, + lcb_clkoff_dc_b => g8t_gptr_lcb_clkoff_dc_b, + lcb_mpw1_dc_b => g8t_gptr_lcb_mpw1_dc_b, + lcb_mpw2_dc_b => g8t_gptr_lcb_mpw2_dc_b, + lcb_delay_lclkr_dc => g8t_gptr_lcb_delay_lclkr_dc, + tri_lcb_mpw1_dc_b => lcb_mpw1_dc_b(0), + tri_lcb_mpw2_dc_b => lcb_mpw2_dc_b, + tri_lcb_delay_lclkr_dc => lcb_delay_lclkr_dc(0), + tri_lcb_clkoff_dc_b => lcb_clkoff_dc_b, + tri_lcb_act_dis_dc => lcb_act_dis_dc, + + ccflush_dc => tc_ac_ccflush_dc, + scan_dis_dc_b => tc_ac_scan_dis_dc_b, + scan_diag_dc => tc_ac_scan_diag_dc, + func_scan_in => tidn, + func_scan_out => open, + + lcb_sg_0 => pc_sg_0(1), + lcb_sl_thold_0_b => pc_func_slp_sl_thold_0_b(1), + + lcb_time_sl_thold_0 => pc_time_sl_thold_0, + lcb_abst_sl_thold_0 => pc_abst_sl_thold_0, + lcb_repr_sl_thold_0 => pc_repr_sl_thold_0, + lcb_ary_nsl_thold_0 => pc_ary_slp_nsl_thold_0, + + time_scan_in => time_scan_int(4), + time_scan_out => time_scan_int(5), + repr_scan_in => repr_scan_int(4), + repr_scan_out => repr_scan_int(5), + abst_scan_in => abst_scan_int(5), + abst_scan_out => abst_scan_int(6), + + abist_di => pc_mm_abist_di_0_q, + abist_bw_odd => pc_mm_abist_g8t_bw_1_q, + abist_bw_even => pc_mm_abist_g8t_bw_0_q, + abist_wr_adr => pc_mm_abist_waddr_0_q(3 TO 9), + wr_abst_act => pc_mm_abist_g8t_wenb_q, + abist_rd0_adr => pc_mm_abist_raddr_0_q(3 TO 9), + rd0_abst_act => pc_mm_abist_g8t1p_renb_0_q, + tc_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc, + abist_ena_1 => pc_mm_abist_ena_dc, + abist_g8t_rd0_comp_ena => pc_mm_abist_wl128_comp_ena_q, + abist_raw_dc_b => pc_mm_abist_raw_dc_b, + obs0_abist_cmp => pc_mm_abist_g8t_dcomp_q, + + lcb_bolt_sl_thold_0 => pc_mm_bolt_sl_thold_0, + pc_bo_enable_2 => pc_mm_bo_enable_2, + pc_bo_reset => pc_mm_bo_reset, + pc_bo_unload => pc_mm_bo_unload, + pc_bo_repair => pc_mm_bo_repair, + pc_bo_shdata => pc_mm_bo_shdata, + pc_bo_select => pc_mm_bo_select(4), + bo_pc_failout => mm_pc_bo_fail(4), + bo_pc_diagloop => mm_pc_bo_diagout(4), + + bw => lru_write(0 to lru_width-1), + wr_adr => lru_wr_addr, + rd_adr => lru_rd_addr, + di => lru_datain(0 to lru_width-1), + do => lru_dataout(0 to lru_width-1) +); +end generate tlb_gen_instance; +xu_mm_ex2_eff_addr_sig <= xu_mm_ex2_eff_addr; +----------------------------------------------------------------------- +-- end of TLB logic +----------------------------------------------------------------------- +----------------------------------------------------------------------- +-- Scan +----------------------------------------------------------------------- +siv_0(0 to scan_right_0) <= sov_0(1 to scan_right_0) & func_scan_in_int(0); +func_scan_out_int(0) <= sov_0(0); +siv_1(0 to scan_right_1) <= sov_1(1 to scan_right_1) & func_scan_in_int(9); +func_scan_out_int(9) <= sov_1(0); +time_scan_int(0) <= time_scan_in_int; +repr_scan_int(0) <= repr_scan_in_int; +abst_scan_int(0) <= abst_scan_in_int(0); +abst_scan_int(3) <= abst_scan_in_int(1); +abst_scan_out_int(0) <= abst_scan_int(2); +abst_scan_out_int(1) <= abst_scan_int(6); +time_scan_out_int <= time_scan_int(5); +repr_scan_out_int <= repr_scan_int(5); +bcfg_scan_out_int <= bcfg_scan_in_int; +dcfg_scan_out_int <= dcfg_scan_in_int; +bsiv(0) <= ccfg_scan_in_int; +ccfg_scan_out_int <= bsov(boot_scan_right); +unused_dc(0) <= PC_ABST_SLP_SL_THOLD_0; +unused_dc(1) <= pc_ary_nsl_thold_0; +unused_dc(2 to 3) <= PC_FUNC_SL_THOLD_0(0 TO 1); +unused_dc(4 to 5) <= PC_FUNC_SL_THOLD_0_B(0 TO 1); +unused_dc(6 to 7) <= PC_FUNC_SLP_SL_THOLD_0(0 TO 1); +unused_dc(8) <= G8T_GPTR_LCB_ACT_DIS_DC; +unused_dc(9 to 11) <= PC_MM_ABIST_RADDR_0_Q(0 TO 2); +unused_dc(12 to 14) <= PC_MM_ABIST_WADDR_0_Q(0 TO 2); +unused_dc(15) <= PC_FUNC_SLP_SL_THOLD_0_B(0); +unused_dc(16 to 17) <= MMUCR0_0_SIG(0 TO 1); +unused_dc(18 to 19) <= MMUCR0_1_SIG(0 TO 1); +unused_dc(20 to 21) <= MMUCR0_2_SIG(0 TO 1); +unused_dc(22 to 23) <= MMUCR0_3_SIG(0 TO 1); +unused_dc(24 to 27) <= MMUCR1_SIG(0 TO 3); +unused_dc(28 to 31) <= MMUCR1_SIG(6 TO 9); +unused_dc(32 to 43) <= MMUCR1_SIG(20 TO 31); +unused_dc(44 to 65) <= TLB_TAG0_EPN(0 TO 21); +unused_dc(66 to 70) <= XU_MM_CCR2_NOTLB_B(8 TO 12); +----------------------------------------------------------------------- +-- Pass thru wire mapping from node to other units +----------------------------------------------------------------------- +an_ac_back_inv_omm <= an_ac_back_inv; +an_ac_back_inv_addr_omm <= an_ac_back_inv_addr; +an_ac_back_inv_target_omm_iua <= an_ac_back_inv_target(0 to 1); +an_ac_back_inv_target_omm_iub <= an_ac_back_inv_target(3 to 4); +an_ac_reld_core_tag_omm <= an_ac_reld_core_tag; +an_ac_reld_data_omm <= an_ac_reld_data; +an_ac_reld_data_vld_omm <= an_ac_reld_data_vld; +an_ac_reld_ecc_err_omm <= an_ac_reld_ecc_err; +an_ac_reld_ecc_err_ue_omm <= an_ac_reld_ecc_err_ue; +an_ac_reld_qw_omm <= an_ac_reld_qw; +an_ac_reld_ditc_omm <= an_ac_reld_ditc; +an_ac_reld_crit_qw_omm <= an_ac_reld_crit_qw; +an_ac_reld_data_coming_omm <= an_ac_reld_data_coming; +an_ac_reld_l1_dump_omm <= an_ac_reld_l1_dump; +an_ac_grffence_en_dc_omm <= an_ac_grffence_en_dc; +an_ac_stcx_complete_omm <= an_ac_stcx_complete; +an_ac_abist_mode_dc_omm <= an_ac_abist_mode_dc; +an_ac_abist_start_test_omm <= an_ac_abist_start_test; +an_ac_abst_scan_in_omm_iu <= an_ac_abst_scan_in(0 to 4); +an_ac_abst_scan_in_omm_xu <= an_ac_abst_scan_in(7 to 9); +an_ac_atpg_en_dc_omm <= an_ac_atpg_en_dc; +an_ac_bcfg_scan_in_omm_bit1 <= an_ac_bcfg_scan_in(1); +an_ac_bcfg_scan_in_omm_bit3 <= an_ac_bcfg_scan_in(3); +an_ac_bcfg_scan_in_omm_bit4 <= an_ac_bcfg_scan_in(4); +an_ac_lbist_ary_wrt_thru_dc_omm <= an_ac_lbist_ary_wrt_thru_dc; +an_ac_ccflush_dc_omm <= an_ac_ccflush_dc; +an_ac_reset_1_complete_omm <= an_ac_reset_1_complete; +an_ac_reset_2_complete_omm <= an_ac_reset_2_complete; +an_ac_reset_3_complete_omm <= an_ac_reset_3_complete; +an_ac_reset_wd_complete_omm <= an_ac_reset_wd_complete; +an_ac_dcfg_scan_in_omm <= an_ac_dcfg_scan_in(1 to 2); +an_ac_debug_stop_omm <= an_ac_debug_stop; +an_ac_func_scan_in_omm_iua <= an_ac_func_scan_in(0 to 21); +an_ac_func_scan_in_omm_iub <= an_ac_func_scan_in(60 to 63); +an_ac_func_scan_in_omm_xu <= an_ac_func_scan_in(31 to 58); +an_ac_lbist_en_dc_omm <= an_ac_lbist_en_dc; +an_ac_pm_thread_stop_omm <= an_ac_pm_thread_stop; +an_ac_regf_scan_in_omm <= an_ac_regf_scan_in; +an_ac_scan_diag_dc_omm <= an_ac_scan_diag_dc; +an_ac_scan_dis_dc_b_omm <= an_ac_scan_dis_dc_b; +an_ac_scom_cch_omm <= an_ac_scom_cch; +an_ac_scom_dch_omm <= an_ac_scom_dch; +an_ac_checkstop_omm <= an_ac_checkstop; +an_ac_crit_interrupt_omm <= an_ac_crit_interrupt; +an_ac_ext_interrupt_omm <= an_ac_ext_interrupt; +an_ac_flh2l2_gate_omm <= an_ac_flh2l2_gate; +an_ac_icbi_ack_omm <= an_ac_icbi_ack; +an_ac_icbi_ack_thread_omm <= an_ac_icbi_ack_thread; +an_ac_req_ld_pop_omm <= an_ac_req_ld_pop; +an_ac_req_spare_ctrl_a1_omm <= an_ac_req_spare_ctrl_a1; +an_ac_req_st_gather_omm <= an_ac_req_st_gather; +an_ac_req_st_pop_omm <= an_ac_req_st_pop; +an_ac_req_st_pop_thrd_omm <= an_ac_req_st_pop_thrd; +an_ac_reservation_vld_omm <= an_ac_reservation_vld; +an_ac_sleep_en_omm <= an_ac_sleep_en; +an_ac_stcx_pass_omm <= an_ac_stcx_pass; +an_ac_sync_ack_omm <= an_ac_sync_ack; +an_ac_ary_nsl_thold_7_omm <= an_ac_ary_nsl_thold_7; +an_ac_ccenable_dc_omm <= an_ac_ccenable_dc; +an_ac_coreid_omm <= an_ac_coreid; +an_ac_external_mchk_omm <= an_ac_external_mchk; +an_ac_fce_7_omm <= an_ac_fce_7; +an_ac_func_nsl_thold_7_omm <= an_ac_func_nsl_thold_7; +an_ac_func_sl_thold_7_omm <= an_ac_func_sl_thold_7; +an_ac_gsd_test_enable_dc_omm <= an_ac_gsd_test_enable_dc; +an_ac_gsd_test_acmode_dc_omm <= an_ac_gsd_test_acmode_dc; +an_ac_gptr_scan_in_omm <= an_ac_gptr_scan_in; +an_ac_hang_pulse_omm <= an_ac_hang_pulse; +an_ac_lbist_ac_mode_dc_omm <= an_ac_lbist_ac_mode_dc; +an_ac_lbist_ip_dc_omm <= an_ac_lbist_ip_dc; +an_ac_malf_alert_omm <= an_ac_malf_alert; +an_ac_perf_interrupt_omm <= an_ac_perf_interrupt; +an_ac_psro_enable_dc_omm <= an_ac_psro_enable_dc; +an_ac_repr_scan_in_omm <= an_ac_repr_scan_in; +an_ac_rtim_sl_thold_7_omm <= an_ac_rtim_sl_thold_7; +an_ac_scan_type_dc_omm <= an_ac_scan_type_dc; +an_ac_scom_sat_id_omm <= an_ac_scom_sat_id; +an_ac_sg_7_omm <= an_ac_sg_7; +an_ac_tb_update_enable_omm <= an_ac_tb_update_enable; +an_ac_tb_update_pulse_omm <= an_ac_tb_update_pulse; +an_ac_time_scan_in_omm <= an_ac_time_scan_in; +ac_an_reld_ditc_pop <= ac_an_reld_ditc_pop_imm; +ac_an_power_managed <= ac_an_power_managed_imm; +ac_an_rvwinkle_mode <= ac_an_rvwinkle_mode_imm; +ac_an_fu_bypass_events <= ac_an_fu_bypass_events_imm; +ac_an_iu_bypass_events <= ac_an_iu_bypass_events_imm; +ac_an_mm_bypass_events <= ac_an_mm_bypass_events_imm; +ac_an_lsu_bypass_events <= ac_an_lsu_bypass_events_imm; +ac_an_event_bus <= ac_an_event_bus_imm; +ac_an_abst_scan_out(0 to 4) <= ac_an_abst_scan_out_imm_iu(0 to 4); +ac_an_abst_scan_out(7 to 9) <= ac_an_abst_scan_out_imm_xu(7 to 9); +ac_an_bcfg_scan_out <= ac_an_bcfg_scan_out_imm; +ac_an_dcfg_scan_out <= ac_an_dcfg_scan_out_imm; +ac_an_func_scan_out(0 to 21) <= ac_an_func_scan_out_imm_iua(0 to 21); +ac_an_func_scan_out(31 to 58) <= ac_an_func_scan_out_imm_xu(31 to 58); +ac_an_func_scan_out(60 to 63) <= ac_an_func_scan_out_imm_iub(60 to 63); +ac_an_regf_scan_out <= ac_an_regf_scan_out_imm; +ac_an_pm_thread_running <= ac_an_pm_thread_running_imm; +ac_an_recov_err <= ac_an_recov_err_imm; +ac_an_scom_cch <= ac_an_scom_cch_imm; +ac_an_scom_dch <= ac_an_scom_dch_imm; +ac_an_special_attn <= ac_an_special_attn_imm; +ac_an_checkstop <= ac_an_checkstop_imm; +ac_an_local_checkstop <= ac_an_local_checkstop_imm; +ac_an_trace_error <= ac_an_trace_error_imm; +ac_an_box_empty <= ac_an_box_empty_imm; +ac_an_machine_check <= ac_an_machine_check_imm; +ac_an_req <= ac_an_req_imm; +ac_an_req_endian <= ac_an_req_endian_imm; +ac_an_req_ld_core_tag <= ac_an_req_ld_core_tag_imm; +ac_an_req_ld_xfr_len <= ac_an_req_ld_xfr_len_imm; +ac_an_req_pwr_token <= ac_an_req_pwr_token_imm; +ac_an_req_ra <= ac_an_req_ra_imm; +ac_an_req_spare_ctrl_a0 <= ac_an_req_spare_ctrl_a0_imm; +ac_an_req_thread <= ac_an_req_thread_imm; +ac_an_req_ttype <= ac_an_req_ttype_imm; +ac_an_req_user_defined <= ac_an_req_user_defined_imm; +ac_an_req_wimg_g <= ac_an_req_wimg_g_imm; +ac_an_req_wimg_i <= ac_an_req_wimg_i_imm; +ac_an_req_wimg_m <= ac_an_req_wimg_m_imm; +ac_an_req_wimg_w <= ac_an_req_wimg_w_imm; +ac_an_st_byte_enbl <= ac_an_st_byte_enbl_imm; +ac_an_st_data <= ac_an_st_data_imm; +ac_an_st_data_pwr_token <= ac_an_st_data_pwr_token_imm; +ac_an_abist_done_dc <= ac_an_abist_done_dc_imm; +ac_an_debug_trigger <= ac_an_debug_trigger_imm; +psro_ringsig_inv1: ac_an_psro_ringsig_b <= not(ac_an_psro_ringsig_imm); +psro_ringsig_inv2: ac_an_psro_ringsig <= not(ac_an_psro_ringsig_b); +ac_an_reset_1_request <= ac_an_reset_1_request_imm; +ac_an_reset_2_request <= ac_an_reset_2_request_imm; +ac_an_reset_3_request <= ac_an_reset_3_request_imm; +ac_an_reset_wd_request <= ac_an_reset_wd_request_imm; +ac_an_dcr_act <= '0'; +ac_an_dcr_val <= '0'; +ac_an_dcr_read <= '0'; +ac_an_dcr_user <= '0'; +ac_an_dcr_etid <= (others => '0'); +ac_an_dcr_addr <= (others => '0'); +ac_an_dcr_data <= (others => '0'); +-- Pass thru wires specifically for Bluegene, PC <--> IU <--> MMU <--> L1P/TPB +bg_ac_an_func_scan_ns <= bg_ac_an_func_scan_ns_imm; +bg_ac_an_abst_scan_ns <= bg_ac_an_abst_scan_ns_imm; +bg_pc_l1p_abist_di_0 <= bg_pc_l1p_abist_di_0_imm; +bg_pc_l1p_abist_g8t1p_renb_0 <= bg_pc_l1p_abist_g8t1p_renb_0_imm; +bg_pc_l1p_abist_g8t_bw_0 <= bg_pc_l1p_abist_g8t_bw_0_imm; +bg_pc_l1p_abist_g8t_bw_1 <= bg_pc_l1p_abist_g8t_bw_1_imm; +bg_pc_l1p_abist_g8t_dcomp <= bg_pc_l1p_abist_g8t_dcomp_imm; +bg_pc_l1p_abist_g8t_wenb <= bg_pc_l1p_abist_g8t_wenb_imm; +bg_pc_l1p_abist_raddr_0 <= bg_pc_l1p_abist_raddr_0_imm; +bg_pc_l1p_abist_waddr_0 <= bg_pc_l1p_abist_waddr_0_imm; +bg_pc_l1p_abist_wl128_comp_ena <= bg_pc_l1p_abist_wl128_comp_ena_imm; +bg_pc_l1p_abist_wl32_comp_ena <= bg_pc_l1p_abist_wl32_comp_ena_imm; +bg_pc_l1p_gptr_sl_thold_2 <= bg_pc_l1p_gptr_sl_thold_2_imm; +bg_pc_l1p_time_sl_thold_2 <= bg_pc_l1p_time_sl_thold_2_imm; +bg_pc_l1p_repr_sl_thold_2 <= bg_pc_l1p_repr_sl_thold_2_imm; +bg_pc_l1p_abst_sl_thold_2 <= bg_pc_l1p_abst_sl_thold_2_imm; +bg_pc_l1p_func_sl_thold_2 <= bg_pc_l1p_func_sl_thold_2_imm; +bg_pc_l1p_func_slp_sl_thold_2 <= bg_pc_l1p_func_slp_sl_thold_2_imm; +bg_pc_l1p_bolt_sl_thold_2 <= bg_pc_l1p_bolt_sl_thold_2_imm; +bg_pc_l1p_ary_nsl_thold_2 <= bg_pc_l1p_ary_nsl_thold_2_imm; +bg_pc_l1p_sg_2 <= bg_pc_l1p_sg_2_imm; +bg_pc_l1p_fce_2 <= bg_pc_l1p_fce_2_imm; +bg_pc_l1p_bo_enable_2 <= bg_pc_l1p_bo_enable_2_imm; +bg_pc_bo_unload <= bg_pc_bo_unload_imm; +bg_pc_bo_load <= bg_pc_bo_load_imm; +bg_pc_bo_repair <= bg_pc_bo_repair_imm; +bg_pc_bo_reset <= bg_pc_bo_reset_imm; +bg_pc_bo_shdata <= bg_pc_bo_shdata_imm; +bg_pc_bo_select <= bg_pc_bo_select_imm; +bg_pc_l1p_ccflush_dc <= bg_pc_l1p_ccflush_dc_imm; +bg_pc_l1p_abist_ena_dc <= bg_pc_l1p_abist_ena_dc_imm; +bg_pc_l1p_abist_raw_dc_b <= bg_pc_l1p_abist_raw_dc_b_imm; +-- Pass thru wires specifically for Bluegene, L1P/TPB -> MMU -> IU -> PC +bg_an_ac_func_scan_sn_omm <= bg_an_ac_func_scan_sn; +bg_an_ac_abst_scan_sn_omm <= bg_an_ac_abst_scan_sn; +bg_pc_bo_fail_omm <= bg_pc_bo_fail; +bg_pc_bo_diagout_omm <= bg_pc_bo_diagout; +end mmq; diff --git a/rel/src/vhdl/work/mmq_dbg.vhdl b/rel/src/vhdl/work/mmq_dbg.vhdl new file mode 100644 index 0000000..44d80b9 --- /dev/null +++ b/rel/src/vhdl/work/mmq_dbg.vhdl @@ -0,0 +1,1796 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +--******************************************************************** +--* +--* TITLE: debug event mux +--* +--* NAME: mmq_dbg.vhdl +--* +--********************************************************************* + +library ieee; +use ieee.std_logic_1164.all; + +library ibm,clib; +use ibm.std_ulogic_unsigned.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; + +library support; +use support.power_logic_pkg.all; + +library tri; +use tri.tri_latches_pkg.all; + +entity mmq_dbg is +generic(thdid_width : integer := 4; + tlb_ways : natural := 4; + tlb_addr_width : natural := 7; + tlb_way_width : natural := 168; + tlb_word_width : natural := 84; + tlb_tag_width : natural := 110; + lru_width : natural := 16; + expand_type : integer := 2 ); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + + pc_func_slp_sl_thold_2 : in std_ulogic; + pc_func_slp_nsl_thold_2 : in std_ulogic; + pc_sg_2 : in std_ulogic; + pc_fce_2 : in std_ulogic; + tc_ac_ccflush_dc : in std_ulogic; + + lcb_clkoff_dc_b : in std_ulogic; + lcb_act_dis_dc : in std_ulogic; + lcb_d_mode_dc : in std_ulogic; + lcb_delay_lclkr_dc : in std_ulogic; + lcb_mpw1_dc_b : in std_ulogic; + lcb_mpw2_dc_b : in std_ulogic; + + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + mmucr2 : in std_ulogic_vector(8 to 11); + + pc_mm_trace_bus_enable : in std_ulogic; + pc_mm_debug_mux1_ctrls : in std_ulogic_vector(0 to 15); + + debug_bus_in : in std_ulogic_vector(0 to 87); + trace_triggers_in : in std_ulogic_vector(0 to 11); + + debug_bus_out : out std_ulogic_vector(0 to 87); + debug_bus_out_int : out std_ulogic_vector(0 to 7); -- internal replicate to iu_fetch + trace_triggers_out : out std_ulogic_vector(0 to 11); + + ----------- spr debug signals + spr_dbg_match_64b : in std_ulogic; -- these match sigs are spr_int phase + spr_dbg_match_any_mmu : in std_ulogic; + spr_dbg_match_any_mas : in std_ulogic; + spr_dbg_match_pid : in std_ulogic; + spr_dbg_match_lpidr : in std_ulogic; + spr_dbg_match_mmucr0 : in std_ulogic; + spr_dbg_match_mmucr1 : in std_ulogic; + spr_dbg_match_mmucr2 : in std_ulogic; + spr_dbg_match_mmucr3 : in std_ulogic; + + spr_dbg_match_mmucsr0 : in std_ulogic; + spr_dbg_match_mmucfg : in std_ulogic; + spr_dbg_match_tlb0cfg : in std_ulogic; + spr_dbg_match_tlb0ps : in std_ulogic; + spr_dbg_match_lratcfg : in std_ulogic; + spr_dbg_match_lratps : in std_ulogic; + spr_dbg_match_eptcfg : in std_ulogic; + spr_dbg_match_lper : in std_ulogic; + spr_dbg_match_lperu : in std_ulogic; + + spr_dbg_match_mas0 : in std_ulogic; + spr_dbg_match_mas1 : in std_ulogic; + spr_dbg_match_mas2 : in std_ulogic; + spr_dbg_match_mas2u : in std_ulogic; + spr_dbg_match_mas3 : in std_ulogic; + spr_dbg_match_mas4 : in std_ulogic; + spr_dbg_match_mas5 : in std_ulogic; + spr_dbg_match_mas6 : in std_ulogic; + spr_dbg_match_mas7 : in std_ulogic; + spr_dbg_match_mas8 : in std_ulogic; + spr_dbg_match_mas01_64b : in std_ulogic; + spr_dbg_match_mas56_64b : in std_ulogic; + spr_dbg_match_mas73_64b : in std_ulogic; + spr_dbg_match_mas81_64b : in std_ulogic; + + spr_dbg_slowspr_val_int : in std_ulogic; -- spr_int phase + spr_dbg_slowspr_rw_int : in std_ulogic; + spr_dbg_slowspr_etid_int : in std_ulogic_vector(0 to 1); + spr_dbg_slowspr_addr_int : in std_ulogic_vector(0 to 9); + spr_dbg_slowspr_val_out : in std_ulogic; -- spr_out phase + spr_dbg_slowspr_done_out : in std_ulogic; + spr_dbg_slowspr_data_out : in std_ulogic_vector(0 to 63); + + + ----------- mmq_inval debug signals + inval_dbg_seq_q : in std_ulogic_vector(0 to 4); + inval_dbg_seq_idle : in std_ulogic; + inval_dbg_seq_snoop_inprogress : in std_ulogic; + inval_dbg_seq_snoop_done : in std_ulogic; + inval_dbg_seq_local_done : in std_ulogic; + inval_dbg_seq_tlb0fi_done : in std_ulogic; + inval_dbg_seq_tlbwe_snoop_done : in std_ulogic; + inval_dbg_ex6_valid : in std_ulogic; + inval_dbg_ex6_thdid : in std_ulogic_vector(0 to 1); -- encoded + inval_dbg_ex6_ttype : in std_ulogic_vector(0 to 2); -- encoded + inval_dbg_snoop_forme : in std_ulogic; + inval_dbg_snoop_local_reject : in std_ulogic; + inval_dbg_an_ac_back_inv_q : in std_ulogic_vector(2 to 8); -- 2=valid b, 3=target b, 4=L, 5=GS, 6=IND, 7=local, 8=reject + inval_dbg_an_ac_back_inv_lpar_id_q : in std_ulogic_vector(0 to 7); + inval_dbg_an_ac_back_inv_addr_q : in std_ulogic_vector(22 to 63); + inval_dbg_snoop_valid_q : in std_ulogic_vector(0 to 2); + inval_dbg_snoop_ack_q : in std_ulogic_vector(0 to 2); + inval_dbg_snoop_attr_q : in std_ulogic_vector(0 to 34); + inval_dbg_snoop_attr_tlb_spec_q : in std_ulogic_vector(18 to 19); + inval_dbg_snoop_vpn_q : in std_ulogic_vector(17 to 51); + inval_dbg_lsu_tokens_q : in std_ulogic_vector(0 to 1); + + ----------- tlb_req debug signals + tlb_req_dbg_ierat_iu5_valid_q : in std_ulogic; + tlb_req_dbg_ierat_iu5_thdid : in std_ulogic_vector(0 to 1); + tlb_req_dbg_ierat_iu5_state_q : in std_ulogic_vector(0 to 3); + tlb_req_dbg_ierat_inptr_q : in std_ulogic_vector(0 to 1); + tlb_req_dbg_ierat_outptr_q : in std_ulogic_vector(0 to 1); + tlb_req_dbg_ierat_req_valid_q : in std_ulogic_vector(0 to 3); + tlb_req_dbg_ierat_req_nonspec_q : in std_ulogic_vector(0 to 3); + tlb_req_dbg_ierat_req_thdid : in std_ulogic_vector(0 to 7); -- encoded + tlb_req_dbg_ierat_req_dup_q : in std_ulogic_vector(0 to 3); + tlb_req_dbg_derat_ex6_valid_q : in std_ulogic; + tlb_req_dbg_derat_ex6_thdid : in std_ulogic_vector(0 to 1); -- encoded + tlb_req_dbg_derat_ex6_state_q : in std_ulogic_vector(0 to 3); + tlb_req_dbg_derat_inptr_q : in std_ulogic_vector(0 to 1); + tlb_req_dbg_derat_outptr_q : in std_ulogic_vector(0 to 1); + tlb_req_dbg_derat_req_valid_q : in std_ulogic_vector(0 to 3); + tlb_req_dbg_derat_req_thdid : in std_ulogic_vector(0 to 7); -- encoded + tlb_req_dbg_derat_req_ttype_q : in std_ulogic_vector(0 to 7); + tlb_req_dbg_derat_req_dup_q : in std_ulogic_vector(0 to 3); + + ----------- tlb_ctl debug signals + tlb_ctl_dbg_seq_q : in std_ulogic_vector(0 to 5); -- tlb_seq_q + tlb_ctl_dbg_seq_idle : in std_ulogic; + tlb_ctl_dbg_seq_any_done_sig : in std_ulogic; + tlb_ctl_dbg_seq_abort : in std_ulogic; + tlb_ctl_dbg_any_tlb_req_sig : in std_ulogic; + tlb_ctl_dbg_any_req_taken_sig : in std_ulogic; + tlb_ctl_dbg_tag0_valid : in std_ulogic; + tlb_ctl_dbg_tag0_thdid : in std_ulogic_vector(0 to 1); -- encoded + tlb_ctl_dbg_tag0_type : in std_ulogic_vector(0 to 2); -- encoded + tlb_ctl_dbg_tag0_wq : in std_ulogic_vector(0 to 1); -- encoded + tlb_ctl_dbg_tag0_gs : in std_ulogic; + tlb_ctl_dbg_tag0_pr : in std_ulogic; + tlb_ctl_dbg_tag0_atsel : in std_ulogic; + tlb_ctl_dbg_tag5_tlb_write_q : in std_ulogic_vector(0 to 3); + tlb_ctl_dbg_resv_valid : in std_ulogic_vector(0 to 3); + tlb_ctl_dbg_set_resv : in std_ulogic_vector(0 to 3); + tlb_ctl_dbg_resv_match_vec_q : in std_ulogic_vector(0 to 3); + tlb_ctl_dbg_any_tag_flush_sig : in std_ulogic; + tlb_ctl_dbg_resv0_tag0_lpid_match : in std_ulogic; + tlb_ctl_dbg_resv0_tag0_pid_match : in std_ulogic; + tlb_ctl_dbg_resv0_tag0_as_snoop_match : in std_ulogic; + tlb_ctl_dbg_resv0_tag0_gs_snoop_match : in std_ulogic; + tlb_ctl_dbg_resv0_tag0_as_tlbwe_match : in std_ulogic; + tlb_ctl_dbg_resv0_tag0_gs_tlbwe_match : in std_ulogic; + tlb_ctl_dbg_resv0_tag0_ind_match : in std_ulogic; + tlb_ctl_dbg_resv0_tag0_epn_loc_match : in std_ulogic; + tlb_ctl_dbg_resv0_tag0_epn_glob_match : in std_ulogic; + tlb_ctl_dbg_resv0_tag0_class_match : in std_ulogic; + tlb_ctl_dbg_resv1_tag0_lpid_match : in std_ulogic; + tlb_ctl_dbg_resv1_tag0_pid_match : in std_ulogic; + tlb_ctl_dbg_resv1_tag0_as_snoop_match : in std_ulogic; + tlb_ctl_dbg_resv1_tag0_gs_snoop_match : in std_ulogic; + tlb_ctl_dbg_resv1_tag0_as_tlbwe_match : in std_ulogic; + tlb_ctl_dbg_resv1_tag0_gs_tlbwe_match : in std_ulogic; + tlb_ctl_dbg_resv1_tag0_ind_match : in std_ulogic; + tlb_ctl_dbg_resv1_tag0_epn_loc_match : in std_ulogic; + tlb_ctl_dbg_resv1_tag0_epn_glob_match : in std_ulogic; + tlb_ctl_dbg_resv1_tag0_class_match : in std_ulogic; + tlb_ctl_dbg_resv2_tag0_lpid_match : in std_ulogic; + tlb_ctl_dbg_resv2_tag0_pid_match : in std_ulogic; + tlb_ctl_dbg_resv2_tag0_as_snoop_match : in std_ulogic; + tlb_ctl_dbg_resv2_tag0_gs_snoop_match : in std_ulogic; + tlb_ctl_dbg_resv2_tag0_as_tlbwe_match : in std_ulogic; + tlb_ctl_dbg_resv2_tag0_gs_tlbwe_match : in std_ulogic; + tlb_ctl_dbg_resv2_tag0_ind_match : in std_ulogic; + tlb_ctl_dbg_resv2_tag0_epn_loc_match : in std_ulogic; + tlb_ctl_dbg_resv2_tag0_epn_glob_match : in std_ulogic; + tlb_ctl_dbg_resv2_tag0_class_match : in std_ulogic; + tlb_ctl_dbg_resv3_tag0_lpid_match : in std_ulogic; + tlb_ctl_dbg_resv3_tag0_pid_match : in std_ulogic; + tlb_ctl_dbg_resv3_tag0_as_snoop_match : in std_ulogic; + tlb_ctl_dbg_resv3_tag0_gs_snoop_match : in std_ulogic; + tlb_ctl_dbg_resv3_tag0_as_tlbwe_match : in std_ulogic; + tlb_ctl_dbg_resv3_tag0_gs_tlbwe_match : in std_ulogic; + tlb_ctl_dbg_resv3_tag0_ind_match : in std_ulogic; + tlb_ctl_dbg_resv3_tag0_epn_loc_match : in std_ulogic; + tlb_ctl_dbg_resv3_tag0_epn_glob_match : in std_ulogic; + tlb_ctl_dbg_resv3_tag0_class_match : in std_ulogic; + tlb_ctl_dbg_clr_resv_q : in std_ulogic_vector(0 to 3); -- tag5 + tlb_ctl_dbg_clr_resv_terms : in std_ulogic_vector(0 to 3); -- tag5, threadwise condensed into to tlbivax, tlbilx, tlbwe, ptereload + + ----------- tlb_cmp debug signals + tlb_cmp_dbg_tag4 : in std_ulogic_vector(0 to tlb_tag_width-1); + tlb_cmp_dbg_tag4_wayhit : in std_ulogic_vector(0 to tlb_ways); + tlb_cmp_dbg_addr4 : in std_ulogic_vector(0 to tlb_addr_width-1); + tlb_cmp_dbg_tag4_way : in std_ulogic_vector(0 to tlb_way_width-1); + tlb_cmp_dbg_tag4_parerr : in std_ulogic_vector(0 to 4); + tlb_cmp_dbg_tag4_lru_dataout_q : in std_ulogic_vector(0 to lru_width-5); + tlb_cmp_dbg_tag5_tlb_datain_q : in std_ulogic_vector(0 to tlb_way_width-1); + tlb_cmp_dbg_tag5_lru_datain_q : in std_ulogic_vector(0 to lru_width-5); + tlb_cmp_dbg_tag5_lru_write : in std_ulogic; + tlb_cmp_dbg_tag5_any_exception : in std_ulogic; + tlb_cmp_dbg_tag5_except_type_q : in std_ulogic_vector(0 to 3); + tlb_cmp_dbg_tag5_except_thdid_q : in std_ulogic_vector(0 to 1); + tlb_cmp_dbg_tag5_erat_rel_val : in std_ulogic_vector(0 to 9); + tlb_cmp_dbg_tag5_erat_rel_data : in std_ulogic_vector(0 to 131); + tlb_cmp_dbg_erat_dup_q : in std_ulogic_vector(0 to 19); + + + tlb_cmp_dbg_addr_enable : in std_ulogic_vector(0 to 8); + tlb_cmp_dbg_pgsize_enable : in std_ulogic; + tlb_cmp_dbg_class_enable : in std_ulogic; + tlb_cmp_dbg_extclass_enable : in std_ulogic_vector(0 to 1); + tlb_cmp_dbg_state_enable : in std_ulogic_vector(0 to 1); + tlb_cmp_dbg_thdid_enable : in std_ulogic; + tlb_cmp_dbg_pid_enable : in std_ulogic; + tlb_cmp_dbg_lpid_enable : in std_ulogic; + tlb_cmp_dbg_ind_enable : in std_ulogic; + tlb_cmp_dbg_iprot_enable : in std_ulogic; + tlb_cmp_dbg_way0_entry_v : in std_ulogic; -- these are tag3 versions + tlb_cmp_dbg_way0_addr_match : in std_ulogic; + tlb_cmp_dbg_way0_pgsize_match : in std_ulogic; + tlb_cmp_dbg_way0_class_match : in std_ulogic; + tlb_cmp_dbg_way0_extclass_match : in std_ulogic; + tlb_cmp_dbg_way0_state_match : in std_ulogic; + tlb_cmp_dbg_way0_thdid_match : in std_ulogic; + tlb_cmp_dbg_way0_pid_match : in std_ulogic; + tlb_cmp_dbg_way0_lpid_match : in std_ulogic; + tlb_cmp_dbg_way0_ind_match : in std_ulogic; + tlb_cmp_dbg_way0_iprot_match : in std_ulogic; + tlb_cmp_dbg_way1_entry_v : in std_ulogic; + tlb_cmp_dbg_way1_addr_match : in std_ulogic; + tlb_cmp_dbg_way1_pgsize_match : in std_ulogic; + tlb_cmp_dbg_way1_class_match : in std_ulogic; + tlb_cmp_dbg_way1_extclass_match : in std_ulogic; + tlb_cmp_dbg_way1_state_match : in std_ulogic; + tlb_cmp_dbg_way1_thdid_match : in std_ulogic; + tlb_cmp_dbg_way1_pid_match : in std_ulogic; + tlb_cmp_dbg_way1_lpid_match : in std_ulogic; + tlb_cmp_dbg_way1_ind_match : in std_ulogic; + tlb_cmp_dbg_way1_iprot_match : in std_ulogic; + tlb_cmp_dbg_way2_entry_v : in std_ulogic; + tlb_cmp_dbg_way2_addr_match : in std_ulogic; + tlb_cmp_dbg_way2_pgsize_match : in std_ulogic; + tlb_cmp_dbg_way2_class_match : in std_ulogic; + tlb_cmp_dbg_way2_extclass_match : in std_ulogic; + tlb_cmp_dbg_way2_state_match : in std_ulogic; + tlb_cmp_dbg_way2_thdid_match : in std_ulogic; + tlb_cmp_dbg_way2_pid_match : in std_ulogic; + tlb_cmp_dbg_way2_lpid_match : in std_ulogic; + tlb_cmp_dbg_way2_ind_match : in std_ulogic; + tlb_cmp_dbg_way2_iprot_match : in std_ulogic; + tlb_cmp_dbg_way3_entry_v : in std_ulogic; + tlb_cmp_dbg_way3_addr_match : in std_ulogic; + tlb_cmp_dbg_way3_pgsize_match : in std_ulogic; + tlb_cmp_dbg_way3_class_match : in std_ulogic; + tlb_cmp_dbg_way3_extclass_match : in std_ulogic; + tlb_cmp_dbg_way3_state_match : in std_ulogic; + tlb_cmp_dbg_way3_thdid_match : in std_ulogic; + tlb_cmp_dbg_way3_pid_match : in std_ulogic; + tlb_cmp_dbg_way3_lpid_match : in std_ulogic; + tlb_cmp_dbg_way3_ind_match : in std_ulogic; + tlb_cmp_dbg_way3_iprot_match : in std_ulogic; + + ----------- lrat debug signals + lrat_dbg_tag1_addr_enable : in std_ulogic; + lrat_dbg_tag2_matchline_q : in std_ulogic_vector(0 to 7); + lrat_dbg_entry0_addr_match : in std_ulogic; -- tag2 + lrat_dbg_entry0_lpid_match : in std_ulogic; + lrat_dbg_entry0_entry_v : in std_ulogic; + lrat_dbg_entry0_entry_x : in std_ulogic; + lrat_dbg_entry0_size : in std_ulogic_vector(0 to 3); + lrat_dbg_entry1_addr_match : in std_ulogic; -- tag2 + lrat_dbg_entry1_lpid_match : in std_ulogic; + lrat_dbg_entry1_entry_v : in std_ulogic; + lrat_dbg_entry1_entry_x : in std_ulogic; + lrat_dbg_entry1_size : in std_ulogic_vector(0 to 3); + lrat_dbg_entry2_addr_match : in std_ulogic; -- tag2 + lrat_dbg_entry2_lpid_match : in std_ulogic; + lrat_dbg_entry2_entry_v : in std_ulogic; + lrat_dbg_entry2_entry_x : in std_ulogic; + lrat_dbg_entry2_size : in std_ulogic_vector(0 to 3); + lrat_dbg_entry3_addr_match : in std_ulogic; -- tag2 + lrat_dbg_entry3_lpid_match : in std_ulogic; + lrat_dbg_entry3_entry_v : in std_ulogic; + lrat_dbg_entry3_entry_x : in std_ulogic; + lrat_dbg_entry3_size : in std_ulogic_vector(0 to 3); + lrat_dbg_entry4_addr_match : in std_ulogic; -- tag2 + lrat_dbg_entry4_lpid_match : in std_ulogic; + lrat_dbg_entry4_entry_v : in std_ulogic; + lrat_dbg_entry4_entry_x : in std_ulogic; + lrat_dbg_entry4_size : in std_ulogic_vector(0 to 3); + lrat_dbg_entry5_addr_match : in std_ulogic; -- tag2 + lrat_dbg_entry5_lpid_match : in std_ulogic; + lrat_dbg_entry5_entry_v : in std_ulogic; + lrat_dbg_entry5_entry_x : in std_ulogic; + lrat_dbg_entry5_size : in std_ulogic_vector(0 to 3); + lrat_dbg_entry6_addr_match : in std_ulogic; -- tag2 + lrat_dbg_entry6_lpid_match : in std_ulogic; + lrat_dbg_entry6_entry_v : in std_ulogic; + lrat_dbg_entry6_entry_x : in std_ulogic; + lrat_dbg_entry6_size : in std_ulogic_vector(0 to 3); + lrat_dbg_entry7_addr_match : in std_ulogic; -- tag2 + lrat_dbg_entry7_lpid_match : in std_ulogic; + lrat_dbg_entry7_entry_v : in std_ulogic; + lrat_dbg_entry7_entry_x : in std_ulogic; + lrat_dbg_entry7_size : in std_ulogic_vector(0 to 3); + + ----------- mmq_htw debug signals + htw_dbg_seq_idle : in std_ulogic; + htw_dbg_pte0_seq_idle : in std_ulogic; + htw_dbg_pte1_seq_idle : in std_ulogic; + htw_dbg_seq_q : in std_ulogic_vector(0 to 1); + htw_dbg_inptr_q : in std_ulogic_vector(0 to 1); + htw_dbg_pte0_seq_q : in std_ulogic_vector(0 to 2); + htw_dbg_pte1_seq_q : in std_ulogic_vector(0 to 2); + htw_dbg_ptereload_ptr_q : in std_ulogic; + htw_dbg_lsuptr_q : in std_ulogic_vector(0 to 1); + htw_dbg_req_valid_q : in std_ulogic_vector(0 to 3); + htw_dbg_resv_valid_vec : in std_ulogic_vector(0 to 3); + htw_dbg_tag4_clr_resv_q : in std_ulogic_vector(0 to 3); + htw_dbg_tag4_clr_resv_terms : in std_ulogic_vector(0 to 3); -- tag4, threadwise condensed into to tlbivax, tlbilx, tlbwe, ptereload + htw_dbg_pte0_score_ptr_q : in std_ulogic_vector(0 to 1); + htw_dbg_pte0_score_cl_offset_q : in std_ulogic_vector(58 to 60); + htw_dbg_pte0_score_error_q : in std_ulogic_vector(0 to 2); + htw_dbg_pte0_score_qwbeat_q : in std_ulogic_vector(0 to 3); -- 4 beats of data per CL + htw_dbg_pte0_score_pending_q : in std_ulogic; + htw_dbg_pte0_score_ibit_q : in std_ulogic; + htw_dbg_pte0_score_dataval_q : in std_ulogic; + htw_dbg_pte0_reld_for_me_tm1 : in std_ulogic; + htw_dbg_pte1_score_ptr_q : in std_ulogic_vector(0 to 1); + htw_dbg_pte1_score_cl_offset_q : in std_ulogic_vector(58 to 60); + htw_dbg_pte1_score_error_q : in std_ulogic_vector(0 to 2); + htw_dbg_pte1_score_qwbeat_q : in std_ulogic_vector(0 to 3); -- 4 beats of data per CL + htw_dbg_pte1_score_pending_q : in std_ulogic; + htw_dbg_pte1_score_ibit_q : in std_ulogic; + htw_dbg_pte1_score_dataval_q : in std_ulogic; + htw_dbg_pte1_reld_for_me_tm1 : in std_ulogic; + + ----------- lsu debug signals + mm_xu_lsu_req : in std_ulogic_vector(0 to thdid_width-1); + -- 0=tlbivax_op, 1=tlbi_complete, 2=mmu read with core_tag=01100, 3=mmu read with core_tag=01101 + mm_xu_lsu_ttype : in std_ulogic_vector(0 to 1); + mm_xu_lsu_wimge : in std_ulogic_vector(0 to 4); + mm_xu_lsu_u : in std_ulogic_vector(0 to 3); + mm_xu_lsu_addr : in std_ulogic_vector(22 to 63); + mm_xu_lsu_lpid : in std_ulogic_vector(0 to 7); -- tlbivax data + mm_xu_lsu_gs : in std_ulogic; -- tlbivax data + mm_xu_lsu_ind : in std_ulogic; -- tlbivax data + mm_xu_lsu_lbit : in std_ulogic; -- -- tlbivax data, "L" bit, for large vs. small + xu_mm_lsu_token : in std_ulogic; + + + ----------- misc top level debug signals + tlb_mas_tlbre : in std_ulogic; + tlb_mas_tlbsx_hit : in std_ulogic; + tlb_mas_tlbsx_miss : in std_ulogic; + tlb_mas_dtlb_error : in std_ulogic; + tlb_mas_itlb_error : in std_ulogic; + tlb_mas_thdid : in std_ulogic_vector(0 to 3); + lrat_mas_tlbre : in std_ulogic; + lrat_mas_tlbsx_hit : in std_ulogic; + lrat_mas_tlbsx_miss : in std_ulogic; + lrat_mas_thdid : in std_ulogic_vector(0 to 3); + lrat_tag3_hit_status : in std_ulogic_vector(0 to 3); -- val,hit,multihit,inval_pgsize + lrat_tag3_hit_entry : in std_ulogic_vector(0 to 2); + + tlb_seq_ierat_req : in std_ulogic; + tlb_seq_derat_req : in std_ulogic; + mm_xu_hold_req : in std_ulogic_vector(0 to 3); + xu_mm_hold_ack : in std_ulogic_vector(0 to 3); + mm_xu_hold_done : in std_ulogic_vector(0 to 3); + mmucsr0_tlb0fi : in std_ulogic; + tlbwe_back_inv_valid : in std_ulogic; + tlbwe_back_inv_attr : in std_ulogic_vector(18 to 19); + xu_mm_lmq_stq_empty : in std_ulogic; + iu_mm_lmq_empty : in std_ulogic; + mm_xu_eratmiss_done : in std_ulogic_vector(0 to 3); + mm_iu_barrier_done : in std_ulogic_vector(0 to 3); + mm_xu_ex3_flush_req : in std_ulogic_vector(0 to 3); + mm_xu_illeg_instr : in std_ulogic_vector(0 to 3); + lrat_tag4_hit_status : in std_ulogic_vector(0 to 3); + lrat_tag4_hit_entry : in std_ulogic_vector(0 to 2); + mm_xu_cr0_eq : in std_ulogic_vector(0 to 3); -- for record forms + mm_xu_cr0_eq_valid : in std_ulogic_vector(0 to 3); -- for record forms + tlb_htw_req_valid : in std_ulogic; + htw_lsu_req_valid : in std_ulogic; + htw_dbg_lsu_thdid : in std_ulogic_vector(0 to 1); + htw_lsu_ttype : in std_ulogic_vector(0 to 1); + htw_lsu_addr : in std_ulogic_vector(22 to 63); + ptereload_req_taken : in std_ulogic; + ptereload_req_pte : in std_ulogic_vector(0 to 63) -- pte entry + + + +); + + -- synopsys translate_off + + + -- synopsys translate_on +end mmq_dbg; + + +architecture mmq_dbg of mmq_dbg is + +constant tagpos_epn : natural := 0; +constant tagpos_pid : natural := 52; -- 14 bits +constant tagpos_is : natural := 66; +constant tagpos_class : natural := 68; +constant tagpos_state : natural := 70; -- state: 0:pr 1:gs 2:as 3:cm +constant tagpos_thdid : natural := 74; +constant tagpos_size : natural := 78; +constant tagpos_type : natural := 82; -- derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload +constant tagpos_lpid : natural := 90; +constant tagpos_ind : natural := 98; +constant tagpos_atsel : natural := 99; +constant tagpos_esel : natural := 100; +constant tagpos_hes : natural := 103; +constant tagpos_wq : natural := 104; +constant tagpos_lrat : natural := 106; +constant tagpos_pt : natural := 107; +constant tagpos_recform : natural := 108; +constant tagpos_endflag : natural := 109; + +-- derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload +constant tagpos_type_derat : natural := tagpos_type; +constant tagpos_type_ierat : natural := tagpos_type+1; +constant tagpos_type_tlbsx : natural := tagpos_type+2; +constant tagpos_type_tlbsrx : natural := tagpos_type+3; +constant tagpos_type_snoop : natural := tagpos_type+4; +constant tagpos_type_tlbre : natural := tagpos_type+5; +constant tagpos_type_tlbwe : natural := tagpos_type+6; +constant tagpos_type_ptereload : natural := tagpos_type+7; +-- state: 0:pr 1:gs 2:as 3:cm +constant tagpos_pr : natural := tagpos_state; +constant tagpos_gs : natural := tagpos_state+1; +constant tagpos_as : natural := tagpos_state+2; +constant tagpos_cm : natural := tagpos_state+3; + +constant waypos_epn : natural := 0; +constant waypos_size : natural := 52; +constant waypos_thdid : natural := 56; +constant waypos_class : natural := 60; +constant waypos_extclass : natural := 62; +constant waypos_lpid : natural := 66; +constant waypos_xbit : natural := 84; +constant waypos_rpn : natural := 88; +constant waypos_rc : natural := 118; +constant waypos_wlc : natural := 120; +constant waypos_resvattr : natural := 122; +constant waypos_vf : natural := 123; +constant waypos_ind : natural := 124; +constant waypos_ubits : natural := 125; +constant waypos_wimge : natural := 129; +constant waypos_usxwr : natural := 134; +constant waypos_gs : natural := 140; +constant waypos_ts : natural := 141; +constant waypos_tid : natural := 144; -- 14 bits + +constant eratpos_epn : natural := 0; +constant eratpos_x : natural := 52; +constant eratpos_size : natural := 53; +constant eratpos_v : natural := 56; +constant eratpos_thdid : natural := 57; +constant eratpos_class : natural := 61; +constant eratpos_extclass : natural := 63; +constant eratpos_wren : natural := 65; +constant eratpos_rpnrsvd : natural := 66; +constant eratpos_rpn : natural := 70; +constant eratpos_r : natural := 100; +constant eratpos_c : natural := 101; +constant eratpos_rsv : natural := 102; +constant eratpos_wlc : natural := 103; +constant eratpos_resvattr : natural := 105; +constant eratpos_vf : natural := 106; +constant eratpos_ubits : natural := 107; +constant eratpos_wimge : natural := 111; +constant eratpos_usxwr : natural := 116; +constant eratpos_gs : natural := 122; +constant eratpos_ts : natural := 123; +constant eratpos_tid : natural := 124; -- 8 bits + +signal pc_mm_trace_bus_enable_q : std_ulogic; -- input=>pc_mm_trace_bus_enable, sleep=>Y, needs_sreset=>0 +signal pc_mm_debug_mux1_ctrls_q : std_ulogic_vector(0 to 15); -- input=>pc_mm_debug_mux1_ctrls, act=>pc_mm_trace_bus_enable_q, sleep=>Y, needs_sreset=>0 +signal pc_mm_debug_mux1_ctrls_loc_d, pc_mm_debug_mux1_ctrls_loc_q : std_ulogic_vector(0 to 15); +signal trigger_data_out_d, trigger_data_out_q : std_ulogic_vector(0 to 11); +signal trace_data_out_d, trace_data_out_q : std_ulogic_vector(0 to 87); +signal trace_data_out_int_q : std_ulogic_vector(0 to 7); +signal debug_d, debug_q : std_ulogic_vector(0 to 371); -- act=>pc_mm_trace_bus_enable_q, sleep=>Y, needs_sreset=>0, scan=>N +signal trigger_d, trigger_q : std_ulogic_vector(0 to 47); -- act=>pc_mm_trace_bus_enable_q, sleep=>Y, needs_sreset=>0, scan=>N +signal debug_bus_in_q : std_ulogic_vector(0 to 87); +signal trace_triggers_in_q : std_ulogic_vector(0 to 11); + +constant trace_bus_enable_offset : integer := 0; +constant debug_mux1_ctrls_offset : integer := trace_bus_enable_offset + 1; +constant debug_mux1_ctrls_loc_offset : integer := debug_mux1_ctrls_offset + pc_mm_debug_mux1_ctrls_q'length; +constant trigger_data_out_offset : natural := debug_mux1_ctrls_loc_offset + pc_mm_debug_mux1_ctrls_loc_q'length; +constant trace_data_out_offset : natural := trigger_data_out_offset + trigger_data_out_q'length; +constant trace_data_out_int_offset : natural := trace_data_out_offset + trace_data_out_q'length; +constant scan_right : natural := trace_data_out_int_offset + trace_data_out_int_q'length-1; + +signal dbg_group0 : std_ulogic_vector(0 to 87); +signal dbg_group1 : std_ulogic_vector(0 to 87); +signal dbg_group2 : std_ulogic_vector(0 to 87); +signal dbg_group3 : std_ulogic_vector(0 to 87); +signal dbg_group4 : std_ulogic_vector(0 to 87); +signal dbg_group5 : std_ulogic_vector(0 to 87); +signal dbg_group6 : std_ulogic_vector(0 to 87); +signal dbg_group7 : std_ulogic_vector(0 to 87); +signal dbg_group8 : std_ulogic_vector(0 to 87); +signal dbg_group9 : std_ulogic_vector(0 to 87); + +signal dbg_group10a : std_ulogic_vector(0 to 87); +signal dbg_group11a : std_ulogic_vector(0 to 87); +signal dbg_group12a : std_ulogic_vector(0 to 87); +signal dbg_group13a : std_ulogic_vector(0 to 87); +signal dbg_group14a : std_ulogic_vector(0 to 87); +signal dbg_group15a : std_ulogic_vector(0 to 87); +signal dbg_group10b : std_ulogic_vector(0 to 87); +signal dbg_group11b : std_ulogic_vector(0 to 87); +signal dbg_group12b : std_ulogic_vector(0 to 87); +signal dbg_group13b : std_ulogic_vector(0 to 87); +signal dbg_group14b : std_ulogic_vector(0 to 87); +signal dbg_group15b : std_ulogic_vector(0 to 87); +signal dbg_group10 : std_ulogic_vector(0 to 87); +signal dbg_group11 : std_ulogic_vector(0 to 87); +signal dbg_group12 : std_ulogic_vector(0 to 87); +signal dbg_group13 : std_ulogic_vector(0 to 87); +signal dbg_group14 : std_ulogic_vector(0 to 87); +signal dbg_group15 : std_ulogic_vector(0 to 87); + +constant group12_offset : natural := 68; +constant group13_offset : natural := 112; + +signal trg_group0 : std_ulogic_vector(0 to 11); +signal trg_group1 : std_ulogic_vector(0 to 11); +signal trg_group2 : std_ulogic_vector(0 to 11); +signal trg_group3a : std_ulogic_vector(0 to 11); +signal trg_group3b : std_ulogic_vector(0 to 11); +signal trg_group3 : std_ulogic_vector(0 to 11); + +signal dbg_group0a : std_ulogic_vector(24 to 55); + +signal tlb_ctl_dbg_tag1_valid : std_ulogic; +signal tlb_ctl_dbg_tag1_thdid : std_ulogic_vector(0 to 1); +signal tlb_ctl_dbg_tag1_type : std_ulogic_vector(0 to 2); +signal tlb_ctl_dbg_tag1_wq : std_ulogic_vector(0 to 1); +signal tlb_ctl_dbg_tag1_gs : std_ulogic; +signal tlb_ctl_dbg_tag1_pr : std_ulogic; +signal tlb_ctl_dbg_tag1_atsel : std_ulogic; +signal tlb_cmp_dbg_tag4_thdid : std_ulogic_vector(0 to 1); -- encoded +signal tlb_cmp_dbg_tag4_type : std_ulogic_vector(0 to 2); -- encoded +signal tlb_cmp_dbg_tag4_valid : std_ulogic; +signal tlb_cmp_dbg_tag5_wayhit : std_ulogic_vector(0 to tlb_ways); +signal tlb_cmp_dbg_tag5_thdid : std_ulogic_vector(0 to 1); -- encoded +signal tlb_cmp_dbg_tag5_type : std_ulogic_vector(0 to 2); -- encoded +signal tlb_cmp_dbg_tag5_class : std_ulogic_vector(0 to 1); -- what kind of derat is it? +signal tlb_cmp_dbg_tag5_iorderat_rel_val : std_ulogic; -- i or d +signal tlb_cmp_dbg_tag5_iorderat_rel_hit : std_ulogic; -- i or d +signal tlb_cmp_dbg_tag5_way : std_ulogic_vector(0 to 167); +signal tlb_cmp_dbg_tag5_lru_dataout : std_ulogic_vector(0 to 11); + + +signal unused_dc : std_ulogic_vector(0 to 11); +-- synopsys translate_off +-- synopsys translate_on + +-- Pervasive +signal pc_func_slp_sl_thold_1 : std_ulogic; +signal pc_func_slp_sl_thold_0 : std_ulogic; +signal pc_func_slp_sl_thold_0_b : std_ulogic; +signal pc_func_slp_sl_force : std_ulogic; +signal pc_func_slp_nsl_thold_1 : std_ulogic; +signal pc_func_slp_nsl_thold_0 : std_ulogic; +signal pc_func_slp_nsl_thold_0_b : std_ulogic; +signal pc_func_slp_nsl_force : std_ulogic; +signal pc_sg_1 : std_ulogic; +signal pc_sg_0 : std_ulogic; +signal pc_fce_1 : std_ulogic; +signal pc_fce_0 : std_ulogic; + +signal siv, sov : std_ulogic_vector(0 to scan_right); + +signal tidn : std_ulogic; +signal tiup : std_ulogic; + + + +begin + +----------------------------------------------------------------------- +-- Logic +----------------------------------------------------------------------- + +tidn <= '0'; +tiup <= '1'; + +pc_mm_debug_mux1_ctrls_loc_d <= pc_mm_debug_mux1_ctrls_q; -- local timing latches + + +----------------------------------------------------------------------- +-- debug input signals from various logic entities +----------------------------------------------------------------------- +debug_d(12) <= tlb_ctl_dbg_tag0_valid; +debug_d(13 to 14) <= tlb_ctl_dbg_tag0_thdid(0 to 1); +debug_d(15 to 17) <= tlb_ctl_dbg_tag0_type(0 to 2); +debug_d(18 to 19) <= tlb_ctl_dbg_tag0_wq(0 to 1); +debug_d(20) <= tlb_ctl_dbg_tag0_gs; +debug_d(21) <= tlb_ctl_dbg_tag0_pr; +debug_d(22) <= tlb_ctl_dbg_tag0_atsel; +debug_d(23) <= '0'; + +tlb_ctl_dbg_tag1_valid <= debug_q(12); +tlb_ctl_dbg_tag1_thdid(0 to 1) <= debug_q(13 to 14); +tlb_ctl_dbg_tag1_type(0 to 2) <= debug_q(15 to 17); +tlb_ctl_dbg_tag1_wq(0 to 1) <= debug_q(18 to 19); +tlb_ctl_dbg_tag1_gs <= debug_q(20); +tlb_ctl_dbg_tag1_pr <= debug_q(21); +tlb_ctl_dbg_tag1_atsel <= debug_q(22); + + + +-- tlb_low_data +-- [0:51] - EPN +-- [52:55] - SIZE (4b) +-- [56:59] - ThdID +-- [60:61] - Class +-- [62] - ExtClass +-- [63] - TID_NZ +-- [64:65] - reserved (2b) +-- [66:73] - 8b for LPID +-- [74:83] - parity 10bits +debug_d(192 to 275) <= TLB_CMP_DBG_TAG4_WAY(0 to 83); +tlb_cmp_dbg_tag5_way(0 to 83) <= debug_q(192 to 275); + +-- tlb_high_data +-- [84] - [0] - X-bit +-- [85:87] - [1:3] - reserved (3b) +-- [88:117] - [4:33] - RPN (30b) +-- [118:119] - [34:35] - R,C +-- [120:121] - [36:37] - WLC (2b) +-- [122] - [38] - ResvAttr +-- [123] - [39] - VF +-- [124] - [40] - IND +-- [125:128] - [41:44] - U0-U3 +-- [129:133] - [45:49] - WIMGE +-- [134:135] - [50:51] - UX,SX +-- [136:137] - [52:53] - UW,SW +-- [138:139] - [54:55] - UR,SR +-- [140] - [56] - GS +-- [141] - [57] - TS +-- [142:143] - [58:59] - reserved (2b) +-- [144:149] - [60:65] - 6b TID msbs +-- [150:157] - [66:73] - 8b TID lsbs +-- [158:167] - [74:83] - parity 10bits +debug_d(276 to 359) <= TLB_CMP_DBG_TAG4_WAY(84 to 167); +tlb_cmp_dbg_tag5_way(84 to 167) <= debug_q(276 to 359); + +-- lru data format +-- [0:3] - valid(0:3) +-- [4:6] - LRU +-- [7] - parity +-- [8:11] - iprot(0:3) +-- [12:14] - reserved +-- [15] - parity +debug_d(360 to 371) <= tlb_cmp_dbg_tag4_lru_dataout_q(0 to 11); +tlb_cmp_dbg_tag5_lru_dataout(0 to 11) <= debug_q(360 to 371); + + +trigger_d(0 to 11) <= (others => '0'); +trigger_d(12 to 23) <= (others => '0'); +trigger_d(24 to 35) <= (others => '0'); +trigger_d(36 to 47) <= (others => '0'); + + +--group0 (slowspr interface) +dbg_group0(0) <= spr_dbg_slowspr_val_int; -- spr_int phase +dbg_group0(1) <= spr_dbg_slowspr_rw_int; +dbg_group0(2 to 3) <= spr_dbg_slowspr_etid_int; +dbg_group0(4 to 13) <= spr_dbg_slowspr_addr_int; +dbg_group0(14) <= spr_dbg_slowspr_done_out; -- spr_out phase +dbg_group0(15) <= spr_dbg_match_any_mmu; -- spr_int phase +dbg_group0(16) <= spr_dbg_match_any_mas; +dbg_group0(17) <= spr_dbg_match_pid; +dbg_group0(18) <= spr_dbg_match_lpidr; +dbg_group0(19) <= spr_dbg_match_mas2; +dbg_group0(20) <= spr_dbg_match_mas01_64b; +dbg_group0(21) <= spr_dbg_match_mas56_64b; +dbg_group0(22) <= spr_dbg_match_mas73_64b; +dbg_group0(23) <= spr_dbg_match_mas81_64b; + +-- alternate bit muxes when 64b decodes 19:23=00000 +dbg_group0a(24) <= spr_dbg_match_mmucr0; +dbg_group0a(25) <= spr_dbg_match_mmucr1; +dbg_group0a(26) <= spr_dbg_match_mmucr2; +dbg_group0a(27) <= spr_dbg_match_mmucr3; +dbg_group0a(28) <= spr_dbg_match_mmucsr0; +dbg_group0a(29) <= spr_dbg_match_mmucfg; +dbg_group0a(30) <= spr_dbg_match_tlb0cfg; +dbg_group0a(31) <= spr_dbg_match_tlb0ps; +dbg_group0a(32) <= spr_dbg_match_lratcfg; +dbg_group0a(33) <= spr_dbg_match_lratps; +dbg_group0a(34) <= spr_dbg_match_eptcfg; +dbg_group0a(35) <= spr_dbg_match_lper; +dbg_group0a(36) <= spr_dbg_match_lperu; +dbg_group0a(37) <= spr_dbg_match_mas0; +dbg_group0a(38) <= spr_dbg_match_mas1; +dbg_group0a(39) <= spr_dbg_match_mas2u; +dbg_group0a(40) <= spr_dbg_match_mas3; +dbg_group0a(41) <= spr_dbg_match_mas4; +dbg_group0a(42) <= spr_dbg_match_mas5; +dbg_group0a(43) <= spr_dbg_match_mas6; +dbg_group0a(44) <= spr_dbg_match_mas7; +dbg_group0a(45) <= spr_dbg_match_mas8; +dbg_group0a(46) <= tlb_mas_tlbre; +dbg_group0a(47) <= tlb_mas_tlbsx_hit; +dbg_group0a(48) <= tlb_mas_tlbsx_miss; +dbg_group0a(49) <= tlb_mas_dtlb_error; +dbg_group0a(50) <= tlb_mas_itlb_error; +dbg_group0a(51) <= tlb_mas_thdid(2) or tlb_mas_thdid(3); -- encoded +dbg_group0a(52) <= tlb_mas_thdid(1) or tlb_mas_thdid(3); -- encoded +dbg_group0a(53) <= lrat_mas_tlbre; +dbg_group0a(54) <= lrat_mas_thdid(2) or lrat_mas_thdid(3); -- encoded +dbg_group0a(55) <= lrat_mas_thdid(1) or lrat_mas_thdid(3); -- encoded +-- alternate bit muxes when 64b decodes 19:23/=00000 +dbg_group0(24 to 55) <= ((24 to 55 => spr_dbg_match_64b) and spr_dbg_slowspr_data_out(0 to 31)) or + ((24 to 55 => not(spr_dbg_match_64b)) and dbg_group0a(24 to 55)); +dbg_group0(56 to 87) <= spr_dbg_slowspr_data_out(32 to 63); + + +-- snoop_attr: +-- 0 -> Local +-- 1:3 -> IS/Class: 0=all, 1=tid, 2=gs, 3=epn, 4=class0, 5=class1, 6=class2, 7=class3 +-- 4:5 -> GS/TS +-- 6:13 -> TID(6:13) +-- 14:17 -> Size +-- 18 -> reserved for tlb, extclass_enable(0) for erats +-- 19 -> mmucsr0.tlb0fi for tlb, or TID_NZ for erats +-- 20:25 -> TID(0:5) +-- 26:33 -> LPID +-- 34 -> IND + +--group1 (invalidate, local generation) +dbg_group1(0 to 4) <= inval_dbg_seq_q(0 to 4); +dbg_group1(5) <= inval_dbg_ex6_valid; +dbg_group1(6 to 7) <= inval_dbg_ex6_thdid(0 to 1); -- encoded +dbg_group1(8 to 9) <= inval_dbg_ex6_ttype(1 to 2); -- encoded +dbg_group1(10) <= htw_lsu_req_valid; +dbg_group1(11) <= mmucsr0_tlb0fi; +dbg_group1(12) <= tlbwe_back_inv_valid; +dbg_group1(13) <= inval_dbg_snoop_forme; +dbg_group1(14) <= inval_dbg_an_ac_back_inv_q(4); -- L bit +dbg_group1(15) <= inval_dbg_an_ac_back_inv_q(7); -- local bit +dbg_group1(16 to 50) <= inval_dbg_snoop_attr_q(0 to 34); +dbg_group1(51 to 52) <= inval_dbg_snoop_attr_tlb_spec_q(18 to 19); +dbg_group1(53 to 87) <= inval_dbg_snoop_vpn_q(17 to 51); + + +--group2 (invalidate, bus snoops) +dbg_group2(0 to 4) <= inval_dbg_seq_q(0 to 4); +dbg_group2(5) <= inval_dbg_snoop_forme; +dbg_group2(6) <= inval_dbg_snoop_local_reject; +dbg_group2(7 to 13) <= inval_dbg_an_ac_back_inv_q(2 to 8); -- 2=valid b, 3=target b, 4=L, 5=GS, 6=IND, 7=local, 8=reject +dbg_group2(14 to 21) <= inval_dbg_an_ac_back_inv_lpar_id_q(0 to 7); +dbg_group2(22 to 63) <= inval_dbg_an_ac_back_inv_addr_q(22 to 63); +dbg_group2(64 to 66) <= inval_dbg_snoop_valid_q(0 to 2); +dbg_group2(67 to 87) <= inval_dbg_snoop_attr_q(0 to 19) & inval_dbg_snoop_attr_q(34); + + +--group3 (lsu interface) +dbg_group3(0 to 4) <= inval_dbg_seq_q(0 to 4); +dbg_group3(5) <= inval_dbg_ex6_valid; +dbg_group3(6 to 7) <= inval_dbg_ex6_thdid(0 to 1); -- encoded +dbg_group3(8 to 9) <= inval_dbg_ex6_ttype(1 to 2); -- encoded +dbg_group3(10) <= inval_dbg_snoop_forme; +dbg_group3(11) <= inval_dbg_an_ac_back_inv_q(7); -- 2=valid b, 3=target b, 4=L, 5=GS, 6=IND, 7=local, 8=reject +dbg_group3(12) <= xu_mm_lmq_stq_empty; +dbg_group3(13) <= iu_mm_lmq_empty; +dbg_group3(14 to 15) <= htw_dbg_seq_q(0 to 1); +dbg_group3(16) <= htw_lsu_req_valid; +dbg_group3(17 to 18) <= htw_dbg_lsu_thdid(0 to 1); +dbg_group3(19 to 20) <= htw_lsu_ttype(0 to 1); +dbg_group3(21) <= xu_mm_lsu_token; +dbg_group3(22) <= inval_dbg_lsu_tokens_q(1); +dbg_group3(23) <= or_reduce(mm_xu_lsu_req); +dbg_group3(24 to 25) <= mm_xu_lsu_ttype; -- 0=tlbivax_op L=0, 1=tlbi_complete, 2=mmu read with core_tag=01100, 3=mmu read with core_tag=01101 +dbg_group3(26 to 30) <= mm_xu_lsu_wimge; +dbg_group3(31) <= mm_xu_lsu_ind; -- tlbivax sec enc data +dbg_group3(32) <= mm_xu_lsu_gs; -- tlbivax sec enc data +dbg_group3(33) <= mm_xu_lsu_lbit; -- tlbivax sec enc data, "L" bit, for large vs. small +dbg_group3(34 to 37) <= mm_xu_lsu_u; +dbg_group3(38 to 45) <= mm_xu_lsu_lpid; -- tlbivax lpar id data +dbg_group3(46 to 87) <= mm_xu_lsu_addr(22 to 63); + + +tlb_cmp_dbg_tag5_iorderat_rel_val <= or_reduce(tlb_cmp_dbg_tag5_erat_rel_val(0 to 3) or tlb_cmp_dbg_tag5_erat_rel_val(5 to 8)); -- i or d +tlb_cmp_dbg_tag5_iorderat_rel_hit <= tlb_cmp_dbg_tag5_erat_rel_val(4) or tlb_cmp_dbg_tag5_erat_rel_val(9); -- i or d + +--group4 (sequencers, the big picture) +dbg_group4(0 to 5) <= tlb_ctl_dbg_seq_q(0 to 5); -- tlb_seq_q +dbg_group4(6 to 7) <= tlb_ctl_dbg_tag0_thdid(0 to 1); -- encoded +dbg_group4(8 to 10) <= tlb_ctl_dbg_tag0_type(0 to 2); -- encoded +dbg_group4(11) <= tlb_ctl_dbg_any_tag_flush_sig; +dbg_group4(12 to 15) <= tlb_cmp_dbg_tag4_wayhit(0 to 3); +dbg_group4(16 to 19) <= mm_xu_eratmiss_done(0 to 3); +dbg_group4(20 to 23) <= mm_iu_barrier_done(0 to 3); +dbg_group4(24 to 27) <= mm_xu_ex3_flush_req(0 to 3); +dbg_group4(28) <= tlb_cmp_dbg_tag5_iorderat_rel_val; -- i or d +dbg_group4(29) <= tlb_cmp_dbg_tag5_iorderat_rel_hit; -- i or d +dbg_group4(30 to 31) <= htw_dbg_seq_q(0 to 1); +dbg_group4(32 to 34) <= htw_dbg_pte0_seq_q(0 to 2); +dbg_group4(35 to 37) <= htw_dbg_pte1_seq_q(0 to 2); +dbg_group4(38 to 42) <= inval_dbg_seq_q(0 to 4); +dbg_group4(43) <= mmucsr0_tlb0fi; +dbg_group4(44) <= inval_dbg_ex6_valid; +dbg_group4(45 to 46) <= inval_dbg_ex6_thdid(0 to 1); -- encoded +dbg_group4(47 to 49) <= inval_dbg_ex6_ttype(0 to 2); -- encoded tlbilx & tlbivax & eratilx & erativax, csync, isync +dbg_group4(50) <= inval_dbg_snoop_forme; +dbg_group4(51 to 57) <= inval_dbg_an_ac_back_inv_q(2 to 8); -- 2=valid b, 3=target b, 4=L, 5=GS, 6=IND, 7=local, 8=reject +dbg_group4(58) <= xu_mm_lmq_stq_empty; +dbg_group4(59) <= iu_mm_lmq_empty; +dbg_group4(60 to 63) <= mm_xu_hold_req(0 to 3); +dbg_group4(64 to 67) <= xu_mm_hold_ack(0 to 3); +dbg_group4(68 to 71) <= mm_xu_hold_done(0 to 3); +dbg_group4(72 to 74) <= inval_dbg_snoop_valid_q(0 to 2); +dbg_group4(75 to 77) <= inval_dbg_snoop_ack_q(0 to 2); +dbg_group4(78) <= or_reduce(mm_xu_lsu_req); +dbg_group4(79 to 80) <= mm_xu_lsu_ttype; -- 0=tlbivax_op L=0, 1=tlbi_complete, 2=mmu read with core_tag=01100, 3=mmu read with core_tag=01101 +dbg_group4(81) <= or_reduce(mm_xu_illeg_instr); +dbg_group4(82 to 85) <= tlb_cmp_dbg_tag5_except_type_q(0 to 3); -- tag5 except valid/type, (hv_priv | lrat_miss | pt_fault | pt_inelig) +dbg_group4(86 to 87) <= tlb_cmp_dbg_tag5_except_thdid_q(0 to 1); -- tag5 encoded thdid + +--group5 (tlb_req) +dbg_group5(0) <= tlb_req_dbg_ierat_iu5_valid_q; +dbg_group5(1 to 2) <= tlb_req_dbg_ierat_iu5_thdid(0 to 1); -- encoded +dbg_group5(3 to 6) <= tlb_req_dbg_ierat_iu5_state_q(0 to 3); +dbg_group5(7) <= tlb_seq_ierat_req; +dbg_group5(8 to 9) <= tlb_req_dbg_ierat_inptr_q(0 to 1); +dbg_group5(10 to 11) <= tlb_req_dbg_ierat_outptr_q(0 to 1); +dbg_group5(12 to 15) <= tlb_req_dbg_ierat_req_valid_q(0 to 3); +dbg_group5(16 to 19) <= tlb_req_dbg_ierat_req_nonspec_q(0 to 3); +dbg_group5(20 to 27) <= tlb_req_dbg_ierat_req_thdid(0 to 7); -- encoded +dbg_group5(28 to 31) <= tlb_req_dbg_ierat_req_dup_q(0 to 3); +dbg_group5(32) <= tlb_req_dbg_derat_ex6_valid_q; +dbg_group5(33 to 34) <= tlb_req_dbg_derat_ex6_thdid(0 to 1); -- encoded +dbg_group5(35 to 38) <= tlb_req_dbg_derat_ex6_state_q(0 to 3); +dbg_group5(39) <= tlb_seq_derat_req; +dbg_group5(40 to 41) <= tlb_req_dbg_derat_inptr_q(0 to 1); +dbg_group5(42 to 43) <= tlb_req_dbg_derat_outptr_q(0 to 1); +dbg_group5(44 to 47) <= tlb_req_dbg_derat_req_valid_q(0 to 3); +dbg_group5(48 to 55) <= tlb_req_dbg_derat_req_thdid(0 to 7); -- encoded +dbg_group5(56 to 63) <= tlb_req_dbg_derat_req_ttype_q(0 to 7); +dbg_group5(64 to 67) <= tlb_req_dbg_derat_req_dup_q(0 to 3); +dbg_group5(68 to 87) <= tlb_cmp_dbg_erat_dup_q(0 to 19); + + -- unused tag bits for certain ops are re-purposed as below: + -- unused tagpos_is def is mas1_v, mas1_iprot for tlbwe, and is pte.valid & 0 for ptereloads + -- unused tagpos_pt, tagpos_recform def are mas8_tgs, mas1_ts for tlbwe + -- unused tagpos_atsel | tagpos_esel used as indirect entry's thdid to update tlb_entry.thdid for ptereloads + -- unused tagpos_wq used as htw reserv write enab & dup bits (set in htw) for ptereloads + -- unused esel for derat,ierat,tlbsx,tlbsrx becomes tlb_seq page size attempted number (1 thru 5) + -- unused "is" for derat,ierat,tlbsx,tlbsrx becomes tlb_seq page size attempted number msb (9 thru 13, or 17 thru 21) + -- unused HES bit for snoops is used as mmucsr0.tlb0fi full invalidate of all non-protected entries + +-- some encoding of debug sigs + -- ttype: derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload +tlb_cmp_dbg_tag4_valid <= or_reduce(tlb_cmp_dbg_tag4(tagpos_thdid to tagpos_thdid+3)); + +tlb_cmp_dbg_tag4_thdid(0) <= (tlb_cmp_dbg_tag4(tagpos_thdid+2) or tlb_cmp_dbg_tag4(tagpos_thdid+3)); -- encoded +tlb_cmp_dbg_tag4_thdid(1) <= (tlb_cmp_dbg_tag4(tagpos_thdid+1) or tlb_cmp_dbg_tag4(tagpos_thdid+3)); -- encoded + +tlb_cmp_dbg_tag4_type(0) <= (tlb_cmp_dbg_tag4(tagpos_type_snoop) or tlb_cmp_dbg_tag4(tagpos_type_tlbre) or + tlb_cmp_dbg_tag4(tagpos_type_tlbwe) or tlb_cmp_dbg_tag4(tagpos_type_ptereload)); -- encoded +tlb_cmp_dbg_tag4_type(1) <= (tlb_cmp_dbg_tag4(tagpos_type_tlbsx) or tlb_cmp_dbg_tag4(tagpos_type_tlbsrx) or + tlb_cmp_dbg_tag4(tagpos_type_tlbwe) or tlb_cmp_dbg_tag4(tagpos_type_ptereload)); -- encoded +tlb_cmp_dbg_tag4_type(2) <= (tlb_cmp_dbg_tag4(tagpos_type_ierat) or tlb_cmp_dbg_tag4(tagpos_type_tlbsrx) or + tlb_cmp_dbg_tag4(tagpos_type_tlbre) or tlb_cmp_dbg_tag4(tagpos_type_ptereload)); -- encoded + +--group6 (general erat and search compare values, truncated epn) +dbg_group6(0) <= tlb_cmp_dbg_tag4_valid; -- or_reduce of thdid; +dbg_group6(1 to 2) <= tlb_cmp_dbg_tag4_thdid(0 to 1); -- encoded +dbg_group6(3 to 5) <= tlb_cmp_dbg_tag4_type(0 to 2); -- encoded +dbg_group6(6 to 7) <= tlb_cmp_dbg_tag4(tagpos_class to tagpos_class+1); +dbg_group6(8 to 9) <= tlb_cmp_dbg_tag4(tagpos_is to tagpos_is+1); +dbg_group6(10 to 12) <= tlb_cmp_dbg_tag4(tagpos_esel to tagpos_esel+2); +dbg_group6(13) <= tlb_cmp_dbg_tag4(tagpos_cm); +dbg_group6(14) <= tlb_cmp_dbg_tag4(tagpos_pr); +dbg_group6(15) <= tlb_cmp_dbg_tag4(tagpos_ind); +dbg_group6(16) <= tlb_cmp_dbg_tag4(tagpos_endflag); +dbg_group6(17 to 23) <= tlb_cmp_dbg_addr4(0 to 6); +dbg_group6(24 to 27) <= tlb_cmp_dbg_tag4_wayhit(0 to tlb_ways-1); +dbg_group6(28) <= tlb_cmp_dbg_tag4(tagpos_gs); +dbg_group6(29 to 36) <= tlb_cmp_dbg_tag4(tagpos_lpid to tagpos_lpid+7); +dbg_group6(37) <= tlb_cmp_dbg_tag4(tagpos_as); +dbg_group6(38 to 51) <= tlb_cmp_dbg_tag4(tagpos_pid to tagpos_pid+13); +dbg_group6(52 to 87) <= tlb_cmp_dbg_tag4(tagpos_epn+16 to tagpos_epn+51); + + + +--group7 (detailed compare/match) +dbg_group7(0) <= tlb_cmp_dbg_tag4_valid; +dbg_group7(1 to 2) <= tlb_cmp_dbg_tag4_thdid(0 to 1); +dbg_group7(3 to 5) <= tlb_cmp_dbg_tag4_type(0 to 2); +dbg_group7(6 to 7) <= tlb_cmp_dbg_tag4(tagpos_is to tagpos_is+1); +dbg_group7(8 to 9) <= tlb_cmp_dbg_tag4(tagpos_class to tagpos_class+1); +dbg_group7(10 to 12) <= tlb_cmp_dbg_tag4(tagpos_esel to tagpos_esel+2); +dbg_group7(13 to 19) <= tlb_cmp_dbg_addr4(0 to 6); +dbg_group7(20 to 23) <= tlb_cmp_dbg_tag4_wayhit(0 to 3); + +debug_d(24 to 32) <= tlb_cmp_dbg_addr_enable(0 to 8); -- these are tag3 versions coming in +debug_d(33) <= tlb_cmp_dbg_pgsize_enable; +debug_d(34) <= tlb_cmp_dbg_class_enable; +debug_d(35 to 36) <= tlb_cmp_dbg_extclass_enable(0 to 1); +debug_d(37 to 38) <= tlb_cmp_dbg_state_enable(0 to 1); +debug_d(39) <= tlb_cmp_dbg_thdid_enable; +debug_d(40) <= tlb_cmp_dbg_pid_enable; +debug_d(41) <= tlb_cmp_dbg_lpid_enable; +debug_d(42) <= tlb_cmp_dbg_ind_enable; +debug_d(43) <= tlb_cmp_dbg_iprot_enable; +debug_d(44) <= tlb_cmp_dbg_way0_entry_v; +debug_d(45) <= tlb_cmp_dbg_way0_addr_match; +debug_d(46) <= tlb_cmp_dbg_way0_pgsize_match; +debug_d(47) <= tlb_cmp_dbg_way0_class_match; +debug_d(48) <= tlb_cmp_dbg_way0_extclass_match; +debug_d(49) <= tlb_cmp_dbg_way0_state_match; +debug_d(50) <= tlb_cmp_dbg_way0_thdid_match; +debug_d(51) <= tlb_cmp_dbg_way0_pid_match; +debug_d(52) <= tlb_cmp_dbg_way0_lpid_match; +debug_d(53) <= tlb_cmp_dbg_way0_ind_match; +debug_d(54) <= tlb_cmp_dbg_way0_iprot_match; +debug_d(55) <= tlb_cmp_dbg_way1_entry_v; +debug_d(56) <= tlb_cmp_dbg_way1_addr_match; +debug_d(57) <= tlb_cmp_dbg_way1_pgsize_match; +debug_d(58) <= tlb_cmp_dbg_way1_class_match; +debug_d(59) <= tlb_cmp_dbg_way1_extclass_match; +debug_d(60) <= tlb_cmp_dbg_way1_state_match; +debug_d(61) <= tlb_cmp_dbg_way1_thdid_match; +debug_d(62) <= tlb_cmp_dbg_way1_pid_match; +debug_d(63) <= tlb_cmp_dbg_way1_lpid_match; +debug_d(64) <= tlb_cmp_dbg_way1_ind_match; +debug_d(65) <= tlb_cmp_dbg_way1_iprot_match; +debug_d(66) <= tlb_cmp_dbg_way2_entry_v; +debug_d(67) <= tlb_cmp_dbg_way2_addr_match; +debug_d(68) <= tlb_cmp_dbg_way2_pgsize_match; +debug_d(69) <= tlb_cmp_dbg_way2_class_match; +debug_d(70) <= tlb_cmp_dbg_way2_extclass_match; +debug_d(71) <= tlb_cmp_dbg_way2_state_match; +debug_d(72) <= tlb_cmp_dbg_way2_thdid_match; +debug_d(73) <= tlb_cmp_dbg_way2_pid_match; +debug_d(74) <= tlb_cmp_dbg_way2_lpid_match; +debug_d(75) <= tlb_cmp_dbg_way2_ind_match; +debug_d(76) <= tlb_cmp_dbg_way2_iprot_match; +debug_d(77) <= tlb_cmp_dbg_way3_entry_v; +debug_d(78) <= tlb_cmp_dbg_way3_addr_match; +debug_d(79) <= tlb_cmp_dbg_way3_pgsize_match; +debug_d(80) <= tlb_cmp_dbg_way3_class_match; +debug_d(81) <= tlb_cmp_dbg_way3_extclass_match; +debug_d(82) <= tlb_cmp_dbg_way3_state_match; +debug_d(83) <= tlb_cmp_dbg_way3_thdid_match; +debug_d(84) <= tlb_cmp_dbg_way3_pid_match; +debug_d(85) <= tlb_cmp_dbg_way3_lpid_match; +debug_d(86) <= tlb_cmp_dbg_way3_ind_match; +debug_d(87) <= tlb_cmp_dbg_way3_iprot_match; + +dbg_group7(24 to 87) <= debug_q(24 to 87); -- tag4 phase, see below + + -- unused tag bits for certain ops are re-purposed as below: + -- unused tagpos_is def is mas1_v, mas1_iprot for tlbwe, and is pte.valid & 0 for ptereloads + -- unused tagpos_pt, tagpos_recform def are mas8_tgs, mas1_ts for tlbwe + -- unused tagpos_atsel | tagpos_esel used as indirect entry's thdid to update tlb_entry.thdid for ptereloads + -- unused tagpos_wq used as htw reserv write enab & dup bits (set in htw) for ptereloads + -- unused esel for derat,ierat,tlbsx,tlbsrx becomes tlb_seq page size attempted number (1 thru 5) + -- unused "is" for derat,ierat,tlbsx,tlbsrx becomes tlb_seq page size attempted number msb (9 thru 13, or 17 thru 21) + -- unused HES bit for snoops is used as mmucsr0.tlb0fi full invalidate of all non-protected entries + -- unused class is derat ttype for derat miss, 0=load,1=store,2=epid load,3=epid store + +--group8 (erat miss, tlbre, tlbsx mas updates and parerr) +dbg_group8(0) <= tlb_cmp_dbg_tag4_valid; +dbg_group8(1 to 2) <= tlb_cmp_dbg_tag4_thdid(0 to 1); +dbg_group8(3 to 5) <= tlb_cmp_dbg_tag4_type(0 to 2); +dbg_group8(6 to 7) <= tlb_cmp_dbg_tag4(tagpos_class to tagpos_class+1); +dbg_group8(8) <= tlb_cmp_dbg_tag4(tagpos_cm); +dbg_group8(9) <= tlb_cmp_dbg_tag4(tagpos_gs); +dbg_group8(10) <= tlb_cmp_dbg_tag4(tagpos_pr); +dbg_group8(11) <= tlb_cmp_dbg_tag4(tagpos_endflag); +dbg_group8(12) <= tlb_cmp_dbg_tag4(tagpos_atsel); +dbg_group8(13 to 15) <= tlb_cmp_dbg_tag4(tagpos_esel to tagpos_esel+2); +dbg_group8(16 to 19) <= tlb_cmp_dbg_tag4(tagpos_size to tagpos_size+3); +dbg_group8(20 to 33) <= tlb_cmp_dbg_tag4(tagpos_pid to tagpos_pid+13); +dbg_group8(34 to 58) <= tlb_cmp_dbg_tag4(tagpos_epn+27 to tagpos_epn+51); +dbg_group8(59 to 65) <= tlb_cmp_dbg_addr4(0 to 6); +dbg_group8(66 to 69) <= tlb_cmp_dbg_tag4_wayhit(0 to tlb_ways-1); +dbg_group8(70) <= tlb_mas_dtlb_error; +dbg_group8(71) <= tlb_mas_itlb_error; +dbg_group8(72) <= tlb_mas_tlbsx_hit; +dbg_group8(73) <= tlb_mas_tlbsx_miss; +dbg_group8(74) <= tlb_mas_tlbre; +dbg_group8(75) <= lrat_mas_tlbre; +dbg_group8(76) <= lrat_mas_tlbsx_hit; +dbg_group8(77 ) <= lrat_mas_tlbsx_miss; +dbg_group8(78 to 80) <= lrat_tag4_hit_entry(0 to 2); +dbg_group8(81 to 85) <= tlb_cmp_dbg_tag4_parerr(0 to 4); -- way0 to 3, lru +dbg_group8(86) <= or_reduce(mm_xu_cr0_eq_valid); +dbg_group8(87) <= or_reduce(mm_xu_cr0_eq and mm_xu_cr0_eq_valid); + + +--group9 (tlbwe, ptereload write control) +dbg_group9(0) <= tlb_cmp_dbg_tag4_valid; +dbg_group9(1 to 2) <= tlb_cmp_dbg_tag4_thdid(0 to 1); +dbg_group9(3 to 5) <= tlb_cmp_dbg_tag4_type(0 to 2); +dbg_group9(6) <= tlb_cmp_dbg_tag4(tagpos_gs); +dbg_group9(7) <= tlb_cmp_dbg_tag4(tagpos_pr); +dbg_group9(8) <= tlb_cmp_dbg_tag4(tagpos_cm); +dbg_group9(9) <= tlb_cmp_dbg_tag4(tagpos_hes); +dbg_group9(10 to 11) <= tlb_cmp_dbg_tag4(tagpos_wq to tagpos_wq+1); +dbg_group9(12) <= tlb_cmp_dbg_tag4(tagpos_atsel); +dbg_group9(13 to 15) <= tlb_cmp_dbg_tag4(tagpos_esel to tagpos_esel+2); +dbg_group9(16 to 17) <= tlb_cmp_dbg_tag4(tagpos_is to tagpos_is+1); +dbg_group9(18) <= tlb_cmp_dbg_tag4(tagpos_pt); +dbg_group9(19) <= tlb_cmp_dbg_tag4(tagpos_recform); +dbg_group9(20) <= tlb_cmp_dbg_tag4(tagpos_ind); +dbg_group9(21 to 27) <= tlb_cmp_dbg_addr4(0 to 6); +dbg_group9(28 to 31) <= tlb_cmp_dbg_tag4_wayhit(0 to tlb_ways-1); +dbg_group9(32 to 43) <= tlb_cmp_dbg_tag4_lru_dataout_q(0 to 11); -- current valid. lru, iprot +dbg_group9(44 to 47) <= lrat_tag4_hit_status(0 to 3); +dbg_group9(48 to 50) <= lrat_tag4_hit_entry(0 to 2); +dbg_group9(51) <= or_reduce(mm_iu_barrier_done); +dbg_group9(52 to 55) <= tlb_ctl_dbg_resv_valid(0 to 3); +dbg_group9(56 to 59) <= tlb_ctl_dbg_resv_match_vec_q(0 to 3); -- tag4 +dbg_group9(60 to 63) <= tlb_ctl_dbg_tag5_tlb_write_q(0 to 3); -- tag5 +dbg_group9(64 to 75) <= tlb_cmp_dbg_tag5_lru_datain_q(0 to 11); -- tag5 +dbg_group9(76) <= tlb_cmp_dbg_tag5_lru_write; -- all bits the same +dbg_group9(77) <= or_reduce(mm_xu_illeg_instr); +dbg_group9(78 to 81) <= tlb_cmp_dbg_tag5_except_type_q(0 to 3); -- tag5 except valid/type, (hv_priv | lrat_miss | pt_fault | pt_inelig) +dbg_group9(82 to 83) <= tlb_cmp_dbg_tag5_except_thdid_q(0 to 1); -- tag5 encoded thdid +dbg_group9(84) <= tlbwe_back_inv_valid; -- valid +dbg_group9(85) <= tlbwe_back_inv_attr(18); -- not extclass enable +dbg_group9(86) <= tlbwe_back_inv_attr(19); -- tid_nz +dbg_group9(87) <= '0'; + + + +debug_d(0 to 1) <= tlb_cmp_dbg_tag4_thdid; -- tag5 thdid encoded +debug_d(2 to 4) <= tlb_cmp_dbg_tag4_type; -- tag5 type encoded +debug_d(5 to 6) <= tlb_cmp_dbg_tag4(tagpos_class to tagpos_class+1); -- what kind of derat is it? +debug_d(7 to 11) <= tlb_cmp_dbg_tag4_wayhit(0 to tlb_ways); + +tlb_cmp_dbg_tag5_thdid(0 to 1) <= debug_q(0 to 1); +tlb_cmp_dbg_tag5_type(0 to 2) <= debug_q(2 to 4); +tlb_cmp_dbg_tag5_class(0 to 1) <= debug_q(5 to 6); +tlb_cmp_dbg_tag5_wayhit(0 to 4) <= debug_q(7 to 11); + + +--group10 (erat reload bus, epn) --------> can mux tlb_datain(0:83) epn for tlbwe/ptereload ops +dbg_group10a(0) <= tlb_cmp_dbg_tag5_iorderat_rel_val; +dbg_group10a(1 to 2) <= tlb_cmp_dbg_tag5_thdid(0 to 1); +dbg_group10a(3 to 5) <= tlb_cmp_dbg_tag5_type(0 to 2); +dbg_group10a(6 to 7) <= tlb_cmp_dbg_tag5_class(0 to 1); -- what kind of derat is it? +dbg_group10a(8 to 11) <= tlb_cmp_dbg_tag5_wayhit(0 to tlb_ways-1); +dbg_group10a(12 to 21) <= tlb_cmp_dbg_tag5_erat_rel_val(0 to 9); +dbg_group10a(22 to 87) <= tlb_cmp_dbg_tag5_erat_rel_data(eratpos_epn to eratpos_wren); + +-- tlb_low_data +-- [0:51] - EPN +-- [52:55] - SIZE (4b) +-- [56:59] - ThdID +-- [60:61] - Class +-- [62] - ExtClass +-- [63] - TID_NZ +-- [64:65] - reserved (2b) +-- [66:73] - 8b for LPID +-- [74:83] - parity 10bits +dbg_group10b(0 to 83) <= tlb_cmp_dbg_tag5_tlb_datain_q(0 to 83); -- tlb_datain epn +dbg_group10b(84) <= Eq(tlb_cmp_dbg_tag5_type(0 to 2),"110") and or_reduce(tlb_ctl_dbg_tag5_tlb_write_q); -- tlbwe +dbg_group10b(85) <= Eq(tlb_cmp_dbg_tag5_type(0 to 2),"111") and or_reduce(tlb_ctl_dbg_tag5_tlb_write_q); -- ptereload +dbg_group10b(86) <= (tlb_ctl_dbg_tag5_tlb_write_q(2) or tlb_ctl_dbg_tag5_tlb_write_q(3)); +dbg_group10b(87) <= (tlb_ctl_dbg_tag5_tlb_write_q(1) or tlb_ctl_dbg_tag5_tlb_write_q(3)); + +dbg_group10 <= dbg_group10b when mmucr2(8)='1' else dbg_group10a; + + +--group11 (erat reload bus, rpn) --------> can mux tlb_datain(84:167) rpn for tlbwe/ptereload ops +dbg_group11a(0) <= tlb_cmp_dbg_tag5_iorderat_rel_val; +dbg_group11a(1 to 2) <= tlb_cmp_dbg_tag5_thdid(0 to 1); +dbg_group11a(3 to 5) <= tlb_cmp_dbg_tag5_type(0 to 2); +dbg_group11a(6 to 7) <= tlb_cmp_dbg_tag5_class(0 to 1); -- what kind of derat is it? +dbg_group11a(8 to 11) <= tlb_cmp_dbg_tag5_wayhit(0 to tlb_ways-1); +dbg_group11a(12 to 21) <= tlb_cmp_dbg_tag5_erat_rel_val(0 to 9); +dbg_group11a(22 to 87) <= tlb_cmp_dbg_tag5_erat_rel_data(eratpos_rpnrsvd to eratpos_tid+7); + +-- tlb_high_data +-- [84] - [0] - X-bit +-- [85:87] - [1:3] - reserved (3b) +-- [88:117] - [4:33] - RPN (30b) +-- [118:119] - [34:35] - R,C +-- [120:121] - [36:37] - WLC (2b) +-- [122] - [38] - ResvAttr +-- [123] - [39] - VF +-- [124] - [40] - IND +-- [125:128] - [41:44] - U0-U3 +-- [129:133] - [45:49] - WIMGE +-- [134:135] - [50:51] - UX,SX +-- [136:137] - [52:53] - UW,SW +-- [138:139] - [54:55] - UR,SR +-- [140] - [56] - GS +-- [141] - [57] - TS +-- [142:143] - [58:59] - reserved (2b) +-- [144:149] - [60:65] - 6b TID msbs +-- [150:157] - [66:73] - 8b TID lsbs +-- [158:167] - [74:83] - parity 10bits +dbg_group11b(0 to 83) <= tlb_cmp_dbg_tag5_tlb_datain_q(84 to 167); -- tlb_datain rpn +dbg_group11b(84) <= Eq(tlb_cmp_dbg_tag5_type(0 to 2),"110") and or_reduce(tlb_ctl_dbg_tag5_tlb_write_q); -- tlbwe +dbg_group11b(85) <= Eq(tlb_cmp_dbg_tag5_type(0 to 2),"111") and or_reduce(tlb_ctl_dbg_tag5_tlb_write_q); -- ptereload +dbg_group11b(86) <= (tlb_ctl_dbg_tag5_tlb_write_q(2) or tlb_ctl_dbg_tag5_tlb_write_q(3)); +dbg_group11b(87) <= (tlb_ctl_dbg_tag5_tlb_write_q(1) or tlb_ctl_dbg_tag5_tlb_write_q(3)); + +dbg_group11 <= dbg_group11b when mmucr2(8)='1' else dbg_group11a; + +--group12 (reservations) +dbg_group12a(0) <= tlb_ctl_dbg_tag1_valid; +dbg_group12a(1 to 2) <= tlb_ctl_dbg_tag1_thdid(0 to 1); +dbg_group12a(3 to 5) <= tlb_ctl_dbg_tag1_type(0 to 2); +dbg_group12a(6 to 7) <= tlb_ctl_dbg_tag1_wq(0 to 1); + +dbg_group12a(8 to 11) <= tlb_ctl_dbg_resv_valid(0 to 3); +dbg_group12a(12 to 15) <= tlb_ctl_dbg_set_resv(0 to 3); +dbg_group12a(16 to 19) <= tlb_ctl_dbg_resv_match_vec_q(0 to 3); -- tag4 + +debug_d(group12_offset+20) <= tlb_ctl_dbg_resv0_tag0_lpid_match; +debug_d(group12_offset+21) <= tlb_ctl_dbg_resv0_tag0_pid_match; +debug_d(group12_offset+22) <= tlb_ctl_dbg_resv0_tag0_as_snoop_match; +debug_d(group12_offset+23) <= tlb_ctl_dbg_resv0_tag0_gs_snoop_match; +debug_d(group12_offset+24) <= tlb_ctl_dbg_resv0_tag0_as_tlbwe_match; +debug_d(group12_offset+25) <= tlb_ctl_dbg_resv0_tag0_gs_tlbwe_match; +debug_d(group12_offset+26) <= tlb_ctl_dbg_resv0_tag0_ind_match; +debug_d(group12_offset+27) <= tlb_ctl_dbg_resv0_tag0_epn_loc_match; +debug_d(group12_offset+28) <= tlb_ctl_dbg_resv0_tag0_epn_glob_match; +debug_d(group12_offset+29) <= tlb_ctl_dbg_resv0_tag0_class_match; +debug_d(group12_offset+30) <= tlb_ctl_dbg_resv1_tag0_lpid_match; +debug_d(group12_offset+31) <= tlb_ctl_dbg_resv1_tag0_pid_match; +debug_d(group12_offset+32) <= tlb_ctl_dbg_resv1_tag0_as_snoop_match; +debug_d(group12_offset+33) <= tlb_ctl_dbg_resv1_tag0_gs_snoop_match; +debug_d(group12_offset+34) <= tlb_ctl_dbg_resv1_tag0_as_tlbwe_match; +debug_d(group12_offset+35) <= tlb_ctl_dbg_resv1_tag0_gs_tlbwe_match; +debug_d(group12_offset+36) <= tlb_ctl_dbg_resv1_tag0_ind_match; +debug_d(group12_offset+37) <= tlb_ctl_dbg_resv1_tag0_epn_loc_match; +debug_d(group12_offset+38) <= tlb_ctl_dbg_resv1_tag0_epn_glob_match; +debug_d(group12_offset+39) <= tlb_ctl_dbg_resv1_tag0_class_match; +debug_d(group12_offset+40) <= tlb_ctl_dbg_resv2_tag0_lpid_match; +debug_d(group12_offset+41) <= tlb_ctl_dbg_resv2_tag0_pid_match; +debug_d(group12_offset+42) <= tlb_ctl_dbg_resv2_tag0_as_snoop_match; +debug_d(group12_offset+43) <= tlb_ctl_dbg_resv2_tag0_gs_snoop_match; +debug_d(group12_offset+44) <= tlb_ctl_dbg_resv2_tag0_as_tlbwe_match; +debug_d(group12_offset+45) <= tlb_ctl_dbg_resv2_tag0_gs_tlbwe_match; +debug_d(group12_offset+46) <= tlb_ctl_dbg_resv2_tag0_ind_match; +debug_d(group12_offset+47) <= tlb_ctl_dbg_resv2_tag0_epn_loc_match; +debug_d(group12_offset+48) <= tlb_ctl_dbg_resv2_tag0_epn_glob_match; +debug_d(group12_offset+49) <= tlb_ctl_dbg_resv2_tag0_class_match; +debug_d(group12_offset+50) <= tlb_ctl_dbg_resv3_tag0_lpid_match; +debug_d(group12_offset+51) <= tlb_ctl_dbg_resv3_tag0_pid_match; +debug_d(group12_offset+52) <= tlb_ctl_dbg_resv3_tag0_as_snoop_match; +debug_d(group12_offset+53) <= tlb_ctl_dbg_resv3_tag0_gs_snoop_match; +debug_d(group12_offset+54) <= tlb_ctl_dbg_resv3_tag0_as_tlbwe_match; +debug_d(group12_offset+55) <= tlb_ctl_dbg_resv3_tag0_gs_tlbwe_match; +debug_d(group12_offset+56) <= tlb_ctl_dbg_resv3_tag0_ind_match; +debug_d(group12_offset+57) <= tlb_ctl_dbg_resv3_tag0_epn_loc_match; +debug_d(group12_offset+58) <= tlb_ctl_dbg_resv3_tag0_epn_glob_match; +debug_d(group12_offset+59) <= tlb_ctl_dbg_resv3_tag0_class_match; + +dbg_group12a(20 to 59) <= debug_q(group12_offset+20 to group12_offset+59); -- tag1 + +dbg_group12a(60 to 63) <= tlb_ctl_dbg_clr_resv_q(0 to 3); -- tag5 +dbg_group12a(64 to 67) <= tlb_ctl_dbg_clr_resv_terms(0 to 3); -- tag5, threadwise condensed into to tlbivax, tlbilx, tlbwe, ptereload + +dbg_group12a(68 to 71) <= htw_dbg_req_valid_q(0 to 3); +dbg_group12a(72 to 75) <= htw_dbg_resv_valid_vec(0 to 3); +dbg_group12a(76 to 79) <= htw_dbg_tag4_clr_resv_q(0 to 3); +dbg_group12a(80 to 83) <= htw_dbg_tag4_clr_resv_terms(0 to 3); -- tag4, threadwise condensed into to tlbivax, tlbilx, tlbwe, ptereload +dbg_group12a(84 to 87) <= "0000"; + +-- tlb_low_data +-- [0:51] - EPN +-- [52:55] - SIZE (4b) +-- [56:59] - ThdID +-- [60:61] - Class +-- [62] - ExtClass +-- [63] - TID_NZ +-- [64:65] - reserved (2b) +-- [66:73] - 8b for LPID +-- [74:83] - parity 10bits +dbg_group12b(0 to 83) <= tlb_cmp_dbg_tag5_way(0 to 83); -- tag5 way epn +dbg_group12b(84) <= (tlb_cmp_dbg_tag5_lru_dataout(0) and tlb_cmp_dbg_tag5_wayhit(0)) or + (tlb_cmp_dbg_tag5_lru_dataout(1) and tlb_cmp_dbg_tag5_wayhit(1)) or + (tlb_cmp_dbg_tag5_lru_dataout(2) and tlb_cmp_dbg_tag5_wayhit(2)) or + (tlb_cmp_dbg_tag5_lru_dataout(3) and tlb_cmp_dbg_tag5_wayhit(3)); -- valid +dbg_group12b(85) <= (tlb_cmp_dbg_tag5_lru_dataout(8) and tlb_cmp_dbg_tag5_wayhit(0)) or + (tlb_cmp_dbg_tag5_lru_dataout(9) and tlb_cmp_dbg_tag5_wayhit(1)) or + (tlb_cmp_dbg_tag5_lru_dataout(10) and tlb_cmp_dbg_tag5_wayhit(2)) or + (tlb_cmp_dbg_tag5_lru_dataout(11) and tlb_cmp_dbg_tag5_wayhit(3)); -- iprot +dbg_group12b(86) <= tlb_cmp_dbg_tag5_lru_dataout(4); -- encoded lru way msb +dbg_group12b(87) <= (not(tlb_cmp_dbg_tag5_lru_dataout(4)) and tlb_cmp_dbg_tag5_lru_dataout(5)) or + (tlb_cmp_dbg_tag5_lru_dataout(4) and tlb_cmp_dbg_tag5_lru_dataout(6)); -- encoded lru way lsb + +dbg_group12 <= dbg_group12b when mmucr2(9)='1' else dbg_group12a; + + -- unused tag bits for certain ops are re-purposed as below: + -- unused tagpos_is def is mas1_v, mas1_iprot for tlbwe, and is pte.valid & 0 for ptereloads + -- unused tagpos_pt, tagpos_recform def are mas8_tgs, mas1_ts for tlbwe + -- unused tagpos_atsel | tagpos_esel used as indirect entry's thdid to update tlb_entry.thdid for ptereloads + -- unused tagpos_wq used as htw reserv write enab & dup bits (set in htw) for ptereloads + -- unused esel for derat,ierat,tlbsx,tlbsrx becomes tlb_seq page size attempted number (1 thru 5) + -- unused "is" for derat,ierat,tlbsx,tlbsrx becomes tlb_seq page size attempted number msb (9 thru 13, or 17 thru 21) + -- unused HES bit for snoops is used as mmucsr0.tlb0fi full invalidate of all non-protected entries + -- unused class is derat ttype for derat miss, 0=load,1=store,2=epid load,3=epid store + + -- type: derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload + +--group13 (lrat match logic) +dbg_group13a(0) <= lrat_dbg_tag1_addr_enable; -- tlb_addr_cap_q(1) +dbg_group13a(1) <= tlb_ctl_dbg_tag1_valid; +dbg_group13a(2 to 3) <= tlb_ctl_dbg_tag1_thdid(0 to 1); +dbg_group13a(4 to 5) <= (tlb_ctl_dbg_tag1_type(0) and tlb_ctl_dbg_tag1_type(1)) & (tlb_ctl_dbg_tag1_type(0) and tlb_ctl_dbg_tag1_type(2)); -- tlbsx,tlbre,tlbwe,ptereload +dbg_group13a(6) <= tlb_ctl_dbg_tag1_gs; +dbg_group13a(7) <= tlb_ctl_dbg_tag1_pr; +dbg_group13a(8) <= tlb_ctl_dbg_tag1_atsel; +dbg_group13a(9 to 11) <= lrat_tag3_hit_entry(0 to 2); +dbg_group13a(12 to 15) <= lrat_tag3_hit_status(0 to 3); -- hit_status to val,hit,multihit,inval_pgsize + +debug_d(group13_offset+16) <= lrat_dbg_entry0_addr_match; -- tag1 +debug_d(group13_offset+17) <= lrat_dbg_entry0_lpid_match; +debug_d(group13_offset+18) <= lrat_dbg_entry0_entry_v; +debug_d(group13_offset+19) <= lrat_dbg_entry0_entry_x; +debug_d(group13_offset+20 to group13_offset+23) <= lrat_dbg_entry0_size(0 to 3); +debug_d(group13_offset+24) <= lrat_dbg_entry1_addr_match; -- tag1 +debug_d(group13_offset+25) <= lrat_dbg_entry1_lpid_match; +debug_d(group13_offset+26) <= lrat_dbg_entry1_entry_v; +debug_d(group13_offset+27) <= lrat_dbg_entry1_entry_x; +debug_d(group13_offset+28 to group13_offset+31) <= lrat_dbg_entry1_size(0 to 3); +debug_d(group13_offset+32) <= lrat_dbg_entry2_addr_match; -- tag1 +debug_d(group13_offset+33) <= lrat_dbg_entry2_lpid_match; +debug_d(group13_offset+34) <= lrat_dbg_entry2_entry_v; +debug_d(group13_offset+35) <= lrat_dbg_entry2_entry_x; +debug_d(group13_offset+36 to group13_offset+39) <= lrat_dbg_entry2_size(0 to 3); +debug_d(group13_offset+40) <= lrat_dbg_entry3_addr_match; -- tag1 +debug_d(group13_offset+41) <= lrat_dbg_entry3_lpid_match; +debug_d(group13_offset+42) <= lrat_dbg_entry3_entry_v; +debug_d(group13_offset+43) <= lrat_dbg_entry3_entry_x; +debug_d(group13_offset+44 to group13_offset+47) <= lrat_dbg_entry3_size(0 to 3); +debug_d(group13_offset+48) <= lrat_dbg_entry4_addr_match ; -- tag1 +debug_d(group13_offset+49) <= lrat_dbg_entry4_lpid_match; +debug_d(group13_offset+50) <= lrat_dbg_entry4_entry_v; +debug_d(group13_offset+51) <= lrat_dbg_entry4_entry_x; +debug_d(group13_offset+52 to group13_offset+55) <= lrat_dbg_entry4_size(0 to 3); +debug_d(group13_offset+56) <= lrat_dbg_entry5_addr_match ; -- tag1 +debug_d(group13_offset+57) <= lrat_dbg_entry5_lpid_match; +debug_d(group13_offset+58) <= lrat_dbg_entry5_entry_v; +debug_d(group13_offset+59) <= lrat_dbg_entry5_entry_x; +debug_d(group13_offset+60 to group13_offset+63) <= lrat_dbg_entry5_size(0 to 3); +debug_d(group13_offset+64) <= lrat_dbg_entry6_addr_match; -- tag1 +debug_d(group13_offset+65) <= lrat_dbg_entry6_lpid_match; +debug_d(group13_offset+66) <= lrat_dbg_entry6_entry_v; +debug_d(group13_offset+67) <= lrat_dbg_entry6_entry_x; +debug_d(group13_offset+68 to group13_offset+71) <= lrat_dbg_entry6_size(0 to 3); +debug_d(group13_offset+72) <= lrat_dbg_entry7_addr_match; -- tag1 +debug_d(group13_offset+73) <= lrat_dbg_entry7_lpid_match; +debug_d(group13_offset+74) <= lrat_dbg_entry7_entry_v; +debug_d(group13_offset+75) <= lrat_dbg_entry7_entry_x; +debug_d(group13_offset+76 to group13_offset+79) <= lrat_dbg_entry7_size(0 to 3); + +dbg_group13a(16 to 79) <= debug_q(group13_offset+16 to group13_offset+79); -- tag2 +dbg_group13a(80 to 87) <= lrat_dbg_tag2_matchline_q(0 to 7); + +-- tlb_high_data +-- [84] - [0] - X-bit +-- [85:87] - [1:3] - reserved (3b) +-- [88:117] - [4:33] - RPN (30b) +-- [118:119] - [34:35] - R,C +-- [120:121] - [36:37] - WLC (2b) +-- [122] - [38] - ResvAttr +-- [123] - [39] - VF +-- [124] - [40] - IND +-- [125:128] - [41:44] - U0-U3 +-- [129:133] - [45:49] - WIMGE +-- [134:135] - [50:51] - UX,SX +-- [136:137] - [52:53] - UW,SW +-- [138:139] - [54:55] - UR,SR +-- [140] - [56] - GS +-- [141] - [57] - TS +-- [142:143] - [58:59] - reserved (2b) +-- [144:149] - [60:65] - 6b TID msbs +-- [150:157] - [66:73] - 8b TID lsbs +-- [158:167] - [74:83] - parity 10bits +dbg_group13b(0 to 83) <= tlb_cmp_dbg_tag5_way(84 to 167); -- tag5 way rpn +dbg_group13b(84) <= (tlb_cmp_dbg_tag5_lru_dataout(0) and tlb_cmp_dbg_tag5_wayhit(0)) or + (tlb_cmp_dbg_tag5_lru_dataout(1) and tlb_cmp_dbg_tag5_wayhit(1)) or + (tlb_cmp_dbg_tag5_lru_dataout(2) and tlb_cmp_dbg_tag5_wayhit(2)) or + (tlb_cmp_dbg_tag5_lru_dataout(3) and tlb_cmp_dbg_tag5_wayhit(3)); -- valid +dbg_group13b(85) <= (tlb_cmp_dbg_tag5_lru_dataout(8) and tlb_cmp_dbg_tag5_wayhit(0)) or + (tlb_cmp_dbg_tag5_lru_dataout(9) and tlb_cmp_dbg_tag5_wayhit(1)) or + (tlb_cmp_dbg_tag5_lru_dataout(10) and tlb_cmp_dbg_tag5_wayhit(2)) or + (tlb_cmp_dbg_tag5_lru_dataout(11) and tlb_cmp_dbg_tag5_wayhit(3)); -- iprot +dbg_group13b(86) <= tlb_cmp_dbg_tag5_lru_dataout(4); -- encoded lru way msb +dbg_group13b(87) <= (not(tlb_cmp_dbg_tag5_lru_dataout(4)) and tlb_cmp_dbg_tag5_lru_dataout(5)) or + (tlb_cmp_dbg_tag5_lru_dataout(4) and tlb_cmp_dbg_tag5_lru_dataout(6)); -- encoded lru way lsb + + +dbg_group13 <= dbg_group13b when mmucr2(9)='1' else dbg_group13a; + + +--group14 (htw control) +dbg_group14a(0 to 1) <= htw_dbg_seq_q(0 to 1); +dbg_group14a(2 to 3) <= htw_dbg_inptr_q(0 to 1); +dbg_group14a(4) <= htw_dbg_ptereload_ptr_q; +dbg_group14a(5 to 6) <= htw_dbg_lsuptr_q(0 to 1); +dbg_group14a(7) <= htw_lsu_ttype(1); +dbg_group14a(8 to 9) <= htw_dbg_lsu_thdid(0 to 1); -- encoded +dbg_group14a(10 to 51) <= htw_lsu_addr(22 to 63); +dbg_group14a(52 to 54) <= htw_dbg_pte0_seq_q(0 to 2); +dbg_group14a(55 to 56) <= htw_dbg_pte0_score_ptr_q(0 to 1); +dbg_group14a(57 to 59) <= htw_dbg_pte0_score_cl_offset_q(58 to 60); +dbg_group14a(60 to 62) <= htw_dbg_pte0_score_error_q(0 to 2); +dbg_group14a(63 to 66) <= htw_dbg_pte0_score_qwbeat_q(0 to 3); -- 4 beats of data per CL +dbg_group14a(67) <= htw_dbg_pte0_score_pending_q; +dbg_group14a(68) <= htw_dbg_pte0_score_ibit_q; +dbg_group14a(69) <= htw_dbg_pte0_score_dataval_q; +dbg_group14a(70 to 72) <= htw_dbg_pte1_seq_q(0 to 2); +dbg_group14a(73 to 74) <= htw_dbg_pte1_score_ptr_q(0 to 1); +dbg_group14a(75 to 77) <= htw_dbg_pte1_score_cl_offset_q(58 to 60); +dbg_group14a(78 to 80) <= htw_dbg_pte1_score_error_q(0 to 2); +dbg_group14a(81 to 84) <= htw_dbg_pte1_score_qwbeat_q(0 to 3); -- 4 beats of data per CL +dbg_group14a(85) <= htw_dbg_pte1_score_pending_q; +dbg_group14a(86) <= htw_dbg_pte1_score_ibit_q; +dbg_group14a(87) <= htw_dbg_pte1_score_dataval_q; + +-- tlb_low_data +-- [0:51] - EPN +-- [52:55] - SIZE (4b) +-- [56:59] - ThdID +-- [60:61] - Class +-- [62] - ExtClass +-- [63] - TID_NZ +-- [64:65] - reserved (2b) +-- [66:73] - 8b for LPID +-- [74:83] - parity 10bits + +-- tlb_high_data +-- [84] - [0] - X-bit +-- [85:87] - [1:3] - reserved (3b) +-- [88:117] - [4:33] - RPN (30b) +-- [118:119] - [34:35] - R,C +-- [120:121] - [36:37] - WLC (2b) +-- [122] - [38] - ResvAttr +-- [123] - [39] - VF +-- [124] - [40] - IND +-- [125:128] - [41:44] - U0-U3 +-- [129:133] - [45:49] - WIMGE +-- [134:135] - [50:51] - UX,SX +-- [136:137] - [52:53] - UW,SW +-- [138:139] - [54:55] - UR,SR +-- [140] - [56] - GS +-- [141] - [57] - TS +-- [142:143] - [58:59] - reserved (2b) +-- [144:149] - [60:65] - 6b TID msbs +-- [150:157] - [66:73] - 8b TID lsbs +-- [158:167] - [74:83] - parity 10bits +dbg_group14b(0) <= (tlb_cmp_dbg_tag5_lru_dataout(0) and tlb_cmp_dbg_tag5_wayhit(0)) or + (tlb_cmp_dbg_tag5_lru_dataout(1) and tlb_cmp_dbg_tag5_wayhit(1)) or + (tlb_cmp_dbg_tag5_lru_dataout(2) and tlb_cmp_dbg_tag5_wayhit(2)) or + (tlb_cmp_dbg_tag5_lru_dataout(3) and tlb_cmp_dbg_tag5_wayhit(3)); -- valid +dbg_group14b(1) <= (tlb_cmp_dbg_tag5_lru_dataout(8) and tlb_cmp_dbg_tag5_wayhit(0)) or + (tlb_cmp_dbg_tag5_lru_dataout(9) and tlb_cmp_dbg_tag5_wayhit(1)) or + (tlb_cmp_dbg_tag5_lru_dataout(10) and tlb_cmp_dbg_tag5_wayhit(2)) or + (tlb_cmp_dbg_tag5_lru_dataout(11) and tlb_cmp_dbg_tag5_wayhit(3)); -- iprot + +dbg_group14b(2) <= tlb_cmp_dbg_tag5_way(140); -- gs +dbg_group14b(3) <= tlb_cmp_dbg_tag5_way(141); -- ts +dbg_group14b(4 to 11) <= tlb_cmp_dbg_tag5_way(66 to 73); -- tlpid +dbg_group14b(12 to 25) <= tlb_cmp_dbg_tag5_way(144 to 157); -- tid, 14bits +dbg_group14b(26 to 45) <= tlb_cmp_dbg_tag5_way(32 to 51); -- epn truncated to lower 20b +dbg_group14b(46 to 49) <= tlb_cmp_dbg_tag5_way(52 to 55); -- size +dbg_group14b(50 to 53) <= tlb_cmp_dbg_tag5_way(56 to 59); -- thdid +dbg_group14b(54) <= tlb_cmp_dbg_tag5_way(84); -- xbit +dbg_group14b(55) <= tlb_cmp_dbg_tag5_way(40); -- ind +dbg_group14b(56 to 57) <= tlb_cmp_dbg_tag5_way(60 to 61); -- class +dbg_group14b(58 to 77) <= tlb_cmp_dbg_tag5_way(98 to 117); -- rpn truncated to lower 20b +dbg_group14b(78 to 81) <= tlb_cmp_dbg_tag5_way(130 to 133); -- imge +dbg_group14b(82 to 87) <= tlb_cmp_dbg_tag5_way(134 to 139); -- user/sup prot bits + +dbg_group14 <= dbg_group14b when mmucr2(10)='1' else dbg_group14a; + +--group15 (ptereload pte) +dbg_group15a(0 to 1) <= htw_dbg_seq_q(0 to 1); +dbg_group15a(2 to 4) <= htw_dbg_pte0_seq_q(0 to 2); +dbg_group15a(5 to 7) <= htw_dbg_pte1_seq_q(0 to 2); +dbg_group15a(8) <= htw_lsu_req_valid; +dbg_group15a(9 to 21) <= htw_lsu_addr(48 to 60); +dbg_group15a(22) <= htw_dbg_ptereload_ptr_q; +dbg_group15a(23) <= ptereload_req_taken; +dbg_group15a(24 to 87) <= ptereload_req_pte(0 to 63); -- pte entry + + +dbg_group15b(0 to 73) <= tlb_cmp_dbg_tag5_way(0 to 73); -- tag5 way epn +dbg_group15b(74 to 77) <= tlb_cmp_dbg_tag5_lru_dataout(0 to 3); +dbg_group15b(78 to 81) <= tlb_cmp_dbg_tag5_lru_dataout(8 to 11); +dbg_group15b(82) <= tlb_cmp_dbg_tag5_lru_dataout(4); -- encoded lsu way msb +dbg_group15b(83) <= (not(tlb_cmp_dbg_tag5_lru_dataout(4)) and tlb_cmp_dbg_tag5_lru_dataout(5)) or + (tlb_cmp_dbg_tag5_lru_dataout(4) and tlb_cmp_dbg_tag5_lru_dataout(6)); -- encoded lsu way lsb +dbg_group15b(84 to 87) <= tlb_cmp_dbg_tag5_wayhit(0 to 3); + +dbg_group15 <= dbg_group15b when mmucr2(10)='1' else dbg_group15a; + + +-- trigger group0 +trg_group0(0) <= not(tlb_ctl_dbg_seq_idle); +trg_group0(1 to 2) <= tlb_ctl_dbg_tag0_thdid(0 to 1); -- encoded +trg_group0(3 to 5) <= tlb_ctl_dbg_tag0_type(0 to 2); -- encoded +trg_group0(6) <= not(inval_dbg_seq_idle); +trg_group0(7) <= inval_dbg_seq_snoop_inprogress; -- bus snoop +trg_group0(8) <= not(htw_dbg_seq_idle); +trg_group0(9) <= not(htw_dbg_pte0_seq_idle); +trg_group0(10) <= not(htw_dbg_pte1_seq_idle); +trg_group0(11) <= tlb_cmp_dbg_tag5_any_exception; -- big or gate + + +-- trigger group1 +trg_group1(0 to 5) <= tlb_ctl_dbg_seq_q(0 to 5); +trg_group1(6 to 10) <= inval_dbg_seq_q(0 to 4); +trg_group1(11) <= tlb_ctl_dbg_seq_any_done_sig or tlb_ctl_dbg_seq_abort or inval_dbg_seq_snoop_done or inval_dbg_seq_local_done or inval_dbg_seq_tlb0fi_done or inval_dbg_seq_tlbwe_snoop_done; + + +-- trigger group2 +trg_group2(0) <= tlb_req_dbg_ierat_iu5_valid_q; +trg_group2(1) <= tlb_req_dbg_derat_ex6_valid_q; +trg_group2(2) <= tlb_ctl_dbg_any_tlb_req_sig; +trg_group2(3) <= tlb_ctl_dbg_any_req_taken_sig; +trg_group2(4) <= tlb_ctl_dbg_seq_any_done_sig or tlb_ctl_dbg_seq_abort; +trg_group2(5) <= inval_dbg_ex6_valid; ----------------> need tlbivax/erativax indication? +trg_group2(6) <= mmucsr0_tlb0fi; +trg_group2(7) <= inval_dbg_snoop_forme; +trg_group2(8) <= tlbwe_back_inv_valid; +trg_group2(9) <= htw_lsu_req_valid; +trg_group2(10) <= inval_dbg_seq_snoop_done or inval_dbg_seq_local_done or inval_dbg_seq_tlb0fi_done or inval_dbg_seq_tlbwe_snoop_done; +trg_group2(11) <= or_reduce(mm_xu_lsu_req); + + +-- trigger group3 +trg_group3a(0) <= spr_dbg_slowspr_val_int; +trg_group3a(1) <= spr_dbg_slowspr_rw_int; +trg_group3a(2 to 3) <= spr_dbg_slowspr_etid_int; +trg_group3a(4) <= spr_dbg_match_64b; +trg_group3a(5) <= spr_dbg_match_any_mmu; -- int phase +trg_group3a(6) <= spr_dbg_match_any_mas; +trg_group3a(7) <= spr_dbg_match_mmucr0 or spr_dbg_match_mmucr1 or spr_dbg_match_mmucr2 or spr_dbg_match_mmucr3; +trg_group3a(8) <= spr_dbg_match_pid or spr_dbg_match_lpidr; +trg_group3a(9) <= spr_dbg_match_lper or spr_dbg_match_lperu; +trg_group3a(10) <= spr_dbg_slowspr_val_out; +trg_group3a(11) <= spr_dbg_slowspr_done_out; + +trg_group3b(0) <= tlb_htw_req_valid; +trg_group3b(1 to 2) <= htw_dbg_seq_q(0 to 1); +trg_group3b(3 to 5) <= htw_dbg_pte0_seq_q(0 to 2); +trg_group3b(6 to 8) <= htw_dbg_pte1_seq_q(0 to 2); +trg_group3b(9) <= htw_dbg_pte0_reld_for_me_tm1 or htw_dbg_pte1_reld_for_me_tm1; +trg_group3b(10) <= or_reduce(htw_dbg_pte0_score_error_q or htw_dbg_pte1_score_error_q); +trg_group3b(11) <= tlb_cmp_dbg_tag5_any_exception; + +trg_group3 <= trg_group3b when mmucr2(11)='1' else trg_group3a; + + + +dbg_mux0: entity clib.c_debug_mux16 + port map( + vd => vdd, + gd => gnd, + + select_bits => pc_mm_debug_mux1_ctrls_loc_q, + trace_data_in => debug_bus_in_q, + trigger_data_in => trace_triggers_in_q, + + dbg_group0 => dbg_group0, + dbg_group1 => dbg_group1, + dbg_group2 => dbg_group2, + dbg_group3 => dbg_group3, + dbg_group4 => dbg_group4, + dbg_group5 => dbg_group5, + dbg_group6 => dbg_group6, + dbg_group7 => dbg_group7, + dbg_group8 => dbg_group8, + dbg_group9 => dbg_group9, + dbg_group10 => dbg_group10, + dbg_group11 => dbg_group11, + dbg_group12 => dbg_group12, + dbg_group13 => dbg_group13, + dbg_group14 => dbg_group14, + dbg_group15 => dbg_group15, + + trg_group0 => trg_group0, + trg_group1 => trg_group1, + trg_group2 => trg_group2, + trg_group3 => trg_group3, + + trace_data_out => trace_data_out_d, + trigger_data_out => trigger_data_out_d +); + +trace_triggers_out <= trigger_data_out_q; +debug_bus_out <= trace_data_out_q; +debug_bus_out_int <= trace_data_out_int_q; + + +-- unused spare signal assignments +unused_dc(0) <= TLB_MAS_THDID(0); +unused_dc(1) <= LRAT_MAS_THDID(0); +unused_dc(2) <= LRAT_MAS_THDID(0); +unused_dc(3) <= INVAL_DBG_LSU_TOKENS_Q(0); +unused_dc(4) <= TLB_CMP_DBG_TAG4(82); -- tagpos_derat, not used for type encoding of '0' +unused_dc(5) <= TLB_CMP_DBG_TAG4(106); -- tagpos_lrat + +unused_dc(6) <= or_reduce(TLB_CMP_DBG_TAG4(0 TO 7)); -- tagpos_epn +unused_dc(7) <= or_reduce(TLB_CMP_DBG_TAG4(8 TO 15)); +unused_dc(8) <= TLB_CMP_DBG_TAG5_WAYHIT(4); + +unused_dc(9) <= DEBUG_Q(23); +unused_dc(10) <= or_reduce(TRIGGER_Q(0 to 47)); +unused_dc(11) <= tlb_cmp_dbg_tag5_lru_dataout(7); -- lru parity bit + + +----------------------------------------------------------------------- +-- Latches +----------------------------------------------------------------------- + +trace_bus_enable_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => pc_func_slp_sl_force, + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + scin => siv(trace_bus_enable_offset), + scout => sov(trace_bus_enable_offset), + din => pc_mm_trace_bus_enable, + dout => pc_mm_trace_bus_enable_q); +debug_mux1_ctrls_latch : tri_rlmreg_p + generic map (width => pc_mm_debug_mux1_ctrls_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => pc_mm_trace_bus_enable_q, + forcee => pc_func_slp_sl_force, + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + scin => siv(debug_mux1_ctrls_offset to debug_mux1_ctrls_offset + pc_mm_debug_mux1_ctrls_q'length-1), + scout => sov(debug_mux1_ctrls_offset to debug_mux1_ctrls_offset + pc_mm_debug_mux1_ctrls_q'length-1), + din => pc_mm_debug_mux1_ctrls, + dout => pc_mm_debug_mux1_ctrls_q); +debug_mux1_ctrls_loc_latch : tri_rlmreg_p + generic map (width => pc_mm_debug_mux1_ctrls_loc_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => pc_mm_trace_bus_enable_q, + forcee => pc_func_slp_sl_force, + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + scin => siv(debug_mux1_ctrls_loc_offset to debug_mux1_ctrls_loc_offset + pc_mm_debug_mux1_ctrls_loc_q'length-1), + scout => sov(debug_mux1_ctrls_loc_offset to debug_mux1_ctrls_loc_offset + pc_mm_debug_mux1_ctrls_loc_q'length-1), + din => pc_mm_debug_mux1_ctrls_loc_d, + dout => pc_mm_debug_mux1_ctrls_loc_q); +trigger_data_latch: tri_rlmreg_p + generic map (width => trigger_data_out_q'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => pc_mm_trace_bus_enable_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(trigger_data_out_offset to trigger_data_out_offset + trigger_data_out_q'length-1), + scout => sov(trigger_data_out_offset to trigger_data_out_offset + trigger_data_out_q'length-1), + din => trigger_data_out_d, + dout => trigger_data_out_q); + +trace_data_out_latch: tri_rlmreg_p + generic map (width => trace_data_out_q'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => pc_mm_trace_bus_enable_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(trace_data_out_offset to trace_data_out_offset + trace_data_out_q'length-1), + scout => sov(trace_data_out_offset to trace_data_out_offset + trace_data_out_q'length-1), + din => trace_data_out_d, + dout => trace_data_out_q); + +trace_data_out_int_latch: tri_rlmreg_p + generic map (width => trace_data_out_int_q'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => pc_mm_trace_bus_enable_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(trace_data_out_int_offset to trace_data_out_int_offset + trace_data_out_int_q'length-1), + scout => sov(trace_data_out_int_offset to trace_data_out_int_offset + trace_data_out_int_q'length-1), + din => trace_data_out_d(0 to 7), + dout => trace_data_out_int_q); + +debug_latch : tri_regk + generic map (width => debug_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => pc_mm_trace_bus_enable_q, + forcee => pc_func_slp_nsl_force, + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_nsl_thold_0_b, + din => debug_d, + dout => debug_q); + +trigger_latch : tri_regk + generic map (width => trigger_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => pc_mm_trace_bus_enable_q, + forcee => pc_func_slp_nsl_force, + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_nsl_thold_0_b, + din => trigger_d, + dout => trigger_q); + + +debug_bus_in_latch : tri_regk + generic map (width => debug_bus_in_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => pc_mm_trace_bus_enable_q, + forcee => pc_func_slp_nsl_force, + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_nsl_thold_0_b, + din => debug_bus_in, + dout => debug_bus_in_q); + +trace_triggers_in_latch : tri_regk + generic map (width => trace_triggers_in_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => pc_mm_trace_bus_enable_q, + forcee => pc_func_slp_nsl_force, + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_nsl_thold_0_b, + din => trace_triggers_in, + dout => trace_triggers_in_q); + +------------------------------------------------- +-- pervasive +------------------------------------------------- + +perv_2to1_plat: tri_plat + generic map (width => 4, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_func_slp_sl_thold_2, + din(1) => pc_func_slp_nsl_thold_2, + din(2) => pc_sg_2, + din(3) => pc_fce_2, + q(0) => pc_func_slp_sl_thold_1, + q(1) => pc_func_slp_nsl_thold_1, + q(2) => pc_sg_1, + q(3) => pc_fce_1); + +perv_1to0_plat: tri_plat + generic map (width => 4, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_func_slp_sl_thold_1, + din(1) => pc_func_slp_nsl_thold_1, + din(2) => pc_sg_1, + din(3) => pc_fce_1, + q(0) => pc_func_slp_sl_thold_0, + q(1) => pc_func_slp_nsl_thold_0, + q(2) => pc_sg_0, + q(3) => pc_fce_0); + +perv_sl_lcbor: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b, + thold => pc_func_slp_sl_thold_0, + sg => pc_sg_0, + act_dis => lcb_act_dis_dc, + forcee => pc_func_slp_sl_force, + thold_b => pc_func_slp_sl_thold_0_b); + +perv_nsl_lcbor: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b, + thold => pc_func_slp_nsl_thold_0, + sg => pc_fce_0, + act_dis => tidn, + forcee => pc_func_slp_nsl_force, + thold_b => pc_func_slp_nsl_thold_0_b); + +----------------------------------------------------------------------- +-- Scan +----------------------------------------------------------------------- +siv(0 to scan_right) <= sov(1 to scan_right) & scan_in; +scan_out <= sov(0); + + +end mmq_dbg; diff --git a/rel/src/vhdl/work/mmq_htw.vhdl b/rel/src/vhdl/work/mmq_htw.vhdl new file mode 100644 index 0000000..2211174 --- /dev/null +++ b/rel/src/vhdl/work/mmq_htw.vhdl @@ -0,0 +1,2780 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; +use ieee.std_logic_1164.all; +library ibm; +use ibm.std_ulogic_unsigned.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_support.all; +library support; +use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity mmq_htw is + generic(thdid_width : integer := 4; + pid_width : integer := 14; + lpid_width : integer := 8; + htw_seq_width : integer := 2; + pte_seq_width : integer := 3; + tlb_way_width : natural := 168; + tlb_word_width : natural := 84; + real_addr_width : integer := 42; + epn_width : integer := 52; + rpn_width : integer := 30; + pte_width : integer := 64; + tlb_tag_width : natural := 110; + expand_type : integer := 2 ); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + +tc_ccflush_dc : in std_ulogic; +tc_scan_dis_dc_b : in std_ulogic; +tc_scan_diag_dc : in std_ulogic; +tc_lbist_en_dc : in std_ulogic; +lcb_d_mode_dc : in std_ulogic; +lcb_clkoff_dc_b : in std_ulogic; +lcb_act_dis_dc : in std_ulogic; +lcb_mpw1_dc_b : in std_ulogic_vector(0 to 4); +lcb_mpw2_dc_b : in std_ulogic; +lcb_delay_lclkr_dc : in std_ulogic_vector(0 to 4); +ac_func_scan_in :in std_ulogic_vector(0 to 1); +ac_func_scan_out :out std_ulogic_vector(0 to 1); +pc_sg_2 : in std_ulogic; +pc_func_sl_thold_2 : in std_ulogic; +pc_func_slp_sl_thold_2 : in std_ulogic; +xu_mm_ccr2_notlb_b : in std_ulogic; +mmucr2_act_override : in std_ulogic; +tlb_delayed_act : in std_ulogic_vector(24 to 28); +tlb_ctl_tag2_flush : in std_ulogic_vector(0 to thdid_width-1); +tlb_ctl_tag3_flush : in std_ulogic_vector(0 to thdid_width-1); +tlb_ctl_tag4_flush : in std_ulogic_vector(0 to thdid_width-1); +tlb_tag2 : in std_ulogic_vector(0 to tlb_tag_width-1); +tlb_tag5_except : in std_ulogic_vector(0 to thdid_width-1); +tlb_htw_req_valid : in std_ulogic; +tlb_htw_req_tag : in std_ulogic_vector(0 to tlb_tag_width-1); +tlb_htw_req_way : in std_ulogic_vector(tlb_word_width to tlb_way_width-1); +htw_lsu_req_valid : out std_ulogic; +htw_lsu_thdid : out std_ulogic_vector(0 to thdid_width-1); +htw_dbg_lsu_thdid : out std_ulogic_vector(0 to 1); +htw_lsu_ttype : out std_ulogic_vector(0 to 1); +htw_lsu_wimge : out std_ulogic_vector(0 to 4); +htw_lsu_u : out std_ulogic_vector(0 to 3); +htw_lsu_addr : out std_ulogic_vector(64-real_addr_width to 63); +htw_lsu_req_taken : in std_ulogic; +htw_quiesce : out std_ulogic_vector(0 to thdid_width-1); +htw_req0_valid : out std_ulogic; +htw_req0_thdid : out std_ulogic_vector(0 to thdid_width-1); +htw_req0_type : out std_ulogic_vector(0 to 1); +htw_req1_valid : out std_ulogic; +htw_req1_thdid : out std_ulogic_vector(0 to thdid_width-1); +htw_req1_type : out std_ulogic_vector(0 to 1); +htw_req2_valid : out std_ulogic; +htw_req2_thdid : out std_ulogic_vector(0 to thdid_width-1); +htw_req2_type : out std_ulogic_vector(0 to 1); +htw_req3_valid : out std_ulogic; +htw_req3_thdid : out std_ulogic_vector(0 to thdid_width-1); +htw_req3_type : out std_ulogic_vector(0 to 1); +ptereload_req_valid : out std_ulogic; +ptereload_req_tag : out std_ulogic_vector(0 to tlb_tag_width-1); +ptereload_req_pte : out std_ulogic_vector(0 to pte_width-1); +ptereload_req_taken : in std_ulogic; +an_ac_reld_core_tag : in std_ulogic_vector(0 to 4); +an_ac_reld_data : in std_ulogic_vector(0 to 127); +an_ac_reld_data_vld : in std_ulogic; +an_ac_reld_ecc_err : in std_ulogic; +an_ac_reld_ecc_err_ue : in std_ulogic; +an_ac_reld_qw : in std_ulogic_vector(58 to 59); +an_ac_reld_ditc : in std_ulogic; +an_ac_reld_crit_qw : in std_ulogic; +htw_dbg_seq_idle : out std_ulogic; +htw_dbg_pte0_seq_idle : out std_ulogic; +htw_dbg_pte1_seq_idle : out std_ulogic; +htw_dbg_seq_q : out std_ulogic_vector(0 to 1); +htw_dbg_inptr_q : out std_ulogic_vector(0 to 1); +htw_dbg_pte0_seq_q : out std_ulogic_vector(0 to 2); +htw_dbg_pte1_seq_q : out std_ulogic_vector(0 to 2); +htw_dbg_ptereload_ptr_q : out std_ulogic; +htw_dbg_lsuptr_q : out std_ulogic_vector(0 to 1); +htw_dbg_req_valid_q : out std_ulogic_vector(0 to 3); +htw_dbg_resv_valid_vec : out std_ulogic_vector(0 to 3); +htw_dbg_tag4_clr_resv_q : out std_ulogic_vector(0 to 3); +htw_dbg_tag4_clr_resv_terms : out std_ulogic_vector(0 to 3); +htw_dbg_pte0_score_ptr_q : out std_ulogic_vector(0 to 1); +htw_dbg_pte0_score_cl_offset_q : out std_ulogic_vector(58 to 60); +htw_dbg_pte0_score_error_q : out std_ulogic_vector(0 to 2); +htw_dbg_pte0_score_qwbeat_q : out std_ulogic_vector(0 to 3); +htw_dbg_pte0_score_pending_q : out std_ulogic; +htw_dbg_pte0_score_ibit_q : out std_ulogic; +htw_dbg_pte0_score_dataval_q : out std_ulogic; +htw_dbg_pte0_reld_for_me_tm1 : out std_ulogic; +htw_dbg_pte1_score_ptr_q : out std_ulogic_vector(0 to 1); +htw_dbg_pte1_score_cl_offset_q : out std_ulogic_vector(58 to 60); +htw_dbg_pte1_score_error_q : out std_ulogic_vector(0 to 2); +htw_dbg_pte1_score_qwbeat_q : out std_ulogic_vector(0 to 3); +htw_dbg_pte1_score_pending_q : out std_ulogic; +htw_dbg_pte1_score_ibit_q : out std_ulogic; +htw_dbg_pte1_score_dataval_q : out std_ulogic; +htw_dbg_pte1_reld_for_me_tm1 : out std_ulogic + +); +end mmq_htw; +ARCHITECTURE MMQ_HTW + OF MMQ_HTW + IS +constant MMU_Mode_Value : std_ulogic := '0'; +constant TlbSel_Tlb : std_ulogic_vector(0 to 1) := "00"; +constant TlbSel_IErat : std_ulogic_vector(0 to 1) := "10"; +constant TlbSel_DErat : std_ulogic_vector(0 to 1) := "11"; +constant Core_Tag0_Value : std_ulogic_vector(0 to 4) := "01100"; +constant Core_Tag1_Value : std_ulogic_vector(0 to 4) := "01101"; +constant ERAT_PgSize_1GB : std_ulogic_vector(0 to 2) := "110"; +constant ERAT_PgSize_16MB : std_ulogic_vector(0 to 2) := "111"; +constant ERAT_PgSize_1MB : std_ulogic_vector(0 to 2) := "101"; +constant ERAT_PgSize_64KB : std_ulogic_vector(0 to 2) := "011"; +constant ERAT_PgSize_4KB : std_ulogic_vector(0 to 2) := "001"; +constant TLB_PgSize_1GB : std_ulogic_vector(0 to 3) := "1010"; +constant TLB_PgSize_16MB : std_ulogic_vector(0 to 3) := "0111"; +constant TLB_PgSize_1MB : std_ulogic_vector(0 to 3) := "0101"; +constant TLB_PgSize_64KB : std_ulogic_vector(0 to 3) := "0011"; +constant TLB_PgSize_4KB : std_ulogic_vector(0 to 3) := "0001"; +-- reserved for indirect entries +constant ERAT_PgSize_256MB : std_ulogic_vector(0 to 2) := "100"; +constant TLB_PgSize_256MB : std_ulogic_vector(0 to 3) := "1001"; +constant HtwSeq_Idle : std_ulogic_vector(0 to 1) := "00"; +constant HtwSeq_Stg1 : std_ulogic_vector(0 to 1) := "01"; +constant HtwSeq_Stg2 : std_ulogic_vector(0 to 1) := "11"; +constant HtwSeq_Stg3 : std_ulogic_vector(0 to 1) := "10"; +constant PteSeq_Idle : std_ulogic_vector(0 to 2) := "000"; +constant PteSeq_Stg1 : std_ulogic_vector(0 to 2) := "001"; +constant PteSeq_Stg2 : std_ulogic_vector(0 to 2) := "011"; +constant PteSeq_Stg3 : std_ulogic_vector(0 to 2) := "010"; +constant PteSeq_Stg4 : std_ulogic_vector(0 to 2) := "110"; +constant PteSeq_Stg5 : std_ulogic_vector(0 to 2) := "111"; +constant PteSeq_Stg6 : std_ulogic_vector(0 to 2) := "101"; +constant PteSeq_Stg7 : std_ulogic_vector(0 to 2) := "100"; +constant tlb_htw_req0_valid_offset : natural := 0; +constant tlb_htw_req0_pending_offset : natural := tlb_htw_req0_valid_offset + 1; +constant tlb_htw_req0_tag_offset : natural := tlb_htw_req0_pending_offset + 1; +constant tlb_htw_req0_way_offset : natural := tlb_htw_req0_tag_offset + tlb_tag_width; +constant tlb_htw_req1_valid_offset : natural := tlb_htw_req0_way_offset + tlb_word_width; +constant tlb_htw_req1_pending_offset : natural := tlb_htw_req1_valid_offset + 1; +constant tlb_htw_req1_tag_offset : natural := tlb_htw_req1_pending_offset + 1; +constant tlb_htw_req1_way_offset : natural := tlb_htw_req1_tag_offset + tlb_tag_width; +constant tlb_htw_req2_valid_offset : natural := tlb_htw_req1_way_offset + tlb_word_width; +constant tlb_htw_req2_pending_offset : natural := tlb_htw_req2_valid_offset + 1; +constant tlb_htw_req2_tag_offset : natural := tlb_htw_req2_pending_offset + 1; +constant tlb_htw_req2_way_offset : natural := tlb_htw_req2_tag_offset + tlb_tag_width; +constant tlb_htw_req3_valid_offset : natural := tlb_htw_req2_way_offset + tlb_word_width; +constant tlb_htw_req3_pending_offset : natural := tlb_htw_req3_valid_offset + 1; +constant tlb_htw_req3_tag_offset : natural := tlb_htw_req3_pending_offset + 1; +constant tlb_htw_req3_way_offset : natural := tlb_htw_req3_tag_offset + tlb_tag_width; +constant spare_a_offset : natural := tlb_htw_req3_way_offset + tlb_word_width; +constant scan_right_0 : natural := spare_a_offset + 16 -1; +constant htw_seq_offset : natural := 0; +constant htw_inptr_offset : natural := htw_seq_offset + htw_seq_width; +constant htw_lsuptr_offset : natural := htw_inptr_offset + 2; +constant htw_lsu_ttype_offset : natural := htw_lsuptr_offset + 2; +constant htw_lsu_thdid_offset : natural := htw_lsu_ttype_offset + 2; +constant htw_lsu_wimge_offset : natural := htw_lsu_thdid_offset + thdid_width; +constant htw_lsu_u_offset : natural := htw_lsu_wimge_offset + 5; +constant htw_lsu_addr_offset : natural := htw_lsu_u_offset + 4; +constant pte0_seq_offset : natural := htw_lsu_addr_offset + real_addr_width; +constant pte0_score_ptr_offset : natural := pte0_seq_offset + pte_seq_width; +constant pte0_score_cl_offset_offset : natural := pte0_score_ptr_offset + 2; +constant pte0_score_error_offset : natural := pte0_score_cl_offset_offset + 3; +constant pte0_score_qwbeat_offset : natural := pte0_score_error_offset + 3; +constant pte0_score_ibit_offset : natural := pte0_score_qwbeat_offset + 4; +constant pte0_score_pending_offset : natural := pte0_score_ibit_offset + 1; +constant pte0_score_dataval_offset : natural := pte0_score_pending_offset + 1; +constant pte1_seq_offset : natural := pte0_score_dataval_offset + 1; +constant pte1_score_ptr_offset : natural := pte1_seq_offset + pte_seq_width; +constant pte1_score_cl_offset_offset : natural := pte1_score_ptr_offset + 2; +constant pte1_score_error_offset : natural := pte1_score_cl_offset_offset + 3; +constant pte1_score_qwbeat_offset : natural := pte1_score_error_offset + 3; +constant pte1_score_ibit_offset : natural := pte1_score_qwbeat_offset + 4; +constant pte1_score_pending_offset : natural := pte1_score_ibit_offset + 1; +constant pte1_score_dataval_offset : natural := pte1_score_pending_offset + 1; +constant pte_load_ptr_offset : natural := pte1_score_dataval_offset + 1; +constant ptereload_ptr_offset : natural := pte_load_ptr_offset + 1; +-- ptereload_ptr_offset + 1 phase +constant reld_core_tag_tm1_offset : natural := ptereload_ptr_offset + 1; +constant reld_qw_tm1_offset : natural := reld_core_tag_tm1_offset + 5; +constant reld_crit_qw_tm1_offset : natural := reld_qw_tm1_offset + 2; +constant reld_ditc_tm1_offset : natural := reld_crit_qw_tm1_offset + 1; +constant reld_data_vld_tm1_offset : natural := reld_ditc_tm1_offset + 1; +-- reld_data_vld_tm1_offset + 1 phase +constant reld_core_tag_t_offset : natural := reld_data_vld_tm1_offset + 1; +constant reld_qw_t_offset : natural := reld_core_tag_t_offset + 5; +constant reld_crit_qw_t_offset : natural := reld_qw_t_offset + 2; +constant reld_ditc_t_offset : natural := reld_crit_qw_t_offset + 1; +constant reld_data_vld_t_offset : natural := reld_ditc_t_offset + 1; +-- reld_data_vld_t_offset + 1 phase +constant reld_core_tag_tp1_offset : natural := reld_data_vld_t_offset + 1; +constant reld_qw_tp1_offset : natural := reld_core_tag_tp1_offset + 5; +constant reld_crit_qw_tp1_offset : natural := reld_qw_tp1_offset + 2; +constant reld_ditc_tp1_offset : natural := reld_crit_qw_tp1_offset + 1; +constant reld_data_vld_tp1_offset : natural := reld_ditc_tp1_offset + 1; +-- reld_data_vld_tp1_offset + 1 phase +constant reld_core_tag_tp2_offset : natural := reld_data_vld_tp1_offset + 1; +constant reld_qw_tp2_offset : natural := reld_core_tag_tp2_offset + 5; +constant reld_crit_qw_tp2_offset : natural := reld_qw_tp2_offset + 2; +constant reld_ditc_tp2_offset : natural := reld_crit_qw_tp2_offset + 1; +constant reld_data_vld_tp2_offset : natural := reld_ditc_tp2_offset + 1; +constant reld_ecc_err_tp2_offset : natural := reld_data_vld_tp2_offset + 1; +constant reld_ecc_err_ue_tp2_offset : natural := reld_ecc_err_tp2_offset + 1; +constant reld_data_tp1_offset : natural := reld_ecc_err_ue_tp2_offset + 1; +constant reld_data_tp2_offset : natural := reld_data_tp1_offset + 128; +constant pte0_reld_data_tp3_offset : natural := reld_data_tp2_offset + 128; +constant pte1_reld_data_tp3_offset : natural := pte0_reld_data_tp3_offset + 64; +constant htw_tag3_offset : natural := pte1_reld_data_tp3_offset + 64; +constant htw_tag4_clr_resv_offset : natural := htw_tag3_offset + tlb_tag_width; +constant htw_tag5_clr_resv_offset : natural := htw_tag4_clr_resv_offset + thdid_width; +constant spare_b_offset : natural := htw_tag5_clr_resv_offset + thdid_width; +constant scan_right_1 : natural := spare_b_offset + 16 -1; +constant tagpos_epn : natural := 0; +constant tagpos_pid : natural := 52; +constant tagpos_is : natural := 66; +constant tagpos_class : natural := 68; +constant tagpos_state : natural := 70; +constant tagpos_thdid : natural := 74; +constant tagpos_size : natural := 78; +constant tagpos_type : natural := 82; +constant tagpos_lpid : natural := 90; +constant tagpos_ind : natural := 98; +constant tagpos_atsel : natural := 99; +constant tagpos_esel : natural := 100; +constant tagpos_hes : natural := 103; +constant tagpos_wq : natural := 104; +constant tagpos_ltwe : natural := 106; +constant tagpos_lpte : natural := 107; +constant tagpos_recform : natural := 108; +constant tagpos_endflag : natural := 109; +-- derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload +constant tagpos_type_derat : natural := tagpos_type; +constant tagpos_type_ierat : natural := tagpos_type+1; +constant tagpos_type_tlbsx : natural := tagpos_type+2; +constant tagpos_type_tlbsrx : natural := tagpos_type+3; +constant tagpos_type_snoop : natural := tagpos_type+4; +constant tagpos_type_tlbre : natural := tagpos_type+5; +constant tagpos_type_tlbwe : natural := tagpos_type+6; +constant tagpos_type_ptereload : natural := tagpos_type+7; +-- state: 0:pr 1:gs 2:as 3:cm +constant tagpos_pr : natural := tagpos_state; +constant tagpos_gs : natural := tagpos_state+1; +constant tagpos_as : natural := tagpos_state+2; +constant tagpos_cm : natural := tagpos_state+3; +constant waypos_epn : natural := 0; +constant waypos_size : natural := 52; +constant waypos_thdid : natural := 56; +constant waypos_class : natural := 60; +constant waypos_extclass : natural := 62; +constant waypos_lpid : natural := 66; +constant waypos_xbit : natural := 84; +constant waypos_rpn : natural := 88; +constant waypos_rc : natural := 118; +constant waypos_wlc : natural := 120; +constant waypos_resvattr : natural := 122; +constant waypos_vf : natural := 123; +constant waypos_ind : natural := 124; +constant waypos_ubits : natural := 125; +constant waypos_wimge : natural := 129; +constant waypos_usxwr : natural := 134; +constant waypos_gs : natural := 140; +constant waypos_ts : natural := 141; +constant waypos_tid : natural := 144; +constant ptepos_rpn : natural := 0; +constant ptepos_wimge : natural := 40; +constant ptepos_r : natural := 45; +constant ptepos_ubits : natural := 46; +constant ptepos_sw0 : natural := 50; +constant ptepos_c : natural := 51; +constant ptepos_size : natural := 52; +constant ptepos_usxwr : natural := 56; +constant ptepos_sw1 : natural := 62; +constant ptepos_valid : natural := 63; +-- Latch signals +signal htw_seq_d, htw_seq_q : std_ulogic_vector(0 to 1); +signal htw_inptr_d, htw_inptr_q : std_ulogic_vector(0 to 1); +signal htw_lsuptr_d, htw_lsuptr_q : std_ulogic_vector(0 to 1); +signal htw_lsu_ttype_d, htw_lsu_ttype_q : std_ulogic_vector(0 to 1); +signal htw_lsu_thdid_d, htw_lsu_thdid_q : std_ulogic_vector(0 to thdid_width-1); +signal htw_lsu_wimge_d, htw_lsu_wimge_q : std_ulogic_vector(0 to 4); +signal htw_lsu_u_d, htw_lsu_u_q : std_ulogic_vector(0 to 3); +signal htw_lsu_addr_d, htw_lsu_addr_q : std_ulogic_vector(64-real_addr_width to 63); +signal pte0_seq_d, pte0_seq_q : std_ulogic_vector(0 to 2); +signal pte0_score_ptr_d, pte0_score_ptr_q : std_ulogic_vector(0 to 1); +signal pte0_score_cl_offset_d, pte0_score_cl_offset_q : std_ulogic_vector(58 to 60); +signal pte0_score_error_d, pte0_score_error_q : std_ulogic_vector(0 to 2); +signal pte0_score_qwbeat_d, pte0_score_qwbeat_q : std_ulogic_vector(0 to 3); +signal pte0_score_pending_d, pte0_score_pending_q : std_ulogic; +signal pte0_score_ibit_d, pte0_score_ibit_q : std_ulogic; +signal pte0_score_dataval_d, pte0_score_dataval_q : std_ulogic; +signal pte1_seq_d, pte1_seq_q : std_ulogic_vector(0 to 2); +signal pte1_score_ptr_d, pte1_score_ptr_q : std_ulogic_vector(0 to 1); +signal pte1_score_cl_offset_d, pte1_score_cl_offset_q : std_ulogic_vector(58 to 60); +signal pte1_score_error_d, pte1_score_error_q : std_ulogic_vector(0 to 2); +signal pte1_score_qwbeat_d, pte1_score_qwbeat_q : std_ulogic_vector(0 to 3); +signal pte1_score_pending_d, pte1_score_pending_q : std_ulogic; +signal pte1_score_ibit_d, pte1_score_ibit_q : std_ulogic; +signal pte1_score_dataval_d, pte1_score_dataval_q : std_ulogic; +signal ptereload_ptr_d, ptereload_ptr_q : std_ulogic; +signal pte_load_ptr_d, pte_load_ptr_q : std_ulogic; +signal tlb_htw_req0_valid_d, tlb_htw_req0_valid_q : std_ulogic; +signal tlb_htw_req0_pending_d, tlb_htw_req0_pending_q : std_ulogic; +signal tlb_htw_req0_tag_d, tlb_htw_req0_tag_q : std_ulogic_vector(0 to tlb_tag_width-1); +signal tlb_htw_req0_way_d, tlb_htw_req0_way_q : std_ulogic_vector(tlb_word_width to tlb_way_width-1); +signal tlb_htw_req0_tag_act : std_ulogic; +signal tlb_htw_req1_valid_d, tlb_htw_req1_valid_q : std_ulogic; +signal tlb_htw_req1_pending_d, tlb_htw_req1_pending_q : std_ulogic; +signal tlb_htw_req1_tag_d, tlb_htw_req1_tag_q : std_ulogic_vector(0 to tlb_tag_width-1); +signal tlb_htw_req1_way_d, tlb_htw_req1_way_q : std_ulogic_vector(tlb_word_width to tlb_way_width-1); +signal tlb_htw_req1_tag_act : std_ulogic; +signal tlb_htw_req2_valid_d, tlb_htw_req2_valid_q : std_ulogic; +signal tlb_htw_req2_pending_d, tlb_htw_req2_pending_q : std_ulogic; +signal tlb_htw_req2_tag_d, tlb_htw_req2_tag_q : std_ulogic_vector(0 to tlb_tag_width-1); +signal tlb_htw_req2_way_d, tlb_htw_req2_way_q : std_ulogic_vector(tlb_word_width to tlb_way_width-1); +signal tlb_htw_req2_tag_act : std_ulogic; +signal tlb_htw_req3_valid_d, tlb_htw_req3_valid_q : std_ulogic; +signal tlb_htw_req3_pending_d, tlb_htw_req3_pending_q : std_ulogic; +signal tlb_htw_req3_tag_d, tlb_htw_req3_tag_q : std_ulogic_vector(0 to tlb_tag_width-1); +signal tlb_htw_req3_way_d, tlb_htw_req3_way_q : std_ulogic_vector(tlb_word_width to tlb_way_width-1); +signal tlb_htw_req3_tag_act : std_ulogic; +-- synopsys translate_off +-- synopsys translate_on +-- t minus 1 phase +signal reld_core_tag_tm1_d, reld_core_tag_tm1_q : std_ulogic_vector(0 to 4); +signal reld_qw_tm1_d, reld_qw_tm1_q : std_ulogic_vector(0 to 1); +signal reld_crit_qw_tm1_d, reld_crit_qw_tm1_q : std_ulogic; +signal reld_ditc_tm1_d, reld_ditc_tm1_q : std_ulogic; +signal reld_data_vld_tm1_d, reld_data_vld_tm1_q : std_ulogic; +-- t phase +signal reld_core_tag_t_d, reld_core_tag_t_q : std_ulogic_vector(0 to 4); +signal reld_qw_t_d, reld_qw_t_q : std_ulogic_vector(0 to 1); +signal reld_crit_qw_t_d, reld_crit_qw_t_q : std_ulogic; +signal reld_ditc_t_d, reld_ditc_t_q : std_ulogic; +signal reld_data_vld_t_d, reld_data_vld_t_q : std_ulogic; +-- t plus 1 phase +signal reld_core_tag_tp1_d, reld_core_tag_tp1_q : std_ulogic_vector(0 to 4); +signal reld_qw_tp1_d, reld_qw_tp1_q : std_ulogic_vector(0 to 1); +signal reld_crit_qw_tp1_d, reld_crit_qw_tp1_q : std_ulogic; +signal reld_ditc_tp1_d, reld_ditc_tp1_q : std_ulogic; +signal reld_data_vld_tp1_d, reld_data_vld_tp1_q : std_ulogic; +signal reld_data_tp1_d, reld_data_tp1_q : std_ulogic_vector(0 to 127); +-- t plus 2 phase +signal reld_core_tag_tp2_d, reld_core_tag_tp2_q : std_ulogic_vector(0 to 4); +signal reld_qw_tp2_d, reld_qw_tp2_q : std_ulogic_vector(0 to 1); +signal reld_crit_qw_tp2_d, reld_crit_qw_tp2_q : std_ulogic; +signal reld_ditc_tp2_d, reld_ditc_tp2_q : std_ulogic; +signal reld_data_vld_tp2_d, reld_data_vld_tp2_q : std_ulogic; +signal reld_data_tp2_d, reld_data_tp2_q : std_ulogic_vector(0 to 127); +signal reld_ecc_err_tp2_d, reld_ecc_err_tp2_q : std_ulogic; +signal reld_ecc_err_ue_tp2_d, reld_ecc_err_ue_tp2_q : std_ulogic; +-- t plus 3 phase +signal pte0_reld_data_tp3_d, pte0_reld_data_tp3_q : std_ulogic_vector(0 to 63); +signal pte1_reld_data_tp3_d, pte1_reld_data_tp3_q : std_ulogic_vector(0 to 63); +signal htw_tag3_d, htw_tag3_q : std_ulogic_vector(0 to tlb_tag_width-1); +signal htw_tag3_clr_resv_term2, htw_tag3_clr_resv_term4, htw_tag3_clr_resv_term5, htw_tag3_clr_resv_term6 : std_ulogic_vector(0 to thdid_width-1); +signal htw_tag3_clr_resv_term7, htw_tag3_clr_resv_term8, htw_tag3_clr_resv_term9, htw_tag3_clr_resv_term11 : std_ulogic_vector(0 to thdid_width-1); +signal htw_tag4_clr_resv_d, htw_tag4_clr_resv_q : std_ulogic_vector(0 to thdid_width-1); +signal htw_tag5_clr_resv_d, htw_tag5_clr_resv_q : std_ulogic_vector(0 to thdid_width-1); +signal spare_a_q, spare_b_q : std_ulogic_vector(0 to 15); +-- logic signals +signal htw_seq_idle : std_ulogic; +signal htw_seq_load_pteaddr : std_ulogic; +signal htw_quiesce_b : std_ulogic_vector(0 to thdid_width-1); +signal tlb_htw_req_valid_vec : std_ulogic_vector(0 to thdid_width-1); +signal tlb_htw_req_valid_notpend_vec : std_ulogic_vector(0 to thdid_width-1); +signal tlb_htw_pte_machines_full : std_ulogic; +signal htw_lsuptr_alt_d : std_ulogic_vector(0 to 1); +-- synopsys translate_off +-- synopsys translate_on +signal pte0_seq_idle : std_ulogic; +signal pte0_reload_req_valid : std_ulogic; +signal pte0_reload_req_taken : std_ulogic; +signal pte0_reld_for_me_tm1 : std_ulogic; +signal pte0_reld_for_me_tp2 : std_ulogic; +signal pte0_reld_enable_lo_tp2 : std_ulogic; +signal pte0_reld_enable_hi_tp2 : std_ulogic; +signal pte0_seq_score_load : std_ulogic; +signal pte0_seq_score_done : std_ulogic; +signal pte0_seq_data_retry : std_ulogic; +signal pte0_seq_clr_resv_ue : std_ulogic; +signal pte1_seq_idle : std_ulogic; +signal pte1_reload_req_valid : std_ulogic; +signal pte1_reload_req_taken : std_ulogic; +signal pte1_reld_for_me_tm1 : std_ulogic; +signal pte1_reld_for_me_tp2 : std_ulogic; +signal pte1_reld_enable_lo_tp2 : std_ulogic; +signal pte1_reld_enable_hi_tp2 : std_ulogic; +signal pte1_seq_score_load : std_ulogic; +signal pte1_seq_score_done : std_ulogic; +signal pte1_seq_data_retry : std_ulogic; +signal pte1_seq_clr_resv_ue : std_ulogic; +signal pte_ra_0 : std_ulogic_vector(64-real_addr_width to 63); +signal pte_ra_0_spsize4K : std_ulogic_vector(64-real_addr_width to 63); +signal pte_ra_0_spsize64K : std_ulogic_vector(64-real_addr_width to 63); +signal pte_ra_1 : std_ulogic_vector(64-real_addr_width to 63); +signal pte_ra_1_spsize4K : std_ulogic_vector(64-real_addr_width to 63); +signal pte_ra_1_spsize64K : std_ulogic_vector(64-real_addr_width to 63); +signal pte_ra_2 : std_ulogic_vector(64-real_addr_width to 63); +signal pte_ra_2_spsize4K : std_ulogic_vector(64-real_addr_width to 63); +signal pte_ra_2_spsize64K : std_ulogic_vector(64-real_addr_width to 63); +signal pte_ra_3 : std_ulogic_vector(64-real_addr_width to 63); +signal pte_ra_3_spsize4K : std_ulogic_vector(64-real_addr_width to 63); +signal pte_ra_3_spsize64K : std_ulogic_vector(64-real_addr_width to 63); +-- synopsys translate_off +-- synopsys translate_on +signal htw_resv0_tag3_lpid_match : std_ulogic; +signal htw_resv0_tag3_pid_match : std_ulogic; +signal htw_resv0_tag3_as_match : std_ulogic; +signal htw_resv0_tag3_gs_match : std_ulogic; +signal htw_resv0_tag3_epn_loc_match : std_ulogic; +signal htw_resv0_tag3_epn_glob_match : std_ulogic; +signal tlb_htw_req0_clr_resv_ue : std_ulogic; +signal htw_resv1_tag3_lpid_match : std_ulogic; +signal htw_resv1_tag3_pid_match : std_ulogic; +signal htw_resv1_tag3_as_match : std_ulogic; +signal htw_resv1_tag3_gs_match : std_ulogic; +signal htw_resv1_tag3_epn_loc_match : std_ulogic; +signal htw_resv1_tag3_epn_glob_match : std_ulogic; +signal tlb_htw_req1_clr_resv_ue : std_ulogic; +signal htw_resv2_tag3_lpid_match : std_ulogic; +signal htw_resv2_tag3_pid_match : std_ulogic; +signal htw_resv2_tag3_as_match : std_ulogic; +signal htw_resv2_tag3_gs_match : std_ulogic; +signal htw_resv2_tag3_epn_loc_match : std_ulogic; +signal htw_resv2_tag3_epn_glob_match : std_ulogic; +signal tlb_htw_req2_clr_resv_ue : std_ulogic; +signal htw_resv3_tag3_lpid_match : std_ulogic; +signal htw_resv3_tag3_pid_match : std_ulogic; +signal htw_resv3_tag3_as_match : std_ulogic; +signal htw_resv3_tag3_gs_match : std_ulogic; +signal htw_resv3_tag3_epn_loc_match : std_ulogic; +signal htw_resv3_tag3_epn_glob_match : std_ulogic; +signal tlb_htw_req3_clr_resv_ue : std_ulogic; +signal htw_resv_valid_vec : std_ulogic_vector(0 to thdid_width-1); +signal htw_tag4_clr_resv_terms : std_ulogic_vector(0 to 3); +signal htw_lsu_act : std_ulogic; +signal pte0_score_act : std_ulogic; +signal pte1_score_act : std_ulogic; +signal reld_act : std_ulogic; +signal pte0_reld_act : std_ulogic; +signal pte1_reld_act : std_ulogic; +signal unused_dc : std_ulogic_vector(0 to 21); +-- synopsys translate_off +-- synopsys translate_on +-- Pervasive +signal pc_sg_1 : std_ulogic; +signal pc_sg_0 : std_ulogic; +signal pc_func_sl_thold_1 : std_ulogic; +signal pc_func_sl_thold_0 : std_ulogic; +signal pc_func_sl_thold_0_b : std_ulogic; +signal pc_func_slp_sl_thold_1 : std_ulogic; +signal pc_func_slp_sl_thold_0 : std_ulogic; +signal pc_func_slp_sl_thold_0_b : std_ulogic; +signal pc_func_sl_force : std_ulogic; +signal pc_func_slp_sl_force : std_ulogic; +signal siv_0 : std_ulogic_vector(0 to scan_right_0); +signal sov_0 : std_ulogic_vector(0 to scan_right_0); +signal siv_1 : std_ulogic_vector(0 to scan_right_1); +signal sov_1 : std_ulogic_vector(0 to scan_right_1); + BEGIN --@@ START OF EXECUTABLE CODE FOR MMQ_HTW + +----------------------------------------------------------------------- +-- Logic +----------------------------------------------------------------------- +-- not quiesced +htw_quiesce_b(0 TO thdid_width-1) <= + ( (0 to thdid_width-1 => tlb_htw_req0_valid_q) and tlb_htw_req0_tag_q(tagpos_thdid to tagpos_thdid+thdid_width-1) ) or + ( (0 to thdid_width-1 => tlb_htw_req1_valid_q) and tlb_htw_req1_tag_q(tagpos_thdid to tagpos_thdid+thdid_width-1) ) or + ( (0 to thdid_width-1 => tlb_htw_req2_valid_q) and tlb_htw_req2_tag_q(tagpos_thdid to tagpos_thdid+thdid_width-1) ) or + ( (0 to thdid_width-1 => tlb_htw_req3_valid_q) and tlb_htw_req3_tag_q(tagpos_thdid to tagpos_thdid+thdid_width-1) ); +htw_quiesce <= not htw_quiesce_b; +tlb_htw_pte_machines_full <= '1' when (pte0_score_pending_q='1' and pte1_score_pending_q='1') + else '0'; +tlb_htw_req_valid_vec <= (tlb_htw_req0_valid_q and (pte0_score_pending_q='0' or pte0_score_ptr_q/="00") and (pte1_score_pending_q='0' or pte1_score_ptr_q/="00")) & + (tlb_htw_req1_valid_q and (pte0_score_pending_q='0' or pte0_score_ptr_q/="01") and (pte1_score_pending_q='0' or pte1_score_ptr_q/="01")) & + (tlb_htw_req2_valid_q and (pte0_score_pending_q='0' or pte0_score_ptr_q/="10") and (pte1_score_pending_q='0' or pte1_score_ptr_q/="10")) & + (tlb_htw_req3_valid_q and (pte0_score_pending_q='0' or pte0_score_ptr_q/="11") and (pte1_score_pending_q='0' or pte1_score_ptr_q/="11")); +-- HTW sequencer for servicing indirect tlb entry hits +Htw_Sequencer: PROCESS (htw_seq_q, tlb_htw_req_valid_vec, tlb_htw_pte_machines_full, htw_lsu_req_taken) +BEGIN +htw_seq_load_pteaddr <= '0'; +htw_lsu_req_valid <= '0'; +CASE htw_seq_q IS + WHEN HtwSeq_Idle => + if tlb_htw_req_valid_vec/="0000" and tlb_htw_pte_machines_full='0' then + htw_seq_d <= HtwSeq_Stg1; + else + htw_seq_d <= HtwSeq_Idle; + end if; + WHEN HtwSeq_Stg1 => + htw_seq_load_pteaddr <= '1'; + htw_seq_d <= HtwSeq_Stg2; + + WHEN HtwSeq_Stg2 => + htw_lsu_req_valid <= '1'; + if htw_lsu_req_taken='1' then + htw_seq_d <= HtwSeq_Idle; + else + htw_seq_d <= HtwSeq_Stg2; + end if; + + WHEN OTHERS => + htw_seq_d <= HtwSeq_Idle; + + END CASE; +END PROCESS Htw_Sequencer; +htw_seq_idle <= '1' when htw_seq_q=HtwSeq_Idle else '0'; +-- PTE sequencer for servicing pte data reloads +Pte0_Sequencer: PROCESS (pte0_seq_q, pte_load_ptr_q, ptereload_ptr_q, htw_lsu_req_taken, ptereload_req_taken, + pte0_score_pending_q, pte0_score_dataval_q, + pte0_score_error_q, pte0_score_qwbeat_q, pte0_score_ibit_q, spare_b_q(0 to 2)) +BEGIN +pte0_reload_req_valid <= '0'; +pte0_reload_req_taken <= '0'; +pte0_seq_score_load <= '0'; +pte0_seq_score_done <= '0'; +pte0_seq_data_retry <= '0'; +pte0_reld_enable_lo_tp2 <= '0'; +pte0_reld_enable_hi_tp2 <= '0'; +pte0_seq_clr_resv_ue <= '0'; +CASE pte0_seq_q IS + WHEN PteSeq_Idle => + if pte_load_ptr_q='0' and htw_lsu_req_taken='1' then + pte0_seq_score_load <= '1'; + pte0_seq_d <= PteSeq_Stg1; + else + pte0_seq_d <= PteSeq_Idle; + end if; + WHEN PteSeq_Stg1 => + if pte0_score_pending_q='1' and pte0_score_dataval_q='1' then + pte0_seq_d <= PteSeq_Stg2; + else + pte0_seq_d <= PteSeq_Stg1; + end if; + + WHEN PteSeq_Stg2 => + if pte0_score_error_q(1)='1' and spare_b_q(0)='1' and (pte0_score_qwbeat_q="1111" or pte0_score_ibit_q='1') then + pte0_seq_d <= PteSeq_Stg4; + elsif pte0_score_error_q(0)='1' and (pte0_score_error_q(2)='0' or spare_b_q(1)='1') and + (pte0_score_qwbeat_q="1111" or pte0_score_ibit_q='1') then + pte0_seq_data_retry <= '1'; + pte0_seq_d <= PteSeq_Stg1; + elsif pte0_score_error_q(1)='1' and (pte0_score_qwbeat_q="1111" or pte0_score_ibit_q='1') then + pte0_seq_d <= PteSeq_Stg4; + elsif pte0_score_error_q(1)='0' and (pte0_score_qwbeat_q="1111" or pte0_score_ibit_q='1') then + pte0_seq_d <= PteSeq_Stg3; + else + pte0_seq_d <= PteSeq_Stg2; + end if; + + WHEN PteSeq_Stg3 => + pte0_reload_req_valid <= '1'; + if ptereload_ptr_q='0' and ptereload_req_taken='1' then + pte0_seq_score_done <= '1'; + pte0_reload_req_taken <= '1'; + pte0_seq_d <= PteSeq_Idle; + else + pte0_seq_d <= PteSeq_Stg3; + end if; + + WHEN PteSeq_Stg4 => + pte0_seq_clr_resv_ue <= not spare_b_q(2); + pte0_seq_d <= PteSeq_Stg5; + + WHEN PteSeq_Stg5 => + pte0_reload_req_valid <= '1'; + if ptereload_ptr_q='0' and ptereload_req_taken='1' then + pte0_seq_score_done <= '1'; + pte0_reload_req_taken <= '1'; + pte0_seq_d <= PteSeq_Idle; + else + pte0_seq_d <= PteSeq_Stg5; + end if; + + WHEN OTHERS => + pte0_seq_d <= PteSeq_Idle; + + END CASE; +END PROCESS Pte0_Sequencer; +pte0_seq_idle <= '1' when pte0_seq_q=PteSeq_Idle else '0'; +-- PTE sequencer for servicing pte data reloads +Pte1_Sequencer: PROCESS (pte1_seq_q, pte_load_ptr_q, ptereload_ptr_q, htw_lsu_req_taken, ptereload_req_taken, + pte1_score_pending_q, pte1_score_dataval_q, + pte1_score_error_q, pte1_score_qwbeat_q, pte1_score_ibit_q, spare_b_q(0 to 2)) +BEGIN +pte1_reload_req_valid <= '0'; +pte1_reload_req_taken <= '0'; +pte1_seq_score_load <= '0'; +pte1_seq_score_done <= '0'; +pte1_seq_data_retry <= '0'; +pte1_reld_enable_lo_tp2 <= '0'; +pte1_reld_enable_hi_tp2 <= '0'; +pte1_seq_clr_resv_ue <= '0'; +CASE pte1_seq_q IS + WHEN PteSeq_Idle => + if pte_load_ptr_q='1' and htw_lsu_req_taken='1' then + pte1_seq_score_load <= '1'; + pte1_seq_d <= PteSeq_Stg1; + else + pte1_seq_d <= PteSeq_Idle; + end if; + WHEN PteSeq_Stg1 => + if pte1_score_pending_q='1' and pte1_score_dataval_q='1' then + pte1_seq_d <= PteSeq_Stg2; + else + pte1_seq_d <= PteSeq_Stg1; + end if; + + WHEN PteSeq_Stg2 => + if pte1_score_error_q(1)='1' and spare_b_q(0)='1' and (pte1_score_qwbeat_q="1111" or pte1_score_ibit_q='1') then + pte1_seq_d <= PteSeq_Stg4; + elsif pte1_score_error_q(0)='1' and (pte1_score_error_q(2)='0' or spare_b_q(1)='1') and + (pte1_score_qwbeat_q="1111" or pte1_score_ibit_q='1') then + pte1_seq_data_retry <= '1'; + pte1_seq_d <= PteSeq_Stg1; + elsif pte1_score_error_q(1)='1' and (pte1_score_qwbeat_q="1111" or pte1_score_ibit_q='1') then + pte1_seq_d <= PteSeq_Stg4; + elsif pte1_score_error_q(1)='0' and (pte1_score_qwbeat_q="1111" or pte1_score_ibit_q='1') then + pte1_seq_d <= PteSeq_Stg3; + else + pte1_seq_d <= PteSeq_Stg2; + end if; + + WHEN PteSeq_Stg3 => + pte1_reload_req_valid <= '1'; + if ptereload_ptr_q='1' and ptereload_req_taken='1' then + pte1_seq_score_done <= '1'; + pte1_reload_req_taken <= '1'; + pte1_seq_d <= PteSeq_Idle; + else + pte1_seq_d <= PteSeq_Stg3; + end if; + + WHEN PteSeq_Stg4 => + pte1_seq_clr_resv_ue <= not spare_b_q(2); + pte1_seq_d <= PteSeq_Stg5; + + WHEN PteSeq_Stg5 => + pte1_reload_req_valid <= '1'; + if ptereload_ptr_q='1' and ptereload_req_taken='1' then + pte1_seq_score_done <= '1'; + pte1_reload_req_taken <= '1'; + pte1_seq_d <= PteSeq_Idle; + else + pte1_seq_d <= PteSeq_Stg5; + end if; + + WHEN OTHERS => + pte1_seq_d <= PteSeq_Idle; + + END CASE; +END PROCESS Pte1_Sequencer; +pte1_seq_idle <= '1' when pte1_seq_q=PteSeq_Idle else '0'; +-- tlb_way IND=0 IND=1 +-- 134 UX SPSIZE0 +-- 135 SX SPSIZE1 +-- 136 UW SPSIZE2 +-- 137 SW SPSIZE3 +-- 138 UR PTRPN +-- 139 SR PA52 +tlb_htw_req0_valid_d <= '1' when (tlb_htw_req_valid='1' and tlb_htw_req0_valid_q='0' and htw_inptr_q="00") + else '0' when (pte0_reload_req_taken='1' and tlb_htw_req0_valid_q='1' and pte0_score_ptr_q="00") + else '0' when (pte1_reload_req_taken='1' and tlb_htw_req0_valid_q='1' and pte1_score_ptr_q="00") + else tlb_htw_req0_valid_q; +tlb_htw_req0_pending_d <= '1' when (htw_lsu_req_taken='1' and tlb_htw_req0_pending_q='0' and htw_lsuptr_q="00") + else '0' when (pte0_reload_req_taken='1' and tlb_htw_req0_pending_q='1' and pte0_score_ptr_q="00") + else '0' when (pte1_reload_req_taken='1' and tlb_htw_req0_pending_q='1' and pte1_score_ptr_q="00") + else tlb_htw_req0_pending_q; +-- the rpn part of the tlb way +tlb_htw_req0_way_d <= tlb_htw_req_way when (tlb_htw_req_valid='1' and tlb_htw_req0_valid_q='0' and htw_inptr_q="00") + else tlb_htw_req0_way_q; +tlb_htw_req0_tag_d(0 TO tagpos_wq-1) <= tlb_htw_req_tag(0 to tagpos_wq-1) when (tlb_htw_req_valid='1' and tlb_htw_req0_valid_q='0' and htw_inptr_q="00") + else tlb_htw_req0_tag_q(0 to tagpos_wq-1); +tlb_htw_req0_tag_d(tagpos_wq+2 TO tlb_tag_width-1) <= tlb_htw_req_tag(tagpos_wq+2 to tlb_tag_width-1) when (tlb_htw_req_valid='1' and tlb_htw_req0_valid_q='0' and htw_inptr_q="00") + else tlb_htw_req0_tag_q(tagpos_wq+2 to tlb_tag_width-1); +-- the WQ bits of the tag are re-purposed as reservation valid and duplicate bits +-- set reservation valid at tlb handoff, clear when ptereload taken.. +-- or, clear reservation if tlbwe,ptereload,tlbi from another thread to avoid duplicates +-- or, clear reservation when L2 UE for this reload +tlb_htw_req0_tag_d(tagpos_wq) <= '0' when ((htw_tag5_clr_resv_q(0)='1' and tlb_tag5_except="0000") or tlb_htw_req0_clr_resv_ue='1') + else '1' when (tlb_htw_req_valid='1' and tlb_htw_req0_valid_q='0' and htw_inptr_q="00") + else '0' when (pte0_reload_req_taken='1' and tlb_htw_req0_valid_q='1' and pte0_score_ptr_q="00") + else '0' when (pte1_reload_req_taken='1' and tlb_htw_req0_valid_q='1' and pte1_score_ptr_q="00") + else tlb_htw_req0_tag_q(tagpos_wq); +-- spare, wq+1 is duplicate indicator in tlb_cmp, but would not make it to tlb handoff +tlb_htw_req0_tag_d(tagpos_wq+1) <= tlb_htw_req0_tag_q(tagpos_wq+1); +tlb_htw_req0_tag_act <= tlb_delayed_act(24+0) or tlb_htw_req0_valid_q; +tlb_htw_req0_clr_resv_ue <= (pte0_seq_clr_resv_ue and Eq(pte0_score_ptr_q,"00")) or + (pte1_seq_clr_resv_ue and Eq(pte1_score_ptr_q,"00")); +htw_req0_valid <= tlb_htw_req0_valid_q; +htw_req0_thdid <= tlb_htw_req0_tag_q(tagpos_thdid to tagpos_thdid+thdid_width-1); +htw_req0_type <= tlb_htw_req0_tag_q(tagpos_type_derat to tagpos_type_ierat); +pte_ra_0_spsize4K <= tlb_htw_req0_way_q(waypos_rpn to waypos_rpn+rpn_width-1) & + tlb_htw_req0_way_q(waypos_usxwr+5) & + tlb_htw_req0_tag_q(tagpos_epn+epn_width-8 to tagpos_epn+epn_width-1) & "000"; +pte_ra_0_spsize64K <= tlb_htw_req0_way_q(waypos_rpn to waypos_rpn+rpn_width-4) & + tlb_htw_req0_tag_q(tagpos_epn+epn_width-16 to tagpos_epn+epn_width-5) & "000"; +-- select based on SPSIZE +pte_ra_0 <= pte_ra_0_spsize64K when tlb_htw_req0_way_q(waypos_usxwr to waypos_usxwr+3)=TLB_PgSize_64KB + else pte_ra_0_spsize4K; +tlb_htw_req1_valid_d <= '1' when (tlb_htw_req_valid='1' and tlb_htw_req1_valid_q='0' and htw_inptr_q="01") + else '0' when (pte0_reload_req_taken='1' and tlb_htw_req1_valid_q='1' and pte0_score_ptr_q="01") + else '0' when (pte1_reload_req_taken='1' and tlb_htw_req1_valid_q='1' and pte1_score_ptr_q="01") + else tlb_htw_req1_valid_q; +tlb_htw_req1_pending_d <= '1' when (htw_lsu_req_taken='1' and tlb_htw_req1_pending_q='0' and htw_lsuptr_q="01") + else '0' when (pte0_reload_req_taken='1' and tlb_htw_req1_pending_q='1' and pte0_score_ptr_q="01") + else '0' when (pte1_reload_req_taken='1' and tlb_htw_req1_pending_q='1' and pte1_score_ptr_q="01") + else tlb_htw_req1_pending_q; +-- the rpn part of the tlb way +tlb_htw_req1_way_d <= tlb_htw_req_way when (tlb_htw_req_valid='1' and tlb_htw_req1_valid_q='0' and htw_inptr_q="01") + else tlb_htw_req1_way_q; +tlb_htw_req1_tag_d(0 TO tagpos_wq-1) <= tlb_htw_req_tag(0 to tagpos_wq-1) when (tlb_htw_req_valid='1' and tlb_htw_req1_valid_q='0' and htw_inptr_q="01") + else tlb_htw_req1_tag_q(0 to tagpos_wq-1); +tlb_htw_req1_tag_d(tagpos_wq+2 TO tlb_tag_width-1) <= tlb_htw_req_tag(tagpos_wq+2 to tlb_tag_width-1) when (tlb_htw_req_valid='1' and tlb_htw_req1_valid_q='0' and htw_inptr_q="01") + else tlb_htw_req1_tag_q(tagpos_wq+2 to tlb_tag_width-1); +-- the WQ bits of the tag are re-purposed as reservation valid and duplicate bits +-- set reservation valid at tlb handoff, clear when ptereload taken.. +-- or, clear reservation if tlbwe,ptereload,tlbi from another thread to avoid duplicates +-- or, clear reservation when L2 UE for this reload +tlb_htw_req1_tag_d(tagpos_wq) <= '0' when ((htw_tag5_clr_resv_q(1)='1' and tlb_tag5_except="0000") or tlb_htw_req1_clr_resv_ue='1') + else '1' when (tlb_htw_req_valid='1' and tlb_htw_req1_valid_q='0' and htw_inptr_q="01") + else '0' when (pte0_reload_req_taken='1' and tlb_htw_req1_valid_q='1' and pte0_score_ptr_q="01") + else '0' when (pte1_reload_req_taken='1' and tlb_htw_req1_valid_q='1' and pte1_score_ptr_q="01") + else tlb_htw_req1_tag_q(tagpos_wq); +-- spare, wq+1 is duplicate indicator in tlb_cmp, but would not make it to tlb handoff +tlb_htw_req1_tag_d(tagpos_wq+1) <= tlb_htw_req1_tag_q(tagpos_wq+1); +tlb_htw_req1_tag_act <= tlb_delayed_act(24+1) or tlb_htw_req1_valid_q; +tlb_htw_req1_clr_resv_ue <= (pte0_seq_clr_resv_ue and Eq(pte0_score_ptr_q,"01")) or + (pte1_seq_clr_resv_ue and Eq(pte1_score_ptr_q,"01")); +htw_req1_valid <= tlb_htw_req1_valid_q; +htw_req1_thdid <= tlb_htw_req1_tag_q(tagpos_thdid to tagpos_thdid+thdid_width-1); +htw_req1_type <= tlb_htw_req1_tag_q(tagpos_type_derat to tagpos_type_ierat); +pte_ra_1_spsize4K <= tlb_htw_req1_way_q(waypos_rpn to waypos_rpn+rpn_width-1) & + tlb_htw_req1_way_q(waypos_usxwr+5) & + tlb_htw_req1_tag_q(tagpos_epn+epn_width-8 to tagpos_epn+epn_width-1) & "000"; +pte_ra_1_spsize64K <= tlb_htw_req1_way_q(waypos_rpn to waypos_rpn+rpn_width-4) & + tlb_htw_req1_tag_q(tagpos_epn+epn_width-16 to tagpos_epn+epn_width-5) & "000"; +pte_ra_1 <= pte_ra_1_spsize64K when tlb_htw_req1_way_q(waypos_usxwr to waypos_usxwr+3)=TLB_PgSize_64KB + else pte_ra_1_spsize4K; +tlb_htw_req2_valid_d <= '1' when (tlb_htw_req_valid='1' and tlb_htw_req2_valid_q='0' and htw_inptr_q="10") + else '0' when (pte0_reload_req_taken='1' and tlb_htw_req2_valid_q='1' and pte0_score_ptr_q="10") + else '0' when (pte1_reload_req_taken='1' and tlb_htw_req2_valid_q='1' and pte1_score_ptr_q="10") + else tlb_htw_req2_valid_q; +tlb_htw_req2_pending_d <= '1' when (htw_lsu_req_taken='1' and tlb_htw_req2_pending_q='0' and htw_lsuptr_q="10") + else '0' when (pte0_reload_req_taken='1' and tlb_htw_req2_pending_q='1' and pte0_score_ptr_q="10") + else '0' when (pte1_reload_req_taken='1' and tlb_htw_req2_pending_q='1' and pte1_score_ptr_q="10") + else tlb_htw_req2_pending_q; +-- the rpn part of the tlb way +tlb_htw_req2_way_d <= tlb_htw_req_way when (tlb_htw_req_valid='1' and tlb_htw_req2_valid_q='0' and htw_inptr_q="10") + else tlb_htw_req2_way_q; +tlb_htw_req2_tag_d(0 TO tagpos_wq-1) <= tlb_htw_req_tag(0 to tagpos_wq-1) when (tlb_htw_req_valid='1' and tlb_htw_req2_valid_q='0' and htw_inptr_q="10") + else tlb_htw_req2_tag_q(0 to tagpos_wq-1); +tlb_htw_req2_tag_d(tagpos_wq+2 TO tlb_tag_width-1) <= tlb_htw_req_tag(tagpos_wq+2 to tlb_tag_width-1) when (tlb_htw_req_valid='1' and tlb_htw_req2_valid_q='0' and htw_inptr_q="10") + else tlb_htw_req2_tag_q(tagpos_wq+2 to tlb_tag_width-1); +-- the WQ bits of the tag are re-purposed as reservation valid and duplicate bits +-- set reservation valid at tlb handoff, clear when ptereload taken.. +-- or, clear reservation if tlbwe,ptereload,tlbi from another thread to avoid duplicates +-- or, clear reservation when L2 UE for this reload +tlb_htw_req2_tag_d(tagpos_wq) <= '0' when ((htw_tag5_clr_resv_q(2)='1' and tlb_tag5_except="0000") or tlb_htw_req2_clr_resv_ue='1') + else '1' when (tlb_htw_req_valid='1' and tlb_htw_req2_valid_q='0' and htw_inptr_q="10") + else '0' when (pte0_reload_req_taken='1' and tlb_htw_req2_valid_q='1' and pte0_score_ptr_q="10") + else '0' when (pte1_reload_req_taken='1' and tlb_htw_req2_valid_q='1' and pte1_score_ptr_q="10") + else tlb_htw_req2_tag_q(tagpos_wq); +tlb_htw_req2_tag_d(tagpos_wq+1) <= tlb_htw_req2_tag_q(tagpos_wq+1); +tlb_htw_req2_tag_act <= tlb_delayed_act(24+2) or tlb_htw_req2_valid_q; +tlb_htw_req2_clr_resv_ue <= (pte0_seq_clr_resv_ue and Eq(pte0_score_ptr_q,"10")) or + (pte1_seq_clr_resv_ue and Eq(pte1_score_ptr_q,"10")); +htw_req2_valid <= tlb_htw_req2_valid_q; +htw_req2_thdid <= tlb_htw_req2_tag_q(tagpos_thdid to tagpos_thdid+thdid_width-1); +htw_req2_type <= tlb_htw_req2_tag_q(tagpos_type_derat to tagpos_type_ierat); +pte_ra_2_spsize4K <= tlb_htw_req2_way_q(waypos_rpn to waypos_rpn+rpn_width-1) & + tlb_htw_req2_way_q(waypos_usxwr+5) & + tlb_htw_req2_tag_q(tagpos_epn+epn_width-8 to tagpos_epn+epn_width-1) & "000"; +pte_ra_2_spsize64K <= tlb_htw_req2_way_q(waypos_rpn to waypos_rpn+rpn_width-4) & + tlb_htw_req2_tag_q(tagpos_epn+epn_width-16 to tagpos_epn+epn_width-5) & "000"; +-- select based on SPSIZE +pte_ra_2 <= pte_ra_2_spsize64K when tlb_htw_req2_way_q(waypos_usxwr to waypos_usxwr+3)=TLB_PgSize_64KB + else pte_ra_2_spsize4K; +tlb_htw_req3_valid_d <= '1' when (tlb_htw_req_valid='1' and tlb_htw_req3_valid_q='0' and htw_inptr_q="11") + else '0' when (pte0_reload_req_taken='1' and tlb_htw_req3_valid_q='1' and pte0_score_ptr_q="11") + else '0' when (pte1_reload_req_taken='1' and tlb_htw_req3_valid_q='1' and pte1_score_ptr_q="11") + else tlb_htw_req3_valid_q; +tlb_htw_req3_pending_d <= '1' when (htw_lsu_req_taken='1' and tlb_htw_req3_pending_q='0' and htw_lsuptr_q="11") + else '0' when (pte0_reload_req_taken='1' and tlb_htw_req3_pending_q='1' and pte0_score_ptr_q="11") + else '0' when (pte1_reload_req_taken='1' and tlb_htw_req3_pending_q='1' and pte1_score_ptr_q="11") + else tlb_htw_req3_pending_q; +-- the rpn part of the tlb way +tlb_htw_req3_way_d <= tlb_htw_req_way when (tlb_htw_req_valid='1' and tlb_htw_req3_valid_q='0' and htw_inptr_q="11") + else tlb_htw_req3_way_q; +tlb_htw_req3_tag_d(0 TO tagpos_wq-1) <= tlb_htw_req_tag(0 to tagpos_wq-1) when (tlb_htw_req_valid='1' and tlb_htw_req3_valid_q='0' and htw_inptr_q="11") + else tlb_htw_req3_tag_q(0 to tagpos_wq-1); +tlb_htw_req3_tag_d(tagpos_wq+2 TO tlb_tag_width-1) <= tlb_htw_req_tag(tagpos_wq+2 to tlb_tag_width-1) when (tlb_htw_req_valid='1' and tlb_htw_req3_valid_q='0' and htw_inptr_q="11") + else tlb_htw_req3_tag_q(tagpos_wq+2 to tlb_tag_width-1); +-- the WQ bits of the tag are re-purposed as reservation valid and duplicate bits +-- set reservation valid at tlb handoff, clear when ptereload taken.. +-- or, clear reservation if tlbwe,ptereload,tlbi from another thread to avoid duplicates +-- or, clear reservation when L2 UE for this reload +tlb_htw_req3_tag_d(tagpos_wq) <= '0' when ((htw_tag5_clr_resv_q(3)='1' and tlb_tag5_except="0000") or tlb_htw_req3_clr_resv_ue='1') + else '1' when (tlb_htw_req_valid='1' and tlb_htw_req3_valid_q='0' and htw_inptr_q="11") + else '0' when (pte0_reload_req_taken='1' and tlb_htw_req3_valid_q='1' and pte0_score_ptr_q="11") + else '0' when (pte1_reload_req_taken='1' and tlb_htw_req3_valid_q='1' and pte1_score_ptr_q="11") + else tlb_htw_req3_tag_q(tagpos_wq); +-- spare, wq+1 is duplicate indicator in tlb_cmp, but would not make it to tlb handoff +tlb_htw_req3_tag_d(tagpos_wq+1) <= tlb_htw_req3_tag_q(tagpos_wq+1); +tlb_htw_req3_tag_act <= tlb_delayed_act(24+3) or tlb_htw_req3_valid_q; +tlb_htw_req3_clr_resv_ue <= (pte0_seq_clr_resv_ue and Eq(pte0_score_ptr_q,"11")) or + (pte1_seq_clr_resv_ue and Eq(pte1_score_ptr_q,"11")); +htw_req3_valid <= tlb_htw_req3_valid_q; +htw_req3_thdid <= tlb_htw_req3_tag_q(tagpos_thdid to tagpos_thdid+thdid_width-1); +htw_req3_type <= tlb_htw_req3_tag_q(tagpos_type_derat to tagpos_type_ierat); +pte_ra_3_spsize4K <= tlb_htw_req3_way_q(waypos_rpn to waypos_rpn+rpn_width-1) & + tlb_htw_req3_way_q(waypos_usxwr+5) & + tlb_htw_req3_tag_q(tagpos_epn+epn_width-8 to tagpos_epn+epn_width-1) & "000"; +pte_ra_3_spsize64K <= tlb_htw_req3_way_q(waypos_rpn to waypos_rpn+rpn_width-4) & + tlb_htw_req3_tag_q(tagpos_epn+epn_width-16 to tagpos_epn+epn_width-5) & "000"; +-- select based on SPSIZE +pte_ra_3 <= pte_ra_3_spsize64K when tlb_htw_req3_way_q(waypos_usxwr to waypos_usxwr+3)=TLB_PgSize_64KB + else pte_ra_3_spsize4K; +-- tag forwarding from tlb_ctl, for reservation clear compares +htw_tag3_d(0 TO tagpos_thdid-1) <= tlb_tag2(0 to tagpos_thdid-1); +htw_tag3_d(tagpos_thdid+thdid_width TO tlb_tag_width-1) <= tlb_tag2(tagpos_thdid+thdid_width to tlb_tag_width-1); +htw_tag3_d(tagpos_thdid TO tagpos_thdid+thdid_width-1) <= tlb_tag2(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag2_flush); +-- reservation clear: +-- (1) proc holding resv executes another tlbsrx. overwriting the old resv +-- (2) any tlbivax snoop with gs,as,lpid,pid,sizemasked(epn,mas6.isize) matching resv.gs,as,lpid,pid,sizemasked(epn,mas6.isize) +-- (note ind bit is not part of tlbivax criteria!!) +-- (3) any proc sets mmucsr0.TLB0_FI=1 with lpidr matching resv.lpid +-- (4) any proc executes tlbilx T=0 (all) with mas5.slpid matching resv.lpid +-- (5) any proc executes tlbilx T=1 (pid) with mas5.slpid and mas6.spid matching resv.lpid,pid +-- (6) any proc executes tlbilx T=3 (vpn) with mas gs,as,slpid,spid,sizemasked(epn,mas6.isize) matching +-- resv.gs,as,lpid,pid,sizemasked(epn,mas6.isize) +-- (note ind bit is not part of tlbilx criteria!!) +-- (7) any proc executes tlbwe not causing exception and with (wq=00 always, or wq=01 and proc holds resv) +-- and mas regs ind,tgs,ts,tlpid,tid,sizemasked(epn,mas1.tsize) match resv.ind,gs,as,lpid,pid,sizemasked(epn,mas1.tsize) +-- (8) any page table reload not causing an exception (due to pt fault, tlb inelig, or lrat miss) +-- and PTE's tag ind=0,tgs,ts,tlpid,tid,sizemasked(epn,pte.size) match resv.ind=0,gs,as,lpid,pid,sizemasked(epn.pte.size) +-- A2-specific non-architected clear states +-- (9) any proc executes tlbwe not causing exception and with (wq=10 clear, or wq=11 always (same as 00)) +-- and mas regs ind,tgs,ts,tlpid,tid,sizemasked(epn,mas1.tsize) match resv.ind,gs,as,lpid,pid,sizemasked(epn,mas1.tsize) +-- (basically same as 7, +-- (10) any proc executes tlbilx T=2 (gs) with mas5.sgs matching resv.gs +-- (11) any proc executes tlbilx T=4 to 7 (class) with T(1:2) matching resv.class +-- ttype <= tlbre & tlbwe & tlbsx & tlbsxr & tlbsrx; +-- IS0: Local bit +-- IS1/Class: 0=all, 1=tid, 2=gs, 3=vpn, 4=class0, 5=class1, 6=class2, 7=class3 +-- mas0.wq: 00=ignore reserv write always, 01=write if reserved, 10=clear reserv, 11=same as 00 +htw_tag3_clr_resv_term2(0) <= '1' when (htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000" and + htw_tag3_q(tagpos_type_snoop)='1' and htw_tag3_q(tagpos_is to tagpos_is+3)="0011" and + htw_resv0_tag3_lpid_match='1' and htw_resv0_tag3_pid_match='1' and htw_resv0_tag3_gs_match='1' and + htw_resv0_tag3_as_match='1' and htw_resv0_tag3_epn_glob_match='1' ) + else '0'; +htw_tag3_clr_resv_term4(0) <= '1' when (htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000" and + htw_tag3_q(tagpos_type_snoop)='1' and htw_tag3_q(tagpos_is to tagpos_is+3)="1000" and + htw_resv0_tag3_lpid_match='1' ) + else '0'; +htw_tag3_clr_resv_term5(0) <= '1' when (htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000" and + htw_tag3_q(tagpos_type_snoop)='1' and htw_tag3_q(tagpos_is to tagpos_is+3)="1001" and + htw_resv0_tag3_lpid_match='1' and htw_resv0_tag3_pid_match='1' ) + else '0'; +htw_tag3_clr_resv_term6(0) <= '1' when (htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000" and + htw_tag3_q(tagpos_type_snoop)='1' and htw_tag3_q(tagpos_is to tagpos_is+3)="1011" and + htw_resv0_tag3_lpid_match='1' and htw_resv0_tag3_pid_match='1' and htw_resv0_tag3_gs_match='1' and + htw_resv0_tag3_as_match='1' and htw_resv0_tag3_epn_loc_match='1' ) + else '0'; +htw_tag3_clr_resv_term7(0) <= '1' when ( (((htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag3_flush))/="0000" and htw_tag3_q(tagpos_wq to tagpos_wq+1)="01") or + ((htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag3_flush))/="0000" and htw_tag3_q(tagpos_wq to tagpos_wq+1)="00")) and + htw_tag3_q(tagpos_type_tlbwe)='1' and + htw_resv0_tag3_gs_match='1' and htw_resv0_tag3_as_match='1' and + htw_resv0_tag3_lpid_match='1' and htw_resv0_tag3_pid_match='1' and + htw_resv0_tag3_epn_loc_match='1' ) + else '0'; +htw_tag3_clr_resv_term8(0) <= '1' when ( htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000" and + htw_tag3_q(tagpos_type_ptereload)='1' and htw_tag3_q(tagpos_wq to tagpos_wq+1)="10" and + htw_resv0_tag3_gs_match='1' and htw_resv0_tag3_as_match='1' and + htw_resv0_tag3_lpid_match='1' and htw_resv0_tag3_pid_match='1' and + htw_resv0_tag3_epn_loc_match='1' ) + else '0'; +htw_tag3_clr_resv_term9(0) <= '1' when ( (((htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag3_flush))/="0000" and htw_tag3_q(tagpos_wq to tagpos_wq+1)="10") or + ((htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag3_flush))/="0000" and htw_tag3_q(tagpos_wq to tagpos_wq+1)="11")) and + htw_tag3_q(tagpos_type_tlbwe)='1' and + htw_resv0_tag3_gs_match='1' and htw_resv0_tag3_as_match='1' and + htw_resv0_tag3_lpid_match='1' and htw_resv0_tag3_pid_match='1' and + htw_resv0_tag3_epn_loc_match='1' ) + else '0'; +htw_tag3_clr_resv_term11(0) <= '1' when (htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000" and + htw_tag3_q(tagpos_type_snoop)='1' and htw_tag3_q(tagpos_is to tagpos_is+1)="11" ) + else '0'; +htw_tag4_clr_resv_d(0) <= htw_tag3_clr_resv_term2(0) or htw_tag3_clr_resv_term4(0) or htw_tag3_clr_resv_term5(0) or htw_tag3_clr_resv_term6(0) or + htw_tag3_clr_resv_term7(0) or htw_tag3_clr_resv_term8(0) or htw_tag3_clr_resv_term9(0) or + htw_tag3_clr_resv_term11(0); +htw_tag3_clr_resv_term2(1) <= '1' when (htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000" and + htw_tag3_q(tagpos_type_snoop)='1' and htw_tag3_q(tagpos_is to tagpos_is+3)="0011" and + htw_resv1_tag3_lpid_match='1' and htw_resv1_tag3_pid_match='1' and htw_resv1_tag3_gs_match='1' and + htw_resv1_tag3_as_match='1' and htw_resv1_tag3_epn_glob_match='1' ) + else '0'; +htw_tag3_clr_resv_term4(1) <= '1' when (htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000" and + htw_tag3_q(tagpos_type_snoop)='1' and htw_tag3_q(tagpos_is to tagpos_is+3)="1000" and + htw_resv1_tag3_lpid_match='1' ) + else '0'; +htw_tag3_clr_resv_term5(1) <= '1' when (htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000" and + htw_tag3_q(tagpos_type_snoop)='1' and htw_tag3_q(tagpos_is to tagpos_is+3)="1001" and + htw_resv1_tag3_lpid_match='1' and htw_resv1_tag3_pid_match='1' ) + else '0'; +htw_tag3_clr_resv_term6(1) <= '1' when (htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000" and + htw_tag3_q(tagpos_type_snoop)='1' and htw_tag3_q(tagpos_is to tagpos_is+3)="1011" and + htw_resv1_tag3_lpid_match='1' and htw_resv1_tag3_pid_match='1' and htw_resv1_tag3_gs_match='1' and + htw_resv1_tag3_as_match='1' and htw_resv1_tag3_epn_loc_match='1' ) + else '0'; +htw_tag3_clr_resv_term7(1) <= '1' when ( (((htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag3_flush))/="0000" and htw_tag3_q(tagpos_wq to tagpos_wq+1)="01") or + ((htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag3_flush))/="0000" and htw_tag3_q(tagpos_wq to tagpos_wq+1)="00")) and + htw_tag3_q(tagpos_type_tlbwe)='1' and + htw_resv1_tag3_gs_match='1' and htw_resv1_tag3_as_match='1' and + htw_resv1_tag3_lpid_match='1' and htw_resv1_tag3_pid_match='1' and + htw_resv1_tag3_epn_loc_match='1' ) + else '0'; +htw_tag3_clr_resv_term8(1) <= '1' when ( htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000" and + htw_tag3_q(tagpos_type_ptereload)='1' and htw_tag3_q(tagpos_wq to tagpos_wq+1)="10" and + htw_resv1_tag3_gs_match='1' and htw_resv1_tag3_as_match='1' and + htw_resv1_tag3_lpid_match='1' and htw_resv1_tag3_pid_match='1' and + htw_resv1_tag3_epn_loc_match='1' ) + else '0'; +htw_tag3_clr_resv_term9(1) <= '1' when ( (((htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag3_flush))/="0000" and htw_tag3_q(tagpos_wq to tagpos_wq+1)="10") or + ((htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag3_flush))/="0000" and htw_tag3_q(tagpos_wq to tagpos_wq+1)="11")) and + htw_tag3_q(tagpos_type_tlbwe)='1' and + htw_resv1_tag3_gs_match='1' and htw_resv1_tag3_as_match='1' and + htw_resv1_tag3_lpid_match='1' and htw_resv1_tag3_pid_match='1' and + htw_resv1_tag3_epn_loc_match='1' ) + else '0'; +htw_tag3_clr_resv_term11(1) <= '1' when (htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000" and + htw_tag3_q(tagpos_type_snoop)='1' and htw_tag3_q(tagpos_is to tagpos_is+1)="11" ) + else '0'; +htw_tag4_clr_resv_d(1) <= htw_tag3_clr_resv_term2(1) or htw_tag3_clr_resv_term4(1) or htw_tag3_clr_resv_term5(1) or htw_tag3_clr_resv_term6(1) or + htw_tag3_clr_resv_term7(1) or htw_tag3_clr_resv_term8(1) or htw_tag3_clr_resv_term9(1) or + htw_tag3_clr_resv_term11(1); +htw_tag3_clr_resv_term2(2) <= '1' when (htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000" and + htw_tag3_q(tagpos_type_snoop)='1' and htw_tag3_q(tagpos_is to tagpos_is+3)="0011" and + htw_resv2_tag3_lpid_match='1' and htw_resv2_tag3_pid_match='1' and htw_resv2_tag3_gs_match='1' and + htw_resv2_tag3_as_match='1' and htw_resv2_tag3_epn_glob_match='1' ) + else '0'; +htw_tag3_clr_resv_term4(2) <= '1' when (htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000" and + htw_tag3_q(tagpos_type_snoop)='1' and htw_tag3_q(tagpos_is to tagpos_is+3)="1000" and + htw_resv2_tag3_lpid_match='1' ) + else '0'; +htw_tag3_clr_resv_term5(2) <= '1' when (htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000" and + htw_tag3_q(tagpos_type_snoop)='1' and htw_tag3_q(tagpos_is to tagpos_is+3)="1001" and + htw_resv2_tag3_lpid_match='1' and htw_resv2_tag3_pid_match='1' ) + else '0'; +htw_tag3_clr_resv_term6(2) <= '1' when (htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000" and + htw_tag3_q(tagpos_type_snoop)='1' and htw_tag3_q(tagpos_is to tagpos_is+3)="1011" and + htw_resv2_tag3_lpid_match='1' and htw_resv2_tag3_pid_match='1' and htw_resv2_tag3_gs_match='1' and + htw_resv2_tag3_as_match='1' and htw_resv2_tag3_epn_loc_match='1' ) + else '0'; +htw_tag3_clr_resv_term7(2) <= '1' when ( (((htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag3_flush))/="0000" and htw_tag3_q(tagpos_wq to tagpos_wq+1)="01") or + ((htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag3_flush))/="0000" and htw_tag3_q(tagpos_wq to tagpos_wq+1)="00")) and + htw_tag3_q(tagpos_type_tlbwe)='1' and + htw_resv2_tag3_gs_match='1' and htw_resv2_tag3_as_match='1' and + htw_resv2_tag3_lpid_match='1' and htw_resv2_tag3_pid_match='1' and + htw_resv2_tag3_epn_loc_match='1' ) + else '0'; +htw_tag3_clr_resv_term8(2) <= '1' when ( htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000" and + htw_tag3_q(tagpos_type_ptereload)='1' and htw_tag3_q(tagpos_wq to tagpos_wq+1)="10" and + htw_resv2_tag3_gs_match='1' and htw_resv2_tag3_as_match='1' and + htw_resv2_tag3_lpid_match='1' and htw_resv2_tag3_pid_match='1' and + htw_resv2_tag3_epn_loc_match='1' ) + else '0'; +htw_tag3_clr_resv_term9(2) <= '1' when ( (((htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag3_flush))/="0000" and htw_tag3_q(tagpos_wq to tagpos_wq+1)="10") or + ((htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag3_flush))/="0000" and htw_tag3_q(tagpos_wq to tagpos_wq+1)="11")) and + htw_tag3_q(tagpos_type_tlbwe)='1' and + htw_resv2_tag3_gs_match='1' and htw_resv2_tag3_as_match='1' and + htw_resv2_tag3_lpid_match='1' and htw_resv2_tag3_pid_match='1' and + htw_resv2_tag3_epn_loc_match='1' ) + else '0'; +htw_tag3_clr_resv_term11(2) <= '1' when (htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000" and + htw_tag3_q(tagpos_type_snoop)='1' and htw_tag3_q(tagpos_is to tagpos_is+1)="11" ) + else '0'; +htw_tag4_clr_resv_d(2) <= htw_tag3_clr_resv_term2(2) or htw_tag3_clr_resv_term4(2) or htw_tag3_clr_resv_term5(2) or htw_tag3_clr_resv_term6(2) or + htw_tag3_clr_resv_term7(2) or htw_tag3_clr_resv_term8(2) or htw_tag3_clr_resv_term9(2) or + htw_tag3_clr_resv_term11(2); +htw_tag3_clr_resv_term2(3) <= '1' when (htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000" and + htw_tag3_q(tagpos_type_snoop)='1' and htw_tag3_q(tagpos_is to tagpos_is+3)="0011" and + htw_resv3_tag3_lpid_match='1' and htw_resv3_tag3_pid_match='1' and htw_resv3_tag3_gs_match='1' and + htw_resv3_tag3_as_match='1' and htw_resv3_tag3_epn_glob_match='1' ) + else '0'; +htw_tag3_clr_resv_term4(3) <= '1' when (htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000" and + htw_tag3_q(tagpos_type_snoop)='1' and htw_tag3_q(tagpos_is to tagpos_is+3)="1000" and + htw_resv3_tag3_lpid_match='1' ) + else '0'; +htw_tag3_clr_resv_term5(3) <= '1' when (htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000" and + htw_tag3_q(tagpos_type_snoop)='1' and htw_tag3_q(tagpos_is to tagpos_is+3)="1001" and + htw_resv3_tag3_lpid_match='1' and htw_resv3_tag3_pid_match='1' ) + else '0'; +htw_tag3_clr_resv_term6(3) <= '1' when (htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000" and + htw_tag3_q(tagpos_type_snoop)='1' and htw_tag3_q(tagpos_is to tagpos_is+3)="1011" and + htw_resv3_tag3_lpid_match='1' and htw_resv3_tag3_pid_match='1' and htw_resv3_tag3_gs_match='1' and + htw_resv3_tag3_as_match='1' and htw_resv3_tag3_epn_loc_match='1' ) + else '0'; +htw_tag3_clr_resv_term7(3) <= '1' when ( (((htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag3_flush))/="0000" and htw_tag3_q(tagpos_wq to tagpos_wq+1)="01") or + ((htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag3_flush))/="0000" and htw_tag3_q(tagpos_wq to tagpos_wq+1)="00")) and + htw_tag3_q(tagpos_type_tlbwe)='1' and + htw_resv3_tag3_gs_match='1' and htw_resv3_tag3_as_match='1' and + htw_resv3_tag3_lpid_match='1' and htw_resv3_tag3_pid_match='1' and + htw_resv3_tag3_epn_loc_match='1' ) + else '0'; +htw_tag3_clr_resv_term8(3) <= '1' when ( htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000" and + htw_tag3_q(tagpos_type_ptereload)='1' and htw_tag3_q(tagpos_wq to tagpos_wq+1)="10" and + htw_resv3_tag3_gs_match='1' and htw_resv3_tag3_as_match='1' and + htw_resv3_tag3_lpid_match='1' and htw_resv3_tag3_pid_match='1' and + htw_resv3_tag3_epn_loc_match='1' ) + else '0'; +htw_tag3_clr_resv_term9(3) <= '1' when ( (((htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag3_flush))/="0000" and htw_tag3_q(tagpos_wq to tagpos_wq+1)="10") or + ((htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag3_flush))/="0000" and htw_tag3_q(tagpos_wq to tagpos_wq+1)="11")) and + htw_tag3_q(tagpos_type_tlbwe)='1' and + htw_resv3_tag3_gs_match='1' and htw_resv3_tag3_as_match='1' and + htw_resv3_tag3_lpid_match='1' and htw_resv3_tag3_pid_match='1' and + htw_resv3_tag3_epn_loc_match='1' ) + else '0'; +htw_tag3_clr_resv_term11(3) <= '1' when (htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000" and + htw_tag3_q(tagpos_type_snoop)='1' and htw_tag3_q(tagpos_is to tagpos_is+1)="11" ) + else '0'; +htw_tag4_clr_resv_d(3) <= htw_tag3_clr_resv_term2(3) or htw_tag3_clr_resv_term4(3) or htw_tag3_clr_resv_term5(3) or htw_tag3_clr_resv_term6(3) or + htw_tag3_clr_resv_term7(3) or htw_tag3_clr_resv_term8(3) or htw_tag3_clr_resv_term9(3) or + htw_tag3_clr_resv_term11(3); +htw_tag5_clr_resv_d <= htw_tag4_clr_resv_q when + (tlb_htw_req_tag(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag4_flush))/="0000" + else "0000"; +htw_resv_valid_vec <= tlb_htw_req0_tag_q(tagpos_wq) & tlb_htw_req1_tag_q(tagpos_wq) & tlb_htw_req2_tag_q(tagpos_wq) & tlb_htw_req3_tag_q(tagpos_wq); +htw_resv0_tag3_lpid_match <= '1' when (htw_tag3_q(tagpos_lpid to tagpos_lpid+lpid_width-1)=tlb_htw_req0_tag_q(tagpos_lpid to tagpos_lpid+lpid_width-1)) else '0'; +htw_resv0_tag3_pid_match <= '1' when (htw_tag3_q(tagpos_pid to tagpos_pid+pid_width-1)=tlb_htw_req0_tag_q(tagpos_pid to tagpos_pid+pid_width-1)) else '0'; +htw_resv0_tag3_as_match <= '1' when (htw_tag3_q(tagpos_as)=tlb_htw_req0_tag_q(tagpos_as)) else '0'; +htw_resv0_tag3_gs_match <= '1' when (htw_tag3_q(tagpos_gs)=tlb_htw_req0_tag_q(tagpos_gs)) else '0'; +htw_resv0_tag3_epn_loc_match <= '1' when (htw_tag3_q(tagpos_epn to tagpos_epn+epn_width-1)=tlb_htw_req0_tag_q(tagpos_epn to tagpos_epn+epn_width-1) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_4KB) or + (htw_tag3_q(tagpos_epn to tagpos_epn+epn_width-5)=tlb_htw_req0_tag_q(tagpos_epn to tagpos_epn+epn_width-5) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_64KB) or + (htw_tag3_q(tagpos_epn to tagpos_epn+epn_width-9)=tlb_htw_req0_tag_q(tagpos_epn to tagpos_epn+epn_width-9) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1MB) or + (htw_tag3_q(tagpos_epn to tagpos_epn+epn_width-13)=tlb_htw_req0_tag_q(tagpos_epn to tagpos_epn+epn_width-13) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_16MB) or + (htw_tag3_q(tagpos_epn to tagpos_epn+epn_width-19)=tlb_htw_req0_tag_q(tagpos_epn to tagpos_epn+epn_width-19) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1GB) + else '0'; +-- global match ignores certain upper epn bits that are not tranferred over bus +-- fix me!! use various upper nibbles dependent on pgsize and mmucr1.tlbi_msb +htw_resv0_tag3_epn_glob_match <= '1' when (htw_tag3_q(tagpos_epn+31 to tagpos_epn+epn_width-1)=tlb_htw_req0_tag_q(tagpos_epn+31 to tagpos_epn+epn_width-1) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_4KB) or + (htw_tag3_q(tagpos_epn+31 to tagpos_epn+epn_width-5)=tlb_htw_req0_tag_q(tagpos_epn+31 to tagpos_epn+epn_width-5) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_64KB) or + (htw_tag3_q(tagpos_epn+31 to tagpos_epn+epn_width-9)=tlb_htw_req0_tag_q(tagpos_epn+31 to tagpos_epn+epn_width-9) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1MB) or + (htw_tag3_q(tagpos_epn+31 to tagpos_epn+epn_width-13)=tlb_htw_req0_tag_q(tagpos_epn+31 to tagpos_epn+epn_width-13) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_16MB) or + (htw_tag3_q(tagpos_epn+31 to tagpos_epn+epn_width-19)=tlb_htw_req0_tag_q(tagpos_epn+31 to tagpos_epn+epn_width-19) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1GB) + else '0'; +htw_resv1_tag3_lpid_match <= '1' when (htw_tag3_q(tagpos_lpid to tagpos_lpid+lpid_width-1)=tlb_htw_req1_tag_q(tagpos_lpid to tagpos_lpid+lpid_width-1)) else '0'; +htw_resv1_tag3_pid_match <= '1' when (htw_tag3_q(tagpos_pid to tagpos_pid+pid_width-1)=tlb_htw_req1_tag_q(tagpos_pid to tagpos_pid+pid_width-1)) else '0'; +htw_resv1_tag3_as_match <= '1' when (htw_tag3_q(tagpos_as)=tlb_htw_req1_tag_q(tagpos_as)) else '0'; +htw_resv1_tag3_gs_match <= '1' when (htw_tag3_q(tagpos_gs)=tlb_htw_req1_tag_q(tagpos_gs)) else '0'; +htw_resv1_tag3_epn_loc_match <= '1' when (htw_tag3_q(tagpos_epn to tagpos_epn+epn_width-1)=tlb_htw_req1_tag_q(tagpos_epn to tagpos_epn+epn_width-1) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_4KB) or + (htw_tag3_q(tagpos_epn to tagpos_epn+epn_width-5)=tlb_htw_req1_tag_q(tagpos_epn to tagpos_epn+epn_width-5) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_64KB) or + (htw_tag3_q(tagpos_epn to tagpos_epn+epn_width-9)=tlb_htw_req1_tag_q(tagpos_epn to tagpos_epn+epn_width-9) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1MB) or + (htw_tag3_q(tagpos_epn to tagpos_epn+epn_width-13)=tlb_htw_req1_tag_q(tagpos_epn to tagpos_epn+epn_width-13) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_16MB) or + (htw_tag3_q(tagpos_epn to tagpos_epn+epn_width-19)=tlb_htw_req1_tag_q(tagpos_epn to tagpos_epn+epn_width-19) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1GB) + else '0'; +-- global match ignores certain upper epn bits that are not tranferred over bus +-- fix me!! use various upper nibbles dependent on pgsize and mmucr1.tlbi_msb +htw_resv1_tag3_epn_glob_match <= '1' when (htw_tag3_q(tagpos_epn+31 to tagpos_epn+epn_width-1)=tlb_htw_req1_tag_q(tagpos_epn+31 to tagpos_epn+epn_width-1) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_4KB) or + (htw_tag3_q(tagpos_epn+31 to tagpos_epn+epn_width-5)=tlb_htw_req1_tag_q(tagpos_epn+31 to tagpos_epn+epn_width-5) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_64KB) or + (htw_tag3_q(tagpos_epn+31 to tagpos_epn+epn_width-9)=tlb_htw_req1_tag_q(tagpos_epn+31 to tagpos_epn+epn_width-9) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1MB) or + (htw_tag3_q(tagpos_epn+31 to tagpos_epn+epn_width-13)=tlb_htw_req1_tag_q(tagpos_epn+31 to tagpos_epn+epn_width-13) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_16MB) or + (htw_tag3_q(tagpos_epn+31 to tagpos_epn+epn_width-19)=tlb_htw_req1_tag_q(tagpos_epn+31 to tagpos_epn+epn_width-19) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1GB) + else '0'; +htw_resv2_tag3_lpid_match <= '1' when (htw_tag3_q(tagpos_lpid to tagpos_lpid+lpid_width-1)=tlb_htw_req2_tag_q(tagpos_lpid to tagpos_lpid+lpid_width-1)) else '0'; +htw_resv2_tag3_pid_match <= '1' when (htw_tag3_q(tagpos_pid to tagpos_pid+pid_width-1)=tlb_htw_req2_tag_q(tagpos_pid to tagpos_pid+pid_width-1)) else '0'; +htw_resv2_tag3_as_match <= '1' when (htw_tag3_q(tagpos_as)=tlb_htw_req2_tag_q(tagpos_as)) else '0'; +htw_resv2_tag3_gs_match <= '1' when (htw_tag3_q(tagpos_gs)=tlb_htw_req2_tag_q(tagpos_gs)) else '0'; +htw_resv2_tag3_epn_loc_match <= '1' when (htw_tag3_q(tagpos_epn to tagpos_epn+epn_width-1)=tlb_htw_req2_tag_q(tagpos_epn to tagpos_epn+epn_width-1) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_4KB) or + (htw_tag3_q(tagpos_epn to tagpos_epn+epn_width-5)=tlb_htw_req2_tag_q(tagpos_epn to tagpos_epn+epn_width-5) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_64KB) or + (htw_tag3_q(tagpos_epn to tagpos_epn+epn_width-9)=tlb_htw_req2_tag_q(tagpos_epn to tagpos_epn+epn_width-9) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1MB) or + (htw_tag3_q(tagpos_epn to tagpos_epn+epn_width-13)=tlb_htw_req2_tag_q(tagpos_epn to tagpos_epn+epn_width-13) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_16MB) or + (htw_tag3_q(tagpos_epn to tagpos_epn+epn_width-19)=tlb_htw_req2_tag_q(tagpos_epn to tagpos_epn+epn_width-19) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1GB) + else '0'; +-- global match ignores certain upper epn bits that are not tranferred over bus +-- fix me!! use various upper nibbles dependent on pgsize and mmucr1.tlbi_msb +htw_resv2_tag3_epn_glob_match <= '1' when (htw_tag3_q(tagpos_epn+31 to tagpos_epn+epn_width-1)=tlb_htw_req2_tag_q(tagpos_epn+31 to tagpos_epn+epn_width-1) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_4KB) or + (htw_tag3_q(tagpos_epn+31 to tagpos_epn+epn_width-5)=tlb_htw_req2_tag_q(tagpos_epn+31 to tagpos_epn+epn_width-5) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_64KB) or + (htw_tag3_q(tagpos_epn+31 to tagpos_epn+epn_width-9)=tlb_htw_req2_tag_q(tagpos_epn+31 to tagpos_epn+epn_width-9) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1MB) or + (htw_tag3_q(tagpos_epn+31 to tagpos_epn+epn_width-13)=tlb_htw_req2_tag_q(tagpos_epn+31 to tagpos_epn+epn_width-13) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_16MB) or + (htw_tag3_q(tagpos_epn+31 to tagpos_epn+epn_width-19)=tlb_htw_req2_tag_q(tagpos_epn+31 to tagpos_epn+epn_width-19) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1GB) + else '0'; +htw_resv3_tag3_lpid_match <= '1' when (htw_tag3_q(tagpos_lpid to tagpos_lpid+lpid_width-1)=tlb_htw_req3_tag_q(tagpos_lpid to tagpos_lpid+lpid_width-1)) else '0'; +htw_resv3_tag3_pid_match <= '1' when (htw_tag3_q(tagpos_pid to tagpos_pid+pid_width-1)=tlb_htw_req3_tag_q(tagpos_pid to tagpos_pid+pid_width-1)) else '0'; +htw_resv3_tag3_as_match <= '1' when (htw_tag3_q(tagpos_as)=tlb_htw_req3_tag_q(tagpos_as)) else '0'; +htw_resv3_tag3_gs_match <= '1' when (htw_tag3_q(tagpos_gs)=tlb_htw_req3_tag_q(tagpos_gs)) else '0'; +htw_resv3_tag3_epn_loc_match <= '1' when (htw_tag3_q(tagpos_epn to tagpos_epn+epn_width-1)=tlb_htw_req3_tag_q(tagpos_epn to tagpos_epn+epn_width-1) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_4KB) or + (htw_tag3_q(tagpos_epn to tagpos_epn+epn_width-5)=tlb_htw_req3_tag_q(tagpos_epn to tagpos_epn+epn_width-5) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_64KB) or + (htw_tag3_q(tagpos_epn to tagpos_epn+epn_width-9)=tlb_htw_req3_tag_q(tagpos_epn to tagpos_epn+epn_width-9) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1MB) or + (htw_tag3_q(tagpos_epn to tagpos_epn+epn_width-13)=tlb_htw_req3_tag_q(tagpos_epn to tagpos_epn+epn_width-13) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_16MB) or + (htw_tag3_q(tagpos_epn to tagpos_epn+epn_width-19)=tlb_htw_req3_tag_q(tagpos_epn to tagpos_epn+epn_width-19) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1GB) + else '0'; +-- global match ignores certain upper epn bits that are not tranferred over bus +-- fix me!! use various upper nibbles dependent on pgsize and mmucr1.tlbi_msb +htw_resv3_tag3_epn_glob_match <= '1' when (htw_tag3_q(tagpos_epn+31 to tagpos_epn+epn_width-1)=tlb_htw_req3_tag_q(tagpos_epn+31 to tagpos_epn+epn_width-1) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_4KB) or + (htw_tag3_q(tagpos_epn+31 to tagpos_epn+epn_width-5)=tlb_htw_req3_tag_q(tagpos_epn+31 to tagpos_epn+epn_width-5) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_64KB) or + (htw_tag3_q(tagpos_epn+31 to tagpos_epn+epn_width-9)=tlb_htw_req3_tag_q(tagpos_epn+31 to tagpos_epn+epn_width-9) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1MB) or + (htw_tag3_q(tagpos_epn+31 to tagpos_epn+epn_width-13)=tlb_htw_req3_tag_q(tagpos_epn+31 to tagpos_epn+epn_width-13) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_16MB) or + (htw_tag3_q(tagpos_epn+31 to tagpos_epn+epn_width-19)=tlb_htw_req3_tag_q(tagpos_epn+31 to tagpos_epn+epn_width-19) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1GB) + else '0'; +pte0_score_act <= (or_reduce(pte0_seq_q) or or_reduce(htw_seq_q) or mmucr2_act_override) and xu_mm_ccr2_notlb_b; +pte0_score_ptr_d <= htw_lsuptr_q when pte0_seq_score_load='1' + else pte0_score_ptr_q; +pte0_score_cl_offset_d <= pte_ra_0(58 to 60) when pte0_seq_score_load='1' and htw_lsuptr_q="00" + else pte_ra_1(58 to 60) when pte0_seq_score_load='1' and htw_lsuptr_q="01" + else pte_ra_2(58 to 60) when pte0_seq_score_load='1' and htw_lsuptr_q="10" + else pte_ra_3(58 to 60) when pte0_seq_score_load='1' and htw_lsuptr_q="11" + else pte0_score_cl_offset_q; +pte0_score_ibit_d <= tlb_htw_req0_way_q(waypos_wimge+1) when pte0_seq_score_load='1' and htw_lsuptr_q="00" + else tlb_htw_req1_way_q(waypos_wimge+1) when pte0_seq_score_load='1' and htw_lsuptr_q="01" + else tlb_htw_req2_way_q(waypos_wimge+1) when pte0_seq_score_load='1' and htw_lsuptr_q="10" + else tlb_htw_req3_way_q(waypos_wimge+1) when pte0_seq_score_load='1' and htw_lsuptr_q="11" + else pte0_score_ibit_q; +pte0_score_pending_d <= '1' when pte0_seq_score_load='1' + else '0' when pte0_seq_score_done='1' + else pte0_score_pending_q; +-- 4 quadword data beats being returned; entire CL repeated if any beat has ecc error +-- ...beats need to be set regardless of ecc present..ecc and any qw happen simultaneously +pte0_score_qwbeat_d(0) <= '0' when pte0_seq_score_load='1' or pte0_seq_data_retry='1' + else '1' when (pte0_score_pending_q='1' and reld_data_vld_tp2_q='1' and reld_ditc_tp2_q='0' + and reld_core_tag_tp2_q=Core_Tag0_Value and reld_qw_tp2_q="00") + else pte0_score_qwbeat_q(0); +pte0_score_qwbeat_d(1) <= '0' when pte0_seq_score_load='1' or pte0_seq_data_retry='1' + else '1' when (pte0_score_pending_q='1' and reld_data_vld_tp2_q='1' and reld_ditc_tp2_q='0' + and reld_core_tag_tp2_q=Core_Tag0_Value and reld_qw_tp2_q="01") + else pte0_score_qwbeat_q(1); +pte0_score_qwbeat_d(2) <= '0' when pte0_seq_score_load='1' or pte0_seq_data_retry='1' + else '1' when (pte0_score_pending_q='1' and reld_data_vld_tp2_q='1' and reld_ditc_tp2_q='0' + and reld_core_tag_tp2_q=Core_Tag0_Value and reld_qw_tp2_q="10") + else pte0_score_qwbeat_q(2); +pte0_score_qwbeat_d(3) <= '0' when pte0_seq_score_load='1' or pte0_seq_data_retry='1' + else '1' when (pte0_score_pending_q='1' and reld_data_vld_tp2_q='1' and reld_ditc_tp2_q='0' + and reld_core_tag_tp2_q=Core_Tag0_Value and reld_qw_tp2_q="11") + else pte0_score_qwbeat_q(3); +-- ecc error detection: bit0=ECC, bit1=UE, bit2=retry +pte0_score_error_d(0) <= '0' when pte0_seq_score_load='1' + else '1' when (pte0_score_pending_q='1' and reld_data_vld_tp2_q='1' and reld_ditc_tp2_q='0' + and reld_core_tag_tp2_q=Core_Tag0_Value + and reld_ecc_err_tp2_q='1') + else pte0_score_error_q(0); +pte0_score_error_d(1) <= '0' when pte0_seq_score_load='1' + else '1' when (pte0_score_pending_q='1' and reld_data_vld_tp2_q='1' and reld_ditc_tp2_q='0' + and reld_core_tag_tp2_q=Core_Tag0_Value + and reld_ecc_err_ue_tp2_q='1') + else pte0_score_error_q(1); +pte0_score_error_d(2) <= '0' when pte0_seq_score_load='1' + else '1' when pte0_seq_data_retry='1' + else pte0_score_error_q(2); +pte0_score_dataval_d <= '0' when pte0_seq_score_load='1' or pte0_seq_data_retry='1' + else '1' when (pte0_score_pending_q='1' and reld_data_vld_tp2_q='1' and reld_ditc_tp2_q='0' + and reld_crit_qw_tp2_q='1' and reld_qw_tp2_q=pte0_score_cl_offset_q(58 to 59) + and reld_core_tag_tp2_q=Core_Tag0_Value) + else pte0_score_dataval_q; +pte1_score_act <= (or_reduce(pte1_seq_q) or or_reduce(htw_seq_q) or mmucr2_act_override) and xu_mm_ccr2_notlb_b; +pte1_score_ptr_d <= htw_lsuptr_q when pte1_seq_score_load='1' + else pte1_score_ptr_q; +pte1_score_cl_offset_d <= pte_ra_0(58 to 60) when pte1_seq_score_load='1' and htw_lsuptr_q="00" + else pte_ra_1(58 to 60) when pte1_seq_score_load='1' and htw_lsuptr_q="01" + else pte_ra_2(58 to 60) when pte1_seq_score_load='1' and htw_lsuptr_q="10" + else pte_ra_3(58 to 60) when pte1_seq_score_load='1' and htw_lsuptr_q="11" + else pte1_score_cl_offset_q; +pte1_score_ibit_d <= tlb_htw_req0_way_q(waypos_wimge+1) when pte1_seq_score_load='1' and htw_lsuptr_q="00" + else tlb_htw_req1_way_q(waypos_wimge+1) when pte1_seq_score_load='1' and htw_lsuptr_q="01" + else tlb_htw_req2_way_q(waypos_wimge+1) when pte1_seq_score_load='1' and htw_lsuptr_q="10" + else tlb_htw_req3_way_q(waypos_wimge+1) when pte1_seq_score_load='1' and htw_lsuptr_q="11" + else pte1_score_ibit_q; +pte1_score_pending_d <= '1' when pte1_seq_score_load='1' + else '0' when pte1_seq_score_done='1' + else pte1_score_pending_q; +-- 4 quadword data beats being returned; entire CL repeated if any beat has ecc error +-- ...beats need to be set regardless of ecc present..ecc and any qw happen simultaneously +pte1_score_qwbeat_d(0) <= '0' when pte1_seq_score_load='1' or pte1_seq_data_retry='1' + else '1' when (pte1_score_pending_q='1' and reld_data_vld_tp2_q='1' and reld_ditc_tp2_q='0' + and reld_core_tag_tp2_q=Core_Tag1_Value and reld_qw_tp2_q="00") + else pte1_score_qwbeat_q(0); +pte1_score_qwbeat_d(1) <= '0' when pte1_seq_score_load='1' or pte1_seq_data_retry='1' + else '1' when (pte1_score_pending_q='1' and reld_data_vld_tp2_q='1' and reld_ditc_tp2_q='0' + and reld_core_tag_tp2_q=Core_Tag1_Value and reld_qw_tp2_q="01") + else pte1_score_qwbeat_q(1); +pte1_score_qwbeat_d(2) <= '0' when pte1_seq_score_load='1' or pte1_seq_data_retry='1' + else '1' when (pte1_score_pending_q='1' and reld_data_vld_tp2_q='1' and reld_ditc_tp2_q='0' + and reld_core_tag_tp2_q=Core_Tag1_Value and reld_qw_tp2_q="10") + else pte1_score_qwbeat_q(2); +pte1_score_qwbeat_d(3) <= '0' when pte1_seq_score_load='1' or pte1_seq_data_retry='1' + else '1' when (pte1_score_pending_q='1' and reld_data_vld_tp2_q='1' and reld_ditc_tp2_q='0' + and reld_core_tag_tp2_q=Core_Tag1_Value and reld_qw_tp2_q="11") + else pte1_score_qwbeat_q(3); +-- ecc error detection: bit0=ECC, bit1=UE, bit2=retry +pte1_score_error_d(0) <= '0' when pte1_seq_score_load='1' + else '1' when (pte1_score_pending_q='1' and reld_data_vld_tp2_q='1' and reld_ditc_tp2_q='0' + and reld_core_tag_tp2_q=Core_Tag1_Value + and reld_ecc_err_tp2_q='1') + else pte1_score_error_q(0); +pte1_score_error_d(1) <= '0' when pte1_seq_score_load='1' + else '1' when (pte1_score_pending_q='1' and reld_data_vld_tp2_q='1' and reld_ditc_tp2_q='0' + and reld_core_tag_tp2_q=Core_Tag1_Value + and reld_ecc_err_ue_tp2_q='1') + else pte1_score_error_q(1); +pte1_score_error_d(2) <= '0' when pte1_seq_score_load='1' + else '1' when pte1_seq_data_retry='1' + else pte1_score_error_q(2); +pte1_score_dataval_d <= '0' when pte1_seq_score_load='1' or pte1_seq_data_retry='1' + else '1' when (pte1_score_pending_q='1' and reld_data_vld_tp2_q='1' and reld_ditc_tp2_q='0' + and reld_crit_qw_tp2_q='1' and reld_qw_tp2_q=pte1_score_cl_offset_q(58 to 59) + and reld_core_tag_tp2_q=Core_Tag1_Value) + else pte1_score_dataval_q; +-- pointers: +-- htw_inptr: tlb to htw incoming request queue pointer, 4 total +-- htw_lsuptr: htw to lru outgoing request queue pointer, 4 total +-- pte_load_ptr: pte machine pointer next to load, 2 total +-- ptereload_ptr: pte to tlb data reload select, 2 total +htw_inptr_d <= "01" when htw_inptr_q="00" and tlb_htw_req0_valid_q='0' and tlb_htw_req1_valid_q='0' and tlb_htw_req_valid='1' + else "10" when htw_inptr_q="00" and tlb_htw_req0_valid_q='0' and tlb_htw_req1_valid_q='1' and tlb_htw_req2_valid_q='0' and tlb_htw_req_valid='1' + else "11" when htw_inptr_q="00" and tlb_htw_req0_valid_q='0' and tlb_htw_req1_valid_q='1' and tlb_htw_req2_valid_q='1' and tlb_htw_req3_valid_q='0' and tlb_htw_req_valid='1' + else "10" when htw_inptr_q="01" and tlb_htw_req1_valid_q='0' and tlb_htw_req2_valid_q='0' and tlb_htw_req_valid='1' + else "11" when htw_inptr_q="01" and tlb_htw_req1_valid_q='0' and tlb_htw_req2_valid_q='1' and tlb_htw_req3_valid_q='0' and tlb_htw_req_valid='1' + else "00" when htw_inptr_q="01" and tlb_htw_req1_valid_q='0' and tlb_htw_req2_valid_q='1' and tlb_htw_req3_valid_q='1' and tlb_htw_req0_valid_q='0' and tlb_htw_req_valid='1' + else "11" when htw_inptr_q="10" and tlb_htw_req2_valid_q='0' and tlb_htw_req3_valid_q='0' and tlb_htw_req_valid='1' + else "00" when htw_inptr_q="10" and tlb_htw_req2_valid_q='0' and tlb_htw_req3_valid_q='1' and tlb_htw_req0_valid_q='0' and tlb_htw_req_valid='1' + else "01" when htw_inptr_q="10" and tlb_htw_req2_valid_q='0' and tlb_htw_req3_valid_q='1' and tlb_htw_req0_valid_q='1' and tlb_htw_req1_valid_q='0' and tlb_htw_req_valid='1' + else "00" when htw_inptr_q="11" and tlb_htw_req3_valid_q='0' and tlb_htw_req0_valid_q='0' and tlb_htw_req_valid='1' + else "01" when htw_inptr_q="11" and tlb_htw_req3_valid_q='0' and tlb_htw_req0_valid_q='1' and tlb_htw_req1_valid_q='0' and tlb_htw_req_valid='1' + else "10" when htw_inptr_q="11" and tlb_htw_req3_valid_q='0' and tlb_htw_req0_valid_q='1' and tlb_htw_req1_valid_q='1' and tlb_htw_req2_valid_q='0' and tlb_htw_req_valid='1' + else pte0_score_ptr_q when ptereload_ptr_q='0' and ptereload_req_taken='1' + else pte1_score_ptr_q when ptereload_ptr_q='1' and ptereload_req_taken='1' + else htw_inptr_q; +htw_lsuptr_d <= "01" when htw_lsuptr_q="00" and tlb_htw_req_valid_vec(0)='0' and tlb_htw_req_valid_vec(1)='1' + else "10" when htw_lsuptr_q="00" and tlb_htw_req_valid_vec(0)='0' and tlb_htw_req_valid_vec(1)='0' and tlb_htw_req_valid_vec(2)='1' + else "11" when htw_lsuptr_q="00" and tlb_htw_req_valid_vec(0)='0' and tlb_htw_req_valid_vec(1)='0' and tlb_htw_req_valid_vec(2)='0' and tlb_htw_req_valid_vec(3)='1' + else "10" when htw_lsuptr_q="01" and tlb_htw_req_valid_vec(1)='0' and tlb_htw_req_valid_vec(2)='1' + else "11" when htw_lsuptr_q="01" and tlb_htw_req_valid_vec(1)='0' and tlb_htw_req_valid_vec(2)='0' and tlb_htw_req_valid_vec(3)='1' + else "00" when htw_lsuptr_q="01" and tlb_htw_req_valid_vec(1)='0' and tlb_htw_req_valid_vec(2)='0' and tlb_htw_req_valid_vec(3)='0' and tlb_htw_req_valid_vec(0)='1' + else "11" when htw_lsuptr_q="10" and tlb_htw_req_valid_vec(2)='0' and tlb_htw_req_valid_vec(3)='1' + else "00" when htw_lsuptr_q="10" and tlb_htw_req_valid_vec(2)='0' and tlb_htw_req_valid_vec(3)='0' and tlb_htw_req_valid_vec(0)='1' + else "01" when htw_lsuptr_q="10" and tlb_htw_req_valid_vec(2)='0' and tlb_htw_req_valid_vec(3)='0' and tlb_htw_req_valid_vec(0)='0' and tlb_htw_req_valid_vec(1)='1' + else "00" when htw_lsuptr_q="11" and tlb_htw_req_valid_vec(3)='0' and tlb_htw_req_valid_vec(0)='1' + else "01" when htw_lsuptr_q="11" and tlb_htw_req_valid_vec(3)='0' and tlb_htw_req_valid_vec(0)='0' and tlb_htw_req_valid_vec(1)='1' + else "10" when htw_lsuptr_q="11" and tlb_htw_req_valid_vec(3)='0' and tlb_htw_req_valid_vec(0)='0' and tlb_htw_req_valid_vec(1)='0' and tlb_htw_req_valid_vec(2)='1' + else htw_lsuptr_q; +tlb_htw_req_valid_notpend_vec <= (tlb_htw_req0_valid_q and not tlb_htw_req0_pending_q) & + (tlb_htw_req1_valid_q and not tlb_htw_req1_pending_q) & + (tlb_htw_req2_valid_q and not tlb_htw_req2_pending_q) & + (tlb_htw_req3_valid_q and not tlb_htw_req3_pending_q); +htw_lsuptr_alt_d <= "01" when htw_lsuptr_q="00" and tlb_htw_req_valid_notpend_vec(0)='1' and htw_lsu_req_taken='1' + else "10" when htw_lsuptr_q="01" and tlb_htw_req_valid_notpend_vec(1)='1' and htw_lsu_req_taken='1' + else "11" when htw_lsuptr_q="10" and tlb_htw_req_valid_notpend_vec(2)='1' and htw_lsu_req_taken='1' + else "00" when htw_lsuptr_q="11" and tlb_htw_req_valid_notpend_vec(3)='1' and htw_lsu_req_taken='1' + else "01" when htw_lsuptr_q="00" and tlb_htw_req_valid_notpend_vec(0)='0' and tlb_htw_req_valid_notpend_vec(1)='1' + else "10" when htw_lsuptr_q="00" and tlb_htw_req_valid_notpend_vec(0)='0' and tlb_htw_req_valid_notpend_vec(1)='0' and tlb_htw_req_valid_notpend_vec(2)='1' + else "11" when htw_lsuptr_q="00" and tlb_htw_req_valid_notpend_vec(0)='0' and tlb_htw_req_valid_notpend_vec(1)='0' and tlb_htw_req_valid_notpend_vec(2)='0' and tlb_htw_req_valid_notpend_vec(3)='1' + else "10" when htw_lsuptr_q="01" and tlb_htw_req_valid_notpend_vec(1)='0' and tlb_htw_req_valid_notpend_vec(2)='1' + else "11" when htw_lsuptr_q="01" and tlb_htw_req_valid_notpend_vec(1)='0' and tlb_htw_req_valid_notpend_vec(2)='0' and tlb_htw_req_valid_notpend_vec(3)='1' + else "00" when htw_lsuptr_q="01" and tlb_htw_req_valid_notpend_vec(1)='0' and tlb_htw_req_valid_notpend_vec(2)='0' and tlb_htw_req_valid_notpend_vec(3)='0' and tlb_htw_req_valid_notpend_vec(0)='1' + else "11" when htw_lsuptr_q="10" and tlb_htw_req_valid_notpend_vec(2)='0' and tlb_htw_req_valid_notpend_vec(3)='1' + else "00" when htw_lsuptr_q="10" and tlb_htw_req_valid_notpend_vec(2)='0' and tlb_htw_req_valid_notpend_vec(3)='0' and tlb_htw_req_valid_notpend_vec(0)='1' + else "01" when htw_lsuptr_q="10" and tlb_htw_req_valid_notpend_vec(2)='0' and tlb_htw_req_valid_notpend_vec(3)='0' and tlb_htw_req_valid_notpend_vec(0)='0' and tlb_htw_req_valid_notpend_vec(1)='1' + else "00" when htw_lsuptr_q="11" and tlb_htw_req_valid_notpend_vec(3)='0' and tlb_htw_req_valid_notpend_vec(0)='1' + else "01" when htw_lsuptr_q="11" and tlb_htw_req_valid_notpend_vec(3)='0' and tlb_htw_req_valid_notpend_vec(0)='0' and tlb_htw_req_valid_notpend_vec(1)='1' + else "10" when htw_lsuptr_q="11" and tlb_htw_req_valid_notpend_vec(3)='0' and tlb_htw_req_valid_notpend_vec(0)='0' and tlb_htw_req_valid_notpend_vec(1)='0' and tlb_htw_req_valid_notpend_vec(2)='1' + else htw_lsuptr_q; +pte_load_ptr_d <= '1' when ptereload_ptr_q='1' and pte1_score_pending_q='1' and pte0_score_pending_d='1' and ptereload_req_taken='1' + else '0' when ptereload_ptr_q='0' and pte0_score_pending_q='1' and pte1_score_pending_d='1' and ptereload_req_taken='1' + else '1' when pte_load_ptr_q='0' and pte0_seq_score_load='1' and pte1_score_pending_q='0' + else '0' when pte_load_ptr_q='1' and pte1_seq_score_load='1' and pte0_score_pending_q='0' + else pte_load_ptr_q; +ptereload_ptr_d <= '1' when ptereload_ptr_q='0' and ptereload_req_taken='1' + else '1' when ptereload_ptr_q='0' and pte0_reload_req_valid='0' and pte1_reload_req_valid='1' + else '0' when ptereload_ptr_q='1' and ptereload_req_taken='1' + else '0' when ptereload_ptr_q='1' and pte0_reload_req_valid='1' and pte1_reload_req_valid='0' + else ptereload_ptr_q; +-- 0=tlbivax_op, 1=tlbi_complete, 2=mmu read with core_tag=01100, 3=mmu read with core_tag=01101 +htw_lsu_ttype_d <= "11" when (pte_load_ptr_q='1' and htw_seq_load_pteaddr='1') + else "10" when htw_seq_load_pteaddr='1' + else htw_lsu_ttype_q; +htw_lsu_thdid_d <= tlb_htw_req0_tag_q(tagpos_thdid to tagpos_thdid+thdid_width-1) when htw_lsuptr_q="00" and tlb_htw_req0_valid_q='1' and htw_seq_load_pteaddr='1' + else tlb_htw_req1_tag_q(tagpos_thdid to tagpos_thdid+thdid_width-1) when htw_lsuptr_q="01" and tlb_htw_req1_valid_q='1' and htw_seq_load_pteaddr='1' + else tlb_htw_req2_tag_q(tagpos_thdid to tagpos_thdid+thdid_width-1) when htw_lsuptr_q="10" and tlb_htw_req2_valid_q='1' and htw_seq_load_pteaddr='1' + else tlb_htw_req3_tag_q(tagpos_thdid to tagpos_thdid+thdid_width-1) when htw_lsuptr_q="11" and tlb_htw_req3_valid_q='1' and htw_seq_load_pteaddr='1' + else htw_lsu_thdid_q; +htw_lsu_wimge_d <= tlb_htw_req0_way_q(waypos_wimge to waypos_wimge+4) when htw_lsuptr_q="00" and tlb_htw_req0_valid_q='1' and htw_seq_load_pteaddr='1' + else tlb_htw_req1_way_q(waypos_wimge to waypos_wimge+4) when htw_lsuptr_q="01" and tlb_htw_req1_valid_q='1' and htw_seq_load_pteaddr='1' + else tlb_htw_req2_way_q(waypos_wimge to waypos_wimge+4) when htw_lsuptr_q="10" and tlb_htw_req2_valid_q='1' and htw_seq_load_pteaddr='1' + else tlb_htw_req3_way_q(waypos_wimge to waypos_wimge+4) when htw_lsuptr_q="11" and tlb_htw_req3_valid_q='1' and htw_seq_load_pteaddr='1' + else htw_lsu_wimge_q; +htw_lsu_u_d <= tlb_htw_req0_way_q(waypos_ubits to waypos_ubits+3) when htw_lsuptr_q="00" and tlb_htw_req0_valid_q='1' and htw_seq_load_pteaddr='1' + else tlb_htw_req1_way_q(waypos_ubits to waypos_ubits+3) when htw_lsuptr_q="01" and tlb_htw_req1_valid_q='1' and htw_seq_load_pteaddr='1' + else tlb_htw_req2_way_q(waypos_ubits to waypos_ubits+3) when htw_lsuptr_q="10" and tlb_htw_req2_valid_q='1' and htw_seq_load_pteaddr='1' + else tlb_htw_req3_way_q(waypos_ubits to waypos_ubits+3) when htw_lsuptr_q="11" and tlb_htw_req3_valid_q='1' and htw_seq_load_pteaddr='1' + else htw_lsu_u_q; +htw_lsu_addr_d <= pte_ra_0 when htw_lsuptr_q="00" and tlb_htw_req0_valid_q='1' and htw_seq_load_pteaddr='1' + else pte_ra_1 when htw_lsuptr_q="01" and tlb_htw_req1_valid_q='1' and htw_seq_load_pteaddr='1' + else pte_ra_2 when htw_lsuptr_q="10" and tlb_htw_req2_valid_q='1' and htw_seq_load_pteaddr='1' + else pte_ra_3 when htw_lsuptr_q="11" and tlb_htw_req3_valid_q='1' and htw_seq_load_pteaddr='1' + else htw_lsu_addr_q; +htw_lsu_act <= (or_reduce(htw_seq_q) or mmucr2_act_override) and xu_mm_ccr2_notlb_b; +htw_lsu_thdid <= htw_lsu_thdid_q; +htw_dbg_lsu_thdid(0) <= htw_lsu_thdid_q(2) or htw_lsu_thdid_q(3); +htw_dbg_lsu_thdid(1) <= htw_lsu_thdid_q(1) or htw_lsu_thdid_q(3); +htw_lsu_ttype <= htw_lsu_ttype_q; +htw_lsu_wimge <= htw_lsu_wimge_q; +htw_lsu_u <= htw_lsu_u_q; +htw_lsu_addr <= htw_lsu_addr_q; +-- L2 data reload stages +-- t minus 2 phase +reld_core_tag_tm1_d <= an_ac_reld_core_tag; +reld_qw_tm1_d <= an_ac_reld_qw; +reld_crit_qw_tm1_d <= an_ac_reld_crit_qw; +reld_ditc_tm1_d <= an_ac_reld_ditc; +reld_data_vld_tm1_d <= an_ac_reld_data_vld; +-- t minus 1 phase +reld_core_tag_t_d <= reld_core_tag_tm1_q; +reld_qw_t_d <= reld_qw_tm1_q; +reld_crit_qw_t_d <= reld_crit_qw_tm1_q; +reld_ditc_t_d <= reld_ditc_tm1_q; +reld_data_vld_t_d <= reld_data_vld_tm1_q; +pte0_reld_for_me_tm1 <= '1' when (reld_data_vld_tm1_q='1' and reld_ditc_tm1_q='0' and reld_crit_qw_tm1_q='1' + and reld_qw_tm1_q=pte0_score_cl_offset_q(58 to 59) and reld_core_tag_tm1_q=Core_Tag0_Value) + else '0'; +pte1_reld_for_me_tm1 <= '1' when (reld_data_vld_tm1_q='1' and reld_ditc_tm1_q='0' and reld_crit_qw_tm1_q='1' + and reld_qw_tm1_q=pte1_score_cl_offset_q(58 to 59) and reld_core_tag_tm1_q=Core_Tag1_Value) + else '0'; +-- t phase +reld_core_tag_tp1_d <= reld_core_tag_t_q; +reld_qw_tp1_d <= reld_qw_t_q; +reld_crit_qw_tp1_d <= reld_crit_qw_t_q; +reld_ditc_tp1_d <= reld_ditc_t_q; +reld_data_vld_tp1_d <= reld_data_vld_t_q; +reld_data_tp1_d <= an_ac_reld_data; +-- t plus 1 phase +reld_core_tag_tp2_d <= reld_core_tag_tp1_q; +reld_qw_tp2_d <= reld_qw_tp1_q; +reld_crit_qw_tp2_d <= reld_crit_qw_tp1_q; +reld_ditc_tp2_d <= reld_ditc_tp1_q; +reld_data_vld_tp2_d <= reld_data_vld_tp1_q; +reld_data_tp2_d <= reld_data_tp1_q; +reld_ecc_err_tp2_d <= an_ac_reld_ecc_err; +reld_ecc_err_ue_tp2_d <= an_ac_reld_ecc_err_ue; +-- t plus 2 phase +pte0_reld_for_me_tp2 <= '1' when (reld_data_vld_tp2_q='1' and reld_ditc_tp2_q='0' and reld_crit_qw_tp2_q='1' + and reld_qw_tp2_q=pte0_score_cl_offset_q(58 to 59) and reld_core_tag_tp2_q=Core_Tag0_Value) + else '0'; +pte0_reld_data_tp3_d <= reld_data_tp2_q(0 to 63) when (pte0_reld_for_me_tp2='1' and pte0_score_cl_offset_q(60)='0') + else reld_data_tp2_q(64 to 127) when (pte0_reld_for_me_tp2='1' and pte0_score_cl_offset_q(60)='1') + else pte0_reld_data_tp3_q; +pte1_reld_for_me_tp2 <= '1' when (reld_data_vld_tp2_q='1' and reld_ditc_tp2_q='0' and reld_crit_qw_tp2_q='1' + and reld_qw_tp2_q=pte1_score_cl_offset_q(58 to 59) and reld_core_tag_tp2_q=Core_Tag1_Value) + else '0'; +pte1_reld_data_tp3_d <= reld_data_tp2_q(0 to 63) when (pte1_reld_for_me_tp2='1' and pte1_score_cl_offset_q(60)='0') + else reld_data_tp2_q(64 to 127) when (pte1_reld_for_me_tp2='1' and pte1_score_cl_offset_q(60)='1') + else pte1_reld_data_tp3_q; +reld_act <= (or_reduce(pte0_seq_q) or or_reduce(pte1_seq_q) or mmucr2_act_override) and xu_mm_ccr2_notlb_b; +pte0_reld_act <= (or_reduce(pte0_seq_q) or mmucr2_act_override) and xu_mm_ccr2_notlb_b; +pte1_reld_act <= (or_reduce(pte1_seq_q) or mmucr2_act_override) and xu_mm_ccr2_notlb_b; +-- ptereload requests to tlb_ctl +ptereload_req_valid <= '0' when (htw_tag4_clr_resv_q/="0000" or htw_tag5_clr_resv_q/="0000") + else pte1_reload_req_valid when ptereload_ptr_q='1' + else pte0_reload_req_valid; +ptereload_req_tag <= tlb_htw_req1_tag_q when ((ptereload_ptr_q='0' and pte0_score_ptr_q="01") or + (ptereload_ptr_q='1' and pte1_score_ptr_q="01")) + else tlb_htw_req2_tag_q when ((ptereload_ptr_q='0' and pte0_score_ptr_q="10") or + (ptereload_ptr_q='1' and pte1_score_ptr_q="10")) + else tlb_htw_req3_tag_q when ((ptereload_ptr_q='0' and pte0_score_ptr_q="11") or + (ptereload_ptr_q='1' and pte1_score_ptr_q="11")) + else tlb_htw_req0_tag_q; +ptereload_req_pte <= pte1_reld_data_tp3_q when ptereload_ptr_q='1' + else pte0_reld_data_tp3_q; +htw_tag4_clr_resv_terms <= (others => '0'); +htw_dbg_seq_idle <= htw_seq_idle; +htw_dbg_pte0_seq_idle <= pte0_seq_idle; +htw_dbg_pte1_seq_idle <= pte1_seq_idle; +htw_dbg_seq_q <= htw_seq_q; +htw_dbg_inptr_q <= htw_inptr_q; +htw_dbg_pte0_seq_q <= pte0_seq_q; +htw_dbg_pte1_seq_q <= pte1_seq_q; +htw_dbg_ptereload_ptr_q <= ptereload_ptr_q; +htw_dbg_lsuptr_q <= htw_lsuptr_q; +htw_dbg_req_valid_q <= tlb_htw_req0_valid_q & tlb_htw_req1_valid_q & tlb_htw_req2_valid_q & tlb_htw_req3_valid_q; +htw_dbg_resv_valid_vec <= htw_resv_valid_vec; +htw_dbg_tag4_clr_resv_q <= htw_tag4_clr_resv_q; +htw_dbg_tag4_clr_resv_terms <= htw_tag4_clr_resv_terms; +htw_dbg_pte0_score_ptr_q <= pte0_score_ptr_q; +htw_dbg_pte0_score_cl_offset_q <= pte0_score_cl_offset_q; +htw_dbg_pte0_score_error_q <= pte0_score_error_q; +htw_dbg_pte0_score_qwbeat_q <= pte0_score_qwbeat_q; +htw_dbg_pte0_score_pending_q <= pte0_score_pending_q; +htw_dbg_pte0_score_ibit_q <= pte0_score_ibit_q; +htw_dbg_pte0_score_dataval_q <= pte0_score_dataval_q; +htw_dbg_pte0_reld_for_me_tm1 <= pte0_reld_for_me_tm1; +htw_dbg_pte1_score_ptr_q <= pte1_score_ptr_q; +htw_dbg_pte1_score_cl_offset_q <= pte1_score_cl_offset_q; +htw_dbg_pte1_score_error_q <= pte1_score_error_q; +htw_dbg_pte1_score_qwbeat_q <= pte1_score_qwbeat_q; +htw_dbg_pte1_score_pending_q <= pte1_score_pending_q; +htw_dbg_pte1_score_ibit_q <= pte1_score_ibit_q; +htw_dbg_pte1_score_dataval_q <= pte1_score_dataval_q; +htw_dbg_pte1_reld_for_me_tm1 <= pte1_reld_for_me_tm1; +-- unused spare signal assignments +unused_dc(0) <= or_reduce(LCB_DELAY_LCLKR_DC(1 TO 4)); +unused_dc(1) <= or_reduce(LCB_MPW1_DC_B(1 TO 4)); +unused_dc(2) <= PC_FUNC_SL_FORCE; +unused_dc(3) <= PC_FUNC_SL_THOLD_0_B; +unused_dc(4) <= TC_SCAN_DIS_DC_B; +unused_dc(5) <= TC_SCAN_DIAG_DC; +unused_dc(6) <= TC_LBIST_EN_DC; +unused_dc(7) <= or_reduce(TLB_HTW_REQ_TAG(104 TO 105)); +unused_dc(8) <= HTW_TAG3_Q(70); +unused_dc(9) <= HTW_TAG3_Q(73); +unused_dc(10) <= or_reduce(HTW_TAG3_Q(82 TO 85)); +unused_dc(11) <= HTW_TAG3_Q(87); +unused_dc(12) <= or_reduce(HTW_TAG3_Q(98 TO 103)); +unused_dc(13) <= or_reduce(HTW_TAG3_Q(106 TO 109)); +unused_dc(14) <= PTE0_RELD_ENABLE_LO_TP2 or PTE0_RELD_ENABLE_HI_TP2; +unused_dc(15) <= PTE1_RELD_ENABLE_LO_TP2 or PTE1_RELD_ENABLE_HI_TP2; +unused_dc(16 TO 19) <= tlb_htw_req0_pending_q & tlb_htw_req1_pending_q & tlb_htw_req2_pending_q & tlb_htw_req3_pending_q; +unused_dc(20 TO 21) <= htw_lsuptr_alt_d; +----------------------------------------------------------------------- +-- Latches +----------------------------------------------------------------------- +-- tlb request valid latches +tlb_htw_req0_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_htw_req0_valid_offset), + scout => sov_0(tlb_htw_req0_valid_offset), + din => tlb_htw_req0_valid_d, + dout => tlb_htw_req0_valid_q); +-- tlb request pending latches.. this req is loaded into a pte machine +tlb_htw_req0_pending_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_htw_req0_pending_offset), + scout => sov_0(tlb_htw_req0_pending_offset), + din => tlb_htw_req0_pending_d, + dout => tlb_htw_req0_pending_q); +-- tlb request tag latches +tlb_htw_req0_tag_latch: tri_rlmreg_p + generic map (width => tlb_htw_req0_tag_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_htw_req0_tag_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_htw_req0_tag_offset to tlb_htw_req0_tag_offset+tlb_htw_req0_tag_q'length-1), + scout => sov_0(tlb_htw_req0_tag_offset to tlb_htw_req0_tag_offset+tlb_htw_req0_tag_q'length-1), + din => tlb_htw_req0_tag_d, + dout => tlb_htw_req0_tag_q ); +-- tlb request tag latches +tlb_htw_req0_way_latch: tri_rlmreg_p + generic map (width => tlb_htw_req0_way_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(24+0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_htw_req0_way_offset to tlb_htw_req0_way_offset+tlb_htw_req0_way_q'length-1), + scout => sov_0(tlb_htw_req0_way_offset to tlb_htw_req0_way_offset+tlb_htw_req0_way_q'length-1), + din => tlb_htw_req0_way_d, + dout => tlb_htw_req0_way_q ); +-- tlb request valid latches +tlb_htw_req1_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_htw_req1_valid_offset), + scout => sov_0(tlb_htw_req1_valid_offset), + din => tlb_htw_req1_valid_d, + dout => tlb_htw_req1_valid_q); +-- tlb request pending latches.. this req is loaded into a pte machine +tlb_htw_req1_pending_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_htw_req1_pending_offset), + scout => sov_0(tlb_htw_req1_pending_offset), + din => tlb_htw_req1_pending_d, + dout => tlb_htw_req1_pending_q); +-- tlb request tag latches +tlb_htw_req1_tag_latch: tri_rlmreg_p + generic map (width => tlb_htw_req1_tag_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_htw_req1_tag_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_htw_req1_tag_offset to tlb_htw_req1_tag_offset+tlb_htw_req1_tag_q'length-1), + scout => sov_0(tlb_htw_req1_tag_offset to tlb_htw_req1_tag_offset+tlb_htw_req1_tag_q'length-1), + din => tlb_htw_req1_tag_d, + dout => tlb_htw_req1_tag_q ); +-- tlb request tag latches +tlb_htw_req1_way_latch: tri_rlmreg_p + generic map (width => tlb_htw_req1_way_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(24+1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_htw_req1_way_offset to tlb_htw_req1_way_offset+tlb_htw_req1_way_q'length-1), + scout => sov_0(tlb_htw_req1_way_offset to tlb_htw_req1_way_offset+tlb_htw_req1_way_q'length-1), + din => tlb_htw_req1_way_d, + dout => tlb_htw_req1_way_q ); +-- tlb request valid latches +tlb_htw_req2_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_htw_req2_valid_offset), + scout => sov_0(tlb_htw_req2_valid_offset), + din => tlb_htw_req2_valid_d, + dout => tlb_htw_req2_valid_q); +-- tlb request pending latches.. this req is loaded into a pte machine +tlb_htw_req2_pending_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_htw_req2_pending_offset), + scout => sov_0(tlb_htw_req2_pending_offset), + din => tlb_htw_req2_pending_d, + dout => tlb_htw_req2_pending_q); +-- tlb request tag latches +tlb_htw_req2_tag_latch: tri_rlmreg_p + generic map (width => tlb_htw_req2_tag_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_htw_req2_tag_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_htw_req2_tag_offset to tlb_htw_req2_tag_offset+tlb_htw_req2_tag_q'length-1), + scout => sov_0(tlb_htw_req2_tag_offset to tlb_htw_req2_tag_offset+tlb_htw_req2_tag_q'length-1), + din => tlb_htw_req2_tag_d, + dout => tlb_htw_req2_tag_q ); +-- tlb request tag latches +tlb_htw_req2_way_latch: tri_rlmreg_p + generic map (width => tlb_htw_req2_way_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(24+2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_htw_req2_way_offset to tlb_htw_req2_way_offset+tlb_htw_req2_way_q'length-1), + scout => sov_0(tlb_htw_req2_way_offset to tlb_htw_req2_way_offset+tlb_htw_req2_way_q'length-1), + din => tlb_htw_req2_way_d, + dout => tlb_htw_req2_way_q ); +-- tlb request valid latches +tlb_htw_req3_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_htw_req3_valid_offset), + scout => sov_0(tlb_htw_req3_valid_offset), + din => tlb_htw_req3_valid_d, + dout => tlb_htw_req3_valid_q); +tlb_htw_req3_pending_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_htw_req3_pending_offset), + scout => sov_0(tlb_htw_req3_pending_offset), + din => tlb_htw_req3_pending_d, + dout => tlb_htw_req3_pending_q); +-- tlb request tag latches +tlb_htw_req3_tag_latch: tri_rlmreg_p + generic map (width => tlb_htw_req3_tag_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_htw_req3_tag_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_htw_req3_tag_offset to tlb_htw_req3_tag_offset+tlb_htw_req3_tag_q'length-1), + scout => sov_0(tlb_htw_req3_tag_offset to tlb_htw_req3_tag_offset+tlb_htw_req3_tag_q'length-1), + din => tlb_htw_req3_tag_d, + dout => tlb_htw_req3_tag_q ); +-- tlb request tag latches +tlb_htw_req3_way_latch: tri_rlmreg_p + generic map (width => tlb_htw_req3_way_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(24+3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_htw_req3_way_offset to tlb_htw_req3_way_offset+tlb_htw_req3_way_q'length-1), + scout => sov_0(tlb_htw_req3_way_offset to tlb_htw_req3_way_offset+tlb_htw_req3_way_q'length-1), + din => tlb_htw_req3_way_d, + dout => tlb_htw_req3_way_q ); +spare_a_latch: tri_rlmreg_p + generic map (width => spare_a_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spare_a_offset to spare_a_offset+spare_a_q'length-1), + scout => sov_0(spare_a_offset to spare_a_offset+spare_a_q'length-1), + din => spare_a_q, + dout => spare_a_q ); +htw_seq_latch: tri_rlmreg_p + generic map (width => htw_seq_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(htw_seq_offset to htw_seq_offset+htw_seq_q'length-1), + scout => sov_1(htw_seq_offset to htw_seq_offset+htw_seq_q'length-1), + din => htw_seq_d(0 to htw_seq_width-1), + dout => htw_seq_q(0 to htw_seq_width-1) ); +htw_inptr_latch: tri_rlmreg_p + generic map (width => htw_inptr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(htw_inptr_offset to htw_inptr_offset+htw_inptr_q'length-1), + scout => sov_1(htw_inptr_offset to htw_inptr_offset+htw_inptr_q'length-1), + din => htw_inptr_d, + dout => htw_inptr_q ); +htw_lsuptr_latch: tri_rlmreg_p + generic map (width => htw_lsuptr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(htw_lsuptr_offset to htw_lsuptr_offset+htw_lsuptr_q'length-1), + scout => sov_1(htw_lsuptr_offset to htw_lsuptr_offset+htw_lsuptr_q'length-1), + din => htw_lsuptr_d, + dout => htw_lsuptr_q ); +htw_lsu_ttype_latch: tri_rlmreg_p + generic map (width => htw_lsu_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => htw_lsu_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(htw_lsu_ttype_offset to htw_lsu_ttype_offset+htw_lsu_ttype_q'length-1), + scout => sov_1(htw_lsu_ttype_offset to htw_lsu_ttype_offset+htw_lsu_ttype_q'length-1), + din => htw_lsu_ttype_d, + dout => htw_lsu_ttype_q ); +htw_lsu_thdid_latch: tri_rlmreg_p + generic map (width => htw_lsu_thdid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => htw_lsu_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(htw_lsu_thdid_offset to htw_lsu_thdid_offset+htw_lsu_thdid_q'length-1), + scout => sov_1(htw_lsu_thdid_offset to htw_lsu_thdid_offset+htw_lsu_thdid_q'length-1), + din => htw_lsu_thdid_d, + dout => htw_lsu_thdid_q ); +htw_lsu_wimge_latch: tri_rlmreg_p + generic map (width => htw_lsu_wimge_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => htw_lsu_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(htw_lsu_wimge_offset to htw_lsu_wimge_offset+htw_lsu_wimge_q'length-1), + scout => sov_1(htw_lsu_wimge_offset to htw_lsu_wimge_offset+htw_lsu_wimge_q'length-1), + din => htw_lsu_wimge_d, + dout => htw_lsu_wimge_q ); +htw_lsu_u_latch: tri_rlmreg_p + generic map (width => htw_lsu_u_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => htw_lsu_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(htw_lsu_u_offset to htw_lsu_u_offset+htw_lsu_u_q'length-1), + scout => sov_1(htw_lsu_u_offset to htw_lsu_u_offset+htw_lsu_u_q'length-1), + din => htw_lsu_u_d, + dout => htw_lsu_u_q ); +htw_lsu_addr_latch: tri_rlmreg_p + generic map (width => htw_lsu_addr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => htw_lsu_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(htw_lsu_addr_offset to htw_lsu_addr_offset+htw_lsu_addr_q'length-1), + scout => sov_1(htw_lsu_addr_offset to htw_lsu_addr_offset+htw_lsu_addr_q'length-1), + din => htw_lsu_addr_d, + dout => htw_lsu_addr_q ); +pte0_seq_latch: tri_rlmreg_p + generic map (width => pte0_seq_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(pte0_seq_offset to pte0_seq_offset+pte0_seq_q'length-1), + scout => sov_1(pte0_seq_offset to pte0_seq_offset+pte0_seq_q'length-1), + din => pte0_seq_d, + dout => pte0_seq_q ); +pte0_score_ptr_latch: tri_rlmreg_p + generic map (width => pte0_score_ptr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => pte0_score_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(pte0_score_ptr_offset to pte0_score_ptr_offset+pte0_score_ptr_q'length-1), + scout => sov_1(pte0_score_ptr_offset to pte0_score_ptr_offset+pte0_score_ptr_q'length-1), + din => pte0_score_ptr_d, + dout => pte0_score_ptr_q ); +pte0_score_cl_offset_latch: tri_rlmreg_p + generic map (width => pte0_score_cl_offset_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => pte0_score_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(pte0_score_cl_offset_offset to pte0_score_cl_offset_offset+pte0_score_cl_offset_q'length-1), + scout => sov_1(pte0_score_cl_offset_offset to pte0_score_cl_offset_offset+pte0_score_cl_offset_q'length-1), + din => pte0_score_cl_offset_d, + dout => pte0_score_cl_offset_q ); +pte0_score_error_latch: tri_rlmreg_p + generic map (width => pte0_score_error_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => pte0_score_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(pte0_score_error_offset to pte0_score_error_offset+pte0_score_error_q'length-1), + scout => sov_1(pte0_score_error_offset to pte0_score_error_offset+pte0_score_error_q'length-1), + din => pte0_score_error_d, + dout => pte0_score_error_q ); +pte0_score_qwbeat_latch: tri_rlmreg_p + generic map (width => pte0_score_qwbeat_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => pte0_score_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(pte0_score_qwbeat_offset to pte0_score_qwbeat_offset+pte0_score_qwbeat_q'length-1), + scout => sov_1(pte0_score_qwbeat_offset to pte0_score_qwbeat_offset+pte0_score_qwbeat_q'length-1), + din => pte0_score_qwbeat_d, + dout => pte0_score_qwbeat_q ); +pte0_score_ibit_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => pte0_score_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(pte0_score_ibit_offset), + scout => sov_1(pte0_score_ibit_offset), + din => pte0_score_ibit_d, + dout => pte0_score_ibit_q); +pte0_score_pending_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => pte0_score_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(pte0_score_pending_offset), + scout => sov_1(pte0_score_pending_offset), + din => pte0_score_pending_d, + dout => pte0_score_pending_q); +pte0_score_dataval_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => pte0_score_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(pte0_score_dataval_offset), + scout => sov_1(pte0_score_dataval_offset), + din => pte0_score_dataval_d, + dout => pte0_score_dataval_q); +pte1_seq_latch: tri_rlmreg_p + generic map (width => pte1_seq_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(pte1_seq_offset to pte1_seq_offset+pte1_seq_q'length-1), + scout => sov_1(pte1_seq_offset to pte1_seq_offset+pte1_seq_q'length-1), + din => pte1_seq_d, + dout => pte1_seq_q ); +pte1_score_ptr_latch: tri_rlmreg_p + generic map (width => pte1_score_ptr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => pte1_score_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(pte1_score_ptr_offset to pte1_score_ptr_offset+pte1_score_ptr_q'length-1), + scout => sov_1(pte1_score_ptr_offset to pte1_score_ptr_offset+pte1_score_ptr_q'length-1), + din => pte1_score_ptr_d, + dout => pte1_score_ptr_q ); +pte1_score_cl_offset_latch: tri_rlmreg_p + generic map (width => pte1_score_cl_offset_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => pte1_score_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(pte1_score_cl_offset_offset to pte1_score_cl_offset_offset+pte1_score_cl_offset_q'length-1), + scout => sov_1(pte1_score_cl_offset_offset to pte1_score_cl_offset_offset+pte1_score_cl_offset_q'length-1), + din => pte1_score_cl_offset_d, + dout => pte1_score_cl_offset_q ); +pte1_score_error_latch: tri_rlmreg_p + generic map (width => pte1_score_error_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => pte1_score_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(pte1_score_error_offset to pte1_score_error_offset+pte1_score_error_q'length-1), + scout => sov_1(pte1_score_error_offset to pte1_score_error_offset+pte1_score_error_q'length-1), + din => pte1_score_error_d, + dout => pte1_score_error_q ); +pte1_score_qwbeat_latch: tri_rlmreg_p + generic map (width => pte1_score_qwbeat_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => pte1_score_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(pte1_score_qwbeat_offset to pte1_score_qwbeat_offset+pte1_score_qwbeat_q'length-1), + scout => sov_1(pte1_score_qwbeat_offset to pte1_score_qwbeat_offset+pte1_score_qwbeat_q'length-1), + din => pte1_score_qwbeat_d, + dout => pte1_score_qwbeat_q ); +pte1_score_ibit_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => pte1_score_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(pte1_score_ibit_offset), + scout => sov_1(pte1_score_ibit_offset), + din => pte1_score_ibit_d, + dout => pte1_score_ibit_q); +pte1_score_pending_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => pte1_score_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(pte1_score_pending_offset), + scout => sov_1(pte1_score_pending_offset), + din => pte1_score_pending_d, + dout => pte1_score_pending_q); +pte1_score_dataval_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => pte1_score_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(pte1_score_dataval_offset), + scout => sov_1(pte1_score_dataval_offset), + din => pte1_score_dataval_d, + dout => pte1_score_dataval_q); +pte_load_ptr_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(pte_load_ptr_offset), + scout => sov_1(pte_load_ptr_offset), + din => pte_load_ptr_d, + dout => pte_load_ptr_q); +ptereload_ptr_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ptereload_ptr_offset), + scout => sov_1(ptereload_ptr_offset), + din => ptereload_ptr_d, + dout => ptereload_ptr_q); +-- t minus 1 phase latches +reld_core_tag_tm1_latch: tri_rlmreg_p + generic map (width => reld_core_tag_tm1_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => reld_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(reld_core_tag_tm1_offset to reld_core_tag_tm1_offset+reld_core_tag_tm1_q'length-1), + scout => sov_1(reld_core_tag_tm1_offset to reld_core_tag_tm1_offset+reld_core_tag_tm1_q'length-1), + din => reld_core_tag_tm1_d, + dout => reld_core_tag_tm1_q ); +reld_qw_tm1_latch: tri_rlmreg_p + generic map (width => reld_qw_tm1_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => reld_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(reld_qw_tm1_offset to reld_qw_tm1_offset+reld_qw_tm1_q'length-1), + scout => sov_1(reld_qw_tm1_offset to reld_qw_tm1_offset+reld_qw_tm1_q'length-1), + din => reld_qw_tm1_d, + dout => reld_qw_tm1_q ); +reld_crit_qw_tm1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => reld_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(reld_crit_qw_tm1_offset), + scout => sov_1(reld_crit_qw_tm1_offset), + din => reld_crit_qw_tm1_d, + dout => reld_crit_qw_tm1_q); +reld_ditc_tm1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => reld_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(reld_ditc_tm1_offset), + scout => sov_1(reld_ditc_tm1_offset), + din => reld_ditc_tm1_d, + dout => reld_ditc_tm1_q); +reld_data_vld_tm1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => reld_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(reld_data_vld_tm1_offset), + scout => sov_1(reld_data_vld_tm1_offset), + din => reld_data_vld_tm1_d, + dout => reld_data_vld_tm1_q); +-- t phase latches +reld_core_tag_t_latch: tri_rlmreg_p + generic map (width => reld_core_tag_t_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => reld_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(reld_core_tag_t_offset to reld_core_tag_t_offset+reld_core_tag_t_q'length-1), + scout => sov_1(reld_core_tag_t_offset to reld_core_tag_t_offset+reld_core_tag_t_q'length-1), + din => reld_core_tag_t_d, + dout => reld_core_tag_t_q ); +reld_qw_t_latch: tri_rlmreg_p + generic map (width => reld_qw_t_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => reld_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(reld_qw_t_offset to reld_qw_t_offset+reld_qw_t_q'length-1), + scout => sov_1(reld_qw_t_offset to reld_qw_t_offset+reld_qw_t_q'length-1), + din => reld_qw_t_d, + dout => reld_qw_t_q ); +reld_crit_qw_t_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => reld_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(reld_crit_qw_t_offset), + scout => sov_1(reld_crit_qw_t_offset), + din => reld_crit_qw_t_d, + dout => reld_crit_qw_t_q); +reld_ditc_t_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => reld_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(reld_ditc_t_offset), + scout => sov_1(reld_ditc_t_offset), + din => reld_ditc_t_d, + dout => reld_ditc_t_q); +reld_data_vld_t_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => reld_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(reld_data_vld_t_offset), + scout => sov_1(reld_data_vld_t_offset), + din => reld_data_vld_t_d, + dout => reld_data_vld_t_q); +-- t plus 1 phase latches +reld_core_tag_tp1_latch: tri_rlmreg_p + generic map (width => reld_core_tag_tp1_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => reld_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(reld_core_tag_tp1_offset to reld_core_tag_tp1_offset+reld_core_tag_tp1_q'length-1), + scout => sov_1(reld_core_tag_tp1_offset to reld_core_tag_tp1_offset+reld_core_tag_tp1_q'length-1), + din => reld_core_tag_tp1_d, + dout => reld_core_tag_tp1_q ); +reld_qw_tp1_latch: tri_rlmreg_p + generic map (width => reld_qw_tp1_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => reld_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(reld_qw_tp1_offset to reld_qw_tp1_offset+reld_qw_tp1_q'length-1), + scout => sov_1(reld_qw_tp1_offset to reld_qw_tp1_offset+reld_qw_tp1_q'length-1), + din => reld_qw_tp1_d, + dout => reld_qw_tp1_q ); +reld_crit_qw_tp1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => reld_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(reld_crit_qw_tp1_offset), + scout => sov_1(reld_crit_qw_tp1_offset), + din => reld_crit_qw_tp1_d, + dout => reld_crit_qw_tp1_q); +reld_ditc_tp1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => reld_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(reld_ditc_tp1_offset), + scout => sov_1(reld_ditc_tp1_offset), + din => reld_ditc_tp1_d, + dout => reld_ditc_tp1_q); +reld_data_vld_tp1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => reld_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(reld_data_vld_tp1_offset), + scout => sov_1(reld_data_vld_tp1_offset), + din => reld_data_vld_tp1_d, + dout => reld_data_vld_tp1_q); +reld_data_tp1_latch: tri_rlmreg_p + generic map (width => reld_data_tp1_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => reld_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(reld_data_tp1_offset to reld_data_tp1_offset+reld_data_tp1_q'length-1), + scout => sov_1(reld_data_tp1_offset to reld_data_tp1_offset+reld_data_tp1_q'length-1), + din => reld_data_tp1_d, + dout => reld_data_tp1_q ); +-- t plus 2 phase latches +reld_core_tag_tp2_latch: tri_rlmreg_p + generic map (width => reld_core_tag_tp2_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => reld_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(reld_core_tag_tp2_offset to reld_core_tag_tp2_offset+reld_core_tag_tp2_q'length-1), + scout => sov_1(reld_core_tag_tp2_offset to reld_core_tag_tp2_offset+reld_core_tag_tp2_q'length-1), + din => reld_core_tag_tp2_d, + dout => reld_core_tag_tp2_q ); +reld_qw_tp2_latch: tri_rlmreg_p + generic map (width => reld_qw_tp2_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => reld_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(reld_qw_tp2_offset to reld_qw_tp2_offset+reld_qw_tp2_q'length-1), + scout => sov_1(reld_qw_tp2_offset to reld_qw_tp2_offset+reld_qw_tp2_q'length-1), + din => reld_qw_tp2_d, + dout => reld_qw_tp2_q ); +reld_crit_qw_tp2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => reld_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(reld_crit_qw_tp2_offset), + scout => sov_1(reld_crit_qw_tp2_offset), + din => reld_crit_qw_tp2_d, + dout => reld_crit_qw_tp2_q); +reld_ditc_tp2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => reld_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(reld_ditc_tp2_offset), + scout => sov_1(reld_ditc_tp2_offset), + din => reld_ditc_tp2_d, + dout => reld_ditc_tp2_q); +reld_data_vld_tp2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => reld_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(reld_data_vld_tp2_offset), + scout => sov_1(reld_data_vld_tp2_offset), + din => reld_data_vld_tp2_d, + dout => reld_data_vld_tp2_q); +reld_data_tp2_latch: tri_rlmreg_p + generic map (width => reld_data_tp2_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => reld_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(reld_data_tp2_offset to reld_data_tp2_offset+reld_data_tp2_q'length-1), + scout => sov_1(reld_data_tp2_offset to reld_data_tp2_offset+reld_data_tp2_q'length-1), + din => reld_data_tp2_d, + dout => reld_data_tp2_q ); +reld_ecc_err_tp2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => reld_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(reld_ecc_err_tp2_offset), + scout => sov_1(reld_ecc_err_tp2_offset), + din => reld_ecc_err_tp2_d, + dout => reld_ecc_err_tp2_q); +reld_ecc_err_ue_tp2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => reld_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(reld_ecc_err_ue_tp2_offset), + scout => sov_1(reld_ecc_err_ue_tp2_offset), + din => reld_ecc_err_ue_tp2_d, + dout => reld_ecc_err_ue_tp2_q); +-- t plus 3 phase +pte0_reld_data_tp3_latch: tri_rlmreg_p + generic map (width => pte0_reld_data_tp3_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => pte0_reld_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(pte0_reld_data_tp3_offset to pte0_reld_data_tp3_offset+pte0_reld_data_tp3_q'length-1), + scout => sov_1(pte0_reld_data_tp3_offset to pte0_reld_data_tp3_offset+pte0_reld_data_tp3_q'length-1), + din => pte0_reld_data_tp3_d, + dout => pte0_reld_data_tp3_q ); +pte1_reld_data_tp3_latch: tri_rlmreg_p + generic map (width => pte1_reld_data_tp3_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => pte1_reld_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(pte1_reld_data_tp3_offset to pte1_reld_data_tp3_offset+pte1_reld_data_tp3_q'length-1), + scout => sov_1(pte1_reld_data_tp3_offset to pte1_reld_data_tp3_offset+pte1_reld_data_tp3_q'length-1), + din => pte1_reld_data_tp3_d, + dout => pte1_reld_data_tp3_q ); +htw_tag3_latch: tri_rlmreg_p + generic map (width => htw_tag3_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(28), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(htw_tag3_offset to htw_tag3_offset+htw_tag3_q'length-1), + scout => sov_1(htw_tag3_offset to htw_tag3_offset+htw_tag3_q'length-1), + din => htw_tag3_d, + dout => htw_tag3_q ); +htw_tag4_clr_resv_latch: tri_rlmreg_p + generic map (width => htw_tag4_clr_resv_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(28), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(htw_tag4_clr_resv_offset to htw_tag4_clr_resv_offset+htw_tag4_clr_resv_q'length-1), + scout => sov_1(htw_tag4_clr_resv_offset to htw_tag4_clr_resv_offset+htw_tag4_clr_resv_q'length-1), + din => htw_tag4_clr_resv_d, + dout => htw_tag4_clr_resv_q ); +htw_tag5_clr_resv_latch: tri_rlmreg_p + generic map (width => htw_tag5_clr_resv_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(28), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(htw_tag5_clr_resv_offset to htw_tag5_clr_resv_offset+htw_tag5_clr_resv_q'length-1), + scout => sov_1(htw_tag5_clr_resv_offset to htw_tag5_clr_resv_offset+htw_tag5_clr_resv_q'length-1), + din => htw_tag5_clr_resv_d, + dout => htw_tag5_clr_resv_q ); +spare_b_latch: tri_rlmreg_p + generic map (width => spare_b_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spare_b_offset to spare_b_offset+spare_b_q'length-1), + scout => sov_1(spare_b_offset to spare_b_offset+spare_b_q'length-1), + din => spare_b_q, + dout => spare_b_q ); +-------------------------------------------------- +-- thold/sg latches +-------------------------------------------------- +perv_2to1_reg: tri_plat + generic map (width => 3, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ccflush_dc, + din(0) => pc_func_sl_thold_2, + din(1) => pc_func_slp_sl_thold_2, + din(2) => pc_sg_2, + q(0) => pc_func_sl_thold_1, + q(1) => pc_func_slp_sl_thold_1, + q(2) => pc_sg_1); +perv_1to0_reg: tri_plat + generic map (width => 3, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ccflush_dc, + din(0) => pc_func_sl_thold_1, + din(1) => pc_func_slp_sl_thold_1, + din(2) => pc_sg_1, + q(0) => pc_func_sl_thold_0, + q(1) => pc_func_slp_sl_thold_0, + q(2) => pc_sg_0); +perv_lcbor_func_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b, + thold => pc_func_sl_thold_0, + sg => pc_sg_0, + act_dis => lcb_act_dis_dc, + forcee => pc_func_sl_force, + thold_b => pc_func_sl_thold_0_b); +perv_lcbor_func_slp_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b, + thold => pc_func_slp_sl_thold_0, + sg => pc_sg_0, + act_dis => lcb_act_dis_dc, + forcee => pc_func_slp_sl_force, + thold_b => pc_func_slp_sl_thold_0_b); +----------------------------------------------------------------------- +-- Scan +----------------------------------------------------------------------- +siv_0(0 TO scan_right_0) <= sov_0(1 to scan_right_0) & ac_func_scan_in(0); +ac_func_scan_out(0) <= sov_0(0); +siv_1(0 TO scan_right_1) <= sov_1(1 to scan_right_1) & ac_func_scan_in(1); +ac_func_scan_out(1) <= sov_1(0); +END MMQ_HTW; diff --git a/rel/src/vhdl/work/mmq_inval.vhdl b/rel/src/vhdl/work/mmq_inval.vhdl new file mode 100644 index 0000000..6035df3 --- /dev/null +++ b/rel/src/vhdl/work/mmq_inval.vhdl @@ -0,0 +1,2989 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +--******************************************************************** +--* TITLE: Memory Management Unit Invalidate Control Logic +--* NAME: mmq_inval.vhdl +--********************************************************************* + +library ieee; +use ieee.std_logic_1164.all; +library ibm; +use ibm.std_ulogic_unsigned.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_support.all; +library support; +use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity mmq_inval is + generic(thdid_width : integer := 4; + ttype_width : integer := 6; + state_width : integer := 2; + pid_width : integer := 14; + lpid_width : integer := 8; + t_width : integer := 3; + rs_is_width : integer := 9; + rs_data_width : integer := 64; + epn_width : integer := 52; + real_addr_width : integer := 42; + rpn_width : integer := 30; + inv_seq_width : integer := 6; + tlb_ways : natural := 4; + tlb_addr_width : natural := 7; + tlb_way_width : natural := 168; + expand_type : integer := 2 ); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + + tc_ccflush_dc : in std_ulogic; + tc_scan_dis_dc_b : in std_ulogic; + tc_scan_diag_dc : in std_ulogic; + tc_lbist_en_dc : in std_ulogic; + + lcb_d_mode_dc : in std_ulogic; + lcb_clkoff_dc_b : in std_ulogic; + lcb_act_dis_dc : in std_ulogic; + lcb_mpw1_dc_b : in std_ulogic_vector(0 to 4); + lcb_mpw2_dc_b : in std_ulogic; + lcb_delay_lclkr_dc : in std_ulogic_vector(0 to 4); + + ac_func_scan_in : in std_ulogic; + ac_func_scan_out : out std_ulogic; + + pc_sg_2 : in std_ulogic; + pc_func_sl_thold_2 : in std_ulogic; + pc_func_slp_sl_thold_2 : in std_ulogic; + pc_func_slp_nsl_thold_2 : in std_ulogic; + pc_fce_2 : in std_ulogic; + mmucr2_act_override : in std_ulogic; + xu_mm_ccr2_notlb : in std_ulogic; + xu_mm_ccr2_notlb_b : out std_ulogic_vector(1 to 12); + + mm_iu_ierat_snoop_coming : out std_ulogic; + mm_iu_ierat_snoop_val : out std_ulogic; + mm_iu_ierat_snoop_attr : out std_ulogic_vector(0 to 25); + mm_iu_ierat_snoop_vpn : out std_ulogic_vector(52-epn_width to 51); + iu_mm_ierat_snoop_ack : in std_ulogic; + + mm_xu_derat_snoop_coming : out std_ulogic; + mm_xu_derat_snoop_val : out std_ulogic; + mm_xu_derat_snoop_attr : out std_ulogic_vector(0 to 25); + mm_xu_derat_snoop_vpn : out std_ulogic_vector(52-epn_width to 51); + xu_mm_derat_snoop_ack : in std_ulogic; + tlb_snoop_coming : out std_ulogic; + tlb_snoop_val : out std_ulogic; + tlb_snoop_attr : out std_ulogic_vector(0 to 34); + tlb_snoop_vpn : out std_ulogic_vector(52-epn_width to 51); + tlb_snoop_ack : in std_ulogic; + an_ac_back_inv : in std_ulogic; + an_ac_back_inv_target : in std_ulogic; + an_ac_back_inv_local : in std_ulogic; + an_ac_back_inv_lbit : in std_ulogic; + an_ac_back_inv_gs : in std_ulogic; + an_ac_back_inv_ind : in std_ulogic; + an_ac_back_inv_addr : in std_ulogic_vector(64-real_addr_width to 63); + an_ac_back_inv_lpar_id : in std_ulogic_vector(0 to lpid_width-1); + ac_an_power_managed : in std_ulogic; + ac_an_back_inv_reject : out std_ulogic; + mmucr0_0 : in std_ulogic_vector(2 to 19); + mmucr0_1 : in std_ulogic_vector(2 to 19); + mmucr0_2 : in std_ulogic_vector(2 to 19); + mmucr0_3 : in std_ulogic_vector(2 to 19); + mmucr1 : in std_ulogic_vector(12 to 19); + mmucr1_csinv : in std_ulogic_vector(0 to 1); + lpidr : in std_ulogic_vector(0 to lpid_width-1); + + mas5_0_sgs : in std_ulogic; + mas5_0_slpid : in std_ulogic_vector(0 to 7); + mas6_0_spid : in std_ulogic_vector(0 to 13); + mas6_0_isize : in std_ulogic_vector(0 to 3); + mas6_0_sind : in std_ulogic; + mas6_0_sas : in std_ulogic; + mas5_1_sgs : in std_ulogic; + mas5_1_slpid : in std_ulogic_vector(0 to 7); + mas6_1_spid : in std_ulogic_vector(0 to 13); + mas6_1_isize : in std_ulogic_vector(0 to 3); + mas6_1_sind : in std_ulogic; + mas6_1_sas : in std_ulogic; + mas5_2_sgs : in std_ulogic; + mas5_2_slpid : in std_ulogic_vector(0 to 7); + mas6_2_spid : in std_ulogic_vector(0 to 13); + mas6_2_isize : in std_ulogic_vector(0 to 3); + mas6_2_sind : in std_ulogic; + mas6_2_sas : in std_ulogic; + mas5_3_sgs : in std_ulogic; + mas5_3_slpid : in std_ulogic_vector(0 to 7); + mas6_3_spid : in std_ulogic_vector(0 to 13); + mas6_3_isize : in std_ulogic_vector(0 to 3); + mas6_3_sind : in std_ulogic; + mas6_3_sas : in std_ulogic; + mmucsr0_tlb0fi : in std_ulogic; + mmq_inval_tlb0fi_done : out std_ulogic; + + + xu_mm_rf1_val : in std_ulogic_vector(0 to thdid_width-1); + xu_mm_rf1_is_tlbivax : in std_ulogic; + xu_mm_rf1_is_tlbilx : in std_ulogic; + xu_mm_rf1_is_erativax : in std_ulogic; + xu_mm_rf1_is_eratilx : in std_ulogic; + xu_mm_ex1_rs_is : in std_ulogic_vector(0 to rs_is_width-1); + xu_mm_ex1_is_isync : in std_ulogic; + xu_mm_ex1_is_csync : in std_ulogic; + xu_mm_ex2_eff_addr : in std_ulogic_vector(64-rs_data_width to 63); + xu_mm_rf1_t : in std_ulogic_vector(0 to t_width-1); + xu_mm_msr_gs : in std_ulogic_vector(0 to thdid_width-1); + xu_mm_msr_pr : in std_ulogic_vector(0 to thdid_width-1); + xu_mm_spr_epcr_dgtmi : in std_ulogic_vector(0 to thdid_width-1); + xu_mm_epcr_dgtmi : out std_ulogic_vector(0 to thdid_width-1); + xu_rf1_flush : in std_ulogic_vector(0 to thdid_width-1); + xu_ex1_flush : in std_ulogic_vector(0 to thdid_width-1); + xu_ex2_flush : in std_ulogic_vector(0 to thdid_width-1); + xu_ex3_flush : in std_ulogic_vector(0 to thdid_width-1); + xu_ex4_flush : in std_ulogic_vector(0 to thdid_width-1); + xu_ex5_flush : in std_ulogic_vector(0 to thdid_width-1); + xu_mm_lmq_stq_empty : in std_ulogic; + xu_mm_hold_ack : in std_ulogic_vector(0 to thdid_width-1); + iu_mm_lmq_empty : in std_ulogic; + tlb_ctl_barrier_done : in std_ulogic_vector(0 to thdid_width-1); + tlb_ctl_ex2_flush_req : in std_ulogic_vector(0 to thdid_width-1); + tlb_ctl_ex2_illeg_instr : in std_ulogic_vector(0 to thdid_width-1); + tlb_ctl_quiesce : in std_ulogic_vector(0 to thdid_width-1); + tlb_req_quiesce : in std_ulogic_vector(0 to thdid_width-1); + + mm_iu_barrier_done : out std_ulogic_vector(0 to thdid_width-1); + mm_xu_ex3_flush_req : out std_ulogic_vector(0 to thdid_width-1); + mm_xu_hold_req : out std_ulogic_vector(0 to thdid_width-1); + mm_xu_hold_done : out std_ulogic_vector(0 to thdid_width-1); + mm_xu_illeg_instr : out std_ulogic_vector(0 to thdid_width-1); + mm_xu_local_snoop_reject : out std_ulogic_vector(0 to thdid_width-1); + mm_xu_quiesce : out std_ulogic_vector(0 to thdid_width-1); + + inval_perf_tlbilx : out std_ulogic; + inval_perf_tlbivax : out std_ulogic; + inval_perf_tlbivax_snoop : out std_ulogic; + inval_perf_tlb_flush : out std_ulogic; + + htw_lsu_req_valid : in std_ulogic; + htw_lsu_thdid : in std_ulogic_vector(0 to thdid_width-1); + htw_lsu_ttype : in std_ulogic_vector(0 to 1); + htw_lsu_wimge : in std_ulogic_vector(0 to 4); + htw_lsu_u : in std_ulogic_vector(0 to 3); + htw_lsu_addr : in std_ulogic_vector(64-real_addr_width to 63); + htw_lsu_req_taken : out std_ulogic; + htw_quiesce : in std_ulogic_vector(0 to thdid_width-1); + tlbwe_back_inv_valid : in std_ulogic; + tlbwe_back_inv_thdid : in std_ulogic_vector(0 to thdid_width-1); + tlbwe_back_inv_addr : in std_ulogic_vector(52-epn_width to 51); + tlbwe_back_inv_attr : in std_ulogic_vector(0 to 34); + tlb_tag5_write : in std_ulogic; + tlbwe_back_inv_pending : out std_ulogic; + + mm_xu_lsu_req : out std_ulogic_vector(0 to thdid_width-1); + mm_xu_lsu_ttype : out std_ulogic_vector(0 to 1); + mm_xu_lsu_wimge : out std_ulogic_vector(0 to 4); + mm_xu_lsu_u : out std_ulogic_vector(0 to 3); + mm_xu_lsu_addr : out std_ulogic_vector(64-real_addr_width to 63); + mm_xu_lsu_lpid : out std_ulogic_vector(0 to 7); + mm_xu_lsu_gs : out std_ulogic; + mm_xu_lsu_ind : out std_ulogic; + mm_xu_lsu_lbit : out std_ulogic; + xu_mm_lsu_token : in std_ulogic; + + inval_dbg_seq_q : out std_ulogic_vector(0 to 4); + inval_dbg_seq_idle : out std_ulogic; + inval_dbg_seq_snoop_inprogress : out std_ulogic; + inval_dbg_seq_snoop_done : out std_ulogic; + inval_dbg_seq_local_done : out std_ulogic; + inval_dbg_seq_tlb0fi_done : out std_ulogic; + inval_dbg_seq_tlbwe_snoop_done : out std_ulogic; + inval_dbg_ex6_valid : out std_ulogic; + inval_dbg_ex6_thdid : out std_ulogic_vector(0 to 1); + inval_dbg_ex6_ttype : out std_ulogic_vector(0 to 2); + inval_dbg_snoop_forme : out std_ulogic; + inval_dbg_snoop_local_reject : out std_ulogic; + inval_dbg_an_ac_back_inv_q : out std_ulogic_vector(2 to 8); + inval_dbg_an_ac_back_inv_lpar_id_q : out std_ulogic_vector(0 to 7); + inval_dbg_an_ac_back_inv_addr_q : out std_ulogic_vector(22 to 63); + inval_dbg_snoop_valid_q : out std_ulogic_vector(0 to 2); + inval_dbg_snoop_ack_q : out std_ulogic_vector(0 to 2); + inval_dbg_snoop_attr_q : out std_ulogic_vector(0 to 34); + inval_dbg_snoop_attr_tlb_spec_q : out std_ulogic_vector(18 to 19); + inval_dbg_snoop_vpn_q : out std_ulogic_vector(17 to 51); + inval_dbg_lsu_tokens_q : out std_ulogic_vector(0 to 1) +); +end mmq_inval; +architecture mmq_inval of mmq_inval is +constant MMU_Mode_Value : std_ulogic := '0'; +constant ERAT_Mode_Value : std_ulogic := '1'; +constant TlbSel_Tlb : std_ulogic_vector(0 to 1) := "00"; +constant TlbSel_IErat : std_ulogic_vector(0 to 1) := "10"; +constant TlbSel_DErat : std_ulogic_vector(0 to 1) := "11"; +constant TLB_PgSize_1GB : std_ulogic_vector(0 to 3) := "1010"; +constant TLB_PgSize_16MB : std_ulogic_vector(0 to 3) := "0111"; +constant TLB_PgSize_1MB : std_ulogic_vector(0 to 3) := "0101"; +constant TLB_PgSize_64KB : std_ulogic_vector(0 to 3) := "0011"; +constant TLB_PgSize_4KB : std_ulogic_vector(0 to 3) := "0001"; +constant TLB_PgSize_256MB : std_ulogic_vector(0 to 3) := "1001"; +constant InvSeq_Idle : std_ulogic_vector(0 to 5) := "000000"; +constant InvSeq_Stg1 : std_ulogic_vector(0 to 5) := "000001"; +constant InvSeq_Stg2 : std_ulogic_vector(0 to 5) := "000011"; +constant InvSeq_Stg3 : std_ulogic_vector(0 to 5) := "000010"; +constant InvSeq_Stg4 : std_ulogic_vector(0 to 5) := "000110"; +constant InvSeq_Stg5 : std_ulogic_vector(0 to 5) := "000100"; +constant InvSeq_Stg6 : std_ulogic_vector(0 to 5) := "000101"; +constant InvSeq_Stg7 : std_ulogic_vector(0 to 5) := "000111"; +constant InvSeq_Stg8 : std_ulogic_vector(0 to 5) := "001000"; +constant InvSeq_Stg9 : std_ulogic_vector(0 to 5) := "001001"; +constant InvSeq_Stg10 : std_ulogic_vector(0 to 5) := "001011"; +constant InvSeq_Stg11 : std_ulogic_vector(0 to 5) := "001010"; +constant InvSeq_Stg12 : std_ulogic_vector(0 to 5) := "001110"; +constant InvSeq_Stg13 : std_ulogic_vector(0 to 5) := "001100"; +constant InvSeq_Stg14 : std_ulogic_vector(0 to 5) := "001101"; +constant InvSeq_Stg15 : std_ulogic_vector(0 to 5) := "001111"; +constant InvSeq_Stg16 : std_ulogic_vector(0 to 5) := "010000"; +constant InvSeq_Stg17 : std_ulogic_vector(0 to 5) := "010001"; +constant InvSeq_Stg18 : std_ulogic_vector(0 to 5) := "010011"; +constant InvSeq_Stg19 : std_ulogic_vector(0 to 5) := "010010"; +constant InvSeq_Stg20 : std_ulogic_vector(0 to 5) := "010110"; +constant InvSeq_Stg21 : std_ulogic_vector(0 to 5) := "010100"; +constant InvSeq_Stg22 : std_ulogic_vector(0 to 5) := "010101"; +constant InvSeq_Stg23 : std_ulogic_vector(0 to 5) := "010111"; +constant InvSeq_Stg24 : std_ulogic_vector(0 to 5) := "011000"; +constant InvSeq_Stg25 : std_ulogic_vector(0 to 5) := "011001"; +constant InvSeq_Stg26 : std_ulogic_vector(0 to 5) := "011011"; +constant InvSeq_Stg27 : std_ulogic_vector(0 to 5) := "011010"; +constant InvSeq_Stg28 : std_ulogic_vector(0 to 5) := "011110"; +constant InvSeq_Stg29 : std_ulogic_vector(0 to 5) := "011100"; +constant InvSeq_Stg30 : std_ulogic_vector(0 to 5) := "011101"; +constant InvSeq_Stg31 : std_ulogic_vector(0 to 5) := "011111"; +constant InvSeq_Stg32 : std_ulogic_vector(0 to 5) := "100000"; +-- mmucr1 bits: 12:13-ICTID/ITTID,14:15-DCTID/DTTID,16:17-resv, TLBI_MSB/TLBI_REJ +constant pos_ictid : natural := 12; +constant pos_ittid : natural := 13; +constant pos_dctid : natural := 14; +constant pos_dttid : natural := 15; +constant pos_tlbi_msb : natural := 18; +constant pos_tlbi_rej : natural := 19; +constant ex1_valid_offset : natural := 0; +constant ex1_ttype_offset : natural := ex1_valid_offset + thdid_width; +constant ex1_state_offset : natural := ex1_ttype_offset + ttype_width-2; +constant ex1_t_offset : natural := ex1_state_offset + state_width; +constant ex2_valid_offset : natural := ex1_t_offset + t_width; +constant ex2_ttype_offset : natural := ex2_valid_offset + thdid_width; +constant ex2_rs_is_offset : natural := ex2_ttype_offset + ttype_width; +constant ex2_state_offset : natural := ex2_rs_is_offset + rs_is_width; +constant ex2_t_offset : natural := ex2_state_offset + state_width; +constant ex3_valid_offset : natural := ex2_t_offset + t_width; +constant ex3_ttype_offset : natural := ex3_valid_offset + thdid_width; +constant ex3_rs_is_offset : natural := ex3_ttype_offset + ttype_width; +constant ex3_state_offset : natural := ex3_rs_is_offset + rs_is_width; +constant ex3_t_offset : natural := ex3_state_offset + state_width; +constant ex3_flush_req_offset : natural := ex3_t_offset + t_width; +constant ex3_ea_offset : natural := ex3_flush_req_offset + thdid_width; +constant ex4_valid_offset : natural := ex3_ea_offset + epn_width+12; +constant ex4_ttype_offset : natural := ex4_valid_offset + thdid_width; +constant ex4_rs_is_offset : natural := ex4_ttype_offset + ttype_width; +constant ex4_state_offset : natural := ex4_rs_is_offset + rs_is_width; +constant ex4_t_offset : natural := ex4_state_offset + state_width; +constant ex5_valid_offset : natural := ex4_t_offset + t_width; +constant ex5_ttype_offset : natural := ex5_valid_offset + thdid_width; +constant ex5_rs_is_offset : natural := ex5_ttype_offset + ttype_width; +constant ex5_state_offset : natural := ex5_rs_is_offset + rs_is_width; +constant ex5_t_offset : natural := ex5_state_offset + state_width; +constant ex6_valid_offset : natural := ex5_t_offset + t_width; +constant ex6_ttype_offset : natural := ex6_valid_offset + thdid_width; +constant ex6_isel_offset : natural := ex6_ttype_offset + ttype_width; +constant ex6_size_offset : natural := ex6_isel_offset + 3; +constant ex6_gs_offset : natural := ex6_size_offset + 4; +constant ex6_ts_offset : natural := ex6_gs_offset + 1; +constant ex6_ind_offset : natural := ex6_ts_offset + 1; +constant ex6_pid_offset : natural := ex6_ind_offset + 1; +constant ex6_lpid_offset : natural := ex6_pid_offset + pid_width; +constant inv_seq_offset : natural := ex6_lpid_offset + lpid_width; +constant hold_req_offset : natural := inv_seq_offset + inv_seq_width; +constant hold_ack_offset : natural := hold_req_offset + thdid_width; +constant hold_done_offset : natural := hold_ack_offset + thdid_width; +constant local_barrier_offset : natural := hold_done_offset + thdid_width; +constant global_barrier_offset : natural := local_barrier_offset + thdid_width; +constant barrier_done_offset : natural := global_barrier_offset + thdid_width; +constant illeg_instr_offset : natural := barrier_done_offset + thdid_width; +constant local_reject_offset : natural := illeg_instr_offset + thdid_width; +constant snoop_valid_offset : natural := local_reject_offset + thdid_width; +constant snoop_attr_offset : natural := snoop_valid_offset + 3; +constant snoop_vpn_offset : natural := snoop_attr_offset + 35; +constant snoop_attr_clone_offset : natural := snoop_vpn_offset + epn_width; +constant snoop_attr_tlb_spec_offset : natural := snoop_attr_clone_offset + 26; +constant snoop_vpn_clone_offset : natural := snoop_attr_tlb_spec_offset + 2; +constant snoop_ack_offset : natural := snoop_vpn_clone_offset + epn_width; +constant snoop_coming_offset : natural := snoop_ack_offset + 3; +constant mm_xu_quiesce_offset : natural := snoop_coming_offset + 5; +constant inv_seq_inprogress_offset : natural := mm_xu_quiesce_offset + thdid_width; +constant xu_mm_ccr2_notlb_offset : natural := inv_seq_inprogress_offset + 6; +constant spare_offset : natural := xu_mm_ccr2_notlb_offset + 13; +constant an_ac_back_inv_offset : natural := spare_offset + 16; +constant an_ac_back_inv_addr_offset : natural := an_ac_back_inv_offset + 9; +constant an_ac_back_inv_lpar_id_offset : natural := an_ac_back_inv_addr_offset + real_addr_width; +constant lsu_tokens_offset : natural := an_ac_back_inv_lpar_id_offset + lpid_width; +constant lsu_req_offset : natural := lsu_tokens_offset + 2; +constant lsu_ttype_offset : natural := lsu_req_offset + thdid_width; +constant lsu_ubits_offset : natural := lsu_ttype_offset + 2; +constant lsu_wimge_offset : natural := lsu_ubits_offset+ 4; +constant lsu_addr_offset : natural := lsu_wimge_offset + 5; +constant lsu_lpid_offset : natural := lsu_addr_offset + real_addr_width; +constant lsu_ind_offset : natural := lsu_lpid_offset + lpid_width; +constant lsu_gs_offset : natural := lsu_ind_offset + 1; +constant lsu_lbit_offset : natural := lsu_gs_offset + 1; +constant power_managed_offset : natural := lsu_lbit_offset + 1; +constant tlbwe_back_inv_offset : natural := power_managed_offset + 4; +constant tlbwe_back_inv_addr_offset : natural := tlbwe_back_inv_offset + thdid_width + 2; +constant tlbwe_back_inv_attr_offset : natural := tlbwe_back_inv_addr_offset + epn_width; +constant scan_right : natural := tlbwe_back_inv_attr_offset + 35 - 1; +signal ex1_valid_d, ex1_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal ex1_ttype_d, ex1_ttype_q : std_ulogic_vector(0 to ttype_width-3); +signal ex1_state_d, ex1_state_q : std_ulogic_vector(0 to state_width-1); +signal ex1_t_d, ex1_t_q : std_ulogic_vector(0 to t_width-1); +signal ex2_valid_d, ex2_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal ex2_ttype_d, ex2_ttype_q : std_ulogic_vector(0 to ttype_width-1); +signal ex2_rs_is_d, ex2_rs_is_q : std_ulogic_vector(0 to rs_is_width-1); +signal ex2_state_d, ex2_state_q : std_ulogic_vector(0 to state_width-1); +signal ex2_t_d, ex2_t_q : std_ulogic_vector(0 to t_width-1); +signal ex3_ea_d, ex3_ea_q : std_ulogic_vector(64-rs_data_width to 63); +signal ex3_valid_d, ex3_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal ex3_ttype_d, ex3_ttype_q : std_ulogic_vector(0 to ttype_width-1); +signal ex3_rs_is_d, ex3_rs_is_q : std_ulogic_vector(0 to rs_is_width-1); +signal ex3_state_d, ex3_state_q : std_ulogic_vector(0 to state_width-1); +signal ex3_t_d, ex3_t_q : std_ulogic_vector(0 to t_width-1); +signal ex3_flush_req_d, ex3_flush_req_q : std_ulogic_vector(0 to thdid_width-1); +signal ex4_valid_d, ex4_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal ex4_ttype_d, ex4_ttype_q : std_ulogic_vector(0 to ttype_width-1); +signal ex4_rs_is_d, ex4_rs_is_q : std_ulogic_vector(0 to rs_is_width-1); +signal ex4_state_d, ex4_state_q : std_ulogic_vector(0 to state_width-1); +signal ex4_t_d, ex4_t_q : std_ulogic_vector(0 to t_width-1); +signal ex5_valid_d, ex5_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal ex5_ttype_d, ex5_ttype_q : std_ulogic_vector(0 to ttype_width-1); +signal ex5_rs_is_d, ex5_rs_is_q : std_ulogic_vector(0 to rs_is_width-1); +signal ex5_state_d, ex5_state_q : std_ulogic_vector(0 to state_width-1); +signal ex5_t_d, ex5_t_q : std_ulogic_vector(0 to t_width-1); +signal ex6_valid_d, ex6_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal ex6_ttype_d, ex6_ttype_q : std_ulogic_vector(0 to ttype_width-1); +signal ex6_isel_d, ex6_isel_q : std_ulogic_vector(0 to 2); +signal ex6_size_d, ex6_size_q : std_ulogic_vector(0 to 3); +signal ex6_gs_d, ex6_gs_q : std_ulogic; +signal ex6_ts_d, ex6_ts_q : std_ulogic; +signal ex6_ind_d, ex6_ind_q : std_ulogic; +signal ex6_pid_d, ex6_pid_q : std_ulogic_vector(0 to pid_width-1); +signal ex6_lpid_d, ex6_lpid_q : std_ulogic_vector(0 to lpid_width-1); +signal inv_seq_d, inv_seq_q : std_ulogic_vector(0 to 5); +signal hold_req_d, hold_req_q : std_ulogic_vector(0 to thdid_width-1); +signal hold_ack_d, hold_ack_q : std_ulogic_vector(0 to thdid_width-1); +signal hold_done_d, hold_done_q : std_ulogic_vector(0 to thdid_width-1); +signal local_barrier_d, local_barrier_q : std_ulogic_vector(0 to thdid_width-1); +signal global_barrier_d, global_barrier_q : std_ulogic_vector(0 to thdid_width-1); +signal barrier_done_d, barrier_done_q : std_ulogic_vector(0 to thdid_width-1); +signal illeg_instr_d, illeg_instr_q : std_ulogic_vector(0 to thdid_width-1); +signal local_reject_d, local_reject_q : std_ulogic_vector(0 to thdid_width-1); +signal inv_seq_inprogress_d, inv_seq_inprogress_q : std_ulogic_vector(0 to 5); +signal snoop_valid_d, snoop_valid_q : std_ulogic_vector(0 to 2); +signal snoop_attr_d, snoop_attr_q : std_ulogic_vector(0 to 34); +signal snoop_vpn_d,snoop_vpn_q : std_ulogic_vector(52-epn_width to 51); +signal snoop_attr_clone_d, snoop_attr_clone_q : std_ulogic_vector(0 to 25); +signal snoop_attr_tlb_spec_d, snoop_attr_tlb_spec_q : std_ulogic_vector(18 to 19); +signal snoop_vpn_clone_d,snoop_vpn_clone_q : std_ulogic_vector(52-epn_width to 51); +signal snoop_ack_d,snoop_ack_q : std_ulogic_vector(0 to 2); +signal snoop_coming_d, snoop_coming_q : std_ulogic_vector(0 to 4); +signal an_ac_back_inv_d, an_ac_back_inv_q : std_ulogic_vector(0 to 8); +signal an_ac_back_inv_addr_d, an_ac_back_inv_addr_q : std_ulogic_vector(64-real_addr_width to 63); +signal an_ac_back_inv_lpar_id_d, an_ac_back_inv_lpar_id_q : std_ulogic_vector(0 to lpid_width-1); +signal lsu_tokens_d, lsu_tokens_q : std_ulogic_vector(0 to 1); +signal lsu_req_d, lsu_req_q : std_ulogic_vector(0 to thdid_width-1); +signal lsu_ttype_d, lsu_ttype_q : std_ulogic_vector(0 to 1); +signal lsu_ubits_d, lsu_ubits_q : std_ulogic_vector(0 to 3); +signal lsu_wimge_d, lsu_wimge_q : std_ulogic_vector(0 to 4); +signal lsu_addr_d, lsu_addr_q : std_ulogic_vector(64-real_addr_width to 63); +signal lsu_lpid_d, lsu_lpid_q : std_ulogic_vector(0 to lpid_width-1); +signal lsu_ind_d, lsu_ind_q : std_ulogic; +signal lsu_gs_d, lsu_gs_q : std_ulogic; +signal lsu_lbit_d, lsu_lbit_q : std_ulogic; +signal xu_mm_ccr2_notlb_d, xu_mm_ccr2_notlb_q : std_ulogic_vector(0 to 12); +signal xu_mm_epcr_dgtmi_q : std_ulogic_vector(0 to thdid_width-1); +signal lpidr_q : std_ulogic_vector(0 to lpid_width-1); +signal mmucr1_q : std_ulogic_vector(12 to 19); +signal mmucr1_csinv_q : std_ulogic_vector(0 to 1); +signal spare_q : std_ulogic_vector(0 to 15); +signal power_managed_d, power_managed_q : std_ulogic_vector(0 to 3); +signal mm_xu_quiesce_d, mm_xu_quiesce_q : std_ulogic_vector(0 to thdid_width-1); +signal inval_quiesce_b : std_ulogic_vector(0 to thdid_width-1); +signal inv_seq_local_done : std_ulogic; +signal inv_seq_snoop_done : std_ulogic; +signal inv_seq_hold_req : std_ulogic_vector(0 to thdid_width-1); +signal inv_seq_hold_done : std_ulogic_vector(0 to thdid_width-1); +signal inv_seq_tlbi_load : std_ulogic; +signal inv_seq_tlbi_complete : std_ulogic; +signal inv_seq_tlb_snoop_val : std_ulogic; +signal inv_seq_htw_load : std_ulogic; +signal inv_seq_ierat_snoop_val : std_ulogic; +signal inv_seq_derat_snoop_val : std_ulogic; +signal inv_seq_snoop_inprogress : std_ulogic; +signal inv_seq_snoop_inprogress_q : std_ulogic_vector(0 to 1); +signal inv_seq_local_inprogress : std_ulogic; +signal inv_seq_local_barrier_set : std_ulogic; +signal inv_seq_global_barrier_set : std_ulogic; +signal inv_seq_local_barrier_done : std_ulogic; +signal inv_seq_global_barrier_done : std_ulogic; +signal inv_seq_idle : std_ulogic; +signal inval_snoop_forme : std_ulogic; +signal inval_snoop_local_reject : std_ulogic; +signal ex6_size_large : std_ulogic; +signal inv_seq_tlb0fi_inprogress : std_ulogic; +signal inv_seq_tlb0fi_inprogress_q : std_ulogic_vector(0 to 1); +signal inv_seq_tlb0fi_done : std_ulogic; +signal ex3_ea_hold : std_ulogic; +signal htw_lsu_req_taken_sig : std_ulogic; +signal inv_seq_tlbwe_inprogress : std_ulogic; +signal inv_seq_tlbwe_inprogress_q : std_ulogic_vector(0 to 1); +signal inv_seq_tlbwe_snoop_done : std_ulogic; +signal tlbwe_back_inv_tid_nz : std_ulogic; +signal tlbwe_back_inv_d, tlbwe_back_inv_q : std_ulogic_vector(0 to thdid_width+1); +signal tlbwe_back_inv_addr_d, tlbwe_back_inv_addr_q : std_ulogic_vector(52-epn_width to 51); +signal tlbwe_back_inv_attr_d, tlbwe_back_inv_attr_q : std_ulogic_vector(0 to 34); +signal back_inv_tid_nz : std_ulogic; +signal ex6_tid_nz : std_ulogic; +signal ex2_rs_pgsize_not_supp : std_ulogic; +signal mas6_isize_not_supp : std_ulogic_vector(0 to thdid_width-1); +signal ex2_hv_state : std_ulogic; +signal ex2_priv_state : std_ulogic; +signal ex2_dgtmi_state : std_ulogic; +signal ex5_hv_state : std_ulogic; +signal ex5_priv_state : std_ulogic; +signal ex5_dgtmi_state : std_ulogic; +signal unused_dc : std_ulogic_vector(0 to 12); +-- synopsys translate_off +-- synopsys translate_on +-- Pervasive +signal pc_sg_1 : std_ulogic; +signal pc_sg_0 : std_ulogic; +signal pc_fce_1 : std_ulogic; +signal pc_fce_0 : std_ulogic; +signal pc_func_sl_thold_1 : std_ulogic; +signal pc_func_sl_thold_0 : std_ulogic; +signal pc_func_sl_thold_0_b : std_ulogic; +signal pc_func_slp_sl_thold_1 : std_ulogic; +signal pc_func_slp_sl_thold_0 : std_ulogic; +signal pc_func_slp_sl_thold_0_b : std_ulogic; +signal pc_func_slp_nsl_thold_1 : std_ulogic; +signal pc_func_slp_nsl_thold_0 : std_ulogic; +signal pc_func_slp_nsl_thold_0_b : std_ulogic; +signal pc_func_sl_force : std_ulogic; +signal pc_func_slp_sl_force : std_ulogic; +signal pc_func_slp_nsl_force : std_ulogic; +signal siv : std_ulogic_vector(0 to scan_right); +signal sov : std_ulogic_vector(0 to scan_right); +signal tidn : std_ulogic; +signal tiup : std_ulogic; +begin +tidn <= '0'; +tiup <= '1'; +xu_mm_ccr2_notlb_d <= (others => xu_mm_ccr2_notlb); +power_managed_d(0) <= ac_an_power_managed; +power_managed_d(1) <= power_managed_q(1); +power_managed_d(2) <= power_managed_q(2); +power_managed_d(3) <= power_managed_q(3); +mm_xu_quiesce <= mm_xu_quiesce_q; +mm_xu_quiesce_d <= tlb_req_quiesce and tlb_ctl_quiesce and + htw_quiesce and + not inval_quiesce_b; +-- not quiesced +inval_quiesce_b <= ( (0 to thdid_width-1 => or_reduce(inv_seq_q)) and ex6_valid_q(0 to thdid_width-1) ); +ex1_valid_d <= xu_mm_rf1_val and not(xu_rf1_flush); +ex1_ttype_d(0 to ttype_width-3) <= xu_mm_rf1_is_tlbilx & xu_mm_rf1_is_tlbivax & xu_mm_rf1_is_eratilx & xu_mm_rf1_is_erativax; +ex1_state_d(0) <= or_reduce(xu_mm_msr_gs and xu_mm_rf1_val); +ex1_state_d(1) <= or_reduce(xu_mm_msr_pr and xu_mm_rf1_val); +ex1_t_d <= xu_mm_rf1_t; +ex2_valid_d <= ex1_valid_q and not(xu_ex1_flush); +ex2_ttype_d(0 to ttype_width-3) <= ex1_ttype_q(0 to ttype_width-3); +ex2_ttype_d(ttype_width-2 to ttype_width-1) <= xu_mm_ex1_is_csync & xu_mm_ex1_is_isync; +ex2_rs_is_d <= xu_mm_ex1_rs_is; +-- RS(55) -> Local rs_is(0) +-- RS(56:57) -> IS rs_is(1 to 2) +-- RS(58:59) -> Class rs_is(3 to 4) +-- RS(60:63) -> Size rs_is(5 to 8) +ex2_state_d <= ex1_state_q; +ex2_t_d <= ex1_t_q; +-- ex2 effective addr capture latch.. hold addr until inv_seq done with it +ex3_ea_hold <= (or_reduce(ex3_valid_q) and or_reduce(ex3_ttype_q(0 to 3))) + or (or_reduce(ex4_valid_q) and or_reduce(ex4_ttype_q(0 to 3))) + or (or_reduce(ex5_valid_q) and or_reduce(ex5_ttype_q(0 to 3))) + or (or_reduce(ex6_valid_q) and or_reduce(ex6_ttype_q(0 to 3))); +ex3_ea_d <= (ex3_ea_q and (64-rs_data_width to 63 => ex3_ea_hold)) + or (xu_mm_ex2_eff_addr and (64-rs_data_width to 63 => not ex3_ea_hold)); +ex2_hv_state <= not ex2_state_q(0) and not ex2_state_q(1); +ex2_priv_state <= not ex2_state_q(1); +ex2_dgtmi_state <= or_reduce(ex2_valid_q and xu_mm_epcr_dgtmi_q); +ex3_valid_d <= ex2_valid_q and not(xu_ex2_flush); +--ex3_ttype_d <= ex2_ttype_q; +ex3_ttype_d(0 to ttype_width-3) <= ex2_ttype_q(0 to ttype_width-3); +ex3_ttype_d(ttype_width-2) <= (ex2_ttype_q(ttype_width-2) and not mmucr1_csinv_q(0)); +ex3_ttype_d(ttype_width-1) <= (ex2_ttype_q(ttype_width-1) and not mmucr1_csinv_q(1)); +ex3_rs_is_d <= ex2_rs_is_q; +ex3_state_d <= ex2_state_q; +ex3_t_d <= ex2_t_q; +ex3_flush_req_d <= (ex2_valid_q and not(xu_ex2_flush)) + when ( ex2_ttype_q(0 to 3)/="0000" and + ( inv_seq_idle='0' or + (ex3_valid_q/="0000" and ex3_ttype_q(0 to 3)/="0000") or + (ex4_valid_q/="0000" and ex4_ttype_q(0 to 3)/="0000") or + (ex5_valid_q/="0000" and ex5_ttype_q(0 to 3)/="0000") or + (ex6_valid_q/="0000" and ex6_ttype_q(0 to 3)/="0000") ) ) + else tlb_ctl_ex2_flush_req; +ex4_valid_d <= ex3_valid_q and not(xu_ex3_flush); +ex4_ttype_d <= ex3_ttype_q; +ex4_rs_is_d <= ex3_rs_is_q; +ex4_state_d <= ex3_state_q; +ex4_t_d <= ex3_t_q; +ex5_valid_d <= ex4_valid_q and not(xu_ex4_flush); +ex5_ttype_d <= ex4_ttype_q; +ex5_rs_is_d <= ex4_rs_is_q; +ex5_state_d <= ex4_state_q; +ex5_t_d <= ex4_t_q; +ex5_hv_state <= not ex5_state_q(0) and not ex5_state_q(1); +ex5_priv_state <= not ex5_state_q(1); +ex5_dgtmi_state <= or_reduce(ex5_valid_q and xu_mm_epcr_dgtmi_q); +-- these are ex6 capture latches.. hold op until inv_seq done with it +ex6_valid_d <= "0000" when inv_seq_local_done='1' + else (ex5_valid_q and not(xu_ex5_flush)) when ( ex6_valid_q="0000" and + ((ex5_ttype_q(0)='1' and ex5_priv_state='1' and ex5_dgtmi_state='0') or + (ex5_ttype_q(0)='1' and ex5_hv_state='1' and ex5_dgtmi_state='1') or + (or_reduce(ex5_ttype_q(1 to 3))='1' and ex5_hv_state='1')) ) + else ex6_valid_q; +--ttype <= tlbilx & tlbivax & eratilx & erativax & csync & isync; +ex6_ttype_d <= ex5_ttype_q when (ex5_valid_q /= "0000" and ex5_ttype_q(0 to 3)/="0000" and ex6_valid_q="0000") + else ex6_ttype_q; +-- ttype -> 0 1 2 3 +-- sources for ttype -> tlbilx tlbivax eratilx erativax +-- RS(55) -> Local rs_is(0) 1 0 1 0 +-- RS(56:57) -> IS rs_is(1 to 2) f(T) 11 f(T) RS(56:57) +-- RS(58:59) -> Class rs_is(3 to 4) g(T) 00 g(T) RS(58:59) +-- RS(60:63) -> Size rs_is(5 to 8) mas6 mas6 n/a RS(60:63) +-- TS (state(1)) mas6 mas6 mmucr0 mmucr0 +-- TID mas6 mas6 mmucr0 mmucr0 +-- GS (state(0)) mas5 mas5 mmucr0 mmucr0 +-- LPID mas5 mas5 lpidr lpidr +-- IND mas6 mas6 0 0 +ex6_isel_d <= '1' & ex5_rs_is_q(3 to 4) when (ex5_valid_q /= "0000" and ex5_ttype_q(3)='1' and ex5_rs_is_q(1 to 2)="10" and ex6_valid_q="0000") + else '0' & ex5_rs_is_q(1 to 2) when (ex5_valid_q /= "0000" and ex5_ttype_q(3)='1' and ex5_rs_is_q(1 to 2)/="10" and ex6_valid_q="0000") + else ex5_t_q(0 to 2) when (ex5_valid_q /= "0000" and ex5_ttype_q(2)='1' and ex6_valid_q="0000") + else "011" when (ex5_valid_q /= "0000" and ex5_ttype_q(1)='1' and ex6_valid_q="0000") + else ex5_t_q(0 to 2) when (ex5_valid_q /= "0000" and ex5_ttype_q(0)='1' and ex6_valid_q="0000") + else ex6_isel_q; +-- T field from tlbilx/eratilx is 0=all, 1=pid, 2=resvd/GS, 3=address, 4-7=class +-- ex1_rs_is(0 to 9) from erativax instr. +-- RS(55) -> ex1_rs_is(0) -> snoop_attr(0) -> Local +-- RS(56:57) -> ex1_rs_is(1:2) -> snoop_attr(0:1) -> IS +-- RS(58:59) -> ex1_rs_is(3:4) -> snoop_attr(2:3) -> Class +-- n/a -> n/a -> snoop_attr(4:5) -> State +-- n/a -> n/a -> snoop_attr(6:13) -> TID(6:13) +-- RS(60:63) -> ex1_rs_is(5:8) -> snoop_attr(14:17) -> Size +-- n/a -> n/a -> snoop_attr(20:25) -> TID(0:5) +-- erat snoop_attr: +-- 0 -> Local +-- 1:3 -> IS/Class: 0=all, 1=tid, 2=gs, 3=epn, 4=class0, 5=class1, 6=class2, 7=class3 +-- 4:5 -> GS/TS +-- 6:13 -> TID(6:13) +-- 14:17 -> Size +-- 18 -> TID_NZ +-- 19 -> mmucsr0.tlb0fi +-- 20:25 -> TID(0:5) +ex6_size_d <= ex5_rs_is_q(5 to 8) when (ex5_valid_q /= "0000" and ex5_ttype_q(3)='1' and ex6_valid_q="0000") + else "0000" when (ex5_valid_q /= "0000" and ex5_ttype_q(2)='1' and ex6_valid_q="0000") + else mas6_0_isize when (ex5_valid_q(0)='1' and ex5_ttype_q(0 to 1)/="00" and ex6_valid_q="0000") + else mas6_1_isize when (ex5_valid_q(1)='1' and ex5_ttype_q(0 to 1)/="00" and ex6_valid_q="0000") + else mas6_2_isize when (ex5_valid_q(2)='1' and ex5_ttype_q(0 to 1)/="00" and ex6_valid_q="0000") + else mas6_3_isize when (ex5_valid_q(3)='1' and ex5_ttype_q(0 to 1)/="00" and ex6_valid_q="0000") + else ex6_size_q; +ex6_size_large <= '1' when (ex6_size_q=TLB_PgSize_64KB or ex6_size_q=TLB_PgSize_1MB or + ex6_size_q=TLB_PgSize_16MB or ex6_size_q=TLB_PgSize_256MB or ex6_size_q=TLB_PgSize_1GB) + else '0'; +-- mmucr0: 0:1-ExtClass, 2:3-TGS/TS, 4:5-TLBSel, 6:19-TID, +ex6_gs_d <= mmucr0_0(2) when (ex5_valid_q(0)='1' and ex5_ttype_q(2 to 3)/="00" and ex6_valid_q="0000") + else mmucr0_1(2) when (ex5_valid_q(1)='1' and ex5_ttype_q(2 to 3)/="00" and ex6_valid_q="0000") + else mmucr0_2(2) when (ex5_valid_q(2)='1' and ex5_ttype_q(2 to 3)/="00" and ex6_valid_q="0000") + else mmucr0_3(2) when (ex5_valid_q(3)='1' and ex5_ttype_q(2 to 3)/="00" and ex6_valid_q="0000") + else mas5_0_sgs when (ex5_valid_q(0)='1' and ex5_ttype_q(0 to 1)/="00" and ex6_valid_q="0000") + else mas5_1_sgs when (ex5_valid_q(1)='1' and ex5_ttype_q(0 to 1)/="00" and ex6_valid_q="0000") + else mas5_2_sgs when (ex5_valid_q(2)='1' and ex5_ttype_q(0 to 1)/="00" and ex6_valid_q="0000") + else mas5_3_sgs when (ex5_valid_q(3)='1' and ex5_ttype_q(0 to 1)/="00" and ex6_valid_q="0000") + else ex6_gs_q; +ex6_ts_d <= mmucr0_0(3) when (ex5_valid_q(0)='1' and ex5_ttype_q(2 to 3)/="00" and ex6_valid_q="0000") + else mmucr0_1(3) when (ex5_valid_q(1)='1' and ex5_ttype_q(2 to 3)/="00" and ex6_valid_q="0000") + else mmucr0_2(3) when (ex5_valid_q(2)='1' and ex5_ttype_q(2 to 3)/="00" and ex6_valid_q="0000") + else mmucr0_3(3) when (ex5_valid_q(3)='1' and ex5_ttype_q(2 to 3)/="00" and ex6_valid_q="0000") + else mas6_0_sas when (ex5_valid_q(0)='1' and ex5_ttype_q(0 to 1)/="00" and ex6_valid_q="0000") + else mas6_1_sas when (ex5_valid_q(1)='1' and ex5_ttype_q(0 to 1)/="00" and ex6_valid_q="0000") + else mas6_2_sas when (ex5_valid_q(2)='1' and ex5_ttype_q(0 to 1)/="00" and ex6_valid_q="0000") + else mas6_3_sas when (ex5_valid_q(3)='1' and ex5_ttype_q(0 to 1)/="00" and ex6_valid_q="0000") + else ex6_ts_q; +ex6_ind_d <= '0' when (ex5_valid_q(0)='1' and ex5_ttype_q(2 to 3)/="00" and ex6_valid_q="0000") + else '0' when (ex5_valid_q(1)='1' and ex5_ttype_q(2 to 3)/="00" and ex6_valid_q="0000") + else '0' when (ex5_valid_q(2)='1' and ex5_ttype_q(2 to 3)/="00" and ex6_valid_q="0000") + else '0' when (ex5_valid_q(3)='1' and ex5_ttype_q(2 to 3)/="00" and ex6_valid_q="0000") + else mas6_0_sind when (ex5_valid_q(0)='1' and ex5_ttype_q(0 to 1)/="00" and ex6_valid_q="0000") + else mas6_1_sind when (ex5_valid_q(1)='1' and ex5_ttype_q(0 to 1)/="00" and ex6_valid_q="0000") + else mas6_2_sind when (ex5_valid_q(2)='1' and ex5_ttype_q(0 to 1)/="00" and ex6_valid_q="0000") + else mas6_3_sind when (ex5_valid_q(3)='1' and ex5_ttype_q(0 to 1)/="00" and ex6_valid_q="0000") + else ex6_ind_q; +ex6_pid_d <= mmucr0_0(6 to 19) when (ex5_valid_q(0)='1' and ex5_ttype_q(2 to 3)/="00" and ex6_valid_q="0000") + else mmucr0_1(6 to 19) when (ex5_valid_q(1)='1' and ex5_ttype_q(2 to 3)/="00" and ex6_valid_q="0000") + else mmucr0_2(6 to 19) when (ex5_valid_q(2)='1' and ex5_ttype_q(2 to 3)/="00" and ex6_valid_q="0000") + else mmucr0_3(6 to 19) when (ex5_valid_q(3)='1' and ex5_ttype_q(2 to 3)/="00" and ex6_valid_q="0000") + else mas6_0_spid when (ex5_valid_q(0)='1' and ex5_ttype_q(0 to 1)/="00" and ex6_valid_q="0000") + else mas6_1_spid when (ex5_valid_q(1)='1' and ex5_ttype_q(0 to 1)/="00" and ex6_valid_q="0000") + else mas6_2_spid when (ex5_valid_q(2)='1' and ex5_ttype_q(0 to 1)/="00" and ex6_valid_q="0000") + else mas6_3_spid when (ex5_valid_q(3)='1' and ex5_ttype_q(0 to 1)/="00" and ex6_valid_q="0000") + else ex6_pid_q; +ex6_lpid_d <= lpidr_q when (ex5_valid_q(0)='1' and ex5_ttype_q(2 to 3)/="00" and ex6_valid_q="0000") + else lpidr_q when (ex5_valid_q(1)='1' and ex5_ttype_q(2 to 3)/="00" and ex6_valid_q="0000") + else lpidr_q when (ex5_valid_q(2)='1' and ex5_ttype_q(2 to 3)/="00" and ex6_valid_q="0000") + else lpidr_q when (ex5_valid_q(3)='1' and ex5_ttype_q(2 to 3)/="00" and ex6_valid_q="0000") + else mas5_0_slpid when (ex5_valid_q(0)='1' and ex5_ttype_q(0 to 1)/="00" and ex6_valid_q="0000") + else mas5_1_slpid when (ex5_valid_q(1)='1' and ex5_ttype_q(0 to 1)/="00" and ex6_valid_q="0000") + else mas5_2_slpid when (ex5_valid_q(2)='1' and ex5_ttype_q(0 to 1)/="00" and ex6_valid_q="0000") + else mas5_3_slpid when (ex5_valid_q(3)='1' and ex5_ttype_q(0 to 1)/="00" and ex6_valid_q="0000") + else ex6_lpid_q; +-- an_ac_back_inv_q: 0=valid b-1, 1=target b-1, 2=valid b, 3=target b, 4=L, 5=GS, 6=IND, 7=local, 8=reject +-- iu barrier op shadow status +local_barrier_d <= (local_barrier_q and not(ex6_valid_q)) when inv_seq_local_barrier_done='1' + else (ex6_valid_q or local_barrier_q) when inv_seq_local_barrier_set='1' + else local_barrier_q; +global_barrier_d <= (others => '0') when ((inv_seq_global_barrier_done='1' and an_ac_back_inv_q(7)='1') or inval_snoop_local_reject='1') + else (ex6_valid_q or global_barrier_q) when inv_seq_global_barrier_set='1' + else global_barrier_q; +barrier_done_d <= (local_barrier_q and ex6_valid_q) when inv_seq_local_barrier_done='1' + else global_barrier_q when ((inv_seq_global_barrier_done='1' and an_ac_back_inv_q(7)='1') or inval_snoop_local_reject='1') + else tlb_ctl_barrier_done; +-- Illegal instr logic +ex2_rs_pgsize_not_supp <= '0' when (ex2_rs_is_q(5 to 8)=TLB_PgSize_4KB or ex2_rs_is_q(5 to 8)=TLB_PgSize_64KB or + ex2_rs_is_q(5 to 8)=TLB_PgSize_1MB or ex2_rs_is_q(5 to 8)=TLB_PgSize_16MB or + ex2_rs_is_q(5 to 8)=TLB_PgSize_1GB ) else '1'; +mas6_isize_not_supp(0) <= '0' when ((mas6_0_isize=TLB_PgSize_4KB or mas6_0_isize=TLB_PgSize_64KB or + mas6_0_isize=TLB_PgSize_1MB or mas6_0_isize=TLB_PgSize_16MB or + mas6_0_isize=TLB_PgSize_1GB) and mas6_0_sind='0') + or ((mas6_0_isize=TLB_PgSize_1MB or mas6_0_isize=TLB_PgSize_256MB) and mas6_0_sind='1') + else '1'; +mas6_isize_not_supp(1) <= '0' when ((mas6_1_isize=TLB_PgSize_4KB or mas6_1_isize=TLB_PgSize_64KB or + mas6_1_isize=TLB_PgSize_1MB or mas6_1_isize=TLB_PgSize_16MB or + mas6_1_isize=TLB_PgSize_1GB) and mas6_1_sind='0') + or ((mas6_1_isize=TLB_PgSize_1MB or mas6_1_isize=TLB_PgSize_256MB) and mas6_1_sind='1') + else '1'; +mas6_isize_not_supp(2) <= '0' when ((mas6_2_isize=TLB_PgSize_4KB or mas6_2_isize=TLB_PgSize_64KB or + mas6_2_isize=TLB_PgSize_1MB or mas6_2_isize=TLB_PgSize_16MB or + mas6_2_isize=TLB_PgSize_1GB) and mas6_2_sind='0') + or ((mas6_2_isize=TLB_PgSize_1MB or mas6_2_isize=TLB_PgSize_256MB) and mas6_2_sind='1') + else '1'; +mas6_isize_not_supp(3) <= '0' when ((mas6_3_isize=TLB_PgSize_4KB or mas6_3_isize=TLB_PgSize_64KB or + mas6_3_isize=TLB_PgSize_1MB or mas6_3_isize=TLB_PgSize_16MB or + mas6_3_isize=TLB_PgSize_1GB) and mas6_3_sind='0') + or ((mas6_3_isize=TLB_PgSize_1MB or mas6_3_isize=TLB_PgSize_256MB) and mas6_3_sind='1') + else '1'; +-- T field from tlbilx/eratilx is 0=all, 1=pid, 2=resvd/GS, 3=address, 4-7=class +illeg_instr_d <= ( ex2_valid_q and mas6_isize_not_supp and (0 to 3 => (ex2_ttype_q(1) and ex2_hv_state)) ) + or ( ex2_valid_q and mas6_isize_not_supp and (0 to 3 => (ex2_ttype_q(0) and Eq(ex2_t_q,"011") and + (ex2_hv_state or (ex2_priv_state and not ex2_dgtmi_state)))) ) + or ( ex2_valid_q and (0 to 3 => (ex2_ttype_q(3) and ex2_hv_state and ex2_rs_pgsize_not_supp)) ) + or ( ex2_valid_q and (0 to 3 => (ex2_ttype_q(2) and ex2_hv_state and ex2_t_q(0) and mmucr1_q(pos_ictid) and mmucr1_q(pos_dctid))) ) + or ( tlb_ctl_ex2_illeg_instr ); +-- invalidate sequencer +--Inv_Sequencer: PROCESS (inv_seq_q, por_seq_q, an_ac_back_inv, an_ac_back_inv_target, +-- ex6_valid_q, ex6_ttype_q) +Inv_Sequencer: PROCESS (inv_seq_q, inval_snoop_forme, xu_mm_lmq_stq_empty, iu_mm_lmq_empty, hold_ack_q, lsu_tokens_q, xu_mm_ccr2_notlb_q(0), + snoop_ack_q, ex6_valid_q, ex6_ttype_q(0 to 3), ex6_ind_q, ex6_isel_q, + mmucsr0_tlb0fi, + tlbwe_back_inv_q(thdid_width+1), + an_ac_back_inv_q(6), an_ac_back_inv_addr_q(54 to 55), htw_lsu_req_valid, lsu_req_q, + power_managed_q(0), power_managed_q(2), power_managed_q(3)) +BEGIN +inv_seq_idle <= '0'; +inv_seq_snoop_inprogress <= '0'; +inv_seq_local_inprogress <= '0'; +inv_seq_local_barrier_set <= '0'; +inv_seq_global_barrier_set <= '0'; +inv_seq_local_barrier_done <= '0'; +inv_seq_global_barrier_done <= '0'; +inv_seq_snoop_done <= '0'; +inv_seq_local_done <= '0'; +inv_seq_tlbi_load <= '0'; +inv_seq_tlbi_complete <= '0'; +inv_seq_htw_load <= '0'; +htw_lsu_req_taken_sig <= '0'; +inv_seq_hold_req(0 to 3) <= (others => '0'); +inv_seq_hold_done(0 to 3) <= (others => '0'); +inv_seq_tlb_snoop_val <= '0'; +inv_seq_ierat_snoop_val <= '0'; +inv_seq_derat_snoop_val <= '0'; +inv_seq_tlb0fi_inprogress <= '0'; +inv_seq_tlb0fi_done <= '0'; +inv_seq_tlbwe_snoop_done <= '0'; +inv_seq_tlbwe_inprogress <= '0'; +CASE inv_seq_q IS + WHEN InvSeq_Idle => + + inv_seq_idle <= '1'; + if inval_snoop_forme='1' then + inv_seq_snoop_inprogress <= '1'; + inv_seq_hold_req(0 to 3) <= "1111"; + inv_seq_d <= InvSeq_Stg8; + elsif htw_lsu_req_valid='1' then + inv_seq_d <= InvSeq_Stg31; + elsif ex6_valid_q/="0000" and (ex6_ttype_q(1)='1' or ex6_ttype_q(3)='1') then + inv_seq_local_inprogress <= '1'; + inv_seq_global_barrier_set <= '1'; + inv_seq_d <= InvSeq_Stg1; + elsif ex6_valid_q/="0000" and (ex6_ttype_q(0)='1' or ex6_ttype_q(2)='1') then + inv_seq_hold_req(0 to 3) <= "1111"; + inv_seq_local_inprogress <= '1'; + inv_seq_local_barrier_set <= '1'; + inv_seq_d <= InvSeq_Stg2; + elsif mmucsr0_tlb0fi='1' then + inv_seq_hold_req(0 to 3) <= "1111"; + inv_seq_tlb0fi_inprogress <= '1'; + inv_seq_d <= InvSeq_Stg16; + elsif tlbwe_back_inv_q(thdid_width+1)='1' then + inv_seq_hold_req(0 to 3) <= "1111"; + inv_seq_tlbwe_inprogress <= '1'; + inv_seq_d <= InvSeq_Stg24; + else + inv_seq_d <= InvSeq_Idle; + end if; + WHEN InvSeq_Stg1 => + inv_seq_local_inprogress <= '1'; + if lsu_tokens_q/="00" then + inv_seq_tlbi_load <= '1'; + inv_seq_local_done <= '1'; + inv_seq_d <= InvSeq_Idle; + else + inv_seq_d <= InvSeq_Stg1; + end if; + WHEN InvSeq_Stg2 => + inv_seq_local_inprogress <= '1'; + if hold_ack_q="1111" then + inv_seq_d <= InvSeq_Stg3; + elsif htw_lsu_req_valid='1' then + inv_seq_d <= InvSeq_Stg23; + else + inv_seq_d <= InvSeq_Stg2; + end if; + + WHEN InvSeq_Stg3 => + inv_seq_local_inprogress <= '1'; + if iu_mm_lmq_empty='1' and xu_mm_lmq_stq_empty='1' and xu_mm_ccr2_notlb_q(0)=MMU_Mode_Value and ex6_ttype_q(0)='1' then + inv_seq_d <= InvSeq_Stg4; + elsif iu_mm_lmq_empty='1' and xu_mm_lmq_stq_empty='1' then + inv_seq_d <= InvSeq_Stg6; + else + inv_seq_d <= InvSeq_Stg3; + end if; + + WHEN InvSeq_Stg4 => + inv_seq_local_inprogress <= '1'; + inv_seq_tlb_snoop_val <= '1'; + inv_seq_d <= InvSeq_Stg5; + + WHEN InvSeq_Stg5 => + inv_seq_local_inprogress <= '1'; + if snoop_ack_q(2)='1' then + inv_seq_d <= InvSeq_Stg6; + else + inv_seq_d <= InvSeq_Stg5; + end if; + + WHEN InvSeq_Stg6 => + inv_seq_local_inprogress <= '1'; + inv_seq_ierat_snoop_val <= not(ex6_ind_q and Eq(ex6_isel_q,"011")); + inv_seq_derat_snoop_val <= not(ex6_ind_q and Eq(ex6_isel_q,"011")); + inv_seq_d <= InvSeq_Stg7; + + WHEN InvSeq_Stg7 => + inv_seq_local_inprogress <= '1'; + if (snoop_ack_q(0 to 1)="11" or (ex6_ind_q and Eq(ex6_isel_q,"011"))='1') then + inv_seq_local_done <= '1'; + inv_seq_local_barrier_done <= '1'; + inv_seq_hold_done(0 to 3) <= "1111"; + inv_seq_d <= InvSeq_Idle; + else + inv_seq_d <= InvSeq_Stg7; + end if; + + WHEN InvSeq_Stg8 => + inv_seq_snoop_inprogress <= '1'; + if (hold_ack_q="1111" or (power_managed_q(0)='1' and power_managed_q(2)='1')) then + inv_seq_d <= InvSeq_Stg9; + elsif htw_lsu_req_valid='1' then + inv_seq_d <= InvSeq_Stg28; + else + inv_seq_d <= InvSeq_Stg8; + end if; + + WHEN InvSeq_Stg9 => + inv_seq_snoop_inprogress <= '1'; + inv_seq_d <= InvSeq_Stg10; + + WHEN InvSeq_Stg10 => + inv_seq_snoop_inprogress <= '1'; + if (power_managed_q(0)='1' and power_managed_q(3)='1') then + inv_seq_d <= InvSeq_Stg14; + elsif ( (iu_mm_lmq_empty='1' or power_managed_q(0)='1') and + (xu_mm_lmq_stq_empty='1' or (power_managed_q(0)='1' and power_managed_q(2)='1')) and + xu_mm_ccr2_notlb_q(0)=MMU_Mode_Value ) then + inv_seq_d <= InvSeq_Stg11; + elsif ( (iu_mm_lmq_empty='1' or power_managed_q(0)='1') and + (xu_mm_lmq_stq_empty='1' or (power_managed_q(0)='1' and power_managed_q(2)='1')) ) then + inv_seq_d <= InvSeq_Stg13; + else + inv_seq_d <= InvSeq_Stg10; + end if; + + WHEN InvSeq_Stg11 => + inv_seq_snoop_inprogress <= '1'; + inv_seq_tlb_snoop_val <= '1'; + inv_seq_d <= InvSeq_Stg12; + + WHEN InvSeq_Stg12 => + inv_seq_snoop_inprogress <= '1'; + if snoop_ack_q(2)='1' or (power_managed_q(0)='1' and power_managed_q(2)='1') then + inv_seq_d <= InvSeq_Stg13; + else + inv_seq_d <= InvSeq_Stg12; + end if; + + WHEN InvSeq_Stg13 => + inv_seq_snoop_inprogress <= '1'; + inv_seq_ierat_snoop_val <= not(an_ac_back_inv_q(6) and Eq(an_ac_back_inv_addr_q(54 to 55),"11")); + inv_seq_derat_snoop_val <= not(an_ac_back_inv_q(6) and Eq(an_ac_back_inv_addr_q(54 to 55),"11")); + inv_seq_d <= InvSeq_Stg14; + + WHEN InvSeq_Stg14 => + inv_seq_snoop_inprogress <= '1'; + if (power_managed_q(0)='1' and power_managed_q(2)='1') then + inv_seq_tlbi_complete <= '1'; + inv_seq_d <= InvSeq_Stg15; + elsif lsu_tokens_q/="00" and (snoop_ack_q(0 to 1)="11" or (an_ac_back_inv_q(6) and Eq(an_ac_back_inv_addr_q(54 to 55),"11"))='1') then + inv_seq_tlbi_complete <= '1'; + inv_seq_d <= InvSeq_Stg15; + else + inv_seq_d <= InvSeq_Stg14; + end if; + + WHEN InvSeq_Stg15 => + if (lsu_req_q="0000" and lsu_tokens_q/="00") or (power_managed_q(0)='1' and power_managed_q(2)='1') then + inv_seq_snoop_inprogress <= '0'; + inv_seq_snoop_done <= '1'; + inv_seq_hold_done(0 to 3) <= "1111"; + inv_seq_global_barrier_done <= '1'; + inv_seq_d <= InvSeq_Idle; + else + inv_seq_snoop_inprogress <= '1'; + inv_seq_d <= InvSeq_Stg15; + end if; + + + WHEN InvSeq_Stg16 => + inv_seq_tlb0fi_inprogress <= '1'; + if hold_ack_q="1111" then + inv_seq_d <= InvSeq_Stg17; + elsif htw_lsu_req_valid='1' then + inv_seq_d <= InvSeq_Stg22; + else + inv_seq_d <= InvSeq_Stg16; + end if; + + WHEN InvSeq_Stg17 => + inv_seq_tlb0fi_inprogress <= '1'; + if iu_mm_lmq_empty='1' and xu_mm_lmq_stq_empty='1' and xu_mm_ccr2_notlb_q(0)=MMU_Mode_Value then + inv_seq_d <= InvSeq_Stg18; + elsif iu_mm_lmq_empty='1' and xu_mm_lmq_stq_empty='1' then + inv_seq_d <= InvSeq_Stg20; + else + inv_seq_d <= InvSeq_Stg17; + end if; + + WHEN InvSeq_Stg18 => + inv_seq_tlb0fi_inprogress <= '1'; + inv_seq_tlb_snoop_val <= '1'; + inv_seq_d <= InvSeq_Stg19; + + WHEN InvSeq_Stg19 => + inv_seq_tlb0fi_inprogress <= '1'; + if snoop_ack_q(2)='1' then + inv_seq_d <= InvSeq_Stg20; + else + inv_seq_d <= InvSeq_Stg19; + end if; + + WHEN InvSeq_Stg20 => + inv_seq_tlb0fi_inprogress <= '1'; + inv_seq_ierat_snoop_val <= '1'; + inv_seq_derat_snoop_val <= '1'; + inv_seq_d <= InvSeq_Stg21; + + WHEN InvSeq_Stg21 => + if (snoop_ack_q(0 to 1)="11") then + inv_seq_tlb0fi_inprogress <= '0'; + inv_seq_tlb0fi_done <= '1'; + inv_seq_hold_done(0 to 3) <= "1111"; + inv_seq_d <= InvSeq_Idle; + else + inv_seq_tlb0fi_inprogress <= '1'; + inv_seq_d <= InvSeq_Stg21; + end if; + WHEN InvSeq_Stg22 => + inv_seq_tlb0fi_inprogress <= '1'; + if lsu_tokens_q/="00" then + inv_seq_htw_load <= '1'; + htw_lsu_req_taken_sig <= '1'; + inv_seq_d <= InvSeq_Stg16; + else + inv_seq_d <= InvSeq_Stg22; + end if; + + WHEN InvSeq_Stg23 => + inv_seq_local_inprogress <= '1'; + if lsu_tokens_q/="00" then + inv_seq_htw_load <= '1'; + htw_lsu_req_taken_sig <= '1'; + inv_seq_d <= InvSeq_Stg2; + else + inv_seq_d <= InvSeq_Stg23; + end if; + + WHEN InvSeq_Stg24 => + inv_seq_tlbwe_inprogress <= '1'; + if hold_ack_q="1111" then + inv_seq_d <= InvSeq_Stg25; + elsif htw_lsu_req_valid='1' then + inv_seq_d <= InvSeq_Stg29; + else + inv_seq_d <= InvSeq_Stg24; + end if; + + WHEN InvSeq_Stg25 => + inv_seq_tlbwe_inprogress <= '1'; + if iu_mm_lmq_empty='1' and xu_mm_lmq_stq_empty='1' then + inv_seq_d <= InvSeq_Stg26; + else + inv_seq_d <= InvSeq_Stg25; + end if; + + WHEN InvSeq_Stg26 => + inv_seq_tlbwe_inprogress <= '1'; + inv_seq_ierat_snoop_val <= '1'; + inv_seq_derat_snoop_val <= '1'; + inv_seq_d <= InvSeq_Stg27; + + WHEN InvSeq_Stg27 => + if (snoop_ack_q(0 to 1)="11") then + inv_seq_tlbwe_inprogress <= '0'; + inv_seq_tlbwe_snoop_done <= '1'; + inv_seq_hold_done(0 to 3) <= "1111"; + inv_seq_d <= InvSeq_Idle; + else + inv_seq_tlbwe_inprogress <= '1'; + inv_seq_d <= InvSeq_Stg27; + end if; + WHEN InvSeq_Stg29 => + inv_seq_tlbwe_inprogress <= '1'; + if lsu_tokens_q/="00" then + inv_seq_htw_load <= '1'; + htw_lsu_req_taken_sig <= '1'; + inv_seq_d <= InvSeq_Stg24; + else + inv_seq_d <= InvSeq_Stg29; + end if; + + WHEN InvSeq_Stg28 => + inv_seq_snoop_inprogress <= '1'; + if lsu_tokens_q/="00" then + inv_seq_htw_load <= '1'; + htw_lsu_req_taken_sig <= '1'; + inv_seq_d <= InvSeq_Stg8; + else + inv_seq_d <= InvSeq_Stg28; + end if; + WHEN InvSeq_Stg31 => + if lsu_tokens_q/="00" then + inv_seq_htw_load <= '1'; + htw_lsu_req_taken_sig <= '1'; + inv_seq_d <= InvSeq_Idle; + else + inv_seq_d <= InvSeq_Stg31; + end if; + WHEN OTHERS => + inv_seq_d <= InvSeq_Idle; + END CASE; +END PROCESS Inv_Sequencer; +hold_req_d <= inv_seq_hold_req; +hold_done_d <= inv_seq_hold_done; +inv_seq_inprogress_d(0) <= inv_seq_snoop_inprogress; +inv_seq_inprogress_d(1) <= inv_seq_snoop_inprogress; +inv_seq_inprogress_d(2) <= inv_seq_tlb0fi_inprogress; +inv_seq_inprogress_d(3) <= inv_seq_tlb0fi_inprogress; +inv_seq_inprogress_d(4) <= inv_seq_tlbwe_inprogress; +inv_seq_inprogress_d(5) <= inv_seq_tlbwe_inprogress; +inv_seq_snoop_inprogress_q(0) <= inv_seq_inprogress_q(0); +inv_seq_snoop_inprogress_q(1) <= inv_seq_inprogress_q(1); +inv_seq_tlb0fi_inprogress_q(0) <= inv_seq_inprogress_q(2); +inv_seq_tlb0fi_inprogress_q(1) <= inv_seq_inprogress_q(3); +inv_seq_tlbwe_inprogress_q(0) <= inv_seq_inprogress_q(4); +inv_seq_tlbwe_inprogress_q(1) <= inv_seq_inprogress_q(5); +hold_ack_d(0) <= '0' when (inv_seq_snoop_done='1' or inv_seq_local_done='1' or inv_seq_tlb0fi_done='1' or inv_seq_tlbwe_snoop_done='1') + else xu_mm_hold_ack(0) when hold_ack_q(0)='0' + else hold_ack_q(0); +hold_ack_d(1) <= '0' when (inv_seq_snoop_done='1' or inv_seq_local_done='1' or inv_seq_tlb0fi_done='1' or inv_seq_tlbwe_snoop_done='1') + else xu_mm_hold_ack(1) when hold_ack_q(1)='0' + else hold_ack_q(1); +hold_ack_d(2) <= '0' when (inv_seq_snoop_done='1' or inv_seq_local_done='1' or inv_seq_tlb0fi_done='1' or inv_seq_tlbwe_snoop_done='1') + else xu_mm_hold_ack(2) when hold_ack_q(2)='0' + else hold_ack_q(2); +hold_ack_d(3) <= '0' when (inv_seq_snoop_done='1' or inv_seq_local_done='1' or inv_seq_tlb0fi_done='1' or inv_seq_tlbwe_snoop_done='1') + else xu_mm_hold_ack(3) when hold_ack_q(3)='0' + else hold_ack_q(3); +mm_xu_hold_req <= hold_req_q; +mm_xu_hold_done <= hold_done_q; +mm_xu_ex3_flush_req <= ex3_flush_req_q; +mm_iu_barrier_done <= barrier_done_q; +mm_xu_illeg_instr <= illeg_instr_q; +mm_xu_local_snoop_reject <= local_reject_q; +mmq_inval_tlb0fi_done <= inv_seq_tlb0fi_done; +inval_snoop_forme <= ( an_ac_back_inv_q(2) and an_ac_back_inv_q(3) and not(power_managed_q(0) and power_managed_q(1)) and Eq(xu_mm_ccr2_notlb_q(0),MMU_Mode_Value) and not mmucr1_q(pos_tlbi_rej) ) + or ( an_ac_back_inv_q(2) and an_ac_back_inv_q(3) and not(power_managed_q(0) and power_managed_q(1)) and Eq(an_ac_back_inv_lpar_id_q,lpidr_q) ); +inval_snoop_local_reject <= ( an_ac_back_inv_q(2) and an_ac_back_inv_q(3) and not(power_managed_q(0) and power_managed_q(1)) and an_ac_back_inv_q(7) + and not Eq(an_ac_back_inv_lpar_id_q,lpidr_q) and (Eq(xu_mm_ccr2_notlb_q(0),ERAT_Mode_Value) or mmucr1_q(pos_tlbi_rej)) ); +local_reject_d <= (global_barrier_q and (0 to thdid_width-1 => inval_snoop_local_reject)); +-- an_ac_back_inv_q: 0=valid b-1, 1=target b-1, 2=valid b, 3=target b, 4=L, 5=GS, 6=IND, 7=local, 8=reject +an_ac_back_inv_d(0) <= an_ac_back_inv; +an_ac_back_inv_d(1) <= an_ac_back_inv_target; +an_ac_back_inv_d(2) <= an_ac_back_inv_q(0) when inval_snoop_forme='0' + else '0' when inv_seq_snoop_done='1' + else an_ac_back_inv_q(2); +an_ac_back_inv_d(3) <= an_ac_back_inv_q(1) when inval_snoop_forme='0' + else '0' when inv_seq_snoop_done='1' + else an_ac_back_inv_q(3); +an_ac_back_inv_d(4) <= an_ac_back_inv_lbit when inval_snoop_forme='0' + else an_ac_back_inv_q(4); +an_ac_back_inv_d(5) <= an_ac_back_inv_gs when inval_snoop_forme='0' + else an_ac_back_inv_q(5); +an_ac_back_inv_d(6) <= an_ac_back_inv_ind when inval_snoop_forme='0' + else an_ac_back_inv_q(6); +an_ac_back_inv_d(7) <= an_ac_back_inv_local when inval_snoop_forme='0' + else an_ac_back_inv_q(7); +-- bit 8 is reject back to L2 (b phase) mmu targetted, but lpar id doesn't match +an_ac_back_inv_d(8) <= ( an_ac_back_inv_q(2) and an_ac_back_inv_q(3) and not Eq(an_ac_back_inv_lpar_id_q,lpidr_q) + and (Eq(xu_mm_ccr2_notlb_q(0),ERAT_Mode_Value) or mmucr1_q(pos_tlbi_rej)) ) + or ( an_ac_back_inv_q(2) and an_ac_back_inv_q(3) and power_managed_q(0) and power_managed_q(1) ); +an_ac_back_inv_addr_d <= an_ac_back_inv_addr when inval_snoop_forme='0' + else an_ac_back_inv_addr_q; +an_ac_back_inv_lpar_id_d <= an_ac_back_inv_lpar_id when inval_snoop_forme='0' + else an_ac_back_inv_lpar_id_q; +ac_an_back_inv_reject <= an_ac_back_inv_q(8); +-- tlbwe back-invalidate to erats request from tlb_cmp +tlbwe_back_inv_d(0 to thdid_width-1) <= tlbwe_back_inv_thdid when tlbwe_back_inv_q(thdid_width)='0' + else (others => '0') when (tlbwe_back_inv_q(thdid_width)='1' and tlbwe_back_inv_q(thdid_width+1)='0' and tlb_tag5_write='0') + else (others => '0') when inv_seq_tlbwe_snoop_done='1' + else tlbwe_back_inv_q(0 to thdid_width-1); +tlbwe_back_inv_d(thdid_width) <= tlbwe_back_inv_valid when tlbwe_back_inv_q(thdid_width)='0' + else '0' when (tlbwe_back_inv_q(thdid_width)='1' and tlbwe_back_inv_q(thdid_width+1)='0' and tlb_tag5_write='0') + else '0' when inv_seq_tlbwe_snoop_done='1' + else tlbwe_back_inv_q(thdid_width); +tlbwe_back_inv_d(thdid_width+1) <= (tlbwe_back_inv_q(thdid_width) and tlb_tag5_write) when tlbwe_back_inv_q(thdid_width+1)='0' + else '0' when inv_seq_tlbwe_snoop_done='1' + else tlbwe_back_inv_q(thdid_width+1); +tlbwe_back_inv_addr_d <= tlbwe_back_inv_addr when tlbwe_back_inv_q(thdid_width)='0' + else tlbwe_back_inv_addr_q; +tlbwe_back_inv_attr_d <= tlbwe_back_inv_attr when tlbwe_back_inv_q(thdid_width)='0' + else tlbwe_back_inv_attr_q; +tlbwe_back_inv_pending <= or_reduce(tlbwe_back_inv_q(thdid_width to thdid_width+1)); +----------------------------------------------------------------------- +-- Load/Store unit request interface +----------------------------------------------------------------------- +htw_lsu_req_taken <= htw_lsu_req_taken_sig; +lsu_tokens_d <= "01" when (xu_mm_lsu_token='1' and lsu_tokens_q="00") + else "10" when (xu_mm_lsu_token='1' and lsu_tokens_q="01") + else "11" when (xu_mm_lsu_token='1' and lsu_tokens_q="10") + else "10" when (lsu_req_q/="0000" and lsu_tokens_q="11") + else "01" when (lsu_req_q/="0000" and lsu_tokens_q="10") + else "00" when (lsu_req_q/="0000" and lsu_tokens_q="01") + else lsu_tokens_q; +lsu_req_d <= "0000" when lsu_tokens_q="00" + else "1000" when inv_seq_tlbi_complete='1' + else htw_lsu_thdid when inv_seq_htw_load='1' + else ex6_valid_q when inv_seq_tlbi_load='1' + else (others => '0'); +lsu_ttype_d <= "01" when inv_seq_tlbi_complete='1' + else htw_lsu_ttype when inv_seq_htw_load='1' + else (others => '0'); +lsu_wimge_d <= htw_lsu_wimge when inv_seq_htw_load='1' + else (others => '0'); +lsu_ubits_d <= htw_lsu_u when inv_seq_htw_load='1' + else (others => '0'); +-- A2 to L2 interface req_ra epn bits for tlbivax op +-- page size mmucr1.tlbi_msb 27:30 31:33 34:35 36:39 40:43 44:47 48:51 TLB w value +-- 4K 0 EA(27:30) EA(31:33) EA(34:35) EA(36:39) EA(40:43) EA(44:47) EA(48:51) 31 +-- 64K 0 EA(27:30) EA(31:33) EA(34:35) EA(36:39) EA(40:43) EA(44:47) 0b0011 31 +-- 1M 0 EA(27:30) EA(31:33) EA(34:35) EA(36:39) EA(40:43) EA(27:30) 0b0101 27 +-- 16M 0 EA(27:30) EA(31:33) EA(34:35) EA(36:39) EA(23:26) EA(27:30) 0b0111 23 +-- 256M 0 EA(27:30) EA(31:33) EA(34:35) EA(19:22) EA(23:26) EA(27:30) 0b1001 19 +-- 1G 0 EA(27:30) EA(31:33) EA(17:18) EA(19:22) EA(23:26) EA(27:30) 0b1010 17 +-- 4K 1 EA(27:30) EA(31:33) EA(34:35) EA(36:39) EA(40:43) EA(44:47) EA(48:51) 27 +-- 64K 1 EA(27:30) EA(31:33) EA(34:35) EA(36:39) EA(40:43) EA(44:47) 0b0011 27 +-- 1M 1 EA(27:30) EA(31:33) EA(34:35) EA(36:39) EA(40:43) EA(23:26) 0b0101 23 +-- 16M 1 EA(27:30) EA(31:33) EA(34:35) EA(36:39) EA(19:22) EA(23:26) 0b0111 19 +-- 256M 1 EA(27:30) EA(31:33) EA(34:35) EA(15:18) EA(19:22) EA(23:26) 0b1001 15 +-- 1G 1 EA(27:30) EA(31:33) EA(13:14) EA(15:18) EA(19:22) EA(23:26) 0b1010 13 +-- A2 to L2 interface req_ra for tlbivax op: +-- 22:26 TID(1:5) +-- 27:51 EPN +-- 52 TS +-- 53 TID(0) +-- 54:55 attributes +-- 56:63 TID(6:13) +lsu_addr_d(64-real_addr_width to 64-real_addr_width+4) <= + htw_lsu_addr(64-real_addr_width to 64-real_addr_width+4) when inv_seq_htw_load='1' + else ex6_pid_q(pid_width-13 to pid_width-9) when inv_seq_tlbi_load='1' + else lsu_addr_q(64-real_addr_width to 64-real_addr_width+4); +lsu_addr_d(64-real_addr_width+5 to 33) <= + htw_lsu_addr(64-real_addr_width+5 to 33) when inv_seq_htw_load='1' + else ex3_ea_q(64-real_addr_width+5 to 33) when inv_seq_tlbi_load='1' + else lsu_addr_q(64-real_addr_width+5 to 33); +lsu_addr_d(34 to 35) <= + htw_lsu_addr(34 to 35) when inv_seq_htw_load='1' + else ex3_ea_q(13 to 14) when (inv_seq_tlbi_load='1' and mmucr1(pos_tlbi_msb)='1' and ex6_size_q=TLB_PgSize_1GB) + else ex3_ea_q(17 to 18) when (inv_seq_tlbi_load='1' and mmucr1(pos_tlbi_msb)='0' and ex6_size_q=TLB_PgSize_1GB) + else ex3_ea_q(34 to 35) when inv_seq_tlbi_load='1' + else lsu_addr_q(34 to 35); +lsu_addr_d(36 to 39) <= + htw_lsu_addr(36 to 39) when inv_seq_htw_load='1' + else ex3_ea_q(15 to 18) when (inv_seq_tlbi_load='1' and mmucr1(pos_tlbi_msb)='1' and + (ex6_size_q=TLB_PgSize_1GB or ex6_size_q=TLB_PgSize_256MB)) + else ex3_ea_q(19 to 22) when (inv_seq_tlbi_load='1' and mmucr1(pos_tlbi_msb)='0' and + (ex6_size_q=TLB_PgSize_1GB or ex6_size_q=TLB_PgSize_256MB)) + else ex3_ea_q(36 to 39) when inv_seq_tlbi_load='1' + else lsu_addr_q(36 to 39); +lsu_addr_d(40 to 41) <= + htw_lsu_addr(40 to 41) when inv_seq_htw_load='1' + else ex3_ea_q(19 to 20) when (inv_seq_tlbi_load='1' and mmucr1(pos_tlbi_msb)='1' and + (ex6_size_q=TLB_PgSize_1GB or ex6_size_q=TLB_PgSize_256MB or ex6_size_q=TLB_PgSize_16MB)) + else ex3_ea_q(23 to 24) when (inv_seq_tlbi_load='1' and mmucr1(pos_tlbi_msb)='0' and + (ex6_size_q=TLB_PgSize_1GB or ex6_size_q=TLB_PgSize_256MB or ex6_size_q=TLB_PgSize_16MB)) + else ex3_ea_q(40 to 41) when inv_seq_tlbi_load='1' + else lsu_addr_q(40 to 41); +lsu_addr_d(42 to 43) <= + htw_lsu_addr(42 to 43) when inv_seq_htw_load='1' + else ex6_isel_q(1 to 2) when (ex6_isel_q(0)='1' and inv_seq_tlbi_load='1') + else ex3_ea_q(21 to 22) when (ex6_isel_q(0)='0' and inv_seq_tlbi_load='1' and mmucr1(pos_tlbi_msb)='1' and + (ex6_size_q=TLB_PgSize_1GB or ex6_size_q=TLB_PgSize_256MB or ex6_size_q=TLB_PgSize_16MB)) + else ex3_ea_q(25 to 26) when (ex6_isel_q(0)='0' and inv_seq_tlbi_load='1' and mmucr1(pos_tlbi_msb)='0' and + (ex6_size_q=TLB_PgSize_1GB or ex6_size_q=TLB_PgSize_256MB or ex6_size_q=TLB_PgSize_16MB)) + else ex3_ea_q(42 to 43) when (ex6_isel_q(0)='0' and inv_seq_tlbi_load='1') + else lsu_addr_q(42 to 43); +lsu_addr_d(44 to 47) <= + htw_lsu_addr(44 to 47) when inv_seq_htw_load='1' + else ex3_ea_q(23 to 26) when (inv_seq_tlbi_load='1' and mmucr1(pos_tlbi_msb)='1' and + (ex6_size_q=TLB_PgSize_1GB or ex6_size_q=TLB_PgSize_256MB or ex6_size_q=TLB_PgSize_16MB or ex6_size_q=TLB_PgSize_1MB)) + else ex3_ea_q(27 to 30) when (inv_seq_tlbi_load='1' and mmucr1(pos_tlbi_msb)='0' and + (ex6_size_q=TLB_PgSize_1GB or ex6_size_q=TLB_PgSize_256MB or ex6_size_q=TLB_PgSize_16MB or ex6_size_q=TLB_PgSize_1MB)) + else ex3_ea_q(44 to 47) when inv_seq_tlbi_load='1' + else lsu_addr_q(44 to 47); +lsu_addr_d(48 to 51) <= htw_lsu_addr(48 to 51) when inv_seq_htw_load='1' + else ex6_size_q(0 to 3) when inv_seq_tlbi_load='1' and ex6_size_large='1' + else ex3_ea_q(48 to 51) when inv_seq_tlbi_load='1' and ex6_size_large='0' + else lsu_addr_q(48 to 51); +lsu_addr_d(52) <= htw_lsu_addr(52) when inv_seq_htw_load='1' + else ex6_ts_q when inv_seq_tlbi_load='1' + else lsu_addr_q(52); +lsu_addr_d(53) <= htw_lsu_addr(53) when inv_seq_htw_load='1' + else ex6_pid_q(0) when inv_seq_tlbi_load='1' + else lsu_addr_q(53); +lsu_addr_d(54 to 55) <= htw_lsu_addr(54 to 55) when inv_seq_htw_load='1' + else ex6_isel_q(1 to 2) when (ex6_isel_q(0)='0' and inv_seq_tlbi_load='1') + else "10" when (ex6_isel_q(0)='1' and inv_seq_tlbi_load='1') + else lsu_addr_q(54 to 55); +lsu_addr_d(56 to 63) <= htw_lsu_addr(56 to 63) when inv_seq_htw_load='1' + else ex6_pid_q(pid_width-8 to pid_width-1) when inv_seq_tlbi_load='1' + else lsu_addr_q(56 to 63); +lsu_lpid_d <= ex6_lpid_q when inv_seq_tlbi_load='1' + else lsu_lpid_q; +lsu_ind_d <= ex6_ind_q when inv_seq_tlbi_load='1' + else lsu_ind_q; +lsu_gs_d <= ex6_gs_q when inv_seq_tlbi_load='1' + else lsu_gs_q; +lsu_lbit_d <= '1' when (inv_seq_tlbi_load='1' and ex6_size_large='1') + else '0' when (inv_seq_tlbi_load='1' and ex6_size_large='0') + else lsu_lbit_q; +mm_xu_lsu_req <= lsu_req_q; +mm_xu_lsu_ttype <= lsu_ttype_q; +mm_xu_lsu_wimge <= lsu_wimge_q; +mm_xu_lsu_u <= lsu_ubits_q; +mm_xu_lsu_addr <= lsu_addr_q; +mm_xu_lsu_lpid <= lsu_lpid_q; +mm_xu_lsu_ind <= lsu_ind_q; +mm_xu_lsu_gs <= lsu_gs_q; +mm_xu_lsu_lbit <= lsu_lbit_q; +----------------------------------------------------------------------- +-- Snoop interfaces to erats and tlb +----------------------------------------------------------------------- +snoop_valid_d(0) <= inv_seq_ierat_snoop_val; +snoop_valid_d(1) <= inv_seq_derat_snoop_val; +snoop_valid_d(2) <= inv_seq_tlb_snoop_val; +snoop_coming_d(0) <= + inv_seq_tlb0fi_inprogress or + inv_seq_tlbwe_inprogress or + inv_seq_local_inprogress or inv_seq_snoop_inprogress; +snoop_coming_d(1) <= snoop_coming_d(0); +snoop_coming_d(2) <= snoop_coming_d(0); +snoop_coming_d(3) <= snoop_coming_d(0) or mmucr2_act_override; +snoop_coming_d(4) <= snoop_coming_d(0) or mmucr2_act_override; +gen64_snoop_attr: if real_addr_width > 32 generate +ex6_tid_nz <= or_reduce(ex6_pid_q(0 to pid_width-1)); +back_inv_tid_nz <= or_reduce(an_ac_back_inv_addr_q(53) & an_ac_back_inv_addr_q(22 to 26) & an_ac_back_inv_addr_q(56 to 63)); +tlbwe_back_inv_tid_nz <= or_reduce(tlbwe_back_inv_attr_q(20 to 25) & tlbwe_back_inv_attr_q(6 to 13)); +snoop_attr_d(0) <= not inv_seq_snoop_inprogress_q(0); +snoop_attr_d(1 to 3) <= '1' & an_ac_back_inv_addr_q(42 to 43) + when inv_seq_snoop_inprogress_q(0)='1' and an_ac_back_inv_addr_q(54 to 55)="10" + else '0' & an_ac_back_inv_addr_q(54 to 55) + when inv_seq_snoop_inprogress_q(0)='1' and an_ac_back_inv_addr_q(54 to 55)/="10" + else "011" when inv_seq_tlbwe_inprogress_q(0)='1' + else (ex6_isel_q(0 to 2) and not(0 to 2 => inv_seq_tlb0fi_inprogress_q(0))); +snoop_attr_d(4 to 13) <= an_ac_back_inv_q(5) & an_ac_back_inv_addr_q(52) & an_ac_back_inv_addr_q(56 to 63) + when inv_seq_snoop_inprogress_q(0)='1' + else tlbwe_back_inv_attr_q(4 to 13) when inv_seq_tlbwe_inprogress_q(0)='1' + else ex6_gs_q & ex6_ts_q & ex6_pid_q(pid_width-8 to pid_width-1); +snoop_attr_d(14 to 17) <= "0001" when inv_seq_snoop_inprogress_q(0)='1' and an_ac_back_inv_q(4)='0' + else an_ac_back_inv_addr_q(48 to 51) when inv_seq_snoop_inprogress_q(0)='1' and an_ac_back_inv_q(4)='1' + else tlbwe_back_inv_attr_q(14 to 17) when inv_seq_tlbwe_inprogress_q(0)='1' + else ex6_size_q(0 to 3); +snoop_attr_d(18) <= not inv_seq_tlbwe_inprogress_q(0) or not tlbwe_back_inv_attr_q(18); +snoop_attr_d(19) <= back_inv_tid_nz when inv_seq_snoop_inprogress_q(0)='1' + else tlbwe_back_inv_tid_nz when inv_seq_tlbwe_inprogress_q(0)='1' + else ex6_tid_nz; +snoop_attr_tlb_spec_d(18) <= '0'; +snoop_attr_tlb_spec_d(19) <= inv_seq_tlb0fi_inprogress_q(0); +snoop_attr_d(20 to 25) <= an_ac_back_inv_addr_q(53) & an_ac_back_inv_addr_q(22 to 26) when inv_seq_snoop_inprogress_q(0)='1' + else tlbwe_back_inv_attr_q(20 to 25) when inv_seq_tlbwe_inprogress_q(0)='1' + else ex6_pid_q(pid_width-14 to pid_width-9); +snoop_attr_d(26 to 33) <= an_ac_back_inv_lpar_id_q when inv_seq_snoop_inprogress_q(0)='1' + else tlbwe_back_inv_attr_q(26 to 33) when inv_seq_tlbwe_inprogress_q(0)='1' + else lpidr_q when inv_seq_tlb0fi_inprogress_q(0)='1' + else ex6_lpid_q; +snoop_attr_d(34) <= an_ac_back_inv_q(6) when inv_seq_snoop_inprogress_q(0)='1' + else tlbwe_back_inv_attr_q(34) when inv_seq_tlbwe_inprogress_q(0)='1' + else ex6_ind_q; +snoop_attr_clone_d(0) <= not inv_seq_snoop_inprogress_q(1); +snoop_attr_clone_d(1 to 3) <= '1' & an_ac_back_inv_addr_q(42 to 43) + when inv_seq_snoop_inprogress_q(1)='1' and an_ac_back_inv_addr_q(54 to 55)="10" + else '0' & an_ac_back_inv_addr_q(54 to 55) + when inv_seq_snoop_inprogress_q(1)='1' and an_ac_back_inv_addr_q(54 to 55)/="10" + else "011" when inv_seq_tlbwe_inprogress_q(1)='1' + else (ex6_isel_q(0 to 2) and not(0 to 2 => inv_seq_tlb0fi_inprogress_q(1))); +snoop_attr_clone_d(4 to 13) <= an_ac_back_inv_q(5) & an_ac_back_inv_addr_q(52) & an_ac_back_inv_addr_q(56 to 63) + when inv_seq_snoop_inprogress_q(1)='1' + else tlbwe_back_inv_attr_q(4 to 13) when inv_seq_tlbwe_inprogress_q(1)='1' + else ex6_gs_q & ex6_ts_q & ex6_pid_q(pid_width-8 to pid_width-1); +snoop_attr_clone_d(14 to 17) <= "0001" when inv_seq_snoop_inprogress_q(1)='1' and an_ac_back_inv_q(4)='0' + else an_ac_back_inv_addr_q(48 to 51) when inv_seq_snoop_inprogress_q(1)='1' and an_ac_back_inv_q(4)='1' + else tlbwe_back_inv_attr_q(14 to 17) when inv_seq_tlbwe_inprogress_q(1)='1' + else ex6_size_q(0 to 3); +snoop_attr_clone_d(18) <= not inv_seq_tlbwe_inprogress_q(1) or not tlbwe_back_inv_attr_q(18); +snoop_attr_clone_d(19) <= back_inv_tid_nz when inv_seq_snoop_inprogress_q(1)='1' + else tlbwe_back_inv_tid_nz when inv_seq_tlbwe_inprogress_q(1)='1' + else ex6_tid_nz; +snoop_attr_clone_d(20 to 25) <= an_ac_back_inv_addr_q(53) & an_ac_back_inv_addr_q(22 to 26) when inv_seq_snoop_inprogress_q(1)='1' + else tlbwe_back_inv_attr_q(20 to 25) when inv_seq_tlbwe_inprogress_q(1)='1' + else ex6_pid_q(pid_width-14 to pid_width-9); +end generate gen64_snoop_attr; +gen32_snoop_attr: if real_addr_width < 33 generate +ex6_tid_nz <= or_reduce(ex6_pid_q(0 to pid_width-1)); +back_inv_tid_nz <= or_reduce(an_ac_back_inv_addr_q(56 to 63)); +tlbwe_back_inv_tid_nz <= or_reduce(tlbwe_back_inv_attr_q(20 to 25) & tlbwe_back_inv_attr_q(6 to 13)); +snoop_attr_d(0) <= not inv_seq_snoop_inprogress_q(0); +snoop_attr_d(1 to 3) <= '1' & an_ac_back_inv_addr_q(42 to 43) + when inv_seq_snoop_inprogress_q(0)='1' and an_ac_back_inv_addr_q(54 to 55)="10" + else '0' & an_ac_back_inv_addr_q(54 to 55) + when inv_seq_snoop_inprogress_q(0)='1' and an_ac_back_inv_addr_q(54 to 55)/="10" + else "011" when inv_seq_tlbwe_inprogress_q(0)='1' + else ex6_isel_q(0 to 2); +snoop_attr_d(4 to 13) <= an_ac_back_inv_q(5) & an_ac_back_inv_addr_q(52) & an_ac_back_inv_addr_q(56 to 63) + when inv_seq_snoop_inprogress_q(0)='1' + else tlbwe_back_inv_attr_q(4 to 13) when inv_seq_tlbwe_inprogress_q(0)='1' + else ex6_gs_q & ex6_ts_q & ex6_pid_q(pid_width-8 to pid_width-1); +snoop_attr_d(14 to 17) <= "0001" when inv_seq_snoop_inprogress_q(0)='1' and an_ac_back_inv_q(4)='0' + else an_ac_back_inv_addr_q(48 to 51) when inv_seq_snoop_inprogress_q(0)='1' and an_ac_back_inv_q(4)='1' + else tlbwe_back_inv_attr_q(14 to 17) when inv_seq_tlbwe_inprogress_q(0)='1' + else ex6_size_q(0 to 3); +snoop_attr_d(18) <= not inv_seq_tlbwe_inprogress_q(0) or not tlbwe_back_inv_attr_q(18); +snoop_attr_d(19) <= back_inv_tid_nz when inv_seq_snoop_inprogress_q(0)='1' + else tlbwe_back_inv_tid_nz when inv_seq_tlbwe_inprogress_q(0)='1' + else ex6_tid_nz; +snoop_attr_tlb_spec_d(18) <= '0'; +snoop_attr_tlb_spec_d(19) <= inv_seq_tlb0fi_inprogress_q(0); +snoop_attr_d(20 to 25) <= (others => '0') when inv_seq_snoop_inprogress_q(0)='1' + else tlbwe_back_inv_attr_q(20 to 25) when inv_seq_tlbwe_inprogress_q(0)='1' + else ex6_pid_q(pid_width-14 to pid_width-9); +snoop_attr_d(26 to 33) <= an_ac_back_inv_lpar_id_q when inv_seq_snoop_inprogress_q(0)='1' + else tlbwe_back_inv_attr_q(26 to 33) when inv_seq_tlbwe_inprogress_q(0)='1' + else lpidr_q when inv_seq_tlb0fi_inprogress_q(0)='1' + else ex6_lpid_q; +snoop_attr_d(34) <= an_ac_back_inv_q(6) when inv_seq_snoop_inprogress_q(0)='1' + else tlbwe_back_inv_attr_q(34) when inv_seq_tlbwe_inprogress_q(0)='1' + else ex6_ind_q; +snoop_attr_clone_d(0) <= not inv_seq_snoop_inprogress_q(1); +snoop_attr_clone_d(1 to 3) <= '1' & an_ac_back_inv_addr_q(42 to 43) + when inv_seq_snoop_inprogress_q(1)='1' and an_ac_back_inv_addr_q(54 to 55)="10" + else '0' & an_ac_back_inv_addr_q(54 to 55) + when inv_seq_snoop_inprogress_q(1)='1' and an_ac_back_inv_addr_q(54 to 55)/="10" + else "011" when inv_seq_tlbwe_inprogress_q(1)='1' + else ex6_isel_q(0 to 2); +snoop_attr_clone_d(4 to 13) <= an_ac_back_inv_q(5) & an_ac_back_inv_addr_q(52) & an_ac_back_inv_addr_q(56 to 63) + when inv_seq_snoop_inprogress_q(1)='1' + else tlbwe_back_inv_attr_q(4 to 13) when inv_seq_tlbwe_inprogress_q(1)='1' + else ex6_gs_q & ex6_ts_q & ex6_pid_q(pid_width-8 to pid_width-1); +snoop_attr_clone_d(14 to 17) <= "0001" when inv_seq_snoop_inprogress_q(1)='1' and an_ac_back_inv_q(4)='0' + else an_ac_back_inv_addr_q(48 to 51) when inv_seq_snoop_inprogress_q(1)='1' and an_ac_back_inv_q(4)='1' + else tlbwe_back_inv_attr_q(14 to 17) when inv_seq_tlbwe_inprogress_q(1)='1' + else ex6_size_q(0 to 3); +snoop_attr_clone_d(18) <= not inv_seq_tlbwe_inprogress_q(1) or not tlbwe_back_inv_attr_q(18); +snoop_attr_clone_d(19) <= back_inv_tid_nz when inv_seq_snoop_inprogress_q(1)='1' + else tlbwe_back_inv_tid_nz when inv_seq_tlbwe_inprogress_q(1)='1' + else ex6_tid_nz; +snoop_attr_clone_d(20 to 25) <= (others => '0') when inv_seq_snoop_inprogress_q(1)='1' + else tlbwe_back_inv_attr_q(20 to 25) when inv_seq_tlbwe_inprogress_q(1)='1' + else ex6_pid_q(pid_width-14 to pid_width-9); +end generate gen32_snoop_attr; +-- A2 to L2 interface req_ra epn bits for tlbivax op +-- page size mmucr1.tlbi_msb 27:30 31:33 34:35 36:39 40:43 44:47 48:51 TLB w value +-- 4K 0 EA(27:30) EA(31:33) EA(34:35) EA(36:39) EA(40:43) EA(44:47) EA(48:51) 31 +-- 64K 0 EA(27:30) EA(31:33) EA(34:35) EA(36:39) EA(40:43) EA(44:47) 0b0011 31 +-- 1M 0 EA(27:30) EA(31:33) EA(34:35) EA(36:39) EA(40:43) EA(27:30) 0b0101 27 +-- 16M 0 EA(27:30) EA(31:33) EA(34:35) EA(36:39) EA(23:26) EA(27:30) 0b0111 23 +-- 256M 0 EA(27:30) EA(31:33) EA(34:35) EA(19:22) EA(23:26) EA(27:30) 0b1001 19 +-- 1G 0 EA(27:30) EA(31:33) EA(17:18) EA(19:22) EA(23:26) EA(27:30) 0b1010 17 +-- 4K 1 EA(27:30) EA(31:33) EA(34:35) EA(36:39) EA(40:43) EA(44:47) EA(48:51) 27 +-- 64K 1 EA(27:30) EA(31:33) EA(34:35) EA(36:39) EA(40:43) EA(44:47) 0b0011 27 +-- 1M 1 EA(27:30) EA(31:33) EA(34:35) EA(36:39) EA(40:43) EA(23:26) 0b0101 23 +-- 16M 1 EA(27:30) EA(31:33) EA(34:35) EA(36:39) EA(19:22) EA(23:26) 0b0111 19 +-- 256M 1 EA(27:30) EA(31:33) EA(34:35) EA(15:18) EA(19:22) EA(23:26) 0b1001 15 +-- 1G 1 EA(27:30) EA(31:33) EA(13:14) EA(15:18) EA(19:22) EA(23:26) 0b1010 13 +-- A2 to L2 interface req_ra for tlbivax op: +-- 22:26 TID(1:5) +-- 27:51 EPN +-- 52 TS +-- 53 TID(0) +-- 54:55 attributes +-- 56:63 TID(6:13) +gen_rs_gte_epn_snoop_vpn: if (rs_data_width > epn_width-1) and (epn_width > real_addr_width) generate +snoop_vpn_d(52-epn_width to 12) <= (others => '0') when inv_seq_snoop_inprogress_q(0)='1' + else tlbwe_back_inv_addr_q(0 to 12) when inv_seq_tlbwe_inprogress_q(0)='1' + else ex3_ea_q(52-epn_width to 12); +snoop_vpn_d(13 to 14) <= an_ac_back_inv_addr_q(34 to 35) when (inv_seq_snoop_inprogress_q(0)='1' and an_ac_back_inv_q(4)='1' and + mmucr1_q(pos_tlbi_msb)='1' and an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_1GB) + else (others => '0') when inv_seq_snoop_inprogress_q(0)='1' + else tlbwe_back_inv_addr_q(13 to 14) when inv_seq_tlbwe_inprogress_q(0)='1' + else ex3_ea_q(13 to 14); +snoop_vpn_d(15 to 16) <= an_ac_back_inv_addr_q(36 to 37) when (inv_seq_snoop_inprogress_q(0)='1' and an_ac_back_inv_q(4)='1' and + mmucr1_q(pos_tlbi_msb)='1' and (an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_1GB or + an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_256MB)) + else (others => '0') when inv_seq_snoop_inprogress_q(0)='1' + else tlbwe_back_inv_addr_q(15 to 16) when inv_seq_tlbwe_inprogress_q(0)='1' + else ex3_ea_q(15 to 16); +snoop_vpn_d(17 to 18) <= an_ac_back_inv_addr_q(38 to 39) when (inv_seq_snoop_inprogress_q(0)='1' and an_ac_back_inv_q(4)='1' and + mmucr1_q(pos_tlbi_msb)='1' and (an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_1GB or + an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_256MB)) + else an_ac_back_inv_addr_q(34 to 35) when (inv_seq_snoop_inprogress_q(0)='1'and an_ac_back_inv_q(4)='1' and + mmucr1_q(pos_tlbi_msb)='0' and an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_1GB ) + else (others => '0') when inv_seq_snoop_inprogress_q(0)='1' + else tlbwe_back_inv_addr_q(17 to 18) when inv_seq_tlbwe_inprogress_q(0)='1' + else ex3_ea_q(17 to 18); +snoop_vpn_d(19 to 22) <= an_ac_back_inv_addr_q(40 to 43) when (inv_seq_snoop_inprogress_q(0)='1' and an_ac_back_inv_q(4)='1' and + mmucr1_q(pos_tlbi_msb)='1' and (an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_1GB or + an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_256MB or an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_16MB)) + else an_ac_back_inv_addr_q(36 to 39) when (inv_seq_snoop_inprogress_q(0)='1'and an_ac_back_inv_q(4)='1' and + mmucr1_q(pos_tlbi_msb)='0' and (an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_1GB or + an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_256MB)) + else (others => '0') when inv_seq_snoop_inprogress_q(0)='1' + else tlbwe_back_inv_addr_q(19 to 22) when inv_seq_tlbwe_inprogress_q(0)='1' + else ex3_ea_q(19 to 22); +snoop_vpn_d(23 to 26) <= an_ac_back_inv_addr_q(44 to 47) when (inv_seq_snoop_inprogress_q(0)='1' and an_ac_back_inv_q(4)='1' and + mmucr1_q(pos_tlbi_msb)='1' and (an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_1GB or + an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_256MB or an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_16MB or + an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_1MB)) + else an_ac_back_inv_addr_q(40 to 43) when (inv_seq_snoop_inprogress_q(0)='1' and an_ac_back_inv_q(4)='1' and + mmucr1_q(pos_tlbi_msb)='0' and (an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_1GB or + an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_256MB or an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_16MB)) + else (others => '0') when inv_seq_snoop_inprogress_q(0)='1' + else tlbwe_back_inv_addr_q(23 to 26) when inv_seq_tlbwe_inprogress_q(0)='1' + else ex3_ea_q(23 to 26); +snoop_vpn_d(27 to 30) <= an_ac_back_inv_addr_q(44 to 47) when (inv_seq_snoop_inprogress_q(0)='1' and an_ac_back_inv_q(4)='1' and + mmucr1_q(pos_tlbi_msb)='0' and (an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_1GB or + an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_256MB or an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_16MB or + an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_1MB)) + else an_ac_back_inv_addr_q(27 to 30) when inv_seq_snoop_inprogress_q(0)='1' + else tlbwe_back_inv_addr_q(27 to 30) when inv_seq_tlbwe_inprogress_q(0)='1' + else ex3_ea_q(27 to 30); +snoop_vpn_d(31) <= an_ac_back_inv_addr_q(31) when inv_seq_snoop_inprogress_q(0)='1' + else tlbwe_back_inv_addr_q(31) when inv_seq_tlbwe_inprogress_q(0)='1' + else ex3_ea_q(31); +snoop_vpn_clone_d(52-epn_width to 12) <= (others => '0') when inv_seq_snoop_inprogress_q(1)='1' + else tlbwe_back_inv_addr_q(0 to 12) when inv_seq_tlbwe_inprogress_q(1)='1' + else ex3_ea_q(52-epn_width to 12); +snoop_vpn_clone_d(13 to 14) <= an_ac_back_inv_addr_q(34 to 35) when (inv_seq_snoop_inprogress_q(1)='1' and an_ac_back_inv_q(4)='1' and + mmucr1_q(pos_tlbi_msb)='1' and an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_1GB) + else (others => '0') when inv_seq_snoop_inprogress_q(1)='1' + else tlbwe_back_inv_addr_q(13 to 14) when inv_seq_tlbwe_inprogress_q(1)='1' + else ex3_ea_q(13 to 14); +snoop_vpn_clone_d(15 to 16) <= an_ac_back_inv_addr_q(36 to 37) when (inv_seq_snoop_inprogress_q(1)='1' and an_ac_back_inv_q(4)='1' and + mmucr1_q(pos_tlbi_msb)='1' and (an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_1GB or + an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_256MB)) + else (others => '0') when inv_seq_snoop_inprogress_q(1)='1' + else tlbwe_back_inv_addr_q(15 to 16) when inv_seq_tlbwe_inprogress_q(1)='1' + else ex3_ea_q(15 to 16); +snoop_vpn_clone_d(17 to 18) <= an_ac_back_inv_addr_q(38 to 39) when (inv_seq_snoop_inprogress_q(1)='1' and an_ac_back_inv_q(4)='1' and + mmucr1_q(pos_tlbi_msb)='1' and (an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_1GB or + an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_256MB)) + else an_ac_back_inv_addr_q(34 to 35) when (inv_seq_snoop_inprogress_q(1)='1'and an_ac_back_inv_q(4)='1' and + mmucr1_q(pos_tlbi_msb)='0' and an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_1GB ) + else (others => '0') when inv_seq_snoop_inprogress_q(1)='1' + else tlbwe_back_inv_addr_q(17 to 18) when inv_seq_tlbwe_inprogress_q(1)='1' + else ex3_ea_q(17 to 18); +snoop_vpn_clone_d(19 to 22) <= an_ac_back_inv_addr_q(40 to 43) when (inv_seq_snoop_inprogress_q(1)='1' and an_ac_back_inv_q(4)='1' and + mmucr1_q(pos_tlbi_msb)='1' and (an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_1GB or + an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_256MB or an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_16MB)) + else an_ac_back_inv_addr_q(36 to 39) when (inv_seq_snoop_inprogress_q(1)='1'and an_ac_back_inv_q(4)='1' and + mmucr1_q(pos_tlbi_msb)='0' and (an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_1GB or + an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_256MB)) + else (others => '0') when inv_seq_snoop_inprogress_q(1)='1' + else tlbwe_back_inv_addr_q(19 to 22) when inv_seq_tlbwe_inprogress_q(1)='1' + else ex3_ea_q(19 to 22); +snoop_vpn_clone_d(23 to 26) <= an_ac_back_inv_addr_q(44 to 47) when (inv_seq_snoop_inprogress_q(1)='1' and an_ac_back_inv_q(4)='1' and + mmucr1_q(pos_tlbi_msb)='1' and (an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_1GB or + an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_256MB or an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_16MB or + an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_1MB)) + else an_ac_back_inv_addr_q(40 to 43) when (inv_seq_snoop_inprogress_q(1)='1' and an_ac_back_inv_q(4)='1' and + mmucr1_q(pos_tlbi_msb)='0' and (an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_1GB or + an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_256MB or an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_16MB)) + else (others => '0') when inv_seq_snoop_inprogress_q(1)='1' + else tlbwe_back_inv_addr_q(23 to 26) when inv_seq_tlbwe_inprogress_q(1)='1' + else ex3_ea_q(23 to 26); +snoop_vpn_clone_d(27 to 30) <= an_ac_back_inv_addr_q(44 to 47) when (inv_seq_snoop_inprogress_q(1)='1' and an_ac_back_inv_q(4)='1' and + mmucr1_q(pos_tlbi_msb)='0' and (an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_1GB or + an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_256MB or an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_16MB or + an_ac_back_inv_addr_q(48 to 51)=TLB_PgSize_1MB)) + else an_ac_back_inv_addr_q(27 to 30) when inv_seq_snoop_inprogress_q(1)='1' + else tlbwe_back_inv_addr_q(27 to 30) when inv_seq_tlbwe_inprogress_q(1)='1' + else ex3_ea_q(27 to 30); +snoop_vpn_clone_d(31) <= an_ac_back_inv_addr_q(31) when inv_seq_snoop_inprogress_q(1)='1' + else tlbwe_back_inv_addr_q(31) when inv_seq_tlbwe_inprogress_q(1)='1' + else ex3_ea_q(31); +end generate gen_rs_gte_epn_snoop_vpn; +gen_rs_gte_ra_snoop_vpn: if (rs_data_width > real_addr_width-1) generate +snoop_vpn_d(32 to 51) <= an_ac_back_inv_addr_q(32 to 51) when inv_seq_snoop_inprogress_q(0)='1' + else tlbwe_back_inv_addr_q(32 to 51) when inv_seq_tlbwe_inprogress_q(0)='1' + else ex3_ea_q(32 to 51); +snoop_vpn_clone_d(32 to 51) <= an_ac_back_inv_addr_q(32 to 51) when inv_seq_snoop_inprogress_q(1)='1' + else tlbwe_back_inv_addr_q(32 to 51) when inv_seq_tlbwe_inprogress_q(1)='1' + else ex3_ea_q(32 to 51); +end generate gen_rs_gte_ra_snoop_vpn; +gen_ra_gt_rs_snoop_vpn: if rs_data_width < real_addr_width generate +snoop_vpn_d(64-real_addr_width to 51) <= an_ac_back_inv_addr_q(64-real_addr_width to 51) when inv_seq_snoop_inprogress_q(0)='1' + else tlbwe_back_inv_addr_q(64-real_addr_width to 51) when inv_seq_tlbwe_inprogress_q(0)='1' + else (64-real_addr_width to 63-rs_data_width => '0') & ex3_ea_q(64-rs_data_width to 51); +snoop_vpn_clone_d(64-real_addr_width to 51) <= an_ac_back_inv_addr_q(64-real_addr_width to 51) when inv_seq_snoop_inprogress_q(1)='1' + else tlbwe_back_inv_addr_q(64-real_addr_width to 51) when inv_seq_tlbwe_inprogress_q(1)='1' + else (64-real_addr_width to 63-rs_data_width => '0') & ex3_ea_q(64-rs_data_width to 51); +end generate gen_ra_gt_rs_snoop_vpn; +gen_epn_gt_rs_snoop_vpn: if (epn_width > real_addr_width) and (rs_data_width < epn_width) generate +snoop_vpn_d(52-epn_width to 63-real_addr_width) <= (others => '0'); +snoop_vpn_clone_d(52-epn_width to 63-real_addr_width) <= (others => '0'); +end generate gen_epn_gt_rs_snoop_vpn; +snoop_ack_d(0) <= iu_mm_ierat_snoop_ack when snoop_ack_q(0)='0' + else '0' when (inv_seq_snoop_done='1' or inv_seq_local_done='1' or inv_seq_tlb0fi_done='1' or inv_seq_tlbwe_snoop_done='1') + else snoop_ack_q(0); +snoop_ack_d(1) <= xu_mm_derat_snoop_ack when snoop_ack_q(1)='0' + else '0' when (inv_seq_snoop_done='1' or inv_seq_local_done='1' or inv_seq_tlb0fi_done='1' or inv_seq_tlbwe_snoop_done='1') + else snoop_ack_q(1); +snoop_ack_d(2) <= tlb_snoop_ack when snoop_ack_q(2)='0' + else '0' when (inv_seq_snoop_done='1' or inv_seq_local_done='1' or inv_seq_tlb0fi_done='1' or inv_seq_tlbwe_snoop_done='1') + else snoop_ack_q(2); +mm_iu_ierat_snoop_coming <= snoop_coming_q(0); +mm_iu_ierat_snoop_val <= snoop_valid_q(0); +mm_iu_ierat_snoop_attr <= snoop_attr_q(0 to 25); +mm_iu_ierat_snoop_vpn <= snoop_vpn_q; +mm_xu_derat_snoop_coming <= snoop_coming_q(1); +mm_xu_derat_snoop_val <= snoop_valid_q(1); +mm_xu_derat_snoop_attr <= snoop_attr_clone_q(0 to 25); +mm_xu_derat_snoop_vpn <= snoop_vpn_clone_q; +tlb_snoop_coming <= snoop_coming_q(2); +tlb_snoop_val <= snoop_valid_q(2); +tlb_snoop_attr(0 to 17) <= snoop_attr_q(0 to 17); +tlb_snoop_attr(18 to 19) <= snoop_attr_tlb_spec_q(18 to 19); +tlb_snoop_attr(20 to 34) <= snoop_attr_q(20 to 34); +tlb_snoop_vpn <= snoop_vpn_q; +xu_mm_ccr2_notlb_b <= not xu_mm_ccr2_notlb_q(1 to 12); +xu_mm_epcr_dgtmi <= xu_mm_epcr_dgtmi_q; +inval_perf_tlbilx <= inv_seq_local_done and not inv_seq_tlbi_load; +inval_perf_tlbivax <= inv_seq_local_done and inv_seq_tlbi_load; +inval_perf_tlbivax_snoop <= inv_seq_snoop_done; +inval_perf_tlb_flush <= or_reduce(ex3_flush_req_q); +inval_dbg_seq_q <= inv_seq_q(1 to 5); +inval_dbg_seq_idle <= inv_seq_idle; +inval_dbg_seq_snoop_inprogress <= inv_seq_snoop_inprogress; +inval_dbg_seq_snoop_done <= inv_seq_snoop_done; +inval_dbg_seq_local_done <= inv_seq_local_done; +inval_dbg_seq_tlb0fi_done <= inv_seq_tlb0fi_done; +inval_dbg_seq_tlbwe_snoop_done <= inv_seq_tlbwe_snoop_done; +inval_dbg_ex6_valid <= or_reduce(ex6_valid_q); +inval_dbg_ex6_thdid(0) <= (ex6_valid_q(2) or ex6_valid_q(3)); +inval_dbg_ex6_thdid(1) <= (ex6_valid_q(1) or ex6_valid_q(3)); +inval_dbg_ex6_ttype(0) <= ex6_ttype_q(4) or ex6_ttype_q(5); +inval_dbg_ex6_ttype(1) <= ex6_ttype_q(2) or ex6_ttype_q(3); +inval_dbg_ex6_ttype(2) <= ex6_ttype_q(1) or ex6_ttype_q(3) or ex6_ttype_q(5); +inval_dbg_snoop_forme <= inval_snoop_forme; +inval_dbg_snoop_local_reject <= inval_snoop_local_reject; +inval_dbg_an_ac_back_inv_q <= an_ac_back_inv_q(2 to 8); +inval_dbg_an_ac_back_inv_lpar_id_q <= an_ac_back_inv_lpar_id_q; +inval_dbg_an_ac_back_inv_addr_q <= an_ac_back_inv_addr_q; +inval_dbg_snoop_valid_q <= snoop_valid_q; +inval_dbg_snoop_ack_q <= snoop_ack_q; +inval_dbg_snoop_attr_q <= snoop_attr_q; +inval_dbg_snoop_attr_tlb_spec_q <= snoop_attr_tlb_spec_q; +inval_dbg_snoop_vpn_q <= snoop_vpn_q(17 to 51); +inval_dbg_lsu_tokens_q <= lsu_tokens_q; +-- unused spare signal assignments +unused_dc(0) <= or_reduce(LCB_DELAY_LCLKR_DC(1 TO 4)); +unused_dc(1) <= or_reduce(LCB_MPW1_DC_B(1 TO 4)); +unused_dc(2) <= PC_FUNC_SL_FORCE; +unused_dc(3) <= PC_FUNC_SL_THOLD_0_B; +unused_dc(4) <= TC_SCAN_DIS_DC_B; +unused_dc(5) <= TC_SCAN_DIAG_DC; +unused_dc(6) <= TC_LBIST_EN_DC; +unused_dc(7) <= or_reduce(MMUCR0_0(4 TO 5)); +unused_dc(8) <= or_reduce(MMUCR0_1(4 TO 5)); +unused_dc(9) <= or_reduce(MMUCR0_2(4 TO 5)); +unused_dc(10) <= or_reduce(MMUCR0_3(4 TO 5)); +unused_dc(11) <= mmucr1_q(13) and or_reduce(mmucr1_q(15 to 17)); +unused_dc(12) <= EX5_RS_IS_Q(0); +-------------------------------------------------- +-- latches +-------------------------------------------------- +ex1_valid_latch: tri_rlmreg_p + generic map (width => ex1_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex1_valid_offset to ex1_valid_offset+ex1_valid_q'length-1), + scout => sov(ex1_valid_offset to ex1_valid_offset+ex1_valid_q'length-1), + din => ex1_valid_d(0 to thdid_width-1), + dout => ex1_valid_q(0 to thdid_width-1) ); +ex1_ttype_latch: tri_rlmreg_p + generic map (width => ex1_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex1_ttype_offset to ex1_ttype_offset+ex1_ttype_q'length-1), + scout => sov(ex1_ttype_offset to ex1_ttype_offset+ex1_ttype_q'length-1), + din => ex1_ttype_d, + dout => ex1_ttype_q ); +ex1_state_latch: tri_rlmreg_p + generic map (width => ex1_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex1_state_offset to ex1_state_offset+ex1_state_q'length-1), + scout => sov(ex1_state_offset to ex1_state_offset+ex1_state_q'length-1), + din => ex1_state_d(0 to state_width-1), + dout => ex1_state_q(0 to state_width-1) ); +ex1_t_latch: tri_rlmreg_p + generic map (width => ex1_t_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex1_t_offset to ex1_t_offset+ex1_t_q'length-1), + scout => sov(ex1_t_offset to ex1_t_offset+ex1_t_q'length-1), + din => ex1_t_d(0 to t_width-1), + dout => ex1_t_q(0 to t_width-1) ); +------------------------------------------------------------------------------- +ex2_valid_latch: tri_rlmreg_p + generic map (width => ex2_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex2_valid_offset to ex2_valid_offset+ex2_valid_q'length-1), + scout => sov(ex2_valid_offset to ex2_valid_offset+ex2_valid_q'length-1), + din => ex2_valid_d(0 to thdid_width-1), + dout => ex2_valid_q(0 to thdid_width-1) ); +ex2_ttype_latch: tri_rlmreg_p + generic map (width => ex2_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex2_ttype_offset to ex2_ttype_offset+ex2_ttype_q'length-1), + scout => sov(ex2_ttype_offset to ex2_ttype_offset+ex2_ttype_q'length-1), + din => ex2_ttype_d(0 to ttype_width-1), + dout => ex2_ttype_q(0 to ttype_width-1) ); +ex2_rs_is_latch: tri_rlmreg_p + generic map (width => ex2_rs_is_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex2_rs_is_offset to ex2_rs_is_offset+ex2_rs_is_q'length-1), + scout => sov(ex2_rs_is_offset to ex2_rs_is_offset+ex2_rs_is_q'length-1), + din => ex2_rs_is_d(0 to rs_is_width-1), + dout => ex2_rs_is_q(0 to rs_is_width-1) ); +ex2_state_latch: tri_rlmreg_p + generic map (width => ex2_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex2_state_offset to ex2_state_offset+ex2_state_q'length-1), + scout => sov(ex2_state_offset to ex2_state_offset+ex2_state_q'length-1), + din => ex2_state_d(0 to state_width-1), + dout => ex2_state_q(0 to state_width-1) ); +ex2_t_latch: tri_rlmreg_p + generic map (width => ex2_t_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex2_t_offset to ex2_t_offset+ex2_t_q'length-1), + scout => sov(ex2_t_offset to ex2_t_offset+ex2_t_q'length-1), + din => ex2_t_d(0 to t_width-1), + dout => ex2_t_q(0 to t_width-1) ); +------------------------------------------------------------------------------- +ex3_valid_latch: tri_rlmreg_p + generic map (width => ex3_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex3_valid_offset to ex3_valid_offset+ex3_valid_q'length-1), + scout => sov(ex3_valid_offset to ex3_valid_offset+ex3_valid_q'length-1), + din => ex3_valid_d(0 to thdid_width-1), + dout => ex3_valid_q(0 to thdid_width-1) ); +ex3_ttype_latch: tri_rlmreg_p + generic map (width => ex3_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex3_ttype_offset to ex3_ttype_offset+ex3_ttype_q'length-1), + scout => sov(ex3_ttype_offset to ex3_ttype_offset+ex3_ttype_q'length-1), + din => ex3_ttype_d(0 to ttype_width-1), + dout => ex3_ttype_q(0 to ttype_width-1) ); +ex3_rs_is_latch: tri_rlmreg_p + generic map (width => ex3_rs_is_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex3_rs_is_offset to ex3_rs_is_offset+ex3_rs_is_q'length-1), + scout => sov(ex3_rs_is_offset to ex3_rs_is_offset+ex3_rs_is_q'length-1), + din => ex3_rs_is_d(0 to rs_is_width-1), + dout => ex3_rs_is_q(0 to rs_is_width-1) ); +ex3_state_latch: tri_rlmreg_p + generic map (width => ex3_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex3_state_offset to ex3_state_offset+ex3_state_q'length-1), + scout => sov(ex3_state_offset to ex3_state_offset+ex3_state_q'length-1), + din => ex3_state_d(0 to state_width-1), + dout => ex3_state_q(0 to state_width-1) ); +ex3_t_latch: tri_rlmreg_p + generic map (width => ex3_t_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex3_t_offset to ex3_t_offset+ex3_t_q'length-1), + scout => sov(ex3_t_offset to ex3_t_offset+ex3_t_q'length-1), + din => ex3_t_d(0 to t_width-1), + dout => ex3_t_q(0 to t_width-1) ); +ex3_flush_req_latch: tri_rlmreg_p + generic map (width => ex3_flush_req_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex3_flush_req_offset to ex3_flush_req_offset+ex3_flush_req_q'length-1), + scout => sov(ex3_flush_req_offset to ex3_flush_req_offset+ex3_flush_req_q'length-1), + din => ex3_flush_req_d(0 to thdid_width-1), + dout => ex3_flush_req_q(0 to thdid_width-1) ); +ex3_ea_latch: tri_rlmreg_p + generic map (width => ex3_ea_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex3_ea_offset to ex3_ea_offset+ex3_ea_q'length-1), + scout => sov(ex3_ea_offset to ex3_ea_offset+ex3_ea_q'length-1), + din => ex3_ea_d(64-rs_data_width to 63), + dout => ex3_ea_q(64-rs_data_width to 63) ); +------------------------------------------------------------------------------- +ex4_valid_latch: tri_rlmreg_p + generic map (width => ex4_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex4_valid_offset to ex4_valid_offset+ex4_valid_q'length-1), + scout => sov(ex4_valid_offset to ex4_valid_offset+ex4_valid_q'length-1), + din => ex4_valid_d(0 to thdid_width-1), + dout => ex4_valid_q(0 to thdid_width-1) ); +ex4_ttype_latch: tri_rlmreg_p + generic map (width => ex4_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex4_ttype_offset to ex4_ttype_offset+ex4_ttype_q'length-1), + scout => sov(ex4_ttype_offset to ex4_ttype_offset+ex4_ttype_q'length-1), + din => ex4_ttype_d(0 to ttype_width-1), + dout => ex4_ttype_q(0 to ttype_width-1) ); +ex4_rs_is_latch: tri_rlmreg_p + generic map (width => ex4_rs_is_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex4_rs_is_offset to ex4_rs_is_offset+ex4_rs_is_q'length-1), + scout => sov(ex4_rs_is_offset to ex4_rs_is_offset+ex4_rs_is_q'length-1), + din => ex4_rs_is_d(0 to rs_is_width-1), + dout => ex4_rs_is_q(0 to rs_is_width-1) ); +ex4_state_latch: tri_rlmreg_p + generic map (width => ex4_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex4_state_offset to ex4_state_offset+ex4_state_q'length-1), + scout => sov(ex4_state_offset to ex4_state_offset+ex4_state_q'length-1), + din => ex4_state_d(0 to state_width-1), + dout => ex4_state_q(0 to state_width-1) ); +ex4_t_latch: tri_rlmreg_p + generic map (width => ex4_t_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex4_t_offset to ex4_t_offset+ex4_t_q'length-1), + scout => sov(ex4_t_offset to ex4_t_offset+ex4_t_q'length-1), + din => ex4_t_d(0 to t_width-1), + dout => ex4_t_q(0 to t_width-1) ); +-------------------------------------------------- +ex5_valid_latch: tri_rlmreg_p + generic map (width => ex5_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex5_valid_offset to ex5_valid_offset+ex5_valid_q'length-1), + scout => sov(ex5_valid_offset to ex5_valid_offset+ex5_valid_q'length-1), + din => ex5_valid_d(0 to thdid_width-1), + dout => ex5_valid_q(0 to thdid_width-1) ); +ex5_ttype_latch: tri_rlmreg_p + generic map (width => ex5_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex5_ttype_offset to ex5_ttype_offset+ex5_ttype_q'length-1), + scout => sov(ex5_ttype_offset to ex5_ttype_offset+ex5_ttype_q'length-1), + din => ex5_ttype_d(0 to ttype_width-1), + dout => ex5_ttype_q(0 to ttype_width-1) ); +ex5_rs_is_latch: tri_rlmreg_p + generic map (width => ex5_rs_is_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex5_rs_is_offset to ex5_rs_is_offset+ex5_rs_is_q'length-1), + scout => sov(ex5_rs_is_offset to ex5_rs_is_offset+ex5_rs_is_q'length-1), + din => ex5_rs_is_d(0 to rs_is_width-1), + dout => ex5_rs_is_q(0 to rs_is_width-1) ); +ex5_state_latch: tri_rlmreg_p + generic map (width => ex5_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex5_state_offset to ex5_state_offset+ex5_state_q'length-1), + scout => sov(ex5_state_offset to ex5_state_offset+ex5_state_q'length-1), + din => ex5_state_d(0 to state_width-1), + dout => ex5_state_q(0 to state_width-1) ); +ex5_t_latch: tri_rlmreg_p + generic map (width => ex5_t_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex5_t_offset to ex5_t_offset+ex5_t_q'length-1), + scout => sov(ex5_t_offset to ex5_t_offset+ex5_t_q'length-1), + din => ex5_t_d(0 to t_width-1), + dout => ex5_t_q(0 to t_width-1) ); +-------------------------------------------------- +ex6_valid_latch: tri_rlmreg_p + generic map (width => ex6_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex6_valid_offset to ex6_valid_offset+ex6_valid_q'length-1), + scout => sov(ex6_valid_offset to ex6_valid_offset+ex6_valid_q'length-1), + din => ex6_valid_d(0 to thdid_width-1), + dout => ex6_valid_q(0 to thdid_width-1) ); +ex6_ttype_latch: tri_rlmreg_p + generic map (width => ex6_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex6_ttype_offset to ex6_ttype_offset+ex6_ttype_q'length-1), + scout => sov(ex6_ttype_offset to ex6_ttype_offset+ex6_ttype_q'length-1), + din => ex6_ttype_d(0 to ttype_width-1), + dout => ex6_ttype_q(0 to ttype_width-1) ); +ex6_isel_latch: tri_rlmreg_p + generic map (width => ex6_isel_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex6_isel_offset to ex6_isel_offset+ex6_isel_q'length-1), + scout => sov(ex6_isel_offset to ex6_isel_offset+ex6_isel_q'length-1), + din => ex6_isel_d(0 to ex6_isel_d'length-1), + dout => ex6_isel_q(0 to ex6_isel_q'length-1) ); +ex6_size_latch: tri_rlmreg_p + generic map (width => ex6_size_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex6_size_offset to ex6_size_offset+ex6_size_q'length-1), + scout => sov(ex6_size_offset to ex6_size_offset+ex6_size_q'length-1), + din => ex6_size_d(0 to ex6_size_d'length-1), + dout => ex6_size_q(0 to ex6_size_q'length-1) ); +ex6_gs_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex6_gs_offset), + scout => sov(ex6_gs_offset), + din => ex6_gs_d, + dout => ex6_gs_q); +ex6_ts_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex6_ts_offset), + scout => sov(ex6_ts_offset), + din => ex6_ts_d, + dout => ex6_ts_q); +ex6_ind_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex6_ind_offset), + scout => sov(ex6_ind_offset), + din => ex6_ind_d, + dout => ex6_ind_q); +ex6_pid_latch: tri_rlmreg_p + generic map (width => ex6_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex6_pid_offset to ex6_pid_offset+ex6_pid_q'length-1), + scout => sov(ex6_pid_offset to ex6_pid_offset+ex6_pid_q'length-1), + din => ex6_pid_d(0 to pid_width-1), + dout => ex6_pid_q(0 to pid_width-1) ); +ex6_lpid_latch: tri_rlmreg_p + generic map (width => ex6_lpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex6_lpid_offset to ex6_lpid_offset+ex6_lpid_q'length-1), + scout => sov(ex6_lpid_offset to ex6_lpid_offset+ex6_lpid_q'length-1), + din => ex6_lpid_d(0 to lpid_width-1), + dout => ex6_lpid_q(0 to lpid_width-1) ); +-------------------------------------------------- +inv_seq_latch: tri_rlmreg_p + generic map (width => inv_seq_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(inv_seq_offset to inv_seq_offset+inv_seq_q'length-1), + scout => sov(inv_seq_offset to inv_seq_offset+inv_seq_q'length-1), + din => inv_seq_d(0 to inv_seq_width-1), + dout => inv_seq_q(0 to inv_seq_width-1) ); +hold_req_latch: tri_rlmreg_p + generic map (width => hold_req_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(hold_req_offset to hold_req_offset+hold_req_q'length-1), + scout => sov(hold_req_offset to hold_req_offset+hold_req_q'length-1), + din => hold_req_d(0 to thdid_width-1), + dout => hold_req_q(0 to thdid_width-1) ); +hold_ack_latch: tri_rlmreg_p + generic map (width => hold_ack_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(hold_ack_offset to hold_ack_offset+hold_ack_q'length-1), + scout => sov(hold_ack_offset to hold_ack_offset+hold_ack_q'length-1), + din => hold_ack_d(0 to thdid_width-1), + dout => hold_ack_q(0 to thdid_width-1) ); +hold_done_latch: tri_rlmreg_p + generic map (width => hold_done_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(hold_done_offset to hold_done_offset+hold_done_q'length-1), + scout => sov(hold_done_offset to hold_done_offset+hold_done_q'length-1), + din => hold_done_d(0 to thdid_width-1), + dout => hold_done_q(0 to thdid_width-1) ); +local_barrier_latch: tri_rlmreg_p + generic map (width => local_barrier_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(local_barrier_offset to local_barrier_offset+local_barrier_q'length-1), + scout => sov(local_barrier_offset to local_barrier_offset+local_barrier_q'length-1), + din => local_barrier_d(0 to thdid_width-1), + dout => local_barrier_q(0 to thdid_width-1) ); +global_barrier_latch: tri_rlmreg_p + generic map (width => global_barrier_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(global_barrier_offset to global_barrier_offset+global_barrier_q'length-1), + scout => sov(global_barrier_offset to global_barrier_offset+global_barrier_q'length-1), + din => global_barrier_d(0 to thdid_width-1), + dout => global_barrier_q(0 to thdid_width-1) ); +barrier_done_latch: tri_rlmreg_p + generic map (width => barrier_done_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(barrier_done_offset to barrier_done_offset+barrier_done_q'length-1), + scout => sov(barrier_done_offset to barrier_done_offset+barrier_done_q'length-1), + din => barrier_done_d(0 to thdid_width-1), + dout => barrier_done_q(0 to thdid_width-1)); +illeg_instr_latch: tri_rlmreg_p + generic map (width => illeg_instr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(illeg_instr_offset to illeg_instr_offset+illeg_instr_q'length-1), + scout => sov(illeg_instr_offset to illeg_instr_offset+illeg_instr_q'length-1), + din => illeg_instr_d(0 to thdid_width-1), + dout => illeg_instr_q(0 to thdid_width-1)); +local_reject_latch: tri_rlmreg_p + generic map (width => local_reject_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(local_reject_offset to local_reject_offset+local_reject_q'length-1), + scout => sov(local_reject_offset to local_reject_offset+local_reject_q'length-1), + din => local_reject_d(0 to thdid_width-1), + dout => local_reject_q(0 to thdid_width-1)); +-- snoop output and ack latches 0:ierat, 1:derat, 2:tlb +snoop_coming_latch: tri_rlmreg_p + generic map (width => snoop_coming_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(snoop_coming_offset to snoop_coming_offset+snoop_coming_q'length-1), + scout => sov(snoop_coming_offset to snoop_coming_offset+snoop_coming_q'length-1), + din => snoop_coming_d, + dout => snoop_coming_q ); +snoop_valid_latch: tri_rlmreg_p + generic map (width => snoop_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(snoop_valid_offset to snoop_valid_offset+snoop_valid_q'length-1), + scout => sov(snoop_valid_offset to snoop_valid_offset+snoop_valid_q'length-1), + din => snoop_valid_d, + dout => snoop_valid_q ); +snoop_attr_latch: tri_rlmreg_p + generic map (width => snoop_attr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => snoop_coming_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(snoop_attr_offset to snoop_attr_offset+snoop_attr_q'length-1), + scout => sov(snoop_attr_offset to snoop_attr_offset+snoop_attr_q'length-1), + din => snoop_attr_d, + dout => snoop_attr_q ); +snoop_vpn_latch: tri_rlmreg_p + generic map (width => snoop_vpn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => snoop_coming_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(snoop_vpn_offset to snoop_vpn_offset+snoop_vpn_q'length-1), + scout => sov(snoop_vpn_offset to snoop_vpn_offset+snoop_vpn_q'length-1), + din => snoop_vpn_d(52-epn_width to 51), + dout => snoop_vpn_q(52-epn_width to 51) ); +snoop_attr_clone_latch: tri_rlmreg_p + generic map (width => snoop_attr_clone_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => snoop_coming_q(4), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(snoop_attr_clone_offset to snoop_attr_clone_offset+snoop_attr_clone_q'length-1), + scout => sov(snoop_attr_clone_offset to snoop_attr_clone_offset+snoop_attr_clone_q'length-1), + din => snoop_attr_clone_d, + dout => snoop_attr_clone_q ); +snoop_attr_tlb_spec_latch: tri_rlmreg_p + generic map (width => snoop_attr_tlb_spec_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => snoop_coming_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(snoop_attr_tlb_spec_offset to snoop_attr_tlb_spec_offset+snoop_attr_tlb_spec_q'length-1), + scout => sov(snoop_attr_tlb_spec_offset to snoop_attr_tlb_spec_offset+snoop_attr_tlb_spec_q'length-1), + din => snoop_attr_tlb_spec_d, + dout => snoop_attr_tlb_spec_q ); +snoop_vpn_clone_latch: tri_rlmreg_p + generic map (width => snoop_vpn_clone_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => snoop_coming_q(4), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(snoop_vpn_clone_offset to snoop_vpn_clone_offset+snoop_vpn_clone_q'length-1), + scout => sov(snoop_vpn_clone_offset to snoop_vpn_clone_offset+snoop_vpn_clone_q'length-1), + din => snoop_vpn_clone_d(52-epn_width to 51), + dout => snoop_vpn_clone_q(52-epn_width to 51) ); +snoop_ack_latch: tri_rlmreg_p + generic map (width => snoop_ack_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(snoop_ack_offset to snoop_ack_offset+snoop_ack_q'length-1), + scout => sov(snoop_ack_offset to snoop_ack_offset+snoop_ack_q'length-1), + din => snoop_ack_d, + dout => snoop_ack_q ); +mm_xu_quiesce_latch: tri_rlmreg_p + generic map (width => mm_xu_quiesce_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(mm_xu_quiesce_offset to mm_xu_quiesce_offset+mm_xu_quiesce_q'length-1), + scout => sov(mm_xu_quiesce_offset to mm_xu_quiesce_offset+mm_xu_quiesce_q'length-1), + din => mm_xu_quiesce_d(0 to thdid_width-1), + dout => mm_xu_quiesce_q(0 to thdid_width-1) ); +-- snoop invalidate input latches +an_ac_back_inv_latch: tri_rlmreg_p + generic map (width => an_ac_back_inv_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(an_ac_back_inv_offset to an_ac_back_inv_offset+an_ac_back_inv_q'length-1), + scout => sov(an_ac_back_inv_offset to an_ac_back_inv_offset+an_ac_back_inv_q'length-1), + din => an_ac_back_inv_d, + dout => an_ac_back_inv_q ); +an_ac_back_inv_addr_latch: tri_rlmreg_p + generic map (width => an_ac_back_inv_addr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(an_ac_back_inv_addr_offset to an_ac_back_inv_addr_offset+an_ac_back_inv_addr_q'length-1), + scout => sov(an_ac_back_inv_addr_offset to an_ac_back_inv_addr_offset+an_ac_back_inv_addr_q'length-1), + din => an_ac_back_inv_addr_d(64-real_addr_width to 63), + dout => an_ac_back_inv_addr_q(64-real_addr_width to 63) ); +an_ac_back_inv_lpar_id_latch: tri_rlmreg_p + generic map (width => an_ac_back_inv_lpar_id_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(an_ac_back_inv_lpar_id_offset to an_ac_back_inv_lpar_id_offset+an_ac_back_inv_lpar_id_q'length-1), + scout => sov(an_ac_back_inv_lpar_id_offset to an_ac_back_inv_lpar_id_offset+an_ac_back_inv_lpar_id_q'length-1), + din => an_ac_back_inv_lpar_id_d(0 to lpid_width-1), + dout => an_ac_back_inv_lpar_id_q(0 to lpid_width-1) ); +-- Load/Store unit request interface latches +lsu_tokens_latch: tri_rlmreg_p + generic map (width => lsu_tokens_q'length, init => 1, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lsu_tokens_offset to lsu_tokens_offset+lsu_tokens_q'length-1), + scout => sov(lsu_tokens_offset to lsu_tokens_offset+lsu_tokens_q'length-1), + din => lsu_tokens_d(0 to 1), + dout => lsu_tokens_q(0 to 1) ); +lsu_req_latch: tri_rlmreg_p + generic map (width => lsu_req_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lsu_req_offset to lsu_req_offset+lsu_req_q'length-1), + scout => sov(lsu_req_offset to lsu_req_offset+lsu_req_q'length-1), + din => lsu_req_d(0 to thdid_width-1), + dout => lsu_req_q(0 to thdid_width-1) ); +lsu_ttype_latch: tri_rlmreg_p + generic map (width => lsu_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lsu_ttype_offset to lsu_ttype_offset+lsu_ttype_q'length-1), + scout => sov(lsu_ttype_offset to lsu_ttype_offset+lsu_ttype_q'length-1), + din => lsu_ttype_d(0 to 1), + dout => lsu_ttype_q(0 to 1) ); +lsu_ubits_latch: tri_rlmreg_p + generic map (width => lsu_ubits_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lsu_ubits_offset to lsu_ubits_offset+lsu_ubits_q'length-1), + scout => sov(lsu_ubits_offset to lsu_ubits_offset+lsu_ubits_q'length-1), + din => lsu_ubits_d(0 to 3), + dout => lsu_ubits_q(0 to 3) ); +lsu_wimge_latch: tri_rlmreg_p + generic map (width => lsu_wimge_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lsu_wimge_offset to lsu_wimge_offset+lsu_wimge_q'length-1), + scout => sov(lsu_wimge_offset to lsu_wimge_offset+lsu_wimge_q'length-1), + din => lsu_wimge_d(0 to 4), + dout => lsu_wimge_q(0 to 4) ); +lsu_addr_latch: tri_rlmreg_p + generic map (width => lsu_addr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lsu_addr_offset to lsu_addr_offset+lsu_addr_q'length-1), + scout => sov(lsu_addr_offset to lsu_addr_offset+lsu_addr_q'length-1), + din => lsu_addr_d(64-real_addr_width to 63), + dout => lsu_addr_q(64-real_addr_width to 63) ); +lsu_lpid_latch: tri_rlmreg_p + generic map (width => lsu_lpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lsu_lpid_offset to lsu_lpid_offset+lsu_lpid_q'length-1), + scout => sov(lsu_lpid_offset to lsu_lpid_offset+lsu_lpid_q'length-1), + din => lsu_lpid_d(0 to lpid_width-1), + dout => lsu_lpid_q(0 to lpid_width-1) ); +lsu_ind_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lsu_ind_offset), + scout => sov(lsu_ind_offset), + din => lsu_ind_d, + dout => lsu_ind_q); +lsu_gs_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lsu_gs_offset), + scout => sov(lsu_gs_offset), + din => lsu_gs_d, + dout => lsu_gs_q); +lsu_lbit_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lsu_lbit_offset), + scout => sov(lsu_lbit_offset), + din => lsu_lbit_d, + dout => lsu_lbit_q); +-- core night-night sleep mode +power_managed_latch: tri_rlmreg_p + generic map (width => power_managed_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(power_managed_offset to power_managed_offset+power_managed_q'length-1), + scout => sov(power_managed_offset to power_managed_offset+power_managed_q'length-1), + din => power_managed_d, + dout => power_managed_q ); +tlbwe_back_inv_latch: tri_rlmreg_p + generic map (width => tlbwe_back_inv_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlbwe_back_inv_offset to tlbwe_back_inv_offset+tlbwe_back_inv_q'length-1), + scout => sov(tlbwe_back_inv_offset to tlbwe_back_inv_offset+tlbwe_back_inv_q'length-1), + din => tlbwe_back_inv_d(0 to thdid_width+1), + dout => tlbwe_back_inv_q(0 to thdid_width+1) ); +tlbwe_back_inv_addr_latch: tri_rlmreg_p + generic map (width => tlbwe_back_inv_addr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlbwe_back_inv_addr_offset to tlbwe_back_inv_addr_offset+tlbwe_back_inv_addr_q'length-1), + scout => sov(tlbwe_back_inv_addr_offset to tlbwe_back_inv_addr_offset+tlbwe_back_inv_addr_q'length-1), + din => tlbwe_back_inv_addr_d(0 to epn_width-1), + dout => tlbwe_back_inv_addr_q(0 to epn_width-1) ); +tlbwe_back_inv_attr_latch: tri_rlmreg_p + generic map (width => tlbwe_back_inv_attr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlbwe_back_inv_attr_offset to tlbwe_back_inv_attr_offset+tlbwe_back_inv_attr_q'length-1), + scout => sov(tlbwe_back_inv_attr_offset to tlbwe_back_inv_attr_offset+tlbwe_back_inv_attr_q'length-1), + din => tlbwe_back_inv_attr_d, + dout => tlbwe_back_inv_attr_q ); +inv_seq_inprogress_latch: tri_rlmreg_p + generic map (width => inv_seq_inprogress_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(inv_seq_inprogress_offset to inv_seq_inprogress_offset+inv_seq_inprogress_q'length-1), + scout => sov(inv_seq_inprogress_offset to inv_seq_inprogress_offset+inv_seq_inprogress_q'length-1), + din => inv_seq_inprogress_d, + dout => inv_seq_inprogress_q); +xu_mm_ccr2_notlb_latch: tri_rlmreg_p + generic map (width => xu_mm_ccr2_notlb_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(xu_mm_ccr2_notlb_offset to xu_mm_ccr2_notlb_offset+xu_mm_ccr2_notlb_q'length-1), + scout => sov(xu_mm_ccr2_notlb_offset to xu_mm_ccr2_notlb_offset+xu_mm_ccr2_notlb_q'length-1), + din => xu_mm_ccr2_notlb_d, + dout => xu_mm_ccr2_notlb_q); +spare_latch: tri_rlmreg_p + generic map (width => spare_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(spare_offset to spare_offset+spare_q'length-1), + scout => sov(spare_offset to spare_offset+spare_q'length-1), + din => spare_q, + dout => spare_q); +-- non-scannable config latches +epcr_dgtmi_latch : tri_regk + generic map (width => xu_mm_epcr_dgtmi_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => pc_func_slp_nsl_force, + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_nsl_thold_0_b, + din => xu_mm_spr_epcr_dgtmi, + dout => xu_mm_epcr_dgtmi_q); +lpidr_latch : tri_regk + generic map (width => lpidr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => pc_func_slp_nsl_force, + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_nsl_thold_0_b, + din => lpidr, + dout => lpidr_q); +mmucr1_latch : tri_regk + generic map (width => mmucr1_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => pc_func_slp_nsl_force, + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_nsl_thold_0_b, + din => mmucr1, + dout => mmucr1_q); +mmucr1_csinv_latch : tri_regk + generic map (width => mmucr1_csinv_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => pc_func_slp_nsl_force, + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_nsl_thold_0_b, + din => mmucr1_csinv, + dout => mmucr1_csinv_q); +-------------------------------------------------- +-- thold/sg latches +-------------------------------------------------- +perv_2to1_reg: tri_plat + generic map (width => 5, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ccflush_dc, + din(0) => pc_func_sl_thold_2, + din(1) => pc_func_slp_sl_thold_2, + din(2) => pc_func_slp_nsl_thold_2, + din(3) => pc_sg_2, + din(4) => pc_fce_2, + q(0) => pc_func_sl_thold_1, + q(1) => pc_func_slp_sl_thold_1, + q(2) => pc_func_slp_nsl_thold_1, + q(3) => pc_sg_1, + q(4) => pc_fce_1); +perv_1to0_reg: tri_plat + generic map (width => 5, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ccflush_dc, + din(0) => pc_func_sl_thold_1, + din(1) => pc_func_slp_sl_thold_1, + din(2) => pc_func_slp_nsl_thold_1, + din(3) => pc_sg_1, + din(4) => pc_fce_1, + q(0) => pc_func_sl_thold_0, + q(1) => pc_func_slp_sl_thold_0, + q(2) => pc_func_slp_nsl_thold_0, + q(3) => pc_sg_0, + q(4) => pc_fce_0); +perv_lcbor_func_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b, + thold => pc_func_sl_thold_0, + sg => pc_sg_0, + act_dis => lcb_act_dis_dc, + forcee => pc_func_sl_force, + thold_b => pc_func_sl_thold_0_b); +perv_lcbor_func_slp_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b, + thold => pc_func_slp_sl_thold_0, + sg => pc_sg_0, + act_dis => lcb_act_dis_dc, + forcee => pc_func_slp_sl_force, + thold_b => pc_func_slp_sl_thold_0_b); +perv_nsl_lcbor: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b, + thold => pc_func_slp_nsl_thold_0, + sg => pc_fce_0, + act_dis => tidn, + forcee => pc_func_slp_nsl_force, + thold_b => pc_func_slp_nsl_thold_0_b); +----------------------------------------------------------------------- +-- Scan +----------------------------------------------------------------------- +siv(0 to scan_right) <= sov(1 to scan_right) & ac_func_scan_in; +ac_func_scan_out <= sov(0); +end mmq_inval; +-- PowerISA v2.06 Sec. 6.11.4.4 TLB Lookaside Information (i.e. shadow/erats) +-- If TLBnCFG HES =0, lookaside info is kept coherent with the TLB and is +-- invisible to software. Any write to the TLB that displaces or updates an entry +-- will be reflected in the lookaside info, invalidating the lookaside info +-- corresponding to the previous TLB entry. Any type of invalidation of an +-- entry in TLB will also invalidate the corresponding lookaside info. +-- If TLBnCFG HES =1, lookaside info is not required to be kept coherent with TLB. +-- Only the following conditions will keep coherency. MMUCRS0.tlb0_fi will +-- invalidate ALL lookaside info. tlbilx and tlbivax invalidate lookaside info +-- corresponding to TLB values that they are specified to invalidate as well as +-- those TLB entry values that would have been invalidated except for their +-- IPROT=1 value. +-- Programming Note: If TLBnCFG HES =1 for a TLB array and it is important that lookaside info +-- corresponding to a TLB entry be invalidated, software should use tlbilx or tlbivax +-- to invalidate the VA. +-- Architecture Note: For TLB's with TLBnCFG HES =1, the tlbilx and tlbivax instructions +-- are defined to invalidate lookaside info (but not TLB entries) with IPROT=1 because +-- tlbwe is not guaranteed to invalidate lookaside info corresponding to the previous +-- value of the TLB entry (i.e. for TLBnCFG HES =1). There needs to be a mechanism to +-- invalidate such lookaside information. diff --git a/rel/src/vhdl/work/mmq_perf.vhdl b/rel/src/vhdl/work/mmq_perf.vhdl new file mode 100644 index 0000000..f61982c --- /dev/null +++ b/rel/src/vhdl/work/mmq_perf.vhdl @@ -0,0 +1,758 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +--******************************************************************** +--* +--* TITLE: Performance event mux +--* +--* NAME: mmq_perf.vhdl +--* +--********************************************************************* + + +library ieee; +use ieee.std_logic_1164.all; + +library ibm,clib; +use ibm.std_ulogic_unsigned.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; + +library support; +use support.power_logic_pkg.all; + +library tri; +use tri.tri_latches_pkg.all; + + +entity mmq_perf is +generic(thdid_width : integer := 4; + expand_type : integer := 2 ); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + + pc_func_sl_thold_2 : in std_ulogic; + pc_func_slp_nsl_thold_2 : in std_ulogic; + pc_sg_2 : in std_ulogic; + pc_fce_2 : in std_ulogic; + tc_ac_ccflush_dc : in std_ulogic; + + lcb_clkoff_dc_b : in std_ulogic; + lcb_act_dis_dc : in std_ulogic; + lcb_d_mode_dc : in std_ulogic; + lcb_delay_lclkr_dc : in std_ulogic; + lcb_mpw1_dc_b : in std_ulogic; + lcb_mpw2_dc_b : in std_ulogic; + + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + xu_mm_msr_gs : in std_ulogic_vector(0 to thdid_width-1); + xu_mm_msr_pr : in std_ulogic_vector(0 to thdid_width-1); + xu_mm_ccr2_notlb_b : in std_ulogic; + +-- count event inputs + xu_mm_ex5_perf_dtlb : in std_ulogic_vector(0 to thdid_width-1); + xu_mm_ex5_perf_itlb : in std_ulogic_vector(0 to thdid_width-1); + + tlb_cmp_perf_event_t0 : in std_ulogic_vector(0 to 9); + tlb_cmp_perf_event_t1 : in std_ulogic_vector(0 to 9); + tlb_cmp_perf_event_t2 : in std_ulogic_vector(0 to 9); + tlb_cmp_perf_event_t3 : in std_ulogic_vector(0 to 9); + tlb_cmp_perf_state : in std_ulogic_vector(0 to 1); -- gs & pr + + tlb_cmp_perf_miss_direct : in std_ulogic; + tlb_cmp_perf_hit_indirect : in std_ulogic; + tlb_cmp_perf_hit_first_page : in std_ulogic; + tlb_cmp_perf_ptereload_noexcep : in std_ulogic; + tlb_cmp_perf_lrat_request : in std_ulogic; + tlb_cmp_perf_lrat_miss : in std_ulogic; + tlb_cmp_perf_pt_fault : in std_ulogic; + tlb_cmp_perf_pt_inelig : in std_ulogic; + tlb_ctl_perf_tlbwec_resv : in std_ulogic; + tlb_ctl_perf_tlbwec_noresv : in std_ulogic; + + derat_req0_thdid : in std_ulogic_vector(0 to thdid_width-1); + derat_req0_valid : in std_ulogic; + derat_req1_thdid : in std_ulogic_vector(0 to thdid_width-1); + derat_req1_valid : in std_ulogic; + derat_req2_thdid : in std_ulogic_vector(0 to thdid_width-1); + derat_req2_valid : in std_ulogic; + derat_req3_thdid : in std_ulogic_vector(0 to thdid_width-1); + derat_req3_valid : in std_ulogic; + + ierat_req0_thdid : in std_ulogic_vector(0 to thdid_width-1); + ierat_req0_valid : in std_ulogic; + ierat_req0_nonspec : in std_ulogic; + ierat_req1_thdid : in std_ulogic_vector(0 to thdid_width-1); + ierat_req1_valid : in std_ulogic; + ierat_req1_nonspec : in std_ulogic; + ierat_req2_thdid : in std_ulogic_vector(0 to thdid_width-1); + ierat_req2_valid : in std_ulogic; + ierat_req2_nonspec : in std_ulogic; + ierat_req3_thdid : in std_ulogic_vector(0 to thdid_width-1); + ierat_req3_valid : in std_ulogic; + ierat_req3_nonspec : in std_ulogic; + + ierat_req_taken : in std_ulogic; + derat_req_taken : in std_ulogic; + tlb_tag0_thdid : in std_ulogic_vector(0 to thdid_width-1); + tlb_tag0_type : in std_ulogic_vector(0 to 1); -- derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload + tlb_seq_idle : in std_ulogic; + + inval_perf_tlbilx : in std_ulogic; + inval_perf_tlbivax : in std_ulogic; + inval_perf_tlbivax_snoop : in std_ulogic; + inval_perf_tlb_flush : in std_ulogic; + + htw_req0_valid : in std_ulogic; + htw_req0_thdid : in std_ulogic_vector(0 to thdid_width-1); + htw_req0_type : in std_ulogic_vector(0 to 1); + htw_req1_valid : in std_ulogic; + htw_req1_thdid : in std_ulogic_vector(0 to thdid_width-1); + htw_req1_type : in std_ulogic_vector(0 to 1); + htw_req2_valid : in std_ulogic; + htw_req2_thdid : in std_ulogic_vector(0 to thdid_width-1); + htw_req2_type : in std_ulogic_vector(0 to 1); + htw_req3_valid : in std_ulogic; + htw_req3_thdid : in std_ulogic_vector(0 to thdid_width-1); + htw_req3_type : in std_ulogic_vector(0 to 1); + + +-- control inputs + pc_mm_event_mux_ctrls : in std_ulogic_vector(0 to 39); + pc_mm_event_count_mode : in std_ulogic_vector(0 to 2); -- 0=count events in problem state,1=sup,2=hypv + rp_mm_event_bus_enable_q : in std_ulogic; -- act for perf related latches from repower + + mm_pc_event_data : out std_ulogic_vector(0 to 7) + +); + -- synopsys translate_off + + + -- synopsys translate_on +end mmq_perf; + + +architecture mmq_perf of mmq_perf is +constant rp_mm_event_bus_enable_offset : natural := 0; +constant pc_mm_event_mux_ctrls_offset : natural := rp_mm_event_bus_enable_offset + 1; +constant pc_mm_event_count_mode_offset : natural := pc_mm_event_mux_ctrls_offset + 40; +constant xu_mm_msr_gs_offset : natural := pc_mm_event_count_mode_offset + 3; +constant xu_mm_msr_pr_offset : natural := xu_mm_msr_gs_offset + thdid_width; +constant event_data_offset : natural := xu_mm_msr_pr_offset + thdid_width; +constant scan_right : natural := event_data_offset + 8 -1; + +signal event_data_d : std_ulogic_vector(0 to 7); +signal event_data_q : std_ulogic_vector(0 to 7); +signal rp_mm_event_bus_enable_int_q : std_ulogic; +signal pc_mm_event_mux_ctrls_q : std_ulogic_vector(0 to 39); +signal pc_mm_event_count_mode_q : std_ulogic_vector(0 to 2); -- 0=count events in problem state,1=sup,2=hypv + +signal mm_perf_event_t0_d, mm_perf_event_t0_q : std_ulogic_vector(0 to 15); +signal mm_perf_event_t1_d, mm_perf_event_t1_q : std_ulogic_vector(0 to 15); +signal mm_perf_event_t2_d, mm_perf_event_t2_q : std_ulogic_vector(0 to 15); +signal mm_perf_event_t3_d, mm_perf_event_t3_q : std_ulogic_vector(0 to 15); + +signal xu_mm_msr_gs_q : std_ulogic_vector(0 to thdid_width-1); +signal xu_mm_msr_pr_q : std_ulogic_vector(0 to thdid_width-1); +signal event_en : std_ulogic_vector(0 to thdid_width); + +signal siv : std_ulogic_vector(0 to scan_right); +signal sov : std_ulogic_vector(0 to scan_right); + +signal tidn : std_ulogic; +signal tiup : std_ulogic; + +signal pc_func_sl_thold_1 : std_ulogic; +signal pc_func_sl_thold_0 : std_ulogic; +signal pc_func_sl_thold_0_b : std_ulogic; +signal pc_func_slp_nsl_thold_1 : std_ulogic; +signal pc_func_slp_nsl_thold_0 : std_ulogic; +signal pc_func_slp_nsl_thold_0_b : std_ulogic; +signal pc_func_slp_nsl_force : std_ulogic; +signal pc_sg_1 : std_ulogic; +signal pc_sg_0 : std_ulogic; +signal pc_fce_1 : std_ulogic; +signal pc_fce_0 : std_ulogic; +signal forcee : std_ulogic; + +begin + +----------------------------------------------------------------------- +-- Logic +----------------------------------------------------------------------- + +tidn <= '0'; +tiup <= '1'; + +event_en(0 to 3) <= ( xu_mm_msr_pr_q(0 to 3) and (0 to 3 => pc_mm_event_count_mode_q(0))) or -- User + (not xu_mm_msr_pr_q(0 to 3) and xu_mm_msr_gs_q(0 to 3) and (0 to 3 => pc_mm_event_count_mode_q(1))) or -- Guest Supervisor + (not xu_mm_msr_pr_q(0 to 3) and not xu_mm_msr_gs_q(0 to 3) and (0 to 3 => pc_mm_event_count_mode_q(2))); -- Hypervisor + +--tlb_cmp_perf_state: 0 =gs, 1=pr +event_en(4) <= (tlb_cmp_perf_state(1) and pc_mm_event_count_mode_q(0)) or -- User + (not tlb_cmp_perf_state(1) and tlb_cmp_perf_state(0) and pc_mm_event_count_mode_q(1)) or -- Guest Supervisor + (not tlb_cmp_perf_state(1) and not tlb_cmp_perf_state(0) and pc_mm_event_count_mode_q(2)); -- Hypervisor + + +---------------------------------------------------- +-- t* threadwise event list +---------------------------------------------------- +-- 0 TLB hit direct entry (instr.) (ind=0 entry hit for fetch) +-- 1 TLB miss direct entry (instr.) (ind=0 entry missed for fetch) +-- 2 TLB miss indirect entry (instr.) (ind=1 entry missed for fetch, results in i-tlb exception) +-- 3 H/W tablewalk hit (instr.) (ptereload with PTE.V=1 for fetch) +-- 4 H/W tablewalk miss (instr.) (ptereload with PTE.V=0 for fetch, results in PT fault exception -> isi) +-- 5 TLB hit direct entry (data) (ind=0 entry hit for load/store/cache op) +-- 6 TLB miss direct entry (data) (ind=0 entry miss for load/store/cache op) +-- 7 TLB miss indirect entry (data) (ind=1 entry missed for load/store/cache op, results in d-tlb exception) +-- 8 H/W tablewalk hit (data) (ptereload with PTE.V=1 for load/store/cache op) +-- 9 H/W tablewalk miss (data) (ptereload with PTE.V=0 for load/store/cache op, results in PT fault exception -> dsi) +-- 10 IERAT miss (or latency), edge (or level) (total ierat misses or latency) +-- 11 DERAT miss (or latency), edge (or level) (total derat misses or latency) + +---------------------------------------------------- +-- core single event list +---------------------------------------------------- +-- t0 group +-- 12 IERAT miss total (part of direct entry search total) +-- 13 DERAT miss total (part of direct entry search total) +-- 14 TLB miss direct entry total (total TLB ind=0 misses) +-- 15 TLB hit direct entry first page size +---------------------------------------------------- +-- t1 group +-- 12 TLB indirect entry hits total (=page table searches) +-- 13 H/W tablewalk successful installs total (with no PTfault, TLB ineligible, or LRAT miss) +-- 14 LRAT translation request total (for GS=1 tlbwe and ptereload) +-- 15 LRAT misses total (for GS=1 tlbwe and ptereload) +---------------------------------------------------- +-- t2 group +-- 12 Page table faults total (PTE.V=0 for ptereload, resulting in isi/dsi) +-- 13 TLB ineligible total (all TLB ways are iprot=1 for ptereloads, resulting in isi/dsi) +-- 14 tlbwe conditional failed total (total tlbwe WQ=01 with no reservation match) +-- 15 tlbwe conditional success total (total tlbwe WQ=01 with reservation match) +---------------------------------------------------- +-- t3 group +-- 12 tlbilx local invalidations sourced total (sourced tlbilx on this core total) +-- 13 tlbivax invalidations sourced total (sourced tlbivax on this core total) +-- 14 tlbivax snoops total (total tlbivax snoops received from bus, local bit = don't care) +-- 15 TLB flush requests total (TLB requested flushes due to TLB busy or instruction hazards) +---------------------------------------------------- + + +-- 0 TLB hit direct entry (instr.) (ind=0 entry hit for fetch) +-- 1 TLB miss direct entry (instr.) (ind=0 entry missed for fetch) +-- 2 TLB miss indirect entry (instr.) (ind=1 entry missed for fetch, results in i-tlb exception) +-- 3 H/W tablewalk hit (instr.) (ptereload with PTE.V=1 for fetch) +-- 4 H/W tablewalk miss (instr.) (ptereload with PTE.V=0 for fetch, results in PT fault exception -> isi) +-- 5 TLB hit direct entry (data) (ind=0 entry hit for load/store/cache op) +-- 6 TLB miss direct entry (data) (ind=0 entry miss for load/store/cache op) +-- 7 TLB miss indirect entry (data) (ind=1 entry missed for load/store/cache op, results in d-tlb exception) +-- 8 H/W tablewalk hit (data) (ptereload with PTE.V=1 for load/store/cache op) +-- 9 H/W tablewalk miss (data) (ptereload with PTE.V=0 for load/store/cache op, results in PT fault exception -> dsi) +mm_perf_event_t0_d(0 to 9) <= tlb_cmp_perf_event_t0(0 to 9) and (0 to 9 => event_en(0)); + +-- 10 IERAT miss (or latency), edge (or level) (total ierat misses or latency) +-- type: derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload +mm_perf_event_t0_d(10) <= (((ierat_req0_valid and ierat_req0_nonspec and ierat_req0_thdid(0)) or + (ierat_req1_valid and ierat_req1_nonspec and ierat_req1_thdid(0)) or + (ierat_req2_valid and ierat_req2_nonspec and ierat_req2_thdid(0)) or + (ierat_req3_valid and ierat_req3_nonspec and ierat_req3_thdid(0)) or + -- ierat nonspec miss request + (not tlb_seq_idle and tlb_tag0_type(1) and tlb_tag0_thdid(0)) or + -- searching tlb for direct entry, or ptereload of instr + (htw_req0_valid and htw_req0_type(1) and htw_req0_thdid(0)) or + (htw_req1_valid and htw_req1_type(1) and htw_req1_thdid(0)) or + (htw_req2_valid and htw_req2_type(1) and htw_req2_thdid(0)) or + (htw_req3_valid and htw_req3_type(1) and htw_req3_thdid(0))) + -- htw servicing miss of instr + and xu_mm_ccr2_notlb_b) + or (xu_mm_ex5_perf_itlb(0) and not xu_mm_ccr2_notlb_b); + +-- 11 DERAT miss (or latency), edge (or level) (total derat misses or latency) +-- type: derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload +mm_perf_event_t0_d(11) <= (((derat_req0_valid and derat_req0_thdid(0)) or + (derat_req1_valid and derat_req1_thdid(0)) or + (derat_req2_valid and derat_req2_thdid(0)) or + (derat_req3_valid and derat_req3_thdid(0)) or + -- derat nonspec miss request + (not tlb_seq_idle and tlb_tag0_type(0) and tlb_tag0_thdid(0)) or + -- searching tlb for direct entry, or ptereload of data + (htw_req0_valid and htw_req0_type(0) and htw_req0_thdid(0)) or + (htw_req1_valid and htw_req1_type(0) and htw_req1_thdid(0)) or + (htw_req2_valid and htw_req2_type(0) and htw_req2_thdid(0)) or + (htw_req3_valid and htw_req3_type(0) and htw_req3_thdid(0))) + -- htw servicing miss of data + and xu_mm_ccr2_notlb_b) + or (xu_mm_ex5_perf_dtlb(0) and not xu_mm_ccr2_notlb_b); + +-- 12 IERAT miss total (part of direct entry search total) +mm_perf_event_t0_d(12) <= ierat_req_taken; + +-- 13 DERAT miss total (part of direct entry search total) +mm_perf_event_t0_d(13) <= derat_req_taken; + +-- 14 TLB miss direct entry total (total TLB ind=0 misses) +mm_perf_event_t0_d(14) <= tlb_cmp_perf_miss_direct and event_en(4); + +-- 15 TLB hit direct entry first page size +mm_perf_event_t0_d(15) <= tlb_cmp_perf_hit_first_page and event_en(4); + + + +-- 0 TLB hit direct entry (instr.) (ind=0 entry hit for fetch) +-- 1 TLB miss direct entry (instr.) (ind=0 entry missed for fetch) +-- 2 TLB miss indirect entry (instr.) (ind=1 entry missed for fetch, results in i-tlb exception) +-- 3 H/W tablewalk hit (instr.) (ptereload with PTE.V=1 for fetch) +-- 4 H/W tablewalk miss (instr.) (ptereload with PTE.V=0 for fetch, results in PT fault exception -> isi) +-- 5 TLB hit direct entry (data) (ind=0 entry hit for load/store/cache op) +-- 6 TLB miss direct entry (data) (ind=0 entry miss for load/store/cache op) +-- 7 TLB miss indirect entry (data) (ind=1 entry missed for load/store/cache op, results in d-tlb exception) +-- 8 H/W tablewalk hit (data) (ptereload with PTE.V=1 for load/store/cache op) +-- 9 H/W tablewalk miss (data) (ptereload with PTE.V=0 for load/store/cache op, results in PT fault exception -> dsi) +mm_perf_event_t1_d(0 to 9) <= tlb_cmp_perf_event_t1(0 to 9) and (0 to 9 => event_en(1)); + +-- 10 IERAT miss (or latency), edge (or level) (total ierat misses or latency) +-- type: derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload +mm_perf_event_t1_d(10) <= (((ierat_req0_valid and ierat_req0_nonspec and ierat_req0_thdid(1)) or + (ierat_req1_valid and ierat_req1_nonspec and ierat_req1_thdid(1)) or + (ierat_req2_valid and ierat_req2_nonspec and ierat_req2_thdid(1)) or + (ierat_req3_valid and ierat_req3_nonspec and ierat_req3_thdid(1)) or + -- ierat nonspec miss request + (not tlb_seq_idle and tlb_tag0_type(1) and tlb_tag0_thdid(1)) or + -- searching tlb for direct entry, or ptereload of instr + (htw_req0_valid and htw_req0_type(1) and htw_req0_thdid(1)) or + (htw_req1_valid and htw_req1_type(1) and htw_req1_thdid(1)) or + (htw_req2_valid and htw_req2_type(1) and htw_req2_thdid(1)) or + (htw_req3_valid and htw_req3_type(1) and htw_req3_thdid(1))) + -- htw servicing miss of instr + and xu_mm_ccr2_notlb_b) + or (xu_mm_ex5_perf_itlb(1) and not xu_mm_ccr2_notlb_b); + +-- 11 DERAT miss (or latency), edge (or level) (total derat misses or latency) +-- type: derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload +mm_perf_event_t1_d(11) <= (((derat_req0_valid and derat_req0_thdid(1)) or + (derat_req1_valid and derat_req1_thdid(1)) or + (derat_req2_valid and derat_req2_thdid(1)) or + (derat_req3_valid and derat_req3_thdid(1)) or + -- derat nonspec miss request + (not tlb_seq_idle and tlb_tag0_type(0) and tlb_tag0_thdid(1)) or + -- searching tlb for direct entry, or ptereload of data + (htw_req0_valid and htw_req0_type(0) and htw_req0_thdid(1)) or + (htw_req1_valid and htw_req1_type(0) and htw_req1_thdid(1)) or + (htw_req2_valid and htw_req2_type(0) and htw_req2_thdid(1)) or + (htw_req3_valid and htw_req3_type(0) and htw_req3_thdid(1))) + -- htw servicing miss of data + and xu_mm_ccr2_notlb_b) + or (xu_mm_ex5_perf_dtlb(1) and not xu_mm_ccr2_notlb_b); + +-- 12 TLB indirect entry hits total (=page table searches) +mm_perf_event_t1_d(12) <= tlb_cmp_perf_hit_indirect and event_en(4); + +-- 13 H/W tablewalk successful installs total (with no PTfault, TLB ineligible, or LRAT miss) +mm_perf_event_t1_d(13) <= tlb_cmp_perf_ptereload_noexcep and event_en(4); + +-- 14 LRAT translation request total (for GS=1 tlbwe and ptereload) +mm_perf_event_t1_d(14) <= tlb_cmp_perf_lrat_request and event_en(4); + +-- 15 LRAT misses total (for GS=1 tlbwe and ptereload) +mm_perf_event_t1_d(15) <= tlb_cmp_perf_lrat_miss and event_en(4); + + +-- 0 TLB hit direct entry (instr.) (ind=0 entry hit for fetch) +-- 1 TLB miss direct entry (instr.) (ind=0 entry missed for fetch) +-- 2 TLB miss indirect entry (instr.) (ind=1 entry missed for fetch, results in i-tlb exception) +-- 3 H/W tablewalk hit (instr.) (ptereload with PTE.V=1 for fetch) +-- 4 H/W tablewalk miss (instr.) (ptereload with PTE.V=0 for fetch, results in PT fault exception -> isi) +-- 5 TLB hit direct entry (data) (ind=0 entry hit for load/store/cache op) +-- 6 TLB miss direct entry (data) (ind=0 entry miss for load/store/cache op) +-- 7 TLB miss indirect entry (data) (ind=1 entry missed for load/store/cache op, results in d-tlb exception) +-- 8 H/W tablewalk hit (data) (ptereload with PTE.V=1 for load/store/cache op) +-- 9 H/W tablewalk miss (data) (ptereload with PTE.V=0 for load/store/cache op, results in PT fault exception -> dsi) +mm_perf_event_t2_d(0 to 9) <= tlb_cmp_perf_event_t2(0 to 9) and (0 to 9 => event_en(2)); + +-- 10 IERAT miss (or latency), edge (or level) (total ierat misses or latency) +-- type: derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload +mm_perf_event_t2_d(10) <= (((ierat_req0_valid and ierat_req0_nonspec and ierat_req0_thdid(2)) or + (ierat_req1_valid and ierat_req1_nonspec and ierat_req1_thdid(2)) or + (ierat_req2_valid and ierat_req2_nonspec and ierat_req2_thdid(2)) or + (ierat_req3_valid and ierat_req3_nonspec and ierat_req3_thdid(2)) or + -- ierat nonspec miss request + (not tlb_seq_idle and tlb_tag0_type(1) and tlb_tag0_thdid(2)) or + -- searching tlb for direct entry, or ptereload of instr + (htw_req0_valid and htw_req0_type(1) and htw_req0_thdid(2)) or + (htw_req1_valid and htw_req1_type(1) and htw_req1_thdid(2)) or + (htw_req2_valid and htw_req2_type(1) and htw_req2_thdid(2)) or + (htw_req3_valid and htw_req3_type(1) and htw_req3_thdid(2))) + -- htw servicing miss of instr + and xu_mm_ccr2_notlb_b) + or (xu_mm_ex5_perf_itlb(2) and not xu_mm_ccr2_notlb_b); + +-- 11 DERAT miss (or latency), edge (or level) (total derat misses or latency) +-- type: derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload +mm_perf_event_t2_d(11) <= (((derat_req0_valid and derat_req0_thdid(2)) or + (derat_req1_valid and derat_req1_thdid(2)) or + (derat_req2_valid and derat_req2_thdid(2)) or + (derat_req3_valid and derat_req3_thdid(2)) or + -- derat nonspec miss request + (not tlb_seq_idle and tlb_tag0_type(0) and tlb_tag0_thdid(2)) or + -- searching tlb for direct entry, or ptereload of data + (htw_req0_valid and htw_req0_type(0) and htw_req0_thdid(2)) or + (htw_req1_valid and htw_req1_type(0) and htw_req1_thdid(2)) or + (htw_req2_valid and htw_req2_type(0) and htw_req2_thdid(2)) or + (htw_req3_valid and htw_req3_type(0) and htw_req3_thdid(2))) + -- htw servicing miss of data + and xu_mm_ccr2_notlb_b) + or (xu_mm_ex5_perf_dtlb(2) and not xu_mm_ccr2_notlb_b); + -- htw servicing miss of data + +-- 12 Page table faults total (PTE.V=0 for ptereload, resulting in isi/dsi) +mm_perf_event_t2_d(12) <= tlb_cmp_perf_pt_fault and event_en(4); + +-- 13 TLB ineligible total (all TLB ways are iprot=1 for ptereloads, resulting in isi/dsi) +mm_perf_event_t2_d(13) <= tlb_cmp_perf_pt_inelig and event_en(4); + +-- 14 tlbwe conditional failed total (total tlbwe WQ=01 with no reservation match) +mm_perf_event_t2_d(14) <= tlb_ctl_perf_tlbwec_noresv and event_en(4); + +-- 15 tlbwe conditional success total (total tlbwe WQ=01 with reservation match) +mm_perf_event_t2_d(15) <= tlb_ctl_perf_tlbwec_resv and event_en(4); + + +---------------------------------------------------- +-- 0 TLB hit direct entry (instr.) (ind=0 entry hit for fetch) +-- 1 TLB miss direct entry (instr.) (ind=0 entry missed for fetch) +-- 2 TLB miss indirect entry (instr.) (ind=1 entry missed for fetch, results in i-tlb exception) +-- 3 H/W tablewalk hit (instr.) (ptereload with PTE.V=1 for fetch) +-- 4 H/W tablewalk miss (instr.) (ptereload with PTE.V=0 for fetch, results in PT fault exception -> isi) +-- 5 TLB hit direct entry (data) (ind=0 entry hit for load/store/cache op) +-- 6 TLB miss direct entry (data) (ind=0 entry miss for load/store/cache op) +-- 7 TLB miss indirect entry (data) (ind=1 entry missed for load/store/cache op, results in d-tlb exception) +-- 8 H/W tablewalk hit (data) (ptereload with PTE.V=1 for load/store/cache op) +-- 9 H/W tablewalk miss (data) (ptereload with PTE.V=0 for load/store/cache op, results in PT fault exception -> dsi) +mm_perf_event_t3_d(0 to 9) <= tlb_cmp_perf_event_t3(0 to 9) and (0 to 9 => event_en(3)); + +-- 10 IERAT miss (or latency), edge (or level) (total ierat misses or latency) +-- type: derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload +mm_perf_event_t3_d(10) <= (((ierat_req0_valid and ierat_req0_nonspec and ierat_req0_thdid(3)) or + (ierat_req1_valid and ierat_req1_nonspec and ierat_req1_thdid(3)) or + (ierat_req2_valid and ierat_req2_nonspec and ierat_req2_thdid(3)) or + (ierat_req3_valid and ierat_req3_nonspec and ierat_req3_thdid(3)) or + -- ierat nonspec miss request + (not tlb_seq_idle and tlb_tag0_type(1) and tlb_tag0_thdid(3)) or + -- searching tlb for direct entry, or ptereload of instr + (htw_req0_valid and htw_req0_type(1) and htw_req0_thdid(3)) or + (htw_req1_valid and htw_req1_type(1) and htw_req1_thdid(3)) or + (htw_req2_valid and htw_req2_type(1) and htw_req2_thdid(3)) or + (htw_req3_valid and htw_req3_type(1) and htw_req3_thdid(3))) + -- htw servicing miss of instr + and xu_mm_ccr2_notlb_b) + or (xu_mm_ex5_perf_itlb(3) and not xu_mm_ccr2_notlb_b); + +-- 11 DERAT miss (or latency), edge (or level) (total derat misses or latency) +-- type: derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload +mm_perf_event_t3_d(11) <= (((derat_req0_valid and derat_req0_thdid(3)) or + (derat_req1_valid and derat_req1_thdid(3)) or + (derat_req2_valid and derat_req2_thdid(3)) or + (derat_req3_valid and derat_req3_thdid(3)) or + -- derat nonspec miss request + (not tlb_seq_idle and tlb_tag0_type(0) and tlb_tag0_thdid(3)) or + -- searching tlb for direct entry, or ptereload of data + (htw_req0_valid and htw_req0_type(0) and htw_req0_thdid(3)) or + (htw_req1_valid and htw_req1_type(0) and htw_req1_thdid(3)) or + (htw_req2_valid and htw_req2_type(0) and htw_req2_thdid(3)) or + (htw_req3_valid and htw_req3_type(0) and htw_req3_thdid(3))) + -- htw servicing miss of data + and xu_mm_ccr2_notlb_b) + or (xu_mm_ex5_perf_dtlb(3) and not xu_mm_ccr2_notlb_b); + +-- t3 group +-- 12 tlbilx local invalidations sourced total (sourced tlbilx on this core total) +mm_perf_event_t3_d(12) <= inval_perf_tlbilx; + +-- 13 tlbivax invalidations sourced total (sourced tlbivax on this core total) +mm_perf_event_t3_d(13) <= inval_perf_tlbivax; + +-- 14 tlbivax snoops total (total tlbivax snoops received from bus, local bit = don't care) +mm_perf_event_t3_d(14) <= inval_perf_tlbivax_snoop; + +-- 15 TLB flush requests total (TLB requested flushes due to TLB busy or instruction hazards) +mm_perf_event_t3_d(15) <= inval_perf_tlb_flush; + +---------------------------------------------------- + +event_mux1: entity clib.c_event_mux + generic map ( events_in => 64, + events_out => 8 ) + port map( + vd => vdd, + gd => gnd, + + t0_events => mm_perf_event_t0_q(0 to 15), + t1_events => mm_perf_event_t1_q(0 to 15), + t2_events => mm_perf_event_t2_q(0 to 15), + t3_events => mm_perf_event_t3_q(0 to 15), + + select_bits => pc_mm_event_mux_ctrls_q(0 to 39), + event_bits => event_data_d(0 to 7) +); + + +mm_pc_event_data <= event_data_q(0 to 7); + + +----------------------------------------------------------------------- +-- Latches +----------------------------------------------------------------------- + +rp_mm_event_bus_enable_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_sl_thold_0_b, + sg => pc_sg_0, + forcee => forcee, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(rp_mm_event_bus_enable_offset), + scout => sov(rp_mm_event_bus_enable_offset), + din => rp_mm_event_bus_enable_q, -- yes, this in the input name + dout => rp_mm_event_bus_enable_int_q); -- this is local internal version + +pc_mm_event_mux_ctrls_latch: tri_rlmreg_p + generic map (width => pc_mm_event_mux_ctrls_q'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_sl_thold_0_b, + sg => pc_sg_0, + forcee => forcee, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(pc_mm_event_mux_ctrls_offset to pc_mm_event_mux_ctrls_offset + pc_mm_event_mux_ctrls_q'length-1), + scout => sov(pc_mm_event_mux_ctrls_offset to pc_mm_event_mux_ctrls_offset + pc_mm_event_mux_ctrls_q'length-1), + din => pc_mm_event_mux_ctrls, + dout => pc_mm_event_mux_ctrls_q ); + +pc_mm_event_count_mode_latch: tri_rlmreg_p + generic map (width => pc_mm_event_count_mode_q'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_sl_thold_0_b, + sg => pc_sg_0, + forcee => forcee, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(pc_mm_event_count_mode_offset to pc_mm_event_count_mode_offset + pc_mm_event_count_mode_q'length-1), + scout => sov(pc_mm_event_count_mode_offset to pc_mm_event_count_mode_offset + pc_mm_event_count_mode_q'length-1), + din => pc_mm_event_count_mode, + dout => pc_mm_event_count_mode_q ); + +xu_mm_msr_gs_latch: tri_rlmreg_p + generic map (width => xu_mm_msr_gs_q'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rp_mm_event_bus_enable_int_q, + thold_b => pc_func_sl_thold_0_b, + sg => pc_sg_0, + forcee => forcee, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(xu_mm_msr_gs_offset to xu_mm_msr_gs_offset + xu_mm_msr_gs_q'length-1), + scout => sov(xu_mm_msr_gs_offset to xu_mm_msr_gs_offset + xu_mm_msr_gs_q'length-1), + din => xu_mm_msr_gs, + dout => xu_mm_msr_gs_q ); + +xu_mm_msr_pr_latch: tri_rlmreg_p + generic map (width => xu_mm_msr_pr_q'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rp_mm_event_bus_enable_int_q, + thold_b => pc_func_sl_thold_0_b, + sg => pc_sg_0, + forcee => forcee, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(xu_mm_msr_pr_offset to xu_mm_msr_pr_offset + xu_mm_msr_pr_q'length-1), + scout => sov(xu_mm_msr_pr_offset to xu_mm_msr_pr_offset + xu_mm_msr_pr_q'length-1), + din => xu_mm_msr_pr, + dout => xu_mm_msr_pr_q ); + + +event_data_latch: tri_rlmreg_p + generic map (width => event_data_q'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rp_mm_event_bus_enable_int_q, + thold_b => pc_func_sl_thold_0_b, + sg => pc_sg_0, + forcee => forcee, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(event_data_offset to event_data_offset + event_data_q'length-1), + scout => sov(event_data_offset to event_data_offset + event_data_q'length-1), + din => event_data_d, + dout => event_data_q ); + +mm_perf_event_t0_latch : tri_regk + generic map (width => mm_perf_event_t0_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rp_mm_event_bus_enable_int_q, + forcee => pc_func_slp_nsl_force, + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_nsl_thold_0_b, + din => mm_perf_event_t0_d, + dout => mm_perf_event_t0_q ); + +mm_perf_event_t1_latch : tri_regk + generic map (width => mm_perf_event_t1_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rp_mm_event_bus_enable_int_q, + forcee => pc_func_slp_nsl_force, + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_nsl_thold_0_b, + din => mm_perf_event_t1_d, + dout => mm_perf_event_t1_q ); + +mm_perf_event_t2_latch : tri_regk + generic map (width => mm_perf_event_t2_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rp_mm_event_bus_enable_int_q, + forcee => pc_func_slp_nsl_force, + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_nsl_thold_0_b, + din => mm_perf_event_t2_d, + dout => mm_perf_event_t2_q ); + +mm_perf_event_t3_latch : tri_regk + generic map (width => mm_perf_event_t3_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rp_mm_event_bus_enable_int_q, + forcee => pc_func_slp_nsl_force, + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_nsl_thold_0_b, + din => mm_perf_event_t3_d, + dout => mm_perf_event_t3_q ); + + +------------------------------------------------- +-- pervasive +------------------------------------------------- + +perv_2to1_reg: tri_plat + generic map (width => 4, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_func_sl_thold_2, + din(1) => pc_func_slp_nsl_thold_2, + din(2) => pc_sg_2, + din(3) => pc_fce_2, + q(0) => pc_func_sl_thold_1, + q(1) => pc_func_slp_nsl_thold_1, + q(2) => pc_sg_1, + q(3) => pc_fce_1); + +perv_1to0_reg: tri_plat + generic map (width => 4, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0) => pc_func_sl_thold_1, + din(1) => pc_func_slp_nsl_thold_1, + din(2) => pc_sg_1, + din(3) => pc_fce_1, + q(0) => pc_func_sl_thold_0, + q(1) => pc_func_slp_nsl_thold_0, + q(2) => pc_sg_0, + q(3) => pc_fce_0); + +perv_lcbor: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b, + thold => pc_func_sl_thold_0, + sg => pc_sg_0, + act_dis => lcb_act_dis_dc, + forcee => forcee, + thold_b => pc_func_sl_thold_0_b); + +perv_nsl_lcbor: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b, + thold => pc_func_slp_nsl_thold_0, + sg => pc_fce_0, + act_dis => tidn, + forcee => pc_func_slp_nsl_force, + thold_b => pc_func_slp_nsl_thold_0_b); + +----------------------------------------------------------------------- +-- Scan +----------------------------------------------------------------------- +siv(0 to scan_right) <= sov(1 to scan_right) & scan_in; +scan_out <= sov(0); + + +end mmq_perf; diff --git a/rel/src/vhdl/work/mmq_perv.vhdl b/rel/src/vhdl/work/mmq_perv.vhdl new file mode 100644 index 0000000..6a6c915 --- /dev/null +++ b/rel/src/vhdl/work/mmq_perv.vhdl @@ -0,0 +1,849 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + + +library ieee; +use ieee.std_logic_1164.all; + +library ibm; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; + +library support; +use support.power_logic_pkg.all; + +library tri; +use tri.tri_latches_pkg.all; + +entity mmq_perv is +generic(expand_type : integer := 2 ); -- 0 = ibm umbra, 1 = xilinx, 2 = ibm mpg +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + pc_mm_sg_3 : in std_ulogic_vector(0 to 1); + pc_mm_func_sl_thold_3 : in std_ulogic_vector(0 to 1); + pc_mm_func_slp_sl_thold_3 : in std_ulogic_vector(0 to 1); + pc_mm_gptr_sl_thold_3 : in std_ulogic; + pc_mm_fce_3 : in std_ulogic; + + pc_mm_time_sl_thold_3 : in std_ulogic; + pc_mm_repr_sl_thold_3 : in std_ulogic; + pc_mm_abst_sl_thold_3 : in std_ulogic; + pc_mm_abst_slp_sl_thold_3 : in std_ulogic; + pc_mm_cfg_sl_thold_3 : in std_ulogic; + pc_mm_cfg_slp_sl_thold_3 : in std_ulogic; + pc_mm_func_nsl_thold_3 : in std_ulogic; + pc_mm_func_slp_nsl_thold_3 : in std_ulogic; + pc_mm_ary_nsl_thold_3 : in std_ulogic; + pc_mm_ary_slp_nsl_thold_3 : in std_ulogic; + + tc_ac_ccflush_dc : in std_ulogic; + tc_scan_diag_dc : in std_ulogic; + tc_ac_scan_dis_dc_b : in std_ulogic; + + pc_sg_0 : out std_ulogic_vector(0 to 1); + pc_sg_1 : out std_ulogic_vector(0 to 1); + pc_sg_2 : out std_ulogic_vector(0 to 1); + pc_func_sl_thold_2 : out std_ulogic_vector(0 to 1); + pc_func_slp_sl_thold_2 : out std_ulogic_vector(0 to 1); + pc_func_slp_nsl_thold_2 : out std_ulogic; + pc_cfg_sl_thold_2 : out std_ulogic; + pc_cfg_slp_sl_thold_2 : out std_ulogic; + pc_fce_2 : out std_ulogic; + + pc_time_sl_thold_0 : out std_ulogic; + pc_repr_sl_thold_0 : out std_ulogic; + pc_abst_sl_thold_0 : out std_ulogic; + pc_abst_slp_sl_thold_0 : out std_ulogic; + pc_ary_nsl_thold_0 : out std_ulogic; + pc_ary_slp_nsl_thold_0 : out std_ulogic; + pc_func_sl_thold_0 : out std_ulogic_vector(0 to 1); + pc_func_sl_thold_0_b : out std_ulogic_vector(0 to 1); + pc_func_slp_sl_thold_0 : out std_ulogic_vector(0 to 1); + pc_func_slp_sl_thold_0_b : out std_ulogic_vector(0 to 1); + + lcb_clkoff_dc_b : out std_ulogic; + lcb_act_dis_dc : out std_ulogic; + lcb_d_mode_dc : out std_ulogic; + lcb_delay_lclkr_dc : out std_ulogic_vector(0 to 4); + lcb_mpw1_dc_b : out std_ulogic_vector(0 to 4); + lcb_mpw2_dc_b : out std_ulogic; + g6t_gptr_lcb_clkoff_dc_b : out std_ulogic; + g6t_gptr_lcb_act_dis_dc : out std_ulogic; + g6t_gptr_lcb_d_mode_dc : out std_ulogic; + g6t_gptr_lcb_delay_lclkr_dc : out std_ulogic_vector(0 to 4); + g6t_gptr_lcb_mpw1_dc_b : out std_ulogic_vector(0 to 4); + g6t_gptr_lcb_mpw2_dc_b : out std_ulogic; + g8t_gptr_lcb_clkoff_dc_b : out std_ulogic; + g8t_gptr_lcb_act_dis_dc : out std_ulogic; + g8t_gptr_lcb_d_mode_dc : out std_ulogic; + g8t_gptr_lcb_delay_lclkr_dc : out std_ulogic_vector(0 to 4); + g8t_gptr_lcb_mpw1_dc_b : out std_ulogic_vector(0 to 4); + g8t_gptr_lcb_mpw2_dc_b : out std_ulogic; + + + -- abist engine controls for arrays from pervasive + pc_mm_abist_dcomp_g6t_2r : in std_ulogic_vector(0 to 3); + pc_mm_abist_di_0 : in std_ulogic_vector(0 to 3); + pc_mm_abist_di_g6t_2r : in std_ulogic_vector(0 to 3); + pc_mm_abist_ena_dc : in std_ulogic; + pc_mm_abist_g6t_r_wb : in std_ulogic; + pc_mm_abist_g8t1p_renb_0 : in std_ulogic; + pc_mm_abist_g8t_bw_0 : in std_ulogic; + pc_mm_abist_g8t_bw_1 : in std_ulogic; + pc_mm_abist_g8t_dcomp : in std_ulogic_vector(0 to 3); + pc_mm_abist_g8t_wenb : in std_ulogic; + pc_mm_abist_raddr_0 : in std_ulogic_vector(0 to 9); + pc_mm_abist_waddr_0 : in std_ulogic_vector(0 to 9); + pc_mm_abist_wl128_comp_ena : in std_ulogic; + + pc_mm_abist_g8t_wenb_q : out std_ulogic; + pc_mm_abist_g8t1p_renb_0_q : out std_ulogic; + pc_mm_abist_di_0_q : out std_ulogic_vector(0 to 3); + pc_mm_abist_g8t_bw_1_q : out std_ulogic; + pc_mm_abist_g8t_bw_0_q : out std_ulogic; + pc_mm_abist_waddr_0_q : out std_ulogic_vector(0 to 9); + pc_mm_abist_raddr_0_q : out std_ulogic_vector(0 to 9); + pc_mm_abist_wl128_comp_ena_q : out std_ulogic; + pc_mm_abist_g8t_dcomp_q : out std_ulogic_vector(0 to 3); + pc_mm_abist_dcomp_g6t_2r_q : out std_ulogic_vector(0 to 3); + pc_mm_abist_di_g6t_2r_q : out std_ulogic_vector(0 to 3); + pc_mm_abist_g6t_r_wb_q : out std_ulogic; + + -- BOLT-ON pervasive for asic + pc_mm_bolt_sl_thold_3 : in std_ulogic; + pc_mm_bo_enable_3 : in std_ulogic; -- general bolt-on enable + pc_mm_bolt_sl_thold_0 : out std_ulogic; + pc_mm_bo_enable_2 : out std_ulogic; + + gptr_scan_in : in std_ulogic; + gptr_scan_out : out std_ulogic; + + time_scan_in : in std_ulogic; + time_scan_in_int : out std_ulogic; + time_scan_out_int : in std_ulogic; + time_scan_out : out std_ulogic; + + func_scan_in : in std_ulogic_vector(0 to 9); + func_scan_in_int : out std_ulogic_vector(0 to 9); + func_scan_out_int : in std_ulogic_vector(0 to 9); + func_scan_out : out std_ulogic_vector(0 to 9); + + repr_scan_in : in std_ulogic; + repr_scan_in_int : out std_ulogic; + repr_scan_out_int : in std_ulogic; + repr_scan_out : out std_ulogic; + + abst_scan_in : in std_ulogic_vector(0 to 1); + abst_scan_in_int : out std_ulogic_vector(0 to 1); + abst_scan_out_int : in std_ulogic_vector(0 to 1); + abst_scan_out : out std_ulogic_vector(0 to 1); + + bcfg_scan_in : in std_ulogic; -- config latches that are setup same on all cores + bcfg_scan_in_int : out std_ulogic; + bcfg_scan_out_int : in std_ulogic; + bcfg_scan_out : out std_ulogic; + + ccfg_scan_in : in std_ulogic; -- config latches that could be setup differently on multiple cores + ccfg_scan_in_int : out std_ulogic; + ccfg_scan_out_int : in std_ulogic; + ccfg_scan_out : out std_ulogic; + + dcfg_scan_in : in std_ulogic; + dcfg_scan_in_int : out std_ulogic; + dcfg_scan_out_int : in std_ulogic; + dcfg_scan_out : out std_ulogic + +); + + +-- synopsys translate_off + +-- synopsys translate_on + +end mmq_perv; +---- +architecture mmq_perv of mmq_perv is + +signal tidn : std_logic; +signal tiup : std_logic; + +signal pc_func_sl_thold_2_int : std_ulogic_vector(0 to 1); +signal pc_func_slp_sl_thold_2_int : std_ulogic_vector(0 to 1); +signal pc_sg_2_int : std_ulogic_vector(0 to 1); +signal pc_gptr_sl_thold_2_int : std_ulogic; +signal pc_fce_2_int : std_ulogic; +signal pc_time_sl_thold_2_int : std_ulogic; +signal pc_repr_sl_thold_2_int : std_ulogic; +signal pc_abst_sl_thold_2_int : std_ulogic; +signal pc_abst_slp_sl_thold_2_int : std_ulogic; +signal pc_cfg_sl_thold_2_int : std_ulogic; +signal pc_cfg_slp_sl_thold_2_int : std_ulogic; +signal pc_func_nsl_thold_2_int : std_ulogic; +signal pc_func_slp_nsl_thold_2_int : std_ulogic; +signal pc_ary_nsl_thold_2_int : std_ulogic; +signal pc_ary_slp_nsl_thold_2_int : std_ulogic; +signal pc_mm_bolt_sl_thold_2_int : std_ulogic; + +signal pc_func_sl_thold_1_int : std_ulogic_vector(0 to 1); +signal pc_func_slp_sl_thold_1_int : std_ulogic_vector(0 to 1); +signal pc_sg_1_int : std_ulogic_vector(0 to 1); +signal pc_gptr_sl_thold_1_int : std_ulogic; +signal pc_fce_1_int : std_ulogic; +signal pc_time_sl_thold_1_int : std_ulogic; +signal pc_repr_sl_thold_1_int : std_ulogic; +signal pc_abst_sl_thold_1_int : std_ulogic; +signal pc_abst_slp_sl_thold_1_int : std_ulogic; +signal pc_cfg_sl_thold_1_int : std_ulogic; +signal pc_cfg_slp_sl_thold_1_int : std_ulogic; +signal pc_func_nsl_thold_1_int : std_ulogic; +signal pc_func_slp_nsl_thold_1_int : std_ulogic; +signal pc_ary_nsl_thold_1_int : std_ulogic; +signal pc_ary_slp_nsl_thold_1_int : std_ulogic; +signal pc_mm_bolt_sl_thold_1_int : std_ulogic; + +signal pc_func_sl_thold_0_int : std_ulogic_vector(0 to 1); +signal pc_func_slp_sl_thold_0_int : std_ulogic_vector(0 to 1); +signal pc_sg_0_int : std_ulogic_vector(0 to 1); +signal pc_gptr_sl_thold_0_int : std_ulogic; +signal pc_fce_0_int : std_ulogic; +signal pc_time_sl_thold_0_int : std_ulogic; +signal pc_repr_sl_thold_0_int : std_ulogic; +signal pc_abst_sl_thold_0_int : std_ulogic; +signal pc_abst_slp_sl_thold_0_int : std_ulogic; +signal pc_cfg_sl_thold_0_int : std_ulogic; +signal pc_cfg_slp_sl_thold_0_int : std_ulogic; +signal pc_func_nsl_thold_0_int : std_ulogic; +signal pc_func_slp_nsl_thold_0_int : std_ulogic; +signal pc_ary_nsl_thold_0_int : std_ulogic; +signal pc_ary_slp_nsl_thold_0_int : std_ulogic; + +signal pc_func_sl_thold_0_b_int : std_ulogic_vector(0 to 1); +signal pc_func_slp_sl_thold_0_b_int : std_ulogic_vector(0 to 1); +signal pc_func_slp_sl_force_int : std_ulogic_vector(0 to 1); +signal pc_func_sl_force_int : std_ulogic_vector(0 to 1); + +signal abst_scan_in_q :std_ulogic_vector(0 to 1); +signal abst_scan_out_q :std_ulogic_vector(0 to 1); +signal time_scan_in_q :std_ulogic; +signal time_scan_out_q :std_ulogic; +signal repr_scan_in_q :std_ulogic; +signal repr_scan_out_q :std_ulogic; +signal gptr_scan_in_q :std_ulogic; +signal gptr_scan_out_int :std_ulogic; +signal gptr_scan_out_q :std_ulogic; +signal gptr_scan_lcbctrl :std_ulogic_vector(0 to 1); +signal bcfg_scan_in_q :std_ulogic; +signal bcfg_scan_out_q :std_ulogic; +signal ccfg_scan_in_q :std_ulogic; +signal ccfg_scan_out_q :std_ulogic; +signal dcfg_scan_in_q :std_ulogic; +signal dcfg_scan_out_q :std_ulogic; +signal func_scan_in_q :std_ulogic_vector(0 to 9); +signal func_scan_out_q :std_ulogic_vector(0 to 9); + +signal slat_force :std_ulogic_vector(0 to 1); +signal abst_slat_thold_b :std_ulogic; +signal abst_slat_d2clk :std_ulogic; +signal abst_slat_lclk :clk_logic; +signal time_slat_thold_b :std_ulogic; +signal time_slat_d2clk :std_ulogic; +signal time_slat_lclk :clk_logic; +signal repr_slat_thold_b :std_ulogic; +signal repr_slat_d2clk :std_ulogic; +signal repr_slat_lclk :clk_logic; +signal gptr_slat_thold_b :std_ulogic; +signal gptr_slat_d2clk :std_ulogic; +signal gptr_slat_lclk :clk_logic; +signal bcfg_slat_thold_b :std_ulogic; +signal bcfg_slat_d2clk :std_ulogic; +signal bcfg_slat_lclk :clk_logic; +signal ccfg_slat_thold_b :std_ulogic; +signal ccfg_slat_d2clk :std_ulogic; +signal ccfg_slat_lclk :clk_logic; +signal dcfg_slat_thold_b :std_ulogic; +signal dcfg_slat_d2clk :std_ulogic; +signal dcfg_slat_lclk :clk_logic; +signal func_slat_thold_b :std_ulogic; +signal func_slat_d2clk :std_ulogic; +signal func_slat_lclk :clk_logic; + +signal pc_abst_sl_thold_0_b : std_ulogic; +signal pc_abst_sl_force : std_ulogic; +signal lcb_delay_lclkr_dc_int : std_ulogic_vector(0 to 4); +signal lcb_d_mode_dc_int : std_ulogic; +signal lcb_mpw1_dc_b_int : std_ulogic_vector(0 to 4); +signal lcb_mpw2_dc_b_int : std_ulogic; +signal lcb_clkoff_dc_b_int : std_ulogic; + +signal abist_siv :std_ulogic_vector(0 to 41); +signal abist_sov :std_ulogic_vector(0 to 41); + +signal unused_dc : std_ulogic_vector(0 to 5); +-- synopsys translate_off +-- synopsys translate_on + +begin + +tidn <= '0'; +tiup <= '1'; + +perv_3to2_reg: tri_plat + generic map (width => 20, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0 to 1) => pc_mm_func_sl_thold_3(0 to 1), + din(2 to 3) => pc_mm_func_slp_sl_thold_3(0 to 1), + din(4 to 5) => pc_mm_sg_3(0 to 1), + din(6) => pc_mm_gptr_sl_thold_3, + din(7) => pc_mm_fce_3, + din(8) => pc_mm_time_sl_thold_3, + din(9) => pc_mm_repr_sl_thold_3, + din(10) => pc_mm_abst_sl_thold_3, + din(11) => pc_mm_abst_slp_sl_thold_3, + din(12) => pc_mm_cfg_sl_thold_3, + din(13) => pc_mm_cfg_slp_sl_thold_3, + din(14) => pc_mm_func_nsl_thold_3, + din(15) => pc_mm_func_slp_nsl_thold_3, + din(16) => pc_mm_ary_nsl_thold_3, + din(17) => pc_mm_ary_slp_nsl_thold_3, + din(18) => pc_mm_bolt_sl_thold_3, + din(19) => pc_mm_bo_enable_3, + q(0 to 1) => pc_func_sl_thold_2_int(0 to 1), + q(2 to 3) => pc_func_slp_sl_thold_2_int(0 to 1), + q(4 to 5) => pc_sg_2_int(0 to 1), + q(6) => pc_gptr_sl_thold_2_int, + q(7) => pc_fce_2_int, + q(8) => pc_time_sl_thold_2_int, + q(9) => pc_repr_sl_thold_2_int, + q(10) => pc_abst_sl_thold_2_int, + q(11) => pc_abst_slp_sl_thold_2_int, + q(12) => pc_cfg_sl_thold_2_int, + q(13) => pc_cfg_slp_sl_thold_2_int, + q(14) => pc_func_nsl_thold_2_int, + q(15) => pc_func_slp_nsl_thold_2_int, + q(16) => pc_ary_nsl_thold_2_int, + q(17) => pc_ary_slp_nsl_thold_2_int, + q(18) => pc_mm_bolt_sl_thold_2_int, + q(19) => pc_mm_bo_enable_2); + + +perv_2to1_reg: tri_plat + generic map (width => 19, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0 to 1) => pc_func_sl_thold_2_int(0 to 1), + din(2 to 3) => pc_func_slp_sl_thold_2_int(0 to 1), + din(4 to 5) => pc_sg_2_int(0 to 1), + din(6) => pc_gptr_sl_thold_2_int, + din(7) => pc_fce_2_int, + din(8) => pc_time_sl_thold_2_int, + din(9) => pc_repr_sl_thold_2_int, + din(10) => pc_abst_sl_thold_2_int, + din(11) => pc_abst_slp_sl_thold_2_int, + din(12) => pc_cfg_sl_thold_2_int, + din(13) => pc_cfg_slp_sl_thold_2_int, + din(14) => pc_func_nsl_thold_2_int, + din(15) => pc_func_slp_nsl_thold_2_int, + din(16) => pc_ary_nsl_thold_2_int, + din(17) => pc_ary_slp_nsl_thold_2_int, + din(18) => pc_mm_bolt_sl_thold_2_int, + q(0 to 1) => pc_func_sl_thold_1_int(0 to 1), + q(2 to 3) => pc_func_slp_sl_thold_1_int(0 to 1), + q(4 to 5) => pc_sg_1_int(0 to 1), + q(6) => pc_gptr_sl_thold_1_int, + q(7) => pc_fce_1_int, + q(8) => pc_time_sl_thold_1_int, + q(9) => pc_repr_sl_thold_1_int, + q(10) => pc_abst_sl_thold_1_int, + q(11) => pc_abst_slp_sl_thold_1_int, + q(12) => pc_cfg_sl_thold_1_int, + q(13) => pc_cfg_slp_sl_thold_1_int, + q(14) => pc_func_nsl_thold_1_int, + q(15) => pc_func_slp_nsl_thold_1_int, + q(16) => pc_ary_nsl_thold_1_int, + q(17) => pc_ary_slp_nsl_thold_1_int, + q(18) => pc_mm_bolt_sl_thold_1_int); + +perv_1to0_reg: tri_plat + generic map (width => 19, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ac_ccflush_dc, + din(0 to 1) => pc_func_sl_thold_1_int(0 to 1), + din(2 to 3) => pc_func_slp_sl_thold_1_int(0 to 1), + din(4 to 5) => pc_sg_1_int(0 to 1), + din(6) => pc_gptr_sl_thold_1_int, + din(7) => pc_fce_1_int, + din(8) => pc_time_sl_thold_1_int, + din(9) => pc_repr_sl_thold_1_int, + din(10) => pc_abst_sl_thold_1_int, + din(11) => pc_abst_slp_sl_thold_1_int, + din(12) => pc_cfg_sl_thold_1_int, + din(13) => pc_cfg_slp_sl_thold_1_int, + din(14) => pc_func_nsl_thold_1_int, + din(15) => pc_func_slp_nsl_thold_1_int, + din(16) => pc_ary_nsl_thold_1_int, + din(17) => pc_ary_slp_nsl_thold_1_int, + din(18) => pc_mm_bolt_sl_thold_1_int, + q(0 to 1) => pc_func_sl_thold_0_int(0 to 1), + q(2 to 3) => pc_func_slp_sl_thold_0_int(0 to 1), + q(4 to 5) => pc_sg_0_int(0 to 1), + q(6) => pc_gptr_sl_thold_0_int, + q(7) => pc_fce_0_int, + q(8) => pc_time_sl_thold_0_int, + q(9) => pc_repr_sl_thold_0_int, + q(10) => pc_abst_sl_thold_0_int, + q(11) => pc_abst_slp_sl_thold_0_int, + q(12) => pc_cfg_sl_thold_0_int, + q(13) => pc_cfg_slp_sl_thold_0_int, + q(14) => pc_func_nsl_thold_0_int, + q(15) => pc_func_slp_nsl_thold_0_int, + q(16) => pc_ary_nsl_thold_0_int, + q(17) => pc_ary_slp_nsl_thold_0_int, + q(18) => pc_mm_bolt_sl_thold_0); + + +pc_time_sl_thold_0 <= pc_time_sl_thold_0_int; +pc_abst_sl_thold_0 <= pc_abst_sl_thold_0_int; +pc_abst_slp_sl_thold_0 <= pc_abst_slp_sl_thold_0_int; +pc_repr_sl_thold_0 <= pc_repr_sl_thold_0_int; +pc_ary_nsl_thold_0 <= pc_ary_nsl_thold_0_int; +pc_ary_slp_nsl_thold_0 <= pc_ary_slp_nsl_thold_0_int; + +pc_func_sl_thold_0 <= pc_func_sl_thold_0_int; +pc_func_sl_thold_0_b <= pc_func_sl_thold_0_b_int; +pc_func_slp_sl_thold_0 <= pc_func_slp_sl_thold_0_int; +pc_func_slp_sl_thold_0_b <= pc_func_slp_sl_thold_0_b_int; + +pc_sg_0 <= pc_sg_0_int; +pc_sg_1 <= pc_sg_1_int; +pc_sg_2 <= pc_sg_2_int; + +pc_func_sl_thold_2 <= pc_func_sl_thold_2_int; +pc_func_slp_sl_thold_2 <= pc_func_slp_sl_thold_2_int; +pc_func_slp_nsl_thold_2 <= pc_func_slp_nsl_thold_2_int; +pc_cfg_sl_thold_2 <= pc_cfg_sl_thold_2_int; +pc_cfg_slp_sl_thold_2 <= pc_cfg_slp_sl_thold_2_int; +pc_fce_2 <= pc_fce_2_int; + + +lcb_clkoff_dc_b <= lcb_clkoff_dc_b_int; +lcb_d_mode_dc <= lcb_d_mode_dc_int; +lcb_delay_lclkr_dc <= lcb_delay_lclkr_dc_int; +lcb_mpw1_dc_b <= lcb_mpw1_dc_b_int; +lcb_mpw2_dc_b <= lcb_mpw2_dc_b_int; + + + + +perv_lcbctrl: tri_lcbcntl_mac + generic map (expand_type => expand_type) + port map ( + vdd => vdd, + gnd => gnd, + sg => pc_sg_0_int(0), + nclk => nclk, + scan_in => gptr_scan_in_q, + scan_diag_dc => tc_scan_diag_dc, + thold => pc_gptr_sl_thold_0_int, + clkoff_dc_b => lcb_clkoff_dc_b_int, + delay_lclkr_dc => lcb_delay_lclkr_dc_int(0 to 4), + act_dis_dc => open, + d_mode_dc => lcb_d_mode_dc_int, + mpw1_dc_b => lcb_mpw1_dc_b_int(0 to 4), + mpw2_dc_b => lcb_mpw2_dc_b_int, + scan_out => gptr_scan_lcbctrl(0)); + +perv_g6t_gptr_lcbctrl: tri_lcbcntl_array_mac + generic map (expand_type => expand_type) + port map ( + vdd => vdd, + gnd => gnd, + sg => pc_sg_0_int(1), + nclk => nclk, + scan_in => gptr_scan_lcbctrl(0), + scan_diag_dc => tc_scan_diag_dc, + thold => pc_gptr_sl_thold_0_int, + clkoff_dc_b => g6t_gptr_lcb_clkoff_dc_b, + delay_lclkr_dc => g6t_gptr_lcb_delay_lclkr_dc(0 to 4), + act_dis_dc => open, + d_mode_dc => g6t_gptr_lcb_d_mode_dc, + mpw1_dc_b => g6t_gptr_lcb_mpw1_dc_b(0 to 4), + mpw2_dc_b => g6t_gptr_lcb_mpw2_dc_b, + scan_out => gptr_scan_lcbctrl(1)); + +perv_g8t_gptr_lcbctrl: tri_lcbcntl_array_mac + generic map (expand_type => expand_type) + port map ( + vdd => vdd, + gnd => gnd, + sg => pc_sg_0_int(1), + nclk => nclk, + scan_in => gptr_scan_lcbctrl(1), + scan_diag_dc => tc_scan_diag_dc, + thold => pc_gptr_sl_thold_0_int, + clkoff_dc_b => g8t_gptr_lcb_clkoff_dc_b, + delay_lclkr_dc => g8t_gptr_lcb_delay_lclkr_dc(0 to 4), + act_dis_dc => open, + d_mode_dc => g8t_gptr_lcb_d_mode_dc, + mpw1_dc_b => g8t_gptr_lcb_mpw1_dc_b(0 to 4), + mpw2_dc_b => g8t_gptr_lcb_mpw2_dc_b, + scan_out => gptr_scan_out_int); + +--never disable act pins, they are used functionally +lcb_act_dis_dc <= '0'; +g8t_gptr_lcb_act_dis_dc <= '0'; +g6t_gptr_lcb_act_dis_dc <= '0'; + +time_scan_in_int <= time_scan_in_q; +repr_scan_in_int <= repr_scan_in_q; +func_scan_in_int <= func_scan_in_q; +bcfg_scan_in_int <= bcfg_scan_in_q; +ccfg_scan_in_int <= ccfg_scan_in_q; +dcfg_scan_in_int <= dcfg_scan_in_q; + +time_scan_out <= time_scan_out_q and tc_ac_scan_dis_dc_b; +gptr_scan_out <= gptr_scan_out_q and tc_ac_scan_dis_dc_b; +repr_scan_out <= repr_scan_out_q and tc_ac_scan_dis_dc_b; +func_scan_out <= func_scan_out_q and (0 to 9 => tc_ac_scan_dis_dc_b); +abst_scan_out <= abst_scan_out_q and (0 to 1 => tc_ac_scan_dis_dc_b); +bcfg_scan_out <= bcfg_scan_out_q and tc_ac_scan_dis_dc_b; +ccfg_scan_out <= ccfg_scan_out_q and tc_ac_scan_dis_dc_b; +dcfg_scan_out <= dcfg_scan_out_q and tc_ac_scan_dis_dc_b; + +-- LCBs for scan only staging latches +slat_force <= pc_sg_0_int; +abst_slat_thold_b <= NOT pc_abst_sl_thold_0_int; +time_slat_thold_b <= NOT pc_time_sl_thold_0_int; +repr_slat_thold_b <= NOT pc_repr_sl_thold_0_int; +gptr_slat_thold_b <= NOT pc_gptr_sl_thold_0_int; +bcfg_slat_thold_b <= NOT pc_cfg_sl_thold_0_int; +ccfg_slat_thold_b <= NOT pc_cfg_sl_thold_0_int; +dcfg_slat_thold_b <= NOT pc_cfg_sl_thold_0_int; +func_slat_thold_b <= NOT pc_func_sl_thold_0_int(0); + +perv_lcbs_abst: tri_lcbs + generic map (expand_type => expand_type ) + port map ( + vd => vdd, + gd => gnd, + delay_lclkr => lcb_delay_lclkr_dc_int(0), + nclk => nclk, + forcee => slat_force(1), + thold_b => abst_slat_thold_b, + dclk => abst_slat_d2clk, + lclk => abst_slat_lclk ); + +perv_abst_stg: tri_slat_scan + generic map (width => 4, init => "0000", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => abst_slat_d2clk, + lclk => abst_slat_lclk, + scan_in(0 to 1) => abst_scan_in, + scan_in(2 to 3) => abst_scan_out_int, + scan_out(0 to 1) => abst_scan_in_q, + scan_out(2 to 3) => abst_scan_out_q ); + +perv_lcbs_time: tri_lcbs + generic map (expand_type => expand_type ) + port map ( + vd => vdd, + gd => gnd, + delay_lclkr => lcb_delay_lclkr_dc_int(0), + nclk => nclk, + forcee => slat_force(1), + thold_b => time_slat_thold_b, + dclk => time_slat_d2clk, + lclk => time_slat_lclk ); + +perv_time_stg: tri_slat_scan + generic map (width => 2, init => "00", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => time_slat_d2clk, + lclk => time_slat_lclk, + scan_in(0) => time_scan_in, + scan_in(1) => time_scan_out_int, + scan_out(0) => time_scan_in_q, + scan_out(1) => time_scan_out_q ); + +perv_lcbs_repr: tri_lcbs + generic map (expand_type => expand_type ) + port map ( + vd => vdd, + gd => gnd, + delay_lclkr => lcb_delay_lclkr_dc_int(0), + nclk => nclk, + forcee => slat_force(1), + thold_b => repr_slat_thold_b, + dclk => repr_slat_d2clk, + lclk => repr_slat_lclk ); + +perv_repr_stg: tri_slat_scan + generic map (width => 2, init => "00", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => repr_slat_d2clk, + lclk => repr_slat_lclk, + scan_in(0) => repr_scan_in, + scan_in(1) => repr_scan_out_int, + scan_out(0) => repr_scan_in_q, + scan_out(1) => repr_scan_out_q ); + +perv_lcbs_gptr: tri_lcbs + generic map (expand_type => expand_type ) + port map ( + vd => vdd, + gd => gnd, + delay_lclkr => tiup, + nclk => nclk, + forcee => slat_force(0), + thold_b => gptr_slat_thold_b, + dclk => gptr_slat_d2clk, + lclk => gptr_slat_lclk ); + +perv_gptr_stg: tri_slat_scan + generic map (width => 2, init => "00", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => gptr_slat_d2clk, + lclk => gptr_slat_lclk, + scan_in(0) => gptr_scan_in, + scan_in(1) => gptr_scan_out_int, + scan_out(0) => gptr_scan_in_q, + scan_out(1) => gptr_scan_out_q ); + +perv_lcbs_bcfg: tri_lcbs + generic map (expand_type => expand_type ) + port map ( + vd => vdd, + gd => gnd, + delay_lclkr => lcb_delay_lclkr_dc_int(0), + nclk => nclk, + forcee => slat_force(0), + thold_b => bcfg_slat_thold_b, + dclk => bcfg_slat_d2clk, + lclk => bcfg_slat_lclk ); + +perv_bcfg_stg: tri_slat_scan + generic map (width => 2, init => "00", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => bcfg_slat_d2clk, + lclk => bcfg_slat_lclk, + scan_in(0) => bcfg_scan_in, + scan_in(1) => bcfg_scan_out_int, + scan_out(0) => bcfg_scan_in_q, + scan_out(1) => bcfg_scan_out_q ); + +perv_lcbs_ccfg: tri_lcbs + generic map (expand_type => expand_type ) + port map ( + vd => vdd, + gd => gnd, + delay_lclkr => lcb_delay_lclkr_dc_int(0), + nclk => nclk, + forcee => slat_force(0), + thold_b => ccfg_slat_thold_b, + dclk => ccfg_slat_d2clk, + lclk => ccfg_slat_lclk ); + +perv_ccfg_stg: tri_slat_scan + generic map (width => 2, init => "00", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => ccfg_slat_d2clk, + lclk => ccfg_slat_lclk, + scan_in(0) => ccfg_scan_in, + scan_in(1) => ccfg_scan_out_int, + scan_out(0) => ccfg_scan_in_q, + scan_out(1) => ccfg_scan_out_q ); + +perv_lcbs_dcfg: tri_lcbs + generic map (expand_type => expand_type ) + port map ( + vd => vdd, + gd => gnd, + delay_lclkr => lcb_delay_lclkr_dc_int(0), + nclk => nclk, + forcee => slat_force(0), + thold_b => dcfg_slat_thold_b, + dclk => dcfg_slat_d2clk, + lclk => dcfg_slat_lclk ); + +perv_dcfg_stg: tri_slat_scan + generic map (width => 2, init => "00", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => dcfg_slat_d2clk, + lclk => dcfg_slat_lclk, + scan_in(0) => dcfg_scan_in, + scan_in(1) => dcfg_scan_out_int, + scan_out(0) => dcfg_scan_in_q, + scan_out(1) => dcfg_scan_out_q ); + +perv_lcbs_func: tri_lcbs + generic map (expand_type => expand_type ) + port map ( + vd => vdd, + gd => gnd, + delay_lclkr => lcb_delay_lclkr_dc_int(0), + nclk => nclk, + forcee => slat_force(0), + thold_b => func_slat_thold_b, + dclk => func_slat_d2clk, + lclk => func_slat_lclk ); + +perv_func_stg: tri_slat_scan + generic map (width => 20, init => "00000000000000000000", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => func_slat_d2clk, + lclk => func_slat_lclk, + scan_in(0 to 9) => func_scan_in, + scan_in(10 to 19) => func_scan_out_int, + scan_out(0 to 9) => func_scan_in_q, + scan_out(10 to 19) => func_scan_out_q ); + + +perv_lcbor_func_sl_0: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b_int, + thold => pc_func_sl_thold_0_int(0), + sg => pc_sg_0_int(0), + act_dis => tidn, + forcee => pc_func_sl_force_int(0), + thold_b => pc_func_sl_thold_0_b_int(0)); + +perv_lcbor_func_sl_1: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b_int, + thold => pc_func_sl_thold_0_int(1), + sg => pc_sg_0_int(1), + act_dis => tidn, + forcee => pc_func_sl_force_int(1), + thold_b => pc_func_sl_thold_0_b_int(1)); + +perv_lcbor_func_slp_sl_0: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b_int, + thold => pc_func_slp_sl_thold_0_int(0), + sg => pc_sg_0_int(0), + act_dis => tidn, + forcee => pc_func_slp_sl_force_int(0), + thold_b => pc_func_slp_sl_thold_0_b_int(0)); + +perv_lcbor_func_slp_sl_1: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b_int, + thold => pc_func_slp_sl_thold_0_int(1), + sg => pc_sg_0_int(1), + act_dis => tidn, + forcee => pc_func_slp_sl_force_int(1), + thold_b => pc_func_slp_sl_thold_0_b_int(1)); + +perv_lcbor_abst_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b_int, + thold => pc_abst_sl_thold_0_int, + sg => pc_sg_0_int(1), + act_dis => tidn, + forcee => pc_abst_sl_force, + thold_b => pc_abst_sl_thold_0_b); + + + +----------------------------------------------------------------------- +-- abist latches +----------------------------------------------------------------------- + +abist_reg: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 42, needs_sreset => 0) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => pc_mm_abist_ena_dc, + thold_b => pc_abst_sl_thold_0_b, + sg => pc_sg_0_int(1), + forcee => pc_abst_sl_force, + delay_lclkr => lcb_delay_lclkr_dc_int(0), + mpw1_b => lcb_mpw1_dc_b_int(0), + mpw2_b => lcb_mpw2_dc_b_int, + d_mode => lcb_d_mode_dc_int, + scin => abist_siv(0 to 41), + scout => abist_sov(0 to 41), + din (0) => pc_mm_abist_g8t_wenb, + din (1) => pc_mm_abist_g8t1p_renb_0, + din (2 to 5) => pc_mm_abist_di_0, + din (6) => pc_mm_abist_g8t_bw_1, + din (7) => pc_mm_abist_g8t_bw_0, + din (8 to 17) => pc_mm_abist_waddr_0, + din (18 to 27) => pc_mm_abist_raddr_0, + din (28) => pc_mm_abist_wl128_comp_ena, + din (29 to 32) => pc_mm_abist_g8t_dcomp, + din (33 to 36) => pc_mm_abist_dcomp_g6t_2r, + din (37 to 40) => pc_mm_abist_di_g6t_2r, + din (41) => pc_mm_abist_g6t_r_wb, + dout(0) => pc_mm_abist_g8t_wenb_q, + dout(1) => pc_mm_abist_g8t1p_renb_0_q, + dout(2 to 5) => pc_mm_abist_di_0_q, + dout(6) => pc_mm_abist_g8t_bw_1_q, + dout(7) => pc_mm_abist_g8t_bw_0_q, + dout(8 to 17) => pc_mm_abist_waddr_0_q, + dout(18 to 27) => pc_mm_abist_raddr_0_q, + dout(28) => pc_mm_abist_wl128_comp_ena_q, + dout(29 to 32) => pc_mm_abist_g8t_dcomp_q, + dout(33 to 36) => pc_mm_abist_dcomp_g6t_2r_q, + dout(37 to 40) => pc_mm_abist_di_g6t_2r_q, + dout(41) => pc_mm_abist_g6t_r_wb_q); + +abist_siv <= abist_sov(1 to abist_sov'right) & abst_scan_in_q(0); +abst_scan_in_int(0) <= abist_sov(0); +abst_scan_in_int(1) <= abst_scan_in_q(1); + +-- unused spare signal assignments +unused_dc(0) <= PC_FCE_0_INT; +unused_dc(1) <= PC_CFG_SLP_SL_THOLD_0_INT; +unused_dc(2) <= PC_FUNC_NSL_THOLD_0_INT; +unused_dc(3) <= PC_FUNC_SLP_NSL_THOLD_0_INT; +unused_dc(4) <= or_reduce(PC_FUNC_SL_FORCE_INT); +unused_dc(5) <= or_reduce(PC_FUNC_SLP_SL_FORCE_INT); + + +end mmq_perv; diff --git a/rel/src/vhdl/work/mmq_spr.vhdl b/rel/src/vhdl/work/mmq_spr.vhdl new file mode 100644 index 0000000..5fd0804 --- /dev/null +++ b/rel/src/vhdl/work/mmq_spr.vhdl @@ -0,0 +1,6981 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +--******************************************************************** +--* TITLE: Memory Management Unit Special Purpose Registers +--* NAME: mmq_spr.vhdl +--********************************************************************* + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library ibm; +use ibm.std_ulogic_unsigned.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_support.all; +library support; +use support.power_logic_pkg.all; + +library tri; +use tri.tri_latches_pkg.all; +entity mmq_spr is + generic(pid_width : integer := 14; + lpid_width : integer := 8; + epn_width : integer := 52; + thdid_width : integer := 4; + class_width : integer := 2; + extclass_width : integer := 2; + mmucr0_width : integer := 20; + mmucr1_width : integer := 32; + mmucr2_width : integer := 32; + mmucr3_width : integer := 15; + spr_ctl_width : integer := 3; + spr_etid_width : integer := 2; + spr_addr_width : integer := 10; + spr_data_width : integer := 64; + real_addr_width : integer := 42; + bcfg_mmucr1_value : integer := 201326592; + bcfg_mmucr2_value : integer := 685361; + bcfg_mmucr3_value : integer := 15; + bcfg_mmucfg_value : integer := 3; + bcfg_tlb0cfg_value : integer := 7; + mmq_spr_cswitch_0to3 : integer := 0; + expand_tlb_type : integer := 2; + expand_type : integer := 2 ); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + + + tc_ccflush_dc : in std_ulogic; + tc_scan_dis_dc_b : in std_ulogic; + tc_scan_diag_dc : in std_ulogic; + tc_lbist_en_dc : in std_ulogic; + + lcb_d_mode_dc : in std_ulogic; + lcb_clkoff_dc_b : in std_ulogic; + lcb_act_dis_dc : in std_ulogic; + lcb_mpw1_dc_b : in std_ulogic_vector(0 to 4); + lcb_mpw2_dc_b : in std_ulogic; + lcb_delay_lclkr_dc : in std_ulogic_vector(0 to 4); + + ac_func_scan_in :in std_ulogic_vector(0 to 1); + ac_func_scan_out :out std_ulogic_vector(0 to 1); + ac_bcfg_scan_in :in std_ulogic; + ac_bcfg_scan_out :out std_ulogic; + + pc_sg_2 : in std_ulogic; + pc_func_sl_thold_2 : in std_ulogic; + pc_func_slp_sl_thold_2 : in std_ulogic; + pc_func_slp_nsl_thold_2 : in std_ulogic; + pc_cfg_sl_thold_2 : in std_ulogic; + pc_cfg_slp_sl_thold_2 : in std_ulogic; + pc_fce_2 : in std_ulogic; + xu_mm_ccr2_notlb_b : in std_ulogic; + mmucr2_act_override : in std_ulogic_vector(5 to 6); + tlb_delayed_act : in std_ulogic_vector(29 to 32); + + mm_iu_ierat_pid0 : out std_ulogic_vector(0 to pid_width-1); + mm_iu_ierat_pid1 : out std_ulogic_vector(0 to pid_width-1); + mm_iu_ierat_pid2 : out std_ulogic_vector(0 to pid_width-1); + mm_iu_ierat_pid3 : out std_ulogic_vector(0 to pid_width-1); + mm_iu_ierat_mmucr0_0 : out std_ulogic_vector(0 to 19); + mm_iu_ierat_mmucr0_1 : out std_ulogic_vector(0 to 19); + mm_iu_ierat_mmucr0_2 : out std_ulogic_vector(0 to 19); + mm_iu_ierat_mmucr0_3 : out std_ulogic_vector(0 to 19); + iu_mm_ierat_mmucr0 : in std_ulogic_vector(0 to 17); + iu_mm_ierat_mmucr0_we : in std_ulogic_vector(0 to thdid_width-1); + mm_iu_ierat_mmucr1 : out std_ulogic_vector(0 to 8); + iu_mm_ierat_mmucr1 : in std_ulogic_vector(0 to 3); + iu_mm_ierat_mmucr1_we : in std_ulogic; + + mm_xu_derat_pid0 : out std_ulogic_vector(0 to pid_width-1); + mm_xu_derat_pid1 : out std_ulogic_vector(0 to pid_width-1); + mm_xu_derat_pid2 : out std_ulogic_vector(0 to pid_width-1); + mm_xu_derat_pid3 : out std_ulogic_vector(0 to pid_width-1); + mm_xu_derat_mmucr0_0 : out std_ulogic_vector(0 to 19); + mm_xu_derat_mmucr0_1 : out std_ulogic_vector(0 to 19); + mm_xu_derat_mmucr0_2 : out std_ulogic_vector(0 to 19); + mm_xu_derat_mmucr0_3 : out std_ulogic_vector(0 to 19); + xu_mm_derat_mmucr0 : in std_ulogic_vector(0 to 17); + xu_mm_derat_mmucr0_we : in std_ulogic_vector(0 to thdid_width-1); + mm_xu_derat_mmucr1 : out std_ulogic_vector(0 to 9); + xu_mm_derat_mmucr1 : in std_ulogic_vector(0 to 4); + xu_mm_derat_mmucr1_we : in std_ulogic; + + pid0 : out std_ulogic_vector(0 to pid_width-1); + pid1 : out std_ulogic_vector(0 to pid_width-1); + pid2 : out std_ulogic_vector(0 to pid_width-1); + pid3 : out std_ulogic_vector(0 to pid_width-1); + mmucr0_0 : out std_ulogic_vector(0 to mmucr0_width-1); + mmucr0_1 : out std_ulogic_vector(0 to mmucr0_width-1); + mmucr0_2 : out std_ulogic_vector(0 to mmucr0_width-1); + mmucr0_3 : out std_ulogic_vector(0 to mmucr0_width-1); + mmucr1 : out std_ulogic_vector(0 to mmucr1_width-1); + mmucr2 : out std_ulogic_vector(0 to mmucr2_width-1); + mmucr3_0 : out std_ulogic_vector(64-mmucr3_width to 63); + mmucr3_1 : out std_ulogic_vector(64-mmucr3_width to 63); + mmucr3_2 : out std_ulogic_vector(64-mmucr3_width to 63); + mmucr3_3 : out std_ulogic_vector(64-mmucr3_width to 63); + mmucfg_lrat : out std_ulogic; + mmucfg_twc : out std_ulogic; + tlb0cfg_pt : out std_ulogic; + tlb0cfg_ind : out std_ulogic; + tlb0cfg_gtwe : out std_ulogic; + + mas0_0_atsel : out std_ulogic; + mas0_0_esel : out std_ulogic_vector(0 to 2); + mas0_0_hes : out std_ulogic; + mas0_0_wq : out std_ulogic_vector(0 to 1); + mas1_0_v : out std_ulogic; + mas1_0_iprot : out std_ulogic; + mas1_0_tid : out std_ulogic_vector(0 to 13); + mas1_0_ind : out std_ulogic; + mas1_0_ts : out std_ulogic; + mas1_0_tsize : out std_ulogic_vector(0 to 3); + mas2_0_epn : out std_ulogic_vector(0 to 51); + mas2_0_wimge : out std_ulogic_vector(0 to 4); + mas3_0_rpnl : out std_ulogic_vector(32 to 52); + mas3_0_ubits : out std_ulogic_vector(0 to 3); + mas3_0_usxwr : out std_ulogic_vector(0 to 5); + mas5_0_sgs : out std_ulogic; + mas5_0_slpid : out std_ulogic_vector(0 to 7); + mas6_0_spid : out std_ulogic_vector(0 to 13); + mas6_0_isize : out std_ulogic_vector(0 to 3); + mas6_0_sind : out std_ulogic; + mas6_0_sas : out std_ulogic; + mas7_0_rpnu : out std_ulogic_vector(22 to 31); + mas8_0_tgs : out std_ulogic; + mas8_0_vf : out std_ulogic; + mas8_0_tlpid : out std_ulogic_vector(0 to 7); + mas0_1_atsel : out std_ulogic; + mas0_1_esel : out std_ulogic_vector(0 to 2); + mas0_1_hes : out std_ulogic; + mas0_1_wq : out std_ulogic_vector(0 to 1); + mas1_1_v : out std_ulogic; + mas1_1_iprot : out std_ulogic; + mas1_1_tid : out std_ulogic_vector(0 to 13); + mas1_1_ind : out std_ulogic; + mas1_1_ts : out std_ulogic; + mas1_1_tsize : out std_ulogic_vector(0 to 3); + mas2_1_epn : out std_ulogic_vector(0 to 51); + mas2_1_wimge : out std_ulogic_vector(0 to 4); + mas3_1_rpnl : out std_ulogic_vector(32 to 52); + mas3_1_ubits : out std_ulogic_vector(0 to 3); + mas3_1_usxwr : out std_ulogic_vector(0 to 5); + mas5_1_sgs : out std_ulogic; + mas5_1_slpid : out std_ulogic_vector(0 to 7); + mas6_1_spid : out std_ulogic_vector(0 to 13); + mas6_1_isize : out std_ulogic_vector(0 to 3); + mas6_1_sind : out std_ulogic; + mas6_1_sas : out std_ulogic; + mas7_1_rpnu : out std_ulogic_vector(22 to 31); + mas8_1_tgs : out std_ulogic; + mas8_1_vf : out std_ulogic; + mas8_1_tlpid : out std_ulogic_vector(0 to 7); + mas0_2_atsel : out std_ulogic; + mas0_2_esel : out std_ulogic_vector(0 to 2); + mas0_2_hes : out std_ulogic; + mas0_2_wq : out std_ulogic_vector(0 to 1); + mas1_2_v : out std_ulogic; + mas1_2_iprot : out std_ulogic; + mas1_2_tid : out std_ulogic_vector(0 to 13); + mas1_2_ind : out std_ulogic; + mas1_2_ts : out std_ulogic; + mas1_2_tsize : out std_ulogic_vector(0 to 3); + mas2_2_epn : out std_ulogic_vector(0 to 51); + mas2_2_wimge : out std_ulogic_vector(0 to 4); + mas3_2_rpnl : out std_ulogic_vector(32 to 52); + mas3_2_ubits : out std_ulogic_vector(0 to 3); + mas3_2_usxwr : out std_ulogic_vector(0 to 5); + mas5_2_sgs : out std_ulogic; + mas5_2_slpid : out std_ulogic_vector(0 to 7); + mas6_2_spid : out std_ulogic_vector(0 to 13); + mas6_2_isize : out std_ulogic_vector(0 to 3); + mas6_2_sind : out std_ulogic; + mas6_2_sas : out std_ulogic; + mas7_2_rpnu : out std_ulogic_vector(22 to 31); + mas8_2_tgs : out std_ulogic; + mas8_2_vf : out std_ulogic; + mas8_2_tlpid : out std_ulogic_vector(0 to 7); + mas0_3_atsel : out std_ulogic; + mas0_3_esel : out std_ulogic_vector(0 to 2); + mas0_3_hes : out std_ulogic; + mas0_3_wq : out std_ulogic_vector(0 to 1); + mas1_3_v : out std_ulogic; + mas1_3_iprot : out std_ulogic; + mas1_3_tid : out std_ulogic_vector(0 to 13); + mas1_3_ind : out std_ulogic; + mas1_3_ts : out std_ulogic; + mas1_3_tsize : out std_ulogic_vector(0 to 3); + mas2_3_epn : out std_ulogic_vector(0 to 51); + mas2_3_wimge : out std_ulogic_vector(0 to 4); + mas3_3_rpnl : out std_ulogic_vector(32 to 52); + mas3_3_ubits : out std_ulogic_vector(0 to 3); + mas3_3_usxwr : out std_ulogic_vector(0 to 5); + mas5_3_sgs : out std_ulogic; + mas5_3_slpid : out std_ulogic_vector(0 to 7); + mas6_3_spid : out std_ulogic_vector(0 to 13); + mas6_3_isize : out std_ulogic_vector(0 to 3); + mas6_3_sind : out std_ulogic; + mas6_3_sas : out std_ulogic; + mas7_3_rpnu : out std_ulogic_vector(22 to 31); + mas8_3_tgs : out std_ulogic; + mas8_3_vf : out std_ulogic; + mas8_3_tlpid : out std_ulogic_vector(0 to 7); + tlb_mas0_esel : in std_ulogic_vector(0 to 2); + tlb_mas1_v : in std_ulogic; + tlb_mas1_iprot : in std_ulogic; + tlb_mas1_tid : in std_ulogic_vector(0 to pid_width-1); + tlb_mas1_tid_error : in std_ulogic_vector(0 to pid_width-1); + tlb_mas1_ind : in std_ulogic; + tlb_mas1_ts : in std_ulogic; + tlb_mas1_ts_error : in std_ulogic; + tlb_mas1_tsize : in std_ulogic_vector(0 to 3); + tlb_mas2_epn : in std_ulogic_vector(0 to epn_width-1); + tlb_mas2_epn_error : in std_ulogic_vector(0 to epn_width-1); + tlb_mas2_wimge : in std_ulogic_vector(0 to 4); + tlb_mas3_rpnl : in std_ulogic_vector(32 to 51); + tlb_mas3_ubits : in std_ulogic_vector(0 to 3); + tlb_mas3_usxwr : in std_ulogic_vector(0 to 5); + tlb_mas6_spid : in std_ulogic_vector(0 to pid_width-1); + tlb_mas6_isize : in std_ulogic_vector(0 to 3); + tlb_mas6_sind : in std_ulogic; + tlb_mas6_sas : in std_ulogic; + tlb_mas7_rpnu : in std_ulogic_vector(22 to 31); + tlb_mas8_tgs : in std_ulogic; + tlb_mas8_vf : in std_ulogic; + tlb_mas8_tlpid : in std_ulogic_vector(0 to 7); + + tlb_mmucr1_een : in std_ulogic_vector(0 to 8); + tlb_mmucr1_we : in std_ulogic; + tlb_mmucr3_thdid : in std_ulogic_vector(0 to thdid_width-1); + tlb_mmucr3_resvattr : in std_ulogic; + tlb_mmucr3_wlc : in std_ulogic_vector(0 to 1); + tlb_mmucr3_class : in std_ulogic_vector(0 to class_width-1); + tlb_mmucr3_extclass : in std_ulogic_vector(0 to extclass_width-1); + tlb_mmucr3_rc : in std_ulogic_vector(0 to 1); + tlb_mmucr3_x : in std_ulogic; + tlb_mas_tlbre : in std_ulogic; + tlb_mas_tlbsx_hit : in std_ulogic; + tlb_mas_tlbsx_miss : in std_ulogic; + tlb_mas_dtlb_error : in std_ulogic; + tlb_mas_itlb_error : in std_ulogic; + tlb_mas_thdid : in std_ulogic_vector(0 to thdid_width-1); + + mmucsr0_tlb0fi : out std_ulogic; + mmq_inval_tlb0fi_done : in std_ulogic; + + lrat_mmucr3_x : in std_ulogic; + lrat_mas0_esel : in std_ulogic_vector(0 to 2); + lrat_mas1_v : in std_ulogic; + lrat_mas1_tsize : in std_ulogic_vector(0 to 3); + lrat_mas2_epn : in std_ulogic_vector(0 to 51); + lrat_mas3_rpnl : in std_ulogic_vector(32 to 51); + lrat_mas7_rpnu : in std_ulogic_vector(22 to 31); + lrat_mas8_tlpid : in std_ulogic_vector(0 to lpid_width-1); + lrat_mas_tlbre : in std_ulogic; + lrat_mas_tlbsx_hit : in std_ulogic; + lrat_mas_tlbsx_miss : in std_ulogic; + lrat_mas_thdid : in std_ulogic_vector(0 to thdid_width-1); + lrat_tag4_hit_entry : in std_ulogic_vector(0 to 2); + + tlb_lper_lpn : in std_ulogic_vector(64-real_addr_width to 51); + tlb_lper_lps : in std_ulogic_vector(60 to 63); + tlb_lper_we : in std_ulogic_vector(0 to thdid_width-1); + + lpidr : out std_ulogic_vector(0 to lpid_width-1); + ac_an_lpar_id : out std_ulogic_vector(0 to lpid_width-1); + + spr_dbg_match_64b : out std_ulogic; + spr_dbg_match_any_mmu : out std_ulogic; + spr_dbg_match_any_mas : out std_ulogic; + spr_dbg_match_pid : out std_ulogic; + spr_dbg_match_lpidr : out std_ulogic; + spr_dbg_match_mmucr0 : out std_ulogic; + spr_dbg_match_mmucr1 : out std_ulogic; + spr_dbg_match_mmucr2 : out std_ulogic; + spr_dbg_match_mmucr3 : out std_ulogic; + + spr_dbg_match_mmucsr0 : out std_ulogic; + spr_dbg_match_mmucfg : out std_ulogic; + spr_dbg_match_tlb0cfg : out std_ulogic; + spr_dbg_match_tlb0ps : out std_ulogic; + spr_dbg_match_lratcfg : out std_ulogic; + spr_dbg_match_lratps : out std_ulogic; + spr_dbg_match_eptcfg : out std_ulogic; + spr_dbg_match_lper : out std_ulogic; + spr_dbg_match_lperu : out std_ulogic; + + spr_dbg_match_mas0 : out std_ulogic; + spr_dbg_match_mas1 : out std_ulogic; + spr_dbg_match_mas2 : out std_ulogic; + spr_dbg_match_mas2u : out std_ulogic; + spr_dbg_match_mas3 : out std_ulogic; + spr_dbg_match_mas4 : out std_ulogic; + spr_dbg_match_mas5 : out std_ulogic; + spr_dbg_match_mas6 : out std_ulogic; + spr_dbg_match_mas7 : out std_ulogic; + spr_dbg_match_mas8 : out std_ulogic; + spr_dbg_match_mas01_64b : out std_ulogic; + spr_dbg_match_mas56_64b : out std_ulogic; + spr_dbg_match_mas73_64b : out std_ulogic; + spr_dbg_match_mas81_64b : out std_ulogic; + + spr_dbg_slowspr_val_int : out std_ulogic; + spr_dbg_slowspr_rw_int : out std_ulogic; + spr_dbg_slowspr_etid_int : out std_ulogic_vector(0 to 1); + spr_dbg_slowspr_addr_int : out std_ulogic_vector(0 to 9); + spr_dbg_slowspr_val_out : out std_ulogic; + spr_dbg_slowspr_done_out : out std_ulogic; + spr_dbg_slowspr_data_out : out std_ulogic_vector(64-spr_data_width to 63); + + xu_mm_slowspr_val : in std_ulogic; + xu_mm_slowspr_rw : in std_ulogic; + xu_mm_slowspr_etid : in std_ulogic_vector(0 to 1); + xu_mm_slowspr_addr : in std_ulogic_vector(0 to 9); + xu_mm_slowspr_data : in std_ulogic_vector(64-spr_data_width to 63); + xu_mm_slowspr_done : in std_ulogic; + + mm_iu_slowspr_val : out std_ulogic; + mm_iu_slowspr_rw : out std_ulogic; + mm_iu_slowspr_etid : out std_ulogic_vector(0 to 1); + mm_iu_slowspr_addr : out std_ulogic_vector(0 to 9); + mm_iu_slowspr_data : out std_ulogic_vector(64-spr_data_width to 63); + mm_iu_slowspr_done : out std_ulogic + + +); +end mmq_spr; +architecture mmq_spr of mmq_spr is +constant Spr_Addr_PID : std_ulogic_vector(0 to 9) := "0000110000"; +constant Spr_Addr_LPID : std_ulogic_vector(0 to 9) := "0101010010"; +constant Spr_Addr_MMUCR0 : std_ulogic_vector(0 to 9) := "1111111100"; +constant Spr_Addr_MMUCR1 : std_ulogic_vector(0 to 9) := "1111111101"; +constant Spr_Addr_MMUCR2 : std_ulogic_vector(0 to 9) := "1111111110"; +constant Spr_Addr_MMUCR3 : std_ulogic_vector(0 to 9) := "1111111111"; +constant Spr_RW_Write : std_ulogic := '0'; +constant Spr_RW_Read : std_ulogic := '1'; +constant Spr_Addr_MAS0 : std_ulogic_vector(0 to 9) := "1001110000"; +constant Spr_Addr_MAS1 : std_ulogic_vector(0 to 9) := "1001110001"; +constant Spr_Addr_MAS2 : std_ulogic_vector(0 to 9) := "1001110010"; +constant Spr_Addr_MAS2U : std_ulogic_vector(0 to 9) := "1001110111"; +constant Spr_Addr_MAS3 : std_ulogic_vector(0 to 9) := "1001110011"; +constant Spr_Addr_MAS4 : std_ulogic_vector(0 to 9) := "1001110100"; +constant Spr_Addr_MAS5 : std_ulogic_vector(0 to 9) := "0101010011"; +constant Spr_Addr_MAS6 : std_ulogic_vector(0 to 9) := "1001110110"; +constant Spr_Addr_MAS7 : std_ulogic_vector(0 to 9) := "1110110000"; +constant Spr_Addr_MAS8 : std_ulogic_vector(0 to 9) := "0101010101"; +constant Spr_Addr_MAS56_64b : std_ulogic_vector(0 to 9) := "0101011100"; +constant Spr_Addr_MAS81_64b : std_ulogic_vector(0 to 9) := "0101011101"; +constant Spr_Addr_MAS73_64b : std_ulogic_vector(0 to 9) := "0101110100"; +constant Spr_Addr_MAS01_64b : std_ulogic_vector(0 to 9) := "0101110101"; +constant Spr_Addr_MMUCFG : std_ulogic_vector(0 to 9) := "1111110111"; +constant Spr_Addr_MMUCSR0 : std_ulogic_vector(0 to 9) := "1111110100"; +constant Spr_Addr_TLB0CFG : std_ulogic_vector(0 to 9) := "1010110000"; +constant Spr_Addr_TLB0PS : std_ulogic_vector(0 to 9) := "0101011000"; +constant Spr_Addr_LRATCFG : std_ulogic_vector(0 to 9) := "0101010110"; +constant Spr_Addr_LRATPS : std_ulogic_vector(0 to 9) := "0101010111"; +constant Spr_Addr_EPTCFG : std_ulogic_vector(0 to 9) := "0101011110"; +constant Spr_Addr_LPER : std_ulogic_vector(0 to 9) := "0000111000"; +constant Spr_Addr_LPERU : std_ulogic_vector(0 to 9) := "0000111001"; +-- MMUCFG: 32:35 resv, 36:39 LPIDSIZE=0x8, 40:46 RASIZE=0x2a, 47 LRAT bcfg, 48 TWC bcfg, +-- 49:52 resv, 53:57 PIDSIZE=0xd, 58:59 resv, 60:61 NTLBS=0b00, 62:63 MAVN=0b01 +constant Spr_Data_MMUCFG : std_ulogic_vector(32 to 63) := "00001000010101011000001101000001"; +-- TLB0CFG: 32:39 ASSOC=0x04, 40:44 resv, 45 PT bcfg, 46 IND bcfg, 47 GTWE bcfg, +-- 48 IPROT=1, 49 resv, 50 HES=1, 51 resv, 52:63 NENTRY=0x200 +constant Spr_Data_TLB0CFG : std_ulogic_vector(32 to 63) := "00000100000000001010001000000000"; +-- TLB0PS: 32:63 PS31-PS0=0x0010_4444 (PS20, PS14, PS10, PS6, PS2 = 1, others = 0) +constant Spr_Data_TLB0PS : std_ulogic_vector(32 to 63) := "00000000000100000100010001000100"; +-- LRATCFG: 32:39 ASSOC=0x00, 40:46 LASIZE=0x2a, 47:49 resv, 50 LPID=1, 51 resv, 52:63 NENTRY=0x008 +constant Spr_Data_LRATCFG : std_ulogic_vector(32 to 63) := "00000000010101000010000000001000"; +-- LRATPS: 32:63 PS31-PS0=0x5154_4400 (PS30, PS28, PS24, PS22, PS20, PS18, PS14, PS10 = 1, others = 0) +constant Spr_Data_LRATPS : std_ulogic_vector(32 to 63) := "01010001010101000100010000000000"; +-- EPTCFG: 32:43 resv, 44:48 PS1=0x12, 49:53 SPS1=0x06, 54:58 PS0=0x0a, 59:63 SPS0=0x02 +constant Spr_Data_EPTCFG : std_ulogic_vector(32 to 63) := "00000000000010010001100101000010"; +-- latches scan chain constants +constant spr_ctl_in_offset : natural := 0; +constant spr_etid_in_offset : natural := spr_ctl_in_offset + spr_ctl_width; +constant spr_addr_in_offset : natural := spr_etid_in_offset + spr_etid_width; +constant spr_data_in_offset : natural := spr_addr_in_offset + spr_addr_width; +constant spr_ctl_int_offset : natural := spr_data_in_offset + spr_data_width; +constant spr_etid_int_offset : natural := spr_ctl_int_offset + spr_ctl_width; +constant spr_addr_int_offset : natural := spr_etid_int_offset + spr_etid_width; +constant spr_data_int_offset : natural := spr_addr_int_offset + spr_addr_width; +constant spr_ctl_out_offset : natural := spr_data_int_offset + spr_data_width; +constant spr_etid_out_offset : natural := spr_ctl_out_offset + spr_ctl_width; +constant spr_addr_out_offset : natural := spr_etid_out_offset + spr_etid_width; +constant spr_data_out_offset : natural := spr_addr_out_offset + spr_addr_width; +constant spr_match_any_mmu_offset : natural := spr_data_out_offset + spr_data_width; +constant spr_match_pid0_offset : natural := spr_match_any_mmu_offset + 1; +constant spr_match_pid1_offset : natural := spr_match_pid0_offset + 1; +constant spr_match_pid2_offset : natural := spr_match_pid1_offset + 1; +constant spr_match_pid3_offset : natural := spr_match_pid2_offset + 1; +constant spr_match_mmucr0_0_offset : natural := spr_match_pid3_offset + 1; +constant spr_match_mmucr0_1_offset : natural := spr_match_mmucr0_0_offset + 1; +constant spr_match_mmucr0_2_offset : natural := spr_match_mmucr0_1_offset + 1; +constant spr_match_mmucr0_3_offset : natural := spr_match_mmucr0_2_offset + 1; +constant spr_match_mmucr1_offset : natural := spr_match_mmucr0_3_offset + 1; +constant spr_match_mmucr2_offset : natural := spr_match_mmucr1_offset + 1; +constant spr_match_mmucr3_0_offset : natural := spr_match_mmucr2_offset + 1; +constant spr_match_mmucr3_1_offset : natural := spr_match_mmucr3_0_offset + 1; +constant spr_match_mmucr3_2_offset : natural := spr_match_mmucr3_1_offset + 1; +constant spr_match_mmucr3_3_offset : natural := spr_match_mmucr3_2_offset + 1; +constant spr_match_lpidr_offset : natural := spr_match_mmucr3_3_offset + 1; +constant pid0_offset : natural := spr_match_lpidr_offset + 1; +constant pid1_offset : natural := pid0_offset + pid_width; +constant pid2_offset : natural := pid1_offset + pid_width; +constant pid3_offset : natural := pid2_offset + pid_width; +constant mmucr0_0_offset : natural := pid3_offset + pid_width; +constant mmucr0_1_offset : natural := mmucr0_0_offset + mmucr0_width; +constant mmucr0_2_offset : natural := mmucr0_1_offset + mmucr0_width; +constant mmucr0_3_offset : natural := mmucr0_2_offset + mmucr0_width; +constant lpidr_offset : natural := mmucr0_3_offset + mmucr0_width; +constant spare_a_offset : natural := lpidr_offset + lpid_width; +constant spr_mmu_act_offset : natural := spare_a_offset + 32; +constant spr_val_act_offset : natural := spr_mmu_act_offset + thdid_width +1; +constant cswitch_offset : natural := spr_val_act_offset + 4; +constant scan_right_0 : natural := cswitch_offset + 4 -1; +-- MAS register constants +constant spr_match_mmucsr0_offset : natural := 0; +constant spr_match_mmucfg_offset : natural := spr_match_mmucsr0_offset + 1; +constant spr_match_tlb0cfg_offset : natural := spr_match_mmucfg_offset + 1; +constant spr_match_tlb0ps_offset : natural := spr_match_tlb0cfg_offset + 1; +constant spr_match_lratcfg_offset : natural := spr_match_tlb0ps_offset + 1; +constant spr_match_lratps_offset : natural := spr_match_lratcfg_offset + 1; +constant spr_match_eptcfg_offset : natural := spr_match_lratps_offset + 1; +constant spr_match_lper_0_offset : natural := spr_match_eptcfg_offset + 1; +constant spr_match_lper_1_offset : natural := spr_match_lper_0_offset + 1; +constant spr_match_lper_2_offset : natural := spr_match_lper_1_offset + 1; +constant spr_match_lper_3_offset : natural := spr_match_lper_2_offset + 1; +constant spr_match_lperu_0_offset : natural := spr_match_lper_3_offset + 1; +constant spr_match_lperu_1_offset : natural := spr_match_lperu_0_offset + 1; +constant spr_match_lperu_2_offset : natural := spr_match_lperu_1_offset + 1; +constant spr_match_lperu_3_offset : natural := spr_match_lperu_2_offset + 1; +constant spr_match_mas0_0_offset : natural := spr_match_lperu_3_offset + 1; +constant spr_match_mas1_0_offset : natural := spr_match_mas0_0_offset + 1; +constant spr_match_mas2_0_offset : natural := spr_match_mas1_0_offset + 1; +constant spr_match_mas2u_0_offset : natural := spr_match_mas2_0_offset + 1; +constant spr_match_mas3_0_offset : natural := spr_match_mas2u_0_offset + 1; +constant spr_match_mas4_0_offset : natural := spr_match_mas3_0_offset + 1; +constant spr_match_mas5_0_offset : natural := spr_match_mas4_0_offset + 1; +constant spr_match_mas6_0_offset : natural := spr_match_mas5_0_offset + 1; +constant spr_match_mas7_0_offset : natural := spr_match_mas6_0_offset + 1; +constant spr_match_mas8_0_offset : natural := spr_match_mas7_0_offset + 1; +constant spr_match_mas01_64b_0_offset : natural := spr_match_mas8_0_offset + 1; +constant spr_match_mas56_64b_0_offset : natural := spr_match_mas01_64b_0_offset + 1; +constant spr_match_mas73_64b_0_offset : natural := spr_match_mas56_64b_0_offset + 1; +constant spr_match_mas81_64b_0_offset : natural := spr_match_mas73_64b_0_offset + 1; +constant spr_match_mas0_1_offset : natural := spr_match_mas81_64b_0_offset + 1; +constant spr_match_mas1_1_offset : natural := spr_match_mas0_1_offset + 1; +constant spr_match_mas2_1_offset : natural := spr_match_mas1_1_offset + 1; +constant spr_match_mas2u_1_offset : natural := spr_match_mas2_1_offset + 1; +constant spr_match_mas3_1_offset : natural := spr_match_mas2u_1_offset + 1; +constant spr_match_mas4_1_offset : natural := spr_match_mas3_1_offset + 1; +constant spr_match_mas5_1_offset : natural := spr_match_mas4_1_offset + 1; +constant spr_match_mas6_1_offset : natural := spr_match_mas5_1_offset + 1; +constant spr_match_mas7_1_offset : natural := spr_match_mas6_1_offset + 1; +constant spr_match_mas8_1_offset : natural := spr_match_mas7_1_offset + 1; +constant spr_match_mas01_64b_1_offset : natural := spr_match_mas8_1_offset + 1; +constant spr_match_mas56_64b_1_offset : natural := spr_match_mas01_64b_1_offset + 1; +constant spr_match_mas73_64b_1_offset : natural := spr_match_mas56_64b_1_offset + 1; +constant spr_match_mas81_64b_1_offset : natural := spr_match_mas73_64b_1_offset + 1; +constant spr_match_mas0_2_offset : natural := spr_match_mas81_64b_1_offset + 1; +constant spr_match_mas1_2_offset : natural := spr_match_mas0_2_offset + 1; +constant spr_match_mas2_2_offset : natural := spr_match_mas1_2_offset + 1; +constant spr_match_mas2u_2_offset : natural := spr_match_mas2_2_offset + 1; +constant spr_match_mas3_2_offset : natural := spr_match_mas2u_2_offset + 1; +constant spr_match_mas4_2_offset : natural := spr_match_mas3_2_offset + 1; +constant spr_match_mas5_2_offset : natural := spr_match_mas4_2_offset + 1; +constant spr_match_mas6_2_offset : natural := spr_match_mas5_2_offset + 1; +constant spr_match_mas7_2_offset : natural := spr_match_mas6_2_offset + 1; +constant spr_match_mas8_2_offset : natural := spr_match_mas7_2_offset + 1; +constant spr_match_mas01_64b_2_offset : natural := spr_match_mas8_2_offset + 1; +constant spr_match_mas56_64b_2_offset : natural := spr_match_mas01_64b_2_offset + 1; +constant spr_match_mas73_64b_2_offset : natural := spr_match_mas56_64b_2_offset + 1; +constant spr_match_mas81_64b_2_offset : natural := spr_match_mas73_64b_2_offset + 1; +constant spr_match_mas0_3_offset : natural := spr_match_mas81_64b_2_offset + 1; +constant spr_match_mas1_3_offset : natural := spr_match_mas0_3_offset + 1; +constant spr_match_mas2_3_offset : natural := spr_match_mas1_3_offset + 1; +constant spr_match_mas2u_3_offset : natural := spr_match_mas2_3_offset + 1; +constant spr_match_mas3_3_offset : natural := spr_match_mas2u_3_offset + 1; +constant spr_match_mas4_3_offset : natural := spr_match_mas3_3_offset + 1; +constant spr_match_mas5_3_offset : natural := spr_match_mas4_3_offset + 1; +constant spr_match_mas6_3_offset : natural := spr_match_mas5_3_offset + 1; +constant spr_match_mas7_3_offset : natural := spr_match_mas6_3_offset + 1; +constant spr_match_mas8_3_offset : natural := spr_match_mas7_3_offset + 1; +constant spr_match_mas01_64b_3_offset : natural := spr_match_mas8_3_offset + 1; +constant spr_match_mas56_64b_3_offset : natural := spr_match_mas01_64b_3_offset + 1; +constant spr_match_mas73_64b_3_offset : natural := spr_match_mas56_64b_3_offset + 1; +constant spr_match_mas81_64b_3_offset : natural := spr_match_mas73_64b_3_offset + 1; +constant spr_match_64b_offset : natural := spr_match_mas81_64b_3_offset + 1; +constant spr_addr_in_clone_offset : natural := spr_match_64b_offset + 1; +constant spr_mas_data_out_offset : natural := spr_addr_in_clone_offset + spr_addr_width; +constant spr_match_any_mas_offset : natural := spr_mas_data_out_offset + spr_data_width; +constant mas0_0_atsel_offset : natural := spr_match_any_mas_offset + 1; +constant mas0_0_esel_offset : natural := mas0_0_atsel_offset + 1; +constant mas0_0_hes_offset : natural := mas0_0_esel_offset + 3; +constant mas0_0_wq_offset : natural := mas0_0_hes_offset + 1; +constant mas1_0_v_offset : natural := mas0_0_wq_offset + 2; +constant mas1_0_iprot_offset : natural := mas1_0_v_offset + 1; +constant mas1_0_tid_offset : natural := mas1_0_iprot_offset + 1; +constant mas1_0_ind_offset : natural := mas1_0_tid_offset + 14; +constant mas1_0_ts_offset : natural := mas1_0_ind_offset + 1; +constant mas1_0_tsize_offset : natural := mas1_0_ts_offset + 1; +constant mas2_0_epn_offset : natural := mas1_0_tsize_offset + 4; +constant mas2_0_wimge_offset : natural := mas2_0_epn_offset + 52+spr_data_width-64; +constant mas3_0_rpnl_offset : natural := mas2_0_wimge_offset + 5; +constant mas3_0_ubits_offset : natural := mas3_0_rpnl_offset + 21; +constant mas3_0_usxwr_offset : natural := mas3_0_ubits_offset + 4; +constant mas5_0_sgs_offset : natural := mas3_0_usxwr_offset + 6; +constant mas5_0_slpid_offset : natural := mas5_0_sgs_offset + 1; +constant mas6_0_spid_offset : natural := mas5_0_slpid_offset + 8; +constant mas6_0_isize_offset : natural := mas6_0_spid_offset + 14; +constant mas6_0_sind_offset : natural := mas6_0_isize_offset + 4; +constant mas6_0_sas_offset : natural := mas6_0_sind_offset + 1; +constant mas7_0_rpnu_offset : natural := mas6_0_sas_offset + 1; +constant mas8_0_tgs_offset : natural := mas7_0_rpnu_offset + 10; +constant mas8_0_vf_offset : natural := mas8_0_tgs_offset + 1; +constant mas8_0_tlpid_offset : natural := mas8_0_vf_offset + 1; +constant mas0_1_atsel_offset : natural := mas8_0_tlpid_offset + 8; +constant mas0_1_esel_offset : natural := mas0_1_atsel_offset + 1; +constant mas0_1_hes_offset : natural := mas0_1_esel_offset + 3; +constant mas0_1_wq_offset : natural := mas0_1_hes_offset + 1; +constant mas1_1_v_offset : natural := mas0_1_wq_offset + 2; +constant mas1_1_iprot_offset : natural := mas1_1_v_offset + 1; +constant mas1_1_tid_offset : natural := mas1_1_iprot_offset + 1; +constant mas1_1_ind_offset : natural := mas1_1_tid_offset + 14; +constant mas1_1_ts_offset : natural := mas1_1_ind_offset + 1; +constant mas1_1_tsize_offset : natural := mas1_1_ts_offset + 1; +constant mas2_1_epn_offset : natural := mas1_1_tsize_offset + 4; +constant mas2_1_wimge_offset : natural := mas2_1_epn_offset + 52+spr_data_width-64; +constant mas3_1_rpnl_offset : natural := mas2_1_wimge_offset + 5; +constant mas3_1_ubits_offset : natural := mas3_1_rpnl_offset + 21; +constant mas3_1_usxwr_offset : natural := mas3_1_ubits_offset + 4; +constant mas5_1_sgs_offset : natural := mas3_1_usxwr_offset + 6; +constant mas5_1_slpid_offset : natural := mas5_1_sgs_offset + 1; +constant mas6_1_spid_offset : natural := mas5_1_slpid_offset + 8; +constant mas6_1_isize_offset : natural := mas6_1_spid_offset + 14; +constant mas6_1_sind_offset : natural := mas6_1_isize_offset + 4; +constant mas6_1_sas_offset : natural := mas6_1_sind_offset + 1; +constant mas7_1_rpnu_offset : natural := mas6_1_sas_offset + 1; +constant mas8_1_tgs_offset : natural := mas7_1_rpnu_offset + 10; +constant mas8_1_vf_offset : natural := mas8_1_tgs_offset + 1; +constant mas8_1_tlpid_offset : natural := mas8_1_vf_offset + 1; +constant mas0_2_atsel_offset : natural := mas8_1_tlpid_offset + 8; +constant mas0_2_esel_offset : natural := mas0_2_atsel_offset + 1; +constant mas0_2_hes_offset : natural := mas0_2_esel_offset + 3; +constant mas0_2_wq_offset : natural := mas0_2_hes_offset + 1; +constant mas1_2_v_offset : natural := mas0_2_wq_offset + 2; +constant mas1_2_iprot_offset : natural := mas1_2_v_offset + 1; +constant mas1_2_tid_offset : natural := mas1_2_iprot_offset + 1; +constant mas1_2_ind_offset : natural := mas1_2_tid_offset + 14; +constant mas1_2_ts_offset : natural := mas1_2_ind_offset + 1; +constant mas1_2_tsize_offset : natural := mas1_2_ts_offset + 1; +constant mas2_2_epn_offset : natural := mas1_2_tsize_offset + 4; +constant mas2_2_wimge_offset : natural := mas2_2_epn_offset + 52+spr_data_width-64; +constant mas3_2_rpnl_offset : natural := mas2_2_wimge_offset + 5; +constant mas3_2_ubits_offset : natural := mas3_2_rpnl_offset + 21; +constant mas3_2_usxwr_offset : natural := mas3_2_ubits_offset + 4; +constant mas5_2_sgs_offset : natural := mas3_2_usxwr_offset + 6; +constant mas5_2_slpid_offset : natural := mas5_2_sgs_offset + 1; +constant mas6_2_spid_offset : natural := mas5_2_slpid_offset + 8; +constant mas6_2_isize_offset : natural := mas6_2_spid_offset + 14; +constant mas6_2_sind_offset : natural := mas6_2_isize_offset + 4; +constant mas6_2_sas_offset : natural := mas6_2_sind_offset + 1; +constant mas7_2_rpnu_offset : natural := mas6_2_sas_offset + 1; +constant mas8_2_tgs_offset : natural := mas7_2_rpnu_offset + 10; +constant mas8_2_vf_offset : natural := mas8_2_tgs_offset + 1; +constant mas8_2_tlpid_offset : natural := mas8_2_vf_offset + 1; +constant mas0_3_atsel_offset : natural := mas8_2_tlpid_offset + 8; +constant mas0_3_esel_offset : natural := mas0_3_atsel_offset + 1; +constant mas0_3_hes_offset : natural := mas0_3_esel_offset + 3; +constant mas0_3_wq_offset : natural := mas0_3_hes_offset + 1; +constant mas1_3_v_offset : natural := mas0_3_wq_offset + 2; +constant mas1_3_iprot_offset : natural := mas1_3_v_offset + 1; +constant mas1_3_tid_offset : natural := mas1_3_iprot_offset + 1; +constant mas1_3_ind_offset : natural := mas1_3_tid_offset + 14; +constant mas1_3_ts_offset : natural := mas1_3_ind_offset + 1; +constant mas1_3_tsize_offset : natural := mas1_3_ts_offset + 1; +constant mas2_3_epn_offset : natural := mas1_3_tsize_offset + 4; +constant mas2_3_wimge_offset : natural := mas2_3_epn_offset + 52+spr_data_width-64; +constant mas3_3_rpnl_offset : natural := mas2_3_wimge_offset + 5; +constant mas3_3_ubits_offset : natural := mas3_3_rpnl_offset + 21; +constant mas3_3_usxwr_offset : natural := mas3_3_ubits_offset + 4; +constant mas5_3_sgs_offset : natural := mas3_3_usxwr_offset + 6; +constant mas5_3_slpid_offset : natural := mas5_3_sgs_offset + 1; +constant mas6_3_spid_offset : natural := mas5_3_slpid_offset + 8; +constant mas6_3_isize_offset : natural := mas6_3_spid_offset + 14; +constant mas6_3_sind_offset : natural := mas6_3_isize_offset + 4; +constant mas6_3_sas_offset : natural := mas6_3_sind_offset + 1; +constant mas7_3_rpnu_offset : natural := mas6_3_sas_offset + 1; +constant mas8_3_tgs_offset : natural := mas7_3_rpnu_offset + 10; +constant mas8_3_vf_offset : natural := mas8_3_tgs_offset + 1; +constant mas8_3_tlpid_offset : natural := mas8_3_vf_offset + 1; +constant mmucsr0_tlb0fi_offset : natural := mas8_3_tlpid_offset + 8; +constant scan_right_a : natural := mmucsr0_tlb0fi_offset + 1; +constant lper_0_alpn_offset : natural := scan_right_a; +constant lper_0_lps_offset : natural := lper_0_alpn_offset + real_addr_width-12; +constant lper_1_alpn_offset : natural := lper_0_lps_offset + 4; +constant lper_1_lps_offset : natural := lper_1_alpn_offset + real_addr_width-12; +constant lper_2_alpn_offset : natural := lper_1_lps_offset + 4; +constant lper_2_lps_offset : natural := lper_2_alpn_offset + real_addr_width-12; +constant lper_3_alpn_offset : natural := lper_2_lps_offset + 4; +constant lper_3_lps_offset : natural := lper_3_alpn_offset + real_addr_width-12; +constant spare_b_offset : natural := lper_3_lps_offset + 4; +constant cat_emf_act_offset : natural := spare_b_offset + 64; +constant scan_right_1 : natural := cat_emf_act_offset + thdid_width -1; +-- boot config scan bits +constant mmucfg_offset : natural := 0; +constant tlb0cfg_offset : natural := mmucfg_offset + 2; +constant mmucr1_offset : natural := tlb0cfg_offset + 3; +constant mmucr2_offset : natural := mmucr1_offset + mmucr1_width; +constant mmucr3_0_offset : natural := mmucr2_offset + mmucr2_width; +constant mmucr3_1_offset : natural := mmucr3_0_offset + mmucr3_width; +constant mmucr3_2_offset : natural := mmucr3_1_offset + mmucr3_width; +constant mmucr3_3_offset : natural := mmucr3_2_offset + mmucr3_width; +constant mas4_0_indd_offset : natural := mmucr3_3_offset + mmucr3_width; +constant mas4_0_tsized_offset : natural := mas4_0_indd_offset + 1; +constant mas4_0_wimged_offset : natural := mas4_0_tsized_offset + 4; +constant mas4_1_indd_offset : natural := mas4_0_wimged_offset + 5; +constant mas4_1_tsized_offset : natural := mas4_1_indd_offset + 1; +constant mas4_1_wimged_offset : natural := mas4_1_tsized_offset + 4; +constant mas4_2_indd_offset : natural := mas4_1_wimged_offset + 5; +constant mas4_2_tsized_offset : natural := mas4_2_indd_offset + 1; +constant mas4_2_wimged_offset : natural := mas4_2_tsized_offset + 4; +constant mas4_3_indd_offset : natural := mas4_2_wimged_offset + 5; +constant mas4_3_tsized_offset : natural := mas4_3_indd_offset + 1; +constant mas4_3_wimged_offset : natural := mas4_3_tsized_offset + 4; +constant bcfg_spare_offset : natural := mas4_3_wimged_offset + 5; +constant boot_scan_right : natural := bcfg_spare_offset + 16 - 1; +signal spr_match_any_mmu, spr_match_any_mmu_q : std_ulogic; +signal spr_match_pid0, spr_match_pid0_q : std_ulogic; +signal spr_match_pid1, spr_match_pid1_q : std_ulogic; +signal spr_match_pid2, spr_match_pid2_q : std_ulogic; +signal spr_match_pid3, spr_match_pid3_q : std_ulogic; +signal spr_match_mmucr0_0, spr_match_mmucr0_0_q : std_ulogic; +signal spr_match_mmucr0_1, spr_match_mmucr0_1_q : std_ulogic; +signal spr_match_mmucr0_2, spr_match_mmucr0_2_q : std_ulogic; +signal spr_match_mmucr0_3, spr_match_mmucr0_3_q : std_ulogic; +signal spr_match_mmucr1, spr_match_mmucr1_q : std_ulogic; +signal spr_match_mmucr2, spr_match_mmucr2_q : std_ulogic; +signal spr_match_mmucr3_0, spr_match_mmucr3_0_q : std_ulogic; +signal spr_match_mmucr3_1, spr_match_mmucr3_1_q : std_ulogic; +signal spr_match_mmucr3_2, spr_match_mmucr3_2_q : std_ulogic; +signal spr_match_mmucr3_3, spr_match_mmucr3_3_q : std_ulogic; +signal spr_match_lpidr, spr_match_lpidr_q : std_ulogic; +signal spr_match_mmucsr0, spr_match_mmucsr0_q : std_ulogic; +signal spr_match_mmucfg, spr_match_mmucfg_q : std_ulogic; +signal spr_match_tlb0cfg, spr_match_tlb0cfg_q : std_ulogic; +signal spr_match_tlb0ps, spr_match_tlb0ps_q : std_ulogic; +signal spr_match_lratcfg, spr_match_lratcfg_q : std_ulogic; +signal spr_match_lratps, spr_match_lratps_q : std_ulogic; +signal spr_match_eptcfg, spr_match_eptcfg_q : std_ulogic; +signal spr_match_lper_0, spr_match_lper_0_q : std_ulogic; +signal spr_match_lper_1, spr_match_lper_1_q : std_ulogic; +signal spr_match_lper_2, spr_match_lper_2_q : std_ulogic; +signal spr_match_lper_3, spr_match_lper_3_q : std_ulogic; +signal spr_match_lperu_0, spr_match_lperu_0_q : std_ulogic; +signal spr_match_lperu_1, spr_match_lperu_1_q : std_ulogic; +signal spr_match_lperu_2, spr_match_lperu_2_q : std_ulogic; +signal spr_match_lperu_3, spr_match_lperu_3_q : std_ulogic; +signal spr_match_mas0_0, spr_match_mas0_0_q : std_ulogic; +signal spr_match_mas1_0, spr_match_mas1_0_q : std_ulogic; +signal spr_match_mas2_0, spr_match_mas2_0_q : std_ulogic; +signal spr_match_mas2u_0, spr_match_mas2u_0_q : std_ulogic; +signal spr_match_mas3_0, spr_match_mas3_0_q : std_ulogic; +signal spr_match_mas4_0, spr_match_mas4_0_q : std_ulogic; +signal spr_match_mas5_0, spr_match_mas5_0_q : std_ulogic; +signal spr_match_mas6_0, spr_match_mas6_0_q : std_ulogic; +signal spr_match_mas7_0, spr_match_mas7_0_q : std_ulogic; +signal spr_match_mas8_0, spr_match_mas8_0_q : std_ulogic; +signal spr_match_mas01_64b_0, spr_match_mas01_64b_0_q : std_ulogic; +signal spr_match_mas56_64b_0, spr_match_mas56_64b_0_q : std_ulogic; +signal spr_match_mas73_64b_0, spr_match_mas73_64b_0_q : std_ulogic; +signal spr_match_mas81_64b_0, spr_match_mas81_64b_0_q : std_ulogic; +signal spr_match_mas0_1, spr_match_mas0_1_q : std_ulogic; +signal spr_match_mas1_1, spr_match_mas1_1_q : std_ulogic; +signal spr_match_mas2_1, spr_match_mas2_1_q : std_ulogic; +signal spr_match_mas2u_1, spr_match_mas2u_1_q : std_ulogic; +signal spr_match_mas3_1, spr_match_mas3_1_q : std_ulogic; +signal spr_match_mas4_1, spr_match_mas4_1_q : std_ulogic; +signal spr_match_mas5_1, spr_match_mas5_1_q : std_ulogic; +signal spr_match_mas6_1, spr_match_mas6_1_q : std_ulogic; +signal spr_match_mas7_1, spr_match_mas7_1_q : std_ulogic; +signal spr_match_mas8_1, spr_match_mas8_1_q : std_ulogic; +signal spr_match_mas01_64b_1, spr_match_mas01_64b_1_q : std_ulogic; +signal spr_match_mas56_64b_1, spr_match_mas56_64b_1_q : std_ulogic; +signal spr_match_mas73_64b_1, spr_match_mas73_64b_1_q : std_ulogic; +signal spr_match_mas81_64b_1, spr_match_mas81_64b_1_q : std_ulogic; +signal spr_match_mas0_2, spr_match_mas0_2_q : std_ulogic; +signal spr_match_mas1_2, spr_match_mas1_2_q : std_ulogic; +signal spr_match_mas2_2, spr_match_mas2_2_q : std_ulogic; +signal spr_match_mas2u_2, spr_match_mas2u_2_q : std_ulogic; +signal spr_match_mas3_2, spr_match_mas3_2_q : std_ulogic; +signal spr_match_mas4_2, spr_match_mas4_2_q : std_ulogic; +signal spr_match_mas5_2, spr_match_mas5_2_q : std_ulogic; +signal spr_match_mas6_2, spr_match_mas6_2_q : std_ulogic; +signal spr_match_mas7_2, spr_match_mas7_2_q : std_ulogic; +signal spr_match_mas8_2, spr_match_mas8_2_q : std_ulogic; +signal spr_match_mas01_64b_2, spr_match_mas01_64b_2_q : std_ulogic; +signal spr_match_mas56_64b_2, spr_match_mas56_64b_2_q : std_ulogic; +signal spr_match_mas73_64b_2, spr_match_mas73_64b_2_q : std_ulogic; +signal spr_match_mas81_64b_2, spr_match_mas81_64b_2_q : std_ulogic; +signal spr_match_mas0_3, spr_match_mas0_3_q : std_ulogic; +signal spr_match_mas1_3, spr_match_mas1_3_q : std_ulogic; +signal spr_match_mas2_3, spr_match_mas2_3_q : std_ulogic; +signal spr_match_mas2u_3, spr_match_mas2u_3_q : std_ulogic; +signal spr_match_mas3_3, spr_match_mas3_3_q : std_ulogic; +signal spr_match_mas4_3, spr_match_mas4_3_q : std_ulogic; +signal spr_match_mas5_3, spr_match_mas5_3_q : std_ulogic; +signal spr_match_mas6_3, spr_match_mas6_3_q : std_ulogic; +signal spr_match_mas7_3, spr_match_mas7_3_q : std_ulogic; +signal spr_match_mas8_3, spr_match_mas8_3_q : std_ulogic; +signal spr_match_mas01_64b_3, spr_match_mas01_64b_3_q : std_ulogic; +signal spr_match_mas56_64b_3, spr_match_mas56_64b_3_q : std_ulogic; +signal spr_match_mas73_64b_3, spr_match_mas73_64b_3_q : std_ulogic; +signal spr_match_mas81_64b_3, spr_match_mas81_64b_3_q : std_ulogic; +signal spr_mas_data_out, spr_mas_data_out_q : std_ulogic_vector(64-spr_data_width to 63); +signal spr_match_any_mas, spr_match_any_mas_q : std_ulogic; +signal spr_match_mas2_64b : std_ulogic; +signal spr_match_mas01_64b : std_ulogic; +signal spr_match_mas56_64b : std_ulogic; +signal spr_match_mas73_64b : std_ulogic; +signal spr_match_mas81_64b : std_ulogic; +signal spr_match_64b, spr_match_64b_q : std_ulogic; +-- added input latches for timing with adding numerous mas regs +signal spr_ctl_in_d, spr_ctl_in_q : std_ulogic_vector(0 to spr_ctl_width-1); +signal spr_etid_in_d, spr_etid_in_q : std_ulogic_vector(0 to spr_etid_width-1); +signal spr_addr_in_d, spr_addr_in_q : std_ulogic_vector(0 to spr_addr_width-1); +signal spr_data_in_d, spr_data_in_q : std_ulogic_vector(64-spr_data_width to 63); +signal spr_addr_in_clone_d, spr_addr_in_clone_q : std_ulogic_vector(0 to spr_addr_width-1); +signal spr_ctl_int_d, spr_ctl_int_q : std_ulogic_vector(0 to spr_ctl_width-1); +signal spr_etid_int_d, spr_etid_int_q : std_ulogic_vector(0 to spr_etid_width-1); +signal spr_addr_int_d, spr_addr_int_q : std_ulogic_vector(0 to spr_addr_width-1); +signal spr_data_int_d, spr_data_int_q : std_ulogic_vector(64-spr_data_width to 63); +signal spr_ctl_out_d, spr_ctl_out_q : std_ulogic_vector(0 to spr_ctl_width-1); +signal spr_etid_out_d, spr_etid_out_q : std_ulogic_vector(0 to spr_etid_width-1); +signal spr_addr_out_d, spr_addr_out_q : std_ulogic_vector(0 to spr_addr_width-1); +signal spr_data_out_d, spr_data_out_q : std_ulogic_vector(64-spr_data_width to 63); +signal pid0_d, pid0_q : std_ulogic_vector(0 to pid_width-1); +signal mmucr0_0_d, mmucr0_0_q : std_ulogic_vector(0 to mmucr0_width-1); +signal mmucr3_0_d, mmucr3_0_q : std_ulogic_vector(64-mmucr3_width to 63); +signal pid1_d, pid1_q : std_ulogic_vector(0 to pid_width-1); +signal mmucr0_1_d, mmucr0_1_q : std_ulogic_vector(0 to mmucr0_width-1); +signal mmucr3_1_d, mmucr3_1_q : std_ulogic_vector(64-mmucr3_width to 63); +signal pid2_d, pid2_q : std_ulogic_vector(0 to pid_width-1); +signal mmucr0_2_d, mmucr0_2_q : std_ulogic_vector(0 to mmucr0_width-1); +signal mmucr3_2_d, mmucr3_2_q : std_ulogic_vector(64-mmucr3_width to 63); +signal pid3_d, pid3_q : std_ulogic_vector(0 to pid_width-1); +signal mmucr0_3_d, mmucr0_3_q : std_ulogic_vector(0 to mmucr0_width-1); +signal mmucr3_3_d, mmucr3_3_q : std_ulogic_vector(64-mmucr3_width to 63); +signal mmucr1_d, mmucr1_q : std_ulogic_vector(0 to mmucr1_width-1); +signal mmucr2_d, mmucr2_q : std_ulogic_vector(0 to mmucr2_width-1); +signal lpidr_d, lpidr_q : std_ulogic_vector(0 to lpid_width-1); +signal mas0_0_atsel_d, mas0_0_atsel_q : std_ulogic; +signal mas0_0_esel_d, mas0_0_esel_q : std_ulogic_vector(0 to 2); +signal mas0_0_hes_d, mas0_0_hes_q : std_ulogic; +signal mas0_0_wq_d, mas0_0_wq_q : std_ulogic_vector(0 to 1); +signal mas1_0_v_d, mas1_0_v_q : std_ulogic; +signal mas1_0_iprot_d, mas1_0_iprot_q : std_ulogic; +signal mas1_0_tid_d, mas1_0_tid_q : std_ulogic_vector(0 to 13); +signal mas1_0_ind_d, mas1_0_ind_q : std_ulogic; +signal mas1_0_ts_d, mas1_0_ts_q : std_ulogic; +signal mas1_0_tsize_d, mas1_0_tsize_q : std_ulogic_vector(0 to 3); +signal mas2_0_epn_d, mas2_0_epn_q : std_ulogic_vector(64-spr_data_width to 51); +signal mas2_0_wimge_d, mas2_0_wimge_q : std_ulogic_vector(0 to 4); +signal mas3_0_rpnl_d, mas3_0_rpnl_q : std_ulogic_vector(32 to 52); +signal mas3_0_ubits_d, mas3_0_ubits_q : std_ulogic_vector(0 to 3); +signal mas3_0_usxwr_d, mas3_0_usxwr_q : std_ulogic_vector(0 to 5); +signal mas4_0_indd_d, mas4_0_indd_q : std_ulogic; +signal mas4_0_tsized_d, mas4_0_tsized_q : std_ulogic_vector(0 to 3); +signal mas4_0_wimged_d, mas4_0_wimged_q : std_ulogic_vector(0 to 4); +signal mas5_0_sgs_d, mas5_0_sgs_q : std_ulogic; +signal mas5_0_slpid_d, mas5_0_slpid_q : std_ulogic_vector(0 to 7); +signal mas6_0_spid_d, mas6_0_spid_q : std_ulogic_vector(0 to 13); +signal mas6_0_isize_d, mas6_0_isize_q : std_ulogic_vector(0 to 3); +signal mas6_0_sind_d, mas6_0_sind_q : std_ulogic; +signal mas6_0_sas_d, mas6_0_sas_q : std_ulogic; +signal mas7_0_rpnu_d, mas7_0_rpnu_q : std_ulogic_vector(22 to 31); +signal mas8_0_tgs_d, mas8_0_tgs_q : std_ulogic; +signal mas8_0_vf_d, mas8_0_vf_q : std_ulogic; +signal mas8_0_tlpid_d, mas8_0_tlpid_q : std_ulogic_vector(0 to 7); +signal mas0_1_atsel_d, mas0_1_atsel_q : std_ulogic; +signal mas0_1_esel_d, mas0_1_esel_q : std_ulogic_vector(0 to 2); +signal mas0_1_hes_d, mas0_1_hes_q : std_ulogic; +signal mas0_1_wq_d, mas0_1_wq_q : std_ulogic_vector(0 to 1); +signal mas1_1_v_d, mas1_1_v_q : std_ulogic; +signal mas1_1_iprot_d, mas1_1_iprot_q : std_ulogic; +signal mas1_1_tid_d, mas1_1_tid_q : std_ulogic_vector(0 to 13); +signal mas1_1_ind_d, mas1_1_ind_q : std_ulogic; +signal mas1_1_ts_d, mas1_1_ts_q : std_ulogic; +signal mas1_1_tsize_d, mas1_1_tsize_q : std_ulogic_vector(0 to 3); +signal mas2_1_epn_d, mas2_1_epn_q : std_ulogic_vector(64-spr_data_width to 51); +signal mas2_1_wimge_d, mas2_1_wimge_q : std_ulogic_vector(0 to 4); +signal mas3_1_rpnl_d, mas3_1_rpnl_q : std_ulogic_vector(32 to 52); +signal mas3_1_ubits_d, mas3_1_ubits_q : std_ulogic_vector(0 to 3); +signal mas3_1_usxwr_d, mas3_1_usxwr_q : std_ulogic_vector(0 to 5); +signal mas4_1_indd_d, mas4_1_indd_q : std_ulogic; +signal mas4_1_tsized_d, mas4_1_tsized_q : std_ulogic_vector(0 to 3); +signal mas4_1_wimged_d, mas4_1_wimged_q : std_ulogic_vector(0 to 4); +signal mas5_1_sgs_d, mas5_1_sgs_q : std_ulogic; +signal mas5_1_slpid_d, mas5_1_slpid_q : std_ulogic_vector(0 to 7); +signal mas6_1_spid_d, mas6_1_spid_q : std_ulogic_vector(0 to 13); +signal mas6_1_isize_d, mas6_1_isize_q : std_ulogic_vector(0 to 3); +signal mas6_1_sind_d, mas6_1_sind_q : std_ulogic; +signal mas6_1_sas_d, mas6_1_sas_q : std_ulogic; +signal mas7_1_rpnu_d, mas7_1_rpnu_q : std_ulogic_vector(22 to 31); +signal mas8_1_tgs_d, mas8_1_tgs_q : std_ulogic; +signal mas8_1_vf_d, mas8_1_vf_q : std_ulogic; +signal mas8_1_tlpid_d, mas8_1_tlpid_q : std_ulogic_vector(0 to 7); +signal mas0_2_atsel_d, mas0_2_atsel_q : std_ulogic; +signal mas0_2_esel_d, mas0_2_esel_q : std_ulogic_vector(0 to 2); +signal mas0_2_hes_d, mas0_2_hes_q : std_ulogic; +signal mas0_2_wq_d, mas0_2_wq_q : std_ulogic_vector(0 to 1); +signal mas1_2_v_d, mas1_2_v_q : std_ulogic; +signal mas1_2_iprot_d, mas1_2_iprot_q : std_ulogic; +signal mas1_2_tid_d, mas1_2_tid_q : std_ulogic_vector(0 to 13); +signal mas1_2_ind_d, mas1_2_ind_q : std_ulogic; +signal mas1_2_ts_d, mas1_2_ts_q : std_ulogic; +signal mas1_2_tsize_d, mas1_2_tsize_q : std_ulogic_vector(0 to 3); +signal mas2_2_epn_d, mas2_2_epn_q : std_ulogic_vector(64-spr_data_width to 51); +signal mas2_2_wimge_d, mas2_2_wimge_q : std_ulogic_vector(0 to 4); +signal mas3_2_rpnl_d, mas3_2_rpnl_q : std_ulogic_vector(32 to 52); +signal mas3_2_ubits_d, mas3_2_ubits_q : std_ulogic_vector(0 to 3); +signal mas3_2_usxwr_d, mas3_2_usxwr_q : std_ulogic_vector(0 to 5); +signal mas4_2_indd_d, mas4_2_indd_q : std_ulogic; +signal mas4_2_tsized_d, mas4_2_tsized_q : std_ulogic_vector(0 to 3); +signal mas4_2_wimged_d, mas4_2_wimged_q : std_ulogic_vector(0 to 4); +signal mas5_2_sgs_d, mas5_2_sgs_q : std_ulogic; +signal mas5_2_slpid_d, mas5_2_slpid_q : std_ulogic_vector(0 to 7); +signal mas6_2_spid_d, mas6_2_spid_q : std_ulogic_vector(0 to 13); +signal mas6_2_isize_d, mas6_2_isize_q : std_ulogic_vector(0 to 3); +signal mas6_2_sind_d, mas6_2_sind_q : std_ulogic; +signal mas6_2_sas_d, mas6_2_sas_q : std_ulogic; +signal mas7_2_rpnu_d, mas7_2_rpnu_q : std_ulogic_vector(22 to 31); +signal mas8_2_tgs_d, mas8_2_tgs_q : std_ulogic; +signal mas8_2_vf_d, mas8_2_vf_q : std_ulogic; +signal mas8_2_tlpid_d, mas8_2_tlpid_q : std_ulogic_vector(0 to 7); +signal mas0_3_atsel_d, mas0_3_atsel_q : std_ulogic; +signal mas0_3_esel_d, mas0_3_esel_q : std_ulogic_vector(0 to 2); +signal mas0_3_hes_d, mas0_3_hes_q : std_ulogic; +signal mas0_3_wq_d, mas0_3_wq_q : std_ulogic_vector(0 to 1); +signal mas1_3_v_d, mas1_3_v_q : std_ulogic; +signal mas1_3_iprot_d, mas1_3_iprot_q : std_ulogic; +signal mas1_3_tid_d, mas1_3_tid_q : std_ulogic_vector(0 to 13); +signal mas1_3_ind_d, mas1_3_ind_q : std_ulogic; +signal mas1_3_ts_d, mas1_3_ts_q : std_ulogic; +signal mas1_3_tsize_d, mas1_3_tsize_q : std_ulogic_vector(0 to 3); +signal mas2_3_epn_d, mas2_3_epn_q : std_ulogic_vector(64-spr_data_width to 51); +signal mas2_3_wimge_d, mas2_3_wimge_q : std_ulogic_vector(0 to 4); +signal mas3_3_rpnl_d, mas3_3_rpnl_q : std_ulogic_vector(32 to 52); +signal mas3_3_ubits_d, mas3_3_ubits_q : std_ulogic_vector(0 to 3); +signal mas3_3_usxwr_d, mas3_3_usxwr_q : std_ulogic_vector(0 to 5); +signal mas4_3_indd_d, mas4_3_indd_q : std_ulogic; +signal mas4_3_tsized_d, mas4_3_tsized_q : std_ulogic_vector(0 to 3); +signal mas4_3_wimged_d, mas4_3_wimged_q : std_ulogic_vector(0 to 4); +signal mas5_3_sgs_d, mas5_3_sgs_q : std_ulogic; +signal mas5_3_slpid_d, mas5_3_slpid_q : std_ulogic_vector(0 to 7); +signal mas6_3_spid_d, mas6_3_spid_q : std_ulogic_vector(0 to 13); +signal mas6_3_isize_d, mas6_3_isize_q : std_ulogic_vector(0 to 3); +signal mas6_3_sind_d, mas6_3_sind_q : std_ulogic; +signal mas6_3_sas_d, mas6_3_sas_q : std_ulogic; +signal mas7_3_rpnu_d, mas7_3_rpnu_q : std_ulogic_vector(22 to 31); +signal mas8_3_tgs_d, mas8_3_tgs_q : std_ulogic; +signal mas8_3_vf_d, mas8_3_vf_q : std_ulogic; +signal mas8_3_tlpid_d, mas8_3_tlpid_q : std_ulogic_vector(0 to 7); +signal mmucsr0_tlb0fi_d, mmucsr0_tlb0fi_q : std_ulogic; +signal lper_0_alpn_d, lper_0_alpn_q : std_ulogic_vector(64-real_addr_width to 51); +signal lper_0_lps_d, lper_0_lps_q : std_ulogic_vector(60 to 63); +signal lper_1_alpn_d, lper_1_alpn_q : std_ulogic_vector(64-real_addr_width to 51); +signal lper_1_lps_d, lper_1_lps_q : std_ulogic_vector(60 to 63); +signal lper_2_alpn_d, lper_2_alpn_q : std_ulogic_vector(64-real_addr_width to 51); +signal lper_2_lps_d, lper_2_lps_q : std_ulogic_vector(60 to 63); +signal lper_3_alpn_d, lper_3_alpn_q : std_ulogic_vector(64-real_addr_width to 51); +signal lper_3_lps_d, lper_3_lps_q : std_ulogic_vector(60 to 63); +-- timing nsl's +signal iu_mm_ierat_mmucr0_q : std_ulogic_vector(0 to 17); +signal iu_mm_ierat_mmucr0_we_q : std_ulogic_vector(0 to thdid_width-1); +signal iu_mm_ierat_mmucr1_q : std_ulogic_vector(0 to 3); +signal iu_mm_ierat_mmucr1_we_q : std_ulogic; +signal xu_mm_derat_mmucr0_q : std_ulogic_vector(0 to 17); +signal xu_mm_derat_mmucr0_we_q : std_ulogic_vector(0 to thdid_width-1); +signal xu_mm_derat_mmucr1_q : std_ulogic_vector(0 to 4); +signal xu_mm_derat_mmucr1_we_q : std_ulogic; +signal spare_a_q : std_ulogic_vector(0 to 31); +signal spare_b_q : std_ulogic_vector(0 to 63); +signal unused_dc : std_ulogic_vector(0 to 13); +-- synopsys translate_off +-- synopsys translate_on +-- Pervasive +signal pc_sg_1 : std_ulogic; +signal pc_sg_0 : std_ulogic; +signal pc_fce_1 : std_ulogic; +signal pc_fce_0 : std_ulogic; +signal pc_func_sl_thold_1 : std_ulogic; +signal pc_func_sl_thold_0 : std_ulogic; +signal pc_func_sl_thold_0_b : std_ulogic; +signal pc_func_slp_sl_thold_1 : std_ulogic; +signal pc_func_slp_sl_thold_0 : std_ulogic; +signal pc_func_slp_sl_thold_0_b : std_ulogic; +signal pc_func_sl_force : std_ulogic; +signal pc_func_slp_sl_force : std_ulogic; +signal pc_cfg_sl_thold_1 : std_ulogic; +signal pc_cfg_sl_thold_0 : std_ulogic; +signal pc_cfg_sl_thold_0_b : std_ulogic; +signal pc_cfg_slp_sl_thold_1 : std_ulogic; +signal pc_cfg_slp_sl_thold_0 : std_ulogic; +signal pc_cfg_slp_sl_thold_0_b : std_ulogic; +signal pc_cfg_sl_force : std_ulogic; +signal pc_cfg_slp_sl_force : std_ulogic; +signal pc_func_slp_nsl_thold_1 : std_ulogic; +signal pc_func_slp_nsl_thold_0 : std_ulogic; +signal pc_func_slp_nsl_thold_0_b : std_ulogic; +signal pc_func_slp_nsl_force : std_ulogic; +signal lcb_dclk : std_ulogic; +signal lcb_lclk : clk_logic; +signal siv_0 : std_ulogic_vector(0 to scan_right_0); +signal sov_0 : std_ulogic_vector(0 to scan_right_0); +signal siv_1 : std_ulogic_vector(0 to scan_right_1); +signal sov_1 : std_ulogic_vector(0 to scan_right_1); +signal bsiv : std_ulogic_vector(0 to boot_scan_right); +signal bsov : std_ulogic_vector(0 to boot_scan_right); +signal mmucfg_q, mmucfg_q_b : std_ulogic_vector(47 to 48); +signal tlb0cfg_q, tlb0cfg_q_b : std_ulogic_vector(45 to 47); +signal bcfg_spare_q, bcfg_spare_q_b : std_ulogic_vector(0 to 15); +signal cat_emf_act_d, cat_emf_act_q : std_ulogic_vector(0 to thdid_width-1); +signal spr_mmu_act_d, spr_mmu_act_q : std_ulogic_vector(0 to thdid_width); +signal spr_val_act_d, spr_val_act_q : std_ulogic_vector(0 to 3); +signal spr_val_act, spr_match_act, spr_match_mas_act, spr_mas_data_out_act : std_ulogic; +signal cswitch_q : std_ulogic_vector(0 to 3); +signal tidn : std_ulogic; +signal tiup : std_ulogic; +begin +tidn <= '0'; +tiup <= '1'; +cat_emf_act_d(0) <= (spr_match_any_mmu and Eq(spr_etid_in_q, "00")) or mmucr2_act_override(6) or (tlb_delayed_act(29+0) and xu_mm_ccr2_notlb_b); +spr_mmu_act_d(0) <= (spr_match_any_mmu and Eq(spr_etid_in_q, "00")) or mmucr2_act_override(5); +cat_emf_act_d(1) <= (spr_match_any_mmu and Eq(spr_etid_in_q, "01")) or mmucr2_act_override(6) or (tlb_delayed_act(29+1) and xu_mm_ccr2_notlb_b); +spr_mmu_act_d(1) <= (spr_match_any_mmu and Eq(spr_etid_in_q, "01")) or mmucr2_act_override(5); +cat_emf_act_d(2) <= (spr_match_any_mmu and Eq(spr_etid_in_q, "10")) or mmucr2_act_override(6) or (tlb_delayed_act(29+2) and xu_mm_ccr2_notlb_b); +spr_mmu_act_d(2) <= (spr_match_any_mmu and Eq(spr_etid_in_q, "10")) or mmucr2_act_override(5); +cat_emf_act_d(3) <= (spr_match_any_mmu and Eq(spr_etid_in_q, "11")) or mmucr2_act_override(6) or (tlb_delayed_act(29+3) and xu_mm_ccr2_notlb_b); +spr_mmu_act_d(3) <= (spr_match_any_mmu and Eq(spr_etid_in_q, "11")) or mmucr2_act_override(5); +spr_mmu_act_d(thdid_width) <= spr_match_any_mmu or mmucr2_act_override(5); +spr_val_act_d(0) <= xu_mm_slowspr_val; +spr_val_act_d(1) <= spr_val_act_q(0); +spr_val_act_d(2) <= spr_val_act_q(1); +spr_val_act_d(3) <= spr_val_act_q(2); +spr_val_act <= spr_val_act_q(0) or spr_val_act_q(1) or spr_val_act_q(2) or spr_val_act_q(3) or mmucr2_act_override(5); +spr_match_act <= spr_val_act_q(0) or spr_val_act_q(1) or mmucr2_act_override(5); +spr_match_mas_act <= spr_val_act_q(0) or spr_val_act_q(1) or mmucr2_act_override(6); +spr_mas_data_out_act <= spr_val_act_q(0) or mmucr2_act_override(6); +----------------------------------------------------------------------- +-- slow spr +----------------------------------------------------------------------- +-- input latches for spr access +spr_ctl_in_d(0) <= xu_mm_slowspr_val; +spr_ctl_in_d(1) <= xu_mm_slowspr_rw; +spr_ctl_in_d(2) <= xu_mm_slowspr_done; +spr_etid_in_d <= xu_mm_slowspr_etid; +spr_addr_in_d <= xu_mm_slowspr_addr; +spr_addr_in_clone_d <= xu_mm_slowspr_addr; +spr_data_in_d <= xu_mm_slowspr_data; +-- internal select latches for spr access +spr_ctl_int_d <= spr_ctl_in_q; +spr_etid_int_d <= spr_etid_in_q; +spr_addr_int_d <= spr_addr_in_q; +spr_data_int_d <= spr_data_in_q; +spr_match_any_mmu <= ( spr_ctl_in_q(0) and (Eq(spr_addr_in_q, Spr_Addr_PID) or Eq(spr_addr_in_q, Spr_Addr_MMUCR0) or + Eq(spr_addr_in_q, Spr_Addr_MMUCR1) or Eq(spr_addr_in_q, Spr_Addr_MMUCR2) or + Eq(spr_addr_in_q, Spr_Addr_MMUCR3) or Eq(spr_addr_in_q, Spr_Addr_LPID) or + Eq(spr_addr_in_clone_q, Spr_Addr_MAS0) or Eq(spr_addr_in_clone_q, Spr_Addr_MAS1) or + Eq(spr_addr_in_clone_q, Spr_Addr_MAS2) or Eq(spr_addr_in_clone_q, Spr_Addr_MAS3) or + Eq(spr_addr_in_clone_q, Spr_Addr_MAS4) or Eq(spr_addr_in_clone_q, Spr_Addr_MAS5) or + Eq(spr_addr_in_clone_q, Spr_Addr_MAS6) or Eq(spr_addr_in_clone_q, Spr_Addr_MAS7) or + Eq(spr_addr_in_clone_q, Spr_Addr_MAS8) or Eq(spr_addr_in_clone_q, Spr_Addr_MAS2U) or + Eq(spr_addr_in_clone_q, Spr_Addr_MAS01_64b) or Eq(spr_addr_in_clone_q, Spr_Addr_MAS56_64b) or + Eq(spr_addr_in_clone_q, Spr_Addr_MAS73_64b) or Eq(spr_addr_in_clone_q, Spr_Addr_MAS81_64b) or + Eq(spr_addr_in_clone_q, Spr_Addr_MMUCFG) or Eq(spr_addr_in_clone_q, Spr_Addr_MMUCSR0) or + Eq(spr_addr_in_clone_q, Spr_Addr_TLB0CFG) or Eq(spr_addr_in_clone_q, Spr_Addr_TLB0PS) or + Eq(spr_addr_in_clone_q, Spr_Addr_LRATCFG) or Eq(spr_addr_in_clone_q, Spr_Addr_LRATPS) or + Eq(spr_addr_in_clone_q, Spr_Addr_EPTCFG) or Eq(spr_addr_in_clone_q, Spr_Addr_LPER) or + Eq(spr_addr_in_clone_q, Spr_Addr_LPERU)) ); +spr_match_pid0 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "00") and Eq(spr_addr_in_q, Spr_Addr_PID)); +spr_match_pid1 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "01") and Eq(spr_addr_in_q, Spr_Addr_PID)); +spr_match_pid2 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "10") and Eq(spr_addr_in_q, Spr_Addr_PID)); +spr_match_pid3 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "11") and Eq(spr_addr_in_q, Spr_Addr_PID)); +spr_match_mmucr0_0 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "00") and Eq(spr_addr_in_q, Spr_Addr_MMUCR0)); +spr_match_mmucr0_1 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "01") and Eq(spr_addr_in_q, Spr_Addr_MMUCR0)); +spr_match_mmucr0_2 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "10") and Eq(spr_addr_in_q, Spr_Addr_MMUCR0)); +spr_match_mmucr0_3 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "11") and Eq(spr_addr_in_q, Spr_Addr_MMUCR0)); +spr_match_mmucr1 <= (spr_ctl_in_q(0) and Eq(spr_addr_in_q, Spr_Addr_MMUCR1)); +spr_match_mmucr2 <= (spr_ctl_in_q(0) and Eq(spr_addr_in_q, Spr_Addr_MMUCR2)); +spr_match_mmucr3_0 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "00") and Eq(spr_addr_in_q, Spr_Addr_MMUCR3)); +spr_match_mmucr3_1 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "01") and Eq(spr_addr_in_q, Spr_Addr_MMUCR3)); +spr_match_mmucr3_2 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "10") and Eq(spr_addr_in_q, Spr_Addr_MMUCR3)); +spr_match_mmucr3_3 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "11") and Eq(spr_addr_in_q, Spr_Addr_MMUCR3)); +spr_match_lpidr <= (spr_ctl_in_q(0) and Eq(spr_addr_in_q, Spr_Addr_LPID)); +spr_match_mmucsr0 <= (spr_ctl_in_q(0) and Eq(spr_addr_in_clone_q, Spr_Addr_MMUCSR0)); +spr_match_mmucfg <= (spr_ctl_in_q(0) and Eq(spr_addr_in_clone_q, Spr_Addr_MMUCFG)); +spr_match_tlb0cfg <= (spr_ctl_in_q(0) and Eq(spr_addr_in_clone_q, Spr_Addr_TLB0CFG)); +spr_match_tlb0ps <= (spr_ctl_in_q(0) and Eq(spr_addr_in_clone_q, Spr_Addr_TLB0PS)); +spr_match_lratcfg <= (spr_ctl_in_q(0) and Eq(spr_addr_in_clone_q, Spr_Addr_LRATCFG)); +spr_match_lratps <= (spr_ctl_in_q(0) and Eq(spr_addr_in_clone_q, Spr_Addr_LRATPS)); +spr_match_eptcfg <= (spr_ctl_in_q(0) and Eq(spr_addr_in_clone_q, Spr_Addr_EPTCFG)); +spr_match_lper_0 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "00") and Eq(spr_addr_in_clone_q, Spr_Addr_LPER)); +spr_match_lperu_0 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "00") and Eq(spr_addr_in_clone_q, Spr_Addr_LPERU)); +spr_match_lper_1 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "01") and Eq(spr_addr_in_clone_q, Spr_Addr_LPER)); +spr_match_lperu_1 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "01") and Eq(spr_addr_in_clone_q, Spr_Addr_LPERU)); +spr_match_lper_2 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "10") and Eq(spr_addr_in_clone_q, Spr_Addr_LPER)); +spr_match_lperu_2 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "10") and Eq(spr_addr_in_clone_q, Spr_Addr_LPERU)); +spr_match_lper_3 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "11") and Eq(spr_addr_in_clone_q, Spr_Addr_LPER)); +spr_match_lperu_3 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "11") and Eq(spr_addr_in_clone_q, Spr_Addr_LPERU)); +spr_match_any_mas <= ( spr_ctl_in_q(0) and (Eq(spr_addr_in_clone_q, Spr_Addr_MAS0) or Eq(spr_addr_in_clone_q, Spr_Addr_MAS1) or Eq(spr_addr_in_clone_q, Spr_Addr_MAS2) or Eq(spr_addr_in_clone_q, Spr_Addr_MAS2U) or + Eq(spr_addr_in_clone_q, Spr_Addr_MAS3) or Eq(spr_addr_in_clone_q, Spr_Addr_MAS4) or Eq(spr_addr_in_clone_q, Spr_Addr_MAS5) or Eq(spr_addr_in_clone_q, Spr_Addr_MAS6) or + Eq(spr_addr_in_clone_q, Spr_Addr_MAS7) or Eq(spr_addr_in_clone_q, Spr_Addr_MAS8) or Eq(spr_addr_in_clone_q, Spr_Addr_MAS01_64b) or Eq(spr_addr_in_clone_q, Spr_Addr_MAS56_64b) or + Eq(spr_addr_in_clone_q, Spr_Addr_MAS73_64b) or Eq(spr_addr_in_clone_q, Spr_Addr_MAS81_64b)) ); +spr_match_mas0_0 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "00") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS0)); +spr_match_mas1_0 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "00") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS1)); +spr_match_mas2_0 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "00") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS2)); +spr_match_mas2u_0 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "00") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS2U)); +spr_match_mas3_0 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "00") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS3)); +spr_match_mas4_0 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "00") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS4)); +spr_match_mas5_0 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "00") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS5)); +spr_match_mas6_0 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "00") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS6)); +spr_match_mas7_0 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "00") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS7)); +spr_match_mas8_0 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "00") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS8)); +spr_match_mas01_64b_0 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "00") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS01_64b)); +spr_match_mas56_64b_0 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "00") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS56_64b)); +spr_match_mas73_64b_0 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "00") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS73_64b)); +spr_match_mas81_64b_0 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "00") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS81_64b)); +spr_match_mas0_1 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "01") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS0)); +spr_match_mas1_1 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "01") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS1)); +spr_match_mas2_1 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "01") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS2)); +spr_match_mas2u_1 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "01") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS2U)); +spr_match_mas3_1 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "01") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS3)); +spr_match_mas4_1 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "01") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS4)); +spr_match_mas5_1 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "01") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS5)); +spr_match_mas6_1 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "01") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS6)); +spr_match_mas7_1 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "01") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS7)); +spr_match_mas8_1 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "01") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS8)); +spr_match_mas01_64b_1 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "01") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS01_64b)); +spr_match_mas56_64b_1 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "01") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS56_64b)); +spr_match_mas73_64b_1 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "01") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS73_64b)); +spr_match_mas81_64b_1 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "01") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS81_64b)); +spr_match_mas0_2 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "10") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS0)); +spr_match_mas1_2 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "10") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS1)); +spr_match_mas2_2 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "10") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS2)); +spr_match_mas2u_2 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "10") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS2U)); +spr_match_mas3_2 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "10") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS3)); +spr_match_mas4_2 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "10") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS4)); +spr_match_mas5_2 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "10") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS5)); +spr_match_mas6_2 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "10") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS6)); +spr_match_mas7_2 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "10") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS7)); +spr_match_mas8_2 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "10") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS8)); +spr_match_mas01_64b_2 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "10") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS01_64b)); +spr_match_mas56_64b_2 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "10") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS56_64b)); +spr_match_mas73_64b_2 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "10") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS73_64b)); +spr_match_mas81_64b_2 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "10") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS81_64b)); +spr_match_mas0_3 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "11") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS0)); +spr_match_mas1_3 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "11") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS1)); +spr_match_mas2_3 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "11") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS2)); +spr_match_mas2u_3 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "11") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS2U)); +spr_match_mas3_3 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "11") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS3)); +spr_match_mas4_3 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "11") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS4)); +spr_match_mas5_3 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "11") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS5)); +spr_match_mas6_3 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "11") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS6)); +spr_match_mas7_3 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "11") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS7)); +spr_match_mas8_3 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "11") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS8)); +spr_match_mas01_64b_3 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "11") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS01_64b)); +spr_match_mas56_64b_3 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "11") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS56_64b)); +spr_match_mas73_64b_3 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "11") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS73_64b)); +spr_match_mas81_64b_3 <= (spr_ctl_in_q(0) and Eq(spr_etid_in_q, "11") and Eq(spr_addr_in_clone_q, Spr_Addr_MAS81_64b)); +spr_match_mas2_64b <= (spr_ctl_in_q(0) and Eq(spr_addr_in_clone_q, Spr_Addr_MAS2)); +spr_match_mas01_64b <= (spr_ctl_in_q(0) and Eq(spr_addr_in_clone_q, Spr_Addr_MAS01_64b)); +spr_match_mas56_64b <= (spr_ctl_in_q(0) and Eq(spr_addr_in_clone_q, Spr_Addr_MAS56_64b)); +spr_match_mas73_64b <= (spr_ctl_in_q(0) and Eq(spr_addr_in_clone_q, Spr_Addr_MAS73_64b)); +spr_match_mas81_64b <= (spr_ctl_in_q(0) and Eq(spr_addr_in_clone_q, Spr_Addr_MAS81_64b)); +spr_match_64b <= spr_match_mas2_64b or spr_match_mas01_64b or spr_match_mas56_64b or spr_match_mas73_64b or spr_match_mas81_64b; +pid0_d <= spr_data_int_q(64-pid_width to 63) when (spr_match_pid0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) else pid0_q; +pid1_d <= spr_data_int_q(64-pid_width to 63) when (spr_match_pid1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) else pid1_q; +pid2_d <= spr_data_int_q(64-pid_width to 63) when (spr_match_pid2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) else pid2_q; +pid3_d <= spr_data_int_q(64-pid_width to 63) when (spr_match_pid3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) else pid3_q; +-- mmucr0: 0-ExtClass, 1-TID_NZ, 2:3-GS/TS, 4:5-TLBSel, 6:19-TID +mmucr0_0_d <= spr_data_int_q(32) & or_reduce(spr_data_int_q(50 to 63)) & spr_data_int_q(34 to 37) & spr_data_int_q(50 to 63) + when (spr_match_mmucr0_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else xu_mm_derat_mmucr0_q(0 to 3) & "11" & mmucr0_0_q(6 to 7) & xu_mm_derat_mmucr0_q(6 to 17) + when xu_mm_derat_mmucr0_we_q(0)='1' and mmucr1_q(14 to 15)="01" + else xu_mm_derat_mmucr0_q(0 to 3) & "11" & xu_mm_derat_mmucr0_q(4 to 5) & mmucr0_0_q(8 to 11) & xu_mm_derat_mmucr0_q(10 to 17) + when xu_mm_derat_mmucr0_we_q(0)='1' and mmucr1_q(14 to 15)="10" + else xu_mm_derat_mmucr0_q(0 to 3) & "11" & xu_mm_derat_mmucr0_q(4 to 17) + when xu_mm_derat_mmucr0_we_q(0)='1' and mmucr1_q(14 to 15)="11" + else xu_mm_derat_mmucr0_q(0 to 3) & "11" & mmucr0_0_q(6 to 11) & xu_mm_derat_mmucr0_q(10 to 17) + when xu_mm_derat_mmucr0_we_q(0)='1' + else iu_mm_ierat_mmucr0_q(0 to 3) & "11" & mmucr0_0_q(6 to 7) & iu_mm_ierat_mmucr0_q(6 to 17) + when iu_mm_ierat_mmucr0_we_q(0)='1' and mmucr1_q(12 to 13)="01" + else iu_mm_ierat_mmucr0_q(0 to 3) & "11" & iu_mm_ierat_mmucr0_q(4 to 5) & mmucr0_0_q(8 to 11) & iu_mm_ierat_mmucr0_q(10 to 17) + when iu_mm_ierat_mmucr0_we_q(0)='1' and mmucr1_q(12 to 13)="10" + else iu_mm_ierat_mmucr0_q(0 to 3) & "11" & iu_mm_ierat_mmucr0_q(4 to 17) + when iu_mm_ierat_mmucr0_we_q(0)='1' and mmucr1_q(12 to 13)="11" + else iu_mm_ierat_mmucr0_q(0 to 3) & "10" & mmucr0_0_q(6 to 11) & iu_mm_ierat_mmucr0_q(10 to 17) + when iu_mm_ierat_mmucr0_we_q(0)='1' + else mmucr0_0_q; +mmucr0_1_d <= spr_data_int_q(32) & or_reduce(spr_data_int_q(50 to 63)) & spr_data_int_q(34 to 37) & spr_data_int_q(50 to 63) + when (spr_match_mmucr0_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else xu_mm_derat_mmucr0_q(0 to 3) & "11" & mmucr0_1_q(6 to 7) & xu_mm_derat_mmucr0_q(6 to 17) + when xu_mm_derat_mmucr0_we_q(1)='1' and mmucr1_q(14 to 15)="01" + else xu_mm_derat_mmucr0_q(0 to 3) & "11" & xu_mm_derat_mmucr0_q(4 to 5) & mmucr0_1_q(8 to 11) & xu_mm_derat_mmucr0_q(10 to 17) + when xu_mm_derat_mmucr0_we_q(1)='1' and mmucr1_q(14 to 15)="10" + else xu_mm_derat_mmucr0_q(0 to 3) & "11" & xu_mm_derat_mmucr0_q(4 to 17) + when xu_mm_derat_mmucr0_we_q(1)='1' and mmucr1_q(14 to 15)="11" + else xu_mm_derat_mmucr0_q(0 to 3) & "11" & mmucr0_1_q(6 to 11) & xu_mm_derat_mmucr0_q(10 to 17) + when xu_mm_derat_mmucr0_we_q(1)='1' + else iu_mm_ierat_mmucr0_q(0 to 3) & "11" & mmucr0_1_q(6 to 7) & iu_mm_ierat_mmucr0_q(6 to 17) + when iu_mm_ierat_mmucr0_we_q(1)='1' and mmucr1_q(12 to 13)="01" + else iu_mm_ierat_mmucr0_q(0 to 3) & "11" & iu_mm_ierat_mmucr0_q(4 to 5) & mmucr0_1_q(8 to 11) & iu_mm_ierat_mmucr0_q(10 to 17) + when iu_mm_ierat_mmucr0_we_q(1)='1' and mmucr1_q(12 to 13)="10" + else iu_mm_ierat_mmucr0_q(0 to 3) & "11" & iu_mm_ierat_mmucr0_q(4 to 17) + when iu_mm_ierat_mmucr0_we_q(1)='1' and mmucr1_q(12 to 13)="11" + else iu_mm_ierat_mmucr0_q(0 to 3) & "10" & mmucr0_1_q(6 to 11) & iu_mm_ierat_mmucr0_q(10 to 17) + when iu_mm_ierat_mmucr0_we_q(1)='1' + else mmucr0_1_q; +mmucr0_2_d <= spr_data_int_q(32) & or_reduce(spr_data_int_q(50 to 63)) & spr_data_int_q(34 to 37) & spr_data_int_q(50 to 63) + when (spr_match_mmucr0_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else xu_mm_derat_mmucr0_q(0 to 3) & "11" & mmucr0_2_q(6 to 7) & xu_mm_derat_mmucr0_q(6 to 17) + when xu_mm_derat_mmucr0_we_q(2)='1' and mmucr1_q(14 to 15)="01" + else xu_mm_derat_mmucr0_q(0 to 3) & "11" & xu_mm_derat_mmucr0_q(4 to 5) & mmucr0_2_q(8 to 11) & xu_mm_derat_mmucr0_q(10 to 17) + when xu_mm_derat_mmucr0_we_q(2)='1' and mmucr1_q(14 to 15)="10" + else xu_mm_derat_mmucr0_q(0 to 3) & "11" & xu_mm_derat_mmucr0_q(4 to 17) + when xu_mm_derat_mmucr0_we_q(2)='1' and mmucr1_q(14 to 15)="11" + else xu_mm_derat_mmucr0_q(0 to 3) & "11" & mmucr0_2_q(6 to 11) & xu_mm_derat_mmucr0_q(10 to 17) + when xu_mm_derat_mmucr0_we_q(2)='1' + else iu_mm_ierat_mmucr0_q(0 to 3) & "11" & mmucr0_2_q(6 to 7) & iu_mm_ierat_mmucr0_q(6 to 17) + when iu_mm_ierat_mmucr0_we_q(2)='1' and mmucr1_q(12 to 13)="01" + else iu_mm_ierat_mmucr0_q(0 to 3) & "11" & iu_mm_ierat_mmucr0_q(4 to 5) & mmucr0_2_q(8 to 11) & iu_mm_ierat_mmucr0_q(10 to 17) + when iu_mm_ierat_mmucr0_we_q(2)='1' and mmucr1_q(12 to 13)="10" + else iu_mm_ierat_mmucr0_q(0 to 3) & "11" & iu_mm_ierat_mmucr0_q(4 to 17) + when iu_mm_ierat_mmucr0_we_q(2)='1' and mmucr1_q(12 to 13)="11" + else iu_mm_ierat_mmucr0_q(0 to 3) & "10" & mmucr0_2_q(6 to 11) & iu_mm_ierat_mmucr0_q(10 to 17) + when iu_mm_ierat_mmucr0_we_q(2)='1' + else mmucr0_2_q; +mmucr0_3_d <= spr_data_int_q(32) & or_reduce(spr_data_int_q(50 to 63)) & spr_data_int_q(34 to 37) & spr_data_int_q(50 to 63) + when (spr_match_mmucr0_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else xu_mm_derat_mmucr0_q(0 to 3) & "11" & mmucr0_3_q(6 to 7) & xu_mm_derat_mmucr0_q(6 to 17) + when xu_mm_derat_mmucr0_we_q(3)='1' and mmucr1_q(14 to 15)="01" + else xu_mm_derat_mmucr0_q(0 to 3) & "11" & xu_mm_derat_mmucr0_q(4 to 5) & mmucr0_3_q(8 to 11) & xu_mm_derat_mmucr0_q(10 to 17) + when xu_mm_derat_mmucr0_we_q(3)='1' and mmucr1_q(14 to 15)="10" + else xu_mm_derat_mmucr0_q(0 to 3) & "11" & xu_mm_derat_mmucr0_q(4 to 17) + when xu_mm_derat_mmucr0_we_q(3)='1' and mmucr1_q(14 to 15)="11" + else xu_mm_derat_mmucr0_q(0 to 3) & "11" & mmucr0_3_q(6 to 11) & xu_mm_derat_mmucr0_q(10 to 17) + when xu_mm_derat_mmucr0_we_q(3)='1' + else iu_mm_ierat_mmucr0_q(0 to 3) & "11" & mmucr0_3_q(6 to 7) & iu_mm_ierat_mmucr0_q(6 to 17) + when iu_mm_ierat_mmucr0_we_q(3)='1' and mmucr1_q(12 to 13)="01" + else iu_mm_ierat_mmucr0_q(0 to 3) & "11" & iu_mm_ierat_mmucr0_q(4 to 5) & mmucr0_3_q(8 to 11) & iu_mm_ierat_mmucr0_q(10 to 17) + when iu_mm_ierat_mmucr0_we_q(3)='1' and mmucr1_q(12 to 13)="10" + else iu_mm_ierat_mmucr0_q(0 to 3) & "11" & iu_mm_ierat_mmucr0_q(4 to 17) + when iu_mm_ierat_mmucr0_we_q(3)='1' and mmucr1_q(12 to 13)="11" + else iu_mm_ierat_mmucr0_q(0 to 3) & "10" & mmucr0_3_q(6 to 11) & iu_mm_ierat_mmucr0_q(10 to 17) + when iu_mm_ierat_mmucr0_we_q(3)='1' + else mmucr0_3_q; +-- mmucr1: 0-IRRE, 1-DRRE, 2-REE, 3-CEE, +-- 4-Disable any context sync inst from invalidating extclass=0 erat entries, +-- 5-Disable isync inst from invalidating extclass=0 erat entries, +-- 6:7-IPEI, 8:9-DPEI, 10:11-TPEI, 12:13-ICTID/ITTID, 14:15-DCTID/DTTID, +-- 16-DCCD, 17-TLBWE_BINV, 18-TLBI_MSB, 19-TLBI_REJ, +-- 20-IERRDET, 21-DERRDET, 22-TERRDET, 23:31-EEN +-- 2) mmucr1: merge EEN bits into single field, seperate I/D/T ERRDET bits +-- 3) mmucr1: add ICTID, ITTID, DCTID, DTTID, TLBI_REJ, and TLBI_MSB bits +mmucr1_d(0 to 16) <= spr_data_int_q(32 to 48) when (spr_match_mmucr1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) else mmucr1_q(0 to 16); +mmucr1_d(17) <= (spr_data_int_q(49) and not cswitch_q(1)) when (spr_match_mmucr1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) else mmucr1_q(17); +mmucr1_d(18 to 19) <= spr_data_int_q(50 to 51) when (spr_match_mmucr1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) else mmucr1_q(18 to 19); +mmucr1_d(20) <= '0' when (spr_match_mmucr1_q='1' and spr_ctl_int_q(1)=Spr_RW_Read and cswitch_q(0)='0') + else spr_data_int_q(52) when (spr_match_mmucr1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write and cswitch_q(0)='1') + else '1' when (iu_mm_ierat_mmucr1_we_q='1' and xu_mm_derat_mmucr1_we_q='0' and tlb_mmucr1_we='0' and mmucr1_q(20 to 22)="000") + else mmucr1_q(20); +mmucr1_d(21) <= '0' when (spr_match_mmucr1_q='1' and spr_ctl_int_q(1)=Spr_RW_Read and cswitch_q(0)='0') + else spr_data_int_q(53) when (spr_match_mmucr1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write and cswitch_q(0)='1') + else '1' when (xu_mm_derat_mmucr1_we_q='1' and tlb_mmucr1_we='0' and mmucr1_q(20 to 22)="000") + else mmucr1_q(21); +mmucr1_d(22) <= '0' when (spr_match_mmucr1_q='1' and spr_ctl_int_q(1)=Spr_RW_Read and cswitch_q(0)='0') + else spr_data_int_q(54) when (spr_match_mmucr1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write and cswitch_q(0)='1') + else '1' when (tlb_mmucr1_we='1' and mmucr1_q(20 to 22)="000") + else mmucr1_q(22); +mmucr1_d(23 to 31) <= (others => '0') when (spr_match_mmucr1_q='1' and spr_ctl_int_q(1)=Spr_RW_Read and cswitch_q(0)='0') + else spr_data_int_q(55 to 63) when (spr_match_mmucr1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write and cswitch_q(0)='1') + else tlb_mmucr1_een when (tlb_mmucr1_we='1' and mmucr1_q(20 to 22)="000") + else "0000" & xu_mm_derat_mmucr1_q when (xu_mm_derat_mmucr1_we_q='1' and mmucr1_q(20 to 22)="000") + else "00000" & iu_mm_ierat_mmucr1_q when (iu_mm_ierat_mmucr1_we_q='1' and mmucr1_q(20 to 22)="000") + else mmucr1_q(23 to 31); +-- mmucr2: +mmucr2_d(0 to 31) <= spr_data_int_q(32 to 63) when (spr_match_mmucr2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) else mmucr2_q(0 to 31); +-- mmucr3: +mmucr3_0_d <= spr_data_int_q(64-mmucr3_width to 63) when (spr_match_mmucr3_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mmucr3_x & tlb_mmucr3_rc & tlb_mmucr3_extclass & tlb_mmucr3_class & tlb_mmucr3_wlc & tlb_mmucr3_resvattr & '0' & tlb_mmucr3_thdid + when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(0)='1') + else lrat_mmucr3_x & "00" & '0' & '0' & "00" & "00" & '0' & '0' & "1111" + when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(0)='1') + else mmucr3_0_q; +mmucr3_1_d <= spr_data_int_q(64-mmucr3_width to 63) when (spr_match_mmucr3_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mmucr3_x & tlb_mmucr3_rc & tlb_mmucr3_extclass & tlb_mmucr3_class & tlb_mmucr3_wlc & tlb_mmucr3_resvattr & '0' & tlb_mmucr3_thdid + when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(1)='1') + else lrat_mmucr3_x & "00" & '0' & '0' & "00" & "00" & '0' & '0' & "1111" + when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(1)='1') + else mmucr3_1_q; +mmucr3_2_d <= spr_data_int_q(64-mmucr3_width to 63) when (spr_match_mmucr3_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mmucr3_x & tlb_mmucr3_rc & tlb_mmucr3_extclass & tlb_mmucr3_class & tlb_mmucr3_wlc & tlb_mmucr3_resvattr & '0' & tlb_mmucr3_thdid + when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(2)='1') + else lrat_mmucr3_x & "00" & '0' & '0' & "00" & "00" & '0' & '0' & "1111" + when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(2)='1') + else mmucr3_2_q; +mmucr3_3_d <= spr_data_int_q(64-mmucr3_width to 63) when (spr_match_mmucr3_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mmucr3_x & tlb_mmucr3_rc & tlb_mmucr3_extclass & tlb_mmucr3_class & tlb_mmucr3_wlc & tlb_mmucr3_resvattr & '0' & tlb_mmucr3_thdid + when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(3)='1') + else lrat_mmucr3_x & "00" & '0' & '0' & "00" & "00" & '0' & '0' & "1111" + when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(3)='1') + else mmucr3_3_q; +lpidr_d <= spr_data_int_q(64-lpid_width to 63) when (spr_match_lpidr_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) else lpidr_q; +mmucsr0_tlb0fi_d <= '1' when (mmucsr0_tlb0fi_q='0' and spr_match_mmucsr0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write and spr_data_int_q(61)='1') + else '0' when mmq_inval_tlb0fi_done='1' + else mmucsr0_tlb0fi_q; +lper_0_alpn_d(32 to 51) <= spr_data_int_q(32 to 51) when (spr_match_lper_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_lper_lpn(32 to 51) when tlb_lper_we(0)='1' + else lper_0_alpn_q(32 to 51); +gen64_lper_0_alpn: if spr_data_width = 64 generate +lper_0_alpn_d(64-real_addr_width to 31) <= spr_data_int_q(64-real_addr_width to 31) + when (spr_match_lper_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(64-real_addr_width+32 to 63) + when (spr_match_lperu_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_lper_lpn(64-real_addr_width to 31) when tlb_lper_we(0)='1' + else lper_0_alpn_q(64-real_addr_width to 31); +end generate gen64_lper_0_alpn; +gen32_lper_0_alpn: if spr_data_width = 32 generate +lper_0_alpn_d(64-real_addr_width to 31) <= spr_data_int_q(64-real_addr_width+32 to 63) + when (spr_match_lperu_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_lper_lpn(64-real_addr_width to 31) when tlb_lper_we(0)='1' + else lper_0_alpn_q(64-real_addr_width to 31); +end generate gen32_lper_0_alpn; +lper_0_lps_d <= spr_data_int_q(60 to 63) when (spr_match_lper_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_lper_lps(60 to 63) when tlb_lper_we(0)='1' + else lper_0_lps_q; +lper_1_alpn_d(32 to 51) <= spr_data_int_q(32 to 51) when (spr_match_lper_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_lper_lpn(32 to 51) when tlb_lper_we(1)='1' + else lper_1_alpn_q(32 to 51); +gen64_lper_1_alpn: if spr_data_width = 64 generate +lper_1_alpn_d(64-real_addr_width to 31) <= spr_data_int_q(64-real_addr_width to 31) + when (spr_match_lper_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(64-real_addr_width+32 to 63) + when (spr_match_lperu_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_lper_lpn(64-real_addr_width to 31) when tlb_lper_we(1)='1' + else lper_1_alpn_q(64-real_addr_width to 31); +end generate gen64_lper_1_alpn; +gen32_lper_1_alpn: if spr_data_width = 32 generate +lper_1_alpn_d(64-real_addr_width to 31) <= spr_data_int_q(64-real_addr_width+32 to 63) + when (spr_match_lperu_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_lper_lpn(64-real_addr_width to 31) when tlb_lper_we(1)='1' + else lper_1_alpn_q(64-real_addr_width to 31); +end generate gen32_lper_1_alpn; +lper_1_lps_d <= spr_data_int_q(60 to 63) when (spr_match_lper_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_lper_lps(60 to 63) when tlb_lper_we(1)='1' + else lper_1_lps_q; +lper_2_alpn_d(32 to 51) <= spr_data_int_q(32 to 51) when (spr_match_lper_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_lper_lpn(32 to 51) when tlb_lper_we(2)='1' + else lper_2_alpn_q(32 to 51); +gen64_lper_2_alpn: if spr_data_width = 64 generate +lper_2_alpn_d(64-real_addr_width to 31) <= spr_data_int_q(64-real_addr_width to 31) + when (spr_match_lper_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(64-real_addr_width+32 to 63) + when (spr_match_lperu_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_lper_lpn(64-real_addr_width to 31) when tlb_lper_we(2)='1' + else lper_2_alpn_q(64-real_addr_width to 31); +end generate gen64_lper_2_alpn; +gen32_lper_2_alpn: if spr_data_width = 32 generate +lper_2_alpn_d(64-real_addr_width to 31) <= spr_data_int_q(64-real_addr_width+32 to 63) + when (spr_match_lperu_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_lper_lpn(64-real_addr_width to 31) when tlb_lper_we(2)='1' + else lper_2_alpn_q(64-real_addr_width to 31); +end generate gen32_lper_2_alpn; +lper_2_lps_d <= spr_data_int_q(60 to 63) when (spr_match_lper_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_lper_lps(60 to 63) when tlb_lper_we(2)='1' + else lper_2_lps_q; +lper_3_alpn_d(32 to 51) <= spr_data_int_q(32 to 51) when (spr_match_lper_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_lper_lpn(32 to 51) when tlb_lper_we(3)='1' + else lper_3_alpn_q(32 to 51); +gen64_lper_3_alpn: if spr_data_width = 64 generate +lper_3_alpn_d(64-real_addr_width to 31) <= spr_data_int_q(64-real_addr_width to 31) + when (spr_match_lper_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(64-real_addr_width+32 to 63) + when (spr_match_lperu_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_lper_lpn(64-real_addr_width to 31) when tlb_lper_we(3)='1' + else lper_3_alpn_q(64-real_addr_width to 31); +end generate gen64_lper_3_alpn; +gen32_lper_3_alpn: if spr_data_width = 32 generate +lper_3_alpn_d(64-real_addr_width to 31) <= spr_data_int_q(64-real_addr_width+32 to 63) + when (spr_match_lperu_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_lper_lpn(64-real_addr_width to 31) when tlb_lper_we(3)='1' + else lper_3_alpn_q(64-real_addr_width to 31); +end generate gen32_lper_3_alpn; +lper_3_lps_d <= spr_data_int_q(60 to 63) when (spr_match_lper_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_lper_lps(60 to 63) when tlb_lper_we(3)='1' + else lper_3_lps_q; +mas1_0_v_d <= spr_data_int_q(32) when ((spr_match_mas1_0_q='1' or spr_match_mas01_64b_0_q='1' or spr_match_mas81_64b_0_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else '0' when (tlb_mas_tlbsx_miss='1' and tlb_mas_thdid(0)='1') + else '1' when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(0)='1') + else tlb_mas1_v when (tlb_mas_tlbre='1' and tlb_mas_thdid(0)='1') + else '0' when (lrat_mas_tlbsx_miss='1' and lrat_mas_thdid(0)='1') + else '1' when (lrat_mas_tlbsx_hit='1' and lrat_mas_thdid(0)='1') + else lrat_mas1_v when (lrat_mas_tlbre='1' and lrat_mas_thdid(0)='1') + else mas1_0_v_q; +mas1_0_iprot_d <= spr_data_int_q(33) when ((spr_match_mas1_0_q='1' or spr_match_mas01_64b_0_q='1' or spr_match_mas81_64b_0_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else '0' when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(0)='1') + else tlb_mas1_iprot when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(0)='1') + else '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(0)='1') + else mas1_0_iprot_q; +mas1_0_tid_d <= spr_data_int_q(34 to 47) when ((spr_match_mas1_0_q='1' or spr_match_mas01_64b_0_q='1' or spr_match_mas81_64b_0_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else mas6_0_spid_q when ( tlb_mas_tlbsx_miss='1' and tlb_mas_thdid(0)='1') + else tlb_mas1_tid_error when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(0)='1') + else tlb_mas1_tid when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(0)='1') + else (others => '0') when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(0)='1') + else mas1_0_tid_q; +mas1_0_ind_d <= spr_data_int_q(50) when ((spr_match_mas1_0_q='1' or spr_match_mas01_64b_0_q='1' or spr_match_mas81_64b_0_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_0_indd_q when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(0)='1') + else tlb_mas1_ind when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(0)='1') + else '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(0)='1') + else mas1_0_ind_q; +mas1_0_ts_d <= spr_data_int_q(51) when ((spr_match_mas1_0_q='1' or spr_match_mas01_64b_0_q='1' or spr_match_mas81_64b_0_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else mas6_0_sas_q when ( tlb_mas_tlbsx_miss='1' and tlb_mas_thdid(0)='1') + else tlb_mas1_ts_error when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(0)='1') + else tlb_mas1_ts when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(0)='1') + else '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(0)='1') + else mas1_0_ts_q; +mas1_0_tsize_d <= spr_data_int_q(52 to 55) when ((spr_match_mas1_0_q='1' or spr_match_mas01_64b_0_q='1' or spr_match_mas81_64b_0_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_0_tsized_q when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(0)='1') + else tlb_mas1_tsize when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(0)='1') + else lrat_mas1_tsize when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(0)='1') + else mas1_0_tsize_q; +mas2_0_epn_d(32 to 51) <= spr_data_int_q(32 to 51) when (spr_match_mas2_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas2_epn_error(32 to 51) when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(0)='1') + else tlb_mas2_epn(32 to 51) when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(0)='1') + else lrat_mas2_epn(32 to 51) when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(0)='1') + else mas2_0_epn_q(32 to 51); +mas2_0_wimge_d <= spr_data_int_q(59 to 63) when (spr_match_mas2_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_0_wimged_q when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(0)='1') + else tlb_mas2_wimge when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(0)='1') + else (others => '0') when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(0)='1') + else mas2_0_wimge_q; +mas3_0_rpnl_d <= spr_data_int_q(32 to 52) + when ((spr_match_mas3_0_q='1' or spr_match_mas73_64b_0_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else (others => '0') when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(0)='1') + else tlb_mas3_rpnl & (tlb_mas3_usxwr(5) and tlb_mas1_ind) + when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(0)='1') + else lrat_mas3_rpnl & '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(0)='1') + else mas3_0_rpnl_q; +mas3_0_ubits_d <= spr_data_int_q(54 to 57) when ((spr_match_mas3_0_q='1' or spr_match_mas73_64b_0_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else (others => '0') when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(0)='1') + else tlb_mas3_ubits when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(0)='1') + else (others => '0') when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(0)='1') + else mas3_0_ubits_q; +mas3_0_usxwr_d <= spr_data_int_q(58 to 63) when ((spr_match_mas3_0_q='1' or spr_match_mas73_64b_0_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else (others => '0') when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(0)='1') + else (tlb_mas3_usxwr(0 to 4) & (tlb_mas3_usxwr(5) and not tlb_mas1_ind)) when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(0)='1') + else (others => '0') when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(0)='1') + else mas3_0_usxwr_q; +mas4_0_indd_d <= spr_data_int_q(48) when (spr_match_mas4_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_0_indd_q; +mas4_0_tsized_d <= spr_data_int_q(52 to 55) when (spr_match_mas4_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_0_tsized_q; +mas4_0_wimged_d <= spr_data_int_q(59 to 63) when (spr_match_mas4_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_0_wimged_q; +mas6_0_spid_d <= spr_data_int_q(34 to 47) when ((spr_match_mas6_0_q='1' or spr_match_mas56_64b_0_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas6_spid when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(0)='1') + else mas6_0_spid_q; +mas6_0_isize_d <= spr_data_int_q(52 to 55) when ((spr_match_mas6_0_q='1' or spr_match_mas56_64b_0_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_0_tsized_q when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(0)='1') + else mas6_0_isize_q; +mas6_0_sind_d <= spr_data_int_q(62) when ((spr_match_mas6_0_q='1' or spr_match_mas56_64b_0_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_0_indd_q when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(0)='1') + else mas6_0_sind_q; +mas6_0_sas_d <= spr_data_int_q(63) when ((spr_match_mas6_0_q='1' or spr_match_mas56_64b_0_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas6_sas when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(0)='1') + else mas6_0_sas_q; +mas1_1_v_d <= spr_data_int_q(32) when ((spr_match_mas1_1_q='1' or spr_match_mas01_64b_1_q='1' or spr_match_mas81_64b_1_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else '0' when (tlb_mas_tlbsx_miss='1' and tlb_mas_thdid(1)='1') + else '1' when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(1)='1') + else tlb_mas1_v when (tlb_mas_tlbre='1' and tlb_mas_thdid(1)='1') + else '0' when (lrat_mas_tlbsx_miss='1' and lrat_mas_thdid(1)='1') + else '1' when (lrat_mas_tlbsx_hit='1' and lrat_mas_thdid(1)='1') + else lrat_mas1_v when (lrat_mas_tlbre='1' and lrat_mas_thdid(1)='1') + else mas1_1_v_q; +mas1_1_iprot_d <= spr_data_int_q(33) when ((spr_match_mas1_1_q='1' or spr_match_mas01_64b_1_q='1' or spr_match_mas81_64b_1_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else '0' when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(1)='1') + else tlb_mas1_iprot when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(1)='1') + else '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(1)='1') + else mas1_1_iprot_q; +mas1_1_tid_d <= spr_data_int_q(34 to 47) when ((spr_match_mas1_1_q='1' or spr_match_mas01_64b_1_q='1' or spr_match_mas81_64b_1_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else mas6_1_spid_q when ( tlb_mas_tlbsx_miss='1' and tlb_mas_thdid(1)='1') + else tlb_mas1_tid_error when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(1)='1') + else tlb_mas1_tid when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(1)='1') + else (others => '0') when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(1)='1') + else mas1_1_tid_q; +mas1_1_ind_d <= spr_data_int_q(50) when ((spr_match_mas1_1_q='1' or spr_match_mas01_64b_1_q='1' or spr_match_mas81_64b_1_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_1_indd_q when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(1)='1') + else tlb_mas1_ind when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(1)='1') + else '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(1)='1') + else mas1_1_ind_q; +mas1_1_ts_d <= spr_data_int_q(51) when ((spr_match_mas1_1_q='1' or spr_match_mas01_64b_1_q='1' or spr_match_mas81_64b_1_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else mas6_1_sas_q when ( tlb_mas_tlbsx_miss='1' and tlb_mas_thdid(1)='1') + else tlb_mas1_ts_error when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(1)='1') + else tlb_mas1_ts when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(1)='1') + else '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(1)='1') + else mas1_1_ts_q; +mas1_1_tsize_d <= spr_data_int_q(52 to 55) when ((spr_match_mas1_1_q='1' or spr_match_mas01_64b_1_q='1' or spr_match_mas81_64b_1_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_1_tsized_q when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(1)='1') + else tlb_mas1_tsize when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(1)='1') + else lrat_mas1_tsize when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(1)='1') + else mas1_1_tsize_q; +mas2_1_epn_d(32 to 51) <= spr_data_int_q(32 to 51) when (spr_match_mas2_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas2_epn_error(32 to 51) when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(1)='1') + else tlb_mas2_epn(32 to 51) when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(1)='1') + else lrat_mas2_epn(32 to 51) when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(1)='1') + else mas2_1_epn_q(32 to 51); +mas2_1_wimge_d <= spr_data_int_q(59 to 63) when (spr_match_mas2_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_1_wimged_q when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(1)='1') + else tlb_mas2_wimge when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(1)='1') + else (others => '0') when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(1)='1') + else mas2_1_wimge_q; +mas3_1_rpnl_d <= spr_data_int_q(32 to 52) + when ((spr_match_mas3_1_q='1' or spr_match_mas73_64b_1_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else (others => '0') when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(1)='1') + else tlb_mas3_rpnl & (tlb_mas3_usxwr(5) and tlb_mas1_ind) + when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(1)='1') + else lrat_mas3_rpnl & '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(1)='1') + else mas3_1_rpnl_q; +mas3_1_ubits_d <= spr_data_int_q(54 to 57) when ((spr_match_mas3_1_q='1' or spr_match_mas73_64b_1_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else (others => '0') when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(1)='1') + else tlb_mas3_ubits when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(1)='1') + else (others => '0') when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(1)='1') + else mas3_1_ubits_q; +mas3_1_usxwr_d <= spr_data_int_q(58 to 63) when ((spr_match_mas3_1_q='1' or spr_match_mas73_64b_1_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else (others => '0') when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(1)='1') + else (tlb_mas3_usxwr(0 to 4) & (tlb_mas3_usxwr(5) and not tlb_mas1_ind)) when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(1)='1') + else (others => '0') when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(1)='1') + else mas3_1_usxwr_q; +mas4_1_indd_d <= spr_data_int_q(48) when (spr_match_mas4_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_1_indd_q; +mas4_1_tsized_d <= spr_data_int_q(52 to 55) when (spr_match_mas4_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_1_tsized_q; +mas4_1_wimged_d <= spr_data_int_q(59 to 63) when (spr_match_mas4_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_1_wimged_q; +mas6_1_spid_d <= spr_data_int_q(34 to 47) when ((spr_match_mas6_1_q='1' or spr_match_mas56_64b_1_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas6_spid when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(1)='1') + else mas6_1_spid_q; +mas6_1_isize_d <= spr_data_int_q(52 to 55) when ((spr_match_mas6_1_q='1' or spr_match_mas56_64b_1_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_1_tsized_q when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(1)='1') + else mas6_1_isize_q; +mas6_1_sind_d <= spr_data_int_q(62) when ((spr_match_mas6_1_q='1' or spr_match_mas56_64b_1_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_1_indd_q when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(1)='1') + else mas6_1_sind_q; +mas6_1_sas_d <= spr_data_int_q(63) when ((spr_match_mas6_1_q='1' or spr_match_mas56_64b_1_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas6_sas when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(1)='1') + else mas6_1_sas_q; +mas1_2_v_d <= spr_data_int_q(32) when ((spr_match_mas1_2_q='1' or spr_match_mas01_64b_2_q='1' or spr_match_mas81_64b_2_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else '0' when (tlb_mas_tlbsx_miss='1' and tlb_mas_thdid(2)='1') + else '1' when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(2)='1') + else tlb_mas1_v when (tlb_mas_tlbre='1' and tlb_mas_thdid(2)='1') + else '0' when (lrat_mas_tlbsx_miss='1' and lrat_mas_thdid(2)='1') + else '1' when (lrat_mas_tlbsx_hit='1' and lrat_mas_thdid(2)='1') + else lrat_mas1_v when (lrat_mas_tlbre='1' and lrat_mas_thdid(2)='1') + else mas1_2_v_q; +mas1_2_iprot_d <= spr_data_int_q(33) when ((spr_match_mas1_2_q='1' or spr_match_mas01_64b_2_q='1' or spr_match_mas81_64b_2_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else '0' when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(2)='1') + else tlb_mas1_iprot when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(2)='1') + else '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(2)='1') + else mas1_2_iprot_q; +mas1_2_tid_d <= spr_data_int_q(34 to 47) when ((spr_match_mas1_2_q='1' or spr_match_mas01_64b_2_q='1' or spr_match_mas81_64b_2_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else mas6_2_spid_q when ( tlb_mas_tlbsx_miss='1' and tlb_mas_thdid(2)='1') + else tlb_mas1_tid_error when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(2)='1') + else tlb_mas1_tid when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(2)='1') + else (others => '0') when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(2)='1') + else mas1_2_tid_q; +mas1_2_ind_d <= spr_data_int_q(50) when ((spr_match_mas1_2_q='1' or spr_match_mas01_64b_2_q='1' or spr_match_mas81_64b_2_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_2_indd_q when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(2)='1') + else tlb_mas1_ind when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(2)='1') + else '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(2)='1') + else mas1_2_ind_q; +mas1_2_ts_d <= spr_data_int_q(51) when ((spr_match_mas1_2_q='1' or spr_match_mas01_64b_2_q='1' or spr_match_mas81_64b_2_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else mas6_2_sas_q when ( tlb_mas_tlbsx_miss='1' and tlb_mas_thdid(2)='1') + else tlb_mas1_ts_error when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(2)='1') + else tlb_mas1_ts when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(2)='1') + else '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(2)='1') + else mas1_2_ts_q; +mas1_2_tsize_d <= spr_data_int_q(52 to 55) when ((spr_match_mas1_2_q='1' or spr_match_mas01_64b_2_q='1' or spr_match_mas81_64b_2_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_2_tsized_q when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(2)='1') + else tlb_mas1_tsize when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(2)='1') + else lrat_mas1_tsize when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(2)='1') + else mas1_2_tsize_q; +mas2_2_epn_d(32 to 51) <= spr_data_int_q(32 to 51) when (spr_match_mas2_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas2_epn_error(32 to 51) when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(2)='1') + else tlb_mas2_epn(32 to 51) when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(2)='1') + else lrat_mas2_epn(32 to 51) when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(2)='1') + else mas2_2_epn_q(32 to 51); +mas2_2_wimge_d <= spr_data_int_q(59 to 63) when (spr_match_mas2_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_2_wimged_q when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(2)='1') + else tlb_mas2_wimge when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(2)='1') + else (others => '0') when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(2)='1') + else mas2_2_wimge_q; +mas3_2_rpnl_d <= spr_data_int_q(32 to 52) + when ((spr_match_mas3_2_q='1' or spr_match_mas73_64b_2_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else (others => '0') when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(2)='1') + else tlb_mas3_rpnl & (tlb_mas3_usxwr(5) and tlb_mas1_ind) + when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(2)='1') + else lrat_mas3_rpnl & '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(2)='1') + else mas3_2_rpnl_q; +mas3_2_ubits_d <= spr_data_int_q(54 to 57) when ((spr_match_mas3_2_q='1' or spr_match_mas73_64b_2_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else (others => '0') when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(2)='1') + else tlb_mas3_ubits when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(2)='1') + else (others => '0') when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(2)='1') + else mas3_2_ubits_q; +mas3_2_usxwr_d <= spr_data_int_q(58 to 63) when ((spr_match_mas3_2_q='1' or spr_match_mas73_64b_2_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else (others => '0') when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(2)='1') + else (tlb_mas3_usxwr(0 to 4) & (tlb_mas3_usxwr(5) and not tlb_mas1_ind)) when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(2)='1') + else (others => '0') when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(2)='1') + else mas3_2_usxwr_q; +mas4_2_indd_d <= spr_data_int_q(48) when (spr_match_mas4_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_2_indd_q; +mas4_2_tsized_d <= spr_data_int_q(52 to 55) when (spr_match_mas4_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_2_tsized_q; +mas4_2_wimged_d <= spr_data_int_q(59 to 63) when (spr_match_mas4_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_2_wimged_q; +mas6_2_spid_d <= spr_data_int_q(34 to 47) when ((spr_match_mas6_2_q='1' or spr_match_mas56_64b_2_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas6_spid when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(2)='1') + else mas6_2_spid_q; +mas6_2_isize_d <= spr_data_int_q(52 to 55) when ((spr_match_mas6_2_q='1' or spr_match_mas56_64b_2_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_2_tsized_q when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(2)='1') + else mas6_2_isize_q; +mas6_2_sind_d <= spr_data_int_q(62) when ((spr_match_mas6_2_q='1' or spr_match_mas56_64b_2_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_2_indd_q when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(2)='1') + else mas6_2_sind_q; +mas6_2_sas_d <= spr_data_int_q(63) when ((spr_match_mas6_2_q='1' or spr_match_mas56_64b_2_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas6_sas when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(2)='1') + else mas6_2_sas_q; +mas1_3_v_d <= spr_data_int_q(32) when ((spr_match_mas1_3_q='1' or spr_match_mas01_64b_3_q='1' or spr_match_mas81_64b_3_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else '0' when (tlb_mas_tlbsx_miss='1' and tlb_mas_thdid(3)='1') + else '1' when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(3)='1') + else tlb_mas1_v when (tlb_mas_tlbre='1' and tlb_mas_thdid(3)='1') + else '0' when (lrat_mas_tlbsx_miss='1' and lrat_mas_thdid(3)='1') + else '1' when (lrat_mas_tlbsx_hit='1' and lrat_mas_thdid(3)='1') + else lrat_mas1_v when (lrat_mas_tlbre='1' and lrat_mas_thdid(3)='1') + else mas1_3_v_q; +mas1_3_iprot_d <= spr_data_int_q(33) when ((spr_match_mas1_3_q='1' or spr_match_mas01_64b_3_q='1' or spr_match_mas81_64b_3_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else '0' when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(3)='1') + else tlb_mas1_iprot when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(3)='1') + else '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(3)='1') + else mas1_3_iprot_q; +mas1_3_tid_d <= spr_data_int_q(34 to 47) when ((spr_match_mas1_3_q='1' or spr_match_mas01_64b_3_q='1' or spr_match_mas81_64b_3_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else mas6_3_spid_q when ( tlb_mas_tlbsx_miss='1' and tlb_mas_thdid(3)='1') + else tlb_mas1_tid_error when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(3)='1') + else tlb_mas1_tid when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(3)='1') + else (others => '0') when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(3)='1') + else mas1_3_tid_q; +mas1_3_ind_d <= spr_data_int_q(50) when ((spr_match_mas1_3_q='1' or spr_match_mas01_64b_3_q='1' or spr_match_mas81_64b_3_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_3_indd_q when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(3)='1') + else tlb_mas1_ind when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(3)='1') + else '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(3)='1') + else mas1_3_ind_q; +mas1_3_ts_d <= spr_data_int_q(51) when ((spr_match_mas1_3_q='1' or spr_match_mas01_64b_3_q='1' or spr_match_mas81_64b_3_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else mas6_3_sas_q when ( tlb_mas_tlbsx_miss='1' and tlb_mas_thdid(3)='1') + else tlb_mas1_ts_error when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(3)='1') + else tlb_mas1_ts when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(3)='1') + else '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(3)='1') + else mas1_3_ts_q; +mas1_3_tsize_d <= spr_data_int_q(52 to 55) when ((spr_match_mas1_3_q='1' or spr_match_mas01_64b_3_q='1' or spr_match_mas81_64b_3_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_3_tsized_q when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(3)='1') + else tlb_mas1_tsize when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(3)='1') + else lrat_mas1_tsize when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(3)='1') + else mas1_3_tsize_q; +mas2_3_epn_d(32 to 51) <= spr_data_int_q(32 to 51) when (spr_match_mas2_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas2_epn_error(32 to 51) when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(3)='1') + else tlb_mas2_epn(32 to 51) when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(3)='1') + else lrat_mas2_epn(32 to 51) when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(3)='1') + else mas2_3_epn_q(32 to 51); +mas2_3_wimge_d <= spr_data_int_q(59 to 63) when (spr_match_mas2_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_3_wimged_q when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(3)='1') + else tlb_mas2_wimge when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(3)='1') + else (others => '0') when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(3)='1') + else mas2_3_wimge_q; +mas3_3_rpnl_d <= spr_data_int_q(32 to 52) + when ((spr_match_mas3_3_q='1' or spr_match_mas73_64b_3_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else (others => '0') when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(3)='1') + else tlb_mas3_rpnl & (tlb_mas3_usxwr(5) and tlb_mas1_ind) + when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(3)='1') + else lrat_mas3_rpnl & '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(3)='1') + else mas3_3_rpnl_q; +mas3_3_ubits_d <= spr_data_int_q(54 to 57) when ((spr_match_mas3_3_q='1' or spr_match_mas73_64b_3_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else (others => '0') when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(3)='1') + else tlb_mas3_ubits when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(3)='1') + else (others => '0') when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(3)='1') + else mas3_3_ubits_q; +mas3_3_usxwr_d <= spr_data_int_q(58 to 63) when ((spr_match_mas3_3_q='1' or spr_match_mas73_64b_3_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else (others => '0') when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(3)='1') + else (tlb_mas3_usxwr(0 to 4) & (tlb_mas3_usxwr(5) and not tlb_mas1_ind)) when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(3)='1') + else (others => '0') when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(3)='1') + else mas3_3_usxwr_q; +mas4_3_indd_d <= spr_data_int_q(48) when (spr_match_mas4_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_3_indd_q; +mas4_3_tsized_d <= spr_data_int_q(52 to 55) when (spr_match_mas4_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_3_tsized_q; +mas4_3_wimged_d <= spr_data_int_q(59 to 63) when (spr_match_mas4_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_3_wimged_q; +mas6_3_spid_d <= spr_data_int_q(34 to 47) when ((spr_match_mas6_3_q='1' or spr_match_mas56_64b_3_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas6_spid when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(3)='1') + else mas6_3_spid_q; +mas6_3_isize_d <= spr_data_int_q(52 to 55) when ((spr_match_mas6_3_q='1' or spr_match_mas56_64b_3_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_3_tsized_q when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(3)='1') + else mas6_3_isize_q; +mas6_3_sind_d <= spr_data_int_q(62) when ((spr_match_mas6_3_q='1' or spr_match_mas56_64b_3_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else mas4_3_indd_q when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(3)='1') + else mas6_3_sind_q; +mas6_3_sas_d <= spr_data_int_q(63) when ((spr_match_mas6_3_q='1' or spr_match_mas56_64b_3_q='1') and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas6_sas when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(3)='1') + else mas6_3_sas_q; +gen32_mas_d: if spr_data_width = 32 generate +mas0_0_atsel_d <= spr_data_int_q(32) when (spr_match_mas0_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else '0' when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1' or + tlb_mas_tlbsx_hit='1' or tlb_mas_tlbsx_miss='1') and tlb_mas_thdid(0)='1') + else '1' when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbsx_miss='1') and lrat_mas_thdid(0)='1') + else mas0_0_atsel_q; +mas0_0_esel_d <= spr_data_int_q(45 to 47) when (spr_match_mas0_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas0_esel when ( (tlb_mas_tlbsx_hit='1') and tlb_mas_thdid(0)='1') + else (others => '0') when ((tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1' or + tlb_mas_tlbsx_miss='1') and tlb_mas_thdid(0)='1') + else lrat_mas0_esel when ( (lrat_mas_tlbsx_hit='1') and lrat_mas_thdid(0)='1') + else mas0_0_esel_q; +mas0_0_hes_d <= spr_data_int_q(49) when (spr_match_mas0_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else '1' when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1' or + tlb_mas_tlbsx_hit='1' or tlb_mas_tlbsx_miss='1') and tlb_mas_thdid(0)='1') + else mas0_0_hes_q; +mas0_0_wq_d <= spr_data_int_q(50 to 51) when (spr_match_mas0_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else "01" when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1' or + tlb_mas_tlbsx_hit='1' or tlb_mas_tlbsx_miss='1') and tlb_mas_thdid(0)='1') + else "00" when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbsx_miss='1') and lrat_mas_thdid(0)='1') + else mas0_0_wq_q; +mas5_0_sgs_d <= spr_data_int_q(32) when (spr_match_mas5_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas5_0_sgs_q; +mas5_0_slpid_d <= spr_data_int_q(56 to 63) when (spr_match_mas5_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas5_0_slpid_q; +mas7_0_rpnu_d <= spr_data_int_q(54 to 63) when (spr_match_mas7_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else (others => '0') when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(0)='1') + else tlb_mas7_rpnu when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(0)='1') + else lrat_mas7_rpnu when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(0)='1') + else mas7_0_rpnu_q; +mas8_0_tgs_d <= spr_data_int_q(32) when (spr_match_mas8_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas8_tgs when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(0)='1') + else '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(0)='1') + else mas8_0_tgs_q; +mas8_0_vf_d <= spr_data_int_q(33) when (spr_match_mas8_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas8_vf when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(0)='1') + else '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(0)='1') + else mas8_0_vf_q; +mas8_0_tlpid_d <= spr_data_int_q(56 to 63) when (spr_match_mas8_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas8_tlpid when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(0)='1') + else lrat_mas8_tlpid when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(0)='1') + else mas8_0_tlpid_q; +mas0_1_atsel_d <= spr_data_int_q(32) when (spr_match_mas0_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else '0' when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1' or + tlb_mas_tlbsx_hit='1' or tlb_mas_tlbsx_miss='1') and tlb_mas_thdid(1)='1') + else '1' when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbsx_miss='1') and lrat_mas_thdid(1)='1') + else mas0_1_atsel_q; +mas0_1_esel_d <= spr_data_int_q(45 to 47) when (spr_match_mas0_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas0_esel when ( (tlb_mas_tlbsx_hit='1') and tlb_mas_thdid(1)='1') + else (others => '0') when ((tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1' or + tlb_mas_tlbsx_miss='1') and tlb_mas_thdid(1)='1') + else lrat_mas0_esel when ( (lrat_mas_tlbsx_hit='1') and lrat_mas_thdid(1)='1') + else mas0_1_esel_q; +mas0_1_hes_d <= spr_data_int_q(49) when (spr_match_mas0_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else '1' when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1' or + tlb_mas_tlbsx_hit='1' or tlb_mas_tlbsx_miss='1') and tlb_mas_thdid(1)='1') + else mas0_1_hes_q; +mas0_1_wq_d <= spr_data_int_q(50 to 51) when (spr_match_mas0_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else "01" when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1' or + tlb_mas_tlbsx_hit='1' or tlb_mas_tlbsx_miss='1') and tlb_mas_thdid(1)='1') + else "00" when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbsx_miss='1') and lrat_mas_thdid(1)='1') + else mas0_1_wq_q; +mas5_1_sgs_d <= spr_data_int_q(32) when (spr_match_mas5_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas5_1_sgs_q; +mas5_1_slpid_d <= spr_data_int_q(56 to 63) when (spr_match_mas5_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas5_1_slpid_q; +mas7_1_rpnu_d <= spr_data_int_q(54 to 63) when (spr_match_mas7_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else (others => '0') when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(1)='1') + else tlb_mas7_rpnu when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(1)='1') + else lrat_mas7_rpnu when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(1)='1') + else mas7_1_rpnu_q; +mas8_1_tgs_d <= spr_data_int_q(32) when (spr_match_mas8_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas8_tgs when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(1)='1') + else '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(1)='1') + else mas8_1_tgs_q; +mas8_1_vf_d <= spr_data_int_q(33) when (spr_match_mas8_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas8_vf when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(1)='1') + else '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(1)='1') + else mas8_1_vf_q; +mas8_1_tlpid_d <= spr_data_int_q(56 to 63) when (spr_match_mas8_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas8_tlpid when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(1)='1') + else lrat_mas8_tlpid when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(1)='1') + else mas8_1_tlpid_q; +mas0_2_atsel_d <= spr_data_int_q(32) when (spr_match_mas0_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else '0' when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1' or + tlb_mas_tlbsx_hit='1' or tlb_mas_tlbsx_miss='1') and tlb_mas_thdid(2)='1') + else '1' when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbsx_miss='1') and lrat_mas_thdid(2)='1') + else mas0_2_atsel_q; +mas0_2_esel_d <= spr_data_int_q(45 to 47) when (spr_match_mas0_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas0_esel when ( (tlb_mas_tlbsx_hit='1') and tlb_mas_thdid(2)='1') + else (others => '0') when ((tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1' or + tlb_mas_tlbsx_miss='1') and tlb_mas_thdid(2)='1') + else lrat_mas0_esel when ( (lrat_mas_tlbsx_hit='1') and lrat_mas_thdid(2)='1') + else mas0_2_esel_q; +mas0_2_hes_d <= spr_data_int_q(49) when (spr_match_mas0_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else '1' when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1' or + tlb_mas_tlbsx_hit='1' or tlb_mas_tlbsx_miss='1') and tlb_mas_thdid(2)='1') + else mas0_2_hes_q; +mas0_2_wq_d <= spr_data_int_q(50 to 51) when (spr_match_mas0_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else "01" when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1' or + tlb_mas_tlbsx_hit='1' or tlb_mas_tlbsx_miss='1') and tlb_mas_thdid(2)='1') + else "00" when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbsx_miss='1') and lrat_mas_thdid(2)='1') + else mas0_2_wq_q; +mas5_2_sgs_d <= spr_data_int_q(32) when (spr_match_mas5_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas5_2_sgs_q; +mas5_2_slpid_d <= spr_data_int_q(56 to 63) when (spr_match_mas5_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas5_2_slpid_q; +mas7_2_rpnu_d <= spr_data_int_q(54 to 63) when (spr_match_mas7_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else (others => '0') when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(2)='1') + else tlb_mas7_rpnu when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(2)='1') + else lrat_mas7_rpnu when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(2)='1') + else mas7_2_rpnu_q; +mas8_2_tgs_d <= spr_data_int_q(32) when (spr_match_mas8_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas8_tgs when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(2)='1') + else '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(2)='1') + else mas8_2_tgs_q; +mas8_2_vf_d <= spr_data_int_q(33) when (spr_match_mas8_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas8_vf when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(2)='1') + else '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(2)='1') + else mas8_2_vf_q; +mas8_2_tlpid_d <= spr_data_int_q(56 to 63) when (spr_match_mas8_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas8_tlpid when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(2)='1') + else lrat_mas8_tlpid when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(2)='1') + else mas8_2_tlpid_q; +mas0_3_atsel_d <= spr_data_int_q(32) when (spr_match_mas0_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else '0' when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1' or + tlb_mas_tlbsx_hit='1' or tlb_mas_tlbsx_miss='1') and tlb_mas_thdid(3)='1') + else '1' when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbsx_miss='1') and lrat_mas_thdid(3)='1') + else mas0_3_atsel_q; +mas0_3_esel_d <= spr_data_int_q(45 to 47) when (spr_match_mas0_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas0_esel when ( (tlb_mas_tlbsx_hit='1') and tlb_mas_thdid(3)='1') + else (others => '0') when ((tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1' or + tlb_mas_tlbsx_miss='1') and tlb_mas_thdid(3)='1') + else lrat_mas0_esel when ( (lrat_mas_tlbsx_hit='1') and lrat_mas_thdid(3)='1') + else mas0_3_esel_q; +mas0_3_hes_d <= spr_data_int_q(49) when (spr_match_mas0_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else '1' when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1' or + tlb_mas_tlbsx_hit='1' or tlb_mas_tlbsx_miss='1') and tlb_mas_thdid(3)='1') + else mas0_3_hes_q; +mas0_3_wq_d <= spr_data_int_q(50 to 51) when (spr_match_mas0_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else "01" when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1' or + tlb_mas_tlbsx_hit='1' or tlb_mas_tlbsx_miss='1') and tlb_mas_thdid(3)='1') + else "00" when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbsx_miss='1') and lrat_mas_thdid(3)='1') + else mas0_3_wq_q; +mas5_3_sgs_d <= spr_data_int_q(32) when (spr_match_mas5_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas5_3_sgs_q; +mas5_3_slpid_d <= spr_data_int_q(56 to 63) when (spr_match_mas5_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas5_3_slpid_q; +mas7_3_rpnu_d <= spr_data_int_q(54 to 63) when (spr_match_mas7_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else (others => '0') when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(3)='1') + else tlb_mas7_rpnu when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(3)='1') + else lrat_mas7_rpnu when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(3)='1') + else mas7_3_rpnu_q; +mas8_3_tgs_d <= spr_data_int_q(32) when (spr_match_mas8_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas8_tgs when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(3)='1') + else '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(3)='1') + else mas8_3_tgs_q; +mas8_3_vf_d <= spr_data_int_q(33) when (spr_match_mas8_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas8_vf when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(3)='1') + else '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(3)='1') + else mas8_3_vf_q; +mas8_3_tlpid_d <= spr_data_int_q(56 to 63) when (spr_match_mas8_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas8_tlpid when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(3)='1') + else lrat_mas8_tlpid when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(3)='1') + else mas8_3_tlpid_q; +end generate gen32_mas_d; +gen64_mas_d: if spr_data_width = 64 generate +mas0_0_atsel_d <= spr_data_int_q(32) when (spr_match_mas0_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(0) when (spr_match_mas01_64b_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else '0' when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1' or + tlb_mas_tlbsx_hit='1' or tlb_mas_tlbsx_miss='1') and tlb_mas_thdid(0)='1') + else '1' when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbsx_miss='1') and lrat_mas_thdid(0)='1') + else mas0_0_atsel_q; +mas0_0_esel_d <= spr_data_int_q(45 to 47) when (spr_match_mas0_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(13 to 15) when (spr_match_mas01_64b_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas0_esel when ( (tlb_mas_tlbsx_hit='1') and tlb_mas_thdid(0)='1') + else (others => '0') when ((tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' + or tlb_mas_itlb_error='1') and tlb_mas_thdid(0)='1') + else lrat_mas0_esel when ( (lrat_mas_tlbsx_hit='1') and lrat_mas_thdid(0)='1') + else mas0_0_esel_q; +mas0_0_hes_d <= spr_data_int_q(49) when (spr_match_mas0_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(17) when (spr_match_mas01_64b_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else '1' when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1' or + tlb_mas_tlbsx_hit='1' or tlb_mas_tlbsx_miss='1') and tlb_mas_thdid(0)='1') + else mas0_0_hes_q; +mas0_0_wq_d <= spr_data_int_q(50 to 51) when (spr_match_mas0_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(18 to 19) when (spr_match_mas01_64b_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else "01" when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1' or + tlb_mas_tlbsx_hit='1' or tlb_mas_tlbsx_miss='1') and tlb_mas_thdid(0)='1') + else "00" when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbsx_miss='1') and lrat_mas_thdid(0)='1') + else mas0_0_wq_q; +mas2_0_epn_d(0 to 31) <= spr_data_int_q(32 to 63) when (spr_match_mas2u_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(0 to 31) when (spr_match_mas2_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas2_epn_error(0 to 31) when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(0)='1') + else tlb_mas2_epn(0 to 31) when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(0)='1') + else lrat_mas2_epn(0 to 31) when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(0)='1') + else mas2_0_epn_q(0 to 31); +mas5_0_sgs_d <= spr_data_int_q(32) when (spr_match_mas5_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(0) when (spr_match_mas56_64b_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas5_0_sgs_q; +mas5_0_slpid_d <= spr_data_int_q(56 to 63) when (spr_match_mas5_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(24 to 31) when (spr_match_mas56_64b_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas5_0_slpid_q; +mas7_0_rpnu_d <= spr_data_int_q(54 to 63) when (spr_match_mas7_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else (others => '0') when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(0)='1') + else spr_data_int_q(22 to 31) when (spr_match_mas73_64b_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas7_rpnu when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(0)='1') + else lrat_mas7_rpnu when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(0)='1') + else mas7_0_rpnu_q; +mas8_0_tgs_d <= spr_data_int_q(32) when (spr_match_mas8_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(0) when (spr_match_mas81_64b_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas8_tgs when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(0)='1') + else '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(0)='1') + else mas8_0_tgs_q; +mas8_0_vf_d <= spr_data_int_q(33) when (spr_match_mas8_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(1) when (spr_match_mas81_64b_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas8_vf when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(0)='1') + else '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(0)='1') + else mas8_0_vf_q; +mas8_0_tlpid_d <= spr_data_int_q(56 to 63) when (spr_match_mas8_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(24 to 31) when (spr_match_mas81_64b_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas8_tlpid when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(0)='1') + else lrat_mas8_tlpid when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(0)='1') + else mas8_0_tlpid_q; +mas0_1_atsel_d <= spr_data_int_q(32) when (spr_match_mas0_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(0) when (spr_match_mas01_64b_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else '0' when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1' or + tlb_mas_tlbsx_hit='1' or tlb_mas_tlbsx_miss='1') and tlb_mas_thdid(1)='1') + else '1' when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbsx_miss='1') and lrat_mas_thdid(1)='1') + else mas0_1_atsel_q; +mas0_1_esel_d <= spr_data_int_q(45 to 47) when (spr_match_mas0_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(13 to 15) when (spr_match_mas01_64b_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas0_esel when ( (tlb_mas_tlbsx_hit='1') and tlb_mas_thdid(1)='1') + else (others => '0') when ((tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' + or tlb_mas_itlb_error='1') and tlb_mas_thdid(1)='1') + else lrat_mas0_esel when ( (lrat_mas_tlbsx_hit='1') and lrat_mas_thdid(1)='1') + else mas0_1_esel_q; +mas0_1_hes_d <= spr_data_int_q(49) when (spr_match_mas0_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(17) when (spr_match_mas01_64b_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else '1' when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1' or + tlb_mas_tlbsx_hit='1' or tlb_mas_tlbsx_miss='1') and tlb_mas_thdid(1)='1') + else mas0_1_hes_q; +mas0_1_wq_d <= spr_data_int_q(50 to 51) when (spr_match_mas0_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(18 to 19) when (spr_match_mas01_64b_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else "01" when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1' or + tlb_mas_tlbsx_hit='1' or tlb_mas_tlbsx_miss='1') and tlb_mas_thdid(1)='1') + else "00" when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbsx_miss='1') and lrat_mas_thdid(1)='1') + else mas0_1_wq_q; +mas2_1_epn_d(0 to 31) <= spr_data_int_q(32 to 63) when (spr_match_mas2u_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(0 to 31) when (spr_match_mas2_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas2_epn_error(0 to 31) when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(1)='1') + else tlb_mas2_epn(0 to 31) when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(1)='1') + else lrat_mas2_epn(0 to 31) when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(1)='1') + else mas2_1_epn_q(0 to 31); +mas5_1_sgs_d <= spr_data_int_q(32) when (spr_match_mas5_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(0) when (spr_match_mas56_64b_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas5_1_sgs_q; +mas5_1_slpid_d <= spr_data_int_q(56 to 63) when (spr_match_mas5_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(24 to 31) when (spr_match_mas56_64b_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas5_1_slpid_q; +mas7_1_rpnu_d <= spr_data_int_q(54 to 63) when (spr_match_mas7_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else (others => '0') when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(1)='1') + else spr_data_int_q(22 to 31) when (spr_match_mas73_64b_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas7_rpnu when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(1)='1') + else lrat_mas7_rpnu when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(1)='1') + else mas7_1_rpnu_q; +mas8_1_tgs_d <= spr_data_int_q(32) when (spr_match_mas8_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(0) when (spr_match_mas81_64b_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas8_tgs when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(1)='1') + else '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(1)='1') + else mas8_1_tgs_q; +mas8_1_vf_d <= spr_data_int_q(33) when (spr_match_mas8_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(1) when (spr_match_mas81_64b_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas8_vf when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(1)='1') + else '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(1)='1') + else mas8_1_vf_q; +mas8_1_tlpid_d <= spr_data_int_q(56 to 63) when (spr_match_mas8_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(24 to 31) when (spr_match_mas81_64b_1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas8_tlpid when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(1)='1') + else lrat_mas8_tlpid when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(1)='1') + else mas8_1_tlpid_q; +mas0_2_atsel_d <= spr_data_int_q(32) when (spr_match_mas0_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(0) when (spr_match_mas01_64b_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else '0' when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1' or + tlb_mas_tlbsx_hit='1' or tlb_mas_tlbsx_miss='1') and tlb_mas_thdid(2)='1') + else '1' when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbsx_miss='1') and lrat_mas_thdid(2)='1') + else mas0_2_atsel_q; +mas0_2_esel_d <= spr_data_int_q(45 to 47) when (spr_match_mas0_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(13 to 15) when (spr_match_mas01_64b_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas0_esel when ( (tlb_mas_tlbsx_hit='1') and tlb_mas_thdid(2)='1') + else (others => '0') when ((tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' + or tlb_mas_itlb_error='1') and tlb_mas_thdid(2)='1') + else lrat_mas0_esel when ( (lrat_mas_tlbsx_hit='1') and lrat_mas_thdid(2)='1') + else mas0_2_esel_q; +mas0_2_hes_d <= spr_data_int_q(49) when (spr_match_mas0_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(17) when (spr_match_mas01_64b_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else '1' when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1' or + tlb_mas_tlbsx_hit='1' or tlb_mas_tlbsx_miss='1') and tlb_mas_thdid(2)='1') + else mas0_2_hes_q; +mas0_2_wq_d <= spr_data_int_q(50 to 51) when (spr_match_mas0_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(18 to 19) when (spr_match_mas01_64b_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else "01" when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1' or + tlb_mas_tlbsx_hit='1' or tlb_mas_tlbsx_miss='1') and tlb_mas_thdid(2)='1') + else "00" when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbsx_miss='1') and lrat_mas_thdid(2)='1') + else mas0_2_wq_q; +mas2_2_epn_d(0 to 31) <= spr_data_int_q(32 to 63) when (spr_match_mas2u_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(0 to 31) when (spr_match_mas2_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas2_epn_error(0 to 31) when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(2)='1') + else tlb_mas2_epn(0 to 31) when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(2)='1') + else lrat_mas2_epn(0 to 31) when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(2)='1') + else mas2_2_epn_q(0 to 31); +mas5_2_sgs_d <= spr_data_int_q(32) when (spr_match_mas5_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(0) when (spr_match_mas56_64b_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas5_2_sgs_q; +mas5_2_slpid_d <= spr_data_int_q(56 to 63) when (spr_match_mas5_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(24 to 31) when (spr_match_mas56_64b_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas5_2_slpid_q; +mas7_2_rpnu_d <= spr_data_int_q(54 to 63) when (spr_match_mas7_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else (others => '0') when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(2)='1') + else spr_data_int_q(22 to 31) when (spr_match_mas73_64b_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas7_rpnu when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(2)='1') + else lrat_mas7_rpnu when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(2)='1') + else mas7_2_rpnu_q; +mas8_2_tgs_d <= spr_data_int_q(32) when (spr_match_mas8_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(0) when (spr_match_mas81_64b_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas8_tgs when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(2)='1') + else '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(2)='1') + else mas8_2_tgs_q; +mas8_2_vf_d <= spr_data_int_q(33) when (spr_match_mas8_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(1) when (spr_match_mas81_64b_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas8_vf when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(2)='1') + else '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(2)='1') + else mas8_2_vf_q; +mas8_2_tlpid_d <= spr_data_int_q(56 to 63) when (spr_match_mas8_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(24 to 31) when (spr_match_mas81_64b_2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas8_tlpid when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(2)='1') + else lrat_mas8_tlpid when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(2)='1') + else mas8_2_tlpid_q; +mas0_3_atsel_d <= spr_data_int_q(32) when (spr_match_mas0_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(0) when (spr_match_mas01_64b_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else '0' when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1' or + tlb_mas_tlbsx_hit='1' or tlb_mas_tlbsx_miss='1') and tlb_mas_thdid(3)='1') + else '1' when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbsx_miss='1') and lrat_mas_thdid(3)='1') + else mas0_3_atsel_q; +mas0_3_esel_d <= spr_data_int_q(45 to 47) when (spr_match_mas0_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(13 to 15) when (spr_match_mas01_64b_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas0_esel when ( (tlb_mas_tlbsx_hit='1') and tlb_mas_thdid(3)='1') + else (others => '0') when ((tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' + or tlb_mas_itlb_error='1') and tlb_mas_thdid(3)='1') + else lrat_mas0_esel when ( (lrat_mas_tlbsx_hit='1') and lrat_mas_thdid(3)='1') + else mas0_3_esel_q; +mas0_3_hes_d <= spr_data_int_q(49) when (spr_match_mas0_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(17) when (spr_match_mas01_64b_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else '1' when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1' or + tlb_mas_tlbsx_hit='1' or tlb_mas_tlbsx_miss='1') and tlb_mas_thdid(3)='1') + else mas0_3_hes_q; +mas0_3_wq_d <= spr_data_int_q(50 to 51) when (spr_match_mas0_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(18 to 19) when (spr_match_mas01_64b_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else "01" when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1' or + tlb_mas_tlbsx_hit='1' or tlb_mas_tlbsx_miss='1') and tlb_mas_thdid(3)='1') + else "00" when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbsx_miss='1') and lrat_mas_thdid(3)='1') + else mas0_3_wq_q; +mas2_3_epn_d(0 to 31) <= spr_data_int_q(32 to 63) when (spr_match_mas2u_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(0 to 31) when (spr_match_mas2_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas2_epn_error(0 to 31) when ( (tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(3)='1') + else tlb_mas2_epn(0 to 31) when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(3)='1') + else lrat_mas2_epn(0 to 31) when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(3)='1') + else mas2_3_epn_q(0 to 31); +mas5_3_sgs_d <= spr_data_int_q(32) when (spr_match_mas5_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(0) when (spr_match_mas56_64b_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas5_3_sgs_q; +mas5_3_slpid_d <= spr_data_int_q(56 to 63) when (spr_match_mas5_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(24 to 31) when (spr_match_mas56_64b_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else mas5_3_slpid_q; +mas7_3_rpnu_d <= spr_data_int_q(54 to 63) when (spr_match_mas7_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else (others => '0') when ( (tlb_mas_tlbsx_miss='1' or tlb_mas_dtlb_error='1' or tlb_mas_itlb_error='1') and tlb_mas_thdid(3)='1') + else spr_data_int_q(22 to 31) when (spr_match_mas73_64b_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas7_rpnu when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(3)='1') + else lrat_mas7_rpnu when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(3)='1') + else mas7_3_rpnu_q; +mas8_3_tgs_d <= spr_data_int_q(32) when (spr_match_mas8_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(0) when (spr_match_mas81_64b_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas8_tgs when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(3)='1') + else '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(3)='1') + else mas8_3_tgs_q; +mas8_3_vf_d <= spr_data_int_q(33) when (spr_match_mas8_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(1) when (spr_match_mas81_64b_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas8_vf when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(3)='1') + else '0' when ((lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(3)='1') + else mas8_3_vf_q; +mas8_3_tlpid_d <= spr_data_int_q(56 to 63) when (spr_match_mas8_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else spr_data_int_q(24 to 31) when (spr_match_mas81_64b_3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) + else tlb_mas8_tlpid when ( (tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(3)='1') + else lrat_mas8_tlpid when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(3)='1') + else mas8_3_tlpid_q; +end generate gen64_mas_d; +-- 0: val, 1: rw, 2: done +spr_ctl_out_d(0) <= spr_ctl_int_q(0); +spr_ctl_out_d(1) <= spr_ctl_int_q(1); +spr_ctl_out_d(2) <= spr_ctl_int_q(2) or spr_match_any_mmu_q; +spr_etid_out_d <= spr_etid_int_q; +spr_addr_out_d <= spr_addr_int_q; +spr_data_out_d(32 to 63) <= + ( ((32 to 63-pid_width => '0') & pid0_q) and (32 to 63 => (spr_match_pid0_q and spr_ctl_int_q(1))) ) or + ( ((32 to 63-pid_width => '0') & pid1_q) and (32 to 63 => (spr_match_pid1_q and spr_ctl_int_q(1))) ) or + ( ((32 to 63-pid_width => '0') & pid2_q) and (32 to 63 => (spr_match_pid2_q and spr_ctl_int_q(1))) ) or + ( ((32 to 63-pid_width => '0') & pid3_q) and (32 to 63 => (spr_match_pid3_q and spr_ctl_int_q(1))) ) or + ( ((32 to 55 => '0') & lpidr_q) and (32 to 63 => (spr_match_lpidr_q and spr_ctl_int_q(1))) ) or + ( (mmucr0_0_q(0 to 5) & (38 to 49 => '0') & mmucr0_0_q(6 to 19)) and (32 to 63 => (spr_match_mmucr0_0_q and spr_ctl_int_q(1))) ) or + ( (mmucr0_1_q(0 to 5) & (38 to 49 => '0') & mmucr0_1_q(6 to 19)) and (32 to 63 => (spr_match_mmucr0_1_q and spr_ctl_int_q(1))) ) or + ( (mmucr0_2_q(0 to 5) & (38 to 49 => '0') & mmucr0_2_q(6 to 19)) and (32 to 63 => (spr_match_mmucr0_2_q and spr_ctl_int_q(1))) ) or + ( (mmucr0_3_q(0 to 5) & (38 to 49 => '0') & mmucr0_3_q(6 to 19)) and (32 to 63 => (spr_match_mmucr0_3_q and spr_ctl_int_q(1))) ) or + ( mmucr1_q and (32 to 63 => (spr_match_mmucr1_q and spr_ctl_int_q(1))) ) or + ( mmucr2_q and (32 to 63 => (spr_match_mmucr2_q and spr_ctl_int_q(1))) ) or + ( ((32 to 63-mmucr3_width => '0') & mmucr3_0_q(64-mmucr3_width to 58) & '0' & mmucr3_0_q(60 to 63)) and (32 to 63 => (spr_match_mmucr3_0_q and spr_ctl_int_q(1))) ) or + ( ((32 to 63-mmucr3_width => '0') & mmucr3_1_q(64-mmucr3_width to 58) & '0' & mmucr3_1_q(60 to 63)) and (32 to 63 => (spr_match_mmucr3_1_q and spr_ctl_int_q(1))) ) or + ( ((32 to 63-mmucr3_width => '0') & mmucr3_2_q(64-mmucr3_width to 58) & '0' & mmucr3_2_q(60 to 63)) and (32 to 63 => (spr_match_mmucr3_2_q and spr_ctl_int_q(1))) ) or + ( ((32 to 63-mmucr3_width => '0') & mmucr3_3_q(64-mmucr3_width to 58) & '0' & mmucr3_3_q(60 to 63)) and (32 to 63 => (spr_match_mmucr3_3_q and spr_ctl_int_q(1))) ) or + ( ((32 to 60 => '0') & mmucsr0_tlb0fi_q & "00") and (32 to 63 => (spr_match_mmucsr0_q and spr_ctl_int_q(1))) ) or + ( (Spr_Data_MMUCFG(32 to 46) & mmucfg_q(47 to 48) & Spr_Data_MMUCFG(49 to 63)) and (32 to 63 => (spr_match_mmucfg_q and spr_ctl_int_q(1))) ) or + ( (Spr_Data_TLB0CFG(32 to 44) & tlb0cfg_q(45 to 47) & Spr_Data_TLB0CFG(48 to 63)) and (32 to 63 => (spr_match_tlb0cfg_q and spr_ctl_int_q(1))) ) or + ( (Spr_Data_TLB0PS) and (32 to 63 => (spr_match_tlb0ps_q and spr_ctl_int_q(1))) ) or + ( (Spr_Data_LRATCFG) and (32 to 63 => (spr_match_lratcfg_q and spr_ctl_int_q(1))) ) or + ( (Spr_Data_LRATPS) and (32 to 63 => (spr_match_lratps_q and spr_ctl_int_q(1))) ) or + ( (Spr_Data_EPTCFG) and (32 to 63 => (spr_match_eptcfg_q and spr_ctl_int_q(1))) ) or + ( (lper_0_alpn_q(32 to 51) & (52 to 59 => '0') & lper_0_lps_q(60 to 63)) and (32 to 63 => (spr_match_lper_0_q and spr_ctl_int_q(1))) ) or + ( (lper_1_alpn_q(32 to 51) & (52 to 59 => '0') & lper_1_lps_q(60 to 63)) and (32 to 63 => (spr_match_lper_1_q and spr_ctl_int_q(1))) ) or + ( (lper_2_alpn_q(32 to 51) & (52 to 59 => '0') & lper_2_lps_q(60 to 63)) and (32 to 63 => (spr_match_lper_2_q and spr_ctl_int_q(1))) ) or + ( (lper_3_alpn_q(32 to 51) & (52 to 59 => '0') & lper_3_lps_q(60 to 63)) and (32 to 63 => (spr_match_lper_3_q and spr_ctl_int_q(1))) ) or + ( ((32 to 63-real_addr_width+32 => '0') & lper_0_alpn_q(64-real_addr_width to 31)) and (32 to 63 => (spr_match_lperu_0_q and spr_ctl_int_q(1))) ) or + ( ((32 to 63-real_addr_width+32 => '0') & lper_1_alpn_q(64-real_addr_width to 31)) and (32 to 63 => (spr_match_lperu_1_q and spr_ctl_int_q(1))) ) or + ( ((32 to 63-real_addr_width+32 => '0') & lper_2_alpn_q(64-real_addr_width to 31)) and (32 to 63 => (spr_match_lperu_2_q and spr_ctl_int_q(1))) ) or + ( ((32 to 63-real_addr_width+32 => '0') & lper_3_alpn_q(64-real_addr_width to 31)) and (32 to 63 => (spr_match_lperu_3_q and spr_ctl_int_q(1))) ) or + ( (spr_mas_data_out_q(32 to 63)) and (32 to 63 => (spr_match_any_mas_q and spr_ctl_int_q(1))) ) or + ( spr_data_int_q(32 to 63) and (32 to 63 => not spr_match_any_mmu_q) ); +spr_mas_data_out(32 to 63) <= + ( (mas0_0_atsel_q & (33 to 44 => '0') & mas0_0_esel_q & '0' & mas0_0_hes_q & mas0_0_wq_q & (52 to 63 => '0')) + and (32 to 63 => spr_match_mas0_0) ) or + ( (mas1_0_v_q & mas1_0_iprot_q & mas1_0_tid_q & "00" & mas1_0_ind_q & mas1_0_ts_q & mas1_0_tsize_q & "00000000") + and (32 to 63 => (spr_match_mas1_0 or spr_match_mas01_64b_0 or spr_match_mas81_64b_0)) ) or + ( (mas2_0_epn_q(32 to 51) & "0000000" & mas2_0_wimge_q) + and (32 to 63 => spr_match_mas2_0) ) or + ( (mas2_0_epn_q(0 to 31) ) + and (32 to 63 => spr_match_mas2u_0) ) or + ( (mas3_0_rpnl_q & '0' & mas3_0_ubits_q & mas3_0_usxwr_q) + and (32 to 63 => (spr_match_mas3_0 or spr_match_mas73_64b_0)) ) or + ( ((32 to 47 => '0') & mas4_0_indd_q & "000" & mas4_0_tsized_q & "000" & mas4_0_wimged_q) + and (32 to 63 => spr_match_mas4_0) ) or + ( (mas5_0_sgs_q & (33 to 55 => '0') & mas5_0_slpid_q) + and (32 to 63 => spr_match_mas5_0) ) or + ( ("00" & mas6_0_spid_q & "0000" & mas6_0_isize_q & "000000" & mas6_0_sind_q & mas6_0_sas_q) + and (32 to 63 => (spr_match_mas6_0 or spr_match_mas56_64b_0)) ) or + ( ((32 to 53 => '0') & mas7_0_rpnu_q) + and (32 to 63 => spr_match_mas7_0) ) or + ( (mas8_0_tgs_q & mas8_0_vf_q & (34 to 55 => '0') & mas8_0_tlpid_q) + and (32 to 63 => spr_match_mas8_0) ) or + ( (mas0_1_atsel_q & (33 to 44 => '0') & mas0_1_esel_q & '0' & mas0_1_hes_q & mas0_1_wq_q & (52 to 63 => '0')) + and (32 to 63 => spr_match_mas0_1) ) or + ( (mas1_1_v_q & mas1_1_iprot_q & mas1_1_tid_q & "00" & mas1_1_ind_q & mas1_1_ts_q & mas1_1_tsize_q & "00000000") + and (32 to 63 => (spr_match_mas1_1 or spr_match_mas01_64b_1 or spr_match_mas81_64b_1)) ) or + ( (mas2_1_epn_q(32 to 51) & "0000000" & mas2_1_wimge_q) + and (32 to 63 => spr_match_mas2_1) ) or + ( (mas2_1_epn_q(0 to 31) ) + and (32 to 63 => spr_match_mas2u_1) ) or + ( (mas3_1_rpnl_q & '0' & mas3_1_ubits_q & mas3_1_usxwr_q) + and (32 to 63 => (spr_match_mas3_1 or spr_match_mas73_64b_1)) ) or + ( ((32 to 47 => '0') & mas4_1_indd_q & "000" & mas4_1_tsized_q & "000" & mas4_1_wimged_q) + and (32 to 63 => spr_match_mas4_1) ) or + ( (mas5_1_sgs_q & (33 to 55 => '0') & mas5_1_slpid_q) + and (32 to 63 => spr_match_mas5_1) ) or + ( ("00" & mas6_1_spid_q & "0000" & mas6_1_isize_q & "000000" & mas6_1_sind_q & mas6_1_sas_q) + and (32 to 63 => (spr_match_mas6_1 or spr_match_mas56_64b_1)) ) or + ( ((32 to 53 => '0') & mas7_1_rpnu_q) + and (32 to 63 => spr_match_mas7_1) ) or + ( (mas8_1_tgs_q & mas8_1_vf_q & (34 to 55 => '0') & mas8_1_tlpid_q) + and (32 to 63 => spr_match_mas8_1) ) or + ( (mas0_2_atsel_q & (33 to 44 => '0') & mas0_2_esel_q & '0' & mas0_2_hes_q & mas0_2_wq_q & (52 to 63 => '0')) + and (32 to 63 => spr_match_mas0_2) ) or + ( (mas1_2_v_q & mas1_2_iprot_q & mas1_2_tid_q & "00" & mas1_2_ind_q & mas1_2_ts_q & mas1_2_tsize_q & "00000000") + and (32 to 63 => (spr_match_mas1_2 or spr_match_mas01_64b_2 or spr_match_mas81_64b_2)) ) or + ( (mas2_2_epn_q(32 to 51) & "0000000" & mas2_2_wimge_q) + and (32 to 63 => spr_match_mas2_2) ) or + ( (mas2_2_epn_q(0 to 31) ) + and (32 to 63 => spr_match_mas2u_2) ) or + ( (mas3_2_rpnl_q & '0' & mas3_2_ubits_q & mas3_2_usxwr_q) + and (32 to 63 => (spr_match_mas3_2 or spr_match_mas73_64b_2)) ) or + ( ((32 to 47 => '0') & mas4_2_indd_q & "000" & mas4_2_tsized_q & "000" & mas4_2_wimged_q) + and (32 to 63 => spr_match_mas4_2) ) or + ( (mas5_2_sgs_q & (33 to 55 => '0') & mas5_2_slpid_q) + and (32 to 63 => spr_match_mas5_2) ) or + ( ("00" & mas6_2_spid_q & "0000" & mas6_2_isize_q & "000000" & mas6_2_sind_q & mas6_2_sas_q) + and (32 to 63 => (spr_match_mas6_2 or spr_match_mas56_64b_2)) ) or + ( ((32 to 53 => '0') & mas7_2_rpnu_q) + and (32 to 63 => spr_match_mas7_2) ) or + ( (mas8_2_tgs_q & mas8_2_vf_q & (34 to 55 => '0') & mas8_2_tlpid_q) + and (32 to 63 => spr_match_mas8_2) ) or + ( (mas0_3_atsel_q & (33 to 44 => '0') & mas0_3_esel_q & '0' & mas0_3_hes_q & mas0_3_wq_q & (52 to 63 => '0')) + and (32 to 63 => spr_match_mas0_3) ) or + ( (mas1_3_v_q & mas1_3_iprot_q & mas1_3_tid_q & "00" & mas1_3_ind_q & mas1_3_ts_q & mas1_3_tsize_q & "00000000") + and (32 to 63 => (spr_match_mas1_3 or spr_match_mas01_64b_3 or spr_match_mas81_64b_3)) ) or + ( (mas2_3_epn_q(32 to 51) & "0000000" & mas2_3_wimge_q) + and (32 to 63 => spr_match_mas2_3) ) or + ( (mas2_3_epn_q(0 to 31) ) + and (32 to 63 => spr_match_mas2u_3) ) or + ( (mas3_3_rpnl_q & '0' & mas3_3_ubits_q & mas3_3_usxwr_q) + and (32 to 63 => (spr_match_mas3_3 or spr_match_mas73_64b_3)) ) or + ( ((32 to 47 => '0') & mas4_3_indd_q & "000" & mas4_3_tsized_q & "000" & mas4_3_wimged_q) + and (32 to 63 => spr_match_mas4_3) ) or + ( (mas5_3_sgs_q & (33 to 55 => '0') & mas5_3_slpid_q) + and (32 to 63 => spr_match_mas5_3) ) or + ( ("00" & mas6_3_spid_q & "0000" & mas6_3_isize_q & "000000" & mas6_3_sind_q & mas6_3_sas_q) + and (32 to 63 => (spr_match_mas6_3 or spr_match_mas56_64b_3)) ) or + ( ((32 to 53 => '0') & mas7_3_rpnu_q) + and (32 to 63 => spr_match_mas7_3) ) or + ( (mas8_3_tgs_q & mas8_3_vf_q & (34 to 55 => '0') & mas8_3_tlpid_q) + and (32 to 63 => spr_match_mas8_3) ); +gen64_spr_data: if spr_data_width = 64 generate +spr_mas_data_out(0 to 31) <= + ( mas2_0_epn_q(0 to 31) + and (0 to 31 => spr_match_mas2_0) ) or + ( (mas0_0_atsel_q & (1 to 12 => '0') & mas0_0_esel_q & '0' & mas0_0_hes_q & mas0_0_wq_q & (20 to 31 => '0')) + and (0 to 31 => spr_match_mas01_64b_0) ) or + ( (mas5_0_sgs_q & (1 to 23 => '0') & mas5_0_slpid_q) + and (0 to 31 => spr_match_mas56_64b_0) ) or + ( ((0 to 21 => '0') & mas7_0_rpnu_q) + and (0 to 31 => spr_match_mas73_64b_0) ) or + ( (mas8_0_tgs_q & mas8_0_vf_q & (34 to 55 => '0') & mas8_0_tlpid_q) + and (0 to 31 => spr_match_mas81_64b_0) ) or + ( mas2_1_epn_q(0 to 31) + and (0 to 31 => spr_match_mas2_1) ) or + ( (mas0_1_atsel_q & (1 to 12 => '0') & mas0_1_esel_q & '0' & mas0_1_hes_q & mas0_1_wq_q & (20 to 31 => '0')) + and (0 to 31 => spr_match_mas01_64b_1) ) or + ( (mas5_1_sgs_q & (1 to 23 => '0') & mas5_1_slpid_q) + and (0 to 31 => spr_match_mas56_64b_1) ) or + ( ((0 to 21 => '0') & mas7_1_rpnu_q) + and (0 to 31 => spr_match_mas73_64b_1) ) or + ( (mas8_1_tgs_q & mas8_1_vf_q & (34 to 55 => '0') & mas8_1_tlpid_q) + and (0 to 31 => spr_match_mas81_64b_1) ) or + ( mas2_2_epn_q(0 to 31) + and (0 to 31 => spr_match_mas2_2) ) or + ( (mas0_2_atsel_q & (1 to 12 => '0') & mas0_2_esel_q & '0' & mas0_2_hes_q & mas0_2_wq_q & (20 to 31 => '0')) + and (0 to 31 => spr_match_mas01_64b_2) ) or + ( (mas5_2_sgs_q & (1 to 23 => '0') & mas5_2_slpid_q) + and (0 to 31 => spr_match_mas56_64b_2) ) or + ( ((0 to 21 => '0') & mas7_2_rpnu_q) + and (0 to 31 => spr_match_mas73_64b_2) ) or + ( (mas8_2_tgs_q & mas8_2_vf_q & (34 to 55 => '0') & mas8_2_tlpid_q) + and (0 to 31 => spr_match_mas81_64b_2) ) or + ( mas2_3_epn_q(0 to 31) + and (0 to 31 => spr_match_mas2_3) ) or + ( (mas0_3_atsel_q & (1 to 12 => '0') & mas0_3_esel_q & '0' & mas0_3_hes_q & mas0_3_wq_q & (20 to 31 => '0')) + and (0 to 31 => spr_match_mas01_64b_3) ) or + ( (mas5_3_sgs_q & (1 to 23 => '0') & mas5_3_slpid_q) + and (0 to 31 => spr_match_mas56_64b_3) ) or + ( ((0 to 21 => '0') & mas7_3_rpnu_q) + and (0 to 31 => spr_match_mas73_64b_3) ) or + ( (mas8_3_tgs_q & mas8_3_vf_q & (34 to 55 => '0') & mas8_3_tlpid_q) + and (0 to 31 => spr_match_mas81_64b_3) ); +spr_data_out_d(0 to 31) <= ( ((0 to 63-real_addr_width => '0') & lper_0_alpn_q(64-real_addr_width to 31)) + and (0 to 31 => (spr_match_lper_0_q and spr_ctl_int_q(1))) ) or + ( ((0 to 63-real_addr_width => '0') & lper_1_alpn_q(64-real_addr_width to 31)) + and (0 to 31 => (spr_match_lper_1_q and spr_ctl_int_q(1))) ) or + ( ((0 to 63-real_addr_width => '0') & lper_2_alpn_q(64-real_addr_width to 31)) + and (0 to 31 => (spr_match_lper_2_q and spr_ctl_int_q(1))) ) or + ( ((0 to 63-real_addr_width => '0') & lper_3_alpn_q(64-real_addr_width to 31)) + and (0 to 31 => (spr_match_lper_3_q and spr_ctl_int_q(1))) ) or + ( spr_mas_data_out_q(0 to 31) and (0 to 31 => (spr_match_any_mas_q and spr_ctl_int_q(1))) ) or + ( spr_data_int_q(0 to 31) and (0 to 31 => (not(spr_match_any_mmu_q) or not(spr_ctl_int_q(1)))) ); +end generate gen64_spr_data; +mm_iu_slowspr_val <= spr_ctl_out_q(0); +mm_iu_slowspr_rw <= spr_ctl_out_q(1); +mm_iu_slowspr_etid <= spr_etid_out_q; +mm_iu_slowspr_addr <= spr_addr_out_q; +mm_iu_slowspr_data <= spr_data_out_q; +mm_iu_slowspr_done <= spr_ctl_out_q(2); +mm_iu_ierat_pid0 <= pid0_q; +mm_iu_ierat_pid1 <= pid1_q; +mm_iu_ierat_pid2 <= pid2_q; +mm_iu_ierat_pid3 <= pid3_q; +mm_iu_ierat_mmucr0_0 <= mmucr0_0_q; +mm_iu_ierat_mmucr0_1 <= mmucr0_1_q; +mm_iu_ierat_mmucr0_2 <= mmucr0_2_q; +mm_iu_ierat_mmucr0_3 <= mmucr0_3_q; +mm_iu_ierat_mmucr1 <= mmucr1_q(0) & mmucr1_q(2 to 5) & mmucr1_q(6 to 7) & mmucr1_q(12 to 13); +mm_xu_derat_pid0 <= pid0_q; +mm_xu_derat_pid1 <= pid1_q; +mm_xu_derat_pid2 <= pid2_q; +mm_xu_derat_pid3 <= pid3_q; +mm_xu_derat_mmucr0_0 <= mmucr0_0_q; +mm_xu_derat_mmucr0_1 <= mmucr0_1_q; +mm_xu_derat_mmucr0_2 <= mmucr0_2_q; +mm_xu_derat_mmucr0_3 <= mmucr0_3_q; +mm_xu_derat_mmucr1 <= mmucr1_q(1) & mmucr1_q(2 to 5) & mmucr1_q(8 to 9) & mmucr1_q(14 to 16); +-- mmucr1: 0-IRRE, 1-DRRE, 2-REE, 3-CEE, +-- 4-Disable any context sync inst from invalidating extclass=0 erat entries, +-- 5-Disable isync inst from invalidating extclass=0 erat entries, +-- 6:7-IPEI, 8:9-DPEI, 10:11-TPEI, 12:13-ICTID/ITTID, 14:15-DCTID/DTTID, +-- 16-DCCD, 17-TLBWE_BINV, 18-TLBI_MSB, 19-TLBI_REJ, +-- 20-IERRDET, 21-DERRDET, 22-TERRDET, 23:31-EEN +pid0 <= pid0_q; +pid1 <= pid1_q; +pid2 <= pid2_q; +pid3 <= pid3_q; +mmucr0_0 <= mmucr0_0_q; +mmucr0_1 <= mmucr0_1_q; +mmucr0_2 <= mmucr0_2_q; +mmucr0_3 <= mmucr0_3_q; +mmucr1 <= mmucr1_q; +mmucr2 <= mmucr2_q; +mmucr3_0 <= mmucr3_0_q; +mmucr3_1 <= mmucr3_1_q; +mmucr3_2 <= mmucr3_2_q; +mmucr3_3 <= mmucr3_3_q; +lpidr <= lpidr_q; +ac_an_lpar_id <= lpidr_q; +mmucfg_lrat <= mmucfg_q(47); +mmucfg_twc <= mmucfg_q(48); +tlb0cfg_pt <= tlb0cfg_q(45); +tlb0cfg_ind <= tlb0cfg_q(46); +tlb0cfg_gtwe <= tlb0cfg_q(47); +mas0_0_atsel <= mas0_0_atsel_q; +mas0_0_esel <= mas0_0_esel_q; +mas0_0_hes <= mas0_0_hes_q; +mas0_0_wq <= mas0_0_wq_q; +mas1_0_v <= mas1_0_v_q; +mas1_0_iprot <= mas1_0_iprot_q; +mas1_0_tid <= mas1_0_tid_q; +mas1_0_ind <= mas1_0_ind_q; +mas1_0_ts <= mas1_0_ts_q; +mas1_0_tsize <= mas1_0_tsize_q; +gen32_mas2_0_epn: if spr_data_width = 32 generate +mas2_0_epn(0 to 31) <=(others => '0'); +mas2_0_epn(32 to 51) <= mas2_0_epn_q(32 to 51); +end generate gen32_mas2_0_epn; +gen64_mas2_0_epn: if spr_data_width = 64 generate +mas2_0_epn <= mas2_0_epn_q; +end generate gen64_mas2_0_epn; +mas2_0_wimge <= mas2_0_wimge_q; +mas3_0_rpnl <= mas3_0_rpnl_q; +mas3_0_ubits <= mas3_0_ubits_q; +mas3_0_usxwr <= mas3_0_usxwr_q; +mas5_0_sgs <= mas5_0_sgs_q; +mas5_0_slpid <= mas5_0_slpid_q; +mas6_0_spid <= mas6_0_spid_q; +mas6_0_isize <= mas6_0_isize_q; +mas6_0_sind <= mas6_0_sind_q; +mas6_0_sas <= mas6_0_sas_q; +mas7_0_rpnu <= mas7_0_rpnu_q; +mas8_0_tgs <= mas8_0_tgs_q; +mas8_0_vf <= mas8_0_vf_q; +mas8_0_tlpid <= mas8_0_tlpid_q; +mas0_1_atsel <= mas0_1_atsel_q; +mas0_1_esel <= mas0_1_esel_q; +mas0_1_hes <= mas0_1_hes_q; +mas0_1_wq <= mas0_1_wq_q; +mas1_1_v <= mas1_1_v_q; +mas1_1_iprot <= mas1_1_iprot_q; +mas1_1_tid <= mas1_1_tid_q; +mas1_1_ind <= mas1_1_ind_q; +mas1_1_ts <= mas1_1_ts_q; +mas1_1_tsize <= mas1_1_tsize_q; +gen32_mas2_1_epn: if spr_data_width = 32 generate +mas2_1_epn(0 to 31) <=(others => '0'); +mas2_1_epn(32 to 51) <= mas2_1_epn_q(32 to 51); +end generate gen32_mas2_1_epn; +gen64_mas2_1_epn: if spr_data_width = 64 generate +mas2_1_epn <= mas2_1_epn_q; +end generate gen64_mas2_1_epn; +mas2_1_wimge <= mas2_1_wimge_q; +mas3_1_rpnl <= mas3_1_rpnl_q; +mas3_1_ubits <= mas3_1_ubits_q; +mas3_1_usxwr <= mas3_1_usxwr_q; +mas5_1_sgs <= mas5_1_sgs_q; +mas5_1_slpid <= mas5_1_slpid_q; +mas6_1_spid <= mas6_1_spid_q; +mas6_1_isize <= mas6_1_isize_q; +mas6_1_sind <= mas6_1_sind_q; +mas6_1_sas <= mas6_1_sas_q; +mas7_1_rpnu <= mas7_1_rpnu_q; +mas8_1_tgs <= mas8_1_tgs_q; +mas8_1_vf <= mas8_1_vf_q; +mas8_1_tlpid <= mas8_1_tlpid_q; +mas0_2_atsel <= mas0_2_atsel_q; +mas0_2_esel <= mas0_2_esel_q; +mas0_2_hes <= mas0_2_hes_q; +mas0_2_wq <= mas0_2_wq_q; +mas1_2_v <= mas1_2_v_q; +mas1_2_iprot <= mas1_2_iprot_q; +mas1_2_tid <= mas1_2_tid_q; +mas1_2_ind <= mas1_2_ind_q; +mas1_2_ts <= mas1_2_ts_q; +mas1_2_tsize <= mas1_2_tsize_q; +gen32_mas2_2_epn: if spr_data_width = 32 generate +mas2_2_epn(0 to 31) <=(others => '0'); +mas2_2_epn(32 to 51) <= mas2_2_epn_q(32 to 51); +end generate gen32_mas2_2_epn; +gen64_mas2_2_epn: if spr_data_width = 64 generate +mas2_2_epn <= mas2_2_epn_q; +end generate gen64_mas2_2_epn; +mas2_2_wimge <= mas2_2_wimge_q; +mas3_2_rpnl <= mas3_2_rpnl_q; +mas3_2_ubits <= mas3_2_ubits_q; +mas3_2_usxwr <= mas3_2_usxwr_q; +mas5_2_sgs <= mas5_2_sgs_q; +mas5_2_slpid <= mas5_2_slpid_q; +mas6_2_spid <= mas6_2_spid_q; +mas6_2_isize <= mas6_2_isize_q; +mas6_2_sind <= mas6_2_sind_q; +mas6_2_sas <= mas6_2_sas_q; +mas7_2_rpnu <= mas7_2_rpnu_q; +mas8_2_tgs <= mas8_2_tgs_q; +mas8_2_vf <= mas8_2_vf_q; +mas8_2_tlpid <= mas8_2_tlpid_q; +mas0_3_atsel <= mas0_3_atsel_q; +mas0_3_esel <= mas0_3_esel_q; +mas0_3_hes <= mas0_3_hes_q; +mas0_3_wq <= mas0_3_wq_q; +mas1_3_v <= mas1_3_v_q; +mas1_3_iprot <= mas1_3_iprot_q; +mas1_3_tid <= mas1_3_tid_q; +mas1_3_ind <= mas1_3_ind_q; +mas1_3_ts <= mas1_3_ts_q; +mas1_3_tsize <= mas1_3_tsize_q; +gen32_mas2_3_epn: if spr_data_width = 32 generate +mas2_3_epn(0 to 31) <=(others => '0'); +mas2_3_epn(32 to 51) <= mas2_3_epn_q(32 to 51); +end generate gen32_mas2_3_epn; +gen64_mas2_3_epn: if spr_data_width = 64 generate +mas2_3_epn <= mas2_3_epn_q; +end generate gen64_mas2_3_epn; +mas2_3_wimge <= mas2_3_wimge_q; +mas3_3_rpnl <= mas3_3_rpnl_q; +mas3_3_ubits <= mas3_3_ubits_q; +mas3_3_usxwr <= mas3_3_usxwr_q; +mas5_3_sgs <= mas5_3_sgs_q; +mas5_3_slpid <= mas5_3_slpid_q; +mas6_3_spid <= mas6_3_spid_q; +mas6_3_isize <= mas6_3_isize_q; +mas6_3_sind <= mas6_3_sind_q; +mas6_3_sas <= mas6_3_sas_q; +mas7_3_rpnu <= mas7_3_rpnu_q; +mas8_3_tgs <= mas8_3_tgs_q; +mas8_3_vf <= mas8_3_vf_q; +mas8_3_tlpid <= mas8_3_tlpid_q; +mmucsr0_tlb0fi <= mmucsr0_tlb0fi_q; +-- debug output formation +spr_dbg_slowspr_val_int <= spr_ctl_int_q(0); +spr_dbg_slowspr_rw_int <= spr_ctl_int_q(1); +spr_dbg_slowspr_etid_int <= spr_etid_int_q; +spr_dbg_slowspr_addr_int <= spr_addr_int_q; +spr_dbg_slowspr_val_out <= spr_ctl_out_q(0); +spr_dbg_slowspr_done_out <= spr_ctl_out_q(2); +spr_dbg_slowspr_data_out <= spr_data_out_q; +spr_dbg_match_64b <= spr_match_64b_q; +spr_dbg_match_any_mmu <= spr_match_any_mmu_q; +spr_dbg_match_any_mas <= spr_match_any_mas_q; +spr_dbg_match_pid <= spr_match_pid0_q or spr_match_pid1_q or spr_match_pid2_q or spr_match_pid3_q; +spr_dbg_match_mmucr0 <= spr_match_mmucr0_0_q or spr_match_mmucr0_1_q or spr_match_mmucr0_2_q or spr_match_mmucr0_3_q; +spr_dbg_match_mmucr1 <= spr_match_mmucr1_q; +spr_dbg_match_mmucr2 <= spr_match_mmucr2_q; +spr_dbg_match_mmucr3 <= spr_match_mmucr3_0_q or spr_match_mmucr3_1_q or spr_match_mmucr3_2_q or spr_match_mmucr3_3_q; +spr_dbg_match_lpidr <= spr_match_lpidr_q; +spr_dbg_match_mmucsr0 <= spr_match_mmucsr0_q; +spr_dbg_match_mmucfg <= spr_match_mmucfg_q; +spr_dbg_match_tlb0cfg <= spr_match_tlb0cfg_q; +spr_dbg_match_tlb0ps <= spr_match_tlb0ps_q; +spr_dbg_match_lratcfg <= spr_match_lratcfg; +spr_dbg_match_lratps <= spr_match_lratps_q; +spr_dbg_match_eptcfg <= spr_match_eptcfg_q; +spr_dbg_match_lper <= spr_match_lper_0_q or spr_match_lper_1_q or spr_match_lper_2_q or spr_match_lper_3_q; +spr_dbg_match_lperu <= spr_match_lperu_0_q or spr_match_lperu_1_q or spr_match_lperu_2_q or spr_match_lperu_3_q; +spr_dbg_match_mas0 <= spr_match_mas0_0_q or spr_match_mas0_1_q or spr_match_mas0_2_q or spr_match_mas0_3_q; +spr_dbg_match_mas1 <= spr_match_mas1_0_q or spr_match_mas1_1_q or spr_match_mas1_2_q or spr_match_mas1_3_q; +spr_dbg_match_mas2 <= spr_match_mas2_0_q or spr_match_mas2_1_q or spr_match_mas2_2_q or spr_match_mas2_3_q; +spr_dbg_match_mas2u <= spr_match_mas2u_0_q or spr_match_mas2u_1_q or spr_match_mas2u_2_q or spr_match_mas2u_3_q; +spr_dbg_match_mas3 <= spr_match_mas3_0_q or spr_match_mas3_1_q or spr_match_mas3_2_q or spr_match_mas3_3_q; +spr_dbg_match_mas4 <= spr_match_mas4_0_q or spr_match_mas4_1_q or spr_match_mas4_2_q or spr_match_mas4_3_q; +spr_dbg_match_mas5 <= spr_match_mas5_0_q or spr_match_mas5_1_q or spr_match_mas5_2_q or spr_match_mas5_3_q; +spr_dbg_match_mas6 <= spr_match_mas6_0_q or spr_match_mas6_1_q or spr_match_mas6_2_q or spr_match_mas6_3_q; +spr_dbg_match_mas7 <= spr_match_mas7_0_q or spr_match_mas7_1_q or spr_match_mas7_2_q or spr_match_mas7_3_q; +spr_dbg_match_mas8 <= spr_match_mas8_0_q or spr_match_mas8_1_q or spr_match_mas8_2_q or spr_match_mas8_3_q; +spr_dbg_match_mas01_64b <= spr_match_mas01_64b_0_q or spr_match_mas01_64b_1_q or spr_match_mas01_64b_2_q or spr_match_mas01_64b_3_q; +spr_dbg_match_mas56_64b <= spr_match_mas56_64b_0_q or spr_match_mas56_64b_1_q or spr_match_mas56_64b_2_q or spr_match_mas56_64b_3_q; +spr_dbg_match_mas73_64b <= spr_match_mas73_64b_0_q or spr_match_mas73_64b_1_q or spr_match_mas73_64b_2_q or spr_match_mas73_64b_3_q; +spr_dbg_match_mas81_64b <= spr_match_mas81_64b_0_q or spr_match_mas81_64b_1_q or spr_match_mas81_64b_2_q or spr_match_mas81_64b_3_q; +unused_dc(0) <= or_reduce(LCB_DELAY_LCLKR_DC(1 TO 4)); +unused_dc(1) <= or_reduce(LCB_MPW1_DC_B(1 TO 4)); +unused_dc(2) <= PC_FUNC_SL_FORCE; +unused_dc(3) <= PC_FUNC_SL_THOLD_0_B; +unused_dc(4) <= TC_SCAN_DIS_DC_B; +unused_dc(5) <= TC_SCAN_DIAG_DC; +unused_dc(6) <= TC_LBIST_EN_DC; +unused_dc(7) <= or_reduce(MMUCFG_Q_B); +unused_dc(8) <= or_reduce(TLB0CFG_Q_B); +unused_dc(9) <= or_reduce(TLB_MAS6_ISIZE); +unused_dc(10) <= TLB_MAS6_SIND; +unused_dc(11) <= or_reduce(LRAT_TAG4_HIT_ENTRY); +unused_dc(12) <= or_reduce(bcfg_spare_q); +unused_dc(13) <= or_reduce(bcfg_spare_q_b); +-------------------------------------------------- +-- latches +-------------------------------------------------- +-- slow spr daisy-chain latches +spr_ctl_in_latch: tri_rlmreg_p + generic map (width => spr_ctl_in_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spr_ctl_in_offset to spr_ctl_in_offset+spr_ctl_in_q'length-1), + scout => sov_0(spr_ctl_in_offset to spr_ctl_in_offset+spr_ctl_in_q'length-1), + din => spr_ctl_in_d(0 to spr_ctl_width-1), + dout => spr_ctl_in_q(0 to spr_ctl_width-1) ); +spr_etid_in_latch: tri_rlmreg_p + generic map (width => spr_etid_in_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spr_etid_in_offset to spr_etid_in_offset+spr_etid_in_q'length-1), + scout => sov_0(spr_etid_in_offset to spr_etid_in_offset+spr_etid_in_q'length-1), + din => spr_etid_in_d(0 to spr_etid_width-1), + dout => spr_etid_in_q(0 to spr_etid_width-1) ); +spr_addr_in_latch: tri_rlmreg_p + generic map (width => spr_addr_in_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spr_addr_in_offset to spr_addr_in_offset+spr_addr_in_q'length-1), + scout => sov_0(spr_addr_in_offset to spr_addr_in_offset+spr_addr_in_q'length-1), + din => spr_addr_in_d(0 to spr_addr_width-1), + dout => spr_addr_in_q(0 to spr_addr_width-1) ); +spr_addr_in_clone_latch: tri_rlmreg_p + generic map (width => spr_addr_in_clone_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_addr_in_clone_offset to spr_addr_in_clone_offset+spr_addr_in_clone_q'length-1), + scout => sov_1(spr_addr_in_clone_offset to spr_addr_in_clone_offset+spr_addr_in_clone_q'length-1), + din => spr_addr_in_clone_d(0 to spr_addr_width-1), + dout => spr_addr_in_clone_q(0 to spr_addr_width-1) ); +spr_data_in_latch: tri_rlmreg_p + generic map (width => spr_data_in_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spr_data_in_offset to spr_data_in_offset+spr_data_in_q'length-1), + scout => sov_0(spr_data_in_offset to spr_data_in_offset+spr_data_in_q'length-1), + din => spr_data_in_d(64-spr_data_width to 63), + dout => spr_data_in_q(64-spr_data_width to 63) ); +-- these are the spr internal select stage latches below +spr_ctl_int_latch: tri_rlmreg_p + generic map (width => spr_ctl_int_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_val_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spr_ctl_int_offset to spr_ctl_int_offset+spr_ctl_int_q'length-1), + scout => sov_0(spr_ctl_int_offset to spr_ctl_int_offset+spr_ctl_int_q'length-1), + din => spr_ctl_int_d(0 to spr_ctl_width-1), + dout => spr_ctl_int_q(0 to spr_ctl_width-1) ); +spr_etid_int_latch: tri_rlmreg_p + generic map (width => spr_etid_int_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_val_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spr_etid_int_offset to spr_etid_int_offset+spr_etid_int_q'length-1), + scout => sov_0(spr_etid_int_offset to spr_etid_int_offset+spr_etid_int_q'length-1), + din => spr_etid_int_d(0 to spr_etid_width-1), + dout => spr_etid_int_q(0 to spr_etid_width-1) ); +spr_addr_int_latch: tri_rlmreg_p + generic map (width => spr_addr_int_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_val_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spr_addr_int_offset to spr_addr_int_offset+spr_addr_int_q'length-1), + scout => sov_0(spr_addr_int_offset to spr_addr_int_offset+spr_addr_int_q'length-1), + din => spr_addr_int_d(0 to spr_addr_width-1), + dout => spr_addr_int_q(0 to spr_addr_width-1) ); +spr_data_int_latch: tri_rlmreg_p + generic map (width => spr_data_int_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_val_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spr_data_int_offset to spr_data_int_offset+spr_data_int_q'length-1), + scout => sov_0(spr_data_int_offset to spr_data_int_offset+spr_data_int_q'length-1), + din => spr_data_int_d(64-spr_data_width to 63), + dout => spr_data_int_q(64-spr_data_width to 63) ); +-- these are the spr out latches below +spr_ctl_out_latch: tri_rlmreg_p + generic map (width => spr_ctl_out_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_val_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spr_ctl_out_offset to spr_ctl_out_offset+spr_ctl_out_q'length-1), + scout => sov_0(spr_ctl_out_offset to spr_ctl_out_offset+spr_ctl_out_q'length-1), + din => spr_ctl_out_d(0 to spr_ctl_width-1), + dout => spr_ctl_out_q(0 to spr_ctl_width-1) ); +spr_etid_out_latch: tri_rlmreg_p + generic map (width => spr_etid_out_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_val_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spr_etid_out_offset to spr_etid_out_offset+spr_etid_out_q'length-1), + scout => sov_0(spr_etid_out_offset to spr_etid_out_offset+spr_etid_out_q'length-1), + din => spr_etid_out_d(0 to spr_etid_width-1), + dout => spr_etid_out_q(0 to spr_etid_width-1) ); +spr_addr_out_latch: tri_rlmreg_p + generic map (width => spr_addr_out_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_val_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spr_addr_out_offset to spr_addr_out_offset+spr_addr_out_q'length-1), + scout => sov_0(spr_addr_out_offset to spr_addr_out_offset+spr_addr_out_q'length-1), + din => spr_addr_out_d(0 to spr_addr_width-1), + dout => spr_addr_out_q(0 to spr_addr_width-1) ); +spr_data_out_latch: tri_rlmreg_p + generic map (width => spr_data_out_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_val_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spr_data_out_offset to spr_data_out_offset+spr_data_out_q'length-1), + scout => sov_0(spr_data_out_offset to spr_data_out_offset+spr_data_out_q'length-1), + din => spr_data_out_d(64-spr_data_width to 63), + dout => spr_data_out_q(64-spr_data_width to 63) ); +-- spr decode match latches for timing +spr_match_any_mmu_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spr_match_any_mmu_offset), + scout => sov_0(spr_match_any_mmu_offset), + din => spr_match_any_mmu, + dout => spr_match_any_mmu_q); +spr_match_pid0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spr_match_pid0_offset), + scout => sov_0(spr_match_pid0_offset), + din => spr_match_pid0, + dout => spr_match_pid0_q); +spr_match_pid1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spr_match_pid1_offset), + scout => sov_0(spr_match_pid1_offset), + din => spr_match_pid1, + dout => spr_match_pid1_q); +spr_match_pid2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spr_match_pid2_offset), + scout => sov_0(spr_match_pid2_offset), + din => spr_match_pid2, + dout => spr_match_pid2_q); +spr_match_pid3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spr_match_pid3_offset), + scout => sov_0(spr_match_pid3_offset), + din => spr_match_pid3, + dout => spr_match_pid3_q); +spr_match_mmucr0_0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spr_match_mmucr0_0_offset), + scout => sov_0(spr_match_mmucr0_0_offset), + din => spr_match_mmucr0_0, + dout => spr_match_mmucr0_0_q); +spr_match_mmucr0_1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spr_match_mmucr0_1_offset), + scout => sov_0(spr_match_mmucr0_1_offset), + din => spr_match_mmucr0_1, + dout => spr_match_mmucr0_1_q); +spr_match_mmucr0_2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spr_match_mmucr0_2_offset), + scout => sov_0(spr_match_mmucr0_2_offset), + din => spr_match_mmucr0_2, + dout => spr_match_mmucr0_2_q); +spr_match_mmucr0_3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spr_match_mmucr0_3_offset), + scout => sov_0(spr_match_mmucr0_3_offset), + din => spr_match_mmucr0_3, + dout => spr_match_mmucr0_3_q); +spr_match_mmucr1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spr_match_mmucr1_offset), + scout => sov_0(spr_match_mmucr1_offset), + din => spr_match_mmucr1, + dout => spr_match_mmucr1_q); +spr_match_mmucr2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spr_match_mmucr2_offset), + scout => sov_0(spr_match_mmucr2_offset), + din => spr_match_mmucr2, + dout => spr_match_mmucr2_q); +spr_match_mmucr3_0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spr_match_mmucr3_0_offset), + scout => sov_0(spr_match_mmucr3_0_offset), + din => spr_match_mmucr3_0, + dout => spr_match_mmucr3_0_q); +spr_match_mmucr3_1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spr_match_mmucr3_1_offset), + scout => sov_0(spr_match_mmucr3_1_offset), + din => spr_match_mmucr3_1, + dout => spr_match_mmucr3_1_q); +spr_match_mmucr3_2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spr_match_mmucr3_2_offset), + scout => sov_0(spr_match_mmucr3_2_offset), + din => spr_match_mmucr3_2, + dout => spr_match_mmucr3_2_q); +spr_match_mmucr3_3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spr_match_mmucr3_3_offset), + scout => sov_0(spr_match_mmucr3_3_offset), + din => spr_match_mmucr3_3, + dout => spr_match_mmucr3_3_q); +spr_match_lpidr_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spr_match_lpidr_offset), + scout => sov_0(spr_match_lpidr_offset), + din => spr_match_lpidr, + dout => spr_match_lpidr_q); +spr_match_mmucsr0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mmucsr0_offset), + scout => sov_1(spr_match_mmucsr0_offset), + din => spr_match_mmucsr0, + dout => spr_match_mmucsr0_q); +spr_match_mmucfg_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mmucfg_offset), + scout => sov_1(spr_match_mmucfg_offset), + din => spr_match_mmucfg, + dout => spr_match_mmucfg_q); +spr_match_tlb0cfg_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_tlb0cfg_offset), + scout => sov_1(spr_match_tlb0cfg_offset), + din => spr_match_tlb0cfg, + dout => spr_match_tlb0cfg_q); +spr_match_tlb0ps_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_tlb0ps_offset), + scout => sov_1(spr_match_tlb0ps_offset), + din => spr_match_tlb0ps, + dout => spr_match_tlb0ps_q); +spr_match_lratcfg_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_lratcfg_offset), + scout => sov_1(spr_match_lratcfg_offset), + din => spr_match_lratcfg, + dout => spr_match_lratcfg_q); +spr_match_lratps_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_lratps_offset), + scout => sov_1(spr_match_lratps_offset), + din => spr_match_lratps, + dout => spr_match_lratps_q); +spr_match_eptcfg_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_eptcfg_offset), + scout => sov_1(spr_match_eptcfg_offset), + din => spr_match_eptcfg, + dout => spr_match_eptcfg_q); +spr_match_lper_0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_lper_0_offset), + scout => sov_1(spr_match_lper_0_offset), + din => spr_match_lper_0, + dout => spr_match_lper_0_q); +spr_match_lper_1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_lper_1_offset), + scout => sov_1(spr_match_lper_1_offset), + din => spr_match_lper_1, + dout => spr_match_lper_1_q); +spr_match_lper_2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_lper_2_offset), + scout => sov_1(spr_match_lper_2_offset), + din => spr_match_lper_2, + dout => spr_match_lper_2_q); +spr_match_lper_3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_lper_3_offset), + scout => sov_1(spr_match_lper_3_offset), + din => spr_match_lper_3, + dout => spr_match_lper_3_q); +spr_match_lperu_0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_lperu_0_offset), + scout => sov_1(spr_match_lperu_0_offset), + din => spr_match_lperu_0, + dout => spr_match_lperu_0_q); +spr_match_lperu_1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_lperu_1_offset), + scout => sov_1(spr_match_lperu_1_offset), + din => spr_match_lperu_1, + dout => spr_match_lperu_1_q); +spr_match_lperu_2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_lperu_2_offset), + scout => sov_1(spr_match_lperu_2_offset), + din => spr_match_lperu_2, + dout => spr_match_lperu_2_q); +spr_match_lperu_3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_lperu_3_offset), + scout => sov_1(spr_match_lperu_3_offset), + din => spr_match_lperu_3, + dout => spr_match_lperu_3_q); +spr_match_mas0_0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas0_0_offset), + scout => sov_1(spr_match_mas0_0_offset), + din => spr_match_mas0_0, + dout => spr_match_mas0_0_q); +spr_match_mas0_1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas0_1_offset), + scout => sov_1(spr_match_mas0_1_offset), + din => spr_match_mas0_1, + dout => spr_match_mas0_1_q); +spr_match_mas0_2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas0_2_offset), + scout => sov_1(spr_match_mas0_2_offset), + din => spr_match_mas0_2, + dout => spr_match_mas0_2_q); +spr_match_mas0_3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas0_3_offset), + scout => sov_1(spr_match_mas0_3_offset), + din => spr_match_mas0_3, + dout => spr_match_mas0_3_q); +spr_match_mas1_0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas1_0_offset), + scout => sov_1(spr_match_mas1_0_offset), + din => spr_match_mas1_0, + dout => spr_match_mas1_0_q); +spr_match_mas1_1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas1_1_offset), + scout => sov_1(spr_match_mas1_1_offset), + din => spr_match_mas1_1, + dout => spr_match_mas1_1_q); +spr_match_mas1_2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas1_2_offset), + scout => sov_1(spr_match_mas1_2_offset), + din => spr_match_mas1_2, + dout => spr_match_mas1_2_q); +spr_match_mas1_3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas1_3_offset), + scout => sov_1(spr_match_mas1_3_offset), + din => spr_match_mas1_3, + dout => spr_match_mas1_3_q); +spr_match_mas2_0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas2_0_offset), + scout => sov_1(spr_match_mas2_0_offset), + din => spr_match_mas2_0, + dout => spr_match_mas2_0_q); +spr_match_mas2_1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas2_1_offset), + scout => sov_1(spr_match_mas2_1_offset), + din => spr_match_mas2_1, + dout => spr_match_mas2_1_q); +spr_match_mas2_2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas2_2_offset), + scout => sov_1(spr_match_mas2_2_offset), + din => spr_match_mas2_2, + dout => spr_match_mas2_2_q); +spr_match_mas2_3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas2_3_offset), + scout => sov_1(spr_match_mas2_3_offset), + din => spr_match_mas2_3, + dout => spr_match_mas2_3_q); +spr_match_mas3_0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas3_0_offset), + scout => sov_1(spr_match_mas3_0_offset), + din => spr_match_mas3_0, + dout => spr_match_mas3_0_q); +spr_match_mas3_1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas3_1_offset), + scout => sov_1(spr_match_mas3_1_offset), + din => spr_match_mas3_1, + dout => spr_match_mas3_1_q); +spr_match_mas3_2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas3_2_offset), + scout => sov_1(spr_match_mas3_2_offset), + din => spr_match_mas3_2, + dout => spr_match_mas3_2_q); +spr_match_mas3_3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas3_3_offset), + scout => sov_1(spr_match_mas3_3_offset), + din => spr_match_mas3_3, + dout => spr_match_mas3_3_q); +spr_match_mas4_0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas4_0_offset), + scout => sov_1(spr_match_mas4_0_offset), + din => spr_match_mas4_0, + dout => spr_match_mas4_0_q); +spr_match_mas4_1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas4_1_offset), + scout => sov_1(spr_match_mas4_1_offset), + din => spr_match_mas4_1, + dout => spr_match_mas4_1_q); +spr_match_mas4_2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas4_2_offset), + scout => sov_1(spr_match_mas4_2_offset), + din => spr_match_mas4_2, + dout => spr_match_mas4_2_q); +spr_match_mas4_3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas4_3_offset), + scout => sov_1(spr_match_mas4_3_offset), + din => spr_match_mas4_3, + dout => spr_match_mas4_3_q); +spr_match_mas5_0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas5_0_offset), + scout => sov_1(spr_match_mas5_0_offset), + din => spr_match_mas5_0, + dout => spr_match_mas5_0_q); +spr_match_mas5_1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas5_1_offset), + scout => sov_1(spr_match_mas5_1_offset), + din => spr_match_mas5_1, + dout => spr_match_mas5_1_q); +spr_match_mas5_2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas5_2_offset), + scout => sov_1(spr_match_mas5_2_offset), + din => spr_match_mas5_2, + dout => spr_match_mas5_2_q); +spr_match_mas5_3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas5_3_offset), + scout => sov_1(spr_match_mas5_3_offset), + din => spr_match_mas5_3, + dout => spr_match_mas5_3_q); +spr_match_mas6_0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas6_0_offset), + scout => sov_1(spr_match_mas6_0_offset), + din => spr_match_mas6_0, + dout => spr_match_mas6_0_q); +spr_match_mas6_1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas6_1_offset), + scout => sov_1(spr_match_mas6_1_offset), + din => spr_match_mas6_1, + dout => spr_match_mas6_1_q); +spr_match_mas6_2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas6_2_offset), + scout => sov_1(spr_match_mas6_2_offset), + din => spr_match_mas6_2, + dout => spr_match_mas6_2_q); +spr_match_mas6_3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas6_3_offset), + scout => sov_1(spr_match_mas6_3_offset), + din => spr_match_mas6_3, + dout => spr_match_mas6_3_q); +spr_match_mas7_0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas7_0_offset), + scout => sov_1(spr_match_mas7_0_offset), + din => spr_match_mas7_0, + dout => spr_match_mas7_0_q); +spr_match_mas7_1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas7_1_offset), + scout => sov_1(spr_match_mas7_1_offset), + din => spr_match_mas7_1, + dout => spr_match_mas7_1_q); +spr_match_mas7_2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas7_2_offset), + scout => sov_1(spr_match_mas7_2_offset), + din => spr_match_mas7_2, + dout => spr_match_mas7_2_q); +spr_match_mas7_3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas7_3_offset), + scout => sov_1(spr_match_mas7_3_offset), + din => spr_match_mas7_3, + dout => spr_match_mas7_3_q); +spr_match_mas8_0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas8_0_offset), + scout => sov_1(spr_match_mas8_0_offset), + din => spr_match_mas8_0, + dout => spr_match_mas8_0_q); +spr_match_mas8_1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas8_1_offset), + scout => sov_1(spr_match_mas8_1_offset), + din => spr_match_mas8_1, + dout => spr_match_mas8_1_q); +spr_match_mas8_2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas8_2_offset), + scout => sov_1(spr_match_mas8_2_offset), + din => spr_match_mas8_2, + dout => spr_match_mas8_2_q); +spr_match_mas8_3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas8_3_offset), + scout => sov_1(spr_match_mas8_3_offset), + din => spr_match_mas8_3, + dout => spr_match_mas8_3_q); +spr_match_mas2u_0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas2u_0_offset), + scout => sov_1(spr_match_mas2u_0_offset), + din => spr_match_mas2u_0, + dout => spr_match_mas2u_0_q); +spr_match_mas2u_1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas2u_1_offset), + scout => sov_1(spr_match_mas2u_1_offset), + din => spr_match_mas2u_1, + dout => spr_match_mas2u_1_q); +spr_match_mas2u_2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas2u_2_offset), + scout => sov_1(spr_match_mas2u_2_offset), + din => spr_match_mas2u_2, + dout => spr_match_mas2u_2_q); +spr_match_mas2u_3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas2u_3_offset), + scout => sov_1(spr_match_mas2u_3_offset), + din => spr_match_mas2u_3, + dout => spr_match_mas2u_3_q); +spr_match_mas01_64b_0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas01_64b_0_offset), + scout => sov_1(spr_match_mas01_64b_0_offset), + din => spr_match_mas01_64b_0, + dout => spr_match_mas01_64b_0_q); +spr_match_mas01_64b_1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas01_64b_1_offset), + scout => sov_1(spr_match_mas01_64b_1_offset), + din => spr_match_mas01_64b_1, + dout => spr_match_mas01_64b_1_q); +spr_match_mas01_64b_2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas01_64b_2_offset), + scout => sov_1(spr_match_mas01_64b_2_offset), + din => spr_match_mas01_64b_2, + dout => spr_match_mas01_64b_2_q); +spr_match_mas01_64b_3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas01_64b_3_offset), + scout => sov_1(spr_match_mas01_64b_3_offset), + din => spr_match_mas01_64b_3, + dout => spr_match_mas01_64b_3_q); +spr_match_mas56_64b_0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas56_64b_0_offset), + scout => sov_1(spr_match_mas56_64b_0_offset), + din => spr_match_mas56_64b_0, + dout => spr_match_mas56_64b_0_q); +spr_match_mas56_64b_1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas56_64b_1_offset), + scout => sov_1(spr_match_mas56_64b_1_offset), + din => spr_match_mas56_64b_1, + dout => spr_match_mas56_64b_1_q); +spr_match_mas56_64b_2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas56_64b_2_offset), + scout => sov_1(spr_match_mas56_64b_2_offset), + din => spr_match_mas56_64b_2, + dout => spr_match_mas56_64b_2_q); +spr_match_mas56_64b_3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas56_64b_3_offset), + scout => sov_1(spr_match_mas56_64b_3_offset), + din => spr_match_mas56_64b_3, + dout => spr_match_mas56_64b_3_q); +spr_match_mas73_64b_0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas73_64b_0_offset), + scout => sov_1(spr_match_mas73_64b_0_offset), + din => spr_match_mas73_64b_0, + dout => spr_match_mas73_64b_0_q); +spr_match_mas73_64b_1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas73_64b_1_offset), + scout => sov_1(spr_match_mas73_64b_1_offset), + din => spr_match_mas73_64b_1, + dout => spr_match_mas73_64b_1_q); +spr_match_mas73_64b_2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas73_64b_2_offset), + scout => sov_1(spr_match_mas73_64b_2_offset), + din => spr_match_mas73_64b_2, + dout => spr_match_mas73_64b_2_q); +spr_match_mas73_64b_3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas73_64b_3_offset), + scout => sov_1(spr_match_mas73_64b_3_offset), + din => spr_match_mas73_64b_3, + dout => spr_match_mas73_64b_3_q); +spr_match_mas81_64b_0_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas81_64b_0_offset), + scout => sov_1(spr_match_mas81_64b_0_offset), + din => spr_match_mas81_64b_0, + dout => spr_match_mas81_64b_0_q); +spr_match_mas81_64b_1_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas81_64b_1_offset), + scout => sov_1(spr_match_mas81_64b_1_offset), + din => spr_match_mas81_64b_1, + dout => spr_match_mas81_64b_1_q); +spr_match_mas81_64b_2_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas81_64b_2_offset), + scout => sov_1(spr_match_mas81_64b_2_offset), + din => spr_match_mas81_64b_2, + dout => spr_match_mas81_64b_2_q); +spr_match_mas81_64b_3_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_mas81_64b_3_offset), + scout => sov_1(spr_match_mas81_64b_3_offset), + din => spr_match_mas81_64b_3, + dout => spr_match_mas81_64b_3_q); +spr_match_64b_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_64b_offset), + scout => sov_1(spr_match_64b_offset), + din => spr_match_64b, + dout => spr_match_64b_q); +-- internal mas data output register +spr_mas_data_out_latch: tri_rlmreg_p + generic map (width => spr_mas_data_out_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_mas_data_out_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_mas_data_out_offset to spr_mas_data_out_offset+spr_mas_data_out_q'length-1), + scout => sov_1(spr_mas_data_out_offset to spr_mas_data_out_offset+spr_mas_data_out_q'length-1), + din => spr_mas_data_out(64-spr_data_width to 63), + dout => spr_mas_data_out_q(64-spr_data_width to 63) ); +spr_match_any_mas_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_match_mas_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spr_match_any_mas_offset), + scout => sov_1(spr_match_any_mas_offset), + din => spr_match_any_mas, + dout => spr_match_any_mas_q); +-- pid spr's +pid0_latch: tri_rlmreg_p + generic map (width => pid0_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_mmu_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(pid0_offset to pid0_offset+pid0_q'length-1), + scout => sov_0(pid0_offset to pid0_offset+pid0_q'length-1), + din => pid0_d(0 to pid_width-1), + dout => pid0_q(0 to pid_width-1) ); +pid1_latch: tri_rlmreg_p + generic map (width => pid1_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_mmu_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(pid1_offset to pid1_offset+pid1_q'length-1), + scout => sov_0(pid1_offset to pid1_offset+pid1_q'length-1), + din => pid1_d(0 to pid_width-1), + dout => pid1_q(0 to pid_width-1) ); +pid2_latch: tri_rlmreg_p + generic map (width => pid2_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_mmu_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(pid2_offset to pid2_offset+pid2_q'length-1), + scout => sov_0(pid2_offset to pid2_offset+pid2_q'length-1), + din => pid2_d(0 to pid_width-1), + dout => pid2_q(0 to pid_width-1) ); +pid3_latch: tri_rlmreg_p + generic map (width => pid3_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_mmu_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(pid3_offset to pid3_offset+pid3_q'length-1), + scout => sov_0(pid3_offset to pid3_offset+pid3_q'length-1), + din => pid3_d(0 to pid_width-1), + dout => pid3_q(0 to pid_width-1) ); +mmucr0_0_latch: tri_rlmreg_p + generic map (width => mmucr0_0_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(mmucr0_0_offset to mmucr0_0_offset+mmucr0_0_q'length-1), + scout => sov_0(mmucr0_0_offset to mmucr0_0_offset+mmucr0_0_q'length-1), + din => mmucr0_0_d(0 to mmucr0_width-1), + dout => mmucr0_0_q(0 to mmucr0_width-1) ); +mmucr0_1_latch: tri_rlmreg_p + generic map (width => mmucr0_1_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(mmucr0_1_offset to mmucr0_1_offset+mmucr0_1_q'length-1), + scout => sov_0(mmucr0_1_offset to mmucr0_1_offset+mmucr0_1_q'length-1), + din => mmucr0_1_d(0 to mmucr0_width-1), + dout => mmucr0_1_q(0 to mmucr0_width-1) ); +mmucr0_2_latch: tri_rlmreg_p + generic map (width => mmucr0_2_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(mmucr0_2_offset to mmucr0_2_offset+mmucr0_2_q'length-1), + scout => sov_0(mmucr0_2_offset to mmucr0_2_offset+mmucr0_2_q'length-1), + din => mmucr0_2_d(0 to mmucr0_width-1), + dout => mmucr0_2_q(0 to mmucr0_width-1) ); +mmucr0_3_latch: tri_rlmreg_p + generic map (width => mmucr0_3_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(mmucr0_3_offset to mmucr0_3_offset+mmucr0_3_q'length-1), + scout => sov_0(mmucr0_3_offset to mmucr0_3_offset+mmucr0_3_q'length-1), + din => mmucr0_3_d(0 to mmucr0_width-1), + dout => mmucr0_3_q(0 to mmucr0_width-1) ); +mmucr1_latch: tri_rlmreg_p + generic map (width => mmucr1_q'length, init => bcfg_mmucr1_value, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(mmucr1_offset to mmucr1_offset+mmucr1_q'length-1), + scout => bsov(mmucr1_offset to mmucr1_offset+mmucr1_q'length-1), + din => mmucr1_d(0 to mmucr1_width-1), + dout => mmucr1_q(0 to mmucr1_width-1) ); +mmucr2_latch: tri_rlmreg_p + generic map (width => mmucr2_q'length, init => bcfg_mmucr2_value, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(mmucr2_offset to mmucr2_offset+mmucr2_q'length-1), + scout => bsov(mmucr2_offset to mmucr2_offset+mmucr2_q'length-1), + din => mmucr2_d(0 to mmucr2_width-1), + dout => mmucr2_q(0 to mmucr2_width-1) ); +mmucr3_0_latch: tri_rlmreg_p + generic map (width => mmucr3_0_q'length, init => bcfg_mmucr3_value, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(mmucr3_0_offset to mmucr3_0_offset+mmucr3_0_q'length-1), + scout => bsov(mmucr3_0_offset to mmucr3_0_offset+mmucr3_0_q'length-1), + din => mmucr3_0_d(64-mmucr3_width to 63), + dout => mmucr3_0_q(64-mmucr3_width to 63) ); +mmucr3_1_latch: tri_rlmreg_p + generic map (width => mmucr3_1_q'length, init => bcfg_mmucr3_value, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(mmucr3_1_offset to mmucr3_1_offset+mmucr3_1_q'length-1), + scout => bsov(mmucr3_1_offset to mmucr3_1_offset+mmucr3_1_q'length-1), + din => mmucr3_1_d(64-mmucr3_width to 63), + dout => mmucr3_1_q(64-mmucr3_width to 63) ); +mmucr3_2_latch: tri_rlmreg_p + generic map (width => mmucr3_2_q'length, init => bcfg_mmucr3_value, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(mmucr3_2_offset to mmucr3_2_offset+mmucr3_2_q'length-1), + scout => bsov(mmucr3_2_offset to mmucr3_2_offset+mmucr3_2_q'length-1), + din => mmucr3_2_d(64-mmucr3_width to 63), + dout => mmucr3_2_q(64-mmucr3_width to 63) ); +mmucr3_3_latch: tri_rlmreg_p + generic map (width => mmucr3_3_q'length, init => bcfg_mmucr3_value, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(mmucr3_3_offset to mmucr3_3_offset+mmucr3_3_q'length-1), + scout => bsov(mmucr3_3_offset to mmucr3_3_offset+mmucr3_3_q'length-1), + din => mmucr3_3_d(64-mmucr3_width to 63), + dout => mmucr3_3_q(64-mmucr3_width to 63) ); +lpidr_latch: tri_rlmreg_p + generic map (width => lpidr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_mmu_act_q(thdid_width), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(lpidr_offset to lpidr_offset+lpidr_q'length-1), + scout => sov_0(lpidr_offset to lpidr_offset+lpidr_q'length-1), + din => lpidr_d(0 to lpid_width-1), + dout => lpidr_q(0 to lpid_width-1) ); +mas0_0_atsel_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas0_0_atsel_offset), + scout => sov_1(mas0_0_atsel_offset), + din => mas0_0_atsel_d, + dout => mas0_0_atsel_q); +mas0_0_esel_latch: tri_rlmreg_p + generic map (width => mas0_0_esel_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas0_0_esel_offset to mas0_0_esel_offset+mas0_0_esel_q'length-1), + scout => sov_1(mas0_0_esel_offset to mas0_0_esel_offset+mas0_0_esel_q'length-1), + din => mas0_0_esel_d(0 to mas0_0_esel_d'length-1), + dout => mas0_0_esel_q(0 to mas0_0_esel_q'length-1) ); +mas0_0_hes_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas0_0_hes_offset), + scout => sov_1(mas0_0_hes_offset), + din => mas0_0_hes_d, + dout => mas0_0_hes_q); +mas0_0_wq_latch: tri_rlmreg_p + generic map (width => mas0_0_wq_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas0_0_wq_offset to mas0_0_wq_offset+mas0_0_wq_q'length-1), + scout => sov_1(mas0_0_wq_offset to mas0_0_wq_offset+mas0_0_wq_q'length-1), + din => mas0_0_wq_d(0 to mas0_0_wq_d'length-1), + dout => mas0_0_wq_q(0 to mas0_0_wq_q'length-1) ); +mas1_0_v_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas1_0_v_offset), + scout => sov_1(mas1_0_v_offset), + din => mas1_0_v_d, + dout => mas1_0_v_q); +mas1_0_iprot_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas1_0_iprot_offset), + scout => sov_1(mas1_0_iprot_offset), + din => mas1_0_iprot_d, + dout => mas1_0_iprot_q); +mas1_0_tid_latch: tri_rlmreg_p + generic map (width => mas1_0_tid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas1_0_tid_offset to mas1_0_tid_offset+mas1_0_tid_q'length-1), + scout => sov_1(mas1_0_tid_offset to mas1_0_tid_offset+mas1_0_tid_q'length-1), + din => mas1_0_tid_d(0 to mas1_0_tid_d'length-1), + dout => mas1_0_tid_q(0 to mas1_0_tid_q'length-1) ); +mas1_0_ind_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas1_0_ind_offset), + scout => sov_1(mas1_0_ind_offset), + din => mas1_0_ind_d, + dout => mas1_0_ind_q); +mas1_0_ts_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas1_0_ts_offset), + scout => sov_1(mas1_0_ts_offset), + din => mas1_0_ts_d, + dout => mas1_0_ts_q); +mas1_0_tsize_latch: tri_rlmreg_p + generic map (width => mas1_0_tsize_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas1_0_tsize_offset to mas1_0_tsize_offset+mas1_0_tsize_q'length-1), + scout => sov_1(mas1_0_tsize_offset to mas1_0_tsize_offset+mas1_0_tsize_q'length-1), + din => mas1_0_tsize_d(0 to mas1_0_tsize_d'length-1), + dout => mas1_0_tsize_q(0 to mas1_0_tsize_q'length-1) ); +mas2_0_epn_latch: tri_rlmreg_p + generic map (width => mas2_0_epn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas2_0_epn_offset to mas2_0_epn_offset+mas2_0_epn_q'length-1), + scout => sov_1(mas2_0_epn_offset to mas2_0_epn_offset+mas2_0_epn_q'length-1), + din => mas2_0_epn_d(52-mas2_0_epn_d'length to 51), + dout => mas2_0_epn_q(52-mas2_0_epn_q'length to 51) ); +mas2_0_wimge_latch: tri_rlmreg_p + generic map (width => mas2_0_wimge_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas2_0_wimge_offset to mas2_0_wimge_offset+mas2_0_wimge_q'length-1), + scout => sov_1(mas2_0_wimge_offset to mas2_0_wimge_offset+mas2_0_wimge_q'length-1), + din => mas2_0_wimge_d(0 to mas2_0_wimge_d'length-1), + dout => mas2_0_wimge_q(0 to mas2_0_wimge_q'length-1) ); +mas3_0_rpnl_latch: tri_rlmreg_p + generic map (width => mas3_0_rpnl_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas3_0_rpnl_offset to mas3_0_rpnl_offset+mas3_0_rpnl_q'length-1), + scout => sov_1(mas3_0_rpnl_offset to mas3_0_rpnl_offset+mas3_0_rpnl_q'length-1), + din => mas3_0_rpnl_d(32 to 32+mas3_0_rpnl_d'length-1), + dout => mas3_0_rpnl_q(32 to 32+mas3_0_rpnl_q'length-1) ); +mas3_0_ubits_latch: tri_rlmreg_p + generic map (width => mas3_0_ubits_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas3_0_ubits_offset to mas3_0_ubits_offset+mas3_0_ubits_q'length-1), + scout => sov_1(mas3_0_ubits_offset to mas3_0_ubits_offset+mas3_0_ubits_q'length-1), + din => mas3_0_ubits_d(0 to mas3_0_ubits_d'length-1), + dout => mas3_0_ubits_q(0 to mas3_0_ubits_q'length-1) ); +mas3_0_usxwr_latch: tri_rlmreg_p + generic map (width => mas3_0_usxwr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas3_0_usxwr_offset to mas3_0_usxwr_offset+mas3_0_usxwr_q'length-1), + scout => sov_1(mas3_0_usxwr_offset to mas3_0_usxwr_offset+mas3_0_usxwr_q'length-1), + din => mas3_0_usxwr_d(0 to mas3_0_usxwr_d'length-1), + dout => mas3_0_usxwr_q(0 to mas3_0_usxwr_q'length-1) ); +mas4_0_indd_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(mas4_0_indd_offset), + scout => bsov(mas4_0_indd_offset), + din => mas4_0_indd_d, + dout => mas4_0_indd_q); +mas4_0_tsized_latch: tri_rlmreg_p + generic map (width => mas4_0_tsized_q'length, init => 1, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(mas4_0_tsized_offset to mas4_0_tsized_offset+mas4_0_tsized_q'length-1), + scout => bsov(mas4_0_tsized_offset to mas4_0_tsized_offset+mas4_0_tsized_q'length-1), + din => mas4_0_tsized_d(0 to mas4_0_tsized_d'length-1), + dout => mas4_0_tsized_q(0 to mas4_0_tsized_q'length-1) ); +mas4_0_wimged_latch: tri_rlmreg_p + generic map (width => mas4_0_wimged_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(mas4_0_wimged_offset to mas4_0_wimged_offset+mas4_0_wimged_q'length-1), + scout => bsov(mas4_0_wimged_offset to mas4_0_wimged_offset+mas4_0_wimged_q'length-1), + din => mas4_0_wimged_d(0 to mas4_0_wimged_d'length-1), + dout => mas4_0_wimged_q(0 to mas4_0_wimged_q'length-1) ); +mas5_0_sgs_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas5_0_sgs_offset), + scout => sov_1(mas5_0_sgs_offset), + din => mas5_0_sgs_d, + dout => mas5_0_sgs_q); +mas5_0_slpid_latch: tri_rlmreg_p + generic map (width => mas5_0_slpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas5_0_slpid_offset to mas5_0_slpid_offset+mas5_0_slpid_q'length-1), + scout => sov_1(mas5_0_slpid_offset to mas5_0_slpid_offset+mas5_0_slpid_q'length-1), + din => mas5_0_slpid_d(0 to mas5_0_slpid_d'length-1), + dout => mas5_0_slpid_q(0 to mas5_0_slpid_q'length-1) ); +mas6_0_spid_latch: tri_rlmreg_p + generic map (width => mas6_0_spid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas6_0_spid_offset to mas6_0_spid_offset+mas6_0_spid_q'length-1), + scout => sov_1(mas6_0_spid_offset to mas6_0_spid_offset+mas6_0_spid_q'length-1), + din => mas6_0_spid_d(0 to mas6_0_spid_d'length-1), + dout => mas6_0_spid_q(0 to mas6_0_spid_q'length-1) ); +mas6_0_isize_latch: tri_rlmreg_p + generic map (width => mas6_0_isize_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas6_0_isize_offset to mas6_0_isize_offset+mas6_0_isize_q'length-1), + scout => sov_1(mas6_0_isize_offset to mas6_0_isize_offset+mas6_0_isize_q'length-1), + din => mas6_0_isize_d(0 to mas6_0_isize_d'length-1), + dout => mas6_0_isize_q(0 to mas6_0_isize_q'length-1) ); +mas6_0_sind_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas6_0_sind_offset), + scout => sov_1(mas6_0_sind_offset), + din => mas6_0_sind_d, + dout => mas6_0_sind_q); +mas6_0_sas_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas6_0_sas_offset), + scout => sov_1(mas6_0_sas_offset), + din => mas6_0_sas_d, + dout => mas6_0_sas_q); +mas7_0_rpnu_latch: tri_rlmreg_p + generic map (width => mas7_0_rpnu_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas7_0_rpnu_offset to mas7_0_rpnu_offset+mas7_0_rpnu_q'length-1), + scout => sov_1(mas7_0_rpnu_offset to mas7_0_rpnu_offset+mas7_0_rpnu_q'length-1), + din => mas7_0_rpnu_d(22 to 22+mas7_0_rpnu_d'length-1), + dout => mas7_0_rpnu_q(22 to 22+mas7_0_rpnu_q'length-1) ); +mas8_0_tgs_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas8_0_tgs_offset), + scout => sov_1(mas8_0_tgs_offset), + din => mas8_0_tgs_d, + dout => mas8_0_tgs_q); +mas8_0_vf_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas8_0_vf_offset), + scout => sov_1(mas8_0_vf_offset), + din => mas8_0_vf_d, + dout => mas8_0_vf_q); +mas8_0_tlpid_latch: tri_rlmreg_p + generic map (width => mas8_0_tlpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas8_0_tlpid_offset to mas8_0_tlpid_offset+mas8_0_tlpid_q'length-1), + scout => sov_1(mas8_0_tlpid_offset to mas8_0_tlpid_offset+mas8_0_tlpid_q'length-1), + din => mas8_0_tlpid_d(0 to mas8_0_tlpid_d'length-1), + dout => mas8_0_tlpid_q(0 to mas8_0_tlpid_q'length-1) ); +mas0_1_atsel_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas0_1_atsel_offset), + scout => sov_1(mas0_1_atsel_offset), + din => mas0_1_atsel_d, + dout => mas0_1_atsel_q); +mas0_1_esel_latch: tri_rlmreg_p + generic map (width => mas0_1_esel_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas0_1_esel_offset to mas0_1_esel_offset+mas0_1_esel_q'length-1), + scout => sov_1(mas0_1_esel_offset to mas0_1_esel_offset+mas0_1_esel_q'length-1), + din => mas0_1_esel_d(0 to mas0_1_esel_d'length-1), + dout => mas0_1_esel_q(0 to mas0_1_esel_q'length-1) ); +mas0_1_hes_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas0_1_hes_offset), + scout => sov_1(mas0_1_hes_offset), + din => mas0_1_hes_d, + dout => mas0_1_hes_q); +mas0_1_wq_latch: tri_rlmreg_p + generic map (width => mas0_1_wq_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas0_1_wq_offset to mas0_1_wq_offset+mas0_1_wq_q'length-1), + scout => sov_1(mas0_1_wq_offset to mas0_1_wq_offset+mas0_1_wq_q'length-1), + din => mas0_1_wq_d(0 to mas0_1_wq_d'length-1), + dout => mas0_1_wq_q(0 to mas0_1_wq_q'length-1) ); +mas1_1_v_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas1_1_v_offset), + scout => sov_1(mas1_1_v_offset), + din => mas1_1_v_d, + dout => mas1_1_v_q); +mas1_1_iprot_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas1_1_iprot_offset), + scout => sov_1(mas1_1_iprot_offset), + din => mas1_1_iprot_d, + dout => mas1_1_iprot_q); +mas1_1_tid_latch: tri_rlmreg_p + generic map (width => mas1_1_tid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas1_1_tid_offset to mas1_1_tid_offset+mas1_1_tid_q'length-1), + scout => sov_1(mas1_1_tid_offset to mas1_1_tid_offset+mas1_1_tid_q'length-1), + din => mas1_1_tid_d(0 to mas1_1_tid_d'length-1), + dout => mas1_1_tid_q(0 to mas1_1_tid_q'length-1) ); +mas1_1_ind_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas1_1_ind_offset), + scout => sov_1(mas1_1_ind_offset), + din => mas1_1_ind_d, + dout => mas1_1_ind_q); +mas1_1_ts_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas1_1_ts_offset), + scout => sov_1(mas1_1_ts_offset), + din => mas1_1_ts_d, + dout => mas1_1_ts_q); +mas1_1_tsize_latch: tri_rlmreg_p + generic map (width => mas1_1_tsize_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas1_1_tsize_offset to mas1_1_tsize_offset+mas1_1_tsize_q'length-1), + scout => sov_1(mas1_1_tsize_offset to mas1_1_tsize_offset+mas1_1_tsize_q'length-1), + din => mas1_1_tsize_d(0 to mas1_1_tsize_d'length-1), + dout => mas1_1_tsize_q(0 to mas1_1_tsize_q'length-1) ); +mas2_1_epn_latch: tri_rlmreg_p + generic map (width => mas2_1_epn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas2_1_epn_offset to mas2_1_epn_offset+mas2_1_epn_q'length-1), + scout => sov_1(mas2_1_epn_offset to mas2_1_epn_offset+mas2_1_epn_q'length-1), + din => mas2_1_epn_d(52-mas2_1_epn_d'length to 51), + dout => mas2_1_epn_q(52-mas2_1_epn_q'length to 51) ); +mas2_1_wimge_latch: tri_rlmreg_p + generic map (width => mas2_1_wimge_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas2_1_wimge_offset to mas2_1_wimge_offset+mas2_1_wimge_q'length-1), + scout => sov_1(mas2_1_wimge_offset to mas2_1_wimge_offset+mas2_1_wimge_q'length-1), + din => mas2_1_wimge_d(0 to mas2_1_wimge_d'length-1), + dout => mas2_1_wimge_q(0 to mas2_1_wimge_q'length-1) ); +mas3_1_rpnl_latch: tri_rlmreg_p + generic map (width => mas3_1_rpnl_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas3_1_rpnl_offset to mas3_1_rpnl_offset+mas3_1_rpnl_q'length-1), + scout => sov_1(mas3_1_rpnl_offset to mas3_1_rpnl_offset+mas3_1_rpnl_q'length-1), + din => mas3_1_rpnl_d(32 to 32+mas3_1_rpnl_d'length-1), + dout => mas3_1_rpnl_q(32 to 32+mas3_1_rpnl_q'length-1) ); +mas3_1_ubits_latch: tri_rlmreg_p + generic map (width => mas3_1_ubits_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas3_1_ubits_offset to mas3_1_ubits_offset+mas3_1_ubits_q'length-1), + scout => sov_1(mas3_1_ubits_offset to mas3_1_ubits_offset+mas3_1_ubits_q'length-1), + din => mas3_1_ubits_d(0 to mas3_1_ubits_d'length-1), + dout => mas3_1_ubits_q(0 to mas3_1_ubits_q'length-1) ); +mas3_1_usxwr_latch: tri_rlmreg_p + generic map (width => mas3_1_usxwr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas3_1_usxwr_offset to mas3_1_usxwr_offset+mas3_1_usxwr_q'length-1), + scout => sov_1(mas3_1_usxwr_offset to mas3_1_usxwr_offset+mas3_1_usxwr_q'length-1), + din => mas3_1_usxwr_d(0 to mas3_1_usxwr_d'length-1), + dout => mas3_1_usxwr_q(0 to mas3_1_usxwr_q'length-1) ); +mas4_1_indd_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(mas4_1_indd_offset), + scout => bsov(mas4_1_indd_offset), + din => mas4_1_indd_d, + dout => mas4_1_indd_q); +mas4_1_tsized_latch: tri_rlmreg_p + generic map (width => mas4_1_tsized_q'length, init => 1, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(mas4_1_tsized_offset to mas4_1_tsized_offset+mas4_1_tsized_q'length-1), + scout => bsov(mas4_1_tsized_offset to mas4_1_tsized_offset+mas4_1_tsized_q'length-1), + din => mas4_1_tsized_d(0 to mas4_1_tsized_d'length-1), + dout => mas4_1_tsized_q(0 to mas4_1_tsized_q'length-1) ); +mas4_1_wimged_latch: tri_rlmreg_p + generic map (width => mas4_1_wimged_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(mas4_1_wimged_offset to mas4_1_wimged_offset+mas4_1_wimged_q'length-1), + scout => bsov(mas4_1_wimged_offset to mas4_1_wimged_offset+mas4_1_wimged_q'length-1), + din => mas4_1_wimged_d(0 to mas4_1_wimged_d'length-1), + dout => mas4_1_wimged_q(0 to mas4_1_wimged_q'length-1) ); +mas5_1_sgs_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas5_1_sgs_offset), + scout => sov_1(mas5_1_sgs_offset), + din => mas5_1_sgs_d, + dout => mas5_1_sgs_q); +mas5_1_slpid_latch: tri_rlmreg_p + generic map (width => mas5_1_slpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas5_1_slpid_offset to mas5_1_slpid_offset+mas5_1_slpid_q'length-1), + scout => sov_1(mas5_1_slpid_offset to mas5_1_slpid_offset+mas5_1_slpid_q'length-1), + din => mas5_1_slpid_d(0 to mas5_1_slpid_d'length-1), + dout => mas5_1_slpid_q(0 to mas5_1_slpid_q'length-1) ); +mas6_1_spid_latch: tri_rlmreg_p + generic map (width => mas6_1_spid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas6_1_spid_offset to mas6_1_spid_offset+mas6_1_spid_q'length-1), + scout => sov_1(mas6_1_spid_offset to mas6_1_spid_offset+mas6_1_spid_q'length-1), + din => mas6_1_spid_d(0 to mas6_1_spid_d'length-1), + dout => mas6_1_spid_q(0 to mas6_1_spid_q'length-1) ); +mas6_1_isize_latch: tri_rlmreg_p + generic map (width => mas6_1_isize_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas6_1_isize_offset to mas6_1_isize_offset+mas6_1_isize_q'length-1), + scout => sov_1(mas6_1_isize_offset to mas6_1_isize_offset+mas6_1_isize_q'length-1), + din => mas6_1_isize_d(0 to mas6_1_isize_d'length-1), + dout => mas6_1_isize_q(0 to mas6_1_isize_q'length-1) ); +mas6_1_sind_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas6_1_sind_offset), + scout => sov_1(mas6_1_sind_offset), + din => mas6_1_sind_d, + dout => mas6_1_sind_q); +mas6_1_sas_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas6_1_sas_offset), + scout => sov_1(mas6_1_sas_offset), + din => mas6_1_sas_d, + dout => mas6_1_sas_q); +mas7_1_rpnu_latch: tri_rlmreg_p + generic map (width => mas7_1_rpnu_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas7_1_rpnu_offset to mas7_1_rpnu_offset+mas7_1_rpnu_q'length-1), + scout => sov_1(mas7_1_rpnu_offset to mas7_1_rpnu_offset+mas7_1_rpnu_q'length-1), + din => mas7_1_rpnu_d(22 to 22+mas7_1_rpnu_d'length-1), + dout => mas7_1_rpnu_q(22 to 22+mas7_1_rpnu_q'length-1) ); +mas8_1_tgs_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas8_1_tgs_offset), + scout => sov_1(mas8_1_tgs_offset), + din => mas8_1_tgs_d, + dout => mas8_1_tgs_q); +mas8_1_vf_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas8_1_vf_offset), + scout => sov_1(mas8_1_vf_offset), + din => mas8_1_vf_d, + dout => mas8_1_vf_q); +mas8_1_tlpid_latch: tri_rlmreg_p + generic map (width => mas8_1_tlpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas8_1_tlpid_offset to mas8_1_tlpid_offset+mas8_1_tlpid_q'length-1), + scout => sov_1(mas8_1_tlpid_offset to mas8_1_tlpid_offset+mas8_1_tlpid_q'length-1), + din => mas8_1_tlpid_d(0 to mas8_1_tlpid_d'length-1), + dout => mas8_1_tlpid_q(0 to mas8_1_tlpid_q'length-1) ); +mas0_2_atsel_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas0_2_atsel_offset), + scout => sov_1(mas0_2_atsel_offset), + din => mas0_2_atsel_d, + dout => mas0_2_atsel_q); +mas0_2_esel_latch: tri_rlmreg_p + generic map (width => mas0_2_esel_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas0_2_esel_offset to mas0_2_esel_offset+mas0_2_esel_q'length-1), + scout => sov_1(mas0_2_esel_offset to mas0_2_esel_offset+mas0_2_esel_q'length-1), + din => mas0_2_esel_d(0 to mas0_2_esel_d'length-1), + dout => mas0_2_esel_q(0 to mas0_2_esel_q'length-1) ); +mas0_2_hes_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas0_2_hes_offset), + scout => sov_1(mas0_2_hes_offset), + din => mas0_2_hes_d, + dout => mas0_2_hes_q); +mas0_2_wq_latch: tri_rlmreg_p + generic map (width => mas0_2_wq_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas0_2_wq_offset to mas0_2_wq_offset+mas0_2_wq_q'length-1), + scout => sov_1(mas0_2_wq_offset to mas0_2_wq_offset+mas0_2_wq_q'length-1), + din => mas0_2_wq_d(0 to mas0_2_wq_d'length-1), + dout => mas0_2_wq_q(0 to mas0_2_wq_q'length-1) ); +mas1_2_v_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas1_2_v_offset), + scout => sov_1(mas1_2_v_offset), + din => mas1_2_v_d, + dout => mas1_2_v_q); +mas1_2_iprot_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas1_2_iprot_offset), + scout => sov_1(mas1_2_iprot_offset), + din => mas1_2_iprot_d, + dout => mas1_2_iprot_q); +mas1_2_tid_latch: tri_rlmreg_p + generic map (width => mas1_2_tid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas1_2_tid_offset to mas1_2_tid_offset+mas1_2_tid_q'length-1), + scout => sov_1(mas1_2_tid_offset to mas1_2_tid_offset+mas1_2_tid_q'length-1), + din => mas1_2_tid_d(0 to mas1_2_tid_d'length-1), + dout => mas1_2_tid_q(0 to mas1_2_tid_q'length-1) ); +mas1_2_ind_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas1_2_ind_offset), + scout => sov_1(mas1_2_ind_offset), + din => mas1_2_ind_d, + dout => mas1_2_ind_q); +mas1_2_ts_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas1_2_ts_offset), + scout => sov_1(mas1_2_ts_offset), + din => mas1_2_ts_d, + dout => mas1_2_ts_q); +mas1_2_tsize_latch: tri_rlmreg_p + generic map (width => mas1_2_tsize_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas1_2_tsize_offset to mas1_2_tsize_offset+mas1_2_tsize_q'length-1), + scout => sov_1(mas1_2_tsize_offset to mas1_2_tsize_offset+mas1_2_tsize_q'length-1), + din => mas1_2_tsize_d(0 to mas1_2_tsize_d'length-1), + dout => mas1_2_tsize_q(0 to mas1_2_tsize_q'length-1) ); +mas2_2_epn_latch: tri_rlmreg_p + generic map (width => mas2_2_epn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas2_2_epn_offset to mas2_2_epn_offset+mas2_2_epn_q'length-1), + scout => sov_1(mas2_2_epn_offset to mas2_2_epn_offset+mas2_2_epn_q'length-1), + din => mas2_2_epn_d(52-mas2_2_epn_d'length to 51), + dout => mas2_2_epn_q(52-mas2_2_epn_q'length to 51) ); +mas2_2_wimge_latch: tri_rlmreg_p + generic map (width => mas2_2_wimge_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas2_2_wimge_offset to mas2_2_wimge_offset+mas2_2_wimge_q'length-1), + scout => sov_1(mas2_2_wimge_offset to mas2_2_wimge_offset+mas2_2_wimge_q'length-1), + din => mas2_2_wimge_d(0 to mas2_2_wimge_d'length-1), + dout => mas2_2_wimge_q(0 to mas2_2_wimge_q'length-1) ); +mas3_2_rpnl_latch: tri_rlmreg_p + generic map (width => mas3_2_rpnl_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas3_2_rpnl_offset to mas3_2_rpnl_offset+mas3_2_rpnl_q'length-1), + scout => sov_1(mas3_2_rpnl_offset to mas3_2_rpnl_offset+mas3_2_rpnl_q'length-1), + din => mas3_2_rpnl_d(32 to 32+mas3_2_rpnl_d'length-1), + dout => mas3_2_rpnl_q(32 to 32+mas3_2_rpnl_q'length-1) ); +mas3_2_ubits_latch: tri_rlmreg_p + generic map (width => mas3_2_ubits_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas3_2_ubits_offset to mas3_2_ubits_offset+mas3_2_ubits_q'length-1), + scout => sov_1(mas3_2_ubits_offset to mas3_2_ubits_offset+mas3_2_ubits_q'length-1), + din => mas3_2_ubits_d(0 to mas3_2_ubits_d'length-1), + dout => mas3_2_ubits_q(0 to mas3_2_ubits_q'length-1) ); +mas3_2_usxwr_latch: tri_rlmreg_p + generic map (width => mas3_2_usxwr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas3_2_usxwr_offset to mas3_2_usxwr_offset+mas3_2_usxwr_q'length-1), + scout => sov_1(mas3_2_usxwr_offset to mas3_2_usxwr_offset+mas3_2_usxwr_q'length-1), + din => mas3_2_usxwr_d(0 to mas3_2_usxwr_d'length-1), + dout => mas3_2_usxwr_q(0 to mas3_2_usxwr_q'length-1) ); +mas4_2_indd_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(mas4_2_indd_offset), + scout => bsov(mas4_2_indd_offset), + din => mas4_2_indd_d, + dout => mas4_2_indd_q); +mas4_2_tsized_latch: tri_rlmreg_p + generic map (width => mas4_2_tsized_q'length, init => 1, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(mas4_2_tsized_offset to mas4_2_tsized_offset+mas4_2_tsized_q'length-1), + scout => bsov(mas4_2_tsized_offset to mas4_2_tsized_offset+mas4_2_tsized_q'length-1), + din => mas4_2_tsized_d(0 to mas4_2_tsized_d'length-1), + dout => mas4_2_tsized_q(0 to mas4_2_tsized_q'length-1) ); +mas4_2_wimged_latch: tri_rlmreg_p + generic map (width => mas4_2_wimged_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(mas4_2_wimged_offset to mas4_2_wimged_offset+mas4_2_wimged_q'length-1), + scout => bsov(mas4_2_wimged_offset to mas4_2_wimged_offset+mas4_2_wimged_q'length-1), + din => mas4_2_wimged_d(0 to mas4_2_wimged_d'length-1), + dout => mas4_2_wimged_q(0 to mas4_2_wimged_q'length-1) ); +mas5_2_sgs_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas5_2_sgs_offset), + scout => sov_1(mas5_2_sgs_offset), + din => mas5_2_sgs_d, + dout => mas5_2_sgs_q); +mas5_2_slpid_latch: tri_rlmreg_p + generic map (width => mas5_2_slpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas5_2_slpid_offset to mas5_2_slpid_offset+mas5_2_slpid_q'length-1), + scout => sov_1(mas5_2_slpid_offset to mas5_2_slpid_offset+mas5_2_slpid_q'length-1), + din => mas5_2_slpid_d(0 to mas5_2_slpid_d'length-1), + dout => mas5_2_slpid_q(0 to mas5_2_slpid_q'length-1) ); +mas6_2_spid_latch: tri_rlmreg_p + generic map (width => mas6_2_spid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas6_2_spid_offset to mas6_2_spid_offset+mas6_2_spid_q'length-1), + scout => sov_1(mas6_2_spid_offset to mas6_2_spid_offset+mas6_2_spid_q'length-1), + din => mas6_2_spid_d(0 to mas6_2_spid_d'length-1), + dout => mas6_2_spid_q(0 to mas6_2_spid_q'length-1) ); +mas6_2_isize_latch: tri_rlmreg_p + generic map (width => mas6_2_isize_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas6_2_isize_offset to mas6_2_isize_offset+mas6_2_isize_q'length-1), + scout => sov_1(mas6_2_isize_offset to mas6_2_isize_offset+mas6_2_isize_q'length-1), + din => mas6_2_isize_d(0 to mas6_2_isize_d'length-1), + dout => mas6_2_isize_q(0 to mas6_2_isize_q'length-1) ); +mas6_2_sind_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas6_2_sind_offset), + scout => sov_1(mas6_2_sind_offset), + din => mas6_2_sind_d, + dout => mas6_2_sind_q); +mas6_2_sas_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas6_2_sas_offset), + scout => sov_1(mas6_2_sas_offset), + din => mas6_2_sas_d, + dout => mas6_2_sas_q); +mas7_2_rpnu_latch: tri_rlmreg_p + generic map (width => mas7_2_rpnu_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas7_2_rpnu_offset to mas7_2_rpnu_offset+mas7_2_rpnu_q'length-1), + scout => sov_1(mas7_2_rpnu_offset to mas7_2_rpnu_offset+mas7_2_rpnu_q'length-1), + din => mas7_2_rpnu_d(22 to 22+mas7_2_rpnu_d'length-1), + dout => mas7_2_rpnu_q(22 to 22+mas7_2_rpnu_q'length-1) ); +mas8_2_tgs_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas8_2_tgs_offset), + scout => sov_1(mas8_2_tgs_offset), + din => mas8_2_tgs_d, + dout => mas8_2_tgs_q); +mas8_2_vf_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas8_2_vf_offset), + scout => sov_1(mas8_2_vf_offset), + din => mas8_2_vf_d, + dout => mas8_2_vf_q); +mas8_2_tlpid_latch: tri_rlmreg_p + generic map (width => mas8_2_tlpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas8_2_tlpid_offset to mas8_2_tlpid_offset+mas8_2_tlpid_q'length-1), + scout => sov_1(mas8_2_tlpid_offset to mas8_2_tlpid_offset+mas8_2_tlpid_q'length-1), + din => mas8_2_tlpid_d(0 to mas8_2_tlpid_d'length-1), + dout => mas8_2_tlpid_q(0 to mas8_2_tlpid_q'length-1) ); +mas0_3_atsel_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas0_3_atsel_offset), + scout => sov_1(mas0_3_atsel_offset), + din => mas0_3_atsel_d, + dout => mas0_3_atsel_q); +mas0_3_esel_latch: tri_rlmreg_p + generic map (width => mas0_3_esel_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas0_3_esel_offset to mas0_3_esel_offset+mas0_3_esel_q'length-1), + scout => sov_1(mas0_3_esel_offset to mas0_3_esel_offset+mas0_3_esel_q'length-1), + din => mas0_3_esel_d(0 to mas0_3_esel_d'length-1), + dout => mas0_3_esel_q(0 to mas0_3_esel_q'length-1) ); +mas0_3_hes_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas0_3_hes_offset), + scout => sov_1(mas0_3_hes_offset), + din => mas0_3_hes_d, + dout => mas0_3_hes_q); +mas0_3_wq_latch: tri_rlmreg_p + generic map (width => mas0_3_wq_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas0_3_wq_offset to mas0_3_wq_offset+mas0_3_wq_q'length-1), + scout => sov_1(mas0_3_wq_offset to mas0_3_wq_offset+mas0_3_wq_q'length-1), + din => mas0_3_wq_d(0 to mas0_3_wq_d'length-1), + dout => mas0_3_wq_q(0 to mas0_3_wq_q'length-1) ); +mas1_3_v_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas1_3_v_offset), + scout => sov_1(mas1_3_v_offset), + din => mas1_3_v_d, + dout => mas1_3_v_q); +mas1_3_iprot_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas1_3_iprot_offset), + scout => sov_1(mas1_3_iprot_offset), + din => mas1_3_iprot_d, + dout => mas1_3_iprot_q); +mas1_3_tid_latch: tri_rlmreg_p + generic map (width => mas1_3_tid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas1_3_tid_offset to mas1_3_tid_offset+mas1_3_tid_q'length-1), + scout => sov_1(mas1_3_tid_offset to mas1_3_tid_offset+mas1_3_tid_q'length-1), + din => mas1_3_tid_d(0 to mas1_3_tid_d'length-1), + dout => mas1_3_tid_q(0 to mas1_3_tid_q'length-1) ); +mas1_3_ind_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas1_3_ind_offset), + scout => sov_1(mas1_3_ind_offset), + din => mas1_3_ind_d, + dout => mas1_3_ind_q); +mas1_3_ts_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas1_3_ts_offset), + scout => sov_1(mas1_3_ts_offset), + din => mas1_3_ts_d, + dout => mas1_3_ts_q); +mas1_3_tsize_latch: tri_rlmreg_p + generic map (width => mas1_3_tsize_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas1_3_tsize_offset to mas1_3_tsize_offset+mas1_3_tsize_q'length-1), + scout => sov_1(mas1_3_tsize_offset to mas1_3_tsize_offset+mas1_3_tsize_q'length-1), + din => mas1_3_tsize_d(0 to mas1_3_tsize_d'length-1), + dout => mas1_3_tsize_q(0 to mas1_3_tsize_q'length-1) ); +mas2_3_epn_latch: tri_rlmreg_p + generic map (width => mas2_3_epn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas2_3_epn_offset to mas2_3_epn_offset+mas2_3_epn_q'length-1), + scout => sov_1(mas2_3_epn_offset to mas2_3_epn_offset+mas2_3_epn_q'length-1), + din => mas2_3_epn_d(52-mas2_3_epn_d'length to 51), + dout => mas2_3_epn_q(52-mas2_3_epn_q'length to 51) ); +mas2_3_wimge_latch: tri_rlmreg_p + generic map (width => mas2_3_wimge_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas2_3_wimge_offset to mas2_3_wimge_offset+mas2_3_wimge_q'length-1), + scout => sov_1(mas2_3_wimge_offset to mas2_3_wimge_offset+mas2_3_wimge_q'length-1), + din => mas2_3_wimge_d(0 to mas2_3_wimge_d'length-1), + dout => mas2_3_wimge_q(0 to mas2_3_wimge_q'length-1) ); +mas3_3_rpnl_latch: tri_rlmreg_p + generic map (width => mas3_3_rpnl_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas3_3_rpnl_offset to mas3_3_rpnl_offset+mas3_3_rpnl_q'length-1), + scout => sov_1(mas3_3_rpnl_offset to mas3_3_rpnl_offset+mas3_3_rpnl_q'length-1), + din => mas3_3_rpnl_d(32 to 32+mas3_3_rpnl_d'length-1), + dout => mas3_3_rpnl_q(32 to 32+mas3_3_rpnl_q'length-1) ); +mas3_3_ubits_latch: tri_rlmreg_p + generic map (width => mas3_3_ubits_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas3_3_ubits_offset to mas3_3_ubits_offset+mas3_3_ubits_q'length-1), + scout => sov_1(mas3_3_ubits_offset to mas3_3_ubits_offset+mas3_3_ubits_q'length-1), + din => mas3_3_ubits_d(0 to mas3_3_ubits_d'length-1), + dout => mas3_3_ubits_q(0 to mas3_3_ubits_q'length-1) ); +mas3_3_usxwr_latch: tri_rlmreg_p + generic map (width => mas3_3_usxwr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas3_3_usxwr_offset to mas3_3_usxwr_offset+mas3_3_usxwr_q'length-1), + scout => sov_1(mas3_3_usxwr_offset to mas3_3_usxwr_offset+mas3_3_usxwr_q'length-1), + din => mas3_3_usxwr_d(0 to mas3_3_usxwr_d'length-1), + dout => mas3_3_usxwr_q(0 to mas3_3_usxwr_q'length-1) ); +mas4_3_indd_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(mas4_3_indd_offset), + scout => bsov(mas4_3_indd_offset), + din => mas4_3_indd_d, + dout => mas4_3_indd_q); +mas4_3_tsized_latch: tri_rlmreg_p + generic map (width => mas4_3_tsized_q'length, init => 1, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(mas4_3_tsized_offset to mas4_3_tsized_offset+mas4_3_tsized_q'length-1), + scout => bsov(mas4_3_tsized_offset to mas4_3_tsized_offset+mas4_3_tsized_q'length-1), + din => mas4_3_tsized_d(0 to mas4_3_tsized_d'length-1), + dout => mas4_3_tsized_q(0 to mas4_3_tsized_q'length-1) ); +mas4_3_wimged_latch: tri_rlmreg_p + generic map (width => mas4_3_wimged_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(mas4_3_wimged_offset to mas4_3_wimged_offset+mas4_3_wimged_q'length-1), + scout => bsov(mas4_3_wimged_offset to mas4_3_wimged_offset+mas4_3_wimged_q'length-1), + din => mas4_3_wimged_d(0 to mas4_3_wimged_d'length-1), + dout => mas4_3_wimged_q(0 to mas4_3_wimged_q'length-1) ); +mas5_3_sgs_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas5_3_sgs_offset), + scout => sov_1(mas5_3_sgs_offset), + din => mas5_3_sgs_d, + dout => mas5_3_sgs_q); +mas5_3_slpid_latch: tri_rlmreg_p + generic map (width => mas5_3_slpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas5_3_slpid_offset to mas5_3_slpid_offset+mas5_3_slpid_q'length-1), + scout => sov_1(mas5_3_slpid_offset to mas5_3_slpid_offset+mas5_3_slpid_q'length-1), + din => mas5_3_slpid_d(0 to mas5_3_slpid_d'length-1), + dout => mas5_3_slpid_q(0 to mas5_3_slpid_q'length-1) ); +mas6_3_spid_latch: tri_rlmreg_p + generic map (width => mas6_3_spid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas6_3_spid_offset to mas6_3_spid_offset+mas6_3_spid_q'length-1), + scout => sov_1(mas6_3_spid_offset to mas6_3_spid_offset+mas6_3_spid_q'length-1), + din => mas6_3_spid_d(0 to mas6_3_spid_d'length-1), + dout => mas6_3_spid_q(0 to mas6_3_spid_q'length-1) ); +mas6_3_isize_latch: tri_rlmreg_p + generic map (width => mas6_3_isize_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas6_3_isize_offset to mas6_3_isize_offset+mas6_3_isize_q'length-1), + scout => sov_1(mas6_3_isize_offset to mas6_3_isize_offset+mas6_3_isize_q'length-1), + din => mas6_3_isize_d(0 to mas6_3_isize_d'length-1), + dout => mas6_3_isize_q(0 to mas6_3_isize_q'length-1) ); +mas6_3_sind_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas6_3_sind_offset), + scout => sov_1(mas6_3_sind_offset), + din => mas6_3_sind_d, + dout => mas6_3_sind_q); +mas6_3_sas_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas6_3_sas_offset), + scout => sov_1(mas6_3_sas_offset), + din => mas6_3_sas_d, + dout => mas6_3_sas_q); +mas7_3_rpnu_latch: tri_rlmreg_p + generic map (width => mas7_3_rpnu_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas7_3_rpnu_offset to mas7_3_rpnu_offset+mas7_3_rpnu_q'length-1), + scout => sov_1(mas7_3_rpnu_offset to mas7_3_rpnu_offset+mas7_3_rpnu_q'length-1), + din => mas7_3_rpnu_d(22 to 22+mas7_3_rpnu_d'length-1), + dout => mas7_3_rpnu_q(22 to 22+mas7_3_rpnu_q'length-1) ); +mas8_3_tgs_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas8_3_tgs_offset), + scout => sov_1(mas8_3_tgs_offset), + din => mas8_3_tgs_d, + dout => mas8_3_tgs_q); +mas8_3_vf_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas8_3_vf_offset), + scout => sov_1(mas8_3_vf_offset), + din => mas8_3_vf_d, + dout => mas8_3_vf_q); +mas8_3_tlpid_latch: tri_rlmreg_p + generic map (width => mas8_3_tlpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mas8_3_tlpid_offset to mas8_3_tlpid_offset+mas8_3_tlpid_q'length-1), + scout => sov_1(mas8_3_tlpid_offset to mas8_3_tlpid_offset+mas8_3_tlpid_q'length-1), + din => mas8_3_tlpid_d(0 to mas8_3_tlpid_d'length-1), + dout => mas8_3_tlpid_q(0 to mas8_3_tlpid_q'length-1) ); +mmucsr0_tlb0fi_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mmucsr0_tlb0fi_offset), + scout => sov_1(mmucsr0_tlb0fi_offset), + din => mmucsr0_tlb0fi_d, + dout => mmucsr0_tlb0fi_q); +lper_0_alpn_latch: tri_rlmreg_p + generic map (width => lper_0_alpn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(lper_0_alpn_offset to lper_0_alpn_offset+lper_0_alpn_q'length-1), + scout => sov_1(lper_0_alpn_offset to lper_0_alpn_offset+lper_0_alpn_q'length-1), + din => lper_0_alpn_d, + dout => lper_0_alpn_q ); +lper_0_lps_latch: tri_rlmreg_p + generic map (width => lper_0_lps_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(lper_0_lps_offset to lper_0_lps_offset+lper_0_lps_q'length-1), + scout => sov_1(lper_0_lps_offset to lper_0_lps_offset+lper_0_lps_q'length-1), + din => lper_0_lps_d, + dout => lper_0_lps_q ); +lper_1_alpn_latch: tri_rlmreg_p + generic map (width => lper_1_alpn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(lper_1_alpn_offset to lper_1_alpn_offset+lper_1_alpn_q'length-1), + scout => sov_1(lper_1_alpn_offset to lper_1_alpn_offset+lper_1_alpn_q'length-1), + din => lper_1_alpn_d, + dout => lper_1_alpn_q ); +lper_1_lps_latch: tri_rlmreg_p + generic map (width => lper_1_lps_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(lper_1_lps_offset to lper_1_lps_offset+lper_1_lps_q'length-1), + scout => sov_1(lper_1_lps_offset to lper_1_lps_offset+lper_1_lps_q'length-1), + din => lper_1_lps_d, + dout => lper_1_lps_q ); +lper_2_alpn_latch: tri_rlmreg_p + generic map (width => lper_2_alpn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(lper_2_alpn_offset to lper_2_alpn_offset+lper_2_alpn_q'length-1), + scout => sov_1(lper_2_alpn_offset to lper_2_alpn_offset+lper_2_alpn_q'length-1), + din => lper_2_alpn_d, + dout => lper_2_alpn_q ); +lper_2_lps_latch: tri_rlmreg_p + generic map (width => lper_2_lps_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(lper_2_lps_offset to lper_2_lps_offset+lper_2_lps_q'length-1), + scout => sov_1(lper_2_lps_offset to lper_2_lps_offset+lper_2_lps_q'length-1), + din => lper_2_lps_d, + dout => lper_2_lps_q ); +lper_3_alpn_latch: tri_rlmreg_p + generic map (width => lper_3_alpn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(lper_3_alpn_offset to lper_3_alpn_offset+lper_3_alpn_q'length-1), + scout => sov_1(lper_3_alpn_offset to lper_3_alpn_offset+lper_3_alpn_q'length-1), + din => lper_3_alpn_d, + dout => lper_3_alpn_q ); +lper_3_lps_latch: tri_rlmreg_p + generic map (width => lper_3_lps_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cat_emf_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(lper_3_lps_offset to lper_3_lps_offset+lper_3_lps_q'length-1), + scout => sov_1(lper_3_lps_offset to lper_3_lps_offset+lper_3_lps_q'length-1), + din => lper_3_lps_d, + dout => lper_3_lps_q ); +spr_mmu_act_latch: tri_rlmreg_p + generic map (width => spr_mmu_act_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spr_mmu_act_offset to spr_mmu_act_offset+spr_mmu_act_q'length-1), + scout => sov_0(spr_mmu_act_offset to spr_mmu_act_offset+spr_mmu_act_q'length-1), + din => spr_mmu_act_d, + dout => spr_mmu_act_q ); +spr_val_act_latch: tri_rlmreg_p + generic map (width => spr_val_act_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spr_val_act_offset to spr_val_act_offset+spr_val_act_q'length-1), + scout => sov_0(spr_val_act_offset to spr_val_act_offset+spr_val_act_q'length-1), + din => spr_val_act_d, + dout => spr_val_act_q ); +cswitch_latch: tri_rlmreg_p + generic map (width => cswitch_q'length, init => mmq_spr_cswitch_0to3, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(cswitch_offset to cswitch_offset+cswitch_q'length-1), + scout => sov_0(cswitch_offset to cswitch_offset+cswitch_q'length-1), + din => cswitch_q, + dout => cswitch_q ); +-- cswitch0: 1=disable side affect of clearing I/D/TERRDET and EEN when reading mmucr1 +-- cswitch1: 1=disable mmucr1.tlbwe_binv bit (make it look like it is reserved per dd1) +-- cswitch2: reserved +-- cswitch3: reserved +cat_emf_act_latch: tri_rlmreg_p + generic map (width => cat_emf_act_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(cat_emf_act_offset to cat_emf_act_offset+cat_emf_act_q'length-1), + scout => sov_1(cat_emf_act_offset to cat_emf_act_offset+cat_emf_act_q'length-1), + din => cat_emf_act_d, + dout => cat_emf_act_q ); +spare_a_latch: tri_rlmreg_p + generic map (width => spare_a_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spare_a_offset to spare_a_offset+spare_a_q'length-1), + scout => sov_0(spare_a_offset to spare_a_offset+spare_a_q'length-1), + din => spare_a_q, + dout => spare_a_q ); +spare_b_latch: tri_rlmreg_p + generic map (width => spare_b_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spare_b_offset to spare_b_offset+spare_b_q'length-1), + scout => sov_1(spare_b_offset to spare_b_offset+spare_b_q'length-1), + din => spare_b_q, + dout => spare_b_q ); +-- non-scannable timing latches +iu_mm_ierat_mmucr0_latch : tri_regk + generic map (width => iu_mm_ierat_mmucr0_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => pc_func_slp_nsl_force, + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_nsl_thold_0_b, + din => iu_mm_ierat_mmucr0, + dout => iu_mm_ierat_mmucr0_q); +iu_mm_ierat_mmucr0_we_latch : tri_regk + generic map (width => iu_mm_ierat_mmucr0_we_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => pc_func_slp_nsl_force, + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_nsl_thold_0_b, + din => iu_mm_ierat_mmucr0_we, + dout => iu_mm_ierat_mmucr0_we_q); +iu_mm_ierat_mmucr1_latch : tri_regk + generic map (width => iu_mm_ierat_mmucr1_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => pc_func_slp_nsl_force, + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_nsl_thold_0_b, + din => iu_mm_ierat_mmucr1, + dout => iu_mm_ierat_mmucr1_q); +xu_mm_derat_mmucr0_latch : tri_regk + generic map (width => xu_mm_derat_mmucr0_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => pc_func_slp_nsl_force, + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_nsl_thold_0_b, + din => xu_mm_derat_mmucr0, + dout => xu_mm_derat_mmucr0_q); +xu_mm_derat_mmucr0_we_latch : tri_regk + generic map (width => xu_mm_derat_mmucr0_we_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => pc_func_slp_nsl_force, + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_nsl_thold_0_b, + din => xu_mm_derat_mmucr0_we, + dout => xu_mm_derat_mmucr0_we_q); +xu_mm_derat_mmucr1_latch : tri_regk + generic map (width => xu_mm_derat_mmucr1_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => pc_func_slp_nsl_force, + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_nsl_thold_0_b, + din => xu_mm_derat_mmucr1, + dout => xu_mm_derat_mmucr1_q); +mm_erat_mmucr1_we_latch : tri_regk + generic map (width => 2, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => pc_func_slp_nsl_force, + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_nsl_thold_0_b, + din(0) => iu_mm_ierat_mmucr1_we, + din(1) => xu_mm_derat_mmucr1_we, + dout(0) => iu_mm_ierat_mmucr1_we_q, + dout(1) => xu_mm_derat_mmucr1_we_q); +-------------------------------------------------- +-- scan only latches for boot config +-- mmucr1, mmucr2, and mmucr3 also in boot config +-------------------------------------------------- +mpg_bcfg_gen: if expand_type /= 1 generate +mmucfg_47to48_latch: tri_slat_scan + generic map (width => 2, init => std_ulogic_vector( to_unsigned( bcfg_mmucfg_value, 2 ) ), + reset_inverts_scan => true, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + dclk => lcb_dclk, + lclk => lcb_lclk, + scan_in => bsiv(mmucfg_offset to mmucfg_offset+1), + scan_out => bsov(mmucfg_offset to mmucfg_offset+1), + q => mmucfg_q(47 to 48), + q_b => mmucfg_q_b(47 to 48) ); +tlb0cfg_45to47_latch: tri_slat_scan + generic map (width => 3, init => std_ulogic_vector( to_unsigned( bcfg_tlb0cfg_value, 3 ) ), + reset_inverts_scan => true, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + dclk => lcb_dclk, + lclk => lcb_lclk, + scan_in => bsiv(tlb0cfg_offset to tlb0cfg_offset+2), + scan_out => bsov(tlb0cfg_offset to tlb0cfg_offset+2), + q => tlb0cfg_q(45 to 47), + q_b => tlb0cfg_q_b(45 to 47) ); +bcfg_spare_latch: tri_slat_scan + generic map (width => 16, init => std_ulogic_vector( to_unsigned( 0, 16 ) ), + reset_inverts_scan => true, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + dclk => lcb_dclk, + lclk => lcb_lclk, + scan_in => bsiv(bcfg_spare_offset to bcfg_spare_offset+bcfg_spare_q'length-1), + scan_out => bsov(bcfg_spare_offset to bcfg_spare_offset+bcfg_spare_q'length-1), + q => bcfg_spare_q, + q_b => bcfg_spare_q_b ); +end generate mpg_bcfg_gen; +fpga_bcfg_gen: if expand_type = 1 generate +mmucfg_47to48_latch: tri_rlmreg_p + generic map (width => 2, init => bcfg_mmucfg_value, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(mmucfg_offset to mmucfg_offset+1), + scout => bsov(mmucfg_offset to mmucfg_offset+1), + din => mmucfg_q(47 to 48), + dout => mmucfg_q(47 to 48) ); +tlb0cfg_45to47_latch: tri_rlmreg_p + generic map (width => 3, init => bcfg_tlb0cfg_value, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(tlb0cfg_offset to tlb0cfg_offset+2), + scout => bsov(tlb0cfg_offset to tlb0cfg_offset+2), + din => tlb0cfg_q(45 to 47), + dout => tlb0cfg_q(45 to 47) ); +bcfg_spare_latch: tri_rlmreg_p + generic map (width => 16, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(bcfg_spare_offset to bcfg_spare_offset+bcfg_spare_q'length-1), + scout => bsov(bcfg_spare_offset to bcfg_spare_offset+bcfg_spare_q'length-1), + din => bcfg_spare_q, + dout => bcfg_spare_q ); +end generate fpga_bcfg_gen; +-- Latch counts +-- 3319 +-- spr_ctl_in_q 3 +-- spr_etid_in_q 2 +-- spr_addr_in_q 10 +-- spr_data_in_q 64 79 +-- spr_ctl_int_q 3 +-- spr_etid_int_q 2 +-- spr_addr_int_q 10 +-- spr_data_int_q 64 79 +-- spr_ctl_out_q 3 +-- spr_etid_out_q 2 +-- spr_addr_out_q 10 +-- spr_data_out_q 64 79 +-- lper_ 0:3 _alpn_q 30 x 4 +-- lper_ 0:3 _lps_q 4 x 4 136 +-- pid 0:3 _q 14 x 4 +-- mmucr0_ 0:3 _q 20 x 4 +-- mmucr1_q 32 +-- mmucr2_q 32 +-- mmucr3_ 0:3 _q 15 x 4 +-- lpidr_q 8 +-- mmucsr0_tlb0fi_q 1 269 +-- mas0__atsel_q 1 x 4 : std_ulogic; +-- mas0__esel_q 3 x 4 : std_ulogic_vector(0 to 2); +-- mas0__hes_q 1 x 4 : std_ulogic; +-- mas0__wq_q 2 x 4 : std_ulogic_vector(0 to 1); +-- mas1__v_q 1 x 4 : std_ulogic; +-- mas1__iprot_q 1 x 4 : std_ulogic; +-- mas1__tid_q 14 x 4 : std_ulogic_vector(0 to 13); +-- mas1__ind_q 1 x 4 : std_ulogic; +-- mas1__ts_q 1 x 4 : std_ulogic; +-- mas1__tsize_q 4 x 4 : std_ulogic_vector(0 to 3); +-- mas2__epn_q 52 x 4 : std_ulogic_vector(64-spr_data_width to 51); +-- mas2__wimge_q 5 x 4 : std_ulogic_vector(0 to 4); +-- mas3__rpnl_q 21 x 4 : std_ulogic_vector(32 to 52); +-- mas3__ubits_q 4 x 4 : std_ulogic_vector(0 to 3); +-- mas3__usxwr_q 6 x 4 : std_ulogic_vector(0 to 5); +-- mas4__indd_q 1 x 4 : std_ulogic; +-- mas4__tsized_q 4 x 4 : std_ulogic_vector(0 to 3); +-- mas4__wimged_q 5 x 4 : std_ulogic_vector(0 to 4); +-- mas5__sgs_q 1 x 4 : std_ulogic; +-- mas5__slpid_q 8 x 4 : std_ulogic_vector(0 to 7); +-- mas6__spid_q 14 x 4 : std_ulogic_vector(0 to 13); +-- mas6__isize_q 4 x 4 : std_ulogic_vector(0 to 3); +-- mas6__sind_q 1 x 4 : std_ulogic; +-- mas6__sas_q 1 x 4 : std_ulogic; +-- mas7__rpnu_q 10 x 4 : std_ulogic_vector(22 to 31); +-- mas8__tgs_q 1 x 4 : std_ulogic; +-- mas8__vf_q 1 x 4 : std_ulogic; +-- mas8__tlpid_q 8 x 4 : std_ulogic_vector(0 to 7); +-- subtotal 176 x 4 = 704 +---------------------------------------------------------------- +-- total 1346 +-------------------------------------------------- +-------------------------------------------------- +-- thold/sg latches +-------------------------------------------------- +perv_2to1_reg: tri_plat + generic map (width => 7, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ccflush_dc, + din(0) => pc_func_sl_thold_2, + din(1) => pc_func_slp_sl_thold_2, + din(2) => pc_cfg_sl_thold_2, + din(3) => pc_cfg_slp_sl_thold_2, + din(4) => pc_func_slp_nsl_thold_2, + din(5) => pc_sg_2, + din(6) => pc_fce_2, + q(0) => pc_func_sl_thold_1, + q(1) => pc_func_slp_sl_thold_1, + q(2) => pc_cfg_sl_thold_1, + q(3) => pc_cfg_slp_sl_thold_1, + q(4) => pc_func_slp_nsl_thold_1, + q(5) => pc_sg_1, + q(6) => pc_fce_1); +perv_1to0_reg: tri_plat + generic map (width => 7, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ccflush_dc, + din(0) => pc_func_sl_thold_1, + din(1) => pc_func_slp_sl_thold_1, + din(2) => pc_cfg_sl_thold_1, + din(3) => pc_cfg_slp_sl_thold_1, + din(4) => pc_func_slp_nsl_thold_1, + din(5) => pc_sg_1, + din(6) => pc_fce_1, + q(0) => pc_func_sl_thold_0, + q(1) => pc_func_slp_sl_thold_0, + q(2) => pc_cfg_sl_thold_0, + q(3) => pc_cfg_slp_sl_thold_0, + q(4) => pc_func_slp_nsl_thold_0, + q(5) => pc_sg_0, + q(6) => pc_fce_0); +perv_lcbor_func_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b, + thold => pc_func_sl_thold_0, + sg => pc_sg_0, + act_dis => lcb_act_dis_dc, + forcee => pc_func_sl_force, + thold_b => pc_func_sl_thold_0_b); +perv_lcbor_func_slp_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b, + thold => pc_func_slp_sl_thold_0, + sg => pc_sg_0, + act_dis => lcb_act_dis_dc, + forcee => pc_func_slp_sl_force, + thold_b => pc_func_slp_sl_thold_0_b); +perv_lcbor_cfg_slp_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b, + thold => pc_cfg_slp_sl_thold_0, + sg => pc_sg_0, + act_dis => lcb_act_dis_dc, + forcee => pc_cfg_slp_sl_force, + thold_b => pc_cfg_slp_sl_thold_0_b); +perv_lcbor_func_slp_nsl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b, + thold => pc_func_slp_nsl_thold_0, + sg => pc_fce_0, + act_dis => tidn, + forcee => pc_func_slp_nsl_force, + thold_b => pc_func_slp_nsl_thold_0_b); +-- these terms in the absence of another lcbor component +-- that drives the thold_b and force into the bcfg_lcb for slat's +pc_cfg_sl_thold_0_b <= NOT pc_cfg_sl_thold_0; +pc_cfg_sl_force <= pc_sg_0; +-------------------------------------------------- +-- local clock buffer for boot config +-------------------------------------------------- +bcfg_lcb: tri_lcbs + generic map (expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + delay_lclkr => lcb_delay_lclkr_dc(0), + nclk => nclk, + forcee => pc_cfg_sl_force, + thold_b => pc_cfg_sl_thold_0_b, + dclk => lcb_dclk, + lclk => lcb_lclk ); +----------------------------------------------------------------------- +-- Scan +----------------------------------------------------------------------- +siv_0(0 to scan_right_0) <= sov_0(1 to scan_right_0) & ac_func_scan_in(0); +ac_func_scan_out(0) <= sov_0(0); +siv_1(0 to scan_right_1) <= sov_1(1 to scan_right_1) & ac_func_scan_in(1); +ac_func_scan_out(1) <= sov_1(0); +bsiv(0 to boot_scan_right) <= bsov(1 to boot_scan_right) & ac_bcfg_scan_in; +ac_bcfg_scan_out <= bsov(0); +end mmq_spr; diff --git a/rel/src/vhdl/work/mmq_tlb_cmp.vhdl b/rel/src/vhdl/work/mmq_tlb_cmp.vhdl new file mode 100644 index 0000000..22e0104 --- /dev/null +++ b/rel/src/vhdl/work/mmq_tlb_cmp.vhdl @@ -0,0 +1,6276 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +--******************************************************************** +--* TITLE: Memory Management Unit TLB Compare Logic +--* NAME: mmq_tlb_cmp.vhdl +--********************************************************************* + +library ieee; +use ieee.std_logic_1164.all; +library ibm; +use ibm.std_ulogic_unsigned.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_support.all; +library support; +use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity mmq_tlb_cmp is + generic(thdid_width : integer := 4; + ttype_width : integer := 4; + state_width : integer := 3; + pid_width : integer := 14; + pid_width_erat : integer := 8; + lpid_width : integer := 8; + class_width : integer := 2; + extclass_width : integer := 2; + tlbsel_width : integer := 2; + epn_width : integer := 52; + vpn_width : integer := 61; + erat_cam_data_width : integer := 75; + erat_ary_data_width : integer := 73; + erat_rel_data_width : integer := 132; + ws_width : integer := 2; + rs_is_width : integer := 9; + ra_entry_width : integer := 12; + rs_data_width : integer := 64; + data_out_width : integer := 64; + error_width : integer := 3; + tlb_num_entry : natural := 512; + tlb_num_entry_log2 : natural := 9; + tlb_ways : natural := 4; + tlb_addr_width : natural := 7; + tlb_way_width : natural := 168; + tlb_word_width : natural := 84; + tlb_seq_width : integer := 6; + inv_seq_width : integer := 5; + por_seq_width : integer := 3; + watermark_width : integer := 4; + eptr_width : integer := 4; + lru_width : integer := 16; + mmucr0_width : integer := 20; + mmucr1_width : integer := 32; + mmucr2_width : integer := 32; + mmucr3_width : integer := 15; + spr_ctl_width : integer := 3; + spr_etid_width : integer := 2; + spr_addr_width : integer := 10; + spr_data_width : integer := 64; + debug_trace_width : integer := 88; + debug_event_width : integer := 16; + real_addr_width : integer := 42; + rpn_width : integer := 30; + pte_width : integer := 64; + check_parity : integer := 1; + tlb_tag_width : natural := 110; + mmq_tlb_cmp_cswitch_0to7 : integer := 0; + expand_type : integer := 2 ); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + +tc_ccflush_dc : in std_ulogic; +tc_scan_dis_dc_b : in std_ulogic; +tc_scan_diag_dc : in std_ulogic; +tc_lbist_en_dc : in std_ulogic; +lcb_d_mode_dc : in std_ulogic; +lcb_clkoff_dc_b : in std_ulogic; +lcb_act_dis_dc : in std_ulogic; +lcb_mpw1_dc_b : in std_ulogic_vector(0 to 4); +lcb_mpw2_dc_b : in std_ulogic; +lcb_delay_lclkr_dc : in std_ulogic_vector(0 to 4); +ac_func_scan_in :in std_ulogic_vector(0 to 2); +ac_func_scan_out :out std_ulogic_vector(0 to 2); +pc_sg_2 : in std_ulogic; +pc_func_sl_thold_2 : in std_ulogic; +pc_func_slp_sl_thold_2 : in std_ulogic; +pc_func_slp_nsl_thold_2 : in std_ulogic; +pc_fce_2 : in std_ulogic; +xu_mm_ccr2_notlb_b : in std_ulogic; +xu_mm_spr_epcr_dmiuh : in std_ulogic_vector(0 to thdid_width-1); +xu_mm_epcr_dgtmi : in std_ulogic_vector(0 to thdid_width-1); +xu_mm_msr_gs : in std_ulogic_vector(0 to thdid_width-1); +xu_mm_msr_pr : in std_ulogic_vector(0 to thdid_width-1); +xu_mm_xucr4_mmu_mchk_q : in std_ulogic; +lpidr : in std_ulogic_vector(0 to lpid_width-1); +mmucr1 : in std_ulogic_vector(10 to 18); +mmucr3_0 : in std_ulogic_vector(64-mmucr3_width to 63); +mmucr3_1 : in std_ulogic_vector(64-mmucr3_width to 63); +mmucr3_2 : in std_ulogic_vector(64-mmucr3_width to 63); +mmucr3_3 : in std_ulogic_vector(64-mmucr3_width to 63); +mm_iu_ierat_rel_val : out std_ulogic_vector(0 to 4); +mm_iu_ierat_rel_data : out std_ulogic_vector(0 to erat_rel_data_width-1); +mm_xu_derat_rel_val : out std_ulogic_vector(0 to 4); +mm_xu_derat_rel_data : out std_ulogic_vector(0 to erat_rel_data_width-1); +tlb_cmp_ierat_dup_val : out std_ulogic_vector(0 to 6); +tlb_cmp_derat_dup_val : out std_ulogic_vector(0 to 6); +tlb_cmp_erat_dup_wait : out std_ulogic_vector(0 to 1); +ierat_req0_pid : in std_ulogic_vector(0 to pid_width-1); +ierat_req0_as : in std_ulogic; +ierat_req0_gs : in std_ulogic; +ierat_req0_epn : in std_ulogic_vector(0 to epn_width-1); +ierat_req0_thdid : in std_ulogic_vector(0 to thdid_width-1); +ierat_req0_valid : in std_ulogic; +ierat_req0_nonspec : in std_ulogic; +ierat_req1_pid : in std_ulogic_vector(0 to pid_width-1); +ierat_req1_as : in std_ulogic; +ierat_req1_gs : in std_ulogic; +ierat_req1_epn : in std_ulogic_vector(0 to epn_width-1); +ierat_req1_thdid : in std_ulogic_vector(0 to thdid_width-1); +ierat_req1_valid : in std_ulogic; +ierat_req1_nonspec : in std_ulogic; +ierat_req2_pid : in std_ulogic_vector(0 to pid_width-1); +ierat_req2_as : in std_ulogic; +ierat_req2_gs : in std_ulogic; +ierat_req2_epn : in std_ulogic_vector(0 to epn_width-1); +ierat_req2_thdid : in std_ulogic_vector(0 to thdid_width-1); +ierat_req2_valid : in std_ulogic; +ierat_req2_nonspec : in std_ulogic; +ierat_req3_pid : in std_ulogic_vector(0 to pid_width-1); +ierat_req3_as : in std_ulogic; +ierat_req3_gs : in std_ulogic; +ierat_req3_epn : in std_ulogic_vector(0 to epn_width-1); +ierat_req3_thdid : in std_ulogic_vector(0 to thdid_width-1); +ierat_req3_valid : in std_ulogic; +ierat_req3_nonspec : in std_ulogic; +ierat_iu4_pid : in std_ulogic_vector(0 to pid_width-1); +ierat_iu4_gs : in std_ulogic; +ierat_iu4_as : in std_ulogic; +ierat_iu4_epn : in std_ulogic_vector(0 to epn_width-1); +ierat_iu4_thdid : in std_ulogic_vector(0 to thdid_width-1); +ierat_iu4_valid : in std_ulogic; +derat_req0_lpid : in std_ulogic_vector(0 to lpid_width-1); +derat_req0_pid : in std_ulogic_vector(0 to pid_width-1); +derat_req0_as : in std_ulogic; +derat_req0_gs : in std_ulogic; +derat_req0_epn : in std_ulogic_vector(0 to epn_width-1); +derat_req0_thdid : in std_ulogic_vector(0 to thdid_width-1); +derat_req0_valid : in std_ulogic; +derat_req1_lpid : in std_ulogic_vector(0 to lpid_width-1); +derat_req1_pid : in std_ulogic_vector(0 to pid_width-1); +derat_req1_as : in std_ulogic; +derat_req1_gs : in std_ulogic; +derat_req1_epn : in std_ulogic_vector(0 to epn_width-1); +derat_req1_thdid : in std_ulogic_vector(0 to thdid_width-1); +derat_req1_valid : in std_ulogic; +derat_req2_lpid : in std_ulogic_vector(0 to lpid_width-1); +derat_req2_pid : in std_ulogic_vector(0 to pid_width-1); +derat_req2_as : in std_ulogic; +derat_req2_gs : in std_ulogic; +derat_req2_epn : in std_ulogic_vector(0 to epn_width-1); +derat_req2_thdid : in std_ulogic_vector(0 to thdid_width-1); +derat_req2_valid : in std_ulogic; +derat_req3_lpid : in std_ulogic_vector(0 to lpid_width-1); +derat_req3_pid : in std_ulogic_vector(0 to pid_width-1); +derat_req3_as : in std_ulogic; +derat_req3_gs : in std_ulogic; +derat_req3_epn : in std_ulogic_vector(0 to epn_width-1); +derat_req3_thdid : in std_ulogic_vector(0 to thdid_width-1); +derat_req3_valid : in std_ulogic; +derat_ex5_lpid : in std_ulogic_vector(0 to lpid_width-1); +derat_ex5_pid : in std_ulogic_vector(0 to pid_width-1); +derat_ex5_gs : in std_ulogic; +derat_ex5_as : in std_ulogic; +derat_ex5_epn : in std_ulogic_vector(0 to epn_width-1); +derat_ex5_thdid : in std_ulogic_vector(0 to thdid_width-1); +derat_ex5_valid : in std_ulogic; +tlb_tag2 : in std_ulogic_vector(0 to tlb_tag_width-1); +tlb_addr2 : in std_ulogic_vector(0 to tlb_addr_width-1); +ex6_illeg_instr : in std_ulogic_vector(0 to 1); +ierat_req_taken : in std_ulogic; +derat_req_taken : in std_ulogic; +ptereload_req_taken : in std_ulogic; +tlb_tag0_type : in std_ulogic_vector(0 to 1); +lrat_tag3_lpn : in std_ulogic_vector(64-real_addr_width to 51); +lrat_tag3_rpn : in std_ulogic_vector(64-real_addr_width to 51); +lrat_tag3_hit_status : in std_ulogic_vector(0 to 3); +lrat_tag3_hit_entry : in std_ulogic_vector(0 to 2); +lrat_tag4_lpn : in std_ulogic_vector(64-real_addr_width to 51); +lrat_tag4_rpn : in std_ulogic_vector(64-real_addr_width to 51); +lrat_tag4_hit_status : in std_ulogic_vector(0 to 3); +lrat_tag4_hit_entry : in std_ulogic_vector(0 to 2); +lru_dataout : in std_ulogic_vector(0 to 15); +tlb_dataout : in std_ulogic_vector(0 to tlb_way_width*tlb_ways-1); +tlb_dataina : out std_ulogic_vector(0 to tlb_way_width-1); +tlb_datainb : out std_ulogic_vector(0 to tlb_way_width-1); +lru_wr_addr : out std_ulogic_vector(0 to tlb_addr_width-1); +lru_write : out std_ulogic_vector(0 to 15); +lru_datain : out std_ulogic_vector(0 to 15); +lru_tag4_dataout : out std_ulogic_vector(0 to 15); +tlb_tag4_esel : out std_ulogic_vector(0 to 2); +tlb_tag4_wq : out std_ulogic_vector(0 to 1); +tlb_tag4_is : out std_ulogic_vector(0 to 1); +tlb_tag4_gs : out std_ulogic; +tlb_tag4_pr : out std_ulogic; +tlb_tag4_hes : out std_ulogic; +tlb_tag4_atsel : out std_ulogic; +tlb_tag4_pt : out std_ulogic; +tlb_tag4_cmp_hit : out std_ulogic; +tlb_tag4_way_ind : out std_ulogic; +tlb_tag4_ptereload : out std_ulogic; +tlb_tag4_endflag : out std_ulogic; +tlb_tag4_parerr : out std_ulogic; +tlb_tag5_except : out std_ulogic_vector(0 to thdid_width-1); +mmucfg_twc : in std_ulogic; +mmucfg_lrat : in std_ulogic; +tlb0cfg_pt : in std_ulogic; +tlb0cfg_gtwe : in std_ulogic; +tlb0cfg_ind : in std_ulogic; +mas2_0_wimge : in std_ulogic_vector(0 to 4); +mas3_0_rpnl : in std_ulogic_vector(32 to 52); +mas3_0_ubits : in std_ulogic_vector(0 to 3); +mas3_0_usxwr : in std_ulogic_vector(0 to 5); +mas7_0_rpnu : in std_ulogic_vector(22 to 31); +mas8_0_vf : in std_ulogic; +mas2_1_wimge : in std_ulogic_vector(0 to 4); +mas3_1_rpnl : in std_ulogic_vector(32 to 52); +mas3_1_ubits : in std_ulogic_vector(0 to 3); +mas3_1_usxwr : in std_ulogic_vector(0 to 5); +mas7_1_rpnu : in std_ulogic_vector(22 to 31); +mas8_1_vf : in std_ulogic; +mas2_2_wimge : in std_ulogic_vector(0 to 4); +mas3_2_rpnl : in std_ulogic_vector(32 to 52); +mas3_2_ubits : in std_ulogic_vector(0 to 3); +mas3_2_usxwr : in std_ulogic_vector(0 to 5); +mas7_2_rpnu : in std_ulogic_vector(22 to 31); +mas8_2_vf : in std_ulogic; +mas2_3_wimge : in std_ulogic_vector(0 to 4); +mas3_3_rpnl : in std_ulogic_vector(32 to 52); +mas3_3_ubits : in std_ulogic_vector(0 to 3); +mas3_3_usxwr : in std_ulogic_vector(0 to 5); +mas7_3_rpnu : in std_ulogic_vector(22 to 31); +mas8_3_vf : in std_ulogic; +tlb_mas0_esel : out std_ulogic_vector(0 to 2); +tlb_mas1_v : out std_ulogic; +tlb_mas1_iprot : out std_ulogic; +tlb_mas1_tid : out std_ulogic_vector(0 to pid_width-1); +tlb_mas1_tid_error : out std_ulogic_vector(0 to pid_width-1); +tlb_mas1_ind : out std_ulogic; +tlb_mas1_ts : out std_ulogic; +tlb_mas1_ts_error : out std_ulogic; +tlb_mas1_tsize : out std_ulogic_vector(0 to 3); +tlb_mas2_epn : out std_ulogic_vector(0 to epn_width-1); +tlb_mas2_epn_error : out std_ulogic_vector(0 to epn_width-1); +tlb_mas2_wimge : out std_ulogic_vector(0 to 4); +tlb_mas3_rpnl : out std_ulogic_vector(32 to 51); +tlb_mas3_ubits : out std_ulogic_vector(0 to 3); +tlb_mas3_usxwr : out std_ulogic_vector(0 to 5); +tlb_mas6_spid : out std_ulogic_vector(0 to pid_width-1); +tlb_mas6_isize : out std_ulogic_vector(0 to 3); +tlb_mas6_sind : out std_ulogic; +tlb_mas6_sas : out std_ulogic; +tlb_mas7_rpnu : out std_ulogic_vector(22 to 31); +tlb_mas8_tgs : out std_ulogic; +tlb_mas8_vf : out std_ulogic; +tlb_mas8_tlpid : out std_ulogic_vector(0 to 7); +tlb_mmucr1_een : out std_ulogic_vector(0 to 8); +tlb_mmucr1_we : out std_ulogic; +tlb_mmucr3_thdid : out std_ulogic_vector(0 to thdid_width-1); +tlb_mmucr3_resvattr : out std_ulogic; +tlb_mmucr3_wlc : out std_ulogic_vector(0 to 1); +tlb_mmucr3_class : out std_ulogic_vector(0 to class_width-1); +tlb_mmucr3_extclass : out std_ulogic_vector(0 to extclass_width-1); +tlb_mmucr3_rc : out std_ulogic_vector(0 to 1); +tlb_mmucr3_x : out std_ulogic; +tlb_mas_tlbre : out std_ulogic; +tlb_mas_tlbsx_hit : out std_ulogic; +tlb_mas_tlbsx_miss : out std_ulogic; +tlb_mas_dtlb_error : out std_ulogic; +tlb_mas_itlb_error : out std_ulogic; +tlb_mas_thdid : out std_ulogic_vector(0 to thdid_width-1); +tlb_htw_req_valid : out std_ulogic; +tlb_htw_req_tag : out std_ulogic_vector(0 to tlb_tag_width-1); +tlb_htw_req_way : out std_ulogic_vector(tlb_word_width to tlb_way_width-1); +tlbwe_back_inv_valid : out std_ulogic; +tlbwe_back_inv_thdid : out std_ulogic_vector(0 to thdid_width-1); +tlbwe_back_inv_addr : out std_ulogic_vector(52-epn_width to 51); +tlbwe_back_inv_attr : out std_ulogic_vector(0 to 34); +ptereload_req_pte_lat : in std_ulogic_vector(0 to pte_width-1); +tlb_ctl_tag2_flush : in std_ulogic_vector(0 to thdid_width-1); +tlb_ctl_tag3_flush : in std_ulogic_vector(0 to thdid_width-1); +tlb_ctl_tag4_flush : in std_ulogic_vector(0 to thdid_width-1); +tlb_resv_match_vec : in std_ulogic_vector(0 to thdid_width-1); +mm_xu_eratmiss_done : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_tlb_miss : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_tlb_inelig : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_lrat_miss : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_pt_fault : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_hv_priv : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_esr_pt : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_esr_data : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_esr_epid : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_esr_st : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_cr0_eq : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_cr0_eq_valid : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_tlb_multihit_err : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_tlb_par_err : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_lru_par_err : out std_ulogic_vector(0 to thdid_width-1); +tlb_delayed_act : in std_ulogic_vector(9 to 16); +tlb_cmp_perf_event_t0 : out std_ulogic_vector(0 to 9); +tlb_cmp_perf_event_t1 : out std_ulogic_vector(0 to 9); +tlb_cmp_perf_event_t2 : out std_ulogic_vector(0 to 9); +tlb_cmp_perf_event_t3 : out std_ulogic_vector(0 to 9); +tlb_cmp_perf_state : out std_ulogic_vector(0 to 1); +tlb_cmp_perf_miss_direct : out std_ulogic; +tlb_cmp_perf_hit_indirect : out std_ulogic; +tlb_cmp_perf_hit_first_page : out std_ulogic; +tlb_cmp_perf_ptereload_noexcep : out std_ulogic; +tlb_cmp_perf_lrat_request : out std_ulogic; +tlb_cmp_perf_lrat_miss : out std_ulogic; +tlb_cmp_perf_pt_fault : out std_ulogic; +tlb_cmp_perf_pt_inelig : out std_ulogic; +tlb_cmp_dbg_tag4 : out std_ulogic_vector(0 to tlb_tag_width-1); +tlb_cmp_dbg_tag4_wayhit : out std_ulogic_vector(0 to tlb_ways); +tlb_cmp_dbg_addr4 : out std_ulogic_vector(0 to tlb_addr_width-1); +tlb_cmp_dbg_tag4_way : out std_ulogic_vector(0 to tlb_way_width-1); +tlb_cmp_dbg_tag4_parerr : out std_ulogic_vector(0 to 4); +tlb_cmp_dbg_tag4_lru_dataout_q : out std_ulogic_vector(0 to 11); +tlb_cmp_dbg_tag5_tlb_datain_q : out std_ulogic_vector(0 to tlb_way_width-1); +tlb_cmp_dbg_tag5_lru_datain_q : out std_ulogic_vector(0 to 11); +tlb_cmp_dbg_tag5_lru_write : out std_ulogic; +tlb_cmp_dbg_tag5_any_exception : out std_ulogic; +tlb_cmp_dbg_tag5_except_type_q : out std_ulogic_vector(0 to 3); +tlb_cmp_dbg_tag5_except_thdid_q : out std_ulogic_vector(0 to 1); +tlb_cmp_dbg_tag5_erat_rel_val : out std_ulogic_vector(0 to 9); +tlb_cmp_dbg_tag5_erat_rel_data : out std_ulogic_vector(0 to 131); +tlb_cmp_dbg_erat_dup_q : out std_ulogic_vector(0 to 19); +tlb_cmp_dbg_addr_enable : out std_ulogic_vector(0 to 8); +tlb_cmp_dbg_pgsize_enable : out std_ulogic; +tlb_cmp_dbg_class_enable : out std_ulogic; +tlb_cmp_dbg_extclass_enable : out std_ulogic_vector(0 to 1); +tlb_cmp_dbg_state_enable : out std_ulogic_vector(0 to 1); +tlb_cmp_dbg_thdid_enable : out std_ulogic; +tlb_cmp_dbg_pid_enable : out std_ulogic; +tlb_cmp_dbg_lpid_enable : out std_ulogic; +tlb_cmp_dbg_ind_enable : out std_ulogic; +tlb_cmp_dbg_iprot_enable : out std_ulogic; +tlb_cmp_dbg_way0_entry_v : out std_ulogic; +tlb_cmp_dbg_way0_addr_match : out std_ulogic; +tlb_cmp_dbg_way0_pgsize_match : out std_ulogic; +tlb_cmp_dbg_way0_class_match : out std_ulogic; +tlb_cmp_dbg_way0_extclass_match : out std_ulogic; +tlb_cmp_dbg_way0_state_match : out std_ulogic; +tlb_cmp_dbg_way0_thdid_match : out std_ulogic; +tlb_cmp_dbg_way0_pid_match : out std_ulogic; +tlb_cmp_dbg_way0_lpid_match : out std_ulogic; +tlb_cmp_dbg_way0_ind_match : out std_ulogic; +tlb_cmp_dbg_way0_iprot_match : out std_ulogic; +tlb_cmp_dbg_way1_entry_v : out std_ulogic; +tlb_cmp_dbg_way1_addr_match : out std_ulogic; +tlb_cmp_dbg_way1_pgsize_match : out std_ulogic; +tlb_cmp_dbg_way1_class_match : out std_ulogic; +tlb_cmp_dbg_way1_extclass_match : out std_ulogic; +tlb_cmp_dbg_way1_state_match : out std_ulogic; +tlb_cmp_dbg_way1_thdid_match : out std_ulogic; +tlb_cmp_dbg_way1_pid_match : out std_ulogic; +tlb_cmp_dbg_way1_lpid_match : out std_ulogic; +tlb_cmp_dbg_way1_ind_match : out std_ulogic; +tlb_cmp_dbg_way1_iprot_match : out std_ulogic; +tlb_cmp_dbg_way2_entry_v : out std_ulogic; +tlb_cmp_dbg_way2_addr_match : out std_ulogic; +tlb_cmp_dbg_way2_pgsize_match : out std_ulogic; +tlb_cmp_dbg_way2_class_match : out std_ulogic; +tlb_cmp_dbg_way2_extclass_match : out std_ulogic; +tlb_cmp_dbg_way2_state_match : out std_ulogic; +tlb_cmp_dbg_way2_thdid_match : out std_ulogic; +tlb_cmp_dbg_way2_pid_match : out std_ulogic; +tlb_cmp_dbg_way2_lpid_match : out std_ulogic; +tlb_cmp_dbg_way2_ind_match : out std_ulogic; +tlb_cmp_dbg_way2_iprot_match : out std_ulogic; +tlb_cmp_dbg_way3_entry_v : out std_ulogic; +tlb_cmp_dbg_way3_addr_match : out std_ulogic; +tlb_cmp_dbg_way3_pgsize_match : out std_ulogic; +tlb_cmp_dbg_way3_class_match : out std_ulogic; +tlb_cmp_dbg_way3_extclass_match : out std_ulogic; +tlb_cmp_dbg_way3_state_match : out std_ulogic; +tlb_cmp_dbg_way3_thdid_match : out std_ulogic; +tlb_cmp_dbg_way3_pid_match : out std_ulogic; +tlb_cmp_dbg_way3_lpid_match : out std_ulogic; +tlb_cmp_dbg_way3_ind_match : out std_ulogic; +tlb_cmp_dbg_way3_iprot_match : out std_ulogic +); +end mmq_tlb_cmp; +ARCHITECTURE MMQ_TLB_CMP + OF MMQ_TLB_CMP + IS +--@@ Signal Declarations +SIGNAL LRU_UPDATE_DATA_PT : STD_ULOGIC_VECTOR(1 TO 175) := +(OTHERS=> 'U'); +component mmq_tlb_matchline + generic ( have_xbit : integer := 1; + num_pgsizes : integer := 5; + have_cmpmask : integer := 1; + cmpmask_width : integer := 5); +port( + vdd : inout power_logic; + gnd : inout power_logic; + addr_in : in std_ulogic_vector(0 to 51); + addr_enable : in std_ulogic_vector(0 to 8); + comp_pgsize : in std_ulogic_vector(0 to 3); + pgsize_enable : in std_ulogic; + entry_size : in std_ulogic_vector(0 to 3); + entry_cmpmask : in std_ulogic_vector(0 to cmpmask_width-1); + entry_xbit : in std_ulogic; + entry_xbitmask : in std_ulogic_vector(0 to cmpmask_width-1); + entry_epn : in std_ulogic_vector(0 to 51); + comp_class : in std_ulogic_vector(0 to 1); + entry_class : in std_ulogic_vector(0 to 1); + class_enable : in std_ulogic; + comp_extclass : in std_ulogic_vector(0 to 1); + entry_extclass : in std_ulogic_vector(0 to 1); + extclass_enable : in std_ulogic_vector(0 to 1); + comp_state : in std_ulogic_vector(0 to 1); + entry_gs : in std_ulogic; + entry_ts : in std_ulogic; + state_enable : in std_ulogic_vector(0 to 1); + entry_thdid : in std_ulogic_vector(0 to 3); + comp_thdid : in std_ulogic_vector(0 to 3); + thdid_enable : in std_ulogic; + entry_pid : in std_ulogic_vector(0 to 13); + comp_pid : in std_ulogic_vector(0 to 13); + pid_enable : in std_ulogic; + entry_lpid : in std_ulogic_vector(0 to 7); + comp_lpid : in std_ulogic_vector(0 to 7); + lpid_enable : in std_ulogic; + entry_ind : in std_ulogic; + comp_ind : in std_ulogic; + ind_enable : in std_ulogic; + entry_iprot : in std_ulogic; + comp_iprot : in std_ulogic; + iprot_enable : in std_ulogic; + entry_v : in std_ulogic; + comp_invalidate : in std_ulogic; + + match : out std_ulogic; + dbg_addr_match : out std_ulogic; + dbg_pgsize_match : out std_ulogic; + dbg_class_match : out std_ulogic; + dbg_extclass_match : out std_ulogic; + dbg_state_match : out std_ulogic; + dbg_thdid_match : out std_ulogic; + dbg_pid_match : out std_ulogic; + dbg_lpid_match : out std_ulogic; + dbg_ind_match : out std_ulogic; + dbg_iprot_match : out std_ulogic +); +end component; +constant MMU_Mode_Value : std_ulogic := '0'; +constant TlbSel_Tlb : std_ulogic_vector(0 to 1) := "00"; +constant TlbSel_IErat : std_ulogic_vector(0 to 1) := "10"; +constant TlbSel_DErat : std_ulogic_vector(0 to 1) := "11"; +constant ERAT_PgSize_1GB : std_ulogic_vector(0 to 2) := "110"; +constant ERAT_PgSize_16MB : std_ulogic_vector(0 to 2) := "111"; +constant ERAT_PgSize_1MB : std_ulogic_vector(0 to 2) := "101"; +constant ERAT_PgSize_64KB : std_ulogic_vector(0 to 2) := "011"; +constant ERAT_PgSize_4KB : std_ulogic_vector(0 to 2) := "001"; +constant TLB_PgSize_1GB : std_ulogic_vector(0 to 3) := "1010"; +constant TLB_PgSize_16MB : std_ulogic_vector(0 to 3) := "0111"; +constant TLB_PgSize_1MB : std_ulogic_vector(0 to 3) := "0101"; +constant TLB_PgSize_64KB : std_ulogic_vector(0 to 3) := "0011"; +constant TLB_PgSize_4KB : std_ulogic_vector(0 to 3) := "0001"; +-- reserved for indirect entries +constant ERAT_PgSize_256MB : std_ulogic_vector(0 to 2) := "100"; +constant TLB_PgSize_256MB : std_ulogic_vector(0 to 3) := "1001"; +constant tlb_way0_offset : natural := 0; +constant tlb_way1_offset : natural := tlb_way0_offset + tlb_way_width; +constant tlb_way0_cmpmask_offset : natural := tlb_way1_offset + tlb_way_width; +constant tlb_way1_cmpmask_offset : natural := tlb_way0_cmpmask_offset + 5; +constant tlb_way0_xbitmask_offset : natural := tlb_way1_cmpmask_offset + 5; +constant tlb_way1_xbitmask_offset : natural := tlb_way0_xbitmask_offset + 5; +constant tlb_tag3_cmpmask_offset : natural := tlb_way1_xbitmask_offset + 5; +constant tlb_tag3_clone1_offset : natural := tlb_tag3_cmpmask_offset + 5; +constant tlb_tag4_way_offset : natural := tlb_tag3_clone1_offset + tlb_tag_width; +constant tlb_tag4_way_rw_offset : natural := tlb_tag4_way_offset + tlb_way_width; +constant tlb_dataina_offset : natural := tlb_tag4_way_rw_offset + tlb_way_width; +constant tlb_erat_rel_offset : natural := tlb_dataina_offset + tlb_way_width; +constant mmucr1_offset : natural := tlb_erat_rel_offset + 132; +constant spare_a_offset : natural := mmucr1_offset + 9; +constant scan_right_0 : natural := spare_a_offset + 16 -1; +constant tlb_way2_offset : natural := 0; +constant tlb_way3_offset : natural := tlb_way2_offset + tlb_way_width; +constant tlb_way2_cmpmask_offset : natural := tlb_way3_offset + tlb_way_width; +constant tlb_way3_cmpmask_offset : natural := tlb_way2_cmpmask_offset + 5; +constant tlb_way2_xbitmask_offset : natural := tlb_way3_cmpmask_offset + 5; +constant tlb_way3_xbitmask_offset : natural := tlb_way2_xbitmask_offset + 5; +constant tlb_tag3_clone2_offset : natural := tlb_way3_xbitmask_offset + 5; +constant tlb_tag3_cmpmask_clone_offset : natural := tlb_tag3_clone2_offset + tlb_tag_width; +constant tlb_erat_rel_clone_offset : natural := tlb_tag3_cmpmask_clone_offset + 5; +constant tlb_tag4_way_clone_offset : natural := tlb_erat_rel_clone_offset + 132; +constant tlb_tag4_way_rw_clone_offset : natural := tlb_tag4_way_clone_offset + tlb_way_width; +constant tlb_datainb_offset : natural := tlb_tag4_way_rw_clone_offset + tlb_way_width; +constant mmucr1_clone_offset : natural := tlb_datainb_offset + tlb_way_width; +constant spare_b_offset : natural := mmucr1_clone_offset + 9; +constant scan_right_1 : natural := spare_b_offset + 16 -1; +constant tlb_tag3_offset : natural := 0; +constant tlb_addr3_offset : natural := tlb_tag3_offset + tlb_tag_width; +constant lru_tag3_dataout_offset : natural := tlb_addr3_offset + tlb_addr_width; +constant tlb_tag4_offset : natural := lru_tag3_dataout_offset + 16; +constant tlb_tag4_wayhit_offset : natural := tlb_tag4_offset + tlb_tag_width; +constant tlb_addr4_offset : natural := tlb_tag4_wayhit_offset + tlb_ways+1; +constant lru_tag4_dataout_offset : natural := tlb_addr4_offset + tlb_addr_width; +constant tlbwe_tag4_back_inv_offset : natural := lru_tag4_dataout_offset + 16; +constant tlbwe_tag4_back_inv_attr_offset : natural := tlbwe_tag4_back_inv_offset + thdid_width + 1; +constant tlb_erat_val_offset : natural := tlbwe_tag4_back_inv_attr_offset + 2; +constant tlb_erat_dup_offset : natural := tlb_erat_val_offset + 2*thdid_width+2; +constant lru_write_offset : natural := tlb_erat_dup_offset + 2*thdid_width+12; +constant lru_wr_addr_offset : natural := lru_write_offset + 16; +constant lru_datain_offset : natural := lru_wr_addr_offset + tlb_addr_width; +constant eratmiss_done_offset : natural := lru_datain_offset + 16; +constant tlb_miss_offset : natural := eratmiss_done_offset + thdid_width; +constant tlb_inelig_offset : natural := tlb_miss_offset + thdid_width; +constant lrat_miss_offset : natural := tlb_inelig_offset + thdid_width; +constant pt_fault_offset : natural := lrat_miss_offset + thdid_width; +constant hv_priv_offset : natural := pt_fault_offset + thdid_width; +constant tlb_tag5_except_offset : natural := hv_priv_offset + thdid_width; +constant tlb_dsi_offset : natural := tlb_tag5_except_offset + thdid_width; +constant tlb_isi_offset : natural := tlb_dsi_offset + thdid_width; +constant esr_pt_offset : natural := tlb_isi_offset + thdid_width; +constant esr_data_offset : natural := esr_pt_offset + thdid_width; +constant esr_epid_offset : natural := esr_data_offset + thdid_width; +constant esr_st_offset : natural := esr_epid_offset + thdid_width; +constant cr0_eq_offset : natural := esr_st_offset + thdid_width; +constant cr0_eq_valid_offset : natural := cr0_eq_offset + thdid_width; +constant tlb_multihit_err_offset : natural := cr0_eq_valid_offset + thdid_width; +constant tag4_parerr_offset : natural := tlb_multihit_err_offset + thdid_width; +constant tlb_par_err_offset : natural := tag4_parerr_offset + 5; +constant lru_par_err_offset : natural := tlb_par_err_offset + thdid_width; +constant cswitch_offset : natural := lru_par_err_offset + thdid_width; +constant spare_c_offset : natural := cswitch_offset + 8; +constant scan_right_2 : natural := spare_c_offset + 16 - 1; +--tlb_tag3_d <= ( 0:51 epn & +-- 52:65 pid & +-- 66:67 IS & +-- 68:69 Class & +-- 70:73 state (pr,gs,as,cm) & +-- 74:77 thdid & +-- 78:81 size & +-- 82:83 derat_miss/ierat_miss & +-- 84:85 tlbsx/tlbsrx & +-- 86:87 inval_snoop/tlbre & +-- 88:89 tlbwe/ptereload & +-- 90:97 lpid & +-- 98 indirect +-- 99 atsel & +-- 100:102 esel & +-- 103:105 hes/wq(0:1) & +-- 106:107 lrat/pt & +-- 108 record form +-- 109 endflag +constant tagpos_epn : natural := 0; +constant tagpos_pid : natural := 52; +constant tagpos_is : natural := 66; +constant tagpos_class : natural := 68; +constant tagpos_state : natural := 70; +constant tagpos_thdid : natural := 74; +constant tagpos_size : natural := 78; +constant tagpos_type : natural := 82; +constant tagpos_lpid : natural := 90; +constant tagpos_ind : natural := 98; +constant tagpos_atsel : natural := 99; +constant tagpos_esel : natural := 100; +constant tagpos_hes : natural := 103; +constant tagpos_wq : natural := 104; +constant tagpos_lrat : natural := 106; +constant tagpos_pt : natural := 107; +constant tagpos_recform : natural := 108; +constant tagpos_endflag : natural := 109; +-- derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload +constant tagpos_type_derat : natural := tagpos_type; +constant tagpos_type_ierat : natural := tagpos_type+1; +constant tagpos_type_tlbsx : natural := tagpos_type+2; +constant tagpos_type_tlbsrx : natural := tagpos_type+3; +constant tagpos_type_snoop : natural := tagpos_type+4; +constant tagpos_type_tlbre : natural := tagpos_type+5; +constant tagpos_type_tlbwe : natural := tagpos_type+6; +constant tagpos_type_ptereload : natural := tagpos_type+7; +-- state: 0:pr 1:gs 2:as 3:cm +constant tagpos_pr : natural := tagpos_state; +constant tagpos_gs : natural := tagpos_state+1; +constant tagpos_as : natural := tagpos_state+2; +constant tagpos_cm : natural := tagpos_state+3; +constant waypos_epn : natural := 0; +constant waypos_size : natural := 52; +constant waypos_thdid : natural := 56; +constant waypos_class : natural := 60; +constant waypos_extclass : natural := 62; +constant waypos_lpid : natural := 66; +constant waypos_xbit : natural := 84; +constant waypos_rpn : natural := 88; +constant waypos_rc : natural := 118; +constant waypos_wlc : natural := 120; +constant waypos_resvattr : natural := 122; +constant waypos_vf : natural := 123; +constant waypos_ind : natural := 124; +constant waypos_ubits : natural := 125; +constant waypos_wimge : natural := 129; +constant waypos_usxwr : natural := 134; +constant waypos_gs : natural := 140; +constant waypos_ts : natural := 141; +constant waypos_tid : natural := 144; +constant eratpos_epn : natural := 0; +constant eratpos_x : natural := 52; +constant eratpos_size : natural := 53; +constant eratpos_v : natural := 56; +constant eratpos_thdid : natural := 57; +constant eratpos_class : natural := 61; +constant eratpos_extclass : natural := 63; +constant eratpos_wren : natural := 65; +constant eratpos_rpnrsvd : natural := 66; +constant eratpos_rpn : natural := 70; +constant eratpos_r : natural := 100; +constant eratpos_c : natural := 101; +constant eratpos_relsoon : natural := 102; +constant eratpos_wlc : natural := 103; +constant eratpos_resvattr : natural := 105; +constant eratpos_vf : natural := 106; +constant eratpos_ubits : natural := 107; +constant eratpos_wimge : natural := 111; +constant eratpos_usxwr : natural := 116; +constant eratpos_gs : natural := 122; +constant eratpos_ts : natural := 123; +constant eratpos_tid : natural := 124; +constant ptepos_rpn : natural := 0; +constant ptepos_wimge : natural := 40; +constant ptepos_r : natural := 45; +constant ptepos_ubits : natural := 46; +constant ptepos_sw0 : natural := 50; +constant ptepos_c : natural := 51; +constant ptepos_size : natural := 52; +constant ptepos_usxwr : natural := 56; +constant ptepos_sw1 : natural := 62; +constant ptepos_valid : natural := 63; +-- mmucr1 bits +constant pos_tlb_pei : natural := 10; +constant pos_lru_pei : natural := 11; +constant pos_ictid : natural := 12; +constant pos_ittid : natural := 13; +constant pos_dctid : natural := 14; +constant pos_dttid : natural := 15; +constant pos_dccd : natural := 16; +constant pos_tlbwe_binv : natural := 17; +constant pos_tlbi_msb : natural := 18; +constant pos_tlbi_rej : natural := 19; +-- Latch signals +-- tag3 phase +signal tlb_way0_d, tlb_way0_q : std_ulogic_vector(0 to tlb_way_width-1); +signal tlb_way1_d, tlb_way1_q : std_ulogic_vector(0 to tlb_way_width-1); +signal tlb_way2_d, tlb_way2_q : std_ulogic_vector(0 to tlb_way_width-1); +signal tlb_way3_d, tlb_way3_q : std_ulogic_vector(0 to tlb_way_width-1); +signal tlb_tag3_d, tlb_tag3_q : std_ulogic_vector(0 to tlb_tag_width-1); +signal tlb_tag3_clone1_d, tlb_tag3_clone1_q : std_ulogic_vector(0 to tlb_tag_width-1); +signal tlb_tag3_clone2_d, tlb_tag3_clone2_q : std_ulogic_vector(0 to tlb_tag_width-1); +signal tlb_addr3_d, tlb_addr3_q : std_ulogic_vector(0 to tlb_addr_width-1); +signal lru_tag3_dataout_d, lru_tag3_dataout_q : std_ulogic_vector(0 to 15); +signal tlb_tag3_cmpmask_d, tlb_tag3_cmpmask_q : std_ulogic_vector(0 to 4); +signal tlb_tag3_cmpmask_clone_d, tlb_tag3_cmpmask_clone_q : std_ulogic_vector(0 to 4); +signal tlb_way0_cmpmask_d, tlb_way0_cmpmask_q : std_ulogic_vector(0 to 4); +signal tlb_way1_cmpmask_d, tlb_way1_cmpmask_q : std_ulogic_vector(0 to 4); +signal tlb_way2_cmpmask_d, tlb_way2_cmpmask_q : std_ulogic_vector(0 to 4); +signal tlb_way3_cmpmask_d, tlb_way3_cmpmask_q : std_ulogic_vector(0 to 4); +signal tlb_way0_xbitmask_d, tlb_way0_xbitmask_q : std_ulogic_vector(0 to 4); +signal tlb_way1_xbitmask_d, tlb_way1_xbitmask_q : std_ulogic_vector(0 to 4); +signal tlb_way2_xbitmask_d, tlb_way2_xbitmask_q : std_ulogic_vector(0 to 4); +signal tlb_way3_xbitmask_d, tlb_way3_xbitmask_q : std_ulogic_vector(0 to 4); +-- tag4 phase +signal tlb_tag4_d, tlb_tag4_q : std_ulogic_vector(0 to tlb_tag_width-1); +signal tlb_tag4_wayhit_d, tlb_tag4_wayhit_q : std_ulogic_vector(0 to tlb_ways); +signal tlb_addr4_d, tlb_addr4_q : std_ulogic_vector(0 to tlb_addr_width-1); +signal tlb_dataina_d, tlb_dataina_q : std_ulogic_vector(0 to tlb_way_width-1); +signal tlb_datainb_d, tlb_datainb_q : std_ulogic_vector(0 to tlb_way_width-1); +signal lru_tag4_dataout_d, lru_tag4_dataout_q : std_ulogic_vector(0 to lru_width-1); +signal tlb_tag4_way_d, tlb_tag4_way_q : std_ulogic_vector(0 to tlb_way_width-1); +signal tlb_tag4_way_clone_d, tlb_tag4_way_clone_q : std_ulogic_vector(0 to tlb_way_width-1); +signal tlb_tag4_way_rw_d, tlb_tag4_way_rw_q : std_ulogic_vector(0 to tlb_way_width-1); +signal tlb_tag4_way_rw_clone_d, tlb_tag4_way_rw_clone_q : std_ulogic_vector(0 to tlb_way_width-1); +signal tlb_tag4_way_rw_or : std_ulogic_vector(0 to tlb_way_width-1); +signal tlbwe_tag4_back_inv_d, tlbwe_tag4_back_inv_q : std_ulogic_vector(0 to thdid_width); +signal tlbwe_tag4_back_inv_attr_d, tlbwe_tag4_back_inv_attr_q : std_ulogic_vector(18 to 19); +-- tag5 phase +signal tlb_erat_val_d, tlb_erat_val_q : std_ulogic_vector(0 to 2*thdid_width+1); +signal tlb_erat_rel_d, tlb_erat_rel_q : std_ulogic_vector(0 to erat_rel_data_width-1); +signal tlb_erat_rel_clone_d, tlb_erat_rel_clone_q : std_ulogic_vector(0 to erat_rel_data_width-1); +signal tlb_erat_dup_d, tlb_erat_dup_q : std_ulogic_vector(0 to 2*thdid_width+11); +signal lru_write_d, lru_write_q : std_ulogic_vector(0 to 15); +signal lru_wr_addr_d, lru_wr_addr_q : std_ulogic_vector(0 to tlb_addr_width-1); +signal lru_datain_d, lru_datain_q : std_ulogic_vector(0 to 15); +signal eratmiss_done_d, eratmiss_done_q : std_ulogic_vector(0 to thdid_width-1); +signal tlb_miss_d, tlb_miss_q : std_ulogic_vector(0 to thdid_width-1); +signal tlb_inelig_d, tlb_inelig_q : std_ulogic_vector(0 to thdid_width-1); +signal lrat_miss_d, lrat_miss_q : std_ulogic_vector(0 to thdid_width-1); +signal pt_fault_d, pt_fault_q : std_ulogic_vector(0 to thdid_width-1); +signal hv_priv_d, hv_priv_q : std_ulogic_vector(0 to thdid_width-1); +signal tlb_tag5_except_d, tlb_tag5_except_q : std_ulogic_vector(0 to thdid_width-1); +signal tlb_dsi_d, tlb_dsi_q : std_ulogic_vector(0 to thdid_width-1); +signal tlb_isi_d, tlb_isi_q : std_ulogic_vector(0 to thdid_width-1); +signal esr_pt_d, esr_pt_q : std_ulogic_vector(0 to thdid_width-1); +signal esr_data_d, esr_data_q : std_ulogic_vector(0 to thdid_width-1); +signal esr_epid_d, esr_epid_q : std_ulogic_vector(0 to thdid_width-1); +signal esr_st_d, esr_st_q : std_ulogic_vector(0 to thdid_width-1); +signal tlb_multihit_err_d, tlb_multihit_err_q : std_ulogic_vector(0 to thdid_width-1); +signal tag4_parerr_d, tag4_parerr_q : std_ulogic_vector(0 to 4); +signal tlb_par_err_d, tlb_par_err_q : std_ulogic_vector(0 to thdid_width-1); +signal lru_par_err_d, lru_par_err_q : std_ulogic_vector(0 to thdid_width-1); +signal cr0_eq_d, cr0_eq_q : std_ulogic_vector(0 to thdid_width-1); +signal cr0_eq_valid_d, cr0_eq_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal mmucr1_q, mmucr1_clone_q : std_ulogic_vector(10 to 18); +signal epcr_dmiuh_q : std_ulogic_vector(0 to thdid_width-1); +signal msr_gs_q, msr_pr_q : std_ulogic_vector(0 to thdid_width-1); +signal spare_a_q, spare_b_q, spare_c_q : std_ulogic_vector(0 to 15); +signal spare_nsl_q, spare_nsl_clone_q : std_ulogic_vector(0 to 7); +signal cswitch_q : std_ulogic_vector(0 to 7); +-- Logic signals +-- tag3 phase +signal pgsize_enable,class_enable,thdid_enable,pid_enable,lpid_enable,ind_enable,iprot_enable : std_ulogic; +signal state_enable,extclass_enable : std_ulogic_vector(0 to 1); +signal addr_enable : std_ulogic_vector(0 to 8); +signal comp_iprot : std_ulogic; +signal comp_extclass : std_ulogic_vector(0 to 1); +signal comp_ind : std_ulogic; +signal pgsize_enable_clone,class_enable_clone,thdid_enable_clone,pid_enable_clone,lpid_enable_clone,ind_enable_clone,iprot_enable_clone : std_ulogic; +signal state_enable_clone,extclass_enable_clone : std_ulogic_vector(0 to 1); +signal addr_enable_clone : std_ulogic_vector(0 to 8); +signal comp_iprot_clone : std_ulogic; +signal comp_extclass_clone : std_ulogic_vector(0 to 1); +signal comp_ind_clone : std_ulogic; +-- synopsys translate_off +-- synopsys translate_on +signal tlbwe_tag3_back_inv_enab : std_ulogic; +signal tlb_tag4_way_or : std_ulogic_vector(0 to tlb_way_width-1); +signal tlb_tag4_way_act : std_ulogic; +signal tlb_tag4_way_clone_act : std_ulogic; +signal tlb_tag4_way_rw_act : std_ulogic; +signal tlb_tag4_way_rw_clone_act : std_ulogic; +-- tag4 phase +signal tlb_tag4_type_sig : std_ulogic_vector(0 to 7); +signal tlb_tag4_esel_sig : std_ulogic_vector(0 to 2); +signal tlb_tag4_hes_sig : std_ulogic; +signal tlb_tag4_wq_sig : std_ulogic_vector(0 to 1); +signal tlb_tag4_is_sig : std_ulogic_vector(0 to 3); +signal lru_update_data : std_ulogic_vector(0 to 2); +signal lru_update_data_enab, lru_update_clear_enab : std_ulogic; +signal tlb_tag4_hes1_mas1_v : std_ulogic_vector(0 to thdid_width-1); +signal tlb_tag4_hes0_mas1_v : std_ulogic_vector(0 to thdid_width-1); +signal tlb_tag4_hes1_mas1_iprot : std_ulogic_vector(0 to thdid_width-1); +signal tlb_tag4_hes0_mas1_iprot : std_ulogic_vector(0 to thdid_width-1); +signal tlb_tag4_ptereload_v : std_ulogic_vector(0 to thdid_width-1); +signal tlb_tag4_ptereload_iprot : std_ulogic_vector(0 to thdid_width-1); +signal tlb_tag4_ptereload_sig : std_ulogic; +signal tlb_tag4_erat_data_cap : std_ulogic; +signal tlb_wayhit : std_ulogic_vector(0 to tlb_ways-1); +signal multihit : std_ulogic; +signal erat_pgsize : std_ulogic_vector(0 to 2); +signal tlb_tag4_size_not_supp : std_ulogic; +signal tlb_tag4_hv_op : std_ulogic; +signal tlb_tag4_epcr_dgtmi : std_ulogic; +signal tlb_way0_addr_match : std_ulogic; +signal tlb_way0_pgsize_match : std_ulogic; +signal tlb_way0_class_match : std_ulogic; +signal tlb_way0_extclass_match : std_ulogic; +signal tlb_way0_state_match : std_ulogic; +signal tlb_way0_thdid_match : std_ulogic; +signal tlb_way0_pid_match : std_ulogic; +signal tlb_way0_lpid_match : std_ulogic; +signal tlb_way0_ind_match : std_ulogic; +signal tlb_way0_iprot_match : std_ulogic; +signal tlb_way1_addr_match : std_ulogic; +signal tlb_way1_pgsize_match : std_ulogic; +signal tlb_way1_class_match : std_ulogic; +signal tlb_way1_extclass_match : std_ulogic; +signal tlb_way1_state_match : std_ulogic; +signal tlb_way1_thdid_match : std_ulogic; +signal tlb_way1_pid_match : std_ulogic; +signal tlb_way1_lpid_match : std_ulogic; +signal tlb_way1_ind_match : std_ulogic; +signal tlb_way1_iprot_match : std_ulogic; +signal tlb_way2_addr_match : std_ulogic; +signal tlb_way2_pgsize_match : std_ulogic; +signal tlb_way2_class_match : std_ulogic; +signal tlb_way2_extclass_match : std_ulogic; +signal tlb_way2_state_match : std_ulogic; +signal tlb_way2_thdid_match : std_ulogic; +signal tlb_way2_pid_match : std_ulogic; +signal tlb_way2_lpid_match : std_ulogic; +signal tlb_way2_ind_match : std_ulogic; +signal tlb_way2_iprot_match : std_ulogic; +signal tlb_way3_addr_match : std_ulogic; +signal tlb_way3_pgsize_match : std_ulogic; +signal tlb_way3_class_match : std_ulogic; +signal tlb_way3_extclass_match : std_ulogic; +signal tlb_way3_state_match : std_ulogic; +signal tlb_way3_thdid_match : std_ulogic; +signal tlb_way3_pid_match : std_ulogic; +signal tlb_way3_lpid_match : std_ulogic; +signal tlb_way3_ind_match : std_ulogic; +signal tlb_way3_iprot_match : std_ulogic; +-- synopsys translate_off +-- synopsys translate_on +signal ierat_req0_tag4_pid_match : std_ulogic; +signal ierat_req0_tag4_as_match : std_ulogic; +signal ierat_req0_tag4_gs_match : std_ulogic; +signal ierat_req0_tag4_epn_match : std_ulogic; +signal ierat_req0_tag4_thdid_match : std_ulogic; +signal ierat_req1_tag4_pid_match : std_ulogic; +signal ierat_req1_tag4_as_match : std_ulogic; +signal ierat_req1_tag4_gs_match : std_ulogic; +signal ierat_req1_tag4_epn_match : std_ulogic; +signal ierat_req1_tag4_thdid_match : std_ulogic; +signal ierat_req2_tag4_pid_match : std_ulogic; +signal ierat_req2_tag4_as_match : std_ulogic; +signal ierat_req2_tag4_gs_match : std_ulogic; +signal ierat_req2_tag4_epn_match : std_ulogic; +signal ierat_req2_tag4_thdid_match : std_ulogic; +signal ierat_req3_tag4_pid_match : std_ulogic; +signal ierat_req3_tag4_as_match : std_ulogic; +signal ierat_req3_tag4_gs_match : std_ulogic; +signal ierat_req3_tag4_epn_match : std_ulogic; +signal ierat_req3_tag4_thdid_match : std_ulogic; +signal ierat_iu4_tag4_lpid_match : std_ulogic; +signal ierat_iu4_tag4_pid_match : std_ulogic; +signal ierat_iu4_tag4_as_match : std_ulogic; +signal ierat_iu4_tag4_gs_match : std_ulogic; +signal ierat_iu4_tag4_epn_match : std_ulogic; +signal ierat_iu4_tag4_thdid_match : std_ulogic; +signal derat_req0_tag4_lpid_match : std_ulogic; +signal derat_req0_tag4_pid_match : std_ulogic; +signal derat_req0_tag4_as_match : std_ulogic; +signal derat_req0_tag4_gs_match : std_ulogic; +signal derat_req0_tag4_epn_match : std_ulogic; +signal derat_req0_tag4_thdid_match : std_ulogic; +signal derat_req1_tag4_lpid_match : std_ulogic; +signal derat_req1_tag4_pid_match : std_ulogic; +signal derat_req1_tag4_as_match : std_ulogic; +signal derat_req1_tag4_gs_match : std_ulogic; +signal derat_req1_tag4_epn_match : std_ulogic; +signal derat_req1_tag4_thdid_match : std_ulogic; +signal derat_req2_tag4_lpid_match : std_ulogic; +signal derat_req2_tag4_pid_match : std_ulogic; +signal derat_req2_tag4_as_match : std_ulogic; +signal derat_req2_tag4_gs_match : std_ulogic; +signal derat_req2_tag4_epn_match : std_ulogic; +signal derat_req2_tag4_thdid_match : std_ulogic; +signal derat_req3_tag4_lpid_match : std_ulogic; +signal derat_req3_tag4_pid_match : std_ulogic; +signal derat_req3_tag4_as_match : std_ulogic; +signal derat_req3_tag4_gs_match : std_ulogic; +signal derat_req3_tag4_epn_match : std_ulogic; +signal derat_req3_tag4_thdid_match : std_ulogic; +signal derat_ex5_tag4_lpid_match : std_ulogic; +signal derat_ex5_tag4_pid_match : std_ulogic; +signal derat_ex5_tag4_as_match : std_ulogic; +signal derat_ex5_tag4_gs_match : std_ulogic; +signal derat_ex5_tag4_epn_match : std_ulogic; +signal derat_ex5_tag4_thdid_match : std_ulogic; +signal ierat_tag4_dup_thdid : std_ulogic_vector(0 to thdid_width-1); +signal derat_tag4_dup_thdid : std_ulogic_vector(0 to thdid_width-1); +signal tlb_way0_lo_calc_par : std_ulogic_vector(0 to 9); +signal tlb_way0_hi_calc_par : std_ulogic_vector(0 to 9); +signal tlb_way0_parerr : std_ulogic; +signal tlb_way1_lo_calc_par : std_ulogic_vector(0 to 9); +signal tlb_way1_hi_calc_par : std_ulogic_vector(0 to 9); +signal tlb_way1_parerr : std_ulogic; +signal tlb_way2_lo_calc_par : std_ulogic_vector(0 to 9); +signal tlb_way2_hi_calc_par : std_ulogic_vector(0 to 9); +signal tlb_way2_parerr : std_ulogic; +signal tlb_way3_lo_calc_par : std_ulogic_vector(0 to 9); +signal tlb_way3_hi_calc_par : std_ulogic_vector(0 to 9); +signal tlb_way3_parerr : std_ulogic; +signal lru_calc_par : std_ulogic_vector(0 to 1); +signal tlb_datain_lo_tlbwe_0_nopar : std_ulogic_vector(0 to tlb_word_width-10-1); +signal tlb_datain_lo_tlbwe_0_par : std_ulogic_vector(0 to 9); +signal tlb_datain_hi_hv_tlbwe_0_nopar : std_ulogic_vector(0 to tlb_word_width-10-1); +signal tlb_datain_hi_gs_tlbwe_0_nopar : std_ulogic_vector(0 to tlb_word_width-10-1); +signal tlb_datain_hi_hv_tlbwe_0_par : std_ulogic_vector(0 to 9); +signal tlb_datain_hi_gs_tlbwe_0_par : std_ulogic_vector(0 to 9); +signal tlb_datain_lo_tlbwe_1_nopar : std_ulogic_vector(0 to tlb_word_width-10-1); +signal tlb_datain_lo_tlbwe_1_par : std_ulogic_vector(0 to 9); +signal tlb_datain_hi_hv_tlbwe_1_nopar : std_ulogic_vector(0 to tlb_word_width-10-1); +signal tlb_datain_hi_gs_tlbwe_1_nopar : std_ulogic_vector(0 to tlb_word_width-10-1); +signal tlb_datain_hi_hv_tlbwe_1_par : std_ulogic_vector(0 to 9); +signal tlb_datain_hi_gs_tlbwe_1_par : std_ulogic_vector(0 to 9); +signal tlb_datain_lo_tlbwe_2_nopar : std_ulogic_vector(0 to tlb_word_width-10-1); +signal tlb_datain_lo_tlbwe_2_par : std_ulogic_vector(0 to 9); +signal tlb_datain_hi_hv_tlbwe_2_nopar : std_ulogic_vector(0 to tlb_word_width-10-1); +signal tlb_datain_hi_gs_tlbwe_2_nopar : std_ulogic_vector(0 to tlb_word_width-10-1); +signal tlb_datain_hi_hv_tlbwe_2_par : std_ulogic_vector(0 to 9); +signal tlb_datain_hi_gs_tlbwe_2_par : std_ulogic_vector(0 to 9); +signal tlb_datain_lo_tlbwe_3_nopar : std_ulogic_vector(0 to tlb_word_width-10-1); +signal tlb_datain_lo_tlbwe_3_par : std_ulogic_vector(0 to 9); +signal tlb_datain_hi_hv_tlbwe_3_nopar : std_ulogic_vector(0 to tlb_word_width-10-1); +signal tlb_datain_hi_gs_tlbwe_3_nopar : std_ulogic_vector(0 to tlb_word_width-10-1); +signal tlb_datain_hi_hv_tlbwe_3_par : std_ulogic_vector(0 to 9); +signal tlb_datain_hi_gs_tlbwe_3_par : std_ulogic_vector(0 to 9); +signal tlb_datain_lo_ptereload_nopar : std_ulogic_vector(0 to tlb_word_width-10-1); +signal tlb_datain_lo_ptereload_par : std_ulogic_vector(0 to 9); +signal tlb_datain_hi_hv_ptereload_nopar : std_ulogic_vector(0 to tlb_word_width-10-1); +signal tlb_datain_hi_gs_ptereload_nopar : std_ulogic_vector(0 to tlb_word_width-10-1); +signal tlb_datain_hi_hv_ptereload_par : std_ulogic_vector(0 to 9); +signal tlb_datain_hi_gs_ptereload_par : std_ulogic_vector(0 to 9); +signal ptereload_req_derived_usxwr : std_ulogic_vector(0 to 5); +signal lrat_tag3_lpn_sig : std_ulogic_vector(22 to 51); +signal lrat_tag3_rpn_sig : std_ulogic_vector(22 to 51); +signal lrat_tag4_lpn_sig : std_ulogic_vector(22 to 51); +signal lrat_tag4_rpn_sig : std_ulogic_vector(22 to 51); +-- synopsys translate_off +-- synopsys translate_on +-- possible eco signals +signal lru_datain_alt_d : std_ulogic_vector(4 to 9); +signal lru_update_data_alt : std_ulogic_vector(0 to 2); +signal tlb_tag4_parerr_enab : std_ulogic; +signal tlb_tag4_tlbre_parerr : std_ulogic; +signal lru_update_data_snoophit_eco : std_ulogic_vector(0 to 2); +signal lru_update_data_erathit_eco : std_ulogic_vector(0 to 2); +-- synopsys translate_off +-- synopsys translate_on +signal unused_dc : std_ulogic_vector(0 to 38); +-- synopsys translate_off +-- synopsys translate_on +-- dd2 eco signals +signal ECO107332_orred_tag4_thdid_flushed : std_ulogic; +signal ECO107332_tlb_par_err_d : std_ulogic_vector(0 to thdid_width-1); +signal ECO107332_lru_par_err_d : std_ulogic_vector(0 to thdid_width-1); +-- Pervasive +signal pc_sg_1 : std_ulogic; +signal pc_sg_0 : std_ulogic; +signal pc_fce_1 : std_ulogic; +signal pc_fce_0 : std_ulogic; +signal pc_func_sl_thold_1 : std_ulogic; +signal pc_func_sl_thold_0 : std_ulogic; +signal pc_func_sl_thold_0_b : std_ulogic; +signal pc_func_slp_sl_thold_1 : std_ulogic; +signal pc_func_slp_sl_thold_0 : std_ulogic; +signal pc_func_slp_sl_thold_0_b : std_ulogic; +signal pc_func_sl_force : std_ulogic; +signal pc_func_slp_sl_force : std_ulogic; +signal pc_func_slp_nsl_thold_1 : std_ulogic; +signal pc_func_slp_nsl_thold_0 : std_ulogic; +signal pc_func_slp_nsl_thold_0_b : std_ulogic_vector(0 to 1); +signal pc_func_slp_nsl_force : std_ulogic_vector(0 to 1); +signal siv_0, sov_0 : std_ulogic_vector(0 to scan_right_0); +signal siv_1, sov_1 : std_ulogic_vector(0 to scan_right_1); +signal siv_2, sov_2 : std_ulogic_vector(0 to scan_right_2); +signal tidn : std_ulogic; +signal tiup : std_ulogic; + BEGIN --@@ START OF EXECUTABLE CODE FOR MMQ_TLB_CMP + +tidn <= '0'; +tiup <= '1'; +-- tag2 phase signals, tlbwe/re ex4, tlbsx/srx ex5 +tlb_addr3_d <= tlb_addr2; +-- latch tlb array outputs +tlb_way0_d <= tlb_dataout(0 to tlb_way_width-1); +tlb_way1_d <= tlb_dataout(tlb_way_width to 2*tlb_way_width-1); +tlb_way2_d <= tlb_dataout(2*tlb_way_width to 3*tlb_way_width-1); +tlb_way3_d <= tlb_dataout(3*tlb_way_width to 4*tlb_way_width-1); +-- tlb_ctl may flush the thdid bits +tlb_tag3_d(0 TO tagpos_thdid-1) <= tlb_tag2(0 to tagpos_thdid-1); +tlb_tag3_d(tagpos_thdid TO tagpos_thdid+thdid_width-1) <= + (others => '0') when ((tlb_tag4_wayhit_q(tlb_ways)='1' or tlb_tag4_q(tagpos_endflag)='1' or or_reduce(tag4_parerr_q(0 to 4))='1') and + tlb_tag4_q(tagpos_type_ptereload)='0' and + (tlb_tag4_q(tagpos_type_ierat)='1' or tlb_tag4_q(tagpos_type_derat)='1')) + else (others => '0') when ((tlb_tag4_wayhit_q(tlb_ways)='1' or tlb_tag4_q(tagpos_endflag)='1' or or_reduce(tag4_parerr_q(0 to 4))='1') and + (tlb_tag4_q(tagpos_type_tlbsx)='1' or tlb_tag4_q(tagpos_type_tlbsrx)='1')) + else (others => '0') when (tlb_tag4_q(tagpos_endflag)='1' and tlb_tag4_q(tagpos_type_snoop)='1') + else (others => '0') when ((tlb_tag4_q(tagpos_type_tlbre)='1' or tlb_tag4_q(tagpos_type_tlbwe)='1' or tlb_tag4_q(tagpos_type_ptereload)='1' ) and + tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000") + else tlb_tag2(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag2_flush); +tlb_tag3_d(tagpos_thdid+thdid_width TO tlb_tag_width-1) <= tlb_tag2(tagpos_thdid+thdid_width to tlb_tag_width-1); +-- clones for timing arrays 0/1 +tlb_tag3_clone1_d(0 TO tagpos_thdid-1) <= tlb_tag2(0 to tagpos_thdid-1); +tlb_tag3_clone1_d(tagpos_thdid TO tagpos_thdid+thdid_width-1) <= + (others => '0') when ((tlb_tag4_wayhit_q(tlb_ways)='1' or tlb_tag4_q(tagpos_endflag)='1' or or_reduce(tag4_parerr_q(0 to 4))='1') and + tlb_tag4_q(tagpos_type_ptereload)='0' and + (tlb_tag4_q(tagpos_type_ierat)='1' or tlb_tag4_q(tagpos_type_derat)='1')) + else (others => '0') when ((tlb_tag4_wayhit_q(tlb_ways)='1' or tlb_tag4_q(tagpos_endflag)='1' or or_reduce(tag4_parerr_q(0 to 4))='1') and + (tlb_tag4_q(tagpos_type_tlbsx)='1' or tlb_tag4_q(tagpos_type_tlbsrx)='1')) + else (others => '0') when (tlb_tag4_q(tagpos_endflag)='1' and tlb_tag4_q(tagpos_type_snoop)='1') + else (others => '0') when ((tlb_tag4_q(tagpos_type_tlbre)='1' or tlb_tag4_q(tagpos_type_tlbwe)='1' or tlb_tag4_q(tagpos_type_ptereload)='1' ) and + tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000") + else tlb_tag2(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag2_flush); +tlb_tag3_clone1_d(tagpos_thdid+thdid_width TO tlb_tag_width-1) <= tlb_tag2(tagpos_thdid+thdid_width to tlb_tag_width-1); +-- clones for timing arrays 2/3 +tlb_tag3_clone2_d(0 TO tagpos_thdid-1) <= tlb_tag2(0 to tagpos_thdid-1); +tlb_tag3_clone2_d(tagpos_thdid TO tagpos_thdid+thdid_width-1) <= + (others => '0') when ((tlb_tag4_wayhit_q(tlb_ways)='1' or tlb_tag4_q(tagpos_endflag)='1' or or_reduce(tag4_parerr_q(0 to 4))='1') and + tlb_tag4_q(tagpos_type_ptereload)='0' and + (tlb_tag4_q(tagpos_type_ierat)='1' or tlb_tag4_q(tagpos_type_derat)='1')) + else (others => '0') when ((tlb_tag4_wayhit_q(tlb_ways)='1' or tlb_tag4_q(tagpos_endflag)='1' or or_reduce(tag4_parerr_q(0 to 4))='1') and + (tlb_tag4_q(tagpos_type_tlbsx)='1' or tlb_tag4_q(tagpos_type_tlbsrx)='1')) + else (others => '0') when (tlb_tag4_q(tagpos_endflag)='1' and tlb_tag4_q(tagpos_type_snoop)='1') + else (others => '0') when ((tlb_tag4_q(tagpos_type_tlbre)='1' or tlb_tag4_q(tagpos_type_tlbwe)='1' or tlb_tag4_q(tagpos_type_ptereload)='1' ) and + tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000") + else tlb_tag2(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag2_flush); +tlb_tag3_clone2_d(tagpos_thdid+thdid_width TO tlb_tag_width-1) <= tlb_tag2(tagpos_thdid+thdid_width to tlb_tag_width-1); +-- size tlb_tag3_cmpmask: 01234 +-- 1GB 11111 +-- 256MB 01111 +-- 16MB 00111 +-- 1MB 00011 +-- 64KB 00001 +-- 4KB 00000 +tlb_tag3_cmpmask_d(0) <= Eq(tlb_tag2(tagpos_size to tagpos_size+3), TLB_PgSize_1GB); +tlb_tag3_cmpmask_d(1) <= Eq(tlb_tag2(tagpos_size to tagpos_size+3), TLB_PgSize_1GB) or + Eq(tlb_tag2(tagpos_size to tagpos_size+3), TLB_PgSize_256MB); +tlb_tag3_cmpmask_d(2) <= Eq(tlb_tag2(tagpos_size to tagpos_size+3), TLB_PgSize_1GB) or + Eq(tlb_tag2(tagpos_size to tagpos_size+3), TLB_PgSize_256MB) or + Eq(tlb_tag2(tagpos_size to tagpos_size+3), TLB_PgSize_16MB); +tlb_tag3_cmpmask_d(3) <= Eq(tlb_tag2(tagpos_size to tagpos_size+3), TLB_PgSize_1GB) or + Eq(tlb_tag2(tagpos_size to tagpos_size+3), TLB_PgSize_256MB) or + Eq(tlb_tag2(tagpos_size to tagpos_size+3), TLB_PgSize_16MB) or + Eq(tlb_tag2(tagpos_size to tagpos_size+3), TLB_PgSize_1MB); +tlb_tag3_cmpmask_d(4) <= Eq(tlb_tag2(tagpos_size to tagpos_size+3), TLB_PgSize_1GB) or + Eq(tlb_tag2(tagpos_size to tagpos_size+3), TLB_PgSize_256MB) or + Eq(tlb_tag2(tagpos_size to tagpos_size+3), TLB_PgSize_16MB) or + Eq(tlb_tag2(tagpos_size to tagpos_size+3), TLB_PgSize_1MB) or + Eq(tlb_tag2(tagpos_size to tagpos_size+3), TLB_PgSize_64KB); +tlb_tag3_cmpmask_clone_d(0) <= Eq(tlb_tag2(tagpos_size to tagpos_size+3), TLB_PgSize_1GB); +tlb_tag3_cmpmask_clone_d(1) <= Eq(tlb_tag2(tagpos_size to tagpos_size+3), TLB_PgSize_1GB) or + Eq(tlb_tag2(tagpos_size to tagpos_size+3), TLB_PgSize_256MB); +tlb_tag3_cmpmask_clone_d(2) <= Eq(tlb_tag2(tagpos_size to tagpos_size+3), TLB_PgSize_1GB) or + Eq(tlb_tag2(tagpos_size to tagpos_size+3), TLB_PgSize_256MB) or + Eq(tlb_tag2(tagpos_size to tagpos_size+3), TLB_PgSize_16MB); +tlb_tag3_cmpmask_clone_d(3) <= Eq(tlb_tag2(tagpos_size to tagpos_size+3), TLB_PgSize_1GB) or + Eq(tlb_tag2(tagpos_size to tagpos_size+3), TLB_PgSize_256MB) or + Eq(tlb_tag2(tagpos_size to tagpos_size+3), TLB_PgSize_16MB) or + Eq(tlb_tag2(tagpos_size to tagpos_size+3), TLB_PgSize_1MB); +tlb_tag3_cmpmask_clone_d(4) <= Eq(tlb_tag2(tagpos_size to tagpos_size+3), TLB_PgSize_1GB) or + Eq(tlb_tag2(tagpos_size to tagpos_size+3), TLB_PgSize_256MB) or + Eq(tlb_tag2(tagpos_size to tagpos_size+3), TLB_PgSize_16MB) or + Eq(tlb_tag2(tagpos_size to tagpos_size+3), TLB_PgSize_1MB) or + Eq(tlb_tag2(tagpos_size to tagpos_size+3), TLB_PgSize_64KB); +-- size tlb_way_cmpmask: 01234 +-- 1GB 11111 +-- 256MB 01111 +-- 16MB 00111 +-- 1MB 00011 +-- 64KB 00001 +-- 4KB 00000 +-- size tlb_way_xbitmask: 01234 +-- 1GB 10000 +-- 256MB 01000 +-- 16MB 00100 +-- 1MB 00010 +-- 64KB 00001 +-- 4KB 00000 +tlb_way0_cmpmask_d(0) <= Eq(tlb_dataout(0*tlb_way_width+waypos_size to 0*tlb_way_width+waypos_size+3), TLB_PgSize_1GB); +tlb_way0_cmpmask_d(1) <= Eq(tlb_dataout(0*tlb_way_width+waypos_size to 0*tlb_way_width+waypos_size+3), TLB_PgSize_1GB) or + Eq(tlb_dataout(0*tlb_way_width+waypos_size to 0*tlb_way_width+waypos_size+3), TLB_PgSize_256MB); +tlb_way0_cmpmask_d(2) <= Eq(tlb_dataout(0*tlb_way_width+waypos_size to 0*tlb_way_width+waypos_size+3), TLB_PgSize_1GB) or + Eq(tlb_dataout(0*tlb_way_width+waypos_size to 0*tlb_way_width+waypos_size+3), TLB_PgSize_256MB) or + Eq(tlb_dataout(0*tlb_way_width+waypos_size to 0*tlb_way_width+waypos_size+3), TLB_PgSize_16MB); +tlb_way0_cmpmask_d(3) <= Eq(tlb_dataout(0*tlb_way_width+waypos_size to 0*tlb_way_width+waypos_size+3), TLB_PgSize_1GB) or + Eq(tlb_dataout(0*tlb_way_width+waypos_size to 0*tlb_way_width+waypos_size+3), TLB_PgSize_256MB) or + Eq(tlb_dataout(0*tlb_way_width+waypos_size to 0*tlb_way_width+waypos_size+3), TLB_PgSize_16MB) or + Eq(tlb_dataout(0*tlb_way_width+waypos_size to 0*tlb_way_width+waypos_size+3), TLB_PgSize_1MB); +tlb_way0_cmpmask_d(4) <= Eq(tlb_dataout(0*tlb_way_width+waypos_size to 0*tlb_way_width+waypos_size+3), TLB_PgSize_1GB) or + Eq(tlb_dataout(0*tlb_way_width+waypos_size to 0*tlb_way_width+waypos_size+3), TLB_PgSize_256MB) or + Eq(tlb_dataout(0*tlb_way_width+waypos_size to 0*tlb_way_width+waypos_size+3), TLB_PgSize_16MB) or + Eq(tlb_dataout(0*tlb_way_width+waypos_size to 0*tlb_way_width+waypos_size+3), TLB_PgSize_1MB) or + Eq(tlb_dataout(0*tlb_way_width+waypos_size to 0*tlb_way_width+waypos_size+3), TLB_PgSize_64KB); +tlb_way0_xbitmask_d(0) <= Eq(tlb_dataout(0*tlb_way_width+waypos_size to 0*tlb_way_width+waypos_size+3), TLB_PgSize_1GB); +tlb_way0_xbitmask_d(1) <= Eq(tlb_dataout(0*tlb_way_width+waypos_size to 0*tlb_way_width+waypos_size+3), TLB_PgSize_256MB); +tlb_way0_xbitmask_d(2) <= Eq(tlb_dataout(0*tlb_way_width+waypos_size to 0*tlb_way_width+waypos_size+3), TLB_PgSize_16MB); +tlb_way0_xbitmask_d(3) <= Eq(tlb_dataout(0*tlb_way_width+waypos_size to 0*tlb_way_width+waypos_size+3), TLB_PgSize_1MB); +tlb_way0_xbitmask_d(4) <= Eq(tlb_dataout(0*tlb_way_width+waypos_size to 0*tlb_way_width+waypos_size+3), TLB_PgSize_64KB); +tlb_way1_cmpmask_d(0) <= Eq(tlb_dataout(1*tlb_way_width+waypos_size to 1*tlb_way_width+waypos_size+3), TLB_PgSize_1GB); +tlb_way1_cmpmask_d(1) <= Eq(tlb_dataout(1*tlb_way_width+waypos_size to 1*tlb_way_width+waypos_size+3), TLB_PgSize_1GB) or + Eq(tlb_dataout(1*tlb_way_width+waypos_size to 1*tlb_way_width+waypos_size+3), TLB_PgSize_256MB); +tlb_way1_cmpmask_d(2) <= Eq(tlb_dataout(1*tlb_way_width+waypos_size to 1*tlb_way_width+waypos_size+3), TLB_PgSize_1GB) or + Eq(tlb_dataout(1*tlb_way_width+waypos_size to 1*tlb_way_width+waypos_size+3), TLB_PgSize_256MB) or + Eq(tlb_dataout(1*tlb_way_width+waypos_size to 1*tlb_way_width+waypos_size+3), TLB_PgSize_16MB); +tlb_way1_cmpmask_d(3) <= Eq(tlb_dataout(1*tlb_way_width+waypos_size to 1*tlb_way_width+waypos_size+3), TLB_PgSize_1GB) or + Eq(tlb_dataout(1*tlb_way_width+waypos_size to 1*tlb_way_width+waypos_size+3), TLB_PgSize_256MB) or + Eq(tlb_dataout(1*tlb_way_width+waypos_size to 1*tlb_way_width+waypos_size+3), TLB_PgSize_16MB) or + Eq(tlb_dataout(1*tlb_way_width+waypos_size to 1*tlb_way_width+waypos_size+3), TLB_PgSize_1MB); +tlb_way1_cmpmask_d(4) <= Eq(tlb_dataout(1*tlb_way_width+waypos_size to 1*tlb_way_width+waypos_size+3), TLB_PgSize_1GB) or + Eq(tlb_dataout(1*tlb_way_width+waypos_size to 1*tlb_way_width+waypos_size+3), TLB_PgSize_256MB) or + Eq(tlb_dataout(1*tlb_way_width+waypos_size to 1*tlb_way_width+waypos_size+3), TLB_PgSize_16MB) or + Eq(tlb_dataout(1*tlb_way_width+waypos_size to 1*tlb_way_width+waypos_size+3), TLB_PgSize_1MB) or + Eq(tlb_dataout(1*tlb_way_width+waypos_size to 1*tlb_way_width+waypos_size+3), TLB_PgSize_64KB); +tlb_way1_xbitmask_d(0) <= Eq(tlb_dataout(1*tlb_way_width+waypos_size to 1*tlb_way_width+waypos_size+3), TLB_PgSize_1GB); +tlb_way1_xbitmask_d(1) <= Eq(tlb_dataout(1*tlb_way_width+waypos_size to 1*tlb_way_width+waypos_size+3), TLB_PgSize_256MB); +tlb_way1_xbitmask_d(2) <= Eq(tlb_dataout(1*tlb_way_width+waypos_size to 1*tlb_way_width+waypos_size+3), TLB_PgSize_16MB); +tlb_way1_xbitmask_d(3) <= Eq(tlb_dataout(1*tlb_way_width+waypos_size to 1*tlb_way_width+waypos_size+3), TLB_PgSize_1MB); +tlb_way1_xbitmask_d(4) <= Eq(tlb_dataout(1*tlb_way_width+waypos_size to 1*tlb_way_width+waypos_size+3), TLB_PgSize_64KB); +tlb_way2_cmpmask_d(0) <= Eq(tlb_dataout(2*tlb_way_width+waypos_size to 2*tlb_way_width+waypos_size+3), TLB_PgSize_1GB); +tlb_way2_cmpmask_d(1) <= Eq(tlb_dataout(2*tlb_way_width+waypos_size to 2*tlb_way_width+waypos_size+3), TLB_PgSize_1GB) or + Eq(tlb_dataout(2*tlb_way_width+waypos_size to 2*tlb_way_width+waypos_size+3), TLB_PgSize_256MB); +tlb_way2_cmpmask_d(2) <= Eq(tlb_dataout(2*tlb_way_width+waypos_size to 2*tlb_way_width+waypos_size+3), TLB_PgSize_1GB) or + Eq(tlb_dataout(2*tlb_way_width+waypos_size to 2*tlb_way_width+waypos_size+3), TLB_PgSize_256MB) or + Eq(tlb_dataout(2*tlb_way_width+waypos_size to 2*tlb_way_width+waypos_size+3), TLB_PgSize_16MB); +tlb_way2_cmpmask_d(3) <= Eq(tlb_dataout(2*tlb_way_width+waypos_size to 2*tlb_way_width+waypos_size+3), TLB_PgSize_1GB) or + Eq(tlb_dataout(2*tlb_way_width+waypos_size to 2*tlb_way_width+waypos_size+3), TLB_PgSize_256MB) or + Eq(tlb_dataout(2*tlb_way_width+waypos_size to 2*tlb_way_width+waypos_size+3), TLB_PgSize_16MB) or + Eq(tlb_dataout(2*tlb_way_width+waypos_size to 2*tlb_way_width+waypos_size+3), TLB_PgSize_1MB); +tlb_way2_cmpmask_d(4) <= Eq(tlb_dataout(2*tlb_way_width+waypos_size to 2*tlb_way_width+waypos_size+3), TLB_PgSize_1GB) or + Eq(tlb_dataout(2*tlb_way_width+waypos_size to 2*tlb_way_width+waypos_size+3), TLB_PgSize_256MB) or + Eq(tlb_dataout(2*tlb_way_width+waypos_size to 2*tlb_way_width+waypos_size+3), TLB_PgSize_16MB) or + Eq(tlb_dataout(2*tlb_way_width+waypos_size to 2*tlb_way_width+waypos_size+3), TLB_PgSize_1MB) or + Eq(tlb_dataout(2*tlb_way_width+waypos_size to 2*tlb_way_width+waypos_size+3), TLB_PgSize_64KB); +tlb_way2_xbitmask_d(0) <= Eq(tlb_dataout(2*tlb_way_width+waypos_size to 2*tlb_way_width+waypos_size+3), TLB_PgSize_1GB); +tlb_way2_xbitmask_d(1) <= Eq(tlb_dataout(2*tlb_way_width+waypos_size to 2*tlb_way_width+waypos_size+3), TLB_PgSize_256MB); +tlb_way2_xbitmask_d(2) <= Eq(tlb_dataout(2*tlb_way_width+waypos_size to 2*tlb_way_width+waypos_size+3), TLB_PgSize_16MB); +tlb_way2_xbitmask_d(3) <= Eq(tlb_dataout(2*tlb_way_width+waypos_size to 2*tlb_way_width+waypos_size+3), TLB_PgSize_1MB); +tlb_way2_xbitmask_d(4) <= Eq(tlb_dataout(2*tlb_way_width+waypos_size to 2*tlb_way_width+waypos_size+3), TLB_PgSize_64KB); +tlb_way3_cmpmask_d(0) <= Eq(tlb_dataout(3*tlb_way_width+waypos_size to 3*tlb_way_width+waypos_size+3), TLB_PgSize_1GB); +tlb_way3_cmpmask_d(1) <= Eq(tlb_dataout(3*tlb_way_width+waypos_size to 3*tlb_way_width+waypos_size+3), TLB_PgSize_1GB) or + Eq(tlb_dataout(3*tlb_way_width+waypos_size to 3*tlb_way_width+waypos_size+3), TLB_PgSize_256MB); +tlb_way3_cmpmask_d(2) <= Eq(tlb_dataout(3*tlb_way_width+waypos_size to 3*tlb_way_width+waypos_size+3), TLB_PgSize_1GB) or + Eq(tlb_dataout(3*tlb_way_width+waypos_size to 3*tlb_way_width+waypos_size+3), TLB_PgSize_256MB) or + Eq(tlb_dataout(3*tlb_way_width+waypos_size to 3*tlb_way_width+waypos_size+3), TLB_PgSize_16MB); +tlb_way3_cmpmask_d(3) <= Eq(tlb_dataout(3*tlb_way_width+waypos_size to 3*tlb_way_width+waypos_size+3), TLB_PgSize_1GB) or + Eq(tlb_dataout(3*tlb_way_width+waypos_size to 3*tlb_way_width+waypos_size+3), TLB_PgSize_256MB) or + Eq(tlb_dataout(3*tlb_way_width+waypos_size to 3*tlb_way_width+waypos_size+3), TLB_PgSize_16MB) or + Eq(tlb_dataout(3*tlb_way_width+waypos_size to 3*tlb_way_width+waypos_size+3), TLB_PgSize_1MB); +tlb_way3_cmpmask_d(4) <= Eq(tlb_dataout(3*tlb_way_width+waypos_size to 3*tlb_way_width+waypos_size+3), TLB_PgSize_1GB) or + Eq(tlb_dataout(3*tlb_way_width+waypos_size to 3*tlb_way_width+waypos_size+3), TLB_PgSize_256MB) or + Eq(tlb_dataout(3*tlb_way_width+waypos_size to 3*tlb_way_width+waypos_size+3), TLB_PgSize_16MB) or + Eq(tlb_dataout(3*tlb_way_width+waypos_size to 3*tlb_way_width+waypos_size+3), TLB_PgSize_1MB) or + Eq(tlb_dataout(3*tlb_way_width+waypos_size to 3*tlb_way_width+waypos_size+3), TLB_PgSize_64KB); +tlb_way3_xbitmask_d(0) <= Eq(tlb_dataout(3*tlb_way_width+waypos_size to 3*tlb_way_width+waypos_size+3), TLB_PgSize_1GB); +tlb_way3_xbitmask_d(1) <= Eq(tlb_dataout(3*tlb_way_width+waypos_size to 3*tlb_way_width+waypos_size+3), TLB_PgSize_256MB); +tlb_way3_xbitmask_d(2) <= Eq(tlb_dataout(3*tlb_way_width+waypos_size to 3*tlb_way_width+waypos_size+3), TLB_PgSize_16MB); +tlb_way3_xbitmask_d(3) <= Eq(tlb_dataout(3*tlb_way_width+waypos_size to 3*tlb_way_width+waypos_size+3), TLB_PgSize_1MB); +tlb_way3_xbitmask_d(4) <= Eq(tlb_dataout(3*tlb_way_width+waypos_size to 3*tlb_way_width+waypos_size+3), TLB_PgSize_64KB); +-- TLB Parity Checking +tlb_way0_lo_calc_par(0) <= xor_reduce(tlb_way0_q(0 to 7)); +tlb_way0_lo_calc_par(1) <= xor_reduce(tlb_way0_q(8 to 15)); +tlb_way0_lo_calc_par(2) <= xor_reduce(tlb_way0_q(16 to 23)); +tlb_way0_lo_calc_par(3) <= xor_reduce(tlb_way0_q(24 to 31)); +tlb_way0_lo_calc_par(4) <= xor_reduce(tlb_way0_q(32 to 39)); +tlb_way0_lo_calc_par(5) <= xor_reduce(tlb_way0_q(40 to 47)); +tlb_way0_lo_calc_par(6) <= xor_reduce(tlb_way0_q(48 to 51)); +tlb_way0_lo_calc_par(7) <= xor_reduce(tlb_way0_q(52 to 59)); +tlb_way0_lo_calc_par(8) <= xor_reduce(tlb_way0_q(60 to 65)); +tlb_way0_lo_calc_par(9) <= xor_reduce(tlb_way0_q(66 to 73)); +tlb_way1_lo_calc_par(0) <= xor_reduce(tlb_way1_q(0 to 7)); +tlb_way1_lo_calc_par(1) <= xor_reduce(tlb_way1_q(8 to 15)); +tlb_way1_lo_calc_par(2) <= xor_reduce(tlb_way1_q(16 to 23)); +tlb_way1_lo_calc_par(3) <= xor_reduce(tlb_way1_q(24 to 31)); +tlb_way1_lo_calc_par(4) <= xor_reduce(tlb_way1_q(32 to 39)); +tlb_way1_lo_calc_par(5) <= xor_reduce(tlb_way1_q(40 to 47)); +tlb_way1_lo_calc_par(6) <= xor_reduce(tlb_way1_q(48 to 51)); +tlb_way1_lo_calc_par(7) <= xor_reduce(tlb_way1_q(52 to 59)); +tlb_way1_lo_calc_par(8) <= xor_reduce(tlb_way1_q(60 to 65)); +tlb_way1_lo_calc_par(9) <= xor_reduce(tlb_way1_q(66 to 73)); +tlb_way2_lo_calc_par(0) <= xor_reduce(tlb_way2_q(0 to 7)); +tlb_way2_lo_calc_par(1) <= xor_reduce(tlb_way2_q(8 to 15)); +tlb_way2_lo_calc_par(2) <= xor_reduce(tlb_way2_q(16 to 23)); +tlb_way2_lo_calc_par(3) <= xor_reduce(tlb_way2_q(24 to 31)); +tlb_way2_lo_calc_par(4) <= xor_reduce(tlb_way2_q(32 to 39)); +tlb_way2_lo_calc_par(5) <= xor_reduce(tlb_way2_q(40 to 47)); +tlb_way2_lo_calc_par(6) <= xor_reduce(tlb_way2_q(48 to 51)); +tlb_way2_lo_calc_par(7) <= xor_reduce(tlb_way2_q(52 to 59)); +tlb_way2_lo_calc_par(8) <= xor_reduce(tlb_way2_q(60 to 65)); +tlb_way2_lo_calc_par(9) <= xor_reduce(tlb_way2_q(66 to 73)); +tlb_way3_lo_calc_par(0) <= xor_reduce(tlb_way3_q(0 to 7)); +tlb_way3_lo_calc_par(1) <= xor_reduce(tlb_way3_q(8 to 15)); +tlb_way3_lo_calc_par(2) <= xor_reduce(tlb_way3_q(16 to 23)); +tlb_way3_lo_calc_par(3) <= xor_reduce(tlb_way3_q(24 to 31)); +tlb_way3_lo_calc_par(4) <= xor_reduce(tlb_way3_q(32 to 39)); +tlb_way3_lo_calc_par(5) <= xor_reduce(tlb_way3_q(40 to 47)); +tlb_way3_lo_calc_par(6) <= xor_reduce(tlb_way3_q(48 to 51)); +tlb_way3_lo_calc_par(7) <= xor_reduce(tlb_way3_q(52 to 59)); +tlb_way3_lo_calc_par(8) <= xor_reduce(tlb_way3_q(60 to 65)); +tlb_way3_lo_calc_par(9) <= xor_reduce(tlb_way3_q(66 to 73)); +tlb_way0_hi_calc_par(0) <= xor_reduce(tlb_way0_q(tlb_word_width+0 to tlb_word_width+7)); +tlb_way0_hi_calc_par(1) <= xor_reduce(tlb_way0_q(tlb_word_width+8 to tlb_word_width+15)); +tlb_way0_hi_calc_par(2) <= xor_reduce(tlb_way0_q(tlb_word_width+16 to tlb_word_width+23)); +tlb_way0_hi_calc_par(3) <= xor_reduce(tlb_way0_q(tlb_word_width+24 to tlb_word_width+31)); +tlb_way0_hi_calc_par(4) <= xor_reduce(tlb_way0_q(tlb_word_width+32 to tlb_word_width+39)); +tlb_way0_hi_calc_par(5) <= xor_reduce(tlb_way0_q(tlb_word_width+40 to tlb_word_width+44)); +tlb_way0_hi_calc_par(6) <= xor_reduce(tlb_way0_q(tlb_word_width+45 to tlb_word_width+49)); +tlb_way0_hi_calc_par(7) <= xor_reduce(tlb_way0_q(tlb_word_width+50 to tlb_word_width+57)); +tlb_way0_hi_calc_par(8) <= xor_reduce(tlb_way0_q(tlb_word_width+58 to tlb_word_width+65)); +tlb_way0_hi_calc_par(9) <= xor_reduce(tlb_way0_q(tlb_word_width+66 to tlb_word_width+73)); +tlb_way1_hi_calc_par(0) <= xor_reduce(tlb_way1_q(tlb_word_width+0 to tlb_word_width+7)); +tlb_way1_hi_calc_par(1) <= xor_reduce(tlb_way1_q(tlb_word_width+8 to tlb_word_width+15)); +tlb_way1_hi_calc_par(2) <= xor_reduce(tlb_way1_q(tlb_word_width+16 to tlb_word_width+23)); +tlb_way1_hi_calc_par(3) <= xor_reduce(tlb_way1_q(tlb_word_width+24 to tlb_word_width+31)); +tlb_way1_hi_calc_par(4) <= xor_reduce(tlb_way1_q(tlb_word_width+32 to tlb_word_width+39)); +tlb_way1_hi_calc_par(5) <= xor_reduce(tlb_way1_q(tlb_word_width+40 to tlb_word_width+44)); +tlb_way1_hi_calc_par(6) <= xor_reduce(tlb_way1_q(tlb_word_width+45 to tlb_word_width+49)); +tlb_way1_hi_calc_par(7) <= xor_reduce(tlb_way1_q(tlb_word_width+50 to tlb_word_width+57)); +tlb_way1_hi_calc_par(8) <= xor_reduce(tlb_way1_q(tlb_word_width+58 to tlb_word_width+65)); +tlb_way1_hi_calc_par(9) <= xor_reduce(tlb_way1_q(tlb_word_width+66 to tlb_word_width+73)); +tlb_way2_hi_calc_par(0) <= xor_reduce(tlb_way2_q(tlb_word_width+0 to tlb_word_width+7)); +tlb_way2_hi_calc_par(1) <= xor_reduce(tlb_way2_q(tlb_word_width+8 to tlb_word_width+15)); +tlb_way2_hi_calc_par(2) <= xor_reduce(tlb_way2_q(tlb_word_width+16 to tlb_word_width+23)); +tlb_way2_hi_calc_par(3) <= xor_reduce(tlb_way2_q(tlb_word_width+24 to tlb_word_width+31)); +tlb_way2_hi_calc_par(4) <= xor_reduce(tlb_way2_q(tlb_word_width+32 to tlb_word_width+39)); +tlb_way2_hi_calc_par(5) <= xor_reduce(tlb_way2_q(tlb_word_width+40 to tlb_word_width+44)); +tlb_way2_hi_calc_par(6) <= xor_reduce(tlb_way2_q(tlb_word_width+45 to tlb_word_width+49)); +tlb_way2_hi_calc_par(7) <= xor_reduce(tlb_way2_q(tlb_word_width+50 to tlb_word_width+57)); +tlb_way2_hi_calc_par(8) <= xor_reduce(tlb_way2_q(tlb_word_width+58 to tlb_word_width+65)); +tlb_way2_hi_calc_par(9) <= xor_reduce(tlb_way2_q(tlb_word_width+66 to tlb_word_width+73)); +tlb_way3_hi_calc_par(0) <= xor_reduce(tlb_way3_q(tlb_word_width+0 to tlb_word_width+7)); +tlb_way3_hi_calc_par(1) <= xor_reduce(tlb_way3_q(tlb_word_width+8 to tlb_word_width+15)); +tlb_way3_hi_calc_par(2) <= xor_reduce(tlb_way3_q(tlb_word_width+16 to tlb_word_width+23)); +tlb_way3_hi_calc_par(3) <= xor_reduce(tlb_way3_q(tlb_word_width+24 to tlb_word_width+31)); +tlb_way3_hi_calc_par(4) <= xor_reduce(tlb_way3_q(tlb_word_width+32 to tlb_word_width+39)); +tlb_way3_hi_calc_par(5) <= xor_reduce(tlb_way3_q(tlb_word_width+40 to tlb_word_width+44)); +tlb_way3_hi_calc_par(6) <= xor_reduce(tlb_way3_q(tlb_word_width+45 to tlb_word_width+49)); +tlb_way3_hi_calc_par(7) <= xor_reduce(tlb_way3_q(tlb_word_width+50 to tlb_word_width+57)); +tlb_way3_hi_calc_par(8) <= xor_reduce(tlb_way3_q(tlb_word_width+58 to tlb_word_width+65)); +tlb_way3_hi_calc_par(9) <= xor_reduce(tlb_way3_q(tlb_word_width+66 to tlb_word_width+73)); +tlb_way0_parerr <= or_reduce(tlb_way0_lo_calc_par(0 to 9) xor tlb_way0_q(74 to 83)) or + or_reduce(tlb_way0_hi_calc_par(0 to 9) xor tlb_way0_q(tlb_word_width+74 to tlb_word_width+83)); +tlb_way1_parerr <= or_reduce(tlb_way1_lo_calc_par(0 to 9) xor tlb_way1_q(74 to 83)) or + or_reduce(tlb_way1_hi_calc_par(0 to 9) xor tlb_way1_q(tlb_word_width+74 to tlb_word_width+83)); +tlb_way2_parerr <= or_reduce(tlb_way2_lo_calc_par(0 to 9) xor tlb_way2_q(74 to 83)) or + or_reduce(tlb_way2_hi_calc_par(0 to 9) xor tlb_way2_q(tlb_word_width+74 to tlb_word_width+83)); +tlb_way3_parerr <= or_reduce(tlb_way3_lo_calc_par(0 to 9) xor tlb_way3_q(74 to 83)) or + or_reduce(tlb_way3_hi_calc_par(0 to 9) xor tlb_way3_q(tlb_word_width+74 to tlb_word_width+83)); +tag4_parerr_d(0) <= tlb_way0_parerr; +tag4_parerr_d(1) <= tlb_way1_parerr; +tag4_parerr_d(2) <= tlb_way2_parerr; +tag4_parerr_d(3) <= tlb_way3_parerr; +-- end of TLB Parity Checking +-- lru data format +-- 0:3 - valid(0:3) +-- 4:6 - LRU +-- 7 - parity +-- 8:11 - iprot(0:3) +-- 12:14 - reserved +-- 15 - parity +lru_tag3_dataout_d <= lru_dataout; +-- tag3 phase signals, tlbwe/re ex5, tlbsx/srx ex6 +-- tlb_ctl may flush the thdid bits +tlb_tag4_d(0 TO tagpos_thdid-1) <= tlb_tag3_q(0 to tagpos_thdid-1); +tlb_tag4_d(tagpos_thdid TO tagpos_thdid+thdid_width-1) <= + (others => '0') when ((tlb_tag4_wayhit_q(tlb_ways)='1' or tlb_tag4_q(tagpos_endflag)='1' or or_reduce(tag4_parerr_q(0 to 4))='1') and + tlb_tag4_q(tagpos_type_ptereload)='0' and + (tlb_tag4_q(tagpos_type_ierat)='1' or tlb_tag4_q(tagpos_type_derat)='1')) + else (others => '0') when ((tlb_tag4_wayhit_q(tlb_ways)='1' or tlb_tag4_q(tagpos_endflag)='1' or or_reduce(tag4_parerr_q(0 to 4))='1') and + (tlb_tag4_q(tagpos_type_tlbsx)='1' or tlb_tag4_q(tagpos_type_tlbsrx)='1')) + else (others => '0') when (tlb_tag4_q(tagpos_endflag)='1' and tlb_tag4_q(tagpos_type_snoop)='1') + else (others => '0') when ((tlb_tag4_q(tagpos_type_tlbre)='1' or tlb_tag4_q(tagpos_type_tlbwe)='1' or tlb_tag4_q(tagpos_type_ptereload)='1') and + tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000") + else tlb_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag3_flush); +tlb_tag4_d(tagpos_thdid+thdid_width TO tlb_tag_width-1) <= tlb_tag3_q(tagpos_thdid+thdid_width to tlb_tag_width-1); +tlb_addr4_d <= tlb_addr3_q; +-- chosen way logic +-- tagpos_type_derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload +-- (ierat or derat) ptereload (tlbsx or tlbsrx) tlbre tlbwe tlb_wayhit MAS0.HES MAS0.ESEL old_lru tag4_way +-- 1 0 x x x 0 x x x 0 +-- 1 0 x x x 1 x x x 1 +-- 1 0 x x x 2 x x x 2 +-- 1 0 x x x 3 x x x 3 +-- x 0 1 x x 0 x x x 0 +-- x 0 1 x x 1 x x x 1 +-- x 0 1 x x 2 x x x 2 +-- x 0 1 x x 3 x x x 3 +-- x x x 1 x x x 0 x 0 +-- x x x 1 x x x 1 x 1 +-- x x x 1 x x x 2 x 2 +-- x x x 1 x x x 3 x 3 +-- x x x x 1 x 0 0 x 0 +-- x x x x 1 x 0 1 x 1 +-- x x x x 1 x 0 2 x 2 +-- x x x x 1 x 0 3 x 3 +-- x x x x 1 x 1 x 0 0 +-- x x x x 1 x 1 x 1 1 +-- x x x x 1 x 1 x 2 2 +-- x x x x 1 x 1 x 3 3 +-- x 1 x x x x x x 0 0 +-- x 1 x x x x x x 1 1 +-- x 1 x x x x x x 2 2 +-- x 1 x x x x x x 3 3 +tlb_tag4_way_d <= ( tlb_way0_q and (0 to tlb_way_width-1 => tlb_wayhit(0)) ) or + ( tlb_way1_q and (0 to tlb_way_width-1 => tlb_wayhit(1)) ); +tlb_tag4_way_clone_d <= ( tlb_way2_q and (0 to tlb_way_width-1 => tlb_wayhit(2)) ) or + ( tlb_way3_q and (0 to tlb_way_width-1 => tlb_wayhit(3)) ); +tlb_tag4_way_or <= tlb_tag4_way_q or tlb_tag4_way_clone_q; +tlb_tag4_way_rw_d <= ( tlb_way0_q and (0 to tlb_way_width-1 => (not tlb_tag3_clone1_q(tagpos_esel+1) and not tlb_tag3_clone1_q(tagpos_esel+2) and or_reduce(tlb_tag3_clone1_q(tagpos_thdid to tagpos_thdid+thdid_width-1)) and + (tlb_tag3_clone1_q(tagpos_type_tlbre) or (tlb_tag3_clone1_q(tagpos_type_tlbwe) and not tlb_tag3_clone1_q(tagpos_hes))) )) ) or + ( tlb_way1_q and (0 to tlb_way_width-1 => (not tlb_tag3_clone1_q(tagpos_esel+1) and tlb_tag3_clone1_q(tagpos_esel+2) and or_reduce(tlb_tag3_clone1_q(tagpos_thdid to tagpos_thdid+thdid_width-1)) and + (tlb_tag3_clone1_q(tagpos_type_tlbre) or (tlb_tag3_clone1_q(tagpos_type_tlbwe) and not tlb_tag3_clone1_q(tagpos_hes))) )) ) or + + ( tlb_way0_q and (0 to tlb_way_width-1 => (not lru_tag3_dataout_q(4) and not lru_tag3_dataout_q(5) and or_reduce(tlb_tag3_clone1_q(tagpos_thdid to tagpos_thdid+thdid_width-1)) and + (tlb_tag3_clone1_q(tagpos_type_ptereload) or (tlb_tag3_clone1_q(tagpos_type_tlbwe) and tlb_tag3_clone1_q(tagpos_hes))) )) ) or + ( tlb_way1_q and (0 to tlb_way_width-1 => (not lru_tag3_dataout_q(4) and lru_tag3_dataout_q(5) and or_reduce(tlb_tag3_clone1_q(tagpos_thdid to tagpos_thdid+thdid_width-1)) and + (tlb_tag3_clone1_q(tagpos_type_ptereload) or (tlb_tag3_clone1_q(tagpos_type_tlbwe) and tlb_tag3_clone1_q(tagpos_hes))) )) ); +tlb_tag4_way_rw_clone_d <= ( tlb_way2_q and (0 to tlb_way_width-1 => ( tlb_tag3_clone2_q(tagpos_esel+1) and not tlb_tag3_clone2_q(tagpos_esel+2) and or_reduce(tlb_tag3_clone2_q(tagpos_thdid to tagpos_thdid+thdid_width-1)) and + (tlb_tag3_clone2_q(tagpos_type_tlbre) or (tlb_tag3_clone2_q(tagpos_type_tlbwe) and not tlb_tag3_clone2_q(tagpos_hes))) )) ) or + ( tlb_way3_q and (0 to tlb_way_width-1 => ( tlb_tag3_clone2_q(tagpos_esel+1) and tlb_tag3_clone2_q(tagpos_esel+2) and or_reduce(tlb_tag3_clone2_q(tagpos_thdid to tagpos_thdid+thdid_width-1)) and + (tlb_tag3_clone2_q(tagpos_type_tlbre) or (tlb_tag3_clone2_q(tagpos_type_tlbwe) and not tlb_tag3_clone2_q(tagpos_hes))) )) ) or + + ( tlb_way2_q and (0 to tlb_way_width-1 => ( lru_tag3_dataout_q(4) and not lru_tag3_dataout_q(6) and or_reduce(tlb_tag3_clone2_q(tagpos_thdid to tagpos_thdid+thdid_width-1)) and + (tlb_tag3_clone2_q(tagpos_type_ptereload) or (tlb_tag3_clone2_q(tagpos_type_tlbwe) and tlb_tag3_clone2_q(tagpos_hes))) )) ) or + ( tlb_way3_q and (0 to tlb_way_width-1 => ( lru_tag3_dataout_q(4) and lru_tag3_dataout_q(6) and or_reduce(tlb_tag3_clone2_q(tagpos_thdid to tagpos_thdid+thdid_width-1)) and + (tlb_tag3_clone2_q(tagpos_type_ptereload) or (tlb_tag3_clone2_q(tagpos_type_tlbwe) and tlb_tag3_clone2_q(tagpos_hes))) )) ) ; +tlb_tag4_way_rw_or <= tlb_tag4_way_rw_q or tlb_tag4_way_rw_clone_q; +tlb_tag4_wayhit_d(0 TO tlb_ways-1) <= tlb_wayhit(0 to tlb_ways-1); +tlb_tag4_wayhit_d(tlb_ways) <= '1' when (tlb_tag4_wayhit_q(tlb_ways)='0' and tlb_wayhit(0 to tlb_ways-1) /= "0000" and + tlb_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000") + else '0'; +tlb_tag4_way_act <= or_reduce(tlb_tag3_clone1_q(tagpos_thdid to tagpos_thdid+thdid_width-1)) and not(tlb_tag4_wayhit_q(tlb_ways)) and not tlb_tag3_clone1_q(tagpos_type_ptereload) and + (tlb_tag3_clone1_q(tagpos_type_derat) or tlb_tag3_clone1_q(tagpos_type_ierat) or tlb_tag3_clone1_q(tagpos_type_tlbsx) or tlb_tag3_clone1_q(tagpos_type_tlbsrx)); +tlb_tag4_way_clone_act <= or_reduce(tlb_tag3_clone2_q(tagpos_thdid to tagpos_thdid+thdid_width-1)) and not(tlb_tag4_wayhit_q(tlb_ways)) and not tlb_tag3_clone2_q(tagpos_type_ptereload) and + (tlb_tag3_clone2_q(tagpos_type_derat) or tlb_tag3_clone2_q(tagpos_type_ierat) or tlb_tag3_clone2_q(tagpos_type_tlbsx) or tlb_tag3_clone2_q(tagpos_type_tlbsrx)); +tlb_tag4_way_rw_act <= or_reduce(tlb_tag3_clone1_q(tagpos_thdid to tagpos_thdid+thdid_width-1)) and + (tlb_tag3_clone1_q(tagpos_type_tlbre) or tlb_tag3_clone1_q(tagpos_type_tlbwe) or tlb_tag3_clone1_q(tagpos_type_ptereload)); +tlb_tag4_way_rw_clone_act <= or_reduce(tlb_tag3_clone2_q(tagpos_thdid to tagpos_thdid+thdid_width-1)) and + (tlb_tag3_clone2_q(tagpos_type_tlbre) or tlb_tag3_clone2_q(tagpos_type_tlbwe) or tlb_tag3_clone2_q(tagpos_type_ptereload)); +lru_tag4_dataout_d <= lru_tag3_dataout_q; +--tlb_tag3_d <= ( 0:51 epn & +-- 52:65 pid & +-- 66:67 IS & +-- 68:69 Class & +-- 70:73 state (pr,gs,as,cm) & +-- 74:77 thdid & +-- 78:81 size & +-- 82:83 derat_miss/ierat_miss & +-- 84:85 tlbsx/tlbsrx & +-- 86:87 inval_snoop/tlbre & +-- 88:89 tlbwe/ptereload & +-- 90:97 lpid & +-- 98 indirect +-- 99 atsel & +-- 100:102 esel & +-- 103:105 hes/wq(0:1) & +-- 106:107 lrat/pt & +-- 108 record form +-- 109 endflag +-- tagpos_epn : natural := 0; +-- tagpos_pid : natural := 52; -- 14 bits +-- tagpos_is : natural := 66; +-- tagpos_class : natural := 68; +-- tagpos_state : natural := 70; -- state: 0:pr 1:gs 2:as 3:cm +-- tagpos_thdid : natural := 74; +-- tagpos_size : natural := 78; +-- tagpos_type : natural := 82; -- derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload +-- tagpos_lpid : natural := 90; +-- tagpos_ind : natural := 98; +-- tagpos_atsel : natural := 99; +-- tagpos_esel : natural := 100; +-- tagpos_hes : natural := 103; +-- tagpos_wq : natural := 104; +-- tagpos_lrat : natural := 106; +-- tagpos_pt : natural := 107; +-- tagpos_recform : natural := 108; +-- tagpos_endflag : natural := 109; +-- For snoop ttypes... +-- tagpos_is -> IS(0): Local snoop +-- tagpos_is+1 to tagpos_is+3 -> IS(1)/Class: 0=all in lpar, 1=tid, 2=gs, 3=vpn, 4=class0, 5=class1, 6=class2, 7=class3 +-- bits 0-7: override for chunks of msb of address for bus snoops, depends on pgsize and mmucr1.tlbi_msb bit +-- mmucr1 11-LRUPEI, 12:13-ICTID/ITTID, 14:15-DCTID/DTTID, 16-DCCD, 17-TLBWE_BINV, 18-TLBI_MSB +-- size tlb_tag3_cmpmask_q: 01234 +-- 1GB 11111 +-- 256MB 01111 +-- 16MB 00111 +-- 1MB 00011 +-- 64KB 00001 +-- 4KB 00000 +addr_enable(0) <= ( or_reduce(tlb_tag3_clone1_q(tagpos_type_derat to tagpos_type_tlbsrx)) and + not tlb_tag3_clone1_q(tagpos_type_ptereload) ) + or ( tlb_tag3_clone1_q(tagpos_type_snoop) and Eq(tlb_tag3_clone1_q(tagpos_is to tagpos_is+3),"1011") ); +addr_enable(1) <= ( or_reduce(tlb_tag3_clone1_q(tagpos_type_derat to tagpos_type_tlbsrx)) and + not tlb_tag3_clone1_q(tagpos_type_ptereload) ) + or ( tlb_tag3_clone1_q(tagpos_type_snoop) and Eq(tlb_tag3_clone1_q(tagpos_is to tagpos_is+3),"1011") ) + or ( tlb_tag3_clone1_q(tagpos_type_snoop) and Eq(tlb_tag3_clone1_q(tagpos_is to tagpos_is+3),"0011") and + mmucr1_q(pos_tlbi_msb) and tlb_tag3_cmpmask_q(0) ); +addr_enable(2) <= ( or_reduce(tlb_tag3_clone1_q(tagpos_type_derat to tagpos_type_tlbsrx)) and + not tlb_tag3_clone1_q(tagpos_type_ptereload) ) + or ( tlb_tag3_clone1_q(tagpos_type_snoop) and Eq(tlb_tag3_clone1_q(tagpos_is to tagpos_is+3),"1011") ) + or ( tlb_tag3_clone1_q(tagpos_type_snoop) and Eq(tlb_tag3_clone1_q(tagpos_is to tagpos_is+3),"0011") and + mmucr1_q(pos_tlbi_msb) and tlb_tag3_cmpmask_q(1) ); +addr_enable(3) <= ( or_reduce(tlb_tag3_clone1_q(tagpos_type_derat to tagpos_type_tlbsrx)) and + not tlb_tag3_clone1_q(tagpos_type_ptereload) ) + or ( tlb_tag3_clone1_q(tagpos_type_snoop) and Eq(tlb_tag3_clone1_q(tagpos_is to tagpos_is+3),"1011") ) + or ( tlb_tag3_clone1_q(tagpos_type_snoop) and Eq(tlb_tag3_clone1_q(tagpos_is to tagpos_is+3),"0011") and + mmucr1_q(pos_tlbi_msb) and tlb_tag3_cmpmask_q(1) ) + or ( tlb_tag3_clone1_q(tagpos_type_snoop) and Eq(tlb_tag3_clone1_q(tagpos_is to tagpos_is+3),"0011") and + not mmucr1_q(pos_tlbi_msb) and tlb_tag3_cmpmask_q(0) ); +addr_enable(4) <= ( or_reduce(tlb_tag3_clone1_q(tagpos_type_derat to tagpos_type_tlbsrx)) and + not tlb_tag3_clone1_q(tagpos_type_ptereload) ) + or ( tlb_tag3_clone1_q(tagpos_type_snoop) and Eq(tlb_tag3_clone1_q(tagpos_is to tagpos_is+3),"1011") ) + or ( tlb_tag3_clone1_q(tagpos_type_snoop) and Eq(tlb_tag3_clone1_q(tagpos_is to tagpos_is+3),"0011") and + mmucr1_q(pos_tlbi_msb) and tlb_tag3_cmpmask_q(2) ) + or ( tlb_tag3_clone1_q(tagpos_type_snoop) and Eq(tlb_tag3_clone1_q(tagpos_is to tagpos_is+3),"0011") and + not mmucr1_q(pos_tlbi_msb) and tlb_tag3_cmpmask_q(1) ); +addr_enable(5) <= ( or_reduce(tlb_tag3_clone1_q(tagpos_type_derat to tagpos_type_tlbsrx)) and + not tlb_tag3_clone1_q(tagpos_type_ptereload) ) + or ( tlb_tag3_clone1_q(tagpos_type_snoop) and Eq(tlb_tag3_clone1_q(tagpos_is to tagpos_is+3),"1011") ) + or ( tlb_tag3_clone1_q(tagpos_type_snoop) and Eq(tlb_tag3_clone1_q(tagpos_is to tagpos_is+3),"0011") and + mmucr1_q(pos_tlbi_msb) and tlb_tag3_cmpmask_q(3) ) + or ( tlb_tag3_clone1_q(tagpos_type_snoop) and Eq(tlb_tag3_clone1_q(tagpos_is to tagpos_is+3),"0011") and + not mmucr1_q(pos_tlbi_msb) and tlb_tag3_cmpmask_q(2) ); +addr_enable(6) <= ( or_reduce(tlb_tag3_clone1_q(tagpos_type_derat to tagpos_type_tlbsrx)) and + not tlb_tag3_clone1_q(tagpos_type_ptereload) ) + or ( tlb_tag3_clone1_q(tagpos_type_snoop) and Eq(tlb_tag3_clone1_q(tagpos_is to tagpos_is+3),"1011") ) + or ( tlb_tag3_clone1_q(tagpos_type_snoop) and Eq(tlb_tag3_clone1_q(tagpos_is to tagpos_is+3),"0011") and + mmucr1_q(pos_tlbi_msb) ) + or ( tlb_tag3_clone1_q(tagpos_type_snoop) and Eq(tlb_tag3_clone1_q(tagpos_is to tagpos_is+3),"0011") and + not mmucr1_q(pos_tlbi_msb) and tlb_tag3_cmpmask_q(3) ); +addr_enable(7) <= ( or_reduce(tlb_tag3_clone1_q(tagpos_type_derat to tagpos_type_tlbsrx)) and + not tlb_tag3_clone1_q(tagpos_type_ptereload) ) + or ( tlb_tag3_clone1_q(tagpos_type_snoop) and Eq(tlb_tag3_clone1_q(tagpos_is+1 to tagpos_is+3),"011") ); +-- bit 8: override to ignore all address bits +addr_enable(8) <= ( or_reduce(tlb_tag3_clone1_q(tagpos_type_derat to tagpos_type_tlbsrx)) and + not tlb_tag3_clone1_q(tagpos_type_ptereload) ) + or ( tlb_tag3_clone1_q(tagpos_type_snoop) and Eq(tlb_tag3_clone1_q(tagpos_is+1 to tagpos_is+3),"011") ); +class_enable <= '1' when (tlb_tag3_clone1_q(tagpos_type_snoop)='1' and tlb_tag3_clone1_q(tagpos_is+1)='1') + else '0'; +pgsize_enable <= tlb_tag3_clone1_q(tagpos_type_snoop) and Eq(tlb_tag3_clone1_q(tagpos_is+1 to tagpos_is+3),"011"); +extclass_enable <= "00"; +-- tagpos_type : natural := 82; -- derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload +--thdid_enable <= '1' when (tlb_tag3_clone1_q(tagpos_type_derat to tagpos_type_ierat) /= 00 and tlb_tag3_clone1_q(tagpos_type_ptereload)='0') +-- else '0'; -- derat,ierat +thdid_enable <= or_reduce(tlb_tag3_clone1_q(tagpos_type_derat to tagpos_type_tlbsrx)) and not tlb_tag3_clone1_q(tagpos_type_ptereload); +pid_enable <= '1' when (tlb_tag3_clone1_q(tagpos_type_derat to tagpos_type_tlbsrx) /= "0000" and + tlb_tag3_clone1_q(tagpos_type_ptereload)='0') + else '1' when (tlb_tag3_clone1_q(tagpos_type_snoop)='1' and tlb_tag3_clone1_q(tagpos_is+1 to tagpos_is+3)="001") + else '1' when (tlb_tag3_clone1_q(tagpos_type_snoop)='1' and tlb_tag3_clone1_q(tagpos_is+1 to tagpos_is+3)="011") + else '0'; +-- gs enable +state_enable(0) <= '1' when (tlb_tag3_clone1_q(tagpos_type_derat to tagpos_type_tlbsrx) /= "0000" and + tlb_tag3_clone1_q(tagpos_type_ptereload)='0') + else '1' when (tlb_tag3_clone1_q(tagpos_type_snoop)='1' and tlb_tag3_clone1_q(tagpos_is+1 to tagpos_is+3)="010" ) + else '1' when (tlb_tag3_clone1_q(tagpos_type_snoop)='1' and tlb_tag3_clone1_q(tagpos_is+1 to tagpos_is+3)="011" ) + else '0'; +-- as enable +state_enable(1) <= '1' when (tlb_tag3_clone1_q(tagpos_type_derat to tagpos_type_tlbsrx) /= "0000" and + tlb_tag3_clone1_q(tagpos_type_ptereload)='0') + else '1' when (tlb_tag3_clone1_q(tagpos_type_snoop)='1' and tlb_tag3_clone1_q(tagpos_is+1 to tagpos_is+3)="011" ) + else '0'; +lpid_enable <= '1' when (tlb_tag3_clone1_q(tagpos_type_derat to tagpos_type_tlbsrx) /= "0000" and + tlb_tag3_clone1_q(tagpos_type_ptereload)='0') + else not(tlb_tag3_clone1_q(tagpos_hes)) when (tlb_tag3_clone1_q(tagpos_type_snoop)='1') + else '0'; +ind_enable <= ( or_reduce(tlb_tag3_clone1_q(tagpos_type_derat to tagpos_type_tlbsrx)) and + not tlb_tag3_clone1_q(tagpos_type_ptereload) ) + or ( tlb_tag3_clone1_q(tagpos_type_snoop) and Eq(tlb_tag3_clone1_q(tagpos_is+1 to tagpos_is+3),"011") ) + or ( tlb_tag3_clone1_q(tagpos_type_snoop) and Eq(tlb_tag3_clone1_q(tagpos_is+1 to tagpos_is+3),"001") and tlb_tag3_clone1_q(tagpos_ind) ); +iprot_enable <= tlb_tag3_clone1_q(tagpos_type_snoop); +-- For snoop ttypes... +-- tagpos_is -> IS(0): Local snoop +-- tagpos_is+1 to tagpos_is+3 -> IS(1)/Class: 0=all in lpar, 1=tid, 2=gs, 3=vpn, 4=class0, 5=class1, 6=class2, 7=class3 +comp_extclass <= (others => '0'); +comp_iprot <= '0'; +comp_ind <= tlb_tag3_clone1_q(tagpos_ind) and not(tlb_tag3_clone1_q(tagpos_type_snoop) and Eq(tlb_tag3_clone1_q(tagpos_is+1 to tagpos_is+3),"001")); +------------------- cloned compare logic, for timing: tlb array 0/1 on set above, tlb array 2/3 on set below +addr_enable_clone(0) <= ( or_reduce(tlb_tag3_clone2_q(tagpos_type_derat to tagpos_type_tlbsrx)) and + not tlb_tag3_clone2_q(tagpos_type_ptereload) ) + or ( tlb_tag3_clone2_q(tagpos_type_snoop) and Eq(tlb_tag3_clone2_q(tagpos_is to tagpos_is+3),"1011") ); +addr_enable_clone(1) <= ( or_reduce(tlb_tag3_clone2_q(tagpos_type_derat to tagpos_type_tlbsrx)) and + not tlb_tag3_clone2_q(tagpos_type_ptereload) ) + or ( tlb_tag3_clone2_q(tagpos_type_snoop) and Eq(tlb_tag3_clone2_q(tagpos_is to tagpos_is+3),"1011") ) + or ( tlb_tag3_clone2_q(tagpos_type_snoop) and Eq(tlb_tag3_clone2_q(tagpos_is to tagpos_is+3),"0011") and + mmucr1_clone_q(pos_tlbi_msb) and tlb_tag3_cmpmask_clone_q(0) ); +addr_enable_clone(2) <= ( or_reduce(tlb_tag3_clone2_q(tagpos_type_derat to tagpos_type_tlbsrx)) and + not tlb_tag3_clone2_q(tagpos_type_ptereload) ) + or ( tlb_tag3_clone2_q(tagpos_type_snoop) and Eq(tlb_tag3_clone2_q(tagpos_is to tagpos_is+3),"1011") ) + or ( tlb_tag3_clone2_q(tagpos_type_snoop) and Eq(tlb_tag3_clone2_q(tagpos_is to tagpos_is+3),"0011") and + mmucr1_clone_q(pos_tlbi_msb) and tlb_tag3_cmpmask_clone_q(1) ); +addr_enable_clone(3) <= ( or_reduce(tlb_tag3_clone2_q(tagpos_type_derat to tagpos_type_tlbsrx)) and + not tlb_tag3_clone2_q(tagpos_type_ptereload) ) + or ( tlb_tag3_clone2_q(tagpos_type_snoop) and Eq(tlb_tag3_clone2_q(tagpos_is to tagpos_is+3),"1011") ) + or ( tlb_tag3_clone2_q(tagpos_type_snoop) and Eq(tlb_tag3_clone2_q(tagpos_is to tagpos_is+3),"0011") and + mmucr1_clone_q(pos_tlbi_msb) and tlb_tag3_cmpmask_clone_q(1) ) + or ( tlb_tag3_clone2_q(tagpos_type_snoop) and Eq(tlb_tag3_clone2_q(tagpos_is to tagpos_is+3),"0011") and + not mmucr1_clone_q(pos_tlbi_msb) and tlb_tag3_cmpmask_clone_q(0) ); +addr_enable_clone(4) <= ( or_reduce(tlb_tag3_clone2_q(tagpos_type_derat to tagpos_type_tlbsrx)) and + not tlb_tag3_clone2_q(tagpos_type_ptereload) ) + or ( tlb_tag3_clone2_q(tagpos_type_snoop) and Eq(tlb_tag3_clone2_q(tagpos_is to tagpos_is+3),"1011") ) + or ( tlb_tag3_clone2_q(tagpos_type_snoop) and Eq(tlb_tag3_clone2_q(tagpos_is to tagpos_is+3),"0011") and + mmucr1_clone_q(pos_tlbi_msb) and tlb_tag3_cmpmask_clone_q(2) ) + or ( tlb_tag3_clone2_q(tagpos_type_snoop) and Eq(tlb_tag3_clone2_q(tagpos_is to tagpos_is+3),"0011") and + not mmucr1_clone_q(pos_tlbi_msb) and tlb_tag3_cmpmask_clone_q(1) ); +addr_enable_clone(5) <= ( or_reduce(tlb_tag3_clone2_q(tagpos_type_derat to tagpos_type_tlbsrx)) and + not tlb_tag3_clone2_q(tagpos_type_ptereload) ) + or ( tlb_tag3_clone2_q(tagpos_type_snoop) and Eq(tlb_tag3_clone2_q(tagpos_is to tagpos_is+3),"1011") ) + or ( tlb_tag3_clone2_q(tagpos_type_snoop) and Eq(tlb_tag3_clone2_q(tagpos_is to tagpos_is+3),"0011") and + mmucr1_clone_q(pos_tlbi_msb) and tlb_tag3_cmpmask_clone_q(3) ) + or ( tlb_tag3_clone2_q(tagpos_type_snoop) and Eq(tlb_tag3_clone2_q(tagpos_is to tagpos_is+3),"0011") and + not mmucr1_clone_q(pos_tlbi_msb) and tlb_tag3_cmpmask_clone_q(2) ); +addr_enable_clone(6) <= ( or_reduce(tlb_tag3_clone2_q(tagpos_type_derat to tagpos_type_tlbsrx)) and + not tlb_tag3_clone2_q(tagpos_type_ptereload) ) + or ( tlb_tag3_clone2_q(tagpos_type_snoop) and Eq(tlb_tag3_clone2_q(tagpos_is to tagpos_is+3),"1011") ) + or ( tlb_tag3_clone2_q(tagpos_type_snoop) and Eq(tlb_tag3_clone2_q(tagpos_is to tagpos_is+3),"0011") and + mmucr1_clone_q(pos_tlbi_msb) ) + or ( tlb_tag3_clone2_q(tagpos_type_snoop) and Eq(tlb_tag3_clone2_q(tagpos_is to tagpos_is+3),"0011") and + not mmucr1_clone_q(pos_tlbi_msb) and tlb_tag3_cmpmask_clone_q(3) ); +addr_enable_clone(7) <= ( or_reduce(tlb_tag3_clone2_q(tagpos_type_derat to tagpos_type_tlbsrx)) and + not tlb_tag3_clone2_q(tagpos_type_ptereload) ) + or ( tlb_tag3_clone2_q(tagpos_type_snoop) and Eq(tlb_tag3_clone2_q(tagpos_is+1 to tagpos_is+3),"011") ); +-- bit 8: override to ignore all address bits +addr_enable_clone(8) <= ( or_reduce(tlb_tag3_clone2_q(tagpos_type_derat to tagpos_type_tlbsrx)) and + not tlb_tag3_clone2_q(tagpos_type_ptereload) ) + or ( tlb_tag3_clone2_q(tagpos_type_snoop) and Eq(tlb_tag3_clone2_q(tagpos_is+1 to tagpos_is+3),"011") ); +class_enable_clone <= '1' when (tlb_tag3_clone2_q(tagpos_type_snoop)='1' and tlb_tag3_clone2_q(tagpos_is+1)='1') + else '0'; +pgsize_enable_clone <= tlb_tag3_clone2_q(tagpos_type_snoop) and Eq(tlb_tag3_clone2_q(tagpos_is+1 to tagpos_is+3),"011"); +extclass_enable_clone <= "00"; +thdid_enable_clone <= or_reduce(tlb_tag3_clone2_q(tagpos_type_derat to tagpos_type_tlbsrx)) and not tlb_tag3_clone2_q(tagpos_type_ptereload); +pid_enable_clone <= '1' when (tlb_tag3_clone2_q(tagpos_type_derat to tagpos_type_tlbsrx) /= "0000" and + tlb_tag3_clone2_q(tagpos_type_ptereload)='0') + else '1' when (tlb_tag3_clone2_q(tagpos_type_snoop)='1' and tlb_tag3_clone2_q(tagpos_is+1 to tagpos_is+3)="001") + else '1' when (tlb_tag3_clone2_q(tagpos_type_snoop)='1' and tlb_tag3_clone2_q(tagpos_is+1 to tagpos_is+3)="011") + else '0'; +-- gs enable +state_enable_clone(0) <= '1' when (tlb_tag3_clone2_q(tagpos_type_derat to tagpos_type_tlbsrx) /= "0000" and + tlb_tag3_clone2_q(tagpos_type_ptereload)='0') + else '1' when (tlb_tag3_clone2_q(tagpos_type_snoop)='1' and tlb_tag3_clone2_q(tagpos_is+1 to tagpos_is+3)="010" ) + else '1' when (tlb_tag3_clone2_q(tagpos_type_snoop)='1' and tlb_tag3_clone2_q(tagpos_is+1 to tagpos_is+3)="011" ) + else '0'; +-- as enable +state_enable_clone(1) <= '1' when (tlb_tag3_clone2_q(tagpos_type_derat to tagpos_type_tlbsrx) /= "0000" and + tlb_tag3_clone2_q(tagpos_type_ptereload)='0') + else '1' when (tlb_tag3_clone2_q(tagpos_type_snoop)='1' and tlb_tag3_clone2_q(tagpos_is+1 to tagpos_is+3)="011" ) + else '0'; +lpid_enable_clone <= '1' when (tlb_tag3_clone2_q(tagpos_type_derat to tagpos_type_tlbsrx) /= "0000" and + tlb_tag3_clone2_q(tagpos_type_ptereload)='0') + else not(tlb_tag3_clone2_q(tagpos_hes)) when (tlb_tag3_clone2_q(tagpos_type_snoop)='1') + else '0'; +ind_enable_clone <= ( or_reduce(tlb_tag3_clone2_q(tagpos_type_derat to tagpos_type_tlbsrx)) and + not tlb_tag3_clone2_q(tagpos_type_ptereload) ) + or ( tlb_tag3_clone2_q(tagpos_type_snoop) and Eq(tlb_tag3_clone2_q(tagpos_is+1 to tagpos_is+3),"011") ) + or ( tlb_tag3_clone2_q(tagpos_type_snoop) and Eq(tlb_tag3_clone2_q(tagpos_is+1 to tagpos_is+3),"001") and tlb_tag3_clone2_q(tagpos_ind) ); +iprot_enable_clone <= tlb_tag3_clone2_q(tagpos_type_snoop); +-- For snoop ttypes... +-- tagpos_is -> IS(0): Local snoop +-- tagpos_is+1 to tagpos_is+3 -> IS(1)/Class: 0=all in lpar, 1=tid, 2=gs, 3=vpn, 4=class0, 5=class1, 6=class2, 7=class3 +comp_extclass_clone <= (others => '0'); +comp_iprot_clone <= '0'; +comp_ind_clone <= tlb_tag3_clone2_q(tagpos_ind) and not(tlb_tag3_clone2_q(tagpos_type_snoop) and Eq(tlb_tag3_clone2_q(tagpos_is+1 to tagpos_is+3),"001")); +------------------- end of cloned compare logic +-- tag4 phase signals, tlbwe/re ex6, tlbsx/srx ex7 +tlb_tag4_type_sig(0 TO 7) <= tlb_tag4_q(tagpos_type to tagpos_type+7); +tlb_tag4_esel_sig(0 TO 2) <= tlb_tag4_q(tagpos_esel to tagpos_esel+2); +tlb_tag4_hes_sig <= tlb_tag4_q(tagpos_hes); +tlb_tag4_wq_sig(0 TO 1) <= tlb_tag4_q(tagpos_wq to tagpos_wq+1); +tlb_tag4_is_sig(0 TO 3) <= tlb_tag4_q(tagpos_is to tagpos_is+3); +tlb_tag4_hv_op <= or_reduce( not msr_gs_q and not msr_pr_q and tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) ); +multihit <= not(Eq(tlb_tag4_wayhit_q(0 to 3),"0000") or Eq(tlb_tag4_wayhit_q(0 to 3),"1000") or Eq(tlb_tag4_wayhit_q(0 to 3),"0100") + or Eq(tlb_tag4_wayhit_q(0 to 3),"0010") or Eq(tlb_tag4_wayhit_q(0 to 3),"0001")) + and or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1)); +-- unused tagpos_is def is mas1_v, mas1_iprot for tlbwe, and is (pte.valid & 0) for ptereloads +-- hes=1 valid bits update data +tlb_tag4_hes1_mas1_v(0 TO thdid_width-1) <= + ( (tlb_tag4_q(tagpos_is) & lru_tag4_dataout_q(1 to 3)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+0) and tlb_tag4_q(tagpos_hes) and not lru_tag4_dataout_q(4) and not lru_tag4_dataout_q(5))) ) + or ( (lru_tag4_dataout_q(0) & tlb_tag4_q(tagpos_is) & lru_tag4_dataout_q(2 to 3)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+0) and tlb_tag4_q(tagpos_hes) and not lru_tag4_dataout_q(4) and lru_tag4_dataout_q(5))) ) + or ( (lru_tag4_dataout_q(0 to 1) & tlb_tag4_q(tagpos_is) & lru_tag4_dataout_q(3)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+0) and tlb_tag4_q(tagpos_hes) and lru_tag4_dataout_q(4) and not lru_tag4_dataout_q(6))) ) + or ( (lru_tag4_dataout_q(0 to 2) & tlb_tag4_q(tagpos_is)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+0) and tlb_tag4_q(tagpos_hes) and lru_tag4_dataout_q(4) and lru_tag4_dataout_q(6))) ) + + or ( (tlb_tag4_q(tagpos_is) & lru_tag4_dataout_q(1 to 3)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+1) and tlb_tag4_q(tagpos_hes) and not lru_tag4_dataout_q(4) and not lru_tag4_dataout_q(5))) ) + or ( (lru_tag4_dataout_q(0) & tlb_tag4_q(tagpos_is) & lru_tag4_dataout_q(2 to 3)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+1) and tlb_tag4_q(tagpos_hes) and not lru_tag4_dataout_q(4) and lru_tag4_dataout_q(5))) ) + or ( (lru_tag4_dataout_q(0 to 1) & tlb_tag4_q(tagpos_is) & lru_tag4_dataout_q(3)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+1) and tlb_tag4_q(tagpos_hes) and lru_tag4_dataout_q(4) and not lru_tag4_dataout_q(6))) ) + or ( (lru_tag4_dataout_q(0 to 2) & tlb_tag4_q(tagpos_is)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+1) and tlb_tag4_q(tagpos_hes) and lru_tag4_dataout_q(4) and lru_tag4_dataout_q(6))) ) + + or ( (tlb_tag4_q(tagpos_is) & lru_tag4_dataout_q(1 to 3)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+2) and tlb_tag4_q(tagpos_hes) and not lru_tag4_dataout_q(4) and not lru_tag4_dataout_q(5))) ) + or ( (lru_tag4_dataout_q(0) & tlb_tag4_q(tagpos_is) & lru_tag4_dataout_q(2 to 3)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+2) and tlb_tag4_q(tagpos_hes) and not lru_tag4_dataout_q(4) and lru_tag4_dataout_q(5))) ) + or ( (lru_tag4_dataout_q(0 to 1) & tlb_tag4_q(tagpos_is) & lru_tag4_dataout_q(3)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+2) and tlb_tag4_q(tagpos_hes) and lru_tag4_dataout_q(4) and not lru_tag4_dataout_q(6))) ) + or ( (lru_tag4_dataout_q(0 to 2) & tlb_tag4_q(tagpos_is)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+2) and tlb_tag4_q(tagpos_hes) and lru_tag4_dataout_q(4) and lru_tag4_dataout_q(6))) ) + + or ( (tlb_tag4_q(tagpos_is) & lru_tag4_dataout_q(1 to 3)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+3) and tlb_tag4_q(tagpos_hes) and not lru_tag4_dataout_q(4) and not lru_tag4_dataout_q(5))) ) + or ( (lru_tag4_dataout_q(0) & tlb_tag4_q(tagpos_is) & lru_tag4_dataout_q(2 to 3)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+3) and tlb_tag4_q(tagpos_hes) and not lru_tag4_dataout_q(4) and lru_tag4_dataout_q(5))) ) + or ( (lru_tag4_dataout_q(0 to 1) & tlb_tag4_q(tagpos_is) & lru_tag4_dataout_q(3)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+3) and tlb_tag4_q(tagpos_hes) and lru_tag4_dataout_q(4) and not lru_tag4_dataout_q(6))) ) + or ( (lru_tag4_dataout_q(0 to 2) & tlb_tag4_q(tagpos_is)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+3) and tlb_tag4_q(tagpos_hes) and lru_tag4_dataout_q(4) and lru_tag4_dataout_q(6))) ); +-- hes=0 valid bits update data +tlb_tag4_hes0_mas1_v(0 TO thdid_width-1) <= + ( (tlb_tag4_q(tagpos_is) & lru_tag4_dataout_q(1 to 3)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+0) and not tlb_tag4_q(tagpos_hes) and not tlb_tag4_q(tagpos_esel+1) and not tlb_tag4_q(tagpos_esel+2))) ) + or ( (lru_tag4_dataout_q(0) & tlb_tag4_q(tagpos_is) & lru_tag4_dataout_q(2 to 3)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+0) and not tlb_tag4_q(tagpos_hes) and not tlb_tag4_q(tagpos_esel+1) and tlb_tag4_q(tagpos_esel+2))) ) + or ( (lru_tag4_dataout_q(0 to 1) & tlb_tag4_q(tagpos_is) & lru_tag4_dataout_q(3)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+0) and not tlb_tag4_q(tagpos_hes) and tlb_tag4_q(tagpos_esel+1) and not tlb_tag4_q(tagpos_esel+2))) ) + or ( (lru_tag4_dataout_q(0 to 2) & tlb_tag4_q(tagpos_is)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+0) and not tlb_tag4_q(tagpos_hes) and tlb_tag4_q(tagpos_esel+1) and tlb_tag4_q(tagpos_esel+2))) ) + + or ( (tlb_tag4_q(tagpos_is) & lru_tag4_dataout_q(1 to 3)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+1) and not tlb_tag4_q(tagpos_hes) and not tlb_tag4_q(tagpos_esel+1) and not tlb_tag4_q(tagpos_esel+2))) ) + or ( (lru_tag4_dataout_q(0) & tlb_tag4_q(tagpos_is) & lru_tag4_dataout_q(2 to 3)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+1) and not tlb_tag4_q(tagpos_hes) and not tlb_tag4_q(tagpos_esel+1) and tlb_tag4_q(tagpos_esel+2))) ) + or ( (lru_tag4_dataout_q(0 to 1) & tlb_tag4_q(tagpos_is) & lru_tag4_dataout_q(3)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+1) and not tlb_tag4_q(tagpos_hes) and tlb_tag4_q(tagpos_esel+1) and not tlb_tag4_q(tagpos_esel+2))) ) + or ( (lru_tag4_dataout_q(0 to 2) & tlb_tag4_q(tagpos_is)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+1) and not tlb_tag4_q(tagpos_hes) and tlb_tag4_q(tagpos_esel+1) and tlb_tag4_q(tagpos_esel+2))) ) + + or ( (tlb_tag4_q(tagpos_is) & lru_tag4_dataout_q(1 to 3)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+2) and not tlb_tag4_q(tagpos_hes) and not tlb_tag4_q(tagpos_esel+1) and not tlb_tag4_q(tagpos_esel+2))) ) + or ( (lru_tag4_dataout_q(0) & tlb_tag4_q(tagpos_is) & lru_tag4_dataout_q(2 to 3)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+2) and not tlb_tag4_q(tagpos_hes) and not tlb_tag4_q(tagpos_esel+1) and tlb_tag4_q(tagpos_esel+2))) ) + or ( (lru_tag4_dataout_q(0 to 1) & tlb_tag4_q(tagpos_is) & lru_tag4_dataout_q(3)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+2) and not tlb_tag4_q(tagpos_hes) and tlb_tag4_q(tagpos_esel+1) and not tlb_tag4_q(tagpos_esel+2))) ) + or ( (lru_tag4_dataout_q(0 to 2) & tlb_tag4_q(tagpos_is)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+2) and not tlb_tag4_q(tagpos_hes) and tlb_tag4_q(tagpos_esel+1) and tlb_tag4_q(tagpos_esel+2))) ) + + or ( (tlb_tag4_q(tagpos_is) & lru_tag4_dataout_q(1 to 3)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+3) and not tlb_tag4_q(tagpos_hes) and not tlb_tag4_q(tagpos_esel+1) and not tlb_tag4_q(tagpos_esel+2))) ) + or ( (lru_tag4_dataout_q(0) & tlb_tag4_q(tagpos_is) & lru_tag4_dataout_q(2 to 3)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+3) and not tlb_tag4_q(tagpos_hes) and not tlb_tag4_q(tagpos_esel+1) and tlb_tag4_q(tagpos_esel+2))) ) + or ( (lru_tag4_dataout_q(0 to 1) & tlb_tag4_q(tagpos_is) & lru_tag4_dataout_q(3)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+3) and not tlb_tag4_q(tagpos_hes) and tlb_tag4_q(tagpos_esel+1) and not tlb_tag4_q(tagpos_esel+2))) ) + or ( (lru_tag4_dataout_q(0 to 2) & tlb_tag4_q(tagpos_is)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+3) and not tlb_tag4_q(tagpos_hes) and tlb_tag4_q(tagpos_esel+1) and tlb_tag4_q(tagpos_esel+2))) ); +-- hes=1 iprot bits update data +tlb_tag4_hes1_mas1_iprot(0 TO thdid_width-1) <= + ( (tlb_tag4_q(tagpos_is+1) & lru_tag4_dataout_q(9 to 11)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+0) and tlb_tag4_q(tagpos_hes) and not lru_tag4_dataout_q(4) and not lru_tag4_dataout_q(5))) ) + or ( (lru_tag4_dataout_q(8) & tlb_tag4_q(tagpos_is+1) & lru_tag4_dataout_q(10 to 11)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+0) and tlb_tag4_q(tagpos_hes) and not lru_tag4_dataout_q(4) and lru_tag4_dataout_q(5))) ) + or ( (lru_tag4_dataout_q(8 to 9) & tlb_tag4_q(tagpos_is+1) & lru_tag4_dataout_q(11)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+0) and tlb_tag4_q(tagpos_hes) and lru_tag4_dataout_q(4) and not lru_tag4_dataout_q(6))) ) + or ( (lru_tag4_dataout_q(8 to 10) & tlb_tag4_q(tagpos_is+1)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+0) and tlb_tag4_q(tagpos_hes) and lru_tag4_dataout_q(4) and lru_tag4_dataout_q(6))) ) + + or ( (tlb_tag4_q(tagpos_is+1) & lru_tag4_dataout_q(9 to 11)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+1) and tlb_tag4_q(tagpos_hes) and not lru_tag4_dataout_q(4) and not lru_tag4_dataout_q(5))) ) + or ( (lru_tag4_dataout_q(8) & tlb_tag4_q(tagpos_is+1) & lru_tag4_dataout_q(10 to 11)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+1) and tlb_tag4_q(tagpos_hes) and not lru_tag4_dataout_q(4) and lru_tag4_dataout_q(5))) ) + or ( (lru_tag4_dataout_q(8 to 9) & tlb_tag4_q(tagpos_is+1) & lru_tag4_dataout_q(11)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+1) and tlb_tag4_q(tagpos_hes) and lru_tag4_dataout_q(4) and not lru_tag4_dataout_q(6))) ) + or ( (lru_tag4_dataout_q(8 to 10) & tlb_tag4_q(tagpos_is+1)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+1) and tlb_tag4_q(tagpos_hes) and lru_tag4_dataout_q(4) and lru_tag4_dataout_q(6))) ) + + or ( (tlb_tag4_q(tagpos_is+1) & lru_tag4_dataout_q(9 to 11)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+2) and tlb_tag4_q(tagpos_hes) and not lru_tag4_dataout_q(4) and not lru_tag4_dataout_q(5))) ) + or ( (lru_tag4_dataout_q(8) & tlb_tag4_q(tagpos_is+1) & lru_tag4_dataout_q(10 to 11)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+2) and tlb_tag4_q(tagpos_hes) and not lru_tag4_dataout_q(4) and lru_tag4_dataout_q(5))) ) + or ( (lru_tag4_dataout_q(8 to 9) & tlb_tag4_q(tagpos_is+1) & lru_tag4_dataout_q(11)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+2) and tlb_tag4_q(tagpos_hes) and lru_tag4_dataout_q(4) and not lru_tag4_dataout_q(6))) ) + or ( (lru_tag4_dataout_q(8 to 10) & tlb_tag4_q(tagpos_is+1)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+2) and tlb_tag4_q(tagpos_hes) and lru_tag4_dataout_q(4) and lru_tag4_dataout_q(6))) ) + + or ( (tlb_tag4_q(tagpos_is+1) & lru_tag4_dataout_q(9 to 11)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+3) and tlb_tag4_q(tagpos_hes) and not lru_tag4_dataout_q(4) and not lru_tag4_dataout_q(5))) ) + or ( (lru_tag4_dataout_q(8) & tlb_tag4_q(tagpos_is+1) & lru_tag4_dataout_q(10 to 11)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+3) and tlb_tag4_q(tagpos_hes) and not lru_tag4_dataout_q(4) and lru_tag4_dataout_q(5))) ) + or ( (lru_tag4_dataout_q(8 to 9) & tlb_tag4_q(tagpos_is+1) & lru_tag4_dataout_q(11)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+3) and tlb_tag4_q(tagpos_hes) and lru_tag4_dataout_q(4) and not lru_tag4_dataout_q(6))) ) + or ( (lru_tag4_dataout_q(8 to 10) & tlb_tag4_q(tagpos_is+1)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+3) and tlb_tag4_q(tagpos_hes) and lru_tag4_dataout_q(4) and lru_tag4_dataout_q(6))) ); +-- hes=0 iprot bits update data +tlb_tag4_hes0_mas1_iprot(0 TO thdid_width-1) <= + ( (tlb_tag4_q(tagpos_is+1) & lru_tag4_dataout_q(9 to 11)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+0) and not tlb_tag4_q(tagpos_hes) and not tlb_tag4_q(tagpos_esel+1) and not tlb_tag4_q(tagpos_esel+2))) ) + or ( (lru_tag4_dataout_q(8) & tlb_tag4_q(tagpos_is+1) & lru_tag4_dataout_q(10 to 11)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+0) and not tlb_tag4_q(tagpos_hes) and not tlb_tag4_q(tagpos_esel+1) and tlb_tag4_q(tagpos_esel+2))) ) + or ( (lru_tag4_dataout_q(8 to 9) & tlb_tag4_q(tagpos_is+1) & lru_tag4_dataout_q(11)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+0) and not tlb_tag4_q(tagpos_hes) and tlb_tag4_q(tagpos_esel+1) and not tlb_tag4_q(tagpos_esel+2))) ) + or ( (lru_tag4_dataout_q(8 to 10) & tlb_tag4_q(tagpos_is+1)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+0) and not tlb_tag4_q(tagpos_hes) and tlb_tag4_q(tagpos_esel+1) and tlb_tag4_q(tagpos_esel+2))) ) + + or ( (tlb_tag4_q(tagpos_is+1) & lru_tag4_dataout_q(9 to 11)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+1) and not tlb_tag4_q(tagpos_hes) and not tlb_tag4_q(tagpos_esel+1) and not tlb_tag4_q(tagpos_esel+2))) ) + or ( (lru_tag4_dataout_q(8) & tlb_tag4_q(tagpos_is+1) & lru_tag4_dataout_q(10 to 11)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+1) and not tlb_tag4_q(tagpos_hes) and not tlb_tag4_q(tagpos_esel+1) and tlb_tag4_q(tagpos_esel+2))) ) + or ( (lru_tag4_dataout_q(8 to 9) & tlb_tag4_q(tagpos_is+1) & lru_tag4_dataout_q(11)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+1) and not tlb_tag4_q(tagpos_hes) and tlb_tag4_q(tagpos_esel+1) and not tlb_tag4_q(tagpos_esel+2))) ) + or ( (lru_tag4_dataout_q(8 to 10) & tlb_tag4_q(tagpos_is+1)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+1) and not tlb_tag4_q(tagpos_hes) and tlb_tag4_q(tagpos_esel+1) and tlb_tag4_q(tagpos_esel+2))) ) + + or ( (tlb_tag4_q(tagpos_is+1) & lru_tag4_dataout_q(9 to 11)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+2) and not tlb_tag4_q(tagpos_hes) and not tlb_tag4_q(tagpos_esel+1) and not tlb_tag4_q(tagpos_esel+2))) ) + or ( (lru_tag4_dataout_q(8) & tlb_tag4_q(tagpos_is+1) & lru_tag4_dataout_q(10 to 11)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+2) and not tlb_tag4_q(tagpos_hes) and not tlb_tag4_q(tagpos_esel+1) and tlb_tag4_q(tagpos_esel+2))) ) + or ( (lru_tag4_dataout_q(8 to 9) & tlb_tag4_q(tagpos_is+1) & lru_tag4_dataout_q(11)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+2) and not tlb_tag4_q(tagpos_hes) and tlb_tag4_q(tagpos_esel+1) and not tlb_tag4_q(tagpos_esel+2))) ) + or ( (lru_tag4_dataout_q(8 to 10) & tlb_tag4_q(tagpos_is+1)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+2) and not tlb_tag4_q(tagpos_hes) and tlb_tag4_q(tagpos_esel+1) and tlb_tag4_q(tagpos_esel+2))) ) + + or ( (tlb_tag4_q(tagpos_is+1) & lru_tag4_dataout_q(9 to 11)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+3) and not tlb_tag4_q(tagpos_hes) and not tlb_tag4_q(tagpos_esel+1) and not tlb_tag4_q(tagpos_esel+2))) ) + or ( (lru_tag4_dataout_q(8) & tlb_tag4_q(tagpos_is+1) & lru_tag4_dataout_q(10 to 11)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+3) and not tlb_tag4_q(tagpos_hes) and not tlb_tag4_q(tagpos_esel+1) and tlb_tag4_q(tagpos_esel+2))) ) + or ( (lru_tag4_dataout_q(8 to 9) & tlb_tag4_q(tagpos_is+1) & lru_tag4_dataout_q(11)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+3) and not tlb_tag4_q(tagpos_hes) and tlb_tag4_q(tagpos_esel+1) and not tlb_tag4_q(tagpos_esel+2))) ) + or ( (lru_tag4_dataout_q(8 to 10) & tlb_tag4_q(tagpos_is+1)) and (0 to thdid_width-1 => (tlb_tag4_q(tagpos_thdid+3) and not tlb_tag4_q(tagpos_hes) and tlb_tag4_q(tagpos_esel+1) and tlb_tag4_q(tagpos_esel+2))) ); +-- ptereload write phase signals +tlb_tag4_ptereload_v(0 TO thdid_width-1) <= (ptereload_req_pte_lat(ptepos_valid) & lru_tag4_dataout_q(1 to 3)) + when (lru_tag4_dataout_q(4 to 5)="00") + else (lru_tag4_dataout_q(0) & ptereload_req_pte_lat(ptepos_valid) & lru_tag4_dataout_q(2 to 3)) + when (lru_tag4_dataout_q(4 to 5)="01") + else (lru_tag4_dataout_q(0 to 1) & ptereload_req_pte_lat(ptepos_valid) & lru_tag4_dataout_q(3)) + when (lru_tag4_dataout_q(4)='1' and lru_tag4_dataout_q(6)='0') + else (lru_tag4_dataout_q(0 to 2) & ptereload_req_pte_lat(ptepos_valid)) + when (lru_tag4_dataout_q(4)='1' and lru_tag4_dataout_q(6)='1') + else lru_tag4_dataout_q(0 to 3); +tlb_tag4_ptereload_iprot(0 TO thdid_width-1) <= ('0' & lru_tag4_dataout_q(9 to 11)) + when (lru_tag4_dataout_q(4 to 5)="00") + else (lru_tag4_dataout_q(8) & '0' & lru_tag4_dataout_q(10 to 11)) + when (lru_tag4_dataout_q(4 to 5)="01") + else (lru_tag4_dataout_q(8 to 9) & '0' & lru_tag4_dataout_q(11)) + when (lru_tag4_dataout_q(4)='1' and lru_tag4_dataout_q(6)='0') + else (lru_tag4_dataout_q(8 to 10) & '0') + when (lru_tag4_dataout_q(4)='1' and lru_tag4_dataout_q(6)='1') + else lru_tag4_dataout_q(8 to 11); +-- 0 1 2 3 4 5 6 7 +-- tag type bits --> derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload +-- lrat_tag4_hit_status(0:3) -> val,hit,multihit,inval_pgsize +lru_write_d <= (others => '1') when ( (tlb_tag4_q(tagpos_type_derat)='1' or tlb_tag4_q(tagpos_type_ierat)='1') + and tlb_tag4_q(tagpos_type_ptereload)='0' + and tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000" + and ((tlb_tag4_wayhit_q(0 to 3) /= "0000" and multihit='0') or + (xu_mm_xucr4_mmu_mchk_q='0' and xu_mm_ccr2_notlb_b='1' and (multihit='1' or or_reduce(tag4_parerr_q(0 to 4))='1'))) ) + else (others => '1') when ( tlb_tag4_q(tagpos_type_snoop)='1' + and tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000" + and (tlb_tag4_wayhit_q(0 to 3) /= "0000" or tlb_tag4_q(tagpos_is+1 to tagpos_is+3)="000") ) + else (others => '1') when ( tlb_tag4_q(tagpos_type_tlbwe)='1' and tlb_tag4_q(tagpos_pr)='0' and ex6_illeg_instr(1)='0' + and (tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not tlb_ctl_tag4_flush)/="0000" + and ((or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and tlb_resv_match_vec)='1' + and tlb_tag4_q(tagpos_wq to tagpos_wq+1)="01" and mmucfg_twc='1') + or tlb_tag4_q(tagpos_wq to tagpos_wq+1)="00" or tlb_tag4_q(tagpos_wq to tagpos_wq+1)="11") + and ((tlb_tag4_q(tagpos_gs)='0' and tlb_tag4_q(tagpos_atsel)='0') or + (tlb_tag4_q(tagpos_gs)='1' and tlb_tag4_q(tagpos_hes)='1' and tlb_tag4_q(tagpos_is+1)='0' + and tlb0cfg_gtwe='1' and tlb_tag4_epcr_dgtmi='0' and lrat_tag4_hit_status="1100" + and (((lru_tag4_dataout_q(0)='0' or lru_tag4_dataout_q(8)='0') and lru_tag4_dataout_q(4 to 5)="00") + or ((lru_tag4_dataout_q(1)='0' or lru_tag4_dataout_q(9)='0') and lru_tag4_dataout_q(4 to 5)="01") + or ((lru_tag4_dataout_q(2)='0' or lru_tag4_dataout_q(10)='0') and lru_tag4_dataout_q(4)='1' and lru_tag4_dataout_q(6)='0') + or ((lru_tag4_dataout_q(3)='0' or lru_tag4_dataout_q(11)='0') and lru_tag4_dataout_q(4)='1' and lru_tag4_dataout_q(6)='1')))) ) + else (others => ptereload_req_pte_lat(ptepos_valid)) when ( tlb_tag4_q(tagpos_type_ptereload)='1' + and (tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000") + and (tlb_tag4_q(tagpos_gs)='0' or (tlb_tag4_q(tagpos_gs)='1' and lrat_tag4_hit_status="1100")) + and (tlb_tag4_q(tagpos_wq to tagpos_wq+1)="10") + and (tlb_tag4_q(tagpos_pt)='1') + and (((lru_tag4_dataout_q(0)='0' or lru_tag4_dataout_q(8)='0') and lru_tag4_dataout_q(4 to 5)="00") + or ((lru_tag4_dataout_q(1)='0' or lru_tag4_dataout_q(9)='0') and lru_tag4_dataout_q(4 to 5)="01") + or ((lru_tag4_dataout_q(2)='0' or lru_tag4_dataout_q(10)='0') and lru_tag4_dataout_q(4)='1' and lru_tag4_dataout_q(6)='0') + or ((lru_tag4_dataout_q(3)='0' or lru_tag4_dataout_q(11)='0') and lru_tag4_dataout_q(4)='1' and lru_tag4_dataout_q(6)='1')) ) + else (others => '0'); +lru_wr_addr_d <= tlb_addr4_q; +-- lru data format +-- 0:3 - valid(0:3) +-- 4:6 - LRU +-- 7 - parity +-- 8:11 - iprot(0:3) +-- 12:14 - reserved +-- 15 - parity +-- tagpos_type: derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload +lru_update_clear_enab <= '1' when ( xu_mm_xucr4_mmu_mchk_q='0' and xu_mm_ccr2_notlb_b='1' and + ((tlb_tag4_q(tagpos_type_derat)='1' or tlb_tag4_q(tagpos_type_ierat)='1') and tlb_tag4_q(tagpos_type_ptereload)='0') and + (multihit='1' or or_reduce(tag4_parerr_q(0 to 4))='1') ) + else '0'; +lru_update_data_enab <= '1' when ( ((tlb_tag4_q(tagpos_type_derat)='1' or tlb_tag4_q(tagpos_type_ierat)='1') and tlb_tag4_q(tagpos_type_ptereload)='0' and + multihit='0' and or_reduce(tag4_parerr_q(0 to 4))='0') + or (tlb_tag4_q(tagpos_type_tlbwe)='1' and (tlb_tag4_q(tagpos_atsel)='0' or tlb_tag4_q(tagpos_gs)='1')) + or (tlb_tag4_q(tagpos_type_ptereload)='1') + or (tlb_tag4_q(tagpos_type_snoop)='1') ) + else '0'; +-- valid bits +lru_datain_d(0 TO 3) <= (others => '0') when lru_update_clear_enab='1' + else ( lru_tag4_dataout_q(0 to 3) and + (lru_tag4_dataout_q(8 to 11) or not(tlb_tag4_wayhit_q(0 to 3))) ) + when tlb_tag4_q(tagpos_type_snoop)='1' + else tlb_tag4_hes1_mas1_v(0 to thdid_width-1) + when tlb_tag4_q(tagpos_type_tlbwe)='1' and tlb_tag4_q(tagpos_hes)='1' + else tlb_tag4_hes0_mas1_v(0 to thdid_width-1) + when tlb_tag4_q(tagpos_type_tlbwe)='1' and tlb_tag4_q(tagpos_hes)='0' + else tlb_tag4_ptereload_v(0 to thdid_width-1) + when tlb_tag4_q(tagpos_type_ptereload)='1' + else lru_tag4_dataout_q(0 to 3); +-- LRU bits +lru_datain_d(4 TO 6) <= (others => '0') when lru_update_clear_enab='1' + else lru_update_data when lru_update_data_enab='1' + else lru_tag4_dataout_q(4 to 6); +lru_datain_alt_d(4 TO 6) <= lru_update_data_alt when ((tlb_tag4_q(tagpos_type_derat)='1' or tlb_tag4_q(tagpos_type_ierat)='1' or + tlb_tag4_q(tagpos_type_snoop)='1') and tlb_tag4_q(tagpos_type_ptereload)='0') + else lru_update_data when (tlb_tag4_q(tagpos_type_tlbwe)='1' and (tlb_tag4_q(tagpos_atsel)='0' or tlb_tag4_q(tagpos_gs)='1')) + else lru_update_data when (tlb_tag4_q(tagpos_type_ptereload)='1') + else lru_tag4_dataout_q(4 to 6); +-- old lru value if no hits +lru_update_data_alt <= (lru_tag4_dataout_q(4 to 6) and (4 to 6 => not tlb_tag4_wayhit_q(4))) or + (lru_update_data_snoophit_eco and (4 to 6 => tlb_tag4_wayhit_q(4) and tlb_tag4_q(tagpos_type_snoop))) or + (lru_update_data_erathit_eco and (4 to 6 => tlb_tag4_wayhit_q(4) and not tlb_tag4_q(tagpos_type_ptereload) + and (tlb_tag4_q(tagpos_type_derat) or tlb_tag4_q(tagpos_type_ierat)))); +lru_datain_alt_d(7) <= xor_reduce(lru_datain_d(0 to 3) & lru_datain_alt_d(4 to 6)); +lru_update_data_snoophit_eco(0 TO 2) <= "000" when (tlb_tag4_wayhit_q(0) and not lru_tag4_dataout_q(6) and not lru_tag4_dataout_q(8))='1' + else "001" when (tlb_tag4_wayhit_q(0) and lru_tag4_dataout_q(6) and not lru_tag4_dataout_q(8))='1' + else "010" when (tlb_tag4_wayhit_q(1) and not lru_tag4_dataout_q(6) and not lru_tag4_dataout_q(9))='1' + else "011" when (tlb_tag4_wayhit_q(1) and lru_tag4_dataout_q(6) and not lru_tag4_dataout_q(9))='1' + else "100" when (tlb_tag4_wayhit_q(2) and not lru_tag4_dataout_q(5) and not lru_tag4_dataout_q(10))='1' + else "110" when (tlb_tag4_wayhit_q(2) and lru_tag4_dataout_q(5) and not lru_tag4_dataout_q(10))='1' + else "101" when (tlb_tag4_wayhit_q(3) and not lru_tag4_dataout_q(5) and not lru_tag4_dataout_q(11))='1' + else "111" when (tlb_tag4_wayhit_q(3) and lru_tag4_dataout_q(5) and not lru_tag4_dataout_q(11))='1' + else lru_tag4_dataout_q(4 to 6); +lru_datain_alt_d(8) <= xor_reduce(lru_datain_d(0 to 3) & lru_update_data_snoophit_eco(0 to 2)); +lru_update_data_erathit_eco(0 TO 2) <= "01" & lru_tag4_dataout_q(6) when (tlb_tag4_wayhit_q(0) and not lru_tag4_dataout_q(9))='1' + else '1' & lru_tag4_dataout_q(5) & '0' when (tlb_tag4_wayhit_q(0) and not lru_tag4_dataout_q(10))='1' + else '1' & lru_tag4_dataout_q(5) & '1' when (tlb_tag4_wayhit_q(0) and not lru_tag4_dataout_q(11))='1' + else '1' & lru_tag4_dataout_q(5) & '0' when (tlb_tag4_wayhit_q(1) and not lru_tag4_dataout_q(10))='1' + else '1' & lru_tag4_dataout_q(5) & '1' when (tlb_tag4_wayhit_q(1) and not lru_tag4_dataout_q(11))='1' + else "00" & lru_tag4_dataout_q(6) when (tlb_tag4_wayhit_q(1) and not lru_tag4_dataout_q(8))='1' + else '1' & lru_tag4_dataout_q(5) & '1' when (tlb_tag4_wayhit_q(2) and not lru_tag4_dataout_q(11))='1' + else "00" & lru_tag4_dataout_q(6) when (tlb_tag4_wayhit_q(2) and not lru_tag4_dataout_q(8))='1' + else "01" & lru_tag4_dataout_q(6) when (tlb_tag4_wayhit_q(2) and not lru_tag4_dataout_q(9))='1' + else "00" & lru_tag4_dataout_q(6) when (tlb_tag4_wayhit_q(3) and not lru_tag4_dataout_q(8))='1' + else "01" & lru_tag4_dataout_q(6) when (tlb_tag4_wayhit_q(3) and not lru_tag4_dataout_q(9))='1' + else '1' & lru_tag4_dataout_q(5) & '0' when (tlb_tag4_wayhit_q(3) and not lru_tag4_dataout_q(10))='1' + else lru_tag4_dataout_q(4 to 6); +lru_datain_alt_d(9) <= xor_reduce(lru_datain_d(0 to 3) & lru_update_data_erathit_eco(0 to 2)); +-- iprot bits +lru_datain_d(8 TO 11) <= (others => '0') when lru_update_clear_enab='1' + else tlb_tag4_hes1_mas1_iprot(0 to thdid_width-1) + when tlb_tag4_q(tagpos_type_tlbwe)='1' and tlb_tag4_q(tagpos_hes)='1' + else tlb_tag4_hes0_mas1_iprot(0 to thdid_width-1) + when tlb_tag4_q(tagpos_type_tlbwe)='1' and tlb_tag4_q(tagpos_hes)='0' + else tlb_tag4_ptereload_iprot(0 to thdid_width-1) + when tlb_tag4_q(tagpos_type_ptereload)='1' + else lru_tag4_dataout_q(8 to 11); +lru_datain_d(12 TO 14) <= (others => '0'); +-- LRU Parity Generation +lru_datain_d(7) <= xor_reduce(lru_datain_d(0 to 6)); +lru_datain_d(15) <= xor_reduce(lru_datain_d(8 to 14) & mmucr1_q(pos_lru_pei)); +-- LRU Parity Checking +lru_calc_par(0) <= xor_reduce(lru_tag3_dataout_q(0 to 6)); +lru_calc_par(1) <= xor_reduce(lru_tag3_dataout_q(8 to 14)); +tag4_parerr_d(4) <= or_reduce(lru_calc_par(0 to 1) xor (lru_tag3_dataout_q(7) & lru_tag3_dataout_q(15))); +tlb_tag4_parerr_enab <= or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1)) and + (or_reduce(tlb_tag4_q(tagpos_type_derat to tagpos_type_tlbsrx)) or tlb_tag4_q(tagpos_type_tlbre)); +-- end of LRU Parity Checking +-- tag4 phase signals, tlbwe/re ex6, tlbsx/srx ex7 +-- 0 1 2 3 4 5 6 7 +-- tag type bits --> derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload +-- tlb_tag4_is: 0:3 -> IS/Class: 0=all, 1=tid, 2=gs, 3=epn, 4=class0, 5=class1, 6=class2, 7=class3 +-- Encoder for the LRU update data +-- +-- Final Table Listing +-- *INPUTS*============================================*OUTPUTS*=============* +-- | | | +-- | tlb_tag4_type_sig | lru_update_data | +-- | | tlb_tag4_hes_sig | | | +-- | | | tlb_tag4_esel_sig | | | +-- | | | | tlb_tag4_wq_sig | | | +-- | | | | | tlb_tag4_is_sig | | | +-- | | | | | | tlb_tag4_wayhit_q | | | +-- | | | | | | | lru_tag4_dataout_q | | | +-- | | | | | | | | | | | +-- | | | | | | | | | | | +-- | | | | | | | | 111111 | | | +-- | 01234567 | 012 01 0123 0123 0123456789012345 | 012 | +-- *TYPE*==============================================+=====================+ +-- | PPPPPPPP P PPP PP PPPP PPPP PPPPPPPPPPPPPPPP | PPP | +-- *POLARITY*----------------------------------------->| +++ | +-- *PHASE*-------------------------------------------->| TTT | +-- *OPTIMIZE*----------------------------------------->| AAA | +-- *TERMS*=============================================+=====================+ +-- 1 | ------0- - --- -- ---- ---1 111-----1110---- | 1.1 | +-- 2 | ----1--- - --- -- ---- 0--1 111------110---- | 1.1 | +-- 3 | ------1- 1 --- -- 1--- ---- 1-110-----10---- | 1.1 | +-- 4 | -------1 - --- -- ---- ---- 1-110-----10---- | 1.1 | +-- 5 | ----0-00 - --- -- ---- 1--- 1111------10---- | 111 | +-- 6 | ------1- 0 -00 -- 1--- ---- -111------10---- | 111 | +-- 7 | ----1--- - --- -- ---- 00-1 111-------10---- | 1.1 | +-- 8 | ----0-00 - --- -- ---- -1-- 111-------10---- | 1.1 | +-- 9 | ------1- 0 -01 -- 1--- ---- 1-1-------10---- | 1.1 | +-- 10 | ----0-00 - --- -- ---- --1- 111-----11-0---- | 1.1 | +-- 11 | ------1- 1 --- -- 1--- ---- 11-11-0----0---- | ..1 | +-- 12 | -------1 - --- -- ---- ---- 11-11-0----0---- | ..1 | +-- 13 | ------1- 1 --- -- ---- ---- --110-1----0---- | ..1 | +-- 14 | -------1 - --- -- ---- ---- --110-1----0---- | ..1 | +-- 15 | ------1- 1 --- -- 1--- ---- 101---1----0---- | 1.1 | +-- 16 | -------1 - --- -- ---- ---- 101---1----0---- | 1.1 | +-- 17 | ------1- 1 --- -- 1--- ---- 011---1----0---- | 1.1 | +-- 18 | -------1 - --- -- ---- ---- 011---1----0---- | 1.1 | +-- 19 | ----0-00 - --- -- ---- ---0 --1---1----0---- | ..1 | +-- 20 | ------1- 0 -0- -- ---- ---- --1---1----0---- | ..1 | +-- 21 | ------1- 1 --- -- 1--- ---- 111100-----0---- | .1. | +-- 22 | -------1 - --- -- ---- ---- 111100-----0---- | .1. | +-- 23 | ------1- 1 --- -- 1--- ---- 110--------0---- | ..1 | +-- 24 | -------1 - --- -- ---- ---- 110--------0---- | ..1 | +-- 25 | ----1--- - --- -- ---- 0001 111--------0---- | 1.1 | +-- 26 | ------1- 0 -10 -- 1--- ---- 11---------0---- | ..1 | +-- 27 | ------0- - --- -- ---- -1-- 1-11----1011---- | .1. | +-- 28 | -------- 1 --- -- ---- ---- 1----1--1-11---- | .1. | +-- 29 | ------0- - --- -- ---- ---- 1----1--1-11---- | .1. | +-- 30 | ------1- 0 -01 -- ---- ---- 1-11----1-11---- | .1. | +-- 31 | ------0- - --- -- ---- --1- 11------110----- | 1.. | +-- 32 | ----1--- - --- -- ---- 0-1- 11-------10----- | 1.. | +-- 33 | ------1- 1 --- -- 1--- ---- 111100----0----- | .1. | +-- 34 | -------1 - --- -- ---- ---- 111100----0----- | .1. | +-- 35 | ------1- 1 --- -- 1--- ---- 1-110-----0----- | 1.. | +-- 36 | -------1 - --- -- ---- ---- 1-110-----0----- | 1.. | +-- 37 | ----0-00 - --- -- ---- 1--- 1111------0----- | 11. | +-- 38 | ------1- 0 -00 -- 1--- ---- -111------0----- | 11. | +-- 39 | ------1- 1 --- -- 1--- ---- 10--------0----- | 1.. | +-- 40 | -------1 - --- -- ---- ---- 10--------0----- | 1.. | +-- 41 | ------1- 1 --- -- 1--- ---- 01--------0----- | 1.. | +-- 42 | -------1 - --- -- ---- ---- 01--------0----- | 1.. | +-- 43 | ----1--- - --- -- ---- 001- 11--------0----- | 1.. | +-- 44 | ----0-00 - --- -- ---- -1-- 11--------0----- | 1.. | +-- 45 | ------1- 0 -01 -- 1--- ---- 1---------0----- | 1.. | +-- 46 | -------- 1 --- -- ---- ---- --1---1-111----- | ..1 | +-- 47 | ------0- - --- -- ---- ---- --1---1-111----- | ..1 | +-- 48 | ------1- 0 -11 -- ---- ---- 111-----111----- | ..1 | +-- 49 | ------1- 1 --- -- ---- ---- --1-0-1---1----- | ..1 | +-- 50 | -------1 - --- -- ---- ---- --1-0-1---1----- | ..1 | +-- 51 | -------- - --- -- ---- ---- -01---1---1----- | ..1 | +-- 52 | -------- - --- -- ---- ---- 0-1---1---1----- | ..1 | +-- 53 | ------00 - --- -- ---- ---0 --1---1---1----- | ..1 | +-- 54 | ------00 - --- -- ---- --1- --1---1---1----- | ..1 | +-- 55 | ------1- 0 -0- -- ---- ---- --1---1---1----- | ..1 | +-- 56 | ----1--- - --- -- ---- 001- 1110------1----- | 1.1 | +-- 57 | ------1- 1 --- -- 1--- ---- 11-0------1----- | ..1 | +-- 58 | -------1 - --- -- ---- ---- 11-0------1----- | ..1 | +-- 59 | ------1- 1 --- -- 1--- ---- --1-1---10------ | .1. | +-- 60 | -------1 - --- -- ---- ---- --1-1---10------ | .1. | +-- 61 | ----0-00 - --- -- ---- --1- 1111----10------ | .11 | +-- 62 | ----0-00 - --- -- ---- ---1 1-11----10------ | .1. | +-- 63 | ----1--- - --- -- ---- -1-- 1-11----10------ | .1. | +-- 64 | ------1- 0 -10 -- 1--- ---- 11-1----10------ | .11 | +-- 65 | ------1- 0 -11 -- 1--- ---- 1-1-----10------ | .1. | +-- 66 | ------1- 1 --- -- 1--- ---- 11111-0--0------ | ..1 | +-- 67 | -------1 - --- -- ---- ---- 11111-0--0------ | ..1 | +-- 68 | ------00 - --- -- ---- 11-- --1---1--0------ | ..1 | +-- 69 | ----1--- - --- -- ---- 01-- ------1--0------ | ..1 | +-- 70 | ------1- 1 --- -- 1--- ---- -11100---0------ | .1. | +-- 71 | -------1 - --- -- ---- ---- -11100---0------ | .1. | +-- 72 | ------1- 1 --- -- 1--- ---- -1--11---0------ | .1. | +-- 73 | -------1 - --- -- ---- ---- -1--11---0------ | .1. | +-- 74 | ----0--- - --- -- 1--- ---- 11-0-1---0------ | .1. | +-- 75 | ----0-00 - --- -- ---- -0-- 1----1---0------ | .1. | +-- 76 | ------1- 0 -1- -- ---- ---- 1----1---0------ | .1. | +-- 77 | ----0-00 - --- -- ---- 1--- 1-11-----0------ | .1. | +-- 78 | ------1- 0 -00 -- 1--- ---- --11-----0------ | .1. | +-- 79 | ------1- 1 --- -- 1--- ---- 0--------0------ | .1. | +-- 80 | -------1 - --- -- ---- ---- 0--------0------ | .1. | +-- 81 | ----1--- - --- -- ---- 01-- 1--------0------ | .1. | +-- 82 | ----0--- - --- -- 1--- ---- 11-0-1--11------ | 11. | +-- 83 | -------- 1 --- -- ---- ---- 11--1---11------ | 1.. | +-- 84 | ------0- - --- -- ---- ---- 11--1---11------ | 1.. | +-- 85 | -------1 - --- -- ---- ---- 1--0----11------ | 1.. | +-- 86 | ------1- 1 --- -- 1--- ---- 1-0-----11------ | 1.. | +-- 87 | -------1 - --- -- ---- ---- 1-0-----11------ | 1.. | +-- 88 | ----0-00 - --- -- ---- ---1 11------11------ | 1.. | +-- 89 | ------1- 0 -1- -- ---- ---- 11------11------ | 1.. | +-- 90 | ----1--- - --- -- ---- 0--- 11--1----1------ | 1.. | +-- 91 | ----1--- - --- -- ---- 01-- 1110-----1------ | 1.1 | +-- 92 | ----1--- - --- -- ---- 01-- 110------1------ | 1.. | +-- 93 | ------1- 1 --- -- 1--- ---- 11111-0-0------- | ..1 | +-- 94 | -------1 - --- -- ---- ---- 11111-0-0------- | ..1 | +-- 95 | ----1--- - --- -- ---- 1--- ------1-0------- | ..1 | +-- 96 | ----0-00 - --- -- ---- --1- 111-----0------- | ..1 | +-- 97 | ------1- 0 -10 -- 1--- ---- 11------0------- | ..1 | +-- 98 | ------1- 1 --- -- 1--- ---- 1--0-0--1------- | 1.. | +-- 99 | ------1- 1 --- -- ---- ---- 1---11--1------- | .1. | +-- 100 | -------1 - --- -- ---- ---- 1---11--1------- | .1. | +-- 101 | ------00 - --- -- ---- -0-- 1----1--1------- | .1. | +-- 102 | ------1- 0 -1- -- ---- ---- 1----1--1------- | .1. | +-- 103 | ----1--- - --- -- ---- ---- 1----1--1------- | .1. | +-- 104 | ----1--- - --- -- ---- -0-- 11--1---1------- | 1.. | +-- 105 | ----1--- - --- -- ---- 1--- 1110----1------- | 1.1 | +-- 106 | ----1--- - --- -- ---- 1--- 110-----1------- | 1.. | +-- 107 | ----1--- - --- -- ---- 1--- 10------1------- | .1. | +-- 108 | ------1- 1 --- -- 1--- ---- -0------1------- | .1. | +-- 109 | -------1 - --- -- ---- ---- -0------1------- | .1. | +-- 110 | ------1- 1 --- -- 0--- ---- ----0-1--------- | ..1 | +-- 111 | ------00 - --- -- ---- 0000 --1---1--------- | ..1 | +-- 112 | ----1--- - --- -- ---- --0- --1---1--------- | ..1 | +-- 113 | ------1- 1 --- -- 0--- ---- --1---1--------- | ..1 | +-- 114 | -------- - --- -- ---- ---- 00----1--------- | ..1 | +-- 115 | ------1- - --- -- 0--- ---- -0----1--------- | ..1 | +-- 116 | ------1- 0 --0 -- ---- ---- -0----1--------- | ..1 | +-- 117 | ------1- 0 -1- -- ---- ---- -0----1--------- | ..1 | +-- 118 | ------00 - --- -- ---- ---- -0----1--------- | ..1 | +-- 119 | ------1- - --- -- 0--- ---- 0-----1--------- | ..1 | +-- 120 | ------1- 0 --1 -- ---- ---- 0-----1--------- | ..1 | +-- 121 | ------1- 0 -1- -- ---- ---- 0-----1--------- | ..1 | +-- 122 | ------00 - --- -- ---- ---- 0-----1--------- | ..1 | +-- 123 | ----1--- - --- -- ---- 0000 ------1--------- | ..1 | +-- 124 | ------1- 0 -0- -- 0--- ---- ------1--------- | ..1 | +-- 125 | ----0--- - --0 -- 1--- ---- 11-0-1---------- | .1. | +-- 126 | ----0--- - -01 -- ---- ---- 11-0-1---------- | .1. | +-- 127 | ----0-0- - --- -- ---- ---- 11-0-1---------- | .1. | +-- 128 | ----0--- - --1 -- ---- ---- 110--1---------- | .1. | +-- 129 | ----0--- 1 --- -- ---- ---- 110--1---------- | .1. | +-- 130 | ----0-0- - --- -- ---- ---- 110--1---------- | .1. | +-- 131 | ------1- 0 -00 -- 1--- ---- --0--1---------- | .1. | +-- 132 | ------00 - --- -- ---- 0000 1----1---------- | .1. | +-- 133 | ----1--- - --- -- ---- 0--- 1----1---------- | .1. | +-- 134 | ------1- - -1- -- 0--- ---- 1----1---------- | .1. | +-- 135 | ------1- 1 --- -- 0--- ---- 1----1---------- | .1. | +-- 136 | ----1--- - --- -- ---- 0000 -----1---------- | .1. | +-- 137 | ------1- 1 --- -- 0--- ---- 10--1----------- | .1. | +-- 138 | ------00 - --- -- ---- 0000 11--1----------- | 1.. | +-- 139 | ----1--- - --- -- ---- 00-- 11--1----------- | 1.. | +-- 140 | ------1- 1 --- -- 0--- ---- 11--1----------- | 1.. | +-- 141 | ----1--- - --- -- ---- 0000 ----1----------- | 1.. | +-- 142 | ------1- 1 --- -- 1--- ---- 1100------------ | 1.1 | +-- 143 | -------1 - --- -- ---- ---- 1100------------ | 1.1 | +-- 144 | ------1- 1 --- -- 1--- ---- 1010------------ | 1.1 | +-- 145 | -------1 - --- -- ---- ---- 1010------------ | 1.1 | +-- 146 | ------1- 1 --- -- 1--- ---- 0110------------ | 1.1 | +-- 147 | -------1 - --- -- ---- ---- 0110------------ | 1.1 | +-- 148 | ----1--- - --- -- ---- 0001 1110------------ | 1.1 | +-- 149 | ----0-00 - --- -- ---- ---- 1110------------ | 1.1 | +-- 150 | ------1- 0 -00 -- 1--- ---- -110------------ | 1.1 | +-- 151 | ------1- 0 -01 -- 1--- ---- 1-10------------ | 1.1 | +-- 152 | ------1- 0 -10 -- 1--- ---- 11-0------------ | 1.1 | +-- 153 | ------1- 0 -00 -- 1--- ---- 0--0------------ | .1. | +-- 154 | ------1- 1 --- -- 1--- ---- 100------------- | 1.. | +-- 155 | -------1 - --- -- ---- ---- 100------------- | 1.. | +-- 156 | ------1- 1 --- -- 1--- ---- 010------------- | 1.. | +-- 157 | -------1 - --- -- ---- ---- 010------------- | 1.. | +-- 158 | ----1--- - --- -- ---- 00-1 110------------- | 1.. | +-- 159 | ----1--- - --- -- ---- 001- 110------------- | 1.. | +-- 160 | ------1- 0 -11 -- ---- ---- 110------------- | 1.. | +-- 161 | ----0-00 - --- -- ---- ---- 110------------- | 1.. | +-- 162 | ------1- 0 -00 -- 1--- ---- -10------------- | 1.. | +-- 163 | ------1- 0 -00 -- 1--- ---- 0-0------------- | .1. | +-- 164 | ------1- 0 -01 -- 1--- ---- 1-0------------- | 1.. | +-- 165 | ------1- 0 -11 -- 0--- ---- 111------------- | ..1 | +-- 166 | ------1- 1 --- -- 1--- ---- 00-------------- | .1. | +-- 167 | -------1 - --- -- ---- ---- 00-------------- | .1. | +-- 168 | ----1--- - --- -- ---- 0--1 10-------------- | .1. | +-- 169 | ----1--- - --- -- ---- 0-1- 10-------------- | .1. | +-- 170 | ----1--- - --- -- ---- 01-- 10-------------- | .1. | +-- 171 | ------1- 0 -1- -- ---- ---- 10-------------- | .1. | +-- 172 | ----0-00 - --- -- ---- ---- 10-------------- | .1. | +-- 173 | ------1- 0 -00 -- 1--- ---- -0-------------- | .1. | +-- 174 | ------1- 0 -1- -- 0--- ---- 11-------------- | 1.. | +-- 175 | ------1- 0 -01 -- 0--- ---- 1--------------- | .1. | +-- *=========================================================================* +-- +-- Table LRU_UPDATE_DATA Signal Assignments for Product Terms +MQQ1:LRU_UPDATE_DATA_PT(1) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_WAYHIT_Q(3) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(8) & + LRU_TAG4_DATAOUT_Q(9) & LRU_TAG4_DATAOUT_Q(10) & + LRU_TAG4_DATAOUT_Q(11) ) , STD_ULOGIC_VECTOR'("011111110")); +MQQ2:LRU_UPDATE_DATA_PT(2) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_WAYHIT_Q(0) & + TLB_TAG4_WAYHIT_Q(3) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(9) & LRU_TAG4_DATAOUT_Q(10) & + LRU_TAG4_DATAOUT_Q(11) ) , STD_ULOGIC_VECTOR'("101111110")); +MQQ3:LRU_UPDATE_DATA_PT(3) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(3) & + LRU_TAG4_DATAOUT_Q(4) & LRU_TAG4_DATAOUT_Q(10) & + LRU_TAG4_DATAOUT_Q(11) ) , STD_ULOGIC_VECTOR'("111111010")); +MQQ4:LRU_UPDATE_DATA_PT(4) <= + Eq(( TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(3) & + LRU_TAG4_DATAOUT_Q(4) & LRU_TAG4_DATAOUT_Q(10) & + LRU_TAG4_DATAOUT_Q(11) ) , STD_ULOGIC_VECTOR'("1111010")); +MQQ5:LRU_UPDATE_DATA_PT(5) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_TYPE_SIG(6) & + TLB_TAG4_TYPE_SIG(7) & TLB_TAG4_WAYHIT_Q(0) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(3) & + LRU_TAG4_DATAOUT_Q(10) & LRU_TAG4_DATAOUT_Q(11) + ) , STD_ULOGIC_VECTOR'("0001111110")); +MQQ6:LRU_UPDATE_DATA_PT(6) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & TLB_TAG4_ESEL_SIG(2) & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(3) & + LRU_TAG4_DATAOUT_Q(10) & LRU_TAG4_DATAOUT_Q(11) + ) , STD_ULOGIC_VECTOR'("1000111110")); +MQQ7:LRU_UPDATE_DATA_PT(7) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_WAYHIT_Q(0) & + TLB_TAG4_WAYHIT_Q(1) & TLB_TAG4_WAYHIT_Q(3) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(10) & + LRU_TAG4_DATAOUT_Q(11) ) , STD_ULOGIC_VECTOR'("100111110")); +MQQ8:LRU_UPDATE_DATA_PT(8) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_TYPE_SIG(6) & + TLB_TAG4_TYPE_SIG(7) & TLB_TAG4_WAYHIT_Q(1) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(10) & + LRU_TAG4_DATAOUT_Q(11) ) , STD_ULOGIC_VECTOR'("000111110")); +MQQ9:LRU_UPDATE_DATA_PT(9) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & TLB_TAG4_ESEL_SIG(2) & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(10) & + LRU_TAG4_DATAOUT_Q(11) ) , STD_ULOGIC_VECTOR'("100111110")); +MQQ10:LRU_UPDATE_DATA_PT(10) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_TYPE_SIG(6) & + TLB_TAG4_TYPE_SIG(7) & TLB_TAG4_WAYHIT_Q(2) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(8) & + LRU_TAG4_DATAOUT_Q(9) & LRU_TAG4_DATAOUT_Q(11) + ) , STD_ULOGIC_VECTOR'("0001111110")); +MQQ11:LRU_UPDATE_DATA_PT(11) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(3) & + LRU_TAG4_DATAOUT_Q(4) & LRU_TAG4_DATAOUT_Q(6) & + LRU_TAG4_DATAOUT_Q(11) ) , STD_ULOGIC_VECTOR'("111111100")); +MQQ12:LRU_UPDATE_DATA_PT(12) <= + Eq(( TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(3) & + LRU_TAG4_DATAOUT_Q(4) & LRU_TAG4_DATAOUT_Q(6) & + LRU_TAG4_DATAOUT_Q(11) ) , STD_ULOGIC_VECTOR'("1111100")); +MQQ13:LRU_UPDATE_DATA_PT(13) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(3) & + LRU_TAG4_DATAOUT_Q(4) & LRU_TAG4_DATAOUT_Q(6) & + LRU_TAG4_DATAOUT_Q(11) ) , STD_ULOGIC_VECTOR'("1111010")); +MQQ14:LRU_UPDATE_DATA_PT(14) <= + Eq(( TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(3) & LRU_TAG4_DATAOUT_Q(4) & + LRU_TAG4_DATAOUT_Q(6) & LRU_TAG4_DATAOUT_Q(11) + ) , STD_ULOGIC_VECTOR'("111010")); +MQQ15:LRU_UPDATE_DATA_PT(15) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(6) & LRU_TAG4_DATAOUT_Q(11) + ) , STD_ULOGIC_VECTOR'("11110110")); +MQQ16:LRU_UPDATE_DATA_PT(16) <= + Eq(( TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(6) & LRU_TAG4_DATAOUT_Q(11) + ) , STD_ULOGIC_VECTOR'("110110")); +MQQ17:LRU_UPDATE_DATA_PT(17) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(6) & LRU_TAG4_DATAOUT_Q(11) + ) , STD_ULOGIC_VECTOR'("11101110")); +MQQ18:LRU_UPDATE_DATA_PT(18) <= + Eq(( TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(6) & LRU_TAG4_DATAOUT_Q(11) + ) , STD_ULOGIC_VECTOR'("101110")); +MQQ19:LRU_UPDATE_DATA_PT(19) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_TYPE_SIG(6) & + TLB_TAG4_TYPE_SIG(7) & TLB_TAG4_WAYHIT_Q(3) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(6) & + LRU_TAG4_DATAOUT_Q(11) ) , STD_ULOGIC_VECTOR'("0000110")); +MQQ20:LRU_UPDATE_DATA_PT(20) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(6) & LRU_TAG4_DATAOUT_Q(11) + ) , STD_ULOGIC_VECTOR'("100110")); +MQQ21:LRU_UPDATE_DATA_PT(21) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(3) & LRU_TAG4_DATAOUT_Q(4) & + LRU_TAG4_DATAOUT_Q(5) & LRU_TAG4_DATAOUT_Q(11) + ) , STD_ULOGIC_VECTOR'("1111111000")); +MQQ22:LRU_UPDATE_DATA_PT(22) <= + Eq(( TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(3) & LRU_TAG4_DATAOUT_Q(4) & + LRU_TAG4_DATAOUT_Q(5) & LRU_TAG4_DATAOUT_Q(11) + ) , STD_ULOGIC_VECTOR'("11111000")); +MQQ23:LRU_UPDATE_DATA_PT(23) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(11) ) , STD_ULOGIC_VECTOR'("1111100")); +MQQ24:LRU_UPDATE_DATA_PT(24) <= + Eq(( TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(11) ) , STD_ULOGIC_VECTOR'("11100")); +MQQ25:LRU_UPDATE_DATA_PT(25) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_WAYHIT_Q(0) & + TLB_TAG4_WAYHIT_Q(1) & TLB_TAG4_WAYHIT_Q(2) & + TLB_TAG4_WAYHIT_Q(3) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(11) ) , STD_ULOGIC_VECTOR'("100011110")); +MQQ26:LRU_UPDATE_DATA_PT(26) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & TLB_TAG4_ESEL_SIG(2) & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(11) + ) , STD_ULOGIC_VECTOR'("10101110")); +MQQ27:LRU_UPDATE_DATA_PT(27) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_WAYHIT_Q(1) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(3) & LRU_TAG4_DATAOUT_Q(8) & + LRU_TAG4_DATAOUT_Q(9) & LRU_TAG4_DATAOUT_Q(10) & + LRU_TAG4_DATAOUT_Q(11) ) , STD_ULOGIC_VECTOR'("011111011")); +MQQ28:LRU_UPDATE_DATA_PT(28) <= + Eq(( TLB_TAG4_HES_SIG & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(5) & LRU_TAG4_DATAOUT_Q(8) & + LRU_TAG4_DATAOUT_Q(10) & LRU_TAG4_DATAOUT_Q(11) + ) , STD_ULOGIC_VECTOR'("111111")); +MQQ29:LRU_UPDATE_DATA_PT(29) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(5) & LRU_TAG4_DATAOUT_Q(8) & + LRU_TAG4_DATAOUT_Q(10) & LRU_TAG4_DATAOUT_Q(11) + ) , STD_ULOGIC_VECTOR'("011111")); +MQQ30:LRU_UPDATE_DATA_PT(30) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & TLB_TAG4_ESEL_SIG(2) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(3) & LRU_TAG4_DATAOUT_Q(8) & + LRU_TAG4_DATAOUT_Q(10) & LRU_TAG4_DATAOUT_Q(11) + ) , STD_ULOGIC_VECTOR'("1001111111")); +MQQ31:LRU_UPDATE_DATA_PT(31) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_WAYHIT_Q(2) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(8) & LRU_TAG4_DATAOUT_Q(9) & + LRU_TAG4_DATAOUT_Q(10) ) , STD_ULOGIC_VECTOR'("0111110")); +MQQ32:LRU_UPDATE_DATA_PT(32) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_WAYHIT_Q(0) & + TLB_TAG4_WAYHIT_Q(2) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(9) & + LRU_TAG4_DATAOUT_Q(10) ) , STD_ULOGIC_VECTOR'("1011110")); +MQQ33:LRU_UPDATE_DATA_PT(33) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(3) & LRU_TAG4_DATAOUT_Q(4) & + LRU_TAG4_DATAOUT_Q(5) & LRU_TAG4_DATAOUT_Q(10) + ) , STD_ULOGIC_VECTOR'("1111111000")); +MQQ34:LRU_UPDATE_DATA_PT(34) <= + Eq(( TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(3) & LRU_TAG4_DATAOUT_Q(4) & + LRU_TAG4_DATAOUT_Q(5) & LRU_TAG4_DATAOUT_Q(10) + ) , STD_ULOGIC_VECTOR'("11111000")); +MQQ35:LRU_UPDATE_DATA_PT(35) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(3) & + LRU_TAG4_DATAOUT_Q(4) & LRU_TAG4_DATAOUT_Q(10) + ) , STD_ULOGIC_VECTOR'("11111100")); +MQQ36:LRU_UPDATE_DATA_PT(36) <= + Eq(( TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(3) & + LRU_TAG4_DATAOUT_Q(4) & LRU_TAG4_DATAOUT_Q(10) + ) , STD_ULOGIC_VECTOR'("111100")); +MQQ37:LRU_UPDATE_DATA_PT(37) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_TYPE_SIG(6) & + TLB_TAG4_TYPE_SIG(7) & TLB_TAG4_WAYHIT_Q(0) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(3) & + LRU_TAG4_DATAOUT_Q(10) ) , STD_ULOGIC_VECTOR'("000111110")); +MQQ38:LRU_UPDATE_DATA_PT(38) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & TLB_TAG4_ESEL_SIG(2) & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(3) & + LRU_TAG4_DATAOUT_Q(10) ) , STD_ULOGIC_VECTOR'("100011110")); +MQQ39:LRU_UPDATE_DATA_PT(39) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(10) + ) , STD_ULOGIC_VECTOR'("111100")); +MQQ40:LRU_UPDATE_DATA_PT(40) <= + Eq(( TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(10) + ) , STD_ULOGIC_VECTOR'("1100")); +MQQ41:LRU_UPDATE_DATA_PT(41) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(10) + ) , STD_ULOGIC_VECTOR'("111010")); +MQQ42:LRU_UPDATE_DATA_PT(42) <= + Eq(( TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(10) + ) , STD_ULOGIC_VECTOR'("1010")); +MQQ43:LRU_UPDATE_DATA_PT(43) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_WAYHIT_Q(0) & + TLB_TAG4_WAYHIT_Q(1) & TLB_TAG4_WAYHIT_Q(2) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(10) ) , STD_ULOGIC_VECTOR'("1001110")); +MQQ44:LRU_UPDATE_DATA_PT(44) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_TYPE_SIG(6) & + TLB_TAG4_TYPE_SIG(7) & TLB_TAG4_WAYHIT_Q(1) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(10) ) , STD_ULOGIC_VECTOR'("0001110")); +MQQ45:LRU_UPDATE_DATA_PT(45) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & TLB_TAG4_ESEL_SIG(2) & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(10) ) , STD_ULOGIC_VECTOR'("1001110")); +MQQ46:LRU_UPDATE_DATA_PT(46) <= + Eq(( TLB_TAG4_HES_SIG & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(6) & LRU_TAG4_DATAOUT_Q(8) & + LRU_TAG4_DATAOUT_Q(9) & LRU_TAG4_DATAOUT_Q(10) + ) , STD_ULOGIC_VECTOR'("111111")); +MQQ47:LRU_UPDATE_DATA_PT(47) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(6) & LRU_TAG4_DATAOUT_Q(8) & + LRU_TAG4_DATAOUT_Q(9) & LRU_TAG4_DATAOUT_Q(10) + ) , STD_ULOGIC_VECTOR'("011111")); +MQQ48:LRU_UPDATE_DATA_PT(48) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & TLB_TAG4_ESEL_SIG(2) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(8) & + LRU_TAG4_DATAOUT_Q(9) & LRU_TAG4_DATAOUT_Q(10) + ) , STD_ULOGIC_VECTOR'("1011111111")); +MQQ49:LRU_UPDATE_DATA_PT(49) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(4) & + LRU_TAG4_DATAOUT_Q(6) & LRU_TAG4_DATAOUT_Q(10) + ) , STD_ULOGIC_VECTOR'("111011")); +MQQ50:LRU_UPDATE_DATA_PT(50) <= + Eq(( TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(4) & LRU_TAG4_DATAOUT_Q(6) & + LRU_TAG4_DATAOUT_Q(10) ) , STD_ULOGIC_VECTOR'("11011")); +MQQ51:LRU_UPDATE_DATA_PT(51) <= + Eq(( LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(6) & LRU_TAG4_DATAOUT_Q(10) + ) , STD_ULOGIC_VECTOR'("0111")); +MQQ52:LRU_UPDATE_DATA_PT(52) <= + Eq(( LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(6) & LRU_TAG4_DATAOUT_Q(10) + ) , STD_ULOGIC_VECTOR'("0111")); +MQQ53:LRU_UPDATE_DATA_PT(53) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_TYPE_SIG(7) & + TLB_TAG4_WAYHIT_Q(3) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(6) & LRU_TAG4_DATAOUT_Q(10) + ) , STD_ULOGIC_VECTOR'("000111")); +MQQ54:LRU_UPDATE_DATA_PT(54) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_TYPE_SIG(7) & + TLB_TAG4_WAYHIT_Q(2) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(6) & LRU_TAG4_DATAOUT_Q(10) + ) , STD_ULOGIC_VECTOR'("001111")); +MQQ55:LRU_UPDATE_DATA_PT(55) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(6) & LRU_TAG4_DATAOUT_Q(10) + ) , STD_ULOGIC_VECTOR'("100111")); +MQQ56:LRU_UPDATE_DATA_PT(56) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_WAYHIT_Q(0) & + TLB_TAG4_WAYHIT_Q(1) & TLB_TAG4_WAYHIT_Q(2) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(3) & + LRU_TAG4_DATAOUT_Q(10) ) , STD_ULOGIC_VECTOR'("100111101")); +MQQ57:LRU_UPDATE_DATA_PT(57) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(3) & + LRU_TAG4_DATAOUT_Q(10) ) , STD_ULOGIC_VECTOR'("1111101")); +MQQ58:LRU_UPDATE_DATA_PT(58) <= + Eq(( TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(3) & + LRU_TAG4_DATAOUT_Q(10) ) , STD_ULOGIC_VECTOR'("11101")); +MQQ59:LRU_UPDATE_DATA_PT(59) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(4) & LRU_TAG4_DATAOUT_Q(8) & + LRU_TAG4_DATAOUT_Q(9) ) , STD_ULOGIC_VECTOR'("1111110")); +MQQ60:LRU_UPDATE_DATA_PT(60) <= + Eq(( TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(4) & LRU_TAG4_DATAOUT_Q(8) & + LRU_TAG4_DATAOUT_Q(9) ) , STD_ULOGIC_VECTOR'("11110")); +MQQ61:LRU_UPDATE_DATA_PT(61) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_TYPE_SIG(6) & + TLB_TAG4_TYPE_SIG(7) & TLB_TAG4_WAYHIT_Q(2) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(3) & + LRU_TAG4_DATAOUT_Q(8) & LRU_TAG4_DATAOUT_Q(9) + ) , STD_ULOGIC_VECTOR'("0001111110")); +MQQ62:LRU_UPDATE_DATA_PT(62) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_TYPE_SIG(6) & + TLB_TAG4_TYPE_SIG(7) & TLB_TAG4_WAYHIT_Q(3) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(3) & LRU_TAG4_DATAOUT_Q(8) & + LRU_TAG4_DATAOUT_Q(9) ) , STD_ULOGIC_VECTOR'("000111110")); +MQQ63:LRU_UPDATE_DATA_PT(63) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_WAYHIT_Q(1) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(3) & LRU_TAG4_DATAOUT_Q(8) & + LRU_TAG4_DATAOUT_Q(9) ) , STD_ULOGIC_VECTOR'("1111110")); +MQQ64:LRU_UPDATE_DATA_PT(64) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & TLB_TAG4_ESEL_SIG(2) & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(3) & + LRU_TAG4_DATAOUT_Q(8) & LRU_TAG4_DATAOUT_Q(9) + ) , STD_ULOGIC_VECTOR'("1010111110")); +MQQ65:LRU_UPDATE_DATA_PT(65) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & TLB_TAG4_ESEL_SIG(2) & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(8) & + LRU_TAG4_DATAOUT_Q(9) ) , STD_ULOGIC_VECTOR'("101111110")); +MQQ66:LRU_UPDATE_DATA_PT(66) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(3) & LRU_TAG4_DATAOUT_Q(4) & + LRU_TAG4_DATAOUT_Q(6) & LRU_TAG4_DATAOUT_Q(9) + ) , STD_ULOGIC_VECTOR'("1111111100")); +MQQ67:LRU_UPDATE_DATA_PT(67) <= + Eq(( TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(3) & LRU_TAG4_DATAOUT_Q(4) & + LRU_TAG4_DATAOUT_Q(6) & LRU_TAG4_DATAOUT_Q(9) + ) , STD_ULOGIC_VECTOR'("11111100")); +MQQ68:LRU_UPDATE_DATA_PT(68) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_TYPE_SIG(7) & + TLB_TAG4_WAYHIT_Q(0) & TLB_TAG4_WAYHIT_Q(1) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(6) & + LRU_TAG4_DATAOUT_Q(9) ) , STD_ULOGIC_VECTOR'("0011110")); +MQQ69:LRU_UPDATE_DATA_PT(69) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_WAYHIT_Q(0) & + TLB_TAG4_WAYHIT_Q(1) & LRU_TAG4_DATAOUT_Q(6) & + LRU_TAG4_DATAOUT_Q(9) ) , STD_ULOGIC_VECTOR'("10110")); +MQQ70:LRU_UPDATE_DATA_PT(70) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(3) & + LRU_TAG4_DATAOUT_Q(4) & LRU_TAG4_DATAOUT_Q(5) & + LRU_TAG4_DATAOUT_Q(9) ) , STD_ULOGIC_VECTOR'("111111000")); +MQQ71:LRU_UPDATE_DATA_PT(71) <= + Eq(( TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(3) & + LRU_TAG4_DATAOUT_Q(4) & LRU_TAG4_DATAOUT_Q(5) & + LRU_TAG4_DATAOUT_Q(9) ) , STD_ULOGIC_VECTOR'("1111000")); +MQQ72:LRU_UPDATE_DATA_PT(72) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(4) & LRU_TAG4_DATAOUT_Q(5) & + LRU_TAG4_DATAOUT_Q(9) ) , STD_ULOGIC_VECTOR'("1111110")); +MQQ73:LRU_UPDATE_DATA_PT(73) <= + Eq(( TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(4) & LRU_TAG4_DATAOUT_Q(5) & + LRU_TAG4_DATAOUT_Q(9) ) , STD_ULOGIC_VECTOR'("11110")); +MQQ74:LRU_UPDATE_DATA_PT(74) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_IS_SIG(0) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(3) & LRU_TAG4_DATAOUT_Q(5) & + LRU_TAG4_DATAOUT_Q(9) ) , STD_ULOGIC_VECTOR'("0111010")); +MQQ75:LRU_UPDATE_DATA_PT(75) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_TYPE_SIG(6) & + TLB_TAG4_TYPE_SIG(7) & TLB_TAG4_WAYHIT_Q(1) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(5) & + LRU_TAG4_DATAOUT_Q(9) ) , STD_ULOGIC_VECTOR'("0000110")); +MQQ76:LRU_UPDATE_DATA_PT(76) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(5) & LRU_TAG4_DATAOUT_Q(9) + ) , STD_ULOGIC_VECTOR'("101110")); +MQQ77:LRU_UPDATE_DATA_PT(77) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_TYPE_SIG(6) & + TLB_TAG4_TYPE_SIG(7) & TLB_TAG4_WAYHIT_Q(0) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(3) & LRU_TAG4_DATAOUT_Q(9) + ) , STD_ULOGIC_VECTOR'("00011110")); +MQQ78:LRU_UPDATE_DATA_PT(78) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & TLB_TAG4_ESEL_SIG(2) & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(3) & LRU_TAG4_DATAOUT_Q(9) + ) , STD_ULOGIC_VECTOR'("10001110")); +MQQ79:LRU_UPDATE_DATA_PT(79) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(9) ) , STD_ULOGIC_VECTOR'("11100")); +MQQ80:LRU_UPDATE_DATA_PT(80) <= + Eq(( TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(9) ) , STD_ULOGIC_VECTOR'("100")); +MQQ81:LRU_UPDATE_DATA_PT(81) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_WAYHIT_Q(0) & + TLB_TAG4_WAYHIT_Q(1) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(9) ) , STD_ULOGIC_VECTOR'("10110")); +MQQ82:LRU_UPDATE_DATA_PT(82) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_IS_SIG(0) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(3) & LRU_TAG4_DATAOUT_Q(5) & + LRU_TAG4_DATAOUT_Q(8) & LRU_TAG4_DATAOUT_Q(9) + ) , STD_ULOGIC_VECTOR'("01110111")); +MQQ83:LRU_UPDATE_DATA_PT(83) <= + Eq(( TLB_TAG4_HES_SIG & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(4) & + LRU_TAG4_DATAOUT_Q(8) & LRU_TAG4_DATAOUT_Q(9) + ) , STD_ULOGIC_VECTOR'("111111")); +MQQ84:LRU_UPDATE_DATA_PT(84) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(4) & + LRU_TAG4_DATAOUT_Q(8) & LRU_TAG4_DATAOUT_Q(9) + ) , STD_ULOGIC_VECTOR'("011111")); +MQQ85:LRU_UPDATE_DATA_PT(85) <= + Eq(( TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(3) & LRU_TAG4_DATAOUT_Q(8) & + LRU_TAG4_DATAOUT_Q(9) ) , STD_ULOGIC_VECTOR'("11011")); +MQQ86:LRU_UPDATE_DATA_PT(86) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(8) & + LRU_TAG4_DATAOUT_Q(9) ) , STD_ULOGIC_VECTOR'("1111011")); +MQQ87:LRU_UPDATE_DATA_PT(87) <= + Eq(( TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(8) & + LRU_TAG4_DATAOUT_Q(9) ) , STD_ULOGIC_VECTOR'("11011")); +MQQ88:LRU_UPDATE_DATA_PT(88) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_TYPE_SIG(6) & + TLB_TAG4_TYPE_SIG(7) & TLB_TAG4_WAYHIT_Q(3) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(8) & LRU_TAG4_DATAOUT_Q(9) + ) , STD_ULOGIC_VECTOR'("00011111")); +MQQ89:LRU_UPDATE_DATA_PT(89) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(8) & + LRU_TAG4_DATAOUT_Q(9) ) , STD_ULOGIC_VECTOR'("1011111")); +MQQ90:LRU_UPDATE_DATA_PT(90) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_WAYHIT_Q(0) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(4) & LRU_TAG4_DATAOUT_Q(9) + ) , STD_ULOGIC_VECTOR'("101111")); +MQQ91:LRU_UPDATE_DATA_PT(91) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_WAYHIT_Q(0) & + TLB_TAG4_WAYHIT_Q(1) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(3) & LRU_TAG4_DATAOUT_Q(9) + ) , STD_ULOGIC_VECTOR'("10111101")); +MQQ92:LRU_UPDATE_DATA_PT(92) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_WAYHIT_Q(0) & + TLB_TAG4_WAYHIT_Q(1) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(9) ) , STD_ULOGIC_VECTOR'("1011101")); +MQQ93:LRU_UPDATE_DATA_PT(93) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(3) & LRU_TAG4_DATAOUT_Q(4) & + LRU_TAG4_DATAOUT_Q(6) & LRU_TAG4_DATAOUT_Q(8) + ) , STD_ULOGIC_VECTOR'("1111111100")); +MQQ94:LRU_UPDATE_DATA_PT(94) <= + Eq(( TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(3) & LRU_TAG4_DATAOUT_Q(4) & + LRU_TAG4_DATAOUT_Q(6) & LRU_TAG4_DATAOUT_Q(8) + ) , STD_ULOGIC_VECTOR'("11111100")); +MQQ95:LRU_UPDATE_DATA_PT(95) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_WAYHIT_Q(0) & + LRU_TAG4_DATAOUT_Q(6) & LRU_TAG4_DATAOUT_Q(8) + ) , STD_ULOGIC_VECTOR'("1110")); +MQQ96:LRU_UPDATE_DATA_PT(96) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_TYPE_SIG(6) & + TLB_TAG4_TYPE_SIG(7) & TLB_TAG4_WAYHIT_Q(2) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(8) + ) , STD_ULOGIC_VECTOR'("00011110")); +MQQ97:LRU_UPDATE_DATA_PT(97) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & TLB_TAG4_ESEL_SIG(2) & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(8) + ) , STD_ULOGIC_VECTOR'("10101110")); +MQQ98:LRU_UPDATE_DATA_PT(98) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(3) & LRU_TAG4_DATAOUT_Q(5) & + LRU_TAG4_DATAOUT_Q(8) ) , STD_ULOGIC_VECTOR'("1111001")); +MQQ99:LRU_UPDATE_DATA_PT(99) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(4) & + LRU_TAG4_DATAOUT_Q(5) & LRU_TAG4_DATAOUT_Q(8) + ) , STD_ULOGIC_VECTOR'("111111")); +MQQ100:LRU_UPDATE_DATA_PT(100) <= + Eq(( TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(4) & LRU_TAG4_DATAOUT_Q(5) & + LRU_TAG4_DATAOUT_Q(8) ) , STD_ULOGIC_VECTOR'("11111")); +MQQ101:LRU_UPDATE_DATA_PT(101) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_TYPE_SIG(7) & + TLB_TAG4_WAYHIT_Q(1) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(5) & LRU_TAG4_DATAOUT_Q(8) + ) , STD_ULOGIC_VECTOR'("000111")); +MQQ102:LRU_UPDATE_DATA_PT(102) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(5) & LRU_TAG4_DATAOUT_Q(8) + ) , STD_ULOGIC_VECTOR'("101111")); +MQQ103:LRU_UPDATE_DATA_PT(103) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(5) & LRU_TAG4_DATAOUT_Q(8) + ) , STD_ULOGIC_VECTOR'("1111")); +MQQ104:LRU_UPDATE_DATA_PT(104) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_WAYHIT_Q(1) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(4) & LRU_TAG4_DATAOUT_Q(8) + ) , STD_ULOGIC_VECTOR'("101111")); +MQQ105:LRU_UPDATE_DATA_PT(105) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_WAYHIT_Q(0) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(3) & + LRU_TAG4_DATAOUT_Q(8) ) , STD_ULOGIC_VECTOR'("1111101")); +MQQ106:LRU_UPDATE_DATA_PT(106) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_WAYHIT_Q(0) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(8) + ) , STD_ULOGIC_VECTOR'("111101")); +MQQ107:LRU_UPDATE_DATA_PT(107) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_WAYHIT_Q(0) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(8) ) , STD_ULOGIC_VECTOR'("11101")); +MQQ108:LRU_UPDATE_DATA_PT(108) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(8) ) , STD_ULOGIC_VECTOR'("11101")); +MQQ109:LRU_UPDATE_DATA_PT(109) <= + Eq(( TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(8) ) , STD_ULOGIC_VECTOR'("101")); +MQQ110:LRU_UPDATE_DATA_PT(110) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(4) & + LRU_TAG4_DATAOUT_Q(6) ) , STD_ULOGIC_VECTOR'("11001")); +MQQ111:LRU_UPDATE_DATA_PT(111) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_TYPE_SIG(7) & + TLB_TAG4_WAYHIT_Q(0) & TLB_TAG4_WAYHIT_Q(1) & + TLB_TAG4_WAYHIT_Q(2) & TLB_TAG4_WAYHIT_Q(3) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(6) + ) , STD_ULOGIC_VECTOR'("00000011")); +MQQ112:LRU_UPDATE_DATA_PT(112) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_WAYHIT_Q(2) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(6) + ) , STD_ULOGIC_VECTOR'("1011")); +MQQ113:LRU_UPDATE_DATA_PT(113) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(6) ) , STD_ULOGIC_VECTOR'("11011")); +MQQ114:LRU_UPDATE_DATA_PT(114) <= + Eq(( LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(6) ) , STD_ULOGIC_VECTOR'("001")); +MQQ115:LRU_UPDATE_DATA_PT(115) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_IS_SIG(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(6) + ) , STD_ULOGIC_VECTOR'("1001")); +MQQ116:LRU_UPDATE_DATA_PT(116) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(2) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(6) ) , STD_ULOGIC_VECTOR'("10001")); +MQQ117:LRU_UPDATE_DATA_PT(117) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(6) ) , STD_ULOGIC_VECTOR'("10101")); +MQQ118:LRU_UPDATE_DATA_PT(118) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_TYPE_SIG(7) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(6) + ) , STD_ULOGIC_VECTOR'("0001")); +MQQ119:LRU_UPDATE_DATA_PT(119) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_IS_SIG(0) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(6) + ) , STD_ULOGIC_VECTOR'("1001")); +MQQ120:LRU_UPDATE_DATA_PT(120) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(2) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(6) ) , STD_ULOGIC_VECTOR'("10101")); +MQQ121:LRU_UPDATE_DATA_PT(121) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(6) ) , STD_ULOGIC_VECTOR'("10101")); +MQQ122:LRU_UPDATE_DATA_PT(122) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_TYPE_SIG(7) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(6) + ) , STD_ULOGIC_VECTOR'("0001")); +MQQ123:LRU_UPDATE_DATA_PT(123) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_WAYHIT_Q(0) & + TLB_TAG4_WAYHIT_Q(1) & TLB_TAG4_WAYHIT_Q(2) & + TLB_TAG4_WAYHIT_Q(3) & LRU_TAG4_DATAOUT_Q(6) + ) , STD_ULOGIC_VECTOR'("100001")); +MQQ124:LRU_UPDATE_DATA_PT(124) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & TLB_TAG4_IS_SIG(0) & + LRU_TAG4_DATAOUT_Q(6) ) , STD_ULOGIC_VECTOR'("10001")); +MQQ125:LRU_UPDATE_DATA_PT(125) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_ESEL_SIG(2) & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(3) & + LRU_TAG4_DATAOUT_Q(5) ) , STD_ULOGIC_VECTOR'("0011101")); +MQQ126:LRU_UPDATE_DATA_PT(126) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_ESEL_SIG(1) & + TLB_TAG4_ESEL_SIG(2) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(3) & + LRU_TAG4_DATAOUT_Q(5) ) , STD_ULOGIC_VECTOR'("0011101")); +MQQ127:LRU_UPDATE_DATA_PT(127) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_TYPE_SIG(6) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(3) & LRU_TAG4_DATAOUT_Q(5) + ) , STD_ULOGIC_VECTOR'("001101")); +MQQ128:LRU_UPDATE_DATA_PT(128) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_ESEL_SIG(2) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(5) + ) , STD_ULOGIC_VECTOR'("011101")); +MQQ129:LRU_UPDATE_DATA_PT(129) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_HES_SIG & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(5) + ) , STD_ULOGIC_VECTOR'("011101")); +MQQ130:LRU_UPDATE_DATA_PT(130) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_TYPE_SIG(6) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(5) + ) , STD_ULOGIC_VECTOR'("001101")); +MQQ131:LRU_UPDATE_DATA_PT(131) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & TLB_TAG4_ESEL_SIG(2) & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(5) ) , STD_ULOGIC_VECTOR'("1000101")); +MQQ132:LRU_UPDATE_DATA_PT(132) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_TYPE_SIG(7) & + TLB_TAG4_WAYHIT_Q(0) & TLB_TAG4_WAYHIT_Q(1) & + TLB_TAG4_WAYHIT_Q(2) & TLB_TAG4_WAYHIT_Q(3) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(5) + ) , STD_ULOGIC_VECTOR'("00000011")); +MQQ133:LRU_UPDATE_DATA_PT(133) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_WAYHIT_Q(0) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(5) + ) , STD_ULOGIC_VECTOR'("1011")); +MQQ134:LRU_UPDATE_DATA_PT(134) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_ESEL_SIG(1) & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(5) ) , STD_ULOGIC_VECTOR'("11011")); +MQQ135:LRU_UPDATE_DATA_PT(135) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(5) ) , STD_ULOGIC_VECTOR'("11011")); +MQQ136:LRU_UPDATE_DATA_PT(136) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_WAYHIT_Q(0) & + TLB_TAG4_WAYHIT_Q(1) & TLB_TAG4_WAYHIT_Q(2) & + TLB_TAG4_WAYHIT_Q(3) & LRU_TAG4_DATAOUT_Q(5) + ) , STD_ULOGIC_VECTOR'("100001")); +MQQ137:LRU_UPDATE_DATA_PT(137) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(4) + ) , STD_ULOGIC_VECTOR'("110101")); +MQQ138:LRU_UPDATE_DATA_PT(138) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_TYPE_SIG(7) & + TLB_TAG4_WAYHIT_Q(0) & TLB_TAG4_WAYHIT_Q(1) & + TLB_TAG4_WAYHIT_Q(2) & TLB_TAG4_WAYHIT_Q(3) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(4) ) , STD_ULOGIC_VECTOR'("000000111")); +MQQ139:LRU_UPDATE_DATA_PT(139) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_WAYHIT_Q(0) & + TLB_TAG4_WAYHIT_Q(1) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(4) + ) , STD_ULOGIC_VECTOR'("100111")); +MQQ140:LRU_UPDATE_DATA_PT(140) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(4) + ) , STD_ULOGIC_VECTOR'("110111")); +MQQ141:LRU_UPDATE_DATA_PT(141) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_WAYHIT_Q(0) & + TLB_TAG4_WAYHIT_Q(1) & TLB_TAG4_WAYHIT_Q(2) & + TLB_TAG4_WAYHIT_Q(3) & LRU_TAG4_DATAOUT_Q(4) + ) , STD_ULOGIC_VECTOR'("100001")); +MQQ142:LRU_UPDATE_DATA_PT(142) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(3) ) , STD_ULOGIC_VECTOR'("1111100")); +MQQ143:LRU_UPDATE_DATA_PT(143) <= + Eq(( TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(3) ) , STD_ULOGIC_VECTOR'("11100")); +MQQ144:LRU_UPDATE_DATA_PT(144) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(3) ) , STD_ULOGIC_VECTOR'("1111010")); +MQQ145:LRU_UPDATE_DATA_PT(145) <= + Eq(( TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(3) ) , STD_ULOGIC_VECTOR'("11010")); +MQQ146:LRU_UPDATE_DATA_PT(146) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(3) ) , STD_ULOGIC_VECTOR'("1110110")); +MQQ147:LRU_UPDATE_DATA_PT(147) <= + Eq(( TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(3) ) , STD_ULOGIC_VECTOR'("10110")); +MQQ148:LRU_UPDATE_DATA_PT(148) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_WAYHIT_Q(0) & + TLB_TAG4_WAYHIT_Q(1) & TLB_TAG4_WAYHIT_Q(2) & + TLB_TAG4_WAYHIT_Q(3) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(3) ) , STD_ULOGIC_VECTOR'("100011110")); +MQQ149:LRU_UPDATE_DATA_PT(149) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_TYPE_SIG(6) & + TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) & + LRU_TAG4_DATAOUT_Q(3) ) , STD_ULOGIC_VECTOR'("0001110")); +MQQ150:LRU_UPDATE_DATA_PT(150) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & TLB_TAG4_ESEL_SIG(2) & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(3) + ) , STD_ULOGIC_VECTOR'("10001110")); +MQQ151:LRU_UPDATE_DATA_PT(151) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & TLB_TAG4_ESEL_SIG(2) & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(2) & LRU_TAG4_DATAOUT_Q(3) + ) , STD_ULOGIC_VECTOR'("10011110")); +MQQ152:LRU_UPDATE_DATA_PT(152) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & TLB_TAG4_ESEL_SIG(2) & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(3) + ) , STD_ULOGIC_VECTOR'("10101110")); +MQQ153:LRU_UPDATE_DATA_PT(153) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & TLB_TAG4_ESEL_SIG(2) & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(3) ) , STD_ULOGIC_VECTOR'("1000100")); +MQQ154:LRU_UPDATE_DATA_PT(154) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) + ) , STD_ULOGIC_VECTOR'("111100")); +MQQ155:LRU_UPDATE_DATA_PT(155) <= + Eq(( TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) + ) , STD_ULOGIC_VECTOR'("1100")); +MQQ156:LRU_UPDATE_DATA_PT(156) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) + ) , STD_ULOGIC_VECTOR'("111010")); +MQQ157:LRU_UPDATE_DATA_PT(157) <= + Eq(( TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) + ) , STD_ULOGIC_VECTOR'("1010")); +MQQ158:LRU_UPDATE_DATA_PT(158) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_WAYHIT_Q(0) & + TLB_TAG4_WAYHIT_Q(1) & TLB_TAG4_WAYHIT_Q(3) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(2) ) , STD_ULOGIC_VECTOR'("1001110")); +MQQ159:LRU_UPDATE_DATA_PT(159) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_WAYHIT_Q(0) & + TLB_TAG4_WAYHIT_Q(1) & TLB_TAG4_WAYHIT_Q(2) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(2) ) , STD_ULOGIC_VECTOR'("1001110")); +MQQ160:LRU_UPDATE_DATA_PT(160) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & TLB_TAG4_ESEL_SIG(2) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(2) ) , STD_ULOGIC_VECTOR'("1011110")); +MQQ161:LRU_UPDATE_DATA_PT(161) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_TYPE_SIG(6) & + TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) + ) , STD_ULOGIC_VECTOR'("000110")); +MQQ162:LRU_UPDATE_DATA_PT(162) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & TLB_TAG4_ESEL_SIG(2) & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(1) & + LRU_TAG4_DATAOUT_Q(2) ) , STD_ULOGIC_VECTOR'("1000110")); +MQQ163:LRU_UPDATE_DATA_PT(163) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & TLB_TAG4_ESEL_SIG(2) & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(2) ) , STD_ULOGIC_VECTOR'("1000100")); +MQQ164:LRU_UPDATE_DATA_PT(164) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & TLB_TAG4_ESEL_SIG(2) & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(2) ) , STD_ULOGIC_VECTOR'("1001110")); +MQQ165:LRU_UPDATE_DATA_PT(165) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & TLB_TAG4_ESEL_SIG(2) & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) & LRU_TAG4_DATAOUT_Q(2) + ) , STD_ULOGIC_VECTOR'("10110111")); +MQQ166:LRU_UPDATE_DATA_PT(166) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) ) , STD_ULOGIC_VECTOR'("11100")); +MQQ167:LRU_UPDATE_DATA_PT(167) <= + Eq(( TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) ) , STD_ULOGIC_VECTOR'("100")); +MQQ168:LRU_UPDATE_DATA_PT(168) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_WAYHIT_Q(0) & + TLB_TAG4_WAYHIT_Q(3) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) ) , STD_ULOGIC_VECTOR'("10110")); +MQQ169:LRU_UPDATE_DATA_PT(169) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_WAYHIT_Q(0) & + TLB_TAG4_WAYHIT_Q(2) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) ) , STD_ULOGIC_VECTOR'("10110")); +MQQ170:LRU_UPDATE_DATA_PT(170) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_WAYHIT_Q(0) & + TLB_TAG4_WAYHIT_Q(1) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) ) , STD_ULOGIC_VECTOR'("10110")); +MQQ171:LRU_UPDATE_DATA_PT(171) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) ) , STD_ULOGIC_VECTOR'("10110")); +MQQ172:LRU_UPDATE_DATA_PT(172) <= + Eq(( TLB_TAG4_TYPE_SIG(4) & TLB_TAG4_TYPE_SIG(6) & + TLB_TAG4_TYPE_SIG(7) & LRU_TAG4_DATAOUT_Q(0) & + LRU_TAG4_DATAOUT_Q(1) ) , STD_ULOGIC_VECTOR'("00010")); +MQQ173:LRU_UPDATE_DATA_PT(173) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & TLB_TAG4_ESEL_SIG(2) & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(1) + ) , STD_ULOGIC_VECTOR'("100010")); +MQQ174:LRU_UPDATE_DATA_PT(174) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & TLB_TAG4_IS_SIG(0) & + LRU_TAG4_DATAOUT_Q(0) & LRU_TAG4_DATAOUT_Q(1) + ) , STD_ULOGIC_VECTOR'("101011")); +MQQ175:LRU_UPDATE_DATA_PT(175) <= + Eq(( TLB_TAG4_TYPE_SIG(6) & TLB_TAG4_HES_SIG & + TLB_TAG4_ESEL_SIG(1) & TLB_TAG4_ESEL_SIG(2) & + TLB_TAG4_IS_SIG(0) & LRU_TAG4_DATAOUT_Q(0) + ) , STD_ULOGIC_VECTOR'("100101")); +-- Table LRU_UPDATE_DATA Signal Assignments for Outputs +MQQ176:LRU_UPDATE_DATA(0) <= + (LRU_UPDATE_DATA_PT(1) OR LRU_UPDATE_DATA_PT(2) + OR LRU_UPDATE_DATA_PT(3) OR LRU_UPDATE_DATA_PT(4) + OR LRU_UPDATE_DATA_PT(5) OR LRU_UPDATE_DATA_PT(6) + OR LRU_UPDATE_DATA_PT(7) OR LRU_UPDATE_DATA_PT(8) + OR LRU_UPDATE_DATA_PT(9) OR LRU_UPDATE_DATA_PT(10) + OR LRU_UPDATE_DATA_PT(15) OR LRU_UPDATE_DATA_PT(16) + OR LRU_UPDATE_DATA_PT(17) OR LRU_UPDATE_DATA_PT(18) + OR LRU_UPDATE_DATA_PT(25) OR LRU_UPDATE_DATA_PT(31) + OR LRU_UPDATE_DATA_PT(32) OR LRU_UPDATE_DATA_PT(35) + OR LRU_UPDATE_DATA_PT(36) OR LRU_UPDATE_DATA_PT(37) + OR LRU_UPDATE_DATA_PT(38) OR LRU_UPDATE_DATA_PT(39) + OR LRU_UPDATE_DATA_PT(40) OR LRU_UPDATE_DATA_PT(41) + OR LRU_UPDATE_DATA_PT(42) OR LRU_UPDATE_DATA_PT(43) + OR LRU_UPDATE_DATA_PT(44) OR LRU_UPDATE_DATA_PT(45) + OR LRU_UPDATE_DATA_PT(56) OR LRU_UPDATE_DATA_PT(82) + OR LRU_UPDATE_DATA_PT(83) OR LRU_UPDATE_DATA_PT(84) + OR LRU_UPDATE_DATA_PT(85) OR LRU_UPDATE_DATA_PT(86) + OR LRU_UPDATE_DATA_PT(87) OR LRU_UPDATE_DATA_PT(88) + OR LRU_UPDATE_DATA_PT(89) OR LRU_UPDATE_DATA_PT(90) + OR LRU_UPDATE_DATA_PT(91) OR LRU_UPDATE_DATA_PT(92) + OR LRU_UPDATE_DATA_PT(98) OR LRU_UPDATE_DATA_PT(104) + OR LRU_UPDATE_DATA_PT(105) OR LRU_UPDATE_DATA_PT(106) + OR LRU_UPDATE_DATA_PT(138) OR LRU_UPDATE_DATA_PT(139) + OR LRU_UPDATE_DATA_PT(140) OR LRU_UPDATE_DATA_PT(141) + OR LRU_UPDATE_DATA_PT(142) OR LRU_UPDATE_DATA_PT(143) + OR LRU_UPDATE_DATA_PT(144) OR LRU_UPDATE_DATA_PT(145) + OR LRU_UPDATE_DATA_PT(146) OR LRU_UPDATE_DATA_PT(147) + OR LRU_UPDATE_DATA_PT(148) OR LRU_UPDATE_DATA_PT(149) + OR LRU_UPDATE_DATA_PT(150) OR LRU_UPDATE_DATA_PT(151) + OR LRU_UPDATE_DATA_PT(152) OR LRU_UPDATE_DATA_PT(154) + OR LRU_UPDATE_DATA_PT(155) OR LRU_UPDATE_DATA_PT(156) + OR LRU_UPDATE_DATA_PT(157) OR LRU_UPDATE_DATA_PT(158) + OR LRU_UPDATE_DATA_PT(159) OR LRU_UPDATE_DATA_PT(160) + OR LRU_UPDATE_DATA_PT(161) OR LRU_UPDATE_DATA_PT(162) + OR LRU_UPDATE_DATA_PT(164) OR LRU_UPDATE_DATA_PT(174) + ); +MQQ177:LRU_UPDATE_DATA(1) <= + (LRU_UPDATE_DATA_PT(5) OR LRU_UPDATE_DATA_PT(6) + OR LRU_UPDATE_DATA_PT(21) OR LRU_UPDATE_DATA_PT(22) + OR LRU_UPDATE_DATA_PT(27) OR LRU_UPDATE_DATA_PT(28) + OR LRU_UPDATE_DATA_PT(29) OR LRU_UPDATE_DATA_PT(30) + OR LRU_UPDATE_DATA_PT(33) OR LRU_UPDATE_DATA_PT(34) + OR LRU_UPDATE_DATA_PT(37) OR LRU_UPDATE_DATA_PT(38) + OR LRU_UPDATE_DATA_PT(59) OR LRU_UPDATE_DATA_PT(60) + OR LRU_UPDATE_DATA_PT(61) OR LRU_UPDATE_DATA_PT(62) + OR LRU_UPDATE_DATA_PT(63) OR LRU_UPDATE_DATA_PT(64) + OR LRU_UPDATE_DATA_PT(65) OR LRU_UPDATE_DATA_PT(70) + OR LRU_UPDATE_DATA_PT(71) OR LRU_UPDATE_DATA_PT(72) + OR LRU_UPDATE_DATA_PT(73) OR LRU_UPDATE_DATA_PT(74) + OR LRU_UPDATE_DATA_PT(75) OR LRU_UPDATE_DATA_PT(76) + OR LRU_UPDATE_DATA_PT(77) OR LRU_UPDATE_DATA_PT(78) + OR LRU_UPDATE_DATA_PT(79) OR LRU_UPDATE_DATA_PT(80) + OR LRU_UPDATE_DATA_PT(81) OR LRU_UPDATE_DATA_PT(82) + OR LRU_UPDATE_DATA_PT(99) OR LRU_UPDATE_DATA_PT(100) + OR LRU_UPDATE_DATA_PT(101) OR LRU_UPDATE_DATA_PT(102) + OR LRU_UPDATE_DATA_PT(103) OR LRU_UPDATE_DATA_PT(107) + OR LRU_UPDATE_DATA_PT(108) OR LRU_UPDATE_DATA_PT(109) + OR LRU_UPDATE_DATA_PT(125) OR LRU_UPDATE_DATA_PT(126) + OR LRU_UPDATE_DATA_PT(127) OR LRU_UPDATE_DATA_PT(128) + OR LRU_UPDATE_DATA_PT(129) OR LRU_UPDATE_DATA_PT(130) + OR LRU_UPDATE_DATA_PT(131) OR LRU_UPDATE_DATA_PT(132) + OR LRU_UPDATE_DATA_PT(133) OR LRU_UPDATE_DATA_PT(134) + OR LRU_UPDATE_DATA_PT(135) OR LRU_UPDATE_DATA_PT(136) + OR LRU_UPDATE_DATA_PT(137) OR LRU_UPDATE_DATA_PT(153) + OR LRU_UPDATE_DATA_PT(163) OR LRU_UPDATE_DATA_PT(166) + OR LRU_UPDATE_DATA_PT(167) OR LRU_UPDATE_DATA_PT(168) + OR LRU_UPDATE_DATA_PT(169) OR LRU_UPDATE_DATA_PT(170) + OR LRU_UPDATE_DATA_PT(171) OR LRU_UPDATE_DATA_PT(172) + OR LRU_UPDATE_DATA_PT(173) OR LRU_UPDATE_DATA_PT(175) + ); +MQQ178:LRU_UPDATE_DATA(2) <= + (LRU_UPDATE_DATA_PT(1) OR LRU_UPDATE_DATA_PT(2) + OR LRU_UPDATE_DATA_PT(3) OR LRU_UPDATE_DATA_PT(4) + OR LRU_UPDATE_DATA_PT(5) OR LRU_UPDATE_DATA_PT(6) + OR LRU_UPDATE_DATA_PT(7) OR LRU_UPDATE_DATA_PT(8) + OR LRU_UPDATE_DATA_PT(9) OR LRU_UPDATE_DATA_PT(10) + OR LRU_UPDATE_DATA_PT(11) OR LRU_UPDATE_DATA_PT(12) + OR LRU_UPDATE_DATA_PT(13) OR LRU_UPDATE_DATA_PT(14) + OR LRU_UPDATE_DATA_PT(15) OR LRU_UPDATE_DATA_PT(16) + OR LRU_UPDATE_DATA_PT(17) OR LRU_UPDATE_DATA_PT(18) + OR LRU_UPDATE_DATA_PT(19) OR LRU_UPDATE_DATA_PT(20) + OR LRU_UPDATE_DATA_PT(23) OR LRU_UPDATE_DATA_PT(24) + OR LRU_UPDATE_DATA_PT(25) OR LRU_UPDATE_DATA_PT(26) + OR LRU_UPDATE_DATA_PT(46) OR LRU_UPDATE_DATA_PT(47) + OR LRU_UPDATE_DATA_PT(48) OR LRU_UPDATE_DATA_PT(49) + OR LRU_UPDATE_DATA_PT(50) OR LRU_UPDATE_DATA_PT(51) + OR LRU_UPDATE_DATA_PT(52) OR LRU_UPDATE_DATA_PT(53) + OR LRU_UPDATE_DATA_PT(54) OR LRU_UPDATE_DATA_PT(55) + OR LRU_UPDATE_DATA_PT(56) OR LRU_UPDATE_DATA_PT(57) + OR LRU_UPDATE_DATA_PT(58) OR LRU_UPDATE_DATA_PT(61) + OR LRU_UPDATE_DATA_PT(64) OR LRU_UPDATE_DATA_PT(66) + OR LRU_UPDATE_DATA_PT(67) OR LRU_UPDATE_DATA_PT(68) + OR LRU_UPDATE_DATA_PT(69) OR LRU_UPDATE_DATA_PT(91) + OR LRU_UPDATE_DATA_PT(93) OR LRU_UPDATE_DATA_PT(94) + OR LRU_UPDATE_DATA_PT(95) OR LRU_UPDATE_DATA_PT(96) + OR LRU_UPDATE_DATA_PT(97) OR LRU_UPDATE_DATA_PT(105) + OR LRU_UPDATE_DATA_PT(110) OR LRU_UPDATE_DATA_PT(111) + OR LRU_UPDATE_DATA_PT(112) OR LRU_UPDATE_DATA_PT(113) + OR LRU_UPDATE_DATA_PT(114) OR LRU_UPDATE_DATA_PT(115) + OR LRU_UPDATE_DATA_PT(116) OR LRU_UPDATE_DATA_PT(117) + OR LRU_UPDATE_DATA_PT(118) OR LRU_UPDATE_DATA_PT(119) + OR LRU_UPDATE_DATA_PT(120) OR LRU_UPDATE_DATA_PT(121) + OR LRU_UPDATE_DATA_PT(122) OR LRU_UPDATE_DATA_PT(123) + OR LRU_UPDATE_DATA_PT(124) OR LRU_UPDATE_DATA_PT(142) + OR LRU_UPDATE_DATA_PT(143) OR LRU_UPDATE_DATA_PT(144) + OR LRU_UPDATE_DATA_PT(145) OR LRU_UPDATE_DATA_PT(146) + OR LRU_UPDATE_DATA_PT(147) OR LRU_UPDATE_DATA_PT(148) + OR LRU_UPDATE_DATA_PT(149) OR LRU_UPDATE_DATA_PT(150) + OR LRU_UPDATE_DATA_PT(151) OR LRU_UPDATE_DATA_PT(152) + OR LRU_UPDATE_DATA_PT(165)); + +--glorp1 +-- lru data format +-- 0:3 - valid(0:3) +-- 4:6 - LRU +-- 7 - parity +-- 8:11 - iprot(0:3) +-- 12:14 - reserved +-- 15 - parity +-- tlb_low_data +-- 0:51 - EPN +-- 52:55 - SIZE (4b) +-- 56:59 - ThdID +-- 60:61 - Class +-- 62 - ExtClass +-- 63 - TID_NZ +-- 64:65 - reserved (2b) +-- 66:73 - 8b for LPID +-- 74:83 - parity 10bits +-- mmucr3 +-- 49 X-bit +-- 50:51 R,C +-- 52 ECL +-- 53 TID_NZ +-- 54:55 Class +-- 56:57 WLC +-- 58:59 ResvAttr +-- 60:63 ThdID +-- unused tagpos_is def is mas1_v, mas1_iprot for tlbwe, and is (pte.valid & 0) for ptereloads +gen64_tlb_datain: if rs_data_width = 64 generate +tlb_datain_lo_tlbwe_0_nopar(0 TO tlb_word_width-10-1) <= + (tlb_tag4_q(tagpos_epn to tagpos_epn+31) and (0 to 31 => tlb_tag4_q(tagpos_cm))) & tlb_tag4_q(tagpos_epn+32 to tagpos_epn+51) & tlb_tag4_q(tagpos_size to tagpos_size+3) & mmucr3_0(60 to 63) & + mmucr3_0(54 to 55) & (mmucr3_0(52) and tlb_tag4_q(tagpos_is+1)) & or_reduce(tlb_tag4_q(tagpos_pid to tagpos_pid+pid_width-1)) & + "00" & tlb_tag4_q(tagpos_lpid to tagpos_lpid+lpid_width-1); +tlb_datain_lo_tlbwe_1_nopar(0 TO tlb_word_width-10-1) <= + (tlb_tag4_q(tagpos_epn to tagpos_epn+31) and (0 to 31 => tlb_tag4_q(tagpos_cm))) & tlb_tag4_q(tagpos_epn+32 to tagpos_epn+51) & tlb_tag4_q(tagpos_size to tagpos_size+3) & mmucr3_1(60 to 63) & + mmucr3_1(54 to 55) & (mmucr3_1(52) and tlb_tag4_q(tagpos_is+1)) & or_reduce(tlb_tag4_q(tagpos_pid to tagpos_pid+pid_width-1)) & + "00" & tlb_tag4_q(tagpos_lpid to tagpos_lpid+lpid_width-1); +tlb_datain_lo_tlbwe_2_nopar(0 TO tlb_word_width-10-1) <= + (tlb_tag4_q(tagpos_epn to tagpos_epn+31) and (0 to 31 => tlb_tag4_q(tagpos_cm))) & tlb_tag4_q(tagpos_epn+32 to tagpos_epn+51) & tlb_tag4_q(tagpos_size to tagpos_size+3) & mmucr3_2(60 to 63) & + mmucr3_2(54 to 55) & (mmucr3_2(52) and tlb_tag4_q(tagpos_is+1)) & or_reduce(tlb_tag4_q(tagpos_pid to tagpos_pid+pid_width-1)) & + "00" & tlb_tag4_q(tagpos_lpid to tagpos_lpid+lpid_width-1); +tlb_datain_lo_tlbwe_3_nopar(0 TO tlb_word_width-10-1) <= + (tlb_tag4_q(tagpos_epn to tagpos_epn+31) and (0 to 31 => tlb_tag4_q(tagpos_cm))) & tlb_tag4_q(tagpos_epn+32 to tagpos_epn+51) & tlb_tag4_q(tagpos_size to tagpos_size+3) & mmucr3_3(60 to 63) & + mmucr3_3(54 to 55) & (mmucr3_3(52) and tlb_tag4_q(tagpos_is+1)) & or_reduce(tlb_tag4_q(tagpos_pid to tagpos_pid+pid_width-1)) & + "00" & tlb_tag4_q(tagpos_lpid to tagpos_lpid+lpid_width-1); +tlb_datain_lo_ptereload_nopar(0 TO tlb_word_width-10-1) <= + tlb_tag4_q(tagpos_epn to tagpos_epn+epn_width-1) & '0' & ptereload_req_pte_lat(ptepos_size to ptepos_size+2) & tlb_tag4_q(tagpos_atsel) & tlb_tag4_q(tagpos_esel to tagpos_esel+2) & + tlb_tag4_q(tagpos_class) & (tlb_tag4_q(tagpos_class) and tlb_tag4_q(tagpos_class+1)) & '0' & or_reduce(tlb_tag4_q(tagpos_pid to tagpos_pid+pid_width-1)) & + "00" & tlb_tag4_q(tagpos_lpid to tagpos_lpid+lpid_width-1); +tlb_dataina_d(0 TO tlb_word_width-1) <= + tlb_datain_lo_tlbwe_0_nopar & tlb_datain_lo_tlbwe_0_par + when (tlb_tag4_q(tagpos_thdid+0)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1') else + tlb_datain_lo_tlbwe_1_nopar & tlb_datain_lo_tlbwe_1_par + when (tlb_tag4_q(tagpos_thdid+1)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1') else + tlb_datain_lo_tlbwe_2_nopar & tlb_datain_lo_tlbwe_2_par + when (tlb_tag4_q(tagpos_thdid+2)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1') else + tlb_datain_lo_tlbwe_3_nopar & tlb_datain_lo_tlbwe_3_par + when (tlb_tag4_q(tagpos_thdid+3)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1') else + tlb_datain_lo_ptereload_nopar & tlb_datain_lo_ptereload_par + when (tlb_tag4_ptereload_sig='1') else + tlb_dataina_q(0 to tlb_word_width-1); +tlb_datainb_d(0 TO tlb_word_width-1) <= + tlb_datain_lo_tlbwe_0_nopar & tlb_datain_lo_tlbwe_0_par + when (tlb_tag4_q(tagpos_thdid+0)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1') else + tlb_datain_lo_tlbwe_1_nopar & tlb_datain_lo_tlbwe_1_par + when (tlb_tag4_q(tagpos_thdid+1)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1') else + tlb_datain_lo_tlbwe_2_nopar & tlb_datain_lo_tlbwe_2_par + when (tlb_tag4_q(tagpos_thdid+2)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1') else + tlb_datain_lo_tlbwe_3_nopar & tlb_datain_lo_tlbwe_3_par + when (tlb_tag4_q(tagpos_thdid+3)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1') else + tlb_datain_lo_ptereload_nopar & tlb_datain_lo_ptereload_par + when (tlb_tag4_ptereload_sig='1') else + tlb_datainb_q(0 to tlb_word_width-1); +end generate gen64_tlb_datain; +gen32_tlb_datain: if rs_data_width = 32 generate +tlb_datain_lo_tlbwe_0_nopar(0 TO tlb_word_width-10-1) <= + (0 to 31 => '0') & tlb_tag4_q(tagpos_epn+32 to tagpos_epn+51) & tlb_tag4_q(tagpos_size to tagpos_size+3) & mmucr3_0(60 to 63) & + mmucr3_0(54 to 55) & (mmucr3_0(52) and tlb_tag4_q(tagpos_is+1)) & or_reduce(tlb_tag4_q(tagpos_pid to tagpos_pid+pid_width-1)) & + "00" & tlb_tag4_q(tagpos_lpid to tagpos_lpid+lpid_width-1); +tlb_datain_lo_tlbwe_1_nopar(0 TO tlb_word_width-10-1) <= + (0 to 31 => '0') & tlb_tag4_q(tagpos_epn+32 to tagpos_epn+51) & tlb_tag4_q(tagpos_size to tagpos_size+3) & mmucr3_1(60 to 63) & + mmucr3_1(54 to 55) & (mmucr3_1(52) and tlb_tag4_q(tagpos_is+1)) & or_reduce(tlb_tag4_q(tagpos_pid to tagpos_pid+pid_width-1)) & + "00" & tlb_tag4_q(tagpos_lpid to tagpos_lpid+lpid_width-1); +tlb_datain_lo_tlbwe_2_nopar(0 TO tlb_word_width-10-1) <= + (0 to 31 => '0') & tlb_tag4_q(tagpos_epn+32 to tagpos_epn+51) & tlb_tag4_q(tagpos_size to tagpos_size+3) & mmucr3_2(60 to 63) & + mmucr3_2(54 to 55) & (mmucr3_2(52) and tlb_tag4_q(tagpos_is+1)) & or_reduce(tlb_tag4_q(tagpos_pid to tagpos_pid+pid_width-1)) & + "00" & tlb_tag4_q(tagpos_lpid to tagpos_lpid+lpid_width-1); +tlb_datain_lo_tlbwe_3_nopar(0 TO tlb_word_width-10-1) <= + (0 to 31 => '0') & tlb_tag4_q(tagpos_epn+32 to tagpos_epn+51) & tlb_tag4_q(tagpos_size to tagpos_size+3) & mmucr3_3(60 to 63) & + mmucr3_3(54 to 55) & (mmucr3_3(52) and tlb_tag4_q(tagpos_is+1)) & or_reduce(tlb_tag4_q(tagpos_pid to tagpos_pid+pid_width-1)) & + "00" & tlb_tag4_q(tagpos_lpid to tagpos_lpid+lpid_width-1); +tlb_datain_lo_ptereload_nopar(0 TO tlb_word_width-10-1) <= + (0 to 31 => '0') & tlb_tag4_q(tagpos_epn+32 to tagpos_epn+epn_width+32-1) & '0' & ptereload_req_pte_lat(ptepos_size to ptepos_size+2) & "1111" & + tlb_tag4_q(tagpos_class to tagpos_class+1) & '0' & or_reduce(tlb_tag4_q(tagpos_pid to tagpos_pid+pid_width-1)) & + "00" & tlb_tag4_q(tagpos_lpid to tagpos_lpid+lpid_width-1); +tlb_dataina_d(0 TO tlb_word_width-1) <= + tlb_datain_lo_tlbwe_0_nopar & tlb_datain_lo_tlbwe_0_par + when (tlb_tag4_q(tagpos_thdid+0)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1') else + tlb_datain_lo_tlbwe_1_nopar & tlb_datain_lo_tlbwe_1_par + when (tlb_tag4_q(tagpos_thdid+1)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1') else + tlb_datain_lo_tlbwe_2_nopar & tlb_datain_lo_tlbwe_2_par + when (tlb_tag4_q(tagpos_thdid+2)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1') else + tlb_datain_lo_tlbwe_3_nopar & tlb_datain_lo_tlbwe_3_par + when (tlb_tag4_q(tagpos_thdid+3)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1') else + tlb_datain_lo_ptereload_nopar & tlb_datain_lo_ptereload_par + when (tlb_tag4_ptereload_sig='1') else + tlb_dataina_q(0 to tlb_word_width-1); +tlb_datainb_d(0 TO tlb_word_width-1) <= + tlb_datain_lo_tlbwe_0_nopar & tlb_datain_lo_tlbwe_0_par + when (tlb_tag4_q(tagpos_thdid+0)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1') else + tlb_datain_lo_tlbwe_1_nopar & tlb_datain_lo_tlbwe_1_par + when (tlb_tag4_q(tagpos_thdid+1)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1') else + tlb_datain_lo_tlbwe_2_nopar & tlb_datain_lo_tlbwe_2_par + when (tlb_tag4_q(tagpos_thdid+2)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1') else + tlb_datain_lo_tlbwe_3_nopar & tlb_datain_lo_tlbwe_3_par + when (tlb_tag4_q(tagpos_thdid+3)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1') else + tlb_datain_lo_ptereload_nopar & tlb_datain_lo_ptereload_par + when (tlb_tag4_ptereload_sig='1') else + tlb_datainb_q(0 to tlb_word_width-1); +end generate gen32_tlb_datain; +-- tlb_high_data +-- 84 - 0 - X-bit +-- 85:87 - 1:3 - reserved (3b) +-- 88:117 - 4:33 - RPN (30b) +-- 118:119 - 34:35 - R,C +-- 120:121 - 36:37 - WLC (2b) +-- 122 - 38 - ResvAttr +-- 123 - 39 - VF +-- 124 - 40 - IND +-- 125:128 - 41:44 - U0-U3 +-- 129:133 - 45:49 - WIMGE +-- 134:135 - 50:51 - UX,SX +-- 136:137 - 52:53 - UW,SW +-- 138:139 - 54:55 - UR,SR +-- 140 - 56 - GS +-- 141 - 57 - TS +-- 142:143 - 58:59 - reserved (2b) +-- 144:149 - 60:65 - 6b TID msbs +-- 150:157 - 66:73 - 8b TID lsbs +-- 158:167 - 74:83 - parity 10bits +-- mmucr3 +-- 49 X-bit +-- 50:51 R,C +-- 52 ECL +-- 53 TID_NZ +-- 54:55 Class +-- 56:57 WLC +-- 58:59 ResvAttr +-- 60:63 ThdID +ptereload_req_derived_usxwr(0) <= ptereload_req_pte_lat(ptepos_usxwr+0) and ptereload_req_pte_lat(ptepos_r); +ptereload_req_derived_usxwr(1) <= ptereload_req_pte_lat(ptepos_usxwr+1) and ptereload_req_pte_lat(ptepos_r); +ptereload_req_derived_usxwr(2) <= ptereload_req_pte_lat(ptepos_usxwr+2) and ptereload_req_pte_lat(ptepos_r) and ptereload_req_pte_lat(ptepos_c); +ptereload_req_derived_usxwr(3) <= ptereload_req_pte_lat(ptepos_usxwr+3) and ptereload_req_pte_lat(ptepos_r) and ptereload_req_pte_lat(ptepos_c); +ptereload_req_derived_usxwr(4) <= ptereload_req_pte_lat(ptepos_usxwr+4) and ptereload_req_pte_lat(ptepos_r); +ptereload_req_derived_usxwr(5) <= ptereload_req_pte_lat(ptepos_usxwr+5) and ptereload_req_pte_lat(ptepos_r); +gen32_lrat_tag3_lpn: if real_addr_width < 42 generate +lrat_tag3_lpn_sig(22 TO 63-real_addr_width) <= (others => '0'); +lrat_tag3_lpn_sig(64-real_addr_width TO 51) <= lrat_tag3_lpn(64-real_addr_width to 51); +end generate gen32_lrat_tag3_lpn; +gen64_lrat_tag3_lpn: if real_addr_width > 41 generate +lrat_tag3_lpn_sig(64-real_addr_width TO 51) <= lrat_tag3_lpn(64-real_addr_width to 51); +end generate gen64_lrat_tag3_lpn; +gen32_lrat_tag3_rpn: if real_addr_width < 42 generate +lrat_tag3_rpn_sig(22 TO 63-real_addr_width) <= (others => '0'); +lrat_tag3_rpn_sig(64-real_addr_width TO 51) <= lrat_tag3_rpn(64-real_addr_width to 51); +end generate gen32_lrat_tag3_rpn; +gen64_lrat_tag3_rpn: if real_addr_width > 41 generate +lrat_tag3_rpn_sig(64-real_addr_width TO 51) <= lrat_tag3_rpn(64-real_addr_width to 51); +end generate gen64_lrat_tag3_rpn; +gen32_lrat_tag4_lpn: if real_addr_width < 42 generate +lrat_tag4_lpn_sig(22 TO 63-real_addr_width) <= (others => '0'); +lrat_tag4_lpn_sig(64-real_addr_width TO 51) <= lrat_tag4_lpn(64-real_addr_width to 51); +end generate gen32_lrat_tag4_lpn; +gen64_lrat_tag4_lpn: if real_addr_width > 41 generate +lrat_tag4_lpn_sig(64-real_addr_width TO 51) <= lrat_tag4_lpn(64-real_addr_width to 51); +end generate gen64_lrat_tag4_lpn; +gen32_lrat_tag4_rpn: if real_addr_width < 42 generate +lrat_tag4_rpn_sig(22 TO 63-real_addr_width) <= (others => '0'); +lrat_tag4_rpn_sig(64-real_addr_width TO 51) <= lrat_tag4_rpn(64-real_addr_width to 51); +end generate gen32_lrat_tag4_rpn; +gen64_lrat_tag4_rpn: if real_addr_width > 41 generate +lrat_tag4_rpn_sig(64-real_addr_width TO 51) <= lrat_tag4_rpn(64-real_addr_width to 51); +end generate gen64_lrat_tag4_rpn; +tlb_datain_hi_hv_tlbwe_0_nopar <= + mmucr3_0(49) & "000" & mas7_0_rpnu & mas3_0_rpnl(32 to 51) & mmucr3_0(50 to 51) & + mmucr3_0(56 to 58) & mas8_0_vf & (tlb_tag4_q(tagpos_ind) and tlb0cfg_ind) & mas3_0_ubits & mas2_0_wimge & + mas3_0_usxwr(0 to 3) & + (mas3_0_usxwr(4) and (not tlb_tag4_q(tagpos_ind) or not tlb0cfg_ind)) & + ((mas3_0_usxwr(5) and (not tlb_tag4_q(tagpos_ind) or not tlb0cfg_ind)) or (mas3_0_rpnl(52) and tlb_tag4_q(tagpos_ind) and tlb0cfg_ind)) & + tlb_tag4_q(tagpos_pt) & tlb_tag4_q(tagpos_recform) & "00" & tlb_tag4_q(tagpos_pid to tagpos_pid+pid_width-1); +tlb_datain_hi_hv_tlbwe_1_nopar <= + mmucr3_1(49) & "000" & mas7_1_rpnu & mas3_1_rpnl(32 to 51) & mmucr3_1(50 to 51) & + mmucr3_1(56 to 58) & mas8_1_vf & (tlb_tag4_q(tagpos_ind) and tlb0cfg_ind) & mas3_1_ubits & mas2_1_wimge & + mas3_1_usxwr(0 to 3) & + (mas3_1_usxwr(4) and (not tlb_tag4_q(tagpos_ind) or not tlb0cfg_ind)) & + ((mas3_1_usxwr(5) and (not tlb_tag4_q(tagpos_ind) or not tlb0cfg_ind)) or (mas3_1_rpnl(52) and tlb_tag4_q(tagpos_ind) and tlb0cfg_ind)) & + tlb_tag4_q(tagpos_pt) & tlb_tag4_q(tagpos_recform) & "00" & tlb_tag4_q(tagpos_pid to tagpos_pid+pid_width-1); +tlb_datain_hi_hv_tlbwe_2_nopar <= + mmucr3_2(49) & "000" & mas7_2_rpnu & mas3_2_rpnl(32 to 51) & mmucr3_2(50 to 51) & + mmucr3_2(56 to 58) & mas8_2_vf & (tlb_tag4_q(tagpos_ind) and tlb0cfg_ind) & mas3_2_ubits & mas2_2_wimge & + mas3_2_usxwr(0 to 3) & + (mas3_2_usxwr(4) and (not tlb_tag4_q(tagpos_ind) or not tlb0cfg_ind)) & + ((mas3_2_usxwr(5) and (not tlb_tag4_q(tagpos_ind) or not tlb0cfg_ind)) or (mas3_2_rpnl(52) and tlb_tag4_q(tagpos_ind) and tlb0cfg_ind)) & + tlb_tag4_q(tagpos_pt) & tlb_tag4_q(tagpos_recform) & "00" & tlb_tag4_q(tagpos_pid to tagpos_pid+pid_width-1); +tlb_datain_hi_hv_tlbwe_3_nopar <= + mmucr3_3(49) & "000" & mas7_3_rpnu & mas3_3_rpnl(32 to 51) & mmucr3_3(50 to 51) & + mmucr3_3(56 to 58) & mas8_3_vf & (tlb_tag4_q(tagpos_ind) and tlb0cfg_ind) & mas3_3_ubits & mas2_3_wimge & + mas3_3_usxwr(0 to 3) & + (mas3_3_usxwr(4) and (not tlb_tag4_q(tagpos_ind) or not tlb0cfg_ind)) & + ((mas3_3_usxwr(5) and (not tlb_tag4_q(tagpos_ind) or not tlb0cfg_ind)) or (mas3_3_rpnl(52) and tlb_tag4_q(tagpos_ind) and tlb0cfg_ind)) & + tlb_tag4_q(tagpos_pt) & tlb_tag4_q(tagpos_recform) & "00" & tlb_tag4_q(tagpos_pid to tagpos_pid+pid_width-1); +tlb_datain_hi_gs_tlbwe_0_nopar <= + mmucr3_0(49) & "000" & lrat_tag4_rpn_sig(22 to 51) & mmucr3_0(50 to 51) & + mmucr3_0(56 to 58) & mas8_0_vf & (tlb_tag4_q(tagpos_ind) and tlb0cfg_ind) & mas3_0_ubits & mas2_0_wimge & + mas3_0_usxwr(0 to 3) & + (mas3_0_usxwr(4) and (not tlb_tag4_q(tagpos_ind) or not tlb0cfg_ind)) & + ((mas3_0_usxwr(5) and (not tlb_tag4_q(tagpos_ind) or not tlb0cfg_ind)) or (mas3_0_rpnl(52) and tlb_tag4_q(tagpos_ind) and tlb0cfg_ind)) & + tlb_tag4_q(tagpos_pt) & tlb_tag4_q(tagpos_recform) & "00" & tlb_tag4_q(tagpos_pid to tagpos_pid+pid_width-1); +tlb_datain_hi_gs_tlbwe_1_nopar <= + mmucr3_1(49) & "000" & lrat_tag4_rpn_sig(22 to 51) & mmucr3_1(50 to 51) & + mmucr3_1(56 to 58) & mas8_1_vf & (tlb_tag4_q(tagpos_ind) and tlb0cfg_ind) & mas3_1_ubits & mas2_1_wimge & + mas3_1_usxwr(0 to 3) & + (mas3_1_usxwr(4) and (not tlb_tag4_q(tagpos_ind) or not tlb0cfg_ind)) & + ((mas3_1_usxwr(5) and (not tlb_tag4_q(tagpos_ind) or not tlb0cfg_ind)) or (mas3_1_rpnl(52) and tlb_tag4_q(tagpos_ind) and tlb0cfg_ind)) & + tlb_tag4_q(tagpos_pt) & tlb_tag4_q(tagpos_recform) & "00" & tlb_tag4_q(tagpos_pid to tagpos_pid+pid_width-1); +tlb_datain_hi_gs_tlbwe_2_nopar <= + mmucr3_2(49) & "000" & lrat_tag4_rpn_sig(22 to 51) & mmucr3_2(50 to 51) & + mmucr3_2(56 to 58) & mas8_2_vf & (tlb_tag4_q(tagpos_ind) and tlb0cfg_ind) & mas3_2_ubits & mas2_2_wimge & + mas3_2_usxwr(0 to 3) & + (mas3_2_usxwr(4) and (not tlb_tag4_q(tagpos_ind) or not tlb0cfg_ind)) & + ((mas3_2_usxwr(5) and (not tlb_tag4_q(tagpos_ind) or not tlb0cfg_ind)) or (mas3_2_rpnl(52) and tlb_tag4_q(tagpos_ind) and tlb0cfg_ind)) & + tlb_tag4_q(tagpos_pt) & tlb_tag4_q(tagpos_recform) & "00" & tlb_tag4_q(tagpos_pid to tagpos_pid+pid_width-1); +tlb_datain_hi_gs_tlbwe_3_nopar <= + mmucr3_3(49) & "000" & lrat_tag4_rpn_sig(22 to 51) & mmucr3_3(50 to 51) & + mmucr3_3(56 to 58) & mas8_3_vf & (tlb_tag4_q(tagpos_ind) and tlb0cfg_ind) & mas3_3_ubits & mas2_3_wimge & + mas3_3_usxwr(0 to 3) & + (mas3_3_usxwr(4) and (not tlb_tag4_q(tagpos_ind) or not tlb0cfg_ind)) & + ((mas3_3_usxwr(5) and (not tlb_tag4_q(tagpos_ind) or not tlb0cfg_ind)) or (mas3_3_rpnl(52) and tlb_tag4_q(tagpos_ind) and tlb0cfg_ind)) & + tlb_tag4_q(tagpos_pt) & tlb_tag4_q(tagpos_recform) & "00" & tlb_tag4_q(tagpos_pid to tagpos_pid+pid_width-1); +tlb_datain_hi_hv_ptereload_nopar <= + '0' & "000" & ptereload_req_pte_lat(ptepos_rpn+10 to ptepos_rpn+39) & ptereload_req_pte_lat(ptepos_r) & ptereload_req_pte_lat(ptepos_c) & + "00" & '0' & '0' & '0' & ptereload_req_pte_lat(ptepos_ubits to ptepos_ubits+3) & ptereload_req_pte_lat(ptepos_wimge to ptepos_wimge+4) & + ptereload_req_derived_usxwr(0 to 5) & + tlb_tag4_q(tagpos_gs) & tlb_tag4_q(tagpos_as) & "00" & tlb_tag4_q(tagpos_pid to tagpos_pid+pid_width-1); +tlb_datain_hi_gs_ptereload_nopar <= + '0' & "000" & lrat_tag4_rpn_sig(22 to 51) & ptereload_req_pte_lat(ptepos_r) & ptereload_req_pte_lat(ptepos_c) & + "00" & '0' & '0' & '0' & ptereload_req_pte_lat(ptepos_ubits to ptepos_ubits+3) & ptereload_req_pte_lat(ptepos_wimge to ptepos_wimge+4) & + ptereload_req_derived_usxwr(0 to 5) & + tlb_tag4_q(tagpos_gs) & tlb_tag4_q(tagpos_as) & "00" & tlb_tag4_q(tagpos_pid to tagpos_pid+pid_width-1); +-- unused tagpos_is def is mas1_v, mas1_iprot for tlbwe, and is (pte.valid & 0) for ptereloads +tlb_dataina_d(tlb_word_width TO 2*tlb_word_width-1) <= + tlb_datain_hi_hv_tlbwe_0_nopar & tlb_datain_hi_hv_tlbwe_0_par + when (tlb_tag4_q(tagpos_thdid+0)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1' and (tlb_tag4_q(tagpos_gs)='0' or tlb_tag4_q(tagpos_is)='0')) else + tlb_datain_hi_hv_tlbwe_1_nopar & tlb_datain_hi_hv_tlbwe_1_par + when (tlb_tag4_q(tagpos_thdid+1)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1' and (tlb_tag4_q(tagpos_gs)='0' or tlb_tag4_q(tagpos_is)='0')) else + tlb_datain_hi_hv_tlbwe_2_nopar & tlb_datain_hi_hv_tlbwe_2_par + when (tlb_tag4_q(tagpos_thdid+2)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1' and (tlb_tag4_q(tagpos_gs)='0' or tlb_tag4_q(tagpos_is)='0')) else + tlb_datain_hi_hv_tlbwe_3_nopar & tlb_datain_hi_hv_tlbwe_3_par + when (tlb_tag4_q(tagpos_thdid+3)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1' and (tlb_tag4_q(tagpos_gs)='0' or tlb_tag4_q(tagpos_is)='0')) else + tlb_datain_hi_gs_tlbwe_0_nopar & tlb_datain_hi_gs_tlbwe_0_par + when (tlb_tag4_q(tagpos_thdid+0)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1' and tlb_tag4_q(tagpos_gs)='1' and tlb_tag4_q(tagpos_is)='1') else + tlb_datain_hi_gs_tlbwe_1_nopar & tlb_datain_hi_gs_tlbwe_1_par + when (tlb_tag4_q(tagpos_thdid+1)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1' and tlb_tag4_q(tagpos_gs)='1' and tlb_tag4_q(tagpos_is)='1') else + tlb_datain_hi_gs_tlbwe_2_nopar & tlb_datain_hi_gs_tlbwe_2_par + when (tlb_tag4_q(tagpos_thdid+2)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1' and tlb_tag4_q(tagpos_gs)='1' and tlb_tag4_q(tagpos_is)='1') else + tlb_datain_hi_gs_tlbwe_3_nopar & tlb_datain_hi_gs_tlbwe_3_par + when (tlb_tag4_q(tagpos_thdid+3)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1' and tlb_tag4_q(tagpos_gs)='1' and tlb_tag4_q(tagpos_is)='1') else + tlb_datain_hi_hv_ptereload_nopar & tlb_datain_hi_hv_ptereload_par + when (tlb_tag4_ptereload_sig='1' and tlb_tag4_q(tagpos_gs)='0') else + tlb_datain_hi_gs_ptereload_nopar & tlb_datain_hi_gs_ptereload_par + when (tlb_tag4_ptereload_sig='1' and tlb_tag4_q(tagpos_gs)='1') else + tlb_dataina_q(tlb_word_width to 2*tlb_word_width-1); +tlb_datainb_d(tlb_word_width TO 2*tlb_word_width-1) <= + tlb_datain_hi_hv_tlbwe_0_nopar & tlb_datain_hi_hv_tlbwe_0_par + when (tlb_tag4_q(tagpos_thdid+0)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1' and (tlb_tag4_q(tagpos_gs)='0' or tlb_tag4_q(tagpos_is)='0')) else + tlb_datain_hi_hv_tlbwe_1_nopar & tlb_datain_hi_hv_tlbwe_1_par + when (tlb_tag4_q(tagpos_thdid+1)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1' and (tlb_tag4_q(tagpos_gs)='0' or tlb_tag4_q(tagpos_is)='0')) else + tlb_datain_hi_hv_tlbwe_2_nopar & tlb_datain_hi_hv_tlbwe_2_par + when (tlb_tag4_q(tagpos_thdid+2)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1' and (tlb_tag4_q(tagpos_gs)='0' or tlb_tag4_q(tagpos_is)='0')) else + tlb_datain_hi_hv_tlbwe_3_nopar & tlb_datain_hi_hv_tlbwe_3_par + when (tlb_tag4_q(tagpos_thdid+3)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1' and (tlb_tag4_q(tagpos_gs)='0' or tlb_tag4_q(tagpos_is)='0')) else + tlb_datain_hi_gs_tlbwe_0_nopar & tlb_datain_hi_gs_tlbwe_0_par + when (tlb_tag4_q(tagpos_thdid+0)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1' and tlb_tag4_q(tagpos_gs)='1' and tlb_tag4_q(tagpos_is)='1') else + tlb_datain_hi_gs_tlbwe_1_nopar & tlb_datain_hi_gs_tlbwe_1_par + when (tlb_tag4_q(tagpos_thdid+1)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1' and tlb_tag4_q(tagpos_gs)='1' and tlb_tag4_q(tagpos_is)='1') else + tlb_datain_hi_gs_tlbwe_2_nopar & tlb_datain_hi_gs_tlbwe_2_par + when (tlb_tag4_q(tagpos_thdid+2)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1' and tlb_tag4_q(tagpos_gs)='1' and tlb_tag4_q(tagpos_is)='1') else + tlb_datain_hi_gs_tlbwe_3_nopar & tlb_datain_hi_gs_tlbwe_3_par + when (tlb_tag4_q(tagpos_thdid+3)='1' and tlb_tag4_q(tagpos_type_tlbwe)='1' and tlb_tag4_q(tagpos_gs)='1' and tlb_tag4_q(tagpos_is)='1') else + tlb_datain_hi_hv_ptereload_nopar & tlb_datain_hi_hv_ptereload_par + when (tlb_tag4_ptereload_sig='1' and tlb_tag4_q(tagpos_gs)='0') else + tlb_datain_hi_gs_ptereload_nopar & tlb_datain_hi_gs_ptereload_par + when (tlb_tag4_ptereload_sig='1' and tlb_tag4_q(tagpos_gs)='1') else + tlb_datainb_q(tlb_word_width to 2*tlb_word_width-1); +-- tlb_high_data +-- 84 - 0 - X-bit +-- 85:87 - 1:3 - reserved (3b) +-- 88:117 - 4:33 - RPN (30b) +-- 118:119 - 34:35 - R,C +-- 120:121 - 36:37 - WLC (2b) +-- 122 - 38 - ResvAttr +-- 123 - 39 - VF +-- 124 - 40 - IND +-- 125:128 - 41:44 - U0-U3 +-- 129:133 - 45:49 - WIMGE +-- 134:135 - 50:51 - UX,SX +-- 136:137 - 52:53 - UW,SW +-- 138:139 - 54:55 - UR,SR +-- 140 - 56 - GS +-- 141 - 57 - TS +-- 142:143 - 58:59 - reserved (2b) +-- 144:149 - 60:65 - 6b TID msbs +-- 150:157 - 66:73 - 8b TID lsbs +-- 158:167 - 74:83 - parity 10bits +-- mmucr3 +-- 49 X-bit +-- 50:51 R,C +-- 52 ECL +-- 53 TID_NZ +-- 54:55 Class +-- 56:57 WLC +-- 58:59 ResvAttr +-- 60:63 ThdID +-- TLB Parity Generation +tlb_datain_lo_tlbwe_0_par(0) <= xor_reduce(tlb_datain_lo_tlbwe_0_nopar(0 to 7)); +tlb_datain_lo_tlbwe_0_par(1) <= xor_reduce(tlb_datain_lo_tlbwe_0_nopar(8 to 15)); +tlb_datain_lo_tlbwe_0_par(2) <= xor_reduce(tlb_datain_lo_tlbwe_0_nopar(16 to 23)); +tlb_datain_lo_tlbwe_0_par(3) <= xor_reduce(tlb_datain_lo_tlbwe_0_nopar(24 to 31)); +tlb_datain_lo_tlbwe_0_par(4) <= xor_reduce(tlb_datain_lo_tlbwe_0_nopar(32 to 39)); +tlb_datain_lo_tlbwe_0_par(5) <= xor_reduce(tlb_datain_lo_tlbwe_0_nopar(40 to 47)); +tlb_datain_lo_tlbwe_0_par(7) <= xor_reduce(tlb_datain_lo_tlbwe_0_nopar(52 to 59)); +tlb_datain_lo_tlbwe_0_par(8) <= xor_reduce(tlb_datain_lo_tlbwe_0_nopar(60 to 65)); +tlb_datain_lo_tlbwe_0_par(9) <= xor_reduce(tlb_datain_lo_tlbwe_0_nopar(66 to 73)); +tlb_datain_lo_tlbwe_1_par(0) <= xor_reduce(tlb_datain_lo_tlbwe_1_nopar(0 to 7)); +tlb_datain_lo_tlbwe_1_par(1) <= xor_reduce(tlb_datain_lo_tlbwe_1_nopar(8 to 15)); +tlb_datain_lo_tlbwe_1_par(2) <= xor_reduce(tlb_datain_lo_tlbwe_1_nopar(16 to 23)); +tlb_datain_lo_tlbwe_1_par(3) <= xor_reduce(tlb_datain_lo_tlbwe_1_nopar(24 to 31)); +tlb_datain_lo_tlbwe_1_par(4) <= xor_reduce(tlb_datain_lo_tlbwe_1_nopar(32 to 39)); +tlb_datain_lo_tlbwe_1_par(5) <= xor_reduce(tlb_datain_lo_tlbwe_1_nopar(40 to 47)); +tlb_datain_lo_tlbwe_1_par(7) <= xor_reduce(tlb_datain_lo_tlbwe_1_nopar(52 to 59)); +tlb_datain_lo_tlbwe_1_par(8) <= xor_reduce(tlb_datain_lo_tlbwe_1_nopar(60 to 65)); +tlb_datain_lo_tlbwe_1_par(9) <= xor_reduce(tlb_datain_lo_tlbwe_1_nopar(66 to 73)); +tlb_datain_lo_tlbwe_2_par(0) <= xor_reduce(tlb_datain_lo_tlbwe_2_nopar(0 to 7)); +tlb_datain_lo_tlbwe_2_par(1) <= xor_reduce(tlb_datain_lo_tlbwe_2_nopar(8 to 15)); +tlb_datain_lo_tlbwe_2_par(2) <= xor_reduce(tlb_datain_lo_tlbwe_2_nopar(16 to 23)); +tlb_datain_lo_tlbwe_2_par(3) <= xor_reduce(tlb_datain_lo_tlbwe_2_nopar(24 to 31)); +tlb_datain_lo_tlbwe_2_par(4) <= xor_reduce(tlb_datain_lo_tlbwe_2_nopar(32 to 39)); +tlb_datain_lo_tlbwe_2_par(5) <= xor_reduce(tlb_datain_lo_tlbwe_2_nopar(40 to 47)); +tlb_datain_lo_tlbwe_2_par(7) <= xor_reduce(tlb_datain_lo_tlbwe_2_nopar(52 to 59)); +tlb_datain_lo_tlbwe_2_par(8) <= xor_reduce(tlb_datain_lo_tlbwe_2_nopar(60 to 65)); +tlb_datain_lo_tlbwe_2_par(9) <= xor_reduce(tlb_datain_lo_tlbwe_2_nopar(66 to 73)); +tlb_datain_lo_tlbwe_3_par(0) <= xor_reduce(tlb_datain_lo_tlbwe_3_nopar(0 to 7)); +tlb_datain_lo_tlbwe_3_par(1) <= xor_reduce(tlb_datain_lo_tlbwe_3_nopar(8 to 15)); +tlb_datain_lo_tlbwe_3_par(2) <= xor_reduce(tlb_datain_lo_tlbwe_3_nopar(16 to 23)); +tlb_datain_lo_tlbwe_3_par(3) <= xor_reduce(tlb_datain_lo_tlbwe_3_nopar(24 to 31)); +tlb_datain_lo_tlbwe_3_par(4) <= xor_reduce(tlb_datain_lo_tlbwe_3_nopar(32 to 39)); +tlb_datain_lo_tlbwe_3_par(5) <= xor_reduce(tlb_datain_lo_tlbwe_3_nopar(40 to 47)); +tlb_datain_lo_tlbwe_3_par(7) <= xor_reduce(tlb_datain_lo_tlbwe_3_nopar(52 to 59)); +tlb_datain_lo_tlbwe_3_par(8) <= xor_reduce(tlb_datain_lo_tlbwe_3_nopar(60 to 65)); +tlb_datain_lo_tlbwe_3_par(9) <= xor_reduce(tlb_datain_lo_tlbwe_3_nopar(66 to 73)); +tlb_datain_lo_tlbwe_0_par(6) <= xor_reduce(tlb_datain_lo_tlbwe_0_nopar(48 to 51) & mmucr1_q(pos_tlb_pei)); +tlb_datain_lo_tlbwe_1_par(6) <= xor_reduce(tlb_datain_lo_tlbwe_1_nopar(48 to 51) & mmucr1_q(pos_tlb_pei)); +tlb_datain_lo_tlbwe_2_par(6) <= xor_reduce(tlb_datain_lo_tlbwe_2_nopar(48 to 51) & mmucr1_clone_q(pos_tlb_pei)); +tlb_datain_lo_tlbwe_3_par(6) <= xor_reduce(tlb_datain_lo_tlbwe_3_nopar(48 to 51) & mmucr1_clone_q(pos_tlb_pei)); +tlb_datain_lo_ptereload_par(0) <= xor_reduce(tlb_datain_lo_ptereload_nopar(0 to 7)); +tlb_datain_lo_ptereload_par(1) <= xor_reduce(tlb_datain_lo_ptereload_nopar(8 to 15)); +tlb_datain_lo_ptereload_par(2) <= xor_reduce(tlb_datain_lo_ptereload_nopar(16 to 23)); +tlb_datain_lo_ptereload_par(3) <= xor_reduce(tlb_datain_lo_ptereload_nopar(24 to 31)); +tlb_datain_lo_ptereload_par(4) <= xor_reduce(tlb_datain_lo_ptereload_nopar(32 to 39)); +tlb_datain_lo_ptereload_par(5) <= xor_reduce(tlb_datain_lo_ptereload_nopar(40 to 47)); +tlb_datain_lo_ptereload_par(6) <= xor_reduce(tlb_datain_lo_ptereload_nopar(48 to 51)); +tlb_datain_lo_ptereload_par(7) <= xor_reduce(tlb_datain_lo_ptereload_nopar(52 to 59)); +tlb_datain_lo_ptereload_par(8) <= xor_reduce(tlb_datain_lo_ptereload_nopar(60 to 65)); +tlb_datain_lo_ptereload_par(9) <= xor_reduce(tlb_datain_lo_ptereload_nopar(66 to 73)); +tlb_datain_hi_hv_tlbwe_0_par(0) <= xor_reduce(tlb_datain_hi_hv_tlbwe_0_nopar(0 to 7)); +tlb_datain_hi_hv_tlbwe_0_par(1) <= xor_reduce(tlb_datain_hi_hv_tlbwe_0_nopar(8 to 15)); +tlb_datain_hi_hv_tlbwe_0_par(2) <= xor_reduce(tlb_datain_hi_hv_tlbwe_0_nopar(16 to 23)); +tlb_datain_hi_hv_tlbwe_0_par(3) <= xor_reduce(tlb_datain_hi_hv_tlbwe_0_nopar(24 to 31)); +tlb_datain_hi_hv_tlbwe_0_par(4) <= xor_reduce(tlb_datain_hi_hv_tlbwe_0_nopar(32 to 39)); +tlb_datain_hi_hv_tlbwe_0_par(5) <= xor_reduce(tlb_datain_hi_hv_tlbwe_0_nopar(40 to 44)); +tlb_datain_hi_hv_tlbwe_0_par(6) <= xor_reduce(tlb_datain_hi_hv_tlbwe_0_nopar(45 to 49)); +tlb_datain_hi_hv_tlbwe_0_par(7) <= xor_reduce(tlb_datain_hi_hv_tlbwe_0_nopar(50 to 57)); +tlb_datain_hi_hv_tlbwe_0_par(8) <= xor_reduce(tlb_datain_hi_hv_tlbwe_0_nopar(58 to 65)); +tlb_datain_hi_hv_tlbwe_0_par(9) <= xor_reduce(tlb_datain_hi_hv_tlbwe_0_nopar(66 to 73)); +tlb_datain_hi_hv_tlbwe_1_par(0) <= xor_reduce(tlb_datain_hi_hv_tlbwe_1_nopar(0 to 7)); +tlb_datain_hi_hv_tlbwe_1_par(1) <= xor_reduce(tlb_datain_hi_hv_tlbwe_1_nopar(8 to 15)); +tlb_datain_hi_hv_tlbwe_1_par(2) <= xor_reduce(tlb_datain_hi_hv_tlbwe_1_nopar(16 to 23)); +tlb_datain_hi_hv_tlbwe_1_par(3) <= xor_reduce(tlb_datain_hi_hv_tlbwe_1_nopar(24 to 31)); +tlb_datain_hi_hv_tlbwe_1_par(4) <= xor_reduce(tlb_datain_hi_hv_tlbwe_1_nopar(32 to 39)); +tlb_datain_hi_hv_tlbwe_1_par(5) <= xor_reduce(tlb_datain_hi_hv_tlbwe_1_nopar(40 to 44)); +tlb_datain_hi_hv_tlbwe_1_par(6) <= xor_reduce(tlb_datain_hi_hv_tlbwe_1_nopar(45 to 49)); +tlb_datain_hi_hv_tlbwe_1_par(7) <= xor_reduce(tlb_datain_hi_hv_tlbwe_1_nopar(50 to 57)); +tlb_datain_hi_hv_tlbwe_1_par(8) <= xor_reduce(tlb_datain_hi_hv_tlbwe_1_nopar(58 to 65)); +tlb_datain_hi_hv_tlbwe_1_par(9) <= xor_reduce(tlb_datain_hi_hv_tlbwe_1_nopar(66 to 73)); +tlb_datain_hi_hv_tlbwe_2_par(0) <= xor_reduce(tlb_datain_hi_hv_tlbwe_2_nopar(0 to 7)); +tlb_datain_hi_hv_tlbwe_2_par(1) <= xor_reduce(tlb_datain_hi_hv_tlbwe_2_nopar(8 to 15)); +tlb_datain_hi_hv_tlbwe_2_par(2) <= xor_reduce(tlb_datain_hi_hv_tlbwe_2_nopar(16 to 23)); +tlb_datain_hi_hv_tlbwe_2_par(3) <= xor_reduce(tlb_datain_hi_hv_tlbwe_2_nopar(24 to 31)); +tlb_datain_hi_hv_tlbwe_2_par(4) <= xor_reduce(tlb_datain_hi_hv_tlbwe_2_nopar(32 to 39)); +tlb_datain_hi_hv_tlbwe_2_par(5) <= xor_reduce(tlb_datain_hi_hv_tlbwe_2_nopar(40 to 44)); +tlb_datain_hi_hv_tlbwe_2_par(6) <= xor_reduce(tlb_datain_hi_hv_tlbwe_2_nopar(45 to 49)); +tlb_datain_hi_hv_tlbwe_2_par(7) <= xor_reduce(tlb_datain_hi_hv_tlbwe_2_nopar(50 to 57)); +tlb_datain_hi_hv_tlbwe_2_par(8) <= xor_reduce(tlb_datain_hi_hv_tlbwe_2_nopar(58 to 65)); +tlb_datain_hi_hv_tlbwe_2_par(9) <= xor_reduce(tlb_datain_hi_hv_tlbwe_2_nopar(66 to 73)); +tlb_datain_hi_hv_tlbwe_3_par(0) <= xor_reduce(tlb_datain_hi_hv_tlbwe_3_nopar(0 to 7)); +tlb_datain_hi_hv_tlbwe_3_par(1) <= xor_reduce(tlb_datain_hi_hv_tlbwe_3_nopar(8 to 15)); +tlb_datain_hi_hv_tlbwe_3_par(2) <= xor_reduce(tlb_datain_hi_hv_tlbwe_3_nopar(16 to 23)); +tlb_datain_hi_hv_tlbwe_3_par(3) <= xor_reduce(tlb_datain_hi_hv_tlbwe_3_nopar(24 to 31)); +tlb_datain_hi_hv_tlbwe_3_par(4) <= xor_reduce(tlb_datain_hi_hv_tlbwe_3_nopar(32 to 39)); +tlb_datain_hi_hv_tlbwe_3_par(5) <= xor_reduce(tlb_datain_hi_hv_tlbwe_3_nopar(40 to 44)); +tlb_datain_hi_hv_tlbwe_3_par(6) <= xor_reduce(tlb_datain_hi_hv_tlbwe_3_nopar(45 to 49)); +tlb_datain_hi_hv_tlbwe_3_par(7) <= xor_reduce(tlb_datain_hi_hv_tlbwe_3_nopar(50 to 57)); +tlb_datain_hi_hv_tlbwe_3_par(8) <= xor_reduce(tlb_datain_hi_hv_tlbwe_3_nopar(58 to 65)); +tlb_datain_hi_hv_tlbwe_3_par(9) <= xor_reduce(tlb_datain_hi_hv_tlbwe_3_nopar(66 to 73)); +tlb_datain_hi_gs_tlbwe_0_par(0) <= xor_reduce(tlb_datain_hi_gs_tlbwe_0_nopar(0 to 7)); +tlb_datain_hi_gs_tlbwe_0_par(1) <= xor_reduce(tlb_datain_hi_gs_tlbwe_0_nopar(8 to 15)); +tlb_datain_hi_gs_tlbwe_0_par(2) <= xor_reduce(tlb_datain_hi_gs_tlbwe_0_nopar(16 to 23)); +tlb_datain_hi_gs_tlbwe_0_par(3) <= xor_reduce(tlb_datain_hi_gs_tlbwe_0_nopar(24 to 31)); +tlb_datain_hi_gs_tlbwe_0_par(4) <= xor_reduce(tlb_datain_hi_gs_tlbwe_0_nopar(32 to 39)); +tlb_datain_hi_gs_tlbwe_0_par(5) <= xor_reduce(tlb_datain_hi_gs_tlbwe_0_nopar(40 to 44)); +tlb_datain_hi_gs_tlbwe_0_par(6) <= xor_reduce(tlb_datain_hi_gs_tlbwe_0_nopar(45 to 49)); +tlb_datain_hi_gs_tlbwe_0_par(7) <= xor_reduce(tlb_datain_hi_gs_tlbwe_0_nopar(50 to 57)); +tlb_datain_hi_gs_tlbwe_0_par(8) <= xor_reduce(tlb_datain_hi_gs_tlbwe_0_nopar(58 to 65)); +tlb_datain_hi_gs_tlbwe_0_par(9) <= xor_reduce(tlb_datain_hi_gs_tlbwe_0_nopar(66 to 73)); +tlb_datain_hi_gs_tlbwe_1_par(0) <= xor_reduce(tlb_datain_hi_gs_tlbwe_1_nopar(0 to 7)); +tlb_datain_hi_gs_tlbwe_1_par(1) <= xor_reduce(tlb_datain_hi_gs_tlbwe_1_nopar(8 to 15)); +tlb_datain_hi_gs_tlbwe_1_par(2) <= xor_reduce(tlb_datain_hi_gs_tlbwe_1_nopar(16 to 23)); +tlb_datain_hi_gs_tlbwe_1_par(3) <= xor_reduce(tlb_datain_hi_gs_tlbwe_1_nopar(24 to 31)); +tlb_datain_hi_gs_tlbwe_1_par(4) <= xor_reduce(tlb_datain_hi_gs_tlbwe_1_nopar(32 to 39)); +tlb_datain_hi_gs_tlbwe_1_par(5) <= xor_reduce(tlb_datain_hi_gs_tlbwe_1_nopar(40 to 44)); +tlb_datain_hi_gs_tlbwe_1_par(6) <= xor_reduce(tlb_datain_hi_gs_tlbwe_1_nopar(45 to 49)); +tlb_datain_hi_gs_tlbwe_1_par(7) <= xor_reduce(tlb_datain_hi_gs_tlbwe_1_nopar(50 to 57)); +tlb_datain_hi_gs_tlbwe_1_par(8) <= xor_reduce(tlb_datain_hi_gs_tlbwe_1_nopar(58 to 65)); +tlb_datain_hi_gs_tlbwe_1_par(9) <= xor_reduce(tlb_datain_hi_gs_tlbwe_1_nopar(66 to 73)); +tlb_datain_hi_gs_tlbwe_2_par(0) <= xor_reduce(tlb_datain_hi_gs_tlbwe_2_nopar(0 to 7)); +tlb_datain_hi_gs_tlbwe_2_par(1) <= xor_reduce(tlb_datain_hi_gs_tlbwe_2_nopar(8 to 15)); +tlb_datain_hi_gs_tlbwe_2_par(2) <= xor_reduce(tlb_datain_hi_gs_tlbwe_2_nopar(16 to 23)); +tlb_datain_hi_gs_tlbwe_2_par(3) <= xor_reduce(tlb_datain_hi_gs_tlbwe_2_nopar(24 to 31)); +tlb_datain_hi_gs_tlbwe_2_par(4) <= xor_reduce(tlb_datain_hi_gs_tlbwe_2_nopar(32 to 39)); +tlb_datain_hi_gs_tlbwe_2_par(5) <= xor_reduce(tlb_datain_hi_gs_tlbwe_2_nopar(40 to 44)); +tlb_datain_hi_gs_tlbwe_2_par(6) <= xor_reduce(tlb_datain_hi_gs_tlbwe_2_nopar(45 to 49)); +tlb_datain_hi_gs_tlbwe_2_par(7) <= xor_reduce(tlb_datain_hi_gs_tlbwe_2_nopar(50 to 57)); +tlb_datain_hi_gs_tlbwe_2_par(8) <= xor_reduce(tlb_datain_hi_gs_tlbwe_2_nopar(58 to 65)); +tlb_datain_hi_gs_tlbwe_2_par(9) <= xor_reduce(tlb_datain_hi_gs_tlbwe_2_nopar(66 to 73)); +tlb_datain_hi_gs_tlbwe_3_par(0) <= xor_reduce(tlb_datain_hi_gs_tlbwe_3_nopar(0 to 7)); +tlb_datain_hi_gs_tlbwe_3_par(1) <= xor_reduce(tlb_datain_hi_gs_tlbwe_3_nopar(8 to 15)); +tlb_datain_hi_gs_tlbwe_3_par(2) <= xor_reduce(tlb_datain_hi_gs_tlbwe_3_nopar(16 to 23)); +tlb_datain_hi_gs_tlbwe_3_par(3) <= xor_reduce(tlb_datain_hi_gs_tlbwe_3_nopar(24 to 31)); +tlb_datain_hi_gs_tlbwe_3_par(4) <= xor_reduce(tlb_datain_hi_gs_tlbwe_3_nopar(32 to 39)); +tlb_datain_hi_gs_tlbwe_3_par(5) <= xor_reduce(tlb_datain_hi_gs_tlbwe_3_nopar(40 to 44)); +tlb_datain_hi_gs_tlbwe_3_par(6) <= xor_reduce(tlb_datain_hi_gs_tlbwe_3_nopar(45 to 49)); +tlb_datain_hi_gs_tlbwe_3_par(7) <= xor_reduce(tlb_datain_hi_gs_tlbwe_3_nopar(50 to 57)); +tlb_datain_hi_gs_tlbwe_3_par(8) <= xor_reduce(tlb_datain_hi_gs_tlbwe_3_nopar(58 to 65)); +tlb_datain_hi_gs_tlbwe_3_par(9) <= xor_reduce(tlb_datain_hi_gs_tlbwe_3_nopar(66 to 73)); +tlb_datain_hi_hv_ptereload_par(0) <= xor_reduce(tlb_datain_hi_hv_ptereload_nopar(0 to 7)); +tlb_datain_hi_hv_ptereload_par(1) <= xor_reduce(tlb_datain_hi_hv_ptereload_nopar(8 to 15)); +tlb_datain_hi_hv_ptereload_par(2) <= xor_reduce(tlb_datain_hi_hv_ptereload_nopar(16 to 23)); +tlb_datain_hi_hv_ptereload_par(3) <= xor_reduce(tlb_datain_hi_hv_ptereload_nopar(24 to 31)); +tlb_datain_hi_hv_ptereload_par(4) <= xor_reduce(tlb_datain_hi_hv_ptereload_nopar(32 to 39)); +tlb_datain_hi_hv_ptereload_par(5) <= xor_reduce(tlb_datain_hi_hv_ptereload_nopar(40 to 44)); +tlb_datain_hi_hv_ptereload_par(6) <= xor_reduce(tlb_datain_hi_hv_ptereload_nopar(45 to 49)); +tlb_datain_hi_hv_ptereload_par(7) <= xor_reduce(tlb_datain_hi_hv_ptereload_nopar(50 to 57)); +tlb_datain_hi_hv_ptereload_par(8) <= xor_reduce(tlb_datain_hi_hv_ptereload_nopar(58 to 65)); +tlb_datain_hi_hv_ptereload_par(9) <= xor_reduce(tlb_datain_hi_hv_ptereload_nopar(66 to 73)); +tlb_datain_hi_gs_ptereload_par(0) <= xor_reduce(tlb_datain_hi_gs_ptereload_nopar(0 to 7)); +tlb_datain_hi_gs_ptereload_par(1) <= xor_reduce(tlb_datain_hi_gs_ptereload_nopar(8 to 15)); +tlb_datain_hi_gs_ptereload_par(2) <= xor_reduce(tlb_datain_hi_gs_ptereload_nopar(16 to 23)); +tlb_datain_hi_gs_ptereload_par(3) <= xor_reduce(tlb_datain_hi_gs_ptereload_nopar(24 to 31)); +tlb_datain_hi_gs_ptereload_par(4) <= xor_reduce(tlb_datain_hi_gs_ptereload_nopar(32 to 39)); +tlb_datain_hi_gs_ptereload_par(5) <= xor_reduce(tlb_datain_hi_gs_ptereload_nopar(40 to 44)); +tlb_datain_hi_gs_ptereload_par(6) <= xor_reduce(tlb_datain_hi_gs_ptereload_nopar(45 to 49)); +tlb_datain_hi_gs_ptereload_par(7) <= xor_reduce(tlb_datain_hi_gs_ptereload_nopar(50 to 57)); +tlb_datain_hi_gs_ptereload_par(8) <= xor_reduce(tlb_datain_hi_gs_ptereload_nopar(58 to 65)); +tlb_datain_hi_gs_ptereload_par(9) <= xor_reduce(tlb_datain_hi_gs_ptereload_nopar(66 to 73)); +-- ex7 phase signals +tlb_dataina <= tlb_dataina_q; +tlb_datainb <= tlb_datainb_q; +tlb_cmp_dbg_tag5_tlb_datain_q <= tlb_dataina_q; +--glorp2 +-- tlb_low_data +-- 0:51 - EPN +-- 52:55 - SIZE (4b) +-- 56:59 - ThdID +-- 60:61 - Class +-- 62:63 - ExtClass +-- 64:65 - reserved (2b) +-- 66:73 - 8b for LPID +-- 74:83 - parity 10bits +-- tlb_high_data +-- 84 - 0 - X-bit +-- 85:87 - 1:3 - reserved (3b) +-- 88:117 - 4:33 - RPN (30b) +-- 118:119 - 34:35 - R,C +-- 120:121 - 36:37 - WLC (2b) +-- 122 - 38 - ResvAttr +-- 123 - 39 - VF +-- 124 - 40 - IND +-- 125:128 - 41:44 - U0-U3 +-- 129:133 - 45:49 - WIMGE +-- 134:136 - 50:52 - UX,UW,UR +-- 137:139 - 53:55 - SX,SW,SR +-- 140 - 56 - GS +-- 141 - 57 - TS +-- 142:143 - 58:59 - reserved (2b) +-- 144:149 - 60:65 - 6b TID msbs +-- 150:157 - 66:73 - 8b TID lsbs +-- 158:167 - 74:83 - parity 10bits +----------- this is what the erat expects on reload bus +-- 0:51 - EPN +-- 52 - X +-- 53:55 - SIZE +-- 56 - V +-- 57:60 - ThdID +-- 61:62 - Class +-- 63:64 - ExtClass +-- 65 - write enable +-- 0:3 66:69 - reserved RPN +-- 4:33 70:99 - RPN +-- 34:35 100:101 - R,C +-- 36 102 - reserved +-- 37:38 103:104 - WLC +-- 39 105 - ResvAttr +-- 40 106 - VF +-- 41:44 107:110 - U0-U3 +-- 45:49 111:115 - WIMGE +-- 50:51 116:117 - UX,SX +-- 52:53 118:119 - UW,SW +-- 54:55 120:121 - UR,SR +-- 56 122 - GS +-- 57 123 - TS +-- 58:65 124:131 - TID lsbs +----------- +-- waypos_epn : natural := 0; +-- waypos_size : natural := 52; +-- waypos_thdid : natural := 56; +-- waypos_class : natural := 60; +-- waypos_extclass : natural := 62; +-- waypos_lpid : natural := 66; +-- waypos_xbit : natural := 84; +-- waypos_rpn : natural := 88; +-- waypos_rc : natural := 118; +-- waypos_wlc : natural := 120; +-- waypos_resvattr : natural := 122; +-- waypos_vf : natural := 123; +-- waypos_ind : natural := 124; +-- waypos_ubits : natural := 125; +-- waypos_wimge : natural := 129; +-- waypos_usxwr : natural := 134; +-- waypos_gs : natural := 140; +-- waypos_ts : natural := 141; +-- waypos_tid : natural := 144; -- 14 bits +tlb_erat_rel_d(eratpos_epn TO epn_width-1) <= tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-1) + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_q(eratpos_epn to epn_width-1); +tlb_erat_rel_d(eratpos_x) <= tlb_tag4_way_or(waypos_xbit) + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_q(eratpos_x); +tlb_erat_rel_d(eratpos_size TO eratpos_size+2) <= erat_pgsize(0 to 2) + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_q(eratpos_size to eratpos_size+2); +tlb_erat_rel_d(eratpos_v) <= '1' + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_q(eratpos_v); +tlb_erat_rel_clone_d(eratpos_epn TO epn_width-1) <= tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-1) + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_clone_q(eratpos_epn to epn_width-1); +tlb_erat_rel_clone_d(eratpos_x) <= tlb_tag4_way_or(waypos_xbit) + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_clone_q(eratpos_x); +tlb_erat_rel_clone_d(eratpos_size TO eratpos_size+2) <= erat_pgsize(0 to 2) + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_clone_q(eratpos_size to eratpos_size+2); +tlb_erat_rel_clone_d(eratpos_v) <= '1' + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_clone_q(eratpos_v); +-- mmucr1 11-LRUPEI, 12:13-ICTID/ITTID, 14:15-DCTID/DTTID, 16-DCCD, 17-TLBWE_BINV, 18-TLBI_MSB +-- +-- ERAT reload THDID values +-- TTYPE ITTID DTTID DCCD THDID(0:3) term +----------------------------------------------------------------------- +-- ierat 0 - - TLB_entry.thdid(0:3) (1) +-- ierat 1 - - TLB_entry.tid(2:5) (2) +-- htw inst 0 - - IND entry.thdid(0:3) (3) +-- htw inst 1 - - PTE_reload.pid(2:5) (4) +-- derat - 0 - TLB_entry.thdid(0:3) (1) +-- derat - 1 - TLB_entry.tid(2:5) (2) +-- htw data - 0 - IND entry.thdid(0:3) (3) +-- htw data - 1 - PTE_reload.pid(2:5) (4) +-- +tlb_erat_rel_d(eratpos_thdid TO eratpos_thdid+thdid_width-1) <= + tlb_tag4_way_or(waypos_thdid to waypos_thdid+thdid_width-1) + when ((tlb_tag4_q(tagpos_type_ierat)='1' and tlb_tag4_q(tagpos_type_ptereload)='0' and mmucr1_q(pos_ittid)='0' and tlb_tag4_q(tagpos_ind)='0') or + (tlb_tag4_q(tagpos_type_derat)='1' and tlb_tag4_q(tagpos_type_ptereload)='0' and mmucr1_q(pos_dttid)='0' and tlb_tag4_q(tagpos_ind)='0')) + else tlb_tag4_way_or(waypos_tid+2 to waypos_tid+5) + when ((tlb_tag4_q(tagpos_type_ierat)='1' and tlb_tag4_q(tagpos_type_ptereload)='0' and mmucr1_q(pos_ittid)='1' and tlb_tag4_q(tagpos_ind)='0') or + (tlb_tag4_q(tagpos_type_derat)='1' and tlb_tag4_q(tagpos_type_ptereload)='0' and mmucr1_q(pos_dttid)='1' and tlb_tag4_q(tagpos_ind)='0')) + else (tlb_tag4_q(tagpos_atsel) & tlb_tag4_q(tagpos_esel to tagpos_esel+2)) + when ((tlb_tag4_q(tagpos_type_ierat)='1' and tlb_tag4_q(tagpos_type_ptereload)='1' and mmucr1_q(pos_ittid)='0' and tlb_tag4_q(tagpos_ind)='0') or + (tlb_tag4_q(tagpos_type_derat)='1' and tlb_tag4_q(tagpos_type_ptereload)='1' and mmucr1_q(pos_dttid)='0' and tlb_tag4_q(tagpos_ind)='0')) + else tlb_tag4_q(tagpos_pid+2 to tagpos_pid+5) + when ((tlb_tag4_q(tagpos_type_ierat)='1' and tlb_tag4_q(tagpos_type_ptereload)='1' and mmucr1_q(pos_ittid)='1' and tlb_tag4_q(tagpos_ind)='0') or + (tlb_tag4_q(tagpos_type_derat)='1' and tlb_tag4_q(tagpos_type_ptereload)='1' and mmucr1_q(pos_dttid)='1' and tlb_tag4_q(tagpos_ind)='0')) + else tlb_erat_rel_q(eratpos_thdid to eratpos_thdid+thdid_width-1); +tlb_erat_rel_clone_d(eratpos_thdid TO eratpos_thdid+thdid_width-1) <= + tlb_tag4_way_or(waypos_thdid to waypos_thdid+thdid_width-1) + when ((tlb_tag4_q(tagpos_type_ierat)='1' and tlb_tag4_q(tagpos_type_ptereload)='0' and mmucr1_clone_q(pos_ittid)='0' and tlb_tag4_q(tagpos_ind)='0') or + (tlb_tag4_q(tagpos_type_derat)='1' and tlb_tag4_q(tagpos_type_ptereload)='0' and mmucr1_clone_q(pos_dttid)='0' and tlb_tag4_q(tagpos_ind)='0')) + else tlb_tag4_way_or(waypos_tid+2 to waypos_tid+5) + when ((tlb_tag4_q(tagpos_type_ierat)='1' and tlb_tag4_q(tagpos_type_ptereload)='0' and mmucr1_clone_q(pos_ittid)='1' and tlb_tag4_q(tagpos_ind)='0') or + (tlb_tag4_q(tagpos_type_derat)='1' and tlb_tag4_q(tagpos_type_ptereload)='0' and mmucr1_clone_q(pos_dttid)='1' and tlb_tag4_q(tagpos_ind)='0')) + else (tlb_tag4_q(tagpos_atsel) & tlb_tag4_q(tagpos_esel to tagpos_esel+2)) + when ((tlb_tag4_q(tagpos_type_ierat)='1' and tlb_tag4_q(tagpos_type_ptereload)='1' and mmucr1_clone_q(pos_ittid)='0' and tlb_tag4_q(tagpos_ind)='0') or + (tlb_tag4_q(tagpos_type_derat)='1' and tlb_tag4_q(tagpos_type_ptereload)='1' and mmucr1_clone_q(pos_dttid)='0' and tlb_tag4_q(tagpos_ind)='0')) + else tlb_tag4_q(tagpos_pid+2 to tagpos_pid+5) + when ((tlb_tag4_q(tagpos_type_ierat)='1' and tlb_tag4_q(tagpos_type_ptereload)='1' and mmucr1_clone_q(pos_ittid)='1' and tlb_tag4_q(tagpos_ind)='0') or + (tlb_tag4_q(tagpos_type_derat)='1' and tlb_tag4_q(tagpos_type_ptereload)='1' and mmucr1_clone_q(pos_dttid)='1' and tlb_tag4_q(tagpos_ind)='0')) + else tlb_erat_rel_clone_q(eratpos_thdid to eratpos_thdid+thdid_width-1); +-- mmucr1 11-LRUPEI, 12:13-ICTID/ITTID, 14:15-DCTID/DTTID, 16-DCCD, 17-TLBWE_BINV, 18-TLBI_MSB +-- +-- ERAT reload CLASS values +-- TTYPE ICTID DCTID DCCD CLASS(0:1) term +--------------------------------------------------------------------------- +-- ierat 0 - - TLB_entry.class(0:1) (1) +-- ierat 1 - - TLB_entry.tid(0:1) (2) +-- htw inst 0 - - 00 (4) +-- htw inst 1 - - PTE_reload.pid(0:1) (5) +-- derat non-epid - 0 0 0 & TLB_entry.class(1) (3) +-- derat non-epid - 0 1 TLB_entry.class(0:1) (1) +-- derat non-epid - 1 - TLB_entry.tid(0:1) (2) +-- derat epid load - 0 0 10 (3) +-- derat epid store - 0 0 11 (3) +-- derat epid - 0 1 TLB_entry.class(0:1) (1) +-- derat epid - 1 - TLB_entry.tid(0:1) (2) +-- htw data non-epid - 0 - 00 (4) +-- htw data non-epid - 1 - PTE_reload.pid(0:1) (5) +-- htw data epid load - 0 - 10 (4) +-- htw data epid store - 0 - 11 (4) +-- htw data epid - 1 - PTE_reload.pid(0:1) (5) +-- +-- non-clone is the ierat side +tlb_erat_rel_d(eratpos_class TO eratpos_class+class_width-1) <= + tlb_tag4_way_or(waypos_class to waypos_class+class_width-1) + when tlb_tag4_erat_data_cap='1' and + ((tlb_tag4_q(tagpos_type_ierat)='1' and tlb_tag4_q(tagpos_type_ptereload)='0' and mmucr1_q(pos_ictid)='0' and tlb_tag4_q(tagpos_ind)='0') or + (tlb_tag4_q(tagpos_type_derat)='1' and tlb_tag4_q(tagpos_type_ptereload)='0' and mmucr1_q(pos_dctid)='0' and mmucr1_q(pos_dccd)='1' and tlb_tag4_q(tagpos_ind)='0')) + else tlb_tag4_way_or(waypos_tid+0 to waypos_tid+1) + when tlb_tag4_erat_data_cap='1' and + ((tlb_tag4_q(tagpos_type_ierat)='1' and tlb_tag4_q(tagpos_type_ptereload)='0' and mmucr1_q(pos_ictid)='1' and tlb_tag4_q(tagpos_ind)='0') or + (tlb_tag4_q(tagpos_type_derat)='1' and tlb_tag4_q(tagpos_type_ptereload)='0' and mmucr1_q(pos_dctid)='1' and tlb_tag4_q(tagpos_ind)='0')) + else ( tlb_tag4_q(tagpos_class) & ((tlb_tag4_q(tagpos_class) and tlb_tag4_q(tagpos_class+1)) or (not(tlb_tag4_q(tagpos_class)) and tlb_tag4_way_or(waypos_class+1))) ) + when (tlb_tag4_erat_data_cap='1' and + tlb_tag4_q(tagpos_type_derat)='1' and tlb_tag4_q(tagpos_type_ptereload)='0' and mmucr1_q(pos_dctid)='0' and mmucr1_q(pos_dccd)='0' and tlb_tag4_q(tagpos_ind)='0') + else (tlb_tag4_q(tagpos_class) & (tlb_tag4_q(tagpos_class) and tlb_tag4_q(tagpos_class+1))) + when tlb_tag4_erat_data_cap='1' and + ((tlb_tag4_q(tagpos_type_ierat)='1' and tlb_tag4_q(tagpos_type_ptereload)='1' and mmucr1_q(pos_ictid)='0' and tlb_tag4_q(tagpos_ind)='0') or + (tlb_tag4_q(tagpos_type_derat)='1' and tlb_tag4_q(tagpos_type_ptereload)='1' and mmucr1_q(pos_dctid)='0' and tlb_tag4_q(tagpos_ind)='0')) + else tlb_tag4_q(tagpos_pid+0 to tagpos_pid+1) + when tlb_tag4_erat_data_cap='1' and + ((tlb_tag4_q(tagpos_type_ierat)='1' and tlb_tag4_q(tagpos_type_ptereload)='1' and mmucr1_q(pos_ictid)='1' and tlb_tag4_q(tagpos_ind)='0') or + (tlb_tag4_q(tagpos_type_derat)='1' and tlb_tag4_q(tagpos_type_ptereload)='1' and mmucr1_q(pos_dctid)='1' and tlb_tag4_q(tagpos_ind)='0')) + else tlb_erat_rel_q(eratpos_class to eratpos_class+class_width-1); +-- clone is the derat side +tlb_erat_rel_clone_d(eratpos_class TO eratpos_class+class_width-1) <= + tlb_tag4_way_or(waypos_class to waypos_class+class_width-1) + when tlb_tag4_erat_data_cap='1' and + ((tlb_tag4_q(tagpos_type_ierat)='1' and tlb_tag4_q(tagpos_type_ptereload)='0' and mmucr1_clone_q(pos_ictid)='0' and tlb_tag4_q(tagpos_ind)='0') or + (tlb_tag4_q(tagpos_type_derat)='1' and tlb_tag4_q(tagpos_type_ptereload)='0' and mmucr1_clone_q(pos_dctid)='0' and mmucr1_clone_q(pos_dccd)='1' and tlb_tag4_q(tagpos_ind)='0')) + else tlb_tag4_way_or(waypos_tid+0 to waypos_tid+1) + when tlb_tag4_erat_data_cap='1' and + ((tlb_tag4_q(tagpos_type_ierat)='1' and tlb_tag4_q(tagpos_type_ptereload)='0' and mmucr1_clone_q(pos_ictid)='1' and tlb_tag4_q(tagpos_ind)='0') or + (tlb_tag4_q(tagpos_type_derat)='1' and tlb_tag4_q(tagpos_type_ptereload)='0' and mmucr1_clone_q(pos_dctid)='1' and tlb_tag4_q(tagpos_ind)='0')) + else ( tlb_tag4_q(tagpos_class) & ((tlb_tag4_q(tagpos_class) and tlb_tag4_q(tagpos_class+1)) or (not(tlb_tag4_q(tagpos_class)) and tlb_tag4_way_or(waypos_class+1))) ) + when (tlb_tag4_erat_data_cap='1' and + tlb_tag4_q(tagpos_type_derat)='1' and tlb_tag4_q(tagpos_type_ptereload)='0' and mmucr1_clone_q(pos_dctid)='0' and mmucr1_clone_q(pos_dccd)='0' and tlb_tag4_q(tagpos_ind)='0') + else (tlb_tag4_q(tagpos_class) & (tlb_tag4_q(tagpos_class) and tlb_tag4_q(tagpos_class+1))) + when tlb_tag4_erat_data_cap='1' and + ((tlb_tag4_q(tagpos_type_ierat)='1' and tlb_tag4_q(tagpos_type_ptereload)='1' and mmucr1_clone_q(pos_ictid)='0' and tlb_tag4_q(tagpos_ind)='0') or + (tlb_tag4_q(tagpos_type_derat)='1' and tlb_tag4_q(tagpos_type_ptereload)='1' and mmucr1_clone_q(pos_dctid)='0' and tlb_tag4_q(tagpos_ind)='0')) + else tlb_tag4_q(tagpos_pid+0 to tagpos_pid+1) + when tlb_tag4_erat_data_cap='1' and + ((tlb_tag4_q(tagpos_type_ierat)='1' and tlb_tag4_q(tagpos_type_ptereload)='1' and mmucr1_clone_q(pos_ictid)='1' and tlb_tag4_q(tagpos_ind)='0') or + (tlb_tag4_q(tagpos_type_derat)='1' and tlb_tag4_q(tagpos_type_ptereload)='1' and mmucr1_clone_q(pos_dctid)='1' and tlb_tag4_q(tagpos_ind)='0')) + else tlb_erat_rel_clone_q(eratpos_class to eratpos_class+class_width-1); +-- non-clone is the ierat side +tlb_erat_rel_d(eratpos_extclass TO eratpos_extclass+1) <= tlb_tag4_way_or(waypos_extclass to waypos_extclass+1) + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_q(eratpos_extclass to eratpos_extclass+1); +tlb_erat_rel_d(eratpos_wren) <= '1' when (tlb_tag4_erat_data_cap='1' and + (tlb_tag4_q(tagpos_type_ierat)='1' or tlb_tag4_q(tagpos_type_derat)='1') and + tlb_tag4_q(tagpos_type_ptereload)='0' and tlb_tag4_wayhit_q(tlb_ways)='1' and + tlb_tag4_q(tagpos_wq+1)='0' and tlb_tag4_q(tagpos_ind)='0' and multihit='0' + and or_reduce(tag4_parerr_q(0 to 4))='0') + else '0' when tlb_tag4_erat_data_cap='1' + else tlb_erat_rel_q(eratpos_wren); +tlb_erat_rel_d(eratpos_rpnrsvd TO eratpos_rpnrsvd+3) <= (others => '0'); +tlb_erat_rel_d(eratpos_rpn TO eratpos_rpn+rpn_width-1) <= tlb_tag4_way_or(waypos_rpn to waypos_rpn+rpn_width-1) + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_q(eratpos_rpn to eratpos_rpn+rpn_width-1); +tlb_erat_rel_d(eratpos_r TO eratpos_c) <= tlb_tag4_way_or(waypos_rc to waypos_rc+1) + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_q(eratpos_r to eratpos_c); +tlb_erat_rel_d(eratpos_relsoon) <= ierat_req_taken or ptereload_req_taken or tlb_tag0_type(1); +tlb_erat_rel_d(eratpos_wlc TO eratpos_wlc+1) <= tlb_tag4_way_or(waypos_wlc to waypos_wlc+1) + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_q(eratpos_wlc to eratpos_wlc+1); +tlb_erat_rel_d(eratpos_resvattr) <= tlb_tag4_way_or(waypos_resvattr) + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_q(eratpos_resvattr); +tlb_erat_rel_d(eratpos_vf) <= tlb_tag4_way_or(waypos_vf) + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_q(eratpos_vf); +tlb_erat_rel_d(eratpos_ubits TO eratpos_ubits+3) <= tlb_tag4_way_or(waypos_ubits to waypos_ubits+3) + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_q(eratpos_ubits to eratpos_ubits+3); +tlb_erat_rel_d(eratpos_wimge TO eratpos_wimge+4) <= tlb_tag4_way_or(waypos_wimge to waypos_wimge+4) + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_q(eratpos_wimge to eratpos_wimge+4); +tlb_erat_rel_d(eratpos_usxwr TO eratpos_usxwr+5) <= tlb_tag4_way_or(waypos_usxwr to waypos_usxwr+5) + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_q(eratpos_usxwr to eratpos_usxwr+5); +tlb_erat_rel_d(eratpos_gs) <= tlb_tag4_way_or(waypos_gs) + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_q(eratpos_gs); +tlb_erat_rel_d(eratpos_ts) <= tlb_tag4_way_or(waypos_ts) + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_q(eratpos_ts); +tlb_erat_rel_d(eratpos_tid TO eratpos_tid+pid_width_erat-1) <= tlb_tag4_way_or(waypos_tid+6 to waypos_tid+14-1) + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_q(eratpos_tid to eratpos_tid+pid_width_erat-1); +-- clone is the derat side +tlb_erat_rel_clone_d(eratpos_extclass TO eratpos_extclass+1) <= tlb_tag4_way_or(waypos_extclass to waypos_extclass+1) + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_clone_q(eratpos_extclass to eratpos_extclass+1); +tlb_erat_rel_clone_d(eratpos_wren) <= '1' when (tlb_tag4_erat_data_cap='1' and + (tlb_tag4_q(tagpos_type_ierat)='1' or tlb_tag4_q(tagpos_type_derat)='1') and + tlb_tag4_q(tagpos_type_ptereload)='0' and tlb_tag4_wayhit_q(tlb_ways)='1' and + tlb_tag4_q(tagpos_wq+1)='0' and tlb_tag4_q(tagpos_ind)='0' and multihit='0') + else '0' when tlb_tag4_erat_data_cap='1' + else tlb_erat_rel_clone_q(eratpos_wren); +tlb_erat_rel_clone_d(eratpos_rpnrsvd TO eratpos_rpnrsvd+3) <= (others => '0'); +tlb_erat_rel_clone_d(eratpos_rpn TO eratpos_rpn+rpn_width-1) <= tlb_tag4_way_or(waypos_rpn to waypos_rpn+rpn_width-1) + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_clone_q(eratpos_rpn to eratpos_rpn+rpn_width-1); +tlb_erat_rel_clone_d(eratpos_r TO eratpos_c) <= tlb_tag4_way_or(waypos_rc to waypos_rc+1) + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_clone_q(eratpos_r to eratpos_c); +tlb_erat_rel_clone_d(eratpos_relsoon) <= derat_req_taken or ptereload_req_taken or tlb_tag0_type(0); +tlb_erat_rel_clone_d(eratpos_wlc TO eratpos_wlc+1) <= tlb_tag4_way_or(waypos_wlc to waypos_wlc+1) + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_clone_q(eratpos_wlc to eratpos_wlc+1); +tlb_erat_rel_clone_d(eratpos_resvattr) <= tlb_tag4_way_or(waypos_resvattr) + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_clone_q(eratpos_resvattr); +tlb_erat_rel_clone_d(eratpos_vf) <= tlb_tag4_way_or(waypos_vf) + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_clone_q(eratpos_vf); +tlb_erat_rel_clone_d(eratpos_ubits TO eratpos_ubits+3) <= tlb_tag4_way_or(waypos_ubits to waypos_ubits+3) + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_clone_q(eratpos_ubits to eratpos_ubits+3); +tlb_erat_rel_clone_d(eratpos_wimge TO eratpos_wimge+4) <= tlb_tag4_way_or(waypos_wimge to waypos_wimge+4) + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_clone_q(eratpos_wimge to eratpos_wimge+4); +tlb_erat_rel_clone_d(eratpos_usxwr TO eratpos_usxwr+5) <= tlb_tag4_way_or(waypos_usxwr to waypos_usxwr+5) + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_clone_q(eratpos_usxwr to eratpos_usxwr+5); +tlb_erat_rel_clone_d(eratpos_gs) <= tlb_tag4_way_or(waypos_gs) + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_clone_q(eratpos_gs); +tlb_erat_rel_clone_d(eratpos_ts) <= tlb_tag4_way_or(waypos_ts) + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_clone_q(eratpos_ts); +tlb_erat_rel_clone_d(eratpos_tid TO eratpos_tid+pid_width_erat-1) <= tlb_tag4_way_or(waypos_tid+6 to waypos_tid+14-1) + when tlb_tag4_erat_data_cap='1' else tlb_erat_rel_clone_q(eratpos_tid to eratpos_tid+pid_width_erat-1); +tlb_tag4_erat_data_cap <= '1' when ((tlb_tag4_q(tagpos_type_ierat)='1' or tlb_tag4_q(tagpos_type_derat)='1') and + tlb_tag4_q(tagpos_type_ptereload)='0' and tlb_tag4_q(tagpos_ind)='0' and + (tlb_tag4_wayhit_q(tlb_ways)='1' or or_reduce(tag4_parerr_q(0 to 4))='1') and + (tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not tlb_ctl_tag4_flush)/="0000" ) + else '1' when ((tlb_tag4_q(tagpos_type_ierat)='1' or tlb_tag4_q(tagpos_type_derat)='1') and + tlb_tag4_q(tagpos_type_ptereload)='1' and tlb_tag4_q(tagpos_ind)='0' and + tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000" ) + else '0'; +-- page size 4b to 3b swizzles for erat reloads +erat_pgsize(0 TO 2) <= ERAT_PgSize_1GB when tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_1GB + else ERAT_PgSize_16MB when tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_16MB + else ERAT_PgSize_1MB when tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_1MB + else ERAT_PgSize_64KB when tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_64KB + else ERAT_PgSize_4KB; +-- tagpos_epn : natural := 0; +-- tagpos_pid : natural := 52; -- 14 bits +-- tagpos_is : natural := 66; +-- tagpos_class : natural := 68; +-- tagpos_state : natural := 70; -- state: 0:pr 1:gs 2:as 3:cm +-- tagpos_thdid : natural := 74; +-- tagpos_size : natural := 78; +-- tagpos_type : natural := 82; -- derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload +-- tagpos_lpid : natural := 90; +-- tagpos_ind : natural := 98; +-- tagpos_atsel : natural := 99; +-- tagpos_esel : natural := 100; +-- tagpos_hes : natural := 103; +-- tagpos_wq : natural := 104; +-- tagpos_lrat : natural := 106; +-- tagpos_pt : natural := 107; +-- tagpos_recform : natural := 108; +-- tagpos_endflag : natural := 109; +-- the ierat response +-- ierat threadwise valid +tlb_erat_val_d(0 TO 3) <= (tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) or ierat_tag4_dup_thdid(0 to thdid_width-1)) + when (tlb_tag4_q(tagpos_type_ierat)='1' and tlb_tag4_q(tagpos_type_ptereload)='0' and + tlb_tag4_q(tagpos_ind)='0' and tlb_tag4_wayhit_q(tlb_ways)='1' and + or_reduce(tag4_parerr_q(0 to 4))='0' and + (tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not tlb_ctl_tag4_flush)/="0000") + else tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) + when (tlb_tag4_q(tagpos_type_ierat)='1' and tlb_tag4_q(tagpos_type_ptereload)='0' and + ((tlb_tag4_q(tagpos_endflag)='1' and tlb_tag4_wayhit_q(tlb_ways)='0') or or_reduce(tag4_parerr_q(0 to 4))='1') and + (tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not tlb_ctl_tag4_flush)/="0000") + else tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) + when (tlb_tag4_q(tagpos_type_ierat)='1' and tlb_tag4_q(tagpos_type_ptereload)='1') + else (others => '0'); +tlb_erat_val_d(4) <= tlb_tag4_q(tagpos_type_ierat) + when (tlb_tag4_q(tagpos_type_ptereload)='0' and tlb_tag4_q(tagpos_ind)='0' and + tlb_tag4_wayhit_q(tlb_ways)='1' and multihit='0' and + (tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not tlb_ctl_tag4_flush)/="0000") + else tlb_tag4_q(tagpos_type_ierat) + when (tlb_tag4_q(tagpos_type_ptereload)='1' and tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000") + else '0'; +-- the derat response +-- derat threadwise valid +tlb_erat_val_d(5 TO 8) <= (tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) or derat_tag4_dup_thdid(0 to thdid_width-1)) + when (tlb_tag4_q(tagpos_type_derat)='1' and tlb_tag4_q(tagpos_type_ptereload)='0' and + tlb_tag4_q(tagpos_ind)='0' and tlb_tag4_wayhit_q(tlb_ways)='1' and + or_reduce(tag4_parerr_q(0 to 4))='0' and + (tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not tlb_ctl_tag4_flush)/="0000") + else tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) + when (tlb_tag4_q(tagpos_type_derat)='1' and tlb_tag4_q(tagpos_type_ptereload)='0' and + ((tlb_tag4_q(tagpos_endflag)='1' and tlb_tag4_wayhit_q(tlb_ways)='0') or or_reduce(tag4_parerr_q(0 to 4))='1') and + (tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not tlb_ctl_tag4_flush)/="0000") + else tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) + when (tlb_tag4_q(tagpos_type_derat)='1' and tlb_tag4_q(tagpos_type_ptereload)='1') + else (others => '0'); +tlb_erat_val_d(9) <= tlb_tag4_q(tagpos_type_derat) + when (tlb_tag4_q(tagpos_type_ptereload)='0' and tlb_tag4_q(tagpos_ind)='0' and + tlb_tag4_wayhit_q(tlb_ways)='1' and multihit='0' and + (tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not tlb_ctl_tag4_flush)/="0000") + else tlb_tag4_q(tagpos_type_derat) + when (tlb_tag4_q(tagpos_type_ptereload)='1' and tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000") + else '0'; +-- waypos_epn : natural := 0; +-- waypos_size : natural := 52; +-- waypos_thdid : natural := 56; +-- waypos_class : natural := 60; +-- waypos_extclass : natural := 62; +-- waypos_lpid : natural := 66; +-- waypos_xbit : natural := 84; +-- waypos_rpn : natural := 88; +-- waypos_rc : natural := 118; +-- waypos_wlc : natural := 120; +-- waypos_resvattr : natural := 122; +-- waypos_vf : natural := 123; +-- waypos_ind : natural := 124; +-- waypos_ubits : natural := 125; +-- waypos_wimge : natural := 129; +-- waypos_usxwr : natural := 134; +-- waypos_gs : natural := 140; +-- waypos_ts : natural := 141; +-- waypos_tid : natural := 144; -- 14 bits +-- chosen tag4_way compares to erat requests from mmq_tlb_req for duplicate checking +ierat_req0_tag4_thdid_match <= '1' when or_reduce(tlb_tag4_way_or(waypos_thdid to waypos_thdid+thdid_width-1) and ierat_req0_thdid)='1' else '0'; +ierat_req0_tag4_pid_match <= '1' when (tlb_tag4_way_or(waypos_tid to waypos_tid+pid_width-1)=ierat_req0_pid or or_reduce(tlb_tag4_way_or(waypos_tid to waypos_tid+pid_width-1))='0') + else '0'; +ierat_req0_tag4_as_match <= '1' when (tlb_tag4_way_or(waypos_ts)=ierat_req0_as) else '0'; +ierat_req0_tag4_gs_match <= '1' when (tlb_tag4_way_or(waypos_gs)=ierat_req0_gs) else '0'; +ierat_req0_tag4_epn_match <= '1' when (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-1)=ierat_req0_epn(52-epn_width to 51) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_4KB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-5)=ierat_req0_epn(52-epn_width to 47) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_64KB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-9)=ierat_req0_epn(52-epn_width to 43) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_1MB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-13)=ierat_req0_epn(52-epn_width to 39) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_16MB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-19)=ierat_req0_epn(52-epn_width to 33) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_1GB) + else '0'; +tlb_erat_dup_d(0) <= '1' when (ierat_req0_tag4_pid_match='1' and + ierat_req0_tag4_as_match='1' and ierat_req0_tag4_gs_match='1' and + ierat_req0_tag4_epn_match='1' and ierat_req0_tag4_thdid_match='1' and + ierat_req0_valid='1' and (ierat_req0_nonspec='1' or (tlb_erat_dup_d(4)='0' and tlb_erat_dup_d(5)='1'))) else '0'; +ierat_req1_tag4_thdid_match <= '1' when or_reduce(tlb_tag4_way_or(waypos_thdid to waypos_thdid+thdid_width-1) and ierat_req1_thdid)='1' else '0'; +ierat_req1_tag4_pid_match <= '1' when (tlb_tag4_way_or(waypos_tid to waypos_tid+pid_width-1)=ierat_req1_pid or or_reduce(tlb_tag4_way_or(waypos_tid to waypos_tid+pid_width-1))='0') + else '0'; +ierat_req1_tag4_as_match <= '1' when (tlb_tag4_way_or(waypos_ts)=ierat_req1_as) else '0'; +ierat_req1_tag4_gs_match <= '1' when (tlb_tag4_way_or(waypos_gs)=ierat_req1_gs) else '0'; +ierat_req1_tag4_epn_match <= '1' when (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-1)=ierat_req1_epn(52-epn_width to 51) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_4KB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-5)=ierat_req1_epn(52-epn_width to 47) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_64KB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-9)=ierat_req1_epn(52-epn_width to 43) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_1MB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-13)=ierat_req1_epn(52-epn_width to 39) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_16MB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-19)=ierat_req1_epn(52-epn_width to 33) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_1GB) + else '0'; +tlb_erat_dup_d(1) <= '1' when (ierat_req1_tag4_pid_match='1' and + ierat_req1_tag4_as_match='1' and ierat_req1_tag4_gs_match='1' and + ierat_req1_tag4_epn_match='1' and ierat_req1_tag4_thdid_match='1' and + ierat_req1_valid='1' and (ierat_req1_nonspec='1' or (tlb_erat_dup_d(4)='0' and tlb_erat_dup_d(5)='1'))) else '0'; +ierat_req2_tag4_thdid_match <= '1' when or_reduce(tlb_tag4_way_or(waypos_thdid to waypos_thdid+thdid_width-1) and ierat_req2_thdid)='1' else '0'; +ierat_req2_tag4_pid_match <= '1' when (tlb_tag4_way_or(waypos_tid to waypos_tid+pid_width-1)=ierat_req2_pid or or_reduce(tlb_tag4_way_or(waypos_tid to waypos_tid+pid_width-1))='0') + else '0'; +ierat_req2_tag4_as_match <= '1' when (tlb_tag4_way_or(waypos_ts)=ierat_req2_as) else '0'; +ierat_req2_tag4_gs_match <= '1' when (tlb_tag4_way_or(waypos_gs)=ierat_req2_gs) else '0'; +ierat_req2_tag4_epn_match <= '1' when (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-1)=ierat_req2_epn(52-epn_width to 51) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_4KB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-5)=ierat_req2_epn(52-epn_width to 47) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_64KB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-9)=ierat_req2_epn(52-epn_width to 43) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_1MB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-13)=ierat_req2_epn(52-epn_width to 39) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_16MB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-19)=ierat_req2_epn(52-epn_width to 33) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_1GB) + else '0'; +tlb_erat_dup_d(2) <= '1' when (ierat_req2_tag4_pid_match='1' and + ierat_req2_tag4_as_match='1' and ierat_req2_tag4_gs_match='1' and + ierat_req2_tag4_epn_match='1' and ierat_req2_tag4_thdid_match='1' and + ierat_req2_valid='1' and (ierat_req2_nonspec='1' or (tlb_erat_dup_d(4)='0' and tlb_erat_dup_d(5)='1'))) else '0'; +ierat_req3_tag4_thdid_match <= '1' when or_reduce(tlb_tag4_way_or(waypos_thdid to waypos_thdid+thdid_width-1) and ierat_req3_thdid)='1' else '0'; +ierat_req3_tag4_pid_match <= '1' when (tlb_tag4_way_or(waypos_tid to waypos_tid+pid_width-1)=ierat_req3_pid or or_reduce(tlb_tag4_way_or(waypos_tid to waypos_tid+pid_width-1))='0') + else '0'; +ierat_req3_tag4_as_match <= '1' when (tlb_tag4_way_or(waypos_ts)=ierat_req3_as) else '0'; +ierat_req3_tag4_gs_match <= '1' when (tlb_tag4_way_or(waypos_gs)=ierat_req3_gs) else '0'; +ierat_req3_tag4_epn_match <= '1' when (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-1)=ierat_req3_epn(52-epn_width to 51) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_4KB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-5)=ierat_req3_epn(52-epn_width to 47) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_64KB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-9)=ierat_req3_epn(52-epn_width to 43) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_1MB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-13)=ierat_req3_epn(52-epn_width to 39) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_16MB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-19)=ierat_req3_epn(52-epn_width to 33) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_1GB) + else '0'; +tlb_erat_dup_d(3) <= '1' when (ierat_req3_tag4_pid_match='1' and + ierat_req3_tag4_as_match='1' and ierat_req3_tag4_gs_match='1' and + ierat_req3_tag4_epn_match='1' and ierat_req3_tag4_thdid_match='1' and + ierat_req3_valid='1' and (ierat_req3_nonspec='1' or (tlb_erat_dup_d(4)='0' and tlb_erat_dup_d(5)='1'))) else '0'; +ierat_iu4_tag4_thdid_match <= '1' when or_reduce(tlb_tag4_way_or(waypos_thdid to waypos_thdid+thdid_width-1) and ierat_iu4_thdid)='1' else '0'; +ierat_iu4_tag4_lpid_match <= '1' when (tlb_tag4_way_or(waypos_lpid to waypos_lpid+lpid_width-1)=lpidr or or_reduce(tlb_tag4_way_or(waypos_lpid to waypos_lpid+lpid_width-1))='0') else '0'; +ierat_iu4_tag4_pid_match <= '1' when (tlb_tag4_way_or(waypos_tid to waypos_tid+pid_width-1)=ierat_iu4_pid or or_reduce(tlb_tag4_way_or(waypos_tid to waypos_tid+pid_width-1))='0') else '0'; +ierat_iu4_tag4_as_match <= '1' when (tlb_tag4_way_or(waypos_ts)=ierat_iu4_as) else '0'; +ierat_iu4_tag4_gs_match <= '1' when (tlb_tag4_way_or(waypos_gs)=ierat_iu4_gs) else '0'; +ierat_iu4_tag4_epn_match <= '1' when (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-1)=ierat_iu4_epn(52-epn_width to 51) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_4KB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-5)=ierat_iu4_epn(52-epn_width to 47) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_64KB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-9)=ierat_iu4_epn(52-epn_width to 43) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_1MB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-13)=ierat_iu4_epn(52-epn_width to 39) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_16MB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-19)=ierat_iu4_epn(52-epn_width to 33) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_1GB) + else '0'; +derat_req0_tag4_thdid_match <= '1' when or_reduce(tlb_tag4_way_or(waypos_thdid to waypos_thdid+thdid_width-1) and derat_req0_thdid)='1' else '0'; +derat_req0_tag4_lpid_match <= '1' when (tlb_tag4_way_or(waypos_lpid to waypos_lpid+lpid_width-1)=derat_req0_lpid or or_reduce(tlb_tag4_way_or(waypos_lpid to waypos_lpid+lpid_width-1))='0') + else '0'; +derat_req0_tag4_pid_match <= '1' when (tlb_tag4_way_or(waypos_tid to waypos_tid+pid_width-1)=derat_req0_pid or or_reduce(tlb_tag4_way_or(waypos_tid to waypos_tid+pid_width-1))='0') + else '0'; +derat_req0_tag4_as_match <= '1' when (tlb_tag4_way_or(waypos_ts)=derat_req0_as) else '0'; +derat_req0_tag4_gs_match <= '1' when (tlb_tag4_way_or(waypos_gs)=derat_req0_gs) else '0'; +derat_req0_tag4_epn_match <= '1' when (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-1)=derat_req0_epn(52-epn_width to 51) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_4KB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-5)=derat_req0_epn(52-epn_width to 47) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_64KB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-9)=derat_req0_epn(52-epn_width to 43) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_1MB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-13)=derat_req0_epn(52-epn_width to 39) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_16MB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-19)=derat_req0_epn(52-epn_width to 33) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_1GB) + else '0'; +tlb_erat_dup_d(10) <= '1' when (derat_req0_tag4_lpid_match='1' and derat_req0_tag4_pid_match='1' and + derat_req0_tag4_as_match='1' and derat_req0_tag4_gs_match='1' and + derat_req0_tag4_epn_match='1' and derat_req0_tag4_thdid_match='1' and + derat_req0_valid='1') else '0'; +derat_req1_tag4_thdid_match <= '1' when or_reduce(tlb_tag4_way_or(waypos_thdid to waypos_thdid+thdid_width-1) and derat_req1_thdid)='1' else '0'; +derat_req1_tag4_lpid_match <= '1' when (tlb_tag4_way_or(waypos_lpid to waypos_lpid+lpid_width-1)=derat_req1_lpid or or_reduce(tlb_tag4_way_or(waypos_lpid to waypos_lpid+lpid_width-1))='0') + else '0'; +derat_req1_tag4_pid_match <= '1' when (tlb_tag4_way_or(waypos_tid to waypos_tid+pid_width-1)=derat_req1_pid or or_reduce(tlb_tag4_way_or(waypos_tid to waypos_tid+pid_width-1))='0') + else '0'; +derat_req1_tag4_as_match <= '1' when (tlb_tag4_way_or(waypos_ts)=derat_req1_as) else '0'; +derat_req1_tag4_gs_match <= '1' when (tlb_tag4_way_or(waypos_gs)=derat_req1_gs) else '0'; +derat_req1_tag4_epn_match <= '1' when (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-1)=derat_req1_epn(52-epn_width to 51) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_4KB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-5)=derat_req1_epn(52-epn_width to 47) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_64KB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-9)=derat_req1_epn(52-epn_width to 43) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_1MB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-13)=derat_req1_epn(52-epn_width to 39) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_16MB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-19)=derat_req1_epn(52-epn_width to 33) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_1GB) + else '0'; +tlb_erat_dup_d(11) <= '1' when (derat_req1_tag4_lpid_match='1' and derat_req1_tag4_pid_match='1' and + derat_req1_tag4_as_match='1' and derat_req1_tag4_gs_match='1' and + derat_req1_tag4_epn_match='1' and derat_req1_tag4_thdid_match='1' and + derat_req1_valid='1') else '0'; +derat_req2_tag4_thdid_match <= '1' when or_reduce(tlb_tag4_way_or(waypos_thdid to waypos_thdid+thdid_width-1) and derat_req2_thdid)='1' else '0'; +derat_req2_tag4_lpid_match <= '1' when (tlb_tag4_way_or(waypos_lpid to waypos_lpid+lpid_width-1)=derat_req2_lpid or or_reduce(tlb_tag4_way_or(waypos_lpid to waypos_lpid+lpid_width-1))='0') + else '0'; +derat_req2_tag4_pid_match <= '1' when (tlb_tag4_way_or(waypos_tid to waypos_tid+pid_width-1)=derat_req2_pid or or_reduce(tlb_tag4_way_or(waypos_tid to waypos_tid+pid_width-1))='0') + else '0'; +derat_req2_tag4_as_match <= '1' when (tlb_tag4_way_or(waypos_ts)=derat_req2_as) else '0'; +derat_req2_tag4_gs_match <= '1' when (tlb_tag4_way_or(waypos_gs)=derat_req2_gs) else '0'; +derat_req2_tag4_epn_match <= '1' when (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-1)=derat_req2_epn(52-epn_width to 51) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_4KB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-5)=derat_req2_epn(52-epn_width to 47) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_64KB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-9)=derat_req2_epn(52-epn_width to 43) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_1MB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-13)=derat_req2_epn(52-epn_width to 39) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_16MB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-19)=derat_req2_epn(52-epn_width to 33) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_1GB) + else '0'; +tlb_erat_dup_d(12) <= '1' when (derat_req2_tag4_lpid_match='1' and derat_req2_tag4_pid_match='1' and + derat_req2_tag4_as_match='1' and derat_req2_tag4_gs_match='1' and + derat_req2_tag4_epn_match='1' and derat_req2_tag4_thdid_match='1' and + derat_req2_valid='1') else '0'; +derat_req3_tag4_thdid_match <= '1' when or_reduce(tlb_tag4_way_or(waypos_thdid to waypos_thdid+thdid_width-1) and derat_req3_thdid)='1' else '0'; +derat_req3_tag4_lpid_match <= '1' when (tlb_tag4_way_or(waypos_lpid to waypos_lpid+lpid_width-1)=derat_req3_lpid or or_reduce(tlb_tag4_way_or(waypos_lpid to waypos_lpid+lpid_width-1))='0') + else '0'; +derat_req3_tag4_pid_match <= '1' when (tlb_tag4_way_or(waypos_tid to waypos_tid+pid_width-1)=derat_req3_pid or or_reduce(tlb_tag4_way_or(waypos_tid to waypos_tid+pid_width-1))='0') + else '0'; +derat_req3_tag4_as_match <= '1' when (tlb_tag4_way_or(waypos_ts)=derat_req3_as) else '0'; +derat_req3_tag4_gs_match <= '1' when (tlb_tag4_way_or(waypos_gs)=derat_req3_gs) else '0'; +derat_req3_tag4_epn_match <= '1' when (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-1)=derat_req3_epn(52-epn_width to 51) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_4KB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-5)=derat_req3_epn(52-epn_width to 47) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_64KB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-9)=derat_req3_epn(52-epn_width to 43) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_1MB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-13)=derat_req3_epn(52-epn_width to 39) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_16MB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-19)=derat_req3_epn(52-epn_width to 33) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_1GB) + else '0'; +tlb_erat_dup_d(13) <= '1' when (derat_req3_tag4_lpid_match='1' and derat_req3_tag4_pid_match='1' and + derat_req3_tag4_as_match='1' and derat_req3_tag4_gs_match='1' and + derat_req3_tag4_epn_match='1' and derat_req3_tag4_thdid_match='1' and + derat_req3_valid='1') else '0'; +derat_ex5_tag4_thdid_match <= '1' when or_reduce(tlb_tag4_way_or(waypos_thdid to waypos_thdid+thdid_width-1) and derat_ex5_thdid)='1' else '0'; +derat_ex5_tag4_lpid_match <= '1' when (tlb_tag4_way_or(waypos_lpid to waypos_lpid+lpid_width-1)=derat_ex5_lpid or or_reduce(tlb_tag4_way_or(waypos_lpid to waypos_lpid+lpid_width-1))='0') else '0'; +derat_ex5_tag4_pid_match <= '1' when (tlb_tag4_way_or(waypos_tid to waypos_tid+pid_width-1)=derat_ex5_pid or or_reduce(tlb_tag4_way_or(waypos_tid to waypos_tid+pid_width-1))='0') else '0'; +derat_ex5_tag4_as_match <= '1' when (tlb_tag4_way_or(waypos_ts)=derat_ex5_as) else '0'; +derat_ex5_tag4_gs_match <= '1' when (tlb_tag4_way_or(waypos_gs)=derat_ex5_gs) else '0'; +derat_ex5_tag4_epn_match <= '1' when (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-1)=derat_ex5_epn(52-epn_width to 51) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_4KB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-5)=derat_ex5_epn(52-epn_width to 47) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_64KB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-9)=derat_ex5_epn(52-epn_width to 43) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_1MB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-13)=derat_ex5_epn(52-epn_width to 39) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_16MB) or + (tlb_tag4_way_or(waypos_epn to waypos_epn+epn_width-19)=derat_ex5_epn(52-epn_width to 33) and tlb_tag4_way_or(waypos_size to waypos_size+3)=TLB_PgSize_1GB) + else '0'; +-- tlb_cmp_ierat_dup_val bits 0:3 are req_tag5_match, 4 is tag5 hit_reload, 5 is stretched hit_reload, 6 is ierat iu5 stage dup, 7:9 counter +-- hit pulse to ierat +tlb_erat_dup_d(4) <= tlb_tag4_q(tagpos_type_ierat) + when (tlb_tag4_q(tagpos_type_ptereload)='0' and tlb_tag4_way_or(waypos_ind)='0' and + tlb_tag4_wayhit_q(tlb_ways)='1' and multihit='0' and + tlb_tag4_q(tagpos_wq+1)='0' and or_reduce(tag4_parerr_q(0 to 4))='0') + else '0'; +-- extended duplicate strobe to ierat +tlb_erat_dup_d(5) <= '1' when (tlb_erat_dup_d(4)='1' or tlb_erat_dup_q(4)='1') + else '1' when tlb_erat_dup_q(7 to 9)/="000" + else '0'; +-- ierat duplicate in iu4 stage +tlb_erat_dup_d(6) <= tlb_tag4_q(tagpos_type_ierat) when + (ierat_iu4_tag4_lpid_match='1' and ierat_iu4_tag4_pid_match='1' and + ierat_iu4_tag4_as_match='1' and ierat_iu4_tag4_gs_match='1' and + ierat_iu4_tag4_epn_match='1' and ierat_iu4_tag4_thdid_match='1' and + ierat_iu4_valid='1' and tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000") else '0'; +-- ierat duplicate counter +tlb_erat_dup_d(7 TO 9) <= "001" when (tlb_erat_dup_q(4)='1' and tlb_erat_dup_q(7 to 9)="000") + else "010" when tlb_erat_dup_q(7 to 9)="001" + else "011" when tlb_erat_dup_q(7 to 9)="010" + else "100" when tlb_erat_dup_q(7 to 9)="011" + else "101" when tlb_erat_dup_q(7 to 9)="100" + else "110" when tlb_erat_dup_q(7 to 9)="101" + else "111" when tlb_erat_dup_q(7 to 9)="110" + else "000" when tlb_erat_dup_q(7 to 9)="111" + else tlb_erat_dup_q(7 to 9); +-- tlb_cmp_ierat_dup_val bits 10:13 are req_tag5_match, 14 is tag5 hit_reload, 15 is stretched hit_reload, 16 is ierat iu5 stage dup, 17:19 counter +-- hit pulse to derat +tlb_erat_dup_d(14) <= tlb_tag4_q(tagpos_type_derat) + when (tlb_tag4_q(tagpos_type_ptereload)='0' and tlb_tag4_way_or(waypos_ind)='0' and + tlb_tag4_wayhit_q(tlb_ways)='1' and multihit='0' and + tlb_tag4_q(tagpos_wq+1)='0' and or_reduce(tag4_parerr_q(0 to 4))='0') + else '0'; +-- extended duplicate strobe to derat +tlb_erat_dup_d(15) <= '1' when (tlb_erat_dup_d(14)='1' or tlb_erat_dup_q(14)='1') + else '1' when tlb_erat_dup_q(17 to 19)/="000" + else '0'; +-- derat duplicate in ex5 stage +tlb_erat_dup_d(16) <= tlb_tag4_q(tagpos_type_derat) when + (derat_ex5_tag4_lpid_match='1' and derat_ex5_tag4_pid_match='1' and + derat_ex5_tag4_as_match='1' and derat_ex5_tag4_gs_match='1' and + derat_ex5_tag4_epn_match='1' and derat_ex5_tag4_thdid_match='1' and + derat_ex5_valid='1' and tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000") else '0'; +-- derat duplicate hit counter +tlb_erat_dup_d(17 TO 19) <= "001" when (tlb_erat_dup_q(14)='1' and tlb_erat_dup_q(17 to 19)="000") + else "010" when tlb_erat_dup_q(17 to 19)="001" + else "011" when tlb_erat_dup_q(17 to 19)="010" + else "100" when tlb_erat_dup_q(17 to 19)="011" + else "101" when tlb_erat_dup_q(17 to 19)="100" + else "110" when tlb_erat_dup_q(17 to 19)="101" + else "111" when tlb_erat_dup_q(17 to 19)="110" + else "000" when tlb_erat_dup_q(17 to 19)="111" + else tlb_erat_dup_q(17 to 19); +-- used in erat reload thdid to invalidate existing duplicates +ierat_tag4_dup_thdid <= ((0 to 3 => tlb_erat_dup_d(0)) and ierat_req0_thdid(0 to 3) and (0 to 3 => ierat_req0_nonspec) and (0 to 3 => not tlb_tag4_q(tagpos_wq+1))) or + ((0 to 3 => tlb_erat_dup_d(1)) and ierat_req1_thdid(0 to 3) and (0 to 3 => ierat_req1_nonspec) and (0 to 3 => not tlb_tag4_q(tagpos_wq+1))) or + ((0 to 3 => tlb_erat_dup_d(2)) and ierat_req2_thdid(0 to 3) and (0 to 3 => ierat_req2_nonspec) and (0 to 3 => not tlb_tag4_q(tagpos_wq+1))) or + ((0 to 3 => tlb_erat_dup_d(3)) and ierat_req3_thdid(0 to 3) and (0 to 3 => ierat_req3_nonspec) and (0 to 3 => not tlb_tag4_q(tagpos_wq+1))); +derat_tag4_dup_thdid <= ((0 to 3 => tlb_erat_dup_d(10)) and derat_req0_thdid(0 to 3) and (0 to 3 => not tlb_tag4_q(tagpos_wq+1))) or + ((0 to 3 => tlb_erat_dup_d(11)) and derat_req1_thdid(0 to 3) and (0 to 3 => not tlb_tag4_q(tagpos_wq+1))) or + ((0 to 3 => tlb_erat_dup_d(12)) and derat_req2_thdid(0 to 3) and (0 to 3 => not tlb_tag4_q(tagpos_wq+1))) or + ((0 to 3 => tlb_erat_dup_d(13)) and derat_req3_thdid(0 to 3) and (0 to 3 => not tlb_tag4_q(tagpos_wq+1))); +tlb_tag4_epcr_dgtmi <= or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and xu_mm_epcr_dgtmi); +tlb_tag4_size_not_supp <= '0' when (tlb_tag4_q(tagpos_size to tagpos_size+3)=TLB_PgSize_4KB or tlb_tag4_q(tagpos_size to tagpos_size+3)=TLB_PgSize_64KB or + tlb_tag4_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1MB or tlb_tag4_q(tagpos_size to tagpos_size+3)=TLB_PgSize_16MB or + tlb_tag4_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1GB or + (tlb_tag4_q(tagpos_size to tagpos_size+3)=TLB_PgSize_256MB and tlb_tag4_q(tagpos_ind)='1')) else '1'; +-- tell the XU that the derat miss is done, and release the thread hold(s) +eratmiss_done_d <= tlb_erat_val_q(0 to 3) or tlb_erat_val_q(5 to 8); +tlb_miss_d <= tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) + when ((tlb_tag4_q(tagpos_type_ierat)='1' or tlb_tag4_q(tagpos_type_derat)='1') and tlb_tag4_q(tagpos_type_ptereload)='0' and + tlb_tag4_q(tagpos_endflag)='1' and tlb_tag4_wayhit_q(0 to 3) = "0000" + and or_reduce(tag4_parerr_q(0 to 4))='0') + else (others => '0'); +-- Event | Exceptions +-- | PT fault | TLB Inelig | LRAT miss +---------------------------------------------------------- +-- tlbwe | - | hv_priv=1 | lrat_miss=1 +-- | | tlbi=1 | esr_pt=0 +-- | | esr_pt=0 | +---------------------------------------------------------- +-- ptereload | DSI | DSI | lrat_miss=1 +-- (data) | pt_fault=1 | tlbi=1 | esr_pt=1 +-- | PT=1 | esr_pt=0 ? | esr_data=1 +-- | | | esr_epid=class(0) +-- | | | esr_st=class(1) +---------------------------------------------------------- +-- ptereload | ISI | ISI | lrat_miss=1 +-- (inst) | pt_fault=1 | tlbi=1 | esr_pt=1 +-- | PT=1 | esr_pt=0 ? | esr_data=0 +---------------------------------------------------------- +-- unused tagpos_is def is mas1_v, mas1_iprot for tlbwe, and is pte.valid & 0 for ptereloads +tlb_inelig_d <= tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) + when (tlb_tag4_q(tagpos_type_ptereload)='1' and tlb_tag4_q(tagpos_is)='1' and lru_tag4_dataout_q(0 to 3)="1111" and lru_tag4_dataout_q(8 to 11)="1111") + or (tlb_tag4_q(tagpos_type_ptereload)='1' and tlb_tag4_q(tagpos_is)='1' and tlb_tag4_size_not_supp='1') + or (tlb_tag4_q(tagpos_type_ptereload)='1' and tlb_tag4_q(tagpos_is)='1' and tlb_tag4_q(tagpos_pt)='0') + else (others => '0'); +lrat_miss_d <= (tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag4_flush)) + when ( ((or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and tlb_resv_match_vec)='1' + and tlb_tag4_q(tagpos_wq to tagpos_wq+1)="01" and mmucfg_twc='1') + or tlb_tag4_q(tagpos_wq to tagpos_wq+1)="00" or tlb_tag4_q(tagpos_wq to tagpos_wq+1)="11") and + tlb_tag4_q(tagpos_type_tlbwe)='1' and tlb_tag4_q(tagpos_gs)='1' and tlb_tag4_q(tagpos_pr)='0' and + tlb_tag4_epcr_dgtmi='0' and mmucfg_lrat='1' and + tlb_tag4_q(tagpos_is)='1' and lrat_tag4_hit_status(0 to 3)/="1100" ) + else tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) + when (tlb_tag4_q(tagpos_type_ptereload)='1' and tlb_tag4_q(tagpos_gs)='1' and mmucfg_lrat='1' and + tlb_tag4_q(tagpos_is)='1' and lrat_tag4_hit_status(0 to 3)/="1100" and + tlb_tag4_q(tagpos_wq to tagpos_wq+1)="10" and + tlb_tag4_q(tagpos_pt)='1') + else (others => '0'); +pt_fault_d <= tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) + when ( tlb_tag4_q(tagpos_type_ptereload)='1' and tlb_tag4_q(tagpos_is)='0' and + tlb_tag4_q(tagpos_wq to tagpos_wq+1)="10" and + tlb_tag4_q(tagpos_pt)='1' ) + else (others => '0'); +-- unused tagpos_is def is mas1_v, mas1_iprot for tlbwe, and is (pte.valid & 0) for ptereloads +-- E.HV Privilege exceptions: +-- 1. guest sup executes tlbre, tlbsx, tlbivax, eratre, eratwe, eratsx, eratilx, or erativax (xu_cpl handles) +-- 2. guest sup executes mtspr or mfspr to a hv priviledged spr (xu_cpl handles) +-- 3. guest sup executes tlbwe, tlbsrx, or tlbilx with EPCR DGTMI =1 (xu_cpl handles) +-- 4. guest sup executes cache locking op when MSRP UCLEP =1 (xu_cpl handles) +-- 5. guest sup tlbwe when TLB0CFG GTWE =0 +-- 6. guest sup tlbwe when MMUCFG LRAT =0 +-- 7. guest sup tlbwe when MAS0 HES =1 and TLBE V =1 and TLBE IPROT =1 and (MAS0 WQ =00 or MAS0 WQ =11 or (MAS0 WQ =01 and resv. exists)), +-- except when write cond. not allowed by reservation is impl. depend. +-- 8. guest sup tlbwe when MAS0 HES =1 and MAS1 IPROT =1 and(MAS0 WQ =00 or MAS0 WQ =11 or (MAS0 WQ =01 and resv. exists)), +-- except when write cond. not allowed by reservation is impl. depend. +-- 9. guest sup tlbwe when MAS0 HES =0 and MAS0 WQ /=10 +-- 10. guest sup tlbwe when MAS0 HES =1 and MAS1 V =0 ??? -> random lru way invalidates allowed by current 2.06 ISA +-- ..this is a possible security hole..FSL considering RFC to allow hvpriv except +-- 11. guest sup tlbilx with MAS5 SGS =0 ??? -> should be protected via mas5 and mas8 are hv priv spr's +hv_priv_d <= (tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag4_flush)) + when ( tlb_tag4_q(tagpos_type_tlbwe)='1' and tlb_tag4_q(tagpos_gs)='1' and tlb_tag4_q(tagpos_pr)='0' and tlb0cfg_gtwe='0' ) or + ( tlb_tag4_q(tagpos_type_tlbwe)='1' and tlb_tag4_q(tagpos_gs)='1' and tlb_tag4_q(tagpos_pr)='0' and mmucfg_lrat='0' ) or + + ( tlb_tag4_q(tagpos_type_tlbwe)='1' and tlb_tag4_q(tagpos_gs)='1' and tlb_tag4_q(tagpos_pr)='0' and tlb_tag4_q(tagpos_hes)='1' + and (tlb_tag4_q(tagpos_wq to tagpos_wq+1)="00" or tlb_tag4_q(tagpos_wq to tagpos_wq+1)="11" or + (tlb_tag4_q(tagpos_wq to tagpos_wq+1)="01" and (or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and tlb_resv_match_vec)='1'))) and + ((lru_tag4_dataout_q(0)='1' and lru_tag4_dataout_q(4 to 5)="00" and lru_tag4_dataout_q(8)='1') or + (lru_tag4_dataout_q(1)='1' and lru_tag4_dataout_q(4 to 5)="01" and lru_tag4_dataout_q(9)='1') or + (lru_tag4_dataout_q(2)='1' and lru_tag4_dataout_q(4)='1' and lru_tag4_dataout_q(6)='0' and lru_tag4_dataout_q(10)='1') or + (lru_tag4_dataout_q(3)='1' and lru_tag4_dataout_q(4)='1' and lru_tag4_dataout_q(6)='1' and lru_tag4_dataout_q(11)='1')) ) or + ( tlb_tag4_q(tagpos_type_tlbwe)='1' and tlb_tag4_q(tagpos_gs)='1' and tlb_tag4_q(tagpos_pr)='0' and tlb_tag4_q(tagpos_hes)='1' + and (tlb_tag4_q(tagpos_wq to tagpos_wq+1)="00" or tlb_tag4_q(tagpos_wq to tagpos_wq+1)="11" or + (tlb_tag4_q(tagpos_wq to tagpos_wq+1)="01" and (or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and tlb_resv_match_vec)='1'))) and + tlb_tag4_q(tagpos_is+1)='1' ) or + + ( tlb_tag4_q(tagpos_type_tlbwe)='1' and tlb_tag4_q(tagpos_gs)='1' and tlb_tag4_q(tagpos_pr)='0' and tlb_tag4_q(tagpos_hes)='0' and tlb_tag4_q(tagpos_wq to tagpos_wq+1)/="10") + + else (others => '0'); +esr_pt_d <= (pt_fault_d or lrat_miss_d) and (0 to 3 => tlb_tag4_q(tagpos_type_ptereload)); +esr_data_d <= (tlb_miss_d or pt_fault_d or tlb_inelig_d or lrat_miss_d) and (0 to 3 => tlb_tag4_q(tagpos_type_derat)); +esr_st_d <= (tlb_miss_d or pt_fault_d or tlb_inelig_d or lrat_miss_d) and (0 to 3 => tlb_tag4_q(tagpos_type_derat)) and (0 to 3 => tlb_tag4_q(tagpos_class+1)); +esr_epid_d <= (tlb_miss_d or pt_fault_d or tlb_inelig_d or lrat_miss_d) and (0 to 3 => tlb_tag4_q(tagpos_type_derat)) and (0 to 3 => tlb_tag4_q(tagpos_class)); +cr0_eq_d <= tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) + when ( (tlb_tag4_q(tagpos_type_tlbsrx)='1' or (tlb_tag4_q(tagpos_type_tlbsx)='1' and tlb_tag4_q(tagpos_recform)='1')) and + tlb_tag4_wayhit_q(tlb_ways)='1' and multihit='0' and or_reduce(tag4_parerr_q(0 to 4))='0' ) + else (others => '0'); +cr0_eq_valid_d <= tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) + when ( (tlb_tag4_q(tagpos_type_tlbsrx)='1' or (tlb_tag4_q(tagpos_type_tlbsx)='1' and tlb_tag4_q(tagpos_recform)='1')) and + (tlb_tag4_q(tagpos_endflag)='1' or (tlb_tag4_wayhit_q(tlb_ways)='1' and multihit='0')) and or_reduce(tag4_parerr_q(0 to 4))='0' ) + else (others => '0'); +tlb_multihit_err_d <= tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) + when ( ((tlb_tag4_q(tagpos_type_derat to tagpos_type_ierat)/="00" and tlb_tag4_q(tagpos_type_ptereload)='0') or + (tlb_tag4_q(tagpos_type_tlbsx to tagpos_type_tlbsrx)/="00")) and + multihit='1' and (tlb_tag4_q(tagpos_endflag)='1' or tlb_tag4_wayhit_q(tlb_ways)='1')) + else (others => '0'); +parerr_gen0: if check_parity = 0 generate +tlb_par_err_d <= tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) + and (0 to 3 => tag4_parerr_q(0) and not(tag4_parerr_q(0)) and or_reduce(tlb_tag4_q(tagpos_type_derat to tagpos_type_tlbre))); +lru_par_err_d <= tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) + and (0 to 3 => tag4_parerr_q(2) and not(tag4_parerr_q(2)) and or_reduce(tlb_tag4_q(tagpos_type_derat to tagpos_type_tlbre))); +tlb_tag4_tlbre_parerr <= '0'; +ECO107332_tlb_par_err_d <= tlb_par_err_d; +ECO107332_lru_par_err_d <= lru_par_err_d; +end generate parerr_gen0; +parerr_gen1: if check_parity = 1 generate +tlb_par_err_d <= tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) + and ( 0 to 3 => (or_reduce(tag4_parerr_q(0 to 3)) and or_reduce(tlb_tag4_q(tagpos_type_derat to tagpos_type_tlbsrx))) or + (tag4_parerr_q(0) and tlb_tag4_q(tagpos_type_tlbre) and not tlb_tag4_q(tagpos_esel+1) and not tlb_tag4_q(tagpos_esel+2)) or + (tag4_parerr_q(1) and tlb_tag4_q(tagpos_type_tlbre) and not tlb_tag4_q(tagpos_esel+1) and tlb_tag4_q(tagpos_esel+2)) or + (tag4_parerr_q(2) and tlb_tag4_q(tagpos_type_tlbre) and tlb_tag4_q(tagpos_esel+1) and not tlb_tag4_q(tagpos_esel+2)) or + (tag4_parerr_q(3) and tlb_tag4_q(tagpos_type_tlbre) and tlb_tag4_q(tagpos_esel+1) and tlb_tag4_q(tagpos_esel+2)) ); +lru_par_err_d <= tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) + and (0 to 3 => tag4_parerr_q(4) and (or_reduce(tlb_tag4_q(tagpos_type_derat to tagpos_type_tlbsrx)) or tlb_tag4_q(tagpos_type_tlbre))); +ECO107332_tlb_par_err_d <= tlb_par_err_d and not(tlb_ctl_tag4_flush); +ECO107332_lru_par_err_d <= lru_par_err_d and not(tlb_ctl_tag4_flush); +tlb_tag4_tlbre_parerr <= (tag4_parerr_q(0) and tlb_tag4_q(tagpos_type_tlbre) and not tlb_tag4_q(tagpos_esel+1) and not tlb_tag4_q(tagpos_esel+2)) or + (tag4_parerr_q(1) and tlb_tag4_q(tagpos_type_tlbre) and not tlb_tag4_q(tagpos_esel+1) and tlb_tag4_q(tagpos_esel+2)) or + (tag4_parerr_q(2) and tlb_tag4_q(tagpos_type_tlbre) and tlb_tag4_q(tagpos_esel+1) and not tlb_tag4_q(tagpos_esel+2)) or + (tag4_parerr_q(3) and tlb_tag4_q(tagpos_type_tlbre) and tlb_tag4_q(tagpos_esel+1) and tlb_tag4_q(tagpos_esel+2)) or + (tag4_parerr_q(4) and tlb_tag4_q(tagpos_type_tlbre)); +end generate parerr_gen1; +tlb_tag5_except_d <= (hv_priv_d or lrat_miss_d or tlb_inelig_d or pt_fault_d or + tlb_multihit_err_d or tlb_par_err_d or lru_par_err_d); +-- these are spares for exceptions +tlb_isi_d <= tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) + when (tlb_tag4_q(tagpos_type_ierat)='1' and tlb_tag4_q(tagpos_type_ptereload)='0' and + tlb_tag4_wayhit_q(0 to 3) = "0000" and tlb_tag4_q(tagpos_endflag)='1') + else (others => '0'); +tlb_dsi_d <= tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) + when (tlb_tag4_q(tagpos_type_derat)='1' and tlb_tag4_q(tagpos_type_ptereload)='0' and + tlb_tag4_wayhit_q(0 to 3) = "0000" and tlb_tag4_q(tagpos_endflag)='1') + else (others => '0'); +-- tlb_low_data +-- 0:51 - EPN +-- 52:55 - SIZE (4b) +-- 56:59 - ThdID +-- 60:61 - Class +-- 62:63 - ExtClass +-- 64:65 - reserved (2b) +-- 66:73 - 8b for LPID +-- 74:83 - parity 10bits +-- tlb_high_data +-- 84 - 0 - X-bit +-- 85:87 - 1:3 - reserved (3b) +-- 88:117 - 4:33 - RPN (30b) +-- 118:119 - 34:35 - R,C +-- 120:121 - 36:37 - WLC (2b) +-- 122 - 38 - ResvAttr +-- 123 - 39 - VF +-- 124 - 40 - IND +-- 125:128 - 41:44 - U0-U3 +-- 129:133 - 45:49 - WIMGE +-- 134:136 - 50:52 - UX,UW,UR +-- 137:139 - 53:55 - SX,SW,SR +-- 140 - 56 - GS +-- 141 - 57 - TS +-- 142:143 - 58:59 - reserved (2b) +-- 144:149 - 60:65 - 6b TID msbs +-- 150:157 - 66:73 - 8b TID lsbs +-- 158:167 - 74:83 - parity 10bits +-- tagpos_epn : natural := 0; +-- tagpos_pid : natural := 52; -- 14 bits +-- tagpos_is : natural := 66; +-- tagpos_class : natural := 68; +-- tagpos_state : natural := 70; -- state: 0:pr 1:gs 2:as 3:cm +-- tagpos_thdid : natural := 74; +-- tagpos_size : natural := 78; +-- tagpos_type : natural := 82; -- derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload +-- tagpos_lpid : natural := 90; +-- tagpos_ind : natural := 98; +-- tagpos_atsel : natural := 99; +-- tagpos_esel : natural := 100; +-- tagpos_hes : natural := 103; +-- tagpos_wq : natural := 104; +-- tagpos_lrat : natural := 106; lrat for tlbwe enabled +-- tagpos_pt : natural := 107; tlb can be loaded from page table (hwt enabled) +-- tagpos_recform : natural := 108; +-- tagpos_endflag : natural := 109; +-- waypos_epn : natural := 0; +-- waypos_size : natural := 52; +-- waypos_thdid : natural := 56; +-- waypos_class : natural := 60; +-- waypos_extclass : natural := 62; +-- waypos_lpid : natural := 66; +-- waypos_xbit : natural := 84; +-- waypos_rpn : natural := 88; +-- waypos_rc : natural := 118; +-- waypos_wlc : natural := 120; +-- waypos_resvattr : natural := 122; +-- waypos_vf : natural := 123; +-- waypos_ind : natural := 124; +-- waypos_ubits : natural := 125; +-- waypos_wimge : natural := 129; +-- waypos_usxwr : natural := 134; +-- waypos_gs : natural := 140; +-- waypos_ts : natural := 141; +-- waypos_tid : natural := 144; -- 14 bits +-- these are tag3 phase components +matchline_comb0 : mmq_tlb_matchline + generic map (have_xbit => 1, num_pgsizes => 5, have_cmpmask => 1, cmpmask_width => 5) + port map ( + vdd => vdd, + gnd => gnd, + addr_in => tlb_tag3_clone1_q(tagpos_epn to tagpos_epn+epn_width-1), + addr_enable => addr_enable, + comp_pgsize => tlb_tag3_clone1_q(tagpos_size to tagpos_size+3), + pgsize_enable => pgsize_enable, + entry_size => tlb_way0_q(waypos_size to waypos_size+3), + entry_cmpmask => tlb_way0_cmpmask_q, + entry_xbit => tlb_way0_q(waypos_xbit), + entry_xbitmask => tlb_way0_xbitmask_q, + entry_epn => tlb_way0_q(waypos_epn to waypos_epn+epn_width-1), + comp_class => tlb_tag3_clone1_q(tagpos_class to tagpos_class+1), + entry_class => tlb_way0_q(waypos_class to waypos_class+1), + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => tlb_way0_q(waypos_extclass to waypos_extclass+1), + extclass_enable => extclass_enable, + comp_state => tlb_tag3_clone1_q(tagpos_state+1 to tagpos_state+2), + entry_gs => tlb_way0_q(waypos_gs), + entry_ts => tlb_way0_q(waypos_ts), + state_enable => state_enable, + entry_thdid => tlb_way0_q(waypos_thdid to waypos_thdid+thdid_width-1), + comp_thdid => tlb_tag3_clone1_q(tagpos_thdid to tagpos_thdid+thdid_width-1), + thdid_enable => thdid_enable, + entry_pid => tlb_way0_q(waypos_tid to waypos_tid+pid_width-1), + comp_pid => tlb_tag3_clone1_q(tagpos_pid to tagpos_pid+pid_width-1), + pid_enable => pid_enable, + entry_lpid => tlb_way0_q(waypos_lpid to waypos_lpid+lpid_width-1), + comp_lpid => tlb_tag3_clone1_q(tagpos_lpid to tagpos_lpid+lpid_width-1), + lpid_enable => lpid_enable, + entry_ind => tlb_way0_q(waypos_ind), + comp_ind => comp_ind, + ind_enable => ind_enable, + entry_iprot => lru_tag3_dataout_q(8), + comp_iprot => comp_iprot, + iprot_enable => iprot_enable, + entry_v => lru_tag3_dataout_q(0), + comp_invalidate => tlb_tag3_clone1_q(tagpos_type_snoop), + + match => tlb_wayhit(0), + dbg_addr_match => tlb_way0_addr_match, + dbg_pgsize_match => tlb_way0_pgsize_match, + dbg_class_match => tlb_way0_class_match, + dbg_extclass_match => tlb_way0_extclass_match, + dbg_state_match => tlb_way0_state_match, + dbg_thdid_match => tlb_way0_thdid_match, + dbg_pid_match => tlb_way0_pid_match, + dbg_lpid_match => tlb_way0_lpid_match, + dbg_ind_match => tlb_way0_ind_match, + dbg_iprot_match => tlb_way0_iprot_match + ); +matchline_comb1 : mmq_tlb_matchline + generic map (have_xbit => 1, num_pgsizes => 5, have_cmpmask => 1, cmpmask_width => 5) + port map ( + vdd => vdd, + gnd => gnd, + addr_in => tlb_tag3_clone1_q(tagpos_epn to tagpos_epn+epn_width-1), + addr_enable => addr_enable, + comp_pgsize => tlb_tag3_clone1_q(tagpos_size to tagpos_size+3), + pgsize_enable => pgsize_enable, + entry_size => tlb_way1_q(waypos_size to waypos_size+3), + entry_cmpmask => tlb_way1_cmpmask_q, + entry_xbit => tlb_way1_q(waypos_xbit), + entry_xbitmask => tlb_way1_xbitmask_q, + entry_epn => tlb_way1_q(waypos_epn to waypos_epn+epn_width-1), + comp_class => tlb_tag3_clone1_q(tagpos_class to tagpos_class+1), + entry_class => tlb_way1_q(waypos_class to waypos_class+1), + class_enable => class_enable, + comp_extclass => comp_extclass, + entry_extclass => tlb_way1_q(waypos_extclass to waypos_extclass+1), + extclass_enable => extclass_enable, + comp_state => tlb_tag3_clone1_q(tagpos_state+1 to tagpos_state+2), + entry_gs => tlb_way1_q(waypos_gs), + entry_ts => tlb_way1_q(waypos_ts), + state_enable => state_enable, + entry_thdid => tlb_way1_q(waypos_thdid to waypos_thdid+thdid_width-1), + comp_thdid => tlb_tag3_clone1_q(tagpos_thdid to tagpos_thdid+thdid_width-1), + thdid_enable => thdid_enable, + entry_pid => tlb_way1_q(waypos_tid to waypos_tid+pid_width-1), + comp_pid => tlb_tag3_clone1_q(tagpos_pid to tagpos_pid+pid_width-1), + pid_enable => pid_enable, + entry_lpid => tlb_way1_q(waypos_lpid to waypos_lpid+lpid_width-1), + comp_lpid => tlb_tag3_clone1_q(tagpos_lpid to tagpos_lpid+lpid_width-1), + lpid_enable => lpid_enable, + entry_ind => tlb_way1_q(waypos_ind), + comp_ind => comp_ind, + ind_enable => ind_enable, + entry_iprot => lru_tag3_dataout_q(9), + comp_iprot => comp_iprot, + iprot_enable => iprot_enable, + entry_v => lru_tag3_dataout_q(1), + comp_invalidate => tlb_tag3_clone1_q(tagpos_type_snoop), + + match => tlb_wayhit(1), + dbg_addr_match => tlb_way1_addr_match, + dbg_pgsize_match => tlb_way1_pgsize_match, + dbg_class_match => tlb_way1_class_match, + dbg_extclass_match => tlb_way1_extclass_match, + dbg_state_match => tlb_way1_state_match, + dbg_thdid_match => tlb_way1_thdid_match, + dbg_pid_match => tlb_way1_pid_match, + dbg_lpid_match => tlb_way1_lpid_match, + dbg_ind_match => tlb_way1_ind_match, + dbg_iprot_match => tlb_way1_iprot_match + ); +matchline_comb2 : mmq_tlb_matchline + generic map (have_xbit => 1, num_pgsizes => 5, have_cmpmask => 1, cmpmask_width => 5) + port map ( + vdd => vdd, + gnd => gnd, + addr_in => tlb_tag3_clone2_q(tagpos_epn to tagpos_epn+epn_width-1), + addr_enable => addr_enable_clone, + comp_pgsize => tlb_tag3_clone2_q(tagpos_size to tagpos_size+3), + pgsize_enable => pgsize_enable_clone, + entry_size => tlb_way2_q(waypos_size to waypos_size+3), + entry_cmpmask => tlb_way2_cmpmask_q, + entry_xbit => tlb_way2_q(waypos_xbit), + entry_xbitmask => tlb_way2_xbitmask_q, + entry_epn => tlb_way2_q(waypos_epn to waypos_epn+epn_width-1), + comp_class => tlb_tag3_clone2_q(tagpos_class to tagpos_class+1), + entry_class => tlb_way2_q(waypos_class to waypos_class+1), + class_enable => class_enable_clone, + comp_extclass => comp_extclass_clone, + entry_extclass => tlb_way2_q(waypos_extclass to waypos_extclass+1), + extclass_enable => extclass_enable_clone, + comp_state => tlb_tag3_clone2_q(tagpos_state+1 to tagpos_state+2), + entry_gs => tlb_way2_q(waypos_gs), + entry_ts => tlb_way2_q(waypos_ts), + state_enable => state_enable_clone, + entry_thdid => tlb_way2_q(waypos_thdid to waypos_thdid+thdid_width-1), + comp_thdid => tlb_tag3_clone2_q(tagpos_thdid to tagpos_thdid+thdid_width-1), + thdid_enable => thdid_enable_clone, + entry_pid => tlb_way2_q(waypos_tid to waypos_tid+pid_width-1), + comp_pid => tlb_tag3_clone2_q(tagpos_pid to tagpos_pid+pid_width-1), + pid_enable => pid_enable_clone, + entry_lpid => tlb_way2_q(waypos_lpid to waypos_lpid+lpid_width-1), + comp_lpid => tlb_tag3_clone2_q(tagpos_lpid to tagpos_lpid+lpid_width-1), + lpid_enable => lpid_enable_clone, + entry_ind => tlb_way2_q(waypos_ind), + comp_ind => comp_ind_clone, + ind_enable => ind_enable_clone, + entry_iprot => lru_tag3_dataout_q(10), + comp_iprot => comp_iprot_clone, + iprot_enable => iprot_enable_clone, + entry_v => lru_tag3_dataout_q(2), + comp_invalidate => tlb_tag3_clone2_q(tagpos_type_snoop), + + match => tlb_wayhit(2), + + dbg_addr_match => tlb_way2_addr_match, + dbg_pgsize_match => tlb_way2_pgsize_match, + dbg_class_match => tlb_way2_class_match, + dbg_extclass_match => tlb_way2_extclass_match, + dbg_state_match => tlb_way2_state_match, + dbg_thdid_match => tlb_way2_thdid_match, + dbg_pid_match => tlb_way2_pid_match, + dbg_lpid_match => tlb_way2_lpid_match, + dbg_ind_match => tlb_way2_ind_match, + dbg_iprot_match => tlb_way2_iprot_match + ); +matchline_comb3 : mmq_tlb_matchline + generic map (have_xbit => 1, num_pgsizes => 5, have_cmpmask => 1, cmpmask_width => 5) + port map ( + vdd => vdd, + gnd => gnd, + addr_in => tlb_tag3_clone2_q(tagpos_epn to tagpos_epn+epn_width-1), + addr_enable => addr_enable_clone, + comp_pgsize => tlb_tag3_clone2_q(tagpos_size to tagpos_size+3), + pgsize_enable => pgsize_enable_clone, + entry_size => tlb_way3_q(waypos_size to waypos_size+3), + entry_cmpmask => tlb_way3_cmpmask_q, + entry_xbit => tlb_way3_q(waypos_xbit), + entry_xbitmask => tlb_way3_xbitmask_q, + entry_epn => tlb_way3_q(waypos_epn to waypos_epn+epn_width-1), + comp_class => tlb_tag3_clone2_q(tagpos_class to tagpos_class+1), + entry_class => tlb_way3_q(waypos_class to waypos_class+1), + class_enable => class_enable_clone, + comp_extclass => comp_extclass_clone, + entry_extclass => tlb_way3_q(waypos_extclass to waypos_extclass+1), + extclass_enable => extclass_enable_clone, + comp_state => tlb_tag3_clone2_q(tagpos_state+1 to tagpos_state+2), + entry_gs => tlb_way3_q(waypos_gs), + entry_ts => tlb_way3_q(waypos_ts), + state_enable => state_enable_clone, + entry_thdid => tlb_way3_q(waypos_thdid to waypos_thdid+thdid_width-1), + comp_thdid => tlb_tag3_clone2_q(tagpos_thdid to tagpos_thdid+thdid_width-1), + thdid_enable => thdid_enable_clone, + entry_pid => tlb_way3_q(waypos_tid to waypos_tid+pid_width-1), + comp_pid => tlb_tag3_clone2_q(tagpos_pid to tagpos_pid+pid_width-1), + pid_enable => pid_enable_clone, + entry_lpid => tlb_way3_q(waypos_lpid to waypos_lpid+lpid_width-1), + comp_lpid => tlb_tag3_clone2_q(tagpos_lpid to tagpos_lpid+lpid_width-1), + lpid_enable => lpid_enable_clone, + entry_ind => tlb_way3_q(waypos_ind), + comp_ind => comp_ind_clone, + ind_enable => ind_enable_clone, + entry_iprot => lru_tag3_dataout_q(11), + comp_iprot => comp_iprot_clone, + iprot_enable => iprot_enable_clone, + entry_v => lru_tag3_dataout_q(3), + comp_invalidate => tlb_tag3_clone2_q(tagpos_type_snoop), + + match => tlb_wayhit(3), + + dbg_addr_match => tlb_way3_addr_match, + dbg_pgsize_match => tlb_way3_pgsize_match, + dbg_class_match => tlb_way3_class_match, + dbg_extclass_match => tlb_way3_extclass_match, + dbg_state_match => tlb_way3_state_match, + dbg_thdid_match => tlb_way3_thdid_match, + dbg_pid_match => tlb_way3_pid_match, + dbg_lpid_match => tlb_way3_lpid_match, + dbg_ind_match => tlb_way3_ind_match, + dbg_iprot_match => tlb_way3_iprot_match + ); +----------------------------------------------------------------------- +-- output assignments +----------------------------------------------------------------------- +tlb_cmp_ierat_dup_val(0 TO 6) <= tlb_erat_dup_q(0 to 6); +tlb_cmp_derat_dup_val(0 TO 6) <= tlb_erat_dup_q(10 to 16); +tlb_cmp_erat_dup_wait <= tlb_erat_dup_q(5) & tlb_erat_dup_q(15); +mm_iu_ierat_rel_val <= tlb_erat_val_q(0 to 4); +mm_iu_ierat_rel_data <= tlb_erat_rel_q; +mm_xu_derat_rel_val <= tlb_erat_val_q(5 to 9); +mm_xu_derat_rel_data <= tlb_erat_rel_clone_q; +mm_xu_eratmiss_done <= eratmiss_done_q; +mm_xu_tlb_miss <= tlb_miss_q; +mm_xu_tlb_inelig <= tlb_inelig_q; +mm_xu_lrat_miss <= lrat_miss_q; +mm_xu_pt_fault <= pt_fault_q; +mm_xu_hv_priv <= hv_priv_q; +mm_xu_esr_pt <= esr_pt_q; +mm_xu_esr_data <= esr_data_q; +mm_xu_esr_epid <= esr_epid_q; +mm_xu_esr_st <= esr_st_q; +mm_xu_cr0_eq <= cr0_eq_q; +mm_xu_cr0_eq_valid <= cr0_eq_valid_q; +mm_xu_tlb_multihit_err <= tlb_multihit_err_q; +mm_xu_tlb_par_err <= tlb_par_err_q; +mm_xu_lru_par_err <= lru_par_err_q; +tlb_tag5_except <= tlb_tag5_except_q; +tlb_tag4_esel <= tlb_tag4_q(tagpos_esel to tagpos_esel+2); +tlb_tag4_wq <= tlb_tag4_q(tagpos_wq to tagpos_wq+1); +tlb_tag4_is <= tlb_tag4_q(tagpos_is to tagpos_is+1); +tlb_tag4_hes <= tlb_tag4_q(tagpos_hes); +tlb_tag4_gs <= tlb_tag4_q(tagpos_gs); +tlb_tag4_pr <= tlb_tag4_q(tagpos_pr); +tlb_tag4_atsel <= tlb_tag4_q(tagpos_atsel); +tlb_tag4_pt <= tlb_tag4_q(tagpos_pt); +tlb_tag4_endflag <= tlb_tag4_q(tagpos_endflag) and or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1)); +lru_tag4_dataout <= lru_tag4_dataout_q(0 to 15); +tlb_tag4_cmp_hit <= tlb_tag4_wayhit_q(tlb_ways); +tlb_tag4_way_ind <= tlb_tag4_way_or(waypos_ind); +tlb_tag4_ptereload_sig <= tlb_tag4_q(tagpos_type_ptereload) and or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1)); +tlb_tag4_ptereload <= tlb_tag4_ptereload_sig; +tlb_tag4_parerr <= or_reduce(tag4_parerr_q(0 to 4)) and tlb_tag4_parerr_enab; +tlb_mas0_esel(0) <= '0'; +tlb_mas0_esel(1 TO 2) <= "01" when tlb_tag4_wayhit_q(0 to tlb_ways)="01001" + else "10" when tlb_tag4_wayhit_q(0 to tlb_ways)="00101" + else "11" when tlb_tag4_wayhit_q(0 to tlb_ways)="00011" + else "00"; +tlb_mas1_v <= lru_tag4_dataout_q(0) when + (tlb_tag4_q(tagpos_type_tlbre)='1' and tlb_tag4_q(tagpos_esel+1 to tagpos_esel+2)="00") + else lru_tag4_dataout_q(1) when + (tlb_tag4_q(tagpos_type_tlbre)='1' and tlb_tag4_q(tagpos_esel+1 to tagpos_esel+2)="01") + else lru_tag4_dataout_q(2) when + (tlb_tag4_q(tagpos_type_tlbre)='1' and tlb_tag4_q(tagpos_esel+1 to tagpos_esel+2)="10") + else lru_tag4_dataout_q(3) when + (tlb_tag4_q(tagpos_type_tlbre)='1' and tlb_tag4_q(tagpos_esel+1 to tagpos_esel+2)="11") + else tlb_tag4_wayhit_q(tlb_ways) when tlb_tag4_q(tagpos_type_tlbsx)='1' + else '0'; +tlb_mas1_iprot <= lru_tag4_dataout_q(8) when + (tlb_tag4_q(tagpos_type_tlbsx)='1' and tlb_tag4_wayhit_q(0 to tlb_ways)="10001") or + (tlb_tag4_q(tagpos_type_tlbre)='1' and tlb_tag4_q(tagpos_esel+1 to tagpos_esel+2)="00") + else lru_tag4_dataout_q(9) when + (tlb_tag4_q(tagpos_type_tlbsx)='1' and tlb_tag4_wayhit_q(0 to tlb_ways)="01001") or + (tlb_tag4_q(tagpos_type_tlbre)='1' and tlb_tag4_q(tagpos_esel+1 to tagpos_esel+2)="01") + else lru_tag4_dataout_q(10) when + (tlb_tag4_q(tagpos_type_tlbsx)='1' and tlb_tag4_wayhit_q(0 to tlb_ways)="00101") or + (tlb_tag4_q(tagpos_type_tlbre)='1' and tlb_tag4_q(tagpos_esel+1 to tagpos_esel+2)="10") + else lru_tag4_dataout_q(11) when + (tlb_tag4_q(tagpos_type_tlbsx)='1' and tlb_tag4_wayhit_q(0 to tlb_ways)="00011") or + (tlb_tag4_q(tagpos_type_tlbre)='1' and tlb_tag4_q(tagpos_esel+1 to tagpos_esel+2)="11") + else '0'; +-- waypos_epn : natural := 0; +-- waypos_size : natural := 52; +-- waypos_thdid : natural := 56; +-- waypos_class : natural := 60; +-- waypos_extclass : natural := 62; +-- waypos_lpid : natural := 66; +-- waypos_xbit : natural := 84; +-- waypos_rpn : natural := 88; +-- waypos_rc : natural := 118; +-- waypos_wlc : natural := 120; +-- waypos_resvattr : natural := 122; +-- waypos_vf : natural := 123; +-- waypos_ind : natural := 124; +-- waypos_ubits : natural := 125; +-- waypos_wimge : natural := 129; +-- waypos_usxwr : natural := 134; +-- waypos_gs : natural := 140; +-- waypos_ts : natural := 141; +-- waypos_tid : natural := 144; -- 14 bits +-- constant tagpos_type : natural := 82; -- derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload +tlb_mas1_tid <= tlb_tag4_way_rw_or(waypos_tid to waypos_tid+13) when ( or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1))='1' and + (tlb_tag4_q(tagpos_type_tlbre) or tlb_tag4_q(tagpos_type_tlbwe) or tlb_tag4_q(tagpos_type_ptereload))='1' ) + else tlb_tag4_way_or(waypos_tid to waypos_tid+13); +tlb_mas1_tid_error <= tlb_tag4_q(tagpos_pid to tagpos_pid+pid_width-1); +tlb_mas1_ind <= tlb_tag4_way_rw_or(waypos_ind) when ( or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1))='1' and + (tlb_tag4_q(tagpos_type_tlbre) or tlb_tag4_q(tagpos_type_tlbwe) or tlb_tag4_q(tagpos_type_ptereload))='1' ) + else tlb_tag4_way_or(waypos_ind); +tlb_mas1_ts <= tlb_tag4_way_rw_or(waypos_ts) when ( or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1))='1' and + (tlb_tag4_q(tagpos_type_tlbre) or tlb_tag4_q(tagpos_type_tlbwe) or tlb_tag4_q(tagpos_type_ptereload))='1' ) + else tlb_tag4_way_or(waypos_ts); +tlb_mas1_ts_error <= tlb_tag4_q(tagpos_state+2); +tlb_mas1_tsize <= tlb_tag4_way_rw_or(waypos_size to waypos_size+3) when ( or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1))='1' and + (tlb_tag4_q(tagpos_type_tlbre) or tlb_tag4_q(tagpos_type_tlbwe) or tlb_tag4_q(tagpos_type_ptereload))='1' ) + else tlb_tag4_way_or(waypos_size to waypos_size+3); +tlb_mas2_epn(0 TO 31) <= ( tlb_tag4_way_rw_or(waypos_epn to waypos_epn+31) and (0 to 31 => tlb_tag4_q(tagpos_cm))) + when ( or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1))='1' and + (tlb_tag4_q(tagpos_type_tlbre) or tlb_tag4_q(tagpos_type_tlbwe) or tlb_tag4_q(tagpos_type_ptereload))='1' ) + else tlb_tag4_way_or(waypos_epn to waypos_epn+31); +tlb_mas2_epn(32 TO epn_width-1) <= tlb_tag4_way_rw_or(waypos_epn+32 to waypos_epn+51) + when ( or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1))='1' and + (tlb_tag4_q(tagpos_type_tlbre) or tlb_tag4_q(tagpos_type_tlbwe) or tlb_tag4_q(tagpos_type_ptereload))='1' ) + else tlb_tag4_way_or(waypos_epn+32 to waypos_epn+51); +tlb_mas2_epn_error <= tlb_tag4_q(tagpos_epn to tagpos_epn+epn_width-1); +tlb_mas2_wimge <= tlb_tag4_way_rw_or(waypos_wimge to waypos_wimge+4) when ( or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1))='1' and + (tlb_tag4_q(tagpos_type_tlbre) or tlb_tag4_q(tagpos_type_tlbwe) or tlb_tag4_q(tagpos_type_ptereload))='1' ) + else tlb_tag4_way_or(waypos_wimge to waypos_wimge+4); +tlb_mas3_rpnl <= tlb_tag4_way_rw_or(waypos_rpn+10 to waypos_rpn+rpn_width-1) when ( or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1))='1' and + (tlb_tag4_q(tagpos_type_tlbre) or tlb_tag4_q(tagpos_type_tlbwe) or tlb_tag4_q(tagpos_type_ptereload))='1' ) + else tlb_tag4_way_or(waypos_rpn+10 to waypos_rpn+rpn_width-1); +tlb_mas3_ubits <= tlb_tag4_way_rw_or(waypos_ubits to waypos_ubits+3) when ( or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1))='1' and + (tlb_tag4_q(tagpos_type_tlbre) or tlb_tag4_q(tagpos_type_tlbwe) or tlb_tag4_q(tagpos_type_ptereload))='1' ) + else tlb_tag4_way_or(waypos_ubits to waypos_ubits+3); +tlb_mas3_usxwr <= tlb_tag4_way_rw_or(waypos_usxwr to waypos_usxwr+5) when ( or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1))='1' and + (tlb_tag4_q(tagpos_type_tlbre) or tlb_tag4_q(tagpos_type_tlbwe) or tlb_tag4_q(tagpos_type_ptereload))='1' ) + else tlb_tag4_way_or(waypos_usxwr to waypos_usxwr+5); +tlb_mas6_spid <= tlb_tag4_q(tagpos_pid to tagpos_pid+pid_width-1); +tlb_mas6_isize <= tlb_tag4_q(tagpos_size to tagpos_size+3); +tlb_mas6_sind <= tlb_tag4_q(tagpos_ind); +tlb_mas6_sas <= tlb_tag4_q(tagpos_state+2); +tlb_mas7_rpnu <= tlb_tag4_way_rw_or(waypos_rpn to waypos_rpn+9) when ( or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1))='1' and + (tlb_tag4_q(tagpos_type_tlbre) or tlb_tag4_q(tagpos_type_tlbwe) or tlb_tag4_q(tagpos_type_ptereload))='1' ) + else tlb_tag4_way_or(waypos_rpn to waypos_rpn+9); +tlb_mas8_tgs <= tlb_tag4_way_rw_or(waypos_gs) when ( or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1))='1' and + (tlb_tag4_q(tagpos_type_tlbre) or tlb_tag4_q(tagpos_type_tlbwe) or tlb_tag4_q(tagpos_type_ptereload))='1' ) + else tlb_tag4_way_or(waypos_gs); +tlb_mas8_vf <= tlb_tag4_way_rw_or(waypos_vf) when ( or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1))='1' and + (tlb_tag4_q(tagpos_type_tlbre) or tlb_tag4_q(tagpos_type_tlbwe) or tlb_tag4_q(tagpos_type_ptereload))='1' ) + else tlb_tag4_way_or(waypos_vf); +tlb_mas8_tlpid <= tlb_tag4_way_rw_or(waypos_lpid to waypos_lpid+lpid_width-1) when ( or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1))='1' and + (tlb_tag4_q(tagpos_type_tlbre) or tlb_tag4_q(tagpos_type_tlbwe) or tlb_tag4_q(tagpos_type_ptereload))='1' ) + else tlb_tag4_way_or(waypos_lpid to waypos_lpid+lpid_width-1); +tlb_mmucr3_thdid <= tlb_tag4_way_rw_or(waypos_thdid to waypos_thdid+thdid_width-1) when ( or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1))='1' and + (tlb_tag4_q(tagpos_type_tlbre) or tlb_tag4_q(tagpos_type_tlbwe) or tlb_tag4_q(tagpos_type_ptereload))='1' ) + else tlb_tag4_way_or(waypos_thdid to waypos_thdid+thdid_width-1); +tlb_mmucr3_resvattr <= tlb_tag4_way_rw_or(waypos_resvattr) when ( or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1))='1' and + (tlb_tag4_q(tagpos_type_tlbre) or tlb_tag4_q(tagpos_type_tlbwe) or tlb_tag4_q(tagpos_type_ptereload))='1' ) + else tlb_tag4_way_or(waypos_resvattr); +tlb_mmucr3_wlc <= tlb_tag4_way_rw_or(waypos_wlc to waypos_wlc+1) when ( or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1))='1' and + (tlb_tag4_q(tagpos_type_tlbre) or tlb_tag4_q(tagpos_type_tlbwe) or tlb_tag4_q(tagpos_type_ptereload))='1' ) + else tlb_tag4_way_or(waypos_wlc to waypos_wlc+1); +tlb_mmucr3_class <= tlb_tag4_way_rw_or(waypos_class to waypos_class+1) when ( or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1))='1' and + (tlb_tag4_q(tagpos_type_tlbre) or tlb_tag4_q(tagpos_type_tlbwe) or tlb_tag4_q(tagpos_type_ptereload))='1' ) + else tlb_tag4_way_or(waypos_class to waypos_class+1); +tlb_mmucr3_extclass <= tlb_tag4_way_rw_or(waypos_extclass to waypos_extclass+1) when ( or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1))='1' and + (tlb_tag4_q(tagpos_type_tlbre) or tlb_tag4_q(tagpos_type_tlbwe) or tlb_tag4_q(tagpos_type_ptereload))='1' ) + else tlb_tag4_way_or(waypos_extclass to waypos_extclass+1); +tlb_mmucr3_rc <= tlb_tag4_way_rw_or(waypos_rc to waypos_rc+1) when ( or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1))='1' and + (tlb_tag4_q(tagpos_type_tlbre) or tlb_tag4_q(tagpos_type_tlbwe) or tlb_tag4_q(tagpos_type_ptereload))='1' ) + else tlb_tag4_way_or(waypos_rc to waypos_rc+1); +tlb_mmucr3_x <= tlb_tag4_way_rw_or(waypos_xbit) when ( or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1))='1' and + (tlb_tag4_q(tagpos_type_tlbre) or tlb_tag4_q(tagpos_type_tlbwe) or tlb_tag4_q(tagpos_type_ptereload))='1' ) + else tlb_tag4_way_or(waypos_xbit); +tlb_mmucr1_een <= tlb_addr4_q & (tag4_parerr_q(2) or tag4_parerr_q(3)) & (tag4_parerr_q(1) or tag4_parerr_q(3)); +tlb_mmucr1_we <= ( ( (or_reduce(tag4_parerr_q(0 to 4)) and or_reduce(tlb_tag4_q(tagpos_type_derat to tagpos_type_tlbsrx)) and not tlb_tag4_q(tagpos_type_ptereload)) or tlb_tag4_tlbre_parerr ) + and ECO107332_orred_tag4_thdid_flushed ) + or ( multihit and tlb_tag4_wayhit_q(tlb_ways) and or_reduce(tlb_tag4_q(tagpos_type_derat to tagpos_type_tlbsrx)) and not tlb_tag4_q(tagpos_type_ptereload) ); +ECO107332_orred_tag4_thdid_flushed <= or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag4_flush)); +tlb_mas_dtlb_error <= tlb_tag4_q(tagpos_type_derat) and tlb_tag4_q(tagpos_endflag) and not tlb_tag4_wayhit_q(tlb_ways) and (not(or_reduce(tag4_parerr_q(0 to 4))) or cswitch_q(6)) and + or_reduce( (msr_gs_q or msr_pr_q or not epcr_dmiuh_q) and tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) ); +tlb_mas_itlb_error <= tlb_tag4_q(tagpos_type_ierat) and tlb_tag4_q(tagpos_endflag) and not tlb_tag4_wayhit_q(tlb_ways) and (not(or_reduce(tag4_parerr_q(0 to 4))) or cswitch_q(6)) and + or_reduce( (msr_gs_q or msr_pr_q or not epcr_dmiuh_q) and tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) ); +tlb_mas_tlbsx_hit <= tlb_tag4_q(tagpos_type_tlbsx) and tlb_tag4_wayhit_q(tlb_ways) and not multihit and tlb_tag4_hv_op and (not(or_reduce(tag4_parerr_q(0 to 4))) or cswitch_q(5)); +tlb_mas_tlbsx_miss <= tlb_tag4_q(tagpos_type_tlbsx) and tlb_tag4_q(tagpos_endflag) and not tlb_tag4_wayhit_q(tlb_ways) and tlb_tag4_hv_op and (not(or_reduce(tag4_parerr_q(0 to 4))) or cswitch_q(6)); +tlb_mas_tlbre <= tlb_tag4_q(tagpos_type_tlbre) and not tlb_tag4_q(tagpos_atsel) and tlb_tag4_hv_op and not ex6_illeg_instr(0) and (not(tlb_tag4_tlbre_parerr) or cswitch_q(7)); +tlb_mas_thdid <= tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag4_flush); +tlbwe_tag3_back_inv_enab <= + ( lru_tag3_dataout_q(0) and (lru_tag3_dataout_q(8) or not cswitch_q(0)) and (not(tlb_tag3_q(tagpos_is)) or not(cswitch_q(3))) and not tlb_tag3_q(tagpos_hes) and not tlb_tag3_q(tagpos_esel+1) and not tlb_tag3_q(tagpos_esel+2) ) or + ( lru_tag3_dataout_q(1) and (lru_tag3_dataout_q(9) or not cswitch_q(0)) and (not(tlb_tag3_q(tagpos_is)) or not(cswitch_q(3))) and not tlb_tag3_q(tagpos_hes) and not tlb_tag3_q(tagpos_esel+1) and tlb_tag3_q(tagpos_esel+2) ) or + ( lru_tag3_dataout_q(2) and (lru_tag3_dataout_q(10) or not cswitch_q(0)) and (not(tlb_tag3_q(tagpos_is)) or not(cswitch_q(3))) and not tlb_tag3_q(tagpos_hes) and tlb_tag3_q(tagpos_esel+1) and not tlb_tag3_q(tagpos_esel+2) ) or + ( lru_tag3_dataout_q(3) and (lru_tag3_dataout_q(11) or not cswitch_q(0)) and (not(tlb_tag3_q(tagpos_is)) or not(cswitch_q(3))) and not tlb_tag3_q(tagpos_hes) and tlb_tag3_q(tagpos_esel+1) and tlb_tag3_q(tagpos_esel+2) ) or + ( lru_tag3_dataout_q(0) and (lru_tag3_dataout_q(8) or not cswitch_q(0)) and (not(tlb_tag3_q(tagpos_is)) or not(cswitch_q(3))) and tlb_tag3_q(tagpos_hes) and cswitch_q(1) and not lru_tag3_dataout_q(4) and not lru_tag3_dataout_q(5) ) or + ( lru_tag3_dataout_q(1) and (lru_tag3_dataout_q(9) or not cswitch_q(0)) and (not(tlb_tag3_q(tagpos_is)) or not(cswitch_q(3))) and tlb_tag3_q(tagpos_hes) and cswitch_q(1) and not lru_tag3_dataout_q(4) and lru_tag3_dataout_q(5) ) or + ( lru_tag3_dataout_q(2) and (lru_tag3_dataout_q(10) or not cswitch_q(0)) and (not(tlb_tag3_q(tagpos_is)) or not(cswitch_q(3))) and tlb_tag3_q(tagpos_hes) and cswitch_q(1) and lru_tag3_dataout_q(4) and not lru_tag3_dataout_q(6) ) or + ( lru_tag3_dataout_q(3) and (lru_tag3_dataout_q(11) or not cswitch_q(0)) and (not(tlb_tag3_q(tagpos_is)) or not(cswitch_q(3))) and tlb_tag3_q(tagpos_hes) and cswitch_q(1) and lru_tag3_dataout_q(4) and lru_tag3_dataout_q(6) ); +tlbwe_tag4_back_inv_d(0 TO thdid_width-1) <= tlb_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag3_flush); +tlbwe_tag4_back_inv_d(thdid_width) <= ( tlbwe_tag3_back_inv_enab and tlb_tag3_q(tagpos_type_tlbwe) and not(Eq(tlb_tag3_q(tagpos_wq to tagpos_wq+1),"10")) and mmucr1_q(pos_tlbwe_binv) and + ((not(tlb_tag3_q(tagpos_gs)) and not(tlb_tag3_q(tagpos_atsel))) or + (tlb_tag3_q(tagpos_gs) and tlb_tag3_q(tagpos_hes) and lrat_tag3_hit_status(1) and not lrat_tag3_hit_status(2))) and + or_reduce(tlb_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag3_flush)) ); +tlbwe_tag4_back_inv_attr_d(18) <= + ( lru_tag3_dataout_q(0) and (lru_tag3_dataout_q(8) or not cswitch_q(2)) and not tlb_tag3_q(tagpos_hes) and not tlb_tag3_q(tagpos_esel+1) and not tlb_tag3_q(tagpos_esel+2) ) or + ( lru_tag3_dataout_q(1) and (lru_tag3_dataout_q(9) or not cswitch_q(2)) and not tlb_tag3_q(tagpos_hes) and not tlb_tag3_q(tagpos_esel+1) and tlb_tag3_q(tagpos_esel+2) ) or + ( lru_tag3_dataout_q(2) and (lru_tag3_dataout_q(10) or not cswitch_q(2)) and not tlb_tag3_q(tagpos_hes) and tlb_tag3_q(tagpos_esel+1) and not tlb_tag3_q(tagpos_esel+2) ) or + ( lru_tag3_dataout_q(3) and (lru_tag3_dataout_q(11) or not cswitch_q(2)) and not tlb_tag3_q(tagpos_hes) and tlb_tag3_q(tagpos_esel+1) and tlb_tag3_q(tagpos_esel+2) ) or + ( lru_tag3_dataout_q(0) and (lru_tag3_dataout_q(8) or not cswitch_q(2)) and tlb_tag3_q(tagpos_hes) and not lru_tag3_dataout_q(4) and not lru_tag3_dataout_q(5) ) or + ( lru_tag3_dataout_q(1) and (lru_tag3_dataout_q(9) or not cswitch_q(2)) and tlb_tag3_q(tagpos_hes) and not lru_tag3_dataout_q(4) and lru_tag3_dataout_q(5) ) or + ( lru_tag3_dataout_q(2) and (lru_tag3_dataout_q(10) or not cswitch_q(2)) and tlb_tag3_q(tagpos_hes) and lru_tag3_dataout_q(4) and not lru_tag3_dataout_q(6) ) or + ( lru_tag3_dataout_q(3) and (lru_tag3_dataout_q(11) or not cswitch_q(2)) and tlb_tag3_q(tagpos_hes) and lru_tag3_dataout_q(4) and lru_tag3_dataout_q(6) ); +tlbwe_tag4_back_inv_attr_d(19) <= '0'; +tlbwe_back_inv_valid <= tlbwe_tag4_back_inv_q(thdid_width) and (not(tlb_tag4_way_rw_or(waypos_ind)) or cswitch_q(4)); +tlbwe_back_inv_thdid <= tlbwe_tag4_back_inv_q(0 to thdid_width-1); +tlbwe_back_inv_addr <= tlb_tag4_way_rw_or(waypos_epn to waypos_epn+51); +tlbwe_back_inv_attr <= '1' & "011" & + tlb_tag4_way_rw_or(waypos_gs) & tlb_tag4_way_rw_or(waypos_ts) & + tlb_tag4_way_rw_or(waypos_tid+6 to waypos_tid+13) & + tlb_tag4_way_rw_or(waypos_size to waypos_size+3) & + tlbwe_tag4_back_inv_attr_q(18 to 19) & + tlb_tag4_way_rw_or(waypos_tid to waypos_tid+5) & + tlb_tag4_way_rw_or(waypos_lpid to waypos_lpid+lpid_width-1) & + tlb_tag4_way_rw_or(waypos_ind); +lru_write <= lru_write_q and (0 to lru_width-1 => not or_reduce(tlb_tag5_except_q)); +lru_wr_addr <= lru_wr_addr_q; +lru_datain <= lru_datain_q; +tlb_htw_req_valid <= '1' when (tlb_tag4_q(tagpos_type_derat to tagpos_type_ierat)/="00" and tlb_tag4_q(tagpos_type_ptereload)='0' and + tlb_tag4_q(tagpos_ind)='1' and tlb_tag4_wayhit_q(tlb_ways)='1' and multihit='0') + else '0'; +tlb_htw_req_way <= tlb_tag4_way_or(tlb_word_width to tlb_way_width-1); +tlb_htw_req_tag(0 TO epn_width-1) <= tlb_tag4_q(0 to epn_width-1); +tlb_htw_req_tag(tagpos_pid TO tagpos_pid+pid_width-1) <= tlb_tag4_way_or(waypos_tid to waypos_tid+pid_width-1); +tlb_htw_req_tag(tagpos_is TO tagpos_class+1) <= tlb_tag4_q(tagpos_is to tagpos_class+1); +tlb_htw_req_tag(tagpos_pr) <= tlb_tag4_q(tagpos_pr); +tlb_htw_req_tag(tagpos_gs) <= tlb_tag4_way_or(waypos_gs); +tlb_htw_req_tag(tagpos_as) <= tlb_tag4_way_or(waypos_ts); +tlb_htw_req_tag(tagpos_cm) <= tlb_tag4_q(tagpos_cm); +tlb_htw_req_tag(tagpos_thdid TO tagpos_lpid-1) <= tlb_tag4_q(tagpos_thdid to tagpos_lpid-1); +tlb_htw_req_tag(tagpos_lpid TO tagpos_lpid+lpid_width-1) <= tlb_tag4_way_or(waypos_lpid to waypos_lpid+lpid_width-1); +tlb_htw_req_tag(tagpos_ind) <= tlb_tag4_q(tagpos_ind); +tlb_htw_req_tag(tagpos_atsel) <= tlb_tag4_way_or(waypos_thdid); +tlb_htw_req_tag(tagpos_esel TO tagpos_esel+2) <= tlb_tag4_way_or(waypos_thdid+1 to waypos_thdid+3); +tlb_htw_req_tag(tagpos_hes TO tlb_tag_width-1) <= tlb_tag4_q(tagpos_hes to tlb_tag_width-1); +--constant tagpos_epn : natural := 0; +--constant tagpos_pid : natural := 52; -- 14 bits +--constant tagpos_is : natural := 66; +--constant tagpos_class : natural := 68; +--constant tagpos_state : natural := 70; -- state: 0:pr 1:gs 2:as 3:cm +--constant tagpos_thdid : natural := 74; +--constant tagpos_size : natural := 78; +--constant tagpos_type : natural := 82; -- derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload +--constant tagpos_lpid : natural := 90; +--constant tagpos_ind : natural := 98; +--constant tagpos_atsel : natural := 99; +--constant tagpos_esel : natural := 100; +--constant tagpos_hes : natural := 103; +--constant tagpos_wq : natural := 104; +--constant tagpos_lrat : natural := 106; +--constant tagpos_pt : natural := 107; +--constant tagpos_recform : natural := 108; +--constant tagpos_endflag : natural := 109; +-- waypos_epn : natural := 0; +-- waypos_size : natural := 52; +-- waypos_thdid : natural := 56; +-- waypos_class : natural := 60; +-- waypos_extclass : natural := 62; +-- waypos_lpid : natural := 66; +-- waypos_xbit : natural := 84; +-- waypos_rpn : natural := 88; +-- waypos_rc : natural := 118; +-- waypos_wlc : natural := 120; +-- waypos_resvattr : natural := 122; +-- waypos_vf : natural := 123; +-- waypos_ind : natural := 124; +-- waypos_ubits : natural := 125; +-- waypos_wimge : natural := 129; +-- waypos_usxwr : natural := 134; +-- waypos_gs : natural := 140; +-- waypos_ts : natural := 141; +-- waypos_tid : natural := 144; -- 14 bits +----------------------------------------------------------------------- +-- Performance events +----------------------------------------------------------------------- +---------------------------------------------------- +-- t* threadwise event list +---------------------------------------------------- +-- 0 TLB hit direct entry (instr.) (ind=0 entry hit for fetch) +-- 1 TLB miss direct entry (instr.) (ind=0 entry missed for fetch) +-- 2 TLB miss indirect entry (instr.) (ind=1 entry missed for fetch, results in i-tlb exception) +-- 3 H/W tablewalk hit (instr.) (ptereload with PTE.V=1 for fetch) +-- 4 H/W tablewalk miss (instr.) (ptereload with PTE.V=0 for fetch, results in PT fault exception -> isi) +-- 5 TLB hit direct entry (data) (ind=0 entry hit for load/store/cache op) +-- 6 TLB miss direct entry (data) (ind=0 entry miss for load/store/cache op) +-- 7 TLB miss indirect entry (data) (ind=1 entry missed for load/store/cache op, results in d-tlb exception) +-- 8 H/W tablewalk hit (data) (ptereload with PTE.V=1 for load/store/cache op) +-- 9 H/W tablewalk miss (data) (ptereload with PTE.V=0 for load/store/cache op, results in PT fault exception -> dsi) +-- 10 IERAT miss (or latency), edge (or level) (total ierat misses or latency) +-- 11 DERAT miss (or latency), edge (or level) (total derat misses or latency) +tlb_cmp_perf_event_t0(0) <= tlb_tag4_q(tagpos_thdid+0) and tlb_tag4_q(tagpos_type_ierat) and not tlb_tag4_q(tagpos_type_ptereload) and + not tlb_tag4_q(tagpos_ind) and tlb_tag4_wayhit_q(tlb_ways) and not multihit; +tlb_cmp_perf_event_t0(1) <= tlb_tag4_q(tagpos_thdid+0) and tlb_tag4_q(tagpos_type_ierat) and not tlb_tag4_q(tagpos_type_ptereload) and + not tlb_tag4_q(tagpos_ind) and not tlb_tag4_wayhit_q(tlb_ways) and + (tlb_tag3_q(tagpos_ind) or tlb_tag4_q(tagpos_endflag)); +tlb_cmp_perf_event_t0(2) <= tlb_tag4_q(tagpos_thdid+0) and tlb_tag4_q(tagpos_type_ierat) and not tlb_tag4_q(tagpos_type_ptereload) and + tlb_tag4_q(tagpos_ind) and not tlb_tag4_wayhit_q(tlb_ways) and + tlb_tag4_q(tagpos_endflag); +tlb_cmp_perf_event_t0(3) <= tlb_tag4_q(tagpos_thdid+0) and tlb_tag4_q(tagpos_type_ierat) and tlb_tag4_q(tagpos_type_ptereload) and + tlb_tag4_q(tagpos_is); +tlb_cmp_perf_event_t0(4) <= tlb_tag4_q(tagpos_thdid+0) and tlb_tag4_q(tagpos_type_ierat) and tlb_tag4_q(tagpos_type_ptereload) and + not tlb_tag4_q(tagpos_is); +tlb_cmp_perf_event_t0(5) <= tlb_tag4_q(tagpos_thdid+0) and tlb_tag4_q(tagpos_type_derat) and not tlb_tag4_q(tagpos_type_ptereload) and + not tlb_tag4_q(tagpos_ind) and tlb_tag4_wayhit_q(tlb_ways) and not multihit; +tlb_cmp_perf_event_t0(6) <= tlb_tag4_q(tagpos_thdid+0) and tlb_tag4_q(tagpos_type_derat) and not tlb_tag4_q(tagpos_type_ptereload) and + not tlb_tag4_q(tagpos_ind) and not tlb_tag4_wayhit_q(tlb_ways) and + (tlb_tag3_q(tagpos_ind) or tlb_tag4_q(tagpos_endflag)); +tlb_cmp_perf_event_t0(7) <= tlb_tag4_q(tagpos_thdid+0) and tlb_tag4_q(tagpos_type_derat) and not tlb_tag4_q(tagpos_type_ptereload) and + tlb_tag4_q(tagpos_ind) and not tlb_tag4_wayhit_q(tlb_ways) and + tlb_tag4_q(tagpos_endflag); +tlb_cmp_perf_event_t0(8) <= tlb_tag4_q(tagpos_thdid+0) and tlb_tag4_q(tagpos_type_derat) and tlb_tag4_q(tagpos_type_ptereload) and + tlb_tag4_q(tagpos_is); +tlb_cmp_perf_event_t0(9) <= tlb_tag4_q(tagpos_thdid+0) and tlb_tag4_q(tagpos_type_derat) and tlb_tag4_q(tagpos_type_ptereload) and + not tlb_tag4_q(tagpos_is); +tlb_cmp_perf_event_t1(0) <= tlb_tag4_q(tagpos_thdid+1) and tlb_tag4_q(tagpos_type_ierat) and not tlb_tag4_q(tagpos_type_ptereload) and + not tlb_tag4_q(tagpos_ind) and tlb_tag4_wayhit_q(tlb_ways) and not multihit; +tlb_cmp_perf_event_t1(1) <= tlb_tag4_q(tagpos_thdid+1) and tlb_tag4_q(tagpos_type_ierat) and not tlb_tag4_q(tagpos_type_ptereload) and + not tlb_tag4_q(tagpos_ind) and not tlb_tag4_wayhit_q(tlb_ways) and + (tlb_tag3_q(tagpos_ind) or tlb_tag4_q(tagpos_endflag)); +tlb_cmp_perf_event_t1(2) <= tlb_tag4_q(tagpos_thdid+1) and tlb_tag4_q(tagpos_type_ierat) and not tlb_tag4_q(tagpos_type_ptereload) and + tlb_tag4_q(tagpos_ind) and not tlb_tag4_wayhit_q(tlb_ways) and + tlb_tag4_q(tagpos_endflag); +tlb_cmp_perf_event_t1(3) <= tlb_tag4_q(tagpos_thdid+1) and tlb_tag4_q(tagpos_type_ierat) and tlb_tag4_q(tagpos_type_ptereload) and + tlb_tag4_q(tagpos_is); +tlb_cmp_perf_event_t1(4) <= tlb_tag4_q(tagpos_thdid+1) and tlb_tag4_q(tagpos_type_ierat) and tlb_tag4_q(tagpos_type_ptereload) and + not tlb_tag4_q(tagpos_is); +tlb_cmp_perf_event_t1(5) <= tlb_tag4_q(tagpos_thdid+1) and tlb_tag4_q(tagpos_type_derat) and not tlb_tag4_q(tagpos_type_ptereload) and + not tlb_tag4_q(tagpos_ind) and tlb_tag4_wayhit_q(tlb_ways) and not multihit; +tlb_cmp_perf_event_t1(6) <= tlb_tag4_q(tagpos_thdid+1) and tlb_tag4_q(tagpos_type_derat) and not tlb_tag4_q(tagpos_type_ptereload) and + not tlb_tag4_q(tagpos_ind) and not tlb_tag4_wayhit_q(tlb_ways) and + (tlb_tag3_q(tagpos_ind) or tlb_tag4_q(tagpos_endflag)); +tlb_cmp_perf_event_t1(7) <= tlb_tag4_q(tagpos_thdid+1) and tlb_tag4_q(tagpos_type_derat) and not tlb_tag4_q(tagpos_type_ptereload) and + tlb_tag4_q(tagpos_ind) and not tlb_tag4_wayhit_q(tlb_ways) and + tlb_tag4_q(tagpos_endflag); +tlb_cmp_perf_event_t1(8) <= tlb_tag4_q(tagpos_thdid+1) and tlb_tag4_q(tagpos_type_derat) and tlb_tag4_q(tagpos_type_ptereload) and + tlb_tag4_q(tagpos_is); +tlb_cmp_perf_event_t1(9) <= tlb_tag4_q(tagpos_thdid+1) and tlb_tag4_q(tagpos_type_derat) and tlb_tag4_q(tagpos_type_ptereload) and + not tlb_tag4_q(tagpos_is); +tlb_cmp_perf_event_t2(0) <= tlb_tag4_q(tagpos_thdid+2) and tlb_tag4_q(tagpos_type_ierat) and not tlb_tag4_q(tagpos_type_ptereload) and + not tlb_tag4_q(tagpos_ind) and tlb_tag4_wayhit_q(tlb_ways) and not multihit; +tlb_cmp_perf_event_t2(1) <= tlb_tag4_q(tagpos_thdid+2) and tlb_tag4_q(tagpos_type_ierat) and not tlb_tag4_q(tagpos_type_ptereload) and + not tlb_tag4_q(tagpos_ind) and not tlb_tag4_wayhit_q(tlb_ways) and + (tlb_tag3_q(tagpos_ind) or tlb_tag4_q(tagpos_endflag)); +tlb_cmp_perf_event_t2(2) <= tlb_tag4_q(tagpos_thdid+2) and tlb_tag4_q(tagpos_type_ierat) and not tlb_tag4_q(tagpos_type_ptereload) and + tlb_tag4_q(tagpos_ind) and not tlb_tag4_wayhit_q(tlb_ways) and + tlb_tag4_q(tagpos_endflag); +tlb_cmp_perf_event_t2(3) <= tlb_tag4_q(tagpos_thdid+2) and tlb_tag4_q(tagpos_type_ierat) and tlb_tag4_q(tagpos_type_ptereload) and + tlb_tag4_q(tagpos_is); +tlb_cmp_perf_event_t2(4) <= tlb_tag4_q(tagpos_thdid+2) and tlb_tag4_q(tagpos_type_ierat) and tlb_tag4_q(tagpos_type_ptereload) and + not tlb_tag4_q(tagpos_is); +tlb_cmp_perf_event_t2(5) <= tlb_tag4_q(tagpos_thdid+2) and tlb_tag4_q(tagpos_type_derat) and not tlb_tag4_q(tagpos_type_ptereload) and + not tlb_tag4_q(tagpos_ind) and tlb_tag4_wayhit_q(tlb_ways) and not multihit; +tlb_cmp_perf_event_t2(6) <= tlb_tag4_q(tagpos_thdid+2) and tlb_tag4_q(tagpos_type_derat) and not tlb_tag4_q(tagpos_type_ptereload) and + not tlb_tag4_q(tagpos_ind) and not tlb_tag4_wayhit_q(tlb_ways) and + (tlb_tag3_q(tagpos_ind) or tlb_tag4_q(tagpos_endflag)); +tlb_cmp_perf_event_t2(7) <= tlb_tag4_q(tagpos_thdid+2) and tlb_tag4_q(tagpos_type_derat) and not tlb_tag4_q(tagpos_type_ptereload) and + tlb_tag4_q(tagpos_ind) and not tlb_tag4_wayhit_q(tlb_ways) and + tlb_tag4_q(tagpos_endflag); +tlb_cmp_perf_event_t2(8) <= tlb_tag4_q(tagpos_thdid+2) and tlb_tag4_q(tagpos_type_derat) and tlb_tag4_q(tagpos_type_ptereload) and + tlb_tag4_q(tagpos_is); +tlb_cmp_perf_event_t2(9) <= tlb_tag4_q(tagpos_thdid+2) and tlb_tag4_q(tagpos_type_derat) and tlb_tag4_q(tagpos_type_ptereload) and + not tlb_tag4_q(tagpos_is); +tlb_cmp_perf_event_t3(0) <= tlb_tag4_q(tagpos_thdid+3) and tlb_tag4_q(tagpos_type_ierat) and not tlb_tag4_q(tagpos_type_ptereload) and + not tlb_tag4_q(tagpos_ind) and tlb_tag4_wayhit_q(tlb_ways) and not multihit; +tlb_cmp_perf_event_t3(1) <= tlb_tag4_q(tagpos_thdid+3) and tlb_tag4_q(tagpos_type_ierat) and not tlb_tag4_q(tagpos_type_ptereload) and + not tlb_tag4_q(tagpos_ind) and not tlb_tag4_wayhit_q(tlb_ways) and + (tlb_tag3_q(tagpos_ind) or tlb_tag4_q(tagpos_endflag)); +tlb_cmp_perf_event_t3(2) <= tlb_tag4_q(tagpos_thdid+3) and tlb_tag4_q(tagpos_type_ierat) and not tlb_tag4_q(tagpos_type_ptereload) and + tlb_tag4_q(tagpos_ind) and not tlb_tag4_wayhit_q(tlb_ways) and + tlb_tag4_q(tagpos_endflag); +tlb_cmp_perf_event_t3(3) <= tlb_tag4_q(tagpos_thdid+3) and tlb_tag4_q(tagpos_type_ierat) and tlb_tag4_q(tagpos_type_ptereload) and + tlb_tag4_q(tagpos_is); +tlb_cmp_perf_event_t3(4) <= tlb_tag4_q(tagpos_thdid+3) and tlb_tag4_q(tagpos_type_ierat) and tlb_tag4_q(tagpos_type_ptereload) and + not tlb_tag4_q(tagpos_is); +tlb_cmp_perf_event_t3(5) <= tlb_tag4_q(tagpos_thdid+3) and tlb_tag4_q(tagpos_type_derat) and not tlb_tag4_q(tagpos_type_ptereload) and + not tlb_tag4_q(tagpos_ind) and tlb_tag4_wayhit_q(tlb_ways) and not multihit; +tlb_cmp_perf_event_t3(6) <= tlb_tag4_q(tagpos_thdid+3) and tlb_tag4_q(tagpos_type_derat) and not tlb_tag4_q(tagpos_type_ptereload) and + not tlb_tag4_q(tagpos_ind) and not tlb_tag4_wayhit_q(tlb_ways) and + (tlb_tag3_q(tagpos_ind) or tlb_tag4_q(tagpos_endflag)); +tlb_cmp_perf_event_t3(7) <= tlb_tag4_q(tagpos_thdid+3) and tlb_tag4_q(tagpos_type_derat) and not tlb_tag4_q(tagpos_type_ptereload) and + tlb_tag4_q(tagpos_ind) and not tlb_tag4_wayhit_q(tlb_ways) and + tlb_tag4_q(tagpos_endflag); +tlb_cmp_perf_event_t3(8) <= tlb_tag4_q(tagpos_thdid+3) and tlb_tag4_q(tagpos_type_derat) and tlb_tag4_q(tagpos_type_ptereload) and + tlb_tag4_q(tagpos_is); +tlb_cmp_perf_event_t3(9) <= tlb_tag4_q(tagpos_thdid+3) and tlb_tag4_q(tagpos_type_derat) and tlb_tag4_q(tagpos_type_ptereload) and + not tlb_tag4_q(tagpos_is); +tlb_cmp_perf_state <= tlb_tag4_q(tagpos_gs) & tlb_tag4_q(tagpos_pr); +---------------------------------------------------- +-- core single event list +---------------------------------------------------- +-- t0 group +-- 12 IERAT miss total (part of direct entry search total) +-- 13 DERAT miss total (part of direct entry search total) +-- 14 TLB miss direct entry total (total TLB ind=0 misses) +-- 15 TLB hit direct entry first page size +---------------------------------------------------- +-- t1 group +-- 12 TLB indirect entry hits total (=page table searches) +-- 13 H/W tablewalk successful installs total (with no PTfault, TLB ineligible, or LRAT miss) +-- 14 LRAT translation request total (for GS=1 tlbwe and ptereload) +-- 15 LRAT misses total (for GS=1 tlbwe and ptereload) +---------------------------------------------------- +-- t2 group +-- 12 Page table faults total (PTE.V=0 for ptereload, resulting in isi/dsi) +-- 13 TLB ineligible total (all TLB ways are iprot=1 for ptereloads, resulting in isi/dsi) +-- 14 tlbwe conditional failed total (total tlbwe WQ=01 with no reservation match) +-- 15 tlbwe conditional success total (total tlbwe WQ=01 with reservation match) +---------------------------------------------------- +-- t3 group +-- 12 tlbilx local invalidations sourced total (sourced tlbilx on this core total) +-- 13 tlbivax invalidations sourced total (sourced tlbivax on this core total) +-- 14 tlbivax snoops total (total tlbivax snoops received from bus, local bit = don't care) +-- 15 TLB flush requests total (TLB requested flushes due to TLB busy or instruction hazards) +---------------------------------------------------- +tlb_cmp_perf_miss_direct <= or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1)) and or_reduce(tlb_tag4_q(tagpos_type_derat to tagpos_type_ierat)) and + not tlb_tag4_q(tagpos_type_ptereload) and not tlb_tag4_q(tagpos_ind) and not tlb_tag4_wayhit_q(tlb_ways) and + (tlb_tag3_q(tagpos_ind) or tlb_tag4_q(tagpos_endflag)); +tlb_cmp_perf_hit_indirect <= or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1)) and or_reduce(tlb_tag4_q(tagpos_type_derat to tagpos_type_ierat)) and + not tlb_tag4_q(tagpos_type_ptereload) and tlb_tag4_q(tagpos_ind) and tlb_tag4_wayhit_q(tlb_ways) and not multihit; +tlb_cmp_perf_hit_first_page <= or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1)) and or_reduce(tlb_tag4_q(tagpos_type_derat to tagpos_type_ierat)) and + not tlb_tag4_q(tagpos_type_ptereload) and not tlb_tag4_q(tagpos_ind) and tlb_tag4_wayhit_q(tlb_ways) and not multihit and + Eq(tlb_tag4_q(tagpos_esel to tagpos_esel+2),"001"); +tlb_cmp_perf_pt_fault <= or_reduce(pt_fault_q); +tlb_cmp_perf_pt_inelig <= or_reduce(tlb_inelig_q); +tlb_cmp_perf_lrat_miss <= or_reduce(lrat_miss_q); +tlb_cmp_perf_ptereload_noexcep <= or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1)) + when ( tlb_tag4_q(tagpos_type_ptereload)='1' and tlb_tag4_q(tagpos_is)='1' and + tlb_tag4_q(tagpos_wq to tagpos_wq+1)="10" and + tlb_tag4_q(tagpos_pt)='1' and + or_reduce(pt_fault_d or tlb_inelig_d or lrat_miss_d)='0' ) + else '0'; +tlb_cmp_perf_lrat_request <= or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag4_flush)) + when ( ((or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and tlb_resv_match_vec)='1' + and tlb_tag4_q(tagpos_wq to tagpos_wq+1)="01" and mmucfg_twc='1') + or tlb_tag4_q(tagpos_wq to tagpos_wq+1)="00" or tlb_tag4_q(tagpos_wq to tagpos_wq+1)="11") and + tlb_tag4_q(tagpos_type_tlbwe)='1' and tlb_tag4_q(tagpos_gs)='1' and tlb_tag4_q(tagpos_pr)='0' and + tlb_tag4_epcr_dgtmi='0' and mmucfg_lrat='1' and + tlb_tag4_q(tagpos_is)='1' ) + else or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1)) + when (tlb_tag4_q(tagpos_type_ptereload)='1' and tlb_tag4_q(tagpos_gs)='1' and mmucfg_lrat='1' and + tlb_tag4_q(tagpos_is)='1' and + tlb_tag4_q(tagpos_wq to tagpos_wq+1)="10" and + tlb_tag4_q(tagpos_pt)='1') + else '0'; +-- 0 TLB hit direct entry (instr.) (ind=0 entry hit for fetch) +-- 1 TLB miss direct entry (instr.) (ind=0 entry missed for fetch) +-- 2 TLB miss indirect entry (instr.) (ind=1 entry missed for fetch, results in i-tlb exception) +-- 3 H/W tablewalk hit (instr.) (ptereload with PTE.V=1 for fetch) +-- 4 H/W tablewalk miss (instr.) (ptereload with PTE.V=0 for fetch, results in PT fault exception -> isi) +-- 5 TLB hit direct entry (data) (ind=0 entry hit for load/store/cache op) +-- 6 TLB miss direct entry (data) (ind=0 entry miss for load/store/cache op) +-- 7 TLB miss indirect entry (data) (ind=1 entry missed for load/store/cache op, results in d-tlb exception) +-- 8 H/W tablewalk hit (data) (ptereload with PTE.V=1 for load/store/cache op) +-- 9 H/W tablewalk miss (data) (ptereload with PTE.V=0 for load/store/cache op, results in PT fault exception -> dsi) +-- 10 IERAT miss (or latency), edge (or level) (total ierat misses or latency) +-- 11 DERAT miss (or latency), edge (or level) (total derat misses or latency) +----------------------------------------------------------------------- +-- Debug trigger and data signals +----------------------------------------------------------------------- +tlb_cmp_dbg_tag4 <= tlb_tag4_q; +tlb_cmp_dbg_tag4_wayhit <= tlb_tag4_wayhit_q; +tlb_cmp_dbg_addr4 <= tlb_addr4_q; +tlb_cmp_dbg_tag4_way <= tlb_tag4_way_rw_or when ( or_reduce(tlb_tag4_q(tagpos_thdid to tagpos_thdid+thdid_width-1))='1' and + (tlb_tag4_q(tagpos_type_tlbre) or tlb_tag4_q(tagpos_type_tlbwe) or tlb_tag4_q(tagpos_type_ptereload))='1' ) + else tlb_tag4_way_or; +tlb_cmp_dbg_tag4_parerr <= tag4_parerr_q; +tlb_cmp_dbg_tag4_lru_dataout_q <= lru_tag4_dataout_q(0 to lru_width-5); +tlb_cmp_dbg_tag5_lru_datain_q <= lru_datain_q(0 to lru_width-5); +tlb_cmp_dbg_tag5_lru_write <= lru_write_q(0); +tlb_cmp_dbg_tag5_any_exception <= or_reduce(tlb_miss_q) or or_reduce(hv_priv_q) or or_reduce(lrat_miss_q) or or_reduce(pt_fault_q) or or_reduce(tlb_inelig_q); +tlb_cmp_dbg_tag5_except_type_q <= or_reduce(hv_priv_q) & or_reduce(lrat_miss_q) & or_reduce(pt_fault_q) & or_reduce(tlb_inelig_q); +tlb_cmp_dbg_tag5_except_thdid_q(0) <= hv_priv_q(2) or hv_priv_q(3) or lrat_miss_q(2) or lrat_miss_q(3) or + pt_fault_q(2) or pt_fault_q(3) or tlb_inelig_q(2) or tlb_inelig_q(3) or + tlb_miss_q(2) or tlb_miss_q(3); +tlb_cmp_dbg_tag5_except_thdid_q(1) <= hv_priv_q(1) or hv_priv_q(3) or lrat_miss_q(1) or lrat_miss_q(3) or + pt_fault_q(1) or pt_fault_q(3) or tlb_inelig_q(1) or tlb_inelig_q(3) or + tlb_miss_q(1) or tlb_miss_q(3); +tlb_cmp_dbg_tag5_erat_rel_val <= tlb_erat_val_q; +tlb_cmp_dbg_tag5_erat_rel_data <= tlb_erat_rel_q; +tlb_cmp_dbg_erat_dup_q <= tlb_erat_dup_q; +tlb_cmp_dbg_addr_enable <= addr_enable; +tlb_cmp_dbg_pgsize_enable <= pgsize_enable; +tlb_cmp_dbg_class_enable <= class_enable; +tlb_cmp_dbg_extclass_enable <= extclass_enable; +tlb_cmp_dbg_state_enable <= state_enable; +tlb_cmp_dbg_thdid_enable <= thdid_enable; +tlb_cmp_dbg_pid_enable <= pid_enable; +tlb_cmp_dbg_lpid_enable <= lpid_enable; +tlb_cmp_dbg_ind_enable <= ind_enable; +tlb_cmp_dbg_iprot_enable <= iprot_enable; +tlb_cmp_dbg_way0_entry_v <= lru_tag3_dataout_q(0); +tlb_cmp_dbg_way0_addr_match <= tlb_way0_addr_match; +tlb_cmp_dbg_way0_pgsize_match <= tlb_way0_pgsize_match; +tlb_cmp_dbg_way0_class_match <= tlb_way0_class_match; +tlb_cmp_dbg_way0_extclass_match <= tlb_way0_extclass_match; +tlb_cmp_dbg_way0_state_match <= tlb_way0_state_match; +tlb_cmp_dbg_way0_thdid_match <= tlb_way0_thdid_match; +tlb_cmp_dbg_way0_pid_match <= tlb_way0_pid_match; +tlb_cmp_dbg_way0_lpid_match <= tlb_way0_lpid_match; +tlb_cmp_dbg_way0_ind_match <= tlb_way0_ind_match; +tlb_cmp_dbg_way0_iprot_match <= tlb_way0_iprot_match; +tlb_cmp_dbg_way1_entry_v <= lru_tag3_dataout_q(1); +tlb_cmp_dbg_way1_addr_match <= tlb_way1_addr_match; +tlb_cmp_dbg_way1_pgsize_match <= tlb_way1_pgsize_match; +tlb_cmp_dbg_way1_class_match <= tlb_way1_class_match; +tlb_cmp_dbg_way1_extclass_match <= tlb_way1_extclass_match; +tlb_cmp_dbg_way1_state_match <= tlb_way1_state_match; +tlb_cmp_dbg_way1_thdid_match <= tlb_way1_thdid_match; +tlb_cmp_dbg_way1_pid_match <= tlb_way1_pid_match; +tlb_cmp_dbg_way1_lpid_match <= tlb_way1_lpid_match; +tlb_cmp_dbg_way1_ind_match <= tlb_way1_ind_match; +tlb_cmp_dbg_way1_iprot_match <= tlb_way1_iprot_match; +tlb_cmp_dbg_way2_entry_v <= lru_tag3_dataout_q(2); +tlb_cmp_dbg_way2_addr_match <= tlb_way2_addr_match; +tlb_cmp_dbg_way2_pgsize_match <= tlb_way2_pgsize_match; +tlb_cmp_dbg_way2_class_match <= tlb_way2_class_match; +tlb_cmp_dbg_way2_extclass_match <= tlb_way2_extclass_match; +tlb_cmp_dbg_way2_state_match <= tlb_way2_state_match; +tlb_cmp_dbg_way2_thdid_match <= tlb_way2_thdid_match; +tlb_cmp_dbg_way2_pid_match <= tlb_way2_pid_match; +tlb_cmp_dbg_way2_lpid_match <= tlb_way2_lpid_match; +tlb_cmp_dbg_way2_ind_match <= tlb_way2_ind_match; +tlb_cmp_dbg_way2_iprot_match <= tlb_way2_iprot_match; +tlb_cmp_dbg_way3_entry_v <= lru_tag3_dataout_q(3); +tlb_cmp_dbg_way3_addr_match <= tlb_way3_addr_match; +tlb_cmp_dbg_way3_pgsize_match <= tlb_way3_pgsize_match; +tlb_cmp_dbg_way3_class_match <= tlb_way3_class_match; +tlb_cmp_dbg_way3_extclass_match <= tlb_way3_extclass_match; +tlb_cmp_dbg_way3_state_match <= tlb_way3_state_match; +tlb_cmp_dbg_way3_thdid_match <= tlb_way3_thdid_match; +tlb_cmp_dbg_way3_pid_match <= tlb_way3_pid_match; +tlb_cmp_dbg_way3_lpid_match <= tlb_way3_lpid_match; +tlb_cmp_dbg_way3_ind_match <= tlb_way3_ind_match; +tlb_cmp_dbg_way3_iprot_match <= tlb_way3_iprot_match; +unused_dc(0) <= or_reduce(LCB_DELAY_LCLKR_DC(1 TO 4)); +unused_dc(1) <= or_reduce(LCB_MPW1_DC_B(1 TO 4)); +unused_dc(2) <= PC_FUNC_SL_FORCE; +unused_dc(3) <= PC_FUNC_SL_THOLD_0_B; +unused_dc(4) <= TC_SCAN_DIS_DC_B; +unused_dc(5) <= TC_SCAN_DIAG_DC; +unused_dc(6) <= TC_LBIST_EN_DC; +unused_dc(7) <= TLB_TAG3_CLONE1_Q(70); +unused_dc(8) <= TLB_TAG3_CLONE1_Q(73); +unused_dc(9) <= or_reduce(TLB_TAG3_CLONE1_Q(99 TO 100)); +unused_dc(10) <= or_reduce(TLB_TAG3_CLONE1_Q(104 TO 109)); +unused_dc(11) <= TLB_TAG3_CLONE2_Q(70); +unused_dc(12) <= TLB_TAG3_CLONE2_Q(73); +unused_dc(13) <= or_reduce(TLB_TAG3_CLONE2_Q(99 TO 100)); +unused_dc(14) <= or_reduce(TLB_TAG3_CLONE2_Q(104 TO 109)); +unused_dc(15) <= '0'; +unused_dc(16) <= TLB_TAG3_CMPMASK_Q(4); +unused_dc(17) <= TLB_TAG3_CMPMASK_CLONE_Q(4); +unused_dc(18) <= or_reduce(MMUCR1_CLONE_Q(11) & MMUCR1_CLONE_Q(17)); +unused_dc(19) <= or_reduce(TLB_TAG4_TYPE_SIG(0 TO 3) & TLB_TAG4_TYPE_SIG(5)); +unused_dc(20) <= TLB_TAG4_ESEL_SIG(0); +unused_dc(21) <= or_reduce(TLB_TAG4_WQ_SIG); +unused_dc(22) <= or_reduce(TLB_TAG4_IS_SIG(1 TO 3)); +unused_dc(23) <= or_reduce(PTERELOAD_REQ_PTE_LAT(0 TO 9)); +unused_dc(24) <= or_reduce(PTERELOAD_REQ_PTE_LAT(50) & PTERELOAD_REQ_PTE_LAT(55) & PTERELOAD_REQ_PTE_LAT(62)); +unused_dc(25) <= or_reduce(MMUCR3_0(53) & MMUCR3_0(59)); +unused_dc(26) <= or_reduce(MMUCR3_1(53) & MMUCR3_1(59)); +unused_dc(27) <= or_reduce(MMUCR3_2(53) & MMUCR3_2(59)); +unused_dc(28) <= or_reduce(MMUCR3_3(53) & MMUCR3_3(59)); +unused_dc(29) <= TLB0CFG_PT; +unused_dc(30) <= or_reduce(TLB_DSI_Q); +unused_dc(31) <= or_reduce(TLB_ISI_Q); +unused_dc(32) <= or_reduce(LRAT_TAG3_LPN_SIG); +unused_dc(33) <= or_reduce(LRAT_TAG3_RPN_SIG); +unused_dc(34) <= or_reduce(LRAT_TAG4_LPN_SIG); +unused_dc(35) <= LRAT_TAG3_HIT_STATUS(0); +unused_dc(36) <= LRAT_TAG3_HIT_STATUS(3); +unused_dc(37) <= or_reduce(LRAT_TAG3_HIT_ENTRY); +unused_dc(38) <= or_reduce(LRAT_TAG4_HIT_ENTRY); +----------------------------------------------------------------------- +-- Latches +----------------------------------------------------------------------- +-- tag3 phase: tlb array data output way latches +tlb_way0_latch: tri_rlmreg_p + generic map (width => tlb_way0_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(12), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_way0_offset to tlb_way0_offset+tlb_way0_q'length-1), + scout => sov_0(tlb_way0_offset to tlb_way0_offset+tlb_way0_q'length-1), + din => tlb_way0_d(0 to tlb_way_width-1), + dout => tlb_way0_q(0 to tlb_way_width-1) ); +tlb_way1_latch: tri_rlmreg_p + generic map (width => tlb_way1_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(12), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_way1_offset to tlb_way1_offset+tlb_way1_q'length-1), + scout => sov_0(tlb_way1_offset to tlb_way1_offset+tlb_way1_q'length-1), + din => tlb_way1_d(0 to tlb_way_width-1), + dout => tlb_way1_q(0 to tlb_way_width-1) ); +tlb_way2_latch: tri_rlmreg_p + generic map (width => tlb_way2_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(13), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(tlb_way2_offset to tlb_way2_offset+tlb_way2_q'length-1), + scout => sov_1(tlb_way2_offset to tlb_way2_offset+tlb_way2_q'length-1), + din => tlb_way2_d(0 to tlb_way_width-1), + dout => tlb_way2_q(0 to tlb_way_width-1) ); +tlb_way3_latch: tri_rlmreg_p + generic map (width => tlb_way3_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(13), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(tlb_way3_offset to tlb_way3_offset+tlb_way3_q'length-1), + scout => sov_1(tlb_way3_offset to tlb_way3_offset+tlb_way3_q'length-1), + din => tlb_way3_d(0 to tlb_way_width-1), + dout => tlb_way3_q(0 to tlb_way_width-1) ); +-- tag3 phase: from tag forwarding pipeline +tlb_tag3_latch: tri_rlmreg_p + generic map (width => tlb_tag3_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(9), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(tlb_tag3_offset to tlb_tag3_offset+tlb_tag3_q'length-1), + scout => sov_2(tlb_tag3_offset to tlb_tag3_offset+tlb_tag3_q'length-1), + din => tlb_tag3_d(0 to tlb_tag_width-1), + dout => tlb_tag3_q(0 to tlb_tag_width-1) ); +tlb_tag3_clone1_latch: tri_rlmreg_p + generic map (width => tlb_tag3_clone1_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(12), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_tag3_clone1_offset to tlb_tag3_clone1_offset+tlb_tag3_clone1_q'length-1), + scout => sov_0(tlb_tag3_clone1_offset to tlb_tag3_clone1_offset+tlb_tag3_clone1_q'length-1), + din => tlb_tag3_clone1_d(0 to tlb_tag_width-1), + dout => tlb_tag3_clone1_q(0 to tlb_tag_width-1) ); +tlb_tag3_clone2_latch: tri_rlmreg_p + generic map (width => tlb_tag3_clone2_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(13), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(tlb_tag3_clone2_offset to tlb_tag3_clone2_offset+tlb_tag3_clone2_q'length-1), + scout => sov_1(tlb_tag3_clone2_offset to tlb_tag3_clone2_offset+tlb_tag3_clone2_q'length-1), + din => tlb_tag3_clone2_d(0 to tlb_tag_width-1), + dout => tlb_tag3_clone2_q(0 to tlb_tag_width-1) ); +-- tag3 phase: from tlb_ctl pipeline addr forwarding +tlb_addr3_latch: tri_rlmreg_p + generic map (width => tlb_addr3_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(9), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(tlb_addr3_offset to tlb_addr3_offset+tlb_addr3_q'length-1), + scout => sov_2(tlb_addr3_offset to tlb_addr3_offset+tlb_addr3_q'length-1), + din => tlb_addr3_d(0 to tlb_addr_width-1), + dout => tlb_addr3_q(0 to tlb_addr_width-1) ); +-- lru g8t array is 2 cyc, data out is in tag3 now +-- tag3 phase: from lru data output +lru_tag3_dataout_latch: tri_rlmreg_p + generic map (width => lru_tag3_dataout_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(9), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(lru_tag3_dataout_offset to lru_tag3_dataout_offset+lru_tag3_dataout_q'length-1), + scout => sov_2(lru_tag3_dataout_offset to lru_tag3_dataout_offset+lru_tag3_dataout_q'length-1), + din => lru_tag3_dataout_d(0 to 15), + dout => lru_tag3_dataout_q(0 to 15) ); +-- tag3 phase: size decoded compare mask tag bits +tlb_tag3_cmpmask_latch: tri_rlmreg_p + generic map (width => tlb_tag3_cmpmask_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(12), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_tag3_cmpmask_offset to tlb_tag3_cmpmask_offset+tlb_tag3_cmpmask_q'length-1), + scout => sov_0(tlb_tag3_cmpmask_offset to tlb_tag3_cmpmask_offset+tlb_tag3_cmpmask_q'length-1), + din => tlb_tag3_cmpmask_d, + dout => tlb_tag3_cmpmask_q ); +tlb_tag3_cmpmask_clone_latch: tri_rlmreg_p + generic map (width => tlb_tag3_cmpmask_clone_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(13), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(tlb_tag3_cmpmask_clone_offset to tlb_tag3_cmpmask_clone_offset+tlb_tag3_cmpmask_clone_q'length-1), + scout => sov_1(tlb_tag3_cmpmask_clone_offset to tlb_tag3_cmpmask_clone_offset+tlb_tag3_cmpmask_clone_q'length-1), + din => tlb_tag3_cmpmask_clone_d, + dout => tlb_tag3_cmpmask_clone_q ); +-- tag3 phase: size decoded compare mask way bits +tlb_way0_cmpmask_latch: tri_rlmreg_p + generic map (width => tlb_way0_cmpmask_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(12), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_way0_cmpmask_offset to tlb_way0_cmpmask_offset+tlb_way0_cmpmask_q'length-1), + scout => sov_0(tlb_way0_cmpmask_offset to tlb_way0_cmpmask_offset+tlb_way0_cmpmask_q'length-1), + din => tlb_way0_cmpmask_d, + dout => tlb_way0_cmpmask_q ); +tlb_way1_cmpmask_latch: tri_rlmreg_p + generic map (width => tlb_way1_cmpmask_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(12), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_way1_cmpmask_offset to tlb_way1_cmpmask_offset+tlb_way1_cmpmask_q'length-1), + scout => sov_0(tlb_way1_cmpmask_offset to tlb_way1_cmpmask_offset+tlb_way1_cmpmask_q'length-1), + din => tlb_way1_cmpmask_d, + dout => tlb_way1_cmpmask_q ); +tlb_way2_cmpmask_latch: tri_rlmreg_p + generic map (width => tlb_way2_cmpmask_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(13), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(tlb_way2_cmpmask_offset to tlb_way2_cmpmask_offset+tlb_way2_cmpmask_q'length-1), + scout => sov_1(tlb_way2_cmpmask_offset to tlb_way2_cmpmask_offset+tlb_way2_cmpmask_q'length-1), + din => tlb_way2_cmpmask_d, + dout => tlb_way2_cmpmask_q ); +tlb_way3_cmpmask_latch: tri_rlmreg_p + generic map (width => tlb_way3_cmpmask_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(13), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(tlb_way3_cmpmask_offset to tlb_way3_cmpmask_offset+tlb_way3_cmpmask_q'length-1), + scout => sov_1(tlb_way3_cmpmask_offset to tlb_way3_cmpmask_offset+tlb_way3_cmpmask_q'length-1), + din => tlb_way3_cmpmask_d, + dout => tlb_way3_cmpmask_q ); +tlb_way0_xbitmask_latch: tri_rlmreg_p + generic map (width => tlb_way0_xbitmask_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(12), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_way0_xbitmask_offset to tlb_way0_xbitmask_offset+tlb_way0_xbitmask_q'length-1), + scout => sov_0(tlb_way0_xbitmask_offset to tlb_way0_xbitmask_offset+tlb_way0_xbitmask_q'length-1), + din => tlb_way0_xbitmask_d, + dout => tlb_way0_xbitmask_q ); +tlb_way1_xbitmask_latch: tri_rlmreg_p + generic map (width => tlb_way1_xbitmask_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(12), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_way1_xbitmask_offset to tlb_way1_xbitmask_offset+tlb_way1_xbitmask_q'length-1), + scout => sov_0(tlb_way1_xbitmask_offset to tlb_way1_xbitmask_offset+tlb_way1_xbitmask_q'length-1), + din => tlb_way1_xbitmask_d, + dout => tlb_way1_xbitmask_q ); +tlb_way2_xbitmask_latch: tri_rlmreg_p + generic map (width => tlb_way2_xbitmask_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(13), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(tlb_way2_xbitmask_offset to tlb_way2_xbitmask_offset+tlb_way2_xbitmask_q'length-1), + scout => sov_1(tlb_way2_xbitmask_offset to tlb_way2_xbitmask_offset+tlb_way2_xbitmask_q'length-1), + din => tlb_way2_xbitmask_d, + dout => tlb_way2_xbitmask_q ); +tlb_way3_xbitmask_latch: tri_rlmreg_p + generic map (width => tlb_way3_xbitmask_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(13), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(tlb_way3_xbitmask_offset to tlb_way3_xbitmask_offset+tlb_way3_xbitmask_q'length-1), + scout => sov_1(tlb_way3_xbitmask_offset to tlb_way3_xbitmask_offset+tlb_way3_xbitmask_q'length-1), + din => tlb_way3_xbitmask_d, + dout => tlb_way3_xbitmask_q ); +-- tag4 phase +tlb_tag4_latch: tri_rlmreg_p + generic map (width => tlb_tag4_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(10), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(tlb_tag4_offset to tlb_tag4_offset+tlb_tag4_q'length-1), + scout => sov_2(tlb_tag4_offset to tlb_tag4_offset+tlb_tag4_q'length-1), + din => tlb_tag4_d(0 to tlb_tag_width-1), + dout => tlb_tag4_q(0 to tlb_tag_width-1) ); +tlb_tag4_wayhit_latch: tri_rlmreg_p + generic map (width => tlb_tag4_wayhit_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(10), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(tlb_tag4_wayhit_offset to tlb_tag4_wayhit_offset+tlb_tag4_wayhit_q'length-1), + scout => sov_2(tlb_tag4_wayhit_offset to tlb_tag4_wayhit_offset+tlb_tag4_wayhit_q'length-1), + din => tlb_tag4_wayhit_d(0 to tlb_ways), + dout => tlb_tag4_wayhit_q(0 to tlb_ways) ); +tlb_addr4_latch: tri_rlmreg_p + generic map (width => tlb_addr4_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(10), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(tlb_addr4_offset to tlb_addr4_offset+tlb_addr4_q'length-1), + scout => sov_2(tlb_addr4_offset to tlb_addr4_offset+tlb_addr4_q'length-1), + din => tlb_addr4_d(0 to tlb_addr_width-1), + dout => tlb_addr4_q(0 to tlb_addr_width-1) ); +tlb_dataina_latch: tri_rlmreg_p + generic map (width => tlb_dataina_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(14), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_dataina_offset to tlb_dataina_offset+tlb_dataina_q'length-1), + scout => sov_0(tlb_dataina_offset to tlb_dataina_offset+tlb_dataina_q'length-1), + din => tlb_dataina_d(0 to tlb_way_width-1), + dout => tlb_dataina_q(0 to tlb_way_width-1) ); +tlb_datainb_latch: tri_rlmreg_p + generic map (width => tlb_datainb_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(15), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(tlb_datainb_offset to tlb_datainb_offset+tlb_datainb_q'length-1), + scout => sov_1(tlb_datainb_offset to tlb_datainb_offset+tlb_datainb_q'length-1), + din => tlb_datainb_d(0 to tlb_way_width-1), + dout => tlb_datainb_q(0 to tlb_way_width-1) ); +lru_tag4_dataout_latch: tri_rlmreg_p + generic map (width => lru_tag4_dataout_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(10), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(lru_tag4_dataout_offset to lru_tag4_dataout_offset+lru_tag4_dataout_q'length-1), + scout => sov_2(lru_tag4_dataout_offset to lru_tag4_dataout_offset+lru_tag4_dataout_q'length-1), + din => lru_tag4_dataout_d(0 to 15), + dout => lru_tag4_dataout_q(0 to 15) ); +tlb_tag4_way_latch: tri_rlmreg_p + generic map (width => tlb_tag4_way_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_tag4_way_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_tag4_way_offset to tlb_tag4_way_offset+tlb_tag4_way_q'length-1), + scout => sov_0(tlb_tag4_way_offset to tlb_tag4_way_offset+tlb_tag4_way_q'length-1), + din => tlb_tag4_way_d(0 to tlb_way_width-1), + dout => tlb_tag4_way_q(0 to tlb_way_width-1) ); +tlb_tag4_way_clone_latch: tri_rlmreg_p + generic map (width => tlb_tag4_way_clone_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_tag4_way_clone_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(tlb_tag4_way_clone_offset to tlb_tag4_way_clone_offset+tlb_tag4_way_clone_q'length-1), + scout => sov_1(tlb_tag4_way_clone_offset to tlb_tag4_way_clone_offset+tlb_tag4_way_clone_q'length-1), + din => tlb_tag4_way_clone_d(0 to tlb_way_width-1), + dout => tlb_tag4_way_clone_q(0 to tlb_way_width-1) ); +tlb_tag4_way_rw_latch: tri_rlmreg_p + generic map (width => tlb_tag4_way_rw_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_tag4_way_rw_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_tag4_way_rw_offset to tlb_tag4_way_rw_offset+tlb_tag4_way_rw_q'length-1), + scout => sov_0(tlb_tag4_way_rw_offset to tlb_tag4_way_rw_offset+tlb_tag4_way_rw_q'length-1), + din => tlb_tag4_way_rw_d(0 to tlb_way_width-1), + dout => tlb_tag4_way_rw_q(0 to tlb_way_width-1) ); +tlb_tag4_way_rw_clone_latch: tri_rlmreg_p + generic map (width => tlb_tag4_way_rw_clone_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_tag4_way_rw_clone_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(tlb_tag4_way_rw_clone_offset to tlb_tag4_way_rw_clone_offset+tlb_tag4_way_rw_clone_q'length-1), + scout => sov_1(tlb_tag4_way_rw_clone_offset to tlb_tag4_way_rw_clone_offset+tlb_tag4_way_rw_clone_q'length-1), + din => tlb_tag4_way_rw_clone_d(0 to tlb_way_width-1), + dout => tlb_tag4_way_rw_clone_q(0 to tlb_way_width-1) ); +tlbwe_tag4_back_inv_latch: tri_rlmreg_p + generic map (width => tlbwe_tag4_back_inv_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(10), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(tlbwe_tag4_back_inv_offset to tlbwe_tag4_back_inv_offset+tlbwe_tag4_back_inv_q'length-1), + scout => sov_2(tlbwe_tag4_back_inv_offset to tlbwe_tag4_back_inv_offset+tlbwe_tag4_back_inv_q'length-1), + din => tlbwe_tag4_back_inv_d, + dout => tlbwe_tag4_back_inv_q ); +tlbwe_tag4_back_inv_attr_latch: tri_rlmreg_p + generic map (width => tlbwe_tag4_back_inv_attr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(10), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(tlbwe_tag4_back_inv_attr_offset to tlbwe_tag4_back_inv_attr_offset+tlbwe_tag4_back_inv_attr_q'length-1), + scout => sov_2(tlbwe_tag4_back_inv_attr_offset to tlbwe_tag4_back_inv_attr_offset+tlbwe_tag4_back_inv_attr_q'length-1), + din => tlbwe_tag4_back_inv_attr_d, + dout => tlbwe_tag4_back_inv_attr_q ); +-- tag5 phase +tlb_erat_val_latch: tri_rlmreg_p + generic map (width => tlb_erat_val_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(14), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(tlb_erat_val_offset to tlb_erat_val_offset+tlb_erat_val_q'length-1), + scout => sov_2(tlb_erat_val_offset to tlb_erat_val_offset+tlb_erat_val_q'length-1), + din => tlb_erat_val_d(0 to 2*thdid_width+1), + dout => tlb_erat_val_q(0 to 2*thdid_width+1) ); +tlb_erat_rel_latch: tri_rlmreg_p + generic map (width => tlb_erat_rel_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(14), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_erat_rel_offset to tlb_erat_rel_offset+tlb_erat_rel_q'length-1), + scout => sov_0(tlb_erat_rel_offset to tlb_erat_rel_offset+tlb_erat_rel_q'length-1), + din => tlb_erat_rel_d(0 to erat_rel_data_width-1), + dout => tlb_erat_rel_q(0 to erat_rel_data_width-1) ); +tlb_erat_rel_clone_latch: tri_rlmreg_p + generic map (width => tlb_erat_rel_clone_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(15), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(tlb_erat_rel_clone_offset to tlb_erat_rel_clone_offset+tlb_erat_rel_clone_q'length-1), + scout => sov_1(tlb_erat_rel_clone_offset to tlb_erat_rel_clone_offset+tlb_erat_rel_clone_q'length-1), + din => tlb_erat_rel_clone_d(0 to erat_rel_data_width-1), + dout => tlb_erat_rel_clone_q(0 to erat_rel_data_width-1) ); +tlb_erat_dup_latch: tri_rlmreg_p + generic map (width => tlb_erat_dup_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(tlb_erat_dup_offset to tlb_erat_dup_offset+tlb_erat_dup_q'length-1), + scout => sov_2(tlb_erat_dup_offset to tlb_erat_dup_offset+tlb_erat_dup_q'length-1), + din => tlb_erat_dup_d, + dout => tlb_erat_dup_q ); +lru_write_latch: tri_rlmreg_p + generic map (width => lru_write_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(11), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(lru_write_offset to lru_write_offset+lru_write_q'length-1), + scout => sov_2(lru_write_offset to lru_write_offset+lru_write_q'length-1), + din => lru_write_d(0 to 15), + dout => lru_write_q(0 to 15) ); +lru_wr_addr_latch: tri_rlmreg_p + generic map (width => lru_wr_addr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(11), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(lru_wr_addr_offset to lru_wr_addr_offset+lru_wr_addr_q'length-1), + scout => sov_2(lru_wr_addr_offset to lru_wr_addr_offset+lru_wr_addr_q'length-1), + din => lru_wr_addr_d(0 to tlb_addr_width-1), + dout => lru_wr_addr_q(0 to tlb_addr_width-1) ); +lru_datain_latch: tri_rlmreg_p + generic map (width => lru_datain_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(11), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(lru_datain_offset to lru_datain_offset+lru_datain_q'length-1), + scout => sov_2(lru_datain_offset to lru_datain_offset+lru_datain_q'length-1), + din => lru_datain_d(0 to 15), + dout => lru_datain_q(0 to 15) ); +eratmiss_done_latch: tri_rlmreg_p + generic map (width => eratmiss_done_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(16), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(eratmiss_done_offset to eratmiss_done_offset+eratmiss_done_q'length-1), + scout => sov_2(eratmiss_done_offset to eratmiss_done_offset+eratmiss_done_q'length-1), + din => eratmiss_done_d(0 to thdid_width-1), + dout => eratmiss_done_q(0 to thdid_width-1)); +tlb_miss_latch: tri_rlmreg_p + generic map (width => tlb_miss_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(16), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(tlb_miss_offset to tlb_miss_offset+tlb_miss_q'length-1), + scout => sov_2(tlb_miss_offset to tlb_miss_offset+tlb_miss_q'length-1), + din => tlb_miss_d(0 to thdid_width-1), + dout => tlb_miss_q(0 to thdid_width-1)); +tlb_inelig_latch: tri_rlmreg_p + generic map (width => tlb_inelig_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(16), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(tlb_inelig_offset to tlb_inelig_offset+tlb_inelig_q'length-1), + scout => sov_2(tlb_inelig_offset to tlb_inelig_offset+tlb_inelig_q'length-1), + din => tlb_inelig_d(0 to thdid_width-1), + dout => tlb_inelig_q(0 to thdid_width-1)); +lrat_miss_latch: tri_rlmreg_p + generic map (width => lrat_miss_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(16), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(lrat_miss_offset to lrat_miss_offset+lrat_miss_q'length-1), + scout => sov_2(lrat_miss_offset to lrat_miss_offset+lrat_miss_q'length-1), + din => lrat_miss_d(0 to thdid_width-1), + dout => lrat_miss_q(0 to thdid_width-1)); +pt_fault_latch: tri_rlmreg_p + generic map (width => pt_fault_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(16), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(pt_fault_offset to pt_fault_offset+pt_fault_q'length-1), + scout => sov_2(pt_fault_offset to pt_fault_offset+pt_fault_q'length-1), + din => pt_fault_d(0 to thdid_width-1), + dout => pt_fault_q(0 to thdid_width-1)); +hv_priv_latch: tri_rlmreg_p + generic map (width => hv_priv_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(16), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(hv_priv_offset to hv_priv_offset+hv_priv_q'length-1), + scout => sov_2(hv_priv_offset to hv_priv_offset+hv_priv_q'length-1), + din => hv_priv_d(0 to thdid_width-1), + dout => hv_priv_q(0 to thdid_width-1)); +tlb_tag5_except_latch: tri_rlmreg_p + generic map (width => tlb_tag5_except_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(11), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(tlb_tag5_except_offset to tlb_tag5_except_offset+tlb_tag5_except_q'length-1), + scout => sov_2(tlb_tag5_except_offset to tlb_tag5_except_offset+tlb_tag5_except_q'length-1), + din => tlb_tag5_except_d(0 to thdid_width-1), + dout => tlb_tag5_except_q(0 to thdid_width-1)); +tlb_dsi_latch: tri_rlmreg_p + generic map (width => tlb_dsi_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(16), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(tlb_dsi_offset to tlb_dsi_offset+tlb_dsi_q'length-1), + scout => sov_2(tlb_dsi_offset to tlb_dsi_offset+tlb_dsi_q'length-1), + din => tlb_dsi_d(0 to thdid_width-1), + dout => tlb_dsi_q(0 to thdid_width-1)); +tlb_isi_latch: tri_rlmreg_p + generic map (width => tlb_isi_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(16), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(tlb_isi_offset to tlb_isi_offset+tlb_isi_q'length-1), + scout => sov_2(tlb_isi_offset to tlb_isi_offset+tlb_isi_q'length-1), + din => tlb_isi_d(0 to thdid_width-1), + dout => tlb_isi_q(0 to thdid_width-1)); +esr_pt_latch: tri_rlmreg_p + generic map (width => esr_pt_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(16), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(esr_pt_offset to esr_pt_offset+esr_pt_q'length-1), + scout => sov_2(esr_pt_offset to esr_pt_offset+esr_pt_q'length-1), + din => esr_pt_d(0 to thdid_width-1), + dout => esr_pt_q(0 to thdid_width-1)); +esr_data_latch: tri_rlmreg_p + generic map (width => esr_data_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(16), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(esr_data_offset to esr_data_offset+esr_data_q'length-1), + scout => sov_2(esr_data_offset to esr_data_offset+esr_data_q'length-1), + din => esr_data_d(0 to thdid_width-1), + dout => esr_data_q(0 to thdid_width-1)); +esr_st_latch: tri_rlmreg_p + generic map (width => esr_st_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(16), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(esr_st_offset to esr_st_offset+esr_st_q'length-1), + scout => sov_2(esr_st_offset to esr_st_offset+esr_st_q'length-1), + din => esr_st_d(0 to thdid_width-1), + dout => esr_st_q(0 to thdid_width-1)); +esr_epid_latch: tri_rlmreg_p + generic map (width => esr_epid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(16), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(esr_epid_offset to esr_epid_offset+esr_epid_q'length-1), + scout => sov_2(esr_epid_offset to esr_epid_offset+esr_epid_q'length-1), + din => esr_epid_d(0 to thdid_width-1), + dout => esr_epid_q(0 to thdid_width-1)); +cr0_eq_latch: tri_rlmreg_p + generic map (width => cr0_eq_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(16), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(cr0_eq_offset to cr0_eq_offset+cr0_eq_q'length-1), + scout => sov_2(cr0_eq_offset to cr0_eq_offset+cr0_eq_q'length-1), + din => cr0_eq_d(0 to thdid_width-1), + dout => cr0_eq_q(0 to thdid_width-1)); +cr0_eq_valid_latch: tri_rlmreg_p + generic map (width => cr0_eq_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(16), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(cr0_eq_valid_offset to cr0_eq_valid_offset+cr0_eq_valid_q'length-1), + scout => sov_2(cr0_eq_valid_offset to cr0_eq_valid_offset+cr0_eq_valid_q'length-1), + din => cr0_eq_valid_d(0 to thdid_width-1), + dout => cr0_eq_valid_q(0 to thdid_width-1)); +tlb_multihit_err_latch: tri_rlmreg_p + generic map (width => tlb_multihit_err_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(16), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(tlb_multihit_err_offset to tlb_multihit_err_offset+tlb_multihit_err_q'length-1), + scout => sov_2(tlb_multihit_err_offset to tlb_multihit_err_offset+tlb_multihit_err_q'length-1), + din => tlb_multihit_err_d(0 to thdid_width-1), + dout => tlb_multihit_err_q(0 to thdid_width-1)); +tag4_parerr_latch: tri_rlmreg_p + generic map (width => tag4_parerr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(10), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(tag4_parerr_offset to tag4_parerr_offset+tag4_parerr_q'length-1), + scout => sov_2(tag4_parerr_offset to tag4_parerr_offset+tag4_parerr_q'length-1), + din => tag4_parerr_d, + dout => tag4_parerr_q ); +tlb_par_err_latch: tri_rlmreg_p + generic map (width => tlb_par_err_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(16), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(tlb_par_err_offset to tlb_par_err_offset+tlb_par_err_q'length-1), + scout => sov_2(tlb_par_err_offset to tlb_par_err_offset+tlb_par_err_q'length-1), + din => ECO107332_tlb_par_err_d(0 to thdid_width-1), + dout => tlb_par_err_q(0 to thdid_width-1)); +lru_par_err_latch: tri_rlmreg_p + generic map (width => lru_par_err_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(16), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(lru_par_err_offset to lru_par_err_offset+lru_par_err_q'length-1), + scout => sov_2(lru_par_err_offset to lru_par_err_offset+lru_par_err_q'length-1), + din => ECO107332_lru_par_err_d(0 to thdid_width-1), + dout => lru_par_err_q(0 to thdid_width-1)); +-- Changed these to scannable to fix nsl > 1 depth into mmq_dbg nsl's +mmucr1_latch: tri_rlmreg_p + generic map (width => mmucr1_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(mmucr1_offset to mmucr1_offset+mmucr1_q'length-1), + scout => sov_0(mmucr1_offset to mmucr1_offset+mmucr1_q'length-1), + din => mmucr1, + dout => mmucr1_q ); +-- Changed these to scannable to fix nsl > 1 depth into mmq_dbg nsl's +mmucr1_clone_latch: tri_rlmreg_p + generic map (width => mmucr1_clone_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mmucr1_clone_offset to mmucr1_clone_offset+mmucr1_clone_q'length-1), + scout => sov_1(mmucr1_clone_offset to mmucr1_clone_offset+mmucr1_clone_q'length-1), + din => mmucr1, + dout => mmucr1_clone_q ); +spare_a_latch: tri_rlmreg_p + generic map (width => spare_a_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(14), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spare_a_offset to spare_a_offset+spare_a_q'length-1), + scout => sov_0(spare_a_offset to spare_a_offset+spare_a_q'length-1), + din => spare_a_q, + dout => spare_a_q ); +spare_b_latch: tri_rlmreg_p + generic map (width => spare_b_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(15), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spare_b_offset to spare_b_offset+spare_b_q'length-1), + scout => sov_1(spare_b_offset to spare_b_offset+spare_b_q'length-1), + din => spare_b_q, + dout => spare_b_q ); +cswitch_latch: tri_rlmreg_p + generic map (width => cswitch_q'length, init => mmq_tlb_cmp_cswitch_0to7, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(cswitch_offset to cswitch_offset+cswitch_q'length-1), + scout => sov_2(cswitch_offset to cswitch_offset+cswitch_q'length-1), + din => cswitch_q, + dout => cswitch_q ); +-- cswitch0: 1= allow tlbwe back inv for iprot=1 entries only +-- cswitch1: 1= allow tlbwe back inv for hes=1 (lru selected) +-- cswitch2: 1= allow tlbwe back inv that ignores erat extclass for iprot=1 entries only +-- cswitch3: 1= allow tlbwe back inv for ind=1 entries +-- cswitch4: 1= allow tlbwe back inv for ind=1 entries +-- cswitch5: 1= allow tlbsx hit with parerr to update mas regs +-- cswitch6: 1= allow tlbsx miss with parerr to update mas regs +-- cswitch7: 1= allow tlbre with parerr to update mas regs +spare_c_latch: tri_rlmreg_p + generic map (width => spare_c_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(16), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_2(spare_c_offset to spare_c_offset+spare_c_q'length-1), + scout => sov_2(spare_c_offset to spare_c_offset+spare_c_q'length-1), + din => spare_c_q, + dout => spare_c_q ); +-- non-scannable timing latches +-- Changed these to spares +spare_nsl_latch : tri_regk + generic map (width => spare_nsl_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => xu_mm_ccr2_notlb_b, + forcee => pc_func_slp_nsl_force(0), + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_nsl_thold_0_b(0), + din => spare_nsl_q, + dout => spare_nsl_q); +spare_nsl_clone_latch : tri_regk + generic map (width => spare_nsl_clone_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => xu_mm_ccr2_notlb_b, + forcee => pc_func_slp_nsl_force(1), + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_nsl_thold_0_b(1), + din => spare_nsl_clone_q, + dout => spare_nsl_clone_q); +epcr_dmiuh_latch : tri_regk + generic map (width => epcr_dmiuh_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => xu_mm_ccr2_notlb_b, + forcee => pc_func_slp_nsl_force(0), + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_nsl_thold_0_b(0), + din => xu_mm_spr_epcr_dmiuh, + dout => epcr_dmiuh_q); +msr_gs_latch : tri_regk + generic map (width => msr_gs_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => xu_mm_ccr2_notlb_b, + forcee => pc_func_slp_nsl_force(0), + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_nsl_thold_0_b(0), + din => xu_mm_msr_gs, + dout => msr_gs_q); +msr_pr_latch : tri_regk + generic map (width => msr_pr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => xu_mm_ccr2_notlb_b, + forcee => pc_func_slp_nsl_force(0), + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_nsl_thold_0_b(0), + din => xu_mm_msr_pr, + dout => msr_pr_q); +-------------------------------------------------- +-- thold/sg latches +-------------------------------------------------- +perv_2to1_reg: tri_plat + generic map (width => 5, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ccflush_dc, + din(0) => pc_func_sl_thold_2, + din(1) => pc_func_slp_sl_thold_2, + din(2) => pc_func_slp_nsl_thold_2, + din(3) => pc_sg_2, + din(4) => pc_fce_2, + q(0) => pc_func_sl_thold_1, + q(1) => pc_func_slp_sl_thold_1, + q(2) => pc_func_slp_nsl_thold_1, + q(3) => pc_sg_1, + q(4) => pc_fce_1); +perv_1to0_reg: tri_plat + generic map (width => 5, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ccflush_dc, + din(0) => pc_func_sl_thold_1, + din(1) => pc_func_slp_sl_thold_1, + din(2) => pc_func_slp_nsl_thold_1, + din(3) => pc_sg_1, + din(4) => pc_fce_1, + q(0) => pc_func_sl_thold_0, + q(1) => pc_func_slp_sl_thold_0, + q(2) => pc_func_slp_nsl_thold_0, + q(3) => pc_sg_0, + q(4) => pc_fce_0); +perv_lcbor_func_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b, + thold => pc_func_sl_thold_0, + sg => pc_sg_0, + act_dis => lcb_act_dis_dc, + forcee => pc_func_sl_force, + thold_b => pc_func_sl_thold_0_b); +perv_lcbor_func_slp_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b, + thold => pc_func_slp_sl_thold_0, + sg => pc_sg_0, + act_dis => lcb_act_dis_dc, + forcee => pc_func_slp_sl_force, + thold_b => pc_func_slp_sl_thold_0_b); +perv_nsl_lcbor: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b, + thold => pc_func_slp_nsl_thold_0, + sg => pc_fce_0, + act_dis => tidn, + forcee => pc_func_slp_nsl_force(0), + thold_b => pc_func_slp_nsl_thold_0_b(0)); +perv_nsl_lcbor_clone: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b, + thold => pc_func_slp_nsl_thold_0, + sg => pc_fce_0, + act_dis => tidn, + forcee => pc_func_slp_nsl_force(1), + thold_b => pc_func_slp_nsl_thold_0_b(1)); +----------------------------------------------------------------------- +-- Scan +----------------------------------------------------------------------- +siv_0(0 TO scan_right_0) <= sov_0(1 to scan_right_0) & ac_func_scan_in(0); +ac_func_scan_out(0) <= sov_0(0); +siv_1(0 TO scan_right_1) <= sov_1(1 to scan_right_1) & ac_func_scan_in(1); +ac_func_scan_out(1) <= sov_1(0); +siv_2(0 TO scan_right_2) <= sov_2(1 to scan_right_2) & ac_func_scan_in(2); +ac_func_scan_out(2) <= sov_2(0); +END MMQ_TLB_CMP; diff --git a/rel/src/vhdl/work/mmq_tlb_ctl.vhdl b/rel/src/vhdl/work/mmq_tlb_ctl.vhdl new file mode 100644 index 0000000..743e7d8 --- /dev/null +++ b/rel/src/vhdl/work/mmq_tlb_ctl.vhdl @@ -0,0 +1,4645 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +--******************************************************************** +--* TITLE: Memory Management Unit TLB Central Control Logic +--* NAME: mmq_tlb_ctl.vhdl +--********************************************************************* + +library ieee; +use ieee.std_logic_1164.all; +library ibm; +use ibm.std_ulogic_unsigned.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_support.all; +library support; +use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity mmq_tlb_ctl is + generic(thdid_width : integer := 4; + ttype_width : integer := 5; + state_width : integer := 4; + pid_width : integer := 14; + lpid_width : integer := 8; + class_width : integer := 2; + extclass_width : integer := 2; + tlbsel_width : integer := 2; + epn_width : integer := 52; + req_epn_width : integer := 52; + vpn_width : integer := 61; + erat_cam_data_width : integer := 75; + erat_ary_data_width : integer := 73; + ws_width : integer := 2; + rs_is_width : integer := 9; + ra_entry_width : integer := 12; + rs_data_width : integer := 64; + data_out_width : integer := 64; + error_width : integer := 3; + tlb_num_entry : natural := 512; + tlb_num_entry_log2 : natural := 9; + tlb_ways : natural := 4; + tlb_addr_width : natural := 7; + tlb_way_width : natural := 168; + tlb_word_width : natural := 84; + tlb_seq_width : integer := 6; + inv_seq_width : integer := 5; + watermark_width : integer := 4; + eptr_width : integer := 4; + lru_width : integer := 26; + mmucr0_width : integer := 20; + mmucr1_width : integer := 32; + mmucr2_width : integer := 32; + mmucr3_width : integer := 15; + spr_ctl_width : integer := 3; + spr_etid_width : integer := 2; + spr_addr_width : integer := 10; + spr_data_width : integer := 64; + debug_trace_width : integer := 88; + debug_event_width : integer := 16; + real_addr_width : integer := 42; + rpn_width : integer := 30; + pte_width : integer := 64; + tlb_tag_width : natural := 110; + expand_type : integer := 2 ); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + +tc_ccflush_dc : in std_ulogic; +tc_scan_dis_dc_b : in std_ulogic; +tc_scan_diag_dc : in std_ulogic; +tc_lbist_en_dc : in std_ulogic; +lcb_d_mode_dc : in std_ulogic; +lcb_clkoff_dc_b : in std_ulogic; +lcb_act_dis_dc : in std_ulogic; +lcb_mpw1_dc_b : in std_ulogic_vector(0 to 4); +lcb_mpw2_dc_b : in std_ulogic; +lcb_delay_lclkr_dc : in std_ulogic_vector(0 to 4); +ac_func_scan_in :in std_ulogic; +ac_func_scan_out :out std_ulogic; +pc_sg_2 : in std_ulogic; +pc_func_sl_thold_2 : in std_ulogic; +pc_func_slp_sl_thold_2 : in std_ulogic; +pc_func_slp_nsl_thold_2 : in std_ulogic; +pc_fce_2 : in std_ulogic; +xu_mm_rf1_val : in std_ulogic_vector(0 to 3); +xu_mm_rf1_is_tlbre : in std_ulogic; +xu_mm_rf1_is_tlbwe : in std_ulogic; +xu_mm_rf1_is_tlbsx : in std_ulogic; +xu_mm_rf1_is_tlbsxr : in std_ulogic; +xu_mm_rf1_is_tlbsrx : in std_ulogic; +xu_mm_ex2_epn : in std_ulogic_vector(64-rs_data_width to 51); +xu_mm_msr_gs : in std_ulogic_vector(0 to thdid_width-1); +xu_mm_msr_pr : in std_ulogic_vector(0 to thdid_width-1); +xu_mm_msr_is : in std_ulogic_vector(0 to thdid_width-1); +xu_mm_msr_ds : in std_ulogic_vector(0 to thdid_width-1); +xu_mm_msr_cm : in std_ulogic_vector(0 to thdid_width-1); +xu_mm_ccr2_notlb_b : in std_ulogic; +xu_mm_epcr_dgtmi : in std_ulogic_vector(0 to thdid_width-1); +xu_mm_xucr4_mmu_mchk : in std_ulogic; +xu_mm_xucr4_mmu_mchk_q : out std_ulogic; +xu_rf1_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_ex1_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_ex2_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_ex3_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_ex4_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_ex5_flush : in std_ulogic_vector(0 to thdid_width-1); +tlb_ctl_ex3_valid : out std_ulogic_vector(0 to thdid_width-1); +tlb_ctl_ex3_ttype : out std_ulogic_vector(0 to ttype_width-1); +tlb_ctl_tag2_flush : out std_ulogic_vector(0 to thdid_width-1); +tlb_ctl_tag3_flush : out std_ulogic_vector(0 to thdid_width-1); +tlb_ctl_tag4_flush : out std_ulogic_vector(0 to thdid_width-1); +tlb_resv_match_vec : out std_ulogic_vector(0 to thdid_width-1); +mm_xu_eratmiss_done : in std_ulogic_vector(0 to thdid_width-1); +mm_xu_tlb_miss : in std_ulogic_vector(0 to thdid_width-1); +mm_xu_tlb_inelig : in std_ulogic_vector(0 to thdid_width-1); +tlb_ctl_barrier_done : out std_ulogic_vector(0 to thdid_width-1); +tlb_ctl_ex2_flush_req : out std_ulogic_vector(0 to thdid_width-1); +tlb_ctl_quiesce : out std_ulogic_vector(0 to thdid_width-1); +tlb_ctl_ex2_illeg_instr : out std_ulogic_vector(0 to thdid_width-1); +ex6_illeg_instr : out std_ulogic_vector(0 to 1); +tlbwe_back_inv_pending : in std_ulogic; +pid0 : in std_ulogic_vector(0 to pid_width-1); +pid1 : in std_ulogic_vector(0 to pid_width-1); +pid2 : in std_ulogic_vector(0 to pid_width-1); +pid3 : in std_ulogic_vector(0 to pid_width-1); +mmucr1_tlbi_msb : in std_ulogic; +mmucr1_tlbwe_binv : in std_ulogic; +mmucr2 : in std_ulogic_vector(0 to mmucr2_width-1); +mmucr3_0 : in std_ulogic_vector(64-mmucr3_width to 63); +mmucr3_1 : in std_ulogic_vector(64-mmucr3_width to 63); +mmucr3_2 : in std_ulogic_vector(64-mmucr3_width to 63); +mmucr3_3 : in std_ulogic_vector(64-mmucr3_width to 63); +lpidr : in std_ulogic_vector(0 to lpid_width-1); +mmucfg_lrat : in std_ulogic; +mmucfg_twc : in std_ulogic; +tlb0cfg_pt : in std_ulogic; +tlb0cfg_ind : in std_ulogic; +tlb0cfg_gtwe : in std_ulogic; +mmucsr0_tlb0fi : in std_ulogic; +mas0_0_atsel : in std_ulogic; +mas0_0_esel : in std_ulogic_vector(0 to 2); +mas0_0_hes : in std_ulogic; +mas0_0_wq : in std_ulogic_vector(0 to 1); +mas1_0_v : in std_ulogic; +mas1_0_iprot : in std_ulogic; +mas1_0_tid : in std_ulogic_vector(0 to 13); +mas1_0_ind : in std_ulogic; +mas1_0_ts : in std_ulogic; +mas1_0_tsize : in std_ulogic_vector(0 to 3); +mas2_0_epn : in std_ulogic_vector(0 to 51); +mas2_0_wimge : in std_ulogic_vector(0 to 4); +mas3_0_usxwr : in std_ulogic_vector(0 to 3); +mas5_0_sgs : in std_ulogic; +mas5_0_slpid : in std_ulogic_vector(0 to 7); +mas6_0_spid : in std_ulogic_vector(0 to 13); +mas6_0_sind : in std_ulogic; +mas6_0_sas : in std_ulogic; +mas8_0_tgs : in std_ulogic; +mas8_0_tlpid : in std_ulogic_vector(0 to 7); +mas0_1_atsel : in std_ulogic; +mas0_1_esel : in std_ulogic_vector(0 to 2); +mas0_1_hes : in std_ulogic; +mas0_1_wq : in std_ulogic_vector(0 to 1); +mas1_1_v : in std_ulogic; +mas1_1_iprot : in std_ulogic; +mas1_1_tid : in std_ulogic_vector(0 to 13); +mas1_1_ind : in std_ulogic; +mas1_1_ts : in std_ulogic; +mas1_1_tsize : in std_ulogic_vector(0 to 3); +mas2_1_epn : in std_ulogic_vector(0 to 51); +mas2_1_wimge : in std_ulogic_vector(0 to 4); +mas3_1_usxwr : in std_ulogic_vector(0 to 3); +mas5_1_sgs : in std_ulogic; +mas5_1_slpid : in std_ulogic_vector(0 to 7); +mas6_1_spid : in std_ulogic_vector(0 to 13); +mas6_1_sind : in std_ulogic; +mas6_1_sas : in std_ulogic; +mas8_1_tgs : in std_ulogic; +mas8_1_tlpid : in std_ulogic_vector(0 to 7); +mas0_2_atsel : in std_ulogic; +mas0_2_esel : in std_ulogic_vector(0 to 2); +mas0_2_hes : in std_ulogic; +mas0_2_wq : in std_ulogic_vector(0 to 1); +mas1_2_v : in std_ulogic; +mas1_2_iprot : in std_ulogic; +mas1_2_tid : in std_ulogic_vector(0 to 13); +mas1_2_ind : in std_ulogic; +mas1_2_ts : in std_ulogic; +mas1_2_tsize : in std_ulogic_vector(0 to 3); +mas2_2_epn : in std_ulogic_vector(0 to 51); +mas2_2_wimge : in std_ulogic_vector(0 to 4); +mas3_2_usxwr : in std_ulogic_vector(0 to 3); +mas5_2_sgs : in std_ulogic; +mas5_2_slpid : in std_ulogic_vector(0 to 7); +mas6_2_spid : in std_ulogic_vector(0 to 13); +mas6_2_sind : in std_ulogic; +mas6_2_sas : in std_ulogic; +mas8_2_tgs : in std_ulogic; +mas8_2_tlpid : in std_ulogic_vector(0 to 7); +mas0_3_atsel : in std_ulogic; +mas0_3_esel : in std_ulogic_vector(0 to 2); +mas0_3_hes : in std_ulogic; +mas0_3_wq : in std_ulogic_vector(0 to 1); +mas1_3_v : in std_ulogic; +mas1_3_iprot : in std_ulogic; +mas1_3_tid : in std_ulogic_vector(0 to 13); +mas1_3_ind : in std_ulogic; +mas1_3_ts : in std_ulogic; +mas1_3_tsize : in std_ulogic_vector(0 to 3); +mas2_3_epn : in std_ulogic_vector(0 to 51); +mas2_3_wimge : in std_ulogic_vector(0 to 4); +mas3_3_usxwr : in std_ulogic_vector(0 to 3); +mas5_3_sgs : in std_ulogic; +mas5_3_slpid : in std_ulogic_vector(0 to 7); +mas6_3_spid : in std_ulogic_vector(0 to 13); +mas6_3_sind : in std_ulogic; +mas6_3_sas : in std_ulogic; +mas8_3_tgs : in std_ulogic; +mas8_3_tlpid : in std_ulogic_vector(0 to 7); +tlb_seq_ierat_req : in std_ulogic; +tlb_seq_derat_req : in std_ulogic; +tlb_seq_ierat_done : out std_ulogic; +tlb_seq_derat_done : out std_ulogic; +tlb_seq_idle : out std_ulogic; +ierat_req_taken : out std_ulogic; +derat_req_taken : out std_ulogic; +ierat_req_epn : in std_ulogic_vector(0 to req_epn_width-1); +ierat_req_pid : in std_ulogic_vector(0 to pid_width-1); +ierat_req_state : in std_ulogic_vector(0 to state_width-1); +ierat_req_thdid : in std_ulogic_vector(0 to thdid_width-1); +ierat_req_dup : in std_ulogic_vector(0 to 1); +derat_req_epn : in std_ulogic_vector(0 to req_epn_width-1); +derat_req_pid : in std_ulogic_vector(0 to pid_width-1); +derat_req_lpid : in std_ulogic_vector(0 to lpid_width-1); +derat_req_state : in std_ulogic_vector(0 to state_width-1); +derat_req_ttype : in std_ulogic_vector(0 to 1); +derat_req_thdid : in std_ulogic_vector(0 to thdid_width-1); +derat_req_dup : in std_ulogic_vector(0 to 1); +ptereload_req_valid : in std_ulogic; +ptereload_req_tag : in std_ulogic_vector(0 to tlb_tag_width-1); +ptereload_req_pte : in std_ulogic_vector(0 to pte_width-1); +ptereload_req_taken : out std_ulogic; +tlb_snoop_coming : in std_ulogic; +tlb_snoop_val : in std_ulogic; +tlb_snoop_attr : in std_ulogic_vector(0 to 34); +tlb_snoop_vpn : in std_ulogic_vector(52-epn_width to 51); +tlb_snoop_ack : out std_ulogic; +lru_rd_addr : out std_ulogic_vector(0 to tlb_addr_width-1); +lru_tag4_dataout : in std_ulogic_vector(0 to 15); +tlb_tag4_esel : in std_ulogic_vector(0 to 2); +tlb_tag4_wq : in std_ulogic_vector(0 to 1); +tlb_tag4_is : in std_ulogic_vector(0 to 1); +tlb_tag4_gs : in std_ulogic; +tlb_tag4_pr : in std_ulogic; +tlb_tag4_hes : in std_ulogic; +tlb_tag4_atsel : in std_ulogic; +tlb_tag4_pt : in std_ulogic; +tlb_tag4_cmp_hit : in std_ulogic; +tlb_tag4_way_ind : in std_ulogic; +tlb_tag4_ptereload : in std_ulogic; +tlb_tag4_endflag : in std_ulogic; +tlb_tag4_parerr : in std_ulogic; +tlb_tag5_except : in std_ulogic_vector(0 to thdid_width-1); +tlb_cmp_erat_dup_wait : in std_ulogic_vector(0 to 1); +tlb_tag0_epn : out std_ulogic_vector(52-epn_width to 51); +tlb_tag0_thdid : out std_ulogic_vector(0 to thdid_width-1); +tlb_tag0_type : out std_ulogic_vector(0 to 7); +tlb_tag0_lpid : out std_ulogic_vector(0 to lpid_width-1); +tlb_tag0_atsel : out std_ulogic; +tlb_tag0_size : out std_ulogic_vector(0 to 3); +tlb_tag0_addr_cap : out std_ulogic; +tlb_tag2 : out std_ulogic_vector(0 to tlb_tag_width-1); +tlb_addr2 : out std_ulogic_vector(0 to tlb_addr_width-1); +tlb_ctl_perf_tlbwec_resv : out std_ulogic; +tlb_ctl_perf_tlbwec_noresv : out std_ulogic; +lrat_tag4_hit_status : in std_ulogic_vector(0 to 3); +tlb_lper_lpn : out std_ulogic_vector(64-real_addr_width to 51); +tlb_lper_lps : out std_ulogic_vector(60 to 63); +tlb_lper_we : out std_ulogic_vector(0 to thdid_width-1); +ptereload_req_pte_lat : out std_ulogic_vector(0 to pte_width-1); +pte_tag0_lpn : out std_ulogic_vector(64-real_addr_width to 51); +pte_tag0_lpid : out std_ulogic_vector(0 to lpid_width-1); +tlb_write : out std_ulogic_vector(0 to tlb_ways-1); +tlb_addr : out std_ulogic_vector(0 to tlb_addr_width-1); +tlb_tag5_write : out std_ulogic; +tlb_delayed_act : out std_ulogic_vector(9 to 32); +tlb_ctl_dbg_seq_q : out std_ulogic_vector(0 to 5); +tlb_ctl_dbg_seq_idle : out std_ulogic; +tlb_ctl_dbg_seq_any_done_sig : out std_ulogic; +tlb_ctl_dbg_seq_abort : out std_ulogic; +tlb_ctl_dbg_any_tlb_req_sig : out std_ulogic; +tlb_ctl_dbg_any_req_taken_sig : out std_ulogic; +tlb_ctl_dbg_tag5_tlb_write_q : out std_ulogic_vector(0 to 3); +tlb_ctl_dbg_tag0_valid : out std_ulogic; +tlb_ctl_dbg_tag0_thdid : out std_ulogic_vector(0 to 1); +tlb_ctl_dbg_tag0_type : out std_ulogic_vector(0 to 2); +tlb_ctl_dbg_tag0_wq : out std_ulogic_vector(0 to 1); +tlb_ctl_dbg_tag0_gs : out std_ulogic; +tlb_ctl_dbg_tag0_pr : out std_ulogic; +tlb_ctl_dbg_tag0_atsel : out std_ulogic; +tlb_ctl_dbg_resv_valid : out std_ulogic_vector(0 to 3); +tlb_ctl_dbg_set_resv : out std_ulogic_vector(0 to 3); +tlb_ctl_dbg_resv_match_vec_q : out std_ulogic_vector(0 to 3); +tlb_ctl_dbg_any_tag_flush_sig : out std_ulogic; +tlb_ctl_dbg_resv0_tag0_lpid_match : out std_ulogic; +tlb_ctl_dbg_resv0_tag0_pid_match : out std_ulogic; +tlb_ctl_dbg_resv0_tag0_as_snoop_match : out std_ulogic; +tlb_ctl_dbg_resv0_tag0_gs_snoop_match : out std_ulogic; +tlb_ctl_dbg_resv0_tag0_as_tlbwe_match : out std_ulogic; +tlb_ctl_dbg_resv0_tag0_gs_tlbwe_match : out std_ulogic; +tlb_ctl_dbg_resv0_tag0_ind_match : out std_ulogic; +tlb_ctl_dbg_resv0_tag0_epn_loc_match : out std_ulogic; +tlb_ctl_dbg_resv0_tag0_epn_glob_match : out std_ulogic; +tlb_ctl_dbg_resv0_tag0_class_match : out std_ulogic; +tlb_ctl_dbg_resv1_tag0_lpid_match : out std_ulogic; +tlb_ctl_dbg_resv1_tag0_pid_match : out std_ulogic; +tlb_ctl_dbg_resv1_tag0_as_snoop_match : out std_ulogic; +tlb_ctl_dbg_resv1_tag0_gs_snoop_match : out std_ulogic; +tlb_ctl_dbg_resv1_tag0_as_tlbwe_match : out std_ulogic; +tlb_ctl_dbg_resv1_tag0_gs_tlbwe_match : out std_ulogic; +tlb_ctl_dbg_resv1_tag0_ind_match : out std_ulogic; +tlb_ctl_dbg_resv1_tag0_epn_loc_match : out std_ulogic; +tlb_ctl_dbg_resv1_tag0_epn_glob_match : out std_ulogic; +tlb_ctl_dbg_resv1_tag0_class_match : out std_ulogic; +tlb_ctl_dbg_resv2_tag0_lpid_match : out std_ulogic; +tlb_ctl_dbg_resv2_tag0_pid_match : out std_ulogic; +tlb_ctl_dbg_resv2_tag0_as_snoop_match : out std_ulogic; +tlb_ctl_dbg_resv2_tag0_gs_snoop_match : out std_ulogic; +tlb_ctl_dbg_resv2_tag0_as_tlbwe_match : out std_ulogic; +tlb_ctl_dbg_resv2_tag0_gs_tlbwe_match : out std_ulogic; +tlb_ctl_dbg_resv2_tag0_ind_match : out std_ulogic; +tlb_ctl_dbg_resv2_tag0_epn_loc_match : out std_ulogic; +tlb_ctl_dbg_resv2_tag0_epn_glob_match : out std_ulogic; +tlb_ctl_dbg_resv2_tag0_class_match : out std_ulogic; +tlb_ctl_dbg_resv3_tag0_lpid_match : out std_ulogic; +tlb_ctl_dbg_resv3_tag0_pid_match : out std_ulogic; +tlb_ctl_dbg_resv3_tag0_as_snoop_match : out std_ulogic; +tlb_ctl_dbg_resv3_tag0_gs_snoop_match : out std_ulogic; +tlb_ctl_dbg_resv3_tag0_as_tlbwe_match : out std_ulogic; +tlb_ctl_dbg_resv3_tag0_gs_tlbwe_match : out std_ulogic; +tlb_ctl_dbg_resv3_tag0_ind_match : out std_ulogic; +tlb_ctl_dbg_resv3_tag0_epn_loc_match : out std_ulogic; +tlb_ctl_dbg_resv3_tag0_epn_glob_match : out std_ulogic; +tlb_ctl_dbg_resv3_tag0_class_match : out std_ulogic; +tlb_ctl_dbg_clr_resv_q : out std_ulogic_vector(0 to 3); +tlb_ctl_dbg_clr_resv_terms : out std_ulogic_vector(0 to 3) +); +end mmq_tlb_ctl; +ARCHITECTURE MMQ_TLB_CTL + OF MMQ_TLB_CTL + IS +constant MMU_Mode_Value : std_ulogic := '0'; +constant TlbSel_Tlb : std_ulogic_vector(0 to 1) := "00"; +constant TlbSel_IErat : std_ulogic_vector(0 to 1) := "10"; +constant TlbSel_DErat : std_ulogic_vector(0 to 1) := "11"; +constant ERAT_PgSize_1GB : std_ulogic_vector(0 to 2) := "110"; +constant ERAT_PgSize_16MB : std_ulogic_vector(0 to 2) := "111"; +constant ERAT_PgSize_1MB : std_ulogic_vector(0 to 2) := "101"; +constant ERAT_PgSize_64KB : std_ulogic_vector(0 to 2) := "011"; +constant ERAT_PgSize_4KB : std_ulogic_vector(0 to 2) := "001"; +constant TLB_PgSize_1GB : std_ulogic_vector(0 to 3) := "1010"; +constant TLB_PgSize_16MB : std_ulogic_vector(0 to 3) := "0111"; +constant TLB_PgSize_1MB : std_ulogic_vector(0 to 3) := "0101"; +constant TLB_PgSize_64KB : std_ulogic_vector(0 to 3) := "0011"; +constant TLB_PgSize_4KB : std_ulogic_vector(0 to 3) := "0001"; +-- reserved for indirect entries +constant ERAT_PgSize_256MB : std_ulogic_vector(0 to 2) := "100"; +constant TLB_PgSize_256MB : std_ulogic_vector(0 to 3) := "1001"; +-- LRAT page sizes +constant LRAT_PgSize_1TB : std_ulogic_vector(0 to 3) := "1111"; +constant LRAT_PgSize_256GB : std_ulogic_vector(0 to 3) := "1110"; +constant LRAT_PgSize_16GB : std_ulogic_vector(0 to 3) := "1100"; +constant LRAT_PgSize_4GB : std_ulogic_vector(0 to 3) := "1011"; +constant LRAT_PgSize_1GB : std_ulogic_vector(0 to 3) := "1010"; +constant LRAT_PgSize_256MB : std_ulogic_vector(0 to 3) := "1001"; +constant LRAT_PgSize_16MB : std_ulogic_vector(0 to 3) := "0111"; +constant LRAT_PgSize_1MB : std_ulogic_vector(0 to 3) := "0101"; +constant TlbSeq_Idle : std_ulogic_vector(0 to 5) := "000000"; +constant TlbSeq_Stg1 : std_ulogic_vector(0 to 5) := "000001"; +constant TlbSeq_Stg2 : std_ulogic_vector(0 to 5) := "000011"; +constant TlbSeq_Stg3 : std_ulogic_vector(0 to 5) := "000010"; +constant TlbSeq_Stg4 : std_ulogic_vector(0 to 5) := "000110"; +constant TlbSeq_Stg5 : std_ulogic_vector(0 to 5) := "000100"; +constant TlbSeq_Stg6 : std_ulogic_vector(0 to 5) := "000101"; +constant TlbSeq_Stg7 : std_ulogic_vector(0 to 5) := "000111"; +constant TlbSeq_Stg8 : std_ulogic_vector(0 to 5) := "001000"; +constant TlbSeq_Stg9 : std_ulogic_vector(0 to 5) := "001001"; +constant TlbSeq_Stg10 : std_ulogic_vector(0 to 5) := "001011"; +constant TlbSeq_Stg11 : std_ulogic_vector(0 to 5) := "001010"; +constant TlbSeq_Stg12 : std_ulogic_vector(0 to 5) := "001110"; +constant TlbSeq_Stg13 : std_ulogic_vector(0 to 5) := "001100"; +constant TlbSeq_Stg14 : std_ulogic_vector(0 to 5) := "001101"; +constant TlbSeq_Stg15 : std_ulogic_vector(0 to 5) := "001111"; +constant TlbSeq_Stg16 : std_ulogic_vector(0 to 5) := "010000"; +constant TlbSeq_Stg17 : std_ulogic_vector(0 to 5) := "010001"; +constant TlbSeq_Stg18 : std_ulogic_vector(0 to 5) := "010011"; +constant TlbSeq_Stg19 : std_ulogic_vector(0 to 5) := "010010"; +constant TlbSeq_Stg20 : std_ulogic_vector(0 to 5) := "010110"; +constant TlbSeq_Stg21 : std_ulogic_vector(0 to 5) := "010100"; +constant TlbSeq_Stg22 : std_ulogic_vector(0 to 5) := "010101"; +constant TlbSeq_Stg23 : std_ulogic_vector(0 to 5) := "010111"; +constant TlbSeq_Stg24 : std_ulogic_vector(0 to 5) := "011000"; +constant TlbSeq_Stg25 : std_ulogic_vector(0 to 5) := "011001"; +constant TlbSeq_Stg26 : std_ulogic_vector(0 to 5) := "011011"; +constant TlbSeq_Stg27 : std_ulogic_vector(0 to 5) := "011010"; +constant TlbSeq_Stg28 : std_ulogic_vector(0 to 5) := "011110"; +constant TlbSeq_Stg29 : std_ulogic_vector(0 to 5) := "011100"; +constant TlbSeq_Stg30 : std_ulogic_vector(0 to 5) := "011101"; +constant TlbSeq_Stg31 : std_ulogic_vector(0 to 5) := "011111"; +constant TlbSeq_Stg32 : std_ulogic_vector(0 to 5) := "100000"; +--tlb_tag0_d <= ( 0:51 epn & +-- 52:65 pid & +-- 66:67 IS & +-- 68:69 Class & +-- 70:73 state (pr,gs,as,cm) & +-- 74:77 thdid & +-- 78:81 size & +-- 82:83 derat_miss/ierat_miss & +-- 84:85 tlbsx/tlbsrx & +-- 86:87 inval_snoop/tlbre & +-- 88:89 tlbwe/ptereload & +-- 90:97 lpid & +-- 98 indirect +-- 99 atsel & +-- 100:102 esel & +-- 103:105 hes/wq(0:1) & +-- 106:107 lrat/pt & +-- 108 record form +-- 109 endflag +constant tagpos_epn : natural := 0; +constant tagpos_pid : natural := 52; +constant tagpos_is : natural := 66; +constant tagpos_class : natural := 68; +constant tagpos_state : natural := 70; +constant tagpos_thdid : natural := 74; +constant tagpos_size : natural := 78; +constant tagpos_type : natural := 82; +constant tagpos_lpid : natural := 90; +constant tagpos_ind : natural := 98; +constant tagpos_atsel : natural := 99; +constant tagpos_esel : natural := 100; +constant tagpos_hes : natural := 103; +constant tagpos_wq : natural := 104; +constant tagpos_lrat : natural := 106; +constant tagpos_pt : natural := 107; +constant tagpos_recform : natural := 108; +constant tagpos_endflag : natural := 109; +-- derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload +constant tagpos_type_derat : natural := tagpos_type; +constant tagpos_type_ierat : natural := tagpos_type+1; +constant tagpos_type_tlbsx : natural := tagpos_type+2; +constant tagpos_type_tlbsrx : natural := tagpos_type+3; +constant tagpos_type_snoop : natural := tagpos_type+4; +constant tagpos_type_tlbre : natural := tagpos_type+5; +constant tagpos_type_tlbwe : natural := tagpos_type+6; +constant tagpos_type_ptereload : natural := tagpos_type+7; +-- state: 0:pr 1:gs 2:as 3:cm +constant tagpos_pr : natural := tagpos_state; +constant tagpos_gs : natural := tagpos_state+1; +constant tagpos_as : natural := tagpos_state+2; +constant tagpos_cm : natural := tagpos_state+3; +constant waypos_epn : natural := 0; +constant waypos_size : natural := 52; +constant waypos_thdid : natural := 56; +constant waypos_class : natural := 60; +constant waypos_extclass : natural := 62; +constant waypos_lpid : natural := 66; +constant waypos_xbit : natural := 84; +constant waypos_rpn : natural := 88; +constant waypos_rc : natural := 118; +constant waypos_wlc : natural := 120; +constant waypos_resvattr : natural := 122; +constant waypos_vf : natural := 123; +constant waypos_ind : natural := 124; +constant waypos_ubits : natural := 125; +constant waypos_wimge : natural := 129; +constant waypos_usxwr : natural := 134; +constant waypos_gs : natural := 140; +constant waypos_ts : natural := 141; +constant waypos_tid : natural := 144; +constant ptepos_rpn : natural := 0; +constant ptepos_wimge : natural := 40; +constant ptepos_r : natural := 45; +constant ptepos_ubits : natural := 46; +constant ptepos_sw0 : natural := 50; +constant ptepos_c : natural := 51; +constant ptepos_size : natural := 52; +constant ptepos_usxwr : natural := 56; +constant ptepos_sw1 : natural := 62; +constant ptepos_valid : natural := 63; +constant xu_ex1_flush_offset : natural := 0; +constant ex1_valid_offset : natural := xu_ex1_flush_offset + thdid_width; +constant ex1_ttype_offset : natural := ex1_valid_offset + thdid_width; +constant ex1_state_offset : natural := ex1_ttype_offset + ttype_width; +constant ex1_pid_offset : natural := ex1_state_offset + state_width+1; +constant ex2_valid_offset : natural := ex1_pid_offset + pid_width; +constant ex2_flush_offset : natural := ex2_valid_offset + thdid_width; +constant ex2_flush_req_offset : natural := ex2_flush_offset + thdid_width; +constant ex2_ttype_offset : natural := ex2_flush_req_offset + thdid_width; +constant ex2_state_offset : natural := ex2_ttype_offset + ttype_width; +constant ex2_pid_offset : natural := ex2_state_offset + state_width+1; +constant ex3_valid_offset : natural := ex2_pid_offset + pid_width; +constant ex3_flush_offset : natural := ex3_valid_offset + thdid_width; +constant ex3_ttype_offset : natural := ex3_flush_offset + thdid_width; +constant ex3_state_offset : natural := ex3_ttype_offset + ttype_width; +constant ex3_pid_offset : natural := ex3_state_offset + state_width+1; +constant ex4_valid_offset : natural := ex3_pid_offset + pid_width; +constant ex4_flush_offset : natural := ex4_valid_offset + thdid_width; +constant ex4_ttype_offset : natural := ex4_flush_offset + thdid_width; +constant ex4_state_offset : natural := ex4_ttype_offset + ttype_width; +constant ex4_pid_offset : natural := ex4_state_offset + state_width+1; +constant ex5_valid_offset : natural := ex4_pid_offset + pid_width; +constant ex5_flush_offset : natural := ex5_valid_offset + thdid_width; +constant ex5_ttype_offset : natural := ex5_flush_offset + thdid_width; +constant ex5_state_offset : natural := ex5_ttype_offset + ttype_width; +constant ex5_pid_offset : natural := ex5_state_offset + state_width+1; +constant ex6_valid_offset : natural := ex5_pid_offset + pid_width; +constant ex6_flush_offset : natural := ex6_valid_offset + thdid_width; +constant ex6_ttype_offset : natural := ex6_flush_offset + thdid_width; +constant ex6_state_offset : natural := ex6_ttype_offset + ttype_width; +constant ex6_pid_offset : natural := ex6_state_offset + state_width+1; +constant tlb_addr_offset : natural := ex6_pid_offset + pid_width; +constant tlb_addr2_offset : natural := tlb_addr_offset + tlb_addr_width; +constant tlb_write_offset : natural := tlb_addr2_offset + tlb_addr_width; +constant tlb_tag0_offset : natural := tlb_write_offset + tlb_ways; +constant tlb_tag1_offset : natural := tlb_tag0_offset + tlb_tag_width; +constant tlb_tag2_offset : natural := tlb_tag1_offset + tlb_tag_width; +constant tlb_seq_offset : natural := tlb_tag2_offset + tlb_tag_width; +constant derat_taken_offset : natural := tlb_seq_offset + tlb_seq_width; +constant xucr4_mmu_mchk_offset : natural := derat_taken_offset + 1; +constant ex6_illeg_instr_offset : natural := xucr4_mmu_mchk_offset + 1; +constant snoop_val_offset : natural := ex6_illeg_instr_offset + 2; +constant snoop_attr_offset : natural := snoop_val_offset + 2; +constant snoop_vpn_offset : natural := snoop_attr_offset + 35; +constant tlb_clr_resv_offset : natural := snoop_vpn_offset + epn_width; +constant tlb_resv_match_vec_offset : natural := tlb_clr_resv_offset + thdid_width; +constant tlb_resv0_valid_offset : natural := tlb_resv_match_vec_offset + thdid_width; +constant tlb_resv0_epn_offset : natural := tlb_resv0_valid_offset + 1; +constant tlb_resv0_pid_offset : natural := tlb_resv0_epn_offset + epn_width; +constant tlb_resv0_lpid_offset : natural := tlb_resv0_pid_offset + pid_width; +constant tlb_resv0_as_offset : natural := tlb_resv0_lpid_offset + lpid_width; +constant tlb_resv0_gs_offset : natural := tlb_resv0_as_offset + 1; +constant tlb_resv0_ind_offset : natural := tlb_resv0_gs_offset + 1; +constant tlb_resv0_class_offset : natural := tlb_resv0_ind_offset + 1; +constant tlb_resv1_valid_offset : natural := tlb_resv0_class_offset + class_width; +constant tlb_resv1_epn_offset : natural := tlb_resv1_valid_offset + 1; +constant tlb_resv1_pid_offset : natural := tlb_resv1_epn_offset + epn_width; +constant tlb_resv1_lpid_offset : natural := tlb_resv1_pid_offset + pid_width; +constant tlb_resv1_as_offset : natural := tlb_resv1_lpid_offset + lpid_width; +constant tlb_resv1_gs_offset : natural := tlb_resv1_as_offset + 1; +constant tlb_resv1_ind_offset : natural := tlb_resv1_gs_offset + 1; +constant tlb_resv1_class_offset : natural := tlb_resv1_ind_offset + 1; +constant tlb_resv2_valid_offset : natural := tlb_resv1_class_offset + class_width; +constant tlb_resv2_epn_offset : natural := tlb_resv2_valid_offset + 1; +constant tlb_resv2_pid_offset : natural := tlb_resv2_epn_offset + epn_width; +constant tlb_resv2_lpid_offset : natural := tlb_resv2_pid_offset + pid_width; +constant tlb_resv2_as_offset : natural := tlb_resv2_lpid_offset + lpid_width; +constant tlb_resv2_gs_offset : natural := tlb_resv2_as_offset + 1; +constant tlb_resv2_ind_offset : natural := tlb_resv2_gs_offset + 1; +constant tlb_resv2_class_offset : natural := tlb_resv2_ind_offset + 1; +constant tlb_resv3_valid_offset : natural := tlb_resv2_class_offset + class_width; +constant tlb_resv3_epn_offset : natural := tlb_resv3_valid_offset + 1; +constant tlb_resv3_pid_offset : natural := tlb_resv3_epn_offset + epn_width; +constant tlb_resv3_lpid_offset : natural := tlb_resv3_pid_offset + pid_width; +constant tlb_resv3_as_offset : natural := tlb_resv3_lpid_offset + lpid_width; +constant tlb_resv3_gs_offset : natural := tlb_resv3_as_offset + 1; +constant tlb_resv3_ind_offset : natural := tlb_resv3_gs_offset + 1; +constant tlb_resv3_class_offset : natural := tlb_resv3_ind_offset + 1; +constant ptereload_req_pte_offset : natural := tlb_resv3_class_offset + class_width; +constant tlb_delayed_act_offset : natural := ptereload_req_pte_offset + pte_width; +constant tlb_ctl_spare_offset : natural := tlb_delayed_act_offset + 33; +constant scan_right : natural := tlb_ctl_spare_offset + 32 -1; +-- Latch signals +signal xu_ex1_flush_d, xu_ex1_flush_q : std_ulogic_vector(0 to thdid_width-1); +signal ex1_valid_d, ex1_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal ex1_ttype_d, ex1_ttype_q : std_ulogic_vector(0 to ttype_width-1); +signal ex1_state_d, ex1_state_q : std_ulogic_vector(0 to state_width); +signal ex1_pid_d, ex1_pid_q : std_ulogic_vector(0 to pid_width-1); +signal ex2_valid_d, ex2_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal ex2_flush_d, ex2_flush_q : std_ulogic_vector(0 to thdid_width-1); +signal ex2_flush_req_d, ex2_flush_req_q : std_ulogic_vector(0 to thdid_width-1); +signal ex2_ttype_d, ex2_ttype_q : std_ulogic_vector(0 to ttype_width-1); +signal ex2_state_d, ex2_state_q : std_ulogic_vector(0 to state_width); +signal ex2_pid_d, ex2_pid_q : std_ulogic_vector(0 to pid_width-1); +signal ex3_valid_d, ex3_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal ex3_flush_d, ex3_flush_q : std_ulogic_vector(0 to thdid_width-1); +signal ex3_ttype_d, ex3_ttype_q : std_ulogic_vector(0 to ttype_width-1); +signal ex3_state_d, ex3_state_q : std_ulogic_vector(0 to state_width); +signal ex3_pid_d, ex3_pid_q : std_ulogic_vector(0 to pid_width-1); +signal ex4_valid_d, ex4_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal ex4_flush_d, ex4_flush_q : std_ulogic_vector(0 to thdid_width-1); +signal ex4_ttype_d, ex4_ttype_q : std_ulogic_vector(0 to ttype_width-1); +signal ex4_state_d, ex4_state_q : std_ulogic_vector(0 to state_width); +signal ex4_pid_d, ex4_pid_q : std_ulogic_vector(0 to pid_width-1); +signal ex5_valid_d, ex5_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal ex5_flush_d, ex5_flush_q : std_ulogic_vector(0 to thdid_width-1); +signal ex5_ttype_d, ex5_ttype_q : std_ulogic_vector(0 to ttype_width-1); +signal ex5_state_d, ex5_state_q : std_ulogic_vector(0 to state_width); +signal ex5_pid_d, ex5_pid_q : std_ulogic_vector(0 to pid_width-1); +signal ex6_valid_d, ex6_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal ex6_flush_d, ex6_flush_q : std_ulogic_vector(0 to thdid_width-1); +signal ex6_ttype_d, ex6_ttype_q : std_ulogic_vector(0 to ttype_width-1); +signal ex6_state_d, ex6_state_q : std_ulogic_vector(0 to state_width); +signal ex6_pid_d, ex6_pid_q : std_ulogic_vector(0 to pid_width-1); +signal tlb_tag0_d, tlb_tag0_q : std_ulogic_vector(0 to tlb_tag_width-1); +signal tlb_tag1_d, tlb_tag1_q : std_ulogic_vector(0 to tlb_tag_width-1); +signal tlb_tag2_d, tlb_tag2_q : std_ulogic_vector(0 to tlb_tag_width-1); +signal tlb_addr_d, tlb_addr_q : std_ulogic_vector(0 to tlb_addr_width-1); +signal tlb_addr2_d, tlb_addr2_q : std_ulogic_vector(0 to tlb_addr_width-1); +signal tlb_write_d, tlb_write_q : std_ulogic_vector(0 to tlb_ways-1); +signal tlb_seq_d, tlb_seq_q : std_ulogic_vector(0 to 5); +signal derat_taken_d, derat_taken_q : std_ulogic; +signal ex6_illeg_instr_d, ex6_illeg_instr_q : std_ulogic_vector(0 to 1); +signal snoop_val_d, snoop_val_q : std_ulogic_vector(0 to 1); +signal snoop_attr_d, snoop_attr_q : std_ulogic_vector(0 to 34); +signal snoop_vpn_d,snoop_vpn_q : std_ulogic_vector(52-epn_width to 51); +signal tlb_resv0_valid_d, tlb_resv0_valid_q : std_ulogic; +signal tlb_resv0_epn_d, tlb_resv0_epn_q : std_ulogic_vector(52-epn_width to 51); +signal tlb_resv0_pid_d, tlb_resv0_pid_q : std_ulogic_vector(0 to pid_width-1); +signal tlb_resv0_lpid_d, tlb_resv0_lpid_q : std_ulogic_vector(0 to lpid_width-1); +signal tlb_resv0_as_d, tlb_resv0_as_q : std_ulogic; +signal tlb_resv0_gs_d, tlb_resv0_gs_q : std_ulogic; +signal tlb_resv0_ind_d, tlb_resv0_ind_q : std_ulogic; +signal tlb_resv0_class_d, tlb_resv0_class_q : std_ulogic_vector(0 to class_width-1); +signal tlb_resv1_valid_d, tlb_resv1_valid_q : std_ulogic; +signal tlb_resv1_epn_d, tlb_resv1_epn_q : std_ulogic_vector(52-epn_width to 51); +signal tlb_resv1_pid_d, tlb_resv1_pid_q : std_ulogic_vector(0 to pid_width-1); +signal tlb_resv1_lpid_d, tlb_resv1_lpid_q : std_ulogic_vector(0 to lpid_width-1); +signal tlb_resv1_as_d, tlb_resv1_as_q : std_ulogic; +signal tlb_resv1_gs_d, tlb_resv1_gs_q : std_ulogic; +signal tlb_resv1_ind_d, tlb_resv1_ind_q : std_ulogic; +signal tlb_resv1_class_d, tlb_resv1_class_q : std_ulogic_vector(0 to class_width-1); +signal tlb_resv2_valid_d, tlb_resv2_valid_q : std_ulogic; +signal tlb_resv2_epn_d, tlb_resv2_epn_q : std_ulogic_vector(52-epn_width to 51); +signal tlb_resv2_pid_d, tlb_resv2_pid_q : std_ulogic_vector(0 to pid_width-1); +signal tlb_resv2_lpid_d, tlb_resv2_lpid_q : std_ulogic_vector(0 to lpid_width-1); +signal tlb_resv2_as_d, tlb_resv2_as_q : std_ulogic; +signal tlb_resv2_gs_d, tlb_resv2_gs_q : std_ulogic; +signal tlb_resv2_ind_d, tlb_resv2_ind_q : std_ulogic; +signal tlb_resv2_class_d, tlb_resv2_class_q : std_ulogic_vector(0 to class_width-1); +signal tlb_resv3_valid_d, tlb_resv3_valid_q : std_ulogic; +signal tlb_resv3_epn_d, tlb_resv3_epn_q : std_ulogic_vector(52-epn_width to 51); +signal tlb_resv3_pid_d, tlb_resv3_pid_q : std_ulogic_vector(0 to pid_width-1); +signal tlb_resv3_lpid_d, tlb_resv3_lpid_q : std_ulogic_vector(0 to lpid_width-1); +signal tlb_resv3_as_d, tlb_resv3_as_q : std_ulogic; +signal tlb_resv3_gs_d, tlb_resv3_gs_q : std_ulogic; +signal tlb_resv3_ind_d, tlb_resv3_ind_q : std_ulogic; +signal tlb_resv3_class_d, tlb_resv3_class_q : std_ulogic_vector(0 to class_width-1); +signal ptereload_req_pte_d, ptereload_req_pte_q : std_ulogic_vector(0 to pte_width-1); +signal tlb_clr_resv_d, tlb_clr_resv_q : std_ulogic_vector(0 to thdid_width-1); +signal tlb_resv_match_vec_d, tlb_resv_match_vec_q : std_ulogic_vector(0 to thdid_width-1); +signal tlb_delayed_act_d, tlb_delayed_act_q : std_ulogic_vector(0 to 32); +signal tlb_ctl_spare_q : std_ulogic_vector(0 to 31); +-- logic signals +signal tlb_seq_next : std_ulogic_vector(0 to 5); +signal tlb_resv0_tag0_lpid_match : std_ulogic; +signal tlb_resv0_tag0_pid_match : std_ulogic; +signal tlb_resv0_tag0_as_snoop_match : std_ulogic; +signal tlb_resv0_tag0_gs_snoop_match : std_ulogic; +signal tlb_resv0_tag0_as_tlbwe_match : std_ulogic; +signal tlb_resv0_tag0_gs_tlbwe_match : std_ulogic; +signal tlb_resv0_tag0_ind_match : std_ulogic; +signal tlb_resv0_tag0_epn_loc_match : std_ulogic; +signal tlb_resv0_tag0_epn_glob_match : std_ulogic; +signal tlb_resv0_tag0_class_match : std_ulogic; +signal tlb_resv1_tag0_lpid_match : std_ulogic; +signal tlb_resv1_tag0_pid_match : std_ulogic; +signal tlb_resv1_tag0_as_snoop_match : std_ulogic; +signal tlb_resv1_tag0_gs_snoop_match : std_ulogic; +signal tlb_resv1_tag0_as_tlbwe_match : std_ulogic; +signal tlb_resv1_tag0_gs_tlbwe_match : std_ulogic; +signal tlb_resv1_tag0_ind_match : std_ulogic; +signal tlb_resv1_tag0_epn_loc_match : std_ulogic; +signal tlb_resv1_tag0_epn_glob_match : std_ulogic; +signal tlb_resv1_tag0_class_match : std_ulogic; +signal tlb_resv2_tag0_lpid_match : std_ulogic; +signal tlb_resv2_tag0_pid_match : std_ulogic; +signal tlb_resv2_tag0_as_snoop_match : std_ulogic; +signal tlb_resv2_tag0_gs_snoop_match : std_ulogic; +signal tlb_resv2_tag0_as_tlbwe_match : std_ulogic; +signal tlb_resv2_tag0_gs_tlbwe_match : std_ulogic; +signal tlb_resv2_tag0_ind_match : std_ulogic; +signal tlb_resv2_tag0_epn_loc_match : std_ulogic; +signal tlb_resv2_tag0_epn_glob_match : std_ulogic; +signal tlb_resv2_tag0_class_match : std_ulogic; +signal tlb_resv3_tag0_lpid_match : std_ulogic; +signal tlb_resv3_tag0_pid_match : std_ulogic; +signal tlb_resv3_tag0_as_snoop_match : std_ulogic; +signal tlb_resv3_tag0_gs_snoop_match : std_ulogic; +signal tlb_resv3_tag0_as_tlbwe_match : std_ulogic; +signal tlb_resv3_tag0_gs_tlbwe_match : std_ulogic; +signal tlb_resv3_tag0_ind_match : std_ulogic; +signal tlb_resv3_tag0_epn_loc_match : std_ulogic; +signal tlb_resv3_tag0_epn_glob_match : std_ulogic; +signal tlb_resv3_tag0_class_match : std_ulogic; +signal tlb_resv0_tag1_lpid_match : std_ulogic; +signal tlb_resv0_tag1_pid_match : std_ulogic; +signal tlb_resv0_tag1_as_snoop_match : std_ulogic; +signal tlb_resv0_tag1_gs_snoop_match : std_ulogic; +signal tlb_resv0_tag1_as_tlbwe_match : std_ulogic; +signal tlb_resv0_tag1_gs_tlbwe_match : std_ulogic; +signal tlb_resv0_tag1_ind_match : std_ulogic; +signal tlb_resv0_tag1_epn_loc_match : std_ulogic; +signal tlb_resv0_tag1_epn_glob_match : std_ulogic; +signal tlb_resv0_tag1_class_match : std_ulogic; +signal tlb_resv1_tag1_lpid_match : std_ulogic; +signal tlb_resv1_tag1_pid_match : std_ulogic; +signal tlb_resv1_tag1_as_snoop_match : std_ulogic; +signal tlb_resv1_tag1_gs_snoop_match : std_ulogic; +signal tlb_resv1_tag1_as_tlbwe_match : std_ulogic; +signal tlb_resv1_tag1_gs_tlbwe_match : std_ulogic; +signal tlb_resv1_tag1_ind_match : std_ulogic; +signal tlb_resv1_tag1_epn_loc_match : std_ulogic; +signal tlb_resv1_tag1_epn_glob_match : std_ulogic; +signal tlb_resv1_tag1_class_match : std_ulogic; +signal tlb_resv2_tag1_lpid_match : std_ulogic; +signal tlb_resv2_tag1_pid_match : std_ulogic; +signal tlb_resv2_tag1_as_snoop_match : std_ulogic; +signal tlb_resv2_tag1_gs_snoop_match : std_ulogic; +signal tlb_resv2_tag1_as_tlbwe_match : std_ulogic; +signal tlb_resv2_tag1_gs_tlbwe_match : std_ulogic; +signal tlb_resv2_tag1_ind_match : std_ulogic; +signal tlb_resv2_tag1_epn_loc_match : std_ulogic; +signal tlb_resv2_tag1_epn_glob_match : std_ulogic; +signal tlb_resv2_tag1_class_match : std_ulogic; +signal tlb_resv3_tag1_lpid_match : std_ulogic; +signal tlb_resv3_tag1_pid_match : std_ulogic; +signal tlb_resv3_tag1_as_snoop_match : std_ulogic; +signal tlb_resv3_tag1_gs_snoop_match : std_ulogic; +signal tlb_resv3_tag1_as_tlbwe_match : std_ulogic; +signal tlb_resv3_tag1_gs_tlbwe_match : std_ulogic; +signal tlb_resv3_tag1_ind_match : std_ulogic; +signal tlb_resv3_tag1_epn_loc_match : std_ulogic; +signal tlb_resv3_tag1_epn_glob_match : std_ulogic; +signal tlb_resv3_tag1_class_match : std_ulogic; +signal tlb_resv_valid_vec : std_ulogic_vector(0 to thdid_width-1); +signal tlb_seq_set_resv : std_ulogic; +signal tlb_seq_snoop_resv : std_ulogic; +signal tlb_seq_snoop_resv_q : std_ulogic_vector(0 to thdid_width-1); +signal tlb_hashed_addr1 : std_ulogic_vector(0 to tlb_addr_width-1); +signal tlb_hashed_addr2 : std_ulogic_vector(0 to tlb_addr_width-1); +signal tlb_hashed_addr3 : std_ulogic_vector(0 to tlb_addr_width-1); +signal tlb_hashed_addr4 : std_ulogic_vector(0 to tlb_addr_width-1); +signal tlb_hashed_addr5 : std_ulogic_vector(0 to tlb_addr_width-1); +signal tlb_hashed_tid0_addr1 : std_ulogic_vector(0 to tlb_addr_width-1); +signal tlb_hashed_tid0_addr2 : std_ulogic_vector(0 to tlb_addr_width-1); +signal tlb_hashed_tid0_addr3 : std_ulogic_vector(0 to tlb_addr_width-1); +signal tlb_hashed_tid0_addr4 : std_ulogic_vector(0 to tlb_addr_width-1); +signal tlb_hashed_tid0_addr5 : std_ulogic_vector(0 to tlb_addr_width-1); +signal tlb_tag0_hashed_addr : std_ulogic_vector(0 to tlb_addr_width-1); +signal tlb_tag0_hashed_tid0_addr : std_ulogic_vector(0 to tlb_addr_width-1); +signal tlb_tag0_tid_notzero : std_ulogic; +signal size_4K_hashed_addr : std_ulogic_vector(0 to tlb_addr_width-1); +signal size_64K_hashed_addr : std_ulogic_vector(0 to tlb_addr_width-1); +signal size_1M_hashed_addr : std_ulogic_vector(0 to tlb_addr_width-1); +signal size_16M_hashed_addr : std_ulogic_vector(0 to tlb_addr_width-1); +signal size_1G_hashed_addr : std_ulogic_vector(0 to tlb_addr_width-1); +signal size_4K_hashed_tid0_addr : std_ulogic_vector(0 to tlb_addr_width-1); +signal size_64K_hashed_tid0_addr : std_ulogic_vector(0 to tlb_addr_width-1); +signal size_1M_hashed_tid0_addr : std_ulogic_vector(0 to tlb_addr_width-1); +signal size_16M_hashed_tid0_addr : std_ulogic_vector(0 to tlb_addr_width-1); +signal size_1G_hashed_tid0_addr : std_ulogic_vector(0 to tlb_addr_width-1); +-- reserved for HTW +signal size_256M_hashed_addr : std_ulogic_vector(0 to tlb_addr_width-1); +signal size_256M_hashed_tid0_addr : std_ulogic_vector(0 to tlb_addr_width-1); +signal tlb_seq_pgsize : std_ulogic_vector(0 to 3); +signal tlb_seq_addr : std_ulogic_vector(0 to tlb_addr_width-1); +signal tlb_seq_esel : std_ulogic_vector(0 to 2); +signal tlb_seq_is : std_ulogic_vector(0 to 1); +signal tlb_addr_p1 : std_ulogic_vector(0 to tlb_addr_width-1); +signal tlb_addr_maxcntm1 : std_ulogic; +signal tlb_seq_addr_incr : std_ulogic; +signal tlb_seq_addr_clr : std_ulogic; +signal tlb_seq_tag0_addr_cap : std_ulogic; +signal tlb_seq_addr_update : std_ulogic; +signal tlb_seq_lrat_enable : std_ulogic; +signal tlb_seq_idle_sig : std_ulogic; +signal tlb_seq_ind : std_ulogic; +signal tlb_seq_ierat_done_sig : std_ulogic; +signal tlb_seq_derat_done_sig : std_ulogic; +signal tlb_seq_snoop_done_sig : std_ulogic; +signal tlb_seq_search_done_sig : std_ulogic; +signal tlb_seq_searchresv_done_sig : std_ulogic; +signal tlb_seq_read_done_sig : std_ulogic; +signal tlb_seq_write_done_sig : std_ulogic; +signal tlb_seq_ptereload_done_sig : std_ulogic; +signal tlb_seq_any_done_sig : std_ulogic; +signal tlb_seq_endflag : std_ulogic; +signal tlb_search_req : std_ulogic; +signal tlb_searchresv_req : std_ulogic; +signal tlb_read_req : std_ulogic; +signal tlb_write_req : std_ulogic; +signal tlb_set_resv0 : std_ulogic; +-- synopsys translate_off +-- synopsys translate_on +signal tlb_set_resv1 : std_ulogic; +-- synopsys translate_off +-- synopsys translate_on +signal tlb_set_resv2 : std_ulogic; +-- synopsys translate_off +-- synopsys translate_on +signal tlb_set_resv3 : std_ulogic; +-- synopsys translate_off +-- synopsys translate_on +signal any_tlb_req_sig : std_ulogic; +signal any_req_taken_sig : std_ulogic; +signal ierat_req_taken_sig : std_ulogic; +signal derat_req_taken_sig : std_ulogic; +signal snoop_req_taken_sig : std_ulogic; +signal search_req_taken_sig : std_ulogic; +signal searchresv_req_taken_sig : std_ulogic; +signal read_req_taken_sig : std_ulogic; +signal write_req_taken_sig : std_ulogic; +signal ptereload_req_taken_sig : std_ulogic; +signal ex3_valid_32b : std_ulogic; +-- synopsys translate_off +-- synopsys translate_on +signal ex1_mas0_atsel : std_ulogic; +signal ex1_mas0_esel : std_ulogic_vector(0 to 2); +signal ex1_mas0_hes : std_ulogic; +signal ex1_mas0_wq : std_ulogic_vector(0 to 1); +signal ex1_mas1_v : std_ulogic; +signal ex1_mas1_iprot : std_ulogic; +signal ex1_mas1_ind : std_ulogic; +signal ex1_mas1_tid : std_ulogic_vector(0 to pid_width-1); +signal ex1_mas1_ts : std_ulogic; +signal ex1_mas1_tsize : std_ulogic_vector(0 to 3); +signal ex1_mas2_epn : std_ulogic_vector(52-epn_width to 51); +signal ex1_mas8_tgs : std_ulogic; +signal ex1_mas8_tlpid : std_ulogic_vector(0 to lpid_width-1); +signal ex1_mmucr3_class : std_ulogic_vector(0 to class_width-1); +signal ex2_mas0_atsel : std_ulogic; +signal ex2_mas0_esel : std_ulogic_vector(0 to 2); +signal ex2_mas0_hes : std_ulogic; +signal ex2_mas0_wq : std_ulogic_vector(0 to 1); +signal ex2_mas1_ind : std_ulogic; +signal ex2_mas1_tid : std_ulogic_vector(0 to pid_width-1); +signal ex2_mas5_slpid : std_ulogic_vector(0 to lpid_width-1); +signal ex2_mas5_1_state : std_ulogic_vector(0 to state_width-1); +signal ex2_mas5_6_state : std_ulogic_vector(0 to state_width-1); +signal ex2_mas6_sind : std_ulogic; +signal ex2_mas6_spid : std_ulogic_vector(0 to pid_width-1); +signal ex2_hv_state : std_ulogic; +signal ex6_hv_state : std_ulogic; +signal ex6_priv_state : std_ulogic; +signal ex6_dgtmi_state : std_ulogic; +signal tlb_ctl_tag1_flush_sig : std_ulogic_vector(0 to thdid_width-1); +signal tlb_ctl_tag2_flush_sig : std_ulogic_vector(0 to thdid_width-1); +signal tlb_ctl_tag3_flush_sig : std_ulogic_vector(0 to thdid_width-1); +signal tlb_ctl_tag4_flush_sig : std_ulogic_vector(0 to thdid_width-1); +signal tlb_ctl_any_tag_flush_sig : std_ulogic; +signal tlb_seq_abort : std_ulogic; +signal tlb_tag4_hit_or_parerr : std_ulogic; +signal tlb_ctl_quiesce_b : std_ulogic_vector(0 to thdid_width-1); +signal ex2_flush_req_local : std_ulogic_vector(0 to thdid_width-1); +signal tlbwe_back_inv_holdoff : std_ulogic; +signal pgsize1_valid : std_ulogic; +signal pgsize2_valid : std_ulogic; +signal pgsize3_valid : std_ulogic; +signal pgsize4_valid : std_ulogic; +signal pgsize5_valid : std_ulogic; +signal pgsize1_tid0_valid : std_ulogic; +signal pgsize2_tid0_valid : std_ulogic; +signal pgsize3_tid0_valid : std_ulogic; +signal pgsize4_tid0_valid : std_ulogic; +signal pgsize5_tid0_valid : std_ulogic; +signal pgsize_qty : std_ulogic_vector(0 to 2); +signal pgsize_tid0_qty : std_ulogic_vector(0 to 2); +signal tlb_tag1_pgsize_eq_16mb : std_ulogic; +signal tlb_tag1_pgsize_gte_1mb : std_ulogic; +signal tlb_tag1_pgsize_gte_64kb : std_ulogic; +-- mas settings errors +signal mas1_tsize_direct : std_ulogic_vector(0 to thdid_width-1); +signal mas1_tsize_indirect : std_ulogic_vector(0 to thdid_width-1); +signal mas1_tsize_lrat : std_ulogic_vector(0 to thdid_width-1); +signal mas3_spsize_indirect : std_ulogic_vector(0 to thdid_width-1); +signal ex2_tlbre_mas1_tsize_not_supp : std_ulogic_vector(0 to thdid_width-1); +signal ex5_tlbre_mas1_tsize_not_supp : std_ulogic_vector(0 to thdid_width-1); +signal ex5_tlbwe_mas1_tsize_not_supp : std_ulogic_vector(0 to thdid_width-1); +signal ex6_tlbwe_mas1_tsize_not_supp : std_ulogic_vector(0 to thdid_width-1); +signal ex5_tlbwe_mas0_lrat_bad_selects : std_ulogic_vector(0 to thdid_width-1); +signal ex6_tlbwe_mas0_lrat_bad_selects : std_ulogic_vector(0 to thdid_width-1); +signal ex5_tlbwe_mas2_ind_bad_wimge : std_ulogic_vector(0 to thdid_width-1); +signal ex6_tlbwe_mas2_ind_bad_wimge : std_ulogic_vector(0 to thdid_width-1); +signal ex5_tlbwe_mas3_ind_bad_spsize : std_ulogic_vector(0 to thdid_width-1); +signal ex6_tlbwe_mas3_ind_bad_spsize : std_ulogic_vector(0 to thdid_width-1); +-- synopsys translate_off +-- synopsys translate_on +-- power clock gating signals +signal tlb_early_act : std_ulogic; +signal tlb_tag0_act : std_ulogic; +signal tlb_snoop_act : std_ulogic; +signal unused_dc : std_ulogic_vector(0 to 35); +-- synopsys translate_off +-- synopsys translate_on +-- Pervasive +signal pc_sg_1 : std_ulogic; +signal pc_sg_0 : std_ulogic; +signal pc_fce_1 : std_ulogic; +signal pc_fce_0 : std_ulogic; +signal pc_func_sl_thold_1 : std_ulogic; +signal pc_func_sl_thold_0 : std_ulogic; +signal pc_func_sl_thold_0_b : std_ulogic; +signal pc_func_slp_sl_thold_1 : std_ulogic; +signal pc_func_slp_sl_thold_0 : std_ulogic; +signal pc_func_slp_sl_thold_0_b : std_ulogic; +signal pc_func_sl_force : std_ulogic; +signal pc_func_slp_sl_force : std_ulogic; +signal pc_func_slp_nsl_thold_1 : std_ulogic; +signal pc_func_slp_nsl_thold_0 : std_ulogic; +signal pc_func_slp_nsl_thold_0_b : std_ulogic; +signal pc_func_slp_nsl_force : std_ulogic; +signal siv : std_ulogic_vector(0 to scan_right); +signal sov : std_ulogic_vector(0 to scan_right); +signal tidn : std_ulogic; +signal tiup : std_ulogic; + BEGIN --@@ START OF EXECUTABLE CODE FOR MMQ_TLB_CTL + +----------------------------------------------------------------------- +-- Logic +----------------------------------------------------------------------- +----------------------------------------------------------------------- +-- Glorp1 - common stuff for erat-only and tlb +----------------------------------------------------------------------- +tidn <= '0'; +tiup <= '1'; +-- not quiesced +tlb_ctl_quiesce_b(0 TO thdid_width-1) <= + ( (0 to thdid_width-1 => or_reduce(tlb_seq_q)) and tlb_tag0_q(tagpos_thdid to tagpos_thdid+thdid_width-1) ); +tlb_ctl_quiesce <= not tlb_ctl_quiesce_b; +xu_ex1_flush_d <= xu_rf1_flush; +ex1_valid_d <= xu_mm_rf1_val and not(xu_rf1_flush); +ex1_ttype_d <= xu_mm_rf1_is_tlbre & xu_mm_rf1_is_tlbwe & xu_mm_rf1_is_tlbsx & xu_mm_rf1_is_tlbsxr & xu_mm_rf1_is_tlbsrx; +ex1_state_d(0) <= or_reduce(xu_mm_msr_pr and xu_mm_rf1_val); +ex1_state_d(1) <= or_reduce(xu_mm_msr_gs and xu_mm_rf1_val); +ex1_state_d(2) <= or_reduce(xu_mm_msr_ds and xu_mm_rf1_val); +ex1_state_d(3) <= or_reduce(xu_mm_msr_cm and xu_mm_rf1_val); +ex1_state_d(4) <= or_reduce(xu_mm_msr_is and xu_mm_rf1_val); +ex1_pid_d <= (pid0 and (0 to pid_width-1 => xu_mm_rf1_val(0))) + or (pid1 and (0 to pid_width-1 => xu_mm_rf1_val(1))) + or (pid2 and (0 to pid_width-1 => xu_mm_rf1_val(2))) + or (pid3 and (0 to pid_width-1 => xu_mm_rf1_val(3))); +ex1_mas0_atsel <= (mas0_0_atsel and ex1_valid_q(0)) + or (mas0_1_atsel and ex1_valid_q(1)) + or (mas0_2_atsel and ex1_valid_q(2)) + or (mas0_3_atsel and ex1_valid_q(3)); +ex1_mas0_esel <= (mas0_0_esel and (0 to 2 => ex1_valid_q(0))) + or (mas0_1_esel and (0 to 2 => ex1_valid_q(1))) + or (mas0_2_esel and (0 to 2 => ex1_valid_q(2))) + or (mas0_3_esel and (0 to 2 => ex1_valid_q(3))); +ex1_mas0_hes <= (mas0_0_hes and ex1_valid_q(0)) + or (mas0_1_hes and ex1_valid_q(1)) + or (mas0_2_hes and ex1_valid_q(2)) + or (mas0_3_hes and ex1_valid_q(3)); +ex1_mas0_wq <= (mas0_0_wq and (0 to 1 => ex1_valid_q(0))) + or (mas0_1_wq and (0 to 1 => ex1_valid_q(1))) + or (mas0_2_wq and (0 to 1 => ex1_valid_q(2))) + or (mas0_3_wq and (0 to 1 => ex1_valid_q(3))); +ex1_mas1_tid <= (mas1_0_tid and (0 to pid_width-1 => ex1_valid_q(0))) + or (mas1_1_tid and (0 to pid_width-1 => ex1_valid_q(1))) + or (mas1_2_tid and (0 to pid_width-1 => ex1_valid_q(2))) + or (mas1_3_tid and (0 to pid_width-1 => ex1_valid_q(3))); +ex1_mas1_ts <= (mas1_0_ts and ex1_valid_q(0)) + or (mas1_1_ts and ex1_valid_q(1)) + or (mas1_2_ts and ex1_valid_q(2)) + or (mas1_3_ts and ex1_valid_q(3)); +ex1_mas1_tsize <= (mas1_0_tsize and (0 to 3 => ex1_valid_q(0))) + or (mas1_1_tsize and (0 to 3 => ex1_valid_q(1))) + or (mas1_2_tsize and (0 to 3 => ex1_valid_q(2))) + or (mas1_3_tsize and (0 to 3 => ex1_valid_q(3))); +ex1_mas1_ind <= (mas1_0_ind and ex1_valid_q(0)) + or (mas1_1_ind and ex1_valid_q(1)) + or (mas1_2_ind and ex1_valid_q(2)) + or (mas1_3_ind and ex1_valid_q(3)); +ex1_mas1_v <= (mas1_0_v and ex1_valid_q(0)) + or (mas1_1_v and ex1_valid_q(1)) + or (mas1_2_v and ex1_valid_q(2)) + or (mas1_3_v and ex1_valid_q(3)); +ex1_mas1_iprot <= (mas1_0_iprot and ex1_valid_q(0)) + or (mas1_1_iprot and ex1_valid_q(1)) + or (mas1_2_iprot and ex1_valid_q(2)) + or (mas1_3_iprot and ex1_valid_q(3)); +ex1_mas2_epn <= (mas2_0_epn(52-epn_width to 51) and (52-epn_width to 51 => ex1_valid_q(0))) + or (mas2_1_epn(52-epn_width to 51) and (52-epn_width to 51 => ex1_valid_q(1))) + or (mas2_2_epn(52-epn_width to 51) and (52-epn_width to 51 => ex1_valid_q(2))) + or (mas2_3_epn(52-epn_width to 51) and (52-epn_width to 51 => ex1_valid_q(3))); +ex1_mas8_tgs <= (mas8_0_tgs and ex1_valid_q(0)) + or (mas8_1_tgs and ex1_valid_q(1)) + or (mas8_2_tgs and ex1_valid_q(2)) + or (mas8_3_tgs and ex1_valid_q(3)); +ex1_mas8_tlpid <= (mas8_0_tlpid and (0 to lpid_width-1 => ex1_valid_q(0))) + or (mas8_1_tlpid and (0 to lpid_width-1 => ex1_valid_q(1))) + or (mas8_2_tlpid and (0 to lpid_width-1 => ex1_valid_q(2))) + or (mas8_3_tlpid and (0 to lpid_width-1 => ex1_valid_q(3))); +-- state: 0:pr 1:gs 2:as 3:cm +ex1_mmucr3_class <= (mmucr3_0(54 to 55) and (54 to 55 => ex1_valid_q(0))) + or (mmucr3_1(54 to 55) and (54 to 55 => ex1_valid_q(1))) + or (mmucr3_2(54 to 55) and (54 to 55 => ex1_valid_q(2))) + or (mmucr3_3(54 to 55) and (54 to 55 => ex1_valid_q(3))); +ex2_mas0_atsel <= (mas0_0_atsel and ex2_valid_q(0)) + or (mas0_1_atsel and ex2_valid_q(1)) + or (mas0_2_atsel and ex2_valid_q(2)) + or (mas0_3_atsel and ex2_valid_q(3)); +ex2_mas0_esel <= (mas0_0_esel and (0 to 2 => ex2_valid_q(0))) + or (mas0_1_esel and (0 to 2 => ex2_valid_q(1))) + or (mas0_2_esel and (0 to 2 => ex2_valid_q(2))) + or (mas0_3_esel and (0 to 2 => ex2_valid_q(3))); +ex2_mas0_hes <= (mas0_0_hes and ex2_valid_q(0)) + or (mas0_1_hes and ex2_valid_q(1)) + or (mas0_2_hes and ex2_valid_q(2)) + or (mas0_3_hes and ex2_valid_q(3)); +ex2_mas0_wq <= (mas0_0_wq and (0 to 1 => ex2_valid_q(0))) + or (mas0_1_wq and (0 to 1 => ex2_valid_q(1))) + or (mas0_2_wq and (0 to 1 => ex2_valid_q(2))) + or (mas0_3_wq and (0 to 1 => ex2_valid_q(3))); +ex2_mas1_ind <= (mas1_0_ind and ex2_valid_q(0)) + or (mas1_1_ind and ex2_valid_q(1)) + or (mas1_2_ind and ex2_valid_q(2)) + or (mas1_3_ind and ex2_valid_q(3)); +ex2_mas1_tid <= (mas1_0_tid and (0 to pid_width-1 => ex2_valid_q(0))) + or (mas1_1_tid and (0 to pid_width-1 => ex2_valid_q(1))) + or (mas1_2_tid and (0 to pid_width-1 => ex2_valid_q(2))) + or (mas1_3_tid and (0 to pid_width-1 => ex2_valid_q(3))); +ex2_mas5_1_state <= ((ex2_state_q(0) & mas5_0_sgs & mas1_0_ts & ex2_state_q(3)) and (0 to 3 => ex2_valid_q(0))) + or ((ex2_state_q(0) & mas5_1_sgs & mas1_1_ts & ex2_state_q(3)) and (0 to 3 => ex2_valid_q(1))) + or ((ex2_state_q(0) & mas5_2_sgs & mas1_2_ts & ex2_state_q(3)) and (0 to 3 => ex2_valid_q(2))) + or ((ex2_state_q(0) & mas5_3_sgs & mas1_3_ts & ex2_state_q(3)) and (0 to 3 => ex2_valid_q(3))); +ex2_mas5_6_state <= ((ex2_state_q(0) & mas5_0_sgs & mas6_0_sas & ex2_state_q(3)) and (0 to 3 => ex2_valid_q(0))) + or ((ex2_state_q(0) & mas5_1_sgs & mas6_1_sas & ex2_state_q(3)) and (0 to 3 => ex2_valid_q(1))) + or ((ex2_state_q(0) & mas5_2_sgs & mas6_2_sas & ex2_state_q(3)) and (0 to 3 => ex2_valid_q(2))) + or ((ex2_state_q(0) & mas5_3_sgs & mas6_3_sas & ex2_state_q(3)) and (0 to 3 => ex2_valid_q(3))); +ex2_mas5_slpid <= (mas5_0_slpid and (0 to lpid_width-1 => ex2_valid_q(0))) + or (mas5_1_slpid and (0 to lpid_width-1 => ex2_valid_q(1))) + or (mas5_2_slpid and (0 to lpid_width-1 => ex2_valid_q(2))) + or (mas5_3_slpid and (0 to lpid_width-1 => ex2_valid_q(3))); +ex2_mas6_spid <= (mas6_0_spid and (0 to pid_width-1 => ex2_valid_q(0))) + or (mas6_1_spid and (0 to pid_width-1 => ex2_valid_q(1))) + or (mas6_2_spid and (0 to pid_width-1 => ex2_valid_q(2))) + or (mas6_3_spid and (0 to pid_width-1 => ex2_valid_q(3))); +ex2_mas6_sind <= (mas6_0_sind and ex2_valid_q(0)) + or (mas6_1_sind and ex2_valid_q(1)) + or (mas6_2_sind and ex2_valid_q(2)) + or (mas6_3_sind and ex2_valid_q(3)); +ex2_valid_d <= ex1_valid_q and not(xu_ex1_flush); +ex2_flush_d <= (ex1_valid_q and xu_ex1_flush) when ex1_ttype_q/="00000" else "0000"; +ex2_flush_req_d <= (ex1_valid_q and not(xu_ex1_flush)) when (ex1_ttype_q(0 to 1)/="00" + and read_req_taken_sig='0' and write_req_taken_sig='0') + else "0000"; +ex2_ttype_d <= ex1_ttype_q; +ex2_state_d <= ex1_state_q; +ex2_pid_d <= ex1_pid_q; +ex2_flush_req_local <= ex2_valid_q when (ex2_ttype_q(2 to 4)/="000" and search_req_taken_sig='0' and searchresv_req_taken_sig='0') + else "0000"; +-- state: 0:pr 1:gs 2:as 3:cm +ex2_hv_state <= not ex2_state_q(0) and not ex2_state_q(1); +ex6_hv_state <= not ex6_state_q(0) and not ex6_state_q(1); +ex6_priv_state <= not ex6_state_q(0); +ex6_dgtmi_state <= or_reduce(ex6_valid_q and xu_mm_epcr_dgtmi); +ex3_valid_d <= ex2_valid_q and not(xu_ex2_flush) and not(ex2_flush_req_q) and not(ex2_flush_req_local); +ex3_flush_d <= ((ex2_valid_q and xu_ex2_flush) or ex2_flush_q or ex2_flush_req_q or ex2_flush_req_local) when ex2_ttype_q/="00000" else "0000"; +ex3_ttype_d <= ex2_ttype_q; +ex3_state_d <= ex2_state_q; +ex3_pid_d <= ex2_pid_q; +tlb_ctl_ex3_valid <= ex3_valid_q; +tlb_ctl_ex3_ttype <= ex3_ttype_q; +ex4_valid_d <= ex3_valid_q and not(xu_ex3_flush); +ex4_flush_d <= ((ex3_valid_q and xu_ex3_flush) or ex3_flush_q) when ex3_ttype_q/="00000" else "0000"; +ex4_ttype_d <= ex3_ttype_q; +-- state: 0:pr 1:gs 2:as 3:cm +ex4_state_d <= ex3_state_q; +ex4_pid_d <= ex3_pid_q; +ex5_valid_d <= ex4_valid_q and not(xu_ex4_flush); +ex5_flush_d <= ((ex4_valid_q and xu_ex4_flush) or ex4_flush_q) when ex4_ttype_q/="00000" else "0000"; +ex5_ttype_d <= ex4_ttype_q; +ex5_state_d <= ex4_state_q; +ex5_pid_d <= ex4_pid_q; +-- ex6 phase are holding latches for non-flushed tlbre,we,sx until tlb_seq is done +ex6_valid_d <= (others => '0') when (tlb_seq_read_done_sig='1' or tlb_seq_write_done_sig='1' or + tlb_seq_search_done_sig='1' or tlb_seq_searchresv_done_sig='1') + else (ex5_valid_q and not(xu_ex5_flush)) when (ex6_valid_q="0000" and ex5_ttype_q/="00000") + else ex6_valid_q; +ex6_flush_d <= ((ex5_valid_q and xu_ex5_flush) or ex5_flush_q) when ex5_ttype_q/="00000" else "0000"; +ex6_ttype_d <= ex5_ttype_q when ex6_valid_q="0000" + else ex6_ttype_q; +ex6_state_d <= ex5_state_q when ex6_valid_q="0000" + else ex6_state_q; +ex6_pid_d <= ex5_pid_q when ex6_valid_q="0000" + else ex6_pid_q; +tlb_ctl_barrier_done <= ex6_valid_q when (tlb_seq_search_done_sig='1' or tlb_seq_searchresv_done_sig='1' or + tlb_seq_read_done_sig='1' or tlb_seq_write_done_sig='1' ) + else (others => '0'); +-- TLB Reservations +-- ttype <= tlbre & tlbwe & tlbsx & tlbsxr & tlbsrx; +-- mas0.wq: 00=ignore reserv, 01=write if reserved, 10=clear reserv, 11=not used +-- reservation set: +-- (1) proc completion of tlbsrx. when no reservation exists +-- (2) proc holding resv executes another tlbsrx. thus establishing new resv +tlb_set_resv0 <= '1' when (ex6_valid_q(0)='1' and ex6_ttype_q(4)='1' and tlb_seq_set_resv='1') + else '0'; +tlb_set_resv1 <= '1' when (ex6_valid_q(1)='1' and ex6_ttype_q(4)='1' and tlb_seq_set_resv='1') + else '0'; +tlb_set_resv2 <= '1' when (ex6_valid_q(2)='1' and ex6_ttype_q(4)='1' and tlb_seq_set_resv='1') + else '0'; +tlb_set_resv3 <= '1' when (ex6_valid_q(3)='1' and ex6_ttype_q(4)='1' and tlb_seq_set_resv='1') + else '0'; +-- reservation clear: +-- (1) proc holding resv executes another tlbsrx. overwriting the old resv +-- (2) any tlbivax snoop with gs,as,lpid,pid,sizemasked(epn,mas6.isize) matching resv.gs,as,lpid,pid,sizemasked(epn,mas6.isize) +-- (note ind bit is not part of tlbivax criteria!!) +-- (3) any proc sets mmucsr0.TLB0_FI=1 with lpidr matching resv.lpid +-- (4) any proc executes tlbilx T=0 (all) with mas5.slpid matching resv.lpid +-- (5) any proc executes tlbilx T=1 (pid) with mas5.slpid and mas6.spid matching resv.lpid,pid +-- (6) any proc executes tlbilx T=3 (vpn) with mas gs,as,slpid,spid,sizemasked(epn,mas6.isize) matching +-- resv.gs,as,lpid,pid,sizemasked(epn,mas6.isize) +-- (note ind bit is not part of tlbilx criteria!!) +-- (7a) any proc executes tlbwe not causing exception and with (wq=00 always, or wq=01 and proc holds resv) +-- and mas regs ind,tgs,ts,tlpid,tid,sizemasked(epn,mas1.tsize) match resv.ind,gs,as,lpid,pid,sizemasked(epn,mas1.tsize) +-- (7b) this proc executes tlbwe not causing exception and with (wq=10 clear my resv regardless of va) +-- (8) any page table reload not causing an exception (due to pt fault, tlb inelig, or lrat miss) +-- and PTE's tag ind=0,tgs,ts,tlpid,tid,sizemasked(epn,pte.size) match resv.ind=0,gs,as,lpid,pid,sizemasked(epn.pte.size) +-- A2-specific non-architected clear states +-- (9) any proc executes tlbwe not causing exception and with (wq=10 clear, or wq=11 always (same as 00)) +-- and mas regs ind,tgs,ts,tlpid,tid,sizemasked(epn,mas1.tsize) match resv.ind,gs,as,lpid,pid,sizemasked(epn,mas1.tsize) +-- (basically same as 7) +-- (10) any proc executes tlbilx T=2 (gs) with mas5.sgs matching resv.gs +-- (11) any proc executes tlbilx T=4 to 7 (class) with T(1:2) matching resv.class +-- ttype <= tlbre & tlbwe & tlbsx & tlbsxr & tlbsrx; +-- IS0: Local bit +-- IS1/Class: 0=all, 1=tid, 2=gs, 3=vpn, 4=class0, 5=class1, 6=class2, 7=class3 +-- mas0.wq: 00=ignore reserv write always, 01=write if reserved, 10=clear reserv, 11=same as 00 +tlb_clr_resv_d(0) <= + (tlb_seq_snoop_resv_q(0) and Eq(tlb_tag1_q(tagpos_is to tagpos_is+3),"0011") and tlb_resv0_tag1_lpid_match and + tlb_resv0_tag1_pid_match and tlb_resv0_tag1_gs_snoop_match and + tlb_resv0_tag1_as_snoop_match and tlb_resv0_tag1_epn_glob_match) + or (tlb_seq_snoop_resv_q(0) and Eq(tlb_tag1_q(tagpos_is to tagpos_is+3),"1000") and tlb_resv0_tag1_lpid_match) + or (tlb_seq_snoop_resv_q(0) and Eq(tlb_tag1_q(tagpos_is to tagpos_is+3),"1001") and + tlb_resv0_tag1_lpid_match and tlb_resv0_tag1_pid_match) + or (tlb_seq_snoop_resv_q(0) and Eq(tlb_tag1_q(tagpos_is to tagpos_is+3),"1011") and tlb_resv0_tag1_lpid_match and + tlb_resv0_tag1_pid_match and tlb_resv0_tag1_gs_snoop_match and + tlb_resv0_tag1_as_snoop_match and tlb_resv0_tag1_epn_loc_match) + or ( ((or_reduce(ex6_valid_q and tlb_resv_valid_vec) and Eq(tlb_tag4_wq,"01")) or + (or_reduce(ex6_valid_q) and Eq(tlb_tag4_wq,"00"))) and ex6_ttype_q(1) and + tlb_resv0_tag1_gs_tlbwe_match and tlb_resv0_tag1_as_tlbwe_match and + tlb_resv0_tag1_lpid_match and tlb_resv0_tag1_pid_match and + tlb_resv0_tag1_epn_loc_match and tlb_resv0_tag1_ind_match ) + or ( ex6_valid_q(0) and Eq(tlb_tag4_wq,"10") and ex6_ttype_q(1) ) + or ( tlb_tag4_ptereload and + tlb_resv0_tag1_gs_snoop_match and tlb_resv0_tag1_as_snoop_match and + tlb_resv0_tag1_lpid_match and tlb_resv0_tag1_pid_match and + tlb_resv0_tag1_epn_loc_match and tlb_resv0_tag1_ind_match ) + or ( ((or_reduce(ex6_valid_q) and Eq(tlb_tag4_wq,"10")) or + (or_reduce(ex6_valid_q) and Eq(tlb_tag4_wq,"11"))) and ex6_ttype_q(1) and + tlb_resv0_tag1_gs_tlbwe_match and tlb_resv0_tag1_as_tlbwe_match and + tlb_resv0_tag1_lpid_match and tlb_resv0_tag1_pid_match and + tlb_resv0_tag1_epn_loc_match and tlb_resv0_tag1_ind_match ) + or (tlb_seq_snoop_resv_q(0) and Eq(tlb_tag1_q(tagpos_is to tagpos_is+1),"11") and + tlb_resv0_tag1_class_match); +tlb_clr_resv_d(1) <= + (tlb_seq_snoop_resv_q(1) and Eq(tlb_tag1_q(tagpos_is to tagpos_is+3),"0011") and tlb_resv1_tag1_lpid_match and + tlb_resv1_tag1_pid_match and tlb_resv1_tag1_gs_snoop_match and + tlb_resv1_tag1_as_snoop_match and tlb_resv1_tag1_epn_glob_match) + or (tlb_seq_snoop_resv_q(1) and Eq(tlb_tag1_q(tagpos_is to tagpos_is+3),"1000") and tlb_resv1_tag1_lpid_match) + or (tlb_seq_snoop_resv_q(1) and Eq(tlb_tag1_q(tagpos_is to tagpos_is+3),"1001") and + tlb_resv1_tag1_lpid_match and tlb_resv1_tag1_pid_match) + or (tlb_seq_snoop_resv_q(1) and Eq(tlb_tag1_q(tagpos_is to tagpos_is+3),"1011") and tlb_resv1_tag1_lpid_match and + tlb_resv1_tag1_pid_match and tlb_resv1_tag1_gs_snoop_match and + tlb_resv1_tag1_as_snoop_match and tlb_resv1_tag1_epn_loc_match) + or ( ((or_reduce(ex6_valid_q and tlb_resv_valid_vec) and Eq(tlb_tag4_wq,"01")) or + (or_reduce(ex6_valid_q) and Eq(tlb_tag4_wq,"00"))) and ex6_ttype_q(1) and + tlb_resv1_tag1_gs_tlbwe_match and tlb_resv1_tag1_as_tlbwe_match and + tlb_resv1_tag1_lpid_match and tlb_resv1_tag1_pid_match and + tlb_resv1_tag1_epn_loc_match and tlb_resv1_tag1_ind_match ) + or ( ex6_valid_q(1) and Eq(tlb_tag4_wq,"10") and ex6_ttype_q(1) ) + or ( tlb_tag4_ptereload and + tlb_resv1_tag1_gs_snoop_match and tlb_resv1_tag1_as_snoop_match and + tlb_resv1_tag1_lpid_match and tlb_resv1_tag1_pid_match and + tlb_resv1_tag1_epn_loc_match and tlb_resv1_tag1_ind_match ) + or ( ((or_reduce(ex6_valid_q) and Eq(tlb_tag4_wq,"10")) or + (or_reduce(ex6_valid_q) and Eq(tlb_tag4_wq,"11"))) and ex6_ttype_q(1) and + tlb_resv1_tag1_gs_tlbwe_match and tlb_resv1_tag1_as_tlbwe_match and + tlb_resv1_tag1_lpid_match and tlb_resv1_tag1_pid_match and + tlb_resv1_tag1_epn_loc_match and tlb_resv1_tag1_ind_match ) + or (tlb_seq_snoop_resv_q(1) and Eq(tlb_tag1_q(tagpos_is to tagpos_is+1),"11") and + tlb_resv1_tag1_class_match); +tlb_clr_resv_d(2) <= + (tlb_seq_snoop_resv_q(2) and Eq(tlb_tag1_q(tagpos_is to tagpos_is+3),"0011") and tlb_resv2_tag1_lpid_match and + tlb_resv2_tag1_pid_match and tlb_resv2_tag1_gs_snoop_match and + tlb_resv2_tag1_as_snoop_match and tlb_resv2_tag1_epn_glob_match) + or (tlb_seq_snoop_resv_q(2) and Eq(tlb_tag1_q(tagpos_is to tagpos_is+3),"1000") and tlb_resv2_tag1_lpid_match) + or (tlb_seq_snoop_resv_q(2) and Eq(tlb_tag1_q(tagpos_is to tagpos_is+3),"1001") and + tlb_resv2_tag1_lpid_match and tlb_resv2_tag1_pid_match) + or (tlb_seq_snoop_resv_q(2) and Eq(tlb_tag1_q(tagpos_is to tagpos_is+3),"1011") and tlb_resv2_tag1_lpid_match and + tlb_resv2_tag1_pid_match and tlb_resv2_tag1_gs_snoop_match and + tlb_resv2_tag1_as_snoop_match and tlb_resv2_tag1_epn_loc_match) + or ( ((or_reduce(ex6_valid_q and tlb_resv_valid_vec) and Eq(tlb_tag4_wq,"01")) or + (or_reduce(ex6_valid_q) and Eq(tlb_tag4_wq,"00"))) and ex6_ttype_q(1) and + tlb_resv2_tag1_gs_tlbwe_match and tlb_resv2_tag1_as_tlbwe_match and + tlb_resv2_tag1_lpid_match and tlb_resv2_tag1_pid_match and + tlb_resv2_tag1_epn_loc_match and tlb_resv2_tag1_ind_match ) + or ( ex6_valid_q(2) and Eq(tlb_tag4_wq,"10") and ex6_ttype_q(1) ) + or ( tlb_tag4_ptereload and + tlb_resv2_tag1_gs_snoop_match and tlb_resv2_tag1_as_snoop_match and + tlb_resv2_tag1_lpid_match and tlb_resv2_tag1_pid_match and + tlb_resv2_tag1_epn_loc_match and tlb_resv2_tag1_ind_match ) + or ( ((or_reduce(ex6_valid_q) and Eq(tlb_tag4_wq,"10")) or + (or_reduce(ex6_valid_q) and Eq(tlb_tag4_wq,"11"))) and ex6_ttype_q(1) and + tlb_resv2_tag1_gs_tlbwe_match and tlb_resv2_tag1_as_tlbwe_match and + tlb_resv2_tag1_lpid_match and tlb_resv2_tag1_pid_match and + tlb_resv2_tag1_epn_loc_match and tlb_resv2_tag1_ind_match ) + or (tlb_seq_snoop_resv_q(2) and Eq(tlb_tag1_q(tagpos_is to tagpos_is+1),"11") and + tlb_resv2_tag1_class_match); +tlb_clr_resv_d(3) <= + (tlb_seq_snoop_resv_q(3) and Eq(tlb_tag1_q(tagpos_is to tagpos_is+3),"0011") and tlb_resv3_tag1_lpid_match and + tlb_resv3_tag1_pid_match and tlb_resv3_tag1_gs_snoop_match and + tlb_resv3_tag1_as_snoop_match and tlb_resv3_tag1_epn_glob_match) + or (tlb_seq_snoop_resv_q(3) and Eq(tlb_tag1_q(tagpos_is to tagpos_is+3),"1000") and tlb_resv3_tag1_lpid_match) + or (tlb_seq_snoop_resv_q(3) and Eq(tlb_tag1_q(tagpos_is to tagpos_is+3),"1001") and + tlb_resv3_tag1_lpid_match and tlb_resv3_tag1_pid_match) + or (tlb_seq_snoop_resv_q(3) and Eq(tlb_tag1_q(tagpos_is to tagpos_is+3),"1011") and tlb_resv3_tag1_lpid_match and + tlb_resv3_tag1_pid_match and tlb_resv3_tag1_gs_snoop_match and + tlb_resv3_tag1_as_snoop_match and tlb_resv3_tag1_epn_loc_match) + or ( ((or_reduce(ex6_valid_q and tlb_resv_valid_vec) and Eq(tlb_tag4_wq,"01")) or + (or_reduce(ex6_valid_q) and Eq(tlb_tag4_wq,"00"))) and ex6_ttype_q(1) and + tlb_resv3_tag1_gs_tlbwe_match and tlb_resv3_tag1_as_tlbwe_match and + tlb_resv3_tag1_lpid_match and tlb_resv3_tag1_pid_match and + tlb_resv3_tag1_epn_loc_match and tlb_resv3_tag1_ind_match ) + or ( ex6_valid_q(3) and Eq(tlb_tag4_wq,"10") and ex6_ttype_q(1) ) + or ( tlb_tag4_ptereload and + tlb_resv3_tag1_gs_snoop_match and tlb_resv3_tag1_as_snoop_match and + tlb_resv3_tag1_lpid_match and tlb_resv3_tag1_pid_match and + tlb_resv3_tag1_epn_loc_match and tlb_resv3_tag1_ind_match ) + or ( ((or_reduce(ex6_valid_q) and Eq(tlb_tag4_wq,"10")) or + (or_reduce(ex6_valid_q) and Eq(tlb_tag4_wq,"11"))) and ex6_ttype_q(1) and + tlb_resv3_tag1_gs_tlbwe_match and tlb_resv3_tag1_as_tlbwe_match and + tlb_resv3_tag1_lpid_match and tlb_resv3_tag1_pid_match and + tlb_resv3_tag1_epn_loc_match and tlb_resv3_tag1_ind_match ) + or (tlb_seq_snoop_resv_q(3) and Eq(tlb_tag1_q(tagpos_is to tagpos_is+1),"11") and + tlb_resv3_tag1_class_match); +tlb_resv_valid_vec <= tlb_resv0_valid_q & tlb_resv1_valid_q & tlb_resv2_valid_q & tlb_resv3_valid_q; +tlb_resv_match_vec <= tlb_resv_match_vec_q; +tlb_resv0_valid_d <= '0' when tlb_clr_resv_q(0)='1' and tlb_tag5_except(0)='0' + else ex6_valid_q(0) when tlb_set_resv0='1' + else tlb_resv0_valid_q; +tlb_resv0_epn_d <= tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-1) when (tlb_set_resv0='1') + else tlb_resv0_epn_q; +tlb_resv0_pid_d <= mas1_0_tid when (tlb_set_resv0='1') + else tlb_resv0_pid_q; +tlb_resv0_lpid_d <= mas5_0_slpid when (tlb_set_resv0='1') + else tlb_resv0_lpid_q; +tlb_resv0_as_d <= mas1_0_ts when (tlb_set_resv0='1') + else tlb_resv0_as_q; +tlb_resv0_gs_d <= mas5_0_sgs when (tlb_set_resv0='1') + else tlb_resv0_gs_q; +tlb_resv0_ind_d <= mas1_0_ind when (tlb_set_resv0='1') + else tlb_resv0_ind_q; +tlb_resv0_class_d <= mmucr3_0(54 to 55) when (tlb_set_resv0='1') + else tlb_resv0_class_q; +-- uniquify snoop/tlbwe as/gs match sigs because tagpos_as/gs are msr state for tlbwe, not mas values +tlb_resv0_tag0_lpid_match <= '1' when (tlb_tag0_q(tagpos_lpid to tagpos_lpid+lpid_width-1)=tlb_resv0_lpid_q) else '0'; +tlb_resv0_tag0_pid_match <= '1' when (tlb_tag0_q(tagpos_pid to tagpos_pid+pid_width-1)=tlb_resv0_pid_q) else '0'; +tlb_resv0_tag0_gs_snoop_match <= '1' when (tlb_tag0_q(tagpos_gs)=tlb_resv0_gs_q) else '0'; +tlb_resv0_tag0_as_snoop_match <= '1' when (tlb_tag0_q(tagpos_as)=tlb_resv0_as_q) else '0'; +-- unused tagpos_pt, tagpos_recform def are mas8_tgs, mas1_ts for tlbwe +tlb_resv0_tag0_gs_tlbwe_match <= '1' when (tlb_tag0_q(tagpos_pt)=tlb_resv0_gs_q) else '0'; +tlb_resv0_tag0_as_tlbwe_match <= '1' when (tlb_tag0_q(tagpos_recform)=tlb_resv0_as_q) else '0'; +tlb_resv0_tag0_ind_match <= '1' when (tlb_tag0_q(tagpos_ind)=tlb_resv0_ind_q) else '0'; +tlb_resv0_tag0_class_match <= '1' when (tlb_tag0_q(tagpos_class to tagpos_class+1)=tlb_resv0_class_q) else '0'; +-- local match includes upper epn bits +tlb_resv0_tag0_epn_loc_match <= '1' when (tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-1)=tlb_resv0_epn_q(52-epn_width to 51) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_4KB) or + (tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-5)=tlb_resv0_epn_q(52-epn_width to 47) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_64KB) or + (tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-9)=tlb_resv0_epn_q(52-epn_width to 43) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1MB) or + (tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-13)=tlb_resv0_epn_q(52-epn_width to 39) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_16MB) or + (tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-17)=tlb_resv0_epn_q(52-epn_width to 35) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_256MB) or + (tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-19)=tlb_resv0_epn_q(52-epn_width to 33) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1GB) + else '0'; +-- global match ignores certain upper epn bits that are not tranferred over bus +-- fix me!! use various upper nibbles dependent on pgsize and mmucr1.tlbi_msb +tlb_resv0_tag0_epn_glob_match <= '1' when (tlb_tag0_q(tagpos_epn+31 to tagpos_epn+epn_width-1)=tlb_resv0_epn_q(52-epn_width+31 to 51) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_4KB) or + (tlb_tag0_q(tagpos_epn+31 to tagpos_epn+epn_width-5)=tlb_resv0_epn_q(52-epn_width+31 to 47) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_64KB) or + (tlb_tag0_q(tagpos_epn+31 to tagpos_epn+epn_width-9)=tlb_resv0_epn_q(52-epn_width+31 to 43) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1MB) or + (tlb_tag0_q(tagpos_epn+31 to tagpos_epn+epn_width-13)=tlb_resv0_epn_q(52-epn_width+31 to 39) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_16MB) or + (tlb_tag0_q(tagpos_epn+31 to tagpos_epn+epn_width-17)=tlb_resv0_epn_q(52-epn_width+31 to 35) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_256MB) or + (tlb_tag0_q(tagpos_epn+31 to tagpos_epn+epn_width-19)=tlb_resv0_epn_q(52-epn_width+31 to 33) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1GB) + else '0'; +-- NOTE: ind is part of reservation tlbwe/ptereload match criteria, but not invalidate criteria +tlb_resv_match_vec_d(0) <= (tlb_resv0_valid_q and tlb_tag0_q(tagpos_type_snoop)='1' + and tlb_resv0_tag0_epn_loc_match and tlb_resv0_tag0_lpid_match and tlb_resv0_tag0_pid_match + and tlb_resv0_tag0_as_snoop_match and tlb_resv0_tag0_gs_snoop_match) or + (tlb_resv0_valid_q and tlb_tag0_q(tagpos_type_tlbwe)='1' + and tlb_resv0_tag0_epn_loc_match and tlb_resv0_tag0_lpid_match and tlb_resv0_tag0_pid_match + and tlb_resv0_tag0_as_tlbwe_match and tlb_resv0_tag0_gs_tlbwe_match and tlb_resv0_tag0_ind_match) or + (tlb_resv0_valid_q and tlb_tag0_q(tagpos_type_ptereload)='1' + and tlb_resv0_tag0_epn_loc_match and tlb_resv0_tag0_lpid_match and tlb_resv0_tag0_pid_match + and tlb_resv0_tag0_as_snoop_match and tlb_resv0_tag0_gs_snoop_match and tlb_resv0_tag0_ind_match); +tlb_resv1_valid_d <= '0' when tlb_clr_resv_q(1)='1' and tlb_tag5_except(1)='0' + else ex6_valid_q(1) when tlb_set_resv1='1' + else tlb_resv1_valid_q; +tlb_resv1_epn_d <= tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-1) when (tlb_set_resv1='1') + else tlb_resv1_epn_q; +tlb_resv1_pid_d <= mas1_1_tid when (tlb_set_resv1='1') + else tlb_resv1_pid_q; +tlb_resv1_lpid_d <= mas5_1_slpid when (tlb_set_resv1='1') + else tlb_resv1_lpid_q; +tlb_resv1_as_d <= mas1_1_ts when (tlb_set_resv1='1') + else tlb_resv1_as_q; +tlb_resv1_gs_d <= mas5_1_sgs when (tlb_set_resv1='1') + else tlb_resv1_gs_q; +tlb_resv1_ind_d <= mas1_1_ind when (tlb_set_resv1='1') + else tlb_resv1_ind_q; +tlb_resv1_class_d <= mmucr3_1(54 to 55) when (tlb_set_resv1='1') + else tlb_resv1_class_q; +-- uniquify snoop/tlbwe as/gs match sigs because tagpos_as/gs are msr state for tlbwe, not mas values +tlb_resv1_tag0_lpid_match <= '1' when (tlb_tag0_q(tagpos_lpid to tagpos_lpid+lpid_width-1)=tlb_resv1_lpid_q) else '0'; +tlb_resv1_tag0_pid_match <= '1' when (tlb_tag0_q(tagpos_pid to tagpos_pid+pid_width-1)=tlb_resv1_pid_q) else '0'; +tlb_resv1_tag0_gs_snoop_match <= '1' when (tlb_tag0_q(tagpos_gs)=tlb_resv1_gs_q) else '0'; +tlb_resv1_tag0_as_snoop_match <= '1' when (tlb_tag0_q(tagpos_as)=tlb_resv1_as_q) else '0'; +-- unused tagpos_pt, tagpos_recform def are mas8_tgs, mas1_ts for tlbwe +tlb_resv1_tag0_gs_tlbwe_match <= '1' when (tlb_tag0_q(tagpos_pt)=tlb_resv1_gs_q) else '0'; +tlb_resv1_tag0_as_tlbwe_match <= '1' when (tlb_tag0_q(tagpos_recform)=tlb_resv1_as_q) else '0'; +tlb_resv1_tag0_ind_match <= '1' when (tlb_tag0_q(tagpos_ind)=tlb_resv1_ind_q) else '0'; +tlb_resv1_tag0_class_match <= '1' when (tlb_tag0_q(tagpos_class to tagpos_class+1)=tlb_resv1_class_q) else '0'; +-- local match includes upper epn bits +tlb_resv1_tag0_epn_loc_match <= '1' when (tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-1)=tlb_resv1_epn_q(52-epn_width to 51) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_4KB) or + (tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-5)=tlb_resv1_epn_q(52-epn_width to 47) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_64KB) or + (tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-9)=tlb_resv1_epn_q(52-epn_width to 43) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1MB) or + (tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-13)=tlb_resv1_epn_q(52-epn_width to 39) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_16MB) or + (tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-17)=tlb_resv1_epn_q(52-epn_width to 35) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_256MB) or + (tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-19)=tlb_resv1_epn_q(52-epn_width to 33) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1GB) + else '0'; +-- global match ignores certain upper epn bits that are not tranferred over bus +-- fix me!! use various upper nibbles dependent on pgsize and mmucr1.tlbi_msb +tlb_resv1_tag0_epn_glob_match <= '1' when (tlb_tag0_q(tagpos_epn+31 to tagpos_epn+epn_width-1)=tlb_resv1_epn_q(52-epn_width+31 to 51) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_4KB) or + (tlb_tag0_q(tagpos_epn+31 to tagpos_epn+epn_width-5)=tlb_resv1_epn_q(52-epn_width+31 to 47) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_64KB) or + (tlb_tag0_q(tagpos_epn+31 to tagpos_epn+epn_width-9)=tlb_resv1_epn_q(52-epn_width+31 to 43) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1MB) or + (tlb_tag0_q(tagpos_epn+31 to tagpos_epn+epn_width-13)=tlb_resv1_epn_q(52-epn_width+31 to 39) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_16MB) or + (tlb_tag0_q(tagpos_epn+31 to tagpos_epn+epn_width-17)=tlb_resv1_epn_q(52-epn_width+31 to 35) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_256MB) or + (tlb_tag0_q(tagpos_epn+31 to tagpos_epn+epn_width-19)=tlb_resv1_epn_q(52-epn_width+31 to 33) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1GB) + else '0'; +-- NOTE: ind is part of reservation tlbwe/ptereload match criteria, but not invalidate criteria +tlb_resv_match_vec_d(1) <= (tlb_resv1_valid_q and tlb_tag0_q(tagpos_type_snoop)='1' + and tlb_resv1_tag0_epn_loc_match and tlb_resv1_tag0_lpid_match and tlb_resv1_tag0_pid_match + and tlb_resv1_tag0_as_snoop_match and tlb_resv1_tag0_gs_snoop_match) or + (tlb_resv1_valid_q and tlb_tag0_q(tagpos_type_tlbwe)='1' + and tlb_resv1_tag0_epn_loc_match and tlb_resv1_tag0_lpid_match and tlb_resv1_tag0_pid_match + and tlb_resv1_tag0_as_tlbwe_match and tlb_resv1_tag0_gs_tlbwe_match and tlb_resv1_tag0_ind_match) or + (tlb_resv1_valid_q and tlb_tag0_q(tagpos_type_ptereload)='1' + and tlb_resv1_tag0_epn_loc_match and tlb_resv1_tag0_lpid_match and tlb_resv1_tag0_pid_match + and tlb_resv1_tag0_as_snoop_match and tlb_resv1_tag0_gs_snoop_match and tlb_resv1_tag0_ind_match); +tlb_resv2_valid_d <= '0' when tlb_clr_resv_q(2)='1' and tlb_tag5_except(2)='0' + else ex6_valid_q(2) when tlb_set_resv2='1' + else tlb_resv2_valid_q; +tlb_resv2_epn_d <= tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-1) when (tlb_set_resv2='1') + else tlb_resv2_epn_q; +tlb_resv2_pid_d <= mas1_2_tid when (tlb_set_resv2='1') + else tlb_resv2_pid_q; +tlb_resv2_lpid_d <= mas5_2_slpid when (tlb_set_resv2='1') + else tlb_resv2_lpid_q; +tlb_resv2_as_d <= mas1_2_ts when (tlb_set_resv2='1') + else tlb_resv2_as_q; +tlb_resv2_gs_d <= mas5_2_sgs when (tlb_set_resv2='1') + else tlb_resv2_gs_q; +tlb_resv2_ind_d <= mas1_2_ind when (tlb_set_resv2='1') + else tlb_resv2_ind_q; +tlb_resv2_class_d <= mmucr3_2(54 to 55) when (tlb_set_resv2='1') + else tlb_resv2_class_q; +-- uniquify snoop/tlbwe as/gs match sigs because tagpos_as/gs are msr state for tlbwe, not mas values +tlb_resv2_tag0_lpid_match <= '1' when (tlb_tag0_q(tagpos_lpid to tagpos_lpid+lpid_width-1)=tlb_resv2_lpid_q) else '0'; +tlb_resv2_tag0_pid_match <= '1' when (tlb_tag0_q(tagpos_pid to tagpos_pid+pid_width-1)=tlb_resv2_pid_q) else '0'; +tlb_resv2_tag0_gs_snoop_match <= '1' when (tlb_tag0_q(tagpos_gs)=tlb_resv2_gs_q) else '0'; +tlb_resv2_tag0_as_snoop_match <= '1' when (tlb_tag0_q(tagpos_as)=tlb_resv2_as_q) else '0'; +-- unused tagpos_pt, tagpos_recform def are mas8_tgs, mas1_ts for tlbwe +tlb_resv2_tag0_gs_tlbwe_match <= '1' when (tlb_tag0_q(tagpos_pt)=tlb_resv2_gs_q) else '0'; +tlb_resv2_tag0_as_tlbwe_match <= '1' when (tlb_tag0_q(tagpos_recform)=tlb_resv2_as_q) else '0'; +tlb_resv2_tag0_ind_match <= '1' when (tlb_tag0_q(tagpos_ind)=tlb_resv2_ind_q) else '0'; +tlb_resv2_tag0_class_match <= '1' when (tlb_tag0_q(tagpos_class to tagpos_class+1)=tlb_resv2_class_q) else '0'; +-- local match includes upper epn bits +tlb_resv2_tag0_epn_loc_match <= '1' when (tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-1)=tlb_resv2_epn_q(52-epn_width to 51) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_4KB) or + (tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-5)=tlb_resv2_epn_q(52-epn_width to 47) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_64KB) or + (tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-9)=tlb_resv2_epn_q(52-epn_width to 43) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1MB) or + (tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-13)=tlb_resv2_epn_q(52-epn_width to 39) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_16MB) or + (tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-17)=tlb_resv2_epn_q(52-epn_width to 35) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_256MB) or + (tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-19)=tlb_resv2_epn_q(52-epn_width to 33) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1GB) + else '0'; +-- global match ignores certain upper epn bits that are not tranferred over bus +-- fix me!! use various upper nibbles dependent on pgsize and mmucr1.tlbi_msb +tlb_resv2_tag0_epn_glob_match <= '1' when (tlb_tag0_q(tagpos_epn+31 to tagpos_epn+epn_width-1)=tlb_resv2_epn_q(52-epn_width+31 to 51) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_4KB) or + (tlb_tag0_q(tagpos_epn+31 to tagpos_epn+epn_width-5)=tlb_resv2_epn_q(52-epn_width+31 to 47) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_64KB) or + (tlb_tag0_q(tagpos_epn+31 to tagpos_epn+epn_width-9)=tlb_resv2_epn_q(52-epn_width+31 to 43) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1MB) or + (tlb_tag0_q(tagpos_epn+31 to tagpos_epn+epn_width-13)=tlb_resv2_epn_q(52-epn_width+31 to 39) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_16MB) or + (tlb_tag0_q(tagpos_epn+31 to tagpos_epn+epn_width-17)=tlb_resv2_epn_q(52-epn_width+31 to 35) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_256MB) or + (tlb_tag0_q(tagpos_epn+31 to tagpos_epn+epn_width-19)=tlb_resv2_epn_q(52-epn_width+31 to 33) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1GB) + else '0'; +-- NOTE: ind is part of reservation tlbwe/ptereload match criteria, but not invalidate criteria +tlb_resv_match_vec_d(2) <= (tlb_resv2_valid_q and tlb_tag0_q(tagpos_type_snoop)='1' + and tlb_resv2_tag0_epn_loc_match and tlb_resv2_tag0_lpid_match and tlb_resv2_tag0_pid_match + and tlb_resv2_tag0_as_snoop_match and tlb_resv2_tag0_gs_snoop_match) or + (tlb_resv2_valid_q and tlb_tag0_q(tagpos_type_tlbwe)='1' + and tlb_resv2_tag0_epn_loc_match and tlb_resv2_tag0_lpid_match and tlb_resv2_tag0_pid_match + and tlb_resv2_tag0_as_tlbwe_match and tlb_resv2_tag0_gs_tlbwe_match and tlb_resv2_tag0_ind_match) or + (tlb_resv2_valid_q and tlb_tag0_q(tagpos_type_ptereload)='1' + and tlb_resv2_tag0_epn_loc_match and tlb_resv2_tag0_lpid_match and tlb_resv2_tag0_pid_match + and tlb_resv2_tag0_as_snoop_match and tlb_resv2_tag0_gs_snoop_match and tlb_resv2_tag0_ind_match); +tlb_resv3_valid_d <= '0' when tlb_clr_resv_q(3)='1' and tlb_tag5_except(3)='0' + else ex6_valid_q(3) when tlb_set_resv3='1' + else tlb_resv3_valid_q; +tlb_resv3_epn_d <= tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-1) when (tlb_set_resv3='1') + else tlb_resv3_epn_q; +tlb_resv3_pid_d <= mas1_3_tid when (tlb_set_resv3='1') + else tlb_resv3_pid_q; +tlb_resv3_lpid_d <= mas5_3_slpid when (tlb_set_resv3='1') + else tlb_resv3_lpid_q; +tlb_resv3_as_d <= mas1_3_ts when (tlb_set_resv3='1') + else tlb_resv3_as_q; +tlb_resv3_gs_d <= mas5_3_sgs when (tlb_set_resv3='1') + else tlb_resv3_gs_q; +tlb_resv3_ind_d <= mas1_3_ind when (tlb_set_resv3='1') + else tlb_resv3_ind_q; +tlb_resv3_class_d <= mmucr3_3(54 to 55) when (tlb_set_resv3='1') + else tlb_resv3_class_q; +tlb_resv3_tag0_lpid_match <= '1' when (tlb_tag0_q(tagpos_lpid to tagpos_lpid+lpid_width-1)=tlb_resv3_lpid_q) else '0'; +tlb_resv3_tag0_pid_match <= '1' when (tlb_tag0_q(tagpos_pid to tagpos_pid+pid_width-1)=tlb_resv3_pid_q) else '0'; +tlb_resv3_tag0_gs_snoop_match <= '1' when (tlb_tag0_q(tagpos_gs)=tlb_resv3_gs_q) else '0'; +tlb_resv3_tag0_as_snoop_match <= '1' when (tlb_tag0_q(tagpos_as)=tlb_resv3_as_q) else '0'; +-- unused tagpos_pt, tagpos_recform def are mas8_tgs, mas1_ts for tlbwe +tlb_resv3_tag0_gs_tlbwe_match <= '1' when (tlb_tag0_q(tagpos_pt)=tlb_resv3_gs_q) else '0'; +tlb_resv3_tag0_as_tlbwe_match <= '1' when (tlb_tag0_q(tagpos_recform)=tlb_resv3_as_q) else '0'; +tlb_resv3_tag0_ind_match <= '1' when (tlb_tag0_q(tagpos_ind)=tlb_resv3_ind_q) else '0'; +tlb_resv3_tag0_class_match <= '1' when (tlb_tag0_q(tagpos_class to tagpos_class+1)=tlb_resv3_class_q) else '0'; +-- local match includes upper epn bits +tlb_resv3_tag0_epn_loc_match <= '1' when (tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-1)=tlb_resv3_epn_q(52-epn_width to 51) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_4KB) or + (tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-5)=tlb_resv3_epn_q(52-epn_width to 47) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_64KB) or + (tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-9)=tlb_resv3_epn_q(52-epn_width to 43) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1MB) or + (tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-13)=tlb_resv3_epn_q(52-epn_width to 39) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_16MB) or + (tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-17)=tlb_resv3_epn_q(52-epn_width to 35) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_256MB) or + (tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-19)=tlb_resv3_epn_q(52-epn_width to 33) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1GB) + else '0'; +-- global match ignores certain upper epn bits that are not tranferred over bus +-- fix me!! use various upper nibbles dependent on pgsize and mmucr1.tlbi_msb +tlb_resv3_tag0_epn_glob_match <= '1' when (tlb_tag0_q(tagpos_epn+31 to tagpos_epn+epn_width-1)=tlb_resv3_epn_q(52-epn_width+31 to 51) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_4KB) or + (tlb_tag0_q(tagpos_epn+31 to tagpos_epn+epn_width-5)=tlb_resv3_epn_q(52-epn_width+31 to 47) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_64KB) or + (tlb_tag0_q(tagpos_epn+31 to tagpos_epn+epn_width-9)=tlb_resv3_epn_q(52-epn_width+31 to 43) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1MB) or + (tlb_tag0_q(tagpos_epn+31 to tagpos_epn+epn_width-13)=tlb_resv3_epn_q(52-epn_width+31 to 39) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_16MB) or + (tlb_tag0_q(tagpos_epn+31 to tagpos_epn+epn_width-17)=tlb_resv3_epn_q(52-epn_width+31 to 35) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_256MB) or + (tlb_tag0_q(tagpos_epn+31 to tagpos_epn+epn_width-19)=tlb_resv3_epn_q(52-epn_width+31 to 33) and tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1GB) + else '0'; +-- NOTE: ind is part of reservation tlbwe/ptereload match criteria, but not invalidate criteria +tlb_resv_match_vec_d(3) <= (tlb_resv3_valid_q and tlb_tag0_q(tagpos_type_snoop)='1' + and tlb_resv3_tag0_epn_loc_match and tlb_resv3_tag0_lpid_match and tlb_resv3_tag0_pid_match + and tlb_resv3_tag0_as_snoop_match and tlb_resv3_tag0_gs_snoop_match) or + (tlb_resv3_valid_q and tlb_tag0_q(tagpos_type_tlbwe)='1' + and tlb_resv3_tag0_epn_loc_match and tlb_resv3_tag0_lpid_match and tlb_resv3_tag0_pid_match + and tlb_resv3_tag0_as_tlbwe_match and tlb_resv3_tag0_gs_tlbwe_match and tlb_resv3_tag0_ind_match) or + (tlb_resv3_valid_q and tlb_tag0_q(tagpos_type_ptereload)='1' + and tlb_resv3_tag0_epn_loc_match and tlb_resv3_tag0_lpid_match and tlb_resv3_tag0_pid_match + and tlb_resv3_tag0_as_snoop_match and tlb_resv3_tag0_gs_snoop_match and tlb_resv3_tag0_ind_match); +tlbaddrwidth7_gen: if tlb_addr_width = 7 generate +-- TLB Address Hash xor terms per size +-- 4K 64K 1M 16M 256M 1G +------------------------------------------------- +-- 6 51 44 37 47 37 43 36 39 35 33 +-- 5 50 43 36 46 36 42 35 38 34 32 +-- 4 49 42 35 45 35 41 34 37 33 31 +-- 3 48 41 34 44 34 40 33 36 32 32 30 +-- 2 47 40 33 43 40 33 39 32 35 31 31 29 +-- 1 46 39 32 42 39 32 38 31 34 30 30 28 28 +-- 0 45 38 31 41 38 31 37 30 33 29 29 27 27 +size_1G_hashed_addr(6) <= tlb_tag0_q(33) xor tlb_tag0_q(tagpos_pid+pid_width-1); +size_1G_hashed_addr(5) <= tlb_tag0_q(32) xor tlb_tag0_q(tagpos_pid+pid_width-2); +size_1G_hashed_addr(4) <= tlb_tag0_q(31) xor tlb_tag0_q(tagpos_pid+pid_width-3); +size_1G_hashed_addr(3) <= tlb_tag0_q(30) xor tlb_tag0_q(tagpos_pid+pid_width-4); +size_1G_hashed_addr(2) <= tlb_tag0_q(29) xor tlb_tag0_q(tagpos_pid+pid_width-5); +size_1G_hashed_addr(1) <= tlb_tag0_q(28) xor tlb_tag0_q(tagpos_pid+pid_width-6); +size_1G_hashed_addr(0) <= tlb_tag0_q(27) xor tlb_tag0_q(tagpos_pid+pid_width-7); +size_1G_hashed_tid0_addr(6) <= tlb_tag0_q(33); +size_1G_hashed_tid0_addr(5) <= tlb_tag0_q(32); +size_1G_hashed_tid0_addr(4) <= tlb_tag0_q(31); +size_1G_hashed_tid0_addr(3) <= tlb_tag0_q(30); +size_1G_hashed_tid0_addr(2) <= tlb_tag0_q(29); +size_1G_hashed_tid0_addr(1) <= tlb_tag0_q(28); +size_1G_hashed_tid0_addr(0) <= tlb_tag0_q(27); +size_256M_hashed_addr(6) <= tlb_tag0_q(35) xor tlb_tag0_q(tagpos_pid+pid_width-1); +size_256M_hashed_addr(5) <= tlb_tag0_q(34) xor tlb_tag0_q(tagpos_pid+pid_width-2); +size_256M_hashed_addr(4) <= tlb_tag0_q(33) xor tlb_tag0_q(tagpos_pid+pid_width-3); +size_256M_hashed_addr(3) <= tlb_tag0_q(32) xor tlb_tag0_q(tagpos_pid+pid_width-4); +size_256M_hashed_addr(2) <= tlb_tag0_q(31) xor tlb_tag0_q(tagpos_pid+pid_width-5); +size_256M_hashed_addr(1) <= tlb_tag0_q(30) xor tlb_tag0_q(28) xor tlb_tag0_q(tagpos_pid+pid_width-6); +size_256M_hashed_addr(0) <= tlb_tag0_q(29) xor tlb_tag0_q(27) xor tlb_tag0_q(tagpos_pid+pid_width-7); +size_256M_hashed_tid0_addr(6) <= tlb_tag0_q(35); +size_256M_hashed_tid0_addr(5) <= tlb_tag0_q(34); +size_256M_hashed_tid0_addr(4) <= tlb_tag0_q(33); +size_256M_hashed_tid0_addr(3) <= tlb_tag0_q(32); +size_256M_hashed_tid0_addr(2) <= tlb_tag0_q(31); +size_256M_hashed_tid0_addr(1) <= tlb_tag0_q(30) xor tlb_tag0_q(28); +size_256M_hashed_tid0_addr(0) <= tlb_tag0_q(29) xor tlb_tag0_q(27); +size_16M_hashed_addr(6) <= tlb_tag0_q(39) xor tlb_tag0_q(tagpos_pid+pid_width-1); +size_16M_hashed_addr(5) <= tlb_tag0_q(38) xor tlb_tag0_q(tagpos_pid+pid_width-2); +size_16M_hashed_addr(4) <= tlb_tag0_q(37) xor tlb_tag0_q(tagpos_pid+pid_width-3); +size_16M_hashed_addr(3) <= tlb_tag0_q(36) xor tlb_tag0_q(32) xor tlb_tag0_q(tagpos_pid+pid_width-4); +size_16M_hashed_addr(2) <= tlb_tag0_q(35) xor tlb_tag0_q(31) xor tlb_tag0_q(tagpos_pid+pid_width-5); +size_16M_hashed_addr(1) <= tlb_tag0_q(34) xor tlb_tag0_q(30) xor tlb_tag0_q(tagpos_pid+pid_width-6); +size_16M_hashed_addr(0) <= tlb_tag0_q(33) xor tlb_tag0_q(29) xor tlb_tag0_q(tagpos_pid+pid_width-7); +size_16M_hashed_tid0_addr(6) <= tlb_tag0_q(39); +size_16M_hashed_tid0_addr(5) <= tlb_tag0_q(38); +size_16M_hashed_tid0_addr(4) <= tlb_tag0_q(37); +size_16M_hashed_tid0_addr(3) <= tlb_tag0_q(36) xor tlb_tag0_q(32); +size_16M_hashed_tid0_addr(2) <= tlb_tag0_q(35) xor tlb_tag0_q(31); +size_16M_hashed_tid0_addr(1) <= tlb_tag0_q(34) xor tlb_tag0_q(30); +size_16M_hashed_tid0_addr(0) <= tlb_tag0_q(33) xor tlb_tag0_q(29); +size_1M_hashed_addr(6) <= tlb_tag0_q(43) xor tlb_tag0_q(36) xor tlb_tag0_q(tagpos_pid+pid_width-1); +size_1M_hashed_addr(5) <= tlb_tag0_q(42) xor tlb_tag0_q(35) xor tlb_tag0_q(tagpos_pid+pid_width-2); +size_1M_hashed_addr(4) <= tlb_tag0_q(41) xor tlb_tag0_q(34) xor tlb_tag0_q(tagpos_pid+pid_width-3); +size_1M_hashed_addr(3) <= tlb_tag0_q(40) xor tlb_tag0_q(33) xor tlb_tag0_q(tagpos_pid+pid_width-4); +size_1M_hashed_addr(2) <= tlb_tag0_q(39) xor tlb_tag0_q(32) xor tlb_tag0_q(tagpos_pid+pid_width-5); +size_1M_hashed_addr(1) <= tlb_tag0_q(38) xor tlb_tag0_q(31) xor tlb_tag0_q(tagpos_pid+pid_width-6); +size_1M_hashed_addr(0) <= tlb_tag0_q(37) xor tlb_tag0_q(30) xor tlb_tag0_q(tagpos_pid+pid_width-7); +size_1M_hashed_tid0_addr(6) <= tlb_tag0_q(43) xor tlb_tag0_q(36); +size_1M_hashed_tid0_addr(5) <= tlb_tag0_q(42) xor tlb_tag0_q(35); +size_1M_hashed_tid0_addr(4) <= tlb_tag0_q(41) xor tlb_tag0_q(34); +size_1M_hashed_tid0_addr(3) <= tlb_tag0_q(40) xor tlb_tag0_q(33); +size_1M_hashed_tid0_addr(2) <= tlb_tag0_q(39) xor tlb_tag0_q(32); +size_1M_hashed_tid0_addr(1) <= tlb_tag0_q(38) xor tlb_tag0_q(31); +size_1M_hashed_tid0_addr(0) <= tlb_tag0_q(37) xor tlb_tag0_q(30); +size_64K_hashed_addr(6) <= tlb_tag0_q(47) xor tlb_tag0_q(37) xor tlb_tag0_q(tagpos_pid+pid_width-1); +size_64K_hashed_addr(5) <= tlb_tag0_q(46) xor tlb_tag0_q(36) xor tlb_tag0_q(tagpos_pid+pid_width-2); +size_64K_hashed_addr(4) <= tlb_tag0_q(45) xor tlb_tag0_q(35) xor tlb_tag0_q(tagpos_pid+pid_width-3); +size_64K_hashed_addr(3) <= tlb_tag0_q(44) xor tlb_tag0_q(34) xor tlb_tag0_q(tagpos_pid+pid_width-4); +size_64K_hashed_addr(2) <= tlb_tag0_q(43) xor tlb_tag0_q(40) xor tlb_tag0_q(33) xor tlb_tag0_q(tagpos_pid+pid_width-5); +size_64K_hashed_addr(1) <= tlb_tag0_q(42) xor tlb_tag0_q(39) xor tlb_tag0_q(32) xor tlb_tag0_q(tagpos_pid+pid_width-6); +size_64K_hashed_addr(0) <= tlb_tag0_q(41) xor tlb_tag0_q(38) xor tlb_tag0_q(31) xor tlb_tag0_q(tagpos_pid+pid_width-7); +size_64K_hashed_tid0_addr(6) <= tlb_tag0_q(47) xor tlb_tag0_q(37); +size_64K_hashed_tid0_addr(5) <= tlb_tag0_q(46) xor tlb_tag0_q(36); +size_64K_hashed_tid0_addr(4) <= tlb_tag0_q(45) xor tlb_tag0_q(35); +size_64K_hashed_tid0_addr(3) <= tlb_tag0_q(44) xor tlb_tag0_q(34); +size_64K_hashed_tid0_addr(2) <= tlb_tag0_q(43) xor tlb_tag0_q(40) xor tlb_tag0_q(33); +size_64K_hashed_tid0_addr(1) <= tlb_tag0_q(42) xor tlb_tag0_q(39) xor tlb_tag0_q(32); +size_64K_hashed_tid0_addr(0) <= tlb_tag0_q(41) xor tlb_tag0_q(38) xor tlb_tag0_q(31); +size_4K_hashed_addr(6) <= tlb_tag0_q(51) xor tlb_tag0_q(44) xor tlb_tag0_q(37) xor tlb_tag0_q(tagpos_pid+pid_width-1); +size_4K_hashed_addr(5) <= tlb_tag0_q(50) xor tlb_tag0_q(43) xor tlb_tag0_q(36) xor tlb_tag0_q(tagpos_pid+pid_width-2); +size_4K_hashed_addr(4) <= tlb_tag0_q(49) xor tlb_tag0_q(42) xor tlb_tag0_q(35) xor tlb_tag0_q(tagpos_pid+pid_width-3); +size_4K_hashed_addr(3) <= tlb_tag0_q(48) xor tlb_tag0_q(41) xor tlb_tag0_q(34) xor tlb_tag0_q(tagpos_pid+pid_width-4); +size_4K_hashed_addr(2) <= tlb_tag0_q(47) xor tlb_tag0_q(40) xor tlb_tag0_q(33) xor tlb_tag0_q(tagpos_pid+pid_width-5); +size_4K_hashed_addr(1) <= tlb_tag0_q(46) xor tlb_tag0_q(39) xor tlb_tag0_q(32) xor tlb_tag0_q(tagpos_pid+pid_width-6); +size_4K_hashed_addr(0) <= tlb_tag0_q(45) xor tlb_tag0_q(38) xor tlb_tag0_q(31) xor tlb_tag0_q(tagpos_pid+pid_width-7); +size_4K_hashed_tid0_addr(6) <= tlb_tag0_q(51) xor tlb_tag0_q(44) xor tlb_tag0_q(37); +size_4K_hashed_tid0_addr(5) <= tlb_tag0_q(50) xor tlb_tag0_q(43) xor tlb_tag0_q(36); +size_4K_hashed_tid0_addr(4) <= tlb_tag0_q(49) xor tlb_tag0_q(42) xor tlb_tag0_q(35); +size_4K_hashed_tid0_addr(3) <= tlb_tag0_q(48) xor tlb_tag0_q(41) xor tlb_tag0_q(34); +size_4K_hashed_tid0_addr(2) <= tlb_tag0_q(47) xor tlb_tag0_q(40) xor tlb_tag0_q(33); +size_4K_hashed_tid0_addr(1) <= tlb_tag0_q(46) xor tlb_tag0_q(39) xor tlb_tag0_q(32); +size_4K_hashed_tid0_addr(0) <= tlb_tag0_q(45) xor tlb_tag0_q(38) xor tlb_tag0_q(31); +end generate tlbaddrwidth7_gen; +--constant TLB_PgSize_1GB := 1010 ; +--constant TLB_PgSize_256MB := 1001 ; +--constant TLB_PgSize_16MB := 0111 ; +--constant TLB_PgSize_1MB := 0101 ; +--constant TLB_PgSize_64KB := 0011 ; +--constant TLB_PgSize_4KB := 0001 ; +tlb_tag0_tid_notzero <= or_reduce(tlb_tag0_q(tagpos_pid to tagpos_pid+pid_width-1)); +-- these are used for direct and indirect page sizes +tlb_tag0_hashed_addr <= size_1G_hashed_addr when tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1GB + else size_256M_hashed_addr when tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_256MB + else size_16M_hashed_addr when tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_16MB + else size_1M_hashed_addr when tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1MB + else size_64K_hashed_addr when tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_64KB + else size_4K_hashed_addr; +tlb_tag0_hashed_tid0_addr <= size_1G_hashed_tid0_addr when tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1GB + else size_256M_hashed_tid0_addr when tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_256MB + else size_16M_hashed_tid0_addr when tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_16MB + else size_1M_hashed_tid0_addr when tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1MB + else size_64K_hashed_tid0_addr when tlb_tag0_q(tagpos_size to tagpos_size+3)=TLB_PgSize_64KB + else size_4K_hashed_tid0_addr; +-- these are used for direct page sizes only +tlb_hashed_addr1 <= size_1G_hashed_addr when mmucr2(28 to 31)=TLB_PgSize_1GB + else size_16M_hashed_addr when mmucr2(28 to 31)=TLB_PgSize_16MB + else size_1M_hashed_addr when mmucr2(28 to 31)=TLB_PgSize_1MB + else size_64K_hashed_addr when mmucr2(28 to 31)=TLB_PgSize_64KB + else size_4K_hashed_addr; +tlb_hashed_tid0_addr1 <= size_1G_hashed_tid0_addr when mmucr2(28 to 31)=TLB_PgSize_1GB + else size_16M_hashed_tid0_addr when mmucr2(28 to 31)=TLB_PgSize_16MB + else size_1M_hashed_tid0_addr when mmucr2(28 to 31)=TLB_PgSize_1MB + else size_64K_hashed_tid0_addr when mmucr2(28 to 31)=TLB_PgSize_64KB + else size_4K_hashed_tid0_addr; +tlb_hashed_addr2 <= size_1G_hashed_addr when mmucr2(24 to 27)=TLB_PgSize_1GB + else size_16M_hashed_addr when mmucr2(24 to 27)=TLB_PgSize_16MB + else size_1M_hashed_addr when mmucr2(24 to 27)=TLB_PgSize_1MB + else size_64K_hashed_addr when mmucr2(24 to 27)=TLB_PgSize_64KB + else size_4K_hashed_addr; +tlb_hashed_tid0_addr2 <= size_1G_hashed_tid0_addr when mmucr2(24 to 27)=TLB_PgSize_1GB + else size_16M_hashed_tid0_addr when mmucr2(24 to 27)=TLB_PgSize_16MB + else size_1M_hashed_tid0_addr when mmucr2(24 to 27)=TLB_PgSize_1MB + else size_64K_hashed_tid0_addr when mmucr2(24 to 27)=TLB_PgSize_64KB + else size_4K_hashed_tid0_addr; +tlb_hashed_addr3 <= size_1G_hashed_addr when mmucr2(20 to 23)=TLB_PgSize_1GB + else size_16M_hashed_addr when mmucr2(20 to 23)=TLB_PgSize_16MB + else size_1M_hashed_addr when mmucr2(20 to 23)=TLB_PgSize_1MB + else size_64K_hashed_addr when mmucr2(20 to 23)=TLB_PgSize_64KB + else size_4K_hashed_addr; +tlb_hashed_tid0_addr3 <= size_1G_hashed_tid0_addr when mmucr2(20 to 23)=TLB_PgSize_1GB + else size_16M_hashed_tid0_addr when mmucr2(20 to 23)=TLB_PgSize_16MB + else size_1M_hashed_tid0_addr when mmucr2(20 to 23)=TLB_PgSize_1MB + else size_64K_hashed_tid0_addr when mmucr2(20 to 23)=TLB_PgSize_64KB + else size_4K_hashed_tid0_addr; +tlb_hashed_addr4 <= size_1G_hashed_addr when mmucr2(16 to 19)=TLB_PgSize_1GB + else size_16M_hashed_addr when mmucr2(16 to 19)=TLB_PgSize_16MB + else size_1M_hashed_addr when mmucr2(16 to 19)=TLB_PgSize_1MB + else size_64K_hashed_addr when mmucr2(16 to 19)=TLB_PgSize_64KB + else size_4K_hashed_addr; +tlb_hashed_tid0_addr4 <= size_1G_hashed_tid0_addr when mmucr2(16 to 19)=TLB_PgSize_1GB + else size_16M_hashed_tid0_addr when mmucr2(16 to 19)=TLB_PgSize_16MB + else size_1M_hashed_tid0_addr when mmucr2(16 to 19)=TLB_PgSize_1MB + else size_64K_hashed_tid0_addr when mmucr2(16 to 19)=TLB_PgSize_64KB + else size_4K_hashed_tid0_addr; +tlb_hashed_addr5 <= size_1G_hashed_addr when mmucr2(12 to 15)=TLB_PgSize_1GB + else size_16M_hashed_addr when mmucr2(12 to 15)=TLB_PgSize_16MB + else size_1M_hashed_addr when mmucr2(12 to 15)=TLB_PgSize_1MB + else size_64K_hashed_addr when mmucr2(12 to 15)=TLB_PgSize_64KB + else size_4K_hashed_addr; +tlb_hashed_tid0_addr5 <= size_1G_hashed_tid0_addr when mmucr2(12 to 15)=TLB_PgSize_1GB + else size_16M_hashed_tid0_addr when mmucr2(12 to 15)=TLB_PgSize_16MB + else size_1M_hashed_tid0_addr when mmucr2(12 to 15)=TLB_PgSize_1MB + else size_64K_hashed_tid0_addr when mmucr2(12 to 15)=TLB_PgSize_64KB + else size_4K_hashed_tid0_addr; +pgsize1_valid <= '1' when mmucr2(28 to 31) /= "0000" else '0'; +pgsize2_valid <= '1' when mmucr2(24 to 27) /= "0000" else '0'; +pgsize3_valid <= '1' when mmucr2(20 to 23) /= "0000" else '0'; +pgsize4_valid <= '1' when mmucr2(16 to 19) /= "0000" else '0'; +pgsize5_valid <= '1' when mmucr2(12 to 15) /= "0000" else '0'; +pgsize1_tid0_valid <= '1' when mmucr2(28 to 31) /= "0000" else '0'; +pgsize2_tid0_valid <= '1' when mmucr2(24 to 27) /= "0000" else '0'; +pgsize3_tid0_valid <= '1' when mmucr2(20 to 23) /= "0000" else '0'; +pgsize4_tid0_valid <= '1' when mmucr2(16 to 19) /= "0000" else '0'; +pgsize5_tid0_valid <= '1' when mmucr2(12 to 15) /= "0000" else '0'; +pgsize_qty <= "101" when (pgsize5_valid='1' and pgsize4_valid='1' and pgsize3_valid='1' and pgsize2_valid='1' and pgsize1_valid='1') + else "100" when (pgsize4_valid='1' and pgsize3_valid='1' and pgsize2_valid='1' and pgsize1_valid='1') + else "011" when (pgsize3_valid='1' and pgsize2_valid='1' and pgsize1_valid='1') + else "010" when (pgsize2_valid='1' and pgsize1_valid='1') + else "001" when (pgsize1_valid='1') + else "000"; +pgsize_tid0_qty <= "101" when (pgsize5_tid0_valid='1' and pgsize4_tid0_valid='1' and pgsize3_tid0_valid='1' and pgsize2_tid0_valid='1' and pgsize1_tid0_valid='1') + else "100" when (pgsize4_tid0_valid='1' and pgsize3_tid0_valid='1' and pgsize2_tid0_valid='1' and pgsize1_tid0_valid='1') + else "011" when (pgsize3_tid0_valid='1' and pgsize2_tid0_valid='1' and pgsize1_tid0_valid='1') + else "010" when (pgsize2_tid0_valid='1' and pgsize1_tid0_valid='1') + else "001" when (pgsize1_tid0_valid='1') + else "000"; +derat_taken_d <= '1' when derat_req_taken_sig='1' + else '0' when ierat_req_taken_sig <= '1' + else derat_taken_q; +-- ttype: derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload +tlb_read_req <= '1' when (ex1_valid_q(0 to 3) /= "0000" and ex1_ttype_q(0)='1') else '0'; +tlb_write_req <= '1' when (ex1_valid_q(0 to 3) /= "0000" and ex1_ttype_q(1)='1') else '0'; +tlb_search_req <= '1' when (ex2_valid_q(0 to 3) /= "0000" and ex2_ttype_q(2 to 3)/="00") else '0'; +tlb_searchresv_req <= '1' when (ex2_valid_q(0 to 3) /= "0000" and ex2_ttype_q(4)='1') else '0'; +tlb_seq_idle_sig <= '1' when tlb_seq_q=TlbSeq_Idle else '0'; +tlbwe_back_inv_holdoff <= tlbwe_back_inv_pending and mmucr1_tlbwe_binv; +tlb_seq_any_done_sig <= tlb_seq_ierat_done_sig or tlb_seq_derat_done_sig or tlb_seq_snoop_done_sig or + tlb_seq_search_done_sig or tlb_seq_searchresv_done_sig or tlb_seq_read_done_sig or + tlb_seq_write_done_sig or tlb_seq_ptereload_done_sig; +any_tlb_req_sig <= snoop_val_q(0) or ptereload_req_valid or tlb_seq_ierat_req or tlb_seq_derat_req or + tlb_search_req or tlb_searchresv_req or tlb_write_req or tlb_read_req; +any_req_taken_sig <= ierat_req_taken_sig or derat_req_taken_sig or snoop_req_taken_sig or + search_req_taken_sig or searchresv_req_taken_sig or read_req_taken_sig or + write_req_taken_sig or ptereload_req_taken_sig; +tlb_tag4_hit_or_parerr <= tlb_tag4_cmp_hit or tlb_tag4_parerr; +-- abort control sequencer back to state_idle +-- tlbsx, tlbsrx, tlbre, tlbwe are flushable ops, so short-cycle sequencer +tlb_seq_abort <= or_reduce( tlb_tag0_q(tagpos_thdid to tagpos_thdid+thdid_width-1) + and (tlb_ctl_tag1_flush_sig or tlb_ctl_tag2_flush_sig or tlb_ctl_tag3_flush_sig or tlb_ctl_tag4_flush_sig) ); +tlb_seq_d <= tlb_seq_next and (0 to 5 => not(tlb_seq_abort)); +-- TLB access sequencer for multiple page size compares for reloads +Tlb_Sequencer: PROCESS (tlb_seq_q, tlb_tag0_q(tagpos_is+1 to tagpos_is+3), tlb_tag0_q(tagpos_size to tagpos_size+3), tlb_tag0_q(tagpos_type to tagpos_type+7), + tlb_tag0_q(tagpos_type to tagpos_type+7), tlb_tag1_q(tagpos_endflag), tlb_tag0_tid_notzero, + tlb_tag4_hit_or_parerr, tlb_tag4_way_ind, tlb_addr_maxcntm1, tlb_cmp_erat_dup_wait, + tlb_seq_ierat_req, tlb_seq_derat_req, tlb_search_req, tlb_searchresv_req, + snoop_val_q(0), tlb_read_req, tlb_write_req, ptereload_req_valid, mmucr2(12 to 31), derat_taken_q, + tlb_hashed_addr1, tlb_hashed_addr2, tlb_hashed_addr3, tlb_hashed_addr4, tlb_hashed_addr5, + tlb_hashed_tid0_addr1, tlb_hashed_tid0_addr2, tlb_hashed_tid0_addr3, tlb_hashed_tid0_addr4, tlb_hashed_tid0_addr5, + pgsize2_valid, pgsize3_valid, pgsize4_valid, pgsize5_valid, + pgsize2_tid0_valid, pgsize3_tid0_valid, pgsize4_tid0_valid, pgsize5_tid0_valid, + size_1M_hashed_addr,size_1M_hashed_tid0_addr,size_256M_hashed_addr,size_256M_hashed_tid0_addr, + tlb_tag0_hashed_addr, tlb_tag0_hashed_tid0_addr, tlb0cfg_ind, tlbwe_back_inv_holdoff) +BEGIN +tlb_seq_addr <= (others => '0'); +tlb_seq_pgsize <= mmucr2(28 to 31); +tlb_seq_ind <= '0'; +tlb_seq_esel <= (others => '0'); +tlb_seq_is <= (others => '0'); +tlb_seq_tag0_addr_cap <= '0'; +tlb_seq_addr_update <= '0'; +tlb_seq_addr_clr <= '0'; +tlb_seq_addr_incr <= '0'; +tlb_seq_lrat_enable <= '0'; +tlb_seq_endflag <= '0'; +tlb_seq_ierat_done_sig <= '0'; +tlb_seq_derat_done_sig <= '0'; +tlb_seq_snoop_done_sig <= '0'; +tlb_seq_search_done_sig <= '0'; +tlb_seq_searchresv_done_sig <= '0'; +tlb_seq_read_done_sig <= '0'; +tlb_seq_write_done_sig <= '0'; +tlb_seq_ptereload_done_sig <= '0'; +ierat_req_taken_sig <= '0'; +derat_req_taken_sig <= '0'; +search_req_taken_sig <= '0'; +searchresv_req_taken_sig <= '0'; +snoop_req_taken_sig <= '0'; +read_req_taken_sig <= '0'; +write_req_taken_sig <= '0'; +ptereload_req_taken_sig <= '0'; +tlb_seq_set_resv <= '0'; +tlb_seq_snoop_resv <= '0'; +CASE tlb_seq_q IS + WHEN TlbSeq_Idle => + if snoop_val_q(0)='1' then + tlb_seq_next <= TlbSeq_Stg24; snoop_req_taken_sig <= '1'; + elsif ptereload_req_valid='1' then + tlb_seq_next <= TlbSeq_Stg19; ptereload_req_taken_sig <= '1'; + elsif tlb_seq_ierat_req='1' and tlb_cmp_erat_dup_wait(0)='0' and (derat_taken_q='1' or tlb_seq_derat_req='0') then + tlb_seq_next <= TlbSeq_Stg1; ierat_req_taken_sig <= '1'; + elsif tlb_seq_derat_req='1' and tlb_cmp_erat_dup_wait(1)='0' then + tlb_seq_next <= TlbSeq_Stg1; derat_req_taken_sig <= '1'; + elsif tlb_search_req='1' then + tlb_seq_next <= TlbSeq_Stg1; search_req_taken_sig <= '1'; + elsif tlb_searchresv_req='1' then + tlb_seq_next <= TlbSeq_Stg1; searchresv_req_taken_sig <= '1'; + elsif (tlb_write_req='1' and tlbwe_back_inv_holdoff='0') then + tlb_seq_next <= TlbSeq_Stg19; write_req_taken_sig <= '1'; + elsif tlb_read_req='1' then + tlb_seq_next <= TlbSeq_Stg19; read_req_taken_sig <= '1'; + else + tlb_seq_next <= TlbSeq_Idle; + end if; + WHEN TlbSeq_Stg1 => + tlb_seq_tag0_addr_cap <= '1'; + tlb_seq_addr_update <= '1'; + tlb_seq_addr <= tlb_hashed_addr1; + tlb_seq_pgsize <= mmucr2(28 to 31); + tlb_seq_is <= "00"; + tlb_seq_esel <= "001"; + if pgsize2_valid='1' then + tlb_seq_next <= TlbSeq_Stg2; + else + tlb_seq_next <= TlbSeq_Stg6; + end if; + + WHEN TlbSeq_Stg2 => + tlb_seq_addr_update <= '1'; + tlb_seq_addr <= tlb_hashed_addr2; + tlb_seq_pgsize <= mmucr2(24 to 27); + tlb_seq_is <= "00"; + tlb_seq_esel <= "010"; + if pgsize3_valid='1' then + tlb_seq_next <= TlbSeq_Stg3; + else + tlb_seq_next <= TlbSeq_Stg6; + end if; + + WHEN TlbSeq_Stg3 => + tlb_seq_addr_update <= '1'; + tlb_seq_addr <= tlb_hashed_addr3; + tlb_seq_pgsize <= mmucr2(20 to 23); + tlb_seq_is <= "00"; + tlb_seq_esel <= "011"; + if pgsize4_valid='1' then + tlb_seq_next <= TlbSeq_Stg4; + else + tlb_seq_next <= TlbSeq_Stg6; + end if; + + WHEN TlbSeq_Stg4 => + tlb_seq_addr_update <= '1'; + tlb_seq_addr <= tlb_hashed_addr4; + tlb_seq_pgsize <= mmucr2(16 to 19); + tlb_seq_is <= "00"; + tlb_seq_esel <= "100"; + if pgsize5_valid='1' then + tlb_seq_next <= TlbSeq_Stg5; + else + tlb_seq_next <= TlbSeq_Stg6; + end if; + + WHEN TlbSeq_Stg5 => + tlb_seq_addr_update <= '1'; + tlb_seq_addr <= tlb_hashed_addr5; + tlb_seq_pgsize <= mmucr2(12 to 15); + tlb_seq_is <= "00"; + tlb_seq_esel <= "101"; + if tlb_tag4_hit_or_parerr='1' and or_reduce(tlb_tag0_q(tagpos_type_tlbsx to tagpos_type_tlbsrx))='1' then + tlb_seq_next <= TlbSeq_Stg30; + elsif tlb_tag4_hit_or_parerr='1' and tlb_tag4_way_ind='0' then + tlb_seq_next <= TlbSeq_Stg31; + else + tlb_seq_next <= TlbSeq_Stg6; + end if; + WHEN TlbSeq_Stg6 => + tlb_seq_addr_update <= '1'; + tlb_seq_addr <= tlb_hashed_tid0_addr1; + tlb_seq_pgsize <= mmucr2(28 to 31); + tlb_seq_is <= "01"; + tlb_seq_esel <= "001"; + if tlb_tag4_hit_or_parerr='1' and or_reduce(tlb_tag0_q(tagpos_type_tlbsx to tagpos_type_tlbsrx))='1' then + tlb_seq_next <= TlbSeq_Stg30; + elsif tlb_tag4_hit_or_parerr='1' and tlb_tag4_way_ind='0' then + tlb_seq_next <= TlbSeq_Stg31; + elsif pgsize2_tid0_valid='1' then + tlb_seq_next <= TlbSeq_Stg7; + elsif tlb0cfg_ind='1' then + tlb_seq_next <= TlbSeq_Stg11; + else + tlb_seq_endflag <= '1'; + tlb_seq_next <= TlbSeq_Stg15; + end if; + + WHEN TlbSeq_Stg7 => + tlb_seq_addr_update <= '1'; + tlb_seq_addr <= tlb_hashed_tid0_addr2; + tlb_seq_pgsize <= mmucr2(24 to 27); + tlb_seq_is <= "01"; + tlb_seq_esel <= "010"; + if tlb_tag4_hit_or_parerr='1' and or_reduce(tlb_tag0_q(tagpos_type_tlbsx to tagpos_type_tlbsrx))='1' then + tlb_seq_next <= TlbSeq_Stg30; + elsif tlb_tag4_hit_or_parerr='1' and tlb_tag4_way_ind='0' then + tlb_seq_next <= TlbSeq_Stg31; + elsif pgsize3_tid0_valid='1' then + tlb_seq_next <= TlbSeq_Stg8; + elsif tlb0cfg_ind='1' then + tlb_seq_next <= TlbSeq_Stg11; + else + tlb_seq_endflag <= '1'; + tlb_seq_next <= TlbSeq_Stg15; + end if; + + WHEN TlbSeq_Stg8 => + tlb_seq_addr_update <= '1'; + tlb_seq_addr <= tlb_hashed_tid0_addr3; + tlb_seq_pgsize <= mmucr2(20 to 23); + tlb_seq_is <= "01"; + tlb_seq_esel <= "011"; + if tlb_tag4_hit_or_parerr='1' and or_reduce(tlb_tag0_q(tagpos_type_tlbsx to tagpos_type_tlbsrx))='1' then + tlb_seq_next <= TlbSeq_Stg30; + elsif tlb_tag4_hit_or_parerr='1' and tlb_tag4_way_ind='0' then + tlb_seq_next <= TlbSeq_Stg31; + elsif pgsize4_tid0_valid='1' then + tlb_seq_next <= TlbSeq_Stg9; + elsif tlb0cfg_ind='1' then + tlb_seq_next <= TlbSeq_Stg11; + else + tlb_seq_endflag <= '1'; + tlb_seq_next <= TlbSeq_Stg15; + end if; + + + WHEN TlbSeq_Stg9 => + tlb_seq_addr_update <= '1'; + tlb_seq_addr <= tlb_hashed_tid0_addr4; + tlb_seq_pgsize <= mmucr2(16 to 19); + tlb_seq_is <= "01"; + tlb_seq_esel <= "100"; + if tlb_tag4_hit_or_parerr='1' and or_reduce(tlb_tag0_q(tagpos_type_tlbsx to tagpos_type_tlbsrx))='1' then + tlb_seq_next <= TlbSeq_Stg30; + elsif tlb_tag4_hit_or_parerr='1' and tlb_tag4_way_ind='0' then + tlb_seq_next <= TlbSeq_Stg31; + elsif pgsize5_tid0_valid='1' then + tlb_seq_next <= TlbSeq_Stg10; + elsif tlb0cfg_ind='1' then + tlb_seq_next <= TlbSeq_Stg11; + else + tlb_seq_endflag <= '1'; + tlb_seq_next <= TlbSeq_Stg15; + end if; + + + WHEN TlbSeq_Stg10 => + tlb_seq_addr_update <= '1'; + tlb_seq_addr <= tlb_hashed_tid0_addr5; + tlb_seq_pgsize <= mmucr2(12 to 15); + tlb_seq_is <= "01"; + tlb_seq_esel <= "101"; + if tlb_tag4_hit_or_parerr='1' and or_reduce(tlb_tag0_q(tagpos_type_tlbsx to tagpos_type_tlbsrx))='1' then + tlb_seq_next <= TlbSeq_Stg30; + elsif tlb_tag4_hit_or_parerr='1' and tlb_tag4_way_ind='0' then + tlb_seq_next <= TlbSeq_Stg31; + elsif tlb0cfg_ind='1' then + tlb_seq_next <= TlbSeq_Stg11; + else + tlb_seq_endflag <= '1'; + tlb_seq_next <= TlbSeq_Stg15; + end if; + + WHEN TlbSeq_Stg11 => + tlb_seq_ind <= '1'; + tlb_seq_addr_update <= '1'; + tlb_seq_addr <= size_1M_hashed_addr; + tlb_seq_pgsize <= TLB_PgSize_1MB; + tlb_seq_is <= "10"; + tlb_seq_esel <= "001"; + if tlb_tag4_hit_or_parerr='1' and or_reduce(tlb_tag0_q(tagpos_type_tlbsx to tagpos_type_tlbsrx))='1' then + tlb_seq_next <= TlbSeq_Stg30; + elsif tlb_tag4_hit_or_parerr='1' and tlb_tag4_way_ind='0' then + tlb_seq_next <= TlbSeq_Stg31; + else + tlb_seq_next <= TlbSeq_Stg12; + end if; + + WHEN TlbSeq_Stg12 => + tlb_seq_ind <= '1'; + tlb_seq_addr_update <= '1'; + tlb_seq_addr <= size_256M_hashed_addr; + tlb_seq_pgsize <= TLB_PgSize_256MB; + tlb_seq_is <= "10"; + tlb_seq_esel <= "010"; + if tlb_tag4_hit_or_parerr='1' and or_reduce(tlb_tag0_q(tagpos_type_tlbsx to tagpos_type_tlbsrx))='1' then + tlb_seq_next <= TlbSeq_Stg30; + elsif tlb_tag4_hit_or_parerr='1' and tlb_tag4_way_ind='0' then + tlb_seq_next <= TlbSeq_Stg31; + else + tlb_seq_next <= TlbSeq_Stg13; + end if; + + WHEN TlbSeq_Stg13 => + tlb_seq_ind <= '1'; + tlb_seq_addr_update <= '1'; + tlb_seq_addr <= size_1M_hashed_tid0_addr; + tlb_seq_pgsize <= TLB_PgSize_1MB; + tlb_seq_is <= "11"; + tlb_seq_esel <= "001"; + if tlb_tag4_hit_or_parerr='1' and or_reduce(tlb_tag0_q(tagpos_type_tlbsx to tagpos_type_tlbsrx))='1' then + tlb_seq_next <= TlbSeq_Stg30; + elsif tlb_tag4_hit_or_parerr='1' and tlb_tag4_way_ind='0' then + tlb_seq_next <= TlbSeq_Stg31; + else + tlb_seq_next <= TlbSeq_Stg14; + end if; + + WHEN TlbSeq_Stg14 => + tlb_seq_ind <= '1'; + tlb_seq_addr_update <= '1'; + tlb_seq_addr <= size_256M_hashed_tid0_addr; + tlb_seq_pgsize <= TLB_PgSize_256MB; + tlb_seq_is <= "11"; + tlb_seq_esel <= "010"; + if tlb_tag4_hit_or_parerr='1' and or_reduce(tlb_tag0_q(tagpos_type_tlbsx to tagpos_type_tlbsrx))='1' then + tlb_seq_next <= TlbSeq_Stg30; + elsif tlb_tag4_hit_or_parerr='1' and tlb_tag4_way_ind='0' then + tlb_seq_next <= TlbSeq_Stg31; + else + tlb_seq_endflag <= '1'; + tlb_seq_next <= TlbSeq_Stg15; + end if; + + WHEN TlbSeq_Stg15 => + tlb_seq_addr <= (others => '0'); + tlb_seq_pgsize <= (others => '0'); + if tlb_tag4_hit_or_parerr='1' and or_reduce(tlb_tag0_q(tagpos_type_tlbsx to tagpos_type_tlbsrx))='1' then + tlb_seq_next <= TlbSeq_Stg30; + elsif tlb_tag4_hit_or_parerr='1' and tlb_tag4_way_ind='0' then + tlb_seq_next <= TlbSeq_Stg31; + elsif tlb_tag4_hit_or_parerr='1' and tlb_tag4_way_ind='1' and + or_reduce(tlb_tag0_q(tagpos_type_derat to tagpos_type_ierat))='1' and tlb_tag0_q(tagpos_type_ptereload)='0' then + tlb_seq_next <= TlbSeq_Stg29; + else + tlb_seq_next <= TlbSeq_Stg16; + end if; + + WHEN TlbSeq_Stg16 => + tlb_seq_addr <= (others => '0'); + tlb_seq_pgsize <= (others => '0'); + if tlb_tag4_hit_or_parerr='1' and or_reduce(tlb_tag0_q(tagpos_type_tlbsx to tagpos_type_tlbsrx))='1' then + tlb_seq_next <= TlbSeq_Stg30; + elsif tlb_tag4_hit_or_parerr='1' and tlb_tag4_way_ind='0' then + tlb_seq_next <= TlbSeq_Stg31; + elsif tlb_tag4_hit_or_parerr='1' and tlb_tag4_way_ind='1' then + tlb_seq_next <= TlbSeq_Stg29; + else + tlb_seq_next <= TlbSeq_Stg17; + end if; + + WHEN TlbSeq_Stg17 => + tlb_seq_addr <= (others => '0'); + tlb_seq_pgsize <= (others => '0'); + if tlb_tag4_hit_or_parerr='1' and or_reduce(tlb_tag0_q(tagpos_type_tlbsx to tagpos_type_tlbsrx))='1' then + tlb_seq_next <= TlbSeq_Stg30; + elsif tlb_tag4_hit_or_parerr='1' and tlb_tag4_way_ind='0' then + tlb_seq_next <= TlbSeq_Stg31; + elsif tlb_tag4_hit_or_parerr='1' and tlb_tag4_way_ind='1' then + tlb_seq_next <= TlbSeq_Stg29; + else + tlb_seq_next <= TlbSeq_Stg18; + end if; + + WHEN TlbSeq_Stg18 => + tlb_seq_addr <= (others => '0'); + tlb_seq_pgsize <= (others => '0'); + if tlb_tag4_hit_or_parerr='1' and or_reduce(tlb_tag0_q(tagpos_type_tlbsx to tagpos_type_tlbsrx))='1' then + tlb_seq_next <= TlbSeq_Stg30; + elsif tlb_tag4_hit_or_parerr='1' and tlb_tag4_way_ind='0' then + tlb_seq_next <= TlbSeq_Stg31; + elsif tlb_tag4_hit_or_parerr='1' and tlb_tag4_way_ind='1' then + tlb_seq_next <= TlbSeq_Stg29; + else + tlb_seq_next <= TlbSeq_Stg30; + end if; + + WHEN TlbSeq_Stg19 => + tlb_seq_pgsize <= tlb_tag0_q(tagpos_size to tagpos_size+3); + tlb_seq_tag0_addr_cap <= '1'; + tlb_seq_addr_update <= '1'; + if tlb_tag0_tid_notzero='1' then + tlb_seq_addr <= tlb_tag0_hashed_addr; + else + tlb_seq_addr <= tlb_tag0_hashed_tid0_addr; + end if; + tlb_seq_next <= TlbSeq_Stg20; + + WHEN TlbSeq_Stg20 => + tlb_seq_addr <= (others => '0'); + tlb_seq_pgsize <= (others => '0'); + tlb_seq_next <= TlbSeq_Stg21; + + WHEN TlbSeq_Stg21 => + tlb_seq_lrat_enable <= tlb_tag0_q(tagpos_type_tlbwe) or tlb_tag0_q(tagpos_type_ptereload); + tlb_seq_addr <= (others => '0'); + tlb_seq_pgsize <= (others => '0'); + tlb_seq_next <= TlbSeq_Stg22; + + WHEN TlbSeq_Stg22 => + tlb_seq_addr <= (others => '0'); + tlb_seq_pgsize <= (others => '0'); + tlb_seq_next <= TlbSeq_Stg23; + + WHEN TlbSeq_Stg23 => + tlb_seq_addr <= (others => '0'); + tlb_seq_pgsize <= (others => '0'); + tlb_seq_read_done_sig <= tlb_tag0_q(tagpos_type_tlbre); + tlb_seq_write_done_sig <= tlb_tag0_q(tagpos_type_tlbwe); + tlb_seq_ptereload_done_sig <= tlb_tag0_q(tagpos_type_ptereload); + if tlb_tag0_q(tagpos_type_tlbre)='1' or tlb_tag0_q(tagpos_type_tlbwe)='1' then + tlb_seq_next <= TlbSeq_Idle; + else + tlb_seq_next <= TlbSeq_Stg31; + end if; + + + WHEN TlbSeq_Stg24 => + tlb_seq_pgsize <= tlb_tag0_q(tagpos_size to tagpos_size+3); + tlb_seq_tag0_addr_cap <= '1'; + tlb_seq_snoop_resv <= '1'; + if (tlb_tag0_q(tagpos_is+1 to tagpos_is+3)="011") then + tlb_seq_addr_update <= '1'; + tlb_seq_addr_clr <= '0'; + tlb_seq_endflag <= '1'; + else + tlb_seq_addr_update <= '0'; + tlb_seq_addr_clr <= '1'; + tlb_seq_endflag <= '0'; + end if; + if tlb_tag0_tid_notzero='1' then + tlb_seq_addr <= tlb_tag0_hashed_addr; + else + tlb_seq_addr <= tlb_tag0_hashed_tid0_addr; + end if; + tlb_seq_next <= TlbSeq_Stg25; + + WHEN TlbSeq_Stg25 => + tlb_seq_addr <= (others => '0'); + tlb_seq_pgsize <= (others => '0'); + if (tlb_tag0_q(tagpos_is+1 to tagpos_is+3)="011") then + tlb_seq_addr_incr <= '0'; + tlb_seq_endflag <= '0'; + else + tlb_seq_addr_incr <= '1'; + tlb_seq_endflag <= tlb_addr_maxcntm1; + end if; + if tlb_tag0_q(tagpos_is+1 to tagpos_is+3)/="011" and tlb_tag1_q(tagpos_endflag)='0' then + tlb_seq_next <= TlbSeq_Stg25; + else + tlb_seq_next <= TlbSeq_Stg26; + end if; + + WHEN TlbSeq_Stg26 => + tlb_seq_addr <= (others => '0'); + tlb_seq_pgsize <= (others => '0'); + tlb_seq_next <= TlbSeq_Stg27; + + WHEN TlbSeq_Stg27 => + tlb_seq_addr <= (others => '0'); + tlb_seq_pgsize <= (others => '0'); + tlb_seq_next <= TlbSeq_Stg28; + + WHEN TlbSeq_Stg28 => + tlb_seq_addr <= (others => '0'); + tlb_seq_pgsize <= (others => '0'); + tlb_seq_next <= TlbSeq_Stg31; + WHEN TlbSeq_Stg29 => + tlb_seq_derat_done_sig <= tlb_tag0_q(tagpos_type_derat) and not tlb_tag0_q(tagpos_type_ptereload); + tlb_seq_ierat_done_sig <= tlb_tag0_q(tagpos_type_ierat) and not tlb_tag0_q(tagpos_type_ptereload); + tlb_seq_addr <= (others => '0'); + tlb_seq_pgsize <= (others => '0'); + tlb_seq_next <= TlbSeq_Idle; + + WHEN TlbSeq_Stg30 => + tlb_seq_addr <= (others => '0'); + tlb_seq_pgsize <= (others => '0'); + tlb_seq_derat_done_sig <= tlb_tag0_q(tagpos_type_derat) and not tlb_tag0_q(tagpos_type_ptereload); + tlb_seq_ierat_done_sig <= tlb_tag0_q(tagpos_type_ierat) and not tlb_tag0_q(tagpos_type_ptereload); + tlb_seq_search_done_sig <= tlb_tag0_q(tagpos_type_tlbsx); + tlb_seq_searchresv_done_sig <= tlb_tag0_q(tagpos_type_tlbsrx); + tlb_seq_snoop_done_sig <= tlb_tag0_q(tagpos_type_snoop); + tlb_seq_set_resv <= tlb_tag0_q(tagpos_type_tlbsrx); + + tlb_seq_next <= TlbSeq_Idle; + + + WHEN TlbSeq_Stg31 => + tlb_seq_addr <= (others => '0'); + tlb_seq_pgsize <= (others => '0'); + tlb_seq_derat_done_sig <= tlb_tag0_q(tagpos_type_derat) and not tlb_tag0_q(tagpos_type_ptereload); + tlb_seq_ierat_done_sig <= tlb_tag0_q(tagpos_type_ierat) and not tlb_tag0_q(tagpos_type_ptereload); + tlb_seq_search_done_sig <= tlb_tag0_q(tagpos_type_tlbsx); + tlb_seq_searchresv_done_sig <= tlb_tag0_q(tagpos_type_tlbsrx); + tlb_seq_snoop_done_sig <= tlb_tag0_q(tagpos_type_snoop); + tlb_seq_set_resv <= tlb_tag0_q(tagpos_type_tlbsrx); + + if (tlb_tag0_q(tagpos_type_ierat)='1' or tlb_tag0_q(tagpos_type_derat)='1' + or tlb_tag0_q(tagpos_type_ptereload)='1') then + tlb_seq_next <= TlbSeq_Stg32; + else + tlb_seq_next <= TlbSeq_Idle; + end if; + + WHEN TlbSeq_Stg32 => + tlb_seq_addr <= (others => '0'); + tlb_seq_pgsize <= (others => '0'); + tlb_seq_next <= TlbSeq_Idle; + + WHEN OTHERS => + tlb_seq_next <= TlbSeq_Idle; + + END CASE; +END PROCESS Tlb_Sequencer; +ierat_req_taken <= ierat_req_taken_sig; +derat_req_taken <= derat_req_taken_sig; +tlb_seq_ierat_done <= tlb_seq_ierat_done_sig; +tlb_seq_derat_done <= tlb_seq_derat_done_sig; +ptereload_req_taken <= ptereload_req_taken_sig; +tlb_seq_idle <= tlb_seq_idle_sig; +-- snoop_val: 0 -> valid, 1 -> ack +snoop_val_d(0) <= tlb_snoop_val when snoop_val_q(0)='0' + else '0' when snoop_req_taken_sig='1' + else snoop_val_q(0); +snoop_val_d(1) <= tlb_seq_snoop_done_sig; +tlb_snoop_ack <= snoop_val_q(1); +-- snoop_attr: +-- 0 -> Local +-- 1:3 -> IS/Class: 0=all, 1=tid, 2=gs, 3=epn, 4=class0, 5=class1, 6=class2, 7=class3 +-- 4:5 -> GS/TS +-- 6:13 -> TID(6:13) +-- 14:17 -> Size +-- 18 -> reserved for tlb, extclass_enable(0) for erats +-- 19 -> mmucsr0.tlb0fi for tlb, or TID_NZ for erats +-- 20:25 -> TID(0:5) +-- 26:33 -> LPID +-- 34 -> IND +snoop_attr_d <= tlb_snoop_attr when snoop_val_q(0)='0' + else snoop_attr_q; +snoop_vpn_d(52-epn_width TO 51) <= tlb_snoop_vpn when snoop_val_q(0)='0' + else snoop_vpn_q(52-epn_width to 51); +ptereload_req_pte_d <= ptereload_req_pte when ptereload_req_taken_sig='1' + else ptereload_req_pte_q; +ptereload_req_pte_lat <= ptereload_req_pte_q; +--tlb_tag0_d <= ( 0:51 epn & +-- 52:65 pid & +-- 66:67 IS & +-- 68:69 Class & +-- 70:73 state (pr,gs,as,cm) & +-- 74:77 thdid & +-- 78:81 size & +-- 82:83 derat_miss/ierat_miss & +-- 84:85 tlbsx/tlbsrx & +-- 86:87 inval_snoop/tlbre & +-- 88:89 tlbwe/ptereload & +-- 90:97 lpid & +-- 98 indirect +-- 99 atsel & +-- 100:102 esel & +-- 103:105 hes/wq(0:1) & +-- 106:107 lrat/pt & +-- 108 record form +-- 109 endflag +-- tagpos_epn : natural := 0; +-- tagpos_pid : natural := 52; -- 14 bits +-- tagpos_is : natural := 66; +-- tagpos_class : natural := 68; +-- tagpos_state : natural := 70; -- state: 0:pr 1:gs 2:as 3:cm +-- tagpos_thdid : natural := 74; +-- tagpos_size : natural := 78; +-- tagpos_type : natural := 82; -- derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload +-- tagpos_lpid : natural := 90; +-- tagpos_ind : natural := 98; +-- tagpos_atsel : natural := 99; +-- tagpos_esel : natural := 100; +-- tagpos_hes : natural := 103; +-- tagpos_wq : natural := 104; +-- tagpos_lrat : natural := 106; +-- tagpos_pt : natural := 107; +-- tagpos_recform : natural := 108; +-- tagpos_endflag : natural := 109; +-- snoop_attr: +-- 0 -> Local +-- 1:3 -> IS/Class: 0=all, 1=tid, 2=gs, 3=epn, 4=class0, 5=class1, 6=class2, 7=class3 +-- 4:5 -> GS/TS +-- 6:13 -> TID(6:13) +-- 14:17 -> Size +-- 18 -> reserved for tlb, extclass_enable(0) for erats +-- 19 -> mmucsr0.tlb0fi for tlb, or TID_NZ for erats +-- 20:25 -> TID(0:5) +-- 26:33 -> LPID +-- 34 -> IND +-- TAG PHASE (q) DESCRPTION OPERATION / EXn +-- -1 prehash arb tlbwe ex1 tlbre ex1 tlbsx ex2 tlbsrx ex2 +-- 0 hash calc tlbwe ex2 tlbre ex2 tlbsx ex3 tlbsrx ex3 +-- 1 tlb/lru cc addr tlbwe ex3 tlbre ex3 tlbsx ex4 tlbsrx ex4 +-- 2 tlb/lru data out tlbwe ex4 tlbre ex4 tlbsx ex5 tlbsrx ex5 +-- 3 comp & select tlbwe ex5 tlbre ex5 tlbsx ex6 tlbsrx ex6 +-- 4 tlb/lru/mas update tlbwe ex6 tlbre ex6 tlbsx ex7 tlbsrx ex7 +-- 5 erat reload +tlb_ctl_tag1_flush_sig <= ex3_flush_q when (tlb_tag0_q(tagpos_type_tlbre)='1' or tlb_tag0_q(tagpos_type_tlbwe)='1') + else ex4_flush_q when (tlb_tag0_q(tagpos_type_tlbsx)='1' or tlb_tag0_q(tagpos_type_tlbsrx)='1') + else (others => '0'); +tlb_ctl_tag2_flush_sig <= ex4_flush_q when (tlb_tag0_q(tagpos_type_tlbre)='1' or tlb_tag0_q(tagpos_type_tlbwe)='1') + else ex5_flush_q when (tlb_tag0_q(tagpos_type_tlbsx)='1' or tlb_tag0_q(tagpos_type_tlbsrx)='1') + else (others => '0'); +tlb_ctl_tag3_flush_sig <= ex5_flush_q when (tlb_tag0_q(tagpos_type_tlbre)='1' or tlb_tag0_q(tagpos_type_tlbwe)='1') + else ex6_flush_q when (tlb_tag0_q(tagpos_type_tlbsx)='1' or tlb_tag0_q(tagpos_type_tlbsrx)='1') + else (others => '0'); +tlb_ctl_tag4_flush_sig <= ex6_flush_q when (tlb_tag0_q(tagpos_type_tlbre)='1' or tlb_tag0_q(tagpos_type_tlbwe)='1') + else (others => '0'); +tlb_ctl_any_tag_flush_sig <= or_reduce(tlb_ctl_tag1_flush_sig or tlb_ctl_tag2_flush_sig or tlb_ctl_tag3_flush_sig or tlb_ctl_tag4_flush_sig); +tlb_ctl_tag2_flush <= tlb_ctl_tag2_flush_sig or tlb_ctl_tag3_flush_sig or tlb_ctl_tag4_flush_sig; +tlb_ctl_tag3_flush <= tlb_ctl_tag3_flush_sig or tlb_ctl_tag4_flush_sig; +tlb_ctl_tag4_flush <= tlb_ctl_tag4_flush_sig; +-- 0 1 2 3 4 5 6 7 +-- tag type bits --> derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload +-- tag -1 phase, tlbwe/re ex1, tlbsx/srx ex2 +tlb_tag0_d(tagpos_type_derat) <= (derat_req_taken_sig) + or (ptereload_req_tag(tagpos_type_derat) and ptereload_req_taken_sig) + or (tlb_tag0_q(tagpos_type_derat) and not tlb_seq_any_done_sig and not tlb_seq_abort); +tlb_tag0_d(tagpos_type_ierat) <= (ierat_req_taken_sig) + or (ptereload_req_tag(tagpos_type_ierat) and ptereload_req_taken_sig) + or (tlb_tag0_q(tagpos_type_ierat) and not tlb_seq_any_done_sig and not tlb_seq_abort); +tlb_tag0_d(tagpos_type_tlbsx) <= (search_req_taken_sig) + or (tlb_tag0_q(tagpos_type_tlbsx) and not tlb_seq_any_done_sig and not tlb_seq_abort); +tlb_tag0_d(tagpos_type_tlbsrx) <= (searchresv_req_taken_sig) + or (tlb_tag0_q(tagpos_type_tlbsrx) and not tlb_seq_any_done_sig and not tlb_seq_abort); +tlb_tag0_d(tagpos_type_snoop) <= (snoop_req_taken_sig) + or (tlb_tag0_q(tagpos_type_snoop) and not tlb_seq_any_done_sig and not tlb_seq_abort); +tlb_tag0_d(tagpos_type_tlbre) <= (read_req_taken_sig) + or (tlb_tag0_q(tagpos_type_tlbre) and not tlb_seq_any_done_sig and not tlb_seq_abort); +tlb_tag0_d(tagpos_type_tlbwe) <= (write_req_taken_sig) + or (tlb_tag0_q(tagpos_type_tlbwe) and not tlb_seq_any_done_sig and not tlb_seq_abort); +tlb_tag0_d(tagpos_type_ptereload) <= (ptereload_req_taken_sig) + or (tlb_tag0_q(tagpos_type_ptereload) and not tlb_seq_any_done_sig and not tlb_seq_abort); +-- state: 0:pr 1:gs 2:as 3:cm +gen64_tag_epn: if rs_data_width = 64 generate +tlb_tag0_d(tagpos_epn TO tagpos_epn+epn_width-1) <= + ( ptereload_req_tag(tagpos_epn to tagpos_epn+epn_width-1) and (tagpos_epn to tagpos_epn+epn_width-1 => ptereload_req_taken_sig) ) + or ( ((ex1_mas2_epn(0 to 31) and (0 to 31 => ex1_state_q(3))) & ex1_mas2_epn(32 to epn_width-1)) and (tagpos_epn to tagpos_epn+epn_width-1 => write_req_taken_sig) ) + or ( ((ex1_mas2_epn(0 to 31) and (0 to 31 => ex1_state_q(3))) & ex1_mas2_epn(32 to epn_width-1)) and (tagpos_epn to tagpos_epn+epn_width-1 => read_req_taken_sig) ) + or ( snoop_vpn_q and (tagpos_epn to tagpos_epn+epn_width-1 => snoop_req_taken_sig) ) + or ( xu_mm_ex2_epn and (tagpos_epn to tagpos_epn+epn_width-1 => searchresv_req_taken_sig) ) + or ( xu_mm_ex2_epn and (tagpos_epn to tagpos_epn+epn_width-1 => search_req_taken_sig) ) + or ( ierat_req_epn and (tagpos_epn to tagpos_epn+epn_width-1 => ierat_req_taken_sig) ) + or ( derat_req_epn and (tagpos_epn to tagpos_epn+epn_width-1 => derat_req_taken_sig) ) + or ( tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-1) and (tagpos_epn to tagpos_epn+epn_width-1 => not any_req_taken_sig) ); +end generate gen64_tag_epn; +gen32_tag_epn: if rs_data_width = 32 generate +tlb_tag0_d(tagpos_epn TO tagpos_epn+epn_width-1) <= + ( ptereload_req_tag(tagpos_epn to tagpos_epn+epn_width-1) and (0 to epn_width-1 => ptereload_req_taken_sig) ) + or ( ex1_mas2_epn(52-epn_width to 51) and (0 to epn_width-1 => write_req_taken_sig) ) + or ( ex1_mas2_epn(52-epn_width to 51) and (0 to epn_width-1 => read_req_taken_sig) ) + or ( snoop_vpn_q(52-epn_width to 51) and (0 to epn_width-1 => snoop_req_taken_sig) ) + or ( xu_mm_ex2_epn(52-epn_width to 51) and (0 to epn_width-1 => searchresv_req_taken_sig) ) + or ( xu_mm_ex2_epn(52-epn_width to 51) and (0 to epn_width-1 => search_req_taken_sig) ) + or ( ierat_req_epn(52-epn_width to 51) and (0 to epn_width-1 => ierat_req_taken_sig) ) + or ( derat_req_epn(52-epn_width to 51) and (0 to epn_width-1 => derat_req_taken_sig) ) + or ( tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-1) and (0 to epn_width-1 => not any_req_taken_sig) ); +end generate gen32_tag_epn; +-- snoop_attr: +-- 0 -> Local +-- 1:3 -> IS/Class: 0=all, 1=tid, 2=gs, 3=epn, 4=class0, 5=class1, 6=class2, 7=class3 +-- 4:5 -> GS/TS +-- 6:13 -> TID(6:13) +-- 14:17 -> Size +-- 18 -> reserved for tlb, extclass_enable(0) for erats +-- 19 -> mmucsr0.tlb0fi for tlb, or TID_NZ for erats +-- 20:25 -> TID(0:5) +-- 26:33 -> LPID +-- 34 -> IND +tlb_tag0_d(tagpos_pid TO tagpos_pid+pid_width-1) <= + ( ptereload_req_tag(tagpos_pid to tagpos_pid+pid_width-1) and (0 to pid_width-1 => ptereload_req_taken_sig) ) + or ( ex1_mas1_tid and (0 to pid_width-1 => write_req_taken_sig) ) + or ( ex1_mas1_tid and (0 to pid_width-1 => read_req_taken_sig) ) + or ( snoop_attr_q(20 to 25) & snoop_attr_q(6 to 13) and (0 to pid_width-1 => snoop_req_taken_sig) ) + or ( ex2_mas1_tid and (0 to pid_width-1 => searchresv_req_taken_sig) ) + or ( ex2_mas6_spid and (0 to pid_width-1 => search_req_taken_sig) ) + or ( ierat_req_pid and (0 to pid_width-1 => ierat_req_taken_sig) ) + or ( derat_req_pid and (0 to pid_width-1 => derat_req_taken_sig) ) + or ( tlb_tag0_q(tagpos_pid to tagpos_pid+pid_width-1) and (0 to pid_width-1 => not any_req_taken_sig) ); +-- snoop_attr: 0 -> Local +-- snoop_attr: 1:3 -> IS/Class: 0=all, 1=tid, 2=gs, 3=vpn, 4=class0, 5=class1, 6=class2, 7=class3 +-- unused tagpos_is def is mas1_v, mas1_iprot for tlbwe, and is (pte.valid & 0) for ptereloads +tlb_tag0_d(tagpos_is TO tagpos_is+1) <= + ((ptereload_req_pte(ptepos_valid) & ptereload_req_tag(tagpos_is+1)) and (0 to 1 => ptereload_req_taken_sig)) + or ((ex1_mas1_v & ex1_mas1_iprot) and (0 to 1 => write_req_taken_sig)) + or (snoop_attr_q(0 to 1) and (0 to 1 => snoop_req_taken_sig)) + or (tlb_tag0_q(tagpos_is to tagpos_is+1) and (0 to 1 => not any_req_taken_sig)); +tlb_tag0_d(tagpos_class TO tagpos_class+1) <= + (ptereload_req_tag(tagpos_class to tagpos_class+1) and (0 to 1 => ptereload_req_taken_sig)) + or (ex1_mmucr3_class and (0 to 1 => write_req_taken_sig)) + or (snoop_attr_q(2 to 3) and (0 to 1 => snoop_req_taken_sig)) + or (derat_req_ttype and (0 to 1 => derat_req_taken_sig)) + or (tlb_tag0_q(tagpos_class to tagpos_class+1) and (0 to 1 => not any_req_taken_sig)); +-- state: 0:pr 1:gs 2:as 3:cm +tlb_tag0_d(tagpos_state TO tagpos_state+state_width-1) <= + (ptereload_req_tag(tagpos_state to tagpos_state+state_width-1) and (0 to state_width-1 => ptereload_req_taken_sig)) + or (ex1_state_q(0 to 3) and (0 to state_width-1 => write_req_taken_sig)) + or (ex1_state_q(0 to 3) and (0 to state_width-1 => read_req_taken_sig)) + or (('0' & snoop_attr_q(4 to 5) & '0') and (0 to state_width-1 => snoop_req_taken_sig)) + or (ex2_mas5_1_state and (0 to state_width-1 => searchresv_req_taken_sig)) + or (ex2_mas5_6_state and (0 to state_width-1 => search_req_taken_sig)) + or (ierat_req_state and (0 to state_width-1 => ierat_req_taken_sig)) + or (derat_req_state and (0 to state_width-1 => derat_req_taken_sig)) + or (tlb_tag0_q(tagpos_state to tagpos_state+state_width-1) and (0 to state_width-1 => not any_req_taken_sig)); +tlb_tag0_d(tagpos_thdid TO tagpos_thdid+thdid_width-1) <= + (ptereload_req_tag(tagpos_thdid to tagpos_thdid+thdid_width-1) and (0 to thdid_width-1 => ptereload_req_taken_sig)) + or (ex1_valid_q and (0 to thdid_width-1 => write_req_taken_sig)) + or (ex1_valid_q and (0 to thdid_width-1 => read_req_taken_sig)) + or ("1111" and (0 to thdid_width-1 => snoop_req_taken_sig)) + or (ex2_valid_q and (0 to thdid_width-1 => searchresv_req_taken_sig)) + or (ex2_valid_q and (0 to thdid_width-1 => search_req_taken_sig)) + or (ierat_req_thdid and (0 to thdid_width-1 => ierat_req_taken_sig)) + or (derat_req_thdid and (0 to thdid_width-1 => derat_req_taken_sig)) + or ( tlb_tag0_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag1_flush_sig) + and not(tlb_ctl_tag2_flush_sig) and not(tlb_ctl_tag3_flush_sig) and not(tlb_ctl_tag4_flush_sig) + and (0 to thdid_width-1 => (not tlb_seq_any_done_sig and not any_req_taken_sig and not tlb_seq_abort)) ); +tlb_tag0_d(tagpos_size TO tagpos_size+3) <= + (('0' & ptereload_req_pte(ptepos_size to ptepos_size+2)) and (0 to 3 => ptereload_req_taken_sig)) + or (ex1_mas1_tsize and (0 to 3 => write_req_taken_sig)) + or (ex1_mas1_tsize and (0 to 3 => read_req_taken_sig)) + or (snoop_attr_q(14 to 17) and (0 to 3 => snoop_req_taken_sig)) + or (mmucr2(28 to 31) and (0 to 3 => searchresv_req_taken_sig)) + or (mmucr2(28 to 31) and (0 to 3 => search_req_taken_sig)) + or (mmucr2(28 to 31) and (0 to 3 => ierat_req_taken_sig)) + or (mmucr2(28 to 31) and (0 to 3 => derat_req_taken_sig)) + or (tlb_tag0_q(tagpos_size to tagpos_size+3) and (0 to 3 => not any_req_taken_sig)); +tlb_tag0_d(tagpos_lpid TO tagpos_lpid+lpid_width-1) <= + (ptereload_req_tag(tagpos_lpid to tagpos_lpid+lpid_width-1) and (0 to lpid_width-1 => ptereload_req_taken_sig)) + or (ex1_mas8_tlpid and (0 to lpid_width-1 => write_req_taken_sig)) + or (ex1_mas8_tlpid and (0 to lpid_width-1 => read_req_taken_sig)) + or (snoop_attr_q(26 to 33) and (0 to lpid_width-1 => snoop_req_taken_sig)) + or (ex2_mas5_slpid and (0 to lpid_width-1 => searchresv_req_taken_sig)) + or (ex2_mas5_slpid and (0 to lpid_width-1 => search_req_taken_sig)) + or (lpidr and (0 to lpid_width-1 => ierat_req_taken_sig)) + or (derat_req_lpid and (0 to lpid_width-1 => derat_req_taken_sig)) + or (tlb_tag0_q(tagpos_lpid to tagpos_lpid+lpid_width-1) and (0 to lpid_width-1 => not any_req_taken_sig)); +tlb_tag0_d(tagpos_ind) <= + (ex1_mas1_ind and write_req_taken_sig) + or (ex1_mas1_ind and read_req_taken_sig) + or (snoop_attr_q(34) and snoop_req_taken_sig) + or (ex2_mas1_ind and searchresv_req_taken_sig) + or (ex2_mas6_sind and search_req_taken_sig) + or (tlb_tag0_q(tagpos_ind) and not any_req_taken_sig); +tlb_tag0_d(tagpos_atsel) <= + (ptereload_req_tag(tagpos_atsel) and ptereload_req_taken_sig) + or (ex1_mas0_atsel and write_req_taken_sig) + or (ex1_mas0_atsel and read_req_taken_sig) + or (ex2_mas0_atsel and searchresv_req_taken_sig) + or (ex2_mas0_atsel and search_req_taken_sig) + or (tlb_tag0_q(tagpos_atsel) and not any_req_taken_sig); +tlb_tag0_d(tagpos_esel TO tagpos_esel+2) <= + (ptereload_req_tag(tagpos_esel to tagpos_esel+2) and (0 to 2 => ptereload_req_taken_sig)) + or (ex1_mas0_esel and (0 to 2 => write_req_taken_sig)) + or (ex1_mas0_esel and (0 to 2 => read_req_taken_sig)) + or (ex2_mas0_esel and (0 to 2 => searchresv_req_taken_sig)) + or (ex2_mas0_esel and (0 to 2 => search_req_taken_sig)) + or (tlb_tag0_q(tagpos_esel to tagpos_esel+2) and (0 to 2 => not any_req_taken_sig)); +tlb_tag0_d(tagpos_hes) <= + (ptereload_req_tag(tagpos_hes) and ptereload_req_taken_sig) + or (ex1_mas0_hes and write_req_taken_sig) + or (ex1_mas0_hes and read_req_taken_sig) + or (snoop_attr_q(19) and snoop_req_taken_sig) + or (ex2_mas0_hes and searchresv_req_taken_sig) + or (ex2_mas0_hes and search_req_taken_sig) + or (ierat_req_taken_sig) + or (derat_req_taken_sig) + or (tlb_tag0_q(tagpos_hes) and not any_req_taken_sig); +tlb_tag0_d(tagpos_wq TO tagpos_wq+1) <= + (ptereload_req_tag(tagpos_wq to tagpos_wq+1) and (0 to 1 => ptereload_req_taken_sig)) + or (ex1_mas0_wq and (0 to 1 => write_req_taken_sig)) + or (ex1_mas0_wq and (0 to 1 => read_req_taken_sig)) + or (ex2_mas0_wq and (0 to 1 => searchresv_req_taken_sig)) + or (ex2_mas0_wq and (0 to 1 => search_req_taken_sig)) + or (ierat_req_dup and (0 to 1 => ierat_req_taken_sig)) + or (derat_req_dup and (0 to 1 => derat_req_taken_sig)) + or (tlb_tag0_q(tagpos_wq to tagpos_wq+1) and (0 to 1 => not any_req_taken_sig)); +tlb_tag0_d(tagpos_lrat) <= + (ptereload_req_tag(tagpos_lrat) and ptereload_req_taken_sig) + or (mmucfg_lrat and write_req_taken_sig) + or (mmucfg_lrat and read_req_taken_sig) + or (mmucfg_lrat and searchresv_req_taken_sig) + or (mmucfg_lrat and search_req_taken_sig) + or (mmucfg_lrat and ierat_req_taken_sig) + or (mmucfg_lrat and derat_req_taken_sig) + or (tlb_tag0_q(tagpos_lrat) and not any_req_taken_sig); +-- unused tagpos_pt def is mas8_tgs for tlbwe +tlb_tag0_d(tagpos_pt) <= + (ptereload_req_tag(tagpos_pt) and ptereload_req_taken_sig) + or (ex1_mas8_tgs and write_req_taken_sig) + or (tlb0cfg_pt and read_req_taken_sig) + or (tlb0cfg_pt and searchresv_req_taken_sig) + or (tlb0cfg_pt and search_req_taken_sig) + or (tlb0cfg_pt and ierat_req_taken_sig) + or (tlb0cfg_pt and derat_req_taken_sig) + or (tlb_tag0_q(tagpos_pt) and not any_req_taken_sig); +-- unused tagpos_recform def is mas1_ts for tlbwe +tlb_tag0_d(tagpos_recform) <= + (ex1_mas1_ts and write_req_taken_sig) + or (searchresv_req_taken_sig) + or (ex2_ttype_q(3) and search_req_taken_sig) + or (tlb_tag0_q(tagpos_recform) and not any_req_taken_sig); +tlb_tag0_d(tagpos_endflag) <= '0'; +-- tagpos_epn : natural := 0; +-- tagpos_pid : natural := 52; -- 14 bits +-- tagpos_is : natural := 66; +-- tagpos_class : natural := 68; +-- tagpos_state : natural := 70; -- state: 0:pr 1:gs 2:as 3:cm +-- tagpos_thdid : natural := 74; +-- tagpos_size : natural := 78; +-- tagpos_type : natural := 82; -- derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload +-- tagpos_lpid : natural := 90; +-- tagpos_ind : natural := 98; +-- tagpos_atsel : natural := 99; +-- tagpos_esel : natural := 100; +-- tagpos_hes : natural := 103; +-- tagpos_wq : natural := 104; +-- tagpos_lrat : natural := 106; +-- tagpos_pt : natural := 107; +-- tagpos_recform : natural := 108; +-- tagpos_endflag : natural := 109; +--ac/q7/vhdl/a2_simwrap_32.vhdl: constant real_addr_width : integer := 32; +--ac/q7/vhdl/a2_simwrap.vhdl: constant real_addr_width : integer := 42; +--ac/q7/vhdl/a2_simwrap_32.vhdl: constant epn_width : integer := 20; +--ac/q7/vhdl/a2_simwrap.vhdl: constant epn_width : integer := 52; +-- tag0 phase, tlbwe/re ex2, tlbsx/srx ex3 +tlb_tag0_epn(52-epn_width TO 51) <= tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-1); +tlb_tag0_thdid <= tlb_tag0_q(tagpos_thdid to tagpos_thdid+thdid_width-1); +tlb_tag0_type <= tlb_tag0_q(tagpos_type to tagpos_type+7); +tlb_tag0_lpid <= tlb_tag0_q(tagpos_lpid to tagpos_lpid+lpid_width-1); +tlb_tag0_atsel <= tlb_tag0_q(tagpos_atsel); +tlb_tag0_size <= tlb_tag0_q(tagpos_size to tagpos_size+3); +tlb_tag0_addr_cap <= tlb_seq_tag0_addr_cap; +tlb_tag1_d(tagpos_epn TO tagpos_epn+epn_width-1) <= tlb_tag0_q(tagpos_epn to tagpos_epn+epn_width-1); +tlb_tag1_d(tagpos_pid TO tagpos_pid+pid_width-1) <= tlb_tag0_q(tagpos_pid to tagpos_pid+pid_width-1); +-- maybe needed for timing here and for ptereload_req_pte(ptepos_size) stuff +-- unused tagpos_is def is (pte.valid & 0) for ptereloads +-- unused isel for derat,ierat,tlbsx,tlbsrx becomes page size attempted number msb (9 thru 13, or 17 thru 21) +tlb_tag1_d(tagpos_is TO tagpos_is+1) <= ((0 to 1 => or_reduce(tlb_tag0_q(tagpos_type_derat to tagpos_type_tlbsrx)) and not tlb_tag0_q(tagpos_type_ptereload)) and tlb_seq_is) or + ((0 to 1 => or_reduce(tlb_tag0_q(tagpos_type_snoop to tagpos_type_ptereload))) and tlb_tag0_q(tagpos_is to tagpos_is+1)); +tlb_tag1_d(tagpos_class TO tagpos_class+1) <= tlb_tag0_q(tagpos_class to tagpos_class+1); +tlb_tag1_d(tagpos_state TO tagpos_state+state_width-1) <= tlb_tag0_q(tagpos_state to tagpos_state+state_width-1); +tlb_tag1_d(tagpos_thdid TO tagpos_thdid+thdid_width-1) <= + (others => '0') when + ( tlb_tag4_hit_or_parerr='1' and tlb_tag0_q(tagpos_type_ptereload)='0' and + (tlb_tag0_q(tagpos_type_ierat)='1' or tlb_tag0_q(tagpos_type_derat)='1' or + tlb_tag0_q(tagpos_type_tlbsx)='1' or tlb_tag0_q(tagpos_type_tlbsrx)='1') ) or + (tlb_tag4_endflag='1' and tlb_tag0_q(tagpos_type_snoop)='1') or + tlb_seq_any_done_sig ='1' or tlb_seq_abort='1' + else tlb_tag0_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag1_flush_sig) and + not(tlb_ctl_tag2_flush_sig) and not(tlb_ctl_tag3_flush_sig) and not(tlb_ctl_tag4_flush_sig); +tlb_tag1_d(tagpos_ind) <= (or_reduce(tlb_tag0_q(tagpos_type_derat to tagpos_type_ierat)) and tlb_seq_ind) or + (not or_reduce(tlb_tag0_q(tagpos_type_derat to tagpos_type_ierat)) and tlb_tag0_q(tagpos_ind)); +-- unused esel for derat,ierat,tlbsx,tlbsrx becomes page size attempted number (1 thru 5) +tlb_tag1_d(tagpos_esel TO tagpos_esel+2) <= ((0 to 2 => or_reduce(tlb_tag0_q(tagpos_type_derat to tagpos_type_tlbsrx)) and not tlb_tag0_q(tagpos_type_ptereload)) and tlb_seq_esel) or + ((0 to 2 => tlb_tag0_q(tagpos_type_ptereload) or not or_reduce(tlb_tag0_q(tagpos_type_derat to tagpos_type_tlbsrx))) and tlb_tag0_q(tagpos_esel to tagpos_esel+2)); +tlb_tag1_d(tagpos_lpid TO tagpos_lpid+lpid_width-1) <= tlb_tag0_q(tagpos_lpid to tagpos_lpid+lpid_width-1); +tlb_tag1_d(tagpos_atsel) <= tlb_tag0_q(tagpos_atsel); +tlb_tag1_d(tagpos_hes) <= tlb_tag0_q(tagpos_hes); +tlb_tag1_d(tagpos_wq TO tagpos_wq+1) <= tlb_tag0_q(tagpos_wq to tagpos_wq+1); +tlb_tag1_d(tagpos_lrat) <= tlb_tag0_q(tagpos_lrat); +tlb_tag1_d(tagpos_pt) <= tlb_tag0_q(tagpos_pt); +tlb_tag1_d(tagpos_recform) <= tlb_tag0_q(tagpos_recform); +-- pgsize bits +tlb_tag1_d(tagpos_size TO tagpos_size+3) <= ((0 to 3 => or_reduce(tlb_tag0_q(tagpos_type_derat to tagpos_type_tlbsrx)) and not tlb_tag0_q(tagpos_type_ptereload)) and tlb_seq_pgsize) or + ((0 to 3 => tlb_tag0_q(tagpos_type_ptereload) or not or_reduce(tlb_tag0_q(tagpos_type_derat to tagpos_type_tlbsrx))) and tlb_tag0_q(tagpos_size to tagpos_size+3)); +-- tag type bits: derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload +tlb_tag1_d(tagpos_type TO tagpos_type+7) <= + "00000000" when (tlb_seq_ierat_done_sig='1' or tlb_seq_derat_done_sig='1' or tlb_seq_snoop_done_sig='1' or tlb_seq_search_done_sig='1' + or tlb_seq_searchresv_done_sig ='1' or tlb_seq_read_done_sig ='1' or tlb_seq_write_done_sig ='1' or tlb_seq_ptereload_done_sig ='1' + or tlb_seq_abort='1') + else tlb_tag0_q(tagpos_type to tagpos_type+7); +-- endflag +tlb_tag1_d(tagpos_endflag) <= tlb_seq_endflag; +tlb_addr_d <= (others => '0') when tlb_seq_addr_clr='1' + else tlb_addr_p1 when tlb_seq_addr_incr='1' + else tlb_seq_addr when tlb_seq_addr_update='1' + else tlb_addr_q; +tlb_addr_p1 <= "0000000" when tlb_addr_q="1111111" + else tlb_addr_q+1; +tlb_addr_maxcntm1 <= '1' when tlb_addr_q="1111110" else '0'; +-- tag1 phase, tlbwe/re ex3, tlbsx/srx ex4 +tlb_tag1_pgsize_eq_16mb <= Eq(tlb_tag1_q(tagpos_size to tagpos_size+3),TLB_PgSize_16MB); +tlb_tag1_pgsize_gte_1mb <= Eq(tlb_tag1_q(tagpos_size to tagpos_size+3),TLB_PgSize_1MB) or + Eq(tlb_tag1_q(tagpos_size to tagpos_size+3),TLB_PgSize_16MB); +tlb_tag1_pgsize_gte_64kb <= Eq(tlb_tag1_q(tagpos_size to tagpos_size+3),TLB_PgSize_1MB) or + Eq(tlb_tag1_q(tagpos_size to tagpos_size+3),TLB_PgSize_16MB) or + Eq(tlb_tag1_q(tagpos_size to tagpos_size+3),TLB_PgSize_64KB); +tlb_tag2_d(tagpos_epn TO tagpos_epn+39) <= tlb_tag1_q(tagpos_epn to tagpos_epn+39); +tlb_tag2_d(tagpos_epn+40 TO tagpos_epn+43) <= tlb_tag1_q(tagpos_epn+40 to tagpos_epn+43) and (40 to 43 => (not tlb_tag1_pgsize_eq_16mb or not tlb_tag1_q(tagpos_type_ptereload))); +tlb_tag2_d(tagpos_epn+44 TO tagpos_epn+47) <= tlb_tag1_q(tagpos_epn+44 to tagpos_epn+47) and (44 to 47 => (not tlb_tag1_pgsize_gte_1mb or not tlb_tag1_q(tagpos_type_ptereload))); +tlb_tag2_d(tagpos_epn+48 TO tagpos_epn+51) <= tlb_tag1_q(tagpos_epn+48 to tagpos_epn+51) and (48 to 51 => (not tlb_tag1_pgsize_gte_64kb or not tlb_tag1_q(tagpos_type_ptereload))); +tlb_tag2_d(tagpos_pid TO tagpos_pid+pid_width-1) <= tlb_tag1_q(tagpos_pid to tagpos_pid+pid_width-1); +tlb_tag2_d(tagpos_is TO tagpos_is+1) <= tlb_tag1_q(tagpos_is to tagpos_is+1); +tlb_tag2_d(tagpos_class TO tagpos_class+1) <= tlb_tag1_q(tagpos_class to tagpos_class+1); +tlb_tag2_d(tagpos_state TO tagpos_state+state_width-1) <= tlb_tag1_q(tagpos_state to tagpos_state+state_width-1); +tlb_tag2_d(tagpos_thdid TO tagpos_thdid+thdid_width-1) <= (others => '0') when + ( tlb_tag4_hit_or_parerr='1' and tlb_tag2_q(tagpos_type_ptereload)='0' and + (tlb_tag2_q(tagpos_type_ierat)='1' or tlb_tag2_q(tagpos_type_derat)='1' or + tlb_tag2_q(tagpos_type_tlbsx)='1' or tlb_tag2_q(tagpos_type_tlbsrx)='1') ) or + (tlb_tag4_endflag='1' and tlb_tag0_q(tagpos_type_snoop)='1') or + tlb_seq_any_done_sig ='1' or tlb_seq_abort='1' + else tlb_tag1_q(tagpos_thdid to tagpos_thdid+thdid_width-1) and + not(tlb_ctl_tag2_flush_sig) and not(tlb_ctl_tag3_flush_sig) and not(tlb_ctl_tag4_flush_sig); +tlb_tag2_d(tagpos_size TO tagpos_size+3) <= tlb_tag1_q(tagpos_size to tagpos_size+3); +tlb_tag2_d(tagpos_type TO tagpos_type+7) <= + "00000000" when (tlb_seq_ierat_done_sig='1' or tlb_seq_derat_done_sig='1' or tlb_seq_snoop_done_sig='1' or tlb_seq_search_done_sig='1' + or tlb_seq_searchresv_done_sig ='1' or tlb_seq_read_done_sig ='1' or tlb_seq_write_done_sig ='1' or tlb_seq_ptereload_done_sig ='1' + or tlb_seq_abort='1') + else tlb_tag1_q(tagpos_type to tagpos_type+7); +tlb_tag2_d(tagpos_lpid TO tagpos_lpid+lpid_width-1) <= tlb_tag1_q(tagpos_lpid to tagpos_lpid+lpid_width-1); +tlb_tag2_d(tagpos_ind) <= tlb_tag1_q(tagpos_ind); +tlb_tag2_d(tagpos_atsel) <= tlb_tag1_q(tagpos_atsel); +tlb_tag2_d(tagpos_esel TO tagpos_esel+2) <= tlb_tag1_q(tagpos_esel to tagpos_esel+2); +tlb_tag2_d(tagpos_hes) <= tlb_tag1_q(tagpos_hes); +tlb_tag2_d(tagpos_wq TO tagpos_wq+1) <= tlb_tag1_q(tagpos_wq to tagpos_wq+1); +tlb_tag2_d(tagpos_lrat) <= tlb_tag1_q(tagpos_lrat); +tlb_tag2_d(tagpos_pt) <= tlb_tag1_q(tagpos_pt); +tlb_tag2_d(tagpos_recform) <= tlb_tag1_q(tagpos_recform); +tlb_tag2_d(tagpos_endflag) <= tlb_tag1_q(tagpos_endflag); +lru_rd_addr <= tlb_addr_q; +tlb_addr <= tlb_addr_q; +tlb_addr2_d <= tlb_addr_q; +-- tag2 phase, tlbwe/re ex4, tlbsx/srx ex5 +tlb_tag2 <= tlb_tag2_q; +tlb_addr2 <= tlb_addr2_q; +-- tag4, tlbwe/re ex6 +tlb_write_d <= "1000" when ( ex6_valid_q/="0000" and ex6_ttype_q(1)='1' and ex6_state_q(0)='0' and ex6_illeg_instr_q(1)='0' + and ( (ex6_state_q(1)='0' and tlb_tag4_atsel='0') or + (ex6_state_q(1)='1' and lrat_tag4_hit_status(0 to 3)="1100" and + (lru_tag4_dataout(0)='0' or lru_tag4_dataout(8)='0') and + tlb_tag4_is(1)='0' and tlb0cfg_gtwe='1' and ex6_dgtmi_state='0')) + and ((or_reduce(ex6_valid_q and tlb_resv_match_vec_q)='1' and tlb_tag4_wq="01" and mmucfg_twc='1') or tlb_tag4_wq="00" or tlb_tag4_wq="11") + and tlb_tag4_hes='1' and lru_tag4_dataout(4 to 5)="00" ) + else "0100" when ( ex6_valid_q/="0000" and ex6_ttype_q(1)='1' and ex6_state_q(0)='0' and ex6_illeg_instr_q(1)='0' + and ((ex6_state_q(1)='0' and tlb_tag4_atsel='0') or + (ex6_state_q(1)='1' and lrat_tag4_hit_status(0 to 3)="1100" and + (lru_tag4_dataout(1)='0' or lru_tag4_dataout(9)='0') and + tlb_tag4_is(1)='0' and tlb0cfg_gtwe='1' and ex6_dgtmi_state='0')) + and ((or_reduce(ex6_valid_q and tlb_resv_match_vec_q)='1' and tlb_tag4_wq="01" and mmucfg_twc='1') or tlb_tag4_wq="00" or tlb_tag4_wq="11") + and tlb_tag4_hes='1' and lru_tag4_dataout(4 to 5)="01" ) + else "0010" when ( ex6_valid_q/="0000" and ex6_ttype_q(1)='1' and ex6_state_q(0)='0' and ex6_illeg_instr_q(1)='0' + and ((ex6_state_q(1)='0' and tlb_tag4_atsel='0') or + (ex6_state_q(1)='1' and lrat_tag4_hit_status(0 to 3)="1100" and + (lru_tag4_dataout(2)='0' or lru_tag4_dataout(10)='0') and + tlb_tag4_is(1)='0' and tlb0cfg_gtwe='1' and ex6_dgtmi_state='0')) + and ((or_reduce(ex6_valid_q and tlb_resv_match_vec_q)='1' and tlb_tag4_wq="01" and mmucfg_twc='1') or tlb_tag4_wq="00" or tlb_tag4_wq="11") + and tlb_tag4_hes='1' and lru_tag4_dataout(4)='1' and lru_tag4_dataout(6)='0' ) + else "0001" when ( ex6_valid_q/="0000" and ex6_ttype_q(1)='1' and ex6_state_q(0)='0' and ex6_illeg_instr_q(1)='0' + and ((ex6_state_q(1)='0' and tlb_tag4_atsel='0') or + (ex6_state_q(1)='1' and lrat_tag4_hit_status(0 to 3)="1100" and + (lru_tag4_dataout(3)='0' or lru_tag4_dataout(11)='0') and + tlb_tag4_is(1)='0' and tlb0cfg_gtwe='1' and ex6_dgtmi_state='0')) + and ((or_reduce(ex6_valid_q and tlb_resv_match_vec_q)='1' and tlb_tag4_wq="01" and mmucfg_twc='1') or tlb_tag4_wq="00" or tlb_tag4_wq="11") + and tlb_tag4_hes='1' and lru_tag4_dataout(4)='1' and lru_tag4_dataout(6)='1' ) + else "1000" when ( ex6_valid_q/="0000" and ex6_ttype_q(1)='1' and ex6_state_q(0)='0' and ex6_illeg_instr_q(1)='0' + and ex6_state_q(1)='0' and tlb_tag4_atsel='0' + and ((or_reduce(ex6_valid_q and tlb_resv_match_vec_q)='1' and tlb_tag4_wq="01" and mmucfg_twc='1') or tlb_tag4_wq="00" or tlb_tag4_wq="11") + and tlb_tag4_hes='0' and tlb_tag4_esel(1 to 2)="00" ) + else "0100" when ( ex6_valid_q/="0000" and ex6_ttype_q(1)='1' and ex6_state_q(0)='0' and ex6_illeg_instr_q(1)='0' + and ex6_state_q(1)='0' and tlb_tag4_atsel='0' + and ((or_reduce(ex6_valid_q and tlb_resv_match_vec_q)='1' and tlb_tag4_wq="01" and mmucfg_twc='1') or tlb_tag4_wq="00" or tlb_tag4_wq="11") + and tlb_tag4_hes='0' and tlb_tag4_esel(1 to 2)="01") + else "0010" when ( ex6_valid_q/="0000" and ex6_ttype_q(1)='1' and ex6_state_q(0)='0' and ex6_illeg_instr_q(1)='0' + and ex6_state_q(1)='0' and tlb_tag4_atsel='0' + and ((or_reduce(ex6_valid_q and tlb_resv_match_vec_q)='1' and tlb_tag4_wq="01" and mmucfg_twc='1') or tlb_tag4_wq="00" or tlb_tag4_wq="11") + and tlb_tag4_hes='0' and tlb_tag4_esel(1 to 2)="10") + else "0001" when ( ex6_valid_q/="0000" and ex6_ttype_q(1)='1' and ex6_state_q(0)='0' and ex6_illeg_instr_q(1)='0' + and ex6_state_q(1)='0' and tlb_tag4_atsel='0' + and ((or_reduce(ex6_valid_q and tlb_resv_match_vec_q)='1' and tlb_tag4_wq="01" and mmucfg_twc='1') or tlb_tag4_wq="00" or tlb_tag4_wq="11") + and tlb_tag4_hes='0' and tlb_tag4_esel(1 to 2)="11") + else "1000" when ( tlb_tag4_ptereload='1' + and (tlb_tag4_gs='0' or (tlb_tag4_gs='1' and lrat_tag4_hit_status(0 to 3)="1100")) + and lru_tag4_dataout(4 to 5)="00" + and (lru_tag4_dataout(0)='0' or lru_tag4_dataout(8)='0') + and tlb_tag4_wq="10" and tlb_tag4_is(0)='1' and tlb_tag4_pt='1') + else "0100" when ( tlb_tag4_ptereload='1' + and (tlb_tag4_gs='0' or (tlb_tag4_gs='1' and lrat_tag4_hit_status(0 to 3)="1100")) + and lru_tag4_dataout(4 to 5)="01" + and (lru_tag4_dataout(1)='0' or lru_tag4_dataout(9)='0') + and tlb_tag4_wq="10" and tlb_tag4_is(0)='1' and tlb_tag4_pt='1') + else "0010" when ( tlb_tag4_ptereload='1' + and (tlb_tag4_gs='0' or (tlb_tag4_gs='1' and lrat_tag4_hit_status(0 to 3)="1100")) + and lru_tag4_dataout(4)='1' and lru_tag4_dataout(6)='0' + and (lru_tag4_dataout(2)='0' or lru_tag4_dataout(10)='0') + and tlb_tag4_wq="10" and tlb_tag4_is(0)='1' and tlb_tag4_pt='1') + else "0001" when ( tlb_tag4_ptereload='1' + and (tlb_tag4_gs='0' or (tlb_tag4_gs='1' and lrat_tag4_hit_status(0 to 3)="1100")) + and lru_tag4_dataout(4)='1' and lru_tag4_dataout(6)='1' + and (lru_tag4_dataout(3)='0' or lru_tag4_dataout(11)='0') + and tlb_tag4_wq="10" and tlb_tag4_is(0)='1' and tlb_tag4_pt='1') + else "0000"; +-- tag5 (ex7) phase signals +tlb_write <= tlb_write_q and (0 to tlb_ways-1 => not or_reduce(tlb_tag5_except)); +tlb_tag5_write <= or_reduce(tlb_write_q) and not or_reduce(tlb_tag5_except); +----------- this is what the erat expects on reload bus +-- 0:51 - EPN +-- 52 - X +-- 53:55 - SIZE +-- 56 - V +-- 57:60 - ThdID +-- 61:62 - Class +-- 63 - ExtClass +-- 64 - TID_NZ +-- 65 - reserved +-- 0:33 66:99 - RPN +-- 34:35 100:101 - R,C +-- 36:40 102:106 - ResvAttr +-- 41:44 107:110 - U0-U3 +-- 45:49 111:115 - WIMGE +-- 50:52 116:118 - UX,UW,UR +-- 53:55 119:121 - SX,SW,SR +-- 56 122 - HS +-- 57 123 - TS +-- 58:65 124:131 - TID +----------- +-- tlb_low_data +-- 0:51 - EPN +-- 52:55 - SIZE (4b) +-- 56:59 - ThdID +-- 60:61 - Class +-- 62 - ExtClass +-- 63 - TID_NZ +-- 64:65 - reserved (2b) +-- 66:73 - 8b for LPID +-- 74:83 - parity 10bits +-- tlb_high_data +-- 84 - 0 - X-bit +-- 85:87 - 1:3 - reserved (3b) +-- 88:117 - 4:33 - RPN (30b) +-- 118:119 - 34:35 - R,C +-- 120:121 - 36:37 - WLC (2b) +-- 122 - 38 - ResvAttr +-- 123 - 39 - VF +-- 124 - 40 - IND +-- 125:128 - 41:44 - U0-U3 +-- 129:133 - 45:49 - WIMGE +-- 134:136 - 50:52 - UX,UW,UR +-- 137:139 - 53:55 - SX,SW,SR +-- 140 - 56 - GS +-- 141 - 57 - TS +-- 142:143 - 58:59 - reserved (2b) +-- 144:149 - 60:65 - 6b TID msbs +-- 150:157 - 66:73 - 8b TID lsbs +-- 158:167 - 74:83 - parity 10bits +-- lru data format +-- 0:3 - valid(0:3) +-- 4:6 - LRU +-- 7 - parity +-- 8:11 - iprot(0:3) +-- 12:14 - reserved +-- 15 - parity +-- wr_ws0_data (LO) +-- 0:51 - EPN +-- 52:53 - Class +-- 54 - V +-- 55 - unused +-- 56 - X +-- 57:59 - SIZE +-- 60:63 - ThdID +-- wr_ws1_data (HI) +-- 0:6 - unused +-- 7:11 - ResvAttr +-- 12:15 - U0-U3 +-- 16:17 - R,C +-- 18:51 - RPN +-- 52:56 - WIMGE +-- 57 - unused +-- 58:59 - UX,SX +-- 60:61 - UW,SW +-- 62:63 - UR,SR +ex3_valid_32b <= or_reduce(ex3_valid_q and not(xu_mm_msr_cm)); +tlb_ctl_ex2_flush_req <= (ex2_valid_q and not(xu_ex2_flush)) + when (ex2_ttype_q(2 to 4)/="000" + and search_req_taken_sig='0' and searchresv_req_taken_sig='0') + else (ex2_valid_q and not(xu_ex2_flush)) when (ex2_flush_req_q/="0000") + else "0000"; +-- illegal instruction terms +-- state: 0:pr 1:gs 2:as 3:cm +mas1_tsize_direct(0) <= ( Eq(mas1_0_tsize,TLB_PgSize_4KB) or Eq(mas1_0_tsize,TLB_PgSize_64KB) or + Eq(mas1_0_tsize,TLB_PgSize_1MB) or Eq(mas1_0_tsize,TLB_PgSize_16MB) or + Eq(mas1_0_tsize,TLB_PgSize_1GB) ); +mas1_tsize_indirect(0) <= ( Eq(mas1_0_tsize,TLB_PgSize_1MB) or Eq(mas1_0_tsize,TLB_PgSize_256MB) ); +mas1_tsize_lrat(0) <= ( Eq(mas1_0_tsize,LRAT_PgSize_1MB) or Eq(mas1_0_tsize,LRAT_PgSize_16MB) or + Eq(mas1_0_tsize,LRAT_PgSize_256MB) or Eq(mas1_0_tsize,LRAT_PgSize_1GB) or + Eq(mas1_0_tsize,LRAT_PgSize_4GB) or Eq(mas1_0_tsize,LRAT_PgSize_16GB) or + Eq(mas1_0_tsize,LRAT_PgSize_256GB) or Eq(mas1_0_tsize,LRAT_PgSize_1TB) ); +ex2_tlbre_mas1_tsize_not_supp(0) <= '1' when ( mas1_tsize_direct(0)='0' and (mas1_0_ind='0' or tlb0cfg_ind='0') and (mas0_0_atsel='0' or ex2_state_q(1)='1') ) or + ( mas1_tsize_indirect(0)='0' and mas1_0_ind='1' and tlb0cfg_ind='1' and (mas0_0_atsel='0' or ex2_state_q(1)='1') ) + else '0'; +ex5_tlbre_mas1_tsize_not_supp(0) <= '1' when ( mas1_tsize_direct(0)='0' and (mas1_0_ind='0' or tlb0cfg_ind='0') and (mas0_0_atsel='0' or ex5_state_q(1)='1') ) or + ( mas1_tsize_indirect(0)='0' and mas1_0_ind='1' and tlb0cfg_ind='1' and (mas0_0_atsel='0' or ex5_state_q(1)='1') ) + else '0'; +ex5_tlbwe_mas1_tsize_not_supp(0) <= '1' when ( mas1_tsize_direct(0)='0' and (mas1_0_ind='0' or tlb0cfg_ind='0') and mas0_0_wq/="10" and (mas0_0_atsel='0' or ex5_state_q(1)='1') ) or + ( mas1_tsize_indirect(0)='0' and mas1_0_ind='1' and tlb0cfg_ind='1' and mas0_0_wq/="10" and (mas0_0_atsel='0' or ex5_state_q(1)='1') ) or + ( mas1_tsize_lrat(0)='0' and mas0_0_atsel='1' and (mas0_0_wq="00" or mas0_0_wq="11") and ex5_state_q(1)='0' ) + else '0'; +ex6_tlbwe_mas1_tsize_not_supp(0) <= '1' when ( mas1_tsize_direct(0)='0' and (mas1_0_ind='0' or tlb0cfg_ind='0') and mas0_0_wq/="10" and (mas0_0_atsel='0' or ex6_state_q(1)='1') ) or + ( mas1_tsize_indirect(0)='0' and mas1_0_ind='1' and tlb0cfg_ind='1' and mas0_0_wq/="10" and (mas0_0_atsel='0' or ex6_state_q(1)='1') ) or + ( mas1_tsize_lrat(0)='0' and mas0_0_atsel='1' and (mas0_0_wq="00" or mas0_0_wq="11") and ex6_state_q(1)='0' ) + else '0'; +ex5_tlbwe_mas0_lrat_bad_selects(0) <= '1' when ( (mas0_0_hes='1' or mas0_0_wq="01" or mas0_0_wq="10") and mas0_0_atsel='1' and ex5_state_q(1)='0' ) + else '0'; +ex6_tlbwe_mas0_lrat_bad_selects(0) <= '1' when ( (mas0_0_hes='1' or mas0_0_wq="01" or mas0_0_wq="10") and mas0_0_atsel='1' and ex6_state_q(1)='0' ) + else '0'; +ex5_tlbwe_mas2_ind_bad_wimge(0) <= '1' when ( mas1_0_ind='1' and tlb0cfg_ind='1' and mas0_0_wq/="10" and + (mas2_0_wimge(1)='1' or mas2_0_wimge(2)='0' or mas2_0_wimge(3)='1' or mas2_0_wimge(4)='1') and + (mas0_0_atsel='0' or ex5_state_q(1)='1') ) + else '0'; +ex6_tlbwe_mas2_ind_bad_wimge(0) <= '1' when ( mas1_0_ind='1' and tlb0cfg_ind='1' and mas0_0_wq/="10" and + (mas2_0_wimge(1)='1' or mas2_0_wimge(2)='0' or mas2_0_wimge(3)='1' or mas2_0_wimge(4)='1') and + (mas0_0_atsel='0' or ex6_state_q(1)='1') ) + else '0'; +-- Added for illegal indirect page size and sub-page size combinations +mas3_spsize_indirect(0) <= '1' when ((mas1_0_tsize=TLB_PgSize_1MB and mas3_0_usxwr(0 to 3)=TLB_PgSize_4KB) or + (mas1_0_tsize=TLB_PgSize_256MB and mas3_0_usxwr(0 to 3)=TLB_PgSize_64KB)) + else '0'; +ex5_tlbwe_mas3_ind_bad_spsize(0) <= '1' when ( mas1_0_ind='1' and tlb0cfg_ind='1' and mas0_0_wq/="10" and mas3_spsize_indirect(0)='0' and (mas0_0_atsel='0' or ex5_state_q(1)='1') ) + else '0'; +ex6_tlbwe_mas3_ind_bad_spsize(0) <= '1' when ( mas1_0_ind='1' and tlb0cfg_ind='1' and mas0_0_wq/="10" and mas3_spsize_indirect(0)='0' and (mas0_0_atsel='0' or ex6_state_q(1)='1') ) + else '0'; +mas1_tsize_direct(1) <= ( Eq(mas1_1_tsize,TLB_PgSize_4KB) or Eq(mas1_1_tsize,TLB_PgSize_64KB) or + Eq(mas1_1_tsize,TLB_PgSize_1MB) or Eq(mas1_1_tsize,TLB_PgSize_16MB) or + Eq(mas1_1_tsize,TLB_PgSize_1GB) ); +mas1_tsize_indirect(1) <= ( Eq(mas1_1_tsize,TLB_PgSize_1MB) or Eq(mas1_1_tsize,TLB_PgSize_256MB) ); +mas1_tsize_lrat(1) <= ( Eq(mas1_1_tsize,LRAT_PgSize_1MB) or Eq(mas1_1_tsize,LRAT_PgSize_16MB) or + Eq(mas1_1_tsize,LRAT_PgSize_256MB) or Eq(mas1_1_tsize,LRAT_PgSize_1GB) or + Eq(mas1_1_tsize,LRAT_PgSize_4GB) or Eq(mas1_1_tsize,LRAT_PgSize_16GB) or + Eq(mas1_1_tsize,LRAT_PgSize_256GB) or Eq(mas1_1_tsize,LRAT_PgSize_1TB) ); +ex2_tlbre_mas1_tsize_not_supp(1) <= '1' when ( mas1_tsize_direct(1)='0' and (mas1_1_ind='0' or tlb0cfg_ind='0') and (mas0_1_atsel='0' or ex2_state_q(1)='1') ) or + ( mas1_tsize_indirect(1)='0' and mas1_1_ind='1' and tlb0cfg_ind='1' and (mas0_1_atsel='0' or ex2_state_q(1)='1') ) + else '0'; +ex5_tlbre_mas1_tsize_not_supp(1) <= '1' when ( mas1_tsize_direct(1)='0' and (mas1_1_ind='0' or tlb0cfg_ind='0') and (mas0_1_atsel='0' or ex5_state_q(1)='1') ) or + ( mas1_tsize_indirect(1)='0' and mas1_1_ind='1' and tlb0cfg_ind='1' and (mas0_1_atsel='0' or ex5_state_q(1)='1') ) + else '0'; +ex5_tlbwe_mas1_tsize_not_supp(1) <= '1' when ( mas1_tsize_direct(1)='0' and (mas1_1_ind='0' or tlb0cfg_ind='0') and mas0_1_wq/="10" and (mas0_1_atsel='0' or ex5_state_q(1)='1') ) or + ( mas1_tsize_indirect(1)='0' and mas1_1_ind='1' and tlb0cfg_ind='1' and mas0_1_wq/="10" and (mas0_1_atsel='0' or ex5_state_q(1)='1') ) or + ( mas1_tsize_lrat(1)='0' and mas0_1_atsel='1' and (mas0_1_wq="00" or mas0_1_wq="11") and ex5_state_q(1)='0' ) + else '0'; +ex6_tlbwe_mas1_tsize_not_supp(1) <= '1' when ( mas1_tsize_direct(1)='0' and (mas1_1_ind='0' or tlb0cfg_ind='0') and mas0_1_wq/="10" and (mas0_1_atsel='0' or ex6_state_q(1)='1') ) or + ( mas1_tsize_indirect(1)='0' and mas1_1_ind='1' and tlb0cfg_ind='1' and mas0_1_wq/="10" and (mas0_1_atsel='0' or ex6_state_q(1)='1') ) or + ( mas1_tsize_lrat(1)='0' and mas0_1_atsel='1' and (mas0_1_wq="00" or mas0_1_wq="11") and ex6_state_q(1)='0' ) + else '0'; +ex5_tlbwe_mas0_lrat_bad_selects(1) <= '1' when ( (mas0_1_hes='1' or mas0_1_wq="01" or mas0_1_wq="10") and mas0_1_atsel='1' and ex5_state_q(1)='0' ) + else '0'; +ex6_tlbwe_mas0_lrat_bad_selects(1) <= '1' when ( (mas0_1_hes='1' or mas0_1_wq="01" or mas0_1_wq="10") and mas0_1_atsel='1' and ex6_state_q(1)='0' ) + else '0'; +ex5_tlbwe_mas2_ind_bad_wimge(1) <= '1' when ( mas1_1_ind='1' and tlb0cfg_ind='1' and mas0_1_wq/="10" and + (mas2_1_wimge(1)='1' or mas2_1_wimge(2)='0' or mas2_1_wimge(3)='1' or mas2_1_wimge(4)='1') and + (mas0_1_atsel='0' or ex5_state_q(1)='1') ) + else '0'; +ex6_tlbwe_mas2_ind_bad_wimge(1) <= '1' when ( mas1_1_ind='1' and tlb0cfg_ind='1' and mas0_1_wq/="10" and + (mas2_1_wimge(1)='1' or mas2_1_wimge(2)='0' or mas2_1_wimge(3)='1' or mas2_1_wimge(4)='1') and + (mas0_1_atsel='0' or ex6_state_q(1)='1') ) + else '0'; +-- Added for illegal indirect page size and sub-page size combinations +mas3_spsize_indirect(1) <= '1' when ((mas1_1_tsize=TLB_PgSize_1MB and mas3_1_usxwr(0 to 3)=TLB_PgSize_4KB) or + (mas1_1_tsize=TLB_PgSize_256MB and mas3_1_usxwr(0 to 3)=TLB_PgSize_64KB)) + else '0'; +ex5_tlbwe_mas3_ind_bad_spsize(1) <= '1' when ( mas1_1_ind='1' and tlb0cfg_ind='1' and mas0_1_wq/="10" and mas3_spsize_indirect(1)='0' and (mas0_1_atsel='0' or ex5_state_q(1)='1') ) + else '0'; +ex6_tlbwe_mas3_ind_bad_spsize(1) <= '1' when ( mas1_1_ind='1' and tlb0cfg_ind='1' and mas0_1_wq/="10" and mas3_spsize_indirect(1)='0' and (mas0_1_atsel='0' or ex6_state_q(1)='1') ) + else '0'; +mas1_tsize_direct(2) <= ( Eq(mas1_2_tsize,TLB_PgSize_4KB) or Eq(mas1_2_tsize,TLB_PgSize_64KB) or + Eq(mas1_2_tsize,TLB_PgSize_1MB) or Eq(mas1_2_tsize,TLB_PgSize_16MB) or + Eq(mas1_2_tsize,TLB_PgSize_1GB) ); +mas1_tsize_indirect(2) <= ( Eq(mas1_2_tsize,TLB_PgSize_1MB) or Eq(mas1_2_tsize,TLB_PgSize_256MB) ); +mas1_tsize_lrat(2) <= ( Eq(mas1_2_tsize,LRAT_PgSize_1MB) or Eq(mas1_2_tsize,LRAT_PgSize_16MB) or + Eq(mas1_2_tsize,LRAT_PgSize_256MB) or Eq(mas1_2_tsize,LRAT_PgSize_1GB) or + Eq(mas1_2_tsize,LRAT_PgSize_4GB) or Eq(mas1_2_tsize,LRAT_PgSize_16GB) or + Eq(mas1_2_tsize,LRAT_PgSize_256GB) or Eq(mas1_2_tsize,LRAT_PgSize_1TB) ); +ex2_tlbre_mas1_tsize_not_supp(2) <= '1' when ( mas1_tsize_direct(2)='0' and (mas1_2_ind='0' or tlb0cfg_ind='0') and (mas0_2_atsel='0' or ex2_state_q(1)='1') ) or + ( mas1_tsize_indirect(2)='0' and mas1_2_ind='1' and tlb0cfg_ind='1' and (mas0_2_atsel='0' or ex2_state_q(1)='1') ) + else '0'; +ex5_tlbre_mas1_tsize_not_supp(2) <= '1' when ( mas1_tsize_direct(2)='0' and (mas1_2_ind='0' or tlb0cfg_ind='0') and (mas0_2_atsel='0' or ex5_state_q(1)='1') ) or + ( mas1_tsize_indirect(2)='0' and mas1_2_ind='1' and tlb0cfg_ind='1' and (mas0_2_atsel='0' or ex5_state_q(1)='1') ) + else '0'; +ex5_tlbwe_mas1_tsize_not_supp(2) <= '1' when ( mas1_tsize_direct(2)='0' and (mas1_2_ind='0' or tlb0cfg_ind='0') and mas0_2_wq/="10" and (mas0_2_atsel='0' or ex5_state_q(1)='1') ) or + ( mas1_tsize_indirect(2)='0' and mas1_2_ind='1' and tlb0cfg_ind='1' and mas0_2_wq/="10" and (mas0_2_atsel='0' or ex5_state_q(1)='1') ) or + ( mas1_tsize_lrat(2)='0' and mas0_2_atsel='1' and (mas0_2_wq="00" or mas0_2_wq="11") and ex5_state_q(1)='0' ) + else '0'; +ex6_tlbwe_mas1_tsize_not_supp(2) <= '1' when ( mas1_tsize_direct(2)='0' and (mas1_2_ind='0' or tlb0cfg_ind='0') and mas0_2_wq/="10" and (mas0_2_atsel='0' or ex6_state_q(1)='1') ) or + ( mas1_tsize_indirect(2)='0' and mas1_2_ind='1' and tlb0cfg_ind='1' and mas0_2_wq/="10" and (mas0_2_atsel='0' or ex6_state_q(1)='1') ) or + ( mas1_tsize_lrat(2)='0' and mas0_2_atsel='1' and (mas0_2_wq="00" or mas0_2_wq="11") and ex6_state_q(1)='0' ) + else '0'; +ex5_tlbwe_mas0_lrat_bad_selects(2) <= '1' when ( (mas0_2_hes='1' or mas0_2_wq="01" or mas0_2_wq="10") and mas0_2_atsel='1' and ex5_state_q(1)='0' ) + else '0'; +ex6_tlbwe_mas0_lrat_bad_selects(2) <= '1' when ( (mas0_2_hes='1' or mas0_2_wq="01" or mas0_2_wq="10") and mas0_2_atsel='1' and ex6_state_q(1)='0' ) + else '0'; +ex5_tlbwe_mas2_ind_bad_wimge(2) <= '1' when ( mas1_2_ind='1' and tlb0cfg_ind='1' and mas0_2_wq/="10" and + (mas2_2_wimge(1)='1' or mas2_2_wimge(2)='0' or mas2_2_wimge(3)='1' or mas2_2_wimge(4)='1') and + (mas0_2_atsel='0' or ex5_state_q(1)='1') ) + else '0'; +ex6_tlbwe_mas2_ind_bad_wimge(2) <= '1' when ( mas1_2_ind='1' and tlb0cfg_ind='1' and mas0_2_wq/="10" and + (mas2_2_wimge(1)='1' or mas2_2_wimge(2)='0' or mas2_2_wimge(3)='1' or mas2_2_wimge(4)='1') and + (mas0_2_atsel='0' or ex6_state_q(1)='1') ) + else '0'; +-- Added for illegal indirect page size and sub-page size combinations +mas3_spsize_indirect(2) <= '1' when ((mas1_2_tsize=TLB_PgSize_1MB and mas3_2_usxwr(0 to 3)=TLB_PgSize_4KB) or + (mas1_2_tsize=TLB_PgSize_256MB and mas3_2_usxwr(0 to 3)=TLB_PgSize_64KB)) + else '0'; +ex5_tlbwe_mas3_ind_bad_spsize(2) <= '1' when ( mas1_2_ind='1' and tlb0cfg_ind='1' and mas0_2_wq/="10" and mas3_spsize_indirect(2)='0' and (mas0_2_atsel='0' or ex5_state_q(1)='1') ) + else '0'; +ex6_tlbwe_mas3_ind_bad_spsize(2) <= '1' when ( mas1_2_ind='1' and tlb0cfg_ind='1' and mas0_2_wq/="10" and mas3_spsize_indirect(2)='0' and (mas0_2_atsel='0' or ex6_state_q(1)='1') ) + else '0'; +mas1_tsize_direct(3) <= ( Eq(mas1_3_tsize,TLB_PgSize_4KB) or Eq(mas1_3_tsize,TLB_PgSize_64KB) or + Eq(mas1_3_tsize,TLB_PgSize_1MB) or Eq(mas1_3_tsize,TLB_PgSize_16MB) or + Eq(mas1_3_tsize,TLB_PgSize_1GB) ); +mas1_tsize_indirect(3) <= ( Eq(mas1_3_tsize,TLB_PgSize_1MB) or Eq(mas1_3_tsize,TLB_PgSize_256MB) ); +mas1_tsize_lrat(3) <= ( Eq(mas1_3_tsize,LRAT_PgSize_1MB) or Eq(mas1_3_tsize,LRAT_PgSize_16MB) or + Eq(mas1_3_tsize,LRAT_PgSize_256MB) or Eq(mas1_3_tsize,LRAT_PgSize_1GB) or + Eq(mas1_3_tsize,LRAT_PgSize_4GB) or Eq(mas1_3_tsize,LRAT_PgSize_16GB) or + Eq(mas1_3_tsize,LRAT_PgSize_256GB) or Eq(mas1_3_tsize,LRAT_PgSize_1TB) ); +ex2_tlbre_mas1_tsize_not_supp(3) <= '1' when ( mas1_tsize_direct(3)='0' and (mas1_3_ind='0' or tlb0cfg_ind='0') and (mas0_3_atsel='0' or ex2_state_q(1)='1') ) or + ( mas1_tsize_indirect(3)='0' and mas1_3_ind='1' and tlb0cfg_ind='1' and (mas0_3_atsel='0' or ex2_state_q(1)='1') ) + else '0'; +ex5_tlbre_mas1_tsize_not_supp(3) <= '1' when ( mas1_tsize_direct(3)='0' and (mas1_3_ind='0' or tlb0cfg_ind='0') and (mas0_3_atsel='0' or ex5_state_q(1)='1') ) or + ( mas1_tsize_indirect(3)='0' and mas1_3_ind='1' and tlb0cfg_ind='1' and (mas0_3_atsel='0' or ex5_state_q(1)='1') ) + else '0'; +ex5_tlbwe_mas1_tsize_not_supp(3) <= '1' when ( mas1_tsize_direct(3)='0' and (mas1_3_ind='0' or tlb0cfg_ind='0') and mas0_3_wq/="10" and (mas0_3_atsel='0' or ex5_state_q(1)='1') ) or + ( mas1_tsize_indirect(3)='0' and mas1_3_ind='1' and tlb0cfg_ind='1' and mas0_3_wq/="10" and (mas0_3_atsel='0' or ex5_state_q(1)='1') ) or + ( mas1_tsize_lrat(3)='0' and mas0_3_atsel='1' and (mas0_3_wq="00" or mas0_3_wq="11") and ex5_state_q(1)='0' ) + else '0'; +ex6_tlbwe_mas1_tsize_not_supp(3) <= '1' when ( mas1_tsize_direct(3)='0' and (mas1_3_ind='0' or tlb0cfg_ind='0') and mas0_3_wq/="10" and (mas0_3_atsel='0' or ex6_state_q(1)='1') ) or + ( mas1_tsize_indirect(3)='0' and mas1_3_ind='1' and tlb0cfg_ind='1' and mas0_3_wq/="10" and (mas0_3_atsel='0' or ex6_state_q(1)='1') ) or + ( mas1_tsize_lrat(3)='0' and mas0_3_atsel='1' and (mas0_3_wq="00" or mas0_3_wq="11") and ex6_state_q(1)='0' ) + else '0'; +ex5_tlbwe_mas0_lrat_bad_selects(3) <= '1' when ( (mas0_3_hes='1' or mas0_3_wq="01" or mas0_3_wq="10") and mas0_3_atsel='1' and ex5_state_q(1)='0' ) + else '0'; +ex6_tlbwe_mas0_lrat_bad_selects(3) <= '1' when ( (mas0_3_hes='1' or mas0_3_wq="01" or mas0_3_wq="10") and mas0_3_atsel='1' and ex6_state_q(1)='0' ) + else '0'; +ex5_tlbwe_mas2_ind_bad_wimge(3) <= '1' when ( mas1_3_ind='1' and tlb0cfg_ind='1' and mas0_3_wq/="10" and + (mas2_3_wimge(1)='1' or mas2_3_wimge(2)='0' or mas2_3_wimge(3)='1' or mas2_3_wimge(4)='1') and + (mas0_3_atsel='0' or ex5_state_q(1)='1') ) + else '0'; +ex6_tlbwe_mas2_ind_bad_wimge(3) <= '1' when ( mas1_3_ind='1' and tlb0cfg_ind='1' and mas0_3_wq/="10" and + (mas2_3_wimge(1)='1' or mas2_3_wimge(2)='0' or mas2_3_wimge(3)='1' or mas2_3_wimge(4)='1') and + (mas0_3_atsel='0' or ex6_state_q(1)='1') ) + else '0'; +-- Added for illegal indirect page size and sub-page size combinations +mas3_spsize_indirect(3) <= '1' when ((mas1_3_tsize=TLB_PgSize_1MB and mas3_3_usxwr(0 to 3)=TLB_PgSize_4KB) or + (mas1_3_tsize=TLB_PgSize_256MB and mas3_3_usxwr(0 to 3)=TLB_PgSize_64KB)) + else '0'; +ex5_tlbwe_mas3_ind_bad_spsize(3) <= '1' when ( mas1_3_ind='1' and tlb0cfg_ind='1' and mas0_3_wq/="10" and mas3_spsize_indirect(3)='0' and (mas0_3_atsel='0' or ex5_state_q(1)='1') ) + else '0'; +ex6_tlbwe_mas3_ind_bad_spsize(3) <= '1' when ( mas1_3_ind='1' and tlb0cfg_ind='1' and mas0_3_wq/="10" and mas3_spsize_indirect(3)='0' and (mas0_3_atsel='0' or ex6_state_q(1)='1') ) + else '0'; +tlb_ctl_ex2_illeg_instr <= ( ex2_tlbre_mas1_tsize_not_supp and ex2_valid_q and not(xu_ex2_flush) and + (0 to 3 => (ex2_ttype_q(0) and ex2_hv_state and not ex2_mas0_atsel)) ) + or ( (ex6_tlbwe_mas1_tsize_not_supp or ex6_tlbwe_mas0_lrat_bad_selects or ex6_tlbwe_mas2_ind_bad_wimge or ex6_tlbwe_mas3_ind_bad_spsize) and ex6_valid_q and + (0 to 3 => (ex6_ttype_q(1) and (ex6_hv_state or (ex6_priv_state and not ex6_dgtmi_state)))) ); +ex6_illeg_instr_d(0) <= ex5_ttype_q(0) and or_reduce(ex5_tlbre_mas1_tsize_not_supp and ex5_valid_q); +ex6_illeg_instr_d(1) <= ex5_ttype_q(1) and or_reduce((ex5_tlbwe_mas1_tsize_not_supp or ex5_tlbwe_mas0_lrat_bad_selects or ex5_tlbwe_mas2_ind_bad_wimge or ex5_tlbwe_mas3_ind_bad_spsize) and ex5_valid_q); +ex6_illeg_instr <= ex6_illeg_instr_q; +-- state: 0:pr 1:gs 2:as 3:cm +-- Event | Exceptions +-- | PT fault | TLB Inelig | LRAT miss +---------------------------------------------------------- +-- tlbwe | - | hv_priv=1 | lrat_miss=1 +-- | | tlbi=1 | esr_pt=0 +-- | | esr_pt=0 | +---------------------------------------------------------- +-- ptereload | DSI | DSI | lrat_miss=1 +-- (data) | pt_fault=1 | tlbi=1 | esr_pt=1 +-- | PT=1 | esr_pt=0 ? | esr_data=1 +-- | | | esr_epid=class(0) +-- | | | esr_st=class(1) +---------------------------------------------------------- +-- ptereload | ISI | ISI | lrat_miss=1 +-- (inst) | pt_fault=1 | tlbi=1 | esr_pt=1 +-- | PT=1 | esr_pt=0 ? | esr_data=0 +---------------------------------------------------------- +tlb_lper_lpn <= ptereload_req_pte_q(ptepos_rpn+10 to ptepos_rpn+39); +tlb_lper_lps <= ptereload_req_pte_q(ptepos_size to ptepos_size+3); +-- lrat hit_status: 0:val,1:hit,2:multihit,3:inval_pgsize +-- unused tagpos_is def is mas1_v, mas1_iprot for tlbwe, and is (pte.valid & 0) for ptereloads +tlb_lper_we <= tlb_tag0_q(tagpos_thdid to tagpos_thdid+thdid_width-1) + when (tlb_tag4_ptereload='1' and tlb_tag4_gs='1' and + mmucfg_lrat='1' and tlb_tag4_pt='1' and tlb_tag4_wq="10" and + tlb_tag4_is(0)='1' and lrat_tag4_hit_status(0 to 3)/="1100") + else (others => '0'); +pte_tag0_lpn <= ptereload_req_pte_q(ptepos_rpn+10 to ptepos_rpn+39); +pte_tag0_lpid <= tlb_tag0_q(tagpos_lpid to tagpos_lpid+lpid_width-1); +-- perf count events +tlb_ctl_perf_tlbwec_resv <= or_reduce(ex6_valid_q and tlb_resv_match_vec_q) and ex6_ttype_q(1) and Eq(tlb_tag4_wq,"01"); +tlb_ctl_perf_tlbwec_noresv <= or_reduce(ex6_valid_q and not tlb_resv_match_vec_q) and ex6_ttype_q(1) and Eq(tlb_tag4_wq,"01"); +-- power clock gating for latches +tlb_early_act <= xu_mm_ccr2_notlb_b and (any_tlb_req_sig or not(tlb_seq_idle_sig) or tlb_ctl_any_tag_flush_sig or tlb_seq_abort); +tlb_delayed_act_d(0 TO 1) <= "11" when tlb_early_act='1' + else "10" when tlb_delayed_act_q(0 to 1)="11" + else "01" when tlb_delayed_act_q(0 to 1)="10" + else "00"; +tlb_delayed_act_d(2 TO 8) <= (2 to 8 => tlb_early_act or tlb_delayed_act_q(0) or tlb_delayed_act_q(1) or mmucr2(1)); +tlb_delayed_act_d(9 TO 16) <= (9 to 16 => tlb_early_act or tlb_delayed_act_q(0) or tlb_delayed_act_q(1) or mmucr2(2)); +tlb_delayed_act_d(17 TO 19) <= (17 to 19 => tlb_early_act or tlb_delayed_act_q(0) or tlb_delayed_act_q(1) or mmucr2(2)); +tlb_delayed_act_d(20 TO 23) <= (20 to 23 => tlb_early_act or tlb_delayed_act_q(0) or tlb_delayed_act_q(1) or mmucr2(3)); +tlb_delayed_act_d(24 TO 28) <= (24 to 28 => tlb_early_act or tlb_delayed_act_q(0) or tlb_delayed_act_q(1) or mmucr2(4)); +tlb_delayed_act_d(29 TO 32) <= (29 to 32 => tlb_early_act or tlb_delayed_act_q(0) or tlb_delayed_act_q(1) or mmucr2(6)); +tlb_delayed_act(9 TO 32) <= tlb_delayed_act_q(9 to 32); +tlb_tag0_act <= tlb_early_act or mmucr2(1); +tlb_snoop_act <= (tlb_snoop_coming or mmucr2(1)) and xu_mm_ccr2_notlb_b; +tlb_ctl_dbg_seq_q <= tlb_seq_q; +tlb_ctl_dbg_seq_idle <= tlb_seq_idle_sig; +tlb_ctl_dbg_seq_any_done_sig <= tlb_seq_any_done_sig; +tlb_ctl_dbg_seq_abort <= tlb_seq_abort; +tlb_ctl_dbg_any_tlb_req_sig <= any_tlb_req_sig; +tlb_ctl_dbg_any_req_taken_sig <= any_req_taken_sig; +tlb_ctl_dbg_tag0_valid <= or_reduce(tlb_tag0_q(tagpos_thdid to tagpos_thdid+thdid_width-1)); +tlb_ctl_dbg_tag0_thdid(0) <= tlb_tag0_q(tagpos_thdid+2) or tlb_tag0_q(tagpos_thdid+3); +tlb_ctl_dbg_tag0_thdid(1) <= tlb_tag0_q(tagpos_thdid+1) or tlb_tag0_q(tagpos_thdid+3); +tlb_ctl_dbg_tag0_type(0) <= tlb_tag0_q(tagpos_type+4) or tlb_tag0_q(tagpos_type+5) or tlb_tag0_q(tagpos_type+6) or tlb_tag0_q(tagpos_type+7); +tlb_ctl_dbg_tag0_type(1) <= tlb_tag0_q(tagpos_type+2) or tlb_tag0_q(tagpos_type+3) or tlb_tag0_q(tagpos_type+6) or tlb_tag0_q(tagpos_type+7); +tlb_ctl_dbg_tag0_type(2) <= tlb_tag0_q(tagpos_type+1) or tlb_tag0_q(tagpos_type+3) or tlb_tag0_q(tagpos_type+5) or tlb_tag0_q(tagpos_type+7); +tlb_ctl_dbg_tag0_wq <= tlb_tag0_q(tagpos_wq to tagpos_wq+1); +tlb_ctl_dbg_tag0_gs <= tlb_tag0_q(tagpos_gs); +tlb_ctl_dbg_tag0_pr <= tlb_tag0_q(tagpos_pr); +tlb_ctl_dbg_tag0_atsel <= tlb_tag0_q(tagpos_atsel); +tlb_ctl_dbg_tag5_tlb_write_q <= tlb_write_q; +tlb_ctl_dbg_resv_valid <= tlb_resv_valid_vec; +tlb_ctl_dbg_set_resv <= tlb_set_resv0 & tlb_set_resv1 & tlb_set_resv2 & tlb_set_resv3; +tlb_ctl_dbg_resv_match_vec_q <= tlb_resv_match_vec_q; +tlb_ctl_dbg_any_tag_flush_sig <= tlb_ctl_any_tag_flush_sig; +tlb_ctl_dbg_resv0_tag0_lpid_match <= tlb_resv0_tag0_lpid_match; +tlb_ctl_dbg_resv0_tag0_pid_match <= tlb_resv0_tag0_pid_match; +tlb_ctl_dbg_resv0_tag0_as_snoop_match <= tlb_resv0_tag0_as_snoop_match; +tlb_ctl_dbg_resv0_tag0_gs_snoop_match <= tlb_resv0_tag0_gs_snoop_match; +tlb_ctl_dbg_resv0_tag0_as_tlbwe_match <= tlb_resv0_tag0_as_tlbwe_match; +tlb_ctl_dbg_resv0_tag0_gs_tlbwe_match <= tlb_resv0_tag0_gs_tlbwe_match; +tlb_ctl_dbg_resv0_tag0_ind_match <= tlb_resv0_tag0_ind_match; +tlb_ctl_dbg_resv0_tag0_epn_loc_match <= tlb_resv0_tag0_epn_loc_match; +tlb_ctl_dbg_resv0_tag0_epn_glob_match <= tlb_resv0_tag0_epn_glob_match; +tlb_ctl_dbg_resv0_tag0_class_match <= tlb_resv0_tag0_class_match; +tlb_ctl_dbg_resv1_tag0_lpid_match <= tlb_resv1_tag0_lpid_match; +tlb_ctl_dbg_resv1_tag0_pid_match <= tlb_resv1_tag0_pid_match; +tlb_ctl_dbg_resv1_tag0_as_snoop_match <= tlb_resv1_tag0_as_snoop_match; +tlb_ctl_dbg_resv1_tag0_gs_snoop_match <= tlb_resv1_tag0_gs_snoop_match; +tlb_ctl_dbg_resv1_tag0_as_tlbwe_match <= tlb_resv1_tag0_as_tlbwe_match; +tlb_ctl_dbg_resv1_tag0_gs_tlbwe_match <= tlb_resv1_tag0_gs_tlbwe_match; +tlb_ctl_dbg_resv1_tag0_ind_match <= tlb_resv1_tag0_ind_match; +tlb_ctl_dbg_resv1_tag0_epn_loc_match <= tlb_resv1_tag0_epn_loc_match; +tlb_ctl_dbg_resv1_tag0_epn_glob_match <= tlb_resv1_tag0_epn_glob_match; +tlb_ctl_dbg_resv1_tag0_class_match <= tlb_resv1_tag0_class_match ; +tlb_ctl_dbg_resv2_tag0_lpid_match <= tlb_resv2_tag0_lpid_match; +tlb_ctl_dbg_resv2_tag0_pid_match <= tlb_resv2_tag0_pid_match; +tlb_ctl_dbg_resv2_tag0_as_snoop_match <= tlb_resv2_tag0_as_snoop_match; +tlb_ctl_dbg_resv2_tag0_gs_snoop_match <= tlb_resv2_tag0_gs_snoop_match; +tlb_ctl_dbg_resv2_tag0_as_tlbwe_match <= tlb_resv2_tag0_as_tlbwe_match; +tlb_ctl_dbg_resv2_tag0_gs_tlbwe_match <= tlb_resv2_tag0_gs_tlbwe_match; +tlb_ctl_dbg_resv2_tag0_ind_match <= tlb_resv2_tag0_ind_match; +tlb_ctl_dbg_resv2_tag0_epn_loc_match <= tlb_resv2_tag0_epn_loc_match; +tlb_ctl_dbg_resv2_tag0_epn_glob_match <= tlb_resv2_tag0_epn_glob_match; +tlb_ctl_dbg_resv2_tag0_class_match <= tlb_resv2_tag0_class_match; +tlb_ctl_dbg_resv3_tag0_lpid_match <= tlb_resv3_tag0_lpid_match; +tlb_ctl_dbg_resv3_tag0_pid_match <= tlb_resv3_tag0_pid_match; +tlb_ctl_dbg_resv3_tag0_as_snoop_match <= tlb_resv3_tag0_as_snoop_match; +tlb_ctl_dbg_resv3_tag0_gs_snoop_match <= tlb_resv3_tag0_gs_snoop_match; +tlb_ctl_dbg_resv3_tag0_as_tlbwe_match <= tlb_resv3_tag0_as_tlbwe_match; +tlb_ctl_dbg_resv3_tag0_gs_tlbwe_match <= tlb_resv3_tag0_gs_tlbwe_match; +tlb_ctl_dbg_resv3_tag0_ind_match <= tlb_resv3_tag0_ind_match; +tlb_ctl_dbg_resv3_tag0_epn_loc_match <= tlb_resv3_tag0_epn_loc_match; +tlb_ctl_dbg_resv3_tag0_epn_glob_match <= tlb_resv3_tag0_epn_glob_match; +tlb_ctl_dbg_resv3_tag0_class_match <= tlb_resv3_tag0_class_match; +tlb_ctl_dbg_clr_resv_q <= tlb_clr_resv_q; +tlb_ctl_dbg_clr_resv_terms <= (others => '0'); +-- unused spare signal assignments +unused_dc(0) <= or_reduce(LCB_DELAY_LCLKR_DC(1 TO 4)); +unused_dc(1) <= or_reduce(LCB_MPW1_DC_B(1 TO 4)); +unused_dc(2) <= PC_FUNC_SL_FORCE; +unused_dc(3) <= PC_FUNC_SL_THOLD_0_B; +unused_dc(4) <= TC_SCAN_DIS_DC_B; +unused_dc(5) <= TC_SCAN_DIAG_DC; +unused_dc(6) <= TC_LBIST_EN_DC; +unused_dc(7) <= TLB_TAG0_Q(109); +unused_dc(8) <= or_reduce(MMUCR3_0(49 TO 53)); +unused_dc(9) <= or_reduce(MMUCR3_0(56 TO 63)); +unused_dc(10) <= or_reduce(MMUCR3_1(49 TO 53)); +unused_dc(11) <= or_reduce(MMUCR3_1(56 TO 63)); +unused_dc(12) <= or_reduce(MMUCR3_2(49 TO 53)); +unused_dc(13) <= or_reduce(MMUCR3_2(56 TO 63)); +unused_dc(14) <= or_reduce(MMUCR3_3(49 TO 53)); +unused_dc(15) <= or_reduce(MMUCR3_3(56 TO 63)); +unused_dc(16) <= or_reduce(PGSIZE_QTY); +unused_dc(17) <= or_reduce(PGSIZE_TID0_QTY); +unused_dc(18) <= PTERELOAD_REQ_TAG(66); +unused_dc(19) <= or_reduce(PTERELOAD_REQ_TAG(78 TO 81)); +unused_dc(20) <= or_reduce(PTERELOAD_REQ_TAG(84 TO 89)); +unused_dc(21) <= PTERELOAD_REQ_TAG(98); +unused_dc(22) <= or_reduce(PTERELOAD_REQ_TAG(108 TO 109)); +unused_dc(23) <= LRU_TAG4_DATAOUT(7); +unused_dc(24) <= or_reduce(LRU_TAG4_DATAOUT(12 TO 15)); +unused_dc(25) <= TLB_TAG4_ESEL(0); +unused_dc(26) <= EX3_VALID_32B; +unused_dc(27) <= MAS2_0_WIMGE(0) or MAS2_1_WIMGE(0) or MAS2_2_WIMGE(0) or MAS2_3_WIMGE(0); +unused_dc(28) <= or_reduce(XU_EX1_FLUSH_Q); +unused_dc(29) <= or_reduce(MM_XU_ERATMISS_DONE); +unused_dc(30) <= or_reduce(MM_XU_TLB_MISS); +unused_dc(31) <= or_reduce(MM_XU_TLB_INELIG); +unused_dc(32) <= MMUCR1_TLBI_MSB; +unused_dc(33) <= MMUCSR0_TLB0FI; +unused_dc(34) <= tlb_tag4_pr; +unused_dc(35) <= or_reduce(MMUCR2(0) & MMUCR2(5) & MMUCR2(7) & MMUCR2(8 to 11)); +----------------------------------------------------------------------- +-- Latches +----------------------------------------------------------------------- +xu_ex1_flush_latch: tri_rlmreg_p + generic map (width => xu_ex1_flush_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(xu_ex1_flush_offset to xu_ex1_flush_offset+xu_ex1_flush_q'length-1), + scout => sov(xu_ex1_flush_offset to xu_ex1_flush_offset+xu_ex1_flush_q'length-1), + din => xu_ex1_flush_d(0 to thdid_width-1), + dout => xu_ex1_flush_q(0 to thdid_width-1) ); +ex1_valid_latch: tri_rlmreg_p + generic map (width => ex1_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex1_valid_offset to ex1_valid_offset+ex1_valid_q'length-1), + scout => sov(ex1_valid_offset to ex1_valid_offset+ex1_valid_q'length-1), + din => ex1_valid_d(0 to thdid_width-1), + dout => ex1_valid_q(0 to thdid_width-1) ); +ex1_ttype_latch: tri_rlmreg_p + generic map (width => ex1_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex1_ttype_offset to ex1_ttype_offset+ex1_ttype_q'length-1), + scout => sov(ex1_ttype_offset to ex1_ttype_offset+ex1_ttype_q'length-1), + din => ex1_ttype_d(0 to ttype_width-1), + dout => ex1_ttype_q(0 to ttype_width-1) ); +ex1_state_latch: tri_rlmreg_p + generic map (width => ex1_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex1_state_offset to ex1_state_offset+ex1_state_q'length-1), + scout => sov(ex1_state_offset to ex1_state_offset+ex1_state_q'length-1), + din => ex1_state_d(0 to state_width), + dout => ex1_state_q(0 to state_width) ); +ex1_pid_latch: tri_rlmreg_p + generic map (width => ex1_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex1_pid_offset to ex1_pid_offset+ex1_pid_q'length-1), + scout => sov(ex1_pid_offset to ex1_pid_offset+ex1_pid_q'length-1), + din => ex1_pid_d(0 to pid_width-1), + dout => ex1_pid_q(0 to pid_width-1) ); +------------------------------------------------------------------------------- +ex2_valid_latch: tri_rlmreg_p + generic map (width => ex2_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex2_valid_offset to ex2_valid_offset+ex2_valid_q'length-1), + scout => sov(ex2_valid_offset to ex2_valid_offset+ex2_valid_q'length-1), + din => ex2_valid_d(0 to thdid_width-1), + dout => ex2_valid_q(0 to thdid_width-1) ); +ex2_flush_latch: tri_rlmreg_p + generic map (width => ex2_flush_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex2_flush_offset to ex2_flush_offset+ex2_flush_q'length-1), + scout => sov(ex2_flush_offset to ex2_flush_offset+ex2_flush_q'length-1), + din => ex2_flush_d(0 to thdid_width-1), + dout => ex2_flush_q(0 to thdid_width-1) ); +ex2_flush_req_latch: tri_rlmreg_p + generic map (width => ex2_flush_req_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex2_flush_req_offset to ex2_flush_req_offset+ex2_flush_req_q'length-1), + scout => sov(ex2_flush_req_offset to ex2_flush_req_offset+ex2_flush_req_q'length-1), + din => ex2_flush_req_d(0 to thdid_width-1), + dout => ex2_flush_req_q(0 to thdid_width-1) ); +ex2_ttype_latch: tri_rlmreg_p + generic map (width => ex2_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex2_ttype_offset to ex2_ttype_offset+ex2_ttype_q'length-1), + scout => sov(ex2_ttype_offset to ex2_ttype_offset+ex2_ttype_q'length-1), + din => ex2_ttype_d(0 to ttype_width-1), + dout => ex2_ttype_q(0 to ttype_width-1) ); +ex2_state_latch: tri_rlmreg_p + generic map (width => ex2_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex2_state_offset to ex2_state_offset+ex2_state_q'length-1), + scout => sov(ex2_state_offset to ex2_state_offset+ex2_state_q'length-1), + din => ex2_state_d(0 to state_width), + dout => ex2_state_q(0 to state_width) ); +ex2_pid_latch: tri_rlmreg_p + generic map (width => ex2_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex2_pid_offset to ex2_pid_offset+ex2_pid_q'length-1), + scout => sov(ex2_pid_offset to ex2_pid_offset+ex2_pid_q'length-1), + din => ex2_pid_d(0 to pid_width-1), + dout => ex2_pid_q(0 to pid_width-1) ); +------------------------------------------------------------------------------- +ex3_valid_latch: tri_rlmreg_p + generic map (width => ex3_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex3_valid_offset to ex3_valid_offset+ex3_valid_q'length-1), + scout => sov(ex3_valid_offset to ex3_valid_offset+ex3_valid_q'length-1), + din => ex3_valid_d(0 to thdid_width-1), + dout => ex3_valid_q(0 to thdid_width-1) ); +ex3_flush_latch: tri_rlmreg_p + generic map (width => ex3_flush_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex3_flush_offset to ex3_flush_offset+ex3_flush_q'length-1), + scout => sov(ex3_flush_offset to ex3_flush_offset+ex3_flush_q'length-1), + din => ex3_flush_d(0 to thdid_width-1), + dout => ex3_flush_q(0 to thdid_width-1) ); +ex3_ttype_latch: tri_rlmreg_p + generic map (width => ex3_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex3_ttype_offset to ex3_ttype_offset+ex3_ttype_q'length-1), + scout => sov(ex3_ttype_offset to ex3_ttype_offset+ex3_ttype_q'length-1), + din => ex3_ttype_d(0 to ttype_width-1), + dout => ex3_ttype_q(0 to ttype_width-1) ); +ex3_state_latch: tri_rlmreg_p + generic map (width => ex3_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex3_state_offset to ex3_state_offset+ex3_state_q'length-1), + scout => sov(ex3_state_offset to ex3_state_offset+ex3_state_q'length-1), + din => ex3_state_d(0 to state_width), + dout => ex3_state_q(0 to state_width) ); +ex3_pid_latch: tri_rlmreg_p + generic map (width => ex3_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex3_pid_offset to ex3_pid_offset+ex3_pid_q'length-1), + scout => sov(ex3_pid_offset to ex3_pid_offset+ex3_pid_q'length-1), + din => ex3_pid_d(0 to pid_width-1), + dout => ex3_pid_q(0 to pid_width-1) ); +------------------------------------------------------------------------------- +ex4_valid_latch: tri_rlmreg_p + generic map (width => ex4_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex4_valid_offset to ex4_valid_offset+ex4_valid_q'length-1), + scout => sov(ex4_valid_offset to ex4_valid_offset+ex4_valid_q'length-1), + din => ex4_valid_d(0 to thdid_width-1), + dout => ex4_valid_q(0 to thdid_width-1) ); +ex4_flush_latch: tri_rlmreg_p + generic map (width => ex4_flush_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex4_flush_offset to ex4_flush_offset+ex4_flush_q'length-1), + scout => sov(ex4_flush_offset to ex4_flush_offset+ex4_flush_q'length-1), + din => ex4_flush_d(0 to thdid_width-1), + dout => ex4_flush_q(0 to thdid_width-1) ); +ex4_ttype_latch: tri_rlmreg_p + generic map (width => ex4_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex4_ttype_offset to ex4_ttype_offset+ex4_ttype_q'length-1), + scout => sov(ex4_ttype_offset to ex4_ttype_offset+ex4_ttype_q'length-1), + din => ex4_ttype_d(0 to ttype_width-1), + dout => ex4_ttype_q(0 to ttype_width-1) ); +ex4_state_latch: tri_rlmreg_p + generic map (width => ex4_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex4_state_offset to ex4_state_offset+ex4_state_q'length-1), + scout => sov(ex4_state_offset to ex4_state_offset+ex4_state_q'length-1), + din => ex4_state_d(0 to state_width), + dout => ex4_state_q(0 to state_width) ); +ex4_pid_latch: tri_rlmreg_p + generic map (width => ex4_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex4_pid_offset to ex4_pid_offset+ex4_pid_q'length-1), + scout => sov(ex4_pid_offset to ex4_pid_offset+ex4_pid_q'length-1), + din => ex4_pid_d(0 to pid_width-1), + dout => ex4_pid_q(0 to pid_width-1) ); +------------------------------------------------------------------------------- +ex5_valid_latch: tri_rlmreg_p + generic map (width => ex5_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex5_valid_offset to ex5_valid_offset+ex5_valid_q'length-1), + scout => sov(ex5_valid_offset to ex5_valid_offset+ex5_valid_q'length-1), + din => ex5_valid_d(0 to thdid_width-1), + dout => ex5_valid_q(0 to thdid_width-1) ); +ex5_flush_latch: tri_rlmreg_p + generic map (width => ex5_flush_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex5_flush_offset to ex5_flush_offset+ex5_flush_q'length-1), + scout => sov(ex5_flush_offset to ex5_flush_offset+ex5_flush_q'length-1), + din => ex5_flush_d(0 to thdid_width-1), + dout => ex5_flush_q(0 to thdid_width-1) ); +ex5_ttype_latch: tri_rlmreg_p + generic map (width => ex5_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex5_ttype_offset to ex5_ttype_offset+ex5_ttype_q'length-1), + scout => sov(ex5_ttype_offset to ex5_ttype_offset+ex5_ttype_q'length-1), + din => ex5_ttype_d(0 to ttype_width-1), + dout => ex5_ttype_q(0 to ttype_width-1) ); +ex5_state_latch: tri_rlmreg_p + generic map (width => ex5_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex5_state_offset to ex5_state_offset+ex5_state_q'length-1), + scout => sov(ex5_state_offset to ex5_state_offset+ex5_state_q'length-1), + din => ex5_state_d(0 to state_width), + dout => ex5_state_q(0 to state_width) ); +ex5_pid_latch: tri_rlmreg_p + generic map (width => ex5_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex5_pid_offset to ex5_pid_offset+ex5_pid_q'length-1), + scout => sov(ex5_pid_offset to ex5_pid_offset+ex5_pid_q'length-1), + din => ex5_pid_d(0 to pid_width-1), + dout => ex5_pid_q(0 to pid_width-1) ); +-------------------------------------------------- +ex6_valid_latch: tri_rlmreg_p + generic map (width => ex6_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex6_valid_offset to ex6_valid_offset+ex6_valid_q'length-1), + scout => sov(ex6_valid_offset to ex6_valid_offset+ex6_valid_q'length-1), + din => ex6_valid_d(0 to thdid_width-1), + dout => ex6_valid_q(0 to thdid_width-1) ); +ex6_flush_latch: tri_rlmreg_p + generic map (width => ex6_flush_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex6_flush_offset to ex6_flush_offset+ex6_flush_q'length-1), + scout => sov(ex6_flush_offset to ex6_flush_offset+ex6_flush_q'length-1), + din => ex6_flush_d(0 to thdid_width-1), + dout => ex6_flush_q(0 to thdid_width-1) ); +ex6_ttype_latch: tri_rlmreg_p + generic map (width => ex6_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex6_ttype_offset to ex6_ttype_offset+ex6_ttype_q'length-1), + scout => sov(ex6_ttype_offset to ex6_ttype_offset+ex6_ttype_q'length-1), + din => ex6_ttype_d(0 to ttype_width-1), + dout => ex6_ttype_q(0 to ttype_width-1) ); +ex6_state_latch: tri_rlmreg_p + generic map (width => ex6_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex6_state_offset to ex6_state_offset+ex6_state_q'length-1), + scout => sov(ex6_state_offset to ex6_state_offset+ex6_state_q'length-1), + din => ex6_state_d(0 to state_width), + dout => ex6_state_q(0 to state_width) ); +ex6_pid_latch: tri_rlmreg_p + generic map (width => ex6_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex6_pid_offset to ex6_pid_offset+ex6_pid_q'length-1), + scout => sov(ex6_pid_offset to ex6_pid_offset+ex6_pid_q'length-1), + din => ex6_pid_d(0 to pid_width-1), + dout => ex6_pid_q(0 to pid_width-1) ); +-------------------------------------------------- +-- ws=1 holding latches for tlbwe's +tlb_tag0_latch: tri_rlmreg_p + generic map (width => tlb_tag0_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_tag0_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_tag0_offset to tlb_tag0_offset+tlb_tag0_q'length-1), + scout => sov(tlb_tag0_offset to tlb_tag0_offset+tlb_tag0_q'length-1), + din => tlb_tag0_d(0 to tlb_tag_width-1), + dout => tlb_tag0_q(0 to tlb_tag_width-1) ); +tlb_tag1_latch: tri_rlmreg_p + generic map (width => tlb_tag1_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_tag1_offset to tlb_tag1_offset+tlb_tag1_q'length-1), + scout => sov(tlb_tag1_offset to tlb_tag1_offset+tlb_tag1_q'length-1), + din => tlb_tag1_d(0 to tlb_tag_width-1), + dout => tlb_tag1_q(0 to tlb_tag_width-1) ); +tlb_tag2_latch: tri_rlmreg_p + generic map (width => tlb_tag2_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_tag2_offset to tlb_tag2_offset+tlb_tag2_q'length-1), + scout => sov(tlb_tag2_offset to tlb_tag2_offset+tlb_tag2_q'length-1), + din => tlb_tag2_d(0 to tlb_tag_width-1), + dout => tlb_tag2_q(0 to tlb_tag_width-1) ); +-- hashed address input to tlb, tag1 phase +tlb_addr_latch: tri_rlmreg_p + generic map (width => tlb_addr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(4), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_addr_offset to tlb_addr_offset+tlb_addr_q'length-1), + scout => sov(tlb_addr_offset to tlb_addr_offset+tlb_addr_q'length-1), + din => tlb_addr_d(0 to tlb_addr_width-1), + dout => tlb_addr_q(0 to tlb_addr_width-1) ); +-- hashed address input to tlb, tag2 phase +tlb_addr2_latch: tri_rlmreg_p + generic map (width => tlb_addr2_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(4), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_addr2_offset to tlb_addr2_offset+tlb_addr2_q'length-1), + scout => sov(tlb_addr2_offset to tlb_addr2_offset+tlb_addr2_q'length-1), + din => tlb_addr2_d(0 to tlb_addr_width-1), + dout => tlb_addr2_q(0 to tlb_addr_width-1) ); +tlb_write_latch: tri_rlmreg_p + generic map (width => tlb_write_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(4), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_write_offset to tlb_write_offset+tlb_write_q'length-1), + scout => sov(tlb_write_offset to tlb_write_offset+tlb_write_q'length-1), + din => tlb_write_d(0 to tlb_ways-1), + dout => tlb_write_q(0 to tlb_ways-1) ); +ex6_illeg_instr_latch: tri_rlmreg_p + generic map (width => ex6_illeg_instr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(4), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex6_illeg_instr_offset to ex6_illeg_instr_offset+ex6_illeg_instr_q'length-1), + scout => sov(ex6_illeg_instr_offset to ex6_illeg_instr_offset+ex6_illeg_instr_q'length-1), + din => ex6_illeg_instr_d, + dout => ex6_illeg_instr_q ); +-- sequencer latches +tlb_seq_latch: tri_rlmreg_p + generic map (width => tlb_seq_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_seq_offset to tlb_seq_offset+tlb_seq_q'length-1), + scout => sov(tlb_seq_offset to tlb_seq_offset+tlb_seq_q'length-1), + din => tlb_seq_d(0 to tlb_seq_width-1), + dout => tlb_seq_q(0 to tlb_seq_width-1) ); +derat_taken_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_taken_offset), + scout => sov(derat_taken_offset), + din => derat_taken_d, + dout => derat_taken_q); +xucr4_mmu_mchk_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(xucr4_mmu_mchk_offset), + scout => sov(xucr4_mmu_mchk_offset), + din => xu_mm_xucr4_mmu_mchk, + dout => xu_mm_xucr4_mmu_mchk_q); +-- data out latches +snoop_val_latch: tri_rlmreg_p + generic map (width => snoop_val_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_snoop_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(snoop_val_offset to snoop_val_offset+snoop_val_q'length-1), + scout => sov(snoop_val_offset to snoop_val_offset+snoop_val_q'length-1), + din => snoop_val_d, + dout => snoop_val_q ); +snoop_attr_latch: tri_rlmreg_p + generic map (width => snoop_attr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_snoop_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(snoop_attr_offset to snoop_attr_offset+snoop_attr_q'length-1), + scout => sov(snoop_attr_offset to snoop_attr_offset+snoop_attr_q'length-1), + din => snoop_attr_d, + dout => snoop_attr_q ); +snoop_vpn_latch: tri_rlmreg_p + generic map (width => snoop_vpn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_snoop_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(snoop_vpn_offset to snoop_vpn_offset+snoop_vpn_q'length-1), + scout => sov(snoop_vpn_offset to snoop_vpn_offset+snoop_vpn_q'length-1), + din => snoop_vpn_d, + dout => snoop_vpn_q ); +tlb_clr_resv_latch: tri_rlmreg_p + generic map (width => tlb_clr_resv_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(4), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_clr_resv_offset to tlb_clr_resv_offset+tlb_clr_resv_q'length-1), + scout => sov(tlb_clr_resv_offset to tlb_clr_resv_offset+tlb_clr_resv_q'length-1), + din => tlb_clr_resv_d, + dout => tlb_clr_resv_q ); +tlb_resv_match_vec_latch: tri_rlmreg_p + generic map (width => tlb_resv_match_vec_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(4), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv_match_vec_offset to tlb_resv_match_vec_offset+tlb_resv_match_vec_q'length-1), + scout => sov(tlb_resv_match_vec_offset to tlb_resv_match_vec_offset+tlb_resv_match_vec_q'length-1), + din => tlb_resv_match_vec_d, + dout => tlb_resv_match_vec_q ); +tlb_resv0_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv0_valid_offset), + scout => sov(tlb_resv0_valid_offset), + din => tlb_resv0_valid_d, + dout => tlb_resv0_valid_q); +tlb_resv0_epn_latch: tri_rlmreg_p + generic map (width => tlb_resv0_epn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv0_epn_offset to tlb_resv0_epn_offset+tlb_resv0_epn_q'length-1), + scout => sov(tlb_resv0_epn_offset to tlb_resv0_epn_offset+tlb_resv0_epn_q'length-1), + din => tlb_resv0_epn_d, + dout => tlb_resv0_epn_q); +tlb_resv0_pid_latch: tri_rlmreg_p + generic map (width => tlb_resv0_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv0_pid_offset to tlb_resv0_pid_offset+tlb_resv0_pid_q'length-1), + scout => sov(tlb_resv0_pid_offset to tlb_resv0_pid_offset+tlb_resv0_pid_q'length-1), + din => tlb_resv0_pid_d(0 to pid_width-1), + dout => tlb_resv0_pid_q(0 to pid_width-1)); +tlb_resv0_lpid_latch: tri_rlmreg_p + generic map (width => tlb_resv0_lpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv0_lpid_offset to tlb_resv0_lpid_offset+tlb_resv0_lpid_q'length-1), + scout => sov(tlb_resv0_lpid_offset to tlb_resv0_lpid_offset+tlb_resv0_lpid_q'length-1), + din => tlb_resv0_lpid_d(0 to lpid_width-1), + dout => tlb_resv0_lpid_q(0 to lpid_width-1)); +tlb_resv0_as_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv0_as_offset), + scout => sov(tlb_resv0_as_offset), + din => tlb_resv0_as_d, + dout => tlb_resv0_as_q); +tlb_resv0_gs_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv0_gs_offset), + scout => sov(tlb_resv0_gs_offset), + din => tlb_resv0_gs_d, + dout => tlb_resv0_gs_q); +tlb_resv0_ind_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv0_ind_offset), + scout => sov(tlb_resv0_ind_offset), + din => tlb_resv0_ind_d, + dout => tlb_resv0_ind_q); +tlb_resv0_class_latch: tri_rlmreg_p + generic map (width => tlb_resv0_class_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv0_class_offset to tlb_resv0_class_offset+tlb_resv0_class_q'length-1), + scout => sov(tlb_resv0_class_offset to tlb_resv0_class_offset+tlb_resv0_class_q'length-1), + din => tlb_resv0_class_d(0 to class_width-1), + dout => tlb_resv0_class_q(0 to class_width-1)); +tlb_resv1_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv1_valid_offset), + scout => sov(tlb_resv1_valid_offset), + din => tlb_resv1_valid_d, + dout => tlb_resv1_valid_q); +tlb_resv1_epn_latch: tri_rlmreg_p + generic map (width => tlb_resv1_epn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv1_epn_offset to tlb_resv1_epn_offset+tlb_resv1_epn_q'length-1), + scout => sov(tlb_resv1_epn_offset to tlb_resv1_epn_offset+tlb_resv1_epn_q'length-1), + din => tlb_resv1_epn_d, + dout => tlb_resv1_epn_q); +tlb_resv1_pid_latch: tri_rlmreg_p + generic map (width => tlb_resv1_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv1_pid_offset to tlb_resv1_pid_offset+tlb_resv1_pid_q'length-1), + scout => sov(tlb_resv1_pid_offset to tlb_resv1_pid_offset+tlb_resv1_pid_q'length-1), + din => tlb_resv1_pid_d(0 to pid_width-1), + dout => tlb_resv1_pid_q(0 to pid_width-1)); +tlb_resv1_lpid_latch: tri_rlmreg_p + generic map (width => tlb_resv1_lpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv1_lpid_offset to tlb_resv1_lpid_offset+tlb_resv1_lpid_q'length-1), + scout => sov(tlb_resv1_lpid_offset to tlb_resv1_lpid_offset+tlb_resv1_lpid_q'length-1), + din => tlb_resv1_lpid_d(0 to lpid_width-1), + dout => tlb_resv1_lpid_q(0 to lpid_width-1)); +tlb_resv1_as_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv1_as_offset), + scout => sov(tlb_resv1_as_offset), + din => tlb_resv1_as_d, + dout => tlb_resv1_as_q); +tlb_resv1_gs_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv1_gs_offset), + scout => sov(tlb_resv1_gs_offset), + din => tlb_resv1_gs_d, + dout => tlb_resv1_gs_q); +tlb_resv1_ind_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv1_ind_offset), + scout => sov(tlb_resv1_ind_offset), + din => tlb_resv1_ind_d, + dout => tlb_resv1_ind_q); +tlb_resv1_class_latch: tri_rlmreg_p + generic map (width => tlb_resv1_class_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv1_class_offset to tlb_resv1_class_offset+tlb_resv1_class_q'length-1), + scout => sov(tlb_resv1_class_offset to tlb_resv1_class_offset+tlb_resv1_class_q'length-1), + din => tlb_resv1_class_d(0 to class_width-1), + dout => tlb_resv1_class_q(0 to class_width-1)); +tlb_resv2_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv2_valid_offset), + scout => sov(tlb_resv2_valid_offset), + din => tlb_resv2_valid_d, + dout => tlb_resv2_valid_q); +tlb_resv2_epn_latch: tri_rlmreg_p + generic map (width => tlb_resv2_epn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv2_epn_offset to tlb_resv2_epn_offset+tlb_resv2_epn_q'length-1), + scout => sov(tlb_resv2_epn_offset to tlb_resv2_epn_offset+tlb_resv2_epn_q'length-1), + din => tlb_resv2_epn_d, + dout => tlb_resv2_epn_q); +tlb_resv2_pid_latch: tri_rlmreg_p + generic map (width => tlb_resv2_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv2_pid_offset to tlb_resv2_pid_offset+tlb_resv2_pid_q'length-1), + scout => sov(tlb_resv2_pid_offset to tlb_resv2_pid_offset+tlb_resv2_pid_q'length-1), + din => tlb_resv2_pid_d(0 to pid_width-1), + dout => tlb_resv2_pid_q(0 to pid_width-1)); +tlb_resv2_lpid_latch: tri_rlmreg_p + generic map (width => tlb_resv2_lpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv2_lpid_offset to tlb_resv2_lpid_offset+tlb_resv2_lpid_q'length-1), + scout => sov(tlb_resv2_lpid_offset to tlb_resv2_lpid_offset+tlb_resv2_lpid_q'length-1), + din => tlb_resv2_lpid_d(0 to lpid_width-1), + dout => tlb_resv2_lpid_q(0 to lpid_width-1)); +tlb_resv2_as_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv2_as_offset), + scout => sov(tlb_resv2_as_offset), + din => tlb_resv2_as_d, + dout => tlb_resv2_as_q); +tlb_resv2_gs_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv2_gs_offset), + scout => sov(tlb_resv2_gs_offset), + din => tlb_resv2_gs_d, + dout => tlb_resv2_gs_q); +tlb_resv2_ind_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv2_ind_offset), + scout => sov(tlb_resv2_ind_offset), + din => tlb_resv2_ind_d, + dout => tlb_resv2_ind_q); +tlb_resv2_class_latch: tri_rlmreg_p + generic map (width => tlb_resv2_class_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv2_class_offset to tlb_resv2_class_offset+tlb_resv2_class_q'length-1), + scout => sov(tlb_resv2_class_offset to tlb_resv2_class_offset+tlb_resv2_class_q'length-1), + din => tlb_resv2_class_d(0 to class_width-1), + dout => tlb_resv2_class_q(0 to class_width-1)); +tlb_resv3_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv3_valid_offset), + scout => sov(tlb_resv3_valid_offset), + din => tlb_resv3_valid_d, + dout => tlb_resv3_valid_q); +tlb_resv3_epn_latch: tri_rlmreg_p + generic map (width => tlb_resv3_epn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv3_epn_offset to tlb_resv3_epn_offset+tlb_resv3_epn_q'length-1), + scout => sov(tlb_resv3_epn_offset to tlb_resv3_epn_offset+tlb_resv3_epn_q'length-1), + din => tlb_resv3_epn_d, + dout => tlb_resv3_epn_q); +tlb_resv3_pid_latch: tri_rlmreg_p + generic map (width => tlb_resv3_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv3_pid_offset to tlb_resv3_pid_offset+tlb_resv3_pid_q'length-1), + scout => sov(tlb_resv3_pid_offset to tlb_resv3_pid_offset+tlb_resv3_pid_q'length-1), + din => tlb_resv3_pid_d(0 to pid_width-1), + dout => tlb_resv3_pid_q(0 to pid_width-1)); +tlb_resv3_lpid_latch: tri_rlmreg_p + generic map (width => tlb_resv3_lpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv3_lpid_offset to tlb_resv3_lpid_offset+tlb_resv3_lpid_q'length-1), + scout => sov(tlb_resv3_lpid_offset to tlb_resv3_lpid_offset+tlb_resv3_lpid_q'length-1), + din => tlb_resv3_lpid_d(0 to lpid_width-1), + dout => tlb_resv3_lpid_q(0 to lpid_width-1)); +tlb_resv3_as_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv3_as_offset), + scout => sov(tlb_resv3_as_offset), + din => tlb_resv3_as_d, + dout => tlb_resv3_as_q); +tlb_resv3_gs_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv3_gs_offset), + scout => sov(tlb_resv3_gs_offset), + din => tlb_resv3_gs_d, + dout => tlb_resv3_gs_q); +tlb_resv3_ind_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv3_ind_offset), + scout => sov(tlb_resv3_ind_offset), + din => tlb_resv3_ind_d, + dout => tlb_resv3_ind_q); +tlb_resv3_class_latch: tri_rlmreg_p + generic map (width => tlb_resv3_class_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act_q(5+3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_resv3_class_offset to tlb_resv3_class_offset+tlb_resv3_class_q'length-1), + scout => sov(tlb_resv3_class_offset to tlb_resv3_class_offset+tlb_resv3_class_q'length-1), + din => tlb_resv3_class_d(0 to class_width-1), + dout => tlb_resv3_class_q(0 to class_width-1)); +ptereload_req_pte_latch: tri_rlmreg_p + generic map (width => ptereload_req_pte_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ptereload_req_valid, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ptereload_req_pte_offset to ptereload_req_pte_offset+ptereload_req_pte_q'length-1), + scout => sov(ptereload_req_pte_offset to ptereload_req_pte_offset+ptereload_req_pte_q'length-1), + din => ptereload_req_pte_d, + dout => ptereload_req_pte_q ); +-- power clock gating latches +tlb_delayed_act_latch: tri_rlmreg_p + generic map (width => tlb_delayed_act_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_delayed_act_offset to tlb_delayed_act_offset+tlb_delayed_act_q'length-1), + scout => sov(tlb_delayed_act_offset to tlb_delayed_act_offset+tlb_delayed_act_q'length-1), + din => tlb_delayed_act_d, + dout => tlb_delayed_act_q ); +-- spare latches +tlb_ctl_spare_latch: tri_rlmreg_p + generic map (width => tlb_ctl_spare_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_ctl_spare_offset to tlb_ctl_spare_offset+tlb_ctl_spare_q'length-1), + scout => sov(tlb_ctl_spare_offset to tlb_ctl_spare_offset+tlb_ctl_spare_q'length-1), + din => tlb_ctl_spare_q, + dout => tlb_ctl_spare_q ); +-- non-scannable timing latches +tlb_resv0_tag1_match_latch : tri_regk + generic map (width => 11, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => xu_mm_ccr2_notlb_b, + forcee => pc_func_slp_nsl_force, + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_nsl_thold_0_b, + din(0) => tlb_resv0_tag0_lpid_match, + din(1) => tlb_resv0_tag0_pid_match, + din(2) => tlb_resv0_tag0_as_snoop_match, + din(3) => tlb_resv0_tag0_gs_snoop_match, + din(4) => tlb_resv0_tag0_as_tlbwe_match, + din(5) => tlb_resv0_tag0_gs_tlbwe_match, + din(6) => tlb_resv0_tag0_ind_match, + din(7) => tlb_resv0_tag0_epn_loc_match, + din(8) => tlb_resv0_tag0_epn_glob_match, + din(9) => tlb_resv0_tag0_class_match, + din(10) => tlb_seq_snoop_resv, + dout(0) => tlb_resv0_tag1_lpid_match, + dout(1) => tlb_resv0_tag1_pid_match, + dout(2) => tlb_resv0_tag1_as_snoop_match, + dout(3) => tlb_resv0_tag1_gs_snoop_match, + dout(4) => tlb_resv0_tag1_as_tlbwe_match, + dout(5) => tlb_resv0_tag1_gs_tlbwe_match, + dout(6) => tlb_resv0_tag1_ind_match, + dout(7) => tlb_resv0_tag1_epn_loc_match, + dout(8) => tlb_resv0_tag1_epn_glob_match, + dout(9) => tlb_resv0_tag1_class_match, + dout(10) => tlb_seq_snoop_resv_q(0)); +tlb_resv1_tag1_match_latch : tri_regk + generic map (width => 11, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => xu_mm_ccr2_notlb_b, + forcee => pc_func_slp_nsl_force, + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_nsl_thold_0_b, + din(0) => tlb_resv1_tag0_lpid_match, + din(1) => tlb_resv1_tag0_pid_match, + din(2) => tlb_resv1_tag0_as_snoop_match, + din(3) => tlb_resv1_tag0_gs_snoop_match, + din(4) => tlb_resv1_tag0_as_tlbwe_match, + din(5) => tlb_resv1_tag0_gs_tlbwe_match, + din(6) => tlb_resv1_tag0_ind_match, + din(7) => tlb_resv1_tag0_epn_loc_match, + din(8) => tlb_resv1_tag0_epn_glob_match, + din(9) => tlb_resv1_tag0_class_match, + din(10) => tlb_seq_snoop_resv, + dout(0) => tlb_resv1_tag1_lpid_match, + dout(1) => tlb_resv1_tag1_pid_match, + dout(2) => tlb_resv1_tag1_as_snoop_match, + dout(3) => tlb_resv1_tag1_gs_snoop_match, + dout(4) => tlb_resv1_tag1_as_tlbwe_match, + dout(5) => tlb_resv1_tag1_gs_tlbwe_match, + dout(6) => tlb_resv1_tag1_ind_match, + dout(7) => tlb_resv1_tag1_epn_loc_match, + dout(8) => tlb_resv1_tag1_epn_glob_match, + dout(9) => tlb_resv1_tag1_class_match, + dout(10) => tlb_seq_snoop_resv_q(1)); +tlb_resv2_tag1_match_latch : tri_regk + generic map (width => 11, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => xu_mm_ccr2_notlb_b, + forcee => pc_func_slp_nsl_force, + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_nsl_thold_0_b, + din(0) => tlb_resv2_tag0_lpid_match, + din(1) => tlb_resv2_tag0_pid_match, + din(2) => tlb_resv2_tag0_as_snoop_match, + din(3) => tlb_resv2_tag0_gs_snoop_match, + din(4) => tlb_resv2_tag0_as_tlbwe_match, + din(5) => tlb_resv2_tag0_gs_tlbwe_match, + din(6) => tlb_resv2_tag0_ind_match, + din(7) => tlb_resv2_tag0_epn_loc_match, + din(8) => tlb_resv2_tag0_epn_glob_match, + din(9) => tlb_resv2_tag0_class_match, + din(10) => tlb_seq_snoop_resv, + dout(0) => tlb_resv2_tag1_lpid_match, + dout(1) => tlb_resv2_tag1_pid_match, + dout(2) => tlb_resv2_tag1_as_snoop_match, + dout(3) => tlb_resv2_tag1_gs_snoop_match, + dout(4) => tlb_resv2_tag1_as_tlbwe_match, + dout(5) => tlb_resv2_tag1_gs_tlbwe_match, + dout(6) => tlb_resv2_tag1_ind_match, + dout(7) => tlb_resv2_tag1_epn_loc_match, + dout(8) => tlb_resv2_tag1_epn_glob_match, + dout(9) => tlb_resv2_tag1_class_match, + dout(10) => tlb_seq_snoop_resv_q(2)); +tlb_resv3_tag1_match_latch : tri_regk + generic map (width => 11, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => xu_mm_ccr2_notlb_b, + forcee => pc_func_slp_nsl_force, + d_mode => lcb_d_mode_dc, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + thold_b => pc_func_slp_nsl_thold_0_b, + din(0) => tlb_resv3_tag0_lpid_match, + din(1) => tlb_resv3_tag0_pid_match, + din(2) => tlb_resv3_tag0_as_snoop_match, + din(3) => tlb_resv3_tag0_gs_snoop_match, + din(4) => tlb_resv3_tag0_as_tlbwe_match, + din(5) => tlb_resv3_tag0_gs_tlbwe_match, + din(6) => tlb_resv3_tag0_ind_match, + din(7) => tlb_resv3_tag0_epn_loc_match, + din(8) => tlb_resv3_tag0_epn_glob_match, + din(9) => tlb_resv3_tag0_class_match, + din(10) => tlb_seq_snoop_resv, + dout(0) => tlb_resv3_tag1_lpid_match, + dout(1) => tlb_resv3_tag1_pid_match, + dout(2) => tlb_resv3_tag1_as_snoop_match, + dout(3) => tlb_resv3_tag1_gs_snoop_match, + dout(4) => tlb_resv3_tag1_as_tlbwe_match, + dout(5) => tlb_resv3_tag1_gs_tlbwe_match, + dout(6) => tlb_resv3_tag1_ind_match, + dout(7) => tlb_resv3_tag1_epn_loc_match, + dout(8) => tlb_resv3_tag1_epn_glob_match, + dout(9) => tlb_resv3_tag1_class_match, + dout(10) => tlb_seq_snoop_resv_q(3)); +-------------------------------------------------- +-- thold/sg latches +-------------------------------------------------- +perv_2to1_reg: tri_plat + generic map (width => 5, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ccflush_dc, + din(0) => pc_func_sl_thold_2, + din(1) => pc_func_slp_sl_thold_2, + din(2) => pc_func_slp_nsl_thold_2, + din(3) => pc_sg_2, + din(4) => pc_fce_2, + q(0) => pc_func_sl_thold_1, + q(1) => pc_func_slp_sl_thold_1, + q(2) => pc_func_slp_nsl_thold_1, + q(3) => pc_sg_1, + q(4) => pc_fce_1); +perv_1to0_reg: tri_plat + generic map (width => 5, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ccflush_dc, + din(0) => pc_func_sl_thold_1, + din(1) => pc_func_slp_sl_thold_1, + din(2) => pc_func_slp_nsl_thold_1, + din(3) => pc_sg_1, + din(4) => pc_fce_1, + q(0) => pc_func_sl_thold_0, + q(1) => pc_func_slp_sl_thold_0, + q(2) => pc_func_slp_nsl_thold_0, + q(3) => pc_sg_0, + q(4) => pc_fce_0); +perv_lcbor_func_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b, + thold => pc_func_sl_thold_0, + sg => pc_sg_0, + act_dis => lcb_act_dis_dc, + forcee => pc_func_sl_force, + thold_b => pc_func_sl_thold_0_b); +perv_lcbor_func_slp_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b, + thold => pc_func_slp_sl_thold_0, + sg => pc_sg_0, + act_dis => lcb_act_dis_dc, + forcee => pc_func_slp_sl_force, + thold_b => pc_func_slp_sl_thold_0_b); +perv_nsl_lcbor: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b, + thold => pc_func_slp_nsl_thold_0, + sg => pc_fce_0, + act_dis => tidn, + forcee => pc_func_slp_nsl_force, + thold_b => pc_func_slp_nsl_thold_0_b); +----------------------------------------------------------------------- +-- Scan +----------------------------------------------------------------------- +siv(0 TO scan_right) <= sov(1 to scan_right) & ac_func_scan_in; +ac_func_scan_out <= sov(0); +END MMQ_TLB_CTL; diff --git a/rel/src/vhdl/work/mmq_tlb_lrat.vhdl b/rel/src/vhdl/work/mmq_tlb_lrat.vhdl new file mode 100644 index 0000000..b941dd4 --- /dev/null +++ b/rel/src/vhdl/work/mmq_tlb_lrat.vhdl @@ -0,0 +1,4326 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +--******************************************************************** +--* TITLE: MMU Logical to Real Translate Logic +--* NAME: mmq_tlb_lrat.vhdl +--********************************************************************* + +library ieee; +use ieee.std_logic_1164.all; +library ibm; +use ibm.std_ulogic_unsigned.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_support.all; +library support; +use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity mmq_tlb_lrat is + generic(thdid_width : integer := 4; + ttype_width : integer := 5; + lpid_width : integer := 8; + spr_data_width : integer := 64; + real_addr_width : integer := 42; + rpn_width : integer := 30; + epn_width : integer := 52; + lrat_num_entry : natural := 8; + lrat_num_entry_log2 : natural := 3; + lrat_maxsize_log2 : integer := 40; + lrat_minsize_log2 : integer := 20; + expand_type : integer := 2 ); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + +tc_ccflush_dc : in std_ulogic; +tc_scan_dis_dc_b : in std_ulogic; +tc_scan_diag_dc : in std_ulogic; +tc_lbist_en_dc : in std_ulogic; +lcb_d_mode_dc : in std_ulogic; +lcb_clkoff_dc_b : in std_ulogic; +lcb_act_dis_dc : in std_ulogic; +lcb_mpw1_dc_b : in std_ulogic_vector(0 to 4); +lcb_mpw2_dc_b : in std_ulogic; +lcb_delay_lclkr_dc : in std_ulogic_vector(0 to 4); +ac_func_scan_in :in std_ulogic; +ac_func_scan_out :out std_ulogic; +pc_sg_2 : in std_ulogic; +pc_func_sl_thold_2 : in std_ulogic; +pc_func_slp_sl_thold_2 : in std_ulogic; +xu_mm_ccr2_notlb_b : in std_ulogic; +tlb_delayed_act : in std_ulogic_vector(20 to 23); +mmucr2_act_override : in std_ulogic; +tlb_ctl_ex3_valid : in std_ulogic_vector(0 to thdid_width-1); +tlb_ctl_ex3_ttype : in std_ulogic_vector(0 to ttype_width-1); +xu_ex3_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_ex4_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_ex5_flush : in std_ulogic_vector(0 to thdid_width-1); +tlb_tag0_epn : in std_ulogic_vector(64-real_addr_width to 51); +tlb_tag0_thdid : in std_ulogic_vector(0 to thdid_width-1); +tlb_tag0_type : in std_ulogic_vector(0 to 7); +tlb_tag0_lpid : in std_ulogic_vector(0 to lpid_width-1); +tlb_tag0_size : in std_ulogic_vector(0 to 3); +tlb_tag0_atsel : in std_ulogic; +tlb_tag0_addr_cap : in std_ulogic; +ex6_illeg_instr : in std_ulogic_vector(0 to 1); +pte_tag0_lpn : in std_ulogic_vector(64-real_addr_width to 51); +pte_tag0_lpid : in std_ulogic_vector(0 to lpid_width-1); +mas0_0_atsel : in std_ulogic; +mas0_0_esel : in std_ulogic_vector(0 to lrat_num_entry_log2-1); +mas0_0_hes : in std_ulogic; +mas0_0_wq : in std_ulogic_vector(0 to 1); +mas1_0_v : in std_ulogic; +mas1_0_tsize : in std_ulogic_vector(0 to 3); +mas2_0_epn : in std_ulogic_vector(64-real_addr_width to 51); +mas7_0_rpnu : in std_ulogic_vector(22 to 31); +mas3_0_rpnl : in std_ulogic_vector(32 to 51); +mas8_0_tlpid : in std_ulogic_vector(0 to lpid_width-1); +mmucr3_0_x : in std_ulogic; +mas0_1_atsel : in std_ulogic; +mas0_1_esel : in std_ulogic_vector(0 to lrat_num_entry_log2-1); +mas0_1_hes : in std_ulogic; +mas0_1_wq : in std_ulogic_vector(0 to 1); +mas1_1_v : in std_ulogic; +mas1_1_tsize : in std_ulogic_vector(0 to 3); +mas2_1_epn : in std_ulogic_vector(64-real_addr_width to 51); +mas7_1_rpnu : in std_ulogic_vector(22 to 31); +mas3_1_rpnl : in std_ulogic_vector(32 to 51); +mas8_1_tlpid : in std_ulogic_vector(0 to lpid_width-1); +mmucr3_1_x : in std_ulogic; +mas0_2_atsel : in std_ulogic; +mas0_2_esel : in std_ulogic_vector(0 to lrat_num_entry_log2-1); +mas0_2_hes : in std_ulogic; +mas0_2_wq : in std_ulogic_vector(0 to 1); +mas1_2_v : in std_ulogic; +mas1_2_tsize : in std_ulogic_vector(0 to 3); +mas2_2_epn : in std_ulogic_vector(64-real_addr_width to 51); +mas7_2_rpnu : in std_ulogic_vector(22 to 31); +mas3_2_rpnl : in std_ulogic_vector(32 to 51); +mas8_2_tlpid : in std_ulogic_vector(0 to lpid_width-1); +mmucr3_2_x : in std_ulogic; +mas0_3_atsel : in std_ulogic; +mas0_3_esel : in std_ulogic_vector(0 to lrat_num_entry_log2-1); +mas0_3_hes : in std_ulogic; +mas0_3_wq : in std_ulogic_vector(0 to 1); +mas1_3_v : in std_ulogic; +mas1_3_tsize : in std_ulogic_vector(0 to 3); +mas2_3_epn : in std_ulogic_vector(64-real_addr_width to 51); +mas7_3_rpnu : in std_ulogic_vector(22 to 31); +mas3_3_rpnl : in std_ulogic_vector(32 to 51); +mas8_3_tlpid : in std_ulogic_vector(0 to lpid_width-1); +mmucr3_3_x : in std_ulogic; +lrat_mmucr3_x : out std_ulogic; +lrat_mas0_esel : out std_ulogic_vector(0 to 2); +lrat_mas1_v : out std_ulogic; +lrat_mas1_tsize : out std_ulogic_vector(0 to 3); +lrat_mas2_epn : out std_ulogic_vector(0 to 51); +lrat_mas3_rpnl : out std_ulogic_vector(32 to 51); +lrat_mas7_rpnu : out std_ulogic_vector(22 to 31); +lrat_mas8_tlpid : out std_ulogic_vector(0 to lpid_width-1); +lrat_mas_tlbre : out std_ulogic; +lrat_mas_tlbsx_hit : out std_ulogic; +lrat_mas_tlbsx_miss : out std_ulogic; +lrat_mas_thdid : out std_ulogic_vector(0 to thdid_width-1); +lrat_tag3_lpn : out std_ulogic_vector(64-real_addr_width to 51); +lrat_tag3_rpn : out std_ulogic_vector(64-real_addr_width to 51); +lrat_tag3_hit_status : out std_ulogic_vector(0 to 3); +lrat_tag3_hit_entry : out std_ulogic_vector(0 to lrat_num_entry_log2-1); +lrat_tag4_lpn : out std_ulogic_vector(64-real_addr_width to 51); +lrat_tag4_rpn : out std_ulogic_vector(64-real_addr_width to 51); +lrat_tag4_hit_status : out std_ulogic_vector(0 to 3); +lrat_tag4_hit_entry : out std_ulogic_vector(0 to lrat_num_entry_log2-1); +lrat_dbg_tag1_addr_enable : out std_ulogic; +lrat_dbg_tag2_matchline_q : out std_ulogic_vector(0 to 7); +lrat_dbg_entry0_addr_match : out std_ulogic; +lrat_dbg_entry0_lpid_match : out std_ulogic; +lrat_dbg_entry0_entry_v : out std_ulogic; +lrat_dbg_entry0_entry_x : out std_ulogic; +lrat_dbg_entry0_size : out std_ulogic_vector(0 to 3); +lrat_dbg_entry1_addr_match : out std_ulogic; +lrat_dbg_entry1_lpid_match : out std_ulogic; +lrat_dbg_entry1_entry_v : out std_ulogic; +lrat_dbg_entry1_entry_x : out std_ulogic; +lrat_dbg_entry1_size : out std_ulogic_vector(0 to 3); +lrat_dbg_entry2_addr_match : out std_ulogic; +lrat_dbg_entry2_lpid_match : out std_ulogic; +lrat_dbg_entry2_entry_v : out std_ulogic; +lrat_dbg_entry2_entry_x : out std_ulogic; +lrat_dbg_entry2_size : out std_ulogic_vector(0 to 3); +lrat_dbg_entry3_addr_match : out std_ulogic; +lrat_dbg_entry3_lpid_match : out std_ulogic; +lrat_dbg_entry3_entry_v : out std_ulogic; +lrat_dbg_entry3_entry_x : out std_ulogic; +lrat_dbg_entry3_size : out std_ulogic_vector(0 to 3); +lrat_dbg_entry4_addr_match : out std_ulogic; +lrat_dbg_entry4_lpid_match : out std_ulogic; +lrat_dbg_entry4_entry_v : out std_ulogic; +lrat_dbg_entry4_entry_x : out std_ulogic; +lrat_dbg_entry4_size : out std_ulogic_vector(0 to 3); +lrat_dbg_entry5_addr_match : out std_ulogic; +lrat_dbg_entry5_lpid_match : out std_ulogic; +lrat_dbg_entry5_entry_v : out std_ulogic; +lrat_dbg_entry5_entry_x : out std_ulogic; +lrat_dbg_entry5_size : out std_ulogic_vector(0 to 3); +lrat_dbg_entry6_addr_match : out std_ulogic; +lrat_dbg_entry6_lpid_match : out std_ulogic; +lrat_dbg_entry6_entry_v : out std_ulogic; +lrat_dbg_entry6_entry_x : out std_ulogic; +lrat_dbg_entry6_size : out std_ulogic_vector(0 to 3); +lrat_dbg_entry7_addr_match : out std_ulogic; +lrat_dbg_entry7_lpid_match : out std_ulogic; +lrat_dbg_entry7_entry_v : out std_ulogic; +lrat_dbg_entry7_entry_x : out std_ulogic; +lrat_dbg_entry7_size : out std_ulogic_vector(0 to 3) +); +end mmq_tlb_lrat; +ARCHITECTURE MMQ_TLB_LRAT + OF MMQ_TLB_LRAT + IS +component mmq_tlb_lrat_matchline + generic (real_addr_width : integer := 42; + lpid_width : integer := 8; + lrat_maxsize_log2 : integer := 40; + lrat_minsize_log2 : integer := 20; + have_xbit : integer := 1; + num_pgsizes : integer := 8; + have_cmpmask : integer := 1; + cmpmask_width : integer := 7); +port( + vdd : inout power_logic; + gnd : inout power_logic; + addr_in : in std_ulogic_vector(64-real_addr_width to 64-lrat_minsize_log2-1); + addr_enable : in std_ulogic; + entry_size : in std_ulogic_vector(0 to 3); + entry_cmpmask : in std_ulogic_vector(0 to cmpmask_width-1); + entry_xbit : in std_ulogic; + entry_xbitmask : in std_ulogic_vector(0 to cmpmask_width-1); + entry_lpn : in std_ulogic_vector(64-real_addr_width to 64-lrat_minsize_log2-1); + entry_lpid : in std_ulogic_vector(0 to lpid_width-1); + comp_lpid : in std_ulogic_vector(0 to lpid_width-1); + lpid_enable : in std_ulogic; + entry_v : in std_ulogic; + + match : out std_ulogic; + dbg_addr_match : out std_ulogic; + dbg_lpid_match : out std_ulogic +); +end component; +constant MMU_Mode_Value : std_ulogic := '0'; +constant TLB_PgSize_1GB : std_ulogic_vector(0 to 3) := "1010"; +constant TLB_PgSize_256MB : std_ulogic_vector(0 to 3) := "1001"; +constant TLB_PgSize_16MB : std_ulogic_vector(0 to 3) := "0111"; +constant TLB_PgSize_1MB : std_ulogic_vector(0 to 3) := "0101"; +constant TLB_PgSize_64KB : std_ulogic_vector(0 to 3) := "0011"; +constant TLB_PgSize_4KB : std_ulogic_vector(0 to 3) := "0001"; +constant LRAT_PgSize_1TB : std_ulogic_vector(0 to 3) := "1111"; +constant LRAT_PgSize_256GB : std_ulogic_vector(0 to 3) := "1110"; +constant LRAT_PgSize_16GB : std_ulogic_vector(0 to 3) := "1100"; +constant LRAT_PgSize_4GB : std_ulogic_vector(0 to 3) := "1011"; +constant LRAT_PgSize_1GB : std_ulogic_vector(0 to 3) := "1010"; +constant LRAT_PgSize_256MB : std_ulogic_vector(0 to 3) := "1001"; +constant LRAT_PgSize_16MB : std_ulogic_vector(0 to 3) := "0111"; +constant LRAT_PgSize_1MB : std_ulogic_vector(0 to 3) := "0101"; +constant LRAT_PgSize_1TB_log2 : integer := 40; +constant LRAT_PgSize_256GB_log2 : integer := 38; +constant LRAT_PgSize_16GB_log2 : integer := 34; +constant LRAT_PgSize_4GB_log2 : integer := 32; +constant LRAT_PgSize_1GB_log2 : integer := 30; +constant LRAT_PgSize_256MB_log2 : integer := 28; +constant LRAT_PgSize_16MB_log2 : integer := 24; +constant LRAT_PgSize_1MB_log2 : integer := 20; +-- derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload +constant tagpos_type : natural := 0; +constant tagpos_type_derat : natural := tagpos_type; +constant tagpos_type_ierat : natural := tagpos_type+1; +constant tagpos_type_tlbsx : natural := tagpos_type+2; +constant tagpos_type_tlbsrx : natural := tagpos_type+3; +constant tagpos_type_snoop : natural := tagpos_type+4; +constant tagpos_type_tlbre : natural := tagpos_type+5; +constant tagpos_type_tlbwe : natural := tagpos_type+6; +constant tagpos_type_ptereload : natural := tagpos_type+7; +-- scan path constants +constant ex4_valid_offset : natural := 0; +constant ex4_ttype_offset : natural := ex4_valid_offset + thdid_width; +constant ex5_valid_offset : natural := ex4_ttype_offset + ttype_width; +constant ex5_ttype_offset : natural := ex5_valid_offset + thdid_width; +constant ex5_esel_offset : natural := ex5_ttype_offset + ttype_width; +constant ex5_atsel_offset : natural := ex5_esel_offset + 3; +constant ex5_wq_offset : natural := ex5_atsel_offset + 1; +constant ex5_hes_offset : natural := ex5_wq_offset + 2; +constant ex6_valid_offset : natural := ex5_hes_offset + 1; +constant ex6_ttype_offset : natural := ex6_valid_offset + thdid_width; +constant ex6_esel_offset : natural := ex6_ttype_offset + ttype_width; +constant ex6_atsel_offset : natural := ex6_esel_offset + 3; +constant ex6_wq_offset : natural := ex6_atsel_offset + 1; +constant ex6_hes_offset : natural := ex6_wq_offset + 2; +constant lrat_tag1_lpn_offset : natural := ex6_hes_offset + 1; +constant lrat_tag2_lpn_offset : natural := lrat_tag1_lpn_offset + rpn_width; +constant lrat_tag3_lpn_offset : natural := lrat_tag2_lpn_offset + rpn_width; +constant lrat_tag3_rpn_offset : natural := lrat_tag3_lpn_offset + rpn_width; +constant lrat_tag4_lpn_offset : natural := lrat_tag3_rpn_offset + rpn_width; +constant lrat_tag4_rpn_offset : natural := lrat_tag4_lpn_offset + rpn_width; +constant lrat_tag1_lpid_offset : natural := lrat_tag4_rpn_offset + rpn_width; +constant lrat_tag1_size_offset : natural := lrat_tag1_lpid_offset + lpid_width; +constant lrat_tag2_size_offset : natural := lrat_tag1_size_offset + 4; +constant lrat_tag2_entry_size_offset : natural := lrat_tag2_size_offset + 4; +constant lrat_tag2_matchline_offset : natural := lrat_tag2_entry_size_offset + 4; +constant lrat_tag3_hit_status_offset : natural := lrat_tag2_matchline_offset + lrat_num_entry; +constant lrat_tag3_hit_entry_offset : natural := lrat_tag3_hit_status_offset + 4; +constant lrat_tag4_hit_status_offset : natural := lrat_tag3_hit_entry_offset + lrat_num_entry_log2; +constant lrat_tag4_hit_entry_offset : natural := lrat_tag4_hit_status_offset + 4; +constant tlb_addr_cap_offset : natural := lrat_tag4_hit_entry_offset + lrat_num_entry_log2; +constant lrat_entry0_lpn_offset : natural := tlb_addr_cap_offset + 2; +constant lrat_entry0_rpn_offset : natural := lrat_entry0_lpn_offset + real_addr_width - lrat_minsize_log2; +constant lrat_entry0_lpid_offset : natural := lrat_entry0_rpn_offset + real_addr_width - lrat_minsize_log2; +constant lrat_entry0_size_offset : natural := lrat_entry0_lpid_offset + lpid_width; +constant lrat_entry0_cmpmask_offset : natural := lrat_entry0_size_offset + 4; +constant lrat_entry0_xbitmask_offset : natural := lrat_entry0_cmpmask_offset + 7; +constant lrat_entry0_xbit_offset : natural := lrat_entry0_xbitmask_offset + 7; +constant lrat_entry0_valid_offset : natural := lrat_entry0_xbit_offset + 1; +constant lrat_entry1_lpn_offset : natural := lrat_entry0_valid_offset + 1; +constant lrat_entry1_rpn_offset : natural := lrat_entry1_lpn_offset + real_addr_width - lrat_minsize_log2; +constant lrat_entry1_lpid_offset : natural := lrat_entry1_rpn_offset + real_addr_width - lrat_minsize_log2; +constant lrat_entry1_size_offset : natural := lrat_entry1_lpid_offset + lpid_width; +constant lrat_entry1_cmpmask_offset : natural := lrat_entry1_size_offset + 4; +constant lrat_entry1_xbitmask_offset : natural := lrat_entry1_cmpmask_offset + 7; +constant lrat_entry1_xbit_offset : natural := lrat_entry1_xbitmask_offset + 7; +constant lrat_entry1_valid_offset : natural := lrat_entry1_xbit_offset + 1; +constant lrat_entry2_lpn_offset : natural := lrat_entry1_valid_offset + 1; +constant lrat_entry2_rpn_offset : natural := lrat_entry2_lpn_offset + real_addr_width - lrat_minsize_log2; +constant lrat_entry2_lpid_offset : natural := lrat_entry2_rpn_offset + real_addr_width - lrat_minsize_log2; +constant lrat_entry2_size_offset : natural := lrat_entry2_lpid_offset + lpid_width; +constant lrat_entry2_cmpmask_offset : natural := lrat_entry2_size_offset + 4; +constant lrat_entry2_xbitmask_offset : natural := lrat_entry2_cmpmask_offset + 7; +constant lrat_entry2_xbit_offset : natural := lrat_entry2_xbitmask_offset + 7; +constant lrat_entry2_valid_offset : natural := lrat_entry2_xbit_offset + 1; +constant lrat_entry3_lpn_offset : natural := lrat_entry2_valid_offset + 1; +constant lrat_entry3_rpn_offset : natural := lrat_entry3_lpn_offset + real_addr_width - lrat_minsize_log2; +constant lrat_entry3_lpid_offset : natural := lrat_entry3_rpn_offset + real_addr_width - lrat_minsize_log2; +constant lrat_entry3_size_offset : natural := lrat_entry3_lpid_offset + lpid_width; +constant lrat_entry3_cmpmask_offset : natural := lrat_entry3_size_offset + 4; +constant lrat_entry3_xbitmask_offset : natural := lrat_entry3_cmpmask_offset + 7; +constant lrat_entry3_xbit_offset : natural := lrat_entry3_xbitmask_offset + 7; +constant lrat_entry3_valid_offset : natural := lrat_entry3_xbit_offset + 1; +constant lrat_entry4_lpn_offset : natural := lrat_entry3_valid_offset + 1; +constant lrat_entry4_rpn_offset : natural := lrat_entry4_lpn_offset + real_addr_width - lrat_minsize_log2; +constant lrat_entry4_lpid_offset : natural := lrat_entry4_rpn_offset + real_addr_width - lrat_minsize_log2; +constant lrat_entry4_size_offset : natural := lrat_entry4_lpid_offset + lpid_width; +constant lrat_entry4_cmpmask_offset : natural := lrat_entry4_size_offset + 4; +constant lrat_entry4_xbitmask_offset : natural := lrat_entry4_cmpmask_offset + 7; +constant lrat_entry4_xbit_offset : natural := lrat_entry4_xbitmask_offset + 7; +constant lrat_entry4_valid_offset : natural := lrat_entry4_xbit_offset + 1; +constant lrat_entry5_lpn_offset : natural := lrat_entry4_valid_offset + 1; +constant lrat_entry5_rpn_offset : natural := lrat_entry5_lpn_offset + real_addr_width - lrat_minsize_log2; +constant lrat_entry5_lpid_offset : natural := lrat_entry5_rpn_offset + real_addr_width - lrat_minsize_log2; +constant lrat_entry5_size_offset : natural := lrat_entry5_lpid_offset + lpid_width; +constant lrat_entry5_cmpmask_offset : natural := lrat_entry5_size_offset + 4; +constant lrat_entry5_xbitmask_offset : natural := lrat_entry5_cmpmask_offset + 7; +constant lrat_entry5_xbit_offset : natural := lrat_entry5_xbitmask_offset + 7; +constant lrat_entry5_valid_offset : natural := lrat_entry5_xbit_offset + 1; +constant lrat_entry6_lpn_offset : natural := lrat_entry5_valid_offset + 1; +constant lrat_entry6_rpn_offset : natural := lrat_entry6_lpn_offset + real_addr_width - lrat_minsize_log2; +constant lrat_entry6_lpid_offset : natural := lrat_entry6_rpn_offset + real_addr_width - lrat_minsize_log2; +constant lrat_entry6_size_offset : natural := lrat_entry6_lpid_offset + lpid_width; +constant lrat_entry6_cmpmask_offset : natural := lrat_entry6_size_offset + 4; +constant lrat_entry6_xbitmask_offset : natural := lrat_entry6_cmpmask_offset + 7; +constant lrat_entry6_xbit_offset : natural := lrat_entry6_xbitmask_offset + 7; +constant lrat_entry6_valid_offset : natural := lrat_entry6_xbit_offset + 1; +constant lrat_entry7_lpn_offset : natural := lrat_entry6_valid_offset + 1; +constant lrat_entry7_rpn_offset : natural := lrat_entry7_lpn_offset + real_addr_width - lrat_minsize_log2; +constant lrat_entry7_lpid_offset : natural := lrat_entry7_rpn_offset + real_addr_width - lrat_minsize_log2; +constant lrat_entry7_size_offset : natural := lrat_entry7_lpid_offset + lpid_width; +constant lrat_entry7_cmpmask_offset : natural := lrat_entry7_size_offset + 4; +constant lrat_entry7_xbitmask_offset : natural := lrat_entry7_cmpmask_offset + 7; +constant lrat_entry7_xbit_offset : natural := lrat_entry7_xbitmask_offset + 7; +constant lrat_entry7_valid_offset : natural := lrat_entry7_xbit_offset + 1; +constant lrat_datain_lpn_offset : natural := lrat_entry7_valid_offset + 1; +constant lrat_datain_rpn_offset : natural := lrat_datain_lpn_offset + real_addr_width - lrat_minsize_log2; +constant lrat_datain_lpid_offset : natural := lrat_datain_rpn_offset + real_addr_width - lrat_minsize_log2; +constant lrat_datain_size_offset : natural := lrat_datain_lpid_offset + lpid_width; +constant lrat_datain_xbit_offset : natural := lrat_datain_size_offset + 4; +constant lrat_datain_valid_offset : natural := lrat_datain_xbit_offset + 1; +constant lrat_mas1_v_offset : natural := lrat_datain_valid_offset + 1; +constant lrat_mas1_tsize_offset : natural := lrat_mas1_v_offset + 1; +constant lrat_mas2_epn_offset : natural := lrat_mas1_tsize_offset + 4; +constant lrat_mas3_rpnl_offset : natural := lrat_mas2_epn_offset + rpn_width; +constant lrat_mas7_rpnu_offset : natural := lrat_mas3_rpnl_offset + 20; +constant lrat_mas8_tlpid_offset : natural := lrat_mas7_rpnu_offset + 10; +constant lrat_mas_tlbre_offset : natural := lrat_mas8_tlpid_offset + lpid_width; +constant lrat_mas_tlbsx_hit_offset : natural := lrat_mas_tlbre_offset + 1; +constant lrat_mas_tlbsx_miss_offset : natural := lrat_mas_tlbsx_hit_offset + 1; +constant lrat_mas_thdid_offset : natural := lrat_mas_tlbsx_miss_offset + 1; +constant lrat_mmucr3_x_offset : natural := lrat_mas_thdid_offset + thdid_width; +constant lrat_entry_act_offset : natural := lrat_mmucr3_x_offset + 1; +constant lrat_mas_act_offset : natural := lrat_entry_act_offset + 8; +constant lrat_datain_act_offset : natural := lrat_mas_act_offset +3; +constant spare_offset : natural := lrat_datain_act_offset +2; +constant scan_right : natural := spare_offset + 64 -1; +constant const_lrat_maxsize_log2 : natural := real_addr_width-2; +-- Latch signals +signal ex4_valid_d, ex4_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal ex4_ttype_d, ex4_ttype_q : std_ulogic_vector(0 to ttype_width-1); +signal ex5_valid_d, ex5_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal ex5_ttype_d, ex5_ttype_q : std_ulogic_vector(0 to ttype_width-1); +signal ex5_esel_d, ex5_esel_q : std_ulogic_vector(0 to 2); +signal ex5_atsel_d, ex5_atsel_q : std_ulogic; +signal ex5_hes_d, ex5_hes_q : std_ulogic; +signal ex5_wq_d, ex5_wq_q : std_ulogic_vector(0 to 1); +signal ex6_valid_d, ex6_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal ex6_ttype_d, ex6_ttype_q : std_ulogic_vector(0 to ttype_width-1); +signal ex6_esel_d, ex6_esel_q : std_ulogic_vector(0 to 2); +signal ex6_atsel_d, ex6_atsel_q : std_ulogic; +signal ex6_hes_d, ex6_hes_q : std_ulogic; +signal ex6_wq_d, ex6_wq_q : std_ulogic_vector(0 to 1); +signal lrat_tag1_lpn_d, lrat_tag1_lpn_q : std_ulogic_vector(64-real_addr_width to 51); +signal lrat_tag2_lpn_d, lrat_tag2_lpn_q : std_ulogic_vector(64-real_addr_width to 51); +signal lrat_tag3_lpn_d, lrat_tag3_lpn_q : std_ulogic_vector(64-real_addr_width to 51); +signal lrat_tag3_rpn_d, lrat_tag3_rpn_q : std_ulogic_vector(64-real_addr_width to 51); +signal lrat_tag4_lpn_d, lrat_tag4_lpn_q : std_ulogic_vector(64-real_addr_width to 51); +signal lrat_tag4_rpn_d, lrat_tag4_rpn_q : std_ulogic_vector(64-real_addr_width to 51); +signal lrat_tag1_lpid_d, lrat_tag1_lpid_q : std_ulogic_vector(0 to lpid_width-1); +signal lrat_tag2_matchline_d, lrat_tag2_matchline_q : std_ulogic_vector(0 to lrat_num_entry-1); +signal lrat_tag1_size_d, lrat_tag1_size_q : std_ulogic_vector(0 to 3); +signal lrat_tag2_size_d, lrat_tag2_size_q : std_ulogic_vector(0 to 3); +signal lrat_tag2_entry_size_d, lrat_tag2_entry_size_q : std_ulogic_vector(0 to 3); +signal lrat_tag3_hit_status_d, lrat_tag3_hit_status_q : std_ulogic_vector(0 to 3); +signal lrat_tag3_hit_entry_d, lrat_tag3_hit_entry_q : std_ulogic_vector(0 to lrat_num_entry_log2-1); +signal lrat_tag4_hit_status_d, lrat_tag4_hit_status_q : std_ulogic_vector(0 to 3); +signal lrat_tag4_hit_entry_d, lrat_tag4_hit_entry_q : std_ulogic_vector(0 to lrat_num_entry_log2-1); +signal tlb_addr_cap_d, tlb_addr_cap_q : std_ulogic_vector(1 to 2); +signal lrat_entry0_lpn_d, lrat_entry0_lpn_q : std_ulogic_vector(64-real_addr_width to 64-lrat_minsize_log2-1); +signal lrat_entry0_rpn_d, lrat_entry0_rpn_q : std_ulogic_vector(64-real_addr_width to 64-lrat_minsize_log2-1); +signal lrat_entry0_lpid_d, lrat_entry0_lpid_q : std_ulogic_vector(0 to lpid_width-1); +signal lrat_entry0_size_d, lrat_entry0_size_q : std_ulogic_vector(0 to 3); +signal lrat_entry0_cmpmask_d, lrat_entry0_cmpmask_q : std_ulogic_vector(0 to 6); +signal lrat_entry0_xbitmask_d, lrat_entry0_xbitmask_q : std_ulogic_vector(0 to 6); +signal lrat_entry0_xbit_d, lrat_entry0_xbit_q : std_ulogic; +signal lrat_entry0_valid_d, lrat_entry0_valid_q : std_ulogic; +signal lrat_entry1_lpn_d, lrat_entry1_lpn_q : std_ulogic_vector(64-real_addr_width to 64-lrat_minsize_log2-1); +signal lrat_entry1_rpn_d, lrat_entry1_rpn_q : std_ulogic_vector(64-real_addr_width to 64-lrat_minsize_log2-1); +signal lrat_entry1_lpid_d, lrat_entry1_lpid_q : std_ulogic_vector(0 to lpid_width-1); +signal lrat_entry1_size_d, lrat_entry1_size_q : std_ulogic_vector(0 to 3); +signal lrat_entry1_cmpmask_d, lrat_entry1_cmpmask_q : std_ulogic_vector(0 to 6); +signal lrat_entry1_xbitmask_d, lrat_entry1_xbitmask_q : std_ulogic_vector(0 to 6); +signal lrat_entry1_xbit_d, lrat_entry1_xbit_q : std_ulogic; +signal lrat_entry1_valid_d, lrat_entry1_valid_q : std_ulogic; +signal lrat_entry2_lpn_d, lrat_entry2_lpn_q : std_ulogic_vector(64-real_addr_width to 64-lrat_minsize_log2-1); +signal lrat_entry2_rpn_d, lrat_entry2_rpn_q : std_ulogic_vector(64-real_addr_width to 64-lrat_minsize_log2-1); +signal lrat_entry2_lpid_d, lrat_entry2_lpid_q : std_ulogic_vector(0 to lpid_width-1); +signal lrat_entry2_size_d, lrat_entry2_size_q : std_ulogic_vector(0 to 3); +signal lrat_entry2_cmpmask_d, lrat_entry2_cmpmask_q : std_ulogic_vector(0 to 6); +signal lrat_entry2_xbitmask_d, lrat_entry2_xbitmask_q : std_ulogic_vector(0 to 6); +signal lrat_entry2_xbit_d, lrat_entry2_xbit_q : std_ulogic; +signal lrat_entry2_valid_d, lrat_entry2_valid_q : std_ulogic; +signal lrat_entry3_lpn_d, lrat_entry3_lpn_q : std_ulogic_vector(64-real_addr_width to 64-lrat_minsize_log2-1); +signal lrat_entry3_rpn_d, lrat_entry3_rpn_q : std_ulogic_vector(64-real_addr_width to 64-lrat_minsize_log2-1); +signal lrat_entry3_lpid_d, lrat_entry3_lpid_q : std_ulogic_vector(0 to lpid_width-1); +signal lrat_entry3_size_d, lrat_entry3_size_q : std_ulogic_vector(0 to 3); +signal lrat_entry3_cmpmask_d, lrat_entry3_cmpmask_q : std_ulogic_vector(0 to 6); +signal lrat_entry3_xbitmask_d, lrat_entry3_xbitmask_q : std_ulogic_vector(0 to 6); +signal lrat_entry3_xbit_d, lrat_entry3_xbit_q : std_ulogic; +signal lrat_entry3_valid_d, lrat_entry3_valid_q : std_ulogic; +signal lrat_entry4_lpn_d, lrat_entry4_lpn_q : std_ulogic_vector(64-real_addr_width to 64-lrat_minsize_log2-1); +signal lrat_entry4_rpn_d, lrat_entry4_rpn_q : std_ulogic_vector(64-real_addr_width to 64-lrat_minsize_log2-1); +signal lrat_entry4_lpid_d, lrat_entry4_lpid_q : std_ulogic_vector(0 to lpid_width-1); +signal lrat_entry4_size_d, lrat_entry4_size_q : std_ulogic_vector(0 to 3); +signal lrat_entry4_cmpmask_d, lrat_entry4_cmpmask_q : std_ulogic_vector(0 to 6); +signal lrat_entry4_xbitmask_d, lrat_entry4_xbitmask_q : std_ulogic_vector(0 to 6); +signal lrat_entry4_xbit_d, lrat_entry4_xbit_q : std_ulogic; +signal lrat_entry4_valid_d, lrat_entry4_valid_q : std_ulogic; +signal lrat_entry5_lpn_d, lrat_entry5_lpn_q : std_ulogic_vector(64-real_addr_width to 64-lrat_minsize_log2-1); +signal lrat_entry5_rpn_d, lrat_entry5_rpn_q : std_ulogic_vector(64-real_addr_width to 64-lrat_minsize_log2-1); +signal lrat_entry5_lpid_d, lrat_entry5_lpid_q : std_ulogic_vector(0 to lpid_width-1); +signal lrat_entry5_size_d, lrat_entry5_size_q : std_ulogic_vector(0 to 3); +signal lrat_entry5_cmpmask_d, lrat_entry5_cmpmask_q : std_ulogic_vector(0 to 6); +signal lrat_entry5_xbitmask_d, lrat_entry5_xbitmask_q : std_ulogic_vector(0 to 6); +signal lrat_entry5_xbit_d, lrat_entry5_xbit_q : std_ulogic; +signal lrat_entry5_valid_d, lrat_entry5_valid_q : std_ulogic; +signal lrat_entry6_lpn_d, lrat_entry6_lpn_q : std_ulogic_vector(64-real_addr_width to 64-lrat_minsize_log2-1); +signal lrat_entry6_rpn_d, lrat_entry6_rpn_q : std_ulogic_vector(64-real_addr_width to 64-lrat_minsize_log2-1); +signal lrat_entry6_lpid_d, lrat_entry6_lpid_q : std_ulogic_vector(0 to lpid_width-1); +signal lrat_entry6_size_d, lrat_entry6_size_q : std_ulogic_vector(0 to 3); +signal lrat_entry6_cmpmask_d, lrat_entry6_cmpmask_q : std_ulogic_vector(0 to 6); +signal lrat_entry6_xbitmask_d, lrat_entry6_xbitmask_q : std_ulogic_vector(0 to 6); +signal lrat_entry6_xbit_d, lrat_entry6_xbit_q : std_ulogic; +signal lrat_entry6_valid_d, lrat_entry6_valid_q : std_ulogic; +signal lrat_entry7_lpn_d, lrat_entry7_lpn_q : std_ulogic_vector(64-real_addr_width to 64-lrat_minsize_log2-1); +signal lrat_entry7_rpn_d, lrat_entry7_rpn_q : std_ulogic_vector(64-real_addr_width to 64-lrat_minsize_log2-1); +signal lrat_entry7_lpid_d, lrat_entry7_lpid_q : std_ulogic_vector(0 to lpid_width-1); +signal lrat_entry7_size_d, lrat_entry7_size_q : std_ulogic_vector(0 to 3); +signal lrat_entry7_cmpmask_d, lrat_entry7_cmpmask_q : std_ulogic_vector(0 to 6); +signal lrat_entry7_xbitmask_d, lrat_entry7_xbitmask_q : std_ulogic_vector(0 to 6); +signal lrat_entry7_xbit_d, lrat_entry7_xbit_q : std_ulogic; +signal lrat_entry7_valid_d, lrat_entry7_valid_q : std_ulogic; +signal lrat_datain_lpn_d, lrat_datain_lpn_q : std_ulogic_vector(64-real_addr_width to 64-lrat_minsize_log2-1); +signal lrat_datain_rpn_d, lrat_datain_rpn_q : std_ulogic_vector(64-real_addr_width to 64-lrat_minsize_log2-1); +signal lrat_datain_lpid_d, lrat_datain_lpid_q : std_ulogic_vector(0 to lpid_width-1); +signal lrat_datain_size_d, lrat_datain_size_q : std_ulogic_vector(0 to 3); +signal lrat_datain_xbit_d, lrat_datain_xbit_q : std_ulogic; +signal lrat_datain_valid_d, lrat_datain_valid_q : std_ulogic; +signal lrat_mas1_v_d, lrat_mas1_v_q : std_ulogic; +signal lrat_mas1_tsize_d, lrat_mas1_tsize_q : std_ulogic_vector(0 to 3); +signal lrat_mas2_epn_d,lrat_mas2_epn_q : std_ulogic_vector(64-real_addr_width to 51); +signal lrat_mas3_rpnl_d,lrat_mas3_rpnl_q : std_ulogic_vector(32 to 51); +signal lrat_mas7_rpnu_d, lrat_mas7_rpnu_q : std_ulogic_vector(22 to 31); +signal lrat_mas8_tlpid_d, lrat_mas8_tlpid_q : std_ulogic_vector(0 to lpid_width-1); +signal lrat_mas_tlbre_d, lrat_mas_tlbre_q : std_ulogic; +signal lrat_mas_tlbsx_hit_d, lrat_mas_tlbsx_hit_q : std_ulogic; +signal lrat_mas_tlbsx_miss_d, lrat_mas_tlbsx_miss_q : std_ulogic; +signal lrat_mas_thdid_d, lrat_mas_thdid_q : std_ulogic_vector(0 to thdid_width-1); +signal lrat_mmucr3_x_d, lrat_mmucr3_x_q : std_ulogic; +signal lrat_entry_act_d, lrat_entry_act_q : std_ulogic_vector(0 to 7); +signal lrat_mas_act_d, lrat_mas_act_q : std_ulogic_vector(0 to 2); +signal lrat_datain_act_d, lrat_datain_act_q : std_ulogic_vector(0 to 1); +signal spare_q : std_ulogic_vector(0 to 63); +-- Logic signals +signal multihit : std_ulogic; +signal addr_enable : std_ulogic; +signal lpid_enable : std_ulogic; +signal lrat_supp_pgsize : std_ulogic; +signal lrat_tag2_size_gt_entry_size : std_ulogic; +signal lrat_tag1_matchline : std_ulogic_vector(0 to lrat_num_entry-1); +signal lrat_entry0_addr_match : std_ulogic; +signal lrat_entry0_lpid_match : std_ulogic; +signal lrat_entry1_addr_match : std_ulogic; +signal lrat_entry1_lpid_match : std_ulogic; +signal lrat_entry2_addr_match : std_ulogic; +signal lrat_entry2_lpid_match : std_ulogic; +signal lrat_entry3_addr_match : std_ulogic; +signal lrat_entry3_lpid_match : std_ulogic; +signal lrat_entry4_addr_match : std_ulogic; +signal lrat_entry4_lpid_match : std_ulogic; +signal lrat_entry5_addr_match : std_ulogic; +signal lrat_entry5_lpid_match : std_ulogic; +signal lrat_entry6_addr_match : std_ulogic; +signal lrat_entry6_lpid_match : std_ulogic; +signal lrat_entry7_addr_match : std_ulogic; +signal lrat_entry7_lpid_match : std_ulogic; +signal unused_dc : std_ulogic_vector(0 to 13); +-- synopsys translate_off +-- synopsys translate_on +-- Pervasive +signal pc_sg_1 : std_ulogic; +signal pc_sg_0 : std_ulogic; +signal pc_func_sl_thold_1 : std_ulogic; +signal pc_func_sl_thold_0 : std_ulogic; +signal pc_func_sl_thold_0_b : std_ulogic; +signal pc_func_slp_sl_thold_1 : std_ulogic; +signal pc_func_slp_sl_thold_0 : std_ulogic; +signal pc_func_slp_sl_thold_0_b : std_ulogic; +signal pc_func_sl_force : std_ulogic; +signal pc_func_slp_sl_force : std_ulogic; +signal siv : std_ulogic_vector(0 to scan_right); +signal sov : std_ulogic_vector(0 to scan_right); +signal tiup : std_ulogic; + BEGIN --@@ START OF EXECUTABLE CODE FOR MMQ_TLB_LRAT + +tiup <= '1'; +-- tag0 phase signals, tlbwe/re ex2, tlbsx/srx ex3 +tlb_addr_cap_d(1) <= tlb_tag0_addr_cap and ((tlb_tag0_type(tagpos_type_tlbsx) and tlb_tag0_atsel) or + tlb_tag0_type(tagpos_type_ptereload) or tlb_tag0_type(tagpos_type_tlbwe)); +lrat_tag1_size_d <= tlb_tag0_size when tlb_tag0_addr_cap='1' + else lrat_tag1_size_q; +gen32_lrat_tag1_lpn: if real_addr_width < 33 generate +lrat_tag1_lpn_d <= tlb_tag0_epn(64-real_addr_width to 51) when (tlb_tag0_addr_cap='1' and tlb_tag0_type(tagpos_type_tlbsx)='1') + else pte_tag0_lpn(64-real_addr_width to 51) when (tlb_tag0_addr_cap='1' and tlb_tag0_type(tagpos_type_ptereload)='1') + else mas3_3_rpnl when (tlb_tag0_addr_cap='1' and tlb_tag0_thdid(3)='1' and tlb_tag0_type(tagpos_type_tlbwe)='1') + else mas3_2_rpnl when (tlb_tag0_addr_cap='1' and tlb_tag0_thdid(2)='1' and tlb_tag0_type(tagpos_type_tlbwe)='1') + else mas3_1_rpnl when (tlb_tag0_addr_cap='1' and tlb_tag0_thdid(1)='1' and tlb_tag0_type(tagpos_type_tlbwe)='1') + else mas3_0_rpnl when (tlb_tag0_addr_cap='1' and tlb_tag0_thdid(0)='1' and tlb_tag0_type(tagpos_type_tlbwe)='1') + else lrat_tag1_lpn_q; +end generate gen32_lrat_tag1_lpn; +gen64_lrat_tag1_lpn: if real_addr_width > 32 generate +lrat_tag1_lpn_d <= tlb_tag0_epn(64-real_addr_width to 51) when (tlb_tag0_addr_cap='1' and tlb_tag0_type(tagpos_type_tlbsx)='1') + else pte_tag0_lpn(64-real_addr_width to 51) when (tlb_tag0_addr_cap='1' and tlb_tag0_type(tagpos_type_ptereload)='1') + else mas7_3_rpnu(64-real_addr_width to 31) & mas3_3_rpnl when (tlb_tag0_addr_cap='1' and tlb_tag0_thdid(3)='1' and tlb_tag0_type(tagpos_type_tlbwe)='1') + else mas7_2_rpnu(64-real_addr_width to 31) & mas3_2_rpnl when (tlb_tag0_addr_cap='1' and tlb_tag0_thdid(2)='1' and tlb_tag0_type(tagpos_type_tlbwe)='1') + else mas7_1_rpnu(64-real_addr_width to 31) & mas3_1_rpnl when (tlb_tag0_addr_cap='1' and tlb_tag0_thdid(1)='1' and tlb_tag0_type(tagpos_type_tlbwe)='1') + else mas7_0_rpnu(64-real_addr_width to 31) & mas3_0_rpnl when (tlb_tag0_addr_cap='1' and tlb_tag0_thdid(0)='1' and tlb_tag0_type(tagpos_type_tlbwe)='1') + else lrat_tag1_lpn_q; +end generate gen64_lrat_tag1_lpn; +lrat_tag1_lpid_d <= tlb_tag0_lpid when (tlb_tag0_addr_cap='1' and tlb_tag0_type(tagpos_type_tlbsx)='1') + else pte_tag0_lpid when (tlb_tag0_addr_cap='1' and tlb_tag0_type(tagpos_type_ptereload)='1') + else mas8_3_tlpid when (tlb_tag0_addr_cap='1' and tlb_tag0_thdid(3)='1' and tlb_tag0_type(tagpos_type_tlbwe)='1') + else mas8_2_tlpid when (tlb_tag0_addr_cap='1' and tlb_tag0_thdid(2)='1' and tlb_tag0_type(tagpos_type_tlbwe)='1') + else mas8_1_tlpid when (tlb_tag0_addr_cap='1' and tlb_tag0_thdid(1)='1' and tlb_tag0_type(tagpos_type_tlbwe)='1') + else mas8_0_tlpid when (tlb_tag0_addr_cap='1' and tlb_tag0_thdid(0)='1' and tlb_tag0_type(tagpos_type_tlbwe)='1') + else lrat_tag1_lpid_q; +-- tag1 phase signals, tlbwe/re ex3, tlbsx/srx ex4 +ex4_valid_d <= tlb_ctl_ex3_valid and not(xu_ex3_flush); +ex4_ttype_d <= tlb_ctl_ex3_ttype; +addr_enable <= tlb_addr_cap_q(1); +lpid_enable <= tlb_addr_cap_q(1); +tlb_addr_cap_d(2) <= tlb_addr_cap_q(1); +lrat_tag2_lpn_d <= lrat_tag1_lpn_q; +lrat_tag2_matchline_d <= lrat_tag1_matchline; +lrat_tag2_size_d <= lrat_tag1_size_q; +lrat_tag2_entry_size_d <= + (lrat_entry0_size_q and (0 to 3 => lrat_tag1_matchline(0))) or + (lrat_entry1_size_q and (0 to 3 => lrat_tag1_matchline(1))) or + (lrat_entry2_size_q and (0 to 3 => lrat_tag1_matchline(2))) or + (lrat_entry3_size_q and (0 to 3 => lrat_tag1_matchline(3))) or + (lrat_entry4_size_q and (0 to 3 => lrat_tag1_matchline(4))) or + (lrat_entry5_size_q and (0 to 3 => lrat_tag1_matchline(5))) or + (lrat_entry6_size_q and (0 to 3 => lrat_tag1_matchline(6))) or + (lrat_entry7_size_q and (0 to 3 => lrat_tag1_matchline(7))); +-- tag2 phase signals, tlbwe/re ex4, tlbsx/srx ex5 +ex5_valid_d <= ex4_valid_q and not(xu_ex4_flush); +ex5_ttype_d <= ex4_ttype_q; +ex5_esel_d <= mas0_1_esel when ex4_valid_q(1)='1' + else mas0_2_esel when ex4_valid_q(2)='1' + else mas0_3_esel when ex4_valid_q(3)='1' + else mas0_0_esel; +ex5_atsel_d <= mas0_1_atsel when ex4_valid_q(1)='1' + else mas0_2_atsel when ex4_valid_q(2)='1' + else mas0_3_atsel when ex4_valid_q(3)='1' + else mas0_0_atsel; +ex5_hes_d <= mas0_1_hes when ex4_valid_q(1)='1' + else mas0_2_hes when ex4_valid_q(2)='1' + else mas0_3_hes when ex4_valid_q(3)='1' + else mas0_0_hes; +ex5_wq_d <= mas0_1_wq when ex4_valid_q(1)='1' + else mas0_2_wq when ex4_valid_q(2)='1' + else mas0_3_wq when ex4_valid_q(3)='1' + else mas0_0_wq; +lrat_tag3_lpn_d <= lrat_tag2_lpn_q; +-- hit_status: val,hit,multihit,inval_pgsize +lrat_tag3_hit_status_d(0) <= tlb_addr_cap_q(2); +lrat_tag3_hit_status_d(1) <= tlb_addr_cap_q(2) and or_reduce(lrat_tag2_matchline_q(0 to lrat_num_entry-1)); +lrat_tag3_hit_status_d(2) <= tlb_addr_cap_q(2) and multihit; +lrat_tag3_hit_status_d(3) <= tlb_addr_cap_q(2) and (not(lrat_supp_pgsize) or lrat_tag2_size_gt_entry_size); +multihit <= '0' when (lrat_tag2_matchline_q(0 to lrat_num_entry-1)="00000000" or + lrat_tag2_matchline_q(0 to lrat_num_entry-1)="10000000" or + lrat_tag2_matchline_q(0 to lrat_num_entry-1)="01000000" or + lrat_tag2_matchline_q(0 to lrat_num_entry-1)="00100000" or + lrat_tag2_matchline_q(0 to lrat_num_entry-1)="00010000" or + lrat_tag2_matchline_q(0 to lrat_num_entry-1)="00001000" or + lrat_tag2_matchline_q(0 to lrat_num_entry-1)="00000100" or + lrat_tag2_matchline_q(0 to lrat_num_entry-1)="00000010" or + lrat_tag2_matchline_q(0 to lrat_num_entry-1)="00000001") + else '1'; +lrat_tag3_hit_entry_d <= "001" when lrat_tag2_matchline_q(0 to lrat_num_entry-1)="01000000" + else "010" when lrat_tag2_matchline_q(0 to lrat_num_entry-1)="00100000" + else "011" when lrat_tag2_matchline_q(0 to lrat_num_entry-1)="00010000" + else "100" when lrat_tag2_matchline_q(0 to lrat_num_entry-1)="00001000" + else "101" when lrat_tag2_matchline_q(0 to lrat_num_entry-1)="00000100" + else "110" when lrat_tag2_matchline_q(0 to lrat_num_entry-1)="00000010" + else "111" when lrat_tag2_matchline_q(0 to lrat_num_entry-1)="00000001" + else "000"; +-- constant TLB_PgSize_1GB : std_ulogic_vector(0 to 3) := 1010 ; +-- constant TLB_PgSize_256MB : std_ulogic_vector(0 to 3) := 1001 ; +-- constant TLB_PgSize_16MB : std_ulogic_vector(0 to 3) := 0111 ; +-- constant TLB_PgSize_1MB : std_ulogic_vector(0 to 3) := 0101 ; +-- constant TLB_PgSize_64KB : std_ulogic_vector(0 to 3) := 0011 ; +-- constant TLB_PgSize_4KB : std_ulogic_vector(0 to 3) := 0001 ; +-- ISA 2.06 pgsize match criteria for tlbwe: +-- MAS1.IND=0 and MAS1.TSIZE 10+5 +-- ..in other words, the biggest page table for A2 is 256M/64K=4K entries x 8 bytes = 32K, +-- .. 32K is always less than the minimum supported LRAT size of 1MB. +-- pgsize match criteria for ptereload: +-- PTE.PS 33 generate +-- rpn(30:31) +lrat_tag3_rpn_d(64-LRAT_PgSize_16GB_log2 TO 64-LRAT_PgSize_4GB_log2-1) <= + lrat_entry0_rpn_q(64-LRAT_PgSize_16GB_log2 to 64-LRAT_PgSize_4GB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB or lrat_tag2_entry_size_q=LRAT_PgSize_1GB or + lrat_tag2_entry_size_q=LRAT_PgSize_4GB) and lrat_tag2_matchline_q(0)='1') + else lrat_entry1_rpn_q(64-LRAT_PgSize_16GB_log2 to 64-LRAT_PgSize_4GB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB or lrat_tag2_entry_size_q=LRAT_PgSize_1GB or + lrat_tag2_entry_size_q=LRAT_PgSize_4GB) and lrat_tag2_matchline_q(1)='1') + else lrat_entry2_rpn_q(64-LRAT_PgSize_16GB_log2 to 64-LRAT_PgSize_4GB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB or lrat_tag2_entry_size_q=LRAT_PgSize_1GB or + lrat_tag2_entry_size_q=LRAT_PgSize_4GB) and lrat_tag2_matchline_q(2)='1') + else lrat_entry3_rpn_q(64-LRAT_PgSize_16GB_log2 to 64-LRAT_PgSize_4GB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB or lrat_tag2_entry_size_q=LRAT_PgSize_1GB or + lrat_tag2_entry_size_q=LRAT_PgSize_4GB) and lrat_tag2_matchline_q(3)='1') + else lrat_entry4_rpn_q(64-LRAT_PgSize_16GB_log2 to 64-LRAT_PgSize_4GB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB or lrat_tag2_entry_size_q=LRAT_PgSize_1GB or + lrat_tag2_entry_size_q=LRAT_PgSize_4GB) and lrat_tag2_matchline_q(4)='1') + else lrat_entry5_rpn_q(64-LRAT_PgSize_16GB_log2 to 64-LRAT_PgSize_4GB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB or lrat_tag2_entry_size_q=LRAT_PgSize_1GB or + lrat_tag2_entry_size_q=LRAT_PgSize_4GB) and lrat_tag2_matchline_q(5)='1') + else lrat_entry6_rpn_q(64-LRAT_PgSize_16GB_log2 to 64-LRAT_PgSize_4GB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB or lrat_tag2_entry_size_q=LRAT_PgSize_1GB or + lrat_tag2_entry_size_q=LRAT_PgSize_4GB) and lrat_tag2_matchline_q(6)='1') + else lrat_entry7_rpn_q(64-LRAT_PgSize_16GB_log2 to 64-LRAT_PgSize_4GB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB or lrat_tag2_entry_size_q=LRAT_PgSize_1GB or + lrat_tag2_entry_size_q=LRAT_PgSize_4GB) and lrat_tag2_matchline_q(7)='1') + else lrat_tag2_lpn_q(64-LRAT_PgSize_16GB_log2 to 64-LRAT_PgSize_4GB_log2-1); +end generate gen64_lrat_tag3_rpn_34; +gen64_lrat_tag3_rpn_38: if real_addr_width > 37 generate +-- rpn(26:29) +lrat_tag3_rpn_d(64-LRAT_PgSize_256GB_log2 TO 64-LRAT_PgSize_16GB_log2-1) <= + lrat_entry0_rpn_q(64-LRAT_PgSize_256GB_log2 to 64-LRAT_PgSize_16GB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB or lrat_tag2_entry_size_q=LRAT_PgSize_1GB or + lrat_tag2_entry_size_q=LRAT_PgSize_4GB or lrat_tag2_entry_size_q=LRAT_PgSize_16GB) and lrat_tag2_matchline_q(0)='1') + else lrat_entry1_rpn_q(64-LRAT_PgSize_256GB_log2 to 64-LRAT_PgSize_16GB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB or lrat_tag2_entry_size_q=LRAT_PgSize_1GB or + lrat_tag2_entry_size_q=LRAT_PgSize_4GB or lrat_tag2_entry_size_q=LRAT_PgSize_16GB) and lrat_tag2_matchline_q(1)='1') + else lrat_entry2_rpn_q(64-LRAT_PgSize_256GB_log2 to 64-LRAT_PgSize_16GB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB or lrat_tag2_entry_size_q=LRAT_PgSize_1GB or + lrat_tag2_entry_size_q=LRAT_PgSize_4GB or lrat_tag2_entry_size_q=LRAT_PgSize_16GB) and lrat_tag2_matchline_q(2)='1') + else lrat_entry3_rpn_q(64-LRAT_PgSize_256GB_log2 to 64-LRAT_PgSize_16GB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB or lrat_tag2_entry_size_q=LRAT_PgSize_1GB or + lrat_tag2_entry_size_q=LRAT_PgSize_4GB or lrat_tag2_entry_size_q=LRAT_PgSize_16GB) and lrat_tag2_matchline_q(3)='1') + else lrat_entry4_rpn_q(64-LRAT_PgSize_256GB_log2 to 64-LRAT_PgSize_16GB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB or lrat_tag2_entry_size_q=LRAT_PgSize_1GB or + lrat_tag2_entry_size_q=LRAT_PgSize_4GB or lrat_tag2_entry_size_q=LRAT_PgSize_16GB) and lrat_tag2_matchline_q(4)='1') + else lrat_entry5_rpn_q(64-LRAT_PgSize_256GB_log2 to 64-LRAT_PgSize_16GB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB or lrat_tag2_entry_size_q=LRAT_PgSize_1GB or + lrat_tag2_entry_size_q=LRAT_PgSize_4GB or lrat_tag2_entry_size_q=LRAT_PgSize_16GB) and lrat_tag2_matchline_q(5)='1') + else lrat_entry6_rpn_q(64-LRAT_PgSize_256GB_log2 to 64-LRAT_PgSize_16GB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB or lrat_tag2_entry_size_q=LRAT_PgSize_1GB or + lrat_tag2_entry_size_q=LRAT_PgSize_4GB or lrat_tag2_entry_size_q=LRAT_PgSize_16GB) and lrat_tag2_matchline_q(6)='1') + else lrat_entry7_rpn_q(64-LRAT_PgSize_256GB_log2 to 64-LRAT_PgSize_16GB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB or lrat_tag2_entry_size_q=LRAT_PgSize_1GB or + lrat_tag2_entry_size_q=LRAT_PgSize_4GB or lrat_tag2_entry_size_q=LRAT_PgSize_16GB) and lrat_tag2_matchline_q(7)='1') + else lrat_tag2_lpn_q(64-LRAT_PgSize_256GB_log2 to 64-LRAT_PgSize_16GB_log2-1); +end generate gen64_lrat_tag3_rpn_38; +gen64_lrat_tag3_rpn_40: if real_addr_width > 39 generate +-- rpn(24:25) +lrat_tag3_rpn_d(64-LRAT_PgSize_1TB_log2 TO 64-LRAT_PgSize_256GB_log2-1) <= + lrat_entry0_rpn_q(64-LRAT_PgSize_1TB_log2 to 64-LRAT_PgSize_256GB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB or lrat_tag2_entry_size_q=LRAT_PgSize_1GB or + lrat_tag2_entry_size_q=LRAT_PgSize_4GB or lrat_tag2_entry_size_q=LRAT_PgSize_16GB or + lrat_tag2_entry_size_q=LRAT_PgSize_256GB) and lrat_tag2_matchline_q(0)='1') + else lrat_entry1_rpn_q(64-LRAT_PgSize_1TB_log2 to 64-LRAT_PgSize_256GB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB or lrat_tag2_entry_size_q=LRAT_PgSize_1GB or + lrat_tag2_entry_size_q=LRAT_PgSize_4GB or lrat_tag2_entry_size_q=LRAT_PgSize_16GB or + lrat_tag2_entry_size_q=LRAT_PgSize_256GB) and lrat_tag2_matchline_q(1)='1') + else lrat_entry2_rpn_q(64-LRAT_PgSize_1TB_log2 to 64-LRAT_PgSize_256GB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB or lrat_tag2_entry_size_q=LRAT_PgSize_1GB or + lrat_tag2_entry_size_q=LRAT_PgSize_4GB or lrat_tag2_entry_size_q=LRAT_PgSize_16GB or + lrat_tag2_entry_size_q=LRAT_PgSize_256GB) and lrat_tag2_matchline_q(2)='1') + else lrat_entry3_rpn_q(64-LRAT_PgSize_1TB_log2 to 64-LRAT_PgSize_256GB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB or lrat_tag2_entry_size_q=LRAT_PgSize_1GB or + lrat_tag2_entry_size_q=LRAT_PgSize_4GB or lrat_tag2_entry_size_q=LRAT_PgSize_16GB or + lrat_tag2_entry_size_q=LRAT_PgSize_256GB) and lrat_tag2_matchline_q(3)='1') + else lrat_entry4_rpn_q(64-LRAT_PgSize_1TB_log2 to 64-LRAT_PgSize_256GB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB or lrat_tag2_entry_size_q=LRAT_PgSize_1GB or + lrat_tag2_entry_size_q=LRAT_PgSize_4GB or lrat_tag2_entry_size_q=LRAT_PgSize_16GB or + lrat_tag2_entry_size_q=LRAT_PgSize_256GB) and lrat_tag2_matchline_q(4)='1') + else lrat_entry5_rpn_q(64-LRAT_PgSize_1TB_log2 to 64-LRAT_PgSize_256GB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB or lrat_tag2_entry_size_q=LRAT_PgSize_1GB or + lrat_tag2_entry_size_q=LRAT_PgSize_4GB or lrat_tag2_entry_size_q=LRAT_PgSize_16GB or + lrat_tag2_entry_size_q=LRAT_PgSize_256GB) and lrat_tag2_matchline_q(5)='1') + else lrat_entry6_rpn_q(64-LRAT_PgSize_1TB_log2 to 64-LRAT_PgSize_256GB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB or lrat_tag2_entry_size_q=LRAT_PgSize_1GB or + lrat_tag2_entry_size_q=LRAT_PgSize_4GB or lrat_tag2_entry_size_q=LRAT_PgSize_16GB or + lrat_tag2_entry_size_q=LRAT_PgSize_256GB) and lrat_tag2_matchline_q(6)='1') + else lrat_entry7_rpn_q(64-LRAT_PgSize_1TB_log2 to 64-LRAT_PgSize_256GB_log2-1) + when ((lrat_tag2_entry_size_q=LRAT_PgSize_1MB or lrat_tag2_entry_size_q=LRAT_PgSize_16MB or + lrat_tag2_entry_size_q=LRAT_PgSize_256MB or lrat_tag2_entry_size_q=LRAT_PgSize_1GB or + lrat_tag2_entry_size_q=LRAT_PgSize_4GB or lrat_tag2_entry_size_q=LRAT_PgSize_16GB or + lrat_tag2_entry_size_q=LRAT_PgSize_256GB) and lrat_tag2_matchline_q(7)='1') + else lrat_tag2_lpn_q(64-LRAT_PgSize_1TB_log2 to 64-LRAT_PgSize_256GB_log2-1); +end generate gen64_lrat_tag3_rpn_40; +gen64_lrat_tag3_rpn_42: if real_addr_width > 41 generate +-- rpn(22:23) +lrat_tag3_rpn_d(64-real_addr_width TO 64-lrat_maxsize_log2-1) <= + lrat_entry0_rpn_q(64-real_addr_width to 64-lrat_maxsize_log2-1) when lrat_tag2_matchline_q(0)='1' + else lrat_entry1_rpn_q(64-real_addr_width to 64-lrat_maxsize_log2-1) when lrat_tag2_matchline_q(1)='1' + else lrat_entry2_rpn_q(64-real_addr_width to 64-lrat_maxsize_log2-1) when lrat_tag2_matchline_q(2)='1' + else lrat_entry3_rpn_q(64-real_addr_width to 64-lrat_maxsize_log2-1) when lrat_tag2_matchline_q(3)='1' + else lrat_entry4_rpn_q(64-real_addr_width to 64-lrat_maxsize_log2-1) when lrat_tag2_matchline_q(4)='1' + else lrat_entry5_rpn_q(64-real_addr_width to 64-lrat_maxsize_log2-1) when lrat_tag2_matchline_q(5)='1' + else lrat_entry6_rpn_q(64-real_addr_width to 64-lrat_maxsize_log2-1) when lrat_tag2_matchline_q(6)='1' + else lrat_entry7_rpn_q(64-real_addr_width to 64-lrat_maxsize_log2-1) when lrat_tag2_matchline_q(7)='1' + else lrat_tag2_lpn_q(64-real_addr_width to 64-lrat_maxsize_log2-1); +end generate gen64_lrat_tag3_rpn_42; +--constant LRAT_PgSize_1TB_log2 : integer := 40; +--constant LRAT_PgSize_256GB_log2 : integer := 38; +--constant LRAT_PgSize_16GB_log2 : integer := 34; +--constant LRAT_PgSize_4GB_log2 : integer := 32; +--constant LRAT_PgSize_1GB_log2 : integer := 30; +--constant LRAT_PgSize_256MB_log2 : integer := 28; +--constant LRAT_PgSize_16MB_log2 : integer := 24; +--constant LRAT_PgSize_1MB_log2 : integer := 20; +-- tag3 phase signals, tlbwe/re ex4, tlbsx/srx ex5 +ex6_valid_d <= ex5_valid_q and not(xu_ex5_flush); +ex6_ttype_d <= ex5_ttype_q; +ex6_esel_d <= ex5_esel_q; +ex6_atsel_d <= ex5_atsel_q; +ex6_hes_d <= ex5_hes_q; +ex6_wq_d <= ex5_wq_q; +lrat_tag4_lpn_d <= lrat_tag3_lpn_q; +lrat_tag4_rpn_d <= lrat_tag3_rpn_q; +lrat_tag4_hit_status_d <= lrat_tag3_hit_status_q; +lrat_tag4_hit_entry_d <= lrat_tag3_hit_entry_q; +lrat_datain_lpn_d <= mas2_0_epn(64-real_addr_width to 63-lrat_minsize_log2) when (ex5_valid_q(0)='1') + else mas2_1_epn(64-real_addr_width to 63-lrat_minsize_log2) when (ex5_valid_q(1)='1') + else mas2_2_epn(64-real_addr_width to 63-lrat_minsize_log2) when (ex5_valid_q(2)='1') + else mas2_3_epn(64-real_addr_width to 63-lrat_minsize_log2) when (ex5_valid_q(3)='1') + else lrat_datain_lpn_q; +gen64_lrat_datain_rpn: if real_addr_width > 32 generate +lrat_datain_rpn_d(64-real_addr_width TO 31) <= mas7_0_rpnu(64-real_addr_width to 31) when (ex5_valid_q(0)='1') + else mas7_1_rpnu(64-real_addr_width to 31) when (ex5_valid_q(1)='1') + else mas7_2_rpnu(64-real_addr_width to 31) when (ex5_valid_q(2)='1') + else mas7_3_rpnu(64-real_addr_width to 31) when (ex5_valid_q(3)='1') + else lrat_datain_rpn_q(64-real_addr_width to 31); +end generate gen64_lrat_datain_rpn; +lrat_datain_rpn_d(32 TO 63-lrat_minsize_log2) <= mas3_0_rpnl(32 to 63-lrat_minsize_log2) when (ex5_valid_q(0)='1') + else mas3_1_rpnl(32 to 63-lrat_minsize_log2) when (ex5_valid_q(1)='1') + else mas3_2_rpnl(32 to 63-lrat_minsize_log2) when (ex5_valid_q(2)='1') + else mas3_3_rpnl(32 to 63-lrat_minsize_log2) when (ex5_valid_q(3)='1') + else lrat_datain_rpn_q(32 to 63-lrat_minsize_log2); +lrat_datain_lpid_d <= mas8_0_tlpid when (ex5_valid_q(0)='1') + else mas8_1_tlpid when (ex5_valid_q(1)='1') + else mas8_2_tlpid when (ex5_valid_q(2)='1') + else mas8_3_tlpid when (ex5_valid_q(3)='1') + else lrat_datain_lpid_q; +lrat_datain_size_d <= mas1_0_tsize when (ex5_valid_q(0)='1') + else mas1_1_tsize when (ex5_valid_q(1)='1') + else mas1_2_tsize when (ex5_valid_q(2)='1') + else mas1_3_tsize when (ex5_valid_q(3)='1') + else lrat_datain_size_q; +lrat_datain_valid_d <= mas1_0_v when (ex5_valid_q(0)='1') + else mas1_1_v when (ex5_valid_q(1)='1') + else mas1_2_v when (ex5_valid_q(2)='1') + else mas1_3_v when (ex5_valid_q(3)='1') + else lrat_datain_valid_q; +lrat_datain_xbit_d <= mmucr3_0_x when (ex5_valid_q(0)='1') + else mmucr3_1_x when (ex5_valid_q(1)='1') + else mmucr3_2_x when (ex5_valid_q(2)='1') + else mmucr3_3_x when (ex5_valid_q(3)='1') + else lrat_datain_xbit_q; +lrat_mmucr3_x_d <= lrat_entry0_xbit_q when (ex5_valid_q/="0000" and ex5_esel_q="000") + else lrat_entry1_xbit_q when (ex5_valid_q/="0000" and ex5_esel_q="001") + else lrat_entry2_xbit_q when (ex5_valid_q/="0000" and ex5_esel_q="010") + else lrat_entry3_xbit_q when (ex5_valid_q/="0000" and ex5_esel_q="011") + else lrat_entry4_xbit_q when (ex5_valid_q/="0000" and ex5_esel_q="100") + else lrat_entry5_xbit_q when (ex5_valid_q/="0000" and ex5_esel_q="101") + else lrat_entry6_xbit_q when (ex5_valid_q/="0000" and ex5_esel_q="110") + else lrat_entry7_xbit_q when (ex5_valid_q/="0000" and ex5_esel_q="111") + else lrat_mmucr3_x_q; +lrat_mas1_v_d <= lrat_entry0_valid_q when (ex5_valid_q/="0000" and ex5_esel_q="000") + else lrat_entry1_valid_q when (ex5_valid_q/="0000" and ex5_esel_q="001") + else lrat_entry2_valid_q when (ex5_valid_q/="0000" and ex5_esel_q="010") + else lrat_entry3_valid_q when (ex5_valid_q/="0000" and ex5_esel_q="011") + else lrat_entry4_valid_q when (ex5_valid_q/="0000" and ex5_esel_q="100") + else lrat_entry5_valid_q when (ex5_valid_q/="0000" and ex5_esel_q="101") + else lrat_entry6_valid_q when (ex5_valid_q/="0000" and ex5_esel_q="110") + else lrat_entry7_valid_q when (ex5_valid_q/="0000" and ex5_esel_q="111") + else lrat_mas1_v_q; +lrat_mas1_tsize_d <= lrat_entry0_size_q when (ex5_valid_q/="0000" and ex5_esel_q="000") + else lrat_entry1_size_q when (ex5_valid_q/="0000" and ex5_esel_q="001") + else lrat_entry2_size_q when (ex5_valid_q/="0000" and ex5_esel_q="010") + else lrat_entry3_size_q when (ex5_valid_q/="0000" and ex5_esel_q="011") + else lrat_entry4_size_q when (ex5_valid_q/="0000" and ex5_esel_q="100") + else lrat_entry5_size_q when (ex5_valid_q/="0000" and ex5_esel_q="101") + else lrat_entry6_size_q when (ex5_valid_q/="0000" and ex5_esel_q="110") + else lrat_entry7_size_q when (ex5_valid_q/="0000" and ex5_esel_q="111") + else lrat_mas1_tsize_q; +lrat_mas2_epn_d(64-real_addr_width TO 64-lrat_minsize_log2-1) <= + lrat_entry0_lpn_q(64-real_addr_width to 64-lrat_minsize_log2-1) when (ex5_valid_q/="0000" and ex5_esel_q="000") + else lrat_entry1_lpn_q(64-real_addr_width to 64-lrat_minsize_log2-1) when (ex5_valid_q/="0000" and ex5_esel_q="001") + else lrat_entry2_lpn_q(64-real_addr_width to 64-lrat_minsize_log2-1) when (ex5_valid_q/="0000" and ex5_esel_q="010") + else lrat_entry3_lpn_q(64-real_addr_width to 64-lrat_minsize_log2-1) when (ex5_valid_q/="0000" and ex5_esel_q="011") + else lrat_entry4_lpn_q(64-real_addr_width to 64-lrat_minsize_log2-1) when (ex5_valid_q/="0000" and ex5_esel_q="100") + else lrat_entry5_lpn_q(64-real_addr_width to 64-lrat_minsize_log2-1) when (ex5_valid_q/="0000" and ex5_esel_q="101") + else lrat_entry6_lpn_q(64-real_addr_width to 64-lrat_minsize_log2-1) when (ex5_valid_q/="0000" and ex5_esel_q="110") + else lrat_entry7_lpn_q(64-real_addr_width to 64-lrat_minsize_log2-1) when (ex5_valid_q/="0000" and ex5_esel_q="111") + else lrat_mas2_epn_q(64-real_addr_width to 64-lrat_minsize_log2-1); +lrat_mas2_epn_d(64-lrat_minsize_log2 TO 51) <= + (others => '0') when (ex5_valid_q/="0000" and ex5_esel_q="000") + else (others => '0') when (ex5_valid_q/="0000" and ex5_esel_q="001") + else (others => '0') when (ex5_valid_q/="0000" and ex5_esel_q="010") + else (others => '0') when (ex5_valid_q/="0000" and ex5_esel_q="011") + else (others => '0') when (ex5_valid_q/="0000" and ex5_esel_q="100") + else (others => '0') when (ex5_valid_q/="0000" and ex5_esel_q="101") + else (others => '0') when (ex5_valid_q/="0000" and ex5_esel_q="110") + else (others => '0') when (ex5_valid_q/="0000" and ex5_esel_q="111") + else lrat_mas2_epn_q(64-lrat_minsize_log2 to 51); +lrat_mas3_rpnl_d(32 TO 64-lrat_minsize_log2-1) <= + lrat_entry0_rpn_q(32 to 64-lrat_minsize_log2-1) when (ex5_valid_q/="0000" and ex5_esel_q="000") + else lrat_entry1_rpn_q(32 to 64-lrat_minsize_log2-1) when (ex5_valid_q/="0000" and ex5_esel_q="001") + else lrat_entry2_rpn_q(32 to 64-lrat_minsize_log2-1) when (ex5_valid_q/="0000" and ex5_esel_q="010") + else lrat_entry3_rpn_q(32 to 64-lrat_minsize_log2-1) when (ex5_valid_q/="0000" and ex5_esel_q="011") + else lrat_entry4_rpn_q(32 to 64-lrat_minsize_log2-1) when (ex5_valid_q/="0000" and ex5_esel_q="100") + else lrat_entry5_rpn_q(32 to 64-lrat_minsize_log2-1) when (ex5_valid_q/="0000" and ex5_esel_q="101") + else lrat_entry6_rpn_q(32 to 64-lrat_minsize_log2-1) when (ex5_valid_q/="0000" and ex5_esel_q="110") + else lrat_entry7_rpn_q(32 to 64-lrat_minsize_log2-1) when (ex5_valid_q/="0000" and ex5_esel_q="111") + else lrat_mas3_rpnl_q(32 to 64-lrat_minsize_log2-1); +lrat_mas3_rpnl_d(64-lrat_minsize_log2 TO 51) <= + (others => '0') when (ex5_valid_q/="0000" and ex5_esel_q="000") + else (others => '0') when (ex5_valid_q/="0000" and ex5_esel_q="001") + else (others => '0') when (ex5_valid_q/="0000" and ex5_esel_q="010") + else (others => '0') when (ex5_valid_q/="0000" and ex5_esel_q="011") + else (others => '0') when (ex5_valid_q/="0000" and ex5_esel_q="100") + else (others => '0') when (ex5_valid_q/="0000" and ex5_esel_q="101") + else (others => '0') when (ex5_valid_q/="0000" and ex5_esel_q="110") + else (others => '0') when (ex5_valid_q/="0000" and ex5_esel_q="111") + else lrat_mas3_rpnl_q(64-lrat_minsize_log2 to 51); +lrat_mas7_rpnu_d(64-real_addr_width TO 31) <= + lrat_entry0_rpn_q(64-real_addr_width to 31) when (ex5_valid_q/="0000" and ex5_esel_q="000") + else lrat_entry1_rpn_q(64-real_addr_width to 31) when (ex5_valid_q/="0000" and ex5_esel_q="001") + else lrat_entry2_rpn_q(64-real_addr_width to 31) when (ex5_valid_q/="0000" and ex5_esel_q="010") + else lrat_entry3_rpn_q(64-real_addr_width to 31) when (ex5_valid_q/="0000" and ex5_esel_q="011") + else lrat_entry4_rpn_q(64-real_addr_width to 31) when (ex5_valid_q/="0000" and ex5_esel_q="100") + else lrat_entry5_rpn_q(64-real_addr_width to 31) when (ex5_valid_q/="0000" and ex5_esel_q="101") + else lrat_entry6_rpn_q(64-real_addr_width to 31) when (ex5_valid_q/="0000" and ex5_esel_q="110") + else lrat_entry7_rpn_q(64-real_addr_width to 31) when (ex5_valid_q/="0000" and ex5_esel_q="111") + else lrat_mas7_rpnu_q(64-real_addr_width to 31); +lrat_mas8_tlpid_d <= lrat_entry0_lpid_q when (ex5_valid_q/="0000" and ex5_esel_q="000") + else lrat_entry1_lpid_q when (ex5_valid_q/="0000" and ex5_esel_q="001") + else lrat_entry2_lpid_q when (ex5_valid_q/="0000" and ex5_esel_q="010") + else lrat_entry3_lpid_q when (ex5_valid_q/="0000" and ex5_esel_q="011") + else lrat_entry4_lpid_q when (ex5_valid_q/="0000" and ex5_esel_q="100") + else lrat_entry5_lpid_q when (ex5_valid_q/="0000" and ex5_esel_q="101") + else lrat_entry6_lpid_q when (ex5_valid_q/="0000" and ex5_esel_q="110") + else lrat_entry7_lpid_q when (ex5_valid_q/="0000" and ex5_esel_q="111") + else lrat_mas8_tlpid_q; +-- ttype -> tlbre,tlbwe,tlbsx,tlbsxr,tlbsrx +lrat_mas_tlbre_d <= '1' when ((ex5_valid_q and not(xu_ex5_flush))/="0000" + and ex5_ttype_q(0)='1' and ex5_atsel_q='1') + else '0'; +lrat_mas_tlbsx_hit_d <= '1' when (ex6_valid_q/="0000" and ex6_ttype_q(2 to 4)/="000" and ex6_ttype_q(0)='1' + and ex6_atsel_q='1' and lrat_tag3_hit_status_q(1)='1') + else '0'; +lrat_mas_tlbsx_miss_d <= '1' when (ex6_valid_q/="0000" and ex6_ttype_q(2 to 4)/="000" and ex6_ttype_q(0)='1' + and ex6_atsel_q='1' and lrat_tag3_hit_status_q(1)='0') + else '0'; +lrat_mas_thdid_d(0 TO thdid_width-1) <= (ex5_valid_q and (0 to thdid_width-1 => ex5_ttype_q(0))) + or (ex6_valid_q and (0 to thdid_width-1 => or_reduce(ex6_ttype_q(2 to 4)))); +-- power clock gating +lrat_mas_act_d(0) <= ((or_reduce(ex4_valid_q) and or_reduce(ex4_ttype_q)) or mmucr2_act_override) and xu_mm_ccr2_notlb_b; +lrat_mas_act_d(1) <= ((or_reduce(ex4_valid_q) and or_reduce(ex4_ttype_q)) or mmucr2_act_override) and xu_mm_ccr2_notlb_b; +lrat_mas_act_d(2) <= (((or_reduce(ex4_valid_q) and or_reduce(ex4_ttype_q)) or mmucr2_act_override) and xu_mm_ccr2_notlb_b) or + (((or_reduce(ex5_valid_q) and or_reduce(ex5_ttype_q)) or mmucr2_act_override) and xu_mm_ccr2_notlb_b) or + (((or_reduce(ex6_valid_q) and or_reduce(ex6_ttype_q)) or mmucr2_act_override) and xu_mm_ccr2_notlb_b); +lrat_datain_act_d(0) <= ((or_reduce(ex4_valid_q) and or_reduce(ex4_ttype_q)) or mmucr2_act_override) and xu_mm_ccr2_notlb_b; +lrat_datain_act_d(1) <= ((or_reduce(ex4_valid_q) and or_reduce(ex4_ttype_q)) or mmucr2_act_override) and xu_mm_ccr2_notlb_b; +-- tag4 phase signals, tlbwe/re ex6 +lrat_entry0_lpn_d <= lrat_datain_lpn_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="000" and ex6_illeg_instr(1)='0') + else lrat_entry0_lpn_q; +lrat_entry0_rpn_d <= lrat_datain_rpn_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="000" and ex6_illeg_instr(1)='0') + else lrat_entry0_rpn_q; +lrat_entry0_lpid_d <= lrat_datain_lpid_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="000" and ex6_illeg_instr(1)='0') + else lrat_entry0_lpid_q; +lrat_entry0_size_d <= lrat_datain_size_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="000" and ex6_illeg_instr(1)='0') + else lrat_entry0_size_q; +lrat_entry0_xbit_d <= lrat_datain_xbit_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="000" and ex6_illeg_instr(1)='0') + else lrat_entry0_xbit_q; +lrat_entry0_valid_d <= lrat_datain_valid_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="000" and ex6_illeg_instr(1)='0') + else lrat_entry0_valid_q; +-- size entry_cmpmask: 0123456 +-- 1TB 1111111 +-- 256GB 0111111 +-- 16GB 0011111 +-- 4GB 0001111 +-- 1GB 0000111 +-- 256MB 0000011 +-- 16MB 0000001 +-- 1MB 0000000 +lrat_entry0_cmpmask_d(0) <= Eq(lrat_datain_size_q, LRAT_PgSize_1TB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="000" and ex6_illeg_instr(1)='0') + else lrat_entry0_cmpmask_q(0); +lrat_entry0_cmpmask_d(1) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="000" and ex6_illeg_instr(1)='0') + else lrat_entry0_cmpmask_q(1); +lrat_entry0_cmpmask_d(2) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="000" and ex6_illeg_instr(1)='0') + else lrat_entry0_cmpmask_q(2); +lrat_entry0_cmpmask_d(3) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="000" and ex6_illeg_instr(1)='0') + else lrat_entry0_cmpmask_q(3); +lrat_entry0_cmpmask_d(4) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_1GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="000" and ex6_illeg_instr(1)='0') + else lrat_entry0_cmpmask_q(4); +lrat_entry0_cmpmask_d(5) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_1GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256MB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="000" and ex6_illeg_instr(1)='0') + else lrat_entry0_cmpmask_q(5); +lrat_entry0_cmpmask_d(6) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_1GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256MB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16MB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="000" and ex6_illeg_instr(1)='0') + else lrat_entry0_cmpmask_q(6); +-- size entry_xbitmask: 0123456 +-- 1TB 1000000 +-- 256GB 0100000 +-- 16GB 0010000 +-- 4GB 0001000 +-- 1GB 0000100 +-- 256MB 0000010 +-- 16MB 0000001 +-- 1MB 0000000 +lrat_entry0_xbitmask_d(0) <= Eq(lrat_datain_size_q, LRAT_PgSize_1TB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="000" and ex6_illeg_instr(1)='0') + else lrat_entry0_xbitmask_q(0); +lrat_entry0_xbitmask_d(1) <= Eq(lrat_datain_size_q, LRAT_PgSize_256GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="000" and ex6_illeg_instr(1)='0') + else lrat_entry0_xbitmask_q(1); +lrat_entry0_xbitmask_d(2) <= Eq(lrat_datain_size_q, LRAT_PgSize_16GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="000" and ex6_illeg_instr(1)='0') + else lrat_entry0_xbitmask_q(2); +lrat_entry0_xbitmask_d(3) <= Eq(lrat_datain_size_q, LRAT_PgSize_4GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="000" and ex6_illeg_instr(1)='0') + else lrat_entry0_xbitmask_q(3); +lrat_entry0_xbitmask_d(4) <= Eq(lrat_datain_size_q, LRAT_PgSize_1GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="000" and ex6_illeg_instr(1)='0') + else lrat_entry0_xbitmask_q(4); +lrat_entry0_xbitmask_d(5) <= Eq(lrat_datain_size_q, LRAT_PgSize_256MB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="000" and ex6_illeg_instr(1)='0') + else lrat_entry0_xbitmask_q(5); +lrat_entry0_xbitmask_d(6) <= Eq(lrat_datain_size_q, LRAT_PgSize_16MB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="000" and ex6_illeg_instr(1)='0') + else lrat_entry0_xbitmask_q(6); +lrat_entry1_lpn_d <= lrat_datain_lpn_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="001" and ex6_illeg_instr(1)='0') + else lrat_entry1_lpn_q; +lrat_entry1_rpn_d <= lrat_datain_rpn_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="001" and ex6_illeg_instr(1)='0') + else lrat_entry1_rpn_q; +lrat_entry1_lpid_d <= lrat_datain_lpid_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="001" and ex6_illeg_instr(1)='0') + else lrat_entry1_lpid_q; +lrat_entry1_size_d <= lrat_datain_size_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="001" and ex6_illeg_instr(1)='0') + else lrat_entry1_size_q; +lrat_entry1_xbit_d <= lrat_datain_xbit_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="001" and ex6_illeg_instr(1)='0') + else lrat_entry1_xbit_q; +lrat_entry1_valid_d <= lrat_datain_valid_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="001" and ex6_illeg_instr(1)='0') + else lrat_entry1_valid_q; +-- size entry_cmpmask: 0123456 +-- 1TB 1111111 +-- 256GB 0111111 +-- 16GB 0011111 +-- 4GB 0001111 +-- 1GB 0000111 +-- 256MB 0000011 +-- 16MB 0000001 +-- 1MB 0000000 +lrat_entry1_cmpmask_d(0) <= Eq(lrat_datain_size_q, LRAT_PgSize_1TB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="001" and ex6_illeg_instr(1)='0') + else lrat_entry1_cmpmask_q(0); +lrat_entry1_cmpmask_d(1) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="001" and ex6_illeg_instr(1)='0') + else lrat_entry1_cmpmask_q(1); +lrat_entry1_cmpmask_d(2) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="001" and ex6_illeg_instr(1)='0') + else lrat_entry1_cmpmask_q(2); +lrat_entry1_cmpmask_d(3) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="001" and ex6_illeg_instr(1)='0') + else lrat_entry1_cmpmask_q(3); +lrat_entry1_cmpmask_d(4) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_1GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="001" and ex6_illeg_instr(1)='0') + else lrat_entry1_cmpmask_q(4); +lrat_entry1_cmpmask_d(5) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_1GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256MB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="001" and ex6_illeg_instr(1)='0') + else lrat_entry1_cmpmask_q(5); +lrat_entry1_cmpmask_d(6) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_1GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256MB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16MB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="001" and ex6_illeg_instr(1)='0') + else lrat_entry1_cmpmask_q(6); +-- size entry_xbitmask: 0123456 +-- 1TB 1000000 +-- 256GB 0100000 +-- 16GB 0010000 +-- 4GB 0001000 +-- 1GB 0000100 +-- 256MB 0000010 +-- 16MB 0000001 +-- 1MB 0000000 +lrat_entry1_xbitmask_d(0) <= Eq(lrat_datain_size_q, LRAT_PgSize_1TB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="001" and ex6_illeg_instr(1)='0') + else lrat_entry1_xbitmask_q(0); +lrat_entry1_xbitmask_d(1) <= Eq(lrat_datain_size_q, LRAT_PgSize_256GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="001" and ex6_illeg_instr(1)='0') + else lrat_entry1_xbitmask_q(1); +lrat_entry1_xbitmask_d(2) <= Eq(lrat_datain_size_q, LRAT_PgSize_16GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="001" and ex6_illeg_instr(1)='0') + else lrat_entry1_xbitmask_q(2); +lrat_entry1_xbitmask_d(3) <= Eq(lrat_datain_size_q, LRAT_PgSize_4GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="001" and ex6_illeg_instr(1)='0') + else lrat_entry1_xbitmask_q(3); +lrat_entry1_xbitmask_d(4) <= Eq(lrat_datain_size_q, LRAT_PgSize_1GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="001" and ex6_illeg_instr(1)='0') + else lrat_entry1_xbitmask_q(4); +lrat_entry1_xbitmask_d(5) <= Eq(lrat_datain_size_q, LRAT_PgSize_256MB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="001" and ex6_illeg_instr(1)='0') + else lrat_entry1_xbitmask_q(5); +lrat_entry1_xbitmask_d(6) <= Eq(lrat_datain_size_q, LRAT_PgSize_16MB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="001" and ex6_illeg_instr(1)='0') + else lrat_entry1_xbitmask_q(6); +lrat_entry2_lpn_d <= lrat_datain_lpn_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="010" and ex6_illeg_instr(1)='0') + else lrat_entry2_lpn_q; +lrat_entry2_rpn_d <= lrat_datain_rpn_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="010" and ex6_illeg_instr(1)='0') + else lrat_entry2_rpn_q; +lrat_entry2_lpid_d <= lrat_datain_lpid_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="010" and ex6_illeg_instr(1)='0') + else lrat_entry2_lpid_q; +lrat_entry2_size_d <= lrat_datain_size_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="010" and ex6_illeg_instr(1)='0') + else lrat_entry2_size_q; +lrat_entry2_xbit_d <= lrat_datain_xbit_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="010" and ex6_illeg_instr(1)='0') + else lrat_entry2_xbit_q; +lrat_entry2_valid_d <= lrat_datain_valid_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="010" and ex6_illeg_instr(1)='0') + else lrat_entry2_valid_q; +-- size entry_cmpmask: 0123456 +-- 1TB 1111111 +-- 256GB 0111111 +-- 16GB 0011111 +-- 4GB 0001111 +-- 1GB 0000111 +-- 256MB 0000011 +-- 16MB 0000001 +-- 1MB 0000000 +lrat_entry2_cmpmask_d(0) <= Eq(lrat_datain_size_q, LRAT_PgSize_1TB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="010" and ex6_illeg_instr(1)='0') + else lrat_entry2_cmpmask_q(0); +lrat_entry2_cmpmask_d(1) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="010" and ex6_illeg_instr(1)='0') + else lrat_entry2_cmpmask_q(1); +lrat_entry2_cmpmask_d(2) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="010" and ex6_illeg_instr(1)='0') + else lrat_entry2_cmpmask_q(2); +lrat_entry2_cmpmask_d(3) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="010" and ex6_illeg_instr(1)='0') + else lrat_entry2_cmpmask_q(3); +lrat_entry2_cmpmask_d(4) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_1GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="010" and ex6_illeg_instr(1)='0') + else lrat_entry2_cmpmask_q(4); +lrat_entry2_cmpmask_d(5) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_1GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256MB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="010" and ex6_illeg_instr(1)='0') + else lrat_entry2_cmpmask_q(5); +lrat_entry2_cmpmask_d(6) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_1GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256MB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16MB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="010" and ex6_illeg_instr(1)='0') + else lrat_entry2_cmpmask_q(6); +-- size entry_xbitmask: 0123456 +-- 1TB 1000000 +-- 256GB 0100000 +-- 16GB 0010000 +-- 4GB 0001000 +-- 1GB 0000100 +-- 256MB 0000010 +-- 16MB 0000001 +-- 1MB 0000000 +lrat_entry2_xbitmask_d(0) <= Eq(lrat_datain_size_q, LRAT_PgSize_1TB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="010" and ex6_illeg_instr(1)='0') + else lrat_entry2_xbitmask_q(0); +lrat_entry2_xbitmask_d(1) <= Eq(lrat_datain_size_q, LRAT_PgSize_256GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="010" and ex6_illeg_instr(1)='0') + else lrat_entry2_xbitmask_q(1); +lrat_entry2_xbitmask_d(2) <= Eq(lrat_datain_size_q, LRAT_PgSize_16GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="010" and ex6_illeg_instr(1)='0') + else lrat_entry2_xbitmask_q(2); +lrat_entry2_xbitmask_d(3) <= Eq(lrat_datain_size_q, LRAT_PgSize_4GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="010" and ex6_illeg_instr(1)='0') + else lrat_entry2_xbitmask_q(3); +lrat_entry2_xbitmask_d(4) <= Eq(lrat_datain_size_q, LRAT_PgSize_1GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="010" and ex6_illeg_instr(1)='0') + else lrat_entry2_xbitmask_q(4); +lrat_entry2_xbitmask_d(5) <= Eq(lrat_datain_size_q, LRAT_PgSize_256MB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="010" and ex6_illeg_instr(1)='0') + else lrat_entry2_xbitmask_q(5); +lrat_entry2_xbitmask_d(6) <= Eq(lrat_datain_size_q, LRAT_PgSize_16MB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="010" and ex6_illeg_instr(1)='0') + else lrat_entry2_xbitmask_q(6); +lrat_entry3_lpn_d <= lrat_datain_lpn_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="011" and ex6_illeg_instr(1)='0') + else lrat_entry3_lpn_q; +lrat_entry3_rpn_d <= lrat_datain_rpn_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="011" and ex6_illeg_instr(1)='0') + else lrat_entry3_rpn_q; +lrat_entry3_lpid_d <= lrat_datain_lpid_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="011" and ex6_illeg_instr(1)='0') + else lrat_entry3_lpid_q; +lrat_entry3_size_d <= lrat_datain_size_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="011" and ex6_illeg_instr(1)='0') + else lrat_entry3_size_q; +lrat_entry3_xbit_d <= lrat_datain_xbit_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="011" and ex6_illeg_instr(1)='0') + else lrat_entry3_xbit_q; +lrat_entry3_valid_d <= lrat_datain_valid_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="011" and ex6_illeg_instr(1)='0') + else lrat_entry3_valid_q; +-- size entry_cmpmask: 0123456 +-- 1TB 1111111 +-- 256GB 0111111 +-- 16GB 0011111 +-- 4GB 0001111 +-- 1GB 0000111 +-- 256MB 0000011 +-- 16MB 0000001 +-- 1MB 0000000 +lrat_entry3_cmpmask_d(0) <= Eq(lrat_datain_size_q, LRAT_PgSize_1TB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="011" and ex6_illeg_instr(1)='0') + else lrat_entry3_cmpmask_q(0); +lrat_entry3_cmpmask_d(1) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="011" and ex6_illeg_instr(1)='0') + else lrat_entry3_cmpmask_q(1); +lrat_entry3_cmpmask_d(2) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="011" and ex6_illeg_instr(1)='0') + else lrat_entry3_cmpmask_q(2); +lrat_entry3_cmpmask_d(3) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="011" and ex6_illeg_instr(1)='0') + else lrat_entry3_cmpmask_q(3); +lrat_entry3_cmpmask_d(4) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_1GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="011" and ex6_illeg_instr(1)='0') + else lrat_entry3_cmpmask_q(4); +lrat_entry3_cmpmask_d(5) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_1GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256MB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="011" and ex6_illeg_instr(1)='0') + else lrat_entry3_cmpmask_q(5); +lrat_entry3_cmpmask_d(6) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_1GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256MB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16MB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="011" and ex6_illeg_instr(1)='0') + else lrat_entry3_cmpmask_q(6); +-- size entry_xbitmask: 0123456 +-- 1TB 1000000 +-- 256GB 0100000 +-- 16GB 0010000 +-- 4GB 0001000 +-- 1GB 0000100 +-- 256MB 0000010 +-- 16MB 0000001 +-- 1MB 0000000 +lrat_entry3_xbitmask_d(0) <= Eq(lrat_datain_size_q, LRAT_PgSize_1TB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="011" and ex6_illeg_instr(1)='0') + else lrat_entry3_xbitmask_q(0); +lrat_entry3_xbitmask_d(1) <= Eq(lrat_datain_size_q, LRAT_PgSize_256GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="011" and ex6_illeg_instr(1)='0') + else lrat_entry3_xbitmask_q(1); +lrat_entry3_xbitmask_d(2) <= Eq(lrat_datain_size_q, LRAT_PgSize_16GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="011" and ex6_illeg_instr(1)='0') + else lrat_entry3_xbitmask_q(2); +lrat_entry3_xbitmask_d(3) <= Eq(lrat_datain_size_q, LRAT_PgSize_4GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="011" and ex6_illeg_instr(1)='0') + else lrat_entry3_xbitmask_q(3); +lrat_entry3_xbitmask_d(4) <= Eq(lrat_datain_size_q, LRAT_PgSize_1GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="011" and ex6_illeg_instr(1)='0') + else lrat_entry3_xbitmask_q(4); +lrat_entry3_xbitmask_d(5) <= Eq(lrat_datain_size_q, LRAT_PgSize_256MB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="011" and ex6_illeg_instr(1)='0') + else lrat_entry3_xbitmask_q(5); +lrat_entry3_xbitmask_d(6) <= Eq(lrat_datain_size_q, LRAT_PgSize_16MB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="011" and ex6_illeg_instr(1)='0') + else lrat_entry3_xbitmask_q(6); +lrat_entry4_lpn_d <= lrat_datain_lpn_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="100" and ex6_illeg_instr(1)='0') + else lrat_entry4_lpn_q; +lrat_entry4_rpn_d <= lrat_datain_rpn_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="100" and ex6_illeg_instr(1)='0') + else lrat_entry4_rpn_q; +lrat_entry4_lpid_d <= lrat_datain_lpid_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="100" and ex6_illeg_instr(1)='0') + else lrat_entry4_lpid_q; +lrat_entry4_size_d <= lrat_datain_size_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="100" and ex6_illeg_instr(1)='0') + else lrat_entry4_size_q; +lrat_entry4_xbit_d <= lrat_datain_xbit_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="100" and ex6_illeg_instr(1)='0') + else lrat_entry4_xbit_q; +lrat_entry4_valid_d <= lrat_datain_valid_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="100" and ex6_illeg_instr(1)='0') + else lrat_entry4_valid_q; +-- size entry_cmpmask: 0123456 +-- 1TB 1111111 +-- 256GB 0111111 +-- 16GB 0011111 +-- 4GB 0001111 +-- 1GB 0000111 +-- 256MB 0000011 +-- 16MB 0000001 +-- 1MB 0000000 +lrat_entry4_cmpmask_d(0) <= Eq(lrat_datain_size_q, LRAT_PgSize_1TB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="100" and ex6_illeg_instr(1)='0') + else lrat_entry4_cmpmask_q(0); +lrat_entry4_cmpmask_d(1) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="100" and ex6_illeg_instr(1)='0') + else lrat_entry4_cmpmask_q(1); +lrat_entry4_cmpmask_d(2) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="100" and ex6_illeg_instr(1)='0') + else lrat_entry4_cmpmask_q(2); +lrat_entry4_cmpmask_d(3) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="100" and ex6_illeg_instr(1)='0') + else lrat_entry4_cmpmask_q(3); +lrat_entry4_cmpmask_d(4) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_1GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="100" and ex6_illeg_instr(1)='0') + else lrat_entry4_cmpmask_q(4); +lrat_entry4_cmpmask_d(5) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_1GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256MB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="100" and ex6_illeg_instr(1)='0') + else lrat_entry4_cmpmask_q(5); +lrat_entry4_cmpmask_d(6) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_1GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256MB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16MB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="100" and ex6_illeg_instr(1)='0') + else lrat_entry4_cmpmask_q(6); +-- size entry_xbitmask: 0123456 +-- 1TB 1000000 +-- 256GB 0100000 +-- 16GB 0010000 +-- 4GB 0001000 +-- 1GB 0000100 +-- 256MB 0000010 +-- 16MB 0000001 +-- 1MB 0000000 +lrat_entry4_xbitmask_d(0) <= Eq(lrat_datain_size_q, LRAT_PgSize_1TB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="100" and ex6_illeg_instr(1)='0') + else lrat_entry4_xbitmask_q(0); +lrat_entry4_xbitmask_d(1) <= Eq(lrat_datain_size_q, LRAT_PgSize_256GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="100" and ex6_illeg_instr(1)='0') + else lrat_entry4_xbitmask_q(1); +lrat_entry4_xbitmask_d(2) <= Eq(lrat_datain_size_q, LRAT_PgSize_16GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="100" and ex6_illeg_instr(1)='0') + else lrat_entry4_xbitmask_q(2); +lrat_entry4_xbitmask_d(3) <= Eq(lrat_datain_size_q, LRAT_PgSize_4GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="100" and ex6_illeg_instr(1)='0') + else lrat_entry4_xbitmask_q(3); +lrat_entry4_xbitmask_d(4) <= Eq(lrat_datain_size_q, LRAT_PgSize_1GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="100" and ex6_illeg_instr(1)='0') + else lrat_entry4_xbitmask_q(4); +lrat_entry4_xbitmask_d(5) <= Eq(lrat_datain_size_q, LRAT_PgSize_256MB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="100" and ex6_illeg_instr(1)='0') + else lrat_entry4_xbitmask_q(5); +lrat_entry4_xbitmask_d(6) <= Eq(lrat_datain_size_q, LRAT_PgSize_16MB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="100" and ex6_illeg_instr(1)='0') + else lrat_entry4_xbitmask_q(6); +lrat_entry5_lpn_d <= lrat_datain_lpn_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="101" and ex6_illeg_instr(1)='0') + else lrat_entry5_lpn_q; +lrat_entry5_rpn_d <= lrat_datain_rpn_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="101" and ex6_illeg_instr(1)='0') + else lrat_entry5_rpn_q; +lrat_entry5_lpid_d <= lrat_datain_lpid_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="101" and ex6_illeg_instr(1)='0') + else lrat_entry5_lpid_q; +lrat_entry5_size_d <= lrat_datain_size_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="101" and ex6_illeg_instr(1)='0') + else lrat_entry5_size_q; +lrat_entry5_xbit_d <= lrat_datain_xbit_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="101" and ex6_illeg_instr(1)='0') + else lrat_entry5_xbit_q; +lrat_entry5_valid_d <= lrat_datain_valid_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="101" and ex6_illeg_instr(1)='0') + else lrat_entry5_valid_q; +-- size entry_cmpmask: 0123456 +-- 1TB 1111111 +-- 256GB 0111111 +-- 16GB 0011111 +-- 4GB 0001111 +-- 1GB 0000111 +-- 256MB 0000011 +-- 16MB 0000001 +-- 1MB 0000000 +lrat_entry5_cmpmask_d(0) <= Eq(lrat_datain_size_q, LRAT_PgSize_1TB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="101" and ex6_illeg_instr(1)='0') + else lrat_entry5_cmpmask_q(0); +lrat_entry5_cmpmask_d(1) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="101" and ex6_illeg_instr(1)='0') + else lrat_entry5_cmpmask_q(1); +lrat_entry5_cmpmask_d(2) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="101" and ex6_illeg_instr(1)='0') + else lrat_entry5_cmpmask_q(2); +lrat_entry5_cmpmask_d(3) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="101" and ex6_illeg_instr(1)='0') + else lrat_entry5_cmpmask_q(3); +lrat_entry5_cmpmask_d(4) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_1GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="101" and ex6_illeg_instr(1)='0') + else lrat_entry5_cmpmask_q(4); +lrat_entry5_cmpmask_d(5) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_1GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256MB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="101" and ex6_illeg_instr(1)='0') + else lrat_entry5_cmpmask_q(5); +lrat_entry5_cmpmask_d(6) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_1GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256MB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16MB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="101" and ex6_illeg_instr(1)='0') + else lrat_entry5_cmpmask_q(6); +-- size entry_xbitmask: 0123456 +-- 1TB 1000000 +-- 256GB 0100000 +-- 16GB 0010000 +-- 4GB 0001000 +-- 1GB 0000100 +-- 256MB 0000010 +-- 16MB 0000001 +-- 1MB 0000000 +lrat_entry5_xbitmask_d(0) <= Eq(lrat_datain_size_q, LRAT_PgSize_1TB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="101" and ex6_illeg_instr(1)='0') + else lrat_entry5_xbitmask_q(0); +lrat_entry5_xbitmask_d(1) <= Eq(lrat_datain_size_q, LRAT_PgSize_256GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="101" and ex6_illeg_instr(1)='0') + else lrat_entry5_xbitmask_q(1); +lrat_entry5_xbitmask_d(2) <= Eq(lrat_datain_size_q, LRAT_PgSize_16GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="101" and ex6_illeg_instr(1)='0') + else lrat_entry5_xbitmask_q(2); +lrat_entry5_xbitmask_d(3) <= Eq(lrat_datain_size_q, LRAT_PgSize_4GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="101" and ex6_illeg_instr(1)='0') + else lrat_entry5_xbitmask_q(3); +lrat_entry5_xbitmask_d(4) <= Eq(lrat_datain_size_q, LRAT_PgSize_1GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="101" and ex6_illeg_instr(1)='0') + else lrat_entry5_xbitmask_q(4); +lrat_entry5_xbitmask_d(5) <= Eq(lrat_datain_size_q, LRAT_PgSize_256MB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="101" and ex6_illeg_instr(1)='0') + else lrat_entry5_xbitmask_q(5); +lrat_entry5_xbitmask_d(6) <= Eq(lrat_datain_size_q, LRAT_PgSize_16MB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="101" and ex6_illeg_instr(1)='0') + else lrat_entry5_xbitmask_q(6); +lrat_entry6_lpn_d <= lrat_datain_lpn_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="110" and ex6_illeg_instr(1)='0') + else lrat_entry6_lpn_q; +lrat_entry6_rpn_d <= lrat_datain_rpn_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="110" and ex6_illeg_instr(1)='0') + else lrat_entry6_rpn_q; +lrat_entry6_lpid_d <= lrat_datain_lpid_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="110" and ex6_illeg_instr(1)='0') + else lrat_entry6_lpid_q; +lrat_entry6_size_d <= lrat_datain_size_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="110" and ex6_illeg_instr(1)='0') + else lrat_entry6_size_q; +lrat_entry6_xbit_d <= lrat_datain_xbit_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="110" and ex6_illeg_instr(1)='0') + else lrat_entry6_xbit_q; +lrat_entry6_valid_d <= lrat_datain_valid_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="110" and ex6_illeg_instr(1)='0') + else lrat_entry6_valid_q; +-- size entry_cmpmask: 0123456 +-- 1TB 1111111 +-- 256GB 0111111 +-- 16GB 0011111 +-- 4GB 0001111 +-- 1GB 0000111 +-- 256MB 0000011 +-- 16MB 0000001 +-- 1MB 0000000 +lrat_entry6_cmpmask_d(0) <= Eq(lrat_datain_size_q, LRAT_PgSize_1TB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="110" and ex6_illeg_instr(1)='0') + else lrat_entry6_cmpmask_q(0); +lrat_entry6_cmpmask_d(1) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="110" and ex6_illeg_instr(1)='0') + else lrat_entry6_cmpmask_q(1); +lrat_entry6_cmpmask_d(2) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="110" and ex6_illeg_instr(1)='0') + else lrat_entry6_cmpmask_q(2); +lrat_entry6_cmpmask_d(3) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="110" and ex6_illeg_instr(1)='0') + else lrat_entry6_cmpmask_q(3); +lrat_entry6_cmpmask_d(4) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_1GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="110" and ex6_illeg_instr(1)='0') + else lrat_entry6_cmpmask_q(4); +lrat_entry6_cmpmask_d(5) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_1GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256MB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="110" and ex6_illeg_instr(1)='0') + else lrat_entry6_cmpmask_q(5); +lrat_entry6_cmpmask_d(6) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_1GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256MB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16MB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="110" and ex6_illeg_instr(1)='0') + else lrat_entry6_cmpmask_q(6); +-- size entry_xbitmask: 0123456 +-- 1TB 1000000 +-- 256GB 0100000 +-- 16GB 0010000 +-- 4GB 0001000 +-- 1GB 0000100 +-- 256MB 0000010 +-- 16MB 0000001 +-- 1MB 0000000 +lrat_entry6_xbitmask_d(0) <= Eq(lrat_datain_size_q, LRAT_PgSize_1TB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="110" and ex6_illeg_instr(1)='0') + else lrat_entry6_xbitmask_q(0); +lrat_entry6_xbitmask_d(1) <= Eq(lrat_datain_size_q, LRAT_PgSize_256GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="110" and ex6_illeg_instr(1)='0') + else lrat_entry6_xbitmask_q(1); +lrat_entry6_xbitmask_d(2) <= Eq(lrat_datain_size_q, LRAT_PgSize_16GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="110" and ex6_illeg_instr(1)='0') + else lrat_entry6_xbitmask_q(2); +lrat_entry6_xbitmask_d(3) <= Eq(lrat_datain_size_q, LRAT_PgSize_4GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="110" and ex6_illeg_instr(1)='0') + else lrat_entry6_xbitmask_q(3); +lrat_entry6_xbitmask_d(4) <= Eq(lrat_datain_size_q, LRAT_PgSize_1GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="110" and ex6_illeg_instr(1)='0') + else lrat_entry6_xbitmask_q(4); +lrat_entry6_xbitmask_d(5) <= Eq(lrat_datain_size_q, LRAT_PgSize_256MB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="110" and ex6_illeg_instr(1)='0') + else lrat_entry6_xbitmask_q(5); +lrat_entry6_xbitmask_d(6) <= Eq(lrat_datain_size_q, LRAT_PgSize_16MB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="110" and ex6_illeg_instr(1)='0') + else lrat_entry6_xbitmask_q(6); +lrat_entry7_lpn_d <= lrat_datain_lpn_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="111" and ex6_illeg_instr(1)='0') + else lrat_entry7_lpn_q; +lrat_entry7_rpn_d <= lrat_datain_rpn_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="111" and ex6_illeg_instr(1)='0') + else lrat_entry7_rpn_q; +lrat_entry7_lpid_d <= lrat_datain_lpid_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="111" and ex6_illeg_instr(1)='0') + else lrat_entry7_lpid_q; +lrat_entry7_size_d <= lrat_datain_size_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="111" and ex6_illeg_instr(1)='0') + else lrat_entry7_size_q; +lrat_entry7_xbit_d <= lrat_datain_xbit_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="111" and ex6_illeg_instr(1)='0') + else lrat_entry7_xbit_q; +lrat_entry7_valid_d <= lrat_datain_valid_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="111" and ex6_illeg_instr(1)='0') + else lrat_entry7_valid_q; +-- size entry_cmpmask: 0123456 +-- 1TB 1111111 +-- 256GB 0111111 +-- 16GB 0011111 +-- 4GB 0001111 +-- 1GB 0000111 +-- 256MB 0000011 +-- 16MB 0000001 +-- 1MB 0000000 +lrat_entry7_cmpmask_d(0) <= Eq(lrat_datain_size_q, LRAT_PgSize_1TB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="111" and ex6_illeg_instr(1)='0') + else lrat_entry7_cmpmask_q(0); +lrat_entry7_cmpmask_d(1) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="111" and ex6_illeg_instr(1)='0') + else lrat_entry7_cmpmask_q(1); +lrat_entry7_cmpmask_d(2) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="111" and ex6_illeg_instr(1)='0') + else lrat_entry7_cmpmask_q(2); +lrat_entry7_cmpmask_d(3) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="111" and ex6_illeg_instr(1)='0') + else lrat_entry7_cmpmask_q(3); +lrat_entry7_cmpmask_d(4) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_1GB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="111" and ex6_illeg_instr(1)='0') + else lrat_entry7_cmpmask_q(4); +lrat_entry7_cmpmask_d(5) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_1GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256MB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="111" and ex6_illeg_instr(1)='0') + else lrat_entry7_cmpmask_q(5); +lrat_entry7_cmpmask_d(6) <= (Eq(lrat_datain_size_q, LRAT_PgSize_1TB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_4GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_1GB) or + Eq(lrat_datain_size_q, LRAT_PgSize_256MB) or + Eq(lrat_datain_size_q, LRAT_PgSize_16MB)) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="111" and ex6_illeg_instr(1)='0') + else lrat_entry7_cmpmask_q(6); +-- size entry_xbitmask: 0123456 +-- 1TB 1000000 +-- 256GB 0100000 +-- 16GB 0010000 +-- 4GB 0001000 +-- 1GB 0000100 +-- 256MB 0000010 +-- 16MB 0000001 +-- 1MB 0000000 +lrat_entry7_xbitmask_d(0) <= Eq(lrat_datain_size_q, LRAT_PgSize_1TB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="111" and ex6_illeg_instr(1)='0') + else lrat_entry7_xbitmask_q(0); +lrat_entry7_xbitmask_d(1) <= Eq(lrat_datain_size_q, LRAT_PgSize_256GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="111" and ex6_illeg_instr(1)='0') + else lrat_entry7_xbitmask_q(1); +lrat_entry7_xbitmask_d(2) <= Eq(lrat_datain_size_q, LRAT_PgSize_16GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="111" and ex6_illeg_instr(1)='0') + else lrat_entry7_xbitmask_q(2); +lrat_entry7_xbitmask_d(3) <= Eq(lrat_datain_size_q, LRAT_PgSize_4GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="111" and ex6_illeg_instr(1)='0') + else lrat_entry7_xbitmask_q(3); +lrat_entry7_xbitmask_d(4) <= Eq(lrat_datain_size_q, LRAT_PgSize_1GB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="111" and ex6_illeg_instr(1)='0') + else lrat_entry7_xbitmask_q(4); +lrat_entry7_xbitmask_d(5) <= Eq(lrat_datain_size_q, LRAT_PgSize_256MB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="111" and ex6_illeg_instr(1)='0') + else lrat_entry7_xbitmask_q(5); +lrat_entry7_xbitmask_d(6) <= Eq(lrat_datain_size_q, LRAT_PgSize_16MB) + when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_atsel_q='1' and ex6_hes_q='0' and (ex6_wq_q="00" or ex6_wq_q="11") and ex6_esel_q="111" and ex6_illeg_instr(1)='0') + else lrat_entry7_xbitmask_q(6); +-- power clock gating for entries +lrat_entry_act_d(0 TO 7) <= (0 to 7 => ((or_reduce(ex5_valid_q) and ex5_atsel_q) or mmucr2_act_override) and xu_mm_ccr2_notlb_b); +-- these are tag1 phase matchline components +matchline_comb0 : mmq_tlb_lrat_matchline + generic map (real_addr_width => real_addr_width, + lpid_width => 8, + lrat_maxsize_log2 => const_lrat_maxsize_log2, + lrat_minsize_log2 => 20, + have_xbit => 1, + num_pgsizes => 8, + have_cmpmask => 1, + cmpmask_width => 7) + port map ( + vdd => vdd, + gnd => gnd, + addr_in => lrat_tag1_lpn_q(64-real_addr_width to 64-lrat_minsize_log2-1), + addr_enable => addr_enable, + entry_size => lrat_entry0_size_q(0 to 3), + entry_cmpmask => lrat_entry0_cmpmask_q(0 to 6), + entry_xbit => lrat_entry0_xbit_q, + entry_xbitmask => lrat_entry0_xbitmask_q(0 to 6), + entry_lpn => lrat_entry0_lpn_q(64-real_addr_width to 64-lrat_minsize_log2-1), + entry_lpid => lrat_entry0_lpid_q(0 to lpid_width-1), + comp_lpid => lrat_tag1_lpid_q(0 to lpid_width-1), + lpid_enable => lpid_enable, + entry_v => lrat_entry0_valid_q, + + match => lrat_tag1_matchline(0), + + dbg_addr_match => lrat_entry0_addr_match, + dbg_lpid_match => lrat_entry0_lpid_match + + ); +matchline_comb1 : mmq_tlb_lrat_matchline + generic map (real_addr_width => real_addr_width, + lpid_width => 8, + lrat_maxsize_log2 => const_lrat_maxsize_log2, + lrat_minsize_log2 => 20, + have_xbit => 1, + num_pgsizes => 8, + have_cmpmask => 1, + cmpmask_width => 7) + port map ( + vdd => vdd, + gnd => gnd, + addr_in => lrat_tag1_lpn_q(64-real_addr_width to 64-lrat_minsize_log2-1), + addr_enable => addr_enable, + entry_size => lrat_entry1_size_q(0 to 3), + entry_cmpmask => lrat_entry1_cmpmask_q(0 to 6), + entry_xbit => lrat_entry1_xbit_q, + entry_xbitmask => lrat_entry1_xbitmask_q(0 to 6), + entry_lpn => lrat_entry1_lpn_q(64-real_addr_width to 64-lrat_minsize_log2-1), + entry_lpid => lrat_entry1_lpid_q(0 to lpid_width-1), + comp_lpid => lrat_tag1_lpid_q(0 to lpid_width-1), + lpid_enable => lpid_enable, + entry_v => lrat_entry1_valid_q, + + match => lrat_tag1_matchline(1), + + dbg_addr_match => lrat_entry1_addr_match, + dbg_lpid_match => lrat_entry1_lpid_match + + ); +matchline_comb2 : mmq_tlb_lrat_matchline + generic map (real_addr_width => real_addr_width, + lpid_width => 8, + lrat_maxsize_log2 => const_lrat_maxsize_log2, + lrat_minsize_log2 => 20, + have_xbit => 1, + num_pgsizes => 8, + have_cmpmask => 1, + cmpmask_width => 7) + port map ( + vdd => vdd, + gnd => gnd, + addr_in => lrat_tag1_lpn_q(64-real_addr_width to 64-lrat_minsize_log2-1), + addr_enable => addr_enable, + entry_size => lrat_entry2_size_q(0 to 3), + entry_cmpmask => lrat_entry2_cmpmask_q(0 to 6), + entry_xbit => lrat_entry2_xbit_q, + entry_xbitmask => lrat_entry2_xbitmask_q(0 to 6), + entry_lpn => lrat_entry2_lpn_q(64-real_addr_width to 64-lrat_minsize_log2-1), + entry_lpid => lrat_entry2_lpid_q(0 to lpid_width-1), + comp_lpid => lrat_tag1_lpid_q(0 to lpid_width-1), + lpid_enable => lpid_enable, + entry_v => lrat_entry2_valid_q, + + match => lrat_tag1_matchline(2), + + dbg_addr_match => lrat_entry2_addr_match, + dbg_lpid_match => lrat_entry2_lpid_match + + ); +matchline_comb3 : mmq_tlb_lrat_matchline + generic map (real_addr_width => real_addr_width, + lpid_width => 8, + lrat_maxsize_log2 => const_lrat_maxsize_log2, + lrat_minsize_log2 => 20, + have_xbit => 1, + num_pgsizes => 8, + have_cmpmask => 1, + cmpmask_width => 7) + port map ( + vdd => vdd, + gnd => gnd, + addr_in => lrat_tag1_lpn_q(64-real_addr_width to 64-lrat_minsize_log2-1), + addr_enable => addr_enable, + entry_size => lrat_entry3_size_q(0 to 3), + entry_cmpmask => lrat_entry3_cmpmask_q(0 to 6), + entry_xbit => lrat_entry3_xbit_q, + entry_xbitmask => lrat_entry3_xbitmask_q(0 to 6), + entry_lpn => lrat_entry3_lpn_q(64-real_addr_width to 64-lrat_minsize_log2-1), + entry_lpid => lrat_entry3_lpid_q(0 to lpid_width-1), + comp_lpid => lrat_tag1_lpid_q(0 to lpid_width-1), + lpid_enable => lpid_enable, + entry_v => lrat_entry3_valid_q, + + match => lrat_tag1_matchline(3), + + dbg_addr_match => lrat_entry3_addr_match, + dbg_lpid_match => lrat_entry3_lpid_match + + ); +matchline_comb4 : mmq_tlb_lrat_matchline + generic map (real_addr_width => real_addr_width, + lpid_width => 8, + lrat_maxsize_log2 => const_lrat_maxsize_log2, + lrat_minsize_log2 => 20, + have_xbit => 1, + num_pgsizes => 8, + have_cmpmask => 1, + cmpmask_width => 7) + port map ( + vdd => vdd, + gnd => gnd, + addr_in => lrat_tag1_lpn_q(64-real_addr_width to 64-lrat_minsize_log2-1), + addr_enable => addr_enable, + entry_size => lrat_entry4_size_q(0 to 3), + entry_cmpmask => lrat_entry4_cmpmask_q(0 to 6), + entry_xbit => lrat_entry4_xbit_q, + entry_xbitmask => lrat_entry4_xbitmask_q(0 to 6), + entry_lpn => lrat_entry4_lpn_q(64-real_addr_width to 64-lrat_minsize_log2-1), + entry_lpid => lrat_entry4_lpid_q(0 to lpid_width-1), + comp_lpid => lrat_tag1_lpid_q(0 to lpid_width-1), + lpid_enable => lpid_enable, + entry_v => lrat_entry4_valid_q, + + match => lrat_tag1_matchline(4), + + dbg_addr_match => lrat_entry4_addr_match, + dbg_lpid_match => lrat_entry4_lpid_match + + ); +matchline_comb5 : mmq_tlb_lrat_matchline + generic map (real_addr_width => real_addr_width, + lpid_width => 8, + lrat_maxsize_log2 => const_lrat_maxsize_log2, + lrat_minsize_log2 => 20, + have_xbit => 1, + num_pgsizes => 8, + have_cmpmask => 1, + cmpmask_width => 7) + port map ( + vdd => vdd, + gnd => gnd, + addr_in => lrat_tag1_lpn_q(64-real_addr_width to 64-lrat_minsize_log2-1), + addr_enable => addr_enable, + entry_size => lrat_entry5_size_q(0 to 3), + entry_cmpmask => lrat_entry5_cmpmask_q(0 to 6), + entry_xbit => lrat_entry5_xbit_q, + entry_xbitmask => lrat_entry5_xbitmask_q(0 to 6), + entry_lpn => lrat_entry5_lpn_q(64-real_addr_width to 64-lrat_minsize_log2-1), + entry_lpid => lrat_entry5_lpid_q(0 to lpid_width-1), + comp_lpid => lrat_tag1_lpid_q(0 to lpid_width-1), + lpid_enable => lpid_enable, + entry_v => lrat_entry5_valid_q, + + match => lrat_tag1_matchline(5), + + dbg_addr_match => lrat_entry5_addr_match, + dbg_lpid_match => lrat_entry5_lpid_match + + ); +matchline_comb6 : mmq_tlb_lrat_matchline + generic map (real_addr_width => real_addr_width, + lpid_width => 8, + lrat_maxsize_log2 => const_lrat_maxsize_log2, + lrat_minsize_log2 => 20, + have_xbit => 1, + num_pgsizes => 8, + have_cmpmask => 1, + cmpmask_width => 7) + port map ( + vdd => vdd, + gnd => gnd, + addr_in => lrat_tag1_lpn_q(64-real_addr_width to 64-lrat_minsize_log2-1), + addr_enable => addr_enable, + entry_size => lrat_entry6_size_q(0 to 3), + entry_cmpmask => lrat_entry6_cmpmask_q(0 to 6), + entry_xbit => lrat_entry6_xbit_q, + entry_xbitmask => lrat_entry6_xbitmask_q(0 to 6), + entry_lpn => lrat_entry6_lpn_q(64-real_addr_width to 64-lrat_minsize_log2-1), + entry_lpid => lrat_entry6_lpid_q(0 to lpid_width-1), + comp_lpid => lrat_tag1_lpid_q(0 to lpid_width-1), + lpid_enable => lpid_enable, + entry_v => lrat_entry6_valid_q, + + match => lrat_tag1_matchline(6), + + dbg_addr_match => lrat_entry6_addr_match, + dbg_lpid_match => lrat_entry6_lpid_match + + ); +matchline_comb7 : mmq_tlb_lrat_matchline + generic map (real_addr_width => real_addr_width, + lpid_width => 8, + lrat_maxsize_log2 => const_lrat_maxsize_log2, + lrat_minsize_log2 => 20, + have_xbit => 1, + num_pgsizes => 8, + have_cmpmask => 1, + cmpmask_width => 7) + port map ( + vdd => vdd, + gnd => gnd, + addr_in => lrat_tag1_lpn_q(64-real_addr_width to 64-lrat_minsize_log2-1), + addr_enable => addr_enable, + entry_size => lrat_entry7_size_q(0 to 3), + entry_cmpmask => lrat_entry7_cmpmask_q(0 to 6), + entry_xbit => lrat_entry7_xbit_q, + entry_xbitmask => lrat_entry7_xbitmask_q(0 to 6), + entry_lpn => lrat_entry7_lpn_q(64-real_addr_width to 64-lrat_minsize_log2-1), + entry_lpid => lrat_entry7_lpid_q(0 to lpid_width-1), + comp_lpid => lrat_tag1_lpid_q(0 to lpid_width-1), + lpid_enable => lpid_enable, + entry_v => lrat_entry7_valid_q, + + match => lrat_tag1_matchline(7), + + dbg_addr_match => lrat_entry7_addr_match, + dbg_lpid_match => lrat_entry7_lpid_match + + ); +----------------------------------------------------------------------- +-- output assignments +----------------------------------------------------------------------- +lrat_tag3_lpn <= lrat_tag3_lpn_q(64-real_addr_width to 51); +lrat_tag3_rpn <= lrat_tag3_rpn_q(64-real_addr_width to 51); +lrat_tag3_hit_status <= lrat_tag3_hit_status_q; +lrat_tag3_hit_entry <= lrat_tag3_hit_entry_q; +lrat_tag4_lpn <= lrat_tag4_lpn_q(64-real_addr_width to 51); +lrat_tag4_rpn <= lrat_tag4_rpn_q(64-real_addr_width to 51); +lrat_tag4_hit_status <= lrat_tag4_hit_status_q; +lrat_tag4_hit_entry <= lrat_tag4_hit_entry_q; +lrat_mas0_esel <= lrat_tag4_hit_entry_q; +lrat_mas1_v <= lrat_mas1_v_q; +lrat_mas1_tsize <= lrat_mas1_tsize_q; +gen64_lrat_mas2_epn: if real_addr_width > 32 generate +lrat_mas2_epn(0 TO 63-real_addr_width) <= (others => '0'); +lrat_mas2_epn(64-real_addr_width TO 31) <= lrat_mas2_epn_q(64-real_addr_width to 31); +lrat_mas2_epn(32 TO 51) <= lrat_mas2_epn_q(32 to 51); +end generate gen64_lrat_mas2_epn; +gen32_lrat_mas2_epn: if real_addr_width < 33 generate +lrat_mas2_epn(0 TO 63-real_addr_width) <= (others => '0'); +lrat_mas2_epn(64-real_addr_width TO 51) <= lrat_mas2_epn_q(64-real_addr_width to 51); +end generate gen32_lrat_mas2_epn; +lrat_mas3_rpnl <= lrat_mas3_rpnl_q; +lrat_mas7_rpnu <= lrat_mas7_rpnu_q; +lrat_mas8_tlpid <= lrat_mas8_tlpid_q; +lrat_mas_tlbre <= lrat_mas_tlbre_q; +lrat_mas_tlbsx_hit <= lrat_mas_tlbsx_hit_q; +lrat_mas_tlbsx_miss <= lrat_mas_tlbsx_miss_q; +lrat_mas_thdid <= lrat_mas_thdid_q; +lrat_mmucr3_x <= lrat_mmucr3_x_q; +lrat_dbg_tag1_addr_enable <= addr_enable; +lrat_dbg_tag2_matchline_q <= lrat_tag2_matchline_q; +lrat_dbg_entry0_addr_match <= lrat_entry0_addr_match; +lrat_dbg_entry0_lpid_match <= lrat_entry0_lpid_match; +lrat_dbg_entry0_entry_v <= lrat_entry0_valid_q; +lrat_dbg_entry0_entry_x <= lrat_entry0_xbit_q; +lrat_dbg_entry0_size <= lrat_entry0_size_q; +lrat_dbg_entry1_addr_match <= lrat_entry1_addr_match; +lrat_dbg_entry1_lpid_match <= lrat_entry1_lpid_match; +lrat_dbg_entry1_entry_v <= lrat_entry1_valid_q; +lrat_dbg_entry1_entry_x <= lrat_entry1_xbit_q; +lrat_dbg_entry1_size <= lrat_entry1_size_q; +lrat_dbg_entry2_addr_match <= lrat_entry2_addr_match; +lrat_dbg_entry2_lpid_match <= lrat_entry2_lpid_match; +lrat_dbg_entry2_entry_v <= lrat_entry2_valid_q; +lrat_dbg_entry2_entry_x <= lrat_entry2_xbit_q; +lrat_dbg_entry2_size <= lrat_entry2_size_q; +lrat_dbg_entry3_addr_match <= lrat_entry3_addr_match; +lrat_dbg_entry3_lpid_match <= lrat_entry3_lpid_match; +lrat_dbg_entry3_entry_v <= lrat_entry3_valid_q; +lrat_dbg_entry3_entry_x <= lrat_entry3_xbit_q; +lrat_dbg_entry3_size <= lrat_entry3_size_q; +lrat_dbg_entry4_addr_match <= lrat_entry4_addr_match; +lrat_dbg_entry4_lpid_match <= lrat_entry4_lpid_match; +lrat_dbg_entry4_entry_v <= lrat_entry4_valid_q; +lrat_dbg_entry4_entry_x <= lrat_entry4_xbit_q; +lrat_dbg_entry4_size <= lrat_entry4_size_q; +lrat_dbg_entry5_addr_match <= lrat_entry5_addr_match; +lrat_dbg_entry5_lpid_match <= lrat_entry5_lpid_match; +lrat_dbg_entry5_entry_v <= lrat_entry5_valid_q; +lrat_dbg_entry5_entry_x <= lrat_entry5_xbit_q; +lrat_dbg_entry5_size <= lrat_entry5_size_q; +lrat_dbg_entry6_addr_match <= lrat_entry6_addr_match; +lrat_dbg_entry6_lpid_match <= lrat_entry6_lpid_match; +lrat_dbg_entry6_entry_v <= lrat_entry6_valid_q; +lrat_dbg_entry6_entry_x <= lrat_entry6_xbit_q; +lrat_dbg_entry6_size <= lrat_entry6_size_q; +lrat_dbg_entry7_addr_match <= lrat_entry7_addr_match; +lrat_dbg_entry7_lpid_match <= lrat_entry7_lpid_match; +lrat_dbg_entry7_entry_v <= lrat_entry7_valid_q; +lrat_dbg_entry7_entry_x <= lrat_entry7_xbit_q; +lrat_dbg_entry7_size <= lrat_entry7_size_q; +-- unused spare signal assignments +unused_dc(0) <= or_reduce(LCB_DELAY_LCLKR_DC(1 TO 4)); +unused_dc(1) <= or_reduce(LCB_MPW1_DC_B(1 TO 4)); +unused_dc(2) <= PC_FUNC_SL_FORCE; +unused_dc(3) <= PC_FUNC_SL_THOLD_0_B; +unused_dc(4) <= TC_SCAN_DIS_DC_B; +unused_dc(5) <= TC_SCAN_DIAG_DC; +unused_dc(6) <= TC_LBIST_EN_DC; +unused_dc(7) <= or_reduce(TLB_TAG0_TYPE(0 TO 1) & TLB_TAG0_TYPE(3 TO 5)); +unused_dc(8) <= EX6_TTYPE_Q(0); +unused_dc(9) <= or_reduce(MAS2_0_EPN(44 TO 51)); +unused_dc(10) <= or_reduce(MAS2_1_EPN(44 TO 51)); +unused_dc(11) <= or_reduce(MAS2_2_EPN(44 TO 51)); +unused_dc(12) <= or_reduce(MAS2_3_EPN(44 TO 51)); +unused_dc(13) <= ex6_illeg_instr(0); +----------------------------------------------------------------------- +-- Latches +----------------------------------------------------------------------- +-- ex4 phase: valid latches +ex4_valid_latch: tri_rlmreg_p + generic map (width => ex4_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex4_valid_offset to ex4_valid_offset+ex4_valid_q'length-1), + scout => sov(ex4_valid_offset to ex4_valid_offset+ex4_valid_q'length-1), + din => ex4_valid_d, + dout => ex4_valid_q ); +-- ex4 phase: ttype latches +ex4_ttype_latch: tri_rlmreg_p + generic map (width => ex4_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex4_ttype_offset to ex4_ttype_offset+ex4_ttype_q'length-1), + scout => sov(ex4_ttype_offset to ex4_ttype_offset+ex4_ttype_q'length-1), + din => ex4_ttype_d, + dout => ex4_ttype_q ); +-- ex5 phase: valid latches +ex5_valid_latch: tri_rlmreg_p + generic map (width => ex5_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex5_valid_offset to ex5_valid_offset+ex5_valid_q'length-1), + scout => sov(ex5_valid_offset to ex5_valid_offset+ex5_valid_q'length-1), + din => ex5_valid_d, + dout => ex5_valid_q ); +-- ex5 phase: ttype latches +ex5_ttype_latch: tri_rlmreg_p + generic map (width => ex5_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex5_ttype_offset to ex5_ttype_offset+ex5_ttype_q'length-1), + scout => sov(ex5_ttype_offset to ex5_ttype_offset+ex5_ttype_q'length-1), + din => ex5_ttype_d, + dout => ex5_ttype_q ); +-- ex6 phase: valid latches +ex6_valid_latch: tri_rlmreg_p + generic map (width => ex6_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex6_valid_offset to ex6_valid_offset+ex6_valid_q'length-1), + scout => sov(ex6_valid_offset to ex6_valid_offset+ex6_valid_q'length-1), + din => ex6_valid_d, + dout => ex6_valid_q ); +-- ex6 phase: ttype latches +ex6_ttype_latch: tri_rlmreg_p + generic map (width => ex6_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex6_ttype_offset to ex6_ttype_offset+ex6_ttype_q'length-1), + scout => sov(ex6_ttype_offset to ex6_ttype_offset+ex6_ttype_q'length-1), + din => ex6_ttype_d, + dout => ex6_ttype_q ); +-- ex5 phase: esel latches +ex5_esel_latch: tri_rlmreg_p + generic map (width => ex5_esel_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex5_esel_offset to ex5_esel_offset+ex5_esel_q'length-1), + scout => sov(ex5_esel_offset to ex5_esel_offset+ex5_esel_q'length-1), + din => ex5_esel_d, + dout => ex5_esel_q ); +-- ex5 phase: atsel latches +ex5_atsel_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex5_atsel_offset), + scout => sov(ex5_atsel_offset), + din => ex5_atsel_d, + dout => ex5_atsel_q); +-- ex5 phase: hes latches +ex5_hes_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex5_hes_offset), + scout => sov(ex5_hes_offset), + din => ex5_hes_d, + dout => ex5_hes_q); +-- ex5 phase: wq latches +ex5_wq_latch: tri_rlmreg_p + generic map (width => ex5_wq_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex5_wq_offset to ex5_wq_offset+ex5_wq_q'length-1), + scout => sov(ex5_wq_offset to ex5_wq_offset+ex5_wq_q'length-1), + din => ex5_wq_d, + dout => ex5_wq_q ); +-- ex6 phase: esel latches +ex6_esel_latch: tri_rlmreg_p + generic map (width => ex6_esel_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex6_esel_offset to ex6_esel_offset+ex6_esel_q'length-1), + scout => sov(ex6_esel_offset to ex6_esel_offset+ex6_esel_q'length-1), + din => ex6_esel_d, + dout => ex6_esel_q ); +-- ex6 phase: atsel latches +ex6_atsel_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex6_atsel_offset), + scout => sov(ex6_atsel_offset), + din => ex6_atsel_d, + dout => ex6_atsel_q); +-- ex6 phase: hes latches +ex6_hes_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex6_hes_offset), + scout => sov(ex6_hes_offset), + din => ex6_hes_d, + dout => ex6_hes_q); +-- ex6 phase: wq latches +ex6_wq_latch: tri_rlmreg_p + generic map (width => ex6_wq_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ex6_wq_offset to ex6_wq_offset+ex6_wq_q'length-1), + scout => sov(ex6_wq_offset to ex6_wq_offset+ex6_wq_q'length-1), + din => ex6_wq_d, + dout => ex6_wq_q ); +-- tag1 phase: logical page number latches +lrat_tag1_lpn_latch: tri_rlmreg_p + generic map (width => lrat_tag1_lpn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(20+0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_tag1_lpn_offset to lrat_tag1_lpn_offset+lrat_tag1_lpn_q'length-1), + scout => sov(lrat_tag1_lpn_offset to lrat_tag1_lpn_offset+lrat_tag1_lpn_q'length-1), + din => lrat_tag1_lpn_d(64-real_addr_width to 51), + dout => lrat_tag1_lpn_q(64-real_addr_width to 51) ); +-- tag2 phase: logical page number latches +lrat_tag2_lpn_latch: tri_rlmreg_p + generic map (width => lrat_tag2_lpn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(20+1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_tag2_lpn_offset to lrat_tag2_lpn_offset+lrat_tag2_lpn_q'length-1), + scout => sov(lrat_tag2_lpn_offset to lrat_tag2_lpn_offset+lrat_tag2_lpn_q'length-1), + din => lrat_tag2_lpn_d(64-real_addr_width to 51), + dout => lrat_tag2_lpn_q(64-real_addr_width to 51) ); +-- tag3 phase: logical page number latches +lrat_tag3_lpn_latch: tri_rlmreg_p + generic map (width => lrat_tag3_lpn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(20+2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_tag3_lpn_offset to lrat_tag3_lpn_offset+lrat_tag3_lpn_q'length-1), + scout => sov(lrat_tag3_lpn_offset to lrat_tag3_lpn_offset+lrat_tag3_lpn_q'length-1), + din => lrat_tag3_lpn_d(64-real_addr_width to 51), + dout => lrat_tag3_lpn_q(64-real_addr_width to 51) ); +-- tag4 phase: logical page number latches +lrat_tag4_lpn_latch: tri_rlmreg_p + generic map (width => lrat_tag4_lpn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(20+3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_tag4_lpn_offset to lrat_tag4_lpn_offset+lrat_tag4_lpn_q'length-1), + scout => sov(lrat_tag4_lpn_offset to lrat_tag4_lpn_offset+lrat_tag4_lpn_q'length-1), + din => lrat_tag4_lpn_d(64-real_addr_width to 51), + dout => lrat_tag4_lpn_q(64-real_addr_width to 51) ); +-- tag3 phase: real page number latches +lrat_tag3_rpn_latch: tri_rlmreg_p + generic map (width => lrat_tag3_rpn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(20+2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_tag3_rpn_offset to lrat_tag3_rpn_offset+lrat_tag3_rpn_q'length-1), + scout => sov(lrat_tag3_rpn_offset to lrat_tag3_rpn_offset+lrat_tag3_rpn_q'length-1), + din => lrat_tag3_rpn_d(64-real_addr_width to 51), + dout => lrat_tag3_rpn_q(64-real_addr_width to 51) ); +-- tag4 phase: real page number latches +lrat_tag4_rpn_latch: tri_rlmreg_p + generic map (width => lrat_tag4_rpn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(20+3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_tag4_rpn_offset to lrat_tag4_rpn_offset+lrat_tag4_rpn_q'length-1), + scout => sov(lrat_tag4_rpn_offset to lrat_tag4_rpn_offset+lrat_tag4_rpn_q'length-1), + din => lrat_tag4_rpn_d(64-real_addr_width to 51), + dout => lrat_tag4_rpn_q(64-real_addr_width to 51) ); +-- tag3 phase: hit status latches +lrat_tag3_hit_status_latch: tri_rlmreg_p + generic map (width => lrat_tag3_hit_status_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(20+2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_tag3_hit_status_offset to lrat_tag3_hit_status_offset+lrat_tag3_hit_status_q'length-1), + scout => sov(lrat_tag3_hit_status_offset to lrat_tag3_hit_status_offset+lrat_tag3_hit_status_q'length-1), + din => lrat_tag3_hit_status_d, + dout => lrat_tag3_hit_status_q ); +-- tag3 phase: hit entry latches +lrat_tag3_hit_entry_latch: tri_rlmreg_p + generic map (width => lrat_tag3_hit_entry_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(20+2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_tag3_hit_entry_offset to lrat_tag3_hit_entry_offset+lrat_tag3_hit_entry_q'length-1), + scout => sov(lrat_tag3_hit_entry_offset to lrat_tag3_hit_entry_offset+lrat_tag3_hit_entry_q'length-1), + din => lrat_tag3_hit_entry_d, + dout => lrat_tag3_hit_entry_q ); +-- tag4 phase: hit status latches +lrat_tag4_hit_status_latch: tri_rlmreg_p + generic map (width => lrat_tag4_hit_status_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(20+3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_tag4_hit_status_offset to lrat_tag4_hit_status_offset+lrat_tag4_hit_status_q'length-1), + scout => sov(lrat_tag4_hit_status_offset to lrat_tag4_hit_status_offset+lrat_tag4_hit_status_q'length-1), + din => lrat_tag4_hit_status_d, + dout => lrat_tag4_hit_status_q ); +-- tag4 phase: hit entry latches +lrat_tag4_hit_entry_latch: tri_rlmreg_p + generic map (width => lrat_tag4_hit_entry_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(20+3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_tag4_hit_entry_offset to lrat_tag4_hit_entry_offset+lrat_tag4_hit_entry_q'length-1), + scout => sov(lrat_tag4_hit_entry_offset to lrat_tag4_hit_entry_offset+lrat_tag4_hit_entry_q'length-1), + din => lrat_tag4_hit_entry_d, + dout => lrat_tag4_hit_entry_q ); +lrat_tag1_lpid_latch: tri_rlmreg_p + generic map (width => lrat_tag1_lpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(20), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_tag1_lpid_offset to lrat_tag1_lpid_offset+lrat_tag1_lpid_q'length-1), + scout => sov(lrat_tag1_lpid_offset to lrat_tag1_lpid_offset+lrat_tag1_lpid_q'length-1), + din => lrat_tag1_lpid_d, + dout => lrat_tag1_lpid_q ); +lrat_tag1_size_latch: tri_rlmreg_p + generic map (width => lrat_tag1_size_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(20), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_tag1_size_offset to lrat_tag1_size_offset+lrat_tag1_size_q'length-1), + scout => sov(lrat_tag1_size_offset to lrat_tag1_size_offset+lrat_tag1_size_q'length-1), + din => lrat_tag1_size_d, + dout => lrat_tag1_size_q ); +lrat_tag2_size_latch: tri_rlmreg_p + generic map (width => lrat_tag2_size_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(21), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_tag2_size_offset to lrat_tag2_size_offset+lrat_tag2_size_q'length-1), + scout => sov(lrat_tag2_size_offset to lrat_tag2_size_offset+lrat_tag2_size_q'length-1), + din => lrat_tag2_size_d, + dout => lrat_tag2_size_q ); +lrat_tag2_entry_size_latch: tri_rlmreg_p + generic map (width => lrat_tag2_entry_size_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(21), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_tag2_entry_size_offset to lrat_tag2_entry_size_offset+lrat_tag2_entry_size_q'length-1), + scout => sov(lrat_tag2_entry_size_offset to lrat_tag2_entry_size_offset+lrat_tag2_entry_size_q'length-1), + din => lrat_tag2_entry_size_d, + dout => lrat_tag2_entry_size_q ); +lrat_tag2_matchline_latch: tri_rlmreg_p + generic map (width => lrat_tag2_matchline_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(21), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_tag2_matchline_offset to lrat_tag2_matchline_offset+lrat_tag2_matchline_q'length-1), + scout => sov(lrat_tag2_matchline_offset to lrat_tag2_matchline_offset+lrat_tag2_matchline_q'length-1), + din => lrat_tag2_matchline_d, + dout => lrat_tag2_matchline_q ); +tlb_addr_cap_latch: tri_rlmreg_p + generic map (width => tlb_addr_cap_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_delayed_act(20), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_addr_cap_offset to tlb_addr_cap_offset+tlb_addr_cap_q'length-1), + scout => sov(tlb_addr_cap_offset to tlb_addr_cap_offset+tlb_addr_cap_q'length-1), + din => tlb_addr_cap_d, + dout => tlb_addr_cap_q ); +spare_latch: tri_rlmreg_p + generic map (width => spare_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(spare_offset to spare_offset+spare_q'length-1), + scout => sov(spare_offset to spare_offset+spare_q'length-1), + din => spare_q, + dout => spare_q ); +lrat_entry_act_latch: tri_rlmreg_p + generic map (width => lrat_entry_act_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry_act_offset to lrat_entry_act_offset+lrat_entry_act_q'length-1), + scout => sov(lrat_entry_act_offset to lrat_entry_act_offset+lrat_entry_act_q'length-1), + din => lrat_entry_act_d, + dout => lrat_entry_act_q ); +lrat_mas_act_latch: tri_rlmreg_p + generic map (width => lrat_mas_act_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_mas_act_offset to lrat_mas_act_offset+lrat_mas_act_q'length-1), + scout => sov(lrat_mas_act_offset to lrat_mas_act_offset+lrat_mas_act_q'length-1), + din => lrat_mas_act_d, + dout => lrat_mas_act_q ); +lrat_datain_act_latch: tri_rlmreg_p + generic map (width => lrat_datain_act_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_datain_act_offset to lrat_datain_act_offset+lrat_datain_act_q'length-1), + scout => sov(lrat_datain_act_offset to lrat_datain_act_offset+lrat_datain_act_q'length-1), + din => lrat_datain_act_d, + dout => lrat_datain_act_q ); +-- LRAT entry latches +lrat_entry0_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry0_valid_offset), + scout => sov(lrat_entry0_valid_offset), + din => lrat_entry0_valid_d, + dout => lrat_entry0_valid_q); +lrat_entry0_xbit_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry0_xbit_offset), + scout => sov(lrat_entry0_xbit_offset), + din => lrat_entry0_xbit_d, + dout => lrat_entry0_xbit_q); +lrat_entry0_lpn_latch: tri_rlmreg_p + generic map (width => lrat_entry0_lpn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry0_lpn_offset to lrat_entry0_lpn_offset+lrat_entry0_lpn_q'length-1), + scout => sov(lrat_entry0_lpn_offset to lrat_entry0_lpn_offset+lrat_entry0_lpn_q'length-1), + din => lrat_entry0_lpn_d, + dout => lrat_entry0_lpn_q ); +lrat_entry0_rpn_latch: tri_rlmreg_p + generic map (width => lrat_entry0_rpn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry0_rpn_offset to lrat_entry0_rpn_offset+lrat_entry0_rpn_q'length-1), + scout => sov(lrat_entry0_rpn_offset to lrat_entry0_rpn_offset+lrat_entry0_rpn_q'length-1), + din => lrat_entry0_rpn_d, + dout => lrat_entry0_rpn_q ); +lrat_entry0_lpid_latch: tri_rlmreg_p + generic map (width => lrat_entry0_lpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry0_lpid_offset to lrat_entry0_lpid_offset+lrat_entry0_lpid_q'length-1), + scout => sov(lrat_entry0_lpid_offset to lrat_entry0_lpid_offset+lrat_entry0_lpid_q'length-1), + din => lrat_entry0_lpid_d, + dout => lrat_entry0_lpid_q ); +lrat_entry0_size_latch: tri_rlmreg_p + generic map (width => lrat_entry0_size_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry0_size_offset to lrat_entry0_size_offset+lrat_entry0_size_q'length-1), + scout => sov(lrat_entry0_size_offset to lrat_entry0_size_offset+lrat_entry0_size_q'length-1), + din => lrat_entry0_size_d, + dout => lrat_entry0_size_q ); +lrat_entry0_cmpmask_latch: tri_rlmreg_p + generic map (width => lrat_entry0_cmpmask_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry0_cmpmask_offset to lrat_entry0_cmpmask_offset+lrat_entry0_cmpmask_q'length-1), + scout => sov(lrat_entry0_cmpmask_offset to lrat_entry0_cmpmask_offset+lrat_entry0_cmpmask_q'length-1), + din => lrat_entry0_cmpmask_d, + dout => lrat_entry0_cmpmask_q ); +lrat_entry0_xbitmask_latch: tri_rlmreg_p + generic map (width => lrat_entry0_xbitmask_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry0_xbitmask_offset to lrat_entry0_xbitmask_offset+lrat_entry0_xbitmask_q'length-1), + scout => sov(lrat_entry0_xbitmask_offset to lrat_entry0_xbitmask_offset+lrat_entry0_xbitmask_q'length-1), + din => lrat_entry0_xbitmask_d, + dout => lrat_entry0_xbitmask_q ); +lrat_entry1_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry1_valid_offset), + scout => sov(lrat_entry1_valid_offset), + din => lrat_entry1_valid_d, + dout => lrat_entry1_valid_q); +lrat_entry1_xbit_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry1_xbit_offset), + scout => sov(lrat_entry1_xbit_offset), + din => lrat_entry1_xbit_d, + dout => lrat_entry1_xbit_q); +lrat_entry1_lpn_latch: tri_rlmreg_p + generic map (width => lrat_entry1_lpn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry1_lpn_offset to lrat_entry1_lpn_offset+lrat_entry1_lpn_q'length-1), + scout => sov(lrat_entry1_lpn_offset to lrat_entry1_lpn_offset+lrat_entry1_lpn_q'length-1), + din => lrat_entry1_lpn_d, + dout => lrat_entry1_lpn_q ); +lrat_entry1_rpn_latch: tri_rlmreg_p + generic map (width => lrat_entry1_rpn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry1_rpn_offset to lrat_entry1_rpn_offset+lrat_entry1_rpn_q'length-1), + scout => sov(lrat_entry1_rpn_offset to lrat_entry1_rpn_offset+lrat_entry1_rpn_q'length-1), + din => lrat_entry1_rpn_d, + dout => lrat_entry1_rpn_q ); +lrat_entry1_lpid_latch: tri_rlmreg_p + generic map (width => lrat_entry1_lpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry1_lpid_offset to lrat_entry1_lpid_offset+lrat_entry1_lpid_q'length-1), + scout => sov(lrat_entry1_lpid_offset to lrat_entry1_lpid_offset+lrat_entry1_lpid_q'length-1), + din => lrat_entry1_lpid_d, + dout => lrat_entry1_lpid_q ); +lrat_entry1_size_latch: tri_rlmreg_p + generic map (width => lrat_entry1_size_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry1_size_offset to lrat_entry1_size_offset+lrat_entry1_size_q'length-1), + scout => sov(lrat_entry1_size_offset to lrat_entry1_size_offset+lrat_entry1_size_q'length-1), + din => lrat_entry1_size_d, + dout => lrat_entry1_size_q ); +lrat_entry1_cmpmask_latch: tri_rlmreg_p + generic map (width => lrat_entry1_cmpmask_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry1_cmpmask_offset to lrat_entry1_cmpmask_offset+lrat_entry1_cmpmask_q'length-1), + scout => sov(lrat_entry1_cmpmask_offset to lrat_entry1_cmpmask_offset+lrat_entry1_cmpmask_q'length-1), + din => lrat_entry1_cmpmask_d, + dout => lrat_entry1_cmpmask_q ); +lrat_entry1_xbitmask_latch: tri_rlmreg_p + generic map (width => lrat_entry1_xbitmask_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry1_xbitmask_offset to lrat_entry1_xbitmask_offset+lrat_entry1_xbitmask_q'length-1), + scout => sov(lrat_entry1_xbitmask_offset to lrat_entry1_xbitmask_offset+lrat_entry1_xbitmask_q'length-1), + din => lrat_entry1_xbitmask_d, + dout => lrat_entry1_xbitmask_q ); +lrat_entry2_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry2_valid_offset), + scout => sov(lrat_entry2_valid_offset), + din => lrat_entry2_valid_d, + dout => lrat_entry2_valid_q); +lrat_entry2_xbit_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry2_xbit_offset), + scout => sov(lrat_entry2_xbit_offset), + din => lrat_entry2_xbit_d, + dout => lrat_entry2_xbit_q); +lrat_entry2_lpn_latch: tri_rlmreg_p + generic map (width => lrat_entry2_lpn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry2_lpn_offset to lrat_entry2_lpn_offset+lrat_entry2_lpn_q'length-1), + scout => sov(lrat_entry2_lpn_offset to lrat_entry2_lpn_offset+lrat_entry2_lpn_q'length-1), + din => lrat_entry2_lpn_d, + dout => lrat_entry2_lpn_q ); +lrat_entry2_rpn_latch: tri_rlmreg_p + generic map (width => lrat_entry2_rpn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry2_rpn_offset to lrat_entry2_rpn_offset+lrat_entry2_rpn_q'length-1), + scout => sov(lrat_entry2_rpn_offset to lrat_entry2_rpn_offset+lrat_entry2_rpn_q'length-1), + din => lrat_entry2_rpn_d, + dout => lrat_entry2_rpn_q ); +lrat_entry2_lpid_latch: tri_rlmreg_p + generic map (width => lrat_entry2_lpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry2_lpid_offset to lrat_entry2_lpid_offset+lrat_entry2_lpid_q'length-1), + scout => sov(lrat_entry2_lpid_offset to lrat_entry2_lpid_offset+lrat_entry2_lpid_q'length-1), + din => lrat_entry2_lpid_d, + dout => lrat_entry2_lpid_q ); +lrat_entry2_size_latch: tri_rlmreg_p + generic map (width => lrat_entry2_size_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry2_size_offset to lrat_entry2_size_offset+lrat_entry2_size_q'length-1), + scout => sov(lrat_entry2_size_offset to lrat_entry2_size_offset+lrat_entry2_size_q'length-1), + din => lrat_entry2_size_d, + dout => lrat_entry2_size_q ); +lrat_entry2_cmpmask_latch: tri_rlmreg_p + generic map (width => lrat_entry2_cmpmask_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry2_cmpmask_offset to lrat_entry2_cmpmask_offset+lrat_entry2_cmpmask_q'length-1), + scout => sov(lrat_entry2_cmpmask_offset to lrat_entry2_cmpmask_offset+lrat_entry2_cmpmask_q'length-1), + din => lrat_entry2_cmpmask_d, + dout => lrat_entry2_cmpmask_q ); +lrat_entry2_xbitmask_latch: tri_rlmreg_p + generic map (width => lrat_entry2_xbitmask_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry2_xbitmask_offset to lrat_entry2_xbitmask_offset+lrat_entry2_xbitmask_q'length-1), + scout => sov(lrat_entry2_xbitmask_offset to lrat_entry2_xbitmask_offset+lrat_entry2_xbitmask_q'length-1), + din => lrat_entry2_xbitmask_d, + dout => lrat_entry2_xbitmask_q ); +lrat_entry3_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry3_valid_offset), + scout => sov(lrat_entry3_valid_offset), + din => lrat_entry3_valid_d, + dout => lrat_entry3_valid_q); +lrat_entry3_xbit_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry3_xbit_offset), + scout => sov(lrat_entry3_xbit_offset), + din => lrat_entry3_xbit_d, + dout => lrat_entry3_xbit_q); +lrat_entry3_lpn_latch: tri_rlmreg_p + generic map (width => lrat_entry3_lpn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry3_lpn_offset to lrat_entry3_lpn_offset+lrat_entry3_lpn_q'length-1), + scout => sov(lrat_entry3_lpn_offset to lrat_entry3_lpn_offset+lrat_entry3_lpn_q'length-1), + din => lrat_entry3_lpn_d, + dout => lrat_entry3_lpn_q ); +lrat_entry3_rpn_latch: tri_rlmreg_p + generic map (width => lrat_entry3_rpn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry3_rpn_offset to lrat_entry3_rpn_offset+lrat_entry3_rpn_q'length-1), + scout => sov(lrat_entry3_rpn_offset to lrat_entry3_rpn_offset+lrat_entry3_rpn_q'length-1), + din => lrat_entry3_rpn_d, + dout => lrat_entry3_rpn_q ); +lrat_entry3_lpid_latch: tri_rlmreg_p + generic map (width => lrat_entry3_lpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry3_lpid_offset to lrat_entry3_lpid_offset+lrat_entry3_lpid_q'length-1), + scout => sov(lrat_entry3_lpid_offset to lrat_entry3_lpid_offset+lrat_entry3_lpid_q'length-1), + din => lrat_entry3_lpid_d, + dout => lrat_entry3_lpid_q ); +lrat_entry3_size_latch: tri_rlmreg_p + generic map (width => lrat_entry3_size_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry3_size_offset to lrat_entry3_size_offset+lrat_entry3_size_q'length-1), + scout => sov(lrat_entry3_size_offset to lrat_entry3_size_offset+lrat_entry3_size_q'length-1), + din => lrat_entry3_size_d, + dout => lrat_entry3_size_q ); +lrat_entry3_cmpmask_latch: tri_rlmreg_p + generic map (width => lrat_entry3_cmpmask_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry3_cmpmask_offset to lrat_entry3_cmpmask_offset+lrat_entry3_cmpmask_q'length-1), + scout => sov(lrat_entry3_cmpmask_offset to lrat_entry3_cmpmask_offset+lrat_entry3_cmpmask_q'length-1), + din => lrat_entry3_cmpmask_d, + dout => lrat_entry3_cmpmask_q ); +lrat_entry3_xbitmask_latch: tri_rlmreg_p + generic map (width => lrat_entry3_xbitmask_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(3), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry3_xbitmask_offset to lrat_entry3_xbitmask_offset+lrat_entry3_xbitmask_q'length-1), + scout => sov(lrat_entry3_xbitmask_offset to lrat_entry3_xbitmask_offset+lrat_entry3_xbitmask_q'length-1), + din => lrat_entry3_xbitmask_d, + dout => lrat_entry3_xbitmask_q ); +lrat_entry4_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(4), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry4_valid_offset), + scout => sov(lrat_entry4_valid_offset), + din => lrat_entry4_valid_d, + dout => lrat_entry4_valid_q); +lrat_entry4_xbit_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(4), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry4_xbit_offset), + scout => sov(lrat_entry4_xbit_offset), + din => lrat_entry4_xbit_d, + dout => lrat_entry4_xbit_q); +lrat_entry4_lpn_latch: tri_rlmreg_p + generic map (width => lrat_entry4_lpn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(4), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry4_lpn_offset to lrat_entry4_lpn_offset+lrat_entry4_lpn_q'length-1), + scout => sov(lrat_entry4_lpn_offset to lrat_entry4_lpn_offset+lrat_entry4_lpn_q'length-1), + din => lrat_entry4_lpn_d, + dout => lrat_entry4_lpn_q ); +lrat_entry4_rpn_latch: tri_rlmreg_p + generic map (width => lrat_entry4_rpn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(4), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry4_rpn_offset to lrat_entry4_rpn_offset+lrat_entry4_rpn_q'length-1), + scout => sov(lrat_entry4_rpn_offset to lrat_entry4_rpn_offset+lrat_entry4_rpn_q'length-1), + din => lrat_entry4_rpn_d, + dout => lrat_entry4_rpn_q ); +lrat_entry4_lpid_latch: tri_rlmreg_p + generic map (width => lrat_entry4_lpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(4), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry4_lpid_offset to lrat_entry4_lpid_offset+lrat_entry4_lpid_q'length-1), + scout => sov(lrat_entry4_lpid_offset to lrat_entry4_lpid_offset+lrat_entry4_lpid_q'length-1), + din => lrat_entry4_lpid_d, + dout => lrat_entry4_lpid_q ); +lrat_entry4_size_latch: tri_rlmreg_p + generic map (width => lrat_entry4_size_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(4), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry4_size_offset to lrat_entry4_size_offset+lrat_entry4_size_q'length-1), + scout => sov(lrat_entry4_size_offset to lrat_entry4_size_offset+lrat_entry4_size_q'length-1), + din => lrat_entry4_size_d, + dout => lrat_entry4_size_q ); +lrat_entry4_cmpmask_latch: tri_rlmreg_p + generic map (width => lrat_entry4_cmpmask_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(4), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry4_cmpmask_offset to lrat_entry4_cmpmask_offset+lrat_entry4_cmpmask_q'length-1), + scout => sov(lrat_entry4_cmpmask_offset to lrat_entry4_cmpmask_offset+lrat_entry4_cmpmask_q'length-1), + din => lrat_entry4_cmpmask_d, + dout => lrat_entry4_cmpmask_q ); +lrat_entry4_xbitmask_latch: tri_rlmreg_p + generic map (width => lrat_entry4_xbitmask_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(4), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry4_xbitmask_offset to lrat_entry4_xbitmask_offset+lrat_entry4_xbitmask_q'length-1), + scout => sov(lrat_entry4_xbitmask_offset to lrat_entry4_xbitmask_offset+lrat_entry4_xbitmask_q'length-1), + din => lrat_entry4_xbitmask_d, + dout => lrat_entry4_xbitmask_q ); +lrat_entry5_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(5), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry5_valid_offset), + scout => sov(lrat_entry5_valid_offset), + din => lrat_entry5_valid_d, + dout => lrat_entry5_valid_q); +lrat_entry5_xbit_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(5), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry5_xbit_offset), + scout => sov(lrat_entry5_xbit_offset), + din => lrat_entry5_xbit_d, + dout => lrat_entry5_xbit_q); +lrat_entry5_lpn_latch: tri_rlmreg_p + generic map (width => lrat_entry5_lpn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(5), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry5_lpn_offset to lrat_entry5_lpn_offset+lrat_entry5_lpn_q'length-1), + scout => sov(lrat_entry5_lpn_offset to lrat_entry5_lpn_offset+lrat_entry5_lpn_q'length-1), + din => lrat_entry5_lpn_d, + dout => lrat_entry5_lpn_q ); +lrat_entry5_rpn_latch: tri_rlmreg_p + generic map (width => lrat_entry5_rpn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(5), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry5_rpn_offset to lrat_entry5_rpn_offset+lrat_entry5_rpn_q'length-1), + scout => sov(lrat_entry5_rpn_offset to lrat_entry5_rpn_offset+lrat_entry5_rpn_q'length-1), + din => lrat_entry5_rpn_d, + dout => lrat_entry5_rpn_q ); +lrat_entry5_lpid_latch: tri_rlmreg_p + generic map (width => lrat_entry5_lpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(5), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry5_lpid_offset to lrat_entry5_lpid_offset+lrat_entry5_lpid_q'length-1), + scout => sov(lrat_entry5_lpid_offset to lrat_entry5_lpid_offset+lrat_entry5_lpid_q'length-1), + din => lrat_entry5_lpid_d, + dout => lrat_entry5_lpid_q ); +lrat_entry5_size_latch: tri_rlmreg_p + generic map (width => lrat_entry5_size_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(5), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry5_size_offset to lrat_entry5_size_offset+lrat_entry5_size_q'length-1), + scout => sov(lrat_entry5_size_offset to lrat_entry5_size_offset+lrat_entry5_size_q'length-1), + din => lrat_entry5_size_d, + dout => lrat_entry5_size_q ); +lrat_entry5_cmpmask_latch: tri_rlmreg_p + generic map (width => lrat_entry5_cmpmask_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(5), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry5_cmpmask_offset to lrat_entry5_cmpmask_offset+lrat_entry5_cmpmask_q'length-1), + scout => sov(lrat_entry5_cmpmask_offset to lrat_entry5_cmpmask_offset+lrat_entry5_cmpmask_q'length-1), + din => lrat_entry5_cmpmask_d, + dout => lrat_entry5_cmpmask_q ); +lrat_entry5_xbitmask_latch: tri_rlmreg_p + generic map (width => lrat_entry5_xbitmask_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(5), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry5_xbitmask_offset to lrat_entry5_xbitmask_offset+lrat_entry5_xbitmask_q'length-1), + scout => sov(lrat_entry5_xbitmask_offset to lrat_entry5_xbitmask_offset+lrat_entry5_xbitmask_q'length-1), + din => lrat_entry5_xbitmask_d, + dout => lrat_entry5_xbitmask_q ); +lrat_entry6_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(6), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry6_valid_offset), + scout => sov(lrat_entry6_valid_offset), + din => lrat_entry6_valid_d, + dout => lrat_entry6_valid_q); +lrat_entry6_xbit_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(6), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry6_xbit_offset), + scout => sov(lrat_entry6_xbit_offset), + din => lrat_entry6_xbit_d, + dout => lrat_entry6_xbit_q); +lrat_entry6_lpn_latch: tri_rlmreg_p + generic map (width => lrat_entry6_lpn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(6), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry6_lpn_offset to lrat_entry6_lpn_offset+lrat_entry6_lpn_q'length-1), + scout => sov(lrat_entry6_lpn_offset to lrat_entry6_lpn_offset+lrat_entry6_lpn_q'length-1), + din => lrat_entry6_lpn_d, + dout => lrat_entry6_lpn_q ); +lrat_entry6_rpn_latch: tri_rlmreg_p + generic map (width => lrat_entry6_rpn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(6), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry6_rpn_offset to lrat_entry6_rpn_offset+lrat_entry6_rpn_q'length-1), + scout => sov(lrat_entry6_rpn_offset to lrat_entry6_rpn_offset+lrat_entry6_rpn_q'length-1), + din => lrat_entry6_rpn_d, + dout => lrat_entry6_rpn_q ); +lrat_entry6_lpid_latch: tri_rlmreg_p + generic map (width => lrat_entry6_lpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(6), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry6_lpid_offset to lrat_entry6_lpid_offset+lrat_entry6_lpid_q'length-1), + scout => sov(lrat_entry6_lpid_offset to lrat_entry6_lpid_offset+lrat_entry6_lpid_q'length-1), + din => lrat_entry6_lpid_d, + dout => lrat_entry6_lpid_q ); +lrat_entry6_size_latch: tri_rlmreg_p + generic map (width => lrat_entry6_size_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(6), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry6_size_offset to lrat_entry6_size_offset+lrat_entry6_size_q'length-1), + scout => sov(lrat_entry6_size_offset to lrat_entry6_size_offset+lrat_entry6_size_q'length-1), + din => lrat_entry6_size_d, + dout => lrat_entry6_size_q ); +lrat_entry6_cmpmask_latch: tri_rlmreg_p + generic map (width => lrat_entry6_cmpmask_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(6), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry6_cmpmask_offset to lrat_entry6_cmpmask_offset+lrat_entry6_cmpmask_q'length-1), + scout => sov(lrat_entry6_cmpmask_offset to lrat_entry6_cmpmask_offset+lrat_entry6_cmpmask_q'length-1), + din => lrat_entry6_cmpmask_d, + dout => lrat_entry6_cmpmask_q ); +lrat_entry6_xbitmask_latch: tri_rlmreg_p + generic map (width => lrat_entry6_xbitmask_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(6), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry6_xbitmask_offset to lrat_entry6_xbitmask_offset+lrat_entry6_xbitmask_q'length-1), + scout => sov(lrat_entry6_xbitmask_offset to lrat_entry6_xbitmask_offset+lrat_entry6_xbitmask_q'length-1), + din => lrat_entry6_xbitmask_d, + dout => lrat_entry6_xbitmask_q ); +lrat_entry7_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(7), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry7_valid_offset), + scout => sov(lrat_entry7_valid_offset), + din => lrat_entry7_valid_d, + dout => lrat_entry7_valid_q); +lrat_entry7_xbit_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(7), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry7_xbit_offset), + scout => sov(lrat_entry7_xbit_offset), + din => lrat_entry7_xbit_d, + dout => lrat_entry7_xbit_q); +lrat_entry7_lpn_latch: tri_rlmreg_p + generic map (width => lrat_entry7_lpn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(7), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry7_lpn_offset to lrat_entry7_lpn_offset+lrat_entry7_lpn_q'length-1), + scout => sov(lrat_entry7_lpn_offset to lrat_entry7_lpn_offset+lrat_entry7_lpn_q'length-1), + din => lrat_entry7_lpn_d, + dout => lrat_entry7_lpn_q ); +lrat_entry7_rpn_latch: tri_rlmreg_p + generic map (width => lrat_entry7_rpn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(7), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry7_rpn_offset to lrat_entry7_rpn_offset+lrat_entry7_rpn_q'length-1), + scout => sov(lrat_entry7_rpn_offset to lrat_entry7_rpn_offset+lrat_entry7_rpn_q'length-1), + din => lrat_entry7_rpn_d, + dout => lrat_entry7_rpn_q ); +lrat_entry7_lpid_latch: tri_rlmreg_p + generic map (width => lrat_entry7_lpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(7), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry7_lpid_offset to lrat_entry7_lpid_offset+lrat_entry7_lpid_q'length-1), + scout => sov(lrat_entry7_lpid_offset to lrat_entry7_lpid_offset+lrat_entry7_lpid_q'length-1), + din => lrat_entry7_lpid_d, + dout => lrat_entry7_lpid_q ); +lrat_entry7_size_latch: tri_rlmreg_p + generic map (width => lrat_entry7_size_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(7), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry7_size_offset to lrat_entry7_size_offset+lrat_entry7_size_q'length-1), + scout => sov(lrat_entry7_size_offset to lrat_entry7_size_offset+lrat_entry7_size_q'length-1), + din => lrat_entry7_size_d, + dout => lrat_entry7_size_q ); +lrat_entry7_cmpmask_latch: tri_rlmreg_p + generic map (width => lrat_entry7_cmpmask_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(7), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry7_cmpmask_offset to lrat_entry7_cmpmask_offset+lrat_entry7_cmpmask_q'length-1), + scout => sov(lrat_entry7_cmpmask_offset to lrat_entry7_cmpmask_offset+lrat_entry7_cmpmask_q'length-1), + din => lrat_entry7_cmpmask_d, + dout => lrat_entry7_cmpmask_q ); +lrat_entry7_xbitmask_latch: tri_rlmreg_p + generic map (width => lrat_entry7_xbitmask_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_entry_act_q(7), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_entry7_xbitmask_offset to lrat_entry7_xbitmask_offset+lrat_entry7_xbitmask_q'length-1), + scout => sov(lrat_entry7_xbitmask_offset to lrat_entry7_xbitmask_offset+lrat_entry7_xbitmask_q'length-1), + din => lrat_entry7_xbitmask_d, + dout => lrat_entry7_xbitmask_q ); +lrat_datain_lpn_latch: tri_rlmreg_p + generic map (width => lrat_datain_lpn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_datain_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_datain_lpn_offset to lrat_datain_lpn_offset+lrat_datain_lpn_q'length-1), + scout => sov(lrat_datain_lpn_offset to lrat_datain_lpn_offset+lrat_datain_lpn_q'length-1), + din => lrat_datain_lpn_d, + dout => lrat_datain_lpn_q ); +lrat_datain_rpn_latch: tri_rlmreg_p + generic map (width => lrat_datain_rpn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_datain_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_datain_rpn_offset to lrat_datain_rpn_offset+lrat_datain_rpn_q'length-1), + scout => sov(lrat_datain_rpn_offset to lrat_datain_rpn_offset+lrat_datain_rpn_q'length-1), + din => lrat_datain_rpn_d, + dout => lrat_datain_rpn_q ); +lrat_datain_lpid_latch: tri_rlmreg_p + generic map (width => lrat_datain_lpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_datain_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_datain_lpid_offset to lrat_datain_lpid_offset+lrat_datain_lpid_q'length-1), + scout => sov(lrat_datain_lpid_offset to lrat_datain_lpid_offset+lrat_datain_lpid_q'length-1), + din => lrat_datain_lpid_d, + dout => lrat_datain_lpid_q ); +lrat_datain_size_latch: tri_rlmreg_p + generic map (width => lrat_datain_size_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_datain_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_datain_size_offset to lrat_datain_size_offset+lrat_datain_size_q'length-1), + scout => sov(lrat_datain_size_offset to lrat_datain_size_offset+lrat_datain_size_q'length-1), + din => lrat_datain_size_d, + dout => lrat_datain_size_q ); +lrat_datain_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_datain_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_datain_valid_offset), + scout => sov(lrat_datain_valid_offset), + din => lrat_datain_valid_d, + dout => lrat_datain_valid_q); +lrat_datain_xbit_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_datain_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_datain_xbit_offset), + scout => sov(lrat_datain_xbit_offset), + din => lrat_datain_xbit_d, + dout => lrat_datain_xbit_q); +lrat_mas1_v_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_mas_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_mas1_v_offset), + scout => sov(lrat_mas1_v_offset), + din => lrat_mas1_v_d, + dout => lrat_mas1_v_q); +lrat_mmucr3_x_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_mas_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_mmucr3_x_offset), + scout => sov(lrat_mmucr3_x_offset), + din => lrat_mmucr3_x_d, + dout => lrat_mmucr3_x_q); +lrat_mas1_tsize_latch: tri_rlmreg_p + generic map (width => lrat_mas1_tsize_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_mas_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_mas1_tsize_offset to lrat_mas1_tsize_offset+lrat_mas1_tsize_q'length-1), + scout => sov(lrat_mas1_tsize_offset to lrat_mas1_tsize_offset+lrat_mas1_tsize_q'length-1), + din => lrat_mas1_tsize_d, + dout => lrat_mas1_tsize_q ); +lrat_mas2_epn_latch: tri_rlmreg_p + generic map (width => lrat_mas2_epn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_mas_act_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_mas2_epn_offset to lrat_mas2_epn_offset+lrat_mas2_epn_q'length-1), + scout => sov(lrat_mas2_epn_offset to lrat_mas2_epn_offset+lrat_mas2_epn_q'length-1), + din => lrat_mas2_epn_d, + dout => lrat_mas2_epn_q ); +lrat_mas3_rpnl_latch: tri_rlmreg_p + generic map (width => lrat_mas3_rpnl_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_mas_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_mas3_rpnl_offset to lrat_mas3_rpnl_offset+lrat_mas3_rpnl_q'length-1), + scout => sov(lrat_mas3_rpnl_offset to lrat_mas3_rpnl_offset+lrat_mas3_rpnl_q'length-1), + din => lrat_mas3_rpnl_d, + dout => lrat_mas3_rpnl_q ); +lrat_mas7_rpnu_latch: tri_rlmreg_p + generic map (width => lrat_mas7_rpnu_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_mas_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_mas7_rpnu_offset to lrat_mas7_rpnu_offset+lrat_mas7_rpnu_q'length-1), + scout => sov(lrat_mas7_rpnu_offset to lrat_mas7_rpnu_offset+lrat_mas7_rpnu_q'length-1), + din => lrat_mas7_rpnu_d, + dout => lrat_mas7_rpnu_q ); +lrat_mas8_tlpid_latch: tri_rlmreg_p + generic map (width => lrat_mas8_tlpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_mas_act_q(1), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_mas8_tlpid_offset to lrat_mas8_tlpid_offset+lrat_mas8_tlpid_q'length-1), + scout => sov(lrat_mas8_tlpid_offset to lrat_mas8_tlpid_offset+lrat_mas8_tlpid_q'length-1), + din => lrat_mas8_tlpid_d, + dout => lrat_mas8_tlpid_q ); +lrat_mas_thdid_latch: tri_rlmreg_p + generic map (width => lrat_mas_thdid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_mas_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_mas_thdid_offset to lrat_mas_thdid_offset+lrat_mas_thdid_q'length-1), + scout => sov(lrat_mas_thdid_offset to lrat_mas_thdid_offset+lrat_mas_thdid_q'length-1), + din => lrat_mas_thdid_d, + dout => lrat_mas_thdid_q ); +lrat_mas_tlbre_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_mas_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_mas_tlbre_offset), + scout => sov(lrat_mas_tlbre_offset), + din => lrat_mas_tlbre_d, + dout => lrat_mas_tlbre_q ); +lrat_mas_tlbsx_hit_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_mas_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_mas_tlbsx_hit_offset), + scout => sov(lrat_mas_tlbsx_hit_offset), + din => lrat_mas_tlbsx_hit_d, + dout => lrat_mas_tlbsx_hit_q ); +lrat_mas_tlbsx_miss_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lrat_mas_act_q(2), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(lrat_mas_tlbsx_miss_offset), + scout => sov(lrat_mas_tlbsx_miss_offset), + din => lrat_mas_tlbsx_miss_d, + dout => lrat_mas_tlbsx_miss_q ); +-------------------------------------------------- +-- thold/sg latches +-------------------------------------------------- +perv_2to1_reg: tri_plat + generic map (width => 3, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ccflush_dc, + din(0) => pc_func_sl_thold_2, + din(1) => pc_func_slp_sl_thold_2, + din(2) => pc_sg_2, + q(0) => pc_func_sl_thold_1, + q(1) => pc_func_slp_sl_thold_1, + q(2) => pc_sg_1); +perv_1to0_reg: tri_plat + generic map (width => 3, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ccflush_dc, + din(0) => pc_func_sl_thold_1, + din(1) => pc_func_slp_sl_thold_1, + din(2) => pc_sg_1, + q(0) => pc_func_sl_thold_0, + q(1) => pc_func_slp_sl_thold_0, + q(2) => pc_sg_0); +perv_lcbor_func_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b, + thold => pc_func_sl_thold_0, + sg => pc_sg_0, + act_dis => lcb_act_dis_dc, + forcee => pc_func_sl_force, + thold_b => pc_func_sl_thold_0_b); +perv_lcbor_func_slp_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b, + thold => pc_func_slp_sl_thold_0, + sg => pc_sg_0, + act_dis => lcb_act_dis_dc, + forcee => pc_func_slp_sl_force, + thold_b => pc_func_slp_sl_thold_0_b); +----------------------------------------------------------------------- +-- Scan +----------------------------------------------------------------------- +siv(0 TO scan_right) <= sov(1 to scan_right) & ac_func_scan_in; +ac_func_scan_out <= sov(0); +END MMQ_TLB_LRAT; diff --git a/rel/src/vhdl/work/mmq_tlb_lrat_matchline.vhdl b/rel/src/vhdl/work/mmq_tlb_lrat_matchline.vhdl new file mode 100644 index 0000000..e47a83d --- /dev/null +++ b/rel/src/vhdl/work/mmq_tlb_lrat_matchline.vhdl @@ -0,0 +1,370 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +--******************************************************************** +--* +--* TITLE: MMU TLB LRAT Match Line Logic for Functional Model +--* +--* NAME: mmq_tlb_lrat_matchline +--* + +LIBRARY IEEE; +USE ieee.std_logic_1164.ALL ; +LIBRARY IBM; +USE ibm.std_ulogic_support.ALL; +USE ibm.std_ulogic_function_support.ALL; +library support; +use support.power_logic_pkg.all; + +------------------------------------------------------------------------ +-- Entity +------------------------------------------------------------------------ + +entity mmq_tlb_lrat_matchline is + generic (real_addr_width : integer := 42; + lpid_width : integer := 8; + lrat_maxsize_log2 : integer := 40; -- 1T largest pgsize + lrat_minsize_log2 : integer := 20; -- 1M smallest pgsize + have_xbit : integer := 1; + num_pgsizes : integer := 8; + have_cmpmask : integer := 1; + cmpmask_width : integer := 7); + +port( -- @{default:nclk}@ + vdd : inout power_logic; + gnd : inout power_logic; + addr_in : in std_ulogic_vector(64-real_addr_width to 64-lrat_minsize_log2-1); + addr_enable : in std_ulogic; + entry_size : in std_ulogic_vector(0 to 3); + entry_cmpmask : in std_ulogic_vector(0 to cmpmask_width-1); + entry_xbit : in std_ulogic; + entry_xbitmask : in std_ulogic_vector(0 to cmpmask_width-1); + entry_lpn : in std_ulogic_vector(64-real_addr_width to 64-lrat_minsize_log2-1); + entry_lpid : in std_ulogic_vector(0 to lpid_width-1); + comp_lpid : in std_ulogic_vector(0 to lpid_width-1); + lpid_enable : in std_ulogic; + entry_v : in std_ulogic; + + match : out std_ulogic; + + dbg_addr_match : out std_ulogic; + dbg_lpid_match : out std_ulogic + +); + + -- synopsys translate_off + -- synopsys translate_on + +end mmq_tlb_lrat_matchline; + +architecture mmq_tlb_lrat_matchline of mmq_tlb_lrat_matchline is + +------------------------------------------------------------------------ +-- Signals +------------------------------------------------------------------------ + + signal entry_lpn_b : std_ulogic_vector(64-lrat_maxsize_log2 to 64-lrat_minsize_log2-1); + signal function_24_43 : std_ulogic; + signal function_26_43 : std_ulogic; + signal function_30_43 : std_ulogic; + signal function_32_43 : std_ulogic; + signal function_34_43 : std_ulogic; + signal function_36_43 : std_ulogic; + signal function_40_43 : std_ulogic; + signal pgsize_eq_16M : std_ulogic; -- PS7 + signal pgsize_eq_256M : std_ulogic; -- PS9 + signal pgsize_eq_1G : std_ulogic; -- PS10 + signal pgsize_eq_4G : std_ulogic; -- PS11 + signal pgsize_eq_16G : std_ulogic; -- PS12 + signal pgsize_eq_256G : std_ulogic; -- PS14 + signal pgsize_eq_1T : std_ulogic; -- PS15 + signal pgsize_gte_16M : std_ulogic; -- PS7 + signal pgsize_gte_256M : std_ulogic; -- PS9 + signal pgsize_gte_1G : std_ulogic; -- PS10 + signal pgsize_gte_4G : std_ulogic; -- PS11 + signal pgsize_gte_16G : std_ulogic; -- PS12 + signal pgsize_gte_256G : std_ulogic; -- PS14 + signal pgsize_gte_1T : std_ulogic; -- PS15 + + signal comp_or_24_25 : std_ulogic; + signal comp_or_26_29 : std_ulogic; + signal comp_or_30_31 : std_ulogic; + signal comp_or_32_33 : std_ulogic; + signal comp_or_34_35 : std_ulogic; + signal comp_or_36_39 : std_ulogic; + signal comp_or_40_43 : std_ulogic; + + signal match_line : std_ulogic_vector(64-real_addr_width to 64-lrat_minsize_log2+lpid_width-1); + signal addr_match : std_ulogic; + signal lpid_match : std_ulogic; + +signal unused_dc : std_ulogic; +-- synopsys translate_off +-- synopsys translate_on + +begin + + match_line(64-real_addr_width to 64-lrat_minsize_log2+lpid_width-1) <= not( + (entry_lpn(64-real_addr_width to 64-lrat_minsize_log2-1) & entry_lpid(0 to lpid_width-1)) xor + (addr_in(64-real_addr_width to 64-lrat_minsize_log2-1) & comp_lpid(0 to lpid_width-1)) + ); + +numpgsz8 : if num_pgsizes = 8 generate + + entry_lpn_b(64-lrat_maxsize_log2 to 64-lrat_minsize_log2-1) <= not(entry_lpn(64-lrat_maxsize_log2 to 64-lrat_minsize_log2-1)); + + +gen_nocmpmask80 : if have_cmpmask = 0 generate + pgsize_eq_16M <= '1' when (entry_size="0111") -- PS7 + else '0'; + pgsize_eq_256M <= '1' when (entry_size="1001") -- PS9 + else '0'; + pgsize_eq_1G <= '1' when (entry_size="1010") -- PS10 + else '0'; + pgsize_eq_4G <= '1' when (entry_size="1011") -- PS11 + else '0'; + pgsize_eq_16G <= '1' when (entry_size="1100") -- PS12 + else '0'; + pgsize_eq_256G <= '1' when (entry_size="1110") -- PS14 + else '0'; + pgsize_eq_1T <= '1' when (entry_size="1111") -- PS15 + else '0'; + + pgsize_gte_16M <= '1' when (entry_size="0111" or -- PS7 or larger + pgsize_gte_256M='1') + else '0'; + pgsize_gte_256M <= '1' when (entry_size="1001" or -- PS9 or larger + pgsize_gte_1G='1') + else '0'; + pgsize_gte_1G <= '1' when (entry_size="1010" or -- PS10 or larger + pgsize_gte_4G='1') + else '0'; + pgsize_gte_4G <= '1' when (entry_size="1011" or -- PS11 or larger + pgsize_gte_16G='1') + else '0'; + pgsize_gte_16G <= '1' when (entry_size="1100" or -- PS12 or larger + pgsize_gte_256G='1') + else '0'; + pgsize_gte_256G <= '1' when (entry_size="1110" or -- PS14 or larger + pgsize_gte_1T='1') + else '0'; + pgsize_gte_1T <= '1' when (entry_size="1111") -- PS15 + else '0'; + +end generate gen_nocmpmask80; + +gen_cmpmask80 : if have_cmpmask = 1 generate +-- size entry_cmpmask: 0123456 +-- 1TB 1111111 +-- 256GB 0111111 +-- 16GB 0011111 +-- 4GB 0001111 +-- 1GB 0000111 +-- 256MB 0000011 +-- 16MB 0000001 +-- 1MB 0000000 + pgsize_gte_1T <= entry_cmpmask(0); + pgsize_gte_256G <= entry_cmpmask(1); + pgsize_gte_16G <= entry_cmpmask(2); + pgsize_gte_4G <= entry_cmpmask(3); + pgsize_gte_1G <= entry_cmpmask(4); + pgsize_gte_256M <= entry_cmpmask(5); + pgsize_gte_16M <= entry_cmpmask(6); + +-- size entry_xbitmask: 0123456 +-- 1TB 1000000 +-- 256GB 0100000 +-- 16GB 0010000 +-- 4GB 0001000 +-- 1GB 0000100 +-- 256MB 0000010 +-- 16MB 0000001 +-- 1MB 0000000 + pgsize_eq_1T <= entry_xbitmask(0); + pgsize_eq_256G <= entry_xbitmask(1); + pgsize_eq_16G <= entry_xbitmask(2); + pgsize_eq_4G <= entry_xbitmask(3); + pgsize_eq_1G <= entry_xbitmask(4); + pgsize_eq_256M <= entry_xbitmask(5); + pgsize_eq_16M <= entry_xbitmask(6); +end generate gen_cmpmask80; + + + +gen_noxbit80 : if have_xbit = 0 generate + function_24_43 <= '0'; + function_26_43 <= '0'; + function_30_43 <= '0'; + function_32_43 <= '0'; + function_34_43 <= '0'; + function_36_43 <= '0'; + function_40_43 <= '0'; +end generate gen_noxbit80; + +gen_xbit80 : if (have_xbit /= 0 and real_addr_width=42) generate + function_24_43 <= not(entry_xbit) or + not(pgsize_eq_1T) or + or_reduce(entry_lpn_b(24 to 43) and addr_in(24 to 43)); + function_26_43 <= not(entry_xbit) or + not(pgsize_eq_256G) or + or_reduce(entry_lpn_b(26 to 43) and addr_in(26 to 43)); + function_30_43 <= not(entry_xbit) or + not(pgsize_eq_16G) or + or_reduce(entry_lpn_b(30 to 43) and addr_in(30 to 43)); + function_32_43 <= not(entry_xbit) or + not(pgsize_eq_4G) or + or_reduce(entry_lpn_b(32 to 43) and addr_in(32 to 43)); + function_34_43 <= not(entry_xbit) or + not(pgsize_eq_1G) or + or_reduce(entry_lpn_b(34 to 43) and addr_in(34 to 43)); + function_36_43 <= not(entry_xbit) or + not(pgsize_eq_256M) or + or_reduce(entry_lpn_b(36 to 43) and addr_in(36 to 43)); + function_40_43 <= not(entry_xbit) or + not(pgsize_eq_16M) or + or_reduce(entry_lpn_b(40 to 43) and addr_in(40 to 43)); +end generate gen_xbit80; + +gen_xbit81 : if (have_xbit /= 0 and real_addr_width=32) generate + function_24_43 <= '1'; + function_26_43 <= '1'; + function_30_43 <= '1'; + function_32_43 <= '1'; + function_34_43 <= not(entry_xbit) or + not(pgsize_eq_1G) or + or_reduce(entry_lpn_b(34 to 43) and addr_in(34 to 43)); + function_36_43 <= not(entry_xbit) or + not(pgsize_eq_256M) or + or_reduce(entry_lpn_b(36 to 43) and addr_in(36 to 43)); + function_40_43 <= not(entry_xbit) or + not(pgsize_eq_16M) or + or_reduce(entry_lpn_b(40 to 43) and addr_in(40 to 43)); +end generate gen_xbit81; + +gen_comp80 : if real_addr_width=42 generate + comp_or_24_25 <= and_reduce(match_line(24 to 25)) or pgsize_gte_1T; + comp_or_26_29 <= and_reduce(match_line(26 to 29)) or pgsize_gte_256G; + comp_or_30_31 <= and_reduce(match_line(30 to 31)) or pgsize_gte_16G; + comp_or_32_33 <= and_reduce(match_line(32 to 33)) or pgsize_gte_4G; + comp_or_34_35 <= and_reduce(match_line(34 to 35)) or pgsize_gte_1G; + comp_or_36_39 <= and_reduce(match_line(36 to 39)) or pgsize_gte_256M; + comp_or_40_43 <= and_reduce(match_line(40 to 43)) or pgsize_gte_16M; +end generate gen_comp80; + +gen_comp81 : if real_addr_width=32 generate + comp_or_24_25 <= '1'; + comp_or_26_29 <= '1'; + comp_or_30_31 <= '1'; + comp_or_32_33 <= '1'; + comp_or_34_35 <= and_reduce(match_line(34 to 35)) or pgsize_gte_1G; + comp_or_36_39 <= and_reduce(match_line(36 to 39)) or pgsize_gte_256M; + comp_or_40_43 <= and_reduce(match_line(40 to 43)) or pgsize_gte_16M; +end generate gen_comp81; + +gen_noxbit81 : if (have_xbit = 0 and real_addr_width=42) generate + addr_match <= ( and_reduce(match_line(22 to 23)) and + comp_or_24_25 and -- Ignore functions based on page size + comp_or_26_29 and + comp_or_30_31 and + comp_or_32_33 and + comp_or_34_35 and + comp_or_36_39 and + comp_or_40_43 ) or -- Regular compare largest page size + not(addr_enable); -- Include address as part of compare, + -- should never ignore for regular compare/read. + -- Could ignore for compare/invalidate +end generate gen_noxbit81; + +gen_noxbit82 : if (have_xbit = 0 and real_addr_width=32) generate + addr_match <= ( and_reduce(match_line(32 to 33)) and + comp_or_34_35 and -- Ignore functions based on page size + comp_or_36_39 and + comp_or_40_43 ) or -- Regular compare largest page size + not(addr_enable); -- Include address as part of compare, + -- should never ignore for regular compare/read. + -- Could ignore for compare/invalidate +end generate gen_noxbit82; + +gen_xbit82 : if (have_xbit /= 0 and real_addr_width=42) generate + addr_match <= (and_reduce(match_line(22 to 23)) and + comp_or_24_25 and -- Ignore functions based on page size + comp_or_26_29 and + comp_or_30_31 and + comp_or_32_33 and + comp_or_34_35 and + comp_or_36_39 and + comp_or_40_43 and + function_24_43 and -- Exclusion functions + function_26_43 and + function_30_43 and + function_32_43 and + function_34_43 and + function_36_43 and + function_40_43) or -- Regular compare largest page size + not(addr_enable); -- Include address as part of compare, + -- should never ignore for regular compare/read. + -- Could ignore for compare/invalidate +end generate gen_xbit82; + +gen_xbit83 : if (have_xbit /= 0 and real_addr_width=32) generate + addr_match <= (and_reduce(match_line(32 to 33)) and + comp_or_34_35 and -- Ignore functions based on page size + comp_or_36_39 and + comp_or_40_43 and + function_34_43 and -- Exclusion functions + function_36_43 and + function_40_43) or -- Regular compare largest page size + not(addr_enable); -- Include address as part of compare, + -- should never ignore for regular compare/read. + -- Could ignore for compare/invalidate +end generate gen_xbit83; + +end generate numpgsz8; -- numpgsz8: num_pgsizes = 8 + + + -- entry_lpid=0 ignores lpid match for translation, not invalidation + lpid_match <= and_reduce(match_line(64-lrat_minsize_log2 to 64-lrat_minsize_log2+lpid_width-1)) or + not(or_reduce(entry_lpid(0 to 7))) or + not(lpid_enable); + + match <= addr_match and -- Address compare + lpid_match and -- LPID compare + entry_v; -- Valid + + -- debug outputs + dbg_addr_match <= addr_match; -- out std_ulogic; + dbg_lpid_match <= lpid_match; -- out std_ulogic; + +gen_unused0 : if have_cmpmask = 0 generate + unused_dc <= '0'; +end generate gen_unused0; +gen_unused1 : if have_cmpmask = 1 generate + unused_dc <= or_reduce(entry_size); +end generate gen_unused1; + +end mmq_tlb_lrat_matchline; diff --git a/rel/src/vhdl/work/mmq_tlb_matchline.vhdl b/rel/src/vhdl/work/mmq_tlb_matchline.vhdl new file mode 100644 index 0000000..29207bc --- /dev/null +++ b/rel/src/vhdl/work/mmq_tlb_matchline.vhdl @@ -0,0 +1,642 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +--******************************************************************** +--* +--* TITLE: MMU TLB Match Line Logic for Functional Model +--* +--* NAME: mmq_tlb_matchline +--* + +LIBRARY IEEE; +USE ieee.std_logic_1164.ALL ; +LIBRARY IBM; +USE ibm.std_ulogic_support.ALL; +USE ibm.std_ulogic_function_support.ALL; +library support; +use support.power_logic_pkg.all; + +------------------------------------------------------------------------ +-- Entity +------------------------------------------------------------------------ + +entity mmq_tlb_matchline is + generic (have_xbit : integer := 1; + num_pgsizes : integer := 5; + have_cmpmask : integer := 1; + cmpmask_width : integer := 5); + +port( -- @{default:nclk}@ + vdd : inout power_logic; + gnd : inout power_logic; + addr_in : in std_ulogic_vector(0 to 51); + addr_enable : in std_ulogic_vector(0 to 8); + comp_pgsize : in std_ulogic_vector(0 to 3); + pgsize_enable : in std_ulogic; + entry_size : in std_ulogic_vector(0 to 3); + entry_cmpmask : in std_ulogic_vector(0 to cmpmask_width-1); + entry_xbit : in std_ulogic; + entry_xbitmask : in std_ulogic_vector(0 to cmpmask_width-1); + entry_epn : in std_ulogic_vector(0 to 51); + comp_class : in std_ulogic_vector(0 to 1); + entry_class : in std_ulogic_vector(0 to 1); + class_enable : in std_ulogic; + comp_extclass : in std_ulogic_vector(0 to 1); + entry_extclass : in std_ulogic_vector(0 to 1); + extclass_enable : in std_ulogic_vector(0 to 1); + comp_state : in std_ulogic_vector(0 to 1); + entry_gs : in std_ulogic; + entry_ts : in std_ulogic; + state_enable : in std_ulogic_vector(0 to 1); + entry_thdid : in std_ulogic_vector(0 to 3); + comp_thdid : in std_ulogic_vector(0 to 3); + thdid_enable : in std_ulogic; + entry_pid : in std_ulogic_vector(0 to 13); + comp_pid : in std_ulogic_vector(0 to 13); + pid_enable : in std_ulogic; + entry_lpid : in std_ulogic_vector(0 to 7); + comp_lpid : in std_ulogic_vector(0 to 7); + lpid_enable : in std_ulogic; + entry_ind : in std_ulogic; + comp_ind : in std_ulogic; + ind_enable : in std_ulogic; + entry_iprot : in std_ulogic; + comp_iprot : in std_ulogic; + iprot_enable : in std_ulogic; + entry_v : in std_ulogic; + comp_invalidate : in std_ulogic; + + match : out std_ulogic; + + dbg_addr_match : out std_ulogic; + dbg_pgsize_match : out std_ulogic; + dbg_class_match : out std_ulogic; + dbg_extclass_match : out std_ulogic; + dbg_state_match : out std_ulogic; + dbg_thdid_match : out std_ulogic; + dbg_pid_match : out std_ulogic; + dbg_lpid_match : out std_ulogic; + dbg_ind_match : out std_ulogic; + dbg_iprot_match : out std_ulogic + +); + + -- synopsys translate_off + -- synopsys translate_on + +end mmq_tlb_matchline; + +architecture mmq_tlb_matchline of mmq_tlb_matchline is + +------------------------------------------------------------------------ +-- Signals +------------------------------------------------------------------------ + + signal entry_epn_b : std_ulogic_vector(30 to 51); + signal function_50_51 : std_ulogic; + signal function_48_51 : std_ulogic; + signal function_46_51 : std_ulogic; + signal function_44_51 : std_ulogic; + signal function_40_51 : std_ulogic; + signal function_36_51 : std_ulogic; + signal function_34_51 : std_ulogic; + signal pgsize_gte_16K : std_ulogic; + signal pgsize_gte_64K : std_ulogic; + signal pgsize_gte_256K : std_ulogic; + signal pgsize_gte_1M : std_ulogic; + signal pgsize_gte_16M : std_ulogic; + signal pgsize_gte_256M : std_ulogic; + signal pgsize_gte_1G : std_ulogic; + signal pgsize_eq_16K : std_ulogic; + signal pgsize_eq_64K : std_ulogic; + signal pgsize_eq_256K : std_ulogic; + signal pgsize_eq_1M : std_ulogic; + signal pgsize_eq_16M : std_ulogic; + signal pgsize_eq_256M : std_ulogic; + signal pgsize_eq_1G : std_ulogic; + signal comp_or_34_35 : std_ulogic; + signal comp_or_36_39 : std_ulogic; + signal comp_or_40_43 : std_ulogic; + signal comp_or_44_45 : std_ulogic; + signal comp_or_44_47 : std_ulogic; + signal comp_or_46_47 : std_ulogic; + signal comp_or_48_49 : std_ulogic; + signal comp_or_48_51 : std_ulogic; + signal comp_or_50_51 : std_ulogic; + signal match_line : std_ulogic_vector(0 to 85); + signal pgsize_match : std_ulogic; + signal addr_match : std_ulogic; + signal class_match : std_ulogic; + signal extclass_match : std_ulogic; + signal state_match : std_ulogic; + signal thdid_match : std_ulogic; + signal pid_match : std_ulogic; + signal lpid_match : std_ulogic; + signal ind_match : std_ulogic; + signal iprot_match : std_ulogic; + signal addr_match_xbit_contrib : std_ulogic; + signal addr_match_lsb_contrib : std_ulogic; + signal addr_match_msb_contrib : std_ulogic; + + signal unused_dc : std_ulogic_vector(0 to 4); +-- synopsys translate_off +-- synopsys translate_on + +begin + + match_line(0 to 85) <= not( + (entry_epn(0 to 51) & entry_size(0 to 3) & entry_class(0 to 1) & entry_extclass(0 to 1) & entry_gs & entry_ts & entry_pid(0 to 13) & entry_lpid(0 to 7) & entry_ind & entry_iprot) xor + (addr_in(0 to 51) & comp_pgsize(0 to 3) & comp_class(0 to 1) & comp_extclass(0 to 1) & comp_state(0 to 1) & comp_pid(0 to 13) & comp_lpid(0 to 7) & comp_ind & comp_iprot) + ); + +numpgsz8 : if num_pgsizes = 8 generate + + entry_epn_b(30 to 51) <= not(entry_epn(30 to 51)); + + unused_dc <= (others => '0'); + +gen_nocmpmask80 : if have_cmpmask = 0 generate + pgsize_gte_1G <= ( entry_size(0) and not(entry_size(1)) and entry_size(2) and not(entry_size(3)) ); + pgsize_gte_256M <= ( entry_size(0) and not(entry_size(1)) and not(entry_size(2)) and entry_size(3) ) or + pgsize_gte_1G; + pgsize_gte_16M <= (not(entry_size(0)) and entry_size(1) and entry_size(2) and entry_size(3) ) or + pgsize_gte_256M; + pgsize_gte_1M <= (not(entry_size(0)) and entry_size(1) and not(entry_size(2)) and entry_size(3) ) or + pgsize_gte_16M; + pgsize_gte_256K <= (not(entry_size(0)) and entry_size(1) and not(entry_size(2)) and not(entry_size(3)) ) or + pgsize_gte_1M; + pgsize_gte_64K <= (not(entry_size(0)) and not(entry_size(1)) and entry_size(2) and entry_size(3) ) or + pgsize_gte_256K; + pgsize_gte_16K <= (not(entry_size(0)) and not(entry_size(1)) and entry_size(2) and not(entry_size(3)) ) or + pgsize_gte_64K; +end generate gen_nocmpmask80; + +gen_cmpmask80 : if have_cmpmask = 1 generate +-- size entry_cmpmask: 0123456 +-- 1GB 1111111 +-- 256MB 0111111 +-- 16MB 0011111 +-- 1MB 0001111 +-- 256KB 0000111 +-- 64KB 0000011 +-- 16KB 0000001 +-- 4KB 0000000 + pgsize_gte_1G <= entry_cmpmask(0); + pgsize_gte_256M <= entry_cmpmask(1); + pgsize_gte_16M <= entry_cmpmask(2); + pgsize_gte_1M <= entry_cmpmask(3); + pgsize_gte_256K <= entry_cmpmask(4); + pgsize_gte_64K <= entry_cmpmask(5); + pgsize_gte_16K <= entry_cmpmask(6); + +-- size entry_xbitmask: 0123456 +-- 1GB 1000000 +-- 256MB 0100000 +-- 16MB 0010000 +-- 1MB 0001000 +-- 256KB 0000100 +-- 64KB 0000010 +-- 16KB 0000001 +-- 4KB 0000000 + pgsize_eq_1G <= entry_xbitmask(0); + pgsize_eq_256M <= entry_xbitmask(1); + pgsize_eq_16M <= entry_xbitmask(2); + pgsize_eq_1M <= entry_xbitmask(3); + pgsize_eq_256K <= entry_xbitmask(4); + pgsize_eq_64K <= entry_xbitmask(5); + pgsize_eq_16K <= entry_xbitmask(6); +end generate gen_cmpmask80; + +gen_noxbit80 : if have_xbit = 0 generate + function_34_51 <= '0'; + function_36_51 <= '0'; + function_40_51 <= '0'; + function_44_51 <= '0'; + function_46_51 <= '0'; + function_48_51 <= '0'; + function_50_51 <= '0'; +end generate gen_noxbit80; + +gen_xbit80 : if have_xbit /= 0 generate + + -- 1G + function_34_51 <= not(entry_xbit) or + not(pgsize_eq_1G) or + or_reduce(entry_epn_b(34 to 51) and addr_in(34 to 51)); + function_36_51 <= not(entry_xbit) or + not(pgsize_eq_256M) or + or_reduce(entry_epn_b(36 to 51) and addr_in(36 to 51)); + function_40_51 <= not(entry_xbit) or + not(pgsize_eq_16M) or + or_reduce(entry_epn_b(40 to 51) and addr_in(40 to 51)); + function_44_51 <= not(entry_xbit) or + not(pgsize_eq_1M) or + or_reduce(entry_epn_b(44 to 51) and addr_in(44 to 51)); + function_46_51 <= not(entry_xbit) or + not(pgsize_eq_256K) or + or_reduce(entry_epn_b(46 to 51) and addr_in(46 to 51)); + function_48_51 <= not(entry_xbit) or + not(pgsize_eq_64K) or + or_reduce(entry_epn_b(48 to 51) and addr_in(48 to 51)); + function_50_51 <= not(entry_xbit) or + not(pgsize_eq_16K) or + or_reduce(entry_epn_b(50 to 51) and addr_in(50 to 51)); +end generate gen_xbit80; + + + comp_or_50_51 <= and_reduce(match_line(50 to 51)) or pgsize_gte_16K; + comp_or_48_49 <= and_reduce(match_line(48 to 49)) or pgsize_gte_64K; + comp_or_46_47 <= and_reduce(match_line(46 to 47)) or pgsize_gte_256K; + comp_or_44_45 <= and_reduce(match_line(44 to 45)) or pgsize_gte_1M; + comp_or_40_43 <= and_reduce(match_line(40 to 43)) or pgsize_gte_16M; + comp_or_36_39 <= and_reduce(match_line(36 to 39)) or pgsize_gte_256M; + comp_or_34_35 <= and_reduce(match_line(34 to 35)) or pgsize_gte_1G; + +gen_noxbit81 : if have_xbit = 0 generate + addr_match <= ( comp_or_34_35 and -- Ignore functions based on page size + comp_or_36_39 and + comp_or_40_43 and + comp_or_44_45 and + comp_or_46_47 and + comp_or_48_49 and + (and_reduce(match_line(0 to 12)) or not(addr_enable(0))) and + (and_reduce(match_line(13 to 14)) or not(addr_enable(1))) and + (and_reduce(match_line(15 to 16)) or not(addr_enable(2))) and + (and_reduce(match_line(17 to 18)) or not(addr_enable(3))) and + (and_reduce(match_line(19 to 22)) or not(addr_enable(4))) and + (and_reduce(match_line(23 to 26)) or not(addr_enable(5))) and + (and_reduce(match_line(27 to 30)) or not(addr_enable(6))) and + (and_reduce(match_line(31 to 33)) or not(addr_enable(7))) + ) or -- Regular compare largest page size + not(addr_enable(8)); -- Include address as part of compare, + -- should never ignore for regular compare/read. + -- Could ignore for compare/invalidate + addr_match_xbit_contrib <= '0'; + + addr_match_lsb_contrib <= ( comp_or_34_35 and -- Ignore functions based on page size + comp_or_36_39 and + comp_or_40_43 and + comp_or_44_45 and + comp_or_46_47 and + comp_or_48_49 and + comp_or_50_51); + + addr_match_msb_contrib <= (and_reduce(match_line(0 to 12)) or not(addr_enable(0))) and + (and_reduce(match_line(13 to 14)) or not(addr_enable(1))) and + (and_reduce(match_line(15 to 16)) or not(addr_enable(2))) and + (and_reduce(match_line(17 to 18)) or not(addr_enable(3))) and + (and_reduce(match_line(19 to 22)) or not(addr_enable(4))) and + (and_reduce(match_line(23 to 26)) or not(addr_enable(5))) and + (and_reduce(match_line(27 to 30)) or not(addr_enable(6))) and + (and_reduce(match_line(31 to 33)) or not(addr_enable(7))) ; + +end generate gen_noxbit81; + +gen_xbit81 : if have_xbit /= 0 generate + addr_match <= ( function_50_51 and -- Exclusion functions + function_48_51 and + function_46_51 and + function_44_51 and + function_40_51 and + function_36_51 and + function_34_51 and + comp_or_34_35 and -- Ignore functions based on page size + comp_or_36_39 and + comp_or_40_43 and + comp_or_44_45 and + comp_or_46_47 and + comp_or_48_49 and + comp_or_50_51 and + (and_reduce(match_line(0 to 12)) or not(addr_enable(0))) and + (and_reduce(match_line(13 to 14)) or not(addr_enable(1))) and + (and_reduce(match_line(15 to 16)) or not(addr_enable(2))) and + (and_reduce(match_line(17 to 18)) or not(addr_enable(3))) and + (and_reduce(match_line(19 to 22)) or not(addr_enable(4))) and + (and_reduce(match_line(23 to 26)) or not(addr_enable(5))) and + (and_reduce(match_line(27 to 30)) or not(addr_enable(6))) and + (and_reduce(match_line(31 to 33)) or not(addr_enable(7))) + ) or -- Regular compare largest page size + not(addr_enable(8)); -- Include address as part of compare, + -- should never ignore for regular compare/read. + -- Could ignore for compare/invalidate + + addr_match_xbit_contrib <= ( function_50_51 and -- Exclusion functions + function_48_51 and + function_46_51 and + function_44_51 and + function_40_51 and + function_36_51 and + function_34_51 ); + + addr_match_lsb_contrib <= ( comp_or_34_35 and -- Ignore functions based on page size + comp_or_36_39 and + comp_or_40_43 and + comp_or_44_45 and + comp_or_46_47 and + comp_or_48_49 and + comp_or_50_51); + + addr_match_msb_contrib <= (and_reduce(match_line(0 to 12)) or not(addr_enable(0))) and + (and_reduce(match_line(13 to 14)) or not(addr_enable(1))) and + (and_reduce(match_line(15 to 16)) or not(addr_enable(2))) and + (and_reduce(match_line(17 to 18)) or not(addr_enable(3))) and + (and_reduce(match_line(19 to 22)) or not(addr_enable(4))) and + (and_reduce(match_line(23 to 26)) or not(addr_enable(5))) and + (and_reduce(match_line(27 to 30)) or not(addr_enable(6))) and + (and_reduce(match_line(31 to 33)) or not(addr_enable(7))) ; + +end generate gen_xbit81; + +end generate numpgsz8; -- numpgsz8: num_pgsizes = 8 + + +numpgsz5 : if num_pgsizes = 5 generate + + -- tie off unused signals + function_50_51 <= '0'; + function_46_51 <= '0'; + pgsize_gte_16K <= '0'; + pgsize_gte_256K <= '0'; + pgsize_eq_16K <= '0'; + pgsize_eq_256K <= '0'; + comp_or_44_45 <= '0'; + comp_or_46_47 <= '0'; + comp_or_48_49 <= '0'; + comp_or_50_51 <= '0'; + + entry_epn_b(30 to 51) <= not(entry_epn(30 to 51)); + +unused_dc(0) <= (pgsize_gte_16K and pgsize_gte_256K and pgsize_eq_16K and pgsize_eq_256K); +unused_dc(1) <= (function_50_51 and function_46_51); +unused_dc(2) <= (comp_or_44_45 and comp_or_46_47 and comp_or_48_49 and comp_or_50_51); +unused_dc(3) <= or_reduce(entry_epn_b(30 to 33)); +unused_dc(4) <= addr_match_xbit_contrib and addr_match_lsb_contrib and addr_match_msb_contrib; + +gen_nocmpmask50 : if have_cmpmask = 0 generate + -- 1010 + pgsize_gte_1G <= ( entry_size(0) and not(entry_size(1)) and entry_size(2) and not(entry_size(3)) ); + + -- 1001, large indirect entry size + pgsize_gte_256M <= ( entry_size(0) and not(entry_size(1)) and not(entry_size(2)) and entry_size(3) ) or + pgsize_gte_1G; + -- 0111 + pgsize_gte_16M <= (not(entry_size(0)) and entry_size(1) and entry_size(2) and entry_size(3)) or + pgsize_gte_256M; + -- 0101 + pgsize_gte_1M <= (not(entry_size(0)) and entry_size(1) and not(entry_size(2)) and entry_size(3)) or + pgsize_gte_16M; + -- 0011 + pgsize_gte_64K <= (not(entry_size(0)) and not(entry_size(1)) and entry_size(2) and entry_size(3)) or + pgsize_gte_1M; + + -- 1010 + pgsize_eq_1G <= ( entry_size(0) and not(entry_size(1)) and entry_size(2) and not(entry_size(3)) ); + -- 1001, large indirect entry size + pgsize_eq_256M <= ( entry_size(0) and not(entry_size(1)) and not(entry_size(2)) and entry_size(3) ); + -- 0111 + pgsize_eq_16M <= ( not(entry_size(0)) and entry_size(1) and entry_size(2) and entry_size(3) ); + -- 0101 + pgsize_eq_1M <= ( not(entry_size(0)) and entry_size(1) and not(entry_size(2)) and entry_size(3) ); + -- 0011 + pgsize_eq_64K <= ( not(entry_size(0)) and not(entry_size(1)) and entry_size(2) and entry_size(3) ); +end generate gen_nocmpmask50; + +gen_cmpmask50 : if have_cmpmask = 1 generate +-- size entry_cmpmask: 01234 +-- 1GB 11111 +-- 256MB 01111 +-- 16MB 00111 +-- 1MB 00011 +-- 64KB 00001 +-- 4KB 00000 + pgsize_gte_1G <= entry_cmpmask(0); + pgsize_gte_256M <= entry_cmpmask(1); + pgsize_gte_16M <= entry_cmpmask(2); + pgsize_gte_1M <= entry_cmpmask(3); + pgsize_gte_64K <= entry_cmpmask(4); + +-- size entry_xbitmask: 01234 +-- 1GB 10000 +-- 256MB 01000 +-- 16MB 00100 +-- 1MB 00010 +-- 64KB 00001 +-- 4KB 00000 + pgsize_eq_1G <= entry_xbitmask(0); + pgsize_eq_256M <= entry_xbitmask(1); + pgsize_eq_16M <= entry_xbitmask(2); + pgsize_eq_1M <= entry_xbitmask(3); + pgsize_eq_64K <= entry_xbitmask(4); +end generate gen_cmpmask50; + + +gen_noxbit50 : if have_xbit = 0 generate + function_34_51 <= '0'; + function_36_51 <= '0'; + function_40_51 <= '0'; + function_44_51 <= '0'; + function_48_51 <= '0'; +end generate gen_noxbit50; + +gen_xbit50 : if have_xbit /= 0 generate + -- 1G + function_34_51 <= not(entry_xbit) or + not(pgsize_eq_1G) or + or_reduce(entry_epn_b(34 to 51) and addr_in(34 to 51)); + -- 256M + function_36_51 <= not(entry_xbit) or + not(pgsize_eq_256M) or + or_reduce(entry_epn_b(36 to 51) and addr_in(36 to 51)); + -- 16M + function_40_51 <= not(entry_xbit) or + not(pgsize_eq_16M) or + or_reduce(entry_epn_b(40 to 51) and addr_in(40 to 51)); + -- 1M + function_44_51 <= not(entry_xbit) or + not(pgsize_eq_1M) or + or_reduce(entry_epn_b(44 to 51) and addr_in(44 to 51)); + -- 64K + function_48_51 <= not(entry_xbit) or + not(pgsize_eq_64K) or + or_reduce(entry_epn_b(48 to 51) and addr_in(48 to 51)); +end generate gen_xbit50; + + comp_or_48_51 <= and_reduce(match_line(48 to 51)) or pgsize_gte_64K; + comp_or_44_47 <= and_reduce(match_line(44 to 47)) or pgsize_gte_1M; + comp_or_40_43 <= and_reduce(match_line(40 to 43)) or pgsize_gte_16M; + comp_or_36_39 <= and_reduce(match_line(36 to 39)) or pgsize_gte_256M; + comp_or_34_35 <= and_reduce(match_line(34 to 35)) or pgsize_gte_1G; -- glorp + +gen_noxbit51 : if have_xbit = 0 generate + addr_match <= ( comp_or_34_35 and -- Ignore functions based on page size + comp_or_36_39 and + comp_or_40_43 and + comp_or_44_47 and + comp_or_48_51 and + (and_reduce(match_line(0 to 12)) or not(addr_enable(0))) and + (and_reduce(match_line(13 to 14)) or not(addr_enable(1))) and + (and_reduce(match_line(15 to 16)) or not(addr_enable(2))) and + (and_reduce(match_line(17 to 18)) or not(addr_enable(3))) and + (and_reduce(match_line(19 to 22)) or not(addr_enable(4))) and + (and_reduce(match_line(23 to 26)) or not(addr_enable(5))) and + (and_reduce(match_line(27 to 30)) or not(addr_enable(6))) and + (and_reduce(match_line(31 to 33)) or not(addr_enable(7))) + ) or -- Regular compare largest page size + not(addr_enable(8)); -- Include address as part of compare, + -- should never ignore for regular compare/read. + -- Could ignore for compare/invalidate + addr_match_xbit_contrib <= '0'; + + addr_match_lsb_contrib <= ( comp_or_34_35 and -- Ignore functions based on page size + comp_or_36_39 and + comp_or_40_43 and + comp_or_44_47 and + comp_or_48_51); + + addr_match_msb_contrib <= (and_reduce(match_line(0 to 12)) or not(addr_enable(0))) and + (and_reduce(match_line(13 to 14)) or not(addr_enable(1))) and + (and_reduce(match_line(15 to 16)) or not(addr_enable(2))) and + (and_reduce(match_line(17 to 18)) or not(addr_enable(3))) and + (and_reduce(match_line(19 to 22)) or not(addr_enable(4))) and + (and_reduce(match_line(23 to 26)) or not(addr_enable(5))) and + (and_reduce(match_line(27 to 30)) or not(addr_enable(6))) and + (and_reduce(match_line(31 to 33)) or not(addr_enable(7))) ; + +end generate gen_noxbit51; + +gen_xbit51 : if have_xbit /= 0 generate + addr_match <= ( function_48_51 and + function_44_51 and + function_40_51 and + function_36_51 and + function_34_51 and + comp_or_34_35 and -- Ignore functions based on page size + comp_or_36_39 and + comp_or_40_43 and + comp_or_44_47 and + comp_or_48_51 and + (and_reduce(match_line(0 to 12)) or not(addr_enable(0))) and + (and_reduce(match_line(13 to 14)) or not(addr_enable(1))) and + (and_reduce(match_line(15 to 16)) or not(addr_enable(2))) and + (and_reduce(match_line(17 to 18)) or not(addr_enable(3))) and + (and_reduce(match_line(19 to 22)) or not(addr_enable(4))) and + (and_reduce(match_line(23 to 26)) or not(addr_enable(5))) and + (and_reduce(match_line(27 to 30)) or not(addr_enable(6))) and + (and_reduce(match_line(31 to 33)) or not(addr_enable(7))) + ) or -- Regular compare largest page size + not(addr_enable(8)); -- Include address as part of compare, + -- should never ignore for regular compare/read. + -- Could ignore for compare/invalidate + + addr_match_xbit_contrib <= ( function_48_51 and -- Exclusion functions + function_44_51 and + function_40_51 and + function_36_51 and + function_34_51 ); + + addr_match_lsb_contrib <= ( comp_or_34_35 and -- Ignore functions based on page size + comp_or_36_39 and + comp_or_40_43 and + comp_or_44_47 and + comp_or_48_51); + + addr_match_msb_contrib <= (and_reduce(match_line(0 to 12)) or not(addr_enable(0))) and + (and_reduce(match_line(13 to 14)) or not(addr_enable(1))) and + (and_reduce(match_line(15 to 16)) or not(addr_enable(2))) and + (and_reduce(match_line(17 to 18)) or not(addr_enable(3))) and + (and_reduce(match_line(19 to 22)) or not(addr_enable(4))) and + (and_reduce(match_line(23 to 26)) or not(addr_enable(5))) and + (and_reduce(match_line(27 to 30)) or not(addr_enable(6))) and + (and_reduce(match_line(31 to 33)) or not(addr_enable(7))) ; + +end generate gen_xbit51; + +end generate numpgsz5; -- numpgsz5: num_pgsizes = 5 + + + pgsize_match <= and_reduce(match_line(52 to 55)) or + not(pgsize_enable); + + class_match <= and_reduce(match_line(56 to 57)) or + not(class_enable); + + extclass_match <= (match_line(58) or + not(extclass_enable(0))) and + (match_line(59) or + not(extclass_enable(1))); + + + state_match <= (match_line(60) or + not(state_enable(0))) and + (match_line(61) or + not(state_enable(1))); + + thdid_match <= or_reduce(entry_thdid(0 to 3) and comp_thdid(0 to 3)) or + not(thdid_enable); + + -- entry_pid=0 ignores pid match for translation, not invalidation + pid_match <= and_reduce(match_line(62 to 75)) or + (not(or_reduce(entry_pid(0 to 13))) and not comp_invalidate) or + not(pid_enable); + + -- entry_lpid=0 ignores lpid match for translation, not invalidation + lpid_match <= and_reduce(match_line(76 to 83)) or + (not(or_reduce(entry_lpid(0 to 7))) and not comp_invalidate) or + not(lpid_enable); + + ind_match <= match_line(84) or + not(ind_enable); + + iprot_match <= match_line(85) or + not(iprot_enable); + + match <= addr_match and -- Address compare + pgsize_match and -- Size compare + class_match and -- Class compare + extclass_match and -- ExtClass compare + state_match and -- State compare + thdid_match and -- ThdID compare + pid_match and -- PID compare + lpid_match and -- LPID compare + ind_match and -- indirect compare + iprot_match and -- inval prot compare + entry_v; -- Valid + + -- debug outputs + dbg_addr_match <= addr_match; -- out std_ulogic; + dbg_pgsize_match <= pgsize_match; -- out std_ulogic; + dbg_class_match <= class_match; -- out std_ulogic; + dbg_extclass_match <= extclass_match; -- out std_ulogic; + dbg_state_match <= state_match; -- out std_ulogic; + dbg_thdid_match <= thdid_match; -- out std_ulogic; + dbg_pid_match <= pid_match; -- out std_ulogic; + dbg_lpid_match <= lpid_match; -- out std_ulogic; + dbg_ind_match <= ind_match; -- out std_ulogic; + dbg_iprot_match <= iprot_match; -- out std_ulogic + +end mmq_tlb_matchline; diff --git a/rel/src/vhdl/work/mmq_tlb_req.vhdl b/rel/src/vhdl/work/mmq_tlb_req.vhdl new file mode 100644 index 0000000..4d3c188 --- /dev/null +++ b/rel/src/vhdl/work/mmq_tlb_req.vhdl @@ -0,0 +1,2838 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +--******************************************************************** +--* TITLE: Memory Management Unit TLB Input Request Queue from ERATs +--* NAME: mmq_tlb_req.vhdl +--********************************************************************* + +library ieee; +use ieee.std_logic_1164.all; +library ibm; +use ibm.std_ulogic_unsigned.all; +use ibm.std_ulogic_function_support.all; +library support; +use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity mmq_tlb_req is + generic(thdid_width : integer := 4; + state_width : integer := 4; + pid_width : integer := 14; + pid_width_erat : integer := 8; + lpid_width : integer := 8; + req_epn_width : integer := 52; + rs_data_width : integer := 64; + expand_type : integer := 2 ); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + +tc_ccflush_dc : in std_ulogic; +tc_scan_dis_dc_b : in std_ulogic; +tc_scan_diag_dc : in std_ulogic; +tc_lbist_en_dc : in std_ulogic; +lcb_d_mode_dc : in std_ulogic; +lcb_clkoff_dc_b : in std_ulogic; +lcb_act_dis_dc : in std_ulogic; +lcb_mpw1_dc_b : in std_ulogic_vector(0 to 4); +lcb_mpw2_dc_b : in std_ulogic; +lcb_delay_lclkr_dc : in std_ulogic_vector(0 to 4); +ac_func_scan_in :in std_ulogic; +ac_func_scan_out :out std_ulogic; +pc_sg_2 : in std_ulogic; +pc_func_sl_thold_2 : in std_ulogic; +pc_func_slp_sl_thold_2 : in std_ulogic; +xu_mm_ccr2_notlb_b : in std_ulogic; +mmucr2_act_override : in std_ulogic; +pid0 : in std_ulogic_vector(0 to pid_width-1); +pid1 : in std_ulogic_vector(0 to pid_width-1); +pid2 : in std_ulogic_vector(0 to pid_width-1); +pid3 : in std_ulogic_vector(0 to pid_width-1); +lpidr : in std_ulogic_vector(0 to lpid_width-1); +iu_mm_ierat_req : in std_ulogic; +iu_mm_ierat_epn : in std_ulogic_vector(0 to 51); +iu_mm_ierat_thdid : in std_ulogic_vector(0 to thdid_width-1); +iu_mm_ierat_state : in std_ulogic_vector(0 to state_width-1); +iu_mm_ierat_tid : in std_ulogic_vector(0 to pid_width-1); +iu_mm_ierat_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_mm_derat_req : in std_ulogic; +xu_mm_derat_epn : in std_ulogic_vector(64-rs_data_width to 51); +xu_mm_derat_thdid : in std_ulogic_vector(0 to thdid_width-1); +xu_mm_derat_ttype : in std_ulogic_vector(0 to 1); +xu_mm_derat_state : in std_ulogic_vector(0 to state_width-1); +xu_mm_derat_tid : in std_ulogic_vector(0 to pid_width-1); +xu_mm_derat_lpid : in std_ulogic_vector(0 to lpid_width-1); +ierat_req0_pid : out std_ulogic_vector(0 to pid_width-1); +ierat_req0_as : out std_ulogic; +ierat_req0_gs : out std_ulogic; +ierat_req0_epn : out std_ulogic_vector(0 to req_epn_width-1); +ierat_req0_thdid : out std_ulogic_vector(0 to thdid_width-1); +ierat_req0_valid : out std_ulogic; +ierat_req0_nonspec : out std_ulogic; +ierat_req1_pid : out std_ulogic_vector(0 to pid_width-1); +ierat_req1_as : out std_ulogic; +ierat_req1_gs : out std_ulogic; +ierat_req1_epn : out std_ulogic_vector(0 to req_epn_width-1); +ierat_req1_thdid : out std_ulogic_vector(0 to thdid_width-1); +ierat_req1_valid : out std_ulogic; +ierat_req1_nonspec : out std_ulogic; +ierat_req2_pid : out std_ulogic_vector(0 to pid_width-1); +ierat_req2_as : out std_ulogic; +ierat_req2_gs : out std_ulogic; +ierat_req2_epn : out std_ulogic_vector(0 to req_epn_width-1); +ierat_req2_thdid : out std_ulogic_vector(0 to thdid_width-1); +ierat_req2_valid : out std_ulogic; +ierat_req2_nonspec : out std_ulogic; +ierat_req3_pid : out std_ulogic_vector(0 to pid_width-1); +ierat_req3_as : out std_ulogic; +ierat_req3_gs : out std_ulogic; +ierat_req3_epn : out std_ulogic_vector(0 to req_epn_width-1); +ierat_req3_thdid : out std_ulogic_vector(0 to thdid_width-1); +ierat_req3_valid : out std_ulogic; +ierat_req3_nonspec : out std_ulogic; +ierat_iu4_pid : out std_ulogic_vector(0 to pid_width-1); +ierat_iu4_gs : out std_ulogic; +ierat_iu4_as : out std_ulogic; +ierat_iu4_epn : out std_ulogic_vector(0 to req_epn_width-1); +ierat_iu4_thdid : out std_ulogic_vector(0 to thdid_width-1); +ierat_iu4_valid : out std_ulogic; +derat_req0_lpid : out std_ulogic_vector(0 to lpid_width-1); +derat_req0_pid : out std_ulogic_vector(0 to pid_width-1); +derat_req0_as : out std_ulogic; +derat_req0_gs : out std_ulogic; +derat_req0_epn : out std_ulogic_vector(0 to req_epn_width-1); +derat_req0_thdid : out std_ulogic_vector(0 to thdid_width-1); +derat_req0_valid : out std_ulogic; +derat_req1_lpid : out std_ulogic_vector(0 to lpid_width-1); +derat_req1_pid : out std_ulogic_vector(0 to pid_width-1); +derat_req1_as : out std_ulogic; +derat_req1_gs : out std_ulogic; +derat_req1_epn : out std_ulogic_vector(0 to req_epn_width-1); +derat_req1_thdid : out std_ulogic_vector(0 to thdid_width-1); +derat_req1_valid : out std_ulogic; +derat_req2_lpid : out std_ulogic_vector(0 to lpid_width-1); +derat_req2_pid : out std_ulogic_vector(0 to pid_width-1); +derat_req2_as : out std_ulogic; +derat_req2_gs : out std_ulogic; +derat_req2_epn : out std_ulogic_vector(0 to req_epn_width-1); +derat_req2_thdid : out std_ulogic_vector(0 to thdid_width-1); +derat_req2_valid : out std_ulogic; +derat_req3_lpid : out std_ulogic_vector(0 to lpid_width-1); +derat_req3_pid : out std_ulogic_vector(0 to pid_width-1); +derat_req3_as : out std_ulogic; +derat_req3_gs : out std_ulogic; +derat_req3_epn : out std_ulogic_vector(0 to req_epn_width-1); +derat_req3_thdid : out std_ulogic_vector(0 to thdid_width-1); +derat_req3_valid : out std_ulogic; +derat_ex5_lpid : out std_ulogic_vector(0 to lpid_width-1); +derat_ex5_pid : out std_ulogic_vector(0 to pid_width-1); +derat_ex5_gs : out std_ulogic; +derat_ex5_as : out std_ulogic; +derat_ex5_epn : out std_ulogic_vector(0 to req_epn_width-1); +derat_ex5_thdid : out std_ulogic_vector(0 to thdid_width-1); +derat_ex5_valid : out std_ulogic; +xu_ex3_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_mm_ex4_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_mm_ex5_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_mm_ierat_miss : in std_ulogic_vector(0 to thdid_width-1); +xu_mm_ierat_flush : in std_ulogic_vector(0 to thdid_width-1); +mm_xu_eratmiss_done : in std_ulogic_vector(0 to thdid_width-1); +mm_xu_tlb_miss : in std_ulogic_vector(0 to thdid_width-1); +tlb_cmp_ierat_dup_val : in std_ulogic_vector(0 to 6); +tlb_cmp_derat_dup_val : in std_ulogic_vector(0 to 6); +tlb_seq_ierat_req : out std_ulogic; +tlb_seq_derat_req : out std_ulogic; +tlb_seq_ierat_done : in std_ulogic; +tlb_seq_derat_done : in std_ulogic; +ierat_req_taken : in std_ulogic; +derat_req_taken : in std_ulogic; +ierat_req_epn : out std_ulogic_vector(0 to req_epn_width-1); +ierat_req_pid : out std_ulogic_vector(0 to pid_width-1); +ierat_req_state : out std_ulogic_vector(0 to state_width-1); +ierat_req_thdid : out std_ulogic_vector(0 to thdid_width-1); +ierat_req_dup : out std_ulogic_vector(0 to 1); +derat_req_epn : out std_ulogic_vector(0 to req_epn_width-1); +derat_req_pid : out std_ulogic_vector(0 to pid_width-1); +derat_req_lpid : out std_ulogic_vector(0 to lpid_width-1); +derat_req_state : out std_ulogic_vector(0 to state_width-1); +derat_req_ttype : out std_ulogic_vector(0 to 1); +derat_req_thdid : out std_ulogic_vector(0 to thdid_width-1); +derat_req_dup : out std_ulogic_vector(0 to 1); +tlb_req_quiesce : out std_ulogic_vector(0 to thdid_width-1); +tlb_req_dbg_ierat_iu5_valid_q : out std_ulogic; +tlb_req_dbg_ierat_iu5_thdid : out std_ulogic_vector(0 to 1); +tlb_req_dbg_ierat_iu5_state_q : out std_ulogic_vector(0 to 3); +tlb_req_dbg_ierat_inptr_q : out std_ulogic_vector(0 to 1); +tlb_req_dbg_ierat_outptr_q : out std_ulogic_vector(0 to 1); +tlb_req_dbg_ierat_req_valid_q : out std_ulogic_vector(0 to 3); +tlb_req_dbg_ierat_req_nonspec_q : out std_ulogic_vector(0 to 3); +tlb_req_dbg_ierat_req_thdid : out std_ulogic_vector(0 to 7); +tlb_req_dbg_ierat_req_dup_q : out std_ulogic_vector(0 to 3); +tlb_req_dbg_derat_ex6_valid_q : out std_ulogic; +tlb_req_dbg_derat_ex6_thdid : out std_ulogic_vector(0 to 1); +tlb_req_dbg_derat_ex6_state_q : out std_ulogic_vector(0 to 3); +tlb_req_dbg_derat_inptr_q : out std_ulogic_vector(0 to 1); +tlb_req_dbg_derat_outptr_q : out std_ulogic_vector(0 to 1); +tlb_req_dbg_derat_req_valid_q : out std_ulogic_vector(0 to 3); +tlb_req_dbg_derat_req_thdid : out std_ulogic_vector(0 to 7); +tlb_req_dbg_derat_req_ttype_q : out std_ulogic_vector(0 to 7); +tlb_req_dbg_derat_req_dup_q : out std_ulogic_vector(0 to 3) + +); +end mmq_tlb_req; +architecture mmq_tlb_req of mmq_tlb_req is +constant MMU_Mode_Value : std_ulogic := '0'; +constant TlbSel_Tlb : std_ulogic_vector(0 to 1) := "00"; +constant TlbSel_IErat : std_ulogic_vector(0 to 1) := "10"; +constant TlbSel_DErat : std_ulogic_vector(0 to 1) := "11"; +constant ierat_req0_valid_offset : natural := 0; +constant ierat_req0_nonspec_offset : natural := ierat_req0_valid_offset + 1; +constant ierat_req0_thdid_offset : natural := ierat_req0_nonspec_offset + 1; +constant ierat_req0_epn_offset : natural := ierat_req0_thdid_offset + thdid_width; +constant ierat_req0_state_offset : natural := ierat_req0_epn_offset + req_epn_width; +constant ierat_req0_pid_offset : natural := ierat_req0_state_offset + state_width; +constant ierat_req0_dup_offset : natural := ierat_req0_pid_offset + pid_width; +constant ierat_req1_valid_offset : natural := ierat_req0_dup_offset + 2; +constant ierat_req1_nonspec_offset : natural := ierat_req1_valid_offset + 1; +constant ierat_req1_thdid_offset : natural := ierat_req1_nonspec_offset + 1; +constant ierat_req1_epn_offset : natural := ierat_req1_thdid_offset + thdid_width; +constant ierat_req1_state_offset : natural := ierat_req1_epn_offset + req_epn_width; +constant ierat_req1_pid_offset : natural := ierat_req1_state_offset + state_width; +constant ierat_req1_dup_offset : natural := ierat_req1_pid_offset + pid_width; +constant ierat_req2_valid_offset : natural := ierat_req1_dup_offset + 2; +constant ierat_req2_nonspec_offset : natural := ierat_req2_valid_offset + 1; +constant ierat_req2_thdid_offset : natural := ierat_req2_nonspec_offset + 1; +constant ierat_req2_epn_offset : natural := ierat_req2_thdid_offset + thdid_width; +constant ierat_req2_state_offset : natural := ierat_req2_epn_offset + req_epn_width; +constant ierat_req2_pid_offset : natural := ierat_req2_state_offset + state_width; +constant ierat_req2_dup_offset : natural := ierat_req2_pid_offset + pid_width; +constant ierat_req3_valid_offset : natural := ierat_req2_dup_offset + 2; +constant ierat_req3_nonspec_offset : natural := ierat_req3_valid_offset + 1; +constant ierat_req3_thdid_offset : natural := ierat_req3_nonspec_offset + 1; +constant ierat_req3_epn_offset : natural := ierat_req3_thdid_offset + thdid_width; +constant ierat_req3_state_offset : natural := ierat_req3_epn_offset + req_epn_width; +constant ierat_req3_pid_offset : natural := ierat_req3_state_offset + state_width; +constant ierat_req3_dup_offset : natural := ierat_req3_pid_offset + pid_width; +constant ierat_inptr_offset : natural := ierat_req3_dup_offset + 2; +constant ierat_outptr_offset : natural := ierat_inptr_offset + 2; +constant tlb_seq_ierat_req_offset : natural := ierat_outptr_offset + 2; +constant ierat_iu3_flush_offset : natural := tlb_seq_ierat_req_offset + 1; +constant xu_mm_ierat_flush_offset : natural := ierat_iu3_flush_offset + thdid_width; +constant xu_mm_ierat_miss_offset : natural := xu_mm_ierat_flush_offset + thdid_width; +constant ierat_iu3_valid_offset : natural := xu_mm_ierat_miss_offset + thdid_width; +constant ierat_iu3_thdid_offset : natural := ierat_iu3_valid_offset + 1; +constant ierat_iu3_epn_offset : natural := ierat_iu3_thdid_offset + thdid_width; +constant ierat_iu3_state_offset : natural := ierat_iu3_epn_offset + req_epn_width; +constant ierat_iu3_pid_offset : natural := ierat_iu3_state_offset + state_width; +constant ierat_iu4_valid_offset : natural := ierat_iu3_pid_offset + pid_width; +constant ierat_iu4_thdid_offset : natural := ierat_iu4_valid_offset + 1; +constant ierat_iu4_epn_offset : natural := ierat_iu4_thdid_offset + thdid_width; +constant ierat_iu4_state_offset : natural := ierat_iu4_epn_offset + req_epn_width; +constant ierat_iu4_pid_offset : natural := ierat_iu4_state_offset + state_width; +constant ierat_iu5_valid_offset : natural := ierat_iu4_pid_offset + pid_width; +constant ierat_iu5_thdid_offset : natural := ierat_iu5_valid_offset + 1; +constant ierat_iu5_epn_offset : natural := ierat_iu5_thdid_offset + thdid_width; +constant ierat_iu5_state_offset : natural := ierat_iu5_epn_offset + req_epn_width; +constant ierat_iu5_pid_offset : natural := ierat_iu5_state_offset + state_width; +constant derat_req0_valid_offset : natural := ierat_iu5_pid_offset + pid_width; +constant derat_req0_thdid_offset : natural := derat_req0_valid_offset + 1; +constant derat_req0_epn_offset : natural := derat_req0_thdid_offset + thdid_width; +constant derat_req0_state_offset : natural := derat_req0_epn_offset + req_epn_width; +constant derat_req0_ttype_offset : natural := derat_req0_state_offset + state_width; +constant derat_req0_pid_offset : natural := derat_req0_ttype_offset + 2; +constant derat_req0_lpid_offset : natural := derat_req0_pid_offset + pid_width; +constant derat_req0_dup_offset : natural := derat_req0_lpid_offset + lpid_width; +constant derat_req1_valid_offset : natural := derat_req0_dup_offset + 2; +constant derat_req1_thdid_offset : natural := derat_req1_valid_offset + 1; +constant derat_req1_epn_offset : natural := derat_req1_thdid_offset + thdid_width; +constant derat_req1_state_offset : natural := derat_req1_epn_offset + req_epn_width; +constant derat_req1_ttype_offset : natural := derat_req1_state_offset + state_width; +constant derat_req1_pid_offset : natural := derat_req1_ttype_offset + 2; +constant derat_req1_lpid_offset : natural := derat_req1_pid_offset + pid_width; +constant derat_req1_dup_offset : natural := derat_req1_lpid_offset + lpid_width; +constant derat_req2_valid_offset : natural := derat_req1_dup_offset + 2; +constant derat_req2_thdid_offset : natural := derat_req2_valid_offset + 1; +constant derat_req2_epn_offset : natural := derat_req2_thdid_offset + thdid_width; +constant derat_req2_state_offset : natural := derat_req2_epn_offset + req_epn_width; +constant derat_req2_ttype_offset : natural := derat_req2_state_offset + state_width; +constant derat_req2_pid_offset : natural := derat_req2_ttype_offset + 2; +constant derat_req2_lpid_offset : natural := derat_req2_pid_offset + pid_width; +constant derat_req2_dup_offset : natural := derat_req2_lpid_offset + lpid_width; +constant derat_req3_valid_offset : natural := derat_req2_dup_offset + 2; +constant derat_req3_thdid_offset : natural := derat_req3_valid_offset + 1; +constant derat_req3_epn_offset : natural := derat_req3_thdid_offset + thdid_width; +constant derat_req3_state_offset : natural := derat_req3_epn_offset + req_epn_width; +constant derat_req3_ttype_offset : natural := derat_req3_state_offset + state_width; +constant derat_req3_pid_offset : natural := derat_req3_ttype_offset + 2; +constant derat_req3_lpid_offset : natural := derat_req3_pid_offset + pid_width; +constant derat_req3_dup_offset : natural := derat_req3_lpid_offset + lpid_width; +constant derat_inptr_offset : natural := derat_req3_dup_offset + 2; +constant derat_outptr_offset : natural := derat_inptr_offset + 2; +constant tlb_seq_derat_req_offset : natural := derat_outptr_offset + 2; +constant derat_ex4_valid_offset : natural := tlb_seq_derat_req_offset + 1; +constant derat_ex4_thdid_offset : natural := derat_ex4_valid_offset + 1; +constant derat_ex4_epn_offset : natural := derat_ex4_thdid_offset + thdid_width; +constant derat_ex4_state_offset : natural := derat_ex4_epn_offset + req_epn_width; +constant derat_ex4_ttype_offset : natural := derat_ex4_state_offset + state_width; +constant derat_ex4_pid_offset : natural := derat_ex4_ttype_offset + 2; +constant derat_ex4_lpid_offset : natural := derat_ex4_pid_offset + pid_width; +constant derat_ex5_valid_offset : natural := derat_ex4_lpid_offset + lpid_width; +constant derat_ex5_thdid_offset : natural := derat_ex5_valid_offset + 1; +constant derat_ex5_epn_offset : natural := derat_ex5_thdid_offset + thdid_width; +constant derat_ex5_state_offset : natural := derat_ex5_epn_offset + req_epn_width; +constant derat_ex5_ttype_offset : natural := derat_ex5_state_offset + state_width; +constant derat_ex5_pid_offset : natural := derat_ex5_ttype_offset + 2; +constant derat_ex5_lpid_offset : natural := derat_ex5_pid_offset + pid_width; +constant derat_ex6_valid_offset : natural := derat_ex5_lpid_offset + lpid_width; +constant derat_ex6_thdid_offset : natural := derat_ex6_valid_offset + 1; +constant derat_ex6_epn_offset : natural := derat_ex6_thdid_offset + thdid_width; +constant derat_ex6_state_offset : natural := derat_ex6_epn_offset + req_epn_width; +constant derat_ex6_ttype_offset : natural := derat_ex6_state_offset + state_width; +constant derat_ex6_pid_offset : natural := derat_ex6_ttype_offset + 2; +constant derat_ex6_lpid_offset : natural := derat_ex6_pid_offset + pid_width; +constant spare_offset : natural := derat_ex6_lpid_offset + lpid_width; +constant scan_right : natural := spare_offset + 32 -1; +-- Latch signals +signal ierat_req0_valid_d, ierat_req0_valid_q : std_ulogic; +signal ierat_req0_nonspec_d, ierat_req0_nonspec_q : std_ulogic; +signal ierat_req0_thdid_d, ierat_req0_thdid_q : std_ulogic_vector(0 to thdid_width-1); +signal ierat_req0_epn_d, ierat_req0_epn_q : std_ulogic_vector(0 to req_epn_width-1); +signal ierat_req0_state_d, ierat_req0_state_q : std_ulogic_vector(0 to state_width-1); +signal ierat_req0_pid_d, ierat_req0_pid_q : std_ulogic_vector(0 to pid_width-1); +signal ierat_req0_dup_d, ierat_req0_dup_q : std_ulogic_vector(0 to 1); +signal ierat_req1_valid_d, ierat_req1_valid_q : std_ulogic; +signal ierat_req1_nonspec_d, ierat_req1_nonspec_q : std_ulogic; +signal ierat_req1_thdid_d, ierat_req1_thdid_q : std_ulogic_vector(0 to thdid_width-1); +signal ierat_req1_epn_d, ierat_req1_epn_q : std_ulogic_vector(0 to req_epn_width-1); +signal ierat_req1_state_d, ierat_req1_state_q : std_ulogic_vector(0 to state_width-1); +signal ierat_req1_pid_d, ierat_req1_pid_q : std_ulogic_vector(0 to pid_width-1); +signal ierat_req1_dup_d, ierat_req1_dup_q : std_ulogic_vector(0 to 1); +signal ierat_req2_valid_d, ierat_req2_valid_q : std_ulogic; +signal ierat_req2_nonspec_d, ierat_req2_nonspec_q : std_ulogic; +signal ierat_req2_thdid_d, ierat_req2_thdid_q : std_ulogic_vector(0 to thdid_width-1); +signal ierat_req2_epn_d, ierat_req2_epn_q : std_ulogic_vector(0 to req_epn_width-1); +signal ierat_req2_state_d, ierat_req2_state_q : std_ulogic_vector(0 to state_width-1); +signal ierat_req2_pid_d, ierat_req2_pid_q : std_ulogic_vector(0 to pid_width-1); +signal ierat_req2_dup_d, ierat_req2_dup_q : std_ulogic_vector(0 to 1); +signal ierat_req3_valid_d, ierat_req3_valid_q : std_ulogic; +signal ierat_req3_nonspec_d, ierat_req3_nonspec_q : std_ulogic; +signal ierat_req3_thdid_d, ierat_req3_thdid_q : std_ulogic_vector(0 to thdid_width-1); +signal ierat_req3_epn_d, ierat_req3_epn_q : std_ulogic_vector(0 to req_epn_width-1); +signal ierat_req3_state_d, ierat_req3_state_q : std_ulogic_vector(0 to state_width-1); +signal ierat_req3_pid_d, ierat_req3_pid_q : std_ulogic_vector(0 to pid_width-1); +signal ierat_req3_dup_d, ierat_req3_dup_q : std_ulogic_vector(0 to 1); +signal ierat_iu3_valid_d, ierat_iu3_valid_q : std_ulogic; +signal ierat_iu3_thdid_d, ierat_iu3_thdid_q : std_ulogic_vector(0 to thdid_width-1); +signal ierat_iu3_epn_d, ierat_iu3_epn_q : std_ulogic_vector(0 to req_epn_width-1); +signal ierat_iu3_state_d, ierat_iu3_state_q : std_ulogic_vector(0 to state_width-1); +signal ierat_iu3_pid_d, ierat_iu3_pid_q : std_ulogic_vector(0 to pid_width-1); +signal ierat_iu4_valid_d, ierat_iu4_valid_q : std_ulogic; +signal ierat_iu4_thdid_d, ierat_iu4_thdid_q : std_ulogic_vector(0 to thdid_width-1); +signal ierat_iu4_epn_d, ierat_iu4_epn_q : std_ulogic_vector(0 to req_epn_width-1); +signal ierat_iu4_state_d, ierat_iu4_state_q : std_ulogic_vector(0 to state_width-1); +signal ierat_iu4_pid_d, ierat_iu4_pid_q : std_ulogic_vector(0 to pid_width-1); +signal ierat_iu5_valid_d, ierat_iu5_valid_q : std_ulogic; +signal ierat_iu5_thdid_d, ierat_iu5_thdid_q : std_ulogic_vector(0 to thdid_width-1); +signal ierat_iu5_epn_d, ierat_iu5_epn_q : std_ulogic_vector(0 to req_epn_width-1); +signal ierat_iu5_state_d, ierat_iu5_state_q : std_ulogic_vector(0 to state_width-1); +signal ierat_iu5_pid_d, ierat_iu5_pid_q : std_ulogic_vector(0 to pid_width-1); +signal ierat_iu3_flush_d, ierat_iu3_flush_q : std_ulogic_vector(0 to thdid_width-1); +signal xu_mm_ierat_flush_d, xu_mm_ierat_flush_q : std_ulogic_vector(0 to thdid_width-1); +signal xu_mm_ierat_miss_d, xu_mm_ierat_miss_q : std_ulogic_vector(0 to thdid_width-1); +signal ierat_inptr_d, ierat_inptr_q : std_ulogic_vector(0 to 1); +signal ierat_outptr_d, ierat_outptr_q : std_ulogic_vector(0 to 1); +signal tlb_seq_ierat_req_d, tlb_seq_ierat_req_q : std_ulogic; +signal derat_req0_valid_d, derat_req0_valid_q : std_ulogic; +signal derat_req0_thdid_d, derat_req0_thdid_q : std_ulogic_vector(0 to thdid_width-1); +signal derat_req0_epn_d, derat_req0_epn_q : std_ulogic_vector(0 to req_epn_width-1); +signal derat_req0_state_d, derat_req0_state_q : std_ulogic_vector(0 to state_width-1); +signal derat_req0_ttype_d, derat_req0_ttype_q : std_ulogic_vector(0 to 1); +signal derat_req0_pid_d, derat_req0_pid_q : std_ulogic_vector(0 to pid_width-1); +signal derat_req0_lpid_d, derat_req0_lpid_q : std_ulogic_vector(0 to lpid_width-1); +signal derat_req0_dup_d, derat_req0_dup_q : std_ulogic_vector(0 to 1); +signal derat_req1_valid_d, derat_req1_valid_q : std_ulogic; +signal derat_req1_thdid_d, derat_req1_thdid_q : std_ulogic_vector(0 to thdid_width-1); +signal derat_req1_epn_d, derat_req1_epn_q : std_ulogic_vector(0 to req_epn_width-1); +signal derat_req1_state_d, derat_req1_state_q : std_ulogic_vector(0 to state_width-1); +signal derat_req1_ttype_d, derat_req1_ttype_q : std_ulogic_vector(0 to 1); +signal derat_req1_pid_d, derat_req1_pid_q : std_ulogic_vector(0 to pid_width-1); +signal derat_req1_lpid_d, derat_req1_lpid_q : std_ulogic_vector(0 to lpid_width-1); +signal derat_req1_dup_d, derat_req1_dup_q : std_ulogic_vector(0 to 1); +signal derat_req2_valid_d, derat_req2_valid_q : std_ulogic; +signal derat_req2_thdid_d, derat_req2_thdid_q : std_ulogic_vector(0 to thdid_width-1); +signal derat_req2_epn_d, derat_req2_epn_q : std_ulogic_vector(0 to req_epn_width-1); +signal derat_req2_state_d, derat_req2_state_q : std_ulogic_vector(0 to state_width-1); +signal derat_req2_ttype_d, derat_req2_ttype_q : std_ulogic_vector(0 to 1); +signal derat_req2_pid_d, derat_req2_pid_q : std_ulogic_vector(0 to pid_width-1); +signal derat_req2_lpid_d, derat_req2_lpid_q : std_ulogic_vector(0 to lpid_width-1); +signal derat_req2_dup_d, derat_req2_dup_q : std_ulogic_vector(0 to 1); +signal derat_req3_valid_d, derat_req3_valid_q : std_ulogic; +signal derat_req3_thdid_d, derat_req3_thdid_q : std_ulogic_vector(0 to thdid_width-1); +signal derat_req3_epn_d, derat_req3_epn_q : std_ulogic_vector(0 to req_epn_width-1); +signal derat_req3_state_d, derat_req3_state_q : std_ulogic_vector(0 to state_width-1); +signal derat_req3_ttype_d, derat_req3_ttype_q : std_ulogic_vector(0 to 1); +signal derat_req3_pid_d, derat_req3_pid_q : std_ulogic_vector(0 to pid_width-1); +signal derat_req3_lpid_d, derat_req3_lpid_q : std_ulogic_vector(0 to lpid_width-1); +signal derat_req3_dup_d, derat_req3_dup_q : std_ulogic_vector(0 to 1); +signal derat_ex4_valid_d, derat_ex4_valid_q : std_ulogic; +signal derat_ex4_thdid_d, derat_ex4_thdid_q : std_ulogic_vector(0 to thdid_width-1); +signal derat_ex4_epn_d, derat_ex4_epn_q : std_ulogic_vector(0 to req_epn_width-1); +signal derat_ex4_state_d, derat_ex4_state_q : std_ulogic_vector(0 to state_width-1); +signal derat_ex4_ttype_d, derat_ex4_ttype_q : std_ulogic_vector(0 to 1); +signal derat_ex4_pid_d, derat_ex4_pid_q : std_ulogic_vector(0 to pid_width-1); +signal derat_ex4_lpid_d, derat_ex4_lpid_q : std_ulogic_vector(0 to lpid_width-1); +signal derat_ex5_valid_d, derat_ex5_valid_q : std_ulogic; +signal derat_ex5_thdid_d, derat_ex5_thdid_q : std_ulogic_vector(0 to thdid_width-1); +signal derat_ex5_epn_d, derat_ex5_epn_q : std_ulogic_vector(0 to req_epn_width-1); +signal derat_ex5_state_d, derat_ex5_state_q : std_ulogic_vector(0 to state_width-1); +signal derat_ex5_ttype_d, derat_ex5_ttype_q : std_ulogic_vector(0 to 1); +signal derat_ex5_pid_d, derat_ex5_pid_q : std_ulogic_vector(0 to pid_width-1); +signal derat_ex5_lpid_d, derat_ex5_lpid_q : std_ulogic_vector(0 to lpid_width-1); +signal derat_ex6_valid_d, derat_ex6_valid_q : std_ulogic; +signal derat_ex6_thdid_d, derat_ex6_thdid_q : std_ulogic_vector(0 to thdid_width-1); +signal derat_ex6_epn_d, derat_ex6_epn_q : std_ulogic_vector(0 to req_epn_width-1); +signal derat_ex6_state_d, derat_ex6_state_q : std_ulogic_vector(0 to state_width-1); +signal derat_ex6_ttype_d, derat_ex6_ttype_q : std_ulogic_vector(0 to 1); +signal derat_ex6_pid_d, derat_ex6_pid_q : std_ulogic_vector(0 to pid_width-1); +signal derat_ex6_lpid_d, derat_ex6_lpid_q : std_ulogic_vector(0 to lpid_width-1); +signal derat_inptr_d, derat_inptr_q : std_ulogic_vector(0 to 1); +signal derat_outptr_d, derat_outptr_q : std_ulogic_vector(0 to 1); +signal tlb_seq_derat_req_d, tlb_seq_derat_req_q : std_ulogic; +signal spare_q : std_ulogic_vector(0 to 31); +-- logic signals +signal ierat_req_pid_mux : std_ulogic_vector(0 to pid_width-1); +signal tlb_req_quiesce_b : std_ulogic_vector(0 to thdid_width-1); +signal unused_dc : std_ulogic_vector(0 to 12); +-- synopsys translate_off +-- synopsys translate_on +-- Pervasive +signal pc_sg_1 : std_ulogic; +signal pc_sg_0 : std_ulogic; +signal pc_func_sl_thold_1 : std_ulogic; +signal pc_func_sl_thold_0 : std_ulogic; +signal pc_func_sl_thold_0_b : std_ulogic; +signal pc_func_slp_sl_thold_1 : std_ulogic; +signal pc_func_slp_sl_thold_0 : std_ulogic; +signal pc_func_slp_sl_thold_0_b : std_ulogic; +signal pc_func_sl_force : std_ulogic; +signal pc_func_slp_sl_force : std_ulogic; +signal siv : std_ulogic_vector(0 to scan_right); +signal sov : std_ulogic_vector(0 to scan_right); +begin +----------------------------------------------------------------------- +-- Logic +----------------------------------------------------------------------- +----------------------------------------------------------------------- +-- Glorp1 - common stuff for erat-only and tlb +----------------------------------------------------------------------- +-- not quiesced +tlb_req_quiesce_b(0 to thdid_width-1) <= + ( (0 to thdid_width-1 => ierat_req0_valid_q) and ierat_req0_thdid_q(0 to thdid_width-1) ) or + ( (0 to thdid_width-1 => ierat_req1_valid_q) and ierat_req1_thdid_q(0 to thdid_width-1) ) or + ( (0 to thdid_width-1 => ierat_req2_valid_q) and ierat_req2_thdid_q(0 to thdid_width-1) ) or + ( (0 to thdid_width-1 => ierat_req3_valid_q) and ierat_req3_thdid_q(0 to thdid_width-1) ) or + ( (0 to thdid_width-1 => derat_req0_valid_q) and derat_req0_thdid_q(0 to thdid_width-1) ) or + ( (0 to thdid_width-1 => derat_req1_valid_q) and derat_req1_thdid_q(0 to thdid_width-1) ) or + ( (0 to thdid_width-1 => derat_req2_valid_q) and derat_req2_thdid_q(0 to thdid_width-1) ) or + ( (0 to thdid_width-1 => derat_req3_valid_q) and derat_req3_thdid_q(0 to thdid_width-1) ) or + ( (0 to thdid_width-1 => derat_ex4_valid_q) and derat_ex4_thdid_q(0 to thdid_width-1) ) or + ( (0 to thdid_width-1 => derat_ex5_valid_q) and derat_ex5_thdid_q(0 to thdid_width-1) ) or + ( (0 to thdid_width-1 => derat_ex6_valid_q) and derat_ex6_thdid_q(0 to thdid_width-1) ) or + ( (0 to thdid_width-1 => ierat_iu3_valid_q) and ierat_iu3_thdid_q(0 to thdid_width-1) ) or + ( (0 to thdid_width-1 => ierat_iu4_valid_q) and ierat_iu4_thdid_q(0 to thdid_width-1) ) or + ( (0 to thdid_width-1 => ierat_iu5_valid_q) and ierat_iu5_thdid_q(0 to thdid_width-1) ); +tlb_req_quiesce <= not tlb_req_quiesce_b; +xu_mm_ierat_flush_d <= xu_mm_ierat_flush; +xu_mm_ierat_miss_d <= xu_mm_ierat_miss; +-- iu pipe for non-speculative ierat flush processing +ierat_iu3_flush_d <= iu_mm_ierat_flush; +ierat_iu3_valid_d <= iu_mm_ierat_req; +ierat_iu4_valid_d <= '1' when (ierat_iu3_valid_q='1' and or_reduce(ierat_iu3_thdid_q and not(ierat_iu3_flush_q) and not(xu_mm_ierat_flush_q))='1') + else '0'; +ierat_iu5_valid_d <= '1' when (ierat_iu4_valid_q='1' and or_reduce(ierat_iu4_thdid_q and not(ierat_iu3_flush_q) and not(xu_mm_ierat_flush_q))='1') + else '0'; +ierat_iu3_thdid_d <= iu_mm_ierat_thdid; +ierat_iu3_state_d <= iu_mm_ierat_state; +ierat_iu3_pid_d <= iu_mm_ierat_tid; +gen64_iu3_epn: if rs_data_width = 64 generate +ierat_iu3_epn_d <= iu_mm_ierat_epn; +end generate gen64_iu3_epn; +gen32_iu3_epn: if rs_data_width < 64 generate +ierat_iu3_epn_d <= (0 to 64-rs_data_width-1 => '0') & iu_mm_ierat_epn(64-rs_data_width to 51); +end generate gen32_iu3_epn; +ierat_iu4_thdid_d <= ierat_iu3_thdid_q; +ierat_iu4_epn_d <= ierat_iu3_epn_q; +ierat_iu4_state_d <= ierat_iu3_state_q; +ierat_iu4_pid_d <= ierat_iu3_pid_q; +ierat_iu5_thdid_d <= ierat_iu4_thdid_q; +ierat_iu5_epn_d <= ierat_iu4_epn_q; +ierat_iu5_state_d <= ierat_iu4_state_q; +ierat_iu5_pid_d <= ierat_iu4_pid_q; +-- ierat request queue logic pointers +ierat_inptr_d <= "00" when ierat_req0_valid_q='1' and ierat_req0_nonspec_q='0' and or_reduce(ierat_req0_thdid_q and (ierat_iu3_flush_q or xu_mm_ierat_flush_q))='1' + else "01" when ierat_req1_valid_q='1' and ierat_req1_nonspec_q='0' and or_reduce(ierat_req1_thdid_q and (ierat_iu3_flush_q or xu_mm_ierat_flush_q))='1' + else "10" when ierat_req2_valid_q='1' and ierat_req2_nonspec_q='0' and or_reduce(ierat_req2_thdid_q and (ierat_iu3_flush_q or xu_mm_ierat_flush_q))='1' + else "11" when ierat_req3_valid_q='1' and ierat_req3_nonspec_q='0' and or_reduce(ierat_req3_thdid_q and (ierat_iu3_flush_q or xu_mm_ierat_flush_q))='1' + else "01" when ierat_inptr_q="00" and ierat_req1_valid_q='0' and ierat_iu5_valid_q='1' and or_reduce(ierat_iu5_thdid_q and not(ierat_iu3_flush_q) and not(xu_mm_ierat_flush_q))='1' + else "10" when ierat_inptr_q="00" and ierat_req2_valid_q='0' and ierat_iu5_valid_q='1' and or_reduce(ierat_iu5_thdid_q and not(ierat_iu3_flush_q) and not(xu_mm_ierat_flush_q))='1' + else "11" when ierat_inptr_q="00" and ierat_req3_valid_q='0' and ierat_iu5_valid_q='1' and or_reduce(ierat_iu5_thdid_q and not(ierat_iu3_flush_q) and not(xu_mm_ierat_flush_q))='1' + else "10" when ierat_inptr_q="01" and ierat_req2_valid_q='0' and ierat_iu5_valid_q='1' and or_reduce(ierat_iu5_thdid_q and not(ierat_iu3_flush_q) and not(xu_mm_ierat_flush_q))='1' + else "11" when ierat_inptr_q="01" and ierat_req3_valid_q='0' and ierat_iu5_valid_q='1' and or_reduce(ierat_iu5_thdid_q and not(ierat_iu3_flush_q) and not(xu_mm_ierat_flush_q))='1' + else "00" when ierat_inptr_q="01" and ierat_req0_valid_q='0' and ierat_iu5_valid_q='1' and or_reduce(ierat_iu5_thdid_q and not(ierat_iu3_flush_q) and not(xu_mm_ierat_flush_q))='1' + else "11" when ierat_inptr_q="10" and ierat_req3_valid_q='0' and ierat_iu5_valid_q='1' and or_reduce(ierat_iu5_thdid_q and not(ierat_iu3_flush_q) and not(xu_mm_ierat_flush_q))='1' + else "00" when ierat_inptr_q="10" and ierat_req0_valid_q='0' and ierat_iu5_valid_q='1' and or_reduce(ierat_iu5_thdid_q and not(ierat_iu3_flush_q) and not(xu_mm_ierat_flush_q))='1' + else "01" when ierat_inptr_q="10" and ierat_req1_valid_q='0' and ierat_iu5_valid_q='1' and or_reduce(ierat_iu5_thdid_q and not(ierat_iu3_flush_q) and not(xu_mm_ierat_flush_q))='1' + else "00" when ierat_inptr_q="11" and ierat_req0_valid_q='0' and ierat_iu5_valid_q='1' and or_reduce(ierat_iu5_thdid_q and not(ierat_iu3_flush_q) and not(xu_mm_ierat_flush_q))='1' + else "01" when ierat_inptr_q="11" and ierat_req1_valid_q='0' and ierat_iu5_valid_q='1' and or_reduce(ierat_iu5_thdid_q and not(ierat_iu3_flush_q) and not(xu_mm_ierat_flush_q))='1' + else "10" when ierat_inptr_q="11" and ierat_req2_valid_q='0' and ierat_iu5_valid_q='1' and or_reduce(ierat_iu5_thdid_q and not(ierat_iu3_flush_q) and not(xu_mm_ierat_flush_q))='1' + else ierat_outptr_q when ierat_req_taken='1' + else ierat_inptr_q; +ierat_outptr_d <= "01" when ierat_outptr_q="00" and ierat_req0_valid_q='1' and ierat_req_taken='1' + else "10" when ierat_outptr_q="01" and ierat_req1_valid_q='1' and ierat_req_taken='1' + else "11" when ierat_outptr_q="10" and ierat_req2_valid_q='1' and ierat_req_taken='1' + else "00" when ierat_outptr_q="11" and ierat_req3_valid_q='1' and ierat_req_taken='1' + else "01" when ierat_outptr_q="00" and ierat_req0_valid_q='0' and ierat_req1_valid_q='1' + else "10" when ierat_outptr_q="00" and ierat_req0_valid_q='0' and ierat_req1_valid_q='0' and ierat_req2_valid_q='1' + else "11" when ierat_outptr_q="00" and ierat_req0_valid_q='0' and ierat_req1_valid_q='0' and ierat_req2_valid_q='0' and ierat_req3_valid_q='1' + else "10" when ierat_outptr_q="01" and ierat_req1_valid_q='0' and ierat_req2_valid_q='1' + else "11" when ierat_outptr_q="01" and ierat_req1_valid_q='0' and ierat_req2_valid_q='0' and ierat_req3_valid_q='1' + else "00" when ierat_outptr_q="01" and ierat_req1_valid_q='0' and ierat_req2_valid_q='0' and ierat_req3_valid_q='0' and ierat_req0_valid_q='1' + else "11" when ierat_outptr_q="10" and ierat_req2_valid_q='0' and ierat_req3_valid_q='1' + else "00" when ierat_outptr_q="10" and ierat_req2_valid_q='0' and ierat_req3_valid_q='0' and ierat_req0_valid_q='1' + else "01" when ierat_outptr_q="10" and ierat_req2_valid_q='0' and ierat_req3_valid_q='0' and ierat_req0_valid_q='0' and ierat_req1_valid_q='1' + else "00" when ierat_outptr_q="11" and ierat_req3_valid_q='0' and ierat_req0_valid_q='1' + else "01" when ierat_outptr_q="11" and ierat_req3_valid_q='0' and ierat_req0_valid_q='0' and ierat_req1_valid_q='1' + else "10" when ierat_outptr_q="11" and ierat_req3_valid_q='0' and ierat_req0_valid_q='0' and ierat_req1_valid_q='0' and ierat_req2_valid_q='1' + else ierat_outptr_q; +tlb_seq_ierat_req_d <= '1' when ((ierat_outptr_q="00" and ierat_req0_valid_q='1' and ierat_req0_nonspec_q='1' and or_reduce(ierat_req0_thdid_q and not(xu_mm_ierat_flush_q))='1') or + (ierat_outptr_q="01" and ierat_req1_valid_q='1' and ierat_req1_nonspec_q='1' and or_reduce(ierat_req1_thdid_q and not(xu_mm_ierat_flush_q))='1') or + (ierat_outptr_q="10" and ierat_req2_valid_q='1' and ierat_req2_nonspec_q='1' and or_reduce(ierat_req2_thdid_q and not(xu_mm_ierat_flush_q))='1') or + (ierat_outptr_q="11" and ierat_req3_valid_q='1' and ierat_req3_nonspec_q='1' and or_reduce(ierat_req3_thdid_q and not(xu_mm_ierat_flush_q))='1')) + else '0'; +tlb_seq_ierat_req <= tlb_seq_ierat_req_q; +-- i-erat queue valid bit is ierat_req_valid_q +-- tlb_cmp_ierat_dup_val bits 0:3 are req_tag5_match, 4 is tag5 hit_reload, 5 is stretched hit_reload, 6 is ierat iu5 stage dup +ierat_req0_valid_d <= '1' when (ierat_iu5_valid_q='1' and or_reduce(ierat_iu5_thdid_q and not(ierat_iu3_flush_q) and not(xu_mm_ierat_flush_q))='1' + and ierat_req0_valid_q='0' and ierat_inptr_q="00") + else '0' when (ierat_req0_valid_q='1' and ierat_req0_nonspec_q='0' and or_reduce(ierat_req0_thdid_q and xu_mm_ierat_flush_q)='1') + else '0' when (ierat_req0_valid_q='1' and ierat_req0_nonspec_q='0' and or_reduce(ierat_req0_thdid_q and ierat_iu3_flush_q)='1') + else '0' when (ierat_req_taken='1' and ierat_req0_valid_q='1' and ierat_req0_nonspec_q='1' and ierat_outptr_q="00") + else '0' when (ierat_req0_nonspec_q='1' and tlb_cmp_ierat_dup_val(0)='1' and tlb_cmp_ierat_dup_val(4)='1') + else ierat_req0_valid_q; +ierat_req0_nonspec_d <= '1' when (ierat_req0_valid_q='1' and ierat_req0_nonspec_q='0' + and or_reduce(ierat_req0_thdid_q and xu_mm_ierat_miss_q and not(xu_mm_ierat_flush_q))='1') + else '0' when (ierat_req0_valid_q='1' and or_reduce(ierat_req0_thdid_q and xu_mm_ierat_flush_q)='1') + else '0' when (ierat_req_taken='1' and ierat_req0_valid_q='1' and ierat_req0_nonspec_q='1' and ierat_outptr_q="00") + else '0' when (ierat_req0_nonspec_q='1' and tlb_cmp_ierat_dup_val(0)='1' and tlb_cmp_ierat_dup_val(4)='1') + else ierat_req0_nonspec_q; +ierat_req0_thdid_d(0 to 3) <= ierat_iu5_thdid_q when (ierat_iu5_valid_q='1' and ierat_req0_valid_q='0' and ierat_inptr_q="00") + else ierat_req0_thdid_q(0 to 3); +ierat_req0_epn_d <= ierat_iu5_epn_q when (ierat_iu5_valid_q='1' and ierat_req0_valid_q='0' and ierat_inptr_q="00") + else ierat_req0_epn_q; +ierat_req0_state_d <= ierat_iu5_state_q when (ierat_iu5_valid_q='1' and ierat_req0_valid_q='0' and ierat_inptr_q="00") + else ierat_req0_state_q; +ierat_req0_pid_d <= ierat_iu5_pid_q when (ierat_iu5_valid_q='1' and ierat_req0_valid_q='0' and ierat_inptr_q="00") + else ierat_req0_pid_q; +ierat_req0_dup_d(0) <= '0'; +ierat_req0_dup_d(1) <= '0' when (ierat_req_taken='1' and ierat_req0_valid_q='1' and ierat_outptr_q="00") + else tlb_cmp_ierat_dup_val(6) when (ierat_iu5_valid_q='1' and ierat_req0_valid_q='0' and ierat_inptr_q="00") + else tlb_cmp_ierat_dup_val(0) when (ierat_req0_valid_q='1' and ierat_req0_dup_q(1)='0' and tlb_cmp_ierat_dup_val(4)='0' and tlb_cmp_ierat_dup_val(5)='1') + else ierat_req0_dup_q(1); +ierat_req1_valid_d <= '1' when (ierat_iu5_valid_q='1' and or_reduce(ierat_iu5_thdid_q and not(ierat_iu3_flush_q) and not(xu_mm_ierat_flush_q))='1' + and ierat_req1_valid_q='0' and ierat_inptr_q="01") + else '0' when (ierat_req1_valid_q='1' and ierat_req1_nonspec_q='0' and or_reduce(ierat_req1_thdid_q and xu_mm_ierat_flush_q)='1') + else '0' when (ierat_req1_valid_q='1' and ierat_req1_nonspec_q='0' and or_reduce(ierat_req1_thdid_q and ierat_iu3_flush_q)='1') + else '0' when (ierat_req_taken='1' and ierat_req1_valid_q='1' and ierat_req1_nonspec_q='1' and ierat_outptr_q="01") + else '0' when (ierat_req1_nonspec_q='1' and tlb_cmp_ierat_dup_val(1)='1' and tlb_cmp_ierat_dup_val(4)='1') + else ierat_req1_valid_q; +ierat_req1_nonspec_d <= '1' when (ierat_req1_valid_q='1' and ierat_req1_nonspec_q='0' + and or_reduce(ierat_req1_thdid_q and xu_mm_ierat_miss_q and not(xu_mm_ierat_flush_q))='1') + else '0' when (ierat_req1_valid_q='1' and or_reduce(ierat_req1_thdid_q and xu_mm_ierat_flush_q)='1') + else '0' when (ierat_req_taken='1' and ierat_req1_valid_q='1' and ierat_req1_nonspec_q='1' and ierat_outptr_q="01") + else '0' when (ierat_req1_nonspec_q='1' and tlb_cmp_ierat_dup_val(1)='1' and tlb_cmp_ierat_dup_val(4)='1') + else ierat_req1_nonspec_q; +ierat_req1_thdid_d(0 to 3) <= ierat_iu5_thdid_q when (ierat_iu5_valid_q='1' and ierat_req1_valid_q='0' and ierat_inptr_q="01") + else ierat_req1_thdid_q(0 to 3); +ierat_req1_epn_d <= ierat_iu5_epn_q when (ierat_iu5_valid_q='1' and ierat_req1_valid_q='0' and ierat_inptr_q="01") + else ierat_req1_epn_q; +ierat_req1_state_d <= ierat_iu5_state_q when (ierat_iu5_valid_q='1' and ierat_req1_valid_q='0' and ierat_inptr_q="01") + else ierat_req1_state_q; +ierat_req1_pid_d <= ierat_iu5_pid_q when (ierat_iu5_valid_q='1' and ierat_req1_valid_q='0' and ierat_inptr_q="01") + else ierat_req1_pid_q; +ierat_req1_dup_d(0) <= '0'; +ierat_req1_dup_d(1) <= '0' when (ierat_req_taken='1' and ierat_req1_valid_q='1' and ierat_outptr_q="01") + else tlb_cmp_ierat_dup_val(6) when (ierat_iu5_valid_q='1' and ierat_req1_valid_q='0' and ierat_inptr_q="01") + else tlb_cmp_ierat_dup_val(1) when (ierat_req1_valid_q='1' and ierat_req1_dup_q(1)='0' and tlb_cmp_ierat_dup_val(4)='0' and tlb_cmp_ierat_dup_val(5)='1') + else ierat_req1_dup_q(1); +ierat_req2_valid_d <= '1' when (ierat_iu5_valid_q='1' and or_reduce(ierat_iu5_thdid_q and not(ierat_iu3_flush_q) and not(xu_mm_ierat_flush_q))='1' + and ierat_req2_valid_q='0' and ierat_inptr_q="10") + else '0' when (ierat_req2_valid_q='1' and ierat_req2_nonspec_q='0' and or_reduce(ierat_req2_thdid_q and xu_mm_ierat_flush_q)='1') + else '0' when (ierat_req2_valid_q='1' and ierat_req2_nonspec_q='0' and or_reduce(ierat_req2_thdid_q and ierat_iu3_flush_q)='1') + else '0' when (ierat_req_taken='1' and ierat_req2_valid_q='1' and ierat_req2_nonspec_q='1' and ierat_outptr_q="10") + else '0' when (ierat_req2_nonspec_q='1' and tlb_cmp_ierat_dup_val(2)='1' and tlb_cmp_ierat_dup_val(4)='1') + else ierat_req2_valid_q; +ierat_req2_nonspec_d <= '1' when (ierat_req2_valid_q='1' and ierat_req2_nonspec_q='0' + and or_reduce(ierat_req2_thdid_q and xu_mm_ierat_miss_q and not(xu_mm_ierat_flush_q))='1') + else '0' when (ierat_req2_valid_q='1' and or_reduce(ierat_req2_thdid_q and xu_mm_ierat_flush_q)='1') + else '0' when (ierat_req_taken='1' and ierat_req2_valid_q='1' and ierat_req2_nonspec_q='1' and ierat_outptr_q="10") + else '0' when (ierat_req2_nonspec_q='1' and tlb_cmp_ierat_dup_val(2)='1' and tlb_cmp_ierat_dup_val(4)='1') + else ierat_req2_nonspec_q; +ierat_req2_thdid_d(0 to 3) <= ierat_iu5_thdid_q when (ierat_iu5_valid_q='1' and ierat_req2_valid_q='0' and ierat_inptr_q="10") + else ierat_req2_thdid_q(0 to 3); +ierat_req2_epn_d <= ierat_iu5_epn_q when (ierat_iu5_valid_q='1' and ierat_req2_valid_q='0' and ierat_inptr_q="10") + else ierat_req2_epn_q; +ierat_req2_state_d <= ierat_iu5_state_q when (ierat_iu5_valid_q='1' and ierat_req2_valid_q='0' and ierat_inptr_q="10") + else ierat_req2_state_q; +ierat_req2_pid_d <= ierat_iu5_pid_q when (ierat_iu5_valid_q='1' and ierat_req2_valid_q='0' and ierat_inptr_q="10") + else ierat_req2_pid_q; +ierat_req2_dup_d(0) <= '0'; +ierat_req2_dup_d(1) <= '0' when (ierat_req_taken='1' and ierat_req2_valid_q='1' and ierat_outptr_q="10") + else tlb_cmp_ierat_dup_val(6) when (ierat_iu5_valid_q='1' and ierat_req2_valid_q='0' and ierat_inptr_q="10") + else tlb_cmp_ierat_dup_val(2) when (ierat_req2_valid_q='1' and ierat_req2_dup_q(1)='0' and tlb_cmp_ierat_dup_val(4)='0' and tlb_cmp_ierat_dup_val(5)='1') + else ierat_req2_dup_q(1); +ierat_req3_valid_d <= '1' when (ierat_iu5_valid_q='1' and or_reduce(ierat_iu5_thdid_q and not(ierat_iu3_flush_q) and not(xu_mm_ierat_flush_q))='1' + and ierat_req3_valid_q='0' and ierat_inptr_q="11") + else '0' when (ierat_req3_valid_q='1' and ierat_req3_nonspec_q='0' and or_reduce(ierat_req3_thdid_q and xu_mm_ierat_flush_q)='1') + else '0' when (ierat_req3_valid_q='1' and ierat_req3_nonspec_q='0' and or_reduce(ierat_req3_thdid_q and ierat_iu3_flush_q)='1') + else '0' when (ierat_req_taken='1' and ierat_req3_valid_q='1' and ierat_req3_nonspec_q='1' and ierat_outptr_q="11") + else '0' when (ierat_req3_nonspec_q='1' and tlb_cmp_ierat_dup_val(3)='1' and tlb_cmp_ierat_dup_val(4)='1') + else ierat_req3_valid_q; +ierat_req3_nonspec_d <= '1' when (ierat_req3_valid_q='1' and ierat_req3_nonspec_q='0' + and or_reduce(ierat_req3_thdid_q and xu_mm_ierat_miss_q and not(xu_mm_ierat_flush_q))='1') + else '0' when (ierat_req3_valid_q='1' and or_reduce(ierat_req3_thdid_q and xu_mm_ierat_flush_q)='1') + else '0' when (ierat_req_taken='1' and ierat_req3_valid_q='1' and ierat_req3_nonspec_q='1' and ierat_outptr_q="11") + else '0' when (ierat_req3_nonspec_q='1' and tlb_cmp_ierat_dup_val(3)='1' and tlb_cmp_ierat_dup_val(4)='1') + else ierat_req3_nonspec_q; +ierat_req3_thdid_d(0 to 3) <= ierat_iu5_thdid_q when (ierat_iu5_valid_q='1' and ierat_req3_valid_q='0' and ierat_inptr_q="11") + else ierat_req3_thdid_q(0 to 3); +ierat_req3_epn_d <= ierat_iu5_epn_q when (ierat_iu5_valid_q='1' and ierat_req3_valid_q='0' and ierat_inptr_q="11") + else ierat_req3_epn_q; +ierat_req3_state_d <= ierat_iu5_state_q when (ierat_iu5_valid_q='1' and ierat_req3_valid_q='0' and ierat_inptr_q="11") + else ierat_req3_state_q; +ierat_req3_pid_d <= ierat_iu5_pid_q when (ierat_iu5_valid_q='1' and ierat_req3_valid_q='0' and ierat_inptr_q="11") + else ierat_req3_pid_q; +ierat_req3_dup_d(0) <= '0'; +ierat_req3_dup_d(1) <= '0' when (ierat_req_taken='1' and ierat_req3_valid_q='1' and ierat_outptr_q="11") + else tlb_cmp_ierat_dup_val(6) when (ierat_iu5_valid_q='1' and ierat_req3_valid_q='0' and ierat_inptr_q="11") + else tlb_cmp_ierat_dup_val(3) when (ierat_req3_valid_q='1' and ierat_req3_dup_q(1)='0' and tlb_cmp_ierat_dup_val(4)='0' and tlb_cmp_ierat_dup_val(5)='1') + else ierat_req3_dup_q(1); +ierat_req_pid_mux <= pid1 when iu_mm_ierat_thdid(1)='1' + else pid2 when iu_mm_ierat_thdid(2)='1' + else pid3 when iu_mm_ierat_thdid(3)='1' + else pid0; +-- xu pipe for non-speculative derat flush processing +derat_ex4_valid_d <= '1' when (xu_mm_derat_req='1' and or_reduce(xu_mm_derat_thdid and not(xu_ex3_flush))='1') + else '0'; +derat_ex5_valid_d <= '1' when (derat_ex4_valid_q='1' and or_reduce(derat_ex4_thdid_q and not(xu_mm_ex4_flush))='1') + else '0'; +derat_ex6_valid_d <= '1' when (derat_ex5_valid_q='1' and or_reduce(derat_ex5_thdid_q and not(xu_mm_ex5_flush))='1') + else '0'; +gen64_ex4_epn: if rs_data_width = 64 generate +derat_ex4_epn_d <= xu_mm_derat_epn; +end generate gen64_ex4_epn; +gen32_ex4_epn: if rs_data_width < 64 generate +derat_ex4_epn_d <= (0 to 64-rs_data_width-1 => '0') & xu_mm_derat_epn(64-rs_data_width to 51); +end generate gen32_ex4_epn; +derat_ex4_thdid_d <= xu_mm_derat_thdid; +derat_ex4_state_d <= xu_mm_derat_state; +derat_ex4_ttype_d <= xu_mm_derat_ttype; +derat_ex4_pid_d <= xu_mm_derat_tid; +derat_ex4_lpid_d <= xu_mm_derat_lpid; +derat_ex5_thdid_d <= derat_ex4_thdid_q; +derat_ex5_epn_d <= derat_ex4_epn_q; +derat_ex5_state_d <= derat_ex4_state_q; +derat_ex5_ttype_d <= derat_ex4_ttype_q; +derat_ex5_pid_d <= derat_ex4_pid_q; +derat_ex6_thdid_d <= derat_ex5_thdid_q; +derat_ex6_epn_d <= derat_ex5_epn_q; +derat_ex6_state_d <= derat_ex5_state_q; +derat_ex6_ttype_d <= derat_ex5_ttype_q; +derat_ex6_pid_d <= derat_ex5_pid_q; +-- use derat lpid for external pid ops +derat_ex5_lpid_d <= derat_ex4_lpid_q when derat_ex4_valid_q='1' and derat_ex4_ttype_q(0)='1' + else lpidr; +derat_ex6_lpid_d <= derat_ex5_lpid_q when derat_ex5_valid_q='1' and derat_ex5_ttype_q(0)='1' + else lpidr; +-- derat request queue logic pointers +derat_inptr_d <= "01" when derat_inptr_q="00" and derat_req1_valid_q='0' and derat_ex6_valid_q='1' + else "10" when derat_inptr_q="00" and derat_req2_valid_q='0' and derat_ex6_valid_q='1' + else "11" when derat_inptr_q="00" and derat_req3_valid_q='0' and derat_ex6_valid_q='1' + else "10" when derat_inptr_q="01" and derat_req2_valid_q='0' and derat_ex6_valid_q='1' + else "11" when derat_inptr_q="01" and derat_req3_valid_q='0' and derat_ex6_valid_q='1' + else "00" when derat_inptr_q="01" and derat_req0_valid_q='0' and derat_ex6_valid_q='1' + else "11" when derat_inptr_q="10" and derat_req3_valid_q='0' and derat_ex6_valid_q='1' + else "00" when derat_inptr_q="10" and derat_req0_valid_q='0' and derat_ex6_valid_q='1' + else "01" when derat_inptr_q="10" and derat_req1_valid_q='0' and derat_ex6_valid_q='1' + else "00" when derat_inptr_q="11" and derat_req0_valid_q='0' and derat_ex6_valid_q='1' + else "01" when derat_inptr_q="11" and derat_req1_valid_q='0' and derat_ex6_valid_q='1' + else "10" when derat_inptr_q="11" and derat_req2_valid_q='0' and derat_ex6_valid_q='1' + else derat_outptr_q when derat_req_taken='1' + else derat_inptr_q; +derat_outptr_d <= "01" when derat_outptr_q="00" and derat_req0_valid_q='1' and derat_req_taken='1' + else "10" when derat_outptr_q="01" and derat_req1_valid_q='1' and derat_req_taken='1' + else "11" when derat_outptr_q="10" and derat_req2_valid_q='1' and derat_req_taken='1' + else "00" when derat_outptr_q="11" and derat_req3_valid_q='1' and derat_req_taken='1' + else "01" when derat_outptr_q="00" and derat_req0_valid_q='0' and derat_req1_valid_q='1' + else "10" when derat_outptr_q="00" and derat_req0_valid_q='0' and derat_req1_valid_q='0' and derat_req2_valid_q='1' + else "11" when derat_outptr_q="00" and derat_req0_valid_q='0' and derat_req1_valid_q='0' and derat_req2_valid_q='0' and derat_req3_valid_q='1' + else "10" when derat_outptr_q="01" and derat_req1_valid_q='0' and derat_req2_valid_q='1' + else "11" when derat_outptr_q="01" and derat_req1_valid_q='0' and derat_req2_valid_q='0' and derat_req3_valid_q='1' + else "00" when derat_outptr_q="01" and derat_req1_valid_q='0' and derat_req2_valid_q='0' and derat_req3_valid_q='0' and derat_req0_valid_q='1' + else "11" when derat_outptr_q="10" and derat_req2_valid_q='0' and derat_req3_valid_q='1' + else "00" when derat_outptr_q="10" and derat_req2_valid_q='0' and derat_req3_valid_q='0' and derat_req0_valid_q='1' + else "01" when derat_outptr_q="10" and derat_req2_valid_q='0' and derat_req3_valid_q='0' and derat_req0_valid_q='0' and derat_req1_valid_q='1' + else "00" when derat_outptr_q="11" and derat_req3_valid_q='0' and derat_req0_valid_q='1' + else "01" when derat_outptr_q="11" and derat_req3_valid_q='0' and derat_req0_valid_q='0' and derat_req1_valid_q='1' + else "10" when derat_outptr_q="11" and derat_req3_valid_q='0' and derat_req0_valid_q='0' and derat_req1_valid_q='0' and derat_req2_valid_q='1' + else derat_outptr_q; +tlb_seq_derat_req_d <= '1' when ((derat_outptr_q="00" and derat_req0_valid_q='1') or + (derat_outptr_q="01" and derat_req1_valid_q='1') or + (derat_outptr_q="10" and derat_req2_valid_q='1') or + (derat_outptr_q="11" and derat_req3_valid_q='1')) + else '0'; +tlb_seq_derat_req <= tlb_seq_derat_req_q; +-- d-erat queue valid bit is derat_req_valid_q +-- tlb_cmp_derat_dup_val : in std_ulogic_vector(0 to 6); -- bit 4 hit/miss pulse, 5 is stretched hit/miss, 6 is ex6 dup +derat_req0_valid_d <= '1' when (derat_ex6_valid_q='1' and derat_req0_valid_q='0' and derat_inptr_q="00") + else '0' when (derat_req_taken='1' and derat_req0_valid_q='1' and derat_outptr_q="00") + else '0' when (tlb_cmp_derat_dup_val(0)='1' and tlb_cmp_derat_dup_val(4)='1') + else derat_req0_valid_q; +derat_req0_thdid_d(0 to 3) <= derat_ex6_thdid_q when (derat_ex6_valid_q='1' and derat_req0_valid_q='0' and derat_inptr_q="00") + else derat_req0_thdid_q(0 to 3); +derat_req0_epn_d <= derat_ex6_epn_q when (derat_ex6_valid_q='1' and derat_req0_valid_q='0' and derat_inptr_q="00") + else derat_req0_epn_q; +derat_req0_state_d <= derat_ex6_state_q when (derat_ex6_valid_q='1' and derat_req0_valid_q='0' and derat_inptr_q="00") + else derat_req0_state_q; +derat_req0_ttype_d <= derat_ex6_ttype_q when (derat_ex6_valid_q='1' and derat_req0_valid_q='0' and derat_inptr_q="00") + else derat_req0_ttype_q; +derat_req0_pid_d <= derat_ex6_pid_q when (derat_ex6_valid_q='1' and derat_req0_valid_q='0' and derat_inptr_q="00") + else derat_req0_pid_q; +derat_req0_lpid_d <= derat_ex6_lpid_q when (derat_ex6_valid_q='1' and derat_req0_valid_q='0' and derat_inptr_q="00") + else derat_req0_lpid_q; +derat_req0_dup_d(0) <= '0'; +derat_req0_dup_d(1) <= '0' when (derat_req_taken='1' and derat_req0_valid_q='1' and derat_outptr_q="00") + else tlb_cmp_derat_dup_val(6) when (derat_ex6_valid_q='1' and derat_req0_valid_q='0' and derat_inptr_q="00") + else tlb_cmp_derat_dup_val(0) when (derat_req0_valid_q='1' and derat_req0_dup_q(1)='0' and tlb_cmp_derat_dup_val(4)='0' and tlb_cmp_derat_dup_val(5)='1') + else derat_req0_dup_q(1); +derat_req1_valid_d <= '1' when (derat_ex6_valid_q='1' and derat_req1_valid_q='0' and derat_inptr_q="01") + else '0' when (derat_req_taken='1' and derat_req1_valid_q='1' and derat_outptr_q="01") + else '0' when (tlb_cmp_derat_dup_val(1)='1' and tlb_cmp_derat_dup_val(4)='1') + else derat_req1_valid_q; +derat_req1_thdid_d(0 to 3) <= derat_ex6_thdid_q when (derat_ex6_valid_q='1' and derat_req1_valid_q='0' and derat_inptr_q="01") + else derat_req1_thdid_q(0 to 3); +derat_req1_epn_d <= derat_ex6_epn_q when (derat_ex6_valid_q='1' and derat_req1_valid_q='0' and derat_inptr_q="01") + else derat_req1_epn_q; +derat_req1_state_d <= derat_ex6_state_q when (derat_ex6_valid_q='1' and derat_req1_valid_q='0' and derat_inptr_q="01") + else derat_req1_state_q; +derat_req1_ttype_d <= derat_ex6_ttype_q when (derat_ex6_valid_q='1' and derat_req1_valid_q='0' and derat_inptr_q="01") + else derat_req1_ttype_q; +derat_req1_pid_d <= derat_ex6_pid_q when (derat_ex6_valid_q='1' and derat_req1_valid_q='0' and derat_inptr_q="01") + else derat_req1_pid_q; +derat_req1_lpid_d <= derat_ex6_lpid_q when (derat_ex6_valid_q='1' and derat_req1_valid_q='0' and derat_inptr_q="01") + else derat_req1_lpid_q; +derat_req1_dup_d(0) <= '0'; +derat_req1_dup_d(1) <= '0' when (derat_req_taken='1' and derat_req1_valid_q='1' and derat_outptr_q="01") + else tlb_cmp_derat_dup_val(6) when (derat_ex6_valid_q='1' and derat_req1_valid_q='0' and derat_inptr_q="01") + else tlb_cmp_derat_dup_val(1) when (derat_req1_valid_q='1' and derat_req1_dup_q(1)='0' and tlb_cmp_derat_dup_val(4)='0' and tlb_cmp_derat_dup_val(5)='1') + else derat_req1_dup_q(1); +derat_req2_valid_d <= '1' when (derat_ex6_valid_q='1' and derat_req2_valid_q='0' and derat_inptr_q="10") + else '0' when (derat_req_taken='1' and derat_req2_valid_q='1' and derat_outptr_q="10") + else '0' when (tlb_cmp_derat_dup_val(2)='1' and tlb_cmp_derat_dup_val(4)='1') + else derat_req2_valid_q; +derat_req2_thdid_d(0 to 3) <= derat_ex6_thdid_q when (derat_ex6_valid_q='1' and derat_req2_valid_q='0' and derat_inptr_q="10") + else derat_req2_thdid_q(0 to 3); +derat_req2_epn_d <= derat_ex6_epn_q when (derat_ex6_valid_q='1' and derat_req2_valid_q='0' and derat_inptr_q="10") + else derat_req2_epn_q; +derat_req2_state_d <= derat_ex6_state_q when (derat_ex6_valid_q='1' and derat_req2_valid_q='0' and derat_inptr_q="10") + else derat_req2_state_q; +derat_req2_ttype_d <= derat_ex6_ttype_q when (derat_ex6_valid_q='1' and derat_req2_valid_q='0' and derat_inptr_q="10") + else derat_req2_ttype_q; +derat_req2_pid_d <= derat_ex6_pid_q when (derat_ex6_valid_q='1' and derat_req2_valid_q='0' and derat_inptr_q="10") + else derat_req2_pid_q; +derat_req2_lpid_d <= derat_ex6_lpid_q when (derat_ex6_valid_q='1' and derat_req2_valid_q='0' and derat_inptr_q="10") + else derat_req2_lpid_q; +derat_req2_dup_d(0) <= '0'; +derat_req2_dup_d(1) <= '0' when (derat_req_taken='1' and derat_req2_valid_q='1' and derat_outptr_q="10") + else tlb_cmp_derat_dup_val(6) when (derat_ex6_valid_q='1' and derat_req2_valid_q='0' and derat_inptr_q="10") + else tlb_cmp_derat_dup_val(2) when (derat_req2_valid_q='1' and derat_req2_dup_q(1)='0' and tlb_cmp_derat_dup_val(4)='0' and tlb_cmp_derat_dup_val(5)='1') + else derat_req2_dup_q(1); +derat_req3_valid_d <= '1' when (derat_ex6_valid_q='1' and derat_req3_valid_q='0' and derat_inptr_q="11") + else '0' when (derat_req_taken='1' and derat_req3_valid_q='1' and derat_outptr_q="11") + else '0' when (tlb_cmp_derat_dup_val(3)='1' and tlb_cmp_derat_dup_val(4)='1') + else derat_req3_valid_q; +derat_req3_thdid_d(0 to 3) <= derat_ex6_thdid_q when (derat_ex6_valid_q='1' and derat_req3_valid_q='0' and derat_inptr_q="11") + else derat_req3_thdid_q(0 to 3); +derat_req3_epn_d <= derat_ex6_epn_q when (derat_ex6_valid_q='1' and derat_req3_valid_q='0' and derat_inptr_q="11") + else derat_req3_epn_q; +derat_req3_state_d <= derat_ex6_state_q when (derat_ex6_valid_q='1' and derat_req3_valid_q='0' and derat_inptr_q="11") + else derat_req3_state_q; +derat_req3_ttype_d <= derat_ex6_ttype_q when (derat_ex6_valid_q='1' and derat_req3_valid_q='0' and derat_inptr_q="11") + else derat_req3_ttype_q; +derat_req3_pid_d <= derat_ex6_pid_q when (derat_ex6_valid_q='1' and derat_req3_valid_q='0' and derat_inptr_q="11") + else derat_req3_pid_q; +derat_req3_lpid_d <= derat_ex6_lpid_q when (derat_ex6_valid_q='1' and derat_req3_valid_q='0' and derat_inptr_q="11") + else derat_req3_lpid_q; +derat_req3_dup_d(0) <= '0'; +derat_req3_dup_d(1) <= '0' when (derat_req_taken='1' and derat_req3_valid_q='1' and derat_outptr_q="11") + else tlb_cmp_derat_dup_val(6) when (derat_ex6_valid_q='1' and derat_req3_valid_q='0' and derat_inptr_q="11") + else tlb_cmp_derat_dup_val(3) when (derat_req3_valid_q='1' and derat_req3_dup_q(1)='0' and tlb_cmp_derat_dup_val(4)='0' and tlb_cmp_derat_dup_val(5)='1') + else derat_req3_dup_q(1); +----------------------------------------------------------------------- +-- output assignments +----------------------------------------------------------------------- +ierat_req_epn <= ierat_req1_epn_q when (ierat_outptr_q="01") + else ierat_req2_epn_q when (ierat_outptr_q="10") + else ierat_req3_epn_q when (ierat_outptr_q="11") + else ierat_req0_epn_q; +ierat_req_pid <= ierat_req1_pid_q when (ierat_outptr_q="01") + else ierat_req2_pid_q when (ierat_outptr_q="10") + else ierat_req3_pid_q when (ierat_outptr_q="11") + else ierat_req0_pid_q; +ierat_req_state <= ierat_req1_state_q when (ierat_outptr_q="01") + else ierat_req2_state_q when (ierat_outptr_q="10") + else ierat_req3_state_q when (ierat_outptr_q="11") + else ierat_req0_state_q; +ierat_req_thdid <= ierat_req1_thdid_q(0 to thdid_width-1) when (ierat_outptr_q="01") + else ierat_req2_thdid_q(0 to thdid_width-1) when (ierat_outptr_q="10") + else ierat_req3_thdid_q(0 to thdid_width-1) when (ierat_outptr_q="11") + else ierat_req0_thdid_q(0 to thdid_width-1); +ierat_req_dup <= ierat_req1_dup_q(0 to 1) when (ierat_outptr_q="01") + else ierat_req2_dup_q(0 to 1) when (ierat_outptr_q="10") + else ierat_req3_dup_q(0 to 1) when (ierat_outptr_q="11") + else ierat_req0_dup_q(0 to 1); +derat_req_epn <= derat_req1_epn_q when (derat_outptr_q="01") + else derat_req2_epn_q when (derat_outptr_q="10") + else derat_req3_epn_q when (derat_outptr_q="11") + else derat_req0_epn_q; +derat_req_pid <= derat_req1_pid_q when (derat_outptr_q="01") + else derat_req2_pid_q when (derat_outptr_q="10") + else derat_req3_pid_q when (derat_outptr_q="11") + else derat_req0_pid_q; +derat_req_lpid <= derat_req1_lpid_q when (derat_outptr_q="01") + else derat_req2_lpid_q when (derat_outptr_q="10") + else derat_req3_lpid_q when (derat_outptr_q="11") + else derat_req0_lpid_q; +derat_req_state <= derat_req1_state_q when (derat_outptr_q="01") + else derat_req2_state_q when (derat_outptr_q="10") + else derat_req3_state_q when (derat_outptr_q="11") + else derat_req0_state_q; +derat_req_ttype <= derat_req1_ttype_q when (derat_outptr_q="01") + else derat_req2_ttype_q when (derat_outptr_q="10") + else derat_req3_ttype_q when (derat_outptr_q="11") + else derat_req0_ttype_q; +derat_req_thdid <= derat_req1_thdid_q(0 to thdid_width-1) when (derat_outptr_q="01") + else derat_req2_thdid_q(0 to thdid_width-1) when (derat_outptr_q="10") + else derat_req3_thdid_q(0 to thdid_width-1) when (derat_outptr_q="11") + else derat_req0_thdid_q(0 to thdid_width-1); +derat_req_dup <= derat_req1_dup_q(0 to 1) when (derat_outptr_q="01") + else derat_req2_dup_q(0 to 1) when (derat_outptr_q="10") + else derat_req3_dup_q(0 to 1) when (derat_outptr_q="11") + else derat_req0_dup_q(0 to 1); +ierat_req0_pid <= ierat_req0_pid_q; +ierat_req0_gs <= ierat_req0_state_q(1); +ierat_req0_as <= ierat_req0_state_q(2); +ierat_req0_epn <= ierat_req0_epn_q; +ierat_req0_thdid <= ierat_req0_thdid_q; +ierat_req0_valid <= ierat_req0_valid_q; +ierat_req0_nonspec <= ierat_req0_nonspec_q; +ierat_req1_pid <= ierat_req1_pid_q; +ierat_req1_gs <= ierat_req1_state_q(1); +ierat_req1_as <= ierat_req1_state_q(2); +ierat_req1_epn <= ierat_req1_epn_q; +ierat_req1_thdid <= ierat_req1_thdid_q; +ierat_req1_valid <= ierat_req1_valid_q; +ierat_req1_nonspec <= ierat_req1_nonspec_q; +ierat_req2_pid <= ierat_req2_pid_q; +ierat_req2_gs <= ierat_req2_state_q(1); +ierat_req2_as <= ierat_req2_state_q(2); +ierat_req2_epn <= ierat_req2_epn_q; +ierat_req2_thdid <= ierat_req2_thdid_q; +ierat_req2_valid <= ierat_req2_valid_q; +ierat_req2_nonspec <= ierat_req2_nonspec_q; +ierat_req3_pid <= ierat_req3_pid_q; +ierat_req3_gs <= ierat_req3_state_q(1); +ierat_req3_as <= ierat_req3_state_q(2); +ierat_req3_epn <= ierat_req3_epn_q; +ierat_req3_thdid <= ierat_req3_thdid_q; +ierat_req3_valid <= ierat_req3_valid_q; +ierat_req3_nonspec <= ierat_req3_nonspec_q; +ierat_iu4_pid <= ierat_iu4_pid_q; +ierat_iu4_gs <= ierat_iu4_state_q(1); +ierat_iu4_as <= ierat_iu4_state_q(2); +ierat_iu4_epn <= ierat_iu4_epn_q; +ierat_iu4_thdid <= ierat_iu4_thdid_q; +ierat_iu4_valid <= ierat_iu4_valid_q; +derat_req0_lpid <= derat_req0_lpid_q; +derat_req0_pid <= derat_req0_pid_q; +derat_req0_gs <= derat_req0_state_q(1); +derat_req0_as <= derat_req0_state_q(2); +derat_req0_epn <= derat_req0_epn_q; +derat_req0_thdid <= derat_req0_thdid_q; +derat_req0_valid <= derat_req0_valid_q; +derat_req1_lpid <= derat_req1_lpid_q; +derat_req1_pid <= derat_req1_pid_q; +derat_req1_gs <= derat_req1_state_q(1); +derat_req1_as <= derat_req1_state_q(2); +derat_req1_epn <= derat_req1_epn_q; +derat_req1_thdid <= derat_req1_thdid_q; +derat_req1_valid <= derat_req1_valid_q; +derat_req2_lpid <= derat_req2_lpid_q; +derat_req2_pid <= derat_req2_pid_q; +derat_req2_gs <= derat_req2_state_q(1); +derat_req2_as <= derat_req2_state_q(2); +derat_req2_epn <= derat_req2_epn_q; +derat_req2_thdid <= derat_req2_thdid_q; +derat_req2_valid <= derat_req2_valid_q; +derat_req3_lpid <= derat_req3_lpid_q; +derat_req3_pid <= derat_req3_pid_q; +derat_req3_gs <= derat_req3_state_q(1); +derat_req3_as <= derat_req3_state_q(2); +derat_req3_epn <= derat_req3_epn_q; +derat_req3_thdid <= derat_req3_thdid_q; +derat_req3_valid <= derat_req3_valid_q; +derat_ex5_lpid <= derat_ex5_lpid_q; +derat_ex5_pid <= derat_ex5_pid_q; +derat_ex5_gs <= derat_ex5_state_q(1); +derat_ex5_as <= derat_ex5_state_q(2); +derat_ex5_epn <= derat_ex5_epn_q; +derat_ex5_thdid <= derat_ex5_thdid_q; +derat_ex5_valid <= derat_ex5_valid_q; +tlb_req_dbg_ierat_iu5_valid_q <= ierat_iu5_valid_q; +tlb_req_dbg_ierat_iu5_thdid(0) <= ierat_iu5_thdid_q(2) or ierat_iu5_thdid_q(3); +tlb_req_dbg_ierat_iu5_thdid(1) <= ierat_iu5_thdid_q(1) or ierat_iu5_thdid_q(3); +tlb_req_dbg_ierat_iu5_state_q <= ierat_iu5_state_q; +tlb_req_dbg_ierat_inptr_q <= ierat_inptr_q; +tlb_req_dbg_ierat_outptr_q <= ierat_outptr_q; +tlb_req_dbg_ierat_req_valid_q <= ierat_req0_valid_q & ierat_req1_valid_q & ierat_req2_valid_q & ierat_req3_valid_q; +tlb_req_dbg_ierat_req_nonspec_q <= ierat_req0_nonspec_q & ierat_req1_nonspec_q & ierat_req2_nonspec_q & ierat_req3_nonspec_q; +tlb_req_dbg_ierat_req_thdid(0) <= ierat_req0_thdid_q(2) or ierat_req0_thdid_q(3); +tlb_req_dbg_ierat_req_thdid(1) <= ierat_req0_thdid_q(1) or ierat_req0_thdid_q(3); +tlb_req_dbg_ierat_req_thdid(2) <= ierat_req1_thdid_q(2) or ierat_req1_thdid_q(3); +tlb_req_dbg_ierat_req_thdid(3) <= ierat_req1_thdid_q(1) or ierat_req1_thdid_q(3); +tlb_req_dbg_ierat_req_thdid(4) <= ierat_req2_thdid_q(2) or ierat_req2_thdid_q(3); +tlb_req_dbg_ierat_req_thdid(5) <= ierat_req2_thdid_q(1) or ierat_req2_thdid_q(3); +tlb_req_dbg_ierat_req_thdid(6) <= ierat_req3_thdid_q(2) or ierat_req3_thdid_q(3); +tlb_req_dbg_ierat_req_thdid(7) <= ierat_req3_thdid_q(1) or ierat_req3_thdid_q(3); +tlb_req_dbg_ierat_req_dup_q <= ierat_req0_dup_q(1) & ierat_req1_dup_q(1) & ierat_req2_dup_q(1) & ierat_req3_dup_q(1); +tlb_req_dbg_derat_ex6_valid_q <= derat_ex6_valid_q; +tlb_req_dbg_derat_ex6_thdid(0) <= derat_ex6_thdid_q(2) or derat_ex6_thdid_q(3); +tlb_req_dbg_derat_ex6_thdid(1) <= derat_ex6_thdid_q(1) or derat_ex6_thdid_q(3); +tlb_req_dbg_derat_ex6_state_q <= derat_ex6_state_q; +tlb_req_dbg_derat_inptr_q <= derat_inptr_q; +tlb_req_dbg_derat_outptr_q <= derat_outptr_q; +tlb_req_dbg_derat_req_valid_q <= derat_req0_valid_q & derat_req1_valid_q & derat_req2_valid_q & derat_req3_valid_q; +tlb_req_dbg_derat_req_thdid(0) <= derat_req0_thdid_q(2) or derat_req0_thdid_q(3); +tlb_req_dbg_derat_req_thdid(1) <= derat_req0_thdid_q(1) or derat_req0_thdid_q(3); +tlb_req_dbg_derat_req_thdid(2) <= derat_req1_thdid_q(2) or derat_req1_thdid_q(3); +tlb_req_dbg_derat_req_thdid(3) <= derat_req1_thdid_q(1) or derat_req1_thdid_q(3); +tlb_req_dbg_derat_req_thdid(4) <= derat_req2_thdid_q(2) or derat_req2_thdid_q(3); +tlb_req_dbg_derat_req_thdid(5) <= derat_req2_thdid_q(1) or derat_req2_thdid_q(3); +tlb_req_dbg_derat_req_thdid(6) <= derat_req3_thdid_q(2) or derat_req3_thdid_q(3); +tlb_req_dbg_derat_req_thdid(7) <= derat_req3_thdid_q(1) or derat_req3_thdid_q(3); +tlb_req_dbg_derat_req_ttype_q(0 to 1) <= derat_req0_ttype_q(0 to 1); +tlb_req_dbg_derat_req_ttype_q(2 to 3) <= derat_req1_ttype_q(0 to 1); +tlb_req_dbg_derat_req_ttype_q(4 to 5) <= derat_req2_ttype_q(0 to 1); +tlb_req_dbg_derat_req_ttype_q(6 to 7) <= derat_req3_ttype_q(0 to 1); +tlb_req_dbg_derat_req_dup_q <= derat_req0_dup_q(1) & derat_req1_dup_q(1) & derat_req2_dup_q(1) & derat_req3_dup_q(1); +-- unused spare signal assignments +unused_dc(0) <= or_reduce(LCB_DELAY_LCLKR_DC(1 TO 4)); +unused_dc(1) <= or_reduce(LCB_MPW1_DC_B(1 TO 4)); +unused_dc(2) <= PC_FUNC_SL_FORCE; +unused_dc(3) <= PC_FUNC_SL_THOLD_0_B; +unused_dc(4) <= TC_SCAN_DIS_DC_B; +unused_dc(5) <= TC_SCAN_DIAG_DC; +unused_dc(6) <= TC_LBIST_EN_DC; +unused_dc(7) <= or_reduce(IERAT_REQ_PID_MUX); +unused_dc(8) <= or_reduce(MM_XU_ERATMISS_DONE); +unused_dc(9) <= or_reduce(MM_XU_TLB_MISS); +unused_dc(10) <= TLB_SEQ_IERAT_DONE; +unused_dc(11) <= TLB_SEQ_DERAT_DONE; +unused_dc(12) <= mmucr2_act_override; +----------------------------------------------------------------------- +-- Latches +----------------------------------------------------------------------- +-- ierat miss request latches +ierat_req0_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_req0_valid_offset), + scout => sov(ierat_req0_valid_offset), + din => ierat_req0_valid_d, + dout => ierat_req0_valid_q); +ierat_req0_nonspec_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_req0_nonspec_offset), + scout => sov(ierat_req0_nonspec_offset), + din => ierat_req0_nonspec_d, + dout => ierat_req0_nonspec_q); +ierat_req0_thdid_latch: tri_rlmreg_p + generic map (width => ierat_req0_thdid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_req0_thdid_offset to ierat_req0_thdid_offset+ierat_req0_thdid_q'length-1), + scout => sov(ierat_req0_thdid_offset to ierat_req0_thdid_offset+ierat_req0_thdid_q'length-1), + din => ierat_req0_thdid_d(0 to thdid_width-1), + dout => ierat_req0_thdid_q(0 to thdid_width-1) ); +ierat_req0_epn_latch: tri_rlmreg_p + generic map (width => ierat_req0_epn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_req0_epn_offset to ierat_req0_epn_offset+ierat_req0_epn_q'length-1), + scout => sov(ierat_req0_epn_offset to ierat_req0_epn_offset+ierat_req0_epn_q'length-1), + din => ierat_req0_epn_d(0 to req_epn_width-1), + dout => ierat_req0_epn_q(0 to req_epn_width-1) ); +ierat_req0_state_latch: tri_rlmreg_p + generic map (width => ierat_req0_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_req0_state_offset to ierat_req0_state_offset+ierat_req0_state_q'length-1), + scout => sov(ierat_req0_state_offset to ierat_req0_state_offset+ierat_req0_state_q'length-1), + din => ierat_req0_state_d(0 to state_width-1), + dout => ierat_req0_state_q(0 to state_width-1) ); +ierat_req0_pid_latch: tri_rlmreg_p + generic map (width => ierat_req0_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_req0_pid_offset to ierat_req0_pid_offset+ierat_req0_pid_q'length-1), + scout => sov(ierat_req0_pid_offset to ierat_req0_pid_offset+ierat_req0_pid_q'length-1), + din => ierat_req0_pid_d(0 to pid_width-1), + dout => ierat_req0_pid_q(0 to pid_width-1) ); +ierat_req0_dup_latch: tri_rlmreg_p + generic map (width => ierat_req0_dup_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_req0_dup_offset to ierat_req0_dup_offset+ierat_req0_dup_q'length-1), + scout => sov(ierat_req0_dup_offset to ierat_req0_dup_offset+ierat_req0_dup_q'length-1), + din => ierat_req0_dup_d, + dout => ierat_req0_dup_q ); +ierat_req1_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_req1_valid_offset), + scout => sov(ierat_req1_valid_offset), + din => ierat_req1_valid_d, + dout => ierat_req1_valid_q); +ierat_req1_nonspec_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_req1_nonspec_offset), + scout => sov(ierat_req1_nonspec_offset), + din => ierat_req1_nonspec_d, + dout => ierat_req1_nonspec_q); +ierat_req1_thdid_latch: tri_rlmreg_p + generic map (width => ierat_req1_thdid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_req1_thdid_offset to ierat_req1_thdid_offset+ierat_req1_thdid_q'length-1), + scout => sov(ierat_req1_thdid_offset to ierat_req1_thdid_offset+ierat_req1_thdid_q'length-1), + din => ierat_req1_thdid_d(0 to thdid_width-1), + dout => ierat_req1_thdid_q(0 to thdid_width-1) ); +ierat_req1_epn_latch: tri_rlmreg_p + generic map (width => ierat_req1_epn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_req1_epn_offset to ierat_req1_epn_offset+ierat_req1_epn_q'length-1), + scout => sov(ierat_req1_epn_offset to ierat_req1_epn_offset+ierat_req1_epn_q'length-1), + din => ierat_req1_epn_d(0 to req_epn_width-1), + dout => ierat_req1_epn_q(0 to req_epn_width-1) ); +ierat_req1_state_latch: tri_rlmreg_p + generic map (width => ierat_req1_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_req1_state_offset to ierat_req1_state_offset+ierat_req1_state_q'length-1), + scout => sov(ierat_req1_state_offset to ierat_req1_state_offset+ierat_req1_state_q'length-1), + din => ierat_req1_state_d(0 to state_width-1), + dout => ierat_req1_state_q(0 to state_width-1) ); +ierat_req1_pid_latch: tri_rlmreg_p + generic map (width => ierat_req1_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_req1_pid_offset to ierat_req1_pid_offset+ierat_req1_pid_q'length-1), + scout => sov(ierat_req1_pid_offset to ierat_req1_pid_offset+ierat_req1_pid_q'length-1), + din => ierat_req1_pid_d(0 to pid_width-1), + dout => ierat_req1_pid_q(0 to pid_width-1) ); +ierat_req1_dup_latch: tri_rlmreg_p + generic map (width => ierat_req1_dup_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_req1_dup_offset to ierat_req1_dup_offset+ierat_req1_dup_q'length-1), + scout => sov(ierat_req1_dup_offset to ierat_req1_dup_offset+ierat_req1_dup_q'length-1), + din => ierat_req1_dup_d, + dout => ierat_req1_dup_q ); +ierat_req2_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_req2_valid_offset), + scout => sov(ierat_req2_valid_offset), + din => ierat_req2_valid_d, + dout => ierat_req2_valid_q); +ierat_req2_nonspec_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_req2_nonspec_offset), + scout => sov(ierat_req2_nonspec_offset), + din => ierat_req2_nonspec_d, + dout => ierat_req2_nonspec_q); +ierat_req2_thdid_latch: tri_rlmreg_p + generic map (width => ierat_req2_thdid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_req2_thdid_offset to ierat_req2_thdid_offset+ierat_req2_thdid_q'length-1), + scout => sov(ierat_req2_thdid_offset to ierat_req2_thdid_offset+ierat_req2_thdid_q'length-1), + din => ierat_req2_thdid_d(0 to thdid_width-1), + dout => ierat_req2_thdid_q(0 to thdid_width-1) ); +ierat_req2_epn_latch: tri_rlmreg_p + generic map (width => ierat_req2_epn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_req2_epn_offset to ierat_req2_epn_offset+ierat_req2_epn_q'length-1), + scout => sov(ierat_req2_epn_offset to ierat_req2_epn_offset+ierat_req2_epn_q'length-1), + din => ierat_req2_epn_d(0 to req_epn_width-1), + dout => ierat_req2_epn_q(0 to req_epn_width-1) ); +ierat_req2_state_latch: tri_rlmreg_p + generic map (width => ierat_req2_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_req2_state_offset to ierat_req2_state_offset+ierat_req2_state_q'length-1), + scout => sov(ierat_req2_state_offset to ierat_req2_state_offset+ierat_req2_state_q'length-1), + din => ierat_req2_state_d(0 to state_width-1), + dout => ierat_req2_state_q(0 to state_width-1) ); +ierat_req2_pid_latch: tri_rlmreg_p + generic map (width => ierat_req2_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_req2_pid_offset to ierat_req2_pid_offset+ierat_req2_pid_q'length-1), + scout => sov(ierat_req2_pid_offset to ierat_req2_pid_offset+ierat_req2_pid_q'length-1), + din => ierat_req2_pid_d(0 to pid_width-1), + dout => ierat_req2_pid_q(0 to pid_width-1) ); +ierat_req2_dup_latch: tri_rlmreg_p + generic map (width => ierat_req2_dup_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_req2_dup_offset to ierat_req2_dup_offset+ierat_req2_dup_q'length-1), + scout => sov(ierat_req2_dup_offset to ierat_req2_dup_offset+ierat_req2_dup_q'length-1), + din => ierat_req2_dup_d, + dout => ierat_req2_dup_q ); +ierat_req3_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_req3_valid_offset), + scout => sov(ierat_req3_valid_offset), + din => ierat_req3_valid_d, + dout => ierat_req3_valid_q); +ierat_req3_nonspec_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_req3_nonspec_offset), + scout => sov(ierat_req3_nonspec_offset), + din => ierat_req3_nonspec_d, + dout => ierat_req3_nonspec_q); +ierat_req3_thdid_latch: tri_rlmreg_p + generic map (width => ierat_req3_thdid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_req3_thdid_offset to ierat_req3_thdid_offset+ierat_req3_thdid_q'length-1), + scout => sov(ierat_req3_thdid_offset to ierat_req3_thdid_offset+ierat_req3_thdid_q'length-1), + din => ierat_req3_thdid_d(0 to thdid_width-1), + dout => ierat_req3_thdid_q(0 to thdid_width-1) ); +ierat_req3_epn_latch: tri_rlmreg_p + generic map (width => ierat_req3_epn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_req3_epn_offset to ierat_req3_epn_offset+ierat_req3_epn_q'length-1), + scout => sov(ierat_req3_epn_offset to ierat_req3_epn_offset+ierat_req3_epn_q'length-1), + din => ierat_req3_epn_d(0 to req_epn_width-1), + dout => ierat_req3_epn_q(0 to req_epn_width-1) ); +ierat_req3_state_latch: tri_rlmreg_p + generic map (width => ierat_req3_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_req3_state_offset to ierat_req3_state_offset+ierat_req3_state_q'length-1), + scout => sov(ierat_req3_state_offset to ierat_req3_state_offset+ierat_req3_state_q'length-1), + din => ierat_req3_state_d(0 to state_width-1), + dout => ierat_req3_state_q(0 to state_width-1) ); +ierat_req3_pid_latch: tri_rlmreg_p + generic map (width => ierat_req3_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_req3_pid_offset to ierat_req3_pid_offset+ierat_req3_pid_q'length-1), + scout => sov(ierat_req3_pid_offset to ierat_req3_pid_offset+ierat_req3_pid_q'length-1), + din => ierat_req3_pid_d(0 to pid_width-1), + dout => ierat_req3_pid_q(0 to pid_width-1) ); +ierat_req3_dup_latch: tri_rlmreg_p + generic map (width => ierat_req3_dup_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_req3_dup_offset to ierat_req3_dup_offset+ierat_req3_dup_q'length-1), + scout => sov(ierat_req3_dup_offset to ierat_req3_dup_offset+ierat_req3_dup_q'length-1), + din => ierat_req3_dup_d, + dout => ierat_req3_dup_q ); +ierat_inptr_latch: tri_rlmreg_p + generic map (width => ierat_inptr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_inptr_offset to ierat_inptr_offset+ierat_inptr_q'length-1), + scout => sov(ierat_inptr_offset to ierat_inptr_offset+ierat_inptr_q'length-1), + din => ierat_inptr_d, + dout => ierat_inptr_q ); +ierat_outptr_latch: tri_rlmreg_p + generic map (width => ierat_outptr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_outptr_offset to ierat_outptr_offset+ierat_outptr_q'length-1), + scout => sov(ierat_outptr_offset to ierat_outptr_offset+ierat_outptr_q'length-1), + din => ierat_outptr_d, + dout => ierat_outptr_q ); +ierat_iu3_flush_latch: tri_rlmreg_p + generic map (width => ierat_iu3_flush_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_iu3_flush_offset to ierat_iu3_flush_offset+ierat_iu3_flush_q'length-1), + scout => sov(ierat_iu3_flush_offset to ierat_iu3_flush_offset+ierat_iu3_flush_q'length-1), + din => ierat_iu3_flush_d, + dout => ierat_iu3_flush_q ); +tlb_seq_ierat_req_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_seq_ierat_req_offset), + scout => sov(tlb_seq_ierat_req_offset), + din => tlb_seq_ierat_req_d, + dout => tlb_seq_ierat_req_q); +xu_mm_ierat_flush_latch: tri_rlmreg_p + generic map (width => xu_mm_ierat_flush_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(xu_mm_ierat_flush_offset to xu_mm_ierat_flush_offset+xu_mm_ierat_flush_q'length-1), + scout => sov(xu_mm_ierat_flush_offset to xu_mm_ierat_flush_offset+xu_mm_ierat_flush_q'length-1), + din => xu_mm_ierat_flush_d, + dout => xu_mm_ierat_flush_q ); +xu_mm_ierat_miss_latch: tri_rlmreg_p + generic map (width => xu_mm_ierat_miss_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(xu_mm_ierat_miss_offset to xu_mm_ierat_miss_offset+xu_mm_ierat_miss_q'length-1), + scout => sov(xu_mm_ierat_miss_offset to xu_mm_ierat_miss_offset+xu_mm_ierat_miss_q'length-1), + din => xu_mm_ierat_miss_d, + dout => xu_mm_ierat_miss_q ); +-- ierat miss request latches +ierat_iu3_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_iu3_valid_offset), + scout => sov(ierat_iu3_valid_offset), + din => ierat_iu3_valid_d, + dout => ierat_iu3_valid_q); +ierat_iu3_thdid_latch: tri_rlmreg_p + generic map (width => ierat_iu3_thdid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_iu3_thdid_offset to ierat_iu3_thdid_offset+ierat_iu3_thdid_q'length-1), + scout => sov(ierat_iu3_thdid_offset to ierat_iu3_thdid_offset+ierat_iu3_thdid_q'length-1), + din => ierat_iu3_thdid_d(0 to thdid_width-1), + dout => ierat_iu3_thdid_q(0 to thdid_width-1) ); +ierat_iu3_epn_latch: tri_rlmreg_p + generic map (width => ierat_iu3_epn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_iu3_epn_offset to ierat_iu3_epn_offset+ierat_iu3_epn_q'length-1), + scout => sov(ierat_iu3_epn_offset to ierat_iu3_epn_offset+ierat_iu3_epn_q'length-1), + din => ierat_iu3_epn_d(0 to req_epn_width-1), + dout => ierat_iu3_epn_q(0 to req_epn_width-1) ); +ierat_iu3_state_latch: tri_rlmreg_p + generic map (width => ierat_iu3_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_iu3_state_offset to ierat_iu3_state_offset+ierat_iu3_state_q'length-1), + scout => sov(ierat_iu3_state_offset to ierat_iu3_state_offset+ierat_iu3_state_q'length-1), + din => ierat_iu3_state_d(0 to state_width-1), + dout => ierat_iu3_state_q(0 to state_width-1) ); +ierat_iu3_pid_latch: tri_rlmreg_p + generic map (width => ierat_iu3_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_iu3_pid_offset to ierat_iu3_pid_offset+ierat_iu3_pid_q'length-1), + scout => sov(ierat_iu3_pid_offset to ierat_iu3_pid_offset+ierat_iu3_pid_q'length-1), + din => ierat_iu3_pid_d(0 to pid_width-1), + dout => ierat_iu3_pid_q(0 to pid_width-1) ); +ierat_iu4_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_iu4_valid_offset), + scout => sov(ierat_iu4_valid_offset), + din => ierat_iu4_valid_d, + dout => ierat_iu4_valid_q); +ierat_iu4_thdid_latch: tri_rlmreg_p + generic map (width => ierat_iu4_thdid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_iu4_thdid_offset to ierat_iu4_thdid_offset+ierat_iu4_thdid_q'length-1), + scout => sov(ierat_iu4_thdid_offset to ierat_iu4_thdid_offset+ierat_iu4_thdid_q'length-1), + din => ierat_iu4_thdid_d(0 to thdid_width-1), + dout => ierat_iu4_thdid_q(0 to thdid_width-1) ); +ierat_iu4_epn_latch: tri_rlmreg_p + generic map (width => ierat_iu4_epn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_iu4_epn_offset to ierat_iu4_epn_offset+ierat_iu4_epn_q'length-1), + scout => sov(ierat_iu4_epn_offset to ierat_iu4_epn_offset+ierat_iu4_epn_q'length-1), + din => ierat_iu4_epn_d(0 to req_epn_width-1), + dout => ierat_iu4_epn_q(0 to req_epn_width-1) ); +ierat_iu4_state_latch: tri_rlmreg_p + generic map (width => ierat_iu4_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_iu4_state_offset to ierat_iu4_state_offset+ierat_iu4_state_q'length-1), + scout => sov(ierat_iu4_state_offset to ierat_iu4_state_offset+ierat_iu4_state_q'length-1), + din => ierat_iu4_state_d(0 to state_width-1), + dout => ierat_iu4_state_q(0 to state_width-1) ); +ierat_iu4_pid_latch: tri_rlmreg_p + generic map (width => ierat_iu4_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_iu4_pid_offset to ierat_iu4_pid_offset+ierat_iu4_pid_q'length-1), + scout => sov(ierat_iu4_pid_offset to ierat_iu4_pid_offset+ierat_iu4_pid_q'length-1), + din => ierat_iu4_pid_d(0 to pid_width-1), + dout => ierat_iu4_pid_q(0 to pid_width-1) ); +ierat_iu5_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_iu5_valid_offset), + scout => sov(ierat_iu5_valid_offset), + din => ierat_iu5_valid_d, + dout => ierat_iu5_valid_q); +ierat_iu5_thdid_latch: tri_rlmreg_p + generic map (width => ierat_iu5_thdid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_iu5_thdid_offset to ierat_iu5_thdid_offset+ierat_iu5_thdid_q'length-1), + scout => sov(ierat_iu5_thdid_offset to ierat_iu5_thdid_offset+ierat_iu5_thdid_q'length-1), + din => ierat_iu5_thdid_d(0 to thdid_width-1), + dout => ierat_iu5_thdid_q(0 to thdid_width-1) ); +ierat_iu5_epn_latch: tri_rlmreg_p + generic map (width => ierat_iu5_epn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_iu5_epn_offset to ierat_iu5_epn_offset+ierat_iu5_epn_q'length-1), + scout => sov(ierat_iu5_epn_offset to ierat_iu5_epn_offset+ierat_iu5_epn_q'length-1), + din => ierat_iu5_epn_d(0 to req_epn_width-1), + dout => ierat_iu5_epn_q(0 to req_epn_width-1) ); +ierat_iu5_state_latch: tri_rlmreg_p + generic map (width => ierat_iu5_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_iu5_state_offset to ierat_iu5_state_offset+ierat_iu5_state_q'length-1), + scout => sov(ierat_iu5_state_offset to ierat_iu5_state_offset+ierat_iu5_state_q'length-1), + din => ierat_iu5_state_d(0 to state_width-1), + dout => ierat_iu5_state_q(0 to state_width-1) ); +ierat_iu5_pid_latch: tri_rlmreg_p + generic map (width => ierat_iu5_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(ierat_iu5_pid_offset to ierat_iu5_pid_offset+ierat_iu5_pid_q'length-1), + scout => sov(ierat_iu5_pid_offset to ierat_iu5_pid_offset+ierat_iu5_pid_q'length-1), + din => ierat_iu5_pid_d(0 to pid_width-1), + dout => ierat_iu5_pid_q(0 to pid_width-1) ); +-- derat miss request latches +derat_req0_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req0_valid_offset), + scout => sov(derat_req0_valid_offset), + din => derat_req0_valid_d, + dout => derat_req0_valid_q); +derat_req0_thdid_latch: tri_rlmreg_p + generic map (width => derat_req0_thdid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req0_thdid_offset to derat_req0_thdid_offset+derat_req0_thdid_q'length-1), + scout => sov(derat_req0_thdid_offset to derat_req0_thdid_offset+derat_req0_thdid_q'length-1), + din => derat_req0_thdid_d(0 to thdid_width-1), + dout => derat_req0_thdid_q(0 to thdid_width-1) ); +derat_req0_epn_latch: tri_rlmreg_p + generic map (width => derat_req0_epn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req0_epn_offset to derat_req0_epn_offset+derat_req0_epn_q'length-1), + scout => sov(derat_req0_epn_offset to derat_req0_epn_offset+derat_req0_epn_q'length-1), + din => derat_req0_epn_d(0 to req_epn_width-1), + dout => derat_req0_epn_q(0 to req_epn_width-1) ); +derat_req0_state_latch: tri_rlmreg_p + generic map (width => derat_req0_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req0_state_offset to derat_req0_state_offset+derat_req0_state_q'length-1), + scout => sov(derat_req0_state_offset to derat_req0_state_offset+derat_req0_state_q'length-1), + din => derat_req0_state_d(0 to state_width-1), + dout => derat_req0_state_q(0 to state_width-1) ); +derat_req0_ttype_latch: tri_rlmreg_p + generic map (width => derat_req0_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req0_ttype_offset to derat_req0_ttype_offset+derat_req0_ttype_q'length-1), + scout => sov(derat_req0_ttype_offset to derat_req0_ttype_offset+derat_req0_ttype_q'length-1), + din => derat_req0_ttype_d, + dout => derat_req0_ttype_q ); +derat_req0_pid_latch: tri_rlmreg_p + generic map (width => derat_req0_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req0_pid_offset to derat_req0_pid_offset+derat_req0_pid_q'length-1), + scout => sov(derat_req0_pid_offset to derat_req0_pid_offset+derat_req0_pid_q'length-1), + din => derat_req0_pid_d(0 to pid_width-1), + dout => derat_req0_pid_q(0 to pid_width-1) ); +derat_req0_lpid_latch: tri_rlmreg_p + generic map (width => derat_req0_lpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req0_lpid_offset to derat_req0_lpid_offset+derat_req0_lpid_q'length-1), + scout => sov(derat_req0_lpid_offset to derat_req0_lpid_offset+derat_req0_lpid_q'length-1), + din => derat_req0_lpid_d(0 to lpid_width-1), + dout => derat_req0_lpid_q(0 to lpid_width-1) ); +derat_req0_dup_latch: tri_rlmreg_p + generic map (width => derat_req0_dup_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req0_dup_offset to derat_req0_dup_offset+derat_req0_dup_q'length-1), + scout => sov(derat_req0_dup_offset to derat_req0_dup_offset+derat_req0_dup_q'length-1), + din => derat_req0_dup_d, + dout => derat_req0_dup_q ); +derat_req1_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req1_valid_offset), + scout => sov(derat_req1_valid_offset), + din => derat_req1_valid_d, + dout => derat_req1_valid_q); +derat_req1_thdid_latch: tri_rlmreg_p + generic map (width => derat_req1_thdid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req1_thdid_offset to derat_req1_thdid_offset+derat_req1_thdid_q'length-1), + scout => sov(derat_req1_thdid_offset to derat_req1_thdid_offset+derat_req1_thdid_q'length-1), + din => derat_req1_thdid_d(0 to thdid_width-1), + dout => derat_req1_thdid_q(0 to thdid_width-1) ); +derat_req1_epn_latch: tri_rlmreg_p + generic map (width => derat_req1_epn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req1_epn_offset to derat_req1_epn_offset+derat_req1_epn_q'length-1), + scout => sov(derat_req1_epn_offset to derat_req1_epn_offset+derat_req1_epn_q'length-1), + din => derat_req1_epn_d(0 to req_epn_width-1), + dout => derat_req1_epn_q(0 to req_epn_width-1) ); +derat_req1_state_latch: tri_rlmreg_p + generic map (width => derat_req1_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req1_state_offset to derat_req1_state_offset+derat_req1_state_q'length-1), + scout => sov(derat_req1_state_offset to derat_req1_state_offset+derat_req1_state_q'length-1), + din => derat_req1_state_d(0 to state_width-1), + dout => derat_req1_state_q(0 to state_width-1) ); +derat_req1_ttype_latch: tri_rlmreg_p + generic map (width => derat_req1_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req1_ttype_offset to derat_req1_ttype_offset+derat_req1_ttype_q'length-1), + scout => sov(derat_req1_ttype_offset to derat_req1_ttype_offset+derat_req1_ttype_q'length-1), + din => derat_req1_ttype_d, + dout => derat_req1_ttype_q ); +derat_req1_pid_latch: tri_rlmreg_p + generic map (width => derat_req1_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req1_pid_offset to derat_req1_pid_offset+derat_req1_pid_q'length-1), + scout => sov(derat_req1_pid_offset to derat_req1_pid_offset+derat_req1_pid_q'length-1), + din => derat_req1_pid_d(0 to pid_width-1), + dout => derat_req1_pid_q(0 to pid_width-1) ); +derat_req1_lpid_latch: tri_rlmreg_p + generic map (width => derat_req1_lpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req1_lpid_offset to derat_req1_lpid_offset+derat_req1_lpid_q'length-1), + scout => sov(derat_req1_lpid_offset to derat_req1_lpid_offset+derat_req1_lpid_q'length-1), + din => derat_req1_lpid_d(0 to lpid_width-1), + dout => derat_req1_lpid_q(0 to lpid_width-1) ); +derat_req1_dup_latch: tri_rlmreg_p + generic map (width => derat_req1_dup_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req1_dup_offset to derat_req1_dup_offset+derat_req1_dup_q'length-1), + scout => sov(derat_req1_dup_offset to derat_req1_dup_offset+derat_req1_dup_q'length-1), + din => derat_req1_dup_d, + dout => derat_req1_dup_q ); +derat_req2_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req2_valid_offset), + scout => sov(derat_req2_valid_offset), + din => derat_req2_valid_d, + dout => derat_req2_valid_q); +derat_req2_thdid_latch: tri_rlmreg_p + generic map (width => derat_req2_thdid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req2_thdid_offset to derat_req2_thdid_offset+derat_req2_thdid_q'length-1), + scout => sov(derat_req2_thdid_offset to derat_req2_thdid_offset+derat_req2_thdid_q'length-1), + din => derat_req2_thdid_d(0 to thdid_width-1), + dout => derat_req2_thdid_q(0 to thdid_width-1) ); +derat_req2_epn_latch: tri_rlmreg_p + generic map (width => derat_req2_epn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req2_epn_offset to derat_req2_epn_offset+derat_req2_epn_q'length-1), + scout => sov(derat_req2_epn_offset to derat_req2_epn_offset+derat_req2_epn_q'length-1), + din => derat_req2_epn_d(0 to req_epn_width-1), + dout => derat_req2_epn_q(0 to req_epn_width-1) ); +derat_req2_state_latch: tri_rlmreg_p + generic map (width => derat_req2_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req2_state_offset to derat_req2_state_offset+derat_req2_state_q'length-1), + scout => sov(derat_req2_state_offset to derat_req2_state_offset+derat_req2_state_q'length-1), + din => derat_req2_state_d(0 to state_width-1), + dout => derat_req2_state_q(0 to state_width-1) ); +derat_req2_ttype_latch: tri_rlmreg_p + generic map (width => derat_req2_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req2_ttype_offset to derat_req2_ttype_offset+derat_req2_ttype_q'length-1), + scout => sov(derat_req2_ttype_offset to derat_req2_ttype_offset+derat_req2_ttype_q'length-1), + din => derat_req2_ttype_d, + dout => derat_req2_ttype_q ); +derat_req2_pid_latch: tri_rlmreg_p + generic map (width => derat_req2_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req2_pid_offset to derat_req2_pid_offset+derat_req2_pid_q'length-1), + scout => sov(derat_req2_pid_offset to derat_req2_pid_offset+derat_req2_pid_q'length-1), + din => derat_req2_pid_d(0 to pid_width-1), + dout => derat_req2_pid_q(0 to pid_width-1) ); +derat_req2_lpid_latch: tri_rlmreg_p + generic map (width => derat_req2_lpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req2_lpid_offset to derat_req2_lpid_offset+derat_req2_lpid_q'length-1), + scout => sov(derat_req2_lpid_offset to derat_req2_lpid_offset+derat_req2_lpid_q'length-1), + din => derat_req2_lpid_d(0 to lpid_width-1), + dout => derat_req2_lpid_q(0 to lpid_width-1) ); +derat_req2_dup_latch: tri_rlmreg_p + generic map (width => derat_req2_dup_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req2_dup_offset to derat_req2_dup_offset+derat_req2_dup_q'length-1), + scout => sov(derat_req2_dup_offset to derat_req2_dup_offset+derat_req2_dup_q'length-1), + din => derat_req2_dup_d, + dout => derat_req2_dup_q ); +derat_req3_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req3_valid_offset), + scout => sov(derat_req3_valid_offset), + din => derat_req3_valid_d, + dout => derat_req3_valid_q); +derat_req3_thdid_latch: tri_rlmreg_p + generic map (width => derat_req3_thdid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req3_thdid_offset to derat_req3_thdid_offset+derat_req3_thdid_q'length-1), + scout => sov(derat_req3_thdid_offset to derat_req3_thdid_offset+derat_req3_thdid_q'length-1), + din => derat_req3_thdid_d(0 to thdid_width-1), + dout => derat_req3_thdid_q(0 to thdid_width-1) ); +derat_req3_epn_latch: tri_rlmreg_p + generic map (width => derat_req3_epn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req3_epn_offset to derat_req3_epn_offset+derat_req3_epn_q'length-1), + scout => sov(derat_req3_epn_offset to derat_req3_epn_offset+derat_req3_epn_q'length-1), + din => derat_req3_epn_d(0 to req_epn_width-1), + dout => derat_req3_epn_q(0 to req_epn_width-1) ); +derat_req3_state_latch: tri_rlmreg_p + generic map (width => derat_req3_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req3_state_offset to derat_req3_state_offset+derat_req3_state_q'length-1), + scout => sov(derat_req3_state_offset to derat_req3_state_offset+derat_req3_state_q'length-1), + din => derat_req3_state_d(0 to state_width-1), + dout => derat_req3_state_q(0 to state_width-1) ); +derat_req3_ttype_latch: tri_rlmreg_p + generic map (width => derat_req3_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req3_ttype_offset to derat_req3_ttype_offset+derat_req3_ttype_q'length-1), + scout => sov(derat_req3_ttype_offset to derat_req3_ttype_offset+derat_req3_ttype_q'length-1), + din => derat_req3_ttype_d, + dout => derat_req3_ttype_q ); +derat_req3_pid_latch: tri_rlmreg_p + generic map (width => derat_req3_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req3_pid_offset to derat_req3_pid_offset+derat_req3_pid_q'length-1), + scout => sov(derat_req3_pid_offset to derat_req3_pid_offset+derat_req3_pid_q'length-1), + din => derat_req3_pid_d(0 to pid_width-1), + dout => derat_req3_pid_q(0 to pid_width-1) ); +derat_req3_lpid_latch: tri_rlmreg_p + generic map (width => derat_req3_lpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req3_lpid_offset to derat_req3_lpid_offset+derat_req3_lpid_q'length-1), + scout => sov(derat_req3_lpid_offset to derat_req3_lpid_offset+derat_req3_lpid_q'length-1), + din => derat_req3_lpid_d(0 to lpid_width-1), + dout => derat_req3_lpid_q(0 to lpid_width-1) ); +derat_req3_dup_latch: tri_rlmreg_p + generic map (width => derat_req3_dup_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_req3_dup_offset to derat_req3_dup_offset+derat_req3_dup_q'length-1), + scout => sov(derat_req3_dup_offset to derat_req3_dup_offset+derat_req3_dup_q'length-1), + din => derat_req3_dup_d, + dout => derat_req3_dup_q ); +derat_inptr_latch: tri_rlmreg_p + generic map (width => derat_inptr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_inptr_offset to derat_inptr_offset+derat_inptr_q'length-1), + scout => sov(derat_inptr_offset to derat_inptr_offset+derat_inptr_q'length-1), + din => derat_inptr_d, + dout => derat_inptr_q ); +derat_outptr_latch: tri_rlmreg_p + generic map (width => derat_outptr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_outptr_offset to derat_outptr_offset+derat_outptr_q'length-1), + scout => sov(derat_outptr_offset to derat_outptr_offset+derat_outptr_q'length-1), + din => derat_outptr_d, + dout => derat_outptr_q ); +tlb_seq_derat_req_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(tlb_seq_derat_req_offset), + scout => sov(tlb_seq_derat_req_offset), + din => tlb_seq_derat_req_d, + dout => tlb_seq_derat_req_q); +-- derat miss request latches +derat_ex4_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_ex4_valid_offset), + scout => sov(derat_ex4_valid_offset), + din => derat_ex4_valid_d, + dout => derat_ex4_valid_q); +derat_ex4_thdid_latch: tri_rlmreg_p + generic map (width => derat_ex4_thdid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_ex4_thdid_offset to derat_ex4_thdid_offset+derat_ex4_thdid_q'length-1), + scout => sov(derat_ex4_thdid_offset to derat_ex4_thdid_offset+derat_ex4_thdid_q'length-1), + din => derat_ex4_thdid_d(0 to thdid_width-1), + dout => derat_ex4_thdid_q(0 to thdid_width-1) ); +derat_ex4_epn_latch: tri_rlmreg_p + generic map (width => derat_ex4_epn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_ex4_epn_offset to derat_ex4_epn_offset+derat_ex4_epn_q'length-1), + scout => sov(derat_ex4_epn_offset to derat_ex4_epn_offset+derat_ex4_epn_q'length-1), + din => derat_ex4_epn_d(0 to req_epn_width-1), + dout => derat_ex4_epn_q(0 to req_epn_width-1) ); +derat_ex4_state_latch: tri_rlmreg_p + generic map (width => derat_ex4_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_ex4_state_offset to derat_ex4_state_offset+derat_ex4_state_q'length-1), + scout => sov(derat_ex4_state_offset to derat_ex4_state_offset+derat_ex4_state_q'length-1), + din => derat_ex4_state_d(0 to state_width-1), + dout => derat_ex4_state_q(0 to state_width-1) ); +derat_ex4_ttype_latch: tri_rlmreg_p + generic map (width => derat_ex4_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_ex4_ttype_offset to derat_ex4_ttype_offset+derat_ex4_ttype_q'length-1), + scout => sov(derat_ex4_ttype_offset to derat_ex4_ttype_offset+derat_ex4_ttype_q'length-1), + din => derat_ex4_ttype_d, + dout => derat_ex4_ttype_q ); +derat_ex4_pid_latch: tri_rlmreg_p + generic map (width => derat_ex4_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_ex4_pid_offset to derat_ex4_pid_offset+derat_ex4_pid_q'length-1), + scout => sov(derat_ex4_pid_offset to derat_ex4_pid_offset+derat_ex4_pid_q'length-1), + din => derat_ex4_pid_d(0 to pid_width-1), + dout => derat_ex4_pid_q(0 to pid_width-1) ); +derat_ex4_lpid_latch: tri_rlmreg_p + generic map (width => derat_ex4_lpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_ex4_lpid_offset to derat_ex4_lpid_offset+derat_ex4_lpid_q'length-1), + scout => sov(derat_ex4_lpid_offset to derat_ex4_lpid_offset+derat_ex4_lpid_q'length-1), + din => derat_ex4_lpid_d(0 to lpid_width-1), + dout => derat_ex4_lpid_q(0 to lpid_width-1) ); +derat_ex5_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_ex5_valid_offset), + scout => sov(derat_ex5_valid_offset), + din => derat_ex5_valid_d, + dout => derat_ex5_valid_q); +derat_ex5_thdid_latch: tri_rlmreg_p + generic map (width => derat_ex5_thdid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_ex5_thdid_offset to derat_ex5_thdid_offset+derat_ex5_thdid_q'length-1), + scout => sov(derat_ex5_thdid_offset to derat_ex5_thdid_offset+derat_ex5_thdid_q'length-1), + din => derat_ex5_thdid_d(0 to thdid_width-1), + dout => derat_ex5_thdid_q(0 to thdid_width-1) ); +derat_ex5_epn_latch: tri_rlmreg_p + generic map (width => derat_ex5_epn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_ex5_epn_offset to derat_ex5_epn_offset+derat_ex5_epn_q'length-1), + scout => sov(derat_ex5_epn_offset to derat_ex5_epn_offset+derat_ex5_epn_q'length-1), + din => derat_ex5_epn_d(0 to req_epn_width-1), + dout => derat_ex5_epn_q(0 to req_epn_width-1) ); +derat_ex5_state_latch: tri_rlmreg_p + generic map (width => derat_ex5_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_ex5_state_offset to derat_ex5_state_offset+derat_ex5_state_q'length-1), + scout => sov(derat_ex5_state_offset to derat_ex5_state_offset+derat_ex5_state_q'length-1), + din => derat_ex5_state_d(0 to state_width-1), + dout => derat_ex5_state_q(0 to state_width-1) ); +derat_ex5_ttype_latch: tri_rlmreg_p + generic map (width => derat_ex5_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_ex5_ttype_offset to derat_ex5_ttype_offset+derat_ex5_ttype_q'length-1), + scout => sov(derat_ex5_ttype_offset to derat_ex5_ttype_offset+derat_ex5_ttype_q'length-1), + din => derat_ex5_ttype_d, + dout => derat_ex5_ttype_q ); +derat_ex5_pid_latch: tri_rlmreg_p + generic map (width => derat_ex5_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_ex5_pid_offset to derat_ex5_pid_offset+derat_ex5_pid_q'length-1), + scout => sov(derat_ex5_pid_offset to derat_ex5_pid_offset+derat_ex5_pid_q'length-1), + din => derat_ex5_pid_d(0 to pid_width-1), + dout => derat_ex5_pid_q(0 to pid_width-1) ); +derat_ex5_lpid_latch: tri_rlmreg_p + generic map (width => derat_ex5_lpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_ex5_lpid_offset to derat_ex5_lpid_offset+derat_ex5_lpid_q'length-1), + scout => sov(derat_ex5_lpid_offset to derat_ex5_lpid_offset+derat_ex5_lpid_q'length-1), + din => derat_ex5_lpid_d(0 to lpid_width-1), + dout => derat_ex5_lpid_q(0 to lpid_width-1) ); +derat_ex6_valid_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_ex6_valid_offset), + scout => sov(derat_ex6_valid_offset), + din => derat_ex6_valid_d, + dout => derat_ex6_valid_q); +derat_ex6_thdid_latch: tri_rlmreg_p + generic map (width => derat_ex6_thdid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_ex6_thdid_offset to derat_ex6_thdid_offset+derat_ex6_thdid_q'length-1), + scout => sov(derat_ex6_thdid_offset to derat_ex6_thdid_offset+derat_ex6_thdid_q'length-1), + din => derat_ex6_thdid_d(0 to thdid_width-1), + dout => derat_ex6_thdid_q(0 to thdid_width-1) ); +derat_ex6_epn_latch: tri_rlmreg_p + generic map (width => derat_ex6_epn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_ex6_epn_offset to derat_ex6_epn_offset+derat_ex6_epn_q'length-1), + scout => sov(derat_ex6_epn_offset to derat_ex6_epn_offset+derat_ex6_epn_q'length-1), + din => derat_ex6_epn_d(0 to req_epn_width-1), + dout => derat_ex6_epn_q(0 to req_epn_width-1) ); +derat_ex6_state_latch: tri_rlmreg_p + generic map (width => derat_ex6_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_ex6_state_offset to derat_ex6_state_offset+derat_ex6_state_q'length-1), + scout => sov(derat_ex6_state_offset to derat_ex6_state_offset+derat_ex6_state_q'length-1), + din => derat_ex6_state_d(0 to state_width-1), + dout => derat_ex6_state_q(0 to state_width-1) ); +derat_ex6_ttype_latch: tri_rlmreg_p + generic map (width => derat_ex6_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_ex6_ttype_offset to derat_ex6_ttype_offset+derat_ex6_ttype_q'length-1), + scout => sov(derat_ex6_ttype_offset to derat_ex6_ttype_offset+derat_ex6_ttype_q'length-1), + din => derat_ex6_ttype_d, + dout => derat_ex6_ttype_q ); +derat_ex6_pid_latch: tri_rlmreg_p + generic map (width => derat_ex6_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_ex6_pid_offset to derat_ex6_pid_offset+derat_ex6_pid_q'length-1), + scout => sov(derat_ex6_pid_offset to derat_ex6_pid_offset+derat_ex6_pid_q'length-1), + din => derat_ex6_pid_d(0 to pid_width-1), + dout => derat_ex6_pid_q(0 to pid_width-1) ); +derat_ex6_lpid_latch: tri_rlmreg_p + generic map (width => derat_ex6_lpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(derat_ex6_lpid_offset to derat_ex6_lpid_offset+derat_ex6_lpid_q'length-1), + scout => sov(derat_ex6_lpid_offset to derat_ex6_lpid_offset+derat_ex6_lpid_q'length-1), + din => derat_ex6_lpid_d(0 to lpid_width-1), + dout => derat_ex6_lpid_q(0 to lpid_width-1) ); +spare_latch: tri_rlmreg_p + generic map (width => spare_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_mm_ccr2_notlb_b, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv(spare_offset to spare_offset+spare_q'length-1), + scout => sov(spare_offset to spare_offset+spare_q'length-1), + din => spare_q, + dout => spare_q ); +-------------------------------------------------- +-- thold/sg latches +-------------------------------------------------- +perv_2to1_reg: tri_plat + generic map (width => 3, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ccflush_dc, + din(0) => pc_func_sl_thold_2, + din(1) => pc_func_slp_sl_thold_2, + din(2) => pc_sg_2, + q(0) => pc_func_sl_thold_1, + q(1) => pc_func_slp_sl_thold_1, + q(2) => pc_sg_1); +perv_1to0_reg: tri_plat + generic map (width => 3, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => tc_ccflush_dc, + din(0) => pc_func_sl_thold_1, + din(1) => pc_func_slp_sl_thold_1, + din(2) => pc_sg_1, + q(0) => pc_func_sl_thold_0, + q(1) => pc_func_slp_sl_thold_0, + q(2) => pc_sg_0); +perv_lcbor_func_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b, + thold => pc_func_sl_thold_0, + sg => pc_sg_0, + act_dis => lcb_act_dis_dc, + forcee => pc_func_sl_force, + thold_b => pc_func_sl_thold_0_b); +perv_lcbor_func_slp_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b, + thold => pc_func_slp_sl_thold_0, + sg => pc_sg_0, + act_dis => lcb_act_dis_dc, + forcee => pc_func_slp_sl_force, + thold_b => pc_func_slp_sl_thold_0_b); +----------------------------------------------------------------------- +-- Scan +----------------------------------------------------------------------- +siv(0 to scan_right) <= sov(1 to scan_right) & ac_func_scan_in; +ac_func_scan_out <= sov(0); +end mmq_tlb_req; diff --git a/rel/src/vhdl/work/pcq.vhdl b/rel/src/vhdl/work/pcq.vhdl new file mode 100644 index 0000000..2bc0d9d --- /dev/null +++ b/rel/src/vhdl/work/pcq.vhdl @@ -0,0 +1,1349 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- +-- Description: Pervasive Core Unit +-- +--***************************************************************************** + +library ieee; +use ieee.std_logic_1164.all; +library ibm,clib; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +library support; +use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + + +entity pcq is +generic(expand_type : integer := 2; -- 0=ibm (Umbra), 1=non-ibm, 2=ibm (MPG) + regmode : integer := 6 -- 6=64-bit model, 5=32-bit model +); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + +-- SCOM and Register Interfaces + --SCOM Satellite + an_ac_scom_sat_id : in std_ulogic_vector(0 to 3); + an_ac_scom_dch : in std_ulogic; + an_ac_scom_cch : in std_ulogic; + ac_an_scom_dch : out std_ulogic; + ac_an_scom_cch : out std_ulogic; + --Slow SPR + slowspr_val_in : in std_ulogic; + slowspr_rw_in : in std_ulogic; + slowspr_etid_in : in std_ulogic_vector(0 to 1); + slowspr_addr_in : in std_ulogic_vector(0 to 9); + slowspr_data_in : in std_ulogic_vector(64-(2**regmode) to 63); + slowspr_done_in : in std_ulogic; + slowspr_val_out : out std_ulogic; + slowspr_rw_out : out std_ulogic; + slowspr_etid_out : out std_ulogic_vector(0 to 1); + slowspr_addr_out : out std_ulogic_vector(0 to 9); + slowspr_data_out : out std_ulogic_vector(64-(2**regmode) to 63); + slowspr_done_out : out std_ulogic; + +-- FIR and Error Signals + ac_an_special_attn : out std_ulogic_vector(0 to 3); + ac_an_checkstop : out std_ulogic_vector(0 to 2); + ac_an_local_checkstop : out std_ulogic_vector(0 to 2); + ac_an_recov_err : out std_ulogic_vector(0 to 2); + ac_an_trace_error : out std_ulogic; + an_ac_checkstop : in std_ulogic; + an_ac_malf_alert : in std_ulogic; + iu_pc_err_icache_parity : in std_ulogic; + iu_pc_err_icachedir_parity : in std_ulogic; + iu_pc_err_icachedir_multihit : in std_ulogic; + iu_pc_err_ucode_illegal : in std_ulogic_vector(0 to 3); + xu_pc_err_dcache_parity : in std_ulogic; + xu_pc_err_dcachedir_parity : in std_ulogic; + xu_pc_err_dcachedir_multihit : in std_ulogic; + xu_pc_err_mcsr_summary : in std_ulogic_vector(0 to 3); + xu_pc_err_ierat_parity : in std_ulogic; + xu_pc_err_derat_parity : in std_ulogic; + xu_pc_err_tlb_parity : in std_ulogic; + xu_pc_err_tlb_lru_parity : in std_ulogic; + xu_pc_err_ierat_multihit : in std_ulogic; + xu_pc_err_derat_multihit : in std_ulogic; + xu_pc_err_tlb_multihit : in std_ulogic; + xu_pc_err_ext_mchk : in std_ulogic; + xu_pc_err_ditc_overrun : in std_ulogic; + xu_pc_err_local_snoop_reject : in std_ulogic; + xu_pc_err_sprg_ecc : in std_ulogic_vector(0 to 3); + xu_pc_err_sprg_ue : in std_ulogic_vector(0 to 3); + xu_pc_err_regfile_parity : in std_ulogic_vector(0 to 3); + xu_pc_err_regfile_ue : in std_ulogic_vector(0 to 3); + xu_pc_err_llbust_attempt : in std_ulogic_vector(0 to 3); + xu_pc_err_llbust_failed : in std_ulogic_vector(0 to 3); + xu_pc_err_l2intrf_ecc : in std_ulogic; + xu_pc_err_l2intrf_ue : in std_ulogic; + xu_pc_err_l2credit_overrun : in std_ulogic; + xu_pc_err_wdt_reset : in std_ulogic_vector(0 to 3); + xu_pc_err_attention_instr : in std_ulogic_vector(0 to 3); + xu_pc_err_debug_event : in std_ulogic_vector(0 to 3); + xu_pc_err_nia_miscmpr : in std_ulogic_vector(0 to 3); + xu_pc_err_invld_reld : in std_ulogic; + xu_pc_err_mchk_disabled : in std_ulogic; + bx_pc_err_inbox_ecc : in std_ulogic; + bx_pc_err_inbox_ue : in std_ulogic; + bx_pc_err_outbox_ecc : in std_ulogic; + bx_pc_err_outbox_ue : in std_ulogic; + fu_pc_err_regfile_parity : in std_ulogic_vector(0 to 3); + fu_pc_err_regfile_ue : in std_ulogic_vector(0 to 3); + pc_iu_inj_icache_parity : out std_ulogic; + pc_iu_inj_icachedir_parity : out std_ulogic; + pc_xu_inj_dcache_parity : out std_ulogic; + pc_xu_inj_dcachedir_parity : out std_ulogic; + pc_xu_inj_sprg_ecc : out std_ulogic_vector(0 to 3); + pc_xu_inj_regfile_parity : out std_ulogic_vector(0 to 3); + pc_fu_inj_regfile_parity : out std_ulogic_vector(0 to 3); + pc_bx_inj_inbox_ecc : out std_ulogic; + pc_bx_inj_outbox_ecc : out std_ulogic; + pc_xu_inj_llbust_attempt : out std_ulogic_vector(0 to 3); + pc_xu_inj_llbust_failed : out std_ulogic_vector(0 to 3); + pc_xu_inj_wdt_reset : out std_ulogic_vector(0 to 3); + pc_iu_inj_icachedir_multihit : out std_ulogic; + pc_xu_inj_dcachedir_multihit : out std_ulogic; + +-- Debug Functions + -- RAM Command/Data + pc_iu_ram_instr : out std_ulogic_vector(0 to 31); + pc_iu_ram_instr_ext : out std_ulogic_vector(0 to 3); + pc_iu_ram_mode : out std_ulogic; + pc_iu_ram_thread : out std_ulogic_vector(0 to 1); + pc_xu_ram_execute : out std_ulogic; + pc_xu_ram_mode : out std_ulogic; + pc_xu_ram_thread : out std_ulogic_vector(0 to 1); + xu_pc_ram_interrupt : in std_ulogic; + xu_pc_ram_done : in std_ulogic; + xu_pc_ram_data : in std_ulogic_vector(64-(2**regmode) to 63); + pc_fu_ram_mode : out std_ulogic; + pc_fu_ram_thread : out std_ulogic_vector(0 to 1); + fu_pc_ram_done : in std_ulogic; + fu_pc_ram_data : in std_ulogic_vector(0 to 63); + pc_xu_msrovride_enab : out std_ulogic; + pc_xu_msrovride_pr : out std_ulogic; + pc_xu_msrovride_gs : out std_ulogic; + pc_xu_msrovride_de : out std_ulogic; + pc_iu_ram_force_cmplt : out std_ulogic; + pc_xu_ram_flush_thread : out std_ulogic; + -- THRCTL + PCCR0 Registers + xu_pc_running : in std_ulogic_vector(0 to 3); + xu_pc_stop_dbg_event : in std_ulogic_vector(0 to 3); + xu_pc_step_done : in std_ulogic_vector(0 to 3); + pc_xu_stop : out std_ulogic_vector(0 to 3); + pc_xu_step : out std_ulogic_vector(0 to 3); + pc_xu_force_ude : out std_ulogic_vector(0 to 3); + pc_xu_extirpts_dis_on_stop : out std_ulogic; + pc_xu_timebase_dis_on_stop : out std_ulogic; + pc_xu_decrem_dis_on_stop : out std_ulogic; + an_ac_debug_stop : in std_ulogic; + pc_xu_dbg_action : out std_ulogic_vector(0 to 11); + +-- Trace/Debug Bus + debug_bus_out : out std_ulogic_vector(0 to 87); + trace_triggers_out : out std_ulogic_vector(0 to 11); + debug_bus_in : in std_ulogic_vector(0 to 87); + trace_triggers_in : in std_ulogic_vector(0 to 11); + --Debug Select Register outputs to units for debug grouping + pc_fu_trace_bus_enable : out std_ulogic; + pc_bx_trace_bus_enable : out std_ulogic; + pc_iu_trace_bus_enable : out std_ulogic; + pc_mm_trace_bus_enable : out std_ulogic; + pc_xu_trace_bus_enable : out std_ulogic; + pc_fu_debug_mux1_ctrls : out std_ulogic_vector(0 to 15); + pc_bx_debug_mux1_ctrls : out std_ulogic_vector(0 to 15); + pc_iu_debug_mux1_ctrls : out std_ulogic_vector(0 to 15); + pc_iu_debug_mux2_ctrls : out std_ulogic_vector(0 to 15); + pc_mm_debug_mux1_ctrls : out std_ulogic_vector(0 to 15); + pc_xu_debug_mux1_ctrls : out std_ulogic_vector(0 to 15); + pc_xu_debug_mux2_ctrls : out std_ulogic_vector(0 to 15); + pc_xu_debug_mux3_ctrls : out std_ulogic_vector(0 to 15); + pc_xu_debug_mux4_ctrls : out std_ulogic_vector(0 to 15); + +-- Perfmon Event Bus + ac_an_event_bus : out std_ulogic_vector(0 to 7); + ac_an_fu_bypass_events : out std_ulogic_vector(0 to 7); + ac_an_iu_bypass_events : out std_ulogic_vector(0 to 7); + ac_an_mm_bypass_events : out std_ulogic_vector(0 to 7); + ac_an_lsu_bypass_events : out std_ulogic_vector(0 to 7); + --Event signals from each unit's Event Mux outputs + fu_pc_event_data : in std_ulogic_vector(0 to 7); + iu_pc_event_data : in std_ulogic_vector(0 to 7); + mm_pc_event_data : in std_ulogic_vector(0 to 7); + xu_pc_event_data : in std_ulogic_vector(0 to 7); + lsu_pc_event_data : in std_ulogic_vector(0 to 7); + ac_pc_trace_to_perfcntr : in std_ulogic_vector(0 to 7); + pc_xu_cache_par_err_event : out std_ulogic; + --Core Event Select Register outputs to units for performance grouping + pc_fu_instr_trace_mode : out std_ulogic; + pc_fu_instr_trace_tid : out std_ulogic_vector(0 to 1); + pc_xu_instr_trace_mode : out std_ulogic; + pc_xu_instr_trace_tid : out std_ulogic_vector(0 to 1); + pc_fu_event_count_mode : out std_ulogic_vector(0 to 2); + pc_iu_event_count_mode : out std_ulogic_vector(0 to 2); + pc_mm_event_count_mode : out std_ulogic_vector(0 to 2); + pc_xu_event_count_mode : out std_ulogic_vector(0 to 2); + pc_fu_event_mux_ctrls : out std_ulogic_vector(0 to 31); + pc_iu_event_mux_ctrls : out std_ulogic_vector(0 to 47); + pc_mm_event_mux_ctrls : out std_ulogic_vector(0 to 39); + pc_xu_event_mux_ctrls : out std_ulogic_vector(0 to 47); + pc_xu_lsu_event_mux_ctrls : out std_ulogic_vector(0 to 47); + pc_fu_event_bus_enable : out std_ulogic; + pc_iu_event_bus_enable : out std_ulogic; + pc_rp_event_bus_enable : out std_ulogic; + pc_xu_event_bus_enable : out std_ulogic; + +-- Reset related + an_ac_reset_1_complete : in std_ulogic; + an_ac_reset_2_complete : in std_ulogic; + an_ac_reset_3_complete : in std_ulogic; + an_ac_reset_wd_complete : in std_ulogic; + pc_xu_reset_1_cmplt : out std_ulogic; + pc_xu_reset_2_cmplt : out std_ulogic; + pc_xu_reset_3_cmplt : out std_ulogic; + pc_xu_reset_wd_cmplt : out std_ulogic; + pc_xu_init_reset : out std_ulogic; + pc_iu_init_reset : out std_ulogic; + +-- Power Management + ac_an_pm_thread_running : out std_ulogic_vector(0 to 3); + an_ac_pm_thread_stop : in std_ulogic_vector(0 to 3); + ac_an_power_managed : out std_ulogic; + ac_an_rvwinkle_mode : out std_ulogic; + xu_pc_spr_ccr0_pme : in std_ulogic_vector(0 to 1); + xu_pc_spr_ccr0_we : in std_ulogic_vector(0 to 3); + +-- Clock, Test, and LCB Controls + an_ac_gsd_test_enable_dc : in std_ulogic; + an_ac_gsd_test_acmode_dc : in std_ulogic; + an_ac_ccflush_dc : in std_ulogic; + an_ac_ccenable_dc : in std_ulogic; + an_ac_lbist_en_dc : in std_ulogic; + an_ac_lbist_ip_dc : in std_ulogic; + an_ac_lbist_ac_mode_dc : in std_ulogic; + an_ac_abist_mode_dc : in std_ulogic; + an_ac_abist_start_test : in std_ulogic; + an_ac_scan_diag_dc : in std_ulogic; + an_ac_scan_dis_dc_b : in std_ulogic; + an_ac_scan_diag_dc_opc : out std_ulogic; + an_ac_scan_dis_dc_b_opc : out std_ulogic; + --Thold input to clock control macro + an_ac_rtim_sl_thold_6 : in std_ulogic; + an_ac_func_sl_thold_6 : in std_ulogic; + an_ac_func_nsl_thold_6 : in std_ulogic; + an_ac_ary_nsl_thold_6 : in std_ulogic; + an_ac_sg_6 : in std_ulogic; + an_ac_fce_6 : in std_ulogic; + an_ac_scan_type_dc : in std_ulogic_vector(0 to 8); + --Thold outputs to the units + pc_xu_ccflush_dc : out std_ulogic; + pc_xu_gptr_sl_thold_3 : out std_ulogic; + pc_xu_time_sl_thold_3 : out std_ulogic; + pc_xu_repr_sl_thold_3 : out std_ulogic; + pc_xu_abst_sl_thold_3 : out std_ulogic; + pc_xu_abst_slp_sl_thold_3 : out std_ulogic; + pc_xu_bolt_sl_thold_3 : out std_ulogic; + pc_xu_regf_sl_thold_3 : out std_ulogic; + pc_xu_regf_slp_sl_thold_3 : out std_ulogic; + pc_xu_func_sl_thold_3 : out std_ulogic_vector(0 to 4); + pc_xu_func_slp_sl_thold_3 : out std_ulogic_vector(0 to 4); + pc_xu_cfg_sl_thold_3 : out std_ulogic; + pc_xu_cfg_slp_sl_thold_3 : out std_ulogic; + pc_xu_func_nsl_thold_3 : out std_ulogic; + pc_xu_func_slp_nsl_thold_3 : out std_ulogic; + pc_xu_ary_nsl_thold_3 : out std_ulogic; + pc_xu_ary_slp_nsl_thold_3 : out std_ulogic; + pc_xu_sg_3 : out std_ulogic_vector(0 to 4); + pc_xu_fce_3 : out std_ulogic_vector(0 to 1); + pc_bx_ccflush_dc : out std_ulogic; + pc_bx_func_sl_thold_3 : out std_ulogic; + pc_bx_func_slp_sl_thold_3 : out std_ulogic; + pc_bx_gptr_sl_thold_3 : out std_ulogic; + pc_bx_time_sl_thold_3 : out std_ulogic; + pc_bx_repr_sl_thold_3 : out std_ulogic; + pc_bx_abst_sl_thold_3 : out std_ulogic; + pc_bx_bolt_sl_thold_3 : out std_ulogic; + pc_bx_ary_nsl_thold_3 : out std_ulogic; + pc_bx_ary_slp_nsl_thold_3 : out std_ulogic; + pc_bx_sg_3 : out std_ulogic; + pc_mm_ccflush_dc : out std_ulogic; + pc_iu_ccflush_dc : out std_ulogic; + pc_iu_gptr_sl_thold_4 : out std_ulogic; + pc_iu_time_sl_thold_4 : out std_ulogic; + pc_iu_repr_sl_thold_4 : out std_ulogic; + pc_iu_abst_sl_thold_4 : out std_ulogic; + pc_iu_abst_slp_sl_thold_4 : out std_ulogic; + pc_iu_bolt_sl_thold_4 : out std_ulogic; + pc_iu_regf_slp_sl_thold_4 : out std_ulogic; + pc_iu_func_sl_thold_4 : out std_ulogic; + pc_iu_func_slp_sl_thold_4 : out std_ulogic; + pc_iu_cfg_sl_thold_4 : out std_ulogic; + pc_iu_cfg_slp_sl_thold_4 : out std_ulogic; + pc_iu_func_nsl_thold_4 : out std_ulogic; + pc_iu_func_slp_nsl_thold_4 : out std_ulogic; + pc_iu_ary_nsl_thold_4 : out std_ulogic; + pc_iu_ary_slp_nsl_thold_4 : out std_ulogic; + pc_iu_sg_4 : out std_ulogic; + pc_iu_fce_4 : out std_ulogic; + pc_fu_ccflush_dc : out std_ulogic; + pc_fu_gptr_sl_thold_3 : out std_ulogic; + pc_fu_time_sl_thold_3 : out std_ulogic; + pc_fu_repr_sl_thold_3 : out std_ulogic; + pc_fu_abst_sl_thold_3 : out std_ulogic; + pc_fu_abst_slp_sl_thold_3 : out std_ulogic; + pc_fu_bolt_sl_thold_3 : out std_ulogic; + pc_fu_func_sl_thold_3 : out std_ulogic_vector(0 to 1); + pc_fu_func_slp_sl_thold_3 : out std_ulogic_vector(0 to 1); + pc_fu_cfg_sl_thold_3 : out std_ulogic; + pc_fu_cfg_slp_sl_thold_3 : out std_ulogic; + pc_fu_func_nsl_thold_3 : out std_ulogic; + pc_fu_func_slp_nsl_thold_3 : out std_ulogic; + pc_fu_ary_nsl_thold_3 : out std_ulogic; + pc_fu_ary_slp_nsl_thold_3 : out std_ulogic; + pc_fu_sg_3 : out std_ulogic_vector(0 to 1); + pc_fu_fce_3 : out std_ulogic; + +-- PSRO Sensors + an_ac_psro_enable_dc : in std_ulogic_vector(0 to 2); + ac_an_psro_ringsig : out std_ulogic; + +-- ABIST Engine + ac_an_abist_done_dc : out std_ulogic; + -- BX ABIST Outputs + pc_bx_abist_di_0 : Out std_ulogic_vector(0 to 3); + pc_bx_abist_ena_dc : Out std_ulogic; + pc_bx_abist_g8t1p_renb_0 : Out std_ulogic; + pc_bx_abist_g8t_bw_0 : Out std_ulogic; + pc_bx_abist_g8t_bw_1 : Out std_ulogic; + pc_bx_abist_g8t_dcomp : Out std_ulogic_vector(0 to 3); + pc_bx_abist_g8t_wenb : Out std_ulogic; + pc_bx_abist_raddr_0 : Out std_ulogic_vector(0 to 9); + pc_bx_abist_raw_dc_b : Out std_ulogic; + pc_bx_abist_waddr_0 : Out std_ulogic_vector(0 to 9); + pc_bx_abist_wl64_g8t_comp_ena : Out std_ulogic; + -- FU ABIST Outputs + pc_fu_abist_di_0 : Out std_ulogic_vector(0 to 3); + pc_fu_abist_di_1 : Out std_ulogic_vector(0 to 3); + pc_fu_abist_ena_dc : Out std_ulogic; + pc_fu_abist_grf_renb_0 : Out std_ulogic; + pc_fu_abist_grf_renb_1 : Out std_ulogic; + pc_fu_abist_grf_wenb_0 : Out std_ulogic; + pc_fu_abist_grf_wenb_1 : Out std_ulogic; + pc_fu_abist_raddr_0 : Out std_ulogic_vector(0 to 9); + pc_fu_abist_raddr_1 : Out std_ulogic_vector(0 to 9); + pc_fu_abist_raw_dc_b : Out std_ulogic; + pc_fu_abist_waddr_0 : Out std_ulogic_vector(0 to 9); + pc_fu_abist_waddr_1 : Out std_ulogic_vector(0 to 9); + pc_fu_abist_wl144_comp_ena : Out std_ulogic; + -- IU ABIST Outputs + pc_iu_abist_dcomp_g6t_2r : Out std_ulogic_vector(0 to 3); + pc_iu_abist_di_0 : Out std_ulogic_vector(0 to 3); + pc_iu_abist_di_g6t_2r : Out std_ulogic_vector(0 to 3); + pc_iu_abist_ena_dc : Out std_ulogic; + pc_iu_abist_g6t_bw : Out std_ulogic_vector(0 to 1); + pc_iu_abist_g6t_r_wb : Out std_ulogic; + pc_iu_abist_g8t1p_renb_0 : Out std_ulogic; + pc_iu_abist_g8t_bw_0 : Out std_ulogic; + pc_iu_abist_g8t_bw_1 : Out std_ulogic; + pc_iu_abist_g8t_dcomp : Out std_ulogic_vector(0 to 3); + pc_iu_abist_g8t_wenb : Out std_ulogic; + pc_iu_abist_raddr_0 : Out std_ulogic_vector(0 to 9); + pc_iu_abist_raw_dc_b : Out std_ulogic; + pc_iu_abist_waddr_0 : Out std_ulogic_vector(0 to 9); + pc_iu_abist_wl128_g8t_comp_ena : Out std_ulogic; + pc_iu_abist_wl256_comp_ena : Out std_ulogic; + pc_iu_abist_wl64_g8t_comp_ena : Out std_ulogic; + -- MMU ABIST Outputs + pc_mm_abist_dcomp_g6t_2r : Out std_ulogic_vector(0 to 3); + pc_mm_abist_di_0 : Out std_ulogic_vector(0 to 3); + pc_mm_abist_di_g6t_2r : Out std_ulogic_vector(0 to 3); + pc_mm_abist_ena_dc : Out std_ulogic; + pc_mm_abist_g6t_r_wb : Out std_ulogic; + pc_mm_abist_g8t1p_renb_0 : Out std_ulogic; + pc_mm_abist_g8t_bw_0 : Out std_ulogic; + pc_mm_abist_g8t_bw_1 : Out std_ulogic; + pc_mm_abist_g8t_dcomp : Out std_ulogic_vector(0 to 3); + pc_mm_abist_g8t_wenb : Out std_ulogic; + pc_mm_abist_raddr_0 : Out std_ulogic_vector(0 to 9); + pc_mm_abist_raw_dc_b : Out std_ulogic; + pc_mm_abist_waddr_0 : Out std_ulogic_vector(0 to 9); + pc_mm_abist_wl128_g8t_comp_ena : Out std_ulogic; + -- XU ABIST Outputs + pc_xu_abist_dcomp_g6t_2r : Out std_ulogic_vector(0 to 3); + pc_xu_abist_di_0 : Out std_ulogic_vector(0 to 3); + pc_xu_abist_di_1 : Out std_ulogic_vector(0 to 3); + pc_xu_abist_di_g6t_2r : Out std_ulogic_vector(0 to 3); + pc_xu_abist_ena_dc : Out std_ulogic; + pc_xu_abist_g6t_bw : Out std_ulogic_vector(0 to 1); + pc_xu_abist_g6t_r_wb : Out std_ulogic; + pc_xu_abist_g8t1p_renb_0 : Out std_ulogic; + pc_xu_abist_g8t_bw_0 : Out std_ulogic; + pc_xu_abist_g8t_bw_1 : Out std_ulogic; + pc_xu_abist_g8t_dcomp : Out std_ulogic_vector(0 to 3); + pc_xu_abist_g8t_wenb : Out std_ulogic; + pc_xu_abist_grf_renb_0 : Out std_ulogic; + pc_xu_abist_grf_renb_1 : Out std_ulogic; + pc_xu_abist_grf_wenb_0 : Out std_ulogic; + pc_xu_abist_grf_wenb_1 : Out std_ulogic; + pc_xu_abist_raddr_0 : Out std_ulogic_vector(0 to 9); + pc_xu_abist_raddr_1 : Out std_ulogic_vector(0 to 9); + pc_xu_abist_raw_dc_b : Out std_ulogic; + pc_xu_abist_waddr_0 : Out std_ulogic_vector(0 to 9); + pc_xu_abist_waddr_1 : Out std_ulogic_vector(0 to 9); + pc_xu_abist_wl144_comp_ena : Out std_ulogic; + pc_xu_abist_wl32_g8t_comp_ena : Out std_ulogic; + pc_xu_abist_wl512_comp_ena : Out std_ulogic; + +-- Bolt-On ABIST + -- Bolt-On interface + an_ac_bo_enable : in std_ulogic; + an_ac_bo_go : in std_ulogic; + an_ac_bo_cntlclk : in std_ulogic; + an_ac_bo_ccflush : in std_ulogic; + an_ac_bo_reset : in std_ulogic; + an_ac_bo_data : in std_ulogic; + an_ac_bo_shcntl : in std_ulogic; + an_ac_bo_shdata : in std_ulogic; + an_ac_bo_sysrepair : in std_ulogic; + an_ac_bo_exe : in std_ulogic; + an_ac_bo_donein : in std_ulogic; + an_ac_bo_sdin : in std_ulogic; + an_ac_bo_waitin : in std_ulogic; + an_ac_bo_failin : in std_ulogic; + an_ac_bo_fcshdata : in std_ulogic; + an_ac_bo_fcreset : in std_ulogic; + ac_an_bo_doneout : out std_ulogic; + ac_an_bo_sdout : out std_ulogic; + ac_an_bo_diagloopout : out std_ulogic; + ac_an_bo_waitout : out std_ulogic; + ac_an_bo_failout : out std_ulogic; + -- Bolt-On back ends + pc_bx_bo_enable_3 : out std_ulogic; + pc_bx_bo_unload : out std_ulogic; + pc_bx_bo_repair : out std_ulogic; + pc_bx_bo_reset : out std_ulogic; + pc_bx_bo_shdata : out std_ulogic; + pc_bx_bo_select : out std_ulogic_vector(0 to 3); + bx_pc_bo_fail : in std_ulogic_vector(0 to 3); + bx_pc_bo_diagout : in std_ulogic_vector(0 to 3); + pc_fu_bo_enable_3 : out std_ulogic; + pc_fu_bo_unload : out std_ulogic; + pc_fu_bo_load : out std_ulogic; + pc_fu_bo_reset : out std_ulogic; + pc_fu_bo_shdata : out std_ulogic; + pc_fu_bo_select : out std_ulogic_vector(0 to 1); + fu_pc_bo_fail : in std_ulogic_vector(0 to 1); + fu_pc_bo_diagout : in std_ulogic_vector(0 to 1); + pc_iu_bo_enable_4 : out std_ulogic; + pc_iu_bo_unload : out std_ulogic; + pc_iu_bo_repair : out std_ulogic; + pc_iu_bo_reset : out std_ulogic; + pc_iu_bo_shdata : out std_ulogic; + pc_iu_bo_select : out std_ulogic_vector(0 to 4); + iu_pc_bo_fail : in std_ulogic_vector(0 to 4); + iu_pc_bo_diagout : in std_ulogic_vector(0 to 4); + pc_mm_bo_enable_4 : out std_ulogic; + pc_mm_bo_unload : out std_ulogic; + pc_mm_bo_repair : out std_ulogic; + pc_mm_bo_reset : out std_ulogic; + pc_mm_bo_shdata : out std_ulogic; + pc_mm_bo_select : out std_ulogic_vector(0 to 4); + mm_pc_bo_fail : in std_ulogic_vector(0 to 4); + mm_pc_bo_diagout : in std_ulogic_vector(0 to 4); + pc_xu_bo_enable_3 : out std_ulogic; + pc_xu_bo_unload : out std_ulogic; + pc_xu_bo_load : out std_ulogic; + pc_xu_bo_repair : out std_ulogic; + pc_xu_bo_reset : out std_ulogic; + pc_xu_bo_shdata : out std_ulogic; + pc_xu_bo_select : out std_ulogic_vector(0 to 8); + xu_pc_bo_fail : in std_ulogic_vector(0 to 8); + xu_pc_bo_diagout : in std_ulogic_vector(0 to 8); + +-- Scanning + gptr_scan_in : in std_ulogic; + ccfg_scan_in : in std_ulogic; + bcfg_scan_in : in std_ulogic; + dcfg_scan_in : in std_ulogic; + abst_scan_in : in std_ulogic; + func_scan_in : in std_ulogic_vector(0 to 1); + gptr_scan_out : out std_ulogic; + ccfg_scan_out : out std_ulogic; + bcfg_scan_out : out std_ulogic; + dcfg_scan_out : out std_ulogic; + abst_scan_out : out std_ulogic; + func_scan_out : out std_ulogic_vector(0 to 1) +); +-- synopsys translate_off + + + + +-- synopsys translate_on +end pcq; + +architecture pcq of pcq is +----------------------------------------------------------------------- +-- Basic/Misc Signals +signal ct_db_func_scan_out : std_ulogic; +signal db_ss_func_scan_out : std_ulogic; +signal lcbctrl_gptr_scan_out : std_ulogic; +-- Misc Controls +signal ct_rg_power_managed : std_ulogic_vector(0 to 3); +signal ct_ck_pm_raise_tholds : std_ulogic; +signal ct_ck_pm_ccflush_disable : std_ulogic; +signal ct_rg_pm_thread_stop : std_ulogic_vector(0 to 3); +signal rg_ct_dis_pwr_savings : std_ulogic; +signal rg_ck_fast_xstop : std_ulogic; +signal sp_db_event_mux_ctrls : std_ulogic_vector(0 to 23); +signal sp_db_event_bus_enable : std_ulogic; +signal ct_rg_hold_during_init : std_ulogic; +-- Clock Controls +signal d_mode_dc : std_ulogic; +signal clkoff_dc_b : std_ulogic; +signal act_dis_dc : std_ulogic; +signal delay_lclkr_dc : std_ulogic_vector(0 to 4); +signal mpw1_dc_b : std_ulogic_vector(0 to 4); +signal mpw2_dc_b : std_ulogic; +signal pc_pc_ccflush_dc : std_ulogic; +signal pc_pc_gptr_sl_thold_0 : std_ulogic; +signal pc_pc_abst_sl_thold_0 : std_ulogic; +signal pc_pc_func_sl_thold_0 : std_ulogic; +signal pc_pc_func_slp_sl_thold_0 : std_ulogic; +signal pc_pc_cfg_sl_thold_0 : std_ulogic; +signal pc_pc_cfg_slp_sl_thold_0 : std_ulogic; +signal pc_pc_sg_0 : std_ulogic; +-- Trace/Trigger signals +signal sp_rg_trace_bus_enable : std_ulogic; +signal rg_db_trace_bus_enable : std_ulogic; +signal rg_db_debug_mux_ctrls : std_ulogic_vector(0 to 15); +signal ck_db_dbg_clks_ctrls : std_ulogic_vector(0 to 13); +signal rg_db_dbg_scom_rdata : std_ulogic_vector(0 to 63); +signal rg_db_dbg_scom_wdata : std_ulogic_vector(0 to 63); +signal rg_db_dbg_scom_decaddr : std_ulogic_vector(0 to 63); +signal rg_db_dbg_scom_misc : std_ulogic_vector(0 to 8); +signal rg_db_dbg_ram_thrctl : std_ulogic_vector(0 to 20); +signal rg_db_dbg_fir0_err : std_ulogic_vector(0 to 31); +signal rg_db_dbg_fir1_err : std_ulogic_vector(0 to 30); +signal rg_db_dbg_fir2_err : std_ulogic_vector(0 to 21); +signal rg_db_dbg_fir_misc : std_ulogic_vector(0 to 35); +signal ct_db_dbg_ctrls : std_ulogic_vector(0 to 36); +signal rg_db_dbg_spr : std_ulogic_vector(0 to 46); +-- Bolt-On ABIST signals +signal pc_bo_unload_out : std_ulogic; +signal pc_bo_load_out : std_ulogic; +signal pc_bo_repair_out : std_ulogic; +signal pc_bo_reset_out : std_ulogic; +signal pc_bo_shdata_out : std_ulogic; +signal pc_bo_select_out : std_ulogic_vector(0 to 39); +signal pc_bo_fail_in : std_ulogic_vector(0 to 39); +signal pc_bo_diagout_in : std_ulogic_vector(0 to 39); +signal abist_done_int : std_ulogic; +signal abst_eng_si : std_ulogic; +signal abst_scan_out_int : std_ulogic; +signal an_ac_abist_start_test_int : std_ulogic; +signal an_ac_abist_mode_dc_int : std_ulogic; +signal bo_pc_abst_sl_thold_6 : std_ulogic; +signal bo_pc_pc_abst_sl_thold_6 : std_ulogic; +signal bo_pc_ary_nsl_thold_6 : std_ulogic; +signal bo_pc_func_sl_thold_6 : std_ulogic; +signal bo_pc_time_sl_thold_6 : std_ulogic; +signal bo_pc_repr_sl_thold_6 : std_ulogic; +signal bo_pc_sg_6 : std_ulogic; +signal pc_pc_bo_go_0 : std_ulogic; +signal pc_pc_bo_enable_0 : std_ulogic; +signal pc_pc_bo_cntlclk_0 : std_ulogic; +signal pc_pc_bo_reset_0 : std_ulogic; +signal pc_pc_bo_fcshdata_0 : std_ulogic; +signal pc_pc_bo_fcreset_0 : std_ulogic; +signal pc_pc_bolt_sl_thold_6 : std_ulogic; +signal pc_pc_bolt_sl_thold_0 : std_ulogic; +-- Unused Signals +signal unused_signals : std_ulogic; + +-- --------------------------------- +-- Special Buffering for PSRO Sensor +signal pcq_psro_ringsig_out : std_ulogic; +signal pcq_psro_ringsig_i : std_ulogic; + + + + + +begin + +unused_signals <= or_reduce(pc_bo_select_out(25 TO 39)); + +-- Outputs +an_ac_scan_diag_dc_opc <= an_ac_scan_diag_dc; +an_ac_scan_dis_dc_b_opc <= an_ac_scan_dis_dc_b; +ac_an_abist_done_dc <= abist_done_int; + + + +pcq_regs : entity work.pcq_regs +generic map(expand_type => expand_type, + regmode => regmode ) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + scan_dis_dc_b => an_ac_scan_dis_dc_b, + lcb_clkoff_dc_b => clkoff_dc_b, + lcb_d_mode_dc => d_mode_dc, + lcb_mpw1_dc_b => mpw1_dc_b(0), + lcb_mpw2_dc_b => mpw2_dc_b, + lcb_delay_lclkr_dc => delay_lclkr_dc(0), + lcb_act_dis_dc => act_dis_dc, + lcb_func_slp_sl_thold_0 => pc_pc_func_slp_sl_thold_0, + lcb_cfg_sl_thold_0 => pc_pc_cfg_sl_thold_0, + lcb_cfg_slp_sl_thold_0 => pc_pc_cfg_slp_sl_thold_0, + lcb_sg_0 => pc_pc_sg_0, + ccfg_scan_in => ccfg_scan_in, + bcfg_scan_in => bcfg_scan_in, + dcfg_scan_in => dcfg_scan_in, + func_scan_in => func_scan_in(0), + ccfg_scan_out => ccfg_scan_out, + bcfg_scan_out => bcfg_scan_out, + dcfg_scan_out => dcfg_scan_out, + func_scan_out => func_scan_out(0), + -- SCOM Satellite interface + an_ac_scom_sat_id => an_ac_scom_sat_id, + an_ac_scom_dch => an_ac_scom_dch, + an_ac_scom_cch => an_ac_scom_cch, + ac_an_scom_dch => ac_an_scom_dch, + ac_an_scom_cch => ac_an_scom_cch, + -- Error Related + ac_an_special_attn => ac_an_special_attn, + ac_an_checkstop => ac_an_checkstop, + ac_an_local_checkstop => ac_an_local_checkstop, + ac_an_recov_err => ac_an_recov_err, + ac_an_trace_error => ac_an_trace_error, + an_ac_checkstop => an_ac_checkstop, + an_ac_malf_alert => an_ac_malf_alert, + rg_ck_fast_xstop => rg_ck_fast_xstop, + iu_pc_err_icache_parity => iu_pc_err_icache_parity, + iu_pc_err_icachedir_parity => iu_pc_err_icachedir_parity, + iu_pc_err_icachedir_multihit => iu_pc_err_icachedir_multihit, + iu_pc_err_ucode_illegal => iu_pc_err_ucode_illegal, + xu_pc_err_dcache_parity => xu_pc_err_dcache_parity, + xu_pc_err_dcachedir_parity => xu_pc_err_dcachedir_parity, + xu_pc_err_dcachedir_multihit => xu_pc_err_dcachedir_multihit, + xu_pc_err_mcsr_summary => xu_pc_err_mcsr_summary, + xu_pc_err_ierat_parity => xu_pc_err_ierat_parity, + xu_pc_err_derat_parity => xu_pc_err_derat_parity, + xu_pc_err_tlb_parity => xu_pc_err_tlb_parity, + xu_pc_err_tlb_lru_parity => xu_pc_err_tlb_lru_parity, + xu_pc_err_ierat_multihit => xu_pc_err_ierat_multihit, + xu_pc_err_derat_multihit => xu_pc_err_derat_multihit, + xu_pc_err_tlb_multihit => xu_pc_err_tlb_multihit, + xu_pc_err_ext_mchk => xu_pc_err_ext_mchk, + xu_pc_err_ditc_overrun => xu_pc_err_ditc_overrun, + xu_pc_err_local_snoop_reject => xu_pc_err_local_snoop_reject, + xu_pc_err_sprg_ecc => xu_pc_err_sprg_ecc, + xu_pc_err_sprg_ue => xu_pc_err_sprg_ue, + xu_pc_err_regfile_parity => xu_pc_err_regfile_parity, + xu_pc_err_regfile_ue => xu_pc_err_regfile_ue, + xu_pc_err_llbust_attempt => xu_pc_err_llbust_attempt, + xu_pc_err_llbust_failed => xu_pc_err_llbust_failed, + xu_pc_err_l2intrf_ecc => xu_pc_err_l2intrf_ecc, + xu_pc_err_l2intrf_ue => xu_pc_err_l2intrf_ue, + xu_pc_err_l2credit_overrun => xu_pc_err_l2credit_overrun, + xu_pc_err_wdt_reset => xu_pc_err_wdt_reset, + xu_pc_err_attention_instr => xu_pc_err_attention_instr, + xu_pc_err_debug_event => xu_pc_err_debug_event, + xu_pc_err_nia_miscmpr => xu_pc_err_nia_miscmpr, + xu_pc_err_invld_reld => xu_pc_err_invld_reld, + xu_pc_err_mchk_disabled => xu_pc_err_mchk_disabled, + bx_pc_err_inbox_ecc => bx_pc_err_inbox_ecc, + bx_pc_err_inbox_ue => bx_pc_err_inbox_ue, + bx_pc_err_outbox_ecc => bx_pc_err_outbox_ecc, + bx_pc_err_outbox_ue => bx_pc_err_outbox_ue, + fu_pc_err_regfile_parity => fu_pc_err_regfile_parity, + fu_pc_err_regfile_ue => fu_pc_err_regfile_ue, + pc_iu_inj_icache_parity => pc_iu_inj_icache_parity, + pc_iu_inj_icachedir_parity => pc_iu_inj_icachedir_parity, + pc_xu_inj_dcache_parity => pc_xu_inj_dcache_parity, + pc_xu_inj_dcachedir_parity => pc_xu_inj_dcachedir_parity, + pc_xu_inj_sprg_ecc => pc_xu_inj_sprg_ecc, + pc_xu_inj_regfile_parity => pc_xu_inj_regfile_parity, + pc_fu_inj_regfile_parity => pc_fu_inj_regfile_parity, + pc_bx_inj_inbox_ecc => pc_bx_inj_inbox_ecc, + pc_bx_inj_outbox_ecc => pc_bx_inj_outbox_ecc, + pc_xu_inj_llbust_attempt => pc_xu_inj_llbust_attempt, + pc_xu_inj_llbust_failed => pc_xu_inj_llbust_failed, + pc_xu_inj_wdt_reset => pc_xu_inj_wdt_reset, + pc_iu_inj_icachedir_multihit => pc_iu_inj_icachedir_multihit, + pc_xu_inj_dcachedir_multihit => pc_xu_inj_dcachedir_multihit, + pc_xu_cache_par_err_event => pc_xu_cache_par_err_event, + -- RAMC/RAMD + pc_iu_ram_instr => pc_iu_ram_instr, + pc_iu_ram_instr_ext => pc_iu_ram_instr_ext, + pc_iu_ram_mode => pc_iu_ram_mode, + pc_iu_ram_thread => pc_iu_ram_thread, + pc_xu_ram_execute => pc_xu_ram_execute, + pc_xu_ram_mode => pc_xu_ram_mode, + pc_xu_ram_thread => pc_xu_ram_thread, + xu_pc_ram_interrupt => xu_pc_ram_interrupt, + xu_pc_ram_done => xu_pc_ram_done, + xu_pc_ram_data => xu_pc_ram_data, + pc_fu_ram_mode => pc_fu_ram_mode, + pc_fu_ram_thread => pc_fu_ram_thread, + fu_pc_ram_done => fu_pc_ram_done, + fu_pc_ram_data => fu_pc_ram_data, + pc_xu_msrovride_enab => pc_xu_msrovride_enab, + pc_xu_msrovride_pr => pc_xu_msrovride_pr, + pc_xu_msrovride_gs => pc_xu_msrovride_gs, + pc_xu_msrovride_de => pc_xu_msrovride_de, + pc_iu_ram_force_cmplt => pc_iu_ram_force_cmplt, + pc_xu_ram_flush_thread => pc_xu_ram_flush_thread, + -- THRCTL + PCCR0 Registers + xu_pc_running => xu_pc_running, + xu_pc_stop_dbg_event => xu_pc_stop_dbg_event, + xu_pc_step_done => xu_pc_step_done, + pc_xu_stop => pc_xu_stop, + pc_xu_step => pc_xu_step, + pc_xu_force_ude => pc_xu_force_ude, + ct_rg_power_managed => ct_rg_power_managed, + ct_rg_pm_thread_stop => ct_rg_pm_thread_stop, + ac_an_pm_thread_running => ac_an_pm_thread_running, + pc_xu_extirpts_dis_on_stop => pc_xu_extirpts_dis_on_stop, + pc_xu_timebase_dis_on_stop => pc_xu_timebase_dis_on_stop, + pc_xu_decrem_dis_on_stop => pc_xu_decrem_dis_on_stop, + ct_rg_hold_during_init => ct_rg_hold_during_init, + an_ac_debug_stop => an_ac_debug_stop, + pc_xu_dbg_action => pc_xu_dbg_action, + rg_ct_dis_pwr_savings => rg_ct_dis_pwr_savings, + -- Debug Registers + sp_rg_trace_bus_enable => sp_rg_trace_bus_enable, + rg_db_trace_bus_enable => rg_db_trace_bus_enable, + pc_fu_trace_bus_enable => pc_fu_trace_bus_enable, + pc_bx_trace_bus_enable => pc_bx_trace_bus_enable, + pc_iu_trace_bus_enable => pc_iu_trace_bus_enable, + pc_mm_trace_bus_enable => pc_mm_trace_bus_enable, + pc_xu_trace_bus_enable => pc_xu_trace_bus_enable, + rg_db_debug_mux_ctrls => rg_db_debug_mux_ctrls, + pc_fu_debug_mux1_ctrls => pc_fu_debug_mux1_ctrls, + pc_bx_debug_mux1_ctrls => pc_bx_debug_mux1_ctrls, + pc_iu_debug_mux1_ctrls => pc_iu_debug_mux1_ctrls, + pc_iu_debug_mux2_ctrls => pc_iu_debug_mux2_ctrls, + pc_mm_debug_mux1_ctrls => pc_mm_debug_mux1_ctrls, + pc_xu_debug_mux1_ctrls => pc_xu_debug_mux1_ctrls, + pc_xu_debug_mux2_ctrls => pc_xu_debug_mux2_ctrls, + pc_xu_debug_mux3_ctrls => pc_xu_debug_mux3_ctrls, + pc_xu_debug_mux4_ctrls => pc_xu_debug_mux4_ctrls, + -- Trace/Trigger Signals + dbg_scom_rdata => rg_db_dbg_scom_rdata, + dbg_scom_wdata => rg_db_dbg_scom_wdata, + dbg_scom_decaddr => rg_db_dbg_scom_decaddr, + dbg_scom_misc => rg_db_dbg_scom_misc, + dbg_ram_thrctl => rg_db_dbg_ram_thrctl, + dbg_fir0_err => rg_db_dbg_fir0_err, + dbg_fir1_err => rg_db_dbg_fir1_err, + dbg_fir2_err => rg_db_dbg_fir2_err, + dbg_fir_misc => rg_db_dbg_fir_misc +); + + +pcq_ctrl : entity work.pcq_ctrl +generic map(expand_type => expand_type) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + scan_dis_dc_b => an_ac_scan_dis_dc_b, + lcb_clkoff_dc_b => clkoff_dc_b, + lcb_mpw1_dc_b => mpw1_dc_b(1), + lcb_mpw2_dc_b => mpw2_dc_b, + lcb_delay_lclkr_dc => delay_lclkr_dc(1), + lcb_act_dis_dc => act_dis_dc, + pc_pc_func_slp_sl_thold_0 => pc_pc_func_slp_sl_thold_0, + pc_pc_sg_0 => pc_pc_sg_0, + func_scan_in => func_scan_in(1), + func_scan_out => ct_db_func_scan_out, + --Stop/Start/Reset + an_ac_reset_1_complete => an_ac_reset_1_complete, + an_ac_reset_2_complete => an_ac_reset_2_complete, + an_ac_reset_3_complete => an_ac_reset_3_complete, + an_ac_reset_wd_complete => an_ac_reset_wd_complete, + pc_xu_reset_1_cmplt => pc_xu_reset_1_cmplt, + pc_xu_reset_2_cmplt => pc_xu_reset_2_cmplt, + pc_xu_reset_3_cmplt => pc_xu_reset_3_cmplt, + pc_xu_reset_wd_cmplt => pc_xu_reset_wd_cmplt, + pc_xu_init_reset => pc_xu_init_reset, + pc_iu_init_reset => pc_iu_init_reset, + ct_rg_hold_during_init => ct_rg_hold_during_init, + --Power Management + ct_rg_power_managed => ct_rg_power_managed, + ct_rg_pm_thread_stop => ct_rg_pm_thread_stop, + an_ac_pm_thread_stop => an_ac_pm_thread_stop, + ac_an_power_managed => ac_an_power_managed, + ac_an_rvwinkle_mode => ac_an_rvwinkle_mode, + ct_ck_pm_ccflush_disable => ct_ck_pm_ccflush_disable, + ct_ck_pm_raise_tholds => ct_ck_pm_raise_tholds, + rg_ct_dis_pwr_savings => rg_ct_dis_pwr_savings, + xu_pc_spr_ccr0_pme => xu_pc_spr_ccr0_pme, + xu_pc_spr_ccr0_we => xu_pc_spr_ccr0_we, + --Trace/Trigger Signals + dbg_ctrls => ct_db_dbg_ctrls +); + + +pcq_dbg : entity work.pcq_dbg +generic map(expand_type => expand_type) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + scan_dis_dc_b => an_ac_scan_dis_dc_b, + lcb_clkoff_dc_b => clkoff_dc_b, + lcb_mpw1_dc_b => mpw1_dc_b(2), + lcb_mpw2_dc_b => mpw2_dc_b, + lcb_delay_lclkr_dc => delay_lclkr_dc(2), + lcb_act_dis_dc => act_dis_dc, + pc_pc_func_slp_sl_thold_0 => pc_pc_func_slp_sl_thold_0, + pc_pc_sg_0 => pc_pc_sg_0, + func_scan_in => ct_db_func_scan_out, + func_scan_out => db_ss_func_scan_out, + --Trace/Trigger Bus + debug_bus_out => debug_bus_out, + trace_triggers_out => trace_triggers_out, + debug_bus_in => debug_bus_in, + trace_triggers_in => trace_triggers_in, + rg_db_trace_bus_enable => rg_db_trace_bus_enable, + rg_db_debug_mux_ctrls => rg_db_debug_mux_ctrls, + --PC Unit internal debug signals + ck_db_dbg_clks_ctrls => ck_db_dbg_clks_ctrls, + rg_db_dbg_scom_rdata => rg_db_dbg_scom_rdata, + rg_db_dbg_scom_wdata => rg_db_dbg_scom_wdata, + rg_db_dbg_scom_decaddr => rg_db_dbg_scom_decaddr, + rg_db_dbg_scom_misc => rg_db_dbg_scom_misc, + rg_db_dbg_ram_thrctl => rg_db_dbg_ram_thrctl, + rg_db_dbg_fir0_err => rg_db_dbg_fir0_err, + rg_db_dbg_fir1_err => rg_db_dbg_fir1_err, + rg_db_dbg_fir2_err => rg_db_dbg_fir2_err, + rg_db_dbg_fir_misc => rg_db_dbg_fir_misc, + ct_db_dbg_ctrls => ct_db_dbg_ctrls, + rg_db_dbg_spr => rg_db_dbg_spr, + --Event Bus + ac_an_event_bus => ac_an_event_bus, + ac_an_fu_bypass_events => ac_an_fu_bypass_events, + ac_an_iu_bypass_events => ac_an_iu_bypass_events, + ac_an_mm_bypass_events => ac_an_mm_bypass_events, + ac_an_lsu_bypass_events => ac_an_lsu_bypass_events, + rg_db_event_bus_enable => sp_db_event_bus_enable, + rg_db_event_mux_ctrls => sp_db_event_mux_ctrls, + fu_pc_event_data => fu_pc_event_data, + iu_pc_event_data => iu_pc_event_data, + mm_pc_event_data => mm_pc_event_data, + xu_pc_event_data => xu_pc_event_data, + lsu_pc_event_data => lsu_pc_event_data, + ac_pc_trace_to_perfcntr => ac_pc_trace_to_perfcntr +); + + +pcq_spr : entity work.pcq_spr +generic map(expand_type => expand_type, + regmode => regmode ) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + scan_dis_dc_b => an_ac_scan_dis_dc_b, + lcb_clkoff_dc_b => clkoff_dc_b, + lcb_mpw1_dc_b => mpw1_dc_b(0), + lcb_mpw2_dc_b => mpw2_dc_b, + lcb_delay_lclkr_dc => delay_lclkr_dc(0), + lcb_act_dis_dc => act_dis_dc, + pc_pc_func_sl_thold_0 => pc_pc_func_sl_thold_0, + pc_pc_sg_0 => pc_pc_sg_0, + func_scan_in => db_ss_func_scan_out, + func_scan_out => func_scan_out(1), + -- slowSPR Interface + slowspr_val_in => slowspr_val_in, + slowspr_rw_in => slowspr_rw_in, + slowspr_etid_in => slowspr_etid_in, + slowspr_addr_in => slowspr_addr_in, + slowspr_data_in => slowspr_data_in(64-(2**regmode) to 63), + slowspr_done_in => slowspr_done_in, + + slowspr_val_out => slowspr_val_out, + slowspr_rw_out => slowspr_rw_out, + slowspr_etid_out => slowspr_etid_out, + slowspr_addr_out => slowspr_addr_out, + slowspr_data_out => slowspr_data_out(64-(2**regmode) to 63), + slowspr_done_out => slowspr_done_out, + -- register outputs + sp_rg_trace_bus_enable => sp_rg_trace_bus_enable, + pc_fu_instr_trace_mode => pc_fu_instr_trace_mode, + pc_fu_instr_trace_tid => pc_fu_instr_trace_tid, + pc_xu_instr_trace_mode => pc_xu_instr_trace_mode, + pc_xu_instr_trace_tid => pc_xu_instr_trace_tid, + pc_fu_event_count_mode => pc_fu_event_count_mode, + pc_iu_event_count_mode => pc_iu_event_count_mode, + pc_mm_event_count_mode => pc_mm_event_count_mode, + pc_xu_event_count_mode => pc_xu_event_count_mode, + pc_fu_event_mux_ctrls => pc_fu_event_mux_ctrls, + pc_iu_event_mux_ctrls => pc_iu_event_mux_ctrls, + pc_mm_event_mux_ctrls => pc_mm_event_mux_ctrls, + pc_xu_event_mux_ctrls => pc_xu_event_mux_ctrls, + pc_xu_lsu_event_mux_ctrls => pc_xu_lsu_event_mux_ctrls, + sp_db_event_mux_ctrls => sp_db_event_mux_ctrls, + pc_fu_event_bus_enable => pc_fu_event_bus_enable, + pc_iu_event_bus_enable => pc_iu_event_bus_enable, + pc_rp_event_bus_enable => pc_rp_event_bus_enable, + pc_xu_event_bus_enable => pc_xu_event_bus_enable, + sp_db_event_bus_enable => sp_db_event_bus_enable, + dbg_spr => rg_db_dbg_spr +); + + +pcq_clks : entity work.pcq_clks +generic map(expand_type => expand_type) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + rtim_sl_thold_6 => an_ac_rtim_sl_thold_6, + func_sl_thold_6 => an_ac_func_sl_thold_6, + func_nsl_thold_6 => an_ac_func_nsl_thold_6, + ary_nsl_thold_6 => an_ac_ary_nsl_thold_6, + sg_6 => an_ac_sg_6, + fce_6 => an_ac_fce_6, + gsd_test_enable_dc => an_ac_gsd_test_enable_dc, + gsd_test_acmode_dc => an_ac_gsd_test_acmode_dc, + ccflush_dc => an_ac_ccflush_dc, + ccenable_dc => an_ac_ccenable_dc, + scan_type_dc => an_ac_scan_type_dc, + lbist_en_dc => an_ac_lbist_en_dc, + lbist_ip_dc => an_ac_lbist_ip_dc, + rg_ck_fast_xstop => rg_ck_fast_xstop, + ct_ck_pm_ccflush_disable => ct_ck_pm_ccflush_disable, + ct_ck_pm_raise_tholds => ct_ck_pm_raise_tholds, +-- Thold + control from bolton frontend + bolton_enable_dc => an_ac_bo_enable, + bolton_enable_sync => pc_pc_bo_enable_0, + bolton_ccflush => an_ac_bo_ccflush, + bc_cntlclk_sync => pc_pc_bo_cntlclk_0, + bolton_fcshdata => pc_pc_bo_fcshdata_0, + bolton_fcreset => pc_pc_bo_fcreset_0, + bo_pc_abst_sl_thold_6 => bo_pc_abst_sl_thold_6, + bo_pc_pc_abst_sl_thold_6 => bo_pc_pc_abst_sl_thold_6, + bo_pc_ary_nsl_thold_6 => bo_pc_ary_nsl_thold_6, + bo_pc_func_sl_thold_6 => bo_pc_func_sl_thold_6, + bo_pc_time_sl_thold_6 => bo_pc_time_sl_thold_6, + bo_pc_repr_sl_thold_6 => bo_pc_repr_sl_thold_6, + bo_pc_sg_6 => bo_pc_sg_6, +-- --Thold outputs to the units + pc_xu_ccflush_dc => pc_xu_ccflush_dc, + pc_xu_gptr_sl_thold_3 => pc_xu_gptr_sl_thold_3, + pc_xu_time_sl_thold_3 => pc_xu_time_sl_thold_3, + pc_xu_repr_sl_thold_3 => pc_xu_repr_sl_thold_3, + pc_xu_abst_sl_thold_3 => pc_xu_abst_sl_thold_3, + pc_xu_abst_slp_sl_thold_3 => pc_xu_abst_slp_sl_thold_3, + pc_xu_bolt_sl_thold_3 => pc_xu_bolt_sl_thold_3, + pc_xu_regf_sl_thold_3 => pc_xu_regf_sl_thold_3, + pc_xu_regf_slp_sl_thold_3 => pc_xu_regf_slp_sl_thold_3, + pc_xu_func_sl_thold_3 => pc_xu_func_sl_thold_3, + pc_xu_func_slp_sl_thold_3 => pc_xu_func_slp_sl_thold_3, + pc_xu_cfg_sl_thold_3 => pc_xu_cfg_sl_thold_3, + pc_xu_cfg_slp_sl_thold_3 => pc_xu_cfg_slp_sl_thold_3, + pc_xu_func_nsl_thold_3 => pc_xu_func_nsl_thold_3, + pc_xu_func_slp_nsl_thold_3 => pc_xu_func_slp_nsl_thold_3, + pc_xu_ary_nsl_thold_3 => pc_xu_ary_nsl_thold_3, + pc_xu_ary_slp_nsl_thold_3 => pc_xu_ary_slp_nsl_thold_3, + pc_xu_sg_3 => pc_xu_sg_3, + pc_xu_fce_3 => pc_xu_fce_3, + pc_bx_ccflush_dc => pc_bx_ccflush_dc, + pc_bx_func_sl_thold_3 => pc_bx_func_sl_thold_3, + pc_bx_func_slp_sl_thold_3 => pc_bx_func_slp_sl_thold_3, + pc_bx_gptr_sl_thold_3 => pc_bx_gptr_sl_thold_3, + pc_bx_time_sl_thold_3 => pc_bx_time_sl_thold_3, + pc_bx_repr_sl_thold_3 => pc_bx_repr_sl_thold_3, + pc_bx_abst_sl_thold_3 => pc_bx_abst_sl_thold_3, + pc_bx_bolt_sl_thold_3 => pc_bx_bolt_sl_thold_3, + pc_bx_ary_nsl_thold_3 => pc_bx_ary_nsl_thold_3, + pc_bx_ary_slp_nsl_thold_3 => pc_bx_ary_slp_nsl_thold_3, + pc_bx_sg_3 => pc_bx_sg_3, + pc_mm_ccflush_dc => pc_mm_ccflush_dc, + pc_iu_ccflush_dc => pc_iu_ccflush_dc, + pc_iu_gptr_sl_thold_4 => pc_iu_gptr_sl_thold_4, + pc_iu_time_sl_thold_4 => pc_iu_time_sl_thold_4, + pc_iu_repr_sl_thold_4 => pc_iu_repr_sl_thold_4, + pc_iu_abst_sl_thold_4 => pc_iu_abst_sl_thold_4, + pc_iu_abst_slp_sl_thold_4 => pc_iu_abst_slp_sl_thold_4, + pc_iu_bolt_sl_thold_4 => pc_iu_bolt_sl_thold_4, + pc_iu_regf_slp_sl_thold_4 => pc_iu_regf_slp_sl_thold_4, + pc_iu_func_sl_thold_4 => pc_iu_func_sl_thold_4, + pc_iu_func_slp_sl_thold_4 => pc_iu_func_slp_sl_thold_4, + pc_iu_cfg_sl_thold_4 => pc_iu_cfg_sl_thold_4, + pc_iu_cfg_slp_sl_thold_4 => pc_iu_cfg_slp_sl_thold_4, + pc_iu_func_nsl_thold_4 => pc_iu_func_nsl_thold_4, + pc_iu_func_slp_nsl_thold_4 => pc_iu_func_slp_nsl_thold_4, + pc_iu_ary_nsl_thold_4 => pc_iu_ary_nsl_thold_4, + pc_iu_ary_slp_nsl_thold_4 => pc_iu_ary_slp_nsl_thold_4, + pc_iu_sg_4 => pc_iu_sg_4, + pc_iu_fce_4 => pc_iu_fce_4, + pc_fu_ccflush_dc => pc_fu_ccflush_dc, + pc_fu_gptr_sl_thold_3 => pc_fu_gptr_sl_thold_3, + pc_fu_time_sl_thold_3 => pc_fu_time_sl_thold_3, + pc_fu_repr_sl_thold_3 => pc_fu_repr_sl_thold_3, + pc_fu_abst_sl_thold_3 => pc_fu_abst_sl_thold_3, + pc_fu_abst_slp_sl_thold_3 => pc_fu_abst_slp_sl_thold_3, + pc_fu_bolt_sl_thold_3 => pc_fu_bolt_sl_thold_3, + pc_fu_func_sl_thold_3 => pc_fu_func_sl_thold_3, + pc_fu_func_slp_sl_thold_3 => pc_fu_func_slp_sl_thold_3, + pc_fu_cfg_sl_thold_3 => pc_fu_cfg_sl_thold_3, + pc_fu_cfg_slp_sl_thold_3 => pc_fu_cfg_slp_sl_thold_3, + pc_fu_func_nsl_thold_3 => pc_fu_func_nsl_thold_3, + pc_fu_func_slp_nsl_thold_3 => pc_fu_func_slp_nsl_thold_3, + pc_fu_ary_nsl_thold_3 => pc_fu_ary_nsl_thold_3, + pc_fu_ary_slp_nsl_thold_3 => pc_fu_ary_slp_nsl_thold_3, + pc_fu_sg_3 => pc_fu_sg_3, + pc_fu_fce_3 => pc_fu_fce_3, + pc_pc_ccflush_dc => pc_pc_ccflush_dc, + pc_pc_gptr_sl_thold_0 => pc_pc_gptr_sl_thold_0, + pc_pc_abst_sl_thold_0 => pc_pc_abst_sl_thold_0, + pc_pc_bolt_sl_thold_6 => pc_pc_bolt_sl_thold_6, + pc_pc_bolt_sl_thold_0 => pc_pc_bolt_sl_thold_0, + pc_pc_func_sl_thold_0 => pc_pc_func_sl_thold_0, + pc_pc_func_slp_sl_thold_0 => pc_pc_func_slp_sl_thold_0, + pc_pc_cfg_sl_thold_0 => pc_pc_cfg_sl_thold_0, + pc_pc_cfg_slp_sl_thold_0 => pc_pc_cfg_slp_sl_thold_0, + pc_pc_sg_0 => pc_pc_sg_0, + dbg_clks_ctrls => ck_db_dbg_clks_ctrls +); + + + +--===================================================================== +-- ABIST and Bolt-On ABIST Function +--===================================================================== +pcq_abist : entity work.pcq_abist +generic map(expand_type => expand_type) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + scan_dis_dc_b => an_ac_scan_dis_dc_b, + lcb_clkoff_dc_b => clkoff_dc_b, + lcb_mpw1_dc_b => mpw1_dc_b(3), + lcb_mpw2_dc_b => mpw2_dc_b, + lcb_delay_lclkr_dc => delay_lclkr_dc(3), + lcb_delay_lclkr_np_dc => delay_lclkr_dc(4), + lcb_act_dis_dc => act_dis_dc, + lcb_d_mode_dc => d_mode_dc, + gptr_thold => pc_pc_gptr_sl_thold_0, + gptr_scan_in => lcbctrl_gptr_scan_out, + gptr_scan_out => gptr_scan_out, + abist_thold => pc_pc_abst_sl_thold_0, + abist_sg => pc_pc_sg_0, + abist_scan_in => abst_scan_in, + abist_scan_out => abst_scan_out_int, + -- Bolton ABIST Engine access + bo_enable => pc_pc_bo_enable_0, + bo_abist_eng_si => abst_eng_si, + -- LBIST + ABIST Engine Controls + abist_done_in_dc => '1', + abist_done_out_dc => abist_done_int, + abist_mode_dc => an_ac_abist_mode_dc_int, + abist_start_test => an_ac_abist_start_test_int, + lbist_mode_dc => an_ac_lbist_en_dc, + lbist_ac_mode_dc => an_ac_lbist_ac_mode_dc, + -- BX ABIST Outputs + pc_bx_abist_di_0 => pc_bx_abist_di_0(0 to 3), + pc_bx_abist_ena_dc => pc_bx_abist_ena_dc, + pc_bx_abist_g8t1p_renb_0 => pc_bx_abist_g8t1p_renb_0, + pc_bx_abist_g8t_bw_0 => pc_bx_abist_g8t_bw_0, + pc_bx_abist_g8t_bw_1 => pc_bx_abist_g8t_bw_1, + pc_bx_abist_g8t_dcomp => pc_bx_abist_g8t_dcomp(0 to 3), + pc_bx_abist_g8t_wenb => pc_bx_abist_g8t_wenb, + pc_bx_abist_raddr_0 => pc_bx_abist_raddr_0(0 to 9), + pc_bx_abist_raw_dc_b => pc_bx_abist_raw_dc_b, + pc_bx_abist_waddr_0 => pc_bx_abist_waddr_0(0 to 9), + pc_bx_abist_wl64_g8t_comp_ena => pc_bx_abist_wl64_g8t_comp_ena, + -- FU ABIST Outputs + pc_fu_abist_di_0 => pc_fu_abist_di_0(0 to 3), + pc_fu_abist_di_1 => pc_fu_abist_di_1(0 to 3), + pc_fu_abist_ena_dc => pc_fu_abist_ena_dc, + pc_fu_abist_grf_renb_0 => pc_fu_abist_grf_renb_0, + pc_fu_abist_grf_renb_1 => pc_fu_abist_grf_renb_1, + pc_fu_abist_grf_wenb_0 => pc_fu_abist_grf_wenb_0, + pc_fu_abist_grf_wenb_1 => pc_fu_abist_grf_wenb_1, + pc_fu_abist_raddr_0 => pc_fu_abist_raddr_0(0 to 9), + pc_fu_abist_raddr_1 => pc_fu_abist_raddr_1(0 to 9), + pc_fu_abist_raw_dc_b => pc_fu_abist_raw_dc_b, + pc_fu_abist_waddr_0 => pc_fu_abist_waddr_0(0 to 9), + pc_fu_abist_waddr_1 => pc_fu_abist_waddr_1(0 to 9), + pc_fu_abist_wl144_comp_ena => pc_fu_abist_wl144_comp_ena, + -- IU ABIST Outputs + pc_iu_abist_dcomp_g6t_2r => pc_iu_abist_dcomp_g6t_2r(0 to 3), + pc_iu_abist_di_0 => pc_iu_abist_di_0(0 to 3), + pc_iu_abist_di_g6t_2r => pc_iu_abist_di_g6t_2r(0 to 3), + pc_iu_abist_ena_dc => pc_iu_abist_ena_dc, + pc_iu_abist_g6t_bw => pc_iu_abist_g6t_bw(0 to 1), + pc_iu_abist_g6t_r_wb => pc_iu_abist_g6t_r_wb, + pc_iu_abist_g8t1p_renb_0 => pc_iu_abist_g8t1p_renb_0, + pc_iu_abist_g8t_bw_0 => pc_iu_abist_g8t_bw_0, + pc_iu_abist_g8t_bw_1 => pc_iu_abist_g8t_bw_1, + pc_iu_abist_g8t_dcomp => pc_iu_abist_g8t_dcomp(0 to 3), + pc_iu_abist_g8t_wenb => pc_iu_abist_g8t_wenb, + pc_iu_abist_raddr_0 => pc_iu_abist_raddr_0(0 to 9), + pc_iu_abist_raw_dc_b => pc_iu_abist_raw_dc_b, + pc_iu_abist_waddr_0 => pc_iu_abist_waddr_0(0 to 9), + pc_iu_abist_wl128_g8t_comp_ena => pc_iu_abist_wl128_g8t_comp_ena, + pc_iu_abist_wl256_comp_ena => pc_iu_abist_wl256_comp_ena, + pc_iu_abist_wl64_g8t_comp_ena => pc_iu_abist_wl64_g8t_comp_ena, + -- MMU ABIST Outputs + pc_mm_abist_dcomp_g6t_2r => pc_mm_abist_dcomp_g6t_2r(0 to 3), + pc_mm_abist_di_0 => pc_mm_abist_di_0(0 to 3), + pc_mm_abist_di_g6t_2r => pc_mm_abist_di_g6t_2r(0 to 3), + pc_mm_abist_ena_dc => pc_mm_abist_ena_dc, + pc_mm_abist_g6t_r_wb => pc_mm_abist_g6t_r_wb, + pc_mm_abist_g8t1p_renb_0 => pc_mm_abist_g8t1p_renb_0, + pc_mm_abist_g8t_bw_0 => pc_mm_abist_g8t_bw_0, + pc_mm_abist_g8t_bw_1 => pc_mm_abist_g8t_bw_1, + pc_mm_abist_g8t_dcomp => pc_mm_abist_g8t_dcomp(0 to 3), + pc_mm_abist_g8t_wenb => pc_mm_abist_g8t_wenb, + pc_mm_abist_raddr_0 => pc_mm_abist_raddr_0(0 to 9), + pc_mm_abist_raw_dc_b => pc_mm_abist_raw_dc_b, + pc_mm_abist_waddr_0 => pc_mm_abist_waddr_0(0 to 9), + pc_mm_abist_wl128_g8t_comp_ena => pc_mm_abist_wl128_g8t_comp_ena, + -- XU ABIST Outputs + pc_xu_abist_dcomp_g6t_2r => pc_xu_abist_dcomp_g6t_2r(0 to 3), + pc_xu_abist_di_0 => pc_xu_abist_di_0(0 to 3), + pc_xu_abist_di_1 => pc_xu_abist_di_1(0 to 3), + pc_xu_abist_di_g6t_2r => pc_xu_abist_di_g6t_2r(0 to 3), + pc_xu_abist_ena_dc => pc_xu_abist_ena_dc, + pc_xu_abist_g6t_bw => pc_xu_abist_g6t_bw(0 to 1), + pc_xu_abist_g6t_r_wb => pc_xu_abist_g6t_r_wb, + pc_xu_abist_g8t1p_renb_0 => pc_xu_abist_g8t1p_renb_0, + pc_xu_abist_g8t_bw_0 => pc_xu_abist_g8t_bw_0, + pc_xu_abist_g8t_bw_1 => pc_xu_abist_g8t_bw_1, + pc_xu_abist_g8t_dcomp => pc_xu_abist_g8t_dcomp(0 to 3), + pc_xu_abist_g8t_wenb => pc_xu_abist_g8t_wenb, + pc_xu_abist_grf_renb_0 => pc_xu_abist_grf_renb_0, + pc_xu_abist_grf_renb_1 => pc_xu_abist_grf_renb_1, + pc_xu_abist_grf_wenb_0 => pc_xu_abist_grf_wenb_0, + pc_xu_abist_grf_wenb_1 => pc_xu_abist_grf_wenb_1, + pc_xu_abist_raddr_0 => pc_xu_abist_raddr_0(0 to 9), + pc_xu_abist_raddr_1 => pc_xu_abist_raddr_1(0 to 9), + pc_xu_abist_raw_dc_b => pc_xu_abist_raw_dc_b, + pc_xu_abist_waddr_0 => pc_xu_abist_waddr_0(0 to 9), + pc_xu_abist_waddr_1 => pc_xu_abist_waddr_1(0 to 9), + pc_xu_abist_wl144_comp_ena => pc_xu_abist_wl144_comp_ena, + pc_xu_abist_wl32_g8t_comp_ena => pc_xu_abist_wl32_g8t_comp_ena, + pc_xu_abist_wl512_comp_ena => pc_xu_abist_wl512_comp_ena +); + + +pcq_bolton : entity work.pcq_abist_bolton_frontend +generic map ( expand_type => expand_type, + num_backends => 40 ) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, +-- BISTCNTL interface + bcreset => pc_pc_bo_reset_0, + bcdata => an_ac_bo_data, + bcshcntl => an_ac_bo_shcntl, + bcshdata => an_ac_bo_shdata, + bcexe => an_ac_bo_exe, + bcsysrepair => an_ac_bo_sysrepair, + bo_enable => pc_pc_bo_enable_0, + bo_go => pc_pc_bo_go_0, +-- daisy chain + donein => an_ac_bo_donein, + sdin => an_ac_bo_sdin, + doneout => ac_an_bo_doneout, + sdout => ac_an_bo_sdout, + diagloop_out => ac_an_bo_diagloopout, + waitin => an_ac_bo_waitin, + failin => an_ac_bo_failin, + waitout => ac_an_bo_waitout, + failout => ac_an_bo_failout, +-- abist engine + abist_done => abist_done_int, + abist_si => abst_eng_si, + abist_start_test_int => an_ac_abist_start_test_int, + abist_start_test => an_ac_abist_start_test, + abist_mode_dc => an_ac_abist_mode_dc, + abist_mode_dc_int => an_ac_abist_mode_dc_int, +-- back ends + bo_unload => pc_bo_unload_out, + bo_load => pc_bo_load_out, + bo_repair => pc_bo_repair_out, + bo_reset => pc_bo_reset_out, + bo_shdata => pc_bo_shdata_out, + bo_select => pc_bo_select_out, + bo_fail => pc_bo_fail_in, + bo_diagout => pc_bo_diagout_in, +-- thold / scan + lbist_ac_mode_dc => an_ac_lbist_ac_mode_dc, + ck_bo_sl_thold_6 => pc_pc_bolt_sl_thold_6, + ck_bo_sl_thold_0 => pc_pc_bolt_sl_thold_0, + ck_bo_sg_0 => pc_pc_sg_0, + lcb_clkoff_dc_b => clkoff_dc_b, + lcb_mpw1_dc_b => mpw1_dc_b(4), + lcb_mpw2_dc_b => mpw2_dc_b, + lcb_delay_lclkr_dc => delay_lclkr_dc(4), + lcb_act_dis_dc => act_dis_dc, + scan_in => abst_scan_out_int, + scan_out => abst_scan_out, +-- thold / sg outputs + bo_pc_abst_sl_thold_6 => bo_pc_abst_sl_thold_6, + bo_pc_pc_abst_sl_thold_6 => bo_pc_pc_abst_sl_thold_6, + bo_pc_ary_nsl_thold_6 => bo_pc_ary_nsl_thold_6, + bo_pc_func_sl_thold_6 => bo_pc_func_sl_thold_6, + bo_pc_time_sl_thold_6 => bo_pc_time_sl_thold_6, + bo_pc_repr_sl_thold_6 => bo_pc_repr_sl_thold_6, + bo_pc_sg_6 => bo_pc_sg_6 +); + + +pcq_bolton_stg : entity work.pcq_abist_bolton_stg +generic map( expand_type => expand_type) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_pc_ccflush_dc => pc_pc_ccflush_dc, + + pu_pc_bo_enable => an_ac_bo_enable, + pu_pc_bo_go => an_ac_bo_go, + pu_pc_bo_cntlclk => an_ac_bo_cntlclk, + pu_pc_bo_reset => an_ac_bo_reset, + pu_pc_bo_fcshdata => an_ac_bo_fcshdata, + pu_pc_bo_fcreset => an_ac_bo_fcreset, + + pc_bx_bo_enable_3 => pc_bx_bo_enable_3, + pc_fu_bo_enable_3 => pc_fu_bo_enable_3, + pc_iu_bo_enable_4 => pc_iu_bo_enable_4, + pc_mm_bo_enable_4 => pc_mm_bo_enable_4, + pc_xu_bo_enable_3 => pc_xu_bo_enable_3, + pc_pc_bo_go_0 => pc_pc_bo_go_0, + pc_pc_bo_enable_0 => pc_pc_bo_enable_0, + pc_pc_bo_cntlclk_0 => pc_pc_bo_cntlclk_0, + pc_pc_bo_reset_0 => pc_pc_bo_reset_0, + pc_pc_bo_fcshdata_0 => pc_pc_bo_fcshdata_0, + pc_pc_bo_fcreset_0 => pc_pc_bo_fcreset_0 +); + + +-- Split up the bolt-on back end signals into individual unit interfaces: +pc_bx_bo_unload <= pc_bo_unload_out; +pc_fu_bo_unload <= pc_bo_unload_out; +pc_iu_bo_unload <= pc_bo_unload_out; +pc_mm_bo_unload <= pc_bo_unload_out; +pc_xu_bo_unload <= pc_bo_unload_out; + +pc_fu_bo_load <= pc_bo_load_out; +pc_xu_bo_load <= pc_bo_load_out; + +pc_bx_bo_repair <= pc_bo_repair_out; +pc_iu_bo_repair <= pc_bo_repair_out; +pc_mm_bo_repair <= pc_bo_repair_out; +pc_xu_bo_repair <= pc_bo_repair_out; + +pc_bx_bo_reset <= pc_bo_reset_out; +pc_fu_bo_reset <= pc_bo_reset_out; +pc_iu_bo_reset <= pc_bo_reset_out; +pc_mm_bo_reset <= pc_bo_reset_out; +pc_xu_bo_reset <= pc_bo_reset_out; + +pc_bx_bo_shdata <= pc_bo_shdata_out; +pc_fu_bo_shdata <= pc_bo_shdata_out; +pc_iu_bo_shdata <= pc_bo_shdata_out; +pc_mm_bo_shdata <= pc_bo_shdata_out; +pc_xu_bo_shdata <= pc_bo_shdata_out; + +pc_bx_bo_select(0 to 3) <= pc_bo_select_out(0 to 3); +pc_fu_bo_select(0 to 1) <= pc_bo_select_out(4 to 5); +pc_iu_bo_select(0 to 4) <= pc_bo_select_out(6 to 10); +pc_mm_bo_select(0 to 4) <= pc_bo_select_out(11 to 15); +pc_xu_bo_select(0 to 8) <= pc_bo_select_out(16 to 24); + +pc_bo_fail_in(0 to 39) <= bx_pc_bo_fail(0 to 3) & fu_pc_bo_fail(0 to 1) & + iu_pc_bo_fail(0 to 4) & mm_pc_bo_fail(0 to 4) & + xu_pc_bo_fail(0 to 8) & x"000" & "000"; + +pc_bo_diagout_in(0 to 39) <= bx_pc_bo_diagout(0 to 3) & fu_pc_bo_diagout(0 to 1) & + iu_pc_bo_diagout(0 to 4) & mm_pc_bo_diagout(0 to 4) & + xu_pc_bo_diagout(0 to 8) & x"000" & "000" ; + + +--===================================================================== +-- PSRO Sensor +--===================================================================== +pcq_psro : entity work.pcq_psro_soft +port map( + vdd => vdd, + gnd => gnd, + pcq_psro_enable => an_ac_psro_enable_dc(0 to 2), + psro_pcq_ringsig => pcq_psro_ringsig_out +); + +u_pcq_psro_rsig_i: pcq_psro_ringsig_i <= not( pcq_psro_ringsig_out ); +u_pcq_psro_rsig_ii: ac_an_psro_ringsig <= not( pcq_psro_ringsig_i ); + + +--===================================================================== +-- LCBCNTL Macro +--===================================================================== +lcbctrl : entity tri.tri_lcbcntl_mac + generic map( expand_type => expand_type ) + port map( + vdd => vdd, + gnd => gnd, + sg => pc_pc_sg_0, + nclk => nclk, + scan_in => gptr_scan_in, + scan_diag_dc => an_ac_scan_diag_dc, + thold => pc_pc_gptr_sl_thold_0, + clkoff_dc_b => clkoff_dc_b, + delay_lclkr_dc => delay_lclkr_dc(0 to 4), + act_dis_dc => open, + d_mode_dc => d_mode_dc, + mpw1_dc_b => mpw1_dc_b(0 to 4), + mpw2_dc_b => mpw2_dc_b, + scan_out => lcbctrl_gptr_scan_out + ); + +-- Forcing act_dis pin on all tri_lcbor components to 0. +-- Using logic signal connected to LCB ACT pin to control if latch held or updated. + act_dis_dc <= '0'; + + +----------------------------------------------------------------------- +end pcq; diff --git a/rel/src/vhdl/work/pcq_abist.vhdl b/rel/src/vhdl/work/pcq_abist.vhdl new file mode 100644 index 0000000..f940943 --- /dev/null +++ b/rel/src/vhdl/work/pcq_abist.vhdl @@ -0,0 +1,625 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- +-- Description: A2 Core ABIST Engine +-- +--***************************************************************************** + +library ieee, ibm; +use ieee.std_logic_1164.all; +use ibm.std_ulogic_support.all; +library support; +USE support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity pcq_abist is +generic(expand_type : integer := 2 ); -- 0=ibm (Umbra), 1=non-ibm, 2=ibm (CDP) +Port (vdd : INOUT power_logic; + gnd : INOUT power_logic; + nclk : In clk_logic; + scan_dis_dc_b : In std_ulogic; + lcb_clkoff_dc_b : In std_ulogic; + lcb_mpw1_dc_b : In std_ulogic; + lcb_mpw2_dc_b : In std_ulogic; + lcb_delay_lclkr_dc : In std_ulogic; + lcb_delay_lclkr_np_dc : In std_ulogic; + lcb_act_dis_dc : In std_ulogic; + lcb_d_mode_dc : In std_ulogic; + gptr_thold : In std_ulogic; + gptr_scan_in : In std_ulogic; + gptr_scan_out : Out std_ulogic; + abist_thold : In std_ulogic; + abist_sg : In std_ulogic; + abist_scan_in : In std_ulogic; + abist_scan_out : Out std_ulogic; + -- Bolton ABIST Engine access + bo_enable : in std_ulogic; + bo_abist_eng_si : in std_ulogic; + -- LBIST + ABIST Engine Controls + abist_done_in_dc : In std_ulogic; + abist_done_out_dc : Out std_ulogic; + abist_mode_dc : In std_ulogic; + abist_start_test : In std_ulogic; + lbist_mode_dc : In std_ulogic; + lbist_ac_mode_dc : In std_ulogic; + -- BX ABIST Outputs + pc_bx_abist_di_0 : Out std_ulogic_vector(0 to 3); + pc_bx_abist_ena_dc : Out std_ulogic; + pc_bx_abist_g8t1p_renb_0 : Out std_ulogic; + pc_bx_abist_g8t_bw_0 : Out std_ulogic; + pc_bx_abist_g8t_bw_1 : Out std_ulogic; + pc_bx_abist_g8t_dcomp : Out std_ulogic_vector(0 to 3); + pc_bx_abist_g8t_wenb : Out std_ulogic; + pc_bx_abist_raddr_0 : Out std_ulogic_vector(0 to 9); + pc_bx_abist_raw_dc_b : Out std_ulogic; + pc_bx_abist_waddr_0 : Out std_ulogic_vector(0 to 9); + pc_bx_abist_wl64_g8t_comp_ena : Out std_ulogic; + -- FU ABIST Outputs + pc_fu_abist_di_0 : Out std_ulogic_vector(0 to 3); + pc_fu_abist_di_1 : Out std_ulogic_vector(0 to 3); + pc_fu_abist_ena_dc : Out std_ulogic; + pc_fu_abist_grf_renb_0 : Out std_ulogic; + pc_fu_abist_grf_renb_1 : Out std_ulogic; + pc_fu_abist_grf_wenb_0 : Out std_ulogic; + pc_fu_abist_grf_wenb_1 : Out std_ulogic; + pc_fu_abist_raddr_0 : Out std_ulogic_vector(0 to 9); + pc_fu_abist_raddr_1 : Out std_ulogic_vector(0 to 9); + pc_fu_abist_raw_dc_b : Out std_ulogic; + pc_fu_abist_waddr_0 : Out std_ulogic_vector(0 to 9); + pc_fu_abist_waddr_1 : Out std_ulogic_vector(0 to 9); + pc_fu_abist_wl144_comp_ena : Out std_ulogic; + -- IU ABIST Outputs + pc_iu_abist_dcomp_g6t_2r : Out std_ulogic_vector(0 to 3); + pc_iu_abist_di_0 : Out std_ulogic_vector(0 to 3); + pc_iu_abist_di_g6t_2r : Out std_ulogic_vector(0 to 3); + pc_iu_abist_ena_dc : Out std_ulogic; + pc_iu_abist_g6t_bw : Out std_ulogic_vector(0 to 1); + pc_iu_abist_g6t_r_wb : Out std_ulogic; + pc_iu_abist_g8t1p_renb_0 : Out std_ulogic; + pc_iu_abist_g8t_bw_0 : Out std_ulogic; + pc_iu_abist_g8t_bw_1 : Out std_ulogic; + pc_iu_abist_g8t_dcomp : Out std_ulogic_vector(0 to 3); + pc_iu_abist_g8t_wenb : Out std_ulogic; + pc_iu_abist_raddr_0 : Out std_ulogic_vector(0 to 9); + pc_iu_abist_raw_dc_b : Out std_ulogic; + pc_iu_abist_waddr_0 : Out std_ulogic_vector(0 to 9); + pc_iu_abist_wl128_g8t_comp_ena : Out std_ulogic; + pc_iu_abist_wl256_comp_ena : Out std_ulogic; + pc_iu_abist_wl64_g8t_comp_ena : Out std_ulogic; + -- MMU ABIST Outputs + pc_mm_abist_dcomp_g6t_2r : Out std_ulogic_vector(0 to 3); + pc_mm_abist_di_0 : Out std_ulogic_vector(0 to 3); + pc_mm_abist_di_g6t_2r : Out std_ulogic_vector(0 to 3); + pc_mm_abist_ena_dc : Out std_ulogic; + pc_mm_abist_g6t_r_wb : Out std_ulogic; + pc_mm_abist_g8t1p_renb_0 : Out std_ulogic; + pc_mm_abist_g8t_bw_0 : Out std_ulogic; + pc_mm_abist_g8t_bw_1 : Out std_ulogic; + pc_mm_abist_g8t_dcomp : Out std_ulogic_vector(0 to 3); + pc_mm_abist_g8t_wenb : Out std_ulogic; + pc_mm_abist_raddr_0 : Out std_ulogic_vector(0 to 9); + pc_mm_abist_raw_dc_b : Out std_ulogic; + pc_mm_abist_waddr_0 : Out std_ulogic_vector(0 to 9); + pc_mm_abist_wl128_g8t_comp_ena : Out std_ulogic; + -- XU ABIST Outputs + pc_xu_abist_dcomp_g6t_2r : Out std_ulogic_vector(0 to 3); + pc_xu_abist_di_0 : Out std_ulogic_vector(0 to 3); + pc_xu_abist_di_1 : Out std_ulogic_vector(0 to 3); + pc_xu_abist_di_g6t_2r : Out std_ulogic_vector(0 to 3); + pc_xu_abist_ena_dc : Out std_ulogic; + pc_xu_abist_g6t_bw : Out std_ulogic_vector(0 to 1); + pc_xu_abist_g6t_r_wb : Out std_ulogic; + pc_xu_abist_g8t1p_renb_0 : Out std_ulogic; + pc_xu_abist_g8t_bw_0 : Out std_ulogic; + pc_xu_abist_g8t_bw_1 : Out std_ulogic; + pc_xu_abist_g8t_dcomp : Out std_ulogic_vector(0 to 3); + pc_xu_abist_g8t_wenb : Out std_ulogic; + pc_xu_abist_grf_renb_0 : Out std_ulogic; + pc_xu_abist_grf_renb_1 : Out std_ulogic; + pc_xu_abist_grf_wenb_0 : Out std_ulogic; + pc_xu_abist_grf_wenb_1 : Out std_ulogic; + pc_xu_abist_raddr_0 : Out std_ulogic_vector(0 to 9); + pc_xu_abist_raddr_1 : Out std_ulogic_vector(0 to 9); + pc_xu_abist_raw_dc_b : Out std_ulogic; + pc_xu_abist_waddr_0 : Out std_ulogic_vector(0 to 9); + pc_xu_abist_waddr_1 : Out std_ulogic_vector(0 to 9); + pc_xu_abist_wl144_comp_ena : Out std_ulogic; + pc_xu_abist_wl32_g8t_comp_ena : Out std_ulogic; + pc_xu_abist_wl512_comp_ena : Out std_ulogic +); + +-- synopsys translate_off + + + + +-- synopsys translate_on +end pcq_abist; + +architecture pcq_abist of pcq_abist is + +--===================================================================== +-- Signal Declarations +--===================================================================== + +-- Scan Ring Ordering: +----------------------------------------------------------------------- +constant staging1_size : positive := 1; +constant staging2_size : positive := 73; +constant staging3_size : positive := 42; +constant staging4_size : positive := 44; +-- start of abst scan chain ordering +constant staging1_offset : natural := 0; +constant staging2_offset : natural := staging1_offset + staging1_size; +constant staging3_offset : natural := staging2_offset + staging2_size; +constant staging4_offset : natural := staging3_offset + staging3_size; +constant abst_right : natural := staging4_offset + staging4_size - 1; +-- end of abst scan chain ordering + +-- Miscellaneous +signal abist_start_test_q : std_ulogic; +signal force_abist : std_ulogic; +signal abist_thold_b : std_ulogic; +signal abist_engine_so : std_ulogic; +signal abst_siv, abst_sov : std_ulogic_vector(0 to abst_right); + +-- ABIST Engine Array Connections +signal abist_raddr_0 : std_ulogic_vector(0 to 9); +signal abist_raddr_1 : std_ulogic_vector(0 to 9); +signal abist_grf_renb_0 : std_ulogic; +signal abist_grf_renb_1 : std_ulogic; +signal abist_g8t1p_renb_0 : std_ulogic; +signal abist_waddr_0 : std_ulogic_vector(0 to 9); +signal abist_waddr_1 : std_ulogic_vector(0 to 9); +signal abist_grf_wenb_0 : std_ulogic; +signal abist_grf_wenb_1 : std_ulogic; +signal abist_g8t_wenb : std_ulogic; +signal abist_di_0 : std_ulogic_vector(0 to 3); +signal abist_di_1 : std_ulogic_vector(0 to 3); +signal abist_di_g6t_2r : std_ulogic_vector(0 to 3); +signal abist_g6t_r_wb : std_ulogic; +signal abist_dcomp : std_ulogic_vector(0 to 3); +signal abist_dcomp_g6t_2r : std_ulogic_vector(0 to 3); +signal abist_wl32_g8t_comp_ena : std_ulogic; +signal abist_wl64_g8t_comp_ena : std_ulogic; +signal abist_wl128_g8t_comp_ena : std_ulogic; +signal abist_wl144_comp_ena : std_ulogic; +signal abist_wl256_comp_ena : std_ulogic; +signal abist_wl512_comp_ena : std_ulogic; +signal abist_bw_0 : std_ulogic; +signal abist_bw_1 : std_ulogic; + +-- ABIST Engine Staging Latches +signal abist_raddr_0_q : std_ulogic_vector(0 to 9); +signal abist_raddr_1_q : std_ulogic_vector(0 to 9); +signal abist_grf_renb_0_q : std_ulogic; +signal abist_grf_renb_1_q : std_ulogic; +signal abist_g8t1p_renb_0_q : std_ulogic; +signal abist_waddr_0_q : std_ulogic_vector(0 to 9); +signal abist_waddr_1_q : std_ulogic_vector(0 to 9); +signal abist_grf_wenb_0_q : std_ulogic; +signal abist_grf_wenb_1_q : std_ulogic; +signal abist_g8t_wenb_q : std_ulogic; +signal abist_di_0_q : std_ulogic_vector(0 to 3); +signal abist_di_1_q : std_ulogic_vector(0 to 3); +signal abist_di_g6t_2r_q : std_ulogic_vector(0 to 3); +signal abist_g6t_r_wb_q : std_ulogic; +signal abist_dcomp_q : std_ulogic_vector(0 to 3); +signal abist_dcomp_g6t_2r_q : std_ulogic_vector(0 to 3); +signal abist_wl32_g8t_comp_ena_q : std_ulogic; +signal abist_wl64_g8t_comp_ena_q : std_ulogic; +signal abist_wl144_comp_ena_q : std_ulogic; +signal abist_wl512_comp_ena_q : std_ulogic; +signal abist_bw_0_q : std_ulogic; +signal abist_bw_1_q : std_ulogic; +signal abist_ena_dc : std_ulogic; +signal abist_raw_dc_b : std_ulogic; + +signal mm_abist_waddr_0_q : std_ulogic_vector(0 to 9); +signal mm_abist_g8t_wenb_q : std_ulogic; +signal mm_abist_raddr_0_q : std_ulogic_vector(0 to 9); +signal mm_abist_g8t1p_renb_0_q : std_ulogic; +signal mm_abist_g6t_r_wb_q : std_ulogic; +signal mm_abist_di_0_q : std_ulogic_vector(0 to 3); +signal mm_abist_di_g6t_2r_q : std_ulogic_vector(0 to 3); +signal mm_abist_bw_0_q : std_ulogic; +signal mm_abist_bw_1_q : std_ulogic; +signal mm_abist_wl128_g8t_comp_ena_q : std_ulogic; +signal mm_abist_dcomp_q : std_ulogic_vector(0 to 3); +signal mm_abist_dcomp_g6t_2r_q : std_ulogic_vector(0 to 3); + +signal iu_abist_waddr_0_q : std_ulogic_vector(0 to 9); +signal iu_abist_g8t_wenb_q : std_ulogic; +signal iu_abist_raddr_0_q : std_ulogic_vector(0 to 9); +signal iu_abist_g8t1p_renb_0_q : std_ulogic; +signal iu_abist_g6t_r_wb_q : std_ulogic; +signal iu_abist_di_0_q : std_ulogic_vector(0 to 3); +signal iu_abist_di_g6t_2r_q : std_ulogic_vector(0 to 3); +signal iu_abist_bw_0_q : std_ulogic; +signal iu_abist_bw_1_q : std_ulogic; +signal iu_abist_wl64_g8t_comp_ena_q : std_ulogic; +signal iu_abist_wl128_g8t_comp_ena_q : std_ulogic; +signal iu_abist_wl256_comp_ena_q : std_ulogic; +signal iu_abist_dcomp_q : std_ulogic_vector(0 to 3); +signal iu_abist_dcomp_g6t_2r_q : std_ulogic_vector(0 to 3); + + +begin + + +--===================================================================== +-- ABIST Engine Instantiation +--===================================================================== +abist_engine: entity tri.tri_caa_prism_abist + port map ( abist_done_in_dc => abist_done_in_dc + , abist_done_out_dc => abist_done_out_dc + , abist_mode_dc => abist_mode_dc + , lbist_mode_dc => lbist_mode_dc + , lbist_ac_mode_dc => lbist_ac_mode_dc + + , abist_waddr_0 => abist_waddr_0(0 to 9) + , abist_waddr_1 => abist_waddr_1(0 to 9) + , abist_grf_wenb_0 => abist_grf_wenb_0 + , abist_grf_wenb_1 => abist_grf_wenb_1 + , abist_raddr_0 => abist_raddr_0(0 to 9) + , abist_raddr_1 => abist_raddr_1(0 to 9) + , abist_grf_renb_0 => abist_grf_renb_0 + , abist_grf_renb_1 => abist_grf_renb_1 + , abist_g8t_wenb => abist_g8t_wenb + , abist_g8t1p_renb_0 => abist_g8t1p_renb_0 + , abist_g6t_r_wb => abist_g6t_r_wb + , abist_di_g6t_2r => abist_di_g6t_2r(0 to 3) + , abist_di_0 => abist_di_0(0 to 3) + , abist_di_1 => abist_di_1(0 to 3) + , abist_dcomp => abist_dcomp(0 to 3) + , abist_dcomp_g6t_2r => abist_dcomp_g6t_2r(0 to 3) + , abist_bw_0 => abist_bw_0 + , abist_bw_1 => abist_bw_1 + , abist_wl32_g8t_comp_ena => abist_wl32_g8t_comp_ena + , abist_wl64_g8t_comp_ena => abist_wl64_g8t_comp_ena + , abist_wl128_g8t_comp_ena => abist_wl128_g8t_comp_ena + , abist_wl144_comp_ena => abist_wl144_comp_ena + , abist_wl256_comp_ena => abist_wl256_comp_ena + , abist_wl512_comp_ena => abist_wl512_comp_ena + , abist_ena_dc => abist_ena_dc + , abist_raw_dc_b => abist_raw_dc_b + + , lcb_clkoff_dc_b => lcb_clkoff_dc_b + , lcb_act_dis_dc => lcb_act_dis_dc + , lcb_d_mode_dc => lcb_d_mode_dc + , lcb_delay_lclkr_dc => lcb_delay_lclkr_dc + , lcb_delay_lclkr_np_dc => lcb_delay_lclkr_np_dc + , lcb_mpw1_dc_b => lcb_mpw1_dc_b + , lcb_mpw2_dc_b => lcb_mpw2_dc_b + , abist_scan_in => abst_sov(abst_right) + , abist_scan_out => abist_engine_so + , abist_sg => abist_sg + , abist_thold => abist_thold + , gptr_scan_in => gptr_scan_in + , gptr_scan_out => gptr_scan_out + , gptr_thold => gptr_thold + , nclk => nclk + , abist_start_test => abist_start_test_q + , scan_dis_dc_b => scan_dis_dc_b + , vdd => vdd + , gnd => gnd + ); + + +--===================================================================== +-- Staging latches for timing +--===================================================================== + lcbor_abist: tri_lcbor + generic map (expand_type => expand_type ) + port map ( clkoff_b => lcb_clkoff_dc_b, + thold => abist_thold, + sg => abist_sg, + act_dis => lcb_act_dis_dc, + forcee => force_abist, + thold_b => abist_thold_b ); + + abist_start_repower: tri_rlmreg_p + generic map (width => staging1_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => '1', + thold_b => abist_thold_b, + sg => abist_sg, + forcee => force_abist, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => abst_siv(staging1_offset to staging1_offset + staging1_size-1), + scout => abst_sov(staging1_offset to staging1_offset + staging1_size-1), + din(0) => abist_start_test, + dout(0) => abist_start_test_q ); + + abist_eng_repower: tri_rlmreg_p + generic map (width => staging2_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => abist_mode_dc, + thold_b => abist_thold_b, + sg => abist_sg, + forcee => force_abist, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => abst_siv(staging2_offset to staging2_offset + staging2_size-1), + scout => abst_sov(staging2_offset to staging2_offset + staging2_size-1), + din(0) => abist_grf_wenb_0, + din(1) => abist_grf_wenb_1, + din(2) => abist_g8t_wenb, + din(3) => abist_grf_renb_0, + din(4) => abist_grf_renb_1, + din(5) => abist_g8t1p_renb_0, + din(6) => abist_g6t_r_wb, + din(7) => abist_bw_0, + din(8) => abist_bw_1, + din(9) => abist_wl32_g8t_comp_ena, + din(10) => abist_wl64_g8t_comp_ena, + din(11) => abist_wl144_comp_ena, + din(12) => abist_wl512_comp_ena, + din(13 to 22) => abist_waddr_0, + din(23 to 32) => abist_waddr_1, + din(33 to 42) => abist_raddr_0, + din(43 to 52) => abist_raddr_1, + din(53 to 56) => abist_di_0, + din(57 to 60) => abist_di_1, + din(61 to 64) => abist_di_g6t_2r, + din(65 to 68) => abist_dcomp, + din(69 to 72) => abist_dcomp_g6t_2r, + dout(0) => abist_grf_wenb_0_q, + dout(1) => abist_grf_wenb_1_q, + dout(2) => abist_g8t_wenb_q, + dout(3) => abist_grf_renb_0_q, + dout(4) => abist_grf_renb_1_q, + dout(5) => abist_g8t1p_renb_0_q, + dout(6) => abist_g6t_r_wb_q, + dout(7) => abist_bw_0_q, + dout(8) => abist_bw_1_q, + dout(9) => abist_wl32_g8t_comp_ena_q, + dout(10) => abist_wl64_g8t_comp_ena_q, + dout(11) => abist_wl144_comp_ena_q, + dout(12) => abist_wl512_comp_ena_q, + dout(13 to 22) => abist_waddr_0_q, + dout(23 to 32) => abist_waddr_1_q, + dout(33 to 42) => abist_raddr_0_q, + dout(43 to 52) => abist_raddr_1_q, + dout(53 to 56) => abist_di_0_q, + dout(57 to 60) => abist_di_1_q, + dout(61 to 64) => abist_di_g6t_2r_q, + dout(65 to 68) => abist_dcomp_q, + dout(69 to 72) => abist_dcomp_g6t_2r_q ); + + abist_mm_repower: tri_rlmreg_p + generic map (width => staging3_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => abist_mode_dc, + thold_b => abist_thold_b, + sg => abist_sg, + forcee => force_abist, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => abst_siv(staging3_offset to staging3_offset + staging3_size-1), + scout => abst_sov(staging3_offset to staging3_offset + staging3_size-1), + din(0) => abist_g8t_wenb, + din(1) => abist_g8t1p_renb_0, + din(2) => abist_g6t_r_wb, + din(3) => abist_bw_0, + din(4) => abist_bw_1, + din(5) => abist_wl128_g8t_comp_ena, + din(6 to 15) => abist_waddr_0, + din(16 to 25) => abist_raddr_0, + din(26 to 29) => abist_di_0, + din(30 to 33) => abist_di_g6t_2r, + din(34 to 37) => abist_dcomp, + din(38 to 41) => abist_dcomp_g6t_2r, + dout(0) => mm_abist_g8t_wenb_q, + dout(1) => mm_abist_g8t1p_renb_0_q, + dout(2) => mm_abist_g6t_r_wb_q, + dout(3) => mm_abist_bw_0_q, + dout(4) => mm_abist_bw_1_q, + dout(5) => mm_abist_wl128_g8t_comp_ena_q, + dout(6 to 15) => mm_abist_waddr_0_q, + dout(16 to 25) => mm_abist_raddr_0_q, + dout(26 to 29) => mm_abist_di_0_q, + dout(30 to 33) => mm_abist_di_g6t_2r_q, + dout(34 to 37) => mm_abist_dcomp_q, + dout(38 to 41) => mm_abist_dcomp_g6t_2r_q ); + + abist_iu_repower: tri_rlmreg_p + generic map (width => staging4_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => abist_mode_dc, + thold_b => abist_thold_b, + sg => abist_sg, + forcee => force_abist, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => abst_siv(staging4_offset to staging4_offset + staging4_size-1), + scout => abst_sov(staging4_offset to staging4_offset + staging4_size-1), + din(0) => abist_g8t_wenb, + din(1) => abist_g8t1p_renb_0, + din(2) => abist_g6t_r_wb, + din(3) => abist_bw_0, + din(4) => abist_bw_1, + din(5) => abist_wl64_g8t_comp_ena, + din(6) => abist_wl128_g8t_comp_ena, + din(7) => abist_wl256_comp_ena, + din(8 to 17) => abist_waddr_0, + din(18 to 27) => abist_raddr_0, + din(28 to 31) => abist_di_0, + din(32 to 35) => abist_di_g6t_2r, + din(36 to 39) => abist_dcomp, + din(40 to 43) => abist_dcomp_g6t_2r, + dout(0) => iu_abist_g8t_wenb_q, + dout(1) => iu_abist_g8t1p_renb_0_q, + dout(2) => iu_abist_g6t_r_wb_q, + dout(3) => iu_abist_bw_0_q, + dout(4) => iu_abist_bw_1_q, + dout(5) => iu_abist_wl64_g8t_comp_ena_q, + dout(6) => iu_abist_wl128_g8t_comp_ena_q, + dout(7) => iu_abist_wl256_comp_ena_q, + dout(8 to 17) => iu_abist_waddr_0_q, + dout(18 to 27) => iu_abist_raddr_0_q, + dout(28 to 31) => iu_abist_di_0_q, + dout(32 to 35) => iu_abist_di_g6t_2r_q, + dout(36 to 39) => iu_abist_dcomp_q, + dout(40 to 43) => iu_abist_dcomp_g6t_2r_q ); + + -- abst ring + abst_siv(0 TO abst_right-1) <= (abist_scan_in and not bo_enable) & abst_sov(0 to abst_right-2); + abst_siv(abst_right) <= bo_abist_eng_si when bo_enable='1' else abst_sov(abst_right-1); + abist_scan_out <= abist_engine_so and scan_dis_dc_b; + + + +--===================================================================== +-- Output Assignments +--===================================================================== +-- Write Ports + pc_bx_abist_waddr_0 <= abist_waddr_0_q(0 to 9); + pc_iu_abist_waddr_0 <= iu_abist_waddr_0_q(0 to 9); + pc_fu_abist_waddr_0 <= abist_waddr_0_q(0 to 9); + pc_mm_abist_waddr_0 <= mm_abist_waddr_0_q(0 to 9); + pc_xu_abist_waddr_0 <= abist_waddr_0_q(0 to 9); + + pc_fu_abist_waddr_1 <= abist_waddr_1_q(0 to 9); + pc_xu_abist_waddr_1 <= abist_waddr_1_q(0 to 9); + + pc_fu_abist_grf_wenb_0 <= abist_grf_wenb_0_q; + pc_xu_abist_grf_wenb_0 <= abist_grf_wenb_0_q; + + pc_fu_abist_grf_wenb_1 <= abist_grf_wenb_1_q; + pc_xu_abist_grf_wenb_1 <= abist_grf_wenb_1_q; + + pc_bx_abist_g8t_wenb <= abist_g8t_wenb_q; + pc_iu_abist_g8t_wenb <= iu_abist_g8t_wenb_q; + pc_mm_abist_g8t_wenb <= mm_abist_g8t_wenb_q; + pc_xu_abist_g8t_wenb <= abist_g8t_wenb_q; + +-- Read Ports + pc_bx_abist_raddr_0 <= abist_raddr_0_q(0 to 9); + pc_iu_abist_raddr_0 <= iu_abist_raddr_0_q(0 to 9); + pc_fu_abist_raddr_0 <= abist_raddr_0_q(0 to 9); + pc_mm_abist_raddr_0 <= mm_abist_raddr_0_q(0 to 9); + pc_xu_abist_raddr_0 <= abist_raddr_0_q(0 to 9); + + pc_fu_abist_raddr_1 <= abist_raddr_1_q(0 to 9); + pc_xu_abist_raddr_1 <= abist_raddr_1_q(0 to 9); + + pc_fu_abist_grf_renb_0 <= abist_grf_renb_0_q; + pc_xu_abist_grf_renb_0 <= abist_grf_renb_0_q; + + pc_fu_abist_grf_renb_1 <= abist_grf_renb_1_q; + pc_xu_abist_grf_renb_1 <= abist_grf_renb_1_q; + + pc_bx_abist_g8t1p_renb_0 <= abist_g8t1p_renb_0_q; + pc_iu_abist_g8t1p_renb_0 <= iu_abist_g8t1p_renb_0_q; + pc_mm_abist_g8t1p_renb_0 <= mm_abist_g8t1p_renb_0_q; + pc_xu_abist_g8t1p_renb_0 <= abist_g8t1p_renb_0_q; + + pc_iu_abist_g6t_r_wb <= iu_abist_g6t_r_wb_q; + pc_mm_abist_g6t_r_wb <= mm_abist_g6t_r_wb_q; + pc_xu_abist_g6t_r_wb <= abist_g6t_r_wb_q; + +-- Data + pc_bx_abist_di_0 <= abist_di_0_q(0 to 3); + pc_iu_abist_di_0 <= iu_abist_di_0_q(0 to 3); + pc_fu_abist_di_0 <= abist_di_0_q(0 to 3); + pc_mm_abist_di_0 <= mm_abist_di_0_q(0 to 3); + pc_xu_abist_di_0 <= abist_di_0_q(0 to 3); + + pc_fu_abist_di_1 <= abist_di_1_q(0 to 3); + pc_xu_abist_di_1 <= abist_di_1_q(0 to 3); + + pc_iu_abist_di_g6t_2r <= iu_abist_di_g6t_2r_q(0 to 3); + pc_mm_abist_di_g6t_2r <= mm_abist_di_g6t_2r_q(0 to 3); + pc_xu_abist_di_g6t_2r <= abist_di_g6t_2r_q(0 to 3); + +-- BW + pc_bx_abist_g8t_bw_0 <= abist_bw_0_q; + pc_iu_abist_g8t_bw_0 <= iu_abist_bw_0_q; + pc_mm_abist_g8t_bw_0 <= mm_abist_bw_0_q; + pc_xu_abist_g8t_bw_0 <= abist_bw_0_q; + + pc_bx_abist_g8t_bw_1 <= abist_bw_1_q; + pc_iu_abist_g8t_bw_1 <= iu_abist_bw_1_q; + pc_mm_abist_g8t_bw_1 <= mm_abist_bw_1_q; + pc_xu_abist_g8t_bw_1 <= abist_bw_1_q; + + pc_iu_abist_g6t_bw <= iu_abist_bw_0_q & iu_abist_bw_1_q; + pc_xu_abist_g6t_bw <= abist_bw_0_q & abist_bw_1_q; + +-- Comp + pc_xu_abist_wl32_g8t_comp_ena <= abist_wl32_g8t_comp_ena_q; + pc_bx_abist_wl64_g8t_comp_ena <= abist_wl64_g8t_comp_ena_q; + pc_iu_abist_wl64_g8t_comp_ena <= iu_abist_wl64_g8t_comp_ena_q; + pc_iu_abist_wl128_g8t_comp_ena <= iu_abist_wl128_g8t_comp_ena_q; + pc_mm_abist_wl128_g8t_comp_ena <= mm_abist_wl128_g8t_comp_ena_q; + pc_fu_abist_wl144_comp_ena <= abist_wl144_comp_ena_q; + pc_xu_abist_wl144_comp_ena <= abist_wl144_comp_ena_q; + pc_iu_abist_wl256_comp_ena <= iu_abist_wl256_comp_ena_q; + pc_xu_abist_wl512_comp_ena <= abist_wl512_comp_ena_q; + + pc_bx_abist_g8t_dcomp <= abist_dcomp_q(0 to 3); + pc_iu_abist_g8t_dcomp <= iu_abist_dcomp_q(0 to 3); + pc_mm_abist_g8t_dcomp <= mm_abist_dcomp_q(0 to 3); + pc_xu_abist_g8t_dcomp <= abist_dcomp_q(0 to 3); + + pc_iu_abist_dcomp_g6t_2r <= iu_abist_dcomp_g6t_2r_q(0 to 3); + pc_mm_abist_dcomp_g6t_2r <= mm_abist_dcomp_g6t_2r_q(0 to 3); + pc_xu_abist_dcomp_g6t_2r <= abist_dcomp_g6t_2r_q(0 to 3); + +-- Misc Ctrl + pc_bx_abist_ena_dc <= abist_ena_dc; + pc_iu_abist_ena_dc <= abist_ena_dc; + pc_fu_abist_ena_dc <= abist_ena_dc; + pc_mm_abist_ena_dc <= abist_ena_dc; + pc_xu_abist_ena_dc <= abist_ena_dc; + + pc_bx_abist_raw_dc_b <= abist_raw_dc_b; + pc_iu_abist_raw_dc_b <= abist_raw_dc_b; + pc_fu_abist_raw_dc_b <= abist_raw_dc_b; + pc_mm_abist_raw_dc_b <= abist_raw_dc_b; + pc_xu_abist_raw_dc_b <= abist_raw_dc_b; + + +----------------------------------------------------------------------- +end pcq_abist; diff --git a/rel/src/vhdl/work/pcq_abist_bolton_frontend.vhdl b/rel/src/vhdl/work/pcq_abist_bolton_frontend.vhdl new file mode 100644 index 0000000..aa6de04 --- /dev/null +++ b/rel/src/vhdl/work/pcq_abist_bolton_frontend.vhdl @@ -0,0 +1,827 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- +-- Description: Pervasive ABIST ASIC Bolt-On +-- +--***************************************************************************** + +library ieee; +use ieee.std_logic_1164.all; +library ibm; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; +library support; +use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity pcq_abist_bolton_frontend is + generic( + expand_type : integer := 2; -- 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) + num_backends : integer := 44); + port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + +-- BISTCNTL interface + bcreset : in std_ulogic; + bcdata : in std_ulogic; + bcshcntl : in std_ulogic; + bcshdata : in std_ulogic; + bcexe : in std_ulogic; + bcsysrepair : in std_ulogic; + bo_enable : in std_ulogic; + bo_go : in std_ulogic; + +-- daisy chain + donein : in std_ulogic; + sdin : in std_ulogic; + doneout : out std_ulogic; + sdout : out std_ulogic; + diagloop_out : out std_ulogic; + waitin : in std_ulogic; + failin : in std_ulogic; + waitout : out std_ulogic; + failout : out std_ulogic; + +-- abist engine + abist_done : in std_ulogic; -- bist engine done + abist_start_test_int : out std_ulogic; -- start bist + abist_start_test : in std_ulogic; -- start bist + abist_si : out std_ulogic; -- to SI of bist engine (reg write) + abist_mode_dc : in std_ulogic; + abist_mode_dc_int : out std_ulogic; + +-- back ends + bo_unload : out std_ulogic; + bo_load : out std_ulogic; + bo_repair : out std_ulogic; -- load repair reg + bo_reset : out std_ulogic; -- reset backends + bo_shdata : out std_ulogic; -- shift data for timing and signature write and diag loop + bo_select : out std_ulogic_vector(0 to num_backends-1); -- select for mask and hier writes + bo_fail : in std_ulogic_vector(0 to num_backends-1); -- fail/no-fix + bo_diagout : in std_ulogic_vector(0 to num_backends-1); -- to diag mux + +-- thold / scan + lbist_ac_mode_dc : in std_ulogic; + ck_bo_sl_thold_6 : in std_ulogic; + ck_bo_sl_thold_0 : in std_ulogic; -- local thold + ck_bo_sg_0 : in std_ulogic; -- local scan gate + lcb_mpw1_dc_b : in std_ulogic; + lcb_mpw2_dc_b : in std_ulogic; + lcb_delay_lclkr_dc : in std_ulogic; + lcb_clkoff_dc_b : in std_ulogic; + lcb_act_dis_dc : in std_ulogic; + scan_in : in std_ulogic; -- scan in for frontend regs + scan_out : out std_ulogic; -- scan out for frontend regs + +-- top level thold / sg outputs, may be again overrided in leaves + bo_pc_abst_sl_thold_6 : out std_ulogic; -- thold to abist registers + bo_pc_pc_abst_sl_thold_6 : out std_ulogic; -- thold to bist engine + bo_pc_ary_nsl_thold_6 : out std_ulogic; -- thold to arrays + bo_pc_func_sl_thold_6 : out std_ulogic; -- thold to staging latches + bo_pc_time_sl_thold_6 : out std_ulogic; -- thold to timing regs + bo_pc_repr_sl_thold_6 : out std_ulogic; -- thold to repair regs + bo_pc_sg_6 : out std_ulogic); -- scan enable to all registers, + -- actual shifting controlled by tholds + +-- synopsys translate_off + + +-- synopsys translate_on +end pcq_abist_bolton_frontend; + +architecture pcq_abist_bolton_frontend of pcq_abist_bolton_frontend is +--===================================================================== +-- Types and Constants +--===================================================================== + + subtype Rstate is integer range 0 to 13; + subtype Tstate is std_ulogic_vector(Rstate); + subtype Renum is integer range 0 to 11; + subtype Tenum is std_ulogic_vector(Renum); + subtype Rinstruction is integer range 0 to 19; + subtype Tinstruction is std_ulogic_vector(Rinstruction); + subtype Rmode is integer range Rinstruction'right-19 to Rinstruction'right-17; + subtype Tmode is std_ulogic_vector(Rmode); + + constant Rkind : integer := Rinstruction'right-16; + constant Rloop : integer := Rinstruction'right-10; + constant Raccumulate : integer := Rinstruction'right-7; + constant RFARR : integer := Rinstruction'right-1; + constant Rmfctmode : integer := Rinstruction'right; + + subtype Tkind is std_ulogic; + subtype Raddr is integer range Rinstruction'right-15 to Rinstruction'right-4; + subtype Taddr is std_ulogic_vector(Raddr); + subtype Rw_addr is integer range Rinstruction'right-3 to Rinstruction'right; + subtype Tw_addr is std_ulogic_vector(0 to 3); + subtype Rr_addr is integer range Rinstruction'right-7 to Rinstruction'right; + subtype Tr_addr is std_ulogic_vector(0 to 7); + subtype Tshuttle is std_ulogic_vector(bo_fail'range); + subtype Tmemmask is Tshuttle; + subtype Tcounter is std_ulogic_vector(0 to 11); + subtype Tdiagptr is std_ulogic_vector(0 to 7); + + constant Rdiagptr_enable : integer := 0; -- bit set to 0: diag rotate disabled, no arrays selected during hierarchical writes + constant Rdiagptr_override : integer := 7; -- bit set to 0: bits 1-7 select array for diag/hierarchical write; bit set to 1: all arrays selected for hier. write + + subtype Rbackend_select is integer range 1 to 6; + subtype Tdiagdecr is std_ulogic_vector(0 to 31); + subtype Rdiagdecr is integer range Tdiagdecr'right-29 to Tdiagdecr'right; + constant Rdiagdecr_enable : integer := Tdiagdecr'right-30; + constant Rdiagdecr_evs : integer := Tdiagdecr'right-31; + + constant type_num : std_ulogic_vector(0 to 11) := X"129"; + constant fareg_length : Tcounter := X"020"; + constant max_sticky_length : Tcounter := X"240"; + constant warmup_length : Tcounter := X"010"; + + constant scan_offset_0 : integer := 0; + constant scan_offset_1 : integer := scan_offset_0 + 7; + constant scan_offset_2 : integer := scan_offset_1 + 3; + constant scan_offset_3 : integer := scan_offset_2 + Tstate'length + 3; + constant scan_offset_4 : integer := scan_offset_3 + Tenum'length; + constant scan_offset_5 : integer := scan_offset_4 + Tinstruction'length; + constant scan_offset_6 : integer := scan_offset_5 + Tshuttle'length; + constant scan_offset_7 : integer := scan_offset_6 + Tcounter'length; + constant scan_offset_8 : integer := scan_offset_7 + Tdiagptr'length; + constant scan_offset_9 : integer := scan_offset_8 + 1; + constant scan_offset_10 : integer := scan_offset_9 + Tmemmask'length; + constant scan_offset_11 : integer := scan_offset_10 + 1; + constant scan_offset_12 : integer := scan_offset_11 + Tdiagdecr'length; + constant scan_offset_13 : integer := scan_offset_12 + 2; + constant scan_offset_14 : integer := scan_offset_13 + bo_fail'length; + subtype Tint_scan is std_ulogic_vector(0 to scan_offset_14-1); + + type sul_bool is array(boolean) of std_ulogic; + constant pos : sul_bool := ( + false => '0' , + true => '1'); + +--===================================================================== +-- State Machine Constants +--===================================================================== + constant SC_IDLE : integer := 0; + constant SC_ENUM : integer := 1; + constant SC_WRITE : integer := 2; + constant SC_READ : integer := 3; + constant SC_IRLOAD : integer := 4; + constant SC_DIAGROT : integer := 5; + constant SC_0 : integer := 6; + constant SC_1 : integer := 7; + constant SC_2 : integer := 8; + constant SC_3PRE : integer := 9; + constant SC_3 : integer := 10; + constant SC_4 : integer := 11; + constant SC_RUNBST : integer := 12; + constant SC_CLEAR : integer := 13; + constant SM_IDLE : Tstate := "10000000000000"; + constant SM_ENUM : Tstate := "01000000000000"; + constant SM_WRITE : Tstate := "00100000000000"; + constant SM_READ : Tstate := "00010000000000"; + constant SM_IRLOAD : Tstate := "00001000000000"; + constant SM_DIAGROT : Tstate := "00000100000000"; + constant SM_0 : Tstate := "00000010000000"; + constant SM_1 : Tstate := "00000001000000"; + constant SM_2 : Tstate := "00000000100000"; + constant SM_3PRE : Tstate := "00000000010000"; + constant SM_3 : Tstate := "00000000001000"; + constant SM_4 : Tstate := "00000000000100"; + constant SM_RUNBST : Tstate := "00000000000010"; + constant SM_CLEAR : Tstate := "00000000000001"; + constant MODE_RUN : Tmode := "000"; + constant MODE_ENUM : Tmode := "001"; + constant MODE_READ : Tmode := "010"; + constant MODE_WRITE : Tmode := "011"; + constant ADDR_BISTMASK : Tw_addr := X"0"; -- control reg 0 + constant ADDR_MEMMASK : Tw_addr := X"1"; -- control reg 1 + constant ADDR_DIAGPTR : Tw_addr := X"2"; -- control reg 2 + constant ADDR_RBISTMASK : Tr_addr := X"00"; -- read control reg 0 + constant ADDR_RMEMMASK : Tr_addr := X"01"; -- read control reg 1 + constant ADDR_RDIAGPTR : Tr_addr := X"02"; -- read control reg 2 + constant ADDR_ABIST : Tw_addr := X"B"; -- control reg B + constant ADDR_TIMING : Tw_addr := X"C"; -- control reg C + constant ADDR_SIGNATURE : Tw_addr := X"D"; -- control reg D + constant ADDR_DIAGCOUNT : Tw_addr := X"E"; -- control reg E + constant ADDR_RDIAGCOUNT : Tr_addr := X"0E"; -- read control reg E + constant ADDR_TYPE : Tr_addr := X"10"; -- status reg 0 + constant ADDR_ENUM : Tr_addr := X"11"; -- status reg 1 + constant ADDR_BISTDONE : Tr_addr := X"12"; -- status reg 2 + constant ADDR_WAIT : Tr_addr := X"13"; -- status reg 3 + constant ADDR_FAIL : Tr_addr := X"14"; -- status reg 4 + + +--===================================================================== +-- Signal Declarations +--===================================================================== + + signal state_q, state_d : Tstate; + signal instruction_d, instruction_q : Tinstruction; + signal shift_instruction, shift_write : std_ulogic; + signal shuttle_select, shuttle_d, shuttle_q : Tshuttle; + signal shift_shuttle : std_ulogic; +-- + signal enum_d, enum_q : Tenum; + signal clear_enum, count_enum : std_ulogic; + signal mode : Tmode; + signal kind : Tkind; + signal addr : Taddr; + signal w_reg_addr : Tw_addr; + signal r_reg_addr : Tr_addr; + signal reg_select : std_ulogic; + signal s_idle, s_enum, s_write, s_read, s_irload, + s_diagrot, s_0, s_1, s_2, s_3pre, s_3, s_4, s_runbst, s_clear : std_ulogic; + signal s_3pre_delayed, s_3_delayed, s_4_delayed : std_ulogic; + signal bistmask_d, bistmask_q, shift_bistmask : std_ulogic; + signal bistdone_q, bistdone_d : std_ulogic; + signal memmask_d, memmask_q : Tmemmask; + signal shift_memmask : std_ulogic; + + signal done_d, done_q, wait_d, wait_q, fail_d, fail_q : std_ulogic; + signal bcshctrl_ff, bcdata_ff, bcshdata_ff, bcexe_ff, bcreset_ff, bo_go_ff, bcsysrepair_ff : std_ulogic; + signal write_signature, write_timing : std_ulogic; + signal int_scan_in, int_scan_out : Tint_scan; + signal ck_bo_sl_thold_0_b : std_ulogic; + signal force_func : std_ulogic; + signal count_d, count_q : Tcounter; + signal count_done : std_ulogic; + + signal diagptr_q, diagptr_d : Tdiagptr; + signal shift_diagptr : std_ulogic; + signal diagmux_and : std_ulogic_vector(bo_diagout'range); + signal bo_select_int : std_ulogic_vector(bo_select'range); + signal sg_int : std_ulogic; + signal diagdecr_q, diagdecr_d : Tdiagdecr; + signal shift_diagcount, diagdecr_zero : std_ulogic; + signal diagloop_out_d, diagloop_out_int : std_ulogic; + signal write_abist_q, write_abist_d : std_ulogic; + signal bo_fail_ff, bo_fail_pre : std_ulogic_vector(0 to num_backends-1); + +begin + + sg_int <= '0' when bo_enable = '1' else ck_bo_sg_0; + +--===================================================================== +-- Shuttle and Diagloop +--===================================================================== + shift_shuttle <= bcshdata_ff and ((s_idle and pos(mode = MODE_READ)) or (s_idle and pos(mode = MODE_RUN)) or s_diagrot or s_read) and bo_enable; + + shuttle : process (bistdone_q, bistmask_q, bo_fail_ff, diagdecr_q, diagptr_q, + enum_q, memmask_q, r_reg_addr) is + begin + shuttle_select <= (others => '0'); + case r_reg_addr is + when ADDR_RBISTMASK => shuttle_select(Tshuttle'right) <= bistmask_q; + when ADDR_RMEMMASK => shuttle_select <= memmask_q; + when ADDR_RDIAGPTR => shuttle_select(Tshuttle'right-diagptr_q'right to Tshuttle'right) <= diagptr_q; + when ADDR_RDIAGCOUNT=> shuttle_select(Tshuttle'right-Tdiagdecr'right to Tshuttle'right) <= diagdecr_q; + when ADDR_TYPE => shuttle_select(Tshuttle'right-type_num'right to Tshuttle'right) <= type_num; + when ADDR_ENUM => shuttle_select(Tshuttle'right-Tenum'right to Tshuttle'right) <= enum_q; + when ADDR_BISTDONE => shuttle_select(Tshuttle'right) <= bistdone_q; + when ADDR_FAIL => shuttle_select <= bo_fail_ff; + when others => null; + end case; + end process; + + shuttle_d <= shuttle_q(1 to shuttle_q'right) & sdin when (shift_shuttle and not s_diagrot) = '1' else + shuttle_q(1 to shuttle_q'right) & diagloop_out_int when (shift_shuttle and s_diagrot) = '1' + else shuttle_select; + sdout <= shuttle_q(shuttle_d'left); + + diagmux : for i in bo_diagout'range generate + begin + diagmux_and(i) <= bo_diagout(i) and bo_select_int(i); + end generate; + diagloop_out_int <= or_reduce(diagmux_and) and diagptr_q(Rdiagptr_enable) and s_diagrot; + diagloop_out_d <= diagloop_out_int and not lbist_ac_mode_dc; + +--===================================================================== +-- Instruction register & universal registers +--===================================================================== + shift_instruction <= bcshctrl_ff and (s_idle or s_irload) and bo_enable; + instruction_d <= instruction_q(1 to instruction_q'right) & bcdata_ff; + abist_si <= bcdata_ff and not bcreset_ff; + shift_write <= ((s_idle and pos(mode = MODE_WRITE)) or s_write) and bcshdata_ff and bo_enable; + shift_diagptr <= shift_write and reg_select and pos(w_reg_addr = ADDR_DIAGPTR) and bo_enable; + diagptr_d <= diagptr_q(1 to diagptr_q'right) & bcdata_ff; + + shift_diagcount <= shift_write and reg_select and pos(w_reg_addr = ADDR_DIAGCOUNT) and bo_enable; + diagdecr_d <= diagdecr_q(1 to diagdecr_q'right) & bcdata_ff + when shift_diagcount = '1' else + diagdecr_q(diagdecr_q'left to Rdiagdecr'left-1) & (diagdecr_q(Rdiagdecr) - 1) + when s_runbst = '1' and diagdecr_q(Rdiagdecr_enable) = '1' else + diagdecr_q; + diagdecr_zero <= pos(diagdecr_q(Rdiagdecr) = 0) and diagdecr_q(Rdiagdecr_enable); + + shift_bistmask <= shift_write and reg_select and pos(w_reg_addr = ADDR_BISTMASK) and bo_enable; + bistmask_d <= bcdata_ff; + + shift_memmask <= shift_write and reg_select and pos(w_reg_addr = ADDR_MEMMASK) and bo_enable; + memmask_d <= memmask_q(1 to memmask_q'right) & bcdata_ff; + + write_timing <= shift_write and reg_select and pos(w_reg_addr = ADDR_TIMING); + write_signature <= shift_write and reg_select and pos(w_reg_addr = ADDR_SIGNATURE); + write_abist_d <= shift_write and reg_select and pos(w_reg_addr = ADDR_ABIST) and not lbist_ac_mode_dc; + +--===================================================================== +-- Backend selection from diagptr +--===================================================================== + bo_select_decoder : for i in bo_select'range generate + begin + bo_select_int(i) <= (diagptr_q(Rdiagptr_override) or pos(diagptr_q(Rbackend_select) = i)) + and diagptr_q(Rdiagptr_enable); + end generate; + bo_select <= (others => '0') when lbist_ac_mode_dc = '1' else bo_select_int when (shift_write and reg_select) = '1' else not memmask_q; + + bo_repair <= s_4 and not lbist_ac_mode_dc; + bo_unload <= (s_3 or s_3pre) and not lbist_ac_mode_dc; + bo_reset <= bcreset_ff or s_clear or (s_runbst and abist_done) or (s_3pre and count_done) or (s_3 and count_done) or lbist_ac_mode_dc; -- reset fail/nofix bits during warmup, reset counters at end of a state + bo_shdata <= '0' when lbist_ac_mode_dc = '1' else shuttle_d(shuttle_d'left) when s_diagrot = '1' else bcdata_ff and not bcreset_ff; + bo_load <= (write_signature) and not lbist_ac_mode_dc; + bo_fail_pre <= (others => '0') when lbist_ac_mode_dc = '1' else bo_fail; + +--===================================================================== +-- Counters +--===================================================================== + count_done <= pos(count_q = X"000"); + bistdone_d <= '0' when s_0 = '1' or s_clear = '1' else '1' when (s_4 = '1' and count_done = '1') or diagdecr_zero = '1' else bistdone_q; + +--===================================================================== +-- Enumeration counter +--===================================================================== + clear_enum <= s_idle and bcexe_ff and pos(mode = MODE_ENUM); + count_enum <= s_enum; + enum_d <= (others => '0') when clear_enum = '1' else enum_q + 1 when count_enum = '1' else enum_q; + +--===================================================================== +-- Daisy Chain FFs +--===================================================================== + done_d <= donein and (bistmask_q or bistdone_q or (s_idle and pos(mode = MODE_ENUM)) or s_enum); + wait_d <= waitin and bistdone_q and diagdecr_q(Rdiagdecr_evs); + fail_d <= failin or (not bistmask_q and s_idle and or_reduce(bo_fail_ff and memmask_q)); + +--===================================================================== +-- Thold/SG Decoder +--===================================================================== + bo_pc_abst_sl_thold_6 <= ck_bo_sl_thold_6 when (bcreset_ff or s_3_delayed or s_clear)='1' + else '0' when (s_1 or s_2 or s_runbst)='1' and diagdecr_zero='0' + else '1'; + bo_pc_ary_nsl_thold_6 <= not(bcreset_ff or s_2 or s_runbst); + bo_pc_func_sl_thold_6 <= not(s_0 or s_1 or s_2 or s_runbst); + bo_pc_time_sl_thold_6 <= ck_bo_sl_thold_6 when (write_timing)='1' else '1'; -- not during reset + bo_pc_repr_sl_thold_6 <= ck_bo_sl_thold_6 when (s_4_delayed or s_3pre_delayed)='1' else '1'; -- not during reset + + bo_pc_sg_6 <= bcreset_ff or write_abist_q or write_timing or s_4_delayed or s_3_delayed or s_3pre_delayed or s_clear; + abist_start_test_int <= s_runbst and not abist_done when bo_enable='1' else abist_start_test; + bo_pc_pc_abst_sl_thold_6 <= ck_bo_sl_thold_6 when write_abist_q='1' else '0' when (s_1 or s_2 or bcreset_ff or s_runbst)='1' else '1'; + abist_mode_dc_int <= s_0 or s_1 or s_2 or s_runbst when bo_enable='1' else abist_mode_dc; + +--===================================================================== +-- State Transitions +--===================================================================== + trans : process (abist_done, bcexe_ff, bcreset_ff, bcshctrl_ff, bcshdata_ff, + bo_go_ff, count_done, count_q, diagdecr_q(Rdiagdecr_evs), diagdecr_zero, + done_q, instruction_q(Raccumulate), instruction_q(RFARR), + instruction_q(Rloop), mode, state_q, bcsysrepair_ff) is + begin + state_d <= state_q; + count_d <= count_q - 1; + case state_q is + when SM_IDLE => + if (bcshctrl_ff = '1') then + state_d <= SM_IRLOAD; + else + case mode is + when MODE_ENUM => if bcexe_ff = '1' then state_d <= SM_ENUM; end if; + when MODE_READ => if bcshdata_ff = '1' then state_d <= SM_READ; end if; + when MODE_WRITE => if bcshdata_ff = '1' then state_d <= SM_WRITE; end if; + when MODE_RUN => + if bo_go_ff = '1' then + if instruction_q(Raccumulate)='1' then + state_d <= SM_0; + count_d <= warmup_length; + else + state_d <= SM_CLEAR; + count_d <= max_sticky_length; + end if; + elsif bcshdata_ff = '1' then + state_d <= SM_DIAGROT; + end if; + when others => null; + end case; + end if; + when SM_IRLOAD => + if (bcshctrl_ff = '0') then + state_d <= SM_IDLE; + end if; + when SM_ENUM => + if (done_q = '1') then + state_d <= SM_IDLE; + end if; + when SM_READ => + if (bcshdata_ff = '0') then + state_d <= SM_IDLE; + end if; + when SM_WRITE => + if (bcshdata_ff = '0') then + state_d <= SM_IDLE; + end if; + when SM_DIAGROT => + if (bcshdata_ff = '0') then + state_d <= SM_IDLE; + end if; + when SM_CLEAR => + if (count_done = '1') then + state_d <= SM_0; + count_d <= warmup_length; + end if; + when SM_0 => + if (count_done = '1') then + state_d <= SM_1; + count_d <= warmup_length; + end if; + when SM_1 => + if (count_done = '1') then + state_d <= SM_2; + end if; + when SM_2 => + if (bcexe_ff = '1') then + state_d <= SM_RUNBST; + end if; + when SM_RUNBST => + if (abist_done = '1') then + state_d <= SM_3PRE; + end if; + if diagdecr_zero = '1' then + state_d <= SM_IDLE; + end if; + count_d <= fareg_length; + when SM_3PRE => + if (count_done = '1') then + state_d <= SM_3; + count_d <= max_sticky_length; + end if; + when SM_3 => + if (count_done = '1') then + if (diagdecr_q(Rdiagdecr_evs) = '0' or instruction_q(RFARR)='1' or bcsysrepair_ff='1') then + state_d <= SM_4; + else + state_d <= SM_IDLE; + end if; + count_d <= fareg_length; + end if; + when SM_4 => + if (count_done = '1') then + if instruction_q(Rloop) = '1' then + state_d <= SM_0; + else + state_d <= SM_IDLE; + end if; + end if; + when others => state_d <= SM_IDLE; + end case; + if bcreset_ff = '1' then + state_d <= SM_IDLE; + end if; + end process; + +--===================================================================== +-- Latches +--===================================================================== +input_reg: entity tri.tri_boltreg_p + generic map (width => scan_offset_1 - scan_offset_0, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => bo_enable, + thold_b => ck_bo_sl_thold_0_b, + sg => sg_int, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => int_scan_in(scan_offset_0 to scan_offset_1-1), + scout => int_scan_out(scan_offset_0 to scan_offset_1-1), + din(0) => bcdata, + din(1) => bcshcntl, + din(2) => bcshdata, + din(3) => bcexe, + din(4) => bcreset, + din(5) => bo_go, + din(6) => bcsysrepair, + dout(0) => bcdata_ff, + dout(1) => bcshctrl_ff, + dout(2) => bcshdata_ff, + dout(3) => bcexe_ff, + dout(4) => bcreset_ff, + dout(5) => bo_go_ff, + dout(6) => bcsysrepair_ff); + +daisy_reg: entity tri.tri_boltreg_p + generic map (width => scan_offset_2 - scan_offset_1, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => bo_enable, + thold_b => ck_bo_sl_thold_0_b, + sg => sg_int, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => int_scan_in(scan_offset_1 to scan_offset_2-1), + scout => int_scan_out(scan_offset_1 to scan_offset_2-1), + din(0) => done_d, + din(1) => wait_d, + din(2) => fail_d, + dout(0) => done_q, + dout(1) => wait_q, + dout(2) => fail_q ); + +doneout <= done_q; +waitout <= wait_q; +failout <= fail_q; + +state_reg: entity tri.tri_boltreg_p + generic map (width => scan_offset_3 - scan_offset_2, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => bo_enable, + thold_b => ck_bo_sl_thold_0_b, + sg => sg_int, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => int_scan_in(scan_offset_2 to scan_offset_3-1), + scout => int_scan_out(scan_offset_2 to scan_offset_3-1), + din(Tstate'range) => state_d, + din(Tstate'right + 1) => s_3pre, + din(Tstate'right + 2) => s_3, + din(Tstate'right + 3) => s_4, + dout(Tstate'range) => state_q, + dout(Tstate'right + 1) => s_3pre_delayed, + dout(Tstate'right + 2) => s_3_delayed, + dout(Tstate'right + 3) => s_4_delayed); + + s_idle <= state_q(SC_IDLE); + s_enum <= state_q(SC_ENUM); + s_write <= state_q(SC_WRITE); + s_read <= state_q(SC_READ); + s_irload <= state_q(SC_IRLOAD); + s_diagrot <= state_q(SC_DIAGROT); + s_0 <= state_q(SC_0); + s_1 <= state_q(SC_1); + s_2 <= state_q(SC_2); + s_3pre <= state_q(SC_3PRE); + s_3 <= state_q(SC_3); + s_4 <= state_q(SC_4); + s_runbst <= state_q(SC_RUNBST); + s_clear <= state_q(SC_CLEAR); + +enum_reg: entity tri.tri_boltreg_p + generic map (width => enum_d'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => bo_enable, + thold_b => ck_bo_sl_thold_0_b, + sg => sg_int, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => int_scan_in(scan_offset_3 to scan_offset_4-1), + scout => int_scan_out(scan_offset_3 to scan_offset_4-1), + din => enum_d, + dout => enum_q ); + +instr_reg: entity tri.tri_boltreg_p + generic map (width => instruction_d'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => shift_instruction, + thold_b => ck_bo_sl_thold_0_b, + sg => sg_int, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => int_scan_in(scan_offset_4 to scan_offset_5-1), + scout => int_scan_out(scan_offset_4 to scan_offset_5-1), + din => instruction_d, + dout => instruction_q ); + +mode <= instruction_q(Rmode); +kind <= instruction_q(Rkind); +addr <= instruction_q(Raddr); +w_reg_addr <= instruction_q(Rw_addr); +r_reg_addr <= instruction_q(Rr_addr); +reg_select <= '1' when addr = X"000" or (kind = '1' and addr = type_num) or (kind = '0' and addr = enum_q) else '0'; + +shuttle_reg: entity tri.tri_boltreg_p + generic map (width => shuttle_d'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => bo_enable, + thold_b => ck_bo_sl_thold_0_b, + sg => sg_int, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => int_scan_in(scan_offset_5 to scan_offset_6-1), + scout => int_scan_out(scan_offset_5 to scan_offset_6-1), + din => shuttle_d, + dout => shuttle_q ); + +count_reg: entity tri.tri_boltreg_p + generic map (width => count_d'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => bo_enable, + thold_b => ck_bo_sl_thold_0_b, + sg => sg_int, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => int_scan_in(scan_offset_6 to scan_offset_7-1), + scout => int_scan_out(scan_offset_6 to scan_offset_7-1), + din => count_d, + dout => count_q ); + +diagptr_reg: entity tri.tri_boltreg_p + generic map (width => diagptr_d'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => shift_diagptr, + thold_b => ck_bo_sl_thold_0_b, + sg => sg_int, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => int_scan_in(scan_offset_7 to scan_offset_8-1), + scout => int_scan_out(scan_offset_7 to scan_offset_8-1), + din => diagptr_d, + dout => diagptr_q ); + +bistmask_reg: entity tri.tri_boltreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => shift_bistmask, + thold_b => ck_bo_sl_thold_0_b, + sg => sg_int, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => int_scan_in(scan_offset_8 to scan_offset_9-1), + scout => int_scan_out(scan_offset_8 to scan_offset_9-1), + din(0) => bistmask_d, + dout(0) => bistmask_q ); + +memmask_reg: entity tri.tri_boltreg_p + generic map (width => memmask_d'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => shift_memmask, + thold_b => ck_bo_sl_thold_0_b, + sg => sg_int, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => int_scan_in(scan_offset_9 to scan_offset_10-1), + scout => int_scan_out(scan_offset_9 to scan_offset_10-1), + din => memmask_d, + dout => memmask_q ); + +bistdone_reg: entity tri.tri_boltreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => bo_enable, + thold_b => ck_bo_sl_thold_0_b, + sg => sg_int, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => int_scan_in(scan_offset_10 to scan_offset_11-1), + scout => int_scan_out(scan_offset_10 to scan_offset_11-1), + din(0) => bistdone_d, + dout(0) => bistdone_q ); + +diagdecr_reg: entity tri.tri_boltreg_p + generic map (width => diagdecr_d'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => bo_enable, + thold_b => ck_bo_sl_thold_0_b, + sg => sg_int, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => int_scan_in(scan_offset_11 to scan_offset_12-1), + scout => int_scan_out(scan_offset_11 to scan_offset_12-1), + din => diagdecr_d, + dout => diagdecr_q ); + +out_reg: entity tri.tri_boltreg_p + generic map (width => scan_offset_13 - scan_offset_12, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => bo_enable, + thold_b => ck_bo_sl_thold_0_b, + sg => sg_int, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => int_scan_in(scan_offset_12 to scan_offset_13-1), + scout => int_scan_out(scan_offset_12 to scan_offset_13-1), + din(0) => diagloop_out_d, + din(1) => write_abist_d, + dout(0) => diagloop_out, + dout(1) => write_abist_q ); + +fail_reg: entity tri.tri_boltreg_p + generic map (width => scan_offset_14 - scan_offset_13, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => bo_enable, + thold_b => ck_bo_sl_thold_0_b, + sg => sg_int, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => int_scan_in(scan_offset_13 to scan_offset_14-1), + scout => int_scan_out(scan_offset_13 to scan_offset_14-1), + din => bo_fail_pre, + dout => bo_fail_ff ); + + +int_scan_in(0) <= scan_in and not bo_enable; +int_scan_in(1 to int_scan_in'right) <= int_scan_out(0 to int_scan_out'right-1); +scan_out <= int_scan_out(int_scan_out'right); + +--===================================================================== +-- Thold/SG Staging +--===================================================================== +lcbor_func: entity tri.tri_lcbor +generic map (expand_type => expand_type ) +port map ( + clkoff_b => lcb_clkoff_dc_b, + thold => ck_bo_sl_thold_0, + sg => sg_int, + act_dis => lcb_act_dis_dc, + forcee => force_func, + thold_b => ck_bo_sl_thold_0_b ); + +----------------------------------------------------------------------- +end pcq_abist_bolton_frontend; diff --git a/rel/src/vhdl/work/pcq_abist_bolton_stg.vhdl b/rel/src/vhdl/work/pcq_abist_bolton_stg.vhdl new file mode 100644 index 0000000..bd09e8c --- /dev/null +++ b/rel/src/vhdl/work/pcq_abist_bolton_stg.vhdl @@ -0,0 +1,211 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- +-- Description: Pervasive ABIST bolt-on sync and staging +-- +--***************************************************************************** + +library ieee; +use ieee.std_logic_1164.all; +library ibm; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +library support; +use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity pcq_abist_bolton_stg is +generic(expand_type : integer := 2); -- 0=ibm (umbra), 1=non-ibm, 2=ibm (mpg) +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + pc_pc_ccflush_dc : in std_ulogic; + + pu_pc_bo_enable : in std_ulogic; + pu_pc_bo_go : in std_ulogic; + pu_pc_bo_cntlclk : in std_ulogic; + pu_pc_bo_reset : in std_ulogic; + pu_pc_bo_fcshdata : in std_ulogic; + pu_pc_bo_fcreset : in std_ulogic; + + pc_bx_bo_enable_3 : out std_ulogic; + pc_fu_bo_enable_3 : out std_ulogic; + pc_iu_bo_enable_4 : out std_ulogic; + pc_mm_bo_enable_4 : out std_ulogic; + pc_xu_bo_enable_3 : out std_ulogic; + pc_pc_bo_go_0 : out std_ulogic; + pc_pc_bo_enable_0 : out std_ulogic; + pc_pc_bo_cntlclk_0 : out std_ulogic; + pc_pc_bo_reset_0 : out std_ulogic; + pc_pc_bo_fcshdata_0 : out std_ulogic; + pc_pc_bo_fcreset_0 : out std_ulogic); + +-- synopsys translate_off + + + +-- synopsys translate_on +end pcq_abist_bolton_stg; + +architecture pcq_abist_bolton_stg of pcq_abist_bolton_stg is + +signal pc_all_bolton_enable_5 : std_ulogic; +signal pc_all_bolton_enable_4 : std_ulogic; +signal pc_all_bolton_enable_3_int : std_ulogic; +signal pc_pc_bolton_enable_2 : std_ulogic; +signal pc_pc_bolton_enable_1 : std_ulogic; +signal pc_pc_bolton_go_1 : std_ulogic; +signal pc_pc_bc_cntlclk_1 : std_ulogic; +signal pc_pc_bc_reset_1 : std_ulogic; +signal pc_pc_bc_fcshdata_1 : std_ulogic; +signal pc_pc_bc_fcreset_1 : std_ulogic; + +begin + + bolton_enable_sync_meta : entity tri.tri_plat -- non-scan plats, cannot use tri_async_lt scan latch for this + generic map( + width => 6, + expand_type => expand_type) + port map( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_dc, + din(0) => pu_pc_bo_enable, + din(1) => pu_pc_bo_go, + din(2) => pu_pc_bo_cntlclk, + din(3) => pu_pc_bo_reset, + din(4) => pu_pc_bo_fcshdata, + din(5) => pu_pc_bo_fcreset, + q(0) => pc_all_bolton_enable_5, + q(1) => pc_pc_bolton_go_1, + q(2) => pc_pc_bc_cntlclk_1, + q(3) => pc_pc_bc_reset_1, + q(4) => pc_pc_bc_fcshdata_1, + q(5) => pc_pc_bc_fcreset_1); + + bolton_enable_sync : entity tri.tri_plat -- non-scan plats, cannot use tri_async_lt scan latch for this + generic map( + width => 6, + expand_type => expand_type) + port map( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_dc, + din(0) => pc_all_bolton_enable_5, + din(1) => pc_pc_bolton_go_1, + din(2) => pc_pc_bc_cntlclk_1, + din(3) => pc_pc_bc_reset_1, + din(4) => pc_pc_bc_fcshdata_1, + din(5) => pc_pc_bc_fcreset_1, + q(0) => pc_all_bolton_enable_4, + q(1) => pc_pc_bo_go_0, + q(2) => pc_pc_bo_cntlclk_0, + q(3) => pc_pc_bo_reset_0, + q(4) => pc_pc_bo_fcshdata_0, + q(5) => pc_pc_bo_fcreset_0); + + + bolton_enable_sync_2 : entity tri.tri_plat -- non-scan plats, cannot use tri_async_lt scan latch for this + generic map( + width => 4, + expand_type => expand_type) + port map( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_dc, + din(0) => pc_all_bolton_enable_4, + din(1) => pc_all_bolton_enable_3_int, + din(2) => pc_pc_bolton_enable_2, + din(3) => pc_pc_bolton_enable_1, + q(0) => pc_all_bolton_enable_3_int, + q(1) => pc_pc_bolton_enable_2, + q(2) => pc_pc_bolton_enable_1, + q(3) => pc_pc_bo_enable_0); + + +-- Splitting out bx/fu/xu unit bolton_enable signals 4to3 staging for placement + timing + bx_bolton_enable_4_3 : entity tri.tri_plat + generic map( width => 1, expand_type => expand_type) + port map( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_dc, + din(0) => pc_all_bolton_enable_4, + q(0) => pc_bx_bo_enable_3 ); + + fu_bolton_enable_4_3 : entity tri.tri_plat + generic map( width => 1, expand_type => expand_type) + port map( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_dc, + din(0) => pc_all_bolton_enable_4, + q(0) => pc_fu_bo_enable_3 ); + + xu_bolton_enable_4_3 : entity tri.tri_plat + generic map( width => 1, expand_type => expand_type) + port map( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_dc, + din(0) => pc_all_bolton_enable_4, + q(0) => pc_xu_bo_enable_3 ); + + +-- Splitting out iu/mm unit bolton_enable signals 5to4 staging for placement + timing + iu_bolton_enable_5_4 : entity tri.tri_plat + generic map( width => 1, expand_type => expand_type) + port map( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_dc, + din(0) => pc_all_bolton_enable_5, + q(0) => pc_iu_bo_enable_4 ); + + mm_bolton_enable_5_4 : entity tri.tri_plat + generic map( width => 1, expand_type => expand_type) + port map( + vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_dc, + din(0) => pc_all_bolton_enable_5, + q(0) => pc_mm_bo_enable_4 ); + + +end architecture pcq_abist_bolton_stg; diff --git a/rel/src/vhdl/work/pcq_clks.vhdl b/rel/src/vhdl/work/pcq_clks.vhdl new file mode 100644 index 0000000..d4f0b24 --- /dev/null +++ b/rel/src/vhdl/work/pcq_clks.vhdl @@ -0,0 +1,464 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- +-- Description: Pervasive Core LCB Controls +-- +--***************************************************************************** + +library ieee; +use ieee.std_logic_1164.all; +library support; +use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity pcq_clks is +generic(expand_type : integer := 2 -- 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) +); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + rtim_sl_thold_6 : in std_ulogic; + func_sl_thold_6 : in std_ulogic; + func_nsl_thold_6 : in std_ulogic; + ary_nsl_thold_6 : in std_ulogic; + sg_6 : in std_ulogic; + fce_6 : in std_ulogic; + gsd_test_enable_dc : in std_ulogic; + gsd_test_acmode_dc : in std_ulogic; + ccflush_dc : in std_ulogic; + ccenable_dc : in std_ulogic; + scan_type_dc : in std_ulogic_vector(0 to 8); + lbist_en_dc : in std_ulogic; + lbist_ip_dc : in std_ulogic; + rg_ck_fast_xstop : in std_ulogic; + ct_ck_pm_ccflush_disable : in std_ulogic; + ct_ck_pm_raise_tholds : in std_ulogic; +-- Thold + control from bolton frontend + bolton_enable_dc : in std_ulogic; + bolton_enable_sync : in std_ulogic; + bolton_ccflush : in std_ulogic; + bolton_fcshdata : in std_ulogic; + bolton_fcreset : in std_ulogic; + bc_cntlclk_sync : in std_ulogic; + bo_pc_abst_sl_thold_6 : in std_ulogic; + bo_pc_pc_abst_sl_thold_6 : in std_ulogic; + bo_pc_ary_nsl_thold_6 : in std_ulogic; + bo_pc_func_sl_thold_6 : in std_ulogic; + bo_pc_time_sl_thold_6 : in std_ulogic; + bo_pc_repr_sl_thold_6 : in std_ulogic; + bo_pc_sg_6 : in std_ulogic; +-- --Thold + control outputs to the units + pc_xu_ccflush_dc : out std_ulogic; + pc_xu_gptr_sl_thold_3 : out std_ulogic; + pc_xu_time_sl_thold_3 : out std_ulogic; + pc_xu_repr_sl_thold_3 : out std_ulogic; + pc_xu_abst_sl_thold_3 : out std_ulogic; + pc_xu_abst_slp_sl_thold_3 : out std_ulogic; + pc_xu_bolt_sl_thold_3 : out std_ulogic; + pc_xu_regf_sl_thold_3 : out std_ulogic; + pc_xu_regf_slp_sl_thold_3 : out std_ulogic; + pc_xu_func_sl_thold_3 : out std_ulogic_vector(0 to 4); + pc_xu_func_slp_sl_thold_3 : out std_ulogic_vector(0 to 4); + pc_xu_cfg_sl_thold_3 : out std_ulogic; + pc_xu_cfg_slp_sl_thold_3 : out std_ulogic; + pc_xu_func_nsl_thold_3 : out std_ulogic; + pc_xu_func_slp_nsl_thold_3 : out std_ulogic; + pc_xu_ary_nsl_thold_3 : out std_ulogic; + pc_xu_ary_slp_nsl_thold_3 : out std_ulogic; + pc_xu_sg_3 : out std_ulogic_vector(0 to 4); + pc_xu_fce_3 : out std_ulogic_vector(0 to 1); + pc_bx_ccflush_dc : out std_ulogic; + pc_bx_func_sl_thold_3 : out std_ulogic; + pc_bx_func_slp_sl_thold_3 : out std_ulogic; + pc_bx_gptr_sl_thold_3 : out std_ulogic; + pc_bx_time_sl_thold_3 : out std_ulogic; + pc_bx_repr_sl_thold_3 : out std_ulogic; + pc_bx_abst_sl_thold_3 : out std_ulogic; + pc_bx_bolt_sl_thold_3 : out std_ulogic; + pc_bx_ary_nsl_thold_3 : out std_ulogic; + pc_bx_ary_slp_nsl_thold_3 : out std_ulogic; + pc_bx_sg_3 : out std_ulogic; + pc_mm_ccflush_dc : out std_ulogic; + pc_iu_ccflush_dc : out std_ulogic; + pc_iu_gptr_sl_thold_4 : out std_ulogic; + pc_iu_time_sl_thold_4 : out std_ulogic; + pc_iu_repr_sl_thold_4 : out std_ulogic; + pc_iu_abst_sl_thold_4 : out std_ulogic; + pc_iu_abst_slp_sl_thold_4 : out std_ulogic; + pc_iu_bolt_sl_thold_4 : out std_ulogic; + pc_iu_regf_slp_sl_thold_4 : out std_ulogic; + pc_iu_func_sl_thold_4 : out std_ulogic; + pc_iu_func_slp_sl_thold_4 : out std_ulogic; + pc_iu_cfg_sl_thold_4 : out std_ulogic; + pc_iu_cfg_slp_sl_thold_4 : out std_ulogic; + pc_iu_func_nsl_thold_4 : out std_ulogic; + pc_iu_func_slp_nsl_thold_4 : out std_ulogic; + pc_iu_ary_nsl_thold_4 : out std_ulogic; + pc_iu_ary_slp_nsl_thold_4 : out std_ulogic; + pc_iu_sg_4 : out std_ulogic; + pc_iu_fce_4 : out std_ulogic; + pc_fu_ccflush_dc : out std_ulogic; + pc_fu_gptr_sl_thold_3 : out std_ulogic; + pc_fu_time_sl_thold_3 : out std_ulogic; + pc_fu_repr_sl_thold_3 : out std_ulogic; + pc_fu_abst_sl_thold_3 : out std_ulogic; + pc_fu_abst_slp_sl_thold_3 : out std_ulogic; + pc_fu_bolt_sl_thold_3 : out std_ulogic; + pc_fu_func_sl_thold_3 : out std_ulogic_vector(0 to 1); + pc_fu_func_slp_sl_thold_3 : out std_ulogic_vector(0 to 1); + pc_fu_cfg_sl_thold_3 : out std_ulogic; + pc_fu_cfg_slp_sl_thold_3 : out std_ulogic; + pc_fu_func_nsl_thold_3 : out std_ulogic; + pc_fu_func_slp_nsl_thold_3 : out std_ulogic; + pc_fu_ary_nsl_thold_3 : out std_ulogic; + pc_fu_ary_slp_nsl_thold_3 : out std_ulogic; + pc_fu_sg_3 : out std_ulogic_vector(0 to 1); + pc_fu_fce_3 : out std_ulogic; + pc_pc_ccflush_dc : out std_ulogic; + pc_pc_gptr_sl_thold_0 : out std_ulogic; + pc_pc_abst_sl_thold_0 : out std_ulogic; + pc_pc_bolt_sl_thold_6 : out std_ulogic; + pc_pc_bolt_sl_thold_0 : out std_ulogic; + pc_pc_func_sl_thold_0 : out std_ulogic; + pc_pc_func_slp_sl_thold_0 : out std_ulogic; + pc_pc_cfg_sl_thold_0 : out std_ulogic; + pc_pc_cfg_slp_sl_thold_0 : out std_ulogic; + pc_pc_sg_0 : out std_ulogic; +-- --Trace/Trigger Signals + dbg_clks_ctrls : out std_ulogic_vector(0 to 13) +); + + +-- synopsys translate_off + +-- synopsys translate_on +end pcq_clks; + +architecture pcq_clks of pcq_clks is +signal rtim_sl_thold_5 : std_ulogic; +signal func_sl_thold_5 : std_ulogic; +signal func_nsl_thold_5 : std_ulogic; +signal ary_nsl_thold_5 : std_ulogic; +signal sg_5 : std_ulogic; +signal fce_5 : std_ulogic; +signal pc_pc_ccflush_out_dc : std_ulogic; +signal pc_pc_gptr_sl_thold_4 : std_ulogic; +signal pc_pc_time_sl_thold_4 : std_ulogic; +signal pc_pc_repr_sl_thold_4 : std_ulogic; +signal pc_pc_abst_sl_thold_4 : std_ulogic; +signal pc_pc_abst_slp_sl_thold_4 : std_ulogic; +signal pc_pc_regf_sl_thold_4 : std_ulogic; +signal pc_pc_regf_slp_sl_thold_4 : std_ulogic; +signal pc_pc_func_sl_thold_4 : std_ulogic_vector(0 to 1); +signal pc_pc_func_slp_sl_thold_4 : std_ulogic_vector(0 to 1); +signal pc_pc_cfg_sl_thold_4 : std_ulogic; +signal pc_pc_cfg_slp_sl_thold_4 : std_ulogic; +signal pc_pc_func_nsl_thold_4 : std_ulogic; +signal pc_pc_func_slp_nsl_thold_4 : std_ulogic; +signal pc_pc_ary_nsl_thold_4 : std_ulogic; +signal pc_pc_ary_slp_nsl_thold_4 : std_ulogic; +signal pc_pc_rtim_sl_thold_4 : std_ulogic; +signal pc_pc_sg_4 : std_ulogic_vector(0 to 1); +signal pc_pc_fce_4 : std_ulogic_vector(0 to 1); +signal bo_pc_sg_5 : std_ulogic; +signal bo_pc_bolt_sl_thold_6 : std_ulogic; +signal bo_pc_abst_sl_thold_5 : std_ulogic; +signal bo_pc_pc_abst_sl_thold_5 : std_ulogic; +signal bo_pc_bolt_sl_thold_5 : std_ulogic; +signal bo_pc_ary_nsl_thold_5 : std_ulogic; +signal bo_pc_func_sl_thold_5 : std_ulogic; +signal bo_pc_time_sl_thold_5 : std_ulogic; +signal bo_pc_repr_sl_thold_5 : std_ulogic; +signal bo_pc_sg_4 : std_ulogic; +signal bo_pc_abst_sl_thold_4 : std_ulogic; +signal bo_pc_pc_abst_sl_thold_4 : std_ulogic; +signal bo_pc_bolt_sl_thold_4 : std_ulogic; +signal bo_pc_ary_nsl_thold_4 : std_ulogic; +signal bo_pc_func_sl_thold_4 : std_ulogic; +signal bo_pc_time_sl_thold_4 : std_ulogic; +signal bo_pc_repr_sl_thold_4 : std_ulogic; +signal bc_cntlclk_sync_2 : std_ulogic; +signal bc_cntlclk_sync_3 : std_ulogic; +signal ccflush_dc_int : std_ulogic; + + + +begin + +ccflush_dc_int <= ccflush_dc or (bolton_enable_dc and bolton_ccflush); + +clkctrl : entity work.pcq_clks_ctrl +generic map (expand_type => expand_type) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + rtim_sl_thold_5 => rtim_sl_thold_5, + func_sl_thold_5 => func_sl_thold_5, + func_nsl_thold_5 => func_nsl_thold_5, + ary_nsl_thold_5 => ary_nsl_thold_5, + sg_5 => sg_5, + fce_5 => fce_5, + gsd_test_enable_dc => gsd_test_enable_dc, + gsd_test_acmode_dc => gsd_test_acmode_dc, + ccflush_dc => ccflush_dc_int, + ccenable_dc => ccenable_dc, + scan_type_dc => scan_type_dc, + lbist_en_dc => lbist_en_dc, + lbist_ip_dc => lbist_ip_dc, + rg_ck_fast_xstop => rg_ck_fast_xstop, + ct_ck_pm_ccflush_disable => ct_ck_pm_ccflush_disable, + ct_ck_pm_raise_tholds => ct_ck_pm_raise_tholds, +-- --Thold + control outputs to the units + pc_pc_ccflush_out_dc => pc_pc_ccflush_out_dc, + pc_pc_gptr_sl_thold_4 => pc_pc_gptr_sl_thold_4, + pc_pc_time_sl_thold_4 => pc_pc_time_sl_thold_4, + pc_pc_repr_sl_thold_4 => pc_pc_repr_sl_thold_4, + pc_pc_cfg_sl_thold_4 => pc_pc_cfg_sl_thold_4, + pc_pc_cfg_slp_sl_thold_4 => pc_pc_cfg_slp_sl_thold_4, + pc_pc_abst_sl_thold_4 => pc_pc_abst_sl_thold_4, + pc_pc_abst_slp_sl_thold_4 => pc_pc_abst_slp_sl_thold_4, + pc_pc_regf_sl_thold_4 => pc_pc_regf_sl_thold_4, + pc_pc_regf_slp_sl_thold_4 => pc_pc_regf_slp_sl_thold_4, + pc_pc_func_sl_thold_4 => pc_pc_func_sl_thold_4, + pc_pc_func_slp_sl_thold_4 => pc_pc_func_slp_sl_thold_4, + pc_pc_func_nsl_thold_4 => pc_pc_func_nsl_thold_4, + pc_pc_func_slp_nsl_thold_4 => pc_pc_func_slp_nsl_thold_4, + pc_pc_ary_nsl_thold_4 => pc_pc_ary_nsl_thold_4, + pc_pc_ary_slp_nsl_thold_4 => pc_pc_ary_slp_nsl_thold_4, + pc_pc_rtim_sl_thold_4 => pc_pc_rtim_sl_thold_4, + pc_pc_sg_4 => pc_pc_sg_4, + pc_pc_fce_4 => pc_pc_fce_4 +); + +clkstg : entity work.pcq_clks_stg +generic map (expand_type => expand_type) +port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_pc_ccflush_out_dc => pc_pc_ccflush_out_dc, + pc_pc_gptr_sl_thold_4 => pc_pc_gptr_sl_thold_4, + pc_pc_time_sl_thold_4 => pc_pc_time_sl_thold_4, + pc_pc_repr_sl_thold_4 => pc_pc_repr_sl_thold_4, + pc_pc_cfg_sl_thold_4 => pc_pc_cfg_sl_thold_4, + pc_pc_cfg_slp_sl_thold_4 => pc_pc_cfg_slp_sl_thold_4, + pc_pc_abst_sl_thold_4 => pc_pc_abst_sl_thold_4, + pc_pc_abst_slp_sl_thold_4 => pc_pc_abst_slp_sl_thold_4, + pc_pc_regf_sl_thold_4 => pc_pc_regf_sl_thold_4, + pc_pc_regf_slp_sl_thold_4 => pc_pc_regf_slp_sl_thold_4, + pc_pc_func_sl_thold_4 => pc_pc_func_sl_thold_4, + pc_pc_func_slp_sl_thold_4 => pc_pc_func_slp_sl_thold_4, + pc_pc_func_nsl_thold_4 => pc_pc_func_nsl_thold_4, + pc_pc_func_slp_nsl_thold_4 => pc_pc_func_slp_nsl_thold_4, + pc_pc_ary_nsl_thold_4 => pc_pc_ary_nsl_thold_4, + pc_pc_ary_slp_nsl_thold_4 => pc_pc_ary_slp_nsl_thold_4, + pc_pc_rtim_sl_thold_4 => pc_pc_rtim_sl_thold_4, + pc_pc_sg_4 => pc_pc_sg_4, + pc_pc_fce_4 => pc_pc_fce_4, +-- Thold + control from bolton frontend + bolton_enable => bolton_enable_sync, + bolton_fcshdata => bolton_fcshdata, + bolton_fcreset => bolton_fcreset, + bo_pc_abst_sl_thold_4 => bo_pc_abst_sl_thold_4, + bo_pc_pc_abst_sl_thold_4 => bo_pc_pc_abst_sl_thold_4, + bo_pc_bolt_sl_thold_4 => bo_pc_bolt_sl_thold_4, + bo_pc_ary_nsl_thold_4 => bo_pc_ary_nsl_thold_4, + bo_pc_func_sl_thold_4 => bo_pc_func_sl_thold_4, + bo_pc_time_sl_thold_4 => bo_pc_time_sl_thold_4, + bo_pc_repr_sl_thold_4 => bo_pc_repr_sl_thold_4, + bo_pc_sg_4 => bo_pc_sg_4, +-- --Thold + control outputs to the units + pc_xu_ccflush_dc => pc_xu_ccflush_dc, + pc_xu_gptr_sl_thold_3 => pc_xu_gptr_sl_thold_3, + pc_xu_time_sl_thold_3 => pc_xu_time_sl_thold_3, + pc_xu_repr_sl_thold_3 => pc_xu_repr_sl_thold_3, + pc_xu_abst_sl_thold_3 => pc_xu_abst_sl_thold_3, + pc_xu_abst_slp_sl_thold_3 => pc_xu_abst_slp_sl_thold_3, + pc_xu_bolt_sl_thold_3 => pc_xu_bolt_sl_thold_3, + pc_xu_regf_sl_thold_3 => pc_xu_regf_sl_thold_3, + pc_xu_regf_slp_sl_thold_3 => pc_xu_regf_slp_sl_thold_3, + pc_xu_func_sl_thold_3 => pc_xu_func_sl_thold_3, + pc_xu_func_slp_sl_thold_3 => pc_xu_func_slp_sl_thold_3, + pc_xu_cfg_sl_thold_3 => pc_xu_cfg_sl_thold_3, + pc_xu_cfg_slp_sl_thold_3 => pc_xu_cfg_slp_sl_thold_3, + pc_xu_func_nsl_thold_3 => pc_xu_func_nsl_thold_3, + pc_xu_func_slp_nsl_thold_3 => pc_xu_func_slp_nsl_thold_3, + pc_xu_ary_nsl_thold_3 => pc_xu_ary_nsl_thold_3, + pc_xu_ary_slp_nsl_thold_3 => pc_xu_ary_slp_nsl_thold_3, + pc_xu_sg_3 => pc_xu_sg_3, + pc_xu_fce_3 => pc_xu_fce_3, + pc_bx_ccflush_dc => pc_bx_ccflush_dc, + pc_bx_func_sl_thold_3 => pc_bx_func_sl_thold_3, + pc_bx_func_slp_sl_thold_3 => pc_bx_func_slp_sl_thold_3, + pc_bx_gptr_sl_thold_3 => pc_bx_gptr_sl_thold_3, + pc_bx_time_sl_thold_3 => pc_bx_time_sl_thold_3, + pc_bx_repr_sl_thold_3 => pc_bx_repr_sl_thold_3, + pc_bx_abst_sl_thold_3 => pc_bx_abst_sl_thold_3, + pc_bx_bolt_sl_thold_3 => pc_bx_bolt_sl_thold_3, + pc_bx_ary_nsl_thold_3 => pc_bx_ary_nsl_thold_3, + pc_bx_ary_slp_nsl_thold_3 => pc_bx_ary_slp_nsl_thold_3, + pc_bx_sg_3 => pc_bx_sg_3, + pc_mm_ccflush_dc => pc_mm_ccflush_dc, + pc_iu_ccflush_dc => pc_iu_ccflush_dc, + pc_iu_gptr_sl_thold_4 => pc_iu_gptr_sl_thold_4, + pc_iu_time_sl_thold_4 => pc_iu_time_sl_thold_4, + pc_iu_repr_sl_thold_4 => pc_iu_repr_sl_thold_4, + pc_iu_abst_sl_thold_4 => pc_iu_abst_sl_thold_4, + pc_iu_abst_slp_sl_thold_4 => pc_iu_abst_slp_sl_thold_4, + pc_iu_bolt_sl_thold_4 => pc_iu_bolt_sl_thold_4, + pc_iu_regf_slp_sl_thold_4 => pc_iu_regf_slp_sl_thold_4, + pc_iu_func_sl_thold_4 => pc_iu_func_sl_thold_4, + pc_iu_func_slp_sl_thold_4 => pc_iu_func_slp_sl_thold_4, + pc_iu_cfg_sl_thold_4 => pc_iu_cfg_sl_thold_4, + pc_iu_cfg_slp_sl_thold_4 => pc_iu_cfg_slp_sl_thold_4, + pc_iu_func_nsl_thold_4 => pc_iu_func_nsl_thold_4, + pc_iu_func_slp_nsl_thold_4 => pc_iu_func_slp_nsl_thold_4, + pc_iu_ary_nsl_thold_4 => pc_iu_ary_nsl_thold_4, + pc_iu_ary_slp_nsl_thold_4 => pc_iu_ary_slp_nsl_thold_4, + pc_iu_sg_4 => pc_iu_sg_4, + pc_iu_fce_4 => pc_iu_fce_4, + pc_fu_ccflush_dc => pc_fu_ccflush_dc, + pc_fu_gptr_sl_thold_3 => pc_fu_gptr_sl_thold_3, + pc_fu_time_sl_thold_3 => pc_fu_time_sl_thold_3, + pc_fu_repr_sl_thold_3 => pc_fu_repr_sl_thold_3, + pc_fu_abst_sl_thold_3 => pc_fu_abst_sl_thold_3, + pc_fu_abst_slp_sl_thold_3 => pc_fu_abst_slp_sl_thold_3, + pc_fu_bolt_sl_thold_3 => pc_fu_bolt_sl_thold_3, + pc_fu_func_sl_thold_3 => pc_fu_func_sl_thold_3, + pc_fu_func_slp_sl_thold_3 => pc_fu_func_slp_sl_thold_3, + pc_fu_cfg_sl_thold_3 => pc_fu_cfg_sl_thold_3, + pc_fu_cfg_slp_sl_thold_3 => pc_fu_cfg_slp_sl_thold_3, + pc_fu_func_nsl_thold_3 => pc_fu_func_nsl_thold_3, + pc_fu_func_slp_nsl_thold_3 => pc_fu_func_slp_nsl_thold_3, + pc_fu_ary_nsl_thold_3 => pc_fu_ary_nsl_thold_3, + pc_fu_ary_slp_nsl_thold_3 => pc_fu_ary_slp_nsl_thold_3, + pc_fu_sg_3 => pc_fu_sg_3, + pc_fu_fce_3 => pc_fu_fce_3, + pc_pc_ccflush_dc => pc_pc_ccflush_dc, + pc_pc_gptr_sl_thold_0 => pc_pc_gptr_sl_thold_0, + pc_pc_abst_sl_thold_0 => pc_pc_abst_sl_thold_0, + pc_pc_bolt_sl_thold_0 => pc_pc_bolt_sl_thold_0, + pc_pc_func_sl_thold_0 => pc_pc_func_sl_thold_0, + pc_pc_func_slp_sl_thold_0 => pc_pc_func_slp_sl_thold_0, + pc_pc_cfg_sl_thold_0 => pc_pc_cfg_sl_thold_0, + pc_pc_cfg_slp_sl_thold_0 => pc_pc_cfg_slp_sl_thold_0, + pc_pc_sg_0 => pc_pc_sg_0 +); + +bolton_thold_gen: tri_plat + generic map( width => 2, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => ccflush_dc_int, + din( 0) => bc_cntlclk_sync, + din( 1) => bc_cntlclk_sync_2, + q( 0) => bc_cntlclk_sync_2, + q( 1) => bc_cntlclk_sync_3 + ); + +bo_pc_bolt_sl_thold_6 <= not bolton_ccflush and not (bc_cntlclk_sync_2 and (bc_cntlclk_sync_2 xor bc_cntlclk_sync_3)) ; +pc_pc_bolt_sl_thold_6 <= bo_pc_bolt_sl_thold_6; + +lvl6to5_plat: tri_plat + generic map( width => 14, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => ccflush_dc_int, + din( 0) => rtim_sl_thold_6, + din( 1) => func_sl_thold_6, + din( 2) => func_nsl_thold_6, + din( 3) => ary_nsl_thold_6, + din( 4) => sg_6, + din( 5) => fce_6, + din( 6) => bo_pc_sg_6, + din( 7) => bo_pc_bolt_sl_thold_6, + din( 8) => bo_pc_abst_sl_thold_6, + din( 9) => bo_pc_pc_abst_sl_thold_6, + din(10) => bo_pc_ary_nsl_thold_6, + din(11) => bo_pc_func_sl_thold_6, + din(12) => bo_pc_time_sl_thold_6, + din(13) => bo_pc_repr_sl_thold_6, + q( 0) => rtim_sl_thold_5, + q( 1) => func_sl_thold_5, + q( 2) => func_nsl_thold_5, + q( 3) => ary_nsl_thold_5, + q( 4) => sg_5, + q( 5) => fce_5, + q( 6) => bo_pc_sg_5, + q( 7) => bo_pc_bolt_sl_thold_5, + q( 8) => bo_pc_abst_sl_thold_5, + q( 9) => bo_pc_pc_abst_sl_thold_5, + q(10) => bo_pc_ary_nsl_thold_5, + q(11) => bo_pc_func_sl_thold_5, + q(12) => bo_pc_time_sl_thold_5, + q(13) => bo_pc_repr_sl_thold_5 + ); + +lvl5to4_plat: tri_plat + generic map( width => 8, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => ccflush_dc_int, + din( 0) => bo_pc_sg_5, + din( 1) => bo_pc_bolt_sl_thold_5, + din( 2) => bo_pc_abst_sl_thold_5, + din( 3) => bo_pc_pc_abst_sl_thold_5, + din( 4) => bo_pc_ary_nsl_thold_5, + din( 5) => bo_pc_func_sl_thold_5, + din( 6) => bo_pc_time_sl_thold_5, + din( 7) => bo_pc_repr_sl_thold_5, + q( 0) => bo_pc_sg_4, + q( 1) => bo_pc_bolt_sl_thold_4, + q( 2) => bo_pc_abst_sl_thold_4, + q( 3) => bo_pc_pc_abst_sl_thold_4, + q( 4) => bo_pc_ary_nsl_thold_4, + q( 5) => bo_pc_func_sl_thold_4, + q( 6) => bo_pc_time_sl_thold_4, + q( 7) => bo_pc_repr_sl_thold_4 + ); + + +--===================================================================== +-- Trace/Trigger Signals +--===================================================================== + dbg_clks_ctrls <= ccenable_dc & -- 0 + gsd_test_enable_dc & -- 1 + gsd_test_acmode_dc & -- 2 + lbist_en_dc & -- 3 + lbist_ip_dc & -- 4 + scan_type_dc(0 to 7) & -- 5:12 + rg_ck_fast_xstop ; -- 13 + +end pcq_clks; diff --git a/rel/src/vhdl/work/pcq_clks_ctrl.vhdl b/rel/src/vhdl/work/pcq_clks_ctrl.vhdl new file mode 100644 index 0000000..b47acbb --- /dev/null +++ b/rel/src/vhdl/work/pcq_clks_ctrl.vhdl @@ -0,0 +1,293 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- +-- Description: Pervasive Core LCB Control Component +-- +--***************************************************************************** + +library ieee; +use ieee.std_logic_1164.all; +library ibm; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +library support; +use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity pcq_clks_ctrl is +generic(expand_type : integer := 2 -- 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) +); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + rtim_sl_thold_5 : in std_ulogic; + func_sl_thold_5 : in std_ulogic; + func_nsl_thold_5 : in std_ulogic; + ary_nsl_thold_5 : in std_ulogic; + sg_5 : in std_ulogic; + fce_5 : in std_ulogic; + gsd_test_enable_dc : in std_ulogic; + gsd_test_acmode_dc : in std_ulogic; + ccflush_dc : in std_ulogic; + ccenable_dc : in std_ulogic; + scan_type_dc : in std_ulogic_vector(0 to 8); + lbist_en_dc : in std_ulogic; + lbist_ip_dc : in std_ulogic; + rg_ck_fast_xstop : in std_ulogic; + ct_ck_pm_ccflush_disable : in std_ulogic; + ct_ck_pm_raise_tholds : in std_ulogic; +-- --Thold + control outputs to the units + pc_pc_ccflush_out_dc : out std_ulogic; + pc_pc_gptr_sl_thold_4 : out std_ulogic; + pc_pc_time_sl_thold_4 : out std_ulogic; + pc_pc_repr_sl_thold_4 : out std_ulogic; + pc_pc_cfg_sl_thold_4 : out std_ulogic; + pc_pc_cfg_slp_sl_thold_4 : out std_ulogic; + pc_pc_abst_sl_thold_4 : out std_ulogic; + pc_pc_abst_slp_sl_thold_4 : out std_ulogic; + pc_pc_regf_sl_thold_4 : out std_ulogic; + pc_pc_regf_slp_sl_thold_4 : out std_ulogic; + pc_pc_func_sl_thold_4 : out std_ulogic_vector(0 to 1); + pc_pc_func_slp_sl_thold_4 : out std_ulogic_vector(0 to 1); + pc_pc_func_nsl_thold_4 : out std_ulogic; + pc_pc_func_slp_nsl_thold_4 : out std_ulogic; + pc_pc_ary_nsl_thold_4 : out std_ulogic; + pc_pc_ary_slp_nsl_thold_4 : out std_ulogic; + pc_pc_rtim_sl_thold_4 : out std_ulogic; + pc_pc_sg_4 : out std_ulogic_vector(0 to 1); + pc_pc_fce_4 : out std_ulogic_vector(0 to 1) +); +-- synopsys translate_off + +-- synopsys translate_on +end pcq_clks_ctrl; + +architecture pcq_clks_ctrl of pcq_clks_ctrl is +-- Scan ring select decodes for scan_type_dc vector +constant scantype_func : natural := 0; +constant scantype_mode : natural := 1; +constant scantype_ccfg : natural := 2; +constant scantype_gptr : natural := 2; +constant scantype_regf : natural := 3; +constant scantype_fuse : natural := 3; +constant scantype_lbst : natural := 4; +constant scantype_abst : natural := 5; +constant scantype_repr : natural := 6; +constant scantype_time : natural := 7; +constant scantype_bndy : natural := 8; +constant scantype_fary : natural := 9; + +signal scan_type_b : std_ulogic_vector(0 to 8); -- scantype; +signal fast_xstop_gated_staged : std_ulogic; +signal fce_in, sg_in : std_ulogic; +signal ary_nsl_thold, func_nsl_thold : std_ulogic; +signal rtim_sl_thold, func_sl_thold : std_ulogic; +signal gptr_sl_thold_in : std_ulogic; +signal time_sl_thold_in : std_ulogic; +signal repr_sl_thold_in : std_ulogic; +signal rtim_sl_thold_in : std_ulogic; +signal cfg_run_sl_thold_in : std_ulogic; +signal cfg_slp_sl_thold_in : std_ulogic; +signal abst_run_sl_thold_in : std_ulogic; +signal abst_slp_sl_thold_in : std_ulogic; +signal regf_run_sl_thold_in : std_ulogic; +signal regf_slp_sl_thold_in : std_ulogic; +signal func_run_sl_thold_in : std_ulogic; +signal func_slp_sl_thold_in : std_ulogic; +signal func_run_nsl_thold_in : std_ulogic; +signal func_slp_nsl_thold_in : std_ulogic; +signal ary_run_nsl_thold_in : std_ulogic; +signal ary_slp_nsl_thold_in : std_ulogic; +signal pm_ccflush_disable_dc : std_ulogic; +signal ccflush_out_dc_int : std_ulogic; +signal testdc : std_ulogic; +signal thold_overide_ctrl : std_ulogic; + +signal unused_signals : std_ulogic; + + + + +begin + + +-- unused signals +unused_signals <= or_reduce(scan_type_b(2) & scan_type_b(4) & scan_type_b(6 to 8) & lbist_ip_dc); + +-- detect test dc mode +testdc <= gsd_test_enable_dc and not gsd_test_acmode_dc; + +-- enable sg/fce before latching +sg_in <= sg_5 and ccenable_dc; +fce_in <= fce_5 and ccenable_dc; + +-- scan chain type +scan_type_b <= GATE_AND(sg_in, not scan_type_dc); + +-- setup for xx_thold_5 inputs +thold_overide_ctrl <= fast_xstop_gated_staged and not sg_in and not lbist_en_dc and not gsd_test_enable_dc; + +rtim_sl_thold <= rtim_sl_thold_5; +func_sl_thold <= func_sl_thold_5 OR thold_overide_ctrl; +func_nsl_thold <= func_nsl_thold_5 OR thold_overide_ctrl; +ary_nsl_thold <= ary_nsl_thold_5 OR thold_overide_ctrl; + +-- setup for plat flush control signals +-- Active when power_management enabled (PM_Sleep_enable or PM_RVW_enable active) +-- If plats were in flush mode, forces plats to be clocked again for power-savings. +pm_ccflush_disable_dc <= ct_ck_pm_ccflush_disable; + +ccflush_out_dc_int <= ccflush_dc AND (NOT pm_ccflush_disable_dc OR lbist_en_dc OR testdc); +pc_pc_ccflush_out_dc <= ccflush_out_dc_int; + + +-- OR and MUX of thold signals + -- scan only: stop if not scanning, not part of LBIST, hence no sg_in here +gptr_sl_thold_in <= func_sl_thold or not scan_type_dc(scantype_gptr) or not ccenable_dc; + + -- scan only: stop if not scanning, not part of LBIST, hence no sg_in here +time_sl_thold_in <= func_sl_thold or not scan_type_dc(scantype_time) or not ccenable_dc; + + -- scan only: stop if not scanning, not part of LBIST, hence no sg_in here +repr_sl_thold_in <= func_sl_thold or not scan_type_dc(scantype_repr) or not ccenable_dc; + + +cfg_run_sl_thold_in <= func_sl_thold or scan_type_b(scantype_mode) or + (ct_ck_pm_raise_tholds and not sg_in and not lbist_en_dc and not gsd_test_enable_dc); + +cfg_slp_sl_thold_in <= func_sl_thold or scan_type_b(scantype_mode); + + +abst_run_sl_thold_in <= func_sl_thold or scan_type_b(scantype_abst) or + (ct_ck_pm_raise_tholds and not sg_in and not lbist_en_dc and not gsd_test_enable_dc); + +abst_slp_sl_thold_in <= func_sl_thold or scan_type_b(scantype_abst); + + +regf_run_sl_thold_in <= func_sl_thold or scan_type_b(scantype_regf) or + (ct_ck_pm_raise_tholds and not sg_in and not lbist_en_dc and not gsd_test_enable_dc); + +regf_slp_sl_thold_in <= func_sl_thold or scan_type_b(scantype_regf); + + +func_run_sl_thold_in <= func_sl_thold or scan_type_b(scantype_func) or + (ct_ck_pm_raise_tholds and not sg_in and not lbist_en_dc and not gsd_test_enable_dc); + +func_slp_sl_thold_in <= func_sl_thold or scan_type_b(scantype_func); + + +func_run_nsl_thold_in <= func_nsl_thold or + (ct_ck_pm_raise_tholds and not fce_in and not lbist_en_dc and not gsd_test_enable_dc); + +func_slp_nsl_thold_in <= func_nsl_thold; + + +ary_run_nsl_thold_in <= ary_nsl_thold or + (ct_ck_pm_raise_tholds and not fce_in and not lbist_en_dc and not gsd_test_enable_dc); + +ary_slp_nsl_thold_in <= ary_nsl_thold; + + +rtim_sl_thold_in <= rtim_sl_thold; + + +-- PLAT staging/redrive +fast_stop_staging: tri_plat + generic map( width => 1, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => ccflush_out_dc_int, + din(0) => rg_ck_fast_xstop, + q(0) => fast_xstop_gated_staged + ); + +sg_fce_plat: tri_plat + generic map(width => 4, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => ccflush_out_dc_int, + din(0) => sg_in, + din(1) => sg_in, + din(2) => fce_in, + din(3) => fce_in, + q(0) => pc_pc_sg_4(0), + q(1) => pc_pc_sg_4(1), + q(2) => pc_pc_fce_4(0), + q(3) => pc_pc_fce_4(1) + ); + +thold_plat: tri_plat + generic map( width => 18, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => ccflush_out_dc_int, + din( 0) => gptr_sl_thold_in, + din( 1) => time_sl_thold_in, + din( 2) => repr_sl_thold_in, + din( 3) => cfg_run_sl_thold_in, + din( 4) => cfg_slp_sl_thold_in, + din( 5) => abst_run_sl_thold_in, + din( 6) => abst_slp_sl_thold_in, + din( 7) => regf_run_sl_thold_in, + din( 8) => regf_slp_sl_thold_in, + din( 9) => func_run_sl_thold_in, + din(10) => func_run_sl_thold_in, + din(11) => func_slp_sl_thold_in, + din(12) => func_slp_sl_thold_in, + din(13) => func_run_nsl_thold_in, + din(14) => func_slp_nsl_thold_in, + din(15) => ary_run_nsl_thold_in, + din(16) => ary_slp_nsl_thold_in, + din(17) => rtim_sl_thold_in, + q( 0) => pc_pc_gptr_sl_thold_4, + q( 1) => pc_pc_time_sl_thold_4, + q( 2) => pc_pc_repr_sl_thold_4, + q( 3) => pc_pc_cfg_sl_thold_4, + q( 4) => pc_pc_cfg_slp_sl_thold_4, + q( 5) => pc_pc_abst_sl_thold_4, + q( 6) => pc_pc_abst_slp_sl_thold_4, + q( 7) => pc_pc_regf_sl_thold_4, + q( 8) => pc_pc_regf_slp_sl_thold_4, + q( 9) => pc_pc_func_sl_thold_4(0), + q(10) => pc_pc_func_sl_thold_4(1), + q(11) => pc_pc_func_slp_sl_thold_4(0), + q(12) => pc_pc_func_slp_sl_thold_4(1), + q(13) => pc_pc_func_nsl_thold_4, + q(14) => pc_pc_func_slp_nsl_thold_4, + q(15) => pc_pc_ary_nsl_thold_4, + q(16) => pc_pc_ary_slp_nsl_thold_4, + q(17) => pc_pc_rtim_sl_thold_4 + ); + +end pcq_clks_ctrl; diff --git a/rel/src/vhdl/work/pcq_clks_stg.vhdl b/rel/src/vhdl/work/pcq_clks_stg.vhdl new file mode 100644 index 0000000..9243b76 --- /dev/null +++ b/rel/src/vhdl/work/pcq_clks_stg.vhdl @@ -0,0 +1,721 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- +-- Description: Pervasive Core LCB Staging +-- +--***************************************************************************** + +library ieee; +use ieee.std_logic_1164.all; +library support; +use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity pcq_clks_stg is +generic(expand_type : integer := 2 -- 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) +); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + pc_pc_ccflush_out_dc : in std_ulogic; + pc_pc_gptr_sl_thold_4 : in std_ulogic; + pc_pc_time_sl_thold_4 : in std_ulogic; + pc_pc_repr_sl_thold_4 : in std_ulogic; + pc_pc_cfg_sl_thold_4 : in std_ulogic; + pc_pc_cfg_slp_sl_thold_4 : in std_ulogic; + pc_pc_abst_sl_thold_4 : in std_ulogic; + pc_pc_abst_slp_sl_thold_4 : in std_ulogic; + pc_pc_regf_sl_thold_4 : in std_ulogic; + pc_pc_regf_slp_sl_thold_4 : in std_ulogic; + pc_pc_func_sl_thold_4 : in std_ulogic_vector(0 to 1); + pc_pc_func_slp_sl_thold_4 : in std_ulogic_vector(0 to 1); + pc_pc_func_nsl_thold_4 : in std_ulogic; + pc_pc_func_slp_nsl_thold_4 : in std_ulogic; + pc_pc_ary_nsl_thold_4 : in std_ulogic; + pc_pc_ary_slp_nsl_thold_4 : in std_ulogic; + pc_pc_rtim_sl_thold_4 : in std_ulogic; + pc_pc_sg_4 : in std_ulogic_vector(0 to 1); + pc_pc_fce_4 : in std_ulogic_vector(0 to 1); +-- Thold + control from bolton frontend + bolton_enable : in std_ulogic; + bolton_fcshdata : in std_ulogic; + bolton_fcreset : in std_ulogic; + bo_pc_abst_sl_thold_4 : in std_ulogic; + bo_pc_pc_abst_sl_thold_4 : in std_ulogic; + bo_pc_bolt_sl_thold_4 : in std_ulogic; + bo_pc_ary_nsl_thold_4 : in std_ulogic; + bo_pc_func_sl_thold_4 : in std_ulogic; + bo_pc_time_sl_thold_4 : in std_ulogic; + bo_pc_repr_sl_thold_4 : in std_ulogic; + bo_pc_sg_4 : in std_ulogic; +-- --Thold + control outputs to the units + pc_xu_ccflush_dc : out std_ulogic; + pc_xu_gptr_sl_thold_3 : out std_ulogic; + pc_xu_time_sl_thold_3 : out std_ulogic; + pc_xu_repr_sl_thold_3 : out std_ulogic; + pc_xu_abst_sl_thold_3 : out std_ulogic; + pc_xu_abst_slp_sl_thold_3 : out std_ulogic; + pc_xu_bolt_sl_thold_3 : out std_ulogic; + pc_xu_regf_sl_thold_3 : out std_ulogic; + pc_xu_regf_slp_sl_thold_3 : out std_ulogic; + pc_xu_func_sl_thold_3 : out std_ulogic_vector(0 to 4); + pc_xu_func_slp_sl_thold_3 : out std_ulogic_vector(0 to 4); + pc_xu_cfg_sl_thold_3 : out std_ulogic; + pc_xu_cfg_slp_sl_thold_3 : out std_ulogic; + pc_xu_func_nsl_thold_3 : out std_ulogic; + pc_xu_func_slp_nsl_thold_3 : out std_ulogic; + pc_xu_ary_nsl_thold_3 : out std_ulogic; + pc_xu_ary_slp_nsl_thold_3 : out std_ulogic; + pc_xu_sg_3 : out std_ulogic_vector(0 to 4); + pc_xu_fce_3 : out std_ulogic_vector(0 to 1); + pc_bx_ccflush_dc : out std_ulogic; + pc_bx_func_sl_thold_3 : out std_ulogic; + pc_bx_func_slp_sl_thold_3 : out std_ulogic; + pc_bx_gptr_sl_thold_3 : out std_ulogic; + pc_bx_time_sl_thold_3 : out std_ulogic; + pc_bx_repr_sl_thold_3 : out std_ulogic; + pc_bx_abst_sl_thold_3 : out std_ulogic; + pc_bx_bolt_sl_thold_3 : out std_ulogic; + pc_bx_ary_nsl_thold_3 : out std_ulogic; + pc_bx_ary_slp_nsl_thold_3 : out std_ulogic; + pc_bx_sg_3 : out std_ulogic; + pc_mm_ccflush_dc : out std_ulogic; + pc_iu_ccflush_dc : out std_ulogic; + pc_iu_gptr_sl_thold_4 : out std_ulogic; + pc_iu_time_sl_thold_4 : out std_ulogic; + pc_iu_repr_sl_thold_4 : out std_ulogic; + pc_iu_abst_sl_thold_4 : out std_ulogic; + pc_iu_abst_slp_sl_thold_4 : out std_ulogic; + pc_iu_bolt_sl_thold_4 : out std_ulogic; + pc_iu_regf_slp_sl_thold_4 : out std_ulogic; + pc_iu_func_sl_thold_4 : out std_ulogic; + pc_iu_func_slp_sl_thold_4 : out std_ulogic; + pc_iu_cfg_sl_thold_4 : out std_ulogic; + pc_iu_cfg_slp_sl_thold_4 : out std_ulogic; + pc_iu_func_nsl_thold_4 : out std_ulogic; + pc_iu_func_slp_nsl_thold_4 : out std_ulogic; + pc_iu_ary_nsl_thold_4 : out std_ulogic; + pc_iu_ary_slp_nsl_thold_4 : out std_ulogic; + pc_iu_sg_4 : out std_ulogic; + pc_iu_fce_4 : out std_ulogic; + pc_fu_ccflush_dc : out std_ulogic; + pc_fu_gptr_sl_thold_3 : out std_ulogic; + pc_fu_time_sl_thold_3 : out std_ulogic; + pc_fu_repr_sl_thold_3 : out std_ulogic; + pc_fu_abst_sl_thold_3 : out std_ulogic; + pc_fu_abst_slp_sl_thold_3 : out std_ulogic; + pc_fu_bolt_sl_thold_3 : out std_ulogic; + pc_fu_func_sl_thold_3 : out std_ulogic_vector(0 to 1); + pc_fu_func_slp_sl_thold_3 : out std_ulogic_vector(0 to 1); + pc_fu_cfg_sl_thold_3 : out std_ulogic; + pc_fu_cfg_slp_sl_thold_3 : out std_ulogic; + pc_fu_func_nsl_thold_3 : out std_ulogic; + pc_fu_func_slp_nsl_thold_3 : out std_ulogic; + pc_fu_ary_nsl_thold_3 : out std_ulogic; + pc_fu_ary_slp_nsl_thold_3 : out std_ulogic; + pc_fu_sg_3 : out std_ulogic_vector(0 to 1); + pc_fu_fce_3 : out std_ulogic; + pc_pc_ccflush_dc : out std_ulogic; + pc_pc_gptr_sl_thold_0 : out std_ulogic; + pc_pc_abst_sl_thold_0 : out std_ulogic; + pc_pc_bolt_sl_thold_0 : out std_ulogic; + pc_pc_func_sl_thold_0 : out std_ulogic; + pc_pc_func_slp_sl_thold_0 : out std_ulogic; + pc_pc_cfg_sl_thold_0 : out std_ulogic; + pc_pc_cfg_slp_sl_thold_0 : out std_ulogic; + pc_pc_sg_0 : out std_ulogic +); + + +-- synopsys translate_off + +-- synopsys translate_on +end pcq_clks_stg; + +architecture pcq_clks_stg of pcq_clks_stg is +signal pc_pc_gptr_sl_thold_3 : std_ulogic; +signal pc_pc_abst_sl_thold_3 : std_ulogic; +signal pc_pc_bolt_sl_thold_3 : std_ulogic; +signal pc_pc_func_sl_thold_3 : std_ulogic; +signal pc_pc_func_slp_sl_thold_3 : std_ulogic; +signal pc_pc_cfg_slp_sl_thold_3 : std_ulogic; +signal pc_pc_cfg_sl_thold_3 : std_ulogic; +signal pc_pc_sg_3 : std_ulogic; +signal pc_pc_gptr_sl_thold_2 : std_ulogic; +signal pc_pc_abst_sl_thold_2 : std_ulogic; +signal pc_pc_bolt_sl_thold_2 : std_ulogic; +signal pc_pc_func_sl_thold_2 : std_ulogic; +signal pc_pc_func_slp_sl_thold_2 : std_ulogic; +signal pc_pc_cfg_slp_sl_thold_2 : std_ulogic; +signal pc_pc_cfg_sl_thold_2 : std_ulogic; +signal pc_pc_sg_2 : std_ulogic; +signal pc_pc_gptr_sl_thold_1 : std_ulogic; +signal pc_pc_abst_sl_thold_1 : std_ulogic; +signal pc_pc_bolt_sl_thold_1 : std_ulogic; +signal pc_pc_func_sl_thold_1 : std_ulogic; +signal pc_pc_func_slp_sl_thold_1 : std_ulogic; +signal pc_pc_cfg_slp_sl_thold_1 : std_ulogic; +signal pc_pc_cfg_sl_thold_1 : std_ulogic; +signal pc_pc_sg_1 : std_ulogic; +signal pc_pc_sg_4_int : std_ulogic_vector(0 to 1); +signal pc_pc_time_sl_thold_4_int : std_ulogic; +signal pc_pc_repr_sl_thold_4_int : std_ulogic; +signal bo_pc_abst_sl_thold_4_int : std_ulogic; +signal pc_pc_abst_sl_thold_4_int : std_ulogic; +signal pc_pc_abst_slp_sl_thold_4_int : std_ulogic; +signal pc_pc_regf_sl_thold_4_int : std_ulogic; +signal pc_pc_regf_slp_sl_thold_4_int : std_ulogic; +signal pc_pc_ary_nsl_thold_4_int : std_ulogic; +signal pc_pc_ary_slp_nsl_thold_4_int : std_ulogic; +signal pc_pc_func_sl_thold_4_int : std_ulogic_vector(0 to 1); +signal pc_pc_bolt_sl_thold_4_int : std_ulogic; +signal pc_pc_func_slp_sl_thold_4_int : std_ulogic_vector(0 to 1); +signal pc_pc_func_nsl_thold_4_int : std_ulogic; +signal pc_pc_func_slp_nsl_thold_4_int : std_ulogic; +signal unused_signals : std_ulogic; + + +begin + + unused_signals <= pc_pc_rtim_sl_thold_4; + + +-- Other units use ccflush signal gated for power-savings operation + pc_xu_ccflush_dc <= pc_pc_ccflush_out_dc; + pc_bx_ccflush_dc <= pc_pc_ccflush_out_dc; + pc_iu_ccflush_dc <= pc_pc_ccflush_out_dc; + pc_fu_ccflush_dc <= pc_pc_ccflush_out_dc; + pc_mm_ccflush_dc <= pc_pc_ccflush_out_dc; + pc_pc_ccflush_dc <= pc_pc_ccflush_out_dc; + + +--===================================================================== +-- Gate in bolt-on thold/sg controls when bolt-on ABIST enabled +--===================================================================== +pc_pc_sg_4_int(0) <= bo_pc_sg_4 or bolton_fcshdata when bolton_enable='1' else pc_pc_sg_4(0); +pc_pc_sg_4_int(1) <= bo_pc_sg_4 or bolton_fcshdata when bolton_enable='1' else pc_pc_sg_4(1); + +pc_pc_func_sl_thold_4_int(0) <= bo_pc_func_sl_thold_4 when bolton_enable='1' else pc_pc_func_sl_thold_4(0); +pc_pc_func_sl_thold_4_int(1) <= bo_pc_func_sl_thold_4 when bolton_enable='1' else pc_pc_func_sl_thold_4(1); +pc_pc_func_slp_sl_thold_4_int(0) <= bo_pc_func_sl_thold_4 when bolton_enable='1' else pc_pc_func_slp_sl_thold_4(0); +pc_pc_func_slp_sl_thold_4_int(1) <= bo_pc_func_sl_thold_4 when bolton_enable='1' else pc_pc_func_slp_sl_thold_4(1); + +pc_pc_func_nsl_thold_4_int <= bo_pc_func_sl_thold_4 when bolton_enable='1' else pc_pc_func_nsl_thold_4; +pc_pc_func_slp_nsl_thold_4_int <= bo_pc_func_sl_thold_4 when bolton_enable='1' else pc_pc_func_slp_nsl_thold_4; + +pc_pc_time_sl_thold_4_int <= bo_pc_time_sl_thold_4 when bolton_enable='1' else pc_pc_time_sl_thold_4; + +pc_pc_repr_sl_thold_4_int <= bo_pc_bolt_sl_thold_4 when (bolton_fcshdata or bolton_fcreset)='1' and bolton_enable='1' else + bo_pc_repr_sl_thold_4 when bolton_enable='1' else + pc_pc_repr_sl_thold_4; + +pc_pc_abst_sl_thold_4_int <= bo_pc_abst_sl_thold_4 when bolton_enable='1' else pc_pc_abst_sl_thold_4; +bo_pc_abst_sl_thold_4_int <= bo_pc_pc_abst_sl_thold_4 when bolton_enable='1' else pc_pc_abst_sl_thold_4; +pc_pc_abst_slp_sl_thold_4_int <= bo_pc_abst_sl_thold_4 when bolton_enable='1' else pc_pc_abst_slp_sl_thold_4; + +pc_pc_regf_sl_thold_4_int <= pc_pc_regf_sl_thold_4; +pc_pc_regf_slp_sl_thold_4_int <= pc_pc_regf_slp_sl_thold_4; + +pc_pc_ary_nsl_thold_4_int <= bo_pc_ary_nsl_thold_4 when bolton_enable='1' else pc_pc_ary_nsl_thold_4; +pc_pc_ary_slp_nsl_thold_4_int <= bo_pc_ary_nsl_thold_4 when bolton_enable='1' else pc_pc_ary_slp_nsl_thold_4; + +pc_pc_bolt_sl_thold_4_int <= bo_pc_bolt_sl_thold_4 when bolton_enable='1' else pc_pc_abst_sl_thold_4; + + +--===================================================================== +-- LCB control signals staged/redriven to other units +--===================================================================== +-- IU and MMU thold/SG/FCE exits PCQ at level 4. +-- The Level 4 to level 3 staging has been moved to the IU RP unit for timing. +pc_iu_gptr_sl_thold_4 <= pc_pc_gptr_sl_thold_4; +pc_iu_time_sl_thold_4 <= pc_pc_time_sl_thold_4_int; +pc_iu_repr_sl_thold_4 <= pc_pc_repr_sl_thold_4_int; +pc_iu_abst_sl_thold_4 <= pc_pc_abst_sl_thold_4_int; +pc_iu_abst_slp_sl_thold_4 <= pc_pc_abst_slp_sl_thold_4_int; +pc_iu_bolt_sl_thold_4 <= pc_pc_bolt_sl_thold_4_int; +pc_iu_regf_slp_sl_thold_4 <= pc_pc_regf_slp_sl_thold_4_int; +pc_iu_func_sl_thold_4 <= pc_pc_func_sl_thold_4_int(1); +pc_iu_func_slp_sl_thold_4 <= pc_pc_func_slp_sl_thold_4_int(1); +pc_iu_cfg_sl_thold_4 <= pc_pc_cfg_sl_thold_4; +pc_iu_cfg_slp_sl_thold_4 <= pc_pc_cfg_slp_sl_thold_4; +pc_iu_func_nsl_thold_4 <= pc_pc_func_nsl_thold_4_int; +pc_iu_func_slp_nsl_thold_4 <= pc_pc_func_slp_nsl_thold_4_int; +pc_iu_ary_nsl_thold_4 <= pc_pc_ary_nsl_thold_4_int; +pc_iu_ary_slp_nsl_thold_4 <= pc_pc_ary_slp_nsl_thold_4_int; +pc_iu_sg_4 <= pc_pc_sg_4_int(1); +pc_iu_fce_4 <= pc_pc_fce_4(1); + + +-- Start of XU thold/SG/FCE staging (level 4 to level 3) +xu_func_stg4to3: tri_plat + generic map( width => 14, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_out_dc, + din( 0) => pc_pc_func_sl_thold_4_int(0), + din( 1) => pc_pc_func_sl_thold_4_int(0), + din( 2) => pc_pc_func_sl_thold_4_int(0), + din( 3) => pc_pc_func_sl_thold_4_int(0), + din( 4) => pc_pc_func_sl_thold_4_int(0), + din( 5) => pc_pc_func_slp_sl_thold_4_int(0), + din( 6) => pc_pc_func_slp_sl_thold_4_int(0), + din( 7) => pc_pc_func_slp_sl_thold_4_int(0), + din( 8) => pc_pc_func_slp_sl_thold_4_int(0), + din( 9) => pc_pc_func_slp_sl_thold_4_int(0), + din(10) => pc_pc_cfg_sl_thold_4, + din(11) => pc_pc_cfg_slp_sl_thold_4, + din(12) => pc_pc_func_nsl_thold_4_int, + din(13) => pc_pc_func_slp_nsl_thold_4_int, + q( 0) => pc_xu_func_sl_thold_3(0), + q( 1) => pc_xu_func_sl_thold_3(1), + q( 2) => pc_xu_func_sl_thold_3(2), + q( 3) => pc_xu_func_sl_thold_3(3), + q( 4) => pc_xu_func_sl_thold_3(4), + q( 5) => pc_xu_func_slp_sl_thold_3(0), + q( 6) => pc_xu_func_slp_sl_thold_3(1), + q( 7) => pc_xu_func_slp_sl_thold_3(2), + q( 8) => pc_xu_func_slp_sl_thold_3(3), + q( 9) => pc_xu_func_slp_sl_thold_3(4), + q(10) => pc_xu_cfg_sl_thold_3, + q(11) => pc_xu_cfg_slp_sl_thold_3, + q(12) => pc_xu_func_nsl_thold_3, + q(13) => pc_xu_func_slp_nsl_thold_3 + ); + +xu_ctrl_stg4to3: tri_plat + generic map( width => 8, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_out_dc, + din( 0) => pc_pc_gptr_sl_thold_4, + din( 1) => pc_pc_sg_4_int(0), + din( 2) => pc_pc_sg_4_int(0), + din( 3) => pc_pc_sg_4_int(0), + din( 4) => pc_pc_sg_4_int(0), + din( 5) => pc_pc_sg_4_int(0), + din( 6) => pc_pc_fce_4(0), + din( 7) => pc_pc_fce_4(0), + q( 0) => pc_xu_gptr_sl_thold_3, + q( 1) => pc_xu_sg_3(0), + q( 2) => pc_xu_sg_3(1), + q( 3) => pc_xu_sg_3(2), + q( 4) => pc_xu_sg_3(3), + q( 5) => pc_xu_sg_3(4), + q( 6) => pc_xu_fce_3(0), + q( 7) => pc_xu_fce_3(1) + ); + +xu_arry_stg4to3: tri_plat + generic map( width => 9, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_out_dc, + din( 0) => pc_pc_time_sl_thold_4_int, + din( 1) => pc_pc_repr_sl_thold_4_int, + din( 2) => pc_pc_abst_sl_thold_4_int, + din( 3) => pc_pc_abst_slp_sl_thold_4_int, + din( 4) => pc_pc_bolt_sl_thold_4_int, + din( 5) => pc_pc_regf_sl_thold_4_int, + din( 6) => pc_pc_regf_slp_sl_thold_4_int, + din( 7) => pc_pc_ary_nsl_thold_4_int, + din( 8) => pc_pc_ary_slp_nsl_thold_4_int, + q( 0) => pc_xu_time_sl_thold_3, + q( 1) => pc_xu_repr_sl_thold_3, + q( 2) => pc_xu_abst_sl_thold_3, + q( 3) => pc_xu_abst_slp_sl_thold_3, + q( 4) => pc_xu_bolt_sl_thold_3, + q( 5) => pc_xu_regf_sl_thold_3, + q( 6) => pc_xu_regf_slp_sl_thold_3, + q( 7) => pc_xu_ary_nsl_thold_3, + q( 8) => pc_xu_ary_slp_nsl_thold_3 + ); + + +-- Start of BX thold/SG/FCE staging (level 4 to level 3) +bx_ctrls_stg4to3: tri_plat + generic map( width => 10, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_out_dc, + din( 0) => pc_pc_func_sl_thold_4_int(0), + din( 1) => pc_pc_func_slp_sl_thold_4_int(0), + din( 2) => pc_pc_gptr_sl_thold_4, + din( 3) => pc_pc_time_sl_thold_4_int, + din( 4) => pc_pc_repr_sl_thold_4_int, + din( 5) => pc_pc_abst_sl_thold_4_int, + din( 6) => pc_pc_bolt_sl_thold_4_int, + din( 7) => pc_pc_ary_nsl_thold_4_int, + din( 8) => pc_pc_ary_slp_nsl_thold_4_int, + din( 9) => pc_pc_sg_4_int(0), + q( 0) => pc_bx_func_sl_thold_3, + q( 1) => pc_bx_func_slp_sl_thold_3, + q( 2) => pc_bx_gptr_sl_thold_3, + q( 3) => pc_bx_time_sl_thold_3, + q( 4) => pc_bx_repr_sl_thold_3, + q( 5) => pc_bx_abst_sl_thold_3, + q( 6) => pc_bx_bolt_sl_thold_3, + q( 7) => pc_bx_ary_nsl_thold_3, + q( 8) => pc_bx_ary_slp_nsl_thold_3, + q( 9) => pc_bx_sg_3 + ); + + +-- Start of FU thold/SG/FCE staging (level 4 to level 3) +fu_func_stg4to3: tri_plat + generic map( width => 8, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_out_dc, + din( 0) => pc_pc_func_sl_thold_4_int(1), + din( 1) => pc_pc_func_sl_thold_4_int(1), + din( 2) => pc_pc_func_slp_sl_thold_4_int(1), + din( 3) => pc_pc_func_slp_sl_thold_4_int(1), + din( 4) => pc_pc_cfg_sl_thold_4, + din( 5) => pc_pc_cfg_slp_sl_thold_4, + din( 6) => pc_pc_func_nsl_thold_4_int, + din( 7) => pc_pc_func_slp_nsl_thold_4_int, + q( 0) => pc_fu_func_sl_thold_3(0), + q( 1) => pc_fu_func_sl_thold_3(1), + q( 2) => pc_fu_func_slp_sl_thold_3(0), + q( 3) => pc_fu_func_slp_sl_thold_3(1), + q( 4) => pc_fu_cfg_sl_thold_3, + q( 5) => pc_fu_cfg_slp_sl_thold_3, + q( 6) => pc_fu_func_nsl_thold_3, + q( 7) => pc_fu_func_slp_nsl_thold_3 + ); + +fu_ctrl_stg4to3: tri_plat + generic map( width => 4, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_out_dc, + din( 0) => pc_pc_gptr_sl_thold_4, + din( 1) => pc_pc_sg_4_int(1), + din( 2) => pc_pc_sg_4_int(1), + din( 3) => pc_pc_fce_4(1), + q( 0) => pc_fu_gptr_sl_thold_3, + q( 1) => pc_fu_sg_3(0), + q( 2) => pc_fu_sg_3(1), + q( 3) => pc_fu_fce_3 + ); + +fu_arry_stg4to3: tri_plat + generic map( width => 7, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_out_dc, + din( 0) => pc_pc_time_sl_thold_4_int, + din( 1) => pc_pc_repr_sl_thold_4_int, + din( 2) => pc_pc_abst_sl_thold_4_int, + din( 3) => pc_pc_abst_slp_sl_thold_4_int, + din( 4) => pc_pc_bolt_sl_thold_4_int, + din( 5) => pc_pc_ary_nsl_thold_4_int, + din( 6) => pc_pc_ary_slp_nsl_thold_4_int, + q( 0) => pc_fu_time_sl_thold_3, + q( 1) => pc_fu_repr_sl_thold_3, + q( 2) => pc_fu_abst_sl_thold_3, + q( 3) => pc_fu_abst_slp_sl_thold_3, + q( 4) => pc_fu_bolt_sl_thold_3, + q( 5) => pc_fu_ary_nsl_thold_3, + q( 6) => pc_fu_ary_slp_nsl_thold_3 + ); + + +-- Start of PC thold/SG staging (level 4 to level 3) +pc_func_stg4to3: tri_plat + generic map( width => 4, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_out_dc, + din( 0) => pc_pc_func_sl_thold_4_int(1), + din( 1) => pc_pc_func_slp_sl_thold_4_int(1), + din( 2) => pc_pc_cfg_sl_thold_4, + din( 3) => pc_pc_cfg_slp_sl_thold_4, + q( 0) => pc_pc_func_sl_thold_3, + q( 1) => pc_pc_func_slp_sl_thold_3, + q( 2) => pc_pc_cfg_sl_thold_3, + q( 3) => pc_pc_cfg_slp_sl_thold_3 + ); + +pc_ctrl_stg4to3: tri_plat + generic map( width => 4, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_out_dc, + din( 0) => pc_pc_gptr_sl_thold_4, + din( 1) => bo_pc_abst_sl_thold_4_int, + din( 2) => pc_pc_bolt_sl_thold_4_int, + din( 3) => pc_pc_sg_4_int(1), + q( 0) => pc_pc_gptr_sl_thold_3, + q( 1) => pc_pc_abst_sl_thold_3, + q( 2) => pc_pc_bolt_sl_thold_3, + q( 3) => pc_pc_sg_3 + ); +-- End of thold/SG/FCE staging (level 4 to level 3) + + +--===================================================================== +-- thold/SG staging (level 3 to level 0) for PC units +--===================================================================== +------------------------------------------------------ +-- FUNC (RUN) +------------------------------------------------------ +func_3_2: tri_plat + generic map( width => 1, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_out_dc, + din(0) => pc_pc_func_sl_thold_3, + q(0) => pc_pc_func_sl_thold_2 + ); +func_2_1: tri_plat + generic map( width => 1, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_out_dc, + din(0) => pc_pc_func_sl_thold_2, + q(0) => pc_pc_func_sl_thold_1 + ); +func_1_0: tri_plat + generic map( width => 1, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_out_dc, + din(0) => pc_pc_func_sl_thold_1, + q(0) => pc_pc_func_sl_thold_0 + ); + +------------------------------------------------------ +-- FUNC (SLEEP) +------------------------------------------------------ +func_slp_3_2: tri_plat + generic map( width => 1, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_out_dc, + din(0) => pc_pc_func_slp_sl_thold_3, + q(0) => pc_pc_func_slp_sl_thold_2 + ); +func_slp_2_1: tri_plat + generic map( width => 1, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_out_dc, + din(0) => pc_pc_func_slp_sl_thold_2, + q(0) => pc_pc_func_slp_sl_thold_1 + ); +func_slp_1_0: tri_plat + generic map( width => 1, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_out_dc, + din(0) => pc_pc_func_slp_sl_thold_1, + q(0) => pc_pc_func_slp_sl_thold_0 + ); + +------------------------------------------------------ +-- CFG (RUN) +------------------------------------------------------ +cfg_3_2: tri_plat + generic map( width => 1, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_out_dc, + din(0) => pc_pc_cfg_sl_thold_3, + q(0) => pc_pc_cfg_sl_thold_2 + ); +cfg_2_1: tri_plat + generic map( width => 1, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_out_dc, + din(0) => pc_pc_cfg_sl_thold_2, + q(0) => pc_pc_cfg_sl_thold_1 + ); +cfg_1_0: tri_plat + generic map( width => 1, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_out_dc, + din(0) => pc_pc_cfg_sl_thold_1, + q(0) => pc_pc_cfg_sl_thold_0 + ); + +------------------------------------------------------ +-- CFG (SLEEP) +------------------------------------------------------ +cfg_slp_3_2: tri_plat + generic map( width => 1, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_out_dc, + din(0) => pc_pc_cfg_slp_sl_thold_3, + q(0) => pc_pc_cfg_slp_sl_thold_2 + ); +cfg_slp_2_1: tri_plat + generic map( width => 1, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_out_dc, + din(0) => pc_pc_cfg_slp_sl_thold_2, + q(0) => pc_pc_cfg_slp_sl_thold_1 + ); +cfg_slp_1_0: tri_plat + generic map( width => 1, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_out_dc, + din(0) => pc_pc_cfg_slp_sl_thold_1, + q(0) => pc_pc_cfg_slp_sl_thold_0 + ); + +------------------------------------------------------ +-- ABST +------------------------------------------------------ +abst_3_2: tri_plat + generic map( width => 2, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_out_dc, + din(0) => pc_pc_abst_sl_thold_3, + din(1) => pc_pc_bolt_sl_thold_3, + q(0) => pc_pc_abst_sl_thold_2, + q(1) => pc_pc_bolt_sl_thold_2 + ); +abst_2_1: tri_plat + generic map( width => 2, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_out_dc, + din(0) => pc_pc_abst_sl_thold_2, + din(1) => pc_pc_bolt_sl_thold_2, + q(0) => pc_pc_abst_sl_thold_1, + q(1) => pc_pc_bolt_sl_thold_1 + ); +abst_1_0: tri_plat + generic map( width => 2, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_out_dc, + din(0) => pc_pc_abst_sl_thold_1, + din(1) => pc_pc_bolt_sl_thold_1, + q(0) => pc_pc_abst_sl_thold_0, + q(1) => pc_pc_bolt_sl_thold_0 + ); + +------------------------------------------------------ +-- GPTR +------------------------------------------------------ +gptr_3_2: tri_plat + generic map( width => 1, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_out_dc, + din(0) => pc_pc_gptr_sl_thold_3, + q(0) => pc_pc_gptr_sl_thold_2 + ); +gptr_2_1: tri_plat + generic map( width => 1, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_out_dc, + din(0) => pc_pc_gptr_sl_thold_2, + q(0) => pc_pc_gptr_sl_thold_1 + ); +gptr_1_0: tri_plat + generic map( width => 1, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_out_dc, + din(0) => pc_pc_gptr_sl_thold_1, + q(0) => pc_pc_gptr_sl_thold_0 + ); + +------------------------------------------------------ +-- SG +------------------------------------------------------ +sg_3_2: tri_plat + generic map( width => 1, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_out_dc, + din(0) => pc_pc_sg_3, + q(0) => pc_pc_sg_2 + ); +sg_2_1: tri_plat + generic map( width => 1, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_out_dc, + din(0) => pc_pc_sg_2, + q(0) => pc_pc_sg_1 + ); +sg_1_0: tri_plat + generic map( width => 1, expand_type => expand_type) + port map( vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_pc_ccflush_out_dc, + din(0) => pc_pc_sg_1, + q(0) => pc_pc_sg_0 + ); + + +end pcq_clks_stg; diff --git a/rel/src/vhdl/work/pcq_ctrl.vhdl b/rel/src/vhdl/work/pcq_ctrl.vhdl new file mode 100644 index 0000000..4453da1 --- /dev/null +++ b/rel/src/vhdl/work/pcq_ctrl.vhdl @@ -0,0 +1,452 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- +-- Description: Pervasive Core Thread Controls +-- +--***************************************************************************** + +library ieee; +use ieee.std_logic_1164.all; +library ibm; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; +library support; +use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity pcq_ctrl is +generic(expand_type : integer := 2 -- 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) +); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + scan_dis_dc_b : in std_ulogic; + lcb_clkoff_dc_b : in std_ulogic; + lcb_mpw1_dc_b : in std_ulogic; + lcb_mpw2_dc_b : in std_ulogic; + lcb_delay_lclkr_dc : in std_ulogic; + lcb_act_dis_dc : in std_ulogic; + pc_pc_func_slp_sl_thold_0 : in std_ulogic; + pc_pc_sg_0 : in std_ulogic; + func_scan_in : in std_ulogic; + func_scan_out : out std_ulogic; +-- Reset Related + an_ac_reset_1_complete : in std_ulogic; + an_ac_reset_2_complete : in std_ulogic; + an_ac_reset_3_complete : in std_ulogic; + an_ac_reset_wd_complete : in std_ulogic; + pc_xu_reset_1_cmplt : out std_ulogic; + pc_xu_reset_2_cmplt : out std_ulogic; + pc_xu_reset_3_cmplt : out std_ulogic; + pc_xu_reset_wd_cmplt : out std_ulogic; + pc_xu_init_reset : out std_ulogic; + pc_iu_init_reset : out std_ulogic; + ct_rg_hold_during_init : out std_ulogic; +-- Power Management + ct_rg_power_managed : out std_ulogic_vector(0 to 3); + ct_rg_pm_thread_stop : out std_ulogic_vector(0 to 3); + an_ac_pm_thread_stop : in std_ulogic_vector(0 to 3); + ac_an_power_managed : out std_ulogic; + ac_an_rvwinkle_mode : out std_ulogic; + ct_ck_pm_ccflush_disable : out std_ulogic; + ct_ck_pm_raise_tholds : out std_ulogic; + rg_ct_dis_pwr_savings : in std_ulogic; + xu_pc_spr_ccr0_pme : in std_ulogic_vector(0 to 1); + xu_pc_spr_ccr0_we : in std_ulogic_vector(0 to 3); +-- Trace/Trigger Signals + dbg_ctrls : out std_ulogic_vector(0 to 36) +); +-- synopsys translate_off + + +-- synopsys translate_on +end pcq_ctrl; + +architecture pcq_ctrl of pcq_ctrl is +--===================================================================== +-- Signal Declarations +--===================================================================== +constant initactive_size : positive := 1; +constant resetsm_size : positive := 5; +constant initerat_size : positive := 1; +constant pmstate_size : positive := 14; +constant sprccr0_size : positive := 6; +constant pmstop_size : positive := 4; +constant resetstat_size : positive := 4; +constant sparectrl_size : positive := 6; + +----------------------------------------------------------------------- +-- Scan Ring Ordering: +-- start of func scan chain ordering +constant initactive_offset : natural := 0; +constant resetsm_offset : natural := initactive_offset + initactive_size; +constant initerat_offset : natural := resetsm_offset + resetsm_size; +constant pmstate_offset : natural := initerat_offset + initerat_size; +constant sprccr0_offset : natural := pmstate_offset + pmstate_size; +constant pmstop_offset : natural := sprccr0_offset + sprccr0_size; +constant resetstat_offset : natural := pmstop_offset + pmstop_size; +constant sparectrl_offset : natural := resetstat_offset + resetstat_size; +constant func_right : natural := sparectrl_offset + sparectrl_size - 1; +-- end of func scan chain ordering + +----------------------------------------------------------------------- +-- Reset State Machine: +constant ResSM_Idle : std_ulogic_vector(0 to 4) := "00000"; +constant ResSM_Start : std_ulogic_vector(0 to 4) := "00001"; +constant ResSM_InitErat : std_ulogic_vector(0 to 4) := "00111"; +constant ResSM_Return : std_ulogic_vector(0 to 4) := "10111"; + +----------------------------------------------------------------------- +-- Basic/Misc signals +signal tiup : std_ulogic; +signal func_siv, func_sov : std_ulogic_vector(0 to func_right); +signal pc_pc_func_slp_sl_thold_0_b : std_ulogic; +signal force_funcslp : std_ulogic; +-- Reset Signals +signal resetsm_active : std_ulogic; +signal resetsm_act_ctrl : std_ulogic; +-- Power management Signals +signal spr_ccr0_pme_q : std_ulogic_vector(0 to 1); +signal spr_ccr0_we_q : std_ulogic_vector(0 to 3); +signal pm_sleep_enable : std_ulogic; +signal pm_rvw_enable : std_ulogic; +signal thread_stopped : std_ulogic_vector(0 to 3); +-- Latch definitions begin +signal resetsm_d, resetsm_q : std_ulogic_vector(0 to resetsm_size-1); +signal init_active_d, init_active_q : std_ulogic; +signal initerat_d, initerat_q : std_ulogic; +signal pmstate_d, pmstate_q : std_ulogic_vector(0 to 3); +signal pmstate_all_d, pmstate_all_q : std_ulogic; +signal pmclkctrl_dly_d, pmclkctrl_dly_q : std_ulogic_vector(0 to 7); +signal rvwinkled_d, rvwinkled_q : std_ulogic; +signal pmstop_q : std_ulogic_vector(0 to pmstop_size-1); +signal reset_complete_q : std_ulogic_vector(0 to resetstat_size-1); +signal pm_ccflush_disable_int : std_ulogic; +signal pm_raise_tholds_int : std_ulogic; +signal spare_ctrl_wrapped_q : std_ulogic_vector(0 to sparectrl_size-1); + + +begin + + +tiup <= '1'; + + +--===================================================================== +-- Reset State Machine +--===================================================================== + -- Counter used to generate reset control pulses. + -- Starts when clocks start because init_active_q inits to 1. + -- Keeps counting until init_active_q is reset, then returns to Idle state. + resetsm_d <= (others=>'0') when (resetsm_q=ResSM_Idle and init_active_q='0') else + ResSM_Start when (resetsm_q=ResSM_Idle and init_active_q='1') else + ResSM_Idle when init_active_q='0' else + resetsm_q + "00001"; + + resetsm_active <= or_reduce(resetsm_q); + resetsm_act_ctrl <= init_active_q or resetsm_active; + + -- The initerat latch controls the init_reset signals to IU and XU. + -- Goes active when ResSM=8. Goes inactive 16 clock cycles later when ResSM returns to Idle. + initerat_d <= '0' when resetsm_q=ResSM_Idle else + '0' when resetsm_q=ResSM_Return else + '1' when resetsm_q=ResSM_InitErat else + initerat_q; + + -- init_active_q initializes to '1'; cleared when Reset_SM count completes (ResSM >= 24). + init_active_d <= '0' when resetsm_q(0 to 1)="11" else init_active_q; + + +--===================================================================== +-- Power Management Latches +--===================================================================== + -- XU signals indicate when power-savings is enabled (sleep or rvw modes), and which + -- threads are stopped. + -- The pmstate latch tracks which threads are stopped when either power-savings mode + -- is enabled. The rvwinkled latch only when pm_rvw_enable is set. + -- If all threads are stopped when power-savings is enabled, then signals to the + -- clock control macro will initiate power savings actions. These controls force + -- ccflush_dc inactive to ensure all PLATs are clocking. After a delay period, the + -- run tholds will be raised to stop clocks. + -- When coming out of power-savings, the tholds will be disabled prior to deactivating + -- ccflush_dc. + pm_sleep_enable <= not spr_ccr0_pme_q(0) and spr_ccr0_pme_q(1); + + pm_rvw_enable <= spr_ccr0_pme_q(0) and not spr_ccr0_pme_q(1); + + thread_stopped <= spr_ccr0_we_q; + + + + pmstate_d <= gate_and((pm_sleep_enable or pm_rvw_enable) and not resetsm_active, + thread_stopped(0 to 3)); + + pmstate_all_d <= and_reduce(pmstate_q); + + pmclkctrl_dly_d(0 to 7) <= pmstate_all_q & pmclkctrl_dly_q(0 to 6); + + rvwinkled_d <= pmclkctrl_dly_q(6) and pm_rvw_enable; + + +--===================================================================== +-- Outputs +--===================================================================== + -- Used as part of thread stop signal to XU. + -- Keeps threads stopped until after the Reset SM completes count. + ct_rg_hold_during_init <= init_active_q; + + -- Init pulse to IU and XU to force initialization of I/D-ERATs. + -- IU also holds instruction fetch until init signal released. + pc_iu_init_reset <= initerat_q; + pc_xu_init_reset <= initerat_q; + + -- Software initiated reset status to XU for DBSR[MRR] and TSR[WRS] + pc_xu_reset_1_cmplt <= reset_complete_q(0); + pc_xu_reset_2_cmplt <= reset_complete_q(1); + pc_xu_reset_3_cmplt <= reset_complete_q(2); + pc_xu_reset_wd_cmplt <= reset_complete_q(3); + + -- To THRCTL[Tx_PM]; indicates core power-managed due to external input. + ct_rg_pm_thread_stop <= pmstop_q; + + -- To THRCTL[Tx_PM]; indicates core power-managed via software actions. + ct_rg_power_managed <= pmstate_q; + + -- Core in rvwinkle power-savings state. L2 can prepare for Chiplet power-down. + ac_an_rvwinkle_mode <= rvwinkled_q; + -- Core in power-savings state due to any combination of power-savings instructions + ac_an_power_managed <= pmclkctrl_dly_q(7); + + -- Goes to clock controls to disable plat flush controls + pm_ccflush_disable_int <= pmstate_all_q or pmclkctrl_dly_q(7); + ct_ck_pm_ccflush_disable <= pm_ccflush_disable_int and not rg_ct_dis_pwr_savings; + -- Goes to clock controls to activate run tholds + pm_raise_tholds_int <= pmstate_all_q and pmclkctrl_dly_q(7); + ct_ck_pm_raise_tholds <= pm_raise_tholds_int and not rg_ct_dis_pwr_savings; + + +--===================================================================== +-- Trace/Trigger Signals +--===================================================================== + dbg_ctrls <= init_active_q & -- 0 + resetsm_q(0 to 4) & -- 1:5 + initerat_q & -- 6 + reset_complete_q(0 to 3) & -- 7:10 + pmstop_q(0 to 3) & -- 11:14 + pmstate_q(0 to 3) & -- 15:18 + rvwinkled_q & -- 19 + spr_ccr0_pme_q(0 to 1) & -- 20:21 + spr_ccr0_we_q(0 to 3) & -- 22:25 + pmclkctrl_dly_q(0 to 7) & -- 26:33 + rg_ct_dis_pwr_savings & -- 34 + pm_ccflush_disable_int & -- 35 + pm_raise_tholds_int ; -- 36 + + +--===================================================================== +-- Latches +--===================================================================== +-- func ring registers start +initactive: tri_rlmlatch_p + generic map (init => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_pc_func_slp_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_funcslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(initactive_offset), + scout => func_sov(initactive_offset), + din => init_active_d, + dout => init_active_q); + +resetsm: tri_rlmreg_p + generic map (width => resetsm_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => resetsm_act_ctrl, + thold_b => pc_pc_func_slp_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_funcslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(resetsm_offset to resetsm_offset + resetsm_size-1), + scout => func_sov(resetsm_offset to resetsm_offset + resetsm_size-1), + din => resetsm_d, + dout => resetsm_q ); + +initerat: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => resetsm_active, + thold_b => pc_pc_func_slp_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_funcslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(initerat_offset), + scout => func_sov(initerat_offset), + din => initerat_d, + dout => initerat_q ); + +pmstate: tri_rlmreg_p + generic map (width => pmstate_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_pc_func_slp_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_funcslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(pmstate_offset to pmstate_offset + pmstate_size-1), + scout => func_sov(pmstate_offset to pmstate_offset + pmstate_size-1), + din(0 to 3) => pmstate_d, + din(4) => pmstate_all_d, + din(5) => rvwinkled_d, + din(6 to 13) => pmclkctrl_dly_d, + dout(0 to 3) => pmstate_q, + dout(4) => pmstate_all_q, + dout(5) => rvwinkled_q, + dout(6 to 13) => pmclkctrl_dly_q ); + +sprccr0: tri_rlmreg_p + generic map (width => sprccr0_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_pc_func_slp_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_funcslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(sprccr0_offset to sprccr0_offset + sprccr0_size-1), + scout => func_sov(sprccr0_offset to sprccr0_offset + sprccr0_size-1), + din(0 to 1) => xu_pc_spr_ccr0_pme, + din(2 to 5) => xu_pc_spr_ccr0_we, + dout(0 to 1) => spr_ccr0_pme_q, + dout(2 to 5) => spr_ccr0_we_q ); + +pmstop: tri_rlmreg_p + generic map (width => pmstop_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_pc_func_slp_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_funcslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(pmstop_offset to pmstop_offset + pmstop_size-1), + scout => func_sov(pmstop_offset to pmstop_offset + pmstop_size-1), + din => an_ac_pm_thread_stop, + dout => pmstop_q ); + +resetstat: tri_rlmreg_p + generic map (width => resetstat_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_pc_func_slp_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_funcslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(resetstat_offset to resetstat_offset + resetstat_size-1), + scout => func_sov(resetstat_offset to resetstat_offset + resetstat_size-1), + din(0) => an_ac_reset_1_complete, + din(1) => an_ac_reset_2_complete, + din(2) => an_ac_reset_3_complete, + din(3) => an_ac_reset_wd_complete, + dout => reset_complete_q ); + +sparectrl: tri_rlmreg_p + generic map (width => sparectrl_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_pc_func_slp_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_funcslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(sparectrl_offset to sparectrl_offset + sparectrl_size-1), + scout => func_sov(sparectrl_offset to sparectrl_offset + sparectrl_size-1), + din => spare_ctrl_wrapped_q, + dout => spare_ctrl_wrapped_q ); +-- func ring registers end + + +--===================================================================== +-- Thold/SG Staging +--===================================================================== +-- func_slp lcbor +lcbor_funcslp: tri_lcbor +generic map (expand_type => expand_type ) +port map ( + clkoff_b => lcb_clkoff_dc_b, + thold => pc_pc_func_slp_sl_thold_0, + sg => pc_pc_sg_0, + act_dis => lcb_act_dis_dc, + forcee => force_funcslp, + thold_b => pc_pc_func_slp_sl_thold_0_b ); + + +--===================================================================== +-- Scan Connections +--===================================================================== +-- Func ring +func_siv(0 TO func_right) <= func_scan_in & func_sov(0 to func_right-1); +func_scan_out <= func_sov(func_right) and scan_dis_dc_b; + + +----------------------------------------------------------------------- +end pcq_ctrl; diff --git a/rel/src/vhdl/work/pcq_dbg.vhdl b/rel/src/vhdl/work/pcq_dbg.vhdl new file mode 100644 index 0000000..b732b80 --- /dev/null +++ b/rel/src/vhdl/work/pcq_dbg.vhdl @@ -0,0 +1,864 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- +-- Description: Pervasive Core Debug/Event Bus Controls +-- +--***************************************************************************** + +library ieee; +use ieee.std_logic_1164.all; +library ibm,clib; +use ibm.std_ulogic_function_support.all; +library support; +use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity pcq_dbg is +generic(expand_type : integer := 2 -- 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) +); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + scan_dis_dc_b : in std_ulogic; + lcb_clkoff_dc_b : in std_ulogic; + lcb_mpw1_dc_b : in std_ulogic; + lcb_mpw2_dc_b : in std_ulogic; + lcb_delay_lclkr_dc : in std_ulogic; + lcb_act_dis_dc : in std_ulogic; + pc_pc_func_slp_sl_thold_0 : in std_ulogic; + pc_pc_sg_0 : in std_ulogic; + func_scan_in : in std_ulogic; + func_scan_out : out std_ulogic; +-- Trace/Trigger Bus + debug_bus_out : out std_ulogic_vector(0 to 87); + trace_triggers_out : out std_ulogic_vector(0 to 11); + debug_bus_in : in std_ulogic_vector(0 to 87); + trace_triggers_in : in std_ulogic_vector(0 to 11); + rg_db_trace_bus_enable : in std_ulogic; + rg_db_debug_mux_ctrls : in std_ulogic_vector(0 to 15); + --PC Unit internal debug signals + ck_db_dbg_clks_ctrls : in std_ulogic_vector(0 to 13); + rg_db_dbg_scom_rdata : in std_ulogic_vector(0 to 63); + rg_db_dbg_scom_wdata : in std_ulogic_vector(0 to 63); + rg_db_dbg_scom_decaddr : in std_ulogic_vector(0 to 63); + rg_db_dbg_scom_misc : in std_ulogic_vector(0 to 8); + rg_db_dbg_ram_thrctl : in std_ulogic_vector(0 to 20); + rg_db_dbg_fir0_err : in std_ulogic_vector(0 to 31); + rg_db_dbg_fir1_err : in std_ulogic_vector(0 to 30); + rg_db_dbg_fir2_err : in std_ulogic_vector(0 to 21); + rg_db_dbg_fir_misc : in std_ulogic_vector(0 to 35); + ct_db_dbg_ctrls : in std_ulogic_vector(0 to 36); + rg_db_dbg_spr : in std_ulogic_vector(0 to 46); +-- Perfmon Event Bus + ac_an_event_bus : out std_ulogic_vector(0 to 7); + ac_an_fu_bypass_events : out std_ulogic_vector(0 to 7); + ac_an_iu_bypass_events : out std_ulogic_vector(0 to 7); + ac_an_mm_bypass_events : out std_ulogic_vector(0 to 7); + ac_an_lsu_bypass_events : out std_ulogic_vector(0 to 7); + --Event signals and event mux controls + rg_db_event_bus_enable : in std_ulogic; + rg_db_event_mux_ctrls : in std_ulogic_vector(0 to 23); + fu_pc_event_data : in std_ulogic_vector(0 to 7); + iu_pc_event_data : in std_ulogic_vector(0 to 7); + mm_pc_event_data : in std_ulogic_vector(0 to 7); + xu_pc_event_data : in std_ulogic_vector(0 to 7); + lsu_pc_event_data : in std_ulogic_vector(0 to 7); + ac_pc_trace_to_perfcntr : in std_ulogic_vector(0 to 7) +); +-- synopsys translate_off + + +-- synopsys translate_on +end pcq_dbg; + +architecture pcq_dbg of pcq_dbg is +--===================================================================== +-- Signal Declarations +--===================================================================== +constant fuevents_size : positive := 8; +constant iuevents_size : positive := 8; +constant mmevents_size : positive := 8; +constant xuevents_size : positive := 8; +constant lsuevents_size : positive := 8; +constant trcevents_size : positive := 8; +constant eventbus_size : positive := 8; +constant scrdata_size : positive := 64; +constant scwdata_size : positive := 64; +constant scmisc_size : positive := 3; +constant ramthrctl_size : positive := 4; +constant traceout_size : positive := 88; +constant triggout_size : positive := 12; + +----------------------------------------------------------------------- +-- Scan Ring Ordering: +-- start of func scan chain ordering +constant fuevents_offset : natural := 0; +constant fubypass_offset : natural := fuevents_offset + fuevents_size; +constant iuevents_offset : natural := fubypass_offset + fuevents_size; +constant iubypass_offset : natural := iuevents_offset + iuevents_size; +constant mmevents_offset : natural := iubypass_offset + iuevents_size; +constant mmbypass_offset : natural := mmevents_offset + mmevents_size; +constant xuevents_offset : natural := mmbypass_offset + mmevents_size; +constant lsuevents_offset : natural := xuevents_offset + xuevents_size; +constant lsubypass_offset : natural := lsuevents_offset + lsuevents_size; +constant trcevents_offset : natural := lsubypass_offset + lsuevents_size; +constant eventbus_offset : natural := trcevents_offset + trcevents_size; +constant scrdata_offset : natural := eventbus_offset + eventbus_size; +constant scwdata_offset : natural := scrdata_offset + scrdata_size; +constant scmisc_offset : natural := scwdata_offset + scwdata_size; +constant ramthrctl_offset : natural := scmisc_offset + scmisc_size; +constant traceout_offset : natural := ramthrctl_offset + ramthrctl_size; +constant triggout_offset : natural := traceout_offset + traceout_size; +constant func_right : natural := triggout_offset + triggout_size - 1; +-- end of func scan chain ordering + +----------------------------------------------------------------------- +-- Basic/Misc signals +signal func_siv, func_sov : std_ulogic_vector(0 to func_right); +signal pc_pc_func_slp_sl_thold_0_b : std_ulogic; +signal force_func : std_ulogic; +-- Trace/Trigger/Event Mux signals +signal debug_group_0 : std_ulogic_vector(0 to traceout_size-1); +signal debug_group_1 : std_ulogic_vector(0 to traceout_size-1); +signal debug_group_2 : std_ulogic_vector(0 to traceout_size-1); +signal debug_group_3 : std_ulogic_vector(0 to traceout_size-1); +signal debug_group_4 : std_ulogic_vector(0 to traceout_size-1); +signal debug_group_5 : std_ulogic_vector(0 to traceout_size-1); +signal debug_group_6 : std_ulogic_vector(0 to traceout_size-1); +signal debug_group_7 : std_ulogic_vector(0 to traceout_size-1); +signal trigg_group_0 : std_ulogic_vector(0 to triggout_size-1); +signal trigg_group_1 : std_ulogic_vector(0 to triggout_size-1); +signal trigg_group_2 : std_ulogic_vector(0 to triggout_size-1); +signal trigg_group_3 : std_ulogic_vector(0 to triggout_size-1); +-- Trace/Trigger input signals +signal fir_icache_parity_q : std_ulogic; +signal fir_icachedir_parity_q : std_ulogic; +signal fir_dcache_parity_q : std_ulogic; +signal fir_dcachedir_parity_q : std_ulogic; +signal fir_sprg_ecc_q : std_ulogic_vector(0 to 3); +signal fir_xu_regf_parity_q : std_ulogic_vector(0 to 3); +signal fir_fu_regf_parity_q : std_ulogic_vector(0 to 3); +signal fir_mcsr_summary_q : std_ulogic_vector(0 to 3); +signal fir_ierat_parity_q : std_ulogic; +signal fir_derat_parity_q : std_ulogic; +signal fir_tlb_parity_q : std_ulogic; +signal fir_tlb_lru_parity_q : std_ulogic; +signal fir_ierat_multihit_q : std_ulogic; +signal fir_derat_multihit_q : std_ulogic; +signal fir_tlb_multihit_q : std_ulogic; +signal fir_external_mchk_q : std_ulogic; +signal fir_ditc_overrun_q : std_ulogic; +signal fir_local_snoop_rej_q : std_ulogic; +signal fir_inbox_ecc_q : std_ulogic; +signal fir_outbox_ecc_q : std_ulogic; +signal fir_scom_reg_parity_q : std_ulogic; +signal fir_scom_ack_err_q : std_ulogic; +signal fir_icachedir_multi_q : std_ulogic; +signal fir_dcachedir_multi_q : std_ulogic; +signal fir_wdt_reset_q : std_ulogic_vector(0 to 3); +signal fir_llbust_attempt_q : std_ulogic_vector(0 to 3); +signal fir_llbust_failed_q : std_ulogic_vector(0 to 3); +signal fir_max_recov_cntr_q : std_ulogic; +signal fir_l2intrf_ecc_q : std_ulogic; +signal fir_l2intrf_ue_q : std_ulogic; +signal fir_l2credit_overrun_q : std_ulogic; +signal fir_sprg_ue_q : std_ulogic; +signal fir_xu_regf_ue_q : std_ulogic; +signal fir_fu_regf_ue_q : std_ulogic; +signal fir_nia_miscmpr_q : std_ulogic; +signal fir_debug_event_q : std_ulogic_vector(0 to 3); +signal fir_inbox_ue_q : std_ulogic; +signal fir_outbox_ue_q : std_ulogic; +signal fir_invld_reld_q : std_ulogic; +signal fir_ucode_illegal_q : std_ulogic; +signal fir_attention_instr_q : std_ulogic_vector(0 to 3); +signal fir_xstop_err_q : std_ulogic_vector(0 to 2); +signal fir_recov_err_q : std_ulogic_vector(0 to 2); +signal fir_scom_err_report_q : std_ulogic_vector(0 to 17); +signal fir_xstop_per_thread_d : std_ulogic_vector(0 to 3); +signal fir_xstop_per_thread_q : std_ulogic_vector(0 to 3); +signal fir_block_ram_mode_q : std_ulogic; +signal fir0_recov_err_pulse_q : std_ulogic; +signal fir1_recov_err_pulse_q : std_ulogic; +signal fir2_recov_err_pulse_q : std_ulogic; +signal scom_rdata_d, scom_rdata_q : std_ulogic_vector(0 to 63); +signal scom_wdata_d, scom_wdata_q : std_ulogic_vector(0 to 63); +signal scom_decaddr_q : std_ulogic_vector(0 to 63); +signal scom_misc_sc_act_d : std_ulogic; +signal scom_misc_sc_act_q : std_ulogic; +signal scom_misc_sc_req_q : std_ulogic; +signal scom_misc_sc_wr_q : std_ulogic; +signal scom_misc_sc_nvld_q : std_ulogic_vector(0 to 2); +signal scom_misc_scaddr_fir_d : std_ulogic; +signal scom_misc_scaddr_fir_q : std_ulogic; +signal scom_misc_sc_par_inj_q : std_ulogic; +signal scom_misc_sc_wparity_d : std_ulogic; +signal scom_misc_sc_wparity_q : std_ulogic; +signal ram_execute_q : std_ulogic; +signal ram_interrupt_q : std_ulogic; +signal ram_error_q : std_ulogic; +signal ram_done_q : std_ulogic; +signal ram_thread_q : std_ulogic_vector(0 to 1); +signal ram_mode_q : std_ulogic; +signal ram_xu_done_in_q : std_ulogic; +signal ram_fu_done_in_q : std_ulogic; +signal thrctl_stop_out_q : std_ulogic_vector(0 to 3); +signal thrctl_step_out_q : std_ulogic_vector(0 to 3); +signal thrctl_run_in_q : std_ulogic_vector(0 to 3); +signal ctrls_init_active_q : std_ulogic; +signal ctrls_resetsm_q : std_ulogic_vector(0 to 4); +signal ctrls_initerat_q : std_ulogic; +signal ctrls_reset_cmplt_q : std_ulogic_vector(0 to 3); +signal ctrls_pm_stop_q : std_ulogic_vector(0 to 3); +signal ctrls_pm_state_q : std_ulogic_vector(0 to 3); +signal ctrls_pm_rvwinkled_q : std_ulogic; +signal ctrls_ccr0_pme_q : std_ulogic_vector(0 to 1); +signal ctrls_ccr0_we_q : std_ulogic_vector(0 to 3); +signal ctrls_pmclkctrl_dly_q : std_ulogic_vector(0 to 7); +signal ctrls_dis_pwr_sav_q : std_ulogic; +signal ctrls_ccflush_dis_q : std_ulogic; +signal ctrls_raise_tholds_q : std_ulogic; +signal clks_ccenable_dc : std_ulogic; +signal clks_fast_xstop : std_ulogic; +signal clks_scan_type_dc : std_ulogic_vector(0 to 7); +signal clks_gsd_tst_en_dc : std_ulogic; +signal clks_gsd_tst_ac_dc : std_ulogic; +signal clks_lbist_en_dc : std_ulogic; +signal clks_lbist_ip_dc : std_ulogic; +signal spr_slowspr_val_l2 : std_ulogic; +signal spr_slowspr_rw_l2 : std_ulogic; +signal spr_slowspr_etid_l2 : std_ulogic_vector(0 to 1); +signal spr_slowspr_addr_l2 : std_ulogic_vector(0 to 9); +signal spr_slowspr_data_l2 : std_ulogic_vector(0 to 31); +signal spr_pc_done_l2 : std_ulogic; + +-- Latch definitions begin +signal fu_events_d, fu_events_q : std_ulogic_vector(0 to fuevents_size-1); +signal fu_bypass_q : std_ulogic_vector(0 to fuevents_size-1); +signal iu_events_d, iu_events_q : std_ulogic_vector(0 to iuevents_size-1); +signal iu_bypass_q : std_ulogic_vector(0 to iuevents_size-1); +signal mm_events_d, mm_events_q : std_ulogic_vector(0 to mmevents_size-1); +signal mm_bypass_q : std_ulogic_vector(0 to mmevents_size-1); +signal xu_events_d, xu_events_q : std_ulogic_vector(0 to xuevents_size-1); +signal lsu_events_d, lsu_events_q : std_ulogic_vector(0 to lsuevents_size-1); +signal lsu_bypass_q : std_ulogic_vector(0 to lsuevents_size-1); +signal trc_events_d, trc_events_q : std_ulogic_vector(0 to trcevents_size-1); +signal event_bus_d, event_bus_q : std_ulogic_vector(0 to eventbus_size-1); +signal trace_data_out_d : std_ulogic_vector(0 to traceout_size-1); +signal trace_data_out_q : std_ulogic_vector(0 to traceout_size-1); +signal trigg_data_out_d : std_ulogic_vector(0 to triggout_size-1); +signal trigg_data_out_q : std_ulogic_vector(0 to triggout_size-1); +signal unused_signals : std_ulogic; + + +begin + + unused_signals <= or_reduce(rg_db_dbg_fir2_err(14 to 19) ); + + +--===================================================================== +-- Event Bus Mux Logic +--===================================================================== + fu_events_d <= fu_pc_event_data; + iu_events_d <= iu_pc_event_data; + mm_events_d <= mm_pc_event_data; + xu_events_d <= xu_pc_event_data; + lsu_events_d <= lsu_pc_event_data; + trc_events_d <= ac_pc_trace_to_perfcntr; + + +event_mux: entity work.pcq_dbg_event + generic map( expand_type => expand_type ) + port map + ( vd => vdd + , gd => gnd + , event_mux_ctrls => rg_db_event_mux_ctrls + , fu_event_data => fu_events_q + , iu_event_data => iu_events_q + , mm_event_data => mm_events_q + , xu_event_data => xu_events_q + , lsu_event_data => lsu_events_q + , trace_bus_data => trc_events_q + ------------------------------------------------- + , event_bus => event_bus_d + ); + + +--===================================================================== +-- Trace/Trigger Bus - Sort out input debug signals +--===================================================================== +-- FIR/Error related signals. + fir_icache_parity_q <= rg_db_dbg_fir0_err(0); + fir_icachedir_parity_q <= rg_db_dbg_fir0_err(1); + fir_dcache_parity_q <= rg_db_dbg_fir0_err(2); + fir_dcachedir_parity_q <= rg_db_dbg_fir0_err(3); + fir_sprg_ecc_q <= rg_db_dbg_fir0_err(4 to 7); + fir_xu_regf_parity_q <= rg_db_dbg_fir0_err(8 to 11); + fir_fu_regf_parity_q <= rg_db_dbg_fir0_err(12 to 15); + fir_inbox_ecc_q <= rg_db_dbg_fir0_err(16); + fir_outbox_ecc_q <= rg_db_dbg_fir0_err(17); + fir_scom_reg_parity_q <= rg_db_dbg_fir0_err(18); + fir_scom_ack_err_q <= rg_db_dbg_fir0_err(19); + fir_wdt_reset_q <= rg_db_dbg_fir0_err(20 to 23); + fir_llbust_attempt_q <= rg_db_dbg_fir0_err(24 to 27); + fir_llbust_failed_q <= rg_db_dbg_fir0_err(28 to 31); + fir_max_recov_cntr_q <= rg_db_dbg_fir1_err(0); + fir_l2intrf_ecc_q <= rg_db_dbg_fir1_err(1); + fir_l2intrf_ue_q <= rg_db_dbg_fir1_err(2); + fir_l2credit_overrun_q <= rg_db_dbg_fir1_err(3); + fir_sprg_ue_q <= or_reduce(rg_db_dbg_fir1_err(4 to 7)); + fir_xu_regf_ue_q <= or_reduce(rg_db_dbg_fir1_err(8 to 11)); + fir_fu_regf_ue_q <= or_reduce(rg_db_dbg_fir1_err(12 to 15)); + fir_nia_miscmpr_q <= or_reduce(rg_db_dbg_fir1_err(16 to 19)); + fir_debug_event_q <= rg_db_dbg_fir1_err(20 to 23); + fir_ucode_illegal_q <= or_reduce(rg_db_dbg_fir1_err(24 to 27)); + fir_inbox_ue_q <= rg_db_dbg_fir1_err(28); + fir_outbox_ue_q <= rg_db_dbg_fir1_err(29); + fir_invld_reld_q <= rg_db_dbg_fir1_err(30); + fir_mcsr_summary_q <= rg_db_dbg_fir2_err(0 to 3); + fir_ierat_parity_q <= rg_db_dbg_fir2_err(4); + fir_derat_parity_q <= rg_db_dbg_fir2_err(5); + fir_tlb_parity_q <= rg_db_dbg_fir2_err(6); + fir_tlb_lru_parity_q <= rg_db_dbg_fir2_err(7); + fir_ierat_multihit_q <= rg_db_dbg_fir2_err(8); + fir_derat_multihit_q <= rg_db_dbg_fir2_err(9); + fir_tlb_multihit_q <= rg_db_dbg_fir2_err(10); + fir_external_mchk_q <= rg_db_dbg_fir2_err(11); + fir_local_snoop_rej_q <= rg_db_dbg_fir2_err(12); + fir_ditc_overrun_q <= rg_db_dbg_fir2_err(13); + fir_icachedir_multi_q <= rg_db_dbg_fir2_err(20); + fir_dcachedir_multi_q <= rg_db_dbg_fir2_err(21); + fir_attention_instr_q <= rg_db_dbg_fir_misc(0 to 3); + fir_xstop_err_q <= rg_db_dbg_fir_misc(4 to 6); + fir_recov_err_q <= rg_db_dbg_fir_misc(7 to 9); + fir_scom_err_report_q <= rg_db_dbg_fir_misc(10 to 27); + fir_xstop_per_thread_d <= rg_db_dbg_fir_misc(28 to 31); + fir_block_ram_mode_q <= rg_db_dbg_fir_misc(32); + fir0_recov_err_pulse_q <= rg_db_dbg_fir_misc(33); + fir1_recov_err_pulse_q <= rg_db_dbg_fir_misc(34); + fir2_recov_err_pulse_q <= rg_db_dbg_fir_misc(35); +-- SCOM error; data; address; control signals + scom_rdata_d <= rg_db_dbg_scom_rdata(0 to 63); + scom_wdata_d <= rg_db_dbg_scom_wdata(0 to 63); + scom_decaddr_q <= rg_db_dbg_scom_decaddr(0 to 63); + scom_misc_sc_act_d <= rg_db_dbg_scom_misc(0); + scom_misc_sc_req_q <= rg_db_dbg_scom_misc(1); + scom_misc_sc_wr_q <= rg_db_dbg_scom_misc(2); + scom_misc_sc_nvld_q <= rg_db_dbg_scom_misc(3 to 5); + scom_misc_scaddr_fir_d <= rg_db_dbg_scom_misc(6); + scom_misc_sc_par_inj_q <= rg_db_dbg_scom_misc(7); + scom_misc_sc_wparity_d <= rg_db_dbg_scom_misc(8); +-- RAM and THRCTL register control signals + ram_execute_q <= rg_db_dbg_ram_thrctl(0); + ram_interrupt_q <= rg_db_dbg_ram_thrctl(1); + ram_error_q <= rg_db_dbg_ram_thrctl(2); + ram_done_q <= rg_db_dbg_ram_thrctl(3); + ram_thread_q <= rg_db_dbg_ram_thrctl(4 to 5); + ram_mode_q <= rg_db_dbg_ram_thrctl(6); + ram_xu_done_in_q <= rg_db_dbg_ram_thrctl(7); + ram_fu_done_in_q <= rg_db_dbg_ram_thrctl(8); + thrctl_stop_out_q <= rg_db_dbg_ram_thrctl(9 to 12); + thrctl_step_out_q <= rg_db_dbg_ram_thrctl(13 to 16); + thrctl_run_in_q <= rg_db_dbg_ram_thrctl(17 to 20); +-- Reset SM and Power Management signals + ctrls_init_active_q <= ct_db_dbg_ctrls(0); + ctrls_resetsm_q <= ct_db_dbg_ctrls(1 to 5); + ctrls_initerat_q <= ct_db_dbg_ctrls(6); + ctrls_reset_cmplt_q <= ct_db_dbg_ctrls(7 to 10); + ctrls_pm_stop_q <= ct_db_dbg_ctrls(11 to 14); + ctrls_pm_state_q <= ct_db_dbg_ctrls(15 to 18); + ctrls_pm_rvwinkled_q <= ct_db_dbg_ctrls(19); + ctrls_ccr0_pme_q <= ct_db_dbg_ctrls(20 to 21); + ctrls_ccr0_we_q <= ct_db_dbg_ctrls(22 to 25); + ctrls_pmclkctrl_dly_q <= ct_db_dbg_ctrls(26 to 33); + ctrls_dis_pwr_sav_q <= ct_db_dbg_ctrls(34); + ctrls_ccflush_dis_q <= ct_db_dbg_ctrls(35); + ctrls_raise_tholds_q <= ct_db_dbg_ctrls(36); +-- Clock control; thold/sg/fce signals around clock control macro + clks_ccenable_dc <= ck_db_dbg_clks_ctrls(0); + clks_gsd_tst_en_dc <= ck_db_dbg_clks_ctrls(1); + clks_gsd_tst_ac_dc <= ck_db_dbg_clks_ctrls(2); + clks_lbist_en_dc <= ck_db_dbg_clks_ctrls(3); + clks_lbist_ip_dc <= ck_db_dbg_clks_ctrls(4); + clks_scan_type_dc <= ck_db_dbg_clks_ctrls(5 to 12); + clks_fast_xstop <= ck_db_dbg_clks_ctrls(13); +-- SPRs; slow_spr bus signals from latches + spr_slowspr_val_l2 <= rg_db_dbg_spr(0); + spr_slowspr_rw_l2 <= rg_db_dbg_spr(1); + spr_slowspr_etid_l2 <= rg_db_dbg_spr(2 to 3); + spr_slowspr_addr_l2 <= rg_db_dbg_spr(4 to 13); + spr_slowspr_data_l2 <= rg_db_dbg_spr(14 to 45); + spr_pc_done_l2 <= rg_db_dbg_spr(46); + + +--===================================================================== +-- Trace/Trigger Bus - Form trace bus groups from input debug signals +--===================================================================== + debug_group_0 <= fir_icache_parity_q & fir_icachedir_parity_q & fir_dcache_parity_q & + fir_dcachedir_parity_q & fir_sprg_ecc_q(0 to 3) & fir_nia_miscmpr_q & + fir_l2intrf_ue_q & fir_sprg_ue_q & fir_invld_reld_q & fir_xu_regf_ue_q & + fir_fu_regf_ue_q & fir_inbox_ue_q & fir_outbox_ue_q & fir_l2credit_overrun_q & + fir_ucode_illegal_q & scom_wdata_q(0 to 63) & "000000"; + + debug_group_1 <= scom_misc_sc_act_q & scom_misc_sc_req_q & scom_misc_sc_wr_q & + scom_misc_sc_nvld_q(0 to 2) & scom_misc_scaddr_fir_q & scom_misc_sc_wparity_q & + scom_misc_sc_par_inj_q & fir_block_ram_mode_q & ram_mode_q & ram_thread_q(0 to 1) & + ram_execute_q & ram_interrupt_q & ram_error_q & ram_done_q & ram_xu_done_in_q & + ram_fu_done_in_q & scom_rdata_q(0 to 63) & "00000"; + + debug_group_2 <= fir_fu_regf_parity_q(0 to 3) & fir_xu_regf_parity_q(0 to 3) & ctrls_init_active_q & + ctrls_resetsm_q(0 to 4) & ctrls_initerat_q & ctrls_reset_cmplt_q(0 to 3) & + scom_decaddr_q(0 to 63) & "00000"; + + debug_group_3 <= fir_mcsr_summary_q(0 to 3) & fir_ierat_parity_q & fir_derat_parity_q & + fir_tlb_parity_q & fir_tlb_lru_parity_q & fir_scom_err_report_q(0 to 17) & + thrctl_run_in_q(0 to 3) & thrctl_stop_out_q(0 to 3) & + thrctl_step_out_q(0 to 3) & fir_attention_instr_q(0 to 3) & + fir_scom_reg_parity_q & fir_scom_ack_err_q & fir_recov_err_q(0 to 2) & + fir_xstop_err_q(0 to 2) & fir_xstop_per_thread_q(0 to 3) & x"00000000" & "00"; + + debug_group_4 <= fir_ierat_multihit_q & fir_derat_multihit_q & fir_tlb_multihit_q & + fir_external_mchk_q & fir_local_snoop_rej_q & fir_ditc_overrun_q & + ctrls_pm_stop_q(0 to 3) & ctrls_pm_state_q(0 to 3) & ctrls_ccr0_pme_q(0 to 1) & + ctrls_ccr0_we_q(0 to 3) & ctrls_pm_rvwinkled_q & clks_ccenable_dc & + clks_scan_type_dc(0 to 7) & clks_gsd_tst_en_dc & clks_gsd_tst_ac_dc & + clks_lbist_en_dc & clks_lbist_ip_dc & clks_fast_xstop & + ctrls_pmclkctrl_dly_q(0 to 7) & ctrls_ccflush_dis_q & ctrls_dis_pwr_sav_q & + ctrls_raise_tholds_q & x"0000000000" & "00"; + + debug_group_5 <= fir_icachedir_multi_q & fir_dcachedir_multi_q & fir_inbox_ecc_q & + fir_outbox_ecc_q & fir_l2intrf_ecc_q & fir0_recov_err_pulse_q & + fir1_recov_err_pulse_q & fir2_recov_err_pulse_q & fir_max_recov_cntr_q & + x"0000000000000000000" & "000"; + + debug_group_6 <= fir_llbust_attempt_q(0 to 3) & fir_llbust_failed_q(0 to 3) & + x"00000000000000000000"; + + debug_group_7 <= fir_wdt_reset_q(0 to 3) & fir_debug_event_q(0 to 3) & + spr_slowspr_val_l2 & spr_slowspr_rw_l2 & spr_pc_done_l2 & + spr_slowspr_etid_l2(0 to 1) & spr_slowspr_addr_l2(0 to 9) & + spr_slowspr_data_l2(0 to 31) & x"00000000" & "0"; + + +--===================================================================== +-- Trace/Trigger Bus - Form trigger bus groups from input debug signals +--===================================================================== + trigg_group_0 <= scom_misc_sc_act_q & scom_misc_sc_req_q & scom_misc_sc_wr_q & + scom_misc_sc_nvld_q(0 to 2) & scom_misc_scaddr_fir_q & + thrctl_stop_out_q(0 to 3) & ctrls_initerat_q; + + trigg_group_1 <= ram_mode_q & ram_execute_q & ram_interrupt_q & ram_error_q & + ram_done_q & ctrls_pm_stop_q(0 to 3) & ctrls_ccr0_pme_q(0 to 1) & + ctrls_ccflush_dis_q; + + trigg_group_2 <= fir_xstop_err_q(0 to 2) & fir_recov_err_q(0 to 2) & + fir_mcsr_summary_q(0 to 3) & fir_external_mchk_q & + fir_l2intrf_ecc_q; + + trigg_group_3 <= fir_wdt_reset_q(0 to 3) & fir_llbust_attempt_q(0 to 3) & + thrctl_run_in_q(0 to 3); + + +--===================================================================== +-- Trace/Trigger Bus - Trace/Trigger Mux +--===================================================================== +-- trace_data_in_d <= debug_bus_in; +-- trigg_data_in_d <= trace_triggers_in; + + +debug_mux: entity clib.c_debug_mux8 + port map + ( vd => vdd + ,gd => gnd + + ,select_bits => rg_db_debug_mux_ctrls + ,trace_data_in => debug_bus_in + ,trigger_data_in => trace_triggers_in + + ,dbg_group0 => debug_group_0 + ,dbg_group1 => debug_group_1 + ,dbg_group2 => debug_group_2 + ,dbg_group3 => debug_group_3 + ,dbg_group4 => debug_group_4 + ,dbg_group5 => debug_group_5 + ,dbg_group6 => debug_group_6 + ,dbg_group7 => debug_group_7 + + ,trg_group0 => trigg_group_0 + ,trg_group1 => trigg_group_1 + ,trg_group2 => trigg_group_2 + ,trg_group3 => trigg_group_3 + + ,trace_data_out => trace_data_out_d + ,trigger_data_out => trigg_data_out_d + ); + + +--===================================================================== +-- Outputs +--===================================================================== + ac_an_event_bus <= event_bus_q; + ac_an_fu_bypass_events <= fu_bypass_q; + ac_an_iu_bypass_events <= iu_bypass_q; + ac_an_mm_bypass_events <= mm_bypass_q; + ac_an_lsu_bypass_events <= lsu_bypass_q; + + + debug_bus_out <= trace_data_out_q; + + trace_triggers_out <= trigg_data_out_q; + + +--===================================================================== +-- Latches +--===================================================================== +-- func ring registers start +fuevents: tri_rlmreg_p + generic map (width => fuevents_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rg_db_event_bus_enable, + thold_b => pc_pc_func_slp_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(fuevents_offset to fuevents_offset + fuevents_size-1), + scout => func_sov(fuevents_offset to fuevents_offset + fuevents_size-1), + din => fu_events_d, + dout => fu_events_q ); + +fubypass: tri_rlmreg_p + generic map (width => fuevents_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rg_db_event_bus_enable, + thold_b => pc_pc_func_slp_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(fubypass_offset to fubypass_offset + fuevents_size-1), + scout => func_sov(fubypass_offset to fubypass_offset + fuevents_size-1), + din => fu_events_q, + dout => fu_bypass_q ); + +iuevents: tri_rlmreg_p + generic map (width => iuevents_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rg_db_event_bus_enable, + thold_b => pc_pc_func_slp_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(iuevents_offset to iuevents_offset + iuevents_size-1), + scout => func_sov(iuevents_offset to iuevents_offset + iuevents_size-1), + din => iu_events_d, + dout => iu_events_q ); + +iubypass: tri_rlmreg_p + generic map (width => iuevents_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rg_db_event_bus_enable, + thold_b => pc_pc_func_slp_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(iubypass_offset to iubypass_offset + iuevents_size-1), + scout => func_sov(iubypass_offset to iubypass_offset + iuevents_size-1), + din => iu_events_q, + dout => iu_bypass_q ); + +mmevents: tri_rlmreg_p + generic map (width => mmevents_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rg_db_event_bus_enable, + thold_b => pc_pc_func_slp_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(mmevents_offset to mmevents_offset + mmevents_size-1), + scout => func_sov(mmevents_offset to mmevents_offset + mmevents_size-1), + din => mm_events_d, + dout => mm_events_q ); + +mmbypass: tri_rlmreg_p + generic map (width => mmevents_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rg_db_event_bus_enable, + thold_b => pc_pc_func_slp_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(mmbypass_offset to mmbypass_offset + mmevents_size-1), + scout => func_sov(mmbypass_offset to mmbypass_offset + mmevents_size-1), + din => mm_events_q, + dout => mm_bypass_q ); + +xuevents: tri_rlmreg_p + generic map (width => xuevents_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rg_db_event_bus_enable, + thold_b => pc_pc_func_slp_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(xuevents_offset to xuevents_offset + xuevents_size-1), + scout => func_sov(xuevents_offset to xuevents_offset + xuevents_size-1), + din => xu_events_d, + dout => xu_events_q ); + +lsuevents: tri_rlmreg_p + generic map (width => lsuevents_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rg_db_event_bus_enable, + thold_b => pc_pc_func_slp_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(lsuevents_offset to lsuevents_offset + lsuevents_size-1), + scout => func_sov(lsuevents_offset to lsuevents_offset + lsuevents_size-1), + din => lsu_events_d, + dout => lsu_events_q ); + +lsubypass: tri_rlmreg_p + generic map (width => lsuevents_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rg_db_event_bus_enable, + thold_b => pc_pc_func_slp_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(lsubypass_offset to lsubypass_offset + lsuevents_size-1), + scout => func_sov(lsubypass_offset to lsubypass_offset + lsuevents_size-1), + din => lsu_events_q, + dout => lsu_bypass_q ); + +trcevents: tri_rlmreg_p + generic map (width => trcevents_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rg_db_event_bus_enable, + thold_b => pc_pc_func_slp_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(trcevents_offset to trcevents_offset + trcevents_size-1), + scout => func_sov(trcevents_offset to trcevents_offset + trcevents_size-1), + din => trc_events_d, + dout => trc_events_q ); + +eventbus: tri_rlmreg_p + generic map (width => eventbus_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rg_db_event_bus_enable, + thold_b => pc_pc_func_slp_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(eventbus_offset to eventbus_offset + eventbus_size-1), + scout => func_sov(eventbus_offset to eventbus_offset + eventbus_size-1), + din => event_bus_d, + dout => event_bus_q ); + +scrdata: tri_rlmreg_p + generic map (width => scrdata_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rg_db_trace_bus_enable, + thold_b => pc_pc_func_slp_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(scrdata_offset to scrdata_offset + scrdata_size-1), + scout => func_sov(scrdata_offset to scrdata_offset + scrdata_size-1), + din => scom_rdata_d, + dout => scom_rdata_q ); + +scwdata: tri_rlmreg_p + generic map (width => scwdata_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rg_db_trace_bus_enable, + thold_b => pc_pc_func_slp_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(scwdata_offset to scwdata_offset + scwdata_size-1), + scout => func_sov(scwdata_offset to scwdata_offset + scwdata_size-1), + din => scom_wdata_d, + dout => scom_wdata_q ); + +scmisc: tri_rlmreg_p + generic map (width => scmisc_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rg_db_trace_bus_enable, + thold_b => pc_pc_func_slp_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(scmisc_offset to scmisc_offset + scmisc_size-1), + scout => func_sov(scmisc_offset to scmisc_offset + scmisc_size-1), + din(0) => scom_misc_sc_act_d, + din(1) => scom_misc_scaddr_fir_d, + din(2) => scom_misc_sc_wparity_d, + dout(0) => scom_misc_sc_act_q, + dout(1) => scom_misc_scaddr_fir_q, + dout(2) => scom_misc_sc_wparity_q ); + +ramthrctl: tri_rlmreg_p + generic map (width => ramthrctl_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rg_db_trace_bus_enable, + thold_b => pc_pc_func_slp_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(ramthrctl_offset to ramthrctl_offset + ramthrctl_size-1), + scout => func_sov(ramthrctl_offset to ramthrctl_offset + ramthrctl_size-1), + din(0 to 3) => fir_xstop_per_thread_d, + dout(0 to 3) => fir_xstop_per_thread_q ); + + +traceout: tri_rlmreg_p + generic map (width => traceout_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rg_db_trace_bus_enable, + thold_b => pc_pc_func_slp_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(traceout_offset to traceout_offset + traceout_size-1), + scout => func_sov(traceout_offset to traceout_offset + traceout_size-1), + din => trace_data_out_d, + dout => trace_data_out_q ); + +triggout: tri_rlmreg_p + generic map (width => triggout_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rg_db_trace_bus_enable, + thold_b => pc_pc_func_slp_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(triggout_offset to triggout_offset + triggout_size-1), + scout => func_sov(triggout_offset to triggout_offset + triggout_size-1), + din => trigg_data_out_d, + dout => trigg_data_out_q ); +-- func ring registers end + + +--===================================================================== +-- Thold/SG Staging +--===================================================================== +-- func lcbor +lcbor_func0: tri_lcbor +generic map (expand_type => expand_type ) +port map ( + clkoff_b => lcb_clkoff_dc_b, + thold => pc_pc_func_slp_sl_thold_0, + sg => pc_pc_sg_0, + act_dis => lcb_act_dis_dc, + forcee => force_func, + thold_b => pc_pc_func_slp_sl_thold_0_b ); + + +--===================================================================== +-- Scan Connections +--===================================================================== +-- Func ring +func_siv(0 TO func_right) <= func_scan_in & func_sov(0 to func_right-1); +func_scan_out <= func_sov(func_right) and scan_dis_dc_b; + + +----------------------------------------------------------------------- +end pcq_dbg; diff --git a/rel/src/vhdl/work/pcq_dbg_event.vhdl b/rel/src/vhdl/work/pcq_dbg_event.vhdl new file mode 100644 index 0000000..7946d6f --- /dev/null +++ b/rel/src/vhdl/work/pcq_dbg_event.vhdl @@ -0,0 +1,164 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- +-- Description: Pervasive Core Event Bus Mux +-- +--***************************************************************************** + +library ieee; +use ieee.std_logic_1164.all; +library support; +use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity pcq_dbg_event is +generic(expand_type : integer := 2 -- 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) +); +port( + vd : inout power_logic; + gd : inout power_logic; + event_mux_ctrls : in std_ulogic_vector(0 to 23); + fu_event_data : in std_ulogic_vector(0 to 7); + iu_event_data : in std_ulogic_vector(0 to 7); + mm_event_data : in std_ulogic_vector(0 to 7); + xu_event_data : in std_ulogic_vector(0 to 7); + lsu_event_data : in std_ulogic_vector(0 to 7); + trace_bus_data : in std_ulogic_vector(0 to 7); + -------------------------------------------------------- + event_bus : out std_ulogic_vector(0 to 7) +); +-- synopsys translate_off + +-- synopsys translate_on +end pcq_dbg_event; + +architecture pcq_dbg_event of pcq_dbg_event is +--===================================================================== +-- Signal Declarations +--===================================================================== +-- Event Mux Signals +signal event_signals_per_bit : std_ulogic_vector(0 to 7); + + +begin + + +--===================================================================== +-- Event Bus Mux Logic +--===================================================================== + with event_mux_ctrls(0 to 2) select -- CESR(40:42) + event_signals_per_bit(0) <= xu_event_data(0) when "000", + iu_event_data(0) when "001", + fu_event_data(0) when "010", + mm_event_data(0) when "011", + lsu_event_data(0) when "100", + xu_event_data(4) when "101", + iu_event_data(4) when "110", + trace_bus_data(0) when others; + + with event_mux_ctrls(3 to 5) select -- CESR(43:45) + event_signals_per_bit(1) <= xu_event_data(1) when "000", + iu_event_data(1) when "001", + fu_event_data(1) when "010", + mm_event_data(1) when "011", + lsu_event_data(1) when "100", + xu_event_data(5) when "101", + iu_event_data(5) when "110", + trace_bus_data(1) when others; + + with event_mux_ctrls(6 to 8) select -- CESR(46:48) + event_signals_per_bit(2) <= xu_event_data(2) when "000", + iu_event_data(2) when "001", + fu_event_data(2) when "010", + mm_event_data(2) when "011", + lsu_event_data(2) when "100", + xu_event_data(6) when "101", + iu_event_data(6) when "110", + trace_bus_data(2) when others; + + with event_mux_ctrls(9 to 11) select -- CESR(49:51) + event_signals_per_bit(3) <= xu_event_data(3) when "000", + iu_event_data(3) when "001", + fu_event_data(3) when "010", + mm_event_data(3) when "011", + lsu_event_data(3) when "100", + xu_event_data(7) when "101", + iu_event_data(7) when "110", + trace_bus_data(3) when others; + + with event_mux_ctrls(12 to 14) select -- CESR(52:54) + event_signals_per_bit(4) <= xu_event_data(4) when "000", + iu_event_data(4) when "001", + fu_event_data(4) when "010", + mm_event_data(4) when "011", + lsu_event_data(4) when "100", + xu_event_data(0) when "101", + iu_event_data(0) when "110", + trace_bus_data(4) when others; + + with event_mux_ctrls(15 to 17) select -- CESR(55:57) + event_signals_per_bit(5) <= xu_event_data(5) when "000", + iu_event_data(5) when "001", + fu_event_data(5) when "010", + mm_event_data(5) when "011", + lsu_event_data(5) when "100", + xu_event_data(1) when "101", + iu_event_data(1) when "110", + trace_bus_data(5) when others; + + with event_mux_ctrls(18 to 20) select -- CESR(58:60) + event_signals_per_bit(6) <= xu_event_data(6) when "000", + iu_event_data(6) when "001", + fu_event_data(6) when "010", + mm_event_data(6) when "011", + lsu_event_data(6) when "100", + xu_event_data(2) when "101", + iu_event_data(2) when "110", + trace_bus_data(6) when others; + + with event_mux_ctrls(21 to 23) select -- CESR(61:63) + event_signals_per_bit(7) <= xu_event_data(7) when "000", + iu_event_data(7) when "001", + fu_event_data(7) when "010", + mm_event_data(7) when "011", + lsu_event_data(7) when "100", + xu_event_data(3) when "101", + iu_event_data(3) when "110", + trace_bus_data(7) when others; + + +--===================================================================== +-- Outputs +--===================================================================== + event_bus(0 to 7) <= event_signals_per_bit(0 to 7); + + +----------------------------------------------------------------------- +end pcq_dbg_event; diff --git a/rel/src/vhdl/work/pcq_local_fir2.vhdl b/rel/src/vhdl/work/pcq_local_fir2.vhdl new file mode 100644 index 0000000..f2060d6 --- /dev/null +++ b/rel/src/vhdl/work/pcq_local_fir2.vhdl @@ -0,0 +1,592 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- +-- Description: Generic Local FIR Component +-- +--***************************************************************************** + +library ieee; +use ieee.std_logic_1164.all; +library ibm; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +library support; +use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + + +--------------------------------------------------------------------- + +entity pcq_local_fir2 is + generic(width : positive := 1; -- this must be >=1 and <=64 + expand_type : integer := 2; -- 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) + impl_lxstop_mchk : boolean := false; -- generate local checkstop /machine check output + use_recov_reset : boolean := false; -- this adds a reset feature without the second wof register. + fir_init : std_ulogic_vector := "0"; -- init value for fir register; length = width ! + fir_mask_init : std_ulogic_vector := "0"; -- init value for fir mask register; length = width ! + fir_mask_par_init : std_ulogic_vector := "0"; -- init value for fir mask register even parity + fir_action0_init : std_ulogic_vector := "0"; -- init value for fir action0 register; length = width ! + fir_action0_par_init : std_ulogic_vector := "0"; -- init value for fir action0 register even parity + fir_action1_init : std_ulogic_vector := "0"; -- init value for fir action1 register; length = width ! + fir_action1_par_init : std_ulogic_vector := "0"); -- init value for fir action1 register even parity + port +-- Global lines for clocking and scan control + ( nclk : in clk_logic + ; vd : inout power_logic + ; gd : inout power_logic + ; lcb_clkoff_dc_b : in std_ulogic --from lcb_cntl external to component + ; lcb_mpw1_dc_b : in std_ulogic --from lcb_cntl external to component + ; lcb_mpw2_dc_b : in std_ulogic --from lcb_cntl external to component + ; lcb_delay_lclkr_dc : in std_ulogic --from lcb_cntl external to component + ; lcb_act_dis_dc : in std_ulogic --from lcb_cntl external to component + ; lcb_sg_0 : in std_ulogic + ; lcb_func_slp_sl_thold_0 : in std_ulogic := '0' + ; lcb_cfg_slp_sl_thold_0 : in std_ulogic := '0' + ; mode_scan_siv : in std_ulogic_vector(0 to 3*(width+1)+width-1) -- scan vector in + ; mode_scan_sov : out std_ulogic_vector(0 to 3*(width+1)+width-1) -- scan vector out + ; func_scan_siv : in std_ulogic_vector(0 to 4) + ; func_scan_sov : out std_ulogic_vector(0 to 4) + -- External interface + ; sys_xstop_in : in std_ulogic := '0' -- freeze FIR on system checkstop from chip GEM + ; error_in : in std_ulogic_vector(0 to width-1) -- needs to be directly off a latch for timing + ; xstop_err : out std_ulogic -- checkstop output to Global FIR + ; recov_err : out std_ulogic -- recoverable output to Global FIR + ; lxstop_mchk : out std_ulogic -- use ONLY if impl_lxstop_mchk = true + ; trace_error : out std_ulogic -- connect to error_input of closest trdata macro + ; recov_reset : in std_ulogic := '0' -- only needed if use_recov_reset = true + ; fir_out : out std_ulogic_vector(0 to width-1) -- output of current FIR state if needed + ; act0_out : out std_ulogic_vector(0 to width-1) -- output of current FIR Act0 state if needed + ; act1_out : out std_ulogic_vector(0 to width-1) -- output of current FIR Act1 state if needed + ; mask_out : out std_ulogic_vector(0 to width-1) -- output of current FIR Mask state if needed + ; sc_parity_error_inject : in std_ulogic -- Force parity error + -- SCOM register connections + ; sc_active : in std_ulogic + ; sc_wr_q : in std_ulogic + ; sc_addr_v : in std_ulogic_vector(0 to 8) + ; sc_wdata : in std_ulogic_vector(0 to width-1) + ; sc_wparity : in std_ulogic + ; sc_rdata : out std_ulogic_vector(0 to width-1) + ; fir_parity_check : out std_ulogic_vector(0 to 2) -- Action0, Action1, Mask reg parity checks + ); + + + +end pcq_local_fir2; + + +architecture pcq_local_fir2 of pcq_local_fir2 is + -- Clocks + signal func_d1clk : std_ulogic; + signal func_d2clk : std_ulogic; + signal func_lclk : clk_logic; + signal mode_d1clk : std_ulogic; + signal mode_d2clk : std_ulogic; + signal mode_lclk : clk_logic; + signal scom_mode_d1clk : std_ulogic; + signal scom_mode_d2clk : std_ulogic; + signal scom_mode_lclk : clk_logic; + signal func_thold_b : std_ulogic; + signal func_force : std_ulogic; + signal mode_thold_b : std_ulogic; + signal mode_force : std_ulogic; + -- FIR regs + signal data_ones : std_ulogic_vector(0 to width-1); + signal or_fir : std_ulogic_vector(0 to width-1); + signal and_fir : std_ulogic_vector(0 to width-1); + signal or_mask : std_ulogic_vector(0 to width-1); + signal and_mask : std_ulogic_vector(0 to width-1); + signal fir_mask_in : std_ulogic_vector(0 to width-1); + signal fir_mask_lt : std_ulogic_vector(0 to width-1); + signal masked : std_ulogic_vector(0 to width-1); + signal fir_mask_par_in : std_ulogic; + signal fir_mask_par_lt : std_ulogic; + signal fir_mask_par_err : std_ulogic; + signal fir_action0_in : std_ulogic_vector(0 to width-1); + signal fir_action0_lt : std_ulogic_vector(0 to width-1); + signal fir_action0_par_in : std_ulogic; + signal fir_action0_par_lt : std_ulogic; + signal fir_action0_par_err : std_ulogic; + signal fir_action1_in : std_ulogic_vector(0 to width-1); + signal fir_action1_lt : std_ulogic_vector(0 to width-1); + signal fir_action1_par_in : std_ulogic; + signal fir_action1_par_lt : std_ulogic; + signal fir_action1_par_err : std_ulogic; + signal fir_reset : std_ulogic_vector(0 to width-1); + signal error_input : std_ulogic_vector(0 to width-1); + signal fir_error_in_reef : std_ulogic_vector(0 to width-1); + signal fir_in : std_ulogic_vector(0 to width-1); + signal fir_lt : std_ulogic_vector(0 to width-1); + signal block_fir : std_ulogic; + signal or_fir_load : std_ulogic; + signal and_fir_ones : std_ulogic; + signal and_fir_load : std_ulogic; + signal or_mask_load : std_ulogic; + signal and_mask_ones : std_ulogic; + signal and_mask_load : std_ulogic; + -- Error report + signal sys_xstop_lt : std_ulogic; + signal recov_in : std_ulogic; + signal recov_lt : std_ulogic; + signal xstop_in : std_ulogic; + signal xstop_lt : std_ulogic; + signal trace_error_in : std_ulogic; + signal trace_error_lt : std_ulogic; + -- Other + signal tieup : std_ulogic; + -- Scan chain hookups + signal mode_si, mode_so : std_ulogic_vector(0 to 3*(width+1)+width-1); + signal func_si, func_so : std_ulogic_vector(0 to 4); + signal unused_signals : std_ulogic; + + +begin + tieup <= '1'; + data_ones <= (others => '1'); +unused_signals <= or_reduce(recov_reset & sc_addr_v(5)); + +--****************************************************** +--* Check width inputs +--****************************************************** + assert (fir_action0_init'length = width) + report "fir_action0_init width error, fir_action0_init must be same width as the component instantiation" + severity error; + + assert (fir_action1_init'length = width) + report "fir_action1_init width error, fir_action1_init must be same width as the component instantiation" + severity error; + + assert (fir_mask_init'length = width) + report "fir_mask_init width error, fir_mask_init must be same width as the component instantiation" + severity error; + +-- This will cause the compile to fail if the wrong width is entered. + verify_action0: if (fir_action0_init'length /= width) generate + fir_in(0 to 95) <= fir_lt(0 to width); + end generate verify_action0; + + verify_action1: if (fir_action1_init'length /= width) generate + fir_in(0 to 95) <= fir_lt(0 to width); + end generate verify_action1; + + verify_action2: if (fir_mask_init'length /= width) generate + fir_in(0 to 95) <= fir_lt(0 to width); + end generate verify_action2; + + +--****************************************************** +--* LCB driver, LCB and Register Instantiations +--****************************************************** +-- functional ring regs; NOT power managed + func_lcbor: entity tri.tri_lcbor + generic map (expand_type => expand_type ) + port map( clkoff_b => lcb_clkoff_dc_b, + thold => lcb_func_slp_sl_thold_0, + sg => lcb_sg_0, + act_dis => lcb_act_dis_dc, + forcee => func_force, + thold_b => func_thold_b + ); + + func_lcb: entity tri.tri_lcbnd + generic map (expand_type => expand_type ) + port map( act => tieup, -- not power saved + vd => vd, + gd => gd, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + nclk => nclk, + forcee => func_force, + sg => lcb_sg_0, + thold_b => func_thold_b, + d1clk => func_d1clk, + d2clk => func_d2clk, + lclk => func_lclk + ); + + +-- config ring regs; NOT power managed + mode_lcbor: entity tri.tri_lcbor + generic map (expand_type => expand_type ) + port map( clkoff_b => lcb_clkoff_dc_b, + thold => lcb_cfg_slp_sl_thold_0, + sg => lcb_sg_0, + act_dis => lcb_act_dis_dc, + forcee => mode_force, + thold_b => mode_thold_b + ); + + mode_lcb: entity tri.tri_lcbnd + generic map (expand_type => expand_type ) + port map( act => tieup, -- not power saved + vd => vd, + gd => gd, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + nclk => nclk, + forcee => mode_force, + sg => lcb_sg_0, + thold_b => mode_thold_b, + d1clk => mode_d1clk, + d2clk => mode_d2clk, + lclk => mode_lclk + ); + + scom_mode_lcb: entity tri.tri_lcbnd + generic map (expand_type => expand_type ) + port map( act => sc_active, -- active during scom access + vd => vd, + gd => gd, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + nclk => nclk, + forcee => mode_force, + sg => lcb_sg_0, + thold_b => mode_thold_b, + d1clk => scom_mode_d1clk, + d2clk => scom_mode_d2clk, + lclk => scom_mode_lclk + ); + +---------------------------------------------------------------------- +-- Mode Registers +---------------------------------------------------------------------- + fir_action0 : entity tri.tri_nlat_scan + generic map( width => width, init => fir_action0_init, expand_type => expand_type ) + port map + ( vd => vd + , gd => gd + , d1clk => scom_mode_d1clk + , d2clk => scom_mode_d2clk + , lclk => scom_mode_lclk + , scan_in => mode_si(0 to width-1) + , scan_out => mode_so(0 to width-1) + , din => fir_action0_in + , q => fir_action0_lt + ); + + fir_action0_par : entity tri.tri_nlat_scan + generic map( width => 1, init => fir_action0_par_init, expand_type => expand_type ) + port map + ( vd => vd + , gd => gd + , d1clk => scom_mode_d1clk + , d2clk => scom_mode_d2clk + , lclk => scom_mode_lclk + , scan_in => mode_si(width to width) + , scan_out => mode_so(width to width) + , din(0) => fir_action0_par_in + , q(0) => fir_action0_par_lt + ); + + fir_action1 : entity tri.tri_nlat_scan + generic map( width => width, init => fir_action1_init, expand_type => expand_type ) + port map + ( vd => vd + , gd => gd + , d1clk => scom_mode_d1clk + , d2clk => scom_mode_d2clk + , lclk => scom_mode_lclk + , scan_in => mode_si(width+1 to 2*width) + , scan_out => mode_so(width+1 to 2*width) + , din => fir_action1_in + , q => fir_action1_lt + ); + + fir_action1_par : entity tri.tri_nlat_scan + generic map( width => 1, init => fir_action1_par_init, expand_type => expand_type ) + port map + ( vd => vd + , gd => gd + , d1clk => scom_mode_d1clk + , d2clk => scom_mode_d2clk + , lclk => scom_mode_lclk + , scan_in => mode_si(2*width+1 to 2*width+1) + , scan_out => mode_so(2*width+1 to 2*width+1) + , din(0) => fir_action1_par_in + , q(0) => fir_action1_par_lt + ); + + + fir_mask : ENTITY tri.tri_nlat_scan + GENERIC MAP( width => width, init => fir_mask_init, expand_type => expand_type ) + port map + ( vd => vd + , gd => gd + , d1clk => scom_mode_d1clk + , d2clk => scom_mode_d2clk + , lclk => scom_mode_lclk + , scan_in => mode_si(2*width+2 to 3*width+1) + , scan_out => mode_so(2*width+2 to 3*width+1) + , din => fir_mask_in + , q => fir_mask_lt + ); + + fir_mask_par : entity tri.tri_nlat_scan + generic map( width => 1, init => fir_mask_par_init, expand_type => expand_type ) + port map + ( vd => vd + , gd => gd + , d1clk => scom_mode_d1clk + , d2clk => scom_mode_d2clk + , lclk => scom_mode_lclk + , scan_in => mode_si(3*width+2 to 3*width+2) + , scan_out => mode_so(3*width+2 to 3*width+2) + , din(0) => fir_mask_par_in + , q(0) => fir_mask_par_lt + ); + + fir : entity tri.tri_nlat_scan + generic map( width => width, init => fir_init, expand_type => expand_type ) + port map + ( vd => vd + , gd => gd + , d1clk => mode_d1clk + , d2clk => mode_d2clk + , lclk => mode_lclk + , scan_in => mode_si(3*width+3 to 4*width+2) + , scan_out => mode_so(3*width+3 to 4*width+2) + , din => fir_in + , q => fir_lt + ); + + +---------------------------------------------------------------------- +-- Func Registers with no power savings +---------------------------------------------------------------------- + sys_xstop : entity tri.tri_nlat + generic map( width => 1, init => "0", expand_type => expand_type ) + port map + ( vd => vd + , gd => gd + , d1clk => func_d1clk + , d2clk => func_d2clk + , lclk => func_lclk + , scan_in => func_si(1) + , scan_out => func_so(1) + , din(0) => sys_xstop_in + , q(0) => sys_xstop_lt + ); + + recov : entity tri.tri_nlat + generic map( width => 1, init => "0", expand_type => expand_type ) + port map + ( vd => vd + , gd => gd + , d1clk => func_d1clk + , d2clk => func_d2clk + , lclk => func_lclk + , scan_in => func_si(2) + , scan_out => func_so(2) + , din(0) => recov_in + , q(0) => recov_lt + ); + + xstop : entity tri.tri_nlat + generic map( width => 1, init => "0", expand_type => expand_type ) + port map + ( vd => vd + , gd => gd + , d1clk => func_d1clk + , d2clk => func_d2clk + , lclk => func_lclk + , scan_in => func_si(3) + , scan_out => func_so(3) + , din(0) => xstop_in + , q(0) => xstop_lt + ); + + trace_err : entity tri.tri_nlat + generic map( width => 1, init => "0", expand_type => expand_type ) + port map + ( vd => vd + , gd => gd + , d1clk => func_d1clk + , d2clk => func_d2clk + , lclk => func_lclk + , scan_in => func_si(4) + , scan_out => func_so(4) + , din(0) => trace_error_in + , q(0) => trace_error_lt + ); + + +--****************************************************** +--* Optional Recovery Reset +--****************************************************** + use_recov_reset_yes: if (use_recov_reset = true) generate + fir_reset <= NOT gate_AND(recov_reset, NOT fir_action0_lt AND fir_action1_lt); + end generate use_recov_reset_yes; + + use_recov_reset_no: if (use_recov_reset = false) generate + fir_reset <= (others => '1') ; + end generate use_recov_reset_no; + + +--****************************************************** +--* FIR +--****************************************************** + -- write to x'0' to write FIR directly + -- write to x'1' to And-Mask FIR + -- write to x'2' to Or-Mask FIR + or_fir_load <= (sc_addr_v(0) or sc_addr_v(2)) and sc_wr_q; + and_fir_ones <= not((sc_addr_v(0) or sc_addr_v(1)) and sc_wr_q); + and_fir_load <= sc_addr_v(1) and sc_wr_q; + + or_fir <= gate_and( or_fir_load, sc_wdata); + + and_fir <= gate_and(and_fir_load, sc_wdata) or + gate_and(and_fir_ones, data_ones ); + + fir_in <= gate_and(not block_fir, error_input) or or_fir or (fir_lt and and_fir and fir_reset); + + + fir_error_in_reef <= error_in; -- does a signal rename for the reef tool + error_input <= fir_error_in_reef; + + +--****************************************************** +--* FIR Mask +--****************************************************** + -- write to x'6' to write FIR-MASK directly + -- write to x'7' to And-Mask FIR-MASK + -- write to x'8' to Or-Mask FIR-MASK + or_mask_load <= (sc_addr_v(6) or sc_addr_v(8)) and sc_wr_q; + and_mask_ones <= not((sc_addr_v(6) or sc_addr_v(7)) and sc_wr_q); + and_mask_load <= sc_addr_v(7) and sc_wr_q; + + or_mask <= gate_and( or_mask_load, sc_wdata); + and_mask <= gate_and(and_mask_load, sc_wdata) or gate_and(and_mask_ones, data_ones); + + fir_mask_in <= or_mask or (fir_mask_lt and and_mask); + fir_mask_par_in <= parity_gen_even(fir_mask_in) when (gate_and(sc_wr_q, or_reduce(sc_addr_v(6 to 8))))='1' else + fir_mask_par_lt; + + fir_mask_par_err <= (xor_reduce(fir_mask_lt) xor fir_mask_par_lt) or + (sc_wr_q and or_reduce(sc_addr_v(6 to 8)) and sc_parity_error_inject); + + masked <= fir_mask_lt; + + +--****************************************************** +--* Action Registers +--****************************************************** + -- write to x'3' to write FIR-Action0 directly + fir_action0_in <= sc_wdata when (sc_addr_v(3) and sc_wr_q) = '1' else fir_action0_lt; + fir_action0_par_in <= sc_wparity when (sc_addr_v(3) and sc_wr_q) = '1' else fir_action0_par_lt; + fir_action0_par_err <= xor_reduce(fir_action0_lt) xor fir_action0_par_lt; + + -- write to x'4' to write FIR-Action1 directly + fir_action1_in <= sc_wdata when (sc_addr_v(4) and sc_wr_q) = '1' else fir_action1_lt; + fir_action1_par_in <= sc_wparity when (sc_addr_v(4) and sc_wr_q) = '1' else fir_action1_par_lt; + fir_action1_par_err <= xor_reduce(fir_action1_lt) xor fir_action1_par_lt; + + +--****************************************************** +--* Summary +--****************************************************** + xstop_in <= or_reduce(fir_lt and fir_action0_lt and not fir_action1_lt and not masked); -- fir_action = 10 + recov_in <= or_reduce(fir_lt and not fir_action0_lt and fir_action1_lt and not masked); -- fir_action = 01 + + block_fir <= xstop_lt or sys_xstop_lt; + + xstop_err <= xstop_lt; + recov_err <= recov_lt; + trace_error <= trace_error_lt; + + fir_out <= fir_lt; + act0_out <= fir_action0_lt; + act1_out <= fir_action1_lt; + mask_out <= fir_mask_lt; + + fir_parity_check <= fir_action0_par_err & fir_action1_par_err & fir_mask_par_err; + + + +--****************************************************** +--* SCOM read logic +--****************************************************** + sc_rdata <= gate_and(sc_addr_v(0), fir_lt ) or + gate_and(sc_addr_v(3), fir_action0_lt) or + gate_and(sc_addr_v(4), fir_action1_lt) or + gate_and(sc_addr_v(6), fir_mask_lt ) ; + + +--****************************************************** +--* Optional MCHK Enable Register and Output +--****************************************************** + mchkgen: if (impl_lxstop_mchk = true) generate + yes: block + signal lxstop_mchk_in : std_ulogic; + signal lxstop_mchk_lt : std_ulogic; + begin + + lxstop_mchk_in <= or_reduce(fir_lt and fir_action0_lt and fir_action1_lt and not masked); -- fir_action = 11 + lxstop_mchk <= lxstop_mchk_lt; + + trace_error_in <= xstop_in or recov_in or lxstop_mchk_in; + + mchk : entity tri.tri_nlat + generic map( width => 1, init => "0", expand_type => expand_type ) + port map + ( d1clk => func_d1clk + , vd => vd + , gd => gd + , lclk => func_lclk + , d2clk => func_d2clk + , scan_in => func_si(0) + , scan_out => func_so(0) + , din(0) => lxstop_mchk_in + , q(0) => lxstop_mchk_lt + ); + end block yes; + end generate mchkgen; + + nomchk: if (impl_lxstop_mchk = false) generate + trace_error_in <= xstop_in or recov_in; + lxstop_mchk <= '0'; + func_so(0) <= func_si(0); + end generate nomchk; + + +--****************************************************** +-- Scan Chain Connections +--****************************************************** + mode_si <= mode_scan_siv; + mode_scan_sov <= mode_so; + + func_si <= func_scan_siv; + func_scan_sov <= func_so; + + +----------------------------------------------------------------------- +end pcq_local_fir2; diff --git a/rel/src/vhdl/work/pcq_psro_soft.vhdl b/rel/src/vhdl/work/pcq_psro_soft.vhdl new file mode 100644 index 0000000..41f44cf --- /dev/null +++ b/rel/src/vhdl/work/pcq_psro_soft.vhdl @@ -0,0 +1,62 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- +-- Description: Core PSRO Sensor +-- +--***************************************************************************** + +library ieee; +use ieee.std_logic_1164.all ; +library support; +use support.power_logic_pkg.all; +library tri; + + +entity pcq_psro_soft is + port ( + vdd : inout power_logic; -- Local Voltage Grid + gnd : inout power_logic; -- Local Gnd + pcq_psro_enable : in std_ulogic_vector(0 to 2); -- from perv + psro_pcq_ringsig : out std_ulogic -- to the PBus, these need to be triple buffered + ); + +end pcq_psro_soft; + + +architecture pcq_psro_soft of pcq_psro_soft is +begin + + pcq_init: entity tri.tri_psro_soft + port map + ( vdd => vdd , + gnd => gnd , + psro_enable => pcq_psro_enable(0 to 2) , + psro_ringsig => psro_pcq_ringsig ); + +end pcq_psro_soft; diff --git a/rel/src/vhdl/work/pcq_regs.vhdl b/rel/src/vhdl/work/pcq_regs.vhdl new file mode 100644 index 0000000..7ba0f08 --- /dev/null +++ b/rel/src/vhdl/work/pcq_regs.vhdl @@ -0,0 +1,2027 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- +-- Description: Pervasive Core Registers + Error Reporting +-- +--***************************************************************************** + +library ieee; +use ieee.std_logic_1164.all; +library ibm,clib; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; +library support; +use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity pcq_regs is +generic(expand_type : integer := 2; -- 0=ibm (Umbra), 1=non-ibm, 2=ibm (MPG) + regmode : integer := 6 -- 6=64-bit model, 5=32-bit model +); +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + scan_dis_dc_b : in std_ulogic; + lcb_clkoff_dc_b : in std_ulogic; + lcb_d_mode_dc : in std_ulogic; + lcb_mpw1_dc_b : in std_ulogic; + lcb_mpw2_dc_b : in std_ulogic; + lcb_delay_lclkr_dc : in std_ulogic; + lcb_act_dis_dc : in std_ulogic; + lcb_func_slp_sl_thold_0 : in std_ulogic; + lcb_cfg_sl_thold_0 : in std_ulogic; + lcb_cfg_slp_sl_thold_0 : in std_ulogic; + lcb_sg_0 : in std_ulogic; + ccfg_scan_in : in std_ulogic; + bcfg_scan_in : in std_ulogic; + dcfg_scan_in : in std_ulogic; + func_scan_in : in std_ulogic; + ccfg_scan_out : out std_ulogic; + bcfg_scan_out : out std_ulogic; + dcfg_scan_out : out std_ulogic; + func_scan_out : out std_ulogic; +-- SCOM Satellite Interface + an_ac_scom_sat_id : in std_ulogic_vector(0 to 3); + an_ac_scom_dch : in std_ulogic; + an_ac_scom_cch : in std_ulogic; + ac_an_scom_dch : out std_ulogic; + ac_an_scom_cch : out std_ulogic; +-- FIR and Error Signals + ac_an_special_attn : out std_ulogic_vector(0 to 3); + ac_an_checkstop : out std_ulogic_vector(0 to 2); + ac_an_local_checkstop : out std_ulogic_vector(0 to 2); + ac_an_recov_err : out std_ulogic_vector(0 to 2); + ac_an_trace_error : out std_ulogic; + an_ac_checkstop : in std_ulogic; + an_ac_malf_alert : in std_ulogic; + rg_ck_fast_xstop : out std_ulogic; + iu_pc_err_icache_parity : in std_ulogic; + iu_pc_err_icachedir_parity : in std_ulogic; + iu_pc_err_icachedir_multihit : in std_ulogic; + iu_pc_err_ucode_illegal : in std_ulogic_vector(0 to 3); + xu_pc_err_dcache_parity : in std_ulogic; + xu_pc_err_dcachedir_parity : in std_ulogic; + xu_pc_err_dcachedir_multihit : in std_ulogic; + xu_pc_err_mcsr_summary : in std_ulogic_vector(0 to 3); + xu_pc_err_ierat_parity : in std_ulogic; + xu_pc_err_derat_parity : in std_ulogic; + xu_pc_err_tlb_parity : in std_ulogic; + xu_pc_err_tlb_lru_parity : in std_ulogic; + xu_pc_err_ierat_multihit : in std_ulogic; + xu_pc_err_derat_multihit : in std_ulogic; + xu_pc_err_tlb_multihit : in std_ulogic; + xu_pc_err_ext_mchk : in std_ulogic; + xu_pc_err_ditc_overrun : in std_ulogic; + xu_pc_err_local_snoop_reject : in std_ulogic; + xu_pc_err_sprg_ecc : in std_ulogic_vector(0 to 3); + xu_pc_err_sprg_ue : in std_ulogic_vector(0 to 3); + xu_pc_err_regfile_parity : in std_ulogic_vector(0 to 3); + xu_pc_err_regfile_ue : in std_ulogic_vector(0 to 3); + xu_pc_err_llbust_attempt : in std_ulogic_vector(0 to 3); + xu_pc_err_llbust_failed : in std_ulogic_vector(0 to 3); + xu_pc_err_l2intrf_ecc : in std_ulogic; + xu_pc_err_l2intrf_ue : in std_ulogic; + xu_pc_err_l2credit_overrun : in std_ulogic; + xu_pc_err_wdt_reset : in std_ulogic_vector(0 to 3); + xu_pc_err_attention_instr : in std_ulogic_vector(0 to 3); + xu_pc_err_debug_event : in std_ulogic_vector(0 to 3); + xu_pc_err_nia_miscmpr : in std_ulogic_vector(0 to 3); + xu_pc_err_invld_reld : in std_ulogic; + xu_pc_err_mchk_disabled : in std_ulogic; + bx_pc_err_inbox_ecc : in std_ulogic; + bx_pc_err_inbox_ue : in std_ulogic; + bx_pc_err_outbox_ecc : in std_ulogic; + bx_pc_err_outbox_ue : in std_ulogic; + fu_pc_err_regfile_parity : in std_ulogic_vector(0 to 3); + fu_pc_err_regfile_ue : in std_ulogic_vector(0 to 3); + pc_iu_inj_icache_parity : out std_ulogic; + pc_iu_inj_icachedir_parity : out std_ulogic; + pc_xu_inj_dcache_parity : out std_ulogic; + pc_xu_inj_dcachedir_parity : out std_ulogic; + pc_xu_inj_sprg_ecc : out std_ulogic_vector(0 to 3); + pc_xu_inj_regfile_parity : out std_ulogic_vector(0 to 3); + pc_fu_inj_regfile_parity : out std_ulogic_vector(0 to 3); + pc_bx_inj_inbox_ecc : out std_ulogic; + pc_bx_inj_outbox_ecc : out std_ulogic; + pc_xu_inj_llbust_attempt : out std_ulogic_vector(0 to 3); + pc_xu_inj_llbust_failed : out std_ulogic_vector(0 to 3); + pc_xu_inj_wdt_reset : out std_ulogic_vector(0 to 3); + pc_iu_inj_icachedir_multihit : out std_ulogic; + pc_xu_inj_dcachedir_multihit : out std_ulogic; + pc_xu_cache_par_err_event : out std_ulogic; +-- SCOM Register Interfaces +-- -- RAM Command/Data + pc_iu_ram_instr : out std_ulogic_vector(0 to 31); + pc_iu_ram_instr_ext : out std_ulogic_vector(0 to 3); + pc_iu_ram_mode : out std_ulogic; + pc_iu_ram_thread : out std_ulogic_vector(0 to 1); + pc_xu_ram_execute : out std_ulogic; + pc_xu_ram_mode : out std_ulogic; + pc_xu_ram_thread : out std_ulogic_vector(0 to 1); + xu_pc_ram_interrupt : in std_ulogic; + xu_pc_ram_done : in std_ulogic; + xu_pc_ram_data : in std_ulogic_vector(64-(2**regmode) to 63); + pc_fu_ram_mode : out std_ulogic; + pc_fu_ram_thread : out std_ulogic_vector(0 to 1); + fu_pc_ram_done : in std_ulogic; + fu_pc_ram_data : in std_ulogic_vector(0 to 63); + pc_xu_msrovride_enab : out std_ulogic; + pc_xu_msrovride_pr : out std_ulogic; + pc_xu_msrovride_gs : out std_ulogic; + pc_xu_msrovride_de : out std_ulogic; + pc_iu_ram_force_cmplt : out std_ulogic; + pc_xu_ram_flush_thread : out std_ulogic; +-- -- THRCTL + PCCR0 Register + pc_xu_stop : out std_ulogic_vector(0 to 3); + pc_xu_step : out std_ulogic_vector(0 to 3); + pc_xu_force_ude : out std_ulogic_vector(0 to 3); + pc_xu_dbg_action : out std_ulogic_vector(0 to 11); + xu_pc_running : in std_ulogic_vector(0 to 3); + xu_pc_stop_dbg_event : in std_ulogic_vector(0 to 3); + xu_pc_step_done : in std_ulogic_vector(0 to 3); + ct_rg_power_managed : in std_ulogic_vector(0 to 3); + ct_rg_pm_thread_stop : in std_ulogic_vector(0 to 3); + ac_an_pm_thread_running : out std_ulogic_vector(0 to 3); + an_ac_debug_stop : in std_ulogic; + pc_xu_extirpts_dis_on_stop : out std_ulogic; + pc_xu_timebase_dis_on_stop : out std_ulogic; + pc_xu_decrem_dis_on_stop : out std_ulogic; + ct_rg_hold_during_init : in std_ulogic; + rg_ct_dis_pwr_savings : out std_ulogic; +-- --Debug Select Register outputs to units for debug grouping + sp_rg_trace_bus_enable : in std_ulogic; + rg_db_trace_bus_enable : out std_ulogic; + pc_fu_trace_bus_enable : out std_ulogic; + pc_bx_trace_bus_enable : out std_ulogic; + pc_iu_trace_bus_enable : out std_ulogic; + pc_mm_trace_bus_enable : out std_ulogic; + pc_xu_trace_bus_enable : out std_ulogic; + rg_db_debug_mux_ctrls : out std_ulogic_vector(0 to 15); + pc_fu_debug_mux1_ctrls : out std_ulogic_vector(0 to 15); + pc_bx_debug_mux1_ctrls : out std_ulogic_vector(0 to 15); + pc_iu_debug_mux1_ctrls : out std_ulogic_vector(0 to 15); + pc_iu_debug_mux2_ctrls : out std_ulogic_vector(0 to 15); + pc_mm_debug_mux1_ctrls : out std_ulogic_vector(0 to 15); + pc_xu_debug_mux1_ctrls : out std_ulogic_vector(0 to 15); + pc_xu_debug_mux2_ctrls : out std_ulogic_vector(0 to 15); + pc_xu_debug_mux3_ctrls : out std_ulogic_vector(0 to 15); + pc_xu_debug_mux4_ctrls : out std_ulogic_vector(0 to 15); +-- Debug Signals to Trace/Trigger Muxes + dbg_scom_rdata : out std_ulogic_vector(0 to 63); + dbg_scom_wdata : out std_ulogic_vector(0 to 63); + dbg_scom_decaddr : out std_ulogic_vector(0 to 63); + dbg_scom_misc : out std_ulogic_vector(0 to 8); + dbg_ram_thrctl : out std_ulogic_vector(0 to 20); + dbg_fir0_err : out std_ulogic_vector(0 to 31); + dbg_fir1_err : out std_ulogic_vector(0 to 30); + dbg_fir2_err : out std_ulogic_vector(0 to 21); + dbg_fir_misc : out std_ulogic_vector(0 to 35) +); + +-- synopsys translate_off + + +-- synopsys translate_on +end pcq_regs; + +architecture pcq_regs of pcq_regs is + +--===================================================================== +-- Signal Declarations +--===================================================================== +constant rami_size : positive := 32; +constant ramc_size : positive := 20; +constant ramd_size : positive := 64; +constant thrctl1_size : positive := 16; +constant thrctl2_size : positive := 12; +constant pccr0_size : positive := 24; +constant recerrcntr_size : positive := 4; +constant spattn_size : positive := 4; +constant abdsr_size : positive := 32; +constant idsr_size : positive := 32; +constant mpdsr_size : positive := 32; +constant xdsr1_size : positive := 32; +constant xdsr2_size : positive := 32; +constant errinj_size : positive := 19; +constant parity_size : positive := 1; +constant scom_misc_size : positive := 6; +constant dcfg_stage1_size : positive := 5; +constant bcfg_stage1_size : positive := 13; +constant bcfg_stage2_size : positive := 15; +constant func_stage1_size : positive := 2; +constant func_stage2_size : positive := 32; +constant func_stage3_size : positive := 11; +constant fu_ram_din_size : positive := 64; +constant xu_ram_din_size : positive := 2**regmode+1; +----------------------------------------------------------------------- +-- Scan Ring Ordering: +-- start of dcfg scan chain ordering +constant abdsr_offset : natural := 0; +constant abdsr_par_offset : natural := abdsr_offset + abdsr_size; +constant idsr_offset : natural := abdsr_par_offset + parity_size; +constant idsr_par_offset : natural := idsr_offset + idsr_size; +constant mpdsr_offset : natural := idsr_par_offset + parity_size; +constant mpdsr_par_offset : natural := mpdsr_offset + mpdsr_size; +constant xdsr1_offset : natural := mpdsr_par_offset + parity_size; +constant xdsr1_par_offset : natural := xdsr1_offset + xdsr1_size; +constant xdsr2_offset : natural := xdsr1_par_offset + parity_size; +constant xdsr2_par_offset : natural := xdsr2_offset + xdsr2_size; +constant pccr0_offset : natural := xdsr2_par_offset + parity_size; +constant recerrcntr_offset : natural := pccr0_offset + pccr0_size; +constant pccr0_par_offset : natural := recerrcntr_offset + recerrcntr_size; +constant dcfg_stage1_offset : natural := pccr0_par_offset + parity_size; +constant dcfg_right : natural := dcfg_stage1_offset + dcfg_stage1_size - 1; +-- end of dcfg scan chain ordering +-- start of bcfg scan chain ordering +constant scommode_offset : natural := 0; +constant thrctl1_offset : natural := scommode_offset + 2; +constant thrctl2_offset : natural := thrctl1_offset + thrctl1_size; +constant spattn1_offset : natural := thrctl2_offset + thrctl2_size; +constant spattn2_offset : natural := spattn1_offset + spattn_size; +constant spattn_par_offset : natural := spattn2_offset + spattn_size; +constant bcfg_stage1_offset : natural := spattn_par_offset + parity_size; +constant bcfg_stage2_offset : natural := bcfg_stage1_offset + bcfg_stage1_size; +constant bcfg_right : natural := bcfg_stage2_offset + bcfg_stage2_size - 1; +-- end of bcfg scan chain ordering +-- start of func scan chain ordering +constant rami_offset : natural := 0; +constant ramc_offset : natural := rami_offset + rami_size; +constant ramd_offset : natural := ramc_offset + ramc_size; +constant fu_ram_din_offset : natural := ramd_offset + ramd_size; +constant xu_ram_din_offset : natural := fu_ram_din_offset + fu_ram_din_size; +constant errinj_offset : natural := xu_ram_din_offset + xu_ram_din_size; +constant sc_misc_offset : natural := errinj_offset + errinj_size; +constant scaddr_dec_offset : natural := sc_misc_offset + scom_misc_size; +constant func_stage1_offset : natural := scaddr_dec_offset + 64; +constant func_stage2_offset : natural := func_stage1_offset + func_stage1_size; +constant func_stage3_offset : natural := func_stage2_offset + func_stage2_size; +constant scomfunc_offset : natural := func_stage3_offset + func_stage3_size; +constant func_right : natural := scomfunc_offset + 177 - 1; +-- end of func scan chain ordering + +----------------------------------------------------------------------- +-- start of scom register addresses +constant scom_width : positive := 64; +-- 0000000000111111111122222222223333333333444444444455555555556666 +-- 0123456789012345678901234567890123456789012345678901234567890123 +constant use_addr : std_ulogic_vector := "1111111111111110111111111011100000000000111111111111111110011111"; +constant addr_is_rdable : std_ulogic_vector := "1001111001100110100110011010000000000000111001111001001000011111"; +constant addr_is_wrable : std_ulogic_vector := "1111101111111110111011111011100000000000111111111111111110011111"; +-- end of scom register addresses + +----------------------------------------------------------------------- +-- Basic/Misc signals +signal tidn, tiup : std_ulogic; +signal tidn_32 : std_ulogic_vector(0 to 31); +signal bcfg_siv, bcfg_sov : std_ulogic_vector(0 to bcfg_right); +signal dcfg_siv, dcfg_sov : std_ulogic_vector(0 to dcfg_right); +signal func_siv, func_sov : std_ulogic_vector(0 to func_right); +signal lcb_func_slp_sl_thold_0_b : std_ulogic; +signal lcb_cfg_slp_sl_thold_0_b : std_ulogic; +signal force_cfgslp : std_ulogic; +signal force_funcslp : std_ulogic; +signal cfgslp_d1clk : std_ulogic; +signal cfgslp_d2clk : std_ulogic; +signal cfgslp_lclk : clk_logic; +signal cfg_slat_force : std_ulogic; +signal cfg_slat_d2clk : std_ulogic; +signal cfg_slat_lclk : clk_logic; +signal cfg_slat_thold_b : std_ulogic; +-- SCOM satellite/decode signals +signal scom_cch_q, scom_dch_q : std_ulogic; +signal scom_act, scom_local_act : std_ulogic; +signal sc_r_nw : std_ulogic; +signal sc_ack : std_ulogic; +signal sc_rdata, sc_wdata : std_ulogic_vector(0 to 63); +signal sc_ack_info : std_ulogic_vector(0 to 1); +signal sc_wparity_out : std_ulogic; +signal sc_wparity : std_ulogic; +signal scom_fsm_err : std_ulogic; +signal scom_ack_err : std_ulogic; +signal scaddr_predecode : std_ulogic_vector(0 to 5); -- satid_nobits=5 (default) +signal scaddr_dec_d : std_ulogic_vector(0 to 63); +signal scaddr_v : std_ulogic_vector(0 to 63); +signal andmask_ones : std_ulogic_vector(0 to 63); +signal sc_req_d, sc_req_q : std_ulogic; +signal sc_wr_d, sc_wr_q : std_ulogic; +signal scaddr_v_d, scaddr_v_q : std_ulogic_vector(0 to 63); +signal scaddr_nvld_d, scaddr_nvld_q : std_ulogic; +signal sc_wr_nvld_d, sc_wr_nvld_q : std_ulogic; +signal sc_rd_nvld_d, sc_rd_nvld_q : std_ulogic; +-- RAM related signals +signal ramc_instr_in : std_ulogic_vector(0 to 3); +signal ramc_mode_in : std_ulogic_vector(0 to 2); +signal ramc_force_cmplt_in : std_ulogic; +signal ramc_force_flush_in : std_ulogic; +signal ramc_msr_de_ovrid_in : std_ulogic; +signal ramc_spare_in : std_ulogic_vector(0 to 2); +signal ramc_msr_ovrid_in : std_ulogic_vector(0 to 2); +signal ramc_execute_in : std_ulogic; +signal ramc_status_in : std_ulogic_vector(0 to 2); +signal or_ramc_load : std_ulogic; +signal and_ramc_ones : std_ulogic; +signal and_ramc_load : std_ulogic; +signal or_ramc : std_ulogic_vector(0 to 63); +signal and_ramc : std_ulogic_vector(0 to 63); +signal rami_d, rami_q : std_ulogic_vector(0 to rami_size-1); +signal rami_out : std_ulogic_vector(0 to 63); +signal ramc_d, ramc_q : std_ulogic_vector(0 to ramc_size-1); +signal ramc_out : std_ulogic_vector(0 to 63); +signal ramic_out : std_ulogic_vector(0 to 63); +signal ramd_d, ramd_q : std_ulogic_vector(0 to ramd_size-1); +signal ramdh_out, ramdl_out : std_ulogic_vector(0 to 63); +signal rg_rg_ram_mode : std_ulogic; +signal ramd_xu_load_zeros : std_ulogic_vector(0 to 64-(2**regmode)); +signal xu_ramd_load_data_d : std_ulogic_vector(0 to 64); +signal xu_ramd_load_data_q : std_ulogic_vector(0 to 64); +signal xu_ramd_load_data : std_ulogic_vector(0 to 63); +signal fu_ramd_load_data_d : std_ulogic_vector(0 to 63); +signal fu_ramd_load_data_q : std_ulogic_vector(0 to 63); +signal xu_ram_done_q : std_ulogic; +signal fu_ram_done_q : std_ulogic; +signal ram_mode_d, ram_mode_q : std_ulogic; +signal ram_execute_d, ram_execute_q : std_ulogic; +signal ram_thread_d, ram_thread_q : std_ulogic_vector(0 to 1); +signal ram_msrovren_d, ram_msrovren_q : std_ulogic; +signal ram_msrovrpr_d, ram_msrovrpr_q : std_ulogic; +signal ram_msrovrgs_d, ram_msrovrgs_q : std_ulogic; +signal ram_msrovrde_d, ram_msrovrde_q : std_ulogic; +signal ram_force_d, ram_force_q : std_ulogic; +signal ram_flush_d, ram_flush_q : std_ulogic; +-- THRCTL related signals +signal or_thrctl_load : std_ulogic; +signal and_thrctl_ones : std_ulogic; +signal and_thrctl_load : std_ulogic; +signal or_thrctl : std_ulogic_vector(0 to 63); +signal and_thrctl : std_ulogic_vector(0 to 63); +signal thrctl_out : std_ulogic_vector(0 to 63); +signal thrctl1_d, thrctl1_q : std_ulogic_vector(0 to thrctl1_size-1); +signal thrctl2_d, thrctl2_q : std_ulogic_vector(0 to thrctl2_size-1); +signal thrctl_stop_in : std_ulogic_vector(0 to 3); +signal thrctl_step_in : std_ulogic_vector(0 to 3); +signal thrctl_run_in : std_ulogic_vector(0 to 3); +signal thrctl_pm_in : std_ulogic_vector(0 to 3); +signal thrctl_misc_dbg_in : std_ulogic_vector(0 to 6); +signal thrctl_spare_in : std_ulogic_vector(0 to 4); +signal tx_stop_d, tx_stop_q : std_ulogic_vector(0 to 3); +signal tx_step_d, tx_step_q : std_ulogic_vector(0 to 3); +signal tx_ude_d, tx_ude_q : std_ulogic_vector(0 to 3); +signal ude_dly_d, ude_dly_q : std_ulogic_vector(0 to 3); +signal force_ude_pulse : std_ulogic_vector(0 to 3); +signal extirpts_dis_d, extirpts_dis_q : std_ulogic; +signal timebase_dis_d, timebase_dis_q : std_ulogic; +signal decrem_dis_d, decrem_dis_q : std_ulogic; +signal ext_debug_stop_q : std_ulogic; +signal external_debug_stop : std_ulogic_vector(0 to 3); +signal stop_dbg_event_q : std_ulogic_vector(0 to 3); +signal step_done_q : std_ulogic_vector(0 to 3); +-- PCCR0 related signals +signal or_pccr0_load : std_ulogic; +signal and_pccr0_ones : std_ulogic; +signal and_pccr0_load : std_ulogic; +signal or_pccr0 : std_ulogic_vector(0 to 63); +signal and_pccr0 : std_ulogic_vector(0 to 63); +signal pccr0_out : std_ulogic_vector(0 to 63); +signal pccr0_par_err : std_ulogic; +signal pccr0_par_in : std_ulogic_vector(0 to pccr0_size+4-1); +signal pccr0_d, pccr0_q : std_ulogic_vector(0 to pccr0_size-1); +signal pccr0_par_d, pccr0_par_q : std_ulogic_vector(0 to 0); +signal debug_mode_d, debug_mode_q : std_ulogic; +signal debug_mode_act : std_ulogic; +signal trace_bus_enable_d : std_ulogic; +signal trace_bus_enable_q : std_ulogic; +signal ram_enab_d, ram_enab_q : std_ulogic; +signal ram_enab_act : std_ulogic; +signal ram_enab_scom_act : std_ulogic; +signal errinj_enab_d, errinj_enab_q : std_ulogic; +signal errinj_enab_act : std_ulogic; +signal errinj_enab_scom_act : std_ulogic; +signal rg_rg_xstop_report_ovride : std_ulogic; +signal rg_rg_fast_xstop_enable : std_ulogic; +signal rg_rg_maxRecErrCntrValue : std_ulogic; +signal rg_rg_gateRecErrCntr : std_ulogic; +signal recErrCntr_pargen : std_ulogic; +signal incr_recErrCntr : std_ulogic_vector(0 to 3); +signal recErrCntr_in : std_ulogic_vector(0 to 3); +signal recErrCntr_q : std_ulogic_vector(0 to 3); +signal pccr0_pervModes_in : std_ulogic_vector(0 to 6); +signal pccr0_spare_in : std_ulogic_vector(0 to 4); +signal pccr0_dbgActSel_in : std_ulogic_vector(0 to 11); +-- spattn related signals +signal or_spattn_load : std_ulogic; +signal and_spattn_ones : std_ulogic; +signal and_spattn_load : std_ulogic; +signal or_spattn : std_ulogic_vector(0 to 63); +signal and_spattn : std_ulogic_vector(0 to 63); +signal spattn_out : std_ulogic_vector(0 to 63); +signal spattn_par_err : std_ulogic; +signal spattn_par_d, spattn_par_q : std_ulogic_vector(0 to 0); +signal spattn_data_d, spattn_data_q : std_ulogic_vector(0 to spattn_size-1); +signal spattn_mask_d, spattn_mask_q : std_ulogic_vector(0 to spattn_size-1); +signal spattn_unused : std_ulogic_vector(spattn_size to 15); +signal spattn_attn_instr_in : std_ulogic_vector(0 to 3); +signal spattn_out_masked : std_ulogic_vector(0 to spattn_size-1); +-- Debug related signals +signal abdsr_data_in : std_ulogic_vector(0 to abdsr_size-1); +signal abdsr_out : std_ulogic_vector(0 to 63); +signal abdsr_par_err : std_ulogic; +signal abdsr_d, abdsr_q : std_ulogic_vector(0 to abdsr_size-1); +signal abdsr_par_d, abdsr_par_q : std_ulogic_vector(0 to 0); +signal idsr_data_in : std_ulogic_vector(0 to idsr_size-1); +signal idsr_out : std_ulogic_vector(0 to 63); +signal idsr_par_err : std_ulogic; +signal idsr_d, idsr_q : std_ulogic_vector(0 to idsr_size-1); +signal idsr_par_d, idsr_par_q : std_ulogic_vector(0 to 0); +signal mpdsr_data_in : std_ulogic_vector(0 to mpdsr_size-1); +signal mpdsr_out : std_ulogic_vector(0 to 63); +signal mpdsr_par_err : std_ulogic; +signal mpdsr_d, mpdsr_q : std_ulogic_vector(0 to mpdsr_size-1); +signal mpdsr_par_d, mpdsr_par_q : std_ulogic_vector(0 to 0); +signal xdsr1_data_in : std_ulogic_vector(0 to xdsr1_size-1); +signal xdsr1_out : std_ulogic_vector(0 to 63); +signal xdsr1_par_err_d : std_ulogic; +signal xdsr1_par_err_q : std_ulogic; +signal xdsr1_d, xdsr1_q : std_ulogic_vector(0 to xdsr1_size-1); +signal xdsr1_par_d, xdsr1_par_q : std_ulogic_vector(0 to 0); +signal xdsr2_data_in : std_ulogic_vector(0 to xdsr2_size-1); +signal xdsr2_out : std_ulogic_vector(0 to 63); +signal xdsr2_par_err : std_ulogic; +signal xdsr2_d, xdsr2_q : std_ulogic_vector(0 to xdsr2_size-1); +signal xdsr2_par_d, xdsr2_par_q : std_ulogic_vector(0 to 0); +-- FIR + Error related signals +signal errinj_out : std_ulogic_vector(0 to 63); +signal errinj_thread_in : std_ulogic_vector(0 to 3); +signal errinj_errtype_in : std_ulogic_vector(0 to 14); +signal errinj_d, errinj_q : std_ulogic_vector(0 to errinj_size-1); +signal attn_instr_int : std_ulogic_vector(0 to 3); +signal rg_rg_ram_mode_xstop : std_ulogic; +signal rg_rg_xstop_err : std_ulogic_vector(0 to 3); +signal rg_rg_any_fir_xstop : std_ulogic; +signal scom_reg_par_checks : std_ulogic_vector(0 to 6); +signal scaddr_fir : std_ulogic; +signal fir_func_si, fir_func_so : std_ulogic; +signal fir_mode_si, fir_mode_so : std_ulogic; +signal fir_data_out : std_ulogic_vector(0 to 63); +signal rg_rg_errinj_shutoff : std_ulogic_vector(0 to 14); +signal sc_parity_error_inject : std_ulogic; +signal inj_icache_parity_d : std_ulogic; +signal inj_icache_parity_q : std_ulogic; +signal inj_icachedir_parity_d : std_ulogic; +signal inj_icachedir_parity_q : std_ulogic; +signal inj_dcache_parity_d : std_ulogic; +signal inj_dcache_parity_q : std_ulogic; +signal inj_dcachedir_parity_d : std_ulogic; +signal inj_dcachedir_parity_q : std_ulogic; +signal inj_xuregfile_parity_d : std_ulogic_vector(0 to 3); +signal inj_xuregfile_parity_q : std_ulogic_vector(0 to 3); +signal inj_furegfile_parity_d : std_ulogic_vector(0 to 3); +signal inj_furegfile_parity_q : std_ulogic_vector(0 to 3); +signal inj_icachedir_multihit_d : std_ulogic; +signal inj_icachedir_multihit_q : std_ulogic; +signal inj_dcachedir_multihit_d : std_ulogic; +signal inj_dcachedir_multihit_q : std_ulogic; +signal inj_sprg_ecc_d : std_ulogic_vector(0 to 3); +signal inj_sprg_ecc_q : std_ulogic_vector(0 to 3); +signal inj_inbox_ecc_d : std_ulogic; +signal inj_inbox_ecc_q : std_ulogic; +signal inj_outbox_ecc_d : std_ulogic; +signal inj_outbox_ecc_q : std_ulogic; +signal inj_llbust_attempt_d : std_ulogic_vector(0 to 3); +signal inj_llbust_attempt_q : std_ulogic_vector(0 to 3); +signal inj_llbust_failed_d : std_ulogic_vector(0 to 3); +signal inj_llbust_failed_q : std_ulogic_vector(0 to 3); +signal inj_wdt_reset_d : std_ulogic_vector(0 to 3); +signal inj_wdt_reset_q : std_ulogic_vector(0 to 3); +signal unused_signals : std_ulogic; + +----------------------------------------------------------------------- + + + +begin + + + tidn <= '0'; + tidn_32 <= (others => '0'); + tiup <= '1'; + +unused_signals <= or_reduce(or_ramc(0 to 31) & or_ramc(36 to 43) & or_ramc(56 to 60) & + and_ramc(0 to 31) & and_ramc(36 to 43) & and_ramc(47) & + and_ramc(52) & and_ramc(56 to 60) & + or_thrctl(0 to 31) & or_thrctl(40 to 47) & or_thrctl(60 to 63) & + and_thrctl(0 to 31) & and_thrctl(40 to 47) & and_thrctl(60 to 63) & + or_pccr0(0 to 31) & or_pccr0(44 to 51) & + and_pccr0(0 to 31) & and_pccr0(44 to 51) & + or_spattn(0 to 31) & or_spattn(36 to 47) & or_spattn(52 to 63) & + and_spattn(0 to 31) & and_spattn(36 to 47) & and_spattn(52 to 63) & + xu_ramd_load_data_q(0)); + + + +--===================================================================== +-- SCOM Satellite and Controls +--===================================================================== + scomsat: entity tri.tri_serial_scom2 + generic map(width => scom_width, + internal_addr_decode => false, + pipeline_paritychk => false, + expand_type => expand_type ) + port map( -- Global lines for clocking and cop control + nclk => nclk + , vd => vdd + , gd => gnd + , scom_func_thold => lcb_func_slp_sl_thold_0 + , sg => lcb_sg_0 + , act_dis_dc => lcb_act_dis_dc + , clkoff_dc_b => lcb_clkoff_dc_b + , mpw1_dc_b => lcb_mpw1_dc_b + , mpw2_dc_b => lcb_mpw2_dc_b + , d_mode_dc => lcb_d_mode_dc + , delay_lclkr_dc => lcb_delay_lclkr_dc + , func_scan_in => func_siv(scomfunc_offset to scomfunc_offset + scom_width+2*((scom_width-1)/16+1)+104) + , func_scan_out => func_sov(scomfunc_offset to scomfunc_offset + scom_width+2*((scom_width-1)/16+1)+104) + , dcfg_scan_dclk => cfg_slat_d2clk + , dcfg_scan_lclk => cfg_slat_lclk + , dcfg_d1clk => cfgslp_d1clk + , dcfg_d2clk => cfgslp_d2clk + , dcfg_lclk => cfgslp_lclk + , dcfg_scan_in => bcfg_siv(scommode_offset to scommode_offset + 1) + , dcfg_scan_out => bcfg_sov(scommode_offset to scommode_offset + 1) + , scom_local_act => scom_local_act + --------------------------------------------------------------------- + -- Global SCOM interface + --------------------------------------------------------------------- + -- tie to VDD/GND to program the base address ranges + , sat_id => an_ac_scom_sat_id + --global serial lines to top level of macro + , scom_dch_in => scom_dch_q + , scom_cch_in => scom_cch_q + , scom_dch_out => ac_an_scom_dch + , scom_cch_out => ac_an_scom_cch + --------------------------------------------------------------------- + -- Internal SCOM interface to parallel registers + --------------------------------------------------------------------- + -- address/control interface + , sc_req => sc_req_d + , sc_ack => sc_ack + , sc_ack_info => sc_ack_info + , sc_r_nw => sc_r_nw + , sc_addr => scaddr_predecode + , sc_rdata => sc_rdata + , sc_wdata => sc_wdata + , sc_wparity => sc_wparity_out + , scom_err => scom_fsm_err + , fsm_reset => tidn + ); + + + scaddr: entity clib.c_scom_addr_decode + generic map( use_addr => use_addr + , addr_is_rdable => addr_is_rdable + , addr_is_wrable => addr_is_wrable + ) + port map( sc_addr => scaddr_predecode -- binary coded scom address + , scaddr_dec => scaddr_dec_d -- one hot coded scom address, not latched + , sc_req => sc_req_d -- scom request + , sc_r_nw => sc_r_nw -- read / not write bit + , scaddr_nvld => scaddr_nvld_d -- scom address not valid; not latched + , sc_wr_nvld => sc_wr_nvld_d -- scom write not allowed, not latched + , sc_rd_nvld => sc_rd_nvld_d -- scom read not allowed, not latched + , vd => vdd + , gd => gnd + ); + + scom_act <= sc_req_d or sc_req_q or scom_local_act; + + sc_wr_d <= not sc_r_nw; + + scaddr_v_d <= gate_and(sc_req_d, scaddr_dec_d); + scaddr_v <= scaddr_v_q; + + sc_ack <= (sc_req_d and not sc_r_nw) or (sc_req_q and sc_r_nw); + + sc_ack_info <= gate_and(not sc_r_nw, (sc_wr_nvld_d or sc_rd_nvld_d) & scaddr_nvld_d) or + gate_and(sc_r_nw, (sc_wr_nvld_q or sc_rd_nvld_q) & scaddr_nvld_q) ; + + scom_ack_err <= or_reduce(sc_ack_info); + + sc_wparity <= sc_wparity_out xor sc_parity_error_inject; + + +--===================================================================== +-- SCOM Register Writes +--===================================================================== + andmask_ones <= (others => '1'); + +----------------------------------------------------------------------- +-- RAM Instruction Register ------------------------------------------- + -- RAMIC RW address = 40 + -- RAMI RW address = 41 + + rami_d(0 to 31) <= sc_wdata(0 to 31) when (scaddr_v(40) and sc_wr_q) = '1' else + sc_wdata(32 to 63) when (scaddr_v(41) and sc_wr_q) = '1' else + rami_q(0 to 31); + + rami_out <= tidn_32 & rami_q(0 to 31); + + ramic_out <= rami_out(32 to 63) & ramc_out(32 to 63); + + +----------------------------------------------------------------------- +-- RAM Control Register ----------------------------------------------- + -- RAMIC RW address = 40 + -- RAMC RW address = 42 + -- RAMC WO with and-mask = 43 + -- RAMC WO with or-mask = 44 + + or_ramc_load <= (scaddr_v(40) or scaddr_v(42) or scaddr_v(44)) and sc_wr_q; + and_ramc_ones <= not((scaddr_v(40) or scaddr_v(42) or scaddr_v(43)) and sc_wr_q); + and_ramc_load <= scaddr_v(43) and sc_wr_q; + + or_ramc <= gate_and(or_ramc_load, sc_wdata); + and_ramc <= gate_and(and_ramc_load, sc_wdata) or gate_and(and_ramc_ones, andmask_ones); + + + -- Instruction fields: set by SCOM; reset by SCOM + ramc_instr_in <= or_ramc(32 to 35) or (ramc_out(32 to 35) and and_ramc(32 to 35)); + + -- Mode/Thread bits: set by SCOM; reset by SCOM + ramc_mode_in <= or_ramc(44 to 46) or (ramc_out(44 to 46) and and_ramc(44 to 46)); + + -- Execute bit: not latched; pulsed by SCOM write + ramc_execute_in <= or_ramc(47); + + -- MSR Override control bits: set by SCOM; reset by SCOM + ramc_msr_ovrid_in <= or_ramc(48 to 50) or (ramc_out(48 to 50) and and_ramc(48 to 50)); + + -- Force Ram Completion bit: set by SCOM; reset by SCOM + ramc_force_cmplt_in <= or_ramc(51) or (ramc_out(51) and and_ramc(51)); + + -- Force Flush bit: not latched; pulsed by SCOM write. + ramc_force_flush_in <= or_ramc(52); + + -- MSR[DE] override control bit: set by SCOM; reset by SCOM + ramc_msr_de_ovrid_in <= or_ramc(53) or (ramc_out(53) and and_ramc(53)); + + -- Spare bits: set by SCOM; reset by SCOM + ramc_spare_in <= or_ramc(54 to 56) or (ramc_out(54 to 56) and and_ramc(54 to 56)); + + -- Interrupt bit: set by SCOM + xu interrupt signal; reset by SCOM + ramc_status_in(0) <= xu_pc_ram_interrupt or or_ramc(61) or (ramc_out(61) and and_ramc(61)); + + -- Error bit: set by SCOM + RAMed threads checkstop bit; reset by SCOM + ramc_status_in(1) <= rg_rg_ram_mode_xstop or or_ramc(62) or (ramc_out(62) and and_ramc(62)); + + -- Done bit: set by SCOM + xu/fu Done signals; reset by SCOM + RAMC_execute + ramc_status_in(2) <= xu_ram_done_q or fu_ram_done_q or or_ramc(63) or + (ramc_out(63) and and_ramc(63) and not ramc_out(47)); + + + ramc_d <= ramc_instr_in & ramc_mode_in & ramc_execute_in & ramc_msr_ovrid_in & ramc_force_cmplt_in & + ramc_force_flush_in & ramc_msr_de_ovrid_in & ramc_spare_in & ramc_status_in; + + -- Instr Extension Mode/Thread/Exec MSR Ovrids/Force + ramc_out <= tidn_32 & ramc_q(0 to 3) & x"00" & ramc_q(4 to 7) & ramc_q(8 to 13) & + -- Spare Latches Status + ramc_q(14 to 16) & "0000" & ramc_q(17 to 19); + + +----------------------------------------------------------------------- +-- RAM Data Register ------------------------------------------------- + -- RAMD R/W address = 45 + -- RAMDH R/W address = 46 + -- RAMDL R/W address = 47 + + + fu_ramd_load_data_d <= fu_pc_ram_data(0 to 63); + + -- For XU, adjusting size of RAM data when compiled as 32-bit core. + ramd_xu_load_zeros(0 to 64-(2**regmode)) <= (others => '0'); + xu_ramd_load_data_d(0 to 64) <= ramd_xu_load_zeros & xu_pc_ram_data(64-(2**regmode) to 63); + xu_ramd_load_data(0 to 63) <= xu_ramd_load_data_q(1 to 64); + + -- Latch Ram data from SCOM, or FU/XU Ram data buses. + ramd_d(0 to 31) <= sc_wdata(0 to 31) when (scaddr_v(45) and sc_wr_q) = '1' else + sc_wdata(32 to 63) when (scaddr_v(46) and sc_wr_q) = '1' else + fu_ramd_load_data_q(0 to 31) when fu_ram_done_q = '1' else + xu_ramd_load_data(0 to 31) when xu_ram_done_q = '1' else + ramd_q(0 to 31); + + ramd_d(32 to 63) <= sc_wdata(32 to 63) when (scaddr_v(45) and sc_wr_q) = '1' else + sc_wdata(32 to 63) when (scaddr_v(47) and sc_wr_q) = '1' else + fu_ramd_load_data_q(32 to 63) when fu_ram_done_q = '1' else + xu_ramd_load_data(32 to 63) when xu_ram_done_q = '1' else + ramd_q(32 to 63); + + ramdh_out <= tidn_32 & ramd_q(0 to 31); + + ramdl_out <= tidn_32 & ramd_q(32 to 63); + + +----------------------------------------------------------------------- +-- Thread Control Register + -- THRCTL RW address = 48 + -- THRCTL WO with and-mask = 49 + -- THRCTL WO with or-mask = 50 + + or_thrctl_load <= (scaddr_v(48) or scaddr_v(50)) and sc_wr_q; + and_thrctl_ones <= not((scaddr_v(48) or scaddr_v(49)) and sc_wr_q); + and_thrctl_load <= scaddr_v(49) and sc_wr_q; + + or_thrctl <= gate_and(or_thrctl_load, sc_wdata); + and_thrctl <= gate_and(and_thrctl_load, sc_wdata) or gate_and(and_thrctl_ones, andmask_ones); + + + -- Stop bit: set by SCOM + misc stop signals; reset by SCOM + thrctl_stop_in <= stop_dbg_event_q(0 to 3) or attn_instr_int(0 to 3) or + rg_rg_xstop_err(0 to 3) or + or_thrctl(32 to 35) or (thrctl_out(32 to 35) and and_thrctl(32 to 35)) ; + + -- Step bit: set by SCOM; reset by SCOM or xu_pc_step_done + thrctl_step_in <= or_thrctl(36 to 39) or + (thrctl_out(36 to 39) and and_thrctl(36 to 39) and not step_done_q(0 to 3)); + + -- Run bit: controlled by external status input + thrctl_run_in <= xu_pc_running(0 to 3); + + -- PM bit: controlled by "power managed" status signals + thrctl_pm_in <= ct_rg_power_managed(0 to 3) or ct_rg_pm_thread_stop(0 to 3); + + -- Misc Debug Ctrl bits: set by SCOM; reset by SCOM + thrctl_misc_dbg_in <= or_thrctl(48 to 54) or (thrctl_out(48 to 54) and and_thrctl(48 to 54)); + + -- Spare bits: set by SCOM; reset by SCOM + thrctl_spare_in <= or_thrctl(55 to 59) or (thrctl_out(55 to 59) and and_thrctl(55 to 59)); + + + thrctl1_d <= thrctl_stop_in & thrctl_step_in & thrctl_run_in & thrctl_pm_in; + thrctl2_d <= thrctl_misc_dbg_in & thrctl_spare_in; + + -- Stop(32:35) Step(36:39) Run(40:43) + thrctl_out <= tidn_32 & thrctl1_q(0 to 3) & thrctl1_q(4 to 7) & thrctl1_q(8 to 11) & + -- PM(44:47) Misc_Debug(48:54) Spare Ltchs(55:59) + thrctl1_q(12 to 15) & thrctl2_q(0 to 6) & thrctl2_q(7 to 11) & x"0"; + + +----------------------------------------------------------------------- +-- PC Unit Configuration Register 0 + -- PCCR0 RW address = 51 + -- PCCR0 WO with and-mask = 52 + -- PCCR0 WO with or-mask = 53 + + or_pccr0_load <= (scaddr_v(51) or scaddr_v(53)) and sc_wr_q; + and_pccr0_ones <= not((scaddr_v(51) or scaddr_v(52)) and sc_wr_q); + and_pccr0_load <= scaddr_v(52) and sc_wr_q; + + or_pccr0 <= gate_and(or_pccr0_load, sc_wdata); + and_pccr0 <= gate_and(and_pccr0_load, sc_wdata) or gate_and(and_pccr0_ones, andmask_ones); + + + -- PCCR0(32:38) are pervasive modes and miscellaneous controls: + -- 32 = Enable Debug mode + -- 33 = Enable Ram mode + -- 34 = Enable Error Inject mode + -- 35 = Enable External Debug Stop + -- 36 = Disable xstop reporting in Ram mode + -- 37 = Enable fast clockstop + -- 38 = Disable power savings + pccr0_pervModes_in <= or_pccr0(32 to 38) or (pccr0_out(32 to 38) and and_pccr0(32 to 38)); + + -- Spare bits: set by SCOM; reset by SCOM + pccr0_spare_in <= or_pccr0(39 to 43) or (pccr0_out(39 to 43) and and_pccr0(39 to 43)); + + + -- PCCR0(48:51) is the Recoverable Error Counter + -- Incremented when gated by a new recoverable error; PCCR0 parity recalculated. + incr_recErrCntr <= recErrCntr_q(0 to 3) + "0001"; + recErrCntr_pargen <= xor_reduce(incr_recErrCntr & pccr0_out(32 to 43) & pccr0_out(52 to 63)); + + recErrCntr_in <= sc_wdata(48 to 51) when (scaddr_v(51) and sc_wr_q) = '1' else + incr_recErrCntr when rg_rg_gateRecErrCntr = '1' else + recErrCntr_q(0 to 3); + + + -- PCCR0(52:63) are the Debug Action Selects: + pccr0_dbgActSel_in <= or_pccr0(52 to 63) or (pccr0_out(52 to 63) and and_pccr0(52 to 63)); + + + -- Load Register + pccr0_d <= pccr0_pervModes_in & pccr0_spare_in & pccr0_dbgActSel_in; + + pccr0_out <= tidn_32 & pccr0_q(0 to 11) & x"0" & recErrCntr_q & pccr0_q(12 to pccr0_size-1); + + -- Parity Bit + pccr0_par_in <= pccr0_d & recErrCntr_in(0 to 3); + pccr0_par_d(0) <= parity_gen_even(pccr0_par_in) when (gate_and(sc_wr_q, or_reduce(scaddr_v(51 to 53))))='1' else + recErrCntr_pargen when rg_rg_gateRecErrCntr = '1' else + pccr0_par_q(0); + + pccr0_par_err <= (xor_reduce(pccr0_out) xor pccr0_par_q(0)) or + (sc_wr_q and or_reduce(scaddr_v(51 to 53)) and sc_parity_error_inject); + + + +----------------------------------------------------------------------- +-- Special Attention and Mask Register + -- SPATTN RW address = 54 + -- SPATTN WO with and-mask = 55 + -- SPATTN WO with or-mask = 56 + + or_spattn_load <= (scaddr_v(54) or scaddr_v(56)) and sc_wr_q; + and_spattn_ones <= not((scaddr_v(54) or scaddr_v(55)) and sc_wr_q); + and_spattn_load <= scaddr_v(55) and sc_wr_q; + + or_spattn <= gate_and(or_spattn_load, sc_wdata); + and_spattn <= gate_and(and_spattn_load, sc_wdata) or gate_and(and_spattn_ones, andmask_ones); + + spattn_unused <= (others => '0'); + + + -- Special Attention Data: + -- attn_instr: Attention signal generated by attn instruction + spattn_attn_instr_in <= attn_instr_int(0 to 3) or or_spattn(32 to 35) or + (spattn_out(32 to 35) and and_spattn(32 to 35)) ; + + + + spattn_data_d <= spattn_attn_instr_in; + + + -- Special Attention Mask: set by SCOM; reset by SCOM + spattn_mask_d <= or_spattn(48 to (48 + spattn_size-1)) or + (spattn_out(48 to (48 + spattn_size-1)) and and_spattn(48 to (48 + spattn_size-1))); + + spattn_out <= tidn_32 & spattn_data_q & spattn_unused & spattn_mask_q & spattn_unused ; + + + -- Parity Bit + spattn_par_d(0) <= parity_gen_even(spattn_mask_d) when (gate_and(sc_wr_q, or_reduce(scaddr_v(54 to 56))))='1' else + spattn_par_q(0); + + spattn_par_err <= (xor_reduce(spattn_mask_q) xor spattn_par_q(0)) or + (sc_wr_q and or_reduce(scaddr_v(54 to 56)) and sc_parity_error_inject); + + +----------------------------------------------------------------------- +-- Debug Select Registers + -- ABDSR RW address = 59 + -- IDSR RW address = 60 + -- MPDSR RW address = 61 + -- XDSR1 RW address = 62 + -- XDSR2 RW address = 63 + + abdsr_data_in <= sc_wdata(32 to 63) when (scaddr_v(59) and sc_wr_q) = '1' else abdsr_out(32 to 63); + abdsr_d <= abdsr_data_in; + -- AXU + BX debug + trigger mux controls + abdsr_out <= tidn_32 & abdsr_q(0 to 31); + -- Parity Bit + abdsr_par_d(0) <= sc_wparity when (scaddr_v(59) and sc_wr_q) = '1' else abdsr_par_q(0); + abdsr_par_err <= xor_reduce(abdsr_q) xor abdsr_par_q(0); + + + idsr_data_in <= sc_wdata(32 to 63) when (scaddr_v(60) and sc_wr_q) = '1' else idsr_out(32 to 63); + idsr_d <= idsr_data_in; + -- IU debug + trigger mux controls + idsr_out <= tidn_32 & idsr_q(0 to 31); + -- Parity Bit + idsr_par_d(0) <= sc_wparity when (scaddr_v(60) and sc_wr_q) = '1' else idsr_par_q(0); + idsr_par_err <= xor_reduce(idsr_q) xor idsr_par_q(0); + + + mpdsr_data_in <= sc_wdata(32 to 63) when (scaddr_v(61) and sc_wr_q) = '1' else mpdsr_out(32 to 63); + mpdsr_d <= mpdsr_data_in; + -- MMU + PC debug + trigger mux controls + mpdsr_out <= tidn_32 & mpdsr_q(0 to 31); + -- Parity Bit + mpdsr_par_d(0) <= sc_wparity when (scaddr_v(61) and sc_wr_q) = '1' else mpdsr_par_q(0); + mpdsr_par_err <= xor_reduce(mpdsr_q) xor mpdsr_par_q(0); + + + xdsr1_data_in <= sc_wdata(32 to 63) when (scaddr_v(62) and sc_wr_q) = '1' else xdsr1_out(32 to 63); + xdsr1_d <= xdsr1_data_in; + -- XU Mux1+2 debug + trigger mux controls + xdsr1_out <= tidn_32 & xdsr1_q(0 to 31); + -- Parity Bit + xdsr1_par_d(0) <= sc_wparity when (scaddr_v(62) and sc_wr_q) = '1' else xdsr1_par_q(0); + xdsr1_par_err_d <= xor_reduce(xdsr1_q) xor xdsr1_par_q(0); + + + xdsr2_data_in <= sc_wdata(32 to 63) when (scaddr_v(63) and sc_wr_q) = '1' else xdsr2_out(32 to 63); + xdsr2_d <= xdsr2_data_in; + -- XU Mux3+4 debug + trigger mux controls + xdsr2_out <= tidn_32 & xdsr2_q(0 to 31); + -- Parity Bit + xdsr2_par_d(0) <= sc_wparity when (scaddr_v(63) and sc_wr_q) = '1' else xdsr2_par_q(0); + xdsr2_par_err <= xor_reduce(xdsr2_q) xor xdsr2_par_q(0); + + +----------------------------------------------------------------------- +-- Error Inject Register + -- ERRINJ RW address = 9 + errinj_thread_in <= sc_wdata(32 to 35) when (scaddr_v(9) and sc_wr_q) = '1' else + errinj_out(32 to 35); + + errinj_errtype_in <= sc_wdata(40 to 54) when (scaddr_v(9) and sc_wr_q) = '1' else + (errinj_out(40 to 54) and not rg_rg_errinj_shutoff); + + errinj_d <= errinj_thread_in & errinj_errtype_in; + + -- Thread Select Rsvd Error Inject Sel + errinj_out <= tidn_32 & errinj_q(0 to 3) & "0000" & errinj_q(4 to 18) & (55 to 63 => '0'); + + +--===================================================================== +-- SCOM Register Read +--===================================================================== + scaddr_fir <= scaddr_v(0) or scaddr_v(3) or scaddr_v(4) or scaddr_v(6) or + scaddr_v(5) or scaddr_v(19) or + scaddr_v(10) or scaddr_v(13) or scaddr_v(14) or scaddr_v(16) or + scaddr_v(20) or scaddr_v(23) or scaddr_v(24) or scaddr_v(26); + + sc_rdata <= gate_and(scaddr_v(40), ramic_out) or + gate_and(scaddr_v(41), rami_out) or + gate_and(scaddr_v(42), ramc_out) or + gate_and(scaddr_v(45), ramd_q(0 to 63)) or + gate_and(scaddr_v(46), ramdh_out) or + gate_and(scaddr_v(47), ramdl_out) or + gate_and(scaddr_v(48), thrctl_out) or + gate_and(scaddr_v(51), pccr0_out) or + gate_and(scaddr_v(54), spattn_out) or + gate_and(scaddr_v(59), abdsr_out) or + gate_and(scaddr_v(60), idsr_out) or + gate_and(scaddr_v(61), mpdsr_out) or + gate_and(scaddr_v(62), xdsr1_out) or + gate_and(scaddr_v(63), xdsr2_out) or + gate_and(scaddr_v(9), errinj_out) or + gate_and(scaddr_fir, fir_data_out) ; + + + +--===================================================================== +-- Output + Signal Assignments +--===================================================================== +-- RAM Command Signals + ram_mode_d <= ram_enab_d and ramc_out(44); + ram_execute_d <= ram_mode_d and ramc_out(47); + ram_thread_d <= ramc_out(45 to 46); + + pc_iu_ram_instr <= rami_out(32 to 63); + pc_iu_ram_instr_ext <= ramc_out(32 to 35); + pc_iu_ram_mode <= ram_mode_q; + pc_iu_ram_thread <= ram_thread_q(0 to 1); + + pc_xu_ram_mode <= ram_mode_q; + pc_xu_ram_thread <= ram_thread_q(0 to 1); + pc_xu_ram_execute <= ram_execute_q; + + pc_fu_ram_mode <= ram_mode_q; + pc_fu_ram_thread <= ram_thread_q(0 to 1); + + rg_rg_ram_mode <= ram_mode_q; + + + ram_msrovren_d <= ram_mode_d and ramc_out(48); + pc_xu_msrovride_enab <= ram_msrovren_q; + + ram_msrovrpr_d <= ram_mode_d and ramc_out(49); + pc_xu_msrovride_pr <= ram_msrovrpr_q; + + ram_msrovrgs_d <= ram_mode_d and ramc_out(50); + pc_xu_msrovride_gs <= ram_msrovrgs_q; + + ram_force_d <= ram_mode_d and ramc_out(51); + pc_iu_ram_force_cmplt <= ram_force_q; + + ram_flush_d <= ram_enab_d and ramc_out(52); + pc_xu_ram_flush_thread <= ram_flush_q; + + ram_msrovrde_d <= ram_mode_d and ramc_out(53); + pc_xu_msrovride_de <= ram_msrovrde_q; + +----------------------------------------------------------------------- +-- Thread Control Signals + -- an_ac_debug_stop, when enabled, forces all threads to stop + external_debug_stop <= gate_and(pccr0_out(35), (0 to 3=> ext_debug_stop_q)); + + tx_stop_d <= ct_rg_pm_thread_stop or external_debug_stop or + (0 to 3 => ct_rg_hold_during_init) or + (thrctl_out(32 to 35) and not tx_step_d(0 to 3)); + pc_xu_stop <= tx_stop_q(0 to 3); + + tx_step_d <= gate_and(debug_mode_d, thrctl_out(36 to 39)); + pc_xu_step <= tx_step_q(0 to 3); + + ac_an_pm_thread_running <= thrctl_out(40 to 43); + + -- Creating single cycle pulse when THRCTL[Tx_UDE] bits become active + ude_dly_d(0 to 3) <= thrctl_out(48 to 51); + force_ude_pulse(0 to 3) <= thrctl_out(48 to 51) and not ude_dly_q(0 to 3); + tx_ude_d <= gate_and(debug_mode_d, force_ude_pulse(0 to 3)); + pc_xu_force_ude <= tx_ude_q(0 to 3); + + extirpts_dis_d <= debug_mode_d and thrctl_out(52); + pc_xu_extirpts_dis_on_stop <= extirpts_dis_q; + + timebase_dis_d <= debug_mode_d and thrctl_out(53); + pc_xu_timebase_dis_on_stop <= timebase_dis_q; + + decrem_dis_d <= debug_mode_d and thrctl_out(54); + pc_xu_decrem_dis_on_stop <= decrem_dis_q; + +----------------------------------------------------------------------- +-- PC Configuration Signals + trace_bus_enable_d <= pccr0_out(32) or sp_rg_trace_bus_enable; + + pc_fu_trace_bus_enable <= trace_bus_enable_q; + pc_bx_trace_bus_enable <= trace_bus_enable_q; + pc_iu_trace_bus_enable <= trace_bus_enable_q; + pc_mm_trace_bus_enable <= trace_bus_enable_q; + pc_xu_trace_bus_enable <= trace_bus_enable_q; + rg_db_trace_bus_enable <= trace_bus_enable_q; + + -- ACT control for latches gated with debug_mode. + debug_mode_d <= pccr0_out(32); + debug_mode_act <= debug_mode_d or debug_mode_q; + + -- ACT control for latches gated with ram_enable. + ram_enab_d <= pccr0_out(33); + ram_enab_act <= ram_enab_d or ram_enab_q; + ram_enab_scom_act <= ram_enab_act or scom_act; + + -- ACT control for latches gated with errinj_enable. + errinj_enab_d <= pccr0_out(34); + errinj_enab_act <= errinj_enab_d or errinj_enab_q; + errinj_enab_scom_act <= errinj_enab_act or scom_act; + + rg_rg_xstop_report_ovride <= pccr0_out(36); + + rg_rg_fast_xstop_enable <= debug_mode_d and pccr0_out(37); + + rg_ct_dis_pwr_savings <= pccr0_out(38); + + + rg_rg_maxRecErrCntrValue <= and_reduce(recErrCntr_q(0 to 3)); + + pc_xu_dbg_action <= pccr0_out(52 to 63); + +----------------------------------------------------------------------- +-- Special Attention Signals + + spattn_out_masked <= spattn_data_q and not spattn_mask_q ; + + -- Drive out special attention signals (thread specific) + ac_an_special_attn(0) <= spattn_out_masked(0); + ac_an_special_attn(1) <= spattn_out_masked(1); + ac_an_special_attn(2) <= spattn_out_masked(2); + ac_an_special_attn(3) <= spattn_out_masked(3); + +----------------------------------------------------------------------- +-- Debug Select Controls + pc_fu_debug_mux1_ctrls <= abdsr_out(32 to 47); + pc_bx_debug_mux1_ctrls <= abdsr_out(48 to 63); + + pc_mm_debug_mux1_ctrls <= mpdsr_out(32 to 47); + rg_db_debug_mux_ctrls <= mpdsr_out(48 to 63); + + pc_iu_debug_mux1_ctrls <= idsr_out(32 to 47); + pc_iu_debug_mux2_ctrls <= idsr_out(48 to 63); + + pc_xu_debug_mux1_ctrls <= xdsr1_out(32 to 47); + pc_xu_debug_mux2_ctrls <= xdsr1_out(48 to 63); + pc_xu_debug_mux3_ctrls <= xdsr2_out(32 to 47); + pc_xu_debug_mux4_ctrls <= xdsr2_out(48 to 63); + +----------------------------------------------------------------------- +-- Error Injection Signals + inj_icache_parity_d <= errinj_enab_d and errinj_out(40); + inj_icachedir_parity_d <= errinj_enab_d and errinj_out(41); + inj_dcache_parity_d <= errinj_enab_d and errinj_out(42); + inj_dcachedir_parity_d <= errinj_enab_d and errinj_out(43); + inj_xuregfile_parity_d(0 to 3) <= gate_and(errinj_enab_d and errinj_out(44), errinj_out(32 to 35)); + inj_furegfile_parity_d(0 to 3) <= gate_and(errinj_enab_d and errinj_out(45), errinj_out(32 to 35)); + inj_sprg_ecc_d(0 to 3) <= gate_and(errinj_enab_d and errinj_out(46), errinj_out(32 to 35)); + inj_inbox_ecc_d <= errinj_enab_d and errinj_out(47); + inj_outbox_ecc_d <= errinj_enab_d and errinj_out(48); + inj_llbust_attempt_d(0 to 3) <= gate_and(errinj_enab_d and errinj_out(49), errinj_out(32 to 35)); + inj_llbust_failed_d(0 to 3) <= gate_and(errinj_enab_d and errinj_out(50), errinj_out(32 to 35)); + inj_wdt_reset_d(0 to 3) <= gate_and(errinj_enab_d and errinj_out(51), errinj_out(32 to 35)); + inj_icachedir_multihit_d <= errinj_enab_d and errinj_out(53); + inj_dcachedir_multihit_d <= errinj_enab_d and errinj_out(54); + + pc_iu_inj_icache_parity <= inj_icache_parity_q; + pc_iu_inj_icachedir_parity <= inj_icachedir_parity_q; + pc_xu_inj_dcache_parity <= inj_dcache_parity_q; + pc_xu_inj_dcachedir_parity <= inj_dcachedir_parity_q; + pc_xu_inj_regfile_parity(0 to 3) <= inj_xuregfile_parity_q(0 to 3); + pc_fu_inj_regfile_parity(0 to 3) <= inj_furegfile_parity_q(0 to 3); + pc_xu_inj_sprg_ecc(0 to 3) <= inj_sprg_ecc_q(0 to 3); + pc_bx_inj_inbox_ecc <= inj_inbox_ecc_q; + pc_bx_inj_outbox_ecc <= inj_outbox_ecc_q; + pc_xu_inj_llbust_attempt(0 to 3) <= inj_llbust_attempt_q(0 to 3); + pc_xu_inj_llbust_failed(0 to 3) <= inj_llbust_failed_q(0 to 3); + pc_xu_inj_wdt_reset(0 to 3) <= inj_wdt_reset_q(0 to 3); + sc_parity_error_inject <= errinj_enab_d and errinj_out(52); + pc_iu_inj_icachedir_multihit <= inj_icachedir_multihit_q; + pc_xu_inj_dcachedir_multihit <= inj_dcachedir_multihit_q; + + +--===================================================================== +-- FIR Related Registers and Error Reporting +--===================================================================== +fir_regs: entity work.pcq_regs_fir + generic map( expand_type => expand_type ) + port map + ( vdd => vdd + , gnd => gnd + , nclk => nclk + , lcb_clkoff_dc_b => lcb_clkoff_dc_b + , lcb_mpw1_dc_b => lcb_mpw1_dc_b + , lcb_mpw2_dc_b => lcb_mpw2_dc_b + , lcb_delay_lclkr_dc => lcb_delay_lclkr_dc + , lcb_act_dis_dc => lcb_act_dis_dc + , lcb_sg_0 => lcb_sg_0 + , lcb_func_slp_sl_thold_0 => lcb_func_slp_sl_thold_0 + , lcb_cfg_slp_sl_thold_0 => lcb_cfg_slp_sl_thold_0 + , cfgslp_d1clk => cfgslp_d1clk + , cfgslp_d2clk => cfgslp_d2clk + , cfgslp_lclk => cfgslp_lclk + , cfg_slat_d2clk => cfg_slat_d2clk + , cfg_slat_lclk => cfg_slat_lclk + , bcfg_scan_in => fir_mode_si + , func_scan_in => fir_func_si + , bcfg_scan_out => fir_mode_so + , func_scan_out => fir_func_so + -- SCOM Satellite Interface + , sc_active => scom_act + , sc_wr_q => sc_wr_q + , sc_addr_v => scaddr_v + , sc_wdata => sc_wdata + , sc_wparity => sc_wparity + , sc_rdata => fir_data_out + -- FIR and Error Signals + , ac_an_special_attn => attn_instr_int + , ac_an_checkstop => ac_an_checkstop + , ac_an_local_checkstop => ac_an_local_checkstop + , ac_an_recov_err => ac_an_recov_err + , ac_an_trace_error => ac_an_trace_error + , an_ac_checkstop => an_ac_checkstop + , an_ac_malf_alert => an_ac_malf_alert + , rg_rg_any_fir_xstop => rg_rg_any_fir_xstop + , iu_pc_err_icache_parity => iu_pc_err_icache_parity + , iu_pc_err_icachedir_parity => iu_pc_err_icachedir_parity + , iu_pc_err_icachedir_multihit => iu_pc_err_icachedir_multihit + , iu_pc_err_ucode_illegal => iu_pc_err_ucode_illegal + , xu_pc_err_dcache_parity => xu_pc_err_dcache_parity + , xu_pc_err_dcachedir_parity => xu_pc_err_dcachedir_parity + , xu_pc_err_dcachedir_multihit => xu_pc_err_dcachedir_multihit + , xu_pc_err_mcsr_summary => xu_pc_err_mcsr_summary + , xu_pc_err_ierat_parity => xu_pc_err_ierat_parity + , xu_pc_err_derat_parity => xu_pc_err_derat_parity + , xu_pc_err_tlb_parity => xu_pc_err_tlb_parity + , xu_pc_err_tlb_lru_parity => xu_pc_err_tlb_lru_parity + , xu_pc_err_ierat_multihit => xu_pc_err_ierat_multihit + , xu_pc_err_derat_multihit => xu_pc_err_derat_multihit + , xu_pc_err_tlb_multihit => xu_pc_err_tlb_multihit + , xu_pc_err_ext_mchk => xu_pc_err_ext_mchk + , xu_pc_err_ditc_overrun => xu_pc_err_ditc_overrun + , xu_pc_err_local_snoop_reject => xu_pc_err_local_snoop_reject + , xu_pc_err_sprg_ecc => xu_pc_err_sprg_ecc + , xu_pc_err_sprg_ue => xu_pc_err_sprg_ue + , xu_pc_err_regfile_parity => xu_pc_err_regfile_parity + , xu_pc_err_regfile_ue => xu_pc_err_regfile_ue + , xu_pc_err_llbust_attempt => xu_pc_err_llbust_attempt + , xu_pc_err_llbust_failed => xu_pc_err_llbust_failed + , xu_pc_err_l2intrf_ecc => xu_pc_err_l2intrf_ecc + , xu_pc_err_l2intrf_ue => xu_pc_err_l2intrf_ue + , xu_pc_err_l2credit_overrun => xu_pc_err_l2credit_overrun + , xu_pc_err_wdt_reset => xu_pc_err_wdt_reset + , xu_pc_err_attention_instr => xu_pc_err_attention_instr + , xu_pc_err_debug_event => xu_pc_err_debug_event + , xu_pc_err_nia_miscmpr => xu_pc_err_nia_miscmpr + , xu_pc_err_invld_reld => xu_pc_err_invld_reld + , xu_pc_err_mchk_disabled => xu_pc_err_mchk_disabled + , bx_pc_err_inbox_ecc => bx_pc_err_inbox_ecc + , bx_pc_err_inbox_ue => bx_pc_err_inbox_ue + , bx_pc_err_outbox_ecc => bx_pc_err_outbox_ecc + , bx_pc_err_outbox_ue => bx_pc_err_outbox_ue + , fu_pc_err_regfile_parity => fu_pc_err_regfile_parity + , fu_pc_err_regfile_ue => fu_pc_err_regfile_ue + , scom_reg_par_checks => scom_reg_par_checks + , scom_sat_fsm_error => scom_fsm_err + , scom_ack_error => scom_ack_err + , sc_parity_error_inject => sc_parity_error_inject + , rg_rg_xstop_report_ovride => rg_rg_xstop_report_ovride + , rg_rg_ram_mode => rg_rg_ram_mode + , rg_rg_ram_mode_xstop => rg_rg_ram_mode_xstop + , rg_rg_xstop_err => rg_rg_xstop_err + , rg_rg_errinj_shutoff => rg_rg_errinj_shutoff + , rg_rg_maxRecErrCntrValue => rg_rg_maxRecErrCntrValue + , rg_rg_gateRecErrCntr => rg_rg_gateRecErrCntr + -- Performance Event Signals + , pc_xu_cache_par_err_event => pc_xu_cache_par_err_event + -- Trace/Trigger Signals + , dbg_fir0_err => dbg_fir0_err + , dbg_fir1_err => dbg_fir1_err + , dbg_fir2_err => dbg_fir2_err + , dbg_fir_misc => dbg_fir_misc + ); + + + scom_reg_par_checks <= abdsr_par_err & idsr_par_err & mpdsr_par_err & + xdsr1_par_err_q & xdsr2_par_err & pccr0_par_err & + spattn_par_err ; + + + rg_ck_fast_xstop <= rg_rg_fast_xstop_enable and rg_rg_any_fir_xstop ; + + +--===================================================================== +-- Trace/Trigger Signals +--===================================================================== + dbg_scom_rdata <= sc_rdata(0 to 63); + + dbg_scom_wdata <= sc_wdata(0 to 63); + + dbg_scom_decaddr <= scaddr_v_q(0 to 63); + + dbg_scom_misc <= scom_act & -- 0 + sc_req_q & -- 1 + sc_wr_q & -- 2 + scaddr_nvld_q & -- 3 + sc_wr_nvld_q & -- 4 + sc_rd_nvld_q & -- 5 + scaddr_fir & -- 6 + sc_parity_error_inject & -- 7 + sc_wparity ; -- 8 + + dbg_ram_thrctl <= ramc_out(47) & -- 0 (RAM execute) + ramc_out(61) & -- 1 (RAM interrupt) + ramc_out(62) & -- 2 (RAM error) + ramc_out(63) & -- 3 (RAM done) + ramc_out(45 to 46) & -- 4:5 (RAM thread) + ram_mode_q & -- 6 + xu_ram_done_q & -- 7 + fu_ram_done_q & -- 8 + tx_stop_q & -- 9:12 + tx_step_q & -- 13:16 + thrctl_out(40 to 43) ; -- 17:20 (xu_pc_run) + + +--===================================================================== +-- Latches +--===================================================================== +-- debug config ring registers start +axbx_dbgsel_reg: tri_rlmreg_p + generic map (width => abdsr_q'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => scom_act, + thold_b => lcb_cfg_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_cfgslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => dcfg_siv(abdsr_offset to abdsr_offset + abdsr_q'length-1), + scout => dcfg_sov(abdsr_offset to abdsr_offset + abdsr_q'length-1), + din => abdsr_d, + dout => abdsr_q ); + +axbx_dbgsel_par: tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => scom_act, + thold_b => lcb_cfg_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_cfgslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => dcfg_siv(abdsr_par_offset to abdsr_par_offset), + scout => dcfg_sov(abdsr_par_offset to abdsr_par_offset), + din => abdsr_par_d, + dout => abdsr_par_q ); + +iu_dbgsel_reg: tri_rlmreg_p + generic map (width => idsr_q'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => scom_act, + thold_b => lcb_cfg_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_cfgslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => dcfg_siv(idsr_offset to idsr_offset + idsr_q'length-1), + scout => dcfg_sov(idsr_offset to idsr_offset + idsr_q'length-1), + din => idsr_d, + dout => idsr_q ); + +iu_dbgsel_par: tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => scom_act, + thold_b => lcb_cfg_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_cfgslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => dcfg_siv(idsr_par_offset to idsr_par_offset), + scout => dcfg_sov(idsr_par_offset to idsr_par_offset), + din => idsr_par_d, + dout => idsr_par_q ); + +mmpc_dbgsel_reg: tri_rlmreg_p + generic map (width => mpdsr_q'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => scom_act, + thold_b => lcb_cfg_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_cfgslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => dcfg_siv(mpdsr_offset to mpdsr_offset + mpdsr_q'length-1), + scout => dcfg_sov(mpdsr_offset to mpdsr_offset + mpdsr_q'length-1), + din => mpdsr_d, + dout => mpdsr_q ); + +mmpc_dbgsel_par: tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => scom_act, + thold_b => lcb_cfg_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_cfgslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => dcfg_siv(mpdsr_par_offset to mpdsr_par_offset), + scout => dcfg_sov(mpdsr_par_offset to mpdsr_par_offset), + din => mpdsr_par_d, + dout => mpdsr_par_q ); + +xu_dbgsel1_reg: tri_rlmreg_p + generic map (width => xdsr1_q'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => scom_act, + thold_b => lcb_cfg_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_cfgslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => dcfg_siv(xdsr1_offset to xdsr1_offset + xdsr1_q'length-1), + scout => dcfg_sov(xdsr1_offset to xdsr1_offset + xdsr1_q'length-1), + din => xdsr1_d, + dout => xdsr1_q ); + +xu_dbgsel1_par: tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => scom_act, + thold_b => lcb_cfg_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_cfgslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => dcfg_siv(xdsr1_par_offset to xdsr1_par_offset), + scout => dcfg_sov(xdsr1_par_offset to xdsr1_par_offset), + din => xdsr1_par_d, + dout => xdsr1_par_q ); + +xu_dbgsel2_reg: tri_rlmreg_p + generic map (width => xdsr2_q'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => scom_act, + thold_b => lcb_cfg_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_cfgslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => dcfg_siv(xdsr2_offset to xdsr2_offset + xdsr2_q'length-1), + scout => dcfg_sov(xdsr2_offset to xdsr2_offset + xdsr2_q'length-1), + din => xdsr2_d, + dout => xdsr2_q ); + +xu_dbgsel2_par: tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => scom_act, + thold_b => lcb_cfg_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_cfgslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => dcfg_siv(xdsr2_par_offset to xdsr2_par_offset), + scout => dcfg_sov(xdsr2_par_offset to xdsr2_par_offset), + din => xdsr2_par_d, + dout => xdsr2_par_q ); + +pccr0_reg: tri_rlmreg_p + generic map (width => pccr0_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => scom_act, + thold_b => lcb_cfg_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_cfgslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => dcfg_siv(pccr0_offset to pccr0_offset + pccr0_size-1), + scout => dcfg_sov(pccr0_offset to pccr0_offset + pccr0_size-1), + din => pccr0_d, + dout => pccr0_q ); + +rec_err_cntr: tri_rlmreg_p + generic map (width => recerrcntr_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => lcb_cfg_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_cfgslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => dcfg_siv(recerrcntr_offset to recerrcntr_offset + recerrcntr_size-1), + scout => dcfg_sov(recerrcntr_offset to recerrcntr_offset + recerrcntr_size-1), + din => recErrCntr_in, + dout => recErrCntr_q ); + +pccr0_par: tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => lcb_cfg_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_cfgslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => dcfg_siv(pccr0_par_offset to pccr0_par_offset), + scout => dcfg_sov(pccr0_par_offset to pccr0_par_offset), + din => pccr0_par_d, + dout => pccr0_par_q ); + +dcfg_stage1: tri_rlmreg_p + generic map (width => dcfg_stage1_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => lcb_cfg_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_cfgslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => dcfg_siv(dcfg_stage1_offset to dcfg_stage1_offset + dcfg_stage1_size-1), + scout => dcfg_sov(dcfg_stage1_offset to dcfg_stage1_offset + dcfg_stage1_size-1), + din(0) => debug_mode_d, + din(1) => ram_enab_d, + din(2) => errinj_enab_d, + din(3) => trace_bus_enable_d, + din(4) => xdsr1_par_err_d, + dout(0) => debug_mode_q, + dout(1) => ram_enab_q, + dout(2) => errinj_enab_q, + dout(3) => trace_bus_enable_q, + dout(4) => xdsr1_par_err_q ); +-- debug config ring registers end +-- boot config ring registers start +thrctl1_reg: tri_rlmreg_p + generic map (width => thrctl1_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => lcb_cfg_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_cfgslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => bcfg_siv(thrctl1_offset to thrctl1_offset + thrctl1_size-1), + scout => bcfg_sov(thrctl1_offset to thrctl1_offset + thrctl1_size-1), + din => thrctl1_d, + dout => thrctl1_q ); + +thrctl2_reg: tri_rlmreg_p + generic map (width => thrctl2_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => scom_act, + thold_b => lcb_cfg_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_cfgslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => bcfg_siv(thrctl2_offset to thrctl2_offset + thrctl2_size-1), + scout => bcfg_sov(thrctl2_offset to thrctl2_offset + thrctl2_size-1), + din => thrctl2_d, + dout => thrctl2_q ); + +spattn_data_reg: tri_rlmreg_p + generic map (width => spattn_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => lcb_cfg_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_cfgslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => bcfg_siv(spattn1_offset to spattn1_offset + spattn_size-1), + scout => bcfg_sov(spattn1_offset to spattn1_offset + spattn_size-1), + din => spattn_data_d, + dout => spattn_data_q ); + +spattn_mask_reg: tri_rlmreg_p + generic map (width => spattn_size, init => 15, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => scom_act, + thold_b => lcb_cfg_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_cfgslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => bcfg_siv(spattn2_offset to spattn2_offset + spattn_size-1), + scout => bcfg_sov(spattn2_offset to spattn2_offset + spattn_size-1), + din => spattn_mask_d, + dout => spattn_mask_q ); + +spattn_par: tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => scom_act, + thold_b => lcb_cfg_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_cfgslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => bcfg_siv(spattn_par_offset to spattn_par_offset), + scout => bcfg_sov(spattn_par_offset to spattn_par_offset), + din => spattn_par_d, + dout => spattn_par_q ); + +bcfg_stage1: tri_rlmreg_p + generic map (width => bcfg_stage1_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => lcb_cfg_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_cfgslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => bcfg_siv(bcfg_stage1_offset to bcfg_stage1_offset + bcfg_stage1_size-1), + scout => bcfg_sov(bcfg_stage1_offset to bcfg_stage1_offset + bcfg_stage1_size-1), + din(0 to 3) => tx_stop_d, + din(4) => an_ac_debug_stop, + din(5 to 8) => xu_pc_stop_dbg_event, + din(9 to 12) => xu_pc_step_done, + dout(0 to 3) => tx_stop_q, + dout(4) => ext_debug_stop_q, + dout(5 to 8) => stop_dbg_event_q, + dout(9 to 12) => step_done_q ); + +bcfg_stage2: tri_ser_rlmreg_p + generic map (width => bcfg_stage2_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => debug_mode_act, + thold_b => lcb_cfg_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_cfgslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => bcfg_siv(bcfg_stage2_offset to bcfg_stage2_offset + bcfg_stage2_size-1), + scout => bcfg_sov(bcfg_stage2_offset to bcfg_stage2_offset + bcfg_stage2_size-1), + din(0 to 3) => tx_step_d, + din(4) => extirpts_dis_d, + din(5) => timebase_dis_d, + din(6) => decrem_dis_d, + din(7 to 10) => ude_dly_d, + din(11 to 14) => tx_ude_d, + dout(0 to 3) => tx_step_q, + dout(4) => extirpts_dis_q, + dout(5) => timebase_dis_q, + dout(6) => decrem_dis_q, + dout(7 to 10) => ude_dly_q, + dout(11 to 14) => tx_ude_q ); +-- boot config ring registers end +-- core config ring registers start +-- NOTE: CCFG ring not used in PCQ; latch added for timing. +ccfg_repwr: tri_slat_scan + generic map (width => 1, init => "0", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => cfg_slat_d2clk, + lclk => cfg_slat_lclk, + scan_in(0) => ccfg_scan_in, + scan_out(0) => ccfg_scan_out ); +-- core config ring registers end +-- func ring registers start +rami_reg: tri_rlmreg_p + generic map (width => rami_q'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ram_enab_scom_act, + thold_b => lcb_func_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_funcslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(rami_offset to rami_offset + rami_q'length-1), + scout => func_sov(rami_offset to rami_offset + rami_q'length-1), + din => rami_d, + dout => rami_q ); + +ramc_reg: tri_rlmreg_p + generic map (width => ramc_q'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ram_enab_scom_act, + thold_b => lcb_func_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_funcslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(ramc_offset to ramc_offset + ramc_q'length-1), + scout => func_sov(ramc_offset to ramc_offset + ramc_q'length-1), + din => ramc_d, + dout => ramc_q ); + +ramd_reg: tri_rlmreg_p + generic map (width => ramd_q'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ram_enab_scom_act, + thold_b => lcb_func_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_funcslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(ramd_offset to ramd_offset + ramd_q'length-1), + scout => func_sov(ramd_offset to ramd_offset + ramd_q'length-1), + din => ramd_d, + dout => ramd_q ); + +fu_ram_din: tri_rlmreg_p + generic map (width => fu_ram_din_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ram_enab_act, + thold_b => lcb_func_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_funcslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(fu_ram_din_offset to fu_ram_din_offset + fu_ram_din_size-1), + scout => func_sov(fu_ram_din_offset to fu_ram_din_offset + fu_ram_din_size-1), + din => fu_ramd_load_data_d, + dout => fu_ramd_load_data_q ); + +xu_ram_din: tri_rlmreg_p + generic map (width => xu_ram_din_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ram_enab_act, + thold_b => lcb_func_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_funcslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(xu_ram_din_offset to xu_ram_din_offset + xu_ram_din_size-1), + scout => func_sov(xu_ram_din_offset to xu_ram_din_offset + xu_ram_din_size-1), + din => xu_ramd_load_data_d, + dout => xu_ramd_load_data_q ); + +errinj_reg: tri_rlmreg_p + generic map (width => errinj_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => errinj_enab_scom_act, + thold_b => lcb_func_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_funcslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(errinj_offset to errinj_offset + errinj_size-1), + scout => func_sov(errinj_offset to errinj_offset + errinj_size-1), + din => errinj_d, + dout => errinj_q ); + +sc_misc: tri_ser_rlmreg_p + generic map (width => scom_misc_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => scom_act, + thold_b => lcb_func_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_funcslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(sc_misc_offset to sc_misc_offset + scom_misc_size-1), + scout => func_sov(sc_misc_offset to sc_misc_offset + scom_misc_size-1), + din(0) => sc_req_d, + din(1) => scaddr_nvld_d, + din(2) => sc_wr_nvld_d, + din(3) => sc_rd_nvld_d, + din(4) => sc_wr_d, + din(5) => ram_flush_d, + dout(0) => sc_req_q, + dout(1) => scaddr_nvld_q, + dout(2) => sc_wr_nvld_q, + dout(3) => sc_rd_nvld_q, + dout(4) => sc_wr_q, + dout(5) => ram_flush_q); + + +scaddr_dec: tri_rlmreg_p + generic map (width => scaddr_v_q'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => scom_act, + thold_b => lcb_func_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_funcslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(scaddr_dec_offset to scaddr_dec_offset + scaddr_v_q'length-1), + scout => func_sov(scaddr_dec_offset to scaddr_dec_offset + scaddr_v_q'length-1), + din => scaddr_v_d, + dout => scaddr_v_q ); + +func_stage1: tri_rlmreg_p + generic map (width => func_stage1_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => lcb_func_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_funcslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(func_stage1_offset to func_stage1_offset + func_stage1_size-1), + scout => func_sov(func_stage1_offset to func_stage1_offset + func_stage1_size-1), + din(0) => an_ac_scom_cch, + din(1) => an_ac_scom_dch, + dout(0) => scom_cch_q, + dout(1) => scom_dch_q ); + + +func_stage2: tri_ser_rlmreg_p + generic map (width => func_stage2_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => errinj_enab_act, + thold_b => lcb_func_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_funcslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(func_stage2_offset to func_stage2_offset + func_stage2_size-1), + scout => func_sov(func_stage2_offset to func_stage2_offset + func_stage2_size-1), + din(0) => inj_icache_parity_d, + din(1) => inj_icachedir_parity_d, + din(2) => inj_dcache_parity_d, + din(3) => inj_dcachedir_parity_d, + din(4 to 7) => inj_xuregfile_parity_d(0 to 3), + din(8 to 11) => inj_furegfile_parity_d(0 to 3), + din(12 to 15) => inj_sprg_ecc_d(0 to 3), + din(16) => inj_inbox_ecc_d, + din(17) => inj_outbox_ecc_d, + din(18 to 21) => inj_llbust_attempt_d(0 to 3), + din(22 to 25) => inj_llbust_failed_d(0 to 3), + din(26 to 29) => inj_wdt_reset_d(0 to 3), + din(30) => inj_icachedir_multihit_d, + din(31) => inj_dcachedir_multihit_d, + dout(0) => inj_icache_parity_q, + dout(1) => inj_icachedir_parity_q, + dout(2) => inj_dcache_parity_q, + dout(3) => inj_dcachedir_parity_q, + dout(4 to 7) => inj_xuregfile_parity_q(0 to 3), + dout(8 to 11) => inj_furegfile_parity_q(0 to 3), + dout(12 to 15) => inj_sprg_ecc_q(0 to 3), + dout(16) => inj_inbox_ecc_q, + dout(17) => inj_outbox_ecc_q, + dout(18 to 21) => inj_llbust_attempt_q(0 to 3), + dout(22 to 25) => inj_llbust_failed_q(0 to 3), + dout(26 to 29) => inj_wdt_reset_q(0 to 3), + dout(30) => inj_icachedir_multihit_q, + dout(31) => inj_dcachedir_multihit_q ); + +func_stage3: tri_ser_rlmreg_p + generic map (width => func_stage3_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ram_enab_act, + thold_b => lcb_func_slp_sl_thold_0_b, + sg => lcb_sg_0, + forcee => force_funcslp, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(func_stage3_offset to func_stage3_offset + func_stage3_size-1), + scout => func_sov(func_stage3_offset to func_stage3_offset + func_stage3_size-1), + din(0) => ram_mode_d, + din(1) => ram_execute_d, + din(2) => ram_msrovren_d, + din(3) => ram_msrovrpr_d, + din(4) => ram_msrovrgs_d, + din(5) => ram_msrovrde_d, + din(6) => ram_force_d, + din(7) => xu_pc_ram_done, + din(8) => fu_pc_ram_done, + din(9 to 10) => ram_thread_d(0 to 1), + dout(0) => ram_mode_q, + dout(1) => ram_execute_q, + dout(2) => ram_msrovren_q, + dout(3) => ram_msrovrpr_q, + dout(4) => ram_msrovrgs_q, + dout(5) => ram_msrovrde_q, + dout(6) => ram_force_q, + dout(7) => xu_ram_done_q, + dout(8) => fu_ram_done_q, + dout(9 to 10) => ram_thread_q(0 to 1) ); +-- func ring registers end + +--===================================================================== +-- additional LCB Staging +--===================================================================== +-- Config ring thold staging - power managaged +cfg_slat_thold_b <= NOT lcb_cfg_sl_thold_0; +cfg_slat_force <= lcb_sg_0; + +lcbs_cfg: tri_lcbs + generic map (expand_type => expand_type ) + port map ( + vd => vdd, + gd => gnd, + delay_lclkr => lcb_delay_lclkr_dc, + nclk => nclk, + forcee => cfg_slat_force, + thold_b => cfg_slat_thold_b, + dclk => cfg_slat_d2clk, + lclk => cfg_slat_lclk ); + + +-- Config ring thold staging - NOT power managed +lcbor_cfgslp: tri_lcbor +generic map (expand_type => expand_type ) +port map ( + clkoff_b => lcb_clkoff_dc_b, + thold => lcb_cfg_slp_sl_thold_0, + sg => lcb_sg_0, + act_dis => lcb_act_dis_dc, + forcee => force_cfgslp, + thold_b => lcb_cfg_slp_sl_thold_0_b ); + +lcbn_cfgslp: tri_lcbnd +generic map (expand_type => expand_type ) +port map ( + vd => vdd, + gd => gnd, + act => tiup, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + nclk => nclk, + forcee => force_cfgslp, + sg => lcb_sg_0, + thold_b => lcb_cfg_slp_sl_thold_0_b, + d1clk => cfgslp_d1clk, + d2clk => cfgslp_d2clk, + lclk => cfgslp_lclk ); + + +-- Func ring thold staging - NOT power managed +lcbor_funcslp: tri_lcbor +generic map (expand_type => expand_type ) +port map ( + clkoff_b => lcb_clkoff_dc_b, + thold => lcb_func_slp_sl_thold_0, + sg => lcb_sg_0, + act_dis => lcb_act_dis_dc, + forcee => force_funcslp, + thold_b => lcb_func_slp_sl_thold_0_b ); + + + +--===================================================================== +-- Scan Connections +--===================================================================== +-- Boot config ring +-- includes latches in pcq_regs along with the pcq_regs_fir boot scan ring +bcfg_siv(0 TO bcfg_right) <= bcfg_scan_in & bcfg_sov(0 to bcfg_right-1); +fir_mode_si <= bcfg_sov(bcfg_right); +bcfg_scan_out <= fir_mode_so and scan_dis_dc_b; + +-- Func config ring +-- includes latches in pcq_regs along with the pcq_regs_fir func scan ring +func_siv(0 TO func_right) <= func_scan_in & func_sov(0 to func_right-1); +fir_func_si <= func_sov(func_right); +func_scan_out <= fir_func_so and scan_dis_dc_b; + +-- Debug config ring +-- includes just pcq_regs latches +dcfg_siv(0 TO dcfg_right) <= dcfg_scan_in & dcfg_sov(0 to dcfg_right-1); +dcfg_scan_out <= dcfg_sov(dcfg_right) and scan_dis_dc_b; + + +----------------------------------------------------------------------- +end pcq_regs; diff --git a/rel/src/vhdl/work/pcq_regs_fir.vhdl b/rel/src/vhdl/work/pcq_regs_fir.vhdl new file mode 100644 index 0000000..f2ebe1a --- /dev/null +++ b/rel/src/vhdl/work/pcq_regs_fir.vhdl @@ -0,0 +1,980 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- +-- Description: Pervasive Core FIR + Error Reporting Function +-- +--***************************************************************************** + +library ieee; +use ieee.std_logic_1164.all; +library ibm; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; +library support; +use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + + +entity pcq_regs_fir is +generic(expand_type : integer := 2); -- 0=ibm (Umbra), 1=non-ibm, 2=ibm (MPG) + +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + lcb_clkoff_dc_b : in std_ulogic; + lcb_mpw1_dc_b : in std_ulogic; + lcb_mpw2_dc_b : in std_ulogic; + lcb_delay_lclkr_dc : in std_ulogic; + lcb_act_dis_dc : in std_ulogic; + lcb_sg_0 : in std_ulogic; + lcb_func_slp_sl_thold_0 : in std_ulogic; + lcb_cfg_slp_sl_thold_0 : in std_ulogic; + cfgslp_d1clk : in std_ulogic; + cfgslp_d2clk : in std_ulogic; + cfgslp_lclk : in clk_logic; + cfg_slat_d2clk : in std_ulogic; + cfg_slat_lclk : in clk_logic; + bcfg_scan_in : in std_ulogic; + bcfg_scan_out : out std_ulogic; + func_scan_in : in std_ulogic; + func_scan_out : out std_ulogic; +-- SCOM Satellite Interface + sc_active : in std_ulogic; + sc_wr_q : in std_ulogic; + sc_addr_v : in std_ulogic_vector(0 to 63); + sc_wdata : in std_ulogic_vector(0 to 63); + sc_wparity : in std_ulogic; + sc_rdata : out std_ulogic_vector(0 to 63); +-- FIR and Error Signals + ac_an_special_attn : out std_ulogic_vector(0 to 3); + ac_an_checkstop : out std_ulogic_vector(0 to 2); + ac_an_local_checkstop : out std_ulogic_vector(0 to 2); + ac_an_recov_err : out std_ulogic_vector(0 to 2); + ac_an_trace_error : out std_ulogic; + rg_rg_any_fir_xstop : out std_ulogic; + an_ac_checkstop : in std_ulogic; + an_ac_malf_alert : in std_ulogic; + iu_pc_err_icache_parity : in std_ulogic; + iu_pc_err_icachedir_parity : in std_ulogic; + iu_pc_err_icachedir_multihit : in std_ulogic; + iu_pc_err_ucode_illegal : in std_ulogic_vector(0 to 3); + xu_pc_err_dcache_parity : in std_ulogic; + xu_pc_err_dcachedir_parity : in std_ulogic; + xu_pc_err_dcachedir_multihit : in std_ulogic; + xu_pc_err_mcsr_summary : in std_ulogic_vector(0 to 3); + xu_pc_err_ierat_parity : in std_ulogic; + xu_pc_err_derat_parity : in std_ulogic; + xu_pc_err_tlb_parity : in std_ulogic; + xu_pc_err_tlb_lru_parity : in std_ulogic; + xu_pc_err_ierat_multihit : in std_ulogic; + xu_pc_err_derat_multihit : in std_ulogic; + xu_pc_err_tlb_multihit : in std_ulogic; + xu_pc_err_ext_mchk : in std_ulogic; + xu_pc_err_ditc_overrun : in std_ulogic; + xu_pc_err_local_snoop_reject : in std_ulogic; + xu_pc_err_sprg_ecc : in std_ulogic_vector(0 to 3); + xu_pc_err_sprg_ue : in std_ulogic_vector(0 to 3); + xu_pc_err_regfile_parity : in std_ulogic_vector(0 to 3); + xu_pc_err_regfile_ue : in std_ulogic_vector(0 to 3); + xu_pc_err_llbust_attempt : in std_ulogic_vector(0 to 3); + xu_pc_err_llbust_failed : in std_ulogic_vector(0 to 3); + xu_pc_err_l2intrf_ecc : in std_ulogic; + xu_pc_err_l2intrf_ue : in std_ulogic; + xu_pc_err_l2credit_overrun : in std_ulogic; + xu_pc_err_wdt_reset : in std_ulogic_vector(0 to 3); + xu_pc_err_attention_instr : in std_ulogic_vector(0 to 3); + xu_pc_err_debug_event : in std_ulogic_vector(0 to 3); + xu_pc_err_nia_miscmpr : in std_ulogic_vector(0 to 3); + xu_pc_err_invld_reld : in std_ulogic; + xu_pc_err_mchk_disabled : in std_ulogic; + bx_pc_err_inbox_ecc : in std_ulogic; + bx_pc_err_inbox_ue : in std_ulogic; + bx_pc_err_outbox_ecc : in std_ulogic; + bx_pc_err_outbox_ue : in std_ulogic; + fu_pc_err_regfile_parity : in std_ulogic_vector(0 to 3); + fu_pc_err_regfile_ue : in std_ulogic_vector(0 to 3); + scom_reg_par_checks : in std_ulogic_vector(0 to 6); + scom_sat_fsm_error : in std_ulogic; + scom_ack_error : in std_ulogic; + sc_parity_error_inject : in std_ulogic; + rg_rg_xstop_report_ovride : in std_ulogic; + rg_rg_ram_mode : in std_ulogic; + rg_rg_ram_mode_xstop : out std_ulogic; + rg_rg_xstop_err : out std_ulogic_vector(0 to 3); + rg_rg_errinj_shutoff : out std_ulogic_vector(0 to 14); + rg_rg_maxRecErrCntrValue : in std_ulogic; + rg_rg_gateRecErrCntr : out std_ulogic; + -- Performance Event Signals + pc_xu_cache_par_err_event : out std_ulogic; +-- Trace/Trigger Signals + dbg_fir0_err : out std_ulogic_vector(0 to 31); + dbg_fir1_err : out std_ulogic_vector(0 to 30); + dbg_fir2_err : out std_ulogic_vector(0 to 21); + dbg_fir_misc : out std_ulogic_vector(0 to 35) +); + +-- synopsys translate_off + + +-- synopsys translate_on +end pcq_regs_fir; + +architecture pcq_regs_fir of pcq_regs_fir is +--===================================================================== +-- Signal Declarations +--===================================================================== +-- FIR0 Init Values +constant fir0_width : positive := 32; +constant fir0_init : std_ulogic_vector := x"00000000"; +constant fir0mask_init : std_ulogic_vector := x"FFFFFFFF"; +constant fir0mask_par_init : std_ulogic_vector := "0"; +constant fir0act0_init : std_ulogic_vector := x"00000F00"; +constant fir0act0_par_init : std_ulogic_vector := "0"; +constant fir0act1_init : std_ulogic_vector := x"FFFFF0FF"; +constant fir0act1_par_init : std_ulogic_vector := "0"; +-- FIR1 Init Values +constant fir1_width : positive := 32; +constant fir1_init : std_ulogic_vector := x"00000000"; +constant fir1mask_init : std_ulogic_vector := x"FFFFFFFF"; +constant fir1mask_par_init : std_ulogic_vector := "0"; +constant fir1act0_init : std_ulogic_vector := x"3FFFFFFF"; +constant fir1act0_par_init : std_ulogic_vector := "0"; +constant fir1act1_init : std_ulogic_vector := x"C0000000"; +constant fir1act1_par_init : std_ulogic_vector := "0"; +-- FIR2 Init Values +constant fir2_width : positive := 22; +constant fir2_init : std_ulogic_vector := x"00000" & "00"; +constant fir2mask_init : std_ulogic_vector := x"FFFE0" & "11"; +constant fir2mask_par_init : std_ulogic_vector := "1"; +constant fir2act0_init : std_ulogic_vector := x"00020" & "00"; +constant fir2act0_par_init : std_ulogic_vector := "1"; +constant fir2act1_init : std_ulogic_vector := x"0FFC0" & "11"; +constant fir2act1_par_init : std_ulogic_vector := "0"; +-- Common Init Values +constant scpar_err_rpt_width : positive := 16; +constant scpar_rpt_reset_value : std_ulogic_vector := x"0000"; +constant scack_err_rpt_width : positive := 2; +constant scack_rpt_reset_value : std_ulogic_vector := "00"; + +-- Scan Ring Ordering: +constant FIR0_bcfg_size : positive := 3*(fir0_width+1)+fir0_width; +constant FIR1_bcfg_size : positive := 3*(fir1_width+1)+fir1_width; +constant FIR2_bcfg_size : positive := 3*(fir2_width+1)+fir2_width; +constant FIR0_func_size : positive := 5; +constant FIR1_func_size : positive := 5; +constant FIR2_func_size : positive := 5; +constant attent_func_size : positive := 4; +constant errout_func_size : positive := 34; +-- start of bcfg scan chain ordering +constant bcfg_fir0_offset : natural := 0; +constant bcfg_fir1_offset : natural := bcfg_fir0_offset + FIR0_bcfg_size; +constant bcfg_fir2_offset : natural := bcfg_fir1_offset + FIR1_bcfg_size; +constant bcfg_erpt1_hld_offset : natural := bcfg_fir2_offset + FIR2_bcfg_size; +constant bcfg_erpt1_msk_offset : natural := bcfg_erpt1_hld_offset + scpar_err_rpt_width; +constant bcfg_erpt2_hld_offset : natural := bcfg_erpt1_msk_offset + scpar_err_rpt_width; +constant bcfg_erpt2_msk_offset : natural := bcfg_erpt2_hld_offset + scack_err_rpt_width; +constant bcfg_right : natural := bcfg_erpt2_msk_offset + scack_err_rpt_width - 1; +-- end of bcfg scan chain ordering +-- start of func scan chain ordering +constant func_fir0_offset : natural := 0; +constant func_fir1_offset : natural := func_fir0_offset + FIR0_func_size; +constant func_fir2_offset : natural := func_fir1_offset + FIR1_func_size; +constant func_attent_offset : natural := func_fir2_offset + FIR2_func_size; +constant func_errout_offset : natural := func_attent_offset + attent_func_size; +constant func_f0err_offset : natural := func_errout_offset + errout_func_size; +constant func_f1err_offset : natural := func_f0err_offset + fir0_width; +constant func_f2err_offset : natural := func_f1err_offset + fir1_width; +constant func_right : natural := func_f2err_offset + fir2_width - 1; +-- end of func scan chain ordering + +----------------------------------------------------------------------- +-- Basic/Misc signals +signal tidn, tiup : std_ulogic; +signal tidn_32 : std_ulogic_vector(0 to 31); +-- Clocks +signal func_d1clk : std_ulogic; +signal func_d2clk : std_ulogic; +signal func_lclk : clk_logic; +signal func_thold_b : std_ulogic; +signal func_force : std_ulogic; +-- SCOM +signal scom_err_rpt_held : std_ulogic_vector(0 to 63); +signal sc_reg_par_err_in : std_ulogic_vector(0 to scpar_err_rpt_width-1); +signal sc_reg_par_err_out : std_ulogic_vector(0 to scpar_err_rpt_width-1); +signal sc_reg_par_err_out_q : std_ulogic_vector(0 to scpar_err_rpt_width-1); +signal sc_reg_par_err_hold : std_ulogic_vector(0 to scpar_err_rpt_width-1); +signal scom_reg_parity_err : std_ulogic; +signal fir_regs_parity_err : std_ulogic; +signal sc_reg_ack_err_in : std_ulogic_vector(0 to scack_err_rpt_width-1); +signal sc_reg_ack_err_out : std_ulogic_vector(0 to scack_err_rpt_width-1); +signal sc_reg_ack_err_out_q : std_ulogic_vector(0 to scack_err_rpt_width-1); +signal sc_reg_ack_err_hold : std_ulogic_vector(0 to scack_err_rpt_width-1); +signal scom_reg_ack_err : std_ulogic; +-- FIR0 +signal fir0_errors : std_ulogic_vector(0 to fir0_width-1); +signal fir0_errors_q : std_ulogic_vector(0 to fir0_width-1); +signal fir0_fir_out : std_ulogic_vector(0 to fir0_width-1); +signal fir0_act0_out : std_ulogic_vector(0 to fir0_width-1); +signal fir0_act1_out : std_ulogic_vector(0 to fir0_width-1); +signal fir0_mask_out : std_ulogic_vector(0 to fir0_width-1); +signal fir0_scrdata : std_ulogic_vector(0 to fir0_width-1); +signal fir0_xstop_err : std_ulogic; +signal fir0_recov_err : std_ulogic; +signal fir0_lxstop_mchk : std_ulogic; +signal fir0_trace_error : std_ulogic; +signal fir0_block_on_checkstop : std_ulogic; +signal fir0_fir_parity_check : std_ulogic_vector(0 to 2); +signal fir0_recoverable_errors : std_ulogic_vector(0 to fir0_width-1); +signal fir0_recov_err_in : std_ulogic_vector(0 to 1); +signal fir0_recov_err_q : std_ulogic_vector(0 to 1); +signal fir0_recov_err_pulse : std_ulogic; +signal fir0_enabled_checkstops : std_ulogic_vector(32 to 32 + fir0_width-1); +-- FIR1 +signal fir1_errors : std_ulogic_vector(0 to fir1_width-1); +signal fir1_errors_q : std_ulogic_vector(0 to fir1_width-1); +signal fir1_fir_out : std_ulogic_vector(0 to fir1_width-1); +signal fir1_act0_out : std_ulogic_vector(0 to fir1_width-1); +signal fir1_act1_out : std_ulogic_vector(0 to fir1_width-1); +signal fir1_mask_out : std_ulogic_vector(0 to fir1_width-1); +signal fir1_scrdata : std_ulogic_vector(0 to fir1_width-1); +signal fir1_xstop_err : std_ulogic; +signal fir1_recov_err : std_ulogic; +signal fir1_lxstop_mchk : std_ulogic; +signal fir1_trace_error : std_ulogic; +signal fir1_block_on_checkstop : std_ulogic; +signal fir1_fir_parity_check : std_ulogic_vector(0 to 2); +signal fir1_recoverable_errors : std_ulogic_vector(0 to fir1_width-1); +signal fir1_recov_err_in : std_ulogic_vector(0 to 1); +signal fir1_recov_err_q : std_ulogic_vector(0 to 1); +signal fir1_recov_err_pulse : std_ulogic; +signal fir1_enabled_checkstops : std_ulogic_vector(32 to 32 + fir1_width-1); +-- FIR2 +signal fir2_errors : std_ulogic_vector(0 to fir2_width-1); +signal fir2_errors_q : std_ulogic_vector(0 to fir2_width-1); +signal fir2_fir_out : std_ulogic_vector(0 to fir2_width-1); +signal fir2_act0_out : std_ulogic_vector(0 to fir2_width-1); +signal fir2_act1_out : std_ulogic_vector(0 to fir2_width-1); +signal fir2_mask_out : std_ulogic_vector(0 to fir2_width-1); +signal fir2_scrdata : std_ulogic_vector(0 to fir2_width-1); +signal fir2_xstop_err : std_ulogic; +signal fir2_recov_err : std_ulogic; +signal fir2_lxstop_mchk : std_ulogic; +signal fir2_trace_error : std_ulogic; +signal fir2_block_on_checkstop : std_ulogic; +signal fir2_fir_parity_check : std_ulogic_vector(0 to 2); +signal fir2_recoverable_errors : std_ulogic_vector(0 to fir2_width-1); +signal fir2_recov_err_in : std_ulogic_vector(0 to 1); +signal fir2_recov_err_q : std_ulogic_vector(0 to 1); +signal fir2_recov_err_pulse : std_ulogic; +signal fir2_enabled_checkstops : std_ulogic_vector(36 to 32 + fir2_width-1); +-- Error Inject Shutoff +signal injoff_icache_parity : std_ulogic; +signal injoff_icachedir_parity : std_ulogic; +signal injoff_dcache_parity : std_ulogic; +signal injoff_dcachedir_parity : std_ulogic; +signal injoff_xuregfile_parity : std_ulogic; +signal injoff_furegfile_parity : std_ulogic; +signal injoff_sprg_ecc : std_ulogic; +signal injoff_inbox_ecc : std_ulogic; +signal injoff_outbox_ecc : std_ulogic; +signal injoff_llbust_attempt : std_ulogic; +signal injoff_llbust_failed : std_ulogic; +signal injoff_wdt_reset : std_ulogic; +signal injoff_scomreg_parity : std_ulogic; +signal injoff_icachedir_multihit : std_ulogic; +signal injoff_dcachedir_multihit : std_ulogic; +signal error_inject_shutoff : std_ulogic_vector(0 to 14); +-- MISC +signal xstop_err_int, xstop_err_q : std_ulogic_vector(0 to 2); +signal xstop_out_d, xstop_out_q : std_ulogic_vector(0 to 2); +signal lxstop_err_int, lxstop_err_q : std_ulogic_vector(0 to 2); +signal xstop_err_per_thread : std_ulogic_vector(0 to 3); +signal xstop_err_common : std_ulogic; +signal an_ac_checkstop_q : std_ulogic; +signal maxRecErrCntrValue_errrpt : std_ulogic; +signal block_xstop_in_ram_mode : std_ulogic; +signal atten_instr_q : std_ulogic_vector(0 to 3); +signal bcfg_siv, bcfg_sov : std_ulogic_vector(0 to bcfg_right); +signal func_siv, func_sov : std_ulogic_vector(0 to func_right); +signal unused_signals : std_ulogic; + +begin + + + tiup <= '1'; + tidn <= '0'; + tidn_32 <= (others => '0'); + + unused_signals <= or_reduce( fir0_scrdata & fir1_scrdata & fir2_scrdata & + fir1_recoverable_errors(0) & sc_addr_v(9) & + sc_addr_v(29 to 63) & sc_wdata & an_ac_malf_alert ); + + + +--===================================================================== +-- FIR0 Instantiation +--===================================================================== +FIR0: entity work.pcq_local_fir2 + generic map( width => fir0_width, + expand_type => expand_type, + impl_lxstop_mchk => false, + use_recov_reset => false, + fir_init => fir0_init, + fir_mask_init => fir0mask_init, + fir_mask_par_init => fir0mask_par_init, + fir_action0_init => fir0act0_init, + fir_action0_par_init => fir0act0_par_init, + fir_action1_init => fir0act1_init, + fir_action1_par_init => fir0act1_par_init + ) + port map + -- Global lines for clocking and scan control + ( nclk => nclk + , vd => vdd + , gd => gnd + , lcb_clkoff_dc_b => lcb_clkoff_dc_b + , lcb_mpw1_dc_b => lcb_mpw1_dc_b + , lcb_mpw2_dc_b => lcb_mpw2_dc_b + , lcb_delay_lclkr_dc => lcb_delay_lclkr_dc + , lcb_act_dis_dc => lcb_act_dis_dc + , lcb_sg_0 => lcb_sg_0 + , lcb_func_slp_sl_thold_0 => lcb_func_slp_sl_thold_0 -- not power-managed + , lcb_cfg_slp_sl_thold_0 => lcb_cfg_slp_sl_thold_0 -- not power-managed + , mode_scan_siv => bcfg_siv(bcfg_fir0_offset to bcfg_fir0_offset + FIR0_bcfg_size-1) + , mode_scan_sov => bcfg_sov(bcfg_fir0_offset to bcfg_fir0_offset + FIR0_bcfg_size-1) + , func_scan_siv => func_siv(func_fir0_offset to func_fir0_offset + FIR0_func_size-1) + , func_scan_sov => func_sov(func_fir0_offset to func_fir0_offset + FIR0_func_size-1) + -- external interface + , error_in => fir0_errors_q -- needs to be directly off a latch for timing + , xstop_err => fir0_xstop_err -- checkstop output to Global FIR + , recov_err => fir0_recov_err -- recoverable output to Global FIR + , lxstop_mchk => fir0_lxstop_mchk -- use ONLY if impl_lxstop_mchk = true + , trace_error => fir0_trace_error -- connect to error_input of closest trdata macro + , sys_xstop_in => fir0_block_on_checkstop -- freeze FIR on other checkstop errors + , recov_reset => tidn -- only needed if use_recov_reset = true + , fir_out => fir0_fir_out -- output of current FIR state if needed + , act0_out => fir0_act0_out -- output of current FIR ACT0 if needed + , act1_out => fir0_act1_out -- output of current FIR ACT1 if needed + , mask_out => fir0_mask_out -- output of current FIR MASK if needed + , sc_parity_error_inject => sc_parity_error_inject -- Force parity error + -- scom register connections + , sc_active => sc_active + , sc_wr_q => sc_wr_q + , sc_addr_v => sc_addr_v(0 to 8) + , sc_wdata => sc_wdata(32 to 32+fir0_width-1) + , sc_wparity => sc_wparity + , sc_rdata => fir0_scrdata + , fir_parity_check => fir0_fir_parity_check + ); + +----------------------------------------------------------------------- +-- Error Input Facility + fir0_errors <= + iu_pc_err_icache_parity & iu_pc_err_icachedir_parity & -- 0:1 + xu_pc_err_dcache_parity & xu_pc_err_dcachedir_parity & -- 2:3 + xu_pc_err_sprg_ecc(0 to 3) & xu_pc_err_regfile_parity(0 to 3) & -- 4:11 + fu_pc_err_regfile_parity(0 to 3) & bx_pc_err_inbox_ecc & -- 12:16 + bx_pc_err_outbox_ecc & scom_reg_parity_err & -- 17:18 + scom_reg_ack_err & xu_pc_err_wdt_reset(0 to 3) & -- 19:23 + xu_pc_err_llbust_attempt(0 to 3) & xu_pc_err_llbust_failed(0 to 3) ; -- 24:31 + +-- Block FIR on checkstop (external input or from other FIRs) + fir0_block_on_checkstop <= an_ac_checkstop_q or xstop_err_q(1) or xstop_err_q(2); + + +--===================================================================== +-- FIR1 Instantiation +--===================================================================== +FIR1: entity work.pcq_local_fir2 + generic map( width => fir1_width, + expand_type => expand_type, + impl_lxstop_mchk => false, + use_recov_reset => false, + fir_init => fir1_init, + fir_mask_init => fir1mask_init, + fir_mask_par_init => fir1mask_par_init, + fir_action0_init => fir1act0_init, + fir_action0_par_init => fir1act0_par_init, + fir_action1_init => fir1act1_init, + fir_action1_par_init => fir1act1_par_init + ) + port map + -- Global lines for clocking and scan control + ( nclk => nclk + , vd => vdd + , gd => gnd + , lcb_clkoff_dc_b => lcb_clkoff_dc_b + , lcb_mpw1_dc_b => lcb_mpw1_dc_b + , lcb_mpw2_dc_b => lcb_mpw2_dc_b + , lcb_delay_lclkr_dc => lcb_delay_lclkr_dc + , lcb_act_dis_dc => lcb_act_dis_dc + , lcb_sg_0 => lcb_sg_0 + , lcb_func_slp_sl_thold_0 => lcb_func_slp_sl_thold_0 -- not power-managed + , lcb_cfg_slp_sl_thold_0 => lcb_cfg_slp_sl_thold_0 -- not power-managed + , mode_scan_siv => bcfg_siv(bcfg_fir1_offset to bcfg_fir1_offset + FIR1_bcfg_size-1) + , mode_scan_sov => bcfg_sov(bcfg_fir1_offset to bcfg_fir1_offset + FIR1_bcfg_size-1) + , func_scan_siv => func_siv(func_fir1_offset to func_fir1_offset + FIR1_func_size-1) + , func_scan_sov => func_sov(func_fir1_offset to func_fir1_offset + FIR1_func_size-1) + -- external interface + , error_in => fir1_errors_q -- needs to be directly off a latch for timing + , xstop_err => fir1_xstop_err -- checkstop output to Global FIR + , recov_err => fir1_recov_err -- recoverable output to Global FIR + , lxstop_mchk => fir1_lxstop_mchk -- use ONLY if impl_lxstop_mchk = true + , trace_error => fir1_trace_error -- connect to error_input of closest trdata macro + , sys_xstop_in => fir1_block_on_checkstop -- freeze FIR on other checkstop errors + , recov_reset => tidn -- only needed if use_recov_reset = true + , fir_out => fir1_fir_out -- output of current FIR state if needed + , act0_out => fir1_act0_out -- output of current FIR ACT0 if needed + , act1_out => fir1_act1_out -- output of current FIR ACT1 if needed + , mask_out => fir1_mask_out -- output of current FIR MASK if needed + , sc_parity_error_inject => sc_parity_error_inject -- Force parity error + -- scom register connections + , sc_active => sc_active + , sc_wr_q => sc_wr_q + , sc_addr_v => sc_addr_v(10 to 18) + , sc_wdata => sc_wdata(32 to 32+fir1_width-1) + , sc_wparity => sc_wparity + , sc_rdata => fir1_scrdata + , fir_parity_check => fir1_fir_parity_check + ); + +----------------------------------------------------------------------- +-- Error Input Facility + fir1_errors <= + maxRecErrCntrValue_errrpt & xu_pc_err_l2intrf_ecc & -- 0:1 + xu_pc_err_l2intrf_ue & xu_pc_err_l2credit_overrun & -- 2:3 + xu_pc_err_sprg_ue(0 to 3) & xu_pc_err_regfile_ue(0 to 3) & -- 4:11 + fu_pc_err_regfile_ue(0 to 3) & xu_pc_err_nia_miscmpr(0 to 3) & -- 12:19 + xu_pc_err_debug_event(0 to 3) & iu_pc_err_ucode_illegal(0 to 3) & -- 20:27 + bx_pc_err_inbox_ue & bx_pc_err_outbox_ue & -- 28:29 + xu_pc_err_invld_reld & fir_regs_parity_err ; -- 30:31 + + +----------------------------------------------------------------------- +-- Block FIR on checkstop (external input or from other FIRs) + fir1_block_on_checkstop <= an_ac_checkstop_q or xstop_err_q(0) or xstop_err_q(2); + + +--===================================================================== +-- FIR2 Instantiation +--===================================================================== +FIR2: entity work.pcq_local_fir2 + generic map( width => fir2_width, + expand_type => expand_type, + impl_lxstop_mchk => false, + use_recov_reset => false, + fir_init => fir2_init, + fir_mask_init => fir2mask_init, + fir_mask_par_init => fir2mask_par_init, + fir_action0_init => fir2act0_init, + fir_action0_par_init => fir2act0_par_init, + fir_action1_init => fir2act1_init, + fir_action1_par_init => fir2act1_par_init + ) + port map + -- Global lines for clocking and scan control + ( nclk => nclk + , vd => vdd + , gd => gnd + , lcb_clkoff_dc_b => lcb_clkoff_dc_b + , lcb_mpw1_dc_b => lcb_mpw1_dc_b + , lcb_mpw2_dc_b => lcb_mpw2_dc_b + , lcb_delay_lclkr_dc => lcb_delay_lclkr_dc + , lcb_act_dis_dc => lcb_act_dis_dc + , lcb_sg_0 => lcb_sg_0 + , lcb_func_slp_sl_thold_0 => lcb_func_slp_sl_thold_0 -- not power-managed + , lcb_cfg_slp_sl_thold_0 => lcb_cfg_slp_sl_thold_0 -- not power-managed + , mode_scan_siv => bcfg_siv(bcfg_fir2_offset to bcfg_fir2_offset + FIR2_bcfg_size-1) + , mode_scan_sov => bcfg_sov(bcfg_fir2_offset to bcfg_fir2_offset + FIR2_bcfg_size-1) + , func_scan_siv => func_siv(func_fir2_offset to func_fir2_offset + FIR2_func_size-1) + , func_scan_sov => func_sov(func_fir2_offset to func_fir2_offset + FIR2_func_size-1) + -- external interface + , error_in => fir2_errors_q -- needs to be directly off a latch for timing + , xstop_err => fir2_xstop_err -- checkstop output to Global FIR + , recov_err => fir2_recov_err -- recoverable output to Global FIR + , lxstop_mchk => fir2_lxstop_mchk -- use ONLY if impl_lxstop_mchk = true + , trace_error => fir2_trace_error -- connect to error_input of closest trdata macro + , sys_xstop_in => fir2_block_on_checkstop -- freeze FIR on other checkstop errors + , recov_reset => tidn -- only needed if use_recov_reset = true + , fir_out => fir2_fir_out -- output of current FIR state if needed + , act0_out => fir2_act0_out -- output of current FIR ACT0 if needed + , act1_out => fir2_act1_out -- output of current FIR ACT1 if needed + , mask_out => fir2_mask_out -- output of current FIR MASK if needed + , sc_parity_error_inject => sc_parity_error_inject -- Force parity error + -- scom register connections + , sc_active => sc_active + , sc_wr_q => sc_wr_q + , sc_addr_v => sc_addr_v(20 to 28) + , sc_wdata => sc_wdata(32 to 32+fir2_width-1) + , sc_wparity => sc_wparity + , sc_rdata => fir2_scrdata + , fir_parity_check => fir2_fir_parity_check + ); + + +----------------------------------------------------------------------- +-- Error Input Facility + fir2_errors <= + xu_pc_err_mcsr_summary(0 to 3) & -- 0:3 + xu_pc_err_ierat_parity & xu_pc_err_derat_parity & -- 4:5 + xu_pc_err_tlb_parity & xu_pc_err_tlb_lru_parity & -- 6:7 + xu_pc_err_ierat_multihit & xu_pc_err_derat_multihit & -- 8:9 + xu_pc_err_tlb_multihit & xu_pc_err_ext_mchk & -- 10:11 + xu_pc_err_local_snoop_reject & xu_pc_err_ditc_overrun & -- 12:13 + xu_pc_err_mchk_disabled & fir2_errors_q(15 to 19) & -- 14:19 spares (wrapback dout=>din) + iu_pc_err_icachedir_multihit & xu_pc_err_dcachedir_multihit ; -- 20:21 + + +----------------------------------------------------------------------- +-- Block FIR on checkstop (external input or from other FIRs) + fir2_block_on_checkstop <= an_ac_checkstop_q or xstop_err_q(0) or xstop_err_q(1); + + +--===================================================================== +-- SCOM Register Read +--===================================================================== + scom_err_rpt_held <= sc_reg_par_err_hold(0 to scpar_err_rpt_width-1) & + sc_reg_ack_err_hold(0 to scack_err_rpt_width-1) & + (scpar_err_rpt_width+scack_err_rpt_width to 63 => '0'); + + sc_rdata <= gate_and(sc_addr_v(0), tidn_32 & fir0_fir_out) or + gate_and(sc_addr_v(3), tidn_32 & fir0_act0_out) or + gate_and(sc_addr_v(4), tidn_32 & fir0_act1_out) or + gate_and(sc_addr_v(6), tidn_32 & fir0_mask_out) or + gate_and(sc_addr_v(10), tidn_32 & fir1_fir_out) or + gate_and(sc_addr_v(13), tidn_32 & fir1_act0_out) or + gate_and(sc_addr_v(14), tidn_32 & fir1_act1_out) or + gate_and(sc_addr_v(16), tidn_32 & fir1_mask_out) or + gate_and(sc_addr_v(20), tidn_32 & fir2_fir_out & "0000000000") or + gate_and(sc_addr_v(23), tidn_32 & fir2_act0_out & "0000000000") or + gate_and(sc_addr_v(24), tidn_32 & fir2_act1_out & "0000000000") or + gate_and(sc_addr_v(26), tidn_32 & fir2_mask_out & "0000000000") or + gate_and(sc_addr_v(5), scom_err_rpt_held) or + gate_and(sc_addr_v(19), fir0_fir_out & fir1_fir_out) ; + + +--===================================================================== +-- Error Related Signals +--===================================================================== +-- SCOM parity error reporting macro + sc_reg_par_err_in <= scom_reg_par_checks & fir0_fir_parity_check & + fir1_fir_parity_check & fir2_fir_parity_check ; + + scom_reg_parity_err <= or_reduce(sc_reg_par_err_out(0 to 6)); + fir_regs_parity_err <= or_reduce(sc_reg_par_err_out(7 to 15)); + + scom_err : entity tri.tri_err_rpt + generic map + ( width => scpar_err_rpt_width + , mask_reset_value => scpar_rpt_reset_value + , inline => false + , expand_type => expand_type + ) -- use to bundle error reporting checkers of the same exact type + port map + ( vd => vdd + , gd => gnd + , err_d1clk => cfgslp_d1clk -- CAUTION: if LCB uses powersavings, + , err_d2clk => cfgslp_d2clk -- errors must always get reported + , err_lclk => cfgslp_lclk + , err_scan_in => bcfg_siv(bcfg_erpt1_hld_offset to bcfg_erpt1_hld_offset + scpar_err_rpt_width-1) + , err_scan_out => bcfg_sov(bcfg_erpt1_hld_offset to bcfg_erpt1_hld_offset + scpar_err_rpt_width-1) + , mode_dclk => cfg_slat_d2clk + , mode_lclk => cfg_slat_lclk + , mode_scan_in => bcfg_siv(bcfg_erpt1_msk_offset to bcfg_erpt1_msk_offset + scpar_err_rpt_width-1) + , mode_scan_out => bcfg_sov(bcfg_erpt1_msk_offset to bcfg_erpt1_msk_offset + scpar_err_rpt_width-1) + , err_in => sc_reg_par_err_in + , err_out => sc_reg_par_err_out + , hold_out => sc_reg_par_err_hold + ); + +----------------------------------------------------------------------- +-- SCOM control error reporting macro + sc_reg_ack_err_in <= scom_ack_error & scom_sat_fsm_error; + scom_reg_ack_err <= or_reduce(sc_reg_ack_err_out); + + sc_ack_err : entity tri.tri_err_rpt + generic map + ( width => scack_err_rpt_width + , mask_reset_value => scack_rpt_reset_value + , inline => false + , expand_type => expand_type + ) -- use to bundle error reporting checkers of the same exact type + port map + ( vd => vdd + , gd => gnd + , err_d1clk => cfgslp_d1clk -- CAUTION: if LCB uses powersavings, + , err_d2clk => cfgslp_d2clk -- errors must always get reported + , err_lclk => cfgslp_lclk + , err_scan_in => bcfg_siv(bcfg_erpt2_hld_offset to bcfg_erpt2_hld_offset + scack_err_rpt_width-1) + , err_scan_out => bcfg_sov(bcfg_erpt2_hld_offset to bcfg_erpt2_hld_offset + scack_err_rpt_width-1) + , mode_dclk => cfg_slat_d2clk + , mode_lclk => cfg_slat_lclk + , mode_scan_in => bcfg_siv(bcfg_erpt2_msk_offset to bcfg_erpt2_msk_offset + scack_err_rpt_width-1) + , mode_scan_out => bcfg_sov(bcfg_erpt2_msk_offset to bcfg_erpt2_msk_offset + scack_err_rpt_width-1) + , err_in => sc_reg_ack_err_in + , err_out => sc_reg_ack_err_out + , hold_out => sc_reg_ack_err_hold + ); + +----------------------------------------------------------------------- +-- Other error reporting macros + + misc_dir_err : entity tri.tri_direct_err_rpt + generic map + ( width => 1 + , expand_type => expand_type + ) + port map + ( vd => vdd + , gd => gnd + , err_in(0) => rg_rg_maxRecErrCntrValue + , err_out(0) => maxRecErrCntrValue_errrpt + ); + + +----------------------------------------------------------------------- +-- Error related facilities used in other functions + -- FIR0 Errors that increment the recoverable error counter + -- Only use fir0_act1_out so that a local_checkstop will count as a recoverable error. + fir0_recoverable_errors <= fir0_errors_q and fir0_act1_out and not fir0_mask_out; + fir0_recov_err_in(0) <= or_reduce(fir0_recoverable_errors); + fir0_recov_err_in(1) <= fir0_recov_err_q(0); + -- Only indicates 1 recoverable error pulse if error input active multiple cycles + fir0_recov_err_pulse <= fir0_recov_err_q(0) and not fir0_recov_err_q(1); + + + -- FIR1 Errors that increment the recoverable error counter + -- Only use fir1_act1_out so that a local_checkstop will count as a recoverable error. + fir1_recoverable_errors <= fir1_errors_q and fir1_act1_out and not fir1_mask_out; + -- Leaving maxRecErrCntrValue (FIR1(0)) out of input that gates recoverable error counter. + fir1_recov_err_in(0) <= or_reduce(fir1_recoverable_errors(1 to fir1_width-1)); + fir1_recov_err_in(1) <= fir1_recov_err_q(0); + -- Only indicates 1 recoverable error pulse if error input active multiple cycles + fir1_recov_err_pulse <= fir1_recov_err_q(0) and not fir1_recov_err_q(1); + + + -- FIR2 Errors that increment the recoverable error counter + -- Only use fir2_act1_out so that a local_checkstop will count as a recoverable error. + fir2_recoverable_errors <= fir2_errors_q and fir2_act1_out and not fir2_mask_out; + fir2_recov_err_in(0) <= or_reduce(fir2_recoverable_errors); + fir2_recov_err_in(1) <= fir2_recov_err_q(0); + -- Only indicates 1 recoverable error pulse if error input active multiple cycles + fir2_recov_err_pulse <= fir2_recov_err_q(0) and not fir2_recov_err_q(1); + + + -- Enabled checkstop errors used to stop failing thread. + fir0_enabled_checkstops <= fir0_fir_out and fir0_act0_out and not fir0_act1_out and not fir0_mask_out; + fir1_enabled_checkstops <= fir1_fir_out and fir1_act0_out and not fir1_act1_out and not fir1_mask_out; + fir2_enabled_checkstops <= fir2_fir_out(4 to fir2_width-1) and -- F!R2(36 to 53) + fir2_act0_out(4 to fir2_width-1) and not + fir2_act1_out(4 to fir2_width-1) and not + fir2_mask_out(4 to fir2_width-1) ; + +----------------------------------------------------------------------- +-- Determines how errors will force failing thread(s) to stop if configured as checkstop: +-- This is based on the error bit definition in each FIR (thread specific or per core). +-- +-- T0 FIR0(36,40,44,52,56,60) FIR1(36,40,44,48,52,56) FIR2(32 and 36:51) +-- T1 FIR0(37,41,45,53,57,61) FIR1(37,41,45,49,53,57) FIR2(33 and 36:51) +-- T2 FIR0(38,42,46,54,58,62) FIR1(38,42,46,50,54,58) FIR2(34 and 36:51) +-- T3 FIR0(39,43,47,55,59,63) FIR1(39,43,47,51,55,59) FIR2(35 and 36:51) +-- Per core FIR0(32:35,48:51) FIR1(32:35,60:63) FIR2(52:53) +-- + xstop_err_common <= or_reduce(fir0_enabled_checkstops(32 to 35) & fir0_enabled_checkstops(48 to 51)) or + or_reduce(fir1_enabled_checkstops(32 to 35) & fir1_enabled_checkstops(60 to 63)) or + or_reduce(fir2_enabled_checkstops(52 to 53)); + + xstop_err_per_thread(0) <= fir0_enabled_checkstops(36) or fir0_enabled_checkstops(40) or + fir0_enabled_checkstops(44) or fir0_enabled_checkstops(52) or + fir0_enabled_checkstops(56) or fir0_enabled_checkstops(60) or + fir1_enabled_checkstops(36) or fir1_enabled_checkstops(40) or + fir1_enabled_checkstops(44) or fir1_enabled_checkstops(48) or + fir1_enabled_checkstops(52) or fir1_enabled_checkstops(56) or + (fir2_fir_out(0) and or_reduce(fir2_enabled_checkstops(36 to 51))) or + xstop_err_common; + + xstop_err_per_thread(1) <= fir0_enabled_checkstops(37) or fir0_enabled_checkstops(41) or + fir0_enabled_checkstops(45) or fir0_enabled_checkstops(53) or + fir0_enabled_checkstops(57) or fir0_enabled_checkstops(61) or + fir1_enabled_checkstops(37) or fir1_enabled_checkstops(41) or + fir1_enabled_checkstops(45) or fir1_enabled_checkstops(49) or + fir1_enabled_checkstops(53) or fir1_enabled_checkstops(57) or + (fir2_fir_out(1) and or_reduce(fir2_enabled_checkstops(36 to 51))) or + xstop_err_common; + + xstop_err_per_thread(2) <= fir0_enabled_checkstops(38) or fir0_enabled_checkstops(42) or + fir0_enabled_checkstops(46) or fir0_enabled_checkstops(54) or + fir0_enabled_checkstops(58) or fir0_enabled_checkstops(62) or + fir1_enabled_checkstops(38) or fir1_enabled_checkstops(42) or + fir1_enabled_checkstops(46) or fir1_enabled_checkstops(50) or + fir1_enabled_checkstops(54) or fir1_enabled_checkstops(58) or + (fir2_fir_out(2) and or_reduce(fir2_enabled_checkstops(36 to 51))) or + xstop_err_common; + + xstop_err_per_thread(3) <= fir0_enabled_checkstops(39) or fir0_enabled_checkstops(43) or + fir0_enabled_checkstops(47) or fir0_enabled_checkstops(55) or + fir0_enabled_checkstops(59) or fir0_enabled_checkstops(63) or + fir1_enabled_checkstops(39) or fir1_enabled_checkstops(43) or + fir1_enabled_checkstops(47) or fir1_enabled_checkstops(51) or + fir1_enabled_checkstops(55) or fir1_enabled_checkstops(59) or + (fir2_fir_out(3) and or_reduce(fir2_enabled_checkstops(36 to 51))) or + xstop_err_common; + +----------------------------------------------------------------------- +-- Report xstop + lxstop errors to Chiplet FIR. Can bypass in Ram mode if override signal active. + xstop_err_int(0) <= fir0_xstop_err; + xstop_err_int(1) <= fir1_xstop_err; + xstop_err_int(2) <= fir2_xstop_err; + + rg_rg_any_fir_xstop <= or_reduce(xstop_err_int(0 to 2)); + + lxstop_err_int(0) <= fir0_lxstop_mchk; + lxstop_err_int(1) <= fir1_lxstop_mchk; + lxstop_err_int(2) <= fir2_lxstop_mchk; + + block_xstop_in_ram_mode <= rg_rg_xstop_report_ovride and rg_rg_ram_mode; + xstop_out_d(0 to 2) <= gate_and(not block_xstop_in_ram_mode, xstop_err_int(0 to 2)); + +----------------------------------------------------------------------- +-- Error injection shutoff control signals + injoff_icache_parity <= fir0_errors_q(0); + injoff_icachedir_parity <= fir0_errors_q(1); + injoff_dcache_parity <= fir0_errors_q(2); + injoff_dcachedir_parity <= fir0_errors_q(3); + injoff_sprg_ecc <= or_reduce(fir0_errors_q(4 to 7)); + injoff_xuregfile_parity <= or_reduce(fir0_errors_q(8 to 11)); + injoff_furegfile_parity <= or_reduce(fir0_errors_q(12 to 15)); + injoff_inbox_ecc <= fir0_errors_q(16); + injoff_outbox_ecc <= fir0_errors_q(17); + injoff_scomreg_parity <= fir0_errors_q(18); + injoff_wdt_reset <= or_reduce(fir0_errors_q(20 to 23)); + injoff_llbust_attempt <= or_reduce(fir0_errors_q(24 to 27)); + injoff_llbust_failed <= or_reduce(fir0_errors_q(28 to 31)); + injoff_icachedir_multihit <= fir2_errors_q(20); + injoff_dcachedir_multihit <= fir2_errors_q(21); + + + error_inject_shutoff <= injoff_icache_parity & injoff_icachedir_parity & + injoff_dcache_parity & injoff_dcachedir_parity & + injoff_xuregfile_parity & injoff_furegfile_parity & + injoff_sprg_ecc & injoff_inbox_ecc & + injoff_outbox_ecc & injoff_llbust_attempt & + injoff_llbust_failed & injoff_wdt_reset & + injoff_scomreg_parity & injoff_icachedir_multihit & + injoff_dcachedir_multihit ; + + +--===================================================================== +-- Output Assignments +--===================================================================== + ac_an_special_attn <= atten_instr_q(0 to 3); + + ac_an_checkstop <= xstop_out_q(0 to 2); + + ac_an_local_checkstop <= lxstop_err_q(0 to 2); + + ac_an_recov_err <= fir0_recov_err & fir1_recov_err & fir2_recov_err; + + ac_an_trace_error <= fir0_trace_error or fir1_trace_error or fir2_trace_error; + + rg_rg_xstop_err <= xstop_err_per_thread(0 to 3); + + rg_rg_ram_mode_xstop <= rg_rg_ram_mode and (fir0_xstop_err or fir1_xstop_err or fir2_xstop_err); + + rg_rg_errinj_shutoff <= error_inject_shutoff; + + rg_rg_gateRecErrCntr <= fir0_recov_err_pulse or fir1_recov_err_pulse or fir2_recov_err_pulse; + + -- Combined performance event for I-Cache and D-Cache parity errors + pc_xu_cache_par_err_event <= or_reduce(fir0_errors_q(0 to 3)); + + +--===================================================================== +-- Trace/Trigger Signals +--===================================================================== + dbg_fir0_err <= fir0_errors_q; + + dbg_fir1_err <= fir1_errors_q(0 to 30); + + dbg_fir2_err <= fir2_errors_q; + + dbg_fir_misc <= atten_instr_q(0 to 3) & -- 0:3 + fir0_xstop_err & -- 4 + fir1_xstop_err & -- 5 + fir2_xstop_err & -- 6 + fir0_recov_err & -- 7 + fir1_recov_err & -- 8 + fir2_recov_err & -- 9 + sc_reg_par_err_out_q(0 to 15) & -- 10:25 + sc_reg_ack_err_out_q(0 to 1) & -- 26:27 + xstop_err_per_thread(0 to 3) & -- 28:31 + block_xstop_in_ram_mode & -- 32 + fir0_recov_err_pulse & -- 33 + fir1_recov_err_pulse & -- 34 + fir2_recov_err_pulse ; -- 35 + + + +--===================================================================== +-- Latches +--===================================================================== + atten_instr : entity tri.tri_nlat_scan + generic map( width => attent_func_size, init => "0000", expand_type => expand_type ) + port map + ( d1clk => func_d1clk + , vd => vdd + , gd => gnd + , lclk => func_lclk + , d2clk => func_d2clk + , scan_in => func_siv(func_attent_offset to func_attent_offset + attent_func_size-1) + , scan_out => func_sov(func_attent_offset to func_attent_offset + attent_func_size-1) + , din => xu_pc_err_attention_instr + , q => atten_instr_q + ); + + error_out : entity tri.tri_nlat_scan + generic map( width => errout_func_size, init => x"00000000" & "00", expand_type => expand_type ) + port map + ( d1clk => func_d1clk + , vd => vdd + , gd => gnd + , lclk => func_lclk + , d2clk => func_d2clk + , scan_in => func_siv(func_errout_offset to func_errout_offset + errout_func_size-1) + , scan_out => func_sov(func_errout_offset to func_errout_offset + errout_func_size-1) + , din(0 to 2) => xstop_err_int + , din(3 to 5) => xstop_out_d + , din(6 to 8) => lxstop_err_int + , din(9 to 10) => fir0_recov_err_in + , din(11 to 12) => fir1_recov_err_in + , din(13 to 14) => fir2_recov_err_in + , din(15) => an_ac_checkstop + , din(16 to 31) => sc_reg_par_err_out + , din(32 to 33) => sc_reg_ack_err_out + , q(0 to 2) => xstop_err_q + , q(3 to 5) => xstop_out_q + , q(6 to 8) => lxstop_err_q + , q(9 to 10) => fir0_recov_err_q + , q(11 to 12) => fir1_recov_err_q + , q(13 to 14) => fir2_recov_err_q + , q(15) => an_ac_checkstop_q + , q(16 to 31) => sc_reg_par_err_out_q + , q(32 to 33) => sc_reg_ack_err_out_q + ); + + f0err_out : entity tri.tri_nlat_scan + generic map( width => fir0_width, init => fir0_init, expand_type => expand_type ) + port map + ( d1clk => func_d1clk + , vd => vdd + , gd => gnd + , lclk => func_lclk + , d2clk => func_d2clk + , scan_in => func_siv(func_f0err_offset to func_f0err_offset + fir0_width-1) + , scan_out => func_sov(func_f0err_offset to func_f0err_offset + fir0_width-1) + , din => fir0_errors + , q => fir0_errors_q + ); + + f1err_out : entity tri.tri_nlat_scan + generic map( width => fir1_width, init => fir1_init, expand_type => expand_type ) + port map + ( d1clk => func_d1clk + , vd => vdd + , gd => gnd + , lclk => func_lclk + , d2clk => func_d2clk + , scan_in => func_siv(func_f1err_offset to func_f1err_offset + fir1_width-1) + , scan_out => func_sov(func_f1err_offset to func_f1err_offset + fir1_width-1) + , din => fir1_errors + , q => fir1_errors_q + ); + + f2err_out : entity tri.tri_nlat_scan + generic map( width => fir2_width, init => fir2_init, expand_type => expand_type ) + port map + ( d1clk => func_d1clk + , vd => vdd + , gd => gnd + , lclk => func_lclk + , d2clk => func_d2clk + , scan_in => func_siv(func_f2err_offset to func_f2err_offset + fir2_width-1) + , scan_out => func_sov(func_f2err_offset to func_f2err_offset + fir2_width-1) + , din => fir2_errors + , q => fir2_errors_q + ); + + +--===================================================================== +-- LCBs +--===================================================================== +-- functional ring regs; NOT power managed + func_lcbor: entity tri.tri_lcbor + generic map (expand_type => expand_type ) + port map( clkoff_b => lcb_clkoff_dc_b, + thold => lcb_func_slp_sl_thold_0, + sg => lcb_sg_0, + act_dis => lcb_act_dis_dc, + forcee => func_force, + thold_b => func_thold_b + ); + + func_lcb: entity tri.tri_lcbnd + generic map (expand_type => expand_type ) + port map( act => tiup, -- not power saved + vd => vdd, + gd => gnd, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + nclk => nclk, + forcee => func_force, + sg => lcb_sg_0, + thold_b => func_thold_b, + d1clk => func_d1clk, + d2clk => func_d2clk, + lclk => func_lclk + ); + + +--===================================================================== +-- Scan Connections +--===================================================================== + bcfg_siv(0 to bcfg_right) <= bcfg_scan_in & bcfg_sov(0 to bcfg_right-1); + bcfg_scan_out <= bcfg_sov(bcfg_right); + + func_siv(0 to func_right) <= func_scan_in & func_sov(0 to func_right-1); + func_scan_out <= func_sov(func_right); + + +----------------------------------------------------------------------- +end pcq_regs_fir; diff --git a/rel/src/vhdl/work/pcq_spr.vhdl b/rel/src/vhdl/work/pcq_spr.vhdl new file mode 100644 index 0000000..3b5ca26 --- /dev/null +++ b/rel/src/vhdl/work/pcq_spr.vhdl @@ -0,0 +1,828 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- +-- Description: Pervasive Core SPRs and slowSPR Interface +-- +--***************************************************************************** + +library ieee; +use ieee.std_logic_1164.all; +library ibm; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; +library support; +use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + + +entity pcq_spr is +generic(regmode : integer := 6; + expand_type : integer := 2 ); -- 0 = ibm umbra, 1 = xilinx, 2 = ibm mpg +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + -- pervasive signals + scan_dis_dc_b : in std_ulogic; + lcb_clkoff_dc_b : in std_ulogic; + lcb_mpw1_dc_b : in std_ulogic; + lcb_mpw2_dc_b : in std_ulogic; + lcb_delay_lclkr_dc : in std_ulogic; + lcb_act_dis_dc : in std_ulogic; + pc_pc_func_sl_thold_0 : in std_ulogic; + pc_pc_sg_0 : in std_ulogic; + func_scan_in : in std_ulogic; + func_scan_out : out std_ulogic; + -- slowSPR Interface + slowspr_val_in : in std_ulogic; + slowspr_rw_in : in std_ulogic; + slowspr_etid_in : in std_ulogic_vector(0 to 1); + slowspr_addr_in : in std_ulogic_vector(0 to 9); + slowspr_data_in : in std_ulogic_vector(64-(2**regmode) to 63); + slowspr_done_in : in std_ulogic; + slowspr_val_out : out std_ulogic; + slowspr_rw_out : out std_ulogic; + slowspr_etid_out : out std_ulogic_vector(0 to 1); + slowspr_addr_out : out std_ulogic_vector(0 to 9); + slowspr_data_out : out std_ulogic_vector(64-(2**regmode) to 63); + slowspr_done_out : out std_ulogic; + -- register outputs + sp_rg_trace_bus_enable : out std_ulogic; + pc_fu_instr_trace_mode : out std_ulogic; + pc_fu_instr_trace_tid : out std_ulogic_vector(0 to 1); + pc_xu_instr_trace_mode : out std_ulogic; + pc_xu_instr_trace_tid : out std_ulogic_vector(0 to 1); + pc_fu_event_count_mode : out std_ulogic_vector(0 to 2); + pc_iu_event_count_mode : out std_ulogic_vector(0 to 2); + pc_mm_event_count_mode : out std_ulogic_vector(0 to 2); + pc_xu_event_count_mode : out std_ulogic_vector(0 to 2); + pc_fu_event_mux_ctrls : out std_ulogic_vector(0 to 31); + pc_iu_event_mux_ctrls : out std_ulogic_vector(0 to 47); + pc_mm_event_mux_ctrls : out std_ulogic_vector(0 to 39); + pc_xu_event_mux_ctrls : out std_ulogic_vector(0 to 47); + pc_xu_lsu_event_mux_ctrls : out std_ulogic_vector(0 to 47); + sp_db_event_mux_ctrls : out std_ulogic_vector(0 to 23); + pc_fu_event_bus_enable : out std_ulogic; + pc_iu_event_bus_enable : out std_ulogic; + pc_rp_event_bus_enable : out std_ulogic; + pc_xu_event_bus_enable : out std_ulogic; + sp_db_event_bus_enable : out std_ulogic; + -- Trace/Trigger Signals + dbg_spr : out std_ulogic_vector(0 to 46) +); + +-- synopsys translate_off + + +-- synopsys translate_on +end pcq_spr; + + +architecture pcq_spr of pcq_spr is +--===================================================================== +-- Signal Declarations +--===================================================================== +-- Scan Ring Constants: +-- Register sizes +constant cesr_size : positive := 32; +constant aesr_size : positive := 32; +constant iesr1_size : positive := 24; +constant iesr2_size : positive := 24; +constant mesr1_size : positive := 20; +constant mesr2_size : positive := 20; +constant xesr1_size : positive := 24; +constant xesr2_size : positive := 24; +constant xesr3_size : positive := 24; +constant xesr4_size : positive := 24; +constant pc_data_size : positive := 2**regmode; + +-- start of func scan chain ordering +constant slowspr_val_offset : natural := 0; +constant slowspr_rw_offset : natural := slowspr_val_offset + 1; +constant slowspr_etid_offset : natural := slowspr_rw_offset + 1; +constant slowspr_addr_offset : natural := slowspr_etid_offset + 2; +constant slowspr_data_offset : natural := slowspr_addr_offset + 10; +constant slowspr_done_offset : natural := slowspr_data_offset + 2**regmode; +constant pc_val_offset : natural := slowspr_done_offset + 1; +constant pc_rw_offset : natural := pc_val_offset + 1; +constant pc_etid_offset : natural := pc_rw_offset + 1; +constant pc_addr_offset : natural := pc_etid_offset + 2; +constant pc_data_offset : natural := pc_addr_offset + 10; +constant pc_done_offset : natural := pc_data_offset + 2**regmode; +constant cesr_offset : natural := pc_done_offset + 1; +constant aesr_offset : natural := cesr_offset + cesr_size; +constant iesr1_offset : natural := aesr_offset + aesr_size; +constant iesr2_offset : natural := iesr1_offset + iesr1_size; +constant mesr1_offset : natural := iesr2_offset + iesr2_size; +constant mesr2_offset : natural := mesr1_offset + mesr1_size; +constant xesr1_offset : natural := mesr2_offset + mesr2_size; +constant xesr2_offset : natural := xesr1_offset + xesr1_size; +constant xesr3_offset : natural := xesr2_offset + xesr2_size; +constant xesr4_offset : natural := xesr3_offset + xesr3_size; +constant func_right : natural := xesr4_offset + xesr4_size - 1; +-- end of func scan chain ordering + +constant CESR_MASK : std_ulogic_vector(32 to 63) := "11111111111111111111111111111111"; +constant EVENTMUX_32_MASK : std_ulogic_vector(32 to 63) := "11111111111111111111111111111111"; +constant EVENTMUX_64_MASK : std_ulogic_vector(32 to 63) := "11111111111111111111000000000000"; +constant EVENTMUX_128_MASK : std_ulogic_vector(32 to 63) := "11111111111111111111111100000000"; + +---------------------------- +-- signals +---------------------------- +signal slowspr_val_d : std_ulogic; +signal slowspr_val_l2 : std_ulogic; +signal slowspr_rw_d : std_ulogic; +signal slowspr_rw_l2 : std_ulogic; +signal slowspr_etid_d : std_ulogic_vector(0 to 1); +signal slowspr_etid_l2 : std_ulogic_vector(0 to 1); +signal slowspr_addr_d : std_ulogic_vector(0 to 9); +signal slowspr_addr_l2 : std_ulogic_vector(0 to 9); +signal slowspr_data_d : std_ulogic_vector(64-(2**regmode) to 63); +signal slowspr_data_l2 : std_ulogic_vector(64-(2**regmode) to 63); +signal slowspr_done_d : std_ulogic; +signal slowspr_done_l2 : std_ulogic; + +signal pc_val_d : std_ulogic; +signal pc_val_l2 : std_ulogic; +signal pc_rw_d : std_ulogic; +signal pc_rw_l2 : std_ulogic; +signal pc_etid_d : std_ulogic_vector(0 to 1); +signal pc_etid_l2 : std_ulogic_vector(0 to 1); +signal pc_addr_d : std_ulogic_vector(0 to 9); +signal pc_addr_l2 : std_ulogic_vector(0 to 9); +signal pc_done_d : std_ulogic; +signal pc_done_l2 : std_ulogic; +signal pc_data_d : std_ulogic_vector(64-(2**regmode) to 63); +signal pc_data_l2 : std_ulogic_vector(64-(2**regmode) to 63); +signal pc_done_int : std_ulogic; +signal pc_data_int : std_ulogic_vector(64-(2**regmode) to 63); +signal pc_reg_data : std_ulogic_vector(32 to 63); + +signal cesr_sel : std_ulogic; +signal cesr_wren : std_ulogic; +signal cesr_rden : std_ulogic; +signal cesr_d : std_ulogic_vector(32 to 32+cesr_size-1); +signal cesr_l2 : std_ulogic_vector(32 to 32+cesr_size-1); +signal cesr_out : std_ulogic_vector(32 to 63); + +signal aesr_sel : std_ulogic; +signal aesr_wren : std_ulogic; +signal aesr_rden : std_ulogic; +signal aesr_d : std_ulogic_vector(32 to 32+aesr_size-1); +signal aesr_l2 : std_ulogic_vector(32 to 32+aesr_size-1); +signal aesr_out : std_ulogic_vector(32 to 63); + +signal iesr1_sel : std_ulogic; +signal iesr1_wren : std_ulogic; +signal iesr1_rden : std_ulogic; +signal iesr1_d : std_ulogic_vector(32 to 32+iesr1_size-1); +signal iesr1_l2 : std_ulogic_vector(32 to 32+iesr1_size-1); +signal iesr1_out : std_ulogic_vector(32 to 63); + +signal iesr2_sel : std_ulogic; +signal iesr2_wren : std_ulogic; +signal iesr2_rden : std_ulogic; +signal iesr2_d : std_ulogic_vector(32 to 32+iesr2_size-1); +signal iesr2_l2 : std_ulogic_vector(32 to 32+iesr2_size-1); +signal iesr2_out : std_ulogic_vector(32 to 63); + +signal mesr1_sel : std_ulogic; +signal mesr1_wren : std_ulogic; +signal mesr1_rden : std_ulogic; +signal mesr1_d : std_ulogic_vector(32 to 32+mesr1_size-1); +signal mesr1_l2 : std_ulogic_vector(32 to 32+mesr1_size-1); +signal mesr1_out : std_ulogic_vector(32 to 63); + +signal mesr2_sel : std_ulogic; +signal mesr2_wren : std_ulogic; +signal mesr2_rden : std_ulogic; +signal mesr2_d : std_ulogic_vector(32 to 32+mesr2_size-1); +signal mesr2_l2 : std_ulogic_vector(32 to 32+mesr2_size-1); +signal mesr2_out : std_ulogic_vector(32 to 63); + +signal xesr1_sel : std_ulogic; +signal xesr1_wren : std_ulogic; +signal xesr1_rden : std_ulogic; +signal xesr1_d : std_ulogic_vector(32 to 32+xesr1_size-1); +signal xesr1_l2 : std_ulogic_vector(32 to 32+xesr1_size-1); +signal xesr1_out : std_ulogic_vector(32 to 63); + +signal xesr2_sel : std_ulogic; +signal xesr2_wren : std_ulogic; +signal xesr2_rden : std_ulogic; +signal xesr2_d : std_ulogic_vector(32 to 32+xesr2_size-1); +signal xesr2_l2 : std_ulogic_vector(32 to 32+xesr2_size-1); +signal xesr2_out : std_ulogic_vector(32 to 63); + +signal xesr3_sel : std_ulogic; +signal xesr3_wren : std_ulogic; +signal xesr3_rden : std_ulogic; +signal xesr3_d : std_ulogic_vector(32 to 32+xesr3_size-1); +signal xesr3_l2 : std_ulogic_vector(32 to 32+xesr3_size-1); +signal xesr3_out : std_ulogic_vector(32 to 63); + +signal xesr4_sel : std_ulogic; +signal xesr4_wren : std_ulogic; +signal xesr4_rden : std_ulogic; +signal xesr4_d : std_ulogic_vector(32 to 32+xesr4_size-1); +signal xesr4_l2 : std_ulogic_vector(32 to 32+xesr4_size-1); +signal xesr4_out : std_ulogic_vector(32 to 63); + +-- misc, pervasive signals +signal tiup : std_ulogic; +signal pc_pc_func_sl_thold_0_b : std_ulogic; +signal force_func : std_ulogic; +signal func_siv : std_ulogic_vector(0 to func_right); +signal func_sov : std_ulogic_vector(0 to func_right); + + +begin + +tiup <= '1'; + +------------------------------------------------- +-- latches +------------------------------------------------- +slowspr_val_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_pc_func_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(slowspr_val_offset), + scout => func_sov(slowspr_val_offset), + din => slowspr_val_d, + dout => slowspr_val_l2); + +slowspr_rw_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => slowspr_val_d, + thold_b => pc_pc_func_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(slowspr_rw_offset), + scout => func_sov(slowspr_rw_offset), + din => slowspr_rw_d, + dout => slowspr_rw_l2); + +slowspr_etid_reg: tri_rlmreg_p + generic map (width => slowspr_etid_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => slowspr_val_d, + thold_b => pc_pc_func_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(slowspr_etid_offset to slowspr_etid_offset + slowspr_etid_l2'length-1), + scout => func_sov(slowspr_etid_offset to slowspr_etid_offset + slowspr_etid_l2'length-1), + din => slowspr_etid_d, + dout => slowspr_etid_l2); + +slowspr_addr_reg: tri_rlmreg_p + generic map (width => slowspr_addr_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => slowspr_val_d, + thold_b => pc_pc_func_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(slowspr_addr_offset to slowspr_addr_offset + slowspr_addr_l2'length-1), + scout => func_sov(slowspr_addr_offset to slowspr_addr_offset + slowspr_addr_l2'length-1), + din => slowspr_addr_d, + dout => slowspr_addr_l2); + +slowspr_data_reg: tri_rlmreg_p + generic map (width => slowspr_data_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => slowspr_val_d, + thold_b => pc_pc_func_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(slowspr_data_offset to slowspr_data_offset + slowspr_data_l2'length-1), + scout => func_sov(slowspr_data_offset to slowspr_data_offset + slowspr_data_l2'length-1), + din => slowspr_data_d, + dout => slowspr_data_l2); + +slowspr_done_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => slowspr_val_d, + thold_b => pc_pc_func_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(slowspr_done_offset), + scout => func_sov(slowspr_done_offset), + din => slowspr_done_d, + dout => slowspr_done_l2); + +pc_val_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_pc_func_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(pc_val_offset), + scout => func_sov(pc_val_offset), + din => pc_val_d, + dout => pc_val_l2); + +pc_rw_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => pc_val_d, + thold_b => pc_pc_func_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(pc_rw_offset), + scout => func_sov(pc_rw_offset), + din => pc_rw_d, + dout => pc_rw_l2); + +pc_etid_reg: tri_rlmreg_p + generic map (width => pc_etid_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => pc_val_d, + thold_b => pc_pc_func_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(pc_etid_offset to pc_etid_offset + pc_etid_l2'length-1), + scout => func_sov(pc_etid_offset to pc_etid_offset + pc_etid_l2'length-1), + din => pc_etid_d, + dout => pc_etid_l2); + +pc_addr_reg: tri_rlmreg_p + generic map (width => pc_addr_l2'length, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => pc_val_d, + thold_b => pc_pc_func_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(pc_addr_offset to pc_addr_offset + pc_addr_l2'length-1), + scout => func_sov(pc_addr_offset to pc_addr_offset + pc_addr_l2'length-1), + din => pc_addr_d, + dout => pc_addr_l2); + +pc_data_reg: tri_rlmreg_p + generic map (width => pc_data_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => pc_val_d, + thold_b => pc_pc_func_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(pc_data_offset to pc_data_offset + pc_data_size-1), + scout => func_sov(pc_data_offset to pc_data_offset + pc_data_size-1), + din => pc_data_d, + dout => pc_data_l2); + +pc_done_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_pc_func_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(pc_done_offset), + scout => func_sov(pc_done_offset), + din => pc_done_d, + dout => pc_done_l2); + +cesr_reg: tri_ser_rlmreg_p + generic map (width => cesr_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => cesr_wren, + thold_b => pc_pc_func_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(cesr_offset to cesr_offset + cesr_size-1), + scout => func_sov(cesr_offset to cesr_offset + cesr_size-1), + din => cesr_d, + dout => cesr_l2); + +aesr_reg: tri_ser_rlmreg_p + generic map (width => aesr_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => aesr_wren, + thold_b => pc_pc_func_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(aesr_offset to aesr_offset + aesr_size-1), + scout => func_sov(aesr_offset to aesr_offset + aesr_size-1), + din => aesr_d, + dout => aesr_l2); + +iesr1_reg: tri_ser_rlmreg_p + generic map (width => iesr1_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iesr1_wren, + thold_b => pc_pc_func_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(iesr1_offset to iesr1_offset + iesr1_size-1), + scout => func_sov(iesr1_offset to iesr1_offset + iesr1_size-1), + din => iesr1_d, + dout => iesr1_l2); + +iesr2_reg: tri_ser_rlmreg_p + generic map (width => iesr2_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => iesr2_wren, + thold_b => pc_pc_func_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(iesr2_offset to iesr2_offset + iesr2_size-1), + scout => func_sov(iesr2_offset to iesr2_offset + iesr2_size-1), + din => iesr2_d, + dout => iesr2_l2); + +mesr1_reg: tri_ser_rlmreg_p + generic map (width => mesr1_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => mesr1_wren, + thold_b => pc_pc_func_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(mesr1_offset to mesr1_offset + mesr1_size-1), + scout => func_sov(mesr1_offset to mesr1_offset + mesr1_size-1), + din => mesr1_d, + dout => mesr1_l2); + +mesr2_reg: tri_ser_rlmreg_p + generic map (width => mesr2_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => mesr2_wren, + thold_b => pc_pc_func_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(mesr2_offset to mesr2_offset + mesr2_size-1), + scout => func_sov(mesr2_offset to mesr2_offset + mesr2_size-1), + din => mesr2_d, + dout => mesr2_l2); + +xesr1_reg: tri_ser_rlmreg_p + generic map (width => xesr1_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xesr1_wren, + thold_b => pc_pc_func_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(xesr1_offset to xesr1_offset + xesr1_size-1), + scout => func_sov(xesr1_offset to xesr1_offset + xesr1_size-1), + din => xesr1_d, + dout => xesr1_l2); + +xesr2_reg: tri_ser_rlmreg_p + generic map (width => xesr2_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xesr2_wren, + thold_b => pc_pc_func_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(xesr2_offset to xesr2_offset + xesr2_size-1), + scout => func_sov(xesr2_offset to xesr2_offset + xesr2_size-1), + din => xesr2_d, + dout => xesr2_l2); + +xesr3_reg: tri_ser_rlmreg_p + generic map (width => xesr3_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xesr3_wren, + thold_b => pc_pc_func_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(xesr3_offset to xesr3_offset + xesr3_size-1), + scout => func_sov(xesr3_offset to xesr3_offset + xesr3_size-1), + din => xesr3_d, + dout => xesr3_l2); + +xesr4_reg: tri_ser_rlmreg_p + generic map (width => xesr4_size, init => 0, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xesr4_wren, + thold_b => pc_pc_func_sl_thold_0_b, + sg => pc_pc_sg_0, + forcee => force_func, + delay_lclkr => lcb_delay_lclkr_dc, + mpw1_b => lcb_mpw1_dc_b, + mpw2_b => lcb_mpw2_dc_b, + scin => func_siv(xesr4_offset to xesr4_offset + xesr4_size-1), + scout => func_sov(xesr4_offset to xesr4_offset + xesr4_size-1), + din => xesr4_d, + dout => xesr4_l2); + +------------------------------------------------- +-- inputs + staging +------------------------------------------------- +slowspr_val_d <= slowspr_val_in; +slowspr_rw_d <= slowspr_rw_in; +slowspr_etid_d <= slowspr_etid_in; +slowspr_addr_d <= slowspr_addr_in; +slowspr_data_d <= slowspr_data_in; +slowspr_done_d <= slowspr_done_in; + +pc_val_d <= slowspr_val_l2; +pc_rw_d <= slowspr_rw_l2; +pc_etid_d <= slowspr_etid_l2; +pc_addr_d <= slowspr_addr_l2; +pc_data_d <= slowspr_data_l2 or pc_data_int; +pc_done_d <= slowspr_done_l2 or pc_done_int; + + +------------------------------------------------- +-- outputs +------------------------------------------------- +slowspr_val_out <= pc_val_l2; +slowspr_rw_out <= pc_rw_l2; +slowspr_etid_out <= pc_etid_l2; +slowspr_addr_out <= pc_addr_l2; +slowspr_data_out <= pc_data_l2; +slowspr_done_out <= pc_done_l2; + +-- Event Select Controls +sp_rg_trace_bus_enable <= cesr_out(36); + +pc_fu_instr_trace_mode <= cesr_out(37); +pc_fu_instr_trace_tid <= cesr_out(38 to 39); +pc_xu_instr_trace_mode <= cesr_out(37); +pc_xu_instr_trace_tid <= cesr_out(38 to 39); + +pc_fu_event_count_mode <= cesr_out(33 to 35); +pc_iu_event_count_mode <= cesr_out(33 to 35); +pc_mm_event_count_mode <= cesr_out(33 to 35); +pc_xu_event_count_mode <= cesr_out(33 to 35); + +pc_fu_event_bus_enable <= cesr_out(32); +pc_iu_event_bus_enable <= cesr_out(32); +pc_rp_event_bus_enable <= cesr_out(32); +pc_xu_event_bus_enable <= cesr_out(32); +sp_db_event_bus_enable <= cesr_out(32); + +pc_fu_event_mux_ctrls <= aesr_out(32 to 63); +pc_iu_event_mux_ctrls <= iesr1_out(32 to 55) & iesr2_out(32 to 55); +pc_mm_event_mux_ctrls <= mesr1_out(32 to 51) & mesr2_out(32 to 51); +pc_xu_event_mux_ctrls <= xesr1_out(32 to 55) & xesr2_out(32 to 55); +pc_xu_lsu_event_mux_ctrls <= xesr3_out(32 to 55) & xesr4_out(32 to 55); +sp_db_event_mux_ctrls <= cesr_out(40 to 63); + + +------------------------------------------------- +-- register select +------------------------------------------------- +cesr_sel <= slowspr_val_l2 and slowspr_addr_l2 = "1110010000"; -- 912 +aesr_sel <= slowspr_val_l2 and slowspr_addr_l2 = "1110010001"; -- 913 +iesr1_sel <= slowspr_val_l2 and slowspr_addr_l2 = "1110010010"; -- 914 +iesr2_sel <= slowspr_val_l2 and slowspr_addr_l2 = "1110010011"; -- 915 +mesr1_sel <= slowspr_val_l2 and slowspr_addr_l2 = "1110010100"; -- 916 +mesr2_sel <= slowspr_val_l2 and slowspr_addr_l2 = "1110010101"; -- 917 +xesr1_sel <= slowspr_val_l2 and slowspr_addr_l2 = "1110010110"; -- 918 +xesr2_sel <= slowspr_val_l2 and slowspr_addr_l2 = "1110010111"; -- 919 +xesr3_sel <= slowspr_val_l2 and slowspr_addr_l2 = "1110011000"; -- 920 +xesr4_sel <= slowspr_val_l2 and slowspr_addr_l2 = "1110011001"; -- 921 + +pc_done_int <= cesr_sel or aesr_sel or iesr1_sel or iesr2_sel or + mesr1_sel or mesr2_sel or xesr1_sel or xesr2_sel or + xesr3_sel or xesr4_sel; + + +------------------------------------------------- +-- register write +------------------------------------------------- +cesr_wren <= cesr_sel and slowspr_rw_l2 = '0'; +aesr_wren <= aesr_sel and slowspr_rw_l2 = '0'; +iesr1_wren <= iesr1_sel and slowspr_rw_l2 = '0'; +iesr2_wren <= iesr2_sel and slowspr_rw_l2 = '0'; +mesr1_wren <= mesr1_sel and slowspr_rw_l2 = '0'; +mesr2_wren <= mesr2_sel and slowspr_rw_l2 = '0'; +xesr1_wren <= xesr1_sel and slowspr_rw_l2 = '0'; +xesr2_wren <= xesr2_sel and slowspr_rw_l2 = '0'; +xesr3_wren <= xesr3_sel and slowspr_rw_l2 = '0'; +xesr4_wren <= xesr4_sel and slowspr_rw_l2 = '0'; + +cesr_d <= CESR_MASK(32 to 32+cesr_size-1) and slowspr_data_l2(32 to 32+cesr_size-1); +aesr_d <= EVENTMUX_32_MASK(32 to 32+aesr_size-1) and slowspr_data_l2(32 to 32+aesr_size-1); +iesr1_d <= EVENTMUX_128_MASK(32 to 32+iesr1_size-1) and slowspr_data_l2(32 to 32+iesr1_size-1); +iesr2_d <= EVENTMUX_128_MASK(32 to 32+iesr2_size-1) and slowspr_data_l2(32 to 32+iesr2_size-1); +mesr1_d <= EVENTMUX_64_MASK(32 to 32+mesr1_size-1) and slowspr_data_l2(32 to 32+mesr1_size-1); +mesr2_d <= EVENTMUX_64_MASK(32 to 32+mesr2_size-1) and slowspr_data_l2(32 to 32+mesr2_size-1); +xesr1_d <= EVENTMUX_128_MASK(32 to 32+xesr1_size-1) and slowspr_data_l2(32 to 32+xesr1_size-1); +xesr2_d <= EVENTMUX_128_MASK(32 to 32+xesr2_size-1) and slowspr_data_l2(32 to 32+xesr2_size-1); +xesr3_d <= EVENTMUX_128_MASK(32 to 32+xesr3_size-1) and slowspr_data_l2(32 to 32+xesr3_size-1); +xesr4_d <= EVENTMUX_128_MASK(32 to 32+xesr4_size-1) and slowspr_data_l2(32 to 32+xesr4_size-1); + + +------------------------------------------------- +-- register read +------------------------------------------------- +cesr_rden <= cesr_sel and slowspr_rw_l2 = '1'; +aesr_rden <= aesr_sel and slowspr_rw_l2 = '1'; +iesr1_rden <= iesr1_sel and slowspr_rw_l2 = '1'; +iesr2_rden <= iesr2_sel and slowspr_rw_l2 = '1'; +mesr1_rden <= mesr1_sel and slowspr_rw_l2 = '1'; +mesr2_rden <= mesr2_sel and slowspr_rw_l2 = '1'; +xesr1_rden <= xesr1_sel and slowspr_rw_l2 = '1'; +xesr2_rden <= xesr2_sel and slowspr_rw_l2 = '1'; +xesr3_rden <= xesr3_sel and slowspr_rw_l2 = '1'; +xesr4_rden <= xesr4_sel and slowspr_rw_l2 = '1'; + +cesr_out(32 to 63) <= cesr_l2; +aesr_out(32 to 63) <= aesr_l2; +iesr1_out(32 to 63) <= iesr1_l2 & (32+iesr1_size to 63 => '0'); +iesr2_out(32 to 63) <= iesr2_l2 & (32+iesr2_size to 63 => '0'); +mesr1_out(32 to 63) <= mesr1_l2 & (32+mesr1_size to 63 => '0'); +mesr2_out(32 to 63) <= mesr2_l2 & (32+mesr2_size to 63 => '0'); +xesr1_out(32 to 63) <= xesr1_l2 & (32+xesr1_size to 63 => '0'); +xesr2_out(32 to 63) <= xesr2_l2 & (32+xesr2_size to 63 => '0'); +xesr3_out(32 to 63) <= xesr3_l2 & (32+xesr3_size to 63 => '0'); +xesr4_out(32 to 63) <= xesr4_l2 & (32+xesr4_size to 63 => '0'); + +pc_reg_data(32 to 63) <= cesr_out when cesr_rden = '1' else + aesr_out when aesr_rden = '1' else + iesr1_out when iesr1_rden = '1' else + iesr2_out when iesr2_rden = '1' else + mesr1_out when mesr1_rden = '1' else + mesr2_out when mesr2_rden = '1' else + xesr1_out when xesr1_rden = '1' else + xesr2_out when xesr2_rden = '1' else + xesr3_out when xesr3_rden = '1' else + xesr4_out when xesr4_rden = '1' else + (others => '0'); + + +r64: if (regmode > 5) generate begin +pc_data_int(0 to 31) <= (others => '0'); +end generate; +pc_data_int(32 to 63) <= pc_reg_data(32 to 63); + + +--===================================================================== +-- Trace/Trigger Signals +--===================================================================== + dbg_spr <= slowspr_val_l2 & -- 0 + slowspr_rw_l2 & -- 1 + slowspr_etid_l2(0 to 1) & -- 2:3 + slowspr_addr_l2(0 to 9) & -- 4:13 + slowspr_data_l2(32 to 63) & -- 14:45 + pc_done_l2 ; -- 46 + + +--===================================================================== +-- Thold/SG Staging +--===================================================================== +-- func_slp lcbor +lcbor_funcslp: tri_lcbor +generic map (expand_type => expand_type ) +port map ( + clkoff_b => lcb_clkoff_dc_b, + thold => pc_pc_func_sl_thold_0, + sg => pc_pc_sg_0, + act_dis => lcb_act_dis_dc, + forcee => force_func, + thold_b => pc_pc_func_sl_thold_0_b ); + + +--===================================================================== +-- Scan Connections +--===================================================================== +-- Func ring +func_siv(0 TO func_right) <= func_scan_in & func_sov(0 to func_right-1); +func_scan_out <= func_sov(func_right) and scan_dis_dc_b; + + +----------------------------------------------------------------------- +end pcq_spr; diff --git a/rel/src/vhdl/work/xuq.vhdl b/rel/src/vhdl/work/xuq.vhdl new file mode 100644 index 0000000..5c5766a --- /dev/null +++ b/rel/src/vhdl/work/xuq.vhdl @@ -0,0 +1,2310 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- +-- Description: XU Top +-- +--***************************************************************************** + +library ieee,ibm,support,work; +use ieee.std_logic_1164.all; +use support.power_logic_pkg.all; +use work.xuq_pkg.mark_unused; + +library tri; +use tri.tri_latches_pkg.all; +entity xuq is + generic ( + expand_type : integer := 2; + threads : integer := 4; + eff_ifar : integer := 62; + uc_ifar : integer := 21; + l_endian_m : integer := 1; + real_data_add : integer := 42; + lmq_entries : integer := 8; + regmode : integer := 6; + hvmode : integer := 1; + a2mode : integer := 1; + dc_size : natural := 14; -- 16K D$ --> 14 32K D$ --> 15 + cl_size : natural := 6; -- 32Byte --> 5 64Byte --> 6 + load_credits : integer := 4; + store_credits : integer := 20; + st_data_32B_mode : integer := 1; + bcfg_epn_0to15 : integer := 0; + bcfg_epn_16to31 : integer := 0; + bcfg_epn_32to47 : integer := (2**16)-1; + bcfg_epn_48to51 : integer := (2**4)-1; + bcfg_rpn_22to31 : integer := (2**10)-1; + bcfg_rpn_32to47 : integer := (2**16)-1; + bcfg_rpn_48to51 : integer := (2**4)-1; + spr_xucr0_init_mod : integer := 0); + port ( + + -- Chip Inputs + an_ac_coreid : in std_ulogic_vector(54 to 61); + spr_pvr_version_dc : in std_ulogic_vector(8 to 15); + spr_pvr_revision_dc : in std_ulogic_vector(12 to 15); + an_ac_ext_interrupt : in std_ulogic_vector(0 to threads-1); + an_ac_crit_interrupt : in std_ulogic_vector(0 to threads-1); + an_ac_perf_interrupt : in std_ulogic_vector(0 to threads-1); + an_ac_tb_update_enable : in std_ulogic; + an_ac_tb_update_pulse : in std_ulogic; + an_ac_hang_pulse : in std_ulogic_vector(0 to threads-1); + an_ac_sleep_en : in std_ulogic_vector(0 to threads-1); + ac_tc_debug_trigger : out std_ulogic_vector(0 to threads-1); + an_ac_external_mchk : in std_ulogic_vector(0 to threads-1); + ac_tc_machine_check : out std_ulogic_vector(0 to threads-1); + an_ac_reservation_vld : in std_ulogic_vector(0 to threads-1); + an_ac_grffence_en_dc : in std_ulogic; + + -- Instruction Issue + iu_xu_is2_vld : in std_ulogic; + iu_xu_is2_instr : in std_ulogic_vector(0 to 31); + iu_xu_is2_match : in std_ulogic; + iu_xu_is2_ta : in std_ulogic_vector(0 to 5); + iu_xu_is2_ta_vld : in std_ulogic; + iu_xu_is2_s1 : in std_ulogic_vector(0 to 5); + iu_xu_is2_s1_vld : in std_ulogic; + iu_xu_is2_s2 : in std_ulogic_vector(0 to 5); + iu_xu_is2_s2_vld : in std_ulogic; + iu_xu_is2_s3 : in std_ulogic_vector(0 to 5); + iu_xu_is2_s3_vld : in std_ulogic; + iu_xu_is2_pred_update : in std_ulogic; + iu_xu_is2_pred_taken_cnt : in std_ulogic_vector(0 to 1); + iu_xu_is2_error : in std_ulogic_vector(0 to 2); + iu_xu_is2_tid : in std_ulogic_vector(0 to 3); + iu_xu_is2_ifar : in std_ulogic_vector(62-eff_ifar to 61); + iu_xu_is2_is_ucode : in std_ulogic; + iu_xu_is2_gshare : in std_ulogic_vector(0 to 3); + iu_xu_is2_axu_ld_or_st : in std_ulogic; + iu_xu_is2_axu_store : in std_ulogic; + iu_xu_is2_axu_ldst_size : in std_ulogic_vector(0 to 5); + iu_xu_is2_axu_ldst_update : in std_ulogic; + iu_xu_is2_axu_mftgpr : in std_ulogic; + iu_xu_is2_axu_mffgpr : in std_ulogic; + iu_xu_is2_axu_movedp : in std_ulogic; + iu_xu_is2_axu_instr_type : in std_ulogic_vector(0 to 2); + iu_xu_is2_axu_ldst_extpid : in std_ulogic; + iu_xu_is2_axu_ldst_tag : in std_ulogic_vector(0 to 8); + iu_xu_is2_axu_ldst_indexed : in std_ulogic; + iu_xu_is2_axu_ldst_forcealign : in std_ulogic; + iu_xu_is2_axu_ldst_forceexcept : in std_ulogic; + iu_xu_is2_ucode_vld : in std_ulogic; + + -- Instruction Fetches + iu_xu_request : in std_ulogic; + iu_xu_thread : in std_ulogic_vector(0 to 3); + iu_xu_ra : in std_ulogic_vector(64-real_data_add to 59); + iu_xu_wimge : in std_ulogic_vector(0 to 4); + iu_xu_userdef : in std_ulogic_vector(0 to 3); + + -- L2 Reload Inputs + an_ac_reld_data_vld : in std_ulogic; + an_ac_reld_core_tag : in std_ulogic_vector(0 to 4); + an_ac_reld_data : in std_ulogic_vector(0 to 127); + an_ac_reld_qw : in std_ulogic_vector(57 to 59); + an_ac_reld_ecc_err : in std_ulogic; + an_ac_reld_ecc_err_ue : in std_ulogic; + an_ac_reld_data_coming : in std_ulogic; + an_ac_reld_ditc : in std_ulogic; + an_ac_reld_crit_qw : in std_ulogic; + an_ac_reld_l1_dump : in std_ulogic; + + -- L2 load/store credit control + an_ac_req_ld_pop : in std_ulogic; + an_ac_req_st_pop : in std_ulogic; + an_ac_req_st_pop_thrd : in std_ulogic_vector(0 to 2); + an_ac_req_st_gather : in std_ulogic; + + an_ac_req_spare_ctrl_a1 : in std_ulogic_vector(0 to 3); + an_ac_flh2l2_gate : in std_ulogic; -- Gate L1 Hit forwarding SPR config bit + + lsu_reld_data_vld : out std_ulogic; -- reload data is coming in 2 cycles + lsu_reld_core_tag : out std_ulogic_vector(3 to 4); -- reload data destinatoin tag (thread) + lsu_reld_qw : out std_ulogic_vector(58 to 59); -- reload data + lsu_reld_ditc : out std_ulogic; -- reload data is for ditc (inbox) + lsu_reld_ecc_err : out std_ulogic; -- reload data has ecc error + lsu_reld_data : out std_ulogic_vector(0 to 127); -- reload data + + lsu_req_st_pop : out std_ulogic; + lsu_req_st_pop_thrd : out std_ulogic_vector(0 to 2); + + mm_xu_cr0_eq_valid : in std_ulogic_vector(0 to 3); + mm_xu_cr0_eq : in std_ulogic_vector(0 to 3); + mm_xu_lsu_req : in std_ulogic_vector(0 to 3); + mm_xu_lsu_ttype : in std_ulogic_vector(0 to 1); + mm_xu_lsu_wimge : in std_ulogic_vector(0 to 4); + mm_xu_lsu_u : in std_ulogic_vector(0 to 3); + mm_xu_lsu_addr : in std_ulogic_vector(64-real_data_add to 63); + mm_xu_lsu_lpid : in std_ulogic_vector(0 to 7); + mm_xu_lsu_lpidr : in std_ulogic_vector(0 to 7); + mm_xu_lsu_gs : in std_ulogic; + mm_xu_lsu_ind : in std_ulogic; + mm_xu_lsu_lbit : in std_ulogic; -- "L" bit, for large vs. small + xu_mm_lsu_token : out std_ulogic; + + -- redrive for boxes logic + ac_an_reld_ditc_pop_int : in std_ulogic_vector(0 to 3); + ac_an_reld_ditc_pop_q : out std_ulogic_vector(0 to 3); + bx_ib_empty_int : in std_ulogic_vector(0 to 3); + bx_ib_empty_q : out std_ulogic_vector(0 to 3); + + -- L2 Back Invalidate Inputs + an_ac_back_inv : in std_ulogic; + an_ac_back_inv_addr : in std_ulogic_vector(64-real_data_add to 63); + an_ac_back_inv_target_bit1 : in std_ulogic; + an_ac_back_inv_target_bit3 : in std_ulogic; + an_ac_back_inv_target_bit4 : in std_ulogic; + + -- L2 STCX complete + an_ac_stcx_complete : in std_ulogic_vector(0 to 3); + an_ac_stcx_pass : in std_ulogic_vector(0 to 3); + xu_iu_stcx_complete : out std_ulogic_vector(0 to 3); + + -- IU Load Miss Interface + xu_iu_ex4_loadmiss_target_type : out std_ulogic_vector(0 to 1); + xu_iu_ex4_loadmiss_tid : out std_ulogic_vector(0 to 3); + xu_iu_ex4_loadmiss_qentry : out std_ulogic_vector(0 to lmq_entries-1); + xu_iu_ex4_loadmiss_target : out std_ulogic_vector(0 to 8); + xu_iu_ex5_loadmiss_target_type : out std_ulogic_vector(0 to 1); + xu_iu_ex5_loadmiss_tid : out std_ulogic_vector(0 to 3); + xu_iu_ex5_loadmiss_qentry : out std_ulogic_vector(0 to lmq_entries-1); + xu_iu_ex5_loadmiss_target : out std_ulogic_vector(0 to 8); + xu_iu_complete_target_type : out std_ulogic_vector(0 to 1); + xu_iu_complete_tid : out std_ulogic_vector(0 to 3); + xu_iu_complete_qentry : out std_ulogic_vector(0 to lmq_entries-1); + xu_iu_larx_done_tid : out std_ulogic_vector(0 to 3); + xu_iu_set_barr_tid : out std_ulogic_vector(0 to 3); + xu_iu_ex6_icbi_val : out std_ulogic_vector(0 to 3); + xu_iu_ex6_icbi_addr : out std_ulogic_vector(64-real_data_add to 57); + + xu_iu_membar_tid : out std_ulogic_vector(0 to 3); + + -- Flush Outputs + xu_n_is2_flush : out std_ulogic_vector(0 to threads-1); + xu_n_rf0_flush : out std_ulogic_vector(0 to threads-1); + xu_n_rf1_flush : out std_ulogic_vector(0 to threads-1); + xu_n_ex1_flush : out std_ulogic_vector(0 to threads-1); + xu_n_ex2_flush : out std_ulogic_vector(0 to threads-1); + xu_n_ex3_flush : out std_ulogic_vector(0 to threads-1); + xu_n_ex4_flush : out std_ulogic_vector(0 to threads-1); + xu_n_ex5_flush : out std_ulogic_vector(0 to threads-1); + + xu_s_rf1_flush : out std_ulogic_vector(0 to threads-1); + xu_s_ex1_flush : out std_ulogic_vector(0 to threads-1); + xu_s_ex2_flush : out std_ulogic_vector(0 to threads-1); + xu_s_ex3_flush : out std_ulogic_vector(0 to threads-1); + xu_s_ex4_flush : out std_ulogic_vector(0 to threads-1); + xu_s_ex5_flush : out std_ulogic_vector(0 to threads-1); + + xu_wu_rf1_flush : out std_ulogic_vector(0 to threads-1); + xu_wu_ex1_flush : out std_ulogic_vector(0 to threads-1); + xu_wu_ex2_flush : out std_ulogic_vector(0 to threads-1); + xu_wu_ex3_flush : out std_ulogic_vector(0 to threads-1); + xu_wu_ex4_flush : out std_ulogic_vector(0 to threads-1); + xu_wu_ex5_flush : out std_ulogic_vector(0 to threads-1); + + xu_wl_rf1_flush : out std_ulogic_vector(0 to threads-1); + xu_wl_ex1_flush : out std_ulogic_vector(0 to threads-1); + xu_wl_ex2_flush : out std_ulogic_vector(0 to threads-1); + xu_wl_ex3_flush : out std_ulogic_vector(0 to threads-1); + xu_wl_ex4_flush : out std_ulogic_vector(0 to threads-1); + xu_wl_ex5_flush : out std_ulogic_vector(0 to threads-1); + + xu_mm_ex4_flush : out std_ulogic_vector(0 to threads-1); + xu_mm_ex5_flush : out std_ulogic_vector(0 to threads-1); + xu_mm_ierat_flush : out std_ulogic_vector(0 to threads-1); + xu_mm_ierat_miss : out std_ulogic_vector(0 to threads-1); + xu_mm_ex5_perf_itlb : out std_ulogic_vector(0 to threads-1); + xu_mm_ex5_perf_dtlb : out std_ulogic_vector(0 to threads-1); + + -- IU Flush Redirect Interface + xu_iu_run_thread : out std_ulogic_vector(0 to 3); + xu_iu_u_flush : out std_ulogic_vector(0 to 3); + xu_iu_l_flush : out std_ulogic_vector(0 to 3); + xu_iu_flush_2ucode : out std_ulogic_vector(0 to 3); + xu_iu_flush_2ucode_type : out std_ulogic_vector(0 to 3); + xu_iu_ucode_restart : out std_ulogic_vector(0 to 3); + xu_iu_ex5_ppc_cpl : out std_ulogic_vector(0 to threads-1); + xu_iu_iu0_flush_ifar0 : out std_ulogic_vector(62-eff_ifar to 61); + xu_iu_iu0_flush_ifar1 : out std_ulogic_vector(62-eff_ifar to 61); + xu_iu_iu0_flush_ifar2 : out std_ulogic_vector(62-eff_ifar to 61); + xu_iu_iu0_flush_ifar3 : out std_ulogic_vector(62-eff_ifar to 61); + xu_iu_uc_flush_ifar0 : out std_ulogic_vector(62-uc_ifar to 61); + xu_iu_uc_flush_ifar1 : out std_ulogic_vector(62-uc_ifar to 61); + xu_iu_uc_flush_ifar2 : out std_ulogic_vector(62-uc_ifar to 61); + xu_iu_uc_flush_ifar3 : out std_ulogic_vector(62-uc_ifar to 61); + + xu_iu_ici : out std_ulogic; + + -- IU Branch Predict Update + xu_iu_ex5_ifar : out std_ulogic_vector(62-eff_ifar to 61); + xu_iu_ex5_val : out std_ulogic; + xu_iu_ex5_tid : out std_ulogic_vector(0 to threads-1); + xu_iu_ex5_br_update : out std_ulogic; + xu_iu_ex5_br_hist : out std_ulogic_vector(0 to 1); + xu_iu_ex5_br_taken : out std_ulogic; + xu_iu_ex5_bclr : out std_ulogic; + xu_iu_ex5_lk : out std_ulogic; + xu_iu_ex5_bh : out std_ulogic_vector(0 to 1); + + -- IU Misc + iu_xu_quiesce : in std_ulogic_vector(0 to threads-1); + xu_iu_ex6_pri : out std_ulogic_vector(0 to 2); + xu_iu_ex6_pri_val : out std_ulogic_vector(0 to 3); + xu_iu_single_instr_mode : out std_ulogic_vector(0 to threads-1); + xu_iu_raise_iss_pri : out std_ulogic_vector(0 to threads-1); + xu_iu_multdiv_done : out std_ulogic_vector(0 to threads-1); + xu_iu_slowspr_done : out std_ulogic_vector(0 to 3); + xu_iu_need_hole : out std_ulogic; + xu_iu_ex5_gshare : out std_ulogic_vector(0 to 3); + xu_iu_ex5_getNIA : out std_ulogic; + + -- FU Ifar bus + fu_xu_rf1_act : in std_ulogic_vector(0 to threads-1); + fu_xu_ex2_ifar_val : in std_ulogic_vector(0 to threads-1); + fu_xu_ex2_ifar_issued : in std_ulogic_vector(0 to threads-1); + fu_xu_ex1_ifar0 : in std_ulogic_vector(62-eff_ifar to 61); + fu_xu_ex1_ifar1 : in std_ulogic_vector(62-eff_ifar to 61); + fu_xu_ex1_ifar2 : in std_ulogic_vector(62-eff_ifar to 61); + fu_xu_ex1_ifar3 : in std_ulogic_vector(62-eff_ifar to 61); + fu_xu_ex2_instr_type : in std_ulogic_vector(0 to 3*threads-1); + fu_xu_ex2_instr_match : in std_ulogic_vector(0 to threads-1); + fu_xu_ex2_is_ucode : in std_ulogic_vector(0 to threads-1); + fu_xu_ex3_trap : in std_ulogic_vector(0 to threads-1); + fu_xu_ex3_ap_int_req : in std_ulogic_vector(0 to threads-1); + fu_xu_ex3_n_flush : in std_ulogic_vector(0 to threads-1); + fu_xu_ex3_np1_flush : in std_ulogic_vector(0 to threads-1); + fu_xu_ex3_flush2ucode : in std_ulogic_vector(0 to threads-1); + fu_xu_ex2_async_block : in std_ulogic_vector(0 to threads-1); + + -- FU CR Write + fu_xu_ex4_cr_val : in std_ulogic_vector(0 to threads-1); + fu_xu_ex4_cr_noflush : in std_ulogic_vector(0 to threads-1); + fu_xu_ex4_cr0 : in std_ulogic_vector(0 to 3); + fu_xu_ex4_cr0_bf : in std_ulogic_vector(0 to 2); + fu_xu_ex4_cr1 : in std_ulogic_vector(0 to 3); + fu_xu_ex4_cr1_bf : in std_ulogic_vector(0 to 2); + fu_xu_ex4_cr2 : in std_ulogic_vector(0 to 3); + fu_xu_ex4_cr2_bf : in std_ulogic_vector(0 to 2); + fu_xu_ex4_cr3 : in std_ulogic_vector(0 to 3); + fu_xu_ex4_cr3_bf : in std_ulogic_vector(0 to 2); + + -- FU Load Data + xu_fu_ex3_eff_addr : out std_ulogic_vector(59 to 63); + xu_fu_ex5_reload_val : out std_ulogic; + xu_fu_ex5_load_le : out std_ulogic; + xu_fu_ex5_load_val : out std_ulogic_vector(0 to threads-1); + xu_fu_ex5_load_tag : out std_ulogic_vector(0 to 8); + xu_fu_ex6_load_data : out std_ulogic_vector(0 to 255); + + -- FU Store Data + fu_xu_ex2_store_data_val : in std_ulogic; + fu_xu_ex2_store_data : in std_ulogic_vector(0 to 255); + + -- Outputs to L2 + ac_an_req_pwr_token : out std_ulogic; + ac_an_req : out std_ulogic; + ac_an_req_ra : out std_ulogic_vector(64-real_data_add to 63); + ac_an_req_ttype : out std_ulogic_vector(0 to 5); + ac_an_req_thread : out std_ulogic_vector(0 to 2); + ac_an_req_wimg_w : out std_ulogic; + ac_an_req_wimg_i : out std_ulogic; + ac_an_req_wimg_m : out std_ulogic; + ac_an_req_wimg_g : out std_ulogic; + ac_an_req_user_defined : out std_ulogic_vector(0 to 3); + ac_an_req_spare_ctrl_a0 : out std_ulogic_vector(0 to 3); + ac_an_req_ld_core_tag : out std_ulogic_vector(0 to 4); + ac_an_req_ld_xfr_len : out std_ulogic_vector(0 to 2); + ac_an_st_byte_enbl : out std_ulogic_vector(0 to 15+(st_data_32B_mode*16)); + ac_an_st_data : out std_ulogic_vector(0 to 127+(st_data_32B_mode*128)); + ac_an_req_endian : out std_ulogic; + ac_an_st_data_pwr_token : out std_ulogic; + + -- TLB ops interface + xu_mm_rf1_val : out std_ulogic_vector(0 to 3); + xu_mm_rf1_is_tlbre : out std_ulogic; + xu_mm_rf1_is_tlbwe : out std_ulogic; + xu_mm_rf1_is_tlbsx : out std_ulogic; + xu_mm_rf1_is_tlbsrx : out std_ulogic; + xu_mm_rf1_is_tlbivax : out std_ulogic; + xu_mm_rf1_is_tlbilx : out std_ulogic; + xu_mm_rf1_is_erativax : out std_ulogic; + xu_mm_rf1_is_eratilx : out std_ulogic; + xu_mm_ex1_is_isync : out std_ulogic; + xu_mm_ex1_is_csync : out std_ulogic; + xu_mm_rf1_t : out std_ulogic_vector(0 to 2); + xu_mm_ex1_rs_is : out std_ulogic_vector(0 to 8); + xu_mm_ex2_eff_addr : out std_ulogic_vector(64-(2**regmode) to 63); + + -- IERAT ops interface + xu_iu_rf1_val : out std_ulogic_vector(0 to 3); + xu_iu_rf1_is_eratre : out std_ulogic; + xu_iu_rf1_is_eratwe : out std_ulogic; + xu_iu_rf1_is_eratsx : out std_ulogic; + xu_iu_rf1_is_eratilx : out std_ulogic; + xu_iu_ex1_is_isync : out std_ulogic; + xu_iu_ex1_is_csync : out std_ulogic; + xu_iu_rf1_ws : out std_ulogic_vector(0 to 1); + xu_iu_rf1_t : out std_ulogic_vector(0 to 2); + xu_iu_ex1_rs_is : out std_ulogic_vector(0 to 8); + xu_iu_ex1_ra_entry : out std_ulogic_vector(8 to 11); + xu_iu_ex1_rb : out std_ulogic_vector(64-(2**regmode) to 51); + -- TLB Write Data + xu_iu_ex4_rs_data : out std_ulogic_vector(64-(2**regmode) to 63); + -- TLB Read Data + iu_xu_ex4_tlb_data : in std_ulogic_vector(64-(2**regmode) to 63); + + mm_xu_illeg_instr : in std_ulogic_vector(0 to threads-1); + + -- ERAT/TLM Misses + mm_xu_tlb_miss : in std_ulogic_vector(0 to threads-1); + mm_xu_eratmiss_done : in std_ulogic_vector(0 to threads-1); + + -- ERAT/TLB Inval + mm_xu_hold_req : in std_ulogic_vector(0 to threads-1); + mm_xu_hold_done : in std_ulogic_vector(0 to threads-1); + xu_mm_hold_ack : out std_ulogic_vector(0 to threads-1); + + -- ERAT/TLB Invalid Accesses + mm_xu_pt_fault : in std_ulogic_vector(0 to threads-1); + mm_xu_tlb_inelig : in std_ulogic_vector(0 to threads-1); + mm_xu_lrat_miss : in std_ulogic_vector(0 to threads-1); + mm_xu_hv_priv : in std_ulogic_vector(0 to threads-1); + mm_xu_esr_pt : in std_ulogic_vector(0 to threads-1); + mm_xu_esr_data : in std_ulogic_vector(0 to threads-1); + mm_xu_esr_epid : in std_ulogic_vector(0 to threads-1); + mm_xu_esr_st : in std_ulogic_vector(0 to threads-1); + mm_xu_ex3_flush_req : in std_ulogic_vector(0 to threads-1); + xu_mm_rf1_is_tlbsxr : out std_ulogic; + + xu_mm_lmq_stq_empty : out std_ulogic; + mm_xu_quiesce : in std_ulogic_vector(0 to threads-1); + + -- D-ERAT Request interface + xu_mm_derat_req : out std_ulogic; + xu_mm_derat_epn : out std_ulogic_vector(62-eff_ifar to 51); + xu_mm_derat_thdid : out std_ulogic_vector(0 to 3); + xu_mm_derat_state : out std_ulogic_vector(0 to 3); + xu_mm_derat_ttype : out std_ulogic_vector(0 to 1); + xu_mm_derat_tid : out std_ulogic_vector(0 to 13); + xu_mm_derat_lpid : out std_ulogic_vector(0 to 7); + + -- Machine Check Interrupts + mm_xu_local_snoop_reject : in std_ulogic_vector(0 to threads-1); + mm_xu_lru_par_err : in std_ulogic_vector(0 to threads-1); + mm_xu_tlb_par_err : in std_ulogic_vector(0 to threads-1); + mm_xu_tlb_multihit_err : in std_ulogic_vector(0 to threads-1); + + -- D-ERAT Reload interface + mm_xu_derat_rel_val : in std_ulogic_vector(0 to 4); + mm_xu_derat_rel_data : in std_ulogic_vector(0 to 131); + + -- D-ERAT Snoop interface + mm_xu_derat_snoop_coming : in std_ulogic; + mm_xu_derat_snoop_val : in std_ulogic; + mm_xu_derat_snoop_attr : in std_ulogic_vector(0 to 25); + mm_xu_derat_snoop_vpn : in std_ulogic_vector(64-(2**REGMODE) to 51); + xu_mm_derat_snoop_ack : out std_ulogic; + + -- D-ERAT Control Register interface + mm_xu_derat_pid0 : in std_ulogic_vector(0 to 13); + mm_xu_derat_pid1 : in std_ulogic_vector(0 to 13); + mm_xu_derat_pid2 : in std_ulogic_vector(0 to 13); + mm_xu_derat_pid3 : in std_ulogic_vector(0 to 13); + mm_xu_derat_mmucr0_0 : in std_ulogic_vector(0 to 19); + mm_xu_derat_mmucr0_1 : in std_ulogic_vector(0 to 19); + mm_xu_derat_mmucr0_2 : in std_ulogic_vector(0 to 19); + mm_xu_derat_mmucr0_3 : in std_ulogic_vector(0 to 19); + xu_mm_derat_mmucr0 : out std_ulogic_vector(0 to 17); + xu_mm_derat_mmucr0_we : out std_ulogic_vector(0 to 3); + mm_xu_derat_mmucr1 : in std_ulogic_vector(0 to 9); + xu_mm_derat_mmucr1 : out std_ulogic_vector(0 to 4); + xu_mm_derat_mmucr1_we : out std_ulogic; + + -- SPR Bits + xu_mm_spr_epcr_dmiuh : out std_ulogic_vector(0 to threads-1); + xu_mm_spr_epcr_dgtmi : out std_ulogic_vector(0 to threads-1); + xu_iu_spr_ccr2_ifratsc : out std_ulogic_vector(0 to 8); + xu_iu_spr_ccr2_ifrat : out std_ulogic; + xu_bx_ccr2_en_ditc : out std_ulogic; + xu_iu_spr_xer0 : out std_ulogic_vector(57 to 63); + xu_iu_spr_xer1 : out std_ulogic_vector(57 to 63); + xu_iu_spr_xer2 : out std_ulogic_vector(57 to 63); + xu_iu_spr_xer3 : out std_ulogic_vector(57 to 63); + xu_iu_msr_gs : out std_ulogic_vector(0 to threads-1); + xu_iu_msr_hv : out std_ulogic_vector(0 to threads-1); + xu_iu_msr_pr : out std_ulogic_vector(0 to threads-1); + xu_iu_msr_is : out std_ulogic_vector(0 to threads-1); + xu_iu_msr_cm : out std_ulogic_vector(0 to threads-1); + xu_iu_hid_mmu_mode : out std_ulogic; + xu_iu_xucr0_rel : out std_ulogic; + xu_mm_msr_gs : out std_ulogic_vector(0 to threads-1); + xu_mm_msr_pr : out std_ulogic_vector(0 to threads-1); + xu_mm_msr_is : out std_ulogic_vector(0 to threads-1); + xu_mm_msr_ds : out std_ulogic_vector(0 to threads-1); + xu_mm_msr_cm : out std_ulogic_vector(0 to threads-1); + xu_mm_hid_mmu_mode : out std_ulogic; + xu_fu_msr_pr : out std_ulogic_vector(0 to threads-1); + xu_fu_msr_gs : out std_ulogic_vector(0 to threads-1); + xu_fu_msr_fp : out std_ulogic_vector(0 to threads-1); + xu_fu_msr_spv : out std_ulogic_vector(0 to threads-1); + xu_fu_ccr2_ap : out std_ulogic_vector(0 to threads-1); + xu_iu_xucr4_mmu_mchk : out std_ulogic; + xu_mm_xucr4_mmu_mchk : out std_ulogic; + + -- Slow SPR Bus + slowspr_val_out : out std_ulogic; + slowspr_rw_out : out std_ulogic; + slowspr_etid_out : out std_ulogic_vector(0 to 1); + slowspr_addr_out : out std_ulogic_vector(0 to 9); + slowspr_data_out : out std_ulogic_vector(64-(2**regmode) to 63); + slowspr_done_out : out std_ulogic; + slowspr_val_in : in std_ulogic; + slowspr_rw_in : in std_ulogic; + slowspr_etid_in : in std_ulogic_vector(0 to 1); + slowspr_addr_in : in std_ulogic_vector(0 to 9); + slowspr_data_in : in std_ulogic_vector(64-(2**regmode) to 63); + slowspr_done_in : in std_ulogic; + + xu_iu_spr_ccr2_en_dcr : out std_ulogic; + + -- Boxes Signals + xu_bx_ex1_mtdp_val : out std_ulogic; -- command from mtdp is valid + xu_bx_ex1_mfdp_val : out std_ulogic; -- command from mtdp is valid + xu_bx_ex1_ipc_thrd : out std_ulogic_vector(0 to 1); -- Thread ID + xu_bx_ex2_ipc_ba : out std_ulogic_vector(0 to 4); -- offset into the active 64B buffer + xu_bx_ex2_ipc_sz : out std_ulogic_vector(0 to 1); -- size of data (00=4B, 10=16B) + xu_bx_ex4_256st_data : out std_ulogic_vector(128 to 255); -- 16B of data to put into outbox buffer + bx_xu_ex4_mtdp_cr_status : in std_ulogic; -- status (pas/fail) of the mtdp (sets CR) + bx_xu_ex4_mfdp_cr_status : in std_ulogic; -- status (pas/fail) of the mfdp (sets CR) + bx_xu_ex5_dp_data : in std_ulogic_vector(0 to 127); -- 16B of data from the inbox buffer + bx_xu_quiesce : in std_ulogic_vector(0 to 3); -- inbox and outbox are empty + bx_lsu_ob_pwr_tok : in std_ulogic; + bx_lsu_ob_req_val : in std_ulogic; -- message buffer data is ready to send + bx_lsu_ob_ditc_val : in std_ulogic; -- send dtic command + bx_lsu_ob_thrd : in std_ulogic_vector(0 to 1); -- source thread + bx_lsu_ob_qw : in std_ulogic_vector(58 to 59); -- destination for the packet + bx_lsu_ob_dest : in std_ulogic_vector(0 to 14); -- destination for the packet + bx_lsu_ob_data : in std_ulogic_vector(0 to 127); -- 16B of data from the outbox + bx_lsu_ob_addr : in std_ulogic_vector(64-real_data_add to 57); -- address for boxes message + lsu_bx_cmd_avail : out std_ulogic; + lsu_bx_cmd_sent : out std_ulogic; + lsu_bx_cmd_stall : out std_ulogic; + + xu_iu_reld_core_tag :out std_ulogic_vector(0 to 4); + xu_iu_reld_core_tag_clone :out std_ulogic_vector(1 to 4); + xu_iu_reld_data :out std_ulogic_vector(0 to 127); + xu_iu_reld_data_coming_clone :out std_ulogic; + xu_iu_reld_data_vld :out std_ulogic; + xu_iu_reld_data_vld_clone :out std_ulogic; + xu_iu_reld_ditc_clone :out std_ulogic; + xu_iu_reld_ecc_err :out std_ulogic; + xu_iu_reld_ecc_err_ue :out std_ulogic; + xu_iu_reld_qw :out std_ulogic_vector(57 to 59); + + -- Pervasive Signals + + ---- FIR and Error Signals + xu_pc_err_mcsr_summary : out std_ulogic_vector(0 to threads-1); + xu_pc_err_local_snoop_reject : out std_ulogic; + xu_pc_err_tlb_lru_parity : out std_ulogic; + xu_pc_err_ext_mchk : out std_ulogic; + xu_pc_err_ierat_multihit : out std_ulogic; + xu_pc_err_derat_multihit : out std_ulogic; + xu_pc_err_tlb_multihit : out std_ulogic; + xu_pc_err_ierat_parity : out std_ulogic; + xu_pc_err_derat_parity : out std_ulogic; + xu_pc_err_tlb_parity : out std_ulogic; + xu_pc_err_mchk_disabled : out std_ulogic; + xu_pc_err_ditc_overrun : out std_ulogic; + xu_pc_err_dcache_parity : out std_ulogic; + xu_pc_err_dcachedir_parity : out std_ulogic; + xu_pc_err_dcachedir_multihit : out std_ulogic; + xu_pc_err_sprg_ecc : out std_ulogic_vector(0 to threads-1); + xu_pc_err_regfile_parity : out std_ulogic_vector(0 to threads-1); + xu_pc_err_llbust_attempt : out std_ulogic_vector(0 to threads-1); + xu_pc_err_llbust_failed : out std_ulogic_vector(0 to threads-1); + xu_pc_err_l2intrf_ecc : out std_ulogic; + xu_pc_err_l2intrf_ue : out std_ulogic; + xu_pc_err_attention_instr : out std_ulogic_vector(0 to threads-1); + xu_pc_err_nia_miscmpr : out std_ulogic_vector(0 to threads-1); + xu_pc_err_wdt_reset : out std_ulogic_vector(0 to threads-1); + xu_pc_err_debug_event : out std_ulogic_vector(0 to threads-1); + xu_pc_err_invld_reld : out std_ulogic; + xu_pc_err_l2credit_overrun : out std_ulogic; + + ---- Error Inject + pc_xu_inj_dcache_parity : in std_ulogic; + pc_xu_inj_dcachedir_parity : in std_ulogic; + pc_xu_inj_dcachedir_multihit : in std_ulogic; + pc_xu_inj_llbust_attempt : in std_ulogic_vector(0 to threads-1); + pc_xu_inj_llbust_failed : in std_ulogic_vector(0 to threads-1); + pc_xu_inj_wdt_reset : in std_ulogic_vector(0 to threads-1); + + ---- RAM Command/Data + pc_xu_ram_mode : in std_ulogic; + pc_xu_ram_thread : in std_ulogic_vector(0 to 1); + pc_xu_ram_execute : in std_ulogic; + pc_xu_ram_flush_thread : in std_ulogic; + xu_iu_ram_issue : out std_ulogic_vector(0 to threads-1); + xu_pc_ram_interrupt : out std_ulogic; + xu_pc_ram_done : out std_ulogic; + xu_pc_ram_data : out std_ulogic_vector(64-(2**regmode) to 63); + + ---- THRCTL Register + pc_xu_stop : in std_ulogic_vector(0 to 3); -- set by thrctl; pwr_mgmt; dbg event + pc_xu_step : in std_ulogic_vector(0 to 3); -- set by thrctl + pc_xu_dbg_action : in std_ulogic_vector(0 to 11); + pc_xu_force_ude : in std_ulogic_vector(0 to threads-1); + xu_pc_step_done : out std_ulogic_vector(0 to threads-1); + xu_pc_running : out std_ulogic_vector(0 to 3); -- also to pwr_mgmt + xu_pc_spr_ccr0_we : out std_ulogic_vector(0 to threads-1); + xu_pc_stop_dbg_event : out std_ulogic_vector(0 to threads-1); + xu_pc_spr_ccr0_pme : out std_ulogic_vector(0 to 1); + pc_xu_msrovride_enab : in std_ulogic; + pc_xu_msrovride_pr : in std_ulogic; + pc_xu_msrovride_gs : in std_ulogic; + pc_xu_msrovride_de : in std_ulogic; + + ---- PCCR0 + pc_xu_extirpts_dis_on_stop : in std_ulogic; + pc_xu_timebase_dis_on_stop : in std_ulogic; + pc_xu_decrem_dis_on_stop : in std_ulogic; + + ---- Debug Ramp Bus + pc_xu_trace_bus_enable : in std_ulogic; + pc_xu_debug_mux1_ctrls : in std_ulogic_vector(0 to 15); + pc_xu_debug_mux2_ctrls : in std_ulogic_vector(0 to 15); + pc_xu_debug_mux3_ctrls : in std_ulogic_vector(0 to 15); + pc_xu_debug_mux4_ctrls : in std_ulogic_vector(0 to 15); + trigger_data_in : in std_ulogic_vector(0 to 11); + debug_data_in : in std_ulogic_vector(0 to 87); + trigger_data_out : out std_ulogic_vector(0 to 11); + debug_data_out : out std_ulogic_vector(0 to 87); + + ---- Performance Event Ramp Bus + pc_xu_event_bus_enable : in std_ulogic; + xu_pc_lsu_event_data : out std_ulogic_vector(0 to 7); + xu_pc_event_data : out std_ulogic_vector(0 to 7); + pc_xu_event_mux_ctrls : in std_ulogic_vector(0 to 47); + pc_xu_lsu_event_mux_ctrls : in std_ulogic_vector(0 to 47); + pc_xu_cache_par_err_event : in std_ulogic; + + ---- Core Event Select Register + pc_xu_instr_trace_mode : in std_ulogic; + pc_xu_instr_trace_tid : in std_ulogic_vector(0 to 1); + pc_xu_event_count_mode : in std_ulogic_vector(0 to 2); + + ---- POR and Sreset + ac_tc_reset_1_request : out std_ulogic; + ac_tc_reset_2_request : out std_ulogic; + ac_tc_reset_3_request : out std_ulogic; + ac_tc_reset_wd_request : out std_ulogic; + + pc_xu_ccflush_dc : in std_ulogic; + an_ac_scan_diag_dc : in std_ulogic; + an_ac_scan_dis_dc_b : in std_ulogic; + an_ac_atpg_en_dc : in std_ulogic; + + ----Thold inputs + pc_xu_gptr_sl_thold_3 : in std_ulogic; + pc_xu_time_sl_thold_3 : in std_ulogic; + pc_xu_repr_sl_thold_3 : in std_ulogic; + pc_xu_abst_sl_thold_3 : in std_ulogic; + pc_xu_abst_slp_sl_thold_3 : in std_ulogic; + pc_xu_regf_sl_thold_3 : in std_ulogic; + pc_xu_regf_slp_sl_thold_3 : in std_ulogic; + pc_xu_func_sl_thold_3 : in std_ulogic_vector(0 to 4); + pc_xu_func_slp_sl_thold_3 : in std_ulogic_vector(0 to 4); + pc_xu_cfg_sl_thold_3 : in std_ulogic; + pc_xu_cfg_slp_sl_thold_3 : in std_ulogic; + pc_xu_func_nsl_thold_3 : in std_ulogic; + pc_xu_func_slp_nsl_thold_3 : in std_ulogic; + pc_xu_ary_nsl_thold_3 : in std_ulogic; + pc_xu_ary_slp_nsl_thold_3 : in std_ulogic; + pc_xu_sg_3 : in std_ulogic_vector(0 to 4); + pc_xu_fce_3 : in std_ulogic_vector(0 to 1); + pc_xu_bolt_sl_thold_3 : in std_ulogic; + + ---- Scan inputs + gptr_scan_in : in std_ulogic; + time_scan_in : in std_ulogic; + repr_scan_in : in std_ulogic; + abst_scan_in : in std_ulogic_vector(0 to 2); + func_scan_in : in std_ulogic_vector(31 to 58); + bcfg_scan_in : in std_ulogic; + ccfg_scan_in : in std_ulogic; + dcfg_scan_in : in std_ulogic; + regf_scan_in : in std_ulogic_vector(0 to 6); + + ---- Scan outputs + gptr_scan_out : out std_ulogic; + time_scan_out : out std_ulogic; + repr_scan_out : out std_ulogic; + abst_scan_out : out std_ulogic_vector(0 to 2); + func_scan_out : out std_ulogic_vector(31 to 58); + bcfg_scan_out : out std_ulogic; + ccfg_scan_out : out std_ulogic; + dcfg_scan_out : out std_ulogic; + regf_scan_out : out std_ulogic_vector(0 to 6); + + pc_xu_init_reset : in std_ulogic; + pc_xu_reset_wd_complete : in std_ulogic; + pc_xu_reset_1_complete : in std_ulogic; + pc_xu_reset_2_complete : in std_ulogic; + pc_xu_reset_3_complete : in std_ulogic; + + ---- Error Signals + xu_pc_err_sprg_ue : out std_ulogic_vector(0 to 3); + xu_pc_err_regfile_ue : out std_ulogic_vector(0 to 3); + + iu_xu_ierat_ex2_flush_req : in std_ulogic_vector(0 to threads-1); + iu_xu_ierat_ex3_par_err : in std_ulogic_vector(0 to threads-1); + iu_xu_ierat_ex4_par_err : in std_ulogic_vector(0 to threads-1); + pc_xu_inj_sprg_ecc : in std_ulogic_vector(0 to 3); + pc_xu_inj_regfile_parity : in std_ulogic_vector(0 to 3); + fu_xu_ex3_regfile_err_det : in std_ulogic_vector(0 to threads-1); + xu_fu_regfile_seq_beg : out std_ulogic; + fu_xu_regfile_seq_end : in std_ulogic; + + ---- Clock,Power + nclk : in clk_logic; + vdd : inout power_logic; + gnd : inout power_logic; + vcs : inout power_logic; + + --- ABIST engine interface + an_ac_lbist_ary_wrt_thru_dc : in std_ulogic; + xu_fu_lbist_ary_wrt_thru_dc : out std_ulogic; + pc_xu_abist_dcomp_g6t_2r : in std_ulogic_vector(0 to 3); + pc_xu_abist_di_g6t_2r : in std_ulogic_vector(0 to 3); + pc_xu_abist_g6t_bw : in std_ulogic_vector(0 to 1); + pc_xu_abist_g6t_r_wb : in std_ulogic; + pc_xu_abist_g8t1p_renb_0 : in std_ulogic; + pc_xu_abist_g8t_bw_0 : in std_ulogic; + pc_xu_abist_g8t_bw_1 : in std_ulogic; + pc_xu_abist_g8t_dcomp : in std_ulogic_vector(0 to 3); + pc_xu_abist_g8t_wenb : in std_ulogic; + pc_xu_abist_wl32_comp_ena : in std_ulogic; + pc_xu_abist_wl512_comp_ena : in std_ulogic; + an_ac_lbist_en_dc : in std_ulogic; + xu_fu_lbist_en_dc : out std_ulogic; + pc_xu_abist_raddr_0 : in std_ulogic_vector(0 to 9); + pc_xu_abist_raddr_1 : in std_ulogic_vector(0 to 9); + pc_xu_abist_grf_renb_0 : in std_ulogic; + pc_xu_abist_grf_renb_1 : in std_ulogic; + pc_xu_abist_ena_dc : in std_ulogic; + pc_xu_abist_waddr_0 : in std_ulogic_vector(0 to 9); + pc_xu_abist_waddr_1 : in std_ulogic_vector(0 to 9); + pc_xu_abist_grf_wenb_0 : in std_ulogic; + pc_xu_abist_grf_wenb_1 : in std_ulogic; + pc_xu_abist_di_0 : in std_ulogic_vector(0 to 3); + pc_xu_abist_di_1 : in std_ulogic_vector(0 to 3); + pc_xu_abist_wl144_comp_ena : in std_ulogic; + pc_xu_abist_raw_dc_b : in std_ulogic; + + pc_xu_bo_enable_3 : in std_ulogic; + pc_xu_bo_unload : in std_ulogic; + pc_xu_bo_load : in std_ulogic; + pc_xu_bo_repair : in std_ulogic; + pc_xu_bo_reset : in std_ulogic; + pc_xu_bo_shdata : in std_ulogic; + pc_xu_bo_select : in std_ulogic_vector(0 to 8); + xu_pc_bo_fail : out std_ulogic_vector(0 to 8); + xu_pc_bo_diagout : out std_ulogic_vector(0 to 8) + + ); +-- synopsys translate_off +-- synopsys translate_on +end xuq; + +architecture xuq of xuq is + +constant tidn : std_ulogic_vector(0 to 63) := (others=>'0'); +constant regsize : integer := 2**regmode; + +-- Signals +signal xu_lsu_ex1_store_data :std_ulogic_vector(64-(2**regmode) to 63); +signal xu_lsu_ex1_eff_addr :std_ulogic_vector(64-(dc_size-3) to 63); +signal lsu_xu_rel_ta_gpr :std_ulogic_vector(0 to 7); +signal lsu_xu_rot_ex6_data_b :std_ulogic_vector(64-(2**regmode) to 63); +signal lsu_xu_rel_wren :std_ulogic; +signal lsu_xu_rot_rel_data :std_ulogic_vector(64-(2**regmode) to 63); +signal is2_flush :std_ulogic_vector(0 to threads-1); +signal rf0_flush :std_ulogic_vector(0 to threads-1); +signal rf1_flush :std_ulogic_vector(0 to threads-1); +signal ex1_flush :std_ulogic_vector(0 to threads-1); +signal ex2_flush :std_ulogic_vector(0 to threads-1); +signal ex3_flush :std_ulogic_vector(0 to threads-1); +signal ex4_flush :std_ulogic_vector(0 to threads-1); +signal ex5_flush :std_ulogic_vector(0 to threads-1); +signal xu_lsu_ex4_flush_local :std_ulogic_vector(0 to threads-1); +signal xu_iu_iu0_flush_ifar :std_ulogic_vector(0 to eff_ifar*threads-1); +signal xu_iu_uc_flush_ifar :std_ulogic_vector(0 to uc_ifar*threads-1); +signal xu_lsu_rf0_derat_val :std_ulogic_vector(0 to threads-1); +signal xu_lsu_rf1_data_act :std_ulogic; +signal xu_lsu_rf0_derat_is_extload :std_ulogic; +signal xu_lsu_rf0_derat_is_extstore :std_ulogic; +signal xu_rf1_val :std_ulogic_vector(0 to 3); +signal xu_rf1_is_eratilx :std_ulogic; +signal xu_ex1_is_isync :std_ulogic; +signal xu_ex1_is_csync :std_ulogic; +signal xu_rf1_ws :std_ulogic_vector(0 to 1); +signal xu_rf1_t :std_ulogic_vector(0 to 2); +signal xu_ex1_rs_is :std_ulogic_vector(0 to 8); +signal xu_ex1_ra_entry :std_ulogic_vector(8 to 11); +signal xu_ex4_rs_data :std_ulogic_vector(64-(2**regmode) to 63); +signal xu_msr_gs :std_ulogic_vector(0 to threads-1); +signal xu_msr_pr :std_ulogic_vector(0 to threads-1); +signal xu_msr_is :std_ulogic_vector(0 to threads-1); +signal xu_msr_ds :std_ulogic_vector(0 to threads-1); +signal cpl_msr_gs :std_ulogic_vector(0 to threads-1); +signal cpl_msr_pr :std_ulogic_vector(0 to threads-1); +signal cpl_msr_fp :std_ulogic_vector(0 to threads-1); +signal cpl_msr_spv :std_ulogic_vector(0 to threads-1); +signal cpl_ccr2_ap :std_ulogic_vector(0 to threads-1); +signal xu_msr_cm :std_ulogic_vector(0 to threads-1); +signal xu_lsu_hid_mmu_mode :std_ulogic; +signal xu_iu_spr_xer :std_ulogic_vector(0 to 7*threads-1); +signal xu_lsu_rf1_axu_ldst_falign :std_ulogic; +signal fu_xu_ex1_ifar :std_ulogic_vector(0 to eff_ifar*threads-1); +signal xu_lsu_ex1_rotsel_ovrd :std_ulogic_vector(0 to 4); +signal xu_lsu_ici :std_ulogic; +signal lsu_xu_ldq_barr_done :std_ulogic_vector(0 to threads-1); +signal lsu_xu_barr_done :std_ulogic_vector(0 to threads-1); +signal lsu_xu_rel_dvc_thrd_id :std_ulogic_vector(0 to 3); +signal lsu_xu_ex2_dvc1_st_cmp :std_ulogic_vector(0 to ((2**regmode)/8)-1); +signal lsu_xu_ex8_dvc1_ld_cmp :std_ulogic_vector(0 to ((2**regmode)/8)-1); +signal lsu_xu_rel_dvc1_en :std_ulogic; +signal lsu_xu_rel_dvc1_cmp :std_ulogic_vector(0 to ((2**regmode)/8)-1); +signal lsu_xu_ex2_dvc2_st_cmp :std_ulogic_vector(0 to ((2**regmode)/8)-1); +signal lsu_xu_ex8_dvc2_ld_cmp :std_ulogic_vector(0 to ((2**regmode)/8)-1); +signal lsu_xu_rel_dvc2_en :std_ulogic; +signal lsu_xu_rel_dvc2_cmp :std_ulogic_vector(0 to ((2**regmode)/8)-1); +signal xu_ex2_eff_addr :std_ulogic_vector(64-(2**regmode) to 63); +signal spr_debug_mux_ctrls :std_ulogic_vector(0 to 15); +signal cpl_debug_mux_ctrls :std_ulogic_vector(0 to 15); +signal fxu_debug_mux_ctrls :std_ulogic_vector(0 to 15); +signal lsu_debug_mux_ctrls :std_ulogic_vector(0 to 15); +signal lsudat_debug_mux_ctrls :std_ulogic_vector(0 to 1); +signal lsu_xu_data_debug0 :std_ulogic_vector(0 to 87); +signal lsu_xu_data_debug1 :std_ulogic_vector(0 to 87); +signal lsu_xu_data_debug2 :std_ulogic_vector(0 to 87); +signal sg_2 :std_ulogic_vector(0 to 3); +signal func_sl_thold_2 :std_ulogic_vector(0 to 3); +signal func_nsl_thold_2 :std_ulogic; +signal func_slp_sl_thold_2 :std_ulogic_vector(0 to 1); +signal ary_nsl_thold_2 :std_ulogic; +signal time_sl_thold_2 :std_ulogic; +signal abst_sl_thold_2 :std_ulogic; +signal repr_sl_thold_2 :std_ulogic; +signal gptr_sl_thold_2 :std_ulogic; +signal cfg_sl_thold_2 :std_ulogic; +signal cfg_slp_sl_thold_2 :std_ulogic; +signal regf_slp_sl_thold_2 :std_ulogic; +signal fce_2 :std_ulogic_vector(0 to 1); +signal clkoff_dc_b :std_ulogic; +signal d_mode_dc :std_ulogic; +signal delay_lclkr_dc :std_ulogic_vector(0 to 4); +signal mpw1_dc_b :std_ulogic_vector(0 to 4); +signal mpw2_dc_b :std_ulogic; +signal g6t_clkoff_dc_b :std_ulogic; +signal g6t_d_mode_dc :std_ulogic; +signal g6t_delay_lclkr_dc :std_ulogic_vector(0 to 4); +signal g6t_mpw1_dc_b :std_ulogic_vector(0 to 4); +signal g6t_mpw2_dc_b :std_ulogic; + +signal fxa_fxb_rf0_val :std_ulogic_vector(0 to threads-1); +signal fxa_fxb_rf0_issued :std_ulogic_vector(0 to threads-1); +signal fxa_fxb_rf0_ucode_val :std_ulogic_vector(0 to threads-1); +signal fxa_fxb_rf0_act :std_ulogic; +signal fxa_fxb_ex1_hold_ctr_flush :std_ulogic; +signal fxa_fxb_rf0_instr :std_ulogic_vector(0 to 31); +signal fxa_fxb_rf0_tid :std_ulogic_vector(0 to threads-1); +signal fxa_fxb_rf0_ta_vld :std_ulogic; +signal fxa_fxb_rf0_ta :std_ulogic_vector(0 to 7); +signal fxa_fxb_rf0_error :std_ulogic_vector(0 to 2); +signal fxa_fxb_rf0_match :std_ulogic; +signal fxa_fxb_rf0_is_ucode :std_ulogic; +signal fxa_fxb_rf0_gshare :std_ulogic_vector(0 to 3); +signal fxa_fxb_rf0_ifar :std_ulogic_vector(62-eff_ifar to 61); +signal fxa_fxb_rf0_s1_vld :std_ulogic; +signal fxa_fxb_rf0_s1 :std_ulogic_vector(0 to 7); +signal fxa_fxb_rf0_s2_vld :std_ulogic; +signal fxa_fxb_rf0_s2 :std_ulogic_vector(0 to 7); +signal fxa_fxb_rf0_s3_vld :std_ulogic; +signal fxa_fxb_rf0_s3 :std_ulogic_vector(0 to 7); +signal fxa_fxb_rf0_axu_instr_type :std_ulogic_vector(0 to 2); +signal fxa_fxb_rf0_axu_ld_or_st :std_ulogic; +signal fxa_fxb_rf0_axu_store :std_ulogic; +signal fxa_fxb_rf0_axu_ldst_forcealign :std_ulogic; +signal fxa_fxb_rf0_axu_ldst_forceexcept :std_ulogic; +signal fxa_fxb_rf0_axu_ldst_indexed :std_ulogic; +signal fxa_fxb_rf0_axu_ldst_tag :std_ulogic_vector(0 to 8); +signal fxa_fxb_rf0_axu_mftgpr :std_ulogic; +signal fxa_fxb_rf0_axu_mffgpr :std_ulogic; +signal fxa_fxb_rf0_axu_movedp :std_ulogic; +signal fxa_fxb_rf0_axu_ldst_size :std_ulogic_vector(0 to 5); +signal fxa_fxb_rf0_axu_ldst_update :std_ulogic; +signal fxa_fxb_rf0_pred_update :std_ulogic; +signal fxa_fxb_rf0_pred_taken_cnt :std_ulogic_vector(0 to 1); +signal fxa_fxb_rf0_mc_dep_chk_val :std_ulogic_vector(0 to threads-1); +signal fxa_fxb_rf1_mul_val :std_ulogic; +signal fxa_fxb_rf1_div_val :std_ulogic; +signal fxa_fxb_rf1_div_ctr :std_ulogic_vector(0 to 7); +signal fxa_fxb_rf0_xu_epid_instr :std_ulogic; +signal fxa_fxb_rf0_axu_is_extload :std_ulogic; +signal fxa_fxb_rf0_axu_is_extstore :std_ulogic; +signal fxa_fxb_rf0_is_mfocrf :std_ulogic; +signal fxa_fxb_rf0_3src_instr :std_ulogic; +signal fxa_fxb_rf0_gpr0_zero :std_ulogic; +signal fxa_fxb_rf0_use_imm :std_ulogic; +signal fxa_fxb_rf1_muldiv_coll :std_ulogic; +signal fxa_cpl_ex2_div_coll :std_ulogic_vector(0 to threads-1); +signal fxb_fxa_ex7_we0 :std_ulogic; +signal fxb_fxa_ex7_wa0 :std_ulogic_vector(0 to 7); +signal fxb_fxa_ex7_wd0 :std_ulogic_vector(64-regsize to 63); +signal fxa_fxb_rf1_do0 :std_ulogic_vector(64-regsize to 63); +signal fxa_fxb_rf1_do1 :std_ulogic_vector(64-regsize to 63); +signal fxa_fxb_rf1_do2 :std_ulogic_vector(64-regsize to 63); +signal fxb_fxa_ex6_clear_barrier :std_ulogic_vector(0 to threads-1); +signal dec_cpl_ex3_mc_dep_chk_val :std_ulogic_vector(0 to threads-1); +signal spr_ccr2_notlb :std_ulogic; +signal fxa_fxb_rf0_spr_tid :std_ulogic_vector(0 to threads-1); +signal fxa_fxb_rf0_cpl_tid :std_ulogic_vector(0 to threads-1); +signal fxa_fxb_rf0_cpl_act :std_ulogic; +signal gpr_cpl_ex3_regfile_err_det :std_ulogic; +signal cpl_gpr_regfile_seq_beg :std_ulogic; +signal gpr_cpl_regfile_seq_end :std_ulogic; +signal fxa_cpl_debug :std_ulogic_vector(0 to 272); +signal cpl_fxa_ex5_set_barr :std_ulogic_vector(0 to threads-1); +signal fxa_iu_set_barr_tid :std_ulogic_vector(0 to threads-1); +signal cpl_iu_set_barr_tid :std_ulogic_vector(0 to threads-1); +signal spr_xucr4_div_barr_thres :std_ulogic_vector(0 to 7); +signal ex4_256st_data :std_ulogic_vector(0 to 255); +signal ex6_ld_par_err :std_ulogic; +signal lsu_xu_ex6_datc_par_err :std_ulogic; +signal ex1_optype1 :std_ulogic; +signal ex1_optype2 :std_ulogic; +signal ex1_optype4 :std_ulogic; +signal ex1_optype8 :std_ulogic; +signal ex1_optype16 :std_ulogic; +signal ex1_optype32 :std_ulogic; +signal ex1_saxu_instr :std_ulogic; +signal ex1_sdp_instr :std_ulogic; +signal ex1_stgpr_instr :std_ulogic; +signal ex1_store_instr :std_ulogic; +signal ex1_axu_op_val :std_ulogic; +signal ex3_algebraic :std_ulogic; +signal ex3_data_swap :std_ulogic; +signal ex3_thrd_id :std_ulogic_vector(0 to 3); +signal rel_upd_dcarr_val :std_ulogic; +signal dcarr_up_way_addr :std_ulogic_vector(0 to 2); +signal ex4_load_op_hit :std_ulogic; +signal ex4_store_hit :std_ulogic; +signal ex4_axu_op_val :std_ulogic; +signal spr_dvc1_act :std_ulogic; +signal spr_dvc2_act :std_ulogic; +signal spr_dvc1_dbg :std_ulogic_vector(64-(2**regmode) to 63); +signal spr_dvc2_dbg :std_ulogic_vector(64-(2**regmode) to 63); +signal ldq_rel_data_val_early :std_ulogic; +signal ldq_rel_op_size :std_ulogic_vector(0 to 5); +signal ldq_rel_addr :std_ulogic_vector(64-(dc_size-3) to 58); +signal ldq_rel_data_val :std_ulogic; +signal ldq_rel_rot_sel :std_ulogic_vector(0 to 4); +signal ldq_rel_axu_val :std_ulogic; +signal ldq_rel_ci :std_ulogic; +signal ldq_rel_thrd_id :std_ulogic_vector(0 to 3); +signal ldq_rel_le_mode :std_ulogic; +signal ldq_rel_algebraic :std_ulogic; +signal ldq_rel_256_data :std_ulogic_vector(0 to 255); +signal ldq_rel_dvc1_en :std_ulogic; +signal ldq_rel_dvc2_en :std_ulogic; +signal ldq_rel_beat_crit_qw :std_ulogic; +signal ldq_rel_beat_crit_qw_block :std_ulogic; +signal dec_spr_rf0_instr :std_ulogic_vector(0 to 31); +signal ctlspr_time_scan_in :std_ulogic; +signal ctlspr_time_scan_out :std_ulogic; +signal ctlspr_repr_scan_in :std_ulogic; +signal ctlspr_repr_scan_out :std_ulogic; +signal ctlspr_gptr_scan_in :std_ulogic; +signal ctlspr_gptr_scan_out :std_ulogic; +signal fxadat_time_scan_in :std_ulogic; +signal fxadat_time_scan_out :std_ulogic; +signal fxadat_repr_scan_in :std_ulogic; +signal fxadat_repr_scan_out :std_ulogic; +signal fxadat_gptr_scan_in :std_ulogic; +signal fxadat_gptr_scan_out :std_ulogic; +signal xu_lsu_spr_xucr0_dcdis :std_ulogic; +signal spr_xucr0_clkg_ctl_b0 :std_ulogic; +signal fxa_perf_muldiv_in_use :std_ulogic; +signal bolt_sl_thold_2 :std_ulogic; +signal bo_enable_2 :std_ulogic; +signal abst_scan_2 :std_ulogic; +signal xu_w_rf1_flush :std_ulogic_vector(0 to threads-1); +signal xu_w_ex1_flush :std_ulogic_vector(0 to threads-1); +signal xu_w_ex2_flush :std_ulogic_vector(0 to threads-1); +signal xu_w_ex3_flush :std_ulogic_vector(0 to threads-1); +signal xu_w_ex4_flush :std_ulogic_vector(0 to threads-1); +signal xu_w_ex5_flush :std_ulogic_vector(0 to threads-1); +signal xu_iu_flush :std_ulogic_vector(0 to 3); +signal spr_xucr4_mmu_mchk :std_ulogic; + +begin + + +-- Misc. Signals +fu_xu_ex1_ifar <= fu_xu_ex1_ifar0 & fu_xu_ex1_ifar1 & fu_xu_ex1_ifar2 & fu_xu_ex1_ifar3; +xu_iu_ici <= xu_lsu_ici; + +-- TLB and ERAT ops interfaces +xu_mm_rf1_val <= xu_rf1_val; +xu_mm_rf1_is_eratilx <= xu_rf1_is_eratilx; +xu_mm_ex1_is_isync <= xu_ex1_is_isync; +xu_mm_ex1_is_csync <= xu_ex1_is_csync; +xu_mm_rf1_t <= xu_rf1_t; +xu_mm_ex1_rs_is <= xu_ex1_rs_is; +xu_mm_ex2_eff_addr <= xu_ex2_eff_addr; + +xu_iu_rf1_is_eratilx <= xu_rf1_is_eratilx; +xu_iu_ex1_is_isync <= xu_ex1_is_isync; +xu_iu_ex1_is_csync <= xu_ex1_is_csync; +xu_iu_rf1_ws <= xu_rf1_ws; +xu_iu_rf1_t <= xu_rf1_t; +xu_iu_ex1_rs_is <= xu_ex1_rs_is; +xu_iu_ex1_ra_entry <= xu_ex1_ra_entry(8 to 11); +xu_iu_ex4_rs_data <= xu_ex4_rs_data; + +-- SPR Bits +xu_lsu_hid_mmu_mode <= spr_ccr2_notlb; +xu_iu_msr_gs <= xu_msr_gs; +xu_iu_msr_hv <= xu_msr_gs; +xu_iu_msr_pr <= xu_msr_pr; +xu_iu_msr_is <= xu_msr_is; +xu_iu_msr_cm <= xu_msr_cm; +xu_iu_hid_mmu_mode <= spr_ccr2_notlb; +xu_mm_msr_gs <= xu_msr_gs; +xu_mm_msr_pr <= xu_msr_pr; +xu_mm_msr_is <= xu_msr_is; +xu_mm_msr_ds <= xu_msr_ds; +xu_mm_msr_cm <= xu_msr_cm; +xu_mm_hid_mmu_mode <= spr_ccr2_notlb; +-- These latched copies in CPL are closer to the FU +xu_fu_msr_gs <= cpl_msr_gs; +xu_fu_msr_pr <= cpl_msr_pr; +xu_fu_msr_fp <= cpl_msr_fp; +xu_fu_msr_spv <= cpl_msr_spv; +xu_fu_ccr2_ap <= cpl_ccr2_ap; + +xu_iu_xucr4_mmu_mchk <= spr_xucr4_mmu_mchk; +xu_mm_xucr4_mmu_mchk <= spr_xucr4_mmu_mchk; + +-- Flushes +xu_n_is2_flush <= is2_flush; +xu_n_rf0_flush <= rf0_flush; +xu_n_rf1_flush <= rf1_flush; +xu_n_ex1_flush <= ex1_flush; +xu_n_ex2_flush <= ex2_flush; +xu_n_ex3_flush <= ex3_flush; +xu_n_ex4_flush <= ex4_flush; +xu_n_ex5_flush <= ex5_flush; + +xu_wu_rf1_flush <= xu_w_rf1_flush; +xu_wu_ex1_flush <= xu_w_ex1_flush; +xu_wu_ex2_flush <= xu_w_ex2_flush; +xu_wu_ex3_flush <= xu_w_ex3_flush; +xu_wu_ex4_flush <= xu_w_ex4_flush; +xu_wu_ex5_flush <= xu_w_ex5_flush; + +xu_wl_rf1_flush <= xu_w_rf1_flush; +xu_wl_ex1_flush <= xu_w_ex1_flush; +xu_wl_ex2_flush <= xu_w_ex2_flush; +xu_wl_ex3_flush <= xu_w_ex3_flush; +xu_wl_ex4_flush <= xu_w_ex4_flush; +xu_wl_ex5_flush <= xu_w_ex5_flush; + +xu_iu_u_flush <= xu_iu_flush; +xu_iu_l_flush <= xu_iu_flush; + +xu_iu_iu0_flush_ifar0 <= xu_iu_iu0_flush_ifar(0 to 1*eff_ifar-1); +xu_iu_iu0_flush_ifar1 <= xu_iu_iu0_flush_ifar(1*eff_ifar to 2*eff_ifar-1); +xu_iu_iu0_flush_ifar2 <= xu_iu_iu0_flush_ifar(2*eff_ifar to 3*eff_ifar-1); +xu_iu_iu0_flush_ifar3 <= xu_iu_iu0_flush_ifar(3*eff_ifar to 4*eff_ifar-1); +xu_iu_uc_flush_ifar0 <= xu_iu_uc_flush_ifar(0 to 1*uc_ifar-1); +xu_iu_uc_flush_ifar1 <= xu_iu_uc_flush_ifar(1*uc_ifar to 2*uc_ifar-1); +xu_iu_uc_flush_ifar2 <= xu_iu_uc_flush_ifar(2*uc_ifar to 3*uc_ifar-1); +xu_iu_uc_flush_ifar3 <= xu_iu_uc_flush_ifar(3*uc_ifar to 4*uc_ifar-1); +xu_iu_spr_xer0 <= xu_iu_spr_xer(0 to 6); +xu_iu_spr_xer1 <= xu_iu_spr_xer(7 to 13); +xu_iu_spr_xer2 <= xu_iu_spr_xer(14 to 20); +xu_iu_spr_xer3 <= xu_iu_spr_xer(21 to 27); + +xu_iu_set_barr_tid <= cpl_iu_set_barr_tid or fxa_iu_set_barr_tid; + +xu_iu_reld_core_tag <= an_ac_reld_core_tag(0 to 4); +xu_iu_reld_data <= an_ac_reld_data(0 to 127); +xu_iu_reld_data_vld <= an_ac_reld_data_vld; +xu_iu_reld_ecc_err <= an_ac_reld_ecc_err; +xu_iu_reld_ecc_err_ue <= an_ac_reld_ecc_err_ue; +xu_iu_reld_qw <= an_ac_reld_qw(57 to 59); + + +-- Passthru to FU +xu_fu_lbist_ary_wrt_thru_dc <= an_ac_lbist_ary_wrt_thru_dc; +xu_fu_lbist_en_dc <= an_ac_lbist_en_dc; + +-- Debug Connections +fxu_debug_mux_ctrls <= pc_xu_debug_mux1_ctrls; +cpl_debug_mux_ctrls <= pc_xu_debug_mux2_ctrls; +lsu_debug_mux_ctrls <= pc_xu_debug_mux3_ctrls; +lsudat_debug_mux_ctrls <= pc_xu_debug_mux4_ctrls(2 to 3); +spr_debug_mux_ctrls <= pc_xu_debug_mux4_ctrls; + + + + + +-- ########################################################################################## +-- CPL/FXUB/CMD +-- ########################################################################################## + +ctlspr : entity work.xuq_ctrl_spr(xuq_ctrl_spr) +generic map( + expand_type => expand_type, + threads => threads, + eff_ifar => eff_ifar, + uc_ifar => uc_ifar, + regsize => regsize, + hvmode => hvmode, + regmode => regmode, + dc_size => dc_size, + cl_size => cl_size, + real_data_add => real_data_add, + a2mode => a2mode, + lmq_entries => lmq_entries, + l_endian_m => l_endian_m, + load_credits => load_credits, + store_credits => store_credits, + st_data_32B_mode => st_data_32B_mode, + spr_xucr0_init_mod => spr_xucr0_init_mod, + bcfg_epn_0to15 => bcfg_epn_0to15, + bcfg_epn_16to31 => bcfg_epn_16to31, + bcfg_epn_32to47 => bcfg_epn_32to47, + bcfg_epn_48to51 => bcfg_epn_48to51, + bcfg_rpn_22to31 => bcfg_rpn_22to31, + bcfg_rpn_32to47 => bcfg_rpn_32to47, + bcfg_rpn_48to51 => bcfg_rpn_48to51) +port map( + + --------------------------------------------------------------------- + -- Pervasive + --------------------------------------------------------------------- + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b, + an_ac_lbist_en_dc => an_ac_lbist_en_dc, + pc_xu_abist_raddr_0 => pc_xu_abist_raddr_0(4 to 9), + pc_xu_abist_ena_dc => pc_xu_abist_ena_dc, + pc_xu_abist_waddr_0 => pc_xu_abist_waddr_0(4 to 9), + pc_xu_abist_di_0 => pc_xu_abist_di_0, + pc_xu_abist_raw_dc_b => pc_xu_abist_raw_dc_b, + pc_xu_ccflush_dc => pc_xu_ccflush_dc, + clkoff_dc_b => clkoff_dc_b, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc, + mpw1_dc_b => mpw1_dc_b, + mpw2_dc_b => mpw2_dc_b, + g6t_clkoff_dc_b => g6t_clkoff_dc_b, + g6t_d_mode_dc => g6t_d_mode_dc, + g6t_delay_lclkr_dc => g6t_delay_lclkr_dc, + g6t_mpw1_dc_b => g6t_mpw1_dc_b, + g6t_mpw2_dc_b => g6t_mpw2_dc_b, + pc_xu_sg_3 => pc_xu_sg_3, + pc_xu_func_sl_thold_3 => pc_xu_func_sl_thold_3, + pc_xu_func_slp_sl_thold_3 => pc_xu_func_slp_sl_thold_3, + pc_xu_func_nsl_thold_3 => pc_xu_func_nsl_thold_3, + pc_xu_func_slp_nsl_thold_3 => pc_xu_func_slp_nsl_thold_3, + pc_xu_gptr_sl_thold_3 => pc_xu_gptr_sl_thold_3, + pc_xu_abst_sl_thold_3 => pc_xu_abst_sl_thold_3, + pc_xu_abst_slp_sl_thold_3 => pc_xu_abst_slp_sl_thold_3, + pc_xu_regf_sl_thold_3 => pc_xu_regf_sl_thold_3, + pc_xu_regf_slp_sl_thold_3 => pc_xu_regf_slp_sl_thold_3, + pc_xu_time_sl_thold_3 => pc_xu_time_sl_thold_3, + pc_xu_cfg_sl_thold_3 => pc_xu_cfg_sl_thold_3, + pc_xu_cfg_slp_sl_thold_3 => pc_xu_cfg_slp_sl_thold_3, + pc_xu_ary_nsl_thold_3 => pc_xu_ary_nsl_thold_3, + pc_xu_ary_slp_nsl_thold_3 => pc_xu_ary_slp_nsl_thold_3, + pc_xu_repr_sl_thold_3 => pc_xu_repr_sl_thold_3, + pc_xu_fce_3 => pc_xu_fce_3, + an_ac_scan_diag_dc => an_ac_scan_diag_dc, + sg_2 => sg_2, + fce_2 => fce_2, + func_sl_thold_2 => func_sl_thold_2, + func_slp_sl_thold_2 => func_slp_sl_thold_2, + func_nsl_thold_2 => func_nsl_thold_2, + abst_sl_thold_2 => abst_sl_thold_2, + time_sl_thold_2 => time_sl_thold_2, + ary_nsl_thold_2 => ary_nsl_thold_2, + repr_sl_thold_2 => repr_sl_thold_2, + gptr_sl_thold_2 => gptr_sl_thold_2, + cfg_sl_thold_2 => cfg_sl_thold_2, + cfg_slp_sl_thold_2 => cfg_slp_sl_thold_2, + regf_slp_sl_thold_2 => regf_slp_sl_thold_2, + pc_xu_bolt_sl_thold_3 => pc_xu_bolt_sl_thold_3, + pc_xu_bo_enable_3 => pc_xu_bo_enable_3, + bolt_sl_thold_2 => bolt_sl_thold_2, + bo_enable_2 => bo_enable_2, + pc_xu_bo_unload => pc_xu_bo_unload, + pc_xu_bo_repair => pc_xu_bo_repair, + pc_xu_bo_reset => pc_xu_bo_reset, + pc_xu_bo_shdata => pc_xu_bo_shdata, + pc_xu_bo_select => pc_xu_bo_select(0 to 4), + xu_pc_bo_fail => xu_pc_bo_fail(0 to 4), + xu_pc_bo_diagout => xu_pc_bo_diagout(0 to 4), + + --------------------------------------------------------------------- + -- Interface with FXU A + --------------------------------------------------------------------- + fxa_fxb_rf0_val => fxa_fxb_rf0_val, + fxa_fxb_rf0_issued => fxa_fxb_rf0_issued, + fxa_fxb_rf0_ucode_val => fxa_fxb_rf0_ucode_val, + fxa_fxb_rf0_act => fxa_fxb_rf0_act, + fxa_fxb_ex1_hold_ctr_flush => fxa_fxb_ex1_hold_ctr_flush, + fxa_fxb_rf0_instr => fxa_fxb_rf0_instr, + fxa_fxb_rf0_tid => fxa_fxb_rf0_tid, + fxa_fxb_rf0_ta_vld => fxa_fxb_rf0_ta_vld, + fxa_fxb_rf0_ta => fxa_fxb_rf0_ta, + fxa_fxb_rf0_error => fxa_fxb_rf0_error, + fxa_fxb_rf0_match => fxa_fxb_rf0_match, + fxa_fxb_rf0_is_ucode => fxa_fxb_rf0_is_ucode, + fxa_fxb_rf0_gshare => fxa_fxb_rf0_gshare, + fxa_fxb_rf0_ifar => fxa_fxb_rf0_ifar, + fxa_fxb_rf0_s1_vld => fxa_fxb_rf0_s1_vld, + fxa_fxb_rf0_s1 => fxa_fxb_rf0_s1, + fxa_fxb_rf0_s2_vld => fxa_fxb_rf0_s2_vld, + fxa_fxb_rf0_s2 => fxa_fxb_rf0_s2, + fxa_fxb_rf0_s3_vld => fxa_fxb_rf0_s3_vld, + fxa_fxb_rf0_s3 => fxa_fxb_rf0_s3, + fxa_fxb_rf0_axu_instr_type => fxa_fxb_rf0_axu_instr_type, + fxa_fxb_rf0_axu_ld_or_st => fxa_fxb_rf0_axu_ld_or_st, + fxa_fxb_rf0_axu_store => fxa_fxb_rf0_axu_store, + fxa_fxb_rf0_axu_ldst_forcealign => fxa_fxb_rf0_axu_ldst_forcealign, + fxa_fxb_rf0_axu_ldst_forceexcept => fxa_fxb_rf0_axu_ldst_forceexcept, + fxa_fxb_rf0_axu_ldst_indexed => fxa_fxb_rf0_axu_ldst_indexed, + fxa_fxb_rf0_axu_ldst_tag => fxa_fxb_rf0_axu_ldst_tag, + fxa_fxb_rf0_axu_mftgpr => fxa_fxb_rf0_axu_mftgpr, + fxa_fxb_rf0_axu_mffgpr => fxa_fxb_rf0_axu_mffgpr, + fxa_fxb_rf0_axu_movedp => fxa_fxb_rf0_axu_movedp, + fxa_fxb_rf0_axu_ldst_size => fxa_fxb_rf0_axu_ldst_size, + fxa_fxb_rf0_axu_ldst_update => fxa_fxb_rf0_axu_ldst_update, + fxa_fxb_rf0_pred_update => fxa_fxb_rf0_pred_update, + fxa_fxb_rf0_pred_taken_cnt => fxa_fxb_rf0_pred_taken_cnt, + fxa_fxb_rf0_mc_dep_chk_val => fxa_fxb_rf0_mc_dep_chk_val, + fxa_fxb_rf1_mul_val => fxa_fxb_rf1_mul_val, + fxa_fxb_rf1_div_val => fxa_fxb_rf1_div_val, + fxa_fxb_rf1_div_ctr => fxa_fxb_rf1_div_ctr, + fxa_fxb_rf0_xu_epid_instr => fxa_fxb_rf0_xu_epid_instr, + fxa_fxb_rf0_axu_is_extload => fxa_fxb_rf0_axu_is_extload, + fxa_fxb_rf0_axu_is_extstore => fxa_fxb_rf0_axu_is_extstore, + fxa_fxb_rf0_is_mfocrf => fxa_fxb_rf0_is_mfocrf, + fxa_fxb_rf0_3src_instr => fxa_fxb_rf0_3src_instr, + fxa_fxb_rf0_gpr0_zero => fxa_fxb_rf0_gpr0_zero, + fxa_fxb_rf0_use_imm => fxa_fxb_rf0_use_imm, + fxa_fxb_rf1_muldiv_coll => fxa_fxb_rf1_muldiv_coll, + fxa_cpl_ex2_div_coll => fxa_cpl_ex2_div_coll, + fxb_fxa_ex7_we0 => fxb_fxa_ex7_we0, + fxb_fxa_ex7_wa0 => fxb_fxa_ex7_wa0, + fxb_fxa_ex7_wd0 => fxb_fxa_ex7_wd0, + fxa_fxb_rf1_do0 => fxa_fxb_rf1_do0, + fxa_fxb_rf1_do1 => fxa_fxb_rf1_do1, + fxa_fxb_rf1_do2 => fxa_fxb_rf1_do2, + + --------------------------------------------------------------------- + -- BOXES Req Interface + --------------------------------------------------------------------- + xu_bx_ex1_mtdp_val => xu_bx_ex1_mtdp_val, + xu_bx_ex1_mfdp_val => xu_bx_ex1_mfdp_val, + xu_bx_ex1_ipc_thrd => xu_bx_ex1_ipc_thrd, + xu_bx_ex2_ipc_ba => xu_bx_ex2_ipc_ba, + xu_bx_ex2_ipc_sz => xu_bx_ex2_ipc_sz, + + --------------------------------------------------------------------- + -- D-ERAT Req Interface + --------------------------------------------------------------------- + xu_mm_derat_epn => xu_mm_derat_epn, + + --------------------------------------------------------------------- + -- TLBSX./TLBSRX. + --------------------------------------------------------------------- + xu_mm_rf1_is_tlbsxr => xu_mm_rf1_is_tlbsxr, + mm_xu_cr0_eq_valid => mm_xu_cr0_eq_valid, + mm_xu_cr0_eq => mm_xu_cr0_eq, + + --------------------------------------------------------------------- + -- FU CR Write + --------------------------------------------------------------------- + fu_xu_ex4_cr_val => fu_xu_ex4_cr_val, + fu_xu_ex4_cr_noflush => fu_xu_ex4_cr_noflush, + fu_xu_ex4_cr0 => fu_xu_ex4_cr0, + fu_xu_ex4_cr0_bf => fu_xu_ex4_cr0_bf, + fu_xu_ex4_cr1 => fu_xu_ex4_cr1, + fu_xu_ex4_cr1_bf => fu_xu_ex4_cr1_bf, + fu_xu_ex4_cr2 => fu_xu_ex4_cr2, + fu_xu_ex4_cr2_bf => fu_xu_ex4_cr2_bf, + fu_xu_ex4_cr3 => fu_xu_ex4_cr3, + fu_xu_ex4_cr3_bf => fu_xu_ex4_cr3_bf, + + --------------------------------------------------------------------- + -- RAM + --------------------------------------------------------------------- + pc_xu_ram_mode => pc_xu_ram_mode, + pc_xu_ram_thread => pc_xu_ram_thread, + pc_xu_ram_execute => pc_xu_ram_execute, + pc_xu_ram_flush_thread => pc_xu_ram_flush_thread, + xu_iu_ram_issue => xu_iu_ram_issue, + xu_pc_ram_interrupt => xu_pc_ram_interrupt, + xu_pc_ram_done => xu_pc_ram_done, + xu_pc_ram_data => xu_pc_ram_data, + + --------------------------------------------------------------------- + -- Interface with PC + --------------------------------------------------------------------- + pc_xu_msrovride_enab => pc_xu_msrovride_enab, + pc_xu_msrovride_gs => pc_xu_msrovride_gs, + pc_xu_msrovride_de => pc_xu_msrovride_de, + + --------------------------------------------------------------------- + -- Interface with IU + --------------------------------------------------------------------- + xu_iu_ex5_val => xu_iu_ex5_val, + xu_iu_ex5_tid => xu_iu_ex5_tid, + xu_iu_ex5_br_update => xu_iu_ex5_br_update, + xu_iu_ex5_br_hist => xu_iu_ex5_br_hist, + xu_iu_ex5_bclr => xu_iu_ex5_bclr, + xu_iu_ex5_lk => xu_iu_ex5_lk, + xu_iu_ex5_bh => xu_iu_ex5_bh, + xu_iu_ex6_pri => xu_iu_ex6_pri, + xu_iu_ex6_pri_val => xu_iu_ex6_pri_val, + xu_iu_spr_xer => xu_iu_spr_xer, + xu_iu_slowspr_done => xu_iu_slowspr_done, + xu_iu_need_hole => xu_iu_need_hole, + fxb_fxa_ex6_clear_barrier => fxb_fxa_ex6_clear_barrier, + xu_iu_ex5_gshare => xu_iu_ex5_gshare, + xu_iu_ex5_getNIA => xu_iu_ex5_getNIA, + + --------------------------------------------------------------------- + -- L2 STCX complete + --------------------------------------------------------------------- + an_ac_stcx_complete => an_ac_stcx_complete, + an_ac_stcx_pass => an_ac_stcx_pass, + xu_iu_stcx_complete => xu_iu_stcx_complete, + xu_iu_reld_core_tag_clone => xu_iu_reld_core_tag_clone, + xu_iu_reld_data_coming_clone => xu_iu_reld_data_coming_clone, + xu_iu_reld_data_vld_clone => xu_iu_reld_data_vld_clone, + xu_iu_reld_ditc_clone => xu_iu_reld_ditc_clone, + + --------------------------------------------------------------------- + -- Slow SPR Bus + --------------------------------------------------------------------- + slowspr_val_in => slowspr_val_in, + slowspr_rw_in => slowspr_rw_in, + slowspr_etid_in => slowspr_etid_in, + slowspr_addr_in => slowspr_addr_in, + slowspr_data_in => slowspr_data_in, + slowspr_done_in => slowspr_done_in, + slowspr_val_out => slowspr_val_out, + slowspr_rw_out => slowspr_rw_out, + slowspr_etid_out => slowspr_etid_out, + slowspr_addr_out => slowspr_addr_out, + slowspr_data_out => slowspr_data_out, + slowspr_done_out => slowspr_done_out, + + --------------------------------------------------------------------- + -- DCR Bus + --------------------------------------------------------------------- + an_ac_dcr_act => tidn(0), + an_ac_dcr_val => tidn(0), + an_ac_dcr_read => tidn(0), + an_ac_dcr_etid => tidn(0 to 1), + an_ac_dcr_data => tidn(64-(2**regmode) to 63), + an_ac_dcr_done => tidn(0), + + --------------------------------------------------------------------- + -- MT/MFDCR CR + --------------------------------------------------------------------- + lsu_xu_ex4_mtdp_cr_status => bx_xu_ex4_mtdp_cr_status, + lsu_xu_ex4_mfdp_cr_status => bx_xu_ex4_mfdp_cr_status, + dec_cpl_ex3_mc_dep_chk_val => dec_cpl_ex3_mc_dep_chk_val, + + --------------------------------------------------------------------- + -- Perf Events + --------------------------------------------------------------------- + fxa_perf_muldiv_in_use => fxa_perf_muldiv_in_use, + xu_pc_event_data => xu_pc_event_data, + + --------------------------------------------------------------------- + -- PC Control Interface + --------------------------------------------------------------------- + pc_xu_event_count_mode => pc_xu_event_count_mode, + pc_xu_event_mux_ctrls => pc_xu_event_mux_ctrls, + + --------------------------------------------------------------------- + -- Debug Ramp & Controls + --------------------------------------------------------------------- + spr_debug_mux_ctrls => spr_debug_mux_ctrls, + fxu_debug_mux_ctrls => fxu_debug_mux_ctrls, + cpl_debug_mux_ctrls => cpl_debug_mux_ctrls, + lsu_debug_mux_ctrls => lsu_debug_mux_ctrls, + trigger_data_in => trigger_data_in, + trigger_data_out => trigger_data_out, + debug_data_in => debug_data_in, + debug_data_out => debug_data_out, + lsu_xu_data_debug0 => lsu_xu_data_debug0, + lsu_xu_data_debug1 => lsu_xu_data_debug1, + lsu_xu_data_debug2 => lsu_xu_data_debug2, + fxa_cpl_debug => fxa_cpl_debug, + + -- CHIP IO + ac_tc_debug_trigger => ac_tc_debug_trigger, + + -- Valids + dec_cpl_rf0_act => fxa_fxb_rf0_cpl_act, + dec_cpl_rf0_tid => fxa_fxb_rf0_cpl_tid, + + -- FU Inputs + fu_xu_rf1_act => fu_xu_rf1_act, + fu_xu_ex1_ifar => fu_xu_ex1_ifar, + fu_xu_ex2_ifar_val => fu_xu_ex2_ifar_val, + fu_xu_ex2_ifar_issued => fu_xu_ex2_ifar_issued, + fu_xu_ex2_instr_type => fu_xu_ex2_instr_type, + fu_xu_ex2_instr_match => fu_xu_ex2_instr_match, + fu_xu_ex2_is_ucode => fu_xu_ex2_is_ucode, + + -- PC Inputs + pc_xu_stop => pc_xu_stop, + pc_xu_step => pc_xu_step, + pc_xu_dbg_action => pc_xu_dbg_action, + pc_xu_force_ude => pc_xu_force_ude, + xu_pc_step_done => xu_pc_step_done, + pc_xu_init_reset => pc_xu_init_reset, + + -- Machine Check Interrupts + mm_xu_local_snoop_reject => mm_xu_local_snoop_reject, + mm_xu_lru_par_err => mm_xu_lru_par_err, + mm_xu_tlb_par_err => mm_xu_tlb_par_err, + mm_xu_tlb_multihit_err => mm_xu_tlb_multihit_err, + an_ac_external_mchk => an_ac_external_mchk, + + -- PC Errors + xu_pc_err_attention_instr => xu_pc_err_attention_instr, + xu_pc_err_nia_miscmpr => xu_pc_err_nia_miscmpr, + xu_pc_err_debug_event => xu_pc_err_debug_event, + + xu_pc_stop_dbg_event => xu_pc_stop_dbg_event, + + -- MMU Flushes + mm_xu_illeg_instr => mm_xu_illeg_instr, + mm_xu_tlb_miss => mm_xu_tlb_miss, + mm_xu_pt_fault => mm_xu_pt_fault, + mm_xu_tlb_inelig => mm_xu_tlb_inelig, + mm_xu_lrat_miss => mm_xu_lrat_miss, + mm_xu_hv_priv => mm_xu_hv_priv, + mm_xu_esr_pt => mm_xu_esr_pt, + mm_xu_esr_data => mm_xu_esr_data, + mm_xu_esr_epid => mm_xu_esr_epid, + mm_xu_esr_st => mm_xu_esr_st, + mm_xu_hold_req => mm_xu_hold_req, + mm_xu_hold_done => mm_xu_hold_done, + xu_mm_hold_ack => xu_mm_hold_ack, + mm_xu_eratmiss_done => mm_xu_eratmiss_done, + mm_xu_ex3_flush_req => mm_xu_ex3_flush_req, + + -- AXU Flushes + fu_xu_ex3_ap_int_req => fu_xu_ex3_ap_int_req, + fu_xu_ex3_trap => fu_xu_ex3_trap, + fu_xu_ex3_n_flush => fu_xu_ex3_n_flush, + fu_xu_ex3_np1_flush => fu_xu_ex3_np1_flush, + fu_xu_ex3_flush2ucode => fu_xu_ex3_flush2ucode, + fu_xu_ex2_async_block => fu_xu_ex2_async_block, + + -- IU Flushes + xu_iu_ex5_br_taken => xu_iu_ex5_br_taken, + xu_iu_ex5_ifar => xu_iu_ex5_ifar, + xu_iu_flush => xu_iu_flush, + xu_iu_iu0_flush_ifar => xu_iu_iu0_flush_ifar, + xu_iu_uc_flush_ifar => xu_iu_uc_flush_ifar, + xu_iu_flush_2ucode => xu_iu_flush_2ucode, + xu_iu_flush_2ucode_type => xu_iu_flush_2ucode_type, + xu_iu_ucode_restart => xu_iu_ucode_restart, + xu_iu_ex5_ppc_cpl => xu_iu_ex5_ppc_cpl, + + -- Flushes + xu_n_is2_flush => is2_flush, + xu_n_rf0_flush => rf0_flush, + xu_n_rf1_flush => rf1_flush, + xu_n_ex1_flush => ex1_flush, + xu_n_ex2_flush => ex2_flush, + xu_n_ex3_flush => ex3_flush, + xu_n_ex4_flush => ex4_flush, + xu_n_ex5_flush => ex5_flush, + + xu_s_rf1_flush => xu_s_rf1_flush, + xu_s_ex1_flush => xu_s_ex1_flush, + xu_s_ex2_flush => xu_s_ex2_flush, + xu_s_ex3_flush => xu_s_ex3_flush, + xu_s_ex4_flush => xu_s_ex4_flush, + xu_s_ex5_flush => xu_s_ex5_flush, + + xu_w_rf1_flush => xu_w_rf1_flush, + xu_w_ex1_flush => xu_w_ex1_flush, + xu_w_ex2_flush => xu_w_ex2_flush, + xu_w_ex3_flush => xu_w_ex3_flush, + xu_w_ex4_flush => xu_w_ex4_flush, + xu_w_ex5_flush => xu_w_ex5_flush, + + xu_lsu_ex4_flush_local => xu_lsu_ex4_flush_local, + xu_mm_ex4_flush => xu_mm_ex4_flush, + xu_mm_ex5_flush => xu_mm_ex5_flush, + xu_mm_ierat_flush => xu_mm_ierat_flush, + xu_mm_ierat_miss => xu_mm_ierat_miss, + xu_mm_ex5_perf_itlb => xu_mm_ex5_perf_itlb, + xu_mm_ex5_perf_dtlb => xu_mm_ex5_perf_dtlb, + + spr_xucr4_div_barr_thres => spr_xucr4_div_barr_thres, + + -- Parity + iu_xu_ierat_ex2_flush_req => iu_xu_ierat_ex2_flush_req, + iu_xu_ierat_ex3_par_err => iu_xu_ierat_ex3_par_err, + iu_xu_ierat_ex4_par_err => iu_xu_ierat_ex4_par_err, + + -- Regfile Parity + fu_xu_ex3_regfile_err_det => fu_xu_ex3_regfile_err_det, + xu_fu_regfile_seq_beg => xu_fu_regfile_seq_beg, + fu_xu_regfile_seq_end => fu_xu_regfile_seq_end, + gpr_cpl_ex3_regfile_err_det => gpr_cpl_ex3_regfile_err_det, + cpl_gpr_regfile_seq_beg => cpl_gpr_regfile_seq_beg, + gpr_cpl_regfile_seq_end => gpr_cpl_regfile_seq_end, + xu_pc_err_mcsr_summary => xu_pc_err_mcsr_summary, + xu_pc_err_ditc_overrun => xu_pc_err_ditc_overrun, + xu_pc_err_local_snoop_reject => xu_pc_err_local_snoop_reject, + xu_pc_err_tlb_lru_parity => xu_pc_err_tlb_lru_parity, + xu_pc_err_ext_mchk => xu_pc_err_ext_mchk, + xu_pc_err_ierat_multihit => xu_pc_err_ierat_multihit, + xu_pc_err_derat_multihit => xu_pc_err_derat_multihit, + xu_pc_err_tlb_multihit => xu_pc_err_tlb_multihit, + xu_pc_err_ierat_parity => xu_pc_err_ierat_parity, + xu_pc_err_derat_parity => xu_pc_err_derat_parity, + xu_pc_err_tlb_parity => xu_pc_err_tlb_parity, + xu_pc_err_mchk_disabled => xu_pc_err_mchk_disabled, + + -- Debug + xu_iu_rf1_val => xu_iu_rf1_val, + xu_rf1_val => xu_rf1_val, + xu_rf1_is_tlbre => xu_mm_rf1_is_tlbre, + xu_rf1_is_tlbwe => xu_mm_rf1_is_tlbwe, + xu_rf1_is_tlbsx => xu_mm_rf1_is_tlbsx, + xu_rf1_is_tlbsrx => xu_mm_rf1_is_tlbsrx, + xu_rf1_is_tlbilx => xu_mm_rf1_is_tlbilx, + xu_rf1_is_tlbivax => xu_mm_rf1_is_tlbivax, + xu_rf1_is_eratre => xu_iu_rf1_is_eratre, + xu_rf1_is_eratwe => xu_iu_rf1_is_eratwe, + xu_rf1_is_eratsx => xu_iu_rf1_is_eratsx, + xu_rf1_is_eratilx => xu_rf1_is_eratilx, + xu_rf1_is_erativax => xu_mm_rf1_is_erativax, + xu_ex1_is_isync => xu_ex1_is_isync, + xu_ex1_is_csync => xu_ex1_is_csync, + xu_rf1_ws => xu_rf1_ws, + xu_rf1_t => xu_rf1_t, + xu_ex1_rs_is => xu_ex1_rs_is, + xu_ex1_ra_entry => xu_ex1_ra_entry, + xu_ex4_rs_data => xu_ex4_rs_data, + + xu_lsu_rf1_data_act => xu_lsu_rf1_data_act, + xu_lsu_rf1_axu_ldst_falign => xu_lsu_rf1_axu_ldst_falign, + xu_lsu_ex1_store_data => xu_lsu_ex1_store_data, + xu_lsu_ex1_rotsel_ovrd => xu_lsu_ex1_rotsel_ovrd, + xu_lsu_ex1_eff_addr => xu_lsu_ex1_eff_addr, + + -- Barrier + cpl_fxa_ex5_set_barr => cpl_fxa_ex5_set_barr, + cpl_iu_set_barr_tid => cpl_iu_set_barr_tid, + + lsu_xu_ex6_datc_par_err => lsu_xu_ex6_datc_par_err, + + lsu_xu_rel_dvc1_en => lsu_xu_rel_dvc1_en, + lsu_xu_rel_dvc2_en => lsu_xu_rel_dvc2_en, + lsu_xu_ex2_dvc1_st_cmp => lsu_xu_ex2_dvc1_st_cmp, + lsu_xu_ex2_dvc2_st_cmp => lsu_xu_ex2_dvc2_st_cmp, + lsu_xu_ex8_dvc1_ld_cmp => lsu_xu_ex8_dvc1_ld_cmp, + lsu_xu_ex8_dvc2_ld_cmp => lsu_xu_ex8_dvc2_ld_cmp, + lsu_xu_rel_dvc_thrd_id => lsu_xu_rel_dvc_thrd_id, + lsu_xu_rel_dvc1_cmp => lsu_xu_rel_dvc1_cmp, + lsu_xu_rel_dvc2_cmp => lsu_xu_rel_dvc2_cmp, + + lsu_xu_rot_ex6_data_b => lsu_xu_rot_ex6_data_b, + lsu_xu_rot_rel_data => lsu_xu_rot_rel_data, + pc_xu_trace_bus_enable => pc_xu_trace_bus_enable, + pc_xu_instr_trace_mode => pc_xu_instr_trace_mode, + pc_xu_instr_trace_tid => pc_xu_instr_trace_tid, + iu_xu_ex4_tlb_data => iu_xu_ex4_tlb_data, + + -- Error Inject + pc_xu_inj_dcachedir_parity => pc_xu_inj_dcachedir_parity, + pc_xu_inj_dcachedir_multihit => pc_xu_inj_dcachedir_multihit, + + ex4_256st_data => ex4_256st_data, + an_ac_flh2l2_gate => an_ac_flh2l2_gate, + + -- ERAT Operations + xu_lsu_rf0_derat_val => xu_lsu_rf0_derat_val, + xu_lsu_rf0_derat_is_extload => xu_lsu_rf0_derat_is_extload, + xu_lsu_rf0_derat_is_extstore => xu_lsu_rf0_derat_is_extstore, + xu_lsu_hid_mmu_mode => xu_lsu_hid_mmu_mode, + ex6_ld_par_err => ex6_ld_par_err, + + xu_mm_derat_req => xu_mm_derat_req, + xu_mm_derat_thdid => xu_mm_derat_thdid, + xu_mm_derat_state => xu_mm_derat_state, + xu_mm_derat_tid => xu_mm_derat_tid, + xu_mm_derat_lpid => xu_mm_derat_lpid, + xu_mm_derat_ttype => xu_mm_derat_ttype, + mm_xu_derat_rel_val => mm_xu_derat_rel_val, + mm_xu_derat_rel_data => mm_xu_derat_rel_data, + mm_xu_derat_pid0 => mm_xu_derat_pid0, + mm_xu_derat_pid1 => mm_xu_derat_pid1, + mm_xu_derat_pid2 => mm_xu_derat_pid2, + mm_xu_derat_pid3 => mm_xu_derat_pid3, + mm_xu_derat_mmucr0_0 => mm_xu_derat_mmucr0_0, + mm_xu_derat_mmucr0_1 => mm_xu_derat_mmucr0_1, + mm_xu_derat_mmucr0_2 => mm_xu_derat_mmucr0_2, + mm_xu_derat_mmucr0_3 => mm_xu_derat_mmucr0_3, + xu_mm_derat_mmucr0 => xu_mm_derat_mmucr0, + xu_mm_derat_mmucr0_we => xu_mm_derat_mmucr0_we, + mm_xu_derat_mmucr1 => mm_xu_derat_mmucr1, + xu_mm_derat_mmucr1 => xu_mm_derat_mmucr1, + xu_mm_derat_mmucr1_we => xu_mm_derat_mmucr1_we, + mm_xu_derat_snoop_coming => mm_xu_derat_snoop_coming, + mm_xu_derat_snoop_val => mm_xu_derat_snoop_val, + mm_xu_derat_snoop_attr => mm_xu_derat_snoop_attr, + mm_xu_derat_snoop_vpn => mm_xu_derat_snoop_vpn, + xu_mm_derat_snoop_ack => xu_mm_derat_snoop_ack, + + ex1_optype1 => ex1_optype1, + ex1_optype2 => ex1_optype2, + ex1_optype4 => ex1_optype4, + ex1_optype8 => ex1_optype8, + ex1_optype16 => ex1_optype16, + ex1_optype32 => ex1_optype32, + ex1_saxu_instr => ex1_saxu_instr, + ex1_sdp_instr => ex1_sdp_instr, + ex1_stgpr_instr => ex1_stgpr_instr, + ex1_store_instr => ex1_store_instr, + ex1_axu_op_val => ex1_axu_op_val, + + ex3_algebraic => ex3_algebraic, + ex3_data_swap => ex3_data_swap, + ex3_thrd_id => ex3_thrd_id, + xu_fu_ex3_eff_addr => xu_fu_ex3_eff_addr, + xu_lsu_ici => xu_lsu_ici, + + -- Update Data Array Valid + rel_upd_dcarr_val => rel_upd_dcarr_val, + + xu_fu_ex5_reload_val => xu_fu_ex5_reload_val, + xu_fu_ex5_load_val => xu_fu_ex5_load_val, + xu_fu_ex5_load_tag => xu_fu_ex5_load_tag, + + -- Data Array Controls + dcarr_up_way_addr => dcarr_up_way_addr, + + -- Debug Data Compare + ex4_load_op_hit => ex4_load_op_hit, + ex4_store_hit => ex4_store_hit, + ex4_axu_op_val => ex4_axu_op_val, + spr_dvc1_act => spr_dvc1_act, + spr_dvc2_act => spr_dvc2_act, + spr_dvc1_dbg => spr_dvc1_dbg, + spr_dvc2_dbg => spr_dvc2_dbg, + + -- Inputs from L2 + an_ac_req_ld_pop => an_ac_req_ld_pop, + an_ac_req_st_pop => an_ac_req_st_pop, + an_ac_req_st_gather => an_ac_req_st_gather, + an_ac_req_st_pop_thrd => an_ac_req_st_pop_thrd, + an_ac_reld_data_vld => an_ac_reld_data_vld, + an_ac_reld_core_tag => an_ac_reld_core_tag, + an_ac_reld_qw => an_ac_reld_qw, + an_ac_reld_data => an_ac_reld_data, + an_ac_reld_data_coming => an_ac_reld_data_coming, + an_ac_reld_ditc => an_ac_reld_ditc, + an_ac_reld_crit_qw => an_ac_reld_crit_qw, + an_ac_reld_l1_dump => an_ac_reld_l1_dump, + an_ac_reld_ecc_err => an_ac_reld_ecc_err, + an_ac_reld_ecc_err_ue => an_ac_reld_ecc_err_ue, + an_ac_back_inv => an_ac_back_inv, + an_ac_back_inv_addr => an_ac_back_inv_addr, + an_ac_back_inv_target_bit1 => an_ac_back_inv_target_bit1, + an_ac_back_inv_target_bit3 => an_ac_back_inv_target_bit3, + an_ac_back_inv_target_bit4 => an_ac_back_inv_target_bit4, + an_ac_req_spare_ctrl_a1 => an_ac_req_spare_ctrl_a1, + + -- redrive to boxes logic + lsu_reld_data_vld => lsu_reld_data_vld, + lsu_reld_core_tag => lsu_reld_core_tag, + lsu_reld_qw => lsu_reld_qw, + lsu_reld_ditc => lsu_reld_ditc, + lsu_reld_ecc_err => lsu_reld_ecc_err, + lsu_reld_data => lsu_reld_data, + + lsu_req_st_pop => lsu_req_st_pop, + lsu_req_st_pop_thrd => lsu_req_st_pop_thrd, + + -- latch and redrive for BXQ + ac_an_reld_ditc_pop_int => ac_an_reld_ditc_pop_int, + ac_an_reld_ditc_pop_q => ac_an_reld_ditc_pop_q , + bx_ib_empty_int => bx_ib_empty_int , + bx_ib_empty_q => bx_ib_empty_q , + + -- Instruction Fetches + iu_xu_ra => iu_xu_ra, + iu_xu_request => iu_xu_request, + iu_xu_wimge => iu_xu_wimge, + iu_xu_thread => iu_xu_thread, + iu_xu_userdef => iu_xu_userdef, + + -- MMU instruction interface + mm_xu_lsu_req => mm_xu_lsu_req, + mm_xu_lsu_ttype => mm_xu_lsu_ttype, + mm_xu_lsu_wimge => mm_xu_lsu_wimge, + mm_xu_lsu_u => mm_xu_lsu_u, + mm_xu_lsu_addr => mm_xu_lsu_addr, + mm_xu_lsu_lpid => mm_xu_lsu_lpid, + mm_xu_lsu_lpidr => mm_xu_lsu_lpidr, + mm_xu_lsu_gs => mm_xu_lsu_gs, + mm_xu_lsu_ind => mm_xu_lsu_ind, + mm_xu_lsu_lbit => mm_xu_lsu_lbit, + xu_mm_lsu_token => xu_mm_lsu_token, + + -- Boxes interface + bx_lsu_ob_pwr_tok => bx_lsu_ob_pwr_tok, + bx_lsu_ob_req_val => bx_lsu_ob_req_val, + bx_lsu_ob_ditc_val => bx_lsu_ob_ditc_val, + bx_lsu_ob_thrd => bx_lsu_ob_thrd, + bx_lsu_ob_qw => bx_lsu_ob_qw, + bx_lsu_ob_dest => bx_lsu_ob_dest, + bx_lsu_ob_data => bx_lsu_ob_data, + bx_lsu_ob_addr => bx_lsu_ob_addr, + lsu_bx_cmd_avail => lsu_bx_cmd_avail, + lsu_bx_cmd_sent => lsu_bx_cmd_sent, + lsu_bx_cmd_stall => lsu_bx_cmd_stall, + + lsu_xu_ldq_barr_done => lsu_xu_ldq_barr_done, + lsu_xu_barr_done => lsu_xu_barr_done, + + -- *** Reload operation Outputs *** + ldq_rel_data_val_early => ldq_rel_data_val_early, + ldq_rel_op_size => ldq_rel_op_size, + ldq_rel_addr => ldq_rel_addr, + ldq_rel_data_val => ldq_rel_data_val, + ldq_rel_rot_sel => ldq_rel_rot_sel, + ldq_rel_axu_val => ldq_rel_axu_val, + ldq_rel_ci => ldq_rel_ci, + ldq_rel_thrd_id => ldq_rel_thrd_id, + ldq_rel_le_mode => ldq_rel_le_mode, + ldq_rel_algebraic => ldq_rel_algebraic, + ldq_rel_256_data => ldq_rel_256_data, + ldq_rel_dvc1_en => ldq_rel_dvc1_en, + ldq_rel_dvc2_en => ldq_rel_dvc2_en, + ldq_rel_beat_crit_qw => ldq_rel_beat_crit_qw, + ldq_rel_beat_crit_qw_block => ldq_rel_beat_crit_qw_block, + lsu_xu_rel_wren => lsu_xu_rel_wren, + lsu_xu_rel_ta_gpr => lsu_xu_rel_ta_gpr, + + xu_iu_ex4_loadmiss_qentry => xu_iu_ex4_loadmiss_qentry, + xu_iu_ex4_loadmiss_target => xu_iu_ex4_loadmiss_target, + xu_iu_ex4_loadmiss_target_type => xu_iu_ex4_loadmiss_target_type, + xu_iu_ex4_loadmiss_tid => xu_iu_ex4_loadmiss_tid, + xu_iu_ex5_loadmiss_qentry => xu_iu_ex5_loadmiss_qentry, + xu_iu_ex5_loadmiss_target => xu_iu_ex5_loadmiss_target, + xu_iu_ex5_loadmiss_target_type => xu_iu_ex5_loadmiss_target_type, + xu_iu_ex5_loadmiss_tid => xu_iu_ex5_loadmiss_tid, + xu_iu_complete_qentry => xu_iu_complete_qentry, + xu_iu_complete_tid => xu_iu_complete_tid, + xu_iu_complete_target_type => xu_iu_complete_target_type, + + -- ICBI Interface + xu_iu_ex6_icbi_val => xu_iu_ex6_icbi_val, + xu_iu_ex6_icbi_addr => xu_iu_ex6_icbi_addr, + + xu_iu_larx_done_tid => xu_iu_larx_done_tid, + xu_mm_lmq_stq_empty => xu_mm_lmq_stq_empty, + + xu_ex1_rb => xu_iu_ex1_rb, + xu_ex2_eff_addr => xu_ex2_eff_addr, + + ac_an_req_pwr_token => ac_an_req_pwr_token, + ac_an_req => ac_an_req, + ac_an_req_ra => ac_an_req_ra, + ac_an_req_ttype => ac_an_req_ttype, + ac_an_req_thread => ac_an_req_thread, + ac_an_req_wimg_w => ac_an_req_wimg_w, + ac_an_req_wimg_i => ac_an_req_wimg_i, + ac_an_req_wimg_m => ac_an_req_wimg_m, + ac_an_req_wimg_g => ac_an_req_wimg_g, + ac_an_req_endian => ac_an_req_endian, + ac_an_req_user_defined => ac_an_req_user_defined, + ac_an_req_spare_ctrl_a0 => ac_an_req_spare_ctrl_a0, + ac_an_req_ld_core_tag => ac_an_req_ld_core_tag, + ac_an_req_ld_xfr_len => ac_an_req_ld_xfr_len, + ac_an_st_byte_enbl => ac_an_st_byte_enbl, + ac_an_st_data => ac_an_st_data, + ac_an_st_data_pwr_token => ac_an_st_data_pwr_token, + + --pervasive + xu_pc_err_dcachedir_parity => xu_pc_err_dcachedir_parity, + xu_pc_err_dcachedir_multihit => xu_pc_err_dcachedir_multihit, + xu_pc_err_l2intrf_ecc => xu_pc_err_l2intrf_ecc, + xu_pc_err_l2intrf_ue => xu_pc_err_l2intrf_ue, + xu_pc_err_invld_reld => xu_pc_err_invld_reld, + xu_pc_err_l2credit_overrun => xu_pc_err_l2credit_overrun, + + -- Performance Counters + pc_xu_event_bus_enable => pc_xu_event_bus_enable, + pc_xu_lsu_event_mux_ctrls => pc_xu_lsu_event_mux_ctrls, + pc_xu_cache_par_err_event => pc_xu_cache_par_err_event, + xu_pc_lsu_event_data => xu_pc_lsu_event_data, + + + -- Decode + dec_spr_rf0_tid => fxa_fxb_rf0_spr_tid, + dec_spr_rf0_instr => dec_spr_rf0_instr, + + -- DCR Bus + ac_an_dcr_act => open, + ac_an_dcr_val => open, + ac_an_dcr_read => open, + ac_an_dcr_user => open, + ac_an_dcr_etid => open, + ac_an_dcr_addr => open, + ac_an_dcr_data => open, + + -- Run State + xu_pc_running => xu_pc_running, + xu_iu_run_thread => xu_iu_run_thread, + xu_iu_single_instr_mode => xu_iu_single_instr_mode, + xu_iu_raise_iss_pri => xu_iu_raise_iss_pri, + xu_pc_spr_ccr0_we => xu_pc_spr_ccr0_we, + + -- Quiesce + iu_xu_quiesce => iu_xu_quiesce, + mm_xu_quiesce => mm_xu_quiesce, + bx_xu_quiesce => bx_xu_quiesce, + + -- PCCR0 + pc_xu_extirpts_dis_on_stop => pc_xu_extirpts_dis_on_stop, + pc_xu_timebase_dis_on_stop => pc_xu_timebase_dis_on_stop, + pc_xu_decrem_dis_on_stop => pc_xu_decrem_dis_on_stop, + + -- MSR Override + pc_xu_msrovride_pr => pc_xu_msrovride_pr, + + -- LiveLock + xu_pc_err_llbust_attempt => xu_pc_err_llbust_attempt, + xu_pc_err_llbust_failed => xu_pc_err_llbust_failed, + + -- Resets + pc_xu_reset_wd_complete => pc_xu_reset_wd_complete, + pc_xu_reset_1_complete => pc_xu_reset_1_complete, + pc_xu_reset_2_complete => pc_xu_reset_2_complete, + pc_xu_reset_3_complete => pc_xu_reset_3_complete, + ac_tc_reset_1_request => ac_tc_reset_1_request, + ac_tc_reset_2_request => ac_tc_reset_2_request, + ac_tc_reset_3_request => ac_tc_reset_3_request, + ac_tc_reset_wd_request => ac_tc_reset_wd_request, + + -- Err Inject + pc_xu_inj_llbust_attempt => pc_xu_inj_llbust_attempt, + pc_xu_inj_llbust_failed => pc_xu_inj_llbust_failed, + pc_xu_inj_wdt_reset => pc_xu_inj_wdt_reset, + xu_pc_err_wdt_reset => xu_pc_err_wdt_reset, + + -- Parity + pc_xu_inj_sprg_ecc => pc_xu_inj_sprg_ecc, + xu_pc_err_sprg_ecc => xu_pc_err_sprg_ecc, + xu_pc_err_sprg_ue => xu_pc_err_sprg_ue, + + -- SPRs + spr_msr_cm => xu_msr_cm, + spr_msr_gs => xu_msr_gs, + spr_msr_pr => xu_msr_pr, + spr_msr_is => xu_msr_is, + spr_msr_ds => xu_msr_ds, + spr_ccr2_en_dcr => xu_iu_spr_ccr2_en_dcr, + spr_ccr2_notlb => spr_ccr2_notlb, + spr_ccr2_en_ditc => xu_bx_ccr2_en_ditc, + xu_lsu_spr_xucr0_dcdis => xu_lsu_spr_xucr0_dcdis, + xu_lsu_spr_xucr0_rel => xu_iu_xucr0_rel, + xu_pc_spr_ccr0_pme => xu_pc_spr_ccr0_pme, + xu_iu_spr_ccr2_ifratsc => xu_iu_spr_ccr2_ifratsc, + xu_iu_spr_ccr2_ifrat => xu_iu_spr_ccr2_ifrat, + spr_xucr0_clkg_ctl_b0 => spr_xucr0_clkg_ctl_b0, + xu_mm_spr_epcr_dmiuh => xu_mm_spr_epcr_dmiuh, + xu_mm_spr_epcr_dgtmi => xu_mm_spr_epcr_dgtmi, + cpl_msr_gs => cpl_msr_gs, + cpl_msr_pr => cpl_msr_pr, + cpl_msr_fp => cpl_msr_fp, + cpl_msr_spv => cpl_msr_spv, + cpl_ccr2_ap => cpl_ccr2_ap, + spr_xucr4_mmu_mchk => spr_xucr4_mmu_mchk, + + -- G8T ABIST Control + an_ac_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc, + ac_tc_machine_check => ac_tc_machine_check, + pc_xu_abist_g8t_wenb => pc_xu_abist_g8t_wenb, + pc_xu_abist_g8t1p_renb_0 => pc_xu_abist_g8t1p_renb_0, + pc_xu_abist_g8t_bw_1 => pc_xu_abist_g8t_bw_1, + pc_xu_abist_g8t_bw_0 => pc_xu_abist_g8t_bw_0, + pc_xu_abist_wl32_comp_ena => pc_xu_abist_wl32_comp_ena, + pc_xu_abist_g8t_dcomp => pc_xu_abist_g8t_dcomp, + + vcs => vcs, + vdd => vdd, + gnd => gnd, + nclk => nclk, + an_ac_coreid => an_ac_coreid, + spr_pvr_version_dc => spr_pvr_version_dc, + spr_pvr_revision_dc => spr_pvr_revision_dc, + an_ac_atpg_en_dc => an_ac_atpg_en_dc, + an_ac_ext_interrupt => an_ac_ext_interrupt, + an_ac_crit_interrupt => an_ac_crit_interrupt, + an_ac_perf_interrupt => an_ac_perf_interrupt, + an_ac_reservation_vld => an_ac_reservation_vld, + an_ac_tb_update_pulse => an_ac_tb_update_pulse, + an_ac_hang_pulse => an_ac_hang_pulse, + an_ac_tb_update_enable => an_ac_tb_update_enable, + an_ac_sleep_en => an_ac_sleep_en, + an_ac_grffence_en_dc => an_ac_grffence_en_dc, + + -- Pervasive + func_scan_in => func_scan_in(35 to 58), + func_scan_out => func_scan_out(35 to 58), + gptr_scan_in => ctlspr_gptr_scan_in, + gptr_scan_out => ctlspr_gptr_scan_out, + bcfg_scan_in => bcfg_scan_in, + bcfg_scan_out => bcfg_scan_out, + dcfg_scan_in => dcfg_scan_in, + dcfg_scan_out => dcfg_scan_out, + ccfg_scan_in => ccfg_scan_in, + ccfg_scan_out => ccfg_scan_out, + regf_scan_in => regf_scan_in, + regf_scan_out => regf_scan_out, + time_scan_in => ctlspr_time_scan_in, + time_scan_out => ctlspr_time_scan_out, + abst_scan_in(0) => abst_scan_in(0), + abst_scan_in(1) => abst_scan_in(2), + abst_scan_out(0) => abst_scan_out(0), + abst_scan_out(1) => abst_scan_2, + repr_scan_in => ctlspr_repr_scan_in, + repr_scan_out => ctlspr_repr_scan_out +); + +-- ########################################################################################## +-- FXUA/DATA +-- ########################################################################################## + +fxadat : entity work.xuq_fxua_data(xuq_fxua_data) +generic map( + expand_type => expand_type, + regmode => regmode, + dc_size => dc_size, + cl_size => cl_size, + l_endian_m => l_endian_m, + threads => threads, + eff_ifar => eff_ifar, + regsize => regsize, + a2mode => a2mode, + hvmode => hvmode, + real_data_add => real_data_add) +port map( + + --------------------------------------------------------------------- + -- Pervasive + --------------------------------------------------------------------- + pc_xu_abist_raddr_0 => pc_xu_abist_raddr_0(1 to 9), + pc_xu_abist_raddr_1 => pc_xu_abist_raddr_1(2 to 9), + pc_xu_abist_grf_renb_0 => pc_xu_abist_grf_renb_0, + pc_xu_abist_grf_renb_1 => pc_xu_abist_grf_renb_1, + pc_xu_abist_ena_dc => pc_xu_abist_ena_dc, + pc_xu_abist_waddr_0 => pc_xu_abist_waddr_0(2 to 9), + pc_xu_abist_waddr_1 => pc_xu_abist_waddr_1(2 to 9), + pc_xu_abist_grf_wenb_0 => pc_xu_abist_grf_wenb_0, + pc_xu_abist_grf_wenb_1 => pc_xu_abist_grf_wenb_1, + pc_xu_abist_di_0 => pc_xu_abist_di_0, + pc_xu_abist_di_1 => pc_xu_abist_di_1, + pc_xu_abist_wl144_comp_ena => pc_xu_abist_wl144_comp_ena, + pc_xu_abist_raw_dc_b => pc_xu_abist_raw_dc_b, + pc_xu_ccflush_dc => pc_xu_ccflush_dc, + clkoff_dc_b => clkoff_dc_b, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc(4 to 4), + mpw1_dc_b => mpw1_dc_b(4 to 4), + mpw2_dc_b => mpw2_dc_b, + g6t_clkoff_dc_b => g6t_clkoff_dc_b, + g6t_d_mode_dc => g6t_d_mode_dc, + g6t_delay_lclkr_dc => g6t_delay_lclkr_dc, + g6t_mpw1_dc_b => g6t_mpw1_dc_b, + g6t_mpw2_dc_b => g6t_mpw2_dc_b, + an_ac_scan_diag_dc => an_ac_scan_diag_dc, + an_ac_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc, + sg_2 => sg_2(0 to 2), + fce_2 => fce_2(0 to 0), + func_sl_thold_2 => func_sl_thold_2, + func_nsl_thold_2 => func_nsl_thold_2, + abst_sl_thold_2 => abst_sl_thold_2, + time_sl_thold_2 => time_sl_thold_2, + ary_nsl_thold_2 => ary_nsl_thold_2, + repr_sl_thold_2 => repr_sl_thold_2, + gptr_sl_thold_2 => gptr_sl_thold_2, + bolt_sl_thold_2 => bolt_sl_thold_2, + bo_enable_2 => bo_enable_2, + pc_xu_bo_unload => pc_xu_bo_unload, + pc_xu_bo_load => pc_xu_bo_load, + pc_xu_bo_repair => pc_xu_bo_repair, + pc_xu_bo_reset => pc_xu_bo_reset, + pc_xu_bo_shdata => pc_xu_bo_shdata, + pc_xu_bo_select => pc_xu_bo_select(5 to 8), + xu_pc_bo_fail => xu_pc_bo_fail(5 to 8), + xu_pc_bo_diagout => xu_pc_bo_diagout(5 to 8), + + --------------------------------------------------------------------- + -- Interface with IU + --------------------------------------------------------------------- + iu_xu_is2_vld => iu_xu_is2_vld, + iu_xu_is2_ifar => iu_xu_is2_ifar, + iu_xu_is2_tid => iu_xu_is2_tid, + iu_xu_is2_instr => iu_xu_is2_instr, + iu_xu_is2_ta_vld => iu_xu_is2_ta_vld, + iu_xu_is2_ta => iu_xu_is2_ta, + iu_xu_is2_s1_vld => iu_xu_is2_s1_vld, + iu_xu_is2_s1 => iu_xu_is2_s1, + iu_xu_is2_s2_vld => iu_xu_is2_s2_vld, + iu_xu_is2_s2 => iu_xu_is2_s2, + iu_xu_is2_s3_vld => iu_xu_is2_s3_vld, + iu_xu_is2_s3 => iu_xu_is2_s3, + iu_xu_is2_axu_ld_or_st => iu_xu_is2_axu_ld_or_st, + iu_xu_is2_axu_store => iu_xu_is2_axu_store, + iu_xu_is2_axu_ldst_size => iu_xu_is2_axu_ldst_size, + iu_xu_is2_axu_ldst_update => iu_xu_is2_axu_ldst_update, + iu_xu_is2_axu_ldst_forcealign => iu_xu_is2_axu_ldst_forcealign, + iu_xu_is2_axu_ldst_forceexcept => iu_xu_is2_axu_ldst_forceexcept, + iu_xu_is2_axu_ldst_extpid => iu_xu_is2_axu_ldst_extpid, + iu_xu_is2_axu_ldst_indexed => iu_xu_is2_axu_ldst_indexed, + iu_xu_is2_axu_ldst_tag => iu_xu_is2_axu_ldst_tag, + iu_xu_is2_axu_mftgpr => iu_xu_is2_axu_mftgpr, + iu_xu_is2_axu_mffgpr => iu_xu_is2_axu_mffgpr, + iu_xu_is2_axu_movedp => iu_xu_is2_axu_movedp, + iu_xu_is2_axu_instr_type => iu_xu_is2_axu_instr_type, + iu_xu_is2_pred_update => iu_xu_is2_pred_update, + iu_xu_is2_pred_taken_cnt => iu_xu_is2_pred_taken_cnt, + iu_xu_is2_error => iu_xu_is2_error, + iu_xu_is2_match => iu_xu_is2_match, + iu_xu_is2_is_ucode => iu_xu_is2_is_ucode, + iu_xu_is2_ucode_vld => iu_xu_is2_ucode_vld, + iu_xu_is2_gshare => iu_xu_is2_gshare, + xu_iu_multdiv_done => xu_iu_multdiv_done, + xu_iu_membar_tid => xu_iu_membar_tid, + + --------------------------------------------------------------------- + -- Interface with LSU + --------------------------------------------------------------------- + lsu_xu_ldq_barr_done => lsu_xu_ldq_barr_done, + lsu_xu_barr_done => lsu_xu_barr_done, + + --------------------------------------------------------------------- + -- Interface with FXU B + --------------------------------------------------------------------- + fxa_fxb_rf0_val => fxa_fxb_rf0_val, + fxa_fxb_rf0_issued => fxa_fxb_rf0_issued, + fxa_fxb_rf0_ucode_val => fxa_fxb_rf0_ucode_val, + fxa_fxb_rf0_act => fxa_fxb_rf0_act, + fxa_fxb_ex1_hold_ctr_flush => fxa_fxb_ex1_hold_ctr_flush, + fxa_fxb_rf0_instr => fxa_fxb_rf0_instr, + fxa_fxb_rf0_tid => fxa_fxb_rf0_tid, + fxa_fxb_rf0_ta_vld => fxa_fxb_rf0_ta_vld, + fxa_fxb_rf0_ta => fxa_fxb_rf0_ta, + fxa_fxb_rf0_error => fxa_fxb_rf0_error, + fxa_fxb_rf0_match => fxa_fxb_rf0_match, + fxa_fxb_rf0_is_ucode => fxa_fxb_rf0_is_ucode, + fxa_fxb_rf0_gshare => fxa_fxb_rf0_gshare, + fxa_fxb_rf0_ifar => fxa_fxb_rf0_ifar, + fxa_fxb_rf0_s1_vld => fxa_fxb_rf0_s1_vld, + fxa_fxb_rf0_s1 => fxa_fxb_rf0_s1, + fxa_fxb_rf0_s2_vld => fxa_fxb_rf0_s2_vld, + fxa_fxb_rf0_s2 => fxa_fxb_rf0_s2, + fxa_fxb_rf0_s3_vld => fxa_fxb_rf0_s3_vld, + fxa_fxb_rf0_s3 => fxa_fxb_rf0_s3, + fxa_fxb_rf0_axu_instr_type => fxa_fxb_rf0_axu_instr_type, + fxa_fxb_rf0_axu_ld_or_st => fxa_fxb_rf0_axu_ld_or_st, + fxa_fxb_rf0_axu_store => fxa_fxb_rf0_axu_store, + fxa_fxb_rf0_axu_mftgpr => fxa_fxb_rf0_axu_mftgpr, + fxa_fxb_rf0_axu_mffgpr => fxa_fxb_rf0_axu_mffgpr, + fxa_fxb_rf0_axu_movedp => fxa_fxb_rf0_axu_movedp, + fxa_fxb_rf0_axu_ldst_size => fxa_fxb_rf0_axu_ldst_size, + fxa_fxb_rf0_axu_ldst_update => fxa_fxb_rf0_axu_ldst_update, + fxa_fxb_rf0_axu_ldst_forcealign => fxa_fxb_rf0_axu_ldst_forcealign, + fxa_fxb_rf0_axu_ldst_forceexcept => fxa_fxb_rf0_axu_ldst_forceexcept, + fxa_fxb_rf0_axu_ldst_indexed => fxa_fxb_rf0_axu_ldst_indexed, + fxa_fxb_rf0_axu_ldst_tag => fxa_fxb_rf0_axu_ldst_tag, + fxa_fxb_rf0_pred_update => fxa_fxb_rf0_pred_update, + fxa_fxb_rf0_pred_taken_cnt => fxa_fxb_rf0_pred_taken_cnt, + fxa_fxb_rf0_mc_dep_chk_val => fxa_fxb_rf0_mc_dep_chk_val, + fxa_fxb_rf1_mul_val => fxa_fxb_rf1_mul_val, + fxa_fxb_rf1_muldiv_coll => fxa_fxb_rf1_muldiv_coll, + fxa_fxb_rf1_div_val => fxa_fxb_rf1_div_val, + fxa_fxb_rf1_div_ctr => fxa_fxb_rf1_div_ctr, + fxa_fxb_rf0_xu_epid_instr => fxa_fxb_rf0_xu_epid_instr, + fxa_fxb_rf0_axu_is_extload => fxa_fxb_rf0_axu_is_extload, + fxa_fxb_rf0_axu_is_extstore => fxa_fxb_rf0_axu_is_extstore, + fxa_fxb_rf0_spr_tid => fxa_fxb_rf0_spr_tid, + fxa_fxb_rf0_cpl_tid => fxa_fxb_rf0_cpl_tid, + fxa_fxb_rf0_cpl_act => fxa_fxb_rf0_cpl_act, + fxa_fxb_rf0_is_mfocrf => fxa_fxb_rf0_is_mfocrf, + fxa_fxb_rf0_3src_instr => fxa_fxb_rf0_3src_instr, + fxa_fxb_rf0_gpr0_zero => fxa_fxb_rf0_gpr0_zero, + fxa_fxb_rf0_use_imm => fxa_fxb_rf0_use_imm, + dec_cpl_ex3_mc_dep_chk_val => dec_cpl_ex3_mc_dep_chk_val, + fxb_fxa_ex7_we0 => fxb_fxa_ex7_we0, + fxb_fxa_ex7_wa0 => fxb_fxa_ex7_wa0, + fxb_fxa_ex7_wd0 => fxb_fxa_ex7_wd0, + fxa_fxb_rf1_do0 => fxa_fxb_rf1_do0, + fxa_fxb_rf1_do1 => fxa_fxb_rf1_do1, + fxa_fxb_rf1_do2 => fxa_fxb_rf1_do2, + fxb_fxa_ex6_clear_barrier => fxb_fxa_ex6_clear_barrier, + fxa_perf_muldiv_in_use => fxa_perf_muldiv_in_use, + + --------------------------------------------------------------------- + -- Flushes + --------------------------------------------------------------------- + xu_is2_flush => is2_flush, + xu_rf0_flush => rf0_flush, + xu_rf1_flush => rf1_flush, + xu_ex1_flush => ex1_flush, + xu_ex2_flush => ex2_flush, + xu_ex3_flush => ex3_flush, + xu_ex4_flush => ex4_flush, + xu_ex5_flush => ex5_flush, + fxa_cpl_ex2_div_coll => fxa_cpl_ex2_div_coll, + cpl_fxa_ex5_set_barr => cpl_fxa_ex5_set_barr, + fxa_iu_set_barr_tid => fxa_iu_set_barr_tid, + spr_xucr4_div_barr_thres => spr_xucr4_div_barr_thres, + + --------------------------------------------------------------------- + -- ICSWX + --------------------------------------------------------------------- + an_ac_back_inv => an_ac_back_inv, + an_ac_back_inv_addr => an_ac_back_inv_addr(62 to 63), + an_ac_back_inv_target_bit3 => an_ac_back_inv_target_bit3, + + --------------------------------------------------------------------- + -- Interface with SPR + --------------------------------------------------------------------- + dec_spr_rf0_instr => dec_spr_rf0_instr, + + --------------------------------------------------------------------- + -- Parity + --------------------------------------------------------------------- + pc_xu_inj_regfile_parity => pc_xu_inj_regfile_parity, + xu_pc_err_regfile_parity => xu_pc_err_regfile_parity, + xu_pc_err_regfile_ue => xu_pc_err_regfile_ue, + gpr_cpl_ex3_regfile_err_det => gpr_cpl_ex3_regfile_err_det, + cpl_gpr_regfile_seq_beg => cpl_gpr_regfile_seq_beg, + gpr_cpl_regfile_seq_end => gpr_cpl_regfile_seq_end, + + --------------------------------------------------------------------- + -- Interface with LSU + --------------------------------------------------------------------- + xu_lsu_rf0_derat_val => xu_lsu_rf0_derat_val, + xu_lsu_rf0_derat_is_extload => xu_lsu_rf0_derat_is_extload, + xu_lsu_rf0_derat_is_extstore => xu_lsu_rf0_derat_is_extstore, + lsu_xu_rel_wren => lsu_xu_rel_wren, + lsu_xu_rel_ta_gpr => lsu_xu_rel_ta_gpr, + fxa_cpl_debug => fxa_cpl_debug, + + -- Execution Pipe + xu_lsu_rf1_data_act => xu_lsu_rf1_data_act, + xu_lsu_rf1_axu_ldst_falign => xu_lsu_rf1_axu_ldst_falign, + xu_lsu_ex1_store_data => xu_lsu_ex1_store_data, + xu_lsu_ex1_eff_addr => xu_lsu_ex1_eff_addr, + xu_lsu_ex1_rotsel_ovrd => xu_lsu_ex1_rotsel_ovrd, + ex1_optype1 => ex1_optype1, + ex1_optype2 => ex1_optype2, + ex1_optype4 => ex1_optype4, + ex1_optype8 => ex1_optype8, + ex1_optype16 => ex1_optype16, + ex1_optype32 => ex1_optype32, + ex1_saxu_instr => ex1_saxu_instr, + ex1_sdp_instr => ex1_sdp_instr, + ex1_stgpr_instr => ex1_stgpr_instr, + ex1_store_instr => ex1_store_instr, + ex1_axu_op_val => ex1_axu_op_val, + + fu_xu_ex2_store_data_val => fu_xu_ex2_store_data_val, + fu_xu_ex2_store_data => fu_xu_ex2_store_data, + + ex3_algebraic => ex3_algebraic, + ex3_data_swap => ex3_data_swap, + ex3_thrd_id => ex3_thrd_id, + bx_xu_ex5_dp_data => bx_xu_ex5_dp_data, + + -- Debug Data Compare + ex4_load_op_hit => ex4_load_op_hit, + ex4_store_hit => ex4_store_hit, + ex4_axu_op_val => ex4_axu_op_val, + spr_dvc1_act => spr_dvc1_act, + spr_dvc2_act => spr_dvc2_act, + spr_dvc1_dbg => spr_dvc1_dbg, + spr_dvc2_dbg => spr_dvc2_dbg, + + -- Update Data Array Valid + rel_upd_dcarr_val => rel_upd_dcarr_val, + + -- Instruction Flush + xu_lsu_ex4_flush_local => xu_lsu_ex4_flush_local, + + -- Error Inject + xu_pc_err_dcache_parity => xu_pc_err_dcache_parity, + pc_xu_inj_dcache_parity => pc_xu_inj_dcache_parity, + + -- Config Bits + xu_lsu_spr_xucr0_dcdis => xu_lsu_spr_xucr0_dcdis, + spr_xucr0_clkg_ctl_b0 => spr_xucr0_clkg_ctl_b0, + + -- Reload Pipe + ldq_rel_data_val_early => ldq_rel_data_val_early, + ldq_rel_op_size => ldq_rel_op_size, + ldq_rel_addr => ldq_rel_addr, + ldq_rel_data_val => ldq_rel_data_val, + ldq_rel_rot_sel => ldq_rel_rot_sel, + ldq_rel_axu_val => ldq_rel_axu_val, + ldq_rel_ci => ldq_rel_ci, + ldq_rel_thrd_id => ldq_rel_thrd_id, + ldq_rel_le_mode => ldq_rel_le_mode, + ldq_rel_algebraic => ldq_rel_algebraic, + ldq_rel_256_data => ldq_rel_256_data, + ldq_rel_dvc1_en => ldq_rel_dvc1_en, + ldq_rel_dvc2_en => ldq_rel_dvc2_en, + ldq_rel_beat_crit_qw => ldq_rel_beat_crit_qw, + ldq_rel_beat_crit_qw_block => ldq_rel_beat_crit_qw_block, + + -- Data Cache Update + dcarr_up_way_addr => dcarr_up_way_addr, + + -- Execution Pipe Outputs + ex4_256st_data => ex4_256st_data, + ex6_ld_par_err => ex6_ld_par_err, + lsu_xu_ex6_datc_par_err => lsu_xu_ex6_datc_par_err, + + --Rotated Data + ex6_xu_ld_data_b => lsu_xu_rot_ex6_data_b, + rel_xu_ld_data => lsu_xu_rot_rel_data, + xu_fu_ex6_load_data => xu_fu_ex6_load_data, + xu_fu_ex5_load_le => xu_fu_ex5_load_le, + + -- Debug Data Compare + lsu_xu_ex2_dvc1_st_cmp => lsu_xu_ex2_dvc1_st_cmp, + lsu_xu_ex2_dvc2_st_cmp => lsu_xu_ex2_dvc2_st_cmp, + lsu_xu_ex8_dvc1_ld_cmp => lsu_xu_ex8_dvc1_ld_cmp, + lsu_xu_ex8_dvc2_ld_cmp => lsu_xu_ex8_dvc2_ld_cmp, + lsu_xu_rel_dvc_thrd_id => lsu_xu_rel_dvc_thrd_id, + lsu_xu_rel_dvc1_en => lsu_xu_rel_dvc1_en, + lsu_xu_rel_dvc1_cmp => lsu_xu_rel_dvc1_cmp, + lsu_xu_rel_dvc2_en => lsu_xu_rel_dvc2_en, + lsu_xu_rel_dvc2_cmp => lsu_xu_rel_dvc2_cmp, + + -- Debug Bus IO + pc_xu_trace_bus_enable => pc_xu_trace_bus_enable, + lsudat_debug_mux_ctrls => lsudat_debug_mux_ctrls, + lsu_xu_data_debug0 => lsu_xu_data_debug0, + lsu_xu_data_debug1 => lsu_xu_data_debug1, + lsu_xu_data_debug2 => lsu_xu_data_debug2, + + --pervasive + vdd => vdd, + gnd => gnd, + vcs => vcs, + nclk => nclk, + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b, + + -- G6T ABIST Control + pc_xu_abist_g6t_bw => pc_xu_abist_g6t_bw, + pc_xu_abist_di_g6t_2r => pc_xu_abist_di_g6t_2r, + pc_xu_abist_wl512_comp_ena => pc_xu_abist_wl512_comp_ena, + pc_xu_abist_dcomp_g6t_2r => pc_xu_abist_dcomp_g6t_2r, + pc_xu_abist_g6t_r_wb => pc_xu_abist_g6t_r_wb, + + -- SCAN Ports + gptr_scan_in => fxadat_gptr_scan_in, + gptr_scan_out => fxadat_gptr_scan_out, + abst_scan_in(0) => abst_scan_in(1), + abst_scan_in(1) => abst_scan_2, + abst_scan_out(0) => abst_scan_out(1), + abst_scan_out(1) => abst_scan_out(2), + repr_scan_in => fxadat_repr_scan_in, + time_scan_in => fxadat_time_scan_in, + func_scan_in => func_scan_in(31 to 34), + repr_scan_out => fxadat_repr_scan_out, + time_scan_out => fxadat_time_scan_out, + func_scan_out => func_scan_out(31 to 34) +); + + +ctlspr_time_scan_in <= fxadat_time_scan_out; +ctlspr_repr_scan_in <= fxadat_repr_scan_out; +ctlspr_gptr_scan_in <= fxadat_gptr_scan_out; +fxadat_time_scan_in <= time_scan_in; +fxadat_repr_scan_in <= repr_scan_in; +fxadat_gptr_scan_in <= gptr_scan_in; +time_scan_out <= ctlspr_time_scan_out; +repr_scan_out <= ctlspr_repr_scan_out; +gptr_scan_out <= ctlspr_gptr_scan_out; +xu_bx_ex4_256st_data <= ex4_256st_data(128 to 255); + +mark_unused(delay_lclkr_dc(0 to 3)); +mark_unused(mpw1_dc_b(0 to 3)); +mark_unused(sg_2(3)); +mark_unused(fce_2(1)); +mark_unused(func_slp_sl_thold_2); +mark_unused(cfg_sl_thold_2); +mark_unused(cfg_slp_sl_thold_2); +mark_unused(regf_slp_sl_thold_2); +mark_unused(pc_xu_abist_raddr_1(0 to 1)); +mark_unused(pc_xu_abist_waddr_1(0 to 1)); +mark_unused(pc_xu_abist_raddr_0(0)); +mark_unused(pc_xu_abist_waddr_0(0 to 1)); + + +end xuq; diff --git a/rel/src/vhdl/work/xuq_add.vhdl b/rel/src/vhdl/work/xuq_add.vhdl new file mode 100644 index 0000000..578e2c4 --- /dev/null +++ b/rel/src/vhdl/work/xuq_add.vhdl @@ -0,0 +1,270 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + +entity xuq_add is +generic( expand_type : integer := 2 ); -- 0 - ibm tech, 1 - other ); +port( + x_b :in std_ulogic_vector(0 to 63) ; -- after xor + y_b :in std_ulogic_vector(0 to 63) ; + ci :in std_ulogic_vector(8 to 8) ; + + sum :out std_ulogic_vector(0 to 63); + cout_32 :out std_ulogic ; + cout_0 :out std_ulogic +); + + +end xuq_add; -- ENTITY + +architecture xuq_add of xuq_add is + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal g01, g01_b :std_ulogic_vector(0 to 63); + signal t01, t01_b :std_ulogic_vector(0 to 63); + signal sum_0, sum_1 :std_ulogic_vector(0 to 63); + signal g08 :std_ulogic_vector(0 to 7); + signal t08 :std_ulogic_vector(0 to 7); + signal c64_b :std_ulogic_vector(0 to 7); + signal cout_32x , cout_32y_b :std_ulogic; + signal ci_cp1_lv1_b , ci_cp1_lv2 , ci_cp1_lv3_b , ci_cp1_lv4 :std_ulogic; + signal ci_cp2_lv2 , ci_cp2_lv3_b :std_ulogic; + + +begin + + + +u_ci_11: ci_cp1_lv1_b <= not ci(8) ; -- x2 +u_ci_12: ci_cp1_lv2 <= not ci_cp1_lv1_b ; -- x2 +u_ci_13: ci_cp1_lv3_b <= not ci_cp1_lv2 ; -- x3 +u_ci_14: ci_cp1_lv4 <= not ci_cp1_lv3_b ; -- x4 + +u_ci_22: ci_cp2_lv2 <= not ci_cp1_lv1_b ; -- x2 +u_ci_23: ci_cp2_lv3_b <= not ci_cp2_lv2 ; -- x3 + + +--//################################################## +--//## pgt +--//################################################## + + u_g01: g01(0 to 63) <= not( x_b(0 to 63) or y_b(0 to 63) ); + u_t01: t01(0 to 63) <= not( x_b(0 to 63) and y_b(0 to 63) ); + u_g01b: g01_b(0 to 63) <= not g01(0 to 63); -- small, buffer off + u_t01b: t01_b(0 to 63) <= not t01(0 to 63); -- small, buffer off + + +--//################################################## +--//## local part of byte group +--//################################################## + + loc_0: entity work.xuq_add_loc(xuq_add_loc) port map( + g01_b(0 to 7) => g01_b(0 to 7) ,--i-- + t01_b(0 to 7) => t01_b(0 to 7) ,--i-- + sum_0(0 to 7) => sum_0(0 to 7) ,--o-- + sum_1(0 to 7) => sum_1(0 to 7) );--o-- + + loc_1: entity work.xuq_add_loc(xuq_add_loc) port map( + g01_b(0 to 7) => g01_b(8 to 15) ,--i-- + t01_b(0 to 7) => t01_b(8 to 15) ,--i-- + sum_0(0 to 7) => sum_0(8 to 15) ,--o-- + sum_1(0 to 7) => sum_1(8 to 15) );--o-- + + loc_2: entity work.xuq_add_loc(xuq_add_loc) port map( + g01_b(0 to 7) => g01_b(16 to 23) ,--i-- + t01_b(0 to 7) => t01_b(16 to 23) ,--i-- + sum_0(0 to 7) => sum_0(16 to 23) ,--o-- + sum_1(0 to 7) => sum_1(16 to 23) );--o-- + + loc_3: entity work.xuq_add_loc(xuq_add_loc) port map( + g01_b(0 to 7) => g01_b(24 to 31) ,--i-- + t01_b(0 to 7) => t01_b(24 to 31) ,--i-- + sum_0(0 to 7) => sum_0(24 to 31) ,--o-- + sum_1(0 to 7) => sum_1(24 to 31) );--o-- + + loc_4: entity work.xuq_add_loc(xuq_add_loc) port map( + g01_b(0 to 7) => g01_b(32 to 39) ,--i-- + t01_b(0 to 7) => t01_b(32 to 39) ,--i-- + sum_0(0 to 7) => sum_0(32 to 39) ,--o-- + sum_1(0 to 7) => sum_1(32 to 39) );--o-- + + loc_5: entity work.xuq_add_loc(xuq_add_loc) port map( + g01_b(0 to 7) => g01_b(40 to 47) ,--i-- + t01_b(0 to 7) => t01_b(40 to 47) ,--i-- + sum_0(0 to 7) => sum_0(40 to 47) ,--o-- + sum_1(0 to 7) => sum_1(40 to 47) );--o-- + + loc_6: entity work.xuq_add_loc(xuq_add_loc) port map( + g01_b(0 to 7) => g01_b(48 to 55) ,--i-- + t01_b(0 to 7) => t01_b(48 to 55) ,--i-- + sum_0(0 to 7) => sum_0(48 to 55) ,--o-- + sum_1(0 to 7) => sum_1(48 to 55) );--o-- + + loc_7: entity work.xuq_add_loc(xuq_add_loc) port map( + g01_b(0 to 7) => g01_b(56 to 63) ,--i-- + t01_b(0 to 7) => t01_b(56 to 63) ,--i-- + sum_0(0 to 7) => sum_0(56 to 63) ,--o-- + sum_1(0 to 7) => sum_1(56 to 63) );--o-- + + +--//################################################## +--//## local part of global carry +--//################################################## + + gclc_0: entity work.xuq_add_glbloc(xuq_add_glbloc) port map( + g01(0 to 7) => g01(0 to 7) ,--i-- + t01(0 to 7) => t01(0 to 7) ,--i-- + g08 => g08(0) ,--o-- + t08 => t08(0) );--o-- + + gclc_1: entity work.xuq_add_glbloc(xuq_add_glbloc) port map( + g01(0 to 7) => g01(8 to 15) ,--i-- + t01(0 to 7) => t01(8 to 15) ,--i-- + g08 => g08(1) ,--o-- + t08 => t08(1) );--o-- + + gclc_2: entity work.xuq_add_glbloc(xuq_add_glbloc) port map( + g01(0 to 7) => g01(16 to 23) ,--i-- + t01(0 to 7) => t01(16 to 23) ,--i-- + g08 => g08(2) ,--o-- + t08 => t08(2) );--o-- + + gclc_3: entity work.xuq_add_glbloc(xuq_add_glbloc) port map( + g01(0 to 7) => g01(24 to 31) ,--i-- + t01(0 to 7) => t01(24 to 31) ,--i-- + g08 => g08(3) ,--o-- + t08 => t08(3) );--o-- + + gclc_4: entity work.xuq_add_glbloc(xuq_add_glbloc) port map( + g01(0 to 7) => g01(32 to 39) ,--i-- + t01(0 to 7) => t01(32 to 39) ,--i-- + g08 => g08(4) ,--o-- + t08 => t08(4) );--o-- + + gclc_5: entity work.xuq_add_glbloc(xuq_add_glbloc) port map( + g01(0 to 7) => g01(40 to 47) ,--i-- + t01(0 to 7) => t01(40 to 47) ,--i-- + g08 => g08(5) ,--o-- + t08 => t08(5) );--o-- + + gclc_6: entity work.xuq_add_glbloc(xuq_add_glbloc) port map( + g01(0 to 7) => g01(48 to 55) ,--i-- + t01(0 to 7) => t01(48 to 55) ,--i-- + g08 => g08(6) ,--o-- + t08 => t08(6) );--o-- + + gclc_7: entity work.xuq_add_glbloc(xuq_add_glbloc) port map( + g01(0 to 7) => g01(56 to 63) ,--i-- + t01(0 to 7) => t01(56 to 63) ,--i-- + g08 => g08(7) ,--o-- + t08 => t08(7) );--o-- + + +--//################################################## +--//## global part of global carry +--//################################################## + + gc: entity work.xuq_add_glbglbci(xuq_add_glbglbci) port map( + g08(0 to 7) => g08(0 to 7) ,--i-- + t08(0 to 7) => t08(0 to 7) ,--i-- + ci => ci_cp1_lv4 ,--i-- + c64_b(0 to 7) => c64_b(0 to 7) );--o-- + + u_c32x: cout_32x <= not c64_b(4) ; --(small) + u_c32y: cout_32y_b <= not cout_32x ; + u_c32: cout_32 <= not cout_32y_b ; --output-- + + u_c64: cout_0 <= not c64_b(0) ; --output-- --rename-- + +--//################################################## +--//## final mux +--//################################################## + + fm_0: entity work.xuq_add_csmux(xuq_add_csmux) port map( + ci_b => c64_b(1) ,--i-- + sum_0(0 to 7) => sum_0(0 to 7) ,--i-- + sum_1(0 to 7) => sum_1(0 to 7) ,--i-- + sum (0 to 7) => sum (0 to 7) );--o-- + + fm_1: entity work.xuq_add_csmux(xuq_add_csmux) port map( + ci_b => c64_b(2) ,--i-- + sum_0(0 to 7) => sum_0(8 to 15) ,--i-- + sum_1(0 to 7) => sum_1(8 to 15) ,--i-- + sum (0 to 7) => sum (8 to 15) );--o-- + + fm_2: entity work.xuq_add_csmux(xuq_add_csmux) port map( + ci_b => c64_b(3) ,--i-- + sum_0(0 to 7) => sum_0(16 to 23) ,--i-- + sum_1(0 to 7) => sum_1(16 to 23) ,--i-- + sum (0 to 7) => sum (16 to 23) );--o-- + + fm_3: entity work.xuq_add_csmux(xuq_add_csmux) port map( + ci_b => c64_b(4) ,--i-- + sum_0(0 to 7) => sum_0(24 to 31) ,--i-- + sum_1(0 to 7) => sum_1(24 to 31) ,--i-- + sum (0 to 7) => sum (24 to 31) );--o-- + + fm_4: entity work.xuq_add_csmux(xuq_add_csmux) port map( + ci_b => c64_b(5) ,--i-- + sum_0(0 to 7) => sum_0(32 to 39) ,--i-- + sum_1(0 to 7) => sum_1(32 to 39) ,--i-- + sum (0 to 7) => sum (32 to 39) );--o-- + + fm_5: entity work.xuq_add_csmux(xuq_add_csmux) port map( + ci_b => c64_b(6) ,--i-- + sum_0(0 to 7) => sum_0(40 to 47) ,--i-- + sum_1(0 to 7) => sum_1(40 to 47) ,--i-- + sum (0 to 7) => sum (40 to 47) );--o-- + + fm_6: entity work.xuq_add_csmux(xuq_add_csmux) port map( + ci_b => c64_b(7) ,--i-- + sum_0(0 to 7) => sum_0(48 to 55) ,--i-- + sum_1(0 to 7) => sum_1(48 to 55) ,--i-- + sum (0 to 7) => sum (48 to 55) );--o-- + + fm_7: entity work.xuq_add_csmux(xuq_add_csmux) port map( + ci_b => ci_cp2_lv3_b ,--i-- + sum_0(0 to 7) => sum_0(56 to 63) ,--i-- + sum_1(0 to 7) => sum_1(56 to 63) ,--i-- + sum (0 to 7) => sum (56 to 63) );--o-- + +end; -- xuq_add ARCHITECTURE + diff --git a/rel/src/vhdl/work/xuq_add_csmux.vhdl b/rel/src/vhdl/work/xuq_add_csmux.vhdl new file mode 100644 index 0000000..86399d3 --- /dev/null +++ b/rel/src/vhdl/work/xuq_add_csmux.vhdl @@ -0,0 +1,93 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; use ieee.std_logic_1164.all ; +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + +-- input phase is important +-- (change X (B) by switching xor/xnor ) + +entity xuq_add_csmux is port( + sum_0 :in std_ulogic_vector(0 to 7) ; -- after xor + sum_1 :in std_ulogic_vector(0 to 7) ; + ci_b :in std_ulogic ; + sum :out std_ulogic_vector(0 to 7) + ); +END xuq_add_csmux; + + +ARCHITECTURE xuq_add_csmux OF xuq_add_csmux IS + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal sum0_b, sum1_b :std_ulogic_vector(0 to 7); + signal int_ci, int_ci_t, int_ci_b :std_ulogic; + + +BEGIN + + u_ci: int_ci <= not ci_b; + u_cit: int_ci_t <= not ci_b; + u_cib: int_ci_b <= not int_ci_t; + + u_sum0_0: sum0_b(0) <= not( sum_0(0) and int_ci_b ); + u_sum0_1: sum0_b(1) <= not( sum_0(1) and int_ci_b ); + u_sum0_2: sum0_b(2) <= not( sum_0(2) and int_ci_b ); + u_sum0_3: sum0_b(3) <= not( sum_0(3) and int_ci_b ); + u_sum0_4: sum0_b(4) <= not( sum_0(4) and int_ci_b ); + u_sum0_5: sum0_b(5) <= not( sum_0(5) and int_ci_b ); + u_sum0_6: sum0_b(6) <= not( sum_0(6) and int_ci_b ); + u_sum0_7: sum0_b(7) <= not( sum_0(7) and int_ci_b ); + + u_sum1_0: sum1_b(0) <= not( sum_1(0) and int_ci ); + u_sum1_1: sum1_b(1) <= not( sum_1(1) and int_ci ); + u_sum1_2: sum1_b(2) <= not( sum_1(2) and int_ci ); + u_sum1_3: sum1_b(3) <= not( sum_1(3) and int_ci ); + u_sum1_4: sum1_b(4) <= not( sum_1(4) and int_ci ); + u_sum1_5: sum1_b(5) <= not( sum_1(5) and int_ci ); + u_sum1_6: sum1_b(6) <= not( sum_1(6) and int_ci ); + u_sum1_7: sum1_b(7) <= not( sum_1(7) and int_ci ); + + u_sum_0: sum(0) <= not( sum0_b(0) and sum1_b(0) ); + u_sum_1: sum(1) <= not( sum0_b(1) and sum1_b(1) ); + u_sum_2: sum(2) <= not( sum0_b(2) and sum1_b(2) ); + u_sum_3: sum(3) <= not( sum0_b(3) and sum1_b(3) ); + u_sum_4: sum(4) <= not( sum0_b(4) and sum1_b(4) ); + u_sum_5: sum(5) <= not( sum0_b(5) and sum1_b(5) ); + u_sum_6: sum(6) <= not( sum0_b(6) and sum1_b(6) ); + u_sum_7: sum(7) <= not( sum0_b(7) and sum1_b(7) ); + + +END; -- ARCH xuq_add_csmux diff --git a/rel/src/vhdl/work/xuq_add_glbglbci.vhdl b/rel/src/vhdl/work/xuq_add_glbglbci.vhdl new file mode 100644 index 0000000..eace10d --- /dev/null +++ b/rel/src/vhdl/work/xuq_add_glbglbci.vhdl @@ -0,0 +1,242 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; use ieee.std_logic_1164.all ; +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + +-- input phase is important +-- (change X (B) by switching xor/xnor ) + +entity xuq_add_glbglbci is port( + g08 :in std_ulogic_vector(0 to 7) ; + t08 :in std_ulogic_vector(0 to 7) ; + ci :in std_ulogic ; + c64_b :out std_ulogic_vector(0 to 7) + ); +END xuq_add_glbglbci; + + +ARCHITECTURE xuq_add_glbglbci OF xuq_add_glbglbci IS + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal b0_g16_b :std_ulogic_vector(0 to 3); + signal b0_t16_b :std_ulogic_vector(0 to 2); + signal b0_g32 :std_ulogic_vector(0 to 1); + signal b0_t32 :std_ulogic_vector(0 to 0); + signal b1_g16_b :std_ulogic_vector(0 to 3); + signal b1_t16_b :std_ulogic_vector(0 to 2); + signal b1_g32 :std_ulogic_vector(0 to 1); + signal b1_t32 :std_ulogic_vector(0 to 0); + signal b2_g16_b :std_ulogic_vector(0 to 3); + signal b2_t16_b :std_ulogic_vector(0 to 2); + signal b2_g32 :std_ulogic_vector(0 to 1); + signal b2_t32 :std_ulogic_vector(0 to 0); + signal b3_g16_b :std_ulogic_vector(0 to 3); + signal b3_t16_b :std_ulogic_vector(0 to 2); + signal b3_g32 :std_ulogic_vector(0 to 1); + signal b3_t32 :std_ulogic_vector(0 to 0); + signal b4_g16_b :std_ulogic_vector(0 to 3); + signal b4_t16_b :std_ulogic_vector(0 to 2); + signal b4_g32 :std_ulogic_vector(0 to 1); + signal b4_t32 :std_ulogic_vector(0 to 0); + signal b5_g16_b :std_ulogic_vector(0 to 2); + signal b5_t16_b :std_ulogic_vector(0 to 1); + signal b5_g32 :std_ulogic_vector(0 to 1); + signal b5_t32 :std_ulogic_vector(0 to 0); + signal b6_g16_b :std_ulogic_vector(0 to 1); + signal b6_t16_b :std_ulogic_vector(0 to 0); + signal b6_g32 :std_ulogic_vector(0 to 0); + signal b7_g16_b :std_ulogic_vector(0 to 0); + signal b7_g32 :std_ulogic_vector(0 to 0); + signal b0_g56_b, b0_c64 :std_ulogic ; + signal g08_b, t08_b :std_ulogic_vector(0 to 0) ; + + + +BEGIN + + --//############################# + --//## byte 0 addr_sel_64 ,--i-- + addr_nsel => addr_nsel_64 ,--i-- + addr(0 to 7) => snoop_addr(0 to 7) ,--i-- + x_b(0 to 7) => x_b(0 to 7) ,--i-- + y_b(0 to 7) => y_b(0 to 7) ,--i-- + sum_0(0 to 7) => sum_0(0 to 7) ,--o-- + sum_1(0 to 7) => sum_1(0 to 7) );--o-- + + loc_1: entity work.xuq_agen_loca(xuq_agen_loca) port map( + addr_sel => addr_sel_64 ,--i-- + addr_nsel => addr_nsel_64 ,--i-- + addr(0 to 7) => snoop_addr(8 to 15) ,--i-- + x_b(0 to 7) => x_b(8 to 15) ,--i-- + y_b(0 to 7) => y_b(8 to 15) ,--i-- + sum_0(0 to 7) => sum_0(8 to 15) ,--o-- + sum_1(0 to 7) => sum_1(8 to 15) );--o-- + + loc_2: entity work.xuq_agen_loca(xuq_agen_loca) port map( + addr_sel => addr_sel_64 ,--i-- + addr_nsel => addr_nsel_64 ,--i-- + addr(0 to 7) => snoop_addr(16 to 23) ,--i-- + x_b(0 to 7) => x_b(16 to 23) ,--i-- + y_b(0 to 7) => y_b(16 to 23) ,--i-- + sum_0(0 to 7) => sum_0(16 to 23) ,--o-- + sum_1(0 to 7) => sum_1(16 to 23) );--o-- + + loc_3: entity work.xuq_agen_loca(xuq_agen_loca) port map( + addr_sel => addr_sel_64 ,--i-- + addr_nsel => addr_nsel_64 ,--i-- + addr(0 to 7) => snoop_addr(24 to 31) ,--i-- + x_b(0 to 7) => x_b(24 to 31) ,--i-- + y_b(0 to 7) => y_b(24 to 31) ,--i-- + sum_0(0 to 7) => sum_0(24 to 31) ,--o-- + sum_1(0 to 7) => sum_1(24 to 31) );--o-- + + loc_4: entity work.xuq_agen_loca(xuq_agen_loca) port map( + addr_sel => addr_sel ,--i-- + addr_nsel => addr_nsel ,--i-- + addr(0 to 7) => snoop_addr(32 to 39) ,--i-- + x_b(0 to 7) => x_b(32 to 39) ,--i-- + y_b(0 to 7) => y_b(32 to 39) ,--i-- + sum_0(0 to 7) => sum_0(32 to 39) ,--o-- + sum_1(0 to 7) => sum_1(32 to 39) );--o-- + + loc_5: entity work.xuq_agen_loca(xuq_agen_loca) port map( + addr_sel => addr_sel ,--i-- + addr_nsel => addr_nsel ,--i-- + addr(0 to 7) => snoop_addr(40 to 47) ,--i-- + x_b(0 to 7) => x_b(40 to 47) ,--i-- + y_b(0 to 7) => y_b(40 to 47) ,--i-- + sum_0(0 to 7) => sum_0(40 to 47) ,--o-- + sum_1(0 to 7) => sum_1(40 to 47) );--o-- + + loc_6: entity work.xuq_agen_locae(xuq_agen_locae) port map( + addr_sel => addr_sel ,--i-- + addr_nsel => addr_nsel ,--i-- + addr(0 to 3) => snoop_addr(48 to 51) ,--i-- + x_b(0 to 7) => x_b(48 to 55) ,--i-- + y_b(0 to 7) => y_b(48 to 55) ,--i-- + sum_0(0 to 3) => sum_0(48 to 51) ,--o-- + sum_1(0 to 3) => sum_1(48 to 51) );--o-- + + +--//################################################## +--//## local part of global carry +--//################################################## + + gclc_1: entity work.xuq_agen_glbloc(xuq_agen_glbloc) port map( + x_b(0 to 7) => x_b(8 to 15) ,--i-- + y_b(0 to 7) => y_b(8 to 15) ,--i-- + g08 => g08(1) ,--o-- + t08 => t08(1) );--o-- + + gclc_2: entity work.xuq_agen_glbloc(xuq_agen_glbloc) port map( + x_b(0 to 7) => x_b(16 to 23) ,--i-- + y_b(0 to 7) => y_b(16 to 23) ,--i-- + g08 => g08(2) ,--o-- + t08 => t08(2) );--o-- + + gclc_3: entity work.xuq_agen_glbloc(xuq_agen_glbloc) port map( + x_b(0 to 7) => x_b(24 to 31) ,--i-- + y_b(0 to 7) => y_b(24 to 31) ,--i-- + g08 => g08(3) ,--o-- + t08 => t08(3) );--o-- + + gclc_4: entity work.xuq_agen_glbloc(xuq_agen_glbloc) port map( + x_b(0 to 7) => x_b(32 to 39) ,--i-- + y_b(0 to 7) => y_b(32 to 39) ,--i-- + g08 => g08(4) ,--o-- + t08 => t08(4) );--o-- + + gclc_5: entity work.xuq_agen_glbloc(xuq_agen_glbloc) port map( + x_b(0 to 7) => x_b(40 to 47) ,--i-- + y_b(0 to 7) => y_b(40 to 47) ,--i-- + g08 => g08(5) ,--o-- + t08 => t08(5) );--o-- + + gclc_6: entity work.xuq_agen_glbloc(xuq_agen_glbloc) port map( + x_b(0 to 7) => x_b(48 to 55) ,--i-- + y_b(0 to 7) => y_b(48 to 55) ,--i-- + g08 => g08(6) ,--o-- + t08 => t08(6) );--o-- + + gclc_7: entity work.xuq_agen_glbloc_lsb(xuq_agen_glbloc_lsb) port map( + x_b(0 to 7) => x_b(56 to 63) ,--i-- + y_b(0 to 7) => y_b(56 to 63) ,--i-- + g08 => g08(7) );--o-- +-- t08 => t08(7) );--o-- + + +--//################################################## +--//## global part of global carry {replicate ending of global carry vertical) +--//################################################## + + gc: entity work.xuq_agen_glbglb(xuq_agen_glbglb) port map( + g08(1 to 7) => g08(1 to 7) ,--i-- + t08(1 to 6) => t08(1 to 6) ,--i-- + c64_b(1 to 7) => c64_b(1 to 7) );--o-- + + + +--//################################################## +--//## final mux (vertical) +--//################################################## + + fm_0: entity work.xuq_agen_csmux(xuq_agen_csmux) port map( + ci_b => c64_b(1) ,--i-- + sum_0(0 to 7) => sum_0 (0 to 7) ,--i-- + sum_1(0 to 7) => sum_1 (0 to 7) ,--i-- + sum (0 to 7) => sum_int (0 to 7) );--o-- + + fm_1: entity work.xuq_agen_csmux(xuq_agen_csmux) port map( + ci_b => c64_b(2) ,--i-- + sum_0(0 to 7) => sum_0 (8 to 15) ,--i-- + sum_1(0 to 7) => sum_1 (8 to 15) ,--i-- + sum (0 to 7) => sum_int (8 to 15) );--o-- + + fm_2: entity work.xuq_agen_csmux(xuq_agen_csmux) port map( + ci_b => c64_b(3) ,--i-- + sum_0(0 to 7) => sum_0 (16 to 23) ,--i-- + sum_1(0 to 7) => sum_1 (16 to 23) ,--i-- + sum (0 to 7) => sum_int (16 to 23) );--o-- + + fm_3: entity work.xuq_agen_csmux(xuq_agen_csmux) port map( + ci_b => c64_b(4) ,--i-- + sum_0(0 to 7) => sum_0 (24 to 31) ,--i-- + sum_1(0 to 7) => sum_1 (24 to 31) ,--i-- + sum (0 to 7) => sum_int (24 to 31) );--o-- + + fm_4: entity work.xuq_agen_csmux(xuq_agen_csmux) port map( + ci_b => c64_b(5) ,--i-- + sum_0(0 to 7) => sum_0 (32 to 39) ,--i-- + sum_1(0 to 7) => sum_1 (32 to 39) ,--i-- + sum (0 to 7) => sum_int (32 to 39) );--o-- + + fm_5: entity work.xuq_agen_csmux(xuq_agen_csmux) port map( + ci_b => c64_b(6) ,--i-- + sum_0(0 to 7) => sum_0 (40 to 47) ,--i-- + sum_1(0 to 7) => sum_1 (40 to 47) ,--i-- + sum (0 to 7) => sum_int (40 to 47) );--o-- + + + fm_6: entity work.xuq_agen_csmuxe(xuq_agen_csmuxe) port map( -- just the 4 msb of the byte go to erat + ci_b => c64_b(7) ,--i-- + sum_0(0 to 3) => sum_0 (48 to 51) ,--i-- + sum_1(0 to 3) => sum_1 (48 to 51) ,--i-- + sum (0 to 3) => sum_int (48 to 51) );--o-- + + kog: entity work.xuq_agen_lo(xuq_agen_lo) port map( -- 12 lsbs are for the DIRECTORY + dir_ig_57_b => dir_ig_57_b ,--i--xuq_agen_lo(kog) // force dir addr 57 to "1" + x_b (0 to 11) => x_b (52 to 63) ,--i--xuq_agen_lo(kog) + y_b (0 to 11) => y_b (52 to 63) ,--i--xuq_agen_lo(kog) + sum (0 to 11) => sum_non_erat(52 to 63) ,--o--xuq_agen_lo(kog) // for the compares etc + sum_arr(1 to 5) => sum_arr (53 to 57) );--o--xuq_agen_lo(kog) // for the array address + + + u_non_b: sum_non_erat_b(0 to 51) <= not( sum_int(0 to 51) ); + u_non: sum_non_erat (0 to 51) <= not( sum_non_erat_b(0 to 51) ); + + sum(0 to 51) <= sum_int(0 to 51) ; --rename-- to ERAT only + + + -- ################################### + -- # repower network for directory + -- ################################### + + + u_sum_lv1_1: sum_arr_lv1_1_b(53 to 57) <= not( sum_arr (53 to 57) ); -- 4x + u_sum_lv2_0: sum_arr_dir01(53 to 57) <= not( sum_arr_lv1_1_b(53 to 57) ); -- 4x --output-- + u_sum_lv2_1: sum_arr_dir45(53 to 57) <= not( sum_arr_lv1_1_b(53 to 57) ); -- 4x --output-- + + + u_sum_lv1_0: sum_arr_lv1_0_b(53 to 57) <= not( sum_arr (53 to 57) ); -- 6x + u_sum_lv2_2: sum_arr_dir23(53 to 57) <= not( sum_arr_lv1_0_b(53 to 57) ); -- 4x --output-- + u_sum_lv2_3: sum_arr_dir67(53 to 57) <= not( sum_arr_lv1_0_b(53 to 57) ); -- 4x --output-- + + + -- ###################################################################### + -- ## this experimental piece is for directory read/write collisions + -- ###################################################################### + -- it is a multi-mode 4 or 5 bit compare + + agcmp: entity work.xuq_agen_cmp(xuq_agen_cmp) port map( -- 11 lsbs are for the DIRECTORY + x_b(53 to 63) => x_b(53 to 63) ,--i--agcmp-- + y_b(53 to 63) => y_b(53 to 63) ,--i--agcmp-- + z (53 to 57) => z (53 to 57) ,--i--agcmp-- (compare data) + inv1_val_b => inv1_val_b ,--i--agcmp-- + ex1_cache_acc_b => ex1_cache_acc_b ,--i--agamp-- + dir_ig_57_b => dir_ig_57_b ,--i--agcmp-- + rel3_val => rel3_val ,--i--agcmp-- + way(0 to 7) => way(0 to 7) ,--i--agcmp-- + ary_write_act_01 => ary_write_act_01 ,--o--agcmp-- + ary_write_act_23 => ary_write_act_23 ,--o--agcmp-- + ary_write_act_45 => ary_write_act_45 ,--o--agcmp-- + ary_write_act_67 => ary_write_act_67 ,--o--agcmp-- + ary_write_act => ary_write_act , + match_oth => match_oth ,--o--agcmp-- for other uses + vdd => vdd , + gnd => gnd); + + +end; -- xuq_agen ARCHITECTURE diff --git a/rel/src/vhdl/work/xuq_agen_cmp.vhdl b/rel/src/vhdl/work/xuq_agen_cmp.vhdl new file mode 100644 index 0000000..8a12727 --- /dev/null +++ b/rel/src/vhdl/work/xuq_agen_cmp.vhdl @@ -0,0 +1,321 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee,ibm,support,tri, work; + use ieee.std_logic_1164.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; +library clib ; + +-- ####################################################### +-- ## want equivalence to (A[53:63] + B[53:63]) => sum[53:63] , then sum[53:57] == z[53:57] +-- ## this is all complicated by another mode for sum[53:56] == z[53:56] +-- ## +-- ## the short cut is to compute (A+B-C)=="00000" / (A+B-c)=="0000" +-- ## it is a shortcut because you substitute a 3:2 compressor delay for a 12 bit adder delay +-- ## since there are more bits in (A+B) than C, there needs to be a carry-in to the compare +-- ####################################################### + +-- 0(53) 1(54) 2(55) 3(56) 4(57) 5(58) 6(59) 7(60) 8(61) 9(62) 10(63) + +entity xuq_agen_cmp is port( + x_b :in std_ulogic_vector(53 to 63) ; + y_b :in std_ulogic_vector(53 to 63) ; + z :in std_ulogic_vector(53 to 57) ; + + inv1_val_b :in std_ulogic; + ex1_cache_acc_b :in std_ulogic; + dir_ig_57_b :in std_ulogic; -- when this is low , bit 57 becomes "1" . + rel3_val :in std_ulogic; + way :in std_ulogic_vector(0 to 7); + + ary_write_act_01 :out std_ulogic ; + ary_write_act_23 :out std_ulogic ; + ary_write_act_45 :out std_ulogic ; + ary_write_act_67 :out std_ulogic ; + ary_write_act :out std_ulogic_vector(0 to 3); + + match_oth :out std_ulogic ; + vdd :inout power_logic; + gnd :inout power_logic + ); + + +END xuq_agen_cmp; + + +ARCHITECTURE xuq_agen_cmp OF xuq_agen_cmp IS + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal unused_car :std_ulogic; + signal sum :std_ulogic_vector(0 to 4); + signal car :std_ulogic_vector(0 to 3); + + signal x :std_ulogic_vector(0 to 4); + signal y :std_ulogic_vector(0 to 4); + signal z_b :std_ulogic_vector(0 to 4); + + signal g1 :std_ulogic_vector(4 to 10); + signal t1 :std_ulogic_vector(4 to 9); + + + signal g_4_b :std_ulogic; + signal g_4e :std_ulogic; + signal t_4e_b :std_ulogic; + signal t_4e :std_ulogic; + signal g_5t7_0_b :std_ulogic; + signal g_5t7_1_b :std_ulogic; + signal g_5t7_2_b :std_ulogic; + signal g_5t7 :std_ulogic; + signal t_5t7_b :std_ulogic; + signal t_5t7 :std_ulogic; + signal g_8t10_0_b :std_ulogic; + signal g_8t10_1_b :std_ulogic; + signal g_8t10_2_b :std_ulogic; + signal g_8t10 :std_ulogic; + signal g_4t10_0_b :std_ulogic; + signal g_4t10_1_b :std_ulogic; + signal g_4t10_2_b :std_ulogic; + signal g_4t10 :std_ulogic; + + + signal dir_ig_57 :std_ulogic; + signal xorcmp :std_ulogic_vector(0 to 3); + signal ulp_0_b :std_ulogic; + signal ulp_1_b :std_ulogic; + signal ulp :std_ulogic; + signal enable_part :std_ulogic; + signal gp1_a_b :std_ulogic; + signal gp2_a_b :std_ulogic; + signal gp12_a :std_ulogic; + signal gp3 :std_ulogic; + signal match_arr_b :std_ulogic; + signal match :std_ulogic; + + signal rel3_val_01 :std_ulogic; + signal rel3_val_23 :std_ulogic; + signal rel3_val_45 :std_ulogic; + signal rel3_val_67 :std_ulogic; + + signal match_lv0_i0 :std_ulogic; + signal match_lv1_i0_b :std_ulogic; + signal match_lv1_i1_b :std_ulogic; + signal ary_write_act_01_b :std_ulogic; + signal ary_write_act_45_b :std_ulogic; + signal ary_write_act_23_b :std_ulogic; + signal ary_write_act_67_b :std_ulogic; + + signal ary_write_act_cpy :std_ulogic_vector(0 to 3); + +BEGIN + + dir_ig_57 <= not dir_ig_57_b ; + + --########################################################################### + --# dont want too put too much loads on the input (slows down rest of agen) + --########################################################################### + + u_x1_0: x(0) <= not x_b(53) ; + u_x1_1: x(1) <= not x_b(54) ; + u_x1_2: x(2) <= not x_b(55) ; + u_x1_3: x(3) <= not x_b(56) ; + u_x1_4: x(4) <= not x_b(57) ; + + u_y1_0: y(0) <= not y_b(53) ; + u_y1_1: y(1) <= not y_b(54) ; + u_y1_2: y(2) <= not y_b(55) ; + u_y1_3: y(3) <= not y_b(56) ; + u_y1_4: y(4) <= not y_b(57) ; + + u_z1_0: z_b(0) <= not( z(53) ); + u_z1_1: z_b(1) <= not( z(54) ); + u_z1_2: z_b(2) <= not( z(55) ); + u_z1_3: z_b(3) <= not( z(56) ); + u_z1_4: z_b(4) <= not( z(57) ); + + u_g1_4: g1(4) <= not( x_b(57) or y_b(57) ); + u_g1_5: g1(5) <= not( x_b(58) or y_b(58) ); + u_g1_6: g1(6) <= not( x_b(59) or y_b(59) ); + u_g1_7: g1(7) <= not( x_b(60) or y_b(60) ); + u_g1_8: g1(8) <= not( x_b(61) or y_b(61) ); + u_g1_9: g1(9) <= not( x_b(62) or y_b(62) ); + u_g1_10: g1(10) <= not( x_b(63) or y_b(63) ); + + u_t1_4: t1(4) <= not( x_b(57) and y_b(57) ); + u_t1_5: t1(5) <= not( x_b(58) and y_b(58) ); + u_t1_6: t1(6) <= not( x_b(59) and y_b(59) ); + u_t1_7: t1(7) <= not( x_b(60) and y_b(60) ); + u_t1_8: t1(8) <= not( x_b(61) and y_b(61) ); + u_t1_9: t1(9) <= not( x_b(62) and y_b(62) ); + + --################################################################################## + --# compressors (a+b-c ... sort of A+B+!C + 1 <== missing the +1 at this point + --################################################################################## + + + u_ac_csa_0: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => x(0) ,--i-- + b => y(0) ,--i-- + c => z_b(0) ,--i-- + sum => sum(0) ,--o-- + car => unused_car );--o-- + + u_ac_csa_1: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => x(1) ,--i-- + b => y(1) ,--i-- + c => z_b(1) ,--i-- + sum => sum(1) ,--o-- + car => car(0) );--o-- + + u_ac_csa_2: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => x(2) ,--i-- + b => y(2) ,--i-- + c => z_b(2) ,--i-- + sum => sum(2) ,--o-- + car => car(1) );--o-- + + u_ac_csa_3: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => x(3) ,--i-- + b => y(3) ,--i-- + c => z_b(3) ,--i-- + sum => sum(3) ,--o-- + car => car(2) );--o-- + + u_ac_csa_4: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => x(4) ,--i-- + b => y(4) ,--i-- + c => z_b(4) ,--i-- + sum => sum(4) ,--o-- + car => car(3) );--o-- + + + --#################################################################### + --# carry path (conditionally includes bit 4 <57> ) + --#################################################################### + + u_g_4: g_4_b <= not( g1(4) ); + u_g_4e: g_4e <= not( g_4_b or dir_ig_57_b); -- neg input and : g1(4) and !dir_ig_57 + u_t_4: t_4e_b <= not( t1(4) or dir_ig_57_b); -- t1(4) or dir_ig_57 + u_t_4e: t_4e <= not( t_4e_b ); + + u_g_5t7_0: g_5t7_0_b <= not( g1(5) ); + u_g_5t7_1: g_5t7_1_b <= not( t1(5) and g1(6) ); + u_g_5t7_2: g_5t7_2_b <= not( t1(5) and t1(6) and g1(7) ); + u_g_5t7: g_5t7 <= not( g_5t7_0_b and g_5t7_1_b and g_5t7_2_b ); + u_t_5t7_0: t_5t7_b <= not( t1(5) and t1(6) and t1(7) ); + u_t_5t7: t_5t7 <= not( t_5t7_b ); + + u_g_8t10_0: g_8t10_0_b <= not( g1(8) ); + u_g_8t10_1: g_8t10_1_b <= not( t1(8) and g1(9) ); + u_g_8t10_2: g_8t10_2_b <= not( t1(8) and t1(9) and g1(10) ); + u_g_8t10: g_8t10 <= not( g_8t10_0_b and g_8t10_1_b and g_8t10_2_b ); + + u_g_4t10_0: g_4t10_0_b <= not( g_4e ) ; + u_g_4t10_1: g_4t10_1_b <= not( t_4e and g_5t7 ) ; + u_g_4t10_2: g_4t10_2_b <= not( t_4e and t_5t7 and g_8t10 ) ; + u_g_4t10: g_4t10 <= not( g_4t10_0_b and g_4t10_1_b and g_4t10_2_b ); + + + --#################################################################### + --# combine it all + --#################################################################### + + + u_xorcmp_0: xorcmp(0) <= sum(0) xor car(0) ; + u_xorcmp_1: xorcmp(1) <= sum(1) xor car(1) ; + u_xorcmp_2: xorcmp(2) <= sum(2) xor car(2) ; + u_xorcmp_3: xorcmp(3) <= sum(3) xor car(3) ; + + u_ulp_0: ulp_0_b <= not( sum(3) and dir_ig_57 ); + u_ulp_1: ulp_1_b <= not( sum(4) and dir_ig_57_b ); + u_ulp: ulp <= not( ulp_0_b and ulp_1_b ); + + + u_en_part: enable_part <= not( inv1_val_b and ex1_cache_acc_b ); + + + u_gp1_a: gp1_a_b <= not( xorcmp(0) and xorcmp(1) and xorcmp(2) ); + u_gp2_a: gp2_a_b <= not( enable_part and ( xorcmp(3) or dir_ig_57 ) ); + u_gp12_a: gp12_a <= not( gp1_a_b or gp2_a_b ); + + u_gp3: gp3 <= ulp xor g_4t10 ; + + u_match_a: match_arr_b <= not( gp12_a and gp3 ); + u_match_i: match <= not( match_arr_b );--output-- small to buffer off + match_oth <= match ; --output-- rename + + -- ###################################################### + -- ## drive to the array pins + -- ###################################################### + + -- ARRAY positions --------------------- + -- array_01 array_45 + -- array_23 array_67 + + rel3_val_01 <= rel3_val and ( way(0) or way(1) ); + rel3_val_23 <= rel3_val and ( way(2) or way(3) ); + rel3_val_45 <= rel3_val and ( way(4) or way(5) ); + rel3_val_67 <= rel3_val and ( way(6) or way(7) ); + + + u_match_lv0_i0: match_lv0_i0 <= not( match_arr_b ); --6 + + u_match_lv1_i0: match_lv1_i0_b <= not( match_lv0_i0 ); --2 + u_match_lv1_i1: match_lv1_i1_b <= not( match_lv0_i0 ); --6 + + u_wact_01b: ary_write_act_01_b <= not( match_lv1_i0_b and rel3_val_01 ) ; --3 + u_wact_45b: ary_write_act_45_b <= not( match_lv1_i0_b and rel3_val_45 ) ; --3 + u_wact_23b: ary_write_act_23_b <= not( match_lv1_i1_b and rel3_val_23 ) ; --4 + u_wact_67b: ary_write_act_67_b <= not( match_lv1_i1_b and rel3_val_67 ) ; --4 + + u_wact_01: ary_write_act_01 <= not( ary_write_act_01_b ) ; --6 --output-- + u_wact_45: ary_write_act_45 <= not( ary_write_act_45_b ) ; --6 --output-- + u_wact_23: ary_write_act_23 <= not( ary_write_act_23_b ) ; --6 --output-- + u_wact_67: ary_write_act_67 <= not( ary_write_act_67_b ) ; --6 --output-- + + u_wact: ary_write_act_cpy <= not (ary_write_act_01_b & ary_write_act_23_b & ary_write_act_45_b & ary_write_act_67_b); + ary_write_act <= ary_write_act_cpy; +END; -- ARCH xuq_agen_cmp diff --git a/rel/src/vhdl/work/xuq_agen_csmux.vhdl b/rel/src/vhdl/work/xuq_agen_csmux.vhdl new file mode 100644 index 0000000..ab05331 --- /dev/null +++ b/rel/src/vhdl/work/xuq_agen_csmux.vhdl @@ -0,0 +1,95 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; use ieee.std_logic_1164.all ; +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + +-- input phase is important +-- (change X (B) by switching xor/xnor ) + +entity xuq_agen_csmux is port( + sum_0 :in std_ulogic_vector(0 to 7) ; -- after xor + sum_1 :in std_ulogic_vector(0 to 7) ; + ci_b :in std_ulogic ; + sum :out std_ulogic_vector(0 to 7) + ); + + +END xuq_agen_csmux; + + +ARCHITECTURE xuq_agen_csmux OF xuq_agen_csmux IS + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal sum0_b, sum1_b :std_ulogic_vector(0 to 7); + signal int_ci, int_ci_t, int_ci_b :std_ulogic; + + +BEGIN + + u_ci: int_ci <= not ci_b; + u_cit: int_ci_t <= not ci_b; + u_cib: int_ci_b <= not int_ci_t; + + u_sum0_0: sum0_b(0) <= not( sum_0(0) and int_ci_b ); + u_sum0_1: sum0_b(1) <= not( sum_0(1) and int_ci_b ); + u_sum0_2: sum0_b(2) <= not( sum_0(2) and int_ci_b ); + u_sum0_3: sum0_b(3) <= not( sum_0(3) and int_ci_b ); + u_sum0_4: sum0_b(4) <= not( sum_0(4) and int_ci_b ); + u_sum0_5: sum0_b(5) <= not( sum_0(5) and int_ci_b ); + u_sum0_6: sum0_b(6) <= not( sum_0(6) and int_ci_b ); + u_sum0_7: sum0_b(7) <= not( sum_0(7) and int_ci_b ); + + u_sum1_0: sum1_b(0) <= not( sum_1(0) and int_ci ); + u_sum1_1: sum1_b(1) <= not( sum_1(1) and int_ci ); + u_sum1_2: sum1_b(2) <= not( sum_1(2) and int_ci ); + u_sum1_3: sum1_b(3) <= not( sum_1(3) and int_ci ); + u_sum1_4: sum1_b(4) <= not( sum_1(4) and int_ci ); + u_sum1_5: sum1_b(5) <= not( sum_1(5) and int_ci ); + u_sum1_6: sum1_b(6) <= not( sum_1(6) and int_ci ); + u_sum1_7: sum1_b(7) <= not( sum_1(7) and int_ci ); + + u_sum_0: sum(0) <= not( sum0_b(0) and sum1_b(0) ); + u_sum_1: sum(1) <= not( sum0_b(1) and sum1_b(1) ); + u_sum_2: sum(2) <= not( sum0_b(2) and sum1_b(2) ); + u_sum_3: sum(3) <= not( sum0_b(3) and sum1_b(3) ); + u_sum_4: sum(4) <= not( sum0_b(4) and sum1_b(4) ); + u_sum_5: sum(5) <= not( sum0_b(5) and sum1_b(5) ); + u_sum_6: sum(6) <= not( sum0_b(6) and sum1_b(6) ); + u_sum_7: sum(7) <= not( sum0_b(7) and sum1_b(7) ); + + +END; -- ARCH xuq_agen_csmux diff --git a/rel/src/vhdl/work/xuq_agen_csmuxe.vhdl b/rel/src/vhdl/work/xuq_agen_csmuxe.vhdl new file mode 100644 index 0000000..f8a5ecb --- /dev/null +++ b/rel/src/vhdl/work/xuq_agen_csmuxe.vhdl @@ -0,0 +1,83 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; use ieee.std_logic_1164.all ; +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + +-- input phase is important +-- (change X (B) by switching xor/xnor ) + +entity xuq_agen_csmuxe is port( + sum_0 :in std_ulogic_vector(0 to 3) ; -- after xor + sum_1 :in std_ulogic_vector(0 to 3) ; + ci_b :in std_ulogic ; + sum :out std_ulogic_vector(0 to 3) + ); + + +END xuq_agen_csmuxe; + + +ARCHITECTURE xuq_agen_csmuxe OF xuq_agen_csmuxe IS + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal sum0_b, sum1_b :std_ulogic_vector(0 to 3); + signal int_ci, int_ci_t, int_ci_b :std_ulogic; + + +BEGIN + + u_ci: int_ci <= not ci_b; + u_cit: int_ci_t <= not ci_b; + u_cib: int_ci_b <= not int_ci_t; + + u_sum0_0: sum0_b(0) <= not( sum_0(0) and int_ci_b ); + u_sum0_1: sum0_b(1) <= not( sum_0(1) and int_ci_b ); + u_sum0_2: sum0_b(2) <= not( sum_0(2) and int_ci_b ); + u_sum0_3: sum0_b(3) <= not( sum_0(3) and int_ci_b ); + + u_sum1_0: sum1_b(0) <= not( sum_1(0) and int_ci ); + u_sum1_1: sum1_b(1) <= not( sum_1(1) and int_ci ); + u_sum1_2: sum1_b(2) <= not( sum_1(2) and int_ci ); + u_sum1_3: sum1_b(3) <= not( sum_1(3) and int_ci ); + + u_sum_0: sum(0) <= not( sum0_b(0) and sum1_b(0) ); + u_sum_1: sum(1) <= not( sum0_b(1) and sum1_b(1) ); + u_sum_2: sum(2) <= not( sum0_b(2) and sum1_b(2) ); + u_sum_3: sum(3) <= not( sum0_b(3) and sum1_b(3) ); + + +END; -- ARCH xuq_agen_csmuxe diff --git a/rel/src/vhdl/work/xuq_agen_glbglb.vhdl b/rel/src/vhdl/work/xuq_agen_glbglb.vhdl new file mode 100644 index 0000000..8e42f4d --- /dev/null +++ b/rel/src/vhdl/work/xuq_agen_glbglb.vhdl @@ -0,0 +1,210 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; use ieee.std_logic_1164.all ; +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + +-- input phase is important +-- (change X (B) by switching xor/xnor ) + +entity xuq_agen_glbglb is port( + g08 :in std_ulogic_vector(1 to 7) ; + t08 :in std_ulogic_vector(1 to 6) ; + c64_b :out std_ulogic_vector(1 to 7) + ); + + +END xuq_agen_glbglb; + + +ARCHITECTURE xuq_agen_glbglb OF xuq_agen_glbglb IS + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal b1_g16_b :std_ulogic_vector(0 to 3); + signal b1_t16_b :std_ulogic_vector(0 to 2); + signal b1_g32 :std_ulogic_vector(0 to 1); + signal b1_t32 :std_ulogic_vector(0 to 0); + signal b2_g16_b :std_ulogic_vector(0 to 3); + signal b2_t16_b :std_ulogic_vector(0 to 2); + signal b2_g32 :std_ulogic_vector(0 to 1); + signal b2_t32 :std_ulogic_vector(0 to 0); + signal b3_g16_b :std_ulogic_vector(0 to 3); + signal b3_t16_b :std_ulogic_vector(0 to 2); + signal b3_g32 :std_ulogic_vector(0 to 1); + signal b3_t32 :std_ulogic_vector(0 to 0); + signal b4_g16_b :std_ulogic_vector(0 to 3); + signal b4_t16_b :std_ulogic_vector(0 to 2); + signal b4_g32 :std_ulogic_vector(0 to 1); + signal b4_t32 :std_ulogic_vector(0 to 0); + signal b5_g16_b :std_ulogic_vector(0 to 2); + signal b5_t16_b :std_ulogic_vector(0 to 1); + signal b5_g32 :std_ulogic_vector(0 to 1); + signal b5_t32 :std_ulogic_vector(0 to 0); + signal b6_g16_b :std_ulogic_vector(0 to 1); + signal b6_t16_b :std_ulogic_vector(0 to 0); + signal b6_g32 :std_ulogic_vector(0 to 0); + signal b7_g16_b :std_ulogic_vector(0 to 0); + signal b7_g32 :std_ulogic_vector(0 to 0); + + +BEGIN + + + --//############################# + --//## byte 1 + --//############################# + + u1_g16_0: b1_g16_b(0) <= not( g08(1) or ( t08(1) and g08(2) ) ); + u1_g16_1: b1_g16_b(1) <= not( g08(3) or ( t08(3) and g08(4) ) ); + u1_g16_2: b1_g16_b(2) <= not( g08(5) or ( t08(5) and g08(6) ) ); + u1_g16_3: b1_g16_b(3) <= not( g08(7) ); + + u1_t16_0: b1_t16_b(0) <= not( t08(1) and t08(2) ); + u1_t16_1: b1_t16_b(1) <= not( t08(3) and t08(4) ); + u1_t16_2: b1_t16_b(2) <= not( t08(5) and t08(6) ); + + u1_g32_0: b1_g32(0) <= not( b1_g16_b(0) and ( b1_t16_b(0) or b1_g16_b(1) ) ) ; + u1_g32_1: b1_g32(1) <= not( b1_g16_b(2) and ( b1_t16_b(2) or b1_g16_b(3) ) ) ; + u1_t32_0: b1_t32(0) <= not( b1_t16_b(0) or b1_t16_b(1) ) ; + + u1_g64_0: c64_b(1) <= not( b1_g32(0) or (b1_t32(0) and b1_g32(1) ) ); --output-- + + + --//############################# + --//## byte 2 + --//############################# + + u2_g16_0: b2_g16_b(0) <= not( g08(2) or ( t08(2) and g08(3) ) ); + u2_g16_1: b2_g16_b(1) <= not( g08(4) or ( t08(4) and g08(5) ) ); + u2_g16_2: b2_g16_b(2) <= not( g08(6) ); + u2_g16_3: b2_g16_b(3) <= not( g08(7) ); + + u2_t16_0: b2_t16_b(0) <= not( t08(2) and t08(3) ); + u2_t16_1: b2_t16_b(1) <= not( t08(4) and t08(5) ); + u2_t16_2: b2_t16_b(2) <= not( t08(6) ); + + u2_g32_0: b2_g32(0) <= not( b2_g16_b(0) and ( b2_t16_b(0) or b2_g16_b(1) ) ) ; + u2_g32_1: b2_g32(1) <= not( b2_g16_b(2) and ( b2_t16_b(2) or b2_g16_b(3) ) ) ; + u2_t32_0: b2_t32(0) <= not( b2_t16_b(0) or b2_t16_b(1) ) ; + + u2_g64_0: c64_b(2) <= not( b2_g32(0) or (b2_t32(0) and b2_g32(1) ) ); --output-- + + + --//############################# + --//## byte 3 + --//############################# + + u3_g16_0: b3_g16_b(0) <= not( g08(3) or ( t08(3) and g08(4) ) ); + u3_g16_1: b3_g16_b(1) <= not( g08(5) ); + u3_g16_2: b3_g16_b(2) <= not( g08(6) ); + u3_g16_3: b3_g16_b(3) <= not( g08(7) ); + + u3_t16_0: b3_t16_b(0) <= not( t08(3) and t08(4) ); + u3_t16_1: b3_t16_b(1) <= not( t08(5) ); + u3_t16_2: b3_t16_b(2) <= not( t08(6) ); + + u3_g32_0: b3_g32(0) <= not( b3_g16_b(0) and ( b3_t16_b(0) or b3_g16_b(1) ) ) ; + u3_g32_1: b3_g32(1) <= not( b3_g16_b(2) and ( b3_t16_b(2) or b3_g16_b(3) ) ) ; + u3_t32_0: b3_t32(0) <= not( b3_t16_b(0) or b3_t16_b(1) ) ; + + u3_g64_0: c64_b(3) <= not( b3_g32(0) or (b3_t32(0) and b3_g32(1) ) ); --output-- + + + --//############################# + --//## byte 4 + --//############################# + + u4_g16_0: b4_g16_b(0) <= not( g08(4) ); + u4_g16_1: b4_g16_b(1) <= not( g08(5) ); + u4_g16_2: b4_g16_b(2) <= not( g08(6) ); + u4_g16_3: b4_g16_b(3) <= not( g08(7) ); + + u4_t16_0: b4_t16_b(0) <= not( t08(4) ); + u4_t16_1: b4_t16_b(1) <= not( t08(5) ); + u4_t16_2: b4_t16_b(2) <= not( t08(6) ); + + u4_g32_0: b4_g32(0) <= not( b4_g16_b(0) and ( b4_t16_b(0) or b4_g16_b(1) ) ) ; + u4_g32_1: b4_g32(1) <= not( b4_g16_b(2) and ( b4_t16_b(2) or b4_g16_b(3) ) ) ; + u4_t32_0: b4_t32(0) <= not( b4_t16_b(0) or b4_t16_b(1) ) ; + + u4_g64_0: c64_b(4) <= not( b4_g32(0) or (b4_t32(0) and b4_g32(1) ) ); --output-- + + + --//############################# + --//## byte 5 + --//############################# + + u5_g16_0: b5_g16_b(0) <= not( g08(5) ); + u5_g16_1: b5_g16_b(1) <= not( g08(6) ); + u5_g16_2: b5_g16_b(2) <= not( g08(7) ); + + u5_t16_0: b5_t16_b(0) <= not( t08(5) ); + u5_t16_1: b5_t16_b(1) <= not( t08(6) ); + + u5_g32_0: b5_g32(0) <= not( b5_g16_b(0) and ( b5_t16_b(0) or b5_g16_b(1) ) ) ; + u5_g32_1: b5_g32(1) <= not( b5_g16_b(2) ) ; + u5_t32_0: b5_t32(0) <= not( b5_t16_b(0) or b5_t16_b(1) ) ; + + u5_g64_0: c64_b(5) <= not( b5_g32(0) or (b5_t32(0) and b5_g32(1) ) ); --output-- + + + --//############################# + --//## byte 6 + --//############################# + + u6_g16_0: b6_g16_b(0) <= not( g08(6) ); + u6_g16_1: b6_g16_b(1) <= not( g08(7) ); + + u6_t16_0: b6_t16_b(0) <= not( t08(6) ); + + + u6_g32_0: b6_g32(0) <= not( b6_g16_b(0) and ( b6_t16_b(0) or b6_g16_b(1) ) ) ; + + + u6_g64_0: c64_b(6) <= not( b6_g32(0) ) ; --output-- + + --//############################# + --//## byte 7 + --//############################# + + u7_g16_0: b7_g16_b(0) <= not( g08(7) ); + + u7_g32_0: b7_g32(0) <= not( b7_g16_b(0) ); + + u7_g64_0: c64_b(7) <= not( b7_g32(0) ) ; --output-- + + +END; -- ARCH xuq_agen_glbglb diff --git a/rel/src/vhdl/work/xuq_agen_glbloc.vhdl b/rel/src/vhdl/work/xuq_agen_glbloc.vhdl new file mode 100644 index 0000000..20a606d --- /dev/null +++ b/rel/src/vhdl/work/xuq_agen_glbloc.vhdl @@ -0,0 +1,112 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; use ieee.std_logic_1164.all ; +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + +entity xuq_agen_glbloc is port( + x_b :in std_ulogic_vector(0 to 7) ; + y_b :in std_ulogic_vector(0 to 7) ; + g08 :out std_ulogic ; + t08 :out std_ulogic + ); + + +END xuq_agen_glbloc; + + +ARCHITECTURE xuq_agen_glbloc OF xuq_agen_glbloc IS + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal g01, t01 :std_ulogic_vector(0 to 7); + signal g02_b, t02_b :std_ulogic_vector(0 to 3); + signal g04, t04 :std_ulogic_vector(0 to 1); + signal g08_b, t08_b :std_ulogic; + + +BEGIN + + u_g01_0: g01(0) <= not( x_b(0) or y_b(0) ); + u_g01_1: g01(1) <= not( x_b(1) or y_b(1) ); + u_g01_2: g01(2) <= not( x_b(2) or y_b(2) ); + u_g01_3: g01(3) <= not( x_b(3) or y_b(3) ); + u_g01_4: g01(4) <= not( x_b(4) or y_b(4) ); + u_g01_5: g01(5) <= not( x_b(5) or y_b(5) ); + u_g01_6: g01(6) <= not( x_b(6) or y_b(6) ); + u_g01_7: g01(7) <= not( x_b(7) or y_b(7) ); + + u_t01_0: t01(0) <= not( x_b(0) and y_b(0) ); + u_t01_1: t01(1) <= not( x_b(1) and y_b(1) ); + u_t01_2: t01(2) <= not( x_b(2) and y_b(2) ); + u_t01_3: t01(3) <= not( x_b(3) and y_b(3) ); + u_t01_4: t01(4) <= not( x_b(4) and y_b(4) ); + u_t01_5: t01(5) <= not( x_b(5) and y_b(5) ); + u_t01_6: t01(6) <= not( x_b(6) and y_b(6) ); + u_t01_7: t01(7) <= not( x_b(7) and y_b(7) ); + + + u_g02_0: g02_b(0) <= not ( g01(0) or ( t01(0) and g01(1) ) ); + u_g02_1: g02_b(1) <= not ( g01(2) or ( t01(2) and g01(3) ) ); + u_g02_2: g02_b(2) <= not ( g01(4) or ( t01(4) and g01(5) ) ); + u_g02_3: g02_b(3) <= not ( g01(6) or ( t01(6) and g01(7) ) ); + + u_t02_0: t02_b(0) <= not ( t01(0) and t01(1) ) ; + u_t02_1: t02_b(1) <= not ( t01(2) and t01(3) ) ; + u_t02_2: t02_b(2) <= not ( t01(4) and t01(5) ) ; + u_t02_3: t02_b(3) <= not ( t01(6) and t01(7) ) ; + + + + u_g04_0: g04(0) <= not ( g02_b(0) and ( t02_b(0) or g02_b(1) ) ) ; + u_g04_1: g04(1) <= not ( g02_b(2) and ( t02_b(2) or g02_b(3) ) ) ; + + u_t04_0: t04(0) <= not ( t02_b(0) or t02_b(1) ) ; + u_t04_1: t04(1) <= not ( t02_b(2) or t02_b(3) ) ; + + + + u_g08_y: g08_b <= not ( g04(0) or ( t04(0) and g04(1) ) ) ; + + u_t08_y: t08_b <= not ( ( t04(0) and t04(1)) ) ; + + + + u_g08_x: g08 <= not ( g08_b ) ; -- output + + u_t08_x: t08 <= not ( t08_b ) ; -- output + +END; -- ARCH xuq_agen_glbloc diff --git a/rel/src/vhdl/work/xuq_agen_glbloc_lsb.vhdl b/rel/src/vhdl/work/xuq_agen_glbloc_lsb.vhdl new file mode 100644 index 0000000..7b87884 --- /dev/null +++ b/rel/src/vhdl/work/xuq_agen_glbloc_lsb.vhdl @@ -0,0 +1,104 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; use ieee.std_logic_1164.all ; +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + +entity xuq_agen_glbloc_lsb is port( + x_b :in std_ulogic_vector(0 to 7) ; + y_b :in std_ulogic_vector(0 to 7) ; + g08 :out std_ulogic + ); + + + +END xuq_agen_glbloc_lsb; + + +ARCHITECTURE xuq_agen_glbloc_lsb OF xuq_agen_glbloc_lsb IS + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal g01 :std_ulogic_vector(0 to 7); + signal t01 :std_ulogic_vector(0 to 6); + signal g02_b :std_ulogic_vector(0 to 3); + signal t02_b :std_ulogic_vector(0 to 2); + signal g04 :std_ulogic_vector(0 to 1); + signal t04 :std_ulogic_vector(0 to 0); + signal g08_b :std_ulogic; + + +BEGIN + + u_g01_0: g01(0) <= not( x_b(0) or y_b(0) ); + u_g01_1: g01(1) <= not( x_b(1) or y_b(1) ); + u_g01_2: g01(2) <= not( x_b(2) or y_b(2) ); + u_g01_3: g01(3) <= not( x_b(3) or y_b(3) ); + u_g01_4: g01(4) <= not( x_b(4) or y_b(4) ); + u_g01_5: g01(5) <= not( x_b(5) or y_b(5) ); + u_g01_6: g01(6) <= not( x_b(6) or y_b(6) ); + u_g01_7: g01(7) <= not( x_b(7) or y_b(7) ); + + u_t01_0: t01(0) <= not( x_b(0) and y_b(0) ); + u_t01_1: t01(1) <= not( x_b(1) and y_b(1) ); + u_t01_2: t01(2) <= not( x_b(2) and y_b(2) ); + u_t01_3: t01(3) <= not( x_b(3) and y_b(3) ); + u_t01_4: t01(4) <= not( x_b(4) and y_b(4) ); + u_t01_5: t01(5) <= not( x_b(5) and y_b(5) ); + u_t01_6: t01(6) <= not( x_b(6) and y_b(6) ); + + + u_g02_0: g02_b(0) <= not ( g01(0) or ( t01(0) and g01(1) ) ); + u_g02_1: g02_b(1) <= not ( g01(2) or ( t01(2) and g01(3) ) ); + u_g02_2: g02_b(2) <= not ( g01(4) or ( t01(4) and g01(5) ) ); + u_g02_3: g02_b(3) <= not ( g01(6) or ( t01(6) and g01(7) ) ); + + u_t02_0: t02_b(0) <= not ( t01(0) and t01(1) ) ; + u_t02_1: t02_b(1) <= not ( t01(2) and t01(3) ) ; + u_t02_2: t02_b(2) <= not ( t01(4) and t01(5) ) ; + + + + u_g04_0: g04(0) <= not ( g02_b(0) and ( t02_b(0) or g02_b(1) ) ) ; + u_g04_1: g04(1) <= not ( g02_b(2) and ( t02_b(2) or g02_b(3) ) ) ; + + u_t04_0: t04(0) <= not ( t02_b(0) or t02_b(1) ) ; + + u_g08_y: g08_b <= not ( g04(0) or ( t04(0) and g04(1) ) ) ; + u_g08_x: g08 <= not ( g08_b ) ; -- output + + +END; -- ARCH xuq_agen_glbloc_lsb diff --git a/rel/src/vhdl/work/xuq_agen_lo.vhdl b/rel/src/vhdl/work/xuq_agen_lo.vhdl new file mode 100644 index 0000000..93b48ae --- /dev/null +++ b/rel/src/vhdl/work/xuq_agen_lo.vhdl @@ -0,0 +1,197 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; use ieee.std_logic_1164.all ; +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + +-- input phase is important +-- (change X (B) by switching xor/xnor ) + +entity xuq_agen_lo is port( + x_b :in std_ulogic_vector(0 to 11) ; -- after xor + y_b :in std_ulogic_vector(0 to 11) ; + sum :out std_ulogic_vector(0 to 11) ; + sum_arr :out std_ulogic_vector(1 to 5) ; + dir_ig_57_b :in std_ulogic -- when this is low , bit 57 becomes "1" . + ); + + +END xuq_agen_lo; + + +ARCHITECTURE xuq_agen_lo OF xuq_agen_lo IS + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal p01_b, p01 :std_ulogic_vector(0 to 11); + signal g01 :std_ulogic_vector(1 to 11); + signal t01 :std_ulogic_vector(1 to 10); + signal sum_x, sum_b :std_ulogic_vector(0 to 11); + signal sum_x_11_b :std_ulogic; + signal g12_x_b, g02_b, g04 ,c :std_ulogic_vector(1 to 11); + signal g12_y_b :std_ulogic_vector(1 to 7); + signal g12_z_b :std_ulogic_vector(1 to 3); + signal t02_b :std_ulogic_vector(1 to 9); + signal t04 :std_ulogic_vector(1 to 7); + + +BEGIN + + --#################################################################### + --# propagate, generate, transmit + --#################################################################### + + u_g01: g01 (1 to 11) <= not( x_b(1 to 11) or y_b(1 to 11) ); + u_t01: t01 (1 to 10) <= not( x_b(1 to 10) and y_b(1 to 10) ); + u_p01b: p01_b(0 to 11) <= not( x_b(0 to 11) xor y_b(0 to 11) ); + u_p01: p01 (0 to 11) <= not( p01_b(0 to 11) ); + + --#################################################################### + --# final sum and drive + --#################################################################### + + u_sumx: sum_x(0 to 10) <= p01(0 to 10) xor c(1 to 11); + u_sumx11b: sum_x_11_b <= not( p01(11) ); + u_sumx11: sum_x(11) <= not( sum_x_11_b ); + + -- 00 01 02 03 04 05 06 07 08 09 10 11 + -- 52 53 54 55 56 57 58 59 60 61 62 63 + + u_sum_b: sum_b (0 to 11) <= not( sum_x(0 to 11) ); + u_sum: sum (0 to 11) <= not( sum_b(0 to 11) ); + u_sum_arr1: sum_arr(1) <= not( sum_b(1) ); + u_sum_arr2: sum_arr(2) <= not( sum_b(2) ); + u_sum_arr3: sum_arr(3) <= not( sum_b(3) ); + u_sum_arr4: sum_arr(4) <= not( sum_b(4) ); + u_sum_arr5: sum_arr(5) <= not( sum_b(5) and dir_ig_57_b ); -- OR with negative inputs + + --#################################################################### + --# carry path is cogge-stone + --#################################################################### + + + u_g02_1: g02_b( 1) <= not( g01( 1) or ( t01( 1) and g01( 2) ) ); + u_g02_2: g02_b( 2) <= not( g01( 2) or ( t01( 2) and g01( 3) ) ); + u_g02_3: g02_b( 3) <= not( g01( 3) or ( t01( 3) and g01( 4) ) ); + u_g02_4: g02_b( 4) <= not( g01( 4) or ( t01( 4) and g01( 5) ) ); + u_g02_5: g02_b( 5) <= not( g01( 5) or ( t01( 5) and g01( 6) ) ); + u_g02_6: g02_b( 6) <= not( g01( 6) or ( t01( 6) and g01( 7) ) ); + u_g02_7: g02_b( 7) <= not( g01( 7) or ( t01( 7) and g01( 8) ) ); + u_g02_8: g02_b( 8) <= not( g01( 8) or ( t01( 8) and g01( 9) ) ); + u_g02_9: g02_b( 9) <= not( g01( 9) or ( t01( 9) and g01(10) ) ); + u_g02_10: g02_b(10) <= not( g01(10) or ( t01(10) and g01(11) ) ); + u_g02_11: g02_b(11) <= not( g01(11) ); + + + u_t02_1: t02_b( 1) <= not( t01( 1) and t01( 2) ); + u_t02_2: t02_b( 2) <= not( t01( 2) and t01( 3) ); + u_t02_3: t02_b( 3) <= not( t01( 3) and t01( 4) ); + u_t02_4: t02_b( 4) <= not( t01( 4) and t01( 5) ); + u_t02_5: t02_b( 5) <= not( t01( 5) and t01( 6) ); + u_t02_6: t02_b( 6) <= not( t01( 6) and t01( 7) ); + u_t02_7: t02_b( 7) <= not( t01( 7) and t01( 8) ); + u_t02_8: t02_b( 8) <= not( t01( 8) and t01( 9) ); + u_t02_9: t02_b( 9) <= not( t01( 9) and t01(10) ); + + + + u_g04_1: g04 ( 1) <= not( g02_b( 1) and ( t02_b( 1) or g02_b( 3) ) ); + u_g04_2: g04 ( 2) <= not( g02_b( 2) and ( t02_b( 2) or g02_b( 4) ) ); + u_g04_3: g04 ( 3) <= not( g02_b( 3) and ( t02_b( 3) or g02_b( 5) ) ); + u_g04_4: g04 ( 4) <= not( g02_b( 4) and ( t02_b( 4) or g02_b( 6) ) ); + u_g04_5: g04 ( 5) <= not( g02_b( 5) and ( t02_b( 5) or g02_b( 7) ) ); + u_g04_6: g04 ( 6) <= not( g02_b( 6) and ( t02_b( 6) or g02_b( 8) ) ); + u_g04_7: g04 ( 7) <= not( g02_b( 7) and ( t02_b( 7) or g02_b( 9) ) ); + u_g04_8: g04 ( 8) <= not( g02_b( 8) and ( t02_b( 8) or g02_b(10) ) ); + u_g04_9: g04 ( 9) <= not( g02_b( 9) and ( t02_b( 9) or g02_b(11) ) ); + u_g04_10: g04 (10) <= not( g02_b(10) ); + u_g04_11: g04 (11) <= not( g02_b(11) ); + + + u_t04_1: t04 ( 1) <= not( t02_b( 1) or t02_b( 3) ); + u_t04_2: t04 ( 2) <= not( t02_b( 2) or t02_b( 4) ); + u_t04_3: t04 ( 3) <= not( t02_b( 3) or t02_b( 5) ); + u_t04_4: t04 ( 4) <= not( t02_b( 4) or t02_b( 6) ); + u_t04_5: t04 ( 5) <= not( t02_b( 5) or t02_b( 7) ); + u_t04_6: t04 ( 6) <= not( t02_b( 6) or t02_b( 8) ); + u_t04_7: t04 ( 7) <= not( t02_b( 7) or t02_b( 9) ); + + + u_g12x_1: g12_x_b( 1) <= not( g04( 1) ); + u_g12y_1: g12_y_b( 1) <= not( t04( 1) and g04( 5) ); + u_g12z_1: g12_z_b( 1) <= not( t04( 1) and t04( 5) and g04( 9) ); + u_c_1: c( 1) <= not( g12_x_b( 1) and g12_y_b( 1) and g12_z_b( 1) ); + + u_g12x_2: g12_x_b( 2) <= not( g04( 2) ); + u_g12y_2: g12_y_b( 2) <= not( t04( 2) and g04( 6) ); + u_g12z_2: g12_z_b( 2) <= not( t04( 2) and t04( 6) and g04(10) ); + u_c_2: c( 2) <= not( g12_x_b( 2) and g12_y_b( 2) and g12_z_b( 2) ); + + u_g12x_3: g12_x_b( 3) <= not( g04( 3) ); + u_g12y_3: g12_y_b( 3) <= not( t04( 3) and g04( 7) ); + u_g12z_3: g12_z_b( 3) <= not( t04( 3) and t04( 7) and g04(11) ); + u_c_3: c( 3) <= not( g12_x_b( 3) and g12_y_b( 3) and g12_z_b( 3) ); + + u_g12x_4: g12_x_b( 4) <= not( g04( 4) ); + u_g12y_4: g12_y_b( 4) <= not( t04( 4) and g04( 8) ); + u_c_4: c( 4) <= not( g12_x_b( 4) and g12_y_b( 4) ); + + u_g12x_5: g12_x_b( 5) <= not( g04( 5) ); + u_g12y_5: g12_y_b( 5) <= not( t04( 5) and g04( 9) ); + u_c_5: c( 5) <= not( g12_x_b( 5) and g12_y_b( 5) ); + + u_g12x_6: g12_x_b( 6) <= not( g04( 6) ); + u_g12y_6: g12_y_b( 6) <= not( t04( 6) and g04(10) ); + u_c_6: c( 6) <= not( g12_x_b( 6) and g12_y_b( 6) ); + + u_g12x_7: g12_x_b( 7) <= not( g04( 7) ); + u_g12y_7: g12_y_b( 7) <= not( t04( 7) and g04(11) ); + u_c_7: c( 7) <= not( g12_x_b( 7) and g12_y_b( 7) ); + + u_g12x_8: g12_x_b( 8) <= not( g04( 8) ); + u_c_8: c( 8) <= not( g12_x_b( 8) ); + + u_g12x_9: g12_x_b( 9) <= not( g04( 9) ); + u_c_9: c( 9) <= not( g12_x_b( 9) ); + + u_g12x_10: g12_x_b(10) <= not( g04(10) ); + u_c_10: c(10) <= not( g12_x_b(10) ); + + u_g12x_11: g12_x_b(11) <= not( g04(11) ); + u_c_11: c(11) <= not( g12_x_b(11) ); + + + + +END; -- ARCH xuq_agen_lo diff --git a/rel/src/vhdl/work/xuq_agen_loca.vhdl b/rel/src/vhdl/work/xuq_agen_loca.vhdl new file mode 100644 index 0000000..01f1260 --- /dev/null +++ b/rel/src/vhdl/work/xuq_agen_loca.vhdl @@ -0,0 +1,207 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; use ieee.std_logic_1164.all ; +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + +-- input phase is important +-- (change X (B) by switching xor/xnor ) + +entity xuq_agen_loca is port( + addr_sel :in std_ulogic ; -- includes "AND mode64" for bits 0 to 31 + addr_nsel :in std_ulogic ; -- includes "AND mode64" for bits 0 to 31 + addr :in std_ulogic_vector(0 to 7) ; + x_b :in std_ulogic_vector(0 to 7) ; -- after xor + y_b :in std_ulogic_vector(0 to 7) ; + sum_0 :out std_ulogic_vector(0 to 7) ; + sum_1 :out std_ulogic_vector(0 to 7) + ); + + + +END xuq_agen_loca; + + +ARCHITECTURE xuq_agen_loca OF xuq_agen_loca IS + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + + signal h01, h01_b :std_ulogic_vector(0 to 7); + signal x :std_ulogic_vector(0 to 7); + signal y :std_ulogic_vector(0 to 7); + signal g01_b :std_ulogic_vector(1 to 7); + signal t01_b :std_ulogic_vector(1 to 7); + signal p01 :std_ulogic_vector(0 to 7); + signal p01_b :std_ulogic_vector(0 to 7); + + + signal g08_b, g08, g04_b, g02 :std_ulogic_vector(1 to 7); + signal t02 :std_ulogic_vector(1 to 7); + signal t04_b :std_ulogic_vector(1 to 7); + signal t08 :std_ulogic_vector(1 to 7); + signal t08_b :std_ulogic_vector(1 to 7); + + +BEGIN + + + --#################################################################### + --# inverter at top to drive to bit location + --#################################################################### + + u_xi: x(0 to 7) <= not x_b(0 to 7) ; -- maybe should be fat wire + u_yi: y(0 to 7) <= not y_b(0 to 7) ; -- maybe should be fat wire + + --#################################################################### + --# funny way to make xor + --#################################################################### + + u_g01: g01_b(1 to 7) <= not( x(1 to 7) and y(1 to 7) ); + u_t01: t01_b(1 to 7) <= not( x(1 to 7) or y(1 to 7) ); + u_p01b: p01_b(0 to 7) <= not( x(0 to 7) xor y(0 to 7) ); + u_p01: p01 (0 to 7) <= not( p01_b(0 to 7) ); + + + u_h01: h01 (0 to 7) <= not( (p01_b(0 to 7) and (0 to 7=> addr_nsel) ) or + (addr (0 to 7) and (0 to 7=> addr_sel ) ) ); + + u_h01b: h01_b(0 to 7) <= not( (p01 (0 to 7) and (0 to 7=> addr_nsel) ) or + (addr (0 to 7) and (0 to 7=> addr_sel ) ) ); + + + --#################################################################### + --# local carry + --#################################################################### + + u_g02_1: g02(1) <= not( g01_b(1) and ( t01_b(1) or g01_b(2) ) ) ; + u_g02_2: g02(2) <= not( g01_b(2) and ( t01_b(2) or g01_b(3) ) ) ; + u_g02_3: g02(3) <= not( g01_b(3) and ( t01_b(3) or g01_b(4) ) ) ; + u_g02_4: g02(4) <= not( g01_b(4) and ( t01_b(4) or g01_b(5) ) ) ; + u_g02_5: g02(5) <= not( g01_b(5) and ( t01_b(5) or g01_b(6) ) ) ; + u_g02_6: g02(6) <= not( g01_b(6) and ( t01_b(6) or g01_b(7) ) ) ;--final-- + u_g02_7: g02(7) <= not( g01_b(7) ) ; + + u_t02_1: t02(1) <= not( t01_b(1) or t01_b(2) ) ; + u_t02_2: t02(2) <= not( t01_b(2) or t01_b(3) ) ; + u_t02_3: t02(3) <= not( t01_b(3) or t01_b(4) ) ; + u_t02_4: t02(4) <= not( t01_b(4) or t01_b(5) ) ; + u_t02_5: t02(5) <= not( t01_b(5) or t01_b(6) ) ; + u_t02_6: t02(6) <= not( g01_b(6) and ( t01_b(6) or t01_b(7) ) ) ;--final-- + u_t02_7: t02(7) <= not( t01_b(7) ) ; + + + + u_g04_1: g04_b(1) <= not( g02(1) or ( t02(1) and g02(3) ) ) ; + u_g04_2: g04_b(2) <= not( g02(2) or ( t02(2) and g02(4) ) ) ; + u_g04_3: g04_b(3) <= not( g02(3) or ( t02(3) and g02(5) ) ) ; + u_g04_4: g04_b(4) <= not( g02(4) or ( t02(4) and g02(6) ) ) ;--final-- + u_g04_5: g04_b(5) <= not( g02(5) or ( t02(5) and g02(7) ) ) ;--final-- + u_g04_6: g04_b(6) <= not( g02(6) ) ; + u_g04_7: g04_b(7) <= not( g02(7) ) ; + + u_t04_1: t04_b(1) <= not( t02(1) and t02(3) ) ; + u_t04_2: t04_b(2) <= not( t02(2) and t02(4) ) ; + u_t04_3: t04_b(3) <= not( t02(3) and t02(5) ) ; + u_t04_4: t04_b(4) <= not( g02(4) or ( t02(4) and t02(6) ) ) ;--final-- + u_t04_5: t04_b(5) <= not( g02(5) or ( t02(5) and t02(7) ) ) ;--final-- + u_t04_6: t04_b(6) <= not( t02(6) ) ; + u_t04_7: t04_b(7) <= not( t02(7) ) ; + + + + u_g08_1: g08(1) <= not( g04_b(1) and ( t04_b(1) or g04_b(5) ) ) ;--final-- + u_g08_2: g08(2) <= not( g04_b(2) and ( t04_b(2) or g04_b(6) ) ) ;--final-- + u_g08_3: g08(3) <= not( g04_b(3) and ( t04_b(3) or g04_b(7) ) ) ;--final-- + u_g08_4: g08(4) <= not( g04_b(4) ) ; + u_g08_5: g08(5) <= not( g04_b(5) ) ; + u_g08_6: g08(6) <= not( g04_b(6) ) ; + u_g08_7: g08(7) <= not( g04_b(7) ) ; + + u_t08_1: t08(1) <= not( g04_b(1) and ( t04_b(1) or t04_b(5) ) ) ;--final-- + u_t08_2: t08(2) <= not( g04_b(2) and ( t04_b(2) or t04_b(6) ) ) ;--final-- + u_t08_3: t08(3) <= not( g04_b(3) and ( t04_b(3) or t04_b(7) ) ) ;--final-- + u_t08_4: t08(4) <= not( t04_b(4) ) ; + u_t08_5: t08(5) <= not( t04_b(5) ) ; + u_t08_6: t08(6) <= not( t04_b(6) ) ; + u_t08_7: t08(7) <= not( t04_b(7) ) ; + + + + + --#################################################################### + --# conditional sums // may need to make NON-xor implementation + --#################################################################### + + u_g08i_1: g08_b(1) <= not g08(1) ; + u_g08i_2: g08_b(2) <= not g08(2) ; + u_g08i_3: g08_b(3) <= not g08(3) ; + u_g08i_4: g08_b(4) <= not g08(4) ; + u_g08i_5: g08_b(5) <= not g08(5) ; + u_g08i_6: g08_b(6) <= not g08(6) ; + u_g08i_7: g08_b(7) <= not g08(7) ; + + u_t08i_1: t08_b(1) <= not t08(1) ; + u_t08i_2: t08_b(2) <= not t08(2) ; + u_t08i_3: t08_b(3) <= not t08(3) ; + u_t08i_4: t08_b(4) <= not t08(4) ; + u_t08i_5: t08_b(5) <= not t08(5) ; + u_t08i_6: t08_b(6) <= not t08(6) ; + u_t08i_7: t08_b(7) <= not t08(7) ; + + + u_sum_0_0: sum_0(0) <= not( ( h01(0) and g08(1) ) or ( h01_b(0) and g08_b(1) ) ); --output-- + u_sum_0_1: sum_0(1) <= not( ( h01(1) and g08(2) ) or ( h01_b(1) and g08_b(2) ) ); --output-- + u_sum_0_2: sum_0(2) <= not( ( h01(2) and g08(3) ) or ( h01_b(2) and g08_b(3) ) ); --output-- + u_sum_0_3: sum_0(3) <= not( ( h01(3) and g08(4) ) or ( h01_b(3) and g08_b(4) ) ); --output-- + u_sum_0_4: sum_0(4) <= not( ( h01(4) and g08(5) ) or ( h01_b(4) and g08_b(5) ) ); --output-- + u_sum_0_5: sum_0(5) <= not( ( h01(5) and g08(6) ) or ( h01_b(5) and g08_b(6) ) ); --output-- + u_sum_0_6: sum_0(6) <= not( ( h01(6) and g08(7) ) or ( h01_b(6) and g08_b(7) ) ); --output-- + u_sum_0_7: sum_0(7) <= not( h01_b(7) ); --output-- + + + u_sum_1_0: sum_1(0) <= not( ( h01(0) and t08(1) ) or ( h01_b(0) and t08_b(1) ) ); --output-- + u_sum_1_1: sum_1(1) <= not( ( h01(1) and t08(2) ) or ( h01_b(1) and t08_b(2) ) ); --output-- + u_sum_1_2: sum_1(2) <= not( ( h01(2) and t08(3) ) or ( h01_b(2) and t08_b(3) ) ); --output-- + u_sum_1_3: sum_1(3) <= not( ( h01(3) and t08(4) ) or ( h01_b(3) and t08_b(4) ) ); --output-- + u_sum_1_4: sum_1(4) <= not( ( h01(4) and t08(5) ) or ( h01_b(4) and t08_b(5) ) ); --output-- + u_sum_1_5: sum_1(5) <= not( ( h01(5) and t08(6) ) or ( h01_b(5) and t08_b(6) ) ); --output-- + u_sum_1_6: sum_1(6) <= not( ( h01(6) and t08(7) ) or ( h01_b(6) and t08_b(7) ) ); --output-- + u_sum_1_7: sum_1(7) <= not( h01(7) ); --output-- + + + + +END; -- ARCH xuq_agen_loca diff --git a/rel/src/vhdl/work/xuq_agen_locae.vhdl b/rel/src/vhdl/work/xuq_agen_locae.vhdl new file mode 100644 index 0000000..ebc3fde --- /dev/null +++ b/rel/src/vhdl/work/xuq_agen_locae.vhdl @@ -0,0 +1,191 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + + +library ieee; use ieee.std_logic_1164.all ; +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + +-- this is used in the agen ... for this byte (half the bits go to ERAT through this macro, others go to DIR from different macro + +entity xuq_agen_locae is port( + addr_sel :in std_ulogic ; -- includes "AND mode64" for bits 0 to 31 + addr_nsel :in std_ulogic ; -- includes "AND mode64" for bits 0 to 31 + addr :in std_ulogic_vector(0 to 3) ; + x_b :in std_ulogic_vector(0 to 7) ; -- after xor + y_b :in std_ulogic_vector(0 to 7) ; + sum_0 :out std_ulogic_vector(0 to 3) ; + sum_1 :out std_ulogic_vector(0 to 3) + ); + + +END xuq_agen_locae; + + +ARCHITECTURE xuq_agen_locae OF xuq_agen_locae IS + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + + signal x :std_ulogic_vector(0 to 7); + signal y :std_ulogic_vector(0 to 7); + signal g01_b :std_ulogic_vector(1 to 7); + signal t01_b :std_ulogic_vector(1 to 7); + signal p01 :std_ulogic_vector(0 to 3); + signal p01_b :std_ulogic_vector(0 to 3); + + + signal g08_b :std_ulogic_vector(1 to 4); + signal g08 :std_ulogic_vector(1 to 4); + signal g04_b :std_ulogic_vector(1 to 7); + signal g02 :std_ulogic_vector(1 to 7); + signal t02 :std_ulogic_vector(1 to 7); + signal t04_b :std_ulogic_vector(1 to 7); + signal t08 :std_ulogic_vector(1 to 4); + signal t08_b :std_ulogic_vector(1 to 4); + + + signal h01, h01_b :std_ulogic_vector(0 to 3); + + +BEGIN + + + --#################################################################### + --# inverter at top to drive to bit location + --#################################################################### + + u_xi: x(0 to 7) <= not x_b(0 to 7) ; -- maybe should be fat wire + u_yi: y(0 to 7) <= not y_b(0 to 7) ; -- maybe should be fat wire + + --#################################################################### + --# pgt + --#################################################################### + + u_g01: g01_b(1 to 7) <= not( x(1 to 7) and y(1 to 7) ); + u_t01: t01_b(1 to 7) <= not( x(1 to 7) or y(1 to 7) ); + u_p01b: p01_b(0 to 3) <= not( x(0 to 3) xor y(0 to 3) ); + u_p01: p01 (0 to 3) <= not( p01_b(0 to 3) ); + + --#################################################################### + --# local carry + --#################################################################### + + u_g02_1: g02(1) <= not( g01_b(1) and ( t01_b(1) or g01_b(2) ) ) ; + u_g02_2: g02(2) <= not( g01_b(2) and ( t01_b(2) or g01_b(3) ) ) ; + u_g02_3: g02(3) <= not( g01_b(3) and ( t01_b(3) or g01_b(4) ) ) ; + u_g02_4: g02(4) <= not( g01_b(4) and ( t01_b(4) or g01_b(5) ) ) ; + u_g02_5: g02(5) <= not( g01_b(5) and ( t01_b(5) or g01_b(6) ) ) ; + u_g02_6: g02(6) <= not( g01_b(6) and ( t01_b(6) or g01_b(7) ) ) ;--final-- + u_g02_7: g02(7) <= not( g01_b(7) ) ; + + u_t02_1: t02(1) <= not( t01_b(1) or t01_b(2) ) ; + u_t02_2: t02(2) <= not( t01_b(2) or t01_b(3) ) ; + u_t02_3: t02(3) <= not( t01_b(3) or t01_b(4) ) ; + u_t02_4: t02(4) <= not( t01_b(4) or t01_b(5) ) ; + u_t02_5: t02(5) <= not( t01_b(5) or t01_b(6) ) ; + u_t02_6: t02(6) <= not( g01_b(6) and ( t01_b(6) or t01_b(7) ) ) ;--final-- + u_t02_7: t02(7) <= not( t01_b(7) ) ; + + + + u_g04_1: g04_b(1) <= not( g02(1) or ( t02(1) and g02(3) ) ) ; + u_g04_2: g04_b(2) <= not( g02(2) or ( t02(2) and g02(4) ) ) ; + u_g04_3: g04_b(3) <= not( g02(3) or ( t02(3) and g02(5) ) ) ; + u_g04_4: g04_b(4) <= not( g02(4) or ( t02(4) and g02(6) ) ) ;--final-- + u_g04_5: g04_b(5) <= not( g02(5) or ( t02(5) and g02(7) ) ) ;--final-- + u_g04_6: g04_b(6) <= not( g02(6) ) ; + u_g04_7: g04_b(7) <= not( g02(7) ) ; + + u_t04_1: t04_b(1) <= not( t02(1) and t02(3) ) ; + u_t04_2: t04_b(2) <= not( t02(2) and t02(4) ) ; + u_t04_3: t04_b(3) <= not( t02(3) and t02(5) ) ; + u_t04_4: t04_b(4) <= not( g02(4) or ( t02(4) and t02(6) ) ) ;--final-- + u_t04_5: t04_b(5) <= not( g02(5) or ( t02(5) and t02(7) ) ) ;--final-- + u_t04_6: t04_b(6) <= not( t02(6) ) ; + u_t04_7: t04_b(7) <= not( t02(7) ) ; + + + + u_g08_1: g08(1) <= not( g04_b(1) and ( t04_b(1) or g04_b(5) ) ) ;--final-- + u_g08_2: g08(2) <= not( g04_b(2) and ( t04_b(2) or g04_b(6) ) ) ;--final-- + u_g08_3: g08(3) <= not( g04_b(3) and ( t04_b(3) or g04_b(7) ) ) ;--final-- + u_g08_4: g08(4) <= not( g04_b(4) ) ; + + u_t08_1: t08(1) <= not( g04_b(1) and ( t04_b(1) or t04_b(5) ) ) ;--final-- + u_t08_2: t08(2) <= not( g04_b(2) and ( t04_b(2) or t04_b(6) ) ) ;--final-- + u_t08_3: t08(3) <= not( g04_b(3) and ( t04_b(3) or t04_b(7) ) ) ;--final-- + u_t08_4: t08(4) <= not( t04_b(4) ) ; + + + + + --#################################################################### + --# conditional sums // may need to make NON-xor implementation + --#################################################################### + + u_g08i_1: g08_b(1) <= not g08(1) ; + u_g08i_2: g08_b(2) <= not g08(2) ; + u_g08i_3: g08_b(3) <= not g08(3) ; + u_g08i_4: g08_b(4) <= not g08(4) ; + + u_t08i_1: t08_b(1) <= not t08(1) ; + u_t08i_2: t08_b(2) <= not t08(2) ; + u_t08i_3: t08_b(3) <= not t08(3) ; + u_t08i_4: t08_b(4) <= not t08(4) ; + + + + u_h01: h01 (0 to 3) <= not( (p01_b(0 to 3) and (0 to 3=> addr_nsel) ) or + (addr (0 to 3) and (0 to 3=> addr_sel ) ) ); + + u_h01b: h01_b(0 to 3) <= not( (p01 (0 to 3) and (0 to 3=> addr_nsel) ) or + (addr (0 to 3) and (0 to 3=> addr_sel ) ) ); + + + u_sum_0_0: sum_0(0) <= not( ( h01(0) and g08(1) ) or ( h01_b(0) and g08_b(1) ) ); --output-- + u_sum_0_1: sum_0(1) <= not( ( h01(1) and g08(2) ) or ( h01_b(1) and g08_b(2) ) ); --output-- + u_sum_0_2: sum_0(2) <= not( ( h01(2) and g08(3) ) or ( h01_b(2) and g08_b(3) ) ); --output-- + u_sum_0_3: sum_0(3) <= not( ( h01(3) and g08(4) ) or ( h01_b(3) and g08_b(4) ) ); --output-- + + + u_sum_1_0: sum_1(0) <= not( ( h01(0) and t08(1) ) or ( h01_b(0) and t08_b(1) ) ); --output-- + u_sum_1_1: sum_1(1) <= not( ( h01(1) and t08(2) ) or ( h01_b(1) and t08_b(2) ) ); --output-- + u_sum_1_2: sum_1(2) <= not( ( h01(2) and t08(3) ) or ( h01_b(2) and t08_b(3) ) ); --output-- + u_sum_1_3: sum_1(3) <= not( ( h01(3) and t08(4) ) or ( h01_b(3) and t08_b(4) ) ); --output-- + + + + +END; -- ARCH xuq_agen_locae diff --git a/rel/src/vhdl/work/xuq_alu.vhdl b/rel/src/vhdl/work/xuq_alu.vhdl new file mode 100644 index 0000000..9cd9005 --- /dev/null +++ b/rel/src/vhdl/work/xuq_alu.vhdl @@ -0,0 +1,574 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +LIBRARY ieee; USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY ibm; + USE ibm.std_ulogic_support.all; + USE ibm.std_ulogic_unsigned.all; + USE ibm.std_ulogic_function_support.all; +LIBRARY support; + USE support.power_logic_pkg.all; +LIBRARY tri; USE tri.tri_latches_pkg.all; +LIBRARY work; USE work.xuq_pkg.all; + +entity xuq_alu is + generic( + expand_type : integer := 2; + regmode : integer := 6; + a2mode : integer := 1; + threads : integer := 4; + dc_size : natural := 14; + fxu_synth : integer := 0); + port( + -- Clocks + nclk : in clk_logic; + + -- Pervasive + d_mode_dc : in std_ulogic; + delay_lclkr_dc : in std_ulogic; + mpw1_dc_b : in std_ulogic; + mpw2_dc_b : in std_ulogic; + func_sl_force : in std_ulogic; + func_sl_thold_0_b : in std_ulogic; + sg_0 : in std_ulogic; + scan_in : in std_ulogic_vector(0 to 1); + scan_out : out std_ulogic_vector(0 to 1); + + -- Power + vdd : inout power_logic; + gnd : inout power_logic; + + -- MSR[CM] Need to do 64 bit math + spr_msr_cm : in std_ulogic_vector(0 to threads-1); + + -- Decode Inputs + dec_alu_rf1_act : in std_ulogic; + dec_alu_ex1_act : in std_ulogic; + dec_alu_rf1_sel : in std_ulogic_vector(0 to 3); + dec_alu_rf1_add_rs0_inv : in std_ulogic_vector(64-(2**regmode) to 63); + dec_alu_rf1_add_ci : in std_ulogic; + dec_alu_rf1_is_cmpl : in std_ulogic; + dec_alu_rf1_tw_cmpsel : in std_ulogic_vector(0 to 5); + dec_ex2_tid : in std_ulogic_vector(0 to threads-1); + dec_ex4_tid : in std_ulogic_vector(0 to threads-1); + dec_alu_rf1_mul_recform : in std_ulogic; + dec_alu_rf1_mul_val : in std_ulogic; + dec_alu_rf1_mul_ret : in std_ulogic; + dec_alu_rf1_mul_sign : in std_ulogic; + dec_alu_rf1_mul_size : in std_ulogic; + dec_alu_rf1_mul_imm : in std_ulogic; + fxa_fxb_rf1_div_ctr : in std_ulogic_vector(0 to 7); + dec_alu_rf1_div_val : in std_ulogic; + dec_alu_rf1_div_sign : in std_ulogic; + dec_alu_rf1_div_size : in std_ulogic; + dec_alu_rf1_div_extd : in std_ulogic; + dec_alu_rf1_div_recform : in std_ulogic; + dec_alu_ex1_is_cmp : in std_ulogic; + dec_alu_rf1_select_64bmode : in std_ulogic; + fxa_fxb_ex1_hold_ctr_flush : in std_ulogic; + + ----- Source Data ----- + -- GPR Sources from Bypass + byp_alu_ex1_rs0 : in std_ulogic_vector(64-(2**regmode) to 63); + byp_alu_ex1_rs1 : in std_ulogic_vector(64-(2**regmode) to 63); + byp_alu_ex1_mulsrc_0 : in std_ulogic_vector(64-(2**regmode) to 63); + byp_alu_ex1_mulsrc_1 : in std_ulogic_vector(64-(2**regmode) to 63); + byp_alu_ex1_divsrc_0 : in std_ulogic_vector(64-(2**regmode) to 63); + byp_alu_ex1_divsrc_1 : in std_ulogic_vector(64-(2**regmode) to 63); + + -- Effective Addresses + xu_ex1_eff_addr_int : out std_ulogic_vector(64-(dc_size-3) to 63); + xu_ex2_eff_addr : out std_ulogic_vector(64-(2**regmode) to 63); + + -- Target Data + alu_byp_ex5_mul_rt : out std_ulogic_vector(64-(2**regmode) to 63); + alu_byp_ex3_div_rt : out std_ulogic_vector(64-(2**regmode) to 63); + alu_ex2_div_done : out std_ulogic; + alu_dec_ex1_ipb_ba : out std_ulogic_vector(27 to 31); + alu_dec_ex1_ipb_sz : out std_ulogic_vector(18 to 19); + alu_dec_div_need_hole : out std_ulogic; + alu_ex3_mul_done : out std_ulogic; + alu_ex4_mul_done : out std_ulogic; + alu_cpl_ex3_trap_val : out std_ulogic; + alu_byp_ex2_rt : out std_ulogic_vector(64-(2**regmode) to 63); + alu_byp_ex1_log_rt : out std_ulogic_vector(64-(2**regmode) to 63); + + -- BYP XER + dec_alu_rf1_xer_ov_update : in std_ulogic; + dec_alu_rf1_xer_ca_update : in std_ulogic; + dec_alu_rf1_sh_right : in std_ulogic; + dec_alu_rf1_sh_word : in std_ulogic; + dec_alu_rf1_sgnxtd_byte : in std_ulogic; + dec_alu_rf1_sgnxtd_half : in std_ulogic; + dec_alu_rf1_sgnxtd_wd : in std_ulogic; + dec_alu_rf1_sra_dw : in std_ulogic; + dec_alu_rf1_sra_wd : in std_ulogic; + dec_alu_rf1_chk_shov_dw : in std_ulogic; + dec_alu_rf1_chk_shov_wd : in std_ulogic; + dec_alu_rf1_use_me_ins_hi : in std_ulogic; + dec_alu_rf1_use_me_ins_lo : in std_ulogic; + dec_alu_rf1_use_mb_ins_hi : in std_ulogic; + dec_alu_rf1_use_mb_ins_lo : in std_ulogic; + dec_alu_rf1_use_me_rb_hi : in std_ulogic; + dec_alu_rf1_use_me_rb_lo : in std_ulogic; + dec_alu_rf1_use_mb_rb_hi : in std_ulogic; + dec_alu_rf1_use_mb_rb_lo : in std_ulogic; + dec_alu_rf1_use_rb_amt_hi : in std_ulogic; + dec_alu_rf1_use_rb_amt_lo : in std_ulogic; + dec_alu_rf1_zm_ins : in std_ulogic; + byp_alu_rf1_isel_fcn : in std_ulogic_vector(0 to 3); + dec_alu_rf1_log_fcn : in std_ulogic_vector(0 to 3); + dec_alu_rf1_me_ins_b : in std_ulogic_vector(0 to 5); + dec_alu_rf1_mb_ins : in std_ulogic_vector(0 to 5); + dec_alu_rf1_sh_amt : in std_ulogic_vector(0 to 5); + dec_alu_rf1_mb_gt_me : in std_ulogic; + alu_byp_ex2_xer : out std_ulogic_vector(0 to 3); + alu_byp_ex5_xer_mul : out std_ulogic_vector(0 to 3); + alu_byp_ex3_xer_div : out std_ulogic_vector(0 to 3); + + -- CR Result to bypass + alu_byp_ex2_cr_recform : out std_ulogic_vector(0 to 3); + alu_byp_ex5_cr_mul : out std_ulogic_vector(0 to 4); + alu_byp_ex3_cr_div : out std_ulogic_vector(0 to 4) + ); + -- synopsys translate_off + -- synopsys translate_on +end xuq_alu; + +architecture xuq_alu of xuq_alu is + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + constant regsize : integer := 2**regmode; + + signal add_log_ex1_add_rt : std_ulogic_vector(64-regsize to 63); + signal rf1_is_add_op : std_ulogic; + signal rf1_is_rot_op : std_ulogic; + signal rf1_is_cmpb_op : std_ulogic; + signal ex2_add_xer_ov : std_ulogic; + signal ex2_add_xer_ca : std_ulogic; + signal ex2_rot_xer_ca : std_ulogic; + signal ex3_div_xer_ov : std_ulogic; + signal ex3_div_xer_ov_update : std_ulogic; + signal ex2_spr_msr_cm : std_ulogic; + signal ex4_spr_msr_cm : std_ulogic; + signal ex2_cr_recform : std_ulogic_vector(0 to 3); + signal log_add_ex2_rt : std_ulogic_vector(64-(2**regmode) to 63); + signal ex2_xer_ca : std_ulogic; + signal rf1_sel_rot_log : std_ulogic; + signal byp_alu_ex1_rs0_b, byp_alu_ex1_rs1_b : std_ulogic_vector(64-(2**regmode) to 63); + + --------------------------------------------------------------------- + -- Latch Signals + --------------------------------------------------------------------- + signal ex1_xer_ov_update_q : std_ulogic; -- Valids for XER[OV], XER[CA] + signal ex2_xer_ov_update_q, ex2_xer_ov_update_d : std_ulogic; + signal ex1_xer_ca_update_q : std_ulogic; + signal ex2_xer_ca_update_q, ex2_xer_ca_update_d : std_ulogic; + signal ex1_is_add_op_q : std_ulogic; -- Unit valids + signal ex1_is_rot_op_q : std_ulogic; + signal ex2_is_rot_op_q : std_ulogic; + signal spr_msr_cm_q : std_ulogic_vector(0 to threads-1); + + --------------------------------------------------------------------- + -- Scanchain + --------------------------------------------------------------------- + constant ex1_xer_ov_update_offset : integer := 3; + constant ex2_xer_ov_update_offset : integer := ex1_xer_ov_update_offset + 1; + constant ex1_xer_ca_update_offset : integer := ex2_xer_ov_update_offset + 1; + constant ex2_xer_ca_update_offset : integer := ex1_xer_ca_update_offset + 1; + constant ex1_is_add_op_offset : integer := ex2_xer_ca_update_offset + 1; + constant ex1_is_rot_op_offset : integer := ex1_is_add_op_offset + 1; + constant ex2_is_rot_op_offset : integer := ex1_is_rot_op_offset + 1; + constant spr_msr_cm_offset : integer := ex2_is_rot_op_offset + 1; + constant scan_right : integer := spr_msr_cm_offset + spr_msr_cm_q'length; + signal siv : std_ulogic_vector(0 to scan_right-1); + signal sov : std_ulogic_vector(0 to scan_right-1); + + + + +begin + + --------------------------------------------------------------------- + -- Source Buffering + --------------------------------------------------------------------- + u_s0i: byp_alu_ex1_rs0_b <= not byp_alu_ex1_rs0; + u_s1i: byp_alu_ex1_rs1_b <= not byp_alu_ex1_rs1; + + --------------------------------------------------------------------- + -- + --------------------------------------------------------------------- + ex2_spr_msr_cm <= or_reduce(spr_msr_cm_q and dec_ex2_tid); + ex4_spr_msr_cm <= or_reduce(spr_msr_cm_q and dec_ex4_tid); + + rf1_sel_rot_log <= not dec_alu_rf1_sel(0); + + rf1_is_add_op <= dec_alu_rf1_sel(0); + rf1_is_rot_op <= dec_alu_rf1_sel(1); + rf1_is_cmpb_op <= dec_alu_rf1_sel(3); + + alu_dec_ex1_ipb_ba <= byp_alu_ex1_rs0(59 to 63); + alu_dec_ex1_ipb_sz <= byp_alu_ex1_rs0(50 to 51); + + --------------------------------------------------------------------- + -- XER Update + --------------------------------------------------------------------- + + ex2_xer_ca_update_d <= ex1_xer_ca_update_q and (ex1_is_add_op_q or ex1_is_rot_op_q); + ex2_xer_ov_update_d <= ex1_xer_ov_update_q and ex1_is_add_op_q; + + with ex2_is_rot_op_q select + ex2_xer_ca <= ex2_rot_xer_ca when '1', + ex2_add_xer_ca when others; + + alu_byp_ex2_xer <= ex2_add_xer_ov & ex2_xer_ca & ex2_xer_ov_update_q & ex2_xer_ca_update_q; + alu_byp_ex3_xer_div <= ex3_div_xer_ov & tidn & ex3_div_xer_ov_update & tidn; + + alu_byp_ex2_cr_recform <= ex2_cr_recform(0 to 2) & (ex2_cr_recform(3) and ex2_xer_ov_update_q); + + --------------------------------------------------------------------- + -- Add + --------------------------------------------------------------------- + xu_alu_add : entity work.xuq_alu_add(xuq_alu_add) + generic map( + expand_type => expand_type, + dc_size => dc_size, + regsize => regsize, + fxu_synth => fxu_synth) + port map( + nclk => nclk, + vdd => vdd, + gnd => gnd, + dec_alu_rf1_add_act => dec_alu_rf1_act, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc, + mpw1_dc_b => mpw1_dc_b, + mpw2_dc_b => mpw2_dc_b, + func_sl_force => func_sl_force, + func_sl_thold_0_b => func_sl_thold_0_b, + sg_0 => sg_0, + scan_in => siv(0), + scan_out => sov(0), + dec_alu_rf1_select_64bmode => dec_alu_rf1_select_64bmode, + dec_alu_rf1_add_rs0_inv => dec_alu_rf1_add_rs0_inv, + dec_alu_rf1_add_ci => dec_alu_rf1_add_ci, + dec_alu_rf1_is_cmpl => dec_alu_rf1_is_cmpl, + dec_alu_rf1_tw_cmpsel => dec_alu_rf1_tw_cmpsel, + dec_alu_ex1_is_cmp => dec_alu_ex1_is_cmp, + byp_alu_ex1_rs0 => byp_alu_ex1_rs0, + byp_alu_ex1_rs1 => byp_alu_ex1_rs1, + log_add_ex2_rt => log_add_ex2_rt, + alu_byp_ex2_rt => alu_byp_ex2_rt, + add_log_ex1_add_rt => add_log_ex1_add_rt, + xu_ex1_eff_addr_int => xu_ex1_eff_addr_int, + xu_ex2_eff_addr => xu_ex2_eff_addr, + ex2_cr_recform => ex2_cr_recform, + ex3_trap_val => alu_cpl_ex3_trap_val, + ex2_add_xer_ov => ex2_add_xer_ov, + ex2_add_xer_ca => ex2_add_xer_ca); + + --------------------------------------------------------------------- + -- Multiply + --------------------------------------------------------------------- + xu_alu_mult : entity work.xuq_alu_mult(xuq_alu_mult) + generic map( + expand_type => expand_type, + regmode => regmode, + a2mode => a2mode, + threads => threads, + fxu_synth => fxu_synth) + port map( + nclk => nclk, + vdd => vdd, + gnd => gnd, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc, + mpw1_dc_b => mpw1_dc_b, + mpw2_dc_b => mpw2_dc_b, + func_sl_force => func_sl_force, + func_sl_thold_0_b => func_sl_thold_0_b, + sg_0 => sg_0, + scan_in => siv(1), + scan_out => sov(1), + dec_alu_rf1_mul_recform => dec_alu_rf1_mul_recform, + dec_alu_rf1_mul_val => dec_alu_rf1_mul_val, + dec_alu_rf1_mul_ret => dec_alu_rf1_mul_ret, + dec_alu_rf1_mul_sign => dec_alu_rf1_mul_sign, + dec_alu_rf1_mul_size => dec_alu_rf1_mul_size, + dec_alu_rf1_mul_imm => dec_alu_rf1_mul_imm, + dec_alu_rf1_xer_ov_update => dec_alu_rf1_xer_ov_update, + fxa_fxb_ex1_hold_ctr_flush => fxa_fxb_ex1_hold_ctr_flush, + ex4_spr_msr_cm => ex4_spr_msr_cm, + byp_alu_ex1_mulsrc_0 => byp_alu_ex1_mulsrc_0, + byp_alu_ex1_mulsrc_1 => byp_alu_ex1_mulsrc_1, + alu_ex3_mul_done => alu_ex3_mul_done, + alu_ex4_mul_done => alu_ex4_mul_done, + alu_byp_ex5_mul_rt => alu_byp_ex5_mul_rt, + alu_byp_ex5_xer_mul => alu_byp_ex5_xer_mul, + alu_byp_ex5_cr_mul => alu_byp_ex5_cr_mul); + + --------------------------------------------------------------------- + -- Divide + --------------------------------------------------------------------- + xuq_alu_div : entity work.xuq_alu_div(xuq_alu_div) + generic map( + expand_type => expand_type, + regsize => regsize) + port map( + nclk => nclk, + vdd => vdd, + gnd => gnd, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc, + mpw1_dc_b => mpw1_dc_b, + mpw2_dc_b => mpw2_dc_b, + func_sl_force => func_sl_force, + func_sl_thold_0_b => func_sl_thold_0_b, + sg_0 => sg_0, + scan_in => scan_in(0), + scan_out => scan_out(0), + fxa_fxb_rf1_div_ctr => fxa_fxb_rf1_div_ctr, + dec_alu_rf1_div_val => dec_alu_rf1_div_val, + dec_alu_rf1_div_sign => dec_alu_rf1_div_sign, + dec_alu_rf1_div_size => dec_alu_rf1_div_size, + dec_alu_rf1_div_extd => dec_alu_rf1_div_extd, + dec_alu_rf1_div_recform => dec_alu_rf1_div_recform, + byp_alu_ex1_divsrc_0 => byp_alu_ex1_divsrc_0, + byp_alu_ex1_divsrc_1 => byp_alu_ex1_divsrc_1, + fxa_fxb_ex1_hold_ctr_flush => fxa_fxb_ex1_hold_ctr_flush, + dec_alu_rf1_xer_ov_update => dec_alu_rf1_xer_ov_update, + alu_dec_div_need_hole => alu_dec_div_need_hole, + alu_byp_ex3_div_rt => alu_byp_ex3_div_rt, + alu_ex2_div_done => alu_ex2_div_done, + ex3_div_xer_ov => ex3_div_xer_ov, + ex3_div_xer_ov_update => ex3_div_xer_ov_update, + alu_byp_ex3_cr_div => alu_byp_ex3_cr_div, + ex2_spr_msr_cm => ex2_spr_msr_cm); + + --------------------------------------------------------------------- + -- MRG + --------------------------------------------------------------------- + xuq_alu_mrg : entity work.xuq_alu_mrg(xuq_alu_mrg) + generic map( + expand_type => expand_type) + port map( + nclk => nclk, + vdd => vdd, + gnd => gnd, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc, + mpw1_dc_b => mpw1_dc_b, + mpw2_dc_b => mpw2_dc_b, + func_sl_force => func_sl_force, + func_sl_thold_0_b => func_sl_thold_0_b, + sg_0 => sg_0, + scan_in => siv(2), + scan_out => sov(2), + rf1_act => dec_alu_rf1_act, + ex1_act => dec_alu_ex1_act, + dec_alu_rf1_zm_ins => dec_alu_rf1_zm_ins, + dec_alu_rf1_mb_ins => dec_alu_rf1_mb_ins, + dec_alu_rf1_me_ins_b => dec_alu_rf1_me_ins_b, + dec_alu_rf1_sh_amt => dec_alu_rf1_sh_amt, + dec_alu_rf1_sh_right => dec_alu_rf1_sh_right, + dec_alu_rf1_sh_word => dec_alu_rf1_sh_word, + dec_alu_rf1_use_rb_amt_hi => dec_alu_rf1_use_rb_amt_hi, + dec_alu_rf1_use_rb_amt_lo => dec_alu_rf1_use_rb_amt_lo, + dec_alu_rf1_use_me_rb_hi => dec_alu_rf1_use_me_rb_hi, + dec_alu_rf1_use_me_rb_lo => dec_alu_rf1_use_me_rb_lo, + dec_alu_rf1_use_mb_rb_hi => dec_alu_rf1_use_mb_rb_hi, + dec_alu_rf1_use_mb_rb_lo => dec_alu_rf1_use_mb_rb_lo, + dec_alu_rf1_use_me_ins_hi => dec_alu_rf1_use_me_ins_hi, + dec_alu_rf1_use_me_ins_lo => dec_alu_rf1_use_me_ins_lo, + dec_alu_rf1_use_mb_ins_hi => dec_alu_rf1_use_mb_ins_hi, + dec_alu_rf1_use_mb_ins_lo => dec_alu_rf1_use_mb_ins_lo, + dec_alu_rf1_chk_shov_wd => dec_alu_rf1_chk_shov_wd, + dec_alu_rf1_chk_shov_dw => dec_alu_rf1_chk_shov_dw, + dec_alu_rf1_mb_gt_me => dec_alu_rf1_mb_gt_me, + dec_alu_rf1_cmp_byt => rf1_is_cmpb_op, + dec_alu_rf1_sgnxtd_byte => dec_alu_rf1_sgnxtd_byte, + dec_alu_rf1_sgnxtd_half => dec_alu_rf1_sgnxtd_half, + dec_alu_rf1_sgnxtd_wd => dec_alu_rf1_sgnxtd_wd, + dec_alu_rf1_sra_wd => dec_alu_rf1_sra_wd, + dec_alu_rf1_sra_dw => dec_alu_rf1_sra_dw, + byp_alu_rf1_isel_fcn => byp_alu_rf1_isel_fcn, + dec_alu_rf1_log_fcn => dec_alu_rf1_log_fcn, + dec_alu_rf1_sel_rot_log => rf1_sel_rot_log, + byp_alu_ex1_rs0_b => byp_alu_ex1_rs0_b, + byp_alu_ex1_rs1_b => byp_alu_ex1_rs1_b, + add_mrg_ex1_add_rt => add_log_ex1_add_rt, + alu_byp_ex1_log_rt => alu_byp_ex1_log_rt, + mrg_add_ex2_rt => log_add_ex2_rt, + ex2_mrg_xer_ca => ex2_rot_xer_ca); + + + mark_unused(dec_alu_rf1_sel(2)); + --------------------------------------------------------------------- + -- Latches + --------------------------------------------------------------------- + ex1_xer_ov_update_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_xer_ov_update_offset), + scout => sov(ex1_xer_ov_update_offset), + din => dec_alu_rf1_xer_ov_update, + dout => ex1_xer_ov_update_q); + ex2_xer_ov_update_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_xer_ov_update_offset), + scout => sov(ex2_xer_ov_update_offset), + din => ex2_xer_ov_update_d, + dout => ex2_xer_ov_update_q); + ex1_xer_ca_update_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_xer_ca_update_offset), + scout => sov(ex1_xer_ca_update_offset), + din => dec_alu_rf1_xer_ca_update, + dout => ex1_xer_ca_update_q); + ex2_xer_ca_update_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_xer_ca_update_offset), + scout => sov(ex2_xer_ca_update_offset), + din => ex2_xer_ca_update_d, + dout => ex2_xer_ca_update_q); + ex1_is_add_op_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_add_op_offset), + scout => sov(ex1_is_add_op_offset), + din => rf1_is_add_op, + dout => ex1_is_add_op_q); + ex1_is_rot_op_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_rot_op_offset), + scout => sov(ex1_is_rot_op_offset), + din => rf1_is_rot_op, + dout => ex1_is_rot_op_q); + ex2_is_rot_op_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_is_rot_op_offset), + scout => sov(ex2_is_rot_op_offset), + din => ex1_is_rot_op_q, + dout => ex2_is_rot_op_q); + spr_msr_cm_latch : tri_rlmreg_p + generic map (width => spr_msr_cm_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(spr_msr_cm_offset to spr_msr_cm_offset + spr_msr_cm_q'length-1), + scout => sov(spr_msr_cm_offset to spr_msr_cm_offset + spr_msr_cm_q'length-1), + din => spr_msr_cm, + dout => spr_msr_cm_q); + siv(0 to siv'right) <= sov(1 to siv'right) & scan_in(1); + scan_out(1) <= sov(0); + +end architecture xuq_alu; diff --git a/rel/src/vhdl/work/xuq_alu_add.vhdl b/rel/src/vhdl/work/xuq_alu_add.vhdl new file mode 100644 index 0000000..d27e2e8 --- /dev/null +++ b/rel/src/vhdl/work/xuq_alu_add.vhdl @@ -0,0 +1,624 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +LIBRARY ieee; USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY ibm; + USE ibm.std_ulogic_support.all; + USE ibm.std_ulogic_unsigned.all; + USE ibm.std_ulogic_function_support.all; +LIBRARY support; + USE support.power_logic_pkg.all; +LIBRARY tri; USE tri.tri_latches_pkg.all; + +entity xuq_alu_add is + generic( + expand_type : integer := 2; + dc_size : natural := 14; + regsize : integer := 64; + fxu_synth : integer := 0); + port( + -- Clocks + nclk : in clk_logic; + + -- Power + vdd : inout power_logic; + gnd : inout power_logic; + + -- Pervasive + dec_alu_rf1_add_act : in std_ulogic; + d_mode_dc : in std_ulogic; + delay_lclkr_dc : in std_ulogic; + mpw1_dc_b : in std_ulogic; + mpw2_dc_b : in std_ulogic; + func_sl_force : in std_ulogic; + func_sl_thold_0_b : in std_ulogic; + sg_0 : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + -- MSR[CM] + dec_alu_rf1_select_64bmode : in std_ulogic; + + -- Decode Inputs + dec_alu_rf1_add_rs0_inv : in std_ulogic_vector(64-regsize to 63); + dec_alu_rf1_add_ci : in std_ulogic; + dec_alu_rf1_is_cmpl : in std_ulogic; + dec_alu_rf1_tw_cmpsel : in std_ulogic_vector(0 to 5); + dec_alu_ex1_is_cmp : in std_ulogic; + + -- Source Data + byp_alu_ex1_rs0 : in std_ulogic_vector(64-regsize to 63); + byp_alu_ex1_rs1 : in std_ulogic_vector(64-regsize to 63); + + -- RS0 and RS1 are Equal + log_add_ex2_rt :in std_ulogic_vector(64-regsize to 63); + alu_byp_ex2_rt :out std_ulogic_vector(64-regsize to 63); + + -- Target Data + add_log_ex1_add_rt : out std_ulogic_vector(64-regsize to 63); + ex2_cr_recform : out std_ulogic_vector(0 to 3); + + -- Effective address + xu_ex1_eff_addr_int : out std_ulogic_vector(64-(dc_size-3) to 63); + xu_ex2_eff_addr : out std_ulogic_vector(64-regsize to 63); + + -- Trap + ex3_trap_val : out std_ulogic; + + -- Carry/Overflow + ex2_add_xer_ov : out std_ulogic; + ex2_add_xer_ca : out std_ulogic + ); + -- synopsys translate_off + + -- synopsys translate_on + + + +end xuq_alu_add; +architecture xuq_alu_add of xuq_alu_add is + constant msb : integer := 64-regsize; + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal ex1_add_act_q : std_ulogic; + signal ex1_rs0_inv_q, ex1_rs0_inv_q_b : std_ulogic_vector(64-regsize to 63); + signal ex1_add_ci_q : std_ulogic; + signal ex1_is_cmpl_q : std_ulogic; + signal ex1_tw_cmpsel_q : std_ulogic_vector(0 to 5); + signal ex2_add_xer_ca_q, ex2_add_xer_ca_d : std_ulogic; + signal ex2_rs0_msb_q, ex2_rs0_msb_d : std_ulogic; + signal ex2_rs1_msb_q, ex2_rs1_msb_d : std_ulogic; + signal ex2_is_cmpl_q : std_ulogic; + signal ex2_overflow_q : std_ulogic; + signal ex2_tw_cmpsel_q : std_ulogic_vector(0 to 5); + signal ex2_is_cmp_q : std_ulogic; + signal ex2_eff_addr_q, ex2_eff_addr_q_b, ex2_eff_addr_d : std_ulogic_vector(64-regsize to 63); + signal ex3_trap_val_q, ex3_trap_val_d : std_ulogic; + signal ex1_select_64bmode_q : std_ulogic; + signal ex2_select_32bcmp_q, ex1_select_32bcmp : std_ulogic; + -- Scanchains + constant ex1_add_act_offset : integer := 0; + constant ex1_rs0_inv_offset : integer := ex1_add_act_offset + 1; + constant ex1_add_ci_offset : integer := ex1_rs0_inv_offset + ex1_rs0_inv_q'length; + constant ex1_is_cmpl_offset : integer := ex1_add_ci_offset + 1; + constant ex1_tw_cmpsel_offset : integer := ex1_is_cmpl_offset + 1; + constant ex2_add_xer_ca_offset : integer := ex1_tw_cmpsel_offset + ex1_tw_cmpsel_q'length; + constant ex2_rs0_msb_offset : integer := ex2_add_xer_ca_offset + 1; + constant ex2_rs1_msb_offset : integer := ex2_rs0_msb_offset + 1; + constant ex2_is_cmpl_offset : integer := ex2_rs1_msb_offset + 1; + constant ex2_overflow_offset : integer := ex2_is_cmpl_offset + 1; + constant ex2_tw_cmpsel_offset : integer := ex2_overflow_offset + 1; + constant ex2_is_cmp_offset : integer := ex2_tw_cmpsel_offset + ex2_tw_cmpsel_q'length; + constant ex2_eff_addr_offset : integer := ex2_is_cmp_offset + 1; + constant ex3_trap_val_offset : integer := ex2_eff_addr_offset + ex2_eff_addr_q'length; + constant ex1_select_64bmode_offset : integer := ex3_trap_val_offset + 1; + constant ex2_select_32bcmp_offset : integer := ex1_select_64bmode_offset + 1; + constant scan_right : integer := ex2_select_32bcmp_offset + 1; + signal siv : std_ulogic_vector(0 to scan_right-1); + signal sov : std_ulogic_vector(0 to scan_right-1); + -- Signals + signal ex1_lclk_int : clk_logic; + signal ex1_d1clk_int, ex1_d2clk_int : std_ulogic; + signal ex2_lclk_int : clk_logic; + signal ex2_d1clk_int, ex2_d2clk_int : std_ulogic; + signal ex1_aop_00 : std_ulogic; + signal ex1_bop_00 : std_ulogic; + signal ex1_aop_32 : std_ulogic; + signal ex1_bop_32 : std_ulogic; + signal ex1_x_b, ex1_y_b , ex1_y : std_ulogic_vector(64-regsize to 63); + signal aop_rep_b , bop_rep_b : std_ulogic_vector(64-regsize to 63); + signal ex1_add_rslt : std_ulogic_vector(64-regsize to 63); + signal ex1_cout_32 : std_ulogic; + signal ex1_cout_00 : std_ulogic; + signal ex2_diff_sign : std_ulogic; + signal ex2_cmp0_eq : std_ulogic; + signal ex2_rslt_gt_s : std_ulogic; + signal ex2_rslt_lt_s : std_ulogic; + signal ex2_rslt_gt_u : std_ulogic; + signal ex2_rslt_lt_u : std_ulogic; + signal ex2_cmp_eq : std_ulogic; + signal ex2_cmp_gt : std_ulogic; + signal ex2_cmp_lt : std_ulogic; + signal ex2_sign_cmp : std_ulogic; + signal ex2_rt_msb : std_ulogic; + signal ex1_overflow : std_ulogic; + signal ex2_cmp0_lo , ex2_cmp0_hi : std_ulogic; + signal ex1_sgn00_32, ex1_sgn11_32 : std_ulogic; + signal ex1_sgn00_64, ex1_sgn11_64 : std_ulogic; + signal ex1_ovf32_00_b, ex1_ovf32_11_b : std_ulogic; + signal ex1_ovf64_00_b, ex1_ovf64_11_b : std_ulogic; + + signal eff0_b, eff0, eff1_b, eff1 : std_ulogic_vector(64-(dc_size-3) to 63); + signal alu_byp_ex2_rt_b : std_ulogic_vector(64-regsize to 63); + + + +begin + + + ex1_select_32bcmp <= not ex1_select_64bmode_q; + + aop_rep_b <= not( byp_alu_ex1_rs0 ) ; + bop_rep_b <= not( byp_alu_ex1_rs1 ) ; + + u_aop_xor: ex1_x_b <= aop_rep_b xor ex1_rs0_inv_q ; -- xor2_x2m --w=12 + u_bop_i: ex1_y <= not bop_rep_b ; -- inv_x1m --w=4 + u_bop_ii: ex1_y_b <= not ex1_y ; -- inv_x2m --w=4 + u_aop_slow00: ex1_aop_00 <= not ex1_x_b(msb); + u_aop_slow32: ex1_aop_32 <= not ex1_x_b(32) ; + u_bop_slow00: ex1_bop_00 <= not ex1_y_b(msb); + u_bop_slow32: ex1_bop_32 <= not ex1_y_b(32) ; + + + csa: entity work.xuq_add(xuq_add) + port map( + x_b(0 to 63) => ex1_x_b, + y_b(0 to 63) => ex1_y_b, + ci(8) => ex1_add_ci_q, + sum(0 to 63) => ex1_add_rslt, + cout_32 => ex1_cout_32, + cout_0 => ex1_cout_00); + + -- Overflow occurs when the sign bit of the inputs differs from the sign of the result + ex1_sgn00_32 <= not ex1_select_64bmode_q and not ex1_aop_32 and not ex1_bop_32 ; + ex1_sgn11_32 <= not ex1_select_64bmode_q and ex1_aop_32 and ex1_bop_32 ; + ex1_sgn00_64 <= ex1_select_64bmode_q and not ex1_aop_00 and not ex1_bop_00 ; + ex1_sgn11_64 <= ex1_select_64bmode_q and ex1_aop_00 and ex1_bop_00 ; + + ex1_ovf32_00_b <= not( ex1_add_rslt(32) and ex1_sgn00_32 ); + ex1_ovf32_11_b <= not( not ex1_add_rslt(32) and ex1_sgn11_32 ); + ex1_ovf64_00_b <= not( ex1_add_rslt(msb) and ex1_sgn00_64 ); + ex1_ovf64_11_b <= not( not ex1_add_rslt(msb) and ex1_sgn11_64 ); + + ex1_overflow <= not ( ex1_ovf64_00_b and + ex1_ovf64_11_b and + ex1_ovf32_00_b and + ex1_ovf32_11_b ); + + + + ex2_add_xer_ov <= ex2_overflow_q; + + --------------------------------------------------------------------- + -- Compare to 0 for record forms / compare instructions + --------------------------------------------------------------------- + + +add_64b_compare : if regsize = 64 generate + + or3232: entity work.xuq_alu_or3232(xuq_alu_or3232) + generic map (expand_type => expand_type) + port map( + d => log_add_ex2_rt(0 to 63) , + or_hi_b => ex2_cmp0_hi , + or_lo_b => ex2_cmp0_lo ); + + ex2_cmp0_eq <= (ex2_cmp0_hi or ex2_select_32bcmp_q) and ex2_cmp0_lo; + + with ex1_select_32bcmp select + ex2_rs0_msb_d <= byp_alu_ex1_rs0(32) when '1', + byp_alu_ex1_rs0(0) when others; + with ex1_select_32bcmp select + ex2_rs1_msb_d <= byp_alu_ex1_rs1(32) when '1', + byp_alu_ex1_rs1(0) when others; + with ex2_select_32bcmp_q select + ex2_rt_msb <= log_add_ex2_rt(32) when '1', + log_add_ex2_rt(0) when others; +end generate; + + + u_ex2_rt_bufi: alu_byp_ex2_rt_b <= not log_add_ex2_rt ; + u_ex2_rt_buf: alu_byp_ex2_rt <= not alu_byp_ex2_rt_b ; + +add_32b_compare : if regsize = 32 generate + ex2_cmp0_lo <= not or_reduce(log_add_ex2_rt(32 to 63)); + ex2_cmp0_hi <= '1'; + ex2_cmp0_eq <= ex2_cmp0_lo; + ex2_rs0_msb_d <= byp_alu_ex1_rs0(32); + ex2_rs1_msb_d <= byp_alu_ex1_rs1(32); + ex2_rt_msb <= log_add_ex2_rt(32); +end generate; + + -- If the signs are different, then we immediately know if one is bigger than the other, but only look at this in case of cmp + ex2_diff_sign <= (ex2_rs0_msb_q xor ex2_rs1_msb_q) and ex2_is_cmp_q; + + -- In case the sigs are not different, we need some more logic + with ex2_is_cmp_q select + ex2_sign_cmp <= ex2_add_xer_ca_q when '1', -- Look at carry out for compares (need to be able to check over flow case) + ex2_rt_msb when others; -- Look at sign bit for record forms (overflow is ignored, ie two positives equal a negative.) + + ex2_rslt_gt_s <= ((ex2_rs1_msb_q and ex2_diff_sign) or (not ex2_sign_cmp and not ex2_diff_sign)) and not ex2_cmp0_eq; -- RS1 < RS0 + ex2_rslt_lt_s <= ((ex2_rs0_msb_q and ex2_diff_sign) or ( ex2_sign_cmp and not ex2_diff_sign)) and not ex2_cmp0_eq; -- RS1 > RS0 + + ex2_rslt_gt_u <= ((ex2_rs0_msb_q and ex2_diff_sign) or (not ex2_sign_cmp and not ex2_diff_sign)) and not ex2_cmp0_eq; -- RS1 < RS0 + ex2_rslt_lt_u <= ((ex2_rs1_msb_q and ex2_diff_sign) or ( ex2_sign_cmp and not ex2_diff_sign)) and not ex2_cmp0_eq; -- RS1 > RS0 + + ex2_cmp_eq <= ex2_cmp0_eq; + ex2_cmp_gt <= (not ex2_is_cmpl_q and ex2_rslt_gt_s) or (ex2_is_cmpl_q and ex2_rslt_gt_u); + ex2_cmp_lt <= (not ex2_is_cmpl_q and ex2_rslt_lt_s) or (ex2_is_cmpl_q and ex2_rslt_lt_u); + + ex2_cr_recform <= ex2_cmp_lt & ex2_cmp_gt & ex2_cmp_eq & ex2_overflow_q; + + ex3_trap_val_d <= ex2_tw_cmpsel_q(0) and ( + (ex2_tw_cmpsel_q(1) and ex2_rslt_lt_s) or + (ex2_tw_cmpsel_q(2) and ex2_rslt_gt_s) or + (ex2_tw_cmpsel_q(3) and ex2_cmp_eq) or + (ex2_tw_cmpsel_q(4) and ex2_rslt_lt_u) or + (ex2_tw_cmpsel_q(5) and ex2_rslt_gt_u)); + + ex3_trap_val <= ex3_trap_val_q; + + -- Determine Carry + with ex1_select_32bcmp select + ex2_add_xer_ca_d <= ex1_cout_32 when '1', + ex1_cout_00 when others; + + ex2_add_xer_ca <= ex2_add_xer_ca_q; + +add_64b_retval : if regsize = 64 generate + add_log_ex1_add_rt <= ex1_add_rslt; + ex2_eff_addr_d <= (ex1_add_rslt(0 to 31) and (0 to 31 => ex1_select_64bmode_q)) & ex1_add_rslt(32 to 63); +end generate; +add_32b_retval : if regsize = 32 generate + add_log_ex1_add_rt <= ex1_add_rslt(32 to 63); + ex2_eff_addr_d <= ex1_add_rslt(32 to 63); +end generate; + + -- Send out eff addr signals + -- Do a seperate add for the DATA rlm. + -- The ALU add is slow on these bits, and we don't want extra loads. + u_eff0_inv1: eff0_b <= not byp_alu_ex1_rs0(64-(dc_size-3) to 63) ; + u_eff0_inv2: eff0 <= not eff0_b ; + u_eff1_inv1: eff1_b <= not byp_alu_ex1_rs1(64-(dc_size-3) to 63) ; + u_eff1_inv2: eff1 <= not eff1_b ; + + xu_ex1_eff_addr_int <= std_ulogic_vector( unsigned(eff0) + unsigned(eff1) ); + + xu_ex2_eff_addr <= ex2_eff_addr_q; + + --------------------------------------------------------------------- + -- Latch instances + --------------------------------------------------------------------- + ex1_add_act_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_add_act_offset), + scout => sov(ex1_add_act_offset), + din => dec_alu_rf1_add_act, + dout => ex1_add_act_q); + ex1_add_ci_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => dec_alu_rf1_add_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_add_ci_offset), + scout => sov(ex1_add_ci_offset), + din => dec_alu_rf1_add_ci, + dout => ex1_add_ci_q); + ex1_is_cmpl_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => dec_alu_rf1_add_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_cmpl_offset), + scout => sov(ex1_is_cmpl_offset), + din => dec_alu_rf1_is_cmpl, + dout => ex1_is_cmpl_q); + ex1_tw_cmpsel_latch : tri_rlmreg_p + generic map (width => ex1_tw_cmpsel_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => dec_alu_rf1_add_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_tw_cmpsel_offset to ex1_tw_cmpsel_offset + ex1_tw_cmpsel_q'length-1), + scout => sov(ex1_tw_cmpsel_offset to ex1_tw_cmpsel_offset + ex1_tw_cmpsel_q'length-1), + din => dec_alu_rf1_tw_cmpsel, + dout => ex1_tw_cmpsel_q); + ex2_add_xer_ca_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => ex1_add_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_add_xer_ca_offset), + scout => sov(ex2_add_xer_ca_offset), + din => ex2_add_xer_ca_d, + dout => ex2_add_xer_ca_q); + ex2_rs0_msb_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_rs0_msb_offset), + scout => sov(ex2_rs0_msb_offset), + din => ex2_rs0_msb_d, + dout => ex2_rs0_msb_q); + ex2_rs1_msb_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_rs1_msb_offset), + scout => sov(ex2_rs1_msb_offset), + din => ex2_rs1_msb_d, + dout => ex2_rs1_msb_q); + ex2_is_cmpl_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_is_cmpl_offset), + scout => sov(ex2_is_cmpl_offset), + din => ex1_is_cmpl_q, + dout => ex2_is_cmpl_q); + ex2_overflow_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_overflow_offset), + scout => sov(ex2_overflow_offset), + din => ex1_overflow, + dout => ex2_overflow_q); + ex2_tw_cmpsel_latch : tri_rlmreg_p + generic map (width => ex2_tw_cmpsel_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_tw_cmpsel_offset to ex2_tw_cmpsel_offset + ex2_tw_cmpsel_q'length-1), + scout => sov(ex2_tw_cmpsel_offset to ex2_tw_cmpsel_offset + ex2_tw_cmpsel_q'length-1), + din => ex1_tw_cmpsel_q, + dout => ex2_tw_cmpsel_q); + ex2_is_cmp_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_is_cmp_offset), + scout => sov(ex2_is_cmp_offset), + din => dec_alu_ex1_is_cmp, + dout => ex2_is_cmp_q); + ex3_trap_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_trap_val_offset), + scout => sov(ex3_trap_val_offset), + din => ex3_trap_val_d, + dout => ex3_trap_val_q); + ex1_select_64bmode_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_select_64bmode_offset), + scout => sov(ex1_select_64bmode_offset), + din => dec_alu_rf1_select_64bmode, + dout => ex1_select_64bmode_q); + ex2_select_32bcmp_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_select_32bcmp_offset), + scout => sov(ex2_select_32bcmp_offset), + din => ex1_select_32bcmp, + dout => ex2_select_32bcmp_q); + + + +ex2_lcb: entity tri.tri_lcbnd(tri_lcbnd) + port map(vd => vdd, + gd => gnd, + act => ex1_add_act_q, + nclk => nclk, + forcee => func_sl_force, + thold_b => func_sl_thold_0_b, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + sg => sg_0, + lclk => ex2_lclk_int, + d1clk => ex2_d1clk_int, + d2clk => ex2_d2clk_int); + +ex1_lcb: entity tri.tri_lcbnd(tri_lcbnd) + port map(vd => vdd, + gd => gnd, + act => dec_alu_rf1_add_act, + nclk => nclk, + forcee => func_sl_force, + thold_b => func_sl_thold_0_b, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + sg => sg_0, + lclk => ex1_lclk_int, + d1clk => ex1_d1clk_int, + d2clk => ex1_d2clk_int); + + + ex2_eff_addr_lat: entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width => ex2_eff_addr_q'length, expand_type => expand_type, btr => "NLI0001_X1_A12TH", init=>(ex2_eff_addr_q'range=>'0')) + port map (vd => vdd, gd => gnd, + LCLK => ex2_lclk_int, + D1CLK => ex2_d1clk_int, + D2CLK => ex2_d2clk_int, + SCANIN => siv(ex2_eff_addr_offset to ex2_eff_addr_offset + ex2_eff_addr_q'length-1), + SCANOUT => sov(ex2_eff_addr_offset to ex2_eff_addr_offset + ex2_eff_addr_q'length-1), + D => ex2_eff_addr_d, + QB => ex2_eff_addr_q_b ); + + u_ex2_eff_addr_q: ex2_eff_addr_q <= not ex2_eff_addr_q_b ; + + ex1_rs0_inv_lat: entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width => ex1_rs0_inv_q'length, expand_type => expand_type, btr => "NLI0001_X1_A12TH", init=>(ex1_rs0_inv_q'range=>'0')) + port map (vd => vdd, gd => gnd, + LCLK => ex1_lclk_int, + D1CLK => ex1_d1clk_int, + D2CLK => ex1_d2clk_int, + SCANIN => siv(ex1_rs0_inv_offset to ex1_rs0_inv_offset + ex1_rs0_inv_q'length-1), + SCANOUT => sov(ex1_rs0_inv_offset to ex1_rs0_inv_offset + ex1_rs0_inv_q'length-1), + D => dec_alu_rf1_add_rs0_inv, + QB => ex1_rs0_inv_q_b ); + + u_ex1_rs0_inv_q: ex1_rs0_inv_q <= not ex1_rs0_inv_q_b ; + + + + siv(0 to siv'right) <= sov(1 to siv'right) & scan_in; + scan_out <= sov(0); + +end architecture xuq_alu_add; diff --git a/rel/src/vhdl/work/xuq_alu_caor.vhdl b/rel/src/vhdl/work/xuq_alu_caor.vhdl new file mode 100644 index 0000000..bd81266 --- /dev/null +++ b/rel/src/vhdl/work/xuq_alu_caor.vhdl @@ -0,0 +1,137 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XU Merge Or-Reduce Component +-- +LIBRARY ieee; USE ieee.std_logic_1164.all; + use ieee.numeric_std.all; +LIBRARY ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; +LIBRARY support; + use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity xuq_alu_caor is generic(expand_type: integer := 2 ); port ( + + ca_root_b :in std_ulogic_vector(0 to 63) ;--data + ca_or_hi :out std_ulogic ;-- upper 32 ORed together + ca_or_lo :out std_ulogic -- lower 32 ORed together +); + +-- synopsys translate_off +-- synopsys translate_on +end xuq_alu_caor; + +architecture xuq_alu_caor of xuq_alu_caor is + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + + signal ca_or_lv1 :std_ulogic_vector(0 to 31) ; + signal ca_or_lv2_b :std_ulogic_vector(0 to 15) ; + signal ca_or_lv3 :std_ulogic_vector(0 to 7) ; + signal ca_or_lv4_b :std_ulogic_vector(0 to 3) ; + signal ca_or_lv5 :std_ulogic_vector(0 to 1) ; + + +begin + + + u_ca_or_00: ca_or_lv1 ( 0) <= not( ca_root_b ( 0) and ca_root_b ( 1) ); + u_ca_or_02: ca_or_lv1 ( 1) <= not( ca_root_b ( 2) and ca_root_b ( 3) ); + u_ca_or_04: ca_or_lv1 ( 2) <= not( ca_root_b ( 4) and ca_root_b ( 5) ); + u_ca_or_06: ca_or_lv1 ( 3) <= not( ca_root_b ( 6) and ca_root_b ( 7) ); + u_ca_or_08: ca_or_lv1 ( 4) <= not( ca_root_b ( 8) and ca_root_b ( 9) ); + u_ca_or_10: ca_or_lv1 ( 5) <= not( ca_root_b (10) and ca_root_b (11) ); + u_ca_or_12: ca_or_lv1 ( 6) <= not( ca_root_b (12) and ca_root_b (13) ); + u_ca_or_14: ca_or_lv1 ( 7) <= not( ca_root_b (14) and ca_root_b (15) ); + u_ca_or_16: ca_or_lv1 ( 8) <= not( ca_root_b (16) and ca_root_b (17) ); + u_ca_or_18: ca_or_lv1 ( 9) <= not( ca_root_b (18) and ca_root_b (19) ); + u_ca_or_20: ca_or_lv1 (10) <= not( ca_root_b (20) and ca_root_b (21) ); + u_ca_or_22: ca_or_lv1 (11) <= not( ca_root_b (22) and ca_root_b (23) ); + u_ca_or_24: ca_or_lv1 (12) <= not( ca_root_b (24) and ca_root_b (25) ); + u_ca_or_26: ca_or_lv1 (13) <= not( ca_root_b (26) and ca_root_b (27) ); + u_ca_or_28: ca_or_lv1 (14) <= not( ca_root_b (28) and ca_root_b (29) ); + u_ca_or_30: ca_or_lv1 (15) <= not( ca_root_b (30) and ca_root_b (31) ); + u_ca_or_32: ca_or_lv1 (16) <= not( ca_root_b (32) and ca_root_b (33) ); + u_ca_or_34: ca_or_lv1 (17) <= not( ca_root_b (34) and ca_root_b (35) ); + u_ca_or_36: ca_or_lv1 (18) <= not( ca_root_b (36) and ca_root_b (37) ); + u_ca_or_38: ca_or_lv1 (19) <= not( ca_root_b (38) and ca_root_b (39) ); + u_ca_or_40: ca_or_lv1 (20) <= not( ca_root_b (40) and ca_root_b (41) ); + u_ca_or_42: ca_or_lv1 (21) <= not( ca_root_b (42) and ca_root_b (43) ); + u_ca_or_44: ca_or_lv1 (22) <= not( ca_root_b (44) and ca_root_b (45) ); + u_ca_or_46: ca_or_lv1 (23) <= not( ca_root_b (46) and ca_root_b (47) ); + u_ca_or_48: ca_or_lv1 (24) <= not( ca_root_b (48) and ca_root_b (49) ); + u_ca_or_50: ca_or_lv1 (25) <= not( ca_root_b (50) and ca_root_b (51) ); + u_ca_or_52: ca_or_lv1 (26) <= not( ca_root_b (52) and ca_root_b (53) ); + u_ca_or_54: ca_or_lv1 (27) <= not( ca_root_b (54) and ca_root_b (55) ); + u_ca_or_56: ca_or_lv1 (28) <= not( ca_root_b (56) and ca_root_b (57) ); + u_ca_or_58: ca_or_lv1 (29) <= not( ca_root_b (58) and ca_root_b (59) ); + u_ca_or_60: ca_or_lv1 (30) <= not( ca_root_b (60) and ca_root_b (61) ); + u_ca_or_62: ca_or_lv1 (31) <= not( ca_root_b (62) and ca_root_b (63) ); + + u_ca_or_01: ca_or_lv2_b( 0) <= not( ca_or_lv1 ( 0) or ca_or_lv1 ( 1) ); + u_ca_or_05: ca_or_lv2_b( 1) <= not( ca_or_lv1 ( 2) or ca_or_lv1 ( 3) ); + u_ca_or_09: ca_or_lv2_b( 2) <= not( ca_or_lv1 ( 4) or ca_or_lv1 ( 5) ); + u_ca_or_13: ca_or_lv2_b( 3) <= not( ca_or_lv1 ( 6) or ca_or_lv1 ( 7) ); + u_ca_or_17: ca_or_lv2_b( 4) <= not( ca_or_lv1 ( 8) or ca_or_lv1 ( 9) ); + u_ca_or_21: ca_or_lv2_b( 5) <= not( ca_or_lv1 (10) or ca_or_lv1 (11) ); + u_ca_or_25: ca_or_lv2_b( 6) <= not( ca_or_lv1 (12) or ca_or_lv1 (13) ); + u_ca_or_29: ca_or_lv2_b( 7) <= not( ca_or_lv1 (14) or ca_or_lv1 (15) ); + u_ca_or_33: ca_or_lv2_b( 8) <= not( ca_or_lv1 (16) or ca_or_lv1 (17) ); + u_ca_or_37: ca_or_lv2_b( 9) <= not( ca_or_lv1 (18) or ca_or_lv1 (19) ); + u_ca_or_41: ca_or_lv2_b(10) <= not( ca_or_lv1 (20) or ca_or_lv1 (21) ); + u_ca_or_45: ca_or_lv2_b(11) <= not( ca_or_lv1 (22) or ca_or_lv1 (23) ); + u_ca_or_49: ca_or_lv2_b(12) <= not( ca_or_lv1 (24) or ca_or_lv1 (25) ); + u_ca_or_53: ca_or_lv2_b(13) <= not( ca_or_lv1 (26) or ca_or_lv1 (27) ); + u_ca_or_57: ca_or_lv2_b(14) <= not( ca_or_lv1 (28) or ca_or_lv1 (29) ); + u_ca_or_61: ca_or_lv2_b(15) <= not( ca_or_lv1 (30) or ca_or_lv1 (31) ); + + u_ca_or_03: ca_or_lv3 ( 0) <= not( ca_or_lv2_b( 0) and ca_or_lv2_b( 1) ); + u_ca_or_11: ca_or_lv3 ( 1) <= not( ca_or_lv2_b( 2) and ca_or_lv2_b( 3) ); + u_ca_or_19: ca_or_lv3 ( 2) <= not( ca_or_lv2_b( 4) and ca_or_lv2_b( 5) ); + u_ca_or_27: ca_or_lv3 ( 3) <= not( ca_or_lv2_b( 6) and ca_or_lv2_b( 7) ); + u_ca_or_35: ca_or_lv3 ( 4) <= not( ca_or_lv2_b( 8) and ca_or_lv2_b( 9) ); + u_ca_or_43: ca_or_lv3 ( 5) <= not( ca_or_lv2_b(10) and ca_or_lv2_b(11) ); + u_ca_or_51: ca_or_lv3 ( 6) <= not( ca_or_lv2_b(12) and ca_or_lv2_b(13) ); + u_ca_or_59: ca_or_lv3 ( 7) <= not( ca_or_lv2_b(14) and ca_or_lv2_b(15) ); + + u_ca_or_07: ca_or_lv4_b( 0) <= not( ca_or_lv3 ( 0) or ca_or_lv3 ( 1) ); + u_ca_or_23: ca_or_lv4_b( 1) <= not( ca_or_lv3 ( 2) or ca_or_lv3 ( 3) ); + u_ca_or_39: ca_or_lv4_b( 2) <= not( ca_or_lv3 ( 4) or ca_or_lv3 ( 5) ); + u_ca_or_55: ca_or_lv4_b( 3) <= not( ca_or_lv3 ( 6) or ca_or_lv3 ( 7) ); + + u_ca_or_15: ca_or_lv5 ( 0) <= not( ca_or_lv4_b( 0) and ca_or_lv4_b( 1) ); + u_ca_or_47: ca_or_lv5 ( 1) <= not( ca_or_lv4_b( 2) and ca_or_lv4_b( 3) ); + + ca_or_hi <= ca_or_lv5(0); -- rename + ca_or_lo <= ca_or_lv5(1); -- rename + +end architecture xuq_alu_caor; diff --git a/rel/src/vhdl/work/xuq_alu_div.vhdl b/rel/src/vhdl/work/xuq_alu_div.vhdl new file mode 100644 index 0000000..0cc1320 --- /dev/null +++ b/rel/src/vhdl/work/xuq_alu_div.vhdl @@ -0,0 +1,1156 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XU Divide +-- +library ieee,ibm,support,tri,work; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ibm.std_ulogic_function_support.all; +use support.power_logic_pkg.all; +use tri.tri_latches_pkg.all; +use work.xuq_pkg.all; + +entity xuq_alu_div is + generic( + expand_type : integer := 2; + regsize : integer := 64); + port( + -- Clocks + nclk : in clk_logic; + + -- Power + vdd : inout power_logic; + gnd : inout power_logic; + + -- Pervasive + d_mode_dc : in std_ulogic; + delay_lclkr_dc : in std_ulogic; + mpw1_dc_b : in std_ulogic; + mpw2_dc_b : in std_ulogic; + func_sl_force : in std_ulogic; + func_sl_thold_0_b : in std_ulogic; + sg_0 : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + -- Decode Inputs + fxa_fxb_rf1_div_ctr : in std_ulogic_vector(0 to 7); + dec_alu_rf1_div_val : in std_ulogic; + dec_alu_rf1_div_sign : in std_ulogic; -- 0: Unsigned, 1: Signed + dec_alu_rf1_div_size : in std_ulogic; -- 0: 32x32, 1: 64x64 + dec_alu_rf1_div_extd : in std_ulogic; -- 0: regular, 1: extended + dec_alu_rf1_div_recform : in std_ulogic; + dec_alu_rf1_xer_ov_update : in std_ulogic; + + -- Source Data + byp_alu_ex1_divsrc_0 : in std_ulogic_vector(64-regsize to 63); -- NUM/DIVIDEND/RA + byp_alu_ex1_divsrc_1 : in std_ulogic_vector(64-regsize to 63); -- DEN/DIVISOR /RB + + -- Flush cycle counter + fxa_fxb_ex1_hold_ctr_flush : in std_ulogic; + + -- Target Data + alu_dec_div_need_hole : out std_ulogic; + alu_byp_ex3_div_rt : out std_ulogic_vector(64-regsize to 63); + alu_ex2_div_done : out std_ulogic; + + -- Overflow + ex3_div_xer_ov : out std_ulogic; + ex3_div_xer_ov_update : out std_ulogic; + + -- Record form + alu_byp_ex3_cr_div : out std_ulogic_vector(0 to 4); + + -- CM + ex2_spr_msr_cm : in std_ulogic + ); +-- synopsys translate_off + +-- synopsys translate_on +end xuq_alu_div; + +architecture xuq_alu_div of xuq_alu_div is + constant msb : integer := 64-regsize; -- 0 in 64 bit core, 32 in 32 bit core + subtype s2 is std_ulogic_vector(0 to 1); + -- Latches + signal ex1_div_ctr_q : std_ulogic_vector(0 to 7); + signal ex1_div_val_q : std_ulogic; + signal ex1_div_sign_q : std_ulogic; + signal ex1_div_size_q : std_ulogic; + signal ex1_div_extd_q : std_ulogic; + signal ex1_div_recform_q : std_ulogic; + signal ex1_xer_ov_update_q : std_ulogic; + signal ex2_div_val_q : std_ulogic; + signal ex1_cycle_act, ex2_cycle_act_q : std_ulogic; + signal ex2_cycles_d, ex2_cycles_q : std_ulogic_vector(0 to 7); + signal ex2_denom_d, ex2_denom_q : std_ulogic_vector(msb to 63); + signal ex2_numer_d, ex2_numer_q : std_ulogic_vector(msb to 64); + signal ex2_dmask_d, ex2_dmask_q : std_ulogic_vector(msb to 63); + signal ex2_div_ovf_q : std_ulogic; + signal ex2_xer_ov_update_q : std_ulogic; + signal ex2_div_recform_q : std_ulogic; + signal ex2_div_size_q : std_ulogic; + signal ex2_div_sign_q : std_ulogic; + signal ex2_div_extd_q : std_ulogic; + signal ex2_2s_rslt_q : std_ulogic; + signal ex2_div_done_q : std_ulogic; + signal ex3_div_val_q : std_ulogic; + signal ex3_cycle_watch_d, ex3_cycle_watch_q : std_ulogic; + signal ex3_quot_watch_d, ex3_quot_watch_q : std_ulogic; + signal ex3_div_ovf_d, ex3_div_ovf_q : std_ulogic; + signal ex3_xer_ov_update_q : std_ulogic; + signal ex3_div_done_q : std_ulogic; + signal ex3_quotient_d, ex3_quotient_q : std_ulogic_vector(msb to 63); + signal ex3_div_recform_q : std_ulogic; + signal ex3_div_size_q : std_ulogic; + signal ex3_2s_rslt_q : std_ulogic; + signal ex3_div_rt_d, ex3_div_rt_q : std_ulogic_vector(msb to 63); + signal ex2_numer_eq_zero_q, ex2_numer_eq_zero_d : std_ulogic; + signal ex2_div_ovf_cond3, ex3_div_ovf_cond3_q : std_ulogic; + signal ex3_spr_msr_cm_q : std_ulogic; + signal need_hole_q, need_hole_d : std_ulogic; + -- Scanchains + constant ex1_div_ctr_offset : integer := 0; + constant ex1_div_val_offset : integer := ex1_div_ctr_offset + ex1_div_ctr_q'length; + constant ex1_div_sign_offset : integer := ex1_div_val_offset + 1; + constant ex1_div_size_offset : integer := ex1_div_sign_offset + 1; + constant ex1_div_extd_offset : integer := ex1_div_size_offset + 1; + constant ex1_div_recform_offset : integer := ex1_div_extd_offset + 1; + constant ex1_xer_ov_update_offset : integer := ex1_div_recform_offset + 1; + constant ex2_div_val_offset : integer := ex1_xer_ov_update_offset + 1; + constant ex2_cycle_act_offset : integer := ex2_div_val_offset + 1; + constant ex2_cycles_offset : integer := ex2_cycle_act_offset + 1; + constant ex2_denom_offset : integer := ex2_cycles_offset + ex2_cycles_q'length; + constant ex2_numer_offset : integer := ex2_denom_offset + ex2_denom_q'length; + constant ex2_dmask_offset : integer := ex2_numer_offset + ex2_numer_q'length; + constant ex2_div_ovf_offset : integer := ex2_dmask_offset + ex2_dmask_q'length; + constant ex2_xer_ov_update_offset : integer := ex2_div_ovf_offset + 1; + constant ex2_div_recform_offset : integer := ex2_xer_ov_update_offset + 1; + constant ex2_div_size_offset : integer := ex2_div_recform_offset + 1; + constant ex2_div_sign_offset : integer := ex2_div_size_offset + 1; + constant ex2_div_extd_offset : integer := ex2_div_sign_offset + 1; + constant ex2_2s_rslt_offset : integer := ex2_div_extd_offset + 1; + constant ex2_div_done_offset : integer := ex2_2s_rslt_offset + 1; + constant ex3_div_val_offset : integer := ex2_div_done_offset + 1; + constant ex3_cycle_watch_offset : integer := ex3_div_val_offset + 1; + constant ex3_quot_watch_offset : integer := ex3_cycle_watch_offset + 1; + constant ex3_div_ovf_offset : integer := ex3_quot_watch_offset + 1; + constant ex3_xer_ov_update_offset : integer := ex3_div_ovf_offset + 1; + constant ex3_div_done_offset : integer := ex3_xer_ov_update_offset + 1; + constant ex3_quotient_offset : integer := ex3_div_done_offset + 1; + constant ex3_div_recform_offset : integer := ex3_quotient_offset + ex3_quotient_q'length; + constant ex3_div_size_offset : integer := ex3_div_recform_offset + 1; + constant ex3_2s_rslt_offset : integer := ex3_div_size_offset + 1; + constant ex3_div_rt_offset : integer := ex3_2s_rslt_offset + 1; + constant ex2_numer_eq_zero_offset : integer := ex3_div_rt_offset + ex3_div_rt_q'length; + constant ex3_div_ovf_cond3_offset : integer := ex2_numer_eq_zero_offset + 1; + constant ex3_spr_msr_cm_offset : integer := ex3_div_ovf_cond3_offset + 1; + constant need_hole_offset : integer := ex3_spr_msr_cm_offset + 1; + constant scan_right : integer := need_hole_offset + 1; + signal sov,siv : std_ulogic_vector(0 to scan_right-1); + -- Signals + signal ex2_denom_shift : std_ulogic_vector(msb to 63); + signal ex2_denom_shift_ctrl : std_ulogic; + signal ex2_sub_or_restore : std_ulogic_vector(msb to 64); + signal ex2_sub_or_restore_ctrl : std_ulogic_vector(0 to 1); + signal ex2_sub_rslt_shift : std_ulogic_vector(msb to 64); + signal ex2_numer_shift : std_ulogic_vector(msb to 64); + signal ex1_denom : std_ulogic_vector(msb to 63); + signal ex1_numer : std_ulogic_vector(msb to 63); + signal mask : std_ulogic_vector(msb to 63); + signal ex2_sub_rslt : std_ulogic_vector(msb to 64); + signal ex1_div_done : std_ulogic; + signal ex1_num_cmp0_lo_nomsb, ex1_num_cmp0_hi_nomsb : std_ulogic; + signal ex1_num_cmp0_lo, ex1_num_cmp0_hi : std_ulogic; + signal ex1_den_cmp0_lo, ex1_den_cmp0_hi : std_ulogic; + signal ex1_den_cmp1_lo, ex1_den_cmp1_hi : std_ulogic; + signal ex3_qot_cmp0_lo, ex3_qot_cmp0_hi : std_ulogic; + signal ex1_div_ovf_cond1_wd, ex1_div_ovf_cond1_dw : std_ulogic; + signal ex1_div_ovf_cond1 : std_ulogic; + signal ex1_div_ovf_cond2 : std_ulogic; + signal ex2_div_ovf_cond4 : std_ulogic; + signal ex2_rslt_sign : std_ulogic; + signal ex2_den_eq_num, ex2_den_gte_num : std_ulogic; + signal ex1_div_ovf : std_ulogic; + signal ex1_divsrc_0, ex1_divsrc_0_2s : std_ulogic_vector(msb to 63); + signal ex1_divsrc_1, ex1_divsrc_1_2s : std_ulogic_vector(msb to 63); + signal ex1_2s_rslt : std_ulogic; + signal ex1_src0_sign, ex1_src1_sign : std_ulogic; + signal ex1_div_cnt_done : std_ulogic; + signal ex3_cmp0_undef : std_ulogic; + signal ex3_cmp0_eq : std_ulogic; + signal ex3_cmp0_gt : std_ulogic; + signal ex3_cmp0_lt : std_ulogic; + signal ex3_quotient_2s : std_ulogic_vector(msb to 63); + signal ex2_cycles_din : std_ulogic_vector(0 to 7); + signal ex2_cycles_gt_64, ex2_cycles_gt_32 : std_ulogic; + signal ex3_lt : std_ulogic; + signal ex2_quot_pushbit : std_ulogic; + signal ex2_denom_rot : std_ulogic_vector(msb to 63); + signal ex3_div_rt : std_ulogic_vector(msb to 63); + signal ex2_numer_act, ex2_denom_act : std_ulogic; + signal tiup, tidn : std_ulogic; + +begin + +-- def divide(num,den,size): +-- q = 0 +-- m = pow(2,size)-1 +-- cycle = size+1 +-- +-- # Normalize +-- p = m +-- +-- while cycle>0: +-- r = den & p +-- if r == 0: +-- break +-- den = rotR1(den,size) +-- p = p>>1 +-- cycle -= 1 +-- +-- den = ((~den + 1) & m) | 2**size +-- size = size + 1 +-- m = pow(2,size)-1 +-- +-- # Divide +-- while cycle>0: +-- # Subtract +-- a = (num+den) & m +-- if signbit(a,size)==0: # Positive +-- q = rotL1(q,size,m) | 1 # 0b...x | 0b0001 = 0b...1 +-- num = rotL1(a,size,m) +-- else: +-- q = rotL1(q,size,m) & -2 # 0b...x & 0b1110 = 0b...0 +-- num = rotL1(num,size,m) +-- cycle -= 1 +-- return q + +tiup <= '1'; +tidn <= '0'; + +--------------------------------------------------------------------- +-- Initialize cycle counter +--------------------------------------------------------------------- +with ex1_div_val_q select + ex2_cycles_din <= ex1_div_ctr_q when '1', + std_ulogic_vector(unsigned(ex2_cycles_q) - 1) when others; + +-- Clear counter if the divide was flushed +ex2_cycles_d <= gate(ex2_cycles_din,not(fxa_fxb_ex1_hold_ctr_flush)); + +ex1_cycle_act <= ex1_div_val_q or (ex2_cycle_act_q and or_reduce(ex2_cycles_q)); + +ex1_div_cnt_done <= '1' when ex2_cycles_q = "00000001" else '0'; + +ex1_div_done <= ex1_div_cnt_done and not fxa_fxb_ex1_hold_ctr_flush; + +alu_ex2_div_done <= ex2_div_done_q; + +--------------------------------------------------------------------- +-- 2's complement negative operands for signed divide +--------------------------------------------------------------------- +ex1_divsrc_0_2s <= std_ulogic_vector(unsigned(not byp_alu_ex1_divsrc_0) + 1); +ex1_divsrc_1_2s <= std_ulogic_vector(unsigned(not byp_alu_ex1_divsrc_1) + 1); + +-- Need to 2's complement the result if one of the operands is negative +div_64b_2scomp : if regsize = 64 generate + with ex1_div_size_q select + ex1_2s_rslt <= (byp_alu_ex1_divsrc_0(0) xor byp_alu_ex1_divsrc_1(0) ) and ex1_div_sign_q when '1', + (byp_alu_ex1_divsrc_0(32) xor byp_alu_ex1_divsrc_1(32)) and ex1_div_sign_q when others; + + with ex1_div_size_q select + ex1_src0_sign <= byp_alu_ex1_divsrc_0(0) when '1', + byp_alu_ex1_divsrc_0(32) when others; + + with ex1_div_size_q select + ex1_src1_sign <= byp_alu_ex1_divsrc_1(0) when '1', + byp_alu_ex1_divsrc_1(32) when others; +end generate; +div_32b_2scomp : if regsize = 32 generate + ex1_2s_rslt <= (byp_alu_ex1_divsrc_0(32) xor byp_alu_ex1_divsrc_1(32)) and ex1_div_sign_q; + ex1_src0_sign <= byp_alu_ex1_divsrc_0(32); + ex1_src1_sign <= byp_alu_ex1_divsrc_1(32); +end generate; + + +with (ex1_div_sign_q and ex1_src0_sign) select + ex1_divsrc_0 <= ex1_divsrc_0_2s when '1', + byp_alu_ex1_divsrc_0 when others; + +with (ex1_div_sign_q and ex1_src1_sign) select + ex1_divsrc_1 <= ex1_divsrc_1_2s when '1', + byp_alu_ex1_divsrc_1 when others; + + +--------------------------------------------------------------------- +-- Fixup Operands for Word/DW Mode +--------------------------------------------------------------------- +div_setup_64b : if regsize = 64 generate + + with ex1_div_size_q select + ex1_denom(0 to 31) <= ex1_divsrc_1(0 to 31) when '1', + ex1_divsrc_1(32 to 63) when others; + + ex1_denom(32 to 63) <= gate(ex1_divsrc_1(32 to 63),ex1_div_size_q); + + + with ex1_div_size_q select + ex1_numer(0 to 31) <= ex1_divsrc_0(0 to 31) when '1', + ex1_divsrc_0(32 to 63) when others; + + ex1_numer(32 to 63) <= gate(ex1_divsrc_0(32 to 63),ex1_div_size_q); + + + mask <= (0 to 31=>tiup) & (32 to 63=>ex1_div_size_q); + + + -- Rotate just the upper 32 for word mode + with ex1_div_size_q select + ex2_denom_rot(0) <= ex2_denom_q(63) when '1', + ex2_denom_q(31) when others; + + ex2_denom_rot(1 to 31) <= ex2_denom_q(msb to 30); + ex2_denom_rot(32 to 63) <= gate(ex2_denom_q(31 to 62),ex2_div_size_q); + +end generate; +div_setup_32b : if regsize = 32 generate + + ex1_denom <= ex1_divsrc_1; + ex1_numer <= ex1_divsrc_0; + + mask <= (32 to 63=>tiup); + + ex2_denom_rot <= ex2_denom_q(63) & ex2_denom_q(msb to 62); + +end generate; + +--------------------------------------------------------------------- +-- Normalize Denominator +--------------------------------------------------------------------- +-- Grab denominator from bypass, shift until normalized, then hold. +with ex1_div_val_q select + ex2_denom_d <= ex1_denom when '1', + ex2_denom_shift when others; + +-- Mask +with ex1_div_val_q select + ex2_dmask_d <= mask when '1', + '0' & ex2_dmask_q(msb to 62) when others; + +ex2_denom_shift_ctrl <= or_reduce(ex2_denom_q and ex2_dmask_q); + + +with ex2_denom_shift_ctrl select + ex2_denom_shift <= ex2_denom_rot when '1', + ex2_denom_q when others; + +ex2_denom_act <= ex1_div_val_q or ex2_denom_shift_ctrl; + +--------------------------------------------------------------------- +-- Work on Numerator +--------------------------------------------------------------------- +with ex1_div_val_q select + ex2_numer_d <= '0' & ex1_numer when '1', + ex2_sub_or_restore when others; + + +ex2_numer_act <= ex1_div_val_q or ex1_cycle_act; + +--------------------------------------------------------------------- +-- Adder +--------------------------------------------------------------------- +ex2_sub_rslt <= std_ulogic_vector(unsigned(ex2_numer_q) - unsigned('0' & ex2_denom_q)); + + + +--------------------------------------------------------------------- +-- Decide to subtract or restore +--------------------------------------------------------------------- +ex2_sub_rslt_shift <= ex2_sub_rslt(msb+1 to 64) & '0'; +ex2_numer_shift <= ex2_numer_q(msb+1 to 64) & ex2_numer_q(msb); + + +ex2_sub_or_restore_ctrl <= (not ex2_denom_shift_ctrl) & ex2_sub_rslt(msb); + +with ex2_sub_or_restore_ctrl select + ex2_sub_or_restore <= ex2_sub_rslt_shift when "10", + ex2_numer_shift when "11", + ex2_numer_q when others; + +--------------------------------------------------------------------- +-- Quotient +--------------------------------------------------------------------- +ex2_quot_pushbit <= not ex2_denom_shift_ctrl and not ex2_sub_rslt(msb); + +with ex2_div_val_q select + ex3_quotient_d <= (msb to 63=>tidn) when '1', + ex3_quotient_q(msb+1 to 63) & ex2_quot_pushbit when others; + +-- 2's complement quotient if necessary for signed divide +ex3_quotient_2s <= std_ulogic_vector(unsigned(not ex3_quotient_q) + 1); + +--------------------------------------------------------------------- +-- Assert done signal to clear barrier, get hole +--------------------------------------------------------------------- +need_hole_d <= '1' when ex2_cycles_q = "00000111" else '0'; +alu_dec_div_need_hole <= need_hole_q; + +--------------------------------------------------------------------- +-- Return quotient +--------------------------------------------------------------------- +with ex3_2s_rslt_q select + ex3_div_rt_d <= ex3_quotient_2s when '1', + ex3_quotient_q when others; + +with ex2_div_size_q select + ex2_rslt_sign <= ex3_div_rt_d(msb) when '1', + ex3_div_rt_d(32) when others; + +-- Return Zero for all undefined cases +div_rslt_64b : if regsize = 64 generate + ex3_div_rt(0 to 31) <= gate(ex3_div_rt_q(0 to 31),not(ex3_div_ovf_q or not ex3_div_size_q)); +end generate; + ex3_div_rt(32 to 63) <= gate(ex3_div_rt_q(32 to 63),not(ex3_div_ovf_q)); + +alu_byp_ex3_div_rt <= ex3_div_rt; + + +-- Divide Undefined/Overflow Conditions +-- ------------------------------------------------------------------------------ +-- | Cond 1 | Cond 2 | Cond 3 | Cond 4 | +-- -----------------------------------------------------------------------------+ +-- | 0x8000... / -1 | / 0 | RA >= RB | Result doesn't | +-- | | | | fit in 32/64 bits | +-- -----------------------------------------------------------------------------+ +-- divw | X | X | | | +-- divwu | | X | | | +-- divwe | X | X | | X | +-- divweu | | X | X | | +-- divd | X | X | | | +-- divdu | | X | | | +-- divde | X | X | | X | +-- divdeu | | X | X | | +-- -----------------------------------------------------------------------------+ + + ex1_num_cmp0_lo_nomsb <= not or_reduce(byp_alu_ex1_divsrc_0(33 to 63)); + ex1_den_cmp0_lo <= not or_reduce(byp_alu_ex1_divsrc_1(32 to 63)); + ex1_den_cmp1_lo <= and_reduce(byp_alu_ex1_divsrc_1(32 to 63)); + ex3_qot_cmp0_lo <= not or_reduce(ex3_div_rt_q(32 to 63)); + ex1_num_cmp0_lo <= not byp_alu_ex1_divsrc_0(32) and ex1_num_cmp0_lo_nomsb; + ex1_div_ovf_cond1_wd <= byp_alu_ex1_divsrc_0(32) and ex1_num_cmp0_lo_nomsb and ex1_den_cmp1_lo; + +div_64b_oflow : if regsize = 64 generate + + ex1_num_cmp0_hi_nomsb <= not or_reduce(byp_alu_ex1_divsrc_0(1 to 31)); + ex1_den_cmp0_hi <= not or_reduce(byp_alu_ex1_divsrc_1(0 to 31)); + ex1_den_cmp1_hi <= and_reduce(byp_alu_ex1_divsrc_1(0 to 31)); + ex3_qot_cmp0_hi <= not or_reduce(ex3_div_rt_q(0 to 31)); + ex1_num_cmp0_hi <= not byp_alu_ex1_divsrc_0(0) and ex1_num_cmp0_hi_nomsb; + ex1_div_ovf_cond1_dw <= byp_alu_ex1_divsrc_0(0) and ex1_num_cmp0_hi_nomsb and + not byp_alu_ex1_divsrc_0(32) and ex1_num_cmp0_lo_nomsb and ex1_den_cmp1_lo and ex1_den_cmp1_hi; + +end generate; +div_32b_oflow : if regsize = 32 generate + + ex1_num_cmp0_hi_nomsb <= '1'; + ex1_den_cmp0_hi <= '1'; + ex1_den_cmp1_hi <= '1'; + ex1_div_ovf_cond1_dw <= '1'; + ex1_num_cmp0_hi <= '1'; + ex3_qot_cmp0_hi <= '1'; + +end generate; + + +with ex1_div_size_q select + ex1_div_ovf_cond1 <= ex1_div_ovf_cond1_dw when '1', + ex1_div_ovf_cond1_wd when others; + +ex1_div_ovf_cond2 <= ex1_den_cmp0_lo and (ex1_den_cmp0_hi or not ex1_div_size_q); + +ex1_div_ovf <= (ex1_div_ovf_cond1 and ex1_div_sign_q) or + ex1_div_ovf_cond2; + +-- Condition 3 +ex2_den_eq_num <= and_reduce(ex2_denom_q xnor ex2_numer_q(msb+1 to 64)); +ex2_den_gte_num <= not(ex2_sub_rslt(msb)) or ex2_den_eq_num; +ex2_div_ovf_cond3 <= ex2_den_gte_num and not ex2_div_sign_q and ex2_div_extd_q; + +-- Condition 4 +-- Need to watch quotient for first 65 cycles of divde, 33 cycles of divwe +ex2_cycles_gt_64 <= '1' when (unsigned(ex2_cycles_q) > 64) else '0'; +ex2_cycles_gt_32 <= '1' when (unsigned(ex2_cycles_q) > 32) else '0'; + +with ex2_div_size_q select + ex3_cycle_watch_d <= ex2_cycles_gt_64 when '1', + ex2_cycles_gt_32 when others; + +-- If any bit is pushed during the watch period, flag overflow +ex3_quot_watch_d <= (ex3_quot_watch_q or (ex3_cycle_watch_q and ex3_quotient_q(63))) and not ex3_div_val_q; + +ex2_numer_eq_zero_d <= ex1_num_cmp0_lo and (ex1_num_cmp0_hi or not ex1_div_size_q); + +ex2_div_ovf_cond4 <= ex3_quot_watch_q or -- overflow out of 32/64 bits + ((ex2_rslt_sign xor ex2_2s_rslt_q) and not ex2_numer_eq_zero_q) or -- result sign differs from expected, numerator not equal to zero + ( ex2_rslt_sign and ex2_numer_eq_zero_q); -- result sign is negative , numerator equal to zero + +ex3_div_ovf_d <= ex2_div_ovf_q or ex3_div_ovf_cond3_q or (ex2_div_ovf_cond4 and (ex2_div_sign_q and ex2_div_extd_q)); + +ex3_div_xer_ov_update <= ex3_xer_ov_update_q and ex3_div_done_q; +ex3_div_xer_ov <= ex3_div_ovf_q; + +--------------------------------------------------------------------- +-- Record forms +--------------------------------------------------------------------- +ex3_cmp0_undef <= ex3_div_ovf_q or -- Overflow Cases + (not ex3_div_size_q and ex3_spr_msr_cm_q); -- Word op in 64b mode + +with ex3_spr_msr_cm_q select + ex3_lt <= ex3_div_rt_q(msb) when '1', + ex3_div_rt_q(32) when others; + +ex3_cmp0_eq <= (ex3_qot_cmp0_lo and + (ex3_qot_cmp0_hi or not ex3_spr_msr_cm_q)) and not ex3_cmp0_undef; + +ex3_cmp0_lt <= ex3_lt and not ex3_cmp0_eq and not ex3_cmp0_undef; +ex3_cmp0_gt <= not ex3_lt and not ex3_cmp0_eq and not ex3_cmp0_undef; + +alu_byp_ex3_cr_div <= ex3_cmp0_lt & ex3_cmp0_gt & ex3_cmp0_eq & (ex3_div_ovf_q and ex3_xer_ov_update_q) & (ex3_div_recform_q and ex3_div_done_q); + +--------------------------------------------------------------------- +-- Latches +--------------------------------------------------------------------- + ex1_div_ctr_latch : tri_rlmreg_p + generic map (width => ex1_div_ctr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => dec_alu_rf1_div_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_div_ctr_offset to ex1_div_ctr_offset + ex1_div_ctr_q'length-1), + scout => sov(ex1_div_ctr_offset to ex1_div_ctr_offset + ex1_div_ctr_q'length-1), + din => fxa_fxb_rf1_div_ctr, + dout => ex1_div_ctr_q); + ex1_div_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_div_val_offset), + scout => sov(ex1_div_val_offset), + din => dec_alu_rf1_div_val, + dout => ex1_div_val_q); + ex1_div_sign_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => dec_alu_rf1_div_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_div_sign_offset), + scout => sov(ex1_div_sign_offset), + din => dec_alu_rf1_div_sign, + dout => ex1_div_sign_q); + ex1_div_size_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => dec_alu_rf1_div_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_div_size_offset), + scout => sov(ex1_div_size_offset), + din => dec_alu_rf1_div_size, + dout => ex1_div_size_q); + ex1_div_extd_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => dec_alu_rf1_div_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_div_extd_offset), + scout => sov(ex1_div_extd_offset), + din => dec_alu_rf1_div_extd, + dout => ex1_div_extd_q); + ex1_div_recform_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => dec_alu_rf1_div_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_div_recform_offset), + scout => sov(ex1_div_recform_offset), + din => dec_alu_rf1_div_recform, + dout => ex1_div_recform_q); + ex1_xer_ov_update_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => dec_alu_rf1_div_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_xer_ov_update_offset), + scout => sov(ex1_xer_ov_update_offset), + din => dec_alu_rf1_xer_ov_update, + dout => ex1_xer_ov_update_q); + ex2_div_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_div_val_offset), + scout => sov(ex2_div_val_offset), + din => ex1_div_val_q, + dout => ex2_div_val_q); + ex2_cycle_act_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_cycle_act_offset), + scout => sov(ex2_cycle_act_offset), + din => ex1_cycle_act, + dout => ex2_cycle_act_q); + ex2_cycles_latch : tri_rlmreg_p + generic map (width => ex2_cycles_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => ex1_cycle_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_cycles_offset to ex2_cycles_offset + ex2_cycles_q'length-1), + scout => sov(ex2_cycles_offset to ex2_cycles_offset + ex2_cycles_q'length-1), + din => ex2_cycles_d, + dout => ex2_cycles_q); + ex2_denom_latch : tri_rlmreg_p + generic map (width => ex2_denom_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => ex2_denom_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_denom_offset to ex2_denom_offset + ex2_denom_q'length-1), + scout => sov(ex2_denom_offset to ex2_denom_offset + ex2_denom_q'length-1), + din => ex2_denom_d, + dout => ex2_denom_q); + ex2_numer_latch : tri_rlmreg_p + generic map (width => ex2_numer_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => ex2_numer_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_numer_offset to ex2_numer_offset + ex2_numer_q'length-1), + scout => sov(ex2_numer_offset to ex2_numer_offset + ex2_numer_q'length-1), + din => ex2_numer_d, + dout => ex2_numer_q); + ex2_dmask_latch : tri_rlmreg_p + generic map (width => ex2_dmask_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => ex2_denom_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_dmask_offset to ex2_dmask_offset + ex2_dmask_q'length-1), + scout => sov(ex2_dmask_offset to ex2_dmask_offset + ex2_dmask_q'length-1), + din => ex2_dmask_d, + dout => ex2_dmask_q); + ex2_div_ovf_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => ex1_div_val_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_div_ovf_offset), + scout => sov(ex2_div_ovf_offset), + din => ex1_div_ovf, + dout => ex2_div_ovf_q); + ex2_xer_ov_update_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_xer_ov_update_offset), + scout => sov(ex2_xer_ov_update_offset), + din => ex1_xer_ov_update_q, + dout => ex2_xer_ov_update_q); + ex2_div_recform_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_div_recform_offset), + scout => sov(ex2_div_recform_offset), + din => ex1_div_recform_q, + dout => ex2_div_recform_q); + ex2_div_size_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => ex1_div_val_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_div_size_offset), + scout => sov(ex2_div_size_offset), + din => ex1_div_size_q, + dout => ex2_div_size_q); + ex2_div_sign_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => ex1_div_val_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_div_sign_offset), + scout => sov(ex2_div_sign_offset), + din => ex1_div_sign_q, + dout => ex2_div_sign_q); + ex2_div_extd_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => ex1_div_val_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_div_extd_offset), + scout => sov(ex2_div_extd_offset), + din => ex1_div_extd_q, + dout => ex2_div_extd_q); + ex2_2s_rslt_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => ex1_div_val_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_2s_rslt_offset), + scout => sov(ex2_2s_rslt_offset), + din => ex1_2s_rslt, + dout => ex2_2s_rslt_q); + ex2_div_done_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_div_done_offset), + scout => sov(ex2_div_done_offset), + din => ex1_div_done, + dout => ex2_div_done_q); + ex3_div_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_div_val_offset), + scout => sov(ex3_div_val_offset), + din => ex2_div_val_q, + dout => ex3_div_val_q); + ex3_cycle_watch_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_cycle_watch_offset), + scout => sov(ex3_cycle_watch_offset), + din => ex3_cycle_watch_d, + dout => ex3_cycle_watch_q); + ex3_quot_watch_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_quot_watch_offset), + scout => sov(ex3_quot_watch_offset), + din => ex3_quot_watch_d, + dout => ex3_quot_watch_q); + ex3_div_ovf_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_div_ovf_offset), + scout => sov(ex3_div_ovf_offset), + din => ex3_div_ovf_d, + dout => ex3_div_ovf_q); + ex3_xer_ov_update_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_xer_ov_update_offset), + scout => sov(ex3_xer_ov_update_offset), + din => ex2_xer_ov_update_q, + dout => ex3_xer_ov_update_q); + ex3_div_done_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_div_done_offset), + scout => sov(ex3_div_done_offset), + din => ex2_div_done_q, + dout => ex3_div_done_q); + ex3_quotient_latch : tri_rlmreg_p + generic map (width => ex3_quotient_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => ex2_cycle_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_quotient_offset to ex3_quotient_offset + ex3_quotient_q'length-1), + scout => sov(ex3_quotient_offset to ex3_quotient_offset + ex3_quotient_q'length-1), + din => ex3_quotient_d, + dout => ex3_quotient_q); + ex3_div_recform_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_div_recform_offset), + scout => sov(ex3_div_recform_offset), + din => ex2_div_recform_q, + dout => ex3_div_recform_q); + ex3_div_size_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_div_size_offset), + scout => sov(ex3_div_size_offset), + din => ex2_div_size_q, + dout => ex3_div_size_q); + ex3_2s_rslt_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_2s_rslt_offset), + scout => sov(ex3_2s_rslt_offset), + din => ex2_2s_rslt_q, + dout => ex3_2s_rslt_q); + ex3_div_rt_latch : tri_rlmreg_p + generic map (width => ex3_div_rt_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => ex2_div_done_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_div_rt_offset to ex3_div_rt_offset + ex3_div_rt_q'length-1), + scout => sov(ex3_div_rt_offset to ex3_div_rt_offset + ex3_div_rt_q'length-1), + din => ex3_div_rt_d, + dout => ex3_div_rt_q); + ex3_div_ovf_cond3_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_div_val_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_div_ovf_cond3_offset), + scout => sov(ex3_div_ovf_cond3_offset), + din => ex2_div_ovf_cond3, + dout => ex3_div_ovf_cond3_q); + ex3_spr_msr_cm_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_spr_msr_cm_offset), + scout => sov(ex3_spr_msr_cm_offset), + din => ex2_spr_msr_cm, + dout => ex3_spr_msr_cm_q); + ex2_numer_eq_zero_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => ex1_div_val_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_numer_eq_zero_offset), + scout => sov(ex2_numer_eq_zero_offset), + din => ex2_numer_eq_zero_d, + dout => ex2_numer_eq_zero_q); + need_hole_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(need_hole_offset), + scout => sov(need_hole_offset), + din => need_hole_d, + dout => need_hole_q); + siv(0 to siv'right) <= sov(1 to siv'right) & scan_in; + scan_out <= sov(0); +end architecture xuq_alu_div; diff --git a/rel/src/vhdl/work/xuq_alu_ins.vhdl b/rel/src/vhdl/work/xuq_alu_ins.vhdl new file mode 100644 index 0000000..1689a17 --- /dev/null +++ b/rel/src/vhdl/work/xuq_alu_ins.vhdl @@ -0,0 +1,242 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +LIBRARY ieee; USE ieee.std_logic_1164.all; + use ieee.numeric_std.all; +LIBRARY ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; +LIBRARY support; + use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity xuq_alu_ins is generic(expand_type: integer := 2 ); port ( + + ins_log_fcn :in std_ulogic_vector(0 to 3) ; -- use pass ra for rlwimi + -- rs, ra/rb + -- 0000 => "0" + -- 0001 => rs AND rb + -- 0010 => rs AND !rb + -- 0011 => rs + -- 0100 => !rs and RB + -- 0101 => RB + -- 0110 => rs xor RB + -- 0111 => rs or RB + -- 1000 => rs nor RB + -- 1001 => rs xnor RB (use for cmp-byt) + -- 1010 => !RB + -- 1011 => rs or !rb + -- 1100 => !rs + -- 1101 => rs nand !rb, !rs or rb + -- 1110 => rs nand rb ... + -- 1111 => "1" + + ins_cmp_byt :in std_ulogic ; + ins_sra_wd :in std_ulogic ; + ins_sra_dw :in std_ulogic ; + + ins_xtd_byte :in std_ulogic ;-- use with xtd + ins_xtd_half :in std_ulogic ;-- use with xtd + ins_xtd_wd :in std_ulogic ;-- use with xtd, sra + + + data0_i :in std_ulogic_vector(0 to 63) ;--data input (rs) + data1_i :in std_ulogic_vector(0 to 63) ;--data input (ra|rb) + mrg_byp_log :out std_ulogic_vector(0 to 63) ; + res_ins :out std_ulogic_vector(0 to 63) --insert data (also result of logicals) +); + +-- synopsys translate_off +-- synopsys translate_on +end xuq_alu_ins; + +architecture xuq_alu_ins of xuq_alu_ins is + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal mrg_byp_log_b :std_ulogic_vector(0 to 63); + + signal res_log :std_ulogic_vector(0 to 63); + signal byt_cmp, byt_cmp_b :std_ulogic_vector(0 to 7); + signal byt_cmp_bus, sign_xtd_bus :std_ulogic_vector(0 to 63); + signal xtd_byte_bus, xtd_half_bus, xtd_wd_bus, sra_dw_bus, sra_wd_bus :std_ulogic_vector(0 to 63); + signal res_ins0_b, res_ins1_b, res_ins2_b :std_ulogic_vector(0 to 63); + signal res_log0_b, res_log1_b, res_log2_b, res_log3_b :std_ulogic_vector(0 to 63); + signal res_log_o0, res_log_o1, res_log_b :std_ulogic_vector(0 to 63); + signal byt0_cmp2_b :std_ulogic_vector(0 to 3) ; + signal byt1_cmp2_b :std_ulogic_vector(0 to 3) ; + signal byt2_cmp2_b :std_ulogic_vector(0 to 3) ; + signal byt3_cmp2_b :std_ulogic_vector(0 to 3) ; + signal byt4_cmp2_b :std_ulogic_vector(0 to 3) ; + signal byt5_cmp2_b :std_ulogic_vector(0 to 3) ; + signal byt6_cmp2_b :std_ulogic_vector(0 to 3) ; + signal byt7_cmp2_b :std_ulogic_vector(0 to 3) ; + + signal byt0_cmp4 :std_ulogic_vector(0 to 1) ; + signal byt1_cmp4 :std_ulogic_vector(0 to 1) ; + signal byt2_cmp4 :std_ulogic_vector(0 to 1) ; + signal byt3_cmp4 :std_ulogic_vector(0 to 1) ; + signal byt4_cmp4 :std_ulogic_vector(0 to 1) ; + signal byt5_cmp4 :std_ulogic_vector(0 to 1) ; + signal byt6_cmp4 :std_ulogic_vector(0 to 1) ; + signal byt7_cmp4 :std_ulogic_vector(0 to 1) ; + + signal sel_cmp_byt,sel_cmp_byt_b : std_ulogic_vector(0 to 63); + + signal data0_b, data1_b : std_ulogic_vector(0 to 63); + signal data0, data1 : std_ulogic_vector(0 to 63); + + +begin + + u_log_s0i: data0_b <= not data0_i; + u_log_s1i: data1_b <= not data1_i; + u_log_s0: data0 <= not data0_b; + u_log_s1: data1 <= not data1_b; + + u_reslog0: res_log0_b(0 to 63) <= not( (0 to 63=> ins_log_fcn(0)) and data0_b(0 to 63) and data1_b(0 to 63) ); + u_reslog1: res_log1_b(0 to 63) <= not( (0 to 63=> ins_log_fcn(1)) and data0_b(0 to 63) and data1(0 to 63) ); + u_reslog2: res_log2_b(0 to 63) <= not( (0 to 63=> ins_log_fcn(2)) and data0(0 to 63) and data1_b(0 to 63) ); + u_reslog3: res_log3_b(0 to 63) <= not( (0 to 63=> ins_log_fcn(3)) and data0(0 to 63) and data1(0 to 63) ); + u_reslog_o0: res_log_o0(0 to 63) <= not( res_log0_b(0 to 63) and res_log1_b(0 to 63) ); + u_reslog_o1: res_log_o1(0 to 63) <= not( res_log2_b(0 to 63) and res_log3_b(0 to 63) ); + u_reslogb: res_log_b (0 to 63) <= not( res_log_o0(0 to 63) or res_log_o1(0 to 63) ); + u_reslog: res_log (0 to 63) <= not( res_log_b(0 to 63) ); + + u_mrg_byp_log_b: mrg_byp_log_b(0 to 63) <= not( res_log (0 to 63) ); + u_mrg_byp_log: mrg_byp_log (0 to 63) <= not( mrg_byp_log_b(0 to 63) ); + + u_byt0cmp2_0: byt0_cmp2_b(0) <= not( res_log(0) and res_log(1) ); + u_byt0cmp2_1: byt0_cmp2_b(1) <= not( res_log(2) and res_log(3) ); + u_byt0cmp2_2: byt0_cmp2_b(2) <= not( res_log(4) and res_log(5) ); + u_byt0cmp2_3: byt0_cmp2_b(3) <= not( res_log(6) and res_log(7) ); + u_byt1cmp2_0: byt1_cmp2_b(0) <= not( res_log(8) and res_log(9) ); + u_byt1cmp2_1: byt1_cmp2_b(1) <= not( res_log(10) and res_log(11) ); + u_byt1cmp2_2: byt1_cmp2_b(2) <= not( res_log(12) and res_log(13) ); + u_byt1cmp2_3: byt1_cmp2_b(3) <= not( res_log(14) and res_log(15) ); + u_byt2cmp2_0: byt2_cmp2_b(0) <= not( res_log(16) and res_log(17) ); + u_byt2cmp2_1: byt2_cmp2_b(1) <= not( res_log(18) and res_log(19) ); + u_byt2cmp2_2: byt2_cmp2_b(2) <= not( res_log(20) and res_log(21) ); + u_byt2cmp2_3: byt2_cmp2_b(3) <= not( res_log(22) and res_log(23) ); + u_byt3cmp2_0: byt3_cmp2_b(0) <= not( res_log(24) and res_log(25) ); + u_byt3cmp2_1: byt3_cmp2_b(1) <= not( res_log(26) and res_log(27) ); + u_byt3cmp2_2: byt3_cmp2_b(2) <= not( res_log(28) and res_log(29) ); + u_byt3cmp2_3: byt3_cmp2_b(3) <= not( res_log(30) and res_log(31) ); + u_byt4cmp2_0: byt4_cmp2_b(0) <= not( res_log(32) and res_log(33) ); + u_byt4cmp2_1: byt4_cmp2_b(1) <= not( res_log(34) and res_log(35) ); + u_byt4cmp2_2: byt4_cmp2_b(2) <= not( res_log(36) and res_log(37) ); + u_byt4cmp2_3: byt4_cmp2_b(3) <= not( res_log(38) and res_log(39) ); + u_byt5cmp2_0: byt5_cmp2_b(0) <= not( res_log(40) and res_log(41) ); + u_byt5cmp2_1: byt5_cmp2_b(1) <= not( res_log(42) and res_log(43) ); + u_byt5cmp2_2: byt5_cmp2_b(2) <= not( res_log(44) and res_log(45) ); + u_byt5cmp2_3: byt5_cmp2_b(3) <= not( res_log(46) and res_log(47) ); + u_byt6cmp2_0: byt6_cmp2_b(0) <= not( res_log(48) and res_log(49) ); + u_byt6cmp2_1: byt6_cmp2_b(1) <= not( res_log(50) and res_log(51) ); + u_byt6cmp2_2: byt6_cmp2_b(2) <= not( res_log(52) and res_log(53) ); + u_byt6cmp2_3: byt6_cmp2_b(3) <= not( res_log(54) and res_log(55) ); + u_byt7cmp2_0: byt7_cmp2_b(0) <= not( res_log(56) and res_log(57) ); + u_byt7cmp2_1: byt7_cmp2_b(1) <= not( res_log(58) and res_log(59) ); + u_byt7cmp2_2: byt7_cmp2_b(2) <= not( res_log(60) and res_log(61) ); + u_byt7cmp2_3: byt7_cmp2_b(3) <= not( res_log(62) and res_log(63) ); + + + u_byt0cmp4_0: byt0_cmp4(0) <= not( byt0_cmp2_b(0) or byt0_cmp2_b(1) ); + u_byt0cmp4_1: byt0_cmp4(1) <= not( byt0_cmp2_b(2) or byt0_cmp2_b(3) ); + u_byt1cmp4_0: byt1_cmp4(0) <= not( byt1_cmp2_b(0) or byt1_cmp2_b(1) ); + u_byt1cmp4_1: byt1_cmp4(1) <= not( byt1_cmp2_b(2) or byt1_cmp2_b(3) ); + u_byt2cmp4_0: byt2_cmp4(0) <= not( byt2_cmp2_b(0) or byt2_cmp2_b(1) ); + u_byt2cmp4_1: byt2_cmp4(1) <= not( byt2_cmp2_b(2) or byt2_cmp2_b(3) ); + u_byt3cmp4_0: byt3_cmp4(0) <= not( byt3_cmp2_b(0) or byt3_cmp2_b(1) ); + u_byt3cmp4_1: byt3_cmp4(1) <= not( byt3_cmp2_b(2) or byt3_cmp2_b(3) ); + u_byt4cmp4_0: byt4_cmp4(0) <= not( byt4_cmp2_b(0) or byt4_cmp2_b(1) ); + u_byt4cmp4_1: byt4_cmp4(1) <= not( byt4_cmp2_b(2) or byt4_cmp2_b(3) ); + u_byt5cmp4_0: byt5_cmp4(0) <= not( byt5_cmp2_b(0) or byt5_cmp2_b(1) ); + u_byt5cmp4_1: byt5_cmp4(1) <= not( byt5_cmp2_b(2) or byt5_cmp2_b(3) ); + u_byt6cmp4_0: byt6_cmp4(0) <= not( byt6_cmp2_b(0) or byt6_cmp2_b(1) ); + u_byt6cmp4_1: byt6_cmp4(1) <= not( byt6_cmp2_b(2) or byt6_cmp2_b(3) ); + u_byt7cmp4_0: byt7_cmp4(0) <= not( byt7_cmp2_b(0) or byt7_cmp2_b(1) ); + u_byt7cmp4_1: byt7_cmp4(1) <= not( byt7_cmp2_b(2) or byt7_cmp2_b(3) ); + + u_byt0cmp8b: byt_cmp_b(0) <= not( byt0_cmp4(0) and byt0_cmp4(1) ); + u_byt1cmp8b: byt_cmp_b(1) <= not( byt1_cmp4(0) and byt1_cmp4(1) ); + u_byt2cmp8b: byt_cmp_b(2) <= not( byt2_cmp4(0) and byt2_cmp4(1) ); + u_byt3cmp8b: byt_cmp_b(3) <= not( byt3_cmp4(0) and byt3_cmp4(1) ); + u_byt4cmp8b: byt_cmp_b(4) <= not( byt4_cmp4(0) and byt4_cmp4(1) ); + u_byt5cmp8b: byt_cmp_b(5) <= not( byt5_cmp4(0) and byt5_cmp4(1) ); + u_byt6cmp8b: byt_cmp_b(6) <= not( byt6_cmp4(0) and byt6_cmp4(1) ); + u_byt7cmp8b: byt_cmp_b(7) <= not( byt7_cmp4(0) and byt7_cmp4(1) ); + + + u_byt0cmp8: byt_cmp(0) <= not( byt_cmp_b(0) ); + u_byt1cmp8: byt_cmp(1) <= not( byt_cmp_b(1) ); + u_byt2cmp8: byt_cmp(2) <= not( byt_cmp_b(2) ); + u_byt3cmp8: byt_cmp(3) <= not( byt_cmp_b(3) ); + u_byt4cmp8: byt_cmp(4) <= not( byt_cmp_b(4) ); + u_byt5cmp8: byt_cmp(5) <= not( byt_cmp_b(5) ); + u_byt6cmp8: byt_cmp(6) <= not( byt_cmp_b(6) ); + u_byt7cmp8: byt_cmp(7) <= not( byt_cmp_b(7) ); + + + byt_cmp_bus( 0 to 7) <= ( 0 to 7=> byt_cmp(0) ); + byt_cmp_bus( 8 to 15) <= ( 8 to 15=> byt_cmp(1) ); + byt_cmp_bus(16 to 23) <= (16 to 23=> byt_cmp(2) ); + byt_cmp_bus(24 to 31) <= (24 to 31=> byt_cmp(3) ); + byt_cmp_bus(32 to 39) <= (32 to 39=> byt_cmp(4) ); + byt_cmp_bus(40 to 47) <= (40 to 47=> byt_cmp(5) ); + byt_cmp_bus(48 to 55) <= (48 to 55=> byt_cmp(6) ); + byt_cmp_bus(56 to 63) <= (56 to 63=> byt_cmp(7) ); + + + + xtd_byte_bus(0 to 63) <= (0 to 56 => data0(56) ) & data0(57 to 63) ; + xtd_half_bus(0 to 63) <= (0 to 48 => data0(48) ) & data0(49 to 63) ; + xtd_wd_bus (0 to 63) <= (0 to 32 => data0(32) ) & data0(33 to 63) ; + sra_wd_bus (0 to 63) <= (0 to 63 => data0(32) ); -- all the bits for sra + sra_dw_bus (0 to 63) <= (0 to 63 => data0(0) ); -- all the bits for sra + + + sign_xtd_bus(0 to 63) <= + ( (0 to 63=> ins_xtd_byte) and xtd_byte_bus(0 to 63) ) or + ( (0 to 63=> ins_xtd_half) and xtd_half_bus(0 to 63) ) or + ( (0 to 63=> ins_xtd_wd ) and xtd_wd_bus (0 to 63) ) or + ( (0 to 63=> ins_sra_wd ) and sra_wd_bus (0 to 63) ) or + ( (0 to 63=> ins_sra_dw ) and sra_dw_bus (0 to 63) ) ; + + sel_cmp_byt <= (0 to 63=> ins_cmp_byt); + sel_cmp_byt_b <= (0 to 63=> not(ins_cmp_byt)); + + u_res_ins0: res_ins0_b(0 to 63) <= not( sel_cmp_byt and byt_cmp_bus(0 to 63) ); + u_res_ins1: res_ins1_b(0 to 63) <= not( sel_cmp_byt_b and res_log(0 to 63) ); + u_res_ins2: res_ins2_b(0 to 63) <= not( sign_xtd_bus(0 to 63) ); + + u_res_ins : res_ins (0 to 63) <= not( res_ins0_b(0 to 63) and res_ins1_b(0 to 63) and res_ins2_b(0 to 63) );--output-- + + +end architecture xuq_alu_ins; diff --git a/rel/src/vhdl/work/xuq_alu_mask.vhdl b/rel/src/vhdl/work/xuq_alu_mask.vhdl new file mode 100644 index 0000000..68ed089 --- /dev/null +++ b/rel/src/vhdl/work/xuq_alu_mask.vhdl @@ -0,0 +1,381 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +LIBRARY ieee; USE ieee.std_logic_1164.all; + use ieee.numeric_std.all; +LIBRARY ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; +LIBRARY support; + use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity xuq_alu_mask is generic(expand_type: integer := 2 ); port ( + mb :in std_ulogic_vector(0 to 5); -- where the mask begins + me_b :in std_ulogic_vector(0 to 5); -- where the mask ends + zm :in std_ulogic; -- set mask to all zeroes. ... not a rot/sh op ... all bits are shifted out + mb_gt_me :in std_ulogic; + mask :out std_ulogic_vector(0 to 63) -- mask shows which rotator bits to keep in the result. +); + +-- synopsys translate_off +-- synopsys translate_on +end xuq_alu_mask; + +architecture xuq_alu_mask of xuq_alu_mask is + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal mask_en_and, mask_en_mb, mask_en_me :std_ulogic ; + signal mask0_b, mask1_b, mask2_b :std_ulogic_vector(0 to 63); + signal mb_mask, me_mask :std_ulogic_vector(0 to 63) ; + + signal mb_msk45, mb_msk45_b :std_ulogic_vector(0 to 2); + signal mb_msk23, mb_msk23_b :std_ulogic_vector(0 to 2); + signal mb_msk01, mb_msk01_b :std_ulogic_vector(0 to 2); + signal mb_msk25, mb_msk25_b :std_ulogic_vector(0 to 14); + signal mb_msk01bb, mb_msk01bbb :std_ulogic_vector(0 to 2); + signal me_msk01, me_msk01_b :std_ulogic_vector( 1 to 3); + signal me_msk23, me_msk23_b :std_ulogic_vector( 1 to 3); + signal me_msk45, me_msk45_b :std_ulogic_vector( 1 to 3); + signal me_msk25, me_msk25_b :std_ulogic_vector(1 to 15); + signal me_msk01bbb, me_msk01bb :std_ulogic_vector(1 to 3); + + +begin + + -- ----------------------------------------------------------------------------------------- + -- generate the MB mask + -- ----------------------------------------------------------------------------------------- + -- 0123 + -- ------ + -- 00 => 1111 (ge) + -- 01 => 0111 + -- 10 => 0011 + -- 11 => 0001 + + -- level 1 (4 bit results) ------------ <3 loads on input> + + u_mb_msk45_0: mb_msk45(0) <= not( mb(4) or mb(5) ); + u_mb_msk45_1: mb_msk45(1) <= not( mb(4) ); + u_mb_msk45_2: mb_msk45(2) <= not( mb(4) and mb(5) ); + u_mb_msk23_0: mb_msk23(0) <= not( mb(2) or mb(3) ); + u_mb_msk23_1: mb_msk23(1) <= not( mb(2) ); + u_mb_msk23_2: mb_msk23(2) <= not( mb(2) and mb(3) ); + u_mb_msk01_0: mb_msk01(0) <= not( mb(0) or mb(1) ); + u_mb_msk01_1: mb_msk01(1) <= not( mb(0) ); + u_mb_msk01_2: mb_msk01(2) <= not( mb(0) and mb(1) ); + + u_mb_msk45b0: mb_msk45_b(0) <= not( mb_msk45(0) ); + u_mb_msk45b1: mb_msk45_b(1) <= not( mb_msk45(1) ); + u_mb_msk45b2: mb_msk45_b(2) <= not( mb_msk45(2) ); + u_mb_msk23b0: mb_msk23_b(0) <= not( mb_msk23(0) ); -- 7 loads on output + u_mb_msk23b1: mb_msk23_b(1) <= not( mb_msk23(1) ); + u_mb_msk23b2: mb_msk23_b(2) <= not( mb_msk23(2) ); + u_mb_msk01b0: mb_msk01_b(0) <= not( mb_msk01(0) ); + u_mb_msk01b1: mb_msk01_b(1) <= not( mb_msk01(1) ); + u_mb_msk01b2: mb_msk01_b(2) <= not( mb_msk01(2) ); + + + -- level 2 (16 bit results) ------------- + + u_mb_msk25_0: mb_msk25(0) <= not( mb_msk23_b(0) or mb_msk45_b(0) ); + u_mb_msk25_1: mb_msk25(1) <= not( mb_msk23_b(0) or mb_msk45_b(1) ); + u_mb_msk25_2: mb_msk25(2) <= not( mb_msk23_b(0) or mb_msk45_b(2) ); + u_mb_msk25_3: mb_msk25(3) <= not( mb_msk23_b(0) ); + u_mb_msk25_4: mb_msk25(4) <= not( mb_msk23_b(0) and ( mb_msk23_b(1) or mb_msk45_b(0) ) ); + u_mb_msk25_5: mb_msk25(5) <= not( mb_msk23_b(0) and ( mb_msk23_b(1) or mb_msk45_b(1) ) ); + u_mb_msk25_6: mb_msk25(6) <= not( mb_msk23_b(0) and ( mb_msk23_b(1) or mb_msk45_b(2) ) ); + u_mb_msk25_7: mb_msk25(7) <= not( mb_msk23_b(1) ); + u_mb_msk25_8: mb_msk25(8) <= not( mb_msk23_b(1) and ( mb_msk23_b(2) or mb_msk45_b(0) ) ); + u_mb_msk25_9: mb_msk25(9) <= not( mb_msk23_b(1) and ( mb_msk23_b(2) or mb_msk45_b(1) ) ); + u_mb_msk25_10: mb_msk25(10) <= not( mb_msk23_b(1) and ( mb_msk23_b(2) or mb_msk45_b(2) ) ); + u_mb_msk25_11: mb_msk25(11) <= not( mb_msk23_b(2) ); + u_mb_msk25_12: mb_msk25(12) <= not( mb_msk23_b(2) and mb_msk45_b(0) ); + u_mb_msk25_13: mb_msk25(13) <= not( mb_msk23_b(2) and mb_msk45_b(1) ); + u_mb_msk25_14: mb_msk25(14) <= not( mb_msk23_b(2) and mb_msk45_b(2) ); + + u_mb_msk01bb0: mb_msk01bb(0) <= not( mb_msk01_b(0) ); + u_mb_msk01bb1: mb_msk01bb(1) <= not( mb_msk01_b(1) ); + u_mb_msk01bb2: mb_msk01bb(2) <= not( mb_msk01_b(2) ); + + + u_mb_msk25b0: mb_msk25_b(0) <= not( mb_msk25(0) ); + u_mb_msk25b1: mb_msk25_b(1) <= not( mb_msk25(1) ); + u_mb_msk25b2: mb_msk25_b(2) <= not( mb_msk25(2) ); + u_mb_msk25b3: mb_msk25_b(3) <= not( mb_msk25(3) ); + u_mb_msk25b4: mb_msk25_b(4) <= not( mb_msk25(4) ); + u_mb_msk25b5: mb_msk25_b(5) <= not( mb_msk25(5) ); + u_mb_msk25b6: mb_msk25_b(6) <= not( mb_msk25(6) ); + u_mb_msk25b7: mb_msk25_b(7) <= not( mb_msk25(7) ); + u_mb_msk25b8: mb_msk25_b(8) <= not( mb_msk25(8) ); + u_mb_msk25b9: mb_msk25_b(9) <= not( mb_msk25(9) ); + u_mb_msk25b10: mb_msk25_b(10) <= not( mb_msk25(10) ); + u_mb_msk25b11: mb_msk25_b(11) <= not( mb_msk25(11) ); + u_mb_msk25b12: mb_msk25_b(12) <= not( mb_msk25(12) ); + u_mb_msk25b13: mb_msk25_b(13) <= not( mb_msk25(13) ); + u_mb_msk25b14: mb_msk25_b(14) <= not( mb_msk25(14) ); + + u_mb_msk01bbb0: mb_msk01bbb(0) <= not( mb_msk01bb(0) ); + u_mb_msk01bbb1: mb_msk01bbb(1) <= not( mb_msk01bb(1) ); + u_mb_msk01bbb2: mb_msk01bbb(2) <= not( mb_msk01bb(2) ); + + -- level 3 ------------------------------------------------------- + u_mb_mask_0: mb_mask(0) <= not( mb_msk01bbb(0) or mb_msk25_b(0) ); + u_mb_mask_1: mb_mask(1) <= not( mb_msk01bbb(0) or mb_msk25_b(1) ); + u_mb_mask_2: mb_mask(2) <= not( mb_msk01bbb(0) or mb_msk25_b(2) ); + u_mb_mask_3: mb_mask(3) <= not( mb_msk01bbb(0) or mb_msk25_b(3) ); + u_mb_mask_4: mb_mask(4) <= not( mb_msk01bbb(0) or mb_msk25_b(4) ); + u_mb_mask_5: mb_mask(5) <= not( mb_msk01bbb(0) or mb_msk25_b(5) ); + u_mb_mask_6: mb_mask(6) <= not( mb_msk01bbb(0) or mb_msk25_b(6) ); + u_mb_mask_7: mb_mask(7) <= not( mb_msk01bbb(0) or mb_msk25_b(7) ); + u_mb_mask_8: mb_mask(8) <= not( mb_msk01bbb(0) or mb_msk25_b(8) ); + u_mb_mask_9: mb_mask(9) <= not( mb_msk01bbb(0) or mb_msk25_b(9) ); + u_mb_mask_10: mb_mask(10) <= not( mb_msk01bbb(0) or mb_msk25_b(10) ); + u_mb_mask_11: mb_mask(11) <= not( mb_msk01bbb(0) or mb_msk25_b(11) ); + u_mb_mask_12: mb_mask(12) <= not( mb_msk01bbb(0) or mb_msk25_b(12) ); + u_mb_mask_13: mb_mask(13) <= not( mb_msk01bbb(0) or mb_msk25_b(13) ); + u_mb_mask_14: mb_mask(14) <= not( mb_msk01bbb(0) or mb_msk25_b(14) ); + u_mb_mask_15: mb_mask(15) <= not( mb_msk01bbb(0) ); + u_mb_mask_16: mb_mask(16) <= not( mb_msk01bbb(0) and ( mb_msk01bbb(1) or mb_msk25_b(0) ) ); + u_mb_mask_17: mb_mask(17) <= not( mb_msk01bbb(0) and ( mb_msk01bbb(1) or mb_msk25_b(1) ) ); + u_mb_mask_18: mb_mask(18) <= not( mb_msk01bbb(0) and ( mb_msk01bbb(1) or mb_msk25_b(2) ) ); + u_mb_mask_19: mb_mask(19) <= not( mb_msk01bbb(0) and ( mb_msk01bbb(1) or mb_msk25_b(3) ) ); + u_mb_mask_20: mb_mask(20) <= not( mb_msk01bbb(0) and ( mb_msk01bbb(1) or mb_msk25_b(4) ) ); + u_mb_mask_21: mb_mask(21) <= not( mb_msk01bbb(0) and ( mb_msk01bbb(1) or mb_msk25_b(5) ) ); + u_mb_mask_22: mb_mask(22) <= not( mb_msk01bbb(0) and ( mb_msk01bbb(1) or mb_msk25_b(6) ) ); + u_mb_mask_23: mb_mask(23) <= not( mb_msk01bbb(0) and ( mb_msk01bbb(1) or mb_msk25_b(7) ) ); + u_mb_mask_24: mb_mask(24) <= not( mb_msk01bbb(0) and ( mb_msk01bbb(1) or mb_msk25_b(8) ) ); + u_mb_mask_25: mb_mask(25) <= not( mb_msk01bbb(0) and ( mb_msk01bbb(1) or mb_msk25_b(9) ) ); + u_mb_mask_26: mb_mask(26) <= not( mb_msk01bbb(0) and ( mb_msk01bbb(1) or mb_msk25_b(10)) ); + u_mb_mask_27: mb_mask(27) <= not( mb_msk01bbb(0) and ( mb_msk01bbb(1) or mb_msk25_b(11)) ); + u_mb_mask_28: mb_mask(28) <= not( mb_msk01bbb(0) and ( mb_msk01bbb(1) or mb_msk25_b(12)) ); + u_mb_mask_29: mb_mask(29) <= not( mb_msk01bbb(0) and ( mb_msk01bbb(1) or mb_msk25_b(13)) ); + u_mb_mask_30: mb_mask(30) <= not( mb_msk01bbb(0) and ( mb_msk01bbb(1) or mb_msk25_b(14)) ); + u_mb_mask_31: mb_mask(31) <= not( mb_msk01bbb(1) ); + u_mb_mask_32: mb_mask(32) <= not( mb_msk01bbb(1) and ( mb_msk01bbb(2) or mb_msk25_b(0) ) ); + u_mb_mask_33: mb_mask(33) <= not( mb_msk01bbb(1) and ( mb_msk01bbb(2) or mb_msk25_b(1) ) ); + u_mb_mask_34: mb_mask(34) <= not( mb_msk01bbb(1) and ( mb_msk01bbb(2) or mb_msk25_b(2) ) ); + u_mb_mask_35: mb_mask(35) <= not( mb_msk01bbb(1) and ( mb_msk01bbb(2) or mb_msk25_b(3) ) ); + u_mb_mask_36: mb_mask(36) <= not( mb_msk01bbb(1) and ( mb_msk01bbb(2) or mb_msk25_b(4) ) ); + u_mb_mask_37: mb_mask(37) <= not( mb_msk01bbb(1) and ( mb_msk01bbb(2) or mb_msk25_b(5) ) ); + u_mb_mask_38: mb_mask(38) <= not( mb_msk01bbb(1) and ( mb_msk01bbb(2) or mb_msk25_b(6) ) ); + u_mb_mask_39: mb_mask(39) <= not( mb_msk01bbb(1) and ( mb_msk01bbb(2) or mb_msk25_b(7) ) ); + u_mb_mask_40: mb_mask(40) <= not( mb_msk01bbb(1) and ( mb_msk01bbb(2) or mb_msk25_b(8) ) ); + u_mb_mask_41: mb_mask(41) <= not( mb_msk01bbb(1) and ( mb_msk01bbb(2) or mb_msk25_b(9) ) ); + u_mb_mask_42: mb_mask(42) <= not( mb_msk01bbb(1) and ( mb_msk01bbb(2) or mb_msk25_b(10)) ); + u_mb_mask_43: mb_mask(43) <= not( mb_msk01bbb(1) and ( mb_msk01bbb(2) or mb_msk25_b(11)) ); + u_mb_mask_44: mb_mask(44) <= not( mb_msk01bbb(1) and ( mb_msk01bbb(2) or mb_msk25_b(12)) ); + u_mb_mask_45: mb_mask(45) <= not( mb_msk01bbb(1) and ( mb_msk01bbb(2) or mb_msk25_b(13)) ); + u_mb_mask_46: mb_mask(46) <= not( mb_msk01bbb(1) and ( mb_msk01bbb(2) or mb_msk25_b(14)) ); + u_mb_mask_47: mb_mask(47) <= not( mb_msk01bbb(2) ); + u_mb_mask_48: mb_mask(48) <= not( mb_msk01bbb(2) and mb_msk25_b(0) ); + u_mb_mask_49: mb_mask(49) <= not( mb_msk01bbb(2) and mb_msk25_b(1) ); + u_mb_mask_50: mb_mask(50) <= not( mb_msk01bbb(2) and mb_msk25_b(2) ); + u_mb_mask_51: mb_mask(51) <= not( mb_msk01bbb(2) and mb_msk25_b(3) ); + u_mb_mask_52: mb_mask(52) <= not( mb_msk01bbb(2) and mb_msk25_b(4) ); + u_mb_mask_53: mb_mask(53) <= not( mb_msk01bbb(2) and mb_msk25_b(5) ); + u_mb_mask_54: mb_mask(54) <= not( mb_msk01bbb(2) and mb_msk25_b(6) ); + u_mb_mask_55: mb_mask(55) <= not( mb_msk01bbb(2) and mb_msk25_b(7) ); + u_mb_mask_56: mb_mask(56) <= not( mb_msk01bbb(2) and mb_msk25_b(8) ); + u_mb_mask_57: mb_mask(57) <= not( mb_msk01bbb(2) and mb_msk25_b(9) ); + u_mb_mask_58: mb_mask(58) <= not( mb_msk01bbb(2) and mb_msk25_b(10) ); + u_mb_mask_59: mb_mask(59) <= not( mb_msk01bbb(2) and mb_msk25_b(11) ); + u_mb_mask_60: mb_mask(60) <= not( mb_msk01bbb(2) and mb_msk25_b(12) ); + u_mb_mask_61: mb_mask(61) <= not( mb_msk01bbb(2) and mb_msk25_b(13) ); + u_mb_mask_62: mb_mask(62) <= not( mb_msk01bbb(2) and mb_msk25_b(14) ); + mb_mask(63) <= tiup ; + + + + -- ----------------------------------------------------------------------------------------- + -- generate the ME mask + -- ----------------------------------------------------------------------------------------- + + -- level 1 (4 bit results) ------------ <3 loads on input> + + u_me_msk45_1: me_msk45(1) <= not( me_b(4) and me_b(5) ); + u_me_msk45_2: me_msk45(2) <= not( me_b(4) ); + u_me_msk45_3: me_msk45(3) <= not( me_b(4) or me_b(5) ); + + u_me_msk23_1: me_msk23(1) <= not( me_b(2) and me_b(3) ); + u_me_msk23_2: me_msk23(2) <= not( me_b(2) ); + u_me_msk23_3: me_msk23(3) <= not( me_b(2) or me_b(3) ); + + u_me_msk01_1: me_msk01(1) <= not( me_b(0) and me_b(1) ); + u_me_msk01_2: me_msk01(2) <= not( me_b(0) ); + u_me_msk01_3: me_msk01(3) <= not( me_b(0) or me_b(1) ); + + + u_me_msk45b1: me_msk45_b(1) <= not( me_msk45(1) ); + u_me_msk45b2: me_msk45_b(2) <= not( me_msk45(2) ); + u_me_msk45b3: me_msk45_b(3) <= not( me_msk45(3) ); + u_me_msk23b1: me_msk23_b(1) <= not( me_msk23(1) ); -- 7 loads on output + u_me_msk23b2: me_msk23_b(2) <= not( me_msk23(2) ); + u_me_msk23b3: me_msk23_b(3) <= not( me_msk23(3) ); + u_me_msk01b1: me_msk01_b(1) <= not( me_msk01(1) ); + u_me_msk01b2: me_msk01_b(2) <= not( me_msk01(2) ); + u_me_msk01b3: me_msk01_b(3) <= not( me_msk01(3) ); + + + -- level 2 (16 bit results) ------------- + + + u_me_msk25_1: me_msk25(1) <= not( me_msk23_b(1) and me_msk45_b(1) ); -- amt >= 1 4:15 + 1:3 + u_me_msk25_2: me_msk25(2) <= not( me_msk23_b(1) and me_msk45_b(2) ); -- amt >= 2 4:15 + 2:3 + u_me_msk25_3: me_msk25(3) <= not( me_msk23_b(1) and me_msk45_b(3) ); -- amt >= 3 4:15 + 3:3 + u_me_msk25_4: me_msk25(4) <= not( me_msk23_b(1) ); -- amt >= 4 4:15 + u_me_msk25_5: me_msk25(5) <= not( me_msk23_b(2) and ( me_msk23_b(1) or me_msk45_b(1) ) ); -- amt >= 5 8:15 + (4:15 * 1:3) + u_me_msk25_6: me_msk25(6) <= not( me_msk23_b(2) and ( me_msk23_b(1) or me_msk45_b(2) ) ); -- amt >= 6 8:15 + (4:15 * 2:3) + u_me_msk25_7: me_msk25(7) <= not( me_msk23_b(2) and ( me_msk23_b(1) or me_msk45_b(3) ) ); -- amt >= 7 8:15 + (4:15 * 3:3) + u_me_msk25_8: me_msk25(8) <= not( me_msk23_b(2) ); -- amt >= 8 8:15 + u_me_msk25_9: me_msk25(9) <= not( me_msk23_b(3) and ( me_msk23_b(2) or me_msk45_b(1) ) ); -- amt >= 9 12:15 + (8:15 * 1:3) + u_me_msk25_10: me_msk25(10) <= not( me_msk23_b(3) and ( me_msk23_b(2) or me_msk45_b(2) ) ); -- amt >= 10 12:15 + (8:15 * 2:3) + u_me_msk25_11: me_msk25(11) <= not( me_msk23_b(3) and ( me_msk23_b(2) or me_msk45_b(3) ) ); -- amt >= 11 12:15 + (8:15 * 3:3) + u_me_msk25_12: me_msk25(12) <= not( me_msk23_b(3) ); -- amt >= 12 12:15 + u_me_msk25_13: me_msk25(13) <= not( me_msk23_b(3) or me_msk45_b(1) ); -- amt >= 13 12:15 & 1:3 + u_me_msk25_14: me_msk25(14) <= not( me_msk23_b(3) or me_msk45_b(2) ); -- amt >= 14 12:15 & 2:3 + u_me_msk25_15: me_msk25(15) <= not( me_msk23_b(3) or me_msk45_b(3) ); -- amt >= 15 12:15 & 3:3 + + u_me_msk01bb1: me_msk01bb(1) <= not( me_msk01_b(1) ); + u_me_msk01bb2: me_msk01bb(2) <= not( me_msk01_b(2) ); + u_me_msk01bb3: me_msk01bb(3) <= not( me_msk01_b(3) ); + + + u_me_msk25b1: me_msk25_b(1) <= not( me_msk25(1) ); + u_me_msk25b2: me_msk25_b(2) <= not( me_msk25(2) ); + u_me_msk25b3: me_msk25_b(3) <= not( me_msk25(3) ); + u_me_msk25b4: me_msk25_b(4) <= not( me_msk25(4) ); + u_me_msk25b5: me_msk25_b(5) <= not( me_msk25(5) ); + u_me_msk25b6: me_msk25_b(6) <= not( me_msk25(6) ); + u_me_msk25b7: me_msk25_b(7) <= not( me_msk25(7) ); + u_me_msk25b8: me_msk25_b(8) <= not( me_msk25(8) ); + u_me_msk25b9: me_msk25_b(9) <= not( me_msk25(9) ); + u_me_msk25b10: me_msk25_b(10) <= not( me_msk25(10) ); + u_me_msk25b11: me_msk25_b(11) <= not( me_msk25(11) ); + u_me_msk25b12: me_msk25_b(12) <= not( me_msk25(12) ); + u_me_msk25b13: me_msk25_b(13) <= not( me_msk25(13) ); + u_me_msk25b14: me_msk25_b(14) <= not( me_msk25(14) ); + u_me_msk25b15: me_msk25_b(15) <= not( me_msk25(15) ); + + u_me_msk01bbb1: me_msk01bbb(1) <= not( me_msk01bb(1) ); + u_me_msk01bbb2: me_msk01bbb(2) <= not( me_msk01bb(2) ); + u_me_msk01bbb3: me_msk01bbb(3) <= not( me_msk01bb(3) ); + + + -- level 3 (16 bit results) ------------- + + me_mask(0) <= tiup ; + u_me_mask_1: me_mask(1) <= not( me_msk01bbb(1) and me_msk25_b(1) ); + u_me_mask_2: me_mask(2) <= not( me_msk01bbb(1) and me_msk25_b(2) ); + u_me_mask_3: me_mask(3) <= not( me_msk01bbb(1) and me_msk25_b(3) ); + u_me_mask_4: me_mask(4) <= not( me_msk01bbb(1) and me_msk25_b(4) ); + u_me_mask_5: me_mask(5) <= not( me_msk01bbb(1) and me_msk25_b(5) ); + u_me_mask_6: me_mask(6) <= not( me_msk01bbb(1) and me_msk25_b(6) ); + u_me_mask_7: me_mask(7) <= not( me_msk01bbb(1) and me_msk25_b(7) ); + u_me_mask_8: me_mask(8) <= not( me_msk01bbb(1) and me_msk25_b(8) ); + u_me_mask_9: me_mask(9) <= not( me_msk01bbb(1) and me_msk25_b(9) ); + u_me_mask_10: me_mask(10) <= not( me_msk01bbb(1) and me_msk25_b(10) ); + u_me_mask_11: me_mask(11) <= not( me_msk01bbb(1) and me_msk25_b(11) ); + u_me_mask_12: me_mask(12) <= not( me_msk01bbb(1) and me_msk25_b(12) ); + u_me_mask_13: me_mask(13) <= not( me_msk01bbb(1) and me_msk25_b(13) ); + u_me_mask_14: me_mask(14) <= not( me_msk01bbb(1) and me_msk25_b(14) ); + u_me_mask_15: me_mask(15) <= not( me_msk01bbb(1) and me_msk25_b(15) ); + u_me_mask_16: me_mask(16) <= not( me_msk01bbb(1) ); + u_me_mask_17: me_mask(17) <= not( me_msk01bbb(2) and ( me_msk01bbb(1) or me_msk25_b(1) ) ); + u_me_mask_18: me_mask(18) <= not( me_msk01bbb(2) and ( me_msk01bbb(1) or me_msk25_b(2) ) ); + u_me_mask_19: me_mask(19) <= not( me_msk01bbb(2) and ( me_msk01bbb(1) or me_msk25_b(3) ) ); + u_me_mask_20: me_mask(20) <= not( me_msk01bbb(2) and ( me_msk01bbb(1) or me_msk25_b(4) ) ); + u_me_mask_21: me_mask(21) <= not( me_msk01bbb(2) and ( me_msk01bbb(1) or me_msk25_b(5) ) ); + u_me_mask_22: me_mask(22) <= not( me_msk01bbb(2) and ( me_msk01bbb(1) or me_msk25_b(6) ) ); + u_me_mask_23: me_mask(23) <= not( me_msk01bbb(2) and ( me_msk01bbb(1) or me_msk25_b(7) ) ); + u_me_mask_24: me_mask(24) <= not( me_msk01bbb(2) and ( me_msk01bbb(1) or me_msk25_b(8) ) ); + u_me_mask_25: me_mask(25) <= not( me_msk01bbb(2) and ( me_msk01bbb(1) or me_msk25_b(9) ) ); + u_me_mask_26: me_mask(26) <= not( me_msk01bbb(2) and ( me_msk01bbb(1) or me_msk25_b(10)) ); + u_me_mask_27: me_mask(27) <= not( me_msk01bbb(2) and ( me_msk01bbb(1) or me_msk25_b(11)) ); + u_me_mask_28: me_mask(28) <= not( me_msk01bbb(2) and ( me_msk01bbb(1) or me_msk25_b(12)) ); + u_me_mask_29: me_mask(29) <= not( me_msk01bbb(2) and ( me_msk01bbb(1) or me_msk25_b(13)) ); + u_me_mask_30: me_mask(30) <= not( me_msk01bbb(2) and ( me_msk01bbb(1) or me_msk25_b(14)) ); + u_me_mask_31: me_mask(31) <= not( me_msk01bbb(2) and ( me_msk01bbb(1) or me_msk25_b(15)) ); + u_me_mask_32: me_mask(32) <= not( me_msk01bbb(2) ); + u_me_mask_33: me_mask(33) <= not( me_msk01bbb(3) and ( me_msk01bbb(2) or me_msk25_b(1) ) ); + u_me_mask_34: me_mask(34) <= not( me_msk01bbb(3) and ( me_msk01bbb(2) or me_msk25_b(2) ) ); + u_me_mask_35: me_mask(35) <= not( me_msk01bbb(3) and ( me_msk01bbb(2) or me_msk25_b(3) ) ); + u_me_mask_36: me_mask(36) <= not( me_msk01bbb(3) and ( me_msk01bbb(2) or me_msk25_b(4) ) ); + u_me_mask_37: me_mask(37) <= not( me_msk01bbb(3) and ( me_msk01bbb(2) or me_msk25_b(5) ) ); + u_me_mask_38: me_mask(38) <= not( me_msk01bbb(3) and ( me_msk01bbb(2) or me_msk25_b(6) ) ); + u_me_mask_39: me_mask(39) <= not( me_msk01bbb(3) and ( me_msk01bbb(2) or me_msk25_b(7) ) ); + u_me_mask_40: me_mask(40) <= not( me_msk01bbb(3) and ( me_msk01bbb(2) or me_msk25_b(8) ) ); + u_me_mask_41: me_mask(41) <= not( me_msk01bbb(3) and ( me_msk01bbb(2) or me_msk25_b(9) ) ); + u_me_mask_42: me_mask(42) <= not( me_msk01bbb(3) and ( me_msk01bbb(2) or me_msk25_b(10)) ); + u_me_mask_43: me_mask(43) <= not( me_msk01bbb(3) and ( me_msk01bbb(2) or me_msk25_b(11)) ); + u_me_mask_44: me_mask(44) <= not( me_msk01bbb(3) and ( me_msk01bbb(2) or me_msk25_b(12)) ); + u_me_mask_45: me_mask(45) <= not( me_msk01bbb(3) and ( me_msk01bbb(2) or me_msk25_b(13)) ); + u_me_mask_46: me_mask(46) <= not( me_msk01bbb(3) and ( me_msk01bbb(2) or me_msk25_b(14)) ); + u_me_mask_47: me_mask(47) <= not( me_msk01bbb(3) and ( me_msk01bbb(2) or me_msk25_b(15)) ); + u_me_mask_48: me_mask(48) <= not( me_msk01bbb(3) ); + u_me_mask_49: me_mask(49) <= not( me_msk01bbb(3) or me_msk25_b(1) ); + u_me_mask_50: me_mask(50) <= not( me_msk01bbb(3) or me_msk25_b(2) ); + u_me_mask_51: me_mask(51) <= not( me_msk01bbb(3) or me_msk25_b(3) ); + u_me_mask_52: me_mask(52) <= not( me_msk01bbb(3) or me_msk25_b(4) ); + u_me_mask_53: me_mask(53) <= not( me_msk01bbb(3) or me_msk25_b(5) ); + u_me_mask_54: me_mask(54) <= not( me_msk01bbb(3) or me_msk25_b(6) ); + u_me_mask_55: me_mask(55) <= not( me_msk01bbb(3) or me_msk25_b(7) ); + u_me_mask_56: me_mask(56) <= not( me_msk01bbb(3) or me_msk25_b(8) ); + u_me_mask_57: me_mask(57) <= not( me_msk01bbb(3) or me_msk25_b(9) ); + u_me_mask_58: me_mask(58) <= not( me_msk01bbb(3) or me_msk25_b(10) ); + u_me_mask_59: me_mask(59) <= not( me_msk01bbb(3) or me_msk25_b(11) ); + u_me_mask_60: me_mask(60) <= not( me_msk01bbb(3) or me_msk25_b(12) ); + u_me_mask_61: me_mask(61) <= not( me_msk01bbb(3) or me_msk25_b(13) ); + u_me_mask_62: me_mask(62) <= not( me_msk01bbb(3) or me_msk25_b(14) ); + u_me_mask_63: me_mask(63) <= not( me_msk01bbb(3) or me_msk25_b(15) ); + + + -- ------------------------------------------------------------------------------------------ + -- Generally the mask starts at bit MB[] and ends at bit ME[] ... (MB[] and ME[]) + -- For non-rotate/shift operations the mask is forced to zero by the ZM control. + -- There are 3 rotate-word operations where MB could be greater than ME. + -- in that case the mask is speced to be (MB[] or ME[]). + -- For those cases, the mask always comes from the instruction bits, is always word mode, + -- and the MB>ME compare can be done during the instruction decode cycle. + -- ------------------------------------------------------------------------------------------- + + mask_en_and <= not mb_gt_me and not zm ; -- could restrict this to only rotates if shifts included below + mask_en_mb <= mb_gt_me and not zm ; -- could alternatively include shift right + mask_en_me <= mb_gt_me and not zm ; -- could alternatively include shift left + + u_mask0: mask0_b(0 to 63) <= not( mb_mask(0 to 63) and me_mask(0 to 63) and (0 to 63=> mask_en_and) ); + u_mask1: mask1_b(0 to 63) <= not( mb_mask(0 to 63) and (0 to 63=> mask_en_mb) ); + u_mask2: mask2_b(0 to 63) <= not( me_mask(0 to 63) and (0 to 63=> mask_en_me) ); + + u_mask: mask(0 to 63) <= not( mask0_b(0 to 63) and mask1_b(0 to 63) and mask2_b(0 to 63) ); + + +end architecture xuq_alu_mask; diff --git a/rel/src/vhdl/work/xuq_alu_mrg.vhdl b/rel/src/vhdl/work/xuq_alu_mrg.vhdl new file mode 100644 index 0000000..485605a --- /dev/null +++ b/rel/src/vhdl/work/xuq_alu_mrg.vhdl @@ -0,0 +1,824 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XU Rotate/Logical/ALU merge Unit +-- +library work,ieee,ibm,support,tri; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_unsigned.all; +use ibm.std_ulogic_function_support.all; +use support.power_logic_pkg.all; +use tri.tri_latches_pkg.all; + +entity xuq_alu_mrg is + generic( + expand_type : integer := 2); + port ( + nclk : in clk_logic; + vdd : inout power_logic; + gnd : inout power_logic; + d_mode_dc : in std_ulogic; + delay_lclkr_dc : in std_ulogic; + mpw1_dc_b : in std_ulogic; + mpw2_dc_b : in std_ulogic; + func_sl_force : in std_ulogic; + func_sl_thold_0_b : in std_ulogic; + sg_0 : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + rf1_act : in std_ulogic; + ex1_act : in std_ulogic; + + dec_alu_rf1_zm_ins : in std_ulogic ; + dec_alu_rf1_mb_ins : in std_ulogic_vector(0 to 5); + dec_alu_rf1_me_ins_b : in std_ulogic_vector(0 to 5); + dec_alu_rf1_sh_amt : in std_ulogic_vector(0 to 5); + dec_alu_rf1_sh_right : in std_ulogic; + dec_alu_rf1_sh_word : in std_ulogic; + + + dec_alu_rf1_use_rb_amt_hi : in std_ulogic; + dec_alu_rf1_use_rb_amt_lo : in std_ulogic; + dec_alu_rf1_use_me_rb_hi : in std_ulogic; + dec_alu_rf1_use_me_rb_lo : in std_ulogic; + dec_alu_rf1_use_mb_rb_hi : in std_ulogic; + dec_alu_rf1_use_mb_rb_lo : in std_ulogic; + dec_alu_rf1_use_me_ins_hi : in std_ulogic; + dec_alu_rf1_use_me_ins_lo : in std_ulogic; + dec_alu_rf1_use_mb_ins_hi : in std_ulogic; + dec_alu_rf1_use_mb_ins_lo : in std_ulogic; + + dec_alu_rf1_chk_shov_wd : in std_ulogic; + dec_alu_rf1_chk_shov_dw : in std_ulogic; + dec_alu_rf1_mb_gt_me : in std_ulogic; + + dec_alu_rf1_cmp_byt : in std_ulogic; + + dec_alu_rf1_sgnxtd_byte : in std_ulogic; + dec_alu_rf1_sgnxtd_half : in std_ulogic; + dec_alu_rf1_sgnxtd_wd : in std_ulogic; + dec_alu_rf1_sra_wd : in std_ulogic; + dec_alu_rf1_sra_dw : in std_ulogic; + + byp_alu_rf1_isel_fcn : in std_ulogic_vector(0 to 3); + dec_alu_rf1_log_fcn : in std_ulogic_vector(0 to 3); + dec_alu_rf1_sel_rot_log : in std_ulogic; + + byp_alu_ex1_rs0_b : in std_ulogic_vector(0 to 63); --rb/ra + byp_alu_ex1_rs1_b : in std_ulogic_vector(0 to 63); --rs + add_mrg_ex1_add_rt : in std_ulogic_vector(0 to 63); + mrg_add_ex2_rt : out std_ulogic_vector(0 to 63); + alu_byp_ex1_log_rt : out std_ulogic_vector(0 to 63); + + ex2_mrg_xer_ca : out std_ulogic + + ); +-- synopsys translate_off +-- synopsys translate_on + +end xuq_alu_mrg; + +architecture xuq_alu_mrg of xuq_alu_mrg is + +-- Latches +signal ex1_mb_ins_q : std_ulogic_vector(0 to 5); -- input=>dec_alu_rf1_mb_ins ,act=>rf1_act -- ins_mb +signal ex1_me_ins_b_q : std_ulogic_vector(0 to 5); -- input=>dec_alu_rf1_me_ins_b ,act=>rf1_act -- ins_me_b +signal ex1_sh_amt_q : std_ulogic_vector(0 to 5); -- input=>dec_alu_rf1_sh_amt ,act=>rf1_act -- ins_amt +signal ex1_sh_right_q, rf1_sh_right : std_ulogic_vector(0 to 2); -- input=>dec_alu_rf1_sh_rgt ,act=>rf1_act -- ins_rgt +signal ex1_sh_word_q, rf1_sh_word : std_ulogic_vector(0 to 1); -- input=>dec_alu_rf1_sh_word ,act=>rf1_act -- ins_word +signal ex1_zm_ins_q : std_ulogic; -- input=>dec_alu_rf1_zm_ins ,act=>rf1_act -- ins_word_dly +signal ex1_chk_shov_wd_q : std_ulogic; -- input=>dec_alu_rf1_chk_shov_wd ,act=>rf1_act -- ins_zm +signal ex1_chk_shov_dw_q : std_ulogic; -- input=>dec_alu_rf1_chk_shov_dw ,act=>rf1_act -- chk_shov_wd +signal ex1_use_sh_amt_hi_q, rf1_use_sh_amt_hi : std_ulogic; -- act=>rf1_act -- chk_shov_dw +signal ex1_use_sh_amt_lo_q, rf1_use_sh_amt_lo : std_ulogic; -- act=>rf1_act -- use_ins_amt_din(0) +signal ex1_use_rb_amt_hi_q : std_ulogic; -- input=>dec_alu_rf1_use_rb_amt_hi ,act=>rf1_act -- use_ins_amt_din(1) +signal ex1_use_rb_amt_lo_q : std_ulogic; -- input=>dec_alu_rf1_use_rb_amt_lo ,act=>rf1_act -- use_rb_amt_din(0) +signal ex1_use_me_rb_hi_q : std_ulogic; -- input=>dec_alu_rf1_use_me_rb_hi ,act=>rf1_act -- use_rb_amt_din(1) +signal ex1_use_me_rb_lo_q : std_ulogic; -- input=>dec_alu_rf1_use_me_rb_lo ,act=>rf1_act -- use_mb_i(0) +signal ex1_use_mb_rb_hi_q : std_ulogic; -- input=>dec_alu_rf1_use_mb_rb_hi ,act=>rf1_act -- use_mb_i(1) +signal ex1_use_mb_rb_lo_q : std_ulogic; -- input=>dec_alu_rf1_use_mb_rb_lo ,act=>rf1_act -- use_me_i(0) +signal ex1_use_me_ins_hi_q : std_ulogic; -- input=>dec_alu_rf1_use_me_ins_hi ,act=>rf1_act -- use_me_i(1) +signal ex1_use_me_ins_lo_q : std_ulogic; -- input=>dec_alu_rf1_use_me_ins_lo ,act=>rf1_act -- use_ins_mb_i(0) +signal ex1_use_mb_ins_hi_q : std_ulogic; -- input=>dec_alu_rf1_use_mb_ins_hi ,act=>rf1_act -- use_ins_mb_i(1) +signal ex1_use_mb_ins_lo_q : std_ulogic; -- input=>dec_alu_rf1_use_mb_ins_lo ,act=>rf1_act -- use_ins_me_i(0) +signal ex1_mb_gt_me_q : std_ulogic; -- input=>dec_alu_rf1_mb_gt_me ,act=>rf1_act -- use_ins_me_i(1) +signal ex1_cmp_byte_q : std_ulogic; -- input=>dec_alu_rf1_cmp_byt ,act=>rf1_act -- mb_gt_me +signal ex1_sgnxtd_byte_q : std_ulogic; -- input=>dec_alu_rf1_sgnxtd_byte ,act=>rf1_act -- ins_cmp_byt_i +signal ex1_sgnxtd_half_q : std_ulogic; -- input=>dec_alu_rf1_sgnxtd_half ,act=>rf1_act -- ins_xtd_byte_i +signal ex1_sgnxtd_wd_q : std_ulogic; -- input=>dec_alu_rf1_sgnxtd_wd ,act=>rf1_act -- ins_xtd_half_i +signal ex1_sra_wd_q : std_ulogic; -- input=>dec_alu_rf1_sra_wd ,act=>rf1_act -- ins_xtd_wd_i +signal ex1_sra_dw_q : std_ulogic; -- input=>dec_alu_rf1_sra_dw ,act=>rf1_act -- ins_sra_wd_i +signal ex1_log_fcn_q, rf1_log_fcn : std_ulogic_vector(0 to 3); -- input=>rf1_log_fcn ,act=>rf1_act -- ins_sra_dw_i +signal ex1_sel_rot_log_q : std_ulogic; -- input=>dec_alu_rf1_sel_rot_log ,act=>rf1_act -- ins_log_fcn_i +signal ex2_sh_word_q : std_ulogic; -- input=>ex1_sh_word_q(1) ,act=>ex1_act -- ins_sel_mrg_i +signal ex2_rotate_b_q, ex1_result : std_ulogic_vector(0 to 63); -- act=>ex1_act +signal ex2_result_b_q, ex1_rotate : std_ulogic_vector(0 to 63); -- act=>ex1_act +signal ex2_mask_b_q, ex1_mask : std_ulogic_vector(0 to 63); -- act=>ex1_act +signal ex2_sra_se_q, ex1_sra_se_b : std_ulogic_vector(0 to 0); -- act=>ex1_act +signal dummy_q : std_ulogic_vector(0 to 0); +-- Scanchains +constant ex1_mb_ins_offset : integer := 0; +constant ex1_me_ins_b_offset : integer := ex1_mb_ins_offset + ex1_mb_ins_q'length; +constant ex1_sh_amt_offset : integer := ex1_me_ins_b_offset + ex1_me_ins_b_q'length; +constant ex1_sh_right_offset : integer := ex1_sh_amt_offset + ex1_sh_amt_q'length; +constant ex1_sh_word_offset : integer := ex1_sh_right_offset + ex1_sh_right_q'length; +constant ex1_zm_ins_offset : integer := ex1_sh_word_offset + ex1_sh_word_q'length; +constant ex1_chk_shov_wd_offset : integer := ex1_zm_ins_offset + 1; +constant ex1_chk_shov_dw_offset : integer := ex1_chk_shov_wd_offset + 1; +constant ex1_use_sh_amt_hi_offset : integer := ex1_chk_shov_dw_offset + 1; +constant ex1_use_sh_amt_lo_offset : integer := ex1_use_sh_amt_hi_offset + 1; +constant ex1_use_rb_amt_hi_offset : integer := ex1_use_sh_amt_lo_offset + 1; +constant ex1_use_rb_amt_lo_offset : integer := ex1_use_rb_amt_hi_offset + 1; +constant ex1_use_me_rb_hi_offset : integer := ex1_use_rb_amt_lo_offset + 1; +constant ex1_use_me_rb_lo_offset : integer := ex1_use_me_rb_hi_offset + 1; +constant ex1_use_mb_rb_hi_offset : integer := ex1_use_me_rb_lo_offset + 1; +constant ex1_use_mb_rb_lo_offset : integer := ex1_use_mb_rb_hi_offset + 1; +constant ex1_use_me_ins_hi_offset : integer := ex1_use_mb_rb_lo_offset + 1; +constant ex1_use_me_ins_lo_offset : integer := ex1_use_me_ins_hi_offset + 1; +constant ex1_use_mb_ins_hi_offset : integer := ex1_use_me_ins_lo_offset + 1; +constant ex1_use_mb_ins_lo_offset : integer := ex1_use_mb_ins_hi_offset + 1; +constant ex1_mb_gt_me_offset : integer := ex1_use_mb_ins_lo_offset + 1; +constant ex1_cmp_byte_offset : integer := ex1_mb_gt_me_offset + 1; +constant ex1_sgnxtd_byte_offset : integer := ex1_cmp_byte_offset + 1; +constant ex1_sgnxtd_half_offset : integer := ex1_sgnxtd_byte_offset + 1; +constant ex1_sgnxtd_wd_offset : integer := ex1_sgnxtd_half_offset + 1; +constant ex1_sra_wd_offset : integer := ex1_sgnxtd_wd_offset + 1; +constant ex1_sra_dw_offset : integer := ex1_sra_wd_offset + 1; +constant ex1_log_fcn_offset : integer := ex1_sra_dw_offset + 1; +constant ex1_sel_rot_log_offset : integer := ex1_log_fcn_offset + ex1_log_fcn_q'length; +constant ex2_sh_word_offset : integer := ex1_sel_rot_log_offset + 1; +constant ex2_rotate_b_offset : integer := ex2_sh_word_offset + 1; +constant ex2_result_b_offset : integer := ex2_rotate_b_offset + ex2_rotate_b_q'length; +constant ex2_mask_b_offset : integer := ex2_result_b_offset + ex2_result_b_q'length; +constant ex2_sra_se_offset : integer := ex2_mask_b_offset + ex2_mask_b_q'length; +constant dummy_offset : integer := ex2_sra_se_offset + ex2_sra_se_q'length; +constant scan_right : integer := dummy_offset + dummy_q'length; +signal siv : std_ulogic_vector(0 to scan_right-1); +signal sov : std_ulogic_vector(0 to scan_right-1); +signal tidn : std_ulogic; +signal rot_lclk_int : clk_logic; +signal rot_d1clk_int, rot_d2clk_int : std_ulogic; +signal ex1_zm : std_ulogic; +signal ex1_use_sh_amt, ex1_use_rb_amt : std_ulogic_vector(0 to 5); +signal ex1_use_me_rb, ex1_use_mb_rb : std_ulogic_vector(0 to 5); +signal ex1_use_me_ins, ex1_use_mb_ins : std_ulogic_vector(0 to 5); +signal ex1_sh_amt0_b, ex1_sh_amt1_b, ex1_sh_amt : std_ulogic_vector(0 to 5); +signal ex1_mb0_b, ex1_mb1_b, ex1_mb : std_ulogic_vector(0 to 5); +signal ex1_me0, ex1_me1, ex1_me_b : std_ulogic_vector(0 to 5); +signal ex1_mask_b, ex1_insert : std_ulogic_vector(0 to 63); +signal ex1_sel_add : std_ulogic; +signal ex1_msk_rot_b, ex1_msk_ins_b, ex1_msk_rot : std_ulogic_vector(0 to 63); +signal ex1_msk_ins : std_ulogic_vector(0 to 63); +signal ex1_result_0_b, ex1_result_1_b, ex1_result_2_b : std_ulogic_vector(0 to 63); +signal ca_root_b : std_ulogic_vector(0 to 63); +signal ca_or_hi, ca_or_lo : std_ulogic; +signal ex1_act_unqiue : std_ulogic; +signal ex1_ins_rs0, ex1_ins_rs1, ex1_rot_rs0 : std_ulogic_vector(0 to 63); +signal ex1_rot_rs1 : std_ulogic_vector(57 to 63); +signal ex2_result_q, ex2_rotate_q : std_ulogic_vector(0 to 63); + + +begin + +tidn <= '0'; + +rf1_sh_right <= (0 to 2=>dec_alu_rf1_sh_right); +rf1_sh_word <= (0 to 1=>dec_alu_rf1_sh_word); +rf1_use_sh_amt_hi <= not dec_alu_rf1_use_rb_amt_hi; +rf1_use_sh_amt_lo <= not dec_alu_rf1_use_rb_amt_lo; + +--------------------------------------------------------------------- +-- Source Buffering +--------------------------------------------------------------------- +u_rot_s0_pass: ex1_ins_rs0 <= not byp_alu_ex1_rs0_b; +u_rot_s1_pass: ex1_ins_rs1 <= not byp_alu_ex1_rs1_b; +u_rot_s0: ex1_rot_rs0 <= not byp_alu_ex1_rs0_b; +u_rot_s1: ex1_rot_rs1 <= not byp_alu_ex1_rs1_b(57 to 63); + +--------------------------------------------------------------------- +-- Rotator / merge control generation +--------------------------------------------------------------------- +ex1_use_sh_amt <= ex1_use_sh_amt_hi_q & (1 to 5=>ex1_use_sh_amt_lo_q); +ex1_use_rb_amt <= ex1_use_rb_amt_hi_q & (1 to 5=>ex1_use_rb_amt_lo_q); +ex1_use_me_rb <= ex1_use_me_rb_hi_q & (1 to 5=>ex1_use_me_rb_lo_q); +ex1_use_mb_rb <= ex1_use_mb_rb_hi_q & (1 to 5=>ex1_use_mb_rb_lo_q); +ex1_use_me_ins <= ex1_use_me_ins_hi_q & (1 to 5=>ex1_use_me_ins_lo_q); +ex1_use_mb_ins <= ex1_use_mb_ins_hi_q & (1 to 5=>ex1_use_mb_ins_lo_q); + +ex1_zm <= (ex1_zm_ins_q ) or -- instr does not use the rotator (dont care if adder used) + (ex1_chk_shov_wd_q and ex1_rot_rs1(58)) or -- word shift with amount from RB + (ex1_chk_shov_dw_q and ex1_rot_rs1(57)); -- doubleword shift with amount from RB + + +u_shamt0: ex1_sh_amt0_b <= ex1_rot_rs1(58 to 63) nand ex1_use_rb_amt; +u_shamt1: ex1_sh_amt1_b <= ex1_sh_amt_q nand ex1_use_sh_amt; + +u_shamt: ex1_sh_amt <= ex1_sh_amt0_b nand ex1_sh_amt1_b; + + +u_mbamt0: ex1_mb0_b <= ex1_rot_rs1(58 to 63) nand ex1_use_mb_rb; +u_mbamt1: ex1_mb1_b <= ex1_mb_ins_q nand ex1_use_mb_ins; + +u_mbamt: ex1_mb <= ex1_mb0_b nand ex1_mb1_b; + + +u_meamt0: ex1_me0 <= ex1_rot_rs1(58 to 63) nand ex1_use_me_rb; +u_meamt1: ex1_me1 <= ex1_me_ins_b_q nand ex1_use_me_ins; + +u_meamt: ex1_me_b <= ex1_me0 nand ex1_me1; + + +--------------------------------------------------------------------- +-- Mask unit +--------------------------------------------------------------------- +msk: entity work.xuq_alu_mask(xuq_alu_mask) + generic map (expand_type => expand_type) + port map( + mb => ex1_mb, + me_b => ex1_me_b, + zm => ex1_zm, + mb_gt_me => ex1_mb_gt_me_q, + mask => ex1_mask); + +--------------------------------------------------------------------- +-- Insert data (includes logicals, sign extend, cmpb) +--------------------------------------------------------------------- +rf1_log_fcn <= dec_alu_rf1_log_fcn or byp_alu_rf1_isel_fcn; + +ins: entity work.xuq_alu_ins(xuq_alu_ins) + generic map (expand_type => expand_type) + port map( + ins_log_fcn => ex1_log_fcn_q, + ins_cmp_byt => ex1_cmp_byte_q, + ins_sra_dw => ex1_sra_dw_q, + ins_sra_wd => ex1_sra_wd_q, + ins_xtd_byte => ex1_sgnxtd_byte_q, + ins_xtd_half => ex1_sgnxtd_half_q, + ins_xtd_wd => ex1_sgnxtd_wd_q, + data0_i => ex1_ins_rs0, + data1_i => ex1_ins_rs1, + mrg_byp_log => alu_byp_ex1_log_rt, + res_ins => ex1_insert ); + +--------------------------------------------------------------------- +-- Rotate unit +--------------------------------------------------------------------- +rol64: entity work.xuq_alu_rol64(xuq_alu_rol64) + generic map (expand_type => expand_type) + port map( + word => ex1_sh_word_q, + right => ex1_sh_right_q, + amt => ex1_sh_amt, + data_i => ex1_rot_rs0, + res_rot => ex1_rotate); + + +--------------------------------------------------------------------- +-- Final muxing +--------------------------------------------------------------------- +u_msk_inv: ex1_mask_b <= not ex1_mask; +u_seladd: ex1_sel_add <= not ex1_sel_rot_log_q; + +u_selrotb: ex1_msk_rot_b <= ex1_mask nand (0 to 63=> ex1_sel_rot_log_q); +u_selinsb: ex1_msk_ins_b <= ex1_mask_b nand (0 to 63=> ex1_sel_rot_log_q); + +u_selrot: ex1_msk_rot <= not ex1_msk_rot_b; +u_selins: ex1_msk_ins <= not ex1_msk_ins_b; + +u_res_din0: ex1_result_0_b <= ex1_rotate nand ex1_msk_rot; +u_res_din1: ex1_result_1_b <= ex1_insert nand ex1_msk_ins; +u_res_din2: ex1_result_2_b <= add_mrg_ex1_add_rt nand (0 to 63=> ex1_sel_add); +u_res_din: ex1_result <= not(ex1_result_0_b and ex1_result_1_b and ex1_result_2_b); + +u_res_q: ex2_result_q <= not ex2_result_b_q; + +mrg_add_ex2_rt <= ex2_result_q; + +--------------------------------------------------------------------- +-- CA Generation +--------------------------------------------------------------------- +caor: entity work.xuq_alu_caor(xuq_alu_caor) + generic map (expand_type => expand_type) + port map( + ca_root_b => ca_root_b, + ca_or_hi => ca_or_hi, + ca_or_lo => ca_or_lo); + +u_rot_inv: ex2_rotate_q <= not ex2_rotate_b_q; +u_ca_root: ca_root_b <= not(ex2_rotate_q and ex2_mask_b_q); + +ex1_sra_se_b(0)<= not((ex1_ins_rs0(0) and not ex1_sh_word_q(0)) or + (ex1_ins_rs0(32) and ex1_sh_word_q(0))); + +ex2_mrg_xer_ca <= ( ca_or_lo and ex2_sra_se_q(0) and ex2_sh_word_q) or + ((ca_or_lo or ca_or_hi) and ex2_sra_se_q(0) and not ex2_sh_word_q); + + +-- To generate a unique LCB for placement +ex1_act_unqiue <= ex1_act or dummy_q(0); + +--------------------------------------------------------------------- +-- Latch Instances +--------------------------------------------------------------------- +ex1_mb_ins_latch : tri_rlmreg_p + generic map (width => ex1_mb_ins_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_mb_ins_offset to ex1_mb_ins_offset + ex1_mb_ins_q'length-1), + scout => sov(ex1_mb_ins_offset to ex1_mb_ins_offset + ex1_mb_ins_q'length-1), + din => dec_alu_rf1_mb_ins, + dout => ex1_mb_ins_q); +ex1_me_ins_b_latch : tri_rlmreg_p + generic map (width => ex1_me_ins_b_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_me_ins_b_offset to ex1_me_ins_b_offset + ex1_me_ins_b_q'length-1), + scout => sov(ex1_me_ins_b_offset to ex1_me_ins_b_offset + ex1_me_ins_b_q'length-1), + din => dec_alu_rf1_me_ins_b, + dout => ex1_me_ins_b_q); +ex1_sh_amt_latch : tri_rlmreg_p + generic map (width => ex1_sh_amt_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_sh_amt_offset to ex1_sh_amt_offset + ex1_sh_amt_q'length-1), + scout => sov(ex1_sh_amt_offset to ex1_sh_amt_offset + ex1_sh_amt_q'length-1), + din => dec_alu_rf1_sh_amt, + dout => ex1_sh_amt_q); +ex1_sh_right_latch : tri_rlmreg_p + generic map (width => ex1_sh_right_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_sh_right_offset to ex1_sh_right_offset + ex1_sh_right_q'length-1), + scout => sov(ex1_sh_right_offset to ex1_sh_right_offset + ex1_sh_right_q'length-1), + din => rf1_sh_right, + dout => ex1_sh_right_q); +ex1_sh_word_latch : tri_rlmreg_p + generic map (width => ex1_sh_word_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_sh_word_offset to ex1_sh_word_offset + ex1_sh_word_q'length-1), + scout => sov(ex1_sh_word_offset to ex1_sh_word_offset + ex1_sh_word_q'length-1), + din => rf1_sh_word, + dout => ex1_sh_word_q); +ex1_zm_ins_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_zm_ins_offset), + scout => sov(ex1_zm_ins_offset), + din => dec_alu_rf1_zm_ins, + dout => ex1_zm_ins_q); +ex1_chk_shov_wd_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_chk_shov_wd_offset), + scout => sov(ex1_chk_shov_wd_offset), + din => dec_alu_rf1_chk_shov_wd, + dout => ex1_chk_shov_wd_q); +ex1_chk_shov_dw_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_chk_shov_dw_offset), + scout => sov(ex1_chk_shov_dw_offset), + din => dec_alu_rf1_chk_shov_dw, + dout => ex1_chk_shov_dw_q); +ex1_use_sh_amt_hi_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_use_sh_amt_hi_offset), + scout => sov(ex1_use_sh_amt_hi_offset), + din => rf1_use_sh_amt_hi, + dout => ex1_use_sh_amt_hi_q); +ex1_use_sh_amt_lo_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_use_sh_amt_lo_offset), + scout => sov(ex1_use_sh_amt_lo_offset), + din => rf1_use_sh_amt_lo, + dout => ex1_use_sh_amt_lo_q); +ex1_use_rb_amt_hi_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_use_rb_amt_hi_offset), + scout => sov(ex1_use_rb_amt_hi_offset), + din => dec_alu_rf1_use_rb_amt_hi, + dout => ex1_use_rb_amt_hi_q); +ex1_use_rb_amt_lo_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_use_rb_amt_lo_offset), + scout => sov(ex1_use_rb_amt_lo_offset), + din => dec_alu_rf1_use_rb_amt_lo, + dout => ex1_use_rb_amt_lo_q); +ex1_use_me_rb_hi_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_use_me_rb_hi_offset), + scout => sov(ex1_use_me_rb_hi_offset), + din => dec_alu_rf1_use_me_rb_hi, + dout => ex1_use_me_rb_hi_q); +ex1_use_me_rb_lo_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_use_me_rb_lo_offset), + scout => sov(ex1_use_me_rb_lo_offset), + din => dec_alu_rf1_use_me_rb_lo, + dout => ex1_use_me_rb_lo_q); +ex1_use_mb_rb_hi_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_use_mb_rb_hi_offset), + scout => sov(ex1_use_mb_rb_hi_offset), + din => dec_alu_rf1_use_mb_rb_hi, + dout => ex1_use_mb_rb_hi_q); +ex1_use_mb_rb_lo_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_use_mb_rb_lo_offset), + scout => sov(ex1_use_mb_rb_lo_offset), + din => dec_alu_rf1_use_mb_rb_lo, + dout => ex1_use_mb_rb_lo_q); +ex1_use_me_ins_hi_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_use_me_ins_hi_offset), + scout => sov(ex1_use_me_ins_hi_offset), + din => dec_alu_rf1_use_me_ins_hi, + dout => ex1_use_me_ins_hi_q); +ex1_use_me_ins_lo_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_use_me_ins_lo_offset), + scout => sov(ex1_use_me_ins_lo_offset), + din => dec_alu_rf1_use_me_ins_lo, + dout => ex1_use_me_ins_lo_q); +ex1_use_mb_ins_hi_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_use_mb_ins_hi_offset), + scout => sov(ex1_use_mb_ins_hi_offset), + din => dec_alu_rf1_use_mb_ins_hi, + dout => ex1_use_mb_ins_hi_q); +ex1_use_mb_ins_lo_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_use_mb_ins_lo_offset), + scout => sov(ex1_use_mb_ins_lo_offset), + din => dec_alu_rf1_use_mb_ins_lo, + dout => ex1_use_mb_ins_lo_q); +ex1_mb_gt_me_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_mb_gt_me_offset), + scout => sov(ex1_mb_gt_me_offset), + din => dec_alu_rf1_mb_gt_me, + dout => ex1_mb_gt_me_q); +ex1_cmp_byte_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_cmp_byte_offset), + scout => sov(ex1_cmp_byte_offset), + din => dec_alu_rf1_cmp_byt, + dout => ex1_cmp_byte_q); +ex1_sgnxtd_byte_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_sgnxtd_byte_offset), + scout => sov(ex1_sgnxtd_byte_offset), + din => dec_alu_rf1_sgnxtd_byte, + dout => ex1_sgnxtd_byte_q); +ex1_sgnxtd_half_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_sgnxtd_half_offset), + scout => sov(ex1_sgnxtd_half_offset), + din => dec_alu_rf1_sgnxtd_half, + dout => ex1_sgnxtd_half_q); +ex1_sgnxtd_wd_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_sgnxtd_wd_offset), + scout => sov(ex1_sgnxtd_wd_offset), + din => dec_alu_rf1_sgnxtd_wd, + dout => ex1_sgnxtd_wd_q); +ex1_sra_wd_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_sra_wd_offset), + scout => sov(ex1_sra_wd_offset), + din => dec_alu_rf1_sra_wd, + dout => ex1_sra_wd_q); +ex1_sra_dw_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_sra_dw_offset), + scout => sov(ex1_sra_dw_offset), + din => dec_alu_rf1_sra_dw, + dout => ex1_sra_dw_q); +ex1_log_fcn_latch : tri_rlmreg_p + generic map (width => ex1_log_fcn_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_log_fcn_offset to ex1_log_fcn_offset + ex1_log_fcn_q'length-1), + scout => sov(ex1_log_fcn_offset to ex1_log_fcn_offset + ex1_log_fcn_q'length-1), + din => rf1_log_fcn, + dout => ex1_log_fcn_q); +ex1_sel_rot_log_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_sel_rot_log_offset), + scout => sov(ex1_sel_rot_log_offset), + din => dec_alu_rf1_sel_rot_log, + dout => ex1_sel_rot_log_q); +ex2_sh_word_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_sh_word_offset), + scout => sov(ex2_sh_word_offset), + din => ex1_sh_word_q(1), + dout => ex2_sh_word_q); +--------------------------------------------------------------------- +-- Placed Latches +--------------------------------------------------------------------- +ex2_mrg_lcb: entity tri.tri_lcbnd(tri_lcbnd) + port map(vd => vdd, + gd => gnd, + act => ex1_act_unqiue, + nclk => nclk, + forcee => func_sl_force, + thold_b => func_sl_thold_0_b, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + sg => sg_0, + lclk => rot_lclk_int, + d1clk => rot_d1clk_int, + d2clk => rot_d2clk_int); + +rot_lat : entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width => ex2_rotate_b_q'length, expand_type => expand_type, btr => "NLI0001_X1_A12TH", init=>(ex2_rotate_b_q'range=>'0')) + port map (vd => vdd, gd => gnd, + LCLK => rot_lclk_int, + D1CLK => rot_d1clk_int, + D2CLK => rot_d2clk_int, + SCANIN => siv(ex2_rotate_b_offset to ex2_rotate_b_offset + ex2_rotate_b_q'length-1), + SCANOUT => sov(ex2_rotate_b_offset to ex2_rotate_b_offset + ex2_rotate_b_q'length-1), + D => ex1_rotate, + QB => ex2_rotate_b_q); +res_lat : entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width => ex2_result_b_q'length, expand_type => expand_type, btr => "NLI0001_X2_A12TH", init=>(ex2_result_b_q'range=>'0')) + port map (vd => vdd, gd => gnd, + LCLK => rot_lclk_int, + D1CLK => rot_d1clk_int, + D2CLK => rot_d2clk_int, + SCANIN => siv(ex2_result_b_offset to ex2_result_b_offset + ex2_result_b_q'length-1), + SCANOUT => sov(ex2_result_b_offset to ex2_result_b_offset + ex2_result_b_q'length-1), + D => ex1_result, + QB => ex2_result_b_q); +msk_lat : entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width => ex2_mask_b_q'length, expand_type => expand_type, btr => "NLI0001_X1_A12TH", init=>(ex2_mask_b_q'range=>'0')) + port map (vd => vdd, gd => gnd, + LCLK => rot_lclk_int, + D1CLK => rot_d1clk_int, + D2CLK => rot_d2clk_int, + SCANIN => siv(ex2_mask_b_offset to ex2_mask_b_offset + ex2_mask_b_q'length-1), + SCANOUT => sov(ex2_mask_b_offset to ex2_mask_b_offset + ex2_mask_b_q'length-1), + D => ex1_mask, + QB => ex2_mask_b_q); +--------------------------------------------------------------------- +-- End Placed Latches +--------------------------------------------------------------------- +ex2_sra_se_latch : entity tri.tri_inv_nlats_wlcb(tri_inv_nlats_wlcb) + generic map (width => ex2_sra_se_q'length, init => 0, expand_type => expand_type, needs_sreset => 1, btr => "NLI0001_X1_A12TH") + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_sra_se_offset to ex2_sra_se_offset + ex2_sra_se_q'length-1), + scout => sov(ex2_sra_se_offset to ex2_sra_se_offset + ex2_sra_se_q'length-1), + D => ex1_sra_se_b, + QB => ex2_sra_se_q); + +dummy_latch : tri_rlmreg_p + generic map (width => dummy_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tidn, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dummy_offset to dummy_offset + dummy_q'length-1), + scout => sov(dummy_offset to dummy_offset + dummy_q'length-1), + din => dummy_q, + dout => dummy_q); + +siv(0 to scan_right-1) <= sov(1 to scan_right-1) & scan_in; +scan_out <= sov(0); + + +end architecture xuq_alu_mrg; diff --git a/rel/src/vhdl/work/xuq_alu_mult.vhdl b/rel/src/vhdl/work/xuq_alu_mult.vhdl new file mode 100644 index 0000000..88410ee --- /dev/null +++ b/rel/src/vhdl/work/xuq_alu_mult.vhdl @@ -0,0 +1,1582 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XU Multiplier Top +-- + +LIBRARY ieee; USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY ibm; + USE ibm.std_ulogic_support.all; + USE ibm.std_ulogic_unsigned.all; + USE ibm.std_ulogic_function_support.all; +LIBRARY support; + USE support.power_logic_pkg.all; +LIBRARY tri; USE tri.tri_latches_pkg.all; +LIBRARY work; USE work.xuq_pkg.all; + +entity xuq_alu_mult is + generic ( + expand_type : integer := 2; + regmode : integer := 6; + a2mode : integer := 1; + threads : integer := 4; + fxu_synth : integer := 0); + port ( + --------------------------------------------------------------------- + -- Clocks & Power + --------------------------------------------------------------------- + nclk : in clk_logic; + vdd : inout power_logic; + gnd : inout power_logic; + + --------------------------------------------------------------------- + -- Pervasive + --------------------------------------------------------------------- + d_mode_dc : in std_ulogic; + delay_lclkr_dc : in std_ulogic; + mpw1_dc_b : in std_ulogic; + mpw2_dc_b : in std_ulogic; + func_sl_force : in std_ulogic; + func_sl_thold_0_b : in std_ulogic; + sg_0 : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + --------------------------------------------------------------------- + -- Interface with Decode + --------------------------------------------------------------------- + dec_alu_rf1_mul_recform : in std_ulogic; + dec_alu_rf1_mul_val : in std_ulogic; + dec_alu_rf1_mul_ret : in std_ulogic; -- 0: Return low word/dword, 1: Return high word/dword + dec_alu_rf1_mul_sign : in std_ulogic; -- 0: Unsigned, 1: Signed + dec_alu_rf1_mul_size : in std_ulogic; -- 0: 32x32, 1: 64x64 + dec_alu_rf1_mul_imm : in std_ulogic; -- 0: Normal 1: Multiplier is 16 bit S.E. immediate + dec_alu_rf1_xer_ov_update : in std_ulogic; + fxa_fxb_ex1_hold_ctr_flush : in std_ulogic; + + --------------------------------------------------------------------- + -- Interface with SPR + --------------------------------------------------------------------- + ex4_spr_msr_cm : in std_ulogic; + + --------------------------------------------------------------------- + -- Interface with Bypass + --------------------------------------------------------------------- + byp_alu_ex1_mulsrc_0 : in std_ulogic_vector(0 to 2**regmode-1); + byp_alu_ex1_mulsrc_1 : in std_ulogic_vector(0 to 2**regmode-1); + alu_byp_ex5_xer_mul : out std_ulogic_vector(0 to 3); + alu_byp_ex5_cr_mul : out std_ulogic_vector(0 to 4); + + --------------------------------------------------------------------- + -- Interface with Mux + --------------------------------------------------------------------- + alu_byp_ex5_mul_rt : out std_ulogic_vector(0 to 2**regmode-1); + + --------------------------------------------------------------------- + -- Multi-drop + --------------------------------------------------------------------- + alu_ex3_mul_done : out std_ulogic; + alu_ex4_mul_done : out std_ulogic + ); + -- synopsys translate_off + -- synopsys translate_on +end xuq_alu_mult; + +architecture xuq_alu_mult of xuq_alu_mult is + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + subtype s2 is std_ulogic_vector(0 to 1); + subtype s4 is std_ulogic_vector(0 to 3); + subtype s5 is std_ulogic_vector(0 to 4); + subtype s6 is std_ulogic_vector(0 to 5); + + signal ex1_mulstage, ex1_mulstage_shift : std_ulogic_vector(0 to 3); + signal ex1_mul_val : std_ulogic; + signal ex2_ready_stage : std_ulogic_vector(0 to 3); + signal ex5_cmp0_eq : std_ulogic; + signal ex5_cmp0_gt : std_ulogic; + signal ex5_cmp0_lt : std_ulogic; + signal ex5_mul_cr_valid : std_ulogic; + signal ex5_xer_ov : std_ulogic; + signal ex3_recycle_s : std_ulogic_vector(196 to 264); + signal ex3_recycle_c : std_ulogic_vector(196 to 264); + signal ex4_pp5_0s : std_ulogic_vector(196 to 264); + signal ex4_pp5_0c : std_ulogic_vector(196 to 264); + signal ex3_recyc_sh00 : std_ulogic; + signal ex3_recyc_sh32 : std_ulogic; + signal ex3_xtd : std_ulogic; + signal ex3_xtd_196_or : std_ulogic; + signal ex3_xtd_196_and : std_ulogic; + signal ex3_xtd_197_or : std_ulogic; + signal ex3_xtd_197_and : std_ulogic; + signal ex3_xtd_ge1 : std_ulogic; + signal ex3_xtd_ge2 : std_ulogic; + signal ex3_xtd_ge3 : std_ulogic; + signal ex1_bs_sign : std_ulogic; + signal ex1_bd_sign : std_ulogic; + signal ex4_xi : std_ulogic_vector(0 to 63); + signal ex4_yi : std_ulogic_vector(0 to 63); + signal ex4_p : std_ulogic_vector(0 to 63); + signal ex4_g : std_ulogic_vector(1 to 63); + signal ex4_t : std_ulogic_vector(1 to 63); + signal ex4_res : std_ulogic_vector(0 to 63); + signal rslt_lo_act : std_ulogic; + signal ex4_ret_mulhw : std_ulogic; + signal ex4_ret_mullw : std_ulogic; + signal ex4_ret_mulli : std_ulogic; + signal ex4_ret_mulld : std_ulogic; + signal ex4_ret_mulldo : std_ulogic; + signal ex4_ret_mulhd : std_ulogic; + + signal ex5_result : std_ulogic_vector(0 to 63); + signal ex4_all0_test : std_ulogic_vector(0 to 63); + signal ex4_all0_test_mid : std_ulogic; + signal ex4_all1_test : std_ulogic_vector(0 to 63); + signal ex4_all1_test_mid : std_ulogic; + signal ex4_all0 : std_ulogic; + signal ex4_all1 : std_ulogic; + signal ex4_all0_lo : std_ulogic; + signal ex4_all0_hi : std_ulogic; + signal ex4_all1_hi : std_ulogic; + signal ex5_sign_rt_cmp0 : std_ulogic; + signal ex5_eq : std_ulogic; + signal ex4_cout_32 : std_ulogic; + signal ex4_xi_b : std_ulogic_vector(0 to 63); + signal ex4_yi_b : std_ulogic_vector(0 to 63); + signal ex1_mulsrc0_act, ex1_mulsrc1_act : std_ulogic; + signal ex2_bs_lo, ex2_bd_lo : std_ulogic_vector(32 to 63); + signal ex2_act, ex3_act, ex4_act : std_ulogic; + + -- Latch Signals + signal ex1_mul_val_q : std_ulogic; -- Valid multiply op + signal ex2_mulstage_q : std_ulogic_vector(0 to 3); -- Stage of multiplication + signal ex3_mulstage_q : std_ulogic_vector(0 to 3); + signal ex4_mulstage_q : std_ulogic_vector(0 to 3); + signal ex5_mulstage_q : std_ulogic_vector(0 to 3); + signal ex1_is_recform_q : std_ulogic; -- Multiply is a record form + signal ex2_is_recform_q : std_ulogic; + signal ex3_is_recform_q : std_ulogic; + signal ex4_is_recform_q : std_ulogic; + signal ex5_is_recform_q : std_ulogic; + signal ex1_retsel_q, ex1_retsel_d : std_ulogic_vector(0 to 2); -- Select which data to return + signal ex2_retsel_q : std_ulogic_vector(0 to 2); + signal ex3_retsel_q : std_ulogic_vector(0 to 2); + signal ex4_retsel_q : std_ulogic_vector(0 to 2); + signal ex1_mul_size_q : std_ulogic; + signal ex1_mul_sign_q : std_ulogic; + signal ex3_mul_done_q, ex3_mul_done_d : std_ulogic; -- Multiply result is done + signal ex4_mul_done_q : std_ulogic; + signal ex5_mul_done_q : std_ulogic; + signal ex1_xer_ov_update_q : std_ulogic; -- Update XER[OV] + signal ex2_xer_ov_update_q : std_ulogic; + signal ex3_xer_ov_update_q : std_ulogic; + signal ex4_xer_ov_update_q : std_ulogic; + signal ex5_xer_ov_update_q : std_ulogic; + signal ex2_bs_lo_sign_q, ex2_bs_lo_sign_d : std_ulogic; -- Sign of operands + signal ex2_bd_lo_sign_q, ex2_bd_lo_sign_d : std_ulogic; + signal ex4_ci_q, ex4_ci_d : std_ulogic; + signal ex5_res_q : std_ulogic_vector(0 to 63); + signal ex5_all0_q : std_ulogic; -- Check different pieces of result for ovf/cr + signal ex5_all1_q : std_ulogic; + signal ex5_all0_lo_q : std_ulogic; + signal ex5_all0_hi_q : std_ulogic; + signal ex5_all1_hi_q : std_ulogic; + signal carry_32_dly1_q : std_ulogic; -- Delayed carry bit for adder + signal all0_lo_dly1_q : std_ulogic; -- Delay low all 0 + signal all0_lo_dly2_q : std_ulogic; + signal all0_lo_dly3_q : std_ulogic; + signal rslt_lo_q, rslt_lo_d : std_ulogic_vector(0 to 31); -- Result holding latches + signal rslt_lo_dly_q, rslt_lo_dly_d : std_ulogic_vector(0 to 31); -- delay low half of result for mulldo + signal ex2_mulsrc_0_q, ex1_mulsrc_0 : std_ulogic_vector(0 to 63); + signal ex2_mulsrc_1_q, ex1_mulsrc_1 : std_ulogic_vector(0 to 63); + signal ex5_rslt_hw_q, ex5_rslt_hw_d : std_ulogic_vector(0 to 7); + signal ex5_rslt_ld_li_q, ex5_rslt_ld_li_d : std_ulogic_vector(0 to 7); + signal ex5_rslt_ldo_q, ex5_rslt_ldo_d : std_ulogic_vector(0 to 7); + signal ex5_rslt_lw_hd_q, ex5_rslt_lw_hd_d : std_ulogic_vector(0 to 7); + signal ex5_cmp0_sel_reshi_q, ex5_cmp0_sel_reshi_d : std_ulogic; + signal ex5_cmp0_sel_reslo_q, ex5_cmp0_sel_reslo_d : std_ulogic; + signal ex5_cmp0_sel_reslodly_q, ex5_cmp0_sel_reslodly_d : std_ulogic; + signal ex5_cmp0_sel_reslodly2_q, ex5_cmp0_sel_reslodly2_d : std_ulogic; + signal ex5_eq_sel_all0_b_q, ex5_eq_sel_all0_b_d : std_ulogic; + signal ex5_eq_sel_all0_hi_b_q, ex5_eq_sel_all0_hi_b_d : std_ulogic; + signal ex5_eq_sel_all0_lo_b_q, ex5_eq_sel_all0_lo_b_d : std_ulogic; + signal ex5_eq_sel_all0_lo1_b_q, ex5_eq_sel_all0_lo1_b_d : std_ulogic; + signal ex5_eq_sel_all0_lo2_b_q, ex5_eq_sel_all0_lo2_b_d : std_ulogic; + signal ex5_eq_sel_all0_lo3_b_q, ex5_eq_sel_all0_lo3_b_d : std_ulogic; + signal ex5_ret_mullw_q : std_ulogic; + signal ex5_ret_mulldo_q : std_ulogic; + signal ex5_cmp0_undef_q, ex5_cmp0_undef_d : std_ulogic; + -- Scanchain + constant ex1_mul_val_offset : integer := 1; + constant ex2_mulstage_offset : integer := ex1_mul_val_offset + 1; + constant ex3_mulstage_offset : integer := ex2_mulstage_offset + ex2_mulstage_q'length; + constant ex4_mulstage_offset : integer := ex3_mulstage_offset + ex3_mulstage_q'length; + constant ex5_mulstage_offset : integer := ex4_mulstage_offset + ex4_mulstage_q'length; + constant ex1_retsel_offset : integer := ex5_mulstage_offset + ex5_mulstage_q'length; + constant ex2_retsel_offset : integer := ex1_retsel_offset + ex1_retsel_q'length; + constant ex3_retsel_offset : integer := ex2_retsel_offset + ex2_retsel_q'length; + constant ex4_retsel_offset : integer := ex3_retsel_offset + ex3_retsel_q'length; + constant ex3_mul_done_offset : integer := ex4_retsel_offset + ex4_retsel_q'length; + constant ex4_mul_done_offset : integer := ex3_mul_done_offset + 1; + constant ex5_mul_done_offset : integer := ex4_mul_done_offset + 1; + constant ex1_is_recform_offset : integer := ex5_mul_done_offset + 1; + constant ex2_is_recform_offset : integer := ex1_is_recform_offset + 1; + constant ex3_is_recform_offset : integer := ex2_is_recform_offset + 1; + constant ex4_is_recform_offset : integer := ex3_is_recform_offset + 1; + constant ex5_is_recform_offset : integer := ex4_is_recform_offset + 1; + constant ex1_xer_ov_update_offset : integer := ex5_is_recform_offset + 1; + constant ex2_xer_ov_update_offset : integer := ex1_xer_ov_update_offset + 1; + constant ex3_xer_ov_update_offset : integer := ex2_xer_ov_update_offset + 1; + constant ex4_xer_ov_update_offset : integer := ex3_xer_ov_update_offset + 1; + constant ex5_xer_ov_update_offset : integer := ex4_xer_ov_update_offset + 1; + constant ex1_mul_size_offset : integer := ex5_xer_ov_update_offset + 1; + constant ex1_mul_sign_offset : integer := ex1_mul_size_offset + 1; + constant ex2_bs_lo_sign_offset : integer := ex1_mul_sign_offset + 1; + constant ex2_bd_lo_sign_offset : integer := ex2_bs_lo_sign_offset + 1; + constant ex5_all0_offset : integer := ex2_bd_lo_sign_offset + 1; + constant ex5_all1_offset : integer := ex5_all0_offset + 1; + constant ex5_all0_lo_offset : integer := ex5_all1_offset + 1; + constant ex5_all0_hi_offset : integer := ex5_all0_lo_offset + 1; + constant ex5_all1_hi_offset : integer := ex5_all0_hi_offset + 1; + constant ex4_ci_offset : integer := ex5_all1_hi_offset + 1; + constant ex5_res_offset : integer := ex4_ci_offset + 1; + constant carry_32_dly1_offset : integer := ex5_res_offset + ex5_res_q'length; + constant all0_lo_dly1_offset : integer := carry_32_dly1_offset + 1; + constant all0_lo_dly2_offset : integer := all0_lo_dly1_offset + 1; + constant all0_lo_dly3_offset : integer := all0_lo_dly2_offset + 1; + constant rslt_lo_offset : integer := all0_lo_dly3_offset + 1; + constant rslt_lo_dly_offset : integer := rslt_lo_offset + rslt_lo_q'length; + constant ex2_mulsrc_0_offset : integer := rslt_lo_dly_offset + rslt_lo_dly_q'length; + constant ex2_mulsrc_1_offset : integer := ex2_mulsrc_0_offset + ex2_mulsrc_0_q'length; + constant ex5_rslt_hw_offset : integer := ex2_mulsrc_1_offset + ex2_mulsrc_1_q'length; + constant ex5_rslt_ld_li_offset : integer := ex5_rslt_hw_offset + ex5_rslt_hw_q'length; + constant ex5_rslt_ldo_offset : integer := ex5_rslt_ld_li_offset + ex5_rslt_ld_li_q'length; + constant ex5_rslt_lw_hd_offset : integer := ex5_rslt_ldo_offset + ex5_rslt_ldo_q'length; + constant ex5_cmp0_sel_reshi_offset : integer := ex5_rslt_lw_hd_offset + ex5_rslt_lw_hd_q'length; + constant ex5_cmp0_sel_reslo_offset : integer := ex5_cmp0_sel_reshi_offset + 1; + constant ex5_cmp0_sel_reslodly_offset : integer := ex5_cmp0_sel_reslo_offset + 1; + constant ex5_cmp0_sel_reslodly2_offset : integer := ex5_cmp0_sel_reslodly_offset + 1; + constant ex5_eq_sel_all0_b_offset : integer := ex5_cmp0_sel_reslodly2_offset + 1; + constant ex5_eq_sel_all0_hi_b_offset : integer := ex5_eq_sel_all0_b_offset + 1; + constant ex5_eq_sel_all0_lo_b_offset : integer := ex5_eq_sel_all0_hi_b_offset + 1; + constant ex5_eq_sel_all0_lo1_b_offset : integer := ex5_eq_sel_all0_lo_b_offset + 1; + constant ex5_eq_sel_all0_lo2_b_offset : integer := ex5_eq_sel_all0_lo1_b_offset + 1; + constant ex5_eq_sel_all0_lo3_b_offset : integer := ex5_eq_sel_all0_lo2_b_offset + 1; + constant ex5_ret_mullw_offset : integer := ex5_eq_sel_all0_lo3_b_offset + 1; + constant ex5_ret_mulldo_offset : integer := ex5_ret_mullw_offset + 1; + constant ex5_cmp0_undef_offset : integer := ex5_ret_mulldo_offset + 1; + constant scan_right : integer := ex5_cmp0_undef_offset + 1; + + signal siv : std_ulogic_vector(0 to scan_right-1); + signal sov : std_ulogic_vector(0 to scan_right-1); + +begin + + --------------------------------------------------------------------- + -- Other signals + --------------------------------------------------------------------- + ex1_retsel_d <= dec_alu_rf1_mul_ret & dec_alu_rf1_mul_size & dec_alu_rf1_mul_imm; + ex5_mul_cr_valid <= ex5_is_recform_q and ex5_mul_done_q; + + --------------------------------------------------------------------- + -- Multiply Stage Counter + --------------------------------------------------------------------- + ex1_mul_val <= ex1_mul_val_q and not fxa_fxb_ex1_hold_ctr_flush; + ex1_mulstage_shift <= tidn & gate(ex2_mulstage_q(0 to 2),not(fxa_fxb_ex1_hold_ctr_flush)); + +mult_64b_stagecnt : if regmode = 6 generate + with ex1_mul_val select + ex1_mulstage <= "1000" when '1', + ex1_mulstage_shift when others; +end generate; +mult_32b_stagecnt : if regmode = 5 generate + ex1_mulstage <= "0000"; +end generate; + + + ------------------------------------------------------------------------------------------------------------------------------------------ + ------------------------------------------------------------------------------------------------------------------------------------------ + -- NEW MULTIPLIER ------------------------------------------------------------------------------------------------------------------------ + ------------------------------------------------------------------------------------------------------------------------------------------ + ------------------------------------------------------------------------------------------------------------------------------------------ + + --------------------------------------------------------------------- + -- Signs + --------------------------------------------------------------------- + + + ex2_bs_lo_sign_d <= ((ex1_bs_sign and ex1_mul_sign_q and (ex1_mulstage(1) or ex1_mulstage(3))) and ex1_mul_size_q ) or + ( ex1_bs_sign and ex1_mul_sign_q and not ex1_mul_size_q ) or + ( ex1_bs_sign and ex1_mul_sign_q and ex1_mulstage(1) and ex1_retsel_q(2)); + ex2_bd_lo_sign_d <= ((ex1_bd_sign and ex1_mul_sign_q and (ex1_mulstage(2) or ex1_mulstage(3))) and ex1_mul_size_q ) or + ( ex1_bd_sign and ex1_mul_sign_q and not ex1_mul_size_q ) or + ( ex1_bd_sign and ex1_mul_sign_q and ex1_retsel_q(2)); + + --------------------------------------------------------------------- + -- Operands + --------------------------------------------------------------------- + ex1_mulsrc0_act <= or_reduce(ex1_mulstage); + ex1_mulsrc1_act <= ex1_mulstage(0) or ex1_mulstage(2); + + with ex1_mul_val_q select + ex1_mulsrc_0(0 to 63) <= byp_alu_ex1_mulsrc_0(0 to 63) when '1', + ex2_mulsrc_0_q(32 to 63) & ex2_mulsrc_0_q(0 to 31) when others; + + + with ex1_mul_val_q select + ex1_mulsrc_1(0 to 63) <= byp_alu_ex1_mulsrc_1(0 to 63) when '1', + ex2_mulsrc_1_q(32 to 63) & ex2_mulsrc_1_q(0 to 31) when others; + + -- Use the saved value for bd_sign when mulsrc1 is clock gated + with (ex1_mulstage(1) or ex1_mulstage(3)) select + ex1_bd_sign <= ex2_mulsrc_1_q(32) when '1', + ex1_mulsrc_1(32) when others; + + + ex1_bs_sign <= ex1_mulsrc_0(32); + ex2_bs_lo <= ex2_mulsrc_0_q(32 to 63); + ex2_bd_lo <= ex2_mulsrc_1_q(32 to 63); + + --------------------------------------------------------------------- + -- Multiply Core + --------------------------------------------------------------------- + mcore : entity work.xuq_alu_mult_core(xuq_alu_mult_core) + generic map (expand_type => expand_type) + port map ( + nclk => nclk, + vdd => vdd, + gnd => gnd, + delay_lclkr_dc => delay_lclkr_dc, + mpw1_dc_b => mpw1_dc_b, + mpw2_dc_b => mpw2_dc_b, + func_sl_force => func_sl_force, + func_sl_thold_0_b => func_sl_thold_0_b, + sg_0 => sg_0, + scan_in => siv(0), + scan_out => sov(0), + ex2_act => ex2_act, + ex3_act => ex3_act, + ex2_bs_lo_sign => ex2_bs_lo_sign_q, + ex2_bd_lo_sign => ex2_bd_lo_sign_q, + ex2_bs_lo => ex2_bs_lo, + ex2_bd_lo => ex2_bd_lo, + ex3_recycle_s => ex3_recycle_s(196 to 264), + ex3_recycle_c => ex3_recycle_c(196 to 263), + ex4_pp5_0s_out => ex4_pp5_0s, + ex4_pp5_0c_out => ex4_pp5_0c(196 to 263)); + + ex4_pp5_0c(264) <= tidn; + + ex2_act <= or_reduce(ex2_mulstage_q); + ex3_act <= or_reduce(ex3_mulstage_q); + ex4_act <= or_reduce(ex4_mulstage_q); + + --------------------------------------------------------------------- + -- Carry In + --------------------------------------------------------------------- + -- |---------|---------| + -- |---------|---------| dly <--/ * for mulli + -- |---------|---------| dly1 <-/ * for mulld + -- |---------|---------| dly <--/ * for mulhd + + ex4_ci_d <= (carry_32_dly1_q and ex3_mulstage_q(2) ) or -- feedback from previous previous add + (ex4_cout_32 and ((ex3_mulstage_q(3) and ex3_retsel_q(1)) or + (ex3_mulstage_q(1) and ex3_retsel_q(2))) ); + + --------------------------------------------------------------------- + -- Adder (ripple carry for simulation, replace with carry look ahead + --------------------------------------------------------------------- + ex4_xi <= ex4_pp5_0s(200 to 263); + ex4_yi <= ex4_pp5_0c(200 to 263); + + ex4_p <= ex4_xi(0 to 63) xor ex4_yi(0 to 63); + ex4_g <= ex4_xi(1 to 63) and ex4_yi(1 to 63); + ex4_t <= ex4_xi(1 to 63) or ex4_yi(1 to 63); + + ex4_xi_b(0 to 63) <= not ex4_xi(0 to 63) ; + ex4_yi_b(0 to 63) <= not ex4_yi(0 to 63) ; + + cla64ci: entity work.xuq_add(xuq_add) + port map( + x_b(0 to 63) => ex4_xi_b(0 to 63), + y_b(0 to 63) => ex4_yi_b(0 to 63), + ci(8) => ex4_ci_q, + sum(0 to 63) => ex4_res(0 to 63), + cout_32 => ex4_cout_32, + cout_0 => open); + + --------------------------------------------------------------------- + -- Determine Recirculation + --------------------------------------------------------------------- + -- Shift amount + ex3_recyc_sh32 <= ex3_retsel_q(1) and (ex3_mulstage_q(1) or ex3_mulstage_q(3)); + ex3_recyc_sh00 <= ex3_retsel_q(1) and (ex3_mulstage_q(2)) ; + + -- Get rid of "bogus" bit + ex3_xtd_196_or <= ex4_pp5_0s(196) or ex4_pp5_0c(196); + ex3_xtd_196_and <= ex4_pp5_0s(196) and ex4_pp5_0c(196); + ex3_xtd_197_or <= ex4_pp5_0s(197) or ex4_pp5_0c(197); + ex3_xtd_197_and <= ex4_pp5_0s(197) and ex4_pp5_0c(197); + + ex3_xtd_ge1 <= ex3_xtd_196_or or ex3_xtd_197_or; + ex3_xtd_ge2 <= ex3_xtd_196_or or ex3_xtd_197_and; + ex3_xtd_ge3 <= ex3_xtd_196_and or (ex3_xtd_196_or and ex3_xtd_197_or); + + + ex3_xtd <= (ex3_mulstage_q(1) and ex3_retsel_q(1) and not ex3_xtd_ge1) or + (ex3_mulstage_q(2) and ex3_retsel_q(1) and not ex3_xtd_ge2) or + (ex3_mulstage_q(3) and ex3_retsel_q(1) and not ex3_xtd_ge3) ; + + ex3_recycle_s(196) <= ex4_pp5_0s(196) and (ex3_retsel_q(1) and not ex3_mulstage_q(0)); + ex3_recycle_c(196) <= ex4_pp5_0c(196) and (ex3_retsel_q(1) and not ex3_mulstage_q(0)) ; + + ex3_recycle_s(197) <= ex4_pp5_0s(197) and (ex3_retsel_q(1) and not ex3_mulstage_q(0)) ; + ex3_recycle_c(197) <= ex4_pp5_0c(197) and (ex3_retsel_q(1) and not ex3_mulstage_q(0)) ; + + ex3_recycle_s(198 to 264) <= ( (198 to 264=> ex3_recyc_sh00) and ( ex4_pp5_0s(198 to 264) ) ) or + ( (198 to 264=> ex3_recyc_sh32) and ( (0 to 31=> ex3_xtd) & ex4_pp5_0s(198 to 231) & tidn ) ) ; + + ex3_recycle_c(198 to 264) <= ( (198 to 264=> ex3_recyc_sh00) and ( ex4_pp5_0c(198 to 264) ) ) or + ( (198 to 264=> ex3_recyc_sh32) and ( (0 to 31=> tidn) & ex4_pp5_0c(198 to 231) & tidn ) ) ; + + --------------------------------------------------------------------- + -- Result + --------------------------------------------------------------------- + rslt_lo_act <= ex5_mulstage_q(0) or ex5_mulstage_q(2); + + rslt_lo_d <= ex5_res_q(32 to 63); + rslt_lo_dly_d <= rslt_lo_q; + + -- RETURN RET SIZE IMM OVF READY + -- mulhw (0 to 31 => '0') & ex5_res_q(0 to 31) 1 0 0 . 1000 + -- mullw ex5_res_q 0 0 0 . 1000 + -- mulli ex5_res_q(32 to 63) & rslt_lo_q . . 1 . 0100 + -- mulld ex5_res_q(32 to 63) & rslt_lo_q 0 1 0 0 0010 + -- mulldo rslt_lo_q & rslt_lo_dly_q 0 1 0 1 0001 + -- mulhd ex5_res_q 1 1 0 . 0001 + + ex4_ret_mulhw <= ex4_retsel_q(0) and not ex4_retsel_q(1) and not ex4_retsel_q(2) ; + ex4_ret_mullw <= not ex4_retsel_q(0) and not ex4_retsel_q(1) and not ex4_retsel_q(2) ; + ex4_ret_mulli <= ex4_retsel_q(2) ; + ex4_ret_mulld <= not ex4_retsel_q(0) and ex4_retsel_q(1) and not ex4_retsel_q(2) and not ex4_xer_ov_update_q; + ex4_ret_mulldo <= not ex4_retsel_q(0) and ex4_retsel_q(1) and not ex4_retsel_q(2) and ex4_xer_ov_update_q; + ex4_ret_mulhd <= ex4_retsel_q(0) and ex4_retsel_q(1) and not ex4_retsel_q(2) ; + + ex5_rslt_hw_d <= (others=>(ex4_ret_mulhw )); + ex5_rslt_ld_li_d <= (others=>(ex4_ret_mulli or ex4_ret_mulld)); + ex5_rslt_ldo_d <= (others=>(ex4_ret_mulldo )); + ex5_rslt_lw_hd_d <= (others=>(ex4_ret_mullw or ex4_ret_mulhd)); + + ex5_result <= (((0 to 31 => '0') & ex5_res_q(0 to 31)) and fanout(ex5_rslt_hw_q ,64)) or + ((ex5_res_q(32 to 63) & rslt_lo_q ) and fanout(ex5_rslt_ld_li_q,64)) or + ((rslt_lo_q & rslt_lo_dly_q ) and fanout(ex5_rslt_ldo_q ,64)) or + ((ex5_res_q ) and fanout(ex5_rslt_lw_hd_q,64)); + + --------------------------------------------------------------------- + -- Overflow + --------------------------------------------------------------------- + ex4_all0_test(0 to 62) <= ( not ex4_p(0 to 62) and not ex4_t(1 to 63) ) or + ( ex4_p(0 to 62) and ex4_t(1 to 63) ) ; + ex4_all0_test(63) <= ( not ex4_p(63) and not ex4_ci_q ) or + ( ex4_p(63) and ex4_ci_q ) ; + ex4_all0_test_mid <= ( not ex4_p(31) and not ex4_cout_32 ) or + ( ex4_p(31) and ex4_cout_32 ) ; + + ex4_all1_test(0 to 62) <= ( ex4_p(0 to 62) and not ex4_g(1 to 63) ) or + ( not ex4_p(0 to 62) and ex4_g(1 to 63) ); + ex4_all1_test(63) <= ( ex4_p(63) and not ex4_ci_q ) or + ( not ex4_p(63) and ex4_ci_q ); + ex4_all1_test_mid <= ( ex4_p(31) and not ex4_cout_32 ) or + ( not ex4_p(31) and ex4_cout_32 ); + + ex4_all0 <= and_reduce( ex4_all0_test(0 to 63) ); + ex4_all1 <= and_reduce( ex4_all1_test(0 to 63) ); + ex4_all0_lo <= and_reduce( ex4_all0_test(32 to 63) ); + ex4_all0_hi <= and_reduce( ex4_all0_test(0 to 30) & ex4_all0_test_mid ); + ex4_all1_hi <= and_reduce( ex4_all1_test(0 to 30) & ex4_all1_test_mid ); + + + -- What sign bit to use for compare to zero? + -- + -- | CM = 1 (64b) | CM = 0 (32b) | + -- hw | '0' | ex5_res_q(0) | <- 64b case is undefined ,return zero + -- lw | ex5_res_q(0) | ex5_res_q(32) | + -- hd | ex5_res_q(0) | ex5_res_q(32) | + -- ld | ex5_res_q(32) | rslt_lo_q(0) | + -- ldo | rslt_lo_q(0) | rslt_lo_dly_q(0) | + + -- (ex5_res_q(0) and (ex5_ret_mullw or ex5_ret_mulhd or ex5_ret_mulhw) and ex5_spr_msr_cm_q) or + -- (ex5_res_q(0) and ex5_ret_mulhw ) or + -- (ex5_res_q(32) and (ex5_ret_mullw or ex5_ret_mulhd or ex5_ret_mulhw) and not ex5_spr_msr_cm_q) or + -- (ex5_res_q(32) and ex5_ret_mulld and ex5_spr_msr_cm_q) or + -- (rslt_lo_q(0) and ex5_ret_mulld and not ex5_spr_msr_cm_q) or + -- (rslt_lo_q(0) and ex5_ret_mulldo and ex5_spr_msr_cm_q) or + -- (rslt_lo_dly_q(0) and ex5_ret_mulldo and not ex5_spr_msr_cm_q); + + ex5_cmp0_undef_d <= ex4_ret_mulhw and ex4_spr_msr_cm; + + ex5_cmp0_sel_reshi_d <= ( ex4_ret_mulhw ) or + ((ex4_ret_mullw or ex4_ret_mulhd) and ex4_spr_msr_cm); + ex5_cmp0_sel_reslo_d <= ((ex4_ret_mullw or ex4_ret_mulhd) and not ex4_spr_msr_cm) or + ( ex4_ret_mulld and ex4_spr_msr_cm); + ex5_cmp0_sel_reslodly_d <= ( ex4_ret_mulld and not ex4_spr_msr_cm) or + ( ex4_ret_mulldo and ex4_spr_msr_cm); + ex5_cmp0_sel_reslodly2_d <= ( ex4_ret_mulldo and not ex4_spr_msr_cm); + + ex5_sign_rt_cmp0 <=(ex5_cmp0_sel_reshi_q and ex5_res_q(0) ) or + (ex5_cmp0_sel_reslo_q and ex5_res_q(32) ) or + (ex5_cmp0_sel_reslodly_q and rslt_lo_q(0) ) or + (ex5_cmp0_sel_reslodly2_q and rslt_lo_dly_q(0) ); + + + -- +-----------------------------+-----------------------------+ + -- | CM = 1 (64b) | CM = 0 (32b) | + -- +-----------------------------+-----------------------------+ + -- lw | all0 | all0_lo + -- hd | all0 | all0 & all0_lo + -- ld | all0_lo & all0_lo_dly2 | all0_lo_dly2 + -- ldo | all0_lo_dly1 & all0_lo_dly3 | all0_lo_dly3 + -- hw | all0_hi | all0_hi <- 64b case is undefined ,return zero + -- +-----------------------------+-----------------------------+ + + -- (ex5_ret_mullw and ex5_all0_q and ex5_spr_msr_cm_q) or + -- (ex5_ret_mullw and ex5_all0_lo_q and not ex5_spr_msr_cm_q) or + -- (ex5_ret_mulhd and ex5_all0_q ) or + -- (ex5_ret_mulhd and ex5_all0_lo_q and not ex5_spr_msr_cm_q) or + -- (ex5_ret_mulld and ex5_all0_lo_q and all0_lo_dly2_q and ex5_spr_msr_cm_q) or + -- (ex5_ret_mulld and all0_lo_dly2_q and not ex5_spr_msr_cm_q) or + -- (ex5_ret_mulldo and all0_lo_dly1_q and all0_lo_dly3_q and ex5_spr_msr_cm_q) or + -- (ex5_ret_mulldo and all0_lo_dly3_q and not ex5_spr_msr_cm_q) or + -- (ex5_ret_mulhw and ex5_all0_hi_q ); + + ex5_eq_sel_all0_hi_b_d <= not( ex4_ret_mulhw ); + + ex5_eq_sel_all0_b_d <= not((ex4_ret_mullw and ex4_spr_msr_cm) or + (ex4_ret_mulhd and ex4_spr_msr_cm)); + + ex5_eq_sel_all0_lo_b_d <= not((ex4_ret_mullw and not ex4_spr_msr_cm) or + (ex4_ret_mulhd and not ex4_spr_msr_cm) or + (ex4_ret_mulld and ex4_spr_msr_cm)); + + ex5_eq_sel_all0_lo1_b_d <= not((ex4_ret_mulldo and ex4_spr_msr_cm)); + + ex5_eq_sel_all0_lo2_b_d <= not( ex4_ret_mulld ); + + ex5_eq_sel_all0_lo3_b_d <= not( ex4_ret_mulldo ); + + + ex5_eq <= (ex5_eq_sel_all0_b_q or ex5_all0_q ) and + (ex5_eq_sel_all0_lo_b_q or ex5_all0_lo_q ) and + (ex5_eq_sel_all0_lo1_b_q or all0_lo_dly1_q) and + (ex5_eq_sel_all0_lo2_b_q or all0_lo_dly2_q) and + (ex5_eq_sel_all0_lo3_b_q or all0_lo_dly3_q) and + (ex5_eq_sel_all0_hi_b_q or ex5_all0_hi_q ); + + ex5_cmp0_eq <= ex5_eq and not ex5_cmp0_undef_q; + ex5_cmp0_gt <= not ex5_sign_rt_cmp0 and not ex5_eq and not ex5_cmp0_undef_q; + ex5_cmp0_lt <= ex5_sign_rt_cmp0 and not ex5_eq and not ex5_cmp0_undef_q; + + -- What sign bit to use for overflow detection? + -- + -- lwo - ex5_res_q(32) + -- ldo - rslt_lo_q(0) + +-- ex5_sign_rt_ov <= (ex5_res_q(32) and ex5_ret_mullw ) or +-- (rslt_lo_q(0) and ex5_ret_mulldo); +-- +-- ex5_xer_ov <= (ex5_ret_mullw and not ex5_sign_rt_ov and not ex5_all0_hi_q) or +-- (ex5_ret_mullw and ex5_sign_rt_ov and not ex5_all1_hi_q) or +-- (ex5_ret_mulldo and not ex5_sign_rt_ov and not ex5_all0_q ) or +-- (ex5_ret_mulldo and ex5_sign_rt_ov and not ex5_all1_q ); + + ex5_xer_ov <= (ex5_ret_mullw_q and ((not ex5_res_q(32) and not ex5_all0_hi_q) or + ( ex5_res_q(32) and not ex5_all1_hi_q))) or + (ex5_ret_mulldo_q and ((not rslt_lo_q(0) and not ex5_all0_q ) or + ( rslt_lo_q(0) and not ex5_all1_q ))); + + + --------------------------------------------------------------------- + -- Return + --------------------------------------------------------------------- + alu_byp_ex5_mul_rt <= ex5_result; + alu_byp_ex5_cr_mul <= ex5_cmp0_lt & ex5_cmp0_gt & ex5_cmp0_eq & (ex5_xer_ov and ex5_xer_ov_update_q) & ex5_mul_cr_valid; + alu_byp_ex5_xer_mul <= ex5_xer_ov & tidn & ex5_xer_ov_update_q & tidn; + + --------------------------------------------------------------------- + -- Assert a signal when the result is ready + --------------------------------------------------------------------- + + -- READY RET SIZE IMM OVERFLOW + -- mulhw 1000 . 0 0 . + -- mullw 1000 . 0 0 . + -- mulli 0100 . . 1 . + -- mulld 0010 0 1 0 0 + -- mulldo 0001 0 1 0 1 + -- mulhd 0001 1 1 0 . + + ex2_ready_stage(0) <= ( not ex2_retsel_q(1) and not ex2_retsel_q(2) ) ; + ex2_ready_stage(1) <= ( ex2_retsel_q(2) ) ; + ex2_ready_stage(2) <= (not ex2_retsel_q(0) and ex2_retsel_q(1) and not ex2_retsel_q(2) and not ex2_xer_ov_update_q) ; + ex2_ready_stage(3) <= (not ex2_retsel_q(0) and ex2_retsel_q(1) and not ex2_retsel_q(2) and ex2_xer_ov_update_q) or + ( ex2_retsel_q(0) and ex2_retsel_q(1) and not ex2_retsel_q(2) ) ; + + + ex3_mul_done_d <= or_reduce(ex2_ready_stage and ex2_mulstage_q); + + alu_ex3_mul_done <= ex3_mul_done_q; + alu_ex4_mul_done <= ex4_mul_done_q; + + + ------------------------------------------------------------------------------------------------------------------------------------------ + ------------------------------------------------------------------------------------------------------------------------------------------ + ------------------------------------------------------------------------------------------------------------------------------------------ + ------------------------------------------------------------------------------------------------------------------------------------------ + ------------------------------------------------------------------------------------------------------------------------------------------ + mark_unused(ex3_recycle_c(264)); + mark_unused(ex5_mulstage_q(1)); + mark_unused(ex5_mulstage_q(3)); + + --------------------------------------------------------------------- + -- Latch Instances + --------------------------------------------------------------------- + ex1_mul_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_mul_val_offset), + scout => sov(ex1_mul_val_offset), + din => dec_alu_rf1_mul_val, + dout => ex1_mul_val_q); + ex2_mulstage_latch : tri_rlmreg_p + generic map (width => ex2_mulstage_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_mulstage_offset to ex2_mulstage_offset + ex2_mulstage_q'length-1), + scout => sov(ex2_mulstage_offset to ex2_mulstage_offset + ex2_mulstage_q'length-1), + din => ex1_mulstage, + dout => ex2_mulstage_q); + ex3_mulstage_latch : tri_rlmreg_p + generic map (width => ex3_mulstage_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_mulstage_offset to ex3_mulstage_offset + ex3_mulstage_q'length-1), + scout => sov(ex3_mulstage_offset to ex3_mulstage_offset + ex3_mulstage_q'length-1), + din => ex2_mulstage_q, + dout => ex3_mulstage_q); + ex4_mulstage_latch : tri_rlmreg_p + generic map (width => ex4_mulstage_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_mulstage_offset to ex4_mulstage_offset + ex4_mulstage_q'length-1), + scout => sov(ex4_mulstage_offset to ex4_mulstage_offset + ex4_mulstage_q'length-1), + din => ex3_mulstage_q, + dout => ex4_mulstage_q); + ex5_mulstage_latch : tri_rlmreg_p + generic map (width => ex5_mulstage_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_mulstage_offset to ex5_mulstage_offset + ex5_mulstage_q'length-1), + scout => sov(ex5_mulstage_offset to ex5_mulstage_offset + ex5_mulstage_q'length-1), + din => ex4_mulstage_q, + dout => ex5_mulstage_q); + ex1_retsel_latch : tri_rlmreg_p + generic map (width => ex1_retsel_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => dec_alu_rf1_mul_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_retsel_offset to ex1_retsel_offset + ex1_retsel_q'length-1), + scout => sov(ex1_retsel_offset to ex1_retsel_offset + ex1_retsel_q'length-1), + din => ex1_retsel_d, + dout => ex1_retsel_q); + ex2_retsel_latch : tri_rlmreg_p + generic map (width => ex2_retsel_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => ex1_mul_val_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_retsel_offset to ex2_retsel_offset + ex2_retsel_q'length-1), + scout => sov(ex2_retsel_offset to ex2_retsel_offset + ex2_retsel_q'length-1), + din => ex1_retsel_q, + dout => ex2_retsel_q); + ex3_retsel_latch : tri_rlmreg_p + generic map (width => ex3_retsel_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_retsel_offset to ex3_retsel_offset + ex3_retsel_q'length-1), + scout => sov(ex3_retsel_offset to ex3_retsel_offset + ex3_retsel_q'length-1), + din => ex2_retsel_q, + dout => ex3_retsel_q); + ex4_retsel_latch : tri_rlmreg_p + generic map (width => ex4_retsel_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_retsel_offset to ex4_retsel_offset + ex4_retsel_q'length-1), + scout => sov(ex4_retsel_offset to ex4_retsel_offset + ex4_retsel_q'length-1), + din => ex3_retsel_q, + dout => ex4_retsel_q); + ex3_mul_done_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_mul_done_offset), + scout => sov(ex3_mul_done_offset), + din => ex3_mul_done_d, + dout => ex3_mul_done_q); + ex4_mul_done_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_mul_done_offset), + scout => sov(ex4_mul_done_offset), + din => ex3_mul_done_q, + dout => ex4_mul_done_q); + ex5_mul_done_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_mul_done_offset), + scout => sov(ex5_mul_done_offset), + din => ex4_mul_done_q, + dout => ex5_mul_done_q); + ex1_is_recform_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => dec_alu_rf1_mul_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_recform_offset), + scout => sov(ex1_is_recform_offset), + din => dec_alu_rf1_mul_recform, + dout => ex1_is_recform_q); + ex2_is_recform_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_is_recform_offset), + scout => sov(ex2_is_recform_offset), + din => ex1_is_recform_q, + dout => ex2_is_recform_q); + ex3_is_recform_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_recform_offset), + scout => sov(ex3_is_recform_offset), + din => ex2_is_recform_q, + dout => ex3_is_recform_q); + ex4_is_recform_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_is_recform_offset), + scout => sov(ex4_is_recform_offset), + din => ex3_is_recform_q, + dout => ex4_is_recform_q); + ex5_is_recform_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_is_recform_offset), + scout => sov(ex5_is_recform_offset), + din => ex4_is_recform_q, + dout => ex5_is_recform_q); + ex1_xer_ov_update_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => dec_alu_rf1_mul_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_xer_ov_update_offset), + scout => sov(ex1_xer_ov_update_offset), + din => dec_alu_rf1_xer_ov_update, + dout => ex1_xer_ov_update_q); + ex2_xer_ov_update_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_xer_ov_update_offset), + scout => sov(ex2_xer_ov_update_offset), + din => ex1_xer_ov_update_q, + dout => ex2_xer_ov_update_q); + ex3_xer_ov_update_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_xer_ov_update_offset), + scout => sov(ex3_xer_ov_update_offset), + din => ex2_xer_ov_update_q, + dout => ex3_xer_ov_update_q); + ex4_xer_ov_update_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_xer_ov_update_offset), + scout => sov(ex4_xer_ov_update_offset), + din => ex3_xer_ov_update_q, + dout => ex4_xer_ov_update_q); + ex5_xer_ov_update_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_xer_ov_update_offset), + scout => sov(ex5_xer_ov_update_offset), + din => ex4_xer_ov_update_q, + dout => ex5_xer_ov_update_q); + ex1_mul_size_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => dec_alu_rf1_mul_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_mul_size_offset), + scout => sov(ex1_mul_size_offset), + din => dec_alu_rf1_mul_size, + dout => ex1_mul_size_q); + ex1_mul_sign_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => dec_alu_rf1_mul_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_mul_sign_offset), + scout => sov(ex1_mul_sign_offset), + din => dec_alu_rf1_mul_sign, + dout => ex1_mul_sign_q); + ex2_bs_lo_sign_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_bs_lo_sign_offset), + scout => sov(ex2_bs_lo_sign_offset), + din => ex2_bs_lo_sign_d, + dout => ex2_bs_lo_sign_q); + ex2_bd_lo_sign_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_bd_lo_sign_offset), + scout => sov(ex2_bd_lo_sign_offset), + din => ex2_bd_lo_sign_d, + dout => ex2_bd_lo_sign_q); + ex5_all0_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_all0_offset), + scout => sov(ex5_all0_offset), + din => ex4_all0, + dout => ex5_all0_q); + ex5_all1_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_all1_offset), + scout => sov(ex5_all1_offset), + din => ex4_all1, + dout => ex5_all1_q); + ex5_all0_lo_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_all0_lo_offset), + scout => sov(ex5_all0_lo_offset), + din => ex4_all0_lo, + dout => ex5_all0_lo_q); + ex5_all0_hi_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_all0_hi_offset), + scout => sov(ex5_all0_hi_offset), + din => ex4_all0_hi, + dout => ex5_all0_hi_q); + ex5_all1_hi_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_all1_hi_offset), + scout => sov(ex5_all1_hi_offset), + din => ex4_all1_hi, + dout => ex5_all1_hi_q); + ex4_ci_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_ci_offset), + scout => sov(ex4_ci_offset), + din => ex4_ci_d, + dout => ex4_ci_q); + ex5_res_latch : tri_rlmreg_p + generic map (width => ex5_res_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => ex4_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_res_offset to ex5_res_offset + ex5_res_q'length-1), + scout => sov(ex5_res_offset to ex5_res_offset + ex5_res_q'length-1), + din => ex4_res, + dout => ex5_res_q); + carry_32_dly1_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(carry_32_dly1_offset), + scout => sov(carry_32_dly1_offset), + din => ex4_cout_32, + dout => carry_32_dly1_q); + all0_lo_dly1_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(all0_lo_dly1_offset), + scout => sov(all0_lo_dly1_offset), + din => ex5_all0_lo_q, + dout => all0_lo_dly1_q); + all0_lo_dly2_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(all0_lo_dly2_offset), + scout => sov(all0_lo_dly2_offset), + din => all0_lo_dly1_q, + dout => all0_lo_dly2_q); + all0_lo_dly3_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(all0_lo_dly3_offset), + scout => sov(all0_lo_dly3_offset), + din => all0_lo_dly2_q, + dout => all0_lo_dly3_q); + rslt_lo_latch : tri_rlmreg_p + generic map (width => rslt_lo_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => rslt_lo_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rslt_lo_offset to rslt_lo_offset + rslt_lo_q'length-1), + scout => sov(rslt_lo_offset to rslt_lo_offset + rslt_lo_q'length-1), + din => rslt_lo_d, + dout => rslt_lo_q); + rslt_lo_dly_latch : tri_rlmreg_p + generic map (width => rslt_lo_dly_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rslt_lo_dly_offset to rslt_lo_dly_offset + rslt_lo_dly_q'length-1), + scout => sov(rslt_lo_dly_offset to rslt_lo_dly_offset + rslt_lo_dly_q'length-1), + din => rslt_lo_dly_d, + dout => rslt_lo_dly_q); + ex2_mulsrc_0_latch : tri_rlmreg_p + generic map (width => ex2_mulsrc_0_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_mulsrc0_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_mulsrc_0_offset to ex2_mulsrc_0_offset + ex2_mulsrc_0_q'length-1), + scout => sov(ex2_mulsrc_0_offset to ex2_mulsrc_0_offset + ex2_mulsrc_0_q'length-1), + din => ex1_mulsrc_0, + dout => ex2_mulsrc_0_q); + ex2_mulsrc_1_latch : tri_rlmreg_p + generic map (width => ex2_mulsrc_1_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_mulsrc1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_mulsrc_1_offset to ex2_mulsrc_1_offset + ex2_mulsrc_1_q'length-1), + scout => sov(ex2_mulsrc_1_offset to ex2_mulsrc_1_offset + ex2_mulsrc_1_q'length-1), + din => ex1_mulsrc_1, + dout => ex2_mulsrc_1_q); + ex5_rslt_hw_latch : tri_rlmreg_p + generic map (width => ex5_rslt_hw_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_mul_done_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_rslt_hw_offset to ex5_rslt_hw_offset + ex5_rslt_hw_q'length-1), + scout => sov(ex5_rslt_hw_offset to ex5_rslt_hw_offset + ex5_rslt_hw_q'length-1), + din => ex5_rslt_hw_d, + dout => ex5_rslt_hw_q); + ex5_rslt_ld_li_latch : tri_rlmreg_p + generic map (width => ex5_rslt_ld_li_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_mul_done_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_rslt_ld_li_offset to ex5_rslt_ld_li_offset + ex5_rslt_ld_li_q'length-1), + scout => sov(ex5_rslt_ld_li_offset to ex5_rslt_ld_li_offset + ex5_rslt_ld_li_q'length-1), + din => ex5_rslt_ld_li_d, + dout => ex5_rslt_ld_li_q); + ex5_rslt_ldo_latch : tri_rlmreg_p + generic map (width => ex5_rslt_ldo_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_mul_done_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_rslt_ldo_offset to ex5_rslt_ldo_offset + ex5_rslt_ldo_q'length-1), + scout => sov(ex5_rslt_ldo_offset to ex5_rslt_ldo_offset + ex5_rslt_ldo_q'length-1), + din => ex5_rslt_ldo_d, + dout => ex5_rslt_ldo_q); + ex5_rslt_lw_hd_latch : tri_rlmreg_p + generic map (width => ex5_rslt_lw_hd_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_mul_done_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_rslt_lw_hd_offset to ex5_rslt_lw_hd_offset + ex5_rslt_lw_hd_q'length-1), + scout => sov(ex5_rslt_lw_hd_offset to ex5_rslt_lw_hd_offset + ex5_rslt_lw_hd_q'length-1), + din => ex5_rslt_lw_hd_d, + dout => ex5_rslt_lw_hd_q); + ex5_cmp0_sel_reshi_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_mul_done_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_cmp0_sel_reshi_offset), + scout => sov(ex5_cmp0_sel_reshi_offset), + din => ex5_cmp0_sel_reshi_d, + dout => ex5_cmp0_sel_reshi_q); + ex5_cmp0_sel_reslo_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_mul_done_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_cmp0_sel_reslo_offset), + scout => sov(ex5_cmp0_sel_reslo_offset), + din => ex5_cmp0_sel_reslo_d, + dout => ex5_cmp0_sel_reslo_q); + ex5_cmp0_sel_reslodly_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_mul_done_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_cmp0_sel_reslodly_offset), + scout => sov(ex5_cmp0_sel_reslodly_offset), + din => ex5_cmp0_sel_reslodly_d, + dout => ex5_cmp0_sel_reslodly_q); + ex5_cmp0_sel_reslodly2_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_mul_done_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_cmp0_sel_reslodly2_offset), + scout => sov(ex5_cmp0_sel_reslodly2_offset), + din => ex5_cmp0_sel_reslodly2_d, + dout => ex5_cmp0_sel_reslodly2_q); + ex5_eq_sel_all0_b_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_mul_done_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_eq_sel_all0_b_offset), + scout => sov(ex5_eq_sel_all0_b_offset), + din => ex5_eq_sel_all0_b_d, + dout => ex5_eq_sel_all0_b_q); + ex5_eq_sel_all0_lo_b_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_mul_done_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_eq_sel_all0_lo_b_offset), + scout => sov(ex5_eq_sel_all0_lo_b_offset), + din => ex5_eq_sel_all0_lo_b_d, + dout => ex5_eq_sel_all0_lo_b_q); + ex5_eq_sel_all0_hi_b_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_mul_done_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_eq_sel_all0_hi_b_offset), + scout => sov(ex5_eq_sel_all0_hi_b_offset), + din => ex5_eq_sel_all0_hi_b_d, + dout => ex5_eq_sel_all0_hi_b_q); + ex5_eq_sel_all0_lo1_b_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_mul_done_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_eq_sel_all0_lo1_b_offset), + scout => sov(ex5_eq_sel_all0_lo1_b_offset), + din => ex5_eq_sel_all0_lo1_b_d, + dout => ex5_eq_sel_all0_lo1_b_q); + ex5_eq_sel_all0_lo2_b_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_mul_done_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_eq_sel_all0_lo2_b_offset), + scout => sov(ex5_eq_sel_all0_lo2_b_offset), + din => ex5_eq_sel_all0_lo2_b_d, + dout => ex5_eq_sel_all0_lo2_b_q); + ex5_eq_sel_all0_lo3_b_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_mul_done_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_eq_sel_all0_lo3_b_offset), + scout => sov(ex5_eq_sel_all0_lo3_b_offset), + din => ex5_eq_sel_all0_lo3_b_d, + dout => ex5_eq_sel_all0_lo3_b_q); + ex5_ret_mullw_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_mul_done_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_ret_mullw_offset), + scout => sov(ex5_ret_mullw_offset), + din => ex4_ret_mullw, + dout => ex5_ret_mullw_q); + ex5_ret_mulldo_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_mul_done_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_ret_mulldo_offset), + scout => sov(ex5_ret_mulldo_offset), + din => ex4_ret_mulldo, + dout => ex5_ret_mulldo_q); + ex5_cmp0_undef_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_mul_done_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_cmp0_undef_offset), + scout => sov(ex5_cmp0_undef_offset), + din => ex5_cmp0_undef_d, + dout => ex5_cmp0_undef_q); + + siv(0 to siv'right) <= sov(1 to siv'right) & scan_in; + scan_out <= sov(0); + +end architecture xuq_alu_mult; diff --git a/rel/src/vhdl/work/xuq_alu_mult_boothdcd.vhdl b/rel/src/vhdl/work/xuq_alu_mult_boothdcd.vhdl new file mode 100644 index 0000000..79e017d --- /dev/null +++ b/rel/src/vhdl/work/xuq_alu_mult_boothdcd.vhdl @@ -0,0 +1,106 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; +use ieee.std_logic_1164.all; +library ibm; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_ao_support.all; +use ibm.std_ulogic_mux_support.all; + +entity xuq_alu_mult_boothdcd is + port( + i0 : in std_ulogic; + i1 : in std_ulogic; + i2 : in std_ulogic; + s_neg : out std_ulogic; + s_x : out std_ulogic; + s_x2 : out std_ulogic); + + + +end xuq_alu_mult_boothdcd; + +architecture xuq_alu_mult_boothdcd of xuq_alu_mult_boothdcd is + + + signal s_add :std_ulogic; + signal sx1_a0_b :std_ulogic; + signal sx1_a1_b :std_ulogic; + signal sx1_t :std_ulogic; + signal sx1_i :std_ulogic; + signal sx2_a0_b :std_ulogic; + signal sx2_a1_b :std_ulogic; + signal sx2_t :std_ulogic; + signal sx2_i :std_ulogic; + signal i0_b, i1_b, i2_b :std_ulogic; + + +begin +-- i0:2 booth recode table +---------------------------------- +-- 000 add sh1=0 sh2=0 sub_adj=0 +-- 001 add sh1=1 sh2=0 sub_adj=0 +-- 010 add sh1=1 sh2=0 sub_adj=0 +-- 011 add sh1=0 sh2=1 sub_adj=0 +-- 100 sub sh1=0 sh2=1 sub_adj=1 +-- 101 sub sh1=1 sh2=0 sub_adj=1 +-- 110 sub sh1=1 sh2=0 sub_adj=1 +-- 111 sub sh1=0 sh2=0 sub_adj=0 + +-- logically correct +------------------------------------ +-- s_neg <= (i0); +-- s_x <= ( not i1 and i2) or ( i1 and not i2); +-- s_x2 <= (i0 and not i1 and not i2) or (not i0 and i1 and i2); + + +u_0i: i0_b <= not( i0 ); +u_1i: i1_b <= not( i1 ); +u_2i: i2_b <= not( i2 ); + + +u_add: s_add <= not( i0 ); +u_sub: s_neg <= not( s_add ); + +u_sx1_a0: sx1_a0_b <= not( i1_b and i2 ) ; +u_sx1_a1: sx1_a1_b <= not( i1 and i2_b ) ; +u_sx1_t: sx1_t <= not( sx1_a0_b and sx1_a1_b ) ; +u_sx1_i: sx1_i <= not( sx1_t ); +u_sx1_ii: s_x <= not( sx1_i ); + +u_sx2_a0: sx2_a0_b <= not( i0 and i1_b and i2_b ) ; +u_sx2_a1: sx2_a1_b <= not( i0_b and i1 and i2 ) ; +u_sx2_t: sx2_t <= not( sx2_a0_b and sx2_a1_b ) ; +u_sx2_i: sx2_i <= not( sx2_t ); +u_sx2_ii: s_x2 <= not( sx2_i ); + + +end; diff --git a/rel/src/vhdl/work/xuq_alu_mult_boothrow.vhdl b/rel/src/vhdl/work/xuq_alu_mult_boothrow.vhdl new file mode 100644 index 0000000..f8ea74d --- /dev/null +++ b/rel/src/vhdl/work/xuq_alu_mult_boothrow.vhdl @@ -0,0 +1,435 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +LIBRARY ieee; USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY ibm; + USE ibm.std_ulogic_support.all; + USE ibm.std_ulogic_unsigned.all; + USE ibm.std_ulogic_function_support.all; +LIBRARY support; + USE support.power_logic_pkg.all; +LIBRARY tri; USE tri.tri_latches_pkg.all; +LIBRARY clib; + +entity xuq_alu_mult_boothrow is + port( + s_neg : in std_ulogic; -- negate the row + s_x : in std_ulogic; -- shift by 0 + s_x2 : in std_ulogic; -- shift by 1 + sign_bit_adj : in std_ulogic; + x : in std_ulogic_vector(0 to 31); -- input (multiplicand) + q : out std_ulogic_vector(0 to 32); -- final output + hot_one : out std_ulogic; -- lsb term for row below + vdd : inout power_logic; + gnd : inout power_logic + ); +-- synopsys translate_off +-- synopsys translate_on +end xuq_alu_mult_boothrow; -- entity + +architecture xuq_alu_mult_boothrow of xuq_alu_mult_boothrow is + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal left : std_ulogic_vector(1 to 32); + +begin + + + + --------------------------------------------------------------------- + -- Build the booth mux row bit by bit + --------------------------------------------------------------------- + u00: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => sign_bit_adj, + RIGHT => left(1), + LEFT => open, + Q => q(0)); + + u01: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(0), + RIGHT => left(2), + LEFT => left(1), + Q => q(1)); + + u02: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(1), + RIGHT => left(3), + LEFT => left(2), + Q => q(2)); + + u03: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(2), + RIGHT => left(4), + LEFT => left(3), + Q => q(3)); + + u04: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(3), + RIGHT => left(5), + LEFT => left(4), + Q => q(4)); + + u05: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(4), + RIGHT => left(6), + LEFT => left(5), + Q => q(5)); + + u06: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(5), + RIGHT => left(7), + LEFT => left(6), + Q => q(6)); + + u07: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(6), + RIGHT => left(8), + LEFT => left(7), + Q => q(7)); + + u08: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(7), + RIGHT => left(9), + LEFT => left(8), + Q => q(8)); + + u09: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(8), + RIGHT => left(10), + LEFT => left(9), + Q => q(9)); + + u10: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(9), + RIGHT => left(11), + LEFT => left(10), + Q => q(10)); + + u11: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(10), + RIGHT => left(12), + LEFT => left(11), + Q => q(11)); + + u12: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(11), + RIGHT => left(13), + LEFT => left(12), + Q => q(12)); + + u13: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(12), + RIGHT => left(14), + LEFT => left(13), + Q => q(13)); + + u14: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(13), + RIGHT => left(15), + LEFT => left(14), + Q => q(14)); + + u15: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(14), + RIGHT => left(16), + LEFT => left(15), + Q => q(15)); + + u16: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(15), + RIGHT => left(17), + LEFT => left(16), + Q => q(16)); + + u17: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(16), + RIGHT => left(18), + LEFT => left(17), + Q => q(17)); + + u18: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(17), + RIGHT => left(19), + LEFT => left(18), + Q => q(18)); + + u19: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(18), + RIGHT => left(20), + LEFT => left(19), + Q => q(19)); + + u20: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(19), + RIGHT => left(21), + LEFT => left(20), + Q => q(20)); + + u21: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(20), + RIGHT => left(22), + LEFT => left(21), + Q => q(21)); + + u22: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(21), + RIGHT => left(23), + LEFT => left(22), + Q => q(22)); + + u23: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(22), + RIGHT => left(24), + LEFT => left(23), + Q => q(23)); + + u24: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(23), + RIGHT => left(25), + LEFT => left(24), + Q => q(24)); + + u25: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(24), + RIGHT => left(26), + LEFT => left(25), + Q => q(25)); + + u26: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(25), + RIGHT => left(27), + LEFT => left(26), + Q => q(26)); + + u27: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(26), + RIGHT => left(28), + LEFT => left(27), + Q => q(27)); + + u28: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(27), + RIGHT => left(29), + LEFT => left(28), + Q => q(28)); + + u29: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(28), + RIGHT => left(30), + LEFT => left(29), + Q => q(29)); + + u30: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(29), + RIGHT => left(31), + LEFT => left(30), + Q => q(30)); + + u31: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(30), + RIGHT => left(32), + LEFT => left(31), + Q => q(31)); + + u32: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map( + vd => vdd, + gd => gnd, + sneg => s_neg, + SX => s_x, + SX2 => s_x2, + X => x(31), + RIGHT => s_neg, + LEFT => left(32), + Q => q(32)); + + + u33: hot_one <= s_neg and (s_x or s_x2) ; +end; diff --git a/rel/src/vhdl/work/xuq_alu_mult_core.vhdl b/rel/src/vhdl/work/xuq_alu_mult_core.vhdl new file mode 100644 index 0000000..9a483dd --- /dev/null +++ b/rel/src/vhdl/work/xuq_alu_mult_core.vhdl @@ -0,0 +1,5926 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +LIBRARY ieee; USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY ibm; + USE ibm.std_ulogic_support.all; + USE ibm.std_ulogic_unsigned.all; + USE ibm.std_ulogic_function_support.all; +LIBRARY support; + USE support.power_logic_pkg.all; +LIBRARY tri; USE tri.tri_latches_pkg.all; +LIBRARY clib ; +LIBRARY work; USE work.xuq_pkg.all; + +-- ##################################################################### +-- ## multiplier with intermediate latches and output latches. +-- ## feedback so that 4 32bit multiplies emulate a 64 bit multiply +-- ##################################################################### + + +entity xuq_alu_mult_core is generic ( expand_type: integer := 2 ); port ( + + -- Pervasive --------------------------------------- + nclk :in clk_logic; + vdd :inout power_logic; + gnd :inout power_logic; + delay_lclkr_dc :in std_ulogic; + mpw1_dc_b :in std_ulogic; + mpw2_dc_b :in std_ulogic; + func_sl_force :in std_ulogic; + func_sl_thold_0_b :in std_ulogic; + sg_0 :in std_ulogic; + scan_in :in std_ulogic; + scan_out :out std_ulogic; + + ex2_act :in std_ulogic; -- for latches at end of first multiply cycle + ex3_act :in std_ulogic; -- for latches at end of second multiply cycle + + -- Numbers to multiply (with seperate sign bit) --------------------------- + ex2_bs_lo_sign :in std_ulogic; -- input data to multiply + ex2_bd_lo_sign :in std_ulogic; -- input data to multiply + ex2_bd_lo :in std_ulogic_vector(0 to 31); -- input data to multiply + ex2_bs_lo :in std_ulogic_vector(0 to 31); -- input data to multiply + + -- Feedback recirculation for multiple cycle multiply --------------------- + ex3_recycle_s :in std_ulogic_vector(196 to 264); --compressor feedback + ex3_recycle_c :in std_ulogic_vector(196 to 263); --compressor feedback + + -- result vectors ---------------(adder 0:63 uses my number 200:263) + ex4_pp5_0s_out :out std_ulogic_vector(196 to 264); -- compressor output to adder + ex4_pp5_0c_out :out std_ulogic_vector(196 to 263) -- compressor output to adder + ); + -- synopsys translate_off + -- synopsys translate_on +end xuq_alu_mult_core; + +architecture xuq_alu_mult_core of xuq_alu_mult_core is + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal ex3_d1clk, ex4_d1clk :std_ulogic ; + signal ex3_d2clk, ex4_d2clk :std_ulogic ; + signal ex3_lclk , ex4_lclk :clk_logic ; + + + signal ex3_pp2_0c_din, ex3_pp2_0c, ex3_pp2_0c_q_b, ex3_pp2_0c_lat_so , ex3_pp2_0c_lat_si :std_ulogic_vector(198 to 240) ; + signal ex3_pp2_0s_din, ex3_pp2_0s, ex3_pp2_0s_q_b, ex3_pp2_0s_lat_so , ex3_pp2_0s_lat_si :std_ulogic_vector(198 to 242) ; + signal ex3_pp2_1c_din, ex3_pp2_1c, ex3_pp2_1c_x, ex3_pp2_1c_x_b, ex3_pp2_1c_q_b, ex3_pp2_1c_lat_so , ex3_pp2_1c_lat_si :std_ulogic_vector(208 to 252) ; + signal ex3_pp2_1s_din, ex3_pp2_1s, ex3_pp2_1s_x, ex3_pp2_1s_x_b, ex3_pp2_1s_q_b, ex3_pp2_1s_lat_so , ex3_pp2_1s_lat_si :std_ulogic_vector(208 to 254) ; + signal ex3_pp2_2c_din, ex3_pp2_2c, ex3_pp2_2c_x, ex3_pp2_2c_x_b, ex3_pp2_2c_q_b, ex3_pp2_2c_lat_so , ex3_pp2_2c_lat_si :std_ulogic_vector(220 to 263) ; + signal ex3_pp2_2s_din, ex3_pp2_2s, ex3_pp2_2s_x, ex3_pp2_2s_x_b, ex3_pp2_2s_q_b, ex3_pp2_2s_lat_so , ex3_pp2_2s_lat_si :std_ulogic_vector(220 to 264) ; + + + signal ex4_pp5_0s_din, ex4_pp5_0s, ex4_pp5_0s_q_b, ex4_pp5_0s_lat_so , ex4_pp5_0s_lat_si :std_ulogic_vector(196 to 264); + signal ex4_pp5_0c_din, ex4_pp5_0c, ex4_pp5_0c_q_b, ex4_pp5_0c_lat_so , ex4_pp5_0c_lat_si :std_ulogic_vector(196 to 263); + + signal ex2_bd_neg, ex2_bd_sh0, ex2_bd_sh1 :std_ulogic_vector(0 to 16) ; + + signal ex2_br_00_out :std_ulogic_vector(0 to 32); + signal ex2_br_01_out :std_ulogic_vector(0 to 32); + signal ex2_br_02_out :std_ulogic_vector(0 to 32); + signal ex2_br_03_out :std_ulogic_vector(0 to 32); + signal ex2_br_04_out :std_ulogic_vector(0 to 32); + signal ex2_br_05_out :std_ulogic_vector(0 to 32); + signal ex2_br_06_out :std_ulogic_vector(0 to 32); + signal ex2_br_07_out :std_ulogic_vector(0 to 32); + signal ex2_br_08_out :std_ulogic_vector(0 to 32); + signal ex2_br_09_out :std_ulogic_vector(0 to 32); + signal ex2_br_10_out :std_ulogic_vector(0 to 32); + signal ex2_br_11_out :std_ulogic_vector(0 to 32); + signal ex2_br_12_out :std_ulogic_vector(0 to 32); + signal ex2_br_13_out :std_ulogic_vector(0 to 32); + signal ex2_br_14_out :std_ulogic_vector(0 to 32); + signal ex2_br_15_out :std_ulogic_vector(0 to 32); + signal ex2_br_16_out :std_ulogic_vector(0 to 32); + signal ex2_hot_one :std_ulogic_vector(0 to 16); + + + signal ex2_pp1_0c :std_ulogic_vector(199 to 234) ; + signal ex2_pp1_0s :std_ulogic_vector(198 to 236) ; + signal ex2_pp1_1c :std_ulogic_vector(203 to 240) ; + signal ex2_pp1_1s :std_ulogic_vector(202 to 242) ; + signal ex2_pp1_2c :std_ulogic_vector(209 to 246) ; + signal ex2_pp1_2s :std_ulogic_vector(208 to 248) ; + signal ex2_pp1_3c :std_ulogic_vector(215 to 252) ; + signal ex2_pp1_3s :std_ulogic_vector(214 to 254) ; + signal ex2_pp1_4c :std_ulogic_vector(221 to 258) ; + signal ex2_pp1_4s :std_ulogic_vector(220 to 260) ; + signal ex2_pp1_5c :std_ulogic_vector(227 to 264) ; + signal ex2_pp1_5s :std_ulogic_vector(226 to 264) ; + + + + + + + signal ex2_pp2_0c :std_ulogic_vector(198 to 240) ; + signal ex2_pp2_0s :std_ulogic_vector(198 to 242) ; + signal ex2_pp2_1c :std_ulogic_vector(208 to 252) ; + signal ex2_pp2_1s :std_ulogic_vector(208 to 254) ; + signal ex2_pp2_2c :std_ulogic_vector(220 to 263) ; + signal ex2_pp2_2s :std_ulogic_vector(220 to 264) ; + + signal ex2_pp2_0k :std_ulogic_vector(201 to 234) ; + signal ex2_pp2_1k :std_ulogic_vector(213 to 246) ; + signal ex2_pp2_2k :std_ulogic_vector(225 to 258) ; + + + signal ex3_pp3_0c :std_ulogic_vector(197 to 242) ; + signal ex3_pp3_0s :std_ulogic_vector(198 to 252) ; + signal ex3_pp3_1c :std_ulogic_vector(219 to 262) ; + signal ex3_pp3_1s :std_ulogic_vector(208 to 264) ; + + signal ex3_pp4_0k :std_ulogic_vector(207 to 242); + signal ex3_pp4_0c :std_ulogic_vector(197 to 262); + signal ex3_pp4_0s :std_ulogic_vector(197 to 264); + + signal ex3_pp5_0k :std_ulogic_vector(196 to 262); + signal ex3_pp5_0c :std_ulogic_vector(195 to 263); + signal ex3_pp5_0s :std_ulogic_vector(196 to 264); + signal ex2_br_00_add :std_ulogic; + signal ex2_br_01_add :std_ulogic; + signal ex2_br_02_add :std_ulogic; + signal ex2_br_03_add :std_ulogic; + signal ex2_br_04_add :std_ulogic; + signal ex2_br_05_add :std_ulogic; + signal ex2_br_06_add :std_ulogic; + signal ex2_br_07_add :std_ulogic; + signal ex2_br_08_add :std_ulogic; + signal ex2_br_09_add :std_ulogic; + signal ex2_br_10_add :std_ulogic; + signal ex2_br_11_add :std_ulogic; + signal ex2_br_12_add :std_ulogic; + signal ex2_br_13_add :std_ulogic; + signal ex2_br_14_add :std_ulogic; + signal ex2_br_15_add :std_ulogic; + signal ex2_br_16_add :std_ulogic; + signal ex2_br_16_sub :std_ulogic; + + signal ex2_pp0_00 :std_ulogic_vector(198 to 234) ; + signal ex2_pp0_01 :std_ulogic_vector(200 to 236) ; + signal ex2_pp0_02 :std_ulogic_vector(202 to 238) ; + signal ex2_pp0_03 :std_ulogic_vector(204 to 240) ; + signal ex2_pp0_04 :std_ulogic_vector(206 to 242) ; + signal ex2_pp0_05 :std_ulogic_vector(208 to 244) ; + signal ex2_pp0_06 :std_ulogic_vector(210 to 246) ; + signal ex2_pp0_07 :std_ulogic_vector(212 to 248) ; + signal ex2_pp0_08 :std_ulogic_vector(214 to 250) ; + signal ex2_pp0_09 :std_ulogic_vector(216 to 252) ; + signal ex2_pp0_10 :std_ulogic_vector(218 to 254) ; + signal ex2_pp0_11 :std_ulogic_vector(220 to 256) ; + signal ex2_pp0_12 :std_ulogic_vector(222 to 258) ; + signal ex2_pp0_13 :std_ulogic_vector(224 to 260) ; + signal ex2_pp0_14 :std_ulogic_vector(226 to 262) ; + signal ex2_pp0_15 :std_ulogic_vector(228 to 264) ; + signal ex2_pp0_16 :std_ulogic_vector(229 to 264) ; + signal ex2_pp0_17 :std_ulogic_vector(232 to 232) ; + + signal ex2_br_00_sign_xor :std_ulogic; + signal ex2_br_01_sign_xor :std_ulogic; + signal ex2_br_02_sign_xor :std_ulogic; + signal ex2_br_03_sign_xor :std_ulogic; + signal ex2_br_04_sign_xor :std_ulogic; + signal ex2_br_05_sign_xor :std_ulogic; + signal ex2_br_06_sign_xor :std_ulogic; + signal ex2_br_07_sign_xor :std_ulogic; + signal ex2_br_08_sign_xor :std_ulogic; + signal ex2_br_09_sign_xor :std_ulogic; + signal ex2_br_10_sign_xor :std_ulogic; + signal ex2_br_11_sign_xor :std_ulogic; + signal ex2_br_12_sign_xor :std_ulogic; + signal ex2_br_13_sign_xor :std_ulogic; + signal ex2_br_14_sign_xor :std_ulogic; + signal ex2_br_15_sign_xor :std_ulogic; + signal ex2_br_16_sign_xor :std_ulogic; + + + signal version :std_ulogic_vector(0 to 7) ; + +begin + + version <= "00010001" ; + + --*********************************** + --** booth decoders + --*********************************** + + bd_00: entity work.xuq_alu_mult_boothdcd port map ( + i0 => ex2_bd_lo_sign ,--i-- + i1 => ex2_bd_lo(0) ,--i-- + i2 => ex2_bd_lo(1) ,--i-- + s_neg => ex2_bd_neg(0) ,--o-- + s_x => ex2_bd_sh0(0) ,--o-- + s_x2 => ex2_bd_sh1(0) );--o-- + bd_01: entity work.xuq_alu_mult_boothdcd port map ( + i0 => ex2_bd_lo(1) ,--i-- + i1 => ex2_bd_lo(2) ,--i-- + i2 => ex2_bd_lo(3) ,--i-- + s_neg => ex2_bd_neg(1) ,--o-- + s_x => ex2_bd_sh0(1) ,--o-- + s_x2 => ex2_bd_sh1(1) );--o-- + bd_02: entity work.xuq_alu_mult_boothdcd port map ( + i0 => ex2_bd_lo(3) ,--i-- + i1 => ex2_bd_lo(4) ,--i-- + i2 => ex2_bd_lo(5) ,--i-- + s_neg => ex2_bd_neg(2) ,--o-- + s_x => ex2_bd_sh0(2) ,--o-- + s_x2 => ex2_bd_sh1(2) );--o-- + bd_03: entity work.xuq_alu_mult_boothdcd port map ( + i0 => ex2_bd_lo(5) ,--i-- + i1 => ex2_bd_lo(6) ,--i-- + i2 => ex2_bd_lo(7) ,--i-- + s_neg => ex2_bd_neg(3) ,--o-- + s_x => ex2_bd_sh0(3) ,--o-- + s_x2 => ex2_bd_sh1(3) );--o-- + bd_04: entity work.xuq_alu_mult_boothdcd port map ( + i0 => ex2_bd_lo(7) ,--i-- + i1 => ex2_bd_lo(8) ,--i-- + i2 => ex2_bd_lo(9) ,--i-- + s_neg => ex2_bd_neg(4) ,--o-- + s_x => ex2_bd_sh0(4) ,--o-- + s_x2 => ex2_bd_sh1(4) );--o-- + bd_05: entity work.xuq_alu_mult_boothdcd port map ( + i0 => ex2_bd_lo(9) ,--i-- + i1 => ex2_bd_lo(10) ,--i-- + i2 => ex2_bd_lo(11) ,--i-- + s_neg => ex2_bd_neg(5) ,--o-- + s_x => ex2_bd_sh0(5) ,--o-- + s_x2 => ex2_bd_sh1(5) );--o-- + bd_06: entity work.xuq_alu_mult_boothdcd port map ( + i0 => ex2_bd_lo(11) ,--i-- + i1 => ex2_bd_lo(12) ,--i-- + i2 => ex2_bd_lo(13) ,--i-- + s_neg => ex2_bd_neg(6) ,--o-- + s_x => ex2_bd_sh0(6) ,--o-- + s_x2 => ex2_bd_sh1(6) );--o-- + bd_07: entity work.xuq_alu_mult_boothdcd port map ( + i0 => ex2_bd_lo(13) ,--i-- + i1 => ex2_bd_lo(14) ,--i-- + i2 => ex2_bd_lo(15) ,--i-- + s_neg => ex2_bd_neg(7) ,--o-- + s_x => ex2_bd_sh0(7) ,--o-- + s_x2 => ex2_bd_sh1(7) );--o-- + bd_08: entity work.xuq_alu_mult_boothdcd port map ( + i0 => ex2_bd_lo(15) ,--i-- + i1 => ex2_bd_lo(16) ,--i-- + i2 => ex2_bd_lo(17) ,--i-- + s_neg => ex2_bd_neg(8) ,--o-- + s_x => ex2_bd_sh0(8) ,--o-- + s_x2 => ex2_bd_sh1(8) );--o-- + bd_09: entity work.xuq_alu_mult_boothdcd port map ( + i0 => ex2_bd_lo(17) ,--i-- + i1 => ex2_bd_lo(18) ,--i-- + i2 => ex2_bd_lo(19) ,--i-- + s_neg => ex2_bd_neg(9) ,--o-- + s_x => ex2_bd_sh0(9) ,--o-- + s_x2 => ex2_bd_sh1(9) );--o-- + bd_10: entity work.xuq_alu_mult_boothdcd port map ( + i0 => ex2_bd_lo(19) ,--i-- + i1 => ex2_bd_lo(20) ,--i-- + i2 => ex2_bd_lo(21) ,--i-- + s_neg => ex2_bd_neg(10) ,--o-- + s_x => ex2_bd_sh0(10) ,--o-- + s_x2 => ex2_bd_sh1(10) );--o-- + bd_11: entity work.xuq_alu_mult_boothdcd port map ( + i0 => ex2_bd_lo(21) ,--i-- + i1 => ex2_bd_lo(22) ,--i-- + i2 => ex2_bd_lo(23) ,--i-- + s_neg => ex2_bd_neg(11) ,--o-- + s_x => ex2_bd_sh0(11) ,--o-- + s_x2 => ex2_bd_sh1(11) );--o-- + bd_12: entity work.xuq_alu_mult_boothdcd port map ( + i0 => ex2_bd_lo(23) ,--i-- + i1 => ex2_bd_lo(24) ,--i-- + i2 => ex2_bd_lo(25) ,--i-- + s_neg => ex2_bd_neg(12) ,--o-- + s_x => ex2_bd_sh0(12) ,--o-- + s_x2 => ex2_bd_sh1(12) );--o-- + bd_13: entity work.xuq_alu_mult_boothdcd port map ( + i0 => ex2_bd_lo(25) ,--i-- + i1 => ex2_bd_lo(26) ,--i-- + i2 => ex2_bd_lo(27) ,--i-- + s_neg => ex2_bd_neg(13) ,--o-- + s_x => ex2_bd_sh0(13) ,--o-- + s_x2 => ex2_bd_sh1(13) );--o-- + bd_14: entity work.xuq_alu_mult_boothdcd port map ( + i0 => ex2_bd_lo(27) ,--i-- + i1 => ex2_bd_lo(28) ,--i-- + i2 => ex2_bd_lo(29) ,--i-- + s_neg => ex2_bd_neg(14) ,--o-- + s_x => ex2_bd_sh0(14) ,--o-- + s_x2 => ex2_bd_sh1(14) );--o-- + bd_15: entity work.xuq_alu_mult_boothdcd port map ( + i0 => ex2_bd_lo(29) ,--i-- + i1 => ex2_bd_lo(30) ,--i-- + i2 => ex2_bd_lo(31) ,--i-- + s_neg => ex2_bd_neg(15) ,--o-- + s_x => ex2_bd_sh0(15) ,--o-- + s_x2 => ex2_bd_sh1(15) );--o-- + bd_16: entity work.xuq_alu_mult_boothdcd port map ( + i0 => ex2_bd_lo(31) ,--i-- + i1 => tidn ,--i-- + i2 => tidn ,--i-- + s_neg => ex2_bd_neg(16) ,--o-- + s_x => ex2_bd_sh0(16) ,--o-- + s_x2 => ex2_bd_sh1(16) );--o-- + + --*********************************** + --** booth muxes + --*********************************** + +br_00: entity work.xuq_alu_mult_boothrow port map ( + vdd => vdd, + gnd => gnd, + s_neg => ex2_bd_neg(0) ,--i-- + s_x => ex2_bd_sh0(0) ,--i-- + s_x2 => ex2_bd_sh1(0) ,--i-- + sign_bit_adj => ex2_bs_lo_sign ,--i-- + x => ex2_bs_lo(0 to 31) ,--i-- + q => ex2_br_00_out(0 to 32) ,--o-- + hot_one => ex2_hot_one(0) );--o-- + br_01: entity work.xuq_alu_mult_boothrow port map ( + vdd => vdd, + gnd => gnd, + s_neg => ex2_bd_neg(1) ,--i-- + s_x => ex2_bd_sh0(1) ,--i-- + s_x2 => ex2_bd_sh1(1) ,--i-- + sign_bit_adj => ex2_bs_lo_sign ,--i-- + x => ex2_bs_lo(0 to 31) ,--i-- + q => ex2_br_01_out(0 to 32) ,--o-- + hot_one => ex2_hot_one(1) );--o-- + br_02: entity work.xuq_alu_mult_boothrow port map ( + vdd => vdd, + gnd => gnd, + s_neg => ex2_bd_neg(2) ,--i-- + s_x => ex2_bd_sh0(2) ,--i-- + s_x2 => ex2_bd_sh1(2) ,--i-- + sign_bit_adj => ex2_bs_lo_sign ,--i-- + x => ex2_bs_lo(0 to 31) ,--i-- + q => ex2_br_02_out(0 to 32) ,--o-- + hot_one => ex2_hot_one(2) );--o-- + br_03: entity work.xuq_alu_mult_boothrow port map ( + vdd => vdd, + gnd => gnd, + s_neg => ex2_bd_neg(3) ,--i-- + s_x => ex2_bd_sh0(3) ,--i-- + s_x2 => ex2_bd_sh1(3) ,--i-- + sign_bit_adj => ex2_bs_lo_sign ,--i-- + x => ex2_bs_lo(0 to 31) ,--i-- + q => ex2_br_03_out(0 to 32) ,--o-- + hot_one => ex2_hot_one(3) );--o-- + br_04: entity work.xuq_alu_mult_boothrow port map ( + vdd => vdd, + gnd => gnd, + s_neg => ex2_bd_neg(4) ,--i-- + s_x => ex2_bd_sh0(4) ,--i-- + s_x2 => ex2_bd_sh1(4) ,--i-- + sign_bit_adj => ex2_bs_lo_sign ,--i-- + x => ex2_bs_lo(0 to 31) ,--i-- + q => ex2_br_04_out(0 to 32) ,--o-- + hot_one => ex2_hot_one(4) );--o-- + br_05: entity work.xuq_alu_mult_boothrow port map ( + vdd => vdd, + gnd => gnd, + s_neg => ex2_bd_neg(5) ,--i-- + s_x => ex2_bd_sh0(5) ,--i-- + s_x2 => ex2_bd_sh1(5) ,--i-- + sign_bit_adj => ex2_bs_lo_sign ,--i-- + x => ex2_bs_lo(0 to 31) ,--i-- + q => ex2_br_05_out(0 to 32) ,--o-- + hot_one => ex2_hot_one(5) );--o-- + br_06: entity work.xuq_alu_mult_boothrow port map ( + vdd => vdd, + gnd => gnd, + s_neg => ex2_bd_neg(6) ,--i-- + s_x => ex2_bd_sh0(6) ,--i-- + s_x2 => ex2_bd_sh1(6) ,--i-- + sign_bit_adj => ex2_bs_lo_sign ,--i-- + x => ex2_bs_lo(0 to 31) ,--i-- + q => ex2_br_06_out(0 to 32) ,--o-- + hot_one => ex2_hot_one(6) );--o-- + br_07: entity work.xuq_alu_mult_boothrow port map ( + vdd => vdd, + gnd => gnd, + s_neg => ex2_bd_neg(7) ,--i-- + s_x => ex2_bd_sh0(7) ,--i-- + s_x2 => ex2_bd_sh1(7) ,--i-- + sign_bit_adj => ex2_bs_lo_sign ,--i-- + x => ex2_bs_lo(0 to 31) ,--i-- + q => ex2_br_07_out(0 to 32) ,--o-- + hot_one => ex2_hot_one(7) );--o-- + br_08: entity work.xuq_alu_mult_boothrow port map ( + vdd => vdd, + gnd => gnd, + s_neg => ex2_bd_neg(8) ,--i-- + s_x => ex2_bd_sh0(8) ,--i-- + s_x2 => ex2_bd_sh1(8) ,--i-- + sign_bit_adj => ex2_bs_lo_sign ,--i-- + x => ex2_bs_lo(0 to 31) ,--i-- + q => ex2_br_08_out(0 to 32) ,--o-- + hot_one => ex2_hot_one(8) );--o-- + br_09: entity work.xuq_alu_mult_boothrow port map ( + vdd => vdd, + gnd => gnd, + s_neg => ex2_bd_neg(9) ,--i-- + s_x => ex2_bd_sh0(9) ,--i-- + s_x2 => ex2_bd_sh1(9) ,--i-- + sign_bit_adj => ex2_bs_lo_sign ,--i-- + x => ex2_bs_lo(0 to 31) ,--i-- + q => ex2_br_09_out(0 to 32) ,--o-- + hot_one => ex2_hot_one(9) );--o-- + br_10: entity work.xuq_alu_mult_boothrow port map ( + vdd => vdd, + gnd => gnd, + s_neg => ex2_bd_neg(10) ,--i-- + s_x => ex2_bd_sh0(10) ,--i-- + s_x2 => ex2_bd_sh1(10) ,--i-- + sign_bit_adj => ex2_bs_lo_sign ,--i-- + x => ex2_bs_lo(0 to 31) ,--i-- + q => ex2_br_10_out(0 to 32) ,--o-- + hot_one => ex2_hot_one(10) );--o-- + br_11: entity work.xuq_alu_mult_boothrow port map ( + vdd => vdd, + gnd => gnd, + s_neg => ex2_bd_neg(11) ,--i-- + s_x => ex2_bd_sh0(11) ,--i-- + s_x2 => ex2_bd_sh1(11) ,--i-- + sign_bit_adj => ex2_bs_lo_sign ,--i-- + x => ex2_bs_lo(0 to 31) ,--i-- + q => ex2_br_11_out(0 to 32) ,--o-- + hot_one => ex2_hot_one(11) );--o-- + br_12: entity work.xuq_alu_mult_boothrow port map ( + vdd => vdd, + gnd => gnd, + s_neg => ex2_bd_neg(12) ,--i-- + s_x => ex2_bd_sh0(12) ,--i-- + s_x2 => ex2_bd_sh1(12) ,--i-- + sign_bit_adj => ex2_bs_lo_sign ,--i-- + x => ex2_bs_lo(0 to 31) ,--i-- + q => ex2_br_12_out(0 to 32) ,--o-- + hot_one => ex2_hot_one(12) );--o-- + br_13: entity work.xuq_alu_mult_boothrow port map ( + vdd => vdd, + gnd => gnd, + s_neg => ex2_bd_neg(13) ,--i-- + s_x => ex2_bd_sh0(13) ,--i-- + s_x2 => ex2_bd_sh1(13) ,--i-- + sign_bit_adj => ex2_bs_lo_sign ,--i-- + x => ex2_bs_lo(0 to 31) ,--i-- + q => ex2_br_13_out(0 to 32) ,--o-- + hot_one => ex2_hot_one(13) );--o-- + br_14: entity work.xuq_alu_mult_boothrow port map ( + vdd => vdd, + gnd => gnd, + s_neg => ex2_bd_neg(14) ,--i-- + s_x => ex2_bd_sh0(14) ,--i-- + s_x2 => ex2_bd_sh1(14) ,--i-- + sign_bit_adj => ex2_bs_lo_sign ,--i-- + x => ex2_bs_lo(0 to 31) ,--i-- + q => ex2_br_14_out(0 to 32) ,--o-- + hot_one => ex2_hot_one(14) );--o-- + br_15: entity work.xuq_alu_mult_boothrow port map ( + vdd => vdd, + gnd => gnd, + s_neg => ex2_bd_neg(15) ,--i-- + s_x => ex2_bd_sh0(15) ,--i-- + s_x2 => ex2_bd_sh1(15) ,--i-- + sign_bit_adj => ex2_bs_lo_sign ,--i-- + x => ex2_bs_lo(0 to 31) ,--i-- + q => ex2_br_15_out(0 to 32) ,--o-- + hot_one => ex2_hot_one(15) );--o-- + br_16: entity work.xuq_alu_mult_boothrow port map ( + vdd => vdd, + gnd => gnd, + s_neg => ex2_bd_neg(16) ,--i-- + s_x => ex2_bd_sh0(16) ,--i-- + s_x2 => ex2_bd_sh1(16) ,--i-- + sign_bit_adj => ex2_bs_lo_sign ,--i-- + x => ex2_bs_lo(0 to 31) ,--i-- + q => ex2_br_16_out(0 to 32) ,--o-- + hot_one => ex2_hot_one(16) );--o-- + + + + + + + + u_br_00_sx: ex2_br_00_sign_xor <= ex2_bs_lo_sign xor ex2_bd_neg(0) ; + u_br_01_sx: ex2_br_01_sign_xor <= ex2_bs_lo_sign xor ex2_bd_neg(1) ; + u_br_02_sx: ex2_br_02_sign_xor <= ex2_bs_lo_sign xor ex2_bd_neg(2) ; + u_br_03_sx: ex2_br_03_sign_xor <= ex2_bs_lo_sign xor ex2_bd_neg(3) ; + u_br_04_sx: ex2_br_04_sign_xor <= ex2_bs_lo_sign xor ex2_bd_neg(4) ; + u_br_05_sx: ex2_br_05_sign_xor <= ex2_bs_lo_sign xor ex2_bd_neg(5) ; + u_br_06_sx: ex2_br_06_sign_xor <= ex2_bs_lo_sign xor ex2_bd_neg(6) ; + u_br_07_sx: ex2_br_07_sign_xor <= ex2_bs_lo_sign xor ex2_bd_neg(7) ; + u_br_08_sx: ex2_br_08_sign_xor <= ex2_bs_lo_sign xor ex2_bd_neg(8) ; + u_br_09_sx: ex2_br_09_sign_xor <= ex2_bs_lo_sign xor ex2_bd_neg(9) ; + u_br_10_sx: ex2_br_10_sign_xor <= ex2_bs_lo_sign xor ex2_bd_neg(10) ; + u_br_11_sx: ex2_br_11_sign_xor <= ex2_bs_lo_sign xor ex2_bd_neg(11) ; + u_br_12_sx: ex2_br_12_sign_xor <= ex2_bs_lo_sign xor ex2_bd_neg(12) ; + u_br_13_sx: ex2_br_13_sign_xor <= ex2_bs_lo_sign xor ex2_bd_neg(13) ; + u_br_14_sx: ex2_br_14_sign_xor <= ex2_bs_lo_sign xor ex2_bd_neg(14) ; + u_br_15_sx: ex2_br_15_sign_xor <= ex2_bs_lo_sign xor ex2_bd_neg(15) ; + u_br_16_sx: ex2_br_16_sign_xor <= ex2_bs_lo_sign xor ex2_bd_neg(16) ; + + + + u_br_00_add: ex2_br_00_add <= not( ex2_br_00_sign_xor and (ex2_bd_sh0(0) or ex2_bd_sh1(0) ) ) ; -- add + u_br_01_add: ex2_br_01_add <= not( ex2_br_01_sign_xor and (ex2_bd_sh0(1) or ex2_bd_sh1(1) ) ) ; -- add + u_br_02_add: ex2_br_02_add <= not( ex2_br_02_sign_xor and (ex2_bd_sh0(2) or ex2_bd_sh1(2) ) ) ; -- add + u_br_03_add: ex2_br_03_add <= not( ex2_br_03_sign_xor and (ex2_bd_sh0(3) or ex2_bd_sh1(3) ) ) ; -- add + u_br_04_add: ex2_br_04_add <= not( ex2_br_04_sign_xor and (ex2_bd_sh0(4) or ex2_bd_sh1(4) ) ) ; -- add + u_br_05_add: ex2_br_05_add <= not( ex2_br_05_sign_xor and (ex2_bd_sh0(5) or ex2_bd_sh1(5) ) ) ; -- add + u_br_06_add: ex2_br_06_add <= not( ex2_br_06_sign_xor and (ex2_bd_sh0(6) or ex2_bd_sh1(6) ) ) ; -- add + u_br_07_add: ex2_br_07_add <= not( ex2_br_07_sign_xor and (ex2_bd_sh0(7) or ex2_bd_sh1(7) ) ) ; -- add + u_br_08_add: ex2_br_08_add <= not( ex2_br_08_sign_xor and (ex2_bd_sh0(8) or ex2_bd_sh1(8) ) ) ; -- add + u_br_09_add: ex2_br_09_add <= not( ex2_br_09_sign_xor and (ex2_bd_sh0(9) or ex2_bd_sh1(9) ) ) ; -- add + u_br_10_add: ex2_br_10_add <= not( ex2_br_10_sign_xor and (ex2_bd_sh0(10) or ex2_bd_sh1(10) ) ) ; -- add + u_br_11_add: ex2_br_11_add <= not( ex2_br_11_sign_xor and (ex2_bd_sh0(11) or ex2_bd_sh1(11) ) ) ; -- add + u_br_12_add: ex2_br_12_add <= not( ex2_br_12_sign_xor and (ex2_bd_sh0(12) or ex2_bd_sh1(12) ) ) ; -- add + u_br_13_add: ex2_br_13_add <= not( ex2_br_13_sign_xor and (ex2_bd_sh0(13) or ex2_bd_sh1(13) ) ) ; -- add + u_br_14_add: ex2_br_14_add <= not( ex2_br_14_sign_xor and (ex2_bd_sh0(14) or ex2_bd_sh1(14) ) ) ; -- add + u_br_15_add: ex2_br_15_add <= not( ex2_br_15_sign_xor and (ex2_bd_sh0(15) or ex2_bd_sh1(15) ) ) ; -- add + u_br_16_add: ex2_br_16_add <= not( ex2_br_16_sign_xor and (ex2_bd_sh0(16) or ex2_bd_sh1(16) ) ) ; -- add + u_br_16_sub: ex2_br_16_sub <= ex2_br_16_sign_xor and (ex2_bd_sh0(16) or ex2_bd_sh1(16) ) ; -- sub + + + + ex2_pp0_00(198) <= tiup ; + ex2_pp0_00(199) <= ex2_br_00_add ; + ex2_pp0_00(200 to 232) <= ex2_br_00_out(0 to 32) ; + ex2_pp0_00(233) <= tidn ; + ex2_pp0_00(234) <= ex2_hot_one(1) ; + + ex2_pp0_01(200) <= tiup ; + ex2_pp0_01(201) <= ex2_br_01_add ; + ex2_pp0_01(202 to 234) <= ex2_br_01_out(0 to 32) ; + ex2_pp0_01(235) <= tidn ; + ex2_pp0_01(236) <= ex2_hot_one(2) ; + + ex2_pp0_02(202) <= tiup ; + ex2_pp0_02(203) <= ex2_br_02_add ; + ex2_pp0_02(204 to 236) <= ex2_br_02_out(0 to 32) ; + ex2_pp0_02(237) <= tidn ; + ex2_pp0_02(238) <= ex2_hot_one(3) ; + + ex2_pp0_03(204) <= tiup ; + ex2_pp0_03(205) <= ex2_br_03_add ; + ex2_pp0_03(206 to 238) <= ex2_br_03_out(0 to 32) ; + ex2_pp0_03(239) <= tidn ; + ex2_pp0_03(240) <= ex2_hot_one(4) ; + + ex2_pp0_04(206) <= tiup ; + ex2_pp0_04(207) <= ex2_br_04_add ; + ex2_pp0_04(208 to 240) <= ex2_br_04_out(0 to 32) ; + ex2_pp0_04(241) <= tidn ; + ex2_pp0_04(242) <= ex2_hot_one(5) ; + + ex2_pp0_05(208) <= tiup ; + ex2_pp0_05(209) <= ex2_br_05_add ; + ex2_pp0_05(210 to 242) <= ex2_br_05_out(0 to 32) ; + ex2_pp0_05(243) <= tidn ; + ex2_pp0_05(244) <= ex2_hot_one(6) ; + + ex2_pp0_06(210) <= tiup ; + ex2_pp0_06(211) <= ex2_br_06_add ; + ex2_pp0_06(212 to 244) <= ex2_br_06_out(0 to 32) ; + ex2_pp0_06(245) <= tidn ; + ex2_pp0_06(246) <= ex2_hot_one(7) ; + + ex2_pp0_07(212) <= tiup ; + ex2_pp0_07(213) <= ex2_br_07_add ; + ex2_pp0_07(214 to 246) <= ex2_br_07_out(0 to 32) ; + ex2_pp0_07(247) <= tidn ; + ex2_pp0_07(248) <= ex2_hot_one(8) ; + + ex2_pp0_08(214) <= tiup ; + ex2_pp0_08(215) <= ex2_br_08_add ; + ex2_pp0_08(216 to 248) <= ex2_br_08_out(0 to 32) ; + ex2_pp0_08(249) <= tidn ; + ex2_pp0_08(250) <= ex2_hot_one(9) ; + + ex2_pp0_09(216) <= tiup ; + ex2_pp0_09(217) <= ex2_br_09_add ; + ex2_pp0_09(218 to 250) <= ex2_br_09_out(0 to 32) ; + ex2_pp0_09(251) <= tidn ; + ex2_pp0_09(252) <= ex2_hot_one(10) ; + + ex2_pp0_10(218) <= tiup ; + ex2_pp0_10(219) <= ex2_br_10_add ; + ex2_pp0_10(220 to 252) <= ex2_br_10_out(0 to 32) ; + ex2_pp0_10(253) <= tidn ; + ex2_pp0_10(254) <= ex2_hot_one(11) ; + + ex2_pp0_11(220) <= tiup ; + ex2_pp0_11(221) <= ex2_br_11_add ; + ex2_pp0_11(222 to 254) <= ex2_br_11_out(0 to 32) ; + ex2_pp0_11(255) <= tidn ; + ex2_pp0_11(256) <= ex2_hot_one(12) ; + + ex2_pp0_12(222) <= tiup ; + ex2_pp0_12(223) <= ex2_br_12_add ; + ex2_pp0_12(224 to 256) <= ex2_br_12_out(0 to 32) ; + ex2_pp0_12(257) <= tidn ; + ex2_pp0_12(258) <= ex2_hot_one(13) ; + + ex2_pp0_13(224) <= tiup ; + ex2_pp0_13(225) <= ex2_br_13_add ; + ex2_pp0_13(226 to 258) <= ex2_br_13_out(0 to 32) ; + ex2_pp0_13(259) <= tidn ; + ex2_pp0_13(260) <= ex2_hot_one(14) ; + + ex2_pp0_14(226) <= tiup ; + ex2_pp0_14(227) <= ex2_br_14_add ; + ex2_pp0_14(228 to 260) <= ex2_br_14_out(0 to 32) ; + ex2_pp0_14(261) <= tidn ; + ex2_pp0_14(262) <= ex2_hot_one(15) ; + + ex2_pp0_15(228) <= tiup ; + ex2_pp0_15(229) <= ex2_br_15_add ; + ex2_pp0_15(230 to 262) <= ex2_br_15_out(0 to 32) ; + ex2_pp0_15(263) <= tidn ; + ex2_pp0_15(264) <= ex2_hot_one(16) ; + + ex2_pp0_16(229) <= ex2_br_16_add ; + ex2_pp0_16(230) <= ex2_br_16_sub ; + ex2_pp0_16(231) <= ex2_br_16_sub ; + ex2_pp0_16(232 to 264) <= ex2_br_16_out(0 to 32) ; + + ex2_pp0_17(232) <= ex2_hot_one(0) ; + + + + + --*********************************** + --** compression level 1 + --*********************************** +--=== g1 : for i in 196 to 264 generate +--=== csa1_0: entity work.c_prism_csa32 generic map( btr => "MLT32_X1_A12TH" ) port map( +--=== a => ex2_pp0_17(i) ,--i-- +--=== b => ex2_pp0_00(i) ,--i-- +--=== c => ex2_pp0_01(i) ,--i-- +--=== sum => ex2_pp1_0s(i) ,--o-- +--=== car => ex2_pp1_0cex2_pp1_0c(23(i-1) );--o-- +--=== csa1_1: entity work.c_prism_csa32 generic map( btr => "MLT32_X1_A12TH" ) port map( +--=== a => ex2_pp0_02(i) ,--i-- +--=== b => ex2_pp0_03(i) ,--i-- +--=== c => ex2_pp0_04(i) ,--i-- +--=== sum => ex2_pp1_1s(i) ,--o-- +--=== car => ex2_pp1_1c(i-1) );--o-- +--=== csa1_2: entity work.c_prism_csa32 generic map( btr => "MLT32_X1_A12TH" ) port map( +--=== a => ex2_pp0_05(i) ,--i-- +--=== b => ex2_pp0_06(i) ,--i-- +--=== c => ex2_pp0_07(i) ,--i-- +--=== sum => ex2_pp1_2s(i) ,--o-- +--=== car => ex2_pp1_2c(i-1) );--o-- +--=== csa1_3: entity work.c_prism_csa32 generic map( btr => "MLT32_X1_A12TH" ) port map( +--=== a => ex2_pp0_08(i) ,--i-- +--=== b => ex2_pp0_09(i) ,--i-- +--=== c => ex2_pp0_10(i) ,--i-- +--=== sum => ex2_pp1_3s(i) ,--o-- +--=== car => ex2_pp1_3c(i-1) );--o-- +--=== csa1_4: entity work.c_prism_csa32 generic map( btr => "MLT32_X1_A12TH" ) port map( +--=== a => ex2_pp0_11(i) ,--i-- +--=== b => ex2_pp0_12(i) ,--i-- +--=== c => ex2_pp0_13(i) ,--i-- +--=== sum => ex2_pp1_4s(i) ,--o-- +--=== car => ex2_pp1_4c(i-1) );--o-- +--=== csa1_5: entity work.c_prism_csa32 generic map( btr => "MLT32_X1_A12TH" ) port map( +--=== a => ex2_pp0_14(i) ,--i-- +--=== b => ex2_pp0_15(i) ,--i-- +--=== c => ex2_pp0_16(i) ,--i-- +--=== sum => ex2_pp1_5s(i) ,--o-- +--=== car => ex2_pp1_5c(i-1) );--o-- +--=== end generate; +--=== ex2_pp1_0c(264) <= tidn ; +--=== ex2_pp1_1c(264) <= tidn ; +--=== ex2_pp1_2c(264) <= tidn ; +--=== ex2_pp1_3c(264) <= tidn ; +--=== ex2_pp1_4c(264) <= tidn ; +--=== ex2_pp1_5c(264) <= tidn ; + + + ------- ----- + + ex2_pp1_0s(236) <= ex2_pp0_01(236) ; --pass_s + ex2_pp1_0s(235) <= tidn ; --pass_none + ex2_pp1_0c(234) <= ex2_pp0_01(234) ; --pass_cs + ex2_pp1_0s(234) <= ex2_pp0_00(234) ; --pass_cs + ex2_pp1_0c(233) <= tidn ; --pass_s + ex2_pp1_0s(233) <= ex2_pp0_01(233) ; --pass_s + ex2_pp1_0c(232) <= tidn ; --wr_csa32 + +-- pp1_02_csa_71: entity work.fuq_csa22_h2(fuq_csa22_h2) port map ( +-- clib.c_prism_csa22 work.xuq_alu_mult_csa22 + + csa1_0_232: entity clib.c_prism_csa32 port map( -- MLT32_X1_A12TH + vd => vdd, + gd => gnd, + a => ex2_pp0_00(232) ,--i-- + b => ex2_pp0_01(232) ,--i-- + c => ex2_pp0_17(232) ,--i-- + sum => ex2_pp1_0s(232) ,--o-- + car => ex2_pp1_0c(231) );--o-- + csa1_0_231: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(231) ,--i-- + b => ex2_pp0_01(231) ,--i-- + sum => ex2_pp1_0s(231) ,--o-- + car => ex2_pp1_0c(230) );--o-- + csa1_0_230: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(230) ,--i-- + b => ex2_pp0_01(230) ,--i-- + sum => ex2_pp1_0s(230) ,--o-- + car => ex2_pp1_0c(229) );--o-- + csa1_0_229: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(229) ,--i-- + b => ex2_pp0_01(229) ,--i-- + sum => ex2_pp1_0s(229) ,--o-- + car => ex2_pp1_0c(228) );--o-- + csa1_0_228: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(228) ,--i-- + b => ex2_pp0_01(228) ,--i-- + sum => ex2_pp1_0s(228) ,--o-- + car => ex2_pp1_0c(227) );--o-- + csa1_0_227: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(227) ,--i-- + b => ex2_pp0_01(227) ,--i-- + sum => ex2_pp1_0s(227) ,--o-- + car => ex2_pp1_0c(226) );--o-- + csa1_0_226: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(226) ,--i-- + b => ex2_pp0_01(226) ,--i-- + sum => ex2_pp1_0s(226) ,--o-- + car => ex2_pp1_0c(225) );--o-- + csa1_0_225: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(225) ,--i-- + b => ex2_pp0_01(225) ,--i-- + sum => ex2_pp1_0s(225) ,--o-- + car => ex2_pp1_0c(224) );--o-- + csa1_0_224: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(224) ,--i-- + b => ex2_pp0_01(224) ,--i-- + sum => ex2_pp1_0s(224) ,--o-- + car => ex2_pp1_0c(223) );--o-- + csa1_0_223: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(223) ,--i-- + b => ex2_pp0_01(223) ,--i-- + sum => ex2_pp1_0s(223) ,--o-- + car => ex2_pp1_0c(222) );--o-- + csa1_0_222: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(222) ,--i-- + b => ex2_pp0_01(222) ,--i-- + sum => ex2_pp1_0s(222) ,--o-- + car => ex2_pp1_0c(221) );--o-- + csa1_0_221: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(221) ,--i-- + b => ex2_pp0_01(221) ,--i-- + sum => ex2_pp1_0s(221) ,--o-- + car => ex2_pp1_0c(220) );--o-- + csa1_0_220: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(220) ,--i-- + b => ex2_pp0_01(220) ,--i-- + sum => ex2_pp1_0s(220) ,--o-- + car => ex2_pp1_0c(219) );--o-- + csa1_0_219: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(219) ,--i-- + b => ex2_pp0_01(219) ,--i-- + sum => ex2_pp1_0s(219) ,--o-- + car => ex2_pp1_0c(218) );--o-- + csa1_0_218: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(218) ,--i-- + b => ex2_pp0_01(218) ,--i-- + sum => ex2_pp1_0s(218) ,--o-- + car => ex2_pp1_0c(217) );--o-- + csa1_0_217: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(217) ,--i-- + b => ex2_pp0_01(217) ,--i-- + sum => ex2_pp1_0s(217) ,--o-- + car => ex2_pp1_0c(216) );--o-- + csa1_0_216: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(216) ,--i-- + b => ex2_pp0_01(216) ,--i-- + sum => ex2_pp1_0s(216) ,--o-- + car => ex2_pp1_0c(215) );--o-- + csa1_0_215: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(215) ,--i-- + b => ex2_pp0_01(215) ,--i-- + sum => ex2_pp1_0s(215) ,--o-- + car => ex2_pp1_0c(214) );--o-- + csa1_0_214: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(214) ,--i-- + b => ex2_pp0_01(214) ,--i-- + sum => ex2_pp1_0s(214) ,--o-- + car => ex2_pp1_0c(213) );--o-- + csa1_0_213: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(213) ,--i-- + b => ex2_pp0_01(213) ,--i-- + sum => ex2_pp1_0s(213) ,--o-- + car => ex2_pp1_0c(212) );--o-- + csa1_0_212: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(212) ,--i-- + b => ex2_pp0_01(212) ,--i-- + sum => ex2_pp1_0s(212) ,--o-- + car => ex2_pp1_0c(211) );--o-- + csa1_0_211: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(211) ,--i-- + b => ex2_pp0_01(211) ,--i-- + sum => ex2_pp1_0s(211) ,--o-- + car => ex2_pp1_0c(210) );--o-- + csa1_0_210: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(210) ,--i-- + b => ex2_pp0_01(210) ,--i-- + sum => ex2_pp1_0s(210) ,--o-- + car => ex2_pp1_0c(209) );--o-- + csa1_0_209: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(209) ,--i-- + b => ex2_pp0_01(209) ,--i-- + sum => ex2_pp1_0s(209) ,--o-- + car => ex2_pp1_0c(208) );--o-- + csa1_0_208: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(208) ,--i-- + b => ex2_pp0_01(208) ,--i-- + sum => ex2_pp1_0s(208) ,--o-- + car => ex2_pp1_0c(207) );--o-- + csa1_0_207: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(207) ,--i-- + b => ex2_pp0_01(207) ,--i-- + sum => ex2_pp1_0s(207) ,--o-- + car => ex2_pp1_0c(206) );--o-- + csa1_0_206: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(206) ,--i-- + b => ex2_pp0_01(206) ,--i-- + sum => ex2_pp1_0s(206) ,--o-- + car => ex2_pp1_0c(205) );--o-- + csa1_0_205: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(205) ,--i-- + b => ex2_pp0_01(205) ,--i-- + sum => ex2_pp1_0s(205) ,--o-- + car => ex2_pp1_0c(204) );--o-- + csa1_0_204: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(204) ,--i-- + b => ex2_pp0_01(204) ,--i-- + sum => ex2_pp1_0s(204) ,--o-- + car => ex2_pp1_0c(203) );--o-- + csa1_0_203: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(203) ,--i-- + b => ex2_pp0_01(203) ,--i-- + sum => ex2_pp1_0s(203) ,--o-- + car => ex2_pp1_0c(202) );--o-- + csa1_0_202: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(202) ,--i-- + b => ex2_pp0_01(202) ,--i-- + sum => ex2_pp1_0s(202) ,--o-- + car => ex2_pp1_0c(201) );--o-- + csa1_0_201: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(201) ,--i-- + b => ex2_pp0_01(201) ,--i-- + sum => ex2_pp1_0s(201) ,--o-- + car => ex2_pp1_0c(200) );--o-- + csa1_0_200: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_00(200) ,--i-- + b => ex2_pp0_01(200) ,--i-- + sum => ex2_pp1_0s(200) ,--o-- + car => ex2_pp1_0c(199) );--o-- + ex2_pp1_0s(199) <= ex2_pp0_00(199) ; --pass_x_s + ex2_pp1_0s(198) <= ex2_pp0_00(198) ; --pass_s + + + + + + ------- ----- + + ex2_pp1_1s(242) <= ex2_pp0_04(242) ; --pass_s + ex2_pp1_1s(241) <= tidn ; --pass_none + ex2_pp1_1c(240) <= ex2_pp0_04(240) ; --pass_cs + ex2_pp1_1s(240) <= ex2_pp0_03(240) ; --pass_cs + ex2_pp1_1c(239) <= tidn ; --pass_s + ex2_pp1_1s(239) <= ex2_pp0_04(239) ; --pass_s + ex2_pp1_1c(238) <= tidn ; --wr_csa32 + csa1_1_238: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(238) ,--i-- + b => ex2_pp0_03(238) ,--i-- + c => ex2_pp0_04(238) ,--i-- + sum => ex2_pp1_1s(238) ,--o-- + car => ex2_pp1_1c(237) );--o-- + csa1_1_237: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_03(237) ,--i-- + b => ex2_pp0_04(237) ,--i-- + sum => ex2_pp1_1s(237) ,--o-- + car => ex2_pp1_1c(236) );--o-- + csa1_1_236: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(236) ,--i-- + b => ex2_pp0_03(236) ,--i-- + c => ex2_pp0_04(236) ,--i-- + sum => ex2_pp1_1s(236) ,--o-- + car => ex2_pp1_1c(235) );--o-- + csa1_1_235: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(235) ,--i-- + b => ex2_pp0_03(235) ,--i-- + c => ex2_pp0_04(235) ,--i-- + sum => ex2_pp1_1s(235) ,--o-- + car => ex2_pp1_1c(234) );--o-- + csa1_1_234: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(234) ,--i-- + b => ex2_pp0_03(234) ,--i-- + c => ex2_pp0_04(234) ,--i-- + sum => ex2_pp1_1s(234) ,--o-- + car => ex2_pp1_1c(233) );--o-- + csa1_1_233: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(233) ,--i-- + b => ex2_pp0_03(233) ,--i-- + c => ex2_pp0_04(233) ,--i-- + sum => ex2_pp1_1s(233) ,--o-- + car => ex2_pp1_1c(232) );--o-- + csa1_1_232: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(232) ,--i-- + b => ex2_pp0_03(232) ,--i-- + c => ex2_pp0_04(232) ,--i-- + sum => ex2_pp1_1s(232) ,--o-- + car => ex2_pp1_1c(231) );--o-- + csa1_1_231: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(231) ,--i-- + b => ex2_pp0_03(231) ,--i-- + c => ex2_pp0_04(231) ,--i-- + sum => ex2_pp1_1s(231) ,--o-- + car => ex2_pp1_1c(230) );--o-- + csa1_1_230: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(230) ,--i-- + b => ex2_pp0_03(230) ,--i-- + c => ex2_pp0_04(230) ,--i-- + sum => ex2_pp1_1s(230) ,--o-- + car => ex2_pp1_1c(229) );--o-- + csa1_1_229: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(229) ,--i-- + b => ex2_pp0_03(229) ,--i-- + c => ex2_pp0_04(229) ,--i-- + sum => ex2_pp1_1s(229) ,--o-- + car => ex2_pp1_1c(228) );--o-- + csa1_1_228: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(228) ,--i-- + b => ex2_pp0_03(228) ,--i-- + c => ex2_pp0_04(228) ,--i-- + sum => ex2_pp1_1s(228) ,--o-- + car => ex2_pp1_1c(227) );--o-- + csa1_1_227: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(227) ,--i-- + b => ex2_pp0_03(227) ,--i-- + c => ex2_pp0_04(227) ,--i-- + sum => ex2_pp1_1s(227) ,--o-- + car => ex2_pp1_1c(226) );--o-- + csa1_1_226: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(226) ,--i-- + b => ex2_pp0_03(226) ,--i-- + c => ex2_pp0_04(226) ,--i-- + sum => ex2_pp1_1s(226) ,--o-- + car => ex2_pp1_1c(225) );--o-- + csa1_1_225: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(225) ,--i-- + b => ex2_pp0_03(225) ,--i-- + c => ex2_pp0_04(225) ,--i-- + sum => ex2_pp1_1s(225) ,--o-- + car => ex2_pp1_1c(224) );--o-- + csa1_1_224: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(224) ,--i-- + b => ex2_pp0_03(224) ,--i-- + c => ex2_pp0_04(224) ,--i-- + sum => ex2_pp1_1s(224) ,--o-- + car => ex2_pp1_1c(223) );--o-- + csa1_1_223: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(223) ,--i-- + b => ex2_pp0_03(223) ,--i-- + c => ex2_pp0_04(223) ,--i-- + sum => ex2_pp1_1s(223) ,--o-- + car => ex2_pp1_1c(222) );--o-- + csa1_1_222: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(222) ,--i-- + b => ex2_pp0_03(222) ,--i-- + c => ex2_pp0_04(222) ,--i-- + sum => ex2_pp1_1s(222) ,--o-- + car => ex2_pp1_1c(221) );--o-- + csa1_1_221: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(221) ,--i-- + b => ex2_pp0_03(221) ,--i-- + c => ex2_pp0_04(221) ,--i-- + sum => ex2_pp1_1s(221) ,--o-- + car => ex2_pp1_1c(220) );--o-- + csa1_1_220: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(220) ,--i-- + b => ex2_pp0_03(220) ,--i-- + c => ex2_pp0_04(220) ,--i-- + sum => ex2_pp1_1s(220) ,--o-- + car => ex2_pp1_1c(219) );--o-- + csa1_1_219: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(219) ,--i-- + b => ex2_pp0_03(219) ,--i-- + c => ex2_pp0_04(219) ,--i-- + sum => ex2_pp1_1s(219) ,--o-- + car => ex2_pp1_1c(218) );--o-- + csa1_1_218: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(218) ,--i-- + b => ex2_pp0_03(218) ,--i-- + c => ex2_pp0_04(218) ,--i-- + sum => ex2_pp1_1s(218) ,--o-- + car => ex2_pp1_1c(217) );--o-- + csa1_1_217: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(217) ,--i-- + b => ex2_pp0_03(217) ,--i-- + c => ex2_pp0_04(217) ,--i-- + sum => ex2_pp1_1s(217) ,--o-- + car => ex2_pp1_1c(216) );--o-- + csa1_1_216: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(216) ,--i-- + b => ex2_pp0_03(216) ,--i-- + c => ex2_pp0_04(216) ,--i-- + sum => ex2_pp1_1s(216) ,--o-- + car => ex2_pp1_1c(215) );--o-- + csa1_1_215: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(215) ,--i-- + b => ex2_pp0_03(215) ,--i-- + c => ex2_pp0_04(215) ,--i-- + sum => ex2_pp1_1s(215) ,--o-- + car => ex2_pp1_1c(214) );--o-- + csa1_1_214: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(214) ,--i-- + b => ex2_pp0_03(214) ,--i-- + c => ex2_pp0_04(214) ,--i-- + sum => ex2_pp1_1s(214) ,--o-- + car => ex2_pp1_1c(213) );--o-- + csa1_1_213: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(213) ,--i-- + b => ex2_pp0_03(213) ,--i-- + c => ex2_pp0_04(213) ,--i-- + sum => ex2_pp1_1s(213) ,--o-- + car => ex2_pp1_1c(212) );--o-- + csa1_1_212: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(212) ,--i-- + b => ex2_pp0_03(212) ,--i-- + c => ex2_pp0_04(212) ,--i-- + sum => ex2_pp1_1s(212) ,--o-- + car => ex2_pp1_1c(211) );--o-- + csa1_1_211: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(211) ,--i-- + b => ex2_pp0_03(211) ,--i-- + c => ex2_pp0_04(211) ,--i-- + sum => ex2_pp1_1s(211) ,--o-- + car => ex2_pp1_1c(210) );--o-- + csa1_1_210: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(210) ,--i-- + b => ex2_pp0_03(210) ,--i-- + c => ex2_pp0_04(210) ,--i-- + sum => ex2_pp1_1s(210) ,--o-- + car => ex2_pp1_1c(209) );--o-- + csa1_1_209: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(209) ,--i-- + b => ex2_pp0_03(209) ,--i-- + c => ex2_pp0_04(209) ,--i-- + sum => ex2_pp1_1s(209) ,--o-- + car => ex2_pp1_1c(208) );--o-- + csa1_1_208: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(208) ,--i-- + b => ex2_pp0_03(208) ,--i-- + c => ex2_pp0_04(208) ,--i-- + sum => ex2_pp1_1s(208) ,--o-- + car => ex2_pp1_1c(207) );--o-- + csa1_1_207: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(207) ,--i-- + b => ex2_pp0_03(207) ,--i-- + c => ex2_pp0_04(207) ,--i-- + sum => ex2_pp1_1s(207) ,--o-- + car => ex2_pp1_1c(206) );--o-- + csa1_1_206: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_02(206) ,--i-- + b => ex2_pp0_03(206) ,--i-- + c => ex2_pp0_04(206) ,--i-- + sum => ex2_pp1_1s(206) ,--o-- + car => ex2_pp1_1c(205) );--o-- + csa1_1_205: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_02(205) ,--i-- + b => ex2_pp0_03(205) ,--i-- + sum => ex2_pp1_1s(205) ,--o-- + car => ex2_pp1_1c(204) );--o-- + csa1_1_204: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_02(204) ,--i-- + b => ex2_pp0_03(204) ,--i-- + sum => ex2_pp1_1s(204) ,--o-- + car => ex2_pp1_1c(203) );--o-- + ex2_pp1_1s(203) <= ex2_pp0_02(203) ; --pass_x_s + ex2_pp1_1s(202) <= ex2_pp0_02(202) ; --pass_s + + + + ------- ----- + + ex2_pp1_2s(248) <= ex2_pp0_07(248) ; --pass_s + ex2_pp1_2s(247) <= tidn ; --pass_none + ex2_pp1_2c(246) <= ex2_pp0_07(246) ; --pass_cs + ex2_pp1_2s(246) <= ex2_pp0_06(246) ; --pass_cs + ex2_pp1_2c(245) <= tidn ; --pass_s + ex2_pp1_2s(245) <= ex2_pp0_07(245) ; --pass_s + ex2_pp1_2c(244) <= tidn ; --wr_csa32 + csa1_2_244: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(244) ,--i-- + b => ex2_pp0_06(244) ,--i-- + c => ex2_pp0_07(244) ,--i-- + sum => ex2_pp1_2s(244) ,--o-- + car => ex2_pp1_2c(243) );--o-- + csa1_2_243: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_06(243) ,--i-- + b => ex2_pp0_07(243) ,--i-- + sum => ex2_pp1_2s(243) ,--o-- + car => ex2_pp1_2c(242) );--o-- + csa1_2_242: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(242) ,--i-- + b => ex2_pp0_06(242) ,--i-- + c => ex2_pp0_07(242) ,--i-- + sum => ex2_pp1_2s(242) ,--o-- + car => ex2_pp1_2c(241) );--o-- + csa1_2_241: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(241) ,--i-- + b => ex2_pp0_06(241) ,--i-- + c => ex2_pp0_07(241) ,--i-- + sum => ex2_pp1_2s(241) ,--o-- + car => ex2_pp1_2c(240) );--o-- + csa1_2_240: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(240) ,--i-- + b => ex2_pp0_06(240) ,--i-- + c => ex2_pp0_07(240) ,--i-- + sum => ex2_pp1_2s(240) ,--o-- + car => ex2_pp1_2c(239) );--o-- + csa1_2_239: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(239) ,--i-- + b => ex2_pp0_06(239) ,--i-- + c => ex2_pp0_07(239) ,--i-- + sum => ex2_pp1_2s(239) ,--o-- + car => ex2_pp1_2c(238) );--o-- + csa1_2_238: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(238) ,--i-- + b => ex2_pp0_06(238) ,--i-- + c => ex2_pp0_07(238) ,--i-- + sum => ex2_pp1_2s(238) ,--o-- + car => ex2_pp1_2c(237) );--o-- + csa1_2_237: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(237) ,--i-- + b => ex2_pp0_06(237) ,--i-- + c => ex2_pp0_07(237) ,--i-- + sum => ex2_pp1_2s(237) ,--o-- + car => ex2_pp1_2c(236) );--o-- + csa1_2_236: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(236) ,--i-- + b => ex2_pp0_06(236) ,--i-- + c => ex2_pp0_07(236) ,--i-- + sum => ex2_pp1_2s(236) ,--o-- + car => ex2_pp1_2c(235) );--o-- + csa1_2_235: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(235) ,--i-- + b => ex2_pp0_06(235) ,--i-- + c => ex2_pp0_07(235) ,--i-- + sum => ex2_pp1_2s(235) ,--o-- + car => ex2_pp1_2c(234) );--o-- + csa1_2_234: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(234) ,--i-- + b => ex2_pp0_06(234) ,--i-- + c => ex2_pp0_07(234) ,--i-- + sum => ex2_pp1_2s(234) ,--o-- + car => ex2_pp1_2c(233) );--o-- + csa1_2_233: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(233) ,--i-- + b => ex2_pp0_06(233) ,--i-- + c => ex2_pp0_07(233) ,--i-- + sum => ex2_pp1_2s(233) ,--o-- + car => ex2_pp1_2c(232) );--o-- + csa1_2_232: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(232) ,--i-- + b => ex2_pp0_06(232) ,--i-- + c => ex2_pp0_07(232) ,--i-- + sum => ex2_pp1_2s(232) ,--o-- + car => ex2_pp1_2c(231) );--o-- + csa1_2_231: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(231) ,--i-- + b => ex2_pp0_06(231) ,--i-- + c => ex2_pp0_07(231) ,--i-- + sum => ex2_pp1_2s(231) ,--o-- + car => ex2_pp1_2c(230) );--o-- + csa1_2_230: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(230) ,--i-- + b => ex2_pp0_06(230) ,--i-- + c => ex2_pp0_07(230) ,--i-- + sum => ex2_pp1_2s(230) ,--o-- + car => ex2_pp1_2c(229) );--o-- + csa1_2_229: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(229) ,--i-- + b => ex2_pp0_06(229) ,--i-- + c => ex2_pp0_07(229) ,--i-- + sum => ex2_pp1_2s(229) ,--o-- + car => ex2_pp1_2c(228) );--o-- + csa1_2_228: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(228) ,--i-- + b => ex2_pp0_06(228) ,--i-- + c => ex2_pp0_07(228) ,--i-- + sum => ex2_pp1_2s(228) ,--o-- + car => ex2_pp1_2c(227) );--o-- + csa1_2_227: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(227) ,--i-- + b => ex2_pp0_06(227) ,--i-- + c => ex2_pp0_07(227) ,--i-- + sum => ex2_pp1_2s(227) ,--o-- + car => ex2_pp1_2c(226) );--o-- + csa1_2_226: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(226) ,--i-- + b => ex2_pp0_06(226) ,--i-- + c => ex2_pp0_07(226) ,--i-- + sum => ex2_pp1_2s(226) ,--o-- + car => ex2_pp1_2c(225) );--o-- + csa1_2_225: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(225) ,--i-- + b => ex2_pp0_06(225) ,--i-- + c => ex2_pp0_07(225) ,--i-- + sum => ex2_pp1_2s(225) ,--o-- + car => ex2_pp1_2c(224) );--o-- + csa1_2_224: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(224) ,--i-- + b => ex2_pp0_06(224) ,--i-- + c => ex2_pp0_07(224) ,--i-- + sum => ex2_pp1_2s(224) ,--o-- + car => ex2_pp1_2c(223) );--o-- + csa1_2_223: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(223) ,--i-- + b => ex2_pp0_06(223) ,--i-- + c => ex2_pp0_07(223) ,--i-- + sum => ex2_pp1_2s(223) ,--o-- + car => ex2_pp1_2c(222) );--o-- + csa1_2_222: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(222) ,--i-- + b => ex2_pp0_06(222) ,--i-- + c => ex2_pp0_07(222) ,--i-- + sum => ex2_pp1_2s(222) ,--o-- + car => ex2_pp1_2c(221) );--o-- + csa1_2_221: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(221) ,--i-- + b => ex2_pp0_06(221) ,--i-- + c => ex2_pp0_07(221) ,--i-- + sum => ex2_pp1_2s(221) ,--o-- + car => ex2_pp1_2c(220) );--o-- + csa1_2_220: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(220) ,--i-- + b => ex2_pp0_06(220) ,--i-- + c => ex2_pp0_07(220) ,--i-- + sum => ex2_pp1_2s(220) ,--o-- + car => ex2_pp1_2c(219) );--o-- + csa1_2_219: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(219) ,--i-- + b => ex2_pp0_06(219) ,--i-- + c => ex2_pp0_07(219) ,--i-- + sum => ex2_pp1_2s(219) ,--o-- + car => ex2_pp1_2c(218) );--o-- + csa1_2_218: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(218) ,--i-- + b => ex2_pp0_06(218) ,--i-- + c => ex2_pp0_07(218) ,--i-- + sum => ex2_pp1_2s(218) ,--o-- + car => ex2_pp1_2c(217) );--o-- + csa1_2_217: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(217) ,--i-- + b => ex2_pp0_06(217) ,--i-- + c => ex2_pp0_07(217) ,--i-- + sum => ex2_pp1_2s(217) ,--o-- + car => ex2_pp1_2c(216) );--o-- + csa1_2_216: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(216) ,--i-- + b => ex2_pp0_06(216) ,--i-- + c => ex2_pp0_07(216) ,--i-- + sum => ex2_pp1_2s(216) ,--o-- + car => ex2_pp1_2c(215) );--o-- + csa1_2_215: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(215) ,--i-- + b => ex2_pp0_06(215) ,--i-- + c => ex2_pp0_07(215) ,--i-- + sum => ex2_pp1_2s(215) ,--o-- + car => ex2_pp1_2c(214) );--o-- + csa1_2_214: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(214) ,--i-- + b => ex2_pp0_06(214) ,--i-- + c => ex2_pp0_07(214) ,--i-- + sum => ex2_pp1_2s(214) ,--o-- + car => ex2_pp1_2c(213) );--o-- + csa1_2_213: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(213) ,--i-- + b => ex2_pp0_06(213) ,--i-- + c => ex2_pp0_07(213) ,--i-- + sum => ex2_pp1_2s(213) ,--o-- + car => ex2_pp1_2c(212) );--o-- + csa1_2_212: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_05(212) ,--i-- + b => ex2_pp0_06(212) ,--i-- + c => ex2_pp0_07(212) ,--i-- + sum => ex2_pp1_2s(212) ,--o-- + car => ex2_pp1_2c(211) );--o-- + csa1_2_211: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_05(211) ,--i-- + b => ex2_pp0_06(211) ,--i-- + sum => ex2_pp1_2s(211) ,--o-- + car => ex2_pp1_2c(210) );--o-- + csa1_2_210: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_05(210) ,--i-- + b => ex2_pp0_06(210) ,--i-- + sum => ex2_pp1_2s(210) ,--o-- + car => ex2_pp1_2c(209) );--o-- + ex2_pp1_2s(209) <= ex2_pp0_05(209) ; --pass_x_s + ex2_pp1_2s(208) <= ex2_pp0_05(208) ; --pass_s + + + + + ------- ----- + + ex2_pp1_3s(254) <= ex2_pp0_10(254) ; --pass_s + ex2_pp1_3s(253) <= tidn ; --pass_none + ex2_pp1_3c(252) <= ex2_pp0_10(252) ; --pass_cs + ex2_pp1_3s(252) <= ex2_pp0_09(252) ; --pass_cs + ex2_pp1_3c(251) <= tidn ; --pass_s + ex2_pp1_3s(251) <= ex2_pp0_10(251) ; --pass_s + ex2_pp1_3c(250) <= tidn ; --wr_csa32 + csa1_3_250: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(250) ,--i-- + b => ex2_pp0_09(250) ,--i-- + c => ex2_pp0_10(250) ,--i-- + sum => ex2_pp1_3s(250) ,--o-- + car => ex2_pp1_3c(249) );--o-- + csa1_3_249: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_09(249) ,--i-- + b => ex2_pp0_10(249) ,--i-- + sum => ex2_pp1_3s(249) ,--o-- + car => ex2_pp1_3c(248) );--o-- + csa1_3_248: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(248) ,--i-- + b => ex2_pp0_09(248) ,--i-- + c => ex2_pp0_10(248) ,--i-- + sum => ex2_pp1_3s(248) ,--o-- + car => ex2_pp1_3c(247) );--o-- + csa1_3_247: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(247) ,--i-- + b => ex2_pp0_09(247) ,--i-- + c => ex2_pp0_10(247) ,--i-- + sum => ex2_pp1_3s(247) ,--o-- + car => ex2_pp1_3c(246) );--o-- + csa1_3_246: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(246) ,--i-- + b => ex2_pp0_09(246) ,--i-- + c => ex2_pp0_10(246) ,--i-- + sum => ex2_pp1_3s(246) ,--o-- + car => ex2_pp1_3c(245) );--o-- + csa1_3_245: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(245) ,--i-- + b => ex2_pp0_09(245) ,--i-- + c => ex2_pp0_10(245) ,--i-- + sum => ex2_pp1_3s(245) ,--o-- + car => ex2_pp1_3c(244) );--o-- + csa1_3_244: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(244) ,--i-- + b => ex2_pp0_09(244) ,--i-- + c => ex2_pp0_10(244) ,--i-- + sum => ex2_pp1_3s(244) ,--o-- + car => ex2_pp1_3c(243) );--o-- + csa1_3_243: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(243) ,--i-- + b => ex2_pp0_09(243) ,--i-- + c => ex2_pp0_10(243) ,--i-- + sum => ex2_pp1_3s(243) ,--o-- + car => ex2_pp1_3c(242) );--o-- + csa1_3_242: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(242) ,--i-- + b => ex2_pp0_09(242) ,--i-- + c => ex2_pp0_10(242) ,--i-- + sum => ex2_pp1_3s(242) ,--o-- + car => ex2_pp1_3c(241) );--o-- + csa1_3_241: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(241) ,--i-- + b => ex2_pp0_09(241) ,--i-- + c => ex2_pp0_10(241) ,--i-- + sum => ex2_pp1_3s(241) ,--o-- + car => ex2_pp1_3c(240) );--o-- + csa1_3_240: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(240) ,--i-- + b => ex2_pp0_09(240) ,--i-- + c => ex2_pp0_10(240) ,--i-- + sum => ex2_pp1_3s(240) ,--o-- + car => ex2_pp1_3c(239) );--o-- + csa1_3_239: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(239) ,--i-- + b => ex2_pp0_09(239) ,--i-- + c => ex2_pp0_10(239) ,--i-- + sum => ex2_pp1_3s(239) ,--o-- + car => ex2_pp1_3c(238) );--o-- + csa1_3_238: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(238) ,--i-- + b => ex2_pp0_09(238) ,--i-- + c => ex2_pp0_10(238) ,--i-- + sum => ex2_pp1_3s(238) ,--o-- + car => ex2_pp1_3c(237) );--o-- + csa1_3_237: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(237) ,--i-- + b => ex2_pp0_09(237) ,--i-- + c => ex2_pp0_10(237) ,--i-- + sum => ex2_pp1_3s(237) ,--o-- + car => ex2_pp1_3c(236) );--o-- + csa1_3_236: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(236) ,--i-- + b => ex2_pp0_09(236) ,--i-- + c => ex2_pp0_10(236) ,--i-- + sum => ex2_pp1_3s(236) ,--o-- + car => ex2_pp1_3c(235) );--o-- + csa1_3_235: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(235) ,--i-- + b => ex2_pp0_09(235) ,--i-- + c => ex2_pp0_10(235) ,--i-- + sum => ex2_pp1_3s(235) ,--o-- + car => ex2_pp1_3c(234) );--o-- + csa1_3_234: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(234) ,--i-- + b => ex2_pp0_09(234) ,--i-- + c => ex2_pp0_10(234) ,--i-- + sum => ex2_pp1_3s(234) ,--o-- + car => ex2_pp1_3c(233) );--o-- + csa1_3_233: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(233) ,--i-- + b => ex2_pp0_09(233) ,--i-- + c => ex2_pp0_10(233) ,--i-- + sum => ex2_pp1_3s(233) ,--o-- + car => ex2_pp1_3c(232) );--o-- + csa1_3_232: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(232) ,--i-- + b => ex2_pp0_09(232) ,--i-- + c => ex2_pp0_10(232) ,--i-- + sum => ex2_pp1_3s(232) ,--o-- + car => ex2_pp1_3c(231) );--o-- + csa1_3_231: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(231) ,--i-- + b => ex2_pp0_09(231) ,--i-- + c => ex2_pp0_10(231) ,--i-- + sum => ex2_pp1_3s(231) ,--o-- + car => ex2_pp1_3c(230) );--o-- + csa1_3_230: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(230) ,--i-- + b => ex2_pp0_09(230) ,--i-- + c => ex2_pp0_10(230) ,--i-- + sum => ex2_pp1_3s(230) ,--o-- + car => ex2_pp1_3c(229) );--o-- + csa1_3_229: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(229) ,--i-- + b => ex2_pp0_09(229) ,--i-- + c => ex2_pp0_10(229) ,--i-- + sum => ex2_pp1_3s(229) ,--o-- + car => ex2_pp1_3c(228) );--o-- + csa1_3_228: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(228) ,--i-- + b => ex2_pp0_09(228) ,--i-- + c => ex2_pp0_10(228) ,--i-- + sum => ex2_pp1_3s(228) ,--o-- + car => ex2_pp1_3c(227) );--o-- + csa1_3_227: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(227) ,--i-- + b => ex2_pp0_09(227) ,--i-- + c => ex2_pp0_10(227) ,--i-- + sum => ex2_pp1_3s(227) ,--o-- + car => ex2_pp1_3c(226) );--o-- + csa1_3_226: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(226) ,--i-- + b => ex2_pp0_09(226) ,--i-- + c => ex2_pp0_10(226) ,--i-- + sum => ex2_pp1_3s(226) ,--o-- + car => ex2_pp1_3c(225) );--o-- + csa1_3_225: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(225) ,--i-- + b => ex2_pp0_09(225) ,--i-- + c => ex2_pp0_10(225) ,--i-- + sum => ex2_pp1_3s(225) ,--o-- + car => ex2_pp1_3c(224) );--o-- + csa1_3_224: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(224) ,--i-- + b => ex2_pp0_09(224) ,--i-- + c => ex2_pp0_10(224) ,--i-- + sum => ex2_pp1_3s(224) ,--o-- + car => ex2_pp1_3c(223) );--o-- + csa1_3_223: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(223) ,--i-- + b => ex2_pp0_09(223) ,--i-- + c => ex2_pp0_10(223) ,--i-- + sum => ex2_pp1_3s(223) ,--o-- + car => ex2_pp1_3c(222) );--o-- + csa1_3_222: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(222) ,--i-- + b => ex2_pp0_09(222) ,--i-- + c => ex2_pp0_10(222) ,--i-- + sum => ex2_pp1_3s(222) ,--o-- + car => ex2_pp1_3c(221) );--o-- + csa1_3_221: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(221) ,--i-- + b => ex2_pp0_09(221) ,--i-- + c => ex2_pp0_10(221) ,--i-- + sum => ex2_pp1_3s(221) ,--o-- + car => ex2_pp1_3c(220) );--o-- + csa1_3_220: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(220) ,--i-- + b => ex2_pp0_09(220) ,--i-- + c => ex2_pp0_10(220) ,--i-- + sum => ex2_pp1_3s(220) ,--o-- + car => ex2_pp1_3c(219) );--o-- + csa1_3_219: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(219) ,--i-- + b => ex2_pp0_09(219) ,--i-- + c => ex2_pp0_10(219) ,--i-- + sum => ex2_pp1_3s(219) ,--o-- + car => ex2_pp1_3c(218) );--o-- + csa1_3_218: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_08(218) ,--i-- + b => ex2_pp0_09(218) ,--i-- + c => ex2_pp0_10(218) ,--i-- + sum => ex2_pp1_3s(218) ,--o-- + car => ex2_pp1_3c(217) );--o-- + csa1_3_217: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_08(217) ,--i-- + b => ex2_pp0_09(217) ,--i-- + sum => ex2_pp1_3s(217) ,--o-- + car => ex2_pp1_3c(216) );--o-- + csa1_3_216: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_08(216) ,--i-- + b => ex2_pp0_09(216) ,--i-- + sum => ex2_pp1_3s(216) ,--o-- + car => ex2_pp1_3c(215) );--o-- + ex2_pp1_3s(215) <= ex2_pp0_08(215) ; --pass_x_s + ex2_pp1_3s(214) <= ex2_pp0_08(214) ; --pass_s + + + + ------- ----- + + ex2_pp1_4s(260) <= ex2_pp0_13(260) ; --pass_s + ex2_pp1_4s(259) <= tidn ; --pass_none + ex2_pp1_4c(258) <= ex2_pp0_13(258) ; --pass_cs + ex2_pp1_4s(258) <= ex2_pp0_12(258) ; --pass_cs + ex2_pp1_4c(257) <= tidn ; --pass_s + ex2_pp1_4s(257) <= ex2_pp0_13(257) ; --pass_s + ex2_pp1_4c(256) <= tidn ; --wr_csa32 + csa1_4_256: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(256) ,--i-- + b => ex2_pp0_12(256) ,--i-- + c => ex2_pp0_13(256) ,--i-- + sum => ex2_pp1_4s(256) ,--o-- + car => ex2_pp1_4c(255) );--o-- + csa1_4_255: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_12(255) ,--i-- + b => ex2_pp0_13(255) ,--i-- + sum => ex2_pp1_4s(255) ,--o-- + car => ex2_pp1_4c(254) );--o-- + csa1_4_254: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(254) ,--i-- + b => ex2_pp0_12(254) ,--i-- + c => ex2_pp0_13(254) ,--i-- + sum => ex2_pp1_4s(254) ,--o-- + car => ex2_pp1_4c(253) );--o-- + csa1_4_253: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(253) ,--i-- + b => ex2_pp0_12(253) ,--i-- + c => ex2_pp0_13(253) ,--i-- + sum => ex2_pp1_4s(253) ,--o-- + car => ex2_pp1_4c(252) );--o-- + csa1_4_252: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(252) ,--i-- + b => ex2_pp0_12(252) ,--i-- + c => ex2_pp0_13(252) ,--i-- + sum => ex2_pp1_4s(252) ,--o-- + car => ex2_pp1_4c(251) );--o-- + csa1_4_251: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(251) ,--i-- + b => ex2_pp0_12(251) ,--i-- + c => ex2_pp0_13(251) ,--i-- + sum => ex2_pp1_4s(251) ,--o-- + car => ex2_pp1_4c(250) );--o-- + csa1_4_250: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(250) ,--i-- + b => ex2_pp0_12(250) ,--i-- + c => ex2_pp0_13(250) ,--i-- + sum => ex2_pp1_4s(250) ,--o-- + car => ex2_pp1_4c(249) );--o-- + csa1_4_249: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(249) ,--i-- + b => ex2_pp0_12(249) ,--i-- + c => ex2_pp0_13(249) ,--i-- + sum => ex2_pp1_4s(249) ,--o-- + car => ex2_pp1_4c(248) );--o-- + csa1_4_248: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(248) ,--i-- + b => ex2_pp0_12(248) ,--i-- + c => ex2_pp0_13(248) ,--i-- + sum => ex2_pp1_4s(248) ,--o-- + car => ex2_pp1_4c(247) );--o-- + csa1_4_247: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(247) ,--i-- + b => ex2_pp0_12(247) ,--i-- + c => ex2_pp0_13(247) ,--i-- + sum => ex2_pp1_4s(247) ,--o-- + car => ex2_pp1_4c(246) );--o-- + csa1_4_246: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(246) ,--i-- + b => ex2_pp0_12(246) ,--i-- + c => ex2_pp0_13(246) ,--i-- + sum => ex2_pp1_4s(246) ,--o-- + car => ex2_pp1_4c(245) );--o-- + csa1_4_245: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(245) ,--i-- + b => ex2_pp0_12(245) ,--i-- + c => ex2_pp0_13(245) ,--i-- + sum => ex2_pp1_4s(245) ,--o-- + car => ex2_pp1_4c(244) );--o-- + csa1_4_244: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(244) ,--i-- + b => ex2_pp0_12(244) ,--i-- + c => ex2_pp0_13(244) ,--i-- + sum => ex2_pp1_4s(244) ,--o-- + car => ex2_pp1_4c(243) );--o-- + csa1_4_243: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(243) ,--i-- + b => ex2_pp0_12(243) ,--i-- + c => ex2_pp0_13(243) ,--i-- + sum => ex2_pp1_4s(243) ,--o-- + car => ex2_pp1_4c(242) );--o-- + csa1_4_242: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(242) ,--i-- + b => ex2_pp0_12(242) ,--i-- + c => ex2_pp0_13(242) ,--i-- + sum => ex2_pp1_4s(242) ,--o-- + car => ex2_pp1_4c(241) );--o-- + csa1_4_241: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(241) ,--i-- + b => ex2_pp0_12(241) ,--i-- + c => ex2_pp0_13(241) ,--i-- + sum => ex2_pp1_4s(241) ,--o-- + car => ex2_pp1_4c(240) );--o-- + csa1_4_240: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(240) ,--i-- + b => ex2_pp0_12(240) ,--i-- + c => ex2_pp0_13(240) ,--i-- + sum => ex2_pp1_4s(240) ,--o-- + car => ex2_pp1_4c(239) );--o-- + csa1_4_239: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(239) ,--i-- + b => ex2_pp0_12(239) ,--i-- + c => ex2_pp0_13(239) ,--i-- + sum => ex2_pp1_4s(239) ,--o-- + car => ex2_pp1_4c(238) );--o-- + csa1_4_238: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(238) ,--i-- + b => ex2_pp0_12(238) ,--i-- + c => ex2_pp0_13(238) ,--i-- + sum => ex2_pp1_4s(238) ,--o-- + car => ex2_pp1_4c(237) );--o-- + csa1_4_237: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(237) ,--i-- + b => ex2_pp0_12(237) ,--i-- + c => ex2_pp0_13(237) ,--i-- + sum => ex2_pp1_4s(237) ,--o-- + car => ex2_pp1_4c(236) );--o-- + csa1_4_236: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(236) ,--i-- + b => ex2_pp0_12(236) ,--i-- + c => ex2_pp0_13(236) ,--i-- + sum => ex2_pp1_4s(236) ,--o-- + car => ex2_pp1_4c(235) );--o-- + csa1_4_235: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(235) ,--i-- + b => ex2_pp0_12(235) ,--i-- + c => ex2_pp0_13(235) ,--i-- + sum => ex2_pp1_4s(235) ,--o-- + car => ex2_pp1_4c(234) );--o-- + csa1_4_234: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(234) ,--i-- + b => ex2_pp0_12(234) ,--i-- + c => ex2_pp0_13(234) ,--i-- + sum => ex2_pp1_4s(234) ,--o-- + car => ex2_pp1_4c(233) );--o-- + csa1_4_233: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(233) ,--i-- + b => ex2_pp0_12(233) ,--i-- + c => ex2_pp0_13(233) ,--i-- + sum => ex2_pp1_4s(233) ,--o-- + car => ex2_pp1_4c(232) );--o-- + csa1_4_232: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(232) ,--i-- + b => ex2_pp0_12(232) ,--i-- + c => ex2_pp0_13(232) ,--i-- + sum => ex2_pp1_4s(232) ,--o-- + car => ex2_pp1_4c(231) );--o-- + csa1_4_231: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(231) ,--i-- + b => ex2_pp0_12(231) ,--i-- + c => ex2_pp0_13(231) ,--i-- + sum => ex2_pp1_4s(231) ,--o-- + car => ex2_pp1_4c(230) );--o-- + csa1_4_230: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(230) ,--i-- + b => ex2_pp0_12(230) ,--i-- + c => ex2_pp0_13(230) ,--i-- + sum => ex2_pp1_4s(230) ,--o-- + car => ex2_pp1_4c(229) );--o-- + csa1_4_229: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(229) ,--i-- + b => ex2_pp0_12(229) ,--i-- + c => ex2_pp0_13(229) ,--i-- + sum => ex2_pp1_4s(229) ,--o-- + car => ex2_pp1_4c(228) );--o-- + csa1_4_228: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(228) ,--i-- + b => ex2_pp0_12(228) ,--i-- + c => ex2_pp0_13(228) ,--i-- + sum => ex2_pp1_4s(228) ,--o-- + car => ex2_pp1_4c(227) );--o-- + csa1_4_227: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(227) ,--i-- + b => ex2_pp0_12(227) ,--i-- + c => ex2_pp0_13(227) ,--i-- + sum => ex2_pp1_4s(227) ,--o-- + car => ex2_pp1_4c(226) );--o-- + csa1_4_226: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(226) ,--i-- + b => ex2_pp0_12(226) ,--i-- + c => ex2_pp0_13(226) ,--i-- + sum => ex2_pp1_4s(226) ,--o-- + car => ex2_pp1_4c(225) );--o-- + csa1_4_225: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(225) ,--i-- + b => ex2_pp0_12(225) ,--i-- + c => ex2_pp0_13(225) ,--i-- + sum => ex2_pp1_4s(225) ,--o-- + car => ex2_pp1_4c(224) );--o-- + csa1_4_224: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_11(224) ,--i-- + b => ex2_pp0_12(224) ,--i-- + c => ex2_pp0_13(224) ,--i-- + sum => ex2_pp1_4s(224) ,--o-- + car => ex2_pp1_4c(223) );--o-- + csa1_4_223: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_11(223) ,--i-- + b => ex2_pp0_12(223) ,--i-- + sum => ex2_pp1_4s(223) ,--o-- + car => ex2_pp1_4c(222) );--o-- + csa1_4_222: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_11(222) ,--i-- + b => ex2_pp0_12(222) ,--i-- + sum => ex2_pp1_4s(222) ,--o-- + car => ex2_pp1_4c(221) );--o-- + ex2_pp1_4s(221) <= ex2_pp0_11(221) ; --pass_x_s + ex2_pp1_4s(220) <= ex2_pp0_11(220) ; --pass_s + + + ------- ----- + + ex2_pp1_5c(264) <= ex2_pp0_16(264) ; --pass_cs + ex2_pp1_5s(264) <= ex2_pp0_15(264) ; --pass_cs + ex2_pp1_5c(263) <= tidn ; --pass_s + ex2_pp1_5s(263) <= ex2_pp0_16(263) ; --pass_s + ex2_pp1_5c(262) <= tidn ; --wr_csa32 + csa1_5_262: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(262) ,--i-- + b => ex2_pp0_15(262) ,--i-- + c => ex2_pp0_16(262) ,--i-- + sum => ex2_pp1_5s(262) ,--o-- + car => ex2_pp1_5c(261) );--o-- + csa1_5_261: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_15(261) ,--i-- + b => ex2_pp0_16(261) ,--i-- + sum => ex2_pp1_5s(261) ,--o-- + car => ex2_pp1_5c(260) );--o-- + csa1_5_260: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(260) ,--i-- + b => ex2_pp0_15(260) ,--i-- + c => ex2_pp0_16(260) ,--i-- + sum => ex2_pp1_5s(260) ,--o-- + car => ex2_pp1_5c(259) );--o-- + csa1_5_259: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(259) ,--i-- + b => ex2_pp0_15(259) ,--i-- + c => ex2_pp0_16(259) ,--i-- + sum => ex2_pp1_5s(259) ,--o-- + car => ex2_pp1_5c(258) );--o-- + csa1_5_258: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(258) ,--i-- + b => ex2_pp0_15(258) ,--i-- + c => ex2_pp0_16(258) ,--i-- + sum => ex2_pp1_5s(258) ,--o-- + car => ex2_pp1_5c(257) );--o-- + csa1_5_257: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(257) ,--i-- + b => ex2_pp0_15(257) ,--i-- + c => ex2_pp0_16(257) ,--i-- + sum => ex2_pp1_5s(257) ,--o-- + car => ex2_pp1_5c(256) );--o-- + csa1_5_256: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(256) ,--i-- + b => ex2_pp0_15(256) ,--i-- + c => ex2_pp0_16(256) ,--i-- + sum => ex2_pp1_5s(256) ,--o-- + car => ex2_pp1_5c(255) );--o-- + csa1_5_255: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(255) ,--i-- + b => ex2_pp0_15(255) ,--i-- + c => ex2_pp0_16(255) ,--i-- + sum => ex2_pp1_5s(255) ,--o-- + car => ex2_pp1_5c(254) );--o-- + csa1_5_254: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(254) ,--i-- + b => ex2_pp0_15(254) ,--i-- + c => ex2_pp0_16(254) ,--i-- + sum => ex2_pp1_5s(254) ,--o-- + car => ex2_pp1_5c(253) );--o-- + csa1_5_253: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(253) ,--i-- + b => ex2_pp0_15(253) ,--i-- + c => ex2_pp0_16(253) ,--i-- + sum => ex2_pp1_5s(253) ,--o-- + car => ex2_pp1_5c(252) );--o-- + csa1_5_252: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(252) ,--i-- + b => ex2_pp0_15(252) ,--i-- + c => ex2_pp0_16(252) ,--i-- + sum => ex2_pp1_5s(252) ,--o-- + car => ex2_pp1_5c(251) );--o-- + csa1_5_251: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(251) ,--i-- + b => ex2_pp0_15(251) ,--i-- + c => ex2_pp0_16(251) ,--i-- + sum => ex2_pp1_5s(251) ,--o-- + car => ex2_pp1_5c(250) );--o-- + csa1_5_250: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(250) ,--i-- + b => ex2_pp0_15(250) ,--i-- + c => ex2_pp0_16(250) ,--i-- + sum => ex2_pp1_5s(250) ,--o-- + car => ex2_pp1_5c(249) );--o-- + csa1_5_249: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(249) ,--i-- + b => ex2_pp0_15(249) ,--i-- + c => ex2_pp0_16(249) ,--i-- + sum => ex2_pp1_5s(249) ,--o-- + car => ex2_pp1_5c(248) );--o-- + csa1_5_248: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(248) ,--i-- + b => ex2_pp0_15(248) ,--i-- + c => ex2_pp0_16(248) ,--i-- + sum => ex2_pp1_5s(248) ,--o-- + car => ex2_pp1_5c(247) );--o-- + csa1_5_247: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(247) ,--i-- + b => ex2_pp0_15(247) ,--i-- + c => ex2_pp0_16(247) ,--i-- + sum => ex2_pp1_5s(247) ,--o-- + car => ex2_pp1_5c(246) );--o-- + csa1_5_246: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(246) ,--i-- + b => ex2_pp0_15(246) ,--i-- + c => ex2_pp0_16(246) ,--i-- + sum => ex2_pp1_5s(246) ,--o-- + car => ex2_pp1_5c(245) );--o-- + csa1_5_245: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(245) ,--i-- + b => ex2_pp0_15(245) ,--i-- + c => ex2_pp0_16(245) ,--i-- + sum => ex2_pp1_5s(245) ,--o-- + car => ex2_pp1_5c(244) );--o-- + csa1_5_244: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(244) ,--i-- + b => ex2_pp0_15(244) ,--i-- + c => ex2_pp0_16(244) ,--i-- + sum => ex2_pp1_5s(244) ,--o-- + car => ex2_pp1_5c(243) );--o-- + csa1_5_243: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(243) ,--i-- + b => ex2_pp0_15(243) ,--i-- + c => ex2_pp0_16(243) ,--i-- + sum => ex2_pp1_5s(243) ,--o-- + car => ex2_pp1_5c(242) );--o-- + csa1_5_242: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(242) ,--i-- + b => ex2_pp0_15(242) ,--i-- + c => ex2_pp0_16(242) ,--i-- + sum => ex2_pp1_5s(242) ,--o-- + car => ex2_pp1_5c(241) );--o-- + csa1_5_241: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(241) ,--i-- + b => ex2_pp0_15(241) ,--i-- + c => ex2_pp0_16(241) ,--i-- + sum => ex2_pp1_5s(241) ,--o-- + car => ex2_pp1_5c(240) );--o-- + csa1_5_240: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(240) ,--i-- + b => ex2_pp0_15(240) ,--i-- + c => ex2_pp0_16(240) ,--i-- + sum => ex2_pp1_5s(240) ,--o-- + car => ex2_pp1_5c(239) );--o-- + csa1_5_239: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(239) ,--i-- + b => ex2_pp0_15(239) ,--i-- + c => ex2_pp0_16(239) ,--i-- + sum => ex2_pp1_5s(239) ,--o-- + car => ex2_pp1_5c(238) );--o-- + csa1_5_238: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(238) ,--i-- + b => ex2_pp0_15(238) ,--i-- + c => ex2_pp0_16(238) ,--i-- + sum => ex2_pp1_5s(238) ,--o-- + car => ex2_pp1_5c(237) );--o-- + csa1_5_237: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(237) ,--i-- + b => ex2_pp0_15(237) ,--i-- + c => ex2_pp0_16(237) ,--i-- + sum => ex2_pp1_5s(237) ,--o-- + car => ex2_pp1_5c(236) );--o-- + csa1_5_236: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(236) ,--i-- + b => ex2_pp0_15(236) ,--i-- + c => ex2_pp0_16(236) ,--i-- + sum => ex2_pp1_5s(236) ,--o-- + car => ex2_pp1_5c(235) );--o-- + csa1_5_235: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(235) ,--i-- + b => ex2_pp0_15(235) ,--i-- + c => ex2_pp0_16(235) ,--i-- + sum => ex2_pp1_5s(235) ,--o-- + car => ex2_pp1_5c(234) );--o-- + csa1_5_234: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(234) ,--i-- + b => ex2_pp0_15(234) ,--i-- + c => ex2_pp0_16(234) ,--i-- + sum => ex2_pp1_5s(234) ,--o-- + car => ex2_pp1_5c(233) );--o-- + csa1_5_233: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(233) ,--i-- + b => ex2_pp0_15(233) ,--i-- + c => ex2_pp0_16(233) ,--i-- + sum => ex2_pp1_5s(233) ,--o-- + car => ex2_pp1_5c(232) );--o-- + csa1_5_232: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(232) ,--i-- + b => ex2_pp0_15(232) ,--i-- + c => ex2_pp0_16(232) ,--i-- + sum => ex2_pp1_5s(232) ,--o-- + car => ex2_pp1_5c(231) );--o-- + csa1_5_231: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(231) ,--i-- + b => ex2_pp0_15(231) ,--i-- + c => ex2_pp0_16(231) ,--i-- + sum => ex2_pp1_5s(231) ,--o-- + car => ex2_pp1_5c(230) );--o-- + csa1_5_230: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(230) ,--i-- + b => ex2_pp0_15(230) ,--i-- + c => ex2_pp0_16(230) ,--i-- + sum => ex2_pp1_5s(230) ,--o-- + car => ex2_pp1_5c(229) );--o-- + csa1_5_229: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp0_14(229) ,--i-- + b => ex2_pp0_15(229) ,--i-- + c => ex2_pp0_16(229) ,--i-- + sum => ex2_pp1_5s(229) ,--o-- + car => ex2_pp1_5c(228) );--o-- + csa1_5_228: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp0_14(228) ,--i-- + b => ex2_pp0_15(228) ,--i-- + sum => ex2_pp1_5s(228) ,--o-- + car => ex2_pp1_5c(227) );--o-- + ex2_pp1_5s(227) <= ex2_pp0_14(227) ; --pass_x_s + ex2_pp1_5s(226) <= ex2_pp0_14(226) ; --pass_s + + + + --*********************************** + --** compression level 2 + --*********************************** + + -- g2 : for i in 196 to 264 generate + + -- csa2_0: entity work.c_prism_csa42 generic map( btr => "MLT42_X1_A12TH" ) port map( + -- a => ex2_pp1_0s(i) ,--i-- + -- b => ex2_pp1_0c(i) ,--i-- + -- c => ex2_pp1_1s(i) ,--i-- + -- d => ex2_pp1_1c(i) ,--i-- + -- ki => ex2_pp2_0k(i) ,--i-- + -- ko => ex2_pp2_0k(i - 1) ,--o-- + -- sum => ex2_pp2_0s(i) ,--o-- + -- car => ex2_pp2_0c(i - 1) );--o-- + -- + -- csa2_1: entity work.c_prism_csa42 generic map( btr => "MLT42_X1_A12TH" ) port map( + -- a => ex2_pp1_2s(i) ,--i-- + -- b => ex2_pp1_2c(i) ,--i-- + -- c => ex2_pp1_3s(i) ,--i-- + -- d => ex2_pp1_3c(i) ,--i-- + -- ki => ex2_pp2_1k(i) ,--i-- + -- ko => ex2_pp2_1k(i - 1) ,--o-- + -- sum => ex2_pp2_1s(i) ,--o-- + -- car => ex2_pp2_1c(i - 1) );--o-- + -- + -- csa2_2: entity work.c_prism_csa42 generic map( btr => "MLT42_X1_A12TH" ) port map( + -- a => ex2_pp1_4s(i) ,--i-- + -- b => ex2_pp1_4c(i) ,--i-- + -- c => ex2_pp1_5s(i) ,--i-- + -- d => ex2_pp1_5c(i) ,--i-- + -- ki => ex2_pp2_2k(i) ,--i-- + -- ko => ex2_pp2_2k(i - 1) ,--o-- + -- sum => ex2_pp2_2s(i) ,--o-- + -- car => ex2_pp2_2c(i - 1) );--o-- + -- + -- end generate; + + + ------- ----- + + ex2_pp2_0s(242) <= ex2_pp1_1s(242) ; --pass_s + ex2_pp2_0s(241) <= tidn ; --pass_none + ex2_pp2_0c(240) <= ex2_pp1_1s(240) ; --pass_cs + ex2_pp2_0s(240) <= ex2_pp1_1c(240) ; --pass_cs + ex2_pp2_0c(239) <= tidn ; --pass_s + ex2_pp2_0s(239) <= ex2_pp1_1s(239) ; --pass_s + ex2_pp2_0c(238) <= tidn ; --pass_s + ex2_pp2_0s(238) <= ex2_pp1_1s(238) ; --pass_s + ex2_pp2_0c(237) <= ex2_pp1_1s(237) ; --pass_cs + ex2_pp2_0s(237) <= ex2_pp1_1c(237) ; --pass_cs + ex2_pp2_0c(236) <= tidn ; --wr_csa32 + csa2_0_236: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0s(236) ,--i-- + b => ex2_pp1_1c(236) ,--i-- + c => ex2_pp1_1s(236) ,--i-- + sum => ex2_pp2_0s(236) ,--o-- + car => ex2_pp2_0c(235) );--o-- + csa2_0_235: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp1_1c(235) ,--i-- + b => ex2_pp1_1s(235) ,--i-- + sum => ex2_pp2_0s(235) ,--o-- + car => ex2_pp2_0c(234) );--o-- + ex2_pp2_0k(234) <= tidn ; --start_k + csa2_0_234: entity clib.c_prism_csa42 port map( -- MLT42_X1_A12TH + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(234) ,--i-- + b => ex2_pp1_0s(234) ,--i-- + c => ex2_pp1_1c(234) ,--i-- + d => ex2_pp1_1s(234) ,--i-- + ki => ex2_pp2_0k(234) ,--i-- + ko => ex2_pp2_0k(233) ,--o-- + sum => ex2_pp2_0s(234) ,--o-- + car => ex2_pp2_0c(233) );--o-- + csa2_0_233: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0s(233) ,--i-- + b => ex2_pp1_1c(233) ,--i-- + c => ex2_pp1_1s(233) ,--i-- + d => tidn ,--i-- + ki => ex2_pp2_0k(233) ,--i-- + ko => ex2_pp2_0k(232) ,--o-- + sum => ex2_pp2_0s(233) ,--o-- + car => ex2_pp2_0c(232) );--o-- + csa2_0_232: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0s(232) ,--i-- + b => ex2_pp1_1c(232) ,--i-- + c => ex2_pp1_1s(232) ,--i-- + d => tidn ,--i-- + ki => ex2_pp2_0k(232) ,--i-- + ko => ex2_pp2_0k(231) ,--o-- + sum => ex2_pp2_0s(232) ,--o-- + car => ex2_pp2_0c(231) );--o-- + csa2_0_231: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(231) ,--i-- + b => ex2_pp1_0s(231) ,--i-- + c => ex2_pp1_1c(231) ,--i-- + d => ex2_pp1_1s(231) ,--i-- + ki => ex2_pp2_0k(231) ,--i-- + ko => ex2_pp2_0k(230) ,--o-- + sum => ex2_pp2_0s(231) ,--o-- + car => ex2_pp2_0c(230) );--o-- + csa2_0_230: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(230) ,--i-- + b => ex2_pp1_0s(230) ,--i-- + c => ex2_pp1_1c(230) ,--i-- + d => ex2_pp1_1s(230) ,--i-- + ki => ex2_pp2_0k(230) ,--i-- + ko => ex2_pp2_0k(229) ,--o-- + sum => ex2_pp2_0s(230) ,--o-- + car => ex2_pp2_0c(229) );--o-- + csa2_0_229: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(229) ,--i-- + b => ex2_pp1_0s(229) ,--i-- + c => ex2_pp1_1c(229) ,--i-- + d => ex2_pp1_1s(229) ,--i-- + ki => ex2_pp2_0k(229) ,--i-- + ko => ex2_pp2_0k(228) ,--o-- + sum => ex2_pp2_0s(229) ,--o-- + car => ex2_pp2_0c(228) );--o-- + csa2_0_228: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(228) ,--i-- + b => ex2_pp1_0s(228) ,--i-- + c => ex2_pp1_1c(228) ,--i-- + d => ex2_pp1_1s(228) ,--i-- + ki => ex2_pp2_0k(228) ,--i-- + ko => ex2_pp2_0k(227) ,--o-- + sum => ex2_pp2_0s(228) ,--o-- + car => ex2_pp2_0c(227) );--o-- + csa2_0_227: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(227) ,--i-- + b => ex2_pp1_0s(227) ,--i-- + c => ex2_pp1_1c(227) ,--i-- + d => ex2_pp1_1s(227) ,--i-- + ki => ex2_pp2_0k(227) ,--i-- + ko => ex2_pp2_0k(226) ,--o-- + sum => ex2_pp2_0s(227) ,--o-- + car => ex2_pp2_0c(226) );--o-- + csa2_0_226: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(226) ,--i-- + b => ex2_pp1_0s(226) ,--i-- + c => ex2_pp1_1c(226) ,--i-- + d => ex2_pp1_1s(226) ,--i-- + ki => ex2_pp2_0k(226) ,--i-- + ko => ex2_pp2_0k(225) ,--o-- + sum => ex2_pp2_0s(226) ,--o-- + car => ex2_pp2_0c(225) );--o-- + csa2_0_225: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(225) ,--i-- + b => ex2_pp1_0s(225) ,--i-- + c => ex2_pp1_1c(225) ,--i-- + d => ex2_pp1_1s(225) ,--i-- + ki => ex2_pp2_0k(225) ,--i-- + ko => ex2_pp2_0k(224) ,--o-- + sum => ex2_pp2_0s(225) ,--o-- + car => ex2_pp2_0c(224) );--o-- + csa2_0_224: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(224) ,--i-- + b => ex2_pp1_0s(224) ,--i-- + c => ex2_pp1_1c(224) ,--i-- + d => ex2_pp1_1s(224) ,--i-- + ki => ex2_pp2_0k(224) ,--i-- + ko => ex2_pp2_0k(223) ,--o-- + sum => ex2_pp2_0s(224) ,--o-- + car => ex2_pp2_0c(223) );--o-- + csa2_0_223: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(223) ,--i-- + b => ex2_pp1_0s(223) ,--i-- + c => ex2_pp1_1c(223) ,--i-- + d => ex2_pp1_1s(223) ,--i-- + ki => ex2_pp2_0k(223) ,--i-- + ko => ex2_pp2_0k(222) ,--o-- + sum => ex2_pp2_0s(223) ,--o-- + car => ex2_pp2_0c(222) );--o-- + csa2_0_222: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(222) ,--i-- + b => ex2_pp1_0s(222) ,--i-- + c => ex2_pp1_1c(222) ,--i-- + d => ex2_pp1_1s(222) ,--i-- + ki => ex2_pp2_0k(222) ,--i-- + ko => ex2_pp2_0k(221) ,--o-- + sum => ex2_pp2_0s(222) ,--o-- + car => ex2_pp2_0c(221) );--o-- + csa2_0_221: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(221) ,--i-- + b => ex2_pp1_0s(221) ,--i-- + c => ex2_pp1_1c(221) ,--i-- + d => ex2_pp1_1s(221) ,--i-- + ki => ex2_pp2_0k(221) ,--i-- + ko => ex2_pp2_0k(220) ,--o-- + sum => ex2_pp2_0s(221) ,--o-- + car => ex2_pp2_0c(220) );--o-- + csa2_0_220: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(220) ,--i-- + b => ex2_pp1_0s(220) ,--i-- + c => ex2_pp1_1c(220) ,--i-- + d => ex2_pp1_1s(220) ,--i-- + ki => ex2_pp2_0k(220) ,--i-- + ko => ex2_pp2_0k(219) ,--o-- + sum => ex2_pp2_0s(220) ,--o-- + car => ex2_pp2_0c(219) );--o-- + csa2_0_219: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(219) ,--i-- + b => ex2_pp1_0s(219) ,--i-- + c => ex2_pp1_1c(219) ,--i-- + d => ex2_pp1_1s(219) ,--i-- + ki => ex2_pp2_0k(219) ,--i-- + ko => ex2_pp2_0k(218) ,--o-- + sum => ex2_pp2_0s(219) ,--o-- + car => ex2_pp2_0c(218) );--o-- + csa2_0_218: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(218) ,--i-- + b => ex2_pp1_0s(218) ,--i-- + c => ex2_pp1_1c(218) ,--i-- + d => ex2_pp1_1s(218) ,--i-- + ki => ex2_pp2_0k(218) ,--i-- + ko => ex2_pp2_0k(217) ,--o-- + sum => ex2_pp2_0s(218) ,--o-- + car => ex2_pp2_0c(217) );--o-- + csa2_0_217: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(217) ,--i-- + b => ex2_pp1_0s(217) ,--i-- + c => ex2_pp1_1c(217) ,--i-- + d => ex2_pp1_1s(217) ,--i-- + ki => ex2_pp2_0k(217) ,--i-- + ko => ex2_pp2_0k(216) ,--o-- + sum => ex2_pp2_0s(217) ,--o-- + car => ex2_pp2_0c(216) );--o-- + csa2_0_216: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(216) ,--i-- + b => ex2_pp1_0s(216) ,--i-- + c => ex2_pp1_1c(216) ,--i-- + d => ex2_pp1_1s(216) ,--i-- + ki => ex2_pp2_0k(216) ,--i-- + ko => ex2_pp2_0k(215) ,--o-- + sum => ex2_pp2_0s(216) ,--o-- + car => ex2_pp2_0c(215) );--o-- + csa2_0_215: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(215) ,--i-- + b => ex2_pp1_0s(215) ,--i-- + c => ex2_pp1_1c(215) ,--i-- + d => ex2_pp1_1s(215) ,--i-- + ki => ex2_pp2_0k(215) ,--i-- + ko => ex2_pp2_0k(214) ,--o-- + sum => ex2_pp2_0s(215) ,--o-- + car => ex2_pp2_0c(214) );--o-- + csa2_0_214: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(214) ,--i-- + b => ex2_pp1_0s(214) ,--i-- + c => ex2_pp1_1c(214) ,--i-- + d => ex2_pp1_1s(214) ,--i-- + ki => ex2_pp2_0k(214) ,--i-- + ko => ex2_pp2_0k(213) ,--o-- + sum => ex2_pp2_0s(214) ,--o-- + car => ex2_pp2_0c(213) );--o-- + csa2_0_213: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(213) ,--i-- + b => ex2_pp1_0s(213) ,--i-- + c => ex2_pp1_1c(213) ,--i-- + d => ex2_pp1_1s(213) ,--i-- + ki => ex2_pp2_0k(213) ,--i-- + ko => ex2_pp2_0k(212) ,--o-- + sum => ex2_pp2_0s(213) ,--o-- + car => ex2_pp2_0c(212) );--o-- + csa2_0_212: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(212) ,--i-- + b => ex2_pp1_0s(212) ,--i-- + c => ex2_pp1_1c(212) ,--i-- + d => ex2_pp1_1s(212) ,--i-- + ki => ex2_pp2_0k(212) ,--i-- + ko => ex2_pp2_0k(211) ,--o-- + sum => ex2_pp2_0s(212) ,--o-- + car => ex2_pp2_0c(211) );--o-- + csa2_0_211: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(211) ,--i-- + b => ex2_pp1_0s(211) ,--i-- + c => ex2_pp1_1c(211) ,--i-- + d => ex2_pp1_1s(211) ,--i-- + ki => ex2_pp2_0k(211) ,--i-- + ko => ex2_pp2_0k(210) ,--o-- + sum => ex2_pp2_0s(211) ,--o-- + car => ex2_pp2_0c(210) );--o-- + csa2_0_210: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(210) ,--i-- + b => ex2_pp1_0s(210) ,--i-- + c => ex2_pp1_1c(210) ,--i-- + d => ex2_pp1_1s(210) ,--i-- + ki => ex2_pp2_0k(210) ,--i-- + ko => ex2_pp2_0k(209) ,--o-- + sum => ex2_pp2_0s(210) ,--o-- + car => ex2_pp2_0c(209) );--o-- + csa2_0_209: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(209) ,--i-- + b => ex2_pp1_0s(209) ,--i-- + c => ex2_pp1_1c(209) ,--i-- + d => ex2_pp1_1s(209) ,--i-- + ki => ex2_pp2_0k(209) ,--i-- + ko => ex2_pp2_0k(208) ,--o-- + sum => ex2_pp2_0s(209) ,--o-- + car => ex2_pp2_0c(208) );--o-- + csa2_0_208: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(208) ,--i-- + b => ex2_pp1_0s(208) ,--i-- + c => ex2_pp1_1c(208) ,--i-- + d => ex2_pp1_1s(208) ,--i-- + ki => ex2_pp2_0k(208) ,--i-- + ko => ex2_pp2_0k(207) ,--o-- + sum => ex2_pp2_0s(208) ,--o-- + car => ex2_pp2_0c(207) );--o-- + csa2_0_207: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(207) ,--i-- + b => ex2_pp1_0s(207) ,--i-- + c => ex2_pp1_1c(207) ,--i-- + d => ex2_pp1_1s(207) ,--i-- + ki => ex2_pp2_0k(207) ,--i-- + ko => ex2_pp2_0k(206) ,--o-- + sum => ex2_pp2_0s(207) ,--o-- + car => ex2_pp2_0c(206) );--o-- + csa2_0_206: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(206) ,--i-- + b => ex2_pp1_0s(206) ,--i-- + c => ex2_pp1_1c(206) ,--i-- + d => ex2_pp1_1s(206) ,--i-- + ki => ex2_pp2_0k(206) ,--i-- + ko => ex2_pp2_0k(205) ,--o-- + sum => ex2_pp2_0s(206) ,--o-- + car => ex2_pp2_0c(205) );--o-- + csa2_0_205: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(205) ,--i-- + b => ex2_pp1_0s(205) ,--i-- + c => ex2_pp1_1c(205) ,--i-- + d => ex2_pp1_1s(205) ,--i-- + ki => ex2_pp2_0k(205) ,--i-- + ko => ex2_pp2_0k(204) ,--o-- + sum => ex2_pp2_0s(205) ,--o-- + car => ex2_pp2_0c(204) );--o-- + csa2_0_204: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(204) ,--i-- + b => ex2_pp1_0s(204) ,--i-- + c => ex2_pp1_1c(204) ,--i-- + d => ex2_pp1_1s(204) ,--i-- + ki => ex2_pp2_0k(204) ,--i-- + ko => ex2_pp2_0k(203) ,--o-- + sum => ex2_pp2_0s(204) ,--o-- + car => ex2_pp2_0c(203) );--o-- + csa2_0_203: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(203) ,--i-- + b => ex2_pp1_0s(203) ,--i-- + c => ex2_pp1_1c(203) ,--i-- + d => ex2_pp1_1s(203) ,--i-- + ki => ex2_pp2_0k(203) ,--i-- + ko => ex2_pp2_0k(202) ,--o-- + sum => ex2_pp2_0s(203) ,--o-- + car => ex2_pp2_0c(202) );--o-- + csa2_0_202: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(202) ,--i-- + b => ex2_pp1_0s(202) ,--i-- + c => ex2_pp1_1s(202) ,--i-- + d => tidn ,--i-- + ki => ex2_pp2_0k(202) ,--i-- + ko => ex2_pp2_0k(201) ,--o-- + sum => ex2_pp2_0s(202) ,--o-- + car => ex2_pp2_0c(201) );--o-- + csa2_0_201: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_0c(201) ,--i-- + b => ex2_pp1_0s(201) ,--i-- + c => ex2_pp2_0k(201) ,--i-- + sum => ex2_pp2_0s(201) ,--o-- + car => ex2_pp2_0c(200) );--o-- + csa2_0_200: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp1_0c(200) ,--i-- + b => ex2_pp1_0s(200) ,--i-- + sum => ex2_pp2_0s(200) ,--o-- + car => ex2_pp2_0c(199) );--o-- + csa2_0_199: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp1_0c(199) ,--i-- + b => ex2_pp1_0s(199) ,--i-- + sum => ex2_pp2_0s(199) ,--o-- + car => ex2_pp2_0c(198) );--o-- + ex2_pp2_0s(198) <= ex2_pp1_0s(198) ; --pass_x_s + + + ------- ----- + + ex2_pp2_1s(254) <= ex2_pp1_3s(254) ; --pass_s + ex2_pp2_1s(253) <= tidn ; --pass_none + ex2_pp2_1c(252) <= ex2_pp1_3s(252) ; --pass_cs + ex2_pp2_1s(252) <= ex2_pp1_3c(252) ; --pass_cs + ex2_pp2_1c(251) <= tidn ; --pass_s + ex2_pp2_1s(251) <= ex2_pp1_3s(251) ; --pass_s + ex2_pp2_1c(250) <= tidn ; --pass_s + ex2_pp2_1s(250) <= ex2_pp1_3s(250) ; --pass_s + ex2_pp2_1c(249) <= ex2_pp1_3s(249) ; --pass_cs + ex2_pp2_1s(249) <= ex2_pp1_3c(249) ; --pass_cs + ex2_pp2_1c(248) <= tidn ; --wr_csa32 + csa2_1_248: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2s(248) ,--i-- + b => ex2_pp1_3c(248) ,--i-- + c => ex2_pp1_3s(248) ,--i-- + sum => ex2_pp2_1s(248) ,--o-- + car => ex2_pp2_1c(247) );--o-- + csa2_1_247: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp1_3c(247) ,--i-- + b => ex2_pp1_3s(247) ,--i-- + sum => ex2_pp2_1s(247) ,--o-- + car => ex2_pp2_1c(246) );--o-- + ex2_pp2_1k(246) <= tidn ; --start_k + csa2_1_246: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(246) ,--i-- + b => ex2_pp1_2s(246) ,--i-- + c => ex2_pp1_3c(246) ,--i-- + d => ex2_pp1_3s(246) ,--i-- + ki => ex2_pp2_1k(246) ,--i-- + ko => ex2_pp2_1k(245) ,--o-- + sum => ex2_pp2_1s(246) ,--o-- + car => ex2_pp2_1c(245) );--o-- + csa2_1_245: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2s(245) ,--i-- + b => ex2_pp1_3c(245) ,--i-- + c => ex2_pp1_3s(245) ,--i-- + d => tidn ,--i-- + ki => ex2_pp2_1k(245) ,--i-- + ko => ex2_pp2_1k(244) ,--o-- + sum => ex2_pp2_1s(245) ,--o-- + car => ex2_pp2_1c(244) );--o-- + csa2_1_244: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2s(244) ,--i-- + b => ex2_pp1_3c(244) ,--i-- + c => ex2_pp1_3s(244) ,--i-- + d => tidn ,--i-- + ki => ex2_pp2_1k(244) ,--i-- + ko => ex2_pp2_1k(243) ,--o-- + sum => ex2_pp2_1s(244) ,--o-- + car => ex2_pp2_1c(243) );--o-- + csa2_1_243: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(243) ,--i-- + b => ex2_pp1_2s(243) ,--i-- + c => ex2_pp1_3c(243) ,--i-- + d => ex2_pp1_3s(243) ,--i-- + ki => ex2_pp2_1k(243) ,--i-- + ko => ex2_pp2_1k(242) ,--o-- + sum => ex2_pp2_1s(243) ,--o-- + car => ex2_pp2_1c(242) );--o-- + csa2_1_242: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(242) ,--i-- + b => ex2_pp1_2s(242) ,--i-- + c => ex2_pp1_3c(242) ,--i-- + d => ex2_pp1_3s(242) ,--i-- + ki => ex2_pp2_1k(242) ,--i-- + ko => ex2_pp2_1k(241) ,--o-- + sum => ex2_pp2_1s(242) ,--o-- + car => ex2_pp2_1c(241) );--o-- + csa2_1_241: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(241) ,--i-- + b => ex2_pp1_2s(241) ,--i-- + c => ex2_pp1_3c(241) ,--i-- + d => ex2_pp1_3s(241) ,--i-- + ki => ex2_pp2_1k(241) ,--i-- + ko => ex2_pp2_1k(240) ,--o-- + sum => ex2_pp2_1s(241) ,--o-- + car => ex2_pp2_1c(240) );--o-- + csa2_1_240: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(240) ,--i-- + b => ex2_pp1_2s(240) ,--i-- + c => ex2_pp1_3c(240) ,--i-- + d => ex2_pp1_3s(240) ,--i-- + ki => ex2_pp2_1k(240) ,--i-- + ko => ex2_pp2_1k(239) ,--o-- + sum => ex2_pp2_1s(240) ,--o-- + car => ex2_pp2_1c(239) );--o-- + csa2_1_239: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(239) ,--i-- + b => ex2_pp1_2s(239) ,--i-- + c => ex2_pp1_3c(239) ,--i-- + d => ex2_pp1_3s(239) ,--i-- + ki => ex2_pp2_1k(239) ,--i-- + ko => ex2_pp2_1k(238) ,--o-- + sum => ex2_pp2_1s(239) ,--o-- + car => ex2_pp2_1c(238) );--o-- + csa2_1_238: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(238) ,--i-- + b => ex2_pp1_2s(238) ,--i-- + c => ex2_pp1_3c(238) ,--i-- + d => ex2_pp1_3s(238) ,--i-- + ki => ex2_pp2_1k(238) ,--i-- + ko => ex2_pp2_1k(237) ,--o-- + sum => ex2_pp2_1s(238) ,--o-- + car => ex2_pp2_1c(237) );--o-- + csa2_1_237: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(237) ,--i-- + b => ex2_pp1_2s(237) ,--i-- + c => ex2_pp1_3c(237) ,--i-- + d => ex2_pp1_3s(237) ,--i-- + ki => ex2_pp2_1k(237) ,--i-- + ko => ex2_pp2_1k(236) ,--o-- + sum => ex2_pp2_1s(237) ,--o-- + car => ex2_pp2_1c(236) );--o-- + csa2_1_236: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(236) ,--i-- + b => ex2_pp1_2s(236) ,--i-- + c => ex2_pp1_3c(236) ,--i-- + d => ex2_pp1_3s(236) ,--i-- + ki => ex2_pp2_1k(236) ,--i-- + ko => ex2_pp2_1k(235) ,--o-- + sum => ex2_pp2_1s(236) ,--o-- + car => ex2_pp2_1c(235) );--o-- + csa2_1_235: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(235) ,--i-- + b => ex2_pp1_2s(235) ,--i-- + c => ex2_pp1_3c(235) ,--i-- + d => ex2_pp1_3s(235) ,--i-- + ki => ex2_pp2_1k(235) ,--i-- + ko => ex2_pp2_1k(234) ,--o-- + sum => ex2_pp2_1s(235) ,--o-- + car => ex2_pp2_1c(234) );--o-- + csa2_1_234: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(234) ,--i-- + b => ex2_pp1_2s(234) ,--i-- + c => ex2_pp1_3c(234) ,--i-- + d => ex2_pp1_3s(234) ,--i-- + ki => ex2_pp2_1k(234) ,--i-- + ko => ex2_pp2_1k(233) ,--o-- + sum => ex2_pp2_1s(234) ,--o-- + car => ex2_pp2_1c(233) );--o-- + csa2_1_233: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(233) ,--i-- + b => ex2_pp1_2s(233) ,--i-- + c => ex2_pp1_3c(233) ,--i-- + d => ex2_pp1_3s(233) ,--i-- + ki => ex2_pp2_1k(233) ,--i-- + ko => ex2_pp2_1k(232) ,--o-- + sum => ex2_pp2_1s(233) ,--o-- + car => ex2_pp2_1c(232) );--o-- + csa2_1_232: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(232) ,--i-- + b => ex2_pp1_2s(232) ,--i-- + c => ex2_pp1_3c(232) ,--i-- + d => ex2_pp1_3s(232) ,--i-- + ki => ex2_pp2_1k(232) ,--i-- + ko => ex2_pp2_1k(231) ,--o-- + sum => ex2_pp2_1s(232) ,--o-- + car => ex2_pp2_1c(231) );--o-- + csa2_1_231: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(231) ,--i-- + b => ex2_pp1_2s(231) ,--i-- + c => ex2_pp1_3c(231) ,--i-- + d => ex2_pp1_3s(231) ,--i-- + ki => ex2_pp2_1k(231) ,--i-- + ko => ex2_pp2_1k(230) ,--o-- + sum => ex2_pp2_1s(231) ,--o-- + car => ex2_pp2_1c(230) );--o-- + csa2_1_230: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(230) ,--i-- + b => ex2_pp1_2s(230) ,--i-- + c => ex2_pp1_3c(230) ,--i-- + d => ex2_pp1_3s(230) ,--i-- + ki => ex2_pp2_1k(230) ,--i-- + ko => ex2_pp2_1k(229) ,--o-- + sum => ex2_pp2_1s(230) ,--o-- + car => ex2_pp2_1c(229) );--o-- + csa2_1_229: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(229) ,--i-- + b => ex2_pp1_2s(229) ,--i-- + c => ex2_pp1_3c(229) ,--i-- + d => ex2_pp1_3s(229) ,--i-- + ki => ex2_pp2_1k(229) ,--i-- + ko => ex2_pp2_1k(228) ,--o-- + sum => ex2_pp2_1s(229) ,--o-- + car => ex2_pp2_1c(228) );--o-- + csa2_1_228: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(228) ,--i-- + b => ex2_pp1_2s(228) ,--i-- + c => ex2_pp1_3c(228) ,--i-- + d => ex2_pp1_3s(228) ,--i-- + ki => ex2_pp2_1k(228) ,--i-- + ko => ex2_pp2_1k(227) ,--o-- + sum => ex2_pp2_1s(228) ,--o-- + car => ex2_pp2_1c(227) );--o-- + csa2_1_227: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(227) ,--i-- + b => ex2_pp1_2s(227) ,--i-- + c => ex2_pp1_3c(227) ,--i-- + d => ex2_pp1_3s(227) ,--i-- + ki => ex2_pp2_1k(227) ,--i-- + ko => ex2_pp2_1k(226) ,--o-- + sum => ex2_pp2_1s(227) ,--o-- + car => ex2_pp2_1c(226) );--o-- + csa2_1_226: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(226) ,--i-- + b => ex2_pp1_2s(226) ,--i-- + c => ex2_pp1_3c(226) ,--i-- + d => ex2_pp1_3s(226) ,--i-- + ki => ex2_pp2_1k(226) ,--i-- + ko => ex2_pp2_1k(225) ,--o-- + sum => ex2_pp2_1s(226) ,--o-- + car => ex2_pp2_1c(225) );--o-- + csa2_1_225: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(225) ,--i-- + b => ex2_pp1_2s(225) ,--i-- + c => ex2_pp1_3c(225) ,--i-- + d => ex2_pp1_3s(225) ,--i-- + ki => ex2_pp2_1k(225) ,--i-- + ko => ex2_pp2_1k(224) ,--o-- + sum => ex2_pp2_1s(225) ,--o-- + car => ex2_pp2_1c(224) );--o-- + csa2_1_224: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(224) ,--i-- + b => ex2_pp1_2s(224) ,--i-- + c => ex2_pp1_3c(224) ,--i-- + d => ex2_pp1_3s(224) ,--i-- + ki => ex2_pp2_1k(224) ,--i-- + ko => ex2_pp2_1k(223) ,--o-- + sum => ex2_pp2_1s(224) ,--o-- + car => ex2_pp2_1c(223) );--o-- + csa2_1_223: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(223) ,--i-- + b => ex2_pp1_2s(223) ,--i-- + c => ex2_pp1_3c(223) ,--i-- + d => ex2_pp1_3s(223) ,--i-- + ki => ex2_pp2_1k(223) ,--i-- + ko => ex2_pp2_1k(222) ,--o-- + sum => ex2_pp2_1s(223) ,--o-- + car => ex2_pp2_1c(222) );--o-- + csa2_1_222: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(222) ,--i-- + b => ex2_pp1_2s(222) ,--i-- + c => ex2_pp1_3c(222) ,--i-- + d => ex2_pp1_3s(222) ,--i-- + ki => ex2_pp2_1k(222) ,--i-- + ko => ex2_pp2_1k(221) ,--o-- + sum => ex2_pp2_1s(222) ,--o-- + car => ex2_pp2_1c(221) );--o-- + csa2_1_221: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(221) ,--i-- + b => ex2_pp1_2s(221) ,--i-- + c => ex2_pp1_3c(221) ,--i-- + d => ex2_pp1_3s(221) ,--i-- + ki => ex2_pp2_1k(221) ,--i-- + ko => ex2_pp2_1k(220) ,--o-- + sum => ex2_pp2_1s(221) ,--o-- + car => ex2_pp2_1c(220) );--o-- + csa2_1_220: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(220) ,--i-- + b => ex2_pp1_2s(220) ,--i-- + c => ex2_pp1_3c(220) ,--i-- + d => ex2_pp1_3s(220) ,--i-- + ki => ex2_pp2_1k(220) ,--i-- + ko => ex2_pp2_1k(219) ,--o-- + sum => ex2_pp2_1s(220) ,--o-- + car => ex2_pp2_1c(219) );--o-- + csa2_1_219: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(219) ,--i-- + b => ex2_pp1_2s(219) ,--i-- + c => ex2_pp1_3c(219) ,--i-- + d => ex2_pp1_3s(219) ,--i-- + ki => ex2_pp2_1k(219) ,--i-- + ko => ex2_pp2_1k(218) ,--o-- + sum => ex2_pp2_1s(219) ,--o-- + car => ex2_pp2_1c(218) );--o-- + csa2_1_218: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(218) ,--i-- + b => ex2_pp1_2s(218) ,--i-- + c => ex2_pp1_3c(218) ,--i-- + d => ex2_pp1_3s(218) ,--i-- + ki => ex2_pp2_1k(218) ,--i-- + ko => ex2_pp2_1k(217) ,--o-- + sum => ex2_pp2_1s(218) ,--o-- + car => ex2_pp2_1c(217) );--o-- + csa2_1_217: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(217) ,--i-- + b => ex2_pp1_2s(217) ,--i-- + c => ex2_pp1_3c(217) ,--i-- + d => ex2_pp1_3s(217) ,--i-- + ki => ex2_pp2_1k(217) ,--i-- + ko => ex2_pp2_1k(216) ,--o-- + sum => ex2_pp2_1s(217) ,--o-- + car => ex2_pp2_1c(216) );--o-- + csa2_1_216: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(216) ,--i-- + b => ex2_pp1_2s(216) ,--i-- + c => ex2_pp1_3c(216) ,--i-- + d => ex2_pp1_3s(216) ,--i-- + ki => ex2_pp2_1k(216) ,--i-- + ko => ex2_pp2_1k(215) ,--o-- + sum => ex2_pp2_1s(216) ,--o-- + car => ex2_pp2_1c(215) );--o-- + csa2_1_215: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(215) ,--i-- + b => ex2_pp1_2s(215) ,--i-- + c => ex2_pp1_3c(215) ,--i-- + d => ex2_pp1_3s(215) ,--i-- + ki => ex2_pp2_1k(215) ,--i-- + ko => ex2_pp2_1k(214) ,--o-- + sum => ex2_pp2_1s(215) ,--o-- + car => ex2_pp2_1c(214) );--o-- + csa2_1_214: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(214) ,--i-- + b => ex2_pp1_2s(214) ,--i-- + c => ex2_pp1_3s(214) ,--i-- + d => tidn ,--i-- + ki => ex2_pp2_1k(214) ,--i-- + ko => ex2_pp2_1k(213) ,--o-- + sum => ex2_pp2_1s(214) ,--o-- + car => ex2_pp2_1c(213) );--o-- + csa2_1_213: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_2c(213) ,--i-- + b => ex2_pp1_2s(213) ,--i-- + c => ex2_pp2_1k(213) ,--i-- + sum => ex2_pp2_1s(213) ,--o-- + car => ex2_pp2_1c(212) );--o-- + csa2_1_212: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp1_2c(212) ,--i-- + b => ex2_pp1_2s(212) ,--i-- + sum => ex2_pp2_1s(212) ,--o-- + car => ex2_pp2_1c(211) );--o-- + csa2_1_211: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp1_2c(211) ,--i-- + b => ex2_pp1_2s(211) ,--i-- + sum => ex2_pp2_1s(211) ,--o-- + car => ex2_pp2_1c(210) );--o-- + csa2_1_210: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp1_2c(210) ,--i-- + b => ex2_pp1_2s(210) ,--i-- + sum => ex2_pp2_1s(210) ,--o-- + car => ex2_pp2_1c(209) );--o-- + csa2_1_209: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp1_2c(209) ,--i-- + b => ex2_pp1_2s(209) ,--i-- + sum => ex2_pp2_1s(209) ,--o-- + car => ex2_pp2_1c(208) );--o-- + ex2_pp2_1s(208) <= ex2_pp1_2s(208) ; --pass_x_s + + + + ------- ----- + + csa2_2_264: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp1_5c(264) ,--i-- + b => ex2_pp1_5s(264) ,--i-- + sum => ex2_pp2_2s(264) ,--o-- + car => ex2_pp2_2c(263) );--o-- + ex2_pp2_2s(263) <= ex2_pp1_5s(263) ; --pass_x_s + ex2_pp2_2c(262) <= tidn ; --pass_s + ex2_pp2_2s(262) <= ex2_pp1_5s(262) ; --pass_s + ex2_pp2_2c(261) <= ex2_pp1_5s(261) ; --pass_cs + ex2_pp2_2s(261) <= ex2_pp1_5c(261) ; --pass_cs + ex2_pp2_2c(260) <= tidn ; --wr_csa32 + csa2_2_260: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4s(260) ,--i-- + b => ex2_pp1_5c(260) ,--i-- + c => ex2_pp1_5s(260) ,--i-- + sum => ex2_pp2_2s(260) ,--o-- + car => ex2_pp2_2c(259) );--o-- + csa2_2_259: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp1_5c(259) ,--i-- + b => ex2_pp1_5s(259) ,--i-- + sum => ex2_pp2_2s(259) ,--o-- + car => ex2_pp2_2c(258) );--o-- + ex2_pp2_2k(258) <= tidn ; --start_k + csa2_2_258: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(258) ,--i-- + b => ex2_pp1_4s(258) ,--i-- + c => ex2_pp1_5c(258) ,--i-- + d => ex2_pp1_5s(258) ,--i-- + ki => ex2_pp2_2k(258) ,--i-- + ko => ex2_pp2_2k(257) ,--o-- + sum => ex2_pp2_2s(258) ,--o-- + car => ex2_pp2_2c(257) );--o-- + csa2_2_257: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4s(257) ,--i-- + b => ex2_pp1_5c(257) ,--i-- + c => ex2_pp1_5s(257) ,--i-- + d => tidn ,--i-- + ki => ex2_pp2_2k(257) ,--i-- + ko => ex2_pp2_2k(256) ,--o-- + sum => ex2_pp2_2s(257) ,--o-- + car => ex2_pp2_2c(256) );--o-- + csa2_2_256: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4s(256) ,--i-- + b => ex2_pp1_5c(256) ,--i-- + c => ex2_pp1_5s(256) ,--i-- + d => tidn ,--i-- + ki => ex2_pp2_2k(256) ,--i-- + ko => ex2_pp2_2k(255) ,--o-- + sum => ex2_pp2_2s(256) ,--o-- + car => ex2_pp2_2c(255) );--o-- + csa2_2_255: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(255) ,--i-- + b => ex2_pp1_4s(255) ,--i-- + c => ex2_pp1_5c(255) ,--i-- + d => ex2_pp1_5s(255) ,--i-- + ki => ex2_pp2_2k(255) ,--i-- + ko => ex2_pp2_2k(254) ,--o-- + sum => ex2_pp2_2s(255) ,--o-- + car => ex2_pp2_2c(254) );--o-- + csa2_2_254: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(254) ,--i-- + b => ex2_pp1_4s(254) ,--i-- + c => ex2_pp1_5c(254) ,--i-- + d => ex2_pp1_5s(254) ,--i-- + ki => ex2_pp2_2k(254) ,--i-- + ko => ex2_pp2_2k(253) ,--o-- + sum => ex2_pp2_2s(254) ,--o-- + car => ex2_pp2_2c(253) );--o-- + csa2_2_253: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(253) ,--i-- + b => ex2_pp1_4s(253) ,--i-- + c => ex2_pp1_5c(253) ,--i-- + d => ex2_pp1_5s(253) ,--i-- + ki => ex2_pp2_2k(253) ,--i-- + ko => ex2_pp2_2k(252) ,--o-- + sum => ex2_pp2_2s(253) ,--o-- + car => ex2_pp2_2c(252) );--o-- + csa2_2_252: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(252) ,--i-- + b => ex2_pp1_4s(252) ,--i-- + c => ex2_pp1_5c(252) ,--i-- + d => ex2_pp1_5s(252) ,--i-- + ki => ex2_pp2_2k(252) ,--i-- + ko => ex2_pp2_2k(251) ,--o-- + sum => ex2_pp2_2s(252) ,--o-- + car => ex2_pp2_2c(251) );--o-- + csa2_2_251: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(251) ,--i-- + b => ex2_pp1_4s(251) ,--i-- + c => ex2_pp1_5c(251) ,--i-- + d => ex2_pp1_5s(251) ,--i-- + ki => ex2_pp2_2k(251) ,--i-- + ko => ex2_pp2_2k(250) ,--o-- + sum => ex2_pp2_2s(251) ,--o-- + car => ex2_pp2_2c(250) );--o-- + csa2_2_250: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(250) ,--i-- + b => ex2_pp1_4s(250) ,--i-- + c => ex2_pp1_5c(250) ,--i-- + d => ex2_pp1_5s(250) ,--i-- + ki => ex2_pp2_2k(250) ,--i-- + ko => ex2_pp2_2k(249) ,--o-- + sum => ex2_pp2_2s(250) ,--o-- + car => ex2_pp2_2c(249) );--o-- + csa2_2_249: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(249) ,--i-- + b => ex2_pp1_4s(249) ,--i-- + c => ex2_pp1_5c(249) ,--i-- + d => ex2_pp1_5s(249) ,--i-- + ki => ex2_pp2_2k(249) ,--i-- + ko => ex2_pp2_2k(248) ,--o-- + sum => ex2_pp2_2s(249) ,--o-- + car => ex2_pp2_2c(248) );--o-- + csa2_2_248: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(248) ,--i-- + b => ex2_pp1_4s(248) ,--i-- + c => ex2_pp1_5c(248) ,--i-- + d => ex2_pp1_5s(248) ,--i-- + ki => ex2_pp2_2k(248) ,--i-- + ko => ex2_pp2_2k(247) ,--o-- + sum => ex2_pp2_2s(248) ,--o-- + car => ex2_pp2_2c(247) );--o-- + csa2_2_247: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(247) ,--i-- + b => ex2_pp1_4s(247) ,--i-- + c => ex2_pp1_5c(247) ,--i-- + d => ex2_pp1_5s(247) ,--i-- + ki => ex2_pp2_2k(247) ,--i-- + ko => ex2_pp2_2k(246) ,--o-- + sum => ex2_pp2_2s(247) ,--o-- + car => ex2_pp2_2c(246) );--o-- + csa2_2_246: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(246) ,--i-- + b => ex2_pp1_4s(246) ,--i-- + c => ex2_pp1_5c(246) ,--i-- + d => ex2_pp1_5s(246) ,--i-- + ki => ex2_pp2_2k(246) ,--i-- + ko => ex2_pp2_2k(245) ,--o-- + sum => ex2_pp2_2s(246) ,--o-- + car => ex2_pp2_2c(245) );--o-- + csa2_2_245: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(245) ,--i-- + b => ex2_pp1_4s(245) ,--i-- + c => ex2_pp1_5c(245) ,--i-- + d => ex2_pp1_5s(245) ,--i-- + ki => ex2_pp2_2k(245) ,--i-- + ko => ex2_pp2_2k(244) ,--o-- + sum => ex2_pp2_2s(245) ,--o-- + car => ex2_pp2_2c(244) );--o-- + csa2_2_244: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(244) ,--i-- + b => ex2_pp1_4s(244) ,--i-- + c => ex2_pp1_5c(244) ,--i-- + d => ex2_pp1_5s(244) ,--i-- + ki => ex2_pp2_2k(244) ,--i-- + ko => ex2_pp2_2k(243) ,--o-- + sum => ex2_pp2_2s(244) ,--o-- + car => ex2_pp2_2c(243) );--o-- + csa2_2_243: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(243) ,--i-- + b => ex2_pp1_4s(243) ,--i-- + c => ex2_pp1_5c(243) ,--i-- + d => ex2_pp1_5s(243) ,--i-- + ki => ex2_pp2_2k(243) ,--i-- + ko => ex2_pp2_2k(242) ,--o-- + sum => ex2_pp2_2s(243) ,--o-- + car => ex2_pp2_2c(242) );--o-- + csa2_2_242: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(242) ,--i-- + b => ex2_pp1_4s(242) ,--i-- + c => ex2_pp1_5c(242) ,--i-- + d => ex2_pp1_5s(242) ,--i-- + ki => ex2_pp2_2k(242) ,--i-- + ko => ex2_pp2_2k(241) ,--o-- + sum => ex2_pp2_2s(242) ,--o-- + car => ex2_pp2_2c(241) );--o-- + csa2_2_241: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(241) ,--i-- + b => ex2_pp1_4s(241) ,--i-- + c => ex2_pp1_5c(241) ,--i-- + d => ex2_pp1_5s(241) ,--i-- + ki => ex2_pp2_2k(241) ,--i-- + ko => ex2_pp2_2k(240) ,--o-- + sum => ex2_pp2_2s(241) ,--o-- + car => ex2_pp2_2c(240) );--o-- + csa2_2_240: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(240) ,--i-- + b => ex2_pp1_4s(240) ,--i-- + c => ex2_pp1_5c(240) ,--i-- + d => ex2_pp1_5s(240) ,--i-- + ki => ex2_pp2_2k(240) ,--i-- + ko => ex2_pp2_2k(239) ,--o-- + sum => ex2_pp2_2s(240) ,--o-- + car => ex2_pp2_2c(239) );--o-- + csa2_2_239: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(239) ,--i-- + b => ex2_pp1_4s(239) ,--i-- + c => ex2_pp1_5c(239) ,--i-- + d => ex2_pp1_5s(239) ,--i-- + ki => ex2_pp2_2k(239) ,--i-- + ko => ex2_pp2_2k(238) ,--o-- + sum => ex2_pp2_2s(239) ,--o-- + car => ex2_pp2_2c(238) );--o-- + csa2_2_238: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(238) ,--i-- + b => ex2_pp1_4s(238) ,--i-- + c => ex2_pp1_5c(238) ,--i-- + d => ex2_pp1_5s(238) ,--i-- + ki => ex2_pp2_2k(238) ,--i-- + ko => ex2_pp2_2k(237) ,--o-- + sum => ex2_pp2_2s(238) ,--o-- + car => ex2_pp2_2c(237) );--o-- + csa2_2_237: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(237) ,--i-- + b => ex2_pp1_4s(237) ,--i-- + c => ex2_pp1_5c(237) ,--i-- + d => ex2_pp1_5s(237) ,--i-- + ki => ex2_pp2_2k(237) ,--i-- + ko => ex2_pp2_2k(236) ,--o-- + sum => ex2_pp2_2s(237) ,--o-- + car => ex2_pp2_2c(236) );--o-- + csa2_2_236: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(236) ,--i-- + b => ex2_pp1_4s(236) ,--i-- + c => ex2_pp1_5c(236) ,--i-- + d => ex2_pp1_5s(236) ,--i-- + ki => ex2_pp2_2k(236) ,--i-- + ko => ex2_pp2_2k(235) ,--o-- + sum => ex2_pp2_2s(236) ,--o-- + car => ex2_pp2_2c(235) );--o-- + csa2_2_235: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(235) ,--i-- + b => ex2_pp1_4s(235) ,--i-- + c => ex2_pp1_5c(235) ,--i-- + d => ex2_pp1_5s(235) ,--i-- + ki => ex2_pp2_2k(235) ,--i-- + ko => ex2_pp2_2k(234) ,--o-- + sum => ex2_pp2_2s(235) ,--o-- + car => ex2_pp2_2c(234) );--o-- + csa2_2_234: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(234) ,--i-- + b => ex2_pp1_4s(234) ,--i-- + c => ex2_pp1_5c(234) ,--i-- + d => ex2_pp1_5s(234) ,--i-- + ki => ex2_pp2_2k(234) ,--i-- + ko => ex2_pp2_2k(233) ,--o-- + sum => ex2_pp2_2s(234) ,--o-- + car => ex2_pp2_2c(233) );--o-- + csa2_2_233: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(233) ,--i-- + b => ex2_pp1_4s(233) ,--i-- + c => ex2_pp1_5c(233) ,--i-- + d => ex2_pp1_5s(233) ,--i-- + ki => ex2_pp2_2k(233) ,--i-- + ko => ex2_pp2_2k(232) ,--o-- + sum => ex2_pp2_2s(233) ,--o-- + car => ex2_pp2_2c(232) );--o-- + csa2_2_232: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(232) ,--i-- + b => ex2_pp1_4s(232) ,--i-- + c => ex2_pp1_5c(232) ,--i-- + d => ex2_pp1_5s(232) ,--i-- + ki => ex2_pp2_2k(232) ,--i-- + ko => ex2_pp2_2k(231) ,--o-- + sum => ex2_pp2_2s(232) ,--o-- + car => ex2_pp2_2c(231) );--o-- + csa2_2_231: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(231) ,--i-- + b => ex2_pp1_4s(231) ,--i-- + c => ex2_pp1_5c(231) ,--i-- + d => ex2_pp1_5s(231) ,--i-- + ki => ex2_pp2_2k(231) ,--i-- + ko => ex2_pp2_2k(230) ,--o-- + sum => ex2_pp2_2s(231) ,--o-- + car => ex2_pp2_2c(230) );--o-- + csa2_2_230: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(230) ,--i-- + b => ex2_pp1_4s(230) ,--i-- + c => ex2_pp1_5c(230) ,--i-- + d => ex2_pp1_5s(230) ,--i-- + ki => ex2_pp2_2k(230) ,--i-- + ko => ex2_pp2_2k(229) ,--o-- + sum => ex2_pp2_2s(230) ,--o-- + car => ex2_pp2_2c(229) );--o-- + csa2_2_229: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(229) ,--i-- + b => ex2_pp1_4s(229) ,--i-- + c => ex2_pp1_5c(229) ,--i-- + d => ex2_pp1_5s(229) ,--i-- + ki => ex2_pp2_2k(229) ,--i-- + ko => ex2_pp2_2k(228) ,--o-- + sum => ex2_pp2_2s(229) ,--o-- + car => ex2_pp2_2c(228) );--o-- + csa2_2_228: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(228) ,--i-- + b => ex2_pp1_4s(228) ,--i-- + c => ex2_pp1_5c(228) ,--i-- + d => ex2_pp1_5s(228) ,--i-- + ki => ex2_pp2_2k(228) ,--i-- + ko => ex2_pp2_2k(227) ,--o-- + sum => ex2_pp2_2s(228) ,--o-- + car => ex2_pp2_2c(227) );--o-- + csa2_2_227: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(227) ,--i-- + b => ex2_pp1_4s(227) ,--i-- + c => ex2_pp1_5c(227) ,--i-- + d => ex2_pp1_5s(227) ,--i-- + ki => ex2_pp2_2k(227) ,--i-- + ko => ex2_pp2_2k(226) ,--o-- + sum => ex2_pp2_2s(227) ,--o-- + car => ex2_pp2_2c(226) );--o-- + csa2_2_226: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(226) ,--i-- + b => ex2_pp1_4s(226) ,--i-- + c => ex2_pp1_5s(226) ,--i-- + d => tidn ,--i-- + ki => ex2_pp2_2k(226) ,--i-- + ko => ex2_pp2_2k(225) ,--o-- + sum => ex2_pp2_2s(226) ,--o-- + car => ex2_pp2_2c(225) );--o-- + csa2_2_225: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex2_pp1_4c(225) ,--i-- + b => ex2_pp1_4s(225) ,--i-- + c => ex2_pp2_2k(225) ,--i-- + sum => ex2_pp2_2s(225) ,--o-- + car => ex2_pp2_2c(224) );--o-- + csa2_2_224: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp1_4c(224) ,--i-- + b => ex2_pp1_4s(224) ,--i-- + sum => ex2_pp2_2s(224) ,--o-- + car => ex2_pp2_2c(223) );--o-- + csa2_2_223: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp1_4c(223) ,--i-- + b => ex2_pp1_4s(223) ,--i-- + sum => ex2_pp2_2s(223) ,--o-- + car => ex2_pp2_2c(222) );--o-- + csa2_2_222: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp1_4c(222) ,--i-- + b => ex2_pp1_4s(222) ,--i-- + sum => ex2_pp2_2s(222) ,--o-- + car => ex2_pp2_2c(221) );--o-- + csa2_2_221: entity work.xuq_alu_mult_csa22 port map( + a => ex2_pp1_4c(221) ,--i-- + b => ex2_pp1_4s(221) ,--i-- + sum => ex2_pp2_2s(221) ,--o-- + car => ex2_pp2_2c(220) );--o-- + ex2_pp2_2s(220) <= ex2_pp1_4s(220) ; --pass_x_s + +----------------------------------------------- +----------------------------------------------- +----------------------------------------------- + + + + + ex3_pp2_0s_din(198 to 242) <= ex2_pp2_0s(198 to 242) ; + ex3_pp2_0c_din(198 to 240) <= ex2_pp2_0c(198 to 240) ; + ex3_pp2_1s_din(208 to 254) <= ex2_pp2_1s(208 to 254) ; + ex3_pp2_1c_din(208 to 252) <= ex2_pp2_1c(208 to 252) ; + ex3_pp2_2s_din(220 to 264) <= ex2_pp2_2s(220 to 264) ; + ex3_pp2_2c_din(220 to 263) <= ex2_pp2_2c(220 to 263) ; + + +--================================================================================== +--== EX3 ( finish compression <6:2> , feedback compression with previous result ) +--================================================================================== + + u_0s_qi: ex3_pp2_0s (198 to 242) <= not ex3_pp2_0s_q_b(198 to 242) ; + u_0c_qi: ex3_pp2_0c (198 to 240) <= not ex3_pp2_0c_q_b(198 to 240) ; + + u_1s_qi: ex3_pp2_1s_x (208 to 254) <= not ex3_pp2_1s_q_b(208 to 254) ; + u_1c_qi: ex3_pp2_1c_x (208 to 252) <= not ex3_pp2_1c_q_b(208 to 252) ; + u_2s_qi: ex3_pp2_2s_x (220 to 264) <= not ex3_pp2_2s_q_b(220 to 264) ; + u_2c_qi: ex3_pp2_2c_x (220 to 263) <= not ex3_pp2_2c_q_b(220 to 263) ; + + u_1s_mini: ex3_pp2_1s_x_b(208 to 254) <= not ex3_pp2_1s_x (208 to 254) ; + u_1c_mini: ex3_pp2_1c_x_b(208 to 252) <= not ex3_pp2_1c_x (208 to 252) ; + u_2s_mini: ex3_pp2_2s_x_b(220 to 264) <= not ex3_pp2_2s_x (220 to 264) ; + u_2c_mini: ex3_pp2_2c_x_b(220 to 263) <= not ex3_pp2_2c_x (220 to 263) ; + + u_1s_mind: ex3_pp2_1s (208 to 254) <= not ex3_pp2_1s_x_b(208 to 254) ; + u_1c_mind: ex3_pp2_1c (208 to 252) <= not ex3_pp2_1c_x_b(208 to 252) ; + u_2s_mind: ex3_pp2_2s (220 to 264) <= not ex3_pp2_2s_x_b(220 to 264) ; + u_2c_mind: ex3_pp2_2c (220 to 263) <= not ex3_pp2_2c_x_b(220 to 263) ; + + + + + + + + + --*********************************** + --** compression level 3 + --*********************************** + + -- g3 : for i in 196 to 264 generate + -- + -- csa3_0: entity work.c_prism_csa32 port map( + -- a => ex3_pp2_0s(i) ,--i-- + -- b => ex3_pp2_0c(i) ,--i-- + -- c => ex3_pp2_1s(i) ,--i-- + -- sum => ex3_pp3_0s(i) ,--o-- + -- car => ex3_pp3_0c(i-1) );--o-- + -- + -- csa3_1: entity work.c_prism_csa32 port map( + -- a => ex3_pp2_1c(i) ,--i-- + -- b => ex3_pp2_2s(i) ,--i-- + -- c => ex3_pp2_2c(i) ,--i-- + -- sum => ex3_pp3_1s(i) ,--o-- + -- car => ex3_pp3_1c(i-1) );--o-- + -- + -- end generate; + + + ------- ----- + + ex3_pp3_0s(252) <= ex3_pp2_1c(252) ; --pass_s + ex3_pp3_0s(251) <= tidn ; --pass_none + ex3_pp3_0s(250) <= tidn ; --pass_none + ex3_pp3_0s(249) <= ex3_pp2_1c(249) ; --pass_s + ex3_pp3_0s(248) <= tidn ; --pass_none + ex3_pp3_0s(247) <= ex3_pp2_1c(247) ; --pass_s + ex3_pp3_0s(246) <= ex3_pp2_1c(246) ; --pass_s + ex3_pp3_0s(245) <= ex3_pp2_1c(245) ; --pass_s + ex3_pp3_0s(244) <= ex3_pp2_1c(244) ; --pass_s + ex3_pp3_0s(243) <= ex3_pp2_1c(243) ; --pass_s + ex3_pp3_0c(242) <= ex3_pp2_1c(242) ; --pass_cs + ex3_pp3_0s(242) <= ex3_pp2_0s(242) ; --pass_cs + ex3_pp3_0c(241) <= tidn ; --pass_s + ex3_pp3_0s(241) <= ex3_pp2_1c(241) ; --pass_s + ex3_pp3_0c(240) <= tidn ; --wr_csa32 + csa3_0_240: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_0c(240) ,--i-- + b => ex3_pp2_0s(240) ,--i-- + c => ex3_pp2_1c(240) ,--i-- + sum => ex3_pp3_0s(240) ,--o-- + car => ex3_pp3_0c(239) );--o-- + csa3_0_239: entity work.xuq_alu_mult_csa22 port map( + a => ex3_pp2_0s(239) ,--i-- + b => ex3_pp2_1c(239) ,--i-- + sum => ex3_pp3_0s(239) ,--o-- + car => ex3_pp3_0c(238) );--o-- + csa3_0_238: entity work.xuq_alu_mult_csa22 port map( + a => ex3_pp2_0s(238) ,--i-- + b => ex3_pp2_1c(238) ,--i-- + sum => ex3_pp3_0s(238) ,--o-- + car => ex3_pp3_0c(237) );--o-- + csa3_0_237: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_0c(237) ,--i-- + b => ex3_pp2_0s(237) ,--i-- + c => ex3_pp2_1c(237) ,--i-- + sum => ex3_pp3_0s(237) ,--o-- + car => ex3_pp3_0c(236) );--o-- + csa3_0_236: entity work.xuq_alu_mult_csa22 port map( + a => ex3_pp2_0s(236) ,--i-- + b => ex3_pp2_1c(236) ,--i-- + sum => ex3_pp3_0s(236) ,--o-- + car => ex3_pp3_0c(235) );--o-- + csa3_0_235: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_0c(235) ,--i-- + b => ex3_pp2_0s(235) ,--i-- + c => ex3_pp2_1c(235) ,--i-- + sum => ex3_pp3_0s(235) ,--o-- + car => ex3_pp3_0c(234) );--o-- + csa3_0_234: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_0c(234) ,--i-- + b => ex3_pp2_0s(234) ,--i-- + c => ex3_pp2_1c(234) ,--i-- + sum => ex3_pp3_0s(234) ,--o-- + car => ex3_pp3_0c(233) );--o-- + csa3_0_233: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_0c(233) ,--i-- + b => ex3_pp2_0s(233) ,--i-- + c => ex3_pp2_1c(233) ,--i-- + sum => ex3_pp3_0s(233) ,--o-- + car => ex3_pp3_0c(232) );--o-- + csa3_0_232: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_0c(232) ,--i-- + b => ex3_pp2_0s(232) ,--i-- + c => ex3_pp2_1c(232) ,--i-- + sum => ex3_pp3_0s(232) ,--o-- + car => ex3_pp3_0c(231) );--o-- + csa3_0_231: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_0c(231) ,--i-- + b => ex3_pp2_0s(231) ,--i-- + c => ex3_pp2_1c(231) ,--i-- + sum => ex3_pp3_0s(231) ,--o-- + car => ex3_pp3_0c(230) );--o-- + csa3_0_230: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_0c(230) ,--i-- + b => ex3_pp2_0s(230) ,--i-- + c => ex3_pp2_1c(230) ,--i-- + sum => ex3_pp3_0s(230) ,--o-- + car => ex3_pp3_0c(229) );--o-- + csa3_0_229: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_0c(229) ,--i-- + b => ex3_pp2_0s(229) ,--i-- + c => ex3_pp2_1c(229) ,--i-- + sum => ex3_pp3_0s(229) ,--o-- + car => ex3_pp3_0c(228) );--o-- + csa3_0_228: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_0c(228) ,--i-- + b => ex3_pp2_0s(228) ,--i-- + c => ex3_pp2_1c(228) ,--i-- + sum => ex3_pp3_0s(228) ,--o-- + car => ex3_pp3_0c(227) );--o-- + csa3_0_227: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_0c(227) ,--i-- + b => ex3_pp2_0s(227) ,--i-- + c => ex3_pp2_1c(227) ,--i-- + sum => ex3_pp3_0s(227) ,--o-- + car => ex3_pp3_0c(226) );--o-- + csa3_0_226: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_0c(226) ,--i-- + b => ex3_pp2_0s(226) ,--i-- + c => ex3_pp2_1c(226) ,--i-- + sum => ex3_pp3_0s(226) ,--o-- + car => ex3_pp3_0c(225) );--o-- + csa3_0_225: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_0c(225) ,--i-- + b => ex3_pp2_0s(225) ,--i-- + c => ex3_pp2_1c(225) ,--i-- + sum => ex3_pp3_0s(225) ,--o-- + car => ex3_pp3_0c(224) );--o-- + csa3_0_224: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_0c(224) ,--i-- + b => ex3_pp2_0s(224) ,--i-- + c => ex3_pp2_1c(224) ,--i-- + sum => ex3_pp3_0s(224) ,--o-- + car => ex3_pp3_0c(223) );--o-- + csa3_0_223: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_0c(223) ,--i-- + b => ex3_pp2_0s(223) ,--i-- + c => ex3_pp2_1c(223) ,--i-- + sum => ex3_pp3_0s(223) ,--o-- + car => ex3_pp3_0c(222) );--o-- + csa3_0_222: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_0c(222) ,--i-- + b => ex3_pp2_0s(222) ,--i-- + c => ex3_pp2_1c(222) ,--i-- + sum => ex3_pp3_0s(222) ,--o-- + car => ex3_pp3_0c(221) );--o-- + csa3_0_221: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_0c(221) ,--i-- + b => ex3_pp2_0s(221) ,--i-- + c => ex3_pp2_1c(221) ,--i-- + sum => ex3_pp3_0s(221) ,--o-- + car => ex3_pp3_0c(220) );--o-- + csa3_0_220: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_0c(220) ,--i-- + b => ex3_pp2_0s(220) ,--i-- + c => ex3_pp2_1c(220) ,--i-- + sum => ex3_pp3_0s(220) ,--o-- + car => ex3_pp3_0c(219) );--o-- + csa3_0_219: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_0c(219) ,--i-- + b => ex3_pp2_0s(219) ,--i-- + c => ex3_pp2_1c(219) ,--i-- + sum => ex3_pp3_0s(219) ,--o-- + car => ex3_pp3_0c(218) );--o-- + csa3_0_218: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_0c(218) ,--i-- + b => ex3_pp2_0s(218) ,--i-- + c => ex3_pp2_1c(218) ,--i-- + sum => ex3_pp3_0s(218) ,--o-- + car => ex3_pp3_0c(217) );--o-- + csa3_0_217: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_0c(217) ,--i-- + b => ex3_pp2_0s(217) ,--i-- + c => ex3_pp2_1c(217) ,--i-- + sum => ex3_pp3_0s(217) ,--o-- + car => ex3_pp3_0c(216) );--o-- + csa3_0_216: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_0c(216) ,--i-- + b => ex3_pp2_0s(216) ,--i-- + c => ex3_pp2_1c(216) ,--i-- + sum => ex3_pp3_0s(216) ,--o-- + car => ex3_pp3_0c(215) );--o-- + csa3_0_215: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_0c(215) ,--i-- + b => ex3_pp2_0s(215) ,--i-- + c => ex3_pp2_1c(215) ,--i-- + sum => ex3_pp3_0s(215) ,--o-- + car => ex3_pp3_0c(214) );--o-- + csa3_0_214: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_0c(214) ,--i-- + b => ex3_pp2_0s(214) ,--i-- + c => ex3_pp2_1c(214) ,--i-- + sum => ex3_pp3_0s(214) ,--o-- + car => ex3_pp3_0c(213) );--o-- + csa3_0_213: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_0c(213) ,--i-- + b => ex3_pp2_0s(213) ,--i-- + c => ex3_pp2_1c(213) ,--i-- + sum => ex3_pp3_0s(213) ,--o-- + car => ex3_pp3_0c(212) );--o-- + csa3_0_212: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_0c(212) ,--i-- + b => ex3_pp2_0s(212) ,--i-- + c => ex3_pp2_1c(212) ,--i-- + sum => ex3_pp3_0s(212) ,--o-- + car => ex3_pp3_0c(211) );--o-- + csa3_0_211: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_0c(211) ,--i-- + b => ex3_pp2_0s(211) ,--i-- + c => ex3_pp2_1c(211) ,--i-- + sum => ex3_pp3_0s(211) ,--o-- + car => ex3_pp3_0c(210) );--o-- + csa3_0_210: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_0c(210) ,--i-- + b => ex3_pp2_0s(210) ,--i-- + c => ex3_pp2_1c(210) ,--i-- + sum => ex3_pp3_0s(210) ,--o-- + car => ex3_pp3_0c(209) );--o-- + csa3_0_209: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_0c(209) ,--i-- + b => ex3_pp2_0s(209) ,--i-- + c => ex3_pp2_1c(209) ,--i-- + sum => ex3_pp3_0s(209) ,--o-- + car => ex3_pp3_0c(208) );--o-- + csa3_0_208: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_0c(208) ,--i-- + b => ex3_pp2_0s(208) ,--i-- + c => ex3_pp2_1c(208) ,--i-- + sum => ex3_pp3_0s(208) ,--o-- + car => ex3_pp3_0c(207) );--o-- + csa3_0_207: entity work.xuq_alu_mult_csa22 port map( + a => ex3_pp2_0c(207) ,--i-- + b => ex3_pp2_0s(207) ,--i-- + sum => ex3_pp3_0s(207) ,--o-- + car => ex3_pp3_0c(206) );--o-- + csa3_0_206: entity work.xuq_alu_mult_csa22 port map( + a => ex3_pp2_0c(206) ,--i-- + b => ex3_pp2_0s(206) ,--i-- + sum => ex3_pp3_0s(206) ,--o-- + car => ex3_pp3_0c(205) );--o-- + csa3_0_205: entity work.xuq_alu_mult_csa22 port map( + a => ex3_pp2_0c(205) ,--i-- + b => ex3_pp2_0s(205) ,--i-- + sum => ex3_pp3_0s(205) ,--o-- + car => ex3_pp3_0c(204) );--o-- + csa3_0_204: entity work.xuq_alu_mult_csa22 port map( + a => ex3_pp2_0c(204) ,--i-- + b => ex3_pp2_0s(204) ,--i-- + sum => ex3_pp3_0s(204) ,--o-- + car => ex3_pp3_0c(203) );--o-- + csa3_0_203: entity work.xuq_alu_mult_csa22 port map( + a => ex3_pp2_0c(203) ,--i-- + b => ex3_pp2_0s(203) ,--i-- + sum => ex3_pp3_0s(203) ,--o-- + car => ex3_pp3_0c(202) );--o-- + csa3_0_202: entity work.xuq_alu_mult_csa22 port map( + a => ex3_pp2_0c(202) ,--i-- + b => ex3_pp2_0s(202) ,--i-- + sum => ex3_pp3_0s(202) ,--o-- + car => ex3_pp3_0c(201) );--o-- + csa3_0_201: entity work.xuq_alu_mult_csa22 port map( + a => ex3_pp2_0c(201) ,--i-- + b => ex3_pp2_0s(201) ,--i-- + sum => ex3_pp3_0s(201) ,--o-- + car => ex3_pp3_0c(200) );--o-- + csa3_0_200: entity work.xuq_alu_mult_csa22 port map( + a => ex3_pp2_0c(200) ,--i-- + b => ex3_pp2_0s(200) ,--i-- + sum => ex3_pp3_0s(200) ,--o-- + car => ex3_pp3_0c(199) );--o-- + csa3_0_199: entity work.xuq_alu_mult_csa22 port map( + a => ex3_pp2_0c(199) ,--i-- + b => ex3_pp2_0s(199) ,--i-- + sum => ex3_pp3_0s(199) ,--o-- + car => ex3_pp3_0c(198) );--o-- + csa3_0_198: entity work.xuq_alu_mult_csa22 port map( + a => ex3_pp2_0c(198) ,--i-- + b => ex3_pp2_0s(198) ,--i-- + sum => ex3_pp3_0s(198) ,--o-- + car => ex3_pp3_0c(197) );--o-- + + + ------- ----- + + ex3_pp3_1s(264) <= ex3_pp2_2s(264) ; --pass_s + csa3_1_263: entity work.xuq_alu_mult_csa22 port map( + a => ex3_pp2_2c(263) ,--i-- + b => ex3_pp2_2s(263) ,--i-- + sum => ex3_pp3_1s(263) ,--o-- + car => ex3_pp3_1c(262) );--o-- + ex3_pp3_1s(262) <= ex3_pp2_2s(262) ; --pass_x_s + ex3_pp3_1c(261) <= ex3_pp2_2s(261) ; --pass_cs + ex3_pp3_1s(261) <= ex3_pp2_2c(261) ; --pass_cs + ex3_pp3_1c(260) <= tidn ; --pass_s + ex3_pp3_1s(260) <= ex3_pp2_2s(260) ; --pass_s + ex3_pp3_1c(259) <= ex3_pp2_2s(259) ; --pass_cs + ex3_pp3_1s(259) <= ex3_pp2_2c(259) ; --pass_cs + ex3_pp3_1c(258) <= ex3_pp2_2s(258) ; --pass_cs + ex3_pp3_1s(258) <= ex3_pp2_2c(258) ; --pass_cs + ex3_pp3_1c(257) <= ex3_pp2_2s(257) ; --pass_cs + ex3_pp3_1s(257) <= ex3_pp2_2c(257) ; --pass_cs + ex3_pp3_1c(256) <= ex3_pp2_2s(256) ; --pass_cs + ex3_pp3_1s(256) <= ex3_pp2_2c(256) ; --pass_cs + ex3_pp3_1c(255) <= ex3_pp2_2s(255) ; --pass_cs + ex3_pp3_1s(255) <= ex3_pp2_2c(255) ; --pass_cs + ex3_pp3_1c(254) <= tidn ; --wr_csa32 + csa3_1_254: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(254) ,--i-- + b => ex3_pp2_2c(254) ,--i-- + c => ex3_pp2_2s(254) ,--i-- + sum => ex3_pp3_1s(254) ,--o-- + car => ex3_pp3_1c(253) );--o-- + csa3_1_253: entity work.xuq_alu_mult_csa22 port map( + a => ex3_pp2_2c(253) ,--i-- + b => ex3_pp2_2s(253) ,--i-- + sum => ex3_pp3_1s(253) ,--o-- + car => ex3_pp3_1c(252) );--o-- + csa3_1_252: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(252) ,--i-- + b => ex3_pp2_2c(252) ,--i-- + c => ex3_pp2_2s(252) ,--i-- + sum => ex3_pp3_1s(252) ,--o-- + car => ex3_pp3_1c(251) );--o-- + csa3_1_251: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(251) ,--i-- + b => ex3_pp2_2c(251) ,--i-- + c => ex3_pp2_2s(251) ,--i-- + sum => ex3_pp3_1s(251) ,--o-- + car => ex3_pp3_1c(250) );--o-- + csa3_1_250: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(250) ,--i-- + b => ex3_pp2_2c(250) ,--i-- + c => ex3_pp2_2s(250) ,--i-- + sum => ex3_pp3_1s(250) ,--o-- + car => ex3_pp3_1c(249) );--o-- + csa3_1_249: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(249) ,--i-- + b => ex3_pp2_2c(249) ,--i-- + c => ex3_pp2_2s(249) ,--i-- + sum => ex3_pp3_1s(249) ,--o-- + car => ex3_pp3_1c(248) );--o-- + csa3_1_248: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(248) ,--i-- + b => ex3_pp2_2c(248) ,--i-- + c => ex3_pp2_2s(248) ,--i-- + sum => ex3_pp3_1s(248) ,--o-- + car => ex3_pp3_1c(247) );--o-- + csa3_1_247: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(247) ,--i-- + b => ex3_pp2_2c(247) ,--i-- + c => ex3_pp2_2s(247) ,--i-- + sum => ex3_pp3_1s(247) ,--o-- + car => ex3_pp3_1c(246) );--o-- + csa3_1_246: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(246) ,--i-- + b => ex3_pp2_2c(246) ,--i-- + c => ex3_pp2_2s(246) ,--i-- + sum => ex3_pp3_1s(246) ,--o-- + car => ex3_pp3_1c(245) );--o-- + csa3_1_245: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(245) ,--i-- + b => ex3_pp2_2c(245) ,--i-- + c => ex3_pp2_2s(245) ,--i-- + sum => ex3_pp3_1s(245) ,--o-- + car => ex3_pp3_1c(244) );--o-- + csa3_1_244: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(244) ,--i-- + b => ex3_pp2_2c(244) ,--i-- + c => ex3_pp2_2s(244) ,--i-- + sum => ex3_pp3_1s(244) ,--o-- + car => ex3_pp3_1c(243) );--o-- + csa3_1_243: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(243) ,--i-- + b => ex3_pp2_2c(243) ,--i-- + c => ex3_pp2_2s(243) ,--i-- + sum => ex3_pp3_1s(243) ,--o-- + car => ex3_pp3_1c(242) );--o-- + csa3_1_242: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(242) ,--i-- + b => ex3_pp2_2c(242) ,--i-- + c => ex3_pp2_2s(242) ,--i-- + sum => ex3_pp3_1s(242) ,--o-- + car => ex3_pp3_1c(241) );--o-- + csa3_1_241: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(241) ,--i-- + b => ex3_pp2_2c(241) ,--i-- + c => ex3_pp2_2s(241) ,--i-- + sum => ex3_pp3_1s(241) ,--o-- + car => ex3_pp3_1c(240) );--o-- + csa3_1_240: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(240) ,--i-- + b => ex3_pp2_2c(240) ,--i-- + c => ex3_pp2_2s(240) ,--i-- + sum => ex3_pp3_1s(240) ,--o-- + car => ex3_pp3_1c(239) );--o-- + csa3_1_239: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(239) ,--i-- + b => ex3_pp2_2c(239) ,--i-- + c => ex3_pp2_2s(239) ,--i-- + sum => ex3_pp3_1s(239) ,--o-- + car => ex3_pp3_1c(238) );--o-- + csa3_1_238: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(238) ,--i-- + b => ex3_pp2_2c(238) ,--i-- + c => ex3_pp2_2s(238) ,--i-- + sum => ex3_pp3_1s(238) ,--o-- + car => ex3_pp3_1c(237) );--o-- + csa3_1_237: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(237) ,--i-- + b => ex3_pp2_2c(237) ,--i-- + c => ex3_pp2_2s(237) ,--i-- + sum => ex3_pp3_1s(237) ,--o-- + car => ex3_pp3_1c(236) );--o-- + csa3_1_236: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(236) ,--i-- + b => ex3_pp2_2c(236) ,--i-- + c => ex3_pp2_2s(236) ,--i-- + sum => ex3_pp3_1s(236) ,--o-- + car => ex3_pp3_1c(235) );--o-- + csa3_1_235: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(235) ,--i-- + b => ex3_pp2_2c(235) ,--i-- + c => ex3_pp2_2s(235) ,--i-- + sum => ex3_pp3_1s(235) ,--o-- + car => ex3_pp3_1c(234) );--o-- + csa3_1_234: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(234) ,--i-- + b => ex3_pp2_2c(234) ,--i-- + c => ex3_pp2_2s(234) ,--i-- + sum => ex3_pp3_1s(234) ,--o-- + car => ex3_pp3_1c(233) );--o-- + csa3_1_233: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(233) ,--i-- + b => ex3_pp2_2c(233) ,--i-- + c => ex3_pp2_2s(233) ,--i-- + sum => ex3_pp3_1s(233) ,--o-- + car => ex3_pp3_1c(232) );--o-- + csa3_1_232: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(232) ,--i-- + b => ex3_pp2_2c(232) ,--i-- + c => ex3_pp2_2s(232) ,--i-- + sum => ex3_pp3_1s(232) ,--o-- + car => ex3_pp3_1c(231) );--o-- + csa3_1_231: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(231) ,--i-- + b => ex3_pp2_2c(231) ,--i-- + c => ex3_pp2_2s(231) ,--i-- + sum => ex3_pp3_1s(231) ,--o-- + car => ex3_pp3_1c(230) );--o-- + csa3_1_230: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(230) ,--i-- + b => ex3_pp2_2c(230) ,--i-- + c => ex3_pp2_2s(230) ,--i-- + sum => ex3_pp3_1s(230) ,--o-- + car => ex3_pp3_1c(229) );--o-- + csa3_1_229: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(229) ,--i-- + b => ex3_pp2_2c(229) ,--i-- + c => ex3_pp2_2s(229) ,--i-- + sum => ex3_pp3_1s(229) ,--o-- + car => ex3_pp3_1c(228) );--o-- + csa3_1_228: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(228) ,--i-- + b => ex3_pp2_2c(228) ,--i-- + c => ex3_pp2_2s(228) ,--i-- + sum => ex3_pp3_1s(228) ,--o-- + car => ex3_pp3_1c(227) );--o-- + csa3_1_227: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(227) ,--i-- + b => ex3_pp2_2c(227) ,--i-- + c => ex3_pp2_2s(227) ,--i-- + sum => ex3_pp3_1s(227) ,--o-- + car => ex3_pp3_1c(226) );--o-- + csa3_1_226: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(226) ,--i-- + b => ex3_pp2_2c(226) ,--i-- + c => ex3_pp2_2s(226) ,--i-- + sum => ex3_pp3_1s(226) ,--o-- + car => ex3_pp3_1c(225) );--o-- + csa3_1_225: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(225) ,--i-- + b => ex3_pp2_2c(225) ,--i-- + c => ex3_pp2_2s(225) ,--i-- + sum => ex3_pp3_1s(225) ,--o-- + car => ex3_pp3_1c(224) );--o-- + csa3_1_224: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(224) ,--i-- + b => ex3_pp2_2c(224) ,--i-- + c => ex3_pp2_2s(224) ,--i-- + sum => ex3_pp3_1s(224) ,--o-- + car => ex3_pp3_1c(223) );--o-- + csa3_1_223: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(223) ,--i-- + b => ex3_pp2_2c(223) ,--i-- + c => ex3_pp2_2s(223) ,--i-- + sum => ex3_pp3_1s(223) ,--o-- + car => ex3_pp3_1c(222) );--o-- + csa3_1_222: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(222) ,--i-- + b => ex3_pp2_2c(222) ,--i-- + c => ex3_pp2_2s(222) ,--i-- + sum => ex3_pp3_1s(222) ,--o-- + car => ex3_pp3_1c(221) );--o-- + csa3_1_221: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(221) ,--i-- + b => ex3_pp2_2c(221) ,--i-- + c => ex3_pp2_2s(221) ,--i-- + sum => ex3_pp3_1s(221) ,--o-- + car => ex3_pp3_1c(220) );--o-- + csa3_1_220: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp2_1s(220) ,--i-- + b => ex3_pp2_2c(220) ,--i-- + c => ex3_pp2_2s(220) ,--i-- + sum => ex3_pp3_1s(220) ,--o-- + car => ex3_pp3_1c(219) );--o-- + ex3_pp3_1s(219) <= ex3_pp2_1s(219) ; --pass_x_s + --ex3_pp3_1c(218) <= tidn ; --pass_s + ex3_pp3_1s(218) <= ex3_pp2_1s(218) ; --pass_s + --ex3_pp3_1c(217) <= tidn ; --pass_s + ex3_pp3_1s(217) <= ex3_pp2_1s(217) ; --pass_s + --ex3_pp3_1c(216) <= tidn ; --pass_s + ex3_pp3_1s(216) <= ex3_pp2_1s(216) ; --pass_s + --ex3_pp3_1c(215) <= tidn ; --pass_s + ex3_pp3_1s(215) <= ex3_pp2_1s(215) ; --pass_s + --ex3_pp3_1c(214) <= tidn ; --pass_s + ex3_pp3_1s(214) <= ex3_pp2_1s(214) ; --pass_s + --ex3_pp3_1c(213) <= tidn ; --pass_s + ex3_pp3_1s(213) <= ex3_pp2_1s(213) ; --pass_s + --ex3_pp3_1c(212) <= tidn ; --pass_s + ex3_pp3_1s(212) <= ex3_pp2_1s(212) ; --pass_s + --ex3_pp3_1c(211) <= tidn ; --pass_s + ex3_pp3_1s(211) <= ex3_pp2_1s(211) ; --pass_s + --ex3_pp3_1c(210) <= tidn ; --pass_s + ex3_pp3_1s(210) <= ex3_pp2_1s(210) ; --pass_s + --ex3_pp3_1c(209) <= tidn ; --pass_s + ex3_pp3_1s(209) <= ex3_pp2_1s(209) ; --pass_s + ex3_pp3_1s(208) <= ex3_pp2_1s(208) ; --pass_s + + + --*********************************** + --** compression level 4 + --*********************************** + +-- g4 : for i in 196 to 264 generate +-- csa4_0: entity work.c_prism_csa42 port map( +-- a => ex3_pp3_0s(i) ,--i-- +-- b => ex3_pp3_0c(i) ,--i-- +-- c => ex3_pp3_1s(i) ,--i-- +-- d => ex3_pp3_1c(i) ,--i-- +-- ki => ex3_pp4_0k(i) ,--i-- +-- ko => ex3_pp4_0k(i - 1) ,--o-- +-- sum => ex3_pp4_0s(i) ,--o-- +-- car => ex3_pp4_0c(i - 1) );--o-- +-- end generate; +-- ex3_pp4_0k(264) <= tidn ; +-- ex3_pp4_0c(264) <= tidn ; + + + + ------- ----- + + ex3_pp4_0s(264) <= ex3_pp3_1s(264) ; --pass_s + ex3_pp4_0s(263) <= ex3_pp3_1s(263) ; --pass_s + ex3_pp4_0c(262) <= ex3_pp3_1s(262) ; --pass_cs + ex3_pp4_0s(262) <= ex3_pp3_1c(262) ; --pass_cs + ex3_pp4_0c(261) <= ex3_pp3_1s(261) ; --pass_cs + ex3_pp4_0s(261) <= ex3_pp3_1c(261) ; --pass_cs + ex3_pp4_0c(260) <= tidn ; --pass_s + ex3_pp4_0s(260) <= ex3_pp3_1s(260) ; --pass_s + ex3_pp4_0c(259) <= ex3_pp3_1s(259) ; --pass_cs + ex3_pp4_0s(259) <= ex3_pp3_1c(259) ; --pass_cs + ex3_pp4_0c(258) <= ex3_pp3_1s(258) ; --pass_cs + ex3_pp4_0s(258) <= ex3_pp3_1c(258) ; --pass_cs + ex3_pp4_0c(257) <= ex3_pp3_1s(257) ; --pass_cs + ex3_pp4_0s(257) <= ex3_pp3_1c(257) ; --pass_cs + ex3_pp4_0c(256) <= ex3_pp3_1s(256) ; --pass_cs + ex3_pp4_0s(256) <= ex3_pp3_1c(256) ; --pass_cs + ex3_pp4_0c(255) <= ex3_pp3_1s(255) ; --pass_cs + ex3_pp4_0s(255) <= ex3_pp3_1c(255) ; --pass_cs + ex3_pp4_0c(254) <= tidn ; --pass_s + ex3_pp4_0s(254) <= ex3_pp3_1s(254) ; --pass_s + ex3_pp4_0c(253) <= ex3_pp3_1s(253) ; --pass_cs + ex3_pp4_0s(253) <= ex3_pp3_1c(253) ; --pass_cs + ex3_pp4_0c(252) <= tidn ; --wr_csa32 + csa4_0_252: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0s(252) ,--i-- + b => ex3_pp3_1c(252) ,--i-- + c => ex3_pp3_1s(252) ,--i-- + sum => ex3_pp4_0s(252) ,--o-- + car => ex3_pp4_0c(251) );--o-- + csa4_0_251: entity work.xuq_alu_mult_csa22 port map( + a => ex3_pp3_1c(251) ,--i-- + b => ex3_pp3_1s(251) ,--i-- + sum => ex3_pp4_0s(251) ,--o-- + car => ex3_pp4_0c(250) );--o-- + csa4_0_250: entity work.xuq_alu_mult_csa22 port map( + a => ex3_pp3_1c(250) ,--i-- + b => ex3_pp3_1s(250) ,--i-- + sum => ex3_pp4_0s(250) ,--o-- + car => ex3_pp4_0c(249) );--o-- + csa4_0_249: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0s(249) ,--i-- + b => ex3_pp3_1c(249) ,--i-- + c => ex3_pp3_1s(249) ,--i-- + sum => ex3_pp4_0s(249) ,--o-- + car => ex3_pp4_0c(248) );--o-- + csa4_0_248: entity work.xuq_alu_mult_csa22 port map( + a => ex3_pp3_1c(248) ,--i-- + b => ex3_pp3_1s(248) ,--i-- + sum => ex3_pp4_0s(248) ,--o-- + car => ex3_pp4_0c(247) );--o-- + csa4_0_247: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0s(247) ,--i-- + b => ex3_pp3_1c(247) ,--i-- + c => ex3_pp3_1s(247) ,--i-- + sum => ex3_pp4_0s(247) ,--o-- + car => ex3_pp4_0c(246) );--o-- + csa4_0_246: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0s(246) ,--i-- + b => ex3_pp3_1c(246) ,--i-- + c => ex3_pp3_1s(246) ,--i-- + sum => ex3_pp4_0s(246) ,--o-- + car => ex3_pp4_0c(245) );--o-- + csa4_0_245: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0s(245) ,--i-- + b => ex3_pp3_1c(245) ,--i-- + c => ex3_pp3_1s(245) ,--i-- + sum => ex3_pp4_0s(245) ,--o-- + car => ex3_pp4_0c(244) );--o-- + csa4_0_244: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0s(244) ,--i-- + b => ex3_pp3_1c(244) ,--i-- + c => ex3_pp3_1s(244) ,--i-- + sum => ex3_pp4_0s(244) ,--o-- + car => ex3_pp4_0c(243) );--o-- + csa4_0_243: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0s(243) ,--i-- + b => ex3_pp3_1c(243) ,--i-- + c => ex3_pp3_1s(243) ,--i-- + sum => ex3_pp4_0s(243) ,--o-- + car => ex3_pp4_0c(242) );--o-- + ex3_pp4_0k(242) <= tidn ; --start_k + csa4_0_242: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(242) ,--i-- + b => ex3_pp3_0s(242) ,--i-- + c => ex3_pp3_1c(242) ,--i-- + d => ex3_pp3_1s(242) ,--i-- + ki => ex3_pp4_0k(242) ,--i-- + ko => ex3_pp4_0k(241) ,--o-- + sum => ex3_pp4_0s(242) ,--o-- + car => ex3_pp4_0c(241) );--o-- + csa4_0_241: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0s(241) ,--i-- + b => ex3_pp3_1c(241) ,--i-- + c => ex3_pp3_1s(241) ,--i-- + d => tidn ,--i-- + ki => ex3_pp4_0k(241) ,--i-- + ko => ex3_pp4_0k(240) ,--o-- + sum => ex3_pp4_0s(241) ,--o-- + car => ex3_pp4_0c(240) );--o-- + csa4_0_240: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0s(240) ,--i-- + b => ex3_pp3_1c(240) ,--i-- + c => ex3_pp3_1s(240) ,--i-- + d => tidn ,--i-- + ki => ex3_pp4_0k(240) ,--i-- + ko => ex3_pp4_0k(239) ,--o-- + sum => ex3_pp4_0s(240) ,--o-- + car => ex3_pp4_0c(239) );--o-- + csa4_0_239: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(239) ,--i-- + b => ex3_pp3_0s(239) ,--i-- + c => ex3_pp3_1c(239) ,--i-- + d => ex3_pp3_1s(239) ,--i-- + ki => ex3_pp4_0k(239) ,--i-- + ko => ex3_pp4_0k(238) ,--o-- + sum => ex3_pp4_0s(239) ,--o-- + car => ex3_pp4_0c(238) );--o-- + csa4_0_238: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(238) ,--i-- + b => ex3_pp3_0s(238) ,--i-- + c => ex3_pp3_1c(238) ,--i-- + d => ex3_pp3_1s(238) ,--i-- + ki => ex3_pp4_0k(238) ,--i-- + ko => ex3_pp4_0k(237) ,--o-- + sum => ex3_pp4_0s(238) ,--o-- + car => ex3_pp4_0c(237) );--o-- + csa4_0_237: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(237) ,--i-- + b => ex3_pp3_0s(237) ,--i-- + c => ex3_pp3_1c(237) ,--i-- + d => ex3_pp3_1s(237) ,--i-- + ki => ex3_pp4_0k(237) ,--i-- + ko => ex3_pp4_0k(236) ,--o-- + sum => ex3_pp4_0s(237) ,--o-- + car => ex3_pp4_0c(236) );--o-- + csa4_0_236: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(236) ,--i-- + b => ex3_pp3_0s(236) ,--i-- + c => ex3_pp3_1c(236) ,--i-- + d => ex3_pp3_1s(236) ,--i-- + ki => ex3_pp4_0k(236) ,--i-- + ko => ex3_pp4_0k(235) ,--o-- + sum => ex3_pp4_0s(236) ,--o-- + car => ex3_pp4_0c(235) );--o-- + csa4_0_235: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(235) ,--i-- + b => ex3_pp3_0s(235) ,--i-- + c => ex3_pp3_1c(235) ,--i-- + d => ex3_pp3_1s(235) ,--i-- + ki => ex3_pp4_0k(235) ,--i-- + ko => ex3_pp4_0k(234) ,--o-- + sum => ex3_pp4_0s(235) ,--o-- + car => ex3_pp4_0c(234) );--o-- + csa4_0_234: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(234) ,--i-- + b => ex3_pp3_0s(234) ,--i-- + c => ex3_pp3_1c(234) ,--i-- + d => ex3_pp3_1s(234) ,--i-- + ki => ex3_pp4_0k(234) ,--i-- + ko => ex3_pp4_0k(233) ,--o-- + sum => ex3_pp4_0s(234) ,--o-- + car => ex3_pp4_0c(233) );--o-- + csa4_0_233: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(233) ,--i-- + b => ex3_pp3_0s(233) ,--i-- + c => ex3_pp3_1c(233) ,--i-- + d => ex3_pp3_1s(233) ,--i-- + ki => ex3_pp4_0k(233) ,--i-- + ko => ex3_pp4_0k(232) ,--o-- + sum => ex3_pp4_0s(233) ,--o-- + car => ex3_pp4_0c(232) );--o-- + csa4_0_232: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(232) ,--i-- + b => ex3_pp3_0s(232) ,--i-- + c => ex3_pp3_1c(232) ,--i-- + d => ex3_pp3_1s(232) ,--i-- + ki => ex3_pp4_0k(232) ,--i-- + ko => ex3_pp4_0k(231) ,--o-- + sum => ex3_pp4_0s(232) ,--o-- + car => ex3_pp4_0c(231) );--o-- + csa4_0_231: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(231) ,--i-- + b => ex3_pp3_0s(231) ,--i-- + c => ex3_pp3_1c(231) ,--i-- + d => ex3_pp3_1s(231) ,--i-- + ki => ex3_pp4_0k(231) ,--i-- + ko => ex3_pp4_0k(230) ,--o-- + sum => ex3_pp4_0s(231) ,--o-- + car => ex3_pp4_0c(230) );--o-- + csa4_0_230: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(230) ,--i-- + b => ex3_pp3_0s(230) ,--i-- + c => ex3_pp3_1c(230) ,--i-- + d => ex3_pp3_1s(230) ,--i-- + ki => ex3_pp4_0k(230) ,--i-- + ko => ex3_pp4_0k(229) ,--o-- + sum => ex3_pp4_0s(230) ,--o-- + car => ex3_pp4_0c(229) );--o-- + csa4_0_229: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(229) ,--i-- + b => ex3_pp3_0s(229) ,--i-- + c => ex3_pp3_1c(229) ,--i-- + d => ex3_pp3_1s(229) ,--i-- + ki => ex3_pp4_0k(229) ,--i-- + ko => ex3_pp4_0k(228) ,--o-- + sum => ex3_pp4_0s(229) ,--o-- + car => ex3_pp4_0c(228) );--o-- + csa4_0_228: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(228) ,--i-- + b => ex3_pp3_0s(228) ,--i-- + c => ex3_pp3_1c(228) ,--i-- + d => ex3_pp3_1s(228) ,--i-- + ki => ex3_pp4_0k(228) ,--i-- + ko => ex3_pp4_0k(227) ,--o-- + sum => ex3_pp4_0s(228) ,--o-- + car => ex3_pp4_0c(227) );--o-- + csa4_0_227: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(227) ,--i-- + b => ex3_pp3_0s(227) ,--i-- + c => ex3_pp3_1c(227) ,--i-- + d => ex3_pp3_1s(227) ,--i-- + ki => ex3_pp4_0k(227) ,--i-- + ko => ex3_pp4_0k(226) ,--o-- + sum => ex3_pp4_0s(227) ,--o-- + car => ex3_pp4_0c(226) );--o-- + csa4_0_226: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(226) ,--i-- + b => ex3_pp3_0s(226) ,--i-- + c => ex3_pp3_1c(226) ,--i-- + d => ex3_pp3_1s(226) ,--i-- + ki => ex3_pp4_0k(226) ,--i-- + ko => ex3_pp4_0k(225) ,--o-- + sum => ex3_pp4_0s(226) ,--o-- + car => ex3_pp4_0c(225) );--o-- + csa4_0_225: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(225) ,--i-- + b => ex3_pp3_0s(225) ,--i-- + c => ex3_pp3_1c(225) ,--i-- + d => ex3_pp3_1s(225) ,--i-- + ki => ex3_pp4_0k(225) ,--i-- + ko => ex3_pp4_0k(224) ,--o-- + sum => ex3_pp4_0s(225) ,--o-- + car => ex3_pp4_0c(224) );--o-- + csa4_0_224: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(224) ,--i-- + b => ex3_pp3_0s(224) ,--i-- + c => ex3_pp3_1c(224) ,--i-- + d => ex3_pp3_1s(224) ,--i-- + ki => ex3_pp4_0k(224) ,--i-- + ko => ex3_pp4_0k(223) ,--o-- + sum => ex3_pp4_0s(224) ,--o-- + car => ex3_pp4_0c(223) );--o-- + csa4_0_223: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(223) ,--i-- + b => ex3_pp3_0s(223) ,--i-- + c => ex3_pp3_1c(223) ,--i-- + d => ex3_pp3_1s(223) ,--i-- + ki => ex3_pp4_0k(223) ,--i-- + ko => ex3_pp4_0k(222) ,--o-- + sum => ex3_pp4_0s(223) ,--o-- + car => ex3_pp4_0c(222) );--o-- + csa4_0_222: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(222) ,--i-- + b => ex3_pp3_0s(222) ,--i-- + c => ex3_pp3_1c(222) ,--i-- + d => ex3_pp3_1s(222) ,--i-- + ki => ex3_pp4_0k(222) ,--i-- + ko => ex3_pp4_0k(221) ,--o-- + sum => ex3_pp4_0s(222) ,--o-- + car => ex3_pp4_0c(221) );--o-- + csa4_0_221: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(221) ,--i-- + b => ex3_pp3_0s(221) ,--i-- + c => ex3_pp3_1c(221) ,--i-- + d => ex3_pp3_1s(221) ,--i-- + ki => ex3_pp4_0k(221) ,--i-- + ko => ex3_pp4_0k(220) ,--o-- + sum => ex3_pp4_0s(221) ,--o-- + car => ex3_pp4_0c(220) );--o-- + csa4_0_220: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(220) ,--i-- + b => ex3_pp3_0s(220) ,--i-- + c => ex3_pp3_1c(220) ,--i-- + d => ex3_pp3_1s(220) ,--i-- + ki => ex3_pp4_0k(220) ,--i-- + ko => ex3_pp4_0k(219) ,--o-- + sum => ex3_pp4_0s(220) ,--o-- + car => ex3_pp4_0c(219) );--o-- + csa4_0_219: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(219) ,--i-- + b => ex3_pp3_0s(219) ,--i-- + c => ex3_pp3_1c(219) ,--i-- + d => ex3_pp3_1s(219) ,--i-- + ki => ex3_pp4_0k(219) ,--i-- + ko => ex3_pp4_0k(218) ,--o-- + sum => ex3_pp4_0s(219) ,--o-- + car => ex3_pp4_0c(218) );--o-- + csa4_0_218: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(218) ,--i-- + b => ex3_pp3_0s(218) ,--i-- + c => ex3_pp3_1s(218) ,--i-- + d => tidn ,--i-- + ki => ex3_pp4_0k(218) ,--i-- + ko => ex3_pp4_0k(217) ,--o-- + sum => ex3_pp4_0s(218) ,--o-- + car => ex3_pp4_0c(217) );--o-- + csa4_0_217: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(217) ,--i-- + b => ex3_pp3_0s(217) ,--i-- + c => ex3_pp3_1s(217) ,--i-- + d => tidn ,--i-- + ki => ex3_pp4_0k(217) ,--i-- + ko => ex3_pp4_0k(216) ,--o-- + sum => ex3_pp4_0s(217) ,--o-- + car => ex3_pp4_0c(216) );--o-- + csa4_0_216: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(216) ,--i-- + b => ex3_pp3_0s(216) ,--i-- + c => ex3_pp3_1s(216) ,--i-- + d => tidn ,--i-- + ki => ex3_pp4_0k(216) ,--i-- + ko => ex3_pp4_0k(215) ,--o-- + sum => ex3_pp4_0s(216) ,--o-- + car => ex3_pp4_0c(215) );--o-- + csa4_0_215: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(215) ,--i-- + b => ex3_pp3_0s(215) ,--i-- + c => ex3_pp3_1s(215) ,--i-- + d => tidn ,--i-- + ki => ex3_pp4_0k(215) ,--i-- + ko => ex3_pp4_0k(214) ,--o-- + sum => ex3_pp4_0s(215) ,--o-- + car => ex3_pp4_0c(214) );--o-- + csa4_0_214: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(214) ,--i-- + b => ex3_pp3_0s(214) ,--i-- + c => ex3_pp3_1s(214) ,--i-- + d => tidn ,--i-- + ki => ex3_pp4_0k(214) ,--i-- + ko => ex3_pp4_0k(213) ,--o-- + sum => ex3_pp4_0s(214) ,--o-- + car => ex3_pp4_0c(213) );--o-- + csa4_0_213: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(213) ,--i-- + b => ex3_pp3_0s(213) ,--i-- + c => ex3_pp3_1s(213) ,--i-- + d => tidn ,--i-- + ki => ex3_pp4_0k(213) ,--i-- + ko => ex3_pp4_0k(212) ,--o-- + sum => ex3_pp4_0s(213) ,--o-- + car => ex3_pp4_0c(212) );--o-- + csa4_0_212: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(212) ,--i-- + b => ex3_pp3_0s(212) ,--i-- + c => ex3_pp3_1s(212) ,--i-- + d => tidn ,--i-- + ki => ex3_pp4_0k(212) ,--i-- + ko => ex3_pp4_0k(211) ,--o-- + sum => ex3_pp4_0s(212) ,--o-- + car => ex3_pp4_0c(211) );--o-- + csa4_0_211: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(211) ,--i-- + b => ex3_pp3_0s(211) ,--i-- + c => ex3_pp3_1s(211) ,--i-- + d => tidn ,--i-- + ki => ex3_pp4_0k(211) ,--i-- + ko => ex3_pp4_0k(210) ,--o-- + sum => ex3_pp4_0s(211) ,--o-- + car => ex3_pp4_0c(210) );--o-- + csa4_0_210: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(210) ,--i-- + b => ex3_pp3_0s(210) ,--i-- + c => ex3_pp3_1s(210) ,--i-- + d => tidn ,--i-- + ki => ex3_pp4_0k(210) ,--i-- + ko => ex3_pp4_0k(209) ,--o-- + sum => ex3_pp4_0s(210) ,--o-- + car => ex3_pp4_0c(209) );--o-- + csa4_0_209: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(209) ,--i-- + b => ex3_pp3_0s(209) ,--i-- + c => ex3_pp3_1s(209) ,--i-- + d => tidn ,--i-- + ki => ex3_pp4_0k(209) ,--i-- + ko => ex3_pp4_0k(208) ,--o-- + sum => ex3_pp4_0s(209) ,--o-- + car => ex3_pp4_0c(208) );--o-- + csa4_0_208: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(208) ,--i-- + b => ex3_pp3_0s(208) ,--i-- + c => ex3_pp3_1s(208) ,--i-- + d => tidn ,--i-- + ki => ex3_pp4_0k(208) ,--i-- + ko => ex3_pp4_0k(207) ,--o-- + sum => ex3_pp4_0s(208) ,--o-- + car => ex3_pp4_0c(207) );--o-- + csa4_0_207: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp3_0c(207) ,--i-- + b => ex3_pp3_0s(207) ,--i-- + c => ex3_pp4_0k(207) ,--i-- + sum => ex3_pp4_0s(207) ,--o-- + car => ex3_pp4_0c(206) );--o-- + csa4_0_206: entity work.xuq_alu_mult_csa22 port map( + a => ex3_pp3_0c(206) ,--i-- + b => ex3_pp3_0s(206) ,--i-- + sum => ex3_pp4_0s(206) ,--o-- + car => ex3_pp4_0c(205) );--o-- + csa4_0_205: entity work.xuq_alu_mult_csa22 port map( + a => ex3_pp3_0c(205) ,--i-- + b => ex3_pp3_0s(205) ,--i-- + sum => ex3_pp4_0s(205) ,--o-- + car => ex3_pp4_0c(204) );--o-- + csa4_0_204: entity work.xuq_alu_mult_csa22 port map( + a => ex3_pp3_0c(204) ,--i-- + b => ex3_pp3_0s(204) ,--i-- + sum => ex3_pp4_0s(204) ,--o-- + car => ex3_pp4_0c(203) );--o-- + csa4_0_203: entity work.xuq_alu_mult_csa22 port map( + a => ex3_pp3_0c(203) ,--i-- + b => ex3_pp3_0s(203) ,--i-- + sum => ex3_pp4_0s(203) ,--o-- + car => ex3_pp4_0c(202) );--o-- + csa4_0_202: entity work.xuq_alu_mult_csa22 port map( + a => ex3_pp3_0c(202) ,--i-- + b => ex3_pp3_0s(202) ,--i-- + sum => ex3_pp4_0s(202) ,--o-- + car => ex3_pp4_0c(201) );--o-- + csa4_0_201: entity work.xuq_alu_mult_csa22 port map( + a => ex3_pp3_0c(201) ,--i-- + b => ex3_pp3_0s(201) ,--i-- + sum => ex3_pp4_0s(201) ,--o-- + car => ex3_pp4_0c(200) );--o-- + csa4_0_200: entity work.xuq_alu_mult_csa22 port map( + a => ex3_pp3_0c(200) ,--i-- + b => ex3_pp3_0s(200) ,--i-- + sum => ex3_pp4_0s(200) ,--o-- + car => ex3_pp4_0c(199) );--o-- + csa4_0_199: entity work.xuq_alu_mult_csa22 port map( + a => ex3_pp3_0c(199) ,--i-- + b => ex3_pp3_0s(199) ,--i-- + sum => ex3_pp4_0s(199) ,--o-- + car => ex3_pp4_0c(198) );--o-- + csa4_0_198: entity work.xuq_alu_mult_csa22 port map( + a => ex3_pp3_0c(198) ,--i-- + b => ex3_pp3_0s(198) ,--i-- + sum => ex3_pp4_0s(198) ,--o-- + car => ex3_pp4_0c(197) );--o-- + ex3_pp4_0s(197) <= ex3_pp3_0c(197) ; --pass_x_s + + + + + --*********************************** + --** compression recycle + --*********************************** + +-- g5 : for i in 196 to 264 generate +-- +-- csa5_0: entity work.c_prism_csa42 port map( +-- a => ex3_pp4_0s(i) ,--i-- +-- b => ex3_pp4_0c(i) ,--i-- +-- c => ex3_recycle_s(i) ,--i-- +-- d => ex3_recycle_c(i) ,--i-- +-- ki => ex3_pp5_0k(i) ,--i-- +-- ko => ex3_pp5_0k(i - 1) ,--o-- +-- sum => ex3_pp5_0s(i) ,--o-- +-- car => ex3_pp5_0c(i - 1) );--o-- +-- +-- end generate; +-- +-- ex3_pp5_0k(264) <= tidn ; +-- ex3_pp5_0c(264) <= tidn ; + + + + ------- ----- + + csa5_0_264: entity work.xuq_alu_mult_csa22 port map( + a => ex3_pp4_0s(264) ,--i-- + b => ex3_recycle_s(264) ,--i-- + sum => ex3_pp5_0s(264) ,--o-- + car => ex3_pp5_0c(263) );--o-- + csa5_0_263: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0s(263) ,--i-- + b => ex3_recycle_c(263) ,--i-- + c => ex3_recycle_s(263) ,--i-- + sum => ex3_pp5_0s(263) ,--o-- + car => ex3_pp5_0c(262) );--o-- + ex3_pp5_0k(262) <= tidn ; --start_k + csa5_0_262: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(262) ,--i-- + b => ex3_pp4_0s(262) ,--i-- + c => ex3_recycle_c(262) ,--i-- + d => ex3_recycle_s(262) ,--i-- + ki => ex3_pp5_0k(262) ,--i-- + ko => ex3_pp5_0k(261) ,--o-- + sum => ex3_pp5_0s(262) ,--o-- + car => ex3_pp5_0c(261) );--o-- + csa5_0_261: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(261) ,--i-- + b => ex3_pp4_0s(261) ,--i-- + c => ex3_recycle_c(261) ,--i-- + d => ex3_recycle_s(261) ,--i-- + ki => ex3_pp5_0k(261) ,--i-- + ko => ex3_pp5_0k(260) ,--o-- + sum => ex3_pp5_0s(261) ,--o-- + car => ex3_pp5_0c(260) );--o-- + csa5_0_260: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0s(260) ,--i-- + b => ex3_recycle_c(260) ,--i-- + c => ex3_recycle_s(260) ,--i-- + d => tidn ,--i-- + ki => ex3_pp5_0k(260) ,--i-- + ko => ex3_pp5_0k(259) ,--o-- + sum => ex3_pp5_0s(260) ,--o-- + car => ex3_pp5_0c(259) );--o-- + csa5_0_259: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(259) ,--i-- + b => ex3_pp4_0s(259) ,--i-- + c => ex3_recycle_c(259) ,--i-- + d => ex3_recycle_s(259) ,--i-- + ki => ex3_pp5_0k(259) ,--i-- + ko => ex3_pp5_0k(258) ,--o-- + sum => ex3_pp5_0s(259) ,--o-- + car => ex3_pp5_0c(258) );--o-- + csa5_0_258: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(258) ,--i-- + b => ex3_pp4_0s(258) ,--i-- + c => ex3_recycle_c(258) ,--i-- + d => ex3_recycle_s(258) ,--i-- + ki => ex3_pp5_0k(258) ,--i-- + ko => ex3_pp5_0k(257) ,--o-- + sum => ex3_pp5_0s(258) ,--o-- + car => ex3_pp5_0c(257) );--o-- + csa5_0_257: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(257) ,--i-- + b => ex3_pp4_0s(257) ,--i-- + c => ex3_recycle_c(257) ,--i-- + d => ex3_recycle_s(257) ,--i-- + ki => ex3_pp5_0k(257) ,--i-- + ko => ex3_pp5_0k(256) ,--o-- + sum => ex3_pp5_0s(257) ,--o-- + car => ex3_pp5_0c(256) );--o-- + csa5_0_256: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(256) ,--i-- + b => ex3_pp4_0s(256) ,--i-- + c => ex3_recycle_c(256) ,--i-- + d => ex3_recycle_s(256) ,--i-- + ki => ex3_pp5_0k(256) ,--i-- + ko => ex3_pp5_0k(255) ,--o-- + sum => ex3_pp5_0s(256) ,--o-- + car => ex3_pp5_0c(255) );--o-- + csa5_0_255: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(255) ,--i-- + b => ex3_pp4_0s(255) ,--i-- + c => ex3_recycle_c(255) ,--i-- + d => ex3_recycle_s(255) ,--i-- + ki => ex3_pp5_0k(255) ,--i-- + ko => ex3_pp5_0k(254) ,--o-- + sum => ex3_pp5_0s(255) ,--o-- + car => ex3_pp5_0c(254) );--o-- + csa5_0_254: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0s(254) ,--i-- + b => ex3_recycle_c(254) ,--i-- + c => ex3_recycle_s(254) ,--i-- + d => tidn ,--i-- + ki => ex3_pp5_0k(254) ,--i-- + ko => ex3_pp5_0k(253) ,--o-- + sum => ex3_pp5_0s(254) ,--o-- + car => ex3_pp5_0c(253) );--o-- + csa5_0_253: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(253) ,--i-- + b => ex3_pp4_0s(253) ,--i-- + c => ex3_recycle_c(253) ,--i-- + d => ex3_recycle_s(253) ,--i-- + ki => ex3_pp5_0k(253) ,--i-- + ko => ex3_pp5_0k(252) ,--o-- + sum => ex3_pp5_0s(253) ,--o-- + car => ex3_pp5_0c(252) );--o-- + csa5_0_252: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0s(252) ,--i-- + b => ex3_recycle_c(252) ,--i-- + c => ex3_recycle_s(252) ,--i-- + d => tidn ,--i-- + ki => ex3_pp5_0k(252) ,--i-- + ko => ex3_pp5_0k(251) ,--o-- + sum => ex3_pp5_0s(252) ,--o-- + car => ex3_pp5_0c(251) );--o-- + csa5_0_251: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(251) ,--i-- + b => ex3_pp4_0s(251) ,--i-- + c => ex3_recycle_c(251) ,--i-- + d => ex3_recycle_s(251) ,--i-- + ki => ex3_pp5_0k(251) ,--i-- + ko => ex3_pp5_0k(250) ,--o-- + sum => ex3_pp5_0s(251) ,--o-- + car => ex3_pp5_0c(250) );--o-- + csa5_0_250: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(250) ,--i-- + b => ex3_pp4_0s(250) ,--i-- + c => ex3_recycle_c(250) ,--i-- + d => ex3_recycle_s(250) ,--i-- + ki => ex3_pp5_0k(250) ,--i-- + ko => ex3_pp5_0k(249) ,--o-- + sum => ex3_pp5_0s(250) ,--o-- + car => ex3_pp5_0c(249) );--o-- + csa5_0_249: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(249) ,--i-- + b => ex3_pp4_0s(249) ,--i-- + c => ex3_recycle_c(249) ,--i-- + d => ex3_recycle_s(249) ,--i-- + ki => ex3_pp5_0k(249) ,--i-- + ko => ex3_pp5_0k(248) ,--o-- + sum => ex3_pp5_0s(249) ,--o-- + car => ex3_pp5_0c(248) );--o-- + csa5_0_248: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(248) ,--i-- + b => ex3_pp4_0s(248) ,--i-- + c => ex3_recycle_c(248) ,--i-- + d => ex3_recycle_s(248) ,--i-- + ki => ex3_pp5_0k(248) ,--i-- + ko => ex3_pp5_0k(247) ,--o-- + sum => ex3_pp5_0s(248) ,--o-- + car => ex3_pp5_0c(247) );--o-- + csa5_0_247: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(247) ,--i-- + b => ex3_pp4_0s(247) ,--i-- + c => ex3_recycle_c(247) ,--i-- + d => ex3_recycle_s(247) ,--i-- + ki => ex3_pp5_0k(247) ,--i-- + ko => ex3_pp5_0k(246) ,--o-- + sum => ex3_pp5_0s(247) ,--o-- + car => ex3_pp5_0c(246) );--o-- + csa5_0_246: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(246) ,--i-- + b => ex3_pp4_0s(246) ,--i-- + c => ex3_recycle_c(246) ,--i-- + d => ex3_recycle_s(246) ,--i-- + ki => ex3_pp5_0k(246) ,--i-- + ko => ex3_pp5_0k(245) ,--o-- + sum => ex3_pp5_0s(246) ,--o-- + car => ex3_pp5_0c(245) );--o-- + csa5_0_245: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(245) ,--i-- + b => ex3_pp4_0s(245) ,--i-- + c => ex3_recycle_c(245) ,--i-- + d => ex3_recycle_s(245) ,--i-- + ki => ex3_pp5_0k(245) ,--i-- + ko => ex3_pp5_0k(244) ,--o-- + sum => ex3_pp5_0s(245) ,--o-- + car => ex3_pp5_0c(244) );--o-- + csa5_0_244: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(244) ,--i-- + b => ex3_pp4_0s(244) ,--i-- + c => ex3_recycle_c(244) ,--i-- + d => ex3_recycle_s(244) ,--i-- + ki => ex3_pp5_0k(244) ,--i-- + ko => ex3_pp5_0k(243) ,--o-- + sum => ex3_pp5_0s(244) ,--o-- + car => ex3_pp5_0c(243) );--o-- + csa5_0_243: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(243) ,--i-- + b => ex3_pp4_0s(243) ,--i-- + c => ex3_recycle_c(243) ,--i-- + d => ex3_recycle_s(243) ,--i-- + ki => ex3_pp5_0k(243) ,--i-- + ko => ex3_pp5_0k(242) ,--o-- + sum => ex3_pp5_0s(243) ,--o-- + car => ex3_pp5_0c(242) );--o-- + csa5_0_242: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(242) ,--i-- + b => ex3_pp4_0s(242) ,--i-- + c => ex3_recycle_c(242) ,--i-- + d => ex3_recycle_s(242) ,--i-- + ki => ex3_pp5_0k(242) ,--i-- + ko => ex3_pp5_0k(241) ,--o-- + sum => ex3_pp5_0s(242) ,--o-- + car => ex3_pp5_0c(241) );--o-- + csa5_0_241: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(241) ,--i-- + b => ex3_pp4_0s(241) ,--i-- + c => ex3_recycle_c(241) ,--i-- + d => ex3_recycle_s(241) ,--i-- + ki => ex3_pp5_0k(241) ,--i-- + ko => ex3_pp5_0k(240) ,--o-- + sum => ex3_pp5_0s(241) ,--o-- + car => ex3_pp5_0c(240) );--o-- + csa5_0_240: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(240) ,--i-- + b => ex3_pp4_0s(240) ,--i-- + c => ex3_recycle_c(240) ,--i-- + d => ex3_recycle_s(240) ,--i-- + ki => ex3_pp5_0k(240) ,--i-- + ko => ex3_pp5_0k(239) ,--o-- + sum => ex3_pp5_0s(240) ,--o-- + car => ex3_pp5_0c(239) );--o-- + csa5_0_239: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(239) ,--i-- + b => ex3_pp4_0s(239) ,--i-- + c => ex3_recycle_c(239) ,--i-- + d => ex3_recycle_s(239) ,--i-- + ki => ex3_pp5_0k(239) ,--i-- + ko => ex3_pp5_0k(238) ,--o-- + sum => ex3_pp5_0s(239) ,--o-- + car => ex3_pp5_0c(238) );--o-- + csa5_0_238: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(238) ,--i-- + b => ex3_pp4_0s(238) ,--i-- + c => ex3_recycle_c(238) ,--i-- + d => ex3_recycle_s(238) ,--i-- + ki => ex3_pp5_0k(238) ,--i-- + ko => ex3_pp5_0k(237) ,--o-- + sum => ex3_pp5_0s(238) ,--o-- + car => ex3_pp5_0c(237) );--o-- + csa5_0_237: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(237) ,--i-- + b => ex3_pp4_0s(237) ,--i-- + c => ex3_recycle_c(237) ,--i-- + d => ex3_recycle_s(237) ,--i-- + ki => ex3_pp5_0k(237) ,--i-- + ko => ex3_pp5_0k(236) ,--o-- + sum => ex3_pp5_0s(237) ,--o-- + car => ex3_pp5_0c(236) );--o-- + csa5_0_236: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(236) ,--i-- + b => ex3_pp4_0s(236) ,--i-- + c => ex3_recycle_c(236) ,--i-- + d => ex3_recycle_s(236) ,--i-- + ki => ex3_pp5_0k(236) ,--i-- + ko => ex3_pp5_0k(235) ,--o-- + sum => ex3_pp5_0s(236) ,--o-- + car => ex3_pp5_0c(235) );--o-- + csa5_0_235: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(235) ,--i-- + b => ex3_pp4_0s(235) ,--i-- + c => ex3_recycle_c(235) ,--i-- + d => ex3_recycle_s(235) ,--i-- + ki => ex3_pp5_0k(235) ,--i-- + ko => ex3_pp5_0k(234) ,--o-- + sum => ex3_pp5_0s(235) ,--o-- + car => ex3_pp5_0c(234) );--o-- + csa5_0_234: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(234) ,--i-- + b => ex3_pp4_0s(234) ,--i-- + c => ex3_recycle_c(234) ,--i-- + d => ex3_recycle_s(234) ,--i-- + ki => ex3_pp5_0k(234) ,--i-- + ko => ex3_pp5_0k(233) ,--o-- + sum => ex3_pp5_0s(234) ,--o-- + car => ex3_pp5_0c(233) );--o-- + csa5_0_233: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(233) ,--i-- + b => ex3_pp4_0s(233) ,--i-- + c => ex3_recycle_c(233) ,--i-- + d => ex3_recycle_s(233) ,--i-- + ki => ex3_pp5_0k(233) ,--i-- + ko => ex3_pp5_0k(232) ,--o-- + sum => ex3_pp5_0s(233) ,--o-- + car => ex3_pp5_0c(232) );--o-- + csa5_0_232: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(232) ,--i-- + b => ex3_pp4_0s(232) ,--i-- + c => ex3_recycle_c(232) ,--i-- + d => ex3_recycle_s(232) ,--i-- + ki => ex3_pp5_0k(232) ,--i-- + ko => ex3_pp5_0k(231) ,--o-- + sum => ex3_pp5_0s(232) ,--o-- + car => ex3_pp5_0c(231) );--o-- + csa5_0_231: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(231) ,--i-- + b => ex3_pp4_0s(231) ,--i-- + c => ex3_recycle_c(231) ,--i-- + d => ex3_recycle_s(231) ,--i-- + ki => ex3_pp5_0k(231) ,--i-- + ko => ex3_pp5_0k(230) ,--o-- + sum => ex3_pp5_0s(231) ,--o-- + car => ex3_pp5_0c(230) );--o-- + csa5_0_230: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(230) ,--i-- + b => ex3_pp4_0s(230) ,--i-- + c => ex3_recycle_c(230) ,--i-- + d => ex3_recycle_s(230) ,--i-- + ki => ex3_pp5_0k(230) ,--i-- + ko => ex3_pp5_0k(229) ,--o-- + sum => ex3_pp5_0s(230) ,--o-- + car => ex3_pp5_0c(229) );--o-- + csa5_0_229: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(229) ,--i-- + b => ex3_pp4_0s(229) ,--i-- + c => ex3_recycle_c(229) ,--i-- + d => ex3_recycle_s(229) ,--i-- + ki => ex3_pp5_0k(229) ,--i-- + ko => ex3_pp5_0k(228) ,--o-- + sum => ex3_pp5_0s(229) ,--o-- + car => ex3_pp5_0c(228) );--o-- + csa5_0_228: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(228) ,--i-- + b => ex3_pp4_0s(228) ,--i-- + c => ex3_recycle_c(228) ,--i-- + d => ex3_recycle_s(228) ,--i-- + ki => ex3_pp5_0k(228) ,--i-- + ko => ex3_pp5_0k(227) ,--o-- + sum => ex3_pp5_0s(228) ,--o-- + car => ex3_pp5_0c(227) );--o-- + csa5_0_227: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(227) ,--i-- + b => ex3_pp4_0s(227) ,--i-- + c => ex3_recycle_c(227) ,--i-- + d => ex3_recycle_s(227) ,--i-- + ki => ex3_pp5_0k(227) ,--i-- + ko => ex3_pp5_0k(226) ,--o-- + sum => ex3_pp5_0s(227) ,--o-- + car => ex3_pp5_0c(226) );--o-- + csa5_0_226: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(226) ,--i-- + b => ex3_pp4_0s(226) ,--i-- + c => ex3_recycle_c(226) ,--i-- + d => ex3_recycle_s(226) ,--i-- + ki => ex3_pp5_0k(226) ,--i-- + ko => ex3_pp5_0k(225) ,--o-- + sum => ex3_pp5_0s(226) ,--o-- + car => ex3_pp5_0c(225) );--o-- + csa5_0_225: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(225) ,--i-- + b => ex3_pp4_0s(225) ,--i-- + c => ex3_recycle_c(225) ,--i-- + d => ex3_recycle_s(225) ,--i-- + ki => ex3_pp5_0k(225) ,--i-- + ko => ex3_pp5_0k(224) ,--o-- + sum => ex3_pp5_0s(225) ,--o-- + car => ex3_pp5_0c(224) );--o-- + csa5_0_224: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(224) ,--i-- + b => ex3_pp4_0s(224) ,--i-- + c => ex3_recycle_c(224) ,--i-- + d => ex3_recycle_s(224) ,--i-- + ki => ex3_pp5_0k(224) ,--i-- + ko => ex3_pp5_0k(223) ,--o-- + sum => ex3_pp5_0s(224) ,--o-- + car => ex3_pp5_0c(223) );--o-- + csa5_0_223: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(223) ,--i-- + b => ex3_pp4_0s(223) ,--i-- + c => ex3_recycle_c(223) ,--i-- + d => ex3_recycle_s(223) ,--i-- + ki => ex3_pp5_0k(223) ,--i-- + ko => ex3_pp5_0k(222) ,--o-- + sum => ex3_pp5_0s(223) ,--o-- + car => ex3_pp5_0c(222) );--o-- + csa5_0_222: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(222) ,--i-- + b => ex3_pp4_0s(222) ,--i-- + c => ex3_recycle_c(222) ,--i-- + d => ex3_recycle_s(222) ,--i-- + ki => ex3_pp5_0k(222) ,--i-- + ko => ex3_pp5_0k(221) ,--o-- + sum => ex3_pp5_0s(222) ,--o-- + car => ex3_pp5_0c(221) );--o-- + csa5_0_221: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(221) ,--i-- + b => ex3_pp4_0s(221) ,--i-- + c => ex3_recycle_c(221) ,--i-- + d => ex3_recycle_s(221) ,--i-- + ki => ex3_pp5_0k(221) ,--i-- + ko => ex3_pp5_0k(220) ,--o-- + sum => ex3_pp5_0s(221) ,--o-- + car => ex3_pp5_0c(220) );--o-- + csa5_0_220: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(220) ,--i-- + b => ex3_pp4_0s(220) ,--i-- + c => ex3_recycle_c(220) ,--i-- + d => ex3_recycle_s(220) ,--i-- + ki => ex3_pp5_0k(220) ,--i-- + ko => ex3_pp5_0k(219) ,--o-- + sum => ex3_pp5_0s(220) ,--o-- + car => ex3_pp5_0c(219) );--o-- + csa5_0_219: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(219) ,--i-- + b => ex3_pp4_0s(219) ,--i-- + c => ex3_recycle_c(219) ,--i-- + d => ex3_recycle_s(219) ,--i-- + ki => ex3_pp5_0k(219) ,--i-- + ko => ex3_pp5_0k(218) ,--o-- + sum => ex3_pp5_0s(219) ,--o-- + car => ex3_pp5_0c(218) );--o-- + csa5_0_218: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(218) ,--i-- + b => ex3_pp4_0s(218) ,--i-- + c => ex3_recycle_c(218) ,--i-- + d => ex3_recycle_s(218) ,--i-- + ki => ex3_pp5_0k(218) ,--i-- + ko => ex3_pp5_0k(217) ,--o-- + sum => ex3_pp5_0s(218) ,--o-- + car => ex3_pp5_0c(217) );--o-- + csa5_0_217: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(217) ,--i-- + b => ex3_pp4_0s(217) ,--i-- + c => ex3_recycle_c(217) ,--i-- + d => ex3_recycle_s(217) ,--i-- + ki => ex3_pp5_0k(217) ,--i-- + ko => ex3_pp5_0k(216) ,--o-- + sum => ex3_pp5_0s(217) ,--o-- + car => ex3_pp5_0c(216) );--o-- + csa5_0_216: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(216) ,--i-- + b => ex3_pp4_0s(216) ,--i-- + c => ex3_recycle_c(216) ,--i-- + d => ex3_recycle_s(216) ,--i-- + ki => ex3_pp5_0k(216) ,--i-- + ko => ex3_pp5_0k(215) ,--o-- + sum => ex3_pp5_0s(216) ,--o-- + car => ex3_pp5_0c(215) );--o-- + csa5_0_215: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(215) ,--i-- + b => ex3_pp4_0s(215) ,--i-- + c => ex3_recycle_c(215) ,--i-- + d => ex3_recycle_s(215) ,--i-- + ki => ex3_pp5_0k(215) ,--i-- + ko => ex3_pp5_0k(214) ,--o-- + sum => ex3_pp5_0s(215) ,--o-- + car => ex3_pp5_0c(214) );--o-- + csa5_0_214: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(214) ,--i-- + b => ex3_pp4_0s(214) ,--i-- + c => ex3_recycle_c(214) ,--i-- + d => ex3_recycle_s(214) ,--i-- + ki => ex3_pp5_0k(214) ,--i-- + ko => ex3_pp5_0k(213) ,--o-- + sum => ex3_pp5_0s(214) ,--o-- + car => ex3_pp5_0c(213) );--o-- + csa5_0_213: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(213) ,--i-- + b => ex3_pp4_0s(213) ,--i-- + c => ex3_recycle_c(213) ,--i-- + d => ex3_recycle_s(213) ,--i-- + ki => ex3_pp5_0k(213) ,--i-- + ko => ex3_pp5_0k(212) ,--o-- + sum => ex3_pp5_0s(213) ,--o-- + car => ex3_pp5_0c(212) );--o-- + csa5_0_212: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(212) ,--i-- + b => ex3_pp4_0s(212) ,--i-- + c => ex3_recycle_c(212) ,--i-- + d => ex3_recycle_s(212) ,--i-- + ki => ex3_pp5_0k(212) ,--i-- + ko => ex3_pp5_0k(211) ,--o-- + sum => ex3_pp5_0s(212) ,--o-- + car => ex3_pp5_0c(211) );--o-- + csa5_0_211: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(211) ,--i-- + b => ex3_pp4_0s(211) ,--i-- + c => ex3_recycle_c(211) ,--i-- + d => ex3_recycle_s(211) ,--i-- + ki => ex3_pp5_0k(211) ,--i-- + ko => ex3_pp5_0k(210) ,--o-- + sum => ex3_pp5_0s(211) ,--o-- + car => ex3_pp5_0c(210) );--o-- + csa5_0_210: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(210) ,--i-- + b => ex3_pp4_0s(210) ,--i-- + c => ex3_recycle_c(210) ,--i-- + d => ex3_recycle_s(210) ,--i-- + ki => ex3_pp5_0k(210) ,--i-- + ko => ex3_pp5_0k(209) ,--o-- + sum => ex3_pp5_0s(210) ,--o-- + car => ex3_pp5_0c(209) );--o-- + csa5_0_209: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(209) ,--i-- + b => ex3_pp4_0s(209) ,--i-- + c => ex3_recycle_c(209) ,--i-- + d => ex3_recycle_s(209) ,--i-- + ki => ex3_pp5_0k(209) ,--i-- + ko => ex3_pp5_0k(208) ,--o-- + sum => ex3_pp5_0s(209) ,--o-- + car => ex3_pp5_0c(208) );--o-- + csa5_0_208: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(208) ,--i-- + b => ex3_pp4_0s(208) ,--i-- + c => ex3_recycle_c(208) ,--i-- + d => ex3_recycle_s(208) ,--i-- + ki => ex3_pp5_0k(208) ,--i-- + ko => ex3_pp5_0k(207) ,--o-- + sum => ex3_pp5_0s(208) ,--o-- + car => ex3_pp5_0c(207) );--o-- + csa5_0_207: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(207) ,--i-- + b => ex3_pp4_0s(207) ,--i-- + c => ex3_recycle_c(207) ,--i-- + d => ex3_recycle_s(207) ,--i-- + ki => ex3_pp5_0k(207) ,--i-- + ko => ex3_pp5_0k(206) ,--o-- + sum => ex3_pp5_0s(207) ,--o-- + car => ex3_pp5_0c(206) );--o-- + csa5_0_206: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(206) ,--i-- + b => ex3_pp4_0s(206) ,--i-- + c => ex3_recycle_c(206) ,--i-- + d => ex3_recycle_s(206) ,--i-- + ki => ex3_pp5_0k(206) ,--i-- + ko => ex3_pp5_0k(205) ,--o-- + sum => ex3_pp5_0s(206) ,--o-- + car => ex3_pp5_0c(205) );--o-- + csa5_0_205: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(205) ,--i-- + b => ex3_pp4_0s(205) ,--i-- + c => ex3_recycle_c(205) ,--i-- + d => ex3_recycle_s(205) ,--i-- + ki => ex3_pp5_0k(205) ,--i-- + ko => ex3_pp5_0k(204) ,--o-- + sum => ex3_pp5_0s(205) ,--o-- + car => ex3_pp5_0c(204) );--o-- + csa5_0_204: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(204) ,--i-- + b => ex3_pp4_0s(204) ,--i-- + c => ex3_recycle_c(204) ,--i-- + d => ex3_recycle_s(204) ,--i-- + ki => ex3_pp5_0k(204) ,--i-- + ko => ex3_pp5_0k(203) ,--o-- + sum => ex3_pp5_0s(204) ,--o-- + car => ex3_pp5_0c(203) );--o-- + csa5_0_203: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(203) ,--i-- + b => ex3_pp4_0s(203) ,--i-- + c => ex3_recycle_c(203) ,--i-- + d => ex3_recycle_s(203) ,--i-- + ki => ex3_pp5_0k(203) ,--i-- + ko => ex3_pp5_0k(202) ,--o-- + sum => ex3_pp5_0s(203) ,--o-- + car => ex3_pp5_0c(202) );--o-- + csa5_0_202: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(202) ,--i-- + b => ex3_pp4_0s(202) ,--i-- + c => ex3_recycle_c(202) ,--i-- + d => ex3_recycle_s(202) ,--i-- + ki => ex3_pp5_0k(202) ,--i-- + ko => ex3_pp5_0k(201) ,--o-- + sum => ex3_pp5_0s(202) ,--o-- + car => ex3_pp5_0c(201) );--o-- + csa5_0_201: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(201) ,--i-- + b => ex3_pp4_0s(201) ,--i-- + c => ex3_recycle_c(201) ,--i-- + d => ex3_recycle_s(201) ,--i-- + ki => ex3_pp5_0k(201) ,--i-- + ko => ex3_pp5_0k(200) ,--o-- + sum => ex3_pp5_0s(201) ,--o-- + car => ex3_pp5_0c(200) );--o-- + csa5_0_200: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(200) ,--i-- + b => ex3_pp4_0s(200) ,--i-- + c => ex3_recycle_c(200) ,--i-- + d => ex3_recycle_s(200) ,--i-- + ki => ex3_pp5_0k(200) ,--i-- + ko => ex3_pp5_0k(199) ,--o-- + sum => ex3_pp5_0s(200) ,--o-- + car => ex3_pp5_0c(199) );--o-- + csa5_0_199: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(199) ,--i-- + b => ex3_pp4_0s(199) ,--i-- + c => ex3_recycle_c(199) ,--i-- + d => ex3_recycle_s(199) ,--i-- + ki => ex3_pp5_0k(199) ,--i-- + ko => ex3_pp5_0k(198) ,--o-- + sum => ex3_pp5_0s(199) ,--o-- + car => ex3_pp5_0c(198) );--o-- + csa5_0_198: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(198) ,--i-- + b => ex3_pp4_0s(198) ,--i-- + c => ex3_recycle_c(198) ,--i-- + d => ex3_recycle_s(198) ,--i-- + ki => ex3_pp5_0k(198) ,--i-- + ko => ex3_pp5_0k(197) ,--o-- + sum => ex3_pp5_0s(198) ,--o-- + car => ex3_pp5_0c(197) );--o-- + csa5_0_197: entity clib.c_prism_csa42 port map( + vd => vdd, + gd => gnd, + a => ex3_pp4_0c(197) ,--i-- + b => ex3_pp4_0s(197) ,--i-- + c => ex3_recycle_c(197) ,--i-- + d => ex3_recycle_s(197) ,--i-- + ki => ex3_pp5_0k(197) ,--i-- + ko => ex3_pp5_0k(196) ,--o-- + sum => ex3_pp5_0s(197) ,--o-- + car => ex3_pp5_0c(196) );--o-- + csa5_0_196: entity clib.c_prism_csa32 port map( + vd => vdd, + gd => gnd, + a => ex3_recycle_c(196) ,--i-- + b => ex3_recycle_s(196) ,--i-- + c => ex3_pp5_0k(196) ,--i-- + sum => ex3_pp5_0s(196) ,--o-- + car => ex3_pp5_0c(195) );--o-- + + + + + ex4_pp5_0s_din(196 to 264) <= ex3_pp5_0s(196 to 264); + ex4_pp5_0c_din(196 to 263) <= ex3_pp5_0c(196 to 263); + +--================================================================================== +--== EX4 (adder ... 64 bit) part of overflow detection +--================================================================================== + + u_sum_qi: ex4_pp5_0s(196 to 264) <= not ex4_pp5_0s_q_b(196 to 264) ; + u_car_qi: ex4_pp5_0c(196 to 263) <= not ex4_pp5_0c_q_b(196 to 263) ; + + ex4_pp5_0s_out(196 to 264) <= ex4_pp5_0s(196 to 264) ; --output-- + ex4_pp5_0c_out(196 to 263) <= ex4_pp5_0c(196 to 263) ; --output-- + + +--================================================================================== +--== Pervasive stuff +--================================================================================== + + + ex3_lcb: tri_lcbnd generic map (expand_type => expand_type) port map ( + delay_lclkr => delay_lclkr_dc ,--in -- tidn , + mpw1_b => mpw1_dc_b ,--in -- tidn , + mpw2_b => mpw2_dc_b ,--in -- tidn , + forcee => func_sl_force ,--in -- tidn , + nclk => nclk ,--in + vd => vdd ,--inout + gd => gnd ,--inout + act => ex2_act ,--in + sg => sg_0 ,--in + thold_b => func_sl_thold_0_b ,--in + d1clk => ex3_d1clk ,--out + d2clk => ex3_d2clk ,--out + lclk => ex3_lclk );--out + + ex4_lcb: tri_lcbnd generic map (expand_type => expand_type) port map ( + delay_lclkr => delay_lclkr_dc ,--in -- tidn , + mpw1_b => mpw1_dc_b ,--in -- tidn , + mpw2_b => mpw2_dc_b ,--in -- tidn , + forcee => func_sl_force ,--in -- tidn , + nclk => nclk ,--in + vd => vdd ,--inout + gd => gnd ,--inout + act => ex3_act ,--in + sg => sg_0 ,--in + thold_b => func_sl_thold_0_b ,--in + d1clk => ex4_d1clk ,--out + d2clk => ex4_d2clk ,--out + lclk => ex4_lclk );--out + +--================================================================================== +--== Latches +--================================================================================== + + + ex3_pp2_0s_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 45,btr => "NLI0001_X1_A12TH", expand_type => expand_type, needs_sreset => 0, init=>(1 to 45=>'0')) port map ( + VD => vdd ,--inout + GD => gnd ,--inout + LCLK => ex3_lclk ,--lclk.clk + D1CLK => ex3_d1clk , + D2CLK => ex3_d2clk , + SCANIN => ex3_pp2_0s_lat_si , + SCANOUT => ex3_pp2_0s_lat_so , + D => ex3_pp2_0s_din(198 to 242) , + QB => ex3_pp2_0s_q_b(198 to 242) ); + ex3_pp2_0c_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 43,btr => "NLI0001_X1_A12TH", expand_type => expand_type, needs_sreset => 0, init=>(1 to 43=>'0') ) port map ( + VD => vdd ,--inout + GD => gnd ,--inout + LCLK => ex3_lclk ,--lclk.clk + D1CLK => ex3_d1clk , + D2CLK => ex3_d2clk , + SCANIN => ex3_pp2_0c_lat_si , + SCANOUT => ex3_pp2_0c_lat_so , + D => ex3_pp2_0c_din(198 to 240) , + QB => ex3_pp2_0c_q_b(198 to 240) ); + + ex3_pp2_1s_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 47,btr => "NLI0001_X1_A12TH", expand_type => expand_type, needs_sreset => 0, init=>(1 to 47=>'0') ) port map ( + VD => vdd ,--inout + GD => gnd ,--inout + LCLK => ex3_lclk ,--lclk.clk + D1CLK => ex3_d1clk , + D2CLK => ex3_d2clk , + SCANIN => ex3_pp2_1s_lat_si , + SCANOUT => ex3_pp2_1s_lat_so , + D => ex3_pp2_1s_din(208 to 254) , + QB => ex3_pp2_1s_q_b(208 to 254) ); + + ex3_pp2_1c_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 45,btr => "NLI0001_X1_A12TH", expand_type => expand_type, needs_sreset => 0, init=>(1 to 45=>'0') ) port map ( + VD => vdd ,--inout + GD => gnd ,--inout + LCLK => ex3_lclk ,--lclk.clk + D1CLK => ex3_d1clk , + D2CLK => ex3_d2clk , + SCANIN => ex3_pp2_1c_lat_si , + SCANOUT => ex3_pp2_1c_lat_so , + D => ex3_pp2_1c_din(208 to 252) , + QB => ex3_pp2_1c_q_b(208 to 252) ); + + ex3_pp2_2s_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 45,btr => "NLI0001_X1_A12TH", expand_type => expand_type, needs_sreset => 0, init=>(1 to 45=>'0') ) port map ( + VD => vdd ,--inout + GD => gnd ,--inout + LCLK => ex3_lclk ,--lclk.clk + D1CLK => ex3_d1clk , + D2CLK => ex3_d2clk , + SCANIN => ex3_pp2_2s_lat_si , + SCANOUT => ex3_pp2_2s_lat_so , + D => ex3_pp2_2s_din(220 to 264) , + QB => ex3_pp2_2s_q_b(220 to 264) ); + + ex3_pp2_2c_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 44,btr => "NLI0001_X1_A12TH", expand_type => expand_type, needs_sreset => 0, init=>(1 to 44=>'0') ) port map ( + VD => vdd ,--inout + GD => gnd ,--inout + LCLK => ex3_lclk ,--lclk.clk + D1CLK => ex3_d1clk , + D2CLK => ex3_d2clk , + SCANIN => ex3_pp2_2c_lat_si , + SCANOUT => ex3_pp2_2c_lat_so , + D => ex3_pp2_2c_din(220 to 263) , + QB => ex3_pp2_2c_q_b(220 to 263) ); + + + ex4_pp5_0s_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 69,btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0, init=>(1 to 69=>'0') ) port map ( + VD => vdd ,--inout + GD => gnd ,--inout + LCLK => ex4_lclk ,--lclk.clk + D1CLK => ex4_d1clk , + D2CLK => ex4_d2clk , + SCANIN => ex4_pp5_0s_lat_si , + SCANOUT => ex4_pp5_0s_lat_so , + D => ex4_pp5_0s_din(196 to 264) , + QB => ex4_pp5_0s_q_b(196 to 264) ); + + ex4_pp5_0c_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 68,btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0, init=>(1 to 68=>'0') ) port map ( + VD => vdd ,--inout + GD => gnd ,--inout + LCLK => ex4_lclk ,--lclk.clk + D1CLK => ex4_d1clk , + D2CLK => ex4_d2clk , + SCANIN => ex4_pp5_0c_lat_si , + SCANOUT => ex4_pp5_0c_lat_so , + D => ex4_pp5_0c_din(196 to 263) , + QB => ex4_pp5_0c_q_b(196 to 263) ); + + + +--================================================================================== +--== scan string (serpentine) +--================================================================================== + + + + ex3_pp2_0s_lat_si(198 to 242) <= scan_in & ex3_pp2_0s_lat_so(198 to 241) ; + ex3_pp2_0c_lat_si(198 to 240) <= ex3_pp2_0c_lat_so(199 to 240) & ex3_pp2_0s_lat_so(242); + ex3_pp2_1s_lat_si(208 to 254) <= ex3_pp2_0c_lat_so(198) & ex3_pp2_1s_lat_so(208 to 253); + ex3_pp2_1c_lat_si(208 to 252) <= ex3_pp2_1c_lat_so(209 to 252) & ex3_pp2_1s_lat_so(254); + ex3_pp2_2s_lat_si(220 to 264) <= ex3_pp2_1c_lat_so(208) & ex3_pp2_2s_lat_so(220 to 263); + ex3_pp2_2c_lat_si(220 to 263) <= ex3_pp2_2c_lat_so(221 to 263) & ex3_pp2_2s_lat_so(264); + + ex4_pp5_0s_lat_si(196 to 264) <= ex3_pp2_2c_lat_so(220) & ex4_pp5_0s_lat_so(196 to 263); + ex4_pp5_0c_lat_si(196 to 263) <= ex4_pp5_0c_lat_so(197 to 263) & ex4_pp5_0s_lat_so(264); + + scan_out <= ex4_pp5_0c_lat_so(196) ; + + + mark_unused(ex2_pp1_1s(241)); + mark_unused(ex2_pp1_1c(238)); + mark_unused(ex2_pp1_1c(239)); + mark_unused(ex2_pp1_2s(247)); + mark_unused(ex2_pp1_2c(244)); + mark_unused(ex2_pp1_2c(245)); + mark_unused(ex2_pp1_3s(253)); + mark_unused(ex2_pp1_3c(250)); + mark_unused(ex2_pp1_3c(251)); + mark_unused(ex2_pp1_4s(259)); + mark_unused(ex2_pp1_4c(256)); + mark_unused(ex2_pp1_4c(257)); + mark_unused(ex2_pp1_5c(262)); + mark_unused(ex2_pp1_5c(263)); + mark_unused(ex3_pp2_0s(241)); + mark_unused(ex3_pp2_0c(236)); + mark_unused(ex3_pp2_0c(238)); + mark_unused(ex3_pp2_0c(239)); + mark_unused(ex3_pp2_1s(253)); + mark_unused(ex3_pp2_1c(248)); + mark_unused(ex3_pp2_1c(250)); + mark_unused(ex3_pp2_1c(251)); + mark_unused(ex3_pp2_2c(260)); + mark_unused(ex3_pp2_2c(262)); + mark_unused(ex3_pp2_1s_x(253)); + mark_unused(ex3_pp2_1c_x(248)); + mark_unused(ex3_pp2_1c_x(250)); + mark_unused(ex3_pp2_1c_x(251)); + mark_unused(ex3_pp2_2c_x(260)); + mark_unused(ex3_pp2_2c_x(262)); + mark_unused(ex3_pp2_1s_x_b(253)); + mark_unused(ex3_pp2_1c_x_b(248)); + mark_unused(ex3_pp2_1c_x_b(250)); + mark_unused(ex3_pp2_1c_x_b(251)); + mark_unused(ex3_pp2_2c_x_b(260)); + mark_unused(ex3_pp2_2c_x_b(262)); + mark_unused(ex3_pp3_0s(248)); + mark_unused(ex3_pp3_0s(250)); + mark_unused(ex3_pp3_0s(251)); + mark_unused(ex3_pp3_0c(240)); + mark_unused(ex3_pp3_0c(241)); + mark_unused(ex3_pp3_1c(254)); + mark_unused(ex3_pp3_1c(260)); + mark_unused(ex3_pp4_0c(252)); + mark_unused(ex3_pp4_0c(254)); + mark_unused(ex3_pp4_0c(260)); + mark_unused(ex2_pp1_0c(232)); + mark_unused(ex2_pp1_0c(233)); + mark_unused(ex2_pp0_00(233)); + mark_unused(ex2_pp0_01(235)); + mark_unused(ex2_pp0_02(237)); + mark_unused(ex2_pp0_03(239)); + mark_unused(ex2_pp0_04(241)); + mark_unused(ex2_pp0_05(243)); + mark_unused(ex2_pp0_06(245)); + mark_unused(ex2_pp0_07(247)); + mark_unused(ex2_pp0_08(249)); + mark_unused(ex2_pp0_09(251)); + mark_unused(ex2_pp0_10(253)); + mark_unused(ex2_pp0_11(255)); + mark_unused(ex2_pp0_12(257)); + mark_unused(ex2_pp0_13(259)); + mark_unused(ex2_pp0_14(261)); + mark_unused(ex2_pp0_15(263)); + mark_unused(ex2_pp1_0s(235)); + mark_unused(ex3_pp5_0c(195)); + mark_unused(version(0 to 7)); + + + +end architecture xuq_alu_mult_core; + + diff --git a/rel/src/vhdl/work/xuq_alu_mult_csa22.vhdl b/rel/src/vhdl/work/xuq_alu_mult_csa22.vhdl new file mode 100644 index 0000000..6a1cb2f --- /dev/null +++ b/rel/src/vhdl/work/xuq_alu_mult_csa22.vhdl @@ -0,0 +1,59 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +library ieee; use ieee.std_logic_1164.all ; +library ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + + +ENTITY xuq_alu_mult_csa22 IS + PORT( + a : IN std_ulogic; + b : IN std_ulogic; + car : OUT std_ulogic; + sum : OUT std_ulogic + ); +END xuq_alu_mult_csa22; + +ARCHITECTURE xuq_alu_mult_csa22 OF xuq_alu_mult_csa22 IS + + signal car_b, sum_b : std_ulogic; + + +BEGIN + + u_22nandc: car_b <= not( a and b ); + u_22nands: sum_b <= not( car_b and (a or b) ); -- this is equiv to an xnor + u_22invc: car <= not car_b; + u_22invs: sum <= not sum_b ; + +END; diff --git a/rel/src/vhdl/work/xuq_alu_or3232.vhdl b/rel/src/vhdl/work/xuq_alu_or3232.vhdl new file mode 100644 index 0000000..28dd66e --- /dev/null +++ b/rel/src/vhdl/work/xuq_alu_or3232.vhdl @@ -0,0 +1,137 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XU ALU or reduce component +-- +LIBRARY ieee; USE ieee.std_logic_1164.all; + use ieee.numeric_std.all; +LIBRARY ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; +LIBRARY support; + use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity xuq_alu_or3232 is generic(expand_type: integer := 2 ); port ( + + d :in std_ulogic_vector(0 to 63) ;--data + or_hi_b :out std_ulogic ;-- upper 32 ORed together + or_lo_b :out std_ulogic -- lower 32 ORed together +); + +-- synopsys translate_off +-- synopsys translate_on +end xuq_alu_or3232; + +architecture xuq_alu_or3232 of xuq_alu_or3232 is + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal or_lv1_b :std_ulogic_vector(0 to 31) ; + signal or_lv2 :std_ulogic_vector(0 to 15) ; + signal or_lv3_b :std_ulogic_vector(0 to 7) ; + signal or_lv4 :std_ulogic_vector(0 to 3) ; + signal or_lv5_b :std_ulogic_vector(0 to 1) ; + + +begin + + + + u_or_00: or_lv1_b( 0) <= not( d ( 0) or d ( 1) ); + u_or_02: or_lv1_b( 1) <= not( d ( 2) or d ( 3) ); + u_or_04: or_lv1_b( 2) <= not( d ( 4) or d ( 5) ); + u_or_06: or_lv1_b( 3) <= not( d ( 6) or d ( 7) ); + u_or_08: or_lv1_b( 4) <= not( d ( 8) or d ( 9) ); + u_or_10: or_lv1_b( 5) <= not( d (10) or d (11) ); + u_or_12: or_lv1_b( 6) <= not( d (12) or d (13) ); + u_or_14: or_lv1_b( 7) <= not( d (14) or d (15) ); + u_or_16: or_lv1_b( 8) <= not( d (16) or d (17) ); + u_or_18: or_lv1_b( 9) <= not( d (18) or d (19) ); + u_or_20: or_lv1_b(10) <= not( d (20) or d (21) ); + u_or_22: or_lv1_b(11) <= not( d (22) or d (23) ); + u_or_24: or_lv1_b(12) <= not( d (24) or d (25) ); + u_or_26: or_lv1_b(13) <= not( d (26) or d (27) ); + u_or_28: or_lv1_b(14) <= not( d (28) or d (29) ); + u_or_30: or_lv1_b(15) <= not( d (30) or d (31) ); + u_or_32: or_lv1_b(16) <= not( d (32) or d (33) ); + u_or_34: or_lv1_b(17) <= not( d (34) or d (35) ); + u_or_36: or_lv1_b(18) <= not( d (36) or d (37) ); + u_or_38: or_lv1_b(19) <= not( d (38) or d (39) ); + u_or_40: or_lv1_b(20) <= not( d (40) or d (41) ); + u_or_42: or_lv1_b(21) <= not( d (42) or d (43) ); + u_or_44: or_lv1_b(22) <= not( d (44) or d (45) ); + u_or_46: or_lv1_b(23) <= not( d (46) or d (47) ); + u_or_48: or_lv1_b(24) <= not( d (48) or d (49) ); + u_or_50: or_lv1_b(25) <= not( d (50) or d (51) ); + u_or_52: or_lv1_b(26) <= not( d (52) or d (53) ); + u_or_54: or_lv1_b(27) <= not( d (54) or d (55) ); + u_or_56: or_lv1_b(28) <= not( d (56) or d (57) ); + u_or_58: or_lv1_b(29) <= not( d (58) or d (59) ); + u_or_60: or_lv1_b(30) <= not( d (60) or d (61) ); + u_or_62: or_lv1_b(31) <= not( d (62) or d (63) ); + + u_or_01: or_lv2 ( 0) <= not( or_lv1_b( 0) and or_lv1_b( 1) ); + u_or_05: or_lv2 ( 1) <= not( or_lv1_b( 2) and or_lv1_b( 3) ); + u_or_09: or_lv2 ( 2) <= not( or_lv1_b( 4) and or_lv1_b( 5) ); + u_or_13: or_lv2 ( 3) <= not( or_lv1_b( 6) and or_lv1_b( 7) ); + u_or_17: or_lv2 ( 4) <= not( or_lv1_b( 8) and or_lv1_b( 9) ); + u_or_21: or_lv2 ( 5) <= not( or_lv1_b(10) and or_lv1_b(11) ); + u_or_25: or_lv2 ( 6) <= not( or_lv1_b(12) and or_lv1_b(13) ); + u_or_29: or_lv2 ( 7) <= not( or_lv1_b(14) and or_lv1_b(15) ); + u_or_33: or_lv2 ( 8) <= not( or_lv1_b(16) and or_lv1_b(17) ); + u_or_37: or_lv2 ( 9) <= not( or_lv1_b(18) and or_lv1_b(19) ); + u_or_41: or_lv2 (10) <= not( or_lv1_b(20) and or_lv1_b(21) ); + u_or_45: or_lv2 (11) <= not( or_lv1_b(22) and or_lv1_b(23) ); + u_or_49: or_lv2 (12) <= not( or_lv1_b(24) and or_lv1_b(25) ); + u_or_53: or_lv2 (13) <= not( or_lv1_b(26) and or_lv1_b(27) ); + u_or_57: or_lv2 (14) <= not( or_lv1_b(28) and or_lv1_b(29) ); + u_or_61: or_lv2 (15) <= not( or_lv1_b(30) and or_lv1_b(31) ); + + u_or_03: or_lv3_b( 0) <= not( or_lv2 ( 0) or or_lv2 ( 1) ); + u_or_11: or_lv3_b( 1) <= not( or_lv2 ( 2) or or_lv2 ( 3) ); + u_or_19: or_lv3_b( 2) <= not( or_lv2 ( 4) or or_lv2 ( 5) ); + u_or_27: or_lv3_b( 3) <= not( or_lv2 ( 6) or or_lv2 ( 7) ); + u_or_35: or_lv3_b( 4) <= not( or_lv2 ( 8) or or_lv2 ( 9) ); + u_or_43: or_lv3_b( 5) <= not( or_lv2 (10) or or_lv2 (11) ); + u_or_51: or_lv3_b( 6) <= not( or_lv2 (12) or or_lv2 (13) ); + u_or_59: or_lv3_b( 7) <= not( or_lv2 (14) or or_lv2 (15) ); + + u_or_07: or_lv4 ( 0) <= not( or_lv3_b( 0) and or_lv3_b( 1) ); + u_or_23: or_lv4 ( 1) <= not( or_lv3_b( 2) and or_lv3_b( 3) ); + u_or_39: or_lv4 ( 2) <= not( or_lv3_b( 4) and or_lv3_b( 5) ); + u_or_55: or_lv4 ( 3) <= not( or_lv3_b( 6) and or_lv3_b( 7) ); + + u_or_15: or_lv5_b( 0) <= not( or_lv4 ( 0) or or_lv4 ( 1) ); + u_or_47: or_lv5_b( 1) <= not( or_lv4 ( 2) or or_lv4 ( 3) ); + + or_hi_b <= or_lv5_b(0); -- rename --output-- + or_lo_b <= or_lv5_b(1); -- rename --output-- + +end architecture xuq_alu_or3232; diff --git a/rel/src/vhdl/work/xuq_alu_rol64.vhdl b/rel/src/vhdl/work/xuq_alu_rol64.vhdl new file mode 100644 index 0000000..9ae6491 --- /dev/null +++ b/rel/src/vhdl/work/xuq_alu_rol64.vhdl @@ -0,0 +1,254 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +LIBRARY ieee; USE ieee.std_logic_1164.all; + use ieee.numeric_std.all; +LIBRARY ibm; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; +LIBRARY support; + use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity xuq_alu_rol64 is generic(expand_type: integer := 2 ); port ( + word :in std_ulogic_vector(0 to 1); -- PPC word mode rotate <2 copies> + right :in std_ulogic_vector(0 to 2); -- emulate a shift right with a rotate left <2 copies> + amt :in std_ulogic_vector(0 to 5); -- shift amout [0:63] + data_i :in std_ulogic_vector(0 to 63); -- data to be shifted + res_rot :out std_ulogic_vector(0 to 63) -- mask shows which rotator bits to keep in the result. +); + +-- synopsys translate_off +-- synopsys translate_on + +end xuq_alu_rol64; + +architecture xuq_alu_rol64 of xuq_alu_rol64 is + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal right_b :std_ulogic_vector(0 to 2); + signal amt_b :std_ulogic_vector(0 to 5); + signal word_b :std_ulogic_vector(0 to 1); + signal word_bus, word_bus_b :std_ulogic_vector(0 to 31 ); + signal data_i0_adj_b :std_ulogic_vector(0 to 31 ); + signal data_i_adj, data_i1_adj_b :std_ulogic_vector(0 to 63); + + signal rolx16_0, rolx16_1, rolx16_2, rolx16_3 :std_ulogic_vector(0 to 63); + signal rolx04_0, rolx04_1, rolx04_2, rolx04_3 :std_ulogic_vector(0 to 63); + signal rolx01_0, rolx01_1, rolx01_2, rolx01_3, rolx01_4 :std_ulogic_vector(0 to 63); + signal shd16, shd16_0_b, shd16_1_b :std_ulogic_vector(0 to 63) ; + signal shd04, shd04_0_b, shd04_1_b :std_ulogic_vector(0 to 63) ; + signal shd01_0_b, shd01_1_b, shd01_2_b :std_ulogic_vector(0 to 63) ; + signal x16_lft_b, x16_rgt_b, lftx16 :std_ulogic_vector(0 to 3); + signal x04_lft_b, x04_rgt_b, lftx04 :std_ulogic_vector(0 to 3); + signal x01_lft_b, x01_rgt_b :std_ulogic_vector(0 to 3); + signal lftx01 :std_ulogic_vector(0 to 4); + + + signal lftx01_inv, lftx01_buf0, lftx01_buf1 :std_ulogic_vector(0 to 4); + signal lftx04_inv, lftx04_buf0, lftx04_buf1 :std_ulogic_vector(0 to 3); + signal lftx16_inv, lftx16_buf0, lftx16_buf1 :std_ulogic_vector(0 to 3); + signal lftx16_0_bus, lftx16_1_bus, lftx16_2_bus, lftx16_3_bus :std_ulogic_vector(0 to 63); + signal lftx04_0_bus, lftx04_1_bus, lftx04_2_bus, lftx04_3_bus :std_ulogic_vector(0 to 63); + signal lftx01_0_bus, lftx01_1_bus, lftx01_2_bus, lftx01_3_bus, lftx01_4_bus :std_ulogic_vector(0 to 63); + + + +begin + + -- ------------------------------------------------------------- + -- how the ppc emulates a rot32 using rot64 hardware. + -- this makes the wrapping corect for the low order 32 bits. + -- upper 32 result bits a garbage + ---------------------------------------------------------------- + + word_b(0 to 1) <= not word(0 to 1) ; + + word_bus_b( 0 to 15) <= (0 to 15 => word_b(0) ); + word_bus_b(16 to 31) <= (16 to 31 => word_b(1) ); + word_bus ( 0 to 15) <= (0 to 15 => word (0) ); + word_bus (16 to 31) <= (16 to 31 => word (1) ); + + + u_dhi0adj: data_i0_adj_b(0 to 31) <= not( data_i( 0 to 31) and word_bus_b(0 to 31) ); + u_dhi1adj: data_i1_adj_b(0 to 31) <= not( data_i(32 to 63) and word_bus (0 to 31) ); + u_dhiadj: data_i_adj (0 to 31) <= not( data_i0_adj_b(0 to 31) and data_i1_adj_b(0 to 31) ); + + u_dlo0adj: data_i1_adj_b(32 to 63) <= not( data_i(32 to 63) ); + u_dloadj: data_i_adj (32 to 63) <= not( data_i1_adj_b(32 to 63) ); + + ----------------------------------------------------------------- + -- decoder without the adder + ----------------------------------------------------------------- + --rotate right by [n] == rotate_left by width -[n] == !n + 1 + + right_b(0 to 2) <= not right(0 to 2) ; + u_amt_b: amt_b(0 to 5) <= not amt(0 to 5) ; + + u_x16lft_0: x16_lft_b(0) <= not( right_b(0) and amt_b(0) and amt_b(1) ); + u_x16lft_1: x16_lft_b(1) <= not( right_b(0) and amt_b(0) and amt (1) ); + u_x16lft_2: x16_lft_b(2) <= not( right_b(0) and amt (0) and amt_b(1) ); + u_x16lft_3: x16_lft_b(3) <= not( right_b(0) and amt (0) and amt (1) ); + + u_x16rgt_0: x16_rgt_b(0) <= not( right (0) and amt_b(0) and amt_b(1) ); + u_x16rgt_1: x16_rgt_b(1) <= not( right (0) and amt_b(0) and amt (1) ); + u_x16rgt_2: x16_rgt_b(2) <= not( right (0) and amt (0) and amt_b(1) ); + u_x16rgt_3: x16_rgt_b(3) <= not( right (0) and amt (0) and amt (1) ); + + u_lftx16_0: lftx16(0) <= not( x16_lft_b(0) and x16_rgt_b(3) ) ; + u_lftx16_1: lftx16(1) <= not( x16_lft_b(1) and x16_rgt_b(2) ) ; + u_lftx16_2: lftx16(2) <= not( x16_lft_b(2) and x16_rgt_b(1) ) ; + u_lftx16_3: lftx16(3) <= not( x16_lft_b(3) and x16_rgt_b(0) ) ; + + + + u_x04lft_0: x04_lft_b(0) <= not( right_b(1) and amt_b(2) and amt_b(3) ); + u_x04lft_1: x04_lft_b(1) <= not( right_b(1) and amt_b(2) and amt (3) ); + u_x04lft_2: x04_lft_b(2) <= not( right_b(1) and amt (2) and amt_b(3) ); + u_x04lft_3: x04_lft_b(3) <= not( right_b(1) and amt (2) and amt (3) ); + + u_x04rgt_0: x04_rgt_b(0) <= not( right (1) and amt_b(2) and amt_b(3) ); + u_x04rgt_1: x04_rgt_b(1) <= not( right (1) and amt_b(2) and amt (3) ); + u_x04rgt_2: x04_rgt_b(2) <= not( right (1) and amt (2) and amt_b(3) ); + u_x04rgt_3: x04_rgt_b(3) <= not( right (1) and amt (2) and amt (3) ); + + u_lftx04_0: lftx04(0) <= not( x04_lft_b(0) and x04_rgt_b(3) ) ; + u_lftx04_1: lftx04(1) <= not( x04_lft_b(1) and x04_rgt_b(2) ) ; + u_lftx04_2: lftx04(2) <= not( x04_lft_b(2) and x04_rgt_b(1) ) ; + u_lftx04_3: lftx04(3) <= not( x04_lft_b(3) and x04_rgt_b(0) ) ; + + + + u_x01lft_0: x01_lft_b(0) <= not( right_b(2) and amt_b(4) and amt_b(5) ); + u_x01lft_1: x01_lft_b(1) <= not( right_b(2) and amt_b(4) and amt (5) ); + u_x01lft_2: x01_lft_b(2) <= not( right_b(2) and amt (4) and amt_b(5) ); + u_x01lft_3: x01_lft_b(3) <= not( right_b(2) and amt (4) and amt (5) ); + + u_x01rgt_0: x01_rgt_b(0) <= not( right (2) and amt_b(4) and amt_b(5) ); + u_x01rgt_1: x01_rgt_b(1) <= not( right (2) and amt_b(4) and amt (5) ); + u_x01rgt_2: x01_rgt_b(2) <= not( right (2) and amt (4) and amt_b(5) ); + u_x01rgt_3: x01_rgt_b(3) <= not( right (2) and amt (4) and amt (5) ); + + u_lftx01_0: lftx01(0) <= not( x01_lft_b(0) ) ; -- the shift is like the +1 + u_lftx01_1: lftx01(1) <= not( x01_lft_b(1) and x01_rgt_b(3) ) ; + u_lftx01_2: lftx01(2) <= not( x01_lft_b(2) and x01_rgt_b(2) ) ; + u_lftx01_3: lftx01(3) <= not( x01_lft_b(3) and x01_rgt_b(1) ) ; + u_lftx01_4: lftx01(4) <= not( x01_rgt_b(0) ) ; + + u_lftx16_inv: lftx16_inv (0 to 3) <= not( lftx16 (0 to 3) ); + u_lftx16_buf0: lftx16_buf0(0 to 3) <= not( lftx16_inv(0 to 3) ); + u_lftx16_buf1: lftx16_buf1(0 to 3) <= not( lftx16_inv(0 to 3) ); + + u_lftx04_inv: lftx04_inv (0 to 3) <= not( lftx04 (0 to 3) ); + u_lftx04_buf0: lftx04_buf0(0 to 3) <= not( lftx04_inv(0 to 3) ); + u_lftx04_buf1: lftx04_buf1(0 to 3) <= not( lftx04_inv(0 to 3) ); + + u_lftx01_inv: lftx01_inv (0 to 4) <= not( lftx01 (0 to 4) ); + u_lftx01_buf0: lftx01_buf0(0 to 4) <= not( lftx01_inv(0 to 4) ); + u_lftx01_buf1: lftx01_buf1(0 to 4) <= not( lftx01_inv(0 to 4) ); + + + lftx16_0_bus( 0 to 31) <= ( 0 to 31 => lftx16_buf0(0) ); + lftx16_0_bus(32 to 63) <= (32 to 63 => lftx16_buf1(0) ); + lftx16_1_bus( 0 to 31) <= ( 0 to 31 => lftx16_buf0(1) ); + lftx16_1_bus(32 to 63) <= (32 to 63 => lftx16_buf1(1) ); + lftx16_2_bus( 0 to 31) <= ( 0 to 31 => lftx16_buf0(2) ); + lftx16_2_bus(32 to 63) <= (32 to 63 => lftx16_buf1(2) ); + lftx16_3_bus( 0 to 31) <= ( 0 to 31 => lftx16_buf0(3) ); + lftx16_3_bus(32 to 63) <= (32 to 63 => lftx16_buf1(3) ); + + lftx04_0_bus( 0 to 31) <= ( 0 to 31 => lftx04_buf0(0) ); + lftx04_0_bus(32 to 63) <= (32 to 63 => lftx04_buf1(0) ); + lftx04_1_bus( 0 to 31) <= ( 0 to 31 => lftx04_buf0(1) ); + lftx04_1_bus(32 to 63) <= (32 to 63 => lftx04_buf1(1) ); + lftx04_2_bus( 0 to 31) <= ( 0 to 31 => lftx04_buf0(2) ); + lftx04_2_bus(32 to 63) <= (32 to 63 => lftx04_buf1(2) ); + lftx04_3_bus( 0 to 31) <= ( 0 to 31 => lftx04_buf0(3) ); + lftx04_3_bus(32 to 63) <= (32 to 63 => lftx04_buf1(3) ); + + lftx01_0_bus( 0 to 31) <= ( 0 to 31 => lftx01_buf0(0) ); + lftx01_0_bus(32 to 63) <= (32 to 63 => lftx01_buf1(0) ); + lftx01_1_bus( 0 to 31) <= ( 0 to 31 => lftx01_buf0(1) ); + lftx01_1_bus(32 to 63) <= (32 to 63 => lftx01_buf1(1) ); + lftx01_2_bus( 0 to 31) <= ( 0 to 31 => lftx01_buf0(2) ); + lftx01_2_bus(32 to 63) <= (32 to 63 => lftx01_buf1(2) ); + lftx01_3_bus( 0 to 31) <= ( 0 to 31 => lftx01_buf0(3) ); + lftx01_3_bus(32 to 63) <= (32 to 63 => lftx01_buf1(3) ); + lftx01_4_bus( 0 to 31) <= ( 0 to 31 => lftx01_buf0(4) ); + lftx01_4_bus(32 to 63) <= (32 to 63 => lftx01_buf1(4) ); + + + + ----------------------------------------------------------------- + -- the shifter + ----------------------------------------------------------------- + + + rolx16_0(0 to 63) <= data_i_adj( 0 to 63) ; + rolx16_1(0 to 63) <= data_i_adj(16 to 63) & data_i_adj(0 to 15) ; + rolx16_2(0 to 63) <= data_i_adj(32 to 63) & data_i_adj(0 to 31) ; + rolx16_3(0 to 63) <= data_i_adj(48 to 63) & data_i_adj(0 to 47) ; + + + u_shd16_0: shd16_0_b(0 to 63) <= not( ( lftx16_0_bus(0 to 63) and rolx16_0(0 to 63) ) or + ( lftx16_1_bus(0 to 63) and rolx16_1(0 to 63) ) ); + u_shd16_1: shd16_1_b(0 to 63) <= not( ( lftx16_2_bus(0 to 63) and rolx16_2(0 to 63) ) or + ( lftx16_3_bus(0 to 63) and rolx16_3(0 to 63) ) ); + u_shd16: shd16 (0 to 63) <= not( shd16_0_b(0 to 63) and shd16_1_b(0 to 63) ); + + + rolx04_0(0 to 63) <= shd16( 0 to 63); + rolx04_1(0 to 63) <= shd16( 4 to 63) & shd16( 0 to 3); + rolx04_2(0 to 63) <= shd16( 8 to 63) & shd16( 0 to 7); + rolx04_3(0 to 63) <= shd16(12 to 63) & shd16( 0 to 11); + + u_shd04_0: shd04_0_b(0 to 63) <= not( ( lftx04_0_bus(0 to 63) and rolx04_0(0 to 63) ) or + ( lftx04_1_bus(0 to 63) and rolx04_1(0 to 63) ) ); + u_shd04_1: shd04_1_b(0 to 63) <= not( ( lftx04_2_bus(0 to 63) and rolx04_2(0 to 63) ) or + ( lftx04_3_bus(0 to 63) and rolx04_3(0 to 63) ) ); + u_shd04: shd04 (0 to 63) <= not( shd04_0_b(0 to 63) and shd04_1_b(0 to 63) ); + + rolx01_0(0 to 63) <= shd04(0 to 63); + rolx01_1(0 to 63) <= shd04(1 to 63) & shd04( 0 ); + rolx01_2(0 to 63) <= shd04(2 to 63) & shd04( 0 to 1); + rolx01_3(0 to 63) <= shd04(3 to 63) & shd04( 0 to 2); + rolx01_4(0 to 63) <= shd04(4 to 63) & shd04( 0 to 3); + + + + u_shd01_0: shd01_0_b(0 to 63) <= not( ( lftx01_0_bus(0 to 63) and rolx01_0(0 to 63) ) or + ( lftx01_1_bus(0 to 63) and rolx01_1(0 to 63) ) ); + u_shd01_1: shd01_1_b(0 to 63) <= not( ( lftx01_2_bus(0 to 63) and rolx01_2(0 to 63) ) or + ( lftx01_3_bus(0 to 63) and rolx01_3(0 to 63) ) ); + u_shd01_2: shd01_2_b(0 to 63) <= not( lftx01_4_bus(0 to 63) and rolx01_4(0 to 63) ); + u_shd01: res_rot (0 to 63) <= not( shd01_0_b(0 to 63) and shd01_1_b(0 to 63) and shd01_2_b(0 to 63) ); + +end architecture xuq_alu_rol64; diff --git a/rel/src/vhdl/work/xuq_byp.vhdl b/rel/src/vhdl/work/xuq_byp.vhdl new file mode 100644 index 0000000..f2b607f --- /dev/null +++ b/rel/src/vhdl/work/xuq_byp.vhdl @@ -0,0 +1,531 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XU Bypass Unit +-- +library ieee,ibm,support,tri; +use ieee.std_logic_1164.all; +use ibm.std_ulogic_function_support.all; +use tri.tri_latches_pkg.all; +use support.power_logic_pkg.all; +use work.xuq_pkg.all; + +entity xuq_byp is +generic ( + threads : integer := 4; + expand_type : integer := 2; + regsize : integer := 64; + eff_ifar : integer := 62); +port ( + -- Clocks + nclk : in clk_logic; + + -- Power + vdd : inout power_logic; + gnd : inout power_logic; + + -- Pervasive + d_mode_dc : in std_ulogic; + delay_lclkr_dc : in std_ulogic; + mpw1_dc_b : in std_ulogic; + mpw2_dc_b : in std_ulogic; + func_sl_force : in std_ulogic; + func_sl_thold_0_b : in std_ulogic; + func_nsl_force : in std_ulogic; + func_nsl_thold_0_b : in std_ulogic; + func_slp_sl_force : in std_ulogic; + func_slp_sl_thold_0_b : in std_ulogic; + sg_0 : in std_ulogic; + scan_in : in std_ulogic_vector(0 to 1); + scan_out : out std_ulogic_vector(0 to 1); + + pc_xu_trace_bus_enable : in std_ulogic; + dec_byp_ex3_instr_trace_val : in std_ulogic; + dec_byp_ex3_instr_trace_gate : in std_ulogic; + + -- Flushes + xu_ex3_flush : in std_ulogic_vector(0 to threads-1); + xu_ex4_flush : in std_ulogic_vector(0 to threads-1); + xu_ex5_flush : in std_ulogic_vector(0 to threads-1); + + dec_rf1_tid : in std_ulogic_vector(0 to threads-1); + dec_ex1_tid : in std_ulogic_vector(0 to threads-1); + dec_ex2_tid : in std_ulogic_vector(0 to threads-1); + dec_ex3_tid : in std_ulogic_vector(0 to threads-1); + dec_ex5_tid : in std_ulogic_vector(0 to threads-1); + + -- Decode Inputs + dec_alu_rf1_sel : in std_ulogic_vector(2 to 2); + dec_byp_rf1_rs0_sel : in std_ulogic_vector(1 to 9); + dec_byp_rf1_rs1_sel : in std_ulogic_vector(1 to 10); + dec_byp_rf1_rs2_sel : in std_ulogic_vector(1 to 9); + dec_byp_rf1_instr : in std_ulogic_vector(6 to 25); + dec_byp_rf1_cr_so_update : in std_ulogic_vector(0 to 1); + dec_byp_ex3_val : in std_ulogic_vector(0 to threads-1); + dec_byp_rf1_cr_we : in std_ulogic; + dec_byp_rf1_is_mcrf : in std_ulogic; + dec_byp_rf1_use_crfld0 : in std_ulogic; + dec_byp_rf1_alu_cmp : in std_ulogic; + dec_byp_rf1_is_mtcrf : in std_ulogic; + dec_byp_rf1_is_mtocrf : in std_ulogic; + dec_byp_rf1_is_isel : in std_ulogic; + dec_byp_rf1_byp_val : in std_ulogic_vector(1 to 3); + dec_byp_ex4_is_eratsxr : in std_ulogic; + dec_byp_rf1_ca_used : in std_ulogic; + dec_byp_rf1_ov_used : in std_ulogic; + dec_byp_ex4_dp_instr : in std_ulogic; + dec_byp_ex4_mtdp_val : in std_ulogic; + dec_byp_ex4_mfdp_val : in std_ulogic; + dec_byp_rf0_act : in std_ulogic; + fxa_fxb_rf0_is_mfocrf : in std_ulogic; + + dec_byp_ex1_spr_sel : in std_ulogic; + lsu_xu_ex5_wren : in std_ulogic; + dec_byp_ex4_is_mfcr : in std_ulogic; + spr_byp_ex4_is_mfxer : in std_ulogic_vector(0 to 3); + dec_byp_ex3_tlb_sel : in std_ulogic_vector(0 to 1); + alu_ex2_div_done : in std_ulogic; + + -- Slow SPR Bus + slowspr_val_in : in std_ulogic; + slowspr_rw_in : in std_ulogic; + slowspr_etid_in : in std_ulogic_vector(0 to 1); + slowspr_addr_in : in std_ulogic_vector(0 to 9); + slowspr_done_in : in std_ulogic; + + -- DCR Bus + dec_byp_ex4_dcr_ack : in std_ulogic; + an_ac_dcr_act : in std_ulogic; + an_ac_dcr_read : in std_ulogic; + an_ac_dcr_etid : in std_ulogic_vector(0 to 1); + an_ac_dcr_data : in std_ulogic_vector(64-regsize to 63); + an_ac_dcr_done : in std_ulogic; + + xu_iu_slowspr_done : out std_ulogic_vector(0 to 3); + mux_cpl_slowspr_done : out std_ulogic_vector(0 to 3); + mux_cpl_slowspr_flush : out std_ulogic_vector(0 to 3); + + -- Source Data + dec_byp_rf1_imm : in std_ulogic_vector(64-regsize to 63); + fxa_fxb_rf1_do0 : in std_ulogic_vector(64-regsize to 63); + fxa_fxb_rf1_do1 : in std_ulogic_vector(64-regsize to 63); + fxa_fxb_rf1_do2 : in std_ulogic_vector(64-regsize to 63); + + -- Result Busses + alu_byp_ex1_log_rt : in std_ulogic_vector(64-regsize to 63); -- ALU Logicals + alu_byp_ex2_rt : in std_ulogic_vector(64-regsize to 63); -- ALU + alu_byp_ex3_div_rt : in std_ulogic_vector(64-regsize to 63); -- Divide + cpl_byp_ex3_spr_rt : in std_ulogic_vector(64-regsize to 63); -- CPL SPR + spr_byp_ex3_spr_rt : in std_ulogic_vector(64-regsize to 63); -- SPR + fspr_byp_ex3_spr_rt : in std_ulogic_vector(64-regsize to 63); -- FXU SPR + lsu_xu_ex4_tlb_data : in std_ulogic_vector(64-regsize to 63); -- D-ERAT + iu_xu_ex4_tlb_data : in std_ulogic_vector(64-regsize to 63); -- I-ERAT + alu_byp_ex5_mul_rt : in std_ulogic_vector(64-regsize to 63); -- Multiply + lsu_xu_rot_ex6_data_b : in std_ulogic_vector(64-regsize to 63); -- Load/Store Hit + lsu_xu_rot_rel_data : in std_ulogic_vector(64-regsize to 63); -- Load/Store Miss + slowspr_data_in : in std_ulogic_vector(64-regsize to 63); -- Slow SPR + + -- Target Data + byp_dec_rf1_xer_ca : out std_ulogic; + byp_alu_ex1_rs0 : out std_ulogic_vector(64-regsize to 63); + byp_alu_ex1_rs1 : out std_ulogic_vector(64-regsize to 63); + byp_alu_ex1_mulsrc_0 : out std_ulogic_vector(64-regsize to 63); + byp_alu_ex1_mulsrc_1 : out std_ulogic_vector(64-regsize to 63); + byp_alu_ex1_divsrc_0 : out std_ulogic_vector(64-regsize to 63); + byp_alu_ex1_divsrc_1 : out std_ulogic_vector(64-regsize to 63); + xu_lsu_ex1_add_src0 : out std_ulogic_vector(64-regsize to 63); + xu_lsu_ex1_add_src1 : out std_ulogic_vector(64-regsize to 63); + + -- Other Outputs + xu_ex1_rs_is : out std_ulogic_vector(0 to 8); + xu_ex1_ra_entry : out std_ulogic_vector(7 to 11); + xu_ex1_rb : out std_ulogic_vector(64-regsize to 51); + xu_ex4_rs_data : out std_ulogic_vector(64-regsize to 63); -- TLB Write Data + xu_mm_derat_epn : out std_ulogic_vector(62-eff_ifar to 51); -- DERAT EPN + xu_pc_ram_data : out std_ulogic_vector(64-regsize to 63); -- RAM Result Capture + mux_spr_ex6_rt : out std_ulogic_vector(64-regsize to 63); -- SPR Write Data + byp_xer_si : out std_ulogic_vector(0 to 7*threads-1); + + -- FU CR Update + fu_xu_ex4_cr_val : in std_ulogic_vector(0 to threads-1); + fu_xu_ex4_cr_noflush : in std_ulogic_vector(0 to threads-1); + fu_xu_ex4_cr0 : in std_ulogic_vector(0 to 3); + fu_xu_ex4_cr0_bf : in std_ulogic_vector(0 to 2); + fu_xu_ex4_cr1 : in std_ulogic_vector(0 to 3); + fu_xu_ex4_cr1_bf : in std_ulogic_vector(0 to 2); + fu_xu_ex4_cr2 : in std_ulogic_vector(0 to 3); + fu_xu_ex4_cr2_bf : in std_ulogic_vector(0 to 2); + fu_xu_ex4_cr3 : in std_ulogic_vector(0 to 3); + fu_xu_ex4_cr3_bf : in std_ulogic_vector(0 to 2); + + -- MMU CR Update + mm_xu_cr0_eq_valid : in std_ulogic_vector(0 to threads-1); + mm_xu_cr0_eq : in std_ulogic_vector(0 to threads-1); + + -- L2 CR Update + an_ac_stcx_complete : in std_ulogic_vector(0 to threads-1); + an_ac_stcx_pass : in std_ulogic_vector(0 to threads-1); + + -- icswx CR Update + an_ac_back_inv : in std_ulogic; + an_ac_back_inv_addr : in std_ulogic_vector(58 to 63); + an_ac_back_inv_target_bit3 : in std_ulogic; + + -- MT/MFDCR + lsu_xu_ex4_mtdp_cr_status : in std_ulogic; + lsu_xu_ex4_mfdp_cr_status : in std_ulogic; + + -- ldawx/wchkall + dec_byp_ex4_is_wchkall : in std_ulogic; + lsu_xu_ex4_cr_upd : in std_ulogic; + lsu_xu_ex5_cr_rslt : in std_ulogic; + + -- CR/XER Signals + alu_byp_ex2_cr_recform : in std_ulogic_vector(0 to 3); + alu_byp_ex5_cr_mul : in std_ulogic_vector(0 to 4); + alu_byp_ex3_cr_div : in std_ulogic_vector(0 to 4); + alu_byp_ex2_xer : in std_ulogic_vector(0 to 3); + alu_byp_ex5_xer_mul : in std_ulogic_vector(0 to 3); + alu_byp_ex3_xer_div : in std_ulogic_vector(0 to 3); + alu_ex4_mul_done : in std_ulogic; + spr_byp_ex4_is_mtxer : in std_ulogic_vector(0 to threads-1); + byp_cpl_ex1_cr_bit : out std_ulogic; + + -- ALU isel controls + byp_alu_rf1_isel_fcn : out std_ulogic_vector(0 to 3); + + -- SPR Inputs + spr_msr_cm : in std_ulogic_vector(0 to threads-1); + dec_byp_ex5_instr : in std_ulogic_vector(12 to 19); + + byp_perf_tx_events : out std_ulogic_vector(0 to 3*threads-1); + + -- GPR Bypass + mux_cpl_ex4_rt : out std_ulogic_vector(64-regsize to 63); + byp_spr_ex6_rt : out std_ulogic_vector(64-regsize to 63); + xu_lsu_ex1_store_data : out std_ulogic_vector(64-regsize to 63); + fxu_spr_ex1_rs2 : out std_ulogic_vector(42 to 55); + fxu_spr_ex1_rs1 : out std_ulogic_vector(54 to 63); + fxu_spr_ex1_rs0 : out std_ulogic_vector(52 to 63); + fxb_fxa_ex7_wd0 : out std_ulogic_vector(64-regsize to 63); + + byp_grp0_debug : out std_ulogic_vector( 0 to 87); + byp_grp1_debug : out std_ulogic_vector( 0 to 87); + byp_grp2_debug : out std_ulogic_vector( 0 to 87); + byp_grp3_debug : out std_ulogic_vector(15 to 87); + byp_grp4_debug : out std_ulogic_vector(14 to 87); + byp_grp5_debug : out std_ulogic_vector(15 to 87); + byp_grp6_debug : out std_ulogic_vector(0 to 87); + byp_grp7_debug : out std_ulogic_vector(0 to 87); + byp_grp8_debug : out std_ulogic_vector(22 to 87) + ); + +-- synopsys translate_off +-- synopsys translate_on + +end xuq_byp; +architecture xuq_byp of xuq_byp is + +constant tidn : std_ulogic := '0'; + +signal siv, sov : std_ulogic_vector(0 to 1); +signal byp_ex5_cr_rt : std_ulogic_vector(32 to 63); +signal byp_ex5_xer_rt : std_ulogic_vector(54 to 63); +signal ex1_mfocrf_rt : std_ulogic_vector(64-regsize to 63); +signal byp_ex5_mtcrxer : std_ulogic_vector(32 to 63); +signal byp_ex5_tlb_rt : std_ulogic_vector(51 to 51); +signal byp_xer_so : std_ulogic_vector(0 to threads-1); +signal xer_cr_ex1_xer_ov_in_pipe : std_ulogic; +signal xer_cr_ex2_xer_ov_in_pipe : std_ulogic; +signal xer_cr_ex3_xer_ov_in_pipe : std_ulogic; +signal xer_cr_ex5_xer_ov_in_pipe : std_ulogic; +signal trace_bus_enable : std_ulogic; + +begin + +--------------------------------------------------------------------- +-- GPR +--------------------------------------------------------------------- +xu_byp_gpr : entity work.xuq_byp_gpr(xuq_byp_gpr) +generic map( + threads => threads, + expand_type => expand_type, + regsize => regsize, + eff_ifar => eff_ifar) +port map( + nclk => nclk, + vdd => vdd, + gnd => gnd, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc, + mpw1_dc_b => mpw1_dc_b, + mpw2_dc_b => mpw2_dc_b, + func_sl_force => func_sl_force, + func_sl_thold_0_b => func_sl_thold_0_b, + func_slp_sl_force => func_slp_sl_force, + func_slp_sl_thold_0_b => func_slp_sl_thold_0_b, + func_nsl_force => func_nsl_force, + func_nsl_thold_0_b => func_nsl_thold_0_b, + sg_0 => sg_0, + scan_in => scan_in(0), + scan_out => scan_out(0), + pc_xu_trace_bus_enable => pc_xu_trace_bus_enable, + dec_byp_ex3_instr_trace_val => dec_byp_ex3_instr_trace_val, + dec_byp_ex3_instr_trace_gate => dec_byp_ex3_instr_trace_gate, + trace_bus_enable => trace_bus_enable, + dec_rf1_tid => dec_rf1_tid, + dec_ex2_tid => dec_ex2_tid, + dec_byp_rf0_act => dec_byp_rf0_act, + dec_alu_rf1_sel => dec_alu_rf1_sel, + dec_byp_rf1_rs0_sel => dec_byp_rf1_rs0_sel, + dec_byp_rf1_rs1_sel => dec_byp_rf1_rs1_sel, + dec_byp_rf1_rs2_sel => dec_byp_rf1_rs2_sel, + fxa_fxb_rf0_is_mfocrf => fxa_fxb_rf0_is_mfocrf, + dec_byp_ex1_spr_sel => dec_byp_ex1_spr_sel, + alu_ex2_div_done => alu_ex2_div_done, + dec_byp_ex3_tlb_sel => dec_byp_ex3_tlb_sel, + alu_ex4_mul_done => alu_ex4_mul_done, + dec_byp_ex4_is_mfcr => dec_byp_ex4_is_mfcr, + spr_byp_ex4_is_mfxer => spr_byp_ex4_is_mfxer, + lsu_xu_ex5_wren => lsu_xu_ex5_wren, + slowspr_val_in => slowspr_val_in, + slowspr_rw_in => slowspr_rw_in, + slowspr_etid_in => slowspr_etid_in, + slowspr_addr_in => slowspr_addr_in, + slowspr_done_in => slowspr_done_in, + dec_byp_ex4_dcr_ack => dec_byp_ex4_dcr_ack, + an_ac_dcr_act => an_ac_dcr_act, + an_ac_dcr_read => an_ac_dcr_read, + an_ac_dcr_etid => an_ac_dcr_etid, + an_ac_dcr_data => an_ac_dcr_data, + an_ac_dcr_done => an_ac_dcr_done, + xu_iu_slowspr_done => xu_iu_slowspr_done, + mux_cpl_slowspr_done => mux_cpl_slowspr_done, + mux_cpl_slowspr_flush => mux_cpl_slowspr_flush, + dec_byp_rf1_imm => dec_byp_rf1_imm, + fxa_fxb_rf1_do0 => fxa_fxb_rf1_do0, + fxa_fxb_rf1_do1 => fxa_fxb_rf1_do1, + fxa_fxb_rf1_do2 => fxa_fxb_rf1_do2, + alu_byp_ex1_log_rt => alu_byp_ex1_log_rt, -- ALU Logicals + alu_byp_ex2_rt => alu_byp_ex2_rt, -- ALU + alu_byp_ex3_div_rt => alu_byp_ex3_div_rt, -- Divide + cpl_byp_ex3_spr_rt => cpl_byp_ex3_spr_rt, -- CPL SPR + spr_byp_ex3_spr_rt => spr_byp_ex3_spr_rt, -- SPR + fspr_byp_ex3_spr_rt => fspr_byp_ex3_spr_rt, -- FXU SPR + lsu_xu_ex4_tlb_data => lsu_xu_ex4_tlb_data, -- D-ERAT + iu_xu_ex4_tlb_data => iu_xu_ex4_tlb_data, -- I-ERAT + alu_byp_ex5_mul_rt => alu_byp_ex5_mul_rt, -- Multiply + lsu_xu_rot_ex6_data_b => lsu_xu_rot_ex6_data_b, -- Load/Store Hit + lsu_xu_rot_rel_data => lsu_xu_rot_rel_data, -- Load/Store Miss + slowspr_data_in => slowspr_data_in, -- Slow SPR + byp_ex5_cr_rt => byp_ex5_cr_rt, + byp_ex5_xer_rt => byp_ex5_xer_rt, + ex1_mfocrf_rt => ex1_mfocrf_rt, + byp_alu_ex1_rs0 => byp_alu_ex1_rs0, + byp_alu_ex1_rs1 => byp_alu_ex1_rs1, + byp_alu_ex1_mulsrc_0 => byp_alu_ex1_mulsrc_0, + byp_alu_ex1_mulsrc_1 => byp_alu_ex1_mulsrc_1, + byp_alu_ex1_divsrc_0 => byp_alu_ex1_divsrc_0, + byp_alu_ex1_divsrc_1 => byp_alu_ex1_divsrc_1, + xu_lsu_ex1_add_src0 => xu_lsu_ex1_add_src0, + xu_lsu_ex1_add_src1 => xu_lsu_ex1_add_src1, + xu_ex1_rs_is => xu_ex1_rs_is, + xu_ex1_ra_entry => xu_ex1_ra_entry, + xu_ex1_rb => xu_ex1_rb, + xu_ex4_rs_data => xu_ex4_rs_data, -- TLB Write Data + xu_mm_derat_epn => xu_mm_derat_epn, -- DERAT EPN + xu_pc_ram_data => xu_pc_ram_data, -- RAM Result Capture + mux_spr_ex6_rt => mux_spr_ex6_rt, -- SPR Write Data + spr_msr_cm => spr_msr_cm, + mux_cpl_ex4_rt => mux_cpl_ex4_rt, + byp_spr_ex6_rt => byp_spr_ex6_rt, + xu_lsu_ex1_store_data => xu_lsu_ex1_store_data, + fxu_spr_ex1_rs2 => fxu_spr_ex1_rs2, + fxu_spr_ex1_rs1 => fxu_spr_ex1_rs1, + fxu_spr_ex1_rs0 => fxu_spr_ex1_rs0, + fxb_fxa_ex7_wd0 => fxb_fxa_ex7_wd0, + byp_ex5_mtcrxer => byp_ex5_mtcrxer, + byp_ex5_tlb_rt => byp_ex5_tlb_rt, + byp_grp0_debug => byp_grp0_debug, + byp_grp1_debug => byp_grp1_debug, + byp_grp2_debug => byp_grp2_debug, + byp_grp3_debug => byp_grp3_debug, + byp_grp4_debug => byp_grp4_debug, + byp_grp5_debug => byp_grp5_debug + ); + + +--------------------------------------------------------------------- +-- CR +--------------------------------------------------------------------- +xu_byp_cr : entity work.xuq_byp_cr(xuq_byp_cr) +generic map( + threads => threads, + expand_type => expand_type, + regsize => regsize) +port map( + nclk => nclk, + vdd => vdd, + gnd => gnd, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc, + mpw1_dc_b => mpw1_dc_b, + mpw2_dc_b => mpw2_dc_b, + func_sl_force => func_sl_force, + func_sl_thold_0_b => func_sl_thold_0_b, + func_nsl_force => func_nsl_force, + func_nsl_thold_0_b => func_nsl_thold_0_b, + func_slp_sl_force => func_slp_sl_force, + func_slp_sl_thold_0_b => func_slp_sl_thold_0_b, + sg_0 => sg_0, + scan_in => siv(0), + scan_out => sov(0), + trace_bus_enable => trace_bus_enable, + dec_byp_ex3_val => dec_byp_ex3_val, + xu_ex3_flush => xu_ex3_flush, + xu_ex4_flush => xu_ex4_flush, + xu_ex5_flush => xu_ex5_flush, + rf1_tid => dec_rf1_tid, + ex1_tid => dec_ex1_tid, + ex2_tid => dec_ex2_tid, + ex3_tid => dec_ex3_tid, + ex5_tid => dec_ex5_tid, + rf1_instr => dec_byp_rf1_instr, + dec_byp_rf1_cr_so_update => dec_byp_rf1_cr_so_update, + dec_byp_rf1_cr_we => dec_byp_rf1_cr_we, + dec_byp_rf1_is_mcrf => dec_byp_rf1_is_mcrf, + dec_byp_rf1_use_crfld0 => dec_byp_rf1_use_crfld0, + dec_byp_rf1_alu_cmp => dec_byp_rf1_alu_cmp, + dec_byp_rf1_is_mtcrf => dec_byp_rf1_is_mtcrf, + dec_byp_rf1_is_mtocrf => dec_byp_rf1_is_mtocrf, + fxa_fxb_rf0_is_mfocrf => fxa_fxb_rf0_is_mfocrf, + dec_byp_rf1_is_isel => dec_byp_rf1_is_isel, + dec_byp_rf1_byp_val => dec_byp_rf1_byp_val, + dec_byp_rf0_act => dec_byp_rf0_act, + dec_byp_ex4_is_eratsxr => dec_byp_ex4_is_eratsxr, + dec_byp_ex4_dp_instr => dec_byp_ex4_dp_instr, + dec_byp_ex4_mtdp_val => dec_byp_ex4_mtdp_val, + dec_byp_ex4_mfdp_val => dec_byp_ex4_mfdp_val, + lsu_xu_ex4_mtdp_cr_status => lsu_xu_ex4_mtdp_cr_status, + lsu_xu_ex4_mfdp_cr_status => lsu_xu_ex4_mfdp_cr_status, + dec_byp_ex4_is_wchkall => dec_byp_ex4_is_wchkall, + lsu_xu_ex4_cr_upd => lsu_xu_ex4_cr_upd, + lsu_xu_ex5_cr_rslt => lsu_xu_ex5_cr_rslt, + byp_cpl_ex1_cr_bit => byp_cpl_ex1_cr_bit, + byp_alu_rf1_isel_fcn => byp_alu_rf1_isel_fcn, + alu_byp_ex2_cr_recform => alu_byp_ex2_cr_recform, + alu_byp_ex5_cr_mul => alu_byp_ex5_cr_mul, + alu_byp_ex3_cr_div => alu_byp_ex3_cr_div, + alu_ex2_div_done => alu_ex2_div_done, + fu_xu_ex4_cr_val => fu_xu_ex4_cr_val, + fu_xu_ex4_cr_noflush => fu_xu_ex4_cr_noflush, + fu_xu_ex4_cr0 => fu_xu_ex4_cr0, + fu_xu_ex4_cr0_bf => fu_xu_ex4_cr0_bf, + fu_xu_ex4_cr1 => fu_xu_ex4_cr1, + fu_xu_ex4_cr1_bf => fu_xu_ex4_cr1_bf, + fu_xu_ex4_cr2 => fu_xu_ex4_cr2, + fu_xu_ex4_cr2_bf => fu_xu_ex4_cr2_bf, + fu_xu_ex4_cr3 => fu_xu_ex4_cr3, + fu_xu_ex4_cr3_bf => fu_xu_ex4_cr3_bf, + mm_xu_cr0_eq_valid => mm_xu_cr0_eq_valid, + mm_xu_cr0_eq => mm_xu_cr0_eq, + an_ac_stcx_complete => an_ac_stcx_complete, + an_ac_stcx_pass => an_ac_stcx_pass, + an_ac_back_inv => an_ac_back_inv, + an_ac_back_inv_addr => an_ac_back_inv_addr, + an_ac_back_inv_target_bit3 => an_ac_back_inv_target_bit3, + byp_ex5_mtcrxer => byp_ex5_mtcrxer, + byp_ex5_tlb_rt => byp_ex5_tlb_rt, + ex5_cr_rt => byp_ex5_cr_rt, + ex1_mfocrf_rt => ex1_mfocrf_rt, + dec_cr_ex5_instr => dec_byp_ex5_instr, + byp_perf_tx_events => byp_perf_tx_events, + byp_xer_so => byp_xer_so, + xer_cr_ex1_xer_ov_in_pipe => xer_cr_ex1_xer_ov_in_pipe, + xer_cr_ex2_xer_ov_in_pipe => xer_cr_ex2_xer_ov_in_pipe, + xer_cr_ex3_xer_ov_in_pipe => xer_cr_ex3_xer_ov_in_pipe, + xer_cr_ex5_xer_ov_in_pipe => xer_cr_ex5_xer_ov_in_pipe, + cr_grp0_debug => byp_grp6_debug, + cr_grp1_debug => byp_grp7_debug + ); + +--------------------------------------------------------------------- +-- XER +--------------------------------------------------------------------- +xu_byp_xer : entity work.xuq_byp_xer(xuq_byp_xer) +generic map( + threads => threads, + expand_type => expand_type, + regsize => regsize) +port map( + nclk => nclk, + vdd => vdd, + gnd => gnd, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc, + mpw1_dc_b => mpw1_dc_b, + mpw2_dc_b => mpw2_dc_b, + func_sl_force => func_sl_force, + func_sl_thold_0_b => func_sl_thold_0_b, + func_slp_sl_force => func_slp_sl_force, + func_slp_sl_thold_0_b => func_slp_sl_thold_0_b, + sg_0 => sg_0, + scan_in => siv(1), + scan_out => sov(1), + trace_bus_enable => trace_bus_enable, + dec_byp_rf1_ca_used => dec_byp_rf1_ca_used, + dec_byp_rf1_ov_used => dec_byp_rf1_ov_used, + rf1_tid => dec_rf1_tid, + ex5_tid => dec_ex5_tid, + dec_byp_ex3_val => dec_byp_ex3_val, + dec_byp_rf1_byp_val => dec_byp_rf1_byp_val(2 to 3), + xu_ex3_flush => xu_ex3_flush, + xu_ex4_flush => xu_ex4_flush, + xu_ex5_flush => xu_ex5_flush, + byp_ex5_xer_rt => byp_ex5_xer_rt, + alu_ex4_mul_done => alu_ex4_mul_done, + alu_ex2_div_done => alu_ex2_div_done, + alu_byp_ex2_xer => alu_byp_ex2_xer, + alu_byp_ex5_xer_mul => alu_byp_ex5_xer_mul, + alu_byp_ex3_xer_div => alu_byp_ex3_xer_div, + spr_byp_ex4_is_mtxer => spr_byp_ex4_is_mtxer, + byp_ex5_mtcrxer => byp_ex5_mtcrxer, + byp_xer_si => byp_xer_si, + byp_xer_so => byp_xer_so, + xer_cr_ex1_xer_ov_in_pipe => xer_cr_ex1_xer_ov_in_pipe, + xer_cr_ex2_xer_ov_in_pipe => xer_cr_ex2_xer_ov_in_pipe, + xer_cr_ex3_xer_ov_in_pipe => xer_cr_ex3_xer_ov_in_pipe, + xer_cr_ex5_xer_ov_in_pipe => xer_cr_ex5_xer_ov_in_pipe, + byp_dec_rf1_xer_ca => byp_dec_rf1_xer_ca, + xer_debug => byp_grp8_debug); + + +siv(0 to siv'right) <= sov(1 to siv'right) & scan_in(1); +scan_out(1) <= sov(0); + +end architecture xuq_byp; diff --git a/rel/src/vhdl/work/xuq_byp_cr.vhdl b/rel/src/vhdl/work/xuq_byp_cr.vhdl new file mode 100644 index 0000000..921fc04 --- /dev/null +++ b/rel/src/vhdl/work/xuq_byp_cr.vhdl @@ -0,0 +1,1705 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XU Bypass Unit +-- +library ieee,ibm,support,tri,work; +use ieee.std_logic_1164.all; +use ibm.std_ulogic_function_support.all; +use tri.tri_latches_pkg.all; +use support.power_logic_pkg.all; +use work.xuq_pkg.all; + +entity xuq_byp_cr is + generic ( + threads : integer := 4; + expand_type : integer := 2; + regsize : integer := 64); + port ( + -- Clocks + nclk : in clk_logic; + + -- Power + vdd : inout power_logic; + gnd : inout power_logic; + + -- Pervasive + d_mode_dc : in std_ulogic; + delay_lclkr_dc : in std_ulogic; + mpw1_dc_b : in std_ulogic; + mpw2_dc_b : in std_ulogic; + func_sl_force : in std_ulogic; + func_sl_thold_0_b : in std_ulogic; + func_nsl_force : in std_ulogic; + func_nsl_thold_0_b : in std_ulogic; + func_slp_sl_force : in std_ulogic; + func_slp_sl_thold_0_b : in std_ulogic; + sg_0 : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + trace_bus_enable : in std_ulogic; + + -- Valid + dec_byp_ex3_val : in std_ulogic_vector(0 to threads-1); + + -- Flushes + xu_ex3_flush : in std_ulogic_vector(0 to threads-1); + xu_ex4_flush : in std_ulogic_vector(0 to threads-1); + xu_ex5_flush : in std_ulogic_vector(0 to threads-1); + + -- Bypass Inputs + rf1_tid : in std_ulogic_vector(0 to threads-1); + ex1_tid : in std_ulogic_vector(0 to threads-1); + ex2_tid : in std_ulogic_vector(0 to threads-1); + ex3_tid : in std_ulogic_vector(0 to threads-1); + ex5_tid : in std_ulogic_vector(0 to threads-1); + rf1_instr : in std_ulogic_vector(6 to 25); + + -- Decode Inputs + fxa_fxb_rf0_is_mfocrf : in std_ulogic; + dec_byp_rf1_cr_so_update : in std_ulogic_vector(0 to 1); + dec_byp_rf1_cr_we : in std_ulogic; + dec_byp_rf1_is_mcrf : in std_ulogic; + dec_byp_rf1_use_crfld0 : in std_ulogic; + dec_byp_rf1_alu_cmp : in std_ulogic; + dec_byp_rf1_is_mtcrf : in std_ulogic; + dec_byp_rf1_is_mtocrf : in std_ulogic; + dec_byp_rf1_is_isel : in std_ulogic; + dec_byp_rf1_byp_val : in std_ulogic_vector(1 to 3); + dec_byp_rf0_act : in std_ulogic; + dec_byp_ex4_is_eratsxr : in std_ulogic; + + -- MT/MF DP + dec_byp_ex4_dp_instr : in std_ulogic; + dec_byp_ex4_mtdp_val : in std_ulogic; + dec_byp_ex4_mfdp_val : in std_ulogic; + lsu_xu_ex4_mtdp_cr_status : in std_ulogic; + lsu_xu_ex4_mfdp_cr_status : in std_ulogic; + + -- ldawx/wchkall + dec_byp_ex4_is_wchkall : in std_ulogic; + lsu_xu_ex4_cr_upd : in std_ulogic; + lsu_xu_ex5_cr_rslt : in std_ulogic; + + -- CR Outputs + byp_cpl_ex1_cr_bit : out std_ulogic; + byp_alu_rf1_isel_fcn : out std_ulogic_vector(0 to 3); + + -- ALU CR Inputs + alu_byp_ex2_cr_recform : in std_ulogic_vector(0 to 3); + alu_byp_ex5_cr_mul : in std_ulogic_vector(0 to 4); + alu_byp_ex3_cr_div : in std_ulogic_vector(0 to 4); + alu_ex2_div_done : in std_ulogic; + + -- AXU CR Inputs + fu_xu_ex4_cr_val : in std_ulogic_vector(0 to threads-1); + fu_xu_ex4_cr_noflush : in std_ulogic_vector(0 to threads-1); + fu_xu_ex4_cr0 : in std_ulogic_vector(0 to 3); + fu_xu_ex4_cr0_bf : in std_ulogic_vector(0 to 2); + fu_xu_ex4_cr1 : in std_ulogic_vector(0 to 3); + fu_xu_ex4_cr1_bf : in std_ulogic_vector(0 to 2); + fu_xu_ex4_cr2 : in std_ulogic_vector(0 to 3); + fu_xu_ex4_cr2_bf : in std_ulogic_vector(0 to 2); + fu_xu_ex4_cr3 : in std_ulogic_vector(0 to 3); + fu_xu_ex4_cr3_bf : in std_ulogic_vector(0 to 2); + + -- MMU CR inputs + mm_xu_cr0_eq_valid : in std_ulogic_vector(0 to threads-1); + mm_xu_cr0_eq : in std_ulogic_vector(0 to threads-1); + + -- L2 STCX complete + an_ac_stcx_complete : in std_ulogic_vector(0 to threads-1); + an_ac_stcx_pass : in std_ulogic_vector(0 to threads-1); + + -- icswx. interface + an_ac_back_inv : in std_ulogic; + an_ac_back_inv_addr : in std_ulogic_vector(58 to 63); + an_ac_back_inv_target_bit3 : in std_ulogic; + + -- mtcrf + byp_ex5_mtcrxer : in std_ulogic_vector(32 to 63); + byp_ex5_tlb_rt : in std_ulogic_vector(51 to 51); + -- mfcr + ex5_cr_rt : out std_ulogic_vector(32 to 63); + -- mfocrf + ex1_mfocrf_rt : out std_ulogic_vector(64-regsize to 63); + + -- Instr + dec_cr_ex5_instr : in std_ulogic_vector(12 to 19); + + byp_perf_tx_events : out std_ulogic_vector(0 to 3*threads-1); + + -- SPR Bits + byp_xer_so : in std_ulogic_vector(0 to threads-1); + xer_cr_ex1_xer_ov_in_pipe : in std_ulogic; + xer_cr_ex2_xer_ov_in_pipe : in std_ulogic; + xer_cr_ex3_xer_ov_in_pipe : in std_ulogic; + xer_cr_ex5_xer_ov_in_pipe : in std_ulogic; + + cr_grp0_debug : out std_ulogic_vector(0 to 87); + cr_grp1_debug : out std_ulogic_vector(0 to 87) + ); + +-- synopsys translate_off + +-- synopsys translate_on +end xuq_byp_cr; +architecture xuq_byp_cr of xuq_byp_cr is + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + type CR_ARY is array (0 to threads-1) of std_ulogic_vector(0 to 7); + subtype s2 is std_ulogic_vector(0 to 1); + subtype s5 is std_ulogic_vector(0 to 4); + + -- Latches + signal rf1_is_mfocrf_q : std_ulogic; -- input=>fxa_fxb_rf0_is_mfocrf , act=>tiup , scan=>N, needs_sreset=>1 + signal ex1_alu_cmp_q : std_ulogic; -- input=>dec_byp_rf1_alu_cmp , act=>exx_act(0) , scan=>Y, needs_sreset=>0 + signal ex1_any_mtcrf_q, ex1_any_mtcrf_d : std_ulogic; -- input=>ex1_any_mtcrf_d , act=>exx_act(0) , scan=>Y, needs_sreset=>0 + signal ex1_cr0_q : std_ulogic_vector(0 to 3); -- input=>rf1_cr0 , act=>exx_act(0) , scan=>Y, needs_sreset=>0 + signal ex1_cr0_bit_q, rf1_cr0_bit : std_ulogic; -- input=>rf1_cr0_bit , act=>exx_act(0) , scan=>Y, needs_sreset=>0 + signal ex1_cr1_q : std_ulogic_vector(0 to 3); -- input=>rf1_cr1 , act=>exx_act(0) , scan=>Y, needs_sreset=>0 + signal ex1_cr1_bit_q, rf1_cr1_bit_i : std_ulogic; -- input=>rf1_cr1_bit_i , act=>exx_act(0) , scan=>Y, needs_sreset=>0 + signal ex1_cr_so_update_q : std_ulogic_vector(0 to 1); -- input=>dec_byp_rf1_cr_so_update , act=>exx_act(0) , scan=>Y, needs_sreset=>0 + signal ex1_cr_we_q : std_ulogic; -- input=>dec_byp_rf1_cr_we , act=>tiup , scan=>Y, needs_sreset=>1 + signal ex1_crt_q, rf1_crt : std_ulogic_vector(0 to 3); -- input=>rf1_crt , act=>exx_act(0) , scan=>Y, needs_sreset=>0 + signal ex1_crt_mask_q, rf1_crt_mask : std_ulogic_vector(0 to 3); -- input=>rf1_crt_mask , act=>exx_act(0) , scan=>Y, needs_sreset=>0 + signal ex1_instr_q : std_ulogic_vector(6 to 19); -- input=>rf1_instr , act=>exx_act(0) , scan=>Y, needs_sreset=>0 + signal ex1_instr_2_q : std_ulogic_vector(22 to 25); -- input=>rf1_instr , act=>exx_act(0) , scan=>Y, needs_sreset=>0 + signal ex1_is_mcrf_q : std_ulogic; -- input=>dec_byp_rf1_is_mcrf , act=>exx_act(0) , scan=>Y, needs_sreset=>0 + signal ex1_use_crfld0_q : std_ulogic; -- input=>dec_byp_rf1_use_crfld0 , act=>exx_act(0) , scan=>Y, needs_sreset=>0 + signal ex2_alu_cmp_q : std_ulogic; -- input=>ex1_alu_cmp_q , act=>exx_act(1) , scan=>N, needs_sreset=>0 + signal ex2_any_mtcrf_q : std_ulogic; -- input=>ex1_any_mtcrf_q , act=>exx_act(1) , scan=>N, needs_sreset=>0 + signal ex2_cr_q : std_ulogic_vector(0 to 7); -- input=>ex1_cr , act=>exx_act(1) , scan=>N, needs_sreset=>0 + signal ex2_cr_we_q : std_ulogic; -- input=>ex1_cr_we_q , act=>tiup , scan=>N, needs_sreset=>1 + signal ex2_instr_q : std_ulogic_vector(6 to 8); -- input=>ex1_instr_q , act=>exx_act(1) , scan=>N, needs_sreset=>0 + signal ex2_use_crfld0_q : std_ulogic; -- input=>ex1_use_crfld0_q , act=>exx_act(1) , scan=>N, needs_sreset=>0 + signal ex3_any_mtcrf_q : std_ulogic; -- input=>ex2_any_mtcrf_q , act=>exx_act(2) , scan=>Y, needs_sreset=>0 + signal ex3_cr_q : std_ulogic_vector(0 to 7); -- input=>ex2_cr , act=>exx_act(2) , scan=>Y, needs_sreset=>0 + signal ex3_div_done_q : std_ulogic; -- input=>alu_ex2_div_done , act=>exx_act(2) , scan=>Y, needs_sreset=>0 + signal ex3_instr_q : std_ulogic_vector(6 to 8); -- input=>ex2_instr_q , act=>exx_act(2) , scan=>Y, needs_sreset=>0 + signal ex4_any_mtcrf_q : std_ulogic; -- input=>ex3_any_mtcrf_q , act=>exx_act(3) , scan=>N, needs_sreset=>0 + signal ex4_cr_q : std_ulogic_vector(0 to 7); -- input=>ex3_cr , act=>exx_act(3) , scan=>N, needs_sreset=>0 + signal ex4_instr_q : std_ulogic_vector(6 to 8); -- input=>ex3_instr_q , act=>exx_act(3) , scan=>N, needs_sreset=>0 + signal ex4_val_q, ex3_val : std_ulogic_vector(0 to threads-1); -- input=>ex3_val , act=>tiup , scan=>N, needs_sreset=>1 + signal ex5_any_mtcrf_q : std_ulogic; -- input=>ex4_any_mtcrf_q , act=>exx_act(4) , scan=>Y, needs_sreset=>0 + signal ex5_axu_val_q, ex4_axu_val : std_ulogic_vector(0 to threads-1); -- input=>ex4_axu_val , act=>tiup , scan=>Y, needs_sreset=>1 + signal ex5_cr_q : std_ulogic_vector(0 to 7); -- input=>ex4_cr , act=>exx_act(4) , scan=>Y, needs_sreset=>0 + signal ex5_dp_instr_q : std_ulogic; -- input=>dec_byp_ex4_dp_instr , act=>exx_act(4) , scan=>Y, needs_sreset=>0 + signal ex5_fu_cr0_q : std_ulogic_vector(0 to 3); -- input=>fu_xu_ex4_cr0 , act=>ex4_axu_act , scan=>Y, needs_sreset=>0 + signal ex5_fu_cr0_bf_q : std_ulogic_vector(0 to 2); -- input=>fu_xu_ex4_cr0_bf , act=>ex4_axu_act , scan=>Y, needs_sreset=>0 + signal ex5_fu_cr1_q : std_ulogic_vector(0 to 3); -- input=>fu_xu_ex4_cr1 , act=>ex4_axu_act , scan=>Y, needs_sreset=>0 + signal ex5_fu_cr1_bf_q : std_ulogic_vector(0 to 2); -- input=>fu_xu_ex4_cr1_bf , act=>ex4_axu_act , scan=>Y, needs_sreset=>0 + signal ex5_fu_cr2_q : std_ulogic_vector(0 to 3); -- input=>fu_xu_ex4_cr2 , act=>ex4_axu_act , scan=>Y, needs_sreset=>0 + signal ex5_fu_cr2_bf_q : std_ulogic_vector(0 to 2); -- input=>fu_xu_ex4_cr2_bf , act=>ex4_axu_act , scan=>Y, needs_sreset=>0 + signal ex5_fu_cr3_q : std_ulogic_vector(0 to 3); -- input=>fu_xu_ex4_cr3 , act=>ex4_axu_act , scan=>Y, needs_sreset=>0 + signal ex5_fu_cr3_bf_q : std_ulogic_vector(0 to 2); -- input=>fu_xu_ex4_cr3_bf , act=>ex4_axu_act , scan=>Y, needs_sreset=>0 + signal ex5_fu_cr_noflush_q : std_ulogic_vector(0 to threads-1); -- input=>fu_xu_ex4_cr_noflush , act=>tiup , scan=>Y, needs_sreset=>0 + signal ex5_fu_cr_val_q : std_ulogic_vector(0 to threads-1); -- input=>fu_xu_ex4_cr_val , act=>tiup , scan=>Y, needs_sreset=>1 + signal ex5_is_eratsxr_q : std_ulogic; -- input=>dec_byp_ex4_is_eratsxr , act=>exx_act(4) , scan=>Y, needs_sreset=>0 + signal ex5_mfdp_cr_status_q : std_ulogic; -- input=>lsu_xu_ex4_mfdp_cr_status , act=>exx_act(4) , scan=>Y, needs_sreset=>0 + signal ex5_mfdp_val_q : std_ulogic; -- input=>dec_byp_ex4_mfdp_val , act=>exx_act(4) , scan=>Y, needs_sreset=>0 + signal ex5_mtdp_cr_status_q : std_ulogic; -- input=>lsu_xu_ex4_mtdp_cr_status , act=>exx_act(4) , scan=>Y, needs_sreset=>0 + signal ex5_mtdp_val_q : std_ulogic; -- input=>dec_byp_ex4_mtdp_val , act=>tiup , scan=>Y, needs_sreset=>1 + signal ex5_val_q, ex4_val : std_ulogic_vector(0 to threads-1); -- input=>ex4_val , act=>tiup , scan=>Y, needs_sreset=>1 + signal ex5_watch_we_q, ex5_watch_we_d : std_ulogic; -- input=>ex5_watch_we_d , act=>tiup , scan=>Y, needs_sreset=>1 + signal ex5_wchkall_fld_q, ex5_wchkall_fld_d : std_ulogic_vector(0 to 2); -- input=>ex5_wchkall_fld_d , act=>exx_act(4) , scan=>Y, needs_sreset=>0 + signal an_ac_back_inv_q : std_ulogic; -- input=>an_ac_back_inv , act=>tiup , scan=>Y, needs_sreset=>1 + signal an_ac_back_inv_addr_q : std_ulogic_vector(58 to 63); -- input=>an_ac_back_inv_addr , act=>tiup , scan=>Y, needs_sreset=>1 + signal an_ac_back_inv_target_bit3_q : std_ulogic; -- input=>an_ac_back_inv_target_bit3 , act=>tiup , scan=>Y, needs_sreset=>1 + signal back_inv_val_q, back_inv_val_d : std_ulogic; -- input=>back_inv_val_d , act=>tiup , scan=>Y, needs_sreset=>1 + signal cr_barrier_we_q, cr_barrier_we_d : std_ulogic_vector(0 to threads-1); -- input=>cr_barrier_we_d , act=>tiup , scan=>Y, needs_sreset=>1 + signal exx_act_q, exx_act_d : std_ulogic_vector(0 to 4); -- input=>exx_act_d , act=>tiup , scan=>Y, needs_sreset=>1 + signal mmu_cr0_eq_q : std_ulogic_vector(0 to threads-1); -- input=>mm_xu_cr0_eq , act=>tiup , scan=>Y, needs_sreset=>1 + signal mmu_cr0_eq_valid_q : std_ulogic_vector(0 to threads-1); -- input=>mm_xu_cr0_eq_valid , act=>tiup , scan=>Y, needs_sreset=>1 + signal stcx_complete_q : std_ulogic_vector(0 to threads-1); -- input=>an_ac_stcx_complete , act=>tiup , scan=>Y, needs_sreset=>1 + signal stcx_pass_q : std_ulogic_vector(0 to threads-1); -- input=>an_ac_stcx_pass , act=>tiup , scan=>Y, needs_sreset=>1 + signal ex1_cr0_byp_pri_dbg_q : std_ulogic_vector(1 to 6); -- input=>rf1_cr0_byp_pri , act=>trace_bus_enable , scan=>Y, sleep=>Y, needs_sreset=>0 + signal ex1_cr1_byp_pri_dbg_q : std_ulogic_vector(1 to 6); -- input=>rf1_cr1_byp_pri , act=>trace_bus_enable , scan=>Y, sleep=>Y, needs_sreset=>0 + signal ex1_crt_byp_pri_dbg_q : std_ulogic_vector(1 to 6); -- input=>rf1_crt_byp_pri , act=>trace_bus_enable , scan=>Y, sleep=>Y, needs_sreset=>0 + signal ex6_val_dbg_q : std_ulogic_vector(0 to threads-1); -- input=>ex5_val , act=>trace_bus_enable , scan=>Y, sleep=>Y, needs_sreset=>0 + + constant ex1_alu_cmp_offset : integer := 0; + constant ex1_any_mtcrf_offset : integer := ex1_alu_cmp_offset + 1; + constant ex1_cr0_offset : integer := ex1_any_mtcrf_offset + 1; + constant ex1_cr0_bit_offset : integer := ex1_cr0_offset + ex1_cr0_q'length; + constant ex1_cr1_offset : integer := ex1_cr0_bit_offset + 1; + constant ex1_cr1_bit_offset : integer := ex1_cr1_offset + ex1_cr1_q'length; + constant ex1_cr_so_update_offset : integer := ex1_cr1_bit_offset + 1; + constant ex1_cr_we_offset : integer := ex1_cr_so_update_offset + ex1_cr_so_update_q'length; + constant ex1_crt_offset : integer := ex1_cr_we_offset + 1; + constant ex1_crt_mask_offset : integer := ex1_crt_offset + ex1_crt_q'length; + constant ex1_instr_offset : integer := ex1_crt_mask_offset + ex1_crt_mask_q'length; + constant ex1_instr_2_offset : integer := ex1_instr_offset + ex1_instr_q'length; + constant ex1_is_mcrf_offset : integer := ex1_instr_2_offset + ex1_instr_2_q'length; + constant ex1_use_crfld0_offset : integer := ex1_is_mcrf_offset + 1; + constant ex3_any_mtcrf_offset : integer := ex1_use_crfld0_offset + 1; + constant ex3_cr_offset : integer := ex3_any_mtcrf_offset + 1; + constant ex3_div_done_offset : integer := ex3_cr_offset + ex3_cr_q'length; + constant ex3_instr_offset : integer := ex3_div_done_offset + 1; + constant ex5_any_mtcrf_offset : integer := ex3_instr_offset + ex3_instr_q'length; + constant ex5_axu_val_offset : integer := ex5_any_mtcrf_offset + 1; + constant ex5_cr_offset : integer := ex5_axu_val_offset + ex5_axu_val_q'length; + constant ex5_dp_instr_offset : integer := ex5_cr_offset + ex5_cr_q'length; + constant ex5_fu_cr0_offset : integer := ex5_dp_instr_offset + 1; + constant ex5_fu_cr0_bf_offset : integer := ex5_fu_cr0_offset + ex5_fu_cr0_q'length; + constant ex5_fu_cr1_offset : integer := ex5_fu_cr0_bf_offset + ex5_fu_cr0_bf_q'length; + constant ex5_fu_cr1_bf_offset : integer := ex5_fu_cr1_offset + ex5_fu_cr1_q'length; + constant ex5_fu_cr2_offset : integer := ex5_fu_cr1_bf_offset + ex5_fu_cr1_bf_q'length; + constant ex5_fu_cr2_bf_offset : integer := ex5_fu_cr2_offset + ex5_fu_cr2_q'length; + constant ex5_fu_cr3_offset : integer := ex5_fu_cr2_bf_offset + ex5_fu_cr2_bf_q'length; + constant ex5_fu_cr3_bf_offset : integer := ex5_fu_cr3_offset + ex5_fu_cr3_q'length; + constant ex5_fu_cr_noflush_offset : integer := ex5_fu_cr3_bf_offset + ex5_fu_cr3_bf_q'length; + constant ex5_fu_cr_val_offset : integer := ex5_fu_cr_noflush_offset + ex5_fu_cr_noflush_q'length; + constant ex5_is_eratsxr_offset : integer := ex5_fu_cr_val_offset + ex5_fu_cr_val_q'length; + constant ex5_mfdp_cr_status_offset : integer := ex5_is_eratsxr_offset + 1; + constant ex5_mfdp_val_offset : integer := ex5_mfdp_cr_status_offset + 1; + constant ex5_mtdp_cr_status_offset : integer := ex5_mfdp_val_offset + 1; + constant ex5_mtdp_val_offset : integer := ex5_mtdp_cr_status_offset + 1; + constant ex5_val_offset : integer := ex5_mtdp_val_offset + 1; + constant ex5_watch_we_offset : integer := ex5_val_offset + ex5_val_q'length; + constant ex5_wchkall_fld_offset : integer := ex5_watch_we_offset + 1; + constant an_ac_back_inv_offset : integer := ex5_wchkall_fld_offset + ex5_wchkall_fld_q'length; + constant an_ac_back_inv_addr_offset : integer := an_ac_back_inv_offset + 1; + constant an_ac_back_inv_target_bit3_offset : integer := an_ac_back_inv_addr_offset + an_ac_back_inv_addr_q'length; + constant back_inv_val_offset : integer := an_ac_back_inv_target_bit3_offset + 1; + constant cr_barrier_we_offset : integer := back_inv_val_offset + 1; + constant exx_act_offset : integer := cr_barrier_we_offset + cr_barrier_we_q'length; + constant mmu_cr0_eq_offset : integer := exx_act_offset + exx_act_q'length; + constant mmu_cr0_eq_valid_offset : integer := mmu_cr0_eq_offset + mmu_cr0_eq_q'length; + constant stcx_complete_offset : integer := mmu_cr0_eq_valid_offset + mmu_cr0_eq_valid_q'length; + constant stcx_pass_offset : integer := stcx_complete_offset + stcx_complete_q'length; + constant ex1_cr0_byp_pri_dbg_offset : integer := stcx_pass_offset + stcx_pass_q'length; + constant ex1_cr1_byp_pri_dbg_offset : integer := ex1_cr0_byp_pri_dbg_offset + ex1_cr0_byp_pri_dbg_q'length; + constant ex1_crt_byp_pri_dbg_offset : integer := ex1_cr1_byp_pri_dbg_offset + ex1_cr1_byp_pri_dbg_q'length; + constant ex6_val_dbg_offset : integer := ex1_crt_byp_pri_dbg_offset + ex1_crt_byp_pri_dbg_q'length; + constant cr_barrier_offset : integer := ex6_val_dbg_offset + ex6_val_dbg_q'length; + constant cr_offset : integer := cr_barrier_offset + 4*threads; + constant scan_right : integer := cr_offset + 32*threads; + signal siv : std_ulogic_vector(0 to scan_right-1); + signal sov : std_ulogic_vector(0 to scan_right-1); + -- Signals + signal rf1_cr0 : std_ulogic_vector(0 to 3); + signal rf1_cr1 : std_ulogic_vector(0 to 3); + signal rf1_cr0_cmp, rf1_cr1_cmp : std_ulogic_vector(1 to 5); + signal rf1_cr0_byp_pri, rf1_cr1_byp_pri : std_ulogic_vector(1 to 6); + signal rf1_crt_cmp : std_ulogic_vector(1 to 5); + signal rf1_crt_byp_pri : std_ulogic_vector(1 to 6); + signal rf1_cr1_val : std_ulogic_vector(1 to 5); + signal rf1_cr0_val : std_ulogic_vector(1 to 5); + signal rf1_crt_val : std_ulogic_vector(1 to 5); + signal rf1_byp_val : std_ulogic_vector(1 to 5); + signal rf1_axu_byp_val : std_ulogic_vector(4 to 5); + signal rf1_isel_fcn : std_ulogic_vector(0 to 3); + signal ex1_xer_so : std_ulogic; + signal ex2_xer_so : std_ulogic; + signal ex3_xer_so : std_ulogic; + signal ex5_xer_so : std_ulogic; + signal ex1_cr_so : std_ulogic; + signal ex2_cr_recform : std_ulogic_vector(0 to 7); + signal ex3_cr_div : std_ulogic_vector(0 to 7); + signal ex5_cr_mul : std_ulogic_vector(0 to 7); + signal ex5_cr_dp : std_ulogic_vector(0 to 7); + signal ex1_cr : std_ulogic_vector(0 to 7); + signal ex3_cr : std_ulogic_vector(0 to 7); + signal ex2_cr : std_ulogic_vector(0 to 7); + signal ex4_cr : std_ulogic_vector(0 to 7); + signal ex5_cr, ex5_cr_fu : std_ulogic_vector(0 to 7); + signal ex5_val, ex5_axu_val : std_ulogic_vector(0 to threads-1); + signal cr_out : std_ulogic_vector(0 to 32*threads-1); + signal cr_mux : std_ulogic_vector(0 to 31); + signal cr0_out, cr1_out : std_ulogic_vector(0 to 3); + signal crt_out : std_ulogic_vector(0 to 3); + signal ex1_cr_mcrf : std_ulogic_vector(0 to 7); + signal ex1_cr_not_mcrf : std_ulogic_vector(0 to 7); + signal rf1_mfocrf_src : std_ulogic_vector(0 to 2); + signal rf1_cr0_source : std_ulogic_vector(0 to 2); + signal rf1_cr1_source : std_ulogic_vector(0 to 4); + signal icswx_tid : std_ulogic_vector(0 to threads-1); + signal ex5_eratsxr_we : std_ulogic_vector(0 to threads-1); + signal ex5_cr_we : std_ulogic_vector(0 to threads-1); + signal ex5_cr_act : std_ulogic_vector(0 to threads-1); + signal ex1_log_cr_bit : std_ulogic; + signal ex1_log_cr : std_ulogic_vector(0 to 3); + signal ex5_fu_cr : CR_ARY; + signal ex5_fu_cr_val : std_ulogic_vector(0 to threads-1); + signal ex5_cr_watch : std_ulogic_vector(0 to 7); + signal ex5_cr_instr : std_ulogic_vector(0 to 7); + signal ex5_cr_instr_update_b : std_ulogic; + signal ex5_instr_cr_dec : std_ulogic_vector(0 to 7); + signal ex5_fu_cr_valid : std_ulogic; + signal ex5_instr_cr_val : std_ulogic_vector(0 to threads-1); + signal ex5_mtcr_val : std_ulogic_vector(0 to threads-1); + signal ex5_icswx_we : std_ulogic_vector(0 to threads-1); + signal cr_grp0_debug_int : std_ulogic_vector(0 to 87); + signal exx_act : std_ulogic_vector(0 to 4); + signal ex4_axu_act : std_ulogic; + +begin + + --------------------------------------------------------------------- + -- Misc Assignments + --------------------------------------------------------------------- + exx_act_d <= dec_byp_rf0_act & exx_act_q(0 to 3); + + exx_act(0) <= exx_act_q(0); + exx_act(1) <= exx_act_q(1); + exx_act(2) <= exx_act_q(2); + exx_act(3) <= exx_act_q(3); + exx_act(4) <= exx_act_q(4); + + ex4_axu_act <= '1'; + + ex1_any_mtcrf_d <= (dec_byp_rf1_is_mtcrf or dec_byp_rf1_is_mtocrf); + + ex3_val <= dec_byp_ex3_val and not xu_ex3_flush; + ex4_val <= ex4_val_q and not xu_ex4_flush; + ex5_val <= ex5_val_q and not xu_ex5_flush; + + ex4_axu_val <= fu_xu_ex4_cr_val and not (xu_ex4_flush and not fu_xu_ex4_cr_noflush); + ex5_axu_val <= ex5_axu_val_q and not (xu_ex5_flush and not ex5_fu_cr_noflush_q); + + + --------------------------------------------------------------------- + -- CR Pipeline Input + --------------------------------------------------------------------- + ex1_xer_so <= or_reduce(byp_xer_so and ex1_tid) or xer_cr_ex1_xer_ov_in_pipe; + ex2_xer_so <= or_reduce(byp_xer_so and ex2_tid) or xer_cr_ex2_xer_ov_in_pipe; + ex3_xer_so <= or_reduce(byp_xer_so and ex3_tid) or xer_cr_ex3_xer_ov_in_pipe; + ex5_xer_so <= or_reduce(byp_xer_so and ex5_tid) or xer_cr_ex5_xer_ov_in_pipe; + + -- EX1 -- + with ex1_cr_so_update_q select + ex1_cr_so <= (ex1_xer_so or ex1_log_cr(3)) when "01", + ex1_log_cr(3) when "10", + ex1_xer_so when others; + + -- xxx_cr_q(0 to 3) <= CR field + -- xxx_cr_q(4 to 6) <= CR target + -- xxx_cr_q(7) <= CR write enable + + ex1_cr_mcrf <= ex1_cr1_q & + ex1_instr_q(6 to 8)& + ex1_cr_we_q; + + ex1_cr_not_mcrf <= ex1_log_cr(0 to 2) & ex1_cr_so & + ex1_instr_q(6 to 8) & + ex1_cr_we_q; + + with ex1_is_mcrf_q select + ex1_cr <= ex1_cr_not_mcrf when '0', + ex1_cr_mcrf when others; + + -- EX2 -- + ex2_cr_recform <= alu_byp_ex2_cr_recform(0 to 2) & (alu_byp_ex2_cr_recform(3) or ex2_xer_so) & + (ex2_instr_q(6 to 8) and (6 to 8 => not ex2_use_crfld0_q)) & + ex2_cr_we_q; + + with ex2_alu_cmp_q select + ex2_cr <= ex2_cr_recform when '1', + ex2_cr_q when others; + + -- EX3 -- + ex3_cr_div <= alu_byp_ex3_cr_div(0 to 2) & (alu_byp_ex3_cr_div(3) or ex3_xer_so) & + (4 to 6 => tidn) & + alu_byp_ex3_cr_div(4); + + + with ex3_div_done_q select + ex3_cr <= ex3_cr_div when '1', + ex3_cr_q when others; + + -- EX4 + ex4_cr <= ex4_cr_q; + + -- EX5 + ex5_cr_dp <= "00" & -- Bits 0,1 + ((ex5_mtdp_cr_status_q and ex5_mtdp_val_q) or + (ex5_mfdp_cr_status_q and ex5_mfdp_val_q)) & -- Bit 2 + ex5_xer_so & -- Bit 3 + (4 to 6 => tidn) & -- Field + ex5_dp_instr_q; -- Valid + + ex5_cr_mul <= alu_byp_ex5_cr_mul(0 to 2) & (alu_byp_ex5_cr_mul(3) or ex5_xer_so) & + (4 to 6 => tidn) & + alu_byp_ex5_cr_mul(4); + + + -- EX5 - Non Bypassed + ex5_wchkall_fld_d <= gate(ex4_instr_q(6 to 8),dec_byp_ex4_is_wchkall); + ex5_watch_we_d <= dec_byp_ex4_is_wchkall or lsu_xu_ex4_cr_upd; + + ex5_cr_watch <=("00" & lsu_xu_ex5_cr_rslt & ex5_xer_so) & + ex5_wchkall_fld_q & + ex5_watch_we_q; + + ex5_fu_cr(0) <= ex5_fu_cr0_q & ex5_fu_cr0_bf_q & ex5_fu_cr_val_q(0); + ex5_fu_cr(1) <= ex5_fu_cr1_q & ex5_fu_cr1_bf_q & ex5_fu_cr_val_q(1); + ex5_fu_cr(2) <= ex5_fu_cr2_q & ex5_fu_cr2_bf_q & ex5_fu_cr_val_q(2); + ex5_fu_cr(3) <= ex5_fu_cr3_q & ex5_fu_cr3_bf_q & ex5_fu_cr_val_q(3); + + -- EX5 Bypass Muxing + ex5_fu_cr_valid <= or_reduce(rf1_tid and ex5_fu_cr_val_q); + ex5_cr_instr_update_b <= not(ex5_cr_dp(7) or ex5_cr_mul(7) or ex5_cr_watch(7)); + + ex5_cr_fu <= gate(ex5_fu_cr(0), rf1_tid(0)) or + gate(ex5_fu_cr(1), rf1_tid(1)) or + gate(ex5_fu_cr(2), rf1_tid(2)) or + gate(ex5_fu_cr(3), rf1_tid(3)); + + + ex5_cr_instr <= gate(ex5_cr_dp, ex5_cr_dp(7) ) or + gate(ex5_cr_mul, ex5_cr_mul(7) ) or + gate(ex5_cr_watch, ex5_cr_watch(7) ) or + gate(ex5_cr_q, ex5_cr_instr_update_b); + + ex5_cr <= gate(ex5_cr_instr, not(ex5_fu_cr_valid)) or + gate(ex5_cr_fu, ex5_fu_cr_valid ); + + --------------------------------------------------------------------- + -- MFOCRF + --------------------------------------------------------------------- + -- Decode FXM Field + with rf1_instr(12 to 19) select + rf1_mfocrf_src <= "000" when "10000000", + "001" when "01000000", + "010" when "00100000", + "011" when "00010000", + "100" when "00001000", + "101" when "00000100", + "110" when "00000010", + "111" when "00000001", + "000" when others; + + with rf1_is_mfocrf_q select + rf1_cr0_source <= rf1_mfocrf_src when '1', + rf1_instr(16 to 18) when others; + + --------------------------------------------------------------------- + -- ISEL + --------------------------------------------------------------------- + with dec_byp_rf1_is_isel select + rf1_cr1_source <= rf1_instr(21 to 25) when '1', + rf1_instr(11 to 15) when others; + + --------------------------------------------------------------------- + -- RF1 Bypass Control + --------------------------------------------------------------------- + -- These bypass valids take into account the new CRs from the AXU + rf1_axu_byp_val(4) <= or_reduce(rf1_tid and ex4_val_q); + rf1_axu_byp_val(5) <= or_reduce(rf1_tid and (ex5_val_q or ex5_fu_cr_val_q)); + + rf1_byp_val(1) <= ex1_cr(7) and dec_byp_rf1_byp_val(1); + rf1_byp_val(2) <= ex2_cr(7) and dec_byp_rf1_byp_val(2); + rf1_byp_val(3) <= ex3_cr(7) and dec_byp_rf1_byp_val(3); + rf1_byp_val(4) <= ex4_cr(7) and rf1_axu_byp_val(4); + rf1_byp_val(5) <= ex5_cr(7) and rf1_axu_byp_val(5); + + -- Source Target + rf1_cr0_cmp(1) <= '1' when rf1_cr0_source = ex1_cr(4 to 6) else '0'; + rf1_cr0_cmp(2) <= '1' when rf1_cr0_source = ex2_cr(4 to 6) else '0'; + rf1_cr0_cmp(3) <= '1' when rf1_cr0_source = ex3_cr(4 to 6) else '0'; + rf1_cr0_cmp(4) <= '1' when rf1_cr0_source = ex4_cr(4 to 6) else '0'; + rf1_cr0_cmp(5) <= '1' when rf1_cr0_source = ex5_cr(4 to 6) else '0'; + + -- Bypass Prioritization + rf1_cr0_val <= rf1_cr0_cmp and rf1_byp_val; + + rf1_cr0_byp_pri(1) <= rf1_cr0_val(1); + rf1_cr0_byp_pri(2) <= not rf1_cr0_val(1) and rf1_cr0_val(2); + rf1_cr0_byp_pri(3) <= not or_reduce(rf1_cr0_val(1 to 2)) and rf1_cr0_val(3); + rf1_cr0_byp_pri(4) <= not or_reduce(rf1_cr0_val(1 to 3)) and rf1_cr0_val(4); + rf1_cr0_byp_pri(5) <= not or_reduce(rf1_cr0_val(1 to 4)) and rf1_cr0_val(5); + rf1_cr0_byp_pri(6) <= not or_reduce(rf1_cr0_val(1 to 5)); + + -- Source Target + rf1_cr1_cmp(1) <= '1' when rf1_cr1_source(0 to 2) = ex1_cr(4 to 6) else '0'; + rf1_cr1_cmp(2) <= '1' when rf1_cr1_source(0 to 2) = ex2_cr(4 to 6) else '0'; + rf1_cr1_cmp(3) <= '1' when rf1_cr1_source(0 to 2) = ex3_cr(4 to 6) else '0'; + rf1_cr1_cmp(4) <= '1' when rf1_cr1_source(0 to 2) = ex4_cr(4 to 6) else '0'; + rf1_cr1_cmp(5) <= '1' when rf1_cr1_source(0 to 2) = ex5_cr(4 to 6) else '0'; + + -- Bypass Prioritization + rf1_cr1_val <= rf1_cr1_cmp and rf1_byp_val; + + rf1_cr1_byp_pri(1) <= rf1_cr1_val(1); + rf1_cr1_byp_pri(2) <= not rf1_cr1_val(1) and rf1_cr1_val(2); + rf1_cr1_byp_pri(3) <= not or_reduce(rf1_cr1_val(1 to 2)) and rf1_cr1_val(3); + rf1_cr1_byp_pri(4) <= not or_reduce(rf1_cr1_val(1 to 3)) and rf1_cr1_val(4); + rf1_cr1_byp_pri(5) <= not or_reduce(rf1_cr1_val(1 to 4)) and rf1_cr1_val(5); + rf1_cr1_byp_pri(6) <= not or_reduce(rf1_cr1_val(1 to 5)); + + -- Source Target + rf1_crt_cmp(1) <= '1' when rf1_instr(6 to 8) = ex1_cr(4 to 6) else '0'; + rf1_crt_cmp(2) <= '1' when rf1_instr(6 to 8) = ex2_cr(4 to 6) else '0'; + rf1_crt_cmp(3) <= '1' when rf1_instr(6 to 8) = ex3_cr(4 to 6) else '0'; + rf1_crt_cmp(4) <= '1' when rf1_instr(6 to 8) = ex4_cr(4 to 6) else '0'; + rf1_crt_cmp(5) <= '1' when rf1_instr(6 to 8) = ex5_cr(4 to 6) else '0'; + + -- Bypass Prioritization + rf1_crt_val <= rf1_crt_cmp and rf1_byp_val; + + rf1_crt_byp_pri(1) <= rf1_crt_val(1); + rf1_crt_byp_pri(2) <= not rf1_crt_val(1) and rf1_crt_val(2); + rf1_crt_byp_pri(3) <= not or_reduce(rf1_crt_val(1 to 2)) and rf1_crt_val(3); + rf1_crt_byp_pri(4) <= not or_reduce(rf1_crt_val(1 to 3)) and rf1_crt_val(4); + rf1_crt_byp_pri(5) <= not or_reduce(rf1_crt_val(1 to 4)) and rf1_crt_val(5); + rf1_crt_byp_pri(6) <= not or_reduce(rf1_crt_val(1 to 5)); + + + --------------------------------------------------------------------- + -- RF1 Source Selection + --------------------------------------------------------------------- + rf1_cr0 <= gate(ex1_cr(0 to 3), rf1_cr0_byp_pri(1)) or + gate(ex2_cr(0 to 3), rf1_cr0_byp_pri(2)) or + gate(ex3_cr(0 to 3), rf1_cr0_byp_pri(3)) or + gate(ex4_cr(0 to 3), rf1_cr0_byp_pri(4)) or + gate(ex5_cr(0 to 3), rf1_cr0_byp_pri(5)) or + gate(cr0_out(0 to 3), rf1_cr0_byp_pri(6)); + + with rf1_instr(19 to 20) select + rf1_cr0_bit <= rf1_cr0(0) when "00", + rf1_cr0(1) when "01", + rf1_cr0(2) when "10", + rf1_cr0(3) when others; + + rf1_cr1 <= gate(ex1_cr(0 to 3), rf1_cr1_byp_pri(1)) or + gate(ex2_cr(0 to 3), rf1_cr1_byp_pri(2)) or + gate(ex3_cr(0 to 3), rf1_cr1_byp_pri(3)) or + gate(ex4_cr(0 to 3), rf1_cr1_byp_pri(4)) or + gate(ex5_cr(0 to 3), rf1_cr1_byp_pri(5)) or + gate(cr1_out(0 to 3), rf1_cr1_byp_pri(6)); + + with rf1_cr1_source(3 to 4) select + rf1_cr1_bit_i <= rf1_cr1(0) when "00", + rf1_cr1(1) when "01", + rf1_cr1(2) when "10", + rf1_cr1(3) when others; + + rf1_crt <= gate(ex1_cr(0 to 3), rf1_crt_byp_pri(1)) or + gate(ex2_cr(0 to 3), rf1_crt_byp_pri(2)) or + gate(ex3_cr(0 to 3), rf1_crt_byp_pri(3)) or + gate(ex4_cr(0 to 3), rf1_crt_byp_pri(4)) or + gate(ex5_cr(0 to 3), rf1_crt_byp_pri(5)) or + gate(crt_out(0 to 3), rf1_crt_byp_pri(6)); + + -- For ISEL + rf1_isel_fcn <= '0' & not(rf1_cr1_bit_i) & rf1_cr1_bit_i & '1'; + + byp_alu_rf1_isel_fcn <= gate(rf1_isel_fcn,dec_byp_rf1_is_isel); + + --------------------------------------------------------------------- + -- CR Logicals + --------------------------------------------------------------------- + with rf1_instr(9 to 10) select + rf1_crt_mask <= "1000" when "00", + "0100" when "01", + "0010" when "10", + "0001" when others; + + ex1_log_cr_bit <= + (ex1_instr_2_q(25) and not ex1_cr1_bit_q and not ex1_cr0_bit_q) or + (ex1_instr_2_q(24) and not ex1_cr1_bit_q and ex1_cr0_bit_q) or + (ex1_instr_2_q(23) and ex1_cr1_bit_q and not ex1_cr0_bit_q) or + (ex1_instr_2_q(22) and ex1_cr1_bit_q and ex1_cr0_bit_q); + + ex1_log_cr(0) <= (ex1_crt_q(0) and not ex1_crt_mask_q(0)) or (ex1_log_cr_bit and ex1_crt_mask_q(0)); + ex1_log_cr(1) <= (ex1_crt_q(1) and not ex1_crt_mask_q(1)) or (ex1_log_cr_bit and ex1_crt_mask_q(1)); + ex1_log_cr(2) <= (ex1_crt_q(2) and not ex1_crt_mask_q(2)) or (ex1_log_cr_bit and ex1_crt_mask_q(2)); + ex1_log_cr(3) <= (ex1_crt_q(3) and not ex1_crt_mask_q(3)) or (ex1_log_cr_bit and ex1_crt_mask_q(3)); + + byp_cpl_ex1_cr_bit <= ex1_cr1_bit_q; + + -- xxx_cr_q(0 to 3) <= CR field + -- xxx_cr_q(4 to 6) <= CR target + -- xxx_cr_q(7) <= CR write enable + + --------------------------------------------------------------------- + -- CR Pipline Decode/Muxing + --------------------------------------------------------------------- + with ex5_cr_instr(4 to 6) select + ex5_instr_cr_dec <= "10000000" when "000", + "01000000" when "001", + "00100000" when "010", + "00010000" when "011", + "00001000" when "100", + "00000100" when "101", + "00000010" when "110", + "00000001" when others; + + + --------------------------------------------------------------------- + -- ICSWX + --------------------------------------------------------------------- + with an_ac_back_inv_addr_q(62 to 63) select + icswx_tid <= "1000" when "00", + "0100" when "01", + "0010" when "10", + "0001" when others; + + back_inv_val_d <= an_ac_back_inv_q and an_ac_back_inv_target_bit3_q; + ex5_icswx_we <= gate(icswx_tid, back_inv_val_q); + + --------------------------------------------------------------------- + -- "Async" CR Updates + --------------------------------------------------------------------- + -- Delay all these by a cycle for timing. + cr_barrier_we_d <= stcx_complete_q or mmu_cr0_eq_valid_q or ex5_icswx_we; + + --------------------------------------------------------------------- + -- CR Writeback + --------------------------------------------------------------------- + xuq_byp_cr_gen : for t in 0 to threads-1 generate + + signal cr_q, cr_d : std_ulogic_vector(32 to 63); + signal cr_barrier_q, cr_barrier_d : std_ulogic_vector(32 to 35); + + signal ex5_fu_cr_dec : std_ulogic_vector(0 to 7); + signal ex5_fu_we : std_ulogic_vector(0 to 7); + signal ex5_instr_we : std_ulogic_vector(0 to 7); + signal ex5_mtcr_we : std_ulogic_vector(0 to 7); + + begin + + -- FU CR decode + with ex5_fu_cr(t)(4 to 6) select + ex5_fu_cr_dec <= "10000000" when "000", + "01000000" when "001", + "00100000" when "010", + "00010000" when "011", + "00001000" when "100", + "00000100" when "101", + "00000010" when "110", + "00000001" when others; + + --------------------------------------------------------------------- + -- CR Write Enables + --------------------------------------------------------------------- + ex5_fu_cr_val(t) <= ex5_fu_cr(t)(7) and ex5_axu_val(t); + ex5_fu_we <= gate(ex5_fu_cr_dec,ex5_fu_cr_val(t)); + + ex5_instr_cr_val(t) <= ex5_cr_instr(7) and ex5_val(t); + ex5_instr_we <= gate(ex5_instr_cr_dec,ex5_instr_cr_val(t)); + + ex5_mtcr_val(t) <= ex5_any_mtcrf_q and ex5_val(t); + ex5_mtcr_we <= gate(dec_cr_ex5_instr(12 to 19),ex5_mtcr_val(t)); + + ex5_eratsxr_we(t) <= ex5_is_eratsxr_q and ex5_val(t); + + --------------------------------------------------------------------- + -- CR Muxing + --------------------------------------------------------------------- + + with s3'(stcx_complete_q(t) & mmu_cr0_eq_valid_q(t) & ex5_icswx_we(t)) select + cr_barrier_d(32 to 35) <= "00" & stcx_pass_q(t) & byp_xer_so(t) when "100", + "00" & mmu_cr0_eq_q(t) & tidn when "010", + an_ac_back_inv_addr_q(58 to 60) & tidn when others; + + + with s5'(ex5_eratsxr_we(t) & ex5_mtcr_we(0) & ex5_instr_we(0) & ex5_fu_we(0) & cr_barrier_we_q(t)) select + cr_d(32 to 35) <= "00" & byp_ex5_tlb_rt(51) & tidn when "10000", + byp_ex5_mtcrxer(32 to 35) when "01000", + ex5_cr_instr(0 to 3) when "00100", + ex5_fu_cr(t)(0 to 3) when "00010", + cr_barrier_q when "00001", + cr_q(32 to 35) when others; + + xuq_byp_cr_field_gen : for f in 1 to 7 generate + + with s3'(ex5_mtcr_we(f) & ex5_instr_we(f) & ex5_fu_we(f)) select + cr_d(32+f*4 to 35+f*4) <= byp_ex5_mtcrxer(32+f*4 to 35+f*4) when "100", + ex5_cr_instr(0 to 3) when "010", + ex5_fu_cr(t)(0 to 3) when "001", + cr_q(32+f*4 to 35+f*4) when others; + + end generate; + + ex5_cr_act(t) <= ex5_val_q(t) or ex5_axu_val_q(t) or cr_barrier_we_q(t); + + + -- For RTX (SIM ONLY) + ex5_cr_we(t) <= ex5_eratsxr_we(t) or + cr_barrier_we_q(t) or + or_reduce(ex5_mtcr_we or ex5_instr_we or ex5_fu_we) or + (ex5_val(t) and ex5_any_mtcrf_q); -- mtcrf 0x00 case + + cr_out(t*32 to t*32+31) <= cr_q; + + --------------------------------------------------------------------- + -- Performance Events + --------------------------------------------------------------------- + byp_perf_tx_events(0+3*t) <= stcx_complete_q(t) and not stcx_pass_q(t); -- STCX Fail + byp_perf_tx_events(1+3*t) <= ex5_icswx_we(t) and not an_ac_back_inv_addr_q(59); -- icswx failed + byp_perf_tx_events(2+3*t) <= ex5_icswx_we(t) and an_ac_back_inv_addr_q(59); -- icswx finished + + + cr_barrier_latch : tri_rlmreg_p + generic map (width => cr_barrier_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(cr_barrier_offset + cr_barrier_q'length*t to cr_barrier_offset + cr_barrier_q'length*(t+1)-1), + scout => sov(cr_barrier_offset + cr_barrier_q'length*t to cr_barrier_offset + cr_barrier_q'length*(t+1)-1), + din => cr_barrier_d, + dout => cr_barrier_q); + cr_latch : tri_rlmreg_p + generic map (width => cr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => ex5_cr_act(t), + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(cr_offset + cr_q'length*t to cr_offset + cr_q'length*(t+1)-1), + scout => sov(cr_offset + cr_q'length*t to cr_offset + cr_q'length*(t+1)-1), + din => cr_d, + dout => cr_q); + end generate; + + --------------------------------------------------------------------- + -- CR Read Ports + --------------------------------------------------------------------- + xuq_byp_cr_mfocr : for t in 0 to 7 generate + ex1_mfocrf_rt(t*4+32 to t*4+35) <= gate(ex1_cr0_q,ex1_instr_q(t+12)); + end generate; + xuq_byp_cr_mfocr_z : if regsize > 32 generate + ex1_mfocrf_rt(0 to 31) <= (others=>'0'); + end generate; + + ex5_cr_rt <= mux_t(cr_out,ex5_tid); + + cr_mux <= mux_t(cr_out,rf1_tid); + + with rf1_cr0_source select + cr0_out <= cr_mux(0 to 3) when "000", + cr_mux(4 to 7) when "001", + cr_mux(8 to 11) when "010", + cr_mux(12 to 15) when "011", + cr_mux(16 to 19) when "100", + cr_mux(20 to 23) when "101", + cr_mux(24 to 27) when "110", + cr_mux(28 to 31) when others; + + with rf1_cr1_source(0 to 2) select + cr1_out <= cr_mux(0 to 3) when "000", + cr_mux(4 to 7) when "001", + cr_mux(8 to 11) when "010", + cr_mux(12 to 15) when "011", + cr_mux(16 to 19) when "100", + cr_mux(20 to 23) when "101", + cr_mux(24 to 27) when "110", + cr_mux(28 to 31) when others; + + with rf1_instr(6 to 8) select + crt_out <= cr_mux(0 to 3) when "000", + cr_mux(4 to 7) when "001", + cr_mux(8 to 11) when "010", + cr_mux(12 to 15) when "011", + cr_mux(16 to 19) when "100", + cr_mux(20 to 23) when "101", + cr_mux(24 to 27) when "110", + cr_mux(28 to 31) when others; + + + mark_unused(ex5_cr_we); + mark_unused(ex1_instr_q(9 to 11)); + mark_unused(an_ac_back_inv_addr_q(61)); + + --------------------------------------------------------------------- + -- Debug + --------------------------------------------------------------------- + cr_grp0_debug <= cr_grp0_debug_int; + cr_grp0_debug_int <= ex6_val_dbg_q & + ex5_fu_cr_val_q & + ex5_fu_cr_noflush_q & + ex1_cr_so_update_q(0 to 1) & + ex1_is_mcrf_q & + ex2_alu_cmp_q & + ex3_div_done_q & + ex5_watch_we_q & + ex5_dp_instr_q & + alu_byp_ex5_cr_mul(4) & + ex5_any_mtcrf_q & + ex5_is_eratsxr_q & + stcx_complete_q(0 to 3) & + mmu_cr0_eq_valid_q(0 to 3) & + ex1_cr1_bit_q & + an_ac_back_inv_q & + an_ac_back_inv_target_bit3_q & + an_ac_back_inv_addr_q(62 to 63) & + ex5_fu_cr(0)(4 to 6) & + ex5_fu_cr(1)(4 to 6) & + ex5_fu_cr(2)(4 to 6) & + ex5_fu_cr(3)(4 to 6) & + ex5_cr_instr(4 to 6) & + dec_cr_ex5_instr(12 to 19) & + ex1_cr0_q(0 to 3) & + ex1_cr1_q(0 to 3) & + ex1_crt_q(0 to 3) & + ex1_cr0_byp_pri_dbg_q(1 to 6) & + ex1_cr1_byp_pri_dbg_q(1 to 6) & + ex1_crt_byp_pri_dbg_q(1 to 6); + + cr_grp1_debug <= cr_grp0_debug_int(0 to 71) & + ex3_cr_q(0 to 7) & + ex5_cr_q(0 to 7); + + --------------------------------------------------------------------- + -- Latches + --------------------------------------------------------------------- +rf1_is_mfocrf_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => fxa_fxb_rf0_is_mfocrf , + dout(0) => rf1_is_mfocrf_q); +ex1_alu_cmp_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_alu_cmp_offset), + scout => sov(ex1_alu_cmp_offset), + din => dec_byp_rf1_alu_cmp , + dout => ex1_alu_cmp_q); +ex1_any_mtcrf_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_any_mtcrf_offset), + scout => sov(ex1_any_mtcrf_offset), + din => ex1_any_mtcrf_d, + dout => ex1_any_mtcrf_q); +ex1_cr0_latch : tri_rlmreg_p + generic map (width => ex1_cr0_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_cr0_offset to ex1_cr0_offset + ex1_cr0_q'length-1), + scout => sov(ex1_cr0_offset to ex1_cr0_offset + ex1_cr0_q'length-1), + din => rf1_cr0 , + dout => ex1_cr0_q); +ex1_cr0_bit_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_cr0_bit_offset), + scout => sov(ex1_cr0_bit_offset), + din => rf1_cr0_bit, + dout => ex1_cr0_bit_q); +ex1_cr1_latch : tri_rlmreg_p + generic map (width => ex1_cr1_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_cr1_offset to ex1_cr1_offset + ex1_cr1_q'length-1), + scout => sov(ex1_cr1_offset to ex1_cr1_offset + ex1_cr1_q'length-1), + din => rf1_cr1 , + dout => ex1_cr1_q); +ex1_cr1_bit_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_cr1_bit_offset), + scout => sov(ex1_cr1_bit_offset), + din => rf1_cr1_bit_i, + dout => ex1_cr1_bit_q); +ex1_cr_so_update_latch : tri_rlmreg_p + generic map (width => ex1_cr_so_update_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_cr_so_update_offset to ex1_cr_so_update_offset + ex1_cr_so_update_q'length-1), + scout => sov(ex1_cr_so_update_offset to ex1_cr_so_update_offset + ex1_cr_so_update_q'length-1), + din => dec_byp_rf1_cr_so_update , + dout => ex1_cr_so_update_q); +ex1_cr_we_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_cr_we_offset), + scout => sov(ex1_cr_we_offset), + din => dec_byp_rf1_cr_we , + dout => ex1_cr_we_q); +ex1_crt_latch : tri_rlmreg_p + generic map (width => ex1_crt_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_crt_offset to ex1_crt_offset + ex1_crt_q'length-1), + scout => sov(ex1_crt_offset to ex1_crt_offset + ex1_crt_q'length-1), + din => rf1_crt, + dout => ex1_crt_q); +ex1_crt_mask_latch : tri_rlmreg_p + generic map (width => ex1_crt_mask_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_crt_mask_offset to ex1_crt_mask_offset + ex1_crt_mask_q'length-1), + scout => sov(ex1_crt_mask_offset to ex1_crt_mask_offset + ex1_crt_mask_q'length-1), + din => rf1_crt_mask, + dout => ex1_crt_mask_q); +ex1_instr_latch : tri_rlmreg_p + generic map (width => ex1_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_instr_offset to ex1_instr_offset + ex1_instr_q'length-1), + scout => sov(ex1_instr_offset to ex1_instr_offset + ex1_instr_q'length-1), + din => rf1_instr(6 to 19), + dout => ex1_instr_q); +ex1_instr_2_latch : tri_rlmreg_p + generic map (width => ex1_instr_2_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_instr_2_offset to ex1_instr_2_offset + ex1_instr_2_q'length-1), + scout => sov(ex1_instr_2_offset to ex1_instr_2_offset + ex1_instr_2_q'length-1), + din => rf1_instr(22 to 25), + dout => ex1_instr_2_q); +ex1_is_mcrf_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_mcrf_offset), + scout => sov(ex1_is_mcrf_offset), + din => dec_byp_rf1_is_mcrf , + dout => ex1_is_mcrf_q); +ex1_use_crfld0_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_use_crfld0_offset), + scout => sov(ex1_use_crfld0_offset), + din => dec_byp_rf1_use_crfld0 , + dout => ex1_use_crfld0_q); +ex2_alu_cmp_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_alu_cmp_q , + dout(0) => ex2_alu_cmp_q); +ex2_any_mtcrf_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_any_mtcrf_q , + dout(0) => ex2_any_mtcrf_q); +ex2_cr_latch : tri_regk + generic map (width => ex2_cr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex1_cr , + dout => ex2_cr_q); +ex2_cr_we_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_cr_we_q , + dout(0) => ex2_cr_we_q); +ex2_instr_latch : tri_regk + generic map (width => ex2_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex1_instr_q(6 to 8), + dout => ex2_instr_q); +ex2_use_crfld0_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_use_crfld0_q , + dout(0) => ex2_use_crfld0_q); +ex3_any_mtcrf_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_any_mtcrf_offset), + scout => sov(ex3_any_mtcrf_offset), + din => ex2_any_mtcrf_q , + dout => ex3_any_mtcrf_q); +ex3_cr_latch : tri_rlmreg_p + generic map (width => ex3_cr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_cr_offset to ex3_cr_offset + ex3_cr_q'length-1), + scout => sov(ex3_cr_offset to ex3_cr_offset + ex3_cr_q'length-1), + din => ex2_cr , + dout => ex3_cr_q); +ex3_div_done_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_div_done_offset), + scout => sov(ex3_div_done_offset), + din => alu_ex2_div_done , + dout => ex3_div_done_q); +ex3_instr_latch : tri_rlmreg_p + generic map (width => ex3_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_instr_offset to ex3_instr_offset + ex3_instr_q'length-1), + scout => sov(ex3_instr_offset to ex3_instr_offset + ex3_instr_q'length-1), + din => ex2_instr_q , + dout => ex3_instr_q); +ex4_any_mtcrf_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_any_mtcrf_q , + dout(0) => ex4_any_mtcrf_q); +ex4_cr_latch : tri_regk + generic map (width => ex4_cr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex3_cr , + dout => ex4_cr_q); +ex4_instr_latch : tri_regk + generic map (width => ex4_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex3_instr_q , + dout => ex4_instr_q); +ex4_val_latch : tri_regk + generic map (width => ex4_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex3_val, + dout => ex4_val_q); +ex5_any_mtcrf_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_any_mtcrf_offset), + scout => sov(ex5_any_mtcrf_offset), + din => ex4_any_mtcrf_q , + dout => ex5_any_mtcrf_q); +ex5_axu_val_latch : tri_rlmreg_p + generic map (width => ex5_axu_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_axu_val_offset to ex5_axu_val_offset + ex5_axu_val_q'length-1), + scout => sov(ex5_axu_val_offset to ex5_axu_val_offset + ex5_axu_val_q'length-1), + din => ex4_axu_val, + dout => ex5_axu_val_q); +ex5_cr_latch : tri_rlmreg_p + generic map (width => ex5_cr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_cr_offset to ex5_cr_offset + ex5_cr_q'length-1), + scout => sov(ex5_cr_offset to ex5_cr_offset + ex5_cr_q'length-1), + din => ex4_cr , + dout => ex5_cr_q); +ex5_dp_instr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_dp_instr_offset), + scout => sov(ex5_dp_instr_offset), + din => dec_byp_ex4_dp_instr , + dout => ex5_dp_instr_q); +ex5_fu_cr0_latch : tri_rlmreg_p + generic map (width => ex5_fu_cr0_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_axu_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_fu_cr0_offset to ex5_fu_cr0_offset + ex5_fu_cr0_q'length-1), + scout => sov(ex5_fu_cr0_offset to ex5_fu_cr0_offset + ex5_fu_cr0_q'length-1), + din => fu_xu_ex4_cr0 , + dout => ex5_fu_cr0_q); +ex5_fu_cr0_bf_latch : tri_rlmreg_p + generic map (width => ex5_fu_cr0_bf_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_axu_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_fu_cr0_bf_offset to ex5_fu_cr0_bf_offset + ex5_fu_cr0_bf_q'length-1), + scout => sov(ex5_fu_cr0_bf_offset to ex5_fu_cr0_bf_offset + ex5_fu_cr0_bf_q'length-1), + din => fu_xu_ex4_cr0_bf , + dout => ex5_fu_cr0_bf_q); +ex5_fu_cr1_latch : tri_rlmreg_p + generic map (width => ex5_fu_cr1_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_axu_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_fu_cr1_offset to ex5_fu_cr1_offset + ex5_fu_cr1_q'length-1), + scout => sov(ex5_fu_cr1_offset to ex5_fu_cr1_offset + ex5_fu_cr1_q'length-1), + din => fu_xu_ex4_cr1 , + dout => ex5_fu_cr1_q); +ex5_fu_cr1_bf_latch : tri_rlmreg_p + generic map (width => ex5_fu_cr1_bf_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_axu_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_fu_cr1_bf_offset to ex5_fu_cr1_bf_offset + ex5_fu_cr1_bf_q'length-1), + scout => sov(ex5_fu_cr1_bf_offset to ex5_fu_cr1_bf_offset + ex5_fu_cr1_bf_q'length-1), + din => fu_xu_ex4_cr1_bf , + dout => ex5_fu_cr1_bf_q); +ex5_fu_cr2_latch : tri_rlmreg_p + generic map (width => ex5_fu_cr2_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_axu_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_fu_cr2_offset to ex5_fu_cr2_offset + ex5_fu_cr2_q'length-1), + scout => sov(ex5_fu_cr2_offset to ex5_fu_cr2_offset + ex5_fu_cr2_q'length-1), + din => fu_xu_ex4_cr2 , + dout => ex5_fu_cr2_q); +ex5_fu_cr2_bf_latch : tri_rlmreg_p + generic map (width => ex5_fu_cr2_bf_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_axu_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_fu_cr2_bf_offset to ex5_fu_cr2_bf_offset + ex5_fu_cr2_bf_q'length-1), + scout => sov(ex5_fu_cr2_bf_offset to ex5_fu_cr2_bf_offset + ex5_fu_cr2_bf_q'length-1), + din => fu_xu_ex4_cr2_bf , + dout => ex5_fu_cr2_bf_q); +ex5_fu_cr3_latch : tri_rlmreg_p + generic map (width => ex5_fu_cr3_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_axu_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_fu_cr3_offset to ex5_fu_cr3_offset + ex5_fu_cr3_q'length-1), + scout => sov(ex5_fu_cr3_offset to ex5_fu_cr3_offset + ex5_fu_cr3_q'length-1), + din => fu_xu_ex4_cr3 , + dout => ex5_fu_cr3_q); +ex5_fu_cr3_bf_latch : tri_rlmreg_p + generic map (width => ex5_fu_cr3_bf_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_axu_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_fu_cr3_bf_offset to ex5_fu_cr3_bf_offset + ex5_fu_cr3_bf_q'length-1), + scout => sov(ex5_fu_cr3_bf_offset to ex5_fu_cr3_bf_offset + ex5_fu_cr3_bf_q'length-1), + din => fu_xu_ex4_cr3_bf , + dout => ex5_fu_cr3_bf_q); +ex5_fu_cr_noflush_latch : tri_rlmreg_p + generic map (width => ex5_fu_cr_noflush_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_fu_cr_noflush_offset to ex5_fu_cr_noflush_offset + ex5_fu_cr_noflush_q'length-1), + scout => sov(ex5_fu_cr_noflush_offset to ex5_fu_cr_noflush_offset + ex5_fu_cr_noflush_q'length-1), + din => fu_xu_ex4_cr_noflush , + dout => ex5_fu_cr_noflush_q); +ex5_fu_cr_val_latch : tri_rlmreg_p + generic map (width => ex5_fu_cr_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_fu_cr_val_offset to ex5_fu_cr_val_offset + ex5_fu_cr_val_q'length-1), + scout => sov(ex5_fu_cr_val_offset to ex5_fu_cr_val_offset + ex5_fu_cr_val_q'length-1), + din => fu_xu_ex4_cr_val , + dout => ex5_fu_cr_val_q); +ex5_is_eratsxr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_is_eratsxr_offset), + scout => sov(ex5_is_eratsxr_offset), + din => dec_byp_ex4_is_eratsxr , + dout => ex5_is_eratsxr_q); +ex5_mfdp_cr_status_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_mfdp_cr_status_offset), + scout => sov(ex5_mfdp_cr_status_offset), + din => lsu_xu_ex4_mfdp_cr_status , + dout => ex5_mfdp_cr_status_q); +ex5_mfdp_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_mfdp_val_offset), + scout => sov(ex5_mfdp_val_offset), + din => dec_byp_ex4_mfdp_val , + dout => ex5_mfdp_val_q); +ex5_mtdp_cr_status_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_mtdp_cr_status_offset), + scout => sov(ex5_mtdp_cr_status_offset), + din => lsu_xu_ex4_mtdp_cr_status , + dout => ex5_mtdp_cr_status_q); +ex5_mtdp_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_mtdp_val_offset), + scout => sov(ex5_mtdp_val_offset), + din => dec_byp_ex4_mtdp_val , + dout => ex5_mtdp_val_q); +ex5_val_latch : tri_rlmreg_p + generic map (width => ex5_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_val_offset to ex5_val_offset + ex5_val_q'length-1), + scout => sov(ex5_val_offset to ex5_val_offset + ex5_val_q'length-1), + din => ex4_val, + dout => ex5_val_q); +ex5_watch_we_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_watch_we_offset), + scout => sov(ex5_watch_we_offset), + din => ex5_watch_we_d, + dout => ex5_watch_we_q); +ex5_wchkall_fld_latch : tri_rlmreg_p + generic map (width => ex5_wchkall_fld_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_wchkall_fld_offset to ex5_wchkall_fld_offset + ex5_wchkall_fld_q'length-1), + scout => sov(ex5_wchkall_fld_offset to ex5_wchkall_fld_offset + ex5_wchkall_fld_q'length-1), + din => ex5_wchkall_fld_d, + dout => ex5_wchkall_fld_q); +an_ac_back_inv_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(an_ac_back_inv_offset), + scout => sov(an_ac_back_inv_offset), + din => an_ac_back_inv , + dout => an_ac_back_inv_q); +an_ac_back_inv_addr_latch : tri_rlmreg_p + generic map (width => an_ac_back_inv_addr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(an_ac_back_inv_addr_offset to an_ac_back_inv_addr_offset + an_ac_back_inv_addr_q'length-1), + scout => sov(an_ac_back_inv_addr_offset to an_ac_back_inv_addr_offset + an_ac_back_inv_addr_q'length-1), + din => an_ac_back_inv_addr , + dout => an_ac_back_inv_addr_q); +an_ac_back_inv_target_bit3_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(an_ac_back_inv_target_bit3_offset), + scout => sov(an_ac_back_inv_target_bit3_offset), + din => an_ac_back_inv_target_bit3 , + dout => an_ac_back_inv_target_bit3_q); +back_inv_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(back_inv_val_offset), + scout => sov(back_inv_val_offset), + din => back_inv_val_d, + dout => back_inv_val_q); +cr_barrier_we_latch : tri_rlmreg_p + generic map (width => cr_barrier_we_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(cr_barrier_we_offset to cr_barrier_we_offset + cr_barrier_we_q'length-1), + scout => sov(cr_barrier_we_offset to cr_barrier_we_offset + cr_barrier_we_q'length-1), + din => cr_barrier_we_d, + dout => cr_barrier_we_q); +exx_act_latch : tri_rlmreg_p + generic map (width => exx_act_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(exx_act_offset to exx_act_offset + exx_act_q'length-1), + scout => sov(exx_act_offset to exx_act_offset + exx_act_q'length-1), + din => exx_act_d, + dout => exx_act_q); +mmu_cr0_eq_latch : tri_rlmreg_p + generic map (width => mmu_cr0_eq_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(mmu_cr0_eq_offset to mmu_cr0_eq_offset + mmu_cr0_eq_q'length-1), + scout => sov(mmu_cr0_eq_offset to mmu_cr0_eq_offset + mmu_cr0_eq_q'length-1), + din => mm_xu_cr0_eq , + dout => mmu_cr0_eq_q); +mmu_cr0_eq_valid_latch : tri_rlmreg_p + generic map (width => mmu_cr0_eq_valid_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(mmu_cr0_eq_valid_offset to mmu_cr0_eq_valid_offset + mmu_cr0_eq_valid_q'length-1), + scout => sov(mmu_cr0_eq_valid_offset to mmu_cr0_eq_valid_offset + mmu_cr0_eq_valid_q'length-1), + din => mm_xu_cr0_eq_valid , + dout => mmu_cr0_eq_valid_q); +stcx_complete_latch : tri_rlmreg_p + generic map (width => stcx_complete_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(stcx_complete_offset to stcx_complete_offset + stcx_complete_q'length-1), + scout => sov(stcx_complete_offset to stcx_complete_offset + stcx_complete_q'length-1), + din => an_ac_stcx_complete , + dout => stcx_complete_q); +stcx_pass_latch : tri_rlmreg_p + generic map (width => stcx_pass_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(stcx_pass_offset to stcx_pass_offset + stcx_pass_q'length-1), + scout => sov(stcx_pass_offset to stcx_pass_offset + stcx_pass_q'length-1), + din => an_ac_stcx_pass , + dout => stcx_pass_q); +ex1_cr0_byp_pri_dbg_latch : tri_rlmreg_p + generic map (width => ex1_cr0_byp_pri_dbg_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_cr0_byp_pri_dbg_offset to ex1_cr0_byp_pri_dbg_offset + ex1_cr0_byp_pri_dbg_q'length-1), + scout => sov(ex1_cr0_byp_pri_dbg_offset to ex1_cr0_byp_pri_dbg_offset + ex1_cr0_byp_pri_dbg_q'length-1), + din => rf1_cr0_byp_pri , + dout => ex1_cr0_byp_pri_dbg_q); +ex1_cr1_byp_pri_dbg_latch : tri_rlmreg_p + generic map (width => ex1_cr1_byp_pri_dbg_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_cr1_byp_pri_dbg_offset to ex1_cr1_byp_pri_dbg_offset + ex1_cr1_byp_pri_dbg_q'length-1), + scout => sov(ex1_cr1_byp_pri_dbg_offset to ex1_cr1_byp_pri_dbg_offset + ex1_cr1_byp_pri_dbg_q'length-1), + din => rf1_cr1_byp_pri , + dout => ex1_cr1_byp_pri_dbg_q); +ex1_crt_byp_pri_dbg_latch : tri_rlmreg_p + generic map (width => ex1_crt_byp_pri_dbg_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_crt_byp_pri_dbg_offset to ex1_crt_byp_pri_dbg_offset + ex1_crt_byp_pri_dbg_q'length-1), + scout => sov(ex1_crt_byp_pri_dbg_offset to ex1_crt_byp_pri_dbg_offset + ex1_crt_byp_pri_dbg_q'length-1), + din => rf1_crt_byp_pri , + dout => ex1_crt_byp_pri_dbg_q); +ex6_val_dbg_latch : tri_rlmreg_p + generic map (width => ex6_val_dbg_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_val_dbg_offset to ex6_val_dbg_offset + ex6_val_dbg_q'length-1), + scout => sov(ex6_val_dbg_offset to ex6_val_dbg_offset + ex6_val_dbg_q'length-1), + din => ex5_val , + dout => ex6_val_dbg_q); + +siv(0 to siv'right) <= sov(1 to siv'right) & scan_in; +scan_out <= sov(0); + + +end architecture xuq_byp_cr; diff --git a/rel/src/vhdl/work/xuq_byp_gpr.vhdl b/rel/src/vhdl/work/xuq_byp_gpr.vhdl new file mode 100644 index 0000000..974612b --- /dev/null +++ b/rel/src/vhdl/work/xuq_byp_gpr.vhdl @@ -0,0 +1,1662 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XU Bypass Unit +-- +library ieee,ibm,support,tri; +use ieee.std_logic_1164.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use tri.tri_latches_pkg.all; +use support.power_logic_pkg.all; +use work.xuq_pkg.all; + +entity xuq_byp_gpr is +generic ( + threads : integer := 4; + expand_type : integer := 2; + regsize : integer := 64; + eff_ifar : integer := 62); +port ( + nclk : in clk_logic; + vdd : inout power_logic; + gnd : inout power_logic; + d_mode_dc : in std_ulogic; + delay_lclkr_dc : in std_ulogic; + mpw1_dc_b : in std_ulogic; + mpw2_dc_b : in std_ulogic; + func_sl_force : in std_ulogic; + func_sl_thold_0_b : in std_ulogic; + func_slp_sl_force : in std_ulogic; + func_slp_sl_thold_0_b : in std_ulogic; + func_nsl_force : in std_ulogic; + func_nsl_thold_0_b : in std_ulogic; + sg_0 : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + dec_byp_ex3_instr_trace_val : in std_ulogic; + dec_byp_ex3_instr_trace_gate : in std_ulogic; + pc_xu_trace_bus_enable : in std_ulogic; + trace_bus_enable : out std_ulogic; + + --<> + dec_rf1_tid : in std_ulogic_vector(0 to threads-1); + dec_ex2_tid : in std_ulogic_vector(0 to threads-1); + dec_byp_rf0_act : in std_ulogic; + + -- Bypass Selects + dec_byp_rf1_rs0_sel : in std_ulogic_vector(1 to 9); + dec_byp_rf1_rs1_sel : in std_ulogic_vector(1 to 10); + dec_byp_rf1_rs2_sel : in std_ulogic_vector(1 to 9); + + -- Result Selects + dec_alu_rf1_sel : in std_ulogic_vector(2 to 2); + fxa_fxb_rf0_is_mfocrf : in std_ulogic; + dec_byp_ex1_spr_sel : in std_ulogic; + alu_ex2_div_done : in std_ulogic; + dec_byp_ex3_tlb_sel : in std_ulogic_vector(0 to 1); + alu_ex4_mul_done : in std_ulogic; + dec_byp_ex4_is_mfcr : in std_ulogic; + spr_byp_ex4_is_mfxer : in std_ulogic_vector(0 to 3); + lsu_xu_ex5_wren : in std_ulogic; + + -- Slow SPR Bus + slowspr_val_in : in std_ulogic; + slowspr_rw_in : in std_ulogic; + slowspr_addr_in : in std_ulogic_vector(0 to 9); + slowspr_etid_in : in std_ulogic_vector(0 to 1); + slowspr_done_in : in std_ulogic; + + -- DCR Bus + dec_byp_ex4_dcr_ack : in std_ulogic; + an_ac_dcr_act : in std_ulogic; + an_ac_dcr_read : in std_ulogic; + an_ac_dcr_etid : in std_ulogic_vector(0 to 1); + an_ac_dcr_done : in std_ulogic; + + -- SPR/DCR Done + xu_iu_slowspr_done : out std_ulogic_vector(0 to 3); + mux_cpl_slowspr_done : out std_ulogic_vector(0 to 3); + mux_cpl_slowspr_flush : out std_ulogic_vector(0 to threads-1); + + + -- Source Data + dec_byp_rf1_imm : in std_ulogic_vector(64-regsize to 63); + fxa_fxb_rf1_do0 : in std_ulogic_vector(64-regsize to 63); + fxa_fxb_rf1_do1 : in std_ulogic_vector(64-regsize to 63); + fxa_fxb_rf1_do2 : in std_ulogic_vector(64-regsize to 63); + + -- Result Busses + alu_byp_ex1_log_rt : in std_ulogic_vector(64-regsize to 63); -- ALU Logicals + alu_byp_ex2_rt : in std_ulogic_vector(64-regsize to 63); -- ALU + alu_byp_ex3_div_rt : in std_ulogic_vector(64-regsize to 63); -- Divide + cpl_byp_ex3_spr_rt : in std_ulogic_vector(64-regsize to 63); -- CPL SPR + spr_byp_ex3_spr_rt : in std_ulogic_vector(64-regsize to 63); -- SPR + fspr_byp_ex3_spr_rt : in std_ulogic_vector(64-regsize to 63); -- FXU SPR + lsu_xu_ex4_tlb_data : in std_ulogic_vector(64-regsize to 63); -- D-ERAT + iu_xu_ex4_tlb_data : in std_ulogic_vector(64-regsize to 63); -- I-ERAT + alu_byp_ex5_mul_rt : in std_ulogic_vector(64-regsize to 63); -- Multiply + lsu_xu_rot_ex6_data_b : in std_ulogic_vector(64-regsize to 63); -- Load/Store Hit + lsu_xu_rot_rel_data : in std_ulogic_vector(64-regsize to 63); -- Load/Store Miss + slowspr_data_in : in std_ulogic_vector(64-regsize to 63); -- Slow SPR + an_ac_dcr_data : in std_ulogic_vector(64-regsize to 63); -- DCR + + byp_ex5_cr_rt : in std_ulogic_vector(32 to 63); + byp_ex5_xer_rt : in std_ulogic_vector(54 to 63); + ex1_mfocrf_rt : in std_ulogic_vector(64-regsize to 63); + + -- Target Data + byp_alu_ex1_rs0 : out std_ulogic_vector(64-regsize to 63); + byp_alu_ex1_rs1 : out std_ulogic_vector(64-regsize to 63); + byp_alu_ex1_mulsrc_0 : out std_ulogic_vector(64-regsize to 63); + byp_alu_ex1_mulsrc_1 : out std_ulogic_vector(64-regsize to 63); + byp_alu_ex1_divsrc_0 : out std_ulogic_vector(64-regsize to 63); + byp_alu_ex1_divsrc_1 : out std_ulogic_vector(64-regsize to 63); + xu_lsu_ex1_add_src0 : out std_ulogic_vector(64-regsize to 63); + xu_lsu_ex1_add_src1 : out std_ulogic_vector(64-regsize to 63); + + -- Other Outputs + xu_ex1_rs_is : out std_ulogic_vector(0 to 8); + xu_ex1_ra_entry : out std_ulogic_vector(7 to 11); + xu_ex1_rb : out std_ulogic_vector(64-regsize to 51); + xu_ex4_rs_data : out std_ulogic_vector(64-regsize to 63); -- TLB Write Data + xu_mm_derat_epn : out std_ulogic_vector(62-eff_ifar to 51); -- DERAT EPN + xu_pc_ram_data : out std_ulogic_vector(64-regsize to 63); -- RAM Result Capture + mux_spr_ex6_rt : out std_ulogic_vector(64-regsize to 63); -- SPR Write Data + + -- SPR Inputs + spr_msr_cm : in std_ulogic_vector(0 to threads-1); + + -- GPR Bypass + mux_cpl_ex4_rt : out std_ulogic_vector(64-regsize to 63); + byp_ex5_mtcrxer : out std_ulogic_vector(32 to 63); + byp_ex5_tlb_rt : out std_ulogic_vector(51 to 51); + byp_spr_ex6_rt : out std_ulogic_vector(64-regsize to 63); + xu_lsu_ex1_store_data : out std_ulogic_vector(64-regsize to 63); + fxu_spr_ex1_rs2 : out std_ulogic_vector(42 to 55); + fxu_spr_ex1_rs1 : out std_ulogic_vector(54 to 63); + fxu_spr_ex1_rs0 : out std_ulogic_vector(52 to 63); + fxb_fxa_ex7_wd0 : out std_ulogic_vector(64-regsize to 63); + + byp_grp0_debug : out std_ulogic_vector( 0 to 87); + byp_grp1_debug : out std_ulogic_vector( 0 to 87); + byp_grp2_debug : out std_ulogic_vector( 0 to 87); + byp_grp3_debug : out std_ulogic_vector(15 to 87); + byp_grp4_debug : out std_ulogic_vector(14 to 87); + byp_grp5_debug : out std_ulogic_vector(15 to 87) + ); + +-- synopsys translate_off +-- synopsys translate_on +end xuq_byp_gpr; +architecture xuq_byp_gpr of xuq_byp_gpr is + +-- Latches Placed latches must have unique acts +signal exx_act_q, exx_act_d : std_ulogic_vector(0 to 6); -- act=>tiup +signal rf1_act_q : std_ulogic; -- input=>dec_byp_rf0_act act=>tiup, sleep=>Y +signal rf1_is_mfocrf_q : std_ulogic; -- input=> fxa_fxb_rf0_is_mfocrf, act => tiup +signal ex1_rs0_u_b_q, rf1_rs0_u : std_ulogic_vector(64-regsize to 63); -- act=>rf1_act_q +signal ex1_rs0_l_b_q, rf1_rs0_l : std_ulogic_vector(64-regsize to 63); -- act=>rf1_act_q +signal ex1_rs1_u_b_q, rf1_rs1_u : std_ulogic_vector(64-regsize to 63); -- act=>rf1_act_q +signal ex1_rs1_l_b_q, rf1_rs1_l : std_ulogic_vector(64-regsize to 63); -- act=>rf1_act_q +signal ex1_rs1_nimm_b_q, rf1_rs1_nimm : std_ulogic_vector(59 to 63); -- act=>exx_act(0) +signal ex1_rs2_q, rf1_rs2 : std_ulogic_vector(64-regsize to 63); -- act=>exx_act(0) +signal ex1_do2_q : std_ulogic_vector(64-regsize to 63); -- input=>fxa_fxb_rf1_do2, act=>exx_act(0) +signal ex1_rs2_gpr_sel_q, ex1_rs2_gpr_sel_d : std_ulogic_vector(0 to regsize/8-1); -- act=>exx_act(0) +signal ex1_rs2_rot_sel_q, ex1_rs2_rot_sel_d : std_ulogic_vector(0 to regsize/8-1); -- act=>exx_act(0) +signal ex1_log_sel_q : std_ulogic; -- input=>dec_alu_rf1_sel(2), act=>exx_act(0) +signal ex1_msr_cm_q, rf1_msr_cm : std_ulogic_vector(0 to 3); -- input=>rf1_msr_cm, act=>exx_act(0) +signal ex2_rt_sel_q, ex1_rt_sel : std_ulogic_vector(0 to regsize/8-1); -- act=>exx_act(1), scan=>N +signal ex2_rt_q, ex1_rt : std_ulogic_vector(64-regsize to 63); -- act=>exx_act(1), scan=>N +signal ex3_rt_q, ex2_rt : std_ulogic_vector(64-regsize to 63); -- act=>exx_act(2) +signal ex4_rt_q, ex3_rt : std_ulogic_vector(64-regsize to 63); -- act=>exx_act(3), scan=>N +signal ex5_rt_q, ex4_rt : std_ulogic_vector(64-regsize to 63); -- act=>exx_act(4) +signal ex6_rt_q, ex5_rt : std_ulogic_vector(64-regsize to 63); -- act=>exx_act(5), scan=>N +signal ex7_rt_q, ex7_rt_q_b, ex6_rt : std_ulogic_vector(64-regsize to 63); -- act=>exx_act(6) +signal ex7_rot_rt_q, ex6_rot_rtu_b : std_ulogic_vector(64-regsize to 63); -- act=>exx_act(6) +signal ex1_is_mfocrf_q, ex1_is_mfocrf_d : std_ulogic_vector(0 to regsize/8-1); -- act=>exx_act(0) +signal ex2_spr_sel_q : std_ulogic; -- input=>dec_byp_ex1_spr_sel, act=>exx_act(1) +signal ex3_spr_sel_q : std_ulogic; -- input=>ex2_spr_sel_q, act=>exx_act(2) +signal ex3_div_done_q, ex3_div_done_d : std_ulogic_vector(0 to regsize/8-1); -- act=>exx_act(2) +signal ex4_spr_sel_q, ex4_spr_sel_d : std_ulogic_vector(0 to regsize/8-1); -- act=>exx_act(3), scan=>N +signal ex4_spr_rt_q, ex4_spr_rt_d : std_ulogic_vector(64-regsize to 63); -- act=>exx_act(3), scan=>N +signal ex4_tlb_sel_q : std_ulogic_vector(0 to 1); -- input=>dec_byp_ex3_tlb_sel act=>exx_act(3), scan=>N +signal ex5_is_mfxer_q, ex5_is_mfxer_d : std_ulogic_vector(0 to regsize/8-1); -- act=>exx_act(4) +signal ex5_is_mfcr_q, ex5_is_mfcr_d : std_ulogic_vector(0 to regsize/8-1); -- act=>exx_act(4) +signal ex5_mul_done_q, ex5_mul_done_d : std_ulogic_vector(0 to regsize/8-1); -- act=>exx_act(4) +signal ex5_dtlb_sel_q, ex5_dtlb_sel_d : std_ulogic_vector(0 to regsize/8-1); -- act=>exx_act(4) +signal ex5_itlb_sel_q, ex5_itlb_sel_d : std_ulogic_vector(0 to regsize/8-1); -- act=>exx_act(4) +signal ex5_tlb_data_iu_q : std_ulogic_vector(64-regsize to 63); -- input=>iu_xu_ex4_tlb_data act=>exx_act(4) +signal ex5_tlb_data_lsu_q : std_ulogic_vector(64-regsize to 63); -- input=>lsu_xu_ex4_tlb_data act=>exx_act(4) +signal ex5_slowspr_sel_q, ex5_slowspr_sel_d : std_ulogic_vector(0 to regsize/8-1); -- act=>ex4_slowspr_act +signal ex5_ones_sel_q, ex5_ones_sel_d : std_ulogic_vector(0 to regsize/8-1); -- act=>ex4_slowspr_act +signal ex5_slowspr_val_q : std_ulogic; -- input=>slowspr_val_in act=>tiup +signal ex5_slowspr_data_q : std_ulogic_vector(64-regsize to 63); -- input=>slowspr_data_in act=>ex4_slowspr_act +signal ex5_slowspr_tid_q, ex5_slowspr_tid_d : std_ulogic_vector(0 to 3); -- act=>ex4_slowspr_act +signal ex5_slowspr_addr_q : std_ulogic_vector(0 to 9); -- input=>slowspr_addr_in, act=>ex4_slowspr_act +signal ex5_slowspr_wr_val_q,ex5_slowspr_wr_val_d : std_ulogic; -- act=>tiup +signal ex6_slowspr_flush_q,ex6_slowspr_flush_d : std_ulogic_vector(0 to threads-1); -- act=>tiup +signal ex4_dcr_act_q : std_ulogic; -- input=>an_ac_dcr_act, act=>tiup +signal ex5_dcr_sel_q, ex5_dcr_sel_d : std_ulogic_vector(0 to regsize/8-1); -- act=>exx_act(4) +signal ex5_dcr_ack_q : std_ulogic; -- input=>dec_byp_ex4_dcr_ack act=>tiup +signal ex5_dcr_data_q : std_ulogic_vector(64-regsize to 63); -- input=>an_ac_dcr_data, act=>ex4_dcr_act_q +signal ex5_dcr_tid_q, ex5_dcr_tid_d : std_ulogic_vector(0 to 3); -- act=>ex4_dcr_act_q +signal ex6_lsu_wren_q, ex6_lsu_wren_d : std_ulogic_vector(0 to regsize/8); -- act=>exx_act(5), scan=>N +signal ex3_derat_epn_q, ex3_derat_epn_d : std_ulogic_vector(62-eff_ifar to 51); -- act=>exx_act(2) +signal spr_msr_cm_q : std_ulogic_vector(0 to threads-1); -- input=>spr_msr_cm act=>tiup +signal trace_bus_enable_q : std_ulogic; -- input=>pc_xu_trace_bus_enable, sleep=>Y, needs_sreset=>0 +signal ex4_instr_trace_val_q : std_ulogic; -- input=>dec_byp_ex3_instr_trace_val,act=>trace_bus_enable_q, sleep=>Y, needs_sreset=>0 +signal ex5_instr_trace_val_q : std_ulogic; -- input=>ex4_instr_trace_val_q, act=>trace_bus_enable_q, sleep=>Y, needs_sreset=>0 +signal ex4_instr_trace_gate_q : std_ulogic; -- input=>dec_byp_ex3_instr_trace_gate,act=>trace_bus_enable_q, sleep=>Y, needs_sreset=>0 +signal ex5_instr_trace_gate_q, ex5_instr_trace_gate_d : std_ulogic_vector(0 to 3); -- input=>ex5_instr_trace_gate_d, act=>trace_bus_enable_q, sleep=>Y, needs_sreset=>0 +signal ex1_rs0_sel_dbg_q : std_ulogic_vector(1 to 9); -- input=>dec_byp_rf1_rs0_sel, act=>trace_bus_enable_q, sleep=>Y, needs_sreset=>0 +signal ex1_rs1_sel_dbg_q : std_ulogic_vector(1 to 10); -- input=>dec_byp_rf1_rs1_sel, act=>trace_bus_enable_q, sleep=>Y, needs_sreset=>0 +signal ex1_rs2_sel_dbg_q : std_ulogic_vector(1 to 9); -- input=>dec_byp_rf1_rs2_sel, act=>trace_bus_enable_q, sleep=>Y, needs_sreset=>0 +signal spare_0_q, spare_0_d : std_ulogic_vector(0 to 15); -- input=>spare_0_d, act=>tiup, +signal spare_1_q, spare_1_d : std_ulogic_vector(0 to 15); -- input=>spare_1_d, act=>tiup, +signal spare_2_q, spare_2_d : std_ulogic_vector(0 to 15); -- input=>spare_2_d, act=>tiup, +signal spare_3_q, spare_3_d : std_ulogic_vector(0 to 15); -- input=>spare_3_d, act=>tiup, +signal spare_4_q, spare_4_d : std_ulogic_vector(0 to 15); -- input=>spare_4_d, act=>tiup, + +-- Scanchains +constant exx_act_offset : integer := 0; +constant rf1_act_offset : integer := exx_act_offset + exx_act_q'length; +constant rf1_is_mfocrf_offset : integer := rf1_act_offset + 1; +constant ex1_rs0_u_b_offset : integer := rf1_is_mfocrf_offset + 1; +constant ex1_rs0_l_b_offset : integer := ex1_rs0_u_b_offset + ex1_rs0_u_b_q'length; +constant ex1_rs1_u_b_offset : integer := ex1_rs0_l_b_offset + ex1_rs0_l_b_q'length; +constant ex1_rs1_l_b_offset : integer := ex1_rs1_u_b_offset + ex1_rs1_u_b_q'length; +constant ex1_rs1_nimm_b_offset : integer := ex1_rs1_l_b_offset + ex1_rs1_l_b_q'length; +constant ex1_rs2_offset : integer := ex1_rs1_nimm_b_offset + ex1_rs1_nimm_b_q'length; +constant ex1_do2_offset : integer := ex1_rs2_offset + ex1_rs2_q'length; +constant ex1_rs2_gpr_sel_offset : integer := ex1_do2_offset + ex1_do2_q'length; +constant ex1_rs2_rot_sel_offset : integer := ex1_rs2_gpr_sel_offset + ex1_rs2_gpr_sel_q'length; +constant ex1_log_sel_offset : integer := ex1_rs2_rot_sel_offset + ex1_rs2_rot_sel_q'length; +constant ex1_msr_cm_offset : integer := ex1_log_sel_offset + 1; +constant ex3_rt_offset : integer := ex1_msr_cm_offset + ex1_msr_cm_q'length; +constant ex5_rt_offset : integer := ex3_rt_offset + ex3_rt_q'length; +constant ex7_rt_offset : integer := ex5_rt_offset + ex5_rt_q'length; +constant ex7_rot_rt_offset : integer := ex7_rt_offset + ex7_rt_q'length; +constant ex1_is_mfocrf_offset : integer := ex7_rot_rt_offset + ex7_rot_rt_q'length; +constant ex2_spr_sel_offset : integer := ex1_is_mfocrf_offset + ex1_is_mfocrf_q'length; +constant ex3_spr_sel_offset : integer := ex2_spr_sel_offset + 1; +constant ex3_div_done_offset : integer := ex3_spr_sel_offset + 1; +constant ex5_is_mfxer_offset : integer := ex3_div_done_offset + ex3_div_done_q'length; +constant ex5_is_mfcr_offset : integer := ex5_is_mfxer_offset + ex5_is_mfxer_q'length; +constant ex5_mul_done_offset : integer := ex5_is_mfcr_offset + ex5_is_mfcr_q'length; +constant ex5_dtlb_sel_offset : integer := ex5_mul_done_offset + ex5_mul_done_q'length; +constant ex5_itlb_sel_offset : integer := ex5_dtlb_sel_offset + ex5_dtlb_sel_q'length; +constant ex5_tlb_data_iu_offset : integer := ex5_itlb_sel_offset + ex5_itlb_sel_q'length; +constant ex5_tlb_data_lsu_offset : integer := ex5_tlb_data_iu_offset + ex5_tlb_data_iu_q'length; +constant ex5_slowspr_sel_offset : integer := ex5_tlb_data_lsu_offset + ex5_tlb_data_lsu_q'length; +constant ex5_ones_sel_offset : integer := ex5_slowspr_sel_offset + ex5_slowspr_sel_q'length; +constant ex5_slowspr_val_offset : integer := ex5_ones_sel_offset + ex5_ones_sel_q'length; +constant ex5_slowspr_data_offset : integer := ex5_slowspr_val_offset + 1; +constant ex5_slowspr_tid_offset : integer := ex5_slowspr_data_offset + ex5_slowspr_data_q'length; +constant ex5_slowspr_addr_offset : integer := ex5_slowspr_tid_offset + ex5_slowspr_tid_q'length; +constant ex5_slowspr_wr_val_offset : integer := ex5_slowspr_addr_offset + ex5_slowspr_addr_q'length; +constant ex6_slowspr_flush_offset : integer := ex5_slowspr_wr_val_offset + 1; +constant ex4_dcr_act_offset : integer := ex6_slowspr_flush_offset + ex6_slowspr_flush_q'length; +constant ex5_dcr_sel_offset : integer := ex4_dcr_act_offset + 1; +constant ex5_dcr_ack_offset : integer := ex5_dcr_sel_offset + ex5_dcr_sel_q'length; +constant ex5_dcr_data_offset : integer := ex5_dcr_ack_offset + 1; +constant ex5_dcr_tid_offset : integer := ex5_dcr_data_offset + ex5_dcr_data_q'length; +constant ex3_derat_epn_offset : integer := ex5_dcr_tid_offset + ex5_dcr_tid_q'length; +constant spr_msr_cm_offset : integer := ex3_derat_epn_offset + ex3_derat_epn_q'length; +constant trace_bus_enable_offset : integer := spr_msr_cm_offset + spr_msr_cm_q'length; +constant ex4_instr_trace_val_offset : integer := trace_bus_enable_offset + 1; +constant ex5_instr_trace_val_offset : integer := ex4_instr_trace_val_offset + 1; +constant ex4_instr_trace_gate_offset : integer := ex5_instr_trace_val_offset + 1; +constant ex5_instr_trace_gate_offset : integer := ex4_instr_trace_gate_offset + 1; +constant ex1_rs0_sel_dbg_offset : integer := ex5_instr_trace_gate_offset + ex5_instr_trace_gate_q'length; +constant ex1_rs1_sel_dbg_offset : integer := ex1_rs0_sel_dbg_offset + ex1_rs0_sel_dbg_q'length; +constant ex1_rs2_sel_dbg_offset : integer := ex1_rs1_sel_dbg_offset + ex1_rs1_sel_dbg_q'length; +constant spare_0_offset : integer := ex1_rs2_sel_dbg_offset + ex1_rs2_sel_dbg_q'length; +constant spare_1_offset : integer := spare_0_offset + spare_0_q'length; +constant spare_2_offset : integer := spare_1_offset + spare_1_q'length; +constant spare_3_offset : integer := spare_2_offset + spare_2_q'length; +constant spare_4_offset : integer := spare_3_offset + spare_3_q'length; +constant scan_right : integer := spare_4_offset + spare_4_q'length; + +signal siv : std_ulogic_vector(0 to scan_right-1); +signal sov : std_ulogic_vector(0 to scan_right-1); +-- Signals +signal tiup : std_ulogic; +signal tidn : std_ulogic_vector(0 to 63); +signal spare_0_lclk : clk_logic; +signal spare_1_lclk : clk_logic; +signal spare_2_lclk : clk_logic; +signal spare_3_lclk : clk_logic; +signal spare_4_lclk : clk_logic; +signal spare_0_d1clk, spare_0_d2clk : std_ulogic; +signal spare_1_d1clk, spare_1_d2clk : std_ulogic; +signal spare_2_d1clk, spare_2_d2clk : std_ulogic; +signal spare_3_d1clk, spare_3_d2clk : std_ulogic; +signal spare_4_d1clk, spare_4_d2clk : std_ulogic; +signal ex1x_d1clk, ex1x_d2clk :std_ulogic ; +signal ex1x_lclk :clk_logic ; +signal ex1_d1clk, ex1_d2clk :std_ulogic ; +signal ex1_lclk :clk_logic ; +signal ex1_slp_d1clk, ex1_slp_d2clk :std_ulogic ; +signal ex1_slp_lclk :clk_logic ; +signal ex7_d1clk, ex7_d2clk :std_ulogic ; +signal ex7_lclk :clk_logic ; +signal exx_act : std_ulogic_vector(0 to 6); +signal rf1_rot_rs0_sel_b : std_ulogic_vector(64-regsize to 63); +signal rf1_rot_rs1_sel_b : std_ulogic_vector(64-regsize to 63); +signal rf1_rot_nimm_rs1_sel_b : std_ulogic_vector(59 to 63); +signal rf1_oth_rs0, rf1_oth_rs0_b : std_ulogic_vector(64-regsize to 63); +signal rf1_oth_rs1, rf1_oth_rs1_b : std_ulogic_vector(64-regsize to 63); +signal rf1_nlsu_rs0, rf1_nlsu_rs0_b : std_ulogic_vector(64-regsize to 63); +signal rf1_nlsu_rs1, rf1_nlsu_rs1_b : std_ulogic_vector(64-regsize to 63); +signal rf1_nimm_rs1, rf1_nimm_rs1_b : std_ulogic_vector(59 to 63); +signal rf1_gpr_rs0_b : std_ulogic_vector(64-regsize to 63); +signal rf1_gpr_rs1_b : std_ulogic_vector(64-regsize to 63); +signal rf1_imm_rs1_b : std_ulogic_vector(64-regsize to 63); +signal rf1_gpr_nimm_rs1_b, rf1_oth_nimm_rs1_b : std_ulogic_vector(59 to 63); +signal ex1_lsu_src0_i1 : std_ulogic_vector(64-regsize to 63); +signal ex1_lsu_src1_i1 : std_ulogic_vector(64-regsize to 63); +signal ex1_lsu_src0_i1_b : std_ulogic_vector(64-regsize to 63); +signal ex1_lsu_src1_i1_b : std_ulogic_vector(64-regsize to 63); +signal ex6_rot_rtl_b , ex6_rot_rt : std_ulogic_vector(64-regsize to 63); +signal ex1_rs2 : std_ulogic_vector(64-regsize to 63); +signal ex4_ones_sel : std_ulogic; +signal ex4_slowspr_sel : std_ulogic; +signal ex4_dcr_sel : std_ulogic; +signal ex5_rt_sel, ex5_nospr_rt_sel : std_ulogic_vector(0 to regsize/8-1); +signal ex5_tlb_rt : std_ulogic_vector(64-regsize to 63); +signal ex5_spr_rt, ex5_nospr_rt : std_ulogic_vector(64-regsize to 63); +signal ex5_cr : std_ulogic_vector(64-regsize to 64); +signal ex5_xer : std_ulogic_vector(64-regsize to 64); +signal ex6_xu_rt, ex6_xu_rt_b : std_ulogic_vector(64-regsize to 63); +signal ex6_lsu_wren_b : std_ulogic_vector(64-regsize to 63); +signal ex5_slowop_done : std_ulogic_vector(0 to 3); +signal ex2_msr_cm : std_ulogic; +signal byp_rs0_debug, byp_rs1_debug, byp_rs2_debug : std_ulogic_vector(0 to 63); +signal byp_gpr_sel_debug : std_ulogic_vector(0 to 19); +signal dec_ex2_tid_int : std_ulogic_vector(0 to threads-1); +signal ex4_slowspr_act : std_ulogic; +signal ex5_slowspr_csync : std_ulogic; +signal ex5_rt_gated : std_ulogic_vector(64-regsize to 63); + + +begin + + +tiup <= '1'; +tidn <= (others=>'0'); + +exx_act_d <= dec_byp_rf0_act & exx_act(0 to 5); + +exx_act(0) <= exx_act_q(0); +exx_act(1) <= exx_act_q(1); +exx_act(2) <= exx_act_q(2) or alu_ex2_div_done; +exx_act(3) <= exx_act_q(3); +exx_act(4) <= exx_act_q(4) or alu_ex4_mul_done or dec_byp_ex4_dcr_ack; +exx_act(5) <= exx_act_q(5) or ex5_slowspr_val_q; +exx_act(6) <= exx_act_q(6); + +ex4_slowspr_act <= '1'; + +--------------------------------------------------------------------- +-- Result Muxing +--------------------------------------------------------------------- + +ex5_cr <= tidn(0 to regsize-32) & byp_ex5_cr_rt; +ex5_xer <= tidn(0 to regsize-32) & byp_ex5_xer_rt(54 to 56) & tidn(35 to 56) & byp_ex5_xer_rt(57 to 63); + +ex4_spr_rt_d <= spr_byp_ex3_spr_rt or cpl_byp_ex3_spr_rt or fspr_byp_ex3_spr_rt; + +ex1_rt <= (ex1_mfocrf_rt and fanout(ex1_is_mfocrf_q,regsize)) or + (alu_byp_ex1_log_rt and not fanout(ex1_is_mfocrf_q,regsize)); + +ex1_rt_sel <= (0 to regsize/8-1=>ex1_log_sel_q) or ex1_is_mfocrf_q; + +ex2_rt <= (ex2_rt_q and fanout(ex2_rt_sel_q,regsize)) or + (alu_byp_ex2_rt and not fanout(ex2_rt_sel_q,regsize)); + +ex3_rt <= (alu_byp_ex3_div_rt and fanout(ex3_div_done_q,regsize)) or + (ex3_rt_q and not fanout(ex3_div_done_q,regsize)); + +ex4_rt <= (ex4_spr_rt_q and fanout(ex4_spr_sel_q, regsize)) or + (ex4_rt_q and not fanout(ex4_spr_sel_q, regsize)); + + +ex5_rt_sel <= not (ex5_dtlb_sel_q or + ex5_itlb_sel_q or + ex5_is_mfxer_q or + ex5_is_mfcr_q or + ex5_mul_done_q); + +ex5_nospr_rt_sel <= not (ex5_slowspr_sel_q or + ex5_dcr_sel_q); + +ex5_tlb_rt <= (ex5_tlb_data_lsu_q and fanout(ex5_dtlb_sel_q,regsize)) or + (ex5_tlb_data_iu_q and fanout(ex5_itlb_sel_q,regsize)); + +ex5_nospr_rt <= ex5_tlb_rt or + (ex5_xer(65-regsize to 64) and fanout(ex5_is_mfxer_q,regsize)) or + (ex5_cr(65-regsize to 64) and fanout(ex5_is_mfcr_q, regsize)) or + (alu_byp_ex5_mul_rt and fanout(ex5_mul_done_q,regsize)) or + (ex5_rt_q and fanout(ex5_rt_sel, regsize)); + +ex5_spr_rt <= (ex5_nospr_rt and fanout(ex5_nospr_rt_sel, regsize)) or + (ex5_slowspr_data_q and fanout(ex5_slowspr_sel_q,regsize)) or + (ex5_dcr_data_q and fanout(ex5_dcr_sel_q, regsize)); + +ex5_rt <= ex5_spr_rt or fanout(ex5_ones_sel_q,regsize); + +ex6_lsu_wren_b <= not fanout(ex6_lsu_wren_q(0 to 7),regsize); +ex6_xu_rt <= (ex6_rt_q and ex6_lsu_wren_b); +ex6_xu_rt_b <= not ex6_xu_rt; + +u_ex6_rt: ex6_rt <= (ex6_rot_rtu_b or ex6_lsu_wren_b) nand ex6_xu_rt_b; + +--------------------------------------------------------------------- +-- Result Outputs +--------------------------------------------------------------------- +-- CPL needs SPR read data included for rfi's +mux_cpl_ex4_rt <= ex4_rt; +byp_ex5_mtcrxer <= ex5_rt_q(32 to 63); +byp_ex5_tlb_rt <= ex5_tlb_rt(51 to 51); +byp_spr_ex6_rt <= ex6_rt_q; +fxb_fxa_ex7_wd0 <= ex7_rt_q; + +xu_pc_ram_data <= ex6_rt_q; +mux_spr_ex6_rt <= ex6_rt_q; +xu_ex4_rs_data <= ex4_rt_q; + +ex2_msr_cm <= or_reduce(spr_msr_cm_q and dec_ex2_tid); +ex3_derat_epn_d(62-eff_ifar to 31) <= gate(ex2_rt(62-eff_ifar to 31),ex2_msr_cm); +ex3_derat_epn_d(32 to 51) <= ex2_rt(32 to 51); +xu_mm_derat_epn <= ex3_derat_epn_q; + + +--------------------------------------------------------------------- +-- Slow SPR +--------------------------------------------------------------------- +with slowspr_etid_in select + ex5_slowspr_tid_d <= "1000" when "00", + "0100" when "01", + "0010" when "10", + "0001" when others; + +with an_ac_dcr_etid select + ex5_dcr_tid_d <= "1000" when "00", + "0100" when "01", + "0010" when "10", + "0001" when others; + +ex4_slowspr_sel <= slowspr_val_in and slowspr_rw_in and slowspr_done_in; +ex4_dcr_sel <= dec_byp_ex4_dcr_ack and an_ac_dcr_read and an_ac_dcr_done; + +ex4_ones_sel <=(slowspr_val_in and slowspr_rw_in and not slowspr_done_in) or + (dec_byp_ex4_dcr_ack and an_ac_dcr_read and not an_ac_dcr_done); + +ex5_slowop_done <=(ex5_slowspr_tid_q and (0 to 3=> ex5_slowspr_val_q)) or + (ex5_dcr_tid_q and (0 to 3=> ex5_dcr_ack_q)); + +ex5_slowspr_wr_val_d <= slowspr_val_in and not slowspr_rw_in and slowspr_done_in; + +ex5_slowspr_csync <=(ex5_slowspr_addr_q(0 to 9) = "1111111101") or -- 1021 MMUCR1 + (ex5_slowspr_addr_q(0 to 9) = "0000110000") or -- 48 PID + (ex5_slowspr_addr_q(0 to 9) = "0101010010"); -- 338 LPIDR + +ex6_slowspr_flush_d <= gate(ex5_slowspr_tid_q,(ex5_slowspr_wr_val_q and ex5_slowspr_csync)); + +xu_iu_slowspr_done <= ex5_slowop_done; +mux_cpl_slowspr_done <= ex5_slowop_done; +mux_cpl_slowspr_flush <= ex6_slowspr_flush_q; + +--------------------------------------------------------------------- +-- Mux Select Fanout +--------------------------------------------------------------------- +ex1_is_mfocrf_d <= (others=>rf1_is_mfocrf_q); +ex4_spr_sel_d <= (others=>ex3_spr_sel_q); +ex3_div_done_d <= (others=>alu_ex2_div_done); +ex5_dtlb_sel_d <= (others=>ex4_tlb_sel_q(0)); +ex5_itlb_sel_d <= (others=>ex4_tlb_sel_q(1)); +ex5_is_mfxer_d <= (others=>or_reduce(spr_byp_ex4_is_mfxer)); +ex5_is_mfcr_d <= (others=>dec_byp_ex4_is_mfcr); +ex5_mul_done_d <= (others=>alu_ex4_mul_done); +ex5_slowspr_sel_d <= (others=>ex4_slowspr_sel); +ex5_dcr_sel_d <= (others=>ex4_dcr_sel); +ex5_ones_sel_d <= (others=>ex4_ones_sel); +ex6_lsu_wren_d <= (others=>lsu_xu_ex5_wren); +ex5_instr_trace_gate_d <= (others=>ex4_instr_trace_gate_q); + +ex1_rs2_gpr_sel_d <= (others=>dec_byp_rf1_rs2_sel(9)); +ex1_rs2_rot_sel_d <= (others=>(ex6_lsu_wren_q(8) and dec_byp_rf1_rs2_sel(6))); + +-- rf1_rsX_byp_pri: +-- (0) Zeros +-- (1) EX1 +-- (2) EX2 +-- (3) EX3 +-- (4) EX4 +-- (5) EX5 +-- (6) EX6 +-- (7) EX7 +-- (8) Rel +-- (.) GPR/Imm +-- (.) GPR + +--------------------------------------------------------------------- +-- Source 0 +--------------------------------------------------------------------- +rf1_oth_rs0 <= gate(ex1_rt, dec_byp_rf1_rs0_sel(1)) or + gate(ex2_rt, dec_byp_rf1_rs0_sel(2)) or + gate(ex3_rt, dec_byp_rf1_rs0_sel(3)) or + gate(ex4_rt, dec_byp_rf1_rs0_sel(4)) or + gate(ex5_rt, dec_byp_rf1_rs0_sel(5)) or + gate(ex6_xu_rt, dec_byp_rf1_rs0_sel(6)) or + gate(ex7_rt_q, dec_byp_rf1_rs0_sel(7)) or + gate(lsu_xu_rot_rel_data, dec_byp_rf1_rs0_sel(8)); + +rf1_oth_rs0_b <= not rf1_oth_rs0; + +rf1_rot_rs0_sel_b <= (others=>(ex6_lsu_wren_q(8) nand dec_byp_rf1_rs0_sel(6))); + + +u_rf1_gpr_rs0_b: rf1_gpr_rs0_b <= fxa_fxb_rf1_do0 nand (0 to 63=> dec_byp_rf1_rs0_sel(9)); + +u_rf1_nlsu_rs0: rf1_nlsu_rs0 <= rf1_gpr_rs0_b nand rf1_oth_rs0_b; + +u_rf1_nlsu_rs0_b: rf1_nlsu_rs0_b <= not(rf1_nlsu_rs0); + +u_rf1_rs0_u_sel: rf1_rs0_u <= (ex6_rot_rtu_b or rf1_rot_rs0_sel_b) nand rf1_nlsu_rs0_b; +u_rf1_rs0_l_sel: rf1_rs0_l <= (ex6_rot_rtl_b or rf1_rot_rs0_sel_b) nand rf1_nlsu_rs0_b; + +--------------------------------------------------------------------- +-- Source 1 +--------------------------------------------------------------------- +rf1_oth_rs1 <= gate(ex1_rt, dec_byp_rf1_rs1_sel(1)) or + gate(ex2_rt, dec_byp_rf1_rs1_sel(2)) or + gate(ex3_rt, dec_byp_rf1_rs1_sel(3)) or + gate(ex4_rt, dec_byp_rf1_rs1_sel(4)) or + gate(ex5_rt, dec_byp_rf1_rs1_sel(5)) or + gate(ex6_xu_rt, dec_byp_rf1_rs1_sel(6)) or + gate(ex7_rt_q, dec_byp_rf1_rs1_sel(7)) or + gate(lsu_xu_rot_rel_data, dec_byp_rf1_rs1_sel(8)); + +rf1_rot_nimm_rs1_sel_b <= (others=>not((ex6_lsu_wren_q(8) and dec_byp_rf1_rs1_sel(6)))); +rf1_rot_rs1_sel_b <= (others=>not((ex6_lsu_wren_q(8) and dec_byp_rf1_rs1_sel(6) and not dec_byp_rf1_rs1_sel(10)))); + +u_rf1_oth_nimm_rs1_b: + rf1_oth_nimm_rs1_b <= not(rf1_oth_rs1(59 to 63)); +u_rf1_oth_rs1_b: rf1_oth_rs1_b <= rf1_oth_rs1 nand (0 to 63=>not(dec_byp_rf1_rs1_sel(10))); + +u_rf1_gpr_nimm_rs1_b: + rf1_gpr_nimm_rs1_b <= fxa_fxb_rf1_do1(59 to 63) nand (59 to 63=> dec_byp_rf1_rs1_sel(9)); +u_rf1_gpr_rs1_b: rf1_gpr_rs1_b <= fxa_fxb_rf1_do1 nand (0 to 63=>(dec_byp_rf1_rs1_sel(9) and not dec_byp_rf1_rs1_sel(10))); + +u_rf1_imm_rs1_b: rf1_imm_rs1_b <= dec_byp_rf1_imm nand (0 to 63=> dec_byp_rf1_rs1_sel(10)); + +u_rf1_nimm_rs1: rf1_nimm_rs1 <= not(rf1_gpr_nimm_rs1_b(59 to 63) and rf1_oth_nimm_rs1_b(59 to 63)); +u_rf1_nlsu_rs1: rf1_nlsu_rs1 <= not(rf1_gpr_rs1_b and rf1_oth_rs1_b and rf1_imm_rs1_b); + +u_rf1_nimm_rs1_b: rf1_nimm_rs1_b <= not(rf1_nimm_rs1); +u_rf1_nlsu_rs1_b: rf1_nlsu_rs1_b <= not(rf1_nlsu_rs1); + +u_rf1_rs1_u_sel: rf1_rs1_u <= (ex6_rot_rtu_b or rf1_rot_rs1_sel_b) nand rf1_nlsu_rs1_b; +u_rf1_rs1_l_sel: rf1_rs1_l <= (ex6_rot_rtl_b or rf1_rot_rs1_sel_b) nand rf1_nlsu_rs1_b; + +-- RA Entry Garbage. For eratwe, I want RS to go down the pipe, but still need RA to go to the erats. +u_rf1_rs1_nimm: rf1_rs1_nimm <= (ex6_rot_rtu_b(59 to 63) or rf1_rot_nimm_rs1_sel_b(59 to 63)) nand rf1_nimm_rs1_b(59 to 63); + +--------------------------------------------------------------------- +-- Source 2 +--------------------------------------------------------------------- +rf1_rs2 <= gate(ex1_rt, dec_byp_rf1_rs2_sel(1)) or + gate(ex2_rt, dec_byp_rf1_rs2_sel(2)) or + gate(ex3_rt, dec_byp_rf1_rs2_sel(3)) or + gate(ex4_rt, dec_byp_rf1_rs2_sel(4)) or + gate(ex5_rt, dec_byp_rf1_rs2_sel(5)) or + gate(ex6_xu_rt, dec_byp_rf1_rs2_sel(6)) or + gate(ex7_rt_q, dec_byp_rf1_rs2_sel(7)) or + gate(lsu_xu_rot_rel_data, dec_byp_rf1_rs2_sel(8)); + +ex1_rs2 <= (ex1_do2_q and fanout(ex1_rs2_gpr_sel_q,regsize)) or + (ex7_rot_rt_q and fanout(ex1_rs2_rot_sel_q,regsize)) or + ex1_rs2_q; + +--------------------------------------------------------------------- +-- Assign output +--------------------------------------------------------------------- +xu_ex1_rs_is <= ex1_rs2(55 to 63); +xu_lsu_ex1_store_data <= ex1_rs2; +fxu_spr_ex1_rs2 <= ex1_rs2(42 to 55); +xu_ex1_ra_entry <= not ex1_rs1_nimm_b_q(59 to 63); + +rf1_msr_cm <=(others=>or_reduce(spr_msr_cm_q and dec_rf1_tid)); +xu_ex1_rb(64-regsize to 31) <=(not ex1_rs1_u_b_q(64-regsize to 31)) and fanout(ex1_msr_cm_q,32); +xu_ex1_rb(32 to 51) <= not ex1_rs1_u_b_q(32 to 51); + +u_rot_rt_i1: ex6_rot_rt <= not lsu_xu_rot_ex6_data_b; +u_rot_rt_i2u: ex6_rot_rtu_b <= not ex6_rot_rt ; +u_rot_rt_i2l: ex6_rot_rtl_b <= not ex6_rot_rt ; + +u_rs0_i1: byp_alu_ex1_rs0 <= not ex1_rs0_u_b_q; +u_rs1_i1: byp_alu_ex1_rs1 <= not ex1_rs1_u_b_q; + + +u_lsu_src0_i1: ex1_lsu_src0_i1 <= not ex1_rs0_l_b_q; + xu_lsu_ex1_add_src0 <= ex1_lsu_src0_i1; +u_lsu_src0_i2: ex1_lsu_src0_i1_b <= not ex1_lsu_src0_i1; + byp_alu_ex1_mulsrc_0 <= not ex1_lsu_src0_i1_b; + byp_alu_ex1_divsrc_0 <= not ex1_lsu_src0_i1_b; + fxu_spr_ex1_rs0 <= not ex1_lsu_src0_i1_b(52 to 63); + + +u_lsu_src1_i1: ex1_lsu_src1_i1 <= not ex1_rs1_l_b_q; + xu_lsu_ex1_add_src1 <= ex1_lsu_src1_i1; +u_lsu_src1_i2: ex1_lsu_src1_i1_b <= not ex1_lsu_src1_i1; + byp_alu_ex1_mulsrc_1 <= not ex1_lsu_src1_i1_b; + byp_alu_ex1_divsrc_1 <= not ex1_lsu_src1_i1_b; + fxu_spr_ex1_rs1 <= not ex1_lsu_src1_i1_b(54 to 63); + +--------------------------------------------------------------------- +-- Debug +--------------------------------------------------------------------- +byp_rs0_debug <= not ex1_rs0_u_b_q; +byp_rs1_debug <= not ex1_rs1_u_b_q; +byp_rs2_debug <= ex1_rs2; + +byp_gpr_sel_debug <= ex1_is_mfocrf_q(0) & + ex1_log_sel_q & + ex2_rt_sel_q(0) & + ex3_div_done_q(0) & + ex4_spr_sel_q(0) & + ex5_dtlb_sel_q(0) & + ex5_itlb_sel_q(0) & + ex5_is_mfxer_q(0) & + ex5_is_mfcr_q(0) & + ex5_mul_done_q(0) & + ex5_slowspr_sel_q(0) & + ex5_dcr_sel_q(0) & + ex5_ones_sel_q(0) & + ex6_lsu_wren_q(0) & + ex5_dcr_ack_q & + ex5_slowspr_val_q & + ex5_slowop_done; + +dec_ex2_tid_int(0) <= dec_ex2_tid(0) and not ex5_instr_trace_val_q; +dec_ex2_tid_int(1 to 2) <= dec_ex2_tid(1 to 2); +dec_ex2_tid_int(3) <= dec_ex2_tid(3) or ex5_instr_trace_val_q; + +ex5_rt_gated(0 to 31) <= ex5_rt_q(0 to 31) and not fanout(ex5_instr_trace_gate_q,regsize/2); +ex5_rt_gated(32 to 63) <= ex5_rt_q(32 to 63); + +-- 0:63 64:67 +byp_grp0_debug <= ex3_rt_q & dec_ex2_tid & byp_gpr_sel_debug; +byp_grp1_debug <= ex5_rt_gated & dec_ex2_tid_int & byp_gpr_sel_debug; +byp_grp2_debug <= ex7_rt_q & dec_ex2_tid & byp_gpr_sel_debug; +-- [14]15:22 23:87 +byp_grp3_debug <= ex1_rs0_sel_dbg_q & byp_rs0_debug; -- ex1_s1_q & ex1_ta_q(0 to 5) & ex1_gpr_we_q +byp_grp4_debug <= ex1_rs1_sel_dbg_q & byp_rs1_debug; -- ex1_s2_q & ex1_ta_q(0 to 5) +byp_grp5_debug <= ex1_rs2_sel_dbg_q & byp_rs2_debug; -- ex1_s3_q & ex1_ta_q(0 to 5) & ex1_gpr_we_q + +trace_bus_enable <= trace_bus_enable_q; + +-- Misc +mark_unused(ex5_cr(64-regsize)); +mark_unused(ex5_xer(64-regsize)); +mark_unused(ex1_mfocrf_rt(64-regsize)); +mark_unused(tidn(0 to 63)); + +--------------------------------------------------------------------- +-- Latch Instances +--------------------------------------------------------------------- +exx_act_latch : tri_rlmreg_p + generic map (width => exx_act_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(exx_act_offset to exx_act_offset + exx_act_q'length-1), + scout => sov(exx_act_offset to exx_act_offset + exx_act_q'length-1), + din => exx_act_d, + dout => exx_act_q); +rf1_act_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(rf1_act_offset), + scout => sov(rf1_act_offset), + din => dec_byp_rf0_act, + dout => rf1_act_q); +rf1_is_mfocrf_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf1_is_mfocrf_offset), + scout => sov(rf1_is_mfocrf_offset), + din => fxa_fxb_rf0_is_mfocrf, + dout => rf1_is_mfocrf_q); + + ex1_rs0_u_b_lat: entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width=> ex1_rs0_l_b_q'length, btr => "NLI0001_X4_A12TH", expand_type => expand_type, needs_sreset => 1, init => (ex1_rs0_l_b_q'range=>'0') ) port map ( + VD => vdd , + GD => gnd , + LCLK => ex1_lclk , + D1CLK => ex1_d1clk , + D2CLK => ex1_d2clk , + SCANIN => siv(ex1_rs0_u_b_offset to ex1_rs0_u_b_offset + ex1_rs0_u_b_q'length-1) , + SCANOUT => sov(ex1_rs0_u_b_offset to ex1_rs0_u_b_offset + ex1_rs0_u_b_q'length-1) , + D => rf1_rs0_u , + QB => ex1_rs0_u_b_q ); + + ex1_rs0_l_b_lat: entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width=> ex1_rs0_l_b_q'length, btr => "NLI0001_X4_A12TH", expand_type => expand_type, needs_sreset => 1, init => (ex1_rs0_l_b_q'range=>'0') ) port map ( + VD => vdd , + GD => gnd , + LCLK => ex1_slp_lclk , + D1CLK => ex1_slp_d1clk , + D2CLK => ex1_slp_d2clk , + SCANIN => siv(ex1_rs0_l_b_offset to ex1_rs0_l_b_offset + ex1_rs0_l_b_q'length-1) , + SCANOUT => sov(ex1_rs0_l_b_offset to ex1_rs0_l_b_offset + ex1_rs0_l_b_q'length-1) , + D => rf1_rs0_l , + QB => ex1_rs0_l_b_q ); + + ex1_rs1_u_b_lat: entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width=> ex1_rs1_l_b_q'length, btr => "NLI0001_X4_A12TH", expand_type => expand_type, needs_sreset => 1, init => (ex1_rs1_l_b_q'range=>'0') ) port map ( + VD => vdd , + GD => gnd , + LCLK => ex1_lclk , + D1CLK => ex1_d1clk , + D2CLK => ex1_d2clk , + SCANIN => siv(ex1_rs1_u_b_offset to ex1_rs1_u_b_offset + ex1_rs1_u_b_q'length-1) , + SCANOUT => sov(ex1_rs1_u_b_offset to ex1_rs1_u_b_offset + ex1_rs1_u_b_q'length-1) , + D => rf1_rs1_u , + QB => ex1_rs1_u_b_q ); + + ex1_rs1_l_b_lat: entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width=> ex1_rs1_l_b_q'length, btr => "NLI0001_X4_A12TH", expand_type => expand_type, needs_sreset => 1, init => (ex1_rs1_l_b_q'range=>'0') ) port map ( + VD => vdd , + GD => gnd , + LCLK => ex1_slp_lclk , + D1CLK => ex1_slp_d1clk , + D2CLK => ex1_slp_d2clk , + SCANIN => siv(ex1_rs1_l_b_offset to ex1_rs1_l_b_offset + ex1_rs1_l_b_q'length-1) , + SCANOUT => sov(ex1_rs1_l_b_offset to ex1_rs1_l_b_offset + ex1_rs1_l_b_q'length-1) , + D => rf1_rs1_l , + QB => ex1_rs1_l_b_q ); + + ex1_rs1_nimm_b_lat: entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width=> ex1_rs1_nimm_b_q'length, btr => "NLI0001_X1_A12TH", expand_type => expand_type, needs_sreset => 1, init => (ex1_rs1_nimm_b_q'range=>'0') ) port map ( + VD => vdd , + GD => gnd , + LCLK => ex1x_lclk , + D1CLK => ex1x_d1clk , + D2CLK => ex1x_d2clk , + SCANIN => siv(ex1_rs1_nimm_b_offset to ex1_rs1_nimm_b_offset + ex1_rs1_nimm_b_q'length-1) , + SCANOUT => sov(ex1_rs1_nimm_b_offset to ex1_rs1_nimm_b_offset + ex1_rs1_nimm_b_q'length-1) , + D => rf1_rs1_nimm , + QB => ex1_rs1_nimm_b_q ); + +ex1_rs2_latch : tri_rlmreg_p + generic map (width => ex1_rs2_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_rs2_offset to ex1_rs2_offset + ex1_rs2_q'length-1), + scout => sov(ex1_rs2_offset to ex1_rs2_offset + ex1_rs2_q'length-1), + din => rf1_rs2, + dout => ex1_rs2_q); +ex1_do2_latch : tri_rlmreg_p + generic map (width => ex1_do2_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_do2_offset to ex1_do2_offset + ex1_do2_q'length-1), + scout => sov(ex1_do2_offset to ex1_do2_offset + ex1_do2_q'length-1), + din => fxa_fxb_rf1_do2, + dout => ex1_do2_q); +ex1_rs2_gpr_sel_latch : tri_rlmreg_p + generic map (width => ex1_rs2_gpr_sel_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_rs2_gpr_sel_offset to ex1_rs2_gpr_sel_offset + ex1_rs2_gpr_sel_q'length-1), + scout => sov(ex1_rs2_gpr_sel_offset to ex1_rs2_gpr_sel_offset + ex1_rs2_gpr_sel_q'length-1), + din => ex1_rs2_gpr_sel_d, + dout => ex1_rs2_gpr_sel_q); +ex1_log_sel_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_log_sel_offset), + scout => sov(ex1_log_sel_offset), + din => dec_alu_rf1_sel(2), + dout => ex1_log_sel_q); +ex1_rs2_rot_sel_latch : tri_rlmreg_p + generic map (width => ex1_rs2_rot_sel_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_rs2_rot_sel_offset to ex1_rs2_rot_sel_offset + ex1_rs2_rot_sel_q'length-1), + scout => sov(ex1_rs2_rot_sel_offset to ex1_rs2_rot_sel_offset + ex1_rs2_rot_sel_q'length-1), + din => ex1_rs2_rot_sel_d, + dout => ex1_rs2_rot_sel_q); +ex1_msr_cm_latch : tri_rlmreg_p + generic map (width => ex1_msr_cm_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_msr_cm_offset to ex1_msr_cm_offset + ex1_msr_cm_q'length-1), + scout => sov(ex1_msr_cm_offset to ex1_msr_cm_offset + ex1_msr_cm_q'length-1), + din => rf1_msr_cm, + dout => ex1_msr_cm_q); +ex2_rt_sel_latch : tri_regk + generic map (width => ex2_rt_sel_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1), + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex1_rt_sel, + dout => ex2_rt_sel_q); +ex2_rt_latch : tri_regk + generic map (width => ex2_rt_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1), + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex1_rt, + dout => ex2_rt_q); +ex3_rt_latch : tri_rlmreg_p + generic map (width => ex3_rt_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_rt_offset to ex3_rt_offset + ex3_rt_q'length-1), + scout => sov(ex3_rt_offset to ex3_rt_offset + ex3_rt_q'length-1), + din => ex2_rt, + dout => ex3_rt_q); +ex4_rt_latch : tri_regk + generic map (width => ex4_rt_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3), + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex3_rt, + dout => ex4_rt_q); +ex5_rt_latch : tri_rlmreg_p + generic map (width => ex5_rt_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_rt_offset to ex5_rt_offset + ex5_rt_q'length-1), + scout => sov(ex5_rt_offset to ex5_rt_offset + ex5_rt_q'length-1), + din => ex4_rt, + dout => ex5_rt_q); +ex6_rt_latch : tri_regk + generic map (width => ex6_rt_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(5), + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex5_rt, + dout => ex6_rt_q); + + ex7_rt_lat: entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width=> ex7_rot_rt_q'length, btr => "NLI0001_X1_A12TH", expand_type => expand_type, needs_sreset => 1, init => (ex7_rot_rt_q'range=>'0') ) port map ( + VD => vdd , + GD => gnd , + LCLK => ex7_lclk , + D1CLK => ex7_d1clk , + D2CLK => ex7_d2clk , + SCANIN => siv(ex7_rt_offset to ex7_rt_offset + ex7_rt_q'length-1) , + SCANOUT => sov(ex7_rt_offset to ex7_rt_offset + ex7_rt_q'length-1) , + D => ex6_rt , + QB => ex7_rt_q_b ); + + ex7_rt_q <= not ex7_rt_q_b ; + + ex7_rot_rt_lat: entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width=> ex7_rot_rt_q'length, btr => "NLI0001_X1_A12TH", expand_type => expand_type, needs_sreset => 1, init => (ex7_rot_rt_q'range=>'0') ) port map ( + VD => vdd , + GD => gnd , + LCLK => ex7_lclk , + D1CLK => ex7_d1clk , + D2CLK => ex7_d2clk , + SCANIN => siv(ex7_rot_rt_offset to ex7_rot_rt_offset + ex7_rot_rt_q'length-1), + SCANOUT => sov(ex7_rot_rt_offset to ex7_rot_rt_offset + ex7_rot_rt_q'length-1), + D => ex6_rot_rtu_b , + QB => ex7_rot_rt_q ); + + + +ex1_is_mfocrf_latch : tri_rlmreg_p + generic map (width => ex1_is_mfocrf_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_mfocrf_offset to ex1_is_mfocrf_offset + ex1_is_mfocrf_q'length-1), + scout => sov(ex1_is_mfocrf_offset to ex1_is_mfocrf_offset + ex1_is_mfocrf_q'length-1), + din => ex1_is_mfocrf_d, + dout => ex1_is_mfocrf_q); +ex2_spr_sel_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_spr_sel_offset), + scout => sov(ex2_spr_sel_offset), + din => dec_byp_ex1_spr_sel, + dout => ex2_spr_sel_q); +ex3_spr_sel_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_spr_sel_offset), + scout => sov(ex3_spr_sel_offset), + din => ex2_spr_sel_q, + dout => ex3_spr_sel_q); +ex3_div_done_latch : tri_rlmreg_p + generic map (width => ex3_div_done_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_div_done_offset to ex3_div_done_offset + ex3_div_done_q'length-1), + scout => sov(ex3_div_done_offset to ex3_div_done_offset + ex3_div_done_q'length-1), + din => ex3_div_done_d, + dout => ex3_div_done_q); +ex4_spr_sel_latch : tri_regk + generic map (width => ex4_spr_sel_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3), + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex4_spr_sel_d, + dout => ex4_spr_sel_q); +ex4_spr_rt_latch : tri_regk + generic map (width => ex4_spr_rt_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3), + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex4_spr_rt_d, + dout => ex4_spr_rt_q); +ex4_tlb_sel_latch : tri_regk + generic map (width => ex4_tlb_sel_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => dec_byp_ex3_tlb_sel, + dout => ex4_tlb_sel_q); +ex5_is_mfxer_latch : tri_rlmreg_p + generic map (width => ex5_is_mfxer_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_is_mfxer_offset to ex5_is_mfxer_offset + ex5_is_mfxer_q'length-1), + scout => sov(ex5_is_mfxer_offset to ex5_is_mfxer_offset + ex5_is_mfxer_q'length-1), + din => ex5_is_mfxer_d, + dout => ex5_is_mfxer_q); +ex5_is_mfcr_latch : tri_rlmreg_p + generic map (width => ex5_is_mfcr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_is_mfcr_offset to ex5_is_mfcr_offset + ex5_is_mfcr_q'length-1), + scout => sov(ex5_is_mfcr_offset to ex5_is_mfcr_offset + ex5_is_mfcr_q'length-1), + din => ex5_is_mfcr_d, + dout => ex5_is_mfcr_q); +ex5_mul_done_latch : tri_rlmreg_p + generic map (width => ex5_mul_done_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_mul_done_offset to ex5_mul_done_offset + ex5_mul_done_q'length-1), + scout => sov(ex5_mul_done_offset to ex5_mul_done_offset + ex5_mul_done_q'length-1), + din => ex5_mul_done_d, + dout => ex5_mul_done_q); +ex5_dtlb_sel_latch : tri_rlmreg_p + generic map (width => ex5_dtlb_sel_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_dtlb_sel_offset to ex5_dtlb_sel_offset + ex5_dtlb_sel_q'length-1), + scout => sov(ex5_dtlb_sel_offset to ex5_dtlb_sel_offset + ex5_dtlb_sel_q'length-1), + din => ex5_dtlb_sel_d, + dout => ex5_dtlb_sel_q); +ex5_itlb_sel_latch : tri_rlmreg_p + generic map (width => ex5_itlb_sel_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_itlb_sel_offset to ex5_itlb_sel_offset + ex5_itlb_sel_q'length-1), + scout => sov(ex5_itlb_sel_offset to ex5_itlb_sel_offset + ex5_itlb_sel_q'length-1), + din => ex5_itlb_sel_d, + dout => ex5_itlb_sel_q); +ex5_tlb_data_iu_latch : tri_rlmreg_p + generic map (width => ex5_tlb_data_iu_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_tlb_data_iu_offset to ex5_tlb_data_iu_offset + ex5_tlb_data_iu_q'length-1), + scout => sov(ex5_tlb_data_iu_offset to ex5_tlb_data_iu_offset + ex5_tlb_data_iu_q'length-1), + din => iu_xu_ex4_tlb_data, + dout => ex5_tlb_data_iu_q); +ex5_tlb_data_lsu_latch : tri_rlmreg_p + generic map (width => ex5_tlb_data_lsu_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_tlb_data_lsu_offset to ex5_tlb_data_lsu_offset + ex5_tlb_data_lsu_q'length-1), + scout => sov(ex5_tlb_data_lsu_offset to ex5_tlb_data_lsu_offset + ex5_tlb_data_lsu_q'length-1), + din => lsu_xu_ex4_tlb_data, + dout => ex5_tlb_data_lsu_q); +ex5_slowspr_sel_latch : tri_rlmreg_p + generic map (width => ex5_slowspr_sel_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_slowspr_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_slowspr_sel_offset to ex5_slowspr_sel_offset + ex5_slowspr_sel_q'length-1), + scout => sov(ex5_slowspr_sel_offset to ex5_slowspr_sel_offset + ex5_slowspr_sel_q'length-1), + din => ex5_slowspr_sel_d, + dout => ex5_slowspr_sel_q); +ex5_ones_sel_latch : tri_rlmreg_p + generic map (width => ex5_ones_sel_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_slowspr_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_ones_sel_offset to ex5_ones_sel_offset + ex5_ones_sel_q'length-1), + scout => sov(ex5_ones_sel_offset to ex5_ones_sel_offset + ex5_ones_sel_q'length-1), + din => ex5_ones_sel_d, + dout => ex5_ones_sel_q); +ex5_slowspr_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_slowspr_val_offset), + scout => sov(ex5_slowspr_val_offset), + din => slowspr_val_in, + dout => ex5_slowspr_val_q); +ex5_slowspr_data_latch : tri_rlmreg_p + generic map (width => ex5_slowspr_data_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_slowspr_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_slowspr_data_offset to ex5_slowspr_data_offset + ex5_slowspr_data_q'length-1), + scout => sov(ex5_slowspr_data_offset to ex5_slowspr_data_offset + ex5_slowspr_data_q'length-1), + din => slowspr_data_in, + dout => ex5_slowspr_data_q); +ex5_slowspr_tid_latch : tri_rlmreg_p + generic map (width => ex5_slowspr_tid_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_slowspr_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_slowspr_tid_offset to ex5_slowspr_tid_offset + ex5_slowspr_tid_q'length-1), + scout => sov(ex5_slowspr_tid_offset to ex5_slowspr_tid_offset + ex5_slowspr_tid_q'length-1), + din => ex5_slowspr_tid_d, + dout => ex5_slowspr_tid_q); +ex5_slowspr_addr_latch : tri_rlmreg_p + generic map (width => ex5_slowspr_addr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_slowspr_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_slowspr_addr_offset to ex5_slowspr_addr_offset + ex5_slowspr_addr_q'length-1), + scout => sov(ex5_slowspr_addr_offset to ex5_slowspr_addr_offset + ex5_slowspr_addr_q'length-1), + din => slowspr_addr_in, + dout => ex5_slowspr_addr_q); +ex5_slowspr_wr_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_slowspr_wr_val_offset), + scout => sov(ex5_slowspr_wr_val_offset), + din => ex5_slowspr_wr_val_d, + dout => ex5_slowspr_wr_val_q); +ex6_slowspr_flush_latch : tri_rlmreg_p + generic map (width => ex6_slowspr_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_slowspr_flush_offset to ex6_slowspr_flush_offset + ex6_slowspr_flush_q'length-1), + scout => sov(ex6_slowspr_flush_offset to ex6_slowspr_flush_offset + ex6_slowspr_flush_q'length-1), + din => ex6_slowspr_flush_d, + dout => ex6_slowspr_flush_q); +ex4_dcr_act_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_dcr_act_offset), + scout => sov(ex4_dcr_act_offset), + din => an_ac_dcr_act, + dout => ex4_dcr_act_q); +ex5_dcr_sel_latch : tri_rlmreg_p + generic map (width => ex5_dcr_sel_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_dcr_sel_offset to ex5_dcr_sel_offset + ex5_dcr_sel_q'length-1), + scout => sov(ex5_dcr_sel_offset to ex5_dcr_sel_offset + ex5_dcr_sel_q'length-1), + din => ex5_dcr_sel_d, + dout => ex5_dcr_sel_q); +ex5_dcr_ack_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_dcr_ack_offset), + scout => sov(ex5_dcr_ack_offset), + din => dec_byp_ex4_dcr_ack, + dout => ex5_dcr_ack_q); +ex5_dcr_data_latch : tri_rlmreg_p + generic map (width => ex5_dcr_data_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_dcr_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_dcr_data_offset to ex5_dcr_data_offset + ex5_dcr_data_q'length-1), + scout => sov(ex5_dcr_data_offset to ex5_dcr_data_offset + ex5_dcr_data_q'length-1), + din => an_ac_dcr_data, + dout => ex5_dcr_data_q); +ex5_dcr_tid_latch : tri_rlmreg_p + generic map (width => ex5_dcr_tid_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_dcr_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_dcr_tid_offset to ex5_dcr_tid_offset + ex5_dcr_tid_q'length-1), + scout => sov(ex5_dcr_tid_offset to ex5_dcr_tid_offset + ex5_dcr_tid_q'length-1), + din => ex5_dcr_tid_d, + dout => ex5_dcr_tid_q); +ex6_lsu_wren_latch : tri_regk + generic map (width => ex6_lsu_wren_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(5), + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex6_lsu_wren_d, + dout => ex6_lsu_wren_q); +ex3_derat_epn_latch : tri_rlmreg_p + generic map (width => ex3_derat_epn_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_derat_epn_offset to ex3_derat_epn_offset + ex3_derat_epn_q'length-1), + scout => sov(ex3_derat_epn_offset to ex3_derat_epn_offset + ex3_derat_epn_q'length-1), + din => ex3_derat_epn_d, + dout => ex3_derat_epn_q); +spr_msr_cm_latch : tri_rlmreg_p + generic map (width => spr_msr_cm_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(spr_msr_cm_offset to spr_msr_cm_offset + spr_msr_cm_q'length-1), + scout => sov(spr_msr_cm_offset to spr_msr_cm_offset + spr_msr_cm_q'length-1), + din => spr_msr_cm, + dout => spr_msr_cm_q); +trace_bus_enable_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(trace_bus_enable_offset), + scout => sov(trace_bus_enable_offset), + din => pc_xu_trace_bus_enable, + dout => trace_bus_enable_q); +ex4_instr_trace_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_instr_trace_val_offset), + scout => sov(ex4_instr_trace_val_offset), + din => dec_byp_ex3_instr_trace_val, + dout => ex4_instr_trace_val_q); +ex5_instr_trace_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_instr_trace_val_offset), + scout => sov(ex5_instr_trace_val_offset), + din => ex4_instr_trace_val_q, + dout => ex5_instr_trace_val_q); +ex4_instr_trace_gate_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_instr_trace_gate_offset), + scout => sov(ex4_instr_trace_gate_offset), + din => dec_byp_ex3_instr_trace_gate, + dout => ex4_instr_trace_gate_q); +ex5_instr_trace_gate_latch : tri_rlmreg_p + generic map (width => ex5_instr_trace_gate_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_instr_trace_gate_offset to ex5_instr_trace_gate_offset + ex5_instr_trace_gate_q'length-1), + scout => sov(ex5_instr_trace_gate_offset to ex5_instr_trace_gate_offset + ex5_instr_trace_gate_q'length-1), + din => ex5_instr_trace_gate_d, + dout => ex5_instr_trace_gate_q); +ex1_rs0_sel_dbg_latch : tri_rlmreg_p + generic map (width => ex1_rs0_sel_dbg_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_rs0_sel_dbg_offset to ex1_rs0_sel_dbg_offset + ex1_rs0_sel_dbg_q'length-1), + scout => sov(ex1_rs0_sel_dbg_offset to ex1_rs0_sel_dbg_offset + ex1_rs0_sel_dbg_q'length-1), + din => dec_byp_rf1_rs0_sel, + dout => ex1_rs0_sel_dbg_q); +ex1_rs1_sel_dbg_latch : tri_rlmreg_p + generic map (width => ex1_rs1_sel_dbg_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_rs1_sel_dbg_offset to ex1_rs1_sel_dbg_offset + ex1_rs1_sel_dbg_q'length-1), + scout => sov(ex1_rs1_sel_dbg_offset to ex1_rs1_sel_dbg_offset + ex1_rs1_sel_dbg_q'length-1), + din => dec_byp_rf1_rs1_sel, + dout => ex1_rs1_sel_dbg_q); +ex1_rs2_sel_dbg_latch : tri_rlmreg_p + generic map (width => ex1_rs2_sel_dbg_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_rs2_sel_dbg_offset to ex1_rs2_sel_dbg_offset + ex1_rs2_sel_dbg_q'length-1), + scout => sov(ex1_rs2_sel_dbg_offset to ex1_rs2_sel_dbg_offset + ex1_rs2_sel_dbg_q'length-1), + din => dec_byp_rf1_rs2_sel, + dout => ex1_rs2_sel_dbg_q); + + +spare_0_lcb: entity tri.tri_lcbnd(tri_lcbnd) + port map(vd => vdd, + gd => gnd, + act => tidn(0), + nclk => nclk, + forcee => func_sl_force, + thold_b => func_sl_thold_0_b, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + sg => sg_0, + lclk => spare_0_lclk, + d1clk => spare_0_d1clk, + d2clk => spare_0_d2clk); +spare_0_latch : entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width => spare_0_q'length, expand_type => expand_type, btr => "NLI0001_X2_A12TH", init=>(spare_0_q'range=>'0')) + port map (vd => vdd, gd => gnd, + LCLK => spare_0_lclk, + D1CLK => spare_0_d1clk, + D2CLK => spare_0_d2clk, + SCANIN => siv(spare_0_offset to spare_0_offset + spare_0_q'length-1), + SCANOUT => sov(spare_0_offset to spare_0_offset + spare_0_q'length-1), + D => spare_0_d, + QB => spare_0_q); +spare_0_d <= not spare_0_q; +mark_unused(spare_0_q); + +spare_1_lcb: entity tri.tri_lcbnd(tri_lcbnd) + port map(vd => vdd, + gd => gnd, + act => tidn(0), + nclk => nclk, + forcee => func_sl_force, + thold_b => func_sl_thold_0_b, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + sg => sg_0, + lclk => spare_1_lclk, + d1clk => spare_1_d1clk, + d2clk => spare_1_d2clk); +spare_1_latch : entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width => spare_1_q'length, expand_type => expand_type, btr => "NLI0001_X2_A12TH", init=>(spare_1_q'range=>'0')) + port map (vd => vdd, gd => gnd, + LCLK => spare_1_lclk, + D1CLK => spare_1_d1clk, + D2CLK => spare_1_d2clk, + SCANIN => siv(spare_1_offset to spare_1_offset + spare_1_q'length-1), + SCANOUT => sov(spare_1_offset to spare_1_offset + spare_1_q'length-1), + D => spare_1_d, + QB => spare_1_q); +spare_1_d <= not spare_1_q; +mark_unused(spare_1_q); + +spare_2_lcb: entity tri.tri_lcbnd(tri_lcbnd) + port map(vd => vdd, + gd => gnd, + act => tidn(0), + nclk => nclk, + forcee => func_sl_force, + thold_b => func_sl_thold_0_b, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + sg => sg_0, + lclk => spare_2_lclk, + d1clk => spare_2_d1clk, + d2clk => spare_2_d2clk); +spare_2_latch : entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width => spare_2_q'length, expand_type => expand_type, btr => "NLI0001_X2_A12TH", init=>(spare_2_q'range=>'0')) + port map (vd => vdd, gd => gnd, + LCLK => spare_2_lclk, + D1CLK => spare_2_d1clk, + D2CLK => spare_2_d2clk, + SCANIN => siv(spare_2_offset to spare_2_offset + spare_2_q'length-1), + SCANOUT => sov(spare_2_offset to spare_2_offset + spare_2_q'length-1), + D => spare_2_d, + QB => spare_2_q); +spare_2_d <= not spare_2_q; +mark_unused(spare_2_q); + +spare_3_lcb: entity tri.tri_lcbnd(tri_lcbnd) + port map(vd => vdd, + gd => gnd, + act => tidn(0), + nclk => nclk, + forcee => func_sl_force, + thold_b => func_sl_thold_0_b, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + sg => sg_0, + lclk => spare_3_lclk, + d1clk => spare_3_d1clk, + d2clk => spare_3_d2clk); +spare_3_latch : entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width => spare_3_q'length, expand_type => expand_type, btr => "NLI0001_X2_A12TH", init=>(spare_3_q'range=>'0')) + port map (vd => vdd, gd => gnd, + LCLK => spare_3_lclk, + D1CLK => spare_3_d1clk, + D2CLK => spare_3_d2clk, + SCANIN => siv(spare_3_offset to spare_3_offset + spare_3_q'length-1), + SCANOUT => sov(spare_3_offset to spare_3_offset + spare_3_q'length-1), + D => spare_3_d, + QB => spare_3_q); +spare_3_d <= not spare_3_q; +mark_unused(spare_3_q); + +spare_4_lcb: entity tri.tri_lcbnd(tri_lcbnd) + port map(vd => vdd, + gd => gnd, + act => tidn(0), + nclk => nclk, + forcee => func_sl_force, + thold_b => func_sl_thold_0_b, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + sg => sg_0, + lclk => spare_4_lclk, + d1clk => spare_4_d1clk, + d2clk => spare_4_d2clk); +spare_4_latch : entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width => spare_4_q'length, expand_type => expand_type, btr => "NLI0001_X2_A12TH", init=>(spare_4_q'range=>'0')) + port map (vd => vdd, gd => gnd, + LCLK => spare_4_lclk, + D1CLK => spare_4_d1clk, + D2CLK => spare_4_d2clk, + SCANIN => siv(spare_4_offset to spare_4_offset + spare_4_q'length-1), + SCANOUT => sov(spare_4_offset to spare_4_offset + spare_4_q'length-1), + D => spare_4_d, + QB => spare_4_q); +spare_4_d <= not spare_4_q; +mark_unused(spare_4_q); + + + + +siv(0 to siv'right) <= sov(1 to siv'right) & scan_in; +scan_out <= sov(0); + + +-- ############################################################### +-- ## LCBs +-- ############################################################### + + ex1x_lcb: tri_lcbnd generic map (expand_type => expand_type) port map ( + delay_lclkr => delay_lclkr_dc ,--in -- tidn , + mpw1_b => mpw1_dc_b ,--in -- tidn , + mpw2_b => mpw2_dc_b ,--in -- tidn , + forcee => func_sl_force ,--in -- tidn , + nclk => nclk ,--in + vd => vdd ,--inout + gd => gnd ,--inout + act => rf1_act_q ,--in + sg => sg_0 ,--in + thold_b => func_sl_thold_0_b ,--in + d1clk => ex1x_d1clk ,--out + d2clk => ex1x_d2clk ,--out + lclk => ex1x_lclk );--out + + + ex1_lcb: tri_lcbnd generic map (expand_type => expand_type) port map ( + delay_lclkr => delay_lclkr_dc ,--in -- tidn , + mpw1_b => mpw1_dc_b ,--in -- tidn , + mpw2_b => mpw2_dc_b ,--in -- tidn , + forcee => func_sl_force ,--in -- tidn , + nclk => nclk ,--in + vd => vdd ,--inout + gd => gnd ,--inout + act => rf1_act_q ,--in + sg => sg_0 ,--in + thold_b => func_sl_thold_0_b ,--in + d1clk => ex1_d1clk ,--out + d2clk => ex1_d2clk ,--out + lclk => ex1_lclk );--out + + ex1_slp_lcb: tri_lcbnd generic map (expand_type => expand_type) port map ( + delay_lclkr => delay_lclkr_dc ,--in -- tidn , + mpw1_b => mpw1_dc_b ,--in -- tidn , + mpw2_b => mpw2_dc_b ,--in -- tidn , + forcee => func_slp_sl_force ,--in -- tidn , + nclk => nclk ,--in + vd => vdd ,--inout + gd => gnd ,--inout + act => rf1_act_q ,--in + sg => sg_0 ,--in + thold_b => func_slp_sl_thold_0_b,--in + d1clk => ex1_slp_d1clk ,--out + d2clk => ex1_slp_d2clk ,--out + lclk => ex1_slp_lclk );--out + + + ex7_lcb: tri_lcbnd generic map (expand_type => expand_type) port map ( + delay_lclkr => delay_lclkr_dc ,--in -- tidn , + mpw1_b => mpw1_dc_b ,--in -- tidn , + mpw2_b => mpw2_dc_b ,--in -- tidn , + forcee => func_sl_force ,--in -- tidn , + nclk => nclk ,--in + vd => vdd ,--inout + gd => gnd ,--inout + act => exx_act(6) ,--in + sg => sg_0 ,--in + thold_b => func_sl_thold_0_b ,--in + d1clk => ex7_d1clk ,--out + d2clk => ex7_d2clk ,--out + lclk => ex7_lclk );--out + + +end architecture xuq_byp_gpr; diff --git a/rel/src/vhdl/work/xuq_byp_xer.vhdl b/rel/src/vhdl/work/xuq_byp_xer.vhdl new file mode 100644 index 0000000..ed068a2 --- /dev/null +++ b/rel/src/vhdl/work/xuq_byp_xer.vhdl @@ -0,0 +1,805 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XU XER Bypass Unit +-- +library ieee,ibm,support,tri,work; +use ieee.std_logic_1164.all; +use ibm.std_ulogic_function_support.all; +use tri.tri_latches_pkg.all; +use support.power_logic_pkg.all; +use work.xuq_pkg.all; + +entity xuq_byp_xer is + generic ( + threads : integer := 4; + expand_type : integer := 2; + regsize : integer := 64); + port ( + -- Clocks + nclk : in clk_logic; + + -- Power + vdd : inout power_logic; + gnd : inout power_logic; + + trace_bus_enable : in std_ulogic; + + -- Pervasive + d_mode_dc : in std_ulogic; + delay_lclkr_dc : in std_ulogic; + mpw1_dc_b : in std_ulogic; + mpw2_dc_b : in std_ulogic; + func_sl_force : in std_ulogic; + func_sl_thold_0_b : in std_ulogic; + func_slp_sl_force : in std_ulogic; + func_slp_sl_thold_0_b : in std_ulogic; + sg_0 : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + -- Used bit signals + dec_byp_rf1_ca_used : in std_ulogic; + dec_byp_rf1_ov_used : in std_ulogic; + + -- Bypass Inputs + rf1_tid : in std_ulogic_vector(0 to threads-1); + ex5_tid : in std_ulogic_vector(0 to threads-1); + + -- Valid + dec_byp_ex3_val : in std_ulogic_vector(0 to threads-1); + dec_byp_rf1_byp_val : in std_ulogic_vector(2 to 3); + + -- Flushes + xu_ex3_flush : in std_ulogic_vector(0 to threads-1); + xu_ex4_flush : in std_ulogic_vector(0 to threads-1); + xu_ex5_flush : in std_ulogic_vector(0 to threads-1); + + -- mfxer + byp_ex5_xer_rt : out std_ulogic_vector(54 to 63); + + -- Valids + alu_ex2_div_done : in std_ulogic; + alu_ex4_mul_done : in std_ulogic; + + -- XER Inputs + alu_byp_ex2_xer : in std_ulogic_vector(0 to 3); -- 0: OV bit 1: CA bit 2: OV Update 3: CA Update + alu_byp_ex5_xer_mul : in std_ulogic_vector(0 to 3); -- 0: OV bit 1: CA bit 2: OV Update 3: CA Update + alu_byp_ex3_xer_div : in std_ulogic_vector(0 to 3); -- 0: OV bit 1: CA bit 2: OV Update 3: CA Update + spr_byp_ex4_is_mtxer : in std_ulogic_vector(0 to threads-1); + byp_ex5_mtcrxer : in std_ulogic_vector(32 to 63); + + -- Outputs + byp_xer_si : out std_ulogic_vector(0 to 7*threads-1); + byp_xer_so : out std_ulogic_vector(0 to threads-1); + xer_cr_ex1_xer_ov_in_pipe : out std_ulogic; + xer_cr_ex2_xer_ov_in_pipe : out std_ulogic; + xer_cr_ex3_xer_ov_in_pipe : out std_ulogic; + xer_cr_ex5_xer_ov_in_pipe : out std_ulogic; + byp_dec_rf1_xer_ca : out std_ulogic; + + xer_debug : out std_ulogic_vector(22 to 87) + ); + +-- synopsys translate_off + +-- synopsys translate_on +end xuq_byp_xer; +architecture xuq_byp_xer of xuq_byp_xer is + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + subtype s2 is std_ulogic_vector(0 to 1); + + -- Signals + signal ex2_xer : std_ulogic_vector(0 to 3); + signal ex3_xer : std_ulogic_vector(0 to 3); + signal ex4_xer : std_ulogic_vector(0 to 3); + signal ex5_xer : std_ulogic_vector(0 to 3); + signal ex3_val : std_ulogic_vector(0 to threads-1); + signal ex4_val : std_ulogic_vector(0 to threads-1); + signal ex5_val : std_ulogic_vector(0 to threads-1); + signal xer_out : std_ulogic_vector(0 to 10*threads-1); + signal rf1_byp_val : std_ulogic_vector(4 to 5); + signal rf1_byp_val_ov : std_ulogic_vector(2 to 5); + signal rf1_byp_ov_pri : std_ulogic_vector(2 to 6); + signal rf1_byp_val_ca : std_ulogic_vector(2 to 5); + signal rf1_byp_ca_pri : std_ulogic_vector(2 to 6); + signal xer_ex5_mux : std_ulogic_vector(54 to 63); + signal xer_rf1_mux : std_ulogic_vector(54 to 63); + signal rf1_ov_byp_from_reg : std_ulogic; + signal rf1_ov : std_ulogic; + signal rf1_ca : std_ulogic; + signal rf1_xer_ov_in_pipe : std_ulogic; + + -- Latches + signal ex3_xer_q : std_ulogic_vector(0 to 3); + signal ex4_xer_q : std_ulogic_vector(0 to 3); + signal ex5_xer_q : std_ulogic_vector(0 to 3); + signal ex4_val_q : std_ulogic_vector(0 to threads-1); + signal ex5_val_q : std_ulogic_vector(0 to threads-1); + signal ex1_xer_ov_bypassed_q : std_ulogic; + signal ex2_xer_ov_bypassed_q : std_ulogic; + signal ex3_xer_ov_bypassed_q : std_ulogic; + signal ex4_xer_ov_bypassed_q : std_ulogic; + signal ex5_xer_ov_bypassed_q : std_ulogic; + signal ex1_ov_byp_from_reg_q : std_ulogic; + signal ex2_ov_byp_from_reg_q : std_ulogic; + signal ex3_ov_byp_from_reg_q : std_ulogic; + signal ex4_ov_byp_from_reg_q : std_ulogic; + signal ex5_ov_byp_from_reg_q : std_ulogic; + signal ex1_xer_ov_in_pipe_q : std_ulogic; + signal ex2_xer_ov_in_pipe_q : std_ulogic; + signal ex3_xer_ov_in_pipe_q : std_ulogic; + signal ex4_xer_ov_in_pipe_q : std_ulogic; + signal ex5_xer_ov_in_pipe_q : std_ulogic; + signal ex5_is_mtxer_q : std_ulogic_vector(0 to threads-1); -- spr_byp_ex4_is_mtxer + signal ex3_div_done_q : std_ulogic; -- input=>alu_ex2_div_done + signal ex5_mul_done_q : std_ulogic; -- input=>alu_ex4_mul_done + signal debug_q, debug_d : std_ulogic_vector(0 to 31); -- input=>debug_d, act=>trace_bus_enable, sleep=>Y, needs_sreset=>0 + + -- Scanchains + constant ex3_xer_offset : integer := 0; + constant ex4_xer_offset : integer := ex3_xer_offset + ex3_xer_q'length; + constant ex5_xer_offset : integer := ex4_xer_offset + ex4_xer_q'length; + constant ex4_val_offset : integer := ex5_xer_offset + ex5_xer_q'length; + constant ex5_val_offset : integer := ex4_val_offset + ex4_val_q'length; + constant ex1_xer_ov_bypassed_offset : integer := ex5_val_offset + ex5_val_q'length; + constant ex2_xer_ov_bypassed_offset : integer := ex1_xer_ov_bypassed_offset + 1; + constant ex3_xer_ov_bypassed_offset : integer := ex2_xer_ov_bypassed_offset + 1; + constant ex4_xer_ov_bypassed_offset : integer := ex3_xer_ov_bypassed_offset + 1; + constant ex5_xer_ov_bypassed_offset : integer := ex4_xer_ov_bypassed_offset + 1; + constant ex1_ov_byp_from_reg_offset : integer := ex5_xer_ov_bypassed_offset + 1; + constant ex2_ov_byp_from_reg_offset : integer := ex1_ov_byp_from_reg_offset + 1; + constant ex3_ov_byp_from_reg_offset : integer := ex2_ov_byp_from_reg_offset + 1; + constant ex4_ov_byp_from_reg_offset : integer := ex3_ov_byp_from_reg_offset + 1; + constant ex5_ov_byp_from_reg_offset : integer := ex4_ov_byp_from_reg_offset + 1; + constant ex1_xer_ov_in_pipe_offset : integer := ex5_ov_byp_from_reg_offset + 1; + constant ex2_xer_ov_in_pipe_offset : integer := ex1_xer_ov_in_pipe_offset + 1; + constant ex3_xer_ov_in_pipe_offset : integer := ex2_xer_ov_in_pipe_offset + 1; + constant ex4_xer_ov_in_pipe_offset : integer := ex3_xer_ov_in_pipe_offset + 1; + constant ex5_xer_ov_in_pipe_offset : integer := ex4_xer_ov_in_pipe_offset + 1; + constant ex5_is_mtxer_offset : integer := ex5_xer_ov_in_pipe_offset + 1; + constant xer_offset : integer := ex5_is_mtxer_offset + ex5_is_mtxer_q'length; + constant ex3_div_done_offset : integer := xer_offset + 10*threads; + constant ex5_mul_done_offset : integer := ex3_div_done_offset + 1; + constant debug_offset : integer := ex5_mul_done_offset + 1; + constant scan_right : integer := debug_offset + debug_q'length; + signal siv : std_ulogic_vector(0 to scan_right-1); + signal sov : std_ulogic_vector(0 to scan_right-1); +begin + + --------------------------------------------------------------------- + -- Valids + --------------------------------------------------------------------- + ex3_val <= dec_byp_ex3_val and not xu_ex3_flush; + ex4_val <= ex4_val_q and not xu_ex4_flush; + ex5_val <= ex5_val_q and not xu_ex5_flush; + + --------------------------------------------------------------------- + -- XER pipeline input + --------------------------------------------------------------------- + ex2_xer <= alu_byp_ex2_xer; + + with ex3_div_done_q select + ex3_xer <= alu_byp_ex3_xer_div when '1', + ex3_xer_q when others; + + ex4_xer <= ex4_xer_q; + + with ex5_mul_done_q select + ex5_xer <= alu_byp_ex5_xer_mul when '1', + ex5_xer_q when others; + + --------------------------------------------------------------------- + -- MFXER + --------------------------------------------------------------------- + xer_ex5_mux <= mux_t(xer_out,ex5_tid); + byp_ex5_xer_rt <= (xer_ex5_mux(54) or (ex5_xer_ov_bypassed_q and not ex5_ov_byp_from_reg_q)) & -- SO bit + (xer_ex5_mux(55) or ex5_xer_ov_bypassed_q) & -- OV bit + xer_ex5_mux(56 to 63); + + --------------------------------------------------------------------- + -- Bypass valids + --------------------------------------------------------------------- + rf1_byp_val(4) <= '1' when rf1_tid = ex4_val_q else '0'; + rf1_byp_val(5) <= '1' when rf1_tid = ex5_val_q else '0'; + + --------------------------------------------------------------------- + -- Bypass control (OV) + --------------------------------------------------------------------- + rf1_byp_val_ov(2) <= ex2_xer(2) and dec_byp_rf1_byp_val(2) and dec_byp_rf1_ov_used; -- OV bit in EX2 is valid, TID is valid, OV bit is used in RF1 instr + rf1_byp_val_ov(3) <= ex3_xer(2) and dec_byp_rf1_byp_val(3) and dec_byp_rf1_ov_used; -- OV bit in EX3 is valid, TID is valid, OV bit is used in RF1 instr + rf1_byp_val_ov(4) <= ex4_xer(2) and rf1_byp_val(4) and dec_byp_rf1_ov_used; -- OV bit in EX4 is valid, TID is valid, OV bit is used in RF1 instr + rf1_byp_val_ov(5) <= ex5_xer(2) and rf1_byp_val(5) and dec_byp_rf1_ov_used; -- OV bit in EX5 is valid, TID is valid, OV bit is used in RF1 instr + + -- Prioritization + rf1_byp_ov_pri(2) <= rf1_byp_val_ov(2); + rf1_byp_ov_pri(3) <= not rf1_byp_val_ov(2) and rf1_byp_val_ov(3); + rf1_byp_ov_pri(4) <= not or_reduce(rf1_byp_val_ov(2 to 3)) and rf1_byp_val_ov(4); + rf1_byp_ov_pri(5) <= not or_reduce(rf1_byp_val_ov(2 to 4)) and rf1_byp_val_ov(5); + rf1_byp_ov_pri(6) <= not or_reduce(rf1_byp_val_ov(2 to 5)); + + --------------------------------------------------------------------- + -- Bypass control (CA) + --------------------------------------------------------------------- + rf1_byp_val_ca(2) <= ex2_xer(3) and dec_byp_rf1_byp_val(2) and dec_byp_rf1_ca_used; -- CA bit in EX2 is valid, TID is valid, CA bit is used in RF1 instr + rf1_byp_val_ca(3) <= ex3_xer(3) and dec_byp_rf1_byp_val(3) and dec_byp_rf1_ca_used; -- CA bit in EX3 is valid, TID is valid, CA bit is used in RF1 instr + rf1_byp_val_ca(4) <= ex4_xer(3) and rf1_byp_val(4) and dec_byp_rf1_ca_used; -- CA bit in EX4 is valid, TID is valid, CA bit is used in RF1 instr + rf1_byp_val_ca(5) <= ex5_xer(3) and rf1_byp_val(5) and dec_byp_rf1_ca_used; -- CA bit in EX5 is valid, TID is valid, CA bit is used in RF1 instr + + -- Prioritization + rf1_byp_ca_pri(2) <= rf1_byp_val_ca(2); + rf1_byp_ca_pri(3) <= not rf1_byp_val_ca(2) and rf1_byp_val_ca(3); + rf1_byp_ca_pri(4) <= not or_reduce(rf1_byp_val_ca(2 to 3)) and rf1_byp_val_ca(4); + rf1_byp_ca_pri(5) <= not or_reduce(rf1_byp_val_ca(2 to 4)) and rf1_byp_val_ca(5); + rf1_byp_ca_pri(6) <= not or_reduce(rf1_byp_val_ca(2 to 5)); + + --------------------------------------------------------------------- + -- RF1 Source Selection + --------------------------------------------------------------------- + rf1_ov <= (ex2_xer(0) and rf1_byp_ov_pri(2)) or + (ex3_xer(0) and rf1_byp_ov_pri(3)) or + (ex4_xer(0) and rf1_byp_ov_pri(4)) or + (ex5_xer(0) and rf1_byp_ov_pri(5)) or + (xer_rf1_mux(55) and rf1_byp_ov_pri(6)); + + rf1_ca <= (ex2_xer(1) and rf1_byp_ca_pri(2)) or + (ex3_xer(1) and rf1_byp_ca_pri(3)) or + (ex4_xer(1) and rf1_byp_ca_pri(4)) or + (ex5_xer(1) and rf1_byp_ca_pri(5)) or + (xer_rf1_mux(56) and rf1_byp_ca_pri(6)); + + xer_rf1_mux <= mux_t(xer_out,rf1_tid); + rf1_ov_byp_from_reg <= rf1_byp_ov_pri(6); + + --------------------------------------------------------------------- + -- XER Writeback + --------------------------------------------------------------------- + xuq_byp_xer_gen : for t in 0 to threads-1 generate + signal xer_d, xer_q : std_ulogic_vector(54 to 63); + signal ex5_mtxer_we : std_ulogic; + signal ex5_ca_we : std_ulogic; + signal ex5_ov_we : std_ulogic; + signal ex5_so_sel : std_ulogic_vector(0 to 2); + signal ex5_ov_sel : std_ulogic_vector(0 to 2); + signal ex5_ca_sel : std_ulogic_vector(0 to 2); + begin + ex5_mtxer_we <= ex5_val(t) and ex5_is_mtxer_q(t); + ex5_ov_we <= ex5_val(t) and ex5_xer(2); + ex5_ca_we <= ex5_val(t) and ex5_xer(3); + + ex5_so_sel(0 to 1) <= ex5_mtxer_we & (ex5_ov_we and ex5_xer(0)); + ex5_so_sel(2) <= not (ex5_so_sel(0) or ex5_so_sel(1)); + + ex5_ov_sel(0 to 1) <= ex5_mtxer_we & ex5_ov_we; + ex5_ov_sel(2) <= not (ex5_ov_sel(0) or ex5_ov_sel(1)); + + ex5_ca_sel(0 to 1) <= ex5_mtxer_we & ex5_ca_we; + ex5_ca_sel(2) <= not (ex5_ca_sel(0) or ex5_ca_sel(1)); + + -- SO Bit + xer_d(54) <= (byp_ex5_mtcrxer(32) and ex5_so_sel(0)) or + ( ex5_so_sel(1)) or + (xer_q(54) and ex5_so_sel(2)); + -- OV Bit + xer_d(55) <= (byp_ex5_mtcrxer(33) and ex5_ov_sel(0)) or + (ex5_xer(0) and ex5_ov_sel(1)) or + (xer_q(55) and ex5_ov_sel(2)); + -- CA Bit + xer_d(56) <= (byp_ex5_mtcrxer(34) and ex5_ca_sel(0)) or + (ex5_xer(1) and ex5_ca_sel(1)) or + (xer_q(56) and ex5_ca_sel(2)); + -- SI + xer_d(57 to 63) <= byp_ex5_mtcrxer(57 to 63) when ex5_mtxer_we = '1' else + xer_q(57 to 63); + + -- XER Output + xer_out(t*10 to t*10+9) <= xer_q; + byp_xer_si(t*7 to t*7+6) <= xer_q(57 to 63); + byp_xer_so(t) <= xer_q(54); + + --------------------------------------------------------------------- + -- XER Latch + --------------------------------------------------------------------- + xer_latch : tri_rlmreg_p + generic map (width => xer_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xer_offset + xer_q'length*t to xer_offset + xer_q'length*(t+1)-1), + scout => sov(xer_offset + xer_q'length*t to xer_offset + xer_q'length*(t+1)-1), + din => xer_d, + dout => xer_q); + end generate; + + --------------------------------------------------------------------- + -- XER output (threadwise) + --------------------------------------------------------------------- + byp_dec_rf1_xer_ca <= rf1_ca; + + rf1_xer_ov_in_pipe <= (ex2_xer(0) and ex2_xer(2) and dec_byp_rf1_byp_val(2)) or + (ex3_xer(0) and ex3_xer(2) and dec_byp_rf1_byp_val(3)) or + (ex4_xer(0) and ex4_xer(2) and rf1_byp_val(4) ) or + (ex5_xer(0) and ex5_xer(2) and rf1_byp_val(5) ); + + xer_cr_ex1_xer_ov_in_pipe <= ex1_xer_ov_in_pipe_q; + xer_cr_ex2_xer_ov_in_pipe <= ex2_xer_ov_in_pipe_q; + xer_cr_ex3_xer_ov_in_pipe <= ex3_xer_ov_in_pipe_q; + xer_cr_ex5_xer_ov_in_pipe <= ex5_xer_ov_in_pipe_q; + + mark_unused(xer_rf1_mux(54)); + mark_unused(xer_rf1_mux(57 to 63)); + mark_unused(byp_ex5_mtcrxer(35 to 56)); + + --------------------------------------------------------------------- + -- Debug + --------------------------------------------------------------------- + debug_d(0 to 31) <= ex5_val & + dec_byp_rf1_ov_used & + dec_byp_rf1_ca_used & + rf1_byp_ov_pri(2 to 6) & + rf1_byp_ca_pri(2 to 6) & + ex2_xer(0 to 3) & + ex3_xer(0 to 3) & + ex4_xer(0 to 3) & + ex5_xer(0 to 3); + + + xer_debug(22 to 87) <= debug_q & + ex3_div_done_q & + ex5_mul_done_q & + ex5_is_mtxer_q(0 to 3) & + ex1_xer_ov_bypassed_q & + ex2_xer_ov_bypassed_q & + ex3_xer_ov_bypassed_q & + ex4_xer_ov_bypassed_q & + ex5_xer_ov_bypassed_q & + ex1_ov_byp_from_reg_q & + ex2_ov_byp_from_reg_q & + ex3_ov_byp_from_reg_q & + ex4_ov_byp_from_reg_q & + ex5_ov_byp_from_reg_q & + ex1_xer_ov_in_pipe_q & + ex2_xer_ov_in_pipe_q & + ex3_xer_ov_in_pipe_q & + ex4_xer_ov_in_pipe_q & + ex5_xer_ov_in_pipe_q & + xer_out( 7 to 9) & + xer_out(17 to 19) & + xer_out(27 to 29) & + xer_out(37 to 39) & + '0'; + + --------------------------------------------------------------------- + -- Latch Instances + --------------------------------------------------------------------- + ex3_xer_latch : tri_rlmreg_p + generic map (width => ex3_xer_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_xer_offset to ex3_xer_offset + ex3_xer_q'length-1), + scout => sov(ex3_xer_offset to ex3_xer_offset + ex3_xer_q'length-1), + din => ex2_xer, + dout => ex3_xer_q); + ex4_xer_latch : tri_rlmreg_p + generic map (width => ex4_xer_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_xer_offset to ex4_xer_offset + ex4_xer_q'length-1), + scout => sov(ex4_xer_offset to ex4_xer_offset + ex4_xer_q'length-1), + din => ex3_xer, + dout => ex4_xer_q); + ex5_xer_latch : tri_rlmreg_p + generic map (width => ex5_xer_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_xer_offset to ex5_xer_offset + ex5_xer_q'length-1), + scout => sov(ex5_xer_offset to ex5_xer_offset + ex5_xer_q'length-1), + din => ex4_xer, + dout => ex5_xer_q); + ex4_val_latch : tri_rlmreg_p + generic map (width => ex4_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_val_offset to ex4_val_offset + ex4_val_q'length-1), + scout => sov(ex4_val_offset to ex4_val_offset + ex4_val_q'length-1), + din => ex3_val, + dout => ex4_val_q); + ex5_val_latch : tri_rlmreg_p + generic map (width => ex5_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_val_offset to ex5_val_offset + ex5_val_q'length-1), + scout => sov(ex5_val_offset to ex5_val_offset + ex5_val_q'length-1), + din => ex4_val, + dout => ex5_val_q); + ex1_xer_ov_bypassed_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_xer_ov_bypassed_offset), + scout => sov(ex1_xer_ov_bypassed_offset), + din => rf1_ov, + dout => ex1_xer_ov_bypassed_q); + ex2_xer_ov_bypassed_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_xer_ov_bypassed_offset), + scout => sov(ex2_xer_ov_bypassed_offset), + din => ex1_xer_ov_bypassed_q, + dout => ex2_xer_ov_bypassed_q); + ex3_xer_ov_bypassed_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_xer_ov_bypassed_offset), + scout => sov(ex3_xer_ov_bypassed_offset), + din => ex2_xer_ov_bypassed_q, + dout => ex3_xer_ov_bypassed_q); + ex4_xer_ov_bypassed_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_xer_ov_bypassed_offset), + scout => sov(ex4_xer_ov_bypassed_offset), + din => ex3_xer_ov_bypassed_q, + dout => ex4_xer_ov_bypassed_q); + ex5_xer_ov_bypassed_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_xer_ov_bypassed_offset), + scout => sov(ex5_xer_ov_bypassed_offset), + din => ex4_xer_ov_bypassed_q, + dout => ex5_xer_ov_bypassed_q); + ex1_ov_byp_from_reg_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_ov_byp_from_reg_offset), + scout => sov(ex1_ov_byp_from_reg_offset), + din => rf1_ov_byp_from_reg, + dout => ex1_ov_byp_from_reg_q); + ex2_ov_byp_from_reg_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_ov_byp_from_reg_offset), + scout => sov(ex2_ov_byp_from_reg_offset), + din => ex1_ov_byp_from_reg_q, + dout => ex2_ov_byp_from_reg_q); + ex3_ov_byp_from_reg_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_ov_byp_from_reg_offset), + scout => sov(ex3_ov_byp_from_reg_offset), + din => ex2_ov_byp_from_reg_q, + dout => ex3_ov_byp_from_reg_q); + ex4_ov_byp_from_reg_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_ov_byp_from_reg_offset), + scout => sov(ex4_ov_byp_from_reg_offset), + din => ex3_ov_byp_from_reg_q, + dout => ex4_ov_byp_from_reg_q); + ex5_ov_byp_from_reg_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_ov_byp_from_reg_offset), + scout => sov(ex5_ov_byp_from_reg_offset), + din => ex4_ov_byp_from_reg_q, + dout => ex5_ov_byp_from_reg_q); + ex1_xer_ov_in_pipe_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_xer_ov_in_pipe_offset), + scout => sov(ex1_xer_ov_in_pipe_offset), + din => rf1_xer_ov_in_pipe, + dout => ex1_xer_ov_in_pipe_q); + ex2_xer_ov_in_pipe_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_xer_ov_in_pipe_offset), + scout => sov(ex2_xer_ov_in_pipe_offset), + din => ex1_xer_ov_in_pipe_q, + dout => ex2_xer_ov_in_pipe_q); + ex3_xer_ov_in_pipe_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_xer_ov_in_pipe_offset), + scout => sov(ex3_xer_ov_in_pipe_offset), + din => ex2_xer_ov_in_pipe_q, + dout => ex3_xer_ov_in_pipe_q); + ex4_xer_ov_in_pipe_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_xer_ov_in_pipe_offset), + scout => sov(ex4_xer_ov_in_pipe_offset), + din => ex3_xer_ov_in_pipe_q, + dout => ex4_xer_ov_in_pipe_q); + ex5_xer_ov_in_pipe_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_xer_ov_in_pipe_offset), + scout => sov(ex5_xer_ov_in_pipe_offset), + din => ex4_xer_ov_in_pipe_q, + dout => ex5_xer_ov_in_pipe_q); + ex5_is_mtxer_latch : tri_rlmreg_p + generic map (width => ex5_is_mtxer_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_is_mtxer_offset to ex5_is_mtxer_offset+ex5_is_mtxer_q'length-1), + scout => sov(ex5_is_mtxer_offset to ex5_is_mtxer_offset+ex5_is_mtxer_q'length-1), + din => spr_byp_ex4_is_mtxer, + dout => ex5_is_mtxer_q); + ex3_div_done_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_div_done_offset), + scout => sov(ex3_div_done_offset), + din => alu_ex2_div_done, + dout => ex3_div_done_q); + ex5_mul_done_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_mul_done_offset), + scout => sov(ex5_mul_done_offset), + din => alu_ex4_mul_done, + dout => ex5_mul_done_q); + debug_latch : tri_rlmreg_p + generic map (width => debug_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(debug_offset to debug_offset + debug_q'length-1), + scout => sov(debug_offset to debug_offset + debug_q'length-1), + din => debug_d, + dout => debug_q); + + siv(0 to siv'right) <= sov(1 to siv'right) & scan_in; + scan_out <= sov(0); + +end architecture xuq_byp_xer; diff --git a/rel/src/vhdl/work/xuq_cpl.vhdl b/rel/src/vhdl/work/xuq_cpl.vhdl new file mode 100644 index 0000000..ca3b858 --- /dev/null +++ b/rel/src/vhdl/work/xuq_cpl.vhdl @@ -0,0 +1,10969 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XU Exception Handler +-- +library ieee,ibm,support,work,tri,clib; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use support.power_logic_pkg.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use tri.tri_latches_pkg.all; +use work.xuq_pkg.all; + +entity xuq_cpl is +generic( + expand_type : integer := 2; + threads : integer := 4; + eff_ifar : integer := 62; + uc_ifar : integer := 21; + regsize : integer := 64; + hvmode : integer := 1; + a2mode : integer := 1); +port( + -- Clocks + nclk : in clk_logic; + + -- CHIP IO + ac_tc_debug_trigger : out std_ulogic_vector(0 to threads-1); + + -- Pervasive + an_ac_scan_dis_dc_b : in std_ulogic; + pc_xu_ccflush_dc : in std_ulogic; + clkoff_dc_b : in std_ulogic; + d_mode_dc : in std_ulogic; + delay_lclkr_dc : in std_ulogic; + mpw1_dc_b : in std_ulogic; + mpw2_dc_b : in std_ulogic; + func_sl_thold_2 : in std_ulogic; + func_nsl_thold_2 : in std_ulogic; + func_slp_sl_thold_2 : in std_ulogic; + func_slp_nsl_thold_2 : in std_ulogic; + cfg_sl_thold_2 : in std_ulogic; + cfg_slp_sl_thold_2 : in std_ulogic; + sg_2 : in std_ulogic; + fce_2 : in std_ulogic; + func_scan_in : in std_ulogic_vector(50 to 53); + func_scan_out : out std_ulogic_vector(50 to 53); + bcfg_scan_in : in std_ulogic; + bcfg_scan_out : out std_ulogic; + ccfg_scan_in : in std_ulogic; + ccfg_scan_out : out std_ulogic; + dcfg_scan_in : in std_ulogic; + dcfg_scan_out : out std_ulogic; + + -- Valids + dec_cpl_rf0_act : in std_ulogic; + dec_cpl_rf0_tid : in std_ulogic_vector(0 to threads-1); + dec_cpl_rf1_val : in std_ulogic_vector(0 to threads-1); + dec_cpl_rf1_issued : in std_ulogic_vector(0 to threads-1); + + -- IU Inputs + dec_cpl_ex2_error : in std_ulogic_vector(0 to 2); + dec_cpl_ex2_match : in std_ulogic; + + -- FU Inputs + fu_xu_rf1_act : in std_ulogic_vector(0 to threads-1); + fu_xu_ex1_ifar : in std_ulogic_vector(0 to eff_ifar*threads-1); + fu_xu_ex2_ifar_issued : in std_ulogic_vector(0 to threads-1); + fu_xu_ex2_ifar_val : in std_ulogic_vector(0 to threads-1); + fu_xu_ex2_instr_type : in std_ulogic_vector(0 to 3*threads-1); + fu_xu_ex2_instr_match : in std_ulogic_vector(0 to threads-1); + fu_xu_ex2_is_ucode : in std_ulogic_vector(0 to threads-1); + + -- PC Inputs + pc_xu_step : in std_ulogic_vector(0 to threads-1); + pc_xu_stop : in std_ulogic_vector(0 to threads-1); + pc_xu_dbg_action : in std_ulogic_vector(0 to 3*threads-1); + pc_xu_force_ude : in std_ulogic_vector(0 to threads-1); + xu_pc_step_done : out std_ulogic_vector(0 to threads-1); + pc_xu_init_reset : in std_ulogic; + + -- Bypass Inputs + byp_cpl_ex1_cr_bit : in std_ulogic; + + -- Decode Inputs + dec_cpl_rf1_pred_taken_cnt : in std_ulogic; + dec_cpl_rf1_instr : in std_ulogic_vector(0 to 31); + dec_cpl_ex3_is_any_store : in std_ulogic; + dec_cpl_ex2_is_any_store_dac : in std_ulogic; + dec_cpl_ex2_is_any_load_dac : in std_ulogic; + dec_cpl_ex3_instr_priv : in std_ulogic; + dec_cpl_ex3_instr_hypv : in std_ulogic; + dec_cpl_ex1_epid_instr : in std_ulogic; + dec_cpl_ex3_tlb_illeg : in std_ulogic; + dec_cpl_ex3_axu_instr_type : in std_ulogic_vector(0 to 2); + dec_cpl_rf1_ucode_val : in std_ulogic_vector(0 to threads-1); + dec_cpl_ex3_mtdp_nr : in std_ulogic; + lsu_xu_ex4_mtdp_cr_status : in std_ulogic; + dec_cpl_ex3_mc_dep_chk_val : in std_ulogic_vector(0 to threads-1); + dec_cpl_ex2_illegal_op : in std_ulogic; + dec_cpl_ex3_mult_coll : in std_ulogic; + fxa_cpl_ex2_div_coll : in std_ulogic_vector(0 to threads-1); + + -- Async Interrupt Req Interface + spr_cpl_ext_interrupt : in std_ulogic_vector(0 to threads-1); + spr_cpl_udec_interrupt : in std_ulogic_vector(0 to threads-1); + spr_cpl_perf_interrupt : in std_ulogic_vector(0 to threads-1); + spr_cpl_dec_interrupt : in std_ulogic_vector(0 to threads-1); + spr_cpl_fit_interrupt : in std_ulogic_vector(0 to threads-1); + spr_cpl_crit_interrupt : in std_ulogic_vector(0 to threads-1); + spr_cpl_wdog_interrupt : in std_ulogic_vector(0 to threads-1); + spr_cpl_dbell_interrupt : in std_ulogic_vector(0 to threads-1); + spr_cpl_cdbell_interrupt : in std_ulogic_vector(0 to threads-1); + spr_cpl_gdbell_interrupt : in std_ulogic_vector(0 to threads-1); + spr_cpl_gcdbell_interrupt : in std_ulogic_vector(0 to threads-1); + spr_cpl_gmcdbell_interrupt : in std_ulogic_vector(0 to threads-1); + + cpl_spr_ex5_dbell_taken : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_cdbell_taken : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_gdbell_taken : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_gcdbell_taken : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_gmcdbell_taken : out std_ulogic_vector(0 to threads-1); + + -- IFAR + dec_cpl_rf1_ifar : in std_ulogic_vector(62-eff_ifar to 61); + + -- Debug Compares + spr_cpl_iac1_en : in std_ulogic_vector(0 to threads-1); + spr_cpl_iac2_en : in std_ulogic_vector(0 to threads-1); + spr_cpl_iac3_en : in std_ulogic_vector(0 to threads-1); + spr_cpl_iac4_en : in std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac1r_cmpr_async : in std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac2r_cmpr_async : in std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac1r_cmpr : in std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac2r_cmpr : in std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac3r_cmpr : in std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac4r_cmpr : in std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac1w_cmpr : in std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac2w_cmpr : in std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac3w_cmpr : in std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac4w_cmpr : in std_ulogic_vector(0 to threads-1); + + -- Interrupt Interface + cpl_spr_ex5_act : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_int : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_gint : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_cint : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_mcint : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_nia : out std_ulogic_vector(0 to eff_ifar*threads-1); + cpl_spr_ex5_esr : out std_ulogic_vector(0 to 17*threads-1); + cpl_spr_ex5_mcsr : out std_ulogic_vector(0 to 15*threads-1); + cpl_spr_ex5_dbsr : out std_ulogic_vector(0 to 19*threads-1); + cpl_spr_ex5_dear_save : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_dear_update_saved : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_dear_update : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_dbsr_update : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_esr_update : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_srr0_dec : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_force_gsrr : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_dbsr_ide : out std_ulogic_vector(0 to threads-1); + spr_cpl_dbsr_ide : in std_ulogic_vector(0 to threads-1); + + -- ALU Inputs + alu_cpl_ex1_eff_addr : in std_ulogic_vector(62 to 63); + + -- Machine Check Interrupts + mm_xu_local_snoop_reject : in std_ulogic_vector(0 to threads-1); + mm_xu_lru_par_err : in std_ulogic_vector(0 to threads-1); + mm_xu_tlb_par_err : in std_ulogic_vector(0 to threads-1); + mm_xu_tlb_multihit_err : in std_ulogic_vector(0 to threads-1); + lsu_xu_ex3_derat_par_err : in std_ulogic_vector(0 to threads-1); + lsu_xu_ex4_derat_par_err : in std_ulogic_vector(0 to threads-1); + lsu_xu_ex3_derat_multihit_err : in std_ulogic_vector(0 to threads-1); + lsu_xu_ex3_l2_uc_ecc_err : in std_ulogic_vector(0 to threads-1); + lsu_xu_ex3_ddir_par_err : in std_ulogic; + lsu_xu_ex4_n_lsu_ddmh_flush : in std_ulogic_vector(0 to 3); + lsu_xu_ex6_datc_par_err : in std_ulogic; + spr_cpl_external_mchk : in std_ulogic_vector(0 to threads-1); + + -- PC Errors + xu_pc_err_attention_instr : out std_ulogic_vector(0 to threads-1); + xu_pc_err_nia_miscmpr : out std_ulogic_vector(0 to threads-1); + xu_pc_err_debug_event : out std_ulogic_vector(0 to threads-1); + + -- Data Storage + lsu_xu_ex3_dsi : in std_ulogic_vector(0 to threads-1); + derat_xu_ex3_dsi : in std_ulogic_vector(0 to threads-1); + spr_cpl_ex3_ct_le : in std_ulogic_vector(0 to threads-1); + spr_cpl_ex3_ct_be : in std_ulogic_vector(0 to threads-1); + + -- Alignment + lsu_xu_ex3_align : in std_ulogic_vector(0 to threads-1); + + -- Program + spr_cpl_ex3_spr_illeg : in std_ulogic; + spr_cpl_ex3_spr_priv : in std_ulogic; + alu_cpl_ex3_trap_val : in std_ulogic; + + -- Hypv Privledge + spr_cpl_ex3_spr_hypv : in std_logic; + + -- Data TLB Miss + derat_xu_ex3_miss : in std_ulogic_vector(0 to threads-1); + + -- uCode + dec_cpl_ex2_is_ucode : in std_ulogic; + + -- RAM + pc_xu_ram_mode : in std_ulogic; + pc_xu_ram_thread : in std_ulogic_vector(0 to 1); + pc_xu_ram_execute : in std_ulogic; + xu_iu_ram_issue : out std_ulogic_vector(0 to threads-1); + xu_pc_ram_interrupt : out std_ulogic; + xu_pc_ram_done : out std_ulogic; + pc_xu_ram_flush_thread : in std_ulogic; + + -- Run State + cpl_spr_stop : out std_ulogic_vector(0 to threads-1); + xu_pc_stop_dbg_event : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_instr_cpl : out std_ulogic_vector(0 to threads-1); + spr_cpl_quiesce : in std_ulogic_vector(0 to threads-1); + cpl_spr_quiesce : out std_ulogic_vector(0 to threads-1); + spr_cpl_ex2_run_ctl_flush : in std_ulogic_vector(0 to threads-1); + + -- MMU Flushes + mm_xu_illeg_instr : in std_ulogic_vector(0 to threads-1); + mm_xu_tlb_miss : in std_ulogic_vector(0 to threads-1); + mm_xu_pt_fault : in std_ulogic_vector(0 to threads-1); + mm_xu_tlb_inelig : in std_ulogic_vector(0 to threads-1); + mm_xu_lrat_miss : in std_ulogic_vector(0 to threads-1); + mm_xu_hv_priv : in std_ulogic_vector(0 to threads-1); + mm_xu_esr_pt : in std_ulogic_vector(0 to threads-1); + mm_xu_esr_data : in std_ulogic_vector(0 to threads-1); + mm_xu_esr_epid : in std_ulogic_vector(0 to threads-1); + mm_xu_esr_st : in std_ulogic_vector(0 to threads-1); + mm_xu_hold_req : in std_ulogic_vector(0 to threads-1); + mm_xu_hold_done : in std_ulogic_vector(0 to threads-1); + xu_mm_hold_ack : out std_ulogic_vector(0 to threads-1); + mm_xu_eratmiss_done : in std_ulogic_vector(0 to threads-1); + mm_xu_ex3_flush_req : in std_ulogic_vector(0 to threads-1); + + -- LSU Flushes + lsu_xu_l2_ecc_err_flush : in std_ulogic_vector(0 to threads-1); + lsu_xu_datc_perr_recovery : in std_ulogic; + lsu_xu_ex3_dep_flush : in std_ulogic; + lsu_xu_ex3_n_flush_req : in std_ulogic; + lsu_xu_ex3_ldq_hit_flush : in std_ulogic; + lsu_xu_ex4_ldq_full_flush : in std_ulogic; + derat_xu_ex3_n_flush_req : in std_ulogic_vector(0 to threads-1); + lsu_xu_ex3_inval_align_2ucode : in std_ulogic; + lsu_xu_ex3_attr : in std_ulogic_vector(0 to 8); + lsu_xu_ex3_derat_vf : in std_ulogic; + + -- AXU Flushes + fu_xu_ex3_ap_int_req : in std_ulogic_vector(0 to threads-1); + fu_xu_ex3_trap : in std_ulogic_vector(0 to threads-1); + fu_xu_ex3_n_flush : in std_ulogic_vector(0 to threads-1); + fu_xu_ex3_np1_flush : in std_ulogic_vector(0 to threads-1); + fu_xu_ex3_flush2ucode : in std_ulogic_vector(0 to threads-1); + fu_xu_ex2_async_block : in std_ulogic_vector(0 to threads-1); + + -- IU Flushes + xu_iu_ex5_br_taken : out std_ulogic; + xu_iu_ex5_ifar : out std_ulogic_vector(62-eff_ifar to 61); + xu_iu_flush : out std_ulogic_vector(0 to threads-1); + xu_iu_iu0_flush_ifar : out std_ulogic_vector(0 to eff_ifar*threads-1); + xu_iu_uc_flush_ifar : out std_ulogic_vector(0 to uc_ifar*threads-1); + xu_iu_flush_2ucode : out std_ulogic_vector(0 to threads-1); + xu_iu_flush_2ucode_type : out std_ulogic_vector(0 to threads-1); + xu_iu_ucode_restart : out std_ulogic_vector(0 to threads-1); + xu_iu_ex5_ppc_cpl : out std_ulogic_vector(0 to threads-1); + + -- Flushes + xu_rf0_flush : out std_ulogic_vector(0 to threads-1); + xu_rf1_flush : out std_ulogic_vector(0 to threads-1); + xu_ex1_flush : out std_ulogic_vector(0 to threads-1); + xu_ex2_flush : out std_ulogic_vector(0 to threads-1); + xu_ex3_flush : out std_ulogic_vector(0 to threads-1); + xu_ex4_flush : out std_ulogic_vector(0 to threads-1); + xu_ex5_flush : out std_ulogic_vector(0 to threads-1); + + xu_n_is2_flush : out std_ulogic_vector(0 to threads-1); + xu_n_rf0_flush : out std_ulogic_vector(0 to threads-1); + xu_n_rf1_flush : out std_ulogic_vector(0 to threads-1); + xu_n_ex1_flush : out std_ulogic_vector(0 to threads-1); + xu_n_ex2_flush : out std_ulogic_vector(0 to threads-1); + xu_n_ex3_flush : out std_ulogic_vector(0 to threads-1); + xu_n_ex4_flush : out std_ulogic_vector(0 to threads-1); + xu_n_ex5_flush : out std_ulogic_vector(0 to threads-1); + + xu_s_rf1_flush : out std_ulogic_vector(0 to threads-1); + xu_s_ex1_flush : out std_ulogic_vector(0 to threads-1); + xu_s_ex2_flush : out std_ulogic_vector(0 to threads-1); + xu_s_ex3_flush : out std_ulogic_vector(0 to threads-1); + xu_s_ex4_flush : out std_ulogic_vector(0 to threads-1); + xu_s_ex5_flush : out std_ulogic_vector(0 to threads-1); + + xu_w_rf1_flush : out std_ulogic_vector(0 to threads-1); + xu_w_ex1_flush : out std_ulogic_vector(0 to threads-1); + xu_w_ex2_flush : out std_ulogic_vector(0 to threads-1); + xu_w_ex3_flush : out std_ulogic_vector(0 to threads-1); + xu_w_ex4_flush : out std_ulogic_vector(0 to threads-1); + xu_w_ex5_flush : out std_ulogic_vector(0 to threads-1); + + xu_lsu_ex4_val : out std_ulogic_vector(0 to threads-1); + xu_lsu_ex4_flush_local : out std_ulogic_vector(0 to threads-1); + xu_mm_ex4_flush : out std_ulogic_vector(0 to threads-1); + xu_mm_ex5_flush : out std_ulogic_vector(0 to threads-1); + xu_mm_ierat_flush : out std_ulogic_vector(0 to threads-1); + xu_mm_ierat_miss : out std_ulogic_vector(0 to threads-1); + + -- Barrier + xu_lsu_ex5_set_barr : out std_ulogic_vector(0 to threads-1); + cpl_fxa_ex5_set_barr : out std_ulogic_vector(0 to threads-1); + cpl_iu_set_barr_tid : out std_ulogic_vector(0 to threads-1); + + -- SPR Bus + cpl_byp_ex3_spr_rt : out std_ulogic_vector(64-regsize to 63); + mux_cpl_ex4_rt : in std_ulogic_vector(64-regsize to 63); + + -- SPR Bits + spr_bit_act : in std_ulogic; + cpl_spr_dbcr0_edm : out std_ulogic_vector(0 to threads-1); + spr_cpl_fp_precise : in std_ulogic_vector(0 to threads-1); + spr_xucr0_mddp : in std_ulogic; + spr_xucr0_mdcp : in std_ulogic; + spr_msr_de : in std_ulogic_vector(0 to threads-1); + spr_msr_spv : in std_ulogic_vector(0 to threads-1); + spr_msr_fp : in std_ulogic_vector(0 to threads-1); + spr_msr_pr : in std_ulogic_vector(0 to threads-1); + spr_msr_gs : in std_ulogic_vector(0 to threads-1); + spr_msr_me : in std_ulogic_vector(0 to threads-1); + spr_msr_cm : in std_ulogic_vector(0 to threads-1); + spr_msr_ucle : in std_ulogic_vector(0 to threads-1); + spr_msrp_uclep : in std_ulogic_vector(0 to threads-1); + spr_ccr2_notlb : in std_ulogic; + spr_ccr2_ucode_dis : in std_ulogic; + spr_ccr2_ap : in std_ulogic_vector(0 to threads-1); + spr_dbcr0_idm : in std_ulogic_vector(0 to threads-1); + spr_dbcr0_icmp : in std_ulogic_vector(0 to threads-1); + spr_dbcr0_brt : in std_ulogic_vector(0 to threads-1); + spr_dbcr0_trap : in std_ulogic_vector(0 to threads-1); + spr_dbcr0_ret : in std_ulogic_vector(0 to threads-1); + spr_dbcr0_irpt : in std_ulogic_vector(0 to threads-1); + spr_dbcr3_ivc : in std_ulogic_vector(0 to threads-1); + spr_epcr_dsigs : in std_ulogic_vector(0 to threads-1); + spr_epcr_isigs : in std_ulogic_vector(0 to threads-1); + spr_epcr_extgs : in std_ulogic_vector(0 to threads-1); + spr_epcr_dtlbgs : in std_ulogic_vector(0 to threads-1); + spr_epcr_itlbgs : in std_ulogic_vector(0 to threads-1); + spr_xucr4_div_barr_thres : out std_ulogic_vector(0 to 7); + spr_ccr0_we : in std_ulogic_vector(0 to threads-1); + spr_dbcr1_iac12m : in std_ulogic_vector(0 to threads-1); + spr_dbcr1_iac34m : in std_ulogic_vector(0 to threads-1); + spr_epcr_duvd : in std_ulogic_vector(0 to threads-1); + spr_xucr0_clkg_ctl : in std_ulogic_vector(2 to 2); + spr_xucr4_mmu_mchk : out std_ulogic; + + cpl_msr_gs : out std_ulogic_vector(0 to threads-1); + cpl_msr_pr : out std_ulogic_vector(0 to threads-1); + cpl_msr_fp : out std_ulogic_vector(0 to threads-1); + cpl_msr_spv : out std_ulogic_vector(0 to threads-1); + cpl_ccr2_ap : out std_ulogic_vector(0 to threads-1); + + -- Slow SPR Bus + mux_cpl_slowspr_flush : in std_ulogic_vector(0 to threads-1); + mux_cpl_slowspr_done : in std_ulogic_vector(0 to threads-1); + dec_cpl_ex1_is_slowspr_wr : in std_ulogic; + dec_cpl_ex3_ddmh_en : in std_ulogic; + dec_cpl_ex3_back_inv : in std_ulogic; + + -- Cache invalidate + xu_lsu_ici : out std_ulogic; + xu_lsu_dci : out std_ulogic; + + -- Perf + pc_xu_event_bus_enable : in std_ulogic; + cpl_perf_tx_events : out std_ulogic_vector(0 to 75); + spr_cpl_async_int : in std_ulogic_vector(0 to 3*threads-1); + xu_mm_ex5_perf_itlb : out std_ulogic_vector(0 to threads-1); + xu_mm_ex5_perf_dtlb : out std_ulogic_vector(0 to threads-1); + + -- Parity + spr_cpl_ex3_sprg_ce : in std_ulogic; + spr_cpl_ex3_sprg_ue : in std_ulogic; + iu_xu_ierat_ex2_flush_req : in std_ulogic_vector(0 to threads-1); + iu_xu_ierat_ex3_par_err : in std_ulogic_vector(0 to threads-1); + iu_xu_ierat_ex4_par_err : in std_ulogic_vector(0 to threads-1); + + -- Regfile Parity + fu_xu_ex3_regfile_err_det : in std_ulogic_vector(0 to threads-1); + xu_fu_regfile_seq_beg : out std_ulogic; + fu_xu_regfile_seq_end : in std_ulogic; + gpr_cpl_ex3_regfile_err_det : in std_ulogic; + cpl_gpr_regfile_seq_beg : out std_ulogic; + gpr_cpl_regfile_seq_end : in std_ulogic; + xu_pc_err_mcsr_summary : out std_ulogic_vector(0 to threads-1); + xu_pc_err_ditc_overrun : out std_ulogic; + xu_pc_err_local_snoop_reject : out std_ulogic; + xu_pc_err_tlb_lru_parity : out std_ulogic; + xu_pc_err_ext_mchk : out std_ulogic; + xu_pc_err_ierat_multihit : out std_ulogic; + xu_pc_err_derat_multihit : out std_ulogic; + xu_pc_err_tlb_multihit : out std_ulogic; + xu_pc_err_ierat_parity : out std_ulogic; + xu_pc_err_derat_parity : out std_ulogic; + xu_pc_err_tlb_parity : out std_ulogic; + xu_pc_err_mchk_disabled : out std_ulogic; + xu_pc_err_sprg_ue : out std_ulogic_vector(0 to threads-1); + + -- Debug + pc_xu_instr_trace_mode : in std_ulogic; + pc_xu_trace_bus_enable : in std_ulogic; + dec_cpl_rf1_instr_trace_val : in std_ulogic; + dec_cpl_rf1_instr_trace_type : in std_ulogic_vector(0 to 1); + dec_cpl_ex3_instr_trace_val : in std_ulogic; + cpl_dec_in_ucode : out std_ulogic_vector(0 to threads-1); + cpl_debug_mux_ctrls : in std_ulogic_vector(0 to 15); + cpl_debug_data_in : in std_ulogic_vector(0 to 87); + cpl_debug_data_out : out std_ulogic_vector(0 to 87); + cpl_trigger_data_in : in std_ulogic_vector(0 to 11); + cpl_trigger_data_out : out std_ulogic_vector(0 to 11); + fxa_cpl_debug : in std_ulogic_vector(0 to 272); + + -- Power + vdd : inout power_logic; + gnd : inout power_logic +); + +-- synopsys translate_off + +-- synopsys translate_on +end xuq_cpl; +architecture xuq_cpl of xuq_cpl is + +constant ivos : integer := 26; +constant ifar_repwr : integer := (eff_ifar+2)/8; +constant MSL : integer := 1274; + +constant PREVn : integer := 0; -- Exception Caused by previous instruction +constant BTAn : integer := 1; -- Branch Target Address Miscompare +constant DEPn : integer := 2; -- LSU Dependancy Flush +constant IMISSn : integer := 3; -- I-ERAT Miss +constant IMCHKn : integer := 4; -- Machine Check Interrupt +constant DBG0n : integer := 5; -- Debug Interrupt (IVC,IAC) +constant ITLBn : integer := 6; -- Instruction TLB Interrupt +constant ISTORn : integer := 7; -- Instruction Storage Interrupt +constant ILRATn : integer := 8; -- Instruction LRAT Interrupt +constant FPEn : integer := 9; -- Parity Error Flush +constant PROG0n : integer := 10; -- Program Interrupt (Illegal Op) +constant PROG1n : integer := 11; -- Program Interrupt (Privledeged Op) +constant UNAVAILn : integer := 12; -- FP, AP, or Vector Unavailable +constant PROG2n : integer := 13; -- Program Interrupt (Unimplemented Op) +constant PROG3n : integer := 14; -- Program Interrupt (FP or AP Enabled) +constant HPRIVn : integer := 15; -- Embedded Hypervisor Privilege Interrupt +constant PROG0An : integer := 16; -- Program Interrupt (tlbwe Illegal MAS settings) +constant DMCHKn : integer := 17; -- Machine Check Interrupt +constant DTLBn : integer := 18; -- Data TLB Interrupt +constant DMISSn : integer := 19; -- D-ERAT Miss +constant DSTORn : integer := 20; -- Data Storage Interrupt +constant ALIGNn : integer := 21; -- Alignment Interrupt +constant DLRATn : integer := 22; -- Data LRAT Interrupt +constant DBG1n : integer := 23; -- Debug Interrupt (DAC,RET,BRT,TRAP) +constant F2Un : integer := 24; -- N Flush to uCode +constant FwBSn : integer := 25; -- N Flush w/Barrier Set +constant Fn : integer := 26; -- N Flush +constant INSTRnp1 : integer := 27; -- RFI, SC, TRAP Instruction +constant MCHKnp1 : integer := 28; -- Machine Check Interrupt +constant GDBMCHKnp1 : integer := 29; -- Guest Processor Doorbell Machine Check Interrupt +constant DBG3np1 : integer := 30; -- Async Debug Interrupt (UDE,IDE,IRPT) +constant CRITnp1 : integer := 31; -- Critical External Input Interrupt +constant WDOGnp1 : integer := 32; -- Watchdog Interrupt +constant CDBELLnp1 : integer := 33; -- Processor Doorbell Critical Interrupt +constant GCDBELLnp1 : integer := 34; -- Guest Processor Doorbell Critical Interrupt +constant EXTnp1 : integer := 35; -- External Input Interrupt +constant FITnp1 : integer := 36; -- Fixed Interval Timer Interrupt +constant DECnp1 : integer := 37; -- Decrementer Interrupt +constant DBELLnp1 : integer := 38; -- Processor Doorbell +constant GDBELLnp1 : integer := 39; -- Guest Processor Doorbell +constant UDECnp1 : integer := 40; -- User Decrementer +constant PERFnp1 : integer := 41; -- Performance Monitor +constant Fnp1 : integer := 42; -- NP1 Flush +constant TRAP : integer := 0; +constant SC : integer := 1; +constant RFI : integer := 2; +constant FP : integer := 0; +constant AP : integer := 1; +constant VEC : integer := 2; +constant DLK : integer := 0; +constant PT : integer := 1; +constant VF : integer := 2; +constant TLBI : integer := 3; +constant RW : integer := 4; +constant UCT : integer := 5; +constant APENA : integer := 0; +constant FPENA : integer := 1; +-- Types +type TID_ARR is array (0 to ifar_repwr-1) of std_ulogic_vector(0 to threads-1); +type DAC is array (1 to 4) of std_ulogic_vector(0 to threads-1); +type DAC_A is array (1 to 2) of std_ulogic_vector(0 to threads-1); +type ARY3 is array (0 to threads-1) of std_ulogic_vector(0 to 2); +type ARY4 is array (0 to threads-1) of std_ulogic_vector(0 to 3); +type ARY5 is array (0 to threads-1) of std_ulogic_vector(0 to 4); +type ARY6 is array (0 to threads-1) of std_ulogic_vector(0 to 5); +type ARY7 is array (0 to threads-1) of std_ulogic_vector(0 to 6); +type ARY9 is array (0 to threads-1) of std_ulogic_vector(0 to 8); +type ARY64 is array (0 to threads-1) of std_ulogic_vector(0 to 63); +type ARY_FPRI is array (0 to threads-1) of std_ulogic_vector(0 to Fnp1); +type ARY_IFAR is array (0 to threads-1) of std_ulogic_vector(0 to 61); +type ARY_BLOCK is array (0 to threads-1) of std_ulogic_vector(1 to 7); +subtype IFAR is std_ulogic_vector(62-eff_ifar to 61); +subtype IFAR_UC is std_ulogic_vector(62-uc_ifar to 61); +subtype TID is std_ulogic_vector(0 to threads-1); +-- Latches +signal is2_flush_q : std_ulogic_vector(0 to threads-1); -- input=>any_flush , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal rf0_flush_q : std_ulogic_vector(0 to threads-1); -- input=>is2_flush , act=>exx_flush_inf_act , scan=>Y, sleep=>N, needs_sreset=>1 +signal rf1_flush_q : std_ulogic_vector(0 to threads-1); -- input=>rf0_flush , act=>exx_flush_inf_act , scan=>Y, sleep=>N, needs_sreset=>1 +signal rf1_tid_q : std_ulogic_vector(0 to threads-1); -- input=>dec_cpl_rf0_tid , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex1_axu_act_q : std_ulogic_vector(0 to threads-1); -- input=>fu_xu_rf1_act , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex1_byte_rev_q, rf1_byte_rev : std_ulogic; -- input=>rf1_byte_rev , act=>exx_act(0) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex1_flush_q : std_ulogic_vector(0 to threads-1); -- input=>rf1_flush , act=>exx_flush_inf_act , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex1_is_any_ldstmw_q, rf1_is_any_ldstmw : std_ulogic; -- input=>rf1_is_any_ldstmw , act=>exx_act(0) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex1_is_attn_q, rf1_is_attn : std_ulogic; -- input=>rf1_is_attn , act=>exx_act(0) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex1_is_dci_q, ex1_is_dci_d : std_ulogic; -- input=>ex1_is_dci_d , act=>exx_act(0) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex1_is_dlock_q, rf1_is_dlock : std_ulogic; -- input=>rf1_is_dlock , act=>exx_act(0) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex1_is_ehpriv_q, rf1_is_ehpriv : std_ulogic; -- input=>rf1_is_ehpriv , act=>exx_act(0) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex1_is_erativax_q, rf1_is_erativax : std_ulogic; -- input=>rf1_is_erativax , act=>exx_act(0) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex1_is_ici_q, ex1_is_ici_d : std_ulogic; -- input=>ex1_is_ici_d , act=>exx_act(0) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex1_is_icswx_q, rf1_is_icswx : std_ulogic; -- input=>rf1_is_icswx , act=>exx_act(0) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex1_is_ilock_q, rf1_is_ilock : std_ulogic; -- input=>rf1_is_ilock , act=>exx_act(0) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex1_is_isync_q, rf1_is_isync : std_ulogic; -- input=>rf1_is_isync , act=>exx_act(0) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex1_is_mfspr_q, rf1_is_mfspr : std_ulogic; -- input=>rf1_is_mfspr , act=>exx_act(0) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex1_is_mtmsr_q, rf1_is_mtmsr : std_ulogic; -- input=>rf1_is_mtmsr , act=>exx_act(0) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex1_is_mtspr_q, rf1_is_mtspr : std_ulogic; -- input=>rf1_is_mtspr , act=>exx_act(0) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex1_is_rfci_q, rf1_is_rfci : std_ulogic; -- input=>rf1_is_rfci , act=>exx_act(0) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex1_is_rfgi_q, rf1_is_rfgi : std_ulogic; -- input=>rf1_is_rfgi , act=>exx_act(0) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex1_is_rfi_q, rf1_is_rfi : std_ulogic; -- input=>rf1_is_rfi , act=>exx_act(0) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex1_is_rfmci_q, rf1_is_rfmci : std_ulogic; -- input=>rf1_is_rfmci , act=>exx_act(0) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex1_is_sc_q, rf1_is_sc : std_ulogic; -- input=>rf1_is_sc , act=>exx_act(0) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex1_is_tlbivax_q, rf1_is_tlbivax : std_ulogic; -- input=>rf1_is_tlbivax , act=>exx_act(0) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex1_is_wrtee_q, rf1_is_wrtee : std_ulogic; -- input=>rf1_is_wrtee , act=>exx_act(0) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex1_is_wrteei_q, rf1_is_wrteei : std_ulogic; -- input=>rf1_is_wrteei , act=>exx_act(0) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex1_is_mtxucr0_q, rf1_is_mtxucr0 : std_ulogic; -- input=>rf1_is_mtxucr0 , act=>exx_act(0) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex1_is_tlbwe_q, rf1_is_tlbwe : std_ulogic; -- input=>rf1_is_tlbwe , act=>exx_act(0) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex1_sc_lev_q, rf1_sc_lev : std_ulogic; -- input=>rf1_sc_lev , act=>exx_act(0) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex1_ucode_val_q : std_ulogic_vector(0 to threads-1); -- input=>rf1_ucode_val , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex1_xu_val_q : std_ulogic_vector(0 to threads-1); -- input=>rf1_xu_val , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex2_axu_act_q : std_ulogic_vector(0 to threads-1); -- input=>ex1_axu_act_q , act=>tiup , scan=>N, sleep=>N, needs_sreset=>1 +signal ex2_any_wrtee_q, ex2_any_wrtee_d : std_ulogic; -- input=>ex2_any_wrtee_d , act=>exx_act(1) , scan=>N, sleep=>N, needs_sreset=>0 +signal ex2_br_taken_q : std_ulogic; -- input=>ex1_br_taken , act=>exx_act(1) , scan=>N, sleep=>N, needs_sreset=>0 +signal ex2_br_update_q : std_ulogic; -- input=>ex1_br_update , act=>exx_act(1) , scan=>N, sleep=>N, needs_sreset=>0 +signal ex2_byte_rev_q : std_ulogic; -- input=>ex1_byte_rev_q , act=>exx_act(1) , scan=>N, sleep=>N, needs_sreset=>0 +signal ex2_ctr_dec_update_q : std_ulogic; -- input=>ex1_ctr_dec_update , act=>exx_act(1) , scan=>N, sleep=>N, needs_sreset=>0 +signal ex2_epid_instr_q : std_ulogic; -- input=>dec_cpl_ex1_epid_instr , act=>exx_act(1) , scan=>N, sleep=>N, needs_sreset=>0 +signal ex2_flush_q : std_ulogic_vector(0 to threads-1); -- input=>ex1_flush , act=>exx_flush_inf_act , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex2_is_attn_q : std_ulogic; -- input=>ex1_is_attn_q , act=>exx_act(1) , scan=>N, sleep=>N, needs_sreset=>0 +signal ex2_is_dci_q : std_ulogic; -- input=>ex1_is_dci_q , act=>exx_act(1) , scan=>N, sleep=>N, needs_sreset=>0 +signal ex2_is_dlock_q : std_ulogic; -- input=>ex1_is_dlock_q , act=>exx_act(1) , scan=>N, sleep=>N, needs_sreset=>0 +signal ex2_is_ehpriv_q : std_ulogic; -- input=>ex1_is_ehpriv_q , act=>exx_act(1) , scan=>N, sleep=>N, needs_sreset=>0 +signal ex2_is_erativax_q : std_ulogic; -- input=>ex1_is_erativax_q , act=>exx_act(1) , scan=>N, sleep=>N, needs_sreset=>0 +signal ex2_is_ici_q : std_ulogic; -- input=>ex1_is_ici_q , act=>exx_act(1) , scan=>N, sleep=>N, needs_sreset=>0 +signal ex2_is_icswx_q : std_ulogic; -- input=>ex1_is_icswx_q , act=>exx_act(1) , scan=>N, sleep=>N, needs_sreset=>0 +signal ex2_is_ilock_q : std_ulogic; -- input=>ex1_is_ilock_q , act=>exx_act(1) , scan=>N, sleep=>N, needs_sreset=>0 +signal ex2_is_isync_q : std_ulogic; -- input=>ex1_is_isync_q , act=>exx_act(1) , scan=>N, sleep=>N, needs_sreset=>0 +signal ex2_is_mtmsr_q : std_ulogic; -- input=>ex1_is_mtmsr_q , act=>exx_act(1) , scan=>N, sleep=>N, needs_sreset=>0 +signal ex2_is_rfci_q : std_ulogic; -- input=>ex1_is_rfci_q , act=>exx_act(1) , scan=>N, sleep=>N, needs_sreset=>0 +signal ex2_is_rfgi_q : std_ulogic; -- input=>ex1_is_rfgi_q , act=>exx_act(1) , scan=>N, sleep=>N, needs_sreset=>0 +signal ex2_is_rfi_q : std_ulogic; -- input=>ex1_is_rfi_q , act=>exx_act(1) , scan=>N, sleep=>N, needs_sreset=>0 +signal ex2_is_rfmci_q : std_ulogic; -- input=>ex1_is_rfmci_q , act=>exx_act(1) , scan=>N, sleep=>N, needs_sreset=>0 +signal ex2_is_sc_q : std_ulogic; -- input=>ex1_is_sc_q , act=>exx_act(1) , scan=>N, sleep=>N, needs_sreset=>0 +signal ex2_is_slowspr_wr_q : std_ulogic; -- input=>dec_cpl_ex1_is_slowspr_wr , act=>exx_act(1) , scan=>N, sleep=>N, needs_sreset=>0 +signal ex2_is_tlbivax_q : std_ulogic; -- input=>ex1_is_tlbivax_q , act=>exx_act(1) , scan=>N, sleep=>N, needs_sreset=>0 +signal ex2_is_tlbwe_q : std_ulogic; -- input=>ex1_is_tlbwe_q , act=>exx_act(1) , scan=>N, sleep=>N, needs_sreset=>0 +signal ex2_lr_update_q : std_ulogic; -- input=>ex1_lr_update , act=>exx_act(1) , scan=>N, sleep=>N, needs_sreset=>0 +signal ex2_n_align_int_q, ex2_n_align_int_d : std_ulogic; -- input=>ex2_n_align_int_d , act=>exx_act(1) , scan=>N, sleep=>N, needs_sreset=>0 +signal ex2_sc_lev_q : std_ulogic; -- input=>ex1_sc_lev_q , act=>exx_act(1) , scan=>N, sleep=>N, needs_sreset=>0 +signal ex2_taken_bclr_q : std_ulogic; -- input=>ex1_taken_bclr , act=>exx_act(1) , scan=>N, sleep=>N, needs_sreset=>0 +signal ex2_ucode_val_q : std_ulogic_vector(0 to threads-1); -- input=>ex1_ucode_val , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex2_xu_val_q : std_ulogic_vector(0 to threads-1); -- input=>ex1_xu_val , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex2_is_mtxucr0_q : std_ulogic; -- input=>ex1_is_mtxucr0_q , act=>exx_act(1) , scan=>N, sleep=>N, needs_sreset=>0 +signal ex3_async_int_block_q, ex3_async_int_block_d : std_ulogic_vector(0 to threads-1); -- input=>ex3_async_int_block_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex3_axu_instr_match_q : std_ulogic_vector(0 to threads-1); -- input=>fu_xu_ex2_instr_match , act=>ex2_axu_act_q , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex3_axu_instr_type_q : std_ulogic_vector(0 to 3*threads-1); -- input=>fu_xu_ex2_instr_type , act=>ex2_axu_act_q , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex3_axu_is_ucode_q : std_ulogic_vector(0 to threads-1); -- input=>fu_xu_ex2_is_ucode , act=>ex2_axu_act_q , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex3_axu_val_q : std_ulogic_vector(0 to threads-1); -- input=>ex2_axu_val , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex3_br_flush_ifar_q : std_ulogic_vector(62-eff_ifar to 61); -- input=>ex2_br_flush_ifar , act=>exx_act(2) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex3_br_taken_q : std_ulogic; -- input=>ex2_br_taken_q , act=>exx_act(2) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex3_br_update_q : std_ulogic; -- input=>ex2_br_update_q , act=>exx_act(2) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex3_byte_rev_q : std_ulogic; -- input=>ex2_byte_rev_q , act=>exx_act(2) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex3_ctr_dec_update_q : std_ulogic; -- input=>ex2_ctr_dec_update_q , act=>exx_act(2) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex3_div_coll_q, ex3_div_coll_d : std_ulogic_vector(0 to threads-1); -- input=>ex3_div_coll_d , act=>exx_act(2) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex3_epid_instr_q : std_ulogic; -- input=>ex2_epid_instr_q , act=>exx_act(2) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex3_flush_q : std_ulogic_vector(0 to threads-1); -- input=>ex2_flush , act=>exx_flush_inf_act , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex3_ierat_flush_req_q : std_ulogic_vector(0 to threads-1); -- input=>iu_xu_ierat_ex2_flush_req , act=>exx_act(2) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex3_illegal_op_q : std_ulogic; -- input=>dec_cpl_ex2_illegal_op , act=>exx_act(2) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex3_is_any_load_dac_q : std_ulogic; -- input=>dec_cpl_ex2_is_any_load_dac, act=>exx_act(2) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex3_is_any_store_dac_q : std_ulogic; --input=>dec_cpl_ex2_is_any_store_dac, act=>exx_act(2) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex3_is_attn_q : std_ulogic; -- input=>ex2_is_attn_q , act=>exx_act(2) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex3_is_dci_q : std_ulogic; -- input=>ex2_is_dci_q , act=>exx_act(2) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex3_is_dlock_q : std_ulogic; -- input=>ex2_is_dlock_q , act=>exx_act(2) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex3_is_ehpriv_q : std_ulogic; -- input=>ex2_is_ehpriv_q , act=>exx_act(2) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex3_is_ici_q : std_ulogic; -- input=>ex2_is_ici_q , act=>exx_act(2) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex3_is_icswx_q : std_ulogic; -- input=>ex2_is_icswx_q , act=>exx_act(2) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex3_is_ilock_q : std_ulogic; -- input=>ex2_is_ilock_q , act=>exx_act(2) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex3_is_isync_q : std_ulogic; -- input=>ex2_is_isync_q , act=>exx_act(2) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex3_is_mtmsr_q : std_ulogic; -- input=>ex2_is_mtmsr_q , act=>exx_act(2) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex3_is_rfci_q : std_ulogic; -- input=>ex2_is_rfci_q , act=>exx_act(2) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex3_is_rfgi_q : std_ulogic; -- input=>ex2_is_rfgi_q , act=>exx_act(2) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex3_is_rfi_q : std_ulogic; -- input=>ex2_is_rfi_q , act=>exx_act(2) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex3_is_rfmci_q : std_ulogic; -- input=>ex2_is_rfmci_q , act=>exx_act(2) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex3_is_sc_q : std_ulogic; -- input=>ex2_is_sc_q , act=>exx_act(2) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex3_is_tlbwe_q : std_ulogic; -- input=>ex2_is_tlbwe_q , act=>exx_act(2) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex3_is_slowspr_wr_q : std_ulogic; -- input=>ex2_is_slowspr_wr_q , act=>exx_act(2) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex3_iu_error_q, ex3_iu_error_d : std_ulogic_vector(1 to 7); -- input=>ex3_iu_error_d , act=>exx_act(2) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex3_lr_update_q : std_ulogic; -- input=>ex2_lr_update_q , act=>exx_act(2) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex3_lrat_miss_q : std_ulogic_vector(0 to threads-1); -- input=>mm_xu_lrat_miss , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex3_mmu_esr_data_q : std_ulogic_vector(0 to threads-1); -- input=>mm_xu_esr_data , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex3_mmu_esr_epid_q : std_ulogic_vector(0 to threads-1); -- input=>mm_xu_esr_epid , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex3_mmu_esr_pt_q : std_ulogic_vector(0 to threads-1); -- input=>mm_xu_esr_pt , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex3_mmu_esr_st_q : std_ulogic_vector(0 to threads-1); -- input=>mm_xu_esr_st , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex3_mmu_hv_priv_q : std_ulogic_vector(0 to threads-1); -- input=>mm_xu_hv_priv , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex3_mtiar_q, ex2_mtiar : std_ulogic; -- input=>ex2_mtiar , act=>exx_act(2) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex3_n_align_int_q : std_ulogic; -- input=>ex2_n_align_int_q , act=>exx_act(2) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex3_n_dcpe_flush_q, ex3_n_dcpe_flush_d : std_ulogic_vector(0 to threads-1); -- input=>ex3_n_dcpe_flush_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex3_n_l2_ecc_err_flush_q : std_ulogic_vector(0 to threads-1); -- input=>lsu_xu_l2_ecc_err_flush , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex3_np1_run_ctl_flush_q : std_ulogic_vector(0 to threads-1); -- input=>spr_cpl_ex2_run_ctl_flush , act=>exx_act(2) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex3_sc_lev_q : std_ulogic; -- input=>ex2_sc_lev_q , act=>exx_act(2) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex3_taken_bclr_q : std_ulogic; -- input=>ex2_taken_bclr_q , act=>exx_act(2) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex3_tlb_inelig_q : std_ulogic_vector(0 to threads-1); -- input=>mm_xu_tlb_inelig , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex3_tlb_local_snoop_reject_q : std_ulogic_vector(0 to threads-1); -- input=>mm_xu_local_snoop_reject , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex3_tlb_lru_par_err_q : std_ulogic_vector(0 to threads-1); -- input=>mm_xu_lru_par_err , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex3_tlb_illeg_q : std_ulogic_vector(0 to threads-1); -- input=>mm_xu_illeg_instr , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex3_tlb_miss_q : std_ulogic_vector(0 to threads-1); -- input=>mm_xu_tlb_miss , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex3_tlb_multihit_err_q : std_ulogic_vector(0 to threads-1); -- input=>mm_xu_tlb_multihit_err , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex3_tlb_par_err_q : std_ulogic_vector(0 to threads-1); -- input=>mm_xu_tlb_par_err , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex3_tlb_pt_fault_q : std_ulogic_vector(0 to threads-1); -- input=>mm_xu_pt_fault , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex3_ucode_val_q : std_ulogic_vector(0 to threads-1); -- input=>ex2_ucode_val , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex3_xu_instr_match_q : std_ulogic; -- input=>dec_cpl_ex2_match , act=>exx_act(2) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex3_xu_is_ucode_q : std_ulogic; -- input=>dec_cpl_ex2_is_ucode , act=>exx_act(2) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex3_xu_val_q : std_ulogic_vector(0 to threads-1); -- input=>ex2_xu_val , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex3_axu_async_block_q : std_ulogic_vector(0 to threads-1); -- input=>fu_xu_ex2_async_block , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex3_is_mtxucr0_q : std_ulogic; -- input=>ex2_is_mtxucr0_q , act=>exx_act(2) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex3_np1_instr_flush_q, ex3_np1_instr_flush_d : std_ulogic; -- input=>ex3_np1_instr_flush_d , act=>exx_act(2) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex4_apena_prog_int_q, ex3_n_apena_prog_int : std_ulogic_vector(0 to threads-1); -- input=>ex3_n_apena_prog_int , act=>exx_act(3) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex4_axu_is_ucode_q : std_ulogic_vector(0 to threads-1); -- input=>ex3_axu_is_ucode_q , act=>exx_act(3) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex4_axu_trap_q : std_ulogic_vector(0 to threads-1); -- input=>fu_xu_ex3_trap , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_axu_val_q : std_ulogic_vector(0 to threads-1); -- input=>ex3_axu_val , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_base_int_block_q : std_ulogic_vector(0 to threads-1); -- input=>ex3_base_int_block , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_br_flush_ifar_q : std_ulogic_vector(62-eff_ifar to 61); -- input=>ex3_br_flush_ifar_q , act=>exx_act(3) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex4_br_taken_q : std_ulogic; -- input=>ex3_br_taken_q , act=>exx_act(3) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex4_br_update_q : std_ulogic; -- input=>ex3_br_update_q , act=>exx_act(3) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex4_byte_rev_q : std_ulogic; -- input=>ex3_byte_rev_q , act=>exx_act(3) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex4_ctr_dec_update_q : std_ulogic; -- input=>ex3_ctr_dec_update_q , act=>exx_act(3) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex4_debug_flush_en_q, ex4_debug_flush_en_d : std_ulogic_vector(0 to threads-1); -- input=>ex4_debug_flush_en_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_debug_int_en_q, ex3_debug_int_en : std_ulogic_vector(0 to threads-1); -- input=>ex3_debug_int_en , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_flush_q : std_ulogic_vector(0 to threads-1); -- input=>ex3_flush , act=>exx_flush_inf_act , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_fpena_prog_int_q, ex3_n_fpena_prog_int : std_ulogic_vector(0 to threads-1); -- input=>ex3_n_fpena_prog_int , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_iac1_cmpr_q, ex3_iac1_cmpr : std_ulogic_vector(0 to threads-1); -- input=>ex3_iac1_cmpr , act=>exx_act(3) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex4_iac2_cmpr_q, ex3_iac2_cmpr : std_ulogic_vector(0 to threads-1); -- input=>ex3_iac2_cmpr , act=>exx_act(3) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex4_iac3_cmpr_q, ex3_iac3_cmpr : std_ulogic_vector(0 to threads-1); -- input=>ex3_iac3_cmpr , act=>exx_act(3) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex4_iac4_cmpr_q, ex3_iac4_cmpr : std_ulogic_vector(0 to threads-1); -- input=>ex3_iac4_cmpr , act=>exx_act(3) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex4_instr_cpl_q, ex4_instr_cpl_d : std_ulogic_vector(0 to threads-1); -- input=>ex4_instr_cpl_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_is_any_load_dac_q : std_ulogic; -- input=>ex3_is_any_load_dac_q , act=>exx_act(3) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex4_is_any_store_dac_q : std_ulogic; -- input=>ex3_is_any_store_dac_q , act=>exx_act(3) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex4_is_attn_q : std_ulogic; -- input=>ex3_is_attn_q , act=>exx_act(3) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex4_is_dci_q : std_ulogic; -- input=>ex3_is_dci_q , act=>exx_act(3) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex4_is_ehpriv_q : std_ulogic; -- input=>ex3_is_ehpriv_q , act=>exx_act(3) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex4_is_ici_q : std_ulogic; -- input=>ex3_is_ici_q , act=>exx_act(3) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex4_is_isync_q : std_ulogic; -- input=>ex3_is_isync_q , act=>exx_act(3) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex4_is_mtmsr_q : std_ulogic; -- input=>ex3_is_mtmsr_q , act=>exx_act(3) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex4_is_tlbwe_q : std_ulogic; -- input=>ex3_is_tlbwe_q , act=>exx_act(3) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex4_is_slowspr_wr_q : std_ulogic; -- input=>ex3_is_slowspr_wr_q , act=>exx_act(3) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex4_lr_update_q : std_ulogic; -- input=>ex3_lr_update_q , act=>exx_act(3) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex4_mcsr_q, ex4_mcsr_d : std_ulogic_vector(0 to 14*threads-1); -- input=>ex4_mcsr_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_mem_attr_q : std_ulogic_vector(lsu_xu_ex3_attr'range); -- input=>lsu_xu_ex3_attr , act=>exx_act(3) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex4_mmu_esr_data_q : std_ulogic_vector(0 to threads-1); -- input=>ex3_mmu_esr_data_q , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_mmu_esr_epid_q : std_ulogic_vector(0 to threads-1); -- input=>ex3_mmu_esr_epid_q , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_mmu_esr_pt_q : std_ulogic_vector(0 to threads-1); -- input=>ex3_mmu_esr_pt_q , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_mmu_esr_st_q : std_ulogic_vector(0 to threads-1); -- input=>ex3_mmu_esr_st_q , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_mmu_esr_val_q, ex4_mmu_esr_val_d : std_ulogic_vector(0 to threads-1); -- input=>ex4_mmu_esr_val_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_mmu_hold_val_q, ex3_mmu_hold_val : std_ulogic_vector(0 to threads-1); -- input=>ex3_mmu_hold_val , act=>tiup , scan=>Y, sleep=>Y, needs_sreset=>1 +signal ex4_mtdp_nr_q : std_ulogic; -- input=>dec_cpl_ex3_mtdp_nr , act=>exx_act(3) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex4_mtiar_q : std_ulogic; -- input=>ex3_mtiar_q , act=>exx_act(3) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex4_n_2ucode_flush_q, ex3_n_2ucode_flush : std_ulogic_vector(0 to threads-1); -- input=>ex3_n_2ucode_flush , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_n_align_int_q, ex3_n_align_int : std_ulogic_vector(0 to threads-1); -- input=>ex3_n_align_int , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_n_any_hpriv_int_q, ex4_n_any_hpriv_int_d : std_ulogic_vector(0 to threads-1); -- input=>ex4_n_any_hpriv_int_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_n_any_unavail_int_q, ex3_n_any_unavail_int : std_ulogic_vector(0 to threads-1); -- input=>ex3_n_any_unavail_int , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_n_ap_unavail_int_q, ex3_n_ap_unavail_int : std_ulogic_vector(0 to threads-1); -- input=>ex3_n_ap_unavail_int , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_n_barr_flush_q, ex3_n_barr_flush : std_ulogic_vector(0 to threads-1); -- input=>ex3_n_barr_flush , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_n_bclr_ta_miscmpr_flush_q,ex3_n_bclr_ta_miscmpr_flush : std_ulogic_vector(0 to threads-1); -- input=>ex3_n_bclr_ta_miscmpr_flush, act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_n_brt_dbg_cint_q, ex3_n_brt_dbg_cint : std_ulogic_vector(0 to threads-1); -- input=>ex3_n_brt_dbg_cint , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_n_dac_dbg_cint_q, ex3_n_dac_dbg_cint : std_ulogic_vector(0 to threads-1); -- input=>ex3_n_dac_dbg_cint , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_n_ddmh_mchk_en_q, ex4_n_ddmh_mchk_en_d : std_ulogic_vector(0 to threads-1); -- input=>ex4_n_ddmh_mchk_en_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_n_dep_flush_q, ex3_n_dep_flush : std_ulogic_vector(0 to threads-1); -- input=>ex3_n_dep_flush , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_n_deratre_par_mchk_mcint_q,ex3_n_deratre_par_mchk_mcint : std_ulogic_vector(0 to threads-1); -- input=>ex3_n_deratre_par_mchk_mcint, act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_n_dlk0_dstor_int_q, ex3_n_dlk0_dstor_int : std_ulogic_vector(0 to threads-1); -- input=>ex3_n_dlk0_dstor_int , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_n_dlk1_dstor_int_q, ex3_n_dlk1_dstor_int : std_ulogic_vector(0 to threads-1); -- input=>ex3_n_dlk1_dstor_int , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_n_dlrat_int_q, ex3_n_dlrat_int : std_ulogic_vector(0 to threads-1); -- input=>ex3_n_dlrat_int , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_n_dmchk_mcint_q, ex3_n_dmchk_mcint : std_ulogic_vector(0 to threads-1); -- input=>ex3_n_dmchk_mcint , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_n_dmiss_flush_q, ex3_n_dmiss_flush : std_ulogic_vector(0 to threads-1); -- input=>ex3_n_dmiss_flush , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_n_dstor_int_q, ex3_n_dstor_int : std_ulogic_vector(0 to threads-1); -- input=>ex3_n_dstor_int , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_n_dtlb_int_q, ex3_n_dtlb_int : std_ulogic_vector(0 to threads-1); -- input=>ex3_n_dtlb_int , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_n_ena_prog_int_q, ex3_n_ena_prog_int : std_ulogic_vector(0 to threads-1); -- input=>ex3_n_ena_prog_int , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_n_flush_q, ex3_n_flush : std_ulogic_vector(0 to threads-1); -- input=>ex3_n_flush , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_n_pe_flush_q, ex3_n_pe_flush : std_ulogic_vector(0 to threads-1); -- input=>ex3_n_pe_flush , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_n_tlb_mchk_flush_q, ex3_n_tlb_mchk_flush : std_ulogic_vector(0 to threads-1); -- input=>ex3_n_tlb_mchk_flush , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_n_fp_unavail_int_q, ex3_n_fp_unavail_int : std_ulogic_vector(0 to threads-1); -- input=>ex3_n_fp_unavail_int , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_n_fu_rfpe_flush_q, ex4_n_fu_rfpe_flush_d : std_ulogic_vector(0 to threads-1); -- input=>ex4_n_fu_rfpe_flush_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_n_iac_dbg_cint_q, ex3_n_iac_dbg_cint : std_ulogic_vector(0 to threads-1); -- input=>ex3_n_iac_dbg_cint , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_n_ieratre_par_mchk_mcint_q,ex3_n_ieratre_par_mchk_mcint : std_ulogic_vector(0 to threads-1); -- input=>ex3_n_ieratre_par_mchk_mcint, act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_n_ilrat_int_q, ex3_n_ilrat_int : std_ulogic_vector(0 to threads-1); -- input=>ex3_n_ilrat_int , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_n_imchk_mcint_q, ex3_n_imchk_mcint : std_ulogic_vector(0 to threads-1); -- input=>ex3_n_imchk_mcint , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_n_imiss_flush_q, ex3_n_imiss_flush : std_ulogic_vector(0 to threads-1); -- input=>ex3_n_imiss_flush , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_n_instr_dbg_cint_q, ex3_n_instr_dbg_cint : std_ulogic_vector(0 to threads-1); -- input=>ex3_n_instr_dbg_cint , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_n_istor_int_q, ex3_n_istor_int : std_ulogic_vector(0 to threads-1); -- input=>ex3_n_istor_int , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_n_itlb_int_q, ex3_n_itlb_int : std_ulogic_vector(0 to threads-1); -- input=>ex3_n_itlb_int , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_n_ivc_dbg_cint_q, ex3_n_ivc_dbg_cint : std_ulogic_vector(0 to threads-1); -- input=>ex3_n_ivc_dbg_cint , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_n_ivc_dbg_match_q, ex3_n_ivc_dbg_match : std_ulogic_vector(0 to threads-1); -- input=>ex3_n_ivc_dbg_match , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_n_ldq_hit_flush_q, ex3_n_ldq_hit_flush : std_ulogic_vector(0 to threads-1); -- input=>ex3_n_ldq_hit_flush , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_n_lsu_ddmh_flush_en_q, ex4_n_lsu_ddmh_flush_en_d : std_ulogic_vector(0 to threads-1); -- input=>ex4_n_lsu_ddmh_flush_en_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_n_lsu_flush_q, ex3_n_lsu_flush : std_ulogic_vector(0 to threads-1); -- input=>ex3_n_lsu_flush , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_n_memattr_miscmpr_flush_q,ex3_n_memattr_miscmpr_flush : std_ulogic_vector(0 to threads-1); -- input=>ex3_n_memattr_miscmpr_flush, act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_n_mmu_hpriv_int_q, ex3_n_mmu_hpriv_int : std_ulogic_vector(0 to threads-1); -- input=>ex3_n_mmu_hpriv_int , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_n_pil_prog_int_q, ex3_n_pil_prog_int : std_ulogic_vector(0 to threads-1); -- input=>ex3_n_pil_prog_int , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_n_ppr_prog_int_q, ex3_n_ppr_prog_int : std_ulogic_vector(0 to threads-1); -- input=>ex3_n_ppr_prog_int , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_n_ptemiss_dlrat_int_q, ex3_n_ptemiss_dlrat_int : std_ulogic_vector(0 to threads-1); -- input=>ex3_n_ptemiss_dlrat_int , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_n_puo_prog_int_q, ex3_n_puo_prog_int : std_ulogic_vector(0 to threads-1); -- input=>ex3_n_puo_prog_int , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_n_ret_dbg_cint_q, ex3_n_ret_dbg_cint : std_ulogic_vector(0 to threads-1); -- input=>ex3_n_ret_dbg_cint , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_n_thrctl_stop_flush_q, ex3_n_thrctl_stop_flush : std_ulogic_vector(0 to threads-1); -- input=>ex3_n_thrctl_stop_flush , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_n_tlbwemiss_dlrat_int_q,ex3_n_tlbwemiss_dlrat_int : std_ulogic_vector(0 to threads-1); -- input=>ex3_n_tlbwemiss_dlrat_int , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_n_tlbwe_pil_prog_int_q,ex3_n_tlbwe_pil_prog_int : std_ulogic_vector(0 to threads-1); -- input=>ex3_n_tlbwe_pil_prog_int , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_n_trap_dbg_cint_q, ex3_n_trap_dbg_cint : std_ulogic_vector(0 to threads-1); -- input=>ex3_n_trap_dbg_cint , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_n_uct_dstor_int_q, ex3_n_uct_dstor_int : std_ulogic_vector(0 to threads-1); -- input=>ex3_n_uct_dstor_int , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_n_vec_unavail_int_q, ex3_n_vec_unavail_int : std_ulogic_vector(0 to threads-1); -- input=>ex3_n_vec_unavail_int , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_n_vf_dstor_int_q, ex3_n_vf_dstor_int : std_ulogic_vector(0 to threads-1); -- input=>ex3_n_vf_dstor_int , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_n_xu_rfpe_flush_q, ex4_n_xu_rfpe_flush_d : std_ulogic_vector(0 to threads-1); -- input=>ex4_n_xu_rfpe_flush_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_np1_cdbell_cint_q, ex3_np1_cdbell_cint : std_ulogic_vector(0 to threads-1); -- input=>ex3_np1_cdbell_cint , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_np1_crit_cint_q, ex3_np1_crit_cint : std_ulogic_vector(0 to threads-1); -- input=>ex3_np1_crit_cint , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_np1_dbell_int_q, ex3_np1_dbell_int : std_ulogic_vector(0 to threads-1); -- input=>ex3_np1_dbell_int , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_np1_dec_int_q, ex3_np1_dec_int : std_ulogic_vector(0 to threads-1); -- input=>ex3_np1_dec_int , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_np1_ext_int_q, ex3_np1_ext_int : std_ulogic_vector(0 to threads-1); -- input=>ex3_np1_ext_int , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_np1_ext_mchk_mcint_q, ex3_np1_ext_mchk_mcint : std_ulogic_vector(0 to threads-1); -- input=>ex3_np1_ext_mchk_mcint , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_np1_fit_int_q, ex3_np1_fit_int : std_ulogic_vector(0 to threads-1); -- input=>ex3_np1_fit_int , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_np1_flush_q, ex3_np1_flush : std_ulogic_vector(0 to threads-1); -- input=>ex3_np1_flush , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_np1_gcdbell_cint_q, ex3_np1_gcdbell_cint : std_ulogic_vector(0 to threads-1); -- input=>ex3_np1_gcdbell_cint , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_np1_gdbell_int_q, ex3_np1_gdbell_int : std_ulogic_vector(0 to threads-1); -- input=>ex3_np1_gdbell_int , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_np1_gmcdbell_cint_q, ex3_np1_gmcdbell_cint : std_ulogic_vector(0 to threads-1); -- input=>ex3_np1_gmcdbell_cint , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_np1_ide_dbg_cint_q, ex3_np1_ide_dbg_cint : std_ulogic_vector(0 to threads-1); -- input=>ex3_np1_ide_dbg_cint , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_np1_instr_int_q, ex3_np1_instr_int : std_ulogic_vector(0 to threads-1); -- input=>ex3_np1_instr_int , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_np1_perf_int_q, ex3_np1_perf_int : std_ulogic_vector(0 to threads-1); -- input=>ex3_np1_perf_int , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_np1_ptr_prog_int_q, ex3_np1_ptr_prog_int : std_ulogic_vector(0 to threads-1); -- input=>ex3_np1_ptr_prog_int , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_np1_rfi_q, ex3_np1_rfi : std_ulogic_vector(0 to threads-1); -- input=>ex3_np1_rfi , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_np1_run_ctl_flush_q, ex3_np1_run_ctl_flush : std_ulogic_vector(0 to threads-1); -- input=>ex3_np1_run_ctl_flush , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_np1_sc_int_q, ex3_np1_sc_int : std_ulogic_vector(0 to threads-1); -- input=>ex3_np1_sc_int , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_np1_ude_dbg_cint_q, ex3_np1_ude_dbg_cint : std_ulogic_vector(0 to threads-1); -- input=>ex3_np1_ude_dbg_cint , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_np1_ude_dbg_event_q, ex3_np1_ude_dbg_event : std_ulogic_vector(0 to threads-1); -- input=>ex3_np1_ude_dbg_event , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_np1_udec_int_q, ex3_np1_udec_int : std_ulogic_vector(0 to threads-1); -- input=>ex3_np1_udec_int , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_np1_wdog_cint_q, ex3_np1_wdog_cint : std_ulogic_vector(0 to threads-1); -- input=>ex3_np1_wdog_cint , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_np1_fu_flush_q, ex3_np1_fu_flush : std_ulogic_vector(0 to threads-1); -- input=>ex3_np1_fu_flush , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_n_ieratsx_par_mchk_mcint_q,ex3_n_ieratsx_par_mchk_mcint : std_ulogic_vector(0 to threads-1); -- input=>ex3_n_ieratsx_par_mchk_mcint,act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_n_tlbmh_mchk_mcint_q : std_ulogic_vector(0 to threads-1); -- input=>ex3_n_tlbmh_mchk_mcint , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_n_sprg_ue_flush_q : std_ulogic_vector(0 to threads-1); -- input=>ex3_n_sprg_ue_flush , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_n_rwaccess_dstor_int_q, ex3_n_rwaccess_dstor_int : std_ulogic_vector(0 to threads-1); -- input=>ex3_n_rwaccess_dstor_int , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_n_exaccess_istor_int_q, ex3_n_exaccess_istor_int : std_ulogic_vector(0 to threads-1); -- input=>ex3_n_exaccess_istor_int , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_sc_lev_q : std_ulogic; -- input=>ex3_sc_lev_q , act=>exx_act(3) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex4_siar_sel_q, ex4_siar_sel_d : std_ulogic_vector(0 to 1); -- input=>ex4_siar_sel_d , act=>ex4_siar_sel_act , scan=>Y, sleep=>N, needs_sreset=>0, init=>1 +signal ex4_step_q, ex4_step_d : std_ulogic_vector(0 to threads-1); -- input=>ex4_step_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_taken_bclr_q : std_ulogic; -- input=>ex3_taken_bclr_q , act=>exx_act(3) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex4_tlb_inelig_q : std_ulogic_vector(0 to threads-1); -- input=>ex3_tlb_inelig_q , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_ucode_val_q : std_ulogic_vector(0 to threads-1); -- input=>ex3_ucode_val , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_xu_is_ucode_q : std_ulogic; -- input=>ex3_xu_is_ucode_q , act=>exx_act(3) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex4_xu_val_q : std_ulogic_vector(0 to threads-1); -- input=>ex3_xu_val , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_cia_act_q, ex3_cia_act : std_ulogic_vector(0 to threads-1); -- input=>ex3_cia_act , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_n_async_dacr_dbg_cint_q, ex3_n_async_dacr_dbg_cint : std_ulogic_vector(0 to threads-1); -- input=>ex3_n_async_dacr_dbg_cint , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_dac1r_cmpr_async_q, ex4_dac1r_cmpr_async_d : std_ulogic_vector(0 to threads-1); -- input=>ex4_dacr_cmpr_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_dac2r_cmpr_async_q, ex4_dac2r_cmpr_async_d : std_ulogic_vector(0 to threads-1); -- input=>ex4_dacw_cmpr_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_thread_stop_q, ex3_thread_stop : std_ulogic_vector(0 to threads-1); -- input=>ex3_thread_stop , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_icmp_event_on_int_ok_q, ex4_icmp_event_on_int_ok : std_ulogic_vector(0 to threads-1); -- input=>ex4_icmp_event_on_int_ok , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_any_val_q : std_ulogic_vector(0 to threads-1); -- input=>ex4_any_val , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_attn_flush_q, ex4_attn_flush : std_ulogic_vector(0 to threads-1); -- input=>ex4_attn_flush , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_axu_trap_pie_q, ex5_axu_trap_pie_d : std_ulogic_vector(0 to threads-1); -- input=>ex5_axu_trap_pie_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_br_taken_q : std_ulogic; -- input=>ex4_br_taken_q , act=>exx_act(4) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex5_cdbell_taken_q, ex5_cdbell_taken_d : std_ulogic_vector(0 to threads-1); -- input=>ex5_cdbell_taken_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_check_bclr_q, ex5_check_bclr_d : std_ulogic_vector(0 to threads-1); -- input=>ex5_check_bclr_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_cia_p1_q, ex5_cia_p1_d : std_ulogic_vector(62-eff_ifar to 61); -- input=>ex5_cia_p1_d , act=>exx_act(4) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex5_dbell_taken_q, ex5_dbell_taken_d : std_ulogic_vector(0 to threads-1); -- input=>ex5_dbell_taken_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_dbsr_update_q, ex4_dbsr_update : std_ulogic_vector(0 to threads-1); -- input=>ex4_dbsr_update , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_dear_update_saved_q, ex5_dear_update_saved_d : std_ulogic_vector(0 to threads-1); -- input=>ex5_dear_update_saved_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_deratre_par_err_q : std_ulogic_vector(0 to threads-1); -- input=>lsu_xu_ex4_derat_par_err , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_div_set_barr_q, ex5_div_set_barr_d : std_ulogic_vector(0 to threads-1); -- input=>ex5_div_set_barr_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_dsigs_q, ex5_dsigs_d : std_ulogic_vector(0 to threads-1); -- input=>ex5_dsigs_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_dtlbgs_q, ex5_dtlbgs_d : std_ulogic_vector(0 to threads-1); -- input=>ex5_dtlbgs_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_err_nia_miscmpr_q, ex5_err_nia_miscmpr_d : std_ulogic_vector(0 to threads-1); -- input=>ex5_err_nia_miscmpr_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_ext_dbg_err_q, ex5_ext_dbg_err_d : std_ulogic_vector(0 to threads-1); -- input=>ex5_ext_dbg_err_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_ext_dbg_ext_q, ex5_ext_dbg_ext_d : std_ulogic_vector(0 to threads-1); -- input=>ex5_ext_dbg_ext_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_extgs_q, ex5_extgs_d : std_ulogic_vector(0 to threads-1); -- input=>ex5_extgs_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_flush_q : std_ulogic_vector(0 to threads-1); -- input=>ex4_flush , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_force_gsrr_q, ex5_force_gsrr_d : std_ulogic_vector(0 to threads-1); -- input=>ex5_force_gsrr_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_gcdbell_taken_q, ex5_gcdbell_taken_d : std_ulogic_vector(0 to threads-1); -- input=>ex5_gcdbell_taken_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_gdbell_taken_q, ex5_gdbell_taken_d : std_ulogic_vector(0 to threads-1); -- input=>ex5_gdbell_taken_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_gmcdbell_taken_q, ex5_gmcdbell_taken_d : std_ulogic_vector(0 to threads-1); -- input=>ex5_gmcdbell_taken_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_ieratre_par_err_q : std_ulogic_vector(0 to threads-1); -- input=>iu_xu_ierat_ex4_par_err , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_in_ucode_q, ex5_in_ucode_d : std_ulogic_vector(0 to threads-1); -- input=>ex5_in_ucode_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_instr_cpl_q, ex4_instr_cpl : std_ulogic_vector(0 to threads-1); -- input=>ex4_instr_cpl , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_is_any_rfi_q, ex4_is_any_rfi : std_ulogic_vector(0 to threads-1); -- input=>ex4_is_any_rfi , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_is_attn_q, ex5_is_attn_d : std_ulogic_vector(0 to threads-1); -- input=>ex5_is_attn_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_is_crit_int_q : std_ulogic_vector(0 to threads-1); -- input=>ex4_is_crit_int , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_is_mchk_int_q : std_ulogic_vector(0 to threads-1); -- input=>ex4_is_mchk_int , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_is_mtmsr_q : std_ulogic; -- input=>ex4_is_mtmsr_q , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_is_isync_q : std_ulogic; -- input=>ex4_is_isync_q , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_is_tlbwe_q : std_ulogic; -- input=>ex4_is_tlbwe_q , act=>exx_act(4) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex5_isigs_q, ex5_isigs_d : std_ulogic_vector(0 to threads-1); -- input=>ex5_isigs_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_itlbgs_q, ex5_itlbgs_d : std_ulogic_vector(0 to threads-1); -- input=>ex5_itlbgs_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_lsu_set_barr_q, ex5_lsu_set_barr_d : std_ulogic_vector(0 to threads-1); -- input=>ex5_lsu_set_barr_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_mem_attr_val_q, ex4_mem_attr_val : std_ulogic_vector(0 to threads-1); -- input=>ex4_mem_attr_val , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_mmu_hold_val_q : std_ulogic_vector(0 to threads-1); -- input=>ex4_mmu_hold_val_q , act=>tiup , scan=>Y, sleep=>Y, needs_sreset=>1 +signal ex5_n_dmiss_flush_q, ex4_n_dmiss_flush : std_ulogic_vector(0 to threads-1); -- input=>ex4_n_dmiss_flush , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_n_ext_dbg_stopc_flush_q,ex5_n_ext_dbg_stopc_flush_d : std_ulogic; -- input=>ex5_n_ext_dbg_stopc_flush_d, act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_n_ext_dbg_stopt_flush_q,ex5_n_ext_dbg_stopt_flush_d : std_ulogic_vector(0 to threads-1); -- input=>ex5_n_ext_dbg_stopt_flush_d, act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_n_imiss_flush_q, ex4_n_imiss_flush : std_ulogic_vector(0 to threads-1); -- input=>ex4_n_imiss_flush , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_n_ptemiss_dlrat_int_q : std_ulogic_vector(0 to threads-1); -- input=>ex4_n_ptemiss_dlrat_int_q , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_np1_icmp_dbg_cint_q, ex5_np1_icmp_dbg_cint_d : std_ulogic_vector(0 to threads-1); -- input=>ex5_np1_icmp_dbg_cint_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_np1_icmp_dbg_event_q, ex5_np1_icmp_dbg_event_d : std_ulogic_vector(0 to threads-1); -- input=>ex5_np1_icmp_dbg_event_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_np1_run_ctl_flush_q, ex4_np1_run_ctl_flush : std_ulogic_vector(0 to threads-1); -- input=>ex4_np1_run_ctl_flush , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_dbsr_ide_q, ex5_dbsr_ide_d : std_ulogic_vector(0 to threads-1); -- input=>ex5_dbsr_ide_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_perf_dtlb_q, ex5_perf_dtlb_d : std_ulogic_vector(0 to threads-1); -- input=>ex5_perf_dtlb_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_perf_itlb_q, ex5_perf_itlb_d : std_ulogic_vector(0 to threads-1); -- input=>ex5_perf_itlb_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_ram_done_q, ex5_ram_done_d : std_ulogic; -- input=>ex5_ram_done_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_ram_issue_q, ex5_ram_issue_d : std_ulogic_vector(0 to threads-1); -- input=>ex5_ram_issue_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_rt_q : std_ulogic_vector(64-regsize to 63); -- input=>mux_cpl_ex4_rt , act=>exx_act(4) , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex5_sel_rt_q, ex5_sel_rt_d : std_ulogic_vector(0 to threads-1); -- input=>ex5_sel_rt_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_srr0_dec_q, ex5_srr0_dec_d : std_ulogic_vector(0 to threads-1); -- input=>ex5_srr0_dec_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_tlb_inelig_q : std_ulogic_vector(0 to threads-1); -- input=>ex4_tlb_inelig_q , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_uc_cia_val_q, ex5_uc_cia_val_d : std_ulogic_vector(0 to threads-1); -- input=>ex5_uc_cia_val_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_xu_ifar_q, ex5_xu_ifar_d : IFAR; -- input=>ex5_xu_ifar_d , act=>exx_act(4) , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_xu_val_q : std_ulogic_vector(0 to threads-1); -- input=>ex4_xu_val , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_n_flush_sprg_ue_flush_q, ex4_n_flush_sprg_ue_flush : std_ulogic_vector(0 to threads-1); -- input=>ex4_n_flush_sprg_ue_flush , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_mcsr_act_q : std_ulogic_vector(0 to threads-1); -- input=>ex4_mcsr_act , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex6_mcsr_act_q, ex6_mcsr_act_d : std_ulogic; -- input=>ex6_mcsr_act_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex6_late_flush_q : std_ulogic_vector(0 to threads-1); -- input=>ex5_late_flush_q(0) , act=>tiup , scan=>N, sleep=>N, needs_sreset=>1 +signal ex6_mmu_hold_val_q : std_ulogic_vector(0 to threads-1); -- input=>ex5_mmu_hold_val_q , act=>tiup , scan=>N, sleep=>Y, needs_sreset=>1 +signal ex6_ram_done_q : std_ulogic; -- input=>ex5_ram_done_q , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex6_ram_interrupt_q, ex6_ram_interrupt_d : std_ulogic; -- input=>ex6_ram_interrupt_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex6_ram_issue_q, ex6_ram_issue_d : std_ulogic_vector(0 to threads-1); -- input=>ex6_ram_issue_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex7_ram_issue_q : std_ulogic_vector(0 to threads-1); -- input=>ex6_ram_issue_q , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex8_ram_issue_q : std_ulogic_vector(0 to threads-1); -- input=>ex7_ram_issue_q , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex6_set_barr_q, ex6_set_barr_d : std_ulogic_vector(0 to threads-1); -- input=>ex6_set_barr_d , act=>tiup , scan=>N, sleep=>N, needs_sreset=>1 +signal ex6_step_done_q, ex5_step_done : std_ulogic_vector(0 to threads-1); -- input=>ex5_step_done , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex6_xu_val_q : std_ulogic_vector(0 to threads-1); -- input=>ex5_xu_val_q , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex6_is_tlbwe_q : std_ulogic; -- input=>ex5_is_tlbwe_q , act=>tiup , scan=>N, sleep=>N, needs_sreset=>0 +signal ex7_is_tlbwe_q, ex7_is_tlbwe_d : std_ulogic_vector(0 to threads-1); -- input=>ex7_is_tlbwe_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex8_is_tlbwe_q : std_ulogic_vector(0 to threads-1); -- input=>ex7_is_tlbwe_q , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ccr2_ap_q : std_ulogic_vector(0 to threads-1); -- input=>spr_ccr2_ap , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal cpl_quiesced_q, cpl_quiesced_d : std_ulogic_vector(0 to threads-1); -- input=>cpl_quiesced_d , act=>tiup , scan=>Y, sleep=>Y, needs_sreset=>1 +signal dbcr0_idm_q : std_ulogic_vector(0 to threads-1); -- input=>spr_dbcr0_idm , act=>spr_bit_act_q , scan=>Y, sleep=>N, needs_sreset=>1 +signal dci_val_q, dci_val_d : std_ulogic; -- input=>dci_val_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal debug_event_en_q, debug_event_en_d : std_ulogic_vector(0 to threads-1); -- input=>debug_event_en_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal derat_hold_present_q, derat_hold_present_d : std_ulogic_vector(0 to threads-1); -- input=>derat_hold_present_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ext_dbg_act_err_q, ext_dbg_act_err_d : std_ulogic_vector(0 to threads-1); -- input=>ext_dbg_act_err_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ext_dbg_act_ext_q, ext_dbg_act_ext_d : std_ulogic_vector(0 to threads-1); -- input=>ext_dbg_act_ext_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ext_dbg_stop_core_q, ext_dbg_stop_core_d : std_ulogic_vector(0 to threads-1); -- input=>ext_dbg_stop_core_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ext_dbg_stop_n_q, ext_dbg_stop_n_d : std_ulogic_vector(0 to threads-1); -- input=>ext_dbg_stop_n_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal external_mchk_q : std_ulogic_vector(0 to threads-1); -- input=>spr_cpl_external_mchk , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal exx_instr_async_block_q, exx_instr_async_block_d : ARY_BLOCK; -- input=>exx_instr_async_block_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal exx_multi_flush_q, exx_multi_flush_d : std_ulogic_vector(0 to threads-1); -- input=>exx_multi_flush_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal force_ude_q : std_ulogic_vector(0 to threads-1); -- input=>pc_xu_force_ude , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal fu_rf_seq_end_q : std_ulogic; -- input=>fu_xu_regfile_seq_end , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal fu_rfpe_ack_q, fu_rfpe_ack_d : std_ulogic_vector(0 to 1); -- input=>fu_rfpe_ack_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal fu_rfpe_hold_present_q, fu_rfpe_hold_present_d : std_ulogic; -- input=>fu_rfpe_hold_present_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ici_hold_present_q, ici_hold_present_d : std_ulogic_vector(0 to 2); -- input=>ici_hold_present_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ici_val_q, ici_val_d : std_ulogic; -- input=>ici_val_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ierat_hold_present_q, ierat_hold_present_d : std_ulogic_vector(0 to threads-1); -- input=>ierat_hold_present_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal mmu_eratmiss_done_q : std_ulogic_vector(0 to threads-1); -- input=>mm_xu_eratmiss_done , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal mmu_hold_present_q, mmu_hold_present_d : std_ulogic_vector(0 to threads-1); -- input=>mmu_hold_present_d , act=>tiup , scan=>Y, sleep=>Y, needs_sreset=>1 +signal mmu_hold_request_q, mmu_hold_request_d : std_ulogic_vector(0 to threads-1); -- input=>mmu_hold_request_d , act=>tiup , scan=>Y, sleep=>Y, needs_sreset=>1 +signal msr_cm_q : std_ulogic_vector(0 to threads-1); -- input=>spr_msr_cm , act=>spr_bit_w_int_act , scan=>Y, sleep=>N, needs_sreset=>1 +signal msr_de_q : std_ulogic_vector(0 to threads-1); -- input=>spr_msr_de , act=>spr_bit_w_int_act , scan=>Y, sleep=>N, needs_sreset=>1 +signal msr_fp_q : std_ulogic_vector(0 to threads-1); -- input=>spr_msr_fp , act=>spr_bit_w_int_act , scan=>Y, sleep=>N, needs_sreset=>1 +signal msr_gs_q : std_ulogic_vector(0 to threads-1); -- input=>spr_msr_gs , act=>spr_bit_w_int_act , scan=>Y, sleep=>N, needs_sreset=>1 +signal msr_me_q : std_ulogic_vector(0 to threads-1); -- input=>spr_msr_me , act=>spr_bit_w_int_act , scan=>Y, sleep=>N, needs_sreset=>1 +signal msr_pr_q : std_ulogic_vector(0 to threads-1); -- input=>spr_msr_pr , act=>spr_bit_w_int_act , scan=>Y, sleep=>N, needs_sreset=>1 +signal msr_spv_q : std_ulogic_vector(0 to threads-1); -- input=>spr_msr_spv , act=>spr_bit_w_int_act , scan=>Y, sleep=>N, needs_sreset=>1 +signal msr_ucle_q : std_ulogic_vector(0 to threads-1); -- input=>spr_msr_ucle , act=>spr_bit_w_int_act , scan=>Y, sleep=>N, needs_sreset=>1 +signal msrp_uclep_q : std_ulogic_vector(0 to threads-1); -- input=>spr_msrp_uclep , act=>spr_bit_act_q , scan=>Y, sleep=>N, needs_sreset=>1 +signal pc_dbg_action_q : std_ulogic_vector(0 to 3*threads-1); -- input=>pc_xu_dbg_action , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal pc_dbg_stop_q, pc_dbg_stop_d : std_ulogic_vector(0 to threads-1); -- input=>pc_dbg_stop_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal pc_dbg_stop_2_q, pc_dbg_stop : std_ulogic_vector(0 to threads-1); -- input=>pc_dbg_stop , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal pc_err_mcsr_rpt_q, pc_err_mcsr_rpt_d : std_ulogic_vector(0 to 10); -- input=>pc_err_mcsr_rpt_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal pc_err_mcsr_summary_q, pc_err_mcsr_summary_d : std_ulogic_vector(0 to threads-1); -- input=>pc_err_mcsr_summary_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal pc_init_reset_q : std_ulogic; -- input=>pc_xu_init_reset , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal quiesced_q, quiesced_d : std_ulogic; -- input=>quiesced_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ram_flush_q, ram_flush_d : std_ulogic_vector(0 to threads-1); -- input=>ram_flush_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ram_ip_q, ram_ip_d : std_ulogic_vector(0 to threads-1); -- input=>ram_ip_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ram_mode_q, ram_mode_d : std_ulogic_vector(0 to threads-1); -- input=>ram_mode_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal slowspr_flush_q : std_ulogic_vector(0 to threads-1); -- input=>mux_cpl_slowspr_flush , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal spr_cpl_async_int_q : std_ulogic_vector(0 to 3*threads-1); -- input=>spr_cpl_async_int , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ram_execute_q, ram_execute_d : std_ulogic_vector(0 to threads-1); -- input=>ram_execute_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ssprwr_ip_q, ssprwr_ip_d : std_ulogic_vector(0 to threads-1); -- input=>ssprwr_ip_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal exx_cm_hold_q : std_ulogic_vector(0 to threads-1); -- input=>exx_cm_hold , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal xu_ex1_n_flush_q : std_ulogic_vector(0 to threads-1); -- input=>rf1_flush , act=>exx_flush_inf_act , scan=>Y, sleep=>N, needs_sreset=>1 +signal xu_ex1_s_flush_q : std_ulogic_vector(0 to threads-1); -- input=>rf1_flush , act=>exx_flush_inf_act , scan=>Y, sleep=>N, needs_sreset=>1 +signal xu_ex1_w_flush_q : std_ulogic_vector(0 to threads-1); -- input=>rf1_flush , act=>exx_flush_inf_act , scan=>Y, sleep=>N, needs_sreset=>1 +signal xu_ex2_n_flush_q : std_ulogic_vector(0 to threads-1); -- input=>ex1_flush , act=>exx_flush_inf_act , scan=>Y, sleep=>N, needs_sreset=>1 +signal xu_ex2_s_flush_q : std_ulogic_vector(0 to threads-1); -- input=>ex1_flush , act=>exx_flush_inf_act , scan=>Y, sleep=>N, needs_sreset=>1 +signal xu_ex2_w_flush_q : std_ulogic_vector(0 to threads-1); -- input=>ex1_flush , act=>exx_flush_inf_act , scan=>Y, sleep=>N, needs_sreset=>1 +signal xu_ex3_n_flush_q : std_ulogic_vector(0 to threads-1); -- input=>ex2_flush , act=>exx_flush_inf_act , scan=>Y, sleep=>N, needs_sreset=>1 +signal xu_ex3_s_flush_q : std_ulogic_vector(0 to threads-1); -- input=>ex2_flush , act=>exx_flush_inf_act , scan=>Y, sleep=>N, needs_sreset=>1 +signal xu_ex3_w_flush_q : std_ulogic_vector(0 to threads-1); -- input=>ex2_flush , act=>exx_flush_inf_act , scan=>Y, sleep=>N, needs_sreset=>1 +signal xu_ex4_n_flush_q : std_ulogic_vector(0 to threads-1); -- input=>ex3_flush , act=>exx_flush_inf_act , scan=>Y, sleep=>N, needs_sreset=>1 +signal xu_ex4_s_flush_q : std_ulogic_vector(0 to threads-1); -- input=>ex3_flush , act=>exx_flush_inf_act , scan=>Y, sleep=>N, needs_sreset=>1 +signal xu_ex4_w_flush_q : std_ulogic_vector(0 to threads-1); -- input=>ex3_flush , act=>exx_flush_inf_act , scan=>Y, sleep=>N, needs_sreset=>1 +signal xu_ex5_n_flush_q : std_ulogic_vector(0 to threads-1); -- input=>ex4_flush , act=>ex4_flush_inf_act , scan=>Y, sleep=>N, needs_sreset=>1 +signal xu_ex5_s_flush_q : std_ulogic_vector(0 to threads-1); -- input=>ex4_flush , act=>ex4_flush_inf_act , scan=>Y, sleep=>N, needs_sreset=>1 +signal xu_ex5_w_flush_q : std_ulogic_vector(0 to threads-1); -- input=>ex4_flush , act=>ex4_flush_inf_act , scan=>Y, sleep=>N, needs_sreset=>1 +signal xu_is2_n_flush_q : std_ulogic_vector(0 to threads-1); -- input=>any_flush , act=>exx_flush_inf_act , scan=>Y, sleep=>N, needs_sreset=>1 +signal xu_rf0_n_flush_q : std_ulogic_vector(0 to threads-1); -- input=>is2_flush , act=>exx_flush_inf_act , scan=>Y, sleep=>N, needs_sreset=>1 +signal xu_rf1_n_flush_q : std_ulogic_vector(0 to threads-1); -- input=>rf0_flush , act=>exx_flush_inf_act , scan=>Y, sleep=>N, needs_sreset=>1 +signal xu_rf1_s_flush_q : std_ulogic_vector(0 to threads-1); -- input=>rf0_flush , act=>exx_flush_inf_act , scan=>Y, sleep=>N, needs_sreset=>1 +signal xu_rf1_w_flush_q : std_ulogic_vector(0 to threads-1); -- input=>rf0_flush , act=>exx_flush_inf_act , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_np1_irpt_dbg_cint_q, ex4_np1_irpt_dbg_cint : std_ulogic_vector(0 to threads-1); -- input=>ex4_np1_irpt_dbg_cint , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex6_np1_irpt_dbg_cint_q, ex6_np1_irpt_dbg_cint_d : std_ulogic_vector(0 to threads-1); -- input=>ex6_np1_irpt_dbg_cint_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_np1_irpt_dbg_event_q, ex4_np1_irpt_dbg_event : std_ulogic_vector(0 to threads-1); -- input=>ex4_np1_irpt_dbg_event , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex6_np1_irpt_dbg_event_q, ex6_np1_irpt_dbg_event_d : std_ulogic_vector(0 to threads-1); -- input=>ex6_np1_irpt_dbg_event_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal clkg_ctl_q : std_ulogic; --input=>spr_xucr0_clkg_ctl(2) , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal xu_rf_seq_end_q : std_ulogic; -- input=>gpr_cpl_regfile_seq_end , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal xu_rfpe_ack_q, xu_rfpe_ack_d : std_ulogic_vector(0 to 1); -- input=>xu_rfpe_ack_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal xu_rfpe_hold_present_q, xu_rfpe_hold_present_d : std_ulogic; -- input=>xu_rfpe_hold_present_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal exx_act_q, exx_act_d : std_ulogic_vector(0 to 4); -- input=>exx_act_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_mchk_int_en_q, ex3_mchk_int_en : std_ulogic_vector(0 to threads-1); -- input=>ex3_mchk_int_en , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex5_mchk_int_en_q : std_ulogic_vector(0 to threads-1); -- input=>ex4_mchk_int_en_q , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>0 +signal trace_bus_enable_q : std_ulogic; -- input=>pc_xu_trace_bus_enable , act=>tiup , scan=>Y, sleep=>Y, needs_sreset=>0 +signal ex1_instr_trace_type_q : std_ulogic_vector(0 to 1); -- input=>dec_cpl_rf1_instr_trace_type,act=>trace_bus_enable_q , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex1_instr_trace_val_q : std_ulogic; -- input=>dec_cpl_rf1_instr_trace_val, act=>trace_bus_enable_q , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex1_xu_issued_q : std_ulogic_vector(0 to threads-1); -- input=>dec_cpl_rf1_issued , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex2_xu_issued_q : std_ulogic_vector(0 to threads-1); -- input=>ex1_xu_issued_q , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex3_xu_issued_q : std_ulogic_vector(0 to threads-1); -- input=>ex2_xu_issued_q , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex4_xu_issued_q, ex3_xu_issued : std_ulogic_vector(0 to threads-1); -- input=>ex3_xu_issued , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex3_axu_issued_q : std_ulogic_vector(0 to threads-1); -- input=>fu_xu_ex2_ifar_issued , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex4_axu_issued_q : std_ulogic_vector(0 to threads-1); -- input=>ex3_axu_issued_q , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex2_instr_dbg_q : std_ulogic_vector(0 to 31); -- input=>ex1_instr , act=>trace_bus_enable_q , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex2_instr_trace_type_q : std_ulogic_vector(0 to 1); -- input=>ex1_instr_trace_type_q , act=>trace_bus_enable_q , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex4_instr_trace_val_q : std_ulogic; -- input=>dec_cpl_ex3_instr_trace_val, act=>trace_bus_enable_q , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex5_axu_val_dbg_q : std_ulogic_vector(0 to threads-1); -- input=>ex4_axu_val , act=>trace_bus_enable_q , scan=>N, sleep=>Y, needs_sreset=>0 +signal ex5_instr_cpl_dbg_q : std_ulogic_vector(0 to threads-1); -- input=>ex4_instr_cpl , act=>trace_bus_enable_q , scan=>N, sleep=>Y, needs_sreset=>0 +signal ex5_instr_trace_val_q : std_ulogic; -- input=>ex4_instr_trace_val_q , act=>trace_bus_enable_q , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex5_siar_q, ex5_siar_d : std_ulogic_vector(62-eff_ifar to 61); -- input=>ex5_siar_d , act=>trace_bus_enable_q , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex5_siar_cpl_q, ex5_siar_cpl_d : std_ulogic; -- input=>ex5_siar_cpl_d , act=>trace_bus_enable_q , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex5_siar_gs_q, ex5_siar_gs_d : std_ulogic; -- input=>ex5_siar_gs_d , act=>trace_bus_enable_q , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex5_siar_issued_q, ex5_siar_issued_d : std_ulogic; -- input=>ex5_siar_issued_d , act=>trace_bus_enable_q , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex5_siar_pr_q, ex5_siar_pr_d : std_ulogic; -- input=>ex5_siar_pr_d , act=>trace_bus_enable_q , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex5_siar_tid_q, ex5_siar_tid_d : std_ulogic_vector(0 to 1); -- input=>ex5_siar_tid_d , act=>trace_bus_enable_q , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex5_ucode_end_dbg_q : std_ulogic_vector(0 to threads-1); -- input=>ex4_ucode_end , act=>trace_bus_enable_q , scan=>Y, sleep=>Y, needs_sreset=>0 +signal ex5_ucode_val_dbg_q : std_ulogic_vector(0 to threads-1); -- input=>ex4_ucode_val , act=>trace_bus_enable_q , scan=>Y, sleep=>Y, needs_sreset=>0 +signal instr_trace_mode_q : std_ulogic; -- input=>pc_xu_instr_trace_mode , act=>trace_bus_enable_q , scan=>Y, sleep=>N, needs_sreset=>0 +signal debug_data_out_q, debug_data_out_d : std_ulogic_vector(0 to 87); -- input=>debug_data_out_d , act=>trace_bus_enable_q , scan=>Y, sleep=>Y, needs_sreset=>0 +signal debug_mux_ctrls_q : std_ulogic_vector(0 to 15); -- input=>cpl_debug_mux_ctrls , act=>trace_bus_enable_q , scan=>Y, sleep=>Y, needs_sreset=>0 +signal debug_mux_ctrls_int_q, debug_mux_ctrls_int : std_ulogic_vector(0 to 15); -- input=>debug_mux_ctrls_int , act=>trace_bus_enable_q , scan=>Y, sleep=>Y, needs_sreset=>0 +signal trigger_data_out_q, trigger_data_out_d : std_ulogic_vector(0 to 11); -- input=>trigger_data_out_d , act=>trace_bus_enable_q , scan=>Y, sleep=>Y, needs_sreset=>0 +signal event_bus_enable_q : std_ulogic; -- input=>pc_xu_event_bus_enable , act=>tiup , scan=>Y, sleep=>Y, needs_sreset=>0 +signal ex2_perf_event_q, ex2_perf_event_d : std_ulogic_vector(0 to 2); -- input=>ex2_perf_event_d , act=>event_bus_enable_q , scan=>N, sleep=>N, needs_sreset=>0 +signal ex3_perf_event_q : std_ulogic_vector(0 to 2); -- input=>ex2_perf_event_q , act=>event_bus_enable_q , scan=>Y, sleep=>N, needs_sreset=>0 +signal ex4_perf_event_q, ex4_perf_event_d : std_ulogic_vector(0 to 3); -- input=>ex4_perf_event_d , act=>event_bus_enable_q , scan=>N, sleep=>N, needs_sreset=>0 +signal ex5_perf_event_q, ex5_perf_event_d : std_ulogic_vector(0 to 14*threads-1); -- input=>ex5_perf_event_d , act=>event_bus_enable_q , scan=>Y, sleep=>N, needs_sreset=>0 +signal spr_bit_act_q : std_ulogic; -- input=>spr_bit_act , act=>tiup , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 +signal clk_override_q : std_ulogic; -- input=>clk_override_q , act=>tidn , scan=>Y, sleep=>N, needs_sreset=>0, ring=>ccfg, + +signal spare_0_q, spare_0_d : std_ulogic_vector(0 to 15); -- input=>spare_0_d, act=>tidn, +signal spare_1_q, spare_1_d : std_ulogic_vector(0 to 15); -- input=>spare_1_d, act=>tidn, +signal spare_2_q, spare_2_d : std_ulogic_vector(0 to 15); -- input=>spare_2_d, act=>tidn, +signal spare_3_q, spare_3_d : std_ulogic_vector(0 to 15); -- input=>spare_3_d, act=>tidn, +signal spare_4_q, spare_4_d : std_ulogic_vector(0 to 7); -- input=>spare_4_d, act=>tidn, +signal spare_5_q, spare_5_d : std_ulogic_vector(0 to 3); -- input=>spare_5_d, act=>tidn, + +-- Per thread controls +signal ex2_ifar_b_q : std_ulogic_vector(0 to eff_ifar*threads-1);--input=>ex1_xu_ifar , act=>ex1_ifar_act(t) , scan=>N, sleep=>N, needs_sreset=>0, iterator=>(t) +signal ex3_ifar_q : std_ulogic_vector(0 to eff_ifar*threads-1);--input=>ex2_ifar , act=>ex2_ifar_act(t) , scan=>Y, sleep=>N, needs_sreset=>0, iterator=>(t) +signal ex4_ifar_q : std_ulogic_vector(0 to eff_ifar*threads-1);--input=>ex3_ifar_q , act=>ex3_ifar_act(t) , scan=>N, sleep=>N, needs_sreset=>0, iterator=>(t) +signal ex5_nia_b_q : std_ulogic_vector(0 to eff_ifar*threads-1); +signal ex4_epid_instr_q : std_ulogic_vector(0 to threads-1); -- input=>ex3_epid_instr_q , act=>ex3_esr_bit_act , scan=>N, sleep=>N, needs_sreset=>1 +signal ex4_is_any_store_q : std_ulogic_vector(0 to threads-1); -- input=>dec_cpl_ex3_is_any_store , act=>ex3_esr_bit_act , scan=>N, sleep=>N, needs_sreset=>1 +signal ex5_flush_2ucode_q, ex5_flush_2ucode_d : std_ulogic_vector(0 to threads-1); -- input=>ex5_flush_2ucode_d , act=>ex4_flush_act , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_ucode_restart_q, ex5_ucode_restart_d : std_ulogic_vector(0 to threads-1); -- input=>ex5_ucode_restart_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_mem_attr_le_q, ex5_mem_attr_le_d : std_ulogic_vector(0 to threads-1); -- input=>ex5_mem_attr_le_d , act=>ex4_flush_act , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex4_dacr_cmpr_q, ex4_dacr_cmpr_d : DAC; -- input=>ex4_dacr_cmpr_d , act=>exx_act(3) , scan=>N, sleep=>N, needs_sreset=>0 +signal ex4_dacw_cmpr_q, ex4_dacw_cmpr_d : DAC; -- input=>ex4_dacw_cmpr_d , act=>exx_act(3) , scan=>N, sleep=>N, needs_sreset=>0 +signal ex5_late_flush_q, ex5_late_flush_d : TID_ARR; -- input=>ex5_late_flush_d , act=>tiup , scan=>Y, sleep=>N, needs_sreset=>1 +signal ex5_esr_q, ex5_esr_d : std_ulogic_vector(0 to 17*threads-1); -- input=>ex5_esr_d , act=>ex4_esr_act(t) , scan=>Y, sleep=>N, needs_sreset=>1, iterator=>(t) +signal ex5_dbsr_q, ex5_dbsr_d : std_ulogic_vector(0 to 19*threads-1); -- input=>ex5_dbsr_d , act=>ex4_dbsr_act(t) , scan=>Y, sleep=>N, needs_sreset=>1, iterator=>(t) +signal ex5_mcsr_q, ex5_mcsr_d : std_ulogic_vector(0 to 15*threads-1); -- input=>ex5_mcsr_d , act=>ex4_mcsr_act(t) , scan=>Y, sleep=>N, needs_sreset=>1, iterator=>(t) +signal dbg_flushcond_q, dbg_flushcond_d : ARY64; -- input=>dbg_flushcond_d , act=>trace_bus_enable_q , scan=>N, sleep=>Y, needs_sreset=>0 + +-- Scanchains +constant is2_flush_offset : integer := 0; +constant rf0_flush_offset : integer := is2_flush_offset + is2_flush_q'length; +constant rf1_flush_offset : integer := rf0_flush_offset + rf0_flush_q'length; +constant rf1_tid_offset : integer := rf1_flush_offset + rf1_flush_q'length; +constant ex1_axu_act_offset : integer := rf1_tid_offset + rf1_tid_q'length; +constant ex1_byte_rev_offset : integer := ex1_axu_act_offset + ex1_axu_act_q'length; +constant ex1_flush_offset : integer := ex1_byte_rev_offset + 1; +constant ex1_is_any_ldstmw_offset : integer := ex1_flush_offset + ex1_flush_q'length; +constant ex1_is_attn_offset : integer := ex1_is_any_ldstmw_offset + 1; +constant ex1_is_dci_offset : integer := ex1_is_attn_offset + 1; +constant ex1_is_dlock_offset : integer := ex1_is_dci_offset + 1; +constant ex1_is_ehpriv_offset : integer := ex1_is_dlock_offset + 1; +constant ex1_is_erativax_offset : integer := ex1_is_ehpriv_offset + 1; +constant ex1_is_ici_offset : integer := ex1_is_erativax_offset + 1; +constant ex1_is_icswx_offset : integer := ex1_is_ici_offset + 1; +constant ex1_is_ilock_offset : integer := ex1_is_icswx_offset + 1; +constant ex1_is_isync_offset : integer := ex1_is_ilock_offset + 1; +constant ex1_is_mfspr_offset : integer := ex1_is_isync_offset + 1; +constant ex1_is_mtmsr_offset : integer := ex1_is_mfspr_offset + 1; +constant ex1_is_mtspr_offset : integer := ex1_is_mtmsr_offset + 1; +constant ex1_is_rfci_offset : integer := ex1_is_mtspr_offset + 1; +constant ex1_is_rfgi_offset : integer := ex1_is_rfci_offset + 1; +constant ex1_is_rfi_offset : integer := ex1_is_rfgi_offset + 1; +constant ex1_is_rfmci_offset : integer := ex1_is_rfi_offset + 1; +constant ex1_is_sc_offset : integer := ex1_is_rfmci_offset + 1; +constant ex1_is_tlbivax_offset : integer := ex1_is_sc_offset + 1; +constant ex1_is_wrtee_offset : integer := ex1_is_tlbivax_offset + 1; +constant ex1_is_wrteei_offset : integer := ex1_is_wrtee_offset + 1; +constant ex1_is_mtxucr0_offset : integer := ex1_is_wrteei_offset + 1; +constant ex1_is_tlbwe_offset : integer := ex1_is_mtxucr0_offset + 1; +constant ex1_sc_lev_offset : integer := ex1_is_tlbwe_offset + 1; +constant ex1_ucode_val_offset : integer := ex1_sc_lev_offset + 1; +constant ex1_xu_val_offset : integer := ex1_ucode_val_offset + ex1_ucode_val_q'length; +constant ex2_flush_offset : integer := ex1_xu_val_offset + ex1_xu_val_q'length; +constant ex2_ucode_val_offset : integer := ex2_flush_offset + ex2_flush_q'length; +constant ex2_xu_val_offset : integer := ex2_ucode_val_offset + ex2_ucode_val_q'length; +constant ex3_async_int_block_offset : integer := ex2_xu_val_offset + ex2_xu_val_q'length; +constant ex3_axu_instr_match_offset : integer := ex3_async_int_block_offset + ex3_async_int_block_q'length; +constant ex3_axu_instr_type_offset : integer := ex3_axu_instr_match_offset + ex3_axu_instr_match_q'length; +constant ex3_axu_is_ucode_offset : integer := ex3_axu_instr_type_offset + ex3_axu_instr_type_q'length; +constant ex3_axu_val_offset : integer := ex3_axu_is_ucode_offset + ex3_axu_is_ucode_q'length; +constant ex3_br_flush_ifar_offset : integer := ex3_axu_val_offset + ex3_axu_val_q'length; +constant ex3_br_taken_offset : integer := ex3_br_flush_ifar_offset + ex3_br_flush_ifar_q'length; +constant ex3_br_update_offset : integer := ex3_br_taken_offset + 1; +constant ex3_byte_rev_offset : integer := ex3_br_update_offset + 1; +constant ex3_ctr_dec_update_offset : integer := ex3_byte_rev_offset + 1; +constant ex3_div_coll_offset : integer := ex3_ctr_dec_update_offset + 1; +constant ex3_epid_instr_offset : integer := ex3_div_coll_offset + ex3_div_coll_q'length; +constant ex3_flush_offset : integer := ex3_epid_instr_offset + 1; +constant ex3_ierat_flush_req_offset : integer := ex3_flush_offset + ex3_flush_q'length; +constant ex3_illegal_op_offset : integer := ex3_ierat_flush_req_offset + ex3_ierat_flush_req_q'length; +constant ex3_is_any_load_dac_offset : integer := ex3_illegal_op_offset + 1; +constant ex3_is_any_store_dac_offset : integer := ex3_is_any_load_dac_offset + 1; +constant ex3_is_attn_offset : integer := ex3_is_any_store_dac_offset + 1; +constant ex3_is_dci_offset : integer := ex3_is_attn_offset + 1; +constant ex3_is_dlock_offset : integer := ex3_is_dci_offset + 1; +constant ex3_is_ehpriv_offset : integer := ex3_is_dlock_offset + 1; +constant ex3_is_ici_offset : integer := ex3_is_ehpriv_offset + 1; +constant ex3_is_icswx_offset : integer := ex3_is_ici_offset + 1; +constant ex3_is_ilock_offset : integer := ex3_is_icswx_offset + 1; +constant ex3_is_isync_offset : integer := ex3_is_ilock_offset + 1; +constant ex3_is_mtmsr_offset : integer := ex3_is_isync_offset + 1; +constant ex3_is_rfci_offset : integer := ex3_is_mtmsr_offset + 1; +constant ex3_is_rfgi_offset : integer := ex3_is_rfci_offset + 1; +constant ex3_is_rfi_offset : integer := ex3_is_rfgi_offset + 1; +constant ex3_is_rfmci_offset : integer := ex3_is_rfi_offset + 1; +constant ex3_is_sc_offset : integer := ex3_is_rfmci_offset + 1; +constant ex3_is_tlbwe_offset : integer := ex3_is_sc_offset + 1; +constant ex3_is_slowspr_wr_offset : integer := ex3_is_tlbwe_offset + 1; +constant ex3_iu_error_offset : integer := ex3_is_slowspr_wr_offset + 1; +constant ex3_lr_update_offset : integer := ex3_iu_error_offset + ex3_iu_error_q'length; +constant ex3_lrat_miss_offset : integer := ex3_lr_update_offset + 1; +constant ex3_mmu_esr_data_offset : integer := ex3_lrat_miss_offset + ex3_lrat_miss_q'length; +constant ex3_mmu_esr_epid_offset : integer := ex3_mmu_esr_data_offset + ex3_mmu_esr_data_q'length; +constant ex3_mmu_esr_pt_offset : integer := ex3_mmu_esr_epid_offset + ex3_mmu_esr_epid_q'length; +constant ex3_mmu_esr_st_offset : integer := ex3_mmu_esr_pt_offset + ex3_mmu_esr_pt_q'length; +constant ex3_mmu_hv_priv_offset : integer := ex3_mmu_esr_st_offset + ex3_mmu_esr_st_q'length; +constant ex3_mtiar_offset : integer := ex3_mmu_hv_priv_offset + ex3_mmu_hv_priv_q'length; +constant ex3_n_align_int_offset : integer := ex3_mtiar_offset + 1; +constant ex3_n_dcpe_flush_offset : integer := ex3_n_align_int_offset + 1; +constant ex3_n_l2_ecc_err_flush_offset : integer := ex3_n_dcpe_flush_offset + ex3_n_dcpe_flush_q'length; +constant ex3_np1_run_ctl_flush_offset : integer := ex3_n_l2_ecc_err_flush_offset + ex3_n_l2_ecc_err_flush_q'length; +constant ex3_sc_lev_offset : integer := ex3_np1_run_ctl_flush_offset + ex3_np1_run_ctl_flush_q'length; +constant ex3_taken_bclr_offset : integer := ex3_sc_lev_offset + 1; +constant ex3_tlb_inelig_offset : integer := ex3_taken_bclr_offset + 1; +constant ex3_tlb_local_snoop_reject_offset : integer := ex3_tlb_inelig_offset + ex3_tlb_inelig_q'length; +constant ex3_tlb_lru_par_err_offset : integer := ex3_tlb_local_snoop_reject_offset + ex3_tlb_local_snoop_reject_q'length; +constant ex3_tlb_illeg_offset : integer := ex3_tlb_lru_par_err_offset + ex3_tlb_lru_par_err_q'length; +constant ex3_tlb_miss_offset : integer := ex3_tlb_illeg_offset + ex3_tlb_illeg_q'length; +constant ex3_tlb_multihit_err_offset : integer := ex3_tlb_miss_offset + ex3_tlb_miss_q'length; +constant ex3_tlb_par_err_offset : integer := ex3_tlb_multihit_err_offset + ex3_tlb_multihit_err_q'length; +constant ex3_tlb_pt_fault_offset : integer := ex3_tlb_par_err_offset + ex3_tlb_par_err_q'length; +constant ex3_ucode_val_offset : integer := ex3_tlb_pt_fault_offset + ex3_tlb_pt_fault_q'length; +constant ex3_xu_instr_match_offset : integer := ex3_ucode_val_offset + ex3_ucode_val_q'length; +constant ex3_xu_is_ucode_offset : integer := ex3_xu_instr_match_offset + 1; +constant ex3_xu_val_offset : integer := ex3_xu_is_ucode_offset + 1; +constant ex3_axu_async_block_offset : integer := ex3_xu_val_offset + ex3_xu_val_q'length; +constant ex3_is_mtxucr0_offset : integer := ex3_axu_async_block_offset + ex3_axu_async_block_q'length; +constant ex3_np1_instr_flush_offset : integer := ex3_is_mtxucr0_offset + 1; +constant ex4_apena_prog_int_offset : integer := ex3_np1_instr_flush_offset + 1; +constant ex4_axu_is_ucode_offset : integer := ex4_apena_prog_int_offset + ex4_apena_prog_int_q'length; +constant ex4_axu_trap_offset : integer := ex4_axu_is_ucode_offset + ex4_axu_is_ucode_q'length; +constant ex4_axu_val_offset : integer := ex4_axu_trap_offset + ex4_axu_trap_q'length; +constant ex4_base_int_block_offset : integer := ex4_axu_val_offset + ex4_axu_val_q'length; +constant ex4_br_flush_ifar_offset : integer := ex4_base_int_block_offset + ex4_base_int_block_q'length; +constant ex4_br_taken_offset : integer := ex4_br_flush_ifar_offset + ex4_br_flush_ifar_q'length; +constant ex4_br_update_offset : integer := ex4_br_taken_offset + 1; +constant ex4_byte_rev_offset : integer := ex4_br_update_offset + 1; +constant ex4_ctr_dec_update_offset : integer := ex4_byte_rev_offset + 1; +constant ex4_debug_flush_en_offset : integer := ex4_ctr_dec_update_offset + 1; +constant ex4_debug_int_en_offset : integer := ex4_debug_flush_en_offset + ex4_debug_flush_en_q'length; +constant ex4_flush_offset : integer := ex4_debug_int_en_offset + ex4_debug_int_en_q'length; +constant ex4_fpena_prog_int_offset : integer := ex4_flush_offset + ex4_flush_q'length; +constant ex4_iac1_cmpr_offset : integer := ex4_fpena_prog_int_offset + ex4_fpena_prog_int_q'length; +constant ex4_iac2_cmpr_offset : integer := ex4_iac1_cmpr_offset + ex4_iac1_cmpr_q'length; +constant ex4_iac3_cmpr_offset : integer := ex4_iac2_cmpr_offset + ex4_iac2_cmpr_q'length; +constant ex4_iac4_cmpr_offset : integer := ex4_iac3_cmpr_offset + ex4_iac3_cmpr_q'length; +constant ex4_instr_cpl_offset : integer := ex4_iac4_cmpr_offset + ex4_iac4_cmpr_q'length; +constant ex4_is_any_load_dac_offset : integer := ex4_instr_cpl_offset + ex4_instr_cpl_q'length; +constant ex4_is_any_store_dac_offset : integer := ex4_is_any_load_dac_offset + 1; +constant ex4_is_attn_offset : integer := ex4_is_any_store_dac_offset + 1; +constant ex4_is_dci_offset : integer := ex4_is_attn_offset + 1; +constant ex4_is_ehpriv_offset : integer := ex4_is_dci_offset + 1; +constant ex4_is_ici_offset : integer := ex4_is_ehpriv_offset + 1; +constant ex4_is_isync_offset : integer := ex4_is_ici_offset + 1; +constant ex4_is_mtmsr_offset : integer := ex4_is_isync_offset + 1; +constant ex4_is_tlbwe_offset : integer := ex4_is_mtmsr_offset + 1; +constant ex4_is_slowspr_wr_offset : integer := ex4_is_tlbwe_offset + 1; +constant ex4_lr_update_offset : integer := ex4_is_slowspr_wr_offset + 1; +constant ex4_mcsr_offset : integer := ex4_lr_update_offset + 1; +constant ex4_mem_attr_offset : integer := ex4_mcsr_offset + ex4_mcsr_q'length; +constant ex4_mmu_esr_data_offset : integer := ex4_mem_attr_offset + ex4_mem_attr_q'length; +constant ex4_mmu_esr_epid_offset : integer := ex4_mmu_esr_data_offset + ex4_mmu_esr_data_q'length; +constant ex4_mmu_esr_pt_offset : integer := ex4_mmu_esr_epid_offset + ex4_mmu_esr_epid_q'length; +constant ex4_mmu_esr_st_offset : integer := ex4_mmu_esr_pt_offset + ex4_mmu_esr_pt_q'length; +constant ex4_mmu_esr_val_offset : integer := ex4_mmu_esr_st_offset + ex4_mmu_esr_st_q'length; +constant ex4_mmu_hold_val_offset : integer := ex4_mmu_esr_val_offset + ex4_mmu_esr_val_q'length; +constant ex4_mtdp_nr_offset : integer := ex4_mmu_hold_val_offset + ex4_mmu_hold_val_q'length; +constant ex4_mtiar_offset : integer := ex4_mtdp_nr_offset + 1; +constant ex4_n_2ucode_flush_offset : integer := ex4_mtiar_offset + 1; +constant ex4_n_align_int_offset : integer := ex4_n_2ucode_flush_offset + ex4_n_2ucode_flush_q'length; +constant ex4_n_any_hpriv_int_offset : integer := ex4_n_align_int_offset + ex4_n_align_int_q'length; +constant ex4_n_any_unavail_int_offset : integer := ex4_n_any_hpriv_int_offset + ex4_n_any_hpriv_int_q'length; +constant ex4_n_ap_unavail_int_offset : integer := ex4_n_any_unavail_int_offset + ex4_n_any_unavail_int_q'length; +constant ex4_n_barr_flush_offset : integer := ex4_n_ap_unavail_int_offset + ex4_n_ap_unavail_int_q'length; +constant ex4_n_bclr_ta_miscmpr_flush_offset : integer := ex4_n_barr_flush_offset + ex4_n_barr_flush_q'length; +constant ex4_n_brt_dbg_cint_offset : integer := ex4_n_bclr_ta_miscmpr_flush_offset + ex4_n_bclr_ta_miscmpr_flush_q'length; +constant ex4_n_dac_dbg_cint_offset : integer := ex4_n_brt_dbg_cint_offset + ex4_n_brt_dbg_cint_q'length; +constant ex4_n_ddmh_mchk_en_offset : integer := ex4_n_dac_dbg_cint_offset + ex4_n_dac_dbg_cint_q'length; +constant ex4_n_dep_flush_offset : integer := ex4_n_ddmh_mchk_en_offset + ex4_n_ddmh_mchk_en_q'length; +constant ex4_n_deratre_par_mchk_mcint_offset : integer := ex4_n_dep_flush_offset + ex4_n_dep_flush_q'length; +constant ex4_n_dlk0_dstor_int_offset : integer := ex4_n_deratre_par_mchk_mcint_offset + ex4_n_deratre_par_mchk_mcint_q'length; +constant ex4_n_dlk1_dstor_int_offset : integer := ex4_n_dlk0_dstor_int_offset + ex4_n_dlk0_dstor_int_q'length; +constant ex4_n_dlrat_int_offset : integer := ex4_n_dlk1_dstor_int_offset + ex4_n_dlk1_dstor_int_q'length; +constant ex4_n_dmchk_mcint_offset : integer := ex4_n_dlrat_int_offset + ex4_n_dlrat_int_q'length; +constant ex4_n_dmiss_flush_offset : integer := ex4_n_dmchk_mcint_offset + ex4_n_dmchk_mcint_q'length; +constant ex4_n_dstor_int_offset : integer := ex4_n_dmiss_flush_offset + ex4_n_dmiss_flush_q'length; +constant ex4_n_dtlb_int_offset : integer := ex4_n_dstor_int_offset + ex4_n_dstor_int_q'length; +constant ex4_n_ena_prog_int_offset : integer := ex4_n_dtlb_int_offset + ex4_n_dtlb_int_q'length; +constant ex4_n_flush_offset : integer := ex4_n_ena_prog_int_offset + ex4_n_ena_prog_int_q'length; +constant ex4_n_pe_flush_offset : integer := ex4_n_flush_offset + ex4_n_flush_q'length; +constant ex4_n_tlb_mchk_flush_offset : integer := ex4_n_pe_flush_offset + ex4_n_pe_flush_q'length; +constant ex4_n_fp_unavail_int_offset : integer := ex4_n_tlb_mchk_flush_offset + ex4_n_tlb_mchk_flush_q'length; +constant ex4_n_fu_rfpe_flush_offset : integer := ex4_n_fp_unavail_int_offset + ex4_n_fp_unavail_int_q'length; +constant ex4_n_iac_dbg_cint_offset : integer := ex4_n_fu_rfpe_flush_offset + ex4_n_fu_rfpe_flush_q'length; +constant ex4_n_ieratre_par_mchk_mcint_offset : integer := ex4_n_iac_dbg_cint_offset + ex4_n_iac_dbg_cint_q'length; +constant ex4_n_ilrat_int_offset : integer := ex4_n_ieratre_par_mchk_mcint_offset + ex4_n_ieratre_par_mchk_mcint_q'length; +constant ex4_n_imchk_mcint_offset : integer := ex4_n_ilrat_int_offset + ex4_n_ilrat_int_q'length; +constant ex4_n_imiss_flush_offset : integer := ex4_n_imchk_mcint_offset + ex4_n_imchk_mcint_q'length; +constant ex4_n_instr_dbg_cint_offset : integer := ex4_n_imiss_flush_offset + ex4_n_imiss_flush_q'length; +constant ex4_n_istor_int_offset : integer := ex4_n_instr_dbg_cint_offset + ex4_n_instr_dbg_cint_q'length; +constant ex4_n_itlb_int_offset : integer := ex4_n_istor_int_offset + ex4_n_istor_int_q'length; +constant ex4_n_ivc_dbg_cint_offset : integer := ex4_n_itlb_int_offset + ex4_n_itlb_int_q'length; +constant ex4_n_ivc_dbg_match_offset : integer := ex4_n_ivc_dbg_cint_offset + ex4_n_ivc_dbg_cint_q'length; +constant ex4_n_ldq_hit_flush_offset : integer := ex4_n_ivc_dbg_match_offset + ex4_n_ivc_dbg_match_q'length; +constant ex4_n_lsu_ddmh_flush_en_offset : integer := ex4_n_ldq_hit_flush_offset + ex4_n_ldq_hit_flush_q'length; +constant ex4_n_lsu_flush_offset : integer := ex4_n_lsu_ddmh_flush_en_offset + ex4_n_lsu_ddmh_flush_en_q'length; +constant ex4_n_memattr_miscmpr_flush_offset : integer := ex4_n_lsu_flush_offset + ex4_n_lsu_flush_q'length; +constant ex4_n_mmu_hpriv_int_offset : integer := ex4_n_memattr_miscmpr_flush_offset + ex4_n_memattr_miscmpr_flush_q'length; +constant ex4_n_pil_prog_int_offset : integer := ex4_n_mmu_hpriv_int_offset + ex4_n_mmu_hpriv_int_q'length; +constant ex4_n_ppr_prog_int_offset : integer := ex4_n_pil_prog_int_offset + ex4_n_pil_prog_int_q'length; +constant ex4_n_ptemiss_dlrat_int_offset : integer := ex4_n_ppr_prog_int_offset + ex4_n_ppr_prog_int_q'length; +constant ex4_n_puo_prog_int_offset : integer := ex4_n_ptemiss_dlrat_int_offset + ex4_n_ptemiss_dlrat_int_q'length; +constant ex4_n_ret_dbg_cint_offset : integer := ex4_n_puo_prog_int_offset + ex4_n_puo_prog_int_q'length; +constant ex4_n_thrctl_stop_flush_offset : integer := ex4_n_ret_dbg_cint_offset + ex4_n_ret_dbg_cint_q'length; +constant ex4_n_tlbwemiss_dlrat_int_offset : integer := ex4_n_thrctl_stop_flush_offset + ex4_n_thrctl_stop_flush_q'length; +constant ex4_n_tlbwe_pil_prog_int_offset : integer := ex4_n_tlbwemiss_dlrat_int_offset + ex4_n_tlbwemiss_dlrat_int_q'length; +constant ex4_n_trap_dbg_cint_offset : integer := ex4_n_tlbwe_pil_prog_int_offset + ex4_n_tlbwe_pil_prog_int_q'length; +constant ex4_n_uct_dstor_int_offset : integer := ex4_n_trap_dbg_cint_offset + ex4_n_trap_dbg_cint_q'length; +constant ex4_n_vec_unavail_int_offset : integer := ex4_n_uct_dstor_int_offset + ex4_n_uct_dstor_int_q'length; +constant ex4_n_vf_dstor_int_offset : integer := ex4_n_vec_unavail_int_offset + ex4_n_vec_unavail_int_q'length; +constant ex4_n_xu_rfpe_flush_offset : integer := ex4_n_vf_dstor_int_offset + ex4_n_vf_dstor_int_q'length; +constant ex4_np1_cdbell_cint_offset : integer := ex4_n_xu_rfpe_flush_offset + ex4_n_xu_rfpe_flush_q'length; +constant ex4_np1_crit_cint_offset : integer := ex4_np1_cdbell_cint_offset + ex4_np1_cdbell_cint_q'length; +constant ex4_np1_dbell_int_offset : integer := ex4_np1_crit_cint_offset + ex4_np1_crit_cint_q'length; +constant ex4_np1_dec_int_offset : integer := ex4_np1_dbell_int_offset + ex4_np1_dbell_int_q'length; +constant ex4_np1_ext_int_offset : integer := ex4_np1_dec_int_offset + ex4_np1_dec_int_q'length; +constant ex4_np1_ext_mchk_mcint_offset : integer := ex4_np1_ext_int_offset + ex4_np1_ext_int_q'length; +constant ex4_np1_fit_int_offset : integer := ex4_np1_ext_mchk_mcint_offset + ex4_np1_ext_mchk_mcint_q'length; +constant ex4_np1_flush_offset : integer := ex4_np1_fit_int_offset + ex4_np1_fit_int_q'length; +constant ex4_np1_gcdbell_cint_offset : integer := ex4_np1_flush_offset + ex4_np1_flush_q'length; +constant ex4_np1_gdbell_int_offset : integer := ex4_np1_gcdbell_cint_offset + ex4_np1_gcdbell_cint_q'length; +constant ex4_np1_gmcdbell_cint_offset : integer := ex4_np1_gdbell_int_offset + ex4_np1_gdbell_int_q'length; +constant ex4_np1_ide_dbg_cint_offset : integer := ex4_np1_gmcdbell_cint_offset + ex4_np1_gmcdbell_cint_q'length; +constant ex4_np1_instr_int_offset : integer := ex4_np1_ide_dbg_cint_offset + ex4_np1_ide_dbg_cint_q'length; +constant ex4_np1_perf_int_offset : integer := ex4_np1_instr_int_offset + ex4_np1_instr_int_q'length; +constant ex4_np1_ptr_prog_int_offset : integer := ex4_np1_perf_int_offset + ex4_np1_perf_int_q'length; +constant ex4_np1_rfi_offset : integer := ex4_np1_ptr_prog_int_offset + ex4_np1_ptr_prog_int_q'length; +constant ex4_np1_run_ctl_flush_offset : integer := ex4_np1_rfi_offset + ex4_np1_rfi_q'length; +constant ex4_np1_sc_int_offset : integer := ex4_np1_run_ctl_flush_offset + ex4_np1_run_ctl_flush_q'length; +constant ex4_np1_ude_dbg_cint_offset : integer := ex4_np1_sc_int_offset + ex4_np1_sc_int_q'length; +constant ex4_np1_ude_dbg_event_offset : integer := ex4_np1_ude_dbg_cint_offset + ex4_np1_ude_dbg_cint_q'length; +constant ex4_np1_udec_int_offset : integer := ex4_np1_ude_dbg_event_offset + ex4_np1_ude_dbg_event_q'length; +constant ex4_np1_wdog_cint_offset : integer := ex4_np1_udec_int_offset + ex4_np1_udec_int_q'length; +constant ex4_np1_fu_flush_offset : integer := ex4_np1_wdog_cint_offset + ex4_np1_wdog_cint_q'length; +constant ex4_n_ieratsx_par_mchk_mcint_offset : integer := ex4_np1_fu_flush_offset + ex4_np1_fu_flush_q'length; +constant ex4_n_tlbmh_mchk_mcint_offset : integer := ex4_n_ieratsx_par_mchk_mcint_offset + ex4_n_ieratsx_par_mchk_mcint_q'length; +constant ex4_n_sprg_ue_flush_offset : integer := ex4_n_tlbmh_mchk_mcint_offset + ex4_n_tlbmh_mchk_mcint_q'length; +constant ex4_n_rwaccess_dstor_int_offset : integer := ex4_n_sprg_ue_flush_offset + ex4_n_sprg_ue_flush_q'length; +constant ex4_n_exaccess_istor_int_offset : integer := ex4_n_rwaccess_dstor_int_offset + ex4_n_rwaccess_dstor_int_q'length; +constant ex4_sc_lev_offset : integer := ex4_n_exaccess_istor_int_offset + ex4_n_exaccess_istor_int_q'length; +constant ex4_siar_sel_offset : integer := ex4_sc_lev_offset + 1; +constant ex4_step_offset : integer := ex4_siar_sel_offset + ex4_siar_sel_q'length; +constant ex4_taken_bclr_offset : integer := ex4_step_offset + ex4_step_q'length; +constant ex4_tlb_inelig_offset : integer := ex4_taken_bclr_offset + 1; +constant ex4_ucode_val_offset : integer := ex4_tlb_inelig_offset + ex4_tlb_inelig_q'length; +constant ex4_xu_is_ucode_offset : integer := ex4_ucode_val_offset + ex4_ucode_val_q'length; +constant ex4_xu_val_offset : integer := ex4_xu_is_ucode_offset + 1; +constant ex4_cia_act_offset : integer := ex4_xu_val_offset + ex4_xu_val_q'length; +constant ex4_n_async_dacr_dbg_cint_offset : integer := ex4_cia_act_offset + ex4_cia_act_q'length; +constant ex4_dac1r_cmpr_async_offset : integer := ex4_n_async_dacr_dbg_cint_offset + ex4_n_async_dacr_dbg_cint_q'length; +constant ex4_dac2r_cmpr_async_offset : integer := ex4_dac1r_cmpr_async_offset + ex4_dac1r_cmpr_async_q'length; +constant ex4_thread_stop_offset : integer := ex4_dac2r_cmpr_async_offset + ex4_dac2r_cmpr_async_q'length; +constant ex5_icmp_event_on_int_ok_offset : integer := ex4_thread_stop_offset + ex4_thread_stop_q'length; +constant ex5_any_val_offset : integer := ex5_icmp_event_on_int_ok_offset + ex5_icmp_event_on_int_ok_q'length; +constant ex5_attn_flush_offset : integer := ex5_any_val_offset + ex5_any_val_q'length; +constant ex5_axu_trap_pie_offset : integer := ex5_attn_flush_offset + ex5_attn_flush_q'length; +constant ex5_br_taken_offset : integer := ex5_axu_trap_pie_offset + ex5_axu_trap_pie_q'length; +constant ex5_cdbell_taken_offset : integer := ex5_br_taken_offset + 1; +constant ex5_check_bclr_offset : integer := ex5_cdbell_taken_offset + ex5_cdbell_taken_q'length; +constant ex5_cia_p1_offset : integer := ex5_check_bclr_offset + ex5_check_bclr_q'length; +constant ex5_dbell_taken_offset : integer := ex5_cia_p1_offset + ex5_cia_p1_q'length; +constant ex5_dbsr_update_offset : integer := ex5_dbell_taken_offset + ex5_dbell_taken_q'length; +constant ex5_dear_update_saved_offset : integer := ex5_dbsr_update_offset + ex5_dbsr_update_q'length; +constant ex5_deratre_par_err_offset : integer := ex5_dear_update_saved_offset + ex5_dear_update_saved_q'length; +constant ex5_div_set_barr_offset : integer := ex5_deratre_par_err_offset + ex5_deratre_par_err_q'length; +constant ex5_dsigs_offset : integer := ex5_div_set_barr_offset + ex5_div_set_barr_q'length; +constant ex5_dtlbgs_offset : integer := ex5_dsigs_offset + ex5_dsigs_q'length; +constant ex5_err_nia_miscmpr_offset : integer := ex5_dtlbgs_offset + ex5_dtlbgs_q'length; +constant ex5_ext_dbg_err_offset : integer := ex5_err_nia_miscmpr_offset + ex5_err_nia_miscmpr_q'length; +constant ex5_ext_dbg_ext_offset : integer := ex5_ext_dbg_err_offset + ex5_ext_dbg_err_q'length; +constant ex5_extgs_offset : integer := ex5_ext_dbg_ext_offset + ex5_ext_dbg_ext_q'length; +constant ex5_flush_offset : integer := ex5_extgs_offset + ex5_extgs_q'length; +constant ex5_force_gsrr_offset : integer := ex5_flush_offset + ex5_flush_q'length; +constant ex5_gcdbell_taken_offset : integer := ex5_force_gsrr_offset + ex5_force_gsrr_q'length; +constant ex5_gdbell_taken_offset : integer := ex5_gcdbell_taken_offset + ex5_gcdbell_taken_q'length; +constant ex5_gmcdbell_taken_offset : integer := ex5_gdbell_taken_offset + ex5_gdbell_taken_q'length; +constant ex5_ieratre_par_err_offset : integer := ex5_gmcdbell_taken_offset + ex5_gmcdbell_taken_q'length; +constant ex5_in_ucode_offset : integer := ex5_ieratre_par_err_offset + ex5_ieratre_par_err_q'length; +constant ex5_instr_cpl_offset : integer := ex5_in_ucode_offset + ex5_in_ucode_q'length; +constant ex5_is_any_rfi_offset : integer := ex5_instr_cpl_offset + ex5_instr_cpl_q'length; +constant ex5_is_attn_offset : integer := ex5_is_any_rfi_offset + ex5_is_any_rfi_q'length; +constant ex5_is_crit_int_offset : integer := ex5_is_attn_offset + ex5_is_attn_q'length; +constant ex5_is_mchk_int_offset : integer := ex5_is_crit_int_offset + ex5_is_crit_int_q'length; +constant ex5_is_mtmsr_offset : integer := ex5_is_mchk_int_offset + ex5_is_mchk_int_q'length; +constant ex5_is_isync_offset : integer := ex5_is_mtmsr_offset + 1; +constant ex5_is_tlbwe_offset : integer := ex5_is_isync_offset + 1; +constant ex5_isigs_offset : integer := ex5_is_tlbwe_offset + 1; +constant ex5_itlbgs_offset : integer := ex5_isigs_offset + ex5_isigs_q'length; +constant ex5_lsu_set_barr_offset : integer := ex5_itlbgs_offset + ex5_itlbgs_q'length; +constant ex5_mem_attr_val_offset : integer := ex5_lsu_set_barr_offset + ex5_lsu_set_barr_q'length; +constant ex5_mmu_hold_val_offset : integer := ex5_mem_attr_val_offset + ex5_mem_attr_val_q'length; +constant ex5_n_dmiss_flush_offset : integer := ex5_mmu_hold_val_offset + ex5_mmu_hold_val_q'length; +constant ex5_n_ext_dbg_stopc_flush_offset : integer := ex5_n_dmiss_flush_offset + ex5_n_dmiss_flush_q'length; +constant ex5_n_ext_dbg_stopt_flush_offset : integer := ex5_n_ext_dbg_stopc_flush_offset + 1; +constant ex5_n_imiss_flush_offset : integer := ex5_n_ext_dbg_stopt_flush_offset + ex5_n_ext_dbg_stopt_flush_q'length; +constant ex5_n_ptemiss_dlrat_int_offset : integer := ex5_n_imiss_flush_offset + ex5_n_imiss_flush_q'length; +constant ex5_np1_icmp_dbg_cint_offset : integer := ex5_n_ptemiss_dlrat_int_offset + ex5_n_ptemiss_dlrat_int_q'length; +constant ex5_np1_icmp_dbg_event_offset : integer := ex5_np1_icmp_dbg_cint_offset + ex5_np1_icmp_dbg_cint_q'length; +constant ex5_np1_run_ctl_flush_offset : integer := ex5_np1_icmp_dbg_event_offset + ex5_np1_icmp_dbg_event_q'length; +constant ex5_dbsr_ide_offset : integer := ex5_np1_run_ctl_flush_offset + ex5_np1_run_ctl_flush_q'length; +constant ex5_perf_dtlb_offset : integer := ex5_dbsr_ide_offset + ex5_dbsr_ide_q'length; +constant ex5_perf_itlb_offset : integer := ex5_perf_dtlb_offset + ex5_perf_dtlb_q'length; +constant ex5_ram_done_offset : integer := ex5_perf_itlb_offset + ex5_perf_itlb_q'length; +constant ex5_ram_issue_offset : integer := ex5_ram_done_offset + 1; +constant ex5_rt_offset : integer := ex5_ram_issue_offset + ex5_ram_issue_q'length; +constant ex5_sel_rt_offset : integer := ex5_rt_offset + ex5_rt_q'length; +constant ex5_srr0_dec_offset : integer := ex5_sel_rt_offset + ex5_sel_rt_q'length; +constant ex5_tlb_inelig_offset : integer := ex5_srr0_dec_offset + ex5_srr0_dec_q'length; +constant ex5_uc_cia_val_offset : integer := ex5_tlb_inelig_offset + ex5_tlb_inelig_q'length; +constant ex5_xu_ifar_offset : integer := ex5_uc_cia_val_offset + ex5_uc_cia_val_q'length; +constant ex5_xu_val_offset : integer := ex5_xu_ifar_offset + ex5_xu_ifar_q'length; +constant ex5_n_flush_sprg_ue_flush_offset : integer := ex5_xu_val_offset + ex5_xu_val_q'length; +constant ex5_mcsr_act_offset : integer := ex5_n_flush_sprg_ue_flush_offset + ex5_n_flush_sprg_ue_flush_q'length; +constant ex6_mcsr_act_offset : integer := ex5_mcsr_act_offset + ex5_mcsr_act_q'length; +constant ex6_ram_done_offset : integer := ex6_mcsr_act_offset + 1; +constant ex6_ram_interrupt_offset : integer := ex6_ram_done_offset + 1; +constant ex6_ram_issue_offset : integer := ex6_ram_interrupt_offset + 1; +constant ex7_ram_issue_offset : integer := ex6_ram_issue_offset + ex6_ram_issue_q'length; +constant ex8_ram_issue_offset : integer := ex7_ram_issue_offset + ex7_ram_issue_q'length; +constant ex6_step_done_offset : integer := ex8_ram_issue_offset + ex8_ram_issue_q'length; +constant ex6_xu_val_offset : integer := ex6_step_done_offset + ex6_step_done_q'length; +constant ex7_is_tlbwe_offset : integer := ex6_xu_val_offset + ex6_xu_val_q'length; +constant ex8_is_tlbwe_offset : integer := ex7_is_tlbwe_offset + ex7_is_tlbwe_q'length; +constant ccr2_ap_offset : integer := ex8_is_tlbwe_offset + ex8_is_tlbwe_q'length; +constant cpl_quiesced_offset : integer := ccr2_ap_offset + ccr2_ap_q'length; +constant dbcr0_idm_offset : integer := cpl_quiesced_offset + cpl_quiesced_q'length; +constant dci_val_offset : integer := dbcr0_idm_offset + dbcr0_idm_q'length; +constant debug_event_en_offset : integer := dci_val_offset + 1; +constant derat_hold_present_offset : integer := debug_event_en_offset + debug_event_en_q'length; +constant ext_dbg_act_err_offset : integer := derat_hold_present_offset + derat_hold_present_q'length; +constant ext_dbg_act_ext_offset : integer := ext_dbg_act_err_offset + ext_dbg_act_err_q'length; +constant ext_dbg_stop_core_offset : integer := ext_dbg_act_ext_offset + ext_dbg_act_ext_q'length; +constant ext_dbg_stop_n_offset : integer := ext_dbg_stop_core_offset + ext_dbg_stop_core_q'length; +constant external_mchk_offset : integer := ext_dbg_stop_n_offset + ext_dbg_stop_n_q'length; +constant exx_multi_flush_offset : integer := external_mchk_offset + external_mchk_q'length; +constant force_ude_offset : integer := exx_multi_flush_offset + exx_multi_flush_q'length; +constant fu_rf_seq_end_offset : integer := force_ude_offset + force_ude_q'length; +constant fu_rfpe_ack_offset : integer := fu_rf_seq_end_offset + 1; +constant fu_rfpe_hold_present_offset : integer := fu_rfpe_ack_offset + fu_rfpe_ack_q'length; +constant ici_hold_present_offset : integer := fu_rfpe_hold_present_offset + 1; +constant ici_val_offset : integer := ici_hold_present_offset + ici_hold_present_q'length; +constant ierat_hold_present_offset : integer := ici_val_offset + 1; +constant mmu_eratmiss_done_offset : integer := ierat_hold_present_offset + ierat_hold_present_q'length; +constant mmu_hold_present_offset : integer := mmu_eratmiss_done_offset + mmu_eratmiss_done_q'length; +constant mmu_hold_request_offset : integer := mmu_hold_present_offset + mmu_hold_present_q'length; +constant msr_cm_offset : integer := mmu_hold_request_offset + mmu_hold_request_q'length; +constant msr_de_offset : integer := msr_cm_offset + msr_cm_q'length; +constant msr_fp_offset : integer := msr_de_offset + msr_de_q'length; +constant msr_gs_offset : integer := msr_fp_offset + msr_fp_q'length; +constant msr_me_offset : integer := msr_gs_offset + msr_gs_q'length; +constant msr_pr_offset : integer := msr_me_offset + msr_me_q'length; +constant msr_spv_offset : integer := msr_pr_offset + msr_pr_q'length; +constant msr_ucle_offset : integer := msr_spv_offset + msr_spv_q'length; +constant msrp_uclep_offset : integer := msr_ucle_offset + msr_ucle_q'length; +constant pc_dbg_action_offset : integer := msrp_uclep_offset + msrp_uclep_q'length; +constant pc_dbg_stop_offset : integer := pc_dbg_action_offset + pc_dbg_action_q'length; +constant pc_dbg_stop_2_offset : integer := pc_dbg_stop_offset + pc_dbg_stop_q'length; +constant pc_err_mcsr_rpt_offset : integer := pc_dbg_stop_2_offset + pc_dbg_stop_2_q'length; +constant pc_err_mcsr_summary_offset : integer := pc_err_mcsr_rpt_offset + pc_err_mcsr_rpt_q'length; +constant pc_init_reset_offset : integer := pc_err_mcsr_summary_offset + pc_err_mcsr_summary_q'length; +constant quiesced_offset : integer := pc_init_reset_offset + 1; +constant ram_flush_offset : integer := quiesced_offset + 1; +constant ram_ip_offset : integer := ram_flush_offset + ram_flush_q'length; +constant ram_mode_offset : integer := ram_ip_offset + ram_ip_q'length; +constant slowspr_flush_offset : integer := ram_mode_offset + ram_mode_q'length; +constant spr_cpl_async_int_offset : integer := slowspr_flush_offset + slowspr_flush_q'length; +constant ram_execute_offset : integer := spr_cpl_async_int_offset + spr_cpl_async_int_q'length; +constant ssprwr_ip_offset : integer := ram_execute_offset + ram_execute_q'length; +constant exx_cm_hold_offset : integer := ssprwr_ip_offset + ssprwr_ip_q'length; +constant xu_ex1_n_flush_offset : integer := exx_cm_hold_offset + exx_cm_hold_q'length; +constant xu_ex1_s_flush_offset : integer := xu_ex1_n_flush_offset + xu_ex1_n_flush_q'length; +constant xu_ex1_w_flush_offset : integer := xu_ex1_s_flush_offset + xu_ex1_s_flush_q'length; +constant xu_ex2_n_flush_offset : integer := xu_ex1_w_flush_offset + xu_ex1_w_flush_q'length; +constant xu_ex2_s_flush_offset : integer := xu_ex2_n_flush_offset + xu_ex2_n_flush_q'length; +constant xu_ex2_w_flush_offset : integer := xu_ex2_s_flush_offset + xu_ex2_s_flush_q'length; +constant xu_ex3_n_flush_offset : integer := xu_ex2_w_flush_offset + xu_ex2_w_flush_q'length; +constant xu_ex3_s_flush_offset : integer := xu_ex3_n_flush_offset + xu_ex3_n_flush_q'length; +constant xu_ex3_w_flush_offset : integer := xu_ex3_s_flush_offset + xu_ex3_s_flush_q'length; +constant xu_ex4_n_flush_offset : integer := xu_ex3_w_flush_offset + xu_ex3_w_flush_q'length; +constant xu_ex4_s_flush_offset : integer := xu_ex4_n_flush_offset + xu_ex4_n_flush_q'length; +constant xu_ex4_w_flush_offset : integer := xu_ex4_s_flush_offset + xu_ex4_s_flush_q'length; +constant xu_ex5_n_flush_offset : integer := xu_ex4_w_flush_offset + xu_ex4_w_flush_q'length; +constant xu_ex5_s_flush_offset : integer := xu_ex5_n_flush_offset + xu_ex5_n_flush_q'length; +constant xu_ex5_w_flush_offset : integer := xu_ex5_s_flush_offset + xu_ex5_s_flush_q'length; +constant xu_is2_n_flush_offset : integer := xu_ex5_w_flush_offset + xu_ex5_w_flush_q'length; +constant xu_rf0_n_flush_offset : integer := xu_is2_n_flush_offset + xu_is2_n_flush_q'length; +constant xu_rf1_n_flush_offset : integer := xu_rf0_n_flush_offset + xu_rf0_n_flush_q'length; +constant xu_rf1_s_flush_offset : integer := xu_rf1_n_flush_offset + xu_rf1_n_flush_q'length; +constant xu_rf1_w_flush_offset : integer := xu_rf1_s_flush_offset + xu_rf1_s_flush_q'length; +constant ex5_np1_irpt_dbg_cint_offset : integer := xu_rf1_w_flush_offset + xu_rf1_w_flush_q'length; +constant ex6_np1_irpt_dbg_cint_offset : integer := ex5_np1_irpt_dbg_cint_offset + ex5_np1_irpt_dbg_cint_q'length; +constant ex5_np1_irpt_dbg_event_offset : integer := ex6_np1_irpt_dbg_cint_offset + ex6_np1_irpt_dbg_cint_q'length; +constant ex6_np1_irpt_dbg_event_offset : integer := ex5_np1_irpt_dbg_event_offset + ex5_np1_irpt_dbg_event_q'length; +constant clkg_ctl_offset : integer := ex6_np1_irpt_dbg_event_offset + ex6_np1_irpt_dbg_event_q'length; +constant xu_rf_seq_end_offset : integer := clkg_ctl_offset + 1; +constant xu_rfpe_ack_offset : integer := xu_rf_seq_end_offset + 1; +constant xu_rfpe_hold_present_offset : integer := xu_rfpe_ack_offset + xu_rfpe_ack_q'length; +constant exx_act_offset : integer := xu_rfpe_hold_present_offset + 1; +constant ex4_mchk_int_en_offset : integer := exx_act_offset + exx_act_q'length; +constant ex5_mchk_int_en_offset : integer := ex4_mchk_int_en_offset + ex4_mchk_int_en_q'length; +constant trace_bus_enable_offset : integer := ex5_mchk_int_en_offset + ex5_mchk_int_en_q'length; +constant ex1_instr_trace_type_offset : integer := trace_bus_enable_offset + 1; +constant ex1_instr_trace_val_offset : integer := ex1_instr_trace_type_offset + ex1_instr_trace_type_q'length; +constant ex1_xu_issued_offset : integer := ex1_instr_trace_val_offset + 1; +constant ex2_xu_issued_offset : integer := ex1_xu_issued_offset + ex1_xu_issued_q'length; +constant ex3_xu_issued_offset : integer := ex2_xu_issued_offset + ex2_xu_issued_q'length; +constant ex4_xu_issued_offset : integer := ex3_xu_issued_offset + ex3_xu_issued_q'length; +constant ex3_axu_issued_offset : integer := ex4_xu_issued_offset + ex4_xu_issued_q'length; +constant ex4_axu_issued_offset : integer := ex3_axu_issued_offset + ex3_axu_issued_q'length; +constant ex2_instr_dbg_offset : integer := ex4_axu_issued_offset + ex4_axu_issued_q'length; +constant ex2_instr_trace_type_offset : integer := ex2_instr_dbg_offset + ex2_instr_dbg_q'length; +constant ex4_instr_trace_val_offset : integer := ex2_instr_trace_type_offset + ex2_instr_trace_type_q'length; +constant ex5_instr_trace_val_offset : integer := ex4_instr_trace_val_offset + 1; +constant ex5_siar_offset : integer := ex5_instr_trace_val_offset + 1; +constant ex5_siar_cpl_offset : integer := ex5_siar_offset + ex5_siar_q'length; +constant ex5_siar_gs_offset : integer := ex5_siar_cpl_offset + 1; +constant ex5_siar_issued_offset : integer := ex5_siar_gs_offset + 1; +constant ex5_siar_pr_offset : integer := ex5_siar_issued_offset + 1; +constant ex5_siar_tid_offset : integer := ex5_siar_pr_offset + 1; +constant ex5_ucode_end_dbg_offset : integer := ex5_siar_tid_offset + ex5_siar_tid_q'length; +constant ex5_ucode_val_dbg_offset : integer := ex5_ucode_end_dbg_offset + ex5_ucode_end_dbg_q'length; +constant instr_trace_mode_offset : integer := ex5_ucode_val_dbg_offset + ex5_ucode_val_dbg_q'length; +constant debug_data_out_offset : integer := instr_trace_mode_offset + 1; +constant debug_mux_ctrls_offset : integer := debug_data_out_offset + debug_data_out_q'length; +constant debug_mux_ctrls_int_offset : integer := debug_mux_ctrls_offset + debug_mux_ctrls_q'length; +constant trigger_data_out_offset : integer := debug_mux_ctrls_int_offset + debug_mux_ctrls_int_q'length; +constant event_bus_enable_offset : integer := trigger_data_out_offset + trigger_data_out_q'length; +constant ex3_perf_event_offset : integer := event_bus_enable_offset + 1; +constant ex5_perf_event_offset : integer := ex3_perf_event_offset + ex3_perf_event_q'length; +constant spr_bit_act_offset : integer := ex5_perf_event_offset + ex5_perf_event_q'length; +constant spare_0_offset : integer := spr_bit_act_offset + 1; +constant spare_1_offset : integer := spare_0_offset + spare_0_q'length; +constant spare_2_offset : integer := spare_1_offset + spare_1_q'length; +constant spare_3_offset : integer := spare_2_offset + spare_2_q'length; +constant spare_4_offset : integer := spare_3_offset + spare_3_q'length; +constant spare_5_offset : integer := spare_4_offset + spare_4_q'length; + +constant exx_instr_async_block_offset : integer := spare_5_offset + spare_5_q'length; +constant ex5_late_flush_offset : integer := exx_instr_async_block_offset + exx_instr_async_block_q(0)'length*threads; +constant ex5_esr_offset : integer := ex5_late_flush_offset + ifar_repwr*threads; +constant ex5_dbsr_offset : integer := ex5_esr_offset + ex5_esr_q'length; +constant ex5_mcsr_offset : integer := ex5_dbsr_offset + ex5_dbsr_q'length; +constant ex4_uc_cia_offset : integer := ex5_mcsr_offset + ex5_mcsr_q'length; +constant ex4_axu_instr_type_offset : integer := ex4_uc_cia_offset + IFAR_UC'length*threads; +constant ex5_mem_attr_offset : integer := ex4_axu_instr_type_offset + 3*threads; +constant ex5_ivo_sel_offset : integer := ex5_mem_attr_offset + ex4_mem_attr_q'length*threads; +constant ex5_nia_b_offset : integer := ex5_ivo_sel_offset + ivos*threads; +constant ex2_ifar_b_offset : integer := ex5_nia_b_offset + eff_ifar*threads; +constant ex3_ifar_offset : integer := ex2_ifar_b_offset + eff_ifar*threads; +constant ex4_ifar_offset : integer := ex3_ifar_offset + eff_ifar*threads; +constant ex4_epid_instr_offset : integer := ex4_ifar_offset + eff_ifar*threads; +constant ex4_is_any_store_offset : integer := ex4_epid_instr_offset + ex4_epid_instr_q'length; +constant ex5_flush_2ucode_offset : integer := ex4_is_any_store_offset + ex4_is_any_store_q'length; +constant ex5_ucode_restart_offset : integer := ex5_flush_2ucode_offset + ex5_flush_2ucode_q'length; +constant ex5_mem_attr_le_offset : integer := ex5_ucode_restart_offset + ex5_ucode_restart_q'length; +constant ex5_cm_hold_cond_offset : integer := ex5_mem_attr_le_offset + ex5_mem_attr_le_q'length; +constant ex3_async_int_block_cond_offset : integer := ex5_cm_hold_cond_offset + 1; +constant ex3_base_int_block_offset : integer := ex3_async_int_block_cond_offset+ 1; +constant ex3_mchk_int_block_offset : integer := ex3_base_int_block_offset + 1; +constant exx_thread_stop_mcflush_offset : integer := ex3_mchk_int_block_offset + 1; +constant exx_lateflush_mcflush_offset : integer := exx_thread_stop_mcflush_offset + 1; +constant exx_csi_mcflush_offset : integer := exx_lateflush_mcflush_offset + 1; +constant exx_hold0_mcflush_offset : integer := exx_csi_mcflush_offset + 1; +constant exx_hold1_mcflush_offset : integer := exx_hold0_mcflush_offset + 1; +constant exx_barr_mcflush_offset : integer := exx_hold1_mcflush_offset + 1; +constant rfpe_quiesce_offset : integer := exx_barr_mcflush_offset + 1; +constant scan_right : integer := rfpe_quiesce_offset + 1; +signal siv : std_ulogic_vector(0 to scan_right-1); +signal sov : std_ulogic_vector(0 to scan_right-1); +signal siv_3 : std_ulogic_vector(0 to 1); +signal sov_3 : std_ulogic_vector(0 to 1); +constant dd1_clk_override_offset_ccfg : integer := 0; +constant scan_right_ccfg : integer := dd1_clk_override_offset_ccfg + 1; +signal siv_ccfg : std_ulogic_vector(0 to scan_right_ccfg-1); +signal sov_ccfg : std_ulogic_vector(0 to scan_right_ccfg-1); +constant ex4_cia_b_offset_bcfg : integer := 0; +constant mcsr_rpt_offset_bcfg : integer := ex4_cia_b_offset_bcfg + IFAR'length*threads; +constant mcsr_rpt2_offset_bcfg : integer := mcsr_rpt_offset_bcfg + pc_err_mcsr_rpt_q'length*threads; +constant scan_right_bcfg : integer := mcsr_rpt2_offset_bcfg + pc_err_mcsr_rpt_q'length*threads; +signal siv_bcfg : std_ulogic_vector(0 to scan_right_bcfg-1); +signal sov_bcfg : std_ulogic_vector(0 to scan_right_bcfg-1); +constant scan_right_dcfg : integer := 1; +signal siv_dcfg : std_ulogic_vector(0 to scan_right_dcfg-1); +signal sov_dcfg : std_ulogic_vector(0 to scan_right_dcfg-1); +-- Signals +signal tiup, tidn : std_ulogic; +-- Valids +signal rf1_xu_val : std_ulogic_vector(0 to threads-1); +signal ex1_xu_val : std_ulogic_vector(0 to threads-1); +signal ex2_xu_val : std_ulogic_vector(0 to threads-1); +signal ex3_xu_val : std_ulogic_vector(0 to threads-1); +signal ex4_xu_val : std_ulogic_vector(0 to threads-1); +signal ex2_axu_val : std_ulogic_vector(0 to threads-1); +signal ex3_axu_val : std_ulogic_vector(0 to threads-1); +signal ex4_axu_val : std_ulogic_vector(0 to threads-1); +signal ex3_any_val : std_ulogic_vector(0 to threads-1); +signal ex4_any_val : std_ulogic_vector(0 to threads-1); +signal ex3_anyuc_val : std_ulogic_vector(0 to threads-1); +signal ex4_anyuc_val : std_ulogic_vector(0 to threads-1); +signal ex3_anyuc_val_q : std_ulogic_vector(0 to threads-1); +signal ex4_anyuc_val_q : std_ulogic_vector(0 to threads-1); +signal rf1_ucode_val : std_ulogic_vector(0 to threads-1); +signal ex1_ucode_val : std_ulogic_vector(0 to threads-1); +signal ex2_ucode_val : std_ulogic_vector(0 to threads-1); +signal ex3_ucode_val : std_ulogic_vector(0 to threads-1); +signal ex4_ucode_val : std_ulogic_vector(0 to threads-1); +signal ex3_xuuc_val_q : std_ulogic_vector(0 to threads-1); +signal ex4_xuuc_val_q : std_ulogic_vector(0 to threads-1); +signal ex3_xuuc_val : std_ulogic_vector(0 to threads-1); +signal ex4_xuuc_val : std_ulogic_vector(0 to threads-1); +signal ex3_dep_val : std_ulogic_vector(0 to threads-1); +-- Flushes +signal iu_flush : std_ulogic_vector(0 to threads-1); +signal any_flush : std_ulogic_vector(0 to threads-1); +signal is2_flush : std_ulogic_vector(0 to threads-1); +signal rf0_flush : std_ulogic_vector(0 to threads-1); +signal rf1_flush : std_ulogic_vector(0 to threads-1); +signal ex1_flush : std_ulogic_vector(0 to threads-1); +signal ex2_flush : std_ulogic_vector(0 to threads-1); +signal ex3_flush : std_ulogic_vector(0 to threads-1); +signal ex4_flush : std_ulogic_vector(0 to threads-1); +-- Other Stuff +signal spare_0_lclk : clk_logic; +signal spare_1_lclk : clk_logic; +signal spare_2_lclk : clk_logic; +signal spare_3_lclk : clk_logic; +signal spare_4_lclk : clk_logic; +signal spare_5_lclk : clk_logic; +signal spare_0_d1clk, spare_0_d2clk : std_ulogic; +signal spare_1_d1clk, spare_1_d2clk : std_ulogic; +signal spare_2_d1clk, spare_2_d2clk : std_ulogic; +signal spare_3_d1clk, spare_3_d2clk : std_ulogic; +signal spare_4_d1clk, spare_4_d2clk : std_ulogic; +signal spare_5_d1clk, spare_5_d2clk : std_ulogic; +signal func_scan_rpwr2_in : std_ulogic_vector(3 to 3); +signal func_scan_rpwr_in, func_scan_rpwr_out : std_ulogic_vector(0 to 3); +signal func_scan_out_gate : std_ulogic_vector(50 to 53); +signal ccfg_scan_rpwr_in, ccfg_scan_rpwr_out : std_ulogic_vector(0 to 0); +signal ccfg_scan_out_gate : std_ulogic_vector(0 to 0); +signal bcfg_scan_rpwr_in, bcfg_scan_rpwr_out : std_ulogic_vector(0 to 0); +signal bcfg_scan_out_gate : std_ulogic_vector(0 to 0); +signal dcfg_scan_rpwr_in, dcfg_scan_rpwr_out : std_ulogic_vector(0 to 0); +signal dcfg_scan_out_gate : std_ulogic_vector(0 to 0); +signal mcsr_bcfg_slp_sl_d1clk : std_ulogic; +signal mcsr_bcfg_slp_sl_d2clk : std_ulogic; +signal mcsr_bcfg_slp_sl_lclk : clk_logic; +signal bcfg_so_d2clk : std_ulogic; +signal bcfg_so_lclk : clk_logic; +signal func_slp_sl_thold_1 : std_ulogic; +signal func_slp_nsl_thold_1 : std_ulogic; +signal func_sl_thold_1 : std_ulogic; +signal func_nsl_thold_1 : std_ulogic; +signal cfg_sl_thold_1 : std_ulogic; +signal cfg_slp_sl_thold_1 : std_ulogic; +signal fce_1 : std_ulogic; +signal sg_1 : std_ulogic; +signal func_slp_sl_thold_0 : std_ulogic; +signal func_slp_nsl_thold_0 : std_ulogic; +signal func_sl_thold_0 : std_ulogic; +signal func_nsl_thold_0 : std_ulogic; +signal cfg_sl_thold_0 : std_ulogic; +signal cfg_slp_sl_thold_0 : std_ulogic; +signal fce_0 : std_ulogic; +signal sg_0 : std_ulogic; +signal cfg_sl_force : std_ulogic; +signal cfg_sl_thold_0_b : std_ulogic; +signal bcfg_sl_force : std_ulogic; +signal bcfg_sl_thold_0_b : std_ulogic; +signal dcfg_sl_force : std_ulogic; +signal dcfg_sl_thold_0_b : std_ulogic; +signal cfg_slp_sl_force : std_ulogic; +signal cfg_slp_sl_thold_0_b : std_ulogic; +signal bcfg_slp_sl_force : std_ulogic; +signal bcfg_slp_sl_thold_0_b : std_ulogic; +signal func_sl_force : std_ulogic; +signal func_sl_thold_0_b : std_ulogic; +signal func_nsl_force : std_ulogic; +signal func_nsl_thold_0_b : std_ulogic; +signal func_slp_sl_force : std_ulogic; +signal func_slp_sl_thold_0_b : std_ulogic; +signal func_slp_nsl_force : std_ulogic; +signal func_slp_nsl_thold_0_b : std_ulogic; +signal so_force : std_ulogic; +signal ccfg_so_thold_0_b : std_ulogic; +signal bcfg_so_thold_0_b : std_ulogic; +signal dcfg_so_thold_0_b : std_ulogic; +signal func_so_thold_0_b : std_ulogic; +signal rf1_is_ldbrx, rf1_is_lwbrx, rf1_is_lhbrx : std_ulogic; +signal rf1_is_stdbrx, rf1_is_stwbrx, rf1_is_sthbrx : std_ulogic; +signal rf1_is_icblc, rf1_is_icbtls : std_ulogic; +signal rf1_is_dcblc, rf1_is_dcbtls, rf1_is_dcbtstls : std_ulogic; +signal rf1_is_wait, rf1_is_eratre : std_ulogic; +signal ex4_np1_mtiar_flush, ex3_np1_mtiar_flush : std_ulogic_vector(0 to threads-1); +signal ex1_instr : std_ulogic_vector(0 to 31); +signal ex1_branch,ex1_br_mispred,ex1_br_taken : std_ulogic; +signal ex1_br_update, ex1_is_bclr : std_ulogic; +signal ex1_lr_update, ex1_ctr_dec_update : std_ulogic; +signal ex1_taken_bclr : std_ulogic; +signal ex1_xu_ifar : IFAR; +signal ex1_ifar_sel, ex1_ifar_sel_b : std_ulogic_vector(ex2_ifar_b_q'range); +signal ex2_br_flush : std_ulogic_vector(0 to threads-1); +signal ex2_br_flush_ifar : IFAR; +signal ex2_ifar : std_ulogic_vector(ex2_ifar_b_q'range); +signal ex4_cia_cmpr : std_ulogic_vector(0 to threads-1); +signal ex3_lr_cmprh, ex3_lr_cmprl : std_ulogic_vector(0 to threads-1); +signal ex3_cia_cmprh, ex3_cia_cmprl : std_ulogic_vector(0 to threads-1); +signal ex4_cia_cmprh, ex4_cia_cmprl : std_ulogic_vector(0 to threads-1); +signal ex3_bclr_cmpr_b : std_ulogic_vector(0 to threads-1); +signal ex4_taken_bclr, ex5_check_bclr : std_ulogic_vector(0 to threads-1); +signal ex4_ucode_end : std_ulogic_vector(0 to threads-1); +signal ex3_async_int_block : std_ulogic_vector(0 to threads-1); +signal ex3_async_int_block_noaxu : std_ulogic_vector(0 to threads-1); +signal ex3_base_int_block : std_ulogic_vector(0 to threads-1); +signal ex3_mchk_int_block : std_ulogic_vector(0 to threads-1); +signal ex3_esr_bit_act : std_ulogic_vector(0 to threads-1); +signal ex4_n_flush : std_ulogic_vector(0 to threads-1); +signal ex4_np1_flush : std_ulogic_vector(0 to threads-1); +signal ex4_cia_p1_out : std_ulogic_vector(0 to eff_ifar*threads-1); +signal ex5_ram_interrupt : std_ulogic_vector(0 to threads-1); +signal ex4_check_cia : std_ulogic_vector(0 to threads-1); +signal ex3_ct : std_ulogic_vector(0 to threads-1); +signal ex4_is_base_int,ex4_is_crit_int,ex4_is_mchk_int: std_ulogic_vector(0 to threads-1); +signal ex5_is_base_hint,ex5_is_base_gint : std_ulogic_vector(0 to threads-1); +signal ex3_np1_step_flush : std_ulogic_vector(0 to threads-1); +signal ex4_clear_bclr_chk : std_ulogic_vector(0 to threads-1); +signal ex5_is_any_int,ex5_is_any_gint,ex5_is_any_hint : std_ulogic_vector(0 to threads-1); +signal ex3_lr_cmpr, ex3_cia_cmpr : std_ulogic_vector(0 to threads-1); +signal ex3_mem_attr_chk : std_ulogic_vector(0 to threads-1); +signal ex3_mem_attr_cmpr : std_ulogic_vector(0 to threads-1); +signal ex4_mem_attr_act : std_ulogic_vector(0 to threads-1); +signal ex4_is_any_store : std_ulogic_vector(0 to threads-1); +signal ex4_epid_instr : std_ulogic_vector(0 to threads-1); +signal ex4_flush_act : std_ulogic_vector(0 to threads-1); +signal ex4_ucode_restart : std_ulogic_vector(0 to threads-1); +signal ex4_uc_cia_val : std_ulogic_vector(0 to threads-1); +signal ex5_flush_update : std_ulogic_vector(0 to threads-1); +signal ex4_cm : std_ulogic_vector(0 to threads-1); +signal exx_multi_flush : std_ulogic_vector(0 to threads-1); +signal hold_state_0, hold_state_1 : std_ulogic_vector(0 to threads-1); +signal spr_givpr : std_ulogic_vector(62-eff_ifar to 51); +signal spr_ivpr : std_ulogic_vector(62-eff_ifar to 51); +signal spr_ctr : std_ulogic_vector(0 to (regsize)*threads-1); +signal spr_lr : std_ulogic_vector(0 to (regsize)*threads-1); +signal spr_iar : std_ulogic_vector(0 to (eff_ifar)*threads-1); +signal spr_xucr3_cm_hold_dly : std_ulogic_vector(0 to 3); +signal spr_xucr3_stop_dly : std_ulogic_vector(0 to 3); +signal spr_xucr3_hold0_dly : std_ulogic_vector(0 to 3); +signal spr_xucr3_hold1_dly : std_ulogic_vector(0 to 3); +signal spr_xucr3_csi_dly : std_ulogic_vector(0 to 3); +signal spr_xucr3_int_dly : std_ulogic_vector(0 to 3); +signal spr_xucr3_asyncblk_dly : std_ulogic_vector(0 to 3); +signal spr_xucr3_flush_dly : std_ulogic_vector(0 to 3); +signal spr_xucr4_barr_dly : std_ulogic_vector(0 to 3); +signal spr_xucr4_lsu_bar_dis : std_ulogic; +signal spr_xucr4_div_bar_dis : std_ulogic; +signal spr_xucr4_mddmh : std_ulogic; +signal spr_xucr4_mmu_mchk_int : std_ulogic; +signal ex3_np1_mtxucr0_flush : std_ulogic_vector(0 to threads-1); +signal ex4_n_lsu_flush : std_ulogic_vector(0 to threads-1); +signal ex4_n_lsu_ddmh_flush : std_ulogic_vector(0 to threads-1); +signal ex3_div_coll : std_ulogic_vector(0 to threads-1); +signal ex3_non_uc_val : std_ulogic_vector(0 to threads-1); +signal ex3_n_ieratmiss_itlb_int : std_ulogic_vector(0 to threads-1); +signal ex3_n_tlbmiss_itlb_int : std_ulogic_vector(0 to threads-1); +signal ex3_n_iemh_mchk_mcint_xuuc : std_ulogic_vector(0 to threads-1); +signal ex3_n_iepe_mchk_mcint_xuuc : std_ulogic_vector(0 to threads-1); +signal ex3_n_il2ecc_mchk_mcint_xuuc : std_ulogic_vector(0 to threads-1); +signal ex3_n_dpovr_mchk_mcint : std_ulogic_vector(0 to threads-1); +signal ex3_n_demh_mchk_mcint_xu : std_ulogic_vector(0 to threads-1); +signal ex3_n_depe_mchk_mcint_xu : std_ulogic_vector(0 to threads-1); +signal ex3_n_dl2ecc_mchk_mcint : std_ulogic_vector(0 to threads-1); +signal ex3_n_ddpe_mchk_mcint_xu : std_ulogic_vector(0 to threads-1); +signal ex3_n_dcpe_mchk_mcint : std_ulogic_vector(0 to threads-1); +signal ex3_n_tlbmh_mchk_mcint : std_ulogic_vector(0 to threads-1); +signal ex3_n_tlbpe_mchk_mcint : std_ulogic_vector(0 to threads-1); +signal ex3_n_tlblru_mchk_mcint : std_ulogic_vector(0 to threads-1); +signal ex3_n_tlbsrej_mchk_mcint : std_ulogic_vector(0 to threads-1); +signal ex3_n_i1w1lock_dstor_int : std_ulogic_vector(0 to threads-1); +signal ex3_n_tlbi_dstor_int : std_ulogic_vector(0 to threads-1); +signal ex3_n_pt_dstor_int : std_ulogic_vector(0 to threads-1); +signal ex3_n_tlbi_istor_int : std_ulogic_vector(0 to threads-1); +signal ex3_n_pt_istor_int : std_ulogic_vector(0 to threads-1); +signal ex3_n_ldstmw_align_int : std_ulogic_vector(0 to threads-1); +signal ex3_n_ldst_align_int : std_ulogic_vector(0 to threads-1); +signal ex3_n_sprpil_prog_int_xu : std_ulogic_vector(0 to threads-1); +signal ex3_n_tlbpil_prog_int_xu : std_ulogic_vector(0 to threads-1); +signal ex3_n_mmupil_prog_int_xu : std_ulogic_vector(0 to threads-1); +signal ex3_n_iupil_prog_int_xuuc : std_ulogic_vector(0 to threads-1); +signal ex3_n_xupil_prog_int_xuuc : std_ulogic_vector(0 to threads-1); +signal ex3_n_ppr_prog_int_en : std_ulogic_vector(0 to threads-1); +signal ex3_n_sprppr_prog_int_xuuc : std_ulogic_vector(0 to threads-1); +signal ex3_n_instrppr_prog_int_xuuc : std_ulogic_vector(0 to threads-1); +signal ex3_n_fu_fp_unavail_int_axu : std_ulogic_vector(0 to threads-1); +signal ex3_n_xu_fp_unavail_int_xuuc : std_ulogic_vector(0 to threads-1); +signal ex3_n_fu_ap_unavail_int_axu : std_ulogic_vector(0 to threads-1); +signal ex3_n_xu_ap_unavail_int_xuuc : std_ulogic_vector(0 to threads-1); +signal ex3_n_fu_vec_unavail_int_axu : std_ulogic_vector(0 to threads-1); +signal ex3_n_xu_vec_unavail_int_xuuc : std_ulogic_vector(0 to threads-1); +signal ex3_n_deratmiss_dtlb_int : std_ulogic_vector(0 to threads-1); +signal ex3_n_tlbmiss_dtlb_int : std_ulogic_vector(0 to threads-1); +signal ex3_n_dacr_dbg_cint_xu : std_ulogic_vector(0 to threads-1); +signal ex3_n_dacw_dbg_cint_xu : std_ulogic_vector(0 to threads-1); +signal msr_guest_priv : std_ulogic_vector(0 to threads-1); +signal ex3_n_spr_hpriv_int_xuuc : std_ulogic_vector(0 to threads-1); +signal ex3_n_instr_hpriv_int_xuuc : std_ulogic_vector(0 to threads-1); +signal ex3_n_ehpriv_hpriv_int : std_ulogic_vector(0 to threads-1); +signal ex3_np1_dbg_cint_en : std_ulogic_vector(0 to threads-1); +signal ex3_np1_instr_flush : std_ulogic_vector(0 to threads-1); +signal ex3_np1_init_flush : std_ulogic_vector(0 to threads-1); +signal ex3_n_ram_flush : std_ulogic_vector(0 to threads-1); +signal ex3_n_mmuhold_flush : std_ulogic_vector(0 to threads-1); +signal ex3_n_ici_flush : std_ulogic_vector(0 to threads-1); +signal ex3_n_dci_flush : std_ulogic_vector(0 to threads-1); +signal ex3_n_mmu_flush : std_ulogic_vector(0 to threads-1); +signal ex3_n_multcoll_flush : std_ulogic_vector(0 to threads-1); +signal ex3_n_lsu_dcpe_flush : std_ulogic_vector(0 to threads-1); +signal ex3_n_fu_rfpe_flush, ex3_n_fu_rfpe_det : std_ulogic_vector(0 to threads-1); +signal ex3_n_xu_rfpe_flush : std_ulogic_vector(0 to threads-1); +signal ex3_n_sprg_ue_flush : std_ulogic_vector(0 to threads-1); +signal ex3_np1_sprg_ce_flush : std_ulogic_vector(0 to threads-1); +signal ex3_n_fu_dep_flush : std_ulogic_vector(0 to threads-1); +signal ex3_n_lsualign_2ucode_flush : std_ulogic_vector(0 to threads-1); +signal ex3_n_fu_2ucode_flush : std_ulogic_vector(0 to threads-1); +signal ex3_n_derat_dep_flush : std_ulogic_vector(0 to threads-1); +signal ex3_n_lsu_dep_flush : std_ulogic_vector(0 to threads-1); +signal ex3_n_lsu_ddpe_flush : std_ulogic_vector(0 to threads-1); +signal ex4_n_ldq_full_flush : std_ulogic_vector(0 to threads-1); +signal ex4_n_ieratre_par_mcint : std_ulogic_vector(0 to threads-1); +signal ex4_n_deratre_par_mcint : std_ulogic_vector(0 to threads-1); +signal ex4_n_tlbwemiss_dlrat_int : std_ulogic_vector(0 to threads-1); +signal ex4_n_tlbwe_pil_prog_int : std_ulogic_vector(0 to threads-1); +signal ex4_n_tlbmh_mchk_mcint : std_ulogic_vector(0 to threads-1); +signal ex4_n_tlbpar_mchk_mcint : std_ulogic_vector(0 to threads-1); +signal ex4_n_mmu_hpriv_int : std_ulogic_vector(0 to threads-1); +signal ex4_ena_prog_int : std_ulogic_vector(0 to threads-1); +signal ex4_barrier_flush : std_ulogic_vector(0 to threads-1); +signal ex4_lsu_barr_flush : std_ulogic_vector(0 to threads-1); +signal ex4_div_barr_flush : std_ulogic_vector(0 to threads-1); +signal ex3_hold_block : std_ulogic_vector(0 to threads-1); +signal ex5_csi : std_ulogic_vector(0 to threads-1); +signal exx_thread_stop_mcflush : std_ulogic_vector(0 to threads-1); +signal exx_lateflush_mcflush : std_ulogic_vector(0 to threads-1); +signal exx_csi_mcflush : std_ulogic_vector(0 to threads-1); +signal exx_hold0_mcflush : std_ulogic_vector(0 to threads-1); +signal exx_hold1_mcflush : std_ulogic_vector(0 to threads-1); +signal exx_barr_mcflush : std_ulogic_vector(0 to threads-1); +signal ex4_late_flush : std_ulogic_vector(0 to threads-1); +signal ex4_n_ddmh_mchk_mcint : std_ulogic_vector(0 to threads-1); +signal ex3_n_ierat_flush : std_ulogic_vector(0 to threads-1); +signal ex3_async_int_block_cond : std_ulogic_vector(0 to threads-1); +signal ex3_base_int_block_cond : std_ulogic_vector(0 to threads-1); +signal ex3_mchk_int_block_cond : std_ulogic_vector(0 to threads-1); +signal ex5_cm_hold_cond : std_ulogic_vector(0 to threads-1); +signal exx_cm_hold : std_ulogic_vector(0 to threads-1); +signal ex5_cia_p1 : IFAR; +signal ex5_msr_cm : std_ulogic; +signal ex2_msr_updater : std_ulogic; +signal ex4_async_block : std_ulogic_vector(0 to threads-1); +signal any_ext_perf_ints : std_ulogic_vector(0 to threads-1); +signal any_ext_perf_int : std_ulogic; +signal ext_int_asserted, crit_int_asserted : std_ulogic_vector(0 to threads-1); +signal perf_int_asserted : std_ulogic_vector(0 to threads-1); +signal rf1_is_dci : std_ulogic; +signal rf1_is_ici : std_ulogic; +signal rf1_th_fld_val : std_ulogic; +signal rf1_opcode_is_31 : boolean; +signal rf1_opcode_is_0 : boolean; +signal rf1_opcode_is_19 : boolean; +signal ex3_dlk_dstor_cond0, ex3_dlk_dstor_cond1 : std_ulogic_vector(0 to threads-1); +signal ex3_dlk_dstor_cond2, ex3_dlk_dstor_cond : std_ulogic_vector(0 to threads-1); +signal ex4_n_fu_rfpe_flush : std_ulogic_vector(0 to threads-1); +signal ex4_n_xu_rfpe_flush : std_ulogic_vector(0 to threads-1); +signal ex4_n_flush_pri_ehpriv : std_ulogic_vector(0 to threads-1); +signal ici_hold_present : std_ulogic; +signal ex4_n_fu_rfpe_set, ex4_n_xu_rfpe_set : std_ulogic; +signal pc_err_mcsr, pc_err_mcsr_rpt : std_ulogic_vector(0 to 11*threads-1); +signal dbg_group0, dbg_group1, dbg_group2, dbg_group3, + dbg_group4, dbg_group5, dbg_group6, dbg_group7, + dbg_group8, dbg_group9, dbg_group10,dbg_group11, + dbg_group12,dbg_group13,dbg_group14,dbg_group15, + dbg_group16,dbg_group17,dbg_group18,dbg_group19, + dbg_group20,dbg_group21,dbg_group22,dbg_group23, + dbg_group24,dbg_group25,dbg_group26,dbg_group27, + dbg_group28,dbg_group29,dbg_group30,dbg_group31: std_ulogic_vector(0 to 87); +signal trg_group0 ,trg_group1 ,trg_group2 ,trg_group3 : std_ulogic_vector(0 to 11); +signal cpl_debug_data_in_int : std_ulogic_vector(0 to 87); +signal dbg_match : ARY3; +signal dbg_misc : ARY4; +signal dbg_valids, dbg_valids_opc, dbg_msr, dbg_int_types : ARY5; +signal dbg_async_block : ARY7; +signal dbg_iuflush : ARY9; +signal ex5_flush_pri_enc_dbg,dbg_hold : ARY6; +signal ex4_cia_out : ARY_IFAR; +signal ex5_axu_ucode_val_opc : std_ulogic_vector(0 to threads-1); +signal ex5_axu_val_dbg_opc, ex5_xu_val_dbg_opc : std_ulogic_vector(0 to threads-1); +signal br_debug : std_ulogic_vector(0 to 11); +signal ex4_xu_siar_val, ex4_axu_siar_val : std_ulogic; +signal ex4_siar_cpl : std_ulogic_vector(0 to threads-1); +signal ex4_siar_sel_act : std_ulogic; +signal ex4_siar_axu_sel : std_ulogic; +signal ex4_siar_tid, ex4_siar_sel, siar_cm : std_ulogic_vector(0 to 3); +signal ex5_xu_ppc_cpl, ex5_axu_ppc_cpl : std_ulogic_vector(0 to threads-1); +signal ex5_xu_trace_val, ex5_axu_trace_val : std_ulogic; +signal exx_act : std_ulogic_vector(0 to 4); +signal ex1_ifar_act, ex2_ifar_act, ex3_ifar_act : std_ulogic_vector(0 to threads-1); +signal ex4_nia_act : std_ulogic_vector(0 to threads-1); +signal ex2_axu_act : std_ulogic; +signal ex4_dbsr_act, ex4_mcsr_act, ex4_esr_act : std_ulogic_vector(0 to threads-1); +signal ex5_mcsr_act : std_ulogic; +signal ex3_uc_cia_act : std_ulogic_vector(0 to threads-1); +signal exx_flush_inf_act, ex4_flush_inf_act : std_ulogic; +signal spr_bit_w_int_act : std_ulogic; +signal exx_np1_icmp_dbg_cint : std_ulogic_vector(0 to threads-1); +signal exx_np1_icmp_dbg_event : std_ulogic_vector(0 to threads-1); +signal ex4_np1_icmp_dbg_en : std_ulogic_vector(0 to threads-1); +signal ex4_n_flush_pri_icmp : std_ulogic_vector(0 to threads-1); +signal ex4_n_flush_pri_irpt : std_ulogic_vector(0 to threads-1); +signal ex4_np1_icmp_dbg_event : std_ulogic_vector(0 to threads-1); +signal ex4_np1_icmp_dbg_cint : std_ulogic_vector(0 to threads-1); +signal ex4_icmp_async_block : std_ulogic_vector(0 to threads-1); +signal exx_np1_irpt_dbg_cint : std_ulogic_vector(0 to threads-1); +signal exx_np1_irpt_dbg_event : std_ulogic_vector(0 to threads-1); +signal ex4_n_flush_pri_dacr_async : std_ulogic_vector(0 to threads-1); +signal ex4_ram_cpl : std_ulogic_vector(0 to threads-1); +signal ex4_siar_cm_mask : IFAR; +signal ex3_n_tlb_mchk_flush_en : std_ulogic_vector(0 to threads-1); +signal ex3_n_tlbmh_mchk_flush : std_ulogic_vector(0 to threads-1); +signal ex3_n_tlbpe_mchk_flush : std_ulogic_vector(0 to threads-1); +signal ex3_n_dexx_mchk_flush_en : std_ulogic_vector(0 to threads-1); +signal ex3_n_demh_mchk_flush : std_ulogic_vector(0 to threads-1); +signal ex3_n_depe_mchk_flush : std_ulogic_vector(0 to threads-1); +signal ex3_n_mmu_mchk_flush_only : std_ulogic; +signal ex3_is_any_ldst : std_ulogic; +signal ex5_ram_issue_gated : std_ulogic_vector(0 to threads-1); +signal rfpe_quiesced : std_ulogic; +signal rfpe_quiesce_cond_b, rfpe_quiesced_ctr_zero_b : std_ulogic; +signal ex4_axu_trap_pie : std_ulogic_vector(0 to threads-1); +signal rf1_is_tlbre : std_ulogic; +signal rf1_is_tlbsx, rf1_is_tlbsrx : std_ulogic; +signal tlbsx_async_block_set : std_ulogic_vector(0 to threads-1); +signal tlbsx_async_block_clr : std_ulogic_vector(0 to threads-1); + +begin + + +tiup <= '1'; +tidn <= '0'; + +exx_act_d <= (clk_override_q or clkg_ctl_q or dec_cpl_rf0_act) & exx_act(0 to 3); + +exx_act(0) <= exx_act_q(0); +exx_act(1) <= exx_act_q(1); +exx_act(2) <= exx_act_q(2); +exx_act(3) <= exx_act_q(3) or or_reduce(ex3_axu_val_q); +exx_act(4) <= exx_act_q(4); + +ex2_axu_act <= or_reduce(ex2_axu_act_q) or clk_override_q; + +ex1_ifar_act <= ex1_xu_val_q or ex1_xu_issued_q or ex1_ucode_val_q or ex1_axu_act_q or (0 to threads-1=>clk_override_q); +ex2_ifar_act <= ex2_xu_val_q or ex2_xu_issued_q or ex2_ucode_val_q or ex2_axu_act_q or (0 to threads-1=>clk_override_q); +ex3_ifar_act <= ex3_xu_val_q or ex3_xu_issued_q or ex3_ucode_val_q or ex3_axu_val_q or (0 to threads-1=>clk_override_q) or ex3_axu_issued_q; + +spr_bit_w_int_act <= spr_bit_act_q or clkg_ctl_q; + +-- Deocode +rf1_opcode_is_31 <= dec_cpl_rf1_instr(0 to 5) = "011111"; +rf1_opcode_is_0 <= dec_cpl_rf1_instr(0 to 5) = "000000"; +rf1_opcode_is_19 <= dec_cpl_rf1_instr(0 to 5) = "010011"; +rf1_is_tlbsx <= '1' when rf1_opcode_is_31 and dec_cpl_rf1_instr(21 to 30) = "1110010010" else '0'; -- 31/914 +rf1_is_tlbsrx <= '1' when rf1_opcode_is_31 and dec_cpl_rf1_instr(21 to 30) = "1101010010" else '0'; -- 31/850 +rf1_is_tlbre <= '1' when rf1_opcode_is_31 and dec_cpl_rf1_instr(21 to 30) = "1110110010" else '0'; -- 31/946 +rf1_is_tlbwe <= '1' when rf1_opcode_is_31 and dec_cpl_rf1_instr(21 to 30) = "1111010010" else '0'; -- 31/978 +rf1_is_eratre <= '1' when rf1_opcode_is_31 and dec_cpl_rf1_instr(21 to 30) = "0010110011" else '0'; -- 31/179 +rf1_is_wait <= '1' when rf1_opcode_is_31 and dec_cpl_rf1_instr(21 to 30) = "0000111110" else '0'; +rf1_is_icblc <= '1' when rf1_opcode_is_31 and dec_cpl_rf1_instr(21 to 30) = "0011100110" else '0'; +rf1_is_icbtls <= '1' when rf1_opcode_is_31 and dec_cpl_rf1_instr(21 to 30) = "0111100110" else '0'; +rf1_is_dcblc <= '1' when rf1_opcode_is_31 and dec_cpl_rf1_instr(21 to 30) = "0110000110" else '0'; +rf1_is_dcbtls <= '1' when rf1_opcode_is_31 and dec_cpl_rf1_instr(21 to 30) = "0010100110" else '0'; +rf1_is_dcbtstls <= '1' when rf1_opcode_is_31 and dec_cpl_rf1_instr(21 to 30) = "0010000110" else '0'; +rf1_is_rfi <= '1' when rf1_opcode_is_19 and dec_cpl_rf1_instr(21 to 30) = "0000110010" else '0'; -- 19/50 +rf1_is_rfci <= '1' when rf1_opcode_is_19 and dec_cpl_rf1_instr(21 to 30) = "0000110011" else '0'; -- 19/51 +rf1_is_rfgi <= '1' when rf1_opcode_is_19 and dec_cpl_rf1_instr(21 to 30) = "0001100110" else '0'; -- 19/102 +rf1_is_rfmci <= '1' when rf1_opcode_is_19 and dec_cpl_rf1_instr(21 to 30) = "0000100110" else '0'; -- 19/38 +rf1_is_mfspr <= '1' when rf1_opcode_is_31 and dec_cpl_rf1_instr(21 to 30) = "0101010011" else '0'; -- 31/339 +rf1_is_mtspr <= '1' when rf1_opcode_is_31 and dec_cpl_rf1_instr(21 to 30) = "0111010011" else '0'; -- 31/467 +rf1_is_mtmsr <= '1' when rf1_opcode_is_31 and dec_cpl_rf1_instr(21 to 30) = "0010010010" else '0'; -- 31/146 +rf1_is_wrtee <= '1' when rf1_opcode_is_31 and dec_cpl_rf1_instr(21 to 30) = "0010000011" else '0'; -- 31/131 +rf1_is_wrteei <= '1' when rf1_opcode_is_31 and dec_cpl_rf1_instr(21 to 30) = "0010100011" else '0'; -- 31/163 +rf1_is_erativax <= '1' when rf1_opcode_is_31 and dec_cpl_rf1_instr(21 to 30) = "1100110011" else '0'; -- 31/819 +rf1_is_isync <= '1' when rf1_opcode_is_19 and dec_cpl_rf1_instr(21 to 30) = "0010010110" else '0'; -- 19/150 +rf1_is_sc <= '1' when dec_cpl_rf1_instr( 0 to 5) = "010001" else '0'; -- 17 +rf1_is_dci <= '1' when rf1_opcode_is_31 and dec_cpl_rf1_instr(21 to 30) = "0111000110" else '0'; -- 31/454 +rf1_is_ici <= '1' when rf1_opcode_is_31 and dec_cpl_rf1_instr(21 to 30) = "1111000110" else '0'; -- 31/966 +rf1_is_tlbivax <= '1' when rf1_opcode_is_31 and dec_cpl_rf1_instr(21 to 30) = "1100010010" else '0'; -- 31/786 +rf1_is_ehpriv <= '1' when rf1_opcode_is_31 and dec_cpl_rf1_instr(21 to 30) = "0100001110" else '0'; -- 31/270 +rf1_is_attn <= '1' when rf1_opcode_is_0 and dec_cpl_rf1_instr(21 to 30) = "0100000000" else '0'; -- 0/256 +rf1_is_icswx <= '1' when rf1_opcode_is_31 and (dec_cpl_rf1_instr(21 to 30) = "0110010110" or -- 31/406 + dec_cpl_rf1_instr(21 to 30) = "1110110110") else '0'; -- 31/950 +rf1_is_any_ldstmw <= '1' when dec_cpl_rf1_instr(0 to 4) = "10111" else '0'; -- 46/47 +rf1_sc_lev <= dec_cpl_rf1_instr(26); + +rf1_is_ldbrx <= '1' when rf1_opcode_is_31 and dec_cpl_rf1_instr(21 to 30) = "1000010100" else '0'; +rf1_is_lwbrx <= '1' when rf1_opcode_is_31 and dec_cpl_rf1_instr(21 to 30) = "1000010110" else '0'; +rf1_is_lhbrx <= '1' when rf1_opcode_is_31 and dec_cpl_rf1_instr(21 to 30) = "1100010110" else '0'; +rf1_is_stdbrx <= '1' when rf1_opcode_is_31 and dec_cpl_rf1_instr(21 to 30) = "1010010100" else '0'; +rf1_is_stwbrx <= '1' when rf1_opcode_is_31 and dec_cpl_rf1_instr(21 to 30) = "1010010110" else '0'; +rf1_is_sthbrx <= '1' when rf1_opcode_is_31 and dec_cpl_rf1_instr(21 to 30) = "1110010110" else '0'; + +rf1_byte_rev <= rf1_is_lhbrx or rf1_is_lwbrx or rf1_is_ldbrx or rf1_is_sthbrx or rf1_is_stwbrx or rf1_is_stdbrx; +rf1_is_dlock <= rf1_is_dcblc or rf1_is_dcbtls or rf1_is_dcbtstls; +rf1_is_ilock <= rf1_is_icblc or rf1_is_icbtls; + +rf1_is_mtxucr0 <= rf1_is_mtspr and (dec_cpl_rf1_instr(11 to 20) = "1011011111"); -- 1014 + +rf1_th_fld_val <= (dec_cpl_rf1_instr(7 to 10) = "0000") or (dec_cpl_rf1_instr(7 to 10) = "0010"); +ex1_is_dci_d <= rf1_is_dci and rf1_th_fld_val; +ex1_is_ici_d <= rf1_is_ici and rf1_th_fld_val; + +ex3_np1_instr_flush_d <= (ex2_is_mtmsr_q or + ex2_is_isync_q or + ex2_is_tlbivax_q or + ex2_is_erativax_q or + ex2_is_attn_q or + ex2_is_dci_q or + ex2_is_ici_q); + + +spare_4_d(0) <= not (rf1_is_tlbsx or rf1_is_tlbsrx); +spare_4_d(1 to 3) <= not spare_4_q(0 to 2); + +spare_4_d(4 to 7) <= not (tlbsx_async_block_set or (spare_4_q(4 to 7) and not tlbsx_async_block_clr)); + +tlbsx_async_block_set <= gate(ex4_instr_cpl_q,spare_4_q(3)); +tlbsx_async_block_clr <= ex4_anyuc_val_q or ex5_is_any_int or ex4_thread_stop_q; + + +xuq_cpl_slice : for t in 0 to threads-1 generate + + signal ex4_cia_b_q, ex4_cia_b_d : IFAR; + signal ex4_uc_cia_q, ex4_uc_cia_d : IFAR_UC; + signal ex4_axu_instr_type_q, ex4_axu_instr_type_d : std_ulogic_vector(0 to 2); + signal ex5_mem_attr_q : std_ulogic_vector(lsu_xu_ex3_attr'range); + signal ex5_ivo_sel_q, ex4_ivo_sel : std_ulogic_vector(0 to ivos-1); + signal ex5_flush_pri_dbg_q : std_ulogic_vector(0 to Fnp1); -- input=>ex4_flush_pri, act=>trace_bus_enable_q, sleep=>Y, needs_sreset=>0, scan=>N + signal ex4_cia_flush, flush_ifar : IFAR; + signal ex4_axu_instr_type : std_ulogic_vector(0 to 2); + signal ex3_ifar, ex4_ifar, ex3_spr_lr : IFAR; + signal ex5_flush_ifar : IFAR; + signal ex4_n_flush_cond, ex4_n_flush_pri : std_ulogic_vector(0 to Fn); + signal ex4_np1_flush_cond, ex4_np1_flush_pri : std_ulogic_vector(Fn+1 to Fnp1); + signal ex4_np1_flush_pri_nongated : std_ulogic_vector(Fn+1 to Fnp1); + signal ex4_np1_flush_pri_instr : std_ulogic_vector(0 to RFI); + signal ex4_flush_pri : std_ulogic_vector(0 to Fnp1); + signal ex4_n_flush_pri_unavail : std_ulogic_vector(0 to VEC); + signal ex4_n_flush_pri_ena : std_ulogic_vector(0 to 1); + signal ex5_ivo_mask_guest : std_ulogic_vector(0 to ivos-1); + signal ex5_ivo_guest_sel, ex5_ivo_hypv_sel : std_ulogic_vector(0 to ivos-1); + signal ex5_ivo : std_ulogic_vector(52 to 59); + signal ex4_nia : IFAR; + signal ex4_nia_instr, ex4_nia_cpl : IFAR; + signal ex4_cia : IFAR; + signal ex4_cia_p1 : IFAR; + signal ex4_cia_sel, ex4_nia_sel : IFAR; + signal ex4_uc_nia : IFAR_UC; + signal ex4_esr_mask : std_ulogic_vector(0 to cpl_spr_ex5_esr'length/threads-1); + signal ex4_cm_mask : IFAR; + signal ex4_dbsr_cond : std_ulogic_vector(0 to 1); + signal ex4_dbsr_en_cond : std_ulogic_vector(0 to 1); + signal ex4_esr_cond, ex4_esr_pri : std_ulogic_vector(0 to UCT); + + begin + + + --============================================================================= + --============================================================================= + -- + -- Interrupt Conditions + -- + --============================================================================= + --============================================================================= + + ------------------------------------------------------------------------------- + -- Critical External Input Interrupt + ------------------------------------------------------------------------------- + ex3_np1_crit_cint(t) <= spr_cpl_crit_interrupt(t) and not ex3_async_int_block(t); + + ------------------------------------------------------------------------------- + -- Machine Check Interrupt + ------------------------------------------------------------------------------- + -- Enable + ex3_mchk_int_en(t) <= (msr_me_q(t) or msr_gs_q(t)) and not ex3_mchk_int_block(t); + + ------------------------------------------------------------------------------- + -- N Flushes [tlb parity error flush] + ------------------------------------------------------------------------------- + ex3_n_tlbmh_mchk_flush(t) <= ex3_n_tlb_mchk_flush_en(t) and ex3_tlb_multihit_err_q(t); + ex3_n_tlbpe_mchk_flush(t) <= ex3_n_tlb_mchk_flush_en(t) and ex3_tlb_par_err_q(t); + + ex3_n_tlb_mchk_flush(t) <= ex3_n_tlbmh_mchk_flush(t) or + ex3_n_tlbpe_mchk_flush(t); + + ------------------------------------------------------------------------------- + -- Instr Machine Check Interrupt + ------------------------------------------------------------------------------- + ex3_n_tlb_mchk_flush_en(t) <= ex3_n_mmu_mchk_flush_only and mmu_eratmiss_done_q(t); + ex3_n_ieratsx_par_mchk_mcint(t) <= ex3_xu_val(t) and iu_xu_ierat_ex3_par_err(t); + + -- Conditions + ex3_n_iemh_mchk_mcint_xuuc(t) <= ex3_iu_error_q(6); + ex3_n_iepe_mchk_mcint_xuuc(t) <= ex3_iu_error_q(5); + ex3_n_il2ecc_mchk_mcint_xuuc(t) <= ex3_iu_error_q(2); + ex3_n_tlbmh_mchk_mcint(t) <= not ex3_n_tlb_mchk_flush_en(t) and ex3_tlb_multihit_err_q(t); + ex3_n_tlbpe_mchk_mcint(t) <= not ex3_n_tlb_mchk_flush_en(t) and ex3_tlb_par_err_q(t); + ex3_n_tlblru_mchk_mcint(t) <= ex3_tlb_lru_par_err_q(t); + ex3_n_tlbsrej_mchk_mcint(t) <= ex3_tlb_local_snoop_reject_q(t); + ex3_n_ieratre_par_mchk_mcint(t) <= ex5_xu_val_q(t) and ex5_ieratre_par_err_q(t); + + spare_5_d(t) <= not(ex3_n_tlbpe_mchk_mcint(t) or ex3_n_tlblru_mchk_mcint(t)); + + -- Summary + ex3_n_imchk_mcint(t) <=(ex3_xuuc_val(t) and (ex3_n_iemh_mchk_mcint_xuuc(t) or + ex3_n_iepe_mchk_mcint_xuuc(t) or + ex3_n_il2ecc_mchk_mcint_xuuc(t))) + or + ex3_n_tlbmh_mchk_mcint(t) or + ex3_n_tlbpe_mchk_mcint(t) or + ex3_n_tlblru_mchk_mcint(t) or + ex3_n_tlbsrej_mchk_mcint(t) or + ex3_n_ieratre_par_mchk_mcint(t); + + ------------------------------------------------------------------------------- + -- Data Machine Check Interrupt + ------------------------------------------------------------------------------- + ex3_n_dexx_mchk_flush_en(t) <= ex3_n_mmu_mchk_flush_only and ex3_is_any_ldst; + + -- Conditions + ex3_n_demh_mchk_mcint_xu(t) <= not ex3_n_dexx_mchk_flush_en(t) and lsu_xu_ex3_derat_multihit_err(t); + ex3_n_depe_mchk_mcint_xu(t) <= not ex3_n_dexx_mchk_flush_en(t) and lsu_xu_ex3_derat_par_err(t); + ex3_n_dl2ecc_mchk_mcint(t) <= lsu_xu_ex3_l2_uc_ecc_err(t); + ex3_n_ddpe_mchk_mcint_xu(t) <= lsu_xu_ex3_ddir_par_err and spr_xucr0_mddp; + ex3_n_deratre_par_mchk_mcint(t) <= ex5_xu_val_q(t) and ex5_deratre_par_err_q(t); + + ex3_n_dpovr_mchk_mcint(t) <= ex4_xu_val(t) and ex4_mtdp_nr_q and not lsu_xu_ex4_mtdp_cr_status; + ex3_n_dcpe_mchk_mcint(t) <= ex6_xu_val_q(t) and lsu_xu_ex6_datc_par_err and spr_xucr0_mdcp; + + + -- Summary + ex3_n_dmchk_mcint(t) <=(ex3_xu_val(t) and (ex3_n_demh_mchk_mcint_xu(t) or + ex3_n_depe_mchk_mcint_xu(t) or + ex3_n_ddpe_mchk_mcint_xu(t))) + or + ex3_n_dl2ecc_mchk_mcint(t) or + ex3_n_dpovr_mchk_mcint(t) or + ex3_n_dcpe_mchk_mcint(t) or + ex3_n_deratre_par_mchk_mcint(t); + + ex4_n_ddmh_mchk_en_d(t) <= ex3_xu_val(t) and dec_cpl_ex3_ddmh_en and spr_xucr4_mddmh; + ex4_n_ddmh_mchk_mcint(t) <= ex4_n_ddmh_mchk_en_q(t) and lsu_xu_ex4_n_lsu_ddmh_flush(t); + + ------------------------------------------------------------------------------- + -- Async Machine Check Interrupt + ------------------------------------------------------------------------------- + ex3_np1_ext_mchk_mcint(t) <= external_mchk_q(t) and not ex3_async_int_block(t); + + ------------------------------------------------------------------------------- + -- Data Storage Interrupt + ------------------------------------------------------------------------------- + ex3_ct(t) <=(spr_cpl_ex3_ct_le(t) and lsu_xu_ex3_attr(8)) or + (spr_cpl_ex3_ct_be(t) and not lsu_xu_ex3_attr(8)); + + ex3_dlk_dstor_cond0(t) <= msrp_uclep_q(t) and msr_gs_q(t); + ex3_dlk_dstor_cond1(t) <= not msr_ucle_q(t) and not msrp_uclep_q(t); + ex3_dlk_dstor_cond2(t) <= not msr_ucle_q(t) and not msr_gs_q(t); + + ex3_dlk_dstor_cond(t) <= ex3_dlk_dstor_cond0(t) or + ex3_dlk_dstor_cond1(t) or + ex3_dlk_dstor_cond2(t); + -- Conditions + ex3_n_rwaccess_dstor_int(t) <= ex3_xuuc_val(t) and derat_xu_ex3_dsi(t); + ex3_n_i1w1lock_dstor_int(t) <= ex3_xu_val(t) and lsu_xu_ex3_dsi(t); + ex3_n_uct_dstor_int(t) <= ex3_xu_val(t) and ex3_is_icswx_q and not ex3_ct(t); + ex3_n_dlk0_dstor_int(t) <= ex3_xu_val(t) and msr_pr_q(t) and ex3_dlk_dstor_cond(t) and ex3_is_dlock_q; + ex3_n_dlk1_dstor_int(t) <= ex3_xu_val(t) and msr_pr_q(t) and ex3_dlk_dstor_cond(t) and ex3_is_ilock_q; + ex3_n_tlbi_dstor_int(t) <= ex3_tlb_inelig_q(t) and ex3_mmu_esr_data_q(t); -- PTE Realod when all ways are IPROT=1 + ex3_n_pt_dstor_int(t) <= ex3_tlb_pt_fault_q(t) and ex3_mmu_esr_data_q(t); -- HTW attempted to install invalid entry in TLB + ex3_n_vf_dstor_int(t) <= ex3_xuuc_val(t) and lsu_xu_ex3_derat_vf and ex3_is_any_ldst; + -- Summary + ex3_n_dstor_int(t) <= ex3_n_rwaccess_dstor_int(t) or + ex3_n_i1w1lock_dstor_int(t) or + ex3_n_uct_dstor_int(t) or + ex3_n_dlk0_dstor_int(t) or + ex3_n_dlk1_dstor_int(t) or + ex3_n_tlbi_dstor_int(t) or + ex3_n_pt_dstor_int(t) or + ex3_n_vf_dstor_int(t); + + ------------------------------------------------------------------------------- + -- Instruction Storage Interrupt + ------------------------------------------------------------------------------- + -- Conditions + ex3_n_exaccess_istor_int(t) <= ex3_xuuc_val(t) and ex3_iu_error_q(4); + ex3_n_tlbi_istor_int(t) <= ex3_tlb_inelig_q(t) and not ex3_mmu_esr_data_q(t); -- PTE Realod when all ways are IPROT=1 + ex3_n_pt_istor_int(t) <= ex3_tlb_pt_fault_q(t) and not ex3_mmu_esr_data_q(t); -- HTW attempted to install invalid entry in TLB + -- Summary + ex3_n_istor_int(t) <= ex3_n_exaccess_istor_int(t) or + ex3_n_tlbi_istor_int(t) or + ex3_n_pt_istor_int(t); + + ------------------------------------------------------------------------------- + -- External Input Interrupt + ------------------------------------------------------------------------------- + ex3_np1_ext_int(t) <= spr_cpl_ext_interrupt(t) and not ex3_async_int_block(t); + + ------------------------------------------------------------------------------- + -- Alignment Interrupt + ------------------------------------------------------------------------------- + -- Conditions + ex3_n_ldstmw_align_int(t) <= ex3_ucode_val(t) and ex3_n_align_int_q; + ex3_n_ldst_align_int(t) <= ex3_xu_val(t) and lsu_xu_ex3_align(t); + -- Summary + ex3_n_align_int(t) <= ex3_n_ldstmw_align_int(t) or + ex3_n_ldst_align_int(t); + + ------------------------------------------------------------------------------- + -- Program Interrupt [illegal] + ------------------------------------------------------------------------------- + -- Conditions + -- Priv SPR accessed in problem state needs to get Priv-Prog Int even if it's an illegal SPR. + ex3_n_sprpil_prog_int_xu(t) <= spr_cpl_ex3_spr_illeg and not (spr_cpl_ex3_spr_priv and msr_pr_q(t)); + ex3_n_tlbpil_prog_int_xu(t) <= dec_cpl_ex3_tlb_illeg; + ex3_n_mmupil_prog_int_xu(t) <= mm_xu_illeg_instr(t) and not ex7_is_tlbwe_q(t); + ex3_n_xupil_prog_int_xuuc(t) <= ex3_illegal_op_q; + ex3_n_iupil_prog_int_xuuc(t) <= ex3_iu_error_q(1); + -- Summary + ex3_n_pil_prog_int(t) <=(ex3_xuuc_val(t) and (ex3_n_iupil_prog_int_xuuc(t) or + ex3_n_xupil_prog_int_xuuc(t))) + or + (ex3_xu_val(t) and (ex3_n_sprpil_prog_int_xu(t) or + ex3_n_tlbpil_prog_int_xu(t) or + ex3_n_mmupil_prog_int_xu(t))); + + ------------------------------------------------------------------------------- + -- Program Interrupt [illegal MAS settings] + ------------------------------------------------------------------------------- + ex3_n_tlbwe_pil_prog_int(t) <= ex3_tlb_illeg_q(t) and ex8_is_tlbwe_q(t); + + ------------------------------------------------------------------------------- + -- Program Interrupt [privileged] + ------------------------------------------------------------------------------- + -- Enable + ex3_n_ppr_prog_int_en(t) <= msr_pr_q(t) and not (ex3_n_dlk0_dstor_int(t) or + ex3_n_dlk1_dstor_int(t)); + -- Conditions + ex3_n_sprppr_prog_int_xuuc(t) <= spr_cpl_ex3_spr_priv; + ex3_n_instrppr_prog_int_xuuc(t) <= dec_cpl_ex3_instr_priv and not ex3_is_ehpriv_q; + -- Summary + ex3_n_ppr_prog_int(t) <= ex3_n_ppr_prog_int_en(t) and + ex3_xuuc_val(t) and (ex3_n_sprppr_prog_int_xuuc(t) or + ex3_n_instrppr_prog_int_xuuc(t)); + + ------------------------------------------------------------------------------- + -- Program Interrupt [unimplemented] + ------------------------------------------------------------------------------- + -- Add the 2ucode flush.. otherwise could run into priority problems. + ex3_n_puo_prog_int(t) <= (ex3_ucode_val(t) or ex3_n_2ucode_flush(t)) and spr_ccr2_ucode_dis; + + ------------------------------------------------------------------------------- + -- Program Interrupt [trap] + ------------------------------------------------------------------------------- + ex3_np1_ptr_prog_int(t) <= ex3_xu_val(t) and alu_cpl_ex3_trap_val and not (spr_dbcr0_trap(t) and msr_de_q(t) and dbcr0_idm_q(t) and debug_event_en_q(t)); + + ------------------------------------------------------------------------------- + -- Program Interrupt [enabled] + ------------------------------------------------------------------------------- + -- Enable + -- Need to block while base interrupts are in progress, until (FE0|FE1)==0. This will keep this from occuring twice. + ex3_n_fpena_prog_int(t) <= fu_xu_ex3_trap(t) and spr_cpl_fp_precise(t) and not ex3_async_int_block_noaxu(t); + ex3_n_apena_prog_int(t) <= ex3_any_val(t) and fu_xu_ex3_ap_int_req(t); + -- Summary + ex3_n_ena_prog_int(t) <= + ex3_n_fpena_prog_int(t) or + ex3_n_apena_prog_int(t); + + ------------------------------------------------------------------------------- + -- XX Unavailable Interrupt + ------------------------------------------------------------------------------- + -- Conditions + ex3_n_fu_fp_unavail_int_axu(t) <= ex3_axu_instr_type_q(2+3*t) and not msr_fp_q(t); + ex3_n_xu_fp_unavail_int_xuuc(t) <= dec_cpl_ex3_axu_instr_type(2) and not msr_fp_q(t); + ex3_n_fu_ap_unavail_int_axu(t) <= ex3_axu_instr_type_q(3*t) and not ccr2_ap_q(t); + ex3_n_xu_ap_unavail_int_xuuc(t) <= dec_cpl_ex3_axu_instr_type(0) and not ccr2_ap_q(t); + ex3_n_fu_vec_unavail_int_axu(t) <= ex3_axu_instr_type_q(1+3*t) and not msr_spv_q(t); + ex3_n_xu_vec_unavail_int_xuuc(t) <= dec_cpl_ex3_axu_instr_type(1) and not msr_spv_q(t); + -- Summary + ex3_n_fp_unavail_int(t) <=(ex3_axu_val(t) and ex3_n_fu_fp_unavail_int_axu(t)) or + (ex3_xuuc_val(t) and ex3_n_xu_fp_unavail_int_xuuc(t)); + + ex3_n_ap_unavail_int(t) <=(ex3_axu_val(t) and ex3_n_fu_ap_unavail_int_axu(t)) or + (ex3_xuuc_val(t) and ex3_n_xu_ap_unavail_int_xuuc(t)); + + ex3_n_vec_unavail_int(t) <=(ex3_axu_val(t) and ex3_n_fu_vec_unavail_int_axu(t)) or + (ex3_xuuc_val(t) and ex3_n_xu_vec_unavail_int_xuuc(t)); + + ex3_n_any_unavail_int(t) <=(ex3_axu_val(t) and (ex3_n_fu_fp_unavail_int_axu(t) or + ex3_n_fu_ap_unavail_int_axu(t) or + ex3_n_fu_vec_unavail_int_axu(t))) + or + (ex3_xuuc_val(t) and (ex3_n_xu_fp_unavail_int_xuuc(t) or + ex3_n_xu_ap_unavail_int_xuuc(t) or + ex3_n_xu_vec_unavail_int_xuuc(t))); + + ------------------------------------------------------------------------------- + -- Instruction Based Interrupts [rfi,sc,trap] + ------------------------------------------------------------------------------- + -- Conditions + ex3_np1_sc_int(t) <= ex3_xu_val(t) and ex3_is_sc_q; + ex3_np1_rfi(t) <= ex3_xu_val(t) and (ex3_is_rfmci_q or ex3_is_rfci_q or ex3_is_rfi_q or ex3_is_rfgi_q); + -- Summary + ex3_np1_instr_int(t) <= ex3_np1_ptr_prog_int(t) or + ex3_np1_sc_int(t) or + ex3_np1_rfi(t); + + ------------------------------------------------------------------------------- + -- Decrementer Interrupt + ------------------------------------------------------------------------------- + ex3_np1_dec_int(t) <= spr_cpl_dec_interrupt(t) and not ex3_async_int_block(t); + + ------------------------------------------------------------------------------- + -- Fixed Interval Timer Interrupt + ------------------------------------------------------------------------------- + ex3_np1_fit_int(t) <= spr_cpl_fit_interrupt(t) and not ex3_async_int_block(t); + + ------------------------------------------------------------------------------- + -- Watchdog Interrupt + ------------------------------------------------------------------------------- + ex3_np1_wdog_cint(t) <= spr_cpl_wdog_interrupt(t) and not ex3_async_int_block(t); + + ------------------------------------------------------------------------------- + -- Data TLB Interrupt + ------------------------------------------------------------------------------- + -- Conditions + ex3_n_deratmiss_dtlb_int(t) <= ex3_xuuc_val(t) and derat_xu_ex3_miss(t) and spr_ccr2_notlb; + ex3_n_tlbmiss_dtlb_int(t) <= ex3_tlb_miss_q(t) and ex3_mmu_esr_data_q(t) and not spr_ccr2_notlb; + -- Summary + ex3_n_dtlb_int(t) <= ex3_n_deratmiss_dtlb_int(t) or + ex3_n_tlbmiss_dtlb_int(t); + ------------------------------------------------------------------------------- + -- Instruction TLB Interrupt + ------------------------------------------------------------------------------- + -- Conditions + ex3_n_ieratmiss_itlb_int(t) <= ex3_xuuc_val(t) and ex3_iu_error_q(7) and spr_ccr2_notlb; + ex3_n_tlbmiss_itlb_int(t) <= ex3_tlb_miss_q(t) and not ex3_mmu_esr_data_q(t) and not spr_ccr2_notlb; + -- Summary + ex3_n_itlb_int(t) <= ex3_n_ieratmiss_itlb_int(t) or + ex3_n_tlbmiss_itlb_int(t); + + ------------------------------------------------------------------------------- + -- Debug Interrupts [synchronous] + ------------------------------------------------------------------------------- + -- Enabled + debug_event_en_d(t) <= not (spr_epcr_duvd(t) and not spr_msr_gs(t) and not spr_msr_pr(t)); + + -- Conditions + -- Note: BRT & ICMP don't record in the DBSR if MSR[DE]=0 + ex3_n_brt_dbg_cint(t) <= ex3_xu_val(t) and ex3_br_update_q and spr_dbcr0_brt(t) and msr_de_q(t) and debug_event_en_q(t); + ex3_n_trap_dbg_cint(t) <= ex3_xu_val(t) and alu_cpl_ex3_trap_val and spr_dbcr0_trap(t) and debug_event_en_q(t); + ex3_n_ret_dbg_cint(t) <= ex3_xu_val(t) and (ex3_is_rfi_q or ex3_is_rfgi_q) and spr_dbcr0_ret(t) and debug_event_en_q(t); + + ex3_n_iac_dbg_cint(t) <= not ram_mode_q(t) and not ex5_in_ucode_q(t) and + ((ex3_xuuc_val(t) and not ex3_xu_is_ucode_q) or + (ex3_axu_val(t) and not ex3_axu_is_ucode_q(t))) and + (ex3_iac1_cmpr(t) or + ex3_iac2_cmpr(t) or + ex3_iac3_cmpr(t) or + ex3_iac4_cmpr(t)) and debug_event_en_q(t); + + ex3_n_async_dacr_dbg_cint(t) <= not ex3_async_int_block(t) and + (fxu_cpl_ex3_dac1r_cmpr_async(t) or + fxu_cpl_ex3_dac2r_cmpr_async(t)); + + ex3_n_dacr_dbg_cint_xu(t) <= fxu_cpl_ex3_dac1r_cmpr(t) or + fxu_cpl_ex3_dac2r_cmpr(t) or + fxu_cpl_ex3_dac3r_cmpr(t) or + fxu_cpl_ex3_dac4r_cmpr(t); + + ex3_n_dacw_dbg_cint_xu(t) <= fxu_cpl_ex3_dac1w_cmpr(t) or + fxu_cpl_ex3_dac2w_cmpr(t) or + fxu_cpl_ex3_dac3w_cmpr(t) or + fxu_cpl_ex3_dac4w_cmpr(t); + + ex3_n_dac_dbg_cint(t) <=(ex3_xu_val(t) and ( ex3_n_dacr_dbg_cint_xu(t) or + ex3_n_dacw_dbg_cint_xu(t))) and debug_event_en_q(t); + + + ex3_n_ivc_dbg_match(t) <= not ex5_in_ucode_q(t) and ( + (ex3_xuuc_val(t) and ex3_xu_instr_match_q and not ex3_xu_is_ucode_q) or + (ex3_axu_val(t) and ex3_axu_instr_match_q(t) and not ex3_axu_is_ucode_q(t))); + + ex3_n_ivc_dbg_cint(t) <= spr_dbcr3_ivc(t) and ex3_n_ivc_dbg_match(t) and debug_event_en_q(t); + + ex3_n_instr_dbg_cint(t) <= ex4_debug_flush_en_d(t) and (ex3_n_ivc_dbg_cint(t) or ex3_n_iac_dbg_cint(t)); + + ------------------------------------------------------------------------------- + -- Debug Interrupts [asynchronous] + ------------------------------------------------------------------------------- + -- Enable + ex3_np1_dbg_cint_en(t) <= not ex3_async_int_block(t); + ex3_np1_ide_dbg_cint(t) <= ex3_np1_dbg_cint_en(t) and debug_event_en_q(t) and + spr_cpl_dbsr_ide(t) and dbcr0_idm_q(t) and msr_de_q(t); + ex3_np1_ude_dbg_cint(t) <= ex3_np1_dbg_cint_en(t) and + force_ude_q(t) and debug_event_en_q(t); + + ex3_np1_ude_dbg_event(t) <= force_ude_q(t) and debug_event_en_q(t); + + + ------------------------------------------------------------------------------- + -- Doorbell Interrupt + ------------------------------------------------------------------------------- + ex3_np1_dbell_int(t) <= spr_cpl_dbell_interrupt(t) and not ex3_async_int_block(t); + + ------------------------------------------------------------------------------- + -- Critical Doorbell Interrupt + ------------------------------------------------------------------------------- + ex3_np1_cdbell_cint(t) <= spr_cpl_cdbell_interrupt(t) and not ex3_async_int_block(t); + + ------------------------------------------------------------------------------- + -- Guest Doorbell Interrupt + ------------------------------------------------------------------------------- + ex3_np1_gdbell_int(t) <= spr_cpl_gdbell_interrupt(t) and not ex3_async_int_block(t); + + ------------------------------------------------------------------------------- + -- Guest Critical Doorbell Interrupt + ------------------------------------------------------------------------------- + ex3_np1_gcdbell_cint(t) <= spr_cpl_gcdbell_interrupt(t) and not ex3_async_int_block(t); + + ------------------------------------------------------------------------------- + -- Guest Machine Check Doorbell Interrupt + ------------------------------------------------------------------------------- + ex3_np1_gmcdbell_cint(t) <= spr_cpl_gmcdbell_interrupt(t) and not ex3_async_int_block(t); + + + ------------------------------------------------------------------------------- + -- Hypervisor Privilege Interrupt + ------------------------------------------------------------------------------- + -- Enable + msr_guest_priv(t) <= not msr_pr_q(t) and msr_gs_q(t); + -- Conditions + ex3_n_spr_hpriv_int_xuuc(t) <= msr_guest_priv(t) and spr_cpl_ex3_spr_hypv; + ex3_n_instr_hpriv_int_xuuc(t) <= msr_guest_priv(t) and dec_cpl_ex3_instr_hypv; + ex3_n_ehpriv_hpriv_int(t) <= ex3_xu_val(t) and ex3_is_ehpriv_q; + -- tlbwe when all ways are IPROT=1 or attempted to install invalid entry in LRAT + ex3_n_mmu_hpriv_int(t) <= msr_guest_priv(t) and ex3_mmu_hv_priv_q(t); + -- Summary + ex4_n_any_hpriv_int_d(t) <=(ex3_xuuc_val(t) and (ex3_n_spr_hpriv_int_xuuc(t) or + ex3_n_instr_hpriv_int_xuuc(t))) + or + ex3_n_ehpriv_hpriv_int(t) or + ex3_n_mmu_hpriv_int(t); + + + ------------------------------------------------------------------------------- + -- Instruction LRAT Interrupt + ------------------------------------------------------------------------------- + ex3_n_ilrat_int(t) <= ex3_lrat_miss_q(t) and ex3_mmu_esr_pt_q(t) and not ex3_mmu_esr_data_q(t); -- PTE Reload missed in the LRAT + + ------------------------------------------------------------------------------- + -- Data LRAT Interrupt + ------------------------------------------------------------------------------- + -- Conditions + ex3_n_ptemiss_dlrat_int(t) <= ex3_lrat_miss_q(t) and ex3_mmu_esr_pt_q(t) and ex3_mmu_esr_data_q(t); -- PTE Reload missed in the LRAT + ex3_n_tlbwemiss_dlrat_int(t) <= ex3_lrat_miss_q(t) and not ex3_mmu_esr_pt_q(t); -- tlbwe missed in the LRAT + -- Summary + ex3_n_dlrat_int(t) <= ex3_n_ptemiss_dlrat_int(t) or + ex3_n_tlbwemiss_dlrat_int(t); + + + ------------------------------------------------------------------------------- + -- User Decrementer Interrupt + ------------------------------------------------------------------------------- + ex3_np1_udec_int(t) <= spr_cpl_udec_interrupt(t) and not ex3_async_int_block(t); + + ------------------------------------------------------------------------------- + -- Performance Monitor Interrupt + ------------------------------------------------------------------------------- + ex3_np1_perf_int(t) <= spr_cpl_perf_interrupt(t) and not ex3_async_int_block(t); + + --============================================================================= + --============================================================================= + -- + -- Flush Conditions + -- + --============================================================================= + --============================================================================= + + ------------------------------------------------------------------------------- + -- NP1 Flushes + ------------------------------------------------------------------------------- + -- Conditions + ex3_np1_instr_flush(t) <= ex3_xu_val(t) and ex3_np1_instr_flush_q; + + ex3_np1_sprg_ce_flush(t) <= or_reduce(ex3_xu_val) and spr_cpl_ex3_sprg_ce; + + ex3_np1_fu_flush(t) <= not ex3_flush(t) and + not fu_xu_ex3_flush2ucode(t) and + fu_xu_ex3_np1_flush(t); + + ex3_np1_run_ctl_flush(t) <= or_reduce(ex3_xu_val) and ex3_np1_run_ctl_flush_q(t); + + ex3_non_uc_val(t) <=(ex3_xu_val(t) and not ex3_xu_is_ucode_q) or + (ex3_axu_val(t) and not ex3_axu_is_ucode_q(t)); + + ex3_np1_step_flush(t) <= ex4_step_q(t) and ex3_non_uc_val(t); + + ex3_np1_init_flush(t) <= pc_init_reset_q; + + ex3_np1_mtxucr0_flush(t) <= or_reduce(ex3_xu_val) and ex3_is_mtxucr0_q; + + -- Summary + ex3_np1_flush(t) <= ex3_np1_instr_flush(t) or + ex3_np1_mtiar_flush(t) or + ex3_np1_run_ctl_flush(t) or + ex3_np1_step_flush(t) or + ex3_np1_init_flush(t) or + ex3_np1_sprg_ce_flush(t) or + ex3_np1_mtxucr0_flush(t) or + slowspr_flush_q(t); + + ------------------------------------------------------------------------------- + -- N Flush [I-ERAT Miss] + ------------------------------------------------------------------------------- + ex3_n_imiss_flush(t) <= ex3_xuuc_val(t) and ex3_iu_error_q(7) and not spr_ccr2_notlb; + ex4_n_imiss_flush(t) <= ex4_n_flush_pri(IMISSn); + + ------------------------------------------------------------------------------- + -- N Flush [D-ERAT Miss] + ------------------------------------------------------------------------------- + ex3_n_dmiss_flush(t) <= ex3_xuuc_val(t) and derat_xu_ex3_miss(t) and not spr_ccr2_notlb; + ex4_n_dmiss_flush(t) <= ex4_n_flush_pri(DMISSn); + + ------------------------------------------------------------------------------- + -- N Flush [Dependant] + ------------------------------------------------------------------------------- + + -- tlb structural hazard due to tlb reload + ex3_n_derat_dep_flush(t) <= ex3_xuuc_val(t) and derat_xu_ex3_n_flush_req(t); + -- dependant op following load miss + ex3_n_lsu_dep_flush(t) <= (ex3_xuuc_val(t) or ex3_dep_val(t)) and lsu_xu_ex3_dep_flush; + -- dependant op following load miss (FU version) + ex3_n_fu_dep_flush(t) <= not ex3_flush(t) and + not fu_xu_ex3_flush2ucode(t) and + fu_xu_ex3_n_flush(t); + + ex3_n_dep_flush(t) <= ex3_n_lsu_dep_flush(t) or + ex3_n_derat_dep_flush(t) or + ex3_n_fu_dep_flush(t); + + ------------------------------------------------------------------------------- + -- N Flush [Load Queue Hit] + ------------------------------------------------------------------------------- + ex3_n_ldq_hit_flush(t) <= lsu_xu_ex3_ldq_hit_flush; + + ------------------------------------------------------------------------------- + -- N Flush [Load Queue Full] + ------------------------------------------------------------------------------- +-- ex3_n_ldq_full_flush(t) <= lsu_xu_ex4_ldq_full_flush; + ex4_n_ldq_full_flush(t) <= ex4_xu_val_q(t) and lsu_xu_ex4_ldq_full_flush; + + + + + ------------------------------------------------------------------------------- + -- N Flushes + ------------------------------------------------------------------------------- + -- Conditions + ex3_n_ram_flush(t) <= ram_flush_q(t); + ex3_n_mmuhold_flush(t) <= ex3_mmu_hold_val(t); + ex3_n_ici_flush(t) <= or_reduce(ex3_xu_val) and not ex3_xu_val(t) and ex3_is_ici_q; -- N Flushes other threads + ex3_n_dci_flush(t) <= or_reduce(ex3_xu_val) and not ex3_xu_val(t) and ex3_is_dci_q; -- N Flushes other threads + ex3_n_mmu_flush(t) <= mm_xu_ex3_flush_req(t); + ex3_n_thrctl_stop_flush(t) <= (pc_dbg_stop_q(t) and not pc_dbg_stop_2_q(t)) and not (ex5_in_ucode_q(t) or ex4_ucode_val(t)); + ex3_n_multcoll_flush(t) <= ex3_xu_val(t) and dec_cpl_ex3_mult_coll; + ex3_n_ierat_flush(t) <= ex3_anyuc_val(t) and ex3_ierat_flush_req_q(t); + + -- Summary + ex3_n_flush(t) <= ex3_n_ram_flush(t) or + ex3_n_mmuhold_flush(t) or + ex3_n_ici_flush(t) or + ex3_n_dci_flush(t) or + ex3_n_mmu_flush(t) or + ex3_n_ierat_flush(t) or + ex5_n_ext_dbg_stopc_flush_q or + ex3_n_thrctl_stop_flush(t) or + ex3_n_multcoll_flush(t); + + ex4_n_lsu_ddmh_flush_en_d(t) <= (or_reduce(ex3_xu_val) and dec_cpl_ex3_ddmh_en) or dec_cpl_ex3_back_inv; + ex4_n_lsu_ddmh_flush(t) <= ex4_n_lsu_ddmh_flush_en_q(t) and lsu_xu_ex4_n_lsu_ddmh_flush(t); -- N Flushes all threads + + ex3_n_lsu_flush(t) <= lsu_xu_ex3_n_flush_req; + ex4_n_lsu_flush(t) <= ex4_xu_val_q(t) and ex4_n_lsu_flush_q(t); + + ------------------------------------------------------------------------------- + -- N Flushes [parity errors] + ------------------------------------------------------------------------------- + ex3_n_demh_mchk_flush(t) <= ex3_n_dexx_mchk_flush_en(t) and ex3_xu_val(t) and lsu_xu_ex3_derat_multihit_err(t); + ex3_n_depe_mchk_flush(t) <= ex3_n_dexx_mchk_flush_en(t) and ex3_xu_val(t) and lsu_xu_ex3_derat_par_err(t); + ex3_n_lsu_dcpe_flush(t) <= or_reduce(ex6_xu_val_q) and lsu_xu_ex6_datc_par_err; + ex3_n_lsu_ddpe_flush(t) <= or_reduce(ex3_xu_val) and lsu_xu_ex3_ddir_par_err; -- N Flushes all threads + ex3_n_fu_rfpe_flush(t) <= or_reduce(ex3_n_fu_rfpe_det); -- N Flushes all threads + ex3_n_xu_rfpe_flush(t) <= or_reduce(ex3_xuuc_val or ex3_dep_val) and gpr_cpl_ex3_regfile_err_det; -- N Flushes all threads + ex3_n_sprg_ue_flush(t) <= ex3_xu_val(t) and spr_cpl_ex3_sprg_ue; + + -- Summary + ex3_n_pe_flush(t) <= ex3_n_l2_ecc_err_flush_q(t) or + ex3_n_dcpe_flush_q(t) or + ex3_n_lsu_dcpe_flush(t) or + ex3_n_lsu_ddpe_flush(t) or + ex3_n_fu_rfpe_flush(t) or + ex3_n_xu_rfpe_flush(t) or + ex3_n_sprg_ue_flush(t) or + ex3_n_demh_mchk_flush(t) or + ex3_n_depe_mchk_flush(t); + + ------------------------------------------------------------------------------- + -- N Flushes [to uCode] + ------------------------------------------------------------------------------- + -- Conditions + ex3_n_lsualign_2ucode_flush(t) <= ex3_xu_val(t) and lsu_xu_ex3_inval_align_2ucode; + ex3_n_fu_2ucode_flush(t) <= not ex3_flush(t) and + fu_xu_ex3_flush2ucode(t) and + fu_xu_ex3_n_flush(t); + -- Summary + ex3_n_2ucode_flush(t) <= ex3_n_lsualign_2ucode_flush(t) or + ex3_n_fu_2ucode_flush(t); + + ------------------------------------------------------------------------------- + -- N Flushes [Barrier Set] + ------------------------------------------------------------------------------- + -- TID of the collision indicates which thread the original divide is running on + -- if that gets flushed, do not set the barrier. + ex3_div_coll_d(t) <= fxa_cpl_ex2_div_coll(t) and not any_flush(t); + ex3_div_coll(t) <= ex3_div_coll_q(t) and not any_flush(t); + + ex3_n_barr_flush(t) <= ex3_xu_val(t) and or_reduce(ex3_div_coll); + + + --============================================================================= + --============================================================================= + -- + -- Multi Cycle Flush Generation + -- + --============================================================================= + --============================================================================= + ex5_step_done(t) <= ex4_step_q(t) and (ex5_instr_cpl_q(t) or ex5_is_any_int(t) or ex5_n_ext_dbg_stopc_flush_q or ex5_n_ext_dbg_stopt_flush_q(t)); + ex4_np1_run_ctl_flush(t) <= or_reduce(ex4_xu_val) and ex4_np1_run_ctl_flush_q(t); + ex4_attn_flush(t) <= ex4_xu_val(t) and ex4_is_attn_q; + + ex3_thread_stop(t) <= ex5_step_done(t) or + ex5_np1_run_ctl_flush_q(t) or + ex4_n_thrctl_stop_flush_q(t) or + ex5_attn_flush_q(t); + + ex5_csi(t) <=(ex5_xu_val_q(t) and (ex5_is_mtmsr_q or ex5_is_isync_q)) or + ex5_is_any_int(t) or + ex5_is_any_rfi_q(t); + + -- Hold the xu_iu_flush interface, during multi cycle flushes + ex4_flush_act(t) <= ex4_n_flush(t) or ex4_np1_flush(t); + + ------------------------------------------------------------------------------- + -- Hold Reqests - per thread + ------------------------------------------------------------------------------- + hold_state_0(t) <= mmu_hold_present_q(t) or + derat_hold_present_q(t) or + ierat_hold_present_q(t) or + ex5_np1_irpt_dbg_cint_q(t); + + -- MMU Hold req: + -- either a local generated local or global tlbivax holds the source thead.. + -- or an incoming from bus global tlbivax that holds all threads + -- or a load/store that misses in derat holds source thread until miss is resolved from tlb + mmu_hold_request_d(t) <= mm_xu_hold_req(t) or (mmu_hold_request_q(t) and or_reduce(ex3_hold_block)); + ex3_mmu_hold_val(t) <= mmu_hold_request_q(t) and not or_reduce(ex3_hold_block); + xu_mm_hold_ack(t) <= ex6_mmu_hold_val_q(t); -- Stage out a few cycles for safety. + + mmu_hold_present_d(t) <= ex3_mmu_hold_val(t) or (mmu_hold_present_q(t) and not mm_xu_hold_done(t)); + ierat_hold_present_d(t) <= ex4_n_imiss_flush(t) or (ierat_hold_present_q(t) and not mmu_eratmiss_done_q(t)); + derat_hold_present_d(t) <= ex4_n_dmiss_flush(t) or (derat_hold_present_q(t) and not mmu_eratmiss_done_q(t)); + -- Hold present needs to stay on long enough for any MMU sourced interrupts to cccur + + ------------------------------------------------------------------------------- + -- Flush/Interrupt Condition Generation + ------------------------------------------------------------------------------- + -- External Debug Actions + ext_dbg_stop_n_d(t) <=((pc_dbg_action_q(3*t to 3*t+2) = "010") or + (pc_dbg_action_q(3*t to 3*t+2) = "110")); + ext_dbg_stop_core_d(t) <=((pc_dbg_action_q(3*t to 3*t+2) = "011") or + (pc_dbg_action_q(3*t to 3*t+2) = "111")); + ext_dbg_act_err_d(t) <= pc_dbg_action_q(3*t to 3*t+2) = "100"; + ext_dbg_act_ext_d(t) <=((pc_dbg_action_q(3*t to 3*t+2) = "101") or + (pc_dbg_action_q(3*t to 3*t+2) = "110") or + (pc_dbg_action_q(3*t to 3*t+2) = "111")); + + cpl_spr_dbcr0_edm(t) <= or_reduce(pc_dbg_action_q(3*t to 3*t+2)); + + pc_dbg_stop_d(t) <= pc_xu_stop(t) and not ex5_in_ucode_q(t); + + ex5_ext_dbg_err_d(t) <= ext_dbg_act_err_q(t) and ex4_dbsr_update(t); + ex5_ext_dbg_ext_d(t) <= ext_dbg_act_ext_q(t) and ex4_dbsr_update(t); + + ex4_step_d(t) <= pc_xu_step(t); + + ex3_ifar <= ex3_ifar_q(eff_ifar*t to eff_ifar*(t+1)-1); + ex4_ifar <= ex4_ifar_q(eff_ifar*t to eff_ifar*(t+1)-1); + + ex3_spr_lr <= spr_lr(regsize*t to regsize*(t+1)-3); + + ex3_lr_cmprl(t) <= '1' when ex3_ifar(32 to 61) = ex3_spr_lr(32 to 61) else '0'; + ex3_cia_cmprl(t) <= '1' when ex3_ifar(32 to 61) = ex4_cia(32 to 61) else '0'; + ex4_cia_cmprl(t) <= '1' when ex4_ifar(32 to 61) = ex4_cia(32 to 61) else '0'; + xuq_cpl_cmprh_gen0 : if IFAR'left < 32 generate + ex3_lr_cmprh(t) <= '1' when ex3_ifar(IFAR'left to 31) = ex3_spr_lr(IFAR'left to 31) else '0'; + ex3_cia_cmprh(t) <= '1' when ex3_ifar(IFAR'left to 31) = ex4_cia(IFAR'left to 31) else '0'; + ex4_cia_cmprh(t) <= '1' when ex4_ifar(IFAR'left to 31) = ex4_cia(IFAR'left to 31) else '0'; + end generate; + xuq_cpl_cmprh_gen1 : if IFAR'left >= 32 generate + ex3_lr_cmprh(t) <= '1'; + ex3_cia_cmprh(t) <= '1'; + ex4_cia_cmprh(t) <= '1'; + end generate; + + -- Don't care the upperhalf of the compare in 32b mode + ex3_lr_cmpr(t) <= ex3_anyuc_val_q(t) and ex3_lr_cmprl(t) and (ex3_lr_cmprh(t) or not msr_cm_q(t)); + ex3_cia_cmpr(t) <= ex3_anyuc_val_q(t) and ex3_cia_cmprl(t) and (ex3_cia_cmprh(t) or not msr_cm_q(t)); + ex4_cia_cmpr(t) <= ex4_anyuc_val_q(t) and ex4_cia_cmprl(t) and (ex4_cia_cmprh(t) or not msr_cm_q(t)); + + -- BLR Checking + -- Clear the bit on a valid instruction or a flush. If the XU redirects via flush, + -- the fetch will be guaranteed correct next time and there is no need for the check. + ex4_clear_bclr_chk(t) <= (ex4_anyuc_val_q(t) and not ram_mode_q(t)) or ex5_late_flush_q(0)(t); + + ex4_taken_bclr(t) <= (ex4_taken_bclr_q and ex4_xu_val(t)); + ex5_check_bclr_d(t) <= (ex5_check_bclr_q(t) and not ex4_clear_bclr_chk(t)) or -- Clear on next valid instr or flush + ex4_taken_bclr(t); -- Set after bclr + + ex5_check_bclr(t) <= ex5_check_bclr_q(t) and not ex4_clear_bclr_chk(t); + + ex3_bclr_cmpr_b(t) <= (not ex3_lr_cmpr(t) and ex4_taken_bclr(t)) or -- bclr with instr BTB, ex4_cia not updated yet + (not ex3_cia_cmpr(t) and ex5_check_bclr(t)); -- use ex4_cia here, LR could have updated due bclrl + + ex3_n_bclr_ta_miscmpr_flush(t) <= not ram_mode_q(t) and ex3_anyuc_val(t) and ex3_bclr_cmpr_b(t); + + -- IFAR Checking + ex4_check_cia(t) <=((ex4_xu_val_q(t) or ex4_axu_val_q(t)) and not ex5_in_ucode_q(t)) or -- Don't check the end of a ucode op... + ex4_ucode_val_q(t); -- Check uCode issue + + ex5_err_nia_miscmpr_d(t) <= ex4_instr_cpl(t) and ex4_check_cia(t) and not ex4_cia_cmpr(t) and not (ex4_taken_bclr(t) or ex5_check_bclr_q(t)); + + -- Page Crossing detection + ex4_mem_attr_act(t) <= ex4_ucode_val(t); + + ex4_mem_attr_val(t) <=(ex4_ucode_val(t) and (ex4_is_any_store_dac_q or ex4_is_any_load_dac_q)) or + (ex5_mem_attr_val_q(t) and ex5_in_ucode_q(t)); + + ex3_mem_attr_cmpr(t) <= '1' when lsu_xu_ex3_attr = ex5_mem_attr_q else '0'; + + ex3_mem_attr_chk(t) <= ex5_in_ucode_q(t) and ex5_mem_attr_val_q(t) and -- uCode attributes valid + (ex3_xu_val(t) and (ex3_is_any_store_dac_q or -- Valid store + ex3_is_any_load_dac_q)); -- Valid load + + ex3_n_memattr_miscmpr_flush(t) <= ex3_mem_attr_chk(t) and not ex3_mem_attr_cmpr(t); + + ex5_mem_attr_le_d(t) <= ex4_mem_attr_q(8) xor ex4_byte_rev_q; + + -- uCode + ex4_ucode_end(t) <= ex5_in_ucode_q(t) and ((ex4_xu_val_q(t) and not ex4_xu_is_ucode_q) or + (ex4_axu_val_q(t) and not ex4_axu_is_ucode_q(t)) or + ex5_is_any_int(t)); + + ex5_in_ucode_d(t) <= ex4_ucode_val(t) or (ex5_in_ucode_q(t) and not (((ex4_np1_flush(t) or ex4_n_flush(t)) and ex4_ucode_restart(t)) or ex5_is_any_int(t))); + + -- Interrupt blocking + ssprwr_ip_d(t) <=(ex4_xu_val(t) and ex4_is_slowspr_wr_q) or + (ssprwr_ip_q(t) and not mux_cpl_slowspr_done(t)); + + exx_instr_async_block_d(t)(1) <= rf1_xu_val(t) and (rf1_is_wait or rf1_is_eratre or rf1_is_tlbwe or rf1_is_tlbre or rf1_is_tlbsx or rf1_is_tlbsrx); + exx_instr_async_block_d(t)(2 to 7) <= exx_instr_async_block_q(t)(1 to 6); + + + -- In RAM Mode + -- In uCode + -- XU uCode Start + --AXU uCode Start + -- Wait instruction in pipe + -- If MSR is updated here a potential interrupt will not get + -- the updated value... blocking is easiest for timing. + ex3_async_int_block_cond(t) <= (ex2_xu_val_q(t) and (ex2_msr_updater or ex2_mtiar or ex2_is_slowspr_wr_q)) or + or_reduce(exx_instr_async_block_q(t)) or + ex4_n_flush_cond(IMISSn) or ex4_n_flush_cond(DMISSn); + -- MMU Hold present not needed, exx_hold0_mcflush will be on in time + + ex3_base_int_block_cond(t) <= ex4_is_mchk_int(t) or ex4_is_crit_int(t) or ex4_is_base_int(t); + ex3_mchk_int_block_cond(t) <= ex4_is_mchk_int(t); + + ex3_hold_block(t) <= ssprwr_ip_q(t) or + ex5_in_ucode_q(t); + + ex3_async_int_block_noaxu(t) <= + ssprwr_ip_q(t) or + ram_mode_q(t) or + ex5_in_ucode_q(t) or + ex3_async_int_block_q(t) or + exx_hold0_mcflush(t) or + exx_hold1_mcflush(t) or + ex4_async_block(t) or + ex4_base_int_block_q(t) or + spare_4_q(4+t); + + + -- Don't block FPenabled ints due to ICMP. FPenabled has higher priority. + ex3_async_int_block(t) <= ex3_async_int_block_noaxu(t) or ex3_axu_async_block_q(t) or ex4_icmp_async_block(t); + + -- Timing Note: base_int_block is causing timing problems. Replacing it with a latched version + ex4_async_block + -- to cover the first cycle after. Can also remove IMISS/DMISS, as they are also included. + + + ex3_debug_int_en(t) <= msr_de_q(t) and dbcr0_idm_q(t) and not (ex4_is_crit_int(t) or ex4_is_mchk_int(t) or ext_dbg_stop_n_q(t) or ext_dbg_stop_core_q(t)); + + ex4_debug_flush_en_d(t) <= ex3_debug_int_en(t) or ext_dbg_stop_n_q(t) or ext_dbg_stop_core_q(t); + + -- This signal will clock gate ESR[FP,AP,SPV,ST,EPID] + -- so they are saved during uCode, flush-to-uCode, and HW table walk + -- Update for non-ucode instructions or on uCode pre-issue. + -- Need to also catch the last cycle of ucode. + -- Use in_ucode for this, we flush after so there's cycles to account for this to clear. + ex3_esr_bit_act(t) <= not (ex3_flush(t) and not ex4_n_flush_pri(F2Un)) and + (ex3_ucode_val_q(t) or + (ex3_xu_val_q(t) and not (ex5_in_ucode_q(t) or ex3_xu_is_ucode_q )) or + (ex3_axu_val_q(t) and not (ex5_in_ucode_q(t) or ex3_axu_is_ucode_q(t)))); + + ------------------------------------------------------------------------------- + -- IFAR Mux + ------------------------------------------------------------------------------- + ex5_sel_rt_d(t) <= ex4_np1_mtiar_flush(t) or ex4_is_any_rfi(t); + + with s3'(ex5_is_any_hint(t) & ex5_is_any_gint(t) & ex5_sel_rt_q(t)) select + ex5_flush_ifar <= spr_ivpr(62-eff_ifar to 51) & ex5_ivo & "00" when "100", + spr_givpr(62-eff_ifar to 51) & ex5_ivo & "00" when "010", + ex5_rt_q(62-eff_ifar to 61) when others; + + + flush_ifar_repwr : for r in 1 to ifar_repwr-1 generate + with (ex5_late_flush_q(r)(t)) select + flush_ifar(64-8*(r+1) to 63-8*r) <= not ex4_cia_b_q(64-8*(r+1) to 63-8*r) when '1', + ex2_br_flush_ifar(64-8*(r+1) to 63-8*r) when others; + end generate; + with (ex5_late_flush_q(0)(t)) select + flush_ifar(56 to 61) <= not ex4_cia_b_q(56 to 61) when '1', + ex2_br_flush_ifar(56 to 61) when others; + + ------------------------------------------------------------------------------- + -- Next instruction address + ------------------------------------------------------------------------------- + ex4_instr_cpl_d(t) <=((ex3_xu_val(t) and not ex3_xu_is_ucode_q) or + (ex3_axu_val(t) and not ex3_axu_is_ucode_q(t))); + + ex4_instr_cpl(t) <= not ram_mode_q(t) and ex4_instr_cpl_q(t) and not ex4_flush(t); + ex4_ram_cpl(t) <= ex4_instr_cpl_q(t) and not ex4_flush(t); + + ex5_flush_update(t) <= ex5_is_any_int(t) or ex5_is_any_rfi_q(t) or ex5_sel_rt_q(t); + + -- Update NIA on a taken branch + with (ex4_xu_val_q(t) and ex4_br_update_q) select + ex4_nia_instr <= ex4_br_flush_ifar_q when '1', -- Branch IFAR + ex4_cia_p1 when others; -- Current IFAR + 1 + + -- Update CIA due to flushes + with ex5_flush_update(t) select + ex4_cia_flush <= ex5_flush_ifar when '1', + ex4_cia when others; + + -- Update NIA when a new instr completes + with (ex4_instr_cpl(t)) select + ex4_nia_cpl <= (ex4_nia_instr and ex4_cm_mask) when '1', -- Next Instr + (ex4_cia_flush and ex4_cm_mask) when others; -- Current/No Instr (or Flushed IAR) + + ex4_nia <= ex4_nia_cpl; + ex4_cia <= not ex4_cia_b_q; + ex4_cia_b_d <= not ex4_nia; + + ex4_cia_p1 <= std_ulogic_vector(unsigned(ex4_cia) + 1); + + -- Preserve the upper 32bits of the ifar until msr_cm_q is stable. + ex5_cm_hold_cond(t) <= (ex5_xu_val_q(t) and ex5_is_mtmsr_q) or ex5_is_any_int(t) or ex5_is_any_rfi_q(t); + + ex4_cm(t) <= msr_cm_q(t) or exx_cm_hold(t); + + ex4_cm_mask(32 to 61) <= (others=>'1'); + xuq_cpl_cm_mask_gen : if IFAR'left < 32 generate + ex4_cm_mask(IFAR'left to 31) <= (others=>ex4_cm(t)); + end generate; + + ex3_cia_act(t) <= ex4_instr_cpl_q(t) or ex5_flush_update(t) or exx_cm_hold(t) or exx_cm_hold_q(t) or spr_xucr0_clkg_ctl(2); + + ex4_nia_act(t) <= ex4_cia_act_q(t) or ex3_cia_act(t) or ex4_n_flush(t) or ex4_np1_flush(t); + + ------------------------------------------------------------------------------- + -- uCode "Next instruction address" + ------------------------------------------------------------------------------- + ex5_uc_cia_val_d(t) <= ex5_in_ucode_q(t) and ex4_uc_cia_val(t); + ex4_uc_cia_val(t) <= ex5_in_ucode_q(t) and (ex5_uc_cia_val_q(t) or ex4_any_val(t)); + + ex3_uc_cia_act(t) <= clkg_ctl_q or (ex5_in_ucode_q(t) and (ex4_xu_val_q(t) or ex4_axu_val_q(t))); + + -- Capture NIA when a new instr completes + -- The IU needs the IFAR of the op being flushed (if there is one there) + with (ex4_xu_val_q(t) or ex4_axu_val_q(t)) select + ex4_uc_nia <= ex4_ifar(IFAR_UC'range) when '1', + ex4_uc_cia_q when others; + + -- Don't capture ops that were flushed into the capture latch (See note above) + with ex4_n_flush(t) select + ex4_uc_cia_d <= ex4_uc_cia_q when '1', + ex4_uc_nia when others; + + xu_iu_uc_flush_ifar(uc_ifar*t to uc_ifar*(t+1)-1) <= ex4_uc_cia_q; + + ------------------------------------------------------------------------------- + -- Exception Priority + ------------------------------------------------------------------------------- + ex4_dbsr_cond(0) <= ex4_n_ivc_dbg_cint_q(t) or + ex4_n_iac_dbg_cint_q(t); + + ex4_dbsr_cond(1) <= ex4_n_dac_dbg_cint_q(t) or + ex4_n_ret_dbg_cint_q(t) or + ex4_n_brt_dbg_cint_q(t) or + ex4_n_trap_dbg_cint_q(t); + + -- Only allow the DBSR to be set, if: + -- the interrupt occured + -- the instruction completed + ex4_dbsr_en_cond(0) <= ex4_anyuc_val(t) or ex4_n_flush_pri(DBG0n); + ex4_dbsr_en_cond(1) <= ex4_anyuc_val(t) or ex4_n_flush_pri(DBG1n); + + ex4_n_flush_cond(PREVn) <= exx_np1_irpt_dbg_cint(t) or exx_np1_icmp_dbg_cint(t) or (ex4_debug_flush_en_q(t) and ex4_n_async_dacr_dbg_cint_q(t)); + ex4_n_flush_cond(BTAn) <= ex4_n_bclr_ta_miscmpr_flush_q(t); + ex4_n_flush_cond(DEPn) <= ex4_n_dep_flush_q(t) or ex4_n_tlb_mchk_flush_q(t); + ex4_n_flush_cond(IMISSn) <= ex4_n_imiss_flush_q(t); + ex4_n_flush_cond(IMCHKn) <= ex4_n_imchk_mcint_q(t) or ex4_n_ieratsx_par_mchk_mcint_q(t); + ex4_n_flush_cond(DBG0n) <= ex4_n_instr_dbg_cint_q(t); + ex4_n_flush_cond(ITLBn) <= ex4_n_itlb_int_q(t); + ex4_n_flush_cond(ISTORn) <= ex4_n_istor_int_q(t); + ex4_n_flush_cond(ILRATn) <= ex4_n_ilrat_int_q(t); + ex4_n_flush_cond(FPEn) <= ex4_n_pe_flush_q(t) or ex4_n_lsu_ddmh_flush(t); + ex4_n_flush_cond(PROG0n) <= ex4_n_pil_prog_int_q(t); + ex4_n_flush_cond(UNAVAILn) <= ex4_n_any_unavail_int_q(t); + ex4_n_flush_cond(PROG1n) <= ex4_n_ppr_prog_int_q(t); + ex4_n_flush_cond(PROG2n) <= ex4_n_puo_prog_int_q(t); + ex4_n_flush_cond(PROG3n) <= ex4_n_ena_prog_int_q(t); + ex4_n_flush_cond(HPRIVn) <= ex4_n_any_hpriv_int_q(t); + ex4_n_flush_cond(PROG0An) <= ex4_n_tlbwe_pil_prog_int_q(t); + ex4_n_flush_cond(DMCHKn) <= ex4_n_dmchk_mcint_q(t) or ex4_n_ddmh_mchk_mcint(t); + ex4_n_flush_cond(DTLBn) <= ex4_n_dtlb_int_q(t); + ex4_n_flush_cond(DMISSn) <= ex4_n_dmiss_flush_q(t); + ex4_n_flush_cond(DSTORn) <= ex4_n_dstor_int_q(t); + ex4_n_flush_cond(ALIGNn) <= ex4_n_align_int_q(t) or ex4_n_memattr_miscmpr_flush_q(t); + ex4_n_flush_cond(DLRATn) <= ex4_n_dlrat_int_q(t); + ex4_n_flush_cond(DBG1n) <= ex4_debug_flush_en_q(t) and ex4_dbsr_cond(1); + ex4_n_flush_cond(F2Un) <= ex4_n_2ucode_flush_q(t); + ex4_n_flush_cond(FwBSn) <= ex4_n_barr_flush_q(t) or (ex4_xu_val_q(t) and ex4_n_ldq_hit_flush_q(t)); + ex4_n_flush_cond(Fn) <= ex4_n_flush_q(t) or ex4_n_ldq_full_flush(t) or ex4_n_lsu_flush(t) or ex4_thread_stop_q(t); + + ex4_np1_flush_cond(INSTRnp1) <= ex4_np1_instr_int_q(t); + ex4_np1_flush_cond(MCHKnp1) <= ex4_np1_ext_mchk_mcint_q(t); + ex4_np1_flush_cond(GDBMCHKnp1) <= ex4_np1_gmcdbell_cint_q(t); + ex4_np1_flush_cond(DBG3np1) <= ex4_debug_flush_en_q(t) and (ex4_np1_ide_dbg_cint_q(t) or ex4_np1_ude_dbg_cint_q(t)); + ex4_np1_flush_cond(CRITnp1) <= ex4_np1_crit_cint_q(t); + ex4_np1_flush_cond(WDOGnp1) <= ex4_np1_wdog_cint_q(t); + ex4_np1_flush_cond(CDBELLnp1) <= ex4_np1_cdbell_cint_q(t); + ex4_np1_flush_cond(GCDBELLnp1) <= ex4_np1_gcdbell_cint_q(t); + ex4_np1_flush_cond(EXTnp1) <= ex4_np1_ext_int_q(t); + ex4_np1_flush_cond(FITnp1) <= ex4_np1_fit_int_q(t); + ex4_np1_flush_cond(DECnp1) <= ex4_np1_dec_int_q(t); + ex4_np1_flush_cond(DBELLnp1) <= ex4_np1_dbell_int_q(t); + ex4_np1_flush_cond(GDBELLnp1) <= ex4_np1_gdbell_int_q(t); + ex4_np1_flush_cond(UDECnp1) <= ex4_np1_udec_int_q(t); + ex4_np1_flush_cond(PERFnp1) <= ex4_np1_perf_int_q(t); + ex4_np1_flush_cond(Fnp1) <= ex4_np1_flush_q(t) or ex4_ucode_end(t) or ex4_np1_fu_flush_q(t); + + xu_cpl_n_pri : entity work.xuq_cpl_pri(xuq_cpl_pri) + generic map (size => ex4_n_flush_cond'length) + port map( + cond => ex4_n_flush_cond, + pri => ex4_n_flush_pri, + or_cond => ex4_n_flush(t)); + + xu_cpl_np1_pri : entity work.xuq_cpl_pri(xuq_cpl_pri) + generic map (size => ex4_np1_flush_cond'length) + port map( + cond => ex4_np1_flush_cond, + pri => ex4_np1_flush_pri_nongated, + or_cond => ex4_np1_flush(t)); + + ex4_np1_flush_pri <= gate(ex4_np1_flush_pri_nongated,(not ex4_n_flush(t))); + + ex4_flush_pri <= ex4_n_flush_pri & ex4_np1_flush_pri; + + ex4_async_block(t) <= ex4_n_flush(t) or ex4_np1_flush(t); + + xu_lsu_ex4_val(t) <= ex4_xu_val_q(t); + + xu_lsu_ex4_flush_local(t) <= or_reduce(ex4_n_flush_cond(PREVn to ISTORn)) or + ex4_n_flush_cond(PROG0n) or + ex4_n_flush_cond(PROG1n) or + ex4_n_flush_cond(UNAVAILn) or + ex4_n_flush_cond(PROG3n) or + ex4_n_dmchk_mcint_q(t) or -- DMCHKn + or_reduce(ex4_n_flush_cond(DTLBn to ALIGNn)) or + (ex4_debug_flush_en_q(t) and ex4_n_dac_dbg_cint_q(t)) or -- DBG1n + ex4_n_flush_cond(F2Un) or + ex4_n_flush_cond(FPEn) or -- FPEn + (ex4_xu_val_q(t) and ex4_n_ldq_hit_flush_q(t)) or -- Fn + ex4_n_flush_q(t) or ex4_n_lsu_flush(t) or -- Fn + ex4_thread_stop_q(t) or -- Fn + ex4_flush_q(t); + + ex5_flush_pri_enc_dbg(t) <= gate("000001",ex5_flush_pri_dbg_q(0)) or + gate("000010",ex5_flush_pri_dbg_q(1)) or + gate("000011",ex5_flush_pri_dbg_q(2)) or + gate("000100",ex5_flush_pri_dbg_q(3)) or + gate("000101",ex5_flush_pri_dbg_q(4)) or + gate("000110",ex5_flush_pri_dbg_q(5)) or + gate("000111",ex5_flush_pri_dbg_q(6)) or + gate("001000",ex5_flush_pri_dbg_q(7)) or + gate("001001",ex5_flush_pri_dbg_q(8)) or + gate("001010",ex5_flush_pri_dbg_q(9)) or + gate("001011",ex5_flush_pri_dbg_q(10)) or + gate("001100",ex5_flush_pri_dbg_q(11)) or + gate("001101",ex5_flush_pri_dbg_q(12)) or + gate("001110",ex5_flush_pri_dbg_q(13)) or + gate("001111",ex5_flush_pri_dbg_q(14)) or + gate("010000",ex5_flush_pri_dbg_q(15)) or + gate("010001",ex5_flush_pri_dbg_q(16)) or + gate("010010",ex5_flush_pri_dbg_q(17)) or + gate("010011",ex5_flush_pri_dbg_q(18)) or + gate("010100",ex5_flush_pri_dbg_q(19)) or + gate("010101",ex5_flush_pri_dbg_q(20)) or + gate("010110",ex5_flush_pri_dbg_q(21)) or + gate("010111",ex5_flush_pri_dbg_q(22)) or + gate("011000",ex5_flush_pri_dbg_q(23)) or + gate("011001",ex5_flush_pri_dbg_q(24)) or + gate("011010",ex5_flush_pri_dbg_q(25)) or + gate("011011",ex5_flush_pri_dbg_q(26)) or + gate("011100",ex5_flush_pri_dbg_q(27)) or + gate("011101",ex5_flush_pri_dbg_q(28)) or + gate("011110",ex5_flush_pri_dbg_q(29)) or + gate("011111",ex5_flush_pri_dbg_q(30)) or + gate("100000",ex5_flush_pri_dbg_q(31)) or + gate("100001",ex5_flush_pri_dbg_q(32)) or + gate("100010",ex5_flush_pri_dbg_q(33)) or + gate("100011",ex5_flush_pri_dbg_q(34)) or + gate("100100",ex5_flush_pri_dbg_q(35)) or + gate("100101",ex5_flush_pri_dbg_q(36)) or + gate("100110",ex5_flush_pri_dbg_q(37)) or + gate("100111",ex5_flush_pri_dbg_q(38)) or + gate("101000",ex5_flush_pri_dbg_q(39)) or + gate("101001",ex5_flush_pri_dbg_q(40)) or + gate("101010",ex5_flush_pri_dbg_q(41)) or + gate("101011",ex5_flush_pri_dbg_q(42)); + + + ex4_n_flush_pri_dacr_async(t) <= ex4_n_flush_cond(PREVn) and ex4_n_async_dacr_dbg_cint_q(t); + + ex4_np1_flush_pri_instr(TRAP) <= not ex4_n_flush(t) and ex4_np1_ptr_prog_int_q(t); + ex4_np1_flush_pri_instr(SC) <= not ex4_n_flush(t) and ex4_np1_sc_int_q(t); + ex4_np1_flush_pri_instr(RFI) <= not ex4_n_flush(t) and ex4_np1_rfi_q(t); + + ex4_n_flush_pri_unavail(FP) <= ex4_n_flush_pri(UNAVAILn) and ex4_n_fp_unavail_int_q(t); + ex4_n_flush_pri_unavail(AP) <= ex4_n_flush_pri(UNAVAILn) and ex4_n_ap_unavail_int_q(t); + ex4_n_flush_pri_unavail(VEC) <= ex4_n_flush_pri(UNAVAILn) and ex4_n_vec_unavail_int_q(t); + + ex4_n_flush_pri_ena(APENA) <= ex4_n_flush_pri(PROG3n) and ex4_apena_prog_int_q(t); + ex4_n_flush_pri_ena(FPENA) <= ex4_n_flush_pri(PROG3n) and ex4_fpena_prog_int_q(t); + + ex4_n_flush_pri_ehpriv(t) <= ex4_n_flush_pri(HPRIVn) and ex4_is_ehpriv_q; + + ex4_n_flush_sprg_ue_flush(t) <= ex4_n_flush_pri(FPEn) and ex4_n_sprg_ue_flush_q(t); + + -- Delay ICMP until just before the next instruction. This strategy should account for barrier ops + + ex4_icmp_event_on_int_ok(t) <= ex4_n_flush_pri_ehpriv(t) or ex4_np1_flush_pri_instr(SC) or ex4_np1_flush_pri_instr(TRAP); + + -- ehpriv/sc/trap causes a flushes, but still needs to set the DBSR. + -- ICMP can only occur or record when DE=1 + ex4_np1_icmp_dbg_en(t) <= spr_dbcr0_icmp(t) and msr_de_q(t) and debug_event_en_q(t); + ex4_np1_icmp_dbg_event(t) <= ex4_np1_icmp_dbg_en(t) and (ex4_instr_cpl(t) or ex4_icmp_event_on_int_ok(t)); + ex4_np1_icmp_dbg_cint(t) <= ex4_np1_icmp_dbg_en(t) and ex4_instr_cpl(t) and ex4_debug_flush_en_q(t); + + ex4_icmp_async_block(t) <=(ex4_np1_icmp_dbg_en(t) and (ex3_anyuc_val_q(t) or ex4_instr_cpl_q(t))) or ex5_np1_icmp_dbg_cint_q(t); + + ex5_np1_icmp_dbg_event_d(t) <=(ex4_np1_icmp_dbg_event(t) and not ((ex5_is_any_int(t) and not ex5_icmp_event_on_int_ok_q(t)) or ex4_thread_stop_q(t))) or + (ex5_np1_icmp_dbg_event_q(t) and not (ex4_anyuc_val_q(t) or (ex5_is_any_int(t) or ex4_thread_stop_q(t)))); + + ex5_np1_icmp_dbg_cint_d(t) <=(ex4_np1_icmp_dbg_cint(t) and not (ex5_is_any_int(t) or ex4_thread_stop_q(t))) or + (ex5_np1_icmp_dbg_cint_q(t) and not (ex4_anyuc_val_q(t) or ex5_is_any_int(t) or ex4_thread_stop_q(t))); + + -- Actually take the ICMP just before the next instruction. + exx_np1_icmp_dbg_cint(t) <= ex5_np1_icmp_dbg_cint_q(t) and (ex4_anyuc_val_q(t) or ex4_thread_stop_q(t)); + exx_np1_icmp_dbg_event(t) <= ex5_np1_icmp_dbg_event_q(t) and (ex4_anyuc_val_q(t) or ex4_thread_stop_q(t) or (ex5_is_any_int(t) and ex5_icmp_event_on_int_ok_q(t))); + + ex4_n_flush_pri_icmp(t) <= ex4_n_flush_pri(PREVn) and exx_np1_icmp_dbg_cint(t); + + + -- Do the same business with IRPT... + ex4_np1_irpt_dbg_cint(t) <= ex4_is_base_int(t) and debug_event_en_q(t) and spr_dbcr0_irpt(t) and ex4_debug_flush_en_q(t); + ex4_np1_irpt_dbg_event(t) <= ex4_is_base_int(t) and debug_event_en_q(t) and spr_dbcr0_irpt(t); + + ex6_np1_irpt_dbg_cint_d(t) <= ex5_np1_irpt_dbg_cint_q(t) or + (ex6_np1_irpt_dbg_cint_q(t) and ex4_base_int_block_q(t)); + exx_np1_irpt_dbg_cint(t) <= ex6_np1_irpt_dbg_cint_q(t) and not ex4_base_int_block_q(t); + + ex6_np1_irpt_dbg_event_d(t) <= ex5_np1_irpt_dbg_event_q(t) or + (ex6_np1_irpt_dbg_event_q(t) and ex4_base_int_block_q(t)); + exx_np1_irpt_dbg_event(t) <= ex6_np1_irpt_dbg_event_q(t) and not ex4_base_int_block_q(t); + + ex4_n_flush_pri_irpt(t) <= ex4_n_flush_pri(PREVn) and exx_np1_irpt_dbg_cint(t); + + + ex4_ivo_sel(0) <= ex4_np1_flush_pri(CRITnp1); + ex4_ivo_sel(1) <= ex4_mchk_int_en_q(t) and (ex4_n_flush_pri(IMCHKn) or ex4_n_flush_pri(DMCHKn) or ex4_np1_flush_pri(MCHKnp1)); + ex4_ivo_sel(2) <= ex4_n_flush_pri(DSTORn); + ex4_ivo_sel(3) <= ex4_n_flush_pri(ISTORn); + ex4_ivo_sel(4) <= ex4_np1_flush_pri(EXTnp1); + ex4_ivo_sel(5) <= ex4_n_flush_pri(ALIGNn); + ex4_ivo_sel(6) <= ex4_n_flush_pri(PROG0n) or ex4_n_flush_pri(PROG0An) or ex4_n_flush_pri(PROG1n) or ex4_n_flush_pri(PROG2n) or ex4_n_flush_pri(PROG3n) or ex4_np1_flush_pri_instr(TRAP); + ex4_ivo_sel(7) <= ex4_n_flush_pri_unavail(FP); + ex4_ivo_sel(8) <= ex4_np1_flush_pri_instr(SC) and not ex4_sc_lev_q; + ex4_ivo_sel(9) <= ex4_n_flush_pri_unavail(AP); + ex4_ivo_sel(10) <= ex4_np1_flush_pri(DECnp1); + ex4_ivo_sel(11) <= ex4_np1_flush_pri(FITnp1); + ex4_ivo_sel(12) <= ex4_np1_flush_pri(WDOGnp1); + ex4_ivo_sel(13) <= ex4_n_flush_pri(DTLBn); + ex4_ivo_sel(14) <= ex4_n_flush_pri(ITLBn); + ex4_ivo_sel(15) <= (ex4_debug_int_en_q(t) and (ex4_n_flush_pri(DBG0n) or ex4_n_flush_pri(DBG1n) or ex4_np1_flush_pri(DBG3np1) or ex4_n_flush_pri_dacr_async(t) or ex4_n_flush_pri_icmp(t) or ex4_n_flush_pri_irpt(t))); + ex4_ivo_sel(16) <= ex4_n_flush_pri_unavail(VEC); + ex4_ivo_sel(17) <= ex4_np1_flush_pri(DBELLnp1); + ex4_ivo_sel(18) <= ex4_np1_flush_pri(CDBELLnp1); + ex4_ivo_sel(19) <= ex4_np1_flush_pri(GDBELLnp1); + ex4_ivo_sel(20) <= ex4_np1_flush_pri(GCDBELLnp1) or ex4_np1_flush_pri(GDBMCHKnp1); + ex4_ivo_sel(21) <= ex4_np1_flush_pri_instr(SC) and ex4_sc_lev_q; + ex4_ivo_sel(22) <= ex4_n_flush_pri(HPRIVn); + ex4_ivo_sel(23) <= ex4_n_flush_pri(ILRATn) or ex4_n_flush_pri(DLRATn); + ex4_ivo_sel(24) <= ex4_np1_flush_pri(UDECnp1); + ex4_ivo_sel(25) <= ex4_np1_flush_pri(PERFnp1); + + + ex5_dsigs_d(t) <= msr_gs_q(t) and spr_epcr_dsigs(t) and not ex4_esr_pri(VF); + ex5_isigs_d(t) <= msr_gs_q(t) and spr_epcr_isigs(t); + ex5_extgs_d(t) <= msr_gs_q(t) and spr_epcr_extgs(t); + ex5_dtlbgs_d(t) <= msr_gs_q(t) and spr_epcr_dtlbgs(t); + ex5_itlbgs_d(t) <= msr_gs_q(t) and spr_epcr_itlbgs(t); + + ex5_ivo_mask_guest(0) <= '0'; + ex5_ivo_mask_guest(1) <= '0'; + ex5_ivo_mask_guest(2) <= ex5_dsigs_q(t) and not ex5_tlb_inelig_q(t); + ex5_ivo_mask_guest(3) <= ex5_isigs_q(t) and not ex5_tlb_inelig_q(t); + ex5_ivo_mask_guest(4) <= ex5_extgs_q(t); + ex5_ivo_mask_guest(5) <= '0'; + ex5_ivo_mask_guest(6) <= '0'; + ex5_ivo_mask_guest(7) <= '0'; + ex5_ivo_mask_guest(8) <= msr_gs_q(t); + ex5_ivo_mask_guest(9) <= '0'; + ex5_ivo_mask_guest(10) <= '0'; + ex5_ivo_mask_guest(11) <= '0'; + ex5_ivo_mask_guest(12) <= '0'; + ex5_ivo_mask_guest(13) <= ex5_dtlbgs_q(t); + ex5_ivo_mask_guest(14) <= ex5_itlbgs_q(t); + ex5_ivo_mask_guest(15) <= '0'; + ex5_ivo_mask_guest(16) <= '0'; + ex5_ivo_mask_guest(17) <= '0'; + ex5_ivo_mask_guest(18) <= '0'; + ex5_ivo_mask_guest(19) <= '0'; + ex5_ivo_mask_guest(20) <= '0'; + ex5_ivo_mask_guest(21) <= '0'; + ex5_ivo_mask_guest(22) <= '0'; + ex5_ivo_mask_guest(23) <= '0'; + ex5_ivo_mask_guest(24) <= '0'; + ex5_ivo_mask_guest(25) <= '0'; + + ex5_ivo_guest_sel <= ex5_ivo_sel_q and ex5_ivo_mask_guest; + ex5_ivo_hypv_sel <= ex5_ivo_sel_q and not ex5_ivo_mask_guest; + + ex5_is_any_gint(t) <= or_reduce(ex5_ivo_guest_sel); + ex5_is_any_hint(t) <= or_reduce(ex5_ivo_hypv_sel); + + ex5_is_any_int(t) <= or_reduce(ex5_ivo_sel_q); + ex4_is_any_rfi(t) <= ex4_np1_flush_pri_instr(RFI); + + ex5_is_base_hint(t) <= or_reduce(ex5_ivo_hypv_sel(2 to 11)) or or_reduce(ex5_ivo_hypv_sel(13 to 14)) or or_reduce(ex5_ivo_hypv_sel(16 to 17)) or ex5_ivo_hypv_sel(19) or or_reduce(ex5_ivo_hypv_sel(21 to 25)); + ex5_is_base_gint(t) <= or_reduce(ex5_ivo_guest_sel(2 to 11)) or or_reduce(ex5_ivo_guest_sel(13 to 14)) or or_reduce(ex5_ivo_guest_sel(16 to 17)) or ex5_ivo_guest_sel(19) or or_reduce(ex5_ivo_guest_sel(21 to 25)); + ex4_is_base_int(t) <= or_reduce(ex4_ivo_sel(2 to 11)) or or_reduce(ex4_ivo_sel(13 to 14)) or or_reduce(ex4_ivo_sel(16 to 17)) or ex4_ivo_sel(19) or or_reduce(ex4_ivo_sel(21 to 25)); + + ex4_is_crit_int(t) <= ex4_ivo_sel(0) or ex4_ivo_sel(12) or ex4_ivo_sel(15) or ex4_ivo_sel(18) or ex4_ivo_sel(20); + ex4_is_mchk_int(t) <= ex4_ivo_sel(1); + + ex5_ivo <= gate(x"02",ex5_ivo_sel_q( 0)) or -- IVOR0 Critical Input + gate(x"00",ex5_ivo_sel_q( 1)) or -- IVOR1 Machine Check + gate(x"06",ex5_ivo_sel_q( 2)) or -- IVOR2 Data Storage + gate(x"08",ex5_ivo_sel_q( 3)) or -- IVOR3 Instr Storage + gate(x"0A",ex5_ivo_sel_q( 4)) or -- IVOR4 External Input + gate(x"0C",ex5_ivo_sel_q( 5)) or -- IVOR5 Alignment + gate(x"0E",ex5_ivo_sel_q( 6)) or -- IVOR6 Program + gate(x"10",ex5_ivo_sel_q( 7)) or -- IVOR7 FP Unavailable + gate(x"12",ex5_ivo_sel_q( 8)) or -- IVOR8 System Call + gate(x"14",ex5_ivo_sel_q( 9)) or -- IVOR9 AP Unavailable + gate(x"16",ex5_ivo_sel_q(10)) or -- IVOR10 Decrementer + gate(x"18",ex5_ivo_sel_q(11)) or -- IVOR11 Fixed Interval Timer + gate(x"1A",ex5_ivo_sel_q(12)) or -- IVOR12 Watchdog + gate(x"1C",ex5_ivo_sel_q(13)) or -- IVOR13 Data TLB Error + gate(x"1E",ex5_ivo_sel_q(14)) or -- IVOR14 Instr TLB Error + gate(x"04",ex5_ivo_sel_q(15)) or -- IVOR15 Debug + gate(x"20",ex5_ivo_sel_q(16)) or -- IVOR32 Vector Unavailable + gate(x"28",ex5_ivo_sel_q(17)) or -- IVOR36 Doorbell + gate(x"2A",ex5_ivo_sel_q(18)) or -- IVOR37 Doorbell Critical + gate(x"2C",ex5_ivo_sel_q(19)) or -- IVOR38 Guest Doorbell + gate(x"2E",ex5_ivo_sel_q(20)) or -- IVOR39 Guest Doorbell Critical / Guest Doorbell Machine Check + gate(x"30",ex5_ivo_sel_q(21)) or -- IVOR40 Embedded Hypervisor System Call + gate(x"32",ex5_ivo_sel_q(22)) or -- IVOR41 Embedded Hypervisor Privilege + gate(x"34",ex5_ivo_sel_q(23)) or -- IVOR42 LRAT Error + gate(x"80",ex5_ivo_sel_q(24)) or -- IVORXX User Decrementer + gate(x"82",ex5_ivo_sel_q(25)); -- IVORXX Performance Monitor + + -- Guest Doorbell is an oddball. It's directed to hypervisor, but it updates GSRR0/GSRR1 + ex5_force_gsrr_d(t) <= ex4_np1_flush_pri(GDBELLnp1); + + ------------------------------------------------------------------------------- + -- IO assignments + ------------------------------------------------------------------------------- + -- This signal will decrement the SRR0 by 1, since the AXU's trap comes on past completion, but the + -- architecture specifies that SRR0 be the address of the instruction that caused the trap. + -- This should only be set if the trap was unmasked. If it was unmasked by an rfi/mtmsr it + -- should get the address of the next instruction. + -- **NOTE** repurposing for other interrupts as well... + + ex4_ena_prog_int(t) <= ex4_n_flush_pri_ena(FPENA) and not ex5_axu_trap_pie_q(t); + ex4_n_ieratre_par_mcint(t) <= ex4_n_flush_pri(IMCHKn) and ex4_n_ieratre_par_mchk_mcint_q(t); + ex4_n_deratre_par_mcint(t) <= ex4_n_flush_pri(DMCHKn) and ex4_n_deratre_par_mchk_mcint_q(t); + ex4_n_mmu_hpriv_int(t) <= ex4_n_flush_pri(HPRIVn) and ex4_n_mmu_hpriv_int_q(t); + ex4_n_tlbwemiss_dlrat_int(t) <= ex4_n_flush_pri(DLRATn) and ex4_n_tlbwemiss_dlrat_int_q(t); + ex4_n_tlbwe_pil_prog_int(t) <= ex4_n_flush_pri(PROG0An); + ex4_n_tlbmh_mchk_mcint(t) <= ex4_n_flush_pri(IMCHKn) and ex4_n_tlbmh_mchk_mcint_q(t) and not mmu_eratmiss_done_q(t); + ex4_n_tlbpar_mchk_mcint(t) <= ex4_n_flush_pri(IMCHKn) and spare_5_q(t) and not mmu_eratmiss_done_q(t); + + + + ex5_srr0_dec_d(t) <= ex4_ena_prog_int(t) or + ex4_n_ieratre_par_mcint(t) or ex4_n_deratre_par_mcint(t) or + ex4_n_mmu_hpriv_int(t) or + ex4_n_tlbwemiss_dlrat_int(t) or + ex4_n_tlbwe_pil_prog_int(t) or + ex4_n_tlbmh_mchk_mcint(t) or + ex4_n_tlbpar_mchk_mcint(t); + + -- If any instruction completes after the trap signal has gone high, signal an imprecise interrupt + -- FP uCode complete comes after the trap signal has gone high, use ex5_in_ucode_q to block this. + + -- Need to account for cycles between ex4 & ex7... + -- EX4 EX5 EX6 EX7 + ex4_axu_trap_pie(t) <= not(spare_1_d(t)) or spare_1_q(t) or spare_1_q(4+t) or spare_1_q(8+t); + + ex5_axu_trap_pie_d(t) <= ex4_axu_trap_q(t) and (ex4_axu_trap_pie(t) or ex5_axu_trap_pie_q(t)); + + + -- Save a side copy of the dear on D-ERAT misses + -- Use that copy to update the dear for D-ERAT misses which resulted in an interrupt during HTW. + ex5_dear_update_saved_d(t) <= derat_hold_present_q(t); + cpl_spr_ex5_dear_update_saved(t) <= ex5_dear_update_saved_q(t); + cpl_spr_ex5_dear_save(t) <= ex5_n_dmiss_flush_q(t); + + -- Select which INTs will update which regs ... These lists go by IVOR# + cpl_spr_ex5_dear_update(t) <= ex5_ivo_sel_q(2) or ex5_ivo_sel_q(5) or ex5_ivo_sel_q(13) or (ex5_ivo_sel_q(23) and ex5_n_ptemiss_dlrat_int_q(t)); + cpl_spr_ex5_esr_update(t) <= ex5_ivo_sel_q(2) or ex5_ivo_sel_q(5) or ex5_ivo_sel_q(13) or ex5_ivo_sel_q(6) or ex5_ivo_sel_q(3) or ex5_ivo_sel_q(16) or ex5_ivo_sel_q(23); + + -- Don't allow lower priority DBSR events to be set if a higher priority event exists + -- Use the IVC/IAC signals that are not gated with MSR[DE] and DBCR[IDM] + ex4_dbsr_update(t) <= or_reduce(ex4_dbsr_cond and ex4_dbsr_en_cond) or exx_np1_icmp_dbg_event(t) or exx_np1_irpt_dbg_event(t) or ex4_n_flush_pri_dacr_async(t) or ex4_np1_ude_dbg_event_q(t); + ex4_dbsr_act(t) <= clkg_ctl_q or or_reduce(ex4_dbsr_cond) or exx_np1_icmp_dbg_event(t) or exx_np1_irpt_dbg_event(t) or ex4_n_flush_pri_dacr_async(t) or ex4_np1_ude_dbg_event_q(t); + + ex4_esr_act(t) <= clkg_ctl_q or ex4_n_flush_pri(PROG0n) or ex4_n_flush_pri(PROG1n) or ex4_n_flush_pri(PROG2n) or ex4_n_flush_pri(PROG3n) or ex4_n_flush_pri(PROG0An) or + ex4_n_flush_pri(ALIGNn) or ex4_n_flush_pri(UNAVAILn) or ex4_np1_ptr_prog_int_q(t) or + ex4_n_flush_pri(DSTORn) or ex4_n_flush_pri(DLRATn) or ex4_n_flush_pri(DTLBn) or + ex4_n_flush_pri(ISTORn) or ex4_n_flush_pri(ILRATn); + ex4_mcsr_act(t) <= clkg_ctl_q or ex4_n_flush_cond(IMCHKn) or ex4_n_flush_cond(DMCHKn) or ex4_np1_flush_cond(MCHKnp1); + + ex4_mcsr_d(0+14*t) <= ex3_n_dpovr_mchk_mcint(t); -- DPOVR: Data Port Overrun + ex4_mcsr_d(1+14*t) <= ex3_n_tlbsrej_mchk_mcint(t); -- TLBIVAXSR:TLBivax Snoop Reject + ex4_mcsr_d(2+14*t) <= ex3_n_tlblru_mchk_mcint(t); -- TLBLRUPE: TLB LRU Parity Error + ex4_mcsr_d(3+14*t) <= ex3_xuuc_val_q(t) and ex3_n_il2ecc_mchk_mcint_xuuc(t); -- IL2ECC: I$ L2 UC ECC Error + ex4_mcsr_d(4+14*t) <= ex3_n_dl2ecc_mchk_mcint(t); -- DL2ECC: D$ L2 UC ECC Error + ex4_mcsr_d(5+14*t) <= ex3_xu_val_q(t) and ex3_n_ddpe_mchk_mcint_xu(t); -- DDPE: D$ Dir Parity Error + ex4_mcsr_d(6+14*t) <= ex3_np1_ext_mchk_mcint(t); -- EXT: External Machine Check + ex4_mcsr_d(7+14*t) <= ex3_n_dcpe_mchk_mcint(t); -- DCPE: D$ Data Parity Error + ex4_mcsr_d(8+14*t) <= ex3_xuuc_val_q(t) and ex3_n_iemh_mchk_mcint_xuuc(t); -- IEMH: I-ERAT Multi-Hit + ex4_mcsr_d(9+14*t) <= ex3_xu_val_q(t) and lsu_xu_ex3_derat_multihit_err(t); -- DEMH: D-ERAT Multi-Hit + ex4_mcsr_d(10+14*t) <= ex3_tlb_multihit_err_q(t); -- TLBMH: TLB Multi-Hit + ex4_mcsr_d(11+14*t) <=(ex3_xuuc_val_q(t) and ex3_n_iepe_mchk_mcint_xuuc(t)) or -- IEPE: I-ERAT Parity Error + ex3_n_ieratre_par_mchk_mcint(t); + ex4_mcsr_d(12+14*t) <=(ex3_xu_val_q(t) and lsu_xu_ex3_derat_par_err(t)) or -- DEPE: D-ERAT Parity Error + ( ex3_n_deratre_par_mchk_mcint(t)); + ex4_mcsr_d(13+14*t) <= ex3_tlb_par_err_q(t); -- TLBPE: TLB Parity Error + + + ex5_mcsr_d(0+15*t) <= ex4_n_flush_pri(DMCHKn) and ex4_mcsr_q(0+14*t); -- DPOVR: Data Port Overrun + ex5_mcsr_d(1+15*t) <= ex4_n_flush_pri(DMCHKn) and ex4_n_ddmh_mchk_mcint(t); -- DDMH: Data Cache Directory MultiHit + ex5_mcsr_d(2+15*t) <= ex4_n_flush_pri(IMCHKn) and ex4_mcsr_q(1+14*t); -- TLBIVAXSR:TLBivax Snoop Reject + ex5_mcsr_d(3+15*t) <= ex4_n_flush_pri(IMCHKn) and ex4_mcsr_q(2+14*t); -- TLBLRUPE: TLB LRU Parity Error + ex5_mcsr_d(4+15*t) <= ex4_n_flush_pri(IMCHKn) and ex4_mcsr_q(3+14*t); -- IL2ECC: I$ L2 UC ECC Error + ex5_mcsr_d(5+15*t) <= ex4_n_flush_pri(DMCHKn) and ex4_mcsr_q(4+14*t); -- DL2ECC: D$ L2 UC ECC Error + ex5_mcsr_d(6+15*t) <= ex4_n_flush_pri(DMCHKn) and ex4_mcsr_q(5+14*t); -- DDPE: D$ Dir Parity Error + ex5_mcsr_d(7+15*t) <= ex4_np1_flush_pri(MCHKnp1) and ex4_mcsr_q(6+14*t); -- EXT: External Machine Check + ex5_mcsr_d(8+15*t) <= ex4_n_flush_pri(DMCHKn) and ex4_mcsr_q(7+14*t); -- DCPE: D$ Data Parity Error + ex5_mcsr_d(9+15*t) <= ex4_n_flush_pri(IMCHKn) and ex4_mcsr_q(8+14*t); -- IEMH: I-ERAT Multi-Hit + ex5_mcsr_d(10+15*t) <= ex4_n_flush_pri(DMCHKn) and ex4_mcsr_q(9+14*t); -- DEMH: D-ERAT Multi-Hit + ex5_mcsr_d(11+15*t) <= ex4_n_flush_pri(IMCHKn) and ex4_mcsr_q(10+14*t); -- TLBMH: TLB Multi-Hit + ex5_mcsr_d(12+15*t) <= ex4_n_flush_pri(IMCHKn) and(ex4_mcsr_q(11+14*t) or + ex4_n_ieratsx_par_mchk_mcint_q(t)); -- IEPE: I-ERAT Parity Error + ex5_mcsr_d(13+15*t) <= ex4_n_flush_pri(DMCHKn) and ex4_mcsr_q(12+14*t); -- DEPE: D-ERAT Parity Error + ex5_mcsr_d(14+15*t) <= ex4_n_flush_pri(IMCHKn) and ex4_mcsr_q(13+14*t); -- TLBPE: TLB Parity Error + + pc_err_mcsr(0+11*t) <= ex5_mcsr_act_q(t) and ex5_mcsr_q(0+15*t); -- DPOVR: Data Port Overrun + pc_err_mcsr(1+11*t) <= ex5_mcsr_act_q(t) and ex5_mcsr_q(2+15*t); -- TLBIVAXSR:TLBivax Snoop Reject + pc_err_mcsr(2+11*t) <= ex5_mcsr_act_q(t) and ex5_mcsr_q(3+15*t); -- TLBLRUPE: TLB LRU Parity Error + pc_err_mcsr(3+11*t) <= ex5_mcsr_act_q(t) and ex5_mcsr_q(7+15*t); -- EXT: External Machine Check + pc_err_mcsr(4+11*t) <= ex5_mcsr_act_q(t) and ex5_mcsr_q(9+15*t); -- IEMH: I-ERAT Multi-Hit + pc_err_mcsr(5+11*t) <= ex5_mcsr_act_q(t) and ex5_mcsr_q(10+15*t); -- DEMH: D-ERAT Multi-Hit + pc_err_mcsr(6+11*t) <= ex5_mcsr_act_q(t) and ex5_mcsr_q(11+15*t); -- TLBMH: TLB Multi-Hit + pc_err_mcsr(7+11*t) <= ex5_mcsr_act_q(t) and ex5_mcsr_q(12+15*t); -- IEPE: I-ERAT Parity Error + pc_err_mcsr(8+11*t) <= ex5_mcsr_act_q(t) and ex5_mcsr_q(13+15*t); -- DEPE: D-ERAT Parity Error + pc_err_mcsr(9+11*t) <= ex5_mcsr_act_q(t) and ex5_mcsr_q(14+15*t); -- TLBPE: TLB Parity Error + pc_err_mcsr(10+11*t) <= not ex5_mchk_int_en_q(t) and or_reduce(pc_err_mcsr(11*t to 11*t+9)); -- MCHK when machine checks are disabled. + pc_err_mcsr_summary_d(t) <= or_reduce(pc_err_mcsr_rpt(11*t to 11*t+9)); + + ex4_esr_mask(0) <= ex4_n_flush_pri(PROG0n) or ex4_n_flush_pri(PROG0An); + ex4_esr_mask(1) <= ex4_n_flush_pri(PROG1n); + ex4_esr_mask(2) <= ex4_np1_flush_pri_instr(TRAP); + ex4_esr_mask(3) <= ex4_n_flush_pri(ALIGNn) or ex4_n_flush_pri(DSTORn) or ex4_n_flush_pri(DTLBn) or ex4_n_flush_pri(DLRATn) or + ex4_n_flush_pri(PROG0n) or ex4_n_flush_pri(PROG1n) or ex4_n_flush_pri(PROG2n) or ex4_n_flush_pri(PROG3n); + ex4_esr_mask(4) <= ex4_n_flush_pri(ALIGNn) or ex4_n_flush_pri(DSTORn) or ex4_n_flush_pri(DTLBn) or ex4_n_flush_pri(DLRATn); + ex4_esr_mask(5) <= ex4_n_flush_pri(DSTORn); + ex4_esr_mask(6) <= ex4_n_flush_pri(DSTORn); + ex4_esr_mask(7) <= ex4_esr_mask(3); + ex4_esr_mask(8) <= ex4_n_flush_pri(PROG2n); + ex4_esr_mask(9) <= '0'; + ex4_esr_mask(10) <= ex4_n_flush_pri_ena(FPENA); + ex4_esr_mask(11) <= ex4_n_flush_pri(DSTORn); + ex4_esr_mask(12) <= ex4_n_flush_pri(DLRATn); + ex4_esr_mask(13) <= ex4_n_flush_pri(ISTORn) or ex4_n_flush_pri(DSTORn); + ex4_esr_mask(14) <= ex4_n_flush_pri(ISTORn) or ex4_n_flush_pri(DSTORn) or ex4_n_flush_pri(ILRATn) or ex4_n_flush_pri(DLRATn); + ex4_esr_mask(15) <= ex4_esr_mask(3) or ex4_n_flush_pri_unavail(VEC); + ex4_esr_mask(16) <= ex4_esr_mask(4); + + ex4_mmu_esr_val_d(t) <= ex3_tlb_inelig_q(t) or ex3_tlb_pt_fault_q(t) or ex3_tlb_miss_q(t); + + -- Force Instruction Type for AP/FP Enabled Interrupts + with ex4_n_flush_pri_ena select + ex4_axu_instr_type <= "001" when "01", + "100" when "10", + ex4_axu_instr_type_q when others; + + with ex4_mmu_esr_val_q(t) select + ex4_is_any_store(t) <= ex4_mmu_esr_st_q(t) when '1', + ex4_is_any_store_q(t) when others; + + + with ex4_mmu_esr_val_q(t) select + ex4_epid_instr(t) <= ex4_mmu_esr_epid_q(t) when '1', + ex4_epid_instr_q(t) when others; + + + ex4_esr_cond(DLK) <= ex4_n_flush_pri(DSTORn) and (ex4_n_dlk0_dstor_int_q(t) or ex4_n_dlk1_dstor_int_q(t)); + ex4_esr_cond(PT) <= ex4_mmu_esr_pt_q(t); + ex4_esr_cond(VF) <= ex4_n_flush_pri(DSTORn) and ex4_n_vf_dstor_int_q(t); + ex4_esr_cond(TLBI) <= ex4_tlb_inelig_q(t); + ex4_esr_cond(RW) <=(ex4_n_flush_pri(DSTORn) and ex4_n_rwaccess_dstor_int_q(t)) or + (ex4_n_flush_pri(ISTORn) and ex4_n_exaccess_istor_int_q(t)); + ex4_esr_cond(UCT) <= ex4_n_flush_pri(DSTORn) and ex4_n_uct_dstor_int_q(t); + + xu_cpl_esr_pri : entity work.xuq_cpl_pri(xuq_cpl_pri) + generic map (size => ex4_esr_cond'length) + port map( + cond => ex4_esr_cond, + pri => ex4_esr_pri); + + + ex5_esr_d(0+17*t) <= ex4_esr_mask(0); -- PIL: Illegal + ex5_esr_d(1+17*t) <= ex4_esr_mask(1); -- PPR: Privledged + ex5_esr_d(2+17*t) <= ex4_esr_mask(2) and ex4_np1_ptr_prog_int_q(t); -- PTR: Trap + ex5_esr_d(3+17*t) <= ex4_esr_mask(3) and ex4_axu_instr_type(2); -- FP: Floating Point + ex5_esr_d(4+17*t) <= ex4_esr_mask(4) and ex4_is_any_store(t) and not ex4_esr_pri(UCT); -- ST: Store + ex5_esr_d(5+17*t) <= ex4_esr_mask(5) and ex4_esr_pri(DLK) and ex4_n_dlk0_dstor_int_q(t); -- DLK0: + ex5_esr_d(6+17*t) <= ex4_esr_mask(6) and ex4_esr_pri(DLK) and ex4_n_dlk1_dstor_int_q(t); -- DLK1: + ex5_esr_d(7+17*t) <= ex4_esr_mask(7) and ex4_axu_instr_type(0); -- AP: Auxillary + ex5_esr_d(8+17*t) <= ex4_esr_mask(8); -- PUO: Unimplemented + ex5_esr_d(9+17*t) <= ex4_esr_mask(9); -- BO: Byte Ordering + ex5_esr_d(10+17*t) <= ex4_esr_mask(10) and ex5_axu_trap_pie_q(t); -- PIE: Imprecise + ex5_esr_d(11+17*t) <= ex4_esr_mask(11) and ex4_esr_pri(UCT); -- UCT: Unvailable Coprocessor Type + ex5_esr_d(12+17*t) <= ex4_esr_mask(12) and ex4_mmu_esr_data_q(t); -- DATA: Data Access + ex5_esr_d(13+17*t) <= ex4_esr_mask(13) and ex4_esr_pri(TLBI); -- TLBI: TLB Ineligible + ex5_esr_d(14+17*t) <= ex4_esr_mask(14) and ex4_esr_pri(PT); -- PT: Page Table + ex5_esr_d(15+17*t) <= ex4_esr_mask(15) and ex4_axu_instr_type(1); -- SPV: Vector + ex5_esr_d(16+17*t) <= ex4_esr_mask(16) and ex4_epid_instr(t); -- EPID: External PID + + ex5_dbsr_d(0+19*t) <= ex4_np1_ude_dbg_event_q(t); -- UDE: Unconditional Debug Event + ex5_dbsr_d(1+19*t) <= exx_np1_icmp_dbg_event(t); -- ICMP: Instr Complete (Must have MSR[DE]=1) + ex5_dbsr_d(2+19*t) <= ex4_dbsr_en_cond(1) and ex4_n_brt_dbg_cint_q(t); -- BRT: Branch Taken (Must have MSR[DE]=1) + ex5_dbsr_d(3+19*t) <= exx_np1_irpt_dbg_event(t); -- IRPT: Interrupt Taken + ex5_dbsr_d(4+19*t) <= ex4_dbsr_en_cond(1) and ex4_n_trap_dbg_cint_q(t); -- TRAP: Trap Taken + ex5_dbsr_d(5+19*t) <= ex4_dbsr_en_cond(0) and ex4_iac1_cmpr_q(t) and ex4_anyuc_val_q(t); -- IAC1: Instruction Address Compare + ex5_dbsr_d(6+19*t) <= ex4_dbsr_en_cond(0) and ex4_iac2_cmpr_q(t) and ex4_anyuc_val_q(t); -- IAC2: Instruction Address Compare + ex5_dbsr_d(7+19*t) <= ex4_dbsr_en_cond(0) and ex4_iac3_cmpr_q(t) and ex4_anyuc_val_q(t); -- IAC3: Instruction Address Compare + ex5_dbsr_d(8+19*t) <= ex4_dbsr_en_cond(0) and ex4_iac4_cmpr_q(t) and ex4_anyuc_val_q(t); -- IAC4: Instruction Address Compare + ex5_dbsr_d(9+19*t) <=(ex4_dbsr_en_cond(1) and ex4_dacr_cmpr_q(1)(t) and ex4_anyuc_val_q(t)) or -- DAC1R Read Data Address Compare + ex4_dac1r_cmpr_async_q(t); + ex5_dbsr_d(10+19*t) <= ex4_dbsr_en_cond(1) and ex4_dacw_cmpr_q(1)(t) and ex4_anyuc_val_q(t); -- DAC1W Write Data Address Compare + ex5_dbsr_d(11+19*t) <=(ex4_dbsr_en_cond(1) and ex4_dacr_cmpr_q(2)(t) and ex4_anyuc_val_q(t)) or -- DAC2R Read Data Address Compare + ex4_dac2r_cmpr_async_q(t); + ex5_dbsr_d(12+19*t) <= ex4_dbsr_en_cond(1) and ex4_dacw_cmpr_q(2)(t) and ex4_anyuc_val_q(t); -- DAC2W Write Data Address Compare + ex5_dbsr_d(13+19*t) <= ex4_dbsr_en_cond(1) and ex4_n_ret_dbg_cint_q(t); -- RET Return Debug Event + ex5_dbsr_d(14+19*t) <= ex4_dbsr_en_cond(1) and ex4_dacr_cmpr_q(3)(t) and ex4_anyuc_val_q(t); -- DAC3R Read Data Address Compare + ex5_dbsr_d(15+19*t) <= ex4_dbsr_en_cond(1) and ex4_dacw_cmpr_q(3)(t) and ex4_anyuc_val_q(t); -- DAC3W Write Data Address Compare + ex5_dbsr_d(16+19*t) <= ex4_dbsr_en_cond(1) and ex4_dacr_cmpr_q(4)(t) and ex4_anyuc_val_q(t); -- DAC4R Read Data Address Compare + ex5_dbsr_d(17+19*t) <= ex4_dbsr_en_cond(1) and ex4_dacw_cmpr_q(4)(t) and ex4_anyuc_val_q(t); -- DAC4W Write Data Address Compare + ex5_dbsr_d(18+19*t) <= ex4_dbsr_en_cond(0) and ex4_n_ivc_dbg_cint_q(t); -- IVC: Instruction Value Compare + + ex5_dbsr_ide_d(t) <=(ex4_dac1r_cmpr_async_q(t) or ex4_dac2r_cmpr_async_q(t)) and not ex5_in_ucode_q(t); + cpl_spr_ex5_dbsr_ide(t) <= ex5_dbsr_ide_q(t); + + + -- restart = flush to IU0 + -- Restart must default to be on in all cases except when in ucode + -- Restart when an interrupt occurs in all cases + -- Restart @ ucode end + -- Restart if a flush to ucode while in ucode occurs (unaligned ld update forms) + ex4_ucode_restart(t) <= not ex4_uc_cia_val(t) or + (ex4_np1_flush_pri(Fnp1) and ex4_ucode_end(t)) or + ex4_n_flush_pri(F2Un) or + ex5_is_any_int(t); + with ex4_flush_act(t) select + ex5_ucode_restart_d(t) <= ex4_ucode_restart(t) when '1', + (ex5_ucode_restart_q(t) or ex5_is_any_int(t)) when others; + + ex5_flush_2ucode_d(t) <= ex4_n_flush_pri(F2Un); + + ex5_ram_interrupt(t) <= ram_ip_q(t) and ex5_is_any_int(t); + ex5_ram_issue_d(t) <= ram_ip_q(t) and ex5_late_flush_q(0)(t); + + -- Mux correct instruction type for ESR + with s2'((ex3_xu_val_q(t) or ex3_ucode_val_q(t)) & ex3_axu_val_q(t)) select + ex4_axu_instr_type_d <= dec_cpl_ex3_axu_instr_type when "10", + ex3_axu_instr_type_q(3*t to 3*t+2) when "01", + "000" when others; + + + + -- Special Handling for Trap Events + -- with ex4_np1_flush_pri_instr(TRAP) select + -- ex4_nia_muxed <= ex4_cia when '1', + -- ex4_nia when others; + ex4_cia_sel <= fanout((not ex4_n_flush(t) and ex4_np1_ptr_prog_int_q(t)),eff_ifar); + ex4_nia_sel <= fanout(( ex4_n_flush(t) or not ex4_np1_ptr_prog_int_q(t)),eff_ifar); + + ex5_dbell_taken_d(t) <= ex4_np1_flush_pri(DBELLnp1); + ex5_cdbell_taken_d(t) <= ex4_np1_flush_pri(CDBELLnp1); + ex5_gdbell_taken_d(t) <= ex4_np1_flush_pri(GDBELLnp1); + ex5_gcdbell_taken_d(t) <= ex4_np1_flush_pri(GCDBELLnp1); + ex5_gmcdbell_taken_d(t) <= ex4_np1_flush_pri(GDBMCHKnp1); + + xu_iu_iu0_flush_ifar(eff_ifar*t to eff_ifar*(t+1)-1) <= flush_ifar; + ex4_cia_p1_out(eff_ifar*t to eff_ifar*(t+1)-1) <= ex4_cia_p1; + cpl_spr_ex5_nia(eff_ifar*t to eff_ifar*(t+1)-1) <= not ex5_nia_b_q(eff_ifar*t to eff_ifar*(t+1)-1); + spr_iar(eff_ifar*t to eff_ifar*(t+1)-1) <= ex4_cia when ram_mode_q(t)='1' else ex4_cia_p1; + + + ex3_n_fu_rfpe_det(t) <= not (ex3_flush_q(t) or ex3_flush(t)) and fu_xu_ex3_regfile_err_det(t); + + ex4_n_fu_rfpe_flush_d(t) <= ex3_n_fu_rfpe_det(t); + ex4_n_xu_rfpe_flush_d(t) <= (ex3_xuuc_val(t) or ex3_dep_val(t)) and gpr_cpl_ex3_regfile_err_det; + + ex4_n_fu_rfpe_flush(t) <= ex4_n_flush_pri(FPEn) and ex4_n_fu_rfpe_flush_q(t); + ex4_n_xu_rfpe_flush(t) <= ex4_n_flush_pri(FPEn) and ex4_n_xu_rfpe_flush_q(t); + + ex4_barrier_flush(t) <= ex4_n_flush_pri(FwBSn); + + cia_out_gen_32 : if eff_ifar /= 62 generate + ex4_cia_out(t) <= (0 to 62-eff_ifar=>'0') & ex4_cia; + end generate; + cia_out_gen_64 : if eff_ifar = 62 generate + ex4_cia_out(t) <= ex4_cia; + end generate; + + ------------------------------------------------------------------------------- + -- Replicated Latches + ------------------------------------------------------------------------------- + ex4_cia_b_latch : tri_rlmreg_p + generic map(width => ex4_cia_b_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, + vd => vdd, + gd => gnd, + act => ex3_cia_act(t), + forcee => bcfg_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => bcfg_sl_thold_0_b, + sg => sg_0, + scin => siv_bcfg(ex4_cia_b_offset_bcfg + ex4_cia_b_q'length*t to ex4_cia_b_offset_bcfg + ex4_cia_b_q'length*(t+1)-1), + scout => sov_bcfg(ex4_cia_b_offset_bcfg + ex4_cia_b_q'length*t to ex4_cia_b_offset_bcfg + ex4_cia_b_q'length*(t+1)-1), + din => ex4_cia_b_d, + dout => ex4_cia_b_q); + ex4_uc_cia_latch : tri_rlmreg_p + generic map (width => ex4_uc_cia_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => ex3_uc_cia_act(t), + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_uc_cia_offset + ex4_uc_cia_q'length*t to ex4_uc_cia_offset + ex4_uc_cia_q'length*(t+1)-1), + scout => sov(ex4_uc_cia_offset + ex4_uc_cia_q'length*t to ex4_uc_cia_offset + ex4_uc_cia_q'length*(t+1)-1), + din => ex4_uc_cia_d, + dout => ex4_uc_cia_q); + ex4_axu_instr_type_latch : tri_rlmreg_p + generic map (width => ex4_axu_instr_type_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex3_esr_bit_act(t), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_axu_instr_type_offset + ex4_axu_instr_type_q'length*t to ex4_axu_instr_type_offset + ex4_axu_instr_type_q'length*(t+1)-1), + scout => sov(ex4_axu_instr_type_offset + ex4_axu_instr_type_q'length*t to ex4_axu_instr_type_offset + ex4_axu_instr_type_q'length*(t+1)-1), + din => ex4_axu_instr_type_d, + dout => ex4_axu_instr_type_q); + ex4_is_any_store_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex3_esr_bit_act(t), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_is_any_store_offset+t), + scout => sov(ex4_is_any_store_offset+t), + din => dec_cpl_ex3_is_any_store, + dout => ex4_is_any_store_q(t)); + ex4_epid_instr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex3_esr_bit_act(t), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_epid_instr_offset+t), + scout => sov(ex4_epid_instr_offset+t), + din => ex3_epid_instr_q, + dout => ex4_epid_instr_q(t)); + ex5_mem_attr_latch : tri_rlmreg_p + generic map (width => ex5_mem_attr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => ex4_mem_attr_act(t), + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_mem_attr_offset + ex5_mem_attr_q'length*t to ex5_mem_attr_offset + ex5_mem_attr_q'length*(t+1)-1), + scout => sov(ex5_mem_attr_offset + ex5_mem_attr_q'length*t to ex5_mem_attr_offset + ex5_mem_attr_q'length*(t+1)-1), + din => ex4_mem_attr_q, + dout => ex5_mem_attr_q); + ex5_flush_2ucode_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_flush_act(t), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_flush_2ucode_offset+t), + scout => sov(ex5_flush_2ucode_offset+t), + din => ex5_flush_2ucode_d(t), + dout => ex5_flush_2ucode_q(t)); + ex5_ucode_restart_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_ucode_restart_offset+t), + scout => sov(ex5_ucode_restart_offset+t), + din => ex5_ucode_restart_d(t), + dout => ex5_ucode_restart_q(t)); + ex5_mem_attr_le_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_flush_act(t), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_mem_attr_le_offset+t), + scout => sov(ex5_mem_attr_le_offset+t), + din => ex5_mem_attr_le_d(t), + dout => ex5_mem_attr_le_q(t)); + ex5_ivo_sel_latch : tri_rlmreg_p + generic map (width => ex5_ivo_sel_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_flush_inf_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_ivo_sel_offset + ex5_ivo_sel_q'length*t to ex5_ivo_sel_offset + ex5_ivo_sel_q'length*(t+1)-1), + scout => sov(ex5_ivo_sel_offset + ex5_ivo_sel_q'length*t to ex5_ivo_sel_offset + ex5_ivo_sel_q'length*(t+1)-1), + din => ex4_ivo_sel, + dout => ex5_ivo_sel_q); + ex5_nia_b_latch : entity tri.tri_aoi22_nlats_wlcb(tri_aoi22_nlats_wlcb) + generic map (width => eff_ifar, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_nia_act(t), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_nia_b_offset + eff_ifar*t to ex5_nia_b_offset + eff_ifar*(t+1)-1), + scout => sov(ex5_nia_b_offset + eff_ifar*t to ex5_nia_b_offset + eff_ifar*(t+1)-1), + A1 => ex4_cia, + A2 => ex4_cia_sel, + B1 => ex4_nia, + B2 => ex4_nia_sel, + QB => ex5_nia_b_q(eff_ifar*t to eff_ifar*(t+1)-1)); + ex5_flush_pri_dbg_latch : tri_regk + generic map (width => ex5_flush_pri_dbg_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex4_flush_pri, + dout => ex5_flush_pri_dbg_q); + exx_instr_async_block_latch : tri_rlmreg_p + generic map (width => exx_instr_async_block_q(t)'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(exx_instr_async_block_offset+exx_instr_async_block_q(t)'length*t to exx_instr_async_block_offset + exx_instr_async_block_q(t)'length*(t+1)-1), + scout => sov(exx_instr_async_block_offset+exx_instr_async_block_q(t)'length*t to exx_instr_async_block_offset + exx_instr_async_block_q(t)'length*(t+1)-1), + din => exx_instr_async_block_d(t), + dout => exx_instr_async_block_q(t)); + ex5_esr_latch : tri_rlmreg_p + generic map (width => ex5_esr_q'length/threads, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_esr_act(t), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_esr_offset+(ex5_esr_q'length*t)/threads to ex5_esr_offset+((ex5_esr_q'length*(t+1))/threads)-1), + scout => sov(ex5_esr_offset+(ex5_esr_q'length*t)/threads to ex5_esr_offset+((ex5_esr_q'length*(t+1))/threads)-1), + din => ex5_esr_d((ex5_esr_q'length*t)/threads to ((ex5_esr_q'length*(t+1))/threads)-1), + dout => ex5_esr_q((ex5_esr_q'length*t)/threads to ((ex5_esr_q'length*(t+1))/threads)-1)); + ex5_dbsr_latch : tri_rlmreg_p + generic map (width => ex5_dbsr_q'length/threads, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_dbsr_act(t), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_dbsr_offset+(ex5_dbsr_q'length*t)/threads to ex5_dbsr_offset+((ex5_dbsr_q'length*(t+1))/threads)-1), + scout => sov(ex5_dbsr_offset+(ex5_dbsr_q'length*t)/threads to ex5_dbsr_offset+((ex5_dbsr_q'length*(t+1))/threads)-1), + din => ex5_dbsr_d((ex5_dbsr_q'length*t)/threads to ((ex5_dbsr_q'length*(t+1))/threads)-1), + dout => ex5_dbsr_q((ex5_dbsr_q'length*t)/threads to ((ex5_dbsr_q'length*(t+1))/threads)-1)); + ex5_mcsr_latch : tri_rlmreg_p + generic map (width => ex5_mcsr_q'length/threads, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_mcsr_act(t), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_mcsr_offset+(ex5_mcsr_q'length*t)/threads to ex5_mcsr_offset+((ex5_mcsr_q'length*(t+1))/threads)-1), + scout => sov(ex5_mcsr_offset+(ex5_mcsr_q'length*t)/threads to ex5_mcsr_offset+((ex5_mcsr_q'length*(t+1))/threads)-1), + din => ex5_mcsr_d((ex5_mcsr_q'length*t)/threads to ((ex5_mcsr_q'length*(t+1))/threads)-1), + dout => ex5_mcsr_q((ex5_mcsr_q'length*t)/threads to ((ex5_mcsr_q'length*(t+1))/threads)-1)); + dbg_flushcond_latch : tri_regk + generic map (width => dbg_flushcond_q(t)'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => dbg_flushcond_d(t), + dout => dbg_flushcond_q(t)); + ex5_np1_icmp_dbg_cint_latch : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_np1_icmp_dbg_cint_offset+t to ex5_np1_icmp_dbg_cint_offset+t), + scout => sov(ex5_np1_icmp_dbg_cint_offset+t to ex5_np1_icmp_dbg_cint_offset+t), + din(0) => ex5_np1_icmp_dbg_cint_d(t), + dout(0) => ex5_np1_icmp_dbg_cint_q(t)); + ex5_np1_icmp_dbg_event_latch : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_np1_icmp_dbg_event_offset+t to ex5_np1_icmp_dbg_event_offset+t), + scout => sov(ex5_np1_icmp_dbg_event_offset+t to ex5_np1_icmp_dbg_event_offset+t), + din(0) => ex5_np1_icmp_dbg_event_d(t), + dout(0) => ex5_np1_icmp_dbg_event_q(t)); + + ------------------------------------------------------------------------------- + -- Performance Monitor + ------------------------------------------------------------------------------- + ex5_perf_itlb_d(t) <= ex4_n_flush_pri(ITLBn); + ex5_perf_dtlb_d(t) <= ex4_n_flush_pri(DTLBn); + + xu_mm_ex5_perf_itlb(t) <= ex5_perf_itlb_q(t); + xu_mm_ex5_perf_dtlb(t) <= ex5_perf_dtlb_q(t); + + ex5_perf_event_d(00+14*t) <= ex4_instr_cpl(t); -- PPE Commit + ex5_perf_event_d(01+14*t) <= ex4_xuuc_val(t); -- Integer Commit + ex5_perf_event_d(02+14*t) <= ex4_np1_flush_pri(Fnp1) and ex4_ucode_end(t); -- uCode Commit + ex5_perf_event_d(03+14*t) <= ex2_br_flush(t) or ex4_n_flush(t) or ex4_np1_flush(t); -- Any Flush + ex5_perf_event_d(04+14*t) <= ex4_xu_val(t) and ex4_perf_event_q(0); -- Branch Commit + ex5_perf_event_d(05+14*t) <= ex4_anyuc_val(t) and ex4_perf_event_q(1); -- Branch Mispredict Commit + ex5_perf_event_d(06+14*t) <= ex4_anyuc_val(t) and ex4_perf_event_q(2); -- Branch Taken Commit + ex5_perf_event_d(07+14*t) <= ex4_n_flush_pri(BTAn); -- Branch TA Mispredict Commit + ex5_perf_event_d(08+14*t) <= ex4_anyuc_val(t) and ex4_perf_event_q(3); -- Mult/Div collision + ex5_perf_event_d(09+14*t) <= (ext_int_asserted(t) or ex5_perf_event_q(09+14*t)) and not ex5_ivo_sel_q(4); -- External Interrupt Pending + ex5_perf_event_d(10+14*t) <= (crit_int_asserted(t) or ex5_perf_event_q(10+14*t)) and not ex5_ivo_sel_q(0); -- Critical External Interrupt Pending + ex5_perf_event_d(11+14*t) <= (perf_int_asserted(t) or ex5_perf_event_q(11+14*t)) and not ex5_ivo_sel_q(25);-- Performance Mon Interrupt Pending + ex5_perf_event_d(12+14*t) <= ex4_anyuc_val(t) and ex4_n_ivc_dbg_match_q(t); -- Opcode Match + ex5_perf_event_d(13+14*t) <= ex4_instr_cpl(t) and not or_reduce(spr_ccr0_we); -- Concurrent Run Instructions + + cpl_perf_tx_events(00+19*t)<= ex5_perf_event_q(00+14*t); -- PPE Commit + cpl_perf_tx_events(01+19*t)<= ex5_perf_event_q(01+14*t); -- Integer Commit + cpl_perf_tx_events(02+19*t)<= ex5_perf_event_q(02+14*t); -- uCode Commit + cpl_perf_tx_events(03+19*t)<= ex5_perf_event_q(03+14*t); -- Any Flush + cpl_perf_tx_events(04+19*t)<= ex5_perf_event_q(04+14*t); -- Branch Commit + cpl_perf_tx_events(05+19*t)<= ex5_perf_event_q(05+14*t); -- Branch Mispredict Commit + cpl_perf_tx_events(06+19*t)<= ex5_perf_event_q(06+14*t); -- Branch Taken Commit + cpl_perf_tx_events(07+19*t)<= ex5_perf_event_q(07+14*t); -- Branch TA Mispredict Commit + cpl_perf_tx_events(08+19*t)<= ex5_perf_event_q(08+14*t); -- Mult/Div collision + cpl_perf_tx_events(09+19*t)<= ex5_perf_event_q(09+14*t); -- External Interrupt Pending + cpl_perf_tx_events(10+19*t)<= ex5_perf_event_q(10+14*t); -- Critical External Interrupt Pending + cpl_perf_tx_events(11+19*t)<= ex5_perf_event_q(11+14*t); -- Performance Mon Interrupt Pending + cpl_perf_tx_events(12+19*t)<= ex5_perf_event_q(12+14*t); -- Opcode Match + cpl_perf_tx_events(13+19*t)<= ex5_perf_event_q(13+14*t); -- Concurrent Run Instructions + cpl_perf_tx_events(14+19*t)<= any_ext_perf_int; -- External, Critical, Perf Interrupts Taken (any thread) + cpl_perf_tx_events(15+19*t)<= ex5_ivo_sel_q(4); -- External Interrupt Taken + cpl_perf_tx_events(16+19*t)<= ex5_ivo_sel_q(0); -- Critical External Interrupt Taken + cpl_perf_tx_events(17+19*t)<= ex5_ivo_sel_q(25); -- Performance Mon Interrupt Taken + cpl_perf_tx_events(18+19*t)<= ex5_ivo_sel_q(17) or ex5_ivo_sel_q(18); -- Processor Doorbell or Critical Doorbell Taken + + any_ext_perf_ints(t) <= ex5_ivo_sel_q(4) or ex5_ivo_sel_q(0) or ex5_ivo_sel_q(25); + + ext_int_asserted(t) <= spr_cpl_async_int(0+3*t) and not spr_cpl_async_int_q(0+3*t); + crit_int_asserted(t) <= spr_cpl_async_int(1+3*t) and not spr_cpl_async_int_q(1+3*t); + perf_int_asserted(t) <= spr_cpl_async_int(2+3*t) and not spr_cpl_async_int_q(2+3*t); + + mark_unused(ex4_esr_pri(VF)); + mark_unused(ex4_esr_pri(RW)); + + -- Ucode Completing Type is FP Not LD/ST + ex5_axu_ucode_val_opc(t) <= ex5_ucode_end_dbg_q(t) and ex4_axu_instr_type_q(2) and not ex5_mem_attr_val_q(t); + + ex5_axu_val_dbg_opc(t) <= ex5_axu_val_dbg_q(t) or ex5_axu_ucode_val_opc(t); + ex5_xu_val_dbg_opc(t) <= ex5_xu_val_q(t) and not ex5_axu_ucode_val_opc(t); + + +end generate; + + + +any_ext_perf_int <= or_reduce(any_ext_perf_ints); + +------------------------------------------------------------------------------- +-- Branch Sub-Unit +------------------------------------------------------------------------------- +xu_cpl_br : entity work.xuq_cpl_br(xuq_cpl_br) +generic map( + expand_type => expand_type, + threads => threads, + eff_ifar => eff_ifar, + uc_ifar => uc_ifar, + regsize => regsize) +port map( + nclk => nclk, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc, + mpw1_dc_b => mpw1_dc_b, + mpw2_dc_b => mpw2_dc_b, + func_sl_thold_0_b => func_sl_thold_0_b, + func_sl_force => func_sl_force, + sg_0 => sg_0, + scan_in => siv_3(0), + scan_out => sov_3(0), + rf1_act => exx_act(0), + ex1_act => exx_act(1), + rf1_tid => rf1_tid_q, + ex1_tid => ex1_xu_val_q, + ex1_xu_val => ex1_xu_val, + dec_cpl_rf1_ifar => dec_cpl_rf1_ifar, + ex1_xu_ifar => ex1_xu_ifar, + dec_cpl_rf1_pred_taken_cnt => dec_cpl_rf1_pred_taken_cnt, + dec_cpl_rf1_instr => dec_cpl_rf1_instr, + byp_cpl_ex1_cr_bit => byp_cpl_ex1_cr_bit, + spr_lr => spr_lr, + spr_ctr => spr_ctr, + ex2_br_flush => ex2_br_flush, + ex2_br_flush_ifar => ex2_br_flush_ifar, + ex1_branch => ex1_branch, + ex1_br_mispred => ex1_br_mispred, + ex1_br_taken => ex1_br_taken, + ex1_br_update => ex1_br_update, + ex1_is_bcctr => open, + ex1_is_bclr => ex1_is_bclr, + ex1_lr_update => ex1_lr_update, + ex1_ctr_dec_update => ex1_ctr_dec_update, + ex1_instr => ex1_instr, + spr_msr_cm => msr_cm_q, + br_debug => br_debug, + vdd => vdd, + gnd => gnd +); + +------------------------------------------------------------------------------- +-- SPR Sub-Unit +------------------------------------------------------------------------------- +xu_cpl_spr : entity work.xuq_cpl_spr(xuq_cpl_spr) +generic map( + hvmode => hvmode, + a2mode => a2mode, + expand_type => expand_type, + threads => threads, + regsize => regsize, + eff_ifar => eff_ifar) +port map( + nclk => nclk, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc, + mpw1_dc_b => mpw1_dc_b, + mpw2_dc_b => mpw2_dc_b, + dcfg_sl_force => dcfg_sl_force, + dcfg_sl_thold_0_b => dcfg_sl_thold_0_b, + func_sl_force => func_sl_force, + func_sl_thold_0_b => func_sl_thold_0_b, + func_nsl_force => func_nsl_force, + func_nsl_thold_0_b => func_nsl_thold_0_b, + sg_0 => sg_0, + scan_in => siv_3(1), + scan_out => sov_3(1), + dcfg_scan_in => siv_dcfg(0), + dcfg_scan_out => sov_dcfg(0), + spr_bit_act => spr_bit_act_q, + exx_act => exx_act(1 to 4), + ex1_instr => ex1_instr(11 to 20), + ex2_tid => ex2_xu_val_q, + ex2_ifar => ex2_ifar, + ex1_is_mfspr => ex1_is_mfspr_q, + ex1_is_mtspr => ex1_is_mtspr_q, + ex4_lr_update => ex4_lr_update_q, + ex4_ctr_dec_update => ex4_ctr_dec_update_q, + ex5_val => ex5_xu_val_q, + ex5_spr_wd => ex5_rt_q, + ex5_cia_p1 => ex5_cia_p1, + ex2_mtiar => ex2_mtiar, + cpl_byp_ex3_spr_rt => cpl_byp_ex3_spr_rt, + ex3_iac1_cmpr => ex3_iac1_cmpr, + ex3_iac2_cmpr => ex3_iac2_cmpr, + ex3_iac3_cmpr => ex3_iac3_cmpr, + ex3_iac4_cmpr => ex3_iac4_cmpr, + spr_cpl_iac1_en => spr_cpl_iac1_en, + spr_cpl_iac2_en => spr_cpl_iac2_en, + spr_cpl_iac3_en => spr_cpl_iac3_en, + spr_cpl_iac4_en => spr_cpl_iac4_en, + spr_dbcr1_iac12m => spr_dbcr1_iac12m, + spr_dbcr1_iac34m => spr_dbcr1_iac34m, + spr_iar => spr_iar, + spr_msr_cm => msr_cm_q, + spr_givpr => spr_givpr, + spr_ivpr => spr_ivpr, + spr_ctr => spr_ctr, + spr_lr => spr_lr, + spr_xucr3_cm_hold_dly => spr_xucr3_cm_hold_dly, + spr_xucr3_stop_dly => spr_xucr3_stop_dly, + spr_xucr3_hold0_dly => spr_xucr3_hold0_dly, + spr_xucr3_hold1_dly => spr_xucr3_hold1_dly, + spr_xucr3_csi_dly => spr_xucr3_csi_dly, + spr_xucr3_int_dly => spr_xucr3_int_dly, + spr_xucr3_asyncblk_dly => spr_xucr3_asyncblk_dly, + spr_xucr3_flush_dly => spr_xucr3_flush_dly, + spr_xucr4_div_bar_dis => spr_xucr4_div_bar_dis, + spr_xucr4_lsu_bar_dis => spr_xucr4_lsu_bar_dis, + spr_xucr4_barr_dly => spr_xucr4_barr_dly, + spr_xucr4_div_barr_thres => spr_xucr4_div_barr_thres, + spr_xucr4_mddmh => spr_xucr4_mddmh, + spr_xucr4_mmu_mchk => spr_xucr4_mmu_mchk_int, + vdd => vdd, + gnd => gnd +); + +------------------------------------------------------------------------------- +-- Error Macros +------------------------------------------------------------------------------- +xu_cpl_sprg_ue_err_rpt : entity tri.tri_direct_err_rpt(tri_direct_err_rpt) +generic map(width => threads, expand_type => expand_type) +port map ( vd => vdd, gd => gnd, + err_in => ex5_n_flush_sprg_ue_flush_q, + err_out => xu_pc_err_sprg_ue); + +xu_cpl_err_debug_rpt : entity tri.tri_direct_err_rpt(tri_direct_err_rpt) +generic map (width => threads, expand_type => expand_type) +port map (vd => vdd, gd => gnd, + err_in => ex5_ext_dbg_err_q, + err_out => xu_pc_err_debug_event); + +xu_cpl_err_attn_rpt : entity tri.tri_direct_err_rpt(tri_direct_err_rpt) +generic map (width => threads, expand_type => expand_type) +port map (vd => vdd, gd => gnd, + err_in => ex5_is_attn_q, + err_out => xu_pc_err_attention_instr); + +xu_cpl_err_nia_rpt : entity tri.tri_direct_err_rpt(tri_direct_err_rpt) +generic map (width => threads, expand_type => expand_type) +port map (vd => vdd, gd => gnd, + err_in => ex5_err_nia_miscmpr_q, + err_out => xu_pc_err_nia_miscmpr); + + +ex6_mcsr_act_d <= or_reduce(ex5_mcsr_act_q); +ex5_mcsr_act <= ex6_mcsr_act_d or ex6_mcsr_act_q; + +bcfg_lcbnd: entity tri.tri_lcbnd +generic map (expand_type => expand_type ) +port map(act => ex5_mcsr_act, + vd => vdd, + gd => gnd, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + nclk => nclk, + forcee => bcfg_slp_sl_force, + sg => sg_0, + thold_b => bcfg_slp_sl_thold_0_b, + d1clk => mcsr_bcfg_slp_sl_d1clk, + d2clk => mcsr_bcfg_slp_sl_d2clk, + lclk => mcsr_bcfg_slp_sl_lclk); + +bcfg_lcbs: tri_lcbs +generic map (expand_type => expand_type ) +port map(vd => vdd, + gd => gnd, + delay_lclkr => delay_lclkr_dc, + nclk => nclk, + forcee => so_force, + thold_b => bcfg_so_thold_0_b, + dclk => bcfg_so_d2clk, + lclk => bcfg_so_lclk); + +xu_cpl_err_mcsr_rpt : entity tri.tri_err_rpt +generic map (width => pc_err_mcsr'length, mask_reset_value => (pc_err_mcsr'range=>'0'), inline => false, expand_type => expand_type) +port map (vd => vdd, gd => gnd, + err_d1clk => mcsr_bcfg_slp_sl_d1clk, + err_d2clk => mcsr_bcfg_slp_sl_d2clk, + err_lclk => mcsr_bcfg_slp_sl_lclk, + err_scan_in => siv_bcfg(mcsr_rpt_offset_bcfg to mcsr_rpt_offset_bcfg + pc_err_mcsr'length-1), + err_scan_out => sov_bcfg(mcsr_rpt_offset_bcfg to mcsr_rpt_offset_bcfg + pc_err_mcsr'length-1), + mode_dclk => bcfg_so_d2clk, + mode_lclk => bcfg_so_lclk, + mode_scan_in => siv_bcfg(mcsr_rpt2_offset_bcfg to mcsr_rpt2_offset_bcfg + pc_err_mcsr'length-1), + mode_scan_out => sov_bcfg(mcsr_rpt2_offset_bcfg to mcsr_rpt2_offset_bcfg + pc_err_mcsr'length-1), + err_in => pc_err_mcsr, + err_out => pc_err_mcsr_rpt); + + pc_err_mcsr_rpt_d <= or_reduce_t(pc_err_mcsr_rpt,threads); + + xu_pc_err_mcsr_summary <= pc_err_mcsr_summary_q; + xu_pc_err_ditc_overrun <= pc_err_mcsr_rpt_q(0); + xu_pc_err_local_snoop_reject <= pc_err_mcsr_rpt_q(1); + xu_pc_err_tlb_lru_parity <= pc_err_mcsr_rpt_q(2); + xu_pc_err_ext_mchk <= pc_err_mcsr_rpt_q(3); + xu_pc_err_ierat_multihit <= pc_err_mcsr_rpt_q(4); + xu_pc_err_derat_multihit <= pc_err_mcsr_rpt_q(5); + xu_pc_err_tlb_multihit <= pc_err_mcsr_rpt_q(6); + xu_pc_err_ierat_parity <= pc_err_mcsr_rpt_q(7); + xu_pc_err_derat_parity <= pc_err_mcsr_rpt_q(8); + xu_pc_err_tlb_parity <= pc_err_mcsr_rpt_q(9); + xu_pc_err_mchk_disabled <= pc_err_mcsr_rpt_q(10); + + +ex5_cm_fctr : entity work.xuq_cpl_fctr(xuq_cpl_fctr) +generic map (threads => threads, expand_type => expand_type, passthru => 1, clockgate => 0) +port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_cm_hold_cond_offset), + scout => sov(ex5_cm_hold_cond_offset), + delay => spr_xucr3_cm_hold_dly, + din => ex5_cm_hold_cond, + dout => exx_cm_hold); + +------------------------------------------------------------------------------- +-- Block Conditions +------------------------------------------------------------------------------- +ex3_async_int_block_fctr : entity work.xuq_cpl_fctr(xuq_cpl_fctr) +generic map (threads => threads, expand_type => expand_type, passthru => 1) +port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_async_int_block_cond_offset), + scout => sov(ex3_async_int_block_cond_offset), + delay => spr_xucr3_asyncblk_dly, + din => ex3_async_int_block_cond, + dout => ex3_async_int_block_d); + +ex3_base_int_block_fctr : entity work.xuq_cpl_fctr(xuq_cpl_fctr) +generic map (threads => threads, expand_type => expand_type, passthru => 1, clockgate => 0) +port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_base_int_block_offset), + scout => sov(ex3_base_int_block_offset), + delay => spr_xucr3_int_dly, + din => ex3_base_int_block_cond, + dout => ex3_base_int_block); + +ex3_mchk_int_block_fctr : entity work.xuq_cpl_fctr(xuq_cpl_fctr) +generic map (threads => threads, expand_type => expand_type, passthru => 1, clockgate => 0) +port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_mchk_int_block_offset), + scout => sov(ex3_mchk_int_block_offset), + delay => spr_xucr3_int_dly, + din => ex3_mchk_int_block_cond, + dout => ex3_mchk_int_block); + +------------------------------------------------------------------------------- +-- Multi-Cycle Flushes +------------------------------------------------------------------------------- +exx_thread_stop_mcflush_fctr : entity work.xuq_cpl_fctr(xuq_cpl_fctr) +generic map (threads => threads, expand_type => expand_type, passthru => 1) +port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(exx_thread_stop_mcflush_offset), + scout => sov(exx_thread_stop_mcflush_offset), + delay => spr_xucr3_stop_dly, + din => ex4_thread_stop_q, + dout => exx_thread_stop_mcflush); + +exx_csi_mcflush_fctr : entity work.xuq_cpl_fctr(xuq_cpl_fctr) +generic map (threads => threads, expand_type => expand_type, passthru => 1) +port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(exx_csi_mcflush_offset), + scout => sov(exx_csi_mcflush_offset), + delay => spr_xucr3_csi_dly, + din => ex5_csi, + dout => exx_csi_mcflush); + +exx_lateflush_mcflush_fctr : entity work.xuq_cpl_fctr(xuq_cpl_fctr) +generic map (threads => threads, expand_type => expand_type, passthru => 0) +port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(exx_lateflush_mcflush_offset), + scout => sov(exx_lateflush_mcflush_offset), + delay => spr_xucr3_flush_dly, + din => ex4_late_flush, + dout => exx_lateflush_mcflush); + +exx_hold0_mcflush_fctr : entity work.xuq_cpl_fctr(xuq_cpl_fctr) +generic map (threads => threads, expand_type => expand_type, passthru => 1) +port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(exx_hold0_mcflush_offset), + scout => sov(exx_hold0_mcflush_offset), + delay => spr_xucr3_hold0_dly, + din => hold_state_0, + dout => exx_hold0_mcflush); + +exx_hold1_mcflush_fctr : entity work.xuq_cpl_fctr(xuq_cpl_fctr) +generic map (threads => threads, expand_type => expand_type, passthru => 1) +port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(exx_hold1_mcflush_offset), + scout => sov(exx_hold1_mcflush_offset), + delay => spr_xucr3_hold1_dly, + din => hold_state_1, + dout => exx_hold1_mcflush); + +exx_barr_mcflush_fctr : entity work.xuq_cpl_fctr(xuq_cpl_fctr) +generic map (threads => threads, expand_type => expand_type, passthru => 0) +port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(exx_barr_mcflush_offset), + scout => sov(exx_barr_mcflush_offset), + delay => spr_xucr4_barr_dly, + din => ex4_barrier_flush, + dout => exx_barr_mcflush); + + +exx_multi_flush_d <= exx_thread_stop_mcflush or + exx_hold0_mcflush or + exx_hold1_mcflush or + exx_barr_mcflush or + exx_csi_mcflush; + +exx_multi_flush <= exx_lateflush_mcflush or + exx_multi_flush_q; + + +------------------------------------------------------------------------------- +-- Flush Pipe +------------------------------------------------------------------------------- +xu_iu_ex5_ppc_cpl <= ex5_instr_cpl_q; + +iu_flush <= ex2_br_flush or ex5_late_flush_q(0); +xu_iu_flush <= iu_flush; + +ex4_late_flush <= ex4_np1_flush or ex4_n_flush; + +ex5_late_flush_repwr : for r in 0 to ifar_repwr-1 generate + ex5_late_flush_d(r) <= ex4_np1_flush or ex4_n_flush or exx_multi_flush or hold_state_1; +end generate; + +exx_flush_inf_act <= clkg_ctl_q or or_reduce(any_flush or is2_flush_q); +ex4_flush_inf_act <= clkg_ctl_q or or_reduce(ex4_flush or ex5_flush_q); + +any_flush <= ex2_br_flush or ex4_np1_flush or ex4_n_flush or exx_multi_flush or hold_state_1; +is2_flush <= ex2_br_flush or ex4_np1_flush or ex4_n_flush or exx_multi_flush or hold_state_1; +rf0_flush <= ex2_br_flush or ex4_np1_flush or ex4_n_flush or exx_multi_flush or hold_state_1; +rf1_flush <= ex2_br_flush or ex4_np1_flush or ex4_n_flush or exx_multi_flush or hold_state_1; +ex1_flush <= ex2_br_flush or ex4_np1_flush or ex4_n_flush or exx_multi_flush or hold_state_1; +ex2_flush <= ex4_np1_flush or ex4_n_flush or exx_multi_flush or hold_state_1; +ex3_flush <= ex4_np1_flush or ex4_n_flush or exx_multi_flush or hold_state_1; +ex4_flush <= ex4_n_flush or exx_multi_flush_q or hold_state_1; + +xu_rf0_flush <= rf0_flush_q; +xu_rf1_flush <= rf1_flush_q; +xu_ex1_flush <= ex1_flush_q; +xu_ex2_flush <= ex2_flush_q; +xu_ex3_flush <= ex3_flush_q; +xu_ex4_flush <= ex4_flush_q; +xu_ex5_flush <= ex5_flush_q; + +xu_n_is2_flush <= xu_is2_n_flush_q; +xu_n_rf0_flush <= xu_rf0_n_flush_q; +xu_n_rf1_flush <= xu_rf1_n_flush_q; +xu_n_ex1_flush <= xu_ex1_n_flush_q; +xu_n_ex2_flush <= xu_ex2_n_flush_q; +xu_n_ex3_flush <= xu_ex3_n_flush_q; +xu_n_ex4_flush <= xu_ex4_n_flush_q; +xu_n_ex5_flush <= xu_ex5_n_flush_q; + +xu_s_rf1_flush <= xu_rf1_s_flush_q; +xu_s_ex1_flush <= xu_ex1_s_flush_q; +xu_s_ex2_flush <= xu_ex2_s_flush_q; +xu_s_ex3_flush <= xu_ex3_s_flush_q; +xu_s_ex4_flush <= xu_ex4_s_flush_q; +xu_s_ex5_flush <= xu_ex5_s_flush_q; + +xu_w_rf1_flush <= xu_rf1_w_flush_q; +xu_w_ex1_flush <= xu_ex1_w_flush_q; +xu_w_ex2_flush <= xu_ex2_w_flush_q; +xu_w_ex3_flush <= xu_ex3_w_flush_q; +xu_w_ex4_flush <= xu_ex4_w_flush_q; +xu_w_ex5_flush <= xu_ex5_w_flush_q; + +-- MMU needs special flushes to avoid flushing a I/D-ERAT miss inside the MMU. +-- However, the I/D-ERAT miss still needs to get flushed out of the XU. +xu_mm_ex4_flush <= ex4_flush_q; +xu_mm_ex5_flush <= ex5_flush_q and not ex5_n_dmiss_flush_q; +xu_mm_ierat_flush <= is2_flush_q and not ierat_hold_present_q; -- Gets set by ex5 +xu_mm_ierat_miss <= ex5_n_imiss_flush_q; + +------------------------------------------------------------------------------- +-- Valid Shadow Pipes +------------------------------------------------------------------------------- +rf1_xu_val <= dec_cpl_rf1_val and not rf1_flush_q; +ex1_xu_val <= ex1_xu_val_q and not ex1_flush_q and not ex1_flush; -- Branch resolve needs fast flush +ex2_xu_val <= ex2_xu_val_q and not ex2_flush; +ex3_xu_val <= ex3_xu_val_q and not ex3_flush; +ex4_xu_val <= ex4_xu_val_q and not ex4_flush; + +ex2_axu_val <= fu_xu_ex2_ifar_val and not ex2_flush_q and not ex2_flush; +ex3_axu_val <= ex3_axu_val_q and not ex3_flush; +ex4_axu_val <= ex4_axu_val_q and not ex4_flush; + +rf1_ucode_val <= dec_cpl_rf1_ucode_val and not rf1_flush_q and not rf1_flush; +ex1_ucode_val <= ex1_ucode_val_q and not ex1_flush; +ex2_ucode_val <= ex2_ucode_val_q and not ex2_flush; +ex3_ucode_val <= ex3_ucode_val_q and not ex3_flush; +ex4_ucode_val <= ex4_ucode_val_q and not ex4_flush; + +ex3_any_val <= (ex3_xu_val_q or ex3_axu_val_q) and not ex3_flush; +ex4_any_val <= (ex4_xu_val_q or ex4_axu_val_q) and not ex4_flush; + + +ex3_anyuc_val <= ex3_anyuc_val_q and not ex3_flush; +ex4_anyuc_val <= ex4_anyuc_val_q and not ex4_flush; + +ex3_anyuc_val_q<= (ex3_xu_val_q or ex3_axu_val_q or + ex3_ucode_val_q); + +ex4_anyuc_val_q<= (ex4_xu_val_q or ex4_axu_val_q or + ex4_ucode_val_q); + +ex3_xuuc_val_q <= (ex3_xu_val_q or ex3_ucode_val_q); +ex4_xuuc_val_q <= (ex4_xu_val_q or ex4_ucode_val_q); + +ex3_xuuc_val <= ex3_xuuc_val_q and not ex3_flush; +ex4_xuuc_val <= ex4_xuuc_val_q and not ex4_flush; + +ex3_dep_val <= dec_cpl_ex3_mc_dep_chk_val and not ex3_flush; + +------------------------------------------------------------------------------- +-- Misc Logic +------------------------------------------------------------------------------- +ex3_n_mmu_mchk_flush_only <= not spr_ccr2_notlb and not spr_xucr4_mmu_mchk_int; + +ex3_is_any_ldst <= ex3_is_any_load_dac_q or ex3_is_any_store_dac_q or ex3_is_icswx_q; + + +ex2_msr_updater <= ex2_is_mtmsr_q or ex2_any_wrtee_q or + ex2_is_rfi_q or ex2_is_rfgi_q or + ex2_is_rfci_q or ex2_is_rfmci_q; + +ex5_cia_p1_d <= mux_t(ex4_cia_p1_out,ex4_xu_val_q); + +ex5_msr_cm <= or_reduce(ex5_xu_val_q and msr_cm_q); + +ex5_cia_p1(32 to 61) <= ex5_cia_p1_q(32 to 61); +ex5_cia_p1_gen : if IFAR'left < 32 generate + ex5_cia_p1(IFAR'left to 31) <= gate(ex5_cia_p1_q(IFAR'left to 31),ex5_msr_cm); +end generate; + +ex2_n_align_int_d <= ex1_is_any_ldstmw_q and or_reduce(alu_cpl_ex1_eff_addr(62 to 63)); + +ex1_taken_bclr <= ex1_is_bclr and ex1_br_taken; + +ex5_n_ext_dbg_stopc_flush_d <= or_reduce(ex4_dbsr_update and ext_dbg_stop_core_q); + +ex5_n_ext_dbg_stopt_flush_d <= ex4_dbsr_update and ext_dbg_stop_n_q; + +ex3_n_dcpe_flush_d <= (0 to threads-1=>lsu_xu_datc_perr_recovery); + +ex2_ifar <= not ex2_ifar_b_q; + +ex3_np1_mtiar_flush <= gate(ex3_xu_val,ex3_mtiar_q); +ex4_np1_mtiar_flush <= gate(ex4_xu_val,ex4_mtiar_q); + +ex2_any_wrtee_d <= ex1_is_wrtee_q or ex1_is_wrteei_q; + +ex7_is_tlbwe_d <= gate(ex6_xu_val_q,ex6_is_tlbwe_q); + +with s3'(pc_xu_ram_mode & pc_xu_ram_thread) select + ram_mode_d <= "1000" when "100", + "0100" when "101", + "0010" when "110", + "0001" when "111", + "0000" when others; + +with s3'(pc_xu_ram_execute & pc_xu_ram_thread) select + ram_execute_d <= "1000" when "100", + "0100" when "101", + "0010" when "110", + "0001" when "111", + "0000" when others; + +with s3'(pc_xu_ram_flush_thread & pc_xu_ram_thread) select + ram_flush_d <= "1000" when "100", + "0100" when "101", + "0010" when "110", + "0001" when "111", + "0000" when others; + + +ram_ip_d <= ram_mode_q and (ram_execute_q or -- Set on Execute + (ram_ip_q and not (ex4_ram_cpl or ex5_is_any_int))); -- Cleared on completion or interrupt + +-- ex5_ram_issue_q comes on when a ram instruction gets flushed. +-- However, if it gets flushed within two cycles of getting issued, +-- the iu does not flush it. accounting for this here. +ex5_ram_issue_gated <= ex5_ram_issue_q and not (ex7_ram_issue_q or ex8_ram_issue_q); + +ex5_ram_done_d <= or_reduce(ram_ip_q and ram_mode_q and gate(ex4_xu_val,not(ex4_xu_is_ucode_q))); +ex6_ram_issue_d <= ram_mode_q and (ram_execute_q or ex5_ram_issue_gated) and not ex5_ram_interrupt; +ex6_ram_interrupt_d <= or_reduce(ex5_ram_interrupt); +xu_iu_ram_issue <= ex6_ram_issue_q; +xu_pc_ram_interrupt <= ex6_ram_interrupt_q; +xu_pc_ram_done <= ex6_ram_done_q; +xu_pc_step_done <= ex6_step_done_q; + +with dec_cpl_ex2_error select + ex3_iu_error_d <= "1000000" when "001", + "0100000" when "010", + "0010000" when "011", + "0001000" when "100", + "0000100" when "101", + "0000010" when "110", + "0000001" when "111", + "0000000" when others; + +ex4_dac1r_cmpr_async_d <= fxu_cpl_ex3_dac1r_cmpr_async; +ex4_dac2r_cmpr_async_d <= fxu_cpl_ex3_dac2r_cmpr_async; + +ex4_dacr_cmpr_d(1) <= fxu_cpl_ex3_dac1r_cmpr; +ex4_dacr_cmpr_d(2) <= fxu_cpl_ex3_dac2r_cmpr; +ex4_dacr_cmpr_d(3) <= fxu_cpl_ex3_dac3r_cmpr; +ex4_dacr_cmpr_d(4) <= fxu_cpl_ex3_dac4r_cmpr; + +ex4_dacw_cmpr_d(1) <= fxu_cpl_ex3_dac1w_cmpr; +ex4_dacw_cmpr_d(2) <= fxu_cpl_ex3_dac2w_cmpr; +ex4_dacw_cmpr_d(3) <= fxu_cpl_ex3_dac3w_cmpr; +ex4_dacw_cmpr_d(4) <= fxu_cpl_ex3_dac4w_cmpr; + +ex5_is_attn_d <= gate(ex4_xu_val,ex4_is_attn_q); + +ex5_xu_ifar_d <= mux_t(ex4_ifar_q,ex4_xu_val_q); + +------------------------------------------------------------------------------- +-- Barrier Set +------------------------------------------------------------------------------- +-- These two should be mutually exclusive +ex4_lsu_barr_flush <= ex4_barrier_flush and ex4_n_ldq_hit_flush_q; +ex4_div_barr_flush <= ex4_barrier_flush and ex4_n_barr_flush_q; + +ex5_lsu_set_barr_d <= gate(ex4_lsu_barr_flush,not(spr_xucr4_lsu_bar_dis)); +ex5_div_set_barr_d <= gate(ex4_div_barr_flush,not(spr_xucr4_div_bar_dis)); + +xu_lsu_ex5_set_barr <= ex5_lsu_set_barr_q; +cpl_fxa_ex5_set_barr <= ex5_div_set_barr_q; + +ex6_set_barr_d <= ex5_lsu_set_barr_q; + +cpl_iu_set_barr_tid <= ex6_set_barr_q; + +------------------------------------------------------------------------------- +-- Quiesce State +------------------------------------------------------------------------------- +cpl_quiesced_d <= not( + ssprwr_ip_q or + ex5_in_ucode_q or + ex3_async_int_block_q or + hold_state_0 or + hold_state_1); + +cpl_spr_quiesce <= cpl_quiesced_q; + +quiesced_d <= and_reduce(spr_cpl_quiesce); + +------------------------------------------------------------------------------- +-- Hold Generation - per core +------------------------------------------------------------------------------- +hold_state_1 <=(others=> + (ici_hold_present or + fu_rfpe_hold_present_q or + xu_rfpe_hold_present_q)); + +dci_val_d <= or_reduce(ex4_xu_val) and ex4_is_dci_q; +ici_val_d <= or_reduce(ex4_xu_val) and ex4_is_ici_q; + +ici_hold_present_d(0 to 2) <= ici_val_d & ici_hold_present_q(0 to 1); +ici_hold_present <= or_reduce(ici_hold_present_q); + +ex4_n_fu_rfpe_set <= or_reduce(ex4_n_fu_rfpe_flush); +ex4_n_xu_rfpe_set <= or_reduce(ex4_n_xu_rfpe_flush); + +-- Put the set in the equation to force wait at least 192 cycles for a divide/slowspr to clear out +rfpe_quiesce_cond_b <= ex4_n_fu_rfpe_set or ex4_n_xu_rfpe_set or not quiesced_q; + +rfpe_quiesced <= not rfpe_quiesce_cond_b and not rfpe_quiesced_ctr_zero_b; + +rfpe_quiesce_fctr : entity work.xuq_cpl_fctr(xuq_cpl_fctr) +generic map (threads => 1, expand_type => expand_type, passthru => 0, clockgate => 0, delay_width => 8) +port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rfpe_quiesce_offset), + scout => sov(rfpe_quiesce_offset), + delay => "11000000", + din(0) => rfpe_quiesce_cond_b, + dout(0) => rfpe_quiesced_ctr_zero_b); + +fu_rfpe_hold_present_d <= (ex4_n_fu_rfpe_set or fu_rfpe_hold_present_q) and not (rfpe_quiesced and fu_rf_seq_end_q); +xu_rfpe_hold_present_d <= (ex4_n_xu_rfpe_set or xu_rfpe_hold_present_q) and not (rfpe_quiesced and xu_rf_seq_end_q); + +fu_rfpe_ack_d(0) <= fu_rfpe_hold_present_q and rfpe_quiesced; +fu_rfpe_ack_d(1) <= fu_rfpe_ack_d(0) and not fu_rfpe_ack_q(0); +xu_fu_regfile_seq_beg <= fu_rfpe_ack_q(1); + +xu_rfpe_ack_d(0) <= xu_rfpe_hold_present_q and rfpe_quiesced; +xu_rfpe_ack_d(1) <= xu_rfpe_ack_d(0) and not xu_rfpe_ack_q(0); +cpl_gpr_regfile_seq_beg <= xu_rfpe_ack_q(1); + +------------------------------------------------------------------------------- +-- IO assignments +------------------------------------------------------------------------------- +pc_dbg_stop <= pc_dbg_stop_q and not (ex5_in_ucode_q or ex4_ucode_val); +cpl_spr_stop <= pc_dbg_stop_2_q; +xu_lsu_dci <= dci_val_q; +xu_lsu_ici <= ici_val_q; +xu_pc_stop_dbg_event <= (0 to threads-1=>ex5_n_ext_dbg_stopc_flush_q) or ex5_n_ext_dbg_stopt_flush_q; +ac_tc_debug_trigger <= ex5_ext_dbg_ext_q; +xu_iu_ex5_ifar <= ex5_xu_ifar_q; +xu_iu_ex5_br_taken <= or_reduce(ex5_xu_val_q) and ex5_br_taken_q; +cpl_spr_ex5_instr_cpl <= ex5_any_val_q; +spr_xucr4_mmu_mchk <= spr_xucr4_mmu_mchk_int; + +xu_iu_flush_2ucode <= ex5_flush_2ucode_q; +xu_iu_ucode_restart <= ex5_ucode_restart_q; +xu_iu_flush_2ucode_type <= ex5_mem_attr_le_q; + +cpl_spr_ex5_act <= ex5_late_flush_q(0) or ex6_late_flush_q; +cpl_spr_ex5_int <= ex5_is_base_hint; +cpl_spr_ex5_gint <= ex5_is_base_gint; +cpl_spr_ex5_cint <= ex5_is_crit_int_q; +cpl_spr_ex5_mcint <= ex5_is_mchk_int_q; +cpl_spr_ex5_srr0_dec <= ex5_srr0_dec_q; +cpl_spr_ex5_force_gsrr <= ex5_force_gsrr_q; +cpl_spr_ex5_dbsr_update <= ex5_dbsr_update_q; +cpl_spr_ex5_esr <= ex5_esr_q; +cpl_spr_ex5_mcsr <= ex5_mcsr_q; +cpl_spr_ex5_dbsr <= ex5_dbsr_q; +cpl_spr_ex5_dbell_taken <= ex5_dbell_taken_q; +cpl_spr_ex5_cdbell_taken <= ex5_cdbell_taken_q; +cpl_spr_ex5_gdbell_taken <= ex5_gdbell_taken_q; +cpl_spr_ex5_gcdbell_taken <= ex5_gcdbell_taken_q; +cpl_spr_ex5_gmcdbell_taken <= ex5_gmcdbell_taken_q; + +cpl_dec_in_ucode <= ex5_in_ucode_q; + +cpl_msr_gs <= msr_gs_q; +cpl_msr_pr <= msr_pr_q; +cpl_msr_fp <= msr_fp_q; +cpl_msr_spv <= msr_spv_q; +cpl_ccr2_ap <= ccr2_ap_q; + +------------------------------------------------------------------------------- +-- Performance Counters +------------------------------------------------------------------------------- +ex2_perf_event_d(0) <= ex1_branch; +ex2_perf_event_d(1) <= ex1_br_mispred; +ex2_perf_event_d(2) <= ex1_br_taken; + +ex4_perf_event_d(0) <= ex3_perf_event_q(0); +ex4_perf_event_d(1) <= ex3_perf_event_q(1); +ex4_perf_event_d(2) <= ex3_perf_event_q(2); +ex4_perf_event_d(3) <= or_reduce(ex3_n_multcoll_flush); + +------------------------------------------------------------------------------- +-- SIAR +------------------------------------------------------------------------------- +ex4_xu_siar_val <= or_reduce(ex4_xuuc_val and not ex5_in_ucode_q); +ex4_axu_siar_val <= or_reduce(ex4_axu_val and not ex5_in_ucode_q); +ex4_siar_cpl <= (ex4_instr_cpl and not ex5_in_ucode_q) or ex4_ucode_val; + +-- Kill the issued bit if the IU issued an Error. The IFAR is invalid in this case. +ex3_xu_issued <= gate(ex3_xu_issued_q,not(or_reduce(ex3_iu_error_q))); + +ex4_siar_sel_act <= ex4_xu_siar_val and ex4_axu_siar_val and trace_bus_enable_q; +ex4_siar_sel_d(0 to 1) <= ex4_siar_sel_q(1) & ex4_siar_sel_q(0); + +with ex4_siar_sel_act select + ex4_siar_axu_sel <= ex4_siar_sel_q(1) when '1', -- Tiebreaker + ex4_axu_siar_val when others; + +with (ex4_siar_axu_sel and not ex4_instr_trace_val_q) select + ex4_siar_tid <= ex4_axu_issued_q when '1', + ex4_xu_issued_q when others; + +with (ex4_siar_axu_sel and not ex4_instr_trace_val_q) select + ex4_siar_sel <= (ex4_axu_val_q and not ex5_in_ucode_q) when '1', + (ex4_xuuc_val_q and not ex5_in_ucode_q) when others; + + +ex4_siar_cm_mask(32 to 61) <= (others=>'1'); +xuq_cpl_siar_cm_mask_gen : if IFAR'left < 32 generate + ex4_siar_cm_mask(IFAR'left to 31) <= (others=>or_reduce(msr_cm_q and ex4_siar_sel)); +end generate; +ex5_siar_d <= ex4_siar_cm_mask and mux_t(ex4_ifar_q,ex4_siar_sel); +ex5_siar_gs_d <= or_reduce(msr_gs_q and ex4_siar_sel); +ex5_siar_pr_d <= or_reduce(msr_pr_q and ex4_siar_sel); +ex5_siar_cpl_d <= or_reduce(ex4_siar_cpl and ex4_siar_sel); +ex5_siar_issued_d <= or_reduce(ex4_siar_tid); +with s4'(ex4_siar_cpl and ex4_siar_sel) select + ex5_siar_tid_d <= "00" when "1000", + "01" when "0100", + "10" when "0010", + "11" when others; + +mark_unused(ex5_siar_issued_q); + +------------------------------------------------------------------------------- +-- Debug +------------------------------------------------------------------------------- +-- NOTE: The following bits can be muxed onto the perf event bus: +-- 0:15, 22:36, 44:59, 66:81 + +-- Rotates on 0:21, 22:43, 44:65, 66:87 + +dbg_subgroup_gen : for t in 0 to threads-1 generate +dbg_valids_opc(t)(0 to 4) <= ex5_xu_val_dbg_opc(t) & ex5_axu_val_dbg_opc(t) & ex5_instr_cpl_dbg_q(t) & ex5_ucode_val_dbg_q(t) & ex5_ucode_end_dbg_q(t); +dbg_valids(t)(0 to 4) <= ex5_xu_val_q(t) & ex5_axu_val_dbg_q(t) & ex5_instr_cpl_dbg_q(t) & ex5_ucode_val_dbg_q(t) & ex5_ucode_end_dbg_q(t); +dbg_iuflush(t)(0 to 8) <= ex2_br_flush(t) & iu_flush(t) & ex5_is_any_hint(t) & ex5_is_any_gint(t) & ex5_ucode_restart_q(t) & ex5_flush_2ucode_q(t) & ex5_mem_attr_le_q(t) & hold_state_0(t) & hold_state_1(t); +dbg_msr(t)(0 to 4) <= msr_de_q(t) & msr_cm_q(t) & msr_gs_q(t) & msr_me_q(t) & msr_pr_q(t); +dbg_match(t)(0) <= ex5_dbsr_q(18+19*t); +dbg_match(t)(1) <= ex5_dbsr_q(5+19*t) or ex5_dbsr_q(6+19*t) or ex5_dbsr_q(7+19*t) or ex5_dbsr_q(8+19*t); +dbg_match(t)(2) <= ex5_dbsr_q(9+19*t) or ex5_dbsr_q(10+19*t) or ex5_dbsr_q(11+19*t) or ex5_dbsr_q(12+19*t) or + ex5_dbsr_q(14+19*t) or ex5_dbsr_q(15+19*t) or ex5_dbsr_q(16+19*t) or ex5_dbsr_q(17+19*t); +dbg_flushcond_d(t)(00) <= ex3_n_lsu_ddpe_flush(t); + +dbg_flushcond_d(t)(01) <= ex3_n_barr_flush(t); + +dbg_flushcond_d(t)(02) <= ex3_n_l2_ecc_err_flush_q(t); +dbg_flushcond_d(t)(03) <= ex3_n_dcpe_flush_q(t); +dbg_flushcond_d(t)(04) <= ex3_n_dlk0_dstor_int(t); +dbg_flushcond_d(t)(05) <= ex3_n_dlk1_dstor_int(t); +dbg_flushcond_d(t)(06) <= ex3_n_ieratre_par_mchk_mcint(t); +dbg_flushcond_d(t)(07) <= ex3_np1_sprg_ce_flush(t); +dbg_flushcond_d(t)(08) <= ex3_n_2ucode_flush(t); +dbg_flushcond_d(t)(09) <= ex3_n_lsualign_2ucode_flush(t); +dbg_flushcond_d(t)(10) <= ex3_n_fu_2ucode_flush(t); +dbg_flushcond_d(t)(11) <= ex3_n_mmuhold_flush(t); +dbg_flushcond_d(t)(12) <= ex3_n_lsu_dcpe_flush(t); +dbg_flushcond_d(t)(13) <= ex5_n_ext_dbg_stopc_flush_q; +dbg_flushcond_d(t)(14) <= ex5_n_ext_dbg_stopt_flush_q(t); +dbg_flushcond_d(t)(15) <= ex3_n_dci_flush(t); +dbg_flushcond_d(t)(16) <= ex3_n_ici_flush(t); +dbg_flushcond_d(t)(17) <= ex3_n_multcoll_flush(t); +dbg_flushcond_d(t)(18) <= ex3_n_ram_flush(t); +dbg_flushcond_d(t)(19) <= ex3_n_derat_dep_flush(t); +dbg_flushcond_d(t)(20) <= ex3_n_lsu_dep_flush(t); +dbg_flushcond_d(t)(21) <= ex3_n_dep_flush(t); +dbg_flushcond_d(t)(22) <= ex3_n_thrctl_stop_flush(t); +dbg_flushcond_d(t)(23) <= ex3_n_bclr_ta_miscmpr_flush(t); +dbg_flushcond_d(t)(24) <= ex3_n_memattr_miscmpr_flush(t); +dbg_flushcond_d(t)(25) <= ex3_np1_instr_flush(t); +dbg_flushcond_d(t)(26) <= ex3_n_ldq_hit_flush(t); +dbg_flushcond_d(t)(27) <= ex3_np1_fu_flush(t); +dbg_flushcond_d(t)(28) <= ex3_n_fu_dep_flush(t); +dbg_flushcond_d(t)(29) <= ex3_n_mmu_flush(t); +dbg_flushcond_d(t)(30) <= ex3_n_tlbmiss_dtlb_int(t); +dbg_flushcond_d(t)(31) <= ex3_n_deratmiss_dtlb_int(t); +dbg_flushcond_d(t)(32) <= ex3_n_tlbmiss_itlb_int(t); +dbg_flushcond_d(t)(33) <= ex3_n_ieratmiss_itlb_int(t); +dbg_flushcond_d(t)(34) <= ex3_n_apena_prog_int(t); +dbg_flushcond_d(t)(35) <= ex3_n_fpena_prog_int(t); +dbg_flushcond_d(t)(36) <= ex3_n_tlbpil_prog_int_xu(t) and ex3_xu_val(t); +dbg_flushcond_d(t)(37) <= ex3_n_sprpil_prog_int_xu(t) and ex3_xu_val(t); +dbg_flushcond_d(t)(38) <= ex3_n_iupil_prog_int_xuuc(t) and ex3_xuuc_val(t); +dbg_flushcond_d(t)(39) <= ex3_n_mmupil_prog_int_xu(t) and ex3_xu_val(t); +dbg_flushcond_d(t)(40) <= ex3_n_xupil_prog_int_xuuc(t) and ex3_xuuc_val(t); +dbg_flushcond_d(t)(41) <= ex3_n_puo_prog_int(t); +dbg_flushcond_d(t)(42) <= ex3_n_sprppr_prog_int_xuuc(t) and ex3_xuuc_val(t); +dbg_flushcond_d(t)(43) <= ex3_n_instrppr_prog_int_xuuc(t) and ex3_xuuc_val(t); +dbg_flushcond_d(t)(44) <= ex3_np1_ptr_prog_int(t); +dbg_flushcond_d(t)(45) <= ex3_n_any_unavail_int(t); +dbg_flushcond_d(t)(46) <= ex3_n_ldst_align_int(t); +dbg_flushcond_d(t)(47) <= ex3_n_ldstmw_align_int(t); +dbg_flushcond_d(t)(48) <= ex3_n_vf_dstor_int(t); +dbg_flushcond_d(t)(49) <= ex3_n_tlbi_dstor_int(t); +dbg_flushcond_d(t)(50) <= ex3_n_i1w1lock_dstor_int(t); +dbg_flushcond_d(t)(51) <= ex3_n_rwaccess_dstor_int(t); +dbg_flushcond_d(t)(52) <= ex3_n_uct_dstor_int(t); +dbg_flushcond_d(t)(53) <= ex3_n_pt_dstor_int(t); +dbg_flushcond_d(t)(54) <= ex3_n_tlbi_istor_int(t); +dbg_flushcond_d(t)(55) <= ex3_n_exaccess_istor_int(t); +dbg_flushcond_d(t)(56) <= ex3_n_pt_istor_int(t); +dbg_flushcond_d(t)(57) <= ex3_np1_instr_int(t); +dbg_flushcond_d(t)(58) <= ex3_n_ptemiss_dlrat_int(t); +dbg_flushcond_d(t)(59) <= ex3_n_tlbwemiss_dlrat_int(t); +dbg_flushcond_d(t)(60) <= ex3_n_spr_hpriv_int_xuuc(t) and ex3_xuuc_val(t); +dbg_flushcond_d(t)(61) <= ex3_n_instr_hpriv_int_xuuc(t) and ex3_xuuc_val(t); +dbg_flushcond_d(t)(62) <= ex3_n_mmu_hpriv_int(t); +dbg_flushcond_d(t)(63) <= ex3_n_ehpriv_hpriv_int(t); + + +dbg_hold(t)(0 to 5) <= mmu_hold_present_q(t) & derat_hold_present_q(t) & ierat_hold_present_q(t) & ici_hold_present & fu_rfpe_hold_present_q & xu_rfpe_hold_present_q; +dbg_async_block(t)(0 to 6) <= ssprwr_ip_q(t) & ex5_in_ucode_q(t) & ram_mode_q(t) & ex3_async_int_block_q(t) & ex4_icmp_async_block(t) & exx_hold0_mcflush(t) & exx_hold1_mcflush(t); +dbg_int_types(t)(0 to 4) <= ex4_is_mchk_int(t) & ex4_is_crit_int(t) & ex5_is_any_hint(t) & ex5_is_any_gint(t) & ex5_is_any_rfi_q(t); +dbg_misc(t)(0 to 3) <= ex5_tlb_inelig_q(t) & ex5_dear_update_saved_q(t) & exx_cm_hold(t) & ex3_esr_bit_act(t); + + +end generate; + +ex5_xu_ppc_cpl <= (ex5_xu_val_q and not (ex5_in_ucode_q or ex5_ucode_end_dbg_q)) or ex5_ucode_val_dbg_q; +ex5_axu_ppc_cpl <= (ex5_axu_val_dbg_q and not (ex5_in_ucode_q or ex5_ucode_end_dbg_q)); + +ex5_axu_trace_val <= instr_trace_mode_q and or_reduce(ex5_axu_ppc_cpl); +ex5_xu_trace_val <= ex5_instr_trace_val_q and or_reduce(ex5_xu_ppc_cpl); + +siar_cm(0) <= msr_cm_q(0) and not ex5_instr_trace_val_q; +siar_cm(1 to 2) <= msr_cm_q(1 to 2); +siar_cm(3) <=(msr_cm_q(3) and not ex5_instr_trace_val_q) or ex5_xu_trace_val; + +-- 0:4 5 6:11 12:73 74:82 83:87 +dbg_group0 <= dbg_valids(0) & ex5_in_ucode_q(0) & ex5_flush_pri_enc_dbg(0) & ex4_cia_out(0) & dbg_iuflush(0) & dbg_msr(0); +dbg_group1 <= dbg_valids(1) & ex5_in_ucode_q(1) & ex5_flush_pri_enc_dbg(1) & ex4_cia_out(1) & dbg_iuflush(1) & dbg_msr(1); +dbg_group2 <= dbg_valids(2) & ex5_in_ucode_q(2) & ex5_flush_pri_enc_dbg(2) & ex4_cia_out(2) & dbg_iuflush(2) & dbg_msr(2); +dbg_group3 <= dbg_valids(3) & ex5_in_ucode_q(3) & ex5_flush_pri_enc_dbg(3) & ex4_cia_out(3) & dbg_iuflush(3) & dbg_msr(3); +-- 0:4 5:9 10:14 15:19 20:23 24:30 31:41 42:55 56:63 64:71 72:79 80:87 +dbg_group4 <= dbg_valids_opc(0) & dbg_valids_opc(1) & dbg_valids_opc(2) & dbg_valids_opc(3) & ex5_in_ucode_q & ex1_instr(0 to 6) & ex1_instr(21 to 31) & ex1_instr(7 to 20) & ex4_cia_out(0)(54 to 61) & ex4_cia_out(1)(54 to 61) & ex4_cia_out(2)(54 to 61) & ex4_cia_out(3)(54 to 61); +-- 0:4 5 6:11 12:75 76:82 83:87 +dbg_group5 <= dbg_valids(0) & ex5_in_ucode_q(0) & ex5_flush_pri_enc_dbg(0) & dbg_flushcond_q(0)(0 to 63) & dbg_iuflush(0)(0 to 6) & dbg_msr(0); +dbg_group6 <= dbg_valids(1) & ex5_in_ucode_q(1) & ex5_flush_pri_enc_dbg(1) & dbg_flushcond_q(1)(0 to 63) & dbg_iuflush(1)(0 to 6) & dbg_msr(1); +dbg_group7 <= dbg_valids(2) & ex5_in_ucode_q(2) & ex5_flush_pri_enc_dbg(2) & dbg_flushcond_q(2)(0 to 63) & dbg_iuflush(2)(0 to 6) & dbg_msr(2); +dbg_group8 <= dbg_valids(3) & ex5_in_ucode_q(3) & ex5_flush_pri_enc_dbg(3) & dbg_flushcond_q(3)(0 to 63) & dbg_iuflush(3)(0 to 6) & dbg_msr(3); +-- 0:4 5 6:11 12:20 21:52 +dbg_group9 <= dbg_valids(0) & ex5_in_ucode_q(0) & ex5_flush_pri_enc_dbg(0) & dbg_iuflush(0) & ex1_instr(0 to 31) & + dbg_hold(0)(0 to 5) & dbg_async_block(0)(0 to 6) & dbg_int_types(0)(0 to 4) & dbg_misc(0)(0 to 3) & -- 53:75 + br_debug & '0'; -- 76:87 + +dbg_group10 <= dbg_valids(1) & ex5_in_ucode_q(1) & ex5_flush_pri_enc_dbg(1) & dbg_iuflush(1) & ex1_instr(0 to 31) & + dbg_hold(1)(0 to 5) & dbg_async_block(1)(0 to 6) & dbg_int_types(1)(0 to 4) & dbg_misc(1)(0 to 3) & -- 53:75 + br_debug & '0'; -- 76:87 + +dbg_group11 <= dbg_valids(2) & ex5_in_ucode_q(2) & ex5_flush_pri_enc_dbg(2) & dbg_iuflush(2) & ex1_instr(0 to 31) & + dbg_hold(2)(0 to 5) & dbg_async_block(2)(0 to 6) & dbg_int_types(2)(0 to 4) & dbg_misc(2)(0 to 3) & -- 53:75 + br_debug & '0'; -- 76:87 + +dbg_group12 <= dbg_valids(3) & ex5_in_ucode_q(3) & ex5_flush_pri_enc_dbg(3) & dbg_iuflush(3) & ex1_instr(0 to 31) & + dbg_hold(3)(0 to 5) & dbg_async_block(3)(0 to 6) & dbg_int_types(3)(0 to 4) & dbg_misc(3)(0 to 3) & -- 53:75 + br_debug & '0'; -- 76:87 + +-- 0:61 62 63 64:67 68 69 70:71 72:75 76:79 80:83 84:87 +dbg_group13 <= ex5_siar_q & ex5_siar_gs_q & ex5_siar_pr_q & siar_cm & ex5_siar_cpl_q & ex5_siar_cpl_q & ex5_siar_tid_q & ex4_xu_issued_q & ex4_axu_issued_q & ex5_instr_cpl_q & ex5_ucode_val_dbg_q; +-- 0:31 32:55 56 57:58 59:63 64 65:66 67 +dbg_group14 <= ex2_instr_dbg_q & x"0ABCDE" & '1' & ex2_instr_trace_type_q & (59 to 63=>'0') & '1' & ex2_instr_trace_type_q & '1' & (68 to 87=>'0'); +-- 0:31 32:36 37 38:43 44 45 +dbg_group15 <= ex1_instr(0 to 31) & dbg_valids(0) & ex5_in_ucode_q(0) & ex5_flush_pri_enc_dbg(0) & iu_flush(0) & ex5_ucode_restart_q(0) & + dbg_valids(1) & ex5_in_ucode_q(1) & ex5_flush_pri_enc_dbg(1) & iu_flush(1) & ex5_ucode_restart_q(1) & + dbg_valids(2) & ex5_in_ucode_q(2) & ex5_flush_pri_enc_dbg(2) & iu_flush(2) & ex5_ucode_restart_q(2) & + dbg_valids(3) & ex5_in_ucode_q(3) & ex5_flush_pri_enc_dbg(3) & iu_flush(3) & ex5_ucode_restart_q(3); +dbg_group16 <= (others=>'0'); +dbg_group17 <= (others=>'0'); +dbg_group18 <= (others=>'0'); +dbg_group19 <= (others=>'0'); +dbg_group20 <= (others=>'0'); +dbg_group21 <= (others=>'0'); +dbg_group22 <= (others=>'0'); +dbg_group23 <= (others=>'0'); +dbg_group24 <= (others=>'0'); +dbg_group25 <= (others=>'0'); +dbg_group26 <= (others=>'0'); +dbg_group27 <= (others=>'0'); +dbg_group28 <= fxa_cpl_debug(0 to 87); +dbg_group29 <= fxa_cpl_debug(88 to 175); +dbg_group30 <= fxa_cpl_debug(207 to 272) & fxa_cpl_debug(176 to 197); +dbg_group31 <= fxa_cpl_debug(198 to 272) & ex5_xu_ifar_q(49 to 61); +trg_group0 <= dbg_valids(0)(0 to 4) & dbg_iuflush(0)(0 to 3) & dbg_match(0)(0 to 2); +trg_group1 <= dbg_valids(1)(0 to 4) & dbg_iuflush(1)(0 to 3) & dbg_match(1)(0 to 2); +trg_group2 <= dbg_valids(2)(0 to 4) & dbg_iuflush(2)(0 to 3) & dbg_match(2)(0 to 2); +trg_group3 <= dbg_valids(3)(0 to 4) & dbg_iuflush(3)(0 to 3) & dbg_match(3)(0 to 2); + +-- fxa_group0( 0:87) (88) Instruction / Mult/Div +-- fxa_group1(88:175) (88) Issue Interface +-- fxa_group2(176:197) (22) GPR Parity Error +-- fxa_group3(198:263) (66) Reload Write Data +-- fxa_group4(264:272) (09) Reload Write Addr/Valid + + +with s2'(ex1_instr_trace_val_q & ex4_instr_trace_val_q) select + debug_mux_ctrls_int <= x"71E0" when "10", -- Group 14 + x"69E0" when "01", -- Group 13 + debug_mux_ctrls_q when others; + + +cpl_debug_data_in_int(0 to 55) <= cpl_debug_data_in(0 to 55); +cpl_debug_data_in_int(56) <= cpl_debug_data_in(56) or ex5_axu_trace_val; +cpl_debug_data_in_int(57 to 63) <= cpl_debug_data_in(57 to 63); +cpl_debug_data_in_int(64) <= cpl_debug_data_in(64) or ex5_axu_trace_val; +cpl_debug_data_in_int(65 to 66) <= cpl_debug_data_in(65 to 66); +cpl_debug_data_in_int(67) <= cpl_debug_data_in(67) or ex5_axu_trace_val; +cpl_debug_data_in_int(68 to 87) <= cpl_debug_data_in(68 to 87); + +xu_debug_mux : entity clib.c_debug_mux32(c_debug_mux32) +port map( + vd => vdd, + gd => gnd, + select_bits => debug_mux_ctrls_int_q, + trace_data_in => cpl_debug_data_in_int, + trigger_data_in => cpl_trigger_data_in, + dbg_group0 => dbg_group0, + dbg_group1 => dbg_group1, + dbg_group2 => dbg_group2, + dbg_group3 => dbg_group3, + dbg_group4 => dbg_group4, + dbg_group5 => dbg_group5, + dbg_group6 => dbg_group6, + dbg_group7 => dbg_group7, + dbg_group8 => dbg_group8, + dbg_group9 => dbg_group9, + dbg_group10 => dbg_group10, + dbg_group11 => dbg_group11, + dbg_group12 => dbg_group12, + dbg_group13 => dbg_group13, + dbg_group14 => dbg_group14, + dbg_group15 => dbg_group15, + dbg_group16 => dbg_group16, + dbg_group17 => dbg_group17, + dbg_group18 => dbg_group18, + dbg_group19 => dbg_group19, + dbg_group20 => dbg_group20, + dbg_group21 => dbg_group21, + dbg_group22 => dbg_group22, + dbg_group23 => dbg_group23, + dbg_group24 => dbg_group24, + dbg_group25 => dbg_group25, + dbg_group26 => dbg_group26, + dbg_group27 => dbg_group27, + dbg_group28 => dbg_group28, + dbg_group29 => dbg_group29, + dbg_group30 => dbg_group30, + dbg_group31 => dbg_group31, + trg_group0 => trg_group0, + trg_group1 => trg_group1, + trg_group2 => trg_group2, + trg_group3 => trg_group3, + trigger_data_out => trigger_data_out_d, + trace_data_out => debug_data_out_d); + +cpl_trigger_data_out <= trigger_data_out_q; +cpl_debug_data_out <= debug_data_out_q; + + +-- Unused Signals +mark_unused(ex3_iu_error_q(3)); +mark_unused(spare_0_q); +mark_unused(spare_1_q); +mark_unused(spare_2_q); +mark_unused(spare_3_q); +mark_unused(spare_4_q); + + +------------------------------------------------------------------------------- +-- Latches +------------------------------------------------------------------------------- +is2_flush_latch : tri_rlmreg_p + generic map (width => is2_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(is2_flush_offset to is2_flush_offset + is2_flush_q'length-1), + scout => sov(is2_flush_offset to is2_flush_offset + is2_flush_q'length-1), + din => any_flush , + dout => is2_flush_q); +rf0_flush_latch : tri_rlmreg_p + generic map (width => rf0_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_flush_inf_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_flush_offset to rf0_flush_offset + rf0_flush_q'length-1), + scout => sov(rf0_flush_offset to rf0_flush_offset + rf0_flush_q'length-1), + din => is2_flush , + dout => rf0_flush_q); +rf1_flush_latch : tri_rlmreg_p + generic map (width => rf1_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_flush_inf_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf1_flush_offset to rf1_flush_offset + rf1_flush_q'length-1), + scout => sov(rf1_flush_offset to rf1_flush_offset + rf1_flush_q'length-1), + din => rf0_flush , + dout => rf1_flush_q); +rf1_tid_latch : tri_rlmreg_p + generic map (width => rf1_tid_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf1_tid_offset to rf1_tid_offset + rf1_tid_q'length-1), + scout => sov(rf1_tid_offset to rf1_tid_offset + rf1_tid_q'length-1), + din => dec_cpl_rf0_tid , + dout => rf1_tid_q); +ex1_axu_act_latch : tri_rlmreg_p + generic map (width => ex1_axu_act_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_axu_act_offset to ex1_axu_act_offset + ex1_axu_act_q'length-1), + scout => sov(ex1_axu_act_offset to ex1_axu_act_offset + ex1_axu_act_q'length-1), + din => fu_xu_rf1_act , + dout => ex1_axu_act_q); +ex1_byte_rev_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_byte_rev_offset), + scout => sov(ex1_byte_rev_offset), + din => rf1_byte_rev, + dout => ex1_byte_rev_q); +ex1_flush_latch : tri_rlmreg_p + generic map (width => ex1_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_flush_inf_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_flush_offset to ex1_flush_offset + ex1_flush_q'length-1), + scout => sov(ex1_flush_offset to ex1_flush_offset + ex1_flush_q'length-1), + din => rf1_flush , + dout => ex1_flush_q); +ex1_is_any_ldstmw_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_any_ldstmw_offset), + scout => sov(ex1_is_any_ldstmw_offset), + din => rf1_is_any_ldstmw, + dout => ex1_is_any_ldstmw_q); +ex1_is_attn_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_attn_offset), + scout => sov(ex1_is_attn_offset), + din => rf1_is_attn, + dout => ex1_is_attn_q); +ex1_is_dci_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_dci_offset), + scout => sov(ex1_is_dci_offset), + din => ex1_is_dci_d, + dout => ex1_is_dci_q); +ex1_is_dlock_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_dlock_offset), + scout => sov(ex1_is_dlock_offset), + din => rf1_is_dlock, + dout => ex1_is_dlock_q); +ex1_is_ehpriv_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_ehpriv_offset), + scout => sov(ex1_is_ehpriv_offset), + din => rf1_is_ehpriv, + dout => ex1_is_ehpriv_q); +ex1_is_erativax_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_erativax_offset), + scout => sov(ex1_is_erativax_offset), + din => rf1_is_erativax, + dout => ex1_is_erativax_q); +ex1_is_ici_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_ici_offset), + scout => sov(ex1_is_ici_offset), + din => ex1_is_ici_d, + dout => ex1_is_ici_q); +ex1_is_icswx_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_icswx_offset), + scout => sov(ex1_is_icswx_offset), + din => rf1_is_icswx, + dout => ex1_is_icswx_q); +ex1_is_ilock_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_ilock_offset), + scout => sov(ex1_is_ilock_offset), + din => rf1_is_ilock, + dout => ex1_is_ilock_q); +ex1_is_isync_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_isync_offset), + scout => sov(ex1_is_isync_offset), + din => rf1_is_isync, + dout => ex1_is_isync_q); +ex1_is_mfspr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_mfspr_offset), + scout => sov(ex1_is_mfspr_offset), + din => rf1_is_mfspr, + dout => ex1_is_mfspr_q); +ex1_is_mtmsr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_mtmsr_offset), + scout => sov(ex1_is_mtmsr_offset), + din => rf1_is_mtmsr, + dout => ex1_is_mtmsr_q); +ex1_is_mtspr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_mtspr_offset), + scout => sov(ex1_is_mtspr_offset), + din => rf1_is_mtspr, + dout => ex1_is_mtspr_q); +ex1_is_rfci_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_rfci_offset), + scout => sov(ex1_is_rfci_offset), + din => rf1_is_rfci, + dout => ex1_is_rfci_q); +ex1_is_rfgi_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_rfgi_offset), + scout => sov(ex1_is_rfgi_offset), + din => rf1_is_rfgi, + dout => ex1_is_rfgi_q); +ex1_is_rfi_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_rfi_offset), + scout => sov(ex1_is_rfi_offset), + din => rf1_is_rfi, + dout => ex1_is_rfi_q); +ex1_is_rfmci_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_rfmci_offset), + scout => sov(ex1_is_rfmci_offset), + din => rf1_is_rfmci, + dout => ex1_is_rfmci_q); +ex1_is_sc_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_sc_offset), + scout => sov(ex1_is_sc_offset), + din => rf1_is_sc, + dout => ex1_is_sc_q); +ex1_is_tlbivax_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_tlbivax_offset), + scout => sov(ex1_is_tlbivax_offset), + din => rf1_is_tlbivax, + dout => ex1_is_tlbivax_q); +ex1_is_wrtee_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_wrtee_offset), + scout => sov(ex1_is_wrtee_offset), + din => rf1_is_wrtee, + dout => ex1_is_wrtee_q); +ex1_is_wrteei_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_wrteei_offset), + scout => sov(ex1_is_wrteei_offset), + din => rf1_is_wrteei, + dout => ex1_is_wrteei_q); +ex1_is_mtxucr0_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_mtxucr0_offset), + scout => sov(ex1_is_mtxucr0_offset), + din => rf1_is_mtxucr0, + dout => ex1_is_mtxucr0_q); +ex1_is_tlbwe_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_tlbwe_offset), + scout => sov(ex1_is_tlbwe_offset), + din => rf1_is_tlbwe, + dout => ex1_is_tlbwe_q); +ex1_sc_lev_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_sc_lev_offset), + scout => sov(ex1_sc_lev_offset), + din => rf1_sc_lev, + dout => ex1_sc_lev_q); +ex1_ucode_val_latch : tri_rlmreg_p + generic map (width => ex1_ucode_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_ucode_val_offset to ex1_ucode_val_offset + ex1_ucode_val_q'length-1), + scout => sov(ex1_ucode_val_offset to ex1_ucode_val_offset + ex1_ucode_val_q'length-1), + din => rf1_ucode_val , + dout => ex1_ucode_val_q); +ex1_xu_val_latch : tri_rlmreg_p + generic map (width => ex1_xu_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_xu_val_offset to ex1_xu_val_offset + ex1_xu_val_q'length-1), + scout => sov(ex1_xu_val_offset to ex1_xu_val_offset + ex1_xu_val_q'length-1), + din => rf1_xu_val , + dout => ex1_xu_val_q); +ex2_axu_act_latch : tri_regk + generic map (width => ex2_axu_act_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex1_axu_act_q , + dout => ex2_axu_act_q); +ex2_any_wrtee_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_any_wrtee_d, + dout(0) => ex2_any_wrtee_q); +ex2_br_taken_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_br_taken , + dout(0) => ex2_br_taken_q); +ex2_br_update_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_br_update , + dout(0) => ex2_br_update_q); +ex2_byte_rev_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_byte_rev_q , + dout(0) => ex2_byte_rev_q); +ex2_ctr_dec_update_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_ctr_dec_update , + dout(0) => ex2_ctr_dec_update_q); +ex2_epid_instr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => dec_cpl_ex1_epid_instr , + dout(0) => ex2_epid_instr_q); +ex2_flush_latch : tri_rlmreg_p + generic map (width => ex2_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_flush_inf_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_flush_offset to ex2_flush_offset + ex2_flush_q'length-1), + scout => sov(ex2_flush_offset to ex2_flush_offset + ex2_flush_q'length-1), + din => ex1_flush , + dout => ex2_flush_q); +ex2_is_attn_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_attn_q , + dout(0) => ex2_is_attn_q); +ex2_is_dci_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_dci_q , + dout(0) => ex2_is_dci_q); +ex2_is_dlock_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_dlock_q , + dout(0) => ex2_is_dlock_q); +ex2_is_ehpriv_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_ehpriv_q , + dout(0) => ex2_is_ehpriv_q); +ex2_is_erativax_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_erativax_q , + dout(0) => ex2_is_erativax_q); +ex2_is_ici_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_ici_q , + dout(0) => ex2_is_ici_q); +ex2_is_icswx_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_icswx_q , + dout(0) => ex2_is_icswx_q); +ex2_is_ilock_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_ilock_q , + dout(0) => ex2_is_ilock_q); +ex2_is_isync_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_isync_q , + dout(0) => ex2_is_isync_q); +ex2_is_mtmsr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_mtmsr_q , + dout(0) => ex2_is_mtmsr_q); +ex2_is_rfci_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_rfci_q , + dout(0) => ex2_is_rfci_q); +ex2_is_rfgi_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_rfgi_q , + dout(0) => ex2_is_rfgi_q); +ex2_is_rfi_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_rfi_q , + dout(0) => ex2_is_rfi_q); +ex2_is_rfmci_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_rfmci_q , + dout(0) => ex2_is_rfmci_q); +ex2_is_sc_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_sc_q , + dout(0) => ex2_is_sc_q); +ex2_is_slowspr_wr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => dec_cpl_ex1_is_slowspr_wr , + dout(0) => ex2_is_slowspr_wr_q); +ex2_is_tlbivax_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_tlbivax_q , + dout(0) => ex2_is_tlbivax_q); +ex2_is_tlbwe_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_tlbwe_q , + dout(0) => ex2_is_tlbwe_q); +ex2_lr_update_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_lr_update , + dout(0) => ex2_lr_update_q); +ex2_n_align_int_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_n_align_int_d, + dout(0) => ex2_n_align_int_q); +ex2_sc_lev_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_sc_lev_q , + dout(0) => ex2_sc_lev_q); +ex2_taken_bclr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_taken_bclr , + dout(0) => ex2_taken_bclr_q); +ex2_ucode_val_latch : tri_rlmreg_p + generic map (width => ex2_ucode_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_ucode_val_offset to ex2_ucode_val_offset + ex2_ucode_val_q'length-1), + scout => sov(ex2_ucode_val_offset to ex2_ucode_val_offset + ex2_ucode_val_q'length-1), + din => ex1_ucode_val , + dout => ex2_ucode_val_q); +ex2_xu_val_latch : tri_rlmreg_p + generic map (width => ex2_xu_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_xu_val_offset to ex2_xu_val_offset + ex2_xu_val_q'length-1), + scout => sov(ex2_xu_val_offset to ex2_xu_val_offset + ex2_xu_val_q'length-1), + din => ex1_xu_val , + dout => ex2_xu_val_q); +ex2_is_mtxucr0_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_mtxucr0_q , + dout(0) => ex2_is_mtxucr0_q); +ex3_async_int_block_latch : tri_rlmreg_p + generic map (width => ex3_async_int_block_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_async_int_block_offset to ex3_async_int_block_offset + ex3_async_int_block_q'length-1), + scout => sov(ex3_async_int_block_offset to ex3_async_int_block_offset + ex3_async_int_block_q'length-1), + din => ex3_async_int_block_d, + dout => ex3_async_int_block_q); +ex3_axu_instr_match_latch : tri_rlmreg_p + generic map (width => ex3_axu_instr_match_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_axu_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_axu_instr_match_offset to ex3_axu_instr_match_offset + ex3_axu_instr_match_q'length-1), + scout => sov(ex3_axu_instr_match_offset to ex3_axu_instr_match_offset + ex3_axu_instr_match_q'length-1), + din => fu_xu_ex2_instr_match , + dout => ex3_axu_instr_match_q); +ex3_axu_instr_type_latch : tri_rlmreg_p + generic map (width => ex3_axu_instr_type_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_axu_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_axu_instr_type_offset to ex3_axu_instr_type_offset + ex3_axu_instr_type_q'length-1), + scout => sov(ex3_axu_instr_type_offset to ex3_axu_instr_type_offset + ex3_axu_instr_type_q'length-1), + din => fu_xu_ex2_instr_type , + dout => ex3_axu_instr_type_q); +ex3_axu_is_ucode_latch : tri_rlmreg_p + generic map (width => ex3_axu_is_ucode_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_axu_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_axu_is_ucode_offset to ex3_axu_is_ucode_offset + ex3_axu_is_ucode_q'length-1), + scout => sov(ex3_axu_is_ucode_offset to ex3_axu_is_ucode_offset + ex3_axu_is_ucode_q'length-1), + din => fu_xu_ex2_is_ucode , + dout => ex3_axu_is_ucode_q); +ex3_axu_val_latch : tri_rlmreg_p + generic map (width => ex3_axu_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_axu_val_offset to ex3_axu_val_offset + ex3_axu_val_q'length-1), + scout => sov(ex3_axu_val_offset to ex3_axu_val_offset + ex3_axu_val_q'length-1), + din => ex2_axu_val , + dout => ex3_axu_val_q); +ex3_br_flush_ifar_latch : tri_rlmreg_p + generic map (width => ex3_br_flush_ifar_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_br_flush_ifar_offset to ex3_br_flush_ifar_offset + ex3_br_flush_ifar_q'length-1), + scout => sov(ex3_br_flush_ifar_offset to ex3_br_flush_ifar_offset + ex3_br_flush_ifar_q'length-1), + din => ex2_br_flush_ifar , + dout => ex3_br_flush_ifar_q); +ex3_br_taken_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_br_taken_offset), + scout => sov(ex3_br_taken_offset), + din => ex2_br_taken_q , + dout => ex3_br_taken_q); +ex3_br_update_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_br_update_offset), + scout => sov(ex3_br_update_offset), + din => ex2_br_update_q , + dout => ex3_br_update_q); +ex3_byte_rev_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_byte_rev_offset), + scout => sov(ex3_byte_rev_offset), + din => ex2_byte_rev_q , + dout => ex3_byte_rev_q); +ex3_ctr_dec_update_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_ctr_dec_update_offset), + scout => sov(ex3_ctr_dec_update_offset), + din => ex2_ctr_dec_update_q , + dout => ex3_ctr_dec_update_q); +ex3_div_coll_latch : tri_rlmreg_p + generic map (width => ex3_div_coll_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_div_coll_offset to ex3_div_coll_offset + ex3_div_coll_q'length-1), + scout => sov(ex3_div_coll_offset to ex3_div_coll_offset + ex3_div_coll_q'length-1), + din => ex3_div_coll_d, + dout => ex3_div_coll_q); +ex3_epid_instr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_epid_instr_offset), + scout => sov(ex3_epid_instr_offset), + din => ex2_epid_instr_q , + dout => ex3_epid_instr_q); +ex3_flush_latch : tri_rlmreg_p + generic map (width => ex3_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_flush_inf_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_flush_offset to ex3_flush_offset + ex3_flush_q'length-1), + scout => sov(ex3_flush_offset to ex3_flush_offset + ex3_flush_q'length-1), + din => ex2_flush , + dout => ex3_flush_q); +ex3_ierat_flush_req_latch : tri_rlmreg_p + generic map (width => ex3_ierat_flush_req_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_ierat_flush_req_offset to ex3_ierat_flush_req_offset + ex3_ierat_flush_req_q'length-1), + scout => sov(ex3_ierat_flush_req_offset to ex3_ierat_flush_req_offset + ex3_ierat_flush_req_q'length-1), + din => iu_xu_ierat_ex2_flush_req , + dout => ex3_ierat_flush_req_q); +ex3_illegal_op_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_illegal_op_offset), + scout => sov(ex3_illegal_op_offset), + din => dec_cpl_ex2_illegal_op , + dout => ex3_illegal_op_q); +ex3_is_any_load_dac_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_any_load_dac_offset), + scout => sov(ex3_is_any_load_dac_offset), + din => dec_cpl_ex2_is_any_load_dac, + dout => ex3_is_any_load_dac_q); +ex3_is_any_store_dac_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_any_store_dac_offset), + scout => sov(ex3_is_any_store_dac_offset), + din => dec_cpl_ex2_is_any_store_dac, + dout => ex3_is_any_store_dac_q); +ex3_is_attn_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_attn_offset), + scout => sov(ex3_is_attn_offset), + din => ex2_is_attn_q , + dout => ex3_is_attn_q); +ex3_is_dci_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_dci_offset), + scout => sov(ex3_is_dci_offset), + din => ex2_is_dci_q , + dout => ex3_is_dci_q); +ex3_is_dlock_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_dlock_offset), + scout => sov(ex3_is_dlock_offset), + din => ex2_is_dlock_q , + dout => ex3_is_dlock_q); +ex3_is_ehpriv_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_ehpriv_offset), + scout => sov(ex3_is_ehpriv_offset), + din => ex2_is_ehpriv_q , + dout => ex3_is_ehpriv_q); +ex3_is_ici_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_ici_offset), + scout => sov(ex3_is_ici_offset), + din => ex2_is_ici_q , + dout => ex3_is_ici_q); +ex3_is_icswx_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_icswx_offset), + scout => sov(ex3_is_icswx_offset), + din => ex2_is_icswx_q , + dout => ex3_is_icswx_q); +ex3_is_ilock_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_ilock_offset), + scout => sov(ex3_is_ilock_offset), + din => ex2_is_ilock_q , + dout => ex3_is_ilock_q); +ex3_is_isync_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_isync_offset), + scout => sov(ex3_is_isync_offset), + din => ex2_is_isync_q , + dout => ex3_is_isync_q); +ex3_is_mtmsr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_mtmsr_offset), + scout => sov(ex3_is_mtmsr_offset), + din => ex2_is_mtmsr_q , + dout => ex3_is_mtmsr_q); +ex3_is_rfci_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_rfci_offset), + scout => sov(ex3_is_rfci_offset), + din => ex2_is_rfci_q , + dout => ex3_is_rfci_q); +ex3_is_rfgi_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_rfgi_offset), + scout => sov(ex3_is_rfgi_offset), + din => ex2_is_rfgi_q , + dout => ex3_is_rfgi_q); +ex3_is_rfi_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_rfi_offset), + scout => sov(ex3_is_rfi_offset), + din => ex2_is_rfi_q , + dout => ex3_is_rfi_q); +ex3_is_rfmci_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_rfmci_offset), + scout => sov(ex3_is_rfmci_offset), + din => ex2_is_rfmci_q , + dout => ex3_is_rfmci_q); +ex3_is_sc_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_sc_offset), + scout => sov(ex3_is_sc_offset), + din => ex2_is_sc_q , + dout => ex3_is_sc_q); +ex3_is_tlbwe_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_tlbwe_offset), + scout => sov(ex3_is_tlbwe_offset), + din => ex2_is_tlbwe_q , + dout => ex3_is_tlbwe_q); +ex3_is_slowspr_wr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_slowspr_wr_offset), + scout => sov(ex3_is_slowspr_wr_offset), + din => ex2_is_slowspr_wr_q , + dout => ex3_is_slowspr_wr_q); +ex3_iu_error_latch : tri_rlmreg_p + generic map (width => ex3_iu_error_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_iu_error_offset to ex3_iu_error_offset + ex3_iu_error_q'length-1), + scout => sov(ex3_iu_error_offset to ex3_iu_error_offset + ex3_iu_error_q'length-1), + din => ex3_iu_error_d, + dout => ex3_iu_error_q); +ex3_lr_update_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_lr_update_offset), + scout => sov(ex3_lr_update_offset), + din => ex2_lr_update_q , + dout => ex3_lr_update_q); +ex3_lrat_miss_latch : tri_rlmreg_p + generic map (width => ex3_lrat_miss_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_lrat_miss_offset to ex3_lrat_miss_offset + ex3_lrat_miss_q'length-1), + scout => sov(ex3_lrat_miss_offset to ex3_lrat_miss_offset + ex3_lrat_miss_q'length-1), + din => mm_xu_lrat_miss , + dout => ex3_lrat_miss_q); +ex3_mmu_esr_data_latch : tri_rlmreg_p + generic map (width => ex3_mmu_esr_data_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_mmu_esr_data_offset to ex3_mmu_esr_data_offset + ex3_mmu_esr_data_q'length-1), + scout => sov(ex3_mmu_esr_data_offset to ex3_mmu_esr_data_offset + ex3_mmu_esr_data_q'length-1), + din => mm_xu_esr_data , + dout => ex3_mmu_esr_data_q); +ex3_mmu_esr_epid_latch : tri_rlmreg_p + generic map (width => ex3_mmu_esr_epid_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_mmu_esr_epid_offset to ex3_mmu_esr_epid_offset + ex3_mmu_esr_epid_q'length-1), + scout => sov(ex3_mmu_esr_epid_offset to ex3_mmu_esr_epid_offset + ex3_mmu_esr_epid_q'length-1), + din => mm_xu_esr_epid , + dout => ex3_mmu_esr_epid_q); +ex3_mmu_esr_pt_latch : tri_rlmreg_p + generic map (width => ex3_mmu_esr_pt_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_mmu_esr_pt_offset to ex3_mmu_esr_pt_offset + ex3_mmu_esr_pt_q'length-1), + scout => sov(ex3_mmu_esr_pt_offset to ex3_mmu_esr_pt_offset + ex3_mmu_esr_pt_q'length-1), + din => mm_xu_esr_pt , + dout => ex3_mmu_esr_pt_q); +ex3_mmu_esr_st_latch : tri_rlmreg_p + generic map (width => ex3_mmu_esr_st_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_mmu_esr_st_offset to ex3_mmu_esr_st_offset + ex3_mmu_esr_st_q'length-1), + scout => sov(ex3_mmu_esr_st_offset to ex3_mmu_esr_st_offset + ex3_mmu_esr_st_q'length-1), + din => mm_xu_esr_st , + dout => ex3_mmu_esr_st_q); +ex3_mmu_hv_priv_latch : tri_rlmreg_p + generic map (width => ex3_mmu_hv_priv_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_mmu_hv_priv_offset to ex3_mmu_hv_priv_offset + ex3_mmu_hv_priv_q'length-1), + scout => sov(ex3_mmu_hv_priv_offset to ex3_mmu_hv_priv_offset + ex3_mmu_hv_priv_q'length-1), + din => mm_xu_hv_priv , + dout => ex3_mmu_hv_priv_q); +ex3_mtiar_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_mtiar_offset), + scout => sov(ex3_mtiar_offset), + din => ex2_mtiar, + dout => ex3_mtiar_q); +ex3_n_align_int_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_n_align_int_offset), + scout => sov(ex3_n_align_int_offset), + din => ex2_n_align_int_q , + dout => ex3_n_align_int_q); +ex3_n_dcpe_flush_latch : tri_rlmreg_p + generic map (width => ex3_n_dcpe_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_n_dcpe_flush_offset to ex3_n_dcpe_flush_offset + ex3_n_dcpe_flush_q'length-1), + scout => sov(ex3_n_dcpe_flush_offset to ex3_n_dcpe_flush_offset + ex3_n_dcpe_flush_q'length-1), + din => ex3_n_dcpe_flush_d, + dout => ex3_n_dcpe_flush_q); +ex3_n_l2_ecc_err_flush_latch : tri_rlmreg_p + generic map (width => ex3_n_l2_ecc_err_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_n_l2_ecc_err_flush_offset to ex3_n_l2_ecc_err_flush_offset + ex3_n_l2_ecc_err_flush_q'length-1), + scout => sov(ex3_n_l2_ecc_err_flush_offset to ex3_n_l2_ecc_err_flush_offset + ex3_n_l2_ecc_err_flush_q'length-1), + din => lsu_xu_l2_ecc_err_flush , + dout => ex3_n_l2_ecc_err_flush_q); +ex3_np1_run_ctl_flush_latch : tri_rlmreg_p + generic map (width => ex3_np1_run_ctl_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_np1_run_ctl_flush_offset to ex3_np1_run_ctl_flush_offset + ex3_np1_run_ctl_flush_q'length-1), + scout => sov(ex3_np1_run_ctl_flush_offset to ex3_np1_run_ctl_flush_offset + ex3_np1_run_ctl_flush_q'length-1), + din => spr_cpl_ex2_run_ctl_flush , + dout => ex3_np1_run_ctl_flush_q); +ex3_sc_lev_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_sc_lev_offset), + scout => sov(ex3_sc_lev_offset), + din => ex2_sc_lev_q , + dout => ex3_sc_lev_q); +ex3_taken_bclr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_taken_bclr_offset), + scout => sov(ex3_taken_bclr_offset), + din => ex2_taken_bclr_q , + dout => ex3_taken_bclr_q); +ex3_tlb_inelig_latch : tri_rlmreg_p + generic map (width => ex3_tlb_inelig_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_tlb_inelig_offset to ex3_tlb_inelig_offset + ex3_tlb_inelig_q'length-1), + scout => sov(ex3_tlb_inelig_offset to ex3_tlb_inelig_offset + ex3_tlb_inelig_q'length-1), + din => mm_xu_tlb_inelig , + dout => ex3_tlb_inelig_q); +ex3_tlb_local_snoop_reject_latch : tri_rlmreg_p + generic map (width => ex3_tlb_local_snoop_reject_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_tlb_local_snoop_reject_offset to ex3_tlb_local_snoop_reject_offset + ex3_tlb_local_snoop_reject_q'length-1), + scout => sov(ex3_tlb_local_snoop_reject_offset to ex3_tlb_local_snoop_reject_offset + ex3_tlb_local_snoop_reject_q'length-1), + din => mm_xu_local_snoop_reject , + dout => ex3_tlb_local_snoop_reject_q); +ex3_tlb_lru_par_err_latch : tri_rlmreg_p + generic map (width => ex3_tlb_lru_par_err_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_tlb_lru_par_err_offset to ex3_tlb_lru_par_err_offset + ex3_tlb_lru_par_err_q'length-1), + scout => sov(ex3_tlb_lru_par_err_offset to ex3_tlb_lru_par_err_offset + ex3_tlb_lru_par_err_q'length-1), + din => mm_xu_lru_par_err , + dout => ex3_tlb_lru_par_err_q); +ex3_tlb_illeg_latch : tri_rlmreg_p + generic map (width => ex3_tlb_illeg_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_tlb_illeg_offset to ex3_tlb_illeg_offset + ex3_tlb_illeg_q'length-1), + scout => sov(ex3_tlb_illeg_offset to ex3_tlb_illeg_offset + ex3_tlb_illeg_q'length-1), + din => mm_xu_illeg_instr , + dout => ex3_tlb_illeg_q); +ex3_tlb_miss_latch : tri_rlmreg_p + generic map (width => ex3_tlb_miss_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_tlb_miss_offset to ex3_tlb_miss_offset + ex3_tlb_miss_q'length-1), + scout => sov(ex3_tlb_miss_offset to ex3_tlb_miss_offset + ex3_tlb_miss_q'length-1), + din => mm_xu_tlb_miss , + dout => ex3_tlb_miss_q); +ex3_tlb_multihit_err_latch : tri_rlmreg_p + generic map (width => ex3_tlb_multihit_err_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_tlb_multihit_err_offset to ex3_tlb_multihit_err_offset + ex3_tlb_multihit_err_q'length-1), + scout => sov(ex3_tlb_multihit_err_offset to ex3_tlb_multihit_err_offset + ex3_tlb_multihit_err_q'length-1), + din => mm_xu_tlb_multihit_err , + dout => ex3_tlb_multihit_err_q); +ex3_tlb_par_err_latch : tri_rlmreg_p + generic map (width => ex3_tlb_par_err_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_tlb_par_err_offset to ex3_tlb_par_err_offset + ex3_tlb_par_err_q'length-1), + scout => sov(ex3_tlb_par_err_offset to ex3_tlb_par_err_offset + ex3_tlb_par_err_q'length-1), + din => mm_xu_tlb_par_err , + dout => ex3_tlb_par_err_q); +ex3_tlb_pt_fault_latch : tri_rlmreg_p + generic map (width => ex3_tlb_pt_fault_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_tlb_pt_fault_offset to ex3_tlb_pt_fault_offset + ex3_tlb_pt_fault_q'length-1), + scout => sov(ex3_tlb_pt_fault_offset to ex3_tlb_pt_fault_offset + ex3_tlb_pt_fault_q'length-1), + din => mm_xu_pt_fault , + dout => ex3_tlb_pt_fault_q); +ex3_ucode_val_latch : tri_rlmreg_p + generic map (width => ex3_ucode_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_ucode_val_offset to ex3_ucode_val_offset + ex3_ucode_val_q'length-1), + scout => sov(ex3_ucode_val_offset to ex3_ucode_val_offset + ex3_ucode_val_q'length-1), + din => ex2_ucode_val , + dout => ex3_ucode_val_q); +ex3_xu_instr_match_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_xu_instr_match_offset), + scout => sov(ex3_xu_instr_match_offset), + din => dec_cpl_ex2_match , + dout => ex3_xu_instr_match_q); +ex3_xu_is_ucode_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_xu_is_ucode_offset), + scout => sov(ex3_xu_is_ucode_offset), + din => dec_cpl_ex2_is_ucode , + dout => ex3_xu_is_ucode_q); +ex3_xu_val_latch : tri_rlmreg_p + generic map (width => ex3_xu_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_xu_val_offset to ex3_xu_val_offset + ex3_xu_val_q'length-1), + scout => sov(ex3_xu_val_offset to ex3_xu_val_offset + ex3_xu_val_q'length-1), + din => ex2_xu_val , + dout => ex3_xu_val_q); +ex3_axu_async_block_latch : tri_rlmreg_p + generic map (width => ex3_axu_async_block_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_axu_async_block_offset to ex3_axu_async_block_offset + ex3_axu_async_block_q'length-1), + scout => sov(ex3_axu_async_block_offset to ex3_axu_async_block_offset + ex3_axu_async_block_q'length-1), + din => fu_xu_ex2_async_block , + dout => ex3_axu_async_block_q); +ex3_is_mtxucr0_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_mtxucr0_offset), + scout => sov(ex3_is_mtxucr0_offset), + din => ex2_is_mtxucr0_q , + dout => ex3_is_mtxucr0_q); +ex3_np1_instr_flush_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_np1_instr_flush_offset), + scout => sov(ex3_np1_instr_flush_offset), + din => ex3_np1_instr_flush_d, + dout => ex3_np1_instr_flush_q); +ex4_apena_prog_int_latch : tri_rlmreg_p + generic map (width => ex4_apena_prog_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_apena_prog_int_offset to ex4_apena_prog_int_offset + ex4_apena_prog_int_q'length-1), + scout => sov(ex4_apena_prog_int_offset to ex4_apena_prog_int_offset + ex4_apena_prog_int_q'length-1), + din => ex3_n_apena_prog_int, + dout => ex4_apena_prog_int_q); +ex4_axu_is_ucode_latch : tri_rlmreg_p + generic map (width => ex4_axu_is_ucode_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_axu_is_ucode_offset to ex4_axu_is_ucode_offset + ex4_axu_is_ucode_q'length-1), + scout => sov(ex4_axu_is_ucode_offset to ex4_axu_is_ucode_offset + ex4_axu_is_ucode_q'length-1), + din => ex3_axu_is_ucode_q , + dout => ex4_axu_is_ucode_q); +ex4_axu_trap_latch : tri_rlmreg_p + generic map (width => ex4_axu_trap_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_axu_trap_offset to ex4_axu_trap_offset + ex4_axu_trap_q'length-1), + scout => sov(ex4_axu_trap_offset to ex4_axu_trap_offset + ex4_axu_trap_q'length-1), + din => fu_xu_ex3_trap , + dout => ex4_axu_trap_q); +ex4_axu_val_latch : tri_rlmreg_p + generic map (width => ex4_axu_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_axu_val_offset to ex4_axu_val_offset + ex4_axu_val_q'length-1), + scout => sov(ex4_axu_val_offset to ex4_axu_val_offset + ex4_axu_val_q'length-1), + din => ex3_axu_val , + dout => ex4_axu_val_q); +ex4_base_int_block_latch : tri_rlmreg_p + generic map (width => ex4_base_int_block_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_base_int_block_offset to ex4_base_int_block_offset + ex4_base_int_block_q'length-1), + scout => sov(ex4_base_int_block_offset to ex4_base_int_block_offset + ex4_base_int_block_q'length-1), + din => ex3_base_int_block , + dout => ex4_base_int_block_q); +ex4_br_flush_ifar_latch : tri_rlmreg_p + generic map (width => ex4_br_flush_ifar_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_br_flush_ifar_offset to ex4_br_flush_ifar_offset + ex4_br_flush_ifar_q'length-1), + scout => sov(ex4_br_flush_ifar_offset to ex4_br_flush_ifar_offset + ex4_br_flush_ifar_q'length-1), + din => ex3_br_flush_ifar_q , + dout => ex4_br_flush_ifar_q); +ex4_br_taken_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_br_taken_offset), + scout => sov(ex4_br_taken_offset), + din => ex3_br_taken_q , + dout => ex4_br_taken_q); +ex4_br_update_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_br_update_offset), + scout => sov(ex4_br_update_offset), + din => ex3_br_update_q , + dout => ex4_br_update_q); +ex4_byte_rev_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_byte_rev_offset), + scout => sov(ex4_byte_rev_offset), + din => ex3_byte_rev_q , + dout => ex4_byte_rev_q); +ex4_ctr_dec_update_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_ctr_dec_update_offset), + scout => sov(ex4_ctr_dec_update_offset), + din => ex3_ctr_dec_update_q , + dout => ex4_ctr_dec_update_q); +ex4_debug_flush_en_latch : tri_rlmreg_p + generic map (width => ex4_debug_flush_en_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_debug_flush_en_offset to ex4_debug_flush_en_offset + ex4_debug_flush_en_q'length-1), + scout => sov(ex4_debug_flush_en_offset to ex4_debug_flush_en_offset + ex4_debug_flush_en_q'length-1), + din => ex4_debug_flush_en_d, + dout => ex4_debug_flush_en_q); +ex4_debug_int_en_latch : tri_rlmreg_p + generic map (width => ex4_debug_int_en_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_debug_int_en_offset to ex4_debug_int_en_offset + ex4_debug_int_en_q'length-1), + scout => sov(ex4_debug_int_en_offset to ex4_debug_int_en_offset + ex4_debug_int_en_q'length-1), + din => ex3_debug_int_en, + dout => ex4_debug_int_en_q); +ex4_flush_latch : tri_rlmreg_p + generic map (width => ex4_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_flush_inf_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_flush_offset to ex4_flush_offset + ex4_flush_q'length-1), + scout => sov(ex4_flush_offset to ex4_flush_offset + ex4_flush_q'length-1), + din => ex3_flush , + dout => ex4_flush_q); +ex4_fpena_prog_int_latch : tri_rlmreg_p + generic map (width => ex4_fpena_prog_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_fpena_prog_int_offset to ex4_fpena_prog_int_offset + ex4_fpena_prog_int_q'length-1), + scout => sov(ex4_fpena_prog_int_offset to ex4_fpena_prog_int_offset + ex4_fpena_prog_int_q'length-1), + din => ex3_n_fpena_prog_int, + dout => ex4_fpena_prog_int_q); +ex4_iac1_cmpr_latch : tri_rlmreg_p + generic map (width => ex4_iac1_cmpr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_iac1_cmpr_offset to ex4_iac1_cmpr_offset + ex4_iac1_cmpr_q'length-1), + scout => sov(ex4_iac1_cmpr_offset to ex4_iac1_cmpr_offset + ex4_iac1_cmpr_q'length-1), + din => ex3_iac1_cmpr, + dout => ex4_iac1_cmpr_q); +ex4_iac2_cmpr_latch : tri_rlmreg_p + generic map (width => ex4_iac2_cmpr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_iac2_cmpr_offset to ex4_iac2_cmpr_offset + ex4_iac2_cmpr_q'length-1), + scout => sov(ex4_iac2_cmpr_offset to ex4_iac2_cmpr_offset + ex4_iac2_cmpr_q'length-1), + din => ex3_iac2_cmpr, + dout => ex4_iac2_cmpr_q); +ex4_iac3_cmpr_latch : tri_rlmreg_p + generic map (width => ex4_iac3_cmpr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_iac3_cmpr_offset to ex4_iac3_cmpr_offset + ex4_iac3_cmpr_q'length-1), + scout => sov(ex4_iac3_cmpr_offset to ex4_iac3_cmpr_offset + ex4_iac3_cmpr_q'length-1), + din => ex3_iac3_cmpr, + dout => ex4_iac3_cmpr_q); +ex4_iac4_cmpr_latch : tri_rlmreg_p + generic map (width => ex4_iac4_cmpr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_iac4_cmpr_offset to ex4_iac4_cmpr_offset + ex4_iac4_cmpr_q'length-1), + scout => sov(ex4_iac4_cmpr_offset to ex4_iac4_cmpr_offset + ex4_iac4_cmpr_q'length-1), + din => ex3_iac4_cmpr, + dout => ex4_iac4_cmpr_q); +ex4_instr_cpl_latch : tri_rlmreg_p + generic map (width => ex4_instr_cpl_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_instr_cpl_offset to ex4_instr_cpl_offset + ex4_instr_cpl_q'length-1), + scout => sov(ex4_instr_cpl_offset to ex4_instr_cpl_offset + ex4_instr_cpl_q'length-1), + din => ex4_instr_cpl_d, + dout => ex4_instr_cpl_q); +ex4_is_any_load_dac_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_is_any_load_dac_offset), + scout => sov(ex4_is_any_load_dac_offset), + din => ex3_is_any_load_dac_q , + dout => ex4_is_any_load_dac_q); +ex4_is_any_store_dac_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_is_any_store_dac_offset), + scout => sov(ex4_is_any_store_dac_offset), + din => ex3_is_any_store_dac_q , + dout => ex4_is_any_store_dac_q); +ex4_is_attn_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_is_attn_offset), + scout => sov(ex4_is_attn_offset), + din => ex3_is_attn_q , + dout => ex4_is_attn_q); +ex4_is_dci_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_is_dci_offset), + scout => sov(ex4_is_dci_offset), + din => ex3_is_dci_q , + dout => ex4_is_dci_q); +ex4_is_ehpriv_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_is_ehpriv_offset), + scout => sov(ex4_is_ehpriv_offset), + din => ex3_is_ehpriv_q , + dout => ex4_is_ehpriv_q); +ex4_is_ici_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_is_ici_offset), + scout => sov(ex4_is_ici_offset), + din => ex3_is_ici_q , + dout => ex4_is_ici_q); +ex4_is_isync_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_is_isync_offset), + scout => sov(ex4_is_isync_offset), + din => ex3_is_isync_q , + dout => ex4_is_isync_q); +ex4_is_mtmsr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_is_mtmsr_offset), + scout => sov(ex4_is_mtmsr_offset), + din => ex3_is_mtmsr_q , + dout => ex4_is_mtmsr_q); +ex4_is_tlbwe_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_is_tlbwe_offset), + scout => sov(ex4_is_tlbwe_offset), + din => ex3_is_tlbwe_q , + dout => ex4_is_tlbwe_q); +ex4_is_slowspr_wr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_is_slowspr_wr_offset), + scout => sov(ex4_is_slowspr_wr_offset), + din => ex3_is_slowspr_wr_q , + dout => ex4_is_slowspr_wr_q); +ex4_lr_update_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_lr_update_offset), + scout => sov(ex4_lr_update_offset), + din => ex3_lr_update_q , + dout => ex4_lr_update_q); +ex4_mcsr_latch : tri_rlmreg_p + generic map (width => ex4_mcsr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_mcsr_offset to ex4_mcsr_offset + ex4_mcsr_q'length-1), + scout => sov(ex4_mcsr_offset to ex4_mcsr_offset + ex4_mcsr_q'length-1), + din => ex4_mcsr_d, + dout => ex4_mcsr_q); +ex4_mem_attr_latch : tri_rlmreg_p + generic map (width => ex4_mem_attr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_mem_attr_offset to ex4_mem_attr_offset + ex4_mem_attr_q'length-1), + scout => sov(ex4_mem_attr_offset to ex4_mem_attr_offset + ex4_mem_attr_q'length-1), + din => lsu_xu_ex3_attr , + dout => ex4_mem_attr_q); +ex4_mmu_esr_data_latch : tri_rlmreg_p + generic map (width => ex4_mmu_esr_data_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_mmu_esr_data_offset to ex4_mmu_esr_data_offset + ex4_mmu_esr_data_q'length-1), + scout => sov(ex4_mmu_esr_data_offset to ex4_mmu_esr_data_offset + ex4_mmu_esr_data_q'length-1), + din => ex3_mmu_esr_data_q , + dout => ex4_mmu_esr_data_q); +ex4_mmu_esr_epid_latch : tri_rlmreg_p + generic map (width => ex4_mmu_esr_epid_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_mmu_esr_epid_offset to ex4_mmu_esr_epid_offset + ex4_mmu_esr_epid_q'length-1), + scout => sov(ex4_mmu_esr_epid_offset to ex4_mmu_esr_epid_offset + ex4_mmu_esr_epid_q'length-1), + din => ex3_mmu_esr_epid_q , + dout => ex4_mmu_esr_epid_q); +ex4_mmu_esr_pt_latch : tri_rlmreg_p + generic map (width => ex4_mmu_esr_pt_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_mmu_esr_pt_offset to ex4_mmu_esr_pt_offset + ex4_mmu_esr_pt_q'length-1), + scout => sov(ex4_mmu_esr_pt_offset to ex4_mmu_esr_pt_offset + ex4_mmu_esr_pt_q'length-1), + din => ex3_mmu_esr_pt_q , + dout => ex4_mmu_esr_pt_q); +ex4_mmu_esr_st_latch : tri_rlmreg_p + generic map (width => ex4_mmu_esr_st_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_mmu_esr_st_offset to ex4_mmu_esr_st_offset + ex4_mmu_esr_st_q'length-1), + scout => sov(ex4_mmu_esr_st_offset to ex4_mmu_esr_st_offset + ex4_mmu_esr_st_q'length-1), + din => ex3_mmu_esr_st_q , + dout => ex4_mmu_esr_st_q); +ex4_mmu_esr_val_latch : tri_rlmreg_p + generic map (width => ex4_mmu_esr_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_mmu_esr_val_offset to ex4_mmu_esr_val_offset + ex4_mmu_esr_val_q'length-1), + scout => sov(ex4_mmu_esr_val_offset to ex4_mmu_esr_val_offset + ex4_mmu_esr_val_q'length-1), + din => ex4_mmu_esr_val_d, + dout => ex4_mmu_esr_val_q); +ex4_mmu_hold_val_latch : tri_rlmreg_p + generic map (width => ex4_mmu_hold_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_mmu_hold_val_offset to ex4_mmu_hold_val_offset + ex4_mmu_hold_val_q'length-1), + scout => sov(ex4_mmu_hold_val_offset to ex4_mmu_hold_val_offset + ex4_mmu_hold_val_q'length-1), + din => ex3_mmu_hold_val, + dout => ex4_mmu_hold_val_q); +ex4_mtdp_nr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_mtdp_nr_offset), + scout => sov(ex4_mtdp_nr_offset), + din => dec_cpl_ex3_mtdp_nr , + dout => ex4_mtdp_nr_q); +ex4_mtiar_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_mtiar_offset), + scout => sov(ex4_mtiar_offset), + din => ex3_mtiar_q , + dout => ex4_mtiar_q); +ex4_n_2ucode_flush_latch : tri_rlmreg_p + generic map (width => ex4_n_2ucode_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_2ucode_flush_offset to ex4_n_2ucode_flush_offset + ex4_n_2ucode_flush_q'length-1), + scout => sov(ex4_n_2ucode_flush_offset to ex4_n_2ucode_flush_offset + ex4_n_2ucode_flush_q'length-1), + din => ex3_n_2ucode_flush, + dout => ex4_n_2ucode_flush_q); +ex4_n_align_int_latch : tri_rlmreg_p + generic map (width => ex4_n_align_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_align_int_offset to ex4_n_align_int_offset + ex4_n_align_int_q'length-1), + scout => sov(ex4_n_align_int_offset to ex4_n_align_int_offset + ex4_n_align_int_q'length-1), + din => ex3_n_align_int, + dout => ex4_n_align_int_q); +ex4_n_any_hpriv_int_latch : tri_rlmreg_p + generic map (width => ex4_n_any_hpriv_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_any_hpriv_int_offset to ex4_n_any_hpriv_int_offset + ex4_n_any_hpriv_int_q'length-1), + scout => sov(ex4_n_any_hpriv_int_offset to ex4_n_any_hpriv_int_offset + ex4_n_any_hpriv_int_q'length-1), + din => ex4_n_any_hpriv_int_d, + dout => ex4_n_any_hpriv_int_q); +ex4_n_any_unavail_int_latch : tri_rlmreg_p + generic map (width => ex4_n_any_unavail_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_any_unavail_int_offset to ex4_n_any_unavail_int_offset + ex4_n_any_unavail_int_q'length-1), + scout => sov(ex4_n_any_unavail_int_offset to ex4_n_any_unavail_int_offset + ex4_n_any_unavail_int_q'length-1), + din => ex3_n_any_unavail_int, + dout => ex4_n_any_unavail_int_q); +ex4_n_ap_unavail_int_latch : tri_rlmreg_p + generic map (width => ex4_n_ap_unavail_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_ap_unavail_int_offset to ex4_n_ap_unavail_int_offset + ex4_n_ap_unavail_int_q'length-1), + scout => sov(ex4_n_ap_unavail_int_offset to ex4_n_ap_unavail_int_offset + ex4_n_ap_unavail_int_q'length-1), + din => ex3_n_ap_unavail_int, + dout => ex4_n_ap_unavail_int_q); +ex4_n_barr_flush_latch : tri_rlmreg_p + generic map (width => ex4_n_barr_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_barr_flush_offset to ex4_n_barr_flush_offset + ex4_n_barr_flush_q'length-1), + scout => sov(ex4_n_barr_flush_offset to ex4_n_barr_flush_offset + ex4_n_barr_flush_q'length-1), + din => ex3_n_barr_flush, + dout => ex4_n_barr_flush_q); +ex4_n_bclr_ta_miscmpr_flush_latch : tri_rlmreg_p + generic map (width => ex4_n_bclr_ta_miscmpr_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_bclr_ta_miscmpr_flush_offset to ex4_n_bclr_ta_miscmpr_flush_offset + ex4_n_bclr_ta_miscmpr_flush_q'length-1), + scout => sov(ex4_n_bclr_ta_miscmpr_flush_offset to ex4_n_bclr_ta_miscmpr_flush_offset + ex4_n_bclr_ta_miscmpr_flush_q'length-1), + din => ex3_n_bclr_ta_miscmpr_flush, + dout => ex4_n_bclr_ta_miscmpr_flush_q); +ex4_n_brt_dbg_cint_latch : tri_rlmreg_p + generic map (width => ex4_n_brt_dbg_cint_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_brt_dbg_cint_offset to ex4_n_brt_dbg_cint_offset + ex4_n_brt_dbg_cint_q'length-1), + scout => sov(ex4_n_brt_dbg_cint_offset to ex4_n_brt_dbg_cint_offset + ex4_n_brt_dbg_cint_q'length-1), + din => ex3_n_brt_dbg_cint, + dout => ex4_n_brt_dbg_cint_q); +ex4_n_dac_dbg_cint_latch : tri_rlmreg_p + generic map (width => ex4_n_dac_dbg_cint_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_dac_dbg_cint_offset to ex4_n_dac_dbg_cint_offset + ex4_n_dac_dbg_cint_q'length-1), + scout => sov(ex4_n_dac_dbg_cint_offset to ex4_n_dac_dbg_cint_offset + ex4_n_dac_dbg_cint_q'length-1), + din => ex3_n_dac_dbg_cint, + dout => ex4_n_dac_dbg_cint_q); +ex4_n_ddmh_mchk_en_latch : tri_rlmreg_p + generic map (width => ex4_n_ddmh_mchk_en_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_ddmh_mchk_en_offset to ex4_n_ddmh_mchk_en_offset + ex4_n_ddmh_mchk_en_q'length-1), + scout => sov(ex4_n_ddmh_mchk_en_offset to ex4_n_ddmh_mchk_en_offset + ex4_n_ddmh_mchk_en_q'length-1), + din => ex4_n_ddmh_mchk_en_d, + dout => ex4_n_ddmh_mchk_en_q); +ex4_n_dep_flush_latch : tri_rlmreg_p + generic map (width => ex4_n_dep_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_dep_flush_offset to ex4_n_dep_flush_offset + ex4_n_dep_flush_q'length-1), + scout => sov(ex4_n_dep_flush_offset to ex4_n_dep_flush_offset + ex4_n_dep_flush_q'length-1), + din => ex3_n_dep_flush, + dout => ex4_n_dep_flush_q); +ex4_n_deratre_par_mchk_mcint_latch : tri_rlmreg_p + generic map (width => ex4_n_deratre_par_mchk_mcint_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_deratre_par_mchk_mcint_offset to ex4_n_deratre_par_mchk_mcint_offset + ex4_n_deratre_par_mchk_mcint_q'length-1), + scout => sov(ex4_n_deratre_par_mchk_mcint_offset to ex4_n_deratre_par_mchk_mcint_offset + ex4_n_deratre_par_mchk_mcint_q'length-1), + din => ex3_n_deratre_par_mchk_mcint, + dout => ex4_n_deratre_par_mchk_mcint_q); +ex4_n_dlk0_dstor_int_latch : tri_rlmreg_p + generic map (width => ex4_n_dlk0_dstor_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_dlk0_dstor_int_offset to ex4_n_dlk0_dstor_int_offset + ex4_n_dlk0_dstor_int_q'length-1), + scout => sov(ex4_n_dlk0_dstor_int_offset to ex4_n_dlk0_dstor_int_offset + ex4_n_dlk0_dstor_int_q'length-1), + din => ex3_n_dlk0_dstor_int, + dout => ex4_n_dlk0_dstor_int_q); +ex4_n_dlk1_dstor_int_latch : tri_rlmreg_p + generic map (width => ex4_n_dlk1_dstor_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_dlk1_dstor_int_offset to ex4_n_dlk1_dstor_int_offset + ex4_n_dlk1_dstor_int_q'length-1), + scout => sov(ex4_n_dlk1_dstor_int_offset to ex4_n_dlk1_dstor_int_offset + ex4_n_dlk1_dstor_int_q'length-1), + din => ex3_n_dlk1_dstor_int, + dout => ex4_n_dlk1_dstor_int_q); +ex4_n_dlrat_int_latch : tri_rlmreg_p + generic map (width => ex4_n_dlrat_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_dlrat_int_offset to ex4_n_dlrat_int_offset + ex4_n_dlrat_int_q'length-1), + scout => sov(ex4_n_dlrat_int_offset to ex4_n_dlrat_int_offset + ex4_n_dlrat_int_q'length-1), + din => ex3_n_dlrat_int, + dout => ex4_n_dlrat_int_q); +ex4_n_dmchk_mcint_latch : tri_rlmreg_p + generic map (width => ex4_n_dmchk_mcint_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_dmchk_mcint_offset to ex4_n_dmchk_mcint_offset + ex4_n_dmchk_mcint_q'length-1), + scout => sov(ex4_n_dmchk_mcint_offset to ex4_n_dmchk_mcint_offset + ex4_n_dmchk_mcint_q'length-1), + din => ex3_n_dmchk_mcint, + dout => ex4_n_dmchk_mcint_q); +ex4_n_dmiss_flush_latch : tri_rlmreg_p + generic map (width => ex4_n_dmiss_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_dmiss_flush_offset to ex4_n_dmiss_flush_offset + ex4_n_dmiss_flush_q'length-1), + scout => sov(ex4_n_dmiss_flush_offset to ex4_n_dmiss_flush_offset + ex4_n_dmiss_flush_q'length-1), + din => ex3_n_dmiss_flush, + dout => ex4_n_dmiss_flush_q); +ex4_n_dstor_int_latch : tri_rlmreg_p + generic map (width => ex4_n_dstor_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_dstor_int_offset to ex4_n_dstor_int_offset + ex4_n_dstor_int_q'length-1), + scout => sov(ex4_n_dstor_int_offset to ex4_n_dstor_int_offset + ex4_n_dstor_int_q'length-1), + din => ex3_n_dstor_int, + dout => ex4_n_dstor_int_q); +ex4_n_dtlb_int_latch : tri_rlmreg_p + generic map (width => ex4_n_dtlb_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_dtlb_int_offset to ex4_n_dtlb_int_offset + ex4_n_dtlb_int_q'length-1), + scout => sov(ex4_n_dtlb_int_offset to ex4_n_dtlb_int_offset + ex4_n_dtlb_int_q'length-1), + din => ex3_n_dtlb_int, + dout => ex4_n_dtlb_int_q); +ex4_n_ena_prog_int_latch : tri_rlmreg_p + generic map (width => ex4_n_ena_prog_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_ena_prog_int_offset to ex4_n_ena_prog_int_offset + ex4_n_ena_prog_int_q'length-1), + scout => sov(ex4_n_ena_prog_int_offset to ex4_n_ena_prog_int_offset + ex4_n_ena_prog_int_q'length-1), + din => ex3_n_ena_prog_int, + dout => ex4_n_ena_prog_int_q); +ex4_n_flush_latch : tri_rlmreg_p + generic map (width => ex4_n_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_flush_offset to ex4_n_flush_offset + ex4_n_flush_q'length-1), + scout => sov(ex4_n_flush_offset to ex4_n_flush_offset + ex4_n_flush_q'length-1), + din => ex3_n_flush, + dout => ex4_n_flush_q); +ex4_n_pe_flush_latch : tri_rlmreg_p + generic map (width => ex4_n_pe_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_pe_flush_offset to ex4_n_pe_flush_offset + ex4_n_pe_flush_q'length-1), + scout => sov(ex4_n_pe_flush_offset to ex4_n_pe_flush_offset + ex4_n_pe_flush_q'length-1), + din => ex3_n_pe_flush, + dout => ex4_n_pe_flush_q); +ex4_n_tlb_mchk_flush_latch : tri_rlmreg_p + generic map (width => ex4_n_tlb_mchk_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_tlb_mchk_flush_offset to ex4_n_tlb_mchk_flush_offset + ex4_n_tlb_mchk_flush_q'length-1), + scout => sov(ex4_n_tlb_mchk_flush_offset to ex4_n_tlb_mchk_flush_offset + ex4_n_tlb_mchk_flush_q'length-1), + din => ex3_n_tlb_mchk_flush, + dout => ex4_n_tlb_mchk_flush_q); +ex4_n_fp_unavail_int_latch : tri_rlmreg_p + generic map (width => ex4_n_fp_unavail_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_fp_unavail_int_offset to ex4_n_fp_unavail_int_offset + ex4_n_fp_unavail_int_q'length-1), + scout => sov(ex4_n_fp_unavail_int_offset to ex4_n_fp_unavail_int_offset + ex4_n_fp_unavail_int_q'length-1), + din => ex3_n_fp_unavail_int, + dout => ex4_n_fp_unavail_int_q); +ex4_n_fu_rfpe_flush_latch : tri_rlmreg_p + generic map (width => ex4_n_fu_rfpe_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_fu_rfpe_flush_offset to ex4_n_fu_rfpe_flush_offset + ex4_n_fu_rfpe_flush_q'length-1), + scout => sov(ex4_n_fu_rfpe_flush_offset to ex4_n_fu_rfpe_flush_offset + ex4_n_fu_rfpe_flush_q'length-1), + din => ex4_n_fu_rfpe_flush_d, + dout => ex4_n_fu_rfpe_flush_q); +ex4_n_iac_dbg_cint_latch : tri_rlmreg_p + generic map (width => ex4_n_iac_dbg_cint_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_iac_dbg_cint_offset to ex4_n_iac_dbg_cint_offset + ex4_n_iac_dbg_cint_q'length-1), + scout => sov(ex4_n_iac_dbg_cint_offset to ex4_n_iac_dbg_cint_offset + ex4_n_iac_dbg_cint_q'length-1), + din => ex3_n_iac_dbg_cint, + dout => ex4_n_iac_dbg_cint_q); +ex4_n_ieratre_par_mchk_mcint_latch : tri_rlmreg_p + generic map (width => ex4_n_ieratre_par_mchk_mcint_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_ieratre_par_mchk_mcint_offset to ex4_n_ieratre_par_mchk_mcint_offset + ex4_n_ieratre_par_mchk_mcint_q'length-1), + scout => sov(ex4_n_ieratre_par_mchk_mcint_offset to ex4_n_ieratre_par_mchk_mcint_offset + ex4_n_ieratre_par_mchk_mcint_q'length-1), + din => ex3_n_ieratre_par_mchk_mcint, + dout => ex4_n_ieratre_par_mchk_mcint_q); +ex4_n_ilrat_int_latch : tri_rlmreg_p + generic map (width => ex4_n_ilrat_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_ilrat_int_offset to ex4_n_ilrat_int_offset + ex4_n_ilrat_int_q'length-1), + scout => sov(ex4_n_ilrat_int_offset to ex4_n_ilrat_int_offset + ex4_n_ilrat_int_q'length-1), + din => ex3_n_ilrat_int, + dout => ex4_n_ilrat_int_q); +ex4_n_imchk_mcint_latch : tri_rlmreg_p + generic map (width => ex4_n_imchk_mcint_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_imchk_mcint_offset to ex4_n_imchk_mcint_offset + ex4_n_imchk_mcint_q'length-1), + scout => sov(ex4_n_imchk_mcint_offset to ex4_n_imchk_mcint_offset + ex4_n_imchk_mcint_q'length-1), + din => ex3_n_imchk_mcint, + dout => ex4_n_imchk_mcint_q); +ex4_n_imiss_flush_latch : tri_rlmreg_p + generic map (width => ex4_n_imiss_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_imiss_flush_offset to ex4_n_imiss_flush_offset + ex4_n_imiss_flush_q'length-1), + scout => sov(ex4_n_imiss_flush_offset to ex4_n_imiss_flush_offset + ex4_n_imiss_flush_q'length-1), + din => ex3_n_imiss_flush, + dout => ex4_n_imiss_flush_q); +ex4_n_instr_dbg_cint_latch : tri_rlmreg_p + generic map (width => ex4_n_instr_dbg_cint_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_instr_dbg_cint_offset to ex4_n_instr_dbg_cint_offset + ex4_n_instr_dbg_cint_q'length-1), + scout => sov(ex4_n_instr_dbg_cint_offset to ex4_n_instr_dbg_cint_offset + ex4_n_instr_dbg_cint_q'length-1), + din => ex3_n_instr_dbg_cint, + dout => ex4_n_instr_dbg_cint_q); +ex4_n_istor_int_latch : tri_rlmreg_p + generic map (width => ex4_n_istor_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_istor_int_offset to ex4_n_istor_int_offset + ex4_n_istor_int_q'length-1), + scout => sov(ex4_n_istor_int_offset to ex4_n_istor_int_offset + ex4_n_istor_int_q'length-1), + din => ex3_n_istor_int, + dout => ex4_n_istor_int_q); +ex4_n_itlb_int_latch : tri_rlmreg_p + generic map (width => ex4_n_itlb_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_itlb_int_offset to ex4_n_itlb_int_offset + ex4_n_itlb_int_q'length-1), + scout => sov(ex4_n_itlb_int_offset to ex4_n_itlb_int_offset + ex4_n_itlb_int_q'length-1), + din => ex3_n_itlb_int, + dout => ex4_n_itlb_int_q); +ex4_n_ivc_dbg_cint_latch : tri_rlmreg_p + generic map (width => ex4_n_ivc_dbg_cint_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_ivc_dbg_cint_offset to ex4_n_ivc_dbg_cint_offset + ex4_n_ivc_dbg_cint_q'length-1), + scout => sov(ex4_n_ivc_dbg_cint_offset to ex4_n_ivc_dbg_cint_offset + ex4_n_ivc_dbg_cint_q'length-1), + din => ex3_n_ivc_dbg_cint, + dout => ex4_n_ivc_dbg_cint_q); +ex4_n_ivc_dbg_match_latch : tri_rlmreg_p + generic map (width => ex4_n_ivc_dbg_match_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_ivc_dbg_match_offset to ex4_n_ivc_dbg_match_offset + ex4_n_ivc_dbg_match_q'length-1), + scout => sov(ex4_n_ivc_dbg_match_offset to ex4_n_ivc_dbg_match_offset + ex4_n_ivc_dbg_match_q'length-1), + din => ex3_n_ivc_dbg_match, + dout => ex4_n_ivc_dbg_match_q); +ex4_n_ldq_hit_flush_latch : tri_rlmreg_p + generic map (width => ex4_n_ldq_hit_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_ldq_hit_flush_offset to ex4_n_ldq_hit_flush_offset + ex4_n_ldq_hit_flush_q'length-1), + scout => sov(ex4_n_ldq_hit_flush_offset to ex4_n_ldq_hit_flush_offset + ex4_n_ldq_hit_flush_q'length-1), + din => ex3_n_ldq_hit_flush, + dout => ex4_n_ldq_hit_flush_q); +ex4_n_lsu_ddmh_flush_en_latch : tri_rlmreg_p + generic map (width => ex4_n_lsu_ddmh_flush_en_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_lsu_ddmh_flush_en_offset to ex4_n_lsu_ddmh_flush_en_offset + ex4_n_lsu_ddmh_flush_en_q'length-1), + scout => sov(ex4_n_lsu_ddmh_flush_en_offset to ex4_n_lsu_ddmh_flush_en_offset + ex4_n_lsu_ddmh_flush_en_q'length-1), + din => ex4_n_lsu_ddmh_flush_en_d, + dout => ex4_n_lsu_ddmh_flush_en_q); +ex4_n_lsu_flush_latch : tri_rlmreg_p + generic map (width => ex4_n_lsu_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_lsu_flush_offset to ex4_n_lsu_flush_offset + ex4_n_lsu_flush_q'length-1), + scout => sov(ex4_n_lsu_flush_offset to ex4_n_lsu_flush_offset + ex4_n_lsu_flush_q'length-1), + din => ex3_n_lsu_flush, + dout => ex4_n_lsu_flush_q); +ex4_n_memattr_miscmpr_flush_latch : tri_rlmreg_p + generic map (width => ex4_n_memattr_miscmpr_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_memattr_miscmpr_flush_offset to ex4_n_memattr_miscmpr_flush_offset + ex4_n_memattr_miscmpr_flush_q'length-1), + scout => sov(ex4_n_memattr_miscmpr_flush_offset to ex4_n_memattr_miscmpr_flush_offset + ex4_n_memattr_miscmpr_flush_q'length-1), + din => ex3_n_memattr_miscmpr_flush, + dout => ex4_n_memattr_miscmpr_flush_q); +ex4_n_mmu_hpriv_int_latch : tri_rlmreg_p + generic map (width => ex4_n_mmu_hpriv_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_mmu_hpriv_int_offset to ex4_n_mmu_hpriv_int_offset + ex4_n_mmu_hpriv_int_q'length-1), + scout => sov(ex4_n_mmu_hpriv_int_offset to ex4_n_mmu_hpriv_int_offset + ex4_n_mmu_hpriv_int_q'length-1), + din => ex3_n_mmu_hpriv_int, + dout => ex4_n_mmu_hpriv_int_q); +ex4_n_pil_prog_int_latch : tri_rlmreg_p + generic map (width => ex4_n_pil_prog_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_pil_prog_int_offset to ex4_n_pil_prog_int_offset + ex4_n_pil_prog_int_q'length-1), + scout => sov(ex4_n_pil_prog_int_offset to ex4_n_pil_prog_int_offset + ex4_n_pil_prog_int_q'length-1), + din => ex3_n_pil_prog_int, + dout => ex4_n_pil_prog_int_q); +ex4_n_ppr_prog_int_latch : tri_rlmreg_p + generic map (width => ex4_n_ppr_prog_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_ppr_prog_int_offset to ex4_n_ppr_prog_int_offset + ex4_n_ppr_prog_int_q'length-1), + scout => sov(ex4_n_ppr_prog_int_offset to ex4_n_ppr_prog_int_offset + ex4_n_ppr_prog_int_q'length-1), + din => ex3_n_ppr_prog_int, + dout => ex4_n_ppr_prog_int_q); +ex4_n_ptemiss_dlrat_int_latch : tri_rlmreg_p + generic map (width => ex4_n_ptemiss_dlrat_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_ptemiss_dlrat_int_offset to ex4_n_ptemiss_dlrat_int_offset + ex4_n_ptemiss_dlrat_int_q'length-1), + scout => sov(ex4_n_ptemiss_dlrat_int_offset to ex4_n_ptemiss_dlrat_int_offset + ex4_n_ptemiss_dlrat_int_q'length-1), + din => ex3_n_ptemiss_dlrat_int, + dout => ex4_n_ptemiss_dlrat_int_q); +ex4_n_puo_prog_int_latch : tri_rlmreg_p + generic map (width => ex4_n_puo_prog_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_puo_prog_int_offset to ex4_n_puo_prog_int_offset + ex4_n_puo_prog_int_q'length-1), + scout => sov(ex4_n_puo_prog_int_offset to ex4_n_puo_prog_int_offset + ex4_n_puo_prog_int_q'length-1), + din => ex3_n_puo_prog_int, + dout => ex4_n_puo_prog_int_q); +ex4_n_ret_dbg_cint_latch : tri_rlmreg_p + generic map (width => ex4_n_ret_dbg_cint_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_ret_dbg_cint_offset to ex4_n_ret_dbg_cint_offset + ex4_n_ret_dbg_cint_q'length-1), + scout => sov(ex4_n_ret_dbg_cint_offset to ex4_n_ret_dbg_cint_offset + ex4_n_ret_dbg_cint_q'length-1), + din => ex3_n_ret_dbg_cint, + dout => ex4_n_ret_dbg_cint_q); +ex4_n_thrctl_stop_flush_latch : tri_rlmreg_p + generic map (width => ex4_n_thrctl_stop_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_thrctl_stop_flush_offset to ex4_n_thrctl_stop_flush_offset + ex4_n_thrctl_stop_flush_q'length-1), + scout => sov(ex4_n_thrctl_stop_flush_offset to ex4_n_thrctl_stop_flush_offset + ex4_n_thrctl_stop_flush_q'length-1), + din => ex3_n_thrctl_stop_flush, + dout => ex4_n_thrctl_stop_flush_q); +ex4_n_tlbwemiss_dlrat_int_latch : tri_rlmreg_p + generic map (width => ex4_n_tlbwemiss_dlrat_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_tlbwemiss_dlrat_int_offset to ex4_n_tlbwemiss_dlrat_int_offset + ex4_n_tlbwemiss_dlrat_int_q'length-1), + scout => sov(ex4_n_tlbwemiss_dlrat_int_offset to ex4_n_tlbwemiss_dlrat_int_offset + ex4_n_tlbwemiss_dlrat_int_q'length-1), + din => ex3_n_tlbwemiss_dlrat_int, + dout => ex4_n_tlbwemiss_dlrat_int_q); +ex4_n_tlbwe_pil_prog_int_latch : tri_rlmreg_p + generic map (width => ex4_n_tlbwe_pil_prog_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_tlbwe_pil_prog_int_offset to ex4_n_tlbwe_pil_prog_int_offset + ex4_n_tlbwe_pil_prog_int_q'length-1), + scout => sov(ex4_n_tlbwe_pil_prog_int_offset to ex4_n_tlbwe_pil_prog_int_offset + ex4_n_tlbwe_pil_prog_int_q'length-1), + din => ex3_n_tlbwe_pil_prog_int, + dout => ex4_n_tlbwe_pil_prog_int_q); +ex4_n_trap_dbg_cint_latch : tri_rlmreg_p + generic map (width => ex4_n_trap_dbg_cint_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_trap_dbg_cint_offset to ex4_n_trap_dbg_cint_offset + ex4_n_trap_dbg_cint_q'length-1), + scout => sov(ex4_n_trap_dbg_cint_offset to ex4_n_trap_dbg_cint_offset + ex4_n_trap_dbg_cint_q'length-1), + din => ex3_n_trap_dbg_cint, + dout => ex4_n_trap_dbg_cint_q); +ex4_n_uct_dstor_int_latch : tri_rlmreg_p + generic map (width => ex4_n_uct_dstor_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_uct_dstor_int_offset to ex4_n_uct_dstor_int_offset + ex4_n_uct_dstor_int_q'length-1), + scout => sov(ex4_n_uct_dstor_int_offset to ex4_n_uct_dstor_int_offset + ex4_n_uct_dstor_int_q'length-1), + din => ex3_n_uct_dstor_int, + dout => ex4_n_uct_dstor_int_q); +ex4_n_vec_unavail_int_latch : tri_rlmreg_p + generic map (width => ex4_n_vec_unavail_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_vec_unavail_int_offset to ex4_n_vec_unavail_int_offset + ex4_n_vec_unavail_int_q'length-1), + scout => sov(ex4_n_vec_unavail_int_offset to ex4_n_vec_unavail_int_offset + ex4_n_vec_unavail_int_q'length-1), + din => ex3_n_vec_unavail_int, + dout => ex4_n_vec_unavail_int_q); +ex4_n_vf_dstor_int_latch : tri_rlmreg_p + generic map (width => ex4_n_vf_dstor_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_vf_dstor_int_offset to ex4_n_vf_dstor_int_offset + ex4_n_vf_dstor_int_q'length-1), + scout => sov(ex4_n_vf_dstor_int_offset to ex4_n_vf_dstor_int_offset + ex4_n_vf_dstor_int_q'length-1), + din => ex3_n_vf_dstor_int, + dout => ex4_n_vf_dstor_int_q); +ex4_n_xu_rfpe_flush_latch : tri_rlmreg_p + generic map (width => ex4_n_xu_rfpe_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_xu_rfpe_flush_offset to ex4_n_xu_rfpe_flush_offset + ex4_n_xu_rfpe_flush_q'length-1), + scout => sov(ex4_n_xu_rfpe_flush_offset to ex4_n_xu_rfpe_flush_offset + ex4_n_xu_rfpe_flush_q'length-1), + din => ex4_n_xu_rfpe_flush_d, + dout => ex4_n_xu_rfpe_flush_q); +ex4_np1_cdbell_cint_latch : tri_rlmreg_p + generic map (width => ex4_np1_cdbell_cint_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_np1_cdbell_cint_offset to ex4_np1_cdbell_cint_offset + ex4_np1_cdbell_cint_q'length-1), + scout => sov(ex4_np1_cdbell_cint_offset to ex4_np1_cdbell_cint_offset + ex4_np1_cdbell_cint_q'length-1), + din => ex3_np1_cdbell_cint, + dout => ex4_np1_cdbell_cint_q); +ex4_np1_crit_cint_latch : tri_rlmreg_p + generic map (width => ex4_np1_crit_cint_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_np1_crit_cint_offset to ex4_np1_crit_cint_offset + ex4_np1_crit_cint_q'length-1), + scout => sov(ex4_np1_crit_cint_offset to ex4_np1_crit_cint_offset + ex4_np1_crit_cint_q'length-1), + din => ex3_np1_crit_cint, + dout => ex4_np1_crit_cint_q); +ex4_np1_dbell_int_latch : tri_rlmreg_p + generic map (width => ex4_np1_dbell_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_np1_dbell_int_offset to ex4_np1_dbell_int_offset + ex4_np1_dbell_int_q'length-1), + scout => sov(ex4_np1_dbell_int_offset to ex4_np1_dbell_int_offset + ex4_np1_dbell_int_q'length-1), + din => ex3_np1_dbell_int, + dout => ex4_np1_dbell_int_q); +ex4_np1_dec_int_latch : tri_rlmreg_p + generic map (width => ex4_np1_dec_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_np1_dec_int_offset to ex4_np1_dec_int_offset + ex4_np1_dec_int_q'length-1), + scout => sov(ex4_np1_dec_int_offset to ex4_np1_dec_int_offset + ex4_np1_dec_int_q'length-1), + din => ex3_np1_dec_int, + dout => ex4_np1_dec_int_q); +ex4_np1_ext_int_latch : tri_rlmreg_p + generic map (width => ex4_np1_ext_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_np1_ext_int_offset to ex4_np1_ext_int_offset + ex4_np1_ext_int_q'length-1), + scout => sov(ex4_np1_ext_int_offset to ex4_np1_ext_int_offset + ex4_np1_ext_int_q'length-1), + din => ex3_np1_ext_int, + dout => ex4_np1_ext_int_q); +ex4_np1_ext_mchk_mcint_latch : tri_rlmreg_p + generic map (width => ex4_np1_ext_mchk_mcint_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_np1_ext_mchk_mcint_offset to ex4_np1_ext_mchk_mcint_offset + ex4_np1_ext_mchk_mcint_q'length-1), + scout => sov(ex4_np1_ext_mchk_mcint_offset to ex4_np1_ext_mchk_mcint_offset + ex4_np1_ext_mchk_mcint_q'length-1), + din => ex3_np1_ext_mchk_mcint, + dout => ex4_np1_ext_mchk_mcint_q); +ex4_np1_fit_int_latch : tri_rlmreg_p + generic map (width => ex4_np1_fit_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_np1_fit_int_offset to ex4_np1_fit_int_offset + ex4_np1_fit_int_q'length-1), + scout => sov(ex4_np1_fit_int_offset to ex4_np1_fit_int_offset + ex4_np1_fit_int_q'length-1), + din => ex3_np1_fit_int, + dout => ex4_np1_fit_int_q); +ex4_np1_flush_latch : tri_rlmreg_p + generic map (width => ex4_np1_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_np1_flush_offset to ex4_np1_flush_offset + ex4_np1_flush_q'length-1), + scout => sov(ex4_np1_flush_offset to ex4_np1_flush_offset + ex4_np1_flush_q'length-1), + din => ex3_np1_flush, + dout => ex4_np1_flush_q); +ex4_np1_gcdbell_cint_latch : tri_rlmreg_p + generic map (width => ex4_np1_gcdbell_cint_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_np1_gcdbell_cint_offset to ex4_np1_gcdbell_cint_offset + ex4_np1_gcdbell_cint_q'length-1), + scout => sov(ex4_np1_gcdbell_cint_offset to ex4_np1_gcdbell_cint_offset + ex4_np1_gcdbell_cint_q'length-1), + din => ex3_np1_gcdbell_cint, + dout => ex4_np1_gcdbell_cint_q); +ex4_np1_gdbell_int_latch : tri_rlmreg_p + generic map (width => ex4_np1_gdbell_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_np1_gdbell_int_offset to ex4_np1_gdbell_int_offset + ex4_np1_gdbell_int_q'length-1), + scout => sov(ex4_np1_gdbell_int_offset to ex4_np1_gdbell_int_offset + ex4_np1_gdbell_int_q'length-1), + din => ex3_np1_gdbell_int, + dout => ex4_np1_gdbell_int_q); +ex4_np1_gmcdbell_cint_latch : tri_rlmreg_p + generic map (width => ex4_np1_gmcdbell_cint_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_np1_gmcdbell_cint_offset to ex4_np1_gmcdbell_cint_offset + ex4_np1_gmcdbell_cint_q'length-1), + scout => sov(ex4_np1_gmcdbell_cint_offset to ex4_np1_gmcdbell_cint_offset + ex4_np1_gmcdbell_cint_q'length-1), + din => ex3_np1_gmcdbell_cint, + dout => ex4_np1_gmcdbell_cint_q); +ex4_np1_ide_dbg_cint_latch : tri_rlmreg_p + generic map (width => ex4_np1_ide_dbg_cint_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_np1_ide_dbg_cint_offset to ex4_np1_ide_dbg_cint_offset + ex4_np1_ide_dbg_cint_q'length-1), + scout => sov(ex4_np1_ide_dbg_cint_offset to ex4_np1_ide_dbg_cint_offset + ex4_np1_ide_dbg_cint_q'length-1), + din => ex3_np1_ide_dbg_cint, + dout => ex4_np1_ide_dbg_cint_q); +ex4_np1_instr_int_latch : tri_rlmreg_p + generic map (width => ex4_np1_instr_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_np1_instr_int_offset to ex4_np1_instr_int_offset + ex4_np1_instr_int_q'length-1), + scout => sov(ex4_np1_instr_int_offset to ex4_np1_instr_int_offset + ex4_np1_instr_int_q'length-1), + din => ex3_np1_instr_int, + dout => ex4_np1_instr_int_q); +ex4_np1_perf_int_latch : tri_rlmreg_p + generic map (width => ex4_np1_perf_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_np1_perf_int_offset to ex4_np1_perf_int_offset + ex4_np1_perf_int_q'length-1), + scout => sov(ex4_np1_perf_int_offset to ex4_np1_perf_int_offset + ex4_np1_perf_int_q'length-1), + din => ex3_np1_perf_int, + dout => ex4_np1_perf_int_q); +ex4_np1_ptr_prog_int_latch : tri_rlmreg_p + generic map (width => ex4_np1_ptr_prog_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_np1_ptr_prog_int_offset to ex4_np1_ptr_prog_int_offset + ex4_np1_ptr_prog_int_q'length-1), + scout => sov(ex4_np1_ptr_prog_int_offset to ex4_np1_ptr_prog_int_offset + ex4_np1_ptr_prog_int_q'length-1), + din => ex3_np1_ptr_prog_int, + dout => ex4_np1_ptr_prog_int_q); +ex4_np1_rfi_latch : tri_rlmreg_p + generic map (width => ex4_np1_rfi_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_np1_rfi_offset to ex4_np1_rfi_offset + ex4_np1_rfi_q'length-1), + scout => sov(ex4_np1_rfi_offset to ex4_np1_rfi_offset + ex4_np1_rfi_q'length-1), + din => ex3_np1_rfi, + dout => ex4_np1_rfi_q); +ex4_np1_run_ctl_flush_latch : tri_rlmreg_p + generic map (width => ex4_np1_run_ctl_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_np1_run_ctl_flush_offset to ex4_np1_run_ctl_flush_offset + ex4_np1_run_ctl_flush_q'length-1), + scout => sov(ex4_np1_run_ctl_flush_offset to ex4_np1_run_ctl_flush_offset + ex4_np1_run_ctl_flush_q'length-1), + din => ex3_np1_run_ctl_flush, + dout => ex4_np1_run_ctl_flush_q); +ex4_np1_sc_int_latch : tri_rlmreg_p + generic map (width => ex4_np1_sc_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_np1_sc_int_offset to ex4_np1_sc_int_offset + ex4_np1_sc_int_q'length-1), + scout => sov(ex4_np1_sc_int_offset to ex4_np1_sc_int_offset + ex4_np1_sc_int_q'length-1), + din => ex3_np1_sc_int, + dout => ex4_np1_sc_int_q); +ex4_np1_ude_dbg_cint_latch : tri_rlmreg_p + generic map (width => ex4_np1_ude_dbg_cint_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_np1_ude_dbg_cint_offset to ex4_np1_ude_dbg_cint_offset + ex4_np1_ude_dbg_cint_q'length-1), + scout => sov(ex4_np1_ude_dbg_cint_offset to ex4_np1_ude_dbg_cint_offset + ex4_np1_ude_dbg_cint_q'length-1), + din => ex3_np1_ude_dbg_cint, + dout => ex4_np1_ude_dbg_cint_q); +ex4_np1_ude_dbg_event_latch : tri_rlmreg_p + generic map (width => ex4_np1_ude_dbg_event_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_np1_ude_dbg_event_offset to ex4_np1_ude_dbg_event_offset + ex4_np1_ude_dbg_event_q'length-1), + scout => sov(ex4_np1_ude_dbg_event_offset to ex4_np1_ude_dbg_event_offset + ex4_np1_ude_dbg_event_q'length-1), + din => ex3_np1_ude_dbg_event, + dout => ex4_np1_ude_dbg_event_q); +ex4_np1_udec_int_latch : tri_rlmreg_p + generic map (width => ex4_np1_udec_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_np1_udec_int_offset to ex4_np1_udec_int_offset + ex4_np1_udec_int_q'length-1), + scout => sov(ex4_np1_udec_int_offset to ex4_np1_udec_int_offset + ex4_np1_udec_int_q'length-1), + din => ex3_np1_udec_int, + dout => ex4_np1_udec_int_q); +ex4_np1_wdog_cint_latch : tri_rlmreg_p + generic map (width => ex4_np1_wdog_cint_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_np1_wdog_cint_offset to ex4_np1_wdog_cint_offset + ex4_np1_wdog_cint_q'length-1), + scout => sov(ex4_np1_wdog_cint_offset to ex4_np1_wdog_cint_offset + ex4_np1_wdog_cint_q'length-1), + din => ex3_np1_wdog_cint, + dout => ex4_np1_wdog_cint_q); +ex4_np1_fu_flush_latch : tri_rlmreg_p + generic map (width => ex4_np1_fu_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1 ) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_np1_fu_flush_offset to ex4_np1_fu_flush_offset + ex4_np1_fu_flush_q'length-1), + scout => sov(ex4_np1_fu_flush_offset to ex4_np1_fu_flush_offset + ex4_np1_fu_flush_q'length-1), + din => ex3_np1_fu_flush, + dout => ex4_np1_fu_flush_q); +ex4_n_ieratsx_par_mchk_mcint_latch : tri_rlmreg_p + generic map (width => ex4_n_ieratsx_par_mchk_mcint_q'length, init => 0, expand_type => expand_type, needs_sreset => 1 ) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_ieratsx_par_mchk_mcint_offset to ex4_n_ieratsx_par_mchk_mcint_offset + ex4_n_ieratsx_par_mchk_mcint_q'length-1), + scout => sov(ex4_n_ieratsx_par_mchk_mcint_offset to ex4_n_ieratsx_par_mchk_mcint_offset + ex4_n_ieratsx_par_mchk_mcint_q'length-1), + din => ex3_n_ieratsx_par_mchk_mcint, + dout => ex4_n_ieratsx_par_mchk_mcint_q); +ex4_n_tlbmh_mchk_mcint_latch : tri_rlmreg_p + generic map (width => ex4_n_tlbmh_mchk_mcint_q'length, init => 0, expand_type => expand_type, needs_sreset => 1 ) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_tlbmh_mchk_mcint_offset to ex4_n_tlbmh_mchk_mcint_offset + ex4_n_tlbmh_mchk_mcint_q'length-1), + scout => sov(ex4_n_tlbmh_mchk_mcint_offset to ex4_n_tlbmh_mchk_mcint_offset + ex4_n_tlbmh_mchk_mcint_q'length-1), + din => ex3_n_tlbmh_mchk_mcint , + dout => ex4_n_tlbmh_mchk_mcint_q); +ex4_n_sprg_ue_flush_latch : tri_rlmreg_p + generic map (width => ex4_n_sprg_ue_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_sprg_ue_flush_offset to ex4_n_sprg_ue_flush_offset + ex4_n_sprg_ue_flush_q'length-1), + scout => sov(ex4_n_sprg_ue_flush_offset to ex4_n_sprg_ue_flush_offset + ex4_n_sprg_ue_flush_q'length-1), + din => ex3_n_sprg_ue_flush , + dout => ex4_n_sprg_ue_flush_q); +ex4_n_rwaccess_dstor_int_latch : tri_rlmreg_p + generic map (width => ex4_n_rwaccess_dstor_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_rwaccess_dstor_int_offset to ex4_n_rwaccess_dstor_int_offset + ex4_n_rwaccess_dstor_int_q'length-1), + scout => sov(ex4_n_rwaccess_dstor_int_offset to ex4_n_rwaccess_dstor_int_offset + ex4_n_rwaccess_dstor_int_q'length-1), + din => ex3_n_rwaccess_dstor_int, + dout => ex4_n_rwaccess_dstor_int_q); +ex4_n_exaccess_istor_int_latch : tri_rlmreg_p + generic map (width => ex4_n_exaccess_istor_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_exaccess_istor_int_offset to ex4_n_exaccess_istor_int_offset + ex4_n_exaccess_istor_int_q'length-1), + scout => sov(ex4_n_exaccess_istor_int_offset to ex4_n_exaccess_istor_int_offset + ex4_n_exaccess_istor_int_q'length-1), + din => ex3_n_exaccess_istor_int, + dout => ex4_n_exaccess_istor_int_q); +ex4_sc_lev_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_sc_lev_offset), + scout => sov(ex4_sc_lev_offset), + din => ex3_sc_lev_q , + dout => ex4_sc_lev_q); +ex4_siar_sel_latch : tri_rlmreg_p + generic map (width => ex4_siar_sel_q'length, init => 1, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_siar_sel_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_siar_sel_offset to ex4_siar_sel_offset + ex4_siar_sel_q'length-1), + scout => sov(ex4_siar_sel_offset to ex4_siar_sel_offset + ex4_siar_sel_q'length-1), + din => ex4_siar_sel_d, + dout => ex4_siar_sel_q); +ex4_step_latch : tri_rlmreg_p + generic map (width => ex4_step_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_step_offset to ex4_step_offset + ex4_step_q'length-1), + scout => sov(ex4_step_offset to ex4_step_offset + ex4_step_q'length-1), + din => ex4_step_d, + dout => ex4_step_q); +ex4_taken_bclr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_taken_bclr_offset), + scout => sov(ex4_taken_bclr_offset), + din => ex3_taken_bclr_q , + dout => ex4_taken_bclr_q); +ex4_tlb_inelig_latch : tri_rlmreg_p + generic map (width => ex4_tlb_inelig_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_tlb_inelig_offset to ex4_tlb_inelig_offset + ex4_tlb_inelig_q'length-1), + scout => sov(ex4_tlb_inelig_offset to ex4_tlb_inelig_offset + ex4_tlb_inelig_q'length-1), + din => ex3_tlb_inelig_q , + dout => ex4_tlb_inelig_q); +ex4_ucode_val_latch : tri_rlmreg_p + generic map (width => ex4_ucode_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_ucode_val_offset to ex4_ucode_val_offset + ex4_ucode_val_q'length-1), + scout => sov(ex4_ucode_val_offset to ex4_ucode_val_offset + ex4_ucode_val_q'length-1), + din => ex3_ucode_val , + dout => ex4_ucode_val_q); +ex4_xu_is_ucode_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_xu_is_ucode_offset), + scout => sov(ex4_xu_is_ucode_offset), + din => ex3_xu_is_ucode_q , + dout => ex4_xu_is_ucode_q); +ex4_xu_val_latch : tri_rlmreg_p + generic map (width => ex4_xu_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_xu_val_offset to ex4_xu_val_offset + ex4_xu_val_q'length-1), + scout => sov(ex4_xu_val_offset to ex4_xu_val_offset + ex4_xu_val_q'length-1), + din => ex3_xu_val , + dout => ex4_xu_val_q); +ex4_cia_act_latch : tri_rlmreg_p + generic map (width => ex4_cia_act_q'length, init => 0, expand_type => expand_type, needs_sreset => 1 ) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_cia_act_offset to ex4_cia_act_offset + ex4_cia_act_q'length-1), + scout => sov(ex4_cia_act_offset to ex4_cia_act_offset + ex4_cia_act_q'length-1), + din => ex3_cia_act, + dout => ex4_cia_act_q); +ex4_n_async_dacr_dbg_cint_latch : tri_rlmreg_p + generic map (width => ex4_n_async_dacr_dbg_cint_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_n_async_dacr_dbg_cint_offset to ex4_n_async_dacr_dbg_cint_offset + ex4_n_async_dacr_dbg_cint_q'length-1), + scout => sov(ex4_n_async_dacr_dbg_cint_offset to ex4_n_async_dacr_dbg_cint_offset + ex4_n_async_dacr_dbg_cint_q'length-1), + din => ex3_n_async_dacr_dbg_cint, + dout => ex4_n_async_dacr_dbg_cint_q); +ex4_dac1r_cmpr_async_latch : tri_rlmreg_p + generic map (width => ex4_dac1r_cmpr_async_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_dac1r_cmpr_async_offset to ex4_dac1r_cmpr_async_offset + ex4_dac1r_cmpr_async_q'length-1), + scout => sov(ex4_dac1r_cmpr_async_offset to ex4_dac1r_cmpr_async_offset + ex4_dac1r_cmpr_async_q'length-1), + din => ex4_dac1r_cmpr_async_d, + dout => ex4_dac1r_cmpr_async_q); +ex4_dac2r_cmpr_async_latch : tri_rlmreg_p + generic map (width => ex4_dac2r_cmpr_async_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_dac2r_cmpr_async_offset to ex4_dac2r_cmpr_async_offset + ex4_dac2r_cmpr_async_q'length-1), + scout => sov(ex4_dac2r_cmpr_async_offset to ex4_dac2r_cmpr_async_offset + ex4_dac2r_cmpr_async_q'length-1), + din => ex4_dac2r_cmpr_async_d, + dout => ex4_dac2r_cmpr_async_q); +ex4_thread_stop_latch : tri_rlmreg_p + generic map (width => ex4_thread_stop_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_thread_stop_offset to ex4_thread_stop_offset + ex4_thread_stop_q'length-1), + scout => sov(ex4_thread_stop_offset to ex4_thread_stop_offset + ex4_thread_stop_q'length-1), + din => ex3_thread_stop, + dout => ex4_thread_stop_q); +ex5_icmp_event_on_int_ok_latch : tri_rlmreg_p + generic map (width => ex5_icmp_event_on_int_ok_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_icmp_event_on_int_ok_offset to ex5_icmp_event_on_int_ok_offset + ex5_icmp_event_on_int_ok_q'length-1), + scout => sov(ex5_icmp_event_on_int_ok_offset to ex5_icmp_event_on_int_ok_offset + ex5_icmp_event_on_int_ok_q'length-1), + din => ex4_icmp_event_on_int_ok, + dout => ex5_icmp_event_on_int_ok_q); +ex5_any_val_latch : tri_rlmreg_p + generic map (width => ex5_any_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_any_val_offset to ex5_any_val_offset + ex5_any_val_q'length-1), + scout => sov(ex5_any_val_offset to ex5_any_val_offset + ex5_any_val_q'length-1), + din => ex4_any_val , + dout => ex5_any_val_q); +ex5_attn_flush_latch : tri_rlmreg_p + generic map (width => ex5_attn_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_attn_flush_offset to ex5_attn_flush_offset + ex5_attn_flush_q'length-1), + scout => sov(ex5_attn_flush_offset to ex5_attn_flush_offset + ex5_attn_flush_q'length-1), + din => ex4_attn_flush, + dout => ex5_attn_flush_q); +ex5_axu_trap_pie_latch : tri_rlmreg_p + generic map (width => ex5_axu_trap_pie_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_axu_trap_pie_offset to ex5_axu_trap_pie_offset + ex5_axu_trap_pie_q'length-1), + scout => sov(ex5_axu_trap_pie_offset to ex5_axu_trap_pie_offset + ex5_axu_trap_pie_q'length-1), + din => ex5_axu_trap_pie_d, + dout => ex5_axu_trap_pie_q); +ex5_br_taken_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_br_taken_offset), + scout => sov(ex5_br_taken_offset), + din => ex4_br_taken_q , + dout => ex5_br_taken_q); +ex5_cdbell_taken_latch : tri_rlmreg_p + generic map (width => ex5_cdbell_taken_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_cdbell_taken_offset to ex5_cdbell_taken_offset + ex5_cdbell_taken_q'length-1), + scout => sov(ex5_cdbell_taken_offset to ex5_cdbell_taken_offset + ex5_cdbell_taken_q'length-1), + din => ex5_cdbell_taken_d, + dout => ex5_cdbell_taken_q); +ex5_check_bclr_latch : tri_rlmreg_p + generic map (width => ex5_check_bclr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_check_bclr_offset to ex5_check_bclr_offset + ex5_check_bclr_q'length-1), + scout => sov(ex5_check_bclr_offset to ex5_check_bclr_offset + ex5_check_bclr_q'length-1), + din => ex5_check_bclr_d, + dout => ex5_check_bclr_q); +ex5_cia_p1_latch : tri_rlmreg_p + generic map (width => ex5_cia_p1_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_cia_p1_offset to ex5_cia_p1_offset + ex5_cia_p1_q'length-1), + scout => sov(ex5_cia_p1_offset to ex5_cia_p1_offset + ex5_cia_p1_q'length-1), + din => ex5_cia_p1_d, + dout => ex5_cia_p1_q); +ex5_dbell_taken_latch : tri_rlmreg_p + generic map (width => ex5_dbell_taken_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_dbell_taken_offset to ex5_dbell_taken_offset + ex5_dbell_taken_q'length-1), + scout => sov(ex5_dbell_taken_offset to ex5_dbell_taken_offset + ex5_dbell_taken_q'length-1), + din => ex5_dbell_taken_d, + dout => ex5_dbell_taken_q); +ex5_dbsr_update_latch : tri_rlmreg_p + generic map (width => ex5_dbsr_update_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_dbsr_update_offset to ex5_dbsr_update_offset + ex5_dbsr_update_q'length-1), + scout => sov(ex5_dbsr_update_offset to ex5_dbsr_update_offset + ex5_dbsr_update_q'length-1), + din => ex4_dbsr_update, + dout => ex5_dbsr_update_q); +ex5_dear_update_saved_latch : tri_rlmreg_p + generic map (width => ex5_dear_update_saved_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_dear_update_saved_offset to ex5_dear_update_saved_offset + ex5_dear_update_saved_q'length-1), + scout => sov(ex5_dear_update_saved_offset to ex5_dear_update_saved_offset + ex5_dear_update_saved_q'length-1), + din => ex5_dear_update_saved_d, + dout => ex5_dear_update_saved_q); +ex5_deratre_par_err_latch : tri_rlmreg_p + generic map (width => ex5_deratre_par_err_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_deratre_par_err_offset to ex5_deratre_par_err_offset + ex5_deratre_par_err_q'length-1), + scout => sov(ex5_deratre_par_err_offset to ex5_deratre_par_err_offset + ex5_deratre_par_err_q'length-1), + din => lsu_xu_ex4_derat_par_err , + dout => ex5_deratre_par_err_q); +ex5_div_set_barr_latch : tri_rlmreg_p + generic map (width => ex5_div_set_barr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_div_set_barr_offset to ex5_div_set_barr_offset + ex5_div_set_barr_q'length-1), + scout => sov(ex5_div_set_barr_offset to ex5_div_set_barr_offset + ex5_div_set_barr_q'length-1), + din => ex5_div_set_barr_d, + dout => ex5_div_set_barr_q); +ex5_dsigs_latch : tri_rlmreg_p + generic map (width => ex5_dsigs_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_dsigs_offset to ex5_dsigs_offset + ex5_dsigs_q'length-1), + scout => sov(ex5_dsigs_offset to ex5_dsigs_offset + ex5_dsigs_q'length-1), + din => ex5_dsigs_d, + dout => ex5_dsigs_q); +ex5_dtlbgs_latch : tri_rlmreg_p + generic map (width => ex5_dtlbgs_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_dtlbgs_offset to ex5_dtlbgs_offset + ex5_dtlbgs_q'length-1), + scout => sov(ex5_dtlbgs_offset to ex5_dtlbgs_offset + ex5_dtlbgs_q'length-1), + din => ex5_dtlbgs_d, + dout => ex5_dtlbgs_q); +ex5_err_nia_miscmpr_latch : tri_rlmreg_p + generic map (width => ex5_err_nia_miscmpr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_err_nia_miscmpr_offset to ex5_err_nia_miscmpr_offset + ex5_err_nia_miscmpr_q'length-1), + scout => sov(ex5_err_nia_miscmpr_offset to ex5_err_nia_miscmpr_offset + ex5_err_nia_miscmpr_q'length-1), + din => ex5_err_nia_miscmpr_d, + dout => ex5_err_nia_miscmpr_q); +ex5_ext_dbg_err_latch : tri_rlmreg_p + generic map (width => ex5_ext_dbg_err_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_ext_dbg_err_offset to ex5_ext_dbg_err_offset + ex5_ext_dbg_err_q'length-1), + scout => sov(ex5_ext_dbg_err_offset to ex5_ext_dbg_err_offset + ex5_ext_dbg_err_q'length-1), + din => ex5_ext_dbg_err_d, + dout => ex5_ext_dbg_err_q); +ex5_ext_dbg_ext_latch : tri_rlmreg_p + generic map (width => ex5_ext_dbg_ext_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_ext_dbg_ext_offset to ex5_ext_dbg_ext_offset + ex5_ext_dbg_ext_q'length-1), + scout => sov(ex5_ext_dbg_ext_offset to ex5_ext_dbg_ext_offset + ex5_ext_dbg_ext_q'length-1), + din => ex5_ext_dbg_ext_d, + dout => ex5_ext_dbg_ext_q); +ex5_extgs_latch : tri_rlmreg_p + generic map (width => ex5_extgs_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_extgs_offset to ex5_extgs_offset + ex5_extgs_q'length-1), + scout => sov(ex5_extgs_offset to ex5_extgs_offset + ex5_extgs_q'length-1), + din => ex5_extgs_d, + dout => ex5_extgs_q); +ex5_flush_latch : tri_rlmreg_p + generic map (width => ex5_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_flush_offset to ex5_flush_offset + ex5_flush_q'length-1), + scout => sov(ex5_flush_offset to ex5_flush_offset + ex5_flush_q'length-1), + din => ex4_flush , + dout => ex5_flush_q); +ex5_force_gsrr_latch : tri_rlmreg_p + generic map (width => ex5_force_gsrr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_force_gsrr_offset to ex5_force_gsrr_offset + ex5_force_gsrr_q'length-1), + scout => sov(ex5_force_gsrr_offset to ex5_force_gsrr_offset + ex5_force_gsrr_q'length-1), + din => ex5_force_gsrr_d, + dout => ex5_force_gsrr_q); +ex5_gcdbell_taken_latch : tri_rlmreg_p + generic map (width => ex5_gcdbell_taken_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_gcdbell_taken_offset to ex5_gcdbell_taken_offset + ex5_gcdbell_taken_q'length-1), + scout => sov(ex5_gcdbell_taken_offset to ex5_gcdbell_taken_offset + ex5_gcdbell_taken_q'length-1), + din => ex5_gcdbell_taken_d, + dout => ex5_gcdbell_taken_q); +ex5_gdbell_taken_latch : tri_rlmreg_p + generic map (width => ex5_gdbell_taken_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_gdbell_taken_offset to ex5_gdbell_taken_offset + ex5_gdbell_taken_q'length-1), + scout => sov(ex5_gdbell_taken_offset to ex5_gdbell_taken_offset + ex5_gdbell_taken_q'length-1), + din => ex5_gdbell_taken_d, + dout => ex5_gdbell_taken_q); +ex5_gmcdbell_taken_latch : tri_rlmreg_p + generic map (width => ex5_gmcdbell_taken_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_gmcdbell_taken_offset to ex5_gmcdbell_taken_offset + ex5_gmcdbell_taken_q'length-1), + scout => sov(ex5_gmcdbell_taken_offset to ex5_gmcdbell_taken_offset + ex5_gmcdbell_taken_q'length-1), + din => ex5_gmcdbell_taken_d, + dout => ex5_gmcdbell_taken_q); +ex5_ieratre_par_err_latch : tri_rlmreg_p + generic map (width => ex5_ieratre_par_err_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_ieratre_par_err_offset to ex5_ieratre_par_err_offset + ex5_ieratre_par_err_q'length-1), + scout => sov(ex5_ieratre_par_err_offset to ex5_ieratre_par_err_offset + ex5_ieratre_par_err_q'length-1), + din => iu_xu_ierat_ex4_par_err , + dout => ex5_ieratre_par_err_q); +ex5_in_ucode_latch : tri_rlmreg_p + generic map (width => ex5_in_ucode_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_in_ucode_offset to ex5_in_ucode_offset + ex5_in_ucode_q'length-1), + scout => sov(ex5_in_ucode_offset to ex5_in_ucode_offset + ex5_in_ucode_q'length-1), + din => ex5_in_ucode_d, + dout => ex5_in_ucode_q); +ex5_instr_cpl_latch : tri_rlmreg_p + generic map (width => ex5_instr_cpl_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_instr_cpl_offset to ex5_instr_cpl_offset + ex5_instr_cpl_q'length-1), + scout => sov(ex5_instr_cpl_offset to ex5_instr_cpl_offset + ex5_instr_cpl_q'length-1), + din => ex4_instr_cpl, + dout => ex5_instr_cpl_q); +ex5_is_any_rfi_latch : tri_rlmreg_p + generic map (width => ex5_is_any_rfi_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_is_any_rfi_offset to ex5_is_any_rfi_offset + ex5_is_any_rfi_q'length-1), + scout => sov(ex5_is_any_rfi_offset to ex5_is_any_rfi_offset + ex5_is_any_rfi_q'length-1), + din => ex4_is_any_rfi, + dout => ex5_is_any_rfi_q); +ex5_is_attn_latch : tri_rlmreg_p + generic map (width => ex5_is_attn_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_is_attn_offset to ex5_is_attn_offset + ex5_is_attn_q'length-1), + scout => sov(ex5_is_attn_offset to ex5_is_attn_offset + ex5_is_attn_q'length-1), + din => ex5_is_attn_d, + dout => ex5_is_attn_q); +ex5_is_crit_int_latch : tri_rlmreg_p + generic map (width => ex5_is_crit_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_is_crit_int_offset to ex5_is_crit_int_offset + ex5_is_crit_int_q'length-1), + scout => sov(ex5_is_crit_int_offset to ex5_is_crit_int_offset + ex5_is_crit_int_q'length-1), + din => ex4_is_crit_int , + dout => ex5_is_crit_int_q); +ex5_is_mchk_int_latch : tri_rlmreg_p + generic map (width => ex5_is_mchk_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_is_mchk_int_offset to ex5_is_mchk_int_offset + ex5_is_mchk_int_q'length-1), + scout => sov(ex5_is_mchk_int_offset to ex5_is_mchk_int_offset + ex5_is_mchk_int_q'length-1), + din => ex4_is_mchk_int , + dout => ex5_is_mchk_int_q); +ex5_is_mtmsr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_is_mtmsr_offset), + scout => sov(ex5_is_mtmsr_offset), + din => ex4_is_mtmsr_q , + dout => ex5_is_mtmsr_q); +ex5_is_isync_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_is_isync_offset), + scout => sov(ex5_is_isync_offset), + din => ex4_is_isync_q , + dout => ex5_is_isync_q); +ex5_is_tlbwe_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_is_tlbwe_offset), + scout => sov(ex5_is_tlbwe_offset), + din => ex4_is_tlbwe_q , + dout => ex5_is_tlbwe_q); +ex5_isigs_latch : tri_rlmreg_p + generic map (width => ex5_isigs_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_isigs_offset to ex5_isigs_offset + ex5_isigs_q'length-1), + scout => sov(ex5_isigs_offset to ex5_isigs_offset + ex5_isigs_q'length-1), + din => ex5_isigs_d, + dout => ex5_isigs_q); +ex5_itlbgs_latch : tri_rlmreg_p + generic map (width => ex5_itlbgs_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_itlbgs_offset to ex5_itlbgs_offset + ex5_itlbgs_q'length-1), + scout => sov(ex5_itlbgs_offset to ex5_itlbgs_offset + ex5_itlbgs_q'length-1), + din => ex5_itlbgs_d, + dout => ex5_itlbgs_q); +ex5_lsu_set_barr_latch : tri_rlmreg_p + generic map (width => ex5_lsu_set_barr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_lsu_set_barr_offset to ex5_lsu_set_barr_offset + ex5_lsu_set_barr_q'length-1), + scout => sov(ex5_lsu_set_barr_offset to ex5_lsu_set_barr_offset + ex5_lsu_set_barr_q'length-1), + din => ex5_lsu_set_barr_d, + dout => ex5_lsu_set_barr_q); +ex5_mem_attr_val_latch : tri_rlmreg_p + generic map (width => ex5_mem_attr_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_mem_attr_val_offset to ex5_mem_attr_val_offset + ex5_mem_attr_val_q'length-1), + scout => sov(ex5_mem_attr_val_offset to ex5_mem_attr_val_offset + ex5_mem_attr_val_q'length-1), + din => ex4_mem_attr_val, + dout => ex5_mem_attr_val_q); +ex5_mmu_hold_val_latch : tri_rlmreg_p + generic map (width => ex5_mmu_hold_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_mmu_hold_val_offset to ex5_mmu_hold_val_offset + ex5_mmu_hold_val_q'length-1), + scout => sov(ex5_mmu_hold_val_offset to ex5_mmu_hold_val_offset + ex5_mmu_hold_val_q'length-1), + din => ex4_mmu_hold_val_q, + dout => ex5_mmu_hold_val_q); +ex5_n_dmiss_flush_latch : tri_rlmreg_p + generic map (width => ex5_n_dmiss_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_n_dmiss_flush_offset to ex5_n_dmiss_flush_offset + ex5_n_dmiss_flush_q'length-1), + scout => sov(ex5_n_dmiss_flush_offset to ex5_n_dmiss_flush_offset + ex5_n_dmiss_flush_q'length-1), + din => ex4_n_dmiss_flush, + dout => ex5_n_dmiss_flush_q); +ex5_n_ext_dbg_stopc_flush_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_n_ext_dbg_stopc_flush_offset), + scout => sov(ex5_n_ext_dbg_stopc_flush_offset), + din => ex5_n_ext_dbg_stopc_flush_d, + dout => ex5_n_ext_dbg_stopc_flush_q); +ex5_n_ext_dbg_stopt_flush_latch : tri_rlmreg_p + generic map (width => ex5_n_ext_dbg_stopt_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_n_ext_dbg_stopt_flush_offset to ex5_n_ext_dbg_stopt_flush_offset + ex5_n_ext_dbg_stopt_flush_q'length-1), + scout => sov(ex5_n_ext_dbg_stopt_flush_offset to ex5_n_ext_dbg_stopt_flush_offset + ex5_n_ext_dbg_stopt_flush_q'length-1), + din => ex5_n_ext_dbg_stopt_flush_d, + dout => ex5_n_ext_dbg_stopt_flush_q); +ex5_n_imiss_flush_latch : tri_rlmreg_p + generic map (width => ex5_n_imiss_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_n_imiss_flush_offset to ex5_n_imiss_flush_offset + ex5_n_imiss_flush_q'length-1), + scout => sov(ex5_n_imiss_flush_offset to ex5_n_imiss_flush_offset + ex5_n_imiss_flush_q'length-1), + din => ex4_n_imiss_flush, + dout => ex5_n_imiss_flush_q); +ex5_n_ptemiss_dlrat_int_latch : tri_rlmreg_p + generic map (width => ex5_n_ptemiss_dlrat_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_n_ptemiss_dlrat_int_offset to ex5_n_ptemiss_dlrat_int_offset + ex5_n_ptemiss_dlrat_int_q'length-1), + scout => sov(ex5_n_ptemiss_dlrat_int_offset to ex5_n_ptemiss_dlrat_int_offset + ex5_n_ptemiss_dlrat_int_q'length-1), + din => ex4_n_ptemiss_dlrat_int_q , + dout => ex5_n_ptemiss_dlrat_int_q); +ex5_np1_run_ctl_flush_latch : tri_rlmreg_p + generic map (width => ex5_np1_run_ctl_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_np1_run_ctl_flush_offset to ex5_np1_run_ctl_flush_offset + ex5_np1_run_ctl_flush_q'length-1), + scout => sov(ex5_np1_run_ctl_flush_offset to ex5_np1_run_ctl_flush_offset + ex5_np1_run_ctl_flush_q'length-1), + din => ex4_np1_run_ctl_flush, + dout => ex5_np1_run_ctl_flush_q); +ex5_dbsr_ide_latch : tri_rlmreg_p + generic map (width => ex5_dbsr_ide_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_dbsr_ide_offset to ex5_dbsr_ide_offset + ex5_dbsr_ide_q'length-1), + scout => sov(ex5_dbsr_ide_offset to ex5_dbsr_ide_offset + ex5_dbsr_ide_q'length-1), + din => ex5_dbsr_ide_d, + dout => ex5_dbsr_ide_q); +ex5_perf_dtlb_latch : tri_rlmreg_p + generic map (width => ex5_perf_dtlb_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_perf_dtlb_offset to ex5_perf_dtlb_offset + ex5_perf_dtlb_q'length-1), + scout => sov(ex5_perf_dtlb_offset to ex5_perf_dtlb_offset + ex5_perf_dtlb_q'length-1), + din => ex5_perf_dtlb_d, + dout => ex5_perf_dtlb_q); +ex5_perf_itlb_latch : tri_rlmreg_p + generic map (width => ex5_perf_itlb_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_perf_itlb_offset to ex5_perf_itlb_offset + ex5_perf_itlb_q'length-1), + scout => sov(ex5_perf_itlb_offset to ex5_perf_itlb_offset + ex5_perf_itlb_q'length-1), + din => ex5_perf_itlb_d, + dout => ex5_perf_itlb_q); +ex5_ram_done_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_ram_done_offset), + scout => sov(ex5_ram_done_offset), + din => ex5_ram_done_d, + dout => ex5_ram_done_q); +ex5_ram_issue_latch : tri_rlmreg_p + generic map (width => ex5_ram_issue_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_ram_issue_offset to ex5_ram_issue_offset + ex5_ram_issue_q'length-1), + scout => sov(ex5_ram_issue_offset to ex5_ram_issue_offset + ex5_ram_issue_q'length-1), + din => ex5_ram_issue_d, + dout => ex5_ram_issue_q); +ex5_rt_latch : tri_rlmreg_p + generic map (width => ex5_rt_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_rt_offset to ex5_rt_offset + ex5_rt_q'length-1), + scout => sov(ex5_rt_offset to ex5_rt_offset + ex5_rt_q'length-1), + din => mux_cpl_ex4_rt , + dout => ex5_rt_q); +ex5_sel_rt_latch : tri_rlmreg_p + generic map (width => ex5_sel_rt_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_sel_rt_offset to ex5_sel_rt_offset + ex5_sel_rt_q'length-1), + scout => sov(ex5_sel_rt_offset to ex5_sel_rt_offset + ex5_sel_rt_q'length-1), + din => ex5_sel_rt_d, + dout => ex5_sel_rt_q); +ex5_srr0_dec_latch : tri_rlmreg_p + generic map (width => ex5_srr0_dec_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_srr0_dec_offset to ex5_srr0_dec_offset + ex5_srr0_dec_q'length-1), + scout => sov(ex5_srr0_dec_offset to ex5_srr0_dec_offset + ex5_srr0_dec_q'length-1), + din => ex5_srr0_dec_d, + dout => ex5_srr0_dec_q); +ex5_tlb_inelig_latch : tri_rlmreg_p + generic map (width => ex5_tlb_inelig_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_tlb_inelig_offset to ex5_tlb_inelig_offset + ex5_tlb_inelig_q'length-1), + scout => sov(ex5_tlb_inelig_offset to ex5_tlb_inelig_offset + ex5_tlb_inelig_q'length-1), + din => ex4_tlb_inelig_q , + dout => ex5_tlb_inelig_q); +ex5_uc_cia_val_latch : tri_rlmreg_p + generic map (width => ex5_uc_cia_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_uc_cia_val_offset to ex5_uc_cia_val_offset + ex5_uc_cia_val_q'length-1), + scout => sov(ex5_uc_cia_val_offset to ex5_uc_cia_val_offset + ex5_uc_cia_val_q'length-1), + din => ex5_uc_cia_val_d, + dout => ex5_uc_cia_val_q); +ex5_xu_ifar_latch : tri_rlmreg_p + generic map (width => ex5_xu_ifar_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_xu_ifar_offset to ex5_xu_ifar_offset + ex5_xu_ifar_q'length-1), + scout => sov(ex5_xu_ifar_offset to ex5_xu_ifar_offset + ex5_xu_ifar_q'length-1), + din => ex5_xu_ifar_d, + dout => ex5_xu_ifar_q); +ex5_xu_val_latch : tri_rlmreg_p + generic map (width => ex5_xu_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_xu_val_offset to ex5_xu_val_offset + ex5_xu_val_q'length-1), + scout => sov(ex5_xu_val_offset to ex5_xu_val_offset + ex5_xu_val_q'length-1), + din => ex4_xu_val , + dout => ex5_xu_val_q); +ex5_n_flush_sprg_ue_flush_latch : tri_rlmreg_p + generic map (width => ex5_n_flush_sprg_ue_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_n_flush_sprg_ue_flush_offset to ex5_n_flush_sprg_ue_flush_offset + ex5_n_flush_sprg_ue_flush_q'length-1), + scout => sov(ex5_n_flush_sprg_ue_flush_offset to ex5_n_flush_sprg_ue_flush_offset + ex5_n_flush_sprg_ue_flush_q'length-1), + din => ex4_n_flush_sprg_ue_flush, + dout => ex5_n_flush_sprg_ue_flush_q); +ex5_mcsr_act_latch : tri_rlmreg_p + generic map (width => ex5_mcsr_act_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_mcsr_act_offset to ex5_mcsr_act_offset + ex5_mcsr_act_q'length-1), + scout => sov(ex5_mcsr_act_offset to ex5_mcsr_act_offset + ex5_mcsr_act_q'length-1), + din => ex4_mcsr_act , + dout => ex5_mcsr_act_q); +ex6_mcsr_act_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_mcsr_act_offset), + scout => sov(ex6_mcsr_act_offset), + din => ex6_mcsr_act_d , + dout => ex6_mcsr_act_q); +ex6_late_flush_latch : tri_regk + generic map (width => ex6_late_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex5_late_flush_q(0), + dout => ex6_late_flush_q); +ex6_mmu_hold_val_latch : tri_regk + generic map (width => ex6_mmu_hold_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex5_mmu_hold_val_q, + dout => ex6_mmu_hold_val_q); +ex6_ram_done_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_ram_done_offset), + scout => sov(ex6_ram_done_offset), + din => ex5_ram_done_q , + dout => ex6_ram_done_q); +ex6_ram_interrupt_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_ram_interrupt_offset), + scout => sov(ex6_ram_interrupt_offset), + din => ex6_ram_interrupt_d, + dout => ex6_ram_interrupt_q); +ex6_ram_issue_latch : tri_rlmreg_p + generic map (width => ex6_ram_issue_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_ram_issue_offset to ex6_ram_issue_offset + ex6_ram_issue_q'length-1), + scout => sov(ex6_ram_issue_offset to ex6_ram_issue_offset + ex6_ram_issue_q'length-1), + din => ex6_ram_issue_d, + dout => ex6_ram_issue_q); +ex7_ram_issue_latch : tri_rlmreg_p + generic map (width => ex7_ram_issue_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex7_ram_issue_offset to ex7_ram_issue_offset + ex7_ram_issue_q'length-1), + scout => sov(ex7_ram_issue_offset to ex7_ram_issue_offset + ex7_ram_issue_q'length-1), + din => ex6_ram_issue_q, + dout => ex7_ram_issue_q); +ex8_ram_issue_latch : tri_rlmreg_p + generic map (width => ex8_ram_issue_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex8_ram_issue_offset to ex8_ram_issue_offset + ex8_ram_issue_q'length-1), + scout => sov(ex8_ram_issue_offset to ex8_ram_issue_offset + ex8_ram_issue_q'length-1), + din => ex7_ram_issue_q, + dout => ex8_ram_issue_q); +ex6_set_barr_latch : tri_regk + generic map (width => ex6_set_barr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex6_set_barr_d, + dout => ex6_set_barr_q); +ex6_step_done_latch : tri_rlmreg_p + generic map (width => ex6_step_done_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_step_done_offset to ex6_step_done_offset + ex6_step_done_q'length-1), + scout => sov(ex6_step_done_offset to ex6_step_done_offset + ex6_step_done_q'length-1), + din => ex5_step_done, + dout => ex6_step_done_q); +ex6_xu_val_latch : tri_rlmreg_p + generic map (width => ex6_xu_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_xu_val_offset to ex6_xu_val_offset + ex6_xu_val_q'length-1), + scout => sov(ex6_xu_val_offset to ex6_xu_val_offset + ex6_xu_val_q'length-1), + din => ex5_xu_val_q , + dout => ex6_xu_val_q); +ex6_is_tlbwe_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex5_is_tlbwe_q , + dout(0) => ex6_is_tlbwe_q); +ex7_is_tlbwe_latch : tri_rlmreg_p + generic map (width => ex7_is_tlbwe_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex7_is_tlbwe_offset to ex7_is_tlbwe_offset + ex7_is_tlbwe_q'length-1), + scout => sov(ex7_is_tlbwe_offset to ex7_is_tlbwe_offset + ex7_is_tlbwe_q'length-1), + din => ex7_is_tlbwe_d, + dout => ex7_is_tlbwe_q); +ex8_is_tlbwe_latch : tri_rlmreg_p + generic map (width => ex8_is_tlbwe_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex8_is_tlbwe_offset to ex8_is_tlbwe_offset + ex8_is_tlbwe_q'length-1), + scout => sov(ex8_is_tlbwe_offset to ex8_is_tlbwe_offset + ex8_is_tlbwe_q'length-1), + din => ex7_is_tlbwe_q , + dout => ex8_is_tlbwe_q); +ccr2_ap_latch : tri_rlmreg_p + generic map (width => ccr2_ap_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ccr2_ap_offset to ccr2_ap_offset + ccr2_ap_q'length-1), + scout => sov(ccr2_ap_offset to ccr2_ap_offset + ccr2_ap_q'length-1), + din => spr_ccr2_ap , + dout => ccr2_ap_q); +cpl_quiesced_latch : tri_rlmreg_p + generic map (width => cpl_quiesced_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(cpl_quiesced_offset to cpl_quiesced_offset + cpl_quiesced_q'length-1), + scout => sov(cpl_quiesced_offset to cpl_quiesced_offset + cpl_quiesced_q'length-1), + din => cpl_quiesced_d, + dout => cpl_quiesced_q); +dbcr0_idm_latch : tri_rlmreg_p + generic map (width => dbcr0_idm_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dbcr0_idm_offset to dbcr0_idm_offset + dbcr0_idm_q'length-1), + scout => sov(dbcr0_idm_offset to dbcr0_idm_offset + dbcr0_idm_q'length-1), + din => spr_dbcr0_idm , + dout => dbcr0_idm_q); +dci_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dci_val_offset), + scout => sov(dci_val_offset), + din => dci_val_d, + dout => dci_val_q); +debug_event_en_latch : tri_rlmreg_p + generic map (width => debug_event_en_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(debug_event_en_offset to debug_event_en_offset + debug_event_en_q'length-1), + scout => sov(debug_event_en_offset to debug_event_en_offset + debug_event_en_q'length-1), + din => debug_event_en_d, + dout => debug_event_en_q); +derat_hold_present_latch : tri_rlmreg_p + generic map (width => derat_hold_present_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(derat_hold_present_offset to derat_hold_present_offset + derat_hold_present_q'length-1), + scout => sov(derat_hold_present_offset to derat_hold_present_offset + derat_hold_present_q'length-1), + din => derat_hold_present_d, + dout => derat_hold_present_q); +ext_dbg_act_err_latch : tri_rlmreg_p + generic map (width => ext_dbg_act_err_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ext_dbg_act_err_offset to ext_dbg_act_err_offset + ext_dbg_act_err_q'length-1), + scout => sov(ext_dbg_act_err_offset to ext_dbg_act_err_offset + ext_dbg_act_err_q'length-1), + din => ext_dbg_act_err_d, + dout => ext_dbg_act_err_q); +ext_dbg_act_ext_latch : tri_rlmreg_p + generic map (width => ext_dbg_act_ext_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ext_dbg_act_ext_offset to ext_dbg_act_ext_offset + ext_dbg_act_ext_q'length-1), + scout => sov(ext_dbg_act_ext_offset to ext_dbg_act_ext_offset + ext_dbg_act_ext_q'length-1), + din => ext_dbg_act_ext_d, + dout => ext_dbg_act_ext_q); +ext_dbg_stop_core_latch : tri_rlmreg_p + generic map (width => ext_dbg_stop_core_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ext_dbg_stop_core_offset to ext_dbg_stop_core_offset + ext_dbg_stop_core_q'length-1), + scout => sov(ext_dbg_stop_core_offset to ext_dbg_stop_core_offset + ext_dbg_stop_core_q'length-1), + din => ext_dbg_stop_core_d, + dout => ext_dbg_stop_core_q); +ext_dbg_stop_n_latch : tri_rlmreg_p + generic map (width => ext_dbg_stop_n_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ext_dbg_stop_n_offset to ext_dbg_stop_n_offset + ext_dbg_stop_n_q'length-1), + scout => sov(ext_dbg_stop_n_offset to ext_dbg_stop_n_offset + ext_dbg_stop_n_q'length-1), + din => ext_dbg_stop_n_d, + dout => ext_dbg_stop_n_q); +external_mchk_latch : tri_rlmreg_p + generic map (width => external_mchk_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(external_mchk_offset to external_mchk_offset + external_mchk_q'length-1), + scout => sov(external_mchk_offset to external_mchk_offset + external_mchk_q'length-1), + din => spr_cpl_external_mchk , + dout => external_mchk_q); +exx_multi_flush_latch : tri_rlmreg_p + generic map (width => exx_multi_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(exx_multi_flush_offset to exx_multi_flush_offset + exx_multi_flush_q'length-1), + scout => sov(exx_multi_flush_offset to exx_multi_flush_offset + exx_multi_flush_q'length-1), + din => exx_multi_flush_d, + dout => exx_multi_flush_q); +force_ude_latch : tri_rlmreg_p + generic map (width => force_ude_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(force_ude_offset to force_ude_offset + force_ude_q'length-1), + scout => sov(force_ude_offset to force_ude_offset + force_ude_q'length-1), + din => pc_xu_force_ude , + dout => force_ude_q); +fu_rf_seq_end_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(fu_rf_seq_end_offset), + scout => sov(fu_rf_seq_end_offset), + din => fu_xu_regfile_seq_end , + dout => fu_rf_seq_end_q); +fu_rfpe_ack_latch : tri_rlmreg_p + generic map (width => fu_rfpe_ack_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(fu_rfpe_ack_offset to fu_rfpe_ack_offset + fu_rfpe_ack_q'length-1), + scout => sov(fu_rfpe_ack_offset to fu_rfpe_ack_offset + fu_rfpe_ack_q'length-1), + din => fu_rfpe_ack_d, + dout => fu_rfpe_ack_q); +fu_rfpe_hold_present_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(fu_rfpe_hold_present_offset), + scout => sov(fu_rfpe_hold_present_offset), + din => fu_rfpe_hold_present_d, + dout => fu_rfpe_hold_present_q); +ici_hold_present_latch : tri_rlmreg_p + generic map (width => ici_hold_present_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ici_hold_present_offset to ici_hold_present_offset + ici_hold_present_q'length-1), + scout => sov(ici_hold_present_offset to ici_hold_present_offset + ici_hold_present_q'length-1), + din => ici_hold_present_d, + dout => ici_hold_present_q); +ici_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ici_val_offset), + scout => sov(ici_val_offset), + din => ici_val_d, + dout => ici_val_q); +ierat_hold_present_latch : tri_rlmreg_p + generic map (width => ierat_hold_present_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ierat_hold_present_offset to ierat_hold_present_offset + ierat_hold_present_q'length-1), + scout => sov(ierat_hold_present_offset to ierat_hold_present_offset + ierat_hold_present_q'length-1), + din => ierat_hold_present_d, + dout => ierat_hold_present_q); +mmu_eratmiss_done_latch : tri_rlmreg_p + generic map (width => mmu_eratmiss_done_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(mmu_eratmiss_done_offset to mmu_eratmiss_done_offset + mmu_eratmiss_done_q'length-1), + scout => sov(mmu_eratmiss_done_offset to mmu_eratmiss_done_offset + mmu_eratmiss_done_q'length-1), + din => mm_xu_eratmiss_done , + dout => mmu_eratmiss_done_q); +mmu_hold_present_latch : tri_rlmreg_p + generic map (width => mmu_hold_present_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(mmu_hold_present_offset to mmu_hold_present_offset + mmu_hold_present_q'length-1), + scout => sov(mmu_hold_present_offset to mmu_hold_present_offset + mmu_hold_present_q'length-1), + din => mmu_hold_present_d, + dout => mmu_hold_present_q); +mmu_hold_request_latch : tri_rlmreg_p + generic map (width => mmu_hold_request_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(mmu_hold_request_offset to mmu_hold_request_offset + mmu_hold_request_q'length-1), + scout => sov(mmu_hold_request_offset to mmu_hold_request_offset + mmu_hold_request_q'length-1), + din => mmu_hold_request_d, + dout => mmu_hold_request_q); +msr_cm_latch : tri_rlmreg_p + generic map (width => msr_cm_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_w_int_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(msr_cm_offset to msr_cm_offset + msr_cm_q'length-1), + scout => sov(msr_cm_offset to msr_cm_offset + msr_cm_q'length-1), + din => spr_msr_cm , + dout => msr_cm_q); +msr_de_latch : tri_rlmreg_p + generic map (width => msr_de_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_w_int_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(msr_de_offset to msr_de_offset + msr_de_q'length-1), + scout => sov(msr_de_offset to msr_de_offset + msr_de_q'length-1), + din => spr_msr_de , + dout => msr_de_q); +msr_fp_latch : tri_rlmreg_p + generic map (width => msr_fp_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_w_int_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(msr_fp_offset to msr_fp_offset + msr_fp_q'length-1), + scout => sov(msr_fp_offset to msr_fp_offset + msr_fp_q'length-1), + din => spr_msr_fp , + dout => msr_fp_q); +msr_gs_latch : tri_rlmreg_p + generic map (width => msr_gs_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_w_int_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(msr_gs_offset to msr_gs_offset + msr_gs_q'length-1), + scout => sov(msr_gs_offset to msr_gs_offset + msr_gs_q'length-1), + din => spr_msr_gs , + dout => msr_gs_q); +msr_me_latch : tri_rlmreg_p + generic map (width => msr_me_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_w_int_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(msr_me_offset to msr_me_offset + msr_me_q'length-1), + scout => sov(msr_me_offset to msr_me_offset + msr_me_q'length-1), + din => spr_msr_me , + dout => msr_me_q); +msr_pr_latch : tri_rlmreg_p + generic map (width => msr_pr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_w_int_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(msr_pr_offset to msr_pr_offset + msr_pr_q'length-1), + scout => sov(msr_pr_offset to msr_pr_offset + msr_pr_q'length-1), + din => spr_msr_pr , + dout => msr_pr_q); +msr_spv_latch : tri_rlmreg_p + generic map (width => msr_spv_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_w_int_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(msr_spv_offset to msr_spv_offset + msr_spv_q'length-1), + scout => sov(msr_spv_offset to msr_spv_offset + msr_spv_q'length-1), + din => spr_msr_spv , + dout => msr_spv_q); +msr_ucle_latch : tri_rlmreg_p + generic map (width => msr_ucle_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_w_int_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(msr_ucle_offset to msr_ucle_offset + msr_ucle_q'length-1), + scout => sov(msr_ucle_offset to msr_ucle_offset + msr_ucle_q'length-1), + din => spr_msr_ucle , + dout => msr_ucle_q); +msrp_uclep_latch : tri_rlmreg_p + generic map (width => msrp_uclep_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(msrp_uclep_offset to msrp_uclep_offset + msrp_uclep_q'length-1), + scout => sov(msrp_uclep_offset to msrp_uclep_offset + msrp_uclep_q'length-1), + din => spr_msrp_uclep , + dout => msrp_uclep_q); +pc_dbg_action_latch : tri_rlmreg_p + generic map (width => pc_dbg_action_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(pc_dbg_action_offset to pc_dbg_action_offset + pc_dbg_action_q'length-1), + scout => sov(pc_dbg_action_offset to pc_dbg_action_offset + pc_dbg_action_q'length-1), + din => pc_xu_dbg_action , + dout => pc_dbg_action_q); +pc_dbg_stop_latch : tri_rlmreg_p + generic map (width => pc_dbg_stop_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(pc_dbg_stop_offset to pc_dbg_stop_offset + pc_dbg_stop_q'length-1), + scout => sov(pc_dbg_stop_offset to pc_dbg_stop_offset + pc_dbg_stop_q'length-1), + din => pc_dbg_stop_d, + dout => pc_dbg_stop_q); +pc_dbg_stop_2_latch : tri_rlmreg_p + generic map (width => pc_dbg_stop_2_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(pc_dbg_stop_2_offset to pc_dbg_stop_2_offset + pc_dbg_stop_2_q'length-1), + scout => sov(pc_dbg_stop_2_offset to pc_dbg_stop_2_offset + pc_dbg_stop_2_q'length-1), + din => pc_dbg_stop, + dout => pc_dbg_stop_2_q); +pc_err_mcsr_rpt_latch : tri_rlmreg_p + generic map (width => pc_err_mcsr_rpt_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(pc_err_mcsr_rpt_offset to pc_err_mcsr_rpt_offset + pc_err_mcsr_rpt_q'length-1), + scout => sov(pc_err_mcsr_rpt_offset to pc_err_mcsr_rpt_offset + pc_err_mcsr_rpt_q'length-1), + din => pc_err_mcsr_rpt_d, + dout => pc_err_mcsr_rpt_q); +pc_err_mcsr_summary_latch : tri_rlmreg_p + generic map (width => pc_err_mcsr_summary_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(pc_err_mcsr_summary_offset to pc_err_mcsr_summary_offset + pc_err_mcsr_summary_q'length-1), + scout => sov(pc_err_mcsr_summary_offset to pc_err_mcsr_summary_offset + pc_err_mcsr_summary_q'length-1), + din => pc_err_mcsr_summary_d, + dout => pc_err_mcsr_summary_q); +pc_init_reset_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(pc_init_reset_offset), + scout => sov(pc_init_reset_offset), + din => pc_xu_init_reset , + dout => pc_init_reset_q); +quiesced_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(quiesced_offset), + scout => sov(quiesced_offset), + din => quiesced_d, + dout => quiesced_q); +ram_flush_latch : tri_rlmreg_p + generic map (width => ram_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ram_flush_offset to ram_flush_offset + ram_flush_q'length-1), + scout => sov(ram_flush_offset to ram_flush_offset + ram_flush_q'length-1), + din => ram_flush_d, + dout => ram_flush_q); +ram_ip_latch : tri_rlmreg_p + generic map (width => ram_ip_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ram_ip_offset to ram_ip_offset + ram_ip_q'length-1), + scout => sov(ram_ip_offset to ram_ip_offset + ram_ip_q'length-1), + din => ram_ip_d, + dout => ram_ip_q); +ram_mode_latch : tri_rlmreg_p + generic map (width => ram_mode_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ram_mode_offset to ram_mode_offset + ram_mode_q'length-1), + scout => sov(ram_mode_offset to ram_mode_offset + ram_mode_q'length-1), + din => ram_mode_d, + dout => ram_mode_q); +slowspr_flush_latch : tri_rlmreg_p + generic map (width => slowspr_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(slowspr_flush_offset to slowspr_flush_offset + slowspr_flush_q'length-1), + scout => sov(slowspr_flush_offset to slowspr_flush_offset + slowspr_flush_q'length-1), + din => mux_cpl_slowspr_flush , + dout => slowspr_flush_q); +spr_cpl_async_int_latch : tri_rlmreg_p + generic map (width => spr_cpl_async_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(spr_cpl_async_int_offset to spr_cpl_async_int_offset + spr_cpl_async_int_q'length-1), + scout => sov(spr_cpl_async_int_offset to spr_cpl_async_int_offset + spr_cpl_async_int_q'length-1), + din => spr_cpl_async_int , + dout => spr_cpl_async_int_q); +ram_execute_latch : tri_rlmreg_p + generic map (width => ram_execute_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ram_execute_offset to ram_execute_offset + ram_execute_q'length-1), + scout => sov(ram_execute_offset to ram_execute_offset + ram_execute_q'length-1), + din => ram_execute_d, + dout => ram_execute_q); +ssprwr_ip_latch : tri_rlmreg_p + generic map (width => ssprwr_ip_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ssprwr_ip_offset to ssprwr_ip_offset + ssprwr_ip_q'length-1), + scout => sov(ssprwr_ip_offset to ssprwr_ip_offset + ssprwr_ip_q'length-1), + din => ssprwr_ip_d, + dout => ssprwr_ip_q); +exx_cm_hold_latch : tri_rlmreg_p + generic map (width => exx_cm_hold_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(exx_cm_hold_offset to exx_cm_hold_offset + exx_cm_hold_q'length-1), + scout => sov(exx_cm_hold_offset to exx_cm_hold_offset + exx_cm_hold_q'length-1), + din => exx_cm_hold , + dout => exx_cm_hold_q); +xu_ex1_n_flush_latch : tri_rlmreg_p + generic map (width => xu_ex1_n_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_flush_inf_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xu_ex1_n_flush_offset to xu_ex1_n_flush_offset + xu_ex1_n_flush_q'length-1), + scout => sov(xu_ex1_n_flush_offset to xu_ex1_n_flush_offset + xu_ex1_n_flush_q'length-1), + din => rf1_flush , + dout => xu_ex1_n_flush_q); +xu_ex1_s_flush_latch : tri_rlmreg_p + generic map (width => xu_ex1_s_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_flush_inf_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xu_ex1_s_flush_offset to xu_ex1_s_flush_offset + xu_ex1_s_flush_q'length-1), + scout => sov(xu_ex1_s_flush_offset to xu_ex1_s_flush_offset + xu_ex1_s_flush_q'length-1), + din => rf1_flush , + dout => xu_ex1_s_flush_q); +xu_ex1_w_flush_latch : tri_rlmreg_p + generic map (width => xu_ex1_w_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_flush_inf_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xu_ex1_w_flush_offset to xu_ex1_w_flush_offset + xu_ex1_w_flush_q'length-1), + scout => sov(xu_ex1_w_flush_offset to xu_ex1_w_flush_offset + xu_ex1_w_flush_q'length-1), + din => rf1_flush , + dout => xu_ex1_w_flush_q); +xu_ex2_n_flush_latch : tri_rlmreg_p + generic map (width => xu_ex2_n_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_flush_inf_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xu_ex2_n_flush_offset to xu_ex2_n_flush_offset + xu_ex2_n_flush_q'length-1), + scout => sov(xu_ex2_n_flush_offset to xu_ex2_n_flush_offset + xu_ex2_n_flush_q'length-1), + din => ex1_flush , + dout => xu_ex2_n_flush_q); +xu_ex2_s_flush_latch : tri_rlmreg_p + generic map (width => xu_ex2_s_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_flush_inf_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xu_ex2_s_flush_offset to xu_ex2_s_flush_offset + xu_ex2_s_flush_q'length-1), + scout => sov(xu_ex2_s_flush_offset to xu_ex2_s_flush_offset + xu_ex2_s_flush_q'length-1), + din => ex1_flush , + dout => xu_ex2_s_flush_q); +xu_ex2_w_flush_latch : tri_rlmreg_p + generic map (width => xu_ex2_w_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_flush_inf_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xu_ex2_w_flush_offset to xu_ex2_w_flush_offset + xu_ex2_w_flush_q'length-1), + scout => sov(xu_ex2_w_flush_offset to xu_ex2_w_flush_offset + xu_ex2_w_flush_q'length-1), + din => ex1_flush , + dout => xu_ex2_w_flush_q); +xu_ex3_n_flush_latch : tri_rlmreg_p + generic map (width => xu_ex3_n_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_flush_inf_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xu_ex3_n_flush_offset to xu_ex3_n_flush_offset + xu_ex3_n_flush_q'length-1), + scout => sov(xu_ex3_n_flush_offset to xu_ex3_n_flush_offset + xu_ex3_n_flush_q'length-1), + din => ex2_flush , + dout => xu_ex3_n_flush_q); +xu_ex3_s_flush_latch : tri_rlmreg_p + generic map (width => xu_ex3_s_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_flush_inf_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xu_ex3_s_flush_offset to xu_ex3_s_flush_offset + xu_ex3_s_flush_q'length-1), + scout => sov(xu_ex3_s_flush_offset to xu_ex3_s_flush_offset + xu_ex3_s_flush_q'length-1), + din => ex2_flush , + dout => xu_ex3_s_flush_q); +xu_ex3_w_flush_latch : tri_rlmreg_p + generic map (width => xu_ex3_w_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_flush_inf_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xu_ex3_w_flush_offset to xu_ex3_w_flush_offset + xu_ex3_w_flush_q'length-1), + scout => sov(xu_ex3_w_flush_offset to xu_ex3_w_flush_offset + xu_ex3_w_flush_q'length-1), + din => ex2_flush , + dout => xu_ex3_w_flush_q); +xu_ex4_n_flush_latch : tri_rlmreg_p + generic map (width => xu_ex4_n_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_flush_inf_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xu_ex4_n_flush_offset to xu_ex4_n_flush_offset + xu_ex4_n_flush_q'length-1), + scout => sov(xu_ex4_n_flush_offset to xu_ex4_n_flush_offset + xu_ex4_n_flush_q'length-1), + din => ex3_flush , + dout => xu_ex4_n_flush_q); +xu_ex4_s_flush_latch : tri_rlmreg_p + generic map (width => xu_ex4_s_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_flush_inf_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xu_ex4_s_flush_offset to xu_ex4_s_flush_offset + xu_ex4_s_flush_q'length-1), + scout => sov(xu_ex4_s_flush_offset to xu_ex4_s_flush_offset + xu_ex4_s_flush_q'length-1), + din => ex3_flush , + dout => xu_ex4_s_flush_q); +xu_ex4_w_flush_latch : tri_rlmreg_p + generic map (width => xu_ex4_w_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_flush_inf_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xu_ex4_w_flush_offset to xu_ex4_w_flush_offset + xu_ex4_w_flush_q'length-1), + scout => sov(xu_ex4_w_flush_offset to xu_ex4_w_flush_offset + xu_ex4_w_flush_q'length-1), + din => ex3_flush , + dout => xu_ex4_w_flush_q); +xu_ex5_n_flush_latch : tri_rlmreg_p + generic map (width => xu_ex5_n_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_flush_inf_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xu_ex5_n_flush_offset to xu_ex5_n_flush_offset + xu_ex5_n_flush_q'length-1), + scout => sov(xu_ex5_n_flush_offset to xu_ex5_n_flush_offset + xu_ex5_n_flush_q'length-1), + din => ex4_flush , + dout => xu_ex5_n_flush_q); +xu_ex5_s_flush_latch : tri_rlmreg_p + generic map (width => xu_ex5_s_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_flush_inf_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xu_ex5_s_flush_offset to xu_ex5_s_flush_offset + xu_ex5_s_flush_q'length-1), + scout => sov(xu_ex5_s_flush_offset to xu_ex5_s_flush_offset + xu_ex5_s_flush_q'length-1), + din => ex4_flush , + dout => xu_ex5_s_flush_q); +xu_ex5_w_flush_latch : tri_rlmreg_p + generic map (width => xu_ex5_w_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_flush_inf_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xu_ex5_w_flush_offset to xu_ex5_w_flush_offset + xu_ex5_w_flush_q'length-1), + scout => sov(xu_ex5_w_flush_offset to xu_ex5_w_flush_offset + xu_ex5_w_flush_q'length-1), + din => ex4_flush , + dout => xu_ex5_w_flush_q); +xu_is2_n_flush_latch : tri_rlmreg_p + generic map (width => xu_is2_n_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_flush_inf_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xu_is2_n_flush_offset to xu_is2_n_flush_offset + xu_is2_n_flush_q'length-1), + scout => sov(xu_is2_n_flush_offset to xu_is2_n_flush_offset + xu_is2_n_flush_q'length-1), + din => any_flush , + dout => xu_is2_n_flush_q); +xu_rf0_n_flush_latch : tri_rlmreg_p + generic map (width => xu_rf0_n_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_flush_inf_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xu_rf0_n_flush_offset to xu_rf0_n_flush_offset + xu_rf0_n_flush_q'length-1), + scout => sov(xu_rf0_n_flush_offset to xu_rf0_n_flush_offset + xu_rf0_n_flush_q'length-1), + din => is2_flush , + dout => xu_rf0_n_flush_q); +xu_rf1_n_flush_latch : tri_rlmreg_p + generic map (width => xu_rf1_n_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_flush_inf_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xu_rf1_n_flush_offset to xu_rf1_n_flush_offset + xu_rf1_n_flush_q'length-1), + scout => sov(xu_rf1_n_flush_offset to xu_rf1_n_flush_offset + xu_rf1_n_flush_q'length-1), + din => rf0_flush , + dout => xu_rf1_n_flush_q); +xu_rf1_s_flush_latch : tri_rlmreg_p + generic map (width => xu_rf1_s_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_flush_inf_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xu_rf1_s_flush_offset to xu_rf1_s_flush_offset + xu_rf1_s_flush_q'length-1), + scout => sov(xu_rf1_s_flush_offset to xu_rf1_s_flush_offset + xu_rf1_s_flush_q'length-1), + din => rf0_flush , + dout => xu_rf1_s_flush_q); +xu_rf1_w_flush_latch : tri_rlmreg_p + generic map (width => xu_rf1_w_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_flush_inf_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xu_rf1_w_flush_offset to xu_rf1_w_flush_offset + xu_rf1_w_flush_q'length-1), + scout => sov(xu_rf1_w_flush_offset to xu_rf1_w_flush_offset + xu_rf1_w_flush_q'length-1), + din => rf0_flush , + dout => xu_rf1_w_flush_q); +ex5_np1_irpt_dbg_cint_latch : tri_rlmreg_p + generic map (width => ex5_np1_irpt_dbg_cint_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_np1_irpt_dbg_cint_offset to ex5_np1_irpt_dbg_cint_offset + ex5_np1_irpt_dbg_cint_q'length-1), + scout => sov(ex5_np1_irpt_dbg_cint_offset to ex5_np1_irpt_dbg_cint_offset + ex5_np1_irpt_dbg_cint_q'length-1), + din => ex4_np1_irpt_dbg_cint, + dout => ex5_np1_irpt_dbg_cint_q); +ex6_np1_irpt_dbg_cint_latch : tri_rlmreg_p + generic map (width => ex6_np1_irpt_dbg_cint_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_np1_irpt_dbg_cint_offset to ex6_np1_irpt_dbg_cint_offset + ex6_np1_irpt_dbg_cint_q'length-1), + scout => sov(ex6_np1_irpt_dbg_cint_offset to ex6_np1_irpt_dbg_cint_offset + ex6_np1_irpt_dbg_cint_q'length-1), + din => ex6_np1_irpt_dbg_cint_d, + dout => ex6_np1_irpt_dbg_cint_q); +ex5_np1_irpt_dbg_event_latch : tri_rlmreg_p + generic map (width => ex5_np1_irpt_dbg_event_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_np1_irpt_dbg_event_offset to ex5_np1_irpt_dbg_event_offset + ex5_np1_irpt_dbg_event_q'length-1), + scout => sov(ex5_np1_irpt_dbg_event_offset to ex5_np1_irpt_dbg_event_offset + ex5_np1_irpt_dbg_event_q'length-1), + din => ex4_np1_irpt_dbg_event, + dout => ex5_np1_irpt_dbg_event_q); +ex6_np1_irpt_dbg_event_latch : tri_rlmreg_p + generic map (width => ex6_np1_irpt_dbg_event_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_np1_irpt_dbg_event_offset to ex6_np1_irpt_dbg_event_offset + ex6_np1_irpt_dbg_event_q'length-1), + scout => sov(ex6_np1_irpt_dbg_event_offset to ex6_np1_irpt_dbg_event_offset + ex6_np1_irpt_dbg_event_q'length-1), + din => ex6_np1_irpt_dbg_event_d, + dout => ex6_np1_irpt_dbg_event_q); +clkg_ctl_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(clkg_ctl_offset), + scout => sov(clkg_ctl_offset), + din => spr_xucr0_clkg_ctl(2) , + dout => clkg_ctl_q); +xu_rf_seq_end_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xu_rf_seq_end_offset), + scout => sov(xu_rf_seq_end_offset), + din => gpr_cpl_regfile_seq_end , + dout => xu_rf_seq_end_q); +xu_rfpe_ack_latch : tri_rlmreg_p + generic map (width => xu_rfpe_ack_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xu_rfpe_ack_offset to xu_rfpe_ack_offset + xu_rfpe_ack_q'length-1), + scout => sov(xu_rfpe_ack_offset to xu_rfpe_ack_offset + xu_rfpe_ack_q'length-1), + din => xu_rfpe_ack_d, + dout => xu_rfpe_ack_q); +xu_rfpe_hold_present_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xu_rfpe_hold_present_offset), + scout => sov(xu_rfpe_hold_present_offset), + din => xu_rfpe_hold_present_d, + dout => xu_rfpe_hold_present_q); +exx_act_latch : tri_rlmreg_p + generic map (width => exx_act_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(exx_act_offset to exx_act_offset + exx_act_q'length-1), + scout => sov(exx_act_offset to exx_act_offset + exx_act_q'length-1), + din => exx_act_d, + dout => exx_act_q); +ex4_mchk_int_en_latch : tri_rlmreg_p + generic map (width => ex4_mchk_int_en_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_mchk_int_en_offset to ex4_mchk_int_en_offset + ex4_mchk_int_en_q'length-1), + scout => sov(ex4_mchk_int_en_offset to ex4_mchk_int_en_offset + ex4_mchk_int_en_q'length-1), + din => ex3_mchk_int_en, + dout => ex4_mchk_int_en_q); +ex5_mchk_int_en_latch : tri_rlmreg_p + generic map (width => ex5_mchk_int_en_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_mchk_int_en_offset to ex5_mchk_int_en_offset + ex5_mchk_int_en_q'length-1), + scout => sov(ex5_mchk_int_en_offset to ex5_mchk_int_en_offset + ex5_mchk_int_en_q'length-1), + din => ex4_mchk_int_en_q, + dout => ex5_mchk_int_en_q); +trace_bus_enable_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(trace_bus_enable_offset), + scout => sov(trace_bus_enable_offset), + din => pc_xu_trace_bus_enable , + dout => trace_bus_enable_q); +ex1_instr_trace_type_latch : tri_rlmreg_p + generic map (width => ex1_instr_trace_type_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_instr_trace_type_offset to ex1_instr_trace_type_offset + ex1_instr_trace_type_q'length-1), + scout => sov(ex1_instr_trace_type_offset to ex1_instr_trace_type_offset + ex1_instr_trace_type_q'length-1), + din => dec_cpl_rf1_instr_trace_type, + dout => ex1_instr_trace_type_q); +ex1_instr_trace_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_instr_trace_val_offset), + scout => sov(ex1_instr_trace_val_offset), + din => dec_cpl_rf1_instr_trace_val, + dout => ex1_instr_trace_val_q); +ex1_xu_issued_latch : tri_rlmreg_p + generic map (width => ex1_xu_issued_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_xu_issued_offset to ex1_xu_issued_offset + ex1_xu_issued_q'length-1), + scout => sov(ex1_xu_issued_offset to ex1_xu_issued_offset + ex1_xu_issued_q'length-1), + din => dec_cpl_rf1_issued , + dout => ex1_xu_issued_q); +ex2_xu_issued_latch : tri_rlmreg_p + generic map (width => ex2_xu_issued_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_xu_issued_offset to ex2_xu_issued_offset + ex2_xu_issued_q'length-1), + scout => sov(ex2_xu_issued_offset to ex2_xu_issued_offset + ex2_xu_issued_q'length-1), + din => ex1_xu_issued_q , + dout => ex2_xu_issued_q); +ex3_xu_issued_latch : tri_rlmreg_p + generic map (width => ex3_xu_issued_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_xu_issued_offset to ex3_xu_issued_offset + ex3_xu_issued_q'length-1), + scout => sov(ex3_xu_issued_offset to ex3_xu_issued_offset + ex3_xu_issued_q'length-1), + din => ex2_xu_issued_q , + dout => ex3_xu_issued_q); +ex4_xu_issued_latch : tri_rlmreg_p + generic map (width => ex4_xu_issued_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_xu_issued_offset to ex4_xu_issued_offset + ex4_xu_issued_q'length-1), + scout => sov(ex4_xu_issued_offset to ex4_xu_issued_offset + ex4_xu_issued_q'length-1), + din => ex3_xu_issued , + dout => ex4_xu_issued_q); +ex3_axu_issued_latch : tri_rlmreg_p + generic map (width => ex3_axu_issued_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_axu_issued_offset to ex3_axu_issued_offset + ex3_axu_issued_q'length-1), + scout => sov(ex3_axu_issued_offset to ex3_axu_issued_offset + ex3_axu_issued_q'length-1), + din => fu_xu_ex2_ifar_issued , + dout => ex3_axu_issued_q); +ex4_axu_issued_latch : tri_rlmreg_p + generic map (width => ex4_axu_issued_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_axu_issued_offset to ex4_axu_issued_offset + ex4_axu_issued_q'length-1), + scout => sov(ex4_axu_issued_offset to ex4_axu_issued_offset + ex4_axu_issued_q'length-1), + din => ex3_axu_issued_q , + dout => ex4_axu_issued_q); +ex2_instr_dbg_latch : tri_rlmreg_p + generic map (width => ex2_instr_dbg_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_instr_dbg_offset to ex2_instr_dbg_offset + ex2_instr_dbg_q'length-1), + scout => sov(ex2_instr_dbg_offset to ex2_instr_dbg_offset + ex2_instr_dbg_q'length-1), + din => ex1_instr , + dout => ex2_instr_dbg_q); +ex2_instr_trace_type_latch : tri_rlmreg_p + generic map (width => ex2_instr_trace_type_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_instr_trace_type_offset to ex2_instr_trace_type_offset + ex2_instr_trace_type_q'length-1), + scout => sov(ex2_instr_trace_type_offset to ex2_instr_trace_type_offset + ex2_instr_trace_type_q'length-1), + din => ex1_instr_trace_type_q , + dout => ex2_instr_trace_type_q); +ex4_instr_trace_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_instr_trace_val_offset), + scout => sov(ex4_instr_trace_val_offset), + din => dec_cpl_ex3_instr_trace_val, + dout => ex4_instr_trace_val_q); +ex5_axu_val_dbg_latch : tri_regk + generic map (width => ex5_axu_val_dbg_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex4_axu_val , + dout => ex5_axu_val_dbg_q); +ex5_instr_cpl_dbg_latch : tri_regk + generic map (width => ex5_instr_cpl_dbg_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex4_instr_cpl , + dout => ex5_instr_cpl_dbg_q); +ex5_instr_trace_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_instr_trace_val_offset), + scout => sov(ex5_instr_trace_val_offset), + din => ex4_instr_trace_val_q , + dout => ex5_instr_trace_val_q); +ex5_siar_latch : tri_rlmreg_p + generic map (width => ex5_siar_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_siar_offset to ex5_siar_offset + ex5_siar_q'length-1), + scout => sov(ex5_siar_offset to ex5_siar_offset + ex5_siar_q'length-1), + din => ex5_siar_d, + dout => ex5_siar_q); +ex5_siar_cpl_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_siar_cpl_offset), + scout => sov(ex5_siar_cpl_offset), + din => ex5_siar_cpl_d, + dout => ex5_siar_cpl_q); +ex5_siar_gs_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_siar_gs_offset), + scout => sov(ex5_siar_gs_offset), + din => ex5_siar_gs_d, + dout => ex5_siar_gs_q); +ex5_siar_issued_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_siar_issued_offset), + scout => sov(ex5_siar_issued_offset), + din => ex5_siar_issued_d, + dout => ex5_siar_issued_q); +ex5_siar_pr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_siar_pr_offset), + scout => sov(ex5_siar_pr_offset), + din => ex5_siar_pr_d, + dout => ex5_siar_pr_q); +ex5_siar_tid_latch : tri_rlmreg_p + generic map (width => ex5_siar_tid_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_siar_tid_offset to ex5_siar_tid_offset + ex5_siar_tid_q'length-1), + scout => sov(ex5_siar_tid_offset to ex5_siar_tid_offset + ex5_siar_tid_q'length-1), + din => ex5_siar_tid_d, + dout => ex5_siar_tid_q); +ex5_ucode_end_dbg_latch : tri_rlmreg_p + generic map (width => ex5_ucode_end_dbg_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_ucode_end_dbg_offset to ex5_ucode_end_dbg_offset + ex5_ucode_end_dbg_q'length-1), + scout => sov(ex5_ucode_end_dbg_offset to ex5_ucode_end_dbg_offset + ex5_ucode_end_dbg_q'length-1), + din => ex4_ucode_end , + dout => ex5_ucode_end_dbg_q); +ex5_ucode_val_dbg_latch : tri_rlmreg_p + generic map (width => ex5_ucode_val_dbg_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_ucode_val_dbg_offset to ex5_ucode_val_dbg_offset + ex5_ucode_val_dbg_q'length-1), + scout => sov(ex5_ucode_val_dbg_offset to ex5_ucode_val_dbg_offset + ex5_ucode_val_dbg_q'length-1), + din => ex4_ucode_val , + dout => ex5_ucode_val_dbg_q); +instr_trace_mode_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(instr_trace_mode_offset), + scout => sov(instr_trace_mode_offset), + din => pc_xu_instr_trace_mode , + dout => instr_trace_mode_q); +debug_data_out_latch : tri_rlmreg_p + generic map (width => debug_data_out_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(debug_data_out_offset to debug_data_out_offset + debug_data_out_q'length-1), + scout => sov(debug_data_out_offset to debug_data_out_offset + debug_data_out_q'length-1), + din => debug_data_out_d, + dout => debug_data_out_q); +debug_mux_ctrls_latch : tri_rlmreg_p + generic map (width => debug_mux_ctrls_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(debug_mux_ctrls_offset to debug_mux_ctrls_offset + debug_mux_ctrls_q'length-1), + scout => sov(debug_mux_ctrls_offset to debug_mux_ctrls_offset + debug_mux_ctrls_q'length-1), + din => cpl_debug_mux_ctrls , + dout => debug_mux_ctrls_q); +debug_mux_ctrls_int_latch : tri_rlmreg_p + generic map (width => debug_mux_ctrls_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(debug_mux_ctrls_int_offset to debug_mux_ctrls_int_offset + debug_mux_ctrls_int_q'length-1), + scout => sov(debug_mux_ctrls_int_offset to debug_mux_ctrls_int_offset + debug_mux_ctrls_int_q'length-1), + din => debug_mux_ctrls_int, + dout => debug_mux_ctrls_int_q); +trigger_data_out_latch : tri_rlmreg_p + generic map (width => trigger_data_out_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(trigger_data_out_offset to trigger_data_out_offset + trigger_data_out_q'length-1), + scout => sov(trigger_data_out_offset to trigger_data_out_offset + trigger_data_out_q'length-1), + din => trigger_data_out_d, + dout => trigger_data_out_q); +event_bus_enable_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(event_bus_enable_offset), + scout => sov(event_bus_enable_offset), + din => pc_xu_event_bus_enable , + dout => event_bus_enable_q); +ex2_perf_event_latch : tri_regk + generic map (width => ex2_perf_event_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => event_bus_enable_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex2_perf_event_d, + dout => ex2_perf_event_q); +ex3_perf_event_latch : tri_rlmreg_p + generic map (width => ex3_perf_event_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => event_bus_enable_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_perf_event_offset to ex3_perf_event_offset + ex3_perf_event_q'length-1), + scout => sov(ex3_perf_event_offset to ex3_perf_event_offset + ex3_perf_event_q'length-1), + din => ex2_perf_event_q , + dout => ex3_perf_event_q); +ex4_perf_event_latch : tri_regk + generic map (width => ex4_perf_event_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => event_bus_enable_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex4_perf_event_d, + dout => ex4_perf_event_q); +ex5_perf_event_latch : tri_rlmreg_p + generic map (width => ex5_perf_event_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => event_bus_enable_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_perf_event_offset to ex5_perf_event_offset + ex5_perf_event_q'length-1), + scout => sov(ex5_perf_event_offset to ex5_perf_event_offset + ex5_perf_event_q'length-1), + din => ex5_perf_event_d, + dout => ex5_perf_event_q); +spr_bit_act_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(spr_bit_act_offset), + scout => sov(spr_bit_act_offset), + din => spr_bit_act, + dout => spr_bit_act_q); + + +dd1_clk_override_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc, + thold_b => ccfg_so_thold_0_b, + scin => siv_ccfg(dd1_clk_override_offset_ccfg to dd1_clk_override_offset_ccfg), + scout => sov_ccfg(dd1_clk_override_offset_ccfg to dd1_clk_override_offset_ccfg), + dout(0) => clk_override_q); + + +spare_0_lcb: entity tri.tri_lcbnd(tri_lcbnd) + port map(vd => vdd, + gd => gnd, + act => tidn, + nclk => nclk, + forcee => func_sl_force, + thold_b => func_sl_thold_0_b, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + sg => sg_0, + lclk => spare_0_lclk, + d1clk => spare_0_d1clk, + d2clk => spare_0_d2clk); +spare_0_latch : entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width => spare_0_q'length, expand_type => expand_type, btr => "NLI0001_X2_A12TH", init=>(spare_0_q'range=>'0')) + port map (vd => vdd, gd => gnd, + LCLK => spare_0_lclk, + D1CLK => spare_0_d1clk, + D2CLK => spare_0_d2clk, + SCANIN => siv(spare_0_offset to spare_0_offset + spare_0_q'length-1), + SCANOUT => sov(spare_0_offset to spare_0_offset + spare_0_q'length-1), + D => spare_0_d, + QB => spare_0_q); +spare_0_d <= not spare_0_q; + +spare_1_lcb: entity tri.tri_lcbnd(tri_lcbnd) + port map(vd => vdd, + gd => gnd, + act => tiup, + nclk => nclk, + forcee => func_sl_force, + thold_b => func_sl_thold_0_b, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + sg => sg_0, + lclk => spare_1_lclk, + d1clk => spare_1_d1clk, + d2clk => spare_1_d2clk); +spare_1_latch : entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width => spare_1_q'length, expand_type => expand_type, btr => "NLI0001_X2_A12TH", init=>(spare_1_q'range=>'0')) + port map (vd => vdd, gd => gnd, + LCLK => spare_1_lclk, + D1CLK => spare_1_d1clk, + D2CLK => spare_1_d2clk, + SCANIN => siv(spare_1_offset to spare_1_offset + spare_1_q'length-1), + SCANOUT => sov(spare_1_offset to spare_1_offset + spare_1_q'length-1), + D => spare_1_d, + QB => spare_1_q); +-- Need to account for cycles between ex4 & ex7... +spare_1_d(0 to 3) <= not (ex4_instr_cpl and not ex5_in_ucode_q); -- EX5 +spare_1_d(4 to 7) <= not spare_1_q(0 to 3); -- EX6 +spare_1_d(8 to 11) <= not spare_1_q(4 to 7); -- EX7 +spare_1_d(12 to 15) <= not spare_1_q(12 to 15); + + +spare_2_lcb: entity tri.tri_lcbnd(tri_lcbnd) + port map(vd => vdd, + gd => gnd, + act => tidn, + nclk => nclk, + forcee => func_sl_force, + thold_b => func_sl_thold_0_b, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + sg => sg_0, + lclk => spare_2_lclk, + d1clk => spare_2_d1clk, + d2clk => spare_2_d2clk); +spare_2_latch : entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width => spare_2_q'length, expand_type => expand_type, btr => "NLI0001_X2_A12TH", init=>(spare_2_q'range=>'0')) + port map (vd => vdd, gd => gnd, + LCLK => spare_2_lclk, + D1CLK => spare_2_d1clk, + D2CLK => spare_2_d2clk, + SCANIN => siv(spare_2_offset to spare_2_offset + spare_2_q'length-1), + SCANOUT => sov(spare_2_offset to spare_2_offset + spare_2_q'length-1), + D => spare_2_d, + QB => spare_2_q); +spare_2_d <= not spare_2_q; + +spare_3_lcb: entity tri.tri_lcbnd(tri_lcbnd) + port map(vd => vdd, + gd => gnd, + act => tidn, + nclk => nclk, + forcee => func_sl_force, + thold_b => func_sl_thold_0_b, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + sg => sg_0, + lclk => spare_3_lclk, + d1clk => spare_3_d1clk, + d2clk => spare_3_d2clk); +spare_3_latch : entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width => spare_3_q'length, expand_type => expand_type, btr => "NLI0001_X2_A12TH", init=>(spare_3_q'range=>'0')) + port map (vd => vdd, gd => gnd, + LCLK => spare_3_lclk, + D1CLK => spare_3_d1clk, + D2CLK => spare_3_d2clk, + SCANIN => siv(spare_3_offset to spare_3_offset + spare_3_q'length-1), + SCANOUT => sov(spare_3_offset to spare_3_offset + spare_3_q'length-1), + D => spare_3_d, + QB => spare_3_q); +spare_3_d <= not spare_3_q; + +spare_4_lcb: entity tri.tri_lcbnd(tri_lcbnd) + port map(vd => vdd, + gd => gnd, + act => tiup, + nclk => nclk, + forcee => func_sl_force, + thold_b => func_sl_thold_0_b, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + sg => sg_0, + lclk => spare_4_lclk, + d1clk => spare_4_d1clk, + d2clk => spare_4_d2clk); +spare_4_latch : entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width => spare_4_q'length, expand_type => expand_type, btr => "NLI0001_X2_A12TH", init=>(spare_4_q'range=>'0')) + port map (vd => vdd, gd => gnd, + LCLK => spare_4_lclk, + D1CLK => spare_4_d1clk, + D2CLK => spare_4_d2clk, + SCANIN => siv(spare_4_offset to spare_4_offset + spare_4_q'length-1), + SCANOUT => sov(spare_4_offset to spare_4_offset + spare_4_q'length-1), + D => spare_4_d, + QB => spare_4_q); + +spare_5_lcb: entity tri.tri_lcbnd(tri_lcbnd) + port map(vd => vdd, + gd => gnd, + act => tiup, + nclk => nclk, + forcee => func_sl_force, + thold_b => func_sl_thold_0_b, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + sg => sg_0, + lclk => spare_5_lclk, + d1clk => spare_5_d1clk, + d2clk => spare_5_d2clk); +spare_5_latch : entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width => spare_5_q'length, expand_type => expand_type, btr => "NLI0001_X2_A12TH", init=>(spare_5_q'range=>'0')) + port map (vd => vdd, gd => gnd, + LCLK => spare_5_lclk, + D1CLK => spare_5_d1clk, + D2CLK => spare_5_d2clk, + SCANIN => siv(spare_5_offset to spare_5_offset + spare_5_q'length-1), + SCANOUT => sov(spare_5_offset to spare_5_offset + spare_5_q'length-1), + D => spare_5_d, + QB => spare_5_q); + + + + + + + + +ex4_dac_cmpr_gem : for t in 1 to 4 generate + ex4_dacr_cmpr_latch : tri_regk + generic map (width => ex4_dacr_cmpr_q(t)'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex4_dacr_cmpr_d(t), + dout => ex4_dacr_cmpr_q(t)); + ex4_dacw_cmpr_latch : tri_regk + generic map (width => ex4_dacw_cmpr_q(t)'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex4_dacw_cmpr_d(t), + dout => ex4_dacw_cmpr_q(t)); +end generate; + +ex5_late_flush_gen : for t in 0 to ifar_repwr-1 generate + ex5_late_flush_latch : tri_rlmreg_p + generic map (width => ex5_late_flush_q(t)'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_flush_inf_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_late_flush_offset+ex5_late_flush_q(t)'length*t to ex5_late_flush_offset + ex5_late_flush_q(t)'length*(t+1)-1), + scout => sov(ex5_late_flush_offset+ex5_late_flush_q(t)'length*t to ex5_late_flush_offset + ex5_late_flush_q(t)'length*(t+1)-1), + din => ex5_late_flush_d(t), + dout => ex5_late_flush_q(t)); +end generate; +ex2_ifar_b_latch_gen : for t in 0 to threads-1 generate + ex2_ifar_b_latch : entity tri.tri_aoi22_nlats_wlcb(tri_aoi22_nlats_wlcb) + generic map (width => eff_ifar, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_ifar_act(t), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_ifar_b_offset+eff_ifar*t to ex2_ifar_b_offset+eff_ifar*(t+1)-1), + scout => sov(ex2_ifar_b_offset+eff_ifar*t to ex2_ifar_b_offset+eff_ifar*(t+1)-1), + A1 => fu_xu_ex1_ifar(eff_ifar*t to eff_ifar*(t+1)-1), + A2 => ex1_ifar_sel_b(eff_ifar*t to eff_ifar*(t+1)-1), + B1 => ex1_xu_ifar, + B2 => ex1_ifar_sel(eff_ifar*t to eff_ifar*(t+1)-1), + QB => ex2_ifar_b_q(eff_ifar*t to eff_ifar*(t+1)-1)); + ex1_ifar_sel(eff_ifar*t to eff_ifar*(t+1)-1) <= (others=> (ex1_xu_val_q(t) or ex1_ucode_val_q(t))); + ex1_ifar_sel_b(eff_ifar*t to eff_ifar*(t+1)-1) <= (others=>not(ex1_xu_val_q(t) or ex1_ucode_val_q(t))); + + ex3_ifar_latch : tri_rlmreg_p + generic map (width => eff_ifar, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_ifar_act(t), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_ifar_offset+eff_ifar*t to ex3_ifar_offset+eff_ifar*(t+1)-1), + scout => sov(ex3_ifar_offset+eff_ifar*t to ex3_ifar_offset+eff_ifar*(t+1)-1), + din => ex2_ifar(eff_ifar*t to eff_ifar*(t+1)-1), + dout => ex3_ifar_q(eff_ifar*t to eff_ifar*(t+1)-1)); + ex4_ifar_latch : tri_rlmreg_p + generic map (width => eff_ifar, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex3_ifar_act(t), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_ifar_offset+eff_ifar*t to ex4_ifar_offset+eff_ifar*(t+1)-1), + scout => sov(ex4_ifar_offset+eff_ifar*t to ex4_ifar_offset+eff_ifar*(t+1)-1), + din => ex3_ifar_q(eff_ifar*t to eff_ifar*(t+1)-1), + dout => ex4_ifar_q(eff_ifar*t to eff_ifar*(t+1)-1)); +end generate; + +------------------------------------------------- +-- Pervasive +------------------------------------------------- +perv_2to1_reg: tri_plat + generic map (width => 8, expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_xu_ccflush_dc, + din(0) => func_slp_sl_thold_2, + din(1) => func_slp_nsl_thold_2, + din(2) => func_sl_thold_2, + din(3) => func_nsl_thold_2, + din(4) => cfg_sl_thold_2, + din(5) => cfg_slp_sl_thold_2, + din(6) => sg_2, + din(7) => fce_2, + q(0) => func_slp_sl_thold_1, + q(1) => func_slp_nsl_thold_1, + q(2) => func_sl_thold_1, + q(3) => func_nsl_thold_1, + q(4) => cfg_sl_thold_1, + q(5) => cfg_slp_sl_thold_1, + q(6) => sg_1, + q(7) => fce_1); + +perv_1to0_reg: tri_plat + generic map (width => 8, expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_xu_ccflush_dc, + din(0) => func_slp_sl_thold_1, + din(1) => func_slp_nsl_thold_1, + din(2) => func_sl_thold_1, + din(3) => func_nsl_thold_1, + din(4) => cfg_sl_thold_1, + din(5) => cfg_slp_sl_thold_1, + din(6) => sg_1, + din(7) => fce_1, + q(0) => func_slp_sl_thold_0, + q(1) => func_slp_nsl_thold_0, + q(2) => func_sl_thold_0, + q(3) => func_nsl_thold_0, + q(4) => cfg_sl_thold_0, + q(5) => cfg_slp_sl_thold_0, + q(6) => sg_0, + q(7) => fce_0); + +perv_lcbor_cfg_sl: tri_lcbor + generic map (expand_type => expand_type) +port map (clkoff_b => clkoff_dc_b, + thold => cfg_sl_thold_0, + sg => sg_0, + act_dis => tidn, + forcee => cfg_sl_force, + thold_b => cfg_sl_thold_0_b); + +bcfg_sl_force <= cfg_sl_force; +bcfg_sl_thold_0_b <= cfg_sl_thold_0_b; +dcfg_sl_force <= cfg_sl_force; +dcfg_sl_thold_0_b <= cfg_sl_thold_0_b; + +perv_lcbor_cfg_slp: tri_lcbor + generic map (expand_type => expand_type) +port map (clkoff_b => clkoff_dc_b, + thold => cfg_slp_sl_thold_0, + sg => sg_0, + act_dis => tidn, + forcee => cfg_slp_sl_force, + thold_b => cfg_slp_sl_thold_0_b); + +bcfg_slp_sl_force <= cfg_slp_sl_force; +bcfg_slp_sl_thold_0_b <= cfg_slp_sl_thold_0_b; + +so_force <= sg_0; +ccfg_so_thold_0_b <= not cfg_sl_thold_0; +bcfg_so_thold_0_b <= not cfg_sl_thold_0; +dcfg_so_thold_0_b <= not cfg_sl_thold_0; +func_so_thold_0_b <= not func_sl_thold_0; + +perv_lcbor_func_sl: tri_lcbor + generic map (expand_type => expand_type) +port map (clkoff_b => clkoff_dc_b, + thold => func_sl_thold_0, + sg => sg_0, + act_dis => tidn, + forcee => func_sl_force, + thold_b => func_sl_thold_0_b); + +perv_lcbor_func_slp_sl: tri_lcbor + generic map (expand_type => expand_type) +port map (clkoff_b => clkoff_dc_b, + thold => func_slp_sl_thold_0, + sg => sg_0, + act_dis => tidn, + forcee => func_slp_sl_force, + thold_b => func_slp_sl_thold_0_b); + +perv_lcbor_func_slp_nsl: tri_lcbor + generic map (expand_type => expand_type) +port map (clkoff_b => clkoff_dc_b, + thold => func_slp_nsl_thold_0, + sg => fce_0, + act_dis => tidn, + forcee => func_slp_nsl_force, + thold_b => func_slp_nsl_thold_0_b); + +perv_lcbor_func_nsl: tri_lcbor + generic map (expand_type => expand_type) +port map (clkoff_b => clkoff_dc_b, + thold => func_nsl_thold_0, + sg => fce_0, + act_dis => tidn, + forcee => func_nsl_force, + thold_b => func_nsl_thold_0_b); + +siv( 0 to MSL-1) <= sov( 1 to MSL-1) & func_scan_rpwr_in(0); +func_scan_rpwr_out(0) <= sov( 0); + +siv(MSL to 2*MSL-1) <= sov(MSL+1 to 2*MSL-1) & func_scan_rpwr_in(1); +func_scan_rpwr_out(1) <= sov(MSL); + +siv(2*MSL to siv'right) <= sov(2*MSL+1 to siv'right) & func_scan_rpwr_in(2); +func_scan_rpwr_out(2) <= sov(2*MSL); + +siv_3(0 to siv_3'right) <= sov_3(1 to siv_3'right) & func_scan_rpwr_in(3); +func_scan_rpwr_out(3) <= sov_3(0); + +siv_ccfg(0 to scan_right_ccfg-1) <= sov_ccfg(1 to scan_right_ccfg-1) & ccfg_scan_rpwr_in(0); +ccfg_scan_rpwr_out <= sov_ccfg(0 to 0); + +siv_bcfg(0 to scan_right_bcfg-1) <= sov_bcfg(1 to scan_right_bcfg-1) & bcfg_scan_rpwr_in(0); +bcfg_scan_rpwr_out <= sov_bcfg(0 to 0); + +siv_dcfg(0 to scan_right_dcfg-1) <= sov_dcfg(1 to scan_right_dcfg-1) & dcfg_scan_rpwr_in(0); +dcfg_scan_rpwr_out <= sov_dcfg(0 to 0); + +ccfg_scan_rpwr_0i_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc, + thold_b => ccfg_so_thold_0_b, + scin(0) => ccfg_scan_in, + scout => ccfg_scan_rpwr_in(0 to 0), + dout => open); +ccfg_scan_rpwr_0o_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc, + thold_b => ccfg_so_thold_0_b, + scin => ccfg_scan_rpwr_out(0 to 0), + scout => ccfg_scan_out_gate(0 to 0), + dout => open); +bcfg_scan_rpwr_0i_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc, + thold_b => bcfg_so_thold_0_b, + scin(0) => bcfg_scan_in, + scout => bcfg_scan_rpwr_in(0 to 0), + dout => open); +bcfg_scan_rpwr_0o_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc, + thold_b => bcfg_so_thold_0_b, + scin => bcfg_scan_rpwr_out(0 to 0), + scout => bcfg_scan_out_gate(0 to 0), + dout => open); +dcfg_scan_rpwr_0i_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc, + thold_b => dcfg_so_thold_0_b, + scin(0) => dcfg_scan_in, + scout => dcfg_scan_rpwr_in(0 to 0), + dout => open); +dcfg_scan_rpwr_0o_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc, + thold_b => dcfg_so_thold_0_b, + scin => dcfg_scan_rpwr_out(0 to 0), + scout => dcfg_scan_out_gate(0 to 0), + dout => open); +func_scan_rpwr_50i_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc, + thold_b => func_so_thold_0_b, + scin => func_scan_in(50 to 50), + scout => func_scan_rpwr_in(0 to 0), + dout => open); +func_scan_rpwr_50o_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc, + thold_b => func_so_thold_0_b, + scin => func_scan_rpwr_out(0 to 0), + scout => func_scan_out_gate(50 to 50), + dout => open); +func_scan_rpwr_51i_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc, + thold_b => func_so_thold_0_b, + scin => func_scan_in(51 to 51), + scout => func_scan_rpwr_in(1 to 1), + dout => open); +func_scan_rpwr_51o_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc, + thold_b => func_so_thold_0_b, + scin => func_scan_rpwr_out(1 to 1), + scout => func_scan_out_gate(51 to 51), + dout => open); +func_scan_rpwr_52i_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc, + thold_b => func_so_thold_0_b, + scin => func_scan_in(52 to 52), + scout => func_scan_rpwr_in(2 to 2), + dout => open); +func_scan_rpwr_52o_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc, + thold_b => func_so_thold_0_b, + scin => func_scan_rpwr_out(2 to 2), + scout => func_scan_out_gate(52 to 52), + dout => open); +func_scan_rpwr_53i_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc, + thold_b => func_so_thold_0_b, + scin => func_scan_in(53 to 53), + scout => func_scan_rpwr2_in(3 to 3), + dout => open); +func_scan_rpwr_53i_2_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc, + thold_b => func_so_thold_0_b, + scin => func_scan_rpwr2_in(3 to 3), + scout => func_scan_rpwr_in(3 to 3), + dout => open); +func_scan_rpwr_53o_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc, + thold_b => func_so_thold_0_b, + scin => func_scan_rpwr_out(3 to 3), + scout => func_scan_out_gate(53 to 53), + dout => open); + +func_scan_out <= gate(func_scan_out_gate,an_ac_scan_dis_dc_b); +ccfg_scan_out <= ccfg_scan_out_gate(0) and an_ac_scan_dis_dc_b; +bcfg_scan_out <= bcfg_scan_out_gate(0) and an_ac_scan_dis_dc_b; +dcfg_scan_out <= dcfg_scan_out_gate(0) and an_ac_scan_dis_dc_b; + + +end architecture xuq_cpl; diff --git a/rel/src/vhdl/work/xuq_cpl_br.vhdl b/rel/src/vhdl/work/xuq_cpl_br.vhdl new file mode 100644 index 0000000..1d9e201 --- /dev/null +++ b/rel/src/vhdl/work/xuq_cpl_br.vhdl @@ -0,0 +1,375 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XU Branch Unit +-- +library ieee,ibm,support,work,tri; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use support.power_logic_pkg.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use tri.tri_latches_pkg.all; +use work.xuq_pkg.all; + +entity xuq_cpl_br is +generic( + expand_type : integer := 2; + threads : integer := 4; + eff_ifar : integer := 62; + uc_ifar : integer := 21; + regsize : integer := 64); +port( + -- Clocks + nclk : in clk_logic; + + -- Pervasive + d_mode_dc : in std_ulogic; + delay_lclkr_dc : in std_ulogic; + mpw1_dc_b : in std_ulogic; + mpw2_dc_b : in std_ulogic; + func_sl_thold_0_b : in std_ulogic; + func_sl_force : in std_ulogic; + sg_0 : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + rf1_act : in std_ulogic; + ex1_act : in std_ulogic; + + rf1_tid : in std_ulogic_vector(0 to threads-1); + ex1_tid : in std_ulogic_vector(0 to threads-1); + ex1_xu_val : in std_ulogic_vector(0 to threads-1); + + dec_cpl_rf1_ifar : in std_ulogic_vector(62-eff_ifar to 61); + ex1_xu_ifar : out std_ulogic_vector(62-eff_ifar to 61); + + dec_cpl_rf1_pred_taken_cnt : in std_ulogic; + dec_cpl_rf1_instr : in std_ulogic_vector(0 to 31); + + byp_cpl_ex1_cr_bit : in std_ulogic; + spr_lr : in std_ulogic_vector(0 to regsize*threads-1); + spr_ctr : in std_ulogic_vector(0 to regsize*threads-1); + + ex2_br_flush : out std_ulogic_vector(0 to threads-1); + ex2_br_flush_ifar : out std_ulogic_vector(62-eff_ifar to 61); + + ex1_branch : out std_ulogic; + ex1_br_mispred : out std_ulogic; + ex1_br_taken : out std_ulogic; + ex1_br_update : out std_ulogic; + ex1_is_bcctr : out std_ulogic; + ex1_is_bclr : out std_ulogic; + ex1_lr_update : out std_ulogic; + ex1_ctr_dec_update : out std_ulogic; + ex1_instr : out std_ulogic_vector(0 to 31); + + spr_msr_cm : in std_ulogic_vector(0 to threads-1); + + br_debug : out std_ulogic_vector(0 to 11); + + -- Power + vdd : inout power_logic; + gnd : inout power_logic +); + + +end xuq_cpl_br; +architecture xuq_cpl_br of xuq_cpl_br is + +signal ex1_instr_q : std_ulogic_vector(0 to 31); +signal ex1_is_b_q : std_ulogic; +signal ex1_is_bcctr_q : std_ulogic; +signal ex1_is_bclr_q : std_ulogic; +signal ex1_ctr_ok_q, ex1_ctr_ok_d : std_ulogic; +signal ex1_pred_taken_cnt_q : std_ulogic; +signal ex1_is_branch_cond_q, ex1_is_branch_cond_d : std_ulogic; +signal ex1_xu_ifar_q : std_ulogic_vector(62-eff_ifar to 61); +signal ex2_br_flush_q, ex2_br_flush_d : std_ulogic_vector(0 to threads-1); +signal ex2_br_flush_ifar_q, ex2_br_flush_ifar_d : std_ulogic_vector(62-eff_ifar to 61); +-- Scanchains +constant ex1_instr_offset : integer := 0; +constant ex1_is_b_offset : integer := ex1_instr_offset + ex1_instr_q'length; +constant ex1_is_bcctr_offset : integer := ex1_is_b_offset + 1; +constant ex1_is_bclr_offset : integer := ex1_is_bcctr_offset + 1; +constant ex1_ctr_ok_offset : integer := ex1_is_bclr_offset + 1; +constant ex1_pred_taken_cnt_offset : integer := ex1_ctr_ok_offset + 1; +constant ex1_is_branch_cond_offset : integer := ex1_pred_taken_cnt_offset + 1; +constant ex1_ifar_offset : integer := ex1_is_branch_cond_offset + 1; +constant ex2_br_flush_offset : integer := ex1_ifar_offset + ex1_xu_ifar_q'length; +constant ex2_br_flush_ifar_offset : integer := ex2_br_flush_offset + ex2_br_flush_q'length; +constant scan_right : integer := ex2_br_flush_ifar_offset + ex2_br_flush_ifar_q'length; +-- Scanchains +signal siv : std_ulogic_vector(0 to scan_right-1); +signal sov : std_ulogic_vector(0 to scan_right-1); +-- Signals +signal tiup : std_ulogic; +signal rf1_ctr : std_ulogic_vector(64-regsize to 63); +signal rf1_instr : std_ulogic_vector(0 to 31); +signal rf1_msr_cm : std_ulogic; +signal rf1_opcode_is_19 : boolean; +signal rf1_is_b,rf1_is_bc,rf1_is_bcctr,rf1_is_bclr : std_ulogic; +signal rf1_ctr_low_zero, rf1_ctr_hi_zero : std_ulogic; +signal rf1_ctr_zero, rf1_ctr_one, rf1_ctr_one_b : std_ulogic; +signal ex1_br_mispred_int,ex1_bcctr_flush : std_ulogic; +signal ex1_imm,ex1_cia : std_ulogic_vector(62-eff_ifar to 61); +signal ex1_br_t_trgt,ex1_br_nt_trgt,ex1_br_imm_trgt: std_ulogic_vector(62-eff_ifar to 61); +signal ex1_br_flush_ifar : std_ulogic_vector(62-eff_ifar to 61); +signal ex1_lr,ex1_ctr : std_ulogic_vector(64-regsize to 63); +signal ex1_taken : std_ulogic; + +begin + + + +tiup <= '1'; + +rf1_instr <= dec_cpl_rf1_instr; + +-- T(AA=1) T(AA=0) NT +--========================================================== +-- b IMM(6:29) CIA+IMM(6:29) N/A +-- bc IMM(16:29) CIA+IMM(16:29) CIA+4 +-- bclr LR CIA+4 +-- bcctr CTR CIA+4 + +-- Deocodes +rf1_opcode_is_19 <= rf1_instr( 0 to 5) = "010011"; -- 19 +rf1_is_b <= '1' when rf1_instr( 0 to 5) = "010010" else '0'; -- 18 +rf1_is_bc <= '1' when rf1_instr( 0 to 5) = "010000" else '0'; -- 16 +rf1_is_bcctr <= '1' when rf1_opcode_is_19 and rf1_instr(21 to 30) = "1000010000" else '0'; -- 19/528 +rf1_is_bclr <= '1' when rf1_opcode_is_19 and rf1_instr(21 to 30) = "0000010000" else '0'; -- 19/16 + +-- The CTR is always decremented before the test +rf1_msr_cm <= or_reduce(spr_msr_cm and rf1_tid); +rf1_ctr <= mux_t(spr_ctr,rf1_tid); +rf1_ctr_low_zero <= not or_reduce(rf1_ctr(32 to 62)); +xuq_cpl_ctr_cmp_0 : if regsize > 32 generate + rf1_ctr_hi_zero <= not or_reduce(rf1_ctr(64-regsize to 31)); +end generate; +xuq_cpl_ctr_cmp_1 : if regsize <= 32 generate + rf1_ctr_hi_zero <= '1'; +end generate; +rf1_ctr_zero <= rf1_ctr_low_zero and (rf1_ctr_hi_zero or not rf1_msr_cm); +rf1_ctr_one <= rf1_ctr_zero and rf1_ctr(63); +rf1_ctr_one_b <= not rf1_ctr_one; + +ex1_ctr_ok_d <= rf1_instr(8) or (rf1_ctr_one_b xor rf1_instr(9)); +ex1_taken <= (ex1_instr_q(6) or (byp_cpl_ex1_cr_bit xnor ex1_instr_q(7))) and ex1_ctr_ok_q; + +ex1_is_branch_cond_d <= rf1_is_bc or rf1_is_bclr or rf1_is_bcctr; + +ex1_cia <= ex1_xu_ifar_q and not (62-eff_ifar to 61=>ex1_instr_q(30)); + +ex1_imm(62-eff_ifar to 37) <= (others=>ex1_imm(38)); + +with ex1_is_b_q select + ex1_imm(38 to 47) <= ex1_instr_q( 6 to 15) when '1', + (38 to 47=>ex1_imm(48)) when others; + +ex1_imm(48 to 61) <= ex1_instr_q(16 to 29); + +ex1_br_nt_trgt <= std_ulogic_vector(unsigned(ex1_xu_ifar_q) + 1); + +ex1_br_imm_trgt <= std_ulogic_vector(unsigned(ex1_cia) + unsigned(ex1_imm)); + +ex1_lr <= mux_t(spr_lr,ex1_tid); +ex1_ctr <= mux_t(spr_ctr,ex1_tid); + +with s2'(ex1_is_bcctr_q & ex1_is_bclr_q) select + ex1_br_t_trgt <= ex1_ctr(64-regsize to 61) when "10", + ex1_lr(64-regsize to 61) when "01", + ex1_br_imm_trgt when others; + +with (ex1_is_b_q or ex1_taken) select + ex1_br_flush_ifar <= ex1_br_t_trgt when '1', + ex1_br_nt_trgt when others; + +ex2_br_flush_ifar_d <= ex1_br_flush_ifar; + +ex1_br_mispred_int <= ex1_is_branch_cond_q and (ex1_taken xor ex1_pred_taken_cnt_q); +ex1_bcctr_flush <= ex1_is_bcctr_q and ex1_taken; + +ex2_br_flush_d <= ex1_xu_val and (0 to threads-1=>(ex1_br_mispred_int or ex1_bcctr_flush)); + +ex2_br_flush_ifar <= ex2_br_flush_ifar_q; +ex2_br_flush <= ex2_br_flush_q; + +ex1_xu_ifar <= ex1_xu_ifar_q; +ex1_branch <= ex1_is_branch_cond_q or ex1_is_b_q; +ex1_br_mispred <= ex1_br_mispred_int; +ex1_br_taken <= (ex1_taken and ex1_is_branch_cond_q) or ex1_is_b_q; +ex1_br_update <= ex1_is_b_q or (ex1_is_branch_cond_q and ex1_taken); +ex1_is_bcctr <= ex1_is_bcctr_q; +ex1_is_bclr <= ex1_is_bclr_q; +ex1_ctr_dec_update <= ex1_is_branch_cond_q and not ex1_instr_q(8); -- !B02 +ex1_lr_update <= (ex1_is_branch_cond_q or ex1_is_b_q) and ex1_instr_q(31); +ex1_instr <= ex1_instr_q; + +mark_unused(ex1_lr(62 to 63)); +mark_unused(ex1_ctr(62 to 63)); + +br_debug <= rf1_msr_cm & rf1_ctr_low_zero & rf1_ctr_hi_zero & rf1_ctr_one & ex1_ctr_ok_q & ex1_taken & ex1_pred_taken_cnt_q & byp_cpl_ex1_cr_bit & ex2_br_flush_q; + +-- Latch Instances +ex1_instr_latch : tri_rlmreg_p + generic map (width => ex1_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_instr_offset to ex1_instr_offset + ex1_instr_q'length-1), + scout => sov(ex1_instr_offset to ex1_instr_offset + ex1_instr_q'length-1), + din => rf1_instr, + dout => ex1_instr_q); +ex1_is_b_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_b_offset), + scout => sov(ex1_is_b_offset), + din => rf1_is_b, + dout => ex1_is_b_q); +ex1_is_bcctr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_bcctr_offset), + scout => sov(ex1_is_bcctr_offset), + din => rf1_is_bcctr, + dout => ex1_is_bcctr_q); +ex1_is_bclr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_bclr_offset), + scout => sov(ex1_is_bclr_offset), + din => rf1_is_bclr, + dout => ex1_is_bclr_q); +ex1_ctr_ok_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_ctr_ok_offset), + scout => sov(ex1_ctr_ok_offset), + din => ex1_ctr_ok_d, + dout => ex1_ctr_ok_q); +ex1_pred_taken_cnt_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_pred_taken_cnt_offset), + scout => sov(ex1_pred_taken_cnt_offset), + din => dec_cpl_rf1_pred_taken_cnt, + dout => ex1_pred_taken_cnt_q); +ex1_is_branch_cond_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_branch_cond_offset), + scout => sov(ex1_is_branch_cond_offset), + din => ex1_is_branch_cond_d, + dout => ex1_is_branch_cond_q); +ex1_ifar_latch : tri_rlmreg_p + generic map (width => ex1_xu_ifar_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_ifar_offset to ex1_ifar_offset + ex1_xu_ifar_q'length-1), + scout => sov(ex1_ifar_offset to ex1_ifar_offset + ex1_xu_ifar_q'length-1), + din => dec_cpl_rf1_ifar, + dout => ex1_xu_ifar_q); +ex2_br_flush_latch : tri_rlmreg_p + generic map (width => ex2_br_flush_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_br_flush_offset to ex2_br_flush_offset + ex2_br_flush_q'length-1), + scout => sov(ex2_br_flush_offset to ex2_br_flush_offset + ex2_br_flush_q'length-1), + din => ex2_br_flush_d, + dout => ex2_br_flush_q); +ex2_br_flush_ifar_latch : tri_rlmreg_p + generic map (width => ex2_br_flush_ifar_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_br_flush_ifar_offset to ex2_br_flush_ifar_offset + ex2_br_flush_ifar_q'length-1), + scout => sov(ex2_br_flush_ifar_offset to ex2_br_flush_ifar_offset + ex2_br_flush_ifar_q'length-1), + din => ex2_br_flush_ifar_d, + dout => ex2_br_flush_ifar_q); + +siv(0 to scan_right-1) <= sov(1 to scan_right-1) & scan_in; +scan_out <= sov(0); + + +end architecture xuq_cpl_br; diff --git a/rel/src/vhdl/work/xuq_cpl_fctr.vhdl b/rel/src/vhdl/work/xuq_cpl_fctr.vhdl new file mode 100644 index 0000000..070de33 --- /dev/null +++ b/rel/src/vhdl/work/xuq_cpl_fctr.vhdl @@ -0,0 +1,139 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XU CPL - Configurable Flush Delay Counter +-- +library ieee,ibm,support,tri; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ibm.std_ulogic_function_support.all; +use support.power_logic_pkg.all; +use tri.tri_latches_pkg.all; + +entity xuq_cpl_fctr is +generic( + expand_type : integer := 2; + threads : integer := 4; + clockgate : integer range 0 to 1 := 1; + passthru : integer range 0 to 1 := 1; + delay_width : integer := 4); +port( + nclk : in clk_logic; + + forcee : in std_ulogic; + thold_b : in std_ulogic; + sg : in std_ulogic; + d_mode : in std_ulogic; + delay_lclkr : in std_ulogic; + mpw1_b : in std_ulogic; + mpw2_b : in std_ulogic; + + scin : in std_ulogic; + scout : out std_ulogic; + + din : in std_ulogic_vector(0 to threads-1); + dout : out std_ulogic_vector(0 to threads-1); + delay : in std_ulogic_vector(0 to delay_width-1); + + vd : inout power_logic; + gd : inout power_logic + +); + +-- synopsys translate_off +-- synopsys translate_on + +end xuq_cpl_fctr; +architecture xuq_cpl_fctr of xuq_cpl_fctr is + +type DELAY_ARR is array (0 to threads-1) of std_ulogic_vector(0 to delay_width-1); +subtype s2 is std_ulogic_vector(0 to 1); +-- Latches +signal delay_q, delay_d : DELAY_ARR; +-- Scanchains +constant delay_offset : integer := 0; +constant scan_right : integer := delay_offset + delay_q(0)'length*threads; +signal siv : std_ulogic_vector(0 to scan_right-1); +signal sov : std_ulogic_vector(0 to scan_right-1); +-- Signals +signal set,zero_b,act : std_ulogic_vector(0 to threads-1); + +begin + +threads_gen : for t in 0 to threads-1 generate +signal delay_m1 : std_ulogic_vector(0 to delay_width-1); +begin + + set(t) <= din(t); + zero_b(t) <= or_reduce(delay_q(t)); + delay_m1 <= std_ulogic_vector(unsigned(delay_q(t)) - 1); + + clockgate_0 : if clockgate = 0 generate + act(t) <= '1'; + + with s2'(set(t) & zero_b(t)) select + delay_d(t) <= delay when "11", + delay when "10", + delay_m1 when "01", + delay_q(t) when others; + end generate; + clockgate_1 : if clockgate = 1 generate + act(t) <= set(t) or zero_b(t); + + with set(t) select + delay_d(t) <= delay when '1', + delay_m1 when others; + end generate; + + passthru_gen_1 : if passthru = 1 generate + dout(t) <= zero_b(t) or din(t); + end generate; + passthru_gen_0 : if passthru = 0 generate + dout(t) <= zero_b(t); + end generate; + + delay_latch : tri_rlmreg_p + generic map (width => delay_q(0)'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vd, gd => gd, + act => act(t), + forcee => forcee, + d_mode => d_mode, delay_lclkr => delay_lclkr, + mpw1_b => mpw1_b, mpw2_b => mpw2_b, + thold_b => thold_b, + sg => sg, + scin => siv(delay_offset+delay_q(0)'length*t to delay_offset+delay_q(0)'length*(t+1)-1), + scout => sov(delay_offset+delay_q(0)'length*t to delay_offset+delay_q(0)'length*(t+1)-1), + din => delay_d(t), + dout => delay_q(t)); + +end generate; + +siv(0 to scan_right-1) <= sov(1 to scan_right-1) & scin; +scout <= sov(0); + +end architecture xuq_cpl_fctr; diff --git a/rel/src/vhdl/work/xuq_cpl_fxub.vhdl b/rel/src/vhdl/work/xuq_cpl_fxub.vhdl new file mode 100644 index 0000000..52bd20b --- /dev/null +++ b/rel/src/vhdl/work/xuq_cpl_fxub.vhdl @@ -0,0 +1,1684 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XU Exception Handler +-- +library ieee,ibm,support,work,tri,clib; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use support.power_logic_pkg.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use tri.tri_latches_pkg.all; +use work.xuq_pkg.all; + +entity xuq_cpl_fxub is +generic( + expand_type : integer := 2; + threads : integer := 4; + eff_ifar : integer := 62; + uc_ifar : integer := 21; + regsize : integer := 64; + hvmode : integer := 1; + regmode : integer := 6; + dc_size : natural := 14; + cl_size : natural := 6; -- 2^6 = 64 Bytes CacheLines + real_data_add : integer := 42; + fxu_synth : integer := 0; + a2mode : integer := 1); +port( + + --------------------------------------------------------------------- + -- Clocks & Power + --------------------------------------------------------------------- + nclk : in clk_logic; + vdd : inout power_logic; + gnd : inout power_logic; + vcs : inout power_logic; + + --------------------------------------------------------------------- + -- Pervasive + --------------------------------------------------------------------- + func_scan_in : in std_ulogic_vector(50 to 58); + func_scan_out : out std_ulogic_vector(50 to 58); + an_ac_scan_dis_dc_b : in std_ulogic; + pc_xu_ccflush_dc : in std_ulogic; + clkoff_dc_b : out std_ulogic; + d_mode_dc : out std_ulogic; + delay_lclkr_dc : out std_ulogic_vector(0 to 4); + mpw1_dc_b : out std_ulogic_vector(0 to 4); + mpw2_dc_b : out std_ulogic; + g6t_clkoff_dc_b : out std_ulogic; + g6t_d_mode_dc : out std_ulogic; + g6t_delay_lclkr_dc : out std_ulogic_vector(0 to 4); + g6t_mpw1_dc_b : out std_ulogic_vector(0 to 4); + g6t_mpw2_dc_b : out std_ulogic; + g8t_clkoff_dc_b : out std_ulogic; + g8t_d_mode_dc : out std_ulogic; + g8t_delay_lclkr_dc : out std_ulogic_vector(0 to 4); + g8t_mpw1_dc_b : out std_ulogic_vector(0 to 4); + g8t_mpw2_dc_b : out std_ulogic; + cam_clkoff_dc_b : out std_ulogic; + cam_d_mode_dc : out std_ulogic; + cam_delay_lclkr_dc : out std_ulogic_vector(0 to 4); + cam_act_dis_dc : out std_ulogic; + cam_mpw1_dc_b : out std_ulogic_vector(0 to 4); + cam_mpw2_dc_b : out std_ulogic; + pc_xu_sg_3 : in std_ulogic_vector(0 to 4); + pc_xu_func_sl_thold_3 : in std_ulogic_vector(0 to 4); + pc_xu_func_slp_sl_thold_3 : in std_ulogic_vector(0 to 4); + pc_xu_func_nsl_thold_3 : in std_ulogic; + pc_xu_func_slp_nsl_thold_3 : in std_ulogic; + pc_xu_gptr_sl_thold_3 : in std_ulogic; + pc_xu_abst_sl_thold_3 : in std_ulogic; + pc_xu_abst_slp_sl_thold_3 : in std_ulogic; + pc_xu_regf_sl_thold_3 : in std_ulogic; + pc_xu_regf_slp_sl_thold_3 : in std_ulogic; + pc_xu_time_sl_thold_3 : in std_ulogic; + pc_xu_cfg_sl_thold_3 : in std_ulogic; + pc_xu_cfg_slp_sl_thold_3 : in std_ulogic; + pc_xu_ary_nsl_thold_3 : in std_ulogic; + pc_xu_ary_slp_nsl_thold_3 : in std_ulogic; + pc_xu_repr_sl_thold_3 : in std_ulogic; + pc_xu_bolt_sl_thold_3 : in std_ulogic; + pc_xu_bo_enable_3 : in std_ulogic; + pc_xu_fce_3 : in std_ulogic_vector(0 to 1); + an_ac_scan_diag_dc : in std_ulogic; + sg_2 : out std_ulogic_vector(0 to 3); + fce_2 : out std_ulogic_vector(0 to 1); + func_sl_thold_2 : out std_ulogic_vector(0 to 3); + func_slp_sl_thold_2 : out std_ulogic_vector(0 to 1); + func_nsl_thold_2 : out std_ulogic; + func_slp_nsl_thold_2 : out std_ulogic; + abst_sl_thold_2 : out std_ulogic; + abst_slp_sl_thold_2 : out std_ulogic; + time_sl_thold_2 : out std_ulogic; + gptr_sl_thold_2 : out std_ulogic; + ary_nsl_thold_2 : out std_ulogic; + ary_slp_nsl_thold_2 : out std_ulogic; + repr_sl_thold_2 : out std_ulogic; + cfg_sl_thold_2 : out std_ulogic; + cfg_slp_sl_thold_2 : out std_ulogic; + regf_slp_sl_thold_2 : out std_ulogic; + bolt_sl_thold_2 : out std_ulogic; + bo_enable_2 : out std_ulogic; + gptr_scan_in : in std_ulogic; + gptr_scan_out : out std_ulogic; + + --------------------------------------------------------------------- + -- Interface with FXU A + --------------------------------------------------------------------- + fxa_fxb_rf0_val : in std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_issued : in std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_ucode_val : in std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_act : in std_ulogic; + fxa_fxb_ex1_hold_ctr_flush : in std_ulogic; + fxa_fxb_rf0_instr : in std_ulogic_vector(0 to 31); + fxa_fxb_rf0_tid : in std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_ta_vld : in std_ulogic; + fxa_fxb_rf0_ta : in std_ulogic_vector(0 to 7); + fxa_fxb_rf0_error : in std_ulogic_vector(0 to 2); + fxa_fxb_rf0_match : in std_ulogic; + fxa_fxb_rf0_is_ucode : in std_ulogic; + fxa_fxb_rf0_gshare : in std_ulogic_vector(0 to 3); + fxa_fxb_rf0_ifar : in std_ulogic_vector(62-eff_ifar to 61); + fxa_fxb_rf0_s1_vld : in std_ulogic; + fxa_fxb_rf0_s1 : in std_ulogic_vector(0 to 7); + fxa_fxb_rf0_s2_vld : in std_ulogic; + fxa_fxb_rf0_s2 : in std_ulogic_vector(0 to 7); + fxa_fxb_rf0_s3_vld : in std_ulogic; + fxa_fxb_rf0_s3 : in std_ulogic_vector(0 to 7); + fxa_fxb_rf0_axu_instr_type : in std_ulogic_vector(0 to 2); + fxa_fxb_rf0_axu_ld_or_st : in std_ulogic; + fxa_fxb_rf0_axu_store : in std_ulogic; + fxa_fxb_rf0_axu_ldst_forcealign : in std_ulogic; + fxa_fxb_rf0_axu_ldst_forceexcept : in std_ulogic; + fxa_fxb_rf0_axu_ldst_indexed : in std_ulogic; + fxa_fxb_rf0_axu_ldst_tag : in std_ulogic_vector(0 to 8); + fxa_fxb_rf0_axu_mftgpr : in std_ulogic; + fxa_fxb_rf0_axu_mffgpr : in std_ulogic; + fxa_fxb_rf0_axu_movedp : in std_ulogic; + fxa_fxb_rf0_axu_ldst_size : in std_ulogic_vector(0 to 5); + fxa_fxb_rf0_axu_ldst_update : in std_ulogic; + fxa_fxb_rf0_pred_update : in std_ulogic; + fxa_fxb_rf0_pred_taken_cnt : in std_ulogic_vector(0 to 1); + fxa_fxb_rf0_mc_dep_chk_val : in std_ulogic_vector(0 to threads-1); + fxa_fxb_rf1_mul_val : in std_ulogic; + fxa_fxb_rf1_div_val : in std_ulogic; + fxa_fxb_rf1_div_ctr : in std_ulogic_vector(0 to 7); + fxa_fxb_rf0_xu_epid_instr : in std_ulogic; + fxa_fxb_rf0_axu_is_extload : in std_ulogic; + fxa_fxb_rf0_axu_is_extstore : in std_ulogic; + fxa_fxb_rf0_is_mfocrf : in std_ulogic; + fxa_fxb_rf0_3src_instr : in std_ulogic; + fxa_fxb_rf0_gpr0_zero : in std_ulogic; + fxa_fxb_rf0_use_imm : in std_ulogic; + fxa_fxb_rf1_muldiv_coll : in std_ulogic; + fxa_cpl_ex2_div_coll : in std_ulogic_vector(0 to threads-1); + fxb_fxa_ex7_we0 : out std_ulogic; + fxb_fxa_ex7_wa0 : out std_ulogic_vector(0 to 7); + fxb_fxa_ex7_wd0 : out std_ulogic_vector(64-regsize to 63); + fxa_fxb_rf1_do0 : in std_ulogic_vector(64-regsize to 63); + fxa_fxb_rf1_do1 : in std_ulogic_vector(64-regsize to 63); + fxa_fxb_rf1_do2 : in std_ulogic_vector(64-regsize to 63); + + --------------------------------------------------------------------- + -- Interface with LSU + --------------------------------------------------------------------- + xu_lsu_rf0_act : out std_ulogic; + xu_lsu_rf1_cache_acc : out std_ulogic; + xu_lsu_rf1_thrd_id : out std_ulogic_vector(0 to threads-1); + xu_lsu_rf1_optype1 : out std_ulogic; + xu_lsu_rf1_optype2 : out std_ulogic; + xu_lsu_rf1_optype4 : out std_ulogic; + xu_lsu_rf1_optype8 : out std_ulogic; + xu_lsu_rf1_optype16 : out std_ulogic; + xu_lsu_rf1_optype32 : out std_ulogic; + xu_lsu_rf1_target_gpr : out std_ulogic_vector(0 to 8); + xu_lsu_rf1_load_instr : out std_ulogic; + xu_lsu_rf1_store_instr : out std_ulogic; + xu_lsu_rf1_dcbf_instr : out std_ulogic; + xu_lsu_rf1_sync_instr : out std_ulogic; + xu_lsu_rf1_mbar_instr : out std_ulogic; + xu_lsu_rf1_l_fld : out std_ulogic_vector(0 to 1); + xu_lsu_rf1_dcbi_instr : out std_ulogic; + xu_lsu_rf1_dcbz_instr : out std_ulogic; + xu_lsu_rf1_dcbt_instr : out std_ulogic; + xu_lsu_rf1_dcbtst_instr : out std_ulogic; + xu_lsu_rf1_th_fld : out std_ulogic_vector(0 to 4); + xu_lsu_rf1_dcbtls_instr : out std_ulogic; + xu_lsu_rf1_dcbtstls_instr : out std_ulogic; + xu_lsu_rf1_dcblc_instr : out std_ulogic; + xu_lsu_rf1_dcbst_instr : out std_ulogic; + xu_lsu_rf1_icbi_instr : out std_ulogic; + xu_lsu_rf1_icblc_instr : out std_ulogic; + xu_lsu_rf1_icbt_instr : out std_ulogic; + xu_lsu_rf1_icbtls_instr : out std_ulogic; + xu_lsu_rf1_tlbsync_instr : out std_ulogic; + xu_lsu_rf1_lock_instr : out std_ulogic; + xu_lsu_rf1_mutex_hint : out std_ulogic; + xu_lsu_rf1_axu_op_val : out std_ulogic; + xu_lsu_rf1_axu_ldst_falign : out std_ulogic; + xu_lsu_rf1_axu_ldst_fexcpt : out std_ulogic; + xu_lsu_ex1_store_data : out std_ulogic_vector(64-(2**regmode) to 63); + xu_lsu_rf1_algebraic : out std_ulogic; + xu_lsu_rf1_byte_rev : out std_ulogic; + xu_lsu_rf1_src_gpr : out std_ulogic; + xu_lsu_rf1_src_axu : out std_ulogic; + xu_lsu_rf1_src_dp : out std_ulogic; + xu_lsu_rf1_targ_gpr : out std_ulogic; + xu_lsu_rf1_targ_axu : out std_ulogic; + xu_lsu_rf1_targ_dp : out std_ulogic; + xu_lsu_ex4_val : out std_ulogic_vector(0 to threads-1); -- There is a valid Instruction in EX4 + xu_lsu_ex1_rotsel_ovrd : out std_ulogic_vector(0 to 4); + xu_lsu_rf1_derat_act : out std_ulogic; + xu_lsu_rf1_derat_is_load : out std_ulogic; + xu_lsu_rf1_derat_is_store : out std_ulogic; + xu_lsu_rf1_src0_vld : out std_ulogic; + xu_lsu_rf1_src0_reg : out std_ulogic_vector(0 to 7); + xu_lsu_rf1_src1_vld : out std_ulogic; + xu_lsu_rf1_src1_reg : out std_ulogic_vector(0 to 7); + xu_lsu_rf1_targ_vld : out std_ulogic; + xu_lsu_rf1_targ_reg : out std_ulogic_vector(0 to 7); + xu_bx_ex1_mtdp_val : out std_ulogic; + xu_bx_ex1_mfdp_val : out std_ulogic; + xu_bx_ex1_ipc_thrd : out std_ulogic_vector(0 to 1); + xu_bx_ex2_ipc_ba : out std_ulogic_vector(0 to 4); + xu_bx_ex2_ipc_sz : out std_ulogic_vector(0 to 1); + xu_lsu_rf1_is_touch : out std_ulogic; + xu_lsu_rf1_is_msgsnd : out std_ulogic; + xu_lsu_rf1_dci_instr : out std_ulogic; + xu_lsu_rf1_ici_instr : out std_ulogic; + xu_lsu_rf1_icswx_instr : out std_ulogic; + xu_lsu_rf1_icswx_dot_instr : out std_ulogic; + xu_lsu_rf1_icswx_epid : out std_ulogic; + xu_lsu_rf1_ldawx_instr : out std_ulogic; + xu_lsu_rf1_wclr_instr : out std_ulogic; + xu_lsu_rf1_wchk_instr : out std_ulogic; + xu_lsu_rf1_derat_ra_eq_ea : out std_ulogic; + xu_lsu_rf1_cmd_act : out std_ulogic; + xu_lsu_rf1_data_act : out std_ulogic; + xu_lsu_rf1_mtspr_trace : out std_ulogic; + lsu_xu_ex5_wren : in std_ulogic; -- FXU Load Hit Write is Valid in EX5 + lsu_xu_rel_wren : in std_ulogic; -- FXU Reload is Valid + lsu_xu_rel_ta_gpr : in std_ulogic_vector(0 to 7); -- FXU Reload Target Register + lsu_xu_need_hole : in std_ulogic; + lsu_xu_rot_ex6_data_b : in std_ulogic_vector(64-(2**regmode) to 63); + lsu_xu_rot_rel_data : in std_ulogic_vector(64-(2**regmode) to 63); + xu_lsu_ex4_dvc1_en : out std_ulogic; + xu_lsu_ex4_dvc2_en : out std_ulogic; + lsu_xu_ex2_dvc1_st_cmp : in std_ulogic_vector(8-(2**regmode)/8 to 7); + lsu_xu_ex2_dvc2_st_cmp : in std_ulogic_vector(8-(2**regmode)/8 to 7); + lsu_xu_ex8_dvc1_ld_cmp : in std_ulogic_vector(8-(2**regmode)/8 to 7); + lsu_xu_ex8_dvc2_ld_cmp : in std_ulogic_vector(8-(2**regmode)/8 to 7); + lsu_xu_rel_dvc1_en : in std_ulogic; + lsu_xu_rel_dvc2_en : in std_ulogic; + lsu_xu_rel_dvc_thrd_id : in std_ulogic_vector(0 to 3); + lsu_xu_rel_dvc1_cmp : in std_ulogic_vector(8-(2**regmode)/8 to 7); + lsu_xu_rel_dvc2_cmp : in std_ulogic_vector(8-(2**regmode)/8 to 7); + xu_lsu_ex1_add_src0 : out std_ulogic_vector(64-regsize to 63); + xu_lsu_ex1_add_src1 : out std_ulogic_vector(64-regsize to 63); + + --------------------------------------------------------------------- + -- Effective Address + --------------------------------------------------------------------- + xu_ex1_eff_addr_int : out std_ulogic_vector(64-(dc_size-3) to 63); + + -- Barrier + xu_lsu_ex5_set_barr : out std_ulogic_vector(0 to threads-1); + cpl_fxa_ex5_set_barr : out std_ulogic_vector(0 to threads-1); + cpl_iu_set_barr_tid : out std_ulogic_vector(0 to threads-1); + + --------------------------------------------------------------------- + -- TLB ops interface + --------------------------------------------------------------------- + xu_iu_rf1_val : out std_ulogic_vector(0 to threads-1); + xu_rf1_val : out std_ulogic_vector(0 to threads-1); + xu_rf1_is_tlbre : out std_ulogic; + xu_rf1_is_tlbwe : out std_ulogic; + xu_rf1_is_tlbsx : out std_ulogic; + xu_rf1_is_tlbsrx : out std_ulogic; + xu_rf1_is_tlbilx : out std_ulogic; + xu_rf1_is_tlbivax : out std_ulogic; + xu_rf1_is_eratre : out std_ulogic; + xu_rf1_is_eratwe : out std_ulogic; + xu_rf1_is_eratsx : out std_ulogic; + xu_rf1_is_eratsrx : out std_ulogic; + xu_rf1_is_eratilx : out std_ulogic; + xu_rf1_is_erativax : out std_ulogic; + xu_ex1_is_isync : out std_ulogic; + xu_ex1_is_csync : out std_ulogic; + xu_rf1_ws : out std_ulogic_vector(0 to 1); + xu_rf1_t : out std_ulogic_vector(0 to 2); + xu_ex1_rs_is : out std_ulogic_vector(0 to 8); + xu_ex1_ra_entry : out std_ulogic_vector(7 to 11); + xu_ex1_rb : out std_ulogic_vector(64-(2**regmode) to 51); + xu_ex2_eff_addr : out std_ulogic_vector(64-(2**regmode) to 63); + xu_ex4_rs_data : out std_ulogic_vector(64-(2**regmode) to 63); + lsu_xu_ex4_tlb_data : in std_ulogic_vector(64-(2**regmode) to 63); + iu_xu_ex4_tlb_data : in std_ulogic_vector(64-(2**regmode) to 63); + + --------------------------------------------------------------------- + -- D-ERAT Req Interface + --------------------------------------------------------------------- + xu_mm_derat_epn : out std_ulogic_vector(62-eff_ifar to 51); + + --------------------------------------------------------------------- + -- Back Invalidate + --------------------------------------------------------------------- + lsu_xu_is2_back_inv : in std_ulogic; + lsu_xu_is2_back_inv_addr : in std_ulogic_vector(64-real_data_add to 63-cl_size); + + --------------------------------------------------------------------- + -- TLBRE + --------------------------------------------------------------------- + mm_xu_mmucr0_0_tlbsel : in std_ulogic_vector(4 to 5); + mm_xu_mmucr0_1_tlbsel : in std_ulogic_vector(4 to 5); + mm_xu_mmucr0_2_tlbsel : in std_ulogic_vector(4 to 5); + mm_xu_mmucr0_3_tlbsel : in std_ulogic_vector(4 to 5); + + --------------------------------------------------------------------- + -- TLBSX./TLBSRX. + --------------------------------------------------------------------- + xu_mm_rf1_is_tlbsxr : out std_ulogic; + mm_xu_cr0_eq_valid : in std_ulogic_vector(0 to threads-1); + mm_xu_cr0_eq : in std_ulogic_vector(0 to threads-1); + + --------------------------------------------------------------------- + -- FU CR Write + --------------------------------------------------------------------- + fu_xu_ex4_cr_val : in std_ulogic_vector(0 to threads-1); + fu_xu_ex4_cr_noflush : in std_ulogic_vector(0 to threads-1); + fu_xu_ex4_cr0 : in std_ulogic_vector(0 to 3); + fu_xu_ex4_cr0_bf : in std_ulogic_vector(0 to 2); + fu_xu_ex4_cr1 : in std_ulogic_vector(0 to 3); + fu_xu_ex4_cr1_bf : in std_ulogic_vector(0 to 2); + fu_xu_ex4_cr2 : in std_ulogic_vector(0 to 3); + fu_xu_ex4_cr2_bf : in std_ulogic_vector(0 to 2); + fu_xu_ex4_cr3 : in std_ulogic_vector(0 to 3); + fu_xu_ex4_cr3_bf : in std_ulogic_vector(0 to 2); + + --------------------------------------------------------------------- + -- RAM + --------------------------------------------------------------------- + xu_pc_ram_data : out std_ulogic_vector(64-(2**regmode) to 63); + + --------------------------------------------------------------------- + -- Interface with IU + --------------------------------------------------------------------- + xu_iu_ex5_val : out std_ulogic; + xu_iu_ex5_tid : out std_ulogic_vector(0 to threads-1); + xu_iu_ex5_br_update : out std_ulogic; + xu_iu_ex5_br_hist : out std_ulogic_vector(0 to 1); + xu_iu_ex5_bclr : out std_ulogic; + xu_iu_ex5_lk : out std_ulogic; + xu_iu_ex5_bh : out std_ulogic_vector(0 to 1); + xu_iu_ex6_pri : out std_ulogic_vector(0 to 2); + xu_iu_ex6_pri_val : out std_ulogic_vector(0 to 3); + xu_iu_spr_xer : out std_ulogic_vector(0 to 7*threads-1); + xu_iu_slowspr_done : out std_ulogic_vector(0 to threads-1); + xu_iu_need_hole : out std_ulogic; + fxb_fxa_ex6_clear_barrier : out std_ulogic_vector(0 to threads-1); + xu_iu_ex5_gshare : out std_ulogic_vector(0 to 3); + xu_iu_ex5_getNIA : out std_ulogic; + + --------------------------------------------------------------------- + -- L2 STCX complete + --------------------------------------------------------------------- + an_ac_stcx_complete : in std_ulogic_vector(0 to threads-1); + an_ac_stcx_pass : in std_ulogic_vector(0 to threads-1); + + --------------------------------------------------------------------- + -- icswx. interface + --------------------------------------------------------------------- + an_ac_back_inv : in std_ulogic; + an_ac_back_inv_addr : in std_ulogic_vector(58 to 63); + an_ac_back_inv_target_bit3 : in std_ulogic; + + --------------------------------------------------------------------- + -- Slow SPR Bus + --------------------------------------------------------------------- + slowspr_val_in : in std_ulogic; + slowspr_rw_in : in std_ulogic; + slowspr_etid_in : in std_ulogic_vector(0 to 1); + slowspr_addr_in : in std_ulogic_vector(0 to 9); + slowspr_data_in : in std_ulogic_vector(64-(2**regmode) to 63); + slowspr_done_in : in std_ulogic; + + --------------------------------------------------------------------- + -- DCR Bus + --------------------------------------------------------------------- + an_ac_dcr_act : in std_ulogic; + an_ac_dcr_val : in std_ulogic; + an_ac_dcr_read : in std_ulogic; + an_ac_dcr_etid : in std_ulogic_vector(0 to 1); + an_ac_dcr_data : in std_ulogic_vector(64-(2**regmode) to 63); + an_ac_dcr_done : in std_ulogic; + + --------------------------------------------------------------------- + -- MT/MFDCR CR + --------------------------------------------------------------------- + lsu_xu_ex4_mtdp_cr_status : in std_ulogic; + lsu_xu_ex4_mfdp_cr_status : in std_ulogic; + dec_cpl_ex3_mc_dep_chk_val : in std_ulogic_vector(0 to threads-1); + + --------------------------------------------------------------------- + -- ldawx/wchkall + --------------------------------------------------------------------- + lsu_xu_ex4_cr_upd : in std_ulogic; + lsu_xu_ex5_cr_rslt : in std_ulogic; + + --------------------------------------------------------------------- + -- Interface with SPR + --------------------------------------------------------------------- + dec_spr_ex4_val : out std_ulogic_vector(0 to threads-1); + dec_spr_ex1_epid_instr : out std_ulogic; + mux_spr_ex2_rt : out std_ulogic_vector(64-(2**regmode) to 63); + fxu_spr_ex1_rs0 : out std_ulogic_vector(52 to 63); + fxu_spr_ex1_rs1 : out std_ulogic_vector(54 to 63); + spr_msr_cm : in std_ulogic_vector(0 to threads-1); + spr_dec_spr_xucr0_ssdly : in std_ulogic_vector(0 to 4); + spr_ccr2_en_attn : in std_ulogic; + spr_ccr2_en_ditc : in std_ulogic; + spr_ccr2_en_pc : in std_ulogic; + spr_ccr2_en_icswx : in std_ulogic; + spr_ccr2_en_dcr : in std_ulogic; + spr_dec_rf1_epcr_dgtmi : in std_ulogic_vector(0 to threads-1); + spr_dec_rf1_msr_ucle : in std_ulogic_vector(0 to threads-1); + spr_dec_rf1_msrp_uclep : in std_ulogic_vector(0 to threads-1); + spr_byp_ex4_is_mfxer : in std_ulogic_vector(0 to threads-1); + spr_byp_ex3_spr_rt : in std_ulogic_vector(64-(2**regmode) to 63); + spr_byp_ex4_is_mtxer : in std_ulogic_vector(0 to threads-1); + spr_ccr2_notlb : in std_ulogic; + dec_spr_rf1_val : out std_ulogic_vector(0 to threads-1); + fxu_spr_ex1_rs2 : out std_ulogic_vector(42 to 55); + + --------------------------------------------------------------------- + -- Perf Events + --------------------------------------------------------------------- + fxa_perf_muldiv_in_use : in std_ulogic; + spr_perf_tx_events : in std_ulogic_vector(0 to 8*threads-1); + xu_pc_event_data : out std_ulogic_vector(0 to 7); + + --------------------------------------------------------------------- + -- PC Control Interface + --------------------------------------------------------------------- + pc_xu_event_bus_enable : in std_ulogic; + pc_xu_event_count_mode : in std_ulogic_vector(0 to 2); + pc_xu_event_mux_ctrls : in std_ulogic_vector(0 to 47); + + --------------------------------------------------------------------- + -- Debug Ramp & Controls + --------------------------------------------------------------------- + pc_xu_trace_bus_enable : in std_ulogic; + pc_xu_instr_trace_mode : in std_ulogic; + pc_xu_instr_trace_tid : in std_ulogic_vector(0 to 1); + xu_lsu_ex2_instr_trace_val : out std_ulogic; + fxu_debug_mux_ctrls : in std_ulogic_vector(0 to 15); + fxu_trigger_data_in : in std_ulogic_vector(0 to 11); + fxu_debug_data_in : in std_ulogic_vector(0 to 87); + fxu_trigger_data_out : out std_ulogic_vector(0 to 11); + fxu_debug_data_out : out std_ulogic_vector(0 to 87); + lsu_xu_data_debug0 : in std_ulogic_vector(0 to 87); + lsu_xu_data_debug1 : in std_ulogic_vector(0 to 87); + lsu_xu_data_debug2 : in std_ulogic_vector(0 to 87); + + --------------------------------------------------------------------- + -- SPR Bits + --------------------------------------------------------------------- + spr_msr_gs : in std_ulogic_vector(0 to threads-1); + spr_msr_ds : in std_ulogic_vector(0 to threads-1); + spr_msr_pr : in std_ulogic_vector(0 to threads-1); + spr_dbcr0_dac1 : in std_ulogic_vector(0 to 2*threads-1); + spr_dbcr0_dac2 : in std_ulogic_vector(0 to 2*threads-1); + spr_dbcr0_dac3 : in std_ulogic_vector(0 to 2*threads-1); + spr_dbcr0_dac4 : in std_ulogic_vector(0 to 2*threads-1); + spr_xucr0_clkg_ctl : in std_ulogic_vector(2 to 2); + + -- CHIP IO + ac_tc_debug_trigger : out std_ulogic_vector(0 to threads-1); + + -- Pervasive + ccfg_scan_in : in std_ulogic; + ccfg_scan_out : out std_ulogic; + bcfg_scan_in : in std_ulogic; + bcfg_scan_out : out std_ulogic; + dcfg_scan_in : in std_ulogic; + dcfg_scan_out : out std_ulogic; + + -- Valids + dec_cpl_rf0_act : in std_ulogic; + dec_cpl_rf0_tid : in std_ulogic_vector(0 to threads-1); + + + -- FU Inputs + fu_xu_rf1_act : in std_ulogic_vector(0 to threads-1); + fu_xu_ex1_ifar : in std_ulogic_vector(0 to eff_ifar*threads-1); + fu_xu_ex2_ifar_val : in std_ulogic_vector(0 to threads-1); + fu_xu_ex2_ifar_issued : in std_ulogic_vector(0 to threads-1); + fu_xu_ex2_instr_type : in std_ulogic_vector(0 to 3*threads-1); + fu_xu_ex2_instr_match : in std_ulogic_vector(0 to threads-1); + fu_xu_ex2_is_ucode : in std_ulogic_vector(0 to threads-1); + + -- PC Inputs + pc_xu_step : in std_ulogic_vector(0 to threads-1); + pc_xu_stop : in std_ulogic_vector(0 to threads-1); + pc_xu_dbg_action : in std_ulogic_vector(0 to 3*threads-1); + pc_xu_force_ude : in std_ulogic_vector(0 to threads-1); + xu_pc_step_done : out std_ulogic_vector(0 to threads-1); + pc_xu_init_reset : in std_ulogic; + + -- Async Interrupt Req Interface + spr_cpl_ext_interrupt : in std_ulogic_vector(0 to threads-1); + spr_cpl_udec_interrupt : in std_ulogic_vector(0 to threads-1); + spr_cpl_perf_interrupt : in std_ulogic_vector(0 to threads-1); + spr_cpl_dec_interrupt : in std_ulogic_vector(0 to threads-1); + spr_cpl_fit_interrupt : in std_ulogic_vector(0 to threads-1); + spr_cpl_crit_interrupt : in std_ulogic_vector(0 to threads-1); + spr_cpl_wdog_interrupt : in std_ulogic_vector(0 to threads-1); + spr_cpl_dbell_interrupt : in std_ulogic_vector(0 to threads-1); + spr_cpl_cdbell_interrupt : in std_ulogic_vector(0 to threads-1); + spr_cpl_gdbell_interrupt : in std_ulogic_vector(0 to threads-1); + spr_cpl_gcdbell_interrupt : in std_ulogic_vector(0 to threads-1); + spr_cpl_gmcdbell_interrupt : in std_ulogic_vector(0 to threads-1); + + cpl_spr_ex5_dbell_taken : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_cdbell_taken : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_gdbell_taken : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_gcdbell_taken : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_gmcdbell_taken : out std_ulogic_vector(0 to threads-1); + + -- Interrupt Interface + cpl_spr_ex5_act : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_int : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_gint : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_cint : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_mcint : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_nia : out std_ulogic_vector(0 to eff_ifar*threads-1); + cpl_spr_ex5_esr : out std_ulogic_vector(0 to 17*threads-1); + cpl_spr_ex5_mcsr : out std_ulogic_vector(0 to 15*threads-1); + cpl_spr_ex5_dbsr : out std_ulogic_vector(0 to 19*threads-1); + cpl_spr_ex5_dear_save : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_dear_update_saved : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_dear_update : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_dbsr_update : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_esr_update : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_srr0_dec : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_force_gsrr : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_dbsr_ide : out std_ulogic_vector(0 to threads-1); + + spr_cpl_dbsr_ide : in std_ulogic_vector(0 to threads-1); + + -- Machine Check Interrupts + mm_xu_local_snoop_reject : in std_ulogic_vector(0 to threads-1); + mm_xu_lru_par_err : in std_ulogic_vector(0 to threads-1); + mm_xu_tlb_par_err : in std_ulogic_vector(0 to threads-1); + mm_xu_tlb_multihit_err : in std_ulogic_vector(0 to threads-1); + lsu_xu_ex3_derat_par_err : in std_ulogic_vector(0 to threads-1); + lsu_xu_ex4_derat_par_err : in std_ulogic_vector(0 to threads-1); + lsu_xu_ex3_derat_multihit_err : in std_ulogic_vector(0 to threads-1); + lsu_xu_ex3_l2_uc_ecc_err : in std_ulogic_vector(0 to threads-1); + lsu_xu_ex3_ddir_par_err : in std_ulogic; + lsu_xu_ex4_n_lsu_ddmh_flush : in std_ulogic_vector(0 to 3); + lsu_xu_ex6_datc_par_err : in std_ulogic; + spr_cpl_external_mchk : in std_ulogic_vector(0 to threads-1); + + -- PC Errors + xu_pc_err_attention_instr : out std_ulogic_vector(0 to threads-1); + xu_pc_err_nia_miscmpr : out std_ulogic_vector(0 to threads-1); + xu_pc_err_debug_event : out std_ulogic_vector(0 to threads-1); + + -- Data Storage + lsu_xu_ex3_dsi : in std_ulogic_vector(0 to threads-1); + derat_xu_ex3_dsi : in std_ulogic_vector(0 to threads-1); + spr_cpl_ex3_ct_le : in std_ulogic_vector(0 to threads-1); + spr_cpl_ex3_ct_be : in std_ulogic_vector(0 to threads-1); + + -- Alignment + lsu_xu_ex3_align : in std_ulogic_vector(0 to threads-1); + + -- Program + spr_cpl_ex3_spr_illeg : in std_ulogic; + spr_cpl_ex3_spr_priv : in std_ulogic; + + -- Hypv Privledge + spr_cpl_ex3_spr_hypv : in std_logic; + + -- Data TLB Miss + derat_xu_ex3_miss : in std_ulogic_vector(0 to threads-1); + + -- RAM + pc_xu_ram_mode : in std_ulogic; + pc_xu_ram_thread : in std_ulogic_vector(0 to 1); + pc_xu_ram_execute : in std_ulogic; + xu_iu_ram_issue : out std_ulogic_vector(0 to threads-1); + xu_pc_ram_interrupt : out std_ulogic; + xu_pc_ram_done : out std_ulogic; + pc_xu_ram_flush_thread : in std_ulogic; + + -- Run State + cpl_spr_stop : out std_ulogic_vector(0 to threads-1); + xu_pc_stop_dbg_event : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_instr_cpl : out std_ulogic_vector(0 to threads-1); + spr_cpl_quiesce : in std_ulogic_vector(0 to threads-1); + cpl_spr_quiesce : out std_ulogic_vector(0 to threads-1); + spr_cpl_ex2_run_ctl_flush : in std_ulogic_vector(0 to threads-1); + + -- MMU Flushes + mm_xu_illeg_instr : in std_ulogic_vector(0 to threads-1); + mm_xu_tlb_miss : in std_ulogic_vector(0 to threads-1); + mm_xu_pt_fault : in std_ulogic_vector(0 to threads-1); + mm_xu_tlb_inelig : in std_ulogic_vector(0 to threads-1); + mm_xu_lrat_miss : in std_ulogic_vector(0 to threads-1); + mm_xu_hv_priv : in std_ulogic_vector(0 to threads-1); + mm_xu_esr_pt : in std_ulogic_vector(0 to threads-1); + mm_xu_esr_data : in std_ulogic_vector(0 to threads-1); + mm_xu_esr_epid : in std_ulogic_vector(0 to threads-1); + mm_xu_esr_st : in std_ulogic_vector(0 to threads-1); + mm_xu_hold_req : in std_ulogic_vector(0 to threads-1); + mm_xu_hold_done : in std_ulogic_vector(0 to threads-1); + xu_mm_hold_ack : out std_ulogic_vector(0 to threads-1); + mm_xu_eratmiss_done : in std_ulogic_vector(0 to threads-1); + mm_xu_ex3_flush_req : in std_ulogic_vector(0 to threads-1); + + -- LSU Flushes + lsu_xu_l2_ecc_err_flush : in std_ulogic_vector(0 to threads-1); + lsu_xu_datc_perr_recovery : in std_ulogic; + lsu_xu_ex3_dep_flush : in std_ulogic; + lsu_xu_ex3_n_flush_req : in std_ulogic; + lsu_xu_ex3_ldq_hit_flush : in std_ulogic; + lsu_xu_ex4_ldq_full_flush : in std_ulogic; + derat_xu_ex3_n_flush_req : in std_ulogic_vector(0 to threads-1); + lsu_xu_ex3_inval_align_2ucode : in std_ulogic; + lsu_xu_ex3_attr : in std_ulogic_vector(0 to 8); + lsu_xu_ex3_derat_vf : in std_ulogic; + + -- AXU Flushes + fu_xu_ex3_ap_int_req : in std_ulogic_vector(0 to threads-1); + fu_xu_ex3_trap : in std_ulogic_vector(0 to threads-1); + fu_xu_ex3_n_flush : in std_ulogic_vector(0 to threads-1); + fu_xu_ex3_np1_flush : in std_ulogic_vector(0 to threads-1); + fu_xu_ex3_flush2ucode : in std_ulogic_vector(0 to threads-1); + fu_xu_ex2_async_block : in std_ulogic_vector(0 to threads-1); + + -- IU Flushes + xu_iu_ex5_br_taken : out std_ulogic; + xu_iu_ex5_ifar : out std_ulogic_vector(62-eff_ifar to 61); + xu_iu_flush : out std_ulogic_vector(0 to threads-1); + xu_iu_iu0_flush_ifar : out std_ulogic_vector(0 to eff_ifar*threads-1); + xu_iu_uc_flush_ifar : out std_ulogic_vector(0 to uc_ifar*threads-1); + xu_iu_flush_2ucode : out std_ulogic_vector(0 to threads-1); + xu_iu_flush_2ucode_type : out std_ulogic_vector(0 to threads-1); + xu_iu_ucode_restart : out std_ulogic_vector(0 to threads-1); + xu_iu_ex5_ppc_cpl : out std_ulogic_vector(0 to threads-1); + + -- Flushes + xu_rf0_flush : out std_ulogic_vector(0 to threads-1); + xu_rf1_flush : out std_ulogic_vector(0 to threads-1); + xu_ex1_flush : out std_ulogic_vector(0 to threads-1); + xu_ex2_flush : out std_ulogic_vector(0 to threads-1); + xu_ex3_flush : out std_ulogic_vector(0 to threads-1); + xu_ex4_flush : out std_ulogic_vector(0 to threads-1); + xu_n_is2_flush : out std_ulogic_vector(0 to threads-1); + xu_n_rf0_flush : out std_ulogic_vector(0 to threads-1); + xu_n_rf1_flush : out std_ulogic_vector(0 to threads-1); + xu_n_ex1_flush : out std_ulogic_vector(0 to threads-1); + xu_n_ex2_flush : out std_ulogic_vector(0 to threads-1); + xu_n_ex3_flush : out std_ulogic_vector(0 to threads-1); + xu_n_ex4_flush : out std_ulogic_vector(0 to threads-1); + xu_n_ex5_flush : out std_ulogic_vector(0 to threads-1); + xu_s_rf1_flush : out std_ulogic_vector(0 to threads-1); + xu_s_ex1_flush : out std_ulogic_vector(0 to threads-1); + xu_s_ex2_flush : out std_ulogic_vector(0 to threads-1); + xu_s_ex3_flush : out std_ulogic_vector(0 to threads-1); + xu_s_ex4_flush : out std_ulogic_vector(0 to threads-1); + xu_s_ex5_flush : out std_ulogic_vector(0 to threads-1); + xu_w_rf1_flush : out std_ulogic_vector(0 to threads-1); + xu_w_ex1_flush : out std_ulogic_vector(0 to threads-1); + xu_w_ex2_flush : out std_ulogic_vector(0 to threads-1); + xu_w_ex3_flush : out std_ulogic_vector(0 to threads-1); + xu_w_ex4_flush : out std_ulogic_vector(0 to threads-1); + xu_w_ex5_flush : out std_ulogic_vector(0 to threads-1); + xu_lsu_ex4_flush_local : out std_ulogic_vector(0 to threads-1); + xu_mm_ex4_flush : out std_ulogic_vector(0 to threads-1); + xu_mm_ex5_flush : out std_ulogic_vector(0 to threads-1); + xu_mm_ierat_flush : out std_ulogic_vector(0 to threads-1); + xu_mm_ierat_miss : out std_ulogic_vector(0 to threads-1); + xu_mm_ex5_perf_itlb : out std_ulogic_vector(0 to threads-1); + xu_mm_ex5_perf_dtlb : out std_ulogic_vector(0 to threads-1); + + + -- SPR Bits + spr_bit_act : in std_ulogic; + spr_cpl_iac1_en : in std_ulogic_vector(0 to threads-1); + spr_cpl_iac2_en : in std_ulogic_vector(0 to threads-1); + spr_cpl_iac3_en : in std_ulogic_vector(0 to threads-1); + spr_cpl_iac4_en : in std_ulogic_vector(0 to threads-1); + spr_dbcr1_iac12m : in std_ulogic_vector(0 to threads-1); + spr_dbcr1_iac34m : in std_ulogic_vector(0 to threads-1); + spr_cpl_fp_precise : in std_ulogic_vector(0 to threads-1); + spr_xucr0_mddp : in std_ulogic; + spr_xucr0_mdcp : in std_ulogic; + spr_msr_de : in std_ulogic_vector(0 to threads-1); + spr_msr_spv : in std_ulogic_vector(0 to threads-1); + spr_msr_fp : in std_ulogic_vector(0 to threads-1); + spr_msr_me : in std_ulogic_vector(0 to threads-1); + spr_msr_ucle : in std_ulogic_vector(0 to threads-1); + spr_msrp_uclep : in std_ulogic_vector(0 to threads-1); + spr_ccr2_ucode_dis : in std_ulogic; + spr_ccr2_ap : in std_ulogic_vector(0 to threads-1); + spr_dbcr0_idm : in std_ulogic_vector(0 to threads-1); + cpl_spr_dbcr0_edm : out std_ulogic_vector(0 to threads-1); + spr_dbcr0_icmp : in std_ulogic_vector(0 to threads-1); + spr_dbcr0_brt : in std_ulogic_vector(0 to threads-1); + spr_dbcr0_trap : in std_ulogic_vector(0 to threads-1); + spr_dbcr0_ret : in std_ulogic_vector(0 to threads-1); + spr_dbcr0_irpt : in std_ulogic_vector(0 to threads-1); + spr_epcr_dsigs : in std_ulogic_vector(0 to threads-1); + spr_epcr_isigs : in std_ulogic_vector(0 to threads-1); + spr_epcr_extgs : in std_ulogic_vector(0 to threads-1); + spr_epcr_dtlbgs : in std_ulogic_vector(0 to threads-1); + spr_epcr_itlbgs : in std_ulogic_vector(0 to threads-1); + spr_xucr4_div_barr_thres : out std_ulogic_vector(0 to 7); + spr_ccr0_we : in std_ulogic_vector(0 to threads-1); + spr_epcr_duvd : in std_ulogic_vector(0 to threads-1); + cpl_msr_gs : out std_ulogic_vector(0 to threads-1); + cpl_msr_pr : out std_ulogic_vector(0 to threads-1); + cpl_msr_fp : out std_ulogic_vector(0 to threads-1); + cpl_msr_spv : out std_ulogic_vector(0 to threads-1); + cpl_ccr2_ap : out std_ulogic_vector(0 to threads-1); + spr_xucr4_mmu_mchk : out std_ulogic; + + -- Cache invalidate + xu_lsu_ici : out std_ulogic; + xu_lsu_dci : out std_ulogic; + + -- Parity + spr_cpl_ex3_sprg_ce : in std_ulogic; + spr_cpl_ex3_sprg_ue : in std_ulogic; + iu_xu_ierat_ex2_flush_req : in std_ulogic_vector(0 to threads-1); + iu_xu_ierat_ex3_par_err : in std_ulogic_vector(0 to threads-1); + iu_xu_ierat_ex4_par_err : in std_ulogic_vector(0 to threads-1); + + -- Regfile Parity + fu_xu_ex3_regfile_err_det : in std_ulogic_vector(0 to threads-1); + xu_fu_regfile_seq_beg : out std_ulogic; + fu_xu_regfile_seq_end : in std_ulogic; + gpr_cpl_ex3_regfile_err_det : in std_ulogic; + cpl_gpr_regfile_seq_beg : out std_ulogic; + gpr_cpl_regfile_seq_end : in std_ulogic; + xu_pc_err_mcsr_summary : out std_ulogic_vector(0 to threads-1); + xu_pc_err_ditc_overrun : out std_ulogic; + xu_pc_err_local_snoop_reject : out std_ulogic; + xu_pc_err_tlb_lru_parity : out std_ulogic; + xu_pc_err_ext_mchk : out std_ulogic; + xu_pc_err_ierat_multihit : out std_ulogic; + xu_pc_err_derat_multihit : out std_ulogic; + xu_pc_err_tlb_multihit : out std_ulogic; + xu_pc_err_ierat_parity : out std_ulogic; + xu_pc_err_derat_parity : out std_ulogic; + xu_pc_err_tlb_parity : out std_ulogic; + xu_pc_err_mchk_disabled : out std_ulogic; + xu_pc_err_sprg_ue : out std_ulogic_vector(0 to threads-1); + + -- Debug + cpl_debug_mux_ctrls : in std_ulogic_vector(0 to 15); + cpl_debug_data_in : in std_ulogic_vector(0 to 87); + cpl_debug_data_out : out std_ulogic_vector(0 to 87); + cpl_trigger_data_in : in std_ulogic_vector(0 to 11); + cpl_trigger_data_out : out std_ulogic_vector(0 to 11); + fxa_cpl_debug : in std_ulogic_vector(0 to 272) +); + +-- synopsys translate_off + +-- synopsys translate_on +end xuq_cpl_fxub; +architecture xuq_cpl_fxub of xuq_cpl_fxub is + +signal clkoff_dc_b_b : std_ulogic; +signal d_mode_dc_b : std_ulogic; +signal delay_lclkr_dc_b : std_ulogic_vector(0 to 4); +signal mpw1_dc_b_b : std_ulogic_vector(0 to 4); +signal mpw2_dc_b_b : std_ulogic; +signal sg_2_b : std_ulogic_vector(0 to 3); +signal fce_2_b : std_ulogic_vector(0 to 1); +signal func_sl_thold_2_b : std_ulogic_vector(0 to 3); +signal func_slp_sl_thold_2_b : std_ulogic_vector(0 to 1); +signal func_nsl_thold_2_b : std_ulogic; +signal func_slp_nsl_thold_2_b : std_ulogic; +signal cfg_sl_thold_2_b : std_ulogic; +signal cfg_slp_sl_thold_2_b : std_ulogic; + +signal dec_cpl_ex3_mult_coll :std_ulogic; +signal dec_cpl_ex3_axu_instr_type :std_ulogic_vector(0 to 2); +signal dec_cpl_ex3_instr_hypv :std_ulogic; +signal dec_cpl_rf1_ucode_val :std_ulogic_vector(0 to threads-1); +signal dec_cpl_ex2_error :std_ulogic_vector(0 to 2); +signal dec_cpl_ex2_match :std_ulogic; +signal dec_cpl_ex2_is_ucode :std_ulogic; +signal dec_cpl_rf1_ifar :std_ulogic_vector(62-eff_ifar to 61); +signal dec_cpl_ex3_is_any_store :std_ulogic; +signal dec_cpl_ex2_is_any_load_dac :std_ulogic; +signal dec_cpl_ex3_instr_priv :std_ulogic; +signal dec_ex1_epid_instr :std_ulogic; +signal dec_cpl_ex2_illegal_op :std_ulogic; +signal alu_cpl_ex3_trap_val :std_ulogic; +signal mux_cpl_ex4_rt :std_ulogic_vector(64-(2**regmode) to 63); +signal dec_cpl_ex2_is_any_store_dac :std_ulogic; +signal dec_cpl_ex3_tlb_illeg :std_ulogic; +signal dec_cpl_ex3_mtdp_nr :std_ulogic; +signal mux_cpl_slowspr_done :std_ulogic_vector(0 to threads-1); +signal mux_cpl_slowspr_flush :std_ulogic_vector(0 to threads-1); +signal dec_cpl_rf1_val :std_ulogic_vector(0 to threads-1); +signal dec_cpl_rf1_issued :std_ulogic_vector(0 to threads-1); +signal dec_cpl_rf1_instr :std_ulogic_vector(0 to 31); +signal cpl_byp_ex3_spr_rt :std_ulogic_vector(64-(2**regmode) to 63); +signal byp_cpl_ex1_cr_bit :std_ulogic; +signal dec_cpl_rf1_pred_taken_cnt :std_ulogic; +signal dec_cpl_ex1_is_slowspr_wr :std_ulogic; +signal dec_cpl_ex3_ddmh_en :std_ulogic; +signal dec_cpl_ex3_back_inv :std_ulogic; +signal fxu_cpl_ex3_dac1r_cmpr_async :std_ulogic_vector(0 to threads-1); +signal fxu_cpl_ex3_dac2r_cmpr_async :std_ulogic_vector(0 to threads-1); +signal fxu_cpl_ex3_dac1r_cmpr :std_ulogic_vector(0 to threads-1); +signal fxu_cpl_ex3_dac2r_cmpr :std_ulogic_vector(0 to threads-1); +signal fxu_cpl_ex3_dac3r_cmpr :std_ulogic_vector(0 to threads-1); +signal fxu_cpl_ex3_dac4r_cmpr :std_ulogic_vector(0 to threads-1); +signal fxu_cpl_ex3_dac1w_cmpr :std_ulogic_vector(0 to threads-1); +signal fxu_cpl_ex3_dac2w_cmpr :std_ulogic_vector(0 to threads-1); +signal fxu_cpl_ex3_dac3w_cmpr :std_ulogic_vector(0 to threads-1); +signal fxu_cpl_ex3_dac4w_cmpr :std_ulogic_vector(0 to threads-1); +signal xu_ex1_eff_addr :std_ulogic_vector(64-(dc_size-3) to 63); +signal xu_rf0_flush_int :std_ulogic_vector(0 to threads-1); +signal xu_rf1_flush_int :std_ulogic_vector(0 to threads-1); +signal xu_ex1_flush_int :std_ulogic_vector(0 to threads-1); +signal xu_ex2_flush_int :std_ulogic_vector(0 to threads-1); +signal xu_ex3_flush_int :std_ulogic_vector(0 to threads-1); +signal xu_ex4_flush_int :std_ulogic_vector(0 to threads-1); +signal xu_ex5_flush_int :std_ulogic_vector(0 to threads-1); +signal cpl_perf_tx_events :std_ulogic_vector(0 to 75); +signal spr_cpl_async_int :std_ulogic_vector(0 to 3*threads-1); +signal spr_dbcr3_ivc_int :std_ulogic_vector(0 to threads-1); +signal dec_cpl_rf1_instr_trace_val :std_ulogic; +signal dec_cpl_rf1_instr_trace_type :std_ulogic_vector(0 to 1); +signal dec_cpl_ex3_instr_trace_val :std_ulogic; +signal cpl_dec_in_ucode :std_ulogic_vector(0 to threads-1); + + + +begin + +perf_count : for t in 0 to threads-1 generate +spr_cpl_async_int(0+3*t) <= spr_perf_tx_events(5+8*t); +spr_cpl_async_int(1+3*t) <= spr_perf_tx_events(6+8*t); +spr_cpl_async_int(2+3*t) <= spr_perf_tx_events(7+8*t); +end generate; + +clkoff_dc_b <= clkoff_dc_b_b; +d_mode_dc <= d_mode_dc_b; +delay_lclkr_dc <= delay_lclkr_dc_b; +mpw1_dc_b <= mpw1_dc_b_b; +mpw2_dc_b <= mpw2_dc_b_b; +sg_2 <= sg_2_b; +fce_2 <= fce_2_b; +func_sl_thold_2 <= func_sl_thold_2_b; +func_slp_sl_thold_2 <= func_slp_sl_thold_2_b; +func_nsl_thold_2 <= func_nsl_thold_2_b; +func_slp_nsl_thold_2 <= func_slp_nsl_thold_2_b; +cfg_sl_thold_2 <= cfg_sl_thold_2_b; +cfg_slp_sl_thold_2 <= cfg_slp_sl_thold_2_b; + + xuq_fxu_b : entity work.xuq_fxu_b(xuq_fxu_b) + generic map( + expand_type => expand_type, + threads => threads, + eff_ifar => eff_ifar, + regmode => regmode, + regsize => regsize, + a2mode => a2mode, + hvmode => hvmode, + dc_size => dc_size, + cl_size => cl_size, + real_data_add => real_data_add, + fxu_synth => fxu_synth) + port map( + nclk => nclk, + vdd => vdd, + gnd => gnd, + vcs => vcs, + func_scan_in => func_scan_in(54 to 58), + func_scan_out => func_scan_out(54 to 58), + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b, + pc_xu_ccflush_dc => pc_xu_ccflush_dc, + clkoff_dc_b => clkoff_dc_b_b, + d_mode_dc => d_mode_dc_b, + delay_lclkr_dc => delay_lclkr_dc_b, + mpw1_dc_b => mpw1_dc_b_b, + mpw2_dc_b => mpw2_dc_b_b, + g6t_clkoff_dc_b => g6t_clkoff_dc_b, + g6t_d_mode_dc => g6t_d_mode_dc, + g6t_delay_lclkr_dc => g6t_delay_lclkr_dc, + g6t_mpw1_dc_b => g6t_mpw1_dc_b, + g6t_mpw2_dc_b => g6t_mpw2_dc_b, + g8t_clkoff_dc_b => g8t_clkoff_dc_b, + g8t_d_mode_dc => g8t_d_mode_dc, + g8t_delay_lclkr_dc => g8t_delay_lclkr_dc, + g8t_mpw1_dc_b => g8t_mpw1_dc_b, + g8t_mpw2_dc_b => g8t_mpw2_dc_b, + cam_clkoff_dc_b => cam_clkoff_dc_b, + cam_d_mode_dc => cam_d_mode_dc, + cam_delay_lclkr_dc => cam_delay_lclkr_dc, + cam_act_dis_dc => cam_act_dis_dc, + cam_mpw1_dc_b => cam_mpw1_dc_b, + cam_mpw2_dc_b => cam_mpw2_dc_b, + pc_xu_sg_3 => pc_xu_sg_3, + pc_xu_func_sl_thold_3 => pc_xu_func_sl_thold_3, + pc_xu_func_slp_sl_thold_3 => pc_xu_func_slp_sl_thold_3, + pc_xu_func_nsl_thold_3 => pc_xu_func_nsl_thold_3, + pc_xu_func_slp_nsl_thold_3 => pc_xu_func_slp_nsl_thold_3, + pc_xu_gptr_sl_thold_3 => pc_xu_gptr_sl_thold_3, + pc_xu_abst_sl_thold_3 => pc_xu_abst_sl_thold_3, + pc_xu_abst_slp_sl_thold_3 => pc_xu_abst_slp_sl_thold_3, + pc_xu_regf_sl_thold_3 => pc_xu_regf_sl_thold_3, + pc_xu_regf_slp_sl_thold_3 => pc_xu_regf_slp_sl_thold_3, + pc_xu_time_sl_thold_3 => pc_xu_time_sl_thold_3, + pc_xu_cfg_sl_thold_3 => pc_xu_cfg_sl_thold_3, + pc_xu_cfg_slp_sl_thold_3 => pc_xu_cfg_slp_sl_thold_3, + pc_xu_ary_nsl_thold_3 => pc_xu_ary_nsl_thold_3, + pc_xu_ary_slp_nsl_thold_3 => pc_xu_ary_slp_nsl_thold_3, + pc_xu_repr_sl_thold_3 => pc_xu_repr_sl_thold_3, + pc_xu_bolt_sl_thold_3 => pc_xu_bolt_sl_thold_3, + pc_xu_bo_enable_3 => pc_xu_bo_enable_3, + pc_xu_fce_3 => pc_xu_fce_3, + an_ac_scan_diag_dc => an_ac_scan_diag_dc, + sg_2 => sg_2_b, + fce_2 => fce_2_b, + func_sl_thold_2 => func_sl_thold_2_b, + func_slp_sl_thold_2 => func_slp_sl_thold_2_b, + func_nsl_thold_2 => func_nsl_thold_2_b, + func_slp_nsl_thold_2 => func_slp_nsl_thold_2_b, + abst_sl_thold_2 => abst_sl_thold_2, + abst_slp_sl_thold_2 => abst_slp_sl_thold_2, + time_sl_thold_2 => time_sl_thold_2, + gptr_sl_thold_2 => gptr_sl_thold_2, + ary_nsl_thold_2 => ary_nsl_thold_2, + ary_slp_nsl_thold_2 => ary_slp_nsl_thold_2, + repr_sl_thold_2 => repr_sl_thold_2, + cfg_sl_thold_2 => cfg_sl_thold_2_b, + cfg_slp_sl_thold_2 => cfg_slp_sl_thold_2_b, + regf_slp_sl_thold_2 => regf_slp_sl_thold_2, + bolt_sl_thold_2 => bolt_sl_thold_2, + bo_enable_2 => bo_enable_2, + gptr_scan_in => gptr_scan_in, + gptr_scan_out => gptr_scan_out, + fxa_fxb_rf0_val => fxa_fxb_rf0_val, + fxa_fxb_rf0_issued => fxa_fxb_rf0_issued, + fxa_fxb_rf0_ucode_val => fxa_fxb_rf0_ucode_val, + fxa_fxb_rf0_act => fxa_fxb_rf0_act, + fxa_fxb_ex1_hold_ctr_flush => fxa_fxb_ex1_hold_ctr_flush, + fxa_fxb_rf0_instr => fxa_fxb_rf0_instr, + fxa_fxb_rf0_tid => fxa_fxb_rf0_tid, + fxa_fxb_rf0_ta_vld => fxa_fxb_rf0_ta_vld, + fxa_fxb_rf0_ta => fxa_fxb_rf0_ta, + fxa_fxb_rf0_error => fxa_fxb_rf0_error, + fxa_fxb_rf0_match => fxa_fxb_rf0_match, + fxa_fxb_rf0_is_ucode => fxa_fxb_rf0_is_ucode, + fxa_fxb_rf0_gshare => fxa_fxb_rf0_gshare, + fxa_fxb_rf0_ifar => fxa_fxb_rf0_ifar, + fxa_fxb_rf0_s1_vld => fxa_fxb_rf0_s1_vld, + fxa_fxb_rf0_s1 => fxa_fxb_rf0_s1, + fxa_fxb_rf0_s2_vld => fxa_fxb_rf0_s2_vld, + fxa_fxb_rf0_s2 => fxa_fxb_rf0_s2, + fxa_fxb_rf0_s3_vld => fxa_fxb_rf0_s3_vld, + fxa_fxb_rf0_s3 => fxa_fxb_rf0_s3, + fxa_fxb_rf0_axu_instr_type => fxa_fxb_rf0_axu_instr_type, + fxa_fxb_rf0_axu_ld_or_st => fxa_fxb_rf0_axu_ld_or_st, + fxa_fxb_rf0_axu_store => fxa_fxb_rf0_axu_store, + fxa_fxb_rf0_axu_ldst_forcealign => fxa_fxb_rf0_axu_ldst_forcealign, + fxa_fxb_rf0_axu_ldst_forceexcept => fxa_fxb_rf0_axu_ldst_forceexcept, + fxa_fxb_rf0_axu_ldst_indexed => fxa_fxb_rf0_axu_ldst_indexed, + fxa_fxb_rf0_axu_ldst_tag => fxa_fxb_rf0_axu_ldst_tag, + fxa_fxb_rf0_axu_mftgpr => fxa_fxb_rf0_axu_mftgpr, + fxa_fxb_rf0_axu_mffgpr => fxa_fxb_rf0_axu_mffgpr, + fxa_fxb_rf0_axu_movedp => fxa_fxb_rf0_axu_movedp, + fxa_fxb_rf0_axu_ldst_size => fxa_fxb_rf0_axu_ldst_size, + fxa_fxb_rf0_axu_ldst_update => fxa_fxb_rf0_axu_ldst_update, + fxa_fxb_rf0_pred_update => fxa_fxb_rf0_pred_update, + fxa_fxb_rf0_pred_taken_cnt => fxa_fxb_rf0_pred_taken_cnt, + fxa_fxb_rf0_mc_dep_chk_val => fxa_fxb_rf0_mc_dep_chk_val, + fxa_fxb_rf1_mul_val => fxa_fxb_rf1_mul_val, + fxa_fxb_rf1_muldiv_coll => fxa_fxb_rf1_muldiv_coll, + fxa_fxb_rf1_div_val => fxa_fxb_rf1_div_val, + fxa_fxb_rf1_div_ctr => fxa_fxb_rf1_div_ctr, + fxa_fxb_rf0_xu_epid_instr => fxa_fxb_rf0_xu_epid_instr, + fxa_fxb_rf0_axu_is_extload => fxa_fxb_rf0_axu_is_extload, + fxa_fxb_rf0_axu_is_extstore => fxa_fxb_rf0_axu_is_extstore, + fxa_fxb_rf0_is_mfocrf => fxa_fxb_rf0_is_mfocrf, + fxa_fxb_rf0_3src_instr => fxa_fxb_rf0_3src_instr, + fxa_fxb_rf0_gpr0_zero => fxa_fxb_rf0_gpr0_zero, + fxa_fxb_rf0_use_imm => fxa_fxb_rf0_use_imm, + fxb_fxa_ex7_we0 => fxb_fxa_ex7_we0, + fxb_fxa_ex7_wa0 => fxb_fxa_ex7_wa0, + fxb_fxa_ex7_wd0 => fxb_fxa_ex7_wd0, + fxa_fxb_rf1_do0 => fxa_fxb_rf1_do0, + fxa_fxb_rf1_do1 => fxa_fxb_rf1_do1, + fxa_fxb_rf1_do2 => fxa_fxb_rf1_do2, + xu_lsu_rf0_act => xu_lsu_rf0_act, + xu_lsu_rf1_cache_acc => xu_lsu_rf1_cache_acc, + xu_lsu_rf1_thrd_id => xu_lsu_rf1_thrd_id, + xu_lsu_rf1_optype1 => xu_lsu_rf1_optype1, + xu_lsu_rf1_optype2 => xu_lsu_rf1_optype2, + xu_lsu_rf1_optype4 => xu_lsu_rf1_optype4, + xu_lsu_rf1_optype8 => xu_lsu_rf1_optype8, + xu_lsu_rf1_optype16 => xu_lsu_rf1_optype16, + xu_lsu_rf1_optype32 => xu_lsu_rf1_optype32, + xu_lsu_rf1_target_gpr => xu_lsu_rf1_target_gpr, + xu_lsu_rf1_load_instr => xu_lsu_rf1_load_instr, + xu_lsu_rf1_store_instr => xu_lsu_rf1_store_instr, + xu_lsu_rf1_dcbf_instr => xu_lsu_rf1_dcbf_instr, + xu_lsu_rf1_sync_instr => xu_lsu_rf1_sync_instr, + xu_lsu_rf1_mbar_instr => xu_lsu_rf1_mbar_instr, + xu_lsu_rf1_l_fld => xu_lsu_rf1_l_fld, + xu_lsu_rf1_dcbi_instr => xu_lsu_rf1_dcbi_instr, + xu_lsu_rf1_dcbz_instr => xu_lsu_rf1_dcbz_instr, + xu_lsu_rf1_dcbt_instr => xu_lsu_rf1_dcbt_instr, + xu_lsu_rf1_dcbtst_instr => xu_lsu_rf1_dcbtst_instr, + xu_lsu_rf1_th_fld => xu_lsu_rf1_th_fld, + xu_lsu_rf1_dcbtls_instr => xu_lsu_rf1_dcbtls_instr, + xu_lsu_rf1_dcbtstls_instr => xu_lsu_rf1_dcbtstls_instr, + xu_lsu_rf1_dcblc_instr => xu_lsu_rf1_dcblc_instr, + xu_lsu_rf1_dcbst_instr => xu_lsu_rf1_dcbst_instr, + xu_lsu_rf1_icbi_instr => xu_lsu_rf1_icbi_instr, + xu_lsu_rf1_icblc_instr => xu_lsu_rf1_icblc_instr, + xu_lsu_rf1_icbt_instr => xu_lsu_rf1_icbt_instr, + xu_lsu_rf1_icbtls_instr => xu_lsu_rf1_icbtls_instr, + xu_lsu_rf1_tlbsync_instr => xu_lsu_rf1_tlbsync_instr, + xu_lsu_rf1_lock_instr => xu_lsu_rf1_lock_instr, + xu_lsu_rf1_mutex_hint => xu_lsu_rf1_mutex_hint, + xu_lsu_rf1_axu_op_val => xu_lsu_rf1_axu_op_val, + xu_lsu_rf1_axu_ldst_falign => xu_lsu_rf1_axu_ldst_falign, + xu_lsu_rf1_axu_ldst_fexcpt => xu_lsu_rf1_axu_ldst_fexcpt, + xu_lsu_ex1_store_data => xu_lsu_ex1_store_data, + xu_lsu_rf1_algebraic => xu_lsu_rf1_algebraic, + xu_lsu_rf1_byte_rev => xu_lsu_rf1_byte_rev, + xu_lsu_rf1_src_gpr => xu_lsu_rf1_src_gpr, + xu_lsu_rf1_src_axu => xu_lsu_rf1_src_axu, + xu_lsu_rf1_src_dp => xu_lsu_rf1_src_dp, + xu_lsu_rf1_targ_gpr => xu_lsu_rf1_targ_gpr, + xu_lsu_rf1_targ_axu => xu_lsu_rf1_targ_axu, + xu_lsu_rf1_targ_dp => xu_lsu_rf1_targ_dp, + xu_lsu_ex1_rotsel_ovrd => xu_lsu_ex1_rotsel_ovrd, + xu_lsu_rf1_derat_act => xu_lsu_rf1_derat_act, + xu_lsu_rf1_derat_is_load => xu_lsu_rf1_derat_is_load, + xu_lsu_rf1_derat_is_store => xu_lsu_rf1_derat_is_store, + xu_lsu_rf1_src0_vld => xu_lsu_rf1_src0_vld, + xu_lsu_rf1_src0_reg => xu_lsu_rf1_src0_reg, + xu_lsu_rf1_src1_vld => xu_lsu_rf1_src1_vld, + xu_lsu_rf1_src1_reg => xu_lsu_rf1_src1_reg, + xu_lsu_rf1_targ_vld => xu_lsu_rf1_targ_vld, + xu_lsu_rf1_targ_reg => xu_lsu_rf1_targ_reg, + xu_bx_ex1_mtdp_val => xu_bx_ex1_mtdp_val, + xu_bx_ex1_mfdp_val => xu_bx_ex1_mfdp_val, + xu_bx_ex1_ipc_thrd => xu_bx_ex1_ipc_thrd, + xu_bx_ex2_ipc_ba => xu_bx_ex2_ipc_ba, + xu_bx_ex2_ipc_sz => xu_bx_ex2_ipc_sz, + xu_lsu_rf1_is_touch => xu_lsu_rf1_is_touch, + xu_lsu_rf1_is_msgsnd => xu_lsu_rf1_is_msgsnd, + xu_lsu_rf1_dci_instr => xu_lsu_rf1_dci_instr, + xu_lsu_rf1_ici_instr => xu_lsu_rf1_ici_instr, + xu_lsu_rf1_icswx_instr => xu_lsu_rf1_icswx_instr, + xu_lsu_rf1_icswx_dot_instr => xu_lsu_rf1_icswx_dot_instr, + xu_lsu_rf1_icswx_epid => xu_lsu_rf1_icswx_epid, + xu_lsu_rf1_ldawx_instr => xu_lsu_rf1_ldawx_instr, + xu_lsu_rf1_wclr_instr => xu_lsu_rf1_wclr_instr, + xu_lsu_rf1_wchk_instr => xu_lsu_rf1_wchk_instr, + xu_lsu_rf1_derat_ra_eq_ea => xu_lsu_rf1_derat_ra_eq_ea, + xu_lsu_rf1_cmd_act => xu_lsu_rf1_cmd_act, + xu_lsu_rf1_data_act => xu_lsu_rf1_data_act, + xu_lsu_rf1_mtspr_trace => xu_lsu_rf1_mtspr_trace, + lsu_xu_ex5_wren => lsu_xu_ex5_wren, + lsu_xu_rel_wren => lsu_xu_rel_wren, + lsu_xu_rel_ta_gpr => lsu_xu_rel_ta_gpr, + lsu_xu_need_hole => lsu_xu_need_hole, + lsu_xu_rot_ex6_data_b => lsu_xu_rot_ex6_data_b, + lsu_xu_rot_rel_data => lsu_xu_rot_rel_data(64-(2**regmode) to 63), + xu_lsu_ex4_dvc1_en => xu_lsu_ex4_dvc1_en, + xu_lsu_ex4_dvc2_en => xu_lsu_ex4_dvc2_en, + lsu_xu_ex2_dvc1_st_cmp => lsu_xu_ex2_dvc1_st_cmp, + lsu_xu_ex2_dvc2_st_cmp => lsu_xu_ex2_dvc2_st_cmp, + lsu_xu_ex8_dvc1_ld_cmp => lsu_xu_ex8_dvc1_ld_cmp, + lsu_xu_ex8_dvc2_ld_cmp => lsu_xu_ex8_dvc2_ld_cmp, + lsu_xu_rel_dvc1_en => lsu_xu_rel_dvc1_en, + lsu_xu_rel_dvc2_en => lsu_xu_rel_dvc2_en, + lsu_xu_rel_dvc_thrd_id => lsu_xu_rel_dvc_thrd_id, + lsu_xu_rel_dvc1_cmp => lsu_xu_rel_dvc1_cmp, + lsu_xu_rel_dvc2_cmp => lsu_xu_rel_dvc2_cmp, + xu_lsu_ex1_add_src0 => xu_lsu_ex1_add_src0, + xu_lsu_ex1_add_src1 => xu_lsu_ex1_add_src1, + xu_ex1_eff_addr_int => xu_ex1_eff_addr, + xu_iu_rf1_val => xu_iu_rf1_val, + xu_rf1_val => xu_rf1_val, + xu_rf1_is_tlbre => xu_rf1_is_tlbre, + xu_rf1_is_tlbwe => xu_rf1_is_tlbwe, + xu_rf1_is_tlbsx => xu_rf1_is_tlbsx, + xu_rf1_is_tlbsrx => xu_rf1_is_tlbsrx, + xu_rf1_is_tlbilx => xu_rf1_is_tlbilx, + xu_rf1_is_tlbivax => xu_rf1_is_tlbivax, + xu_rf1_is_eratre => xu_rf1_is_eratre, + xu_rf1_is_eratwe => xu_rf1_is_eratwe, + xu_rf1_is_eratsx => xu_rf1_is_eratsx, + xu_rf1_is_eratsrx => xu_rf1_is_eratsrx, + xu_rf1_is_eratilx => xu_rf1_is_eratilx, + xu_rf1_is_erativax => xu_rf1_is_erativax, + xu_ex1_is_isync => xu_ex1_is_isync, + xu_ex1_is_csync => xu_ex1_is_csync, + xu_rf1_ws => xu_rf1_ws, + xu_rf1_t => xu_rf1_t, + xu_ex1_rs_is => xu_ex1_rs_is, + xu_ex1_ra_entry => xu_ex1_ra_entry, + xu_ex1_rb => xu_ex1_rb, + xu_ex2_eff_addr => xu_ex2_eff_addr, + xu_ex4_rs_data => xu_ex4_rs_data, + lsu_xu_ex4_tlb_data => lsu_xu_ex4_tlb_data, + iu_xu_ex4_tlb_data => iu_xu_ex4_tlb_data, + xu_mm_derat_epn => xu_mm_derat_epn, + lsu_xu_is2_back_inv => lsu_xu_is2_back_inv, + lsu_xu_is2_back_inv_addr => lsu_xu_is2_back_inv_addr, + mm_xu_mmucr0_0_tlbsel => mm_xu_mmucr0_0_tlbsel, + mm_xu_mmucr0_1_tlbsel => mm_xu_mmucr0_1_tlbsel, + mm_xu_mmucr0_2_tlbsel => mm_xu_mmucr0_2_tlbsel, + mm_xu_mmucr0_3_tlbsel => mm_xu_mmucr0_3_tlbsel, + xu_mm_rf1_is_tlbsxr => xu_mm_rf1_is_tlbsxr, + mm_xu_cr0_eq_valid => mm_xu_cr0_eq_valid, + mm_xu_cr0_eq => mm_xu_cr0_eq, + fu_xu_ex4_cr_val => fu_xu_ex4_cr_val, + fu_xu_ex4_cr_noflush => fu_xu_ex4_cr_noflush, + fu_xu_ex4_cr0 => fu_xu_ex4_cr0, + fu_xu_ex4_cr0_bf => fu_xu_ex4_cr0_bf, + fu_xu_ex4_cr1 => fu_xu_ex4_cr1, + fu_xu_ex4_cr1_bf => fu_xu_ex4_cr1_bf, + fu_xu_ex4_cr2 => fu_xu_ex4_cr2, + fu_xu_ex4_cr2_bf => fu_xu_ex4_cr2_bf, + fu_xu_ex4_cr3 => fu_xu_ex4_cr3, + fu_xu_ex4_cr3_bf => fu_xu_ex4_cr3_bf, + xu_pc_ram_data => xu_pc_ram_data, + xu_iu_ex5_val => xu_iu_ex5_val, + xu_iu_ex5_tid => xu_iu_ex5_tid, + xu_iu_ex5_br_update => xu_iu_ex5_br_update, + xu_iu_ex5_br_hist => xu_iu_ex5_br_hist, + xu_iu_ex5_bclr => xu_iu_ex5_bclr, + xu_iu_ex5_lk => xu_iu_ex5_lk, + xu_iu_ex5_bh => xu_iu_ex5_bh, + xu_iu_ex6_pri => xu_iu_ex6_pri, + xu_iu_ex6_pri_val => xu_iu_ex6_pri_val, + xu_iu_spr_xer => xu_iu_spr_xer, + xu_iu_slowspr_done => xu_iu_slowspr_done, + xu_iu_need_hole => xu_iu_need_hole, + fxb_fxa_ex6_clear_barrier => fxb_fxa_ex6_clear_barrier, + xu_iu_ex5_gshare => xu_iu_ex5_gshare, + xu_iu_ex5_getNIA => xu_iu_ex5_getNIA, + an_ac_stcx_complete => an_ac_stcx_complete, + an_ac_stcx_pass => an_ac_stcx_pass, + an_ac_back_inv => an_ac_back_inv, + an_ac_back_inv_addr => an_ac_back_inv_addr, + an_ac_back_inv_target_bit3 => an_ac_back_inv_target_bit3, + slowspr_val_in => slowspr_val_in, + slowspr_rw_in => slowspr_rw_in, + slowspr_etid_in => slowspr_etid_in, + slowspr_addr_in => slowspr_addr_in, + slowspr_data_in => slowspr_data_in, + slowspr_done_in => slowspr_done_in, + an_ac_dcr_act => an_ac_dcr_act, + an_ac_dcr_val => an_ac_dcr_val, + an_ac_dcr_read => an_ac_dcr_read, + an_ac_dcr_etid => an_ac_dcr_etid, + an_ac_dcr_data => an_ac_dcr_data, + an_ac_dcr_done => an_ac_dcr_done, + lsu_xu_ex4_mtdp_cr_status => lsu_xu_ex4_mtdp_cr_status, + lsu_xu_ex4_mfdp_cr_status => lsu_xu_ex4_mfdp_cr_status, + lsu_xu_ex4_cr_upd => lsu_xu_ex4_cr_upd, + lsu_xu_ex5_cr_rslt => lsu_xu_ex5_cr_rslt, + dec_cpl_ex3_mult_coll => dec_cpl_ex3_mult_coll, + dec_cpl_ex3_axu_instr_type => dec_cpl_ex3_axu_instr_type, + dec_cpl_ex3_instr_hypv => dec_cpl_ex3_instr_hypv, + dec_cpl_rf1_ucode_val => dec_cpl_rf1_ucode_val, + dec_cpl_ex2_error => dec_cpl_ex2_error, + dec_cpl_ex2_match => dec_cpl_ex2_match, + dec_cpl_ex2_is_ucode => dec_cpl_ex2_is_ucode, + dec_cpl_rf1_ifar => dec_cpl_rf1_ifar, + dec_cpl_ex3_is_any_store => dec_cpl_ex3_is_any_store, + dec_cpl_ex2_is_any_load_dac => dec_cpl_ex2_is_any_load_dac, + dec_cpl_ex3_instr_priv => dec_cpl_ex3_instr_priv, + dec_cpl_ex1_epid_instr => dec_ex1_epid_instr, + dec_cpl_ex2_illegal_op => dec_cpl_ex2_illegal_op, + alu_cpl_ex3_trap_val => alu_cpl_ex3_trap_val, + mux_cpl_ex4_rt => mux_cpl_ex4_rt, + dec_cpl_ex2_is_any_store_dac => dec_cpl_ex2_is_any_store_dac, + dec_cpl_ex3_tlb_illeg => dec_cpl_ex3_tlb_illeg, + dec_cpl_ex3_mtdp_nr => dec_cpl_ex3_mtdp_nr, + mux_cpl_slowspr_done => mux_cpl_slowspr_done, + mux_cpl_slowspr_flush => mux_cpl_slowspr_flush, + dec_cpl_rf1_val => dec_cpl_rf1_val, + dec_cpl_rf1_issued => dec_cpl_rf1_issued, + dec_cpl_rf1_instr => dec_cpl_rf1_instr, + cpl_byp_ex3_spr_rt => cpl_byp_ex3_spr_rt, + byp_cpl_ex1_cr_bit => byp_cpl_ex1_cr_bit, + dec_cpl_rf1_pred_taken_cnt => dec_cpl_rf1_pred_taken_cnt, + dec_cpl_ex1_is_slowspr_wr => dec_cpl_ex1_is_slowspr_wr, + dec_cpl_ex3_ddmh_en => dec_cpl_ex3_ddmh_en, + dec_cpl_ex3_back_inv => dec_cpl_ex3_back_inv, + xu_rf1_flush => xu_rf1_flush_int, + xu_ex1_flush => xu_ex1_flush_int, + xu_ex2_flush => xu_ex2_flush_int, + xu_ex3_flush => xu_ex3_flush_int, + xu_ex4_flush => xu_ex4_flush_int, + xu_ex5_flush => xu_ex5_flush_int, + dec_spr_ex4_val => dec_spr_ex4_val, + mux_spr_ex2_rt => mux_spr_ex2_rt, + fxu_spr_ex1_rs0 => fxu_spr_ex1_rs0, + fxu_spr_ex1_rs1 => fxu_spr_ex1_rs1, + spr_bit_act => spr_bit_act, + spr_msr_cm => spr_msr_cm, + spr_dec_spr_xucr0_ssdly => spr_dec_spr_xucr0_ssdly, + spr_ccr2_en_attn => spr_ccr2_en_attn, + spr_ccr2_en_ditc => spr_ccr2_en_ditc, + spr_ccr2_en_pc => spr_ccr2_en_pc, + spr_ccr2_en_icswx => spr_ccr2_en_icswx, + spr_ccr2_en_dcr => spr_ccr2_en_dcr, + spr_dec_rf1_epcr_dgtmi => spr_dec_rf1_epcr_dgtmi, + spr_dec_rf1_msrp_uclep => spr_dec_rf1_msrp_uclep, + spr_dec_rf1_msr_ucle => spr_dec_rf1_msr_ucle, + spr_byp_ex4_is_mfxer => spr_byp_ex4_is_mfxer, + spr_byp_ex3_spr_rt => spr_byp_ex3_spr_rt, + spr_byp_ex4_is_mtxer => spr_byp_ex4_is_mtxer, + spr_ccr2_notlb => spr_ccr2_notlb, + dec_spr_rf1_val => dec_spr_rf1_val, + fxu_spr_ex1_rs2 => fxu_spr_ex1_rs2, + fxa_perf_muldiv_in_use => fxa_perf_muldiv_in_use, + cpl_perf_tx_events => cpl_perf_tx_events, + spr_perf_tx_events => spr_perf_tx_events, + xu_pc_event_data => xu_pc_event_data, + pc_xu_event_bus_enable => pc_xu_event_bus_enable, + pc_xu_event_count_mode => pc_xu_event_count_mode, + pc_xu_event_mux_ctrls => pc_xu_event_mux_ctrls, + pc_xu_trace_bus_enable => pc_xu_trace_bus_enable, + pc_xu_instr_trace_mode => pc_xu_instr_trace_mode, + pc_xu_instr_trace_tid => pc_xu_instr_trace_tid, + xu_lsu_ex2_instr_trace_val => xu_lsu_ex2_instr_trace_val, + dec_cpl_rf1_instr_trace_val => dec_cpl_rf1_instr_trace_val, + dec_cpl_rf1_instr_trace_type => dec_cpl_rf1_instr_trace_type, + dec_cpl_ex3_instr_trace_val => dec_cpl_ex3_instr_trace_val, + cpl_dec_in_ucode => cpl_dec_in_ucode, + lsu_xu_data_debug0 => lsu_xu_data_debug0, + lsu_xu_data_debug1 => lsu_xu_data_debug1, + lsu_xu_data_debug2 => lsu_xu_data_debug2, + fxu_debug_mux_ctrls => fxu_debug_mux_ctrls, + fxu_debug_data_in => fxu_debug_data_in, + fxu_trigger_data_in => fxu_trigger_data_in, + fxu_debug_data_out => fxu_debug_data_out, + fxu_trigger_data_out => fxu_trigger_data_out, + fxu_cpl_ex3_dac1r_cmpr_async => fxu_cpl_ex3_dac1r_cmpr_async, + fxu_cpl_ex3_dac2r_cmpr_async => fxu_cpl_ex3_dac2r_cmpr_async, + fxu_cpl_ex3_dac1r_cmpr => fxu_cpl_ex3_dac1r_cmpr, + fxu_cpl_ex3_dac2r_cmpr => fxu_cpl_ex3_dac2r_cmpr, + fxu_cpl_ex3_dac3r_cmpr => fxu_cpl_ex3_dac3r_cmpr, + fxu_cpl_ex3_dac4r_cmpr => fxu_cpl_ex3_dac4r_cmpr, + fxu_cpl_ex3_dac1w_cmpr => fxu_cpl_ex3_dac1w_cmpr, + fxu_cpl_ex3_dac2w_cmpr => fxu_cpl_ex3_dac2w_cmpr, + fxu_cpl_ex3_dac3w_cmpr => fxu_cpl_ex3_dac3w_cmpr, + fxu_cpl_ex3_dac4w_cmpr => fxu_cpl_ex3_dac4w_cmpr, + spr_msr_gs => spr_msr_gs, + spr_msr_ds => spr_msr_ds, + spr_msr_pr => spr_msr_pr, + spr_dbcr0_dac1 => spr_dbcr0_dac1, + spr_dbcr0_dac2 => spr_dbcr0_dac2, + spr_dbcr0_dac3 => spr_dbcr0_dac3, + spr_dbcr0_dac4 => spr_dbcr0_dac4, + spr_dbcr3_ivc => spr_dbcr3_ivc_int, + spr_xucr0_clkg_ctl => spr_xucr0_clkg_ctl(2 to 2) + ); + + xu_cpl : entity work.xuq_cpl(xuq_cpl) + generic map( + expand_type => expand_type, + threads => threads, + regsize => regsize, + eff_ifar => eff_ifar) + port map( + -- Clocks + nclk => nclk, + -- CHIP IO + ac_tc_debug_trigger => ac_tc_debug_trigger, + -- Pervasive + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b, + pc_xu_ccflush_dc => pc_xu_ccflush_dc, + clkoff_dc_b => clkoff_dc_b_b, + d_mode_dc => d_mode_dc_b, + delay_lclkr_dc => delay_lclkr_dc_b(3), + mpw1_dc_b => mpw1_dc_b_b(3), + mpw2_dc_b => mpw2_dc_b_b, + func_slp_sl_thold_2 => func_slp_sl_thold_2_b(0), + func_slp_nsl_thold_2 => func_slp_nsl_thold_2_b, + func_sl_thold_2 => func_sl_thold_2_b(0), + func_nsl_thold_2 => func_nsl_thold_2_b, + cfg_sl_thold_2 => cfg_sl_thold_2_b, + cfg_slp_sl_thold_2 => cfg_slp_sl_thold_2_b, + sg_2 => sg_2_b(0), + fce_2 => fce_2_b(0), + func_scan_in => func_scan_in(50 to 53), + func_scan_out => func_scan_out(50 to 53), + bcfg_scan_in => bcfg_scan_in, + bcfg_scan_out => bcfg_scan_out, + ccfg_scan_in => ccfg_scan_in, + ccfg_scan_out => ccfg_scan_out, + dcfg_scan_in => dcfg_scan_in, + dcfg_scan_out => dcfg_scan_out, + + -- Valids + dec_cpl_rf0_act => dec_cpl_rf0_act, + dec_cpl_rf0_tid => dec_cpl_rf0_tid, + dec_cpl_rf1_val => dec_cpl_rf1_val, + dec_cpl_rf1_issued => dec_cpl_rf1_issued, + -- FU Inputs + fu_xu_rf1_act => fu_xu_rf1_act, + fu_xu_ex2_ifar_val => fu_xu_ex2_ifar_val, + fu_xu_ex2_ifar_issued => fu_xu_ex2_ifar_issued, + fu_xu_ex1_ifar => fu_xu_ex1_ifar, + fu_xu_ex2_instr_type => fu_xu_ex2_instr_type, + fu_xu_ex2_instr_match => fu_xu_ex2_instr_match, + fu_xu_ex2_is_ucode => fu_xu_ex2_is_ucode, + fu_xu_ex3_trap => fu_xu_ex3_trap, + fu_xu_ex3_ap_int_req => fu_xu_ex3_ap_int_req, + -- PC Inputs + pc_xu_step => pc_xu_step, + pc_xu_stop => pc_xu_stop, + pc_xu_dbg_action => pc_xu_dbg_action, + pc_xu_force_ude => pc_xu_force_ude, + xu_pc_step_done => xu_pc_step_done, + -- Bypass Inputs + byp_cpl_ex1_cr_bit => byp_cpl_ex1_cr_bit, + -- Decode Inputs + dec_cpl_rf1_pred_taken_cnt => dec_cpl_rf1_pred_taken_cnt, + dec_cpl_rf1_instr => dec_cpl_rf1_instr, + dec_cpl_ex2_error => dec_cpl_ex2_error, + dec_cpl_ex2_match => dec_cpl_ex2_match, + dec_cpl_ex2_is_ucode => dec_cpl_ex2_is_ucode, + dec_cpl_ex3_is_any_store => dec_cpl_ex3_is_any_store, + dec_cpl_ex2_is_any_store_dac => dec_cpl_ex2_is_any_store_dac, + dec_cpl_ex2_is_any_load_dac => dec_cpl_ex2_is_any_load_dac, + dec_cpl_ex3_instr_priv => dec_cpl_ex3_instr_priv, + dec_cpl_ex1_epid_instr => dec_ex1_epid_instr, + dec_cpl_ex2_illegal_op => dec_cpl_ex2_illegal_op, + dec_cpl_ex3_mult_coll => dec_cpl_ex3_mult_coll, + dec_cpl_ex3_tlb_illeg => dec_cpl_ex3_tlb_illeg, + dec_cpl_ex3_axu_instr_type => dec_cpl_ex3_axu_instr_type, + dec_cpl_ex3_mc_dep_chk_val => dec_cpl_ex3_mc_dep_chk_val, + dec_cpl_rf1_ucode_val => dec_cpl_rf1_ucode_val, + dec_cpl_ex3_mtdp_nr => dec_cpl_ex3_mtdp_nr, + lsu_xu_ex4_mtdp_cr_status => lsu_xu_ex4_mtdp_cr_status, + dec_cpl_ex3_instr_hypv => dec_cpl_ex3_instr_hypv, + fxa_cpl_ex2_div_coll => fxa_cpl_ex2_div_coll, + -- Async Interrupt Req Interface + spr_cpl_ext_interrupt => spr_cpl_ext_interrupt, + spr_cpl_dec_interrupt => spr_cpl_dec_interrupt, + spr_cpl_udec_interrupt => spr_cpl_udec_interrupt, + spr_cpl_perf_interrupt => spr_cpl_perf_interrupt, + spr_cpl_fit_interrupt => spr_cpl_fit_interrupt, + spr_cpl_crit_interrupt => spr_cpl_crit_interrupt, + spr_cpl_wdog_interrupt => spr_cpl_wdog_interrupt, + spr_cpl_dbell_interrupt => spr_cpl_dbell_interrupt, + spr_cpl_cdbell_interrupt => spr_cpl_cdbell_interrupt, + spr_cpl_gdbell_interrupt => spr_cpl_gdbell_interrupt, + spr_cpl_gcdbell_interrupt => spr_cpl_gcdbell_interrupt, + spr_cpl_gmcdbell_interrupt => spr_cpl_gmcdbell_interrupt, + cpl_spr_ex5_dbell_taken => cpl_spr_ex5_dbell_taken, + cpl_spr_ex5_cdbell_taken => cpl_spr_ex5_cdbell_taken, + cpl_spr_ex5_gdbell_taken => cpl_spr_ex5_gdbell_taken, + cpl_spr_ex5_gcdbell_taken => cpl_spr_ex5_gcdbell_taken, + cpl_spr_ex5_gmcdbell_taken => cpl_spr_ex5_gmcdbell_taken, + -- Debug Compares + dec_cpl_rf1_ifar => dec_cpl_rf1_ifar, + fxu_cpl_ex3_dac1r_cmpr_async => fxu_cpl_ex3_dac1r_cmpr_async, + fxu_cpl_ex3_dac2r_cmpr_async => fxu_cpl_ex3_dac2r_cmpr_async, + fxu_cpl_ex3_dac1r_cmpr => fxu_cpl_ex3_dac1r_cmpr, + fxu_cpl_ex3_dac2r_cmpr => fxu_cpl_ex3_dac2r_cmpr, + fxu_cpl_ex3_dac3r_cmpr => fxu_cpl_ex3_dac3r_cmpr, + fxu_cpl_ex3_dac4r_cmpr => fxu_cpl_ex3_dac4r_cmpr, + fxu_cpl_ex3_dac1w_cmpr => fxu_cpl_ex3_dac1w_cmpr, + fxu_cpl_ex3_dac2w_cmpr => fxu_cpl_ex3_dac2w_cmpr, + fxu_cpl_ex3_dac3w_cmpr => fxu_cpl_ex3_dac3w_cmpr, + fxu_cpl_ex3_dac4w_cmpr => fxu_cpl_ex3_dac4w_cmpr, + -- Interrupt Interface + cpl_spr_ex5_act => cpl_spr_ex5_act, + cpl_spr_ex5_int => cpl_spr_ex5_int, + cpl_spr_ex5_gint => cpl_spr_ex5_gint, + cpl_spr_ex5_cint => cpl_spr_ex5_cint, + cpl_spr_ex5_mcint => cpl_spr_ex5_mcint, + cpl_spr_ex5_nia => cpl_spr_ex5_nia, + cpl_spr_ex5_esr => cpl_spr_ex5_esr, + cpl_spr_ex5_mcsr => cpl_spr_ex5_mcsr, + cpl_spr_ex5_dbsr => cpl_spr_ex5_dbsr, + cpl_spr_ex5_dear_save => cpl_spr_ex5_dear_save, + cpl_spr_ex5_dear_update_saved => cpl_spr_ex5_dear_update_saved, + cpl_spr_ex5_dear_update => cpl_spr_ex5_dear_update, + cpl_spr_ex5_dbsr_update => cpl_spr_ex5_dbsr_update, + cpl_spr_ex5_esr_update => cpl_spr_ex5_esr_update, + cpl_spr_ex5_srr0_dec => cpl_spr_ex5_srr0_dec, + cpl_spr_ex5_force_gsrr => cpl_spr_ex5_force_gsrr, + cpl_spr_ex5_dbsr_ide => cpl_spr_ex5_dbsr_ide, + spr_cpl_dbsr_ide => spr_cpl_dbsr_ide, + -- ALU Inputs + alu_cpl_ex1_eff_addr => xu_ex1_eff_addr(62 to 63), + -- Machine Check Interrupts + mm_xu_local_snoop_reject => mm_xu_local_snoop_reject, + mm_xu_lru_par_err => mm_xu_lru_par_err, + mm_xu_tlb_par_err => mm_xu_tlb_par_err, + mm_xu_tlb_multihit_err => mm_xu_tlb_multihit_err, + lsu_xu_ex3_derat_par_err => lsu_xu_ex3_derat_par_err, + lsu_xu_ex4_derat_par_err => lsu_xu_ex4_derat_par_err, + lsu_xu_ex3_derat_multihit_err => lsu_xu_ex3_derat_multihit_err, + lsu_xu_ex3_l2_uc_ecc_err => lsu_xu_ex3_l2_uc_ecc_err, + lsu_xu_ex3_ddir_par_err => lsu_xu_ex3_ddir_par_err, + lsu_xu_ex4_n_lsu_ddmh_flush => lsu_xu_ex4_n_lsu_ddmh_flush, + lsu_xu_ex6_datc_par_err => lsu_xu_ex6_datc_par_err, + spr_cpl_external_mchk => spr_cpl_external_mchk, + -- ATTN complete + xu_pc_err_attention_instr => xu_pc_err_attention_instr, + xu_pc_err_nia_miscmpr => xu_pc_err_nia_miscmpr, + xu_pc_err_debug_event => xu_pc_err_debug_event, + -- Data Storage + derat_xu_ex3_dsi => derat_xu_ex3_dsi, + lsu_xu_ex3_dsi => lsu_xu_ex3_dsi, + spr_cpl_ex3_ct_le => spr_cpl_ex3_ct_le, + spr_cpl_ex3_ct_be => spr_cpl_ex3_ct_be, + -- Alignment + lsu_xu_ex3_align => lsu_xu_ex3_align, + -- Program + spr_cpl_ex3_spr_illeg => spr_cpl_ex3_spr_illeg, + spr_cpl_ex3_spr_priv => spr_cpl_ex3_spr_priv, + alu_cpl_ex3_trap_val => alu_cpl_ex3_trap_val, + -- Hypv Privledge + spr_cpl_ex3_spr_hypv => spr_cpl_ex3_spr_hypv, + -- Data TLB Miss + derat_xu_ex3_miss => derat_xu_ex3_miss, + mm_xu_illeg_instr => mm_xu_illeg_instr, + -- Instr TLB Miss + mm_xu_tlb_miss => mm_xu_tlb_miss, + -- RAM + pc_xu_ram_mode => pc_xu_ram_mode, + pc_xu_ram_thread => pc_xu_ram_thread, + pc_xu_ram_execute => pc_xu_ram_execute, + pc_xu_ram_flush_thread => pc_xu_ram_flush_thread, + xu_iu_ram_issue => xu_iu_ram_issue, + xu_pc_ram_interrupt => xu_pc_ram_interrupt, + xu_pc_ram_done => xu_pc_ram_done, + pc_xu_init_reset => pc_xu_init_reset, + -- Run State + cpl_spr_stop => cpl_spr_stop, + cpl_spr_ex5_instr_cpl => cpl_spr_ex5_instr_cpl, + xu_pc_stop_dbg_event => xu_pc_stop_dbg_event, + spr_cpl_quiesce => spr_cpl_quiesce, + cpl_spr_quiesce => cpl_spr_quiesce, + spr_cpl_ex2_run_ctl_flush => spr_cpl_ex2_run_ctl_flush, + -- MMU Flushes + mm_xu_pt_fault => mm_xu_pt_fault, + mm_xu_tlb_inelig => mm_xu_tlb_inelig, + mm_xu_lrat_miss => mm_xu_lrat_miss, + mm_xu_hv_priv => mm_xu_hv_priv, + mm_xu_esr_pt => mm_xu_esr_pt, + mm_xu_esr_data => mm_xu_esr_data, + mm_xu_esr_epid => mm_xu_esr_epid, + mm_xu_esr_st => mm_xu_esr_st, + mm_xu_hold_req => mm_xu_hold_req, + mm_xu_hold_done => mm_xu_hold_done, + xu_mm_hold_ack => xu_mm_hold_ack, + mm_xu_eratmiss_done => mm_xu_eratmiss_done, + mm_xu_ex3_flush_req => mm_xu_ex3_flush_req, + -- LSU Flushes + lsu_xu_l2_ecc_err_flush => lsu_xu_l2_ecc_err_flush, + lsu_xu_datc_perr_recovery => lsu_xu_datc_perr_recovery, + lsu_xu_ex3_dep_flush => lsu_xu_ex3_dep_flush, + lsu_xu_ex3_n_flush_req => lsu_xu_ex3_n_flush_req, + lsu_xu_ex3_ldq_hit_flush => lsu_xu_ex3_ldq_hit_flush, + lsu_xu_ex4_ldq_full_flush => lsu_xu_ex4_ldq_full_flush, + derat_xu_ex3_n_flush_req => derat_xu_ex3_n_flush_req, + lsu_xu_ex3_inval_align_2ucode => lsu_xu_ex3_inval_align_2ucode, + lsu_xu_ex3_attr => lsu_xu_ex3_attr, + lsu_xu_ex3_derat_vf => lsu_xu_ex3_derat_vf, + -- AXU Flushes + fu_xu_ex3_n_flush => fu_xu_ex3_n_flush, + fu_xu_ex3_np1_flush => fu_xu_ex3_np1_flush, + fu_xu_ex3_flush2ucode => fu_xu_ex3_flush2ucode, + fu_xu_ex2_async_block => fu_xu_ex2_async_block, + -- IU Flushes + xu_iu_ex5_br_taken => xu_iu_ex5_br_taken, + xu_iu_ex5_ifar => xu_iu_ex5_ifar, + xu_iu_flush => xu_iu_flush, + xu_iu_iu0_flush_ifar => xu_iu_iu0_flush_ifar, + xu_iu_uc_flush_ifar => xu_iu_uc_flush_ifar, + xu_iu_flush_2ucode => xu_iu_flush_2ucode, + xu_iu_flush_2ucode_type => xu_iu_flush_2ucode_type, + xu_iu_ucode_restart => xu_iu_ucode_restart, + xu_iu_ex5_ppc_cpl => xu_iu_ex5_ppc_cpl, + -- Flushes + xu_n_is2_flush => xu_n_is2_flush, + xu_n_rf0_flush => xu_n_rf0_flush, + xu_n_rf1_flush => xu_n_rf1_flush, + xu_n_ex1_flush => xu_n_ex1_flush, + xu_n_ex2_flush => xu_n_ex2_flush, + xu_n_ex3_flush => xu_n_ex3_flush, + xu_n_ex4_flush => xu_n_ex4_flush, + xu_n_ex5_flush => xu_n_ex5_flush, + xu_s_rf1_flush => xu_s_rf1_flush, + xu_s_ex1_flush => xu_s_ex1_flush, + xu_s_ex2_flush => xu_s_ex2_flush, + xu_s_ex3_flush => xu_s_ex3_flush, + xu_s_ex4_flush => xu_s_ex4_flush, + xu_s_ex5_flush => xu_s_ex5_flush, + xu_w_rf1_flush => xu_w_rf1_flush, + xu_w_ex1_flush => xu_w_ex1_flush, + xu_w_ex2_flush => xu_w_ex2_flush, + xu_w_ex3_flush => xu_w_ex3_flush, + xu_w_ex4_flush => xu_w_ex4_flush, + xu_w_ex5_flush => xu_w_ex5_flush, + xu_rf0_flush => xu_rf0_flush_int, + xu_rf1_flush => xu_rf1_flush_int, + xu_ex1_flush => xu_ex1_flush_int, + xu_ex2_flush => xu_ex2_flush_int, + xu_ex3_flush => xu_ex3_flush_int, + xu_ex4_flush => xu_ex4_flush_int, + xu_ex5_flush => xu_ex5_flush_int, + xu_mm_ex4_flush => xu_mm_ex4_flush, + xu_mm_ex5_flush => xu_mm_ex5_flush, + xu_mm_ierat_flush => xu_mm_ierat_flush, + xu_mm_ierat_miss => xu_mm_ierat_miss, + xu_mm_ex5_perf_itlb => xu_mm_ex5_perf_itlb, + xu_mm_ex5_perf_dtlb => xu_mm_ex5_perf_dtlb, + xu_lsu_ex4_flush_local => xu_lsu_ex4_flush_local, + xu_lsu_dci => xu_lsu_dci, + xu_lsu_ici => xu_lsu_ici, + xu_lsu_ex4_val => xu_lsu_ex4_val, + -- Parity + spr_cpl_ex3_sprg_ue => spr_cpl_ex3_sprg_ue, + spr_cpl_ex3_sprg_ce => spr_cpl_ex3_sprg_ce, + iu_xu_ierat_ex2_flush_req => iu_xu_ierat_ex2_flush_req, + iu_xu_ierat_ex3_par_err => iu_xu_ierat_ex3_par_err, + iu_xu_ierat_ex4_par_err => iu_xu_ierat_ex4_par_err, + -- Regfile Parity + fu_xu_ex3_regfile_err_det => fu_xu_ex3_regfile_err_det, + xu_fu_regfile_seq_beg => xu_fu_regfile_seq_beg, + fu_xu_regfile_seq_end => fu_xu_regfile_seq_end, + gpr_cpl_ex3_regfile_err_det => gpr_cpl_ex3_regfile_err_det, + cpl_gpr_regfile_seq_beg => cpl_gpr_regfile_seq_beg, + gpr_cpl_regfile_seq_end => gpr_cpl_regfile_seq_end, + xu_pc_err_mcsr_summary => xu_pc_err_mcsr_summary, + xu_pc_err_ditc_overrun => xu_pc_err_ditc_overrun, + xu_pc_err_local_snoop_reject => xu_pc_err_local_snoop_reject, + xu_pc_err_tlb_lru_parity => xu_pc_err_tlb_lru_parity, + xu_pc_err_ext_mchk => xu_pc_err_ext_mchk, + xu_pc_err_ierat_multihit => xu_pc_err_ierat_multihit, + xu_pc_err_derat_multihit => xu_pc_err_derat_multihit, + xu_pc_err_tlb_multihit => xu_pc_err_tlb_multihit, + xu_pc_err_ierat_parity => xu_pc_err_ierat_parity, + xu_pc_err_derat_parity => xu_pc_err_derat_parity, + xu_pc_err_mchk_disabled => xu_pc_err_mchk_disabled, + xu_pc_err_tlb_parity => xu_pc_err_tlb_parity, + xu_pc_err_sprg_ue => xu_pc_err_sprg_ue, + -- Perf + cpl_perf_tx_events => cpl_perf_tx_events, + spr_cpl_async_int => spr_cpl_async_int, + -- Barrier + xu_lsu_ex5_set_barr => xu_lsu_ex5_set_barr, + cpl_fxa_ex5_set_barr => cpl_fxa_ex5_set_barr, + cpl_iu_set_barr_tid => cpl_iu_set_barr_tid, + -- Read Data + cpl_byp_ex3_spr_rt => cpl_byp_ex3_spr_rt, + -- Write Data + mux_cpl_ex4_rt => mux_cpl_ex4_rt, + -- SPR Bits + spr_bit_act => spr_bit_act, + spr_cpl_iac1_en => spr_cpl_iac1_en, + spr_cpl_iac2_en => spr_cpl_iac2_en, + spr_cpl_iac3_en => spr_cpl_iac3_en, + spr_cpl_iac4_en => spr_cpl_iac4_en, + spr_dbcr1_iac12m => spr_dbcr1_iac12m, + spr_dbcr1_iac34m => spr_dbcr1_iac34m, + spr_cpl_fp_precise => spr_cpl_fp_precise, + spr_xucr0_mddp => spr_xucr0_mddp, + spr_xucr0_mdcp => spr_xucr0_mdcp, + spr_msr_de => spr_msr_de, + spr_msr_spv => spr_msr_spv, + spr_msr_fp => spr_msr_fp, + spr_msr_pr => spr_msr_pr, + spr_msr_gs => spr_msr_gs, + spr_msr_me => spr_msr_me, + spr_msr_cm => spr_msr_cm, + spr_msr_ucle => spr_msr_ucle, + spr_msrp_uclep => spr_msrp_uclep, + spr_ccr2_notlb => spr_ccr2_notlb, + spr_ccr2_ucode_dis => spr_ccr2_ucode_dis, + spr_ccr2_ap => spr_ccr2_ap, + spr_dbcr0_idm => spr_dbcr0_idm, + cpl_spr_dbcr0_edm => cpl_spr_dbcr0_edm, + spr_dbcr0_icmp => spr_dbcr0_icmp, + spr_dbcr0_brt => spr_dbcr0_brt, + spr_dbcr0_trap => spr_dbcr0_trap, + spr_dbcr0_ret => spr_dbcr0_ret, + spr_dbcr0_irpt => spr_dbcr0_irpt, + spr_dbcr3_ivc => spr_dbcr3_ivc_int, + spr_epcr_dsigs => spr_epcr_dsigs, + spr_epcr_isigs => spr_epcr_isigs, + spr_epcr_extgs => spr_epcr_extgs, + spr_epcr_dtlbgs => spr_epcr_dtlbgs, + spr_epcr_itlbgs => spr_epcr_itlbgs, + spr_xucr4_div_barr_thres => spr_xucr4_div_barr_thres, + spr_xucr4_mmu_mchk => spr_xucr4_mmu_mchk, + spr_ccr0_we => spr_ccr0_we, + spr_epcr_duvd => spr_epcr_duvd, + cpl_msr_gs => cpl_msr_gs, + cpl_msr_pr => cpl_msr_pr, + cpl_msr_fp => cpl_msr_fp, + cpl_msr_spv => cpl_msr_spv, + cpl_ccr2_ap => cpl_ccr2_ap, + spr_xucr0_clkg_ctl => spr_xucr0_clkg_ctl(2 to 2), + -- Slow SPR Bus + mux_cpl_slowspr_flush => mux_cpl_slowspr_flush, + mux_cpl_slowspr_done => mux_cpl_slowspr_done, + dec_cpl_ex1_is_slowspr_wr => dec_cpl_ex1_is_slowspr_wr, + dec_cpl_ex3_ddmh_en => dec_cpl_ex3_ddmh_en, + dec_cpl_ex3_back_inv => dec_cpl_ex3_back_inv, + -- Debug + pc_xu_event_bus_enable => pc_xu_event_bus_enable, + pc_xu_trace_bus_enable => pc_xu_trace_bus_enable, + pc_xu_instr_trace_mode => pc_xu_instr_trace_mode, + dec_cpl_rf1_instr_trace_val => dec_cpl_rf1_instr_trace_val, + dec_cpl_rf1_instr_trace_type => dec_cpl_rf1_instr_trace_type, + dec_cpl_ex3_instr_trace_val => dec_cpl_ex3_instr_trace_val, + cpl_dec_in_ucode => cpl_dec_in_ucode, + cpl_debug_mux_ctrls => cpl_debug_mux_ctrls, + cpl_debug_data_in => cpl_debug_data_in, + cpl_debug_data_out => cpl_debug_data_out, + cpl_trigger_data_in => cpl_trigger_data_in, + cpl_trigger_data_out => cpl_trigger_data_out, + fxa_cpl_debug => fxa_cpl_debug, + -- Power + vdd => vdd, + gnd => gnd + ); + +xu_ex1_eff_addr_int <= xu_ex1_eff_addr; +xu_rf0_flush <= xu_rf0_flush_int; +xu_rf1_flush <= xu_rf1_flush_int; +xu_ex1_flush <= xu_ex1_flush_int; +xu_ex2_flush <= xu_ex2_flush_int; +xu_ex3_flush <= xu_ex3_flush_int; +xu_ex4_flush <= xu_ex4_flush_int; +dec_spr_ex1_epid_instr <= dec_ex1_epid_instr; + +end xuq_cpl_fxub; diff --git a/rel/src/vhdl/work/xuq_cpl_pri.vhdl b/rel/src/vhdl/work/xuq_cpl_pri.vhdl new file mode 100644 index 0000000..9671cdc --- /dev/null +++ b/rel/src/vhdl/work/xuq_cpl_pri.vhdl @@ -0,0 +1,116 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: Prioritizer +-- +library ieee,ibm,support; +use ieee.std_logic_1164.all; +use ibm.std_ulogic_function_support.reverse; + +entity xuq_cpl_pri is +generic( + size : integer range 3 to 32 := 32; -- Size of "cond" + rev : integer range 0 to 1 := 0; -- 0 = 0 is highest, 1 = 0 is lowest + cmp_zero : integer range 0 to 1 := 0); -- 1 = include comparing cond to zero in pri vector +port( + cond : in std_ulogic_vector(0 to size-1); + pri : out std_ulogic_vector(0 to size-1+cmp_zero); + or_cond : out std_ulogic +); + +-- synopsys translate_off +-- synopsys translate_on + +end xuq_cpl_pri; +architecture xuq_cpl_pri of xuq_cpl_pri is + +constant s : integer := size-1; +signal l0 : std_ulogic_vector(0 to s); +signal or_l1,or_l2,or_l3,or_l4,or_l5: std_ulogic_vector(0 to s); + + +begin + +rev_gen0 : if rev = 0 generate + l0(0 to s) <= cond(0 to s); +end generate; +rev_gen1 : if rev = 1 generate + l0(0 to s) <= reverse(cond(0 to s)); +end generate; + +-- Odd Numbered Levels are inverted + +l1_not: or_l1(0) <= not l0(0); +l1_nor: or_l1(1 to s) <= l0(0 to s-1) nor l0(1 to s); + + +or_l2_gen0 : if s >= 2 generate + or_l2(0 to 1) <= not or_l1(0 to 1); + or_l2(2 to s) <= or_l1(2 to s) nand or_l1(0 to s-2); +end generate; +or_l2_gen1 : if s < 2 generate + or_l2 <= not or_l1; +end generate; + +or_l3_gen0 : if s >= 4 generate + or_l3(0 to 3) <= not or_l2(0 to 3); + or_l3(4 to s) <= or_l2(4 to s) nor or_l2(0 to s-4); +end generate; +or_l3_gen1 : if s < 4 generate + or_l3 <= not or_l2; +end generate; + +or_l4_gen0 : if s >= 8 generate + or_l4(0 to 7) <= not or_l3(0 to 7); + or_l4(8 to s) <= or_l3(8 to s) nand or_l3(0 to s-8); +end generate; +or_l4_gen1 : if s < 8 generate + or_l4 <= not or_l3; +end generate; + +or_l5_gen0 : if s >= 16 generate + or_l5(0 to 15) <= not or_l4(0 to 15); + or_l5(16 to s) <= or_l4(16 to s) nor or_l4(0 to s-16); +end generate; +or_l5_gen1 : if s < 16 generate + or_l5 <= not or_l4; +end generate; + + +pri(0) <= cond(0); +pri(1 to s) <= cond(1 to s) and or_l5(0 to s-1); + +cmp_zero_gen : if cmp_zero = 1 generate +pri(s+1) <= or_l5(s); +end generate; + +or_cond <= not or_l5(s); + + + +end architecture xuq_cpl_pri; diff --git a/rel/src/vhdl/work/xuq_cpl_spr.vhdl b/rel/src/vhdl/work/xuq_cpl_spr.vhdl new file mode 100644 index 0000000..86d0c08 --- /dev/null +++ b/rel/src/vhdl/work/xuq_cpl_spr.vhdl @@ -0,0 +1,267 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XU SPR - Wrapper +-- +library ieee,ibm,support,work,tri; +use ieee.std_logic_1164.all; +use support.power_logic_pkg.all; +use ibm.std_ulogic_function_support.all; +use tri.tri_latches_pkg.all; + +entity xuq_cpl_spr is +generic( + hvmode : integer := 1; + a2mode : integer := 1; + expand_type : integer := 2; + threads : integer := 4; + regsize : integer := 64; + eff_ifar : integer := 62); +port( + nclk : in clk_logic; + + d_mode_dc : in std_ulogic; + delay_lclkr_dc : in std_ulogic; + mpw1_dc_b : in std_ulogic; + mpw2_dc_b : in std_ulogic; + + dcfg_sl_force : in std_ulogic; + dcfg_sl_thold_0_b : in std_ulogic; + func_sl_force : in std_ulogic; + func_sl_thold_0_b : in std_ulogic; + func_nsl_force : in std_ulogic; + func_nsl_thold_0_b : in std_ulogic; + sg_0 : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + dcfg_scan_in : in std_ulogic; + dcfg_scan_out : out std_ulogic; + + -- Decode + spr_bit_act : in std_ulogic; + exx_act : in std_ulogic_vector(1 to 4); + ex1_instr : in std_ulogic_vector(11 to 20); + ex2_tid : in std_ulogic_vector(0 to threads-1); + ex1_is_mfspr : in std_ulogic; + ex1_is_mtspr : in std_ulogic; + ex4_lr_update : in std_ulogic; + ex4_ctr_dec_update : in std_ulogic; + + -- IFAR + ex2_ifar : in std_ulogic_vector(0 to eff_ifar*threads-1); + + -- Write Interface + ex5_val : in std_ulogic_vector(0 to threads-1); + ex5_spr_wd : in std_ulogic_vector(64-regsize to 63); + ex5_cia_p1 : in std_ulogic_vector(62-eff_ifar to 61); + + ex2_mtiar : out std_ulogic; + + -- Read Data + cpl_byp_ex3_spr_rt : out std_ulogic_vector(64-regsize to 63); + + + -- IAC Compare + ex3_iac1_cmpr : out std_ulogic_vector(0 to threads-1); + ex3_iac2_cmpr : out std_ulogic_vector(0 to threads-1); + ex3_iac3_cmpr : out std_ulogic_vector(0 to threads-1); + ex3_iac4_cmpr : out std_ulogic_vector(0 to threads-1); + + -- SPRs + spr_cpl_iac1_en : in std_ulogic_vector(0 to threads-1); + spr_cpl_iac2_en : in std_ulogic_vector(0 to threads-1); + spr_cpl_iac3_en : in std_ulogic_vector(0 to threads-1); + spr_cpl_iac4_en : in std_ulogic_vector(0 to threads-1); + spr_dbcr1_iac12m : in std_ulogic_vector(0 to threads-1); + spr_dbcr1_iac34m : in std_ulogic_vector(0 to threads-1); + spr_iar : in std_ulogic_vector(0 to eff_ifar*threads-1); + spr_msr_cm : in std_ulogic_vector(0 to threads-1); + spr_givpr : out std_ulogic_vector(0 to eff_ifar-10-1); + spr_ivpr : out std_ulogic_vector(0 to eff_ifar-10-1); + spr_xucr3_hold1_dly : out std_ulogic_vector(0 to 3); + spr_xucr3_cm_hold_dly : out std_ulogic_vector(0 to 3); + spr_xucr3_stop_dly : out std_ulogic_vector(0 to 3); + spr_xucr3_hold0_dly : out std_ulogic_vector(0 to 3); + spr_xucr3_csi_dly : out std_ulogic_vector(0 to 3); + spr_xucr3_int_dly : out std_ulogic_vector(0 to 3); + spr_xucr3_asyncblk_dly : out std_ulogic_vector(0 to 3); + spr_xucr3_flush_dly : out std_ulogic_vector(0 to 3); + spr_xucr4_mmu_mchk : out std_ulogic; + spr_xucr4_mddmh : out std_ulogic; + spr_xucr4_div_barr_thres : out std_ulogic_vector(0 to 7); + spr_xucr4_div_bar_dis : out std_ulogic; + spr_xucr4_lsu_bar_dis : out std_ulogic; + spr_xucr4_barr_dly : out std_ulogic_vector(0 to 3); + spr_ctr : out std_ulogic_vector(0 to (regsize)*threads-1); + spr_lr : out std_ulogic_vector(0 to (regsize)*threads-1); + + -- Power + vdd : inout power_logic; + gnd : inout power_logic +); + +-- synopsys translate_off + +-- synopsys translate_on +end xuq_cpl_spr; +architecture xuq_cpl_spr of xuq_cpl_spr is + + +signal siv : std_ulogic_vector(0 to threads); +signal sov : std_ulogic_vector(0 to threads); +signal cspr_tspr_ex5_is_mtspr : std_ulogic; +signal cspr_tspr_ex5_instr : std_ulogic_vector(11 to 20); +signal cspr_tspr_ex2_instr : std_ulogic_vector(11 to 20); +signal tspr_cspr_ex2_tspr_rt : std_ulogic_vector(0 to regsize*threads-1); + +begin + +xu_cpl_spr_cspr : entity work.xuq_cpl_spr_cspr(xuq_cpl_spr_cspr) +generic map( + hvmode => hvmode, + a2mode => a2mode, + expand_type => expand_type, + threads => threads, + regsize => regsize, + eff_ifar => eff_ifar) +port map( + nclk => nclk, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc, + mpw1_dc_b => mpw1_dc_b, + mpw2_dc_b => mpw2_dc_b, + dcfg_sl_force => dcfg_sl_force, + dcfg_sl_thold_0_b => dcfg_sl_thold_0_b, + func_sl_force => func_sl_force, + func_sl_thold_0_b => func_sl_thold_0_b, + func_nsl_force => func_nsl_force, + func_nsl_thold_0_b => func_nsl_thold_0_b, + sg_0 => sg_0, + scan_in => siv(threads), + scan_out => sov(threads), + dcfg_scan_in => dcfg_scan_in, + dcfg_scan_out => dcfg_scan_out, + -- Decode + spr_bit_act => spr_bit_act, + exx_act => exx_act, + ex1_instr => ex1_instr, + ex2_tid => ex2_tid, + ex1_is_mfspr => ex1_is_mfspr, + ex1_is_mtspr => ex1_is_mtspr, + -- IFAR + ex2_ifar => ex2_ifar, + -- Write Interface + ex5_valid => ex5_val, + ex5_spr_wd => ex5_spr_wd, + ex2_mtiar => ex2_mtiar, + -- SPRT Interface + cspr_tspr_ex5_is_mtspr => cspr_tspr_ex5_is_mtspr, + cspr_tspr_ex5_instr => cspr_tspr_ex5_instr, + cspr_tspr_ex2_instr => cspr_tspr_ex2_instr, + -- Read Data + tspr_cspr_ex2_tspr_rt => tspr_cspr_ex2_tspr_rt, + cpl_byp_ex3_spr_rt => cpl_byp_ex3_spr_rt, + -- IAC Compare + ex3_iac1_cmpr => ex3_iac1_cmpr, + ex3_iac2_cmpr => ex3_iac2_cmpr, + ex3_iac3_cmpr => ex3_iac3_cmpr, + ex3_iac4_cmpr => ex3_iac4_cmpr, + -- SPRs + spr_cpl_iac1_en => spr_cpl_iac1_en, + spr_cpl_iac2_en => spr_cpl_iac2_en, + spr_cpl_iac3_en => spr_cpl_iac3_en, + spr_cpl_iac4_en => spr_cpl_iac4_en, + spr_dbcr1_iac12m => spr_dbcr1_iac12m, + spr_dbcr1_iac34m => spr_dbcr1_iac34m, + spr_msr_cm => spr_msr_cm, + spr_givpr => spr_givpr, + spr_ivpr => spr_ivpr, + spr_xucr3_hold1_dly => spr_xucr3_hold1_dly, + spr_xucr3_cm_hold_dly => spr_xucr3_cm_hold_dly, + spr_xucr3_stop_dly => spr_xucr3_stop_dly, + spr_xucr3_hold0_dly => spr_xucr3_hold0_dly, + spr_xucr3_csi_dly => spr_xucr3_csi_dly, + spr_xucr3_int_dly => spr_xucr3_int_dly, + spr_xucr3_asyncblk_dly => spr_xucr3_asyncblk_dly, + spr_xucr3_flush_dly => spr_xucr3_flush_dly, + spr_xucr4_mmu_mchk => spr_xucr4_mmu_mchk, + spr_xucr4_mddmh => spr_xucr4_mddmh, + spr_xucr4_div_barr_thres => spr_xucr4_div_barr_thres, + spr_xucr4_div_bar_dis => spr_xucr4_div_bar_dis, + spr_xucr4_lsu_bar_dis => spr_xucr4_lsu_bar_dis, + spr_xucr4_barr_dly => spr_xucr4_barr_dly, + -- Power + vdd => vdd, + gnd => gnd +); + +thread : for t in 0 to threads-1 generate +xu_cpl_spr_tspr : entity work.xuq_cpl_spr_tspr(xuq_cpl_spr_tspr) +generic map( + hvmode => hvmode, + a2mode => a2mode, + expand_type => expand_type, + regsize => regsize, + eff_ifar => eff_ifar) +port map( + nclk => nclk, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc, + mpw1_dc_b => mpw1_dc_b, + mpw2_dc_b => mpw2_dc_b, + func_sl_force => func_sl_force, + func_sl_thold_0_b => func_sl_thold_0_b, + sg_0 => sg_0, + scan_in => siv(t), + scan_out => sov(t), + cspr_tspr_ex2_instr => cspr_tspr_ex2_instr, + tspr_cspr_ex2_tspr_rt => tspr_cspr_ex2_tspr_rt(regsize*t to regsize*(t+1)-1), + -- Write Interface + ex5_val => ex5_val(t), + cspr_tspr_ex5_is_mtspr => cspr_tspr_ex5_is_mtspr, + cspr_tspr_ex5_instr => cspr_tspr_ex5_instr, + ex5_spr_wd => ex5_spr_wd, + ex5_cia_p1 => ex5_cia_p1, + -- Decode Signals + ex4_lr_update => ex4_lr_update, + ex4_ctr_dec_update => ex4_ctr_dec_update, + -- SPRs + spr_iar => spr_iar(eff_ifar*t to eff_ifar*(t+1)-1), + spr_ctr => spr_ctr((regsize)*t to (regsize)*(t+1)-1), + spr_lr => spr_lr((regsize)*t to (regsize)*(t+1)-1), + -- Power + vdd => vdd, + gnd => gnd +); +end generate; + +siv(0 to threads) <= sov(1 to threads) & scan_in; +scan_out <= sov(0); + + +end architecture xuq_cpl_spr; diff --git a/rel/src/vhdl/work/xuq_cpl_spr_cspr.vhdl b/rel/src/vhdl/work/xuq_cpl_spr_cspr.vhdl new file mode 100644 index 0000000..1468e98 --- /dev/null +++ b/rel/src/vhdl/work/xuq_cpl_spr_cspr.vhdl @@ -0,0 +1,995 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XU SPR - per core registers & array +-- +library ieee,ibm,support,work,tri; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use support.power_logic_pkg.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use tri.tri_latches_pkg.all; +use work.xuq_pkg.all; + +entity xuq_cpl_spr_cspr is +generic( + hvmode : integer := 1; + a2mode : integer := 1; + expand_type : integer := 2; + threads : integer := 4; + regsize : integer := 64; + eff_ifar : integer := 62); +port( + nclk : in clk_logic; + + d_mode_dc : in std_ulogic; + delay_lclkr_dc : in std_ulogic; + mpw1_dc_b : in std_ulogic; + mpw2_dc_b : in std_ulogic; + + dcfg_sl_force : in std_ulogic; + dcfg_sl_thold_0_b : in std_ulogic; + func_sl_force : in std_ulogic; + func_sl_thold_0_b : in std_ulogic; + func_nsl_force : in std_ulogic; + func_nsl_thold_0_b : in std_ulogic; + sg_0 : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + dcfg_scan_in : in std_ulogic; + dcfg_scan_out : out std_ulogic; + + -- Decode + spr_bit_act : in std_ulogic; + exx_act : in std_ulogic_vector(1 to 4); + ex1_instr : in std_ulogic_vector(11 to 20); + ex2_tid : in std_ulogic_vector(0 to threads-1); + ex1_is_mfspr : in std_ulogic; + ex1_is_mtspr : in std_ulogic; + + -- IFAR + ex2_ifar : in std_ulogic_vector(0 to eff_ifar*threads-1); + + -- Write Interface + ex5_valid : in std_ulogic_vector(0 to threads-1); + ex5_spr_wd : in std_ulogic_vector(64-regsize to 63); + + ex2_mtiar : out std_ulogic; + + -- SPRT Interface + cspr_tspr_ex5_is_mtspr : out std_ulogic; + cspr_tspr_ex5_instr : out std_ulogic_vector(11 to 20); + cspr_tspr_ex2_instr : out std_ulogic_vector(11 to 20); + + -- Read Data + tspr_cspr_ex2_tspr_rt : in std_ulogic_vector(0 to regsize*threads-1); + cpl_byp_ex3_spr_rt : out std_ulogic_vector(64-regsize to 63); + + + -- IAC Compare + ex3_iac1_cmpr : out std_ulogic_vector(0 to threads-1); + ex3_iac2_cmpr : out std_ulogic_vector(0 to threads-1); + ex3_iac3_cmpr : out std_ulogic_vector(0 to threads-1); + ex3_iac4_cmpr : out std_ulogic_vector(0 to threads-1); + + -- SPRs + spr_cpl_iac1_en : in std_ulogic_vector(0 to threads-1); + spr_cpl_iac2_en : in std_ulogic_vector(0 to threads-1); + spr_cpl_iac3_en : in std_ulogic_vector(0 to threads-1); + spr_cpl_iac4_en : in std_ulogic_vector(0 to threads-1); + spr_dbcr1_iac12m : in std_ulogic_vector(0 to threads-1); + spr_dbcr1_iac34m : in std_ulogic_vector(0 to threads-1); + spr_msr_cm : in std_ulogic_vector(0 to threads-1); + spr_givpr : out std_ulogic_vector(0 to eff_ifar-10-1); + spr_ivpr : out std_ulogic_vector(0 to eff_ifar-10-1); + spr_xucr3_hold1_dly : out std_ulogic_vector(0 to 3); + spr_xucr3_cm_hold_dly : out std_ulogic_vector(0 to 3); + spr_xucr3_stop_dly : out std_ulogic_vector(0 to 3); + spr_xucr3_hold0_dly : out std_ulogic_vector(0 to 3); + spr_xucr3_csi_dly : out std_ulogic_vector(0 to 3); + spr_xucr3_int_dly : out std_ulogic_vector(0 to 3); + spr_xucr3_asyncblk_dly : out std_ulogic_vector(0 to 3); + spr_xucr3_flush_dly : out std_ulogic_vector(0 to 3); + spr_xucr4_mmu_mchk : out std_ulogic; + spr_xucr4_mddmh : out std_ulogic; + spr_xucr4_div_barr_thres : out std_ulogic_vector(0 to 7); + spr_xucr4_div_bar_dis : out std_ulogic; + spr_xucr4_lsu_bar_dis : out std_ulogic; + spr_xucr4_barr_dly : out std_ulogic_vector(0 to 3); + + -- Power + vdd : inout power_logic; + gnd : inout power_logic +); + +-- synopsys translate_off + +-- synopsys translate_on +end xuq_cpl_spr_cspr; +architecture xuq_cpl_spr_cspr of xuq_cpl_spr_cspr is + +constant ui : integer := 62-eff_ifar; +-- Types +subtype DO is std_ulogic_vector(65-regsize to 64); +type IFAR_ARR is array (0 to threads-1) of std_ulogic_vector(62-eff_ifar to 61); +type IACM_ARR is array (0 to threads-1) of std_ulogic_vector(0 to regsize/8-1); +-- SPR Registers +signal givpr_d , givpr_q : std_ulogic_vector(64-(eff_ifar-10) to 63); +signal iac1_d , iac1_q : std_ulogic_vector(64-(eff_ifar) to 63); +signal iac2_d , iac2_q : std_ulogic_vector(64-(eff_ifar) to 63); +signal iac3_d , iac3_q : std_ulogic_vector(64-(eff_ifar) to 63); +signal iac4_d , iac4_q : std_ulogic_vector(64-(eff_ifar) to 63); +signal ivpr_d , ivpr_q : std_ulogic_vector(64-(eff_ifar-10) to 63); +signal xucr3_d , xucr3_q : std_ulogic_vector(32 to 63); +signal xucr4_d , xucr4_q : std_ulogic_vector(48 to 63); +-- FUNC Scanchain +constant givpr_offset : natural := 0; +constant iac1_offset : natural := givpr_offset + givpr_q'length*hvmode; +constant iac2_offset : natural := iac1_offset + iac1_q'length; +constant iac3_offset : natural := iac2_offset + iac2_q'length; +constant iac4_offset : natural := iac3_offset + iac3_q'length*a2mode; +constant ivpr_offset : natural := iac4_offset + iac4_q'length*a2mode; +constant last_reg_offset : natural := ivpr_offset + ivpr_q'length; +-- BCFG Scanchain +constant last_reg_offset_bcfg : natural := 1; +-- CCFG Scanchain +constant last_reg_offset_ccfg : natural := 1; +-- DCFG Scanchain +constant xucr3_offset_dcfg : natural := 0; +constant xucr4_offset_dcfg : natural := xucr3_offset_dcfg + xucr3_q'length; +constant last_reg_offset_dcfg : natural := xucr4_offset_dcfg + xucr4_q'length; +-- Latches +signal ex2_is_mfspr_q : std_ulogic; -- ex1_is_mfspr exx_act(1) +signal ex2_is_mtspr_q : std_ulogic; -- ex1_is_mtspr exx_act(1) +signal ex2_instr_q : std_ulogic_vector(11 to 20); -- ex1_instr exx_act(1) +signal ex3_is_mtspr_q : std_ulogic; -- ex2_is_mtspr_q exx_act(2) +signal ex3_instr_q : std_ulogic_vector(11 to 20); -- ex2_instr_q exx_act(2) +signal ex3_spr_rt_q, ex3_spr_rt_d : std_ulogic_vector(64-regsize to 63); -- exx_act(2) +signal ex3_iac1_cmpr_q, ex3_iac1_cmpr_d: std_ulogic_vector(0 to threads-1); -- input=>ex3_iac1_cmpr_d , act=>tiup , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex3_iac2_cmpr_q, ex3_iac2_cmpr_d: std_ulogic_vector(0 to threads-1); -- input=>ex3_iac2_cmpr_d , act=>tiup , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex3_iac3_cmpr_q, ex3_iac3_cmpr_d: std_ulogic_vector(0 to threads-1); -- input=>ex3_iac3_cmpr_d , act=>tiup , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex3_iac4_cmpr_q, ex3_iac4_cmpr_d: std_ulogic_vector(0 to threads-1); -- input=>ex3_iac4_cmpr_d , act=>tiup , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex4_is_mtspr_q : std_ulogic; -- ex3_is_mtspr_q exx_act(3) +signal ex4_instr_q : std_ulogic_vector(11 to 20); -- ex3_instr_q exx_act(3) +signal ex5_is_mtspr_q : std_ulogic; -- ex4_is_mtspr_q exx_act(4) +signal ex5_instr_q : std_ulogic_vector(11 to 20); -- ex4_instr_q exx_act(4) +signal dbcr1_iac12m_2_q, dbcr1_iac12m_2_d : IACM_ARR; -- input=>dbcr1_iac12m_2_d , act=>spr_bit_act , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 +signal dbcr1_iac34m_2_q, dbcr1_iac34m_2_d : IACM_ARR; -- input=>dbcr1_iac34m_2_d , act=>spr_bit_act , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 +--signal msrovride_enab_q : std_ulogic; -- pc_xu_msrovride_enab +--signal msrovride_gs_q : std_ulogic; -- pc_xu_msrovride_gs +--signal ram_thread_q : std_ulogic_vector(0 to 1); -- pc_xu_ram_thread +signal iac1_en_q : std_ulogic_vector(0 to threads-1); -- input=>spr_cpl_iac1_en +signal iac2_en_q : std_ulogic_vector(0 to threads-1); -- input=>spr_cpl_iac2_en +signal iac3_en_q : std_ulogic_vector(0 to threads-1); -- input=>spr_cpl_iac3_en +signal iac4_en_q : std_ulogic_vector(0 to threads-1); -- input=>spr_cpl_iac4_en +signal dbcr1_iac12m_q : std_ulogic_vector(0 to threads-1); -- input=>spr_dbcr1_iac12m +signal dbcr1_iac34m_q : std_ulogic_vector(0 to threads-1); -- input=>spr_dbcr1_iac34m +-- Scanchains +constant ex2_is_mfspr_offset : integer := last_reg_offset; +constant ex2_is_mtspr_offset : integer := ex2_is_mfspr_offset + 1; +constant ex2_instr_offset : integer := ex2_is_mtspr_offset + 1; +constant ex3_is_mtspr_offset : integer := ex2_instr_offset + ex2_instr_q'length; +constant ex3_instr_offset : integer := ex3_is_mtspr_offset + 1; +constant ex3_spr_rt_offset : integer := ex3_instr_offset + ex3_instr_q'length; +constant ex3_iac1_cmpr_offset : integer := ex3_spr_rt_offset + ex3_spr_rt_q'length; +constant ex3_iac2_cmpr_offset : integer := ex3_iac1_cmpr_offset + ex3_iac1_cmpr_q'length; +constant ex3_iac3_cmpr_offset : integer := ex3_iac2_cmpr_offset + ex3_iac2_cmpr_q'length; +constant ex3_iac4_cmpr_offset : integer := ex3_iac3_cmpr_offset + ex3_iac3_cmpr_q'length; +constant ex4_is_mtspr_offset : integer := ex3_iac4_cmpr_offset + ex3_iac4_cmpr_q'length; +constant ex4_instr_offset : integer := ex4_is_mtspr_offset + 1; +constant ex5_is_mtspr_offset : integer := ex4_instr_offset + ex4_instr_q'length; +constant ex5_instr_offset : integer := ex5_is_mtspr_offset + 1; +constant iac1_en_offset : integer := ex5_instr_offset + ex5_instr_q'length; +constant iac2_en_offset : integer := iac1_en_offset + iac1_en_q'length; +constant iac3_en_offset : integer := iac2_en_offset + iac2_en_q'length; +constant iac4_en_offset : integer := iac3_en_offset + iac3_en_q'length; +constant dbcr1_iac12m_offset : integer := iac4_en_offset + iac4_en_q'length; +constant dbcr1_iac34m_offset : integer := dbcr1_iac12m_offset + dbcr1_iac12m_q'length; +constant scan_right : integer := dbcr1_iac34m_offset + dbcr1_iac34m_q'length; +signal siv : std_ulogic_vector(0 to scan_right-1); +signal sov : std_ulogic_vector(0 to scan_right-1); +constant scan_right_dcfg : integer := last_reg_offset_dcfg; +signal siv_dcfg : std_ulogic_vector(0 to scan_right_dcfg-1); +signal sov_dcfg : std_ulogic_vector(0 to scan_right_dcfg-1); +-- Signals +signal tiup : std_ulogic; +signal tidn : std_ulogic_vector(00 to 63); +signal ex2_iac1_cmprh : std_ulogic_vector(0 to threads-1); +signal ex2_iac2_cmprh : std_ulogic_vector(0 to threads-1); +signal ex2_iac3_cmprh : std_ulogic_vector(0 to threads-1); +signal ex2_iac4_cmprh : std_ulogic_vector(0 to threads-1); +signal ex2_iac1_cmprl : std_ulogic_vector(0 to threads-1); +signal ex2_iac2_cmprl : std_ulogic_vector(0 to threads-1); +signal ex2_iac3_cmprl : std_ulogic_vector(0 to threads-1); +signal ex2_iac4_cmprl : std_ulogic_vector(0 to threads-1); +signal ex2_iac1_cmpr : std_ulogic_vector(0 to threads-1); +signal ex2_iac2_cmpr : std_ulogic_vector(0 to threads-1); +signal ex2_iac3_cmpr : std_ulogic_vector(0 to threads-1); +signal ex2_iac4_cmpr : std_ulogic_vector(0 to threads-1); +signal ex2_iac1_cmpr_sel : std_ulogic_vector(0 to threads-1); +signal ex2_iac2_cmpr_sel : std_ulogic_vector(0 to threads-1); +signal ex2_iac3_cmpr_sel : std_ulogic_vector(0 to threads-1); +signal ex2_iac4_cmpr_sel : std_ulogic_vector(0 to threads-1); +signal ex2_instr : std_ulogic_vector(11 to 20); +signal ex5_is_mtspr : std_ulogic; +signal ex5_instr : std_ulogic_vector(11 to 20); +signal ex2_cspr_rt,ex2_tspr_rt : std_ulogic_vector(64-regsize to 63); +signal ex5_val : std_ulogic; +-- Data + +signal ex5_givpr_di : std_ulogic_vector(givpr_q'range); +signal ex5_iac1_di : std_ulogic_vector(iac1_q'range); +signal ex5_iac2_di : std_ulogic_vector(iac2_q'range); +signal ex5_iac3_di : std_ulogic_vector(iac3_q'range); +signal ex5_iac4_di : std_ulogic_vector(iac4_q'range); +signal ex5_ivpr_di : std_ulogic_vector(ivpr_q'range); +signal ex5_xucr3_di : std_ulogic_vector(xucr3_q'range); +signal ex5_xucr4_di : std_ulogic_vector(xucr4_q'range); +signal + ex2_givpr_rdec , ex2_iac1_rdec , ex2_iac2_rdec , ex2_iac3_rdec + , ex2_iac4_rdec , ex2_ivpr_rdec , ex2_xucr3_rdec , ex2_xucr4_rdec + : std_ulogic; +signal + ex2_givpr_re , ex2_iac1_re , ex2_iac2_re , ex2_iac3_re + , ex2_iac4_re , ex2_ivpr_re , ex2_xucr3_re , ex2_xucr4_re + : std_ulogic; +signal + ex5_givpr_wdec , ex5_iac1_wdec , ex5_iac2_wdec , ex5_iac3_wdec + , ex5_iac4_wdec , ex5_ivpr_wdec , ex5_xucr3_wdec , ex5_xucr4_wdec + : std_ulogic; +signal + ex5_givpr_we , ex5_iac1_we , ex5_iac2_we , ex5_iac3_we + , ex5_iac4_we , ex5_ivpr_we , ex5_xucr3_we , ex5_xucr4_we + : std_ulogic; +signal + givpr_act , iac1_act , iac2_act , iac3_act + , iac4_act , ivpr_act , xucr3_act , xucr4_act + : std_ulogic; +signal + givpr_do , iac1_do , iac2_do , iac3_do + , iac4_do , ivpr_do , xucr3_do , xucr4_do + : std_ulogic_vector(0 to 64); + +begin + + +tiup <= '1'; +tidn <= (others=>'0'); + +ex2_instr <= ex2_instr_q; +ex5_is_mtspr <= ex5_is_mtspr_q; +ex5_instr <= ex5_instr_q; +ex5_val <= or_reduce(ex5_valid); + +ex2_mtiar <= ex2_is_mtspr_q and (ex2_instr_q(11 to 20) = "1001011011"); -- 882 + +cspr_tspr_ex5_is_mtspr <= ex5_is_mtspr_q; +cspr_tspr_ex5_instr <= ex5_instr_q; +cspr_tspr_ex2_instr <= ex2_instr_q; + + +-- SPR Input Control +-- IAC1 +iac1_act <= ex5_iac1_we; +iac1_d <= ex5_iac1_di; + +-- IAC2 +iac2_act <= ex5_iac2_we; +iac2_d <= ex5_iac2_di; + +-- IAC3 +iac3_act <= ex5_iac3_we; +iac3_d <= ex5_iac3_di; + +-- IAC4 +iac4_act <= ex5_iac4_we; +iac4_d <= ex5_iac4_di; + +-- IVPR +ivpr_act <= ex5_ivpr_we; +ivpr_d <= ex5_ivpr_di; + +-- GIVR +givpr_act <= ex5_givpr_we; +givpr_d <= ex5_givpr_di; + +-- XUCR3 +xucr3_act <= ex5_xucr3_we; +xucr3_d <= ex5_xucr3_di; + +-- XUCR4 +xucr4_act <= ex5_xucr4_we; +xucr4_d <= ex5_xucr4_di; + + + +-- IAC Compares +ex3_iac1_cmpr <= ex3_iac1_cmpr_q; +ex3_iac2_cmpr <= ex3_iac2_cmpr_q; +ex3_iac3_cmpr <= ex3_iac3_cmpr_q; +ex3_iac4_cmpr <= ex3_iac4_cmpr_q; + +ifar_cmp : for t in 0 to threads-1 generate +signal ex2_ifar_int : std_ulogic_vector(62-eff_ifar to 61); +signal ex2_iac2_mask : std_ulogic_vector(62-eff_ifar to 61); +signal ex2_iac4_mask : std_ulogic_vector(62-eff_ifar to 61); +begin + + ex2_ifar_int <= ex2_ifar(eff_ifar*t to eff_ifar*(t+1)-1); + + ex2_iac2_mask <= iac2_q or not fanout(dbcr1_iac12m_2_q(t),eff_ifar); + ex2_iac4_mask <= iac4_q or not fanout(dbcr1_iac34m_2_q(t),eff_ifar); + + xuq_spr_iac_cmprh_gen0 : if eff_ifar > 32 generate -- ui=62-eff_ifar + ex2_iac1_cmprh(t) <= and_reduce((ex2_ifar_int(ui to 31) xnor iac1_q(ui+2 to 33)) or not ex2_iac2_mask(ui to 31)); + ex2_iac2_cmprh(t) <= and_reduce((ex2_ifar_int(ui to 31) xnor iac2_q(ui+2 to 33)) ); + ex2_iac3_cmprh(t) <= and_reduce((ex2_ifar_int(ui to 31) xnor iac3_q(ui+2 to 33)) or not ex2_iac4_mask(ui to 31)); + ex2_iac4_cmprh(t) <= and_reduce((ex2_ifar_int(ui to 31) xnor iac4_q(ui+2 to 33)) ); + + ex2_iac1_cmprl(t) <= and_reduce((ex2_ifar_int(32 to 61) xnor iac1_q(32+2 to 63)) or not ex2_iac2_mask(32 to 61)); + ex2_iac2_cmprl(t) <= and_reduce((ex2_ifar_int(32 to 61) xnor iac2_q(32+2 to 63)) ); + ex2_iac3_cmprl(t) <= and_reduce((ex2_ifar_int(32 to 61) xnor iac3_q(32+2 to 63)) or not ex2_iac4_mask(32 to 61)); + ex2_iac4_cmprl(t) <= and_reduce((ex2_ifar_int(32 to 61) xnor iac4_q(32+2 to 63)) ); + + ex2_iac1_cmpr(t) <= ex2_iac1_cmprl(t) and (ex2_iac1_cmprh(t) or not spr_msr_cm(t)); + ex2_iac2_cmpr(t) <= ex2_iac2_cmprl(t) and (ex2_iac2_cmprh(t) or not spr_msr_cm(t)); + ex2_iac3_cmpr(t) <= ex2_iac3_cmprl(t) and (ex2_iac3_cmprh(t) or not spr_msr_cm(t)); + ex2_iac4_cmpr(t) <= ex2_iac4_cmprl(t) and (ex2_iac4_cmprh(t) or not spr_msr_cm(t)); + end generate; + + xuq_spr_iac_cmprh_gen1 : if eff_ifar <= 32 generate -- ui=62-eff_ifar + ex2_iac1_cmprh(t) <= '1'; + ex2_iac2_cmprh(t) <= '1'; + ex2_iac3_cmprh(t) <= '1'; + ex2_iac4_cmprh(t) <= '1'; + + ex2_iac1_cmprl(t) <= and_reduce((ex2_ifar(ui to 61) xnor iac1_q(ui+2 to 63)) or not ex2_iac2_mask(ui to 61)); + ex2_iac2_cmprl(t) <= and_reduce((ex2_ifar(ui to 61) xnor iac2_q(ui+2 to 63)) ); + ex2_iac3_cmprl(t) <= and_reduce((ex2_ifar(ui to 61) xnor iac3_q(ui+2 to 63)) or not ex2_iac4_mask(ui to 61)); + ex2_iac4_cmprl(t) <= and_reduce((ex2_ifar(ui to 61) xnor iac4_q(ui+2 to 63)) ); + + ex2_iac1_cmpr(t) <= ex2_iac1_cmprl(t); + ex2_iac2_cmpr(t) <= ex2_iac2_cmprl(t); + ex2_iac3_cmpr(t) <= ex2_iac3_cmprl(t); + ex2_iac4_cmpr(t) <= ex2_iac4_cmprl(t); + end generate; + + ex2_iac1_cmpr_sel(t) <= ex2_iac1_cmpr(t); + ex2_iac2_cmpr_sel(t) <= ex2_iac2_cmpr(t) when dbcr1_iac12m_2_q(t)(0)='0' else ex2_iac1_cmpr(t); + ex2_iac3_cmpr_sel(t) <= ex2_iac3_cmpr(t); + ex2_iac4_cmpr_sel(t) <= ex2_iac4_cmpr(t) when dbcr1_iac34m_2_q(t)(0)='0' else ex2_iac3_cmpr(t); + + ex3_iac1_cmpr_d(t) <= ex2_iac1_cmpr_sel(t) and iac1_en_q(t); + ex3_iac2_cmpr_d(t) <= ex2_iac2_cmpr_sel(t) and iac2_en_q(t); + ex3_iac3_cmpr_d(t) <= ex2_iac3_cmpr_sel(t) and iac3_en_q(t); + ex3_iac4_cmpr_d(t) <= ex2_iac4_cmpr_sel(t) and iac4_en_q(t); +end generate; + +-- MSR Override + + +readmux_00 : if a2mode = 0 and hvmode = 0 generate +ex2_cspr_rt <= + (iac1_do(DO'range) and (DO'range => ex2_iac1_re )) or + (iac2_do(DO'range) and (DO'range => ex2_iac2_re )) or + (ivpr_do(DO'range) and (DO'range => ex2_ivpr_re )) or + (xucr3_do(DO'range) and (DO'range => ex2_xucr3_re )) or + (xucr4_do(DO'range) and (DO'range => ex2_xucr4_re )); +end generate; +readmux_01 : if a2mode = 0 and hvmode = 1 generate +ex2_cspr_rt <= + (givpr_do(DO'range) and (DO'range => ex2_givpr_re )) or + (iac1_do(DO'range) and (DO'range => ex2_iac1_re )) or + (iac2_do(DO'range) and (DO'range => ex2_iac2_re )) or + (ivpr_do(DO'range) and (DO'range => ex2_ivpr_re )) or + (xucr3_do(DO'range) and (DO'range => ex2_xucr3_re )) or + (xucr4_do(DO'range) and (DO'range => ex2_xucr4_re )); +end generate; +readmux_10 : if a2mode = 1 and hvmode = 0 generate +ex2_cspr_rt <= + (iac1_do(DO'range) and (DO'range => ex2_iac1_re )) or + (iac2_do(DO'range) and (DO'range => ex2_iac2_re )) or + (iac3_do(DO'range) and (DO'range => ex2_iac3_re )) or + (iac4_do(DO'range) and (DO'range => ex2_iac4_re )) or + (ivpr_do(DO'range) and (DO'range => ex2_ivpr_re )) or + (xucr3_do(DO'range) and (DO'range => ex2_xucr3_re )) or + (xucr4_do(DO'range) and (DO'range => ex2_xucr4_re )); +end generate; +readmux_11 : if a2mode = 1 and hvmode = 1 generate +ex2_cspr_rt <= + (givpr_do(DO'range) and (DO'range => ex2_givpr_re )) or + (iac1_do(DO'range) and (DO'range => ex2_iac1_re )) or + (iac2_do(DO'range) and (DO'range => ex2_iac2_re )) or + (iac3_do(DO'range) and (DO'range => ex2_iac3_re )) or + (iac4_do(DO'range) and (DO'range => ex2_iac4_re )) or + (ivpr_do(DO'range) and (DO'range => ex2_ivpr_re )) or + (xucr3_do(DO'range) and (DO'range => ex2_xucr3_re )) or + (xucr4_do(DO'range) and (DO'range => ex2_xucr4_re )); +end generate; + +-- Read Muxing +ex2_tspr_rt <= mux_t(tspr_cspr_ex2_tspr_rt,ex2_tid); +ex3_spr_rt_d <= gate((ex2_tspr_rt or ex2_cspr_rt),ex2_is_mfspr_q); +cpl_byp_ex3_spr_rt <= ex3_spr_rt_q; + + +ex2_givpr_rdec <= (ex2_instr(11 to 20) = "1111101101"); -- 447 +ex2_iac1_rdec <= (ex2_instr(11 to 20) = "1100001001"); -- 312 +ex2_iac2_rdec <= (ex2_instr(11 to 20) = "1100101001"); -- 313 +ex2_iac3_rdec <= (ex2_instr(11 to 20) = "1101001001"); -- 314 +ex2_iac4_rdec <= (ex2_instr(11 to 20) = "1101101001"); -- 315 +ex2_ivpr_rdec <= (ex2_instr(11 to 20) = "1111100001"); -- 63 +ex2_xucr3_rdec <= (ex2_instr(11 to 20) = "1010011010"); -- 852 +ex2_xucr4_rdec <= (ex2_instr(11 to 20) = "1010111010"); -- 853 +ex2_givpr_re <= ex2_givpr_rdec; +ex2_iac1_re <= ex2_iac1_rdec; +ex2_iac2_re <= ex2_iac2_rdec; +ex2_iac3_re <= ex2_iac3_rdec; +ex2_iac4_re <= ex2_iac4_rdec; +ex2_ivpr_re <= ex2_ivpr_rdec; +ex2_xucr3_re <= ex2_xucr3_rdec; +ex2_xucr4_re <= ex2_xucr4_rdec; + +ex5_givpr_wdec <= (ex5_instr(11 to 20) = "1111101101"); -- 447 +ex5_iac1_wdec <= (ex5_instr(11 to 20) = "1100001001"); -- 312 +ex5_iac2_wdec <= (ex5_instr(11 to 20) = "1100101001"); -- 313 +ex5_iac3_wdec <= (ex5_instr(11 to 20) = "1101001001"); -- 314 +ex5_iac4_wdec <= (ex5_instr(11 to 20) = "1101101001"); -- 315 +ex5_ivpr_wdec <= (ex5_instr(11 to 20) = "1111100001"); -- 63 +ex5_xucr3_wdec <= (ex5_instr(11 to 20) = "1010011010"); -- 852 +ex5_xucr4_wdec <= (ex5_instr(11 to 20) = "1010111010"); -- 853 +ex5_givpr_we <= ex5_val and ex5_is_mtspr and ex5_givpr_wdec; +ex5_iac1_we <= ex5_val and ex5_is_mtspr and ex5_iac1_wdec; +ex5_iac2_we <= ex5_val and ex5_is_mtspr and ex5_iac2_wdec; +ex5_iac3_we <= ex5_val and ex5_is_mtspr and ex5_iac3_wdec; +ex5_iac4_we <= ex5_val and ex5_is_mtspr and ex5_iac4_wdec; +ex5_ivpr_we <= ex5_val and ex5_is_mtspr and ex5_ivpr_wdec; +ex5_xucr3_we <= ex5_val and ex5_is_mtspr and ex5_xucr3_wdec; +ex5_xucr4_we <= ex5_val and ex5_is_mtspr and ex5_xucr4_wdec; + +spr_givpr <= givpr_q(64-(eff_ifar-10) to 63); +spr_ivpr <= ivpr_q(64-(eff_ifar-10) to 63); +spr_xucr3_hold1_dly <= xucr3_q(32 to 35); +spr_xucr3_cm_hold_dly <= xucr3_q(36 to 39); +spr_xucr3_stop_dly <= xucr3_q(40 to 43); +spr_xucr3_hold0_dly <= xucr3_q(44 to 47); +spr_xucr3_csi_dly <= xucr3_q(48 to 51); +spr_xucr3_int_dly <= xucr3_q(52 to 55); +spr_xucr3_asyncblk_dly <= xucr3_q(56 to 59); +spr_xucr3_flush_dly <= xucr3_q(60 to 63); +spr_xucr4_mmu_mchk <= xucr4_q(48); +spr_xucr4_mddmh <= xucr4_q(49); +spr_xucr4_div_barr_thres <= xucr4_q(50 to 57); +spr_xucr4_div_bar_dis <= xucr4_q(58); +spr_xucr4_lsu_bar_dis <= xucr4_q(59); +spr_xucr4_barr_dly <= xucr4_q(60 to 63); + +-- GIVPR +ex5_givpr_di <= ex5_spr_wd(52-(eff_ifar-10) to 51); --GIVPR +givpr_do <= tidn(0 to 52-(eff_ifar-10)) & + givpr_q(64-(eff_ifar-10) to 63) & --GIVPR + tidn(52 to 63) ; --/// +-- IAC1 +ex5_iac1_di <= ex5_spr_wd(62-(eff_ifar) to 61) ; --IAC1 +iac1_do <= tidn(0 to 62-(eff_ifar)) & + iac1_q(64-(eff_ifar) to 63) & --IAC1 + tidn(62 to 63) ; --/// +-- IAC2 +ex5_iac2_di <= ex5_spr_wd(62-(eff_ifar) to 61) ; --IAC2 +iac2_do <= tidn(0 to 62-(eff_ifar)) & + iac2_q(64-(eff_ifar) to 63) & --IAC2 + tidn(62 to 63) ; --/// +-- IAC3 +ex5_iac3_di <= ex5_spr_wd(62-(eff_ifar) to 61) ; --IAC3 +iac3_do <= tidn(0 to 62-(eff_ifar)) & + iac3_q(64-(eff_ifar) to 63) & --IAC3 + tidn(62 to 63) ; --/// +-- IAC4 +ex5_iac4_di <= ex5_spr_wd(62-(eff_ifar) to 61) ; --IAC4 +iac4_do <= tidn(0 to 62-(eff_ifar)) & + iac4_q(64-(eff_ifar) to 63) & --IAC4 + tidn(62 to 63) ; --/// +-- IVPR +ex5_ivpr_di <= ex5_spr_wd(52-(eff_ifar-10) to 51); --IVPR +ivpr_do <= tidn(0 to 52-(eff_ifar-10)) & + ivpr_q(64-(eff_ifar-10) to 63) & --IVPR + tidn(52 to 63) ; --/// +-- XUCR3 +ex5_xucr3_di <= ex5_spr_wd(32 to 35) & --HOLD1_DLY + ex5_spr_wd(36 to 39) & --CM_HOLD_DLY + ex5_spr_wd(40 to 43) & --STOP_DLY + ex5_spr_wd(44 to 47) & --HOLD0_DLY + ex5_spr_wd(48 to 51) & --CSI_DLY + ex5_spr_wd(52 to 55) & --INT_DLY + ex5_spr_wd(56 to 59) & --ASYNCBLK_DLY + ex5_spr_wd(60 to 63) ; --FLUSH_DLY +xucr3_do <= tidn(0 to 0) & + tidn(0 to 31) & --/// + xucr3_q(32 to 35) & --HOLD1_DLY + xucr3_q(36 to 39) & --CM_HOLD_DLY + xucr3_q(40 to 43) & --STOP_DLY + xucr3_q(44 to 47) & --HOLD0_DLY + xucr3_q(48 to 51) & --CSI_DLY + xucr3_q(52 to 55) & --INT_DLY + xucr3_q(56 to 59) & --ASYNCBLK_DLY + xucr3_q(60 to 63) ; --FLUSH_DLY +-- XUCR4 +ex5_xucr4_di <= ex5_spr_wd(46 to 46) & --MMU_MCHK + ex5_spr_wd(47 to 47) & --MDDMH + ex5_spr_wd(48 to 55) & --DIV_BARR_THRES + ex5_spr_wd(58 to 58) & --DIV_BAR_DIS + ex5_spr_wd(59 to 59) & --LSU_BAR_DIS + ex5_spr_wd(60 to 63) ; --BARR_DLY +xucr4_do <= tidn(0 to 0) & + tidn(0 to 31) & --/// + tidn(32 to 45) & --/// + xucr4_q(48 to 48) & --MMU_MCHK + xucr4_q(49 to 49) & --MDDMH + xucr4_q(50 to 57) & --DIV_BARR_THRES + tidn(56 to 57) & --/// + xucr4_q(58 to 58) & --DIV_BAR_DIS + xucr4_q(59 to 59) & --LSU_BAR_DIS + xucr4_q(60 to 63) ; --BARR_DLY + +-- Unused Signals +mark_unused(givpr_do(0 to 64-regsize)); +mark_unused(iac1_do(0 to 64-regsize)); +mark_unused(iac2_do(0 to 64-regsize)); +mark_unused(iac3_do(0 to 64-regsize)); +mark_unused(iac4_do(0 to 64-regsize)); +mark_unused(ivpr_do(0 to 64-regsize)); +mark_unused(xucr3_do(0 to 64-regsize)); +mark_unused(xucr4_do(0 to 64-regsize)); + +givpr_latch_gen : if hvmode = 1 generate +givpr_latch : tri_ser_rlmreg_p +generic map(width => givpr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => givpr_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(givpr_offset to givpr_offset + givpr_q'length-1), + scout => sov(givpr_offset to givpr_offset + givpr_q'length-1), + din => givpr_d, + dout => givpr_q); +end generate; +givpr_latch_tie : if hvmode = 0 generate + givpr_q <= (others=>'0'); +end generate; +iac1_latch : tri_ser_rlmreg_p +generic map(width => iac1_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => iac1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(iac1_offset to iac1_offset + iac1_q'length-1), + scout => sov(iac1_offset to iac1_offset + iac1_q'length-1), + din => iac1_d, + dout => iac1_q); +iac2_latch : tri_ser_rlmreg_p +generic map(width => iac2_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => iac2_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(iac2_offset to iac2_offset + iac2_q'length-1), + scout => sov(iac2_offset to iac2_offset + iac2_q'length-1), + din => iac2_d, + dout => iac2_q); +iac3_latch_gen : if a2mode = 1 generate +iac3_latch : tri_ser_rlmreg_p +generic map(width => iac3_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => iac3_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(iac3_offset to iac3_offset + iac3_q'length-1), + scout => sov(iac3_offset to iac3_offset + iac3_q'length-1), + din => iac3_d, + dout => iac3_q); +end generate; +iac3_latch_tie : if a2mode = 0 generate + iac3_q <= (others=>'0'); +end generate; +iac4_latch_gen : if a2mode = 1 generate +iac4_latch : tri_ser_rlmreg_p +generic map(width => iac4_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => iac4_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(iac4_offset to iac4_offset + iac4_q'length-1), + scout => sov(iac4_offset to iac4_offset + iac4_q'length-1), + din => iac4_d, + dout => iac4_q); +end generate; +iac4_latch_tie : if a2mode = 0 generate + iac4_q <= (others=>'0'); +end generate; +ivpr_latch : tri_ser_rlmreg_p +generic map(width => ivpr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => ivpr_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ivpr_offset to ivpr_offset + ivpr_q'length-1), + scout => sov(ivpr_offset to ivpr_offset + ivpr_q'length-1), + din => ivpr_d, + dout => ivpr_q); +xucr3_latch : tri_ser_rlmreg_p +generic map(width => xucr3_q'length, init => 37753921, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => xucr3_act, + forcee => dcfg_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => dcfg_sl_thold_0_b, + sg => sg_0, + scin => siv_dcfg(xucr3_offset_dcfg to xucr3_offset_dcfg + xucr3_q'length-1), + scout => sov_dcfg(xucr3_offset_dcfg to xucr3_offset_dcfg + xucr3_q'length-1), + din => xucr3_d, + dout => xucr3_q); +xucr4_latch : tri_ser_rlmreg_p +generic map(width => xucr4_q'length, init => 320, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => xucr4_act, + forcee => dcfg_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => dcfg_sl_thold_0_b, + sg => sg_0, + scin => siv_dcfg(xucr4_offset_dcfg to xucr4_offset_dcfg + xucr4_q'length-1), + scout => sov_dcfg(xucr4_offset_dcfg to xucr4_offset_dcfg + xucr4_q'length-1), + din => xucr4_d, + dout => xucr4_q); + + +mark_unused(tidn(46 to 51)); + +-- Latch Instances +ex2_is_mfspr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_is_mfspr_offset), + scout => sov(ex2_is_mfspr_offset), + din => ex1_is_mfspr, + dout => ex2_is_mfspr_q); +ex2_is_mtspr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_is_mtspr_offset), + scout => sov(ex2_is_mtspr_offset), + din => ex1_is_mtspr, + dout => ex2_is_mtspr_q); +ex2_instr_latch : tri_rlmreg_p + generic map (width => ex2_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_instr_offset to ex2_instr_offset + ex2_instr_q'length-1), + scout => sov(ex2_instr_offset to ex2_instr_offset + ex2_instr_q'length-1), + din => ex1_instr, + dout => ex2_instr_q); +ex3_is_mtspr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_mtspr_offset), + scout => sov(ex3_is_mtspr_offset), + din => ex2_is_mtspr_q, + dout => ex3_is_mtspr_q); +ex3_instr_latch : tri_rlmreg_p + generic map (width => ex3_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_instr_offset to ex3_instr_offset + ex3_instr_q'length-1), + scout => sov(ex3_instr_offset to ex3_instr_offset + ex3_instr_q'length-1), + din => ex2_instr_q, + dout => ex3_instr_q); +ex3_spr_rt_latch : tri_rlmreg_p + generic map (width => ex3_spr_rt_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_spr_rt_offset to ex3_spr_rt_offset + ex3_spr_rt_q'length-1), + scout => sov(ex3_spr_rt_offset to ex3_spr_rt_offset + ex3_spr_rt_q'length-1), + din => ex3_spr_rt_d, + dout => ex3_spr_rt_q); +ex3_iac1_cmpr_latch : tri_rlmreg_p + generic map (width => ex3_iac1_cmpr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_iac1_cmpr_offset to ex3_iac1_cmpr_offset + ex3_iac1_cmpr_q'length-1), + scout => sov(ex3_iac1_cmpr_offset to ex3_iac1_cmpr_offset + ex3_iac1_cmpr_q'length-1), + din => ex3_iac1_cmpr_d, + dout => ex3_iac1_cmpr_q); +ex3_iac2_cmpr_latch : tri_rlmreg_p + generic map (width => ex3_iac2_cmpr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_iac2_cmpr_offset to ex3_iac2_cmpr_offset + ex3_iac2_cmpr_q'length-1), + scout => sov(ex3_iac2_cmpr_offset to ex3_iac2_cmpr_offset + ex3_iac2_cmpr_q'length-1), + din => ex3_iac2_cmpr_d, + dout => ex3_iac2_cmpr_q); +ex3_iac3_cmpr_latch : tri_rlmreg_p + generic map (width => ex3_iac3_cmpr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_iac3_cmpr_offset to ex3_iac3_cmpr_offset + ex3_iac3_cmpr_q'length-1), + scout => sov(ex3_iac3_cmpr_offset to ex3_iac3_cmpr_offset + ex3_iac3_cmpr_q'length-1), + din => ex3_iac3_cmpr_d, + dout => ex3_iac3_cmpr_q); +ex3_iac4_cmpr_latch : tri_rlmreg_p + generic map (width => ex3_iac4_cmpr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_iac4_cmpr_offset to ex3_iac4_cmpr_offset + ex3_iac4_cmpr_q'length-1), + scout => sov(ex3_iac4_cmpr_offset to ex3_iac4_cmpr_offset + ex3_iac4_cmpr_q'length-1), + din => ex3_iac4_cmpr_d, + dout => ex3_iac4_cmpr_q); +ex4_is_mtspr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_is_mtspr_offset), + scout => sov(ex4_is_mtspr_offset), + din => ex3_is_mtspr_q, + dout => ex4_is_mtspr_q); +ex4_instr_latch : tri_rlmreg_p + generic map (width => ex4_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_instr_offset to ex4_instr_offset + ex4_instr_q'length-1), + scout => sov(ex4_instr_offset to ex4_instr_offset + ex4_instr_q'length-1), + din => ex3_instr_q, + dout => ex4_instr_q); +ex5_is_mtspr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_is_mtspr_offset), + scout => sov(ex5_is_mtspr_offset), + din => ex4_is_mtspr_q, + dout => ex5_is_mtspr_q); +ex5_instr_latch : tri_rlmreg_p + generic map (width => ex5_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_instr_offset to ex5_instr_offset + ex5_instr_q'length-1), + scout => sov(ex5_instr_offset to ex5_instr_offset + ex5_instr_q'length-1), + din => ex4_instr_q, + dout => ex5_instr_q); + +dbcr1_iacm_gen : for t in 0 to threads-1 generate +dbcr1_iac12m_2_latch : tri_regk + generic map (width => dbcr1_iac12m_2_q(t)'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => dbcr1_iac12m_2_d(t), + dout => dbcr1_iac12m_2_q(t)); +dbcr1_iac34m_2_latch : tri_regk + generic map (width => dbcr1_iac34m_2_q(t)'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => dbcr1_iac34m_2_d(t), + dout => dbcr1_iac34m_2_q(t)); +dbcr1_iac12m_2_d(t) <= (others=>dbcr1_iac12m_q(t)); +dbcr1_iac34m_2_d(t) <= (others=>dbcr1_iac34m_q(t)); +end generate; + +iac1_en_latch : tri_rlmreg_p + generic map (width => iac1_en_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(iac1_en_offset to iac1_en_offset + iac1_en_q'length-1), + scout => sov(iac1_en_offset to iac1_en_offset + iac1_en_q'length-1), + din => spr_cpl_iac1_en , + dout => iac1_en_q); +iac2_en_latch : tri_rlmreg_p + generic map (width => iac2_en_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(iac2_en_offset to iac2_en_offset + iac2_en_q'length-1), + scout => sov(iac2_en_offset to iac2_en_offset + iac2_en_q'length-1), + din => spr_cpl_iac2_en , + dout => iac2_en_q); +iac3_en_latch : tri_rlmreg_p + generic map (width => iac3_en_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(iac3_en_offset to iac3_en_offset + iac3_en_q'length-1), + scout => sov(iac3_en_offset to iac3_en_offset + iac3_en_q'length-1), + din => spr_cpl_iac3_en , + dout => iac3_en_q); +iac4_en_latch : tri_rlmreg_p + generic map (width => iac4_en_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(iac4_en_offset to iac4_en_offset + iac4_en_q'length-1), + scout => sov(iac4_en_offset to iac4_en_offset + iac4_en_q'length-1), + din => spr_cpl_iac4_en , + dout => iac4_en_q); +dbcr1_iac12m_latch : tri_rlmreg_p + generic map (width => dbcr1_iac12m_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dbcr1_iac12m_offset to dbcr1_iac12m_offset + dbcr1_iac12m_q'length-1), + scout => sov(dbcr1_iac12m_offset to dbcr1_iac12m_offset + dbcr1_iac12m_q'length-1), + din => spr_dbcr1_iac12m, + dout => dbcr1_iac12m_q); +dbcr1_iac34m_latch : tri_rlmreg_p + generic map (width => dbcr1_iac34m_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dbcr1_iac34m_offset to dbcr1_iac34m_offset + dbcr1_iac34m_q'length-1), + scout => sov(dbcr1_iac34m_offset to dbcr1_iac34m_offset + dbcr1_iac34m_q'length-1), + din => spr_dbcr1_iac34m, + dout => dbcr1_iac34m_q); + +siv(0 to scan_right-1) <= sov(1 to scan_right-1) & scan_in; +scan_out <= sov(0); + + +dcfg_l : if sov_dcfg'length > 1 generate +siv_dcfg(0 to scan_right_dcfg-1) <= sov_dcfg(1 to scan_right_dcfg-1) & dcfg_scan_in; +dcfg_scan_out <= sov_dcfg(0); +end generate; +dcfg_s : if sov_dcfg'length <= 1 generate +dcfg_scan_out <= dcfg_scan_in; +sov_dcfg <= (others=>'0'); +siv_dcfg <= (others=>'0'); +end generate; + +end architecture xuq_cpl_spr_cspr; diff --git a/rel/src/vhdl/work/xuq_cpl_spr_tspr.vhdl b/rel/src/vhdl/work/xuq_cpl_spr_tspr.vhdl new file mode 100644 index 0000000..54f7c96 --- /dev/null +++ b/rel/src/vhdl/work/xuq_cpl_spr_tspr.vhdl @@ -0,0 +1,307 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XU SPR - per thread register slice +-- +library ieee,ibm,support,work,tri; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use support.power_logic_pkg.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use tri.tri_latches_pkg.all; +use work.xuq_pkg.all; + +entity xuq_cpl_spr_tspr is +generic( + hvmode : integer := 1; + a2mode : integer := 1; + expand_type : integer := 2; + regsize : integer := 64; + eff_ifar : integer := 62); +port( + nclk : in clk_logic; + d_mode_dc : in std_ulogic; + delay_lclkr_dc : in std_ulogic; + mpw1_dc_b : in std_ulogic; + mpw2_dc_b : in std_ulogic; + func_sl_force : in std_ulogic; + func_sl_thold_0_b : in std_ulogic; + sg_0 : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + -- Read Interface + cspr_tspr_ex2_instr : in std_ulogic_vector(11 to 20); + tspr_cspr_ex2_tspr_rt : out std_ulogic_vector(64-regsize to 63); + + -- Write Interface + ex5_val : in std_ulogic; + cspr_tspr_ex5_is_mtspr : in std_ulogic; + cspr_tspr_ex5_instr : in std_ulogic_vector(11 to 20); + ex5_spr_wd : in std_ulogic_vector(64-regsize to 63); + ex5_cia_p1 : in std_ulogic_vector(62-eff_ifar to 61); + + -- Decode Signals + ex4_lr_update : in std_ulogic; + ex4_ctr_dec_update : in std_ulogic; + + + -- SPRs + spr_iar : in std_ulogic_vector(62-eff_ifar to 61); + spr_ctr : out std_ulogic_vector(0 to regsize-1); + spr_lr : out std_ulogic_vector(0 to regsize-1); + + -- Power + vdd : inout power_logic; + gnd : inout power_logic +); + +-- synopsys translate_off + +-- synopsys translate_on +end xuq_cpl_spr_tspr; +architecture xuq_cpl_spr_tspr of xuq_cpl_spr_tspr is + +-- Types +subtype DO is std_ulogic_vector(65-regsize to 64); +-- SPR Registers +signal ctr_d , ctr_q : std_ulogic_vector(64-(regsize) to 63); +signal lr_d , lr_q : std_ulogic_vector(64-(regsize) to 63); +-- FUNC Scanchain +constant ctr_offset : natural := 0; +constant lr_offset : natural := ctr_offset + ctr_q'length; +constant last_reg_offset : natural := lr_offset + lr_q'length; +-- BCFG Scanchain +constant last_reg_offset_bcfg : natural := 1; +-- CCFG Scanchain +constant last_reg_offset_ccfg : natural := 1; +-- DCFG Scanchain +constant last_reg_offset_dcfg : natural := 1; +-- Latches +signal ex5_lr_update_q : std_ulogic; -- ex4_lr_update +signal ex5_ctr_dec_update_q : std_ulogic; -- ex4_ctr_dec_update +-- Scanchains +constant ex5_lr_update_offset : integer := last_reg_offset; +constant ex5_ctr_dec_update_offset : integer := ex5_lr_update_offset + 1; +constant scan_right : integer := ex5_ctr_dec_update_offset + 1; +signal siv : std_ulogic_vector(0 to scan_right-1); +signal sov : std_ulogic_vector(0 to scan_right-1); +-- Signals +signal tiup : std_ulogic; +signal tidn : std_ulogic_vector(00 to 63); +signal ex2_instr : std_ulogic_vector(11 to 20); +signal ex5_is_mtspr : std_ulogic; +signal ex5_instr : std_ulogic_vector(11 to 20); +signal ex5_lr_update : std_ulogic; +signal ex5_ctr_dec_update : std_ulogic; +signal spr_iar_int : std_ulogic_vector(0 to 62); +-- Data + +signal ex5_ctr_di : std_ulogic_vector(ctr_q'range); +signal ex5_lr_di : std_ulogic_vector(lr_q'range); +signal + ex2_ctr_rdec , ex2_iar_rdec , ex2_lr_rdec + : std_ulogic; +signal + ex2_ctr_re , ex2_iar_re , ex2_lr_re + : std_ulogic; +signal + ex5_ctr_wdec , ex5_iar_wdec , ex5_lr_wdec + : std_ulogic; +signal + ex5_ctr_we , ex5_iar_we , ex5_lr_we + : std_ulogic; +signal + ctr_act , iar_act , lr_act + : std_ulogic; +signal + ctr_do , iar_do , lr_do + : std_ulogic_vector(0 to 64); + +begin + + +tiup <= '1'; +tidn <= (others=>'0'); +ex2_instr <= cspr_tspr_ex2_instr; +ex5_is_mtspr <= cspr_tspr_ex5_is_mtspr; +ex5_instr <= cspr_tspr_ex5_instr; + +ex5_lr_update <= ex5_val and ex5_lr_update_q; +ex5_ctr_dec_update <= ex5_val and ex5_ctr_dec_update_q; + +spr_iar_int <= tidn(0 to 62-eff_ifar) & spr_iar; + +-- SPR Input Control +-- CTR +ctr_act <= ex5_ctr_we or ex5_ctr_dec_update; + +with ex5_ctr_dec_update_q select + ctr_d <= std_ulogic_vector(unsigned(ctr_q) - 1) when '1', + ex5_ctr_di when others; + +-- IAR +iar_act <= tiup; + +-- LR +lr_act <= ex5_lr_we or ex5_lr_update; + +with ex5_lr_update select + lr_d <= ex5_cia_p1 & "00" when '1', + ex5_lr_di when others; + + + + +readmux_00 : if a2mode = 0 and hvmode = 0 generate +tspr_cspr_ex2_tspr_rt <= + (ctr_do(DO'range) and (DO'range => ex2_ctr_re )) or + (iar_do(DO'range) and (DO'range => ex2_iar_re )) or + (lr_do(DO'range) and (DO'range => ex2_lr_re )); +end generate; +readmux_01 : if a2mode = 0 and hvmode = 1 generate +tspr_cspr_ex2_tspr_rt <= + (ctr_do(DO'range) and (DO'range => ex2_ctr_re )) or + (iar_do(DO'range) and (DO'range => ex2_iar_re )) or + (lr_do(DO'range) and (DO'range => ex2_lr_re )); +end generate; +readmux_10 : if a2mode = 1 and hvmode = 0 generate +tspr_cspr_ex2_tspr_rt <= + (ctr_do(DO'range) and (DO'range => ex2_ctr_re )) or + (iar_do(DO'range) and (DO'range => ex2_iar_re )) or + (lr_do(DO'range) and (DO'range => ex2_lr_re )); +end generate; +readmux_11 : if a2mode = 1 and hvmode = 1 generate +tspr_cspr_ex2_tspr_rt <= + (ctr_do(DO'range) and (DO'range => ex2_ctr_re )) or + (iar_do(DO'range) and (DO'range => ex2_iar_re )) or + (lr_do(DO'range) and (DO'range => ex2_lr_re )); +end generate; + +ex2_ctr_rdec <= (ex2_instr(11 to 20) = "0100100000"); -- 9 +ex2_iar_rdec <= (ex2_instr(11 to 20) = "1001011011"); -- 882 +ex2_lr_rdec <= (ex2_instr(11 to 20) = "0100000000"); -- 8 +ex2_ctr_re <= ex2_ctr_rdec; +ex2_iar_re <= ex2_iar_rdec; +ex2_lr_re <= ex2_lr_rdec; + +ex5_ctr_wdec <= (ex5_instr(11 to 20) = "0100100000"); -- 9 +ex5_iar_wdec <= (ex5_instr(11 to 20) = "1001011011"); -- 882 +ex5_lr_wdec <= (ex5_instr(11 to 20) = "0100000000"); -- 8 +ex5_ctr_we <= ex5_val and ex5_is_mtspr and ex5_ctr_wdec; +ex5_iar_we <= ex5_val and ex5_is_mtspr and ex5_iar_wdec; +ex5_lr_we <= ex5_val and ex5_is_mtspr and ex5_lr_wdec; + +spr_ctr <= ctr_q(64-(regsize) to 63); +spr_lr <= lr_q(64-(regsize) to 63); + +-- CTR +ex5_ctr_di <= ex5_spr_wd(64-(regsize) to 63) ; --CTR +ctr_do <= tidn(0 to 64-(regsize)) & + ctr_q(64-(regsize) to 63) ; --CTR +-- IAR +iar_do <= tidn(0 to 0) & + spr_iar_int(1 to 62) & --IAR + tidn(62 to 63) ; --/// +-- LR +ex5_lr_di <= ex5_spr_wd(64-(regsize) to 63) ; --LR +lr_do <= tidn(0 to 64-(regsize)) & + lr_q(64-(regsize) to 63) ; --LR + +-- Unused Signals +mark_unused(ctr_do(0 to 64-regsize)); +mark_unused(iar_do(0 to 64-regsize)); +mark_unused(lr_do(0 to 64-regsize)); + +ctr_latch : tri_ser_rlmreg_p +generic map(width => ctr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => ctr_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ctr_offset to ctr_offset + ctr_q'length-1), + scout => sov(ctr_offset to ctr_offset + ctr_q'length-1), + din => ctr_d, + dout => ctr_q); +lr_latch : tri_ser_rlmreg_p +generic map(width => lr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => lr_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(lr_offset to lr_offset + lr_q'length-1), + scout => sov(lr_offset to lr_offset + lr_q'length-1), + din => lr_d, + dout => lr_q); + + +mark_unused(tidn(1 to 61)); +mark_unused(spr_iar_int(0)); +mark_unused(iar_act); +mark_unused(ex5_iar_we); + +-- Latch Instances +ex5_lr_update_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_lr_update_offset), + scout => sov(ex5_lr_update_offset), + din => ex4_lr_update, + dout => ex5_lr_update_q); +ex5_ctr_dec_update_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_ctr_dec_update_offset), + scout => sov(ex5_ctr_dec_update_offset), + din => ex4_ctr_dec_update, + dout => ex5_ctr_dec_update_q); + +siv(0 to scan_right-1) <= sov(1 to scan_right-1) & scan_in; +scan_out <= sov(0); + + +end architecture xuq_cpl_spr_tspr; diff --git a/rel/src/vhdl/work/xuq_ctrl.vhdl b/rel/src/vhdl/work/xuq_ctrl.vhdl new file mode 100644 index 0000000..eceacd8 --- /dev/null +++ b/rel/src/vhdl/work/xuq_ctrl.vhdl @@ -0,0 +1,2322 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XU Exception Handler +-- +library ieee,ibm,support,work,tri,clib; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use support.power_logic_pkg.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use tri.tri_latches_pkg.all; +use work.xuq_pkg.all; + +entity xuq_ctrl is +generic( + expand_type : integer := 2; + threads : integer := 4; + eff_ifar : integer := 62; + uc_ifar : integer := 21; + regsize : integer := 64; + hvmode : integer := 1; + regmode : integer := 6; + dc_size : natural := 14; + cl_size : natural := 6; -- 2^6 = 64 Bytes CacheLines + real_data_add : integer := 42; + fxu_synth : integer := 0; + a2mode : integer := 1; + lmq_entries : integer := 8; + l_endian_m : integer := 1; + load_credits : integer := 4; + store_credits : integer := 20; + st_data_32B_mode : integer := 1; -- 0 = 16B store data to L2, 1 = 32B data + bcfg_epn_0to15 : integer := 0; + bcfg_epn_16to31 : integer := 0; + bcfg_epn_32to47 : integer := (2**16)-1; + bcfg_epn_48to51 : integer := (2**4)-1; + bcfg_rpn_22to31 : integer := (2**10)-1; + bcfg_rpn_32to47 : integer := (2**16)-1; + bcfg_rpn_48to51 : integer := (2**4)-1); +port( + + --------------------------------------------------------------------- + -- Pervasive + --------------------------------------------------------------------- + func_scan_in :in std_ulogic_vector(41 to 58); + func_scan_out :out std_ulogic_vector(41 to 58); + an_ac_grffence_en_dc :in std_ulogic; + an_ac_scan_dis_dc_b :in std_ulogic; + an_ac_lbist_en_dc :in std_ulogic; + pc_xu_abist_raddr_0 :in std_ulogic_vector(5 to 9); + pc_xu_abist_ena_dc :in std_ulogic; + pc_xu_abist_waddr_0 :in std_ulogic_vector(5 to 9); + pc_xu_abist_di_0 :in std_ulogic_vector(0 to 3); + pc_xu_abist_raw_dc_b :in std_ulogic; + pc_xu_ccflush_dc :in std_ulogic; + clkoff_dc_b :out std_ulogic; + d_mode_dc :out std_ulogic; + delay_lclkr_dc :out std_ulogic_vector(0 to 4); + mpw1_dc_b :out std_ulogic_vector(0 to 4); + mpw2_dc_b :out std_ulogic; + g6t_clkoff_dc_b :out std_ulogic; + g6t_d_mode_dc :out std_ulogic; + g6t_delay_lclkr_dc :out std_ulogic_vector(0 to 4); + g6t_mpw1_dc_b :out std_ulogic_vector(0 to 4); + g6t_mpw2_dc_b :out std_ulogic; + pc_xu_sg_3 :in std_ulogic_vector(0 to 4); + pc_xu_func_sl_thold_3 :in std_ulogic_vector(0 to 4); + pc_xu_func_slp_sl_thold_3 :in std_ulogic_vector(0 to 4); + pc_xu_func_nsl_thold_3 :in std_ulogic; + pc_xu_func_slp_nsl_thold_3 :in std_ulogic; + pc_xu_gptr_sl_thold_3 :in std_ulogic; + pc_xu_abst_sl_thold_3 :in std_ulogic; + pc_xu_abst_slp_sl_thold_3 :in std_ulogic; + pc_xu_regf_sl_thold_3 :in std_ulogic; + pc_xu_regf_slp_sl_thold_3 :in std_ulogic; + pc_xu_time_sl_thold_3 :in std_ulogic; + pc_xu_cfg_sl_thold_3 :in std_ulogic; + pc_xu_cfg_slp_sl_thold_3 :in std_ulogic; + pc_xu_ary_nsl_thold_3 :in std_ulogic; + pc_xu_ary_slp_nsl_thold_3 :in std_ulogic; + pc_xu_repr_sl_thold_3 :in std_ulogic; + pc_xu_fce_3 :in std_ulogic_vector(0 to 1); + an_ac_scan_diag_dc :in std_ulogic; + sg_2 :out std_ulogic_vector(0 to 3); + fce_2 :out std_ulogic_vector(0 to 1); + func_sl_thold_2 :out std_ulogic_vector(0 to 3); + func_slp_sl_thold_2 :out std_ulogic_vector(0 to 1); + func_nsl_thold_2 :out std_ulogic; + func_slp_nsl_thold_2 :out std_ulogic; + abst_sl_thold_2 :out std_ulogic; + time_sl_thold_2 :out std_ulogic; + gptr_sl_thold_2 :out std_ulogic; + ary_nsl_thold_2 :out std_ulogic; + repr_sl_thold_2 :out std_ulogic; + cfg_sl_thold_2 :out std_ulogic; + cfg_slp_sl_thold_2 :out std_ulogic; + regf_slp_sl_thold_2 :out std_ulogic; + gptr_scan_in :in std_ulogic; + gptr_scan_out :out std_ulogic; + time_scan_in :in std_ulogic; + time_scan_out :out std_ulogic; + pc_xu_bolt_sl_thold_3 :in std_ulogic; + pc_xu_bo_enable_3 :in std_ulogic; + bolt_sl_thold_2 :out std_ulogic; + bo_enable_2 :out std_ulogic; + pc_xu_bo_unload :in std_ulogic; + pc_xu_bo_repair :in std_ulogic; + pc_xu_bo_reset :in std_ulogic; + pc_xu_bo_shdata :in std_ulogic; + pc_xu_bo_select :in std_ulogic_vector(1 to 4); + xu_pc_bo_fail :out std_ulogic_vector(1 to 4); + xu_pc_bo_diagout :out std_ulogic_vector(1 to 4); + + ------------------------------------------------------------------------ + -- Interface with FXU A + ------------------------------------------------------------------------ + fxa_fxb_rf0_val :in std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_issued :in std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_ucode_val :in std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_act :in std_ulogic; + fxa_fxb_ex1_hold_ctr_flush :in std_ulogic; + fxa_fxb_rf0_instr :in std_ulogic_vector(0 to 31); + fxa_fxb_rf0_tid :in std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_ta_vld :in std_ulogic; + fxa_fxb_rf0_ta :in std_ulogic_vector(0 to 7); + fxa_fxb_rf0_error :in std_ulogic_vector(0 to 2); + fxa_fxb_rf0_match :in std_ulogic; + fxa_fxb_rf0_is_ucode :in std_ulogic; + fxa_fxb_rf0_gshare :in std_ulogic_vector(0 to 3); + fxa_fxb_rf0_ifar :in std_ulogic_vector(62-eff_ifar to 61); + fxa_fxb_rf0_s1_vld :in std_ulogic; + fxa_fxb_rf0_s1 :in std_ulogic_vector(0 to 7); + fxa_fxb_rf0_s2_vld :in std_ulogic; + fxa_fxb_rf0_s2 :in std_ulogic_vector(0 to 7); + fxa_fxb_rf0_s3_vld :in std_ulogic; + fxa_fxb_rf0_s3 :in std_ulogic_vector(0 to 7); + fxa_fxb_rf0_axu_instr_type :in std_ulogic_vector(0 to 2); + fxa_fxb_rf0_axu_ld_or_st :in std_ulogic; + fxa_fxb_rf0_axu_store :in std_ulogic; + fxa_fxb_rf0_axu_ldst_forcealign :in std_ulogic; + fxa_fxb_rf0_axu_ldst_forceexcept :in std_ulogic; + fxa_fxb_rf0_axu_ldst_indexed :in std_ulogic; + fxa_fxb_rf0_axu_ldst_tag :in std_ulogic_vector(0 to 8); + fxa_fxb_rf0_axu_mftgpr :in std_ulogic; + fxa_fxb_rf0_axu_mffgpr :in std_ulogic; + fxa_fxb_rf0_axu_movedp :in std_ulogic; + fxa_fxb_rf0_axu_ldst_size :in std_ulogic_vector(0 to 5); + fxa_fxb_rf0_axu_ldst_update :in std_ulogic; + fxa_fxb_rf0_pred_update :in std_ulogic; + fxa_fxb_rf0_pred_taken_cnt :in std_ulogic_vector(0 to 1); + fxa_fxb_rf0_mc_dep_chk_val :in std_ulogic_vector(0 to threads-1); + fxa_fxb_rf1_mul_val :in std_ulogic; + fxa_fxb_rf1_div_val :in std_ulogic; + fxa_fxb_rf1_div_ctr :in std_ulogic_vector(0 to 7); + fxa_fxb_rf0_xu_epid_instr :in std_ulogic; + fxa_fxb_rf0_axu_is_extload :in std_ulogic; + fxa_fxb_rf0_axu_is_extstore :in std_ulogic; + fxa_fxb_rf0_is_mfocrf :in std_ulogic; + fxa_fxb_rf0_3src_instr :in std_ulogic; + fxa_fxb_rf0_gpr0_zero :in std_ulogic; + fxa_fxb_rf0_use_imm :in std_ulogic; + fxa_fxb_rf1_muldiv_coll :in std_ulogic; + fxa_cpl_ex2_div_coll :in std_ulogic_vector(0 to threads-1); + fxb_fxa_ex7_we0 :out std_ulogic; + fxb_fxa_ex7_wa0 :out std_ulogic_vector(0 to 7); + fxb_fxa_ex7_wd0 :out std_ulogic_vector(64-regsize to 63); + fxa_fxb_rf1_do0 :in std_ulogic_vector(64-regsize to 63); + fxa_fxb_rf1_do1 :in std_ulogic_vector(64-regsize to 63); + fxa_fxb_rf1_do2 :in std_ulogic_vector(64-regsize to 63); + xu_bx_ex1_mtdp_val :out std_ulogic; + xu_bx_ex1_mfdp_val :out std_ulogic; + xu_bx_ex1_ipc_thrd :out std_ulogic_vector(0 to 1); + xu_bx_ex2_ipc_ba :out std_ulogic_vector(0 to 4); + xu_bx_ex2_ipc_sz :out std_ulogic_vector(0 to 1); + + ------------------------------------------------------------------------ + -- D-ERAT Req Interface + ------------------------------------------------------------------------ + xu_mm_derat_epn :out std_ulogic_vector(62-eff_ifar to 51); + + ------------------------------------------------------------------------ + -- TLBSX./TLBSRX. + ------------------------------------------------------------------------ + xu_mm_rf1_is_tlbsxr :out std_ulogic; + mm_xu_cr0_eq_valid :in std_ulogic_vector(0 to threads-1); + mm_xu_cr0_eq :in std_ulogic_vector(0 to threads-1); + + ------------------------------------------------------------------------ + -- FU CR Write + ------------------------------------------------------------------------ + fu_xu_ex4_cr_val :in std_ulogic_vector(0 to threads-1); + fu_xu_ex4_cr_noflush :in std_ulogic_vector(0 to threads-1); + fu_xu_ex4_cr0 :in std_ulogic_vector(0 to 3); + fu_xu_ex4_cr0_bf :in std_ulogic_vector(0 to 2); + fu_xu_ex4_cr1 :in std_ulogic_vector(0 to 3); + fu_xu_ex4_cr1_bf :in std_ulogic_vector(0 to 2); + fu_xu_ex4_cr2 :in std_ulogic_vector(0 to 3); + fu_xu_ex4_cr2_bf :in std_ulogic_vector(0 to 2); + fu_xu_ex4_cr3 :in std_ulogic_vector(0 to 3); + fu_xu_ex4_cr3_bf :in std_ulogic_vector(0 to 2); + + -------------------------------------------------------------------- + -- RAM + -------------------------------------------------------------------- + pc_xu_ram_mode :in std_ulogic; + pc_xu_ram_thread :in std_ulogic_vector(0 to 1); + pc_xu_ram_execute :in std_ulogic; + pc_xu_ram_flush_thread :in std_ulogic; + xu_iu_ram_issue :out std_ulogic_vector(0 to threads-1); + xu_pc_ram_interrupt :out std_ulogic; + xu_pc_ram_done :out std_ulogic; + xu_pc_ram_data :out std_ulogic_vector(64-(2**regmode) to 63); + + -------------------------------------------------------------------- + -- Interface with IU + -------------------------------------------------------------------- + xu_iu_ex5_val :out std_ulogic; + xu_iu_ex5_tid :out std_ulogic_vector(0 to threads-1); + xu_iu_ex5_br_update :out std_ulogic; + xu_iu_ex5_br_hist :out std_ulogic_vector(0 to 1); + xu_iu_ex5_bclr :out std_ulogic; + xu_iu_ex5_lk :out std_ulogic; + xu_iu_ex5_bh :out std_ulogic_vector(0 to 1); + xu_iu_ex6_pri :out std_ulogic_vector(0 to 2); + xu_iu_ex6_pri_val :out std_ulogic_vector(0 to 3); + xu_iu_spr_xer :out std_ulogic_vector(0 to 7*threads-1); + xu_iu_slowspr_done :out std_ulogic_vector(0 to threads-1); + xu_iu_need_hole :out std_ulogic; + fxb_fxa_ex6_clear_barrier :out std_ulogic_vector(0 to threads-1); + xu_iu_ex5_gshare :out std_ulogic_vector(0 to 3); + xu_iu_ex5_getNIA :out std_ulogic; + + ------------------------------------------------------------------------ + -- L2 STCX complete + ------------------------------------------------------------------------ + an_ac_stcx_complete :in std_ulogic_vector(0 to threads-1); + an_ac_stcx_pass :in std_ulogic_vector(0 to threads-1); + + ------------------------------------------------------------------------ + -- Slow SPR Bus + ------------------------------------------------------------------------ + slowspr_val_in :in std_ulogic; + slowspr_rw_in :in std_ulogic; + slowspr_etid_in :in std_ulogic_vector(0 to 1); + slowspr_addr_in :in std_ulogic_vector(0 to 9); + slowspr_data_in :in std_ulogic_vector(64-(2**regmode) to 63); + slowspr_done_in :in std_ulogic; + + ------------------------------------------------------------------------ + -- DCR Bus + ------------------------------------------------------------------------ + an_ac_dcr_act :in std_ulogic; + an_ac_dcr_val :in std_ulogic; + an_ac_dcr_read :in std_ulogic; + an_ac_dcr_etid :in std_ulogic_vector(0 to 1); + an_ac_dcr_data :in std_ulogic_vector(64-(2**regmode) to 63); + an_ac_dcr_done :in std_ulogic; + + ------------------------------------------------------------------------ + -- MT/MFDCR CR + ------------------------------------------------------------------------ + lsu_xu_ex4_mtdp_cr_status :in std_ulogic; + lsu_xu_ex4_mfdp_cr_status :in std_ulogic; + dec_cpl_ex3_mc_dep_chk_val :in std_ulogic_vector(0 to threads-1); + + ------------------------------------------------------------------------ + -- Interface with SPR + ------------------------------------------------------------------------ + dec_spr_ex4_val :out std_ulogic_vector(0 to threads-1); + dec_spr_ex1_epid_instr :out std_ulogic; + mux_spr_ex2_rt :out std_ulogic_vector(64-(2**regmode) to 63); + fxu_spr_ex1_rs0 :out std_ulogic_vector(52 to 63); + fxu_spr_ex1_rs1 :out std_ulogic_vector(54 to 63); + spr_msr_cm :in std_ulogic_vector(0 to threads-1); + spr_dec_spr_xucr0_ssdly :in std_ulogic_vector(0 to 4); + spr_ccr2_en_attn :in std_ulogic; + spr_ccr2_en_ditc :in std_ulogic; + spr_ccr2_en_pc :in std_ulogic; + spr_ccr2_en_icswx :in std_ulogic; + spr_ccr2_en_dcr :in std_ulogic; + spr_dec_rf1_epcr_dgtmi :in std_ulogic_vector(0 to threads-1); + spr_byp_ex4_is_mfxer :in std_ulogic_vector(0 to threads-1); + spr_byp_ex3_spr_rt :in std_ulogic_vector(64-(2**regmode) to 63); + spr_byp_ex4_is_mtxer :in std_ulogic_vector(0 to threads-1); + spr_ccr2_notlb :in std_ulogic; + dec_spr_rf1_val :out std_ulogic_vector(0 to threads-1); + fxu_spr_ex1_rs2 :out std_ulogic_vector(42 to 55); + + ------------------------------------------------------------------------ + -- Perf Events + ------------------------------------------------------------------------ + fxa_perf_muldiv_in_use :in std_ulogic; + spr_perf_tx_events :in std_ulogic_vector(0 to 8*threads-1); + xu_pc_event_data :out std_ulogic_vector(0 to 7); + + ------------------------------------------------------------------------ + -- PC Control Interface + ------------------------------------------------------------------------ + pc_xu_event_count_mode :in std_ulogic_vector(0 to 2); + pc_xu_event_mux_ctrls :in std_ulogic_vector(0 to 47); + + ------------------------------------------------------------------------ + -- Debug Ramp & Controls + ------------------------------------------------------------------------ + fxu_debug_mux_ctrls :in std_ulogic_vector(0 to 15); + cpl_debug_mux_ctrls :in std_ulogic_vector(0 to 15); + lsu_debug_mux_ctrls :in std_ulogic_vector(0 to 15); + ctrl_trigger_data_in :in std_ulogic_vector(0 to 11); + ctrl_trigger_data_out :out std_ulogic_vector(0 to 11); + ctrl_debug_data_in :in std_ulogic_vector(0 to 87); + ctrl_debug_data_out :out std_ulogic_vector(0 to 87); + lsu_xu_data_debug0 :in std_ulogic_vector(0 to 87); + lsu_xu_data_debug1 :in std_ulogic_vector(0 to 87); + lsu_xu_data_debug2 :in std_ulogic_vector(0 to 87); + fxa_cpl_debug :in std_ulogic_vector(0 to 272); + + ------------------------------------------------------------------------ + -- SPR Bits + ------------------------------------------------------------------------ + spr_msr_gs :in std_ulogic_vector(0 to threads-1); + spr_msr_ds :in std_ulogic_vector(0 to threads-1); + spr_msr_pr :in std_ulogic_vector(0 to threads-1); + spr_dbcr0_dac1 :in std_ulogic_vector(0 to 2*threads-1); + spr_dbcr0_dac2 :in std_ulogic_vector(0 to 2*threads-1); + spr_dbcr0_dac3 :in std_ulogic_vector(0 to 2*threads-1); + spr_dbcr0_dac4 :in std_ulogic_vector(0 to 2*threads-1); + + -- CHIP IO + ac_tc_debug_trigger :out std_ulogic_vector(0 to threads-1); + + -- Pervasive + bcfg_scan_in :in std_ulogic; + bcfg_scan_out :out std_ulogic; + dcfg_scan_in :in std_ulogic; + dcfg_scan_out :out std_ulogic; + + -- Valids + dec_cpl_rf0_act :in std_ulogic; + dec_cpl_rf0_tid :in std_ulogic_vector(0 to threads-1); + + -- FU Inputs + fu_xu_rf1_act :in std_ulogic_vector(0 to threads-1); + fu_xu_ex1_ifar :in std_ulogic_vector(0 to eff_ifar*threads-1); + fu_xu_ex2_ifar_val :in std_ulogic_vector(0 to threads-1); + fu_xu_ex2_ifar_issued :in std_ulogic_vector(0 to threads-1); + fu_xu_ex2_instr_type :in std_ulogic_vector(0 to 3*threads-1); + fu_xu_ex2_instr_match :in std_ulogic_vector(0 to threads-1); + fu_xu_ex2_is_ucode :in std_ulogic_vector(0 to threads-1); + + -- PC Inputs + pc_xu_step :in std_ulogic_vector(0 to threads-1); + pc_xu_stop :in std_ulogic_vector(0 to threads-1); + pc_xu_dbg_action :in std_ulogic_vector(0 to 3*threads-1); + pc_xu_force_ude :in std_ulogic_vector(0 to threads-1); + xu_pc_step_done :out std_ulogic_vector(0 to threads-1); + pc_xu_init_reset :in std_ulogic; + + -- Async Interrupt Req Interface + spr_cpl_ext_interrupt :in std_ulogic_vector(0 to threads-1); + spr_cpl_udec_interrupt :in std_ulogic_vector(0 to threads-1); + spr_cpl_perf_interrupt :in std_ulogic_vector(0 to threads-1); + spr_cpl_dec_interrupt :in std_ulogic_vector(0 to threads-1); + spr_cpl_fit_interrupt :in std_ulogic_vector(0 to threads-1); + spr_cpl_crit_interrupt :in std_ulogic_vector(0 to threads-1); + spr_cpl_wdog_interrupt :in std_ulogic_vector(0 to threads-1); + spr_cpl_dbell_interrupt :in std_ulogic_vector(0 to threads-1); + spr_cpl_cdbell_interrupt :in std_ulogic_vector(0 to threads-1); + spr_cpl_gdbell_interrupt :in std_ulogic_vector(0 to threads-1); + spr_cpl_gcdbell_interrupt :in std_ulogic_vector(0 to threads-1); + spr_cpl_gmcdbell_interrupt :in std_ulogic_vector(0 to threads-1); + + cpl_spr_ex5_dbell_taken :out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_cdbell_taken :out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_gdbell_taken :out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_gcdbell_taken :out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_gmcdbell_taken :out std_ulogic_vector(0 to threads-1); + + -- Interrupt Interface + cpl_spr_ex5_act :out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_int :out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_gint :out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_cint :out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_mcint :out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_nia :out std_ulogic_vector(0 to eff_ifar*threads-1); + cpl_spr_ex5_esr :out std_ulogic_vector(0 to 17*threads-1); + cpl_spr_ex5_mcsr :out std_ulogic_vector(0 to 15*threads-1); + cpl_spr_ex5_dbsr :out std_ulogic_vector(0 to 19*threads-1); + cpl_spr_ex5_dear_save :out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_dear_update_saved :out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_dear_update :out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_dbsr_update :out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_esr_update :out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_srr0_dec :out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_force_gsrr :out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_dbsr_ide :out std_ulogic_vector(0 to threads-1); + + spr_cpl_dbsr_ide :in std_ulogic_vector(0 to threads-1); + + -- Machine Check Interrupts + mm_xu_local_snoop_reject :in std_ulogic_vector(0 to threads-1); + mm_xu_lru_par_err :in std_ulogic_vector(0 to threads-1); + mm_xu_tlb_par_err :in std_ulogic_vector(0 to threads-1); + mm_xu_tlb_multihit_err :in std_ulogic_vector(0 to threads-1); + spr_cpl_external_mchk :in std_ulogic_vector(0 to threads-1); + + -- PC Errors + xu_pc_err_attention_instr :out std_ulogic_vector(0 to threads-1); + xu_pc_err_nia_miscmpr :out std_ulogic_vector(0 to threads-1); + xu_pc_err_debug_event :out std_ulogic_vector(0 to threads-1); + + spr_cpl_ex3_ct_le :in std_ulogic_vector(0 to threads-1); + spr_cpl_ex3_ct_be :in std_ulogic_vector(0 to threads-1); + + -- Program + spr_cpl_ex3_spr_illeg :in std_ulogic; + spr_cpl_ex3_spr_priv :in std_ulogic; + + -- Hypv Privledge + spr_cpl_ex3_spr_hypv :in std_logic; + + -- Run State + cpl_spr_stop :out std_ulogic_vector(0 to threads-1); + xu_pc_stop_dbg_event :out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_instr_cpl :out std_ulogic_vector(0 to threads-1); + spr_cpl_quiesce :in std_ulogic_vector(0 to threads-1); + cpl_spr_quiesce :out std_ulogic_vector(0 to threads-1); + spr_cpl_ex2_run_ctl_flush :in std_ulogic_vector(0 to threads-1); + + -- MMU Flushes + mm_xu_illeg_instr :in std_ulogic_vector(0 to threads-1); + mm_xu_tlb_miss :in std_ulogic_vector(0 to threads-1); + mm_xu_pt_fault :in std_ulogic_vector(0 to threads-1); + mm_xu_tlb_inelig :in std_ulogic_vector(0 to threads-1); + mm_xu_lrat_miss :in std_ulogic_vector(0 to threads-1); + mm_xu_hv_priv :in std_ulogic_vector(0 to threads-1); + mm_xu_esr_pt :in std_ulogic_vector(0 to threads-1); + mm_xu_esr_data :in std_ulogic_vector(0 to threads-1); + mm_xu_esr_epid :in std_ulogic_vector(0 to threads-1); + mm_xu_esr_st :in std_ulogic_vector(0 to threads-1); + mm_xu_hold_req :in std_ulogic_vector(0 to threads-1); + mm_xu_hold_done :in std_ulogic_vector(0 to threads-1); + xu_mm_hold_ack :out std_ulogic_vector(0 to threads-1); + mm_xu_eratmiss_done :in std_ulogic_vector(0 to threads-1); + mm_xu_ex3_flush_req :in std_ulogic_vector(0 to threads-1); + + -- AXU Flushes + fu_xu_ex3_ap_int_req :in std_ulogic_vector(0 to threads-1); + fu_xu_ex3_trap :in std_ulogic_vector(0 to threads-1); + fu_xu_ex3_n_flush :in std_ulogic_vector(0 to threads-1); + fu_xu_ex3_np1_flush :in std_ulogic_vector(0 to threads-1); + fu_xu_ex3_flush2ucode :in std_ulogic_vector(0 to threads-1); + fu_xu_ex2_async_block :in std_ulogic_vector(0 to threads-1); + + -- IU Flushes + xu_iu_ex5_br_taken :out std_ulogic; + xu_iu_ex5_ifar :out std_ulogic_vector(62-eff_ifar to 61); + xu_iu_flush :out std_ulogic_vector(0 to threads-1); + xu_iu_iu0_flush_ifar :out std_ulogic_vector(0 to eff_ifar*threads-1); + xu_iu_uc_flush_ifar :out std_ulogic_vector(0 to uc_ifar*threads-1); + xu_iu_flush_2ucode :out std_ulogic_vector(0 to threads-1); + xu_iu_flush_2ucode_type :out std_ulogic_vector(0 to threads-1); + xu_iu_ucode_restart :out std_ulogic_vector(0 to threads-1); + xu_iu_ex5_ppc_cpl :out std_ulogic_vector(0 to threads-1); + + -- Flushes + xu_n_is2_flush : out std_ulogic_vector(0 to threads-1); + xu_n_rf0_flush : out std_ulogic_vector(0 to threads-1); + xu_n_rf1_flush : out std_ulogic_vector(0 to threads-1); + xu_n_ex1_flush : out std_ulogic_vector(0 to threads-1); + xu_n_ex2_flush : out std_ulogic_vector(0 to threads-1); + xu_n_ex3_flush : out std_ulogic_vector(0 to threads-1); + xu_n_ex4_flush : out std_ulogic_vector(0 to threads-1); + xu_n_ex5_flush : out std_ulogic_vector(0 to threads-1); + + xu_s_rf1_flush : out std_ulogic_vector(0 to threads-1); + xu_s_ex1_flush : out std_ulogic_vector(0 to threads-1); + xu_s_ex2_flush : out std_ulogic_vector(0 to threads-1); + xu_s_ex3_flush : out std_ulogic_vector(0 to threads-1); + xu_s_ex4_flush : out std_ulogic_vector(0 to threads-1); + xu_s_ex5_flush : out std_ulogic_vector(0 to threads-1); + + xu_w_rf1_flush : out std_ulogic_vector(0 to threads-1); + xu_w_ex1_flush : out std_ulogic_vector(0 to threads-1); + xu_w_ex2_flush : out std_ulogic_vector(0 to threads-1); + xu_w_ex3_flush : out std_ulogic_vector(0 to threads-1); + xu_w_ex4_flush : out std_ulogic_vector(0 to threads-1); + xu_w_ex5_flush : out std_ulogic_vector(0 to threads-1); + + xu_lsu_ex4_flush_local :out std_ulogic_vector(0 to threads-1); + xu_mm_ex4_flush :out std_ulogic_vector(0 to threads-1); + xu_mm_ex5_flush :out std_ulogic_vector(0 to threads-1); + xu_mm_ierat_flush :out std_ulogic_vector(0 to threads-1); + xu_mm_ierat_miss :out std_ulogic_vector(0 to threads-1); + xu_mm_ex5_perf_itlb :out std_ulogic_vector(0 to threads-1); + xu_mm_ex5_perf_dtlb :out std_ulogic_vector(0 to threads-1); + + -- SPR Bits + spr_bit_act :in std_ulogic; + spr_epcr_duvd :in std_ulogic_vector(0 to threads-1); + spr_cpl_iac1_en :in std_ulogic_vector(0 to threads-1); + spr_cpl_iac2_en :in std_ulogic_vector(0 to threads-1); + spr_cpl_iac3_en :in std_ulogic_vector(0 to threads-1); + spr_cpl_iac4_en :in std_ulogic_vector(0 to threads-1); + spr_dbcr1_iac12m :in std_ulogic_vector(0 to threads-1); + spr_dbcr1_iac34m :in std_ulogic_vector(0 to threads-1); + spr_cpl_fp_precise :in std_ulogic_vector(0 to threads-1); + spr_xucr0_mddp :in std_ulogic; + spr_xucr0_mdcp :in std_ulogic; + spr_msr_de :in std_ulogic_vector(0 to threads-1); + spr_msr_spv :in std_ulogic_vector(0 to threads-1); + spr_msr_fp :in std_ulogic_vector(0 to threads-1); + spr_msr_me :in std_ulogic_vector(0 to threads-1); + spr_msr_ucle :in std_ulogic_vector(0 to threads-1); + spr_msrp_uclep :in std_ulogic_vector(0 to threads-1); + spr_ccr2_ucode_dis :in std_ulogic; + spr_ccr2_ap :in std_ulogic_vector(0 to threads-1); + spr_dbcr0_idm :in std_ulogic_vector(0 to threads-1); + cpl_spr_dbcr0_edm :out std_ulogic_vector(0 to threads-1); + spr_dbcr0_icmp :in std_ulogic_vector(0 to threads-1); + spr_dbcr0_brt :in std_ulogic_vector(0 to threads-1); + spr_dbcr0_trap :in std_ulogic_vector(0 to threads-1); + spr_dbcr0_ret :in std_ulogic_vector(0 to threads-1); + spr_dbcr0_irpt :in std_ulogic_vector(0 to threads-1); + spr_epcr_dsigs :in std_ulogic_vector(0 to threads-1); + spr_epcr_isigs :in std_ulogic_vector(0 to threads-1); + spr_epcr_extgs :in std_ulogic_vector(0 to threads-1); + spr_epcr_dtlbgs :in std_ulogic_vector(0 to threads-1); + spr_epcr_itlbgs :in std_ulogic_vector(0 to threads-1); + spr_xucr4_div_barr_thres :out std_ulogic_vector(0 to 7); + spr_ccr0_we :in std_ulogic_vector(0 to threads-1); + cpl_msr_gs :out std_ulogic_vector(0 to threads-1); + cpl_msr_pr :out std_ulogic_vector(0 to threads-1); + cpl_msr_fp :out std_ulogic_vector(0 to threads-1); + cpl_msr_spv :out std_ulogic_vector(0 to threads-1); + cpl_ccr2_ap :out std_ulogic_vector(0 to threads-1); + spr_xucr0_clkg_ctl :in std_ulogic_vector(1 to 3); + spr_xucr4_mmu_mchk :out std_ulogic; + + -- Parity + spr_cpl_ex3_sprg_ce :in std_ulogic; + spr_cpl_ex3_sprg_ue :in std_ulogic; + iu_xu_ierat_ex2_flush_req :in std_ulogic_vector(0 to threads-1); + iu_xu_ierat_ex3_par_err :in std_ulogic_vector(0 to threads-1); + iu_xu_ierat_ex4_par_err :in std_ulogic_vector(0 to threads-1); + + -- Regfile Parity + fu_xu_ex3_regfile_err_det :in std_ulogic_vector(0 to threads-1); + xu_fu_regfile_seq_beg :out std_ulogic; + fu_xu_regfile_seq_end :in std_ulogic; + gpr_cpl_ex3_regfile_err_det :in std_ulogic; + cpl_gpr_regfile_seq_beg :out std_ulogic; + gpr_cpl_regfile_seq_end :in std_ulogic; + xu_pc_err_mcsr_summary :out std_ulogic_vector(0 to threads-1); + xu_pc_err_ditc_overrun :out std_ulogic; + xu_pc_err_local_snoop_reject :out std_ulogic; + xu_pc_err_tlb_lru_parity :out std_ulogic; + xu_pc_err_ext_mchk :out std_ulogic; + xu_pc_err_ierat_multihit :out std_ulogic; + xu_pc_err_derat_multihit :out std_ulogic; + xu_pc_err_tlb_multihit :out std_ulogic; + xu_pc_err_ierat_parity :out std_ulogic; + xu_pc_err_derat_parity :out std_ulogic; + xu_pc_err_tlb_parity :out std_ulogic; + xu_pc_err_mchk_disabled :out std_ulogic; + xu_pc_err_sprg_ue :out std_ulogic_vector(0 to threads-1); + + -- Debug + xu_iu_rf1_val :out std_ulogic_vector(0 to threads-1); + xu_rf1_val :out std_ulogic_vector(0 to threads-1); + xu_rf1_is_tlbre :out std_ulogic; + xu_rf1_is_tlbwe :out std_ulogic; + xu_rf1_is_tlbsx :out std_ulogic; + xu_rf1_is_tlbsrx :out std_ulogic; + xu_rf1_is_tlbilx :out std_ulogic; + xu_rf1_is_tlbivax :out std_ulogic; + xu_rf1_is_eratre :out std_ulogic; + xu_rf1_is_eratwe :out std_ulogic; + xu_rf1_is_eratsx :out std_ulogic; + xu_rf1_is_eratsrx :out std_ulogic; + xu_rf1_is_eratilx :out std_ulogic; + xu_rf1_is_erativax :out std_ulogic; + xu_ex1_is_isync :out std_ulogic; + xu_ex1_is_csync :out std_ulogic; + xu_rf1_ws :out std_ulogic_vector(0 to 1); + xu_rf1_t :out std_ulogic_vector(0 to 2); + xu_ex1_rs_is :out std_ulogic_vector(0 to 8); + xu_ex1_ra_entry :out std_ulogic_vector(8 to 11); + xu_ex4_rs_data :out std_ulogic_vector(64-(2**regmode) to 63); + + xu_lsu_rf1_data_act :out std_ulogic; + xu_lsu_rf1_axu_ldst_falign :out std_ulogic; + xu_lsu_ex1_store_data :out std_ulogic_vector(64-(2**regmode) to 63); + xu_lsu_ex1_rotsel_ovrd :out std_ulogic_vector(0 to 4); + xu_lsu_ex1_eff_addr :out std_ulogic_vector(64-(dc_size-3) to 63); + + -- Barrier + cpl_fxa_ex5_set_barr :out std_ulogic_vector(0 to threads-1); + cpl_iu_set_barr_tid :out std_ulogic_vector(0 to threads-1); + + lsu_xu_ex6_datc_par_err :in std_ulogic; + + lsu_xu_ex2_dvc1_st_cmp :in std_ulogic_vector(8-(2**regmode)/8 to 7); + lsu_xu_ex2_dvc2_st_cmp :in std_ulogic_vector(8-(2**regmode)/8 to 7); + lsu_xu_ex8_dvc1_ld_cmp :in std_ulogic_vector(8-(2**regmode)/8 to 7); + lsu_xu_ex8_dvc2_ld_cmp :in std_ulogic_vector(8-(2**regmode)/8 to 7); + lsu_xu_rel_dvc1_en :in std_ulogic; + lsu_xu_rel_dvc2_en :in std_ulogic; + lsu_xu_rel_dvc_thrd_id :in std_ulogic_vector(0 to 3); + lsu_xu_rel_dvc1_cmp :in std_ulogic_vector(8-(2**regmode)/8 to 7); + lsu_xu_rel_dvc2_cmp :in std_ulogic_vector(8-(2**regmode)/8 to 7); + + lsu_xu_rot_ex6_data_b :in std_ulogic_vector(64-(2**regmode) to 63); + lsu_xu_rot_rel_data :in std_ulogic_vector(64-(2**regmode) to 63); + pc_xu_trace_bus_enable :in std_ulogic; + pc_xu_instr_trace_mode :in std_ulogic; + pc_xu_instr_trace_tid :in std_ulogic_vector(0 to 1); + iu_xu_ex4_tlb_data :in std_ulogic_vector(64-(2**regmode) to 63); + + -- Error Inject + pc_xu_inj_dcachedir_parity :in std_ulogic; + pc_xu_inj_dcachedir_multihit :in std_ulogic; + + ex4_256st_data :in std_ulogic_vector(0 to 255); + + xu_lsu_mtspr_trace_en :in std_ulogic_vector(0 to 3); + xu_lsu_spr_xucr0_aflsta :in std_ulogic; + xu_lsu_spr_xucr0_flsta :in std_ulogic; + xu_lsu_spr_xucr0_l2siw :in std_ulogic; + xu_lsu_spr_xucr0_dcdis :in std_ulogic; + xu_lsu_spr_xucr0_wlk :in std_ulogic; + xu_lsu_spr_xucr0_clfc :in std_ulogic; + xu_lsu_spr_xucr0_flh2l2 :in std_ulogic; + xu_lsu_spr_xucr0_cred :in std_ulogic; + xu_lsu_spr_xucr0_rel :in std_ulogic; + xu_lsu_spr_xucr0_mbar_ack :in std_ulogic; + xu_lsu_spr_xucr0_tlbsync :in std_ulogic; -- use sync_ack from L2 for tlbsync when 1 + xu_lsu_spr_xucr0_cls :in std_ulogic; -- Cacheline Size = 1 => 128Byte size, 0 => 64Byte size + xu_lsu_spr_ccr2_dfrat :in std_ulogic; + xu_lsu_spr_ccr2_dfratsc :in std_ulogic_vector(0 to 8); + + an_ac_flh2l2_gate :in std_ulogic; -- Gate L1 Hit forwarding SPR config bit + + -- ERAT Operations + xu_lsu_rf0_derat_val :in std_ulogic_vector(0 to 3); -- TLB Valid Operation + xu_lsu_rf0_derat_is_extload :in std_ulogic; -- Cache access should be treated as an external load + xu_lsu_rf0_derat_is_extstore :in std_ulogic; -- Cache access should be treated as an external store + xu_lsu_hid_mmu_mode :in std_ulogic; -- MMU mode + ex6_ld_par_err :in std_ulogic; + + xu_mm_derat_req :out std_ulogic; + xu_mm_derat_thdid :out std_ulogic_vector(0 to 3); + xu_mm_derat_state :out std_ulogic_vector(0 to 3); + xu_mm_derat_tid :out std_ulogic_vector(0 to 13); + xu_mm_derat_lpid :out std_ulogic_vector(0 to 7); + xu_mm_derat_ttype :out std_ulogic_vector(0 to 1); + mm_xu_derat_rel_val :in std_ulogic_vector(0 to 4); + mm_xu_derat_rel_data :in std_ulogic_vector(0 to 131); + mm_xu_derat_pid0 :in std_ulogic_vector(0 to 13); -- Thread0 PID Number + mm_xu_derat_pid1 :in std_ulogic_vector(0 to 13); -- Thread1 PID Number + mm_xu_derat_pid2 :in std_ulogic_vector(0 to 13); -- Thread2 PID Number + mm_xu_derat_pid3 :in std_ulogic_vector(0 to 13); -- Thread3 PID Number + mm_xu_derat_mmucr0_0 :in std_ulogic_vector(0 to 19); + mm_xu_derat_mmucr0_1 :in std_ulogic_vector(0 to 19); + mm_xu_derat_mmucr0_2 :in std_ulogic_vector(0 to 19); + mm_xu_derat_mmucr0_3 :in std_ulogic_vector(0 to 19); + xu_mm_derat_mmucr0 :out std_ulogic_vector(0 to 17); + xu_mm_derat_mmucr0_we :out std_ulogic_vector(0 to 3); + mm_xu_derat_mmucr1 :in std_ulogic_vector(0 to 9); + xu_mm_derat_mmucr1 :out std_ulogic_vector(0 to 4); + xu_mm_derat_mmucr1_we :out std_ulogic; + mm_xu_derat_snoop_coming :in std_ulogic; + mm_xu_derat_snoop_val :in std_ulogic; + mm_xu_derat_snoop_attr :in std_ulogic_vector(0 to 25); + mm_xu_derat_snoop_vpn :in std_ulogic_vector(64-(2**REGMODE) to 51); + xu_mm_derat_snoop_ack :out std_ulogic; + + xu_lsu_slowspr_val :in std_ulogic; + xu_lsu_slowspr_rw :in std_ulogic; + xu_lsu_slowspr_etid :in std_ulogic_vector(0 to 1); + xu_lsu_slowspr_addr :in std_ulogic_vector(0 to 9); + xu_lsu_slowspr_data :in std_ulogic_vector(64-(2**REGMODE) to 63); + xu_lsu_slowspr_done :in std_ulogic; + slowspr_val_out :out std_ulogic; + slowspr_rw_out :out std_ulogic; + slowspr_etid_out :out std_ulogic_vector(0 to 1); + slowspr_addr_out :out std_ulogic_vector(0 to 9); + slowspr_data_out :out std_ulogic_vector(64-(2**REGMODE) to 63); + slowspr_done_out :out std_ulogic; + + ex1_optype1 :out std_ulogic; + ex1_optype2 :out std_ulogic; + ex1_optype4 :out std_ulogic; + ex1_optype8 :out std_ulogic; + ex1_optype16 :out std_ulogic; + ex1_optype32 :out std_ulogic; + ex1_saxu_instr :out std_ulogic; + ex1_sdp_instr :out std_ulogic; + ex1_stgpr_instr :out std_ulogic; + ex1_store_instr :out std_ulogic; + ex1_axu_op_val :out std_ulogic; + ex3_algebraic :out std_ulogic; + ex3_data_swap :out std_ulogic; + ex3_thrd_id :out std_ulogic_vector(0 to 3); + xu_fu_ex3_eff_addr :out std_ulogic_vector(59 to 63); + xu_lsu_ici :out std_ulogic; + + -- Update Data Array Valid + rel_upd_dcarr_val :out std_ulogic; + + xu_fu_ex5_reload_val :out std_ulogic; + xu_fu_ex5_load_val :out std_ulogic_vector(0 to 3); + xu_fu_ex5_load_tag :out std_ulogic_vector(0 to 8); + + -- Data Array Controls + dcarr_up_way_addr :out std_ulogic_vector(0 to 2); + + -- SPR status + lsu_xu_spr_xucr0_cslc_xuop :out std_ulogic; -- Invalidate type instruction invalidated lock + lsu_xu_spr_xucr0_cslc_binv :out std_ulogic; -- Back-Invalidate invalidated lock + lsu_xu_spr_xucr0_clo :out std_ulogic; -- Cache Lock instruction caused an overlock + lsu_xu_spr_xucr0_cul :out std_ulogic; -- Cache Lock unable to lock + lsu_xu_spr_epsc_epr :out std_ulogic_vector(0 to 3); + lsu_xu_spr_epsc_egs :out std_ulogic_vector(0 to 3); + + -- Debug Data Compare + ex4_load_op_hit :out std_ulogic; + ex4_store_hit :out std_ulogic; + ex4_axu_op_val :out std_ulogic; + spr_dvc1_act :out std_ulogic; + spr_dvc2_act :out std_ulogic; + spr_dvc1_dbg :out std_ulogic_vector(64-(2**regmode) to 63); + spr_dvc2_dbg :out std_ulogic_vector(64-(2**regmode) to 63); + + -- Inputs from L2 + an_ac_req_ld_pop :in std_ulogic; + an_ac_req_st_pop :in std_ulogic; + an_ac_req_st_gather :in std_ulogic; + an_ac_req_st_pop_thrd :in std_ulogic_vector(0 to 2); -- decrement outbox credit count + + an_ac_reld_data_vld :in std_ulogic; + an_ac_reld_core_tag :in std_ulogic_vector(0 to 4); + an_ac_reld_qw :in std_ulogic_vector(57 to 59); + an_ac_reld_data :in std_ulogic_vector(0 to 127); + an_ac_reld_data_coming :in std_ulogic; + an_ac_reld_ditc :in std_ulogic; + an_ac_reld_crit_qw :in std_ulogic; + an_ac_reld_l1_dump :in std_ulogic; + + an_ac_reld_ecc_err :in std_ulogic; + an_ac_reld_ecc_err_ue :in std_ulogic; + + an_ac_back_inv :in std_ulogic; + an_ac_back_inv_addr :in std_ulogic_vector(64-real_data_add to 63); + an_ac_back_inv_target_bit1 :in std_ulogic; + an_ac_back_inv_target_bit3 :in std_ulogic; + an_ac_back_inv_target_bit4 :in std_ulogic; + an_ac_req_spare_ctrl_a1 :in std_ulogic_vector(0 to 3); + + xu_iu_stcx_complete : out std_ulogic_vector(0 to 3); + xu_iu_reld_core_tag_clone :out std_ulogic_vector(1 to 4); + xu_iu_reld_data_coming_clone :out std_ulogic; + xu_iu_reld_data_vld_clone :out std_ulogic; + xu_iu_reld_ditc_clone :out std_ulogic; + + + -- redrive to boxes logic + lsu_reld_data_vld :out std_ulogic; -- reload data is coming in 2 cycles + lsu_reld_core_tag :out std_ulogic_vector(3 to 4); -- reload data destinatoin tag (thread) + lsu_reld_qw :out std_ulogic_vector(58 to 59); -- reload data destinatoin tag (thread) + lsu_reld_ditc :out std_ulogic; -- reload data is for ditc (inbox) + lsu_reld_ecc_err :out std_ulogic; -- reload data has ecc error + lsu_reld_data :out std_ulogic_vector(0 to 127); -- reload data + + lsu_req_st_pop :out std_ulogic; -- decrement outbox credit count + lsu_req_st_pop_thrd :out std_ulogic_vector(0 to 2); -- decrement outbox credit count + + -- redrive for boxes logic + ac_an_reld_ditc_pop_int : in std_ulogic_vector(0 to 3); + ac_an_reld_ditc_pop_q : out std_ulogic_vector(0 to 3); + bx_ib_empty_int : in std_ulogic_vector(0 to 3); + bx_ib_empty_q : out std_ulogic_vector(0 to 3); + + -- Instruction Fetches + iu_xu_ra :in std_ulogic_vector(64-real_data_add to 59); + iu_xu_request :in std_ulogic; + iu_xu_wimge :in std_ulogic_vector(0 to 4); + iu_xu_thread :in std_ulogic_vector(0 to 3); + iu_xu_userdef :in std_ulogic_vector(0 to 3); + + -- MMU instruction interface + mm_xu_lsu_req :in std_ulogic_vector(0 to 3); + mm_xu_lsu_ttype :in std_ulogic_vector(0 to 1); + mm_xu_lsu_wimge :in std_ulogic_vector(0 to 4); + mm_xu_lsu_u :in std_ulogic_vector(0 to 3); + mm_xu_lsu_addr :in std_ulogic_vector(64-real_data_add to 63); + mm_xu_lsu_lpid :in std_ulogic_vector(0 to 7); + mm_xu_lsu_lpidr :in std_ulogic_vector(0 to 7); + mm_xu_lsu_gs :in std_ulogic; + mm_xu_lsu_ind :in std_ulogic; + mm_xu_lsu_lbit :in std_ulogic; -- "L" bit, for large vs. small + xu_mm_lsu_token :out std_ulogic; + + -- Boxes interface + bx_lsu_ob_pwr_tok :in std_ulogic; + bx_lsu_ob_req_val :in std_ulogic; -- message buff data is ready to send + bx_lsu_ob_ditc_val :in std_ulogic; -- send dtic command + bx_lsu_ob_thrd :in std_ulogic_vector(0 to 1); -- source thread + bx_lsu_ob_qw :in std_ulogic_vector(58 to 59); -- QW address + bx_lsu_ob_dest :in std_ulogic_vector(0 to 14); -- destination for the packet + bx_lsu_ob_data :in std_ulogic_vector(0 to 127); -- 16B of data from the outbox + bx_lsu_ob_addr :in std_ulogic_vector(64-real_data_add to 57); -- address for boxes message + lsu_bx_cmd_avail :out std_ulogic; + lsu_bx_cmd_sent :out std_ulogic; + lsu_bx_cmd_stall :out std_ulogic; + + lsu_xu_ldq_barr_done :out std_ulogic_vector(0 to 3); -- LWSYNC/mbar internal acknowledgements + lsu_xu_barr_done :out std_ulogic_vector(0 to 3); + + -- *** Reload operation Outputs *** + ldq_rel_data_val_early :out std_ulogic; + ldq_rel_op_size :out std_ulogic_vector(0 to 5); + ldq_rel_addr :out std_ulogic_vector(64-(dc_size-3) to 58); + ldq_rel_data_val :out std_ulogic; + ldq_rel_rot_sel :out std_ulogic_vector(0 to 4); + ldq_rel_axu_val :out std_ulogic; + ldq_rel_ci :out std_ulogic; + ldq_rel_thrd_id :out std_ulogic_vector(0 to 3); + ldq_rel_le_mode :out std_ulogic; + ldq_rel_algebraic :out std_ulogic; + ldq_rel_256_data :out std_ulogic_vector(0 to 255); + + ldq_rel_dvc1_en :out std_ulogic; + ldq_rel_dvc2_en :out std_ulogic; + ldq_rel_beat_crit_qw :out std_ulogic; + ldq_rel_beat_crit_qw_block :out std_ulogic; -- Reload Data had an ecc error + lsu_xu_rel_wren :out std_ulogic; + lsu_xu_rel_ta_gpr :out std_ulogic_vector(0 to 7); + + xu_iu_ex4_loadmiss_qentry :out std_ulogic_vector(0 to lmq_entries-1); + xu_iu_ex4_loadmiss_target :out std_ulogic_vector(0 to 8); + xu_iu_ex4_loadmiss_target_type :out std_ulogic_vector(0 to 1); + xu_iu_ex4_loadmiss_tid :out std_ulogic_vector(0 to 3); + xu_iu_ex5_loadmiss_qentry :out std_ulogic_vector(0 to lmq_entries-1); + xu_iu_ex5_loadmiss_target :out std_ulogic_vector(0 to 8); + xu_iu_ex5_loadmiss_target_type :out std_ulogic_vector(0 to 1); + xu_iu_ex5_loadmiss_tid :out std_ulogic_vector(0 to 3); + xu_iu_complete_qentry :out std_ulogic_vector(0 to lmq_entries-1); + xu_iu_complete_tid :out std_ulogic_vector(0 to 3); + xu_iu_complete_target_type :out std_ulogic_vector(0 to 1); + + -- ICBI Interface + xu_iu_ex6_icbi_val :out std_ulogic_vector(0 to 3); + xu_iu_ex6_icbi_addr :out std_ulogic_vector(64-real_data_add to 57); + + xu_iu_larx_done_tid :out std_ulogic_vector(0 to 3); + xu_mm_lmq_stq_empty :out std_ulogic; + lsu_xu_quiesce :out std_ulogic_vector(0 to 3); + lsu_xu_dbell_val :out std_ulogic; + lsu_xu_dbell_type :out std_ulogic_vector(0 to 4); + lsu_xu_dbell_brdcast :out std_ulogic; + lsu_xu_dbell_lpid_match :out std_ulogic; + lsu_xu_dbell_pirtag :out std_ulogic_vector(50 to 63); + + xu_ex1_rb :out std_ulogic_vector(64-(2**regmode) to 51); + xu_ex2_eff_addr :out std_ulogic_vector(64-(2**regmode) to 63); + + ac_an_req_pwr_token :out std_ulogic; + ac_an_req :out std_ulogic; + ac_an_req_ra :out std_ulogic_vector(64-real_data_add to 63); + ac_an_req_ttype :out std_ulogic_vector(0 to 5); + ac_an_req_thread :out std_ulogic_vector(0 to 2); + ac_an_req_wimg_w :out std_ulogic; + ac_an_req_wimg_i :out std_ulogic; + ac_an_req_wimg_m :out std_ulogic; + ac_an_req_wimg_g :out std_ulogic; + ac_an_req_endian :out std_ulogic; + ac_an_req_user_defined :out std_ulogic_vector(0 to 3); + ac_an_req_spare_ctrl_a0 :out std_ulogic_vector(0 to 3); + ac_an_req_ld_core_tag :out std_ulogic_vector(0 to 4); + ac_an_req_ld_xfr_len :out std_ulogic_vector(0 to 2); + ac_an_st_byte_enbl :out std_ulogic_vector(0 to 15+(st_data_32B_mode*16)); + ac_an_st_data :out std_ulogic_vector(0 to 127+(st_data_32B_mode*128)); + ac_an_st_data_pwr_token :out std_ulogic; + + --pervasive + xu_pc_err_dcachedir_parity :out std_ulogic; + xu_pc_err_dcachedir_multihit :out std_ulogic; + xu_pc_err_l2intrf_ecc :out std_ulogic; + xu_pc_err_l2intrf_ue :out std_ulogic; + xu_pc_err_invld_reld :out std_ulogic; + xu_pc_err_l2credit_overrun :out std_ulogic; + + -- Performance Counters + pc_xu_event_bus_enable :in std_ulogic; + pc_xu_lsu_event_mux_ctrls :in std_ulogic_vector(0 to 47); + pc_xu_cache_par_err_event :in std_ulogic; + xu_pc_lsu_event_data :out std_ulogic_vector(0 to 7); + + -- Debug Trace Bus + lsu_xu_cmd_debug :out std_ulogic_vector(0 to 175); + + -- G8T ABIST Control + an_ac_lbist_ary_wrt_thru_dc :in std_ulogic; + pc_xu_abist_g8t_wenb :in std_ulogic; + pc_xu_abist_g8t1p_renb_0 :in std_ulogic; + pc_xu_abist_g8t_bw_1 :in std_ulogic; + pc_xu_abist_g8t_bw_0 :in std_ulogic; + pc_xu_abist_wl32_comp_ena :in std_ulogic; + pc_xu_abist_g8t_dcomp :in std_ulogic_vector(0 to 3); + + vcs :inout power_logic; + vdd :inout power_logic; + gnd :inout power_logic; + nclk :in clk_logic; + an_ac_coreid :in std_ulogic_vector(6 to 7); + an_ac_atpg_en_dc :in std_ulogic; + + ccfg_scan_in :in std_ulogic; + ccfg_scan_out :out std_ulogic; + regf_scan_in :in std_ulogic_vector(0 to 6); + regf_scan_out :out std_ulogic_vector(0 to 6); + abst_scan_in :in std_ulogic; + abst_scan_out :out std_ulogic; + repr_scan_in :in std_ulogic; + repr_scan_out :out std_ulogic +); + +-- synopsys translate_off + + +-- synopsys translate_on +end xuq_ctrl; +architecture xuq_ctrl of xuq_ctrl is + +signal clkoff_dc_b_b :std_ulogic; +signal d_mode_dc_b :std_ulogic; +signal delay_lclkr_dc_b :std_ulogic_vector(0 to 4); +signal mpw1_dc_b_b :std_ulogic_vector(0 to 4); +signal mpw2_dc_b_b :std_ulogic; +signal sg_2_b :std_ulogic_vector(0 to 3); +signal fce_2_b :std_ulogic_vector(0 to 1); +signal func_sl_thold_2_b :std_ulogic_vector(0 to 3); +signal func_slp_sl_thold_2_b :std_ulogic_vector(0 to 1); +signal func_nsl_thold_2_b :std_ulogic; +signal func_slp_nsl_thold_2_b :std_ulogic; +signal time_sl_thold_2_b :std_ulogic; +signal repr_sl_thold_2_b :std_ulogic; +signal cfg_slp_sl_thold_2_b :std_ulogic; +signal regf_slp_sl_thold_2_b :std_ulogic; +signal bolt_sl_thold_2_b : std_ulogic; +signal bo_enable_2_b : std_ulogic; + +signal cam_clkoff_dc_b :std_ulogic; +signal cam_d_mode_dc :std_ulogic; +signal cam_act_dis_dc :std_ulogic; +signal cam_delay_lclkr_dc :std_ulogic_vector(0 to 4); +signal cam_mpw1_dc_b :std_ulogic_vector(0 to 4); +signal cam_mpw2_dc_b :std_ulogic; +signal xu_lsu_rf0_act :std_ulogic; +signal xu_lsu_rf1_cache_acc :std_ulogic; +signal xu_lsu_rf1_thrd_id :std_ulogic_vector(0 to threads-1); +signal xu_lsu_rf1_optype1 :std_ulogic; +signal xu_lsu_rf1_optype2 :std_ulogic; +signal xu_lsu_rf1_optype4 :std_ulogic; +signal xu_lsu_rf1_optype8 :std_ulogic; +signal xu_lsu_rf1_optype16 :std_ulogic; +signal xu_lsu_rf1_optype32 :std_ulogic; +signal xu_lsu_rf1_target_gpr :std_ulogic_vector(0 to 8); +signal xu_lsu_rf1_load_instr :std_ulogic; +signal xu_lsu_rf1_store_instr :std_ulogic; +signal xu_lsu_rf1_dcbf_instr :std_ulogic; +signal xu_lsu_rf1_sync_instr :std_ulogic; +signal xu_lsu_rf1_mbar_instr :std_ulogic; +signal xu_lsu_rf1_l_fld :std_ulogic_vector(0 to 1); +signal xu_lsu_rf1_dcbi_instr :std_ulogic; +signal xu_lsu_rf1_dcbz_instr :std_ulogic; +signal xu_lsu_rf1_dcbt_instr :std_ulogic; +signal xu_lsu_rf1_dcbtst_instr :std_ulogic; +signal xu_lsu_rf1_th_fld :std_ulogic_vector(0 to 4); +signal xu_lsu_rf1_dcbtls_instr :std_ulogic; +signal xu_lsu_rf1_dcbtstls_instr :std_ulogic; +signal xu_lsu_rf1_dcblc_instr :std_ulogic; +signal xu_lsu_rf1_dcbst_instr :std_ulogic; +signal xu_lsu_rf1_icbi_instr :std_ulogic; +signal xu_lsu_rf1_icblc_instr :std_ulogic; +signal xu_lsu_rf1_icbt_instr :std_ulogic; +signal xu_lsu_rf1_icbtls_instr :std_ulogic; +signal xu_lsu_rf1_tlbsync_instr :std_ulogic; +signal xu_lsu_rf1_lock_instr :std_ulogic; +signal xu_lsu_rf1_mutex_hint :std_ulogic; +signal xu_lsu_rf1_axu_op_val :std_ulogic; +signal xu_lsu_rf1_axu_ldst_falign_int :std_ulogic; +signal xu_lsu_rf1_axu_ldst_fexcpt :std_ulogic; +signal xu_lsu_rf1_algebraic :std_ulogic; +signal xu_lsu_rf1_byte_rev :std_ulogic; +signal xu_lsu_rf1_src_gpr :std_ulogic; +signal xu_lsu_rf1_src_axu :std_ulogic; +signal xu_lsu_rf1_src_dp :std_ulogic; +signal xu_lsu_rf1_targ_gpr :std_ulogic; +signal xu_lsu_rf1_targ_axu :std_ulogic; +signal xu_lsu_rf1_targ_dp :std_ulogic; +signal xu_lsu_ex4_val :std_ulogic_vector(0 to 3); -- There is a valid Instruction in EX4 +signal xu_lsu_rf1_derat_act :std_ulogic; +signal xu_lsu_rf1_derat_is_load :std_ulogic; +signal xu_lsu_rf1_derat_is_store :std_ulogic; +signal xu_lsu_rf1_src0_vld :std_ulogic; +signal xu_lsu_rf1_src0_reg :std_ulogic_vector(0 to 7); +signal xu_lsu_rf1_src1_vld :std_ulogic; +signal xu_lsu_rf1_src1_reg :std_ulogic_vector(0 to 7); +signal xu_lsu_rf1_targ_vld :std_ulogic; +signal xu_lsu_rf1_targ_reg :std_ulogic_vector(0 to 7); +signal xu_lsu_rf1_is_touch :std_ulogic; +signal xu_lsu_rf1_is_msgsnd :std_ulogic; +signal xu_lsu_rf1_dci_instr :std_ulogic; +signal xu_lsu_rf1_ici_instr :std_ulogic; +signal xu_lsu_rf1_icswx_instr :std_ulogic; +signal xu_lsu_rf1_icswx_dot_instr :std_ulogic; +signal xu_lsu_rf1_icswx_epid :std_ulogic; +signal xu_lsu_rf1_ldawx_instr :std_ulogic; +signal xu_lsu_rf1_wclr_instr :std_ulogic; +signal xu_lsu_rf1_wchk_instr :std_ulogic; +signal xu_lsu_rf1_derat_ra_eq_ea :std_ulogic; +signal xu_lsu_rf1_cmd_act :std_ulogic; +signal xu_lsu_rf1_mtspr_trace :std_ulogic; +signal lsu_xu_ex5_wren :std_ulogic; -- FXU Load Hit Write is Valid in EX5 +signal lsu_xu_rel_wren_int :std_ulogic; -- FXU Reload is Valid +signal lsu_xu_rel_ta_gpr_int :std_ulogic_vector(0 to 7); -- FXU Reload Target Register +signal xu_lsu_ex4_dvc1_en :std_ulogic; +signal xu_lsu_ex4_dvc2_en :std_ulogic; +signal xu_lsu_ex1_add_src0 :std_ulogic_vector(64-regsize to 63); +signal xu_lsu_ex1_add_src1 :std_ulogic_vector(64-regsize to 63); +signal xu_rf1_is_eratre_int :std_ulogic; +signal xu_rf1_is_eratwe_int :std_ulogic; +signal xu_rf1_is_eratsx_int :std_ulogic; +signal xu_rf1_is_eratsrx_int :std_ulogic; +signal xu_rf1_is_eratilx_int :std_ulogic; +signal xu_rf1_is_erativax_int :std_ulogic; +signal xu_ex1_is_isync_int :std_ulogic; +signal xu_ex1_is_csync_int :std_ulogic; +signal xu_rf1_ws_int :std_ulogic_vector(0 to 1); +signal xu_rf1_t_int :std_ulogic_vector(0 to 2); +signal xu_ex1_rs_is_int :std_ulogic_vector(0 to 8); +signal xu_ex1_ra_entry_int :std_ulogic_vector(7 to 11); +signal lsu_xu_ex4_tlb_data :std_ulogic_vector(64-(2**regmode) to 63); +signal lsu_xu_is2_back_inv :std_ulogic; +signal lsu_xu_is2_back_inv_addr :std_ulogic_vector(64-real_data_add to 63-cl_size); +signal lsu_xu_ex4_cr_upd :std_ulogic; +signal lsu_xu_ex5_cr_rslt :std_ulogic; +signal lsu_xu_ex3_derat_par_err :std_ulogic_vector(0 to threads-1); +signal lsu_xu_ex3_derat_multihit_err :std_ulogic_vector(0 to threads-1); +signal lsu_xu_ex3_l2_uc_ecc_err :std_ulogic_vector(0 to 3); +signal lsu_xu_ex3_ddir_par_err :std_ulogic; +signal lsu_xu_ex4_n_lsu_ddmh_flush :std_ulogic_vector(0 to threads-1); +signal lsu_xu_ex3_dsi :std_ulogic_vector(0 to threads-1); +signal derat_xu_ex3_dsi :std_ulogic_vector(0 to threads-1); +signal lsu_xu_ex3_align :std_ulogic_vector(0 to threads-1); +signal derat_xu_ex3_miss :std_ulogic_vector(0 to threads-1); +signal lsu_xu_l2_ecc_err_flush :std_ulogic_vector(0 to threads-1); +signal lsu_xu_datc_perr_recovery :std_ulogic; +signal lsu_xu_ex3_dep_flush :std_ulogic; +signal lsu_xu_ex3_n_flush_req :std_ulogic; +signal lsu_xu_ex3_ldq_hit_flush :std_ulogic; +signal lsu_xu_ex4_ldq_full_flush :std_ulogic; +signal derat_xu_ex3_n_flush_req :std_ulogic_vector(0 to threads-1); +signal lsu_xu_ex3_inval_align_2ucode :std_ulogic; +signal lsu_xu_ex3_attr :std_ulogic_vector(0 to 8); +signal lsu_xu_ex3_derat_vf :std_ulogic; +signal xu_lsu_ex4_flush_local_int :std_ulogic_vector(0 to 3); -- EX4 flush (comes very LATE in the cycle) +signal xu_lsu_dci :std_ulogic; +signal xu_rf0_flush :std_ulogic_vector(0 to threads-1); +signal xu_rf1_flush :std_ulogic_vector(0 to threads-1); +signal xu_ex1_flush :std_ulogic_vector(0 to threads-1); +signal xu_ex2_flush :std_ulogic_vector(0 to threads-1); +signal xu_ex3_flush :std_ulogic_vector(0 to threads-1); +signal xu_ex4_flush :std_ulogic_vector(0 to threads-1); +signal bcfg_scan_out_int :std_ulogic; +signal ccfg_scan_out_int :std_ulogic; +signal dcfg_scan_out_int :std_ulogic; +signal xu_ex4_rs_data_int :std_ulogic_vector(64-(2**regmode) to 63); +signal xu_lsu_ex5_set_barr :std_ulogic_vector(0 to threads-1); +signal xu_ex1_eff_addr_int :std_ulogic_vector(64-(dc_size-3) to 63); +signal lsu_xu_ex4_derat_par_err :std_ulogic_vector(0 to 3); +signal fxu_trigger_data_in :std_ulogic_vector(0 to 11); +signal fxu_debug_data_in :std_ulogic_vector(0 to 87); +signal fxu_trigger_data_out :std_ulogic_vector(0 to 11); +signal fxu_debug_data_out :std_ulogic_vector(0 to 87); +signal cpl_debug_data_in :std_ulogic_vector(0 to 87); +signal cpl_debug_data_out :std_ulogic_vector(0 to 87); +signal cpl_trigger_data_in :std_ulogic_vector(0 to 11); +signal cpl_trigger_data_out :std_ulogic_vector(0 to 11); +signal lsu_trigger_data_in :std_ulogic_vector(0 to 11); +signal lsu_debug_data_in :std_ulogic_vector(0 to 87); +signal lsu_trigger_data_out :std_ulogic_vector(0 to 11); +signal lsu_debug_data_out :std_ulogic_vector(0 to 87); +signal ary_slp_nsl_thold_2 :std_ulogic; +signal abst_slp_sl_thold_2 :std_ulogic; +signal xu_n_ex5_flush_int :std_ulogic_vector(0 to threads-1); +signal lsu_xu_need_hole :std_ulogic; +signal xu_lsu_ex2_instr_trace_val :std_ulogic; +signal g8t_clkoff_dc_b :std_ulogic; +signal g8t_d_mode_dc :std_ulogic; +signal g8t_delay_lclkr_dc :std_ulogic_vector(0 to 4); +signal g8t_mpw1_dc_b :std_ulogic_vector(0 to 4); +signal g8t_mpw2_dc_b :std_ulogic; +signal spr_xucr4_mmu_mchk_int :std_ulogic; + + +begin + +xu_n_ex5_flush <= xu_n_ex5_flush_int; +spr_xucr4_mmu_mchk <= spr_xucr4_mmu_mchk_int; + +-- DEBUG BUS CHAINS +fxu_trigger_data_in <= ctrl_trigger_data_in; +fxu_debug_data_in <= ctrl_debug_data_in; +cpl_debug_data_in <= fxu_debug_data_out; +cpl_trigger_data_in <= fxu_trigger_data_out; +lsu_debug_data_in <= cpl_debug_data_out; +lsu_trigger_data_in <= cpl_trigger_data_out; +ctrl_debug_data_out <= lsu_debug_data_out; +ctrl_trigger_data_out<= lsu_trigger_data_out; + +clkoff_dc_b <= clkoff_dc_b_b; +d_mode_dc <= d_mode_dc_b; +delay_lclkr_dc <= delay_lclkr_dc_b; +mpw1_dc_b <= mpw1_dc_b_b; +mpw2_dc_b <= mpw2_dc_b_b; +sg_2 <= sg_2_b; +fce_2 <= fce_2_b; +func_sl_thold_2 <= func_sl_thold_2_b; +func_slp_sl_thold_2 <= func_slp_sl_thold_2_b; +func_nsl_thold_2 <= func_nsl_thold_2_b; +func_slp_nsl_thold_2 <= func_slp_nsl_thold_2_b; +time_sl_thold_2 <= time_sl_thold_2_b; +repr_sl_thold_2 <= repr_sl_thold_2_b; +cfg_slp_sl_thold_2 <= cfg_slp_sl_thold_2_b; +regf_slp_sl_thold_2 <= regf_slp_sl_thold_2_b; +bolt_sl_thold_2 <= bolt_sl_thold_2_b; +bo_enable_2 <= bo_enable_2_b; + + xuq_cpl_fxub : entity work.xuq_cpl_fxub(xuq_cpl_fxub) + generic map( + expand_type => expand_type, + threads => threads, + eff_ifar => eff_ifar, + regmode => regmode, + regsize => regsize, + hvmode => hvmode, + dc_size => dc_size, + cl_size => cl_size, + real_data_add => real_data_add, + uc_ifar => uc_ifar, + fxu_synth => fxu_synth, + a2mode => a2mode) + port map( + --------------------------------------------------------------------- + -- Clocks & Power + --------------------------------------------------------------------- + nclk => nclk, + vdd => vdd, + gnd => gnd, + vcs => vcs, + + --------------------------------------------------------------------- + -- Pervasive + --------------------------------------------------------------------- + func_scan_in => func_scan_in(50 to 58), + func_scan_out => func_scan_out(50 to 58), + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b, + pc_xu_ccflush_dc => pc_xu_ccflush_dc, + clkoff_dc_b => clkoff_dc_b_b, + d_mode_dc => d_mode_dc_b, + delay_lclkr_dc => delay_lclkr_dc_b, + mpw1_dc_b => mpw1_dc_b_b, + mpw2_dc_b => mpw2_dc_b_b, + g6t_clkoff_dc_b => g6t_clkoff_dc_b, + g6t_d_mode_dc => g6t_d_mode_dc, + g6t_delay_lclkr_dc => g6t_delay_lclkr_dc, + g6t_mpw1_dc_b => g6t_mpw1_dc_b, + g6t_mpw2_dc_b => g6t_mpw2_dc_b, + g8t_clkoff_dc_b => g8t_clkoff_dc_b, + g8t_d_mode_dc => g8t_d_mode_dc, + g8t_delay_lclkr_dc => g8t_delay_lclkr_dc, + g8t_mpw1_dc_b => g8t_mpw1_dc_b, + g8t_mpw2_dc_b => g8t_mpw2_dc_b, + cam_clkoff_dc_b => cam_clkoff_dc_b, + cam_d_mode_dc => cam_d_mode_dc, + cam_delay_lclkr_dc => cam_delay_lclkr_dc, + cam_act_dis_dc => cam_act_dis_dc, + cam_mpw1_dc_b => cam_mpw1_dc_b, + cam_mpw2_dc_b => cam_mpw2_dc_b, + pc_xu_sg_3 => pc_xu_sg_3, + pc_xu_func_sl_thold_3 => pc_xu_func_sl_thold_3, + pc_xu_func_slp_sl_thold_3 => pc_xu_func_slp_sl_thold_3, + pc_xu_func_nsl_thold_3 => pc_xu_func_nsl_thold_3, + pc_xu_func_slp_nsl_thold_3 => pc_xu_func_slp_nsl_thold_3, + pc_xu_gptr_sl_thold_3 => pc_xu_gptr_sl_thold_3, + pc_xu_abst_sl_thold_3 => pc_xu_abst_sl_thold_3, + pc_xu_abst_slp_sl_thold_3 => pc_xu_abst_slp_sl_thold_3, + pc_xu_regf_sl_thold_3 => pc_xu_regf_sl_thold_3, + pc_xu_regf_slp_sl_thold_3 => pc_xu_regf_slp_sl_thold_3, + pc_xu_time_sl_thold_3 => pc_xu_time_sl_thold_3, + pc_xu_cfg_sl_thold_3 => pc_xu_cfg_sl_thold_3, + pc_xu_cfg_slp_sl_thold_3 => pc_xu_cfg_slp_sl_thold_3, + pc_xu_ary_nsl_thold_3 => pc_xu_ary_nsl_thold_3, + pc_xu_ary_slp_nsl_thold_3 => pc_xu_ary_slp_nsl_thold_3, + pc_xu_repr_sl_thold_3 => pc_xu_repr_sl_thold_3, + pc_xu_fce_3 => pc_xu_fce_3, + pc_xu_bolt_sl_thold_3 => pc_xu_bolt_sl_thold_3, + pc_xu_bo_enable_3 => pc_xu_bo_enable_3, + bolt_sl_thold_2 => bolt_sl_thold_2_b, + bo_enable_2 => bo_enable_2_b, + an_ac_scan_diag_dc => an_ac_scan_diag_dc, + sg_2 => sg_2_b, + fce_2 => fce_2_b, + func_sl_thold_2 => func_sl_thold_2_b, + func_slp_sl_thold_2 => func_slp_sl_thold_2_b, + func_nsl_thold_2 => func_nsl_thold_2_b, + func_slp_nsl_thold_2 => func_slp_nsl_thold_2_b, + abst_sl_thold_2 => abst_sl_thold_2, + abst_slp_sl_thold_2 => abst_slp_sl_thold_2, + time_sl_thold_2 => time_sl_thold_2_b, + gptr_sl_thold_2 => gptr_sl_thold_2, + ary_nsl_thold_2 => ary_nsl_thold_2, + ary_slp_nsl_thold_2 => ary_slp_nsl_thold_2, + repr_sl_thold_2 => repr_sl_thold_2_b, + cfg_sl_thold_2 => cfg_sl_thold_2, + cfg_slp_sl_thold_2 => cfg_slp_sl_thold_2_b, + regf_slp_sl_thold_2 => regf_slp_sl_thold_2_b, + gptr_scan_in => gptr_scan_in, + gptr_scan_out => gptr_scan_out, + fxa_fxb_rf0_val => fxa_fxb_rf0_val, + fxa_fxb_rf0_issued => fxa_fxb_rf0_issued, + fxa_fxb_rf0_ucode_val => fxa_fxb_rf0_ucode_val, + fxa_fxb_rf0_act => fxa_fxb_rf0_act, + fxa_fxb_ex1_hold_ctr_flush => fxa_fxb_ex1_hold_ctr_flush, + fxa_fxb_rf0_instr => fxa_fxb_rf0_instr, + fxa_fxb_rf0_tid => fxa_fxb_rf0_tid, + fxa_fxb_rf0_ta_vld => fxa_fxb_rf0_ta_vld, + fxa_fxb_rf0_ta => fxa_fxb_rf0_ta, + fxa_fxb_rf0_error => fxa_fxb_rf0_error, + fxa_fxb_rf0_match => fxa_fxb_rf0_match, + fxa_fxb_rf0_is_ucode => fxa_fxb_rf0_is_ucode, + fxa_fxb_rf0_gshare => fxa_fxb_rf0_gshare, + fxa_fxb_rf0_ifar => fxa_fxb_rf0_ifar, + fxa_fxb_rf0_s1_vld => fxa_fxb_rf0_s1_vld, + fxa_fxb_rf0_s1 => fxa_fxb_rf0_s1, + fxa_fxb_rf0_s2_vld => fxa_fxb_rf0_s2_vld, + fxa_fxb_rf0_s2 => fxa_fxb_rf0_s2, + fxa_fxb_rf0_s3_vld => fxa_fxb_rf0_s3_vld, + fxa_fxb_rf0_s3 => fxa_fxb_rf0_s3, + fxa_fxb_rf0_axu_instr_type => fxa_fxb_rf0_axu_instr_type, + fxa_fxb_rf0_axu_ld_or_st => fxa_fxb_rf0_axu_ld_or_st, + fxa_fxb_rf0_axu_store => fxa_fxb_rf0_axu_store, + fxa_fxb_rf0_axu_ldst_forcealign => fxa_fxb_rf0_axu_ldst_forcealign, + fxa_fxb_rf0_axu_ldst_forceexcept => fxa_fxb_rf0_axu_ldst_forceexcept, + fxa_fxb_rf0_axu_ldst_indexed => fxa_fxb_rf0_axu_ldst_indexed, + fxa_fxb_rf0_axu_ldst_tag => fxa_fxb_rf0_axu_ldst_tag, + fxa_fxb_rf0_axu_mftgpr => fxa_fxb_rf0_axu_mftgpr, + fxa_fxb_rf0_axu_mffgpr => fxa_fxb_rf0_axu_mffgpr, + fxa_fxb_rf0_axu_movedp => fxa_fxb_rf0_axu_movedp, + fxa_fxb_rf0_axu_ldst_size => fxa_fxb_rf0_axu_ldst_size, + fxa_fxb_rf0_axu_ldst_update => fxa_fxb_rf0_axu_ldst_update, + fxa_fxb_rf0_pred_update => fxa_fxb_rf0_pred_update, + fxa_fxb_rf0_pred_taken_cnt => fxa_fxb_rf0_pred_taken_cnt, + fxa_fxb_rf0_mc_dep_chk_val => fxa_fxb_rf0_mc_dep_chk_val, + fxa_fxb_rf1_mul_val => fxa_fxb_rf1_mul_val, + fxa_fxb_rf1_div_val => fxa_fxb_rf1_div_val, + fxa_fxb_rf1_div_ctr => fxa_fxb_rf1_div_ctr, + fxa_fxb_rf0_xu_epid_instr => fxa_fxb_rf0_xu_epid_instr, + fxa_fxb_rf0_axu_is_extload => fxa_fxb_rf0_axu_is_extload, + fxa_fxb_rf0_axu_is_extstore => fxa_fxb_rf0_axu_is_extstore, + fxa_fxb_rf0_is_mfocrf => fxa_fxb_rf0_is_mfocrf, + fxa_fxb_rf0_3src_instr => fxa_fxb_rf0_3src_instr, + fxa_fxb_rf0_gpr0_zero => fxa_fxb_rf0_gpr0_zero, + fxa_fxb_rf0_use_imm => fxa_fxb_rf0_use_imm, + fxa_fxb_rf1_muldiv_coll => fxa_fxb_rf1_muldiv_coll, + fxa_cpl_ex2_div_coll => fxa_cpl_ex2_div_coll, + fxb_fxa_ex7_we0 => fxb_fxa_ex7_we0, + fxb_fxa_ex7_wa0 => fxb_fxa_ex7_wa0, + fxb_fxa_ex7_wd0 => fxb_fxa_ex7_wd0, + fxa_fxb_rf1_do0 => fxa_fxb_rf1_do0, + fxa_fxb_rf1_do1 => fxa_fxb_rf1_do1, + fxa_fxb_rf1_do2 => fxa_fxb_rf1_do2, + xu_lsu_rf0_act => xu_lsu_rf0_act, + xu_lsu_rf1_cache_acc => xu_lsu_rf1_cache_acc, + xu_lsu_rf1_thrd_id => xu_lsu_rf1_thrd_id, + xu_lsu_rf1_optype1 => xu_lsu_rf1_optype1, + xu_lsu_rf1_optype2 => xu_lsu_rf1_optype2, + xu_lsu_rf1_optype4 => xu_lsu_rf1_optype4, + xu_lsu_rf1_optype8 => xu_lsu_rf1_optype8, + xu_lsu_rf1_optype16 => xu_lsu_rf1_optype16, + xu_lsu_rf1_optype32 => xu_lsu_rf1_optype32, + xu_lsu_rf1_target_gpr => xu_lsu_rf1_target_gpr, + xu_lsu_rf1_load_instr => xu_lsu_rf1_load_instr, + xu_lsu_rf1_store_instr => xu_lsu_rf1_store_instr, + xu_lsu_rf1_dcbf_instr => xu_lsu_rf1_dcbf_instr, + xu_lsu_rf1_sync_instr => xu_lsu_rf1_sync_instr, + xu_lsu_rf1_mbar_instr => xu_lsu_rf1_mbar_instr, + xu_lsu_rf1_l_fld => xu_lsu_rf1_l_fld, + xu_lsu_rf1_dcbi_instr => xu_lsu_rf1_dcbi_instr, + xu_lsu_rf1_dcbz_instr => xu_lsu_rf1_dcbz_instr, + xu_lsu_rf1_dcbt_instr => xu_lsu_rf1_dcbt_instr, + xu_lsu_rf1_dcbtst_instr => xu_lsu_rf1_dcbtst_instr, + xu_lsu_rf1_th_fld => xu_lsu_rf1_th_fld, + xu_lsu_rf1_dcbtls_instr => xu_lsu_rf1_dcbtls_instr, + xu_lsu_rf1_dcbtstls_instr => xu_lsu_rf1_dcbtstls_instr, + xu_lsu_rf1_dcblc_instr => xu_lsu_rf1_dcblc_instr, + xu_lsu_rf1_dcbst_instr => xu_lsu_rf1_dcbst_instr, + xu_lsu_rf1_icbi_instr => xu_lsu_rf1_icbi_instr, + xu_lsu_rf1_icblc_instr => xu_lsu_rf1_icblc_instr, + xu_lsu_rf1_icbt_instr => xu_lsu_rf1_icbt_instr, + xu_lsu_rf1_icbtls_instr => xu_lsu_rf1_icbtls_instr, + xu_lsu_rf1_tlbsync_instr => xu_lsu_rf1_tlbsync_instr, + xu_lsu_rf1_lock_instr => xu_lsu_rf1_lock_instr, + xu_lsu_rf1_mutex_hint => xu_lsu_rf1_mutex_hint, + xu_lsu_rf1_axu_op_val => xu_lsu_rf1_axu_op_val, + xu_lsu_rf1_axu_ldst_falign => xu_lsu_rf1_axu_ldst_falign_int, + xu_lsu_rf1_axu_ldst_fexcpt => xu_lsu_rf1_axu_ldst_fexcpt, + xu_lsu_ex1_store_data => xu_lsu_ex1_store_data, + xu_lsu_rf1_algebraic => xu_lsu_rf1_algebraic, + xu_lsu_rf1_byte_rev => xu_lsu_rf1_byte_rev, + xu_lsu_rf1_src_gpr => xu_lsu_rf1_src_gpr, + xu_lsu_rf1_src_axu => xu_lsu_rf1_src_axu, + xu_lsu_rf1_src_dp => xu_lsu_rf1_src_dp, + xu_lsu_rf1_targ_gpr => xu_lsu_rf1_targ_gpr, + xu_lsu_rf1_targ_axu => xu_lsu_rf1_targ_axu, + xu_lsu_rf1_targ_dp => xu_lsu_rf1_targ_dp, + xu_lsu_ex4_val => xu_lsu_ex4_val, + xu_lsu_ex1_rotsel_ovrd => xu_lsu_ex1_rotsel_ovrd, + xu_lsu_rf1_derat_act => xu_lsu_rf1_derat_act, + xu_lsu_rf1_derat_is_load => xu_lsu_rf1_derat_is_load, + xu_lsu_rf1_derat_is_store => xu_lsu_rf1_derat_is_store, + xu_lsu_rf1_src0_vld => xu_lsu_rf1_src0_vld, + xu_lsu_rf1_src0_reg => xu_lsu_rf1_src0_reg, + xu_lsu_rf1_src1_vld => xu_lsu_rf1_src1_vld, + xu_lsu_rf1_src1_reg => xu_lsu_rf1_src1_reg, + xu_lsu_rf1_targ_vld => xu_lsu_rf1_targ_vld, + xu_lsu_rf1_targ_reg => xu_lsu_rf1_targ_reg, + xu_bx_ex1_mtdp_val => xu_bx_ex1_mtdp_val, + xu_bx_ex1_mfdp_val => xu_bx_ex1_mfdp_val, + xu_bx_ex1_ipc_thrd => xu_bx_ex1_ipc_thrd, + xu_bx_ex2_ipc_ba => xu_bx_ex2_ipc_ba, + xu_bx_ex2_ipc_sz => xu_bx_ex2_ipc_sz, + xu_lsu_rf1_is_touch => xu_lsu_rf1_is_touch, + xu_lsu_rf1_is_msgsnd => xu_lsu_rf1_is_msgsnd, + xu_lsu_rf1_dci_instr => xu_lsu_rf1_dci_instr, + xu_lsu_rf1_ici_instr => xu_lsu_rf1_ici_instr, + xu_lsu_rf1_icswx_instr => xu_lsu_rf1_icswx_instr, + xu_lsu_rf1_icswx_dot_instr => xu_lsu_rf1_icswx_dot_instr, + xu_lsu_rf1_icswx_epid => xu_lsu_rf1_icswx_epid, + xu_lsu_rf1_ldawx_instr => xu_lsu_rf1_ldawx_instr, + xu_lsu_rf1_wclr_instr => xu_lsu_rf1_wclr_instr, + xu_lsu_rf1_wchk_instr => xu_lsu_rf1_wchk_instr, + xu_lsu_rf1_derat_ra_eq_ea => xu_lsu_rf1_derat_ra_eq_ea, + xu_lsu_rf1_cmd_act => xu_lsu_rf1_cmd_act, + xu_lsu_rf1_data_act => xu_lsu_rf1_data_act, + xu_lsu_rf1_mtspr_trace => xu_lsu_rf1_mtspr_trace, + lsu_xu_ex5_wren => lsu_xu_ex5_wren, + lsu_xu_rel_wren => lsu_xu_rel_wren_int, + lsu_xu_rel_ta_gpr => lsu_xu_rel_ta_gpr_int, + lsu_xu_need_hole => lsu_xu_need_hole, + lsu_xu_rot_ex6_data_b => lsu_xu_rot_ex6_data_b, + lsu_xu_rot_rel_data => lsu_xu_rot_rel_data, + xu_lsu_ex4_dvc1_en => xu_lsu_ex4_dvc1_en, + xu_lsu_ex4_dvc2_en => xu_lsu_ex4_dvc2_en, + lsu_xu_ex2_dvc1_st_cmp => lsu_xu_ex2_dvc1_st_cmp, + lsu_xu_ex2_dvc2_st_cmp => lsu_xu_ex2_dvc2_st_cmp, + lsu_xu_ex8_dvc1_ld_cmp => lsu_xu_ex8_dvc1_ld_cmp, + lsu_xu_ex8_dvc2_ld_cmp => lsu_xu_ex8_dvc2_ld_cmp, + lsu_xu_rel_dvc1_en => lsu_xu_rel_dvc1_en, + lsu_xu_rel_dvc2_en => lsu_xu_rel_dvc2_en, + lsu_xu_rel_dvc_thrd_id => lsu_xu_rel_dvc_thrd_id, + lsu_xu_rel_dvc1_cmp => lsu_xu_rel_dvc1_cmp, + lsu_xu_rel_dvc2_cmp => lsu_xu_rel_dvc2_cmp, + xu_lsu_ex1_add_src0 => xu_lsu_ex1_add_src0, + xu_lsu_ex1_add_src1 => xu_lsu_ex1_add_src1, + xu_ex1_eff_addr_int => xu_ex1_eff_addr_int, + -- Barrier + xu_lsu_ex5_set_barr => xu_lsu_ex5_set_barr, + cpl_fxa_ex5_set_barr => cpl_fxa_ex5_set_barr, + cpl_iu_set_barr_tid => cpl_iu_set_barr_tid, + xu_iu_rf1_val => xu_iu_rf1_val, + xu_rf1_val => xu_rf1_val, + xu_rf1_is_tlbre => xu_rf1_is_tlbre, + xu_rf1_is_tlbwe => xu_rf1_is_tlbwe, + xu_rf1_is_tlbsx => xu_rf1_is_tlbsx, + xu_rf1_is_tlbsrx => xu_rf1_is_tlbsrx, + xu_rf1_is_tlbilx => xu_rf1_is_tlbilx, + xu_rf1_is_tlbivax => xu_rf1_is_tlbivax, + xu_rf1_is_eratre => xu_rf1_is_eratre_int, + xu_rf1_is_eratwe => xu_rf1_is_eratwe_int, + xu_rf1_is_eratsx => xu_rf1_is_eratsx_int, + xu_rf1_is_eratsrx => xu_rf1_is_eratsrx_int, + xu_rf1_is_eratilx => xu_rf1_is_eratilx_int, + xu_rf1_is_erativax => xu_rf1_is_erativax_int, + xu_ex1_is_isync => xu_ex1_is_isync_int, + xu_ex1_is_csync => xu_ex1_is_csync_int, + xu_rf1_ws => xu_rf1_ws_int, + xu_rf1_t => xu_rf1_t_int, + xu_ex1_rs_is => xu_ex1_rs_is_int, + xu_ex1_ra_entry => xu_ex1_ra_entry_int, + xu_ex1_rb => xu_ex1_rb, + xu_ex2_eff_addr => xu_ex2_eff_addr, + xu_ex4_rs_data => xu_ex4_rs_data_int, + lsu_xu_ex4_tlb_data => lsu_xu_ex4_tlb_data, + iu_xu_ex4_tlb_data => iu_xu_ex4_tlb_data, + xu_mm_derat_epn => xu_mm_derat_epn, + lsu_xu_is2_back_inv => lsu_xu_is2_back_inv, + lsu_xu_is2_back_inv_addr => lsu_xu_is2_back_inv_addr, + mm_xu_mmucr0_0_tlbsel => mm_xu_derat_mmucr0_0(4 to 5), + mm_xu_mmucr0_1_tlbsel => mm_xu_derat_mmucr0_1(4 to 5), + mm_xu_mmucr0_2_tlbsel => mm_xu_derat_mmucr0_2(4 to 5), + mm_xu_mmucr0_3_tlbsel => mm_xu_derat_mmucr0_3(4 to 5), + xu_mm_rf1_is_tlbsxr => xu_mm_rf1_is_tlbsxr, + mm_xu_cr0_eq_valid => mm_xu_cr0_eq_valid, + mm_xu_cr0_eq => mm_xu_cr0_eq, + fu_xu_ex4_cr_val => fu_xu_ex4_cr_val, + fu_xu_ex4_cr_noflush => fu_xu_ex4_cr_noflush, + fu_xu_ex4_cr0 => fu_xu_ex4_cr0, + fu_xu_ex4_cr0_bf => fu_xu_ex4_cr0_bf, + fu_xu_ex4_cr1 => fu_xu_ex4_cr1, + fu_xu_ex4_cr1_bf => fu_xu_ex4_cr1_bf, + fu_xu_ex4_cr2 => fu_xu_ex4_cr2, + fu_xu_ex4_cr2_bf => fu_xu_ex4_cr2_bf, + fu_xu_ex4_cr3 => fu_xu_ex4_cr3, + fu_xu_ex4_cr3_bf => fu_xu_ex4_cr3_bf, + xu_pc_ram_data => xu_pc_ram_data, + xu_iu_ex5_val => xu_iu_ex5_val, + xu_iu_ex5_tid => xu_iu_ex5_tid, + xu_iu_ex5_br_update => xu_iu_ex5_br_update, + xu_iu_ex5_br_hist => xu_iu_ex5_br_hist, + xu_iu_ex5_bclr => xu_iu_ex5_bclr, + xu_iu_ex5_lk => xu_iu_ex5_lk, + xu_iu_ex5_bh => xu_iu_ex5_bh, + xu_iu_ex6_pri => xu_iu_ex6_pri, + xu_iu_ex6_pri_val => xu_iu_ex6_pri_val, + xu_iu_spr_xer => xu_iu_spr_xer, + xu_iu_slowspr_done => xu_iu_slowspr_done, + xu_iu_need_hole => xu_iu_need_hole, + fxb_fxa_ex6_clear_barrier => fxb_fxa_ex6_clear_barrier, + xu_iu_ex5_gshare => xu_iu_ex5_gshare, + xu_iu_ex5_getNIA => xu_iu_ex5_getNIA, + an_ac_stcx_complete => an_ac_stcx_complete, + an_ac_stcx_pass => an_ac_stcx_pass, + + an_ac_back_inv => an_ac_back_inv, + an_ac_back_inv_addr => an_ac_back_inv_addr(58 to 63), + an_ac_back_inv_target_bit3 => an_ac_back_inv_target_bit3, + slowspr_val_in => slowspr_val_in, + slowspr_rw_in => slowspr_rw_in, + slowspr_etid_in => slowspr_etid_in, + slowspr_addr_in => slowspr_addr_in, + slowspr_data_in => slowspr_data_in, + slowspr_done_in => slowspr_done_in, + an_ac_dcr_act => an_ac_dcr_act, + an_ac_dcr_val => an_ac_dcr_val, + an_ac_dcr_read => an_ac_dcr_read, + an_ac_dcr_etid => an_ac_dcr_etid, + an_ac_dcr_data => an_ac_dcr_data, + an_ac_dcr_done => an_ac_dcr_done, + lsu_xu_ex4_mtdp_cr_status => lsu_xu_ex4_mtdp_cr_status, + lsu_xu_ex4_mfdp_cr_status => lsu_xu_ex4_mfdp_cr_status, + dec_cpl_ex3_mc_dep_chk_val => dec_cpl_ex3_mc_dep_chk_val, + lsu_xu_ex4_cr_upd => lsu_xu_ex4_cr_upd, + lsu_xu_ex5_cr_rslt => lsu_xu_ex5_cr_rslt, + dec_spr_ex4_val => dec_spr_ex4_val, + dec_spr_ex1_epid_instr => dec_spr_ex1_epid_instr, + mux_spr_ex2_rt => mux_spr_ex2_rt, + fxu_spr_ex1_rs0 => fxu_spr_ex1_rs0, + fxu_spr_ex1_rs1 => fxu_spr_ex1_rs1, + spr_msr_cm => spr_msr_cm, + spr_dec_spr_xucr0_ssdly => spr_dec_spr_xucr0_ssdly, + spr_ccr2_en_attn => spr_ccr2_en_attn, + spr_ccr2_en_ditc => spr_ccr2_en_ditc, + spr_ccr2_en_pc => spr_ccr2_en_pc, + spr_ccr2_en_icswx => spr_ccr2_en_icswx, + spr_ccr2_en_dcr => spr_ccr2_en_dcr, + spr_dec_rf1_epcr_dgtmi => spr_dec_rf1_epcr_dgtmi, + spr_dec_rf1_msr_ucle => spr_msr_ucle, + spr_dec_rf1_msrp_uclep => spr_msrp_uclep, + spr_byp_ex4_is_mfxer => spr_byp_ex4_is_mfxer, + spr_byp_ex3_spr_rt => spr_byp_ex3_spr_rt, + spr_byp_ex4_is_mtxer => spr_byp_ex4_is_mtxer, + spr_ccr2_notlb => spr_ccr2_notlb, + dec_spr_rf1_val => dec_spr_rf1_val, + fxu_spr_ex1_rs2 => fxu_spr_ex1_rs2, + fxa_perf_muldiv_in_use => fxa_perf_muldiv_in_use, + spr_perf_tx_events => spr_perf_tx_events, + xu_pc_event_data => xu_pc_event_data, + pc_xu_event_bus_enable => pc_xu_event_bus_enable, + pc_xu_event_count_mode => pc_xu_event_count_mode, + pc_xu_event_mux_ctrls => pc_xu_event_mux_ctrls, + pc_xu_trace_bus_enable => pc_xu_trace_bus_enable, + pc_xu_instr_trace_mode => pc_xu_instr_trace_mode, + pc_xu_instr_trace_tid => pc_xu_instr_trace_tid, + xu_lsu_ex2_instr_trace_val => xu_lsu_ex2_instr_trace_val, + fxu_debug_mux_ctrls => fxu_debug_mux_ctrls, + fxu_trigger_data_in => fxu_trigger_data_in, + fxu_debug_data_in => fxu_debug_data_in, + fxu_trigger_data_out => fxu_trigger_data_out, + fxu_debug_data_out => fxu_debug_data_out, + lsu_xu_data_debug0 => lsu_xu_data_debug0, + lsu_xu_data_debug1 => lsu_xu_data_debug1, + lsu_xu_data_debug2 => lsu_xu_data_debug2, + spr_msr_gs => spr_msr_gs, + spr_msr_ds => spr_msr_ds, + spr_msr_pr => spr_msr_pr, + spr_dbcr0_dac1 => spr_dbcr0_dac1, + spr_dbcr0_dac2 => spr_dbcr0_dac2, + spr_dbcr0_dac3 => spr_dbcr0_dac3, + spr_dbcr0_dac4 => spr_dbcr0_dac4, + spr_xucr4_mmu_mchk => spr_xucr4_mmu_mchk_int, + ac_tc_debug_trigger => ac_tc_debug_trigger, + bcfg_scan_in => bcfg_scan_in, + bcfg_scan_out => bcfg_scan_out_int, + ccfg_scan_in => ccfg_scan_in, + ccfg_scan_out => ccfg_scan_out_int, + dcfg_scan_in => dcfg_scan_in, + dcfg_scan_out => dcfg_scan_out_int, + dec_cpl_rf0_act => dec_cpl_rf0_act, + dec_cpl_rf0_tid => dec_cpl_rf0_tid, + fu_xu_rf1_act => fu_xu_rf1_act, + fu_xu_ex1_ifar => fu_xu_ex1_ifar, + fu_xu_ex2_ifar_val => fu_xu_ex2_ifar_val, + fu_xu_ex2_ifar_issued => fu_xu_ex2_ifar_issued, + fu_xu_ex2_instr_type => fu_xu_ex2_instr_type, + fu_xu_ex2_instr_match => fu_xu_ex2_instr_match, + fu_xu_ex2_is_ucode => fu_xu_ex2_is_ucode, + pc_xu_step => pc_xu_step, + pc_xu_stop => pc_xu_stop, + pc_xu_dbg_action => pc_xu_dbg_action, + pc_xu_force_ude => pc_xu_force_ude, + xu_pc_step_done => xu_pc_step_done, + pc_xu_init_reset => pc_xu_init_reset, + spr_cpl_ext_interrupt => spr_cpl_ext_interrupt, + spr_cpl_udec_interrupt => spr_cpl_udec_interrupt, + spr_cpl_perf_interrupt => spr_cpl_perf_interrupt, + spr_cpl_dec_interrupt => spr_cpl_dec_interrupt, + spr_cpl_fit_interrupt => spr_cpl_fit_interrupt, + spr_cpl_crit_interrupt => spr_cpl_crit_interrupt, + spr_cpl_wdog_interrupt => spr_cpl_wdog_interrupt, + spr_cpl_dbell_interrupt => spr_cpl_dbell_interrupt, + spr_cpl_cdbell_interrupt => spr_cpl_cdbell_interrupt, + spr_cpl_gdbell_interrupt => spr_cpl_gdbell_interrupt, + spr_cpl_gcdbell_interrupt => spr_cpl_gcdbell_interrupt, + spr_cpl_gmcdbell_interrupt => spr_cpl_gmcdbell_interrupt, + cpl_spr_ex5_dbell_taken => cpl_spr_ex5_dbell_taken, + cpl_spr_ex5_cdbell_taken => cpl_spr_ex5_cdbell_taken, + cpl_spr_ex5_gdbell_taken => cpl_spr_ex5_gdbell_taken, + cpl_spr_ex5_gcdbell_taken => cpl_spr_ex5_gcdbell_taken, + cpl_spr_ex5_gmcdbell_taken => cpl_spr_ex5_gmcdbell_taken, + cpl_spr_ex5_act => cpl_spr_ex5_act, + cpl_spr_ex5_int => cpl_spr_ex5_int, + cpl_spr_ex5_gint => cpl_spr_ex5_gint, + cpl_spr_ex5_cint => cpl_spr_ex5_cint, + cpl_spr_ex5_mcint => cpl_spr_ex5_mcint, + cpl_spr_ex5_nia => cpl_spr_ex5_nia, + cpl_spr_ex5_esr => cpl_spr_ex5_esr, + cpl_spr_ex5_mcsr => cpl_spr_ex5_mcsr, + cpl_spr_ex5_dbsr => cpl_spr_ex5_dbsr, + cpl_spr_ex5_dear_save => cpl_spr_ex5_dear_save, + cpl_spr_ex5_dear_update_saved => cpl_spr_ex5_dear_update_saved, + cpl_spr_ex5_dear_update => cpl_spr_ex5_dear_update, + cpl_spr_ex5_dbsr_update => cpl_spr_ex5_dbsr_update, + cpl_spr_ex5_esr_update => cpl_spr_ex5_esr_update, + cpl_spr_ex5_srr0_dec => cpl_spr_ex5_srr0_dec, + cpl_spr_ex5_force_gsrr => cpl_spr_ex5_force_gsrr, + cpl_spr_ex5_dbsr_ide => cpl_spr_ex5_dbsr_ide, + spr_cpl_dbsr_ide => spr_cpl_dbsr_ide, + mm_xu_local_snoop_reject => mm_xu_local_snoop_reject, + mm_xu_lru_par_err => mm_xu_lru_par_err, + mm_xu_tlb_par_err => mm_xu_tlb_par_err, + mm_xu_tlb_multihit_err => mm_xu_tlb_multihit_err, + lsu_xu_ex3_derat_par_err => lsu_xu_ex3_derat_par_err, + lsu_xu_ex4_derat_par_err => lsu_xu_ex4_derat_par_err, + lsu_xu_ex3_derat_multihit_err => lsu_xu_ex3_derat_multihit_err, + lsu_xu_ex3_l2_uc_ecc_err => lsu_xu_ex3_l2_uc_ecc_err, + lsu_xu_ex3_ddir_par_err => lsu_xu_ex3_ddir_par_err, + lsu_xu_ex4_n_lsu_ddmh_flush => lsu_xu_ex4_n_lsu_ddmh_flush, + lsu_xu_ex6_datc_par_err => lsu_xu_ex6_datc_par_err, + spr_cpl_external_mchk => spr_cpl_external_mchk, + xu_pc_err_attention_instr => xu_pc_err_attention_instr, + xu_pc_err_nia_miscmpr => xu_pc_err_nia_miscmpr, + xu_pc_err_debug_event => xu_pc_err_debug_event, + lsu_xu_ex3_dsi => lsu_xu_ex3_dsi, + derat_xu_ex3_dsi => derat_xu_ex3_dsi, + spr_cpl_ex3_ct_le => spr_cpl_ex3_ct_le, + spr_cpl_ex3_ct_be => spr_cpl_ex3_ct_be, + lsu_xu_ex3_align => lsu_xu_ex3_align, + spr_cpl_ex3_spr_illeg => spr_cpl_ex3_spr_illeg, + spr_cpl_ex3_spr_priv => spr_cpl_ex3_spr_priv, + spr_cpl_ex3_spr_hypv => spr_cpl_ex3_spr_hypv, + derat_xu_ex3_miss => derat_xu_ex3_miss, + pc_xu_ram_mode => pc_xu_ram_mode, + pc_xu_ram_thread => pc_xu_ram_thread, + pc_xu_ram_execute => pc_xu_ram_execute, + xu_iu_ram_issue => xu_iu_ram_issue, + xu_pc_ram_interrupt => xu_pc_ram_interrupt, + xu_pc_ram_done => xu_pc_ram_done, + pc_xu_ram_flush_thread => pc_xu_ram_flush_thread, + cpl_spr_stop => cpl_spr_stop, + xu_pc_stop_dbg_event => xu_pc_stop_dbg_event, + cpl_spr_ex5_instr_cpl => cpl_spr_ex5_instr_cpl, + spr_cpl_quiesce => spr_cpl_quiesce, + cpl_spr_quiesce => cpl_spr_quiesce, + spr_cpl_ex2_run_ctl_flush => spr_cpl_ex2_run_ctl_flush, + mm_xu_illeg_instr => mm_xu_illeg_instr, + mm_xu_tlb_miss => mm_xu_tlb_miss, + mm_xu_pt_fault => mm_xu_pt_fault, + mm_xu_tlb_inelig => mm_xu_tlb_inelig, + mm_xu_lrat_miss => mm_xu_lrat_miss, + mm_xu_hv_priv => mm_xu_hv_priv, + mm_xu_esr_pt => mm_xu_esr_pt, + mm_xu_esr_data => mm_xu_esr_data, + mm_xu_esr_epid => mm_xu_esr_epid, + mm_xu_esr_st => mm_xu_esr_st, + mm_xu_hold_req => mm_xu_hold_req, + mm_xu_hold_done => mm_xu_hold_done, + xu_mm_hold_ack => xu_mm_hold_ack, + mm_xu_eratmiss_done => mm_xu_eratmiss_done, + mm_xu_ex3_flush_req => mm_xu_ex3_flush_req, + lsu_xu_l2_ecc_err_flush => lsu_xu_l2_ecc_err_flush, + lsu_xu_datc_perr_recovery => lsu_xu_datc_perr_recovery, + lsu_xu_ex3_dep_flush => lsu_xu_ex3_dep_flush, + lsu_xu_ex3_n_flush_req => lsu_xu_ex3_n_flush_req, + lsu_xu_ex3_ldq_hit_flush => lsu_xu_ex3_ldq_hit_flush, + lsu_xu_ex4_ldq_full_flush => lsu_xu_ex4_ldq_full_flush, + derat_xu_ex3_n_flush_req => derat_xu_ex3_n_flush_req, + lsu_xu_ex3_inval_align_2ucode => lsu_xu_ex3_inval_align_2ucode, + lsu_xu_ex3_attr => lsu_xu_ex3_attr, + lsu_xu_ex3_derat_vf => lsu_xu_ex3_derat_vf, + fu_xu_ex3_ap_int_req => fu_xu_ex3_ap_int_req, + fu_xu_ex3_trap => fu_xu_ex3_trap, + fu_xu_ex3_n_flush => fu_xu_ex3_n_flush, + fu_xu_ex3_np1_flush => fu_xu_ex3_np1_flush, + fu_xu_ex3_flush2ucode => fu_xu_ex3_flush2ucode, + fu_xu_ex2_async_block => fu_xu_ex2_async_block, + xu_iu_ex5_br_taken => xu_iu_ex5_br_taken, + xu_iu_ex5_ifar => xu_iu_ex5_ifar, + xu_iu_flush => xu_iu_flush, + xu_iu_iu0_flush_ifar => xu_iu_iu0_flush_ifar, + xu_iu_uc_flush_ifar => xu_iu_uc_flush_ifar, + xu_iu_flush_2ucode => xu_iu_flush_2ucode, + xu_iu_flush_2ucode_type => xu_iu_flush_2ucode_type, + xu_iu_ucode_restart => xu_iu_ucode_restart, + xu_iu_ex5_ppc_cpl => xu_iu_ex5_ppc_cpl, + xu_rf0_flush => xu_rf0_flush, + xu_rf1_flush => xu_rf1_flush, + xu_ex1_flush => xu_ex1_flush, + xu_ex2_flush => xu_ex2_flush, + xu_ex3_flush => xu_ex3_flush, + xu_ex4_flush => xu_ex4_flush, + xu_n_is2_flush => xu_n_is2_flush, + xu_n_rf0_flush => xu_n_rf0_flush, + xu_n_rf1_flush => xu_n_rf1_flush, + xu_n_ex1_flush => xu_n_ex1_flush, + xu_n_ex2_flush => xu_n_ex2_flush, + xu_n_ex3_flush => xu_n_ex3_flush, + xu_n_ex4_flush => xu_n_ex4_flush, + xu_n_ex5_flush => xu_n_ex5_flush_int, + xu_s_rf1_flush => xu_s_rf1_flush, + xu_s_ex1_flush => xu_s_ex1_flush, + xu_s_ex2_flush => xu_s_ex2_flush, + xu_s_ex3_flush => xu_s_ex3_flush, + xu_s_ex4_flush => xu_s_ex4_flush, + xu_s_ex5_flush => xu_s_ex5_flush, + xu_w_rf1_flush => xu_w_rf1_flush, + xu_w_ex1_flush => xu_w_ex1_flush, + xu_w_ex2_flush => xu_w_ex2_flush, + xu_w_ex3_flush => xu_w_ex3_flush, + xu_w_ex4_flush => xu_w_ex4_flush, + xu_w_ex5_flush => xu_w_ex5_flush, + xu_lsu_ex4_flush_local => xu_lsu_ex4_flush_local_int, + xu_mm_ex4_flush => xu_mm_ex4_flush, + xu_mm_ex5_flush => xu_mm_ex5_flush, + xu_mm_ierat_flush => xu_mm_ierat_flush, + xu_mm_ierat_miss => xu_mm_ierat_miss, + xu_mm_ex5_perf_itlb => xu_mm_ex5_perf_itlb, + xu_mm_ex5_perf_dtlb => xu_mm_ex5_perf_dtlb, + spr_cpl_iac1_en => spr_cpl_iac1_en, + spr_cpl_iac2_en => spr_cpl_iac2_en, + spr_cpl_iac3_en => spr_cpl_iac3_en, + spr_cpl_iac4_en => spr_cpl_iac4_en, + spr_bit_act => spr_bit_act, + spr_epcr_duvd => spr_epcr_duvd, + spr_dbcr1_iac12m => spr_dbcr1_iac12m, + spr_dbcr1_iac34m => spr_dbcr1_iac34m, + spr_cpl_fp_precise => spr_cpl_fp_precise, + spr_xucr0_mddp => spr_xucr0_mddp, + spr_xucr0_mdcp => spr_xucr0_mdcp, + spr_msr_de => spr_msr_de, + spr_msr_spv => spr_msr_spv, + spr_msr_fp => spr_msr_fp, + spr_msr_me => spr_msr_me, + spr_msr_ucle => spr_msr_ucle, + spr_msrp_uclep => spr_msrp_uclep, + spr_ccr2_ucode_dis => spr_ccr2_ucode_dis, + spr_ccr2_ap => spr_ccr2_ap, + spr_dbcr0_idm => spr_dbcr0_idm, + cpl_spr_dbcr0_edm => cpl_spr_dbcr0_edm, + spr_dbcr0_icmp => spr_dbcr0_icmp, + spr_dbcr0_brt => spr_dbcr0_brt, + spr_dbcr0_trap => spr_dbcr0_trap, + spr_dbcr0_ret => spr_dbcr0_ret, + spr_dbcr0_irpt => spr_dbcr0_irpt, + spr_epcr_dsigs => spr_epcr_dsigs, + spr_epcr_isigs => spr_epcr_isigs, + spr_epcr_extgs => spr_epcr_extgs, + spr_epcr_dtlbgs => spr_epcr_dtlbgs, + spr_epcr_itlbgs => spr_epcr_itlbgs, + spr_xucr4_div_barr_thres => spr_xucr4_div_barr_thres, + spr_ccr0_we => spr_ccr0_we, + cpl_msr_gs => cpl_msr_gs, + cpl_msr_pr => cpl_msr_pr, + cpl_msr_fp => cpl_msr_fp, + cpl_msr_spv => cpl_msr_spv, + cpl_ccr2_ap => cpl_ccr2_ap, + xu_lsu_ici => xu_lsu_ici, + xu_lsu_dci => xu_lsu_dci, + spr_xucr0_clkg_ctl => spr_xucr0_clkg_ctl(2 to 2), + spr_cpl_ex3_sprg_ce => spr_cpl_ex3_sprg_ce, + spr_cpl_ex3_sprg_ue => spr_cpl_ex3_sprg_ue, + iu_xu_ierat_ex2_flush_req => iu_xu_ierat_ex2_flush_req, + iu_xu_ierat_ex3_par_err => iu_xu_ierat_ex3_par_err, + iu_xu_ierat_ex4_par_err => iu_xu_ierat_ex4_par_err, + fu_xu_ex3_regfile_err_det => fu_xu_ex3_regfile_err_det, + xu_fu_regfile_seq_beg => xu_fu_regfile_seq_beg, + fu_xu_regfile_seq_end => fu_xu_regfile_seq_end, + gpr_cpl_ex3_regfile_err_det => gpr_cpl_ex3_regfile_err_det, + cpl_gpr_regfile_seq_beg => cpl_gpr_regfile_seq_beg, + gpr_cpl_regfile_seq_end => gpr_cpl_regfile_seq_end, + xu_pc_err_mcsr_summary => xu_pc_err_mcsr_summary, + xu_pc_err_ditc_overrun => xu_pc_err_ditc_overrun, + xu_pc_err_local_snoop_reject => xu_pc_err_local_snoop_reject, + xu_pc_err_tlb_lru_parity => xu_pc_err_tlb_lru_parity, + xu_pc_err_ext_mchk => xu_pc_err_ext_mchk, + xu_pc_err_ierat_multihit => xu_pc_err_ierat_multihit, + xu_pc_err_derat_multihit => xu_pc_err_derat_multihit, + xu_pc_err_tlb_multihit => xu_pc_err_tlb_multihit, + xu_pc_err_ierat_parity => xu_pc_err_ierat_parity, + xu_pc_err_derat_parity => xu_pc_err_derat_parity, + xu_pc_err_tlb_parity => xu_pc_err_tlb_parity, + xu_pc_err_mchk_disabled => xu_pc_err_mchk_disabled, + xu_pc_err_sprg_ue => xu_pc_err_sprg_ue, + cpl_debug_mux_ctrls => cpl_debug_mux_ctrls, + cpl_debug_data_in => cpl_debug_data_in, + cpl_debug_data_out => cpl_debug_data_out, + cpl_trigger_data_in => cpl_trigger_data_in, + cpl_trigger_data_out => cpl_trigger_data_out, + fxa_cpl_debug => fxa_cpl_debug + ); + +lsucmd : entity work.xuq_lsu_cmd(xuq_lsu_cmd) +generic map(expand_type => expand_type, + lmq_entries => lmq_entries, + l_endian_m => l_endian_m, + regmode => regmode, + dc_size => dc_size, + cl_size => cl_size, + real_data_add => real_data_add, + a2mode => a2mode, + load_credits => load_credits, + store_credits => store_credits, + bcfg_epn_0to15 => bcfg_epn_0to15, + bcfg_epn_16to31 => bcfg_epn_16to31, + bcfg_epn_32to47 => bcfg_epn_32to47, + bcfg_epn_48to51 => bcfg_epn_48to51, + bcfg_rpn_22to31 => bcfg_rpn_22to31, + bcfg_rpn_32to47 => bcfg_rpn_32to47, + bcfg_rpn_48to51 => bcfg_rpn_48to51, + st_data_32B_mode => st_data_32B_mode) +port map( + xu_lsu_rf0_act => xu_lsu_rf0_act, + xu_lsu_rf1_cmd_act => xu_lsu_rf1_cmd_act, + xu_lsu_rf1_axu_op_val => xu_lsu_rf1_axu_op_val, + xu_lsu_rf1_axu_ldst_falign => xu_lsu_rf1_axu_ldst_falign_int, + xu_lsu_rf1_axu_ldst_fexcpt => xu_lsu_rf1_axu_ldst_fexcpt, + xu_lsu_rf1_cache_acc => xu_lsu_rf1_cache_acc, + xu_lsu_rf1_thrd_id => xu_lsu_rf1_thrd_id, + xu_lsu_rf1_optype1 => xu_lsu_rf1_optype1, + xu_lsu_rf1_optype2 => xu_lsu_rf1_optype2, + xu_lsu_rf1_optype4 => xu_lsu_rf1_optype4, + xu_lsu_rf1_optype8 => xu_lsu_rf1_optype8, + xu_lsu_rf1_optype16 => xu_lsu_rf1_optype16, + xu_lsu_rf1_optype32 => xu_lsu_rf1_optype32, + xu_lsu_rf1_target_gpr => xu_lsu_rf1_target_gpr, + xu_lsu_rf1_mtspr_trace => xu_lsu_rf1_mtspr_trace, + xu_lsu_rf1_load_instr => xu_lsu_rf1_load_instr, + xu_lsu_rf1_store_instr => xu_lsu_rf1_store_instr, + xu_lsu_rf1_dcbf_instr => xu_lsu_rf1_dcbf_instr, + xu_lsu_rf1_sync_instr => xu_lsu_rf1_sync_instr, + xu_lsu_rf1_l_fld => xu_lsu_rf1_l_fld, + xu_lsu_rf1_dcbi_instr => xu_lsu_rf1_dcbi_instr, + xu_lsu_rf1_dcbz_instr => xu_lsu_rf1_dcbz_instr, + xu_lsu_rf1_dcbt_instr => xu_lsu_rf1_dcbt_instr, + xu_lsu_rf1_dcbtst_instr => xu_lsu_rf1_dcbtst_instr, + xu_lsu_rf1_th_fld => xu_lsu_rf1_th_fld, + xu_lsu_rf1_dcbtls_instr => xu_lsu_rf1_dcbtls_instr, + xu_lsu_rf1_dcbtstls_instr => xu_lsu_rf1_dcbtstls_instr, + xu_lsu_rf1_dcblc_instr => xu_lsu_rf1_dcblc_instr, + xu_lsu_rf1_dcbst_instr => xu_lsu_rf1_dcbst_instr, + xu_lsu_rf1_icbi_instr => xu_lsu_rf1_icbi_instr, + xu_lsu_rf1_icblc_instr => xu_lsu_rf1_icblc_instr, + xu_lsu_rf1_icbt_instr => xu_lsu_rf1_icbt_instr, + xu_lsu_rf1_icbtls_instr => xu_lsu_rf1_icbtls_instr, + xu_lsu_rf1_icswx_instr => xu_lsu_rf1_icswx_instr, + xu_lsu_rf1_icswx_dot_instr => xu_lsu_rf1_icswx_dot_instr, + xu_lsu_rf1_icswx_epid => xu_lsu_rf1_icswx_epid, + xu_lsu_rf1_tlbsync_instr => xu_lsu_rf1_tlbsync_instr, + xu_lsu_rf1_ldawx_instr => xu_lsu_rf1_ldawx_instr, + xu_lsu_rf1_wclr_instr => xu_lsu_rf1_wclr_instr, + xu_lsu_rf1_wchk_instr => xu_lsu_rf1_wchk_instr, + xu_lsu_rf1_lock_instr => xu_lsu_rf1_lock_instr, + xu_lsu_rf1_mutex_hint => xu_lsu_rf1_mutex_hint, + xu_lsu_rf1_mbar_instr => xu_lsu_rf1_mbar_instr, + xu_lsu_rf1_is_msgsnd => xu_lsu_rf1_is_msgsnd, + xu_lsu_rf1_dci_instr => xu_lsu_rf1_dci_instr, + xu_lsu_rf1_ici_instr => xu_lsu_rf1_ici_instr, + xu_lsu_rf1_algebraic => xu_lsu_rf1_algebraic, + xu_lsu_rf1_byte_rev => xu_lsu_rf1_byte_rev, + xu_lsu_rf1_src_gpr => xu_lsu_rf1_src_gpr, + xu_lsu_rf1_src_axu => xu_lsu_rf1_src_axu, + xu_lsu_rf1_src_dp => xu_lsu_rf1_src_dp, + xu_lsu_rf1_targ_gpr => xu_lsu_rf1_targ_gpr, + xu_lsu_rf1_targ_axu => xu_lsu_rf1_targ_axu, + xu_lsu_rf1_targ_dp => xu_lsu_rf1_targ_dp, + xu_lsu_ex4_val => xu_lsu_ex4_val, + xu_lsu_ex1_add_src0 => xu_lsu_ex1_add_src0, + xu_lsu_ex1_add_src1 => xu_lsu_ex1_add_src1, + xu_lsu_ex2_instr_trace_val => xu_lsu_ex2_instr_trace_val, + + -- Dependency Checking on loadmisses + xu_lsu_rf1_src0_vld => xu_lsu_rf1_src0_vld, + xu_lsu_rf1_src0_reg => xu_lsu_rf1_src0_reg, + xu_lsu_rf1_src1_vld => xu_lsu_rf1_src1_vld, + xu_lsu_rf1_src1_reg => xu_lsu_rf1_src1_reg, + xu_lsu_rf1_targ_vld => xu_lsu_rf1_targ_vld, + xu_lsu_rf1_targ_reg => xu_lsu_rf1_targ_reg, + + -- Error Inject + pc_xu_inj_dcachedir_parity => pc_xu_inj_dcachedir_parity, + pc_xu_inj_dcachedir_multihit => pc_xu_inj_dcachedir_multihit, + + -- Signals Coming DERAT + derat_xu_ex3_n_flush_req => derat_xu_ex3_n_flush_req, + derat_xu_ex3_miss => derat_xu_ex3_miss, + derat_xu_ex3_dsi => derat_xu_ex3_dsi, + lsu_xu_ex3_derat_multihit_err => lsu_xu_ex3_derat_multihit_err, + lsu_xu_ex3_derat_par_err => lsu_xu_ex3_derat_par_err, + lsu_xu_ex4_derat_par_err => lsu_xu_ex4_derat_par_err, + + ex4_256st_data => ex4_256st_data, + xu_lsu_ex4_dvc1_en => xu_lsu_ex4_dvc1_en, + xu_lsu_ex4_dvc2_en => xu_lsu_ex4_dvc2_en, + + xu_lsu_mtspr_trace_en => xu_lsu_mtspr_trace_en, + spr_xucr0_clkg_ctl_b1 => spr_xucr0_clkg_ctl(1), + spr_xucr0_clkg_ctl_b3 => spr_xucr0_clkg_ctl(3), + spr_xucr4_mmu_mchk => spr_xucr4_mmu_mchk_int, + xu_lsu_spr_xucr0_aflsta => xu_lsu_spr_xucr0_aflsta, + xu_lsu_spr_xucr0_flsta => xu_lsu_spr_xucr0_flsta, + xu_lsu_spr_xucr0_l2siw => xu_lsu_spr_xucr0_l2siw, + xu_lsu_spr_xucr0_dcdis => xu_lsu_spr_xucr0_dcdis, + xu_lsu_spr_xucr0_wlk => xu_lsu_spr_xucr0_wlk, + xu_lsu_spr_xucr0_flh2l2 => xu_lsu_spr_xucr0_flh2l2, + xu_lsu_spr_xucr0_clfc => xu_lsu_spr_xucr0_clfc, + xu_lsu_spr_xucr0_cred => xu_lsu_spr_xucr0_cred, + xu_lsu_spr_xucr0_rel => xu_lsu_spr_xucr0_rel, + xu_lsu_spr_xucr0_mbar_ack => xu_lsu_spr_xucr0_mbar_ack, + xu_lsu_spr_xucr0_tlbsync => xu_lsu_spr_xucr0_tlbsync, + xu_lsu_spr_xucr0_cls => xu_lsu_spr_xucr0_cls, + xu_lsu_spr_ccr2_dfrat => xu_lsu_spr_ccr2_dfrat, + xu_lsu_spr_ccr2_dfratsc => xu_lsu_spr_ccr2_dfratsc, + xu_lsu_ex5_set_barr => xu_lsu_ex5_set_barr, + + an_ac_flh2l2_gate => an_ac_flh2l2_gate, + + xu_lsu_dci => xu_lsu_dci, + + -- ERAT Operations + xu_lsu_rf0_derat_val => xu_lsu_rf0_derat_val, + xu_lsu_rf1_derat_act => xu_lsu_rf1_derat_act, + xu_lsu_rf1_derat_ra_eq_ea => xu_lsu_rf1_derat_ra_eq_ea, + xu_lsu_rf1_derat_is_load => xu_lsu_rf1_derat_is_load, + xu_lsu_rf1_derat_is_store => xu_lsu_rf1_derat_is_store, + xu_lsu_rf0_derat_is_extload => xu_lsu_rf0_derat_is_extload, + xu_lsu_rf0_derat_is_extstore => xu_lsu_rf0_derat_is_extstore, + xu_lsu_rf1_is_eratre => xu_rf1_is_eratre_int, + xu_lsu_rf1_is_eratwe => xu_rf1_is_eratwe_int, + xu_lsu_rf1_is_eratsx => xu_rf1_is_eratsx_int, + xu_lsu_rf1_is_eratilx => xu_rf1_is_eratilx_int, + xu_lsu_ex1_is_isync => xu_ex1_is_isync_int, + xu_lsu_ex1_is_csync => xu_ex1_is_csync_int, + xu_lsu_rf1_is_touch => xu_lsu_rf1_is_touch, + xu_lsu_rf1_ws => xu_rf1_ws_int, + xu_lsu_rf1_t => xu_rf1_t_int, + xu_lsu_ex1_rs_is => xu_ex1_rs_is_int, + xu_lsu_ex1_ra_entry => xu_ex1_ra_entry_int(7 to 11), + xu_lsu_ex4_rs_data => xu_ex4_rs_data_int, + xu_lsu_msr_gs => spr_msr_gs, + xu_lsu_msr_pr => spr_msr_pr, + xu_lsu_msr_ds => spr_msr_ds, + xu_lsu_msr_cm => spr_msr_cm, + xu_lsu_hid_mmu_mode => xu_lsu_hid_mmu_mode, + ex6_ld_par_err => ex6_ld_par_err, + + xu_lsu_rf0_flush => xu_rf0_flush, + xu_lsu_rf1_flush => xu_rf1_flush, + xu_lsu_ex1_flush => xu_ex1_flush, + xu_lsu_ex2_flush => xu_ex2_flush, + xu_lsu_ex3_flush => xu_ex3_flush, + xu_lsu_ex4_flush => xu_ex4_flush, + xu_lsu_ex5_flush => xu_n_ex5_flush_int, + + lsu_xu_ex4_tlb_data => lsu_xu_ex4_tlb_data, + xu_mm_derat_req => xu_mm_derat_req, + xu_mm_derat_thdid => xu_mm_derat_thdid, + xu_mm_derat_state => xu_mm_derat_state, + xu_mm_derat_tid => xu_mm_derat_tid, + xu_mm_derat_lpid => xu_mm_derat_lpid, + xu_mm_derat_ttype => xu_mm_derat_ttype, + mm_xu_derat_rel_val => mm_xu_derat_rel_val, + mm_xu_derat_rel_data => mm_xu_derat_rel_data, + mm_xu_derat_pid0 => mm_xu_derat_pid0, + mm_xu_derat_pid1 => mm_xu_derat_pid1, + mm_xu_derat_pid2 => mm_xu_derat_pid2, + mm_xu_derat_pid3 => mm_xu_derat_pid3, + mm_xu_derat_mmucr0_0 => mm_xu_derat_mmucr0_0, + mm_xu_derat_mmucr0_1 => mm_xu_derat_mmucr0_1, + mm_xu_derat_mmucr0_2 => mm_xu_derat_mmucr0_2, + mm_xu_derat_mmucr0_3 => mm_xu_derat_mmucr0_3, + xu_mm_derat_mmucr0 => xu_mm_derat_mmucr0, + xu_mm_derat_mmucr0_we => xu_mm_derat_mmucr0_we, + mm_xu_derat_mmucr1 => mm_xu_derat_mmucr1, + xu_mm_derat_mmucr1 => xu_mm_derat_mmucr1, + xu_mm_derat_mmucr1_we => xu_mm_derat_mmucr1_we, + mm_xu_derat_snoop_coming => mm_xu_derat_snoop_coming, + mm_xu_derat_snoop_val => mm_xu_derat_snoop_val, + mm_xu_derat_snoop_attr => mm_xu_derat_snoop_attr, + mm_xu_derat_snoop_vpn => mm_xu_derat_snoop_vpn , + xu_mm_derat_snoop_ack => xu_mm_derat_snoop_ack , + + xu_lsu_slowspr_val => xu_lsu_slowspr_val, + xu_lsu_slowspr_rw => xu_lsu_slowspr_rw, + xu_lsu_slowspr_etid => xu_lsu_slowspr_etid, + xu_lsu_slowspr_addr => xu_lsu_slowspr_addr, + xu_lsu_slowspr_data => xu_lsu_slowspr_data, + xu_lsu_slowspr_done => xu_lsu_slowspr_done, + slowspr_val_out => slowspr_val_out, + slowspr_rw_out => slowspr_rw_out, + slowspr_etid_out => slowspr_etid_out, + slowspr_addr_out => slowspr_addr_out, + slowspr_data_out => slowspr_data_out, + slowspr_done_out => slowspr_done_out, + + ex1_optype1 => ex1_optype1, + ex1_optype2 => ex1_optype2, + ex1_optype4 => ex1_optype4, + ex1_optype8 => ex1_optype8, + ex1_optype16 => ex1_optype16, + ex1_optype32 => ex1_optype32, + ex1_saxu_instr => ex1_saxu_instr, + ex1_sdp_instr => ex1_sdp_instr, + ex1_stgpr_instr => ex1_stgpr_instr, + ex1_store_instr => ex1_store_instr, + ex1_axu_op_val => ex1_axu_op_val, + + lsu_xu_ex3_align => lsu_xu_ex3_align, + lsu_xu_ex3_dsi => lsu_xu_ex3_dsi, + lsu_xu_ex3_inval_align_2ucode => lsu_xu_ex3_inval_align_2ucode, + lsu_xu_ex3_attr => lsu_xu_ex3_attr, + lsu_xu_ex3_derat_vf => lsu_xu_ex3_derat_vf, + + lsu_xu_ex3_n_flush_req => lsu_xu_ex3_n_flush_req, + lsu_xu_ex4_ldq_full_flush => lsu_xu_ex4_ldq_full_flush, + lsu_xu_ex3_ldq_hit_flush => lsu_xu_ex3_ldq_hit_flush, + lsu_xu_ex3_dep_flush => lsu_xu_ex3_dep_flush, + lsu_xu_datc_perr_recovery => lsu_xu_datc_perr_recovery, + lsu_xu_l2_ecc_err_flush => lsu_xu_l2_ecc_err_flush, + + ex3_algebraic => ex3_algebraic, + ex3_data_swap => ex3_data_swap, + ex3_thrd_id => ex3_thrd_id, + xu_fu_ex3_eff_addr => xu_fu_ex3_eff_addr, + + lsu_xu_ex3_ddir_par_err => lsu_xu_ex3_ddir_par_err, + lsu_xu_ex4_n_lsu_ddmh_flush => lsu_xu_ex4_n_lsu_ddmh_flush, + + -- back invalidate + lsu_xu_is2_back_inv => lsu_xu_is2_back_inv, + lsu_xu_is2_back_inv_addr => lsu_xu_is2_back_inv_addr, + lsu_xu_ex4_cr_upd => lsu_xu_ex4_cr_upd, + lsu_xu_ex5_cr_rslt => lsu_xu_ex5_cr_rslt, + + -- Update Data Array Valid + rel_upd_dcarr_val => rel_upd_dcarr_val, + + lsu_xu_ex5_wren => lsu_xu_ex5_wren, + lsu_xu_rel_wren => lsu_xu_rel_wren_int, + lsu_xu_rel_ta_gpr => lsu_xu_rel_ta_gpr_int, + lsu_xu_need_hole => lsu_xu_need_hole, + xu_fu_ex5_reload_val => xu_fu_ex5_reload_val, + xu_fu_ex5_load_val => xu_fu_ex5_load_val, + xu_fu_ex5_load_tag => xu_fu_ex5_load_tag, + + -- Data Array Controls + dcarr_up_way_addr => dcarr_up_way_addr, + + -- SPR status + lsu_xu_spr_xucr0_cslc_xuop => lsu_xu_spr_xucr0_cslc_xuop, + lsu_xu_spr_xucr0_cslc_binv => lsu_xu_spr_xucr0_cslc_binv, + lsu_xu_spr_xucr0_clo => lsu_xu_spr_xucr0_clo, + lsu_xu_spr_xucr0_cul => lsu_xu_spr_xucr0_cul, + lsu_xu_spr_epsc_epr => lsu_xu_spr_epsc_epr, + lsu_xu_spr_epsc_egs => lsu_xu_spr_epsc_egs, + + -- Debug Data Compare + ex4_load_op_hit => ex4_load_op_hit, + ex4_store_hit => ex4_store_hit, + ex4_axu_op_val => ex4_axu_op_val, + spr_dvc1_act => spr_dvc1_act, + spr_dvc2_act => spr_dvc2_act, + spr_dvc1_dbg => spr_dvc1_dbg, + spr_dvc2_dbg => spr_dvc2_dbg, + + -- Inputs from L2 + an_ac_req_ld_pop => an_ac_req_ld_pop, + an_ac_req_st_pop => an_ac_req_st_pop, + an_ac_req_st_gather => an_ac_req_st_gather, + an_ac_req_st_pop_thrd => an_ac_req_st_pop_thrd, + an_ac_reld_data_val => an_ac_reld_data_vld, + an_ac_reld_core_tag => an_ac_reld_core_tag, + an_ac_reld_qw => an_ac_reld_qw, + an_ac_reld_data => an_ac_reld_data, + an_ac_reld_ecc_err => an_ac_reld_ecc_err, + an_ac_reld_ecc_err_ue => an_ac_reld_ecc_err_ue, + an_ac_reld_data_coming => an_ac_reld_data_coming, + an_ac_reld_ditc => an_ac_reld_ditc, + an_ac_reld_crit_qw => an_ac_reld_crit_qw, + an_ac_reld_l1_dump => an_ac_reld_l1_dump, + + an_ac_back_inv => an_ac_back_inv, + an_ac_back_inv_addr => an_ac_back_inv_addr, + an_ac_back_inv_target_bit1 => an_ac_back_inv_target_bit1, + an_ac_back_inv_target_bit4 => an_ac_back_inv_target_bit4, + + an_ac_req_spare_ctrl_a1 => an_ac_req_spare_ctrl_a1, + + an_ac_stcx_complete => an_ac_stcx_complete, + xu_iu_stcx_complete => xu_iu_stcx_complete, + xu_iu_reld_core_tag_clone => xu_iu_reld_core_tag_clone, + xu_iu_reld_data_coming_clone => xu_iu_reld_data_coming_clone, + xu_iu_reld_data_vld_clone => xu_iu_reld_data_vld_clone, + xu_iu_reld_ditc_clone => xu_iu_reld_ditc_clone, + + lsu_reld_data_vld => lsu_reld_data_vld, + lsu_reld_core_tag => lsu_reld_core_tag, + lsu_reld_qw => lsu_reld_qw, + lsu_reld_ditc => lsu_reld_ditc, + lsu_reld_ecc_err => lsu_reld_ecc_err, + lsu_reld_data => lsu_reld_data, + lsu_req_st_pop => lsu_req_st_pop, + lsu_req_st_pop_thrd => lsu_req_st_pop_thrd, + + -- latch and redrive for BXQ + ac_an_reld_ditc_pop_int => ac_an_reld_ditc_pop_int, + ac_an_reld_ditc_pop_q => ac_an_reld_ditc_pop_q , + bx_ib_empty_int => bx_ib_empty_int , + bx_ib_empty_q => bx_ib_empty_q , + + + -- Instruction Fetches + i_x_ra => iu_xu_ra, + i_x_request => iu_xu_request, + i_x_wimge => iu_xu_wimge, + i_x_thread => iu_xu_thread, + i_x_userdef => iu_xu_userdef, + + -- MMU instruction interface + mm_xu_lsu_req => mm_xu_lsu_req, + mm_xu_lsu_ttype => mm_xu_lsu_ttype, + mm_xu_lsu_wimge => mm_xu_lsu_wimge, + mm_xu_lsu_u => mm_xu_lsu_u, + mm_xu_lsu_addr => mm_xu_lsu_addr, + mm_xu_lsu_lpid => mm_xu_lsu_lpid, + mm_xu_lsu_lpidr => mm_xu_lsu_lpidr, + mm_xu_lsu_gs => mm_xu_lsu_gs , + mm_xu_lsu_ind => mm_xu_lsu_ind , + mm_xu_lsu_lbit => mm_xu_lsu_lbit, + xu_mm_lsu_token => xu_mm_lsu_token, + + -- inputs from boxes + bx_lsu_ob_pwr_tok => bx_lsu_ob_pwr_tok, + bx_lsu_ob_req_val => bx_lsu_ob_req_val, + bx_lsu_ob_ditc_val => bx_lsu_ob_ditc_val, + bx_lsu_ob_thrd => bx_lsu_ob_thrd, + bx_lsu_ob_qw => bx_lsu_ob_qw, + bx_lsu_ob_dest => bx_lsu_ob_dest, + bx_lsu_ob_data => bx_lsu_ob_data, + bx_lsu_ob_addr => bx_lsu_ob_addr, + + -- outputs to boxes + lsu_bx_cmd_avail => lsu_bx_cmd_avail, + lsu_bx_cmd_sent => lsu_bx_cmd_sent, + lsu_bx_cmd_stall => lsu_bx_cmd_stall, + + lsu_xu_ldq_barr_done => lsu_xu_ldq_barr_done, + lsu_xu_barr_done => lsu_xu_barr_done, + + -- *** Reload operation Outputs *** + ldq_rel_data_val_early => ldq_rel_data_val_early, + ldq_rel_op_size => ldq_rel_op_size, + ldq_rel_addr => ldq_rel_addr, + ldq_rel_data_val => ldq_rel_data_val, + ldq_rel_rot_sel => ldq_rel_rot_sel, + ldq_rel_axu_val => ldq_rel_axu_val, + ldq_rel_ci => ldq_rel_ci, + ldq_rel_thrd_id => ldq_rel_thrd_id, + ldq_rel_le_mode => ldq_rel_le_mode, + ldq_rel_algebraic => ldq_rel_algebraic, + ldq_rel_256_data => ldq_rel_256_data, + ldq_rel_dvc1_en => ldq_rel_dvc1_en, + ldq_rel_dvc2_en => ldq_rel_dvc2_en, + ldq_rel_beat_crit_qw => ldq_rel_beat_crit_qw, + ldq_rel_beat_crit_qw_block => ldq_rel_beat_crit_qw_block, + + xu_iu_ex4_loadmiss_qentry => xu_iu_ex4_loadmiss_qentry, + xu_iu_ex4_loadmiss_target => xu_iu_ex4_loadmiss_target, + xu_iu_ex4_loadmiss_target_type => xu_iu_ex4_loadmiss_target_type, + xu_iu_ex4_loadmiss_tid => xu_iu_ex4_loadmiss_tid, + xu_iu_ex5_loadmiss_qentry => xu_iu_ex5_loadmiss_qentry, + xu_iu_ex5_loadmiss_target => xu_iu_ex5_loadmiss_target, + xu_iu_ex5_loadmiss_target_type => xu_iu_ex5_loadmiss_target_type, + xu_iu_ex5_loadmiss_tid => xu_iu_ex5_loadmiss_tid, + xu_iu_complete_qentry => xu_iu_complete_qentry, + xu_iu_complete_tid => xu_iu_complete_tid, + xu_iu_complete_target_type => xu_iu_complete_target_type, + + -- ICBI Interface + xu_iu_ex6_icbi_val => xu_iu_ex6_icbi_val, + xu_iu_ex6_icbi_addr => xu_iu_ex6_icbi_addr, + + xu_iu_larx_done_tid => xu_iu_larx_done_tid, + xu_mm_lmq_stq_empty => xu_mm_lmq_stq_empty, + lsu_xu_quiesce => lsu_xu_quiesce, + lsu_xu_dbell_val => lsu_xu_dbell_val, + lsu_xu_dbell_type => lsu_xu_dbell_type, + lsu_xu_dbell_brdcast => lsu_xu_dbell_brdcast, + lsu_xu_dbell_lpid_match => lsu_xu_dbell_lpid_match, + lsu_xu_dbell_pirtag => lsu_xu_dbell_pirtag, + + ac_an_req_pwr_token => ac_an_req_pwr_token, + ac_an_req => ac_an_req, + ac_an_req_ra => ac_an_req_ra, + ac_an_req_ttype => ac_an_req_ttype, + ac_an_req_thread => ac_an_req_thread, + ac_an_req_wimg_w => ac_an_req_wimg_w, + ac_an_req_wimg_i => ac_an_req_wimg_i, + ac_an_req_wimg_m => ac_an_req_wimg_m, + ac_an_req_wimg_g => ac_an_req_wimg_g, + ac_an_req_endian => ac_an_req_endian, + ac_an_req_user_defined => ac_an_req_user_defined, + ac_an_req_spare_ctrl_a0 => ac_an_req_spare_ctrl_a0, + ac_an_req_ld_core_tag => ac_an_req_ld_core_tag, + ac_an_req_ld_xfr_len => ac_an_req_ld_xfr_len, + ac_an_st_byte_enbl => ac_an_st_byte_enbl, + ac_an_st_data => ac_an_st_data, + ac_an_st_data_pwr_token => ac_an_st_data_pwr_token, + + lsu_xu_ex3_l2_uc_ecc_err => lsu_xu_ex3_l2_uc_ecc_err, + xu_pc_err_dcachedir_parity => xu_pc_err_dcachedir_parity, + xu_pc_err_dcachedir_multihit => xu_pc_err_dcachedir_multihit, + xu_pc_err_l2intrf_ecc => xu_pc_err_l2intrf_ecc, + xu_pc_err_l2intrf_ue => xu_pc_err_l2intrf_ue, + xu_pc_err_invld_reld => xu_pc_err_invld_reld, + xu_pc_err_l2credit_overrun => xu_pc_err_l2credit_overrun, + pc_xu_event_bus_enable => pc_xu_event_bus_enable, + pc_xu_event_count_mode => pc_xu_event_count_mode, + pc_xu_lsu_event_mux_ctrls => pc_xu_lsu_event_mux_ctrls, + pc_xu_cache_par_err_event => pc_xu_cache_par_err_event, + xu_pc_lsu_event_data => xu_pc_lsu_event_data, + + -- Debug Trace Bus + pc_xu_trace_bus_enable => pc_xu_trace_bus_enable, + lsu_debug_mux_ctrls => lsu_debug_mux_ctrls, + trigger_data_in => lsu_trigger_data_in, + debug_data_in => lsu_debug_data_in, + trigger_data_out => lsu_trigger_data_out, + debug_data_out => lsu_debug_data_out, + lsu_xu_cmd_debug => lsu_xu_cmd_debug, + + --pervasive + vcs => vcs, + vdd => vdd, + gnd => gnd, + nclk => nclk, + + -- ABIST + pc_xu_abist_g8t_wenb => pc_xu_abist_g8t_wenb, + pc_xu_abist_g8t1p_renb_0 => pc_xu_abist_g8t1p_renb_0, + pc_xu_abist_di_0 => pc_xu_abist_di_0, + pc_xu_abist_g8t_bw_1 => pc_xu_abist_g8t_bw_1, + pc_xu_abist_g8t_bw_0 => pc_xu_abist_g8t_bw_0, + pc_xu_abist_waddr_0 => pc_xu_abist_waddr_0(5 to 9), + pc_xu_abist_raddr_0 => pc_xu_abist_raddr_0(5 to 9), + an_ac_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc, + pc_xu_abist_ena_dc => pc_xu_abist_ena_dc, + pc_xu_abist_wl32_comp_ena => pc_xu_abist_wl32_comp_ena, + pc_xu_abist_raw_dc_b => pc_xu_abist_raw_dc_b, + pc_xu_abist_g8t_dcomp => pc_xu_abist_g8t_dcomp, + pc_xu_bo_unload => pc_xu_bo_unload, + pc_xu_bo_repair => pc_xu_bo_repair, + pc_xu_bo_reset => pc_xu_bo_reset, + pc_xu_bo_shdata => pc_xu_bo_shdata, + pc_xu_bo_select => pc_xu_bo_select, + xu_pc_bo_fail => xu_pc_bo_fail, + xu_pc_bo_diagout => xu_pc_bo_diagout, + + an_ac_grffence_en_dc => an_ac_grffence_en_dc, + an_ac_coreid => an_ac_coreid, + pc_xu_init_reset => pc_xu_init_reset, + pc_xu_ccflush_dc => pc_xu_ccflush_dc, + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b, + an_ac_atpg_en_dc => an_ac_atpg_en_dc, + an_ac_scan_diag_dc => an_ac_scan_diag_dc, + an_ac_lbist_en_dc => an_ac_lbist_en_dc, + clkoff_dc_b => clkoff_dc_b_b, + sg_2 => sg_2_b(2 to 3), + fce_2 => fce_2_b(1), + func_sl_thold_2 => func_sl_thold_2_b(2 to 3), + func_nsl_thold_2 => func_nsl_thold_2_b, + func_slp_sl_thold_2 => func_slp_sl_thold_2_b(1), + func_slp_nsl_thold_2 => func_slp_nsl_thold_2_b, + cfg_slp_sl_thold_2 => cfg_slp_sl_thold_2_b, + ary_slp_nsl_thold_2 => ary_slp_nsl_thold_2, + regf_slp_sl_thold_2 => regf_slp_sl_thold_2_b, + abst_slp_sl_thold_2 => abst_slp_sl_thold_2, + time_sl_thold_2 => time_sl_thold_2_b, + repr_sl_thold_2 => repr_sl_thold_2_b, + bolt_sl_thold_2 => bolt_sl_thold_2_b, + bo_enable_2 => bo_enable_2_b, + d_mode_dc => d_mode_dc_b, + delay_lclkr_dc => delay_lclkr_dc_b, + mpw1_dc_b => mpw1_dc_b_b, + mpw2_dc_b => mpw2_dc_b_b, + g8t_clkoff_dc_b => g8t_clkoff_dc_b, + g8t_d_mode_dc => g8t_d_mode_dc, + g8t_delay_lclkr_dc => g8t_delay_lclkr_dc, + g8t_mpw1_dc_b => g8t_mpw1_dc_b, + g8t_mpw2_dc_b => g8t_mpw2_dc_b, + cam_clkoff_dc_b => cam_clkoff_dc_b, + cam_d_mode_dc => cam_d_mode_dc, + cam_delay_lclkr_dc => cam_delay_lclkr_dc, + cam_act_dis_dc => cam_act_dis_dc, + cam_mpw1_dc_b => cam_mpw1_dc_b, + cam_mpw2_dc_b => cam_mpw2_dc_b, + bcfg_scan_in => bcfg_scan_out_int, + bcfg_scan_out => bcfg_scan_out, + ccfg_scan_in => ccfg_scan_out_int, + ccfg_scan_out => ccfg_scan_out, + dcfg_scan_in => dcfg_scan_out_int, + dcfg_scan_out => dcfg_scan_out, + regf_scan_in => regf_scan_in, + regf_scan_out => regf_scan_out, + abst_scan_in => abst_scan_in, + time_scan_in => time_scan_in, + repr_scan_in => repr_scan_in, + abst_scan_out => abst_scan_out, + time_scan_out => time_scan_out, + repr_scan_out => repr_scan_out, + func_scan_in => func_scan_in(41 to 49), + func_scan_out => func_scan_out(41 to 49) +); + +xu_lsu_ex4_flush_local <= xu_lsu_ex4_flush_local_int; + +xu_rf1_is_eratre <= xu_rf1_is_eratre_int; +xu_rf1_is_eratwe <= xu_rf1_is_eratwe_int; +xu_rf1_is_eratsx <= xu_rf1_is_eratsx_int; +xu_rf1_is_eratsrx <= xu_rf1_is_eratsrx_int; +xu_rf1_is_eratilx <= xu_rf1_is_eratilx_int; +xu_rf1_is_erativax <= xu_rf1_is_erativax_int; +xu_ex1_is_isync <= xu_ex1_is_isync_int; +xu_ex1_is_csync <= xu_ex1_is_csync_int; +xu_rf1_ws <= xu_rf1_ws_int; +xu_rf1_t <= xu_rf1_t_int; +xu_ex1_rs_is <= xu_ex1_rs_is_int; +xu_ex1_ra_entry <= xu_ex1_ra_entry_int(8 to 11); +xu_ex4_rs_data <= xu_ex4_rs_data_int; +xu_lsu_ex1_eff_addr <= xu_ex1_eff_addr_int; +lsu_xu_rel_wren <= lsu_xu_rel_wren_int; +lsu_xu_rel_ta_gpr <= lsu_xu_rel_ta_gpr_int; +xu_lsu_rf1_axu_ldst_falign <= xu_lsu_rf1_axu_ldst_falign_int; + +end xuq_ctrl; diff --git a/rel/src/vhdl/work/xuq_ctrl_spr.vhdl b/rel/src/vhdl/work/xuq_ctrl_spr.vhdl new file mode 100644 index 0000000..389ed37 --- /dev/null +++ b/rel/src/vhdl/work/xuq_ctrl_spr.vhdl @@ -0,0 +1,2420 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XU Control and SPR +-- +library ieee,ibm,support,work,tri,clib; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use support.power_logic_pkg.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use tri.tri_latches_pkg.all; +use work.xuq_pkg.all; + +entity xuq_ctrl_spr is +generic( + expand_type : integer := 2; + threads : integer := 4; + eff_ifar : integer := 62; + spr_xucr0_init_mod : integer := 0; + uc_ifar : integer := 21; + regsize : integer := 64; + hvmode : integer := 1; + regmode : integer := 6; + dc_size : natural := 14; + cl_size : natural := 6; -- 2^6 = 64 Bytes CacheLines + real_data_add : integer := 42; + fxu_synth : integer := 0; + a2mode : integer := 1; + lmq_entries : integer := 8; + l_endian_m : integer := 1; + load_credits : integer := 4; + store_credits : integer := 20; + st_data_32B_mode : integer := 1; -- 0 = 16B store data to L2, 1 = 32B data + bcfg_epn_0to15 : integer := 0; + bcfg_epn_16to31 : integer := 0; + bcfg_epn_32to47 : integer := (2**16)-1; + bcfg_epn_48to51 : integer := (2**4)-1; + bcfg_rpn_22to31 : integer := (2**10)-1; + bcfg_rpn_32to47 : integer := (2**16)-1; + bcfg_rpn_48to51 : integer := (2**4)-1); +port( + + -------------------------------------------------------------------- + -- Interface with FXU A + -------------------------------------------------------------------- + fxa_fxb_rf0_val :in std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_issued :in std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_ucode_val :in std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_act :in std_ulogic; + fxa_fxb_ex1_hold_ctr_flush :in std_ulogic; + fxa_fxb_rf0_instr :in std_ulogic_vector(0 to 31); + fxa_fxb_rf0_tid :in std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_ta_vld :in std_ulogic; + fxa_fxb_rf0_ta :in std_ulogic_vector(0 to 7); + fxa_fxb_rf0_error :in std_ulogic_vector(0 to 2); + fxa_fxb_rf0_match :in std_ulogic; + fxa_fxb_rf0_is_ucode :in std_ulogic; + fxa_fxb_rf0_gshare :in std_ulogic_vector(0 to 3); + fxa_fxb_rf0_ifar :in std_ulogic_vector(62-eff_ifar to 61); + fxa_fxb_rf0_s1_vld :in std_ulogic; + fxa_fxb_rf0_s1 :in std_ulogic_vector(0 to 7); + fxa_fxb_rf0_s2_vld :in std_ulogic; + fxa_fxb_rf0_s2 :in std_ulogic_vector(0 to 7); + fxa_fxb_rf0_s3_vld :in std_ulogic; + fxa_fxb_rf0_s3 :in std_ulogic_vector(0 to 7); + fxa_fxb_rf0_axu_instr_type :in std_ulogic_vector(0 to 2); + fxa_fxb_rf0_axu_ld_or_st :in std_ulogic; + fxa_fxb_rf0_axu_store :in std_ulogic; + fxa_fxb_rf0_axu_ldst_forcealign :in std_ulogic; + fxa_fxb_rf0_axu_ldst_forceexcept :in std_ulogic; + fxa_fxb_rf0_axu_ldst_indexed :in std_ulogic; + fxa_fxb_rf0_axu_ldst_tag :in std_ulogic_vector(0 to 8); + fxa_fxb_rf0_axu_mftgpr :in std_ulogic; + fxa_fxb_rf0_axu_mffgpr :in std_ulogic; + fxa_fxb_rf0_axu_movedp :in std_ulogic; + fxa_fxb_rf0_axu_ldst_size :in std_ulogic_vector(0 to 5); + fxa_fxb_rf0_axu_ldst_update :in std_ulogic; + fxa_fxb_rf0_pred_update :in std_ulogic; + fxa_fxb_rf0_pred_taken_cnt :in std_ulogic_vector(0 to 1); + fxa_fxb_rf0_mc_dep_chk_val :in std_ulogic_vector(0 to threads-1); + fxa_fxb_rf1_mul_val :in std_ulogic; + fxa_fxb_rf1_div_val :in std_ulogic; + fxa_fxb_rf1_div_ctr :in std_ulogic_vector(0 to 7); + fxa_fxb_rf0_xu_epid_instr :in std_ulogic; + fxa_fxb_rf0_axu_is_extload :in std_ulogic; + fxa_fxb_rf0_axu_is_extstore :in std_ulogic; + fxa_fxb_rf0_is_mfocrf :in std_ulogic; + fxa_fxb_rf0_3src_instr :in std_ulogic; + fxa_fxb_rf0_gpr0_zero :in std_ulogic; + fxa_fxb_rf0_use_imm :in std_ulogic; + fxa_fxb_rf1_muldiv_coll :in std_ulogic; + fxa_cpl_ex2_div_coll :in std_ulogic_vector(0 to threads-1); + fxb_fxa_ex7_we0 :out std_ulogic; + fxb_fxa_ex7_wa0 :out std_ulogic_vector(0 to 7); + fxb_fxa_ex7_wd0 :out std_ulogic_vector(64-regsize to 63); + fxb_fxa_ex6_clear_barrier :out std_ulogic_vector(0 to threads-1); + fxa_fxb_rf1_do0 :in std_ulogic_vector(64-regsize to 63); + fxa_fxb_rf1_do1 :in std_ulogic_vector(64-regsize to 63); + fxa_fxb_rf1_do2 :in std_ulogic_vector(64-regsize to 63); + + xu_bx_ex1_mtdp_val :out std_ulogic; + xu_bx_ex1_mfdp_val :out std_ulogic; + xu_bx_ex1_ipc_thrd :out std_ulogic_vector(0 to 1); + xu_bx_ex2_ipc_ba :out std_ulogic_vector(0 to 4); + xu_bx_ex2_ipc_sz :out std_ulogic_vector(0 to 1); + + -------------------------------------------------------------------- + -- D-ERAT Req Interface + -------------------------------------------------------------------- + xu_mm_derat_epn :out std_ulogic_vector(62-eff_ifar to 51); + + ------------------------------------------------------------------------ + -- TLBSX./TLBSRX. + ------------------------------------------------------------------------ + xu_mm_rf1_is_tlbsxr :out std_ulogic; + mm_xu_cr0_eq_valid :in std_ulogic_vector(0 to threads-1); + mm_xu_cr0_eq :in std_ulogic_vector(0 to threads-1); + + -------------------------------------------------------------------- + -- FU CR Write + -------------------------------------------------------------------- + fu_xu_ex4_cr_val :in std_ulogic_vector(0 to threads-1); + fu_xu_ex4_cr_noflush :in std_ulogic_vector(0 to threads-1); + fu_xu_ex4_cr0 :in std_ulogic_vector(0 to 3); + fu_xu_ex4_cr0_bf :in std_ulogic_vector(0 to 2); + fu_xu_ex4_cr1 :in std_ulogic_vector(0 to 3); + fu_xu_ex4_cr1_bf :in std_ulogic_vector(0 to 2); + fu_xu_ex4_cr2 :in std_ulogic_vector(0 to 3); + fu_xu_ex4_cr2_bf :in std_ulogic_vector(0 to 2); + fu_xu_ex4_cr3 :in std_ulogic_vector(0 to 3); + fu_xu_ex4_cr3_bf :in std_ulogic_vector(0 to 2); + + -------------------------------------------------------------------- + -- RAM + -------------------------------------------------------------------- + pc_xu_ram_mode :in std_ulogic; + pc_xu_ram_thread :in std_ulogic_vector(0 to 1); + pc_xu_ram_execute :in std_ulogic; + pc_xu_ram_flush_thread :in std_ulogic; + xu_iu_ram_issue :out std_ulogic_vector(0 to threads-1); + xu_pc_ram_interrupt :out std_ulogic; + xu_pc_ram_done :out std_ulogic; + xu_pc_ram_data :out std_ulogic_vector(64-(2**regmode) to 63); + pc_xu_msrovride_enab :in std_ulogic; + pc_xu_msrovride_gs :in std_ulogic; + pc_xu_msrovride_de :in std_ulogic; + + + -------------------------------------------------------------------- + -- Interface with IU + -------------------------------------------------------------------- + xu_iu_ex5_val :out std_ulogic; + xu_iu_ex5_tid :out std_ulogic_vector(0 to threads-1); + xu_iu_ex5_br_update :out std_ulogic; + xu_iu_ex5_br_hist :out std_ulogic_vector(0 to 1); + xu_iu_ex5_bclr :out std_ulogic; + xu_iu_ex5_lk :out std_ulogic; + xu_iu_ex5_bh :out std_ulogic_vector(0 to 1); + xu_iu_ex6_pri :out std_ulogic_vector(0 to 2); + xu_iu_ex6_pri_val :out std_ulogic_vector(0 to 3); + xu_iu_spr_xer :out std_ulogic_vector(0 to 7*threads-1); + xu_iu_slowspr_done :out std_ulogic_vector(0 to threads-1); + xu_iu_need_hole :out std_ulogic; + xu_iu_ex5_gshare :out std_ulogic_vector(0 to 3); + xu_iu_ex5_getNIA :out std_ulogic; + + ------------------------------------------------------------------------ + -- L2 STCX complete + ------------------------------------------------------------------------ + an_ac_stcx_complete :in std_ulogic_vector(0 to threads-1); + an_ac_stcx_pass :in std_ulogic_vector(0 to threads-1); + xu_iu_stcx_complete : out std_ulogic_vector(0 to 3); + xu_iu_reld_core_tag_clone :out std_ulogic_vector(1 to 4); + xu_iu_reld_data_coming_clone :out std_ulogic; + xu_iu_reld_data_vld_clone :out std_ulogic; + xu_iu_reld_ditc_clone :out std_ulogic; + + ------------------------------------------------------------------------ + -- Slow SPR Bus + ------------------------------------------------------------------------ + slowspr_val_in :in std_ulogic; + slowspr_rw_in :in std_ulogic; + slowspr_etid_in :in std_ulogic_vector(0 to 1); + slowspr_addr_in :in std_ulogic_vector(0 to 9); + slowspr_data_in :in std_ulogic_vector(64-(2**regmode) to 63); + slowspr_done_in :in std_ulogic; + slowspr_val_out :out std_ulogic; + slowspr_rw_out :out std_ulogic; + slowspr_etid_out :out std_ulogic_vector(0 to 1); + slowspr_addr_out :out std_ulogic_vector(0 to 9); + slowspr_data_out :out std_ulogic_vector(64-(2**REGMODE) to 63); + slowspr_done_out :out std_ulogic; + + ------------------------------------------------------------------------ + -- DCR Bus + ------------------------------------------------------------------------ + an_ac_dcr_act :in std_ulogic; + an_ac_dcr_val :in std_ulogic; + an_ac_dcr_read :in std_ulogic; + an_ac_dcr_etid :in std_ulogic_vector(0 to 1); + an_ac_dcr_data :in std_ulogic_vector(64-(2**regmode) to 63); + an_ac_dcr_done :in std_ulogic; + + ------------------------------------------------------------------------ + -- MT/MFDCR CR + ------------------------------------------------------------------------ + lsu_xu_ex4_mtdp_cr_status :in std_ulogic; + lsu_xu_ex4_mfdp_cr_status :in std_ulogic; + dec_cpl_ex3_mc_dep_chk_val :in std_ulogic_vector(0 to threads-1); + + ------------------------------------------------------------------------ + -- Perf Events + ------------------------------------------------------------------------ + xu_pc_event_data :out std_ulogic_vector(0 to 7); + + ------------------------------------------------------------------------ + -- PC Control Interface + ------------------------------------------------------------------------ + pc_xu_event_count_mode :in std_ulogic_vector(0 to 2); + pc_xu_event_mux_ctrls :in std_ulogic_vector(0 to 47); + + ------------------------------------------------------------------------ + -- Debug Ramp & Controls + ------------------------------------------------------------------------ + fxu_debug_mux_ctrls :in std_ulogic_vector(0 to 15); + cpl_debug_mux_ctrls :in std_ulogic_vector(0 to 15); + lsu_debug_mux_ctrls :in std_ulogic_vector(0 to 15); + spr_debug_mux_ctrls :in std_ulogic_vector(0 to 15); + trigger_data_in :in std_ulogic_vector(0 to 11); + trigger_data_out :out std_ulogic_vector(0 to 11); + debug_data_in :in std_ulogic_vector(0 to 87); + debug_data_out :out std_ulogic_vector(0 to 87); + lsu_xu_data_debug0 :in std_ulogic_vector(0 to 87); + lsu_xu_data_debug1 :in std_ulogic_vector(0 to 87); + lsu_xu_data_debug2 :in std_ulogic_vector(0 to 87); + fxa_cpl_debug :in std_ulogic_vector(0 to 272); + + ------------------------------------------------------------------------ + -- SPR Bits + ------------------------------------------------------------------------ + + -- CHIP IO + ac_tc_debug_trigger :out std_ulogic_vector(0 to threads-1); + + -- Valids + dec_cpl_rf0_act :in std_ulogic; + dec_cpl_rf0_tid :in std_ulogic_vector(0 to threads-1); + + -- FU Inputs + fu_xu_rf1_act :in std_ulogic_vector(0 to threads-1); + fu_xu_ex1_ifar :in std_ulogic_vector(0 to eff_ifar*threads-1); + fu_xu_ex2_ifar_val :in std_ulogic_vector(0 to threads-1); + fu_xu_ex2_ifar_issued :in std_ulogic_vector(0 to threads-1); + fu_xu_ex2_instr_type :in std_ulogic_vector(0 to 3*threads-1); + fu_xu_ex2_instr_match :in std_ulogic_vector(0 to threads-1); + fu_xu_ex2_is_ucode :in std_ulogic_vector(0 to threads-1); + + -- PC Inputs + pc_xu_step :in std_ulogic_vector(0 to threads-1); + pc_xu_stop :in std_ulogic_vector(0 to threads-1); + pc_xu_dbg_action :in std_ulogic_vector(0 to 3*threads-1); + pc_xu_force_ude :in std_ulogic_vector(0 to threads-1); + xu_pc_step_done :out std_ulogic_vector(0 to threads-1); + pc_xu_init_reset :in std_ulogic; + + -- Machine Check Interrupts + mm_xu_local_snoop_reject :in std_ulogic_vector(0 to threads-1); + mm_xu_lru_par_err :in std_ulogic_vector(0 to threads-1); + mm_xu_tlb_par_err :in std_ulogic_vector(0 to threads-1); + mm_xu_tlb_multihit_err :in std_ulogic_vector(0 to threads-1); + an_ac_external_mchk :in std_ulogic_vector(0 to threads-1); + + -- PC Errors + xu_pc_err_attention_instr :out std_ulogic_vector(0 to threads-1); + xu_pc_err_nia_miscmpr :out std_ulogic_vector(0 to threads-1); + xu_pc_err_debug_event :out std_ulogic_vector(0 to threads-1); + + -- Run State + xu_pc_stop_dbg_event :out std_ulogic_vector(0 to threads-1); + + -- MMU Flushes + mm_xu_illeg_instr :in std_ulogic_vector(0 to threads-1); + mm_xu_tlb_miss :in std_ulogic_vector(0 to threads-1); + mm_xu_pt_fault :in std_ulogic_vector(0 to threads-1); + mm_xu_tlb_inelig :in std_ulogic_vector(0 to threads-1); + mm_xu_lrat_miss :in std_ulogic_vector(0 to threads-1); + mm_xu_hv_priv :in std_ulogic_vector(0 to threads-1); + mm_xu_esr_pt :in std_ulogic_vector(0 to threads-1); + mm_xu_esr_data :in std_ulogic_vector(0 to threads-1); + mm_xu_esr_epid :in std_ulogic_vector(0 to threads-1); + mm_xu_esr_st :in std_ulogic_vector(0 to threads-1); + mm_xu_hold_req :in std_ulogic_vector(0 to threads-1); + mm_xu_hold_done :in std_ulogic_vector(0 to threads-1); + xu_mm_hold_ack :out std_ulogic_vector(0 to threads-1); + mm_xu_eratmiss_done :in std_ulogic_vector(0 to threads-1); + mm_xu_ex3_flush_req :in std_ulogic_vector(0 to threads-1); + + -- AXU Flushes + fu_xu_ex3_ap_int_req :in std_ulogic_vector(0 to threads-1); + fu_xu_ex3_trap :in std_ulogic_vector(0 to threads-1); + fu_xu_ex3_n_flush :in std_ulogic_vector(0 to threads-1); + fu_xu_ex3_np1_flush :in std_ulogic_vector(0 to threads-1); + fu_xu_ex3_flush2ucode :in std_ulogic_vector(0 to threads-1); + fu_xu_ex2_async_block :in std_ulogic_vector(0 to threads-1); + + -- IU Flushes + xu_iu_ex5_br_taken :out std_ulogic; + xu_iu_ex5_ifar :out std_ulogic_vector(62-eff_ifar to 61); + xu_iu_flush :out std_ulogic_vector(0 to threads-1); + xu_iu_iu0_flush_ifar :out std_ulogic_vector(0 to eff_ifar*threads-1); + xu_iu_uc_flush_ifar :out std_ulogic_vector(0 to uc_ifar*threads-1); + xu_iu_flush_2ucode :out std_ulogic_vector(0 to threads-1); + xu_iu_flush_2ucode_type :out std_ulogic_vector(0 to threads-1); + xu_iu_ucode_restart :out std_ulogic_vector(0 to threads-1); + xu_iu_ex5_ppc_cpl :out std_ulogic_vector(0 to threads-1); + + -- Flushes + xu_n_is2_flush :out std_ulogic_vector(0 to threads-1); + xu_n_rf0_flush :out std_ulogic_vector(0 to threads-1); + xu_n_rf1_flush :out std_ulogic_vector(0 to threads-1); + xu_n_ex1_flush :out std_ulogic_vector(0 to threads-1); + xu_n_ex2_flush :out std_ulogic_vector(0 to threads-1); + xu_n_ex3_flush :out std_ulogic_vector(0 to threads-1); + xu_n_ex4_flush :out std_ulogic_vector(0 to threads-1); + xu_n_ex5_flush :out std_ulogic_vector(0 to threads-1); + + xu_s_rf1_flush :out std_ulogic_vector(0 to threads-1); + xu_s_ex1_flush :out std_ulogic_vector(0 to threads-1); + xu_s_ex2_flush :out std_ulogic_vector(0 to threads-1); + xu_s_ex3_flush :out std_ulogic_vector(0 to threads-1); + xu_s_ex4_flush :out std_ulogic_vector(0 to threads-1); + xu_s_ex5_flush :out std_ulogic_vector(0 to threads-1); + + xu_w_rf1_flush :out std_ulogic_vector(0 to threads-1); + xu_w_ex1_flush :out std_ulogic_vector(0 to threads-1); + xu_w_ex2_flush :out std_ulogic_vector(0 to threads-1); + xu_w_ex3_flush :out std_ulogic_vector(0 to threads-1); + xu_w_ex4_flush :out std_ulogic_vector(0 to threads-1); + xu_w_ex5_flush :out std_ulogic_vector(0 to threads-1); + + xu_lsu_ex4_flush_local :out std_ulogic_vector(0 to threads-1); + xu_mm_ex4_flush :out std_ulogic_vector(0 to threads-1); + xu_mm_ex5_flush :out std_ulogic_vector(0 to threads-1); + xu_mm_ierat_flush :out std_ulogic_vector(0 to threads-1); + xu_mm_ierat_miss :out std_ulogic_vector(0 to threads-1); + xu_mm_ex5_perf_itlb :out std_ulogic_vector(0 to threads-1); + xu_mm_ex5_perf_dtlb :out std_ulogic_vector(0 to threads-1); + + -- SPR Bits + spr_xucr4_div_barr_thres :out std_ulogic_vector(0 to 7); + + iu_xu_ierat_ex2_flush_req :in std_ulogic_vector(0 to threads-1); + -- Parity + iu_xu_ierat_ex3_par_err :in std_ulogic_vector(0 to threads-1); + iu_xu_ierat_ex4_par_err :in std_ulogic_vector(0 to threads-1); + + -- Regfile Parity + fu_xu_ex3_regfile_err_det :in std_ulogic_vector(0 to threads-1); + xu_fu_regfile_seq_beg :out std_ulogic; + fu_xu_regfile_seq_end :in std_ulogic; + gpr_cpl_ex3_regfile_err_det :in std_ulogic; + cpl_gpr_regfile_seq_beg :out std_ulogic; + gpr_cpl_regfile_seq_end :in std_ulogic; + xu_pc_err_mcsr_summary :out std_ulogic_vector(0 to threads-1); + xu_pc_err_ditc_overrun :out std_ulogic; + xu_pc_err_local_snoop_reject :out std_ulogic; + xu_pc_err_tlb_lru_parity :out std_ulogic; + xu_pc_err_ext_mchk :out std_ulogic; + xu_pc_err_ierat_multihit :out std_ulogic; + xu_pc_err_derat_multihit :out std_ulogic; + xu_pc_err_tlb_multihit :out std_ulogic; + xu_pc_err_ierat_parity :out std_ulogic; + xu_pc_err_derat_parity :out std_ulogic; + xu_pc_err_tlb_parity :out std_ulogic; + xu_pc_err_mchk_disabled :out std_ulogic; + + -- Debug + xu_iu_rf1_val :out std_ulogic_vector(0 to threads-1); + xu_rf1_val :out std_ulogic_vector(0 to threads-1); + xu_rf1_is_tlbre :out std_ulogic; + xu_rf1_is_tlbwe :out std_ulogic; + xu_rf1_is_tlbsx :out std_ulogic; + xu_rf1_is_tlbsrx :out std_ulogic; + xu_rf1_is_tlbilx :out std_ulogic; + xu_rf1_is_tlbivax :out std_ulogic; + xu_rf1_is_eratre :out std_ulogic; + xu_rf1_is_eratwe :out std_ulogic; + xu_rf1_is_eratsx :out std_ulogic; + xu_rf1_is_eratilx :out std_ulogic; + xu_rf1_is_erativax :out std_ulogic; + xu_ex1_is_isync :out std_ulogic; + xu_ex1_is_csync :out std_ulogic; + xu_rf1_ws :out std_ulogic_vector(0 to 1); + xu_rf1_t :out std_ulogic_vector(0 to 2); + xu_ex1_rs_is :out std_ulogic_vector(0 to 8); + xu_ex1_ra_entry :out std_ulogic_vector(8 to 11); + xu_ex4_rs_data :out std_ulogic_vector(64-(2**regmode) to 63); + + xu_lsu_rf1_data_act :out std_ulogic; + xu_lsu_rf1_axu_ldst_falign :out std_ulogic; + xu_lsu_ex1_store_data :out std_ulogic_vector(64-(2**regmode) to 63); + xu_lsu_ex1_rotsel_ovrd :out std_ulogic_vector(0 to 4); + xu_lsu_ex1_eff_addr :out std_ulogic_vector(64-(dc_size-3) to 63); + + -- Barrier + cpl_fxa_ex5_set_barr :out std_ulogic_vector(0 to threads-1); + cpl_iu_set_barr_tid :out std_ulogic_vector(0 to threads-1); + + lsu_xu_ex6_datc_par_err :in std_ulogic; + + lsu_xu_ex2_dvc1_st_cmp :in std_ulogic_vector(8-(2**regmode)/8 to 7); + lsu_xu_ex2_dvc2_st_cmp :in std_ulogic_vector(8-(2**regmode)/8 to 7); + lsu_xu_ex8_dvc1_ld_cmp :in std_ulogic_vector(8-(2**regmode)/8 to 7); + lsu_xu_ex8_dvc2_ld_cmp :in std_ulogic_vector(8-(2**regmode)/8 to 7); + lsu_xu_rel_dvc1_en :in std_ulogic; + lsu_xu_rel_dvc2_en :in std_ulogic; + lsu_xu_rel_dvc_thrd_id :in std_ulogic_vector(0 to 3); + lsu_xu_rel_dvc1_cmp :in std_ulogic_vector(8-(2**regmode)/8 to 7); + lsu_xu_rel_dvc2_cmp :in std_ulogic_vector(8-(2**regmode)/8 to 7); + + lsu_xu_rot_ex6_data_b :in std_ulogic_vector(64-(2**regmode) to 63); + lsu_xu_rot_rel_data :in std_ulogic_vector(64-(2**regmode) to 63); + pc_xu_trace_bus_enable :in std_ulogic; + pc_xu_instr_trace_mode :in std_ulogic; + pc_xu_instr_trace_tid :in std_ulogic_vector(0 to 1); + iu_xu_ex4_tlb_data :in std_ulogic_vector(64-(2**regmode) to 63); + + -- Error Inject + pc_xu_inj_dcachedir_parity :in std_ulogic; + pc_xu_inj_dcachedir_multihit :in std_ulogic; + + ex4_256st_data :in std_ulogic_vector(0 to 255); + + an_ac_flh2l2_gate :in std_ulogic; -- Gate L1 Hit forwarding SPR config bit + + -- ERAT Operations + xu_lsu_rf0_derat_val :in std_ulogic_vector(0 to 3); -- TLB Valid Operation + xu_lsu_rf0_derat_is_extload :in std_ulogic; -- Cache access should be treated as an external load + xu_lsu_rf0_derat_is_extstore :in std_ulogic; -- Cache access should be treated as an external store + xu_lsu_hid_mmu_mode :in std_ulogic; -- MMU mode + ex6_ld_par_err :in std_ulogic; + + xu_mm_derat_req :out std_ulogic; + xu_mm_derat_thdid :out std_ulogic_vector(0 to 3); + xu_mm_derat_state :out std_ulogic_vector(0 to 3); + xu_mm_derat_tid :out std_ulogic_vector(0 to 13); + xu_mm_derat_lpid :out std_ulogic_vector(0 to 7); + xu_mm_derat_ttype :out std_ulogic_vector(0 to 1); + mm_xu_derat_rel_val :in std_ulogic_vector(0 to 4); + mm_xu_derat_rel_data :in std_ulogic_vector(0 to 131); + mm_xu_derat_pid0 :in std_ulogic_vector(0 to 13); -- Thread0 PID Number + mm_xu_derat_pid1 :in std_ulogic_vector(0 to 13); -- Thread1 PID Number + mm_xu_derat_pid2 :in std_ulogic_vector(0 to 13); -- Thread2 PID Number + mm_xu_derat_pid3 :in std_ulogic_vector(0 to 13); -- Thread3 PID Number + mm_xu_derat_mmucr0_0 :in std_ulogic_vector(0 to 19); + mm_xu_derat_mmucr0_1 :in std_ulogic_vector(0 to 19); + mm_xu_derat_mmucr0_2 :in std_ulogic_vector(0 to 19); + mm_xu_derat_mmucr0_3 :in std_ulogic_vector(0 to 19); + xu_mm_derat_mmucr0 :out std_ulogic_vector(0 to 17); + xu_mm_derat_mmucr0_we :out std_ulogic_vector(0 to 3); + mm_xu_derat_mmucr1 :in std_ulogic_vector(0 to 9); + xu_mm_derat_mmucr1 :out std_ulogic_vector(0 to 4); + xu_mm_derat_mmucr1_we :out std_ulogic; + mm_xu_derat_snoop_coming :in std_ulogic; + mm_xu_derat_snoop_val :in std_ulogic; + mm_xu_derat_snoop_attr :in std_ulogic_vector(0 to 25); + mm_xu_derat_snoop_vpn :in std_ulogic_vector(64-(2**REGMODE) to 51); + xu_mm_derat_snoop_ack :out std_ulogic; + + ex1_optype1 :out std_ulogic; + ex1_optype2 :out std_ulogic; + ex1_optype4 :out std_ulogic; + ex1_optype8 :out std_ulogic; + ex1_optype16 :out std_ulogic; + ex1_optype32 :out std_ulogic; + ex1_saxu_instr :out std_ulogic; + ex1_sdp_instr :out std_ulogic; + ex1_stgpr_instr :out std_ulogic; + ex1_store_instr :out std_ulogic; + ex1_axu_op_val :out std_ulogic; + + ex3_algebraic :out std_ulogic; + ex3_data_swap :out std_ulogic; + ex3_thrd_id :out std_ulogic_vector(0 to 3); + xu_fu_ex3_eff_addr :out std_ulogic_vector(59 to 63); + xu_lsu_ici :out std_ulogic; + + -- Update Data Array Valid + rel_upd_dcarr_val :out std_ulogic; + + xu_fu_ex5_reload_val :out std_ulogic; + xu_fu_ex5_load_val :out std_ulogic_vector(0 to 3); + xu_fu_ex5_load_tag :out std_ulogic_vector(0 to 8); + + -- Data Array Controls + dcarr_up_way_addr :out std_ulogic_vector(0 to 2); + + -- Debug Data Compare + ex4_load_op_hit :out std_ulogic; + ex4_store_hit :out std_ulogic; + ex4_axu_op_val :out std_ulogic; + spr_dvc1_act :out std_ulogic; + spr_dvc2_act :out std_ulogic; + spr_dvc1_dbg :out std_ulogic_vector(64-(2**regmode) to 63); + spr_dvc2_dbg :out std_ulogic_vector(64-(2**regmode) to 63); + + -- Inputs from L2 + an_ac_req_ld_pop :in std_ulogic; + an_ac_req_st_pop :in std_ulogic; + an_ac_req_st_gather :in std_ulogic; + an_ac_req_st_pop_thrd :in std_ulogic_vector(0 to 2); -- decrement outbox credit count + + an_ac_reld_data_vld :in std_ulogic; + an_ac_reld_core_tag :in std_ulogic_vector(0 to 4); + an_ac_reld_qw :in std_ulogic_vector(57 to 59); + an_ac_reld_data :in std_ulogic_vector(0 to 127); + an_ac_reld_data_coming :in std_ulogic; + an_ac_reld_ditc :in std_ulogic; + an_ac_reld_crit_qw :in std_ulogic; + an_ac_reld_l1_dump :in std_ulogic; + + an_ac_reld_ecc_err :in std_ulogic; + an_ac_reld_ecc_err_ue :in std_ulogic; + + an_ac_back_inv :in std_ulogic; + an_ac_back_inv_addr :in std_ulogic_vector(64-real_data_add to 63); + an_ac_back_inv_target_bit1 :in std_ulogic; + an_ac_back_inv_target_bit3 :in std_ulogic; + an_ac_back_inv_target_bit4 :in std_ulogic; + an_ac_req_spare_ctrl_a1 :in std_ulogic_vector(0 to 3); + + + -- redrive to boxes logic + lsu_reld_data_vld :out std_ulogic; -- reload data is coming in 2 cycles + lsu_reld_core_tag :out std_ulogic_vector(3 to 4); -- reload data destinatoin tag (thread) + lsu_reld_qw :out std_ulogic_vector(58 to 59); -- reload data destinatoin tag (thread) + lsu_reld_ditc :out std_ulogic; -- reload data is for ditc (inbox) + lsu_reld_ecc_err :out std_ulogic; -- reload data has ecc error + lsu_reld_data :out std_ulogic_vector(0 to 127); -- reload data + + lsu_req_st_pop :out std_ulogic; -- decrement outbox credit count + lsu_req_st_pop_thrd :out std_ulogic_vector(0 to 2); -- decrement outbox credit count + + -- redrive for boxes logic + ac_an_reld_ditc_pop_int : in std_ulogic_vector(0 to 3); + ac_an_reld_ditc_pop_q : out std_ulogic_vector(0 to 3); + bx_ib_empty_int : in std_ulogic_vector(0 to 3); + bx_ib_empty_q : out std_ulogic_vector(0 to 3); + + -- Instruction Fetches + iu_xu_ra :in std_ulogic_vector(64-real_data_add to 59); + iu_xu_request :in std_ulogic; + iu_xu_wimge :in std_ulogic_vector(0 to 4); + iu_xu_thread :in std_ulogic_vector(0 to 3); + iu_xu_userdef :in std_ulogic_vector(0 to 3); + + -- MMU instruction interface + mm_xu_lsu_req :in std_ulogic_vector(0 to 3); + mm_xu_lsu_ttype :in std_ulogic_vector(0 to 1); + mm_xu_lsu_wimge :in std_ulogic_vector(0 to 4); + mm_xu_lsu_u :in std_ulogic_vector(0 to 3); + mm_xu_lsu_addr :in std_ulogic_vector(64-real_data_add to 63); + mm_xu_lsu_lpid :in std_ulogic_vector(0 to 7); + mm_xu_lsu_lpidr :in std_ulogic_vector(0 to 7); + mm_xu_lsu_gs :in std_ulogic; + mm_xu_lsu_ind :in std_ulogic; + mm_xu_lsu_lbit :in std_ulogic; -- "L" bit, for large vs. small + xu_mm_lsu_token :out std_ulogic; + + -- Boxes interface + bx_lsu_ob_pwr_tok :in std_ulogic; + bx_lsu_ob_req_val :in std_ulogic; -- message buff data is ready to send + bx_lsu_ob_ditc_val :in std_ulogic; -- send dtic command + bx_lsu_ob_thrd :in std_ulogic_vector(0 to 1); -- source thread + bx_lsu_ob_qw :in std_ulogic_vector(58 to 59); -- QW address + bx_lsu_ob_dest :in std_ulogic_vector(0 to 14); -- destination for the packet + bx_lsu_ob_data :in std_ulogic_vector(0 to 127); -- 16B of data from the outbox + bx_lsu_ob_addr :in std_ulogic_vector(64-real_data_add to 57); -- address for boxes message + lsu_bx_cmd_avail :out std_ulogic; + lsu_bx_cmd_sent :out std_ulogic; + lsu_bx_cmd_stall :out std_ulogic; + + lsu_xu_ldq_barr_done :out std_ulogic_vector(0 to 3); -- LWSYNC/mbar internal acknowledgements + lsu_xu_barr_done :out std_ulogic_vector(0 to 3); + + -- *** Reload operation Outputs *** + ldq_rel_data_val_early :out std_ulogic; + ldq_rel_op_size :out std_ulogic_vector(0 to 5); + ldq_rel_addr :out std_ulogic_vector(64-(dc_size-3) to 58); + ldq_rel_data_val :out std_ulogic; + ldq_rel_rot_sel :out std_ulogic_vector(0 to 4); + ldq_rel_axu_val :out std_ulogic; + ldq_rel_ci :out std_ulogic; + ldq_rel_thrd_id :out std_ulogic_vector(0 to 3); + ldq_rel_le_mode :out std_ulogic; + ldq_rel_algebraic :out std_ulogic; + ldq_rel_256_data :out std_ulogic_vector(0 to 255); + + ldq_rel_dvc1_en :out std_ulogic; + ldq_rel_dvc2_en :out std_ulogic; + ldq_rel_beat_crit_qw :out std_ulogic; + ldq_rel_beat_crit_qw_block :out std_ulogic; -- Reload Data had an ecc error + lsu_xu_rel_wren :out std_ulogic; + lsu_xu_rel_ta_gpr :out std_ulogic_vector(0 to 7); + + xu_iu_ex4_loadmiss_qentry :out std_ulogic_vector(0 to lmq_entries-1); + xu_iu_ex4_loadmiss_target :out std_ulogic_vector(0 to 8); + xu_iu_ex4_loadmiss_target_type :out std_ulogic_vector(0 to 1); + xu_iu_ex4_loadmiss_tid :out std_ulogic_vector(0 to 3); + xu_iu_ex5_loadmiss_qentry :out std_ulogic_vector(0 to lmq_entries-1); + xu_iu_ex5_loadmiss_target :out std_ulogic_vector(0 to 8); + xu_iu_ex5_loadmiss_target_type :out std_ulogic_vector(0 to 1); + xu_iu_ex5_loadmiss_tid :out std_ulogic_vector(0 to 3); + xu_iu_complete_qentry :out std_ulogic_vector(0 to lmq_entries-1); + xu_iu_complete_tid :out std_ulogic_vector(0 to 3); + xu_iu_complete_target_type :out std_ulogic_vector(0 to 1); + + -- ICBI Interface + xu_iu_ex6_icbi_val :out std_ulogic_vector(0 to 3); + xu_iu_ex6_icbi_addr :out std_ulogic_vector(64-real_data_add to 57); + + xu_iu_larx_done_tid :out std_ulogic_vector(0 to 3); + xu_mm_lmq_stq_empty :out std_ulogic; + xu_ex1_rb :out std_ulogic_vector(64-(2**regmode) to 51); + xu_ex2_eff_addr :out std_ulogic_vector(64-(2**regmode) to 63); + + ac_an_req_pwr_token :out std_ulogic; + ac_an_req :out std_ulogic; + ac_an_req_ra :out std_ulogic_vector(64-real_data_add to 63); + ac_an_req_ttype :out std_ulogic_vector(0 to 5); + ac_an_req_thread :out std_ulogic_vector(0 to 2); + ac_an_req_wimg_w :out std_ulogic; + ac_an_req_wimg_i :out std_ulogic; + ac_an_req_wimg_m :out std_ulogic; + ac_an_req_wimg_g :out std_ulogic; + ac_an_req_endian :out std_ulogic; + ac_an_req_user_defined :out std_ulogic_vector(0 to 3); + ac_an_req_spare_ctrl_a0 :out std_ulogic_vector(0 to 3); + ac_an_req_ld_core_tag :out std_ulogic_vector(0 to 4); + ac_an_req_ld_xfr_len :out std_ulogic_vector(0 to 2); + ac_an_st_byte_enbl :out std_ulogic_vector(0 to 15+(st_data_32B_mode*16)); + ac_an_st_data :out std_ulogic_vector(0 to 127+(st_data_32B_mode*128)); + ac_an_st_data_pwr_token :out std_ulogic; + + --pervasive + xu_pc_err_dcachedir_parity :out std_ulogic; + xu_pc_err_dcachedir_multihit :out std_ulogic; + xu_pc_err_l2intrf_ecc :out std_ulogic; + xu_pc_err_l2intrf_ue :out std_ulogic; + xu_pc_err_invld_reld :out std_ulogic; + xu_pc_err_l2credit_overrun :out std_ulogic; + + -- Performance Counters + pc_xu_event_bus_enable :in std_ulogic; + pc_xu_lsu_event_mux_ctrls :in std_ulogic_vector(0 to 47); + pc_xu_cache_par_err_event :in std_ulogic; + xu_pc_lsu_event_data :out std_ulogic_vector(0 to 7); + fxa_perf_muldiv_in_use :in std_ulogic; + + -- Decode + dec_spr_rf0_tid :in std_ulogic_vector(0 to threads-1); + dec_spr_rf0_instr :in std_ulogic_vector(0 to 31); + + -- DCR Bus + ac_an_dcr_act :out std_ulogic; + ac_an_dcr_val :out std_ulogic; + ac_an_dcr_read :out std_ulogic; + ac_an_dcr_user :out std_ulogic; + ac_an_dcr_etid :out std_ulogic_vector(0 to 1); + ac_an_dcr_addr :out std_ulogic_vector(11 to 20); + ac_an_dcr_data :out std_ulogic_vector(64-regsize to 63); + + -- Run State + xu_pc_running :out std_ulogic_vector(0 to threads-1); + xu_iu_run_thread :out std_ulogic_vector(0 to threads-1); + xu_iu_single_instr_mode :out std_ulogic_vector(0 to threads-1); + xu_iu_raise_iss_pri :out std_ulogic_vector(0 to threads-1); + xu_pc_spr_ccr0_we :out std_ulogic_vector(0 to threads-1); + + -- Quiesce + iu_xu_quiesce :in std_ulogic_vector(0 to threads-1); + mm_xu_quiesce :in std_ulogic_vector(0 to threads-1); + bx_xu_quiesce :in std_ulogic_vector(0 to threads-1); + + -- PCCR0 + pc_xu_extirpts_dis_on_stop :in std_ulogic; + pc_xu_timebase_dis_on_stop :in std_ulogic; + pc_xu_decrem_dis_on_stop :in std_ulogic; + + -- MSR Override + pc_xu_msrovride_pr :in std_ulogic; + + -- LiveLock + xu_pc_err_llbust_attempt :out std_ulogic_vector(0 to threads-1); + xu_pc_err_llbust_failed :out std_ulogic_vector(0 to threads-1); + + -- Resets + pc_xu_reset_wd_complete :in std_ulogic; + pc_xu_reset_1_complete :in std_ulogic; + pc_xu_reset_2_complete :in std_ulogic; + pc_xu_reset_3_complete :in std_ulogic; + ac_tc_reset_1_request :out std_ulogic; + ac_tc_reset_2_request :out std_ulogic; + ac_tc_reset_3_request :out std_ulogic; + ac_tc_reset_wd_request :out std_ulogic; + + -- Err Inject + pc_xu_inj_llbust_attempt :in std_ulogic_vector(0 to threads-1); + pc_xu_inj_llbust_failed :in std_ulogic_vector(0 to threads-1); + pc_xu_inj_wdt_reset :in std_ulogic_vector(0 to threads-1); + xu_pc_err_wdt_reset :out std_ulogic_vector(0 to threads-1); + + -- Parity + pc_xu_inj_sprg_ecc :in std_ulogic_vector(0 to threads-1); + xu_pc_err_sprg_ecc :out std_ulogic_vector(0 to threads-1); + xu_pc_err_sprg_ue :out std_ulogic_vector(0 to threads-1); + + -- SPRs + spr_msr_is :out std_ulogic_vector(0 to threads-1); + spr_msr_gs :out std_ulogic_vector(0 to threads-1); + spr_msr_pr :out std_ulogic_vector(0 to threads-1); + spr_msr_ds :out std_ulogic_vector(0 to threads-1); + spr_msr_cm :out std_ulogic_vector(0 to threads-1); + spr_msr_fp :out std_ulogic_vector(0 to threads-1); + spr_msr_spv :out std_ulogic_vector(0 to threads-1); + spr_ccr2_ap :out std_ulogic_vector(0 to threads-1); + spr_ccr2_en_dcr :out std_ulogic; + spr_ccr2_notlb :out std_ulogic; + spr_ccr2_en_ditc :out std_ulogic; + xu_lsu_spr_xucr0_dcdis :out std_ulogic; + xu_lsu_spr_xucr0_rel :out std_ulogic; + xu_pc_spr_ccr0_pme :out std_ulogic_vector(0 to 1); + xu_iu_spr_ccr2_ifratsc :out std_ulogic_vector(0 to 8); + xu_iu_spr_ccr2_ifrat :out std_ulogic; + spr_xucr0_clkg_ctl_b0 :out std_ulogic; + xu_mm_spr_epcr_dmiuh :out std_ulogic_vector(0 to threads-1); + xu_mm_spr_epcr_dgtmi :out std_ulogic_vector(0 to threads-1); + cpl_msr_gs :out std_ulogic_vector(0 to threads-1); + cpl_msr_pr :out std_ulogic_vector(0 to threads-1); + cpl_msr_fp :out std_ulogic_vector(0 to threads-1); + cpl_msr_spv :out std_ulogic_vector(0 to threads-1); + cpl_ccr2_ap :out std_ulogic_vector(0 to threads-1); + spr_xucr4_mmu_mchk :out std_ulogic; + + --------------------------------------------------------------------- + -- Pervasive + --------------------------------------------------------------------- + pc_xu_bolt_sl_thold_3 :in std_ulogic; + pc_xu_bo_enable_3 :in std_ulogic; + bolt_sl_thold_2 :out std_ulogic; + bo_enable_2 :out std_ulogic; + pc_xu_bo_unload :in std_ulogic; + pc_xu_bo_repair :in std_ulogic; + pc_xu_bo_reset :in std_ulogic; + pc_xu_bo_shdata :in std_ulogic; + pc_xu_bo_select :in std_ulogic_vector(0 to 4); + xu_pc_bo_fail :out std_ulogic_vector(0 to 4); + xu_pc_bo_diagout :out std_ulogic_vector(0 to 4); + an_ac_coreid :in std_ulogic_vector(54 to 61); + spr_pvr_version_dc :in std_ulogic_vector(8 to 15); + spr_pvr_revision_dc :in std_ulogic_vector(12 to 15); + an_ac_atpg_en_dc :in std_ulogic; + an_ac_ext_interrupt :in std_ulogic_vector(0 to threads-1); + an_ac_crit_interrupt :in std_ulogic_vector(0 to threads-1); + an_ac_perf_interrupt :in std_ulogic_vector(0 to threads-1); + an_ac_reservation_vld :in std_ulogic_vector(0 to threads-1); + an_ac_grffence_en_dc :in std_ulogic; + an_ac_tb_update_pulse :in std_ulogic; + an_ac_tb_update_enable :in std_ulogic; + an_ac_sleep_en :in std_ulogic_vector(0 to threads-1); + an_ac_hang_pulse :in std_ulogic_vector(0 to threads-1); + an_ac_scan_dis_dc_b :in std_ulogic; + an_ac_lbist_en_dc :in std_ulogic; + an_ac_lbist_ary_wrt_thru_dc :in std_ulogic; + ac_tc_machine_check :out std_ulogic_vector(0 to threads-1); + pc_xu_abist_raddr_0 :in std_ulogic_vector(4 to 9); + pc_xu_abist_ena_dc :in std_ulogic; + pc_xu_abist_waddr_0 :in std_ulogic_vector(4 to 9); + pc_xu_abist_di_0 :in std_ulogic_vector(0 to 3); + pc_xu_abist_raw_dc_b :in std_ulogic; + pc_xu_ccflush_dc :in std_ulogic; + pc_xu_abist_g8t_wenb :in std_ulogic; + pc_xu_abist_g8t1p_renb_0 :in std_ulogic; + pc_xu_abist_g8t_bw_1 :in std_ulogic; + pc_xu_abist_g8t_bw_0 :in std_ulogic; + pc_xu_abist_wl32_comp_ena :in std_ulogic; + pc_xu_abist_g8t_dcomp :in std_ulogic_vector(0 to 3); + clkoff_dc_b :out std_ulogic; + d_mode_dc :out std_ulogic; + delay_lclkr_dc :out std_ulogic_vector(0 to 4); + mpw1_dc_b :out std_ulogic_vector(0 to 4); + mpw2_dc_b :out std_ulogic; + g6t_clkoff_dc_b :out std_ulogic; + g6t_d_mode_dc :out std_ulogic; + g6t_delay_lclkr_dc :out std_ulogic_vector(0 to 4); + g6t_mpw1_dc_b :out std_ulogic_vector(0 to 4); + g6t_mpw2_dc_b :out std_ulogic; + pc_xu_sg_3 :in std_ulogic_vector(0 to 4); + pc_xu_func_sl_thold_3 :in std_ulogic_vector(0 to 4); + pc_xu_func_slp_sl_thold_3 :in std_ulogic_vector(0 to 4); + pc_xu_func_nsl_thold_3 :in std_ulogic; + pc_xu_func_slp_nsl_thold_3 :in std_ulogic; + pc_xu_gptr_sl_thold_3 :in std_ulogic; + pc_xu_abst_sl_thold_3 :in std_ulogic; + pc_xu_abst_slp_sl_thold_3 :in std_ulogic; + pc_xu_regf_sl_thold_3 :in std_ulogic; + pc_xu_regf_slp_sl_thold_3 :in std_ulogic; + pc_xu_time_sl_thold_3 :in std_ulogic; + pc_xu_cfg_sl_thold_3 :in std_ulogic; + pc_xu_cfg_slp_sl_thold_3 :in std_ulogic; + pc_xu_ary_nsl_thold_3 :in std_ulogic; + pc_xu_ary_slp_nsl_thold_3 :in std_ulogic; + pc_xu_repr_sl_thold_3 :in std_ulogic; + pc_xu_fce_3 :in std_ulogic_vector(0 to 1); + an_ac_scan_diag_dc :in std_ulogic; + sg_2 :out std_ulogic_vector(0 to 3); + fce_2 :out std_ulogic_vector(0 to 1); + func_sl_thold_2 :out std_ulogic_vector(0 to 3); + func_slp_sl_thold_2 :out std_ulogic_vector(0 to 1); + func_slp_nsl_thold_2 :out std_ulogic; + func_nsl_thold_2 :out std_ulogic; + abst_sl_thold_2 :out std_ulogic; + time_sl_thold_2 :out std_ulogic; + gptr_sl_thold_2 :out std_ulogic; + ary_nsl_thold_2 :out std_ulogic; + repr_sl_thold_2 :out std_ulogic; + cfg_sl_thold_2 :out std_ulogic; + cfg_slp_sl_thold_2 :out std_ulogic; + regf_slp_sl_thold_2 :out std_ulogic; + gptr_scan_in :in std_ulogic; + gptr_scan_out :out std_ulogic; + time_scan_in :in std_ulogic; + time_scan_out :out std_ulogic; + ccfg_scan_in :in std_ulogic; + ccfg_scan_out :out std_ulogic; + regf_scan_in :in std_ulogic_vector(0 to 6); + regf_scan_out :out std_ulogic_vector(0 to 6); + abst_scan_in :in std_ulogic_vector(0 to 1); + abst_scan_out :out std_ulogic_vector(0 to 1); + repr_scan_in :in std_ulogic; + repr_scan_out :out std_ulogic; + func_scan_in :in std_ulogic_vector(35 to 58); + func_scan_out :out std_ulogic_vector(35 to 58); + bcfg_scan_in :in std_ulogic; + bcfg_scan_out :out std_ulogic; + dcfg_scan_in :in std_ulogic; + dcfg_scan_out :out std_ulogic; + + vcs :inout power_logic; + vdd :inout power_logic; + gnd :inout power_logic; + nclk :in clk_logic +); + +-- synopsys translate_off + +-- synopsys translate_on +end xuq_ctrl_spr; +architecture xuq_ctrl_spr of xuq_ctrl_spr is + +signal bolt_sl_thold_2_b : std_ulogic; +signal bo_enable_2_b : std_ulogic; +signal clkoff_dc_b_b : std_ulogic; +signal d_mode_dc_b : std_ulogic; +signal delay_lclkr_dc_b : std_ulogic_vector(0 to 4); +signal mpw1_dc_b_b : std_ulogic_vector(0 to 4); +signal mpw2_dc_b_b : std_ulogic; +signal sg_2_b : std_ulogic_vector(0 to 3); +signal fce_2_b : std_ulogic_vector(0 to 1); +signal func_sl_thold_2_b : std_ulogic_vector(0 to 3); +signal func_slp_sl_thold_2_b : std_ulogic_vector(0 to 1); +signal func_slp_nsl_thold_2_b : std_ulogic; +signal func_nsl_thold_2_b : std_ulogic; +signal abst_sl_thold_2_b : std_ulogic; +signal time_sl_thold_2_b : std_ulogic; +signal gptr_sl_thold_2_b : std_ulogic; +signal ary_nsl_thold_2_b : std_ulogic; +signal repr_sl_thold_2_b : std_ulogic; +signal cfg_sl_thold_2_b : std_ulogic; +signal cfg_slp_sl_thold_2_b : std_ulogic; + +signal dec_spr_ex4_val :std_ulogic_vector(0 to threads-1); +signal dec_spr_ex1_epid_instr :std_ulogic; +signal mux_spr_ex2_rt :std_ulogic_vector(64-(2**regmode) to 63); +signal fxu_spr_ex1_rs0 :std_ulogic_vector(52 to 63); +signal fxu_spr_ex1_rs1 :std_ulogic_vector(54 to 63); +signal spr_msr_cm_int :std_ulogic_vector(0 to threads-1); +signal spr_dec_spr_xucr0_ssdly :std_ulogic_vector(0 to 4); +signal spr_ccr2_en_attn :std_ulogic; +signal spr_ccr2_en_ditc_int :std_ulogic; +signal spr_ccr2_en_pc :std_ulogic; +signal spr_ccr2_en_icswx :std_ulogic; +signal spr_ccr2_en_dcr_int :std_ulogic; +signal spr_dec_rf1_epcr_dgtmi :std_ulogic_vector(0 to threads-1); +signal spr_byp_ex4_is_mfxer :std_ulogic_vector(0 to threads-1); +signal spr_byp_ex3_spr_rt :std_ulogic_vector(64-(2**regmode) to 63); +signal spr_byp_ex4_is_mtxer :std_ulogic_vector(0 to threads-1); +signal spr_ccr2_notlb_int :std_ulogic; +signal dec_spr_rf1_val :std_ulogic_vector(0 to threads-1); +signal fxu_spr_ex1_rs2 :std_ulogic_vector(42 to 55); +signal spr_perf_tx_events :std_ulogic_vector(0 to 8*threads-1); +signal spr_msr_gs_int :std_ulogic_vector(0 to threads-1); +signal spr_msr_ds_int :std_ulogic_vector(0 to threads-1); +signal spr_msr_pr_int :std_ulogic_vector(0 to threads-1); +signal spr_dbcr0_dac1 :std_ulogic_vector(0 to 2*threads-1); +signal spr_dbcr0_dac2 :std_ulogic_vector(0 to 2*threads-1); +signal spr_dbcr0_dac3 :std_ulogic_vector(0 to 2*threads-1); +signal spr_dbcr0_dac4 :std_ulogic_vector(0 to 2*threads-1); +signal spr_cpl_external_mchk :std_ulogic_vector(0 to threads-1); +signal spr_cpl_ext_interrupt :std_ulogic_vector(0 to threads-1); +signal spr_cpl_dec_interrupt :std_ulogic_vector(0 to threads-1); +signal spr_cpl_udec_interrupt :std_ulogic_vector(0 to threads-1); +signal spr_cpl_perf_interrupt :std_ulogic_vector(0 to threads-1); +signal spr_cpl_fit_interrupt :std_ulogic_vector(0 to threads-1); +signal spr_cpl_crit_interrupt :std_ulogic_vector(0 to threads-1); +signal spr_cpl_wdog_interrupt :std_ulogic_vector(0 to threads-1); +signal spr_cpl_dbell_interrupt :std_ulogic_vector(0 to threads-1); +signal spr_cpl_cdbell_interrupt :std_ulogic_vector(0 to threads-1); +signal spr_cpl_gdbell_interrupt :std_ulogic_vector(0 to threads-1); +signal spr_cpl_gcdbell_interrupt :std_ulogic_vector(0 to threads-1); +signal spr_cpl_gmcdbell_interrupt :std_ulogic_vector(0 to threads-1); +signal cpl_spr_ex5_dbell_taken :std_ulogic_vector(0 to threads-1); +signal cpl_spr_ex5_cdbell_taken :std_ulogic_vector(0 to threads-1); +signal cpl_spr_ex5_gdbell_taken :std_ulogic_vector(0 to threads-1); +signal cpl_spr_ex5_gcdbell_taken :std_ulogic_vector(0 to threads-1); +signal cpl_spr_ex5_gmcdbell_taken :std_ulogic_vector(0 to threads-1); +signal spr_bit_act :std_ulogic; +signal cpl_spr_ex5_act :std_ulogic_vector(0 to threads-1); +signal cpl_spr_ex5_int :std_ulogic_vector(0 to threads-1); +signal cpl_spr_ex5_gint :std_ulogic_vector(0 to threads-1); +signal cpl_spr_ex5_cint :std_ulogic_vector(0 to threads-1); +signal cpl_spr_ex5_mcint :std_ulogic_vector(0 to threads-1); +signal cpl_spr_ex5_nia :std_ulogic_vector(0 to eff_ifar*threads-1); +signal cpl_spr_ex5_esr :std_ulogic_vector(0 to 17*threads-1); +signal cpl_spr_ex5_mcsr :std_ulogic_vector(0 to 15*threads-1); +signal cpl_spr_ex5_dbsr :std_ulogic_vector(0 to 19*threads-1); +signal cpl_spr_ex5_dear_update :std_ulogic_vector(0 to threads-1); +signal cpl_spr_ex5_dear_update_saved :std_ulogic_vector(0 to threads-1); +signal cpl_spr_ex5_dear_save :std_ulogic_vector(0 to threads-1); +signal cpl_spr_ex5_dbsr_update :std_ulogic_vector(0 to threads-1); +signal cpl_spr_ex5_esr_update :std_ulogic_vector(0 to threads-1); +signal cpl_spr_ex5_srr0_dec :std_ulogic_vector(0 to threads-1); +signal cpl_spr_ex5_force_gsrr :std_ulogic_vector(0 to threads-1); +signal cpl_spr_ex5_dbsr_ide :std_ulogic_vector(0 to threads-1); +signal spr_cpl_dbsr_ide :std_ulogic_vector(0 to threads-1); +signal spr_cpl_ex3_ct_le :std_ulogic_vector(0 to threads-1); +signal spr_cpl_ex3_ct_be :std_ulogic_vector(0 to threads-1); +signal spr_cpl_ex3_spr_hypv :std_ulogic; +signal spr_cpl_ex3_spr_illeg :std_ulogic; +signal spr_cpl_ex3_spr_priv :std_ulogic; +signal cpl_spr_stop :std_ulogic_vector(0 to threads-1); +signal cpl_spr_ex5_instr_cpl :std_ulogic_vector(0 to threads-1); +signal cpl_spr_quiesce :std_ulogic_vector(0 to threads-1); +signal spr_cpl_quiesce :std_ulogic_vector(0 to threads-1); +signal spr_cpl_ex2_run_ctl_flush :std_ulogic_vector(0 to threads-1); +signal spr_cpl_fp_precise :std_ulogic_vector(0 to threads-1); +signal spr_cpl_iac1_en :std_ulogic_vector(0 to threads-1); +signal spr_cpl_iac2_en :std_ulogic_vector(0 to threads-1); +signal spr_cpl_iac3_en :std_ulogic_vector(0 to threads-1); +signal spr_cpl_iac4_en :std_ulogic_vector(0 to threads-1); +signal spr_dbcr1_iac12m :std_ulogic_vector(0 to threads-1); +signal spr_dbcr1_iac34m :std_ulogic_vector(0 to threads-1); +signal spr_epcr_duvd :std_ulogic_vector(0 to threads-1); +signal spr_xucr0_mddp :std_ulogic; +signal spr_xucr0_mdcp :std_ulogic; +signal spr_msr_de :std_ulogic_vector(0 to threads-1); +signal spr_msr_spv_int :std_ulogic_vector(0 to threads-1); +signal spr_msr_fp_int :std_ulogic_vector(0 to threads-1); +signal spr_msr_me :std_ulogic_vector(0 to threads-1); +signal spr_msr_ucle :std_ulogic_vector(0 to threads-1); +signal spr_msrp_uclep :std_ulogic_vector(0 to threads-1); +signal spr_ccr2_ucode_dis :std_ulogic; +signal spr_ccr2_ap_int :std_ulogic_vector(0 to 3); +signal cpl_spr_dbcr0_edm :std_ulogic_vector(0 to threads-1); +signal spr_dbcr0_idm :std_ulogic_vector(0 to threads-1); +signal spr_dbcr0_icmp :std_ulogic_vector(0 to threads-1); +signal spr_dbcr0_brt :std_ulogic_vector(0 to threads-1); +signal spr_dbcr0_trap :std_ulogic_vector(0 to threads-1); +signal spr_dbcr0_ret :std_ulogic_vector(0 to threads-1); +signal spr_dbcr0_irpt :std_ulogic_vector(0 to threads-1); +signal spr_epcr_dsigs :std_ulogic_vector(0 to threads-1); +signal spr_epcr_isigs :std_ulogic_vector(0 to threads-1); +signal spr_epcr_extgs :std_ulogic_vector(0 to threads-1); +signal spr_epcr_dtlbgs :std_ulogic_vector(0 to threads-1); +signal spr_epcr_itlbgs :std_ulogic_vector(0 to threads-1); +signal spr_cpl_ex3_sprg_ce :std_ulogic; +signal spr_cpl_ex3_sprg_ue :std_ulogic; +signal xu_lsu_slowspr_val :std_ulogic; +signal xu_lsu_slowspr_rw :std_ulogic; +signal xu_lsu_slowspr_etid :std_ulogic_vector(0 to 1); +signal xu_lsu_slowspr_addr :std_ulogic_vector(0 to 9); +signal xu_lsu_slowspr_data :std_ulogic_vector(64-(2**REGMODE) to 63); +signal xu_lsu_slowspr_done :std_ulogic; +signal lsu_xu_dbell_val :std_ulogic; +signal lsu_xu_dbell_type :std_ulogic_vector(0 to 4); +signal lsu_xu_dbell_brdcast :std_ulogic; +signal lsu_xu_dbell_lpid_match :std_ulogic; +signal lsu_xu_dbell_pirtag :std_ulogic_vector(50 to 63); +signal lsu_xu_quiesce :std_ulogic_vector(0 to threads-1); +signal xu_lsu_mtspr_trace_en :std_ulogic_vector(0 to threads-1); +signal lsu_xu_spr_xucr0_cslc_xuop :std_ulogic; +signal lsu_xu_spr_xucr0_cslc_binv :std_ulogic; +signal lsu_xu_spr_xucr0_clo :std_ulogic; +signal lsu_xu_spr_xucr0_cul :std_ulogic; +signal lsu_xu_spr_epsc_epr :std_ulogic_vector(0 to 3); +signal lsu_xu_spr_epsc_egs :std_ulogic_vector(0 to 3); +signal xu_lsu_spr_xucr0_aflsta :std_ulogic; +signal xu_lsu_spr_xucr0_flsta :std_ulogic; +signal xu_lsu_spr_xucr0_l2siw :std_ulogic; +signal xu_lsu_spr_xucr0_dcdis_int :std_ulogic; +signal xu_lsu_spr_xucr0_wlk :std_ulogic; +signal xu_lsu_spr_xucr0_clfc :std_ulogic; +signal xu_lsu_spr_xucr0_flh2l2 :std_ulogic; +signal xu_lsu_spr_xucr0_cred :std_ulogic; +signal xu_lsu_spr_xucr0_rel_int :std_ulogic; +signal xu_lsu_spr_xucr0_mbar_ack :std_ulogic; +signal xu_lsu_spr_xucr0_tlbsync :std_ulogic; +signal xu_lsu_spr_xucr0_cls :std_ulogic; +signal xu_lsu_spr_ccr2_dfrat :std_ulogic; +signal xu_lsu_spr_ccr2_dfratsc :std_ulogic_vector(0 to 8); +signal ctrl_bcfg_scan_in :std_ulogic; +signal ctrl_ccfg_scan_in :std_ulogic; +signal ctrl_dcfg_scan_in :std_ulogic; +signal ctrl_time_scan_in :std_ulogic; +signal ctrl_repr_scan_in :std_ulogic; +signal ctrl_gptr_scan_in :std_ulogic; +signal ctrl_bcfg_scan_out :std_ulogic; +signal ctrl_ccfg_scan_out :std_ulogic; +signal ctrl_dcfg_scan_out :std_ulogic; +signal ctrl_time_scan_out :std_ulogic; +signal ctrl_repr_scan_out :std_ulogic; +signal ctrl_gptr_scan_out :std_ulogic; +signal spr_bcfg_scan_in :std_ulogic; +signal spr_ccfg_scan_in :std_ulogic; +signal spr_dcfg_scan_in :std_ulogic; +signal spr_time_scan_in :std_ulogic; +signal spr_repr_scan_in :std_ulogic; +signal spr_gptr_scan_in :std_ulogic; +signal spr_bcfg_scan_out :std_ulogic; +signal spr_ccfg_scan_out :std_ulogic; +signal spr_dcfg_scan_out :std_ulogic; +signal spr_time_scan_out :std_ulogic; +signal spr_repr_scan_out :std_ulogic; +signal spr_gptr_scan_out :std_ulogic; +signal xu_s_rf1_flush_int :std_ulogic_vector(0 to threads-1); +signal xu_s_ex1_flush_int :std_ulogic_vector(0 to threads-1); +signal xu_s_ex2_flush_int :std_ulogic_vector(0 to threads-1); +signal xu_s_ex3_flush_int :std_ulogic_vector(0 to threads-1); +signal xu_s_ex4_flush_int :std_ulogic_vector(0 to threads-1); +signal xu_s_ex5_flush_int :std_ulogic_vector(0 to threads-1); +signal spr_ccr0_we :std_ulogic_vector(0 to threads-1); +signal spr_xucr0_clkg_ctl :std_ulogic_vector(0 to 3); +signal spr_debug_data_in :std_ulogic_vector(0 to 87); +signal spr_debug_data_out :std_ulogic_vector(0 to 87); +signal spr_trigger_data_in :std_ulogic_vector(0 to 11); +signal spr_trigger_data_out :std_ulogic_vector(0 to 11); +signal ctrl_debug_data_in :std_ulogic_vector(0 to 87); +signal ctrl_debug_data_out :std_ulogic_vector(0 to 87); +signal ctrl_trigger_data_in :std_ulogic_vector(0 to 11); +signal ctrl_trigger_data_out :std_ulogic_vector(0 to 11); +signal lsu_xu_cmd_debug :std_ulogic_vector(0 to 175); + +begin + +-- DEBUG BUS CHAINS +ctrl_trigger_data_in <= trigger_data_in; +ctrl_debug_data_in <= debug_data_in; +spr_debug_data_in <= ctrl_debug_data_out; +spr_trigger_data_in <= ctrl_trigger_data_out; +debug_data_out <= spr_debug_data_out; +trigger_data_out <= spr_trigger_data_out; + +-- SCAN CHAINS +ctrl_bcfg_scan_in <= bcfg_scan_in; +ctrl_ccfg_scan_in <= ccfg_scan_in; +ctrl_dcfg_scan_in <= dcfg_scan_in; +ctrl_time_scan_in <= time_scan_in; +ctrl_repr_scan_in <= repr_scan_in; +ctrl_gptr_scan_in <= gptr_scan_in; + +spr_bcfg_scan_in <= ctrl_bcfg_scan_out; +spr_ccfg_scan_in <= ctrl_ccfg_scan_out; +spr_dcfg_scan_in <= ctrl_dcfg_scan_out; +spr_time_scan_in <= ctrl_time_scan_out; +spr_repr_scan_in <= ctrl_repr_scan_out; +spr_gptr_scan_in <= ctrl_gptr_scan_out; + +bcfg_scan_out <= spr_bcfg_scan_out; +ccfg_scan_out <= spr_ccfg_scan_out; +dcfg_scan_out <= spr_dcfg_scan_out; +time_scan_out <= spr_time_scan_out; +repr_scan_out <= spr_repr_scan_out; +gptr_scan_out <= spr_gptr_scan_out; + + +xu_lsu_slowspr_done <= '0'; + +xu_s_rf1_flush <= xu_s_rf1_flush_int; +xu_s_ex1_flush <= xu_s_ex1_flush_int; +xu_s_ex2_flush <= xu_s_ex2_flush_int; +xu_s_ex3_flush <= xu_s_ex3_flush_int; +xu_s_ex4_flush <= xu_s_ex4_flush_int; +xu_s_ex5_flush <= xu_s_ex5_flush_int; + +xu_mm_spr_epcr_dgtmi <= spr_dec_rf1_epcr_dgtmi; + +xu_pc_spr_ccr0_we <= spr_ccr0_we; + +bolt_sl_thold_2 <= bolt_sl_thold_2_b; +bo_enable_2 <= bo_enable_2_b; +clkoff_dc_b <= clkoff_dc_b_b; +d_mode_dc <= d_mode_dc_b; +delay_lclkr_dc <= delay_lclkr_dc_b; +mpw1_dc_b <= mpw1_dc_b_b; +mpw2_dc_b <= mpw2_dc_b_b; +sg_2 <= sg_2_b; +fce_2 <= fce_2_b; +func_sl_thold_2 <= func_sl_thold_2_b; +func_slp_sl_thold_2 <= func_slp_sl_thold_2_b; +func_slp_nsl_thold_2 <= func_slp_nsl_thold_2_b; +func_nsl_thold_2 <= func_nsl_thold_2_b; +abst_sl_thold_2 <= abst_sl_thold_2_b; +time_sl_thold_2 <= time_sl_thold_2_b; +gptr_sl_thold_2 <= gptr_sl_thold_2_b; +ary_nsl_thold_2 <= ary_nsl_thold_2_b; +repr_sl_thold_2 <= repr_sl_thold_2_b; +cfg_sl_thold_2 <= cfg_sl_thold_2_b; +cfg_slp_sl_thold_2 <= cfg_slp_sl_thold_2_b; + +-- ########################################################################################## +-- CPL/FXUB/CMD +-- ########################################################################################## + +ctrl : entity work.xuq_ctrl(xuq_ctrl) +generic map( + expand_type => expand_type, + threads => threads, + eff_ifar => eff_ifar, + uc_ifar => uc_ifar, + regsize => regsize, + hvmode => hvmode, + regmode => regmode, + dc_size => dc_size, + cl_size => cl_size, + real_data_add => real_data_add, + fxu_synth => fxu_synth, + a2mode => a2mode, + lmq_entries => lmq_entries, + l_endian_m => l_endian_m, + load_credits => load_credits, + store_credits => store_credits, + st_data_32B_mode => st_data_32B_mode, + bcfg_epn_0to15 => bcfg_epn_0to15, + bcfg_epn_16to31 => bcfg_epn_16to31, + bcfg_epn_32to47 => bcfg_epn_32to47, + bcfg_epn_48to51 => bcfg_epn_48to51, + bcfg_rpn_22to31 => bcfg_rpn_22to31, + bcfg_rpn_32to47 => bcfg_rpn_32to47, + bcfg_rpn_48to51 => bcfg_rpn_48to51) +port map( + + --------------------------------------------------------------------- + -- Pervasive + --------------------------------------------------------------------- + an_ac_grffence_en_dc => an_ac_grffence_en_dc, + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b, + an_ac_lbist_en_dc => an_ac_lbist_en_dc, + pc_xu_abist_raddr_0 => pc_xu_abist_raddr_0(5 to 9), + pc_xu_abist_ena_dc => pc_xu_abist_ena_dc, + pc_xu_abist_waddr_0 => pc_xu_abist_waddr_0(5 to 9), + pc_xu_abist_di_0 => pc_xu_abist_di_0, + pc_xu_abist_raw_dc_b => pc_xu_abist_raw_dc_b, + pc_xu_ccflush_dc => pc_xu_ccflush_dc, + clkoff_dc_b => clkoff_dc_b_b, + d_mode_dc => d_mode_dc_b, + delay_lclkr_dc => delay_lclkr_dc_b, + mpw1_dc_b => mpw1_dc_b_b, + mpw2_dc_b => mpw2_dc_b_b, + g6t_clkoff_dc_b => g6t_clkoff_dc_b, + g6t_d_mode_dc => g6t_d_mode_dc, + g6t_delay_lclkr_dc => g6t_delay_lclkr_dc, + g6t_mpw1_dc_b => g6t_mpw1_dc_b, + g6t_mpw2_dc_b => g6t_mpw2_dc_b, + pc_xu_sg_3 => pc_xu_sg_3, + pc_xu_func_sl_thold_3 => pc_xu_func_sl_thold_3, + pc_xu_func_slp_sl_thold_3 => pc_xu_func_slp_sl_thold_3, + pc_xu_func_nsl_thold_3 => pc_xu_func_nsl_thold_3, + pc_xu_func_slp_nsl_thold_3 => pc_xu_func_slp_nsl_thold_3, + pc_xu_gptr_sl_thold_3 => pc_xu_gptr_sl_thold_3, + pc_xu_abst_sl_thold_3 => pc_xu_abst_sl_thold_3, + pc_xu_abst_slp_sl_thold_3 => pc_xu_abst_slp_sl_thold_3, + pc_xu_regf_sl_thold_3 => pc_xu_regf_sl_thold_3, + pc_xu_regf_slp_sl_thold_3 => pc_xu_regf_slp_sl_thold_3, + pc_xu_time_sl_thold_3 => pc_xu_time_sl_thold_3, + pc_xu_cfg_sl_thold_3 => pc_xu_cfg_sl_thold_3, + pc_xu_cfg_slp_sl_thold_3 => pc_xu_cfg_slp_sl_thold_3, + pc_xu_ary_nsl_thold_3 => pc_xu_ary_nsl_thold_3, + pc_xu_ary_slp_nsl_thold_3 => pc_xu_ary_slp_nsl_thold_3, + pc_xu_repr_sl_thold_3 => pc_xu_repr_sl_thold_3, + pc_xu_fce_3 => pc_xu_fce_3, + an_ac_scan_diag_dc => an_ac_scan_diag_dc, + sg_2 => sg_2_b, + fce_2 => fce_2_b, + func_sl_thold_2 => func_sl_thold_2_b, + func_slp_sl_thold_2 => func_slp_sl_thold_2_b, + func_slp_nsl_thold_2 => func_slp_nsl_thold_2_b, + func_nsl_thold_2 => func_nsl_thold_2_b, + abst_sl_thold_2 => abst_sl_thold_2_b, + time_sl_thold_2 => time_sl_thold_2_b, + gptr_sl_thold_2 => gptr_sl_thold_2_b, + ary_nsl_thold_2 => ary_nsl_thold_2_b, + repr_sl_thold_2 => repr_sl_thold_2_b, + bolt_sl_thold_2 => bolt_sl_thold_2_b, + bo_enable_2 => bo_enable_2_b, + cfg_sl_thold_2 => cfg_sl_thold_2_b, + cfg_slp_sl_thold_2 => cfg_slp_sl_thold_2_b, + regf_slp_sl_thold_2 => regf_slp_sl_thold_2, + pc_xu_bolt_sl_thold_3 => pc_xu_bolt_sl_thold_3, + pc_xu_bo_enable_3 => pc_xu_bo_enable_3, + + --------------------------------------------------------------------- + -- Interface with FXU A + --------------------------------------------------------------------- + fxa_fxb_rf0_val => fxa_fxb_rf0_val, + fxa_fxb_rf0_issued => fxa_fxb_rf0_issued, + fxa_fxb_rf0_ucode_val => fxa_fxb_rf0_ucode_val, + fxa_fxb_rf0_act => fxa_fxb_rf0_act, + fxa_fxb_ex1_hold_ctr_flush => fxa_fxb_ex1_hold_ctr_flush, + fxa_fxb_rf0_instr => fxa_fxb_rf0_instr, + fxa_fxb_rf0_tid => fxa_fxb_rf0_tid, + fxa_fxb_rf0_ta_vld => fxa_fxb_rf0_ta_vld, + fxa_fxb_rf0_ta => fxa_fxb_rf0_ta, + fxa_fxb_rf0_error => fxa_fxb_rf0_error, + fxa_fxb_rf0_match => fxa_fxb_rf0_match, + fxa_fxb_rf0_is_ucode => fxa_fxb_rf0_is_ucode, + fxa_fxb_rf0_gshare => fxa_fxb_rf0_gshare, + fxa_fxb_rf0_ifar => fxa_fxb_rf0_ifar, + fxa_fxb_rf0_s1_vld => fxa_fxb_rf0_s1_vld, + fxa_fxb_rf0_s1 => fxa_fxb_rf0_s1, + fxa_fxb_rf0_s2_vld => fxa_fxb_rf0_s2_vld, + fxa_fxb_rf0_s2 => fxa_fxb_rf0_s2, + fxa_fxb_rf0_s3_vld => fxa_fxb_rf0_s3_vld, + fxa_fxb_rf0_s3 => fxa_fxb_rf0_s3, + fxa_fxb_rf0_axu_instr_type => fxa_fxb_rf0_axu_instr_type, + fxa_fxb_rf0_axu_ld_or_st => fxa_fxb_rf0_axu_ld_or_st, + fxa_fxb_rf0_axu_store => fxa_fxb_rf0_axu_store, + fxa_fxb_rf0_axu_ldst_forcealign => fxa_fxb_rf0_axu_ldst_forcealign, + fxa_fxb_rf0_axu_ldst_forceexcept => fxa_fxb_rf0_axu_ldst_forceexcept, + fxa_fxb_rf0_axu_ldst_indexed => fxa_fxb_rf0_axu_ldst_indexed, + fxa_fxb_rf0_axu_ldst_tag => fxa_fxb_rf0_axu_ldst_tag, + fxa_fxb_rf0_axu_mftgpr => fxa_fxb_rf0_axu_mftgpr, + fxa_fxb_rf0_axu_mffgpr => fxa_fxb_rf0_axu_mffgpr, + fxa_fxb_rf0_axu_movedp => fxa_fxb_rf0_axu_movedp, + fxa_fxb_rf0_axu_ldst_size => fxa_fxb_rf0_axu_ldst_size, + fxa_fxb_rf0_axu_ldst_update => fxa_fxb_rf0_axu_ldst_update, + fxa_fxb_rf0_pred_update => fxa_fxb_rf0_pred_update, + fxa_fxb_rf0_pred_taken_cnt => fxa_fxb_rf0_pred_taken_cnt, + fxa_fxb_rf0_mc_dep_chk_val => fxa_fxb_rf0_mc_dep_chk_val, + fxa_fxb_rf1_mul_val => fxa_fxb_rf1_mul_val, + fxa_fxb_rf1_div_val => fxa_fxb_rf1_div_val, + fxa_fxb_rf1_div_ctr => fxa_fxb_rf1_div_ctr, + fxa_fxb_rf0_xu_epid_instr => fxa_fxb_rf0_xu_epid_instr, + fxa_fxb_rf0_axu_is_extload => fxa_fxb_rf0_axu_is_extload, + fxa_fxb_rf0_axu_is_extstore => fxa_fxb_rf0_axu_is_extstore, + fxa_fxb_rf0_is_mfocrf => fxa_fxb_rf0_is_mfocrf, + fxa_fxb_rf0_3src_instr => fxa_fxb_rf0_3src_instr, + fxa_fxb_rf0_gpr0_zero => fxa_fxb_rf0_gpr0_zero, + fxa_fxb_rf0_use_imm => fxa_fxb_rf0_use_imm, + fxa_fxb_rf1_muldiv_coll => fxa_fxb_rf1_muldiv_coll, + fxa_cpl_ex2_div_coll => fxa_cpl_ex2_div_coll, + fxb_fxa_ex7_we0 => fxb_fxa_ex7_we0, + fxb_fxa_ex7_wa0 => fxb_fxa_ex7_wa0, + fxb_fxa_ex7_wd0 => fxb_fxa_ex7_wd0, + fxa_fxb_rf1_do0 => fxa_fxb_rf1_do0, + fxa_fxb_rf1_do1 => fxa_fxb_rf1_do1, + fxa_fxb_rf1_do2 => fxa_fxb_rf1_do2, + + --------------------------------------------------------------------- + -- BOXES Req Interface + --------------------------------------------------------------------- + xu_bx_ex1_mtdp_val => xu_bx_ex1_mtdp_val, + xu_bx_ex1_mfdp_val => xu_bx_ex1_mfdp_val, + xu_bx_ex1_ipc_thrd => xu_bx_ex1_ipc_thrd, + xu_bx_ex2_ipc_ba => xu_bx_ex2_ipc_ba, + xu_bx_ex2_ipc_sz => xu_bx_ex2_ipc_sz, + + --------------------------------------------------------------------- + -- D-ERAT Req Interface + --------------------------------------------------------------------- + xu_mm_derat_epn => xu_mm_derat_epn, + + --------------------------------------------------------------------- + -- TLBSX./TLBSRX. + --------------------------------------------------------------------- + xu_mm_rf1_is_tlbsxr => xu_mm_rf1_is_tlbsxr, + mm_xu_cr0_eq_valid => mm_xu_cr0_eq_valid, + mm_xu_cr0_eq => mm_xu_cr0_eq, + + --------------------------------------------------------------------- + -- FU CR Write + --------------------------------------------------------------------- + fu_xu_ex4_cr_val => fu_xu_ex4_cr_val, + fu_xu_ex4_cr_noflush => fu_xu_ex4_cr_noflush, + fu_xu_ex4_cr0 => fu_xu_ex4_cr0, + fu_xu_ex4_cr0_bf => fu_xu_ex4_cr0_bf, + fu_xu_ex4_cr1 => fu_xu_ex4_cr1, + fu_xu_ex4_cr1_bf => fu_xu_ex4_cr1_bf, + fu_xu_ex4_cr2 => fu_xu_ex4_cr2, + fu_xu_ex4_cr2_bf => fu_xu_ex4_cr2_bf, + fu_xu_ex4_cr3 => fu_xu_ex4_cr3, + fu_xu_ex4_cr3_bf => fu_xu_ex4_cr3_bf, + + --------------------------------------------------------------------- + -- RAM + --------------------------------------------------------------------- + pc_xu_ram_mode => pc_xu_ram_mode, + pc_xu_ram_thread => pc_xu_ram_thread, + pc_xu_ram_execute => pc_xu_ram_execute, + pc_xu_ram_flush_thread => pc_xu_ram_flush_thread, + xu_iu_ram_issue => xu_iu_ram_issue, + xu_pc_ram_interrupt => xu_pc_ram_interrupt, + xu_pc_ram_done => xu_pc_ram_done, + xu_pc_ram_data => xu_pc_ram_data, + + --------------------------------------------------------------------- + -- Interface with IU + --------------------------------------------------------------------- + xu_iu_ex5_val => xu_iu_ex5_val, + xu_iu_ex5_tid => xu_iu_ex5_tid, + xu_iu_ex5_br_update => xu_iu_ex5_br_update, + xu_iu_ex5_br_hist => xu_iu_ex5_br_hist, + xu_iu_ex5_bclr => xu_iu_ex5_bclr, + xu_iu_ex5_lk => xu_iu_ex5_lk, + xu_iu_ex5_bh => xu_iu_ex5_bh, + xu_iu_ex6_pri => xu_iu_ex6_pri, + xu_iu_ex6_pri_val => xu_iu_ex6_pri_val, + xu_iu_spr_xer => xu_iu_spr_xer, + xu_iu_slowspr_done => xu_iu_slowspr_done, + xu_iu_need_hole => xu_iu_need_hole, + fxb_fxa_ex6_clear_barrier => fxb_fxa_ex6_clear_barrier, + xu_iu_ex5_gshare => xu_iu_ex5_gshare, + xu_iu_ex5_getNIA => xu_iu_ex5_getNIA, + + --------------------------------------------------------------------- + -- L2 STCX complete + --------------------------------------------------------------------- + an_ac_stcx_complete => an_ac_stcx_complete, + an_ac_stcx_pass => an_ac_stcx_pass, + xu_iu_stcx_complete => xu_iu_stcx_complete, + xu_iu_reld_core_tag_clone => xu_iu_reld_core_tag_clone, + xu_iu_reld_data_coming_clone => xu_iu_reld_data_coming_clone, + xu_iu_reld_data_vld_clone => xu_iu_reld_data_vld_clone, + xu_iu_reld_ditc_clone => xu_iu_reld_ditc_clone, + + --------------------------------------------------------------------- + -- Slow SPR Bus + --------------------------------------------------------------------- + slowspr_val_in => slowspr_val_in, + slowspr_rw_in => slowspr_rw_in, + slowspr_etid_in => slowspr_etid_in, + slowspr_addr_in => slowspr_addr_in, + slowspr_data_in => slowspr_data_in, + slowspr_done_in => slowspr_done_in, + + --------------------------------------------------------------------- + -- DCR Bus + --------------------------------------------------------------------- + an_ac_dcr_act => an_ac_dcr_act, + an_ac_dcr_val => an_ac_dcr_val, + an_ac_dcr_read => an_ac_dcr_read, + an_ac_dcr_etid => an_ac_dcr_etid, + an_ac_dcr_data => an_ac_dcr_data, + an_ac_dcr_done => an_ac_dcr_done, + + --------------------------------------------------------------------- + -- MT/MFDCR CR + --------------------------------------------------------------------- + lsu_xu_ex4_mtdp_cr_status => lsu_xu_ex4_mtdp_cr_status, + lsu_xu_ex4_mfdp_cr_status => lsu_xu_ex4_mfdp_cr_status, + dec_cpl_ex3_mc_dep_chk_val => dec_cpl_ex3_mc_dep_chk_val, + + --------------------------------------------------------------------- + -- Interface with SPR + --------------------------------------------------------------------- + dec_spr_ex4_val => dec_spr_ex4_val, + dec_spr_ex1_epid_instr => dec_spr_ex1_epid_instr, + mux_spr_ex2_rt => mux_spr_ex2_rt, + fxu_spr_ex1_rs0 => fxu_spr_ex1_rs0, + fxu_spr_ex1_rs1 => fxu_spr_ex1_rs1, + spr_msr_cm => spr_msr_cm_int, + spr_dec_spr_xucr0_ssdly => spr_dec_spr_xucr0_ssdly, + spr_ccr2_en_attn => spr_ccr2_en_attn, + spr_ccr2_en_ditc => spr_ccr2_en_ditc_int, + spr_ccr2_en_pc => spr_ccr2_en_pc, + spr_ccr2_en_icswx => spr_ccr2_en_icswx, + spr_ccr2_en_dcr => spr_ccr2_en_dcr_int, + spr_dec_rf1_epcr_dgtmi => spr_dec_rf1_epcr_dgtmi, + spr_byp_ex4_is_mfxer => spr_byp_ex4_is_mfxer, + spr_byp_ex3_spr_rt => spr_byp_ex3_spr_rt, + spr_byp_ex4_is_mtxer => spr_byp_ex4_is_mtxer, + spr_ccr2_notlb => spr_ccr2_notlb_int, + dec_spr_rf1_val => dec_spr_rf1_val, + fxu_spr_ex1_rs2 => fxu_spr_ex1_rs2, + + --------------------------------------------------------------------- + -- Perf Events + --------------------------------------------------------------------- + fxa_perf_muldiv_in_use => fxa_perf_muldiv_in_use, + spr_perf_tx_events => spr_perf_tx_events, + xu_pc_event_data => xu_pc_event_data, + + --------------------------------------------------------------------- + -- PC Control Interface + --------------------------------------------------------------------- + pc_xu_event_count_mode => pc_xu_event_count_mode, + pc_xu_event_mux_ctrls => pc_xu_event_mux_ctrls, + + --------------------------------------------------------------------- + -- Debug Ramp & Controls + --------------------------------------------------------------------- + fxu_debug_mux_ctrls => fxu_debug_mux_ctrls, + cpl_debug_mux_ctrls => cpl_debug_mux_ctrls, + lsu_debug_mux_ctrls => lsu_debug_mux_ctrls, + ctrl_trigger_data_in => ctrl_trigger_data_in, + ctrl_trigger_data_out => ctrl_trigger_data_out, + ctrl_debug_data_in => ctrl_debug_data_in, + ctrl_debug_data_out => ctrl_debug_data_out, + lsu_xu_data_debug0 => lsu_xu_data_debug0, + lsu_xu_data_debug1 => lsu_xu_data_debug1, + lsu_xu_data_debug2 => lsu_xu_data_debug2, + fxa_cpl_debug => fxa_cpl_debug, + + --------------------------------------------------------------------- + -- SPR Bits + --------------------------------------------------------------------- + spr_msr_gs => spr_msr_gs_int, + spr_msr_ds => spr_msr_ds_int, + spr_msr_pr => spr_msr_pr_int, + spr_dbcr0_dac1 => spr_dbcr0_dac1, + spr_dbcr0_dac2 => spr_dbcr0_dac2, + spr_dbcr0_dac3 => spr_dbcr0_dac3, + spr_dbcr0_dac4 => spr_dbcr0_dac4, + + -- CHIP IO + ac_tc_debug_trigger => ac_tc_debug_trigger, + + -- Valids + dec_cpl_rf0_act => dec_cpl_rf0_act, + dec_cpl_rf0_tid => dec_cpl_rf0_tid, + + -- FU Inputs + fu_xu_rf1_act => fu_xu_rf1_act, + fu_xu_ex1_ifar => fu_xu_ex1_ifar, + fu_xu_ex2_ifar_val => fu_xu_ex2_ifar_val, + fu_xu_ex2_ifar_issued => fu_xu_ex2_ifar_issued, + fu_xu_ex2_instr_type => fu_xu_ex2_instr_type, + fu_xu_ex2_instr_match => fu_xu_ex2_instr_match, + fu_xu_ex2_is_ucode => fu_xu_ex2_is_ucode, + + -- PC Inputs + pc_xu_stop => pc_xu_stop, + pc_xu_step => pc_xu_step, + pc_xu_dbg_action => pc_xu_dbg_action, + pc_xu_force_ude => pc_xu_force_ude, + xu_pc_step_done => xu_pc_step_done, + pc_xu_init_reset => pc_xu_init_reset, + + -- Async Interrupt Req Interface + spr_cpl_external_mchk => spr_cpl_external_mchk, + spr_cpl_ext_interrupt => spr_cpl_ext_interrupt, + spr_cpl_udec_interrupt => spr_cpl_udec_interrupt, + spr_cpl_perf_interrupt => spr_cpl_perf_interrupt, + spr_cpl_dec_interrupt => spr_cpl_dec_interrupt, + spr_cpl_fit_interrupt => spr_cpl_fit_interrupt, + spr_cpl_crit_interrupt => spr_cpl_crit_interrupt, + spr_cpl_wdog_interrupt => spr_cpl_wdog_interrupt, + spr_cpl_dbell_interrupt => spr_cpl_dbell_interrupt, + spr_cpl_cdbell_interrupt => spr_cpl_cdbell_interrupt, + spr_cpl_gdbell_interrupt => spr_cpl_gdbell_interrupt, + spr_cpl_gcdbell_interrupt => spr_cpl_gcdbell_interrupt, + spr_cpl_gmcdbell_interrupt => spr_cpl_gmcdbell_interrupt, + cpl_spr_ex5_dbell_taken => cpl_spr_ex5_dbell_taken, + cpl_spr_ex5_cdbell_taken => cpl_spr_ex5_cdbell_taken, + cpl_spr_ex5_gdbell_taken => cpl_spr_ex5_gdbell_taken, + cpl_spr_ex5_gcdbell_taken => cpl_spr_ex5_gcdbell_taken, + cpl_spr_ex5_gmcdbell_taken => cpl_spr_ex5_gmcdbell_taken, + + -- Interrupt Interface + cpl_spr_ex5_act => cpl_spr_ex5_act, + cpl_spr_ex5_int => cpl_spr_ex5_int, + cpl_spr_ex5_gint => cpl_spr_ex5_gint, + cpl_spr_ex5_cint => cpl_spr_ex5_cint, + cpl_spr_ex5_mcint => cpl_spr_ex5_mcint, + cpl_spr_ex5_nia => cpl_spr_ex5_nia, + cpl_spr_ex5_esr => cpl_spr_ex5_esr, + cpl_spr_ex5_mcsr => cpl_spr_ex5_mcsr, + cpl_spr_ex5_dbsr => cpl_spr_ex5_dbsr, + cpl_spr_ex5_dear_save => cpl_spr_ex5_dear_save, + cpl_spr_ex5_dear_update_saved => cpl_spr_ex5_dear_update_saved, + cpl_spr_ex5_dear_update => cpl_spr_ex5_dear_update, + cpl_spr_ex5_dbsr_update => cpl_spr_ex5_dbsr_update, + cpl_spr_ex5_esr_update => cpl_spr_ex5_esr_update, + cpl_spr_ex5_srr0_dec => cpl_spr_ex5_srr0_dec, + cpl_spr_ex5_force_gsrr => cpl_spr_ex5_force_gsrr, + cpl_spr_ex5_dbsr_ide => cpl_spr_ex5_dbsr_ide, + spr_cpl_dbsr_ide => spr_cpl_dbsr_ide, + + -- Machine Check Interrupts + mm_xu_local_snoop_reject => mm_xu_local_snoop_reject, + mm_xu_lru_par_err => mm_xu_lru_par_err, + mm_xu_tlb_par_err => mm_xu_tlb_par_err, + mm_xu_tlb_multihit_err => mm_xu_tlb_multihit_err, + + -- PC Errors + xu_pc_err_attention_instr => xu_pc_err_attention_instr, + xu_pc_err_nia_miscmpr => xu_pc_err_nia_miscmpr, + xu_pc_err_debug_event => xu_pc_err_debug_event, + + spr_cpl_ex3_ct_le => spr_cpl_ex3_ct_le, + spr_cpl_ex3_ct_be => spr_cpl_ex3_ct_be, + + -- Program + spr_cpl_ex3_spr_illeg => spr_cpl_ex3_spr_illeg, + spr_cpl_ex3_spr_priv => spr_cpl_ex3_spr_priv, + + -- Hypv Privledge + spr_cpl_ex3_spr_hypv => spr_cpl_ex3_spr_hypv, + + -- Run State + cpl_spr_stop => cpl_spr_stop, + cpl_spr_ex5_instr_cpl => cpl_spr_ex5_instr_cpl, + spr_cpl_quiesce => spr_cpl_quiesce, + cpl_spr_quiesce => cpl_spr_quiesce, + spr_cpl_ex2_run_ctl_flush => spr_cpl_ex2_run_ctl_flush, + xu_pc_stop_dbg_event => xu_pc_stop_dbg_event, + + -- MMU Flushes + mm_xu_illeg_instr => mm_xu_illeg_instr, + mm_xu_tlb_miss => mm_xu_tlb_miss, + mm_xu_pt_fault => mm_xu_pt_fault, + mm_xu_tlb_inelig => mm_xu_tlb_inelig, + mm_xu_lrat_miss => mm_xu_lrat_miss, + mm_xu_hv_priv => mm_xu_hv_priv, + mm_xu_esr_pt => mm_xu_esr_pt, + mm_xu_esr_data => mm_xu_esr_data, + mm_xu_esr_epid => mm_xu_esr_epid, + mm_xu_esr_st => mm_xu_esr_st, + mm_xu_hold_req => mm_xu_hold_req, + mm_xu_hold_done => mm_xu_hold_done, + xu_mm_hold_ack => xu_mm_hold_ack, + mm_xu_eratmiss_done => mm_xu_eratmiss_done, + mm_xu_ex3_flush_req => mm_xu_ex3_flush_req, + + -- AXU Flushes + fu_xu_ex3_ap_int_req => fu_xu_ex3_ap_int_req, + fu_xu_ex3_trap => fu_xu_ex3_trap, + fu_xu_ex3_n_flush => fu_xu_ex3_n_flush, + fu_xu_ex3_np1_flush => fu_xu_ex3_np1_flush, + fu_xu_ex3_flush2ucode => fu_xu_ex3_flush2ucode, + fu_xu_ex2_async_block => fu_xu_ex2_async_block, + + -- IU Flushes + xu_iu_ex5_br_taken => xu_iu_ex5_br_taken, + xu_iu_ex5_ifar => xu_iu_ex5_ifar, + xu_iu_flush => xu_iu_flush, + xu_iu_iu0_flush_ifar => xu_iu_iu0_flush_ifar, + xu_iu_uc_flush_ifar => xu_iu_uc_flush_ifar, + xu_iu_flush_2ucode => xu_iu_flush_2ucode, + xu_iu_flush_2ucode_type => xu_iu_flush_2ucode_type, + xu_iu_ucode_restart => xu_iu_ucode_restart, + xu_iu_ex5_ppc_cpl => xu_iu_ex5_ppc_cpl, + + -- Flushes + xu_n_is2_flush => xu_n_is2_flush, + xu_n_rf0_flush => xu_n_rf0_flush, + xu_n_rf1_flush => xu_n_rf1_flush, + xu_n_ex1_flush => xu_n_ex1_flush, + xu_n_ex2_flush => xu_n_ex2_flush, + xu_n_ex3_flush => xu_n_ex3_flush, + xu_n_ex4_flush => xu_n_ex4_flush, + xu_n_ex5_flush => xu_n_ex5_flush, + xu_s_rf1_flush => xu_s_rf1_flush_int, + xu_s_ex1_flush => xu_s_ex1_flush_int, + xu_s_ex2_flush => xu_s_ex2_flush_int, + xu_s_ex3_flush => xu_s_ex3_flush_int, + xu_s_ex4_flush => xu_s_ex4_flush_int, + xu_s_ex5_flush => xu_s_ex5_flush_int, + xu_w_rf1_flush => xu_w_rf1_flush, + xu_w_ex1_flush => xu_w_ex1_flush, + xu_w_ex2_flush => xu_w_ex2_flush, + xu_w_ex3_flush => xu_w_ex3_flush, + xu_w_ex4_flush => xu_w_ex4_flush, + xu_w_ex5_flush => xu_w_ex5_flush, + xu_lsu_ex4_flush_local => xu_lsu_ex4_flush_local, + xu_mm_ex4_flush => xu_mm_ex4_flush, + xu_mm_ex5_flush => xu_mm_ex5_flush, + xu_mm_ierat_flush => xu_mm_ierat_flush, + xu_mm_ierat_miss => xu_mm_ierat_miss, + xu_mm_ex5_perf_itlb => xu_mm_ex5_perf_itlb, + xu_mm_ex5_perf_dtlb => xu_mm_ex5_perf_dtlb, + + -- SPR Bits + spr_bit_act => spr_bit_act, + spr_cpl_iac1_en => spr_cpl_iac1_en, + spr_cpl_iac2_en => spr_cpl_iac2_en, + spr_cpl_iac3_en => spr_cpl_iac3_en, + spr_cpl_iac4_en => spr_cpl_iac4_en, + spr_dbcr1_iac12m => spr_dbcr1_iac12m, + spr_dbcr1_iac34m => spr_dbcr1_iac34m, + spr_epcr_duvd => spr_epcr_duvd, + spr_cpl_fp_precise => spr_cpl_fp_precise, + spr_xucr0_mddp => spr_xucr0_mddp, + spr_xucr0_mdcp => spr_xucr0_mdcp, + spr_msr_de => spr_msr_de, + spr_msr_spv => spr_msr_spv_int, + spr_msr_fp => spr_msr_fp_int, + spr_msr_me => spr_msr_me, + spr_msr_ucle => spr_msr_ucle, + spr_msrp_uclep => spr_msrp_uclep, + spr_ccr2_ucode_dis => spr_ccr2_ucode_dis, + spr_ccr2_ap => spr_ccr2_ap_int, + spr_dbcr0_idm => spr_dbcr0_idm, + cpl_spr_dbcr0_edm => cpl_spr_dbcr0_edm, + spr_dbcr0_icmp => spr_dbcr0_icmp, + spr_dbcr0_brt => spr_dbcr0_brt, + spr_dbcr0_trap => spr_dbcr0_trap, + spr_dbcr0_ret => spr_dbcr0_ret, + spr_dbcr0_irpt => spr_dbcr0_irpt, + spr_epcr_dsigs => spr_epcr_dsigs, + spr_epcr_isigs => spr_epcr_isigs, + spr_epcr_extgs => spr_epcr_extgs, + spr_epcr_dtlbgs => spr_epcr_dtlbgs, + spr_epcr_itlbgs => spr_epcr_itlbgs, + spr_xucr4_div_barr_thres => spr_xucr4_div_barr_thres, + spr_ccr0_we => spr_ccr0_we, + cpl_msr_gs => cpl_msr_gs, + cpl_msr_pr => cpl_msr_pr, + cpl_msr_fp => cpl_msr_fp, + cpl_msr_spv => cpl_msr_spv, + cpl_ccr2_ap => cpl_ccr2_ap, + spr_xucr0_clkg_ctl => spr_xucr0_clkg_ctl(1 to 3), + spr_xucr4_mmu_mchk => spr_xucr4_mmu_mchk, + + -- Parity + spr_cpl_ex3_sprg_ce => spr_cpl_ex3_sprg_ce, + spr_cpl_ex3_sprg_ue => spr_cpl_ex3_sprg_ue, + iu_xu_ierat_ex2_flush_req => iu_xu_ierat_ex2_flush_req, + iu_xu_ierat_ex3_par_err => iu_xu_ierat_ex3_par_err, + iu_xu_ierat_ex4_par_err => iu_xu_ierat_ex4_par_err, + + -- Regfile Parity + fu_xu_ex3_regfile_err_det => fu_xu_ex3_regfile_err_det, + xu_fu_regfile_seq_beg => xu_fu_regfile_seq_beg, + fu_xu_regfile_seq_end => fu_xu_regfile_seq_end, + gpr_cpl_ex3_regfile_err_det => gpr_cpl_ex3_regfile_err_det, + cpl_gpr_regfile_seq_beg => cpl_gpr_regfile_seq_beg, + gpr_cpl_regfile_seq_end => gpr_cpl_regfile_seq_end, + xu_pc_err_mcsr_summary => xu_pc_err_mcsr_summary, + xu_pc_err_ditc_overrun => xu_pc_err_ditc_overrun, + xu_pc_err_local_snoop_reject => xu_pc_err_local_snoop_reject, + xu_pc_err_tlb_lru_parity => xu_pc_err_tlb_lru_parity, + xu_pc_err_ext_mchk => xu_pc_err_ext_mchk, + xu_pc_err_ierat_multihit => xu_pc_err_ierat_multihit, + xu_pc_err_derat_multihit => xu_pc_err_derat_multihit, + xu_pc_err_tlb_multihit => xu_pc_err_tlb_multihit, + xu_pc_err_ierat_parity => xu_pc_err_ierat_parity, + xu_pc_err_derat_parity => xu_pc_err_derat_parity, + xu_pc_err_tlb_parity => xu_pc_err_tlb_parity, + xu_pc_err_mchk_disabled => xu_pc_err_mchk_disabled, + xu_pc_err_sprg_ue => xu_pc_err_sprg_ue, + + -- Debug + xu_iu_rf1_val => xu_iu_rf1_val, + xu_rf1_val => xu_rf1_val, + xu_rf1_is_tlbre => xu_rf1_is_tlbre, + xu_rf1_is_tlbwe => xu_rf1_is_tlbwe, + xu_rf1_is_tlbsx => xu_rf1_is_tlbsx, + xu_rf1_is_tlbsrx => xu_rf1_is_tlbsrx, + xu_rf1_is_tlbilx => xu_rf1_is_tlbilx, + xu_rf1_is_tlbivax => xu_rf1_is_tlbivax, + xu_rf1_is_eratre => xu_rf1_is_eratre, + xu_rf1_is_eratwe => xu_rf1_is_eratwe, + xu_rf1_is_eratsx => xu_rf1_is_eratsx, + xu_rf1_is_eratilx => xu_rf1_is_eratilx, + xu_rf1_is_erativax => xu_rf1_is_erativax, + xu_ex1_is_isync => xu_ex1_is_isync, + xu_ex1_is_csync => xu_ex1_is_csync, + xu_rf1_ws => xu_rf1_ws, + xu_rf1_t => xu_rf1_t, + xu_ex1_rs_is => xu_ex1_rs_is, + xu_ex1_ra_entry => xu_ex1_ra_entry, + xu_ex4_rs_data => xu_ex4_rs_data, + + xu_lsu_rf1_data_act => xu_lsu_rf1_data_act, + xu_lsu_rf1_axu_ldst_falign => xu_lsu_rf1_axu_ldst_falign, + xu_lsu_ex1_store_data => xu_lsu_ex1_store_data, + xu_lsu_ex1_rotsel_ovrd => xu_lsu_ex1_rotsel_ovrd, + xu_lsu_ex1_eff_addr => xu_lsu_ex1_eff_addr, + + -- Barrier + cpl_fxa_ex5_set_barr => cpl_fxa_ex5_set_barr, + cpl_iu_set_barr_tid => cpl_iu_set_barr_tid, + + lsu_xu_ex6_datc_par_err => lsu_xu_ex6_datc_par_err, + + lsu_xu_ex2_dvc1_st_cmp => lsu_xu_ex2_dvc1_st_cmp, + lsu_xu_ex2_dvc2_st_cmp => lsu_xu_ex2_dvc2_st_cmp, + lsu_xu_ex8_dvc1_ld_cmp => lsu_xu_ex8_dvc1_ld_cmp, + lsu_xu_ex8_dvc2_ld_cmp => lsu_xu_ex8_dvc2_ld_cmp, + lsu_xu_rel_dvc1_en => lsu_xu_rel_dvc1_en, + lsu_xu_rel_dvc2_en => lsu_xu_rel_dvc2_en, + lsu_xu_rel_dvc_thrd_id => lsu_xu_rel_dvc_thrd_id, + lsu_xu_rel_dvc1_cmp => lsu_xu_rel_dvc1_cmp, + lsu_xu_rel_dvc2_cmp => lsu_xu_rel_dvc2_cmp, + + lsu_xu_rot_ex6_data_b => lsu_xu_rot_ex6_data_b, + lsu_xu_rot_rel_data => lsu_xu_rot_rel_data, + pc_xu_trace_bus_enable => pc_xu_trace_bus_enable, + pc_xu_instr_trace_mode => pc_xu_instr_trace_mode, + pc_xu_instr_trace_tid => pc_xu_instr_trace_tid, + iu_xu_ex4_tlb_data => iu_xu_ex4_tlb_data, + + -- Error Inject + pc_xu_inj_dcachedir_parity => pc_xu_inj_dcachedir_parity, + pc_xu_inj_dcachedir_multihit => pc_xu_inj_dcachedir_multihit, + + ex4_256st_data => ex4_256st_data, + + xu_lsu_mtspr_trace_en => xu_lsu_mtspr_trace_en, + xu_lsu_spr_xucr0_aflsta => xu_lsu_spr_xucr0_aflsta, + xu_lsu_spr_xucr0_flsta => xu_lsu_spr_xucr0_flsta, + xu_lsu_spr_xucr0_l2siw => xu_lsu_spr_xucr0_l2siw, + xu_lsu_spr_xucr0_dcdis => xu_lsu_spr_xucr0_dcdis_int, + xu_lsu_spr_xucr0_wlk => xu_lsu_spr_xucr0_wlk, + xu_lsu_spr_xucr0_clfc => xu_lsu_spr_xucr0_clfc, + xu_lsu_spr_xucr0_flh2l2 => xu_lsu_spr_xucr0_flh2l2, + xu_lsu_spr_xucr0_cred => xu_lsu_spr_xucr0_cred, + xu_lsu_spr_xucr0_rel => xu_lsu_spr_xucr0_rel_int, + xu_lsu_spr_xucr0_mbar_ack => xu_lsu_spr_xucr0_mbar_ack, + xu_lsu_spr_xucr0_tlbsync => xu_lsu_spr_xucr0_tlbsync, + xu_lsu_spr_xucr0_cls => xu_lsu_spr_xucr0_cls, + xu_lsu_spr_ccr2_dfrat => xu_lsu_spr_ccr2_dfrat, + xu_lsu_spr_ccr2_dfratsc => xu_lsu_spr_ccr2_dfratsc, + + an_ac_flh2l2_gate => an_ac_flh2l2_gate, + + -- ERAT Operations + xu_lsu_rf0_derat_val => xu_lsu_rf0_derat_val, + xu_lsu_rf0_derat_is_extload => xu_lsu_rf0_derat_is_extload, + xu_lsu_rf0_derat_is_extstore => xu_lsu_rf0_derat_is_extstore, + + + xu_lsu_hid_mmu_mode => xu_lsu_hid_mmu_mode, + ex6_ld_par_err => ex6_ld_par_err, + + xu_mm_derat_req => xu_mm_derat_req, + xu_mm_derat_thdid => xu_mm_derat_thdid, + xu_mm_derat_state => xu_mm_derat_state, + xu_mm_derat_tid => xu_mm_derat_tid, + xu_mm_derat_lpid => xu_mm_derat_lpid, + xu_mm_derat_ttype => xu_mm_derat_ttype, + mm_xu_derat_rel_val => mm_xu_derat_rel_val, + mm_xu_derat_rel_data => mm_xu_derat_rel_data, + mm_xu_derat_pid0 => mm_xu_derat_pid0, + mm_xu_derat_pid1 => mm_xu_derat_pid1, + mm_xu_derat_pid2 => mm_xu_derat_pid2, + mm_xu_derat_pid3 => mm_xu_derat_pid3, + mm_xu_derat_mmucr0_0 => mm_xu_derat_mmucr0_0, + mm_xu_derat_mmucr0_1 => mm_xu_derat_mmucr0_1, + mm_xu_derat_mmucr0_2 => mm_xu_derat_mmucr0_2, + mm_xu_derat_mmucr0_3 => mm_xu_derat_mmucr0_3, + xu_mm_derat_mmucr0 => xu_mm_derat_mmucr0, + xu_mm_derat_mmucr0_we => xu_mm_derat_mmucr0_we, + mm_xu_derat_mmucr1 => mm_xu_derat_mmucr1, + xu_mm_derat_mmucr1 => xu_mm_derat_mmucr1, + xu_mm_derat_mmucr1_we => xu_mm_derat_mmucr1_we, + mm_xu_derat_snoop_coming => mm_xu_derat_snoop_coming, + mm_xu_derat_snoop_val => mm_xu_derat_snoop_val, + mm_xu_derat_snoop_attr => mm_xu_derat_snoop_attr, + mm_xu_derat_snoop_vpn => mm_xu_derat_snoop_vpn, + xu_mm_derat_snoop_ack => xu_mm_derat_snoop_ack, + + xu_lsu_slowspr_val => xu_lsu_slowspr_val, + xu_lsu_slowspr_rw => xu_lsu_slowspr_rw, + xu_lsu_slowspr_etid => xu_lsu_slowspr_etid, + xu_lsu_slowspr_addr => xu_lsu_slowspr_addr, + xu_lsu_slowspr_data => xu_lsu_slowspr_data, + xu_lsu_slowspr_done => xu_lsu_slowspr_done, + slowspr_val_out => slowspr_val_out, + slowspr_rw_out => slowspr_rw_out, + slowspr_etid_out => slowspr_etid_out, + slowspr_addr_out => slowspr_addr_out, + slowspr_data_out => slowspr_data_out, + slowspr_done_out => slowspr_done_out, + + ex1_optype1 => ex1_optype1, + ex1_optype2 => ex1_optype2, + ex1_optype4 => ex1_optype4, + ex1_optype8 => ex1_optype8, + ex1_optype16 => ex1_optype16, + ex1_optype32 => ex1_optype32, + ex1_saxu_instr => ex1_saxu_instr, + ex1_sdp_instr => ex1_sdp_instr, + ex1_stgpr_instr => ex1_stgpr_instr, + ex1_store_instr => ex1_store_instr, + ex1_axu_op_val => ex1_axu_op_val, + + ex3_algebraic => ex3_algebraic, + ex3_data_swap => ex3_data_swap, + ex3_thrd_id => ex3_thrd_id, + xu_fu_ex3_eff_addr => xu_fu_ex3_eff_addr, + xu_lsu_ici => xu_lsu_ici, + + -- Update Data Array Valid + rel_upd_dcarr_val => rel_upd_dcarr_val, + + xu_fu_ex5_reload_val => xu_fu_ex5_reload_val, + xu_fu_ex5_load_val => xu_fu_ex5_load_val, + xu_fu_ex5_load_tag => xu_fu_ex5_load_tag, + + -- Data Array Controls + dcarr_up_way_addr => dcarr_up_way_addr, + + -- SPR status + lsu_xu_spr_xucr0_cslc_xuop => lsu_xu_spr_xucr0_cslc_xuop, + lsu_xu_spr_xucr0_cslc_binv => lsu_xu_spr_xucr0_cslc_binv, + lsu_xu_spr_xucr0_clo => lsu_xu_spr_xucr0_clo, + lsu_xu_spr_xucr0_cul => lsu_xu_spr_xucr0_cul, + lsu_xu_spr_epsc_epr => lsu_xu_spr_epsc_epr, + lsu_xu_spr_epsc_egs => lsu_xu_spr_epsc_egs, + + -- Debug Data Compare + ex4_load_op_hit => ex4_load_op_hit, + ex4_store_hit => ex4_store_hit, + ex4_axu_op_val => ex4_axu_op_val, + spr_dvc1_act => spr_dvc1_act, + spr_dvc2_act => spr_dvc2_act, + spr_dvc1_dbg => spr_dvc1_dbg, + spr_dvc2_dbg => spr_dvc2_dbg, + + -- Inputs from L2 + an_ac_req_ld_pop => an_ac_req_ld_pop, + an_ac_req_st_pop => an_ac_req_st_pop, + an_ac_req_st_gather => an_ac_req_st_gather, + an_ac_req_st_pop_thrd => an_ac_req_st_pop_thrd, + an_ac_reld_data_vld => an_ac_reld_data_vld, + an_ac_reld_core_tag => an_ac_reld_core_tag, + an_ac_reld_qw => an_ac_reld_qw, + an_ac_reld_data => an_ac_reld_data, + an_ac_reld_data_coming => an_ac_reld_data_coming, + an_ac_reld_ditc => an_ac_reld_ditc, + an_ac_reld_crit_qw => an_ac_reld_crit_qw, + an_ac_reld_l1_dump => an_ac_reld_l1_dump, + an_ac_reld_ecc_err => an_ac_reld_ecc_err, + an_ac_reld_ecc_err_ue => an_ac_reld_ecc_err_ue, + an_ac_back_inv => an_ac_back_inv, + an_ac_back_inv_addr => an_ac_back_inv_addr, + an_ac_back_inv_target_bit1 => an_ac_back_inv_target_bit1, + an_ac_back_inv_target_bit3 => an_ac_back_inv_target_bit3, + an_ac_back_inv_target_bit4 => an_ac_back_inv_target_bit4, + an_ac_req_spare_ctrl_a1 => an_ac_req_spare_ctrl_a1, + + -- redrive to boxes logic + lsu_reld_data_vld => lsu_reld_data_vld, + lsu_reld_core_tag => lsu_reld_core_tag, + lsu_reld_qw => lsu_reld_qw, + lsu_reld_ditc => lsu_reld_ditc, + lsu_reld_ecc_err => lsu_reld_ecc_err, + lsu_reld_data => lsu_reld_data, + + lsu_req_st_pop => lsu_req_st_pop, + lsu_req_st_pop_thrd => lsu_req_st_pop_thrd, + + -- latch and redrive for BXQ + ac_an_reld_ditc_pop_int => ac_an_reld_ditc_pop_int, + ac_an_reld_ditc_pop_q => ac_an_reld_ditc_pop_q , + bx_ib_empty_int => bx_ib_empty_int , + bx_ib_empty_q => bx_ib_empty_q , + + -- Instruction Fetches + iu_xu_ra => iu_xu_ra, + iu_xu_request => iu_xu_request, + iu_xu_wimge => iu_xu_wimge, + iu_xu_thread => iu_xu_thread, + iu_xu_userdef => iu_xu_userdef, + + -- MMU instruction interface + mm_xu_lsu_req => mm_xu_lsu_req, + mm_xu_lsu_ttype => mm_xu_lsu_ttype, + mm_xu_lsu_wimge => mm_xu_lsu_wimge, + mm_xu_lsu_u => mm_xu_lsu_u, + mm_xu_lsu_addr => mm_xu_lsu_addr, + mm_xu_lsu_lpid => mm_xu_lsu_lpid, + mm_xu_lsu_lpidr => mm_xu_lsu_lpidr, + mm_xu_lsu_gs => mm_xu_lsu_gs, + mm_xu_lsu_ind => mm_xu_lsu_ind, + mm_xu_lsu_lbit => mm_xu_lsu_lbit, + xu_mm_lsu_token => xu_mm_lsu_token, + + -- Boxes interface + bx_lsu_ob_pwr_tok => bx_lsu_ob_pwr_tok, + bx_lsu_ob_req_val => bx_lsu_ob_req_val, + bx_lsu_ob_ditc_val => bx_lsu_ob_ditc_val, + bx_lsu_ob_thrd => bx_lsu_ob_thrd, + bx_lsu_ob_qw => bx_lsu_ob_qw, + bx_lsu_ob_dest => bx_lsu_ob_dest, + bx_lsu_ob_data => bx_lsu_ob_data, + bx_lsu_ob_addr => bx_lsu_ob_addr, + lsu_bx_cmd_avail => lsu_bx_cmd_avail, + lsu_bx_cmd_sent => lsu_bx_cmd_sent, + lsu_bx_cmd_stall => lsu_bx_cmd_stall, + + lsu_xu_ldq_barr_done => lsu_xu_ldq_barr_done, + lsu_xu_barr_done => lsu_xu_barr_done, + + -- *** Reload operation Outputs *** + ldq_rel_data_val_early => ldq_rel_data_val_early, + ldq_rel_op_size => ldq_rel_op_size, + ldq_rel_addr => ldq_rel_addr, + ldq_rel_data_val => ldq_rel_data_val, + ldq_rel_rot_sel => ldq_rel_rot_sel, + ldq_rel_axu_val => ldq_rel_axu_val, + ldq_rel_ci => ldq_rel_ci, + ldq_rel_thrd_id => ldq_rel_thrd_id, + ldq_rel_le_mode => ldq_rel_le_mode, + ldq_rel_algebraic => ldq_rel_algebraic, + ldq_rel_256_data => ldq_rel_256_data, + ldq_rel_dvc1_en => ldq_rel_dvc1_en, + ldq_rel_dvc2_en => ldq_rel_dvc2_en, + ldq_rel_beat_crit_qw => ldq_rel_beat_crit_qw, + ldq_rel_beat_crit_qw_block => ldq_rel_beat_crit_qw_block, + lsu_xu_rel_wren => lsu_xu_rel_wren, + lsu_xu_rel_ta_gpr => lsu_xu_rel_ta_gpr, + + xu_iu_ex4_loadmiss_qentry => xu_iu_ex4_loadmiss_qentry, + xu_iu_ex4_loadmiss_target => xu_iu_ex4_loadmiss_target, + xu_iu_ex4_loadmiss_target_type => xu_iu_ex4_loadmiss_target_type, + xu_iu_ex4_loadmiss_tid => xu_iu_ex4_loadmiss_tid, + xu_iu_ex5_loadmiss_qentry => xu_iu_ex5_loadmiss_qentry, + xu_iu_ex5_loadmiss_target => xu_iu_ex5_loadmiss_target, + xu_iu_ex5_loadmiss_target_type => xu_iu_ex5_loadmiss_target_type, + xu_iu_ex5_loadmiss_tid => xu_iu_ex5_loadmiss_tid, + xu_iu_complete_qentry => xu_iu_complete_qentry, + xu_iu_complete_tid => xu_iu_complete_tid, + xu_iu_complete_target_type => xu_iu_complete_target_type, + + -- ICBI Interface + xu_iu_ex6_icbi_val => xu_iu_ex6_icbi_val, + xu_iu_ex6_icbi_addr => xu_iu_ex6_icbi_addr, + + xu_iu_larx_done_tid => xu_iu_larx_done_tid, + xu_mm_lmq_stq_empty => xu_mm_lmq_stq_empty, + lsu_xu_quiesce => lsu_xu_quiesce, + lsu_xu_dbell_val => lsu_xu_dbell_val, + lsu_xu_dbell_type => lsu_xu_dbell_type, + lsu_xu_dbell_brdcast => lsu_xu_dbell_brdcast, + lsu_xu_dbell_lpid_match => lsu_xu_dbell_lpid_match, + lsu_xu_dbell_pirtag => lsu_xu_dbell_pirtag, + + xu_ex1_rb => xu_ex1_rb, + xu_ex2_eff_addr => xu_ex2_eff_addr, + + ac_an_req_pwr_token => ac_an_req_pwr_token, + ac_an_req => ac_an_req, + ac_an_req_ra => ac_an_req_ra, + ac_an_req_ttype => ac_an_req_ttype, + ac_an_req_thread => ac_an_req_thread, + ac_an_req_wimg_w => ac_an_req_wimg_w, + ac_an_req_wimg_i => ac_an_req_wimg_i, + ac_an_req_wimg_m => ac_an_req_wimg_m, + ac_an_req_wimg_g => ac_an_req_wimg_g, + ac_an_req_endian => ac_an_req_endian, + ac_an_req_user_defined => ac_an_req_user_defined, + ac_an_req_spare_ctrl_a0 => ac_an_req_spare_ctrl_a0, + ac_an_req_ld_core_tag => ac_an_req_ld_core_tag, + ac_an_req_ld_xfr_len => ac_an_req_ld_xfr_len, + ac_an_st_byte_enbl => ac_an_st_byte_enbl, + ac_an_st_data => ac_an_st_data, + ac_an_st_data_pwr_token => ac_an_st_data_pwr_token, + + --pervasive + xu_pc_err_dcachedir_parity => xu_pc_err_dcachedir_parity, + xu_pc_err_dcachedir_multihit => xu_pc_err_dcachedir_multihit, + xu_pc_err_l2intrf_ecc => xu_pc_err_l2intrf_ecc, + xu_pc_err_l2intrf_ue => xu_pc_err_l2intrf_ue, + xu_pc_err_invld_reld => xu_pc_err_invld_reld, + xu_pc_err_l2credit_overrun => xu_pc_err_l2credit_overrun, + + -- Performance Counters + pc_xu_event_bus_enable => pc_xu_event_bus_enable, + pc_xu_lsu_event_mux_ctrls => pc_xu_lsu_event_mux_ctrls, + pc_xu_cache_par_err_event => pc_xu_cache_par_err_event, + xu_pc_lsu_event_data => xu_pc_lsu_event_data, + + -- Debug Trace Bus + lsu_xu_cmd_debug => lsu_xu_cmd_debug, + + -- G8T ABIST Control + an_ac_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc, + pc_xu_abist_g8t_wenb => pc_xu_abist_g8t_wenb, + pc_xu_abist_g8t1p_renb_0 => pc_xu_abist_g8t1p_renb_0, + pc_xu_abist_g8t_bw_1 => pc_xu_abist_g8t_bw_1, + pc_xu_abist_g8t_bw_0 => pc_xu_abist_g8t_bw_0, + pc_xu_abist_wl32_comp_ena => pc_xu_abist_wl32_comp_ena, + pc_xu_abist_g8t_dcomp => pc_xu_abist_g8t_dcomp, + pc_xu_bo_unload => pc_xu_bo_unload, + pc_xu_bo_repair => pc_xu_bo_repair, + pc_xu_bo_reset => pc_xu_bo_reset, + pc_xu_bo_shdata => pc_xu_bo_shdata, + pc_xu_bo_select => pc_xu_bo_select(1 to 4), + xu_pc_bo_fail => xu_pc_bo_fail(1 to 4), + xu_pc_bo_diagout => xu_pc_bo_diagout(1 to 4), + + vcs => vcs, + vdd => vdd, + gnd => gnd, + nclk => nclk, + an_ac_coreid => an_ac_coreid(60 to 61), + an_ac_atpg_en_dc => an_ac_atpg_en_dc, + + -- Pervasive + bcfg_scan_in => ctrl_bcfg_scan_in, + bcfg_scan_out => ctrl_bcfg_scan_out, + dcfg_scan_in => ctrl_dcfg_scan_in, + dcfg_scan_out => ctrl_dcfg_scan_out, + gptr_scan_in => ctrl_gptr_scan_in, + gptr_scan_out => ctrl_gptr_scan_out, + time_scan_in => ctrl_time_scan_in, + time_scan_out => ctrl_time_scan_out, + func_scan_in => func_scan_in(41 to 58), + func_scan_out => func_scan_out(41 to 58), + ccfg_scan_in => ctrl_ccfg_scan_in, + ccfg_scan_out => ctrl_ccfg_scan_out, + regf_scan_in => regf_scan_in, + regf_scan_out => regf_scan_out, + abst_scan_in => abst_scan_in(0), + abst_scan_out => abst_scan_out(0), + repr_scan_in => ctrl_repr_scan_in, + repr_scan_out => ctrl_repr_scan_out +); + +-- ########################################################################################## +-- SPR +-- ########################################################################################## +xu_spr : entity work.xuq_spr(xuq_spr) +generic map( + hvmode => hvmode, + a2mode => a2mode, + expand_type => expand_type, + threads => threads, + regsize => regsize, + eff_ifar => eff_ifar, + spr_xucr0_init_mod => spr_xucr0_init_mod) +port map( + nclk => nclk, + + -- CHIP IO + an_ac_coreid => an_ac_coreid, + spr_pvr_version_dc => spr_pvr_version_dc, + spr_pvr_revision_dc => spr_pvr_revision_dc, + an_ac_ext_interrupt => an_ac_ext_interrupt, + an_ac_crit_interrupt => an_ac_crit_interrupt, + an_ac_perf_interrupt => an_ac_perf_interrupt, + an_ac_reservation_vld => an_ac_reservation_vld, + an_ac_tb_update_pulse => an_ac_tb_update_pulse, + an_ac_tb_update_enable => an_ac_tb_update_enable, + an_ac_sleep_en => an_ac_sleep_en, + an_ac_hang_pulse => an_ac_hang_pulse, + ac_tc_machine_check => ac_tc_machine_check, + an_ac_external_mchk => an_ac_external_mchk, + pc_xu_instr_trace_mode => pc_xu_instr_trace_mode, + pc_xu_instr_trace_tid => pc_xu_instr_trace_tid, + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b, + an_ac_scan_diag_dc => an_ac_scan_diag_dc, + pc_xu_ccflush_dc => pc_xu_ccflush_dc, + clkoff_dc_b => clkoff_dc_b_b, + d_mode_dc => d_mode_dc_b, + delay_lclkr_dc => delay_lclkr_dc_b(2), + mpw1_dc_b => mpw1_dc_b_b(2), + mpw2_dc_b => mpw2_dc_b_b, + func_sl_thold_2 => func_sl_thold_2_b(1), + func_slp_sl_thold_2 => func_slp_sl_thold_2_b(0), + func_nsl_thold_2 => func_nsl_thold_2_b, + func_slp_nsl_thold_2 => func_slp_nsl_thold_2_b, + cfg_sl_thold_2 => cfg_sl_thold_2_b, + cfg_slp_sl_thold_2 => cfg_slp_sl_thold_2_b, + ary_nsl_thold_2 => ary_nsl_thold_2_b, + time_sl_thold_2 => time_sl_thold_2_b, + gptr_sl_thold_2 => gptr_sl_thold_2_b, + abst_sl_thold_2 => abst_sl_thold_2_b, + repr_sl_thold_2 => repr_sl_thold_2_b, + sg_2 => sg_2_b(1), + fce_2 => fce_2_b(0), + func_scan_in => func_scan_in(35 to 40), + func_scan_out => func_scan_out(35 to 40), + bcfg_scan_in => spr_bcfg_scan_in, + bcfg_scan_out => spr_bcfg_scan_out, + ccfg_scan_in => spr_ccfg_scan_in, + ccfg_scan_out => spr_ccfg_scan_out, + dcfg_scan_in => spr_dcfg_scan_in, + dcfg_scan_out => spr_dcfg_scan_out, + time_scan_in => spr_time_scan_in, + time_scan_out => spr_time_scan_out, + abst_scan_in => abst_scan_in(1), + abst_scan_out => abst_scan_out(1), + repr_scan_in => spr_repr_scan_in, + repr_scan_out => spr_repr_scan_out, + gptr_scan_in => spr_gptr_scan_in, + gptr_scan_out => spr_gptr_scan_out, + + -- Decode + dec_spr_rf0_tid => dec_spr_rf0_tid, + dec_spr_rf0_instr => dec_spr_rf0_instr, + dec_spr_rf1_val => dec_spr_rf1_val, + dec_spr_ex1_epid_instr => dec_spr_ex1_epid_instr, + dec_spr_ex4_val => dec_spr_ex4_val, + + -- Read Data + spr_byp_ex3_spr_rt => spr_byp_ex3_spr_rt, + + fxu_spr_ex1_rs2 => fxu_spr_ex1_rs2, + + -- Write Data + fxu_spr_ex1_rs0 => fxu_spr_ex1_rs0, + fxu_spr_ex1_rs1 => fxu_spr_ex1_rs1, + mux_spr_ex2_rt => mux_spr_ex2_rt, + + -- Interrupt Interface + cpl_spr_ex5_act => cpl_spr_ex5_act, + cpl_spr_ex5_int => cpl_spr_ex5_int, + cpl_spr_ex5_gint => cpl_spr_ex5_gint, + cpl_spr_ex5_cint => cpl_spr_ex5_cint, + cpl_spr_ex5_mcint => cpl_spr_ex5_mcint, + cpl_spr_ex5_nia => cpl_spr_ex5_nia, + cpl_spr_ex5_esr => cpl_spr_ex5_esr, + cpl_spr_ex5_mcsr => cpl_spr_ex5_mcsr, + cpl_spr_ex5_dbsr => cpl_spr_ex5_dbsr, + cpl_spr_ex5_dear_save => cpl_spr_ex5_dear_save, + cpl_spr_ex5_dear_update_saved => cpl_spr_ex5_dear_update_saved, + cpl_spr_ex5_dear_update => cpl_spr_ex5_dear_update, + cpl_spr_ex5_dbsr_update => cpl_spr_ex5_dbsr_update, + cpl_spr_ex5_esr_update => cpl_spr_ex5_esr_update, + cpl_spr_ex5_srr0_dec => cpl_spr_ex5_srr0_dec, + cpl_spr_ex5_force_gsrr => cpl_spr_ex5_force_gsrr, + cpl_spr_ex5_dbsr_ide => cpl_spr_ex5_dbsr_ide, + spr_cpl_dbsr_ide => spr_cpl_dbsr_ide, + + -- Async Interrupt Req Interface + spr_cpl_external_mchk => spr_cpl_external_mchk, + spr_cpl_ext_interrupt => spr_cpl_ext_interrupt, + spr_cpl_udec_interrupt => spr_cpl_udec_interrupt, + spr_cpl_perf_interrupt => spr_cpl_perf_interrupt, + spr_cpl_dec_interrupt => spr_cpl_dec_interrupt, + spr_cpl_fit_interrupt => spr_cpl_fit_interrupt, + spr_cpl_crit_interrupt => spr_cpl_crit_interrupt, + spr_cpl_wdog_interrupt => spr_cpl_wdog_interrupt, + spr_cpl_dbell_interrupt => spr_cpl_dbell_interrupt, + spr_cpl_cdbell_interrupt => spr_cpl_cdbell_interrupt, + spr_cpl_gdbell_interrupt => spr_cpl_gdbell_interrupt, + spr_cpl_gcdbell_interrupt => spr_cpl_gcdbell_interrupt, + spr_cpl_gmcdbell_interrupt => spr_cpl_gmcdbell_interrupt, + cpl_spr_ex5_dbell_taken => cpl_spr_ex5_dbell_taken, + cpl_spr_ex5_cdbell_taken => cpl_spr_ex5_cdbell_taken, + cpl_spr_ex5_gdbell_taken => cpl_spr_ex5_gdbell_taken, + cpl_spr_ex5_gcdbell_taken => cpl_spr_ex5_gcdbell_taken, + cpl_spr_ex5_gmcdbell_taken => cpl_spr_ex5_gmcdbell_taken, + + -- DBELL Int + lsu_xu_dbell_val => lsu_xu_dbell_val, + lsu_xu_dbell_type => lsu_xu_dbell_type, + lsu_xu_dbell_brdcast => lsu_xu_dbell_brdcast, + lsu_xu_dbell_lpid_match => lsu_xu_dbell_lpid_match, + lsu_xu_dbell_pirtag => lsu_xu_dbell_pirtag, + + -- Slow SPR Bus + xu_lsu_slowspr_val => xu_lsu_slowspr_val, + xu_lsu_slowspr_rw => xu_lsu_slowspr_rw, + xu_lsu_slowspr_etid => xu_lsu_slowspr_etid, + xu_lsu_slowspr_addr => xu_lsu_slowspr_addr, + xu_lsu_slowspr_data => xu_lsu_slowspr_data, + + -- DCR Bus + ac_an_dcr_act => ac_an_dcr_act, + ac_an_dcr_val => ac_an_dcr_val, + ac_an_dcr_read => ac_an_dcr_read, + ac_an_dcr_user => ac_an_dcr_user, + ac_an_dcr_etid => ac_an_dcr_etid, + ac_an_dcr_addr => ac_an_dcr_addr, + ac_an_dcr_data => ac_an_dcr_data, + + -- Flush + xu_ex4_flush => xu_s_ex4_flush_int, + xu_ex5_flush => xu_s_ex5_flush_int, + + -- Trap + spr_cpl_fp_precise => spr_cpl_fp_precise, + spr_cpl_ex3_spr_hypv => spr_cpl_ex3_spr_hypv, + spr_cpl_ex3_spr_illeg => spr_cpl_ex3_spr_illeg, + spr_cpl_ex3_spr_priv => spr_cpl_ex3_spr_priv, + spr_cpl_ex3_ct_le => spr_cpl_ex3_ct_le, + spr_cpl_ex3_ct_be => spr_cpl_ex3_ct_be, + + -- Run State + cpl_spr_stop => cpl_spr_stop, + xu_pc_running => xu_pc_running, + xu_iu_run_thread => xu_iu_run_thread, + xu_iu_single_instr_mode => xu_iu_single_instr_mode, + xu_iu_raise_iss_pri => xu_iu_raise_iss_pri, + spr_cpl_ex2_run_ctl_flush => spr_cpl_ex2_run_ctl_flush, + xu_pc_spr_ccr0_we => spr_ccr0_we, + + -- Quiesce + iu_xu_quiesce => iu_xu_quiesce, + lsu_xu_quiesce => lsu_xu_quiesce, + mm_xu_quiesce => mm_xu_quiesce, + bx_xu_quiesce => bx_xu_quiesce, + spr_cpl_quiesce => spr_cpl_quiesce, + cpl_spr_quiesce => cpl_spr_quiesce, + + -- PCCR0 + pc_xu_extirpts_dis_on_stop => pc_xu_extirpts_dis_on_stop, + pc_xu_timebase_dis_on_stop => pc_xu_timebase_dis_on_stop, + pc_xu_decrem_dis_on_stop => pc_xu_decrem_dis_on_stop, + + -- MSR Override + pc_xu_ram_mode => pc_xu_ram_mode, + pc_xu_ram_thread => pc_xu_ram_thread, + pc_xu_msrovride_enab => pc_xu_msrovride_enab, + pc_xu_msrovride_pr => pc_xu_msrovride_pr, + pc_xu_msrovride_gs => pc_xu_msrovride_gs, + pc_xu_msrovride_de => pc_xu_msrovride_de, + + -- LiveLock + cpl_spr_ex5_instr_cpl => cpl_spr_ex5_instr_cpl, + xu_pc_err_llbust_attempt => xu_pc_err_llbust_attempt, + xu_pc_err_llbust_failed => xu_pc_err_llbust_failed, + + -- XER + spr_byp_ex4_is_mtxer => spr_byp_ex4_is_mtxer, + spr_byp_ex4_is_mfxer => spr_byp_ex4_is_mfxer, + + -- Resets + pc_xu_reset_wd_complete => pc_xu_reset_wd_complete, + pc_xu_reset_1_complete => pc_xu_reset_1_complete, + pc_xu_reset_2_complete => pc_xu_reset_2_complete, + pc_xu_reset_3_complete => pc_xu_reset_3_complete, + ac_tc_reset_1_request => ac_tc_reset_1_request, + ac_tc_reset_2_request => ac_tc_reset_2_request, + ac_tc_reset_3_request => ac_tc_reset_3_request, + ac_tc_reset_wd_request => ac_tc_reset_wd_request, + + -- Err Inject + pc_xu_inj_llbust_attempt => pc_xu_inj_llbust_attempt, + pc_xu_inj_llbust_failed => pc_xu_inj_llbust_failed, + pc_xu_inj_wdt_reset => pc_xu_inj_wdt_reset, + xu_pc_err_wdt_reset => xu_pc_err_wdt_reset, + + -- Parity + spr_cpl_ex3_sprg_ce => spr_cpl_ex3_sprg_ce, + spr_cpl_ex3_sprg_ue => spr_cpl_ex3_sprg_ue, + pc_xu_inj_sprg_ecc => pc_xu_inj_sprg_ecc, + xu_pc_err_sprg_ecc => xu_pc_err_sprg_ecc, + + -- Perf + spr_perf_tx_events => spr_perf_tx_events, + xu_lsu_mtspr_trace_en => xu_lsu_mtspr_trace_en, + + -- SPRs + spr_bit_act => spr_bit_act, + spr_cpl_iac1_en => spr_cpl_iac1_en, + spr_cpl_iac2_en => spr_cpl_iac2_en, + spr_cpl_iac3_en => spr_cpl_iac3_en, + spr_cpl_iac4_en => spr_cpl_iac4_en, + spr_dbcr1_iac12m => spr_dbcr1_iac12m, + spr_dbcr1_iac34m => spr_dbcr1_iac34m, + spr_epcr_duvd => spr_epcr_duvd, + lsu_xu_spr_xucr0_cslc_xuop => lsu_xu_spr_xucr0_cslc_xuop, + lsu_xu_spr_xucr0_cslc_binv => lsu_xu_spr_xucr0_cslc_binv, + lsu_xu_spr_xucr0_clo => lsu_xu_spr_xucr0_clo, + lsu_xu_spr_xucr0_cul => lsu_xu_spr_xucr0_cul, + lsu_xu_spr_epsc_epr => lsu_xu_spr_epsc_epr, + lsu_xu_spr_epsc_egs => lsu_xu_spr_epsc_egs, + spr_epcr_extgs => spr_epcr_extgs, + spr_msr_pr => spr_msr_pr_int, + spr_msr_is => spr_msr_is, + spr_msr_cm => spr_msr_cm_int, + spr_msr_gs => spr_msr_gs_int, + spr_msr_me => spr_msr_me, + xu_lsu_spr_xucr0_clfc => xu_lsu_spr_xucr0_clfc, + xu_pc_spr_ccr0_pme => xu_pc_spr_ccr0_pme, + spr_ccr2_en_dcr => spr_ccr2_en_dcr_int, + spr_ccr2_en_pc => spr_ccr2_en_pc, + xu_iu_spr_ccr2_ifratsc => xu_iu_spr_ccr2_ifratsc, + xu_iu_spr_ccr2_ifrat => xu_iu_spr_ccr2_ifrat, + xu_lsu_spr_ccr2_dfratsc => xu_lsu_spr_ccr2_dfratsc, + xu_lsu_spr_ccr2_dfrat => xu_lsu_spr_ccr2_dfrat, + spr_ccr2_ucode_dis => spr_ccr2_ucode_dis, + spr_ccr2_ap => spr_ccr2_ap_int, + spr_ccr2_en_attn => spr_ccr2_en_attn, + spr_ccr2_en_ditc => spr_ccr2_en_ditc_int, + spr_ccr2_en_icswx => spr_ccr2_en_icswx, + spr_ccr2_notlb => spr_ccr2_notlb_int, + xu_lsu_spr_xucr0_mbar_ack => xu_lsu_spr_xucr0_mbar_ack, + xu_lsu_spr_xucr0_tlbsync => xu_lsu_spr_xucr0_tlbsync, + spr_dec_spr_xucr0_ssdly => spr_dec_spr_xucr0_ssdly, + spr_xucr0_cls => xu_lsu_spr_xucr0_cls, + xu_lsu_spr_xucr0_aflsta => xu_lsu_spr_xucr0_aflsta, + spr_xucr0_mddp => spr_xucr0_mddp, + xu_lsu_spr_xucr0_cred => xu_lsu_spr_xucr0_cred, + xu_lsu_spr_xucr0_rel => xu_lsu_spr_xucr0_rel_int, + spr_xucr0_mdcp => spr_xucr0_mdcp, + xu_lsu_spr_xucr0_flsta => xu_lsu_spr_xucr0_flsta, + xu_lsu_spr_xucr0_l2siw => xu_lsu_spr_xucr0_l2siw, + xu_lsu_spr_xucr0_flh2l2 => xu_lsu_spr_xucr0_flh2l2, + xu_lsu_spr_xucr0_dcdis => xu_lsu_spr_xucr0_dcdis_int, + xu_lsu_spr_xucr0_wlk => xu_lsu_spr_xucr0_wlk, + cpl_spr_dbcr0_edm => cpl_spr_dbcr0_edm, + spr_dbcr0_idm => spr_dbcr0_idm, + spr_dbcr0_icmp => spr_dbcr0_icmp, + spr_dbcr0_brt => spr_dbcr0_brt, + spr_dbcr0_irpt => spr_dbcr0_irpt, + spr_dbcr0_trap => spr_dbcr0_trap, + spr_dbcr0_dac1 => spr_dbcr0_dac1, + spr_dbcr0_dac2 => spr_dbcr0_dac2, + spr_dbcr0_ret => spr_dbcr0_ret, + spr_dbcr0_dac3 => spr_dbcr0_dac3, + spr_dbcr0_dac4 => spr_dbcr0_dac4, + spr_epcr_dtlbgs => spr_epcr_dtlbgs, + spr_epcr_itlbgs => spr_epcr_itlbgs, + spr_epcr_dsigs => spr_epcr_dsigs, + spr_epcr_isigs => spr_epcr_isigs, + spr_epcr_dgtmi => spr_dec_rf1_epcr_dgtmi, + xu_mm_spr_epcr_dmiuh => xu_mm_spr_epcr_dmiuh, + spr_msr_ucle => spr_msr_ucle, + spr_msr_spv => spr_msr_spv_int, + spr_msr_fp => spr_msr_fp_int, + spr_msr_de => spr_msr_de, + spr_msr_ds => spr_msr_ds_int, + spr_msrp_uclep => spr_msrp_uclep, + spr_xucr0_clkg_ctl => spr_xucr0_clkg_ctl, + + -- ABIST + an_ac_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc, + pc_xu_abist_ena_dc => pc_xu_abist_ena_dc, + pc_xu_abist_g8t_wenb => pc_xu_abist_g8t_wenb, + pc_xu_abist_waddr_0 => pc_xu_abist_waddr_0(4 to 9), + pc_xu_abist_di_0 => pc_xu_abist_di_0, + pc_xu_abist_g8t1p_renb_0 => pc_xu_abist_g8t1p_renb_0, + pc_xu_abist_raddr_0 => pc_xu_abist_raddr_0(4 to 9), + pc_xu_abist_wl32_comp_ena => pc_xu_abist_wl32_comp_ena, + pc_xu_abist_raw_dc_b => pc_xu_abist_raw_dc_b, + pc_xu_abist_g8t_dcomp => pc_xu_abist_g8t_dcomp, + pc_xu_abist_g8t_bw_1 => pc_xu_abist_g8t_bw_1, + pc_xu_abist_g8t_bw_0 => pc_xu_abist_g8t_bw_0, + bolt_sl_thold_2 => bolt_sl_thold_2_b, + bo_enable_2 => bo_enable_2_b, + pc_xu_bo_unload => pc_xu_bo_unload, + pc_xu_bo_repair => pc_xu_bo_repair, + pc_xu_bo_reset => pc_xu_bo_reset, + pc_xu_bo_shdata => pc_xu_bo_shdata, + pc_xu_bo_select => pc_xu_bo_select(0), + xu_pc_bo_fail => xu_pc_bo_fail(0), + xu_pc_bo_diagout => xu_pc_bo_diagout(0), + + -- Debug + lsu_xu_cmd_debug => lsu_xu_cmd_debug, + pc_xu_trace_bus_enable => pc_xu_trace_bus_enable, + spr_debug_mux_ctrls => spr_debug_mux_ctrls, + spr_debug_data_in => spr_debug_data_in, + spr_debug_data_out => spr_debug_data_out, + spr_trigger_data_in => spr_trigger_data_in, + spr_trigger_data_out => spr_trigger_data_out, + + -- Power + vcs => vcs, + vdd => vdd, + gnd => gnd +); + +spr_msr_gs <= spr_msr_gs_int; +spr_msr_pr <= spr_msr_pr_int; +spr_msr_ds <= spr_msr_ds_int; +spr_msr_cm <= spr_msr_cm_int; +spr_msr_fp <= spr_msr_fp_int; +spr_msr_spv <= spr_msr_spv_int; +spr_ccr2_ap <= spr_ccr2_ap_int; +spr_ccr2_en_dcr <= spr_ccr2_en_dcr_int; +spr_ccr2_notlb <= spr_ccr2_notlb_int; +spr_ccr2_en_ditc <= spr_ccr2_en_ditc_int; +xu_lsu_spr_xucr0_dcdis <= xu_lsu_spr_xucr0_dcdis_int; +xu_lsu_spr_xucr0_rel <= xu_lsu_spr_xucr0_rel_int; +spr_xucr0_clkg_ctl_b0 <= spr_xucr0_clkg_ctl(0); + +end xuq_ctrl_spr; diff --git a/rel/src/vhdl/work/xuq_debug.vhdl b/rel/src/vhdl/work/xuq_debug.vhdl new file mode 100644 index 0000000..926567b --- /dev/null +++ b/rel/src/vhdl/work/xuq_debug.vhdl @@ -0,0 +1,240 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XU Debug Event Muxing +-- +library ieee,ibm,support,work,tri,clib; +use ieee.std_logic_1164.all; +use support.power_logic_pkg.all; +use tri.tri_latches_pkg.all; + +entity xuq_debug is +generic( + expand_type : integer := 2); +port( + -- Clocks + nclk : in clk_logic; + + -- Pervasive + d_mode_dc : in std_ulogic; + delay_lclkr_dc : in std_ulogic; + mpw1_dc_b : in std_ulogic; + mpw2_dc_b : in std_ulogic; + sg_0 : in std_ulogic; + func_slp_sl_thold_0_b : in std_ulogic; + func_slp_sl_force : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + dec_byp_ex3_instr_trace_val : in std_ulogic; + + pc_xu_trace_bus_enable : in std_ulogic; + debug_mux_ctrls : in std_ulogic_vector(0 to 15); + trigger_data_in : in std_ulogic_vector(0 to 11); + debug_data_in : in std_ulogic_vector(0 to 87); + trigger_data_out : out std_ulogic_vector(0 to 11); + debug_data_out : out std_ulogic_vector(0 to 87); + + dbg_group0 : in std_ulogic_vector(0 to 87) := (others=>'0'); + dbg_group1 : in std_ulogic_vector(0 to 87) := (others=>'0'); + dbg_group2 : in std_ulogic_vector(0 to 87) := (others=>'0'); + dbg_group3 : in std_ulogic_vector(0 to 87) := (others=>'0'); + dbg_group4 : in std_ulogic_vector(0 to 87) := (others=>'0'); + dbg_group5 : in std_ulogic_vector(0 to 87) := (others=>'0'); + dbg_group6 : in std_ulogic_vector(0 to 87) := (others=>'0'); + dbg_group7 : in std_ulogic_vector(0 to 87) := (others=>'0'); + dbg_group8 : in std_ulogic_vector(0 to 87) := (others=>'0'); + dbg_group9 : in std_ulogic_vector(0 to 87) := (others=>'0'); + dbg_group10 : in std_ulogic_vector(0 to 87) := (others=>'0'); + dbg_group11 : in std_ulogic_vector(0 to 87) := (others=>'0'); + dbg_group12 : in std_ulogic_vector(0 to 87) := (others=>'0'); + dbg_group13 : in std_ulogic_vector(0 to 87) := (others=>'0'); + dbg_group14 : in std_ulogic_vector(0 to 87) := (others=>'0'); + dbg_group15 : in std_ulogic_vector(0 to 87) := (others=>'0'); + + trg_group0 : in std_ulogic_vector(0 to 11) := (others=>'0'); + trg_group1 : in std_ulogic_vector(0 to 11) := (others=>'0'); + trg_group2 : in std_ulogic_vector(0 to 11) := (others=>'0'); + trg_group3 : in std_ulogic_vector(0 to 11) := (others=>'0'); + + -- Power + vdd : inout power_logic; + gnd : inout power_logic +); + +-- synopsys translate_off + +-- synopsys translate_on +end xuq_debug; +architecture xuq_debug of xuq_debug is + +signal tiup : std_ulogic; +-- Latches +signal trace_bus_enable_q : std_ulogic; -- input=>pc_xu_trace_bus_enable, sleep=>Y, needs_sreset=>0 +signal debug_mux_ctrls_q : std_ulogic_vector(0 to 15); -- input=>debug_mux_ctrls, act=>trace_bus_enable_q, sleep=>Y, needs_sreset=>0 +signal debug_mux_ctrls_int_q, debug_mux_ctrls_int : std_ulogic_vector(0 to 15); -- input=>debug_mux_ctrls_int, act=>trace_bus_enable_q, sleep=>Y, needs_sreset=>0 +signal trigger_data_out_q, trigger_data_out_d : std_ulogic_vector(0 to 11); -- act=>trace_bus_enable_q, sleep=>Y, needs_sreset=>0 +signal debug_data_out_q, debug_data_out_d : std_ulogic_vector(0 to 87); -- act=>trace_bus_enable_q, sleep=>Y, needs_sreset=>0 +signal ex4_instr_trace_val_q : std_ulogic; -- input=>dec_byp_ex3_instr_trace_val,act=>trace_bus_enable_q, sleep=>Y, needs_sreset=>0 +-- Scanrings +constant trace_bus_enable_offset : integer := 0; +constant debug_mux_ctrls_offset : integer := trace_bus_enable_offset + 1; +constant debug_mux_ctrls_int_offset : integer := debug_mux_ctrls_offset + debug_mux_ctrls_q'length; +constant trigger_data_out_offset : integer := debug_mux_ctrls_int_offset + debug_mux_ctrls_int_q'length; +constant debug_data_out_offset : integer := trigger_data_out_offset + trigger_data_out_q'length; +constant ex4_instr_trace_val_offset : integer := debug_data_out_offset + debug_data_out_q'length; +constant scan_right : integer := ex4_instr_trace_val_offset + 1; +signal siv : std_ulogic_vector(0 to scan_right-1); +signal sov : std_ulogic_vector(0 to scan_right-1); + +begin + +tiup <= '1'; +trigger_data_out <= trigger_data_out_q; +debug_data_out <= debug_data_out_q; + +with ex4_instr_trace_val_q select + debug_mux_ctrls_int <= x"11E0" when '1', + debug_mux_ctrls_q when others; + +xu_debug_mux : entity clib.c_debug_mux16(c_debug_mux16) +port map( + vd => vdd, + gd => gnd, + select_bits => debug_mux_ctrls_int_q, + trace_data_in => debug_data_in, + trigger_data_in => trigger_data_in, + dbg_group0 => dbg_group0, + dbg_group1 => dbg_group1, + dbg_group2 => dbg_group2, + dbg_group3 => dbg_group3, + dbg_group4 => dbg_group4, + dbg_group5 => dbg_group5, + dbg_group6 => dbg_group6, + dbg_group7 => dbg_group7, + dbg_group8 => dbg_group8, + dbg_group9 => dbg_group9, + dbg_group10 => dbg_group10, + dbg_group11 => dbg_group11, + dbg_group12 => dbg_group12, + dbg_group13 => dbg_group13, + dbg_group14 => dbg_group14, + dbg_group15 => dbg_group15, + trg_group0 => trg_group0, + trg_group1 => trg_group1, + trg_group2 => trg_group2, + trg_group3 => trg_group3, + trigger_data_out => trigger_data_out_d, + trace_data_out => debug_data_out_d); + +-- Latches +trace_bus_enable_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(trace_bus_enable_offset), + scout => sov(trace_bus_enable_offset), + din => pc_xu_trace_bus_enable, + dout => trace_bus_enable_q); +debug_mux_ctrls_latch : tri_rlmreg_p + generic map (width => debug_mux_ctrls_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(debug_mux_ctrls_offset to debug_mux_ctrls_offset + debug_mux_ctrls_q'length-1), + scout => sov(debug_mux_ctrls_offset to debug_mux_ctrls_offset + debug_mux_ctrls_q'length-1), + din => debug_mux_ctrls, + dout => debug_mux_ctrls_q); +debug_mux_ctrls_int_latch : tri_rlmreg_p + generic map (width => debug_mux_ctrls_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(debug_mux_ctrls_int_offset to debug_mux_ctrls_int_offset + debug_mux_ctrls_int_q'length-1), + scout => sov(debug_mux_ctrls_int_offset to debug_mux_ctrls_int_offset + debug_mux_ctrls_int_q'length-1), + din => debug_mux_ctrls_int, + dout => debug_mux_ctrls_int_q); +trigger_data_out_latch : tri_rlmreg_p + generic map (width => trigger_data_out_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(trigger_data_out_offset to trigger_data_out_offset + trigger_data_out_q'length-1), + scout => sov(trigger_data_out_offset to trigger_data_out_offset + trigger_data_out_q'length-1), + din => trigger_data_out_d, + dout => trigger_data_out_q); +debug_data_out_latch : tri_rlmreg_p + generic map (width => debug_data_out_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(debug_data_out_offset to debug_data_out_offset + debug_data_out_q'length-1), + scout => sov(debug_data_out_offset to debug_data_out_offset + debug_data_out_q'length-1), + din => debug_data_out_d, + dout => debug_data_out_q); +ex4_instr_trace_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_instr_trace_val_offset), + scout => sov(ex4_instr_trace_val_offset), + din => dec_byp_ex3_instr_trace_val, + dout => ex4_instr_trace_val_q); + +siv(0 to scan_right-1) <= sov(1 to scan_right-1) & scan_in; +scan_out <= sov(0); + + +end architecture xuq_debug; + diff --git a/rel/src/vhdl/work/xuq_debug_mux32.vhdl b/rel/src/vhdl/work/xuq_debug_mux32.vhdl new file mode 100644 index 0000000..0481ed0 --- /dev/null +++ b/rel/src/vhdl/work/xuq_debug_mux32.vhdl @@ -0,0 +1,370 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: LSU Debug Event Muxing +-- +library ieee,ibm,support,work,tri,work; +use ieee.std_logic_1164.all; +use support.power_logic_pkg.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; +use tri.tri_latches_pkg.all; +use work.xuq_pkg.all; + +entity xuq_debug_mux32 is +generic(expand_type :integer := 2); +port( + + -- PC Debug Control + trace_bus_enable :in std_ulogic; + trace_unit_sel :in std_ulogic_vector(0 to 15); + + -- Pass Thru Debug Trace Bus + debug_data_in :in std_ulogic_vector(0 to 87); + trigger_data_in :in std_ulogic_vector(0 to 11); + + -- Debug Data In + dbg_group0 :in std_ulogic_vector(0 to 87); + dbg_group1 :in std_ulogic_vector(0 to 87); + dbg_group2 :in std_ulogic_vector(0 to 87); + dbg_group3 :in std_ulogic_vector(0 to 87); + dbg_group4 :in std_ulogic_vector(0 to 87); + dbg_group5 :in std_ulogic_vector(0 to 87); + dbg_group6 :in std_ulogic_vector(0 to 87); + dbg_group7 :in std_ulogic_vector(0 to 87); + dbg_group8 :in std_ulogic_vector(0 to 87); + dbg_group9 :in std_ulogic_vector(0 to 87); + dbg_group10 :in std_ulogic_vector(0 to 87); + dbg_group11 :in std_ulogic_vector(0 to 87); + dbg_group12 :in std_ulogic_vector(0 to 87); + dbg_group13 :in std_ulogic_vector(0 to 87); + dbg_group14 :in std_ulogic_vector(0 to 87); + dbg_group15 :in std_ulogic_vector(0 to 87); + dbg_group16 :in std_ulogic_vector(0 to 87); + dbg_group17 :in std_ulogic_vector(0 to 87); + dbg_group18 :in std_ulogic_vector(0 to 87); + dbg_group19 :in std_ulogic_vector(0 to 87); + dbg_group20 :in std_ulogic_vector(0 to 87); + dbg_group21 :in std_ulogic_vector(0 to 87); + dbg_group22 :in std_ulogic_vector(0 to 87); + dbg_group23 :in std_ulogic_vector(0 to 87); + dbg_group24 :in std_ulogic_vector(0 to 87); + dbg_group25 :in std_ulogic_vector(0 to 87); + dbg_group26 :in std_ulogic_vector(0 to 87); + dbg_group27 :in std_ulogic_vector(0 to 87); + dbg_group28 :in std_ulogic_vector(0 to 87); + dbg_group29 :in std_ulogic_vector(0 to 87); + dbg_group30 :in std_ulogic_vector(0 to 87); + dbg_group31 :in std_ulogic_vector(0 to 87); + + -- Trigger Data In + trg_group0 :in std_ulogic_vector(0 to 11); + trg_group1 :in std_ulogic_vector(0 to 11); + trg_group2 :in std_ulogic_vector(0 to 11); + trg_group3 :in std_ulogic_vector(0 to 11); + + -- Outputs + trigger_data_out :out std_ulogic_vector(0 to 11); + debug_data_out :out std_ulogic_vector(0 to 87); + + -- Power + vdd :inout power_logic; + gnd :inout power_logic; + nclk :in clk_logic; + sg_0 :in std_ulogic; + func_slp_sl_thold_0_b :in std_ulogic; + func_slp_sl_force :in std_ulogic; + d_mode_dc :in std_ulogic; + delay_lclkr_dc :in std_ulogic; + mpw1_dc_b :in std_ulogic; + mpw2_dc_b :in std_ulogic; + scan_in :in std_ulogic; + scan_out :out std_ulogic +); + +-- synopsys translate_off + +-- synopsys translate_on +end xuq_debug_mux32; +architecture xuq_debug_mux32 of xuq_debug_mux32 is + +type ARY_32 is array (0 to 31) of std_ulogic_vector(0 to 3); + +signal dbg_group_int_data :std_ulogic_vector(0 to 87); +signal dbg_group_rotate0 :std_ulogic_vector(0 to 87); +signal dbg_group_rotate1 :std_ulogic_vector(0 to 87); +signal dbg_group_rotate2 :std_ulogic_vector(0 to 87); +signal dbg_group_rotate3 :std_ulogic_vector(0 to 87); +signal dbg_group_rotate :std_ulogic_vector(0 to 87); +signal dbg_group_pthru_data0 :std_ulogic_vector(0 to 21); +signal dbg_group_pthru_data1 :std_ulogic_vector(0 to 21); +signal dbg_group_pthru_data2 :std_ulogic_vector(0 to 21); +signal dbg_group_pthru_data3 :std_ulogic_vector(0 to 21); +signal dbg_group_pthru_data :std_ulogic_vector(0 to 87); +signal debug_data_out_d :std_ulogic_vector(0 to 87); +signal debug_data_out_q :std_ulogic_vector(0 to 87); +signal dbg_group_int_trig :std_ulogic_vector(0 to 11); +signal dbg_group_rot_trig0 :std_ulogic_vector(0 to 11); +signal dbg_group_rot_trig1 :std_ulogic_vector(0 to 11); +signal dbg_group_rot_trig :std_ulogic_vector(0 to 11); +signal dbg_group_pthru_trig0 :std_ulogic_vector(0 to 5); +signal dbg_group_pthru_trig1 :std_ulogic_vector(0 to 5); +signal dbg_group_pthru_trig :std_ulogic_vector(0 to 11); +signal trigger_data_out_d :std_ulogic_vector(0 to 11); +signal trigger_data_out_q :std_ulogic_vector(0 to 11); +signal trace_unit_sel10 :std_ulogic_vector(0 to 31); +signal trace_unit_selC840 :std_ulogic_vector(0 to 31); +signal trace_unit_sel3210 :std_ulogic_vector(0 to 31); +signal dbg_data_unit_sel_d :ARY_32; +signal dbg_data_unit_sel_q :ARY_32; +signal dbg_trace_unit_sel_d :std_ulogic_vector(32 to 46); +signal dbg_trace_unit_sel_q :std_ulogic_vector(32 to 46); +signal dbg_rot_grp_sel :std_ulogic_vector(0 to 3); +signal dbg_data_pthru_sel :std_ulogic_vector(0 to 3); +signal dbg_trig_grp_sel :std_ulogic_vector(0 to 3); +signal dbg_rot_trig_sel :std_ulogic; +signal dbg_trig_pthru_sel :std_ulogic_vector(0 to 1); + +constant dbg_data_unit_sel_offset :natural := 0; +constant dbg_trace_unit_sel_offset :natural := dbg_data_unit_sel_offset + dbg_data_unit_sel_q(0)'length*32; +constant trigger_data_out_offset :natural := dbg_trace_unit_sel_offset + 15; +constant debug_data_out_offset :natural := trigger_data_out_offset + 12; +constant scan_right :natural := debug_data_out_offset + 88 - 1; +signal siv :std_ulogic_vector(0 to scan_right); +signal sov :std_ulogic_vector(0 to scan_right); + +begin + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- MUX Control Generation +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +-- Generate 1-hot Debug Data Group Select +with trace_unit_sel(0) select + trace_unit_sel10 <= x"80000000" when '0', + x"00008000" when others; + +with trace_unit_sel(1 to 2) select + trace_unit_selC840 <= trace_unit_sel10(0 to 31) when "00", + x"0" & trace_unit_sel10(0 to 27) when "01", + x"00" & trace_unit_sel10(0 to 23) when "10", + x"000" & trace_unit_sel10(0 to 19) when others; + +with trace_unit_sel(3 to 4) select + trace_unit_sel3210 <= trace_unit_selC840(0 to 31) when "00", + '0' & trace_unit_selC840(0 to 30) when "01", + "00" & trace_unit_selC840(0 to 29) when "10", + "000" & trace_unit_selC840(0 to 28) when others; + +-- Generate 1-hot Debug Data Group Rotate +with trace_unit_sel(5 to 6) select + dbg_trace_unit_sel_d(32 to 35) <= "1000" when "00", + "0100" when "01", + "0010" when "10", + "0001" when others; + +-- Debug Data Pass Through +dbg_trace_unit_sel_d(36 to 39) <= trace_unit_sel(7 to 10); + +-- Generate 1-hot Trigger Group Select +with trace_unit_sel(11 to 12) select + dbg_trace_unit_sel_d(40 to 43) <= "1000" when "00", + "0100" when "01", + "0010" when "10", + "0001" when others; + +-- Generate 1-hot Trigger Group Rotate +dbg_trace_unit_sel_d(44) <= trace_unit_sel(13); + +-- Trigger Pass Through +dbg_trace_unit_sel_d(45 to 46) <= trace_unit_sel(14 to 15); + +dbg_rot_grp_sel <= dbg_trace_unit_sel_q(32 to 35); +dbg_data_pthru_sel <= dbg_trace_unit_sel_q(36 to 39); +dbg_trig_grp_sel <= dbg_trace_unit_sel_q(40 to 43); +dbg_rot_trig_sel <= dbg_trace_unit_sel_q(44); +dbg_trig_pthru_sel <= dbg_trace_unit_sel_q(45 to 46); + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Debug Muxing +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +-- Select Internal Debug Group +dbg_group_int_data <= (dbg_group0 and fanout(dbg_data_unit_sel_q(00),88)) or + (dbg_group1 and fanout(dbg_data_unit_sel_q(01),88)) or + (dbg_group2 and fanout(dbg_data_unit_sel_q(02),88)) or + (dbg_group3 and fanout(dbg_data_unit_sel_q(03),88)) or + (dbg_group4 and fanout(dbg_data_unit_sel_q(04),88)) or + (dbg_group5 and fanout(dbg_data_unit_sel_q(05),88)) or + (dbg_group6 and fanout(dbg_data_unit_sel_q(06),88)) or + (dbg_group7 and fanout(dbg_data_unit_sel_q(07),88)) or + (dbg_group8 and fanout(dbg_data_unit_sel_q(08),88)) or + (dbg_group9 and fanout(dbg_data_unit_sel_q(09),88)) or + (dbg_group10 and fanout(dbg_data_unit_sel_q(10),88)) or + (dbg_group11 and fanout(dbg_data_unit_sel_q(11),88)) or + (dbg_group12 and fanout(dbg_data_unit_sel_q(12),88)) or + (dbg_group13 and fanout(dbg_data_unit_sel_q(13),88)) or + (dbg_group14 and fanout(dbg_data_unit_sel_q(14),88)) or + (dbg_group15 and fanout(dbg_data_unit_sel_q(15),88)) or + (dbg_group16 and fanout(dbg_data_unit_sel_q(16),88)) or + (dbg_group17 and fanout(dbg_data_unit_sel_q(17),88)) or + (dbg_group18 and fanout(dbg_data_unit_sel_q(18),88)) or + (dbg_group19 and fanout(dbg_data_unit_sel_q(19),88)) or + (dbg_group20 and fanout(dbg_data_unit_sel_q(20),88)) or + (dbg_group21 and fanout(dbg_data_unit_sel_q(21),88)) or + (dbg_group22 and fanout(dbg_data_unit_sel_q(22),88)) or + (dbg_group23 and fanout(dbg_data_unit_sel_q(23),88)) or + (dbg_group24 and fanout(dbg_data_unit_sel_q(24),88)) or + (dbg_group25 and fanout(dbg_data_unit_sel_q(25),88)) or + (dbg_group26 and fanout(dbg_data_unit_sel_q(26),88)) or + (dbg_group27 and fanout(dbg_data_unit_sel_q(27),88)) or + (dbg_group28 and fanout(dbg_data_unit_sel_q(28),88)) or + (dbg_group29 and fanout(dbg_data_unit_sel_q(29),88)) or + (dbg_group30 and fanout(dbg_data_unit_sel_q(30),88)) or + (dbg_group31 and fanout(dbg_data_unit_sel_q(31),88)); + +-- Rotate Internal Debug Group +dbg_group_rotate0 <= dbg_group_int_data(0 to 87); +dbg_group_rotate1 <= dbg_group_int_data(66 to 87) & dbg_group_int_data(0 to 65); +dbg_group_rotate2 <= dbg_group_int_data(44 to 87) & dbg_group_int_data(0 to 43); +dbg_group_rotate3 <= dbg_group_int_data(22 to 87) & dbg_group_int_data(0 to 21); +dbg_group_rotate <= gate(dbg_group_rotate0, dbg_rot_grp_sel(0)) or gate(dbg_group_rotate1, dbg_rot_grp_sel(1)) or + gate(dbg_group_rotate2, dbg_rot_grp_sel(2)) or gate(dbg_group_rotate3, dbg_rot_grp_sel(3)); + +-- Pass Thru Debug Select +dbg_group_pthru_data0 <= gate(dbg_group_rotate(0 to 21), dbg_data_pthru_sel(0)) or gate(debug_data_in(0 to 21), not dbg_data_pthru_sel(0)); +dbg_group_pthru_data1 <= gate(dbg_group_rotate(22 to 43), dbg_data_pthru_sel(1)) or gate(debug_data_in(22 to 43), not dbg_data_pthru_sel(1)); +dbg_group_pthru_data2 <= gate(dbg_group_rotate(44 to 65), dbg_data_pthru_sel(2)) or gate(debug_data_in(44 to 65), not dbg_data_pthru_sel(2)); +dbg_group_pthru_data3 <= gate(dbg_group_rotate(66 to 87), dbg_data_pthru_sel(3)) or gate(debug_data_in(66 to 87), not dbg_data_pthru_sel(3)); +dbg_group_pthru_data <= dbg_group_pthru_data0 & dbg_group_pthru_data1 & dbg_group_pthru_data2 & dbg_group_pthru_data3; + +debug_data_out_d <= dbg_group_pthru_data; + +-- Select Internal Trigger Group +dbg_group_int_trig <= gate(trg_group0, dbg_trig_grp_sel(0)) or gate(trg_group1, dbg_trig_grp_sel(1)) or gate(trg_group2, dbg_trig_grp_sel(2)) or gate(trg_group3, dbg_trig_grp_sel(3)); + +-- Rotate Internal Trigger Group +dbg_group_rot_trig0 <= dbg_group_int_trig(0 to 11); +dbg_group_rot_trig1 <= dbg_group_int_trig(6 to 11) & dbg_group_int_trig(0 to 5); +dbg_group_rot_trig <= gate(dbg_group_rot_trig0, not dbg_rot_trig_sel) or gate(dbg_group_rot_trig1, dbg_rot_trig_sel); + +-- Pass Thru Trigger Select +dbg_group_pthru_trig0 <= gate(dbg_group_rot_trig(0 to 5), dbg_trig_pthru_sel(0)) or gate(trigger_data_in(0 to 5), not dbg_trig_pthru_sel(0)); +dbg_group_pthru_trig1 <= gate(dbg_group_rot_trig(6 to 11), dbg_trig_pthru_sel(1)) or gate(trigger_data_in(6 to 11), not dbg_trig_pthru_sel(1)); +dbg_group_pthru_trig <= dbg_group_pthru_trig0 & dbg_group_pthru_trig1; + +trigger_data_out_d <= dbg_group_pthru_trig; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Outputs +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +debug_data_out <= debug_data_out_q; +trigger_data_out <= trigger_data_out_q; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Latches +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +dbg_data_unit_sel_gen : for g in 0 to 31 generate + dbg_data_unit_sel_latch : tri_rlmreg_p + generic map (width => dbg_data_unit_sel_q(g)'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => trace_bus_enable, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(dbg_data_unit_sel_offset+dbg_data_unit_sel_q(g)'length*g to dbg_data_unit_sel_offset + dbg_data_unit_sel_q(g)'length*(g+1)-1), + scout => sov(dbg_data_unit_sel_offset+dbg_data_unit_sel_q(g)'length*g to dbg_data_unit_sel_offset + dbg_data_unit_sel_q(g)'length*(g+1)-1), + din => dbg_data_unit_sel_d(g), + dout => dbg_data_unit_sel_q(g)); + + dbg_data_unit_sel_d(g) <= (others=>trace_unit_sel3210(g)); + +end generate; +dbg_trace_unit_sel_latch : tri_rlmreg_p +generic map (width => dbg_trace_unit_sel_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => trace_bus_enable, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(dbg_trace_unit_sel_offset to dbg_trace_unit_sel_offset + dbg_trace_unit_sel_q'length-1), + scout => sov(dbg_trace_unit_sel_offset to dbg_trace_unit_sel_offset + dbg_trace_unit_sel_q'length-1), + din => dbg_trace_unit_sel_d, + dout => dbg_trace_unit_sel_q); +trigger_data_out_latch : tri_rlmreg_p +generic map (width => trigger_data_out_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => trace_bus_enable, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(trigger_data_out_offset to trigger_data_out_offset + trigger_data_out_q'length-1), + scout => sov(trigger_data_out_offset to trigger_data_out_offset + trigger_data_out_q'length-1), + din => trigger_data_out_d, + dout => trigger_data_out_q); +debug_data_out_latch : tri_rlmreg_p +generic map (width => debug_data_out_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => trace_bus_enable, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(debug_data_out_offset to debug_data_out_offset + debug_data_out_q'length-1), + scout => sov(debug_data_out_offset to debug_data_out_offset + debug_data_out_q'length-1), + din => debug_data_out_d, + dout => debug_data_out_q); + +siv(0 to scan_right) <= sov(1 to scan_right) & scan_in; +scan_out <= sov(0); + +end architecture xuq_debug_mux32; diff --git a/rel/src/vhdl/work/xuq_dec_a.vhdl b/rel/src/vhdl/work/xuq_dec_a.vhdl new file mode 100644 index 0000000..dd2342a --- /dev/null +++ b/rel/src/vhdl/work/xuq_dec_a.vhdl @@ -0,0 +1,2754 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XU_A Decode +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.numeric_std.all; +LIBRARY ibm; +USE ibm.std_ulogic_support.all; +USE ibm.std_ulogic_function_support.all; +LIBRARY support; +USE support.power_logic_pkg.all; +LIBRARY tri; +USE tri.tri_latches_pkg.all; +LIBRARY work; +USE work.xuq_pkg.all; + +entity xuq_dec_a is + generic( + expand_type : integer := 2; + threads : integer := 4; + regmode : integer := 6; + regsize : integer := 63; + real_data_add : integer := 42; + eff_ifar : integer := 62); + port( + nclk : in clk_logic; + + vdd : inout power_logic; + gnd : inout power_logic; + + d_mode_dc : in std_ulogic; + delay_lclkr_dc : in std_ulogic; + mpw1_dc_b : in std_ulogic; + mpw2_dc_b : in std_ulogic; + func_sl_force : in std_ulogic; + func_sl_thold_0_b : in std_ulogic; + sg_0 : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + iu_xu_is2_vld : in std_ulogic; + iu_xu_is2_ifar : in std_ulogic_vector(62-eff_ifar to 61); + iu_xu_is2_tid : in std_ulogic_vector(0 to threads-1); + iu_xu_is2_instr : in std_ulogic_vector(0 to 31); + iu_xu_is2_ta_vld : in std_ulogic; + iu_xu_is2_ta : in std_ulogic_vector(0 to 5); + iu_xu_is2_s1_vld : in std_ulogic; + iu_xu_is2_s1 : in std_ulogic_vector(0 to 5); + iu_xu_is2_s2_vld : in std_ulogic; + iu_xu_is2_s2 : in std_ulogic_vector(0 to 5); + iu_xu_is2_s3_vld : in std_ulogic; + iu_xu_is2_s3 : in std_ulogic_vector(0 to 5); + iu_xu_is2_axu_ld_or_st : in std_ulogic; + iu_xu_is2_axu_store : in std_ulogic; + iu_xu_is2_axu_ldst_size : in std_ulogic_vector(0 to 5); + iu_xu_is2_axu_ldst_update : in std_ulogic; + iu_xu_is2_axu_ldst_forcealign : in std_ulogic; + iu_xu_is2_axu_ldst_forceexcept : in std_ulogic; + iu_xu_is2_axu_ldst_extpid : in std_ulogic; + iu_xu_is2_axu_ldst_indexed : in std_ulogic; + iu_xu_is2_axu_ldst_tag : in std_ulogic_vector(0 to 8); + iu_xu_is2_axu_mftgpr : in std_ulogic; + iu_xu_is2_axu_mffgpr : in std_ulogic; + iu_xu_is2_axu_movedp : in std_ulogic; + iu_xu_is2_axu_instr_type : in std_ulogic_vector(0 to 2); + iu_xu_is2_pred_update : in std_ulogic; + iu_xu_is2_pred_taken_cnt : in std_ulogic_vector(0 to 1); + iu_xu_is2_error : in std_ulogic_vector(0 to 2); + iu_xu_is2_match : in std_ulogic; + iu_xu_is2_is_ucode : in std_ulogic; + iu_xu_is2_ucode_vld : in std_ulogic; + iu_xu_is2_gshare : in std_ulogic_vector(0 to 3); + xu_div_barr_done : out std_ulogic_vector(0 to threads-1); + xu_div_coll_barr_done : out std_ulogic_vector(0 to threads-1); + + dec_gpr_rf0_re0 : out std_ulogic; + dec_gpr_rf0_re1 : out std_ulogic; + dec_gpr_rf0_re2 : out std_ulogic; + dec_gpr_rf0_ra0 : out std_ulogic_vector(0 to 7); + dec_gpr_rf0_ra1 : out std_ulogic_vector(0 to 7); + dec_gpr_rf0_ra2 : out std_ulogic_vector(0 to 7); + dec_gpr_rel_ta_gpr : out std_ulogic_vector(0 to 7); + dec_gpr_rel_wren : out std_ulogic; + + fxa_fxb_rf0_val : out std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_issued : out std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_ucode_val : out std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_act : out std_ulogic; + fxa_fxb_ex1_hold_ctr_flush : out std_ulogic; + fxa_fxb_rf0_instr : out std_ulogic_vector(0 to 31); + fxa_fxb_rf0_tid : out std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_ta_vld : out std_ulogic; + fxa_fxb_rf0_ta : out std_ulogic_vector(0 to 7); + fxa_fxb_rf0_error : out std_ulogic_vector(0 to 2); + fxa_fxb_rf0_match : out std_ulogic; + fxa_fxb_rf0_is_ucode : out std_ulogic; + fxa_fxb_rf0_gshare : out std_ulogic_vector(0 to 3); + fxa_fxb_rf0_ifar : out std_ulogic_vector(62-eff_ifar to 61); + fxa_fxb_rf0_s1_vld : out std_ulogic; + fxa_fxb_rf0_s1 : out std_ulogic_vector(0 to 7); + fxa_fxb_rf0_s2_vld : out std_ulogic; + fxa_fxb_rf0_s2 : out std_ulogic_vector(0 to 7); + fxa_fxb_rf0_s3_vld : out std_ulogic; + fxa_fxb_rf0_s3 : out std_ulogic_vector(0 to 7); + fxa_fxb_rf0_axu_instr_type : out std_ulogic_vector(0 to 2); + fxa_fxb_rf0_axu_ld_or_st : out std_ulogic; + fxa_fxb_rf0_axu_store : out std_ulogic; + fxa_fxb_rf0_axu_ldst_forcealign : out std_ulogic; + fxa_fxb_rf0_axu_ldst_forceexcept : out std_ulogic; + fxa_fxb_rf0_axu_ldst_indexed : out std_ulogic; + fxa_fxb_rf0_axu_ldst_tag : out std_ulogic_vector(0 to 8); + fxa_fxb_rf0_axu_mftgpr : out std_ulogic; + fxa_fxb_rf0_axu_mffgpr : out std_ulogic; + fxa_fxb_rf0_axu_movedp : out std_ulogic; + fxa_fxb_rf0_axu_ldst_size : out std_ulogic_vector(0 to 5); + fxa_fxb_rf0_axu_ldst_update : out std_ulogic; + fxa_fxb_rf0_pred_update : out std_ulogic; + fxa_fxb_rf0_pred_taken_cnt : out std_ulogic_vector(0 to 1); + fxa_fxb_rf0_mc_dep_chk_val : out std_ulogic_vector(0 to threads-1); + fxa_fxb_rf1_mul_val : out std_ulogic; + fxa_fxb_rf1_muldiv_coll : out std_ulogic; + fxa_fxb_rf1_div_val : out std_ulogic; + fxa_fxb_rf1_div_ctr : out std_ulogic_vector(0 to 7); + fxa_fxb_rf0_xu_epid_instr : out std_ulogic; + fxa_fxb_rf0_axu_is_extload : out std_ulogic; + fxa_fxb_rf0_axu_is_extstore : out std_ulogic; + fxa_fxb_rf0_spr_tid : out std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_cpl_tid : out std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_cpl_act : out std_ulogic; + fxa_fxb_rf0_is_mfocrf : out std_ulogic; + fxa_fxb_rf0_3src_instr : out std_ulogic; + fxa_fxb_rf0_gpr0_zero : out std_ulogic; + fxa_fxb_rf0_use_imm : out std_ulogic; + dec_cpl_ex3_mc_dep_chk_val : out std_ulogic_vector(0 to threads-1); + fxa_cpl_ex2_div_coll : out std_ulogic_vector(0 to threads-1); + cpl_fxa_ex5_set_barr : in std_ulogic_vector(0 to threads-1); + fxa_iu_set_barr_tid : out std_ulogic_vector(0 to threads-1); + spr_xucr4_div_barr_thres : in std_ulogic_vector(0 to 7); + fxa_perf_muldiv_in_use : out std_ulogic; + + xu_is2_flush : in std_ulogic_vector(0 to threads-1); + xu_rf0_flush : in std_ulogic_vector(0 to threads-1); + xu_rf1_flush : in std_ulogic_vector(0 to threads-1); + xu_ex1_flush : in std_ulogic_vector(0 to threads-1); + xu_ex2_flush : in std_ulogic_vector(0 to threads-1); + xu_ex3_flush : in std_ulogic_vector(0 to threads-1); + xu_ex4_flush : in std_ulogic_vector(0 to threads-1); + xu_ex5_flush : in std_ulogic_vector(0 to threads-1); + + an_ac_back_inv : in std_ulogic; + an_ac_back_inv_addr : in std_ulogic_vector(62 to 63); + an_ac_back_inv_target_bit3 : in std_ulogic; + + dec_spr_rf0_instr : out std_ulogic_vector(0 to 31); + spr_xucr0_clkg_ctl_b0 : in std_ulogic; + + xu_lsu_rf0_derat_is_extload : out std_ulogic; + xu_lsu_rf0_derat_is_extstore : out std_ulogic; + xu_lsu_rf0_derat_val : out std_ulogic_vector(0 to threads-1); + lsu_xu_rel_wren : in std_ulogic; + lsu_xu_rel_ta_gpr : in std_ulogic_vector(0 to 7); + + dec_debug : out std_ulogic_vector(0 to 175) + ); +end xuq_dec_a; +ARCHITECTURE XUQ_DEC_A + OF XUQ_DEC_A + IS +--@@ Signal Declarations +SIGNAL TBL_3SRC_DEC_PT : STD_ULOGIC_VECTOR(1 TO 15) := +(OTHERS=> 'U'); +SIGNAL TBL_GPR0_ZERO_PT : STD_ULOGIC_VECTOR(1 TO 33) := +(OTHERS=> 'U'); +SIGNAL TBL_RF0_DEC_PT : STD_ULOGIC_VECTOR(1 TO 11) := +(OTHERS=> 'U'); +SIGNAL TBL_RF0_EPID_DEC_PT : STD_ULOGIC_VECTOR(1 TO 9) := +(OTHERS=> 'U'); +SIGNAL TBL_USE_IMM_PT : STD_ULOGIC_VECTOR(1 TO 15) := +(OTHERS=> 'U'); +subtype s2 is std_ulogic_vector(0 to 1); +subtype s3 is std_ulogic_vector(0 to 2); +constant tiup : std_ulogic := '1'; +constant tidn : std_ulogic := '0'; +signal rf0_axu_instr_type_q : std_ulogic_vector(0 to 2); +signal rf0_axu_ld_or_st_q : std_ulogic; +signal rf0_axu_ldst_extpid_q : std_ulogic; +signal rf0_axu_ldst_forcealign_q : std_ulogic; +signal rf0_axu_ldst_forceexcept_q : std_ulogic; +signal rf0_axu_ldst_indexed_q : std_ulogic; +signal rf0_axu_ldst_size_q : std_ulogic_vector(0 to 5); +signal rf0_axu_ldst_tag_q : std_ulogic_vector(0 to 8); +signal rf0_axu_ldst_update_q : std_ulogic; +signal rf0_axu_mffgpr_q : std_ulogic; +signal rf0_axu_mftgpr_q : std_ulogic; +signal rf0_axu_movedp_q : std_ulogic; +signal rf0_axu_store_q : std_ulogic; +signal rf0_error_q : std_ulogic_vector(0 to 2); +signal rf0_gshare_q : std_ulogic_vector(0 to 3); +signal rf0_ifar_q : std_ulogic_vector(62-eff_ifar to 61); +signal rf0_instr_q : std_ulogic_vector(0 to 31); +signal rf0_is_ucode_q : std_ulogic; +signal rf0_match_q : std_ulogic; +signal rf0_pred_taken_cnt_q : std_ulogic_vector(0 to 1); +signal rf0_pred_update_q : std_ulogic; +signal rf0_s1_q : std_ulogic_vector(0 to 5); +signal rf0_s1_vld_q, rf0_s1_vld_d : std_ulogic; +signal rf0_s2_q : std_ulogic_vector(0 to 5); +signal rf0_s2_vld_q, rf0_s2_vld_d : std_ulogic; +signal rf0_s3_q : std_ulogic_vector(0 to 5); +signal rf0_s3_vld_q, rf0_s3_vld_d : std_ulogic; +signal rf0_ta_q : std_ulogic_vector(0 to 5); +signal rf0_ta_vld_q, rf0_ta_vld_d : std_ulogic; +signal rf0_tid_q : std_ulogic_vector(0 to threads-1); +signal rf0_ucode_val_q, rf0_ucode_val_d : std_ulogic_vector(0 to threads-1); +signal rf0_val_q, rf0_val_d : std_ulogic_vector(0 to threads-1); +signal rf1_barrier_done_q, rf0_barrier_done : std_ulogic; +signal rf1_div_coll_q, rf1_div_coll_d : std_ulogic; +signal rf1_div_val_q, rf0_div_val : std_ulogic_vector(0 to threads-1); +signal rf1_mul_valid_q, rf0_mul_valid : std_ulogic; +signal rf1_muldiv_coll_q, rf0_muldiv_coll : std_ulogic; +signal rf1_multdiv_val_q, rf0_multdiv_val : std_ulogic_vector(0 to threads-1); +signal rf1_recirc_ctr_q, rf1_recirc_ctr_d : std_ulogic_vector(0 to 7); +signal rf1_recirc_ctr_flush_q, rf0_recirc_ctr_flush : std_ulogic; +signal ex1_div_coll_q, ex1_div_coll_d : std_ulogic; +signal ex1_div_val_q, ex1_div_val_d : std_ulogic_vector(0 to threads-1); +signal ex1_muldiv_in_use_q : std_ulogic; +signal ex1_multdiv_val_q, ex1_multdiv_val_d : std_ulogic_vector(0 to threads-1); +signal ex1_recirc_ctr_flush_q : std_ulogic; +signal ex2_div_coll_q, ex2_div_coll_d : std_ulogic; +signal ex2_div_val_q, ex2_div_val_d : std_ulogic_vector(0 to threads-1); +signal ex2_multdiv_val_q, ex2_multdiv_val_d : std_ulogic_vector(0 to threads-1); +signal ex3_div_val_q, ex3_div_val_d : std_ulogic_vector(0 to threads-1); +signal ex3_multdiv_val_q, ex3_multdiv_val_d : std_ulogic_vector(0 to threads-1); +signal ex4_div_val_q, ex4_div_val_d : std_ulogic_vector(0 to threads-1); +signal ex5_div_val_q, ex5_div_val_d : std_ulogic_vector(0 to threads-1); +signal ex6_div_barr_val_q : std_ulogic; +signal ex6_set_barr_q, ex5_set_barr : std_ulogic_vector(0 to threads-1); +signal an_ac_back_inv_q : std_ulogic; +signal an_ac_back_inv_addr_q : std_ulogic_vector(62 to 63); +signal an_ac_back_inv_target_bit3_q : std_ulogic; +signal back_inv_val_q, back_inv_val_d : std_ulogic; +signal coll_tid_q, coll_tid_d : std_ulogic_vector(0 to threads-1); +signal div_barr_done_q, div_barr_done_d : std_ulogic_vector(0 to threads-1); +signal div_barr_thres_q : std_ulogic_vector(0 to 7); +signal div_coll_barr_done_q, div_coll_barr_done_d : std_ulogic_vector(0 to threads-1); +signal hold_divide_q : std_ulogic; +signal hold_error_q, hold_error_d : std_ulogic_vector(0 to 2); +signal hold_ifar_q, hold_ifar_d : std_ulogic_vector(62-eff_ifar to 61); +signal hold_instr_q, hold_instr_d : std_ulogic_vector(0 to 31); +signal hold_is_ucode_q, hold_is_ucode_d : std_ulogic; +signal hold_match_q, hold_match_d : std_ulogic; +signal hold_s1_q, hold_s1_d : std_ulogic_vector(0 to 7); +signal hold_s1_vld_q, hold_s1_vld_d : std_ulogic; +signal hold_s2_q, hold_s2_d : std_ulogic_vector(0 to 7); +signal hold_s2_vld_q, hold_s2_vld_d : std_ulogic; +signal hold_s3_q, hold_s3_d : std_ulogic_vector(0 to 7); +signal hold_s3_vld_q, hold_s3_vld_d : std_ulogic; +signal hold_ta_q, hold_ta_d : std_ulogic_vector(0 to 7); +signal hold_ta_vld_q, hold_ta_vld_d : std_ulogic; +signal hold_tid_q, hold_tid_d : std_ulogic_vector(0 to threads-1); +signal hold_use_imm_q, hold_use_imm_d : std_ulogic; +signal lsu_xu_rel_ta_gpr_q : std_ulogic_vector(0 to 7); +signal lsu_xu_rel_wren_q : std_ulogic; +signal spare_0_q, spare_0_d : std_ulogic_vector(0 to 15); +signal spare_1_q, spare_1_d : std_ulogic_vector(0 to 15); +constant rf0_axu_instr_type_offset : integer := 0; +constant rf0_axu_ld_or_st_offset : integer := rf0_axu_instr_type_offset + rf0_axu_instr_type_q'length; +constant rf0_axu_ldst_extpid_offset : integer := rf0_axu_ld_or_st_offset + 1; +constant rf0_axu_ldst_forcealign_offset : integer := rf0_axu_ldst_extpid_offset + 1; +constant rf0_axu_ldst_forceexcept_offset : integer := rf0_axu_ldst_forcealign_offset + 1; +constant rf0_axu_ldst_indexed_offset : integer := rf0_axu_ldst_forceexcept_offset + 1; +constant rf0_axu_ldst_size_offset : integer := rf0_axu_ldst_indexed_offset + 1; +constant rf0_axu_ldst_tag_offset : integer := rf0_axu_ldst_size_offset + rf0_axu_ldst_size_q'length; +constant rf0_axu_ldst_update_offset : integer := rf0_axu_ldst_tag_offset + rf0_axu_ldst_tag_q'length; +constant rf0_axu_mffgpr_offset : integer := rf0_axu_ldst_update_offset + 1; +constant rf0_axu_mftgpr_offset : integer := rf0_axu_mffgpr_offset + 1; +constant rf0_axu_movedp_offset : integer := rf0_axu_mftgpr_offset + 1; +constant rf0_axu_store_offset : integer := rf0_axu_movedp_offset + 1; +constant rf0_error_offset : integer := rf0_axu_store_offset + 1; +constant rf0_gshare_offset : integer := rf0_error_offset + rf0_error_q'length; +constant rf0_ifar_offset : integer := rf0_gshare_offset + rf0_gshare_q'length; +constant rf0_instr_offset : integer := rf0_ifar_offset + rf0_ifar_q'length; +constant rf0_is_ucode_offset : integer := rf0_instr_offset + rf0_instr_q'length; +constant rf0_match_offset : integer := rf0_is_ucode_offset + 1; +constant rf0_pred_taken_cnt_offset : integer := rf0_match_offset + 1; +constant rf0_pred_update_offset : integer := rf0_pred_taken_cnt_offset + rf0_pred_taken_cnt_q'length; +constant rf0_s1_offset : integer := rf0_pred_update_offset + 1; +constant rf0_s1_vld_offset : integer := rf0_s1_offset + rf0_s1_q'length; +constant rf0_s2_offset : integer := rf0_s1_vld_offset + 1; +constant rf0_s2_vld_offset : integer := rf0_s2_offset + rf0_s2_q'length; +constant rf0_s3_offset : integer := rf0_s2_vld_offset + 1; +constant rf0_s3_vld_offset : integer := rf0_s3_offset + rf0_s3_q'length; +constant rf0_ta_offset : integer := rf0_s3_vld_offset + 1; +constant rf0_ta_vld_offset : integer := rf0_ta_offset + rf0_ta_q'length; +constant rf0_tid_offset : integer := rf0_ta_vld_offset + 1; +constant rf0_ucode_val_offset : integer := rf0_tid_offset + rf0_tid_q'length; +constant rf0_val_offset : integer := rf0_ucode_val_offset + rf0_ucode_val_q'length; +constant rf1_barrier_done_offset : integer := rf0_val_offset + rf0_val_q'length; +constant rf1_div_coll_offset : integer := rf1_barrier_done_offset + 1; +constant rf1_div_val_offset : integer := rf1_div_coll_offset + 1; +constant rf1_mul_valid_offset : integer := rf1_div_val_offset + rf1_div_val_q'length; +constant rf1_muldiv_coll_offset : integer := rf1_mul_valid_offset + 1; +constant rf1_multdiv_val_offset : integer := rf1_muldiv_coll_offset + 1; +constant rf1_recirc_ctr_offset : integer := rf1_multdiv_val_offset + rf1_multdiv_val_q'length; +constant rf1_recirc_ctr_flush_offset : integer := rf1_recirc_ctr_offset + rf1_recirc_ctr_q'length; +constant ex1_div_coll_offset : integer := rf1_recirc_ctr_flush_offset + 1; +constant ex1_div_val_offset : integer := ex1_div_coll_offset + 1; +constant ex1_muldiv_in_use_offset : integer := ex1_div_val_offset + ex1_div_val_q'length; +constant ex1_multdiv_val_offset : integer := ex1_muldiv_in_use_offset + 1; +constant ex1_recirc_ctr_flush_offset : integer := ex1_multdiv_val_offset + ex1_multdiv_val_q'length; +constant ex2_div_coll_offset : integer := ex1_recirc_ctr_flush_offset + 1; +constant ex2_div_val_offset : integer := ex2_div_coll_offset + 1; +constant ex2_multdiv_val_offset : integer := ex2_div_val_offset + ex2_div_val_q'length; +constant ex3_div_val_offset : integer := ex2_multdiv_val_offset + ex2_multdiv_val_q'length; +constant ex3_multdiv_val_offset : integer := ex3_div_val_offset + ex3_div_val_q'length; +constant ex4_div_val_offset : integer := ex3_multdiv_val_offset + ex3_multdiv_val_q'length; +constant ex5_div_val_offset : integer := ex4_div_val_offset + ex4_div_val_q'length; +constant ex6_div_barr_val_offset : integer := ex5_div_val_offset + ex5_div_val_q'length; +constant ex6_set_barr_offset : integer := ex6_div_barr_val_offset + 1; +constant an_ac_back_inv_offset : integer := ex6_set_barr_offset + ex6_set_barr_q'length; +constant an_ac_back_inv_addr_offset : integer := an_ac_back_inv_offset + 1; +constant an_ac_back_inv_target_bit3_offset : integer := an_ac_back_inv_addr_offset + an_ac_back_inv_addr_q'length; +constant back_inv_val_offset : integer := an_ac_back_inv_target_bit3_offset + 1; +constant coll_tid_offset : integer := back_inv_val_offset + 1; +constant div_barr_done_offset : integer := coll_tid_offset + coll_tid_q'length; +constant div_barr_thres_offset : integer := div_barr_done_offset + div_barr_done_q'length; +constant div_coll_barr_done_offset : integer := div_barr_thres_offset + div_barr_thres_q'length; +constant hold_divide_offset : integer := div_coll_barr_done_offset + div_coll_barr_done_q'length; +constant hold_error_offset : integer := hold_divide_offset + 1; +constant hold_ifar_offset : integer := hold_error_offset + hold_error_q'length; +constant hold_instr_offset : integer := hold_ifar_offset + hold_ifar_q'length; +constant hold_is_ucode_offset : integer := hold_instr_offset + hold_instr_q'length; +constant hold_match_offset : integer := hold_is_ucode_offset + 1; +constant hold_s1_offset : integer := hold_match_offset + 1; +constant hold_s1_vld_offset : integer := hold_s1_offset + hold_s1_q'length; +constant hold_s2_offset : integer := hold_s1_vld_offset + 1; +constant hold_s2_vld_offset : integer := hold_s2_offset + hold_s2_q'length; +constant hold_s3_offset : integer := hold_s2_vld_offset + 1; +constant hold_s3_vld_offset : integer := hold_s3_offset + hold_s3_q'length; +constant hold_ta_offset : integer := hold_s3_vld_offset + 1; +constant hold_ta_vld_offset : integer := hold_ta_offset + hold_ta_q'length; +constant hold_tid_offset : integer := hold_ta_vld_offset + 1; +constant hold_use_imm_offset : integer := hold_tid_offset + hold_tid_q'length; +constant lsu_xu_rel_ta_gpr_offset : integer := hold_use_imm_offset + 1; +constant lsu_xu_rel_wren_offset : integer := lsu_xu_rel_ta_gpr_offset + lsu_xu_rel_ta_gpr_q'length; +constant spare_0_offset : integer := lsu_xu_rel_wren_offset + 1; +constant spare_1_offset : integer := spare_0_offset + spare_0_q'length; +constant scan_right : integer := spare_1_offset + spare_1_q'length; +signal siv : std_ulogic_vector(0 to scan_right-1); +signal sov : std_ulogic_vector(0 to scan_right-1); +signal spare_0_lclk : clk_logic; +signal spare_1_lclk : clk_logic; +signal spare_0_d1clk, spare_0_d2clk : std_ulogic; +signal spare_1_d1clk, spare_1_d2clk : std_ulogic; +signal rf0_is_mfocrf : std_ulogic; +signal rf0_valid : std_ulogic; +signal rf0_hold_latch_act : std_ulogic; +signal rf0_multicyc_op : std_ulogic; +signal rf0_singlcyc_op : std_ulogic; +signal rf0_recirc_ctr_init : std_ulogic_vector(0 to 7); +signal rf0_recirc_ctr_done : std_ulogic; +signal rf0_recirc_ctr_start : std_ulogic; +signal rf0_divide, rf0_multiply : std_ulogic; +signal rf0_muldiv_in_use, rf1_muldiv_in_use : std_ulogic; +signal rf0_div_coll : std_ulogic; +signal rf0_derat_is_extload, rf0_derat_is_extstore : std_ulogic; +signal rf0_axu_is_extload, rf0_axu_is_extstore : std_ulogic; +signal rf0_thread_num : std_ulogic_vector(0 to 1); +signal icswx_val : std_ulogic_vector(0 to threads-1); +signal icswx_thrd_dec : std_ulogic_vector(0 to threads-1); +signal rf0_3source_instr : std_ulogic; +signal rf0_gpr0_zero : std_ulogic; +signal rf0_axu_gpr0_zero : std_ulogic; +signal ex5_div_barr_val : std_ulogic; +signal rf0_recirc_ctr_dec : std_ulogic_vector(0 to 7); +signal rf0_recirc_ctr_clear : std_ulogic; +signal rf1_barrier_en : std_ulogic; +signal rf1_barrier_done : std_ulogic_vector(0 to threads-1); +signal rf0_div_valid : std_ulogic; +signal ex5_div_val : std_ulogic_vector(0 to threads-1); +signal rf1_hold_tid_flush : std_ulogic; +signal rf0_tid : std_ulogic_vector(0 to threads-1); +signal rf0_use_imm : std_ulogic; +signal is2_act : std_ulogic; +signal rf0_instr : std_ulogic_vector(0 to 31); + BEGIN --@@ START OF EXECUTABLE CODE FOR XUQ_DEC_A + +fxa_fxb_rf0_spr_tid <= rf0_tid or rf0_ucode_val_q; +fxa_fxb_rf0_cpl_act <= or_reduce(rf0_tid or rf0_ucode_val_q); +fxa_fxb_rf0_cpl_tid <= rf0_tid_q; +fxa_fxb_rf0_is_mfocrf <= rf0_is_mfocrf; +fxa_fxb_rf0_3src_instr <= rf0_3source_instr and not rf0_recirc_ctr_done; +fxa_fxb_rf0_gpr0_zero <= (rf0_gpr0_zero or rf0_axu_gpr0_zero) and not rf0_recirc_ctr_done; +rf0_axu_gpr0_zero <= rf0_axu_ld_or_st_q and not or_reduce(rf0_s1_q); +dec_spr_rf0_instr <= rf0_instr; +fxa_fxb_rf0_instr <= rf0_instr; +mark_unused(spr_xucr0_clkg_ctl_b0); +is2_act <= '1'; +rf0_ucode_val_d <= iu_xu_is2_tid and (0 to threads-1=>iu_xu_is2_ucode_vld) and not xu_is2_flush; +rf0_val_d <= iu_xu_is2_tid and (0 to threads-1=>iu_xu_is2_vld) and not xu_is2_flush; +rf0_ta_vld_d <= iu_xu_is2_ta_vld and or_reduce(iu_xu_is2_tid and (0 to threads-1=> iu_xu_is2_vld) and not xu_is2_flush); +rf0_s1_vld_d <= iu_xu_is2_s1_vld and or_reduce(iu_xu_is2_tid and (0 to threads-1=>(iu_xu_is2_vld or iu_xu_is2_ucode_vld)) and not xu_is2_flush); +rf0_s2_vld_d <= iu_xu_is2_s2_vld and or_reduce(iu_xu_is2_tid and (0 to threads-1=>(iu_xu_is2_vld or iu_xu_is2_ucode_vld)) and not xu_is2_flush); +rf0_s3_vld_d <= iu_xu_is2_s3_vld and or_reduce(iu_xu_is2_tid and (0 to threads-1=>(iu_xu_is2_vld or iu_xu_is2_ucode_vld)) and not xu_is2_flush); + WITH s2'(rf0_recirc_ctr_start & rf0_recirc_ctr_done) SELECT fxa_fxb_rf0_val <= "0000" when "10", + hold_tid_q and not xu_rf0_flush when "01", + rf0_val_q and not xu_rf0_flush when others; + WITH s2'(rf0_recirc_ctr_start & (rf0_recirc_ctr_done or rf0_recirc_ctr_flush)) SELECT fxa_fxb_rf0_issued <= "0000" when "10", + hold_tid_q when "01", + (rf0_val_q or rf0_ucode_val_q) when others; + WITH s2'(rf0_recirc_ctr_start & rf0_recirc_ctr_done) SELECT fxa_fxb_rf0_ta_vld <= '0' when "10", + hold_ta_vld_q when "01", + rf0_ta_vld_q when others; +fxa_fxb_rf0_ucode_val <= rf0_ucode_val_q and not xu_rf0_flush; +fxa_fxb_rf0_act <= or_reduce(rf0_val_q) or or_reduce(rf0_ucode_val_q) or rf0_recirc_ctr_done; + WITH rf0_tid_q(0 to 3) SELECT rf0_thread_num <= "11" when "0001", + "10" when "0010", + "01" when "0100", + "00" when others; +rf0_valid <= or_reduce(rf0_val_q and not xu_rf0_flush); +rf1_muldiv_in_use <= or_reduce(rf1_recirc_ctr_q); +rf0_muldiv_in_use <= rf1_muldiv_in_use or rf0_recirc_ctr_start; +fxa_perf_muldiv_in_use <= ex1_muldiv_in_use_q; +rf1_hold_tid_flush <= or_reduce(hold_tid_q and xu_rf1_flush); +rf0_recirc_ctr_flush <= rf1_muldiv_in_use and rf1_hold_tid_flush; +rf0_recirc_ctr_clear <= rf0_recirc_ctr_flush or not (rf0_muldiv_in_use); +rf0_recirc_ctr_start <= rf0_valid and not rf1_muldiv_in_use and rf0_multicyc_op; +rf0_muldiv_coll <= rf0_valid and rf1_muldiv_in_use and (rf0_multicyc_op or rf0_singlcyc_op); +rf0_div_coll <= rf0_muldiv_coll and rf0_divide; +with rf0_recirc_ctr_start select + rf0_recirc_ctr_dec <= rf0_recirc_ctr_init when '1', + std_ulogic_vector(unsigned(rf1_recirc_ctr_q) - 1) when others; +with rf0_recirc_ctr_clear select + rf1_recirc_ctr_d <= (others=>'0') when '1', + rf0_recirc_ctr_dec when others; +rf0_recirc_ctr_done <= '1' when (rf1_recirc_ctr_q = "00000001") else '0'; +rf0_barrier_done <= hold_divide_q and (rf0_recirc_ctr_done or (rf0_recirc_ctr_flush and ex5_div_barr_val)); +rf1_barrier_done <= (others=>rf1_barrier_done_q); +fxa_iu_set_barr_tid <= ex6_set_barr_q; +ex5_set_barr <= gate(cpl_fxa_ex5_set_barr,rf1_muldiv_in_use); +coll_tid_d <= (coll_tid_q or ex5_set_barr) and not rf1_barrier_done; +div_coll_barr_done_d <= (coll_tid_q or ex5_set_barr) and not (0 to threads-1=>rf1_muldiv_in_use); +div_barr_done_d <= (hold_tid_q and rf1_barrier_done) or + icswx_val; +xu_div_coll_barr_done <= div_coll_barr_done_q; +xu_div_barr_done <= div_barr_done_q; +rf0_hold_latch_act <= rf0_recirc_ctr_start; +rf0_mul_valid <= rf0_valid and rf0_multiply and not rf1_muldiv_in_use; +rf0_div_valid <= rf0_valid and rf0_divide and not rf1_muldiv_in_use; +fxa_fxb_rf1_div_val <= or_reduce(rf1_div_val_q); +fxa_fxb_rf1_mul_val <= rf1_mul_valid_q; +fxa_fxb_rf1_div_ctr <= rf1_recirc_ctr_q; +fxa_fxb_ex1_hold_ctr_flush <= ex1_recirc_ctr_flush_q; +rf1_barrier_en <= '1' when (rf1_recirc_ctr_q > div_barr_thres_q) else '0'; +rf1_div_coll_d <= rf0_div_coll and or_reduce(rf0_tid_q and not coll_tid_q) and not rf1_hold_tid_flush; +ex1_div_coll_d <= rf1_div_coll_q and rf1_barrier_en and hold_divide_q and not rf1_hold_tid_flush; +ex2_div_coll_d <= ex1_div_coll_q and not rf1_hold_tid_flush; +fxa_cpl_ex2_div_coll <= gate(hold_tid_q,ex2_div_coll_q); +fxa_fxb_rf1_muldiv_coll <= rf1_muldiv_coll_q; +rf0_div_val <= gate(rf0_val_q,rf0_div_valid); +ex1_div_val_d <= rf1_div_val_q and not xu_rf1_flush; +ex2_div_val_d <= ex1_div_val_q and not xu_ex1_flush; +ex3_div_val_d <= ex2_div_val_q and not xu_ex2_flush; +ex4_div_val_d <= ex3_div_val_q and not xu_ex3_flush; +ex5_div_val_d <= ex4_div_val_q and not xu_ex4_flush; +ex5_div_val <= ex5_div_val_q and not xu_ex5_flush; +ex5_div_barr_val <= (or_reduce(ex5_div_val)) or + (ex6_div_barr_val_q and rf1_muldiv_in_use); +rf0_multdiv_val <= gate(rf0_val_q,rf0_recirc_ctr_start); +ex1_multdiv_val_d <= rf1_multdiv_val_q and not xu_rf1_flush; +ex2_multdiv_val_d <= ex1_multdiv_val_q and not xu_ex1_flush; +ex3_multdiv_val_d <= ex2_multdiv_val_q and not xu_ex2_flush; +fxa_fxb_rf0_mc_dep_chk_val <= rf0_multdiv_val; +dec_cpl_ex3_mc_dep_chk_val <= ex3_multdiv_val_q; +hold_tid_d <= rf0_tid_q; +hold_instr_d <= rf0_instr_q; +hold_ta_vld_d <= rf0_ta_vld_q; +hold_ta_d <= rf0_ta_q & rf0_thread_num; +hold_error_d <= rf0_error_q; +hold_match_d <= rf0_match_q; +hold_is_ucode_d <= rf0_is_ucode_q; +hold_ifar_d <= rf0_ifar_q; +hold_s1_d <= rf0_s1_q & rf0_thread_num; +hold_s2_d <= rf0_s2_q & rf0_thread_num; +hold_s3_d <= rf0_s3_q & rf0_thread_num; +hold_s1_vld_d <= rf0_s1_vld_q; +hold_s2_vld_d <= rf0_s2_vld_q; +hold_s3_vld_d <= rf0_s3_vld_q; +hold_use_imm_d <= rf0_use_imm; +with rf0_recirc_ctr_done select + fxa_fxb_rf0_tid <= (rf0_val_q or rf0_ucode_val_q) when '0', + hold_tid_q when others; +with rf0_recirc_ctr_done select + rf0_instr <= rf0_instr_q when '0', + hold_instr_q when others; +with rf0_recirc_ctr_done select + rf0_tid <= rf0_tid_q when '0', + hold_tid_q when others; +with rf0_recirc_ctr_done select + fxa_fxb_rf0_ta <= rf0_ta_q & rf0_thread_num when '0', + hold_ta_q when others; +with rf0_recirc_ctr_done select + fxa_fxb_rf0_error <= rf0_error_q when '0', + hold_error_q when others; +with rf0_recirc_ctr_done select + fxa_fxb_rf0_match <= rf0_match_q when '0', + hold_match_q when others; +with rf0_recirc_ctr_done select + fxa_fxb_rf0_is_ucode <= rf0_is_ucode_q when '0', + hold_is_ucode_q when others; +with rf0_recirc_ctr_done select + fxa_fxb_rf0_ifar <= rf0_ifar_q when '0', + hold_ifar_q when others; +with rf0_recirc_ctr_done select + fxa_fxb_rf0_s1 <= rf0_s1_q & rf0_thread_num when '0', + hold_s1_q when others; +with rf0_recirc_ctr_done select + fxa_fxb_rf0_s2 <= rf0_s2_q & rf0_thread_num when '0', + hold_s2_q when others; +with rf0_recirc_ctr_done select + fxa_fxb_rf0_s3 <= rf0_s3_q & rf0_thread_num when '0', + hold_s3_q when others; +with rf0_recirc_ctr_done select + fxa_fxb_rf0_s1_vld <= rf0_s1_vld_q when '0', + hold_s1_vld_q when others; +with rf0_recirc_ctr_done select + fxa_fxb_rf0_s2_vld <= rf0_s2_vld_q when '0', + hold_s2_vld_q when others; +with rf0_recirc_ctr_done select + fxa_fxb_rf0_s3_vld <= rf0_s3_vld_q when '0', + hold_s3_vld_q when others; +with rf0_recirc_ctr_done select + fxa_fxb_rf0_use_imm <= rf0_use_imm when '0', + hold_use_imm_q when others; +fxa_fxb_rf0_axu_ld_or_st <= rf0_axu_ld_or_st_q and not rf0_recirc_ctr_done; +fxa_fxb_rf0_axu_store <= rf0_axu_store_q and not rf0_recirc_ctr_done; +fxa_fxb_rf0_axu_mftgpr <= rf0_axu_mftgpr_q and not rf0_recirc_ctr_done; +fxa_fxb_rf0_axu_mffgpr <= rf0_axu_mffgpr_q and not rf0_recirc_ctr_done; +fxa_fxb_rf0_axu_movedp <= rf0_axu_movedp_q and not rf0_recirc_ctr_done; +fxa_fxb_rf0_pred_update <= rf0_pred_update_q and not rf0_recirc_ctr_done; +fxa_fxb_rf0_gshare <= rf0_gshare_q; +fxa_fxb_rf0_axu_instr_type <= rf0_axu_instr_type_q; +fxa_fxb_rf0_axu_ldst_forcealign <= rf0_axu_ldst_forcealign_q; +fxa_fxb_rf0_axu_ldst_forceexcept <= rf0_axu_ldst_forceexcept_q; +fxa_fxb_rf0_axu_ldst_indexed <= rf0_axu_ldst_indexed_q; +fxa_fxb_rf0_axu_ldst_tag <= rf0_axu_ldst_tag_q; +fxa_fxb_rf0_axu_ldst_size <= rf0_axu_ldst_size_q; +fxa_fxb_rf0_axu_ldst_update <= rf0_axu_ldst_update_q; +fxa_fxb_rf0_pred_taken_cnt <= rf0_pred_taken_cnt_q; + WITH an_ac_back_inv_addr_q(62 to 63) SELECT icswx_thrd_dec <= "1000" when "00", + "0100" when "01", + "0010" when "10", + "0001" when others; +back_inv_val_d <= an_ac_back_inv_q and an_ac_back_inv_target_bit3_q; +icswx_val <= gate(icswx_thrd_dec, back_inv_val_q); +dec_gpr_rf0_re0 <= rf0_s1_vld_q; +dec_gpr_rf0_re1 <= rf0_s2_vld_q; +dec_gpr_rf0_re2 <= rf0_s3_vld_q; +dec_gpr_rf0_ra0 <= rf0_s1_q & rf0_thread_num; +dec_gpr_rf0_ra1 <= rf0_s2_q & rf0_thread_num; +dec_gpr_rf0_ra2 <= rf0_s3_q & rf0_thread_num; +dec_gpr_rel_wren <= lsu_xu_rel_wren_q; +dec_gpr_rel_ta_gpr <= lsu_xu_rel_ta_gpr_q; +rf0_axu_is_extload <= rf0_axu_ldst_extpid_q and ((rf0_axu_ld_or_st_q and not (rf0_axu_mftgpr_q or rf0_axu_mffgpr_q)) and not rf0_axu_store_q); +rf0_axu_is_extstore <= rf0_axu_ldst_extpid_q and ((rf0_axu_ld_or_st_q and not (rf0_axu_mftgpr_q or rf0_axu_mffgpr_q)) and rf0_axu_store_q); +xu_lsu_rf0_derat_is_extload <= rf0_derat_is_extload or rf0_axu_is_extload; +xu_lsu_rf0_derat_is_extstore <= rf0_derat_is_extstore or rf0_axu_is_extstore; +fxa_fxb_rf0_xu_epid_instr <= not rf0_recirc_ctr_done and (rf0_derat_is_extload or rf0_derat_is_extstore); +fxa_fxb_rf0_axu_is_extload <= not rf0_recirc_ctr_done and rf0_axu_is_extload; +fxa_fxb_rf0_axu_is_extstore <= not rf0_recirc_ctr_done and rf0_axu_is_extstore; +xu_lsu_rf0_derat_val <= rf0_val_q or rf0_ucode_val_q; +dec_debug(0 TO 87) <= rf0_val_q & + rf0_instr_q(0 to 5) & + rf0_instr_q(21 to 30) & + hold_instr_q(0 to 5) & + hold_instr_q(21 to 30) & + rf0_ta_vld_q & + rf0_s1_vld_q & + rf0_s2_vld_q & + rf0_s3_vld_q & + xu_rf0_flush & + hold_ta_vld_q & + ex1_recirc_ctr_flush_q & + rf0_recirc_ctr_start & + rf0_recirc_ctr_done & + rf1_recirc_ctr_q & + hold_tid_q & + rf0_divide & + rf0_multiply & + rf1_barrier_done_q & + ex6_set_barr_q & + coll_tid_q & + div_coll_barr_done_q & + div_barr_done_q & + rf1_muldiv_coll_q & + rf1_div_coll_q & + ex1_div_coll_q & + cpl_fxa_ex5_set_barr & + ex5_div_barr_val & + back_inv_val_q; +dec_debug(88 TO 175) <= rf0_val_q & + rf0_instr_q & + rf0_ta_q & + rf0_error_q & + rf0_match_q & + rf0_is_ucode_q & + rf0_s1_vld_q & + rf0_s2_vld_q & + rf0_s3_vld_q & + rf0_axu_ld_or_st_q & + rf0_axu_store_q & + rf0_axu_mftgpr_q & + rf0_axu_mffgpr_q & + rf0_axu_movedp_q & + rf0_pred_update_q & + rf0_gshare_q & + rf0_axu_instr_type_q & + rf0_axu_ldst_forcealign_q & + rf0_axu_ldst_forceexcept_q & + rf0_axu_ldst_indexed_q & + rf0_axu_ldst_tag_q & + rf0_axu_ldst_size_q & + rf0_axu_ldst_update_q & + rf0_pred_taken_cnt_q & + rf0_recirc_ctr_done & + rf0_recirc_ctr_start & + rf1_muldiv_coll_q & + back_inv_val_q; +-- +-- Final Table Listing +-- *INPUTS*===============*OUTPUTS*========================* +-- | | | +-- | rf0_instr_q | | +-- | | rf0_instr_q | | +-- | | | rf0_instr_q | rf0_recirc_ctr_init | +-- | | | | | | rf0_singlcyc_op | +-- | | | | | | | rf0_multicyc_op | +-- | | | | | | | | rf0_divide | +-- | | | | | | | | | rf0_multiply | +-- | | | | | | | | | | rf0_is_mfocrf | +-- | | | | | | | | | | | | +-- | 000000 1 2222222223 | | | | | | | | +-- | 012345 1 1234567890 | 01234567 | | | | | | +-- *TYPE*=================+================================+ +-- | PPPPPP P PPPPPPPPPP | PPPPPPPP P P P P P | +-- *POLARITY*------------>| ++++++++ + + + + + | +-- *PHASE*--------------->| TTTTTTTT T T T T T | +-- *TERMS*================+================================+ +-- 1 | 011111 1 0000010011 | ........ . . . . 1 | +-- 2 | 011111 - 1-11101001 | .......1 . . . . . | +-- 3 | 011111 - -011101011 | ........ 1 . . 1 . | +-- 4 | 011111 - -00-001011 | ........ 1 . . 1 . | +-- 5 | 011111 - -011101001 | ......1. . 1 . 1 . | +-- 6 | 011111 - -110-01001 | 1......1 . 1 1 . . | +-- 7 | 011111 - -00-001001 | ......11 . 1 . 1 . | +-- 8 | 011111 - -110-01011 | .1.....1 . 1 1 . . | +-- 9 | 011111 - -111-01011 | ..1....1 . 1 1 . . | +-- 10 | 011111 - -111-01001 | .1.....1 . 1 1 . . | +-- 11 | 000111 - ---------- | .......1 . 1 . 1 . | +-- *=======================================================* +-- +-- Table TBL_RF0_DEC Signal Assignments for Product Terms +MQQ1:TBL_RF0_DEC_PT(1) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(11) & RF0_INSTR_Q(21) & + RF0_INSTR_Q(22) & RF0_INSTR_Q(23) & + RF0_INSTR_Q(24) & RF0_INSTR_Q(25) & + RF0_INSTR_Q(26) & RF0_INSTR_Q(27) & + RF0_INSTR_Q(28) & RF0_INSTR_Q(29) & + RF0_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("01111110000010011")); +MQQ2:TBL_RF0_DEC_PT(2) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(21) & RF0_INSTR_Q(23) & + RF0_INSTR_Q(24) & RF0_INSTR_Q(25) & + RF0_INSTR_Q(26) & RF0_INSTR_Q(27) & + RF0_INSTR_Q(28) & RF0_INSTR_Q(29) & + RF0_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111111101001")); +MQQ3:TBL_RF0_DEC_PT(3) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(22) & RF0_INSTR_Q(23) & + RF0_INSTR_Q(24) & RF0_INSTR_Q(25) & + RF0_INSTR_Q(26) & RF0_INSTR_Q(27) & + RF0_INSTR_Q(28) & RF0_INSTR_Q(29) & + RF0_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111011101011")); +MQQ4:TBL_RF0_DEC_PT(4) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(22) & RF0_INSTR_Q(23) & + RF0_INSTR_Q(25) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111100001011")); +MQQ5:TBL_RF0_DEC_PT(5) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(22) & RF0_INSTR_Q(23) & + RF0_INSTR_Q(24) & RF0_INSTR_Q(25) & + RF0_INSTR_Q(26) & RF0_INSTR_Q(27) & + RF0_INSTR_Q(28) & RF0_INSTR_Q(29) & + RF0_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111011101001")); +MQQ6:TBL_RF0_DEC_PT(6) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(22) & RF0_INSTR_Q(23) & + RF0_INSTR_Q(24) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111111001001")); +MQQ7:TBL_RF0_DEC_PT(7) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(22) & RF0_INSTR_Q(23) & + RF0_INSTR_Q(25) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111100001001")); +MQQ8:TBL_RF0_DEC_PT(8) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(22) & RF0_INSTR_Q(23) & + RF0_INSTR_Q(24) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111111001011")); +MQQ9:TBL_RF0_DEC_PT(9) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(22) & RF0_INSTR_Q(23) & + RF0_INSTR_Q(24) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111111101011")); +MQQ10:TBL_RF0_DEC_PT(10) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(22) & RF0_INSTR_Q(23) & + RF0_INSTR_Q(24) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111111101001")); +MQQ11:TBL_RF0_DEC_PT(11) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) + ) , STD_ULOGIC_VECTOR'("000111")); +-- Table TBL_RF0_DEC Signal Assignments for Outputs +MQQ12:RF0_RECIRC_CTR_INIT(0) <= + (TBL_RF0_DEC_PT(6)); +MQQ13:RF0_RECIRC_CTR_INIT(1) <= + (TBL_RF0_DEC_PT(8) OR TBL_RF0_DEC_PT(10) + ); +MQQ14:RF0_RECIRC_CTR_INIT(2) <= + (TBL_RF0_DEC_PT(9)); +MQQ15:RF0_RECIRC_CTR_INIT(3) <= + ('0'); +MQQ16:RF0_RECIRC_CTR_INIT(4) <= + ('0'); +MQQ17:RF0_RECIRC_CTR_INIT(5) <= + ('0'); +MQQ18:RF0_RECIRC_CTR_INIT(6) <= + (TBL_RF0_DEC_PT(5) OR TBL_RF0_DEC_PT(7) + ); +MQQ19:RF0_RECIRC_CTR_INIT(7) <= + (TBL_RF0_DEC_PT(2) OR TBL_RF0_DEC_PT(6) + OR TBL_RF0_DEC_PT(7) OR TBL_RF0_DEC_PT(8) + OR TBL_RF0_DEC_PT(9) OR TBL_RF0_DEC_PT(10) + OR TBL_RF0_DEC_PT(11)); +MQQ20:RF0_SINGLCYC_OP <= + (TBL_RF0_DEC_PT(3) OR TBL_RF0_DEC_PT(4) + ); +MQQ21:RF0_MULTICYC_OP <= + (TBL_RF0_DEC_PT(5) OR TBL_RF0_DEC_PT(6) + OR TBL_RF0_DEC_PT(7) OR TBL_RF0_DEC_PT(8) + OR TBL_RF0_DEC_PT(9) OR TBL_RF0_DEC_PT(10) + OR TBL_RF0_DEC_PT(11)); +MQQ22:RF0_DIVIDE <= + (TBL_RF0_DEC_PT(6) OR TBL_RF0_DEC_PT(8) + OR TBL_RF0_DEC_PT(9) OR TBL_RF0_DEC_PT(10) + ); +MQQ23:RF0_MULTIPLY <= + (TBL_RF0_DEC_PT(3) OR TBL_RF0_DEC_PT(4) + OR TBL_RF0_DEC_PT(5) OR TBL_RF0_DEC_PT(7) + OR TBL_RF0_DEC_PT(11)); +MQQ24:RF0_IS_MFOCRF <= + (TBL_RF0_DEC_PT(1)); + +-- +-- Final Table Listing +-- *INPUTS*=============*OUTPUTS*=================* +-- | | | +-- | rf0_instr_q | rf0_derat_is_extload | +-- | | rf0_instr_q | | rf0_derat_is_extstore | +-- | | | | | | | +-- | 000000 2222222223 | | | | +-- | 012345 1234567890 | | | | +-- *TYPE*===============+=========================+ +-- | PPPPPP PPPPPPPPPP | P P | +-- *POLARITY*---------->| + + | +-- *PHASE*------------->| T T | +-- *TERMS*==============+=========================+ +-- 1 | 011111 1110110110 | . 1 | +-- 2 | 011111 1111111111 | . 1 | +-- 3 | 011111 1111011111 | 1 . | +-- 4 | 011111 00000111-1 | 1 . | +-- 5 | 011111 00100111-1 | . 1 | +-- 6 | 011111 0-00-11111 | 1 . | +-- 7 | 011111 000--11111 | 1 . | +-- 8 | 011111 0011-11111 | . 1 | +-- 9 | 011111 0-10011111 | . 1 | +-- *==============================================* +-- +-- Table TBL_RF0_EPID_DEC Signal Assignments for Product Terms +MQQ25:TBL_RF0_EPID_DEC_PT(1) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(21) & RF0_INSTR_Q(22) & + RF0_INSTR_Q(23) & RF0_INSTR_Q(24) & + RF0_INSTR_Q(25) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111111110110110")); +MQQ26:TBL_RF0_EPID_DEC_PT(2) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(21) & RF0_INSTR_Q(22) & + RF0_INSTR_Q(23) & RF0_INSTR_Q(24) & + RF0_INSTR_Q(25) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111111111111111")); +MQQ27:TBL_RF0_EPID_DEC_PT(3) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(21) & RF0_INSTR_Q(22) & + RF0_INSTR_Q(23) & RF0_INSTR_Q(24) & + RF0_INSTR_Q(25) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111111111011111")); +MQQ28:TBL_RF0_EPID_DEC_PT(4) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(21) & RF0_INSTR_Q(22) & + RF0_INSTR_Q(23) & RF0_INSTR_Q(24) & + RF0_INSTR_Q(25) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111000001111")); +MQQ29:TBL_RF0_EPID_DEC_PT(5) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(21) & RF0_INSTR_Q(22) & + RF0_INSTR_Q(23) & RF0_INSTR_Q(24) & + RF0_INSTR_Q(25) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111001001111")); +MQQ30:TBL_RF0_EPID_DEC_PT(6) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(21) & RF0_INSTR_Q(23) & + RF0_INSTR_Q(24) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111100011111")); +MQQ31:TBL_RF0_EPID_DEC_PT(7) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(21) & RF0_INSTR_Q(22) & + RF0_INSTR_Q(23) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111100011111")); +MQQ32:TBL_RF0_EPID_DEC_PT(8) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(21) & RF0_INSTR_Q(22) & + RF0_INSTR_Q(23) & RF0_INSTR_Q(24) & + RF0_INSTR_Q(26) & RF0_INSTR_Q(27) & + RF0_INSTR_Q(28) & RF0_INSTR_Q(29) & + RF0_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111001111111")); +MQQ33:TBL_RF0_EPID_DEC_PT(9) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(21) & RF0_INSTR_Q(23) & + RF0_INSTR_Q(24) & RF0_INSTR_Q(25) & + RF0_INSTR_Q(26) & RF0_INSTR_Q(27) & + RF0_INSTR_Q(28) & RF0_INSTR_Q(29) & + RF0_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111010011111")); +-- Table TBL_RF0_EPID_DEC Signal Assignments for Outputs +MQQ34:RF0_DERAT_IS_EXTLOAD <= + (TBL_RF0_EPID_DEC_PT(3) OR TBL_RF0_EPID_DEC_PT(4) + OR TBL_RF0_EPID_DEC_PT(6) OR TBL_RF0_EPID_DEC_PT(7) + ); +MQQ35:RF0_DERAT_IS_EXTSTORE <= + (TBL_RF0_EPID_DEC_PT(1) OR TBL_RF0_EPID_DEC_PT(2) + OR TBL_RF0_EPID_DEC_PT(5) OR TBL_RF0_EPID_DEC_PT(8) + OR TBL_RF0_EPID_DEC_PT(9)); + +-- +-- Final Table Listing +-- *INPUTS*========================*OUTPUTS*===========* +-- | | | +-- | rf0_instr_q | | +-- | | | rf0_3source_instr | +-- | | rf0_instr_q | | | +-- | | | rf0_instr_q | | | +-- | | | | | | | +-- | 000000 2222222223 33 | | | +-- | 012345 1234567890 01 | | | +-- *TYPE*==========================+===================+ +-- | PPPPPP PPPPPPPPPP PP | P | +-- *POLARITY*--------------------->| + | +-- *PHASE*------------------------>| T | +-- *TERMS*=========================+===================+ +-- 1 | 011111 0-1001011- -- | 1 | +-- 2 | 011111 1111010010 -- | 1 | +-- 3 | 011111 1110-10110 -- | 1 | +-- 4 | 011111 10100101-0 -- | 1 | +-- 5 | 011111 001001-1-1 -- | 1 | +-- 6 | 011111 0010-101-1 -- | 1 | +-- 7 | 011111 001-01-111 -- | 1 | +-- 8 | 011111 001--10111 -- | 1 | +-- 9 | 011111 0-1001-111 -- | 1 | +-- 10 | 011111 0-10-10111 -- | 1 | +-- 11 | 011111 001-01011- -- | 1 | +-- 12 | 10-10- ---------- -- | 1 | +-- 13 | 111110 ---------- 0- | 1 | +-- 14 | 1001-- ---------- -- | 1 | +-- 15 | 10-1-1 ---------- -- | 1 | +-- *===================================================* +-- +-- Table TBL_3SRC_DEC Signal Assignments for Product Terms +MQQ36:TBL_3SRC_DEC_PT(1) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(21) & RF0_INSTR_Q(23) & + RF0_INSTR_Q(24) & RF0_INSTR_Q(25) & + RF0_INSTR_Q(26) & RF0_INSTR_Q(27) & + RF0_INSTR_Q(28) & RF0_INSTR_Q(29) + ) , STD_ULOGIC_VECTOR'("01111101001011")); +MQQ37:TBL_3SRC_DEC_PT(2) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(21) & RF0_INSTR_Q(22) & + RF0_INSTR_Q(23) & RF0_INSTR_Q(24) & + RF0_INSTR_Q(25) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111111111010010")); +MQQ38:TBL_3SRC_DEC_PT(3) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(21) & RF0_INSTR_Q(22) & + RF0_INSTR_Q(23) & RF0_INSTR_Q(24) & + RF0_INSTR_Q(26) & RF0_INSTR_Q(27) & + RF0_INSTR_Q(28) & RF0_INSTR_Q(29) & + RF0_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111111010110")); +MQQ39:TBL_3SRC_DEC_PT(4) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(21) & RF0_INSTR_Q(22) & + RF0_INSTR_Q(23) & RF0_INSTR_Q(24) & + RF0_INSTR_Q(25) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111101001010")); +MQQ40:TBL_3SRC_DEC_PT(5) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(21) & RF0_INSTR_Q(22) & + RF0_INSTR_Q(23) & RF0_INSTR_Q(24) & + RF0_INSTR_Q(25) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(28) & RF0_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111100100111")); +MQQ41:TBL_3SRC_DEC_PT(6) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(21) & RF0_INSTR_Q(22) & + RF0_INSTR_Q(23) & RF0_INSTR_Q(24) & + RF0_INSTR_Q(26) & RF0_INSTR_Q(27) & + RF0_INSTR_Q(28) & RF0_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111100101011")); +MQQ42:TBL_3SRC_DEC_PT(7) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(21) & RF0_INSTR_Q(22) & + RF0_INSTR_Q(23) & RF0_INSTR_Q(25) & + RF0_INSTR_Q(26) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111100101111")); +MQQ43:TBL_3SRC_DEC_PT(8) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(21) & RF0_INSTR_Q(22) & + RF0_INSTR_Q(23) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111100110111")); +MQQ44:TBL_3SRC_DEC_PT(9) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(21) & RF0_INSTR_Q(23) & + RF0_INSTR_Q(24) & RF0_INSTR_Q(25) & + RF0_INSTR_Q(26) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111101001111")); +MQQ45:TBL_3SRC_DEC_PT(10) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(21) & RF0_INSTR_Q(23) & + RF0_INSTR_Q(24) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111101010111")); +MQQ46:TBL_3SRC_DEC_PT(11) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(21) & RF0_INSTR_Q(22) & + RF0_INSTR_Q(23) & RF0_INSTR_Q(25) & + RF0_INSTR_Q(26) & RF0_INSTR_Q(27) & + RF0_INSTR_Q(28) & RF0_INSTR_Q(29) + ) , STD_ULOGIC_VECTOR'("01111100101011")); +MQQ47:TBL_3SRC_DEC_PT(12) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) + ) , STD_ULOGIC_VECTOR'("1010")); +MQQ48:TBL_3SRC_DEC_PT(13) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("1111100")); +MQQ49:TBL_3SRC_DEC_PT(14) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) + ) , STD_ULOGIC_VECTOR'("1001")); +MQQ50:TBL_3SRC_DEC_PT(15) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(05) + ) , STD_ULOGIC_VECTOR'("1011")); +-- Table TBL_3SRC_DEC Signal Assignments for Outputs +MQQ51:RF0_3SOURCE_INSTR <= + (TBL_3SRC_DEC_PT(1) OR TBL_3SRC_DEC_PT(2) + OR TBL_3SRC_DEC_PT(3) OR TBL_3SRC_DEC_PT(4) + OR TBL_3SRC_DEC_PT(5) OR TBL_3SRC_DEC_PT(6) + OR TBL_3SRC_DEC_PT(7) OR TBL_3SRC_DEC_PT(8) + OR TBL_3SRC_DEC_PT(9) OR TBL_3SRC_DEC_PT(10) + OR TBL_3SRC_DEC_PT(11) OR TBL_3SRC_DEC_PT(12) + OR TBL_3SRC_DEC_PT(13) OR TBL_3SRC_DEC_PT(14) + OR TBL_3SRC_DEC_PT(15)); + +-- +-- Final Table Listing +-- *INPUTS*========================*OUTPUTS*==============* +-- | | | +-- | rf0_instr_q | rf0_gpr0_zero | +-- | | rf0_instr_q | | | +-- | | | rf0_instr_q | | | +-- | | | | rf0_s1_q | | | +-- | | | | | | | | +-- | 000000 2222222223 33 000000 | | | +-- | 012345 1234567890 01 012345 | | | +-- *TYPE*==========================+======================+ +-- | PPPPPP PPPPPPPPPP PP PPPPPP | P | +-- *POLARITY*--------------------->| + | +-- *PHASE*------------------------>| T | +-- *TERMS*=========================+======================+ +-- 1 | 0-1111 0010-00110 -- 000000 | 1 | +-- 2 | 0-1111 00000101-- -- 000000 | 1 | +-- 3 | 0-1111 0--001011- -- 000000 | 1 | +-- 4 | 0-1111 00111-0110 -- 000000 | 1 | +-- 5 | 0-1111 1-11110110 -- 000000 | 1 | +-- 6 | 0-1111 00--01011- -- 000000 | 1 | +-- 7 | 0-1111 0--001-111 -- 000000 | 1 | +-- 8 | 0-1111 -11-010110 -- 000000 | 1 | +-- 9 | 0-1111 10-00101-0 -- 000000 | 1 | +-- 10 | 0-1111 110-110011 -- 000000 | 1 | +-- 11 | 0-1111 11101-0110 -- 000000 | 1 | +-- 12 | 0-1111 1111--1111 -- 000000 | 1 | +-- 13 | 0-1111 110-010010 -- 000000 | 1 | +-- 14 | 011111 0010100011 -- ------ | 1 | +-- 15 | 0-1111 0-11100110 -- 000000 | 1 | +-- 16 | 011111 0011-01110 -- ------ | 1 | +-- 17 | 0-1111 11-0010-10 -- 000000 | 1 | +-- 18 | 0-1111 0-00--1111 -- 000000 | 1 | +-- 19 | 0-1111 0000110011 -- 000000 | 1 | +-- 20 | 0-1111 10--010101 -- 000000 | 1 | +-- 21 | 0-1111 00-1--1111 -- 000000 | 1 | +-- 22 | 0-1111 00-001-1-1 -- 000000 | 1 | +-- 23 | 0-1111 01010101-1 -- 000000 | 1 | +-- 24 | 0-1111 0-100-0110 -- 000000 | 1 | +-- 25 | 0-1111 00-10101-0 -- 000000 | 1 | +-- 26 | 0-1111 0000010-10 -- 000000 | 1 | +-- 27 | 0-1111 0010010-11 -- 000000 | 1 | +-- 28 | 10---0 ---------- -- 000000 | 1 | +-- 29 | 0-1111 0000-10110 -- 000000 | 1 | +-- 30 | 1-1010 ---------- -0 000000 | 1 | +-- 31 | 1-1-10 ---------- 00 000000 | 1 | +-- 32 | 0-1111 -----01111 -- 000000 | 1 | +-- 33 | -0111- ---------- -- 000000 | 1 | +-- *======================================================* +-- +-- Table TBL_GPR0_ZERO Signal Assignments for Product Terms +MQQ52:TBL_GPR0_ZERO_PT(1) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) & + RF0_INSTR_Q(05) & RF0_INSTR_Q(21) & + RF0_INSTR_Q(22) & RF0_INSTR_Q(23) & + RF0_INSTR_Q(24) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) & + RF0_S1_Q(00) & RF0_S1_Q(01) & + RF0_S1_Q(02) & RF0_S1_Q(03) & + RF0_S1_Q(04) & RF0_S1_Q(05) + ) , STD_ULOGIC_VECTOR'("01111001000110000000")); +MQQ53:TBL_GPR0_ZERO_PT(2) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) & + RF0_INSTR_Q(05) & RF0_INSTR_Q(21) & + RF0_INSTR_Q(22) & RF0_INSTR_Q(23) & + RF0_INSTR_Q(24) & RF0_INSTR_Q(25) & + RF0_INSTR_Q(26) & RF0_INSTR_Q(27) & + RF0_INSTR_Q(28) & RF0_S1_Q(00) & + RF0_S1_Q(01) & RF0_S1_Q(02) & + RF0_S1_Q(03) & RF0_S1_Q(04) & + RF0_S1_Q(05) ) , STD_ULOGIC_VECTOR'("0111100000101000000")); +MQQ54:TBL_GPR0_ZERO_PT(3) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) & + RF0_INSTR_Q(05) & RF0_INSTR_Q(21) & + RF0_INSTR_Q(24) & RF0_INSTR_Q(25) & + RF0_INSTR_Q(26) & RF0_INSTR_Q(27) & + RF0_INSTR_Q(28) & RF0_INSTR_Q(29) & + RF0_S1_Q(00) & RF0_S1_Q(01) & + RF0_S1_Q(02) & RF0_S1_Q(03) & + RF0_S1_Q(04) & RF0_S1_Q(05) + ) , STD_ULOGIC_VECTOR'("011110001011000000")); +MQQ55:TBL_GPR0_ZERO_PT(4) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) & + RF0_INSTR_Q(05) & RF0_INSTR_Q(21) & + RF0_INSTR_Q(22) & RF0_INSTR_Q(23) & + RF0_INSTR_Q(24) & RF0_INSTR_Q(25) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) & + RF0_S1_Q(00) & RF0_S1_Q(01) & + RF0_S1_Q(02) & RF0_S1_Q(03) & + RF0_S1_Q(04) & RF0_S1_Q(05) + ) , STD_ULOGIC_VECTOR'("01111001110110000000")); +MQQ56:TBL_GPR0_ZERO_PT(5) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) & + RF0_INSTR_Q(05) & RF0_INSTR_Q(21) & + RF0_INSTR_Q(23) & RF0_INSTR_Q(24) & + RF0_INSTR_Q(25) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) & + RF0_S1_Q(00) & RF0_S1_Q(01) & + RF0_S1_Q(02) & RF0_S1_Q(03) & + RF0_S1_Q(04) & RF0_S1_Q(05) + ) , STD_ULOGIC_VECTOR'("01111111110110000000")); +MQQ57:TBL_GPR0_ZERO_PT(6) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) & + RF0_INSTR_Q(05) & RF0_INSTR_Q(21) & + RF0_INSTR_Q(22) & RF0_INSTR_Q(25) & + RF0_INSTR_Q(26) & RF0_INSTR_Q(27) & + RF0_INSTR_Q(28) & RF0_INSTR_Q(29) & + RF0_S1_Q(00) & RF0_S1_Q(01) & + RF0_S1_Q(02) & RF0_S1_Q(03) & + RF0_S1_Q(04) & RF0_S1_Q(05) + ) , STD_ULOGIC_VECTOR'("011110001011000000")); +MQQ58:TBL_GPR0_ZERO_PT(7) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) & + RF0_INSTR_Q(05) & RF0_INSTR_Q(21) & + RF0_INSTR_Q(24) & RF0_INSTR_Q(25) & + RF0_INSTR_Q(26) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) & + RF0_S1_Q(00) & RF0_S1_Q(01) & + RF0_S1_Q(02) & RF0_S1_Q(03) & + RF0_S1_Q(04) & RF0_S1_Q(05) + ) , STD_ULOGIC_VECTOR'("011110001111000000")); +MQQ59:TBL_GPR0_ZERO_PT(8) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) & + RF0_INSTR_Q(05) & RF0_INSTR_Q(22) & + RF0_INSTR_Q(23) & RF0_INSTR_Q(25) & + RF0_INSTR_Q(26) & RF0_INSTR_Q(27) & + RF0_INSTR_Q(28) & RF0_INSTR_Q(29) & + RF0_INSTR_Q(30) & RF0_S1_Q(00) & + RF0_S1_Q(01) & RF0_S1_Q(02) & + RF0_S1_Q(03) & RF0_S1_Q(04) & + RF0_S1_Q(05) ) , STD_ULOGIC_VECTOR'("0111111010110000000")); +MQQ60:TBL_GPR0_ZERO_PT(9) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) & + RF0_INSTR_Q(05) & RF0_INSTR_Q(21) & + RF0_INSTR_Q(22) & RF0_INSTR_Q(24) & + RF0_INSTR_Q(25) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(30) & RF0_S1_Q(00) & + RF0_S1_Q(01) & RF0_S1_Q(02) & + RF0_S1_Q(03) & RF0_S1_Q(04) & + RF0_S1_Q(05) ) , STD_ULOGIC_VECTOR'("0111110001010000000")); +MQQ61:TBL_GPR0_ZERO_PT(10) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) & + RF0_INSTR_Q(05) & RF0_INSTR_Q(21) & + RF0_INSTR_Q(22) & RF0_INSTR_Q(23) & + RF0_INSTR_Q(25) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) & + RF0_S1_Q(00) & RF0_S1_Q(01) & + RF0_S1_Q(02) & RF0_S1_Q(03) & + RF0_S1_Q(04) & RF0_S1_Q(05) + ) , STD_ULOGIC_VECTOR'("01111110110011000000")); +MQQ62:TBL_GPR0_ZERO_PT(11) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) & + RF0_INSTR_Q(05) & RF0_INSTR_Q(21) & + RF0_INSTR_Q(22) & RF0_INSTR_Q(23) & + RF0_INSTR_Q(24) & RF0_INSTR_Q(25) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) & + RF0_S1_Q(00) & RF0_S1_Q(01) & + RF0_S1_Q(02) & RF0_S1_Q(03) & + RF0_S1_Q(04) & RF0_S1_Q(05) + ) , STD_ULOGIC_VECTOR'("01111111010110000000")); +MQQ63:TBL_GPR0_ZERO_PT(12) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) & + RF0_INSTR_Q(05) & RF0_INSTR_Q(21) & + RF0_INSTR_Q(22) & RF0_INSTR_Q(23) & + RF0_INSTR_Q(24) & RF0_INSTR_Q(27) & + RF0_INSTR_Q(28) & RF0_INSTR_Q(29) & + RF0_INSTR_Q(30) & RF0_S1_Q(00) & + RF0_S1_Q(01) & RF0_S1_Q(02) & + RF0_S1_Q(03) & RF0_S1_Q(04) & + RF0_S1_Q(05) ) , STD_ULOGIC_VECTOR'("0111111111111000000")); +MQQ64:TBL_GPR0_ZERO_PT(13) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) & + RF0_INSTR_Q(05) & RF0_INSTR_Q(21) & + RF0_INSTR_Q(22) & RF0_INSTR_Q(23) & + RF0_INSTR_Q(25) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) & + RF0_S1_Q(00) & RF0_S1_Q(01) & + RF0_S1_Q(02) & RF0_S1_Q(03) & + RF0_S1_Q(04) & RF0_S1_Q(05) + ) , STD_ULOGIC_VECTOR'("01111110010010000000")); +MQQ65:TBL_GPR0_ZERO_PT(14) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(21) & RF0_INSTR_Q(22) & + RF0_INSTR_Q(23) & RF0_INSTR_Q(24) & + RF0_INSTR_Q(25) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111110010100011")); +MQQ66:TBL_GPR0_ZERO_PT(15) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) & + RF0_INSTR_Q(05) & RF0_INSTR_Q(21) & + RF0_INSTR_Q(23) & RF0_INSTR_Q(24) & + RF0_INSTR_Q(25) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) & + RF0_S1_Q(00) & RF0_S1_Q(01) & + RF0_S1_Q(02) & RF0_S1_Q(03) & + RF0_S1_Q(04) & RF0_S1_Q(05) + ) , STD_ULOGIC_VECTOR'("01111011100110000000")); +MQQ67:TBL_GPR0_ZERO_PT(16) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(21) & RF0_INSTR_Q(22) & + RF0_INSTR_Q(23) & RF0_INSTR_Q(24) & + RF0_INSTR_Q(26) & RF0_INSTR_Q(27) & + RF0_INSTR_Q(28) & RF0_INSTR_Q(29) & + RF0_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111001101110")); +MQQ68:TBL_GPR0_ZERO_PT(17) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) & + RF0_INSTR_Q(05) & RF0_INSTR_Q(21) & + RF0_INSTR_Q(22) & RF0_INSTR_Q(24) & + RF0_INSTR_Q(25) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(29) & + RF0_INSTR_Q(30) & RF0_S1_Q(00) & + RF0_S1_Q(01) & RF0_S1_Q(02) & + RF0_S1_Q(03) & RF0_S1_Q(04) & + RF0_S1_Q(05) ) , STD_ULOGIC_VECTOR'("0111111001010000000")); +MQQ69:TBL_GPR0_ZERO_PT(18) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) & + RF0_INSTR_Q(05) & RF0_INSTR_Q(21) & + RF0_INSTR_Q(23) & RF0_INSTR_Q(24) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) & + RF0_S1_Q(00) & RF0_S1_Q(01) & + RF0_S1_Q(02) & RF0_S1_Q(03) & + RF0_S1_Q(04) & RF0_S1_Q(05) + ) , STD_ULOGIC_VECTOR'("011110001111000000")); +MQQ70:TBL_GPR0_ZERO_PT(19) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) & + RF0_INSTR_Q(05) & RF0_INSTR_Q(21) & + RF0_INSTR_Q(22) & RF0_INSTR_Q(23) & + RF0_INSTR_Q(24) & RF0_INSTR_Q(25) & + RF0_INSTR_Q(26) & RF0_INSTR_Q(27) & + RF0_INSTR_Q(28) & RF0_INSTR_Q(29) & + RF0_INSTR_Q(30) & RF0_S1_Q(00) & + RF0_S1_Q(01) & RF0_S1_Q(02) & + RF0_S1_Q(03) & RF0_S1_Q(04) & + RF0_S1_Q(05) ) , STD_ULOGIC_VECTOR'("011110000110011000000")); +MQQ71:TBL_GPR0_ZERO_PT(20) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) & + RF0_INSTR_Q(05) & RF0_INSTR_Q(21) & + RF0_INSTR_Q(22) & RF0_INSTR_Q(25) & + RF0_INSTR_Q(26) & RF0_INSTR_Q(27) & + RF0_INSTR_Q(28) & RF0_INSTR_Q(29) & + RF0_INSTR_Q(30) & RF0_S1_Q(00) & + RF0_S1_Q(01) & RF0_S1_Q(02) & + RF0_S1_Q(03) & RF0_S1_Q(04) & + RF0_S1_Q(05) ) , STD_ULOGIC_VECTOR'("0111110010101000000")); +MQQ72:TBL_GPR0_ZERO_PT(21) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) & + RF0_INSTR_Q(05) & RF0_INSTR_Q(21) & + RF0_INSTR_Q(22) & RF0_INSTR_Q(24) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) & + RF0_S1_Q(00) & RF0_S1_Q(01) & + RF0_S1_Q(02) & RF0_S1_Q(03) & + RF0_S1_Q(04) & RF0_S1_Q(05) + ) , STD_ULOGIC_VECTOR'("011110011111000000")); +MQQ73:TBL_GPR0_ZERO_PT(22) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) & + RF0_INSTR_Q(05) & RF0_INSTR_Q(21) & + RF0_INSTR_Q(22) & RF0_INSTR_Q(24) & + RF0_INSTR_Q(25) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(28) & RF0_INSTR_Q(30) & + RF0_S1_Q(00) & RF0_S1_Q(01) & + RF0_S1_Q(02) & RF0_S1_Q(03) & + RF0_S1_Q(04) & RF0_S1_Q(05) + ) , STD_ULOGIC_VECTOR'("011110000111000000")); +MQQ74:TBL_GPR0_ZERO_PT(23) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) & + RF0_INSTR_Q(05) & RF0_INSTR_Q(21) & + RF0_INSTR_Q(22) & RF0_INSTR_Q(23) & + RF0_INSTR_Q(24) & RF0_INSTR_Q(25) & + RF0_INSTR_Q(26) & RF0_INSTR_Q(27) & + RF0_INSTR_Q(28) & RF0_INSTR_Q(30) & + RF0_S1_Q(00) & RF0_S1_Q(01) & + RF0_S1_Q(02) & RF0_S1_Q(03) & + RF0_S1_Q(04) & RF0_S1_Q(05) + ) , STD_ULOGIC_VECTOR'("01111010101011000000")); +MQQ75:TBL_GPR0_ZERO_PT(24) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) & + RF0_INSTR_Q(05) & RF0_INSTR_Q(21) & + RF0_INSTR_Q(23) & RF0_INSTR_Q(24) & + RF0_INSTR_Q(25) & RF0_INSTR_Q(27) & + RF0_INSTR_Q(28) & RF0_INSTR_Q(29) & + RF0_INSTR_Q(30) & RF0_S1_Q(00) & + RF0_S1_Q(01) & RF0_S1_Q(02) & + RF0_S1_Q(03) & RF0_S1_Q(04) & + RF0_S1_Q(05) ) , STD_ULOGIC_VECTOR'("0111101000110000000")); +MQQ76:TBL_GPR0_ZERO_PT(25) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) & + RF0_INSTR_Q(05) & RF0_INSTR_Q(21) & + RF0_INSTR_Q(22) & RF0_INSTR_Q(24) & + RF0_INSTR_Q(25) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(30) & RF0_S1_Q(00) & + RF0_S1_Q(01) & RF0_S1_Q(02) & + RF0_S1_Q(03) & RF0_S1_Q(04) & + RF0_S1_Q(05) ) , STD_ULOGIC_VECTOR'("0111100101010000000")); +MQQ77:TBL_GPR0_ZERO_PT(26) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) & + RF0_INSTR_Q(05) & RF0_INSTR_Q(21) & + RF0_INSTR_Q(22) & RF0_INSTR_Q(23) & + RF0_INSTR_Q(24) & RF0_INSTR_Q(25) & + RF0_INSTR_Q(26) & RF0_INSTR_Q(27) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) & + RF0_S1_Q(00) & RF0_S1_Q(01) & + RF0_S1_Q(02) & RF0_S1_Q(03) & + RF0_S1_Q(04) & RF0_S1_Q(05) + ) , STD_ULOGIC_VECTOR'("01111000001010000000")); +MQQ78:TBL_GPR0_ZERO_PT(27) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) & + RF0_INSTR_Q(05) & RF0_INSTR_Q(21) & + RF0_INSTR_Q(22) & RF0_INSTR_Q(23) & + RF0_INSTR_Q(24) & RF0_INSTR_Q(25) & + RF0_INSTR_Q(26) & RF0_INSTR_Q(27) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) & + RF0_S1_Q(00) & RF0_S1_Q(01) & + RF0_S1_Q(02) & RF0_S1_Q(03) & + RF0_S1_Q(04) & RF0_S1_Q(05) + ) , STD_ULOGIC_VECTOR'("01111001001011000000")); +MQQ79:TBL_GPR0_ZERO_PT(28) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(05) & RF0_S1_Q(00) & + RF0_S1_Q(01) & RF0_S1_Q(02) & + RF0_S1_Q(03) & RF0_S1_Q(04) & + RF0_S1_Q(05) ) , STD_ULOGIC_VECTOR'("100000000")); +MQQ80:TBL_GPR0_ZERO_PT(29) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) & + RF0_INSTR_Q(05) & RF0_INSTR_Q(21) & + RF0_INSTR_Q(22) & RF0_INSTR_Q(23) & + RF0_INSTR_Q(24) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) & + RF0_S1_Q(00) & RF0_S1_Q(01) & + RF0_S1_Q(02) & RF0_S1_Q(03) & + RF0_S1_Q(04) & RF0_S1_Q(05) + ) , STD_ULOGIC_VECTOR'("01111000010110000000")); +MQQ81:TBL_GPR0_ZERO_PT(30) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) & + RF0_INSTR_Q(05) & RF0_INSTR_Q(31) & + RF0_S1_Q(00) & RF0_S1_Q(01) & + RF0_S1_Q(02) & RF0_S1_Q(03) & + RF0_S1_Q(04) & RF0_S1_Q(05) + ) , STD_ULOGIC_VECTOR'("110100000000")); +MQQ82:TBL_GPR0_ZERO_PT(31) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(30) & RF0_INSTR_Q(31) & + RF0_S1_Q(00) & RF0_S1_Q(01) & + RF0_S1_Q(02) & RF0_S1_Q(03) & + RF0_S1_Q(04) & RF0_S1_Q(05) + ) , STD_ULOGIC_VECTOR'("111000000000")); +MQQ83:TBL_GPR0_ZERO_PT(32) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) & + RF0_INSTR_Q(05) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) & + RF0_S1_Q(00) & RF0_S1_Q(01) & + RF0_S1_Q(02) & RF0_S1_Q(03) & + RF0_S1_Q(04) & RF0_S1_Q(05) + ) , STD_ULOGIC_VECTOR'("0111101111000000")); +MQQ84:TBL_GPR0_ZERO_PT(33) <= + Eq(( RF0_INSTR_Q(01) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) & + RF0_S1_Q(00) & RF0_S1_Q(01) & + RF0_S1_Q(02) & RF0_S1_Q(03) & + RF0_S1_Q(04) & RF0_S1_Q(05) + ) , STD_ULOGIC_VECTOR'("0111000000")); +-- Table TBL_GPR0_ZERO Signal Assignments for Outputs +MQQ85:RF0_GPR0_ZERO <= + (TBL_GPR0_ZERO_PT(1) OR TBL_GPR0_ZERO_PT(2) + OR TBL_GPR0_ZERO_PT(3) OR TBL_GPR0_ZERO_PT(4) + OR TBL_GPR0_ZERO_PT(5) OR TBL_GPR0_ZERO_PT(6) + OR TBL_GPR0_ZERO_PT(7) OR TBL_GPR0_ZERO_PT(8) + OR TBL_GPR0_ZERO_PT(9) OR TBL_GPR0_ZERO_PT(10) + OR TBL_GPR0_ZERO_PT(11) OR TBL_GPR0_ZERO_PT(12) + OR TBL_GPR0_ZERO_PT(13) OR TBL_GPR0_ZERO_PT(14) + OR TBL_GPR0_ZERO_PT(15) OR TBL_GPR0_ZERO_PT(16) + OR TBL_GPR0_ZERO_PT(17) OR TBL_GPR0_ZERO_PT(18) + OR TBL_GPR0_ZERO_PT(19) OR TBL_GPR0_ZERO_PT(20) + OR TBL_GPR0_ZERO_PT(21) OR TBL_GPR0_ZERO_PT(22) + OR TBL_GPR0_ZERO_PT(23) OR TBL_GPR0_ZERO_PT(24) + OR TBL_GPR0_ZERO_PT(25) OR TBL_GPR0_ZERO_PT(26) + OR TBL_GPR0_ZERO_PT(27) OR TBL_GPR0_ZERO_PT(28) + OR TBL_GPR0_ZERO_PT(29) OR TBL_GPR0_ZERO_PT(30) + OR TBL_GPR0_ZERO_PT(31) OR TBL_GPR0_ZERO_PT(32) + OR TBL_GPR0_ZERO_PT(33)); + +-- +-- Final Table Listing +-- *INPUTS*========================*OUTPUTS*===================* +-- | | | +-- | rf0_instr_q | | +-- | | rf0_instr_q | | +-- | | | rf0_instr_q | | +-- | | | | | | +-- | | | | | rf0_use_imm | +-- | 000000 2222222223 33 | | | +-- | 012345 1234567890 01 | | | +-- *TYPE*==========================+===========================+ +-- | PPPPPP PPPPPPPPPP PP | P | +-- *POLARITY*--------------------->| + | +-- *PHASE*------------------------>| T | +-- *TERMS*=========================+===========================+ +-- 1 | 011--1 -0-1101000 -- | 1 | +-- 2 | 011--1 10-1010101 -- | 1 | +-- 3 | 011--1 0010-00011 -- | 1 | +-- 4 | 011--1 0-11010011 -- | 1 | +-- 5 | 011--1 00100100-0 -- | 1 | +-- 6 | 011--1 -011-010-0 -- | 1 | +-- 7 | -0-01- ---------- -- | 1 | +-- 8 | -01--0 ---------- -- | 1 | +-- 9 | 0110-- ---------- -- | 1 | +-- 10 | 0-110- ---------- -- | 1 | +-- 11 | --1010 ---------- -0 | 1 | +-- 12 | 1-1-10 ---------- 0- | 1 | +-- 13 | 10---- ---------- -- | 1 | +-- 14 | 01-0-0 ---------- -- | 1 | +-- 15 | -0--11 ---------- -- | 1 | +-- *===========================================================* +-- +-- Table TBL_USE_IMM Signal Assignments for Product Terms +MQQ86:TBL_USE_IMM_PT(1) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(22) & RF0_INSTR_Q(24) & + RF0_INSTR_Q(25) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(29) & RF0_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("011101101000")); +MQQ87:TBL_USE_IMM_PT(2) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(21) & RF0_INSTR_Q(22) & + RF0_INSTR_Q(24) & RF0_INSTR_Q(25) & + RF0_INSTR_Q(26) & RF0_INSTR_Q(27) & + RF0_INSTR_Q(28) & RF0_INSTR_Q(29) & + RF0_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("0111101010101")); +MQQ88:TBL_USE_IMM_PT(3) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(21) & RF0_INSTR_Q(22) & + RF0_INSTR_Q(23) & RF0_INSTR_Q(24) & + RF0_INSTR_Q(26) & RF0_INSTR_Q(27) & + RF0_INSTR_Q(28) & RF0_INSTR_Q(29) & + RF0_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("0111001000011")); +MQQ89:TBL_USE_IMM_PT(4) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(21) & RF0_INSTR_Q(23) & + RF0_INSTR_Q(24) & RF0_INSTR_Q(25) & + RF0_INSTR_Q(26) & RF0_INSTR_Q(27) & + RF0_INSTR_Q(28) & RF0_INSTR_Q(29) & + RF0_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("0111011010011")); +MQQ90:TBL_USE_IMM_PT(5) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(21) & RF0_INSTR_Q(22) & + RF0_INSTR_Q(23) & RF0_INSTR_Q(24) & + RF0_INSTR_Q(25) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("0111001001000")); +MQQ91:TBL_USE_IMM_PT(6) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(22) & RF0_INSTR_Q(23) & + RF0_INSTR_Q(24) & RF0_INSTR_Q(26) & + RF0_INSTR_Q(27) & RF0_INSTR_Q(28) & + RF0_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("01110110100")); +MQQ92:TBL_USE_IMM_PT(7) <= + Eq(( RF0_INSTR_Q(01) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) ) , STD_ULOGIC_VECTOR'("001")); +MQQ93:TBL_USE_IMM_PT(8) <= + Eq(( RF0_INSTR_Q(01) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(05) ) , STD_ULOGIC_VECTOR'("010")); +MQQ94:TBL_USE_IMM_PT(9) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(02) & RF0_INSTR_Q(03) + ) , STD_ULOGIC_VECTOR'("0110")); +MQQ95:TBL_USE_IMM_PT(10) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(04) + ) , STD_ULOGIC_VECTOR'("0110")); +MQQ96:TBL_USE_IMM_PT(11) <= + Eq(( RF0_INSTR_Q(02) & RF0_INSTR_Q(03) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(31) ) , STD_ULOGIC_VECTOR'("10100")); +MQQ97:TBL_USE_IMM_PT(12) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(02) & + RF0_INSTR_Q(04) & RF0_INSTR_Q(05) & + RF0_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("11100")); +MQQ98:TBL_USE_IMM_PT(13) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) + ) , STD_ULOGIC_VECTOR'("10")); +MQQ99:TBL_USE_IMM_PT(14) <= + Eq(( RF0_INSTR_Q(00) & RF0_INSTR_Q(01) & + RF0_INSTR_Q(03) & RF0_INSTR_Q(05) + ) , STD_ULOGIC_VECTOR'("0100")); +MQQ100:TBL_USE_IMM_PT(15) <= + Eq(( RF0_INSTR_Q(01) & RF0_INSTR_Q(04) & + RF0_INSTR_Q(05) ) , STD_ULOGIC_VECTOR'("011")); +-- Table TBL_USE_IMM Signal Assignments for Outputs +MQQ101:RF0_USE_IMM <= + (TBL_USE_IMM_PT(1) OR TBL_USE_IMM_PT(2) + OR TBL_USE_IMM_PT(3) OR TBL_USE_IMM_PT(4) + OR TBL_USE_IMM_PT(5) OR TBL_USE_IMM_PT(6) + OR TBL_USE_IMM_PT(7) OR TBL_USE_IMM_PT(8) + OR TBL_USE_IMM_PT(9) OR TBL_USE_IMM_PT(10) + OR TBL_USE_IMM_PT(11) OR TBL_USE_IMM_PT(12) + OR TBL_USE_IMM_PT(13) OR TBL_USE_IMM_PT(14) + OR TBL_USE_IMM_PT(15)); + +rf0_axu_instr_type_latch : tri_rlmreg_p + generic map (width => rf0_axu_instr_type_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => is2_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_axu_instr_type_offset to rf0_axu_instr_type_offset + rf0_axu_instr_type_q'length-1), + scout => sov(rf0_axu_instr_type_offset to rf0_axu_instr_type_offset + rf0_axu_instr_type_q'length-1), + din => iu_xu_is2_axu_instr_type , + dout => rf0_axu_instr_type_q); +rf0_axu_ld_or_st_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_axu_ld_or_st_offset), + scout => sov(rf0_axu_ld_or_st_offset), + din => iu_xu_is2_axu_ld_or_st , + dout => rf0_axu_ld_or_st_q); +rf0_axu_ldst_extpid_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => is2_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_axu_ldst_extpid_offset), + scout => sov(rf0_axu_ldst_extpid_offset), + din => iu_xu_is2_axu_ldst_extpid , + dout => rf0_axu_ldst_extpid_q); +rf0_axu_ldst_forcealign_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => is2_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_axu_ldst_forcealign_offset), + scout => sov(rf0_axu_ldst_forcealign_offset), + din => iu_xu_is2_axu_ldst_forcealign, + dout => rf0_axu_ldst_forcealign_q); +rf0_axu_ldst_forceexcept_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => is2_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_axu_ldst_forceexcept_offset), + scout => sov(rf0_axu_ldst_forceexcept_offset), + din => iu_xu_is2_axu_ldst_forceexcept, + dout => rf0_axu_ldst_forceexcept_q); +rf0_axu_ldst_indexed_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => is2_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_axu_ldst_indexed_offset), + scout => sov(rf0_axu_ldst_indexed_offset), + din => iu_xu_is2_axu_ldst_indexed , + dout => rf0_axu_ldst_indexed_q); +rf0_axu_ldst_size_latch : tri_rlmreg_p + generic map (width => rf0_axu_ldst_size_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => is2_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_axu_ldst_size_offset to rf0_axu_ldst_size_offset + rf0_axu_ldst_size_q'length-1), + scout => sov(rf0_axu_ldst_size_offset to rf0_axu_ldst_size_offset + rf0_axu_ldst_size_q'length-1), + din => iu_xu_is2_axu_ldst_size , + dout => rf0_axu_ldst_size_q); +rf0_axu_ldst_tag_latch : tri_rlmreg_p + generic map (width => rf0_axu_ldst_tag_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => is2_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_axu_ldst_tag_offset to rf0_axu_ldst_tag_offset + rf0_axu_ldst_tag_q'length-1), + scout => sov(rf0_axu_ldst_tag_offset to rf0_axu_ldst_tag_offset + rf0_axu_ldst_tag_q'length-1), + din => iu_xu_is2_axu_ldst_tag , + dout => rf0_axu_ldst_tag_q); +rf0_axu_ldst_update_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => is2_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_axu_ldst_update_offset), + scout => sov(rf0_axu_ldst_update_offset), + din => iu_xu_is2_axu_ldst_update , + dout => rf0_axu_ldst_update_q); +rf0_axu_mffgpr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => is2_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_axu_mffgpr_offset), + scout => sov(rf0_axu_mffgpr_offset), + din => iu_xu_is2_axu_mffgpr , + dout => rf0_axu_mffgpr_q); +rf0_axu_mftgpr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => is2_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_axu_mftgpr_offset), + scout => sov(rf0_axu_mftgpr_offset), + din => iu_xu_is2_axu_mftgpr , + dout => rf0_axu_mftgpr_q); +rf0_axu_movedp_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => is2_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_axu_movedp_offset), + scout => sov(rf0_axu_movedp_offset), + din => iu_xu_is2_axu_movedp , + dout => rf0_axu_movedp_q); +rf0_axu_store_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => is2_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_axu_store_offset), + scout => sov(rf0_axu_store_offset), + din => iu_xu_is2_axu_store , + dout => rf0_axu_store_q); +rf0_error_latch : tri_rlmreg_p + generic map (width => rf0_error_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => is2_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_error_offset to rf0_error_offset + rf0_error_q'length-1), + scout => sov(rf0_error_offset to rf0_error_offset + rf0_error_q'length-1), + din => iu_xu_is2_error , + dout => rf0_error_q); +rf0_gshare_latch : tri_rlmreg_p + generic map (width => rf0_gshare_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => is2_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_gshare_offset to rf0_gshare_offset + rf0_gshare_q'length-1), + scout => sov(rf0_gshare_offset to rf0_gshare_offset + rf0_gshare_q'length-1), + din => iu_xu_is2_gshare , + dout => rf0_gshare_q); +rf0_ifar_latch : tri_rlmreg_p + generic map (width => rf0_ifar_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => is2_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_ifar_offset to rf0_ifar_offset + rf0_ifar_q'length-1), + scout => sov(rf0_ifar_offset to rf0_ifar_offset + rf0_ifar_q'length-1), + din => iu_xu_is2_ifar , + dout => rf0_ifar_q); +rf0_instr_latch : tri_rlmreg_p + generic map (width => rf0_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => is2_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_instr_offset to rf0_instr_offset + rf0_instr_q'length-1), + scout => sov(rf0_instr_offset to rf0_instr_offset + rf0_instr_q'length-1), + din => iu_xu_is2_instr , + dout => rf0_instr_q); +rf0_is_ucode_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => is2_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_is_ucode_offset), + scout => sov(rf0_is_ucode_offset), + din => iu_xu_is2_is_ucode , + dout => rf0_is_ucode_q); +rf0_match_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => is2_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_match_offset), + scout => sov(rf0_match_offset), + din => iu_xu_is2_match , + dout => rf0_match_q); +rf0_pred_taken_cnt_latch : tri_rlmreg_p + generic map (width => rf0_pred_taken_cnt_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => is2_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_pred_taken_cnt_offset to rf0_pred_taken_cnt_offset + rf0_pred_taken_cnt_q'length-1), + scout => sov(rf0_pred_taken_cnt_offset to rf0_pred_taken_cnt_offset + rf0_pred_taken_cnt_q'length-1), + din => iu_xu_is2_pred_taken_cnt , + dout => rf0_pred_taken_cnt_q); +rf0_pred_update_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => is2_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_pred_update_offset), + scout => sov(rf0_pred_update_offset), + din => iu_xu_is2_pred_update , + dout => rf0_pred_update_q); +rf0_s1_latch : tri_rlmreg_p + generic map (width => rf0_s1_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => is2_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_s1_offset to rf0_s1_offset + rf0_s1_q'length-1), + scout => sov(rf0_s1_offset to rf0_s1_offset + rf0_s1_q'length-1), + din => iu_xu_is2_s1 , + dout => rf0_s1_q); +rf0_s1_vld_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => is2_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_s1_vld_offset), + scout => sov(rf0_s1_vld_offset), + din => rf0_s1_vld_d, + dout => rf0_s1_vld_q); +rf0_s2_latch : tri_rlmreg_p + generic map (width => rf0_s2_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => is2_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_s2_offset to rf0_s2_offset + rf0_s2_q'length-1), + scout => sov(rf0_s2_offset to rf0_s2_offset + rf0_s2_q'length-1), + din => iu_xu_is2_s2 , + dout => rf0_s2_q); +rf0_s2_vld_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => is2_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_s2_vld_offset), + scout => sov(rf0_s2_vld_offset), + din => rf0_s2_vld_d, + dout => rf0_s2_vld_q); +rf0_s3_latch : tri_rlmreg_p + generic map (width => rf0_s3_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => is2_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_s3_offset to rf0_s3_offset + rf0_s3_q'length-1), + scout => sov(rf0_s3_offset to rf0_s3_offset + rf0_s3_q'length-1), + din => iu_xu_is2_s3 , + dout => rf0_s3_q); +rf0_s3_vld_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => is2_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_s3_vld_offset), + scout => sov(rf0_s3_vld_offset), + din => rf0_s3_vld_d, + dout => rf0_s3_vld_q); +rf0_ta_latch : tri_rlmreg_p + generic map (width => rf0_ta_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => is2_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_ta_offset to rf0_ta_offset + rf0_ta_q'length-1), + scout => sov(rf0_ta_offset to rf0_ta_offset + rf0_ta_q'length-1), + din => iu_xu_is2_ta , + dout => rf0_ta_q); +rf0_ta_vld_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => is2_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_ta_vld_offset), + scout => sov(rf0_ta_vld_offset), + din => rf0_ta_vld_d, + dout => rf0_ta_vld_q); +rf0_tid_latch : tri_rlmreg_p + generic map (width => rf0_tid_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => is2_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_tid_offset to rf0_tid_offset + rf0_tid_q'length-1), + scout => sov(rf0_tid_offset to rf0_tid_offset + rf0_tid_q'length-1), + din => iu_xu_is2_tid , + dout => rf0_tid_q); +rf0_ucode_val_latch : tri_rlmreg_p + generic map (width => rf0_ucode_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_ucode_val_offset to rf0_ucode_val_offset + rf0_ucode_val_q'length-1), + scout => sov(rf0_ucode_val_offset to rf0_ucode_val_offset + rf0_ucode_val_q'length-1), + din => rf0_ucode_val_d, + dout => rf0_ucode_val_q); +rf0_val_latch : tri_rlmreg_p + generic map (width => rf0_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_val_offset to rf0_val_offset + rf0_val_q'length-1), + scout => sov(rf0_val_offset to rf0_val_offset + rf0_val_q'length-1), + din => rf0_val_d, + dout => rf0_val_q); +rf1_barrier_done_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf1_barrier_done_offset), + scout => sov(rf1_barrier_done_offset), + din => rf0_barrier_done, + dout => rf1_barrier_done_q); +rf1_div_coll_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf1_div_coll_offset), + scout => sov(rf1_div_coll_offset), + din => rf1_div_coll_d, + dout => rf1_div_coll_q); +rf1_div_val_latch : tri_rlmreg_p + generic map (width => rf1_div_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf1_div_val_offset to rf1_div_val_offset + rf1_div_val_q'length-1), + scout => sov(rf1_div_val_offset to rf1_div_val_offset + rf1_div_val_q'length-1), + din => rf0_div_val, + dout => rf1_div_val_q); +rf1_mul_valid_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf1_mul_valid_offset), + scout => sov(rf1_mul_valid_offset), + din => rf0_mul_valid, + dout => rf1_mul_valid_q); +rf1_muldiv_coll_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf1_muldiv_coll_offset), + scout => sov(rf1_muldiv_coll_offset), + din => rf0_muldiv_coll, + dout => rf1_muldiv_coll_q); +rf1_multdiv_val_latch : tri_rlmreg_p + generic map (width => rf1_multdiv_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf1_multdiv_val_offset to rf1_multdiv_val_offset + rf1_multdiv_val_q'length-1), + scout => sov(rf1_multdiv_val_offset to rf1_multdiv_val_offset + rf1_multdiv_val_q'length-1), + din => rf0_multdiv_val, + dout => rf1_multdiv_val_q); +rf1_recirc_ctr_latch : tri_rlmreg_p + generic map (width => rf1_recirc_ctr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf1_recirc_ctr_offset to rf1_recirc_ctr_offset + rf1_recirc_ctr_q'length-1), + scout => sov(rf1_recirc_ctr_offset to rf1_recirc_ctr_offset + rf1_recirc_ctr_q'length-1), + din => rf1_recirc_ctr_d, + dout => rf1_recirc_ctr_q); +rf1_recirc_ctr_flush_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf1_recirc_ctr_flush_offset), + scout => sov(rf1_recirc_ctr_flush_offset), + din => rf0_recirc_ctr_flush, + dout => rf1_recirc_ctr_flush_q); +ex1_div_coll_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_div_coll_offset), + scout => sov(ex1_div_coll_offset), + din => ex1_div_coll_d, + dout => ex1_div_coll_q); +ex1_div_val_latch : tri_rlmreg_p + generic map (width => ex1_div_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_div_val_offset to ex1_div_val_offset + ex1_div_val_q'length-1), + scout => sov(ex1_div_val_offset to ex1_div_val_offset + ex1_div_val_q'length-1), + din => ex1_div_val_d, + dout => ex1_div_val_q); +ex1_muldiv_in_use_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_muldiv_in_use_offset), + scout => sov(ex1_muldiv_in_use_offset), + din => rf1_muldiv_in_use , + dout => ex1_muldiv_in_use_q); +ex1_multdiv_val_latch : tri_rlmreg_p + generic map (width => ex1_multdiv_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_multdiv_val_offset to ex1_multdiv_val_offset + ex1_multdiv_val_q'length-1), + scout => sov(ex1_multdiv_val_offset to ex1_multdiv_val_offset + ex1_multdiv_val_q'length-1), + din => ex1_multdiv_val_d, + dout => ex1_multdiv_val_q); +ex1_recirc_ctr_flush_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_recirc_ctr_flush_offset), + scout => sov(ex1_recirc_ctr_flush_offset), + din => rf1_recirc_ctr_flush_q , + dout => ex1_recirc_ctr_flush_q); +ex2_div_coll_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_div_coll_offset), + scout => sov(ex2_div_coll_offset), + din => ex2_div_coll_d, + dout => ex2_div_coll_q); +ex2_div_val_latch : tri_rlmreg_p + generic map (width => ex2_div_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_div_val_offset to ex2_div_val_offset + ex2_div_val_q'length-1), + scout => sov(ex2_div_val_offset to ex2_div_val_offset + ex2_div_val_q'length-1), + din => ex2_div_val_d, + dout => ex2_div_val_q); +ex2_multdiv_val_latch : tri_rlmreg_p + generic map (width => ex2_multdiv_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_multdiv_val_offset to ex2_multdiv_val_offset + ex2_multdiv_val_q'length-1), + scout => sov(ex2_multdiv_val_offset to ex2_multdiv_val_offset + ex2_multdiv_val_q'length-1), + din => ex2_multdiv_val_d, + dout => ex2_multdiv_val_q); +ex3_div_val_latch : tri_rlmreg_p + generic map (width => ex3_div_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_div_val_offset to ex3_div_val_offset + ex3_div_val_q'length-1), + scout => sov(ex3_div_val_offset to ex3_div_val_offset + ex3_div_val_q'length-1), + din => ex3_div_val_d, + dout => ex3_div_val_q); +ex3_multdiv_val_latch : tri_rlmreg_p + generic map (width => ex3_multdiv_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_multdiv_val_offset to ex3_multdiv_val_offset + ex3_multdiv_val_q'length-1), + scout => sov(ex3_multdiv_val_offset to ex3_multdiv_val_offset + ex3_multdiv_val_q'length-1), + din => ex3_multdiv_val_d, + dout => ex3_multdiv_val_q); +ex4_div_val_latch : tri_rlmreg_p + generic map (width => ex4_div_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_div_val_offset to ex4_div_val_offset + ex4_div_val_q'length-1), + scout => sov(ex4_div_val_offset to ex4_div_val_offset + ex4_div_val_q'length-1), + din => ex4_div_val_d, + dout => ex4_div_val_q); +ex5_div_val_latch : tri_rlmreg_p + generic map (width => ex5_div_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_div_val_offset to ex5_div_val_offset + ex5_div_val_q'length-1), + scout => sov(ex5_div_val_offset to ex5_div_val_offset + ex5_div_val_q'length-1), + din => ex5_div_val_d, + dout => ex5_div_val_q); +ex6_div_barr_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_div_barr_val_offset), + scout => sov(ex6_div_barr_val_offset), + din => ex5_div_barr_val , + dout => ex6_div_barr_val_q); +ex6_set_barr_latch : tri_rlmreg_p + generic map (width => ex6_set_barr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_set_barr_offset to ex6_set_barr_offset + ex6_set_barr_q'length-1), + scout => sov(ex6_set_barr_offset to ex6_set_barr_offset + ex6_set_barr_q'length-1), + din => ex5_set_barr, + dout => ex6_set_barr_q); +an_ac_back_inv_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(an_ac_back_inv_offset), + scout => sov(an_ac_back_inv_offset), + din => an_ac_back_inv , + dout => an_ac_back_inv_q); +an_ac_back_inv_addr_latch : tri_rlmreg_p + generic map (width => an_ac_back_inv_addr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => an_ac_back_inv_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(an_ac_back_inv_addr_offset to an_ac_back_inv_addr_offset + an_ac_back_inv_addr_q'length-1), + scout => sov(an_ac_back_inv_addr_offset to an_ac_back_inv_addr_offset + an_ac_back_inv_addr_q'length-1), + din => an_ac_back_inv_addr , + dout => an_ac_back_inv_addr_q); +an_ac_back_inv_target_bit3_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => an_ac_back_inv , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(an_ac_back_inv_target_bit3_offset), + scout => sov(an_ac_back_inv_target_bit3_offset), + din => an_ac_back_inv_target_bit3 , + dout => an_ac_back_inv_target_bit3_q); +back_inv_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(back_inv_val_offset), + scout => sov(back_inv_val_offset), + din => back_inv_val_d, + dout => back_inv_val_q); +coll_tid_latch : tri_rlmreg_p + generic map (width => coll_tid_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(coll_tid_offset to coll_tid_offset + coll_tid_q'length-1), + scout => sov(coll_tid_offset to coll_tid_offset + coll_tid_q'length-1), + din => coll_tid_d, + dout => coll_tid_q); +div_barr_done_latch : tri_rlmreg_p + generic map (width => div_barr_done_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(div_barr_done_offset to div_barr_done_offset + div_barr_done_q'length-1), + scout => sov(div_barr_done_offset to div_barr_done_offset + div_barr_done_q'length-1), + din => div_barr_done_d, + dout => div_barr_done_q); +div_barr_thres_latch : tri_rlmreg_p + generic map (width => div_barr_thres_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(div_barr_thres_offset to div_barr_thres_offset + div_barr_thres_q'length-1), + scout => sov(div_barr_thres_offset to div_barr_thres_offset + div_barr_thres_q'length-1), + din => spr_xucr4_div_barr_thres , + dout => div_barr_thres_q); +div_coll_barr_done_latch : tri_rlmreg_p + generic map (width => div_coll_barr_done_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(div_coll_barr_done_offset to div_coll_barr_done_offset + div_coll_barr_done_q'length-1), + scout => sov(div_coll_barr_done_offset to div_coll_barr_done_offset + div_coll_barr_done_q'length-1), + din => div_coll_barr_done_d, + dout => div_coll_barr_done_q); +hold_divide_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_hold_latch_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(hold_divide_offset), + scout => sov(hold_divide_offset), + din => rf0_divide , + dout => hold_divide_q); +hold_error_latch : tri_rlmreg_p + generic map (width => hold_error_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_hold_latch_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(hold_error_offset to hold_error_offset + hold_error_q'length-1), + scout => sov(hold_error_offset to hold_error_offset + hold_error_q'length-1), + din => hold_error_d, + dout => hold_error_q); +hold_ifar_latch : tri_rlmreg_p + generic map (width => hold_ifar_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_hold_latch_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(hold_ifar_offset to hold_ifar_offset + hold_ifar_q'length-1), + scout => sov(hold_ifar_offset to hold_ifar_offset + hold_ifar_q'length-1), + din => hold_ifar_d, + dout => hold_ifar_q); +hold_instr_latch : tri_rlmreg_p + generic map (width => hold_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_hold_latch_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(hold_instr_offset to hold_instr_offset + hold_instr_q'length-1), + scout => sov(hold_instr_offset to hold_instr_offset + hold_instr_q'length-1), + din => hold_instr_d, + dout => hold_instr_q); +hold_is_ucode_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_hold_latch_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(hold_is_ucode_offset), + scout => sov(hold_is_ucode_offset), + din => hold_is_ucode_d, + dout => hold_is_ucode_q); +hold_match_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_hold_latch_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(hold_match_offset), + scout => sov(hold_match_offset), + din => hold_match_d, + dout => hold_match_q); +hold_s1_latch : tri_rlmreg_p + generic map (width => hold_s1_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_hold_latch_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(hold_s1_offset to hold_s1_offset + hold_s1_q'length-1), + scout => sov(hold_s1_offset to hold_s1_offset + hold_s1_q'length-1), + din => hold_s1_d, + dout => hold_s1_q); +hold_s1_vld_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_hold_latch_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(hold_s1_vld_offset), + scout => sov(hold_s1_vld_offset), + din => hold_s1_vld_d, + dout => hold_s1_vld_q); +hold_s2_latch : tri_rlmreg_p + generic map (width => hold_s2_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_hold_latch_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(hold_s2_offset to hold_s2_offset + hold_s2_q'length-1), + scout => sov(hold_s2_offset to hold_s2_offset + hold_s2_q'length-1), + din => hold_s2_d, + dout => hold_s2_q); +hold_s2_vld_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_hold_latch_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(hold_s2_vld_offset), + scout => sov(hold_s2_vld_offset), + din => hold_s2_vld_d, + dout => hold_s2_vld_q); +hold_s3_latch : tri_rlmreg_p + generic map (width => hold_s3_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_hold_latch_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(hold_s3_offset to hold_s3_offset + hold_s3_q'length-1), + scout => sov(hold_s3_offset to hold_s3_offset + hold_s3_q'length-1), + din => hold_s3_d, + dout => hold_s3_q); +hold_s3_vld_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_hold_latch_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(hold_s3_vld_offset), + scout => sov(hold_s3_vld_offset), + din => hold_s3_vld_d, + dout => hold_s3_vld_q); +hold_ta_latch : tri_rlmreg_p + generic map (width => hold_ta_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_hold_latch_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(hold_ta_offset to hold_ta_offset + hold_ta_q'length-1), + scout => sov(hold_ta_offset to hold_ta_offset + hold_ta_q'length-1), + din => hold_ta_d, + dout => hold_ta_q); +hold_ta_vld_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_hold_latch_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(hold_ta_vld_offset), + scout => sov(hold_ta_vld_offset), + din => hold_ta_vld_d, + dout => hold_ta_vld_q); +hold_tid_latch : tri_rlmreg_p + generic map (width => hold_tid_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_hold_latch_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(hold_tid_offset to hold_tid_offset + hold_tid_q'length-1), + scout => sov(hold_tid_offset to hold_tid_offset + hold_tid_q'length-1), + din => hold_tid_d, + dout => hold_tid_q); +hold_use_imm_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_hold_latch_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(hold_use_imm_offset), + scout => sov(hold_use_imm_offset), + din => hold_use_imm_d, + dout => hold_use_imm_q); +lsu_xu_rel_ta_gpr_latch : tri_rlmreg_p + generic map (width => lsu_xu_rel_ta_gpr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(lsu_xu_rel_ta_gpr_offset to lsu_xu_rel_ta_gpr_offset + lsu_xu_rel_ta_gpr_q'length-1), + scout => sov(lsu_xu_rel_ta_gpr_offset to lsu_xu_rel_ta_gpr_offset + lsu_xu_rel_ta_gpr_q'length-1), + din => lsu_xu_rel_ta_gpr , + dout => lsu_xu_rel_ta_gpr_q); +lsu_xu_rel_wren_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(lsu_xu_rel_wren_offset), + scout => sov(lsu_xu_rel_wren_offset), + din => lsu_xu_rel_wren , + dout => lsu_xu_rel_wren_q); +spare_0_lcb: entity tri.tri_lcbnd(tri_lcbnd) + port map(vd => vdd, + gd => gnd, + act => tidn, + nclk => nclk, + forcee => func_sl_force, + thold_b => func_sl_thold_0_b, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + sg => sg_0, + lclk => spare_0_lclk, + d1clk => spare_0_d1clk, + d2clk => spare_0_d2clk); +spare_0_latch : entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width => spare_0_q'length, expand_type => expand_type, btr => "NLI0001_X2_A12TH", init=>(spare_0_q'range=>'0')) + port map (vd => vdd, gd => gnd, + LCLK => spare_0_lclk, + D1CLK => spare_0_d1clk, + D2CLK => spare_0_d2clk, + SCANIN => siv(spare_0_offset to spare_0_offset + spare_0_q'length-1), + SCANOUT => sov(spare_0_offset to spare_0_offset + spare_0_q'length-1), + D => spare_0_d, + QB => spare_0_q); +spare_0_d <= not spare_0_q; +mark_unused(spare_0_q); +spare_1_lcb: entity tri.tri_lcbnd(tri_lcbnd) + port map(vd => vdd, + gd => gnd, + act => tidn, + nclk => nclk, + forcee => func_sl_force, + thold_b => func_sl_thold_0_b, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + sg => sg_0, + lclk => spare_1_lclk, + d1clk => spare_1_d1clk, + d2clk => spare_1_d2clk); +spare_1_latch : entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width => spare_1_q'length, expand_type => expand_type, btr => "NLI0001_X2_A12TH", init=>(spare_1_q'range=>'0')) + port map (vd => vdd, gd => gnd, + LCLK => spare_1_lclk, + D1CLK => spare_1_d1clk, + D2CLK => spare_1_d2clk, + SCANIN => siv(spare_1_offset to spare_1_offset + spare_1_q'length-1), + SCANOUT => sov(spare_1_offset to spare_1_offset + spare_1_q'length-1), + D => spare_1_d, + QB => spare_1_q); +spare_1_d <= not spare_1_q; +mark_unused(spare_1_q); +siv(0 TO siv'right) <= sov(1 to siv'right) & scan_in; +scan_out <= sov(0); +END XUQ_DEC_A; diff --git a/rel/src/vhdl/work/xuq_dec_b.vhdl b/rel/src/vhdl/work/xuq_dec_b.vhdl new file mode 100644 index 0000000..f48278f --- /dev/null +++ b/rel/src/vhdl/work/xuq_dec_b.vhdl @@ -0,0 +1,8790 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XU_B Decode +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.numeric_std.all; +LIBRARY ibm; +USE ibm.std_ulogic_support.all; +USE ibm.std_ulogic_function_support.all; +LIBRARY support; +USE support.power_logic_pkg.all; +LIBRARY tri; +USE tri.tri_latches_pkg.all; +LIBRARY work; +USE work.xuq_pkg.all; + +entity xuq_dec_b is + generic( + expand_type : integer := 2; + threads : integer := 4; + regmode : integer := 6; + regsize : integer := 64; + cl_size : natural := 6; + real_data_add : integer := 42; + eff_ifar : integer := 62); + port( + nclk : in clk_logic; + + vdd : inout power_logic; + gnd : inout power_logic; + + d_mode_dc : in std_ulogic; + delay_lclkr_dc : in std_ulogic; + mpw1_dc_b : in std_ulogic; + mpw2_dc_b : in std_ulogic; + func_sl_force : in std_ulogic; + func_sl_thold_0_b : in std_ulogic; + func_nsl_force : in std_ulogic; + func_nsl_thold_0_b : in std_ulogic; + func_slp_sl_force : in std_ulogic; + func_slp_sl_thold_0_b : in std_ulogic; + func_slp_nsl_force : in std_ulogic; + func_slp_nsl_thold_0_b : in std_ulogic; + sg_0 : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + slowspr_val_in : in std_ulogic; + slowspr_rw_in : in std_ulogic; + slowspr_etid_in : in std_ulogic_vector(0 to 1); + an_ac_dcr_act : in std_ulogic; + an_ac_dcr_val : in std_ulogic; + an_ac_dcr_read : in std_ulogic; + an_ac_dcr_etid : in std_ulogic_vector(0 to 1); + an_ac_dcr_ack : out std_ulogic; + dec_byp_ex4_dcr_ack : out std_ulogic; + + xu_mm_rf1_is_tlbsxr : out std_ulogic; + mm_xu_mmucr0_0_tlbsel : in std_ulogic_vector(4 to 5); + mm_xu_mmucr0_1_tlbsel : in std_ulogic_vector(4 to 5); + mm_xu_mmucr0_2_tlbsel : in std_ulogic_vector(4 to 5); + mm_xu_mmucr0_3_tlbsel : in std_ulogic_vector(4 to 5); + + fxb_fxa_ex7_we0 : out std_ulogic; + fxb_fxa_ex7_wa0 : out std_ulogic_vector(0 to 7); + + xu_rf1_flush : in std_ulogic_vector(0 to threads-1); + xu_ex1_flush : in std_ulogic_vector(0 to threads-1); + xu_ex2_flush : in std_ulogic_vector(0 to threads-1); + xu_ex3_flush : in std_ulogic_vector(0 to threads-1); + xu_ex4_flush : in std_ulogic_vector(0 to threads-1); + xu_ex5_flush : in std_ulogic_vector(0 to threads-1); + + fxa_fxb_rf0_val : in std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_issued : in std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_ucode_val : in std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_act : in std_ulogic; + fxa_fxb_rf0_instr : in std_ulogic_vector(0 to 31); + fxa_fxb_rf0_tid : in std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_ta_vld : in std_ulogic; + fxa_fxb_rf0_ta : in std_ulogic_vector(0 to 7); + fxa_fxb_rf0_error : in std_ulogic_vector(0 to 2); + fxa_fxb_rf0_match : in std_ulogic; + fxa_fxb_rf0_is_ucode : in std_ulogic; + fxa_fxb_rf0_gshare : in std_ulogic_vector(0 to 3); + fxa_fxb_rf0_ifar : in std_ulogic_vector(62-eff_ifar to 61); + fxa_fxb_rf0_s1_vld : in std_ulogic; + fxa_fxb_rf0_s1 : in std_ulogic_vector(0 to 7); + fxa_fxb_rf0_s2_vld : in std_ulogic; + fxa_fxb_rf0_s2 : in std_ulogic_vector(0 to 7); + fxa_fxb_rf0_s3_vld : in std_ulogic; + fxa_fxb_rf0_s3 : in std_ulogic_vector(0 to 7); + fxa_fxb_rf0_axu_instr_type : in std_ulogic_vector(0 to 2); + fxa_fxb_rf0_axu_ld_or_st : in std_ulogic; + fxa_fxb_rf0_axu_store : in std_ulogic; + fxa_fxb_rf0_axu_ldst_forcealign : in std_ulogic; + fxa_fxb_rf0_axu_ldst_forceexcept : in std_ulogic; + fxa_fxb_rf0_axu_ldst_indexed : in std_ulogic; + fxa_fxb_rf0_axu_ldst_tag : in std_ulogic_vector(0 to 8); + fxa_fxb_rf0_axu_mftgpr : in std_ulogic; + fxa_fxb_rf0_axu_mffgpr : in std_ulogic; + fxa_fxb_rf0_axu_movedp : in std_ulogic; + fxa_fxb_rf0_axu_ldst_size : in std_ulogic_vector(0 to 5); + fxa_fxb_rf0_axu_ldst_update : in std_ulogic; + fxa_fxb_rf0_pred_update : in std_ulogic; + fxa_fxb_rf0_pred_taken_cnt : in std_ulogic_vector(0 to 1); + fxa_fxb_rf0_mc_dep_chk_val : in std_ulogic_vector(0 to threads-1); + fxa_fxb_rf1_muldiv_coll : in std_ulogic; + fxa_fxb_rf0_xu_epid_instr : in std_ulogic; + fxa_fxb_rf0_axu_is_extload : in std_ulogic; + fxa_fxb_rf0_axu_is_extstore : in std_ulogic; + fxa_fxb_rf0_3src_instr : in std_ulogic; + fxa_fxb_rf0_gpr0_zero : in std_ulogic; + fxa_fxb_rf0_use_imm : in std_ulogic; + + alu_dec_ex1_ipb_ba : in std_ulogic_vector(27 to 31); + alu_dec_div_need_hole : in std_ulogic; + + dec_byp_rf1_rs0_sel : out std_ulogic_vector(1 to 9); + dec_byp_rf1_rs1_sel : out std_ulogic_vector(1 to 10); + dec_byp_rf1_rs2_sel : out std_ulogic_vector(1 to 9); + dec_byp_rf1_imm : out std_ulogic_vector(64-regsize to 63); + dec_byp_rf1_instr : out std_ulogic_vector(6 to 25); + dec_byp_rf1_cr_so_update : out std_ulogic_vector(0 to 1); + dec_byp_ex3_val : out std_ulogic_vector(0 to threads-1); + dec_byp_rf1_cr_we : out std_ulogic; + dec_byp_rf1_is_mcrf : out std_ulogic; + dec_byp_rf1_use_crfld0 : out std_ulogic; + dec_byp_rf1_alu_cmp : out std_ulogic; + dec_byp_rf1_is_mtcrf : out std_ulogic; + dec_byp_rf1_is_mtocrf : out std_ulogic; + dec_byp_rf1_byp_val : out std_ulogic_vector(1 to 3); + dec_byp_ex4_is_eratsxr : out std_ulogic; + dec_byp_rf1_ca_used : out std_ulogic; + dec_byp_rf1_ov_used : out std_ulogic; + dec_byp_ex4_dp_instr : out std_ulogic; + dec_byp_ex4_mtdp_val : out std_ulogic; + dec_byp_ex4_mfdp_val : out std_ulogic; + dec_byp_ex4_is_wchkall : out std_ulogic; + dec_byp_ex5_instr : out std_ulogic_vector(12 to 19); + dec_byp_rf0_act : out std_ulogic; + + dec_alu_rf1_act : out std_ulogic; + dec_alu_ex1_act : out std_ulogic; + dec_alu_rf1_sel : out std_ulogic_vector(0 to 3); + dec_alu_rf1_add_rs0_inv : out std_ulogic_vector(64-(2**regmode) to 63); + dec_alu_rf1_add_ci : out std_ulogic; + +dec_alu_rf1_mul_recform : out std_ulogic; +dec_alu_rf1_div_recform : out std_ulogic; +dec_alu_rf1_mul_ret : out std_ulogic; +dec_alu_rf1_mul_sign : out std_ulogic; +dec_alu_rf1_mul_size : out std_ulogic; +dec_alu_rf1_mul_imm : out std_ulogic; +dec_alu_rf1_div_sign : out std_ulogic; +dec_alu_rf1_div_size : out std_ulogic; +dec_alu_rf1_div_extd : out std_ulogic; +dec_alu_rf1_is_cmpl : out std_ulogic; +dec_alu_rf1_tw_cmpsel : out std_ulogic_vector(0 to 5); +dec_alu_ex1_is_cmp : out std_ulogic; +dec_rf1_is_isel : out std_ulogic; +dec_alu_rf1_xer_ov_update : out std_ulogic; +dec_alu_rf1_xer_ca_update : out std_ulogic; +dec_alu_rf1_sh_right : out std_ulogic; +dec_alu_rf1_sh_word : out std_ulogic; +dec_alu_rf1_sgnxtd_byte : out std_ulogic; +dec_alu_rf1_sgnxtd_half : out std_ulogic; +dec_alu_rf1_sgnxtd_wd : out std_ulogic; +dec_alu_rf1_sra_dw : out std_ulogic; +dec_alu_rf1_sra_wd : out std_ulogic; +dec_alu_rf1_chk_shov_dw : out std_ulogic; +dec_alu_rf1_chk_shov_wd : out std_ulogic; +dec_alu_rf1_use_me_ins_hi : out std_ulogic; +dec_alu_rf1_use_me_ins_lo : out std_ulogic; +dec_alu_rf1_use_mb_ins_hi : out std_ulogic; +dec_alu_rf1_use_mb_ins_lo : out std_ulogic; +dec_alu_rf1_use_me_rb_hi : out std_ulogic; +dec_alu_rf1_use_me_rb_lo : out std_ulogic; +dec_alu_rf1_use_mb_rb_hi : out std_ulogic; +dec_alu_rf1_use_mb_rb_lo : out std_ulogic; +dec_alu_rf1_use_rb_amt_hi : out std_ulogic; +dec_alu_rf1_use_rb_amt_lo : out std_ulogic; +dec_alu_rf1_zm_ins : out std_ulogic; +dec_alu_rf1_cr_logical : out std_ulogic; +dec_alu_rf1_cr_log_fcn : out std_ulogic_vector(0 to 3); +dec_alu_rf1_log_fcn : out std_ulogic_vector(0 to 3); +dec_alu_rf1_me_ins_b : out std_ulogic_vector(0 to 5); +dec_alu_rf1_mb_ins : out std_ulogic_vector(0 to 5); +dec_alu_rf1_sh_amt : out std_ulogic_vector(0 to 5); +dec_alu_rf1_mb_gt_me : out std_ulogic; +dec_alu_rf1_select_64bmode : out std_ulogic; +alu_ex3_mul_done : in std_ulogic; +alu_ex2_div_done : in std_ulogic; +dec_rf1_tid : out std_ulogic_vector(0 to threads-1); +dec_ex1_tid : out std_ulogic_vector(0 to threads-1); +dec_ex2_tid : out std_ulogic_vector(0 to threads-1); +dec_ex3_tid : out std_ulogic_vector(0 to threads-1); +dec_ex4_tid : out std_ulogic_vector(0 to threads-1); +dec_ex5_tid : out std_ulogic_vector(0 to threads-1); +dec_byp_ex1_spr_sel : out std_ulogic; +dec_byp_ex4_is_mfcr : out std_ulogic; +dec_byp_ex3_tlb_sel : out std_ulogic_vector(0 to 1); +dec_spr_ex1_is_mtspr : out std_ulogic; +dec_spr_ex1_is_mfspr : out std_ulogic; +dec_cpl_rf1_val : out std_ulogic_vector(0 to threads-1); +dec_cpl_rf1_issued : out std_ulogic_vector(0 to threads-1); +dec_spr_rf1_val : out std_ulogic_vector(0 to threads-1); +dec_spr_ex4_val : out std_ulogic_vector(0 to threads-1); +dec_cpl_rf1_instr : out std_ulogic_vector(0 to 31); +dec_fspr_ex1_instr : out std_ulogic_vector(11 to 20); +dec_fspr_ex6_val : out std_ulogic_vector(0 to threads-1); +dec_cpl_rf1_ifar : out std_ulogic_vector(62-eff_ifar to 61); +dec_cpl_rf1_pred_taken_cnt : out std_ulogic; +dec_cpl_rf1_ucode_val : out std_ulogic_vector(0 to threads-1); +dec_cpl_ex2_error : out std_ulogic_vector(0 to 2); +dec_cpl_ex2_match : out std_ulogic; +dec_cpl_ex2_is_ucode : out std_ulogic; +dec_cpl_ex3_is_any_store : out std_ulogic; +ex2_is_any_load_dac : out std_ulogic; +ex2_is_any_store_dac : out std_ulogic; +dec_cpl_ex3_mtdp_nr : out std_ulogic; +dec_cpl_ex3_instr_priv : out std_ulogic; +dec_cpl_ex3_mult_coll : out std_ulogic; +dec_cpl_ex3_tlb_illeg : out std_ulogic; +dec_cpl_ex3_axu_instr_type : out std_ulogic_vector(0 to 2); +dec_cpl_ex3_instr_hypv : out std_ulogic; +dec_cpl_ex1_epid_instr : out std_ulogic; +dec_cpl_ex2_illegal_op : out std_ulogic; +dec_cpl_ex1_is_slowspr_wr : out std_ulogic; +dec_cpl_ex3_ddmh_en : out std_ulogic; +dec_cpl_ex3_back_inv : out std_ulogic; +xu_lsu_rf0_act : out std_ulogic; +xu_lsu_rf1_cache_acc : out std_ulogic; +xu_lsu_rf1_axu_op_val : out std_ulogic; +xu_lsu_rf1_axu_ldst_falign : out std_ulogic; +xu_lsu_rf1_axu_ldst_fexcpt : out std_ulogic; +xu_lsu_rf1_thrd_id : out std_ulogic_vector(0 to 3); +xu_lsu_rf1_optype1 : out std_ulogic; +xu_lsu_rf1_optype2 : out std_ulogic; +xu_lsu_rf1_optype4 : out std_ulogic; +xu_lsu_rf1_optype8 : out std_ulogic; +xu_lsu_rf1_optype16 : out std_ulogic; +xu_lsu_rf1_optype32 : out std_ulogic; +xu_lsu_rf1_target_gpr : out std_ulogic_vector(0 to 8); +xu_lsu_rf1_load_instr : out std_ulogic; +xu_lsu_rf1_store_instr : out std_ulogic; +xu_lsu_rf1_dcbf_instr : out std_ulogic; +xu_lsu_rf1_sync_instr : out std_ulogic; +xu_lsu_rf1_mbar_instr : out std_ulogic; +xu_lsu_rf1_l_fld : out std_ulogic_vector(0 to 1); +xu_lsu_rf1_dcbi_instr : out std_ulogic; +xu_lsu_rf1_dcbz_instr : out std_ulogic; +xu_lsu_rf1_dcbt_instr : out std_ulogic; +xu_lsu_rf1_dcbtst_instr : out std_ulogic; +xu_lsu_rf1_th_fld : out std_ulogic_vector(0 to 4); +xu_lsu_rf1_dcbtls_instr : out std_ulogic; +xu_lsu_rf1_dcbtstls_instr : out std_ulogic; +xu_lsu_rf1_dcblc_instr : out std_ulogic; +xu_lsu_rf1_dcbst_instr : out std_ulogic; +xu_lsu_rf1_icbi_instr : out std_ulogic; +xu_lsu_rf1_icblc_instr : out std_ulogic; +xu_lsu_rf1_icbt_instr : out std_ulogic; +xu_lsu_rf1_icbtls_instr : out std_ulogic; +xu_lsu_rf1_tlbsync_instr : out std_ulogic; +xu_lsu_rf1_lock_instr : out std_ulogic; +xu_lsu_rf1_mutex_hint : out std_ulogic; +xu_lsu_rf1_algebraic : out std_ulogic; +xu_lsu_rf1_byte_rev : out std_ulogic; +xu_lsu_rf1_src_gpr : out std_ulogic; +xu_lsu_rf1_src_axu : out std_ulogic; +xu_lsu_rf1_src_dp : out std_ulogic; +xu_lsu_rf1_targ_gpr : out std_ulogic; +xu_lsu_rf1_targ_axu : out std_ulogic; +xu_lsu_rf1_targ_dp : out std_ulogic; +xu_lsu_ex1_rotsel_ovrd : out std_ulogic_vector(0 to 4); +lsu_xu_ex5_wren : in std_ulogic; +lsu_xu_rel_wren : in std_ulogic; +lsu_xu_rel_ta_gpr : in std_ulogic_vector(0 to 7); +lsu_xu_need_hole : in std_ulogic; +xu_lsu_rf1_src0_vld : out std_ulogic; +xu_lsu_rf1_src0_reg : out std_ulogic_vector(0 to 7); +xu_lsu_rf1_src1_vld : out std_ulogic; +xu_lsu_rf1_src1_reg : out std_ulogic_vector(0 to 7); +xu_lsu_rf1_targ_vld : out std_ulogic; +xu_lsu_rf1_targ_reg : out std_ulogic_vector(0 to 7); +xu_bx_ex1_mtdp_val : out std_ulogic; +xu_bx_ex1_mfdp_val : out std_ulogic; +xu_bx_ex1_ipc_thrd : out std_ulogic_vector(0 to 1); +xu_bx_ex2_ipc_ba : out std_ulogic_vector(0 to 4); +xu_bx_ex2_ipc_sz : out std_ulogic_vector(0 to 1); +xu_lsu_rf1_is_touch : out std_ulogic; +xu_lsu_rf1_is_msgsnd : out std_ulogic; +xu_lsu_rf1_dci_instr : out std_ulogic; +xu_lsu_rf1_ici_instr : out std_ulogic; +xu_lsu_rf1_icswx_instr : out std_ulogic; +xu_lsu_rf1_icswx_dot_instr : out std_ulogic; +xu_lsu_rf1_icswx_epid : out std_ulogic; +xu_lsu_rf1_ldawx_instr : out std_ulogic; +xu_lsu_rf1_wclr_instr : out std_ulogic; +xu_lsu_rf1_wchk_instr : out std_ulogic; +xu_lsu_rf1_derat_ra_eq_ea : out std_ulogic; +xu_lsu_rf1_cmd_act : out std_ulogic; +xu_lsu_rf1_data_act : out std_ulogic; +xu_lsu_rf1_mtspr_trace : out std_ulogic; +xu_iu_rf1_val : out std_ulogic_vector(0 to threads-1); +xu_rf1_val : out std_ulogic_vector(0 to threads-1); +xu_rf1_is_tlbre : out std_ulogic; +xu_rf1_is_tlbwe : out std_ulogic; +xu_rf1_is_tlbsx : out std_ulogic; +xu_rf1_is_tlbsrx : out std_ulogic; +xu_rf1_is_tlbivax : out std_ulogic; +xu_rf1_is_tlbilx : out std_ulogic; +xu_rf1_is_eratre : out std_ulogic; +xu_rf1_is_eratwe : out std_ulogic; +xu_rf1_is_eratsx : out std_ulogic; +xu_rf1_is_eratsrx : out std_ulogic; +xu_rf1_is_erativax : out std_ulogic; +xu_rf1_is_eratilx : out std_ulogic; +xu_ex1_is_isync : out std_ulogic; +xu_ex1_is_csync : out std_ulogic; +xu_lsu_rf1_derat_act : out std_ulogic; +xu_lsu_rf1_derat_is_load : out std_ulogic; +xu_lsu_rf1_derat_is_store : out std_ulogic; +xu_rf1_ws : out std_ulogic_vector(0 to 1); +xu_rf1_t : out std_ulogic_vector(0 to 2); +lsu_xu_is2_back_inv : in std_ulogic; +lsu_xu_is2_back_inv_addr : in std_ulogic_vector(64-real_data_add to 63-cl_size); +byp_dec_rf1_xer_ca : in std_ulogic; +spr_dec_rf1_msr_ucle : in std_ulogic_vector(0 to threads-1); +spr_dec_rf1_msrp_uclep : in std_ulogic_vector(0 to threads-1); +spr_dec_rf1_epcr_dgtmi : in std_ulogic_vector(0 to threads-1); +spr_dec_spr_xucr0_ssdly : in std_ulogic_vector(0 to 4); +byp_xer_si : in std_ulogic_vector(0 to 7*threads-1); +xu_iu_ex6_pri : out std_ulogic_vector(0 to 2); +xu_iu_ex6_pri_val : out std_ulogic_vector(0 to 3); +xu_iu_need_hole : out std_ulogic; +fxb_fxa_ex6_clear_barrier : out std_ulogic_vector(0 to threads-1); +xu_iu_ex5_gshare : out std_ulogic_vector(0 to 3); +xu_iu_ex5_getNIA : out std_ulogic; +xu_iu_ex5_val : out std_ulogic; +xu_iu_ex5_tid : out std_ulogic_vector(0 to threads-1); +xu_iu_ex5_br_update : out std_ulogic; +xu_iu_ex5_br_hist : out std_ulogic_vector(0 to 1); +xu_iu_ex5_bclr : out std_ulogic; +xu_iu_ex5_lk : out std_ulogic; +xu_iu_ex5_bh : out std_ulogic_vector(0 to 1); +pc_xu_trace_bus_enable : in std_ulogic; +pc_xu_instr_trace_mode : in std_ulogic; +pc_xu_instr_trace_tid : in std_ulogic_vector(0 to 1); +dec_byp_ex3_instr_trace_val : out std_ulogic; +dec_byp_ex3_instr_trace_gate : out std_ulogic; +dec_cpl_rf1_instr_trace_val : out std_ulogic; +dec_cpl_rf1_instr_trace_type : out std_ulogic_vector(0 to 1); +dec_cpl_ex3_instr_trace_val : out std_ulogic; +xu_lsu_ex2_instr_trace_val : out std_ulogic; +cpl_dec_in_ucode : in std_ulogic_vector(0 to threads-1); +spr_bit_act : in std_ulogic; +spr_msr_cm : in std_ulogic_vector(0 to threads-1); +spr_ccr2_notlb : in std_ulogic; +spr_ccr2_en_attn : in std_ulogic; +spr_ccr2_en_ditc : in std_ulogic; +spr_ccr2_en_pc : in std_ulogic; +spr_ccr2_en_icswx : in std_ulogic; +spr_ccr2_en_dcr : in std_ulogic; +spr_xucr0_clkg_ctl : in std_ulogic_vector(2 to 2); +byp_grp3_debug : out std_ulogic_vector(0 to 14); +byp_grp4_debug : out std_ulogic_vector(0 to 13); +byp_grp5_debug : out std_ulogic_vector(0 to 14); +dec_grp0_debug : out std_ulogic_vector(0 to 87); +dec_grp1_debug : out std_ulogic_vector(0 to 87) + ); +end xuq_dec_b; +ARCHITECTURE XUQ_DEC_B + OF XUQ_DEC_B + IS +--@@ Signal Declarations +SIGNAL TBL_LD_ST_DEC_PT : STD_ULOGIC_VECTOR(1 TO 77) := +(OTHERS=> 'U'); +SIGNAL TBL_MASTER_DEC_PT : STD_ULOGIC_VECTOR(1 TO 97) := +(OTHERS=> 'U'); +SIGNAL TBL_PRI_CHANGE_PT : STD_ULOGIC_VECTOR(1 TO 7) := +(OTHERS=> 'U'); +SIGNAL TBL_RECFORM_DEC_PT : STD_ULOGIC_VECTOR(1 TO 29) := +(OTHERS=> 'U'); +SIGNAL TBL_VAL_STG_GATE_PT : STD_ULOGIC_VECTOR(1 TO 47) := +(OTHERS=> 'U'); +SIGNAL TBL_XER_DEC_PT : STD_ULOGIC_VECTOR(1 TO 37) := +(OTHERS=> 'U'); +subtype s2 is std_ulogic_vector(0 to 1); +subtype s3 is std_ulogic_vector(0 to 2); +signal is1_need_hole_q, is1_need_hole_d : std_ulogic; +signal is2_need_hole_q, is2_need_hole_d : std_ulogic; +signal rf0_back_inv_q : std_ulogic; +signal rf0_back_inv_addr_q : std_ulogic_vector(64-real_data_add to 63-cl_size); +signal rf0_need_hole_q : std_ulogic; +signal rf1_3src_instr_q : std_ulogic; +signal rf1_act_q, rf0_act : std_ulogic; +signal rf1_axu_instr_type_q : std_ulogic_vector(0 to 2); +signal rf1_axu_is_extload_q : std_ulogic; +signal rf1_axu_is_extstore_q : std_ulogic; +signal rf1_axu_ld_or_st_q : std_ulogic; +signal rf1_axu_ldst_forcealign_q : std_ulogic; +signal rf1_axu_ldst_forceexcept_q : std_ulogic; +signal rf1_axu_ldst_indexed_q : std_ulogic; +signal rf1_axu_ldst_size_q : std_ulogic_vector(0 to 5); +signal rf1_axu_ldst_tag_q : std_ulogic_vector(0 to 8); +signal rf1_axu_ldst_update_q : std_ulogic; +signal rf1_axu_mffgpr_q : std_ulogic; +signal rf1_axu_mftgpr_q : std_ulogic; +signal rf1_axu_movedp_q : std_ulogic; +signal rf1_axu_store_q : std_ulogic; +signal rf1_back_inv_q : std_ulogic; +signal rf1_back_inv_addr_q : std_ulogic_vector(64-real_data_add to 63-cl_size); +signal rf1_error_q : std_ulogic_vector(0 to 2); +signal rf1_gpr0_zero_q : std_ulogic; +signal rf1_gshare_q : std_ulogic_vector(0 to 3); +signal rf1_ifar_q : std_ulogic_vector(62-eff_ifar to 61); +signal rf1_instr_q : std_ulogic_vector(0 to 31); +signal rf1_instr_21to30_00_q, rf1_instr_21to30_00_d : std_ulogic_vector(21 to 30); +signal rf1_instr_21to30_01_q, rf1_instr_21to30_01_d : std_ulogic_vector(21 to 30); +signal rf1_instr_21to30_02_q, rf1_instr_21to30_02_d : std_ulogic_vector(21 to 30); +signal rf1_instr_21to30_03_q, rf1_instr_21to30_03_d : std_ulogic_vector(21 to 30); +signal rf1_instr_21to30_04_q, rf1_instr_21to30_04_d : std_ulogic_vector(21 to 30); +signal rf1_instr_21to30_05_q, rf1_instr_21to30_05_d : std_ulogic_vector(21 to 30); +signal rf1_instr_21to30_06_q, rf1_instr_21to30_06_d : std_ulogic_vector(21 to 30); +signal rf1_instr_21to30_07_q, rf1_instr_21to30_07_d : std_ulogic_vector(21 to 30); +signal rf1_instr_21to30_08_q, rf1_instr_21to30_08_d : std_ulogic_vector(21 to 30); +signal rf1_instr_21to30_09_q, rf1_instr_21to30_09_d : std_ulogic_vector(21 to 30); +signal rf1_instr_21to30_10_q, rf1_instr_21to30_10_d : std_ulogic_vector(21 to 30); +signal rf1_is_isel_q, rf1_is_isel_d : std_ulogic; +signal rf1_is_ucode_q : std_ulogic; +signal rf1_issued_q : std_ulogic_vector(0 to threads-1); +signal rf1_match_q : std_ulogic; +signal rf1_mc_dep_chk_val_q, rf1_mc_dep_chk_val_d : std_ulogic_vector(0 to threads-1); +signal rf1_need_hole_q : std_ulogic; +signal rf1_opcode_is_31_q, rf1_opcode_is_31_d : std_ulogic_vector(0 to 9); +signal rf1_pred_taken_cnt_q : std_ulogic_vector(0 to 1); +signal rf1_pred_update_q : std_ulogic; +signal rf1_s1_q : std_ulogic_vector(0 to 7); +signal rf1_s1_vld_q : std_ulogic; +signal rf1_s2_q : std_ulogic_vector(0 to 7); +signal rf1_s2_vld_q : std_ulogic; +signal rf1_s3_q : std_ulogic_vector(0 to 7); +signal rf1_s3_vld_q : std_ulogic; +signal rf1_ta_q : std_ulogic_vector(0 to 7); +signal rf1_ta_vld_q : std_ulogic; +signal rf1_tid_q : std_ulogic_vector(0 to threads-1); +signal rf1_tid_2_q : std_ulogic_vector(0 to threads-1); +signal rf1_ucode_val_q : std_ulogic_vector(0 to threads-1); +signal rf1_use_imm_q : std_ulogic; +signal rf1_val_q : std_ulogic_vector(0 to threads-1); +signal rf1_val_iu_q : std_ulogic_vector(0 to threads-1); +signal rf1_xu_epid_instr_q : std_ulogic; +signal ex1_act_q, ex1_act_d : std_ulogic; +signal ex1_axu_instr_type_q, ex1_axu_instr_type_d : std_ulogic_vector(0 to 2); +signal ex1_axu_movedp_q : std_ulogic; +signal ex1_back_inv_q : std_ulogic; +signal ex1_bh_q : std_ulogic_vector(0 to 1); +signal ex1_clear_barrier_q : std_ulogic; +signal ex1_ddmh_en_q, ex1_ddmh_en_d : std_ulogic; +signal ex1_ditc_illeg_q, ex1_ditc_illeg_d : std_ulogic; +signal ex1_dp_indexed_q, ex1_dp_indexed_d : std_ulogic; +signal ex1_epid_instr_q, ex1_epid_instr_d : std_ulogic; +signal ex1_error_q : std_ulogic_vector(0 to 2); +signal ex1_getNIA_q : std_ulogic; +signal ex1_gpr_we_q, ex1_gpr_we_d : std_ulogic; +signal ex1_gshare_q : std_ulogic_vector(0 to 3); +signal ex1_instr_q : std_ulogic_vector(11 to 25); +signal ex1_instr_hypv_q : std_ulogic; +signal ex1_instr_priv_q : std_ulogic; +signal ex1_is_any_load_dac_q : std_ulogic; +signal ex1_is_any_store_q : std_ulogic; +signal ex1_is_any_store_dac_q : std_ulogic; +signal ex1_is_attn_q : std_ulogic; +signal ex1_is_bclr_q : std_ulogic; +signal ex1_is_cmp_q : std_ulogic; +signal ex1_is_csync_q, rf1_is_csync : std_ulogic; +signal ex1_is_eratsxr_q : std_ulogic; +signal ex1_is_icswx_q, ex1_is_icswx_d : std_ulogic; +signal ex1_is_isync_q : std_ulogic; +signal ex1_is_ld_w_update_q : std_ulogic; +signal ex1_is_lmw_q : std_ulogic; +signal ex1_is_lswi_q : std_ulogic; +signal ex1_is_lswx_q : std_ulogic; +signal ex1_is_mfcr_q : std_ulogic; +signal ex1_is_mfspr_q : std_ulogic; +signal ex1_is_msgclr_q : std_ulogic; +signal ex1_is_msgsnd_q : std_ulogic; +signal ex1_is_mtspr_q : std_ulogic; +signal ex1_is_sc_q : std_ulogic; +signal ex1_is_st_w_update_q : std_ulogic; +signal ex1_is_ucode_q : std_ulogic; +signal ex1_is_wchkall_q : std_ulogic; +signal ex1_lk_q : std_ulogic; +signal ex1_match_q : std_ulogic; +signal ex1_mfdcr_instr_q, rf1_mfdcr_instr : std_ulogic; +signal ex1_mfdp_val_q, ex1_mfdp_val_d : std_ulogic; +signal ex1_mtdcr_instr_q, rf1_mtdcr_instr : std_ulogic; +signal ex1_mtdp_nr_q, ex1_mtdp_nr_d : std_ulogic; +signal ex1_mtdp_val_q, ex1_mtdp_val_d : std_ulogic; +signal ex1_muldiv_coll_q : std_ulogic; +signal ex1_need_hole_q : std_ulogic; +signal ex1_num_regs_q, ex1_num_regs_d : std_ulogic_vector(0 to 5); +signal ex1_ovr_rotsel_q, ex1_ovr_rotsel_d : std_ulogic; +signal ex1_pred_taken_cnt_q : std_ulogic_vector(0 to 1); +signal ex1_pred_update_q : std_ulogic; +signal ex1_pri_q : std_ulogic_vector(0 to 2); +signal ex1_rotsel_ovrd_q, ex1_rotsel_ovrd_d : std_ulogic_vector(0 to 4); +signal ex1_s1_q : std_ulogic_vector(0 to 7); +signal ex1_s2_q : std_ulogic_vector(0 to 7); +signal ex1_s3_q : std_ulogic_vector(0 to 7); +signal ex1_spr_sel_q : std_ulogic; +signal ex1_ta_q : std_ulogic_vector(0 to 7); +signal ex1_tid_q : std_ulogic_vector(0 to threads-1); +signal ex1_tlb_data_val_q, ex1_tlb_data_val_d : std_ulogic; +signal ex1_tlb_illeg_q, ex1_tlb_illeg_d : std_ulogic; +signal ex1_trace_type_q, rf1_trace_type : std_ulogic_vector(0 to 1); +signal ex1_trace_val_q, rf1_trace_val : std_ulogic; +signal ex1_val_q, ex1_val_d : std_ulogic_vector(0 to threads-1); +signal ex1_axu_ld_or_st_q : std_ulogic; +signal ex2_act_q, ex2_act_d : std_ulogic; +signal ex2_axu_instr_type_q : std_ulogic_vector(0 to 2); +signal ex2_back_inv_q : std_ulogic; +signal ex2_bh_q : std_ulogic_vector(0 to 1); +signal ex2_clear_barrier_q : std_ulogic; +signal ex2_ddmh_en_q : std_ulogic; +signal ex2_ditc_illeg_q, ex2_ditc_illeg_d : std_ulogic; +signal ex2_error_q : std_ulogic_vector(0 to 2); +signal ex2_getNIA_q : std_ulogic; +signal ex2_gpr_we_q, ex2_gpr_we_d : std_ulogic; +signal ex2_gshare_q : std_ulogic_vector(0 to 3); +signal ex2_instr_q : std_ulogic_vector(12 to 25); +signal ex2_instr_hypv_q : std_ulogic; +signal ex2_instr_priv_q : std_ulogic; +signal ex2_ipb_ba_q, ex2_ipb_ba_d : std_ulogic_vector(0 to 4); +signal ex2_ipb_sz_q, ex2_ipb_sz_d : std_ulogic_vector(0 to 1); +signal ex2_is_any_load_dac_q : std_ulogic; +signal ex2_is_any_store_q : std_ulogic; +signal ex2_is_any_store_dac_q : std_ulogic; +signal ex2_is_attn_q : std_ulogic; +signal ex2_is_bclr_q : std_ulogic; +signal ex2_is_eratsxr_q : std_ulogic; +signal ex2_is_icswx_q : std_ulogic; +signal ex2_is_ld_w_update_q : std_ulogic; +signal ex2_is_lmw_q : std_ulogic; +signal ex2_is_lswi_q : std_ulogic; +signal ex2_is_lswx_q : std_ulogic; +signal ex2_is_mfcr_q : std_ulogic; +signal ex2_is_msgclr_q : std_ulogic; +signal ex2_is_msgsnd_q : std_ulogic; +signal ex2_is_sc_q : std_ulogic; +signal ex2_is_st_w_update_q : std_ulogic; +signal ex2_is_ucode_q : std_ulogic; +signal ex2_is_wchkall_q : std_ulogic; +signal ex2_lk_q : std_ulogic; +signal ex2_match_q : std_ulogic; +signal ex2_mfdp_val_q : std_ulogic; +signal ex2_mtdp_nr_q : std_ulogic; +signal ex2_mtdp_val_q : std_ulogic; +signal ex2_muldiv_coll_q : std_ulogic; +signal ex2_need_hole_q : std_ulogic; +signal ex2_pred_taken_cnt_q : std_ulogic_vector(0 to 1); +signal ex2_pred_update_q : std_ulogic; +signal ex2_pri_q : std_ulogic_vector(0 to 2); +signal ex2_ra_eq_rt_q, ex2_ra_eq_rt_d : std_ulogic; +signal ex2_ra_eq_zero_q, ex2_ra_eq_zero_d : std_ulogic; +signal ex2_ra_in_rng_lmw_q, ex2_ra_in_rng_lmw_d : std_ulogic; +signal ex2_ra_in_rng_nowrap_q, ex2_ra_in_rng_nowrap_d : std_ulogic; +signal ex2_ra_in_rng_wrap_q, ex2_ra_in_rng_wrap_d : std_ulogic; +signal ex2_range_wrap_q, ex2_range_wrap_d : std_ulogic; +signal ex2_rb_eq_rt_q, ex2_rb_eq_rt_d : std_ulogic; +signal ex2_rb_in_rng_nowrap_q, ex2_rb_in_rng_nowrap_d : std_ulogic; +signal ex2_rb_in_rng_wrap_q, ex2_rb_in_rng_wrap_d : std_ulogic; +signal ex2_slowspr_dcr_rd_q, ex1_slowspr_dcr_rd : std_ulogic; +signal ex2_ta_q : std_ulogic_vector(0 to 7); +signal ex2_tid_q : std_ulogic_vector(0 to threads-1); +signal ex2_tlb_data_val_q : std_ulogic; +signal ex2_tlb_illeg_q : std_ulogic; +signal ex2_trace_type_q : std_ulogic_vector(0 to 1); +signal ex2_trace_val_q : std_ulogic; +signal ex2_val_q, ex2_val_d : std_ulogic_vector(0 to threads-1); +signal ex3_act_q, ex3_act_d : std_ulogic; +signal ex3_axu_instr_type_q : std_ulogic_vector(0 to 2); +signal ex3_back_inv_q : std_ulogic; +signal ex3_bh_q : std_ulogic_vector(0 to 1); +signal ex3_clear_barrier_q : std_ulogic; +signal ex3_ddmh_en_q : std_ulogic; +signal ex3_div_done_q : std_ulogic; +signal ex3_getNIA_q : std_ulogic; +signal ex3_gpr_we_q : std_ulogic; +signal ex3_gshare_q : std_ulogic_vector(0 to 3); +signal ex3_instr_q : std_ulogic_vector(12 to 19); +signal ex3_instr_hypv_q : std_ulogic; +signal ex3_instr_priv_q : std_ulogic; +signal ex3_is_any_store_q : std_ulogic; +signal ex3_is_bclr_q : std_ulogic; +signal ex3_is_eratsxr_q : std_ulogic; +signal ex3_is_mfcr_q : std_ulogic; +signal ex3_is_wchkall_q : std_ulogic; +signal ex3_lk_q : std_ulogic; +signal ex3_mfdp_val_q : std_ulogic; +signal ex3_mtdp_nr_q : std_ulogic; +signal ex3_mtdp_val_q : std_ulogic; +signal ex3_muldiv_coll_q : std_ulogic; +signal ex3_need_hole_q : std_ulogic; +signal ex3_pred_taken_cnt_q : std_ulogic_vector(0 to 1); +signal ex3_pred_update_q : std_ulogic; +signal ex3_pri_q : std_ulogic_vector(0 to 2); +signal ex3_slowspr_dcr_rd_q : std_ulogic; +signal ex3_ta_q : std_ulogic_vector(0 to 7); +signal ex3_tid_q : std_ulogic_vector(0 to threads-1); +signal ex3_tlb_data_val_q : std_ulogic; +signal ex3_tlb_illeg_q : std_ulogic; +signal ex3_trace_type_q : std_ulogic_vector(0 to 1); +signal ex3_trace_val_q : std_ulogic; +signal ex3_val_q, ex3_val_d : std_ulogic_vector(0 to threads-1); +signal ex4_act_q, ex4_act_d : std_ulogic; +signal ex4_bh_q : std_ulogic_vector(0 to 1); +signal ex4_clear_barrier_q : std_ulogic; +signal ex4_dp_instr_q, ex4_dp_instr_d : std_ulogic; +signal ex4_getNIA_q : std_ulogic; +signal ex4_gpr_we_q, ex4_gpr_we_d : std_ulogic; +signal ex4_gshare_q : std_ulogic_vector(0 to 3); +signal ex4_instr_q : std_ulogic_vector(12 to 19); +signal ex4_is_bclr_q : std_ulogic; +signal ex4_is_eratsxr_q : std_ulogic; +signal ex4_is_mfcr_q : std_ulogic; +signal ex4_is_wchkall_q : std_ulogic; +signal ex4_lk_q : std_ulogic; +signal ex4_mfdp_val_q : std_ulogic; +signal ex4_mtdp_val_q : std_ulogic; +signal ex4_pred_taken_cnt_q : std_ulogic_vector(0 to 1); +signal ex4_pred_update_q : std_ulogic; +signal ex4_pri_q : std_ulogic_vector(0 to 2); +signal ex4_slowspr_dcr_rd_q : std_ulogic; +signal ex4_ta_q : std_ulogic_vector(0 to 7); +signal ex4_tid_q : std_ulogic_vector(0 to threads-1); +signal ex4_val_q, ex4_val_d : std_ulogic_vector(0 to threads-1); +signal ex5_act_q, ex5_act_d : std_ulogic; +signal ex5_bh_q : std_ulogic_vector(0 to 1); +signal ex5_clear_barrier_q : std_ulogic; +signal ex5_getNIA_q : std_ulogic; +signal ex5_gpr_we_q, ex5_gpr_we_d : std_ulogic; +signal ex5_gshare_q : std_ulogic_vector(0 to 3); +signal ex5_instr_q : std_ulogic_vector(12 to 19); +signal ex5_is_bclr_q : std_ulogic; +signal ex5_lk_q : std_ulogic; +signal ex5_pred_taken_cnt_q : std_ulogic_vector(0 to 1); +signal ex5_pred_update_q : std_ulogic; +signal ex5_pri_q : std_ulogic_vector(0 to 2); +signal ex5_slowspr_dcr_rd_q, ex5_slowspr_dcr_rd_d : std_ulogic_vector(0 to threads-1); +signal ex5_ta_q : std_ulogic_vector(0 to 7); +signal ex5_tid_q : std_ulogic_vector(0 to threads-1); +signal ex5_val_q, ex5_val_d : std_ulogic_vector(0 to threads-1); +signal ex6_clear_barrier_q, ex6_clear_barrier_d : std_ulogic_vector(0 to threads-1); +signal ex6_gpr_we_q, ex6_gpr_we_d : std_ulogic; +signal ex6_pri_q : std_ulogic_vector(0 to 2); +signal ex6_ta_q, ex6_ta_d : std_ulogic_vector(0 to 7); +signal ex6_val_q, ex6_val_d : std_ulogic_vector(0 to threads-1); +signal ex7_gpr_we_q : std_ulogic; +signal ex7_ta_q : std_ulogic_vector(0 to 7); +signal ex7_val_q : std_ulogic_vector(0 to threads-1); +signal an_ac_dcr_val_q : std_ulogic; +signal dcr_ack_q, dcr_ack : std_ulogic; +signal dcr_act_q : std_ulogic; +signal dcr_etid_q : std_ulogic_vector(0 to 1); +signal dcr_read_q : std_ulogic; +signal dcr_val_q, dcr_val_d : std_ulogic; +signal instr_trace_mode_q : std_ulogic; +signal instr_trace_tid_q : std_ulogic_vector(0 to 1); +signal lsu_xu_need_hole_q, lsu_xu_need_hole_d : std_ulogic; +signal lsu_xu_rel_ta_gpr_q : std_ulogic_vector(0 to 7); +signal lsu_xu_rel_wren_q : std_ulogic; +signal mmucr0_0_tlbsel_q : std_ulogic_vector(4 to 5); +signal mmucr0_1_tlbsel_q : std_ulogic_vector(4 to 5); +signal mmucr0_2_tlbsel_q : std_ulogic_vector(4 to 5); +signal mmucr0_3_tlbsel_q : std_ulogic_vector(4 to 5); +signal slowspr_etid_q : std_ulogic_vector(0 to 1); +signal slowspr_rw_q : std_ulogic; +signal slowspr_val_q : std_ulogic; +signal spr_ccr2_en_attn_q : std_ulogic; +signal spr_ccr2_en_dcr_q : std_ulogic; +signal spr_ccr2_en_ditc_q : std_ulogic; +signal spr_ccr2_en_icswx_q : std_ulogic; +signal spr_ccr2_en_pc_q : std_ulogic; +signal spr_ccr2_notlb_q : std_ulogic; +signal spr_msr_cm_q : std_ulogic_vector(0 to threads-1); +signal t0_hold_ta_q : std_ulogic_vector(0 to 5); +signal t1_hold_ta_q : std_ulogic_vector(0 to 5); +signal t2_hold_ta_q : std_ulogic_vector(0 to 5); +signal t3_hold_ta_q : std_ulogic_vector(0 to 5); +signal trace_bus_enable_q : std_ulogic; +signal clkg_ctl_q : std_ulogic; +signal spr_bit_act_q : std_ulogic; +signal spare_0_q, spare_0_d : std_ulogic_vector(0 to 15); +signal spare_1_q, spare_1_d : std_ulogic_vector(0 to 15); +constant is1_need_hole_offset : integer := 0; +constant is2_need_hole_offset : integer := is1_need_hole_offset + 1; +constant rf0_back_inv_offset : integer := is2_need_hole_offset + 1; +constant rf0_back_inv_addr_offset : integer := rf0_back_inv_offset + 1; +constant rf0_need_hole_offset : integer := rf0_back_inv_addr_offset + rf0_back_inv_addr_q'length; +constant rf1_act_offset : integer := rf0_need_hole_offset + 1; +constant rf1_axu_ld_or_st_offset : integer := rf1_act_offset + 1; +constant rf1_back_inv_offset : integer := rf1_axu_ld_or_st_offset + 1; +constant rf1_need_hole_offset : integer := rf1_back_inv_offset + 1; +constant rf1_ta_vld_offset : integer := rf1_need_hole_offset + 1; +constant rf1_ucode_val_offset : integer := rf1_ta_vld_offset + 1; +constant rf1_val_offset : integer := rf1_ucode_val_offset + rf1_ucode_val_q'length; +constant rf1_val_iu_offset : integer := rf1_val_offset + rf1_val_q'length; +constant ex1_act_offset : integer := rf1_val_iu_offset + rf1_val_iu_q'length; +constant ex1_axu_instr_type_offset : integer := ex1_act_offset + 1; +constant ex1_axu_movedp_offset : integer := ex1_axu_instr_type_offset + ex1_axu_instr_type_q'length; +constant ex1_back_inv_offset : integer := ex1_axu_movedp_offset + 1; +constant ex1_bh_offset : integer := ex1_back_inv_offset + 1; +constant ex1_clear_barrier_offset : integer := ex1_bh_offset + ex1_bh_q'length; +constant ex1_ddmh_en_offset : integer := ex1_clear_barrier_offset + 1; +constant ex1_ditc_illeg_offset : integer := ex1_ddmh_en_offset + 1; +constant ex1_dp_indexed_offset : integer := ex1_ditc_illeg_offset + 1; +constant ex1_epid_instr_offset : integer := ex1_dp_indexed_offset + 1; +constant ex1_error_offset : integer := ex1_epid_instr_offset + 1; +constant ex1_getNIA_offset : integer := ex1_error_offset + ex1_error_q'length; +constant ex1_gpr_we_offset : integer := ex1_getNIA_offset + 1; +constant ex1_gshare_offset : integer := ex1_gpr_we_offset + 1; +constant ex1_instr_offset : integer := ex1_gshare_offset + ex1_gshare_q'length; +constant ex1_instr_hypv_offset : integer := ex1_instr_offset + ex1_instr_q'length; +constant ex1_instr_priv_offset : integer := ex1_instr_hypv_offset + 1; +constant ex1_is_any_load_dac_offset : integer := ex1_instr_priv_offset + 1; +constant ex1_is_any_store_offset : integer := ex1_is_any_load_dac_offset + 1; +constant ex1_is_any_store_dac_offset : integer := ex1_is_any_store_offset + 1; +constant ex1_is_attn_offset : integer := ex1_is_any_store_dac_offset + 1; +constant ex1_is_bclr_offset : integer := ex1_is_attn_offset + 1; +constant ex1_is_cmp_offset : integer := ex1_is_bclr_offset + 1; +constant ex1_is_csync_offset : integer := ex1_is_cmp_offset + 1; +constant ex1_is_eratsxr_offset : integer := ex1_is_csync_offset + 1; +constant ex1_is_icswx_offset : integer := ex1_is_eratsxr_offset + 1; +constant ex1_is_isync_offset : integer := ex1_is_icswx_offset + 1; +constant ex1_is_ld_w_update_offset : integer := ex1_is_isync_offset + 1; +constant ex1_is_lmw_offset : integer := ex1_is_ld_w_update_offset + 1; +constant ex1_is_lswi_offset : integer := ex1_is_lmw_offset + 1; +constant ex1_is_lswx_offset : integer := ex1_is_lswi_offset + 1; +constant ex1_is_mfcr_offset : integer := ex1_is_lswx_offset + 1; +constant ex1_is_mfspr_offset : integer := ex1_is_mfcr_offset + 1; +constant ex1_is_msgclr_offset : integer := ex1_is_mfspr_offset + 1; +constant ex1_is_msgsnd_offset : integer := ex1_is_msgclr_offset + 1; +constant ex1_is_mtspr_offset : integer := ex1_is_msgsnd_offset + 1; +constant ex1_is_sc_offset : integer := ex1_is_mtspr_offset + 1; +constant ex1_is_st_w_update_offset : integer := ex1_is_sc_offset + 1; +constant ex1_is_ucode_offset : integer := ex1_is_st_w_update_offset + 1; +constant ex1_is_wchkall_offset : integer := ex1_is_ucode_offset + 1; +constant ex1_lk_offset : integer := ex1_is_wchkall_offset + 1; +constant ex1_match_offset : integer := ex1_lk_offset + 1; +constant ex1_mfdcr_instr_offset : integer := ex1_match_offset + 1; +constant ex1_mfdp_val_offset : integer := ex1_mfdcr_instr_offset + 1; +constant ex1_mtdcr_instr_offset : integer := ex1_mfdp_val_offset + 1; +constant ex1_mtdp_nr_offset : integer := ex1_mtdcr_instr_offset + 1; +constant ex1_mtdp_val_offset : integer := ex1_mtdp_nr_offset + 1; +constant ex1_muldiv_coll_offset : integer := ex1_mtdp_val_offset + 1; +constant ex1_need_hole_offset : integer := ex1_muldiv_coll_offset + 1; +constant ex1_num_regs_offset : integer := ex1_need_hole_offset + 1; +constant ex1_ovr_rotsel_offset : integer := ex1_num_regs_offset + ex1_num_regs_q'length; +constant ex1_pred_taken_cnt_offset : integer := ex1_ovr_rotsel_offset + 1; +constant ex1_pred_update_offset : integer := ex1_pred_taken_cnt_offset + ex1_pred_taken_cnt_q'length; +constant ex1_pri_offset : integer := ex1_pred_update_offset + 1; +constant ex1_rotsel_ovrd_offset : integer := ex1_pri_offset + ex1_pri_q'length; +constant ex1_s1_offset : integer := ex1_rotsel_ovrd_offset + ex1_rotsel_ovrd_q'length; +constant ex1_s2_offset : integer := ex1_s1_offset + ex1_s1_q'length; +constant ex1_s3_offset : integer := ex1_s2_offset + ex1_s2_q'length; +constant ex1_spr_sel_offset : integer := ex1_s3_offset + ex1_s3_q'length; +constant ex1_ta_offset : integer := ex1_spr_sel_offset + 1; +constant ex1_tid_offset : integer := ex1_ta_offset + ex1_ta_q'length; +constant ex1_tlb_data_val_offset : integer := ex1_tid_offset + ex1_tid_q'length; +constant ex1_tlb_illeg_offset : integer := ex1_tlb_data_val_offset + 1; +constant ex1_trace_type_offset : integer := ex1_tlb_illeg_offset + 1; +constant ex1_trace_val_offset : integer := ex1_trace_type_offset + ex1_trace_type_q'length; +constant ex1_val_offset : integer := ex1_trace_val_offset + 1; +constant ex1_axu_ld_or_st_offset : integer := ex1_val_offset + ex1_val_q'length; +constant ex2_act_offset : integer := ex1_axu_ld_or_st_offset + 1; +constant ex2_back_inv_offset : integer := ex2_act_offset + 1; +constant ex2_clear_barrier_offset : integer := ex2_back_inv_offset + 1; +constant ex2_ipb_ba_offset : integer := ex2_clear_barrier_offset + 1; +constant ex2_ipb_sz_offset : integer := ex2_ipb_ba_offset + ex2_ipb_ba_q'length; +constant ex2_gpr_we_offset : integer := ex2_ipb_sz_offset + ex2_ipb_sz_q'length; +constant ex2_is_ucode_offset : integer := ex2_gpr_we_offset + 1; +constant ex2_muldiv_coll_offset : integer := ex2_is_ucode_offset + 1; +constant ex2_need_hole_offset : integer := ex2_muldiv_coll_offset + 1; +constant ex2_val_offset : integer := ex2_need_hole_offset + 1; +constant ex3_act_offset : integer := ex2_val_offset + ex2_val_q'length; +constant ex3_axu_instr_type_offset : integer := ex3_act_offset + 1; +constant ex3_back_inv_offset : integer := ex3_axu_instr_type_offset + ex3_axu_instr_type_q'length; +constant ex3_bh_offset : integer := ex3_back_inv_offset + 1; +constant ex3_clear_barrier_offset : integer := ex3_bh_offset + ex3_bh_q'length; +constant ex3_ddmh_en_offset : integer := ex3_clear_barrier_offset + 1; +constant ex3_div_done_offset : integer := ex3_ddmh_en_offset + 1; +constant ex3_getNIA_offset : integer := ex3_div_done_offset + 1; +constant ex3_gpr_we_offset : integer := ex3_getNIA_offset + 1; +constant ex3_gshare_offset : integer := ex3_gpr_we_offset + 1; +constant ex3_instr_offset : integer := ex3_gshare_offset + ex3_gshare_q'length; +constant ex3_instr_hypv_offset : integer := ex3_instr_offset + ex3_instr_q'length; +constant ex3_instr_priv_offset : integer := ex3_instr_hypv_offset + 1; +constant ex3_is_any_store_offset : integer := ex3_instr_priv_offset + 1; +constant ex3_is_bclr_offset : integer := ex3_is_any_store_offset + 1; +constant ex3_is_eratsxr_offset : integer := ex3_is_bclr_offset + 1; +constant ex3_is_mfcr_offset : integer := ex3_is_eratsxr_offset + 1; +constant ex3_is_wchkall_offset : integer := ex3_is_mfcr_offset + 1; +constant ex3_lk_offset : integer := ex3_is_wchkall_offset + 1; +constant ex3_mfdp_val_offset : integer := ex3_lk_offset + 1; +constant ex3_mtdp_nr_offset : integer := ex3_mfdp_val_offset + 1; +constant ex3_mtdp_val_offset : integer := ex3_mtdp_nr_offset + 1; +constant ex3_muldiv_coll_offset : integer := ex3_mtdp_val_offset + 1; +constant ex3_need_hole_offset : integer := ex3_muldiv_coll_offset + 1; +constant ex3_pred_taken_cnt_offset : integer := ex3_need_hole_offset + 1; +constant ex3_pred_update_offset : integer := ex3_pred_taken_cnt_offset + ex3_pred_taken_cnt_q'length; +constant ex3_pri_offset : integer := ex3_pred_update_offset + 1; +constant ex3_slowspr_dcr_rd_offset : integer := ex3_pri_offset + ex3_pri_q'length; +constant ex3_ta_offset : integer := ex3_slowspr_dcr_rd_offset + 1; +constant ex3_tid_offset : integer := ex3_ta_offset + ex3_ta_q'length; +constant ex3_tlb_data_val_offset : integer := ex3_tid_offset + ex3_tid_q'length; +constant ex3_tlb_illeg_offset : integer := ex3_tlb_data_val_offset + 1; +constant ex3_trace_type_offset : integer := ex3_tlb_illeg_offset + 1; +constant ex3_trace_val_offset : integer := ex3_trace_type_offset + ex3_trace_type_q'length; +constant ex3_val_offset : integer := ex3_trace_val_offset + 1; +constant ex4_act_offset : integer := ex3_val_offset + ex3_val_q'length; +constant ex4_clear_barrier_offset : integer := ex4_act_offset + 1; +constant ex4_gpr_we_offset : integer := ex4_clear_barrier_offset + 1; +constant ex4_val_offset : integer := ex4_gpr_we_offset + 1; +constant ex5_act_offset : integer := ex4_val_offset + ex4_val_q'length; +constant ex5_bh_offset : integer := ex5_act_offset + 1; +constant ex5_clear_barrier_offset : integer := ex5_bh_offset + ex5_bh_q'length; +constant ex5_getNIA_offset : integer := ex5_clear_barrier_offset + 1; +constant ex5_gpr_we_offset : integer := ex5_getNIA_offset + 1; +constant ex5_gshare_offset : integer := ex5_gpr_we_offset + 1; +constant ex5_instr_offset : integer := ex5_gshare_offset + ex5_gshare_q'length; +constant ex5_is_bclr_offset : integer := ex5_instr_offset + ex5_instr_q'length; +constant ex5_lk_offset : integer := ex5_is_bclr_offset + 1; +constant ex5_pred_taken_cnt_offset : integer := ex5_lk_offset + 1; +constant ex5_pred_update_offset : integer := ex5_pred_taken_cnt_offset + ex5_pred_taken_cnt_q'length; +constant ex5_pri_offset : integer := ex5_pred_update_offset + 1; +constant ex5_slowspr_dcr_rd_offset : integer := ex5_pri_offset + ex5_pri_q'length; +constant ex5_ta_offset : integer := ex5_slowspr_dcr_rd_offset + ex5_slowspr_dcr_rd_q'length; +constant ex5_tid_offset : integer := ex5_ta_offset + ex5_ta_q'length; +constant ex5_val_offset : integer := ex5_tid_offset + ex5_tid_q'length; +constant ex6_clear_barrier_offset : integer := ex5_val_offset + ex5_val_q'length; +constant ex6_gpr_we_offset : integer := ex6_clear_barrier_offset + ex6_clear_barrier_q'length; +constant ex6_pri_offset : integer := ex6_gpr_we_offset + 1; +constant ex6_ta_offset : integer := ex6_pri_offset + ex6_pri_q'length; +constant ex6_val_offset : integer := ex6_ta_offset + ex6_ta_q'length; +constant ex7_gpr_we_offset : integer := ex6_val_offset + ex6_val_q'length; +constant ex7_ta_offset : integer := ex7_gpr_we_offset + 1; +constant ex7_val_offset : integer := ex7_ta_offset + ex7_ta_q'length; +constant an_ac_dcr_val_offset : integer := ex7_val_offset + ex7_val_q'length; +constant dcr_ack_offset : integer := an_ac_dcr_val_offset + 1; +constant dcr_act_offset : integer := dcr_ack_offset + 1; +constant dcr_etid_offset : integer := dcr_act_offset + 1; +constant dcr_read_offset : integer := dcr_etid_offset + dcr_etid_q'length; +constant dcr_val_offset : integer := dcr_read_offset + 1; +constant instr_trace_mode_offset : integer := dcr_val_offset + 1; +constant instr_trace_tid_offset : integer := instr_trace_mode_offset + 1; +constant lsu_xu_need_hole_offset : integer := instr_trace_tid_offset + instr_trace_tid_q'length; +constant lsu_xu_rel_ta_gpr_offset : integer := lsu_xu_need_hole_offset + 1; +constant lsu_xu_rel_wren_offset : integer := lsu_xu_rel_ta_gpr_offset + lsu_xu_rel_ta_gpr_q'length; +constant mmucr0_0_tlbsel_offset : integer := lsu_xu_rel_wren_offset + 1; +constant mmucr0_1_tlbsel_offset : integer := mmucr0_0_tlbsel_offset + mmucr0_0_tlbsel_q'length; +constant mmucr0_2_tlbsel_offset : integer := mmucr0_1_tlbsel_offset + mmucr0_1_tlbsel_q'length; +constant mmucr0_3_tlbsel_offset : integer := mmucr0_2_tlbsel_offset + mmucr0_2_tlbsel_q'length; +constant slowspr_etid_offset : integer := mmucr0_3_tlbsel_offset + mmucr0_3_tlbsel_q'length; +constant slowspr_rw_offset : integer := slowspr_etid_offset + slowspr_etid_q'length; +constant slowspr_val_offset : integer := slowspr_rw_offset + 1; +constant spr_ccr2_en_attn_offset : integer := slowspr_val_offset + 1; +constant spr_ccr2_en_dcr_offset : integer := spr_ccr2_en_attn_offset + 1; +constant spr_ccr2_en_ditc_offset : integer := spr_ccr2_en_dcr_offset + 1; +constant spr_ccr2_en_icswx_offset : integer := spr_ccr2_en_ditc_offset + 1; +constant spr_ccr2_en_pc_offset : integer := spr_ccr2_en_icswx_offset + 1; +constant spr_ccr2_notlb_offset : integer := spr_ccr2_en_pc_offset + 1; +constant spr_msr_cm_offset : integer := spr_ccr2_notlb_offset + 1; +constant t0_hold_ta_offset : integer := spr_msr_cm_offset + spr_msr_cm_q'length; +constant t1_hold_ta_offset : integer := t0_hold_ta_offset + t0_hold_ta_q'length; +constant t2_hold_ta_offset : integer := t1_hold_ta_offset + t1_hold_ta_q'length; +constant t3_hold_ta_offset : integer := t2_hold_ta_offset + t2_hold_ta_q'length; +constant trace_bus_enable_offset : integer := t3_hold_ta_offset + t3_hold_ta_q'length; +constant clkg_ctl_offset : integer := trace_bus_enable_offset + 1; +constant spr_bit_act_offset : integer := clkg_ctl_offset + 1; +constant spare_0_offset : integer := spr_bit_act_offset + 1; +constant spare_1_offset : integer := spare_0_offset + spare_0_q'length; +constant xu_dec_sspr_offset : integer := spare_1_offset + spare_1_q'length; +constant scan_right : integer := xu_dec_sspr_offset + 1; +signal siv : std_ulogic_vector(0 to scan_right-1); +signal sov : std_ulogic_vector(0 to scan_right-1); +signal spare_0_lclk : clk_logic; +signal spare_1_lclk : clk_logic; +signal spare_0_d1clk, spare_0_d2clk : std_ulogic; +signal spare_1_d1clk, spare_1_d2clk : std_ulogic; +signal rf0_opcode_is_31 : std_ulogic; +signal rf1_opcode_is_31, rf1_opcode_is_0, + rf1_opcode_is_19, rf1_opcode_is_62, rf1_opcode_is_58 : boolean; +signal + rf1_is_attn , rf1_is_bc , rf1_is_bclr , rf1_is_dcbf , rf1_is_dcbi , + rf1_is_dcbst , rf1_is_dcblc , rf1_is_dcbt , rf1_is_dcbtls , rf1_is_dcbtst , + rf1_is_dcbtstls , rf1_is_dcbz , rf1_is_dci , rf1_is_eratilx , rf1_is_erativax , + rf1_is_eratre , rf1_is_eratsx , rf1_is_eratsrx , rf1_is_eratwe , rf1_is_ici , + rf1_is_icbi , rf1_is_icblc , rf1_is_icbt , rf1_is_icbtls , rf1_is_isync , + rf1_is_ld , rf1_is_ldarx , rf1_is_ldbrx , rf1_is_ldu , rf1_is_lhbrx , + rf1_is_lmw , rf1_is_lswi , rf1_is_lswx , rf1_is_lwa , rf1_is_lwarx , + rf1_is_lwbrx , rf1_is_mfcr , rf1_is_mfdp , rf1_is_mfdpx , rf1_is_mtdp , + rf1_is_mtdpx , rf1_is_mfspr , rf1_is_mtcrf , rf1_is_mtmsr , rf1_is_mtspr , + rf1_is_neg , rf1_is_rfci , rf1_is_rfi , rf1_is_rfmci , rf1_is_sc , + rf1_is_std , rf1_is_stdbrx , rf1_is_stdcxr , rf1_is_stdu , rf1_is_sthbrx , + rf1_is_stwcxr , rf1_is_stwbrx , rf1_is_subf , rf1_is_subfc , rf1_is_subfe , + rf1_is_subfic , rf1_is_subfme , rf1_is_subfze , rf1_is_td , rf1_is_tdi , + rf1_is_tlbilx , rf1_is_tlbivax , rf1_is_tlbre , rf1_is_tlbsx , rf1_is_tlbsrx , + rf1_is_tlbwe , rf1_is_tlbwec , rf1_is_tw , rf1_is_twi , + rf1_is_wrtee , rf1_is_dcbstep , rf1_is_dcbtep , rf1_is_dcbfep , rf1_is_dcbtstep , + rf1_is_icbiep , rf1_is_dcbzep , rf1_is_rfgi , rf1_is_ehpriv , rf1_is_msgclr , + rf1_is_msgsnd , rf1_is_icswx , rf1_is_icswepx , rf1_is_wchkall , rf1_is_wclr , + rf1_is_mfdcr , rf1_is_mfdcrux , rf1_is_mfdcrx , rf1_is_mtdcr , rf1_is_mtdcrux , + rf1_is_mtdcrx , rf1_is_mulhd , rf1_is_mulhdu , rf1_is_mulhw , rf1_is_mulhwu , + rf1_is_mulld , rf1_is_mulli , rf1_is_mullw , rf1_is_divd , rf1_is_divdu , + rf1_is_divw , rf1_is_divwu , rf1_is_divwe , rf1_is_divweu , rf1_is_divde , + rf1_is_divdeu , rf1_is_eratsxr , rf1_is_tlbsxr : std_ulogic; +signal tiup : std_ulogic; +signal tidn : std_ulogic; +signal rf1_add_ext : std_ulogic; +signal rf1_sub : std_ulogic; +signal rf1_is_any_store : std_ulogic; +signal rf1_is_any_load_axu : std_ulogic; +signal rf1_is_any_store_axu : std_ulogic; +signal rf1_is_any_load_dac : std_ulogic; +signal rf1_is_any_store_dac : std_ulogic; +signal rf1_imm_size : std_ulogic; +signal rf1_imm_signext : std_ulogic; +signal rf1_16b_imm : std_ulogic_vector(0 to 15); +signal rf1_64b_imm : std_ulogic_vector(0 to 63); +signal rf1_imm_sign_ext : std_ulogic_vector(0 to 63); +signal rf1_imm_shifted : std_ulogic_vector(0 to 63); +signal rf1_shift_imm : std_ulogic; +signal rf1_zero_imm : std_ulogic; +signal rf1_ones_imm : std_ulogic; +signal rf1_gpr0_zero : std_ulogic; +signal rf1_cache_acc : std_ulogic; +signal rf1_touch_drop : std_ulogic; +signal rf1_wclr_all : std_ulogic; +signal rf1_xer_ca : std_ulogic; +signal rf1_xer_ca_update : std_ulogic; +signal rf1_xer_ov_update : std_ulogic; +signal rf1_lk : std_ulogic; +signal rf1_bh : std_ulogic_vector(0 to 1); +signal rf1_cmp : std_ulogic; +signal rf1_cmp_lfld : std_ulogic; +signal rf1_is_st_w_update : std_ulogic; +signal rf1_is_ld_w_update : std_ulogic; +signal rf1_rs0_byp_cmp, rf1_rs1_byp_cmp, rf1_rs2_byp_cmp : std_ulogic_vector(1 to 8); +signal rf1_rs0_byp_stageval, rf1_rs1_byp_stageval, rf1_rs2_byp_stageval : std_ulogic_vector(1 to 7); +signal rf1_rs0_byp_val : std_ulogic_vector(0 to 8); +signal rf1_rs1_byp_val : std_ulogic_vector(1 to 8); +signal rf1_rs2_byp_val : std_ulogic_vector(1 to 8); +signal rf1_rs0_sel : std_ulogic_vector(1 to 9); +signal rf1_rs1_sel : std_ulogic_vector(1 to 9); +signal rf1_rs2_sel : std_ulogic_vector(1 to 9); +signal rf1_cmp_uext : std_ulogic; +signal rf1_val_stg : std_ulogic; +signal rf1_val_w_ldstm : std_ulogic; +signal rf1_instr_priv : std_ulogic; +signal rf1_instr_hypv : std_ulogic; +signal rf1_use_crfld0 : std_ulogic; +signal rf1_use_crfld0_nmult : std_ulogic; +signal rf1_rs1_use_imm : std_ulogic; +signal ex3_tlbsel : std_ulogic_vector(12 to 13); +signal ex1_ipc_ln : std_ulogic_vector(0 to 1); +signal ex1_dp_rot_addr : std_ulogic_vector(0 to 5); +signal ex1_dp_rot_op_size : std_ulogic_vector(0 to 5); +signal ex1_dp_rot_r_amt : std_ulogic_vector(0 to 5); +signal ex1_dp_rot_l_amt : std_ulogic_vector(0 to 5); +signal ex1_dp_rot_dir : std_ulogic_vector(0 to 1); +signal ex1_dp_rot_amt : std_ulogic_vector(0 to 5); +signal rf1_mfdp : std_ulogic; +signal rf1_mtdp : std_ulogic; +signal rf1_derat_is_load : std_ulogic; +signal rf1_derat_is_store : std_ulogic; +signal rf1_tlbsel : std_ulogic_vector(12 to 12); +signal rf1_tlb_illeg_ws : std_ulogic; +signal rf1_tlb_illeg_ws2 : std_ulogic; +signal rf1_tlb_illeg_ws3 : std_ulogic; +signal rf1_tlb_illeg_sel : std_ulogic; +signal rf1_tlb_illeg_t : std_ulogic; +signal rf1_clear_barrier : std_ulogic; +signal rf1_th_fld_b0 : std_ulogic; +signal rf1_th_fld_c : std_ulogic; +signal rf1_th_fld_l2 : std_ulogic; +signal rf1_num_bytes : std_ulogic_vector(0 to 7); +signal rf1_num_bytes_plus3 : std_ulogic_vector(0 to 7); +signal ex1_lower_bnd : std_ulogic_vector(0 to 5); +signal ex1_upper_bnd : std_ulogic_vector(0 to 5); +signal ex1_upper_bnd_wrap : std_ulogic_vector(0 to 5); +signal ex2_ra_in_rng : std_ulogic; +signal ex2_rb_in_rng : std_ulogic; +signal slowspr_need_hole : std_ulogic; +signal rf1_src0_vld : std_ulogic; +signal rf1_src0_reg : std_ulogic_vector(0 to 7); +signal rf1_src1_vld : std_ulogic; +signal rf1_src1_reg : std_ulogic_vector(0 to 7); +signal rf1_targ_vld : std_ulogic; +signal rf1_targ_reg : std_ulogic_vector(0 to 7); +signal rf1_spr_msr_cm : std_ulogic; +signal rf1_spr_sel : std_ulogic; +signal rf1_is_trap : std_ulogic; +signal rf1_cr_so_update : std_ulogic_vector(0 to 1); +signal rf1_cr_we : std_ulogic; +signal rf1_alu_cmp : std_ulogic; +signal rf1_pri : std_ulogic_vector(0 to 2); +signal rf1_instr_hypv_other : std_ulogic; +signal rf1_instr_hypv_tbl : std_ulogic; +signal rf1_instr_priv_other : std_ulogic; +signal rf1_instr_priv_tbl : std_ulogic; +signal rf1_sel : std_ulogic_vector(0 to 3); +signal rf1_imm_size_tbl : std_ulogic; +signal rf1_imm_signext_tbl : std_ulogic; +signal rf1_getNIA : std_ulogic; +signal rf1_mtspr_trace : std_ulogic; +signal rf1_ldst_trgt_gate : std_ulogic; +signal rf1_axu_instr_type : std_ulogic_vector(0 to 2); +signal rf1_axu_ldst_forcealign : std_ulogic; +signal rf1_axu_ldst_forceexcept : std_ulogic; +signal rf1_axu_ldst_indexed_b : std_ulogic; +signal rf1_axu_mftgpr : std_ulogic; +signal rf1_axu_mffgpr : std_ulogic; +signal rf1_axu_movedp : std_ulogic; +signal rf1_axu_ldst_size : std_ulogic_vector(1 to 5); +signal rf1_axu_ldst_update : std_ulogic; +signal rf1_axu_instr_priv : std_ulogic; +signal ex1_is_slowspr_rd : std_ulogic; +signal ex1_is_slowspr_wr : std_ulogic; +signal ex5_slow_op_done : std_ulogic; +signal ex5_ta_etid : std_ulogic_vector(0 to 1); +signal ex5_hold_ta : std_ulogic_vector(t0_hold_ta_q'range); +signal dcr_val : std_ulogic; +signal rf1_xer_si_zero_b : std_ulogic; +signal rf1_spr_xer_si : std_ulogic_vector(0 to 6); +signal rf1_force_64b_cmp, rf1_force_32b_cmp : std_ulogic; +signal rf1_trace_mtspr, rf1_trace_ldst : std_ulogic; +signal instr_trace_tid : std_ulogic_vector(0 to threads-1); +signal rf1_is_touch, rf1_derat_ra_eq_ea : std_ulogic; +signal rf1_target_gpr : std_ulogic_vector(0 to 8); +signal rf1_cmd_act, rf1_derat_act : std_ulogic; +signal rf1_zero_imm_binv, rf1_ones_imm_binv : std_ulogic; + BEGIN --@@ START OF EXECUTABLE CODE FOR XUQ_DEC_B + +tiup <= '1'; +tidn <= '0'; +ex1_val_d <= rf1_val_q and not xu_rf1_flush; +ex2_val_d <= ex1_val_q and not xu_ex1_flush; +ex3_val_d <= ex2_val_q and not xu_ex2_flush; +ex4_val_d <= ex3_val_q and not xu_ex3_flush; +ex5_val_d <= ex4_val_q and not xu_ex4_flush; +ex6_val_d <= ex5_val_q and not xu_ex5_flush; +rf1_val_stg <= or_reduce(rf1_val_q); +rf0_act <= fxa_fxb_rf0_act or rf0_back_inv_q or clkg_ctl_q; +dec_byp_rf0_act <= rf0_act; +ex1_act_d <= rf1_act_q; +ex2_act_d <= ex1_act_q; +ex3_act_d <= ex2_act_q; +ex4_act_d <= ex3_act_q; +ex5_act_d <= ex4_act_q; +dec_alu_rf1_act <= rf1_act_q; +dec_alu_ex1_act <= ex1_act_q; +rf1_spr_msr_cm <= or_reduce(spr_msr_cm_q and rf1_tid_q); +rf1_cmp_lfld <= rf1_instr_q(10); +rf1_force_64b_cmp <= rf1_is_tdi or rf1_is_td or (rf1_alu_cmp and rf1_cmp_lfld) or rf1_back_inv_q; +rf1_force_32b_cmp <= rf1_is_twi or rf1_is_tw or (rf1_alu_cmp and not rf1_cmp_lfld); +dec_alu_rf1_select_64bmode <= (rf1_spr_msr_cm and not rf1_force_32b_cmp) or rf1_force_64b_cmp; +rf1_axu_ldst_forcealign <= rf1_axu_ldst_forcealign_q and rf1_axu_ld_or_st_q; +rf1_axu_ldst_forceexcept <= rf1_axu_ldst_forceexcept_q and rf1_axu_ld_or_st_q; +rf1_axu_ldst_indexed_b <= not(rf1_axu_ldst_indexed_q) and rf1_axu_ld_or_st_q; +rf1_axu_mftgpr <= rf1_axu_mftgpr_q and rf1_axu_ld_or_st_q; +rf1_axu_mffgpr <= rf1_axu_mffgpr_q and rf1_axu_ld_or_st_q; +rf1_axu_movedp <= rf1_axu_movedp_q and rf1_axu_ld_or_st_q; +rf1_axu_ldst_size <= gate(rf1_axu_ldst_size_q(1 to 5), rf1_axu_ld_or_st_q); +rf1_axu_ldst_update <= rf1_axu_ldst_update_q and rf1_axu_ld_or_st_q; +rf1_axu_instr_type <= gate(rf1_axu_instr_type_q, (rf1_axu_ld_or_st_q or or_reduce(rf1_ucode_val_q))); +rf1_ldst_trgt_gate <= not(rf1_cache_acc) or rf1_is_st_w_update or rf1_axu_ldst_update; +ex1_gpr_we_d <= rf1_ta_vld_q and rf1_ldst_trgt_gate; +ex2_gpr_we_d <= ex1_gpr_we_q and not ex1_slowspr_dcr_rd; +ex4_gpr_we_d <= ex3_gpr_we_q; +ex5_gpr_we_d <= ex4_gpr_we_q; +ex6_gpr_we_d <= (or_reduce(ex6_val_d) and (lsu_xu_ex5_wren or ex5_gpr_we_q)) or ex5_slow_op_done; +fxb_fxa_ex7_we0 <= ex7_gpr_we_q; +fxb_fxa_ex7_wa0 <= ex7_ta_q; +with instr_trace_tid_q select + instr_trace_tid <= "1000" when "00", + "0100" when "01", + "0010" when "10", + "0001" when others; +rf1_trace_val <= instr_trace_mode_q and not rf1_is_ucode_q and + or_reduce((rf1_val_q or rf1_ucode_val_q) and instr_trace_tid and not cpl_dec_in_ucode); +rf1_trace_mtspr <= rf1_is_mtspr or rf1_is_mtmsr or rf1_is_mtcrf or rf1_is_wrtee; +rf1_trace_ldst <= rf1_is_any_load_dac or rf1_is_any_store_dac or rf1_is_icswx or rf1_is_icswepx; + WITH s2'(rf1_trace_mtspr & rf1_trace_ldst) SELECT rf1_trace_type <= "10" when "10", + "11" when "01", + "01" when others; +dec_cpl_rf1_instr_trace_val <= rf1_trace_val; +dec_byp_ex3_instr_trace_val <= ex3_trace_val_q and ex3_trace_type_q(0); +dec_cpl_ex3_instr_trace_val <= ex3_trace_val_q; +xu_lsu_ex2_instr_trace_val <= ex2_trace_val_q and and_reduce(ex2_trace_type_q); +dec_byp_ex3_instr_trace_gate <= ex3_trace_val_q and ex3_trace_type_q(0) and ex3_trace_type_q(1) and not or_reduce(spr_msr_cm_q and instr_trace_tid); +dec_cpl_rf1_instr_trace_type <= rf1_trace_type; +dcr_val <= an_ac_dcr_val and spr_ccr2_en_dcr_q; +dcr_val_d <= dcr_val or (dcr_val_q and or_reduce(ex4_val_q)); +dcr_ack <= (dcr_val_q and not or_reduce(ex4_val_q)); +dec_byp_ex4_dcr_ack <= dcr_ack; +an_ac_dcr_ack <= dcr_ack_q; +ex5_slow_op_done <= (slowspr_val_q and slowspr_rw_q ) or + ( dcr_ack and dcr_read_q); +dec_cpl_ex1_is_slowspr_wr <= ex1_is_slowspr_wr or (ex1_mtdcr_instr_q and spr_ccr2_en_dcr_q); +ex1_slowspr_dcr_rd <= ex1_is_slowspr_rd or ex1_mfdcr_instr_q; +ex5_slowspr_dcr_rd_d <= gate(ex4_val_q,ex4_slowspr_dcr_rd_q); +ex5_ta_etid <= gate(slowspr_etid_q,slowspr_val_q) or + gate( dcr_etid_q, dcr_val_q); +with ex5_ta_etid select + ex5_hold_ta <= t0_hold_ta_q when "00", + t1_hold_ta_q when "01", + t2_hold_ta_q when "10", + t3_hold_ta_q when others; +with ex5_slow_op_done select + ex6_ta_d <= ex5_ta_q when '0', + ex5_hold_ta & ex5_ta_etid when others; +xu_iu_ex6_pri <= ex6_pri_q; +xu_iu_ex6_pri_val <= gate(ex6_val_q,or_reduce(ex6_pri_q)); +xu_dec_sspr : entity work.xuq_dec_sspr(xuq_dec_sspr) + generic map( + expand_type => expand_type, + threads => threads, + ctr_size => spr_dec_spr_xucr0_ssdly'length) + port map( + nclk => nclk, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc, + mpw1_dc_b => mpw1_dc_b, + mpw2_dc_b => mpw2_dc_b, + func_sl_force => func_sl_force, + func_sl_thold_0_b => func_sl_thold_0_b, + sg_0 => sg_0, + scan_in => siv(xu_dec_sspr_offset), + scan_out => sov(xu_dec_sspr_offset), + rf1_act => rf1_act_q, + rf1_val => rf1_val_q, + rf1_instr => rf1_instr_q, + slowspr_need_hole => slowspr_need_hole, + spr_dec_spr_xucr0_ssdly => spr_dec_spr_xucr0_ssdly, + ex1_is_slowspr_rd => ex1_is_slowspr_rd, + ex1_is_slowspr_wr => ex1_is_slowspr_wr, + vdd => vdd, + gnd => gnd); +lsu_xu_need_hole_d <= lsu_xu_need_hole; +is1_need_hole_d <= slowspr_need_hole; +is2_need_hole_d <= is1_need_hole_q or an_ac_dcr_val_q; +xu_iu_need_hole <= slowspr_need_hole or an_ac_dcr_val_q or alu_dec_div_need_hole or lsu_xu_need_hole_q; +dec_spr_ex1_is_mtspr <= ex1_is_mtspr_q; +dec_spr_ex1_is_mfspr <= ex1_is_mfspr_q; +dec_spr_ex4_val <= ex4_val_q; +dec_cpl_rf1_ucode_val <= rf1_ucode_val_q; +ex2_is_any_load_dac <= ex2_is_any_load_dac_q; +ex2_is_any_store_dac <= ex2_is_any_store_dac_q; +dec_cpl_ex3_is_any_store <= ex3_is_any_store_q; +dec_cpl_ex3_instr_priv <= ex3_instr_priv_q; +dec_cpl_ex3_mtdp_nr <= ex3_mtdp_nr_q; +dec_cpl_ex3_instr_hypv <= ex3_instr_hypv_q; +ex1_axu_instr_type_d <= rf1_axu_instr_type; +dec_cpl_ex3_axu_instr_type <= ex3_axu_instr_type_q; +dec_cpl_rf1_issued <= rf1_issued_q; +dec_cpl_rf1_val <= rf1_val_q; +dec_spr_rf1_val <= rf1_val_q or rf1_ucode_val_q; +dec_cpl_rf1_instr <= rf1_instr_q; +dec_cpl_ex2_error <= ex2_error_q; +dec_cpl_ex2_match <= ex2_match_q; +dec_cpl_ex2_is_ucode <= ex2_is_ucode_q; +dec_fspr_ex1_instr <= ex1_instr_q(11 to 20); +dec_fspr_ex6_val <= ex6_val_q; +xu_iu_ex5_val <= or_reduce(ex5_val_q and not xu_ex5_flush); +xu_iu_ex5_tid <= ex5_tid_q; +xu_iu_ex5_br_update <= ex5_pred_update_q; +xu_iu_ex5_br_hist <= ex5_pred_taken_cnt_q; +xu_iu_ex5_bclr <= ex5_is_bclr_q; +xu_iu_ex5_lk <= ex5_lk_q; +xu_iu_ex5_bh <= ex5_bh_q; +xu_iu_ex5_gshare <= ex5_gshare_q; +rf1_getNIA <= rf1_is_bc and + (rf1_instr_q(6 to 10) = "10100") and + (rf1_instr_q(11 to 15) = "11111") and + (rf1_instr_q(16 to 29) = "00000000000001") and + not rf1_instr_q(30) and + rf1_instr_q(31); +xu_iu_ex5_getNIA <= ex5_getNIA_q; +dec_byp_ex5_instr <= ex5_instr_q(12 to 19); +dec_byp_rf1_instr <= rf1_instr_q(6 to 25); +dec_byp_rf1_cr_so_update <= rf1_cr_so_update(0) & (rf1_cr_so_update(1) or rf1_use_crfld0); +dec_byp_ex3_val <= ex3_val_q; +dec_byp_rf1_cr_we <= rf1_cr_we or rf1_use_crfld0_nmult; +dec_byp_rf1_use_crfld0 <= rf1_use_crfld0; +dec_byp_rf1_alu_cmp <= rf1_alu_cmp or rf1_use_crfld0; +dec_byp_rf1_is_mtocrf <= tidn; +dec_byp_rf1_byp_val(1) <= or_reduce(rf1_tid_q and ex1_val_q); +dec_byp_rf1_byp_val(2) <= or_reduce(rf1_tid_q and ex2_val_q); +dec_byp_rf1_byp_val(3) <= or_reduce(rf1_tid_q and ex3_val_q); +dec_byp_ex4_is_eratsxr <= ex4_is_eratsxr_q; +dec_cpl_rf1_ifar <= rf1_ifar_q; +dec_cpl_rf1_pred_taken_cnt <= rf1_pred_taken_cnt_q(0); +dcdmrg : entity work.xuq_dec_dcdmrg(xuq_dec_dcdmrg) + port map ( + i => rf1_instr_q, + dec_alu_rf1_sel_rot_log => open, + dec_alu_rf1_sh_right => dec_alu_rf1_sh_right, + dec_alu_rf1_sh_word => dec_alu_rf1_sh_word, + dec_alu_rf1_sgnxtd_byte => dec_alu_rf1_sgnxtd_byte, + dec_alu_rf1_sgnxtd_half => dec_alu_rf1_sgnxtd_half, + dec_alu_rf1_sgnxtd_wd => dec_alu_rf1_sgnxtd_wd, + dec_alu_rf1_sra_dw => dec_alu_rf1_sra_dw, + dec_alu_rf1_sra_wd => dec_alu_rf1_sra_wd, + dec_alu_rf1_chk_shov_dw => dec_alu_rf1_chk_shov_dw, + dec_alu_rf1_chk_shov_wd => dec_alu_rf1_chk_shov_wd, + dec_alu_rf1_use_me_ins_hi => dec_alu_rf1_use_me_ins_hi, + dec_alu_rf1_use_me_ins_lo => dec_alu_rf1_use_me_ins_lo, + dec_alu_rf1_use_mb_ins_hi => dec_alu_rf1_use_mb_ins_hi, + dec_alu_rf1_use_mb_ins_lo => dec_alu_rf1_use_mb_ins_lo, + dec_alu_rf1_use_me_rb_hi => dec_alu_rf1_use_me_rb_hi, + dec_alu_rf1_use_me_rb_lo => dec_alu_rf1_use_me_rb_lo, + dec_alu_rf1_use_mb_rb_hi => dec_alu_rf1_use_mb_rb_hi, + dec_alu_rf1_use_mb_rb_lo => dec_alu_rf1_use_mb_rb_lo, + dec_alu_rf1_use_rb_amt_hi => dec_alu_rf1_use_rb_amt_hi, + dec_alu_rf1_use_rb_amt_lo => dec_alu_rf1_use_rb_amt_lo, + dec_alu_rf1_zm_ins => dec_alu_rf1_zm_ins, + dec_alu_rf1_cr_logical => dec_alu_rf1_cr_logical, + dec_alu_rf1_cr_log_fcn => dec_alu_rf1_cr_log_fcn, + dec_alu_rf1_log_fcn => dec_alu_rf1_log_fcn, + dec_alu_rf1_me_ins_b => dec_alu_rf1_me_ins_b, + dec_alu_rf1_mb_ins => dec_alu_rf1_mb_ins, + dec_alu_rf1_sh_amt => dec_alu_rf1_sh_amt, + dec_alu_rf1_mb_gt_me => dec_alu_rf1_mb_gt_me); +rf1_is_isel_d <= '1' when fxa_fxb_rf0_instr(0 to 5) = "011111" and + fxa_fxb_rf0_instr(26 to 30) = "01111" else '0'; +dec_rf1_is_isel <= rf1_is_isel_q; +dec_alu_rf1_xer_ov_update <= rf1_xer_ov_update; +dec_alu_rf1_xer_ca_update <= rf1_xer_ca_update; +dec_rf1_tid <= rf1_tid_2_q; +dec_ex1_tid <= ex1_tid_q; +dec_ex2_tid <= ex2_tid_q; +dec_ex3_tid <= ex3_tid_q; +dec_ex4_tid <= ex4_tid_q; +dec_ex5_tid <= ex5_tid_q; +dec_byp_ex4_is_mfcr <= ex4_is_mfcr_q; +rf1_xer_si_zero_b <= or_reduce(rf1_spr_xer_si); +rf1_spr_xer_si <= (byp_xer_si(0 to 6) and (0 to 6 => rf1_tid_q(0))) or + (byp_xer_si(7 to 13) and (7 to 13 => rf1_tid_q(1))) or + (byp_xer_si(14 to 20) and (14 to 20 => rf1_tid_q(2))) or + (byp_xer_si(21 to 27) and (21 to 27 => rf1_tid_q(3))); +rf1_lk <= rf1_instr_q(31); +rf1_bh <= rf1_instr_q(19 to 20); +rf1_instr_hypv_other <= ((rf1_is_tlbwe or rf1_is_tlbsrx or rf1_is_tlbwec or rf1_is_tlbilx ) and or_reduce(spr_dec_rf1_epcr_dgtmi and rf1_val_q)) or + ((rf1_is_dcblc or rf1_is_dcbtls or rf1_is_dcbtstls or rf1_is_icblc or rf1_is_icbtls) and or_reduce(spr_dec_rf1_msrp_uclep and rf1_val_q)); +rf1_instr_hypv <= rf1_instr_hypv_tbl or rf1_instr_hypv_other; +rf1_axu_instr_priv <= rf1_axu_is_extstore_q or rf1_axu_is_extload_q or rf1_axu_movedp_q; +rf1_instr_priv_other <= (rf1_is_dcblc or rf1_is_dcbtls or rf1_is_dcbtstls or rf1_is_icblc or rf1_is_icbtls) + and not or_reduce(spr_dec_rf1_msr_ucle and rf1_val_q); +rf1_instr_priv <= rf1_instr_priv_tbl or rf1_instr_priv_other or (rf1_axu_ld_or_st_q and rf1_axu_instr_priv); +rf1_mfdcr_instr <= rf1_is_mfdcr or rf1_is_mfdcrux or rf1_is_mfdcrx; +rf1_mtdcr_instr <= rf1_is_mtdcr or rf1_is_mtdcrux or rf1_is_mtdcrx; + WITH s2'(rf1_is_lswi & rf1_is_lswx) SELECT rf1_num_bytes <= "00" & not or_reduce(rf1_instr_q(16 to 20)) & rf1_instr_q(16 to 20) when "10", + '0' & rf1_spr_xer_si when "01", + (others=>tidn) when others; +rf1_num_bytes_plus3 <= std_ulogic_vector(unsigned(rf1_num_bytes) + 3); +ex1_num_regs_d <= rf1_num_bytes_plus3(0 to 5); +ex1_lower_bnd <= ex1_ta_q(0 to 5); +ex1_upper_bnd <= std_ulogic_vector(unsigned(ex1_lower_bnd) + unsigned(ex1_num_regs_q)); +ex1_upper_bnd_wrap <= '0' & ex1_upper_bnd(1 to 5); +ex2_range_wrap_d <= ex1_upper_bnd(0); +ex2_ra_in_rng_lmw_d <= '1' when ex1_s1_q(0 to 5) >= ex1_lower_bnd else '0'; +ex2_ra_in_rng_nowrap_d <= '1' when (ex1_s1_q(0 to 5) >= ex1_lower_bnd) and + (ex1_s1_q(0 to 5) < ex1_upper_bnd) else '0'; +ex2_ra_in_rng_wrap_d <= '1' when (ex1_s1_q(0 to 5) < ex1_upper_bnd_wrap)else '0'; +ex2_ra_in_rng <= (ex2_ra_in_rng_nowrap_q ) or + (ex2_ra_in_rng_wrap_q and ex2_range_wrap_q); +ex2_rb_in_rng_nowrap_d <= '1' when (ex1_s2_q(0 to 5) >= ex1_lower_bnd) and + (ex1_s2_q(0 to 5) < ex1_upper_bnd) else '0'; +ex2_rb_in_rng_wrap_d <= '1' when (ex1_s2_q(0 to 5) < ex1_upper_bnd_wrap)else '0'; +ex2_rb_in_rng <= (ex2_rb_in_rng_nowrap_q ) or + (ex2_rb_in_rng_wrap_q and ex2_range_wrap_q); +ex2_ra_eq_zero_d <= '1' when ex1_s1_q(0 to 5) = "000000" else '0'; +ex2_ra_eq_rt_d <= (ex1_s1_q(0 to 5) = ex1_ta_q(0 to 5)) and not ex1_axu_ld_or_st_q; +ex2_rb_eq_rt_d <= '1' when ex1_s2_q(0 to 5) = ex1_ta_q(0 to 5) else '0'; +ex1_ditc_illeg_d <= (rf1_is_mfdp or rf1_is_mfdpx or rf1_is_mtdp or rf1_is_mtdpx) and + not rf1_instr_q(20) and rf1_instr_q(16); +ex2_ditc_illeg_d <= (ex1_axu_ld_or_st_q and ex1_axu_movedp_q and not ex1_ovr_rotsel_q) or + ex1_ditc_illeg_q; +dec_cpl_ex2_illegal_op <= ex2_ditc_illeg_q + or (ex2_is_icswx_q and not spr_ccr2_en_icswx_q) + or (ex2_is_attn_q and not spr_ccr2_en_attn_q) + or ((ex2_mtdp_val_q or ex2_mfdp_val_q) and not spr_ccr2_en_ditc_q) + or ((ex2_is_msgsnd_q or ex2_is_msgclr_q) and not spr_ccr2_en_pc_q) + or (ex2_is_st_w_update_q and ex2_ra_eq_zero_q) + or (ex2_is_ld_w_update_q and (ex2_ra_eq_zero_q or + ex2_ra_eq_rt_q)) + or (ex2_is_lmw_q and ex2_ra_in_rng_lmw_q) + or (ex2_is_lswi_q and ex2_ra_in_rng) + or (ex2_is_lswx_q and (ex2_ra_eq_rt_q or + ex2_rb_eq_rt_q or + ex2_ra_in_rng or + ex2_rb_in_rng)) + or (ex2_is_sc_q and or_reduce(ex2_instr_q(20 to 25))); +rf1_rs1_use_imm <= rf1_use_imm_q or + rf1_axu_ldst_indexed_b or + rf1_back_inv_q; +rf1_gpr0_zero <= rf1_gpr0_zero_q or rf1_back_inv_q; +rf1_rs0_byp_cmp(1) <= '1' when rf1_s1_q = ex1_ta_q else '0'; +rf1_rs0_byp_cmp(2) <= '1' when rf1_s1_q = ex2_ta_q else '0'; +rf1_rs0_byp_cmp(3) <= '1' when rf1_s1_q = ex3_ta_q else '0'; +rf1_rs0_byp_cmp(4) <= '1' when rf1_s1_q = ex4_ta_q else '0'; +rf1_rs0_byp_cmp(5) <= '1' when rf1_s1_q = ex5_ta_q else '0'; +rf1_rs0_byp_cmp(6) <= '1' when rf1_s1_q = ex6_ta_q else '0'; +rf1_rs0_byp_cmp(7) <= '1' when rf1_s1_q = ex7_ta_q else '0'; +rf1_rs0_byp_cmp(8) <= '1' when rf1_s1_q = lsu_xu_rel_ta_gpr_q else '0'; +rf1_rs0_byp_stageval(1) <= or_reduce(ex1_val_q) and ex1_gpr_we_q; +rf1_rs0_byp_stageval(2) <= or_reduce(ex2_val_q) and ex2_gpr_we_q; +rf1_rs0_byp_stageval(3) <= or_reduce(ex3_val_q) and ex3_gpr_we_q; +rf1_rs0_byp_stageval(4) <= or_reduce(ex4_val_q) and ex4_gpr_we_q; +rf1_rs0_byp_stageval(5) <= or_reduce(ex5_val_q) and ex5_gpr_we_q; +rf1_rs0_byp_stageval(6) <= or_reduce(ex6_val_q) and ex6_gpr_we_q; +rf1_rs0_byp_stageval(7) <= or_reduce(ex7_val_q) and ex7_gpr_we_q; +rf1_rs0_byp_val(0) <= rf1_gpr0_zero; +rf1_rs0_byp_val(1) <= rf1_rs0_byp_stageval(1) and rf1_s1_vld_q and rf1_rs0_byp_cmp(1); +rf1_rs0_byp_val(2) <= rf1_rs0_byp_stageval(2) and rf1_s1_vld_q and rf1_rs0_byp_cmp(2); +rf1_rs0_byp_val(3) <= rf1_rs0_byp_stageval(3) and rf1_s1_vld_q and rf1_rs0_byp_cmp(3); +rf1_rs0_byp_val(4) <= rf1_rs0_byp_stageval(4) and rf1_s1_vld_q and rf1_rs0_byp_cmp(4); +rf1_rs0_byp_val(5) <= rf1_rs0_byp_stageval(5) and rf1_s1_vld_q and rf1_rs0_byp_cmp(5); +rf1_rs0_byp_val(6) <= rf1_rs0_byp_stageval(6) and rf1_s1_vld_q and rf1_rs0_byp_cmp(6); +rf1_rs0_byp_val(7) <= rf1_rs0_byp_stageval(7) and rf1_s1_vld_q and rf1_rs0_byp_cmp(7); +rf1_rs0_byp_val(8) <= lsu_xu_rel_wren_q and rf1_s1_vld_q and rf1_rs0_byp_cmp(8); +rf1_rs0_sel(1) <= rf1_rs0_byp_val(1) and not rf1_rs0_byp_val(0); +rf1_rs0_sel(2) <= rf1_rs0_byp_val(2) and not or_reduce(rf1_rs0_byp_val(0 to 1)); +rf1_rs0_sel(3) <= rf1_rs0_byp_val(3) and not or_reduce(rf1_rs0_byp_val(0 to 2)); +rf1_rs0_sel(4) <= rf1_rs0_byp_val(4) and not or_reduce(rf1_rs0_byp_val(0 to 3)); +rf1_rs0_sel(5) <= rf1_rs0_byp_val(5) and not or_reduce(rf1_rs0_byp_val(0 to 4)); +rf1_rs0_sel(6) <= rf1_rs0_byp_val(6) and not or_reduce(rf1_rs0_byp_val(0 to 5)); +rf1_rs0_sel(7) <= rf1_rs0_byp_val(7) and not or_reduce(rf1_rs0_byp_val(0 to 6)); +rf1_rs0_sel(8) <= rf1_rs0_byp_val(8) and not or_reduce(rf1_rs0_byp_val(0 to 7)); +rf1_rs0_sel(9) <= not or_reduce(rf1_rs0_byp_val(0 to 8)); +dec_byp_rf1_rs0_sel <= rf1_rs0_sel(1 to 9); +rf1_rs1_byp_cmp(1) <= '1' when rf1_s2_q = ex1_ta_q else '0'; +rf1_rs1_byp_cmp(2) <= '1' when rf1_s2_q = ex2_ta_q else '0'; +rf1_rs1_byp_cmp(3) <= '1' when rf1_s2_q = ex3_ta_q else '0'; +rf1_rs1_byp_cmp(4) <= '1' when rf1_s2_q = ex4_ta_q else '0'; +rf1_rs1_byp_cmp(5) <= '1' when rf1_s2_q = ex5_ta_q else '0'; +rf1_rs1_byp_cmp(6) <= '1' when rf1_s2_q = ex6_ta_q else '0'; +rf1_rs1_byp_cmp(7) <= '1' when rf1_s2_q = ex7_ta_q else '0'; +rf1_rs1_byp_cmp(8) <= '1' when rf1_s2_q = lsu_xu_rel_ta_gpr_q else '0'; +rf1_rs1_byp_stageval(1) <= or_reduce(ex1_val_q) and ex1_gpr_we_q; +rf1_rs1_byp_stageval(2) <= or_reduce(ex2_val_q) and ex2_gpr_we_q; +rf1_rs1_byp_stageval(3) <= or_reduce(ex3_val_q) and ex3_gpr_we_q; +rf1_rs1_byp_stageval(4) <= or_reduce(ex4_val_q) and ex4_gpr_we_q; +rf1_rs1_byp_stageval(5) <= or_reduce(ex5_val_q) and ex5_gpr_we_q; +rf1_rs1_byp_stageval(6) <= or_reduce(ex6_val_q) and ex6_gpr_we_q; +rf1_rs1_byp_stageval(7) <= or_reduce(ex7_val_q) and ex7_gpr_we_q; +rf1_rs1_byp_val(1) <= rf1_rs1_byp_stageval(1) and rf1_s2_vld_q and rf1_rs1_byp_cmp(1); +rf1_rs1_byp_val(2) <= rf1_rs1_byp_stageval(2) and rf1_s2_vld_q and rf1_rs1_byp_cmp(2); +rf1_rs1_byp_val(3) <= rf1_rs1_byp_stageval(3) and rf1_s2_vld_q and rf1_rs1_byp_cmp(3); +rf1_rs1_byp_val(4) <= rf1_rs1_byp_stageval(4) and rf1_s2_vld_q and rf1_rs1_byp_cmp(4); +rf1_rs1_byp_val(5) <= rf1_rs1_byp_stageval(5) and rf1_s2_vld_q and rf1_rs1_byp_cmp(5); +rf1_rs1_byp_val(6) <= rf1_rs1_byp_stageval(6) and rf1_s2_vld_q and rf1_rs1_byp_cmp(6); +rf1_rs1_byp_val(7) <= rf1_rs1_byp_stageval(7) and rf1_s2_vld_q and rf1_rs1_byp_cmp(7); +rf1_rs1_byp_val(8) <= lsu_xu_rel_wren_q and rf1_s2_vld_q and rf1_rs1_byp_cmp(8); +rf1_rs1_sel(1) <= rf1_rs1_byp_val(1); +rf1_rs1_sel(2) <= rf1_rs1_byp_val(2) and not rf1_rs1_byp_val(1); +rf1_rs1_sel(3) <= rf1_rs1_byp_val(3) and not or_reduce(rf1_rs1_byp_val(1 to 2)); +rf1_rs1_sel(4) <= rf1_rs1_byp_val(4) and not or_reduce(rf1_rs1_byp_val(1 to 3)); +rf1_rs1_sel(5) <= rf1_rs1_byp_val(5) and not or_reduce(rf1_rs1_byp_val(1 to 4)); +rf1_rs1_sel(6) <= rf1_rs1_byp_val(6) and not or_reduce(rf1_rs1_byp_val(1 to 5)); +rf1_rs1_sel(7) <= rf1_rs1_byp_val(7) and not or_reduce(rf1_rs1_byp_val(1 to 6)); +rf1_rs1_sel(8) <= rf1_rs1_byp_val(8) and not or_reduce(rf1_rs1_byp_val(1 to 7)); +rf1_rs1_sel(9) <= not or_reduce(rf1_rs1_byp_val(1 to 8)); +dec_byp_rf1_rs1_sel <= rf1_rs1_sel(1 to 9) & rf1_rs1_use_imm; +rf1_rs2_byp_cmp(1) <= '1' when rf1_s3_q = ex1_ta_q else '0'; +rf1_rs2_byp_cmp(2) <= '1' when rf1_s3_q = ex2_ta_q else '0'; +rf1_rs2_byp_cmp(3) <= '1' when rf1_s3_q = ex3_ta_q else '0'; +rf1_rs2_byp_cmp(4) <= '1' when rf1_s3_q = ex4_ta_q else '0'; +rf1_rs2_byp_cmp(5) <= '1' when rf1_s3_q = ex5_ta_q else '0'; +rf1_rs2_byp_cmp(6) <= '1' when rf1_s3_q = ex6_ta_q else '0'; +rf1_rs2_byp_cmp(7) <= '1' when rf1_s3_q = ex7_ta_q else '0'; +rf1_rs2_byp_cmp(8) <= '1' when rf1_s3_q = lsu_xu_rel_ta_gpr_q else '0'; +rf1_rs2_byp_stageval(1) <= or_reduce(ex1_val_q) and ex1_gpr_we_q; +rf1_rs2_byp_stageval(2) <= or_reduce(ex2_val_q) and ex2_gpr_we_q; +rf1_rs2_byp_stageval(3) <= or_reduce(ex3_val_q) and ex3_gpr_we_q; +rf1_rs2_byp_stageval(4) <= or_reduce(ex4_val_q) and ex4_gpr_we_q; +rf1_rs2_byp_stageval(5) <= or_reduce(ex5_val_q) and ex5_gpr_we_q; +rf1_rs2_byp_stageval(6) <= or_reduce(ex6_val_q) and ex6_gpr_we_q; +rf1_rs2_byp_stageval(7) <= or_reduce(ex7_val_q) and ex7_gpr_we_q; +rf1_rs2_byp_val(1) <= rf1_rs2_byp_stageval(1) and rf1_s3_vld_q and rf1_rs2_byp_cmp(1); +rf1_rs2_byp_val(2) <= rf1_rs2_byp_stageval(2) and rf1_s3_vld_q and rf1_rs2_byp_cmp(2); +rf1_rs2_byp_val(3) <= rf1_rs2_byp_stageval(3) and rf1_s3_vld_q and rf1_rs2_byp_cmp(3); +rf1_rs2_byp_val(4) <= rf1_rs2_byp_stageval(4) and rf1_s3_vld_q and rf1_rs2_byp_cmp(4); +rf1_rs2_byp_val(5) <= rf1_rs2_byp_stageval(5) and rf1_s3_vld_q and rf1_rs2_byp_cmp(5); +rf1_rs2_byp_val(6) <= rf1_rs2_byp_stageval(6) and rf1_s3_vld_q and rf1_rs2_byp_cmp(6); +rf1_rs2_byp_val(7) <= rf1_rs2_byp_stageval(7) and rf1_s3_vld_q and rf1_rs2_byp_cmp(7); +rf1_rs2_byp_val(8) <= lsu_xu_rel_wren_q and rf1_s3_vld_q and rf1_rs2_byp_cmp(8); +rf1_rs2_sel(1) <= rf1_rs2_byp_val(1); +rf1_rs2_sel(2) <= rf1_rs2_byp_val(2) and not rf1_rs2_byp_val(1); +rf1_rs2_sel(3) <= rf1_rs2_byp_val(3) and not or_reduce(rf1_rs2_byp_val(1 to 2)); +rf1_rs2_sel(4) <= rf1_rs2_byp_val(4) and not or_reduce(rf1_rs2_byp_val(1 to 3)); +rf1_rs2_sel(5) <= rf1_rs2_byp_val(5) and not or_reduce(rf1_rs2_byp_val(1 to 4)); +rf1_rs2_sel(6) <= rf1_rs2_byp_val(6) and not or_reduce(rf1_rs2_byp_val(1 to 5)); +rf1_rs2_sel(7) <= rf1_rs2_byp_val(7) and not or_reduce(rf1_rs2_byp_val(1 to 6)); +rf1_rs2_sel(8) <= rf1_rs2_byp_val(8) and not or_reduce(rf1_rs2_byp_val(1 to 7)); +rf1_rs2_sel(9) <= not or_reduce(rf1_rs2_byp_val(1 to 8)); +dec_byp_rf1_rs2_sel <= rf1_rs2_sel(1 to 9); +dec_alu_rf1_sel(0) <= rf1_sel(0) or rf1_axu_ld_or_st_q or rf1_back_inv_q; +dec_alu_rf1_sel(1 TO 3) <= rf1_sel(1 to 3); +dec_alu_ex1_is_cmp <= ex1_is_cmp_q; +rf1_xer_ca <= byp_dec_rf1_xer_ca; + WITH s2'(rf1_add_ext & rf1_sub) SELECT dec_alu_rf1_add_ci <= rf1_xer_ca when "10", + '1' when "01", + '0' when others; +dec_alu_rf1_add_rs0_inv <= (others=> + (rf1_is_subf or rf1_is_subfc or rf1_is_subfe or + rf1_is_subfic or rf1_is_subfme or rf1_is_subfze or + rf1_is_neg or rf1_cmp)); +rf1_is_tlbsxr <= rf1_is_tlbsx and rf1_instr_q(31); +rf1_is_eratsxr <= rf1_is_eratsx and rf1_instr_q(31); +xu_mm_rf1_is_tlbsxr <= rf1_is_tlbsxr; +dec_alu_rf1_is_cmpl <= rf1_cmp_uext; +dec_alu_rf1_tw_cmpsel <= rf1_is_trap & rf1_instr_q(6 to 10); +dec_byp_ex1_spr_sel <= ex1_spr_sel_q; +xu_lsu_rf1_mtspr_trace <= rf1_mtspr_trace; +dec_alu_rf1_mul_ret <= rf1_is_mulhw or rf1_is_mulhwu or rf1_is_mulhd or rf1_is_mulhdu; +dec_alu_rf1_mul_size <= rf1_is_mulld or rf1_is_mulhd or rf1_is_mulhdu or rf1_is_mulli; +dec_alu_rf1_mul_imm <= rf1_is_mulli; +dec_alu_rf1_mul_sign <= not (rf1_is_mulhdu or rf1_is_mulhwu); +dec_alu_rf1_mul_recform <= rf1_instr_q(31) and + (rf1_is_mulhd or rf1_is_mulhdu or rf1_is_mulhw or + rf1_is_mulhwu or rf1_is_mulld or rf1_is_mullw); +dec_alu_rf1_div_size <= rf1_is_divd or rf1_is_divdu or + rf1_is_divde or rf1_is_divdeu; +dec_alu_rf1_div_extd <= rf1_is_divde or rf1_is_divdeu or + rf1_is_divwe or rf1_is_divweu; +dec_alu_rf1_div_sign <= rf1_is_divw or rf1_is_divd or + rf1_is_divwe or rf1_is_divde; +dec_alu_rf1_div_recform <= rf1_instr_q(31) and + (rf1_is_divd or rf1_is_divdu or + rf1_is_divw or rf1_is_divwu or + rf1_is_divde or rf1_is_divdeu or + rf1_is_divwe or rf1_is_divweu); +dec_cpl_ex3_mult_coll <= ex3_muldiv_coll_q or + ((ex3_div_done_q or alu_ex3_mul_done) and ex3_need_hole_q); +rf1_imm_size <= rf1_imm_size_tbl or rf1_axu_ldst_indexed_b; +rf1_imm_signext <= rf1_imm_signext_tbl or rf1_axu_ldst_indexed_b; + WITH (rf1_is_std or rf1_is_stdu or rf1_is_lwa or rf1_is_ld or rf1_is_ldu) SELECT rf1_16b_imm <= rf1_instr_q(16 to 31) when '0', + rf1_instr_q(16 to 29) & (30 to 31 => tidn) when others; +with rf1_back_inv_q select + rf1_64b_imm <= (0 to (63-real_data_add) => '0') & rf1_back_inv_addr_q & ((64-cl_size) to 63 => '0') when '1', + (0 to 37 => '0') & rf1_instr_q(6 to 31) when others; + WITH s2'((rf1_imm_size and not rf1_back_inv_q) & rf1_imm_signext) SELECT rf1_imm_sign_ext <= (0 to 47 => rf1_16b_imm(0)) & rf1_16b_imm when "11", + (0 to 47 => '0') & rf1_16b_imm when "10", + rf1_64b_imm when others; + WITH (rf1_shift_imm and not rf1_back_inv_q) SELECT rf1_imm_shifted <= rf1_imm_sign_ext when '0', + rf1_imm_sign_ext(16 to 63) & (48 to 63 => '0') when others; +rf1_zero_imm_binv <= rf1_zero_imm and not rf1_back_inv_q; +rf1_ones_imm_binv <= rf1_ones_imm and not rf1_back_inv_q; +dec_byp_rf1_imm <= (rf1_imm_shifted(64-regsize to 63) and (not (64-regsize to 63 => rf1_zero_imm_binv))) or (64-regsize to 63 => rf1_ones_imm_binv); +dec_byp_ex4_is_wchkall <= ex4_is_wchkall_q; +rf1_mfdp <= rf1_is_mfdp or rf1_is_mfdpx or (rf1_axu_mffgpr and rf1_axu_movedp); +rf1_mtdp <= rf1_is_mtdp or rf1_is_mtdpx or (rf1_axu_mftgpr and rf1_axu_movedp); +ex1_mtdp_nr_d <= (rf1_is_mtdp or rf1_is_mtdpx) and not rf1_instr_q(31); +ex1_mtdp_val_d <= rf1_mtdp; +ex1_mfdp_val_d <= rf1_mfdp; +ex4_dp_instr_d <= ex3_mtdp_val_q or ex3_mfdp_val_q; +dec_byp_ex4_dp_instr <= ex4_dp_instr_q and spr_ccr2_en_ditc_q; +dec_byp_ex4_mtdp_val <= ex4_mtdp_val_q and spr_ccr2_en_ditc_q and or_reduce(ex4_val_q); +dec_byp_ex4_mfdp_val <= ex4_mfdp_val_q and spr_ccr2_en_ditc_q and or_reduce(ex4_val_q); +xu_bx_ex1_mtdp_val <= ex1_mtdp_val_q and or_reduce(ex2_val_d); +xu_bx_ex1_mfdp_val <= ex1_mfdp_val_q and or_reduce(ex2_val_d); +xu_bx_ex1_ipc_thrd <= "00" when ex1_tid_q = "1000" else + "01" when ex1_tid_q = "0100" else + "10" when ex1_tid_q = "0010" else + "11" when ex1_tid_q = "0001" else + "00"; +ex1_dp_indexed_d <= rf1_is_mtdpx or rf1_is_mfdpx or + ((rf1_axu_mffgpr or rf1_axu_mftgpr) and rf1_axu_movedp and not rf1_axu_ldst_indexed_b); +with ex1_dp_indexed_q select + ex2_ipb_ba_d <= ex1_instr_q(11 to 15) when '0', + alu_dec_ex1_ipb_ba(27 to 31) when others; +xu_bx_ex2_ipc_ba <= ex2_ipb_ba_q; +ex2_ipb_sz_d <= ex1_instr_q(16 to 17); +xu_bx_ex2_ipc_sz <= ex2_ipb_sz_q; +ex1_ipc_ln <= ex1_instr_q(18 to 19); +ex1_dp_rot_addr <= "01" & ex2_ipb_ba_d(3 to 4) & "00"; +with ex2_ipb_sz_d select + ex1_dp_rot_op_size <= "010000" when "10", + "001000" when "01", + "000100" when "00", + "000000" when others; +ex1_dp_rot_r_amt <= std_ulogic_vector(unsigned(ex1_dp_rot_addr) + unsigned(ex1_dp_rot_op_size)); +ex1_dp_rot_l_amt <= std_ulogic_vector(32 - unsigned(ex1_dp_rot_r_amt)); +ex1_dp_rot_dir <= "10" when (ex2_ipb_ba_d(3 to 4) < ex1_ipc_ln) or (ex1_axu_movedp_q = '0') else + "00" when ex2_ipb_ba_d(3 to 4) = ex1_ipc_ln else + "01" when ex2_ipb_ba_d(3 to 4) > ex1_ipc_ln else + "11"; +with ex1_dp_rot_dir select + ex1_dp_rot_amt <= "000000" when "00", + ex1_dp_rot_r_amt when "01", + ex1_dp_rot_l_amt when "10", + "000000" when others; +ex1_ovr_rotsel_d <= rf1_axu_mffgpr or rf1_axu_mftgpr; +ex1_epid_instr_d <= rf1_xu_epid_instr_q or rf1_axu_is_extload_q or rf1_axu_is_extstore_q; +dec_cpl_ex1_epid_instr <= ex1_epid_instr_q; +xu_lsu_rf1_is_touch <= rf1_is_touch; +rf1_is_touch <= rf1_is_dcbt or rf1_is_dcbtep or rf1_is_dcbtst or rf1_is_dcbtstep or rf1_is_icbt or + ((rf1_is_dcbtls or rf1_is_dcbtstls or rf1_is_dcblc) and not (rf1_th_fld_c or rf1_th_fld_l2)) or + ((rf1_is_icbtls or rf1_is_icblc) and not (rf1_th_fld_c or rf1_th_fld_l2)); +rf1_th_fld_b0 <= rf1_instr_q(6) and (rf1_is_dcbt or rf1_is_dcbtep or rf1_is_dcbtst or rf1_is_dcbtstep); +rf1_th_fld_c <= '1' when (rf1_th_fld_b0='0' and (rf1_instr_q(7 to 10) = "0000")) else '0'; +rf1_th_fld_l2 <= '1' when (rf1_th_fld_b0='0' and (rf1_instr_q(7 to 10) = "0010")) else '0'; +xu_lsu_rf1_target_gpr <= rf1_target_gpr; +with rf1_axu_ld_or_st_q select + rf1_target_gpr <= '0' & rf1_ta_q(0 to 7) when '0', + rf1_axu_ldst_tag_q when others; +ex1_rotsel_ovrd_d <= rf1_axu_ldst_size(1 to 5); +xu_lsu_rf1_derat_ra_eq_ea <= rf1_derat_ra_eq_ea; +rf1_derat_ra_eq_ea <= rf1_back_inv_q or (rf1_val_stg and rf1_is_msgsnd) or rf1_mtspr_trace; +xu_lsu_rf1_thrd_id <= rf1_tid_q; +xu_lsu_rf1_axu_op_val <= rf1_axu_ld_or_st_q; +xu_lsu_rf1_axu_ldst_falign <= rf1_axu_ldst_forcealign and rf1_val_stg; +xu_lsu_rf1_axu_ldst_fexcpt <= rf1_axu_ldst_forceexcept and rf1_val_stg; +with ex1_ovr_rotsel_q select + xu_lsu_ex1_rotsel_ovrd <= ex1_rotsel_ovrd_q when '1', + ex1_dp_rot_amt(1 to 5) when others; +xu_lsu_rf0_act <= rf0_act; +xu_lsu_rf1_cache_acc <= rf1_cache_acc; +rf1_touch_drop <= (rf1_is_dcbt or rf1_is_dcbtep or rf1_is_dcbtst or rf1_is_dcbtstep or rf1_is_icbt or + rf1_is_dcbtls or rf1_is_dcbtstls or rf1_is_dcblc or rf1_is_icbtls or rf1_is_icblc) and not (rf1_th_fld_l2 or rf1_th_fld_c); +rf1_wclr_all <= rf1_is_wclr and not rf1_instr_q(9); +ex1_ddmh_en_d <= rf1_cache_acc and not (rf1_touch_drop or rf1_wclr_all); +dec_cpl_ex3_ddmh_en <= ex3_ddmh_en_q; +dec_cpl_ex3_back_inv <= ex3_back_inv_q; +xu_lsu_rf1_load_instr <= rf1_is_any_load_axu; +xu_lsu_rf1_store_instr <= rf1_is_any_store_axu; +xu_lsu_rf1_l_fld <= rf1_instr_q(9 to 10); +xu_lsu_rf1_th_fld <= rf1_instr_q(6 to 10); +xu_lsu_rf1_mutex_hint <= rf1_instr_q(31); +xu_lsu_rf1_byte_rev <= not or_reduce(rf1_ucode_val_q) and (rf1_is_lhbrx or rf1_is_lwbrx or rf1_is_ldbrx or rf1_is_sthbrx or rf1_is_stwbrx or rf1_is_stdbrx); +xu_lsu_rf1_dcbf_instr <= rf1_is_dcbf or rf1_is_dcbfep; +xu_lsu_rf1_dcbi_instr <= rf1_is_dcbi; +xu_lsu_rf1_dcbz_instr <= rf1_is_dcbz or rf1_is_dcbzep; +xu_lsu_rf1_dcbt_instr <= rf1_is_dcbt or rf1_is_dcbtep; +xu_lsu_rf1_dcbtst_instr <= rf1_is_dcbtst or rf1_is_dcbtstep; +xu_lsu_rf1_dcbtls_instr <= rf1_is_dcbtls; +xu_lsu_rf1_dcbtstls_instr <= rf1_is_dcbtstls; +xu_lsu_rf1_dcblc_instr <= rf1_is_dcblc; +xu_lsu_rf1_dcbst_instr <= rf1_is_dcbst or rf1_is_dcbstep; +xu_lsu_rf1_icbi_instr <= rf1_is_icbi or rf1_is_icbiep; +xu_lsu_rf1_icblc_instr <= rf1_is_icblc; +xu_lsu_rf1_icbt_instr <= rf1_is_icbt; +xu_lsu_rf1_icbtls_instr <= rf1_is_icbtls; +xu_lsu_rf1_lock_instr <= rf1_is_ldarx or rf1_is_lwarx or rf1_is_stdcxr or rf1_is_stwcxr; +xu_lsu_rf1_dci_instr <= rf1_is_dci and rf1_val_stg; +xu_lsu_rf1_ici_instr <= rf1_is_ici and rf1_val_stg; +xu_iu_rf1_val <= rf1_val_iu_q; +xu_rf1_val <= rf1_val_q; +xu_rf1_is_tlbre <= rf1_is_tlbre; +xu_rf1_is_tlbwe <= rf1_is_tlbwe; +xu_rf1_is_tlbsx <= rf1_is_tlbsx; +xu_rf1_is_tlbsrx <= rf1_is_tlbsrx; +xu_rf1_is_tlbilx <= rf1_is_tlbilx; +xu_rf1_is_tlbivax <= rf1_is_tlbivax; +xu_rf1_is_eratre <= rf1_is_eratre; +xu_rf1_is_eratwe <= rf1_is_eratwe; +xu_rf1_is_eratsx <= rf1_is_eratsx; +xu_rf1_is_eratsrx <= rf1_is_eratsrx; +xu_rf1_is_eratilx <= rf1_is_eratilx; +xu_rf1_is_erativax <= rf1_is_erativax; +xu_lsu_rf1_cmd_act <= rf1_cmd_act or or_reduce(rf1_ucode_val_q); +xu_lsu_rf1_derat_act <= rf1_derat_act or or_reduce(rf1_ucode_val_q) or (rf1_val_stg and (rf1_is_isync or rf1_is_csync or rf1_is_eratre or rf1_is_eratwe or + rf1_is_eratsx or rf1_is_eratilx or (rf1_is_wclr and rf1_instr_q(9)))); +xu_lsu_rf1_derat_is_load <= rf1_derat_is_load or (rf1_is_wclr and rf1_instr_q(9)); +xu_lsu_rf1_derat_is_store <= rf1_derat_is_store; +xu_rf1_ws <= rf1_instr_q(19 to 20); +xu_rf1_t <= rf1_instr_q(8 to 10); +xu_ex1_is_isync <= ex1_is_isync_q; +xu_ex1_is_csync <= ex1_is_csync_q; +rf1_is_csync <= rf1_is_sc or rf1_is_mtmsr or rf1_is_ehpriv or + rf1_is_rfi or rf1_is_rfci or rf1_is_rfmci or rf1_is_rfgi or + (rf1_is_mtspr and ((rf1_instr_q(11 to 20) = "1000000001") or + (rf1_instr_q(11 to 20) = "1001001010"))); +rf1_mc_dep_chk_val_d <= fxa_fxb_rf0_mc_dep_chk_val; +rf1_val_w_ldstm <= rf1_val_stg or + or_reduce(rf1_mc_dep_chk_val_q) or + or_reduce(rf1_ucode_val_q); +rf1_targ_vld <= rf1_ta_vld_q when rf1_3src_instr_q = '0' else rf1_s3_vld_q; +rf1_targ_reg <= rf1_ta_q when rf1_3src_instr_q = '0' else rf1_s3_q; +rf1_src0_vld <= rf1_s1_vld_q when rf1_3src_instr_q = '0' else rf1_s1_vld_q; +rf1_src0_reg <= rf1_s1_q when rf1_3src_instr_q = '0' else rf1_s1_q; +rf1_src1_vld <= rf1_s2_vld_q when rf1_3src_instr_q = '0' else rf1_s2_vld_q; +rf1_src1_reg <= rf1_s2_q when rf1_3src_instr_q = '0' else rf1_s2_q; +xu_lsu_rf1_targ_vld <= rf1_targ_vld and rf1_val_w_ldstm; +xu_lsu_rf1_targ_reg <= rf1_targ_reg; +xu_lsu_rf1_src0_vld <= rf1_src0_vld and rf1_val_w_ldstm and not rf1_gpr0_zero_q; +xu_lsu_rf1_src0_reg <= rf1_src0_reg; +xu_lsu_rf1_src1_vld <= rf1_src1_vld and rf1_val_w_ldstm; +xu_lsu_rf1_src1_reg <= rf1_src1_reg; +ex3_tlbsel <= mmucr0_0_tlbsel_q when ex3_tid_q = "1000" else + mmucr0_1_tlbsel_q when ex3_tid_q = "0100" else + mmucr0_2_tlbsel_q when ex3_tid_q = "0010" else + mmucr0_3_tlbsel_q when ex3_tid_q = "0001" else + "00"; + WITH s3'(ex3_tlb_data_val_q & ex3_tlbsel) SELECT dec_byp_ex3_tlb_sel <= "10" when "111", + "01" when "110", + "00" when others; +ex1_tlb_data_val_d <= rf1_is_eratre or rf1_is_eratsx; +rf1_tlbsel(12) <= mmucr0_0_tlbsel_q(4) when rf1_tid_q = "1000" else + mmucr0_1_tlbsel_q(4) when rf1_tid_q = "0100" else + mmucr0_2_tlbsel_q(4) when rf1_tid_q = "0010" else + mmucr0_3_tlbsel_q(4) when rf1_tid_q = "0001" else + '0'; +rf1_tlb_illeg_ws <= (rf1_is_eratwe or rf1_is_eratre) and rf1_instr_q(16 to 18)/="000"; +rf1_tlb_illeg_ws2 <= (rf1_is_eratwe or rf1_is_eratre) and rf1_instr_q(19 to 20)="10" and rf1_spr_msr_cm; +rf1_tlb_illeg_ws3 <= rf1_is_eratwe and rf1_instr_q(19 to 20)="11" and rf1_tlbsel(12)='0'; +rf1_tlb_illeg_t <= rf1_is_tlbilx and rf1_instr_q(8 to 10) = "010"; +rf1_tlb_illeg_sel <= ((rf1_is_tlbwe or rf1_is_tlbre or rf1_is_tlbsx or rf1_is_tlbsrx or rf1_is_tlbilx or rf1_is_tlbivax) and spr_ccr2_notlb_q) + or ((rf1_is_eratwe or rf1_is_eratre or rf1_is_eratsx) and not rf1_tlbsel(12)) + or ((rf1_is_erativax) and not spr_ccr2_notlb_q); +ex1_tlb_illeg_d <= rf1_tlb_illeg_ws or rf1_tlb_illeg_ws2 or rf1_tlb_illeg_ws3 or rf1_tlb_illeg_sel or rf1_tlb_illeg_t; +dec_cpl_ex3_tlb_illeg <= ex3_tlb_illeg_q; +rf1_clear_barrier <= rf1_is_mtmsr or rf1_is_rfci or rf1_is_rfi or rf1_is_rfmci or rf1_is_sc or rf1_is_rfgi or rf1_is_isync; +ex6_clear_barrier_d <= (0 to threads-1 => ex5_clear_barrier_q) and ex6_val_d; +fxb_fxa_ex6_clear_barrier <= ex6_clear_barrier_q; +byp_grp3_debug <= ex1_s1_q & ex1_ta_q(0 to 5) & ex1_gpr_we_q; +byp_grp4_debug <= ex1_s2_q & ex1_ta_q(0 to 5); +byp_grp5_debug <= ex1_s3_q & ex1_ta_q(0 to 5) & ex1_gpr_we_q; +dec_grp0_debug <= rf1_ucode_val_q & + rf1_val_q & + rf1_instr_q & + rf1_cache_acc & + rf1_axu_ld_or_st_q & + rf1_is_any_load_axu & + rf1_is_any_store_axu & + rf1_derat_is_load & + rf1_derat_is_store & + rf1_derat_ra_eq_ea & + rf1_axu_ldst_forcealign & + rf1_axu_ldst_forceexcept & + rf1_is_any_load_dac & + rf1_is_any_store_dac & + rf1_is_touch & + rf1_target_gpr & + rf1_targ_vld & + rf1_targ_reg & + rf1_src0_vld & + rf1_src0_reg & + rf1_src1_vld & + rf1_src1_reg; +dec_grp1_debug <= rf1_ucode_val_q & + rf1_val_q & + rf1_instr_q & + rf1_cache_acc & + rf1_axu_ld_or_st_q & + rf1_is_any_load_axu & + rf1_is_any_store_axu & + rf1_derat_is_load & + rf1_derat_is_store & + rf1_derat_ra_eq_ea & + rf1_axu_ldst_forcealign & + rf1_axu_ldst_forceexcept & + rf1_is_any_load_dac & + rf1_is_any_store_dac & + rf1_back_inv_q & + rf1_back_inv_addr_q; +rf1_is_attn <= '1' when rf1_opcode_is_0 and rf1_instr_21to30_00_q(21 to 30) = "0100000000" else '0'; +rf1_is_bc <= '1' when rf1_instr_q( 0 to 5) = "010000" else '0'; +rf1_is_bclr <= '1' when rf1_opcode_is_19 and rf1_instr_21to30_00_q(21 to 30) = "0000010000" else '0'; +rf1_is_dcbf <= '1' when rf1_opcode_is_31_q(0) = '1' and rf1_instr_21to30_00_q(21 to 30) = "0001010110" else '0'; +rf1_is_dcbi <= '1' when rf1_opcode_is_31_q(0) = '1' and rf1_instr_21to30_00_q(21 to 30) = "0111010110" else '0'; +rf1_is_dcbst <= '1' when rf1_opcode_is_31_q(0) = '1' and rf1_instr_21to30_00_q(21 to 30) = "0000110110" else '0'; +rf1_is_dcblc <= '1' when rf1_opcode_is_31_q(0) = '1' and rf1_instr_21to30_00_q(21 to 30) = "0110000110" else '0'; +rf1_is_dcbt <= '1' when rf1_opcode_is_31_q(0) = '1' and rf1_instr_21to30_00_q(21 to 30) = "0100010110" else '0'; +rf1_is_dcbtls <= '1' when rf1_opcode_is_31_q(0) = '1' and rf1_instr_21to30_00_q(21 to 30) = "0010100110" else '0'; +rf1_is_dcbtst <= '1' when rf1_opcode_is_31_q(0) = '1' and rf1_instr_21to30_01_q(21 to 30) = "0011110110" else '0'; +rf1_is_dcbtstls <= '1' when rf1_opcode_is_31_q(0) = '1' and rf1_instr_21to30_01_q(21 to 30) = "0010000110" else '0'; +rf1_is_dcbz <= '1' when rf1_opcode_is_31_q(1) = '1' and rf1_instr_21to30_01_q(21 to 30) = "1111110110" else '0'; +rf1_is_dci <= '1' when rf1_opcode_is_31_q(1) = '1' and rf1_instr_21to30_01_q(21 to 30) = "0111000110" else '0'; +rf1_is_eratilx <= '1' when rf1_opcode_is_31_q(1) = '1' and rf1_instr_21to30_01_q(21 to 30) = "0000110011" else '0'; +rf1_is_erativax <= '1' when rf1_opcode_is_31_q(1) = '1' and rf1_instr_21to30_01_q(21 to 30) = "1100110011" else '0'; +rf1_is_eratre <= '1' when rf1_opcode_is_31_q(1) = '1' and rf1_instr_21to30_01_q(21 to 30) = "0010110011" else '0'; +rf1_is_eratsx <= '1' when rf1_opcode_is_31_q(1) = '1' and rf1_instr_21to30_01_q(21 to 30) = "0010010011" else '0'; +rf1_is_eratsrx <= '1' when rf1_opcode_is_31_q(1) = '1' and rf1_instr_21to30_02_q(21 to 30) = "1101110011" else '0'; +rf1_is_eratwe <= '1' when rf1_opcode_is_31_q(1) = '1' and rf1_instr_21to30_02_q(21 to 30) = "0011010011" else '0'; +rf1_is_ici <= '1' when rf1_opcode_is_31_q(2) = '1' and rf1_instr_21to30_02_q(21 to 30) = "1111000110" else '0'; +rf1_is_icbi <= '1' when rf1_opcode_is_31_q(2) = '1' and rf1_instr_21to30_02_q(21 to 30) = "1111010110" else '0'; +rf1_is_icblc <= '1' when rf1_opcode_is_31_q(2) = '1' and rf1_instr_21to30_02_q(21 to 30) = "0011100110" else '0'; +rf1_is_icbt <= '1' when rf1_opcode_is_31_q(2) = '1' and rf1_instr_21to30_02_q(21 to 30) = "0000010110" else '0'; +rf1_is_icbtls <= '1' when rf1_opcode_is_31_q(2) = '1' and rf1_instr_21to30_02_q(21 to 30) = "0111100110" else '0'; +rf1_is_isync <= '1' when rf1_opcode_is_19 and rf1_instr_21to30_02_q(21 to 30) = "0010010110" else '0'; +rf1_is_ld <= '1' when rf1_opcode_is_58 and rf1_instr_q(30 to 31) = "00" else '0'; +rf1_is_ldarx <= '1' when rf1_opcode_is_31_q(2) = '1' and rf1_instr_21to30_03_q(21 to 30) = "0001010100" else '0'; +rf1_is_ldbrx <= '1' when rf1_opcode_is_31_q(2) = '1' and rf1_instr_21to30_03_q(21 to 30) = "1000010100" else '0'; +rf1_is_ldu <= '1' when rf1_opcode_is_58 and rf1_instr_q(30 to 31) = "01" else '0'; +rf1_is_lhbrx <= '1' when rf1_opcode_is_31_q(2) = '1' and rf1_instr_21to30_03_q(21 to 30) = "1100010110" else '0'; +rf1_is_lmw <= '1' when rf1_instr_q( 0 to 5) = "101110" else '0'; +rf1_is_lswi <= '1' when rf1_opcode_is_31_q(3) = '1' and rf1_instr_21to30_03_q(21 to 30) = "1001010101" else '0'; +rf1_is_lswx <= '1' when rf1_opcode_is_31_q(3) = '1' and rf1_instr_21to30_03_q(21 to 30) = "1000010101" else '0'; +rf1_is_lwa <= '1' when rf1_opcode_is_58 and rf1_instr_q(30 to 31) = "10" else '0'; +rf1_is_lwarx <= '1' when rf1_opcode_is_31_q(3) = '1' and rf1_instr_21to30_03_q(21 to 30) = "0000010100" else '0'; +rf1_is_lwbrx <= '1' when rf1_opcode_is_31_q(3) = '1' and rf1_instr_21to30_03_q(21 to 30) = "1000010110" else '0'; +rf1_is_mfcr <= '1' when rf1_opcode_is_31_q(3) = '1' and (rf1_instr_21to30_03_q(21 to 30) & rf1_instr_q(11) = "00000100110") else '0'; +rf1_is_mfdp <= '1' when rf1_opcode_is_31_q(3) = '1' and rf1_instr_21to30_04_q(21 to 30) = "0000100011" else '0'; +rf1_is_mfdpx <= '1' when rf1_opcode_is_31_q(3) = '1' and rf1_instr_21to30_04_q(21 to 30) = "0000000011" else '0'; +rf1_is_mtdp <= '1' when rf1_opcode_is_31_q(3) = '1' and rf1_instr_21to30_04_q(21 to 30) = "0001100011" else '0'; +rf1_is_mtdpx <= '1' when rf1_opcode_is_31_q(4) = '1' and rf1_instr_21to30_04_q(21 to 30) = "0001000011" else '0'; +rf1_is_mfspr <= '1' when rf1_opcode_is_31_q(4) = '1' and rf1_instr_21to30_04_q(21 to 30) = "0101010011" else '0'; +rf1_is_mtcrf <= '1' when rf1_opcode_is_31_q(4) = '1' and rf1_instr_21to30_04_q(21 to 30) = "0010010000" else '0'; +rf1_is_mtmsr <= '1' when rf1_opcode_is_31_q(4) = '1' and rf1_instr_21to30_04_q(21 to 30) = "0010010010" else '0'; +rf1_is_mtspr <= '1' when rf1_opcode_is_31_q(4) = '1' and rf1_instr_21to30_04_q(21 to 30) = "0111010011" else '0'; +rf1_is_neg <= '1' when rf1_opcode_is_31_q(4) = '1' and rf1_instr_21to30_05_q(22 to 30) = "001101000" else '0'; +rf1_is_rfci <= '1' when rf1_opcode_is_19 and rf1_instr_21to30_05_q(21 to 30) = "0000110011" else '0'; +rf1_is_rfi <= '1' when rf1_opcode_is_19 and rf1_instr_21to30_05_q(21 to 30) = "0000110010" else '0'; +rf1_is_rfmci <= '1' when rf1_opcode_is_19 and rf1_instr_21to30_05_q(21 to 30) = "0000100110" else '0'; +rf1_is_sc <= '1' when rf1_instr_q( 0 to 5) = "010001" else '0'; +rf1_is_std <= '1' when rf1_opcode_is_62 and rf1_instr_q(30 to 31) = "00" else '0'; +rf1_is_stdbrx <= '1' when rf1_opcode_is_31_q(4) = '1' and rf1_instr_21to30_05_q(21 to 30) = "1010010100" else '0'; +rf1_is_stdcxr <= '1' when rf1_opcode_is_31_q(4) = '1' and rf1_instr_21to30_05_q(21 to 30) = "0011010110" else '0'; +rf1_is_stdu <= '1' when rf1_opcode_is_62 and rf1_instr_q(30 to 31) = "01" else '0'; +rf1_is_sthbrx <= '1' when rf1_opcode_is_31_q(5) = '1' and rf1_instr_21to30_05_q(21 to 30) = "1110010110" else '0'; +rf1_is_stwcxr <= '1' when rf1_opcode_is_31_q(5) = '1' and rf1_instr_21to30_05_q(21 to 30) = "0010010110" else '0'; +rf1_is_stwbrx <= '1' when rf1_opcode_is_31_q(5) = '1' and rf1_instr_21to30_06_q(21 to 30) = "1010010110" else '0'; +rf1_is_subf <= '1' when rf1_opcode_is_31_q(5) = '1' and rf1_instr_21to30_06_q(22 to 30) = "000101000" else '0'; +rf1_is_subfc <= '1' when rf1_opcode_is_31_q(5) = '1' and rf1_instr_21to30_06_q(22 to 30) = "000001000" else '0'; +rf1_is_subfe <= '1' when rf1_opcode_is_31_q(5) = '1' and rf1_instr_21to30_06_q(22 to 30) = "010001000" else '0'; +rf1_is_subfic <= '1' when rf1_instr_q( 0 to 5) = "001000" else '0'; +rf1_is_subfme <= '1' when rf1_opcode_is_31_q(5) = '1' and rf1_instr_21to30_06_q(22 to 30) = "011101000" else '0'; +rf1_is_subfze <= '1' when rf1_opcode_is_31_q(5) = '1' and rf1_instr_21to30_06_q(22 to 30) = "011001000" else '0'; +rf1_is_td <= '1' when rf1_opcode_is_31_q(6) = '1' and rf1_instr_21to30_06_q(21 to 30) = "0001000100" else '0'; +rf1_is_tdi <= '1' when rf1_instr_q( 0 to 5) = "000010" else '0'; +rf1_is_tlbilx <= '1' when rf1_opcode_is_31_q(6) = '1' and rf1_instr_21to30_06_q(21 to 30) = "0000010010" else '0'; +rf1_is_tlbivax <= '1' when rf1_opcode_is_31_q(6) = '1' and rf1_instr_21to30_07_q(21 to 30) = "1100010010" else '0'; +rf1_is_tlbre <= '1' when rf1_opcode_is_31_q(6) = '1' and rf1_instr_21to30_07_q(21 to 30) = "1110110010" else '0'; +rf1_is_tlbsx <= '1' when rf1_opcode_is_31_q(6) = '1' and rf1_instr_21to30_07_q(21 to 30) = "1110010010" else '0'; +rf1_is_tlbsrx <= '1' when rf1_opcode_is_31_q(6) = '1' and rf1_instr_21to30_07_q(21 to 30) = "1101010010" else '0'; +rf1_is_tlbwe <= '1' when rf1_opcode_is_31_q(6) = '1' and rf1_instr_21to30_07_q(21 to 30) = "1111010010" else '0'; +rf1_is_tlbwec <= '0'; +rf1_is_tw <= '1' when rf1_opcode_is_31_q(6) = '1' and rf1_instr_21to30_07_q(21 to 30) = "0000000100" else '0'; +rf1_is_twi <= '1' when rf1_instr_q( 0 to 5) = "000011" else '0'; +rf1_is_wrtee <= '1' when rf1_opcode_is_31_q(7) = '1' and rf1_instr_21to30_07_q(21 to 30) = "0010000011" else '0'; +rf1_is_dcbstep <= '1' when rf1_opcode_is_31_q(7) = '1' and rf1_instr_21to30_07_q(21 to 30) = "0000111111" else '0'; +rf1_is_dcbtep <= '1' when rf1_opcode_is_31_q(7) = '1' and rf1_instr_21to30_08_q(21 to 30) = "0100111111" else '0'; +rf1_is_dcbfep <= '1' when rf1_opcode_is_31_q(7) = '1' and rf1_instr_21to30_08_q(21 to 30) = "0001111111" else '0'; +rf1_is_dcbtstep <= '1' when rf1_opcode_is_31_q(7) = '1' and rf1_instr_21to30_08_q(21 to 30) = "0011111111" else '0'; +rf1_is_icbiep <= '1' when rf1_opcode_is_31_q(7) = '1' and rf1_instr_21to30_08_q(21 to 30) = "1111011111" else '0'; +rf1_is_dcbzep <= '1' when rf1_opcode_is_31_q(7) = '1' and rf1_instr_21to30_08_q(21 to 30) = "1111111111" else '0'; +rf1_is_rfgi <= '1' when rf1_opcode_is_19 and rf1_instr_21to30_08_q(21 to 30) = "0001100110" else '0'; +rf1_is_ehpriv <= '1' when rf1_opcode_is_31_q(7) = '1' and rf1_instr_21to30_08_q(21 to 30) = "0100001110" else '0'; +rf1_is_msgclr <= '1' when rf1_opcode_is_31_q(8) = '1' and rf1_instr_21to30_08_q(21 to 30) = "0011101110" else '0'; +rf1_is_msgsnd <= '1' when rf1_opcode_is_31_q(8) = '1' and rf1_instr_21to30_09_q(21 to 30) = "0011001110" else '0'; +rf1_is_icswx <= '1' when rf1_opcode_is_31_q(8) = '1' and rf1_instr_21to30_09_q(21 to 30) = "0110010110" else '0'; +rf1_is_icswepx <= '1' when rf1_opcode_is_31_q(8) = '1' and rf1_instr_21to30_09_q(21 to 30) = "1110110110" else '0'; +rf1_is_wchkall <= '1' when rf1_opcode_is_31_q(8) = '1' and rf1_instr_21to30_09_q(21 to 30) = "1110000110" else '0'; +rf1_is_wclr <= '1' when rf1_opcode_is_31_q(8) = '1' and rf1_instr_21to30_09_q(21 to 30) = "1110100110" else '0'; +rf1_is_mfdcr <= '1' when rf1_opcode_is_31_q(8) = '1' and rf1_instr_21to30_09_q(21 to 30) = "0101000011" else '0'; +rf1_is_mfdcrux <= '1' when rf1_opcode_is_31_q(8) = '1' and rf1_instr_21to30_09_q(21 to 30) = "0100100011" else '0'; +rf1_is_mfdcrx <= '1' when rf1_opcode_is_31_q(9) = '1' and rf1_instr_21to30_09_q(21 to 30) = "0100000011" else '0'; +rf1_is_mtdcr <= '1' when rf1_opcode_is_31_q(9) = '1' and rf1_instr_21to30_10_q(21 to 30) = "0111000011" else '0'; +rf1_is_mtdcrux <= '1' when rf1_opcode_is_31_q(9) = '1' and rf1_instr_21to30_10_q(21 to 30) = "0110100011" else '0'; +rf1_is_mtdcrx <= '1' when rf1_opcode_is_31_q(9) = '1' and rf1_instr_21to30_10_q(21 to 30) = "0110000011" else '0'; +rf1_is_mulhd <= '1' when rf1_opcode_is_31 and rf1_instr_q(22 to 30) = "001001001" else '0'; +rf1_is_mulhdu <= '1' when rf1_opcode_is_31 and rf1_instr_q(22 to 30) = "000001001" else '0'; +rf1_is_mulhw <= '1' when rf1_opcode_is_31 and rf1_instr_q(22 to 30) = "001001011" else '0'; +rf1_is_mulhwu <= '1' when rf1_opcode_is_31 and rf1_instr_q(22 to 30) = "000001011" else '0'; +rf1_is_mulld <= '1' when rf1_opcode_is_31 and rf1_instr_q(22 to 30) = "011101001" else '0'; +rf1_is_mulli <= '1' when rf1_instr_q( 0 to 5) = "000111" else '0'; +rf1_is_mullw <= '1' when rf1_opcode_is_31 and rf1_instr_q(22 to 30) = "011101011" else '0'; +rf1_is_divd <= '1' when rf1_opcode_is_31 and rf1_instr_q(22 to 30) = "111101001" else '0'; +rf1_is_divdu <= '1' when rf1_opcode_is_31 and rf1_instr_q(22 to 30) = "111001001" else '0'; +rf1_is_divw <= '1' when rf1_opcode_is_31 and rf1_instr_q(22 to 30) = "111101011" else '0'; +rf1_is_divwu <= '1' when rf1_opcode_is_31 and rf1_instr_q(22 to 30) = "111001011" else '0'; +rf1_is_divwe <= '1' when rf1_opcode_is_31 and rf1_instr_q(22 to 30) = "110101011" else '0'; +rf1_is_divweu <= '1' when rf1_opcode_is_31 and rf1_instr_q(22 to 30) = "110001011" else '0'; +rf1_is_divde <= '1' when rf1_opcode_is_31 and rf1_instr_q(22 to 30) = "110101001" else '0'; +rf1_is_divdeu <= '1' when rf1_opcode_is_31 and rf1_instr_q(22 to 30) = "110001001" else '0'; +opcode_31_gen : for i in 0 to 9 generate +rf1_opcode_is_31_d(i) <= rf0_opcode_is_31; +end generate; +rf1_instr_21to30_00_d <= fxa_fxb_rf0_instr(21 to 30); +rf1_instr_21to30_01_d <= fxa_fxb_rf0_instr(21 to 30); +rf1_instr_21to30_02_d <= fxa_fxb_rf0_instr(21 to 30); +rf1_instr_21to30_03_d <= fxa_fxb_rf0_instr(21 to 30); +rf1_instr_21to30_04_d <= fxa_fxb_rf0_instr(21 to 30); +rf1_instr_21to30_05_d <= fxa_fxb_rf0_instr(21 to 30); +rf1_instr_21to30_06_d <= fxa_fxb_rf0_instr(21 to 30); +rf1_instr_21to30_07_d <= fxa_fxb_rf0_instr(21 to 30); +rf1_instr_21to30_08_d <= fxa_fxb_rf0_instr(21 to 30); +rf1_instr_21to30_09_d <= fxa_fxb_rf0_instr(21 to 30); +rf1_instr_21to30_10_d <= fxa_fxb_rf0_instr(21 to 30); +rf0_opcode_is_31 <= '1' when fxa_fxb_rf0_instr(0 to 5) = "011111" else '0'; +rf1_opcode_is_31 <= rf1_instr_q(0 to 5) = "011111"; +rf1_opcode_is_0 <= rf1_instr_q(0 to 5) = "000000"; +rf1_opcode_is_19 <= rf1_instr_q(0 to 5) = "010011"; +rf1_opcode_is_62 <= rf1_instr_q(0 to 5) = "111110"; +rf1_opcode_is_58 <= rf1_instr_q(0 to 5) = "111010"; +-- +-- Final Table Listing +-- *INPUTS*========================*OUTPUTS*==============================================* +-- | | | +-- | rf1_instr_q | | +-- | | rf1_instr_q | | +-- | | | rf1_instr_q | | +-- | | | | | | +-- | | | | | dec_byp_rf1_is_mcrf | +-- | | | | | | dec_byp_rf1_is_mtcrf | +-- | | | | | | | rf1_add_ext | +-- | | | | | | | | rf1_alu_cmp | +-- | | | | | | | | | rf1_cmp | +-- | | | | | | | | | | rf1_cmp_uext | +-- | | | | | | | | | | | rf1_cr_so_update | +-- | | | | | | | | | | | | rf1_cr_we | +-- | | | | | | | | | | | | | rf1_imm_signext_tbl | +-- | | | | | | | | | | | | | | rf1_imm_size_tbl | +-- | | | | | | | | | | | | | | | rf1_instr_hypv_tbl | +-- | | | | | | | | | | | | | | | | rf1_instr_priv_tbl | +-- | | | | | | | | | | | | | | | | | rf1_is_trap | +-- | | | | | | | | | | | | | | | | | | rf1_ones_imm | +-- | | | | | | | | | | | | | | | | | | | rf1_sel | +-- | | | | | | | | | | | | | | | | | | | | rf1_shift_imm | +-- | | | | | | | | | | | | | | | | | | | | | rf1_spr_sel | +-- | | | | | | | | | | | | | | | | | | | | | | rf1_sub | +-- | | | | | | | | | | | | | | | | | | | | | | | rf1_zero_imm | +-- | | | | | | | | | | | | | | | | | | | | | | | | | +-- | 000000 2222222223 33 | | | | | | | 00 | | | | | | | 0000 | | | | | +-- | 012345 1234567890 01 | | | | | | | 01 | | | | | | | 0123 | | | | | +-- *TYPE*==========================+======================================================+ +-- | PPPPPP PPPPPPPPPP PP | P P P P P P PP P P P P P P P PPPP P P P P | +-- *POLARITY*--------------------->| + + + + + + ++ + + + + + + + ++++ + + + + | +-- *PHASE*------------------------>| T T T T T T TT T T T T T T T TTTT T T T T | +-- *TERMS*=========================+======================================================+ +-- 1 | 010011 1000010000 -- | . . . . . . .. . . . . . . . .... . 1 . . | +-- 2 | 010011 0000000000 -- | 1 . . . . . .. 1 . . . . . . .... . . . . | +-- 3 | 010011 0000100110 -- | . . . . . . .. . . . 1 . . . .... . . . . | +-- 4 | 010011 0000110011 -- | . . . . . . .. . . . 1 . . . .... . . . . | +-- 5 | 010011 0-11000001 -- | . . . . . . 1. 1 . . . . . . .... . . . . | +-- 6 | 011111 0111111100 -- | . . . . . . .. . . . . . . . ...1 . . . . | +-- 7 | 010011 01-0100001 -- | . . . . . . 1. 1 . . . . . . .... . . . . | +-- 8 | 010011 0011-00001 -- | . . . . . . 1. 1 . . . . . . .... . . . . | +-- 9 | 010011 0-00100001 -- | . . . . . . 1. 1 . . . . . . .... . . . . | +-- 10 | 010011 0100-00001 -- | . . . . . . 1. 1 . . . . . . .... . . . . | +-- 11 | 010011 001-000001 -- | . . . . . . 1. 1 . . . . . . .... . . . . | +-- 12 | 011111 0101001110 -- | . . . . . . .. . . . . . . . .... . 1 . . | +-- 13 | 010011 000-100110 -- | . . . . . . .. . . . . 1 . . .... . 1 . . | +-- 14 | 011111 0000100000 -- | . . . . . 1 .. . . . . . . . .... . . . . | +-- 15 | 011111 0100001110 -- | . . . . . . .. . . . . 1 . . .... . . . . | +-- 16 | 010011 000011001- -- | . . . . . . .. . . . . 1 . . .... . 1 . . | +-- 17 | 011111 0010010000 -- | . 1 . . . . 1. . . . . . . . .... . . . . | +-- 18 | 011111 1000110110 -- | . . . . . . .. . . . 1 1 . . .... . . . . | +-- 19 | 011111 0001010011 -- | . . . . . . .. . . . . 1 . . .... . 1 . . | +-- 20 | 011111 -111000110 -- | . . . . . . .. . . . . 1 . . .... . . . . | +-- 21 | 01-111 110011101- -- | . . . . . . .. . . . . . . . .1.. . . . . | +-- 22 | 011111 1100110011 -- | . . . . . . .. . . . 1 1 . . 1... . . . . | +-- 23 | 011111 -001101000 -- | . . . . . . .. . . . . . . . 1... . . 1 1 | +-- 24 | 01-111 111-011010 -- | . . . . . . .. . . . . . . . .1.. . . . . | +-- 25 | 011111 1111-11111 -- | . . . . . . .. . . . . 1 . . 1... . . . . | +-- 26 | 011111 1110110-10 -- | . . . . . . .. . . . . 1 . . .... . . . . | +-- 27 | 011111 0111010110 -- | . . . . . . .. . . . . 1 . . 1... . . . . | +-- 28 | 011111 0101-10011 -- | . . . . . . .. . . . . . . . .... . 1 . . | +-- 29 | 011111 1110-10010 -- | . . . . . . .. . . . 1 . . . .... . . . . | +-- 30 | 01111- -000011000 -- | . . . . . . .. . . . . . . . .1.. . . . . | +-- 31 | 011111 0010100011 -- | . . . . . . .. . . 1 . 1 . . 1... . . . . | +-- 32 | 011--1 011-011100 -- | . . . . . . .. . . . . . . . ..1. . . . . | +-- 33 | 011111 -0110010-0 -- | . . . . . . .. . . . . . . . .... . . . 1 | +-- 34 | 011111 10-1010101 -- | . . . . . . .. . . 1 . . . . 1... . . . 1 | +-- 35 | 011111 0010000011 -- | . . . . . . .. . . . . 1 . . 1... . . . 1 | +-- 36 | 011--1 000-111100 -- | . . . . . . .. . . . . . . . ..1. . . . . | +-- 37 | 01-111 -000011011 -- | . . . . . . .. . . . . . . . .1.. . . . . | +-- 38 | 0-1111 11101-0110 -- | . . . . . . .. . . . . . . . 1... . . . . | +-- 39 | 011111 00100100-0 -- | . . . . . . .. . . . . . . . .... . . . 1 | +-- 40 | 011111 -0111010-0 -- | . . 1 . . . .. . . . . . . 1 1... . . . . | +-- 41 | 011111 0011-01110 -- | . . . . . . .. . . . 1 1 . . 1... . . . . | +-- 42 | 0-1111 0-11100110 -- | . . . . . . .. . . . . . . . 1... . . . . | +-- 43 | 011111 0-11010011 -- | . . . . . . .. . . . . . . . 1... . . . 1 | +-- 44 | 011111 001-010011 -- | . . . . . . .. . . . 1 1 . . .... . . . . | +-- 45 | 011111 000-000100 -- | . . . . 1 . .. . . . . . 1 . 1... . . 1 . | +-- 46 | 011111 00-0110011 -- | . . . . . . .. . . . 1 1 . . .... . . . . | +-- 47 | 011111 11-0010010 -- | . . . . . . .. . . . 1 . . . 1... . . . . | +-- 48 | 01-111 1100-110-0 -- | . . . . . . .. . . . . . . . .1.. . . . . | +-- 49 | 0-1111 110-010010 -- | . . . . . . .. . . . . . . . 1... . . . . | +-- 50 | 01-111 11-0-11010 -- | . . . . . . .. . . . . . . . .1.. . . . . | +-- 51 | 011111 11--010010 -- | . . . . . . .. . . . . 1 . . .... . . . . | +-- 52 | 011111 0000-00000 -- | . . . 1 1 . .1 1 . . . . . . 1... . . 1 . | +-- 53 | 011111 -000-01000 -- | . . . . . . .. . . . . . . . 1... . . 1 . | +-- 54 | 0-1111 0000110-11 -- | . . . . . . .. . . . . . . . 1... . . . . | +-- 55 | 011111 000--00011 -- | . . . . . . .. . . . . 1 . . .... . . . . | +-- 56 | 0-1111 0010-00110 -- | . . . . . . .. . . . . . . . 1... . . . . | +-- 57 | 011--1 01-0-11100 -- | . . . . . . .. . . . . . . . ..1. . . . . | +-- 58 | 011--1 0-00-11100 -- | . . . . . . .. . . . . . . . ..1. . . . . | +-- 59 | 011111 00-1-11111 -- | . . . . . . .. . . . . 1 . . 1... . . . . | +-- 60 | 0-1111 111--10110 -- | . . . . . . .. . . . . . . . 1... . . . . | +-- 61 | 0-1111 0101-101-1 -- | . . . . . . .. . . . . . . . 1... . . . . | +-- 62 | 0-1111 --00001010 -- | . . . . . . .. . . . . . . . 1... . . . . | +-- 63 | 0-1111 10-001010- -- | . . . . . . .. . . . . . . . 1... . . . . | +-- 64 | 011111 00-0010010 -- | . . . . . . .. . . . . 1 . . 1... . . . . | +-- 65 | 011111 00-00111-1 -- | . . . . . . .. . . . . 1 . . 1... . . . . | +-- 66 | 011111 0--0011111 -- | . . . . . . .. . . . . 1 . . 1... . . . . | +-- 67 | 011111 0-00-11111 -- | . . . . . . .. . . . . 1 . . 1... . . . . | +-- 68 | 011111 -01-0010-0 -- | . . 1 . . . .. . . . . . . . 1... . . . . | +-- 69 | 0-1111 0011-1011- -- | . . . . . . .. . . . . . . . 1... . . . . | +-- 70 | 0-1111 00-10101-0 -- | . . . . . . .. . . . . . . . 1... . . . . | +-- 71 | 0-1111 0-100-0110 -- | . . . . . . .. . . . . . . . 1... . . . . | +-- 72 | 0-1111 00000101-- -- | . . . . . . .. . . . . . . . 1... . . . . | +-- 73 | 0-1111 0000-1011- -- | . . . . . . .. . . . . . . . 1... . . . . | +-- 74 | 0-1111 000--1-111 -- | . . . . . . .. . . . . . . . 1... . . . . | +-- 75 | 0-1111 00-0-101-1 -- | . . . . . . .. . . . . . . . 1... . . . . | +-- 76 | 0-1111 ---0010110 -- | . . . . . . .. . . . . . . . 1... . . . . | +-- 77 | 0-1111 0--0-10111 -- | . . . . . . .. . . . . . . . 1... . . . . | +-- 78 | 011--1 -----01111 -- | . . . . . . .. . . . . . . . ..1. . . . . | +-- 79 | 010000 ---------- -- | . . . . . . .. . 1 1 . . . . .... . . . . | +-- 80 | 1-1010 ---------- -0 | . . . . . . .. . 1 1 . . . . 1... . . . . | +-- 81 | 011110 -------00- -- | . . . . . . .. . . . . . . . .1.. . . . . | +-- 82 | 001000 ---------- -- | . . . . . . .. . 1 1 . . . . 1... . . 1 . | +-- 83 | 001010 ---------- -- | . . . . . 1 .. . . 1 . . . . .... . . . . | +-- 84 | 1-1-10 ---------- 0- | . . . . . . .. . 1 1 . . . . 1... . . . . | +-- 85 | 011110 ------0--- -- | . . . . . . .. . . . . . . . .1.. . . . . | +-- 86 | 01010- ---------- -- | . . . . . . .. . . . . . . . .1.. . . . . | +-- 87 | 00001- ---------- -- | . . . . 1 . .. . 1 1 . . 1 . 1... . . 1 . | +-- 88 | 001111 ---------- -- | . . . . . . .. . . . . . . . .... 1 . . . | +-- 89 | 011-01 ---------- -- | . . . . . . .. . . . . . . . .... 1 . . . | +-- 90 | 0101-1 ---------- -- | . . . . . . .. . . . . . . . .1.. . . . . | +-- 91 | 0110-1 ---------- -- | . . . . . . .. . . . . . . . .... 1 . . . | +-- 92 | 00101- ---------- -- | . . . 1 1 . .1 1 . . . . . . 1... . . 1 . | +-- 93 | 011-0- ---------- -- | . . . . . . .. . . 1 . . . . ..1. . . . . | +-- 94 | 10---- ---------- -- | . . . . . . .. . 1 1 . . . . 1... . . . . | +-- 95 | 0110-- ---------- -- | . . . . . . .. . . 1 . . . . ..1. . . . . | +-- 96 | -0--11 ---------- -- | . . . . . . .. . 1 1 . . . . .... . . . . | +-- 97 | -011-- ---------- -- | . . . . . . .. . 1 1 . . . . 1... . . . . | +-- *======================================================================================* +-- +-- Table TBL_MASTER_DEC Signal Assignments for Product Terms +MQQ1:TBL_MASTER_DEC_PT(1) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0100111000010000")); +MQQ2:TBL_MASTER_DEC_PT(2) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0100110000000000")); +MQQ3:TBL_MASTER_DEC_PT(3) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0100110000100110")); +MQQ4:TBL_MASTER_DEC_PT(4) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0100110000110011")); +MQQ5:TBL_MASTER_DEC_PT(5) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("010011011000001")); +MQQ6:TBL_MASTER_DEC_PT(6) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111110111111100")); +MQQ7:TBL_MASTER_DEC_PT(7) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("010011010100001")); +MQQ8:TBL_MASTER_DEC_PT(8) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("010011001100001")); +MQQ9:TBL_MASTER_DEC_PT(9) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("010011000100001")); +MQQ10:TBL_MASTER_DEC_PT(10) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("010011010000001")); +MQQ11:TBL_MASTER_DEC_PT(11) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("010011001000001")); +MQQ12:TBL_MASTER_DEC_PT(12) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111110101001110")); +MQQ13:TBL_MASTER_DEC_PT(13) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("010011000100110")); +MQQ14:TBL_MASTER_DEC_PT(14) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111110000100000")); +MQQ15:TBL_MASTER_DEC_PT(15) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111110100001110")); +MQQ16:TBL_MASTER_DEC_PT(16) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) ) , STD_ULOGIC_VECTOR'("010011000011001")); +MQQ17:TBL_MASTER_DEC_PT(17) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111110010010000")); +MQQ18:TBL_MASTER_DEC_PT(18) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111111000110110")); +MQQ19:TBL_MASTER_DEC_PT(19) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111110001010011")); +MQQ20:TBL_MASTER_DEC_PT(20) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111111000110")); +MQQ21:TBL_MASTER_DEC_PT(21) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(21) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) + ) , STD_ULOGIC_VECTOR'("01111110011101")); +MQQ22:TBL_MASTER_DEC_PT(22) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111111100110011")); +MQQ23:TBL_MASTER_DEC_PT(23) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111001101000")); +MQQ24:TBL_MASTER_DEC_PT(24) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(21) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111111011010")); +MQQ25:TBL_MASTER_DEC_PT(25) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111111111111")); +MQQ26:TBL_MASTER_DEC_PT(26) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111111011010")); +MQQ27:TBL_MASTER_DEC_PT(27) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111110111010110")); +MQQ28:TBL_MASTER_DEC_PT(28) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111010110011")); +MQQ29:TBL_MASTER_DEC_PT(29) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111111010010")); +MQQ30:TBL_MASTER_DEC_PT(30) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111000011000")); +MQQ31:TBL_MASTER_DEC_PT(31) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111110010100011")); +MQQ32:TBL_MASTER_DEC_PT(32) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("0111011011100")); +MQQ33:TBL_MASTER_DEC_PT(33) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111101100100")); +MQQ34:TBL_MASTER_DEC_PT(34) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111101010101")); +MQQ35:TBL_MASTER_DEC_PT(35) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111110010000011")); +MQQ36:TBL_MASTER_DEC_PT(36) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("0111000111100")); +MQQ37:TBL_MASTER_DEC_PT(37) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111000011011")); +MQQ38:TBL_MASTER_DEC_PT(38) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(02) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(21) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111111010110")); +MQQ39:TBL_MASTER_DEC_PT(39) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111001001000")); +MQQ40:TBL_MASTER_DEC_PT(40) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111101110100")); +MQQ41:TBL_MASTER_DEC_PT(41) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111001101110")); +MQQ42:TBL_MASTER_DEC_PT(42) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(02) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(21) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111011100110")); +MQQ43:TBL_MASTER_DEC_PT(43) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111011010011")); +MQQ44:TBL_MASTER_DEC_PT(44) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111001010011")); +MQQ45:TBL_MASTER_DEC_PT(45) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111000000100")); +MQQ46:TBL_MASTER_DEC_PT(46) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111000110011")); +MQQ47:TBL_MASTER_DEC_PT(47) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111110010010")); +MQQ48:TBL_MASTER_DEC_PT(48) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(21) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("0111111001100")); +MQQ49:TBL_MASTER_DEC_PT(49) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(02) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(21) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111110010010")); +MQQ50:TBL_MASTER_DEC_PT(50) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(21) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("0111111011010")); +MQQ51:TBL_MASTER_DEC_PT(51) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111111010010")); +MQQ52:TBL_MASTER_DEC_PT(52) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111000000000")); +MQQ53:TBL_MASTER_DEC_PT(53) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111100001000")); +MQQ54:TBL_MASTER_DEC_PT(54) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(02) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(21) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111000011011")); +MQQ55:TBL_MASTER_DEC_PT(55) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111100000011")); +MQQ56:TBL_MASTER_DEC_PT(56) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(02) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(21) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111001000110")); +MQQ57:TBL_MASTER_DEC_PT(57) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("011101011100")); +MQQ58:TBL_MASTER_DEC_PT(58) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("011100011100")); +MQQ59:TBL_MASTER_DEC_PT(59) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111100111111")); +MQQ60:TBL_MASTER_DEC_PT(60) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(02) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(21) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("0111111110110")); +MQQ61:TBL_MASTER_DEC_PT(61) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(02) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(21) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("0111101011011")); +MQQ62:TBL_MASTER_DEC_PT(62) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(02) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("0111100001010")); +MQQ63:TBL_MASTER_DEC_PT(63) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(02) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(21) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) ) , STD_ULOGIC_VECTOR'("0111110001010")); +MQQ64:TBL_MASTER_DEC_PT(64) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111000010010")); +MQQ65:TBL_MASTER_DEC_PT(65) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111100001111")); +MQQ66:TBL_MASTER_DEC_PT(66) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111100011111")); +MQQ67:TBL_MASTER_DEC_PT(67) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111100011111")); +MQQ68:TBL_MASTER_DEC_PT(68) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("0111110100100")); +MQQ69:TBL_MASTER_DEC_PT(69) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(02) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(21) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) ) , STD_ULOGIC_VECTOR'("0111100111011")); +MQQ70:TBL_MASTER_DEC_PT(70) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(02) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(21) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("0111100101010")); +MQQ71:TBL_MASTER_DEC_PT(71) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(02) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(21) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("0111101000110")); +MQQ72:TBL_MASTER_DEC_PT(72) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(02) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(21) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) ) , STD_ULOGIC_VECTOR'("0111100000101")); +MQQ73:TBL_MASTER_DEC_PT(73) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(02) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(21) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) ) , STD_ULOGIC_VECTOR'("0111100001011")); +MQQ74:TBL_MASTER_DEC_PT(74) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(02) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(21) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("011110001111")); +MQQ75:TBL_MASTER_DEC_PT(75) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(02) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(21) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("011110001011")); +MQQ76:TBL_MASTER_DEC_PT(76) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(02) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("011110010110")); +MQQ77:TBL_MASTER_DEC_PT(77) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(02) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(21) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("011110010111")); +MQQ78:TBL_MASTER_DEC_PT(78) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011101111")); +MQQ79:TBL_MASTER_DEC_PT(79) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) + ) , STD_ULOGIC_VECTOR'("010000")); +MQQ80:TBL_MASTER_DEC_PT(80) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(02) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("110100")); +MQQ81:TBL_MASTER_DEC_PT(81) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) + ) , STD_ULOGIC_VECTOR'("01111000")); +MQQ82:TBL_MASTER_DEC_PT(82) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) + ) , STD_ULOGIC_VECTOR'("001000")); +MQQ83:TBL_MASTER_DEC_PT(83) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) + ) , STD_ULOGIC_VECTOR'("001010")); +MQQ84:TBL_MASTER_DEC_PT(84) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(02) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("11100")); +MQQ85:TBL_MASTER_DEC_PT(85) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(27) ) , STD_ULOGIC_VECTOR'("0111100")); +MQQ86:TBL_MASTER_DEC_PT(86) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) ) , STD_ULOGIC_VECTOR'("01010")); +MQQ87:TBL_MASTER_DEC_PT(87) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) ) , STD_ULOGIC_VECTOR'("00001")); +MQQ88:TBL_MASTER_DEC_PT(88) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) + ) , STD_ULOGIC_VECTOR'("001111")); +MQQ89:TBL_MASTER_DEC_PT(89) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) ) , STD_ULOGIC_VECTOR'("01101")); +MQQ90:TBL_MASTER_DEC_PT(90) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(05) ) , STD_ULOGIC_VECTOR'("01011")); +MQQ91:TBL_MASTER_DEC_PT(91) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(05) ) , STD_ULOGIC_VECTOR'("01101")); +MQQ92:TBL_MASTER_DEC_PT(92) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) ) , STD_ULOGIC_VECTOR'("00101")); +MQQ93:TBL_MASTER_DEC_PT(93) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(04) + ) , STD_ULOGIC_VECTOR'("0110")); +MQQ94:TBL_MASTER_DEC_PT(94) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) + ) , STD_ULOGIC_VECTOR'("10")); +MQQ95:TBL_MASTER_DEC_PT(95) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) + ) , STD_ULOGIC_VECTOR'("0110")); +MQQ96:TBL_MASTER_DEC_PT(96) <= + Eq(( RF1_INSTR_Q(01) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) ) , STD_ULOGIC_VECTOR'("011")); +MQQ97:TBL_MASTER_DEC_PT(97) <= + Eq(( RF1_INSTR_Q(01) & RF1_INSTR_Q(02) & + RF1_INSTR_Q(03) ) , STD_ULOGIC_VECTOR'("011")); +-- Table TBL_MASTER_DEC Signal Assignments for Outputs +MQQ98:DEC_BYP_RF1_IS_MCRF <= + (TBL_MASTER_DEC_PT(2)); +MQQ99:DEC_BYP_RF1_IS_MTCRF <= + (TBL_MASTER_DEC_PT(17)); +MQQ100:RF1_ADD_EXT <= + (TBL_MASTER_DEC_PT(40) OR TBL_MASTER_DEC_PT(68) + ); +MQQ101:RF1_ALU_CMP <= + (TBL_MASTER_DEC_PT(52) OR TBL_MASTER_DEC_PT(92) + ); +MQQ102:RF1_CMP <= + (TBL_MASTER_DEC_PT(45) OR TBL_MASTER_DEC_PT(52) + OR TBL_MASTER_DEC_PT(87) OR TBL_MASTER_DEC_PT(92) + ); +MQQ103:RF1_CMP_UEXT <= + (TBL_MASTER_DEC_PT(14) OR TBL_MASTER_DEC_PT(83) + ); +MQQ104:RF1_CR_SO_UPDATE(00) <= + (TBL_MASTER_DEC_PT(5) OR TBL_MASTER_DEC_PT(7) + OR TBL_MASTER_DEC_PT(8) OR TBL_MASTER_DEC_PT(9) + OR TBL_MASTER_DEC_PT(10) OR TBL_MASTER_DEC_PT(11) + OR TBL_MASTER_DEC_PT(17)); +MQQ105:RF1_CR_SO_UPDATE(01) <= + (TBL_MASTER_DEC_PT(52) OR TBL_MASTER_DEC_PT(92) + ); +MQQ106:RF1_CR_WE <= + (TBL_MASTER_DEC_PT(2) OR TBL_MASTER_DEC_PT(5) + OR TBL_MASTER_DEC_PT(7) OR TBL_MASTER_DEC_PT(8) + OR TBL_MASTER_DEC_PT(9) OR TBL_MASTER_DEC_PT(10) + OR TBL_MASTER_DEC_PT(11) OR TBL_MASTER_DEC_PT(52) + OR TBL_MASTER_DEC_PT(92)); +MQQ107:RF1_IMM_SIGNEXT_TBL <= + (TBL_MASTER_DEC_PT(79) OR TBL_MASTER_DEC_PT(80) + OR TBL_MASTER_DEC_PT(82) OR TBL_MASTER_DEC_PT(84) + OR TBL_MASTER_DEC_PT(87) OR TBL_MASTER_DEC_PT(94) + OR TBL_MASTER_DEC_PT(96) OR TBL_MASTER_DEC_PT(97) + ); +MQQ108:RF1_IMM_SIZE_TBL <= + (TBL_MASTER_DEC_PT(31) OR TBL_MASTER_DEC_PT(34) + OR TBL_MASTER_DEC_PT(79) OR TBL_MASTER_DEC_PT(80) + OR TBL_MASTER_DEC_PT(82) OR TBL_MASTER_DEC_PT(83) + OR TBL_MASTER_DEC_PT(84) OR TBL_MASTER_DEC_PT(87) + OR TBL_MASTER_DEC_PT(93) OR TBL_MASTER_DEC_PT(94) + OR TBL_MASTER_DEC_PT(95) OR TBL_MASTER_DEC_PT(96) + OR TBL_MASTER_DEC_PT(97)); +MQQ109:RF1_INSTR_HYPV_TBL <= + (TBL_MASTER_DEC_PT(3) OR TBL_MASTER_DEC_PT(4) + OR TBL_MASTER_DEC_PT(18) OR TBL_MASTER_DEC_PT(22) + OR TBL_MASTER_DEC_PT(29) OR TBL_MASTER_DEC_PT(41) + OR TBL_MASTER_DEC_PT(44) OR TBL_MASTER_DEC_PT(46) + OR TBL_MASTER_DEC_PT(47)); +MQQ110:RF1_INSTR_PRIV_TBL <= + (TBL_MASTER_DEC_PT(13) OR TBL_MASTER_DEC_PT(15) + OR TBL_MASTER_DEC_PT(16) OR TBL_MASTER_DEC_PT(18) + OR TBL_MASTER_DEC_PT(19) OR TBL_MASTER_DEC_PT(20) + OR TBL_MASTER_DEC_PT(22) OR TBL_MASTER_DEC_PT(25) + OR TBL_MASTER_DEC_PT(26) OR TBL_MASTER_DEC_PT(27) + OR TBL_MASTER_DEC_PT(31) OR TBL_MASTER_DEC_PT(35) + OR TBL_MASTER_DEC_PT(41) OR TBL_MASTER_DEC_PT(44) + OR TBL_MASTER_DEC_PT(46) OR TBL_MASTER_DEC_PT(51) + OR TBL_MASTER_DEC_PT(55) OR TBL_MASTER_DEC_PT(59) + OR TBL_MASTER_DEC_PT(64) OR TBL_MASTER_DEC_PT(65) + OR TBL_MASTER_DEC_PT(66) OR TBL_MASTER_DEC_PT(67) + ); +MQQ111:RF1_IS_TRAP <= + (TBL_MASTER_DEC_PT(45) OR TBL_MASTER_DEC_PT(87) + ); +MQQ112:RF1_ONES_IMM <= + (TBL_MASTER_DEC_PT(40)); +MQQ113:RF1_SEL(00) <= + (TBL_MASTER_DEC_PT(22) OR TBL_MASTER_DEC_PT(23) + OR TBL_MASTER_DEC_PT(25) OR TBL_MASTER_DEC_PT(27) + OR TBL_MASTER_DEC_PT(31) OR TBL_MASTER_DEC_PT(34) + OR TBL_MASTER_DEC_PT(35) OR TBL_MASTER_DEC_PT(38) + OR TBL_MASTER_DEC_PT(40) OR TBL_MASTER_DEC_PT(41) + OR TBL_MASTER_DEC_PT(42) OR TBL_MASTER_DEC_PT(43) + OR TBL_MASTER_DEC_PT(45) OR TBL_MASTER_DEC_PT(47) + OR TBL_MASTER_DEC_PT(49) OR TBL_MASTER_DEC_PT(52) + OR TBL_MASTER_DEC_PT(53) OR TBL_MASTER_DEC_PT(54) + OR TBL_MASTER_DEC_PT(56) OR TBL_MASTER_DEC_PT(59) + OR TBL_MASTER_DEC_PT(60) OR TBL_MASTER_DEC_PT(61) + OR TBL_MASTER_DEC_PT(62) OR TBL_MASTER_DEC_PT(63) + OR TBL_MASTER_DEC_PT(64) OR TBL_MASTER_DEC_PT(65) + OR TBL_MASTER_DEC_PT(66) OR TBL_MASTER_DEC_PT(67) + OR TBL_MASTER_DEC_PT(68) OR TBL_MASTER_DEC_PT(69) + OR TBL_MASTER_DEC_PT(70) OR TBL_MASTER_DEC_PT(71) + OR TBL_MASTER_DEC_PT(72) OR TBL_MASTER_DEC_PT(73) + OR TBL_MASTER_DEC_PT(74) OR TBL_MASTER_DEC_PT(75) + OR TBL_MASTER_DEC_PT(76) OR TBL_MASTER_DEC_PT(77) + OR TBL_MASTER_DEC_PT(80) OR TBL_MASTER_DEC_PT(82) + OR TBL_MASTER_DEC_PT(84) OR TBL_MASTER_DEC_PT(87) + OR TBL_MASTER_DEC_PT(92) OR TBL_MASTER_DEC_PT(94) + OR TBL_MASTER_DEC_PT(97)); +MQQ114:RF1_SEL(01) <= + (TBL_MASTER_DEC_PT(21) OR TBL_MASTER_DEC_PT(24) + OR TBL_MASTER_DEC_PT(30) OR TBL_MASTER_DEC_PT(37) + OR TBL_MASTER_DEC_PT(48) OR TBL_MASTER_DEC_PT(50) + OR TBL_MASTER_DEC_PT(81) OR TBL_MASTER_DEC_PT(85) + OR TBL_MASTER_DEC_PT(86) OR TBL_MASTER_DEC_PT(90) + ); +MQQ115:RF1_SEL(02) <= + (TBL_MASTER_DEC_PT(32) OR TBL_MASTER_DEC_PT(36) + OR TBL_MASTER_DEC_PT(57) OR TBL_MASTER_DEC_PT(58) + OR TBL_MASTER_DEC_PT(78) OR TBL_MASTER_DEC_PT(93) + OR TBL_MASTER_DEC_PT(95)); +MQQ116:RF1_SEL(03) <= + (TBL_MASTER_DEC_PT(6)); +MQQ117:RF1_SHIFT_IMM <= + (TBL_MASTER_DEC_PT(88) OR TBL_MASTER_DEC_PT(89) + OR TBL_MASTER_DEC_PT(91)); +MQQ118:RF1_SPR_SEL <= + (TBL_MASTER_DEC_PT(1) OR TBL_MASTER_DEC_PT(12) + OR TBL_MASTER_DEC_PT(13) OR TBL_MASTER_DEC_PT(16) + OR TBL_MASTER_DEC_PT(19) OR TBL_MASTER_DEC_PT(28) + ); +MQQ119:RF1_SUB <= + (TBL_MASTER_DEC_PT(23) OR TBL_MASTER_DEC_PT(45) + OR TBL_MASTER_DEC_PT(52) OR TBL_MASTER_DEC_PT(53) + OR TBL_MASTER_DEC_PT(82) OR TBL_MASTER_DEC_PT(87) + OR TBL_MASTER_DEC_PT(92)); +MQQ120:RF1_ZERO_IMM <= + (TBL_MASTER_DEC_PT(23) OR TBL_MASTER_DEC_PT(33) + OR TBL_MASTER_DEC_PT(34) OR TBL_MASTER_DEC_PT(35) + OR TBL_MASTER_DEC_PT(39) OR TBL_MASTER_DEC_PT(43) + ); + +-- +-- Final Table Listing +-- *INPUTS*==========================================================*OUTPUTS*============================================* +-- | | | +-- | rf1_instr_q | | +-- | | rf1_instr_q | | +-- | | | rf1_instr_q | rf1_derat_is_load | +-- | | | | rf1_instr_q | | rf1_derat_is_store | +-- | | | | | rf1_axu_ld_or_st_q | | | rf1_is_any_load_axu | +-- | | | | | | rf1_axu_ldst_size_q | | | | rf1_is_any_load_dac | +-- | | | | | | | rf1_axu_mftgpr_q | | | | | rf1_is_any_store | +-- | | | | | | | | rf1_axu_mffgpr_q | | | | | | rf1_is_any_store_axu | +-- | | | | | | | | | rf1_axu_movedp_q | | | | | | | rf1_is_any_store_dac | +-- | | | | | | | | | | rf1_axu_store_q | | | | | | | | rf1_is_ld_w_update | +-- | | | | | | | | | | | rf1_xer_si_zero_b | | | | | | | | | rf1_is_st_w_update | +-- | | | | | | | | | | | | rf1_axu_ldst_update_q | | | | | | | | | | xu_lsu_rf1_algebraic | +-- | | | | | | | | | | | | | | | | | | | | | | | | xu_lsu_rf1_ldawx_instr | +-- | | | | | | | | | | | | | | | | | | | | | | | | | xu_lsu_rf1_optype1 | +-- | | | | | | | | | | | | | | | | | | | | | | | | | | xu_lsu_rf1_optype16 | +-- | | | | | | | | | | | | | | | | | | | | | | | | | | | xu_lsu_rf1_optype2 | +-- | | | | | | | | | | | | | | | | | | | | | | | | | | | | xu_lsu_rf1_optype32 | +-- | | | | | | | | | | | | | | | | | | | | | | | | | | | | | xu_lsu_rf1_optype4 | +-- | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | xu_lsu_rf1_optype8 | +-- | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | +-- | 000000 0 2222222223 33 | 000000 | | | | | | | | | | | | | | | | | | | | | | | | | +-- | 012345 9 1234567890 01 | 012345 | | | | | | | | | | | | | | | | | | | | | | | | | +-- *TYPE*============================================================+====================================================+ +-- | PPPPPP P PPPPPPPPPP PP P PPPPPP P P P P P P | P P P P P P P P P P P P P P P P P | +-- *POLARITY*------------------------------------------------------->| + + + + + + + + + + + + + + + + + | +-- *PHASE*---------------------------------------------------------->| T T T T T T T T T T T T T T T T T | +-- *TERMS*===========================================================+====================================================+ +-- 1 | 011111 1 1110100110 -- - ------ - - - - - - | 1 . . 1 . . . . . . . . . . . . . | +-- 2 | 011111 - 0011010100 -- - ------ - - - - - - | . . . . . . . . . . 1 . . . . . . | +-- 3 | 011111 - 1111111111 -- - ------ - - - - - - | . 1 . . 1 . 1 . . . . . . . . . . | +-- 4 | 011111 - 1111011111 -- - ------ - - - - - - | 1 . . 1 . . . . . . . . . . . . . | +-- 5 | 011111 - 0011110111 -- - ------ - - - - - - | . . . . . 1 . . 1 . . 1 . . . . . | +-- 6 | 011111 - 1001010101 -- - ------ - - - - - - | 1 . . 1 . . . . . . . . . . . . . | +-- 7 | 011111 - 0110000110 -- - ------ - - - - - - | 1 . . 1 . . . . . . . . . . . . . | +-- 8 | 011111 - 1110110110 -- - ------ - - - - - - | . 1 . . 1 . . . . . . . . . . 1 . | +-- 9 | 011111 - 101001010- -- - ------ - - - - 1 - | . 1 . . 1 . 1 . . . . . . . . . . | +-- 10 | 011111 - 1111110110 -- - ------ - - - - - - | . 1 . . 1 . 1 . . . . . . . . . . | +-- 11 | 011111 - 0011010110 -- - ------ - - - - - - | . . . . . 1 . . . . . . . . . . 1 | +-- 12 | 011111 - 1111010110 -- - ------ - - - - - - | 1 . . 1 . . . . . . . . . . . . . | +-- 13 | 011111 - 1011010101 -- - ------ - - - - - - | . 1 . . 1 . 1 . . . . . . . . . . | +-- 14 | 011111 - 0000110110 -- - ------ - - - - - - | 1 . . . . . 1 . . . . . . . . . . | +-- 15 | 011111 - 1000010100 -- - ------ - - - - - - | 1 . 1 1 . . . . . . . . . . . . 1 | +-- 16 | 011111 - 0001010110 -- - ------ - - - - - - | 1 . . . . . 1 . . . . . . . . . . | +-- 17 | 011111 - 010001-111 -- - ------ - - - - - - | . . 1 . . . . . . . . . . 1 . . . | +-- 18 | 011111 - 0-11100110 -- - ------ - - - - - - | 1 . . 1 . . . . . . . . . . . . . | +-- 19 | 011111 - 1100010110 -- - ------ - - - - - - | 1 . 1 1 . . . . . . . . . 1 . . . | +-- 20 | 011111 - 0101010101 -- - ------ - - - - - - | 1 . 1 1 . . . . . 1 . . . . . 1 . | +-- 21 | 011111 - 000-111111 -- - ------ - - - - - - | 1 . . . . . 1 . . . . . . . . . . | +-- 22 | 011111 - 001101-111 -- - ------ - - - - - - | . . . . . 1 . . . . . 1 . . . . . | +-- 23 | 011111 - -00001010- -- - ------ - - - - 1 - | 1 . . 1 . . . . . . . . . . . . . | +-- 24 | 011111 - 001-100110 -- - ------ - - - - - - | 1 . . 1 . . . . . . . . . . . . . | +-- 25 | 011111 - 1010010100 -- - ------ - - - - - - | . 1 . . 1 1 1 . . . . . . . . . 1 | +-- 26 | 011111 - 0000010100 -- - ------ - - - - - - | 1 . 1 1 . . . . . . . . . . . 1 . | +-- 27 | 011111 - 1000010110 -- - ------ - - - - - - | 1 . 1 1 . . . . . . . . . . . 1 . | +-- 28 | 011111 - 1110010110 -- - ------ - - - - - - | . 1 . . 1 1 1 . . . . . . 1 . . . | +-- 29 | 011111 - 0101010111 -- - ------ - - - - - - | 1 . 1 1 . . . . . 1 . . . 1 . . . | +-- 30 | 011111 - 01011101-1 -- - ------ - - - - - - | 1 . . 1 . . . 1 . . . . . . . . . | +-- 31 | 011111 - 0010110101 -- - ------ - - - - - - | . 1 . . 1 1 1 . 1 . . . . . . . 1 | +-- 32 | 011111 - 0110110111 -- - ------ - - - - - - | . 1 . . 1 1 1 . 1 . . . . 1 . . . | +-- 33 | 011111 - 00001101-1 -- - ------ - - - - - - | 1 . . 1 . . . 1 . . . . . . . . . | +-- 34 | 011111 - 0010110111 -- - ------ - - - - - - | . 1 . . 1 1 1 . 1 . . . . . . 1 . | +-- 35 | 011111 - 000001-101 -- - ------ - - - - - - | 1 . 1 1 . . . . . . . . . . . . 1 | +-- 36 | 011111 - 00100-0110 -- - ------ - - - - - - | . 1 . . 1 . 1 . . . . . . . . . . | +-- 37 | 011111 - 0-10010110 -- - ------ - - - - - - | . 1 . . 1 . . . . . . . . . . 1 . | +-- 38 | 011111 - 00-1010100 -- - ------ - - - - - - | 1 . 1 1 . . . . . . . . . . . . 1 | +-- 39 | 011111 - 000101-111 -- - ------ - - - - - - | 1 . 1 1 . . . . . . . 1 . . . . . | +-- 40 | 011111 - 0-11010110 -- - ------ - - - - - - | . 1 . . 1 . 1 . . . . . . . . . . | +-- 41 | 011111 - 001001-101 -- - ------ - - - - - - | . 1 . . 1 1 1 . . . . . . . . . 1 | +-- 42 | ------ - ---------- -- 1 ------ 0 0 0 0 - 1 | . . . . . . . 1 . . . . . . . . . | +-- 43 | ------ - ---------- -- 1 ------ 0 0 0 1 - 1 | . . . . . . . . 1 . . . . . . . . | +-- 44 | 011111 - 000001-111 -- - ------ - - - - - - | 1 . 1 1 . . . . . . . . . . . 1 . | +-- 45 | 011111 - 011001-111 -- - ------ - - - - - - | . 1 . . 1 1 1 . . . . . . 1 . . . | +-- 46 | 011111 - 0100-1-111 -- - ------ - - - - - - | 1 . . 1 . . . . . . . . . . . . . | +-- 47 | 011111 - 0-0-110111 -- - ------ - - - - - - | 1 . . 1 . . . 1 . . . . . . . . . | +-- 48 | 011111 - 001001-111 -- - ------ - - - - - - | . 1 . . 1 1 1 . . . . . . . . 1 . | +-- 49 | 011111 - -010010110 -- - ------ - - - - - - | . 1 . . 1 1 1 . . . . . . . . 1 . | +-- 50 | 011111 - 0011-1-111 -- - ------ - - - - - - | . 1 . . 1 . 1 . . . . . . . . . . | +-- 51 | 011111 - 0-0001011- -- - ------ - - - - - - | 1 . . 1 . . . . . . . . . . . . . | +-- 52 | 011111 - 0011-1011- -- - ------ - - - - - - | . 1 . . 1 . 1 . . . . . . . . . . | +-- 53 | 111110 - ---------- 01 - ------ - - - - - - | . . . . . . . . 1 . . . . . . . . | +-- 54 | 111010 - ---------- 01 - ------ - - - - - - | 1 . . 1 . . . 1 . . . . . . . . . | +-- 55 | 100000 - ---------- -- - ------ - - - - - - | 1 . 1 1 . . . . . . . . . . . 1 . | +-- 56 | 111010 - ---------- 00 - ------ - - - - - - | 1 . 1 1 . . . . . . . . . . . . 1 | +-- 57 | 111010 - ---------- 10 - ------ - - - - - - | 1 . 1 1 . . . . . 1 . . . . . 1 . | +-- 58 | 101010 - ---------- -- - ------ - - - - - - | . . . . . . . . . 1 . . . . . . . | +-- 59 | ------ - ---------- -- 1 ------ 0 0 0 0 - - | 1 . 1 1 . . . . . . . . . . . . . | +-- 60 | ------ - ---------- -- 1 ------ 0 0 0 1 - - | . 1 . . 1 1 1 . . . . . . . . . . | +-- 61 | 100010 - ---------- -- - ------ - - - - - - | 1 . 1 1 . . . . . . . 1 . . . . . | +-- 62 | 1001-1 - ---------- -- - ------ - - - - - - | . . . . . . . . 1 . . . . . . . . | +-- 63 | 10-101 - ---------- -- - ------ - - - - - - | . . . . . . . . 1 . . . . . . . . | +-- 64 | 1010-0 - ---------- -- - ------ - - - - - - | 1 . 1 1 . . . . . . . . . 1 . . . | +-- 65 | 10010- - ---------- -- - ------ - - - - - - | . 1 . . 1 1 1 . . . . . . . . 1 . | +-- 66 | 111110 - ---------- 0- - ------ - - - - - - | . 1 . . 1 1 1 . . . . . . . . . 1 | +-- 67 | 101-10 - ---------- -- - ------ - - - - - - | 1 . . 1 . . . . . . . . . . . . . | +-- 68 | 10-0-1 - ---------- -- - ------ - - - - - - | 1 . . 1 . . . 1 . . . . . . . . . | +-- 69 | ------ - ---------- -- 1 -1---- - - - - - - | . . . . . . . . . . . . 1 . . . . | +-- 70 | ------ - ---------- -- 1 1----- - - - - - - | . . . . . . . . . . . . . . 1 . . | +-- 71 | ------ - ---------- -- 1 -----1 - - - - - - | . . . . . . . . . . . 1 . . . . . | +-- 72 | 10011- - ---------- -- - ------ - - - - - - | . 1 . . 1 1 1 . . . . 1 . . . . . | +-- 73 | ------ - ---------- -- 1 ----1- - - - - - - | . . . . . . . . . . . . . 1 . . . | +-- 74 | 10110- - ---------- -- - ------ - - - - - - | . 1 . . 1 1 1 . . . . . . 1 . . . | +-- 75 | ------ - ---------- -- 1 --1--- - - - - - - | . . . . . . . . . . . . . . . . 1 | +-- 76 | ------ - ---------- -- 1 ---1-- - - - - - - | . . . . . . . . . . . . . . . 1 . | +-- 77 | 10-1-1 - ---------- -- - ------ - - - - - - | . 1 . . 1 . 1 . . . . . . . . . . | +-- *======================================================================================================================* +-- +-- Table TBL_LD_ST_DEC Signal Assignments for Product Terms +MQQ121:TBL_LD_ST_DEC_PT(1) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(09) & RF1_INSTR_Q(21) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("01111111110100110")); +MQQ122:TBL_LD_ST_DEC_PT(2) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111110011010100")); +MQQ123:TBL_LD_ST_DEC_PT(3) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111111111111111")); +MQQ124:TBL_LD_ST_DEC_PT(4) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111111111011111")); +MQQ125:TBL_LD_ST_DEC_PT(5) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111110011110111")); +MQQ126:TBL_LD_ST_DEC_PT(6) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111111001010101")); +MQQ127:TBL_LD_ST_DEC_PT(7) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111110110000110")); +MQQ128:TBL_LD_ST_DEC_PT(8) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111111110110110")); +MQQ129:TBL_LD_ST_DEC_PT(9) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_XER_SI_ZERO_B + ) , STD_ULOGIC_VECTOR'("0111111010010101")); +MQQ130:TBL_LD_ST_DEC_PT(10) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111111111110110")); +MQQ131:TBL_LD_ST_DEC_PT(11) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111110011010110")); +MQQ132:TBL_LD_ST_DEC_PT(12) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111111111010110")); +MQQ133:TBL_LD_ST_DEC_PT(13) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111111011010101")); +MQQ134:TBL_LD_ST_DEC_PT(14) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111110000110110")); +MQQ135:TBL_LD_ST_DEC_PT(15) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111111000010100")); +MQQ136:TBL_LD_ST_DEC_PT(16) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111110001010110")); +MQQ137:TBL_LD_ST_DEC_PT(17) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111010001111")); +MQQ138:TBL_LD_ST_DEC_PT(18) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111011100110")); +MQQ139:TBL_LD_ST_DEC_PT(19) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111111100010110")); +MQQ140:TBL_LD_ST_DEC_PT(20) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111110101010101")); +MQQ141:TBL_LD_ST_DEC_PT(21) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111000111111")); +MQQ142:TBL_LD_ST_DEC_PT(22) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111001101111")); +MQQ143:TBL_LD_ST_DEC_PT(23) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_XER_SI_ZERO_B ) , STD_ULOGIC_VECTOR'("011111000010101")); +MQQ144:TBL_LD_ST_DEC_PT(24) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111001100110")); +MQQ145:TBL_LD_ST_DEC_PT(25) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111111010010100")); +MQQ146:TBL_LD_ST_DEC_PT(26) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111110000010100")); +MQQ147:TBL_LD_ST_DEC_PT(27) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111111000010110")); +MQQ148:TBL_LD_ST_DEC_PT(28) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111111110010110")); +MQQ149:TBL_LD_ST_DEC_PT(29) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111110101010111")); +MQQ150:TBL_LD_ST_DEC_PT(30) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111010111011")); +MQQ151:TBL_LD_ST_DEC_PT(31) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111110010110101")); +MQQ152:TBL_LD_ST_DEC_PT(32) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111110110110111")); +MQQ153:TBL_LD_ST_DEC_PT(33) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111000011011")); +MQQ154:TBL_LD_ST_DEC_PT(34) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("0111110010110111")); +MQQ155:TBL_LD_ST_DEC_PT(35) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111000001101")); +MQQ156:TBL_LD_ST_DEC_PT(36) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111001000110")); +MQQ157:TBL_LD_ST_DEC_PT(37) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111010010110")); +MQQ158:TBL_LD_ST_DEC_PT(38) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111001010100")); +MQQ159:TBL_LD_ST_DEC_PT(39) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111000101111")); +MQQ160:TBL_LD_ST_DEC_PT(40) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111011010110")); +MQQ161:TBL_LD_ST_DEC_PT(41) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111001001101")); +MQQ162:TBL_LD_ST_DEC_PT(42) <= + Eq(( RF1_AXU_LD_OR_ST_Q & RF1_AXU_MFTGPR_Q & + RF1_AXU_MFFGPR_Q & RF1_AXU_MOVEDP_Q & + RF1_AXU_STORE_Q & RF1_AXU_LDST_UPDATE_Q + ) , STD_ULOGIC_VECTOR'("100001")); +MQQ163:TBL_LD_ST_DEC_PT(43) <= + Eq(( RF1_AXU_LD_OR_ST_Q & RF1_AXU_MFTGPR_Q & + RF1_AXU_MFFGPR_Q & RF1_AXU_MOVEDP_Q & + RF1_AXU_STORE_Q & RF1_AXU_LDST_UPDATE_Q + ) , STD_ULOGIC_VECTOR'("100011")); +MQQ164:TBL_LD_ST_DEC_PT(44) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111000001111")); +MQQ165:TBL_LD_ST_DEC_PT(45) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111011001111")); +MQQ166:TBL_LD_ST_DEC_PT(46) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111101001111")); +MQQ167:TBL_LD_ST_DEC_PT(47) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111100110111")); +MQQ168:TBL_LD_ST_DEC_PT(48) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111001001111")); +MQQ169:TBL_LD_ST_DEC_PT(49) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111010010110")); +MQQ170:TBL_LD_ST_DEC_PT(50) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111100111111")); +MQQ171:TBL_LD_ST_DEC_PT(51) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) + ) , STD_ULOGIC_VECTOR'("01111100001011")); +MQQ172:TBL_LD_ST_DEC_PT(52) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) + ) , STD_ULOGIC_VECTOR'("01111100111011")); +MQQ173:TBL_LD_ST_DEC_PT(53) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(30) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("11111001")); +MQQ174:TBL_LD_ST_DEC_PT(54) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(30) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("11101001")); +MQQ175:TBL_LD_ST_DEC_PT(55) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) + ) , STD_ULOGIC_VECTOR'("100000")); +MQQ176:TBL_LD_ST_DEC_PT(56) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(30) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("11101000")); +MQQ177:TBL_LD_ST_DEC_PT(57) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(30) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("11101010")); +MQQ178:TBL_LD_ST_DEC_PT(58) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) + ) , STD_ULOGIC_VECTOR'("101010")); +MQQ179:TBL_LD_ST_DEC_PT(59) <= + Eq(( RF1_AXU_LD_OR_ST_Q & RF1_AXU_MFTGPR_Q & + RF1_AXU_MFFGPR_Q & RF1_AXU_MOVEDP_Q & + RF1_AXU_STORE_Q ) , STD_ULOGIC_VECTOR'("10000")); +MQQ180:TBL_LD_ST_DEC_PT(60) <= + Eq(( RF1_AXU_LD_OR_ST_Q & RF1_AXU_MFTGPR_Q & + RF1_AXU_MFFGPR_Q & RF1_AXU_MOVEDP_Q & + RF1_AXU_STORE_Q ) , STD_ULOGIC_VECTOR'("10001")); +MQQ181:TBL_LD_ST_DEC_PT(61) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) + ) , STD_ULOGIC_VECTOR'("100010")); +MQQ182:TBL_LD_ST_DEC_PT(62) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(05) ) , STD_ULOGIC_VECTOR'("10011")); +MQQ183:TBL_LD_ST_DEC_PT(63) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) ) , STD_ULOGIC_VECTOR'("10101")); +MQQ184:TBL_LD_ST_DEC_PT(64) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(05) ) , STD_ULOGIC_VECTOR'("10100")); +MQQ185:TBL_LD_ST_DEC_PT(65) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) ) , STD_ULOGIC_VECTOR'("10010")); +MQQ186:TBL_LD_ST_DEC_PT(66) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("1111100")); +MQQ187:TBL_LD_ST_DEC_PT(67) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) ) , STD_ULOGIC_VECTOR'("10110")); +MQQ188:TBL_LD_ST_DEC_PT(68) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(05) + ) , STD_ULOGIC_VECTOR'("1001")); +MQQ189:TBL_LD_ST_DEC_PT(69) <= + Eq(( RF1_AXU_LD_OR_ST_Q & RF1_AXU_LDST_SIZE_Q(01) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ190:TBL_LD_ST_DEC_PT(70) <= + Eq(( RF1_AXU_LD_OR_ST_Q & RF1_AXU_LDST_SIZE_Q(00) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ191:TBL_LD_ST_DEC_PT(71) <= + Eq(( RF1_AXU_LD_OR_ST_Q & RF1_AXU_LDST_SIZE_Q(05) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ192:TBL_LD_ST_DEC_PT(72) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) ) , STD_ULOGIC_VECTOR'("10011")); +MQQ193:TBL_LD_ST_DEC_PT(73) <= + Eq(( RF1_AXU_LD_OR_ST_Q & RF1_AXU_LDST_SIZE_Q(04) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ194:TBL_LD_ST_DEC_PT(74) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) ) , STD_ULOGIC_VECTOR'("10110")); +MQQ195:TBL_LD_ST_DEC_PT(75) <= + Eq(( RF1_AXU_LD_OR_ST_Q & RF1_AXU_LDST_SIZE_Q(02) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ196:TBL_LD_ST_DEC_PT(76) <= + Eq(( RF1_AXU_LD_OR_ST_Q & RF1_AXU_LDST_SIZE_Q(03) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ197:TBL_LD_ST_DEC_PT(77) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(05) + ) , STD_ULOGIC_VECTOR'("1011")); +-- Table TBL_LD_ST_DEC Signal Assignments for Outputs +MQQ198:RF1_DERAT_IS_LOAD <= + (TBL_LD_ST_DEC_PT(1) OR TBL_LD_ST_DEC_PT(4) + OR TBL_LD_ST_DEC_PT(6) OR TBL_LD_ST_DEC_PT(7) + OR TBL_LD_ST_DEC_PT(12) OR TBL_LD_ST_DEC_PT(14) + OR TBL_LD_ST_DEC_PT(15) OR TBL_LD_ST_DEC_PT(16) + OR TBL_LD_ST_DEC_PT(18) OR TBL_LD_ST_DEC_PT(19) + OR TBL_LD_ST_DEC_PT(20) OR TBL_LD_ST_DEC_PT(21) + OR TBL_LD_ST_DEC_PT(23) OR TBL_LD_ST_DEC_PT(24) + OR TBL_LD_ST_DEC_PT(26) OR TBL_LD_ST_DEC_PT(27) + OR TBL_LD_ST_DEC_PT(29) OR TBL_LD_ST_DEC_PT(30) + OR TBL_LD_ST_DEC_PT(33) OR TBL_LD_ST_DEC_PT(35) + OR TBL_LD_ST_DEC_PT(38) OR TBL_LD_ST_DEC_PT(39) + OR TBL_LD_ST_DEC_PT(44) OR TBL_LD_ST_DEC_PT(46) + OR TBL_LD_ST_DEC_PT(47) OR TBL_LD_ST_DEC_PT(51) + OR TBL_LD_ST_DEC_PT(54) OR TBL_LD_ST_DEC_PT(55) + OR TBL_LD_ST_DEC_PT(56) OR TBL_LD_ST_DEC_PT(57) + OR TBL_LD_ST_DEC_PT(59) OR TBL_LD_ST_DEC_PT(61) + OR TBL_LD_ST_DEC_PT(64) OR TBL_LD_ST_DEC_PT(67) + OR TBL_LD_ST_DEC_PT(68)); +MQQ199:RF1_DERAT_IS_STORE <= + (TBL_LD_ST_DEC_PT(3) OR TBL_LD_ST_DEC_PT(8) + OR TBL_LD_ST_DEC_PT(9) OR TBL_LD_ST_DEC_PT(10) + OR TBL_LD_ST_DEC_PT(13) OR TBL_LD_ST_DEC_PT(25) + OR TBL_LD_ST_DEC_PT(28) OR TBL_LD_ST_DEC_PT(31) + OR TBL_LD_ST_DEC_PT(32) OR TBL_LD_ST_DEC_PT(34) + OR TBL_LD_ST_DEC_PT(36) OR TBL_LD_ST_DEC_PT(37) + OR TBL_LD_ST_DEC_PT(40) OR TBL_LD_ST_DEC_PT(41) + OR TBL_LD_ST_DEC_PT(45) OR TBL_LD_ST_DEC_PT(48) + OR TBL_LD_ST_DEC_PT(49) OR TBL_LD_ST_DEC_PT(50) + OR TBL_LD_ST_DEC_PT(52) OR TBL_LD_ST_DEC_PT(60) + OR TBL_LD_ST_DEC_PT(65) OR TBL_LD_ST_DEC_PT(66) + OR TBL_LD_ST_DEC_PT(72) OR TBL_LD_ST_DEC_PT(74) + OR TBL_LD_ST_DEC_PT(77)); +MQQ200:RF1_IS_ANY_LOAD_AXU <= + (TBL_LD_ST_DEC_PT(15) OR TBL_LD_ST_DEC_PT(17) + OR TBL_LD_ST_DEC_PT(19) OR TBL_LD_ST_DEC_PT(20) + OR TBL_LD_ST_DEC_PT(26) OR TBL_LD_ST_DEC_PT(27) + OR TBL_LD_ST_DEC_PT(29) OR TBL_LD_ST_DEC_PT(35) + OR TBL_LD_ST_DEC_PT(38) OR TBL_LD_ST_DEC_PT(39) + OR TBL_LD_ST_DEC_PT(44) OR TBL_LD_ST_DEC_PT(55) + OR TBL_LD_ST_DEC_PT(56) OR TBL_LD_ST_DEC_PT(57) + OR TBL_LD_ST_DEC_PT(59) OR TBL_LD_ST_DEC_PT(61) + OR TBL_LD_ST_DEC_PT(64)); +MQQ201:RF1_IS_ANY_LOAD_DAC <= + (TBL_LD_ST_DEC_PT(1) OR TBL_LD_ST_DEC_PT(4) + OR TBL_LD_ST_DEC_PT(6) OR TBL_LD_ST_DEC_PT(7) + OR TBL_LD_ST_DEC_PT(12) OR TBL_LD_ST_DEC_PT(15) + OR TBL_LD_ST_DEC_PT(18) OR TBL_LD_ST_DEC_PT(19) + OR TBL_LD_ST_DEC_PT(20) OR TBL_LD_ST_DEC_PT(23) + OR TBL_LD_ST_DEC_PT(24) OR TBL_LD_ST_DEC_PT(26) + OR TBL_LD_ST_DEC_PT(27) OR TBL_LD_ST_DEC_PT(29) + OR TBL_LD_ST_DEC_PT(30) OR TBL_LD_ST_DEC_PT(33) + OR TBL_LD_ST_DEC_PT(35) OR TBL_LD_ST_DEC_PT(38) + OR TBL_LD_ST_DEC_PT(39) OR TBL_LD_ST_DEC_PT(44) + OR TBL_LD_ST_DEC_PT(46) OR TBL_LD_ST_DEC_PT(47) + OR TBL_LD_ST_DEC_PT(51) OR TBL_LD_ST_DEC_PT(54) + OR TBL_LD_ST_DEC_PT(55) OR TBL_LD_ST_DEC_PT(56) + OR TBL_LD_ST_DEC_PT(57) OR TBL_LD_ST_DEC_PT(59) + OR TBL_LD_ST_DEC_PT(61) OR TBL_LD_ST_DEC_PT(64) + OR TBL_LD_ST_DEC_PT(67) OR TBL_LD_ST_DEC_PT(68) + ); +MQQ202:RF1_IS_ANY_STORE <= + (TBL_LD_ST_DEC_PT(3) OR TBL_LD_ST_DEC_PT(8) + OR TBL_LD_ST_DEC_PT(9) OR TBL_LD_ST_DEC_PT(10) + OR TBL_LD_ST_DEC_PT(13) OR TBL_LD_ST_DEC_PT(25) + OR TBL_LD_ST_DEC_PT(28) OR TBL_LD_ST_DEC_PT(31) + OR TBL_LD_ST_DEC_PT(32) OR TBL_LD_ST_DEC_PT(34) + OR TBL_LD_ST_DEC_PT(36) OR TBL_LD_ST_DEC_PT(37) + OR TBL_LD_ST_DEC_PT(40) OR TBL_LD_ST_DEC_PT(41) + OR TBL_LD_ST_DEC_PT(45) OR TBL_LD_ST_DEC_PT(48) + OR TBL_LD_ST_DEC_PT(49) OR TBL_LD_ST_DEC_PT(50) + OR TBL_LD_ST_DEC_PT(52) OR TBL_LD_ST_DEC_PT(60) + OR TBL_LD_ST_DEC_PT(65) OR TBL_LD_ST_DEC_PT(66) + OR TBL_LD_ST_DEC_PT(72) OR TBL_LD_ST_DEC_PT(74) + OR TBL_LD_ST_DEC_PT(77)); +MQQ203:RF1_IS_ANY_STORE_AXU <= + (TBL_LD_ST_DEC_PT(5) OR TBL_LD_ST_DEC_PT(11) + OR TBL_LD_ST_DEC_PT(22) OR TBL_LD_ST_DEC_PT(25) + OR TBL_LD_ST_DEC_PT(28) OR TBL_LD_ST_DEC_PT(31) + OR TBL_LD_ST_DEC_PT(32) OR TBL_LD_ST_DEC_PT(34) + OR TBL_LD_ST_DEC_PT(41) OR TBL_LD_ST_DEC_PT(45) + OR TBL_LD_ST_DEC_PT(48) OR TBL_LD_ST_DEC_PT(49) + OR TBL_LD_ST_DEC_PT(60) OR TBL_LD_ST_DEC_PT(65) + OR TBL_LD_ST_DEC_PT(66) OR TBL_LD_ST_DEC_PT(72) + OR TBL_LD_ST_DEC_PT(74)); +MQQ204:RF1_IS_ANY_STORE_DAC <= + (TBL_LD_ST_DEC_PT(3) OR TBL_LD_ST_DEC_PT(9) + OR TBL_LD_ST_DEC_PT(10) OR TBL_LD_ST_DEC_PT(13) + OR TBL_LD_ST_DEC_PT(14) OR TBL_LD_ST_DEC_PT(16) + OR TBL_LD_ST_DEC_PT(21) OR TBL_LD_ST_DEC_PT(25) + OR TBL_LD_ST_DEC_PT(28) OR TBL_LD_ST_DEC_PT(31) + OR TBL_LD_ST_DEC_PT(32) OR TBL_LD_ST_DEC_PT(34) + OR TBL_LD_ST_DEC_PT(36) OR TBL_LD_ST_DEC_PT(40) + OR TBL_LD_ST_DEC_PT(41) OR TBL_LD_ST_DEC_PT(45) + OR TBL_LD_ST_DEC_PT(48) OR TBL_LD_ST_DEC_PT(49) + OR TBL_LD_ST_DEC_PT(50) OR TBL_LD_ST_DEC_PT(52) + OR TBL_LD_ST_DEC_PT(60) OR TBL_LD_ST_DEC_PT(65) + OR TBL_LD_ST_DEC_PT(66) OR TBL_LD_ST_DEC_PT(72) + OR TBL_LD_ST_DEC_PT(74) OR TBL_LD_ST_DEC_PT(77) + ); +MQQ205:RF1_IS_LD_W_UPDATE <= + (TBL_LD_ST_DEC_PT(30) OR TBL_LD_ST_DEC_PT(33) + OR TBL_LD_ST_DEC_PT(42) OR TBL_LD_ST_DEC_PT(47) + OR TBL_LD_ST_DEC_PT(54) OR TBL_LD_ST_DEC_PT(68) + ); +MQQ206:RF1_IS_ST_W_UPDATE <= + (TBL_LD_ST_DEC_PT(5) OR TBL_LD_ST_DEC_PT(31) + OR TBL_LD_ST_DEC_PT(32) OR TBL_LD_ST_DEC_PT(34) + OR TBL_LD_ST_DEC_PT(43) OR TBL_LD_ST_DEC_PT(53) + OR TBL_LD_ST_DEC_PT(62) OR TBL_LD_ST_DEC_PT(63) + ); +MQQ207:XU_LSU_RF1_ALGEBRAIC <= + (TBL_LD_ST_DEC_PT(20) OR TBL_LD_ST_DEC_PT(29) + OR TBL_LD_ST_DEC_PT(57) OR TBL_LD_ST_DEC_PT(58) + ); +MQQ208:XU_LSU_RF1_LDAWX_INSTR <= + (TBL_LD_ST_DEC_PT(2)); +MQQ209:XU_LSU_RF1_OPTYPE1 <= + (TBL_LD_ST_DEC_PT(5) OR TBL_LD_ST_DEC_PT(22) + OR TBL_LD_ST_DEC_PT(39) OR TBL_LD_ST_DEC_PT(61) + OR TBL_LD_ST_DEC_PT(71) OR TBL_LD_ST_DEC_PT(72) + ); +MQQ210:XU_LSU_RF1_OPTYPE16 <= + (TBL_LD_ST_DEC_PT(69)); +MQQ211:XU_LSU_RF1_OPTYPE2 <= + (TBL_LD_ST_DEC_PT(17) OR TBL_LD_ST_DEC_PT(19) + OR TBL_LD_ST_DEC_PT(28) OR TBL_LD_ST_DEC_PT(29) + OR TBL_LD_ST_DEC_PT(32) OR TBL_LD_ST_DEC_PT(45) + OR TBL_LD_ST_DEC_PT(64) OR TBL_LD_ST_DEC_PT(73) + OR TBL_LD_ST_DEC_PT(74)); +MQQ212:XU_LSU_RF1_OPTYPE32 <= + (TBL_LD_ST_DEC_PT(70)); +MQQ213:XU_LSU_RF1_OPTYPE4 <= + (TBL_LD_ST_DEC_PT(8) OR TBL_LD_ST_DEC_PT(20) + OR TBL_LD_ST_DEC_PT(26) OR TBL_LD_ST_DEC_PT(27) + OR TBL_LD_ST_DEC_PT(34) OR TBL_LD_ST_DEC_PT(37) + OR TBL_LD_ST_DEC_PT(44) OR TBL_LD_ST_DEC_PT(48) + OR TBL_LD_ST_DEC_PT(49) OR TBL_LD_ST_DEC_PT(55) + OR TBL_LD_ST_DEC_PT(57) OR TBL_LD_ST_DEC_PT(65) + OR TBL_LD_ST_DEC_PT(76)); +MQQ214:XU_LSU_RF1_OPTYPE8 <= + (TBL_LD_ST_DEC_PT(11) OR TBL_LD_ST_DEC_PT(15) + OR TBL_LD_ST_DEC_PT(25) OR TBL_LD_ST_DEC_PT(31) + OR TBL_LD_ST_DEC_PT(35) OR TBL_LD_ST_DEC_PT(38) + OR TBL_LD_ST_DEC_PT(41) OR TBL_LD_ST_DEC_PT(56) + OR TBL_LD_ST_DEC_PT(66) OR TBL_LD_ST_DEC_PT(75) + ); + +-- +-- Final Table Listing +-- *INPUTS*====================================*OUTPUTS*==========================* +-- | | | +-- | rf1_instr_q | | +-- | | rf1_instr_q | | +-- | | | rf1_instr_q | rf1_use_crfld0 | +-- | | | | rf1_axu_mftgpr | | rf1_use_crfld0_nmult | +-- | | | | | rf1_axu_mffgpr | | | xu_lsu_rf1_icswx_instr | +-- | | | | | | rf1_axu_movedp | | | | xu_lsu_rf1_icswx_dot_instr | +-- | | | | | | | rf1_val_stg | | | | | xu_lsu_rf1_icswx_epid | +-- | | | | | | | | | | | | | | ex1_is_icswx_d | +-- | | | | | | | | | | | | | | | | +-- | 000000 2222222223 3 | | | | | | | | | | | | +-- | 012345 1234567890 1 | | | | | | | | | | | | +-- *TYPE*======================================+==================================+ +-- | PPPPPP PPPPPPPPPP P P P P P | P P P P P P | +-- *POLARITY*--------------------------------->| + + + + + + | +-- *PHASE*------------------------------------>| T T T T T T | +-- *TERMS*=====================================+==================================+ +-- 1 | 011111 1110110110 0 - - - - | . . 1 . 1 1 | +-- 2 | 011111 0110010110 0 - - - - | . . 1 . . 1 | +-- 3 | 011111 1110110110 1 - - - - | . . . 1 1 1 | +-- 4 | 011111 0110010110 1 - - - - | . . . 1 . 1 | +-- 5 | 0111-- 000--00011 1 - - - - | 1 1 . . . . | +-- 6 | 01-1-1 000-111100 1 - - - - | 1 1 . . . . | +-- 7 | 01-1-1 011-011100 1 - - - - | 1 1 . . . . | +-- 8 | 01-1-1 -000011011 1 - - - - | 1 1 . . . . | +-- 9 | 01-1-1 110011101- 1 - - - - | 1 1 . . . . | +-- 10 | 01-1-1 -0111010-- 1 - - - - | 1 . . . . . | +-- 11 | 01-1-1 -00-0010-1 1 - - - - | 1 . . . . . | +-- 12 | 01-1-1 111-011010 1 - - - - | 1 1 . . . . | +-- 13 | 0111-- -00-101000 1 - - - - | 1 1 . . . . | +-- 14 | 01-1-1 -011-010-0 1 - - - - | . 1 . . . . | +-- 15 | 0111-- -0000-1000 1 - - - - | 1 1 . . . . | +-- 16 | 01-1-1 0-00-11100 1 - - - - | 1 1 . . . . | +-- 17 | 01-1-1 01-0-11100 1 - - - - | 1 1 . . . . | +-- 18 | 01-1-1 --00001010 1 - - - - | 1 1 . . . . | +-- 19 | 01-1-1 11-0-11010 1 - - - - | 1 1 . . . . | +-- 20 | 01-1-1 1100-110-0 1 - - - - | 1 1 . . . . | +-- 21 | 01-1-1 -01-0010-0 1 - - - - | 1 1 . . . . | +-- 22 | 0111-0 -------00- 1 - - - - | 1 1 . . . . | +-- 23 | ------ ---------- 1 - 1 1 1 | 1 1 . . . . | +-- 24 | ------ ---------- 1 1 - 1 1 | 1 1 . . . . | +-- 25 | 0111-0 ------0--- 1 - - - - | 1 1 . . . . | +-- 26 | 0-1101 ---------- - - - - - | 1 1 . . . . | +-- 27 | 01110- ---------- - - - - - | 1 1 . . . . | +-- 28 | 0101-1 ---------- 1 - - - - | 1 1 . . . . | +-- 29 | 01-10- ---------- 1 - - - - | 1 1 . . . . | +-- *==============================================================================* +-- +-- Table TBL_RECFORM_DEC Signal Assignments for Product Terms +MQQ215:TBL_RECFORM_DEC_PT(1) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_INSTR_Q(31) ) , STD_ULOGIC_VECTOR'("01111111101101100")); +MQQ216:TBL_RECFORM_DEC_PT(2) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_INSTR_Q(31) ) , STD_ULOGIC_VECTOR'("01111101100101100")); +MQQ217:TBL_RECFORM_DEC_PT(3) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_INSTR_Q(31) ) , STD_ULOGIC_VECTOR'("01111111101101101")); +MQQ218:TBL_RECFORM_DEC_PT(4) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_INSTR_Q(31) ) , STD_ULOGIC_VECTOR'("01111101100101101")); +MQQ219:TBL_RECFORM_DEC_PT(5) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_INSTR_Q(31) ) , STD_ULOGIC_VECTOR'("0111000000111")); +MQQ220:TBL_RECFORM_DEC_PT(6) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("01110001111001")); +MQQ221:TBL_RECFORM_DEC_PT(7) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("01110110111001")); +MQQ222:TBL_RECFORM_DEC_PT(8) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("01110000110111")); +MQQ223:TBL_RECFORM_DEC_PT(9) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("01111100111011")); +MQQ224:TBL_RECFORM_DEC_PT(10) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("011101110101")); +MQQ225:TBL_RECFORM_DEC_PT(11) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(30) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("011100001011")); +MQQ226:TBL_RECFORM_DEC_PT(12) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("01111110110101")); +MQQ227:TBL_RECFORM_DEC_PT(13) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_INSTR_Q(31) ) , STD_ULOGIC_VECTOR'("0111001010001")); +MQQ228:TBL_RECFORM_DEC_PT(14) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(30) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("011101101001")); +MQQ229:TBL_RECFORM_DEC_PT(15) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_INSTR_Q(31) ) , STD_ULOGIC_VECTOR'("0111000010001")); +MQQ230:TBL_RECFORM_DEC_PT(16) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_INSTR_Q(31) ) , STD_ULOGIC_VECTOR'("0111000111001")); +MQQ231:TBL_RECFORM_DEC_PT(17) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_INSTR_Q(31) ) , STD_ULOGIC_VECTOR'("0111010111001")); +MQQ232:TBL_RECFORM_DEC_PT(18) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_INSTR_Q(31) ) , STD_ULOGIC_VECTOR'("0111000010101")); +MQQ233:TBL_RECFORM_DEC_PT(19) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_INSTR_Q(31) ) , STD_ULOGIC_VECTOR'("0111110110101")); +MQQ234:TBL_RECFORM_DEC_PT(20) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(30) & + RF1_INSTR_Q(31) ) , STD_ULOGIC_VECTOR'("0111110011001")); +MQQ235:TBL_RECFORM_DEC_PT(21) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(30) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("011101001001")); +MQQ236:TBL_RECFORM_DEC_PT(22) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("01110001")); +MQQ237:TBL_RECFORM_DEC_PT(23) <= + Eq(( RF1_INSTR_Q(31) & RF1_AXU_MFFGPR & + RF1_AXU_MOVEDP & RF1_VAL_STG + ) , STD_ULOGIC_VECTOR'("1111")); +MQQ238:TBL_RECFORM_DEC_PT(24) <= + Eq(( RF1_INSTR_Q(31) & RF1_AXU_MFTGPR & + RF1_AXU_MOVEDP & RF1_VAL_STG + ) , STD_ULOGIC_VECTOR'("1111")); +MQQ239:TBL_RECFORM_DEC_PT(25) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(31) ) , STD_ULOGIC_VECTOR'("0111001")); +MQQ240:TBL_RECFORM_DEC_PT(26) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(02) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) ) , STD_ULOGIC_VECTOR'("01101")); +MQQ241:TBL_RECFORM_DEC_PT(27) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) ) , STD_ULOGIC_VECTOR'("01110")); +MQQ242:TBL_RECFORM_DEC_PT(28) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("010111")); +MQQ243:TBL_RECFORM_DEC_PT(29) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(31) ) , STD_ULOGIC_VECTOR'("01101")); +-- Table TBL_RECFORM_DEC Signal Assignments for Outputs +MQQ244:RF1_USE_CRFLD0 <= + (TBL_RECFORM_DEC_PT(5) OR TBL_RECFORM_DEC_PT(6) + OR TBL_RECFORM_DEC_PT(7) OR TBL_RECFORM_DEC_PT(8) + OR TBL_RECFORM_DEC_PT(9) OR TBL_RECFORM_DEC_PT(10) + OR TBL_RECFORM_DEC_PT(11) OR TBL_RECFORM_DEC_PT(12) + OR TBL_RECFORM_DEC_PT(13) OR TBL_RECFORM_DEC_PT(15) + OR TBL_RECFORM_DEC_PT(16) OR TBL_RECFORM_DEC_PT(17) + OR TBL_RECFORM_DEC_PT(18) OR TBL_RECFORM_DEC_PT(19) + OR TBL_RECFORM_DEC_PT(20) OR TBL_RECFORM_DEC_PT(21) + OR TBL_RECFORM_DEC_PT(22) OR TBL_RECFORM_DEC_PT(23) + OR TBL_RECFORM_DEC_PT(24) OR TBL_RECFORM_DEC_PT(25) + OR TBL_RECFORM_DEC_PT(26) OR TBL_RECFORM_DEC_PT(27) + OR TBL_RECFORM_DEC_PT(28) OR TBL_RECFORM_DEC_PT(29) + ); +MQQ245:RF1_USE_CRFLD0_NMULT <= + (TBL_RECFORM_DEC_PT(5) OR TBL_RECFORM_DEC_PT(6) + OR TBL_RECFORM_DEC_PT(7) OR TBL_RECFORM_DEC_PT(8) + OR TBL_RECFORM_DEC_PT(9) OR TBL_RECFORM_DEC_PT(12) + OR TBL_RECFORM_DEC_PT(13) OR TBL_RECFORM_DEC_PT(14) + OR TBL_RECFORM_DEC_PT(15) OR TBL_RECFORM_DEC_PT(16) + OR TBL_RECFORM_DEC_PT(17) OR TBL_RECFORM_DEC_PT(18) + OR TBL_RECFORM_DEC_PT(19) OR TBL_RECFORM_DEC_PT(20) + OR TBL_RECFORM_DEC_PT(21) OR TBL_RECFORM_DEC_PT(22) + OR TBL_RECFORM_DEC_PT(23) OR TBL_RECFORM_DEC_PT(24) + OR TBL_RECFORM_DEC_PT(25) OR TBL_RECFORM_DEC_PT(26) + OR TBL_RECFORM_DEC_PT(27) OR TBL_RECFORM_DEC_PT(28) + OR TBL_RECFORM_DEC_PT(29)); +MQQ246:XU_LSU_RF1_ICSWX_INSTR <= + (TBL_RECFORM_DEC_PT(1) OR TBL_RECFORM_DEC_PT(2) + ); +MQQ247:XU_LSU_RF1_ICSWX_DOT_INSTR <= + (TBL_RECFORM_DEC_PT(3) OR TBL_RECFORM_DEC_PT(4) + ); +MQQ248:XU_LSU_RF1_ICSWX_EPID <= + (TBL_RECFORM_DEC_PT(1) OR TBL_RECFORM_DEC_PT(3) + ); +MQQ249:EX1_IS_ICSWX_D <= + (TBL_RECFORM_DEC_PT(1) OR TBL_RECFORM_DEC_PT(2) + OR TBL_RECFORM_DEC_PT(3) OR TBL_RECFORM_DEC_PT(4) + ); + +-- +-- Final Table Listing +-- *INPUTS*===================================*OUTPUTS*=================* +-- | | | +-- | rf1_instr_q | dec_byp_rf1_ca_used | +-- | | rf1_instr_q | | dec_byp_rf1_ov_used | +-- | | | rf1_instr_q | | | rf1_xer_ca_update | +-- | | | | rf1_instr_q | | | | rf1_xer_ov_update | +-- | | | | | | | | | | | +-- | 000000 1111111112 2222222223 3 | | | | | | +-- | 012345 1234567890 1234567890 1 | | | | | | +-- *TYPE*=====================================+=========================+ +-- | PPPPPP PPPPPPPPPP PPPPPPPPPP P | P P P P | +-- *POLARITY*-------------------------------->| + + + + | +-- *PHASE*----------------------------------->| T T T T | +-- *TERMS*====================================+=========================+ +-- 1 | 011111 0000100000 0101010011 - | 1 1 . . | +-- 2 | 011111 ---------- 110011101- - | . . 1 . | +-- 3 | 01-1-1 ---------- 110011101- 1 | . 1 . . | +-- 4 | 0111-1 ---------- 001-010110 - | . 1 . . | +-- 5 | 011111 ---------- 100-101000 - | . . . 1 | +-- 6 | 01-1-1 ---------- 011-011100 1 | . 1 . . | +-- 7 | 011111 ---------- 1-00001010 - | . . . 1 | +-- 8 | 01-1-1 ---------- 000-111100 1 | . 1 . . | +-- 9 | 011111 ---------- 10111010-- - | . . . 1 | +-- 10 | 0111-1 ---------- 0000-00000 - | . 1 . . | +-- 11 | 011111 ---------- 1011-010-0 - | . . . 1 | +-- 12 | 01-1-1 ---------- 111-011010 1 | . 1 . . | +-- 13 | 011111 ---------- 1100-110-0 - | . . 1 . | +-- 14 | 01-1-1 ---------- 1100-110-0 1 | . 1 . . | +-- 15 | 01-1-1 ---------- 01-0-11100 1 | . 1 . . | +-- 16 | 011111 ---------- 111--010-1 - | . . . 1 | +-- 17 | 011111 ---------- 10-00010-0 - | . . . 1 | +-- 18 | 01-1-1 ---------- 0-00-11100 1 | . 1 . . | +-- 19 | 01-1-1 ---------- -0000-1011 1 | . 1 . . | +-- 20 | 011111 ---------- -011-010-0 - | 1 . 1 . | +-- 21 | 011111 ---------- -01-0010-0 - | 1 . . . | +-- 22 | 01-1-1 ---------- 11-0-11010 1 | . 1 . . | +-- 23 | 0111-- ---------- -00-101000 1 | . 1 . . | +-- 24 | 01-1-1 ---------- -01-0010-0 1 | . 1 . . | +-- 25 | 011111 ---------- -0-00010-0 - | . . 1 . | +-- 26 | 0111-- ---------- -0000-1000 1 | . 1 . . | +-- 27 | 01-1-1 ---------- --00001010 1 | . 1 . . | +-- 28 | 01-1-1 ---------- -0111010-- 1 | . 1 . . | +-- 29 | 01-1-1 ---------- -00-0010-1 1 | . 1 . . | +-- 30 | 001-00 ---------- ---------- - | . . 1 . | +-- 31 | 0111-0 ---------- -------00- 1 | . 1 . . | +-- 32 | 00101- ---------- ---------- - | . 1 . . | +-- 33 | 0111-0 ---------- ------0--- 1 | . 1 . . | +-- 34 | 001101 ---------- ---------- - | . 1 1 . | +-- 35 | 0101-1 ---------- ---------- 1 | . 1 . . | +-- 36 | 01-10- ---------- ---------- 1 | . 1 . . | +-- 37 | 01110- ---------- ---------- - | . 1 . . | +-- *====================================================================* +-- +-- Table TBL_XER_DEC Signal Assignments for Product Terms +MQQ250:TBL_XER_DEC_PT(1) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(11) & RF1_INSTR_Q(12) & + RF1_INSTR_Q(13) & RF1_INSTR_Q(14) & + RF1_INSTR_Q(15) & RF1_INSTR_Q(16) & + RF1_INSTR_Q(17) & RF1_INSTR_Q(18) & + RF1_INSTR_Q(19) & RF1_INSTR_Q(20) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111100001000000101010011")); +MQQ251:TBL_XER_DEC_PT(2) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) ) , STD_ULOGIC_VECTOR'("011111110011101")); +MQQ252:TBL_XER_DEC_PT(3) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("01111100111011")); +MQQ253:TBL_XER_DEC_PT(4) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(21) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111001010110")); +MQQ254:TBL_XER_DEC_PT(5) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111100101000")); +MQQ255:TBL_XER_DEC_PT(6) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("01110110111001")); +MQQ256:TBL_XER_DEC_PT(7) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("011111100001010")); +MQQ257:TBL_XER_DEC_PT(8) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("01110001111001")); +MQQ258:TBL_XER_DEC_PT(9) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) + ) , STD_ULOGIC_VECTOR'("01111110111010")); +MQQ259:TBL_XER_DEC_PT(10) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(21) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111000000000")); +MQQ260:TBL_XER_DEC_PT(11) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111110110100")); +MQQ261:TBL_XER_DEC_PT(12) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("01111110110101")); +MQQ262:TBL_XER_DEC_PT(13) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111111001100")); +MQQ263:TBL_XER_DEC_PT(14) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(30) & + RF1_INSTR_Q(31) ) , STD_ULOGIC_VECTOR'("0111110011001")); +MQQ264:TBL_XER_DEC_PT(15) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_INSTR_Q(31) ) , STD_ULOGIC_VECTOR'("0111010111001")); +MQQ265:TBL_XER_DEC_PT(16) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("0111111110101")); +MQQ266:TBL_XER_DEC_PT(17) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(30) + ) , STD_ULOGIC_VECTOR'("01111110000100")); +MQQ267:TBL_XER_DEC_PT(18) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_INSTR_Q(31) ) , STD_ULOGIC_VECTOR'("0111000111001")); +MQQ268:TBL_XER_DEC_PT(19) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_INSTR_Q(31) ) , STD_ULOGIC_VECTOR'("0111000010111")); +MQQ269:TBL_XER_DEC_PT(20) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("0111110110100")); +MQQ270:TBL_XER_DEC_PT(21) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("0111110100100")); +MQQ271:TBL_XER_DEC_PT(22) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_INSTR_Q(31) ) , STD_ULOGIC_VECTOR'("0111110110101")); +MQQ272:TBL_XER_DEC_PT(23) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_INSTR_Q(31) ) , STD_ULOGIC_VECTOR'("0111001010001")); +MQQ273:TBL_XER_DEC_PT(24) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(30) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("011101001001")); +MQQ274:TBL_XER_DEC_PT(25) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(30) ) , STD_ULOGIC_VECTOR'("0111110000100")); +MQQ275:TBL_XER_DEC_PT(26) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_INSTR_Q(31) ) , STD_ULOGIC_VECTOR'("0111000010001")); +MQQ276:TBL_XER_DEC_PT(27) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_INSTR_Q(31) ) , STD_ULOGIC_VECTOR'("0111000010101")); +MQQ277:TBL_XER_DEC_PT(28) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("011101110101")); +MQQ278:TBL_XER_DEC_PT(29) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(30) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("011100001011")); +MQQ279:TBL_XER_DEC_PT(30) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) ) , STD_ULOGIC_VECTOR'("00100")); +MQQ280:TBL_XER_DEC_PT(31) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("01110001")); +MQQ281:TBL_XER_DEC_PT(32) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) ) , STD_ULOGIC_VECTOR'("00101")); +MQQ282:TBL_XER_DEC_PT(33) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(31) ) , STD_ULOGIC_VECTOR'("0111001")); +MQQ283:TBL_XER_DEC_PT(34) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) + ) , STD_ULOGIC_VECTOR'("001101")); +MQQ284:TBL_XER_DEC_PT(35) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("010111")); +MQQ285:TBL_XER_DEC_PT(36) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(31) ) , STD_ULOGIC_VECTOR'("01101")); +MQQ286:TBL_XER_DEC_PT(37) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) ) , STD_ULOGIC_VECTOR'("01110")); +-- Table TBL_XER_DEC Signal Assignments for Outputs +MQQ287:DEC_BYP_RF1_CA_USED <= + (TBL_XER_DEC_PT(1) OR TBL_XER_DEC_PT(20) + OR TBL_XER_DEC_PT(21)); +MQQ288:DEC_BYP_RF1_OV_USED <= + (TBL_XER_DEC_PT(1) OR TBL_XER_DEC_PT(3) + OR TBL_XER_DEC_PT(4) OR TBL_XER_DEC_PT(6) + OR TBL_XER_DEC_PT(8) OR TBL_XER_DEC_PT(10) + OR TBL_XER_DEC_PT(12) OR TBL_XER_DEC_PT(14) + OR TBL_XER_DEC_PT(15) OR TBL_XER_DEC_PT(18) + OR TBL_XER_DEC_PT(19) OR TBL_XER_DEC_PT(22) + OR TBL_XER_DEC_PT(23) OR TBL_XER_DEC_PT(24) + OR TBL_XER_DEC_PT(26) OR TBL_XER_DEC_PT(27) + OR TBL_XER_DEC_PT(28) OR TBL_XER_DEC_PT(29) + OR TBL_XER_DEC_PT(31) OR TBL_XER_DEC_PT(32) + OR TBL_XER_DEC_PT(33) OR TBL_XER_DEC_PT(34) + OR TBL_XER_DEC_PT(35) OR TBL_XER_DEC_PT(36) + OR TBL_XER_DEC_PT(37)); +MQQ289:RF1_XER_CA_UPDATE <= + (TBL_XER_DEC_PT(2) OR TBL_XER_DEC_PT(13) + OR TBL_XER_DEC_PT(20) OR TBL_XER_DEC_PT(25) + OR TBL_XER_DEC_PT(30) OR TBL_XER_DEC_PT(34) + ); +MQQ290:RF1_XER_OV_UPDATE <= + (TBL_XER_DEC_PT(5) OR TBL_XER_DEC_PT(7) + OR TBL_XER_DEC_PT(9) OR TBL_XER_DEC_PT(11) + OR TBL_XER_DEC_PT(16) OR TBL_XER_DEC_PT(17) + ); + +-- +-- Final Table Listing +-- *INPUTS*=============================*OUTPUTS*=* +-- | | | +-- | rf1_instr_q | rf1_pri | +-- | | rf1_instr_q | | | +-- | | | rf1_instr_q | | | +-- | | | | | | | +-- | 000000 000011111111112 22222222233 | 000 | +-- | 012345 678901234567890 12345678901 | 012 | +-- *TYPE*===============================+=========+ +-- | PPPPPP PPPPPPPPPPPPPPP PPPPPPPPPPP | PPP | +-- *POLARITY*-------------------------->| +++ | +-- *PHASE*----------------------------->| TTT | +-- *TERMS*==============================+=========+ +-- 1 | 011111 111111111111111 01101111000 | ..1 | +-- 2 | 011111 000100001000010 01101111000 | 1.. | +-- 3 | 011111 000010000100001 01101111000 | .1. | +-- 4 | 011111 001010010100101 01101111000 | 1.1 | +-- 5 | 011111 001100011000110 01101111000 | .11 | +-- 6 | 011111 000110001100011 01101111000 | 11. | +-- 7 | 011111 001110011100111 01101111000 | 111 | +-- *==============================================* +-- +-- Table TBL_PRI_CHANGE Signal Assignments for Product Terms +MQQ291:TBL_PRI_CHANGE_PT(1) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(06) & RF1_INSTR_Q(07) & + RF1_INSTR_Q(08) & RF1_INSTR_Q(09) & + RF1_INSTR_Q(10) & RF1_INSTR_Q(11) & + RF1_INSTR_Q(12) & RF1_INSTR_Q(13) & + RF1_INSTR_Q(14) & RF1_INSTR_Q(15) & + RF1_INSTR_Q(16) & RF1_INSTR_Q(17) & + RF1_INSTR_Q(18) & RF1_INSTR_Q(19) & + RF1_INSTR_Q(20) & RF1_INSTR_Q(21) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("01111111111111111111101101111000")); +MQQ292:TBL_PRI_CHANGE_PT(2) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(06) & RF1_INSTR_Q(07) & + RF1_INSTR_Q(08) & RF1_INSTR_Q(09) & + RF1_INSTR_Q(10) & RF1_INSTR_Q(11) & + RF1_INSTR_Q(12) & RF1_INSTR_Q(13) & + RF1_INSTR_Q(14) & RF1_INSTR_Q(15) & + RF1_INSTR_Q(16) & RF1_INSTR_Q(17) & + RF1_INSTR_Q(18) & RF1_INSTR_Q(19) & + RF1_INSTR_Q(20) & RF1_INSTR_Q(21) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("01111100010000100001001101111000")); +MQQ293:TBL_PRI_CHANGE_PT(3) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(06) & RF1_INSTR_Q(07) & + RF1_INSTR_Q(08) & RF1_INSTR_Q(09) & + RF1_INSTR_Q(10) & RF1_INSTR_Q(11) & + RF1_INSTR_Q(12) & RF1_INSTR_Q(13) & + RF1_INSTR_Q(14) & RF1_INSTR_Q(15) & + RF1_INSTR_Q(16) & RF1_INSTR_Q(17) & + RF1_INSTR_Q(18) & RF1_INSTR_Q(19) & + RF1_INSTR_Q(20) & RF1_INSTR_Q(21) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("01111100001000010000101101111000")); +MQQ294:TBL_PRI_CHANGE_PT(4) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(06) & RF1_INSTR_Q(07) & + RF1_INSTR_Q(08) & RF1_INSTR_Q(09) & + RF1_INSTR_Q(10) & RF1_INSTR_Q(11) & + RF1_INSTR_Q(12) & RF1_INSTR_Q(13) & + RF1_INSTR_Q(14) & RF1_INSTR_Q(15) & + RF1_INSTR_Q(16) & RF1_INSTR_Q(17) & + RF1_INSTR_Q(18) & RF1_INSTR_Q(19) & + RF1_INSTR_Q(20) & RF1_INSTR_Q(21) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("01111100101001010010101101111000")); +MQQ295:TBL_PRI_CHANGE_PT(5) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(06) & RF1_INSTR_Q(07) & + RF1_INSTR_Q(08) & RF1_INSTR_Q(09) & + RF1_INSTR_Q(10) & RF1_INSTR_Q(11) & + RF1_INSTR_Q(12) & RF1_INSTR_Q(13) & + RF1_INSTR_Q(14) & RF1_INSTR_Q(15) & + RF1_INSTR_Q(16) & RF1_INSTR_Q(17) & + RF1_INSTR_Q(18) & RF1_INSTR_Q(19) & + RF1_INSTR_Q(20) & RF1_INSTR_Q(21) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("01111100110001100011001101111000")); +MQQ296:TBL_PRI_CHANGE_PT(6) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(06) & RF1_INSTR_Q(07) & + RF1_INSTR_Q(08) & RF1_INSTR_Q(09) & + RF1_INSTR_Q(10) & RF1_INSTR_Q(11) & + RF1_INSTR_Q(12) & RF1_INSTR_Q(13) & + RF1_INSTR_Q(14) & RF1_INSTR_Q(15) & + RF1_INSTR_Q(16) & RF1_INSTR_Q(17) & + RF1_INSTR_Q(18) & RF1_INSTR_Q(19) & + RF1_INSTR_Q(20) & RF1_INSTR_Q(21) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("01111100011000110001101101111000")); +MQQ297:TBL_PRI_CHANGE_PT(7) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(06) & RF1_INSTR_Q(07) & + RF1_INSTR_Q(08) & RF1_INSTR_Q(09) & + RF1_INSTR_Q(10) & RF1_INSTR_Q(11) & + RF1_INSTR_Q(12) & RF1_INSTR_Q(13) & + RF1_INSTR_Q(14) & RF1_INSTR_Q(15) & + RF1_INSTR_Q(16) & RF1_INSTR_Q(17) & + RF1_INSTR_Q(18) & RF1_INSTR_Q(19) & + RF1_INSTR_Q(20) & RF1_INSTR_Q(21) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) & RF1_INSTR_Q(31) + ) , STD_ULOGIC_VECTOR'("01111100111001110011101101111000")); +-- Table TBL_PRI_CHANGE Signal Assignments for Outputs +MQQ298:RF1_PRI(00) <= + (TBL_PRI_CHANGE_PT(2) OR TBL_PRI_CHANGE_PT(4) + OR TBL_PRI_CHANGE_PT(6) OR TBL_PRI_CHANGE_PT(7) + ); +MQQ299:RF1_PRI(01) <= + (TBL_PRI_CHANGE_PT(3) OR TBL_PRI_CHANGE_PT(5) + OR TBL_PRI_CHANGE_PT(6) OR TBL_PRI_CHANGE_PT(7) + ); +MQQ300:RF1_PRI(02) <= + (TBL_PRI_CHANGE_PT(1) OR TBL_PRI_CHANGE_PT(4) + OR TBL_PRI_CHANGE_PT(5) OR TBL_PRI_CHANGE_PT(7) + ); + +-- +-- Final Table Listing +-- *INPUTS*==================================================*OUTPUTS*=========================================* +-- | | | +-- | rf1_instr_q | rf1_cache_acc | +-- | | rf1_instr_q | | xu_lsu_rf1_is_msgsnd | +-- | | | rf1_instr_q | | | xu_lsu_rf1_mbar_instr | +-- | | | | rf1_instr_q | | | | xu_lsu_rf1_sync_instr | +-- | | | | | rf1_axu_ld_or_st_q | | | | | xu_lsu_rf1_tlbsync_instr | +-- | | | | | | rf1_axu_mftgpr | | | | | | xu_lsu_rf1_wclr_instr | +-- | | | | | | | rf1_axu_mffgpr | | | | | | | xu_lsu_rf1_wchk_instr | +-- | | | | | | | | rf1_axu_movedp | | | | | | | | xu_lsu_rf1_src_gpr | +-- | | | | | | | | | rf1_val_stg | | | | | | | | | xu_lsu_rf1_src_axu | +-- | | | | | | | | | | | | | | | | | | | | xu_lsu_rf1_src_dp | +-- | | | | | | | | | | | | | | | | | | | | | xu_lsu_rf1_targ_gpr | +-- | | | | | | | | | | | | | | | | | | | | | | xu_lsu_rf1_targ_axu | +-- | | | | | | | | | | | | | | | | | | | | | | | xu_lsu_rf1_targ_dp | +-- | | | | | | | | | | | | | | | | | | | | | | | | rf1_cmd_act | +-- | | | | | | | | | | | | | | | | | | | | | | | | | xu_lsu_rf1_data_act | +-- | | | | | | | | | | | | | | | | | | | | | | | | | | rf1_mtspr_trace | +-- | | | | | | | | | | | | | | | | | | | | | | | | | | | rf1_derat_act | +-- | 000000 1111111112 2222222223 33 | | | | | | | | | | | | | | | | | | | | | | | | +-- | 012345 1234567890 1234567890 01 | | | | | | | | | | | | | | | | | | | | | | | | +-- *TYPE*====================================================+=================================================+ +-- | PPPPPP PPPPPPPPPP PPPPPPPPPP PP P P P P P | P P P P P P P P P P P P P P P P P | +-- *POLARITY*----------------------------------------------->| + + + + + + + + + + + + + + + + + | +-- *PHASE*-------------------------------------------------->| T T T T T T T T T T T T T T T T T | +-- *TERMS*===================================================+=================================================+ +-- 1 | 011111 0111011111 0111010011 -- - - - - 1 | . . . . . . . . . . . . . 1 . 1 . | +-- 2 | 011111 ---------- 0000-00011 -- - - - 0 1 | . . . . . . . . . . 1 . . . . . . | +-- 3 | 011111 ---------- 1110000110 -- - - - - 1 | . . . . . . 1 . . . . . . . . . . | +-- 4 | 011111 ---------- 0011001110 -- - - - - 1 | . 1 . . . . . . . . . . . 1 . . . | +-- 5 | 011111 ---------- 1101010110 -- - - - - 1 | . . 1 . . . . . . . . . . 1 . . . | +-- 6 | 011111 ---------- 1000110110 -- - - - - 1 | . . . . 1 . . . . . . . . 1 . . . | +-- 7 | 011111 ---------- 1110100110 -- - - - - 1 | 1 . . . . 1 . . . . . . . 1 . . . | +-- 8 | 011111 ---------- 1001010110 -- - - - - 1 | . . . 1 . . . . . . . . . 1 . . . | +-- 9 | 011111 ---------- 1110-10110 -- - - - - 1 | . . . . . . . . . . . . . . 1 . . | +-- 10 | 011111 ---------- 0001-00011 -- - - - - 1 | . . . . . . . 1 . . . . 1 1 1 . . | +-- 11 | 011111 ---------- 0000-00011 -- - - - - 1 | . . . . . . . . . 1 . . . 1 1 . . | +-- 12 | 011111 ---------- 1111-11111 -- - - - - 1 | 1 . . . . . . . . . . . . 1 . . 1 | +-- 13 | 011111 ---------- 0-11100110 -- - - - - 1 | 1 . . . . . . . . . . . . 1 . . 1 | +-- 14 | 011111 ---------- 001--10111 -- - - - - 1 | . . . . . . . . . . . . . . 1 . . | +-- 15 | 011111 ---------- 0-1001011- -- - - - - 1 | . . . . . . . . . . . . . . 1 . . | +-- 16 | 011111 ---------- 001-01011- -- - - - - 1 | . . . . . . . . . . . . . . 1 . . | +-- 17 | 011111 ---------- -11-0-0110 -- - - - - 1 | . . . . . . . . . . . . . 1 . . . | +-- 18 | 011111 ---------- 00--01-111 -- - - - - 1 | . . . . . . . . . . . . . . 1 . . | +-- 19 | 011111 ---------- 0010-00110 -- - - - - 1 | 1 . . . . . . . . . . . . 1 . . 1 | +-- 20 | 011111 ---------- 0-100-0110 -- - - - - 1 | 1 . . . . . . . . . . . . . . . 1 | +-- 21 | 011111 ---------- 01010101-1 -- - - - - 1 | 1 . . . . . . . . . . . . 1 1 . 1 | +-- 22 | 011111 ---------- 0-1-010110 -- - - - - 1 | 1 . . . . . . . . . . . . . . . 1 | +-- 23 | 011111 ---------- 0-00-11111 -- - - - - 1 | 1 . . . . . . . . . . . . 1 . . 1 | +-- 24 | 011111 ---------- 00-1010100 -- - - - - 1 | 1 . . . . . . . . . . . . 1 1 . 1 | +-- 25 | 011111 ---------- 0000-10110 -- - - - - 1 | 1 . . . . . . . . . . . . 1 . . 1 | +-- 26 | 011111 ---------- 00-1-11111 -- - - - - 1 | 1 . . . . . . . . . . . . 1 . . 1 | +-- 27 | 011111 ---------- 000001010- -- - - - - 1 | 1 . . . . . . . . . . . . 1 1 . 1 | +-- 28 | 011111 ---------- 111--10110 -- - - - - 1 | 1 . . . . . . . . . . . . 1 . . 1 | +-- 29 | 011111 ---------- 0011-1011- -- - - - - 1 | 1 . . . . . . . . . . . . 1 . . 1 | +-- 30 | 011111 ---------- 10-00101-0 -- - - - - 1 | 1 . . . . . . . . . . . . 1 1 . 1 | +-- 31 | 011111 ---------- 0010-101-1 -- - - - - 1 | 1 . . . . . . . . . . . . 1 1 . 1 | +-- 32 | 011111 ---------- 1--0010110 -- - - - - 1 | 1 . . . . . . . . . . . . 1 1 . 1 | +-- 33 | 011111 ---------- 0-10-10111 -- - - - - 1 | 1 . . . . . . . . . . . . 1 1 . 1 | +-- 34 | 011111 ---------- 00-001-1-1 -- - - - - 1 | 1 . . . . . . . . . . . . 1 1 . 1 | +-- 35 | 011111 ---------- 0--001011- -- - - - - 1 | 1 . . . . . . . . . . . . 1 . . 1 | +-- 36 | 011111 ---------- 00--01011- -- - - - - 1 | 1 . . . . . . . . . . . . 1 . . 1 | +-- 37 | 011111 ---------- 0--001-111 -- - - - - 1 | 1 . . . . . . . . . . . . 1 1 . 1 | +-- 38 | 1-1010 ---------- ---------- -0 - - - - 1 | 1 . . . . . . . . . . . . 1 1 . 1 | +-- 39 | ------ ---------- ---------- -- 1 0 0 0 1 | 1 . . . . . . . . . . . . 1 1 . 1 | +-- 40 | 10-0-0 ---------- ---------- -- - - - - 1 | 1 . . . . . . . . . . . . 1 1 . 1 | +-- 41 | 111110 ---------- ---------- 0- - - - - 1 | 1 . . . . . . . . . . . . 1 1 . 1 | +-- 42 | ------ ---------- ---------- -- - - 1 1 1 | . . . . . . . . . 1 . 1 . 1 1 . . | +-- 43 | ------ ---------- ---------- -- - 1 - 1 1 | . . . . . . . . 1 . . . 1 1 1 . . | +-- 44 | ------ ---------- ---------- -- - 1 - 0 1 | . . . . . . . . 1 . 1 . . 1 1 . . | +-- 45 | ------ ---------- ---------- -- - - 1 0 1 | . . . . . . . 1 . . . 1 . 1 1 . . | +-- 46 | 10-10- ---------- ---------- -- - - - - 1 | 1 . . . . . . . . . . . . 1 1 . 1 | +-- 47 | 1001-- ---------- ---------- -- - - - - 1 | 1 . . . . . . . . . . . . 1 1 . 1 | +-- *===========================================================================================================* +-- +-- Table TBL_VAL_STG_GATE Signal Assignments for Product Terms +MQQ301:TBL_VAL_STG_GATE_PT(1) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(11) & RF1_INSTR_Q(12) & + RF1_INSTR_Q(13) & RF1_INSTR_Q(14) & + RF1_INSTR_Q(15) & RF1_INSTR_Q(16) & + RF1_INSTR_Q(17) & RF1_INSTR_Q(18) & + RF1_INSTR_Q(19) & RF1_INSTR_Q(20) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_VAL_STG ) , STD_ULOGIC_VECTOR'("011111011101111101110100111")); +MQQ302:TBL_VAL_STG_GATE_PT(2) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) & RF1_AXU_MOVEDP & + RF1_VAL_STG ) , STD_ULOGIC_VECTOR'("01111100000001101")); +MQQ303:TBL_VAL_STG_GATE_PT(3) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_VAL_STG ) , STD_ULOGIC_VECTOR'("01111111100001101")); +MQQ304:TBL_VAL_STG_GATE_PT(4) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_VAL_STG ) , STD_ULOGIC_VECTOR'("01111100110011101")); +MQQ305:TBL_VAL_STG_GATE_PT(5) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_VAL_STG ) , STD_ULOGIC_VECTOR'("01111111010101101")); +MQQ306:TBL_VAL_STG_GATE_PT(6) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_VAL_STG ) , STD_ULOGIC_VECTOR'("01111110001101101")); +MQQ307:TBL_VAL_STG_GATE_PT(7) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_VAL_STG ) , STD_ULOGIC_VECTOR'("01111111101001101")); +MQQ308:TBL_VAL_STG_GATE_PT(8) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_VAL_STG ) , STD_ULOGIC_VECTOR'("01111110010101101")); +MQQ309:TBL_VAL_STG_GATE_PT(9) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) & RF1_VAL_STG + ) , STD_ULOGIC_VECTOR'("0111111110101101")); +MQQ310:TBL_VAL_STG_GATE_PT(10) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) & RF1_VAL_STG + ) , STD_ULOGIC_VECTOR'("0111110001000111")); +MQQ311:TBL_VAL_STG_GATE_PT(11) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) & RF1_VAL_STG + ) , STD_ULOGIC_VECTOR'("0111110000000111")); +MQQ312:TBL_VAL_STG_GATE_PT(12) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) & RF1_VAL_STG + ) , STD_ULOGIC_VECTOR'("0111111111111111")); +MQQ313:TBL_VAL_STG_GATE_PT(13) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) & RF1_VAL_STG + ) , STD_ULOGIC_VECTOR'("0111110111001101")); +MQQ314:TBL_VAL_STG_GATE_PT(14) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_VAL_STG ) , STD_ULOGIC_VECTOR'("011111001101111")); +MQQ315:TBL_VAL_STG_GATE_PT(15) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_VAL_STG ) , STD_ULOGIC_VECTOR'("011111010010111")); +MQQ316:TBL_VAL_STG_GATE_PT(16) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_VAL_STG ) , STD_ULOGIC_VECTOR'("011111001010111")); +MQQ317:TBL_VAL_STG_GATE_PT(17) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(22) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) & RF1_VAL_STG + ) , STD_ULOGIC_VECTOR'("01111111001101")); +MQQ318:TBL_VAL_STG_GATE_PT(18) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) & RF1_VAL_STG + ) , STD_ULOGIC_VECTOR'("01111100011111")); +MQQ319:TBL_VAL_STG_GATE_PT(19) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) & RF1_VAL_STG + ) , STD_ULOGIC_VECTOR'("0111110010001101")); +MQQ320:TBL_VAL_STG_GATE_PT(20) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_VAL_STG ) , STD_ULOGIC_VECTOR'("011111010001101")); +MQQ321:TBL_VAL_STG_GATE_PT(21) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(30) & RF1_VAL_STG + ) , STD_ULOGIC_VECTOR'("0111110101010111")); +MQQ322:TBL_VAL_STG_GATE_PT(22) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_VAL_STG ) , STD_ULOGIC_VECTOR'("011111010101101")); +MQQ323:TBL_VAL_STG_GATE_PT(23) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_VAL_STG ) , STD_ULOGIC_VECTOR'("011111000111111")); +MQQ324:TBL_VAL_STG_GATE_PT(24) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) & RF1_VAL_STG + ) , STD_ULOGIC_VECTOR'("0111110010101001")); +MQQ325:TBL_VAL_STG_GATE_PT(25) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) & RF1_VAL_STG + ) , STD_ULOGIC_VECTOR'("0111110000101101")); +MQQ326:TBL_VAL_STG_GATE_PT(26) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_VAL_STG ) , STD_ULOGIC_VECTOR'("011111001111111")); +MQQ327:TBL_VAL_STG_GATE_PT(27) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_VAL_STG + ) , STD_ULOGIC_VECTOR'("0111110000010101")); +MQQ328:TBL_VAL_STG_GATE_PT(28) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_VAL_STG ) , STD_ULOGIC_VECTOR'("011111111101101")); +MQQ329:TBL_VAL_STG_GATE_PT(29) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_VAL_STG ) , STD_ULOGIC_VECTOR'("011111001110111")); +MQQ330:TBL_VAL_STG_GATE_PT(30) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(30) & + RF1_VAL_STG ) , STD_ULOGIC_VECTOR'("011111100010101")); +MQQ331:TBL_VAL_STG_GATE_PT(31) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(23) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(27) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(30) & + RF1_VAL_STG ) , STD_ULOGIC_VECTOR'("011111001010111")); +MQQ332:TBL_VAL_STG_GATE_PT(32) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_VAL_STG ) , STD_ULOGIC_VECTOR'("011111100101101")); +MQQ333:TBL_VAL_STG_GATE_PT(33) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(23) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_INSTR_Q(30) & + RF1_VAL_STG ) , STD_ULOGIC_VECTOR'("011111010101111")); +MQQ334:TBL_VAL_STG_GATE_PT(34) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(24) & RF1_INSTR_Q(25) & + RF1_INSTR_Q(26) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(30) & RF1_VAL_STG + ) , STD_ULOGIC_VECTOR'("01111100001111")); +MQQ335:TBL_VAL_STG_GATE_PT(35) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_VAL_STG + ) , STD_ULOGIC_VECTOR'("01111100010111")); +MQQ336:TBL_VAL_STG_GATE_PT(36) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(22) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(27) & RF1_INSTR_Q(28) & + RF1_INSTR_Q(29) & RF1_VAL_STG + ) , STD_ULOGIC_VECTOR'("01111100010111")); +MQQ337:TBL_VAL_STG_GATE_PT(37) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(21) & RF1_INSTR_Q(24) & + RF1_INSTR_Q(25) & RF1_INSTR_Q(26) & + RF1_INSTR_Q(28) & RF1_INSTR_Q(29) & + RF1_INSTR_Q(30) & RF1_VAL_STG + ) , STD_ULOGIC_VECTOR'("01111100011111")); +MQQ338:TBL_VAL_STG_GATE_PT(38) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(02) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(04) & + RF1_INSTR_Q(05) & RF1_INSTR_Q(31) & + RF1_VAL_STG ) , STD_ULOGIC_VECTOR'("1101001")); +MQQ339:TBL_VAL_STG_GATE_PT(39) <= + Eq(( RF1_AXU_LD_OR_ST_Q & RF1_AXU_MFTGPR & + RF1_AXU_MFFGPR & RF1_AXU_MOVEDP & + RF1_VAL_STG ) , STD_ULOGIC_VECTOR'("10001")); +MQQ340:TBL_VAL_STG_GATE_PT(40) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(05) & + RF1_VAL_STG ) , STD_ULOGIC_VECTOR'("10001")); +MQQ341:TBL_VAL_STG_GATE_PT(41) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_INSTR_Q(04) & RF1_INSTR_Q(05) & + RF1_INSTR_Q(30) & RF1_VAL_STG + ) , STD_ULOGIC_VECTOR'("11111001")); +MQQ342:TBL_VAL_STG_GATE_PT(42) <= + Eq(( RF1_AXU_MFFGPR & RF1_AXU_MOVEDP & + RF1_VAL_STG ) , STD_ULOGIC_VECTOR'("111")); +MQQ343:TBL_VAL_STG_GATE_PT(43) <= + Eq(( RF1_AXU_MFTGPR & RF1_AXU_MOVEDP & + RF1_VAL_STG ) , STD_ULOGIC_VECTOR'("111")); +MQQ344:TBL_VAL_STG_GATE_PT(44) <= + Eq(( RF1_AXU_MFTGPR & RF1_AXU_MOVEDP & + RF1_VAL_STG ) , STD_ULOGIC_VECTOR'("101")); +MQQ345:TBL_VAL_STG_GATE_PT(45) <= + Eq(( RF1_AXU_MFFGPR & RF1_AXU_MOVEDP & + RF1_VAL_STG ) , STD_ULOGIC_VECTOR'("101")); +MQQ346:TBL_VAL_STG_GATE_PT(46) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(03) & RF1_INSTR_Q(04) & + RF1_VAL_STG ) , STD_ULOGIC_VECTOR'("10101")); +MQQ347:TBL_VAL_STG_GATE_PT(47) <= + Eq(( RF1_INSTR_Q(00) & RF1_INSTR_Q(01) & + RF1_INSTR_Q(02) & RF1_INSTR_Q(03) & + RF1_VAL_STG ) , STD_ULOGIC_VECTOR'("10011")); +-- Table TBL_VAL_STG_GATE Signal Assignments for Outputs +MQQ348:RF1_CACHE_ACC <= + (TBL_VAL_STG_GATE_PT(7) OR TBL_VAL_STG_GATE_PT(12) + OR TBL_VAL_STG_GATE_PT(13) OR TBL_VAL_STG_GATE_PT(19) + OR TBL_VAL_STG_GATE_PT(20) OR TBL_VAL_STG_GATE_PT(21) + OR TBL_VAL_STG_GATE_PT(22) OR TBL_VAL_STG_GATE_PT(23) + OR TBL_VAL_STG_GATE_PT(24) OR TBL_VAL_STG_GATE_PT(25) + OR TBL_VAL_STG_GATE_PT(26) OR TBL_VAL_STG_GATE_PT(27) + OR TBL_VAL_STG_GATE_PT(28) OR TBL_VAL_STG_GATE_PT(29) + OR TBL_VAL_STG_GATE_PT(30) OR TBL_VAL_STG_GATE_PT(31) + OR TBL_VAL_STG_GATE_PT(32) OR TBL_VAL_STG_GATE_PT(33) + OR TBL_VAL_STG_GATE_PT(34) OR TBL_VAL_STG_GATE_PT(35) + OR TBL_VAL_STG_GATE_PT(36) OR TBL_VAL_STG_GATE_PT(37) + OR TBL_VAL_STG_GATE_PT(38) OR TBL_VAL_STG_GATE_PT(39) + OR TBL_VAL_STG_GATE_PT(40) OR TBL_VAL_STG_GATE_PT(41) + OR TBL_VAL_STG_GATE_PT(46) OR TBL_VAL_STG_GATE_PT(47) + ); +MQQ349:XU_LSU_RF1_IS_MSGSND <= + (TBL_VAL_STG_GATE_PT(4)); +MQQ350:XU_LSU_RF1_MBAR_INSTR <= + (TBL_VAL_STG_GATE_PT(5)); +MQQ351:XU_LSU_RF1_SYNC_INSTR <= + (TBL_VAL_STG_GATE_PT(8)); +MQQ352:XU_LSU_RF1_TLBSYNC_INSTR <= + (TBL_VAL_STG_GATE_PT(6)); +MQQ353:XU_LSU_RF1_WCLR_INSTR <= + (TBL_VAL_STG_GATE_PT(7)); +MQQ354:XU_LSU_RF1_WCHK_INSTR <= + (TBL_VAL_STG_GATE_PT(3)); +MQQ355:XU_LSU_RF1_SRC_GPR <= + (TBL_VAL_STG_GATE_PT(10) OR TBL_VAL_STG_GATE_PT(45) + ); +MQQ356:XU_LSU_RF1_SRC_AXU <= + (TBL_VAL_STG_GATE_PT(43) OR TBL_VAL_STG_GATE_PT(44) + ); +MQQ357:XU_LSU_RF1_SRC_DP <= + (TBL_VAL_STG_GATE_PT(11) OR TBL_VAL_STG_GATE_PT(42) + ); +MQQ358:XU_LSU_RF1_TARG_GPR <= + (TBL_VAL_STG_GATE_PT(2) OR TBL_VAL_STG_GATE_PT(44) + ); +MQQ359:XU_LSU_RF1_TARG_AXU <= + (TBL_VAL_STG_GATE_PT(42) OR TBL_VAL_STG_GATE_PT(45) + ); +MQQ360:XU_LSU_RF1_TARG_DP <= + (TBL_VAL_STG_GATE_PT(10) OR TBL_VAL_STG_GATE_PT(43) + ); +MQQ361:RF1_CMD_ACT <= + (TBL_VAL_STG_GATE_PT(1) OR TBL_VAL_STG_GATE_PT(4) + OR TBL_VAL_STG_GATE_PT(5) OR TBL_VAL_STG_GATE_PT(6) + OR TBL_VAL_STG_GATE_PT(7) OR TBL_VAL_STG_GATE_PT(8) + OR TBL_VAL_STG_GATE_PT(10) OR TBL_VAL_STG_GATE_PT(11) + OR TBL_VAL_STG_GATE_PT(12) OR TBL_VAL_STG_GATE_PT(13) + OR TBL_VAL_STG_GATE_PT(17) OR TBL_VAL_STG_GATE_PT(19) + OR TBL_VAL_STG_GATE_PT(21) OR TBL_VAL_STG_GATE_PT(23) + OR TBL_VAL_STG_GATE_PT(24) OR TBL_VAL_STG_GATE_PT(25) + OR TBL_VAL_STG_GATE_PT(26) OR TBL_VAL_STG_GATE_PT(27) + OR TBL_VAL_STG_GATE_PT(28) OR TBL_VAL_STG_GATE_PT(29) + OR TBL_VAL_STG_GATE_PT(30) OR TBL_VAL_STG_GATE_PT(31) + OR TBL_VAL_STG_GATE_PT(32) OR TBL_VAL_STG_GATE_PT(33) + OR TBL_VAL_STG_GATE_PT(34) OR TBL_VAL_STG_GATE_PT(35) + OR TBL_VAL_STG_GATE_PT(36) OR TBL_VAL_STG_GATE_PT(37) + OR TBL_VAL_STG_GATE_PT(38) OR TBL_VAL_STG_GATE_PT(39) + OR TBL_VAL_STG_GATE_PT(40) OR TBL_VAL_STG_GATE_PT(41) + OR TBL_VAL_STG_GATE_PT(42) OR TBL_VAL_STG_GATE_PT(43) + OR TBL_VAL_STG_GATE_PT(44) OR TBL_VAL_STG_GATE_PT(45) + OR TBL_VAL_STG_GATE_PT(46) OR TBL_VAL_STG_GATE_PT(47) + ); +MQQ362:XU_LSU_RF1_DATA_ACT <= + (TBL_VAL_STG_GATE_PT(9) OR TBL_VAL_STG_GATE_PT(10) + OR TBL_VAL_STG_GATE_PT(11) OR TBL_VAL_STG_GATE_PT(14) + OR TBL_VAL_STG_GATE_PT(15) OR TBL_VAL_STG_GATE_PT(16) + OR TBL_VAL_STG_GATE_PT(18) OR TBL_VAL_STG_GATE_PT(21) + OR TBL_VAL_STG_GATE_PT(24) OR TBL_VAL_STG_GATE_PT(27) + OR TBL_VAL_STG_GATE_PT(30) OR TBL_VAL_STG_GATE_PT(31) + OR TBL_VAL_STG_GATE_PT(32) OR TBL_VAL_STG_GATE_PT(33) + OR TBL_VAL_STG_GATE_PT(34) OR TBL_VAL_STG_GATE_PT(37) + OR TBL_VAL_STG_GATE_PT(38) OR TBL_VAL_STG_GATE_PT(39) + OR TBL_VAL_STG_GATE_PT(40) OR TBL_VAL_STG_GATE_PT(41) + OR TBL_VAL_STG_GATE_PT(42) OR TBL_VAL_STG_GATE_PT(43) + OR TBL_VAL_STG_GATE_PT(44) OR TBL_VAL_STG_GATE_PT(45) + OR TBL_VAL_STG_GATE_PT(46) OR TBL_VAL_STG_GATE_PT(47) + ); +MQQ363:RF1_MTSPR_TRACE <= + (TBL_VAL_STG_GATE_PT(1)); +MQQ364:RF1_DERAT_ACT <= + (TBL_VAL_STG_GATE_PT(12) OR TBL_VAL_STG_GATE_PT(13) + OR TBL_VAL_STG_GATE_PT(19) OR TBL_VAL_STG_GATE_PT(20) + OR TBL_VAL_STG_GATE_PT(21) OR TBL_VAL_STG_GATE_PT(22) + OR TBL_VAL_STG_GATE_PT(23) OR TBL_VAL_STG_GATE_PT(24) + OR TBL_VAL_STG_GATE_PT(25) OR TBL_VAL_STG_GATE_PT(26) + OR TBL_VAL_STG_GATE_PT(27) OR TBL_VAL_STG_GATE_PT(28) + OR TBL_VAL_STG_GATE_PT(29) OR TBL_VAL_STG_GATE_PT(30) + OR TBL_VAL_STG_GATE_PT(31) OR TBL_VAL_STG_GATE_PT(32) + OR TBL_VAL_STG_GATE_PT(33) OR TBL_VAL_STG_GATE_PT(34) + OR TBL_VAL_STG_GATE_PT(35) OR TBL_VAL_STG_GATE_PT(36) + OR TBL_VAL_STG_GATE_PT(37) OR TBL_VAL_STG_GATE_PT(38) + OR TBL_VAL_STG_GATE_PT(39) OR TBL_VAL_STG_GATE_PT(40) + OR TBL_VAL_STG_GATE_PT(41) OR TBL_VAL_STG_GATE_PT(46) + OR TBL_VAL_STG_GATE_PT(47)); + +mark_unused(rf1_num_bytes_plus3(6 to 7)); +mark_unused(ex1_dp_rot_amt(0)); +is1_need_hole_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(is1_need_hole_offset), + scout => sov(is1_need_hole_offset), + din => is1_need_hole_d, + dout => is1_need_hole_q); +is2_need_hole_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(is2_need_hole_offset), + scout => sov(is2_need_hole_offset), + din => is2_need_hole_d, + dout => is2_need_hole_q); +rf0_back_inv_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_back_inv_offset), + scout => sov(rf0_back_inv_offset), + din => lsu_xu_is2_back_inv , + dout => rf0_back_inv_q); +rf0_back_inv_addr_latch : tri_rlmreg_p + generic map (width => rf0_back_inv_addr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => lsu_xu_is2_back_inv , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_back_inv_addr_offset to rf0_back_inv_addr_offset + rf0_back_inv_addr_q'length-1), + scout => sov(rf0_back_inv_addr_offset to rf0_back_inv_addr_offset + rf0_back_inv_addr_q'length-1), + din => lsu_xu_is2_back_inv_addr , + dout => rf0_back_inv_addr_q); +rf0_need_hole_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_need_hole_offset), + scout => sov(rf0_need_hole_offset), + din => is2_need_hole_q , + dout => rf0_need_hole_q); +rf1_3src_instr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => fxa_fxb_rf0_3src_instr , + dout(0) => rf1_3src_instr_q); +rf1_act_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf1_act_offset), + scout => sov(rf1_act_offset), + din => rf0_act, + dout => rf1_act_q); +rf1_axu_instr_type_latch : tri_regk + generic map (width => rf1_axu_instr_type_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => fxa_fxb_rf0_axu_instr_type , + dout => rf1_axu_instr_type_q); +rf1_axu_is_extload_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => fxa_fxb_rf0_axu_is_extload , + dout(0) => rf1_axu_is_extload_q); +rf1_axu_is_extstore_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => fxa_fxb_rf0_axu_is_extstore , + dout(0) => rf1_axu_is_extstore_q); +rf1_axu_ld_or_st_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf1_axu_ld_or_st_offset), + scout => sov(rf1_axu_ld_or_st_offset), + din => fxa_fxb_rf0_axu_ld_or_st , + dout => rf1_axu_ld_or_st_q); +rf1_axu_ldst_forcealign_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => fxa_fxb_rf0_axu_ldst_forcealign , + dout(0) => rf1_axu_ldst_forcealign_q); +rf1_axu_ldst_forceexcept_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => fxa_fxb_rf0_axu_ldst_forceexcept , + dout(0) => rf1_axu_ldst_forceexcept_q); +rf1_axu_ldst_indexed_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => fxa_fxb_rf0_axu_ldst_indexed , + dout(0) => rf1_axu_ldst_indexed_q); +rf1_axu_ldst_size_latch : tri_regk + generic map (width => rf1_axu_ldst_size_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => fxa_fxb_rf0_axu_ldst_size , + dout => rf1_axu_ldst_size_q); +rf1_axu_ldst_tag_latch : tri_regk + generic map (width => rf1_axu_ldst_tag_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => fxa_fxb_rf0_axu_ldst_tag , + dout => rf1_axu_ldst_tag_q); +rf1_axu_ldst_update_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => fxa_fxb_rf0_axu_ldst_update , + dout(0) => rf1_axu_ldst_update_q); +rf1_axu_mffgpr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => fxa_fxb_rf0_axu_mffgpr , + dout(0) => rf1_axu_mffgpr_q); +rf1_axu_mftgpr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => fxa_fxb_rf0_axu_mftgpr , + dout(0) => rf1_axu_mftgpr_q); +rf1_axu_movedp_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => fxa_fxb_rf0_axu_movedp , + dout(0) => rf1_axu_movedp_q); +rf1_axu_store_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => fxa_fxb_rf0_axu_store , + dout(0) => rf1_axu_store_q); +rf1_back_inv_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(rf1_back_inv_offset), + scout => sov(rf1_back_inv_offset), + din => rf0_back_inv_q , + dout => rf1_back_inv_q); +rf1_back_inv_addr_latch : tri_regk + generic map (width => rf1_back_inv_addr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_back_inv_q , + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => rf0_back_inv_addr_q , + dout => rf1_back_inv_addr_q); +rf1_error_latch : tri_regk + generic map (width => rf1_error_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => fxa_fxb_rf0_error , + dout => rf1_error_q); +rf1_gpr0_zero_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => fxa_fxb_rf0_gpr0_zero , + dout(0) => rf1_gpr0_zero_q); +rf1_gshare_latch : tri_regk + generic map (width => rf1_gshare_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => fxa_fxb_rf0_gshare , + dout => rf1_gshare_q); +rf1_ifar_latch : tri_regk + generic map (width => rf1_ifar_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => fxa_fxb_rf0_ifar , + dout => rf1_ifar_q); +rf1_instr_latch : tri_regk + generic map (width => rf1_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => fxa_fxb_rf0_instr , + dout => rf1_instr_q); +rf1_instr_21to30_00_latch : tri_regk + generic map (width => rf1_instr_21to30_00_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rf1_instr_21to30_00_d, + dout => rf1_instr_21to30_00_q); +rf1_instr_21to30_01_latch : tri_regk + generic map (width => rf1_instr_21to30_01_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rf1_instr_21to30_01_d, + dout => rf1_instr_21to30_01_q); +rf1_instr_21to30_02_latch : tri_regk + generic map (width => rf1_instr_21to30_02_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rf1_instr_21to30_02_d, + dout => rf1_instr_21to30_02_q); +rf1_instr_21to30_03_latch : tri_regk + generic map (width => rf1_instr_21to30_03_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rf1_instr_21to30_03_d, + dout => rf1_instr_21to30_03_q); +rf1_instr_21to30_04_latch : tri_regk + generic map (width => rf1_instr_21to30_04_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rf1_instr_21to30_04_d, + dout => rf1_instr_21to30_04_q); +rf1_instr_21to30_05_latch : tri_regk + generic map (width => rf1_instr_21to30_05_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rf1_instr_21to30_05_d, + dout => rf1_instr_21to30_05_q); +rf1_instr_21to30_06_latch : tri_regk + generic map (width => rf1_instr_21to30_06_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rf1_instr_21to30_06_d, + dout => rf1_instr_21to30_06_q); +rf1_instr_21to30_07_latch : tri_regk + generic map (width => rf1_instr_21to30_07_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rf1_instr_21to30_07_d, + dout => rf1_instr_21to30_07_q); +rf1_instr_21to30_08_latch : tri_regk + generic map (width => rf1_instr_21to30_08_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rf1_instr_21to30_08_d, + dout => rf1_instr_21to30_08_q); +rf1_instr_21to30_09_latch : tri_regk + generic map (width => rf1_instr_21to30_09_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rf1_instr_21to30_09_d, + dout => rf1_instr_21to30_09_q); +rf1_instr_21to30_10_latch : tri_regk + generic map (width => rf1_instr_21to30_10_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rf1_instr_21to30_10_d, + dout => rf1_instr_21to30_10_q); +rf1_is_isel_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rf1_is_isel_d, + dout(0) => rf1_is_isel_q); +rf1_is_ucode_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => fxa_fxb_rf0_is_ucode , + dout(0) => rf1_is_ucode_q); +rf1_issued_latch : tri_regk + generic map (width => rf1_issued_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => fxa_fxb_rf0_issued , + dout => rf1_issued_q); +rf1_match_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => fxa_fxb_rf0_match , + dout(0) => rf1_match_q); +rf1_mc_dep_chk_val_latch : tri_regk + generic map (width => rf1_mc_dep_chk_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rf1_mc_dep_chk_val_d, + dout => rf1_mc_dep_chk_val_q); +rf1_need_hole_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf1_need_hole_offset), + scout => sov(rf1_need_hole_offset), + din => rf0_need_hole_q , + dout => rf1_need_hole_q); +rf1_opcode_is_31_latch : tri_regk + generic map (width => rf1_opcode_is_31_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rf1_opcode_is_31_d, + dout => rf1_opcode_is_31_q); +rf1_pred_taken_cnt_latch : tri_regk + generic map (width => rf1_pred_taken_cnt_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => fxa_fxb_rf0_pred_taken_cnt , + dout => rf1_pred_taken_cnt_q); +rf1_pred_update_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => fxa_fxb_rf0_pred_update , + dout(0) => rf1_pred_update_q); +rf1_s1_latch : tri_regk + generic map (width => rf1_s1_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => fxa_fxb_rf0_s1 , + dout => rf1_s1_q); +rf1_s1_vld_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => fxa_fxb_rf0_s1_vld , + dout(0) => rf1_s1_vld_q); +rf1_s2_latch : tri_regk + generic map (width => rf1_s2_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => fxa_fxb_rf0_s2 , + dout => rf1_s2_q); +rf1_s2_vld_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => fxa_fxb_rf0_s2_vld , + dout(0) => rf1_s2_vld_q); +rf1_s3_latch : tri_regk + generic map (width => rf1_s3_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => fxa_fxb_rf0_s3 , + dout => rf1_s3_q); +rf1_s3_vld_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => fxa_fxb_rf0_s3_vld , + dout(0) => rf1_s3_vld_q); +rf1_ta_latch : tri_regk + generic map (width => rf1_ta_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => fxa_fxb_rf0_ta , + dout => rf1_ta_q); +rf1_ta_vld_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf1_ta_vld_offset), + scout => sov(rf1_ta_vld_offset), + din => fxa_fxb_rf0_ta_vld , + dout => rf1_ta_vld_q); +rf1_tid_latch : tri_regk + generic map (width => rf1_tid_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => fxa_fxb_rf0_tid , + dout => rf1_tid_q); +rf1_tid_2_latch : tri_regk + generic map (width => rf1_tid_2_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => fxa_fxb_rf0_tid , + dout => rf1_tid_2_q); +rf1_ucode_val_latch : tri_rlmreg_p + generic map (width => rf1_ucode_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf1_ucode_val_offset to rf1_ucode_val_offset + rf1_ucode_val_q'length-1), + scout => sov(rf1_ucode_val_offset to rf1_ucode_val_offset + rf1_ucode_val_q'length-1), + din => fxa_fxb_rf0_ucode_val , + dout => rf1_ucode_val_q); +rf1_use_imm_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => fxa_fxb_rf0_use_imm , + dout(0) => rf1_use_imm_q); +rf1_val_latch : tri_rlmreg_p + generic map (width => rf1_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf1_val_offset to rf1_val_offset + rf1_val_q'length-1), + scout => sov(rf1_val_offset to rf1_val_offset + rf1_val_q'length-1), + din => fxa_fxb_rf0_val , + dout => rf1_val_q); +rf1_val_iu_latch : tri_rlmreg_p + generic map (width => rf1_val_iu_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf1_val_iu_offset to rf1_val_iu_offset + rf1_val_iu_q'length-1), + scout => sov(rf1_val_iu_offset to rf1_val_iu_offset + rf1_val_iu_q'length-1), + din => fxa_fxb_rf0_val , + dout => rf1_val_iu_q); +rf1_xu_epid_instr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => fxa_fxb_rf0_xu_epid_instr , + dout(0) => rf1_xu_epid_instr_q); +ex1_act_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_act_offset), + scout => sov(ex1_act_offset), + din => ex1_act_d, + dout => ex1_act_q); +ex1_axu_instr_type_latch : tri_rlmreg_p + generic map (width => ex1_axu_instr_type_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_axu_instr_type_offset to ex1_axu_instr_type_offset + ex1_axu_instr_type_q'length-1), + scout => sov(ex1_axu_instr_type_offset to ex1_axu_instr_type_offset + ex1_axu_instr_type_q'length-1), + din => ex1_axu_instr_type_d, + dout => ex1_axu_instr_type_q); +ex1_axu_movedp_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_axu_movedp_offset), + scout => sov(ex1_axu_movedp_offset), + din => rf1_axu_movedp_q , + dout => ex1_axu_movedp_q); +ex1_back_inv_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_back_inv_offset), + scout => sov(ex1_back_inv_offset), + din => rf1_back_inv_q , + dout => ex1_back_inv_q); +ex1_bh_latch : tri_rlmreg_p + generic map (width => ex1_bh_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_bh_offset to ex1_bh_offset + ex1_bh_q'length-1), + scout => sov(ex1_bh_offset to ex1_bh_offset + ex1_bh_q'length-1), + din => rf1_bh , + dout => ex1_bh_q); +ex1_clear_barrier_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_clear_barrier_offset), + scout => sov(ex1_clear_barrier_offset), + din => rf1_clear_barrier , + dout => ex1_clear_barrier_q); +ex1_ddmh_en_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_ddmh_en_offset), + scout => sov(ex1_ddmh_en_offset), + din => ex1_ddmh_en_d, + dout => ex1_ddmh_en_q); +ex1_ditc_illeg_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_ditc_illeg_offset), + scout => sov(ex1_ditc_illeg_offset), + din => ex1_ditc_illeg_d, + dout => ex1_ditc_illeg_q); +ex1_dp_indexed_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_dp_indexed_offset), + scout => sov(ex1_dp_indexed_offset), + din => ex1_dp_indexed_d, + dout => ex1_dp_indexed_q); +ex1_epid_instr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_epid_instr_offset), + scout => sov(ex1_epid_instr_offset), + din => ex1_epid_instr_d, + dout => ex1_epid_instr_q); +ex1_error_latch : tri_rlmreg_p + generic map (width => ex1_error_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_error_offset to ex1_error_offset + ex1_error_q'length-1), + scout => sov(ex1_error_offset to ex1_error_offset + ex1_error_q'length-1), + din => rf1_error_q , + dout => ex1_error_q); +ex1_getNIA_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_getNIA_offset), + scout => sov(ex1_getNIA_offset), + din => rf1_getNIA , + dout => ex1_getNIA_q); +ex1_gpr_we_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_gpr_we_offset), + scout => sov(ex1_gpr_we_offset), + din => ex1_gpr_we_d, + dout => ex1_gpr_we_q); +ex1_gshare_latch : tri_rlmreg_p + generic map (width => ex1_gshare_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_gshare_offset to ex1_gshare_offset + ex1_gshare_q'length-1), + scout => sov(ex1_gshare_offset to ex1_gshare_offset + ex1_gshare_q'length-1), + din => rf1_gshare_q , + dout => ex1_gshare_q); +ex1_instr_latch : tri_rlmreg_p + generic map (width => ex1_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_instr_offset to ex1_instr_offset + ex1_instr_q'length-1), + scout => sov(ex1_instr_offset to ex1_instr_offset + ex1_instr_q'length-1), + din => rf1_instr_q(11 to 25), + dout => ex1_instr_q); +ex1_instr_hypv_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_instr_hypv_offset), + scout => sov(ex1_instr_hypv_offset), + din => rf1_instr_hypv , + dout => ex1_instr_hypv_q); +ex1_instr_priv_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_instr_priv_offset), + scout => sov(ex1_instr_priv_offset), + din => rf1_instr_priv , + dout => ex1_instr_priv_q); +ex1_is_any_load_dac_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_any_load_dac_offset), + scout => sov(ex1_is_any_load_dac_offset), + din => rf1_is_any_load_dac , + dout => ex1_is_any_load_dac_q); +ex1_is_any_store_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_any_store_offset), + scout => sov(ex1_is_any_store_offset), + din => rf1_is_any_store , + dout => ex1_is_any_store_q); +ex1_is_any_store_dac_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_any_store_dac_offset), + scout => sov(ex1_is_any_store_dac_offset), + din => rf1_is_any_store_dac , + dout => ex1_is_any_store_dac_q); +ex1_is_attn_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_attn_offset), + scout => sov(ex1_is_attn_offset), + din => rf1_is_attn , + dout => ex1_is_attn_q); +ex1_is_bclr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_bclr_offset), + scout => sov(ex1_is_bclr_offset), + din => rf1_is_bclr , + dout => ex1_is_bclr_q); +ex1_is_cmp_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_cmp_offset), + scout => sov(ex1_is_cmp_offset), + din => rf1_cmp , + dout => ex1_is_cmp_q); +ex1_is_csync_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_csync_offset), + scout => sov(ex1_is_csync_offset), + din => rf1_is_csync, + dout => ex1_is_csync_q); +ex1_is_eratsxr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_eratsxr_offset), + scout => sov(ex1_is_eratsxr_offset), + din => rf1_is_eratsxr , + dout => ex1_is_eratsxr_q); +ex1_is_icswx_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_icswx_offset), + scout => sov(ex1_is_icswx_offset), + din => ex1_is_icswx_d, + dout => ex1_is_icswx_q); +ex1_is_isync_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_isync_offset), + scout => sov(ex1_is_isync_offset), + din => rf1_is_isync , + dout => ex1_is_isync_q); +ex1_is_ld_w_update_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_ld_w_update_offset), + scout => sov(ex1_is_ld_w_update_offset), + din => rf1_is_ld_w_update , + dout => ex1_is_ld_w_update_q); +ex1_is_lmw_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_lmw_offset), + scout => sov(ex1_is_lmw_offset), + din => rf1_is_lmw , + dout => ex1_is_lmw_q); +ex1_is_lswi_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_lswi_offset), + scout => sov(ex1_is_lswi_offset), + din => rf1_is_lswi , + dout => ex1_is_lswi_q); +ex1_is_lswx_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_lswx_offset), + scout => sov(ex1_is_lswx_offset), + din => rf1_is_lswx , + dout => ex1_is_lswx_q); +ex1_is_mfcr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_mfcr_offset), + scout => sov(ex1_is_mfcr_offset), + din => rf1_is_mfcr , + dout => ex1_is_mfcr_q); +ex1_is_mfspr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_mfspr_offset), + scout => sov(ex1_is_mfspr_offset), + din => rf1_is_mfspr , + dout => ex1_is_mfspr_q); +ex1_is_msgclr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_msgclr_offset), + scout => sov(ex1_is_msgclr_offset), + din => rf1_is_msgclr , + dout => ex1_is_msgclr_q); +ex1_is_msgsnd_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_msgsnd_offset), + scout => sov(ex1_is_msgsnd_offset), + din => rf1_is_msgsnd , + dout => ex1_is_msgsnd_q); +ex1_is_mtspr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_mtspr_offset), + scout => sov(ex1_is_mtspr_offset), + din => rf1_is_mtspr , + dout => ex1_is_mtspr_q); +ex1_is_sc_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_sc_offset), + scout => sov(ex1_is_sc_offset), + din => rf1_is_sc , + dout => ex1_is_sc_q); +ex1_is_st_w_update_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_st_w_update_offset), + scout => sov(ex1_is_st_w_update_offset), + din => rf1_is_st_w_update , + dout => ex1_is_st_w_update_q); +ex1_is_ucode_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_ucode_offset), + scout => sov(ex1_is_ucode_offset), + din => rf1_is_ucode_q , + dout => ex1_is_ucode_q); +ex1_is_wchkall_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_wchkall_offset), + scout => sov(ex1_is_wchkall_offset), + din => rf1_is_wchkall , + dout => ex1_is_wchkall_q); +ex1_lk_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_lk_offset), + scout => sov(ex1_lk_offset), + din => rf1_lk , + dout => ex1_lk_q); +ex1_match_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_match_offset), + scout => sov(ex1_match_offset), + din => rf1_match_q , + dout => ex1_match_q); +ex1_mfdcr_instr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_mfdcr_instr_offset), + scout => sov(ex1_mfdcr_instr_offset), + din => rf1_mfdcr_instr, + dout => ex1_mfdcr_instr_q); +ex1_mfdp_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_mfdp_val_offset), + scout => sov(ex1_mfdp_val_offset), + din => ex1_mfdp_val_d, + dout => ex1_mfdp_val_q); +ex1_mtdcr_instr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_mtdcr_instr_offset), + scout => sov(ex1_mtdcr_instr_offset), + din => rf1_mtdcr_instr, + dout => ex1_mtdcr_instr_q); +ex1_mtdp_nr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_mtdp_nr_offset), + scout => sov(ex1_mtdp_nr_offset), + din => ex1_mtdp_nr_d, + dout => ex1_mtdp_nr_q); +ex1_mtdp_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_mtdp_val_offset), + scout => sov(ex1_mtdp_val_offset), + din => ex1_mtdp_val_d, + dout => ex1_mtdp_val_q); +ex1_muldiv_coll_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_muldiv_coll_offset), + scout => sov(ex1_muldiv_coll_offset), + din => fxa_fxb_rf1_muldiv_coll , + dout => ex1_muldiv_coll_q); +ex1_need_hole_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_need_hole_offset), + scout => sov(ex1_need_hole_offset), + din => rf1_need_hole_q , + dout => ex1_need_hole_q); +ex1_num_regs_latch : tri_rlmreg_p + generic map (width => ex1_num_regs_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_num_regs_offset to ex1_num_regs_offset + ex1_num_regs_q'length-1), + scout => sov(ex1_num_regs_offset to ex1_num_regs_offset + ex1_num_regs_q'length-1), + din => ex1_num_regs_d, + dout => ex1_num_regs_q); +ex1_ovr_rotsel_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_ovr_rotsel_offset), + scout => sov(ex1_ovr_rotsel_offset), + din => ex1_ovr_rotsel_d, + dout => ex1_ovr_rotsel_q); +ex1_pred_taken_cnt_latch : tri_rlmreg_p + generic map (width => ex1_pred_taken_cnt_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_pred_taken_cnt_offset to ex1_pred_taken_cnt_offset + ex1_pred_taken_cnt_q'length-1), + scout => sov(ex1_pred_taken_cnt_offset to ex1_pred_taken_cnt_offset + ex1_pred_taken_cnt_q'length-1), + din => rf1_pred_taken_cnt_q , + dout => ex1_pred_taken_cnt_q); +ex1_pred_update_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_pred_update_offset), + scout => sov(ex1_pred_update_offset), + din => rf1_pred_update_q , + dout => ex1_pred_update_q); +ex1_pri_latch : tri_rlmreg_p + generic map (width => ex1_pri_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_pri_offset to ex1_pri_offset + ex1_pri_q'length-1), + scout => sov(ex1_pri_offset to ex1_pri_offset + ex1_pri_q'length-1), + din => rf1_pri , + dout => ex1_pri_q); +ex1_rotsel_ovrd_latch : tri_rlmreg_p + generic map (width => ex1_rotsel_ovrd_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_rotsel_ovrd_offset to ex1_rotsel_ovrd_offset + ex1_rotsel_ovrd_q'length-1), + scout => sov(ex1_rotsel_ovrd_offset to ex1_rotsel_ovrd_offset + ex1_rotsel_ovrd_q'length-1), + din => ex1_rotsel_ovrd_d, + dout => ex1_rotsel_ovrd_q); +ex1_s1_latch : tri_rlmreg_p + generic map (width => ex1_s1_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_s1_offset to ex1_s1_offset + ex1_s1_q'length-1), + scout => sov(ex1_s1_offset to ex1_s1_offset + ex1_s1_q'length-1), + din => rf1_s1_q , + dout => ex1_s1_q); +ex1_s2_latch : tri_rlmreg_p + generic map (width => ex1_s2_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_s2_offset to ex1_s2_offset + ex1_s2_q'length-1), + scout => sov(ex1_s2_offset to ex1_s2_offset + ex1_s2_q'length-1), + din => rf1_s2_q , + dout => ex1_s2_q); +ex1_s3_latch : tri_rlmreg_p + generic map (width => ex1_s3_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_s3_offset to ex1_s3_offset + ex1_s3_q'length-1), + scout => sov(ex1_s3_offset to ex1_s3_offset + ex1_s3_q'length-1), + din => rf1_s3_q , + dout => ex1_s3_q); +ex1_spr_sel_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_spr_sel_offset), + scout => sov(ex1_spr_sel_offset), + din => rf1_spr_sel , + dout => ex1_spr_sel_q); +ex1_ta_latch : tri_rlmreg_p + generic map (width => ex1_ta_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_ta_offset to ex1_ta_offset + ex1_ta_q'length-1), + scout => sov(ex1_ta_offset to ex1_ta_offset + ex1_ta_q'length-1), + din => rf1_ta_q , + dout => ex1_ta_q); +ex1_tid_latch : tri_rlmreg_p + generic map (width => ex1_tid_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_tid_offset to ex1_tid_offset + ex1_tid_q'length-1), + scout => sov(ex1_tid_offset to ex1_tid_offset + ex1_tid_q'length-1), + din => rf1_tid_q , + dout => ex1_tid_q); +ex1_tlb_data_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_tlb_data_val_offset), + scout => sov(ex1_tlb_data_val_offset), + din => ex1_tlb_data_val_d, + dout => ex1_tlb_data_val_q); +ex1_tlb_illeg_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_tlb_illeg_offset), + scout => sov(ex1_tlb_illeg_offset), + din => ex1_tlb_illeg_d, + dout => ex1_tlb_illeg_q); +ex1_trace_type_latch : tri_rlmreg_p + generic map (width => ex1_trace_type_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_trace_type_offset to ex1_trace_type_offset + ex1_trace_type_q'length-1), + scout => sov(ex1_trace_type_offset to ex1_trace_type_offset + ex1_trace_type_q'length-1), + din => rf1_trace_type, + dout => ex1_trace_type_q); +ex1_trace_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_trace_val_offset), + scout => sov(ex1_trace_val_offset), + din => rf1_trace_val, + dout => ex1_trace_val_q); +ex1_val_latch : tri_rlmreg_p + generic map (width => ex1_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_val_offset to ex1_val_offset + ex1_val_q'length-1), + scout => sov(ex1_val_offset to ex1_val_offset + ex1_val_q'length-1), + din => ex1_val_d, + dout => ex1_val_q); +ex1_axu_ld_or_st_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_axu_ld_or_st_offset), + scout => sov(ex1_axu_ld_or_st_offset), + din => rf1_axu_ld_or_st_q, + dout => ex1_axu_ld_or_st_q); +ex2_act_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_act_offset), + scout => sov(ex2_act_offset), + din => ex2_act_d, + dout => ex2_act_q); +ex2_axu_instr_type_latch : tri_regk + generic map (width => ex2_axu_instr_type_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex1_axu_instr_type_q , + dout => ex2_axu_instr_type_q); +ex2_back_inv_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_back_inv_offset), + scout => sov(ex2_back_inv_offset), + din => ex1_back_inv_q , + dout => ex2_back_inv_q); +ex2_bh_latch : tri_regk + generic map (width => ex2_bh_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex1_bh_q , + dout => ex2_bh_q); +ex2_clear_barrier_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_clear_barrier_offset), + scout => sov(ex2_clear_barrier_offset), + din => ex1_clear_barrier_q , + dout => ex2_clear_barrier_q); +ex2_ddmh_en_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_ddmh_en_q , + dout(0) => ex2_ddmh_en_q); +ex2_ditc_illeg_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_ditc_illeg_d, + dout(0) => ex2_ditc_illeg_q); +ex2_error_latch : tri_regk + generic map (width => ex2_error_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex1_error_q , + dout => ex2_error_q); +ex2_getNIA_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_getNIA_q , + dout(0) => ex2_getNIA_q); +ex2_gpr_we_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_gpr_we_offset), + scout => sov(ex2_gpr_we_offset), + din => ex2_gpr_we_d, + dout => ex2_gpr_we_q); +ex2_gshare_latch : tri_regk + generic map (width => ex2_gshare_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex1_gshare_q , + dout => ex2_gshare_q); +ex2_instr_latch : tri_regk + generic map (width => ex2_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex1_instr_q(12 to 25), + dout => ex2_instr_q); +ex2_instr_hypv_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_instr_hypv_q , + dout(0) => ex2_instr_hypv_q); +ex2_instr_priv_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_instr_priv_q , + dout(0) => ex2_instr_priv_q); +ex2_ipb_ba_latch : tri_rlmreg_p + generic map (width => ex2_ipb_ba_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_ipb_ba_offset to ex2_ipb_ba_offset + ex2_ipb_ba_q'length-1), + scout => sov(ex2_ipb_ba_offset to ex2_ipb_ba_offset + ex2_ipb_ba_q'length-1), + din => ex2_ipb_ba_d, + dout => ex2_ipb_ba_q); +ex2_ipb_sz_latch : tri_rlmreg_p + generic map (width => ex2_ipb_sz_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_ipb_sz_offset to ex2_ipb_sz_offset + ex2_ipb_sz_q'length-1), + scout => sov(ex2_ipb_sz_offset to ex2_ipb_sz_offset + ex2_ipb_sz_q'length-1), + din => ex2_ipb_sz_d, + dout => ex2_ipb_sz_q); +ex2_is_any_load_dac_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_any_load_dac_q , + dout(0) => ex2_is_any_load_dac_q); +ex2_is_any_store_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_any_store_q , + dout(0) => ex2_is_any_store_q); +ex2_is_any_store_dac_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_any_store_dac_q , + dout(0) => ex2_is_any_store_dac_q); +ex2_is_attn_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_attn_q , + dout(0) => ex2_is_attn_q); +ex2_is_bclr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_bclr_q , + dout(0) => ex2_is_bclr_q); +ex2_is_eratsxr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_eratsxr_q , + dout(0) => ex2_is_eratsxr_q); +ex2_is_icswx_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_icswx_q , + dout(0) => ex2_is_icswx_q); +ex2_is_ld_w_update_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_ld_w_update_q , + dout(0) => ex2_is_ld_w_update_q); +ex2_is_lmw_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_lmw_q , + dout(0) => ex2_is_lmw_q); +ex2_is_lswi_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_lswi_q , + dout(0) => ex2_is_lswi_q); +ex2_is_lswx_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_lswx_q , + dout(0) => ex2_is_lswx_q); +ex2_is_mfcr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_mfcr_q , + dout(0) => ex2_is_mfcr_q); +ex2_is_msgclr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_msgclr_q , + dout(0) => ex2_is_msgclr_q); +ex2_is_msgsnd_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_msgsnd_q , + dout(0) => ex2_is_msgsnd_q); +ex2_is_sc_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_sc_q , + dout(0) => ex2_is_sc_q); +ex2_is_st_w_update_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_st_w_update_q , + dout(0) => ex2_is_st_w_update_q); +ex2_is_ucode_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_is_ucode_offset), + scout => sov(ex2_is_ucode_offset), + din => ex1_is_ucode_q , + dout => ex2_is_ucode_q); +ex2_is_wchkall_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_wchkall_q , + dout(0) => ex2_is_wchkall_q); +ex2_lk_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_lk_q , + dout(0) => ex2_lk_q); +ex2_match_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_match_q , + dout(0) => ex2_match_q); +ex2_mfdp_val_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_mfdp_val_q , + dout(0) => ex2_mfdp_val_q); +ex2_mtdp_nr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_mtdp_nr_q , + dout(0) => ex2_mtdp_nr_q); +ex2_mtdp_val_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_mtdp_val_q , + dout(0) => ex2_mtdp_val_q); +ex2_muldiv_coll_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_muldiv_coll_offset), + scout => sov(ex2_muldiv_coll_offset), + din => ex1_muldiv_coll_q , + dout => ex2_muldiv_coll_q); +ex2_need_hole_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_need_hole_offset), + scout => sov(ex2_need_hole_offset), + din => ex1_need_hole_q , + dout => ex2_need_hole_q); +ex2_pred_taken_cnt_latch : tri_regk + generic map (width => ex2_pred_taken_cnt_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex1_pred_taken_cnt_q , + dout => ex2_pred_taken_cnt_q); +ex2_pred_update_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_pred_update_q , + dout(0) => ex2_pred_update_q); +ex2_pri_latch : tri_regk + generic map (width => ex2_pri_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex1_pri_q , + dout => ex2_pri_q); +ex2_ra_eq_rt_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_ra_eq_rt_d, + dout(0) => ex2_ra_eq_rt_q); +ex2_ra_eq_zero_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_ra_eq_zero_d, + dout(0) => ex2_ra_eq_zero_q); +ex2_ra_in_rng_lmw_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_ra_in_rng_lmw_d, + dout(0) => ex2_ra_in_rng_lmw_q); +ex2_ra_in_rng_nowrap_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_ra_in_rng_nowrap_d, + dout(0) => ex2_ra_in_rng_nowrap_q); +ex2_ra_in_rng_wrap_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_ra_in_rng_wrap_d, + dout(0) => ex2_ra_in_rng_wrap_q); +ex2_range_wrap_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_range_wrap_d, + dout(0) => ex2_range_wrap_q); +ex2_rb_eq_rt_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_rb_eq_rt_d, + dout(0) => ex2_rb_eq_rt_q); +ex2_rb_in_rng_nowrap_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_rb_in_rng_nowrap_d, + dout(0) => ex2_rb_in_rng_nowrap_q); +ex2_rb_in_rng_wrap_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_rb_in_rng_wrap_d, + dout(0) => ex2_rb_in_rng_wrap_q); +ex2_slowspr_dcr_rd_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_slowspr_dcr_rd, + dout(0) => ex2_slowspr_dcr_rd_q); +ex2_ta_latch : tri_regk + generic map (width => ex2_ta_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex1_ta_q , + dout => ex2_ta_q); +ex2_tid_latch : tri_regk + generic map (width => ex2_tid_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex1_tid_q , + dout => ex2_tid_q); +ex2_tlb_data_val_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_tlb_data_val_q , + dout(0) => ex2_tlb_data_val_q); +ex2_tlb_illeg_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex1_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_tlb_illeg_q , + dout(0) => ex2_tlb_illeg_q); +ex2_trace_type_latch : tri_regk + generic map (width => ex2_trace_type_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex1_trace_type_q , + dout => ex2_trace_type_q); +ex2_trace_val_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_trace_val_q , + dout(0) => ex2_trace_val_q); +ex2_val_latch : tri_rlmreg_p + generic map (width => ex2_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_val_offset to ex2_val_offset + ex2_val_q'length-1), + scout => sov(ex2_val_offset to ex2_val_offset + ex2_val_q'length-1), + din => ex2_val_d, + dout => ex2_val_q); +ex3_act_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_act_offset), + scout => sov(ex3_act_offset), + din => ex3_act_d, + dout => ex3_act_q); +ex3_axu_instr_type_latch : tri_rlmreg_p + generic map (width => ex3_axu_instr_type_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_axu_instr_type_offset to ex3_axu_instr_type_offset + ex3_axu_instr_type_q'length-1), + scout => sov(ex3_axu_instr_type_offset to ex3_axu_instr_type_offset + ex3_axu_instr_type_q'length-1), + din => ex2_axu_instr_type_q , + dout => ex3_axu_instr_type_q); +ex3_back_inv_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_back_inv_offset), + scout => sov(ex3_back_inv_offset), + din => ex2_back_inv_q , + dout => ex3_back_inv_q); +ex3_bh_latch : tri_rlmreg_p + generic map (width => ex3_bh_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_bh_offset to ex3_bh_offset + ex3_bh_q'length-1), + scout => sov(ex3_bh_offset to ex3_bh_offset + ex3_bh_q'length-1), + din => ex2_bh_q , + dout => ex3_bh_q); +ex3_clear_barrier_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_clear_barrier_offset), + scout => sov(ex3_clear_barrier_offset), + din => ex2_clear_barrier_q , + dout => ex3_clear_barrier_q); +ex3_ddmh_en_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_ddmh_en_offset), + scout => sov(ex3_ddmh_en_offset), + din => ex2_ddmh_en_q , + dout => ex3_ddmh_en_q); +ex3_div_done_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_div_done_offset), + scout => sov(ex3_div_done_offset), + din => alu_ex2_div_done , + dout => ex3_div_done_q); +ex3_getNIA_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_getNIA_offset), + scout => sov(ex3_getNIA_offset), + din => ex2_getNIA_q , + dout => ex3_getNIA_q); +ex3_gpr_we_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_gpr_we_offset), + scout => sov(ex3_gpr_we_offset), + din => ex2_gpr_we_q , + dout => ex3_gpr_we_q); +ex3_gshare_latch : tri_rlmreg_p + generic map (width => ex3_gshare_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_gshare_offset to ex3_gshare_offset + ex3_gshare_q'length-1), + scout => sov(ex3_gshare_offset to ex3_gshare_offset + ex3_gshare_q'length-1), + din => ex2_gshare_q , + dout => ex3_gshare_q); +ex3_instr_latch : tri_rlmreg_p + generic map (width => ex3_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_instr_offset to ex3_instr_offset + ex3_instr_q'length-1), + scout => sov(ex3_instr_offset to ex3_instr_offset + ex3_instr_q'length-1), + din => ex2_instr_q(12 to 19), + dout => ex3_instr_q); +ex3_instr_hypv_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_instr_hypv_offset), + scout => sov(ex3_instr_hypv_offset), + din => ex2_instr_hypv_q , + dout => ex3_instr_hypv_q); +ex3_instr_priv_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_instr_priv_offset), + scout => sov(ex3_instr_priv_offset), + din => ex2_instr_priv_q , + dout => ex3_instr_priv_q); +ex3_is_any_store_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_any_store_offset), + scout => sov(ex3_is_any_store_offset), + din => ex2_is_any_store_q , + dout => ex3_is_any_store_q); +ex3_is_bclr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_bclr_offset), + scout => sov(ex3_is_bclr_offset), + din => ex2_is_bclr_q , + dout => ex3_is_bclr_q); +ex3_is_eratsxr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_eratsxr_offset), + scout => sov(ex3_is_eratsxr_offset), + din => ex2_is_eratsxr_q , + dout => ex3_is_eratsxr_q); +ex3_is_mfcr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_mfcr_offset), + scout => sov(ex3_is_mfcr_offset), + din => ex2_is_mfcr_q , + dout => ex3_is_mfcr_q); +ex3_is_wchkall_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_wchkall_offset), + scout => sov(ex3_is_wchkall_offset), + din => ex2_is_wchkall_q , + dout => ex3_is_wchkall_q); +ex3_lk_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_lk_offset), + scout => sov(ex3_lk_offset), + din => ex2_lk_q , + dout => ex3_lk_q); +ex3_mfdp_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_mfdp_val_offset), + scout => sov(ex3_mfdp_val_offset), + din => ex2_mfdp_val_q , + dout => ex3_mfdp_val_q); +ex3_mtdp_nr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_mtdp_nr_offset), + scout => sov(ex3_mtdp_nr_offset), + din => ex2_mtdp_nr_q , + dout => ex3_mtdp_nr_q); +ex3_mtdp_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_mtdp_val_offset), + scout => sov(ex3_mtdp_val_offset), + din => ex2_mtdp_val_q , + dout => ex3_mtdp_val_q); +ex3_muldiv_coll_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_muldiv_coll_offset), + scout => sov(ex3_muldiv_coll_offset), + din => ex2_muldiv_coll_q , + dout => ex3_muldiv_coll_q); +ex3_need_hole_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_need_hole_offset), + scout => sov(ex3_need_hole_offset), + din => ex2_need_hole_q , + dout => ex3_need_hole_q); +ex3_pred_taken_cnt_latch : tri_rlmreg_p + generic map (width => ex3_pred_taken_cnt_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_pred_taken_cnt_offset to ex3_pred_taken_cnt_offset + ex3_pred_taken_cnt_q'length-1), + scout => sov(ex3_pred_taken_cnt_offset to ex3_pred_taken_cnt_offset + ex3_pred_taken_cnt_q'length-1), + din => ex2_pred_taken_cnt_q , + dout => ex3_pred_taken_cnt_q); +ex3_pred_update_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_pred_update_offset), + scout => sov(ex3_pred_update_offset), + din => ex2_pred_update_q , + dout => ex3_pred_update_q); +ex3_pri_latch : tri_rlmreg_p + generic map (width => ex3_pri_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_pri_offset to ex3_pri_offset + ex3_pri_q'length-1), + scout => sov(ex3_pri_offset to ex3_pri_offset + ex3_pri_q'length-1), + din => ex2_pri_q , + dout => ex3_pri_q); +ex3_slowspr_dcr_rd_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_slowspr_dcr_rd_offset), + scout => sov(ex3_slowspr_dcr_rd_offset), + din => ex2_slowspr_dcr_rd_q , + dout => ex3_slowspr_dcr_rd_q); +ex3_ta_latch : tri_rlmreg_p + generic map (width => ex3_ta_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_ta_offset to ex3_ta_offset + ex3_ta_q'length-1), + scout => sov(ex3_ta_offset to ex3_ta_offset + ex3_ta_q'length-1), + din => ex2_ta_q , + dout => ex3_ta_q); +ex3_tid_latch : tri_rlmreg_p + generic map (width => ex3_tid_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_tid_offset to ex3_tid_offset + ex3_tid_q'length-1), + scout => sov(ex3_tid_offset to ex3_tid_offset + ex3_tid_q'length-1), + din => ex2_tid_q , + dout => ex3_tid_q); +ex3_tlb_data_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_tlb_data_val_offset), + scout => sov(ex3_tlb_data_val_offset), + din => ex2_tlb_data_val_q , + dout => ex3_tlb_data_val_q); +ex3_tlb_illeg_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex2_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_tlb_illeg_offset), + scout => sov(ex3_tlb_illeg_offset), + din => ex2_tlb_illeg_q , + dout => ex3_tlb_illeg_q); +ex3_trace_type_latch : tri_rlmreg_p + generic map (width => ex3_trace_type_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_trace_type_offset to ex3_trace_type_offset + ex3_trace_type_q'length-1), + scout => sov(ex3_trace_type_offset to ex3_trace_type_offset + ex3_trace_type_q'length-1), + din => ex2_trace_type_q, + dout => ex3_trace_type_q); +ex3_trace_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_trace_val_offset), + scout => sov(ex3_trace_val_offset), + din => ex2_trace_val_q , + dout => ex3_trace_val_q); +ex3_val_latch : tri_rlmreg_p + generic map (width => ex3_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_val_offset to ex3_val_offset + ex3_val_q'length-1), + scout => sov(ex3_val_offset to ex3_val_offset + ex3_val_q'length-1), + din => ex3_val_d, + dout => ex3_val_q); +ex4_act_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_act_offset), + scout => sov(ex4_act_offset), + din => ex4_act_d, + dout => ex4_act_q); +ex4_bh_latch : tri_regk + generic map (width => ex4_bh_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex3_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex3_bh_q , + dout => ex4_bh_q); +ex4_clear_barrier_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_clear_barrier_offset), + scout => sov(ex4_clear_barrier_offset), + din => ex3_clear_barrier_q , + dout => ex4_clear_barrier_q); +ex4_dp_instr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex3_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex4_dp_instr_d, + dout(0) => ex4_dp_instr_q); +ex4_getNIA_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex3_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_getNIA_q , + dout(0) => ex4_getNIA_q); +ex4_gpr_we_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_gpr_we_offset), + scout => sov(ex4_gpr_we_offset), + din => ex4_gpr_we_d, + dout => ex4_gpr_we_q); +ex4_gshare_latch : tri_regk + generic map (width => ex4_gshare_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex3_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex3_gshare_q , + dout => ex4_gshare_q); +ex4_instr_latch : tri_regk + generic map (width => ex4_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex3_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex3_instr_q , + dout => ex4_instr_q); +ex4_is_bclr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex3_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_is_bclr_q , + dout(0) => ex4_is_bclr_q); +ex4_is_eratsxr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex3_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_is_eratsxr_q , + dout(0) => ex4_is_eratsxr_q); +ex4_is_mfcr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex3_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_is_mfcr_q , + dout(0) => ex4_is_mfcr_q); +ex4_is_wchkall_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex3_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_is_wchkall_q , + dout(0) => ex4_is_wchkall_q); +ex4_lk_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex3_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_lk_q , + dout(0) => ex4_lk_q); +ex4_mfdp_val_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex3_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_mfdp_val_q , + dout(0) => ex4_mfdp_val_q); +ex4_mtdp_val_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex3_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_mtdp_val_q , + dout(0) => ex4_mtdp_val_q); +ex4_pred_taken_cnt_latch : tri_regk + generic map (width => ex4_pred_taken_cnt_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex3_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex3_pred_taken_cnt_q , + dout => ex4_pred_taken_cnt_q); +ex4_pred_update_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex3_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_pred_update_q , + dout(0) => ex4_pred_update_q); +ex4_pri_latch : tri_regk + generic map (width => ex4_pri_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex3_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex3_pri_q , + dout => ex4_pri_q); +ex4_slowspr_dcr_rd_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex3_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_slowspr_dcr_rd_q , + dout(0) => ex4_slowspr_dcr_rd_q); +ex4_ta_latch : tri_regk + generic map (width => ex4_ta_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex3_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex3_ta_q , + dout => ex4_ta_q); +ex4_tid_latch : tri_regk + generic map (width => ex4_tid_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex3_act_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex3_tid_q , + dout => ex4_tid_q); +ex4_val_latch : tri_rlmreg_p + generic map (width => ex4_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_val_offset to ex4_val_offset + ex4_val_q'length-1), + scout => sov(ex4_val_offset to ex4_val_offset + ex4_val_q'length-1), + din => ex4_val_d, + dout => ex4_val_q); +ex5_act_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_act_offset), + scout => sov(ex5_act_offset), + din => ex5_act_d, + dout => ex5_act_q); +ex5_bh_latch : tri_rlmreg_p + generic map (width => ex5_bh_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_bh_offset to ex5_bh_offset + ex5_bh_q'length-1), + scout => sov(ex5_bh_offset to ex5_bh_offset + ex5_bh_q'length-1), + din => ex4_bh_q , + dout => ex5_bh_q); +ex5_clear_barrier_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_clear_barrier_offset), + scout => sov(ex5_clear_barrier_offset), + din => ex4_clear_barrier_q , + dout => ex5_clear_barrier_q); +ex5_getNIA_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_getNIA_offset), + scout => sov(ex5_getNIA_offset), + din => ex4_getNIA_q , + dout => ex5_getNIA_q); +ex5_gpr_we_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_gpr_we_offset), + scout => sov(ex5_gpr_we_offset), + din => ex5_gpr_we_d, + dout => ex5_gpr_we_q); +ex5_gshare_latch : tri_rlmreg_p + generic map (width => ex5_gshare_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_gshare_offset to ex5_gshare_offset + ex5_gshare_q'length-1), + scout => sov(ex5_gshare_offset to ex5_gshare_offset + ex5_gshare_q'length-1), + din => ex4_gshare_q , + dout => ex5_gshare_q); +ex5_instr_latch : tri_rlmreg_p + generic map (width => ex5_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_instr_offset to ex5_instr_offset + ex5_instr_q'length-1), + scout => sov(ex5_instr_offset to ex5_instr_offset + ex5_instr_q'length-1), + din => ex4_instr_q , + dout => ex5_instr_q); +ex5_is_bclr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_is_bclr_offset), + scout => sov(ex5_is_bclr_offset), + din => ex4_is_bclr_q , + dout => ex5_is_bclr_q); +ex5_lk_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_lk_offset), + scout => sov(ex5_lk_offset), + din => ex4_lk_q , + dout => ex5_lk_q); +ex5_pred_taken_cnt_latch : tri_rlmreg_p + generic map (width => ex5_pred_taken_cnt_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_pred_taken_cnt_offset to ex5_pred_taken_cnt_offset + ex5_pred_taken_cnt_q'length-1), + scout => sov(ex5_pred_taken_cnt_offset to ex5_pred_taken_cnt_offset + ex5_pred_taken_cnt_q'length-1), + din => ex4_pred_taken_cnt_q , + dout => ex5_pred_taken_cnt_q); +ex5_pred_update_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_pred_update_offset), + scout => sov(ex5_pred_update_offset), + din => ex4_pred_update_q , + dout => ex5_pred_update_q); +ex5_pri_latch : tri_rlmreg_p + generic map (width => ex5_pri_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_pri_offset to ex5_pri_offset + ex5_pri_q'length-1), + scout => sov(ex5_pri_offset to ex5_pri_offset + ex5_pri_q'length-1), + din => ex4_pri_q , + dout => ex5_pri_q); +ex5_slowspr_dcr_rd_latch : tri_rlmreg_p + generic map (width => ex5_slowspr_dcr_rd_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_slowspr_dcr_rd_offset to ex5_slowspr_dcr_rd_offset + ex5_slowspr_dcr_rd_q'length-1), + scout => sov(ex5_slowspr_dcr_rd_offset to ex5_slowspr_dcr_rd_offset + ex5_slowspr_dcr_rd_q'length-1), + din => ex5_slowspr_dcr_rd_d, + dout => ex5_slowspr_dcr_rd_q); +ex5_ta_latch : tri_rlmreg_p + generic map (width => ex5_ta_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_ta_offset to ex5_ta_offset + ex5_ta_q'length-1), + scout => sov(ex5_ta_offset to ex5_ta_offset + ex5_ta_q'length-1), + din => ex4_ta_q , + dout => ex5_ta_q); +ex5_tid_latch : tri_rlmreg_p + generic map (width => ex5_tid_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex4_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_tid_offset to ex5_tid_offset + ex5_tid_q'length-1), + scout => sov(ex5_tid_offset to ex5_tid_offset + ex5_tid_q'length-1), + din => ex4_tid_q , + dout => ex5_tid_q); +ex5_val_latch : tri_rlmreg_p + generic map (width => ex5_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_val_offset to ex5_val_offset + ex5_val_q'length-1), + scout => sov(ex5_val_offset to ex5_val_offset + ex5_val_q'length-1), + din => ex5_val_d, + dout => ex5_val_q); +ex6_clear_barrier_latch : tri_rlmreg_p + generic map (width => ex6_clear_barrier_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_clear_barrier_offset to ex6_clear_barrier_offset + ex6_clear_barrier_q'length-1), + scout => sov(ex6_clear_barrier_offset to ex6_clear_barrier_offset + ex6_clear_barrier_q'length-1), + din => ex6_clear_barrier_d, + dout => ex6_clear_barrier_q); +ex6_gpr_we_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_gpr_we_offset), + scout => sov(ex6_gpr_we_offset), + din => ex6_gpr_we_d, + dout => ex6_gpr_we_q); +ex6_pri_latch : tri_rlmreg_p + generic map (width => ex6_pri_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex5_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_pri_offset to ex6_pri_offset + ex6_pri_q'length-1), + scout => sov(ex6_pri_offset to ex6_pri_offset + ex6_pri_q'length-1), + din => ex5_pri_q , + dout => ex6_pri_q); +ex6_ta_latch : tri_rlmreg_p + generic map (width => ex6_ta_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_ta_offset to ex6_ta_offset + ex6_ta_q'length-1), + scout => sov(ex6_ta_offset to ex6_ta_offset + ex6_ta_q'length-1), + din => ex6_ta_d, + dout => ex6_ta_q); +ex6_val_latch : tri_rlmreg_p + generic map (width => ex6_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_val_offset to ex6_val_offset + ex6_val_q'length-1), + scout => sov(ex6_val_offset to ex6_val_offset + ex6_val_q'length-1), + din => ex6_val_d, + dout => ex6_val_q); +ex7_gpr_we_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex7_gpr_we_offset), + scout => sov(ex7_gpr_we_offset), + din => ex6_gpr_we_q , + dout => ex7_gpr_we_q); +ex7_ta_latch : tri_rlmreg_p + generic map (width => ex7_ta_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex7_ta_offset to ex7_ta_offset + ex7_ta_q'length-1), + scout => sov(ex7_ta_offset to ex7_ta_offset + ex7_ta_q'length-1), + din => ex6_ta_q , + dout => ex7_ta_q); +ex7_val_latch : tri_rlmreg_p + generic map (width => ex7_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex7_val_offset to ex7_val_offset + ex7_val_q'length-1), + scout => sov(ex7_val_offset to ex7_val_offset + ex7_val_q'length-1), + din => ex6_val_q , + dout => ex7_val_q); +an_ac_dcr_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(an_ac_dcr_val_offset), + scout => sov(an_ac_dcr_val_offset), + din => an_ac_dcr_val , + dout => an_ac_dcr_val_q); +dcr_ack_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dcr_ack_offset), + scout => sov(dcr_ack_offset), + din => dcr_ack, + dout => dcr_ack_q); +dcr_act_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dcr_act_offset), + scout => sov(dcr_act_offset), + din => an_ac_dcr_act , + dout => dcr_act_q); +dcr_etid_latch : tri_rlmreg_p + generic map (width => dcr_etid_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => dcr_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dcr_etid_offset to dcr_etid_offset + dcr_etid_q'length-1), + scout => sov(dcr_etid_offset to dcr_etid_offset + dcr_etid_q'length-1), + din => an_ac_dcr_etid , + dout => dcr_etid_q); +dcr_read_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => dcr_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dcr_read_offset), + scout => sov(dcr_read_offset), + din => an_ac_dcr_read , + dout => dcr_read_q); +dcr_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dcr_val_offset), + scout => sov(dcr_val_offset), + din => dcr_val_d, + dout => dcr_val_q); +instr_trace_mode_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(instr_trace_mode_offset), + scout => sov(instr_trace_mode_offset), + din => pc_xu_instr_trace_mode , + dout => instr_trace_mode_q); +instr_trace_tid_latch : tri_rlmreg_p + generic map (width => instr_trace_tid_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(instr_trace_tid_offset to instr_trace_tid_offset + instr_trace_tid_q'length-1), + scout => sov(instr_trace_tid_offset to instr_trace_tid_offset + instr_trace_tid_q'length-1), + din => pc_xu_instr_trace_tid , + dout => instr_trace_tid_q); +lsu_xu_need_hole_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(lsu_xu_need_hole_offset), + scout => sov(lsu_xu_need_hole_offset), + din => lsu_xu_need_hole_d, + dout => lsu_xu_need_hole_q); +lsu_xu_rel_ta_gpr_latch : tri_rlmreg_p + generic map (width => lsu_xu_rel_ta_gpr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(lsu_xu_rel_ta_gpr_offset to lsu_xu_rel_ta_gpr_offset + lsu_xu_rel_ta_gpr_q'length-1), + scout => sov(lsu_xu_rel_ta_gpr_offset to lsu_xu_rel_ta_gpr_offset + lsu_xu_rel_ta_gpr_q'length-1), + din => lsu_xu_rel_ta_gpr , + dout => lsu_xu_rel_ta_gpr_q); +lsu_xu_rel_wren_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(lsu_xu_rel_wren_offset), + scout => sov(lsu_xu_rel_wren_offset), + din => lsu_xu_rel_wren , + dout => lsu_xu_rel_wren_q); +mmucr0_0_tlbsel_latch : tri_rlmreg_p + generic map (width => mmucr0_0_tlbsel_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(mmucr0_0_tlbsel_offset to mmucr0_0_tlbsel_offset + mmucr0_0_tlbsel_q'length-1), + scout => sov(mmucr0_0_tlbsel_offset to mmucr0_0_tlbsel_offset + mmucr0_0_tlbsel_q'length-1), + din => mm_xu_mmucr0_0_tlbsel , + dout => mmucr0_0_tlbsel_q); +mmucr0_1_tlbsel_latch : tri_rlmreg_p + generic map (width => mmucr0_1_tlbsel_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(mmucr0_1_tlbsel_offset to mmucr0_1_tlbsel_offset + mmucr0_1_tlbsel_q'length-1), + scout => sov(mmucr0_1_tlbsel_offset to mmucr0_1_tlbsel_offset + mmucr0_1_tlbsel_q'length-1), + din => mm_xu_mmucr0_1_tlbsel , + dout => mmucr0_1_tlbsel_q); +mmucr0_2_tlbsel_latch : tri_rlmreg_p + generic map (width => mmucr0_2_tlbsel_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(mmucr0_2_tlbsel_offset to mmucr0_2_tlbsel_offset + mmucr0_2_tlbsel_q'length-1), + scout => sov(mmucr0_2_tlbsel_offset to mmucr0_2_tlbsel_offset + mmucr0_2_tlbsel_q'length-1), + din => mm_xu_mmucr0_2_tlbsel , + dout => mmucr0_2_tlbsel_q); +mmucr0_3_tlbsel_latch : tri_rlmreg_p + generic map (width => mmucr0_3_tlbsel_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(mmucr0_3_tlbsel_offset to mmucr0_3_tlbsel_offset + mmucr0_3_tlbsel_q'length-1), + scout => sov(mmucr0_3_tlbsel_offset to mmucr0_3_tlbsel_offset + mmucr0_3_tlbsel_q'length-1), + din => mm_xu_mmucr0_3_tlbsel , + dout => mmucr0_3_tlbsel_q); +slowspr_etid_latch : tri_rlmreg_p + generic map (width => slowspr_etid_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => slowspr_val_in , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(slowspr_etid_offset to slowspr_etid_offset + slowspr_etid_q'length-1), + scout => sov(slowspr_etid_offset to slowspr_etid_offset + slowspr_etid_q'length-1), + din => slowspr_etid_in , + dout => slowspr_etid_q); +slowspr_rw_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => slowspr_val_in , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(slowspr_rw_offset), + scout => sov(slowspr_rw_offset), + din => slowspr_rw_in , + dout => slowspr_rw_q); +slowspr_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(slowspr_val_offset), + scout => sov(slowspr_val_offset), + din => slowspr_val_in , + dout => slowspr_val_q); +spr_ccr2_en_attn_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(spr_ccr2_en_attn_offset), + scout => sov(spr_ccr2_en_attn_offset), + din => spr_ccr2_en_attn , + dout => spr_ccr2_en_attn_q); +spr_ccr2_en_dcr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(spr_ccr2_en_dcr_offset), + scout => sov(spr_ccr2_en_dcr_offset), + din => spr_ccr2_en_dcr , + dout => spr_ccr2_en_dcr_q); +spr_ccr2_en_ditc_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(spr_ccr2_en_ditc_offset), + scout => sov(spr_ccr2_en_ditc_offset), + din => spr_ccr2_en_ditc , + dout => spr_ccr2_en_ditc_q); +spr_ccr2_en_icswx_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(spr_ccr2_en_icswx_offset), + scout => sov(spr_ccr2_en_icswx_offset), + din => spr_ccr2_en_icswx , + dout => spr_ccr2_en_icswx_q); +spr_ccr2_en_pc_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(spr_ccr2_en_pc_offset), + scout => sov(spr_ccr2_en_pc_offset), + din => spr_ccr2_en_pc , + dout => spr_ccr2_en_pc_q); +spr_ccr2_notlb_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(spr_ccr2_notlb_offset), + scout => sov(spr_ccr2_notlb_offset), + din => spr_ccr2_notlb , + dout => spr_ccr2_notlb_q); +spr_msr_cm_latch : tri_rlmreg_p + generic map (width => spr_msr_cm_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(spr_msr_cm_offset to spr_msr_cm_offset + spr_msr_cm_q'length-1), + scout => sov(spr_msr_cm_offset to spr_msr_cm_offset + spr_msr_cm_q'length-1), + din => spr_msr_cm , + dout => spr_msr_cm_q); +t0_hold_ta_latch : tri_rlmreg_p + generic map (width => t0_hold_ta_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex5_slowspr_dcr_rd_q(0), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(t0_hold_ta_offset to t0_hold_ta_offset + t0_hold_ta_q'length-1), + scout => sov(t0_hold_ta_offset to t0_hold_ta_offset + t0_hold_ta_q'length-1), + din => ex5_ta_q(0 to 5) , + dout => t0_hold_ta_q); +t1_hold_ta_latch : tri_rlmreg_p + generic map (width => t1_hold_ta_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex5_slowspr_dcr_rd_q(1), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(t1_hold_ta_offset to t1_hold_ta_offset + t1_hold_ta_q'length-1), + scout => sov(t1_hold_ta_offset to t1_hold_ta_offset + t1_hold_ta_q'length-1), + din => ex5_ta_q(0 to 5) , + dout => t1_hold_ta_q); +t2_hold_ta_latch : tri_rlmreg_p + generic map (width => t2_hold_ta_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex5_slowspr_dcr_rd_q(2), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(t2_hold_ta_offset to t2_hold_ta_offset + t2_hold_ta_q'length-1), + scout => sov(t2_hold_ta_offset to t2_hold_ta_offset + t2_hold_ta_q'length-1), + din => ex5_ta_q(0 to 5) , + dout => t2_hold_ta_q); +t3_hold_ta_latch : tri_rlmreg_p + generic map (width => t3_hold_ta_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex5_slowspr_dcr_rd_q(3), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(t3_hold_ta_offset to t3_hold_ta_offset + t3_hold_ta_q'length-1), + scout => sov(t3_hold_ta_offset to t3_hold_ta_offset + t3_hold_ta_q'length-1), + din => ex5_ta_q(0 to 5) , + dout => t3_hold_ta_q); +trace_bus_enable_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(trace_bus_enable_offset), + scout => sov(trace_bus_enable_offset), + din => pc_xu_trace_bus_enable , + dout => trace_bus_enable_q); +clkg_ctl_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(clkg_ctl_offset), + scout => sov(clkg_ctl_offset), + din => spr_xucr0_clkg_ctl(2), + dout => clkg_ctl_q); +spr_bit_act_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(spr_bit_act_offset), + scout => sov(spr_bit_act_offset), + din => spr_bit_act, + dout => spr_bit_act_q); +spare_0_lcb: entity tri.tri_lcbnd(tri_lcbnd) + port map(vd => vdd, + gd => gnd, + act => tidn, + nclk => nclk, + forcee => func_sl_force, + thold_b => func_sl_thold_0_b, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + sg => sg_0, + lclk => spare_0_lclk, + d1clk => spare_0_d1clk, + d2clk => spare_0_d2clk); +spare_0_latch : entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width => spare_0_q'length, expand_type => expand_type, btr => "NLI0001_X2_A12TH", init=>(spare_0_q'range=>'0')) + port map (vd => vdd, gd => gnd, + LCLK => spare_0_lclk, + D1CLK => spare_0_d1clk, + D2CLK => spare_0_d2clk, + SCANIN => siv(spare_0_offset to spare_0_offset + spare_0_q'length-1), + SCANOUT => sov(spare_0_offset to spare_0_offset + spare_0_q'length-1), + D => spare_0_d, + QB => spare_0_q); +spare_0_d <= not spare_0_q; +mark_unused(spare_0_q); +spare_1_lcb: entity tri.tri_lcbnd(tri_lcbnd) + port map(vd => vdd, + gd => gnd, + act => tidn, + nclk => nclk, + forcee => func_sl_force, + thold_b => func_sl_thold_0_b, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + sg => sg_0, + lclk => spare_1_lclk, + d1clk => spare_1_d1clk, + d2clk => spare_1_d2clk); +spare_1_latch : entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width => spare_1_q'length, expand_type => expand_type, btr => "NLI0001_X2_A12TH", init=>(spare_1_q'range=>'0')) + port map (vd => vdd, gd => gnd, + LCLK => spare_1_lclk, + D1CLK => spare_1_d1clk, + D2CLK => spare_1_d2clk, + SCANIN => siv(spare_1_offset to spare_1_offset + spare_1_q'length-1), + SCANOUT => sov(spare_1_offset to spare_1_offset + spare_1_q'length-1), + D => spare_1_d, + QB => spare_1_q); +spare_1_d <= not spare_1_q; +mark_unused(spare_1_q); +siv(0 TO siv'right) <= sov(1 to siv'right) & scan_in; +scan_out <= sov(0); +END XUQ_DEC_B; diff --git a/rel/src/vhdl/work/xuq_dec_dcdmrg.vhdl b/rel/src/vhdl/work/xuq_dec_dcdmrg.vhdl new file mode 100644 index 0000000..bd3abb3 --- /dev/null +++ b/rel/src/vhdl/work/xuq_dec_dcdmrg.vhdl @@ -0,0 +1,492 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +LIBRARY work ; +LIBRARY ieee; USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY ibm; + USE ibm.std_ulogic_support.all; + USE ibm.std_ulogic_unsigned.all; + USE ibm.std_ulogic_function_support.all; +LIBRARY support; + USE support.power_logic_pkg.all; +LIBRARY tri; USE tri.tri_latches_pkg.all; +LIBRARY work; USE work.xuq_pkg.all; + +entity xuq_dec_dcdmrg is + port ( + i : in std_ulogic_vector(0 to 31); + dec_alu_rf1_sel_rot_log : out std_ulogic; + dec_alu_rf1_sh_right : out std_ulogic; + dec_alu_rf1_sh_word : out std_ulogic; + dec_alu_rf1_sgnxtd_byte : out std_ulogic; + dec_alu_rf1_sgnxtd_half : out std_ulogic; + dec_alu_rf1_sgnxtd_wd : out std_ulogic; + dec_alu_rf1_sra_dw : out std_ulogic; + dec_alu_rf1_sra_wd : out std_ulogic; + dec_alu_rf1_chk_shov_dw : out std_ulogic; + dec_alu_rf1_chk_shov_wd : out std_ulogic; + + dec_alu_rf1_use_me_ins_hi : out std_ulogic; + dec_alu_rf1_use_me_ins_lo : out std_ulogic; + dec_alu_rf1_use_mb_ins_hi : out std_ulogic; + dec_alu_rf1_use_mb_ins_lo : out std_ulogic; + + dec_alu_rf1_use_me_rb_hi : out std_ulogic; + dec_alu_rf1_use_me_rb_lo : out std_ulogic; + dec_alu_rf1_use_mb_rb_hi : out std_ulogic; + dec_alu_rf1_use_mb_rb_lo : out std_ulogic; + + dec_alu_rf1_use_rb_amt_hi : out std_ulogic; + dec_alu_rf1_use_rb_amt_lo : out std_ulogic; + dec_alu_rf1_zm_ins : out std_ulogic; + dec_alu_rf1_cr_logical : out std_ulogic; + dec_alu_rf1_cr_log_fcn : out std_ulogic_vector(0 to 3); + dec_alu_rf1_log_fcn : out std_ulogic_vector(0 to 3); + dec_alu_rf1_me_ins_b : out std_ulogic_vector(0 to 5); + dec_alu_rf1_mb_ins : out std_ulogic_vector(0 to 5); + dec_alu_rf1_sh_amt : out std_ulogic_vector(0 to 5); + dec_alu_rf1_mb_gt_me : out std_ulogic + ); +-- synopsys translate_off +-- synopsys translate_on + +end xuq_dec_dcdmrg; + +architecture xuq_dec_dcdmrg of xuq_dec_dcdmrg is + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal cmp_byt : std_ulogic; + signal cr_log : std_ulogic; + signal rotlw : std_ulogic; + signal imm_log : std_ulogic; + signal rotld : std_ulogic; + signal x31 : std_ulogic; + signal f0_xxxx00 : std_ulogic; + signal f0_xxx0xx : std_ulogic; + signal f0_xxxx0x : std_ulogic; + signal f1_1xxxx : std_ulogic; + signal f1_111xx : std_ulogic; + signal f1_110xx : std_ulogic; + signal f1_x1x1x : std_ulogic; + signal f1_x1xx0 : std_ulogic; + signal f1_x1xx1 : std_ulogic; + signal f1_xxx00 : std_ulogic; + signal f1_xxx11 : std_ulogic; + signal f1_xx10x : std_ulogic; + signal f2_11xxx : std_ulogic; + signal f2_xxx0x : std_ulogic; + signal f2_111xx : std_ulogic; + signal f1_xxx01 : std_ulogic; + signal f1_xxx10 : std_ulogic; + signal f2_xx01x : std_ulogic; + signal f2_xx00x : std_ulogic; + signal rotlw_nm : std_ulogic; + signal rotlw_pass : std_ulogic; + signal rotld_pass : std_ulogic; + signal sh_lft_rb : std_ulogic; + signal sh_lft_rb_dw : std_ulogic; + signal sh_rgt : std_ulogic; + signal sh_rgt_rb : std_ulogic; + signal sh_rgt_rb_dw : std_ulogic; + signal shift_imm : std_ulogic; + signal sh_rb : std_ulogic; + signal sh_rb_dw : std_ulogic; + signal sh_rb_wd : std_ulogic; + signal x31_sh_log_sgn : std_ulogic; + signal op_sgn_xtd : std_ulogic; + signal op_sra : std_ulogic; + signal wd_if_sh : std_ulogic; + signal xtd_log : std_ulogic; + signal sh_word_int : std_ulogic; + signal imm_xor_or : std_ulogic; + signal imm_and_or : std_ulogic; + signal xtd_nor : std_ulogic; + signal xtd_eqv_orc_nand : std_ulogic; + signal xtd_nand : std_ulogic; + signal xtd_andc_xor_or : std_ulogic; + signal xtd_and_eqv_orc : std_ulogic; + signal xtd_or_orc : std_ulogic; + signal xtd_xor_or : std_ulogic; + signal sel_ins_amt_hi : std_ulogic; + signal sel_ins_me_lo_wd : std_ulogic; + signal sel_ins_me_lo_dw : std_ulogic; + signal sel_ins_amt_lo : std_ulogic; + signal sel_ins_me_hi : std_ulogic; + signal rot_imm_mb : std_ulogic; + signal gt5_g_45 : std_ulogic; + signal gt5_g_23 : std_ulogic; + signal gt5_g_1 : std_ulogic; + signal gt5_t_23 : std_ulogic; + signal gt5_t_1 : std_ulogic; + signal mb_gt_me_cmp_wd0_b : std_ulogic; + signal mb_gt_me_cmp_wd1_b : std_ulogic; + signal mb_gt_me_cmp_wd2_b : std_ulogic; + signal mb_gt_me_cmp_wd : std_ulogic; + signal gt6_g_45 : std_ulogic; + signal gt6_g_23 : std_ulogic; + signal gt6_g_01 : std_ulogic; + signal gt6_t_23 : std_ulogic; + signal gt6_t_01 : std_ulogic; + signal mb_gt_me_cmp_dw0_b : std_ulogic; + signal mb_gt_me_cmp_dw1_b : std_ulogic; + signal mb_gt_me_cmp_dw2_b : std_ulogic; + signal mb_gt_me_cmp_dw : std_ulogic; + signal me_ins : std_ulogic_vector(0 to 5); + signal gt5_in0 : std_ulogic_vector(1 to 5); + signal gt5_in1 : std_ulogic_vector(1 to 5); + signal gt6_in0 : std_ulogic_vector(0 to 5); + signal gt6_in1 : std_ulogic_vector(0 to 5); + signal gt5_g_b : std_ulogic_vector(1 to 5); + signal gt5_t_b : std_ulogic_vector(1 to 4); + signal gt6_g_b : std_ulogic_vector(0 to 5); + signal gt6_t_b : std_ulogic_vector(0 to 4); + signal f0_xxxx11 : std_ulogic; + signal f1_0xxxx : std_ulogic; + signal f1_1xxx0 : std_ulogic; + signal f1_xxxx0 : std_ulogic; + signal f1_xxxx1 : std_ulogic; + signal f2_xxx1x : std_ulogic; + signal f1_xx1xx : std_ulogic; + signal xtd_nand_or_orc : std_ulogic; + signal rld_cr : std_ulogic; + signal rld_cl : std_ulogic; + signal rld_icr : std_ulogic; + signal rld_icl : std_ulogic; + signal rld_ic : std_ulogic; + signal rld_imi : std_ulogic; + signal sh_lft_imm_dw : std_ulogic; + signal sh_lft_imm : std_ulogic; + signal sh_rgt_imm_dw : std_ulogic; + signal sh_rgt_imm : std_ulogic; + signal rotld_en_mbgtme : std_ulogic; + signal rf1_log_fcn : std_ulogic_vector(0 to 3); + signal isel : std_ulogic; + +begin + + ---------------------------------------------------- + -- decode primary field opcode bits [0:5] --- + ---------------------------------------------------- + isel <= '1' when x31='1' and i(26 to 30) = "01111" else '0'; + + cmp_byt <= '1' when x31='1' and i(21 to 30) = "0111111100" else '0'; -- 31/508 + + cr_log <= not i(0) and i(1) and not i(2) and not i(3) and i(4) and i(5) ; --010011 (19) + rotlw <= not i(0) and i(1) and not i(2) and i(3) ; --0101xx (20:23) + imm_log <= not i(0) and i(1) and i(2) and (not i(3) or not i(4) ); --0110xx (24:27) + --01110x (28,29) + rotld <= not i(0) and i(1) and i(2) and i(3) and i(4) and not i(5) ; --011110 (30) + x31 <= not i(0) and i(1) and i(2) and i(3) and i(4) and i(5) ; --011111 (31) + + f0_xxxx00 <= not i(4) and not i(5) ; + f0_xxx0xx <= not i(3) ; + f0_xxxx0x <= not i(4) ; + f0_xxxx11 <= i(4) and i(5) ; + + + ----------------------------------------------------- + -- decode i(21:25) + ----------------------------------------------------- + + f1_0xxxx <= not i(21) ; + f1_110xx <= i(21) and i(22) and not i(23) ; + f1_111xx <= i(21) and i(22) and i(23) ; + f1_1xxx0 <= i(21) and not i(25) ; + f1_1xxxx <= i(21) ; + f1_x1x1x <= i(22) and i(24) ; + f1_xx1xx <= i(23) ; + f1_x1xx0 <= i(22) and not i(25) ; + f1_x1xx1 <= i(22) and i(25) ; + f1_xx10x <= i(23) and not i(24) ; + f1_xxx01 <= not i(24) and i(25) ; + f1_xxx11 <= i(24) and i(25) ; + f1_xxxx0 <= not i(25) ; + f1_xxxx1 <= i(25) ; + f1_xxx00 <= not i(24) and not i(25) ; + f1_xxx10 <= i(24) and not i(25) ; + + ----------------------------------------------------- + -- decode i(26:30) + ----------------------------------------------------- + + f2_11xxx <= i(26) and i(27) ; -- shifts / logicals / sign_xtd + f2_xxx0x <= not i(29) ; -- word / double + f2_111xx <= i(26) and i(27) and i(28) ; + f2_xx01x <= not i(28) and i(29) ; + f2_xx00x <= not i(28) and not i(29) ; + f2_xxx1x <= i(29) ; + + + rotlw_nm <= rotlw and f0_xxxx11 ; + rotlw_pass <= rotlw and f0_xxxx00 ; + + rotld_pass <= rld_imi ; + + sh_lft_rb <= x31 and f1_0xxxx ; + sh_lft_rb_dw <= x31 and f1_0xxxx and f2_xxx1x ; + sh_rgt <= x31 and f1_1xxxx ; + sh_rgt_rb <= x31 and f1_1xxx0 ; + sh_rgt_rb_dw <= x31 and f1_1xxx0 and f2_xxx1x ; + shift_imm <= x31 and f1_xxxx1 ; + sh_rb <= x31 and f1_xxxx0 ; + sh_rb_dw <= x31 and f1_xxxx0 and f2_xxx1x ; + sh_rb_wd <= x31 and f1_xxxx0 and f2_xxx0x ; + x31_sh_log_sgn <= x31 and f2_11xxx ; + op_sgn_xtd <= x31 and f1_111xx ; + op_sra <= x31 and f1_110xx ; + wd_if_sh <= x31 and f2_xxx0x ; + xtd_log <= x31 and f2_111xx ; + + sh_lft_imm_dw <= tidn; + sh_lft_imm <= tidn; + sh_rgt_imm_dw <= x31 and i(21) and i(25) and i(29) ; + sh_rgt_imm <= x31 and i(21) and i(25) ; + + ----------------------------------------------------- + -- output signal + ----------------------------------------------------- + + -- (select to rot/log result instead of the adder result) + dec_alu_rf1_sel_rot_log <= (cmp_byt ) or + (cr_log ) or + (rotlw ) or + (imm_log ) or + (rotld ) or + (x31_sh_log_sgn ); + + -- (zero out the mask to pass "insert_data" as the result) + dec_alu_rf1_zm_ins <= (isel ) or + (cmp_byt ) or + (cr_log ) or + (xtd_log ) or + (imm_log ) or + (op_sgn_xtd ); -- sgn extends + + -- (only needs to be correct when shifting) + dec_alu_rf1_sh_right <= sh_rgt; + + sh_word_int <=(rotlw ) or + (wd_if_sh ); + + -- (only needs to be correct when shifting) + dec_alu_rf1_sh_word <= sh_word_int ; + dec_alu_rf1_cr_logical <= cr_log ; + + dec_alu_rf1_sgnxtd_byte <= op_sgn_xtd and f1_xxx01 and not isel; + dec_alu_rf1_sgnxtd_half <= op_sgn_xtd and f1_xxx00 and not isel; + dec_alu_rf1_sgnxtd_wd <= op_sgn_xtd and f1_xxx10 and not isel; + dec_alu_rf1_sra_dw <= op_sra and f2_xx01x and not isel; + dec_alu_rf1_sra_wd <= op_sra and f2_xx00x and not isel; + + dec_alu_rf1_cr_log_fcn(0) <= i(25) ; + dec_alu_rf1_cr_log_fcn(1) <= i(24) ; + dec_alu_rf1_cr_log_fcn(2) <= i(23) ; + dec_alu_rf1_cr_log_fcn(3) <= i(22) ; + + imm_xor_or <= f0_xxx0xx ; + imm_and_or <= f0_xxxx0x ; + xtd_nor <= f1_xxx11 ; + xtd_eqv_orc_nand <= f1_x1xx0 ; + xtd_nand <= f1_x1x1x ; + xtd_nand_or_orc <= f1_xx1xx ; + xtd_andc_xor_or <= f1_xxx01 ; + xtd_and_eqv_orc <= f1_xxx00 ; + xtd_or_orc <= f1_xx10x ; + xtd_xor_or <= f1_x1xx1 ; + + + with cmp_byt select + dec_alu_rf1_log_fcn <= "1001" when '1', + rf1_log_fcn when others; + + + rf1_log_fcn(0) <= (xtd_log and xtd_nor ) or -- xtd_log nor + (xtd_log and xtd_eqv_orc_nand ) or -- xtd_log eqv,orc,nand + (cmp_byt ) ; -- xnor + + rf1_log_fcn(1) <= (xtd_log and xtd_xor_or ) or -- xtd_log xor,or + (xtd_log and xtd_nand ) or -- xtd_log nand + (imm_log and imm_xor_or ) or -- xor,or + (rotlw_pass ) or -- pass rlwimi + (rotld_pass ) ; -- pass rldimi + + rf1_log_fcn(2) <= (xtd_log and xtd_andc_xor_or ) or -- xtd_log andc,xor,or + (xtd_log and xtd_nand_or_orc ) or -- xtd_log nand_or_orc + (imm_log and imm_xor_or ) ; -- xor,or + + + rf1_log_fcn(3) <= (cmp_byt ) or -- xnor + (xtd_log and xtd_and_eqv_orc ) or -- xtd_log and,eqv_orc + (xtd_log and xtd_or_orc ) or -- xtd_log or,orc + (imm_log and imm_and_or ) or -- and,or + (rotlw_pass ) or -- pass rlwimi + (rotld_pass ) ; -- pass rldimi + + + dec_alu_rf1_chk_shov_dw <= (sh_rb_dw ); + dec_alu_rf1_chk_shov_wd <= (sh_rb_wd ); + + + ----------------------------------------------- + + dec_alu_rf1_me_ins_b(0 to 5) <= not me_ins(0 to 5) ; + + me_ins(0) <= ( rotlw ) or -- force_msb + ( i(26) and sel_ins_me_hi ) or + ( not i(30) and sel_ins_amt_hi ) ; + + me_ins(1 to 5) <= ( i(26 to 30) and (1 to 5=> sel_ins_me_lo_wd) ) or + ( i(21 to 25) and (1 to 5=> sel_ins_me_lo_dw) ) or + ( not i(16 to 20) and (1 to 5=> sel_ins_amt_lo ) ) ; + + sel_ins_me_lo_wd <= rotlw ; + sel_ins_me_lo_dw <= rld_cr or rld_icr ; + + sel_ins_amt_lo <= rld_ic or rld_imi or sh_lft_rb ; + sel_ins_amt_hi <= rld_ic or rld_imi or sh_lft_rb_dw ; + sel_ins_me_hi <= rld_cr or rld_icr ; + + + dec_alu_rf1_use_me_rb_hi <= ( sh_lft_rb_dw ); + dec_alu_rf1_use_me_rb_lo <= ( sh_lft_rb ); + + dec_alu_rf1_use_me_ins_hi <= rld_cr or rld_icr or rld_imi or rld_ic or rotlw or sh_lft_imm_dw ; + dec_alu_rf1_use_me_ins_lo <= rld_cr or rld_icr or rld_imi or rld_ic or rotlw or sh_lft_imm ; + + rld_icl <= rotld and not i(27) and not i(28) and not i(29) ; + rld_icr <= rotld and not i(27) and not i(28) and i(29) ; + rld_ic <= rotld and not i(27) and i(28) and not i(29) ; + rld_imi <= rotld and not i(27) and i(28) and i(29) ; + rld_cl <= rotld and i(27) and not i(30); + rld_cr <= rotld and i(27) and i(30); + + + ----------------------------------------------- + + dec_alu_rf1_mb_ins(0) <= ( i(26) and rot_imm_mb ) or + ( i(30) and shift_imm ) or + ( rotlw ) or -- force_msb + ( wd_if_sh ) ; -- force_msb + + + dec_alu_rf1_mb_ins(1 to 5) <= ( i(21 to 25) and (1 to 5=> rot_imm_mb ) ) or + ( i(16 to 20) and (1 to 5=> shift_imm ) ) ; + + + rot_imm_mb <= ( rotlw ) or + ( rld_cl or rld_icl or rld_ic or rld_imi ) ; + + + dec_alu_rf1_use_mb_rb_lo <= sh_rgt_rb ; + dec_alu_rf1_use_mb_rb_hi <= sh_rgt_rb_dw ; + dec_alu_rf1_use_mb_ins_hi <= rld_cl or rld_icl or rld_imi or rld_ic or rotlw or sh_rgt_imm_dw or wd_if_sh; + dec_alu_rf1_use_mb_ins_lo <= rld_cl or rld_icl or rld_imi or rld_ic or rotlw or sh_rgt_imm ; + + + ----------------------------------------------- + + dec_alu_rf1_use_rb_amt_hi <= ( rld_cr ) or + ( rld_cl ) or + ( sh_rb_dw ) ; + + + + dec_alu_rf1_use_rb_amt_lo <= ( rld_cr ) or + ( rld_cl ) or + ( rotlw_nm ) or -- rlwnm + ( sh_rb ) ; + + + + dec_alu_rf1_sh_amt(0) <= i(30) and not sh_word_int ; + dec_alu_rf1_sh_amt(1 to 5) <= i(16 to 20) ; + + ----------------------------------------------- + + + rotld_en_mbgtme <= rld_imi or rld_ic ; + + dec_alu_rf1_mb_gt_me <= (mb_gt_me_cmp_wd and rotlw ) or + (mb_gt_me_cmp_dw and rotld_en_mbgtme ) ; -- rldic,rldimi + + + + --------------------------------------------- + + gt5_in1(1 to 5) <= i(21 to 25) ; -- mb + gt5_in0(1 to 5) <= not i(26 to 30) ; -- me + + gt6_in1(0 to 5) <= i(26) & i(21 to 25) ; -- mb + gt6_in0(0 to 5) <= i(30) & i(16 to 20) ; -- me not( not amt ) + + -------------------------------------------- + + gt5_g_b(1 to 5) <= not( gt5_in0(1 to 5) and gt5_in1(1 to 5) ); + gt5_t_b(1 to 4) <= not( gt5_in0(1 to 4) or gt5_in1(1 to 4) ); + + gt5_g_45 <= not( gt5_g_b(4) and (gt5_t_b(4) or gt5_g_b(5) ) ); + gt5_g_23 <= not( gt5_g_b(2) and (gt5_t_b(2) or gt5_g_b(3) ) ); + gt5_g_1 <= not( gt5_g_b(1) ); + + gt5_t_23 <= not( gt5_t_b(2) or gt5_t_b(3) ); + gt5_t_1 <= not( gt5_t_b(1) ); + + mb_gt_me_cmp_wd0_b <= not( gt5_g_1 ); + mb_gt_me_cmp_wd1_b <= not( gt5_g_23 and gt5_t_1 ); + mb_gt_me_cmp_wd2_b <= not( gt5_g_45 and gt5_t_1 and gt5_t_23 ); + + mb_gt_me_cmp_wd <= not( mb_gt_me_cmp_wd0_b and mb_gt_me_cmp_wd1_b and mb_gt_me_cmp_wd2_b ); + + ---------------------------------------------- + + gt6_g_b(0 to 5) <= not( gt6_in0(0 to 5) and gt6_in1(0 to 5) ); + gt6_t_b(0 to 4) <= not( gt6_in0(0 to 4) or gt6_in1(0 to 4) ); + + gt6_g_45 <= not( gt6_g_b(4) and (gt6_t_b(4) or gt6_g_b(5) ) ); + gt6_g_23 <= not( gt6_g_b(2) and (gt6_t_b(2) or gt6_g_b(3) ) ); + gt6_g_01 <= not( gt6_g_b(0) and (gt6_t_b(0) or gt6_g_b(1) ) ); + + gt6_t_23 <= not( gt6_t_b(2) or gt6_t_b(3) ); + gt6_t_01 <= not( gt6_t_b(0) or gt6_t_b(1) ); + + mb_gt_me_cmp_dw0_b <= not( gt6_g_01 ); + mb_gt_me_cmp_dw1_b <= not( gt6_g_23 and gt6_t_01 ); + mb_gt_me_cmp_dw2_b <= not( gt6_g_45 and gt6_t_01 and gt6_t_23 ); + + mb_gt_me_cmp_dw <= not( mb_gt_me_cmp_dw0_b and mb_gt_me_cmp_dw1_b and mb_gt_me_cmp_dw2_b ); + + ---------------------------------------------- + + mark_unused(i(6 to 15)); + mark_unused(i(31)); + + +end architecture xuq_dec_dcdmrg; diff --git a/rel/src/vhdl/work/xuq_dec_sspr.vhdl b/rel/src/vhdl/work/xuq_dec_sspr.vhdl new file mode 100644 index 0000000..60f1ac1 --- /dev/null +++ b/rel/src/vhdl/work/xuq_dec_sspr.vhdl @@ -0,0 +1,480 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XU SlowSPR Decode & Hole generation +-- +library ieee,ibm,support,work,tri; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use support.power_logic_pkg.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use tri.tri_latches_pkg.all; +use work.xuq_pkg.all; + +entity xuq_dec_sspr is +generic( + expand_type : integer := 2; + threads : integer := 4; + ctr_size : integer := 5); +port( + nclk : in clk_logic; + + d_mode_dc : in std_ulogic; + delay_lclkr_dc : in std_ulogic; + mpw1_dc_b : in std_ulogic; + mpw2_dc_b : in std_ulogic; + + func_sl_force : in std_ulogic; + func_sl_thold_0_b : in std_ulogic; + sg_0 : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + rf1_act : in std_ulogic; + rf1_val : in std_ulogic_vector(0 to threads-1); + rf1_instr : in std_ulogic_vector(0 to 31); + + spr_dec_spr_xucr0_ssdly : in std_ulogic_vector(0 to ctr_size-1); + + slowspr_need_hole : out std_ulogic; + ex1_is_slowspr_rd : out std_ulogic; + ex1_is_slowspr_wr : out std_ulogic; + + -- Power + vdd : inout power_logic; + gnd : inout power_logic +); + +-- synopsys translate_off + +-- synopsys translate_on +end xuq_dec_sspr; +architecture xuq_dec_sspr of xuq_dec_sspr is + +subtype s2 is std_ulogic_vector(0 to 1); +type T_ctr is array (0 to threads-1) of std_ulogic_vector(0 to ctr_size-1); +-- Latches +signal slowspr_ctr_q, slowspr_ctr_d : T_ctr; +signal spr_xucr0_ssdly_q : std_ulogic_vector(0 to ctr_size-1); -- spr_dec_spr_xucr0_ssdly +signal ex1_is_slowspr_wr_q, rf1_is_slowspr_wr : std_ulogic; +signal ex1_is_slowspr_rd_q, rf1_is_slowspr_rd : std_ulogic; +signal slowspr_hole_q, slowspr_hole_d : std_ulogic; +-- Scanchains +constant slowspr_ctr_offset : integer := 0; +constant spr_xucr0_ssdly_offset : integer := slowspr_ctr_offset + slowspr_ctr_q(0)'length*threads; +constant ex1_is_slowspr_wr_offset : integer := spr_xucr0_ssdly_offset + spr_xucr0_ssdly_q'length; +constant ex1_is_slowspr_rd_offset : integer := ex1_is_slowspr_wr_offset + 1; +constant slowspr_hole_offset : integer := ex1_is_slowspr_rd_offset + 1; +constant scan_right : integer := slowspr_hole_offset + 1; +-- Latch Instances +signal siv : std_ulogic_vector(0 to scan_right-1); +signal sov : std_ulogic_vector(0 to scan_right-1); +-- Signals +signal tiup : std_ulogic; +signal rf1_opcode_is_31 : std_ulogic; +signal rf1_is_mfspr, rf1_is_mtspr : std_ulogic; +signal rf1_slowspr_range : std_ulogic; +signal rf1_sspr_ctr_init, rf1_sspr_ctr_act : std_ulogic_vector(0 to threads-1); +signal slowspr_ctr_zero, slowspr_ctr_one : std_ulogic_vector(0 to threads-1); +signal slowspr_hole : std_ulogic_vector(0 to threads-1); +signal slowspr_ctr_m1 : T_ctr; +signal + rf1_dvc1_re , rf1_dvc2_re , rf1_eplc_re , rf1_epsc_re + , rf1_eptcfg_re , rf1_immr_re , rf1_imr_re , rf1_iucr0_re + , rf1_iucr1_re , rf1_iucr2_re , rf1_iudbg0_re , rf1_iudbg1_re + , rf1_iudbg2_re , rf1_iulfsr_re , rf1_iullcr_re , rf1_lper_re + , rf1_lperu_re , rf1_lpidr_re , rf1_lratcfg_re , rf1_lratps_re + , rf1_mas0_re , rf1_mas0_mas1_re, rf1_mas1_re , rf1_mas2_re + , rf1_mas2u_re , rf1_mas3_re , rf1_mas4_re , rf1_mas5_re + , rf1_mas5_mas6_re, rf1_mas6_re , rf1_mas7_re , rf1_mas7_mas3_re + , rf1_mas8_re , rf1_mas8_mas1_re, rf1_mmucfg_re , rf1_mmucr0_re + , rf1_mmucr1_re , rf1_mmucr2_re , rf1_mmucr3_re , rf1_mmucsr0_re + , rf1_pid_re , rf1_ppr32_re , rf1_tlb0cfg_re , rf1_tlb0ps_re + , rf1_xucr2_re , rf1_xudbg0_re , rf1_xudbg1_re , rf1_xudbg2_re + : std_ulogic; +signal + rf1_dvc1_we , rf1_dvc2_we , rf1_eplc_we , rf1_epsc_we + , rf1_immr_we , rf1_imr_we , rf1_iucr0_we , rf1_iucr1_we + , rf1_iucr2_we , rf1_iudbg0_we , rf1_iulfsr_we , rf1_iullcr_we + , rf1_lper_we , rf1_lperu_we , rf1_lpidr_we , rf1_mas0_we + , rf1_mas0_mas1_we, rf1_mas1_we , rf1_mas2_we , rf1_mas2u_we + , rf1_mas3_we , rf1_mas4_we , rf1_mas5_we , rf1_mas5_mas6_we + , rf1_mas6_we , rf1_mas7_we , rf1_mas7_mas3_we, rf1_mas8_we + , rf1_mas8_mas1_we, rf1_mmucr0_we , rf1_mmucr1_we , rf1_mmucr2_we + , rf1_mmucr3_we , rf1_mmucsr0_we , rf1_pid_we , rf1_ppr32_we + , rf1_xucr2_we , rf1_xudbg0_we + : std_ulogic; +signal + rf1_dvc1_rdec , rf1_dvc2_rdec , rf1_eplc_rdec , rf1_epsc_rdec + , rf1_eptcfg_rdec, rf1_immr_rdec , rf1_imr_rdec , rf1_iucr0_rdec + , rf1_iucr1_rdec , rf1_iucr2_rdec , rf1_iudbg0_rdec, rf1_iudbg1_rdec + , rf1_iudbg2_rdec, rf1_iulfsr_rdec, rf1_iullcr_rdec, rf1_lper_rdec + , rf1_lperu_rdec , rf1_lpidr_rdec , rf1_lratcfg_rdec, rf1_lratps_rdec + , rf1_mas0_rdec , rf1_mas0_mas1_rdec, rf1_mas1_rdec , rf1_mas2_rdec + , rf1_mas2u_rdec , rf1_mas3_rdec , rf1_mas4_rdec , rf1_mas5_rdec + , rf1_mas5_mas6_rdec, rf1_mas6_rdec , rf1_mas7_rdec , rf1_mas7_mas3_rdec + , rf1_mas8_rdec , rf1_mas8_mas1_rdec, rf1_mmucfg_rdec, rf1_mmucr0_rdec + , rf1_mmucr1_rdec, rf1_mmucr2_rdec, rf1_mmucr3_rdec, rf1_mmucsr0_rdec + , rf1_pid_rdec , rf1_ppr32_rdec , rf1_tlb0cfg_rdec, rf1_tlb0ps_rdec + , rf1_xucr2_rdec , rf1_xudbg0_rdec, rf1_xudbg1_rdec, rf1_xudbg2_rdec + : std_ulogic; +signal + rf1_dvc1_wdec , rf1_dvc2_wdec , rf1_eplc_wdec , rf1_epsc_wdec + , rf1_immr_wdec , rf1_imr_wdec , rf1_iucr0_wdec , rf1_iucr1_wdec + , rf1_iucr2_wdec , rf1_iudbg0_wdec, rf1_iulfsr_wdec, rf1_iullcr_wdec + , rf1_lper_wdec , rf1_lperu_wdec , rf1_lpidr_wdec , rf1_mas0_wdec + , rf1_mas0_mas1_wdec, rf1_mas1_wdec , rf1_mas2_wdec , rf1_mas2u_wdec + , rf1_mas3_wdec , rf1_mas4_wdec , rf1_mas5_wdec , rf1_mas5_mas6_wdec + , rf1_mas6_wdec , rf1_mas7_wdec , rf1_mas7_mas3_wdec, rf1_mas8_wdec + , rf1_mas8_mas1_wdec, rf1_mmucr0_wdec, rf1_mmucr1_wdec, rf1_mmucr2_wdec + , rf1_mmucr3_wdec, rf1_mmucsr0_wdec, rf1_pid_wdec , rf1_ppr32_wdec + , rf1_xucr2_wdec , rf1_xudbg0_wdec + : std_ulogic; + +begin + +tiup <= '1'; + +-- Slow SPR Hole +slowspr_hole_gen : for t in 0 to threads-1 generate + + rf1_sspr_ctr_act(t) <= rf1_val(t) or not slowspr_ctr_zero(t); + + rf1_sspr_ctr_init(t) <= rf1_val(t) and rf1_is_mfspr and rf1_is_slowspr_rd; + + slowspr_ctr_m1(t) <= std_ulogic_vector(unsigned(slowspr_ctr_q(t)) - 1); + + with s2'(rf1_sspr_ctr_init(t) & slowspr_ctr_zero(t)) select + slowspr_ctr_d(t) <= slowspr_ctr_m1(t) when "00", -- Decrement + (others=>'0') when "01", -- Hold + spr_xucr0_ssdly_q when others; -- Init + + slowspr_ctr_zero(t) <= not or_reduce(slowspr_ctr_q(t)); + + slowspr_ctr_one(t) <= not or_reduce(slowspr_ctr_q(t)(0 to ctr_size-2)) and slowspr_ctr_q(t)(ctr_size-1); + + with (not or_reduce(spr_xucr0_ssdly_q)) select + slowspr_hole(t) <= rf1_sspr_ctr_init(t) when '1', + slowspr_ctr_one(t) when others; + +end generate; + +slowspr_hole_d <= or_reduce(slowspr_hole); +slowspr_need_hole <= slowspr_hole_q; +ex1_is_slowspr_wr <= ex1_is_slowspr_wr_q; +ex1_is_slowspr_rd <= ex1_is_slowspr_rd_q; + +-- Deocde +rf1_opcode_is_31 <= rf1_instr(0 to 5) = "011111"; +rf1_is_mfspr <= '1' when rf1_opcode_is_31='1' and rf1_instr(21 to 30) = "0101010011" else '0'; -- 31/339 +rf1_is_mtspr <= '1' when rf1_opcode_is_31='1' and rf1_instr(21 to 30) = "0111010011" else '0'; -- 31/467 +rf1_slowspr_range <=((rf1_instr(16 to 20) = "11110") or -- 976-991 + (rf1_instr(16 to 20) = "11100")) -- 912-927 + and rf1_instr(11); +rf1_dvc1_rdec <= (rf1_instr(11 to 20) = "1111001001"); -- 318 +rf1_dvc2_rdec <= (rf1_instr(11 to 20) = "1111101001"); -- 319 +rf1_eplc_rdec <= (rf1_instr(11 to 20) = "1001111101"); -- 947 +rf1_epsc_rdec <= (rf1_instr(11 to 20) = "1010011101"); -- 948 +rf1_eptcfg_rdec <= (rf1_instr(11 to 20) = "1111001010"); -- 350 +rf1_immr_rdec <= (rf1_instr(11 to 20) = "1000111011"); -- 881 +rf1_imr_rdec <= (rf1_instr(11 to 20) = "1000011011"); -- 880 +rf1_iucr0_rdec <= (rf1_instr(11 to 20) = "1001111111"); -- 1011 +rf1_iucr1_rdec <= (rf1_instr(11 to 20) = "1001111011"); -- 883 +rf1_iucr2_rdec <= (rf1_instr(11 to 20) = "1010011011"); -- 884 +rf1_iudbg0_rdec <= (rf1_instr(11 to 20) = "1100011011"); -- 888 +rf1_iudbg1_rdec <= (rf1_instr(11 to 20) = "1100111011"); -- 889 +rf1_iudbg2_rdec <= (rf1_instr(11 to 20) = "1101011011"); -- 890 +rf1_iulfsr_rdec <= (rf1_instr(11 to 20) = "1101111011"); -- 891 +rf1_iullcr_rdec <= (rf1_instr(11 to 20) = "1110011011"); -- 892 +rf1_lper_rdec <= (rf1_instr(11 to 20) = "1100000001"); -- 56 +rf1_lperu_rdec <= (rf1_instr(11 to 20) = "1100100001"); -- 57 +rf1_lpidr_rdec <= (rf1_instr(11 to 20) = "1001001010"); -- 338 +rf1_lratcfg_rdec <= (rf1_instr(11 to 20) = "1011001010"); -- 342 +rf1_lratps_rdec <= (rf1_instr(11 to 20) = "1011101010"); -- 343 +rf1_mas0_rdec <= (rf1_instr(11 to 20) = "1000010011"); -- 624 +rf1_mas0_mas1_rdec<= (rf1_instr(11 to 20) = "1010101011"); -- 373 +rf1_mas1_rdec <= (rf1_instr(11 to 20) = "1000110011"); -- 625 +rf1_mas2_rdec <= (rf1_instr(11 to 20) = "1001010011"); -- 626 +rf1_mas2u_rdec <= (rf1_instr(11 to 20) = "1011110011"); -- 631 +rf1_mas3_rdec <= (rf1_instr(11 to 20) = "1001110011"); -- 627 +rf1_mas4_rdec <= (rf1_instr(11 to 20) = "1010010011"); -- 628 +rf1_mas5_rdec <= (rf1_instr(11 to 20) = "1001101010"); -- 339 +rf1_mas5_mas6_rdec<= (rf1_instr(11 to 20) = "1110001010"); -- 348 +rf1_mas6_rdec <= (rf1_instr(11 to 20) = "1011010011"); -- 630 +rf1_mas7_rdec <= (rf1_instr(11 to 20) = "1000011101"); -- 944 +rf1_mas7_mas3_rdec<= (rf1_instr(11 to 20) = "1010001011"); -- 372 +rf1_mas8_rdec <= (rf1_instr(11 to 20) = "1010101010"); -- 341 +rf1_mas8_mas1_rdec<= (rf1_instr(11 to 20) = "1110101010"); -- 349 +rf1_mmucfg_rdec <= (rf1_instr(11 to 20) = "1011111111"); -- 1015 +rf1_mmucr0_rdec <= (rf1_instr(11 to 20) = "1110011111"); -- 1020 +rf1_mmucr1_rdec <= (rf1_instr(11 to 20) = "1110111111"); -- 1021 +rf1_mmucr2_rdec <= (rf1_instr(11 to 20) = "1111011111"); -- 1022 +rf1_mmucr3_rdec <= (rf1_instr(11 to 20) = "1111111111"); -- 1023 +rf1_mmucsr0_rdec <= (rf1_instr(11 to 20) = "1010011111"); -- 1012 +rf1_pid_rdec <= (rf1_instr(11 to 20) = "1000000001"); -- 48 +rf1_ppr32_rdec <= (rf1_instr(11 to 20) = "0001011100"); -- 898 +rf1_tlb0cfg_rdec <= (rf1_instr(11 to 20) = "1000010101"); -- 688 +rf1_tlb0ps_rdec <= (rf1_instr(11 to 20) = "1100001010"); -- 344 +rf1_xucr2_rdec <= (rf1_instr(11 to 20) = "1100011111"); -- 1016 +rf1_xudbg0_rdec <= (rf1_instr(11 to 20) = "1010111011"); -- 885 +rf1_xudbg1_rdec <= (rf1_instr(11 to 20) = "1011011011"); -- 886 +rf1_xudbg2_rdec <= (rf1_instr(11 to 20) = "1011111011"); -- 887 +rf1_dvc1_re <= rf1_dvc1_rdec; +rf1_dvc2_re <= rf1_dvc2_rdec; +rf1_eplc_re <= rf1_eplc_rdec; +rf1_epsc_re <= rf1_epsc_rdec; +rf1_eptcfg_re <= rf1_eptcfg_rdec; +rf1_immr_re <= rf1_immr_rdec; +rf1_imr_re <= rf1_imr_rdec; +rf1_iucr0_re <= rf1_iucr0_rdec; +rf1_iucr1_re <= rf1_iucr1_rdec; +rf1_iucr2_re <= rf1_iucr2_rdec; +rf1_iudbg0_re <= rf1_iudbg0_rdec; +rf1_iudbg1_re <= rf1_iudbg1_rdec; +rf1_iudbg2_re <= rf1_iudbg2_rdec; +rf1_iulfsr_re <= rf1_iulfsr_rdec; +rf1_iullcr_re <= rf1_iullcr_rdec; +rf1_lper_re <= rf1_lper_rdec; +rf1_lperu_re <= rf1_lperu_rdec; +rf1_lpidr_re <= rf1_lpidr_rdec; +rf1_lratcfg_re <= rf1_lratcfg_rdec; +rf1_lratps_re <= rf1_lratps_rdec; +rf1_mas0_re <= rf1_mas0_rdec; +rf1_mas0_mas1_re <= rf1_mas0_mas1_rdec; +rf1_mas1_re <= rf1_mas1_rdec; +rf1_mas2_re <= rf1_mas2_rdec; +rf1_mas2u_re <= rf1_mas2u_rdec; +rf1_mas3_re <= rf1_mas3_rdec; +rf1_mas4_re <= rf1_mas4_rdec; +rf1_mas5_re <= rf1_mas5_rdec; +rf1_mas5_mas6_re <= rf1_mas5_mas6_rdec; +rf1_mas6_re <= rf1_mas6_rdec; +rf1_mas7_re <= rf1_mas7_rdec; +rf1_mas7_mas3_re <= rf1_mas7_mas3_rdec; +rf1_mas8_re <= rf1_mas8_rdec; +rf1_mas8_mas1_re <= rf1_mas8_mas1_rdec; +rf1_mmucfg_re <= rf1_mmucfg_rdec; +rf1_mmucr0_re <= rf1_mmucr0_rdec; +rf1_mmucr1_re <= rf1_mmucr1_rdec; +rf1_mmucr2_re <= rf1_mmucr2_rdec; +rf1_mmucr3_re <= rf1_mmucr3_rdec; +rf1_mmucsr0_re <= rf1_mmucsr0_rdec; +rf1_pid_re <= rf1_pid_rdec; +rf1_ppr32_re <= rf1_ppr32_rdec; +rf1_tlb0cfg_re <= rf1_tlb0cfg_rdec; +rf1_tlb0ps_re <= rf1_tlb0ps_rdec; +rf1_xucr2_re <= rf1_xucr2_rdec; +rf1_xudbg0_re <= rf1_xudbg0_rdec; +rf1_xudbg1_re <= rf1_xudbg1_rdec; +rf1_xudbg2_re <= rf1_xudbg2_rdec; +rf1_dvc1_wdec <= rf1_dvc1_rdec; +rf1_dvc2_wdec <= rf1_dvc2_rdec; +rf1_eplc_wdec <= rf1_eplc_rdec; +rf1_epsc_wdec <= rf1_epsc_rdec; +rf1_immr_wdec <= rf1_immr_rdec; +rf1_imr_wdec <= rf1_imr_rdec; +rf1_iucr0_wdec <= rf1_iucr0_rdec; +rf1_iucr1_wdec <= rf1_iucr1_rdec; +rf1_iucr2_wdec <= rf1_iucr2_rdec; +rf1_iudbg0_wdec <= rf1_iudbg0_rdec; +rf1_iulfsr_wdec <= rf1_iulfsr_rdec; +rf1_iullcr_wdec <= rf1_iullcr_rdec; +rf1_lper_wdec <= rf1_lper_rdec; +rf1_lperu_wdec <= rf1_lperu_rdec; +rf1_lpidr_wdec <= rf1_lpidr_rdec; +rf1_mas0_wdec <= rf1_mas0_rdec; +rf1_mas0_mas1_wdec<= rf1_mas0_mas1_rdec; +rf1_mas1_wdec <= rf1_mas1_rdec; +rf1_mas2_wdec <= rf1_mas2_rdec; +rf1_mas2u_wdec <= rf1_mas2u_rdec; +rf1_mas3_wdec <= rf1_mas3_rdec; +rf1_mas4_wdec <= rf1_mas4_rdec; +rf1_mas5_wdec <= rf1_mas5_rdec; +rf1_mas5_mas6_wdec<= rf1_mas5_mas6_rdec; +rf1_mas6_wdec <= rf1_mas6_rdec; +rf1_mas7_wdec <= rf1_mas7_rdec; +rf1_mas7_mas3_wdec<= rf1_mas7_mas3_rdec; +rf1_mas8_wdec <= rf1_mas8_rdec; +rf1_mas8_mas1_wdec<= rf1_mas8_mas1_rdec; +rf1_mmucr0_wdec <= rf1_mmucr0_rdec; +rf1_mmucr1_wdec <= rf1_mmucr1_rdec; +rf1_mmucr2_wdec <= rf1_mmucr2_rdec; +rf1_mmucr3_wdec <= rf1_mmucr3_rdec; +rf1_mmucsr0_wdec <= rf1_mmucsr0_rdec; +rf1_pid_wdec <= rf1_pid_rdec; +rf1_ppr32_wdec <= rf1_ppr32_rdec; +rf1_xucr2_wdec <= rf1_xucr2_rdec; +rf1_xudbg0_wdec <= rf1_xudbg0_rdec; +rf1_dvc1_we <= rf1_dvc1_wdec; +rf1_dvc2_we <= rf1_dvc2_wdec; +rf1_eplc_we <= rf1_eplc_wdec; +rf1_epsc_we <= rf1_epsc_wdec; +rf1_immr_we <= rf1_immr_wdec; +rf1_imr_we <= rf1_imr_wdec; +rf1_iucr0_we <= rf1_iucr0_wdec; +rf1_iucr1_we <= rf1_iucr1_wdec; +rf1_iucr2_we <= rf1_iucr2_wdec; +rf1_iudbg0_we <= rf1_iudbg0_wdec; +rf1_iulfsr_we <= rf1_iulfsr_wdec; +rf1_iullcr_we <= rf1_iullcr_wdec; +rf1_lper_we <= rf1_lper_wdec; +rf1_lperu_we <= rf1_lperu_wdec; +rf1_lpidr_we <= rf1_lpidr_wdec; +rf1_mas0_we <= rf1_mas0_wdec; +rf1_mas0_mas1_we <= rf1_mas0_mas1_wdec; +rf1_mas1_we <= rf1_mas1_wdec; +rf1_mas2_we <= rf1_mas2_wdec; +rf1_mas2u_we <= rf1_mas2u_wdec; +rf1_mas3_we <= rf1_mas3_wdec; +rf1_mas4_we <= rf1_mas4_wdec; +rf1_mas5_we <= rf1_mas5_wdec; +rf1_mas5_mas6_we <= rf1_mas5_mas6_wdec; +rf1_mas6_we <= rf1_mas6_wdec; +rf1_mas7_we <= rf1_mas7_wdec; +rf1_mas7_mas3_we <= rf1_mas7_mas3_wdec; +rf1_mas8_we <= rf1_mas8_wdec; +rf1_mas8_mas1_we <= rf1_mas8_mas1_wdec; +rf1_mmucr0_we <= rf1_mmucr0_wdec; +rf1_mmucr1_we <= rf1_mmucr1_wdec; +rf1_mmucr2_we <= rf1_mmucr2_wdec; +rf1_mmucr3_we <= rf1_mmucr3_wdec; +rf1_mmucsr0_we <= rf1_mmucsr0_wdec; +rf1_pid_we <= rf1_pid_wdec; +rf1_ppr32_we <= rf1_ppr32_wdec; +rf1_xucr2_we <= rf1_xucr2_wdec; +rf1_xudbg0_we <= rf1_xudbg0_wdec; + +rf1_is_slowspr_wr <=(rf1_is_mtspr and (rf1_slowspr_range or + rf1_dvc1_we or rf1_dvc2_we or rf1_eplc_we + or rf1_epsc_we or rf1_immr_we or rf1_imr_we + or rf1_iucr0_we or rf1_iucr1_we or rf1_iucr2_we + or rf1_iudbg0_we or rf1_iulfsr_we or rf1_iullcr_we + or rf1_lper_we or rf1_lperu_we or rf1_lpidr_we + or rf1_mas0_we or rf1_mas0_mas1_we or rf1_mas1_we + or rf1_mas2_we or rf1_mas2u_we or rf1_mas3_we + or rf1_mas4_we or rf1_mas5_we or rf1_mas5_mas6_we + or rf1_mas6_we or rf1_mas7_we or rf1_mas7_mas3_we + or rf1_mas8_we or rf1_mas8_mas1_we or rf1_mmucr0_we + or rf1_mmucr1_we or rf1_mmucr2_we or rf1_mmucr3_we + or rf1_mmucsr0_we or rf1_pid_we or rf1_ppr32_we + or rf1_xucr2_we or rf1_xudbg0_we )); +rf1_is_slowspr_rd <= (rf1_is_mfspr and (rf1_slowspr_range or + rf1_dvc1_re or rf1_dvc2_re or rf1_eplc_re + or rf1_epsc_re or rf1_eptcfg_re or rf1_immr_re + or rf1_imr_re or rf1_iucr0_re or rf1_iucr1_re + or rf1_iucr2_re or rf1_iudbg0_re or rf1_iudbg1_re + or rf1_iudbg2_re or rf1_iulfsr_re or rf1_iullcr_re + or rf1_lper_re or rf1_lperu_re or rf1_lpidr_re + or rf1_lratcfg_re or rf1_lratps_re or rf1_mas0_re + or rf1_mas0_mas1_re or rf1_mas1_re or rf1_mas2_re + or rf1_mas2u_re or rf1_mas3_re or rf1_mas4_re + or rf1_mas5_re or rf1_mas5_mas6_re or rf1_mas6_re + or rf1_mas7_re or rf1_mas7_mas3_re or rf1_mas8_re + or rf1_mas8_mas1_re or rf1_mmucfg_re or rf1_mmucr0_re + or rf1_mmucr1_re or rf1_mmucr2_re or rf1_mmucr3_re + or rf1_mmucsr0_re or rf1_pid_re or rf1_ppr32_re + or rf1_tlb0cfg_re or rf1_tlb0ps_re or rf1_xucr2_re + or rf1_xudbg0_re or rf1_xudbg1_re or rf1_xudbg2_re )); + +mark_unused(rf1_instr(6 to 10)); +mark_unused(rf1_instr(31)); + +-- Latch Instances +slowspr_ctr_gen : for t in 0 to threads-1 generate +slowspr_ctr_latch : tri_rlmreg_p + generic map (width => slowspr_ctr_q(t)'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_sspr_ctr_act(t), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(slowspr_ctr_offset+slowspr_ctr_q(t)'length*t to slowspr_ctr_offset+slowspr_ctr_q(t)'length*(t+1)-1), + scout => sov(slowspr_ctr_offset+slowspr_ctr_q(t)'length*t to slowspr_ctr_offset+slowspr_ctr_q(t)'length*(t+1)-1), + din => slowspr_ctr_d(t), + dout => slowspr_ctr_q(t)); +end generate; +spr_xucr0_ssdly_latch : tri_rlmreg_p + generic map (width => spr_xucr0_ssdly_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(spr_xucr0_ssdly_offset to spr_xucr0_ssdly_offset + spr_xucr0_ssdly_q'length-1), + scout => sov(spr_xucr0_ssdly_offset to spr_xucr0_ssdly_offset + spr_xucr0_ssdly_q'length-1), + din => spr_dec_spr_xucr0_ssdly, + dout => spr_xucr0_ssdly_q); +ex1_is_slowspr_wr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_slowspr_wr_offset), + scout => sov(ex1_is_slowspr_wr_offset), + din => rf1_is_slowspr_wr, + dout => ex1_is_slowspr_wr_q); +ex1_is_slowspr_rd_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_slowspr_rd_offset), + scout => sov(ex1_is_slowspr_rd_offset), + din => rf1_is_slowspr_rd, + dout => ex1_is_slowspr_rd_q); +slowspr_hole_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(slowspr_hole_offset), + scout => sov(slowspr_hole_offset), + din => slowspr_hole_d, + dout => slowspr_hole_q); + +siv(0 to siv'right) <= sov(1 to siv'right) & scan_in; +scan_out <= sov(0); + +end architecture xuq_dec_sspr; diff --git a/rel/src/vhdl/work/xuq_eccchk.vhdl b/rel/src/vhdl/work/xuq_eccchk.vhdl new file mode 100644 index 0000000..8316de3 --- /dev/null +++ b/rel/src/vhdl/work/xuq_eccchk.vhdl @@ -0,0 +1,284 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XU ECC Check Macro +-- +library ieee,ibm,support; +use ieee.std_logic_1164.all; +use ibm.std_ulogic_function_support.all; +use work.xuq_pkg.all; + +entity xuq_eccchk is +generic( + regsize : integer := 32); +port( + din : in std_ulogic_vector(0 to regsize-1); + EnCorr : in std_ulogic; + NSyn : in std_ulogic_vector(0 to 8-(64/regsize)); + Corrd : out std_ulogic_vector(0 to regsize-1); + SBE : out std_ulogic; + UE : out std_ulogic + ); + +-- synopsys translate_off +-- synopsys translate_on + +end xuq_eccchk; +architecture xuq_eccchk of xuq_eccchk is +begin +ecc64 : if regsize = 64 generate + + signal Syn : std_ulogic_vector(0 to 7); -- syndrome bits inverted + signal DcdD : std_ulogic_vector(0 to 71); -- decode data bits + signal Synzero : std_ulogic; + signal SBE_int : std_ulogic; + signal A0to1 : std_ulogic_vector(0 to 3); + signal A2to3 : std_ulogic_vector(0 to 3); + signal A4to5 : std_ulogic_vector(0 to 3); + signal A6to7 : std_ulogic_vector(0 to 2); + + begin + + -- ==================================================================== + -- 64 Data Bits, 8 Check bits + -- Single bit error correction, Double bit error detection + -- ==================================================================== + -- ECC Matrix Description + -- ==================================================================== + -- Syn 0 111011010011101001100101101101001100101101001011001101001110100110000000 + -- Syn 1 110110101011010101010101011010101010101010101010101010101101010101000000 + -- Syn 2 101101100110110011001100110110011001100110011001100110011011001100100000 + -- Syn 3 011100011110001111000011110001111000011110000111100001111000111100010000 + -- Syn 4 000011111110000000111111110000000111111110000000011111111000000000001000 + -- Syn 5 000000000001111111111111110000000000000001111111111111111000000000000100 + -- Syn 6 000000000000000000000000001111111111111111111111111111111000000000000010 + -- Syn 7 000000000000000000000000000000000000000000000000000000000111111100000001 + + Syn <= not NSyn(0 to 7); + + A0to1(0) <= not (NSyn(0) and NSyn(1) and EnCorr); + A0to1(1) <= not (NSyn(0) and Syn(1) and EnCorr); + A0to1(2) <= not ( Syn(0) and NSyn(1) and EnCorr); + A0to1(3) <= not ( Syn(0) and Syn(1) and EnCorr); + + A2to3(0) <= not (NSyn(2) and NSyn(3)); + A2to3(1) <= not (NSyn(2) and Syn(3)); + A2to3(2) <= not ( Syn(2) and NSyn(3)); + A2to3(3) <= not ( Syn(2) and Syn(3)); + + A4to5(0) <= not (NSyn(4) and NSyn(5)); + A4to5(1) <= not (NSyn(4) and Syn(5)); + A4to5(2) <= not ( Syn(4) and NSyn(5)); + A4to5(3) <= not ( Syn(4) and Syn(5)); + + A6to7(0) <= not (NSyn(6) and NSyn(7)); + A6to7(1) <= not (NSyn(6) and Syn(7)); + A6to7(2) <= not ( Syn(6) and NSyn(7)); + + DcdD( 0) <= not (A0to1(3) or A2to3(2) or A4to5(0) or A6to7(0)); -- 11 10 00 00 + DcdD( 1) <= not (A0to1(3) or A2to3(1) or A4to5(0) or A6to7(0)); -- 11 01 00 00 + DcdD( 2) <= not (A0to1(2) or A2to3(3) or A4to5(0) or A6to7(0)); -- 10 11 00 00 + DcdD( 3) <= not (A0to1(1) or A2to3(3) or A4to5(0) or A6to7(0)); -- 01 11 00 00 + DcdD( 4) <= not (A0to1(3) or A2to3(0) or A4to5(2) or A6to7(0)); -- 11 00 10 00 + DcdD( 5) <= not (A0to1(2) or A2to3(2) or A4to5(2) or A6to7(0)); -- 10 10 10 00 + DcdD( 6) <= not (A0to1(1) or A2to3(2) or A4to5(2) or A6to7(0)); -- 01 10 10 00 + DcdD( 7) <= not (A0to1(2) or A2to3(1) or A4to5(2) or A6to7(0)); -- 10 01 10 00 + DcdD( 8) <= not (A0to1(1) or A2to3(1) or A4to5(2) or A6to7(0)); -- 01 01 10 00 + DcdD( 9) <= not (A0to1(0) or A2to3(3) or A4to5(2) or A6to7(0)); -- 00 11 10 00 + DcdD(10) <= not (A0to1(3) or A2to3(3) or A4to5(2) or A6to7(0)); -- 11 11 10 00 + DcdD(11) <= not (A0to1(3) or A2to3(0) or A4to5(1) or A6to7(0)); -- 11 00 01 00 + DcdD(12) <= not (A0to1(2) or A2to3(2) or A4to5(1) or A6to7(0)); -- 10 10 01 00 + DcdD(13) <= not (A0to1(1) or A2to3(2) or A4to5(1) or A6to7(0)); -- 01 10 01 00 + DcdD(14) <= not (A0to1(2) or A2to3(1) or A4to5(1) or A6to7(0)); -- 10 01 01 00 + DcdD(15) <= not (A0to1(1) or A2to3(1) or A4to5(1) or A6to7(0)); -- 01 01 01 00 + DcdD(16) <= not (A0to1(0) or A2to3(3) or A4to5(1) or A6to7(0)); -- 00 11 01 00 + DcdD(17) <= not (A0to1(3) or A2to3(3) or A4to5(1) or A6to7(0)); -- 11 11 01 00 + DcdD(18) <= not (A0to1(2) or A2to3(0) or A4to5(3) or A6to7(0)); -- 10 00 11 00 + DcdD(19) <= not (A0to1(1) or A2to3(0) or A4to5(3) or A6to7(0)); -- 01 00 11 00 + DcdD(20) <= not (A0to1(0) or A2to3(2) or A4to5(3) or A6to7(0)); -- 00 10 11 00 + DcdD(21) <= not (A0to1(3) or A2to3(2) or A4to5(3) or A6to7(0)); -- 11 10 11 00 + DcdD(22) <= not (A0to1(0) or A2to3(1) or A4to5(3) or A6to7(0)); -- 00 01 11 00 + DcdD(23) <= not (A0to1(3) or A2to3(1) or A4to5(3) or A6to7(0)); -- 11 01 11 00 + DcdD(24) <= not (A0to1(2) or A2to3(3) or A4to5(3) or A6to7(0)); -- 10 11 11 00 + DcdD(25) <= not (A0to1(1) or A2to3(3) or A4to5(3) or A6to7(0)); -- 01 11 11 00 + DcdD(26) <= not (A0to1(3) or A2to3(0) or A4to5(0) or A6to7(2)); -- 11 00 00 10 + DcdD(27) <= not (A0to1(2) or A2to3(2) or A4to5(0) or A6to7(2)); -- 10 10 00 10 + DcdD(28) <= not (A0to1(1) or A2to3(2) or A4to5(0) or A6to7(2)); -- 01 10 00 10 + DcdD(29) <= not (A0to1(2) or A2to3(1) or A4to5(0) or A6to7(2)); -- 10 01 00 10 + DcdD(30) <= not (A0to1(1) or A2to3(1) or A4to5(0) or A6to7(2)); -- 01 01 00 10 + DcdD(31) <= not (A0to1(0) or A2to3(3) or A4to5(0) or A6to7(2)); -- 00 11 00 10 + DcdD(32) <= not (A0to1(3) or A2to3(3) or A4to5(0) or A6to7(2)); -- 11 11 00 10 + DcdD(33) <= not (A0to1(2) or A2to3(0) or A4to5(2) or A6to7(2)); -- 10 00 10 10 + DcdD(34) <= not (A0to1(1) or A2to3(0) or A4to5(2) or A6to7(2)); -- 01 00 10 10 + DcdD(35) <= not (A0to1(0) or A2to3(2) or A4to5(2) or A6to7(2)); -- 00 10 10 10 + DcdD(36) <= not (A0to1(3) or A2to3(2) or A4to5(2) or A6to7(2)); -- 11 10 10 10 + DcdD(37) <= not (A0to1(0) or A2to3(1) or A4to5(2) or A6to7(2)); -- 00 01 10 10 + DcdD(38) <= not (A0to1(3) or A2to3(1) or A4to5(2) or A6to7(2)); -- 11 01 10 10 + DcdD(39) <= not (A0to1(2) or A2to3(3) or A4to5(2) or A6to7(2)); -- 10 11 10 10 + DcdD(40) <= not (A0to1(1) or A2to3(3) or A4to5(2) or A6to7(2)); -- 01 11 10 10 + DcdD(41) <= not (A0to1(2) or A2to3(0) or A4to5(1) or A6to7(2)); -- 10 00 01 10 + DcdD(42) <= not (A0to1(1) or A2to3(0) or A4to5(1) or A6to7(2)); -- 01 00 01 10 + DcdD(43) <= not (A0to1(0) or A2to3(2) or A4to5(1) or A6to7(2)); -- 00 10 01 10 + DcdD(44) <= not (A0to1(3) or A2to3(2) or A4to5(1) or A6to7(2)); -- 11 10 01 10 + DcdD(45) <= not (A0to1(0) or A2to3(1) or A4to5(1) or A6to7(2)); -- 00 01 01 10 + DcdD(46) <= not (A0to1(3) or A2to3(1) or A4to5(1) or A6to7(2)); -- 11 01 01 10 + DcdD(47) <= not (A0to1(2) or A2to3(3) or A4to5(1) or A6to7(2)); -- 10 11 01 10 + DcdD(48) <= not (A0to1(1) or A2to3(3) or A4to5(1) or A6to7(2)); -- 01 11 01 10 + DcdD(49) <= not (A0to1(0) or A2to3(0) or A4to5(3) or A6to7(2)); -- 00 00 11 10 + DcdD(50) <= not (A0to1(3) or A2to3(0) or A4to5(3) or A6to7(2)); -- 11 00 11 10 + DcdD(51) <= not (A0to1(2) or A2to3(2) or A4to5(3) or A6to7(2)); -- 10 10 11 10 + DcdD(52) <= not (A0to1(1) or A2to3(2) or A4to5(3) or A6to7(2)); -- 01 10 11 10 + DcdD(53) <= not (A0to1(2) or A2to3(1) or A4to5(3) or A6to7(2)); -- 10 01 11 10 + DcdD(54) <= not (A0to1(1) or A2to3(1) or A4to5(3) or A6to7(2)); -- 01 01 11 10 + DcdD(55) <= not (A0to1(0) or A2to3(3) or A4to5(3) or A6to7(2)); -- 00 11 11 10 + DcdD(56) <= not (A0to1(3) or A2to3(3) or A4to5(3) or A6to7(2)); -- 11 11 11 10 + DcdD(57) <= not (A0to1(3) or A2to3(0) or A4to5(0) or A6to7(1)); -- 11 00 00 01 + DcdD(58) <= not (A0to1(2) or A2to3(2) or A4to5(0) or A6to7(1)); -- 10 10 00 01 + DcdD(59) <= not (A0to1(1) or A2to3(2) or A4to5(0) or A6to7(1)); -- 01 10 00 01 + DcdD(60) <= not (A0to1(2) or A2to3(1) or A4to5(0) or A6to7(1)); -- 10 01 00 01 + DcdD(61) <= not (A0to1(1) or A2to3(1) or A4to5(0) or A6to7(1)); -- 01 01 00 01 + DcdD(62) <= not (A0to1(0) or A2to3(3) or A4to5(0) or A6to7(1)); -- 00 11 00 01 + DcdD(63) <= not (A0to1(3) or A2to3(3) or A4to5(0) or A6to7(1)); -- 11 11 00 01 + DcdD(64) <= not (A0to1(2) or A2to3(0) or A4to5(0) or A6to7(0)); -- 10 00 00 00 + DcdD(65) <= not (A0to1(1) or A2to3(0) or A4to5(0) or A6to7(0)); -- 01 00 00 00 + DcdD(66) <= not (A0to1(0) or A2to3(2) or A4to5(0) or A6to7(0)); -- 00 10 00 00 + DcdD(67) <= not (A0to1(0) or A2to3(1) or A4to5(0) or A6to7(0)); -- 00 01 00 00 + DcdD(68) <= not (A0to1(0) or A2to3(0) or A4to5(2) or A6to7(0)); -- 00 00 10 00 + DcdD(69) <= not (A0to1(0) or A2to3(0) or A4to5(1) or A6to7(0)); -- 00 00 01 00 + DcdD(70) <= not (A0to1(0) or A2to3(0) or A4to5(0) or A6to7(2)); -- 00 00 00 10 + DcdD(71) <= not (A0to1(0) or A2to3(0) or A4to5(0) or A6to7(1)); -- 00 00 00 01 + Synzero <= not (A0to1(0) or A2to3(0) or A4to5(0) or A6to7(0)); -- 00 00 00 00 + + CorrD(0 to 63) <= Din(0 to 63) xor DcdD(0 to 63); + + SBE_int <= '1' when DcdD(0 to 71) /= (0 to 71=>'0') else '0'; + SBE <= SBE_int; + UE <= (not SBE_int) and ((not Synzero)) and EnCorr; + +end generate; +ecc32 : if regsize = 32 generate + + signal Syn : std_ulogic_vector(0 to 6); -- syndrome bits inverted + signal DcdD : std_ulogic_vector(0 to 38); -- decode data bits + signal Synzero : std_ulogic; + signal SBE_int : std_ulogic; + signal A0to1 : std_ulogic_vector(0 to 3); + signal A2to3 : std_ulogic_vector(0 to 3); + signal A4to6 : std_ulogic_vector(0 to 7); + + begin + + -- ==================================================================== + -- 32 Data Bits, 7 Check bits + -- Single bit error correction, Double bit error detection + -- ==================================================================== + -- ECC Matrix Description + -- ==================================================================== + -- Syn 0 111011010011101001100101101101001000000 + -- Syn 1 110110101011010101010101011010100100000 + -- Syn 2 101101100110110011001100110110010010000 + -- Syn 3 011100011110001111000011110001110001000 + -- Syn 4 000011111110000000111111110000000000100 + -- Syn 5 000000000001111111111111110000000000010 + -- Syn 6 000000000000000000000000001111110000001 + + Syn <= not NSyn(0 to 6); + + A0to1(0) <= not (NSyn(0) and NSyn(1) and EnCorr); + A0to1(1) <= not (NSyn(0) and Syn(1) and EnCorr); + A0to1(2) <= not ( Syn(0) and NSyn(1) and EnCorr); + A0to1(3) <= not ( Syn(0) and Syn(1) and EnCorr); + + A2to3(0) <= not (NSyn(2) and NSyn(3)); + A2to3(1) <= not (NSyn(2) and Syn(3)); + A2to3(2) <= not ( Syn(2) and NSyn(3)); + A2to3(3) <= not ( Syn(2) and Syn(3)); + + A4to6(0) <= not (NSyn(4) and NSyn(5) and NSyn(6)); + A4to6(1) <= not (NSyn(4) and NSyn(5) and Syn(6)); + A4to6(2) <= not (NSyn(4) and Syn(5) and NSyn(6)); + A4to6(3) <= not (NSyn(4) and Syn(5) and Syn(6)); + A4to6(4) <= not ( Syn(4) and NSyn(5) and NSyn(6)); + A4to6(5) <= not ( Syn(4) and NSyn(5) and Syn(6)); + A4to6(6) <= not ( Syn(4) and Syn(5) and NSyn(6)); + A4to6(7) <= not ( Syn(4) and Syn(5) and Syn(6)); + + DcdD( 0) <= not (A0to1(3) or A2to3(2) or A4to6(0)); -- 11 10 000 + DcdD( 1) <= not (A0to1(3) or A2to3(1) or A4to6(0)); -- 11 01 000 + DcdD( 2) <= not (A0to1(2) or A2to3(3) or A4to6(0)); -- 10 11 000 + DcdD( 3) <= not (A0to1(1) or A2to3(3) or A4to6(0)); -- 01 11 000 + DcdD( 4) <= not (A0to1(3) or A2to3(0) or A4to6(4)); -- 11 00 100 + DcdD( 5) <= not (A0to1(2) or A2to3(2) or A4to6(4)); -- 10 10 100 + DcdD( 6) <= not (A0to1(1) or A2to3(2) or A4to6(4)); -- 01 10 100 + DcdD( 7) <= not (A0to1(2) or A2to3(1) or A4to6(4)); -- 10 01 100 + DcdD( 8) <= not (A0to1(1) or A2to3(1) or A4to6(4)); -- 01 01 100 + DcdD( 9) <= not (A0to1(0) or A2to3(3) or A4to6(4)); -- 00 11 100 + DcdD(10) <= not (A0to1(3) or A2to3(3) or A4to6(4)); -- 11 11 100 + DcdD(11) <= not (A0to1(3) or A2to3(0) or A4to6(2)); -- 11 00 010 + DcdD(12) <= not (A0to1(2) or A2to3(2) or A4to6(2)); -- 10 10 010 + DcdD(13) <= not (A0to1(1) or A2to3(2) or A4to6(2)); -- 01 10 010 + DcdD(14) <= not (A0to1(2) or A2to3(1) or A4to6(2)); -- 10 01 010 + DcdD(15) <= not (A0to1(1) or A2to3(1) or A4to6(2)); -- 01 01 010 + DcdD(16) <= not (A0to1(0) or A2to3(3) or A4to6(2)); -- 00 11 010 + DcdD(17) <= not (A0to1(3) or A2to3(3) or A4to6(2)); -- 11 11 010 + DcdD(18) <= not (A0to1(2) or A2to3(0) or A4to6(6)); -- 10 00 110 + DcdD(19) <= not (A0to1(1) or A2to3(0) or A4to6(6)); -- 01 00 110 + DcdD(20) <= not (A0to1(0) or A2to3(2) or A4to6(6)); -- 00 10 110 + DcdD(21) <= not (A0to1(3) or A2to3(2) or A4to6(6)); -- 11 10 110 + DcdD(22) <= not (A0to1(0) or A2to3(1) or A4to6(6)); -- 00 01 110 + DcdD(23) <= not (A0to1(3) or A2to3(1) or A4to6(6)); -- 11 01 110 + DcdD(24) <= not (A0to1(2) or A2to3(3) or A4to6(6)); -- 10 11 110 + DcdD(25) <= not (A0to1(1) or A2to3(3) or A4to6(6)); -- 01 11 110 + DcdD(26) <= not (A0to1(3) or A2to3(0) or A4to6(1)); -- 11 00 001 + DcdD(27) <= not (A0to1(2) or A2to3(2) or A4to6(1)); -- 10 10 001 + DcdD(28) <= not (A0to1(1) or A2to3(2) or A4to6(1)); -- 01 10 001 + DcdD(29) <= not (A0to1(2) or A2to3(1) or A4to6(1)); -- 10 01 001 + DcdD(30) <= not (A0to1(1) or A2to3(1) or A4to6(1)); -- 01 01 001 + DcdD(31) <= not (A0to1(0) or A2to3(3) or A4to6(1)); -- 00 11 001 + DcdD(32) <= not (A0to1(2) or A2to3(0) or A4to6(0)); -- 10 00 000 + DcdD(33) <= not (A0to1(1) or A2to3(0) or A4to6(0)); -- 01 00 000 + DcdD(34) <= not (A0to1(0) or A2to3(2) or A4to6(0)); -- 00 10 000 + DcdD(35) <= not (A0to1(0) or A2to3(1) or A4to6(0)); -- 00 01 000 + DcdD(36) <= not (A0to1(0) or A2to3(0) or A4to6(4)); -- 00 00 100 + DcdD(37) <= not (A0to1(0) or A2to3(0) or A4to6(2)); -- 00 00 010 + DcdD(38) <= not (A0to1(0) or A2to3(0) or A4to6(1)); -- 00 00 001 + Synzero <= not (A0to1(0) or A2to3(0) or A4to6(0)); -- 00 00 000 + + CorrD(0 to 31) <= Din(0 to 31) xor DcdD(0 to 31); + + SBE_int <= '1' when DcdD(0 to 38) /= (0 to 38=>'0') else '0'; + SBE <= SBE_int; + UE <= (not SBE_int) and ((not Synzero)) and EnCorr; + + mark_unused(A4to6(3)); + mark_unused(A4to6(5)); + mark_unused(A4to6(7)); + +end generate; + +end xuq_eccchk; diff --git a/rel/src/vhdl/work/xuq_eccgen.vhdl b/rel/src/vhdl/work/xuq_eccgen.vhdl new file mode 100644 index 0000000..7a9b3e4 --- /dev/null +++ b/rel/src/vhdl/work/xuq_eccgen.vhdl @@ -0,0 +1,154 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XU ECC Generation Macro +-- +library ieee,ibm,support; +use ieee.std_logic_1164.all; +use ibm.std_ulogic_function_support.all; + +entity xuq_eccgen is +generic( + regsize : integer := 64); +port( + din : in std_ulogic_vector(0 to regsize+8-(64/regsize)); + Syn : out std_ulogic_vector(0 to 8-(64/regsize)) + ); + +-- synopsys translate_off +-- synopsys translate_on + +end xuq_eccgen; +architecture xuq_eccgen of xuq_eccgen is +begin +ecc64 : if regsize = 64 generate + + signal e : std_ulogic_vector(0 to 71); -- syndrome bits inverted + signal l1term : std_ulogic_vector(0 to 22); + + begin + + -- ==================================================================== + -- 64 data bits, 8 check bits + -- single bit error correction, double bit error detection + -- ==================================================================== + -- ecc matrix description + -- ==================================================================== + -- syn 0 111011010011101001100101101101001100101101001011001101001110100110000000 + -- syn 1 110110101011010101010101011010101010101010101010101010101101010101000000 + -- syn 2 101101100110110011001100110110011001100110011001100110011011001100100000 + -- syn 3 011100011110001111000011110001111000011110000111100001111000111100010000 + -- syn 4 000011111110000000111111110000000111111110000000011111111000000000001000 + -- syn 5 000000000001111111111111110000000000000001111111111111111000000000000100 + -- syn 6 000000000000000000000000001111111111111111111111111111111000000000000010 + -- syn 7 000000000000000000000000000000000000000000000000000000000111111100000001 + + e(0 to 71) <= din(0 to 71); + + l1term(0) <= parity_map(e(0)&e(10)&e(17)&e(21)&e(32)&e(36)&e(44)&e(56)); + l1term(1) <= parity_map(e(22)&e(23)&e(24)&e(25)&e(53)&e(54)&e(55)&e(56)); + l1term(2) <= parity_map(e(1)&e(4)&e(11)&e(23)&e(26)&e(38)&e(46)&e(50)); + l1term(3) <= parity_map(e(2)&e(5)&e(12)&e(24)&e(27)&e(39)&e(47)&e(51)); + l1term(4) <= parity_map(e(3)&e(6)&e(13)&e(25)&e(28)&e(40)&e(48)&e(52)); + l1term(5) <= parity_map(e(7)&e(8)&e(9)&e(10)&e(37)&e(38)&e(39)&e(40)); + l1term(6) <= parity_map(e(14)&e(15)&e(16)&e(17)&e(45)&e(46)&e(47)&e(48)); + l1term(7) <= parity_map(e(18)&e(19)&e(20)&e(21)&e(49)&e(50)&e(51)&e(52)); + l1term(8) <= parity_map(e(7)&e(14)&e(18)&e(29)&e(33)&e(41)&e(53)&e(57)); + l1term(9) <= parity_map(e(58)&e(60)&e(63)&e(64)); + l1term(10) <= parity_map(e(8)&e(15)&e(19)&e(30)&e(34)&e(42)&e(54)&e(57)); + l1term(11) <= parity_map(e(59)&e(61)&e(63)&e(65)); + l1term(12) <= parity_map(e(9)&e(16)&e(20)&e(31)&e(35)&e(43)&e(55)&e(58)); + l1term(13) <= parity_map(e(59)&e(62)&e(63)&e(66)); + l1term(14) <= parity_map(e(1)&e(2)&e(3)&e(29)&e(30)&e(31)&e(32)&e(60)); + l1term(15) <= parity_map(e(61)&e(62)&e(63)&e(67)); + l1term(16) <= parity_map(e(4)&e(5)&e(6)&e(33)&e(34)&e(35)&e(36)&e(68)); + l1term(17) <= parity_map(e(11)&e(12)&e(13)&e(41)&e(42)&e(43)&e(44)&e(69)); + l1term(18) <= parity_map(e(26)&e(27)&e(28)&e(29)&e(30)&e(31)&e(32)&e(33)); + l1term(19) <= parity_map(e(34)&e(35)&e(36)&e(37)&e(38)&e(39)&e(40)&e(41)); + l1term(20) <= parity_map(e(42)&e(43)&e(44)&e(45)&e(46)&e(47)&e(48)&e(49)); + l1term(21) <= parity_map(e(50)&e(51)&e(52)&e(53)&e(54)&e(55)&e(56)&e(70)); + l1term(22) <= parity_map(e(57)&e(58)&e(59)&e(60)&e(61)&e(62)&e(63)&e(71)); + Syn(0) <= parity_map(l1term(0)&l1term(2)&l1term(3)&l1term(8)&l1term(9)); + Syn(1) <= parity_map(l1term(0)&l1term(2)&l1term(4)&l1term(10)&l1term(11)); + Syn(2) <= parity_map(l1term(0)&l1term(3)&l1term(4)&l1term(12)&l1term(13)); + Syn(3) <= parity_map(l1term(1)&l1term(5)&l1term(6)&l1term(14)&l1term(15)); + Syn(4) <= parity_map(l1term(1)&l1term(5)&l1term(7)&l1term(16)); + Syn(5) <= parity_map(l1term(1)&l1term(6)&l1term(7)&l1term(17)); + Syn(6) <= parity_map(l1term(18)&l1term(19)&l1term(20)&l1term(21)); + Syn(7) <= l1term(22); + +end generate; +ecc32 : if regsize = 32 generate + + signal e : std_ulogic_vector(0 to 38); -- syndrome bits inverted + signal l1term : std_ulogic_vector(0 to 13); + + begin + + -- ==================================================================== + -- 32 Data Bits, 7 Check bits + -- Single bit error correction, Double bit error detection + -- ==================================================================== + -- ECC Matrix Description + -- ==================================================================== + -- Syn 0 111011010011101001100101101101001000000 + -- Syn 1 110110101011010101010101011010100100000 + -- Syn 2 101101100110110011001100110110010010000 + -- Syn 3 011100011110001111000011110001110001000 + -- Syn 4 000011111110000000111111110000000000100 + -- Syn 5 000000000001111111111111110000000000010 + -- Syn 6 000000000000000000000000001111110000001 + + e(0 to 38) <= din(0 to 38); + + l1term(0) <= parity_map(e(0)&e(1)&e(4)&e(10)&e(11)&e(17)&e(21)&e(23)); + l1term(1) <= parity_map(e(2)&e(3)&e(9)&e(10)&e(16)&e(17)&e(24)&e(25)); + l1term(2) <= parity_map(e(18)&e(19)&e(20)&e(21)&e(22)&e(23)&e(24)&e(25)); + l1term(3) <= parity_map(e(2)&e(5)&e(7)&e(12)&e(14)&e(18)&e(24)&e(26)); + l1term(4) <= parity_map(e(27)&e(29)&e(32)); + l1term(5) <= parity_map(e(3)&e(6)&e(8)&e(13)&e(15)&e(19)&e(25)&e(26)); + l1term(6) <= parity_map(e(28)&e(30)&e(33)); + l1term(7) <= parity_map(e(0)&e(5)&e(6)&e(12)&e(13)&e(20)&e(21)&e(27)); + l1term(8) <= parity_map(e(28)&e(31)&e(34)); + l1term(9) <= parity_map(e(1)&e(7)&e(8)&e(14)&e(15)&e(22)&e(23)&e(29)); + l1term(10) <= parity_map(e(30)&e(31)&e(35)); + l1term(11) <= parity_map(e(4)&e(5)&e(6)&e(7)&e(8)&e(9)&e(10)&e(36)); + l1term(12) <= parity_map(e(11)&e(12)&e(13)&e(14)&e(15)&e(16)&e(17)&e(37)); + l1term(13) <= parity_map(e(26)&e(27)&e(28)&e(29)&e(30)&e(31)&e(38)); + Syn(0) <= parity_map(l1term(0)&l1term(3)&l1term(4)); + Syn(1) <= parity_map(l1term(0)&l1term(5)&l1term(6)); + Syn(2) <= parity_map(l1term(1)&l1term(7)&l1term(8)); + Syn(3) <= parity_map(l1term(1)&l1term(9)&l1term(10)); + Syn(4) <= parity_map(l1term(2)&l1term(11)); + Syn(5) <= parity_map(l1term(2)&l1term(12)); + Syn(6) <= l1term(13); + +end generate; + +end xuq_eccgen; + diff --git a/rel/src/vhdl/work/xuq_fxu_a.vhdl b/rel/src/vhdl/work/xuq_fxu_a.vhdl new file mode 100644 index 0000000..7db8127 --- /dev/null +++ b/rel/src/vhdl/work/xuq_fxu_a.vhdl @@ -0,0 +1,818 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: xuq_fxu_a_A Top +-- +LIBRARY ieee; USE ieee.std_logic_1164.all; +LIBRARY support; + USE support.power_logic_pkg.all; +LIBRARY tri; USE tri.tri_latches_pkg.all; +LIBRARY work; USE work.xuq_pkg.mark_unused; + +entity xuq_fxu_a is + generic( + expand_type : integer := 2; + threads : integer := 4; + eff_ifar : integer := 62; + regmode : integer := 6; + regsize : integer := 64; + a2mode : integer := 1; + hvmode : integer := 1; + real_data_add : integer := 42); + port( + --------------------------------------------------------------------- + -- Clocks & Power + --------------------------------------------------------------------- + nclk : in clk_logic; + vdd : inout power_logic; + gnd : inout power_logic; + vcs : inout power_logic; + + --------------------------------------------------------------------- + -- Pervasive + --------------------------------------------------------------------- + an_ac_scan_dis_dc_b : in std_ulogic; + func_scan_in : in std_ulogic_vector(14 to 14); + func_scan_out : out std_ulogic_vector(14 to 14); + abst_scan_in : in std_ulogic; + abst_scan_out : out std_ulogic; + pc_xu_abist_raddr_0 : in std_ulogic_vector(2 to 9); + pc_xu_abist_raddr_1 : in std_ulogic_vector(2 to 9); + pc_xu_abist_grf_renb_0 : in std_ulogic; + pc_xu_abist_grf_renb_1 : in std_ulogic; + pc_xu_abist_ena_dc : in std_ulogic; + pc_xu_abist_waddr_0 : in std_ulogic_vector(2 to 9); + pc_xu_abist_waddr_1 : in std_ulogic_vector(2 to 9); + pc_xu_abist_grf_wenb_0 : in std_ulogic; + pc_xu_abist_grf_wenb_1 : in std_ulogic; + pc_xu_abist_di_0 : in std_ulogic_vector(0 to 3); + pc_xu_abist_di_1 : in std_ulogic_vector(0 to 3); + pc_xu_abist_wl144_comp_ena : in std_ulogic; + pc_xu_abist_raw_dc_b : in std_ulogic; + pc_xu_ccflush_dc : in std_ulogic; + bo_enable_2 : in std_ulogic; -- general bolt-on enable, probably DC + pc_xu_bo_reset : in std_ulogic; -- execute sticky bit decode + pc_xu_bo_unload : in std_ulogic; + pc_xu_bo_load : in std_ulogic; + pc_xu_bo_shdata : in std_ulogic; -- shift data for timing write + pc_xu_bo_select : in std_ulogic_vector(0 to 1); -- select for mask and hier writes + xu_pc_bo_fail : out std_ulogic_vector(0 to 1); -- fail/no-fix reg + xu_pc_bo_diagout : out std_ulogic_vector(0 to 1); + clkoff_dc_b : in std_ulogic; + d_mode_dc : in std_ulogic; + delay_lclkr_dc : in std_ulogic_vector(4 to 4); + mpw1_dc_b : in std_ulogic_vector(4 to 4); + mpw2_dc_b : in std_ulogic; + an_ac_scan_diag_dc : in std_ulogic; + an_ac_lbist_ary_wrt_thru_dc : in std_ulogic; + scan_dis_dc_b : in std_ulogic; + sg_2 : in std_ulogic_vector(0 to 0); + fce_2 : in std_ulogic_vector(0 to 0); + func_sl_thold_2 : in std_ulogic_vector(0 to 0); + func_nsl_thold_2 : in std_ulogic; + abst_sl_thold_2 : in std_ulogic; + time_sl_thold_2 : in std_ulogic; + gptr_sl_thold_2 : in std_ulogic; + bolt_sl_thold_2 : in std_ulogic; + ary_nsl_thold_2 : in std_ulogic; + time_scan_in : in std_ulogic; + time_scan_out : out std_ulogic; + gptr_scan_in : in std_ulogic; + gptr_scan_out : out std_ulogic; + + --------------------------------------------------------------------- + -- Interface with IU + --------------------------------------------------------------------- + iu_xu_is2_vld : in std_ulogic; + iu_xu_is2_ifar : in std_ulogic_vector(62-eff_ifar to 61); + iu_xu_is2_tid : in std_ulogic_vector(0 to threads-1); + iu_xu_is2_instr : in std_ulogic_vector(0 to 31); + iu_xu_is2_ta_vld : in std_ulogic; + iu_xu_is2_ta : in std_ulogic_vector(0 to 5); + iu_xu_is2_s1_vld : in std_ulogic; + iu_xu_is2_s1 : in std_ulogic_vector(0 to 5); + iu_xu_is2_s2_vld : in std_ulogic; + iu_xu_is2_s2 : in std_ulogic_vector(0 to 5); + iu_xu_is2_s3_vld : in std_ulogic; + iu_xu_is2_s3 : in std_ulogic_vector(0 to 5); + iu_xu_is2_axu_ld_or_st : in std_ulogic; + iu_xu_is2_axu_store : in std_ulogic; + iu_xu_is2_axu_ldst_size : in std_ulogic_vector(0 to 5); + iu_xu_is2_axu_ldst_update : in std_ulogic; + iu_xu_is2_axu_ldst_forcealign : in std_ulogic; + iu_xu_is2_axu_ldst_forceexcept : in std_ulogic; + iu_xu_is2_axu_ldst_extpid : in std_ulogic; + iu_xu_is2_axu_ldst_indexed : in std_ulogic; + iu_xu_is2_axu_ldst_tag : in std_ulogic_vector(0 to 8); + iu_xu_is2_axu_mftgpr : in std_ulogic; + iu_xu_is2_axu_mffgpr : in std_ulogic; + iu_xu_is2_axu_movedp : in std_ulogic; + iu_xu_is2_axu_instr_type : in std_ulogic_vector(0 to 2); + iu_xu_is2_pred_update : in std_ulogic; + iu_xu_is2_pred_taken_cnt : in std_ulogic_vector(0 to 1); + iu_xu_is2_error : in std_ulogic_vector(0 to 2); + iu_xu_is2_match : in std_ulogic; + iu_xu_is2_is_ucode : in std_ulogic; + iu_xu_is2_ucode_vld : in std_ulogic; + iu_xu_is2_gshare : in std_ulogic_vector(0 to 3); + xu_iu_multdiv_done : out std_ulogic_vector(0 to threads-1); + xu_iu_membar_tid : out std_ulogic_vector(0 to threads-1); + + --------------------------------------------------------------------- + -- Interface with LSU + --------------------------------------------------------------------- + lsu_xu_ldq_barr_done : in std_ulogic_vector(0 to threads-1); + lsu_xu_barr_done : in std_ulogic_vector(0 to threads-1); + + --------------------------------------------------------------------- + -- Interface with FXU B + --------------------------------------------------------------------- + fxa_fxb_rf0_val : out std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_issued : out std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_ucode_val : out std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_act : out std_ulogic; + fxa_fxb_ex1_hold_ctr_flush : out std_ulogic; + fxa_fxb_rf0_instr : out std_ulogic_vector(0 to 31); + fxa_fxb_rf0_tid : out std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_ta_vld : out std_ulogic; + fxa_fxb_rf0_ta : out std_ulogic_vector(0 to 7); + fxa_fxb_rf0_error : out std_ulogic_vector(0 to 2); + fxa_fxb_rf0_match : out std_ulogic; + fxa_fxb_rf0_is_ucode : out std_ulogic; + fxa_fxb_rf0_gshare : out std_ulogic_vector(0 to 3); + fxa_fxb_rf0_ifar : out std_ulogic_vector(62-eff_ifar to 61); + fxa_fxb_rf0_s1_vld : out std_ulogic; + fxa_fxb_rf0_s1 : out std_ulogic_vector(0 to 7); + fxa_fxb_rf0_s2_vld : out std_ulogic; + fxa_fxb_rf0_s2 : out std_ulogic_vector(0 to 7); + fxa_fxb_rf0_s3_vld : out std_ulogic; + fxa_fxb_rf0_s3 : out std_ulogic_vector(0 to 7); + fxa_fxb_rf0_axu_instr_type : out std_ulogic_vector(0 to 2); + fxa_fxb_rf0_axu_ld_or_st : out std_ulogic; + fxa_fxb_rf0_axu_store : out std_ulogic; + fxa_fxb_rf0_axu_mftgpr : out std_ulogic; + fxa_fxb_rf0_axu_mffgpr : out std_ulogic; + fxa_fxb_rf0_axu_movedp : out std_ulogic; + fxa_fxb_rf0_axu_ldst_size : out std_ulogic_vector(0 to 5); + fxa_fxb_rf0_axu_ldst_update : out std_ulogic; + fxa_fxb_rf0_axu_ldst_forcealign : out std_ulogic; + fxa_fxb_rf0_axu_ldst_forceexcept : out std_ulogic; + fxa_fxb_rf0_axu_ldst_indexed : out std_ulogic; + fxa_fxb_rf0_axu_ldst_tag : out std_ulogic_vector(0 to 8); + fxa_fxb_rf0_pred_update : out std_ulogic; + fxa_fxb_rf0_pred_taken_cnt : out std_ulogic_vector(0 to 1); + fxa_fxb_rf0_mc_dep_chk_val : out std_ulogic_vector(0 to threads-1); + fxa_fxb_rf1_mul_val : out std_ulogic; + fxa_fxb_rf1_muldiv_coll : out std_ulogic; + fxa_fxb_rf1_div_val : out std_ulogic; + fxa_fxb_rf1_div_ctr : out std_ulogic_vector(0 to 7); + fxa_fxb_rf0_xu_epid_instr : out std_ulogic; + fxa_fxb_rf0_axu_is_extload : out std_ulogic; + fxa_fxb_rf0_axu_is_extstore : out std_ulogic; + fxa_fxb_rf0_spr_tid : out std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_cpl_tid : out std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_cpl_act : out std_ulogic; + fxa_fxb_rf0_is_mfocrf : out std_ulogic; + fxa_fxb_rf0_3src_instr : out std_ulogic; + fxa_fxb_rf0_gpr0_zero : out std_ulogic; + fxa_fxb_rf0_use_imm : out std_ulogic; + dec_cpl_ex3_mc_dep_chk_val : out std_ulogic_vector(0 to threads-1); + fxb_fxa_ex7_we0 : in std_ulogic; + fxb_fxa_ex7_wa0 : in std_ulogic_vector(0 to 7); + fxb_fxa_ex7_wd0 : in std_ulogic_vector(64-regsize to 63); + fxa_fxb_rf1_do0 : out std_ulogic_vector(64-regsize to 63); + fxa_fxb_rf1_do1 : out std_ulogic_vector(64-regsize to 63); + fxa_fxb_rf1_do2 : out std_ulogic_vector(64-regsize to 63); + fxb_fxa_ex6_clear_barrier : in std_ulogic_vector(0 to threads-1); + fxa_perf_muldiv_in_use : out std_ulogic; + + --------------------------------------------------------------------- + -- Flushes + --------------------------------------------------------------------- + xu_is2_flush : in std_ulogic_vector(0 to threads-1); + xu_rf0_flush : in std_ulogic_vector(0 to threads-1); + xu_rf1_flush : in std_ulogic_vector(0 to threads-1); + xu_ex1_flush : in std_ulogic_vector(0 to threads-1); + xu_ex2_flush : in std_ulogic_vector(0 to threads-1); + xu_ex3_flush : in std_ulogic_vector(0 to threads-1); + xu_ex4_flush : in std_ulogic_vector(0 to threads-1); + xu_ex5_flush : in std_ulogic_vector(0 to threads-1); + fxa_cpl_ex2_div_coll : out std_ulogic_vector(0 to threads-1); + cpl_fxa_ex5_set_barr : in std_ulogic_vector(0 to threads-1); + fxa_iu_set_barr_tid : out std_ulogic_vector(0 to threads-1); + spr_xucr4_div_barr_thres : in std_ulogic_vector(0 to 7); + + --------------------------------------------------------------------- + -- ICSWX + --------------------------------------------------------------------- + an_ac_back_inv : in std_ulogic; + an_ac_back_inv_addr : in std_ulogic_vector(62 to 63); + an_ac_back_inv_target_bit3 : in std_ulogic; + + --------------------------------------------------------------------- + -- Interface with SPR + --------------------------------------------------------------------- + dec_spr_rf0_instr : out std_ulogic_vector(0 to 31); + + --------------------------------------------------------------------- + -- Parity + --------------------------------------------------------------------- + pc_xu_inj_regfile_parity : in std_ulogic_vector(0 to 3); + xu_pc_err_regfile_parity : out std_ulogic_vector(0 to threads-1); + xu_pc_err_regfile_ue : out std_ulogic_vector(0 to 3); + gpr_cpl_ex3_regfile_err_det : out std_ulogic; + cpl_gpr_regfile_seq_beg : in std_ulogic; + gpr_cpl_regfile_seq_end : out std_ulogic; + + --------------------------------------------------------------------- + -- Interface with LSU + --------------------------------------------------------------------- + xu_lsu_rf0_derat_is_extload : out std_ulogic; + xu_lsu_rf0_derat_is_extstore : out std_ulogic; + xu_lsu_rf0_derat_val : out std_ulogic_vector(0 to threads-1); + lsu_xu_rel_wren : in std_ulogic; + lsu_xu_rel_ta_gpr : in std_ulogic_vector(0 to 7); + lsu_xu_rot_rel_data : in std_ulogic_vector(64-(2**regmode) to 63+(2**regmode)/8); + + spr_xucr0_clkg_ctl_b0 : in std_ulogic; + fxa_cpl_debug : out std_ulogic_vector(0 to 272) + ); + -- synopsys translate_off + + -- synopsys translate_on +end xuq_fxu_a; + +architecture xuq_fxu_a of xuq_fxu_a is + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + --------------------------------------------------------------------- + -- Pervasive Signals + --------------------------------------------------------------------- + signal func_sl_thold_1 : std_ulogic; + signal func_nsl_thold_1 : std_ulogic; + signal time_sl_thold_1 : std_ulogic; + signal gptr_sl_thold_1 : std_ulogic; + signal bolt_sl_thold_1 : std_ulogic; + signal sg_1 : std_ulogic; + signal fce_1 : std_ulogic_vector(0 to 1); + signal abst_sl_thold_1 : std_ulogic; + signal ary_nsl_thold_1 : std_ulogic; + signal func_sl_thold_0 : std_ulogic; + signal func_nsl_thold_0 : std_ulogic; + signal time_sl_thold_0 : std_ulogic; + signal gptr_sl_thold_0 : std_ulogic; + signal bolt_sl_thold_0 : std_ulogic; + signal sg_0 : std_ulogic; + signal fce_0 : std_ulogic_vector(0 to 1); + signal abst_sl_thold_0 : std_ulogic; + signal ary_nsl_thold_0 : std_ulogic; + signal func_sl_force : std_ulogic; + signal func_nsl_force : std_ulogic; + signal func_sl_thold_0_b : std_ulogic; + signal func_nsl_thold_0_b : std_ulogic; + signal func_scan_rpwr_in : std_ulogic_vector(14 to 14); + signal func_scan_rpwr_out : std_ulogic_vector(14 to 14); + signal func_scan_out_gate : std_ulogic_vector(14 to 14); + signal func_so_thold_0_b, so_force : std_ulogic; + + --------------------------------------------------------------------- + -- ABIST + --------------------------------------------------------------------- + signal abst_sl_thold_0_b : std_ulogic; + signal abst_sl_force : std_ulogic; + signal pc_xu_abist_raddr_0_q : std_ulogic_vector(2 to 9); + signal pc_xu_abist_raddr_1_q : std_ulogic_vector(2 to 9); + signal pc_xu_abist_grf_renb_0_q : std_ulogic; + signal pc_xu_abist_grf_renb_1_q : std_ulogic; + signal pc_xu_abist_waddr_0_q : std_ulogic_vector(2 to 9); + signal pc_xu_abist_waddr_1_q : std_ulogic_vector(2 to 9); + signal pc_xu_abist_grf_wenb_0_q : std_ulogic; + signal pc_xu_abist_grf_wenb_1_q : std_ulogic; + signal pc_xu_abist_di_0_q : std_ulogic_vector(0 to 3); + signal pc_xu_abist_di_1_q : std_ulogic_vector(0 to 3); + signal pc_xu_abist_wl144_comp_ena_q : std_ulogic; + signal slat_force : std_ulogic; + signal abst_slat_thold_b : std_ulogic; + signal abst_slat_d2clk : std_ulogic; + signal abst_slat_lclk : clk_logic; + signal abist_siv : std_ulogic_vector(0 to 45); + signal abist_sov : std_ulogic_vector(0 to 45); + signal abst_scan_in_q : std_ulogic; + signal abst_scan_out_int : std_ulogic; + signal abst_scan_out_q : std_ulogic; + signal abst_scan_in_2_q : std_ulogic; + signal abst_scan_out_2_q : std_ulogic; + + --------------------------------------------------------------------- + -- Scan Chain + --------------------------------------------------------------------- + signal siv_14 : std_ulogic_vector(0 to 1); + signal sov_14 : std_ulogic_vector(0 to 1); + + --------------------------------------------------------------------- + -- GPR Signals + --------------------------------------------------------------------- + signal dec_gpr_rf0_re0 : std_ulogic; + signal dec_gpr_rf0_re1 : std_ulogic; + signal dec_gpr_rf0_re2 : std_ulogic; + signal dec_gpr_rf0_ra0 : std_ulogic_vector(0 to 7); + signal dec_gpr_rf0_ra1 : std_ulogic_vector(0 to 7); + signal dec_gpr_rf0_ra2 : std_ulogic_vector(0 to 7); + signal dec_gpr_rel_ta_gpr : std_ulogic_vector(0 to 7); + signal dec_gpr_rel_wren : std_ulogic; + signal gpr_rel_data : std_ulogic_vector(64-regsize to 69+regsize/8); + signal gpr_data_out_0 : std_ulogic_vector(64-regsize to 69+regsize/8); + signal gpr_data_out_1 : std_ulogic_vector(64-regsize to 69+regsize/8); + signal gpr_data_out_2 : std_ulogic_vector(64-regsize to 69+regsize/8); + signal xu_div_coll_barr_done : std_ulogic_vector(0 to threads-1); + signal xu_div_barr_done : std_ulogic_vector(0 to threads-1); + signal gpr_debug : std_ulogic_vector(0 to 21); + signal dec_debug : std_ulogic_vector(0 to 175); + signal gpr_we1_debug : std_ulogic_vector(0 to 74); + +begin + + fxa_cpl_debug <= dec_debug & gpr_debug & (0 to 74=>'0'); + + gpr_we1_debug(0 to 65) <= gpr_rel_data(0 to 63) & dec_gpr_rel_wren & dec_gpr_rel_ta_gpr(0); + gpr_we1_debug(66 to 74) <= dec_gpr_rel_wren & dec_gpr_rel_ta_gpr; + + mark_unused(gpr_we1_debug); + + --------------------------------------------------------------------- + -- Clear Barrier + --------------------------------------------------------------------- + xu_iu_membar_tid <= lsu_xu_ldq_barr_done or xu_div_coll_barr_done; + + xu_iu_multdiv_done <= xu_div_barr_done or fxb_fxa_ex6_clear_barrier or lsu_xu_barr_done; + + --------------------------------------------------------------------- + -- ABIST latches + --------------------------------------------------------------------- + abist_reg: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 45, needs_sreset => 0) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => pc_xu_abist_ena_dc, + thold_b => abst_sl_thold_0_b, + sg => sg_0, + forcee => abst_sl_force, + delay_lclkr => delay_lclkr_dc(4), + mpw1_b => mpw1_dc_b(4), + mpw2_b => mpw2_dc_b, + d_mode => d_mode_dc, + scin => abist_siv(1 to 45), + scout => abist_sov(1 to 45), + din(0 to 7) => pc_xu_abist_raddr_0, + din(8 to 15) => pc_xu_abist_raddr_1, + din(16) => pc_xu_abist_grf_renb_0, + din(17) => pc_xu_abist_grf_renb_1, + din(18 to 25) => pc_xu_abist_waddr_0, + din(26 to 33) => pc_xu_abist_waddr_1, + din(34) => pc_xu_abist_grf_wenb_0, + din(35) => pc_xu_abist_grf_wenb_1, + din(36 to 39) => pc_xu_abist_di_0, + din(40 to 43) => pc_xu_abist_di_1, + din(44) => pc_xu_abist_wl144_comp_ena, + --------------------------------------------------------------------- + dout(0 to 7) => pc_xu_abist_raddr_0_q, + dout(8 to 15) => pc_xu_abist_raddr_1_q, + dout(16) => pc_xu_abist_grf_renb_0_q, + dout(17) => pc_xu_abist_grf_renb_1_q, + dout(18 to 25) => pc_xu_abist_waddr_0_q, + dout(26 to 33) => pc_xu_abist_waddr_1_q, + dout(34) => pc_xu_abist_grf_wenb_0_q, + dout(35) => pc_xu_abist_grf_wenb_1_q, + dout(36 to 39) => pc_xu_abist_di_0_q, + dout(40 to 43) => pc_xu_abist_di_1_q, + dout(44) => pc_xu_abist_wl144_comp_ena_q); + + slat_force <= sg_0; + abst_slat_thold_b <= NOT abst_sl_thold_0; + + perv_lcbs_abst: tri_lcbs + generic map (expand_type => expand_type ) + port map (vd => vdd, + gd => gnd, + delay_lclkr => delay_lclkr_dc(4), + nclk => nclk, + forcee => slat_force, + thold_b => abst_slat_thold_b, + dclk => abst_slat_d2clk, + lclk => abst_slat_lclk ); + + perv_abst_stg: tri_slat_scan + generic map (width => 4, init => (1 to 4=>'0'), expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + dclk => abst_slat_d2clk, + lclk => abst_slat_lclk, + scan_in(0) => abst_scan_in, + scan_in(1) => abst_scan_out_int, + scan_in(2) => abst_scan_in_q, + scan_in(3) => abst_scan_out_q, + scan_out(0) => abst_scan_in_q, + scan_out(1) => abst_scan_out_q, + scan_out(2) => abst_scan_in_2_q, + scan_out(3) => abst_scan_out_2_q); + + + abist_siv <= abist_sov(1 to abist_sov'right) & abst_scan_in_2_q; + abst_scan_out_int <= abist_sov(0); + abst_scan_out <= abst_scan_out_2_q and scan_dis_dc_b; + + + + ------------------------------------------------- + -- Pervasive + ------------------------------------------------- + perv_2to1_reg: tri_plat + generic map (width => 10, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_xu_ccflush_dc, + din(0) => abst_sl_thold_2, + din(1) => func_sl_thold_2(0), + din(2) => sg_2(0), + din(3) => fce_2(0), + din(4) => fce_2(0), + din(5) => ary_nsl_thold_2, + din(6) => time_sl_thold_2, + din(7) => gptr_sl_thold_2, + din(8) => bolt_sl_thold_2, + din(9) => func_nsl_thold_2, + q(0) => abst_sl_thold_1, + q(1) => func_sl_thold_1, + q(2) => sg_1, + q(3) => fce_1(0), + q(4) => fce_1(1), + q(5) => ary_nsl_thold_1, + q(6) => time_sl_thold_1, + q(7) => gptr_sl_thold_1, + q(8) => bolt_sl_thold_1, + q(9) => func_nsl_thold_1); + + perv_1to0_reg: tri_plat + generic map (width => 10, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_xu_ccflush_dc, + din(0) => abst_sl_thold_1, + din(1) => func_sl_thold_1, + din(2) => sg_1, + din(3) => fce_1(0), + din(4) => fce_1(1), + din(5) => ary_nsl_thold_1, + din(6) => time_sl_thold_1, + din(7) => gptr_sl_thold_1, + din(8) => bolt_sl_thold_1, + din(9) => func_nsl_thold_1, + q(0) => abst_sl_thold_0, + q(1) => func_sl_thold_0, + q(2) => sg_0, + q(3) => fce_0(0), + q(4) => fce_0(1), + q(5) => ary_nsl_thold_0, + q(6) => time_sl_thold_0, + q(7) => gptr_sl_thold_0, + q(8) => bolt_sl_thold_0, + q(9) => func_nsl_thold_0); + + perv_lcbor_func_nsl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_dc_b, + thold => func_nsl_thold_0, + sg => fce_0(0), + act_dis => tidn, + forcee => func_nsl_force, + thold_b => func_nsl_thold_0_b); + + perv_lcbor_func_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_dc_b, + thold => func_sl_thold_0, + sg => sg_0, + act_dis => tidn, + forcee => func_sl_force, + thold_b => func_sl_thold_0_b); + + perv_lcbor_abst_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_dc_b, + thold => abst_sl_thold_0, + sg => sg_0, + act_dis => tidn, + forcee => abst_sl_force, + thold_b => abst_sl_thold_0_b); + + so_force <= sg_0; + func_so_thold_0_b <= not func_sl_thold_0; + + + ------------------------------------------------------------------------------- + -- Decode A + ------------------------------------------------------------------------------- + xu_dec_a : entity work.xuq_dec_a(xuq_dec_a) + generic map( + expand_type => expand_type, + threads => threads, + regmode => regmode, + regsize => regsize, + real_data_add => real_data_add, + eff_ifar => eff_ifar) + port map( + nclk => nclk, + vdd => vdd, + gnd => gnd, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc(4), + mpw1_dc_b => mpw1_dc_b(4), + mpw2_dc_b => mpw2_dc_b, + func_sl_force => func_sl_force, + func_sl_thold_0_b => func_sl_thold_0_b, + sg_0 => sg_0, + scan_in => siv_14(0), + scan_out => sov_14(0), + iu_xu_is2_vld => iu_xu_is2_vld, + iu_xu_is2_ifar => iu_xu_is2_ifar, + iu_xu_is2_tid => iu_xu_is2_tid, + iu_xu_is2_instr => iu_xu_is2_instr, + iu_xu_is2_ta_vld => iu_xu_is2_ta_vld, + iu_xu_is2_ta => iu_xu_is2_ta, + iu_xu_is2_s1_vld => iu_xu_is2_s1_vld, + iu_xu_is2_s1 => iu_xu_is2_s1, + iu_xu_is2_s2_vld => iu_xu_is2_s2_vld, + iu_xu_is2_s2 => iu_xu_is2_s2, + iu_xu_is2_s3_vld => iu_xu_is2_s3_vld, + iu_xu_is2_s3 => iu_xu_is2_s3, + iu_xu_is2_axu_ld_or_st => iu_xu_is2_axu_ld_or_st, + iu_xu_is2_axu_store => iu_xu_is2_axu_store, + iu_xu_is2_axu_ldst_size => iu_xu_is2_axu_ldst_size, + iu_xu_is2_axu_ldst_update => iu_xu_is2_axu_ldst_update, + iu_xu_is2_axu_ldst_forcealign => iu_xu_is2_axu_ldst_forcealign, + iu_xu_is2_axu_ldst_forceexcept => iu_xu_is2_axu_ldst_forceexcept, + iu_xu_is2_axu_ldst_extpid => iu_xu_is2_axu_ldst_extpid, + iu_xu_is2_axu_ldst_indexed => iu_xu_is2_axu_ldst_indexed, + iu_xu_is2_axu_ldst_tag => iu_xu_is2_axu_ldst_tag, + iu_xu_is2_axu_mftgpr => iu_xu_is2_axu_mftgpr, + iu_xu_is2_axu_mffgpr => iu_xu_is2_axu_mffgpr, + iu_xu_is2_axu_movedp => iu_xu_is2_axu_movedp, + iu_xu_is2_axu_instr_type => iu_xu_is2_axu_instr_type, + iu_xu_is2_pred_update => iu_xu_is2_pred_update, + iu_xu_is2_pred_taken_cnt => iu_xu_is2_pred_taken_cnt, + iu_xu_is2_error => iu_xu_is2_error, + iu_xu_is2_match => iu_xu_is2_match, + iu_xu_is2_is_ucode => iu_xu_is2_is_ucode, + iu_xu_is2_ucode_vld => iu_xu_is2_ucode_vld, + iu_xu_is2_gshare => iu_xu_is2_gshare, + xu_div_coll_barr_done => xu_div_coll_barr_done, + xu_div_barr_done => xu_div_barr_done, + dec_gpr_rf0_re0 => dec_gpr_rf0_re0, + dec_gpr_rf0_re1 => dec_gpr_rf0_re1, + dec_gpr_rf0_re2 => dec_gpr_rf0_re2, + dec_gpr_rf0_ra0 => dec_gpr_rf0_ra0, + dec_gpr_rf0_ra1 => dec_gpr_rf0_ra1, + dec_gpr_rf0_ra2 => dec_gpr_rf0_ra2, + dec_gpr_rel_ta_gpr => dec_gpr_rel_ta_gpr, + dec_gpr_rel_wren => dec_gpr_rel_wren, + fxa_fxb_rf0_val => fxa_fxb_rf0_val, + fxa_fxb_rf0_issued => fxa_fxb_rf0_issued, + fxa_fxb_rf0_ucode_val => fxa_fxb_rf0_ucode_val, + fxa_fxb_rf0_act => fxa_fxb_rf0_act, + fxa_fxb_ex1_hold_ctr_flush => fxa_fxb_ex1_hold_ctr_flush, + fxa_fxb_rf0_instr => fxa_fxb_rf0_instr, + fxa_fxb_rf0_tid => fxa_fxb_rf0_tid, + fxa_fxb_rf0_ta_vld => fxa_fxb_rf0_ta_vld, + fxa_fxb_rf0_ta => fxa_fxb_rf0_ta, + fxa_fxb_rf0_error => fxa_fxb_rf0_error, + fxa_fxb_rf0_match => fxa_fxb_rf0_match, + fxa_fxb_rf0_is_ucode => fxa_fxb_rf0_is_ucode, + fxa_fxb_rf0_gshare => fxa_fxb_rf0_gshare, + fxa_fxb_rf0_ifar => fxa_fxb_rf0_ifar, + fxa_fxb_rf0_s1_vld => fxa_fxb_rf0_s1_vld, + fxa_fxb_rf0_s1 => fxa_fxb_rf0_s1, + fxa_fxb_rf0_s2_vld => fxa_fxb_rf0_s2_vld, + fxa_fxb_rf0_s2 => fxa_fxb_rf0_s2, + fxa_fxb_rf0_s3_vld => fxa_fxb_rf0_s3_vld, + fxa_fxb_rf0_s3 => fxa_fxb_rf0_s3, + fxa_fxb_rf0_axu_instr_type => fxa_fxb_rf0_axu_instr_type, + fxa_fxb_rf0_axu_ld_or_st => fxa_fxb_rf0_axu_ld_or_st, + fxa_fxb_rf0_axu_store => fxa_fxb_rf0_axu_store, + fxa_fxb_rf0_axu_mftgpr => fxa_fxb_rf0_axu_mftgpr, + fxa_fxb_rf0_axu_mffgpr => fxa_fxb_rf0_axu_mffgpr, + fxa_fxb_rf0_axu_movedp => fxa_fxb_rf0_axu_movedp, + fxa_fxb_rf0_axu_ldst_size => fxa_fxb_rf0_axu_ldst_size, + fxa_fxb_rf0_axu_ldst_update => fxa_fxb_rf0_axu_ldst_update, + fxa_fxb_rf0_axu_ldst_forcealign => fxa_fxb_rf0_axu_ldst_forcealign, + fxa_fxb_rf0_axu_ldst_forceexcept => fxa_fxb_rf0_axu_ldst_forceexcept, + fxa_fxb_rf0_axu_ldst_indexed => fxa_fxb_rf0_axu_ldst_indexed, + fxa_fxb_rf0_axu_ldst_tag => fxa_fxb_rf0_axu_ldst_tag, + fxa_fxb_rf0_pred_update => fxa_fxb_rf0_pred_update, + fxa_fxb_rf0_pred_taken_cnt => fxa_fxb_rf0_pred_taken_cnt, + fxa_fxb_rf0_mc_dep_chk_val => fxa_fxb_rf0_mc_dep_chk_val, + fxa_fxb_rf1_mul_val => fxa_fxb_rf1_mul_val, + fxa_fxb_rf1_muldiv_coll => fxa_fxb_rf1_muldiv_coll, + fxa_fxb_rf1_div_val => fxa_fxb_rf1_div_val, + fxa_fxb_rf1_div_ctr => fxa_fxb_rf1_div_ctr, + fxa_fxb_rf0_xu_epid_instr => fxa_fxb_rf0_xu_epid_instr, + fxa_fxb_rf0_axu_is_extload => fxa_fxb_rf0_axu_is_extload, + fxa_fxb_rf0_axu_is_extstore => fxa_fxb_rf0_axu_is_extstore, + fxa_fxb_rf0_spr_tid => fxa_fxb_rf0_spr_tid, + fxa_fxb_rf0_cpl_tid => fxa_fxb_rf0_cpl_tid, + fxa_fxb_rf0_cpl_act => fxa_fxb_rf0_cpl_act, + fxa_fxb_rf0_is_mfocrf => fxa_fxb_rf0_is_mfocrf, + fxa_fxb_rf0_3src_instr => fxa_fxb_rf0_3src_instr, + fxa_fxb_rf0_gpr0_zero => fxa_fxb_rf0_gpr0_zero, + fxa_fxb_rf0_use_imm => fxa_fxb_rf0_use_imm, + dec_cpl_ex3_mc_dep_chk_val => dec_cpl_ex3_mc_dep_chk_val, + fxa_perf_muldiv_in_use => fxa_perf_muldiv_in_use, + xu_is2_flush => xu_is2_flush, + xu_rf0_flush => xu_rf0_flush, + xu_rf1_flush => xu_rf1_flush, + xu_ex1_flush => xu_ex1_flush, + xu_ex2_flush => xu_ex2_flush, + xu_ex3_flush => xu_ex3_flush, + xu_ex4_flush => xu_ex4_flush, + xu_ex5_flush => xu_ex5_flush, + fxa_cpl_ex2_div_coll => fxa_cpl_ex2_div_coll, + cpl_fxa_ex5_set_barr => cpl_fxa_ex5_set_barr, + fxa_iu_set_barr_tid => fxa_iu_set_barr_tid, + spr_xucr4_div_barr_thres => spr_xucr4_div_barr_thres, + an_ac_back_inv => an_ac_back_inv, + an_ac_back_inv_addr => an_ac_back_inv_addr, + an_ac_back_inv_target_bit3 => an_ac_back_inv_target_bit3, + dec_spr_rf0_instr => dec_spr_rf0_instr, + xu_lsu_rf0_derat_is_extload => xu_lsu_rf0_derat_is_extload, + xu_lsu_rf0_derat_is_extstore => xu_lsu_rf0_derat_is_extstore, + xu_lsu_rf0_derat_val => xu_lsu_rf0_derat_val, + lsu_xu_rel_wren => lsu_xu_rel_wren, + lsu_xu_rel_ta_gpr => lsu_xu_rel_ta_gpr, + spr_xucr0_clkg_ctl_b0 => spr_xucr0_clkg_ctl_b0, + dec_debug => dec_debug); + + --------------------------------------------------------------------- + -- GPR + --------------------------------------------------------------------- + gpr_rel_data <= lsu_xu_rot_rel_data & "000000"; + + xuq_fxu_gpr : entity work.xuq_fxu_gpr(xuq_fxu_gpr) + generic map( + expand_type => expand_type, + regsize => regsize, + threads => threads) + port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc(4), + clkoff_dc_b => clkoff_dc_b, + mpw1_dc_b => mpw1_dc_b(4), + mpw2_dc_b => mpw2_dc_b, + func_sl_force => func_sl_force, + func_sl_thold_0_b => func_sl_thold_0_b, + func_nsl_force => func_nsl_force, + func_nsl_thold_0_b => func_nsl_thold_0_b, + sg_0 => sg_0, + scan_in => siv_14(1), + scan_out => sov_14(1), + an_ac_scan_diag_dc => an_ac_scan_diag_dc, + + r0e_addr_abist => pc_xu_abist_raddr_0_q(2 to 9), + r1e_addr_abist => pc_xu_abist_raddr_1_q(2 to 9), + r0e_en_abist => pc_xu_abist_grf_renb_0_q, + r1e_en_abist => pc_xu_abist_grf_renb_1_q, + r0e_sel_lbist => an_ac_lbist_ary_wrt_thru_dc, + r1e_sel_lbist => an_ac_lbist_ary_wrt_thru_dc, + abist_en => pc_xu_abist_ena_dc, + lbist_en => an_ac_lbist_ary_wrt_thru_dc, + w0e_addr_abist => pc_xu_abist_waddr_0_q(2 to 9), + w0l_addr_abist => pc_xu_abist_waddr_1_q(2 to 9), + w0e_en_abist => pc_xu_abist_grf_wenb_0_q, + w0l_en_abist => pc_xu_abist_grf_wenb_1_q, + w0e_data_abist => pc_xu_abist_di_0_q, + w0l_data_abist => pc_xu_abist_di_1_q, + r0e_abist_comp_en => pc_xu_abist_wl144_comp_ena_q, + r1e_abist_comp_en => pc_xu_abist_wl144_comp_ena_q, + abist_raw_dc_b => pc_xu_abist_raw_dc_b, + + bo_enable_2 => bo_enable_2, -- general bolt-on enable, probably DC + pc_xu_bo_reset => pc_xu_bo_reset, -- execute sticky bit decode + pc_xu_bo_unload => pc_xu_bo_unload, + pc_xu_bo_load => pc_xu_bo_load, + pc_xu_bo_shdata => pc_xu_bo_shdata, -- shift data for timing write + pc_xu_bo_select => pc_xu_bo_select, -- select for mask and hier writes + xu_pc_bo_fail => xu_pc_bo_fail, -- fail/no-fix reg + xu_pc_bo_diagout => xu_pc_bo_diagout, + + lcb_fce_0 => fce_0(1), + lcb_scan_diag_dc => an_ac_scan_diag_dc, + lcb_scan_dis_dc_b => scan_dis_dc_b, + lcb_sg_0 => sg_0, + lcb_abst_sl_thold_0 => abst_sl_thold_0, + lcb_ary_nsl_thold_0 => ary_nsl_thold_0, + lcb_time_sl_thold_0 => time_sl_thold_0, + lcb_gptr_sl_thold_0 => gptr_sl_thold_0, + lcb_bolt_sl_thold_0 => bolt_sl_thold_0, + + gpr_abst_scan_in => abist_siv(0), + gpr_abst_scan_out => abist_sov(0), + gpr_time_scan_in => time_scan_in, + gpr_time_scan_out => time_scan_out, + gpr_gptr_scan_in => gptr_scan_in, + gpr_gptr_scan_out => gptr_scan_out, + + pc_xu_inj_regfile_parity => pc_xu_inj_regfile_parity, + xu_pc_err_regfile_parity => xu_pc_err_regfile_parity, + xu_pc_err_regfile_ue => xu_pc_err_regfile_ue, + gpr_cpl_ex3_regfile_err_det => gpr_cpl_ex3_regfile_err_det, + cpl_gpr_regfile_seq_beg => cpl_gpr_regfile_seq_beg, + gpr_cpl_regfile_seq_end => gpr_cpl_regfile_seq_end, + + r0_en => dec_gpr_rf0_re0, + r0_addr_func => dec_gpr_rf0_ra0, + r0_data_out => gpr_data_out_0, + + r1_en => dec_gpr_rf0_re1, + r1_addr_func => dec_gpr_rf0_ra1, + r1_data_out => gpr_data_out_1, + + r2_en => dec_gpr_rf0_re2, + r2_addr_func => dec_gpr_rf0_ra2, + r2_data_out => gpr_data_out_2, + + w_e_act => fxb_fxa_ex7_we0, + w_e_addr_func => fxb_fxa_ex7_wa0, + w_e_data_func => fxb_fxa_ex7_wd0, + + w_l_act => dec_gpr_rel_wren, + w_l_addr_func => dec_gpr_rel_ta_gpr, + w_l_data_func => gpr_rel_data, + + gpr_debug => gpr_debug); + + fxa_fxb_rf1_do0 <= gpr_data_out_0(64-regsize to 63); + fxa_fxb_rf1_do1 <= gpr_data_out_1(64-regsize to 63); + fxa_fxb_rf1_do2 <= gpr_data_out_2(64-regsize to 63); + +siv_14(0 to sov_14'right) <= sov_14(1 to sov_14'right) & func_scan_rpwr_in(14); +func_scan_rpwr_out(14) <= sov_14(0); +func_scan_out(14) <= func_scan_out_gate(14) and an_ac_scan_dis_dc_b; + +func_scan_rpwr_i_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc(4), + thold_b => func_so_thold_0_b, + scin => func_scan_in(14 to 14), + scout => func_scan_rpwr_in(14 to 14), + dout => open); +func_scan_rpwr_o_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc(4), + thold_b => func_so_thold_0_b, + scin => func_scan_rpwr_out(14 to 14), + scout => func_scan_out_gate(14 to 14), + dout => open); + + +mark_unused(gpr_data_out_0(64 to 77)); +mark_unused(gpr_data_out_1(64 to 77)); +mark_unused(gpr_data_out_2(64 to 77)); + + +end architecture xuq_fxu_a; + diff --git a/rel/src/vhdl/work/xuq_fxu_b.vhdl b/rel/src/vhdl/work/xuq_fxu_b.vhdl new file mode 100644 index 0000000..523932f --- /dev/null +++ b/rel/src/vhdl/work/xuq_fxu_b.vhdl @@ -0,0 +1,1854 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XUQ FXU B Top +-- +LIBRARY ieee; USE ieee.std_logic_1164.all; +LIBRARY support; + USE support.power_logic_pkg.all; +LIBRARY tri; USE tri.tri_latches_pkg.all; +LIBRARY work; USE work.xuq_pkg.all; + +entity xuq_fxu_b is + generic( + expand_type : integer := 2; + threads : integer := 4; + eff_ifar : integer := 62; + regmode : integer := 6; + regsize : integer := 64; + a2mode : integer := 1; + hvmode : integer := 1; + dc_size : natural := 14; + cl_size : natural := 6; -- 2^6 = 64 Bytes CacheLines + real_data_add : integer := 42; + fxu_synth : integer := 0); + port( + --------------------------------------------------------------------- + -- Clocks & Power + --------------------------------------------------------------------- + nclk : in clk_logic; + vdd : inout power_logic; + gnd : inout power_logic; + vcs : inout power_logic; + + --------------------------------------------------------------------- + -- Pervasive + --------------------------------------------------------------------- + func_scan_in : in std_ulogic_vector(54 to 58); + func_scan_out : out std_ulogic_vector(54 to 58); + an_ac_scan_dis_dc_b : in std_ulogic; + pc_xu_ccflush_dc : in std_ulogic; + clkoff_dc_b : out std_ulogic; + d_mode_dc : out std_ulogic; + delay_lclkr_dc : out std_ulogic_vector(0 to 4); + mpw1_dc_b : out std_ulogic_vector(0 to 4); + mpw2_dc_b : out std_ulogic; + g6t_clkoff_dc_b : out std_ulogic; + g6t_d_mode_dc : out std_ulogic; + g6t_delay_lclkr_dc : out std_ulogic_vector(0 to 4); + g6t_mpw1_dc_b : out std_ulogic_vector(0 to 4); + g6t_mpw2_dc_b : out std_ulogic; + g8t_clkoff_dc_b : out std_ulogic; + g8t_d_mode_dc : out std_ulogic; + g8t_delay_lclkr_dc : out std_ulogic_vector(0 to 4); + g8t_mpw1_dc_b : out std_ulogic_vector(0 to 4); + g8t_mpw2_dc_b : out std_ulogic; + cam_clkoff_dc_b : out std_ulogic; + cam_d_mode_dc : out std_ulogic; + cam_delay_lclkr_dc : out std_ulogic_vector(0 to 4); + cam_act_dis_dc : out std_ulogic; + cam_mpw1_dc_b : out std_ulogic_vector(0 to 4); + cam_mpw2_dc_b : out std_ulogic; + pc_xu_sg_3 : in std_ulogic_vector(0 to 4); + pc_xu_func_sl_thold_3 : in std_ulogic_vector(0 to 4); + pc_xu_func_slp_sl_thold_3 : in std_ulogic_vector(0 to 4); + pc_xu_func_nsl_thold_3 : in std_ulogic; + pc_xu_func_slp_nsl_thold_3 : in std_ulogic; + pc_xu_gptr_sl_thold_3 : in std_ulogic; + pc_xu_abst_sl_thold_3 : in std_ulogic; + pc_xu_abst_slp_sl_thold_3 : in std_ulogic; + pc_xu_regf_sl_thold_3 : in std_ulogic; + pc_xu_regf_slp_sl_thold_3 : in std_ulogic; + pc_xu_time_sl_thold_3 : in std_ulogic; + pc_xu_cfg_sl_thold_3 : in std_ulogic; + pc_xu_cfg_slp_sl_thold_3 : in std_ulogic; + pc_xu_ary_nsl_thold_3 : in std_ulogic; + pc_xu_ary_slp_nsl_thold_3 : in std_ulogic; + pc_xu_repr_sl_thold_3 : in std_ulogic; + pc_xu_bolt_sl_thold_3 : in std_ulogic; + pc_xu_bo_enable_3 : in std_ulogic; + pc_xu_fce_3 : in std_ulogic_vector(0 to 1); + an_ac_scan_diag_dc : in std_ulogic; + sg_2 : out std_ulogic_vector(0 to 3); + fce_2 : out std_ulogic_vector(0 to 1); + func_sl_thold_2 : out std_ulogic_vector(0 to 3); + func_slp_sl_thold_2 : out std_ulogic_vector(0 to 1); + func_nsl_thold_2 : out std_ulogic; + func_slp_nsl_thold_2 : out std_ulogic; + abst_sl_thold_2 : out std_ulogic; + abst_slp_sl_thold_2 : out std_ulogic; + time_sl_thold_2 : out std_ulogic; + gptr_sl_thold_2 : out std_ulogic; + ary_nsl_thold_2 : out std_ulogic; + ary_slp_nsl_thold_2 : out std_ulogic; + repr_sl_thold_2 : out std_ulogic; + cfg_sl_thold_2 : out std_ulogic; + cfg_slp_sl_thold_2 : out std_ulogic; + regf_slp_sl_thold_2 : out std_ulogic; + bolt_sl_thold_2 : out std_ulogic; + bo_enable_2 : out std_ulogic; + gptr_scan_in : in std_ulogic; + gptr_scan_out : out std_ulogic; + + --------------------------------------------------------------------- + -- Interface with FXU A + --------------------------------------------------------------------- + fxa_fxb_rf0_val : in std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_issued : in std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_ucode_val : in std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_act : in std_ulogic; + fxa_fxb_ex1_hold_ctr_flush : in std_ulogic; + fxa_fxb_rf0_instr : in std_ulogic_vector(0 to 31); + fxa_fxb_rf0_tid : in std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_ta_vld : in std_ulogic; + fxa_fxb_rf0_ta : in std_ulogic_vector(0 to 7); + fxa_fxb_rf0_error : in std_ulogic_vector(0 to 2); + fxa_fxb_rf0_match : in std_ulogic; + fxa_fxb_rf0_is_ucode : in std_ulogic; + fxa_fxb_rf0_gshare : in std_ulogic_vector(0 to 3); + fxa_fxb_rf0_ifar : in std_ulogic_vector(62-eff_ifar to 61); + fxa_fxb_rf0_s1_vld : in std_ulogic; + fxa_fxb_rf0_s1 : in std_ulogic_vector(0 to 7); + fxa_fxb_rf0_s2_vld : in std_ulogic; + fxa_fxb_rf0_s2 : in std_ulogic_vector(0 to 7); + fxa_fxb_rf0_s3_vld : in std_ulogic; + fxa_fxb_rf0_s3 : in std_ulogic_vector(0 to 7); + fxa_fxb_rf0_axu_instr_type : in std_ulogic_vector(0 to 2); + fxa_fxb_rf0_axu_ld_or_st : in std_ulogic; + fxa_fxb_rf0_axu_store : in std_ulogic; + fxa_fxb_rf0_axu_ldst_forcealign : in std_ulogic; + fxa_fxb_rf0_axu_ldst_forceexcept : in std_ulogic; + fxa_fxb_rf0_axu_ldst_indexed : in std_ulogic; + fxa_fxb_rf0_axu_ldst_tag : in std_ulogic_vector(0 to 8); + fxa_fxb_rf0_axu_mftgpr : in std_ulogic; + fxa_fxb_rf0_axu_mffgpr : in std_ulogic; + fxa_fxb_rf0_axu_movedp : in std_ulogic; + fxa_fxb_rf0_axu_ldst_size : in std_ulogic_vector(0 to 5); + fxa_fxb_rf0_axu_ldst_update : in std_ulogic; + fxa_fxb_rf0_pred_update : in std_ulogic; + fxa_fxb_rf0_pred_taken_cnt : in std_ulogic_vector(0 to 1); + fxa_fxb_rf0_mc_dep_chk_val : in std_ulogic_vector(0 to threads-1); + fxa_fxb_rf1_mul_val : in std_ulogic; + fxa_fxb_rf1_div_val : in std_ulogic; + fxa_fxb_rf1_div_ctr : in std_ulogic_vector(0 to 7); + fxa_fxb_rf0_xu_epid_instr : in std_ulogic; + fxa_fxb_rf0_axu_is_extload : in std_ulogic; + fxa_fxb_rf0_axu_is_extstore : in std_ulogic; + fxa_fxb_rf0_is_mfocrf : in std_ulogic; + fxa_fxb_rf0_3src_instr : in std_ulogic; + fxa_fxb_rf0_gpr0_zero : in std_ulogic; + fxa_fxb_rf0_use_imm : in std_ulogic; + fxa_fxb_rf1_muldiv_coll : in std_ulogic; + fxb_fxa_ex7_we0 : out std_ulogic; + fxb_fxa_ex7_wa0 : out std_ulogic_vector(0 to 7); + fxb_fxa_ex7_wd0 : out std_ulogic_vector(64-regsize to 63); + fxa_fxb_rf1_do0 : in std_ulogic_vector(64-regsize to 63); + fxa_fxb_rf1_do1 : in std_ulogic_vector(64-regsize to 63); + fxa_fxb_rf1_do2 : in std_ulogic_vector(64-regsize to 63); + + --------------------------------------------------------------------- + -- Interface with LSU + --------------------------------------------------------------------- + xu_lsu_rf0_act : out std_ulogic; + xu_lsu_rf1_cache_acc : out std_ulogic; + xu_lsu_rf1_thrd_id : out std_ulogic_vector(0 to threads-1); + xu_lsu_rf1_optype1 : out std_ulogic; + xu_lsu_rf1_optype2 : out std_ulogic; + xu_lsu_rf1_optype4 : out std_ulogic; + xu_lsu_rf1_optype8 : out std_ulogic; + xu_lsu_rf1_optype16 : out std_ulogic; + xu_lsu_rf1_optype32 : out std_ulogic; + xu_lsu_rf1_target_gpr : out std_ulogic_vector(0 to 8); + xu_lsu_rf1_load_instr : out std_ulogic; + xu_lsu_rf1_store_instr : out std_ulogic; + xu_lsu_rf1_dcbf_instr : out std_ulogic; + xu_lsu_rf1_sync_instr : out std_ulogic; + xu_lsu_rf1_mbar_instr : out std_ulogic; + xu_lsu_rf1_l_fld : out std_ulogic_vector(0 to 1); + xu_lsu_rf1_dcbi_instr : out std_ulogic; + xu_lsu_rf1_dcbz_instr : out std_ulogic; + xu_lsu_rf1_dcbt_instr : out std_ulogic; + xu_lsu_rf1_dcbtst_instr : out std_ulogic; + xu_lsu_rf1_th_fld : out std_ulogic_vector(0 to 4); + xu_lsu_rf1_dcbtls_instr : out std_ulogic; + xu_lsu_rf1_dcbtstls_instr : out std_ulogic; + xu_lsu_rf1_dcblc_instr : out std_ulogic; + xu_lsu_rf1_dcbst_instr : out std_ulogic; + xu_lsu_rf1_icbi_instr : out std_ulogic; + xu_lsu_rf1_icblc_instr : out std_ulogic; + xu_lsu_rf1_icbt_instr : out std_ulogic; + xu_lsu_rf1_icbtls_instr : out std_ulogic; + xu_lsu_rf1_tlbsync_instr : out std_ulogic; + xu_lsu_rf1_lock_instr : out std_ulogic; + xu_lsu_rf1_mutex_hint : out std_ulogic; + xu_lsu_rf1_axu_op_val : out std_ulogic; + xu_lsu_rf1_axu_ldst_falign : out std_ulogic; + xu_lsu_rf1_axu_ldst_fexcpt : out std_ulogic; + xu_lsu_ex1_store_data : out std_ulogic_vector(64-(2**regmode) to 63); + xu_lsu_rf1_algebraic : out std_ulogic; + xu_lsu_rf1_byte_rev : out std_ulogic; + xu_lsu_rf1_src_gpr : out std_ulogic; + xu_lsu_rf1_src_axu : out std_ulogic; + xu_lsu_rf1_src_dp : out std_ulogic; + xu_lsu_rf1_targ_gpr : out std_ulogic; + xu_lsu_rf1_targ_axu : out std_ulogic; + xu_lsu_rf1_targ_dp : out std_ulogic; + xu_lsu_ex1_rotsel_ovrd : out std_ulogic_vector(0 to 4); + xu_lsu_rf1_derat_act : out std_ulogic; + xu_lsu_rf1_derat_is_load : out std_ulogic; + xu_lsu_rf1_derat_is_store : out std_ulogic; + xu_lsu_rf1_src0_vld : out std_ulogic; + xu_lsu_rf1_src0_reg : out std_ulogic_vector(0 to 7); + xu_lsu_rf1_src1_vld : out std_ulogic; + xu_lsu_rf1_src1_reg : out std_ulogic_vector(0 to 7); + xu_lsu_rf1_targ_vld : out std_ulogic; + xu_lsu_rf1_targ_reg : out std_ulogic_vector(0 to 7); + xu_bx_ex1_mtdp_val : out std_ulogic; + xu_bx_ex1_mfdp_val : out std_ulogic; + xu_bx_ex1_ipc_thrd : out std_ulogic_vector(0 to 1); + xu_bx_ex2_ipc_ba : out std_ulogic_vector(0 to 4); + xu_bx_ex2_ipc_sz : out std_ulogic_vector(0 to 1); + xu_lsu_rf1_is_touch : out std_ulogic; + xu_lsu_rf1_is_msgsnd : out std_ulogic; + xu_lsu_rf1_dci_instr : out std_ulogic; + xu_lsu_rf1_ici_instr : out std_ulogic; + xu_lsu_rf1_icswx_instr : out std_ulogic; + xu_lsu_rf1_icswx_dot_instr : out std_ulogic; + xu_lsu_rf1_icswx_epid : out std_ulogic; + xu_lsu_rf1_ldawx_instr : out std_ulogic; + xu_lsu_rf1_wclr_instr : out std_ulogic; + xu_lsu_rf1_wchk_instr : out std_ulogic; + xu_lsu_rf1_derat_ra_eq_ea : out std_ulogic; + xu_lsu_rf1_cmd_act : out std_ulogic; + xu_lsu_rf1_data_act : out std_ulogic; + xu_lsu_rf1_mtspr_trace : out std_ulogic; + lsu_xu_ex5_wren : in std_ulogic; -- FXU Load Hit Write is Valid in EX5 + lsu_xu_rel_wren : in std_ulogic; -- FXU Reload is Valid + lsu_xu_rel_ta_gpr : in std_ulogic_vector(0 to 7); -- FXU Reload Target Register + lsu_xu_need_hole : in std_ulogic; + lsu_xu_rot_ex6_data_b : in std_ulogic_vector(64-(2**regmode) to 63); + lsu_xu_rot_rel_data : in std_ulogic_vector(64-(2**regmode) to 63); + xu_lsu_ex4_dvc1_en : out std_ulogic; + xu_lsu_ex4_dvc2_en : out std_ulogic; + lsu_xu_ex2_dvc1_st_cmp : in std_ulogic_vector(8-(2**regmode)/8 to 7); + lsu_xu_ex2_dvc2_st_cmp : in std_ulogic_vector(8-(2**regmode)/8 to 7); + lsu_xu_ex8_dvc1_ld_cmp : in std_ulogic_vector(8-(2**regmode)/8 to 7); + lsu_xu_ex8_dvc2_ld_cmp : in std_ulogic_vector(8-(2**regmode)/8 to 7); + lsu_xu_rel_dvc1_en : in std_ulogic; + lsu_xu_rel_dvc2_en : in std_ulogic; + lsu_xu_rel_dvc_thrd_id : in std_ulogic_vector(0 to 3); + lsu_xu_rel_dvc1_cmp : in std_ulogic_vector(8-(2**regmode)/8 to 7); + lsu_xu_rel_dvc2_cmp : in std_ulogic_vector(8-(2**regmode)/8 to 7); + xu_lsu_ex1_add_src0 : out std_ulogic_vector(64-regsize to 63); + xu_lsu_ex1_add_src1 : out std_ulogic_vector(64-regsize to 63); + + --------------------------------------------------------------------- + -- Effective Address + --------------------------------------------------------------------- + xu_ex1_eff_addr_int : out std_ulogic_vector(64-(dc_size-3) to 63); + + --------------------------------------------------------------------- + -- TLB ops interface + --------------------------------------------------------------------- + xu_iu_rf1_val : out std_ulogic_vector(0 to threads-1); + xu_rf1_val : out std_ulogic_vector(0 to threads-1); + xu_rf1_is_tlbre : out std_ulogic; + xu_rf1_is_tlbwe : out std_ulogic; + xu_rf1_is_tlbsx : out std_ulogic; + xu_rf1_is_tlbsrx : out std_ulogic; + xu_rf1_is_tlbilx : out std_ulogic; + xu_rf1_is_tlbivax : out std_ulogic; + xu_rf1_is_eratre : out std_ulogic; + xu_rf1_is_eratwe : out std_ulogic; + xu_rf1_is_eratsx : out std_ulogic; + xu_rf1_is_eratsrx : out std_ulogic; + xu_rf1_is_eratilx : out std_ulogic; + xu_rf1_is_erativax : out std_ulogic; + xu_ex1_is_isync : out std_ulogic; + xu_ex1_is_csync : out std_ulogic; + xu_rf1_ws : out std_ulogic_vector(0 to 1); + xu_rf1_t : out std_ulogic_vector(0 to 2); + xu_ex1_rs_is : out std_ulogic_vector(0 to 8); + xu_ex1_ra_entry : out std_ulogic_vector(7 to 11); + xu_ex1_rb : out std_ulogic_vector(64-(2**regmode) to 51); + xu_ex2_eff_addr : out std_ulogic_vector(64-(2**regmode) to 63); + xu_ex4_rs_data : out std_ulogic_vector(64-(2**regmode) to 63); + lsu_xu_ex4_tlb_data : in std_ulogic_vector(64-(2**regmode) to 63); + iu_xu_ex4_tlb_data : in std_ulogic_vector(64-(2**regmode) to 63); + + --------------------------------------------------------------------- + -- D-ERAT Req Interface + --------------------------------------------------------------------- + xu_mm_derat_epn : out std_ulogic_vector(62-eff_ifar to 51); + + --------------------------------------------------------------------- + -- Back Invalidate + --------------------------------------------------------------------- + lsu_xu_is2_back_inv : in std_ulogic; + lsu_xu_is2_back_inv_addr : in std_ulogic_vector(64-real_data_add to 63-cl_size); + + --------------------------------------------------------------------- + -- TLBRE + --------------------------------------------------------------------- + mm_xu_mmucr0_0_tlbsel : in std_ulogic_vector(4 to 5); + mm_xu_mmucr0_1_tlbsel : in std_ulogic_vector(4 to 5); + mm_xu_mmucr0_2_tlbsel : in std_ulogic_vector(4 to 5); + mm_xu_mmucr0_3_tlbsel : in std_ulogic_vector(4 to 5); + + --------------------------------------------------------------------- + -- TLBSX./TLBSRX. + --------------------------------------------------------------------- + xu_mm_rf1_is_tlbsxr : out std_ulogic; + mm_xu_cr0_eq_valid : in std_ulogic_vector(0 to threads-1); + mm_xu_cr0_eq : in std_ulogic_vector(0 to threads-1); + + --------------------------------------------------------------------- + -- FU CR Write + --------------------------------------------------------------------- + fu_xu_ex4_cr_val : in std_ulogic_vector(0 to threads-1); + fu_xu_ex4_cr_noflush : in std_ulogic_vector(0 to threads-1); + fu_xu_ex4_cr0 : in std_ulogic_vector(0 to 3); + fu_xu_ex4_cr0_bf : in std_ulogic_vector(0 to 2); + fu_xu_ex4_cr1 : in std_ulogic_vector(0 to 3); + fu_xu_ex4_cr1_bf : in std_ulogic_vector(0 to 2); + fu_xu_ex4_cr2 : in std_ulogic_vector(0 to 3); + fu_xu_ex4_cr2_bf : in std_ulogic_vector(0 to 2); + fu_xu_ex4_cr3 : in std_ulogic_vector(0 to 3); + fu_xu_ex4_cr3_bf : in std_ulogic_vector(0 to 2); + + --------------------------------------------------------------------- + -- RAM + --------------------------------------------------------------------- + xu_pc_ram_data : out std_ulogic_vector(64-(2**regmode) to 63); + + --------------------------------------------------------------------- + -- Interface with IU + --------------------------------------------------------------------- + xu_iu_ex5_val : out std_ulogic; + xu_iu_ex5_tid : out std_ulogic_vector(0 to threads-1); + xu_iu_ex5_br_update : out std_ulogic; + xu_iu_ex5_br_hist : out std_ulogic_vector(0 to 1); + xu_iu_ex5_bclr : out std_ulogic; + xu_iu_ex5_lk : out std_ulogic; + xu_iu_ex5_bh : out std_ulogic_vector(0 to 1); + xu_iu_ex6_pri : out std_ulogic_vector(0 to 2); + xu_iu_ex6_pri_val : out std_ulogic_vector(0 to 3); + xu_iu_spr_xer : out std_ulogic_vector(0 to 7*threads-1); + xu_iu_slowspr_done : out std_ulogic_vector(0 to threads-1); + xu_iu_need_hole : out std_ulogic; + fxb_fxa_ex6_clear_barrier : out std_ulogic_vector(0 to threads-1); + xu_iu_ex5_gshare : out std_ulogic_vector(0 to 3); + xu_iu_ex5_getNIA : out std_ulogic; + + --------------------------------------------------------------------- + -- L2 STCX complete + --------------------------------------------------------------------- + an_ac_stcx_complete : in std_ulogic_vector(0 to threads-1); + an_ac_stcx_pass : in std_ulogic_vector(0 to threads-1); + + --------------------------------------------------------------------- + -- icswx. interface + --------------------------------------------------------------------- + an_ac_back_inv : in std_ulogic; + an_ac_back_inv_addr : in std_ulogic_vector(58 to 63); + an_ac_back_inv_target_bit3 : in std_ulogic; + + --------------------------------------------------------------------- + -- Slow SPR Bus + --------------------------------------------------------------------- + slowspr_val_in : in std_ulogic; + slowspr_rw_in : in std_ulogic; + slowspr_etid_in : in std_ulogic_vector(0 to 1); + slowspr_addr_in : in std_ulogic_vector(0 to 9); + slowspr_data_in : in std_ulogic_vector(64-(2**regmode) to 63); + slowspr_done_in : in std_ulogic; + + --------------------------------------------------------------------- + -- DCR Bus + --------------------------------------------------------------------- + an_ac_dcr_act : in std_ulogic; + an_ac_dcr_val : in std_ulogic; + an_ac_dcr_read : in std_ulogic; + an_ac_dcr_etid : in std_ulogic_vector(0 to 1); + an_ac_dcr_data : in std_ulogic_vector(64-(2**regmode) to 63); + an_ac_dcr_done : in std_ulogic; + an_ac_dcr_ack : out std_ulogic; + + --------------------------------------------------------------------- + -- MT/MFDCR CR + --------------------------------------------------------------------- + lsu_xu_ex4_mtdp_cr_status : in std_ulogic; + lsu_xu_ex4_mfdp_cr_status : in std_ulogic; + + --------------------------------------------------------------------- + -- ldawx/wchkall + --------------------------------------------------------------------- + lsu_xu_ex4_cr_upd : in std_ulogic; + lsu_xu_ex5_cr_rslt : in std_ulogic; + + --------------------------------------------------------------------- + -- Interface with CPL + --------------------------------------------------------------------- + dec_cpl_ex3_mult_coll : out std_ulogic; + dec_cpl_ex3_axu_instr_type : out std_ulogic_vector(0 to 2); + dec_cpl_ex3_instr_hypv : out std_ulogic; + dec_cpl_rf1_ucode_val : out std_ulogic_vector(0 to threads-1); + dec_cpl_ex2_error : out std_ulogic_vector(0 to 2); + dec_cpl_ex2_match : out std_ulogic; + dec_cpl_ex2_is_ucode : out std_ulogic; + dec_cpl_rf1_ifar : out std_ulogic_vector(62-eff_ifar to 61); + dec_cpl_ex3_is_any_store : out std_ulogic; + dec_cpl_ex2_is_any_load_dac : out std_ulogic; + dec_cpl_ex3_instr_priv : out std_ulogic; + dec_cpl_ex1_epid_instr : out std_ulogic; + dec_cpl_ex2_illegal_op : out std_ulogic; + alu_cpl_ex3_trap_val : out std_ulogic; + mux_cpl_ex4_rt : out std_ulogic_vector(64-(2**regmode) to 63); + dec_cpl_ex2_is_any_store_dac : out std_ulogic; + dec_cpl_ex3_tlb_illeg : out std_ulogic; + dec_cpl_ex3_mtdp_nr : out std_ulogic; + mux_cpl_slowspr_done : out std_ulogic_vector(0 to threads-1); + mux_cpl_slowspr_flush : out std_ulogic_vector(0 to threads-1); + dec_cpl_rf1_val : out std_ulogic_vector(0 to threads-1); + dec_cpl_rf1_issued : out std_ulogic_vector(0 to threads-1); + dec_cpl_rf1_instr : out std_ulogic_vector(0 to 31); + cpl_byp_ex3_spr_rt : in std_ulogic_vector(64-(2**regmode) to 63); + byp_cpl_ex1_cr_bit : out std_ulogic; + dec_cpl_rf1_pred_taken_cnt : out std_ulogic; + dec_cpl_ex1_is_slowspr_wr : out std_ulogic; + dec_cpl_ex3_ddmh_en : out std_ulogic; + dec_cpl_ex3_back_inv : out std_ulogic; + + --------------------------------------------------------------------- + -- Flushes + --------------------------------------------------------------------- + xu_rf1_flush : in std_ulogic_vector(0 to threads-1); + xu_ex1_flush : in std_ulogic_vector(0 to threads-1); + xu_ex2_flush : in std_ulogic_vector(0 to threads-1); + xu_ex3_flush : in std_ulogic_vector(0 to threads-1); + xu_ex4_flush : in std_ulogic_vector(0 to threads-1); + xu_ex5_flush : in std_ulogic_vector(0 to threads-1); + + --------------------------------------------------------------------- + -- Interface with SPR + --------------------------------------------------------------------- + dec_spr_ex4_val : out std_ulogic_vector(0 to threads-1); + mux_spr_ex2_rt : out std_ulogic_vector(64-(2**regmode) to 63); + fxu_spr_ex1_rs0 : out std_ulogic_vector(52 to 63); + fxu_spr_ex1_rs1 : out std_ulogic_vector(54 to 63); + spr_msr_cm : in std_ulogic_vector(0 to threads-1); + spr_dec_spr_xucr0_ssdly : in std_ulogic_vector(0 to 4); + spr_ccr2_en_attn : in std_ulogic; + spr_ccr2_en_ditc : in std_ulogic; + spr_ccr2_en_pc : in std_ulogic; + spr_ccr2_en_icswx : in std_ulogic; + spr_ccr2_en_dcr : in std_ulogic; + spr_dec_rf1_epcr_dgtmi : in std_ulogic_vector(0 to threads-1); + spr_dec_rf1_msr_ucle : in std_ulogic_vector(0 to threads-1); + spr_dec_rf1_msrp_uclep : in std_ulogic_vector(0 to threads-1); + spr_byp_ex4_is_mfxer : in std_ulogic_vector(0 to threads-1); + spr_byp_ex3_spr_rt : in std_ulogic_vector(64-(2**regmode) to 63); + spr_byp_ex4_is_mtxer : in std_ulogic_vector(0 to threads-1); + spr_ccr2_notlb : in std_ulogic; + dec_spr_rf1_val : out std_ulogic_vector(0 to threads-1); + fxu_spr_ex1_rs2 : out std_ulogic_vector(42 to 55); + + --------------------------------------------------------------------- + -- Perf Events + --------------------------------------------------------------------- + cpl_perf_tx_events : in std_ulogic_vector(0 to 75); + spr_perf_tx_events : in std_ulogic_vector(0 to 8*threads-1); + fxa_perf_muldiv_in_use : in std_ulogic; + xu_pc_event_data : out std_ulogic_vector(0 to 7); + + --------------------------------------------------------------------- + -- PC Control Interface + --------------------------------------------------------------------- + pc_xu_event_bus_enable : in std_ulogic; + pc_xu_event_count_mode : in std_ulogic_vector(0 to 2); + pc_xu_event_mux_ctrls : in std_ulogic_vector(0 to 47); + + --------------------------------------------------------------------- + -- Debug Ramp & Controls + --------------------------------------------------------------------- + pc_xu_trace_bus_enable : in std_ulogic; + pc_xu_instr_trace_mode : in std_ulogic; + pc_xu_instr_trace_tid : in std_ulogic_vector(0 to 1); + dec_cpl_rf1_instr_trace_val : out std_ulogic; + dec_cpl_rf1_instr_trace_type : out std_ulogic_vector(0 to 1); + dec_cpl_ex3_instr_trace_val : out std_ulogic; + xu_lsu_ex2_instr_trace_val : out std_ulogic; + cpl_dec_in_ucode : in std_ulogic_vector(0 to threads-1); + fxu_debug_mux_ctrls : in std_ulogic_vector(0 to 15); + fxu_trigger_data_in : in std_ulogic_vector(0 to 11); + fxu_debug_data_in : in std_ulogic_vector(0 to 87); + fxu_trigger_data_out : out std_ulogic_vector(0 to 11); + fxu_debug_data_out : out std_ulogic_vector(0 to 87); + lsu_xu_data_debug0 : in std_ulogic_vector(0 to 87); + lsu_xu_data_debug1 : in std_ulogic_vector(0 to 87); + lsu_xu_data_debug2 : in std_ulogic_vector(0 to 87); + + --------------------------------------------------------------------- + -- DAC + --------------------------------------------------------------------- + fxu_cpl_ex3_dac1r_cmpr_async : out std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac2r_cmpr_async : out std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac1r_cmpr : out std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac2r_cmpr : out std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac3r_cmpr : out std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac4r_cmpr : out std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac1w_cmpr : out std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac2w_cmpr : out std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac3w_cmpr : out std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac4w_cmpr : out std_ulogic_vector(0 to threads-1); + + --------------------------------------------------------------------- + -- SPR Bits + --------------------------------------------------------------------- + spr_bit_act : in std_ulogic; + spr_msr_gs : in std_ulogic_vector(0 to threads-1); + spr_msr_ds : in std_ulogic_vector(0 to threads-1); + spr_msr_pr : in std_ulogic_vector(0 to threads-1); + spr_dbcr0_dac1 : in std_ulogic_vector(0 to 2*threads-1); + spr_dbcr0_dac2 : in std_ulogic_vector(0 to 2*threads-1); + spr_dbcr0_dac3 : in std_ulogic_vector(0 to 2*threads-1); + spr_dbcr0_dac4 : in std_ulogic_vector(0 to 2*threads-1); + spr_dbcr3_ivc : out std_ulogic_vector(0 to threads-1); + spr_xucr0_clkg_ctl : in std_ulogic_vector(2 to 2) + ); + -- synopsys translate_off + + + -- synopsys translate_on +end xuq_fxu_b; + +architecture xuq_fxu_b of xuq_fxu_b is + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + -- Signals + signal sg_2_b : std_ulogic_vector(0 to 3); + signal fce_2_b : std_ulogic_vector(0 to 1); + signal func_sl_thold_2_b : std_ulogic_vector(0 to 3); + signal func_slp_sl_thold_2_b : std_ulogic_vector(0 to 1); + signal func_slp_nsl_thold_2_b : std_ulogic; + signal func_nsl_thold_2_b : std_ulogic; + signal clkoff_dc_b_b : std_ulogic; + signal d_mode_dc_b : std_ulogic; + signal delay_lclkr_dc_b : std_ulogic_vector(0 to 4); + signal mpw1_dc_b_b : std_ulogic_vector(0 to 4); + signal mpw2_dc_b_b : std_ulogic; + + signal func_slp_sl_thold_1 : std_ulogic; + signal func_slp_nsl_thold_1 : std_ulogic; + signal func_sl_thold_1 : std_ulogic; + signal func_nsl_thold_1 : std_ulogic; + signal sg_1 : std_ulogic; + signal fce_1 : std_ulogic; + signal func_slp_sl_thold_0 : std_ulogic; + signal func_slp_nsl_thold_0 : std_ulogic; + signal func_sl_thold_0 : std_ulogic; + signal func_nsl_thold_0 : std_ulogic; + signal sg_0 : std_ulogic; + signal fce_0 : std_ulogic; + signal func_sl_force : std_ulogic; + signal func_nsl_force : std_ulogic; + signal func_sl_thold_0_b : std_ulogic; + signal func_nsl_thold_0_b : std_ulogic; + signal func_slp_sl_force : std_ulogic; + signal func_slp_sl_thold_0_b : std_ulogic; + signal func_slp_nsl_force : std_ulogic; + signal func_slp_nsl_thold_0_b : std_ulogic; + signal so_force : std_ulogic; + signal func_so_thold_0_b : std_ulogic; + + -- temp + signal dec_spr_ex1_is_mfspr : std_ulogic; + signal dec_spr_ex1_is_mtspr : std_ulogic; + + -- Inter-Unit Signals + signal byp_alu_ex1_rs0 : std_ulogic_vector(64-regsize to 63); + signal byp_alu_ex1_rs1 : std_ulogic_vector(64-regsize to 63); + signal alu_byp_ex2_rt : std_ulogic_vector(64-regsize to 63); + signal alu_byp_ex2_rt_b : std_ulogic_vector(64-regsize to 63); + signal alu_byp_ex1_log_rt : std_ulogic_vector(64-regsize to 63); -- ALU Logicals + signal byp_spr_ex6_rt : std_ulogic_vector(64-regsize to 63); + signal byp_alu_ex1_mulsrc_0 : std_ulogic_vector(64-regsize to 63); + signal byp_alu_ex1_mulsrc_1 : std_ulogic_vector(64-regsize to 63); + signal byp_alu_ex1_divsrc_0 : std_ulogic_vector(64-regsize to 63); + signal byp_alu_ex1_divsrc_1 : std_ulogic_vector(64-regsize to 63); + signal alu_ex2_div_done : std_ulogic; + signal alu_ex3_mul_done : std_ulogic; + signal alu_ex4_mul_done : std_ulogic; + signal alu_byp_ex3_cr_div : std_ulogic_vector(0 to 4); + signal alu_byp_ex3_xer_div : std_ulogic_vector(0 to 3); + signal dec_byp_rf1_rs0_sel : std_ulogic_vector(1 to 9); + signal dec_byp_rf1_rs1_sel : std_ulogic_vector(1 to 10); + signal dec_byp_rf1_rs2_sel : std_ulogic_vector(1 to 9); + signal dec_byp_rf1_instr : std_ulogic_vector(6 to 25); + signal dec_byp_rf1_cr_so_update : std_ulogic_vector(0 to 1); + signal dec_byp_ex3_val : std_ulogic_vector(0 to threads-1); + signal dec_byp_rf1_cr_we : std_ulogic; + signal dec_byp_rf1_is_mcrf : std_ulogic; + signal dec_byp_rf1_use_crfld0 : std_ulogic; + signal dec_byp_rf1_alu_cmp : std_ulogic; + signal dec_byp_rf1_is_mtcrf : std_ulogic; + signal dec_byp_rf1_is_mtocrf : std_ulogic; + signal dec_byp_rf1_byp_val : std_ulogic_vector(1 to 3); + signal dec_byp_ex4_is_eratsxr : std_ulogic; + signal dec_byp_ex3_tlb_sel : std_ulogic_vector(0 to 1); + signal dec_alu_rf1_div_val : std_ulogic; + signal dec_alu_rf1_div_sign : std_ulogic; + signal dec_alu_rf1_div_size : std_ulogic; + signal dec_alu_rf1_div_extd : std_ulogic; + signal dec_alu_rf1_div_recform : std_ulogic; + signal dec_alu_rf1_sel : std_ulogic_vector(0 to 3); -- ADD,ROT,LOG,CMPB + signal dec_alu_rf1_add_rs0_inv : std_ulogic_vector(64-regsize to 63); + signal dec_alu_rf1_add_ci : std_ulogic; + signal dec_alu_rf1_is_cmpl : std_ulogic; + signal dec_alu_rf1_tw_cmpsel : std_ulogic_vector(0 to 5); + signal dec_rf1_is_isel : std_ulogic; + signal dec_alu_rf1_xer_ov_update : std_ulogic; + signal dec_alu_rf1_xer_ca_update : std_ulogic; + signal dec_alu_rf1_sh_right : std_ulogic; + signal dec_alu_rf1_sh_word : std_ulogic; + signal dec_alu_rf1_sgnxtd_byte : std_ulogic; + signal dec_alu_rf1_sgnxtd_half : std_ulogic; + signal dec_alu_rf1_sgnxtd_wd : std_ulogic; + signal dec_alu_rf1_sra_dw : std_ulogic; + signal dec_alu_rf1_sra_wd : std_ulogic; + signal dec_alu_rf1_chk_shov_dw : std_ulogic; + signal dec_alu_rf1_chk_shov_wd : std_ulogic; + signal dec_alu_rf1_use_me_ins_hi : std_ulogic; + signal dec_alu_rf1_use_me_ins_lo : std_ulogic; + signal dec_alu_rf1_use_mb_ins_hi : std_ulogic; + signal dec_alu_rf1_use_mb_ins_lo : std_ulogic; + signal dec_alu_rf1_use_me_rb_hi : std_ulogic; + signal dec_alu_rf1_use_me_rb_lo : std_ulogic; + signal dec_alu_rf1_use_mb_rb_hi : std_ulogic; + signal dec_alu_rf1_use_mb_rb_lo : std_ulogic; + signal dec_alu_rf1_use_rb_amt_hi : std_ulogic; + signal dec_alu_rf1_use_rb_amt_lo : std_ulogic; + signal dec_alu_rf1_zm_ins : std_ulogic; + signal dec_alu_rf1_log_fcn : std_ulogic_vector(0 to 3); + signal dec_alu_rf1_me_ins_b : std_ulogic_vector(0 to 5); + signal dec_alu_rf1_mb_ins : std_ulogic_vector(0 to 5); + signal dec_alu_rf1_sh_amt : std_ulogic_vector(0 to 5); + signal dec_alu_rf1_mb_gt_me : std_ulogic; + signal dec_alu_rf1_mul_recform : std_ulogic; + signal dec_alu_rf1_mul_val : std_ulogic; + signal dec_alu_rf1_mul_ret : std_ulogic; + signal dec_alu_rf1_mul_sign : std_ulogic; + signal dec_alu_rf1_mul_size : std_ulogic; + signal dec_alu_rf1_mul_imm : std_ulogic; + signal dec_alu_ex1_is_cmp : std_ulogic; + signal dec_alu_rf1_select_64bmode : std_ulogic; + signal dec_byp_rf1_imm : std_ulogic_vector(64-regsize to 63); + signal dec_rf1_tid : std_ulogic_vector(0 to threads-1); + signal dec_ex1_tid : std_ulogic_vector(0 to threads-1); + signal dec_ex2_tid : std_ulogic_vector(0 to threads-1); + signal dec_ex3_tid : std_ulogic_vector(0 to threads-1); + signal dec_ex4_tid : std_ulogic_vector(0 to threads-1); + signal dec_ex5_tid : std_ulogic_vector(0 to threads-1); + signal dec_byp_rf1_ca_used : std_ulogic; + signal dec_byp_rf1_ov_used : std_ulogic; + signal dec_byp_ex4_dp_instr : std_ulogic; + signal dec_byp_ex4_mtdp_val : std_ulogic; + signal dec_byp_ex4_mfdp_val : std_ulogic; + signal dec_byp_ex4_is_wchkall : std_ulogic; + signal dec_byp_ex1_spr_sel : std_ulogic; + signal dec_byp_ex4_is_mfcr : std_ulogic; + signal alu_byp_ex5_mul_rt : std_ulogic_vector(64-regsize to 63); + signal alu_byp_ex3_div_rt : std_ulogic_vector(64-regsize to 63); + signal alu_dec_ex1_ipb_ba : std_ulogic_vector(27 to 31); + signal alu_dec_div_need_hole : std_ulogic; + signal byp_dec_rf1_xer_ca : std_ulogic; + signal alu_byp_ex2_cr_recform : std_ulogic_vector(0 to 3); + signal alu_byp_ex5_cr_mul : std_ulogic_vector(0 to 4); + signal alu_byp_ex2_xer : std_ulogic_vector(0 to 3); + signal alu_byp_ex5_xer_mul : std_ulogic_vector(0 to 3); + signal dec_byp_ex5_instr : std_ulogic_vector(12 to 19); + signal dec_byp_rf0_act : std_ulogic; + signal ex2_is_any_store_dac : std_ulogic; + signal ex2_is_any_load_dac : std_ulogic; + signal fspr_byp_ex3_spr_rt : std_ulogic_vector(64-regsize to 63); + signal dec_fspr_ex1_instr : std_ulogic_vector(11 to 20); + signal dec_fspr_ex6_val : std_ulogic_vector(0 to threads-1); + signal byp_alu_rf1_isel_fcn : std_ulogic_vector(0 to 3); + signal dec_byp_ex4_dcr_ack : std_ulogic; + signal byp_perf_tx_events : std_ulogic_vector(0 to 3*threads-1); + signal dec_byp_ex3_instr_trace_val : std_ulogic; + signal dec_byp_ex3_instr_trace_gate : std_ulogic; + signal ex7_we0 : std_ulogic; + signal ex7_wa0 : std_ulogic_vector(0 to 7); + signal ex7_wd0 : std_ulogic_vector(64-regsize to 63); + signal dec_alu_rf1_act : std_ulogic; + signal dec_alu_ex1_act : std_ulogic; + + -- Scan + signal siv_54, sov_54 : std_ulogic_vector(0 to 2); + signal siv_55, sov_55 : std_ulogic_vector(0 to 2); + signal siv_56, sov_56 : std_ulogic_vector(0 to 4); + signal siv_57, sov_57 : std_ulogic_vector(0 to 3); + signal siv_58, sov_58 : std_ulogic_vector(0 to 2); + -- SPR bits + signal byp_xer_si : std_ulogic_vector(0 to 7*threads-1); + signal gpr_we0_debug : std_ulogic_vector(0 to 87); + signal byp_grp0_debug : std_ulogic_vector(0 to 87); + signal byp_grp1_debug : std_ulogic_vector(0 to 87); + signal byp_grp2_debug : std_ulogic_vector(0 to 87); + signal byp_grp3_debug : std_ulogic_vector(0 to 87); + signal byp_grp4_debug : std_ulogic_vector(0 to 87); + signal byp_grp5_debug : std_ulogic_vector(0 to 87); + signal byp_grp6_debug : std_ulogic_vector(0 to 87); + signal byp_grp7_debug : std_ulogic_vector(0 to 87); + signal byp_grp8_debug : std_ulogic_vector(22 to 87); + signal dec_grp0_debug : std_ulogic_vector(0 to 87); + signal dec_grp1_debug : std_ulogic_vector(0 to 87); + signal dbg_group0, dbg_group1, dbg_group2, dbg_group3, + dbg_group4, dbg_group5, dbg_group6, dbg_group7, + dbg_group8, dbg_group9, dbg_group10,dbg_group11, + dbg_group12,dbg_group13,dbg_group14,dbg_group15: std_ulogic_vector(0 to 87); + signal trg_group0 ,trg_group1 ,trg_group2 ,trg_group3 : std_ulogic_vector(0 to 11); + +begin + + sg_2 <= sg_2_b; + fce_2 <= fce_2_b; + func_sl_thold_2 <= func_sl_thold_2_b; + func_slp_sl_thold_2 <= func_slp_sl_thold_2_b; + func_slp_nsl_thold_2 <= func_slp_nsl_thold_2_b; + func_nsl_thold_2 <= func_nsl_thold_2_b; + clkoff_dc_b <= clkoff_dc_b_b; + d_mode_dc <= d_mode_dc_b; + delay_lclkr_dc <= delay_lclkr_dc_b; + mpw1_dc_b <= mpw1_dc_b_b; + mpw2_dc_b <= mpw2_dc_b_b; + + ------------------------------------------------- + -- Pervasive + ------------------------------------------------- + perv_2to1_reg: tri_plat + generic map (width => 6, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_xu_ccflush_dc, + din(0) => func_slp_sl_thold_2_b(0), + din(1) => func_slp_nsl_thold_2_b, + din(2) => func_sl_thold_2_b(0), + din(3) => func_nsl_thold_2_b, + din(4) => fce_2_b(0), + din(5) => sg_2_b(0), + q(0) => func_slp_sl_thold_1, + q(1) => func_slp_nsl_thold_1, + q(2) => func_sl_thold_1, + q(3) => func_nsl_thold_1, + q(4) => fce_1, + q(5) => sg_1 + ); + + perv_1to0_reg: tri_plat + generic map (width => 6, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_xu_ccflush_dc, + din(0) => func_slp_sl_thold_1, + din(1) => func_slp_nsl_thold_1, + din(2) => func_sl_thold_1, + din(3) => func_nsl_thold_1, + din(4) => fce_1, + din(5) => sg_1, + q(0) => func_slp_sl_thold_0, + q(1) => func_slp_nsl_thold_0, + q(2) => func_sl_thold_0, + q(3) => func_nsl_thold_0, + q(4) => fce_0, + q(5) => sg_0 + ); + + perv_lcbor_func_nsl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_dc_b_b, + thold => func_nsl_thold_0, + sg => fce_0, + act_dis => tidn, + forcee => func_nsl_force, + thold_b => func_nsl_thold_0_b); + + perv_lcbor_func_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_dc_b_b, + thold => func_sl_thold_0, + sg => sg_0, + act_dis => tidn, + forcee => func_sl_force, + thold_b => func_sl_thold_0_b); + + perv_lcbor_func_slp_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_dc_b_b, + thold => func_slp_sl_thold_0, + sg => sg_0, + act_dis => tidn, + forcee => func_slp_sl_force, + thold_b => func_slp_sl_thold_0_b); + + perv_lcbor_func_slp_nsl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_dc_b_b, + thold => func_slp_nsl_thold_0, + sg => fce_0, + act_dis => tidn, + forcee => func_slp_nsl_force, + thold_b => func_slp_nsl_thold_0_b); + + so_force <= sg_0; + func_so_thold_0_b <= not func_sl_thold_0; + --------------------------------------------------------------------- + -- TEMP + --------------------------------------------------------------------- + dec_alu_rf1_mul_val <= fxa_fxb_rf1_mul_val; + dec_alu_rf1_div_val <= fxa_fxb_rf1_div_val; + + --------------------------------------------------------------------- + -- Multi-drops + --------------------------------------------------------------------- + xu_iu_spr_xer <= byp_xer_si; + dec_cpl_ex2_is_any_store_dac <= ex2_is_any_store_dac; + dec_cpl_ex2_is_any_load_dac <= ex2_is_any_load_dac; + + --------------------------------------------------------------------- + -- Bypass + --------------------------------------------------------------------- + xu_byp : entity work.xuq_byp(xuq_byp) + generic map( + threads => threads, + expand_type => expand_type, + regsize => regsize, + eff_ifar => eff_ifar) + port map( + nclk => nclk, + vdd => vdd, + gnd => gnd, + d_mode_dc => d_mode_dc_b, + delay_lclkr_dc => delay_lclkr_dc_b(4), + mpw1_dc_b => mpw1_dc_b_b(4), + mpw2_dc_b => mpw2_dc_b_b, + func_sl_force => func_sl_force, + func_sl_thold_0_b => func_sl_thold_0_b, + func_nsl_force => func_nsl_force, + func_nsl_thold_0_b => func_nsl_thold_0_b, + func_slp_sl_force => func_slp_sl_force, + func_slp_sl_thold_0_b => func_slp_sl_thold_0_b, + sg_0 => sg_0, + scan_in(0) => siv_55(1), + scan_in(1) => siv_56(1), + scan_out(0) => sov_55(1), + scan_out(1) => sov_56(1), + pc_xu_trace_bus_enable => pc_xu_trace_bus_enable, + dec_byp_ex3_instr_trace_val => dec_byp_ex3_instr_trace_val, + dec_byp_ex3_instr_trace_gate => dec_byp_ex3_instr_trace_gate, + fu_xu_ex4_cr_val => fu_xu_ex4_cr_val, + fu_xu_ex4_cr_noflush => fu_xu_ex4_cr_noflush, + fu_xu_ex4_cr0 => fu_xu_ex4_cr0, + fu_xu_ex4_cr0_bf => fu_xu_ex4_cr0_bf, + fu_xu_ex4_cr1 => fu_xu_ex4_cr1, + fu_xu_ex4_cr1_bf => fu_xu_ex4_cr1_bf, + fu_xu_ex4_cr2 => fu_xu_ex4_cr2, + fu_xu_ex4_cr2_bf => fu_xu_ex4_cr2_bf, + fu_xu_ex4_cr3 => fu_xu_ex4_cr3, + fu_xu_ex4_cr3_bf => fu_xu_ex4_cr3_bf, + mm_xu_cr0_eq_valid => mm_xu_cr0_eq_valid, + mm_xu_cr0_eq => mm_xu_cr0_eq, + an_ac_stcx_complete => an_ac_stcx_complete, + an_ac_stcx_pass => an_ac_stcx_pass, + an_ac_back_inv => an_ac_back_inv, + an_ac_back_inv_addr => an_ac_back_inv_addr, + an_ac_back_inv_target_bit3 => an_ac_back_inv_target_bit3, + xu_ex3_flush => xu_ex3_flush, + xu_ex4_flush => xu_ex4_flush, + xu_ex5_flush => xu_ex5_flush, + fxa_fxb_rf0_is_mfocrf => fxa_fxb_rf0_is_mfocrf, + dec_alu_rf1_sel => dec_alu_rf1_sel(2 to 2), + dec_byp_rf1_rs0_sel => dec_byp_rf1_rs0_sel, + dec_byp_rf1_rs1_sel => dec_byp_rf1_rs1_sel, + dec_byp_rf1_rs2_sel => dec_byp_rf1_rs2_sel, + dec_byp_rf1_imm => dec_byp_rf1_imm, + dec_byp_rf1_instr => dec_byp_rf1_instr, + dec_byp_rf1_cr_so_update => dec_byp_rf1_cr_so_update, + dec_byp_ex3_val => dec_byp_ex3_val, + dec_byp_rf1_cr_we => dec_byp_rf1_cr_we, + dec_byp_rf1_is_mcrf => dec_byp_rf1_is_mcrf, + dec_byp_rf1_use_crfld0 => dec_byp_rf1_use_crfld0, + dec_byp_rf1_alu_cmp => dec_byp_rf1_alu_cmp, + dec_byp_rf1_is_mtcrf => dec_byp_rf1_is_mtcrf, + dec_byp_rf1_is_mtocrf => dec_byp_rf1_is_mtocrf, + dec_byp_rf1_is_isel => dec_rf1_is_isel, + dec_byp_rf1_byp_val => dec_byp_rf1_byp_val, + dec_byp_ex4_is_eratsxr => dec_byp_ex4_is_eratsxr, + dec_rf1_tid => dec_rf1_tid, + dec_ex1_tid => dec_ex1_tid, + dec_ex2_tid => dec_ex2_tid, + dec_ex3_tid => dec_ex3_tid, + dec_ex5_tid => dec_ex5_tid, + dec_byp_rf1_ca_used => dec_byp_rf1_ca_used, + dec_byp_rf1_ov_used => dec_byp_rf1_ov_used, + dec_byp_ex4_dp_instr => dec_byp_ex4_dp_instr, + dec_byp_ex4_mtdp_val => dec_byp_ex4_mtdp_val, + dec_byp_ex4_mfdp_val => dec_byp_ex4_mfdp_val, + lsu_xu_ex4_mtdp_cr_status => lsu_xu_ex4_mtdp_cr_status, + lsu_xu_ex4_mfdp_cr_status => lsu_xu_ex4_mfdp_cr_status, + dec_byp_ex4_is_wchkall => dec_byp_ex4_is_wchkall, + lsu_xu_ex4_cr_upd => lsu_xu_ex4_cr_upd, + lsu_xu_ex5_cr_rslt => lsu_xu_ex5_cr_rslt, + fxa_fxb_rf1_do0 => fxa_fxb_rf1_do0, + fxa_fxb_rf1_do1 => fxa_fxb_rf1_do1, + fxa_fxb_rf1_do2 => fxa_fxb_rf1_do2, + spr_byp_ex4_is_mtxer => spr_byp_ex4_is_mtxer, + lsu_xu_rot_rel_data => lsu_xu_rot_rel_data, + alu_byp_ex2_cr_recform => alu_byp_ex2_cr_recform, + alu_byp_ex5_cr_mul => alu_byp_ex5_cr_mul, + alu_byp_ex3_cr_div => alu_byp_ex3_cr_div, + alu_byp_ex2_xer => alu_byp_ex2_xer, + alu_byp_ex5_xer_mul => alu_byp_ex5_xer_mul, + alu_byp_ex3_xer_div => alu_byp_ex3_xer_div, + alu_ex4_mul_done => alu_ex4_mul_done, + alu_ex2_div_done => alu_ex2_div_done, + mux_cpl_ex4_rt => mux_cpl_ex4_rt, + byp_spr_ex6_rt => byp_spr_ex6_rt, + fxb_fxa_ex7_wd0 => ex7_wd0, + xu_ex1_rs_is => xu_ex1_rs_is, + xu_ex1_ra_entry => xu_ex1_ra_entry, + xu_ex1_rb => xu_ex1_rb, + xu_lsu_ex1_store_data => xu_lsu_ex1_store_data, + fxu_spr_ex1_rs2 => fxu_spr_ex1_rs2, + fxu_spr_ex1_rs1 => fxu_spr_ex1_rs1, + fxu_spr_ex1_rs0 => fxu_spr_ex1_rs0, + byp_xer_si => byp_xer_si, + byp_dec_rf1_xer_ca => byp_dec_rf1_xer_ca, + byp_alu_ex1_rs0 => byp_alu_ex1_rs0, + byp_alu_ex1_rs1 => byp_alu_ex1_rs1, + byp_alu_ex1_mulsrc_0 => byp_alu_ex1_mulsrc_0, + byp_alu_ex1_mulsrc_1 => byp_alu_ex1_mulsrc_1, + byp_alu_ex1_divsrc_0 => byp_alu_ex1_divsrc_0, + byp_alu_ex1_divsrc_1 => byp_alu_ex1_divsrc_1, + byp_cpl_ex1_cr_bit => byp_cpl_ex1_cr_bit, + dec_byp_ex5_instr => dec_byp_ex5_instr, + dec_byp_rf0_act => dec_byp_rf0_act, + xu_lsu_ex1_add_src0 => xu_lsu_ex1_add_src0, + xu_lsu_ex1_add_src1 => xu_lsu_ex1_add_src1, + byp_alu_rf1_isel_fcn => byp_alu_rf1_isel_fcn, + spr_msr_cm => spr_msr_cm, + xu_ex4_rs_data => xu_ex4_rs_data, + dec_byp_ex1_spr_sel => dec_byp_ex1_spr_sel, + slowspr_val_in => slowspr_val_in, + slowspr_rw_in => slowspr_rw_in, + slowspr_etid_in => slowspr_etid_in, + slowspr_addr_in => slowspr_addr_in, + slowspr_data_in => slowspr_data_in, + slowspr_done_in => slowspr_done_in, + dec_byp_ex4_dcr_ack => dec_byp_ex4_dcr_ack, + an_ac_dcr_act => an_ac_dcr_act, + an_ac_dcr_read => an_ac_dcr_read, + an_ac_dcr_etid => an_ac_dcr_etid, + an_ac_dcr_data => an_ac_dcr_data, + an_ac_dcr_done => an_ac_dcr_done, + xu_iu_slowspr_done => xu_iu_slowspr_done, + mux_cpl_slowspr_done => mux_cpl_slowspr_done, + mux_cpl_slowspr_flush => mux_cpl_slowspr_flush, + lsu_xu_ex5_wren => lsu_xu_ex5_wren, + dec_byp_ex4_is_mfcr => dec_byp_ex4_is_mfcr, + spr_byp_ex4_is_mfxer => spr_byp_ex4_is_mfxer, + dec_byp_ex3_tlb_sel => dec_byp_ex3_tlb_sel, + alu_byp_ex1_log_rt => alu_byp_ex1_log_rt, + alu_byp_ex2_rt => alu_byp_ex2_rt, + cpl_byp_ex3_spr_rt => cpl_byp_ex3_spr_rt, + spr_byp_ex3_spr_rt => spr_byp_ex3_spr_rt, + fspr_byp_ex3_spr_rt => fspr_byp_ex3_spr_rt, + alu_byp_ex5_mul_rt => alu_byp_ex5_mul_rt, + alu_byp_ex3_div_rt => alu_byp_ex3_div_rt, + lsu_xu_ex4_tlb_data => lsu_xu_ex4_tlb_data, + iu_xu_ex4_tlb_data => iu_xu_ex4_tlb_data, + lsu_xu_rot_ex6_data_b => lsu_xu_rot_ex6_data_b, + xu_mm_derat_epn => xu_mm_derat_epn, + xu_pc_ram_data => xu_pc_ram_data, + byp_perf_tx_events => byp_perf_tx_events, + byp_grp0_debug => byp_grp0_debug, + byp_grp1_debug => byp_grp1_debug, + byp_grp2_debug => byp_grp2_debug, + byp_grp3_debug => byp_grp3_debug(15 to 87), + byp_grp4_debug => byp_grp4_debug(14 to 87), + byp_grp5_debug => byp_grp5_debug(15 to 87), + byp_grp6_debug => byp_grp6_debug, + byp_grp7_debug => byp_grp7_debug, + byp_grp8_debug => byp_grp8_debug + ); + + ------------------------------------------------------------------------------- + -- Decode + ------------------------------------------------------------------------------- + xu_dec_b : entity work.xuq_dec_b(xuq_dec_b) + generic map( + expand_type => expand_type, + threads => threads, + regmode => regmode, + regsize => regsize, + cl_size => cl_size, + real_data_add => real_data_add, + eff_ifar => eff_ifar) + port map( + nclk => nclk, + vdd => vdd, + gnd => gnd, + d_mode_dc => d_mode_dc_b, + delay_lclkr_dc => delay_lclkr_dc_b(4), + mpw1_dc_b => mpw1_dc_b_b(4), + mpw2_dc_b => mpw2_dc_b_b, + func_nsl_force => func_nsl_force, + func_nsl_thold_0_b => func_nsl_thold_0_b, + func_sl_force => func_sl_force, + func_sl_thold_0_b => func_sl_thold_0_b, + func_slp_sl_force => func_slp_sl_force, + func_slp_sl_thold_0_b => func_slp_sl_thold_0_b, + func_slp_nsl_force => func_slp_nsl_force, + func_slp_nsl_thold_0_b => func_slp_nsl_thold_0_b, + sg_0 => sg_0, + scan_in => siv_54(1), + scan_out => sov_54(1), + pc_xu_trace_bus_enable => pc_xu_trace_bus_enable, + pc_xu_instr_trace_mode => pc_xu_instr_trace_mode, + pc_xu_instr_trace_tid => pc_xu_instr_trace_tid, + dec_byp_ex3_instr_trace_val => dec_byp_ex3_instr_trace_val, + dec_byp_ex3_instr_trace_gate => dec_byp_ex3_instr_trace_gate, + dec_cpl_rf1_instr_trace_val => dec_cpl_rf1_instr_trace_val, + dec_cpl_rf1_instr_trace_type => dec_cpl_rf1_instr_trace_type, + dec_cpl_ex3_instr_trace_val => dec_cpl_ex3_instr_trace_val, + xu_lsu_ex2_instr_trace_val => xu_lsu_ex2_instr_trace_val, + cpl_dec_in_ucode => cpl_dec_in_ucode, + slowspr_val_in => slowspr_val_in, + slowspr_rw_in => slowspr_rw_in, + slowspr_etid_in => slowspr_etid_in, + dec_byp_ex4_dcr_ack => dec_byp_ex4_dcr_ack, + an_ac_dcr_act => an_ac_dcr_act, + an_ac_dcr_val => an_ac_dcr_val, + an_ac_dcr_read => an_ac_dcr_read, + an_ac_dcr_etid => an_ac_dcr_etid, + an_ac_dcr_ack => an_ac_dcr_ack, + mm_xu_mmucr0_0_tlbsel => mm_xu_mmucr0_0_tlbsel, + mm_xu_mmucr0_1_tlbsel => mm_xu_mmucr0_1_tlbsel, + mm_xu_mmucr0_2_tlbsel => mm_xu_mmucr0_2_tlbsel, + mm_xu_mmucr0_3_tlbsel => mm_xu_mmucr0_3_tlbsel, + xu_mm_rf1_is_tlbsxr => xu_mm_rf1_is_tlbsxr, + fxb_fxa_ex7_we0 => ex7_we0, + fxb_fxa_ex7_wa0 => ex7_wa0, + dec_byp_ex4_is_mfcr => dec_byp_ex4_is_mfcr, + dec_byp_ex3_tlb_sel => dec_byp_ex3_tlb_sel, + xu_rf1_flush => xu_rf1_flush, + xu_ex1_flush => xu_ex1_flush, + xu_ex2_flush => xu_ex2_flush, + xu_ex3_flush => xu_ex3_flush, + xu_ex4_flush => xu_ex4_flush, + xu_ex5_flush => xu_ex5_flush, + fxa_fxb_rf0_val => fxa_fxb_rf0_val, + fxa_fxb_rf0_issued => fxa_fxb_rf0_issued, + fxa_fxb_rf0_ucode_val => fxa_fxb_rf0_ucode_val, + fxa_fxb_rf0_act => fxa_fxb_rf0_act, + fxa_fxb_rf0_instr => fxa_fxb_rf0_instr, + fxa_fxb_rf0_tid => fxa_fxb_rf0_tid, + fxa_fxb_rf0_ta_vld => fxa_fxb_rf0_ta_vld, + fxa_fxb_rf0_ta => fxa_fxb_rf0_ta, + fxa_fxb_rf0_error => fxa_fxb_rf0_error, + fxa_fxb_rf0_match => fxa_fxb_rf0_match, + fxa_fxb_rf0_is_ucode => fxa_fxb_rf0_is_ucode, + fxa_fxb_rf0_gshare => fxa_fxb_rf0_gshare, + fxa_fxb_rf0_ifar => fxa_fxb_rf0_ifar, + fxa_fxb_rf0_s1_vld => fxa_fxb_rf0_s1_vld, + fxa_fxb_rf0_s1 => fxa_fxb_rf0_s1, + fxa_fxb_rf0_s2_vld => fxa_fxb_rf0_s2_vld, + fxa_fxb_rf0_s2 => fxa_fxb_rf0_s2, + fxa_fxb_rf0_s3_vld => fxa_fxb_rf0_s3_vld, + fxa_fxb_rf0_s3 => fxa_fxb_rf0_s3, + fxa_fxb_rf0_axu_instr_type => fxa_fxb_rf0_axu_instr_type, + fxa_fxb_rf0_axu_ld_or_st => fxa_fxb_rf0_axu_ld_or_st, + fxa_fxb_rf0_axu_store => fxa_fxb_rf0_axu_store, + fxa_fxb_rf0_axu_ldst_forcealign => fxa_fxb_rf0_axu_ldst_forcealign, + fxa_fxb_rf0_axu_ldst_forceexcept => fxa_fxb_rf0_axu_ldst_forceexcept, + fxa_fxb_rf0_axu_ldst_indexed => fxa_fxb_rf0_axu_ldst_indexed, + fxa_fxb_rf0_axu_ldst_tag => fxa_fxb_rf0_axu_ldst_tag, + fxa_fxb_rf0_axu_mftgpr => fxa_fxb_rf0_axu_mftgpr, + fxa_fxb_rf0_axu_mffgpr => fxa_fxb_rf0_axu_mffgpr, + fxa_fxb_rf0_axu_movedp => fxa_fxb_rf0_axu_movedp, + fxa_fxb_rf0_axu_ldst_size => fxa_fxb_rf0_axu_ldst_size, + fxa_fxb_rf0_axu_ldst_update => fxa_fxb_rf0_axu_ldst_update, + fxa_fxb_rf0_pred_update => fxa_fxb_rf0_pred_update, + fxa_fxb_rf0_pred_taken_cnt => fxa_fxb_rf0_pred_taken_cnt, + fxa_fxb_rf0_mc_dep_chk_val => fxa_fxb_rf0_mc_dep_chk_val, + fxa_fxb_rf0_xu_epid_instr => fxa_fxb_rf0_xu_epid_instr, + fxa_fxb_rf0_axu_is_extload => fxa_fxb_rf0_axu_is_extload, + fxa_fxb_rf0_axu_is_extstore => fxa_fxb_rf0_axu_is_extstore, + fxa_fxb_rf0_3src_instr => fxa_fxb_rf0_3src_instr, + fxa_fxb_rf0_gpr0_zero => fxa_fxb_rf0_gpr0_zero, + fxa_fxb_rf0_use_imm => fxa_fxb_rf0_use_imm, + fxa_fxb_rf1_muldiv_coll => fxa_fxb_rf1_muldiv_coll, + alu_dec_ex1_ipb_ba => alu_dec_ex1_ipb_ba, + alu_dec_div_need_hole => alu_dec_div_need_hole, + dec_byp_rf1_rs0_sel => dec_byp_rf1_rs0_sel, + dec_byp_rf1_rs1_sel => dec_byp_rf1_rs1_sel, + dec_byp_rf1_rs2_sel => dec_byp_rf1_rs2_sel, + dec_byp_rf1_instr => dec_byp_rf1_instr, + dec_byp_rf1_cr_so_update => dec_byp_rf1_cr_so_update, + dec_byp_ex3_val => dec_byp_ex3_val, + dec_byp_rf1_cr_we => dec_byp_rf1_cr_we, + dec_byp_rf1_is_mcrf => dec_byp_rf1_is_mcrf, + dec_byp_rf1_use_crfld0 => dec_byp_rf1_use_crfld0, + dec_byp_rf1_alu_cmp => dec_byp_rf1_alu_cmp, + dec_byp_rf1_is_mtcrf => dec_byp_rf1_is_mtcrf, + dec_byp_rf1_is_mtocrf => dec_byp_rf1_is_mtocrf, + dec_byp_rf1_byp_val => dec_byp_rf1_byp_val, + dec_byp_ex4_is_eratsxr => dec_byp_ex4_is_eratsxr, + dec_byp_rf1_ca_used => dec_byp_rf1_ca_used, + dec_byp_rf1_ov_used => dec_byp_rf1_ov_used, + dec_byp_ex4_dp_instr => dec_byp_ex4_dp_instr, + dec_byp_ex4_mtdp_val => dec_byp_ex4_mtdp_val, + dec_byp_ex4_mfdp_val => dec_byp_ex4_mfdp_val, + dec_byp_ex4_is_wchkall => dec_byp_ex4_is_wchkall, + dec_alu_rf1_act => dec_alu_rf1_act, + dec_alu_ex1_act => dec_alu_ex1_act, + dec_alu_rf1_sel => dec_alu_rf1_sel, + dec_alu_rf1_add_rs0_inv => dec_alu_rf1_add_rs0_inv, + dec_alu_rf1_add_ci => dec_alu_rf1_add_ci, + dec_alu_rf1_is_cmpl => dec_alu_rf1_is_cmpl, + dec_alu_rf1_tw_cmpsel => dec_alu_rf1_tw_cmpsel, + dec_rf1_is_isel => dec_rf1_is_isel, + dec_alu_rf1_xer_ov_update => dec_alu_rf1_xer_ov_update, + dec_alu_rf1_xer_ca_update => dec_alu_rf1_xer_ca_update, + dec_alu_rf1_sh_right => dec_alu_rf1_sh_right, + dec_alu_rf1_sh_word => dec_alu_rf1_sh_word, + dec_alu_rf1_sgnxtd_byte => dec_alu_rf1_sgnxtd_byte, + dec_alu_rf1_sgnxtd_half => dec_alu_rf1_sgnxtd_half, + dec_alu_rf1_sgnxtd_wd => dec_alu_rf1_sgnxtd_wd, + dec_alu_rf1_sra_dw => dec_alu_rf1_sra_dw, + dec_alu_rf1_sra_wd => dec_alu_rf1_sra_wd, + dec_alu_rf1_chk_shov_dw => dec_alu_rf1_chk_shov_dw, + dec_alu_rf1_chk_shov_wd => dec_alu_rf1_chk_shov_wd, + dec_alu_rf1_use_me_ins_hi => dec_alu_rf1_use_me_ins_hi, + dec_alu_rf1_use_me_ins_lo => dec_alu_rf1_use_me_ins_lo, + dec_alu_rf1_use_mb_ins_hi => dec_alu_rf1_use_mb_ins_hi, + dec_alu_rf1_use_mb_ins_lo => dec_alu_rf1_use_mb_ins_lo, + dec_alu_rf1_use_me_rb_hi => dec_alu_rf1_use_me_rb_hi, + dec_alu_rf1_use_me_rb_lo => dec_alu_rf1_use_me_rb_lo, + dec_alu_rf1_use_mb_rb_hi => dec_alu_rf1_use_mb_rb_hi, + dec_alu_rf1_use_mb_rb_lo => dec_alu_rf1_use_mb_rb_lo, + dec_alu_rf1_use_rb_amt_hi => dec_alu_rf1_use_rb_amt_hi, + dec_alu_rf1_use_rb_amt_lo => dec_alu_rf1_use_rb_amt_lo, + dec_alu_rf1_zm_ins => dec_alu_rf1_zm_ins, + dec_alu_rf1_log_fcn => dec_alu_rf1_log_fcn, + dec_alu_rf1_me_ins_b => dec_alu_rf1_me_ins_b, + dec_alu_rf1_mb_ins => dec_alu_rf1_mb_ins, + dec_alu_rf1_sh_amt => dec_alu_rf1_sh_amt, + dec_alu_rf1_mb_gt_me => dec_alu_rf1_mb_gt_me, + alu_ex3_mul_done => alu_ex3_mul_done, + alu_ex2_div_done => alu_ex2_div_done, + dec_alu_rf1_mul_recform => dec_alu_rf1_mul_recform, + dec_alu_rf1_div_recform => dec_alu_rf1_div_recform, + dec_alu_rf1_mul_ret => dec_alu_rf1_mul_ret, + dec_alu_rf1_mul_sign => dec_alu_rf1_mul_sign, + dec_alu_rf1_mul_size => dec_alu_rf1_mul_size, + dec_alu_rf1_mul_imm => dec_alu_rf1_mul_imm, + dec_alu_rf1_div_sign => dec_alu_rf1_div_sign, + dec_alu_rf1_div_size => dec_alu_rf1_div_size, + dec_alu_rf1_div_extd => dec_alu_rf1_div_extd, + dec_alu_ex1_is_cmp => dec_alu_ex1_is_cmp, + dec_alu_rf1_select_64bmode => dec_alu_rf1_select_64bmode, + dec_cpl_rf1_ifar => dec_cpl_rf1_ifar, + dec_byp_rf1_imm => dec_byp_rf1_imm, + dec_rf1_tid => dec_rf1_tid, + dec_ex1_tid => dec_ex1_tid, + dec_ex2_tid => dec_ex2_tid, + dec_ex3_tid => dec_ex3_tid, + dec_ex4_tid => dec_ex4_tid, + dec_ex5_tid => dec_ex5_tid, + dec_byp_ex1_spr_sel => dec_byp_ex1_spr_sel, + dec_spr_ex1_is_mtspr => dec_spr_ex1_is_mtspr, + dec_spr_ex1_is_mfspr => dec_spr_ex1_is_mfspr, + dec_cpl_rf1_val => dec_cpl_rf1_val, + dec_cpl_rf1_issued => dec_cpl_rf1_issued, + dec_spr_rf1_val => dec_spr_rf1_val, + dec_spr_ex4_val => dec_spr_ex4_val, + dec_fspr_ex1_instr => dec_fspr_ex1_instr, + dec_fspr_ex6_val => dec_fspr_ex6_val, + dec_cpl_rf1_instr => dec_cpl_rf1_instr, + dec_cpl_rf1_pred_taken_cnt => dec_cpl_rf1_pred_taken_cnt, + dec_cpl_ex1_is_slowspr_wr => dec_cpl_ex1_is_slowspr_wr, + dec_cpl_ex3_ddmh_en => dec_cpl_ex3_ddmh_en, + dec_cpl_ex3_back_inv => dec_cpl_ex3_back_inv, + dec_cpl_ex2_error => dec_cpl_ex2_error, + dec_cpl_ex2_match => dec_cpl_ex2_match, + dec_cpl_ex2_is_ucode => dec_cpl_ex2_is_ucode, + dec_cpl_ex3_is_any_store => dec_cpl_ex3_is_any_store, + ex2_is_any_store_dac => ex2_is_any_store_dac, + ex2_is_any_load_dac => ex2_is_any_load_dac, + dec_cpl_ex3_instr_priv => dec_cpl_ex3_instr_priv, + dec_cpl_ex1_epid_instr => dec_cpl_ex1_epid_instr, + dec_cpl_ex2_illegal_op => dec_cpl_ex2_illegal_op, + dec_cpl_ex3_mtdp_nr => dec_cpl_ex3_mtdp_nr, + dec_cpl_ex3_mult_coll => dec_cpl_ex3_mult_coll, + dec_cpl_ex3_tlb_illeg => dec_cpl_ex3_tlb_illeg, + dec_cpl_ex3_axu_instr_type => dec_cpl_ex3_axu_instr_type, + dec_cpl_ex3_instr_hypv => dec_cpl_ex3_instr_hypv, + dec_cpl_rf1_ucode_val => dec_cpl_rf1_ucode_val, + byp_dec_rf1_xer_ca => byp_dec_rf1_xer_ca, + spr_dec_rf1_epcr_dgtmi => spr_dec_rf1_epcr_dgtmi, + spr_dec_rf1_msr_ucle => spr_dec_rf1_msr_ucle, + spr_dec_rf1_msrp_uclep => spr_dec_rf1_msrp_uclep, + xu_lsu_rf0_act => xu_lsu_rf0_act, + xu_lsu_rf1_cache_acc => xu_lsu_rf1_cache_acc, + xu_lsu_rf1_axu_op_val => xu_lsu_rf1_axu_op_val, + xu_lsu_rf1_axu_ldst_falign => xu_lsu_rf1_axu_ldst_falign, + xu_lsu_rf1_axu_ldst_fexcpt => xu_lsu_rf1_axu_ldst_fexcpt, + xu_lsu_rf1_thrd_id => xu_lsu_rf1_thrd_id, + xu_lsu_rf1_optype1 => xu_lsu_rf1_optype1, + xu_lsu_rf1_optype2 => xu_lsu_rf1_optype2, + xu_lsu_rf1_optype4 => xu_lsu_rf1_optype4, + xu_lsu_rf1_optype8 => xu_lsu_rf1_optype8, + xu_lsu_rf1_optype16 => xu_lsu_rf1_optype16, + xu_lsu_rf1_optype32 => xu_lsu_rf1_optype32, + xu_lsu_rf1_target_gpr => xu_lsu_rf1_target_gpr, + xu_lsu_rf1_load_instr => xu_lsu_rf1_load_instr, + xu_lsu_rf1_store_instr => xu_lsu_rf1_store_instr, + xu_lsu_rf1_dcbf_instr => xu_lsu_rf1_dcbf_instr, + xu_lsu_rf1_sync_instr => xu_lsu_rf1_sync_instr, + xu_lsu_rf1_mbar_instr => xu_lsu_rf1_mbar_instr, + xu_lsu_rf1_l_fld => xu_lsu_rf1_l_fld, + xu_lsu_rf1_dcbi_instr => xu_lsu_rf1_dcbi_instr, + xu_lsu_rf1_dcbz_instr => xu_lsu_rf1_dcbz_instr, + xu_lsu_rf1_dcbt_instr => xu_lsu_rf1_dcbt_instr, + xu_lsu_rf1_dcbtst_instr => xu_lsu_rf1_dcbtst_instr, + xu_lsu_rf1_th_fld => xu_lsu_rf1_th_fld, + xu_lsu_rf1_dcbtls_instr => xu_lsu_rf1_dcbtls_instr, + xu_lsu_rf1_dcbtstls_instr => xu_lsu_rf1_dcbtstls_instr, + xu_lsu_rf1_dcblc_instr => xu_lsu_rf1_dcblc_instr, + xu_lsu_rf1_dcbst_instr => xu_lsu_rf1_dcbst_instr, + xu_lsu_rf1_icbi_instr => xu_lsu_rf1_icbi_instr, + xu_lsu_rf1_icblc_instr => xu_lsu_rf1_icblc_instr, + xu_lsu_rf1_icbt_instr => xu_lsu_rf1_icbt_instr, + xu_lsu_rf1_icbtls_instr => xu_lsu_rf1_icbtls_instr, + xu_lsu_rf1_tlbsync_instr => xu_lsu_rf1_tlbsync_instr, + xu_lsu_rf1_lock_instr => xu_lsu_rf1_lock_instr, + xu_lsu_rf1_mutex_hint => xu_lsu_rf1_mutex_hint, + xu_lsu_rf1_algebraic => xu_lsu_rf1_algebraic, + xu_lsu_rf1_byte_rev => xu_lsu_rf1_byte_rev, + xu_lsu_rf1_src_gpr => xu_lsu_rf1_src_gpr, + xu_lsu_rf1_src_axu => xu_lsu_rf1_src_axu, + xu_lsu_rf1_src_dp => xu_lsu_rf1_src_dp, + xu_lsu_rf1_targ_gpr => xu_lsu_rf1_targ_gpr, + xu_lsu_rf1_targ_axu => xu_lsu_rf1_targ_axu, + xu_lsu_rf1_targ_dp => xu_lsu_rf1_targ_dp, + xu_lsu_ex1_rotsel_ovrd => xu_lsu_ex1_rotsel_ovrd, + lsu_xu_ex5_wren => lsu_xu_ex5_wren, + lsu_xu_rel_wren => lsu_xu_rel_wren, + lsu_xu_rel_ta_gpr => lsu_xu_rel_ta_gpr, + lsu_xu_need_hole => lsu_xu_need_hole, + xu_lsu_rf1_src0_vld => xu_lsu_rf1_src0_vld, + xu_lsu_rf1_src0_reg => xu_lsu_rf1_src0_reg, + xu_lsu_rf1_src1_vld => xu_lsu_rf1_src1_vld, + xu_lsu_rf1_src1_reg => xu_lsu_rf1_src1_reg, + xu_lsu_rf1_targ_vld => xu_lsu_rf1_targ_vld, + xu_lsu_rf1_targ_reg => xu_lsu_rf1_targ_reg, + xu_bx_ex1_mtdp_val => xu_bx_ex1_mtdp_val, + xu_bx_ex1_mfdp_val => xu_bx_ex1_mfdp_val, + xu_bx_ex1_ipc_thrd => xu_bx_ex1_ipc_thrd, + xu_bx_ex2_ipc_ba => xu_bx_ex2_ipc_ba, + xu_bx_ex2_ipc_sz => xu_bx_ex2_ipc_sz, + xu_lsu_rf1_is_touch => xu_lsu_rf1_is_touch, + xu_lsu_rf1_is_msgsnd => xu_lsu_rf1_is_msgsnd, + xu_lsu_rf1_dci_instr => xu_lsu_rf1_dci_instr, + xu_lsu_rf1_ici_instr => xu_lsu_rf1_ici_instr, + xu_lsu_rf1_icswx_instr => xu_lsu_rf1_icswx_instr, + xu_lsu_rf1_icswx_dot_instr => xu_lsu_rf1_icswx_dot_instr, + xu_lsu_rf1_icswx_epid => xu_lsu_rf1_icswx_epid, + xu_lsu_rf1_ldawx_instr => xu_lsu_rf1_ldawx_instr, + xu_lsu_rf1_wclr_instr => xu_lsu_rf1_wclr_instr, + xu_lsu_rf1_wchk_instr => xu_lsu_rf1_wchk_instr, + xu_lsu_rf1_derat_ra_eq_ea => xu_lsu_rf1_derat_ra_eq_ea, + xu_lsu_rf1_cmd_act => xu_lsu_rf1_cmd_act, + xu_lsu_rf1_data_act => xu_lsu_rf1_data_act, + xu_lsu_rf1_mtspr_trace => xu_lsu_rf1_mtspr_trace, + xu_iu_rf1_val => xu_iu_rf1_val, + xu_rf1_val => xu_rf1_val, + xu_rf1_is_tlbre => xu_rf1_is_tlbre, + xu_rf1_is_tlbwe => xu_rf1_is_tlbwe, + xu_rf1_is_tlbsx => xu_rf1_is_tlbsx, + xu_rf1_is_tlbsrx => xu_rf1_is_tlbsrx, + xu_rf1_is_tlbivax => xu_rf1_is_tlbivax, + xu_rf1_is_tlbilx => xu_rf1_is_tlbilx, + xu_rf1_is_eratre => xu_rf1_is_eratre, + xu_rf1_is_eratwe => xu_rf1_is_eratwe, + xu_rf1_is_eratsx => xu_rf1_is_eratsx, + xu_rf1_is_eratsrx => xu_rf1_is_eratsrx, + xu_rf1_is_erativax => xu_rf1_is_erativax, + xu_rf1_is_eratilx => xu_rf1_is_eratilx, + xu_ex1_is_isync => xu_ex1_is_isync, + xu_ex1_is_csync => xu_ex1_is_csync, + xu_lsu_rf1_derat_act => xu_lsu_rf1_derat_act, + xu_lsu_rf1_derat_is_load => xu_lsu_rf1_derat_is_load, + xu_lsu_rf1_derat_is_store => xu_lsu_rf1_derat_is_store, + xu_rf1_ws => xu_rf1_ws, + xu_rf1_t => xu_rf1_t, + lsu_xu_is2_back_inv => lsu_xu_is2_back_inv, + lsu_xu_is2_back_inv_addr => lsu_xu_is2_back_inv_addr, + xu_iu_ex6_pri => xu_iu_ex6_pri, + xu_iu_ex6_pri_val => xu_iu_ex6_pri_val, + fxb_fxa_ex6_clear_barrier => fxb_fxa_ex6_clear_barrier, + xu_iu_ex5_gshare => xu_iu_ex5_gshare, + xu_iu_ex5_getNIA => xu_iu_ex5_getNIA, + xu_iu_need_hole => xu_iu_need_hole, + byp_xer_si => byp_xer_si, + xu_iu_ex5_val => xu_iu_ex5_val, + xu_iu_ex5_tid => xu_iu_ex5_tid, + xu_iu_ex5_br_update => xu_iu_ex5_br_update, + xu_iu_ex5_br_hist => xu_iu_ex5_br_hist, + xu_iu_ex5_bclr => xu_iu_ex5_bclr, + xu_iu_ex5_lk => xu_iu_ex5_lk, + xu_iu_ex5_bh => xu_iu_ex5_bh, + dec_byp_ex5_instr => dec_byp_ex5_instr, + dec_byp_rf0_act => dec_byp_rf0_act, + spr_msr_cm => spr_msr_cm, + spr_ccr2_notlb => spr_ccr2_notlb, + spr_dec_spr_xucr0_ssdly => spr_dec_spr_xucr0_ssdly, + spr_ccr2_en_attn => spr_ccr2_en_attn, + spr_ccr2_en_pc => spr_ccr2_en_pc, + spr_ccr2_en_ditc => spr_ccr2_en_ditc, + spr_ccr2_en_icswx => spr_ccr2_en_icswx, + spr_ccr2_en_dcr => spr_ccr2_en_dcr, + spr_xucr0_clkg_ctl => spr_xucr0_clkg_ctl, + spr_bit_act => spr_bit_act, + byp_grp3_debug => byp_grp3_debug(0 to 14), + byp_grp4_debug => byp_grp4_debug(0 to 13), + byp_grp5_debug => byp_grp5_debug(0 to 14), + dec_grp0_debug => dec_grp0_debug, + dec_grp1_debug => dec_grp1_debug + ); + + --------------------------------------------------------------------- + -- ALU + --------------------------------------------------------------------- + xu_alu : entity work.xuq_alu(xuq_alu) + generic map( + expand_type => expand_type, + regmode => regmode, + a2mode => a2mode, + threads => threads, + dc_size => dc_size, + fxu_synth => fxu_synth) + port map( + nclk => nclk, + vdd => vdd, + gnd => gnd, + d_mode_dc => d_mode_dc_b, + delay_lclkr_dc => delay_lclkr_dc_b(4), + mpw1_dc_b => mpw1_dc_b_b(4), + mpw2_dc_b => mpw2_dc_b_b, + func_sl_force => func_sl_force, + func_sl_thold_0_b => func_sl_thold_0_b, + sg_0 => sg_0, + scan_in(0) => siv_57(1), + scan_in(1) => siv_58(1), + scan_out(0) => sov_57(1), + scan_out(1) => sov_58(1), + spr_msr_cm => spr_msr_cm, + dec_alu_rf1_act => dec_alu_rf1_act, + dec_alu_ex1_act => dec_alu_ex1_act, + dec_alu_rf1_sel => dec_alu_rf1_sel, + dec_alu_rf1_add_rs0_inv => dec_alu_rf1_add_rs0_inv, + dec_alu_rf1_add_ci => dec_alu_rf1_add_ci, + dec_alu_rf1_is_cmpl => dec_alu_rf1_is_cmpl, + dec_alu_rf1_tw_cmpsel => dec_alu_rf1_tw_cmpsel, + dec_alu_rf1_xer_ov_update => dec_alu_rf1_xer_ov_update, + dec_alu_rf1_xer_ca_update => dec_alu_rf1_xer_ca_update, + dec_alu_rf1_sh_right => dec_alu_rf1_sh_right, + dec_alu_rf1_sh_word => dec_alu_rf1_sh_word, + dec_alu_rf1_sgnxtd_byte => dec_alu_rf1_sgnxtd_byte, + dec_alu_rf1_sgnxtd_half => dec_alu_rf1_sgnxtd_half, + dec_alu_rf1_sgnxtd_wd => dec_alu_rf1_sgnxtd_wd, + dec_alu_rf1_sra_dw => dec_alu_rf1_sra_dw, + dec_alu_rf1_sra_wd => dec_alu_rf1_sra_wd, + dec_alu_rf1_chk_shov_dw => dec_alu_rf1_chk_shov_dw, + dec_alu_rf1_chk_shov_wd => dec_alu_rf1_chk_shov_wd, + dec_alu_rf1_use_me_ins_hi => dec_alu_rf1_use_me_ins_hi, + dec_alu_rf1_use_me_ins_lo => dec_alu_rf1_use_me_ins_lo, + dec_alu_rf1_use_mb_ins_hi => dec_alu_rf1_use_mb_ins_hi, + dec_alu_rf1_use_mb_ins_lo => dec_alu_rf1_use_mb_ins_lo, + dec_alu_rf1_use_me_rb_hi => dec_alu_rf1_use_me_rb_hi, + dec_alu_rf1_use_me_rb_lo => dec_alu_rf1_use_me_rb_lo, + dec_alu_rf1_use_mb_rb_hi => dec_alu_rf1_use_mb_rb_hi, + dec_alu_rf1_use_mb_rb_lo => dec_alu_rf1_use_mb_rb_lo, + dec_alu_rf1_use_rb_amt_hi => dec_alu_rf1_use_rb_amt_hi, + dec_alu_rf1_use_rb_amt_lo => dec_alu_rf1_use_rb_amt_lo, + dec_alu_rf1_zm_ins => dec_alu_rf1_zm_ins, + dec_alu_rf1_log_fcn => dec_alu_rf1_log_fcn, + dec_alu_rf1_me_ins_b => dec_alu_rf1_me_ins_b, + dec_alu_rf1_mb_ins => dec_alu_rf1_mb_ins, + dec_alu_rf1_sh_amt => dec_alu_rf1_sh_amt, + dec_alu_rf1_mb_gt_me => dec_alu_rf1_mb_gt_me, + byp_alu_rf1_isel_fcn => byp_alu_rf1_isel_fcn, + fxa_fxb_ex1_hold_ctr_flush => fxa_fxb_ex1_hold_ctr_flush, + dec_ex2_tid => dec_ex2_tid, + dec_ex4_tid => dec_ex4_tid, + dec_alu_rf1_mul_recform => dec_alu_rf1_mul_recform, + dec_alu_rf1_div_recform => dec_alu_rf1_div_recform, + dec_alu_rf1_mul_val => dec_alu_rf1_mul_val, + dec_alu_rf1_mul_ret => dec_alu_rf1_mul_ret, + dec_alu_rf1_mul_sign => dec_alu_rf1_mul_sign, + dec_alu_rf1_mul_size => dec_alu_rf1_mul_size, + dec_alu_rf1_mul_imm => dec_alu_rf1_mul_imm, + dec_alu_rf1_div_val => dec_alu_rf1_div_val, + dec_alu_rf1_div_sign => dec_alu_rf1_div_sign, + dec_alu_rf1_div_size => dec_alu_rf1_div_size, + dec_alu_rf1_div_extd => dec_alu_rf1_div_extd, + fxa_fxb_rf1_div_ctr => fxa_fxb_rf1_div_ctr, + dec_alu_ex1_is_cmp => dec_alu_ex1_is_cmp, + dec_alu_rf1_select_64bmode => dec_alu_rf1_select_64bmode, + alu_cpl_ex3_trap_val => alu_cpl_ex3_trap_val, + byp_alu_ex1_rs0 => byp_alu_ex1_rs0, + byp_alu_ex1_rs1 => byp_alu_ex1_rs1, + byp_alu_ex1_mulsrc_0 => byp_alu_ex1_mulsrc_0, + byp_alu_ex1_mulsrc_1 => byp_alu_ex1_mulsrc_1, + byp_alu_ex1_divsrc_0 => byp_alu_ex1_divsrc_0, + byp_alu_ex1_divsrc_1 => byp_alu_ex1_divsrc_1, + xu_ex1_eff_addr_int => xu_ex1_eff_addr_int, + xu_ex2_eff_addr => xu_ex2_eff_addr, + alu_byp_ex5_mul_rt => alu_byp_ex5_mul_rt, + alu_byp_ex3_div_rt => alu_byp_ex3_div_rt, + alu_ex2_div_done => alu_ex2_div_done, + alu_dec_ex1_ipb_ba => alu_dec_ex1_ipb_ba, + alu_dec_div_need_hole => alu_dec_div_need_hole, + alu_ex3_mul_done => alu_ex3_mul_done, + alu_ex4_mul_done => alu_ex4_mul_done, + alu_byp_ex2_cr_recform => alu_byp_ex2_cr_recform, + alu_byp_ex5_cr_mul => alu_byp_ex5_cr_mul, + alu_byp_ex3_cr_div => alu_byp_ex3_cr_div, + alu_byp_ex2_xer => alu_byp_ex2_xer, + alu_byp_ex5_xer_mul => alu_byp_ex5_xer_mul, + alu_byp_ex3_xer_div => alu_byp_ex3_xer_div, + alu_byp_ex1_log_rt => alu_byp_ex1_log_rt, + alu_byp_ex2_rt => alu_byp_ex2_rt); + + --------------------------------------------------------------------- + -- SPR + --------------------------------------------------------------------- + mux_spr_ex2_rt <= alu_byp_ex2_rt; + alu_byp_ex2_rt_b <= alu_byp_ex2_rt; + + --------------------------------------------------------------------- + -- Pervasive + --------------------------------------------------------------------- + xu_perv : entity work.xuq_perv(xuq_perv) + generic map( + expand_type => expand_type) + port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + pc_xu_sg_3 => pc_xu_sg_3, + pc_xu_func_sl_thold_3 => pc_xu_func_sl_thold_3, + pc_xu_func_slp_sl_thold_3 => pc_xu_func_slp_sl_thold_3, + pc_xu_gptr_sl_thold_3 => pc_xu_gptr_sl_thold_3, + pc_xu_func_nsl_thold_3 => pc_xu_func_nsl_thold_3, + pc_xu_func_slp_nsl_thold_3 => pc_xu_func_slp_nsl_thold_3, + pc_xu_abst_sl_thold_3 => pc_xu_abst_sl_thold_3, + pc_xu_abst_slp_sl_thold_3 => pc_xu_abst_slp_sl_thold_3, + pc_xu_regf_sl_thold_3 => pc_xu_regf_sl_thold_3, + pc_xu_regf_slp_sl_thold_3 => pc_xu_regf_slp_sl_thold_3, + pc_xu_time_sl_thold_3 => pc_xu_time_sl_thold_3, + pc_xu_ary_nsl_thold_3 => pc_xu_ary_nsl_thold_3, + pc_xu_ary_slp_nsl_thold_3 => pc_xu_ary_slp_nsl_thold_3, + pc_xu_repr_sl_thold_3 => pc_xu_repr_sl_thold_3, + pc_xu_cfg_sl_thold_3 => pc_xu_cfg_sl_thold_3, + pc_xu_cfg_slp_sl_thold_3 => pc_xu_cfg_slp_sl_thold_3, + pc_xu_bolt_sl_thold_3 => pc_xu_bolt_sl_thold_3, + pc_xu_bo_enable_3 => pc_xu_bo_enable_3, + pc_xu_fce_3 => pc_xu_fce_3, + pc_xu_ccflush_dc => pc_xu_ccflush_dc, + an_ac_scan_diag_dc => an_ac_scan_diag_dc, + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b, + sg_2 => sg_2_b, + func_sl_thold_2 => func_sl_thold_2_b, + func_slp_sl_thold_2 => func_slp_sl_thold_2_b, + func_nsl_thold_2 => func_nsl_thold_2_b, + func_slp_nsl_thold_2 => func_slp_nsl_thold_2_b, + ary_nsl_thold_2 => ary_nsl_thold_2, + ary_slp_nsl_thold_2 => ary_slp_nsl_thold_2, + time_sl_thold_2 => time_sl_thold_2, + gptr_sl_thold_2 => gptr_sl_thold_2, + abst_sl_thold_2 => abst_sl_thold_2, + abst_slp_sl_thold_2 => abst_slp_sl_thold_2, + regf_sl_thold_2 => open, + repr_sl_thold_2 => repr_sl_thold_2, + cfg_sl_thold_2 => cfg_sl_thold_2, + cfg_slp_sl_thold_2 => cfg_slp_sl_thold_2, + regf_slp_sl_thold_2 => regf_slp_sl_thold_2, + bolt_sl_thold_2 => bolt_sl_thold_2, + bo_enable_2 => bo_enable_2, + sg_0 => open, + sg_1 => open, + ary_nsl_thold_0 => open, + abst_sl_thold_0 => open, + time_sl_thold_0 => open, + repr_sl_thold_0 => open, + fce_2 => fce_2_b, + clkoff_dc_b => clkoff_dc_b_b, + d_mode_dc => d_mode_dc_b, + delay_lclkr_dc => delay_lclkr_dc_b, + mpw1_dc_b => mpw1_dc_b_b, + mpw2_dc_b => mpw2_dc_b_b, + g6t_clkoff_dc_b => g6t_clkoff_dc_b, + g6t_d_mode_dc => g6t_d_mode_dc, + g6t_delay_lclkr_dc => g6t_delay_lclkr_dc, + g6t_mpw1_dc_b => g6t_mpw1_dc_b, + g6t_mpw2_dc_b => g6t_mpw2_dc_b, + g8t_clkoff_dc_b => g8t_clkoff_dc_b, + g8t_d_mode_dc => g8t_d_mode_dc, + g8t_delay_lclkr_dc => g8t_delay_lclkr_dc, + g8t_mpw1_dc_b => g8t_mpw1_dc_b, + g8t_mpw2_dc_b => g8t_mpw2_dc_b, + cam_clkoff_dc_b => cam_clkoff_dc_b, + cam_d_mode_dc => cam_d_mode_dc, + cam_delay_lclkr_dc => cam_delay_lclkr_dc, + cam_act_dis_dc => cam_act_dis_dc, + cam_mpw1_dc_b => cam_mpw1_dc_b, + cam_mpw2_dc_b => cam_mpw2_dc_b, + gptr_scan_in => gptr_scan_in, + gptr_scan_out => gptr_scan_out + ); + + --------------------------------------------------------------------- + -- Perf + --------------------------------------------------------------------- + xu_perf : entity work.xuq_perf(xuq_perf) + generic map( + expand_type => expand_type) + port map( + nclk => nclk, + func_sl_thold_2 => func_sl_thold_2_b(1), + sg_2 => sg_2_b(1), + d_mode_dc => d_mode_dc_b, + delay_lclkr_dc => delay_lclkr_dc_b(4), + mpw1_dc_b => mpw1_dc_b_b(4), + mpw2_dc_b => mpw2_dc_b_b, + clkoff_dc_b => clkoff_dc_b_b, + pc_xu_ccflush_dc => pc_xu_ccflush_dc, + scan_in => siv_56(2), + scan_out => sov_56(2), + cpl_perf_tx_events => cpl_perf_tx_events, + spr_perf_tx_events => spr_perf_tx_events, + byp_perf_tx_events => byp_perf_tx_events, + fxa_perf_muldiv_in_use => fxa_perf_muldiv_in_use, + pc_xu_event_bus_enable => pc_xu_event_bus_enable, + pc_xu_event_count_mode => pc_xu_event_count_mode, + pc_xu_event_mux_ctrls => pc_xu_event_mux_ctrls, + xu_pc_event_data => xu_pc_event_data, + spr_msr_gs => spr_msr_gs, + spr_msr_pr => spr_msr_pr, + -- Power + vdd => vdd, + gnd => gnd); + + --------------------------------------------------------------------- + -- Debug + --------------------------------------------------------------------- + + xu_fxu_debug : entity work.xuq_debug(xuq_debug) + generic map( + expand_type => expand_type) + port map( + nclk => nclk, + d_mode_dc => d_mode_dc_b, + delay_lclkr_dc => delay_lclkr_dc_b(4), + mpw1_dc_b => mpw1_dc_b_b(4), + mpw2_dc_b => mpw2_dc_b_b, + func_slp_sl_thold_0_b => func_slp_sl_thold_0_b, + func_slp_sl_force => func_slp_sl_force, + sg_0 => sg_0, + scan_in => siv_56(3), + scan_out => sov_56(3), + dec_byp_ex3_instr_trace_val => dec_byp_ex3_instr_trace_val, + pc_xu_trace_bus_enable => pc_xu_trace_bus_enable, + debug_mux_ctrls => fxu_debug_mux_ctrls, + trigger_data_in => fxu_trigger_data_in, + debug_data_in => fxu_debug_data_in, + trigger_data_out => fxu_trigger_data_out, + debug_data_out => fxu_debug_data_out, + dbg_group0 => dbg_group0, + dbg_group1 => dbg_group1, + dbg_group2 => dbg_group2, + dbg_group3 => dbg_group3, + dbg_group4 => dbg_group4, + dbg_group5 => dbg_group5, + dbg_group6 => dbg_group6, + dbg_group7 => dbg_group7, + dbg_group8 => dbg_group8, + dbg_group9 => dbg_group9, + dbg_group10 => dbg_group10, + dbg_group11 => dbg_group11, + dbg_group12 => dbg_group12, + dbg_group13 => dbg_group13, + dbg_group14 => dbg_group14, + dbg_group15 => dbg_group15, + trg_group0 => trg_group0, + trg_group1 => trg_group1, + trg_group2 => trg_group2, + trg_group3 => trg_group3, + vdd => vdd, + gnd => gnd + ); + + fxb_fxa_ex7_we0 <= ex7_we0; + fxb_fxa_ex7_wa0 <= ex7_wa0; + fxb_fxa_ex7_wd0 <= ex7_wd0; + + gpr_we0_debug(0 to 65) <= ex7_wd0(0 to 63) & ex7_we0 & ex7_wa0(0); + gpr_we0_debug(66 to 87) <= ex7_we0 & ex7_wa0 & (9 to 21=>'0'); + + dbg_group0 <= (others=>'0'); + dbg_group1 <= byp_grp1_debug; + dbg_group2 <= (others=>'0'); + dbg_group3 <= (others=>'0'); + dbg_group4 <= (others=>'0'); + dbg_group5 <= (others=>'0'); + dbg_group6 <= byp_grp6_debug; + dbg_group7 <= byp_grp7_debug; + dbg_group8 <= (0 to 21=>'0') & byp_grp8_debug; + dbg_group9 <= (others=>'0'); + dbg_group10 <= (others=>'0'); + dbg_group11 <= dec_grp1_debug; + dbg_group12 <= lsu_xu_data_debug0; + dbg_group13 <= lsu_xu_data_debug1; + dbg_group14 <= lsu_xu_data_debug2; + dbg_group15 <= (others=>'0'); + trg_group0 <= (others=>'0'); + trg_group1 <= (others=>'0'); + trg_group2 <= (others=>'0'); + trg_group3 <= (others=>'0'); + + mark_unused(byp_grp0_debug); + mark_unused(byp_grp2_debug); + mark_unused(byp_grp3_debug); + mark_unused(byp_grp4_debug); + mark_unused(byp_grp5_debug); + mark_unused(gpr_we0_debug); + mark_unused(dec_grp0_debug); + + --------------------------------------------------------------------- + -- SPR + --------------------------------------------------------------------- + xu_fxu_spr : entity work.xuq_fxu_spr(xuq_fxu_spr) + generic map ( + hvmode => hvmode, + a2mode => a2mode, + expand_type => expand_type, + threads => threads, + regsize => regsize, + eff_ifar => eff_ifar) + port map( + nclk => nclk, + d_mode_dc => d_mode_dc_b, + delay_lclkr_dc => delay_lclkr_dc_b(4), + mpw1_dc_b => mpw1_dc_b_b(4), + mpw2_dc_b => mpw2_dc_b_b, + func_sl_force => func_sl_force, + func_sl_thold_0_b => func_sl_thold_0_b, + func_nsl_force => func_nsl_force, + func_nsl_thold_0_b => func_nsl_thold_0_b, + sg_0 => sg_0, + scan_in => siv_57(2), + scan_out => sov_57(2), + ex1_tid => dec_ex1_tid, + ex1_instr => dec_fspr_ex1_instr, + dec_spr_ex1_is_mfspr => dec_spr_ex1_is_mfspr, + dec_spr_ex1_is_mtspr => dec_spr_ex1_is_mtspr, + ex6_val => dec_fspr_ex6_val, + ex6_spr_wd => byp_spr_ex6_rt, + fspr_byp_ex3_spr_rt => fspr_byp_ex3_spr_rt, + mux_spr_ex2_rt => alu_byp_ex2_rt_b, + ex2_is_any_load_dac => ex2_is_any_load_dac, + ex2_is_any_store_dac => ex2_is_any_store_dac, + xu_lsu_ex4_dvc1_en => xu_lsu_ex4_dvc1_en, + xu_lsu_ex4_dvc2_en => xu_lsu_ex4_dvc2_en, + lsu_xu_ex2_dvc1_st_cmp => lsu_xu_ex2_dvc1_st_cmp, + lsu_xu_ex2_dvc2_st_cmp => lsu_xu_ex2_dvc2_st_cmp, + lsu_xu_ex8_dvc1_ld_cmp => lsu_xu_ex8_dvc1_ld_cmp, + lsu_xu_ex8_dvc2_ld_cmp => lsu_xu_ex8_dvc2_ld_cmp, + lsu_xu_rel_dvc1_en => lsu_xu_rel_dvc1_en, + lsu_xu_rel_dvc2_en => lsu_xu_rel_dvc2_en, + lsu_xu_rel_dvc_thrd_id => lsu_xu_rel_dvc_thrd_id, + lsu_xu_rel_dvc1_cmp => lsu_xu_rel_dvc1_cmp, + lsu_xu_rel_dvc2_cmp => lsu_xu_rel_dvc2_cmp, + fxu_cpl_ex3_dac1r_cmpr_async => fxu_cpl_ex3_dac1r_cmpr_async, + fxu_cpl_ex3_dac2r_cmpr_async => fxu_cpl_ex3_dac2r_cmpr_async, + fxu_cpl_ex3_dac1r_cmpr => fxu_cpl_ex3_dac1r_cmpr, + fxu_cpl_ex3_dac2r_cmpr => fxu_cpl_ex3_dac2r_cmpr, + fxu_cpl_ex3_dac3r_cmpr => fxu_cpl_ex3_dac3r_cmpr, + fxu_cpl_ex3_dac4r_cmpr => fxu_cpl_ex3_dac4r_cmpr, + fxu_cpl_ex3_dac1w_cmpr => fxu_cpl_ex3_dac1w_cmpr, + fxu_cpl_ex3_dac2w_cmpr => fxu_cpl_ex3_dac2w_cmpr, + fxu_cpl_ex3_dac3w_cmpr => fxu_cpl_ex3_dac3w_cmpr, + fxu_cpl_ex3_dac4w_cmpr => fxu_cpl_ex3_dac4w_cmpr, + spr_bit_act => spr_bit_act, + spr_msr_pr => spr_msr_pr, + spr_msr_ds => spr_msr_ds, + spr_dbcr0_dac1 => spr_dbcr0_dac1, + spr_dbcr0_dac2 => spr_dbcr0_dac2, + spr_dbcr0_dac3 => spr_dbcr0_dac3, + spr_dbcr0_dac4 => spr_dbcr0_dac4, + spr_dbcr3_ivc => spr_dbcr3_ivc, + vdd => vdd, + gnd => gnd + ); + +-- Scan Repower +func_scan_rpwr_54i_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc_b(4), + thold_b => func_so_thold_0_b, + scin => siv_54(siv_54'left to siv_54'left), + scout => sov_54(sov_54'left to sov_54'left), + dout => open); +func_scan_rpwr_54o_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc_b(4), + thold_b => func_so_thold_0_b, + scin => siv_54(siv_54'right to siv_54'right), + scout => sov_54(sov_54'right to sov_54'right), + dout => open); +func_scan_rpwr_55i_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc_b(4), + thold_b => func_so_thold_0_b, + scin => siv_55(siv_55'left to siv_55'left), + scout => sov_55(sov_55'left to sov_55'left), + dout => open); +func_scan_rpwr_55o_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc_b(4), + thold_b => func_so_thold_0_b, + scin => siv_55(siv_55'right to siv_55'right), + scout => sov_55(sov_55'right to sov_55'right), + dout => open); +func_scan_rpwr_56i_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc_b(4), + thold_b => func_so_thold_0_b, + scin => siv_56(siv_56'left to siv_56'left), + scout => sov_56(sov_56'left to sov_56'left), + dout => open); +func_scan_rpwr_56o_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc_b(4), + thold_b => func_so_thold_0_b, + scin => siv_56(siv_56'right to siv_56'right), + scout => sov_56(sov_56'right to sov_56'right), + dout => open); +func_scan_rpwr_57i_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc_b(4), + thold_b => func_so_thold_0_b, + scin => siv_57(siv_57'left to siv_57'left), + scout => sov_57(sov_57'left to sov_57'left), + dout => open); +func_scan_rpwr_57o_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc_b(4), + thold_b => func_so_thold_0_b, + scin => siv_57(siv_57'right to siv_57'right), + scout => sov_57(sov_57'right to sov_57'right), + dout => open); +func_scan_rpwr_58i_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc_b(4), + thold_b => func_so_thold_0_b, + scin => siv_58(siv_58'left to siv_58'left), + scout => sov_58(sov_58'left to sov_58'left), + dout => open); +func_scan_rpwr_58o_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc_b(4), + thold_b => func_so_thold_0_b, + scin => siv_58(siv_58'right to siv_58'right), + scout => sov_58(sov_58'right to sov_58'right), + dout => open); + + +siv_54(0 to sov_54'right) <= sov_54(1 to sov_54'right) & func_scan_in(54); +func_scan_out(54) <= sov_54(0) and an_ac_scan_dis_dc_b; +siv_55(0 to sov_55'right) <= sov_55(1 to sov_55'right) & func_scan_in(55); +func_scan_out(55) <= sov_55(0) and an_ac_scan_dis_dc_b; +siv_56(0 to sov_56'right) <= sov_56(1 to sov_56'right) & func_scan_in(56); +func_scan_out(56) <= sov_56(0) and an_ac_scan_dis_dc_b; +siv_57(0 to sov_57'right) <= sov_57(1 to sov_57'right) & func_scan_in(57); +func_scan_out(57) <= sov_57(0) and an_ac_scan_dis_dc_b; +siv_58(0 to sov_58'right) <= sov_58(1 to sov_58'right) & func_scan_in(58); +func_scan_out(58) <= sov_58(0) and an_ac_scan_dis_dc_b; + + + + +end architecture xuq_fxu_b; + diff --git a/rel/src/vhdl/work/xuq_fxu_gpr.vhdl b/rel/src/vhdl/work/xuq_fxu_gpr.vhdl new file mode 100644 index 0000000..044223a --- /dev/null +++ b/rel/src/vhdl/work/xuq_fxu_gpr.vhdl @@ -0,0 +1,1295 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XUQ_FXU GPR Top +-- +LIBRARY ieee; USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY ibm; + USE ibm.std_ulogic_support.all; + USE ibm.std_ulogic_unsigned.all; + USE ibm.std_ulogic_function_support.all; +LIBRARY support; + USE support.power_logic_pkg.all; +LIBRARY tri; USE tri.tri_latches_pkg.all; + +entity xuq_fxu_gpr is + generic( + expand_type : integer := 2; + regsize : integer := 64; + threads : integer := 4); + port ( + -- Clocks and Scan Cntls + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + + -- Pervasive + d_mode_dc : in std_ulogic; + delay_lclkr_dc : in std_ulogic; + clkoff_dc_b : in std_ulogic; + mpw1_dc_b : in std_ulogic; + mpw2_dc_b : in std_ulogic; + func_sl_force : in std_ulogic; + func_sl_thold_0_b : in std_ulogic; + func_nsl_force : in std_ulogic; + func_nsl_thold_0_b : in std_ulogic; + sg_0 : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + an_ac_scan_diag_dc : in std_ulogic; + + -- ABIST/LBIST + lbist_en : in std_ulogic; + abist_en : in std_ulogic; + abist_raw_dc_b : in std_ulogic; + r0e_sel_lbist : in std_ulogic; + r1e_sel_lbist : in std_ulogic; + r0e_abist_comp_en : in std_ulogic; + r1e_abist_comp_en : in std_ulogic; + r0e_addr_abist : in std_ulogic_vector(2 to 9); + r1e_addr_abist : in std_ulogic_vector(2 to 9); + r0e_en_abist : in std_ulogic; + r1e_en_abist : in std_ulogic; + w0e_addr_abist : in std_ulogic_vector(2 to 9); + w0l_addr_abist : in std_ulogic_vector(2 to 9); + w0e_en_abist : in std_ulogic; + w0l_en_abist : in std_ulogic; + w0e_data_abist : in std_ulogic_vector(0 to 3); + w0l_data_abist : in std_ulogic_vector(0 to 3); + + -- BOLT-ON + bo_enable_2 : in std_ulogic; -- general bolt-on enable, probably DC + pc_xu_bo_reset : in std_ulogic; -- execute sticky bit decode + pc_xu_bo_unload : in std_ulogic; + pc_xu_bo_load : in std_ulogic; + pc_xu_bo_shdata : in std_ulogic; -- shift data for timing write + pc_xu_bo_select : in std_ulogic_vector(0 to 1); -- select for mask and hier writes + xu_pc_bo_fail : out std_ulogic_vector(0 to 1); -- fail/no-fix reg + xu_pc_bo_diagout : out std_ulogic_vector(0 to 1); + + -- LCB Signals + lcb_fce_0 : in std_ulogic; + lcb_scan_diag_dc : in std_ulogic; + lcb_scan_dis_dc_b : in std_ulogic; + lcb_sg_0 : in std_ulogic; + lcb_abst_sl_thold_0 : in std_ulogic; + lcb_ary_nsl_thold_0 : in std_ulogic; + lcb_time_sl_thold_0 : in std_ulogic; + lcb_gptr_sl_thold_0 : in std_ulogic; + lcb_bolt_sl_thold_0 : in std_ulogic; + + -- Scanchains + gpr_gptr_scan_in : in std_ulogic; + gpr_gptr_scan_out : out std_ulogic; + gpr_time_scan_in : in std_ulogic; + gpr_time_scan_out : out std_ulogic; + gpr_abst_scan_in : in std_ulogic; + gpr_abst_scan_out : out std_ulogic; + + -- Parity + pc_xu_inj_regfile_parity : in std_ulogic_vector(0 to 3); + xu_pc_err_regfile_parity : out std_ulogic_vector(0 to threads-1); + xu_pc_err_regfile_ue : out std_ulogic_vector(0 to 3); + gpr_cpl_ex3_regfile_err_det : out std_ulogic; + cpl_gpr_regfile_seq_beg : in std_ulogic; + gpr_cpl_regfile_seq_end : out std_ulogic; + + -- Read Port: 0 + r0_en : in std_ulogic; -- Read enable + r0_addr_func : in std_ulogic_vector(0 to 7); -- Read Address + r0_data_out : out std_ulogic_vector(64-regsize to 69+regsize/8); -- Read Data + + -- Read Port: 1 + r1_en : in std_ulogic; + r1_addr_func : in std_ulogic_vector(0 to 7); + r1_data_out : out std_ulogic_vector(64-regsize to 69+regsize/8); + + -- Read Port: 2 + r2_en : in std_ulogic; + r2_addr_func : in std_ulogic_vector(0 to 7); + r2_data_out : out std_ulogic_vector(64-regsize to 69+regsize/8); + + -- Read Port: 3 + r3_en : in std_ulogic := '0'; + r3_addr_func : in std_ulogic_vector(0 to 7) := "00000000"; + r3_data_out : out std_ulogic_vector(64-regsize to 69+regsize/8) := (others=>'0'); + + -- Write Port: Early + w_e_act : in std_ulogic; + w_e_addr_func : in std_ulogic_vector(0 to 7); + w_e_data_func : in std_ulogic_vector(64-regsize to 63); + + -- Write Port: Late + w_l_act : in std_ulogic; + w_l_addr_func : in std_ulogic_vector(0 to 7); + w_l_data_func : in std_ulogic_vector(64-regsize to 69+regsize/8); + + gpr_debug : out std_ulogic_vector(0 to 21) + + ); + + -- synopsys translate_off + -- synopsys translate_on +end xuq_fxu_gpr; + +architecture xuq_fxu_gpr of xuq_fxu_gpr is + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + subtype s3 is std_ulogic_vector(0 to 2); + + --------------------------------------------------------------------- + -- Signals + --------------------------------------------------------------------- + signal siv_abst, sov_abst : std_ulogic_vector(0 to 7); + signal siv_time, sov_time : std_ulogic_vector(0 to 1); + + signal lcb_clkoff_dc_b : std_ulogic_vector(0 to 1); + signal lcb_delay_lclkr_dc : std_ulogic_vector(0 to 4); + signal lcb_act_dis_dc : std_ulogic; + signal lcb_d_mode_dc : std_ulogic; + signal lcb_mpw1_dc_b : std_ulogic_vector(0 to 4); + signal lcb_mpw2_dc_b : std_ulogic; + signal arr_delay_lclkr_dc : std_ulogic_vector(0 to 9); + signal arr_mpw1_dc_b : std_ulogic_vector(1 to 9); + signal r0_array_data : std_ulogic_vector(64-regsize to 69+regsize/8); + signal r1_array_data : std_ulogic_vector(64-regsize to 69+regsize/8); + signal r2_array_data : std_ulogic_vector(64-regsize to 69+regsize/8); + signal r3_array_data : std_ulogic_vector(64-regsize to 69+regsize/8); + signal gpr_do0_par : std_ulogic_vector(8-regsize/8 to 7); + signal gpr_do0_par_err : std_ulogic; + signal gpr_do1_par : std_ulogic_vector(8-regsize/8 to 7); + signal gpr_do1_par_err : std_ulogic; + signal gpr_do2_par : std_ulogic_vector(8-regsize/8 to 7); + signal gpr_do2_par_err : std_ulogic; + signal gpr_do3_par : std_ulogic_vector(8-regsize/8 to 7); + signal gpr_do3_par_err : std_ulogic; + signal r0_read_enable : std_ulogic; + signal r1_read_enable : std_ulogic; + signal r2_read_enable : std_ulogic; + signal r3_read_enable : std_ulogic; + signal r0_read_addr : std_ulogic_vector(0 to 7); + signal r1_read_addr : std_ulogic_vector(0 to 7); + signal r2_read_addr : std_ulogic_vector(0 to 7); + signal r3_read_addr : std_ulogic_vector(0 to 7); + signal w_e_data, w0e_data, w1e_data : std_ulogic_vector(64-regsize to 69+regsize/8); + signal w_l_data : std_ulogic_vector(64-regsize to 69+regsize/8); + signal w_e_enable : std_ulogic; + signal w_l_enable : std_ulogic; + signal w_e_addr : std_ulogic_vector(0 to 7); + signal w_l_addr : std_ulogic_vector(0 to 7); + signal w_e_data_func_par : std_ulogic_vector(64-regsize to 69+regsize/8); + signal w_e_parity : std_ulogic_vector(8-regsize/8 to 7); + signal perr_sm_next : std_ulogic_vector(0 to 4); + signal perr_write_data_sel : std_ulogic_vector(0 to 1); + signal tri_err_in : std_ulogic_vector(0 to 7); + signal tri_err_out : std_ulogic_vector(0 to 7); + signal r0_byp_r : std_ulogic; + signal r1_byp_r : std_ulogic; + signal r2_byp_r : std_ulogic; + signal r3_byp_r : std_ulogic; + signal perr_tid : std_ulogic_vector(0 to threads-1); + signal perr_ue, perr_ce : std_ulogic; + signal w_e_tid : std_ulogic_vector(0 to threads-1); + signal perr_inj : std_ulogic; + + --------------------------------------------------------------------- + -- Latches + --------------------------------------------------------------------- + signal ex3_regfile_err_det_q, ex2_regfile_err_det : std_ulogic; -- input=>ex2_regfile_err_det , act=>tiup , scan=>Y, needs_sreset=>0 + signal gpr_do0_par_err_q : std_ulogic; -- input=>gpr_do0_par_err , act=>tiup , scan=>Y, needs_sreset=>0 + signal gpr_do1_par_err_q : std_ulogic; -- input=>gpr_do1_par_err , act=>tiup , scan=>Y, needs_sreset=>0 + signal gpr_do2_par_err_q : std_ulogic; -- input=>gpr_do2_par_err , act=>tiup , scan=>Y, needs_sreset=>0 + signal gpr_do3_par_err_q : std_ulogic; -- input=>gpr_do3_par_err , act=>tiup , scan=>Y, needs_sreset=>0 + signal r0_array_data_q : std_ulogic_vector(0 to 63+regsize/8); -- input=>r0_array_data , act=>r0_read_enable_q , scan=>Y, needs_sreset=>0 + signal r0_read_addr_q : std_ulogic_vector(0 to 7); -- input=>r0_read_addr , act=>r0_read_enable , scan=>N, needs_sreset=>0 + signal r0_read_addr_1_q : std_ulogic_vector(0 to 7); -- input=>r0_read_addr_q , act=>r0_read_enable_q , scan=>Y, needs_sreset=>0 + signal r0_read_addr_2_q : std_ulogic_vector(0 to 7); -- input=>r0_read_addr_1_q , act=>r0_read_val_q , scan=>N, needs_sreset=>0 + signal r0_read_enable_q : std_ulogic; -- input=>r0_read_enable , act=>tiup , scan=>N, needs_sreset=>1 + signal r0_read_val_q : std_ulogic; -- input=>r0_read_enable_q , act=>tiup , scan=>Y, needs_sreset=>1 + signal r1_array_data_q : std_ulogic_vector(0 to 63+regsize/8); -- input=>r1_array_data , act=>r1_read_enable_q , scan=>Y, needs_sreset=>0 + signal r1_read_addr_q : std_ulogic_vector(0 to 7); -- input=>r1_read_addr , act=>r1_read_enable , scan=>N, needs_sreset=>0 + signal r1_read_addr_1_q : std_ulogic_vector(0 to 7); -- input=>r1_read_addr_q , act=>r1_read_enable_q , scan=>Y, needs_sreset=>0 + signal r1_read_addr_2_q : std_ulogic_vector(0 to 7); -- input=>r1_read_addr_1_q , act=>r1_read_val_q , scan=>N, needs_sreset=>0 + signal r1_read_enable_q : std_ulogic; -- input=>r1_read_enable , act=>tiup , scan=>N, needs_sreset=>1 + signal r1_read_val_q : std_ulogic; -- input=>r1_read_enable_q , act=>tiup , scan=>Y, needs_sreset=>1 + signal r2_array_data_q : std_ulogic_vector(0 to 63+regsize/8); -- input=>r2_array_data , act=>r2_read_enable_q , scan=>Y, needs_sreset=>0 + signal r2_read_addr_q : std_ulogic_vector(0 to 7); -- input=>r2_read_addr , act=>r2_read_enable , scan=>N, needs_sreset=>0 + signal r2_read_addr_1_q : std_ulogic_vector(0 to 7); -- input=>r2_read_addr_q , act=>r2_read_enable_q , scan=>Y, needs_sreset=>0 + signal r2_read_addr_2_q : std_ulogic_vector(0 to 7); -- input=>r2_read_addr_1_q , act=>r2_read_val_q , scan=>N, needs_sreset=>0 + signal r2_read_enable_q : std_ulogic; -- input=>r2_read_enable , act=>tiup , scan=>N, needs_sreset=>1 + signal r2_read_val_q : std_ulogic; -- input=>r2_read_enable_q , act=>tiup , scan=>Y, needs_sreset=>1 + signal r3_array_data_q : std_ulogic_vector(0 to 63+regsize/8); -- input=>r3_array_data , act=>r3_read_enable_q , scan=>Y, needs_sreset=>0 + signal r3_read_enable_q : std_ulogic; -- input=>r3_read_enable , act=>tiup , scan=>N, needs_sreset=>1 + signal r3_read_val_q : std_ulogic; -- input=>r3_read_enable_q , act=>tiup , scan=>Y, needs_sreset=>1 + signal perr_addr_q, perr_addr_d : std_ulogic_vector(0 to 7); -- input=>perr_addr_d , act=>tiup , scan=>Y, needs_sreset=>0 + signal perr_direction_q, perr_direction_d : std_ulogic_vector(0 to 1); -- input=>perr_direction_d , act=>tiup , scan=>Y, needs_sreset=>0 + signal perr_inj_q : std_ulogic_vector(0 to 3); -- input=>pc_xu_inj_regfile_parity , act=>tiup , scan=>Y, needs_sreset=>0 + signal perr_sm_q, perr_sm_d : std_ulogic_vector(0 to 4); -- input=>perr_sm_d , act=>tiup , scan=>Y, needs_sreset=>1, init=>2**(perr_sm_q'length-1) + signal perr_write_data_q, perr_write_data_d : std_ulogic_vector(64-regsize to 69+regsize/8);-- input=>perr_write_data_d , act=>perr_sm_q(2) , scan=>Y, needs_sreset=>0 + signal err_regfile_parity_q, err_regfile_parity_d : std_ulogic_vector(0 to threads-1); -- input=>err_regfile_parity_d , act=>tiup , scan=>Y, needs_sreset=>1 + signal err_regfile_ue_q, err_regfile_ue_d : std_ulogic_vector(0 to threads-1); -- input=>err_regfile_ue_d , act=>tiup , scan=>Y, needs_sreset=>1 + signal err_seq_0_q : std_ulogic; -- input=>cpl_gpr_regfile_seq_beg , act=>tiup , scan=>Y, needs_sreset=>1 + signal wthru_r0_w_e_q, wthru_r0_w_e_d : std_ulogic; -- input=>wthru_r0_w_e_d , act=>tiup , scan=>Y, needs_sreset=>1 + signal wthru_r0_w_l_q, wthru_r0_w_l_d : std_ulogic; -- input=>wthru_r0_w_l_d , act=>tiup , scan=>Y, needs_sreset=>1 + signal wthru_r1_w_e_q, wthru_r1_w_e_d : std_ulogic; -- input=>wthru_r1_w_e_d , act=>tiup , scan=>Y, needs_sreset=>1 + signal wthru_r1_w_l_q, wthru_r1_w_l_d : std_ulogic; -- input=>wthru_r1_w_l_d , act=>tiup , scan=>Y, needs_sreset=>1 + signal wthru_r2_w_e_q, wthru_r2_w_e_d : std_ulogic; -- input=>wthru_r2_w_e_d , act=>tiup , scan=>Y, needs_sreset=>1 + signal wthru_r2_w_l_q, wthru_r2_w_l_d : std_ulogic; -- input=>wthru_r2_w_l_d , act=>tiup , scan=>Y, needs_sreset=>1 + signal wthru_r3_w_e_q, wthru_r3_w_e_d : std_ulogic; -- input=>wthru_r3_w_e_d , act=>tiup , scan=>Y, needs_sreset=>1 + signal wthru_r3_w_l_q, wthru_r3_w_l_d : std_ulogic; -- input=>wthru_r3_w_l_d , act=>tiup , scan=>Y, needs_sreset=>1 + --------------------------------------------------------------------- + -- Scanchain + --------------------------------------------------------------------- + constant ex3_regfile_err_det_offset : integer := 0; + constant gpr_do0_par_err_offset : integer := ex3_regfile_err_det_offset + 1; + constant gpr_do1_par_err_offset : integer := gpr_do0_par_err_offset + 1; + constant gpr_do2_par_err_offset : integer := gpr_do1_par_err_offset + 1; + constant gpr_do3_par_err_offset : integer := gpr_do2_par_err_offset + 1; + constant r0_array_data_offset : integer := gpr_do3_par_err_offset + 1; + constant r0_read_addr_1_offset : integer := r0_array_data_offset + r0_array_data_q'length; + constant r0_read_val_offset : integer := r0_read_addr_1_offset + r0_read_addr_1_q'length; + constant r1_array_data_offset : integer := r0_read_val_offset + 1; + constant r1_read_addr_1_offset : integer := r1_array_data_offset + r1_array_data_q'length; + constant r1_read_val_offset : integer := r1_read_addr_1_offset + r1_read_addr_1_q'length; + constant r2_array_data_offset : integer := r1_read_val_offset + 1; + constant r2_read_addr_1_offset : integer := r2_array_data_offset + r2_array_data_q'length; + constant r2_read_val_offset : integer := r2_read_addr_1_offset + r2_read_addr_1_q'length; + constant r3_array_data_offset : integer := r2_read_val_offset + 1; + constant r3_read_val_offset : integer := r3_array_data_offset + r3_array_data_q'length; + constant perr_addr_offset : integer := r3_read_val_offset + 1; + constant perr_direction_offset : integer := perr_addr_offset + perr_addr_q'length; + constant perr_inj_offset : integer := perr_direction_offset + perr_direction_q'length; + constant perr_sm_offset : integer := perr_inj_offset + perr_inj_q'length; + constant perr_write_data_offset : integer := perr_sm_offset + perr_sm_q'length; + constant err_regfile_parity_offset : integer := perr_write_data_offset + perr_write_data_q'length; + constant err_regfile_ue_offset : integer := err_regfile_parity_offset + err_regfile_parity_q'length; + constant err_seq_0_offset : integer := err_regfile_ue_offset + err_regfile_ue_q'length; + constant wthru_r0_w_e_offset : integer := err_seq_0_offset + 1; + constant wthru_r0_w_l_offset : integer := wthru_r0_w_e_offset + 1; + constant wthru_r1_w_e_offset : integer := wthru_r0_w_l_offset + 1; + constant wthru_r1_w_l_offset : integer := wthru_r1_w_e_offset + 1; + constant wthru_r2_w_e_offset : integer := wthru_r1_w_l_offset + 1; + constant wthru_r2_w_l_offset : integer := wthru_r2_w_e_offset + 1; + constant wthru_r3_w_e_offset : integer := wthru_r2_w_l_offset + 1; + constant wthru_r3_w_l_offset : integer := wthru_r3_w_e_offset + 1; + constant scan_right : integer := wthru_r3_w_l_offset + 1; + signal siv : std_ulogic_vector(0 to scan_right-1); + signal sov : std_ulogic_vector(0 to scan_right-1); + +begin + + + --------------------------------------------------------------------- + -- Pervasive + --------------------------------------------------------------------- + tri_err_in <= err_regfile_parity_q & err_regfile_ue_q; + + xu_gpr_err_rpt : entity tri.tri_direct_err_rpt(tri_direct_err_rpt) + generic map( + width => 8, + expand_type => expand_type) + port map( + vd => vdd, + gd => gnd, + err_in => tri_err_in, + err_out => tri_err_out); + + xu_pc_err_regfile_parity <= tri_err_out(0 to 3); + xu_pc_err_regfile_ue <= tri_err_out(4 to 7); + + + --------------------------------------------------------------------- + -- Parity Generation / Error injection + --------------------------------------------------------------------- +gpr_64b_par_gen : if regsize = 64 generate + w_e_parity(0) <= xor_reduce(w_e_data_func(0 to 7 )); + w_e_parity(1) <= xor_reduce(w_e_data_func(8 to 15)); + w_e_parity(2) <= xor_reduce(w_e_data_func(16 to 23)); + w_e_parity(3) <= xor_reduce(w_e_data_func(24 to 31)); + w_e_parity(4) <= xor_reduce(w_e_data_func(32 to 39)); + w_e_parity(5) <= xor_reduce(w_e_data_func(40 to 47)); + w_e_parity(6) <= xor_reduce(w_e_data_func(48 to 55)); + w_e_parity(7) <= xor_reduce(w_e_data_func(56 to 63)); +end generate; + +gpr_32b_par_gen : if regsize = 32 generate + w_e_parity(4) <= xor_reduce(w_e_data_func(32 to 39)); + w_e_parity(5) <= xor_reduce(w_e_data_func(40 to 47)); + w_e_parity(6) <= xor_reduce(w_e_data_func(48 to 55)); + w_e_parity(7) <= xor_reduce(w_e_data_func(56 to 63)); +end generate; + + --------------------------------------------------------------------- + -- Assign outputs + --------------------------------------------------------------------- + r0_data_out <= r0_array_data(64-regsize to 69+regsize/8); + r1_data_out <= r1_array_data(64-regsize to 69+regsize/8); + r2_data_out <= r2_array_data(64-regsize to 69+regsize/8); + r3_data_out <= r3_array_data(64-regsize to 69+regsize/8); + +gpr_64b_data_out : if regsize = 64 generate + w_e_data_func_par <= w_e_data_func & w_e_parity & "000000"; + + with perr_sm_q(3) select + w_e_data <= w_e_data_func_par when '0', + perr_write_data_q when others; + + w_l_data <= w_l_data_func; +end generate; +gpr_32b_data_out : if regsize = 32 generate + w_e_data_func_par <= w_e_data_func & w_e_parity & "0000000000"; + + with perr_sm_q(3) select + w_e_data <= (0 to 31 => tidn) & w_e_data_func_par when '0', + (0 to 31 => tidn) & perr_write_data_q when others; + + w_l_data <= (0 to 31 => tidn) & w_l_data_func; +end generate; + + with w_e_addr_func(6 to 7) select + w_e_tid <= "0100" when "01", + "0010" when "10", + "0001" when "11", + "1000" when others; + + perr_inj <= or_reduce(w_e_tid and perr_inj_q) and perr_sm_q(0); + + w0e_data(64-regsize) <= w_e_data(64-regsize) xor perr_inj; + w0e_data(65-regsize to 69+regsize/8) <= w_e_data(65-regsize to 69+regsize/8); + + w1e_data(64-regsize) <= w_e_data(64-regsize); + w1e_data(65-regsize to 69+regsize/8) <= w_e_data(65-regsize to 69+regsize/8); + + --------------------------------------------------------------------- + -- Read Enables and Addresses + --------------------------------------------------------------------- + -- Ports 1 and 3 are used for reading out data for error correction. + -- Enables + r0_read_enable <= r0_en or lbist_en; + with perr_sm_q(1) select + r1_read_enable <=(r1_en or lbist_en) when '0', + '1' when others; + r2_read_enable <=(r2_en or lbist_en); + with perr_sm_q(1) select + r3_read_enable <=(r3_en or lbist_en) when '0', + '1' when others; + + -- Addresses + r0_read_addr <= r0_addr_func; + with perr_sm_q(1) select + r1_read_addr <= r1_addr_func when '0', + perr_addr_q when others; + r2_read_addr <= r2_addr_func; + with perr_sm_q(1) select + r3_read_addr <= (others=>tidn) when '0', + perr_addr_q when others; + + --------------------------------------------------------------------- + -- Writeback + --------------------------------------------------------------------- + -- Use early port to write back parity data + with perr_sm_q(3) select + w_e_enable <= w_e_act when '0', + '1' when others; + w_l_enable <= w_l_act; + + with perr_sm_q(3) select + w_e_addr <= w_e_addr_func when '0', + perr_addr_q when others; + w_l_addr <= w_l_addr_func; + + --------------------------------------------------------------------- + -- Parity Checking, Error Correction + --------------------------------------------------------------------- + + -- Arg... what a mess + -- RF0 r0_read_enable r0_read_addr + -- RF1 r0_read_enable_q r0_read_addr_q r0_array_data + -- EX1 r0_read_val_q r0_read_addr_1_q r0_array_data_q gpr_do0_par_err + -- EX2 r0_read_addr_2_q gpr_do0_par_err_q + +gpr_parity_chk : for i in (8-regsize/8) to 7 generate + gpr_do0_par(i) <= xor_reduce(r0_array_data_q(8*i to 8*i+7)); + gpr_do1_par(i) <= xor_reduce(r1_array_data_q(8*i to 8*i+7)); + gpr_do2_par(i) <= xor_reduce(r2_array_data_q(8*i to 8*i+7)); + gpr_do3_par(i) <= xor_reduce(r3_array_data_q(8*i to 8*i+7)); +end generate; + + gpr_do0_par_err <= r0_read_val_q and (r0_array_data_q(64 to 63+regsize/8) /= gpr_do0_par); + gpr_do1_par_err <= r1_read_val_q and (r1_array_data_q(64 to 63+regsize/8) /= gpr_do1_par); + gpr_do2_par_err <= r2_read_val_q and (r2_array_data_q(64 to 63+regsize/8) /= gpr_do2_par); + gpr_do3_par_err <= r3_read_val_q and (r3_array_data_q(64 to 63+regsize/8) /= gpr_do3_par); + + -- Parity error detected + ex2_regfile_err_det <= perr_sm_q(0) and (gpr_do0_par_err_q or gpr_do1_par_err_q or gpr_do2_par_err_q); + gpr_cpl_ex3_regfile_err_det <= ex3_regfile_err_det_q; + + + -- Save the offending address on any parity error and hold. + perr_addr_d <= r0_read_addr_2_q when (gpr_do0_par_err_q and perr_sm_q(0)) = '1' else + r1_read_addr_2_q when (gpr_do1_par_err_q and perr_sm_q(0)) = '1' else + r2_read_addr_2_q when (gpr_do2_par_err_q and perr_sm_q(0)) = '1' else + perr_addr_q; + -- Save the direction of transfer + perr_direction_d <= "10" when ((gpr_do0_par_err_q or gpr_do1_par_err_q) and perr_sm_q(0)) = '1' else -- gpr_b writes to gpr_a + "01" when ( gpr_do2_par_err_q and perr_sm_q(0)) = '1' else -- gpr_a writes to gpr_b + perr_direction_q; + + -- Save data read out to write in next cycle + perr_write_data_sel <= perr_direction_q and (0 to 1 => perr_sm_q(2)); + with perr_write_data_sel select + perr_write_data_d <= r1_array_data when "01", + r3_array_data when "10", + (others=>tidn) when others; + + --------------------------------------------------------------------- + -- State Machine + --------------------------------------------------------------------- + -- State 0 = 1000 = Default, no parity error + -- State 1 = 0100 = Parity error detected. Flush System, read out both entries + -- State 2 = 0010 = Write back corrected entry + -- State 3 = 0001 = Flag Unrecoverable Error + + perr_sm_d <= ("10000" and (0 to 4 => perr_sm_next(0))) or + ("01000" and (0 to 4 => perr_sm_next(1))) or + ("00100" and (0 to 4 => perr_sm_next(2))) or + ("00010" and (0 to 4 => perr_sm_next(3))) or + ("00001" and (0 to 4 => perr_sm_next(4))) or + (perr_sm_q and (0 to 4 => not (or_reduce(perr_sm_next)))); + + -- Go to State 0 at the end of the sequence. That's either after a UE, or writeback is done + perr_sm_next(0) <= perr_sm_q(4); + gpr_cpl_regfile_seq_end <= perr_sm_q(3); -- fix later to 4 + + -- Go to State 1 when a parity error is detected. + perr_sm_next(1) <= perr_sm_q(0) and err_seq_0_q; + + -- Go to State 2 when both sets of data have been read out + perr_sm_next(2) <= perr_sm_q(1); + + -- Go to State 3 after read has completed, check for parity error + perr_sm_next(3) <= perr_sm_q(2); + perr_sm_next(4) <= perr_sm_q(3); + + with perr_addr_q(6 to 7) select + perr_tid <= "1000" when "00", + "0100" when "01", + "0010" when "10", + "0001" when others; + + -- Check for parity error on the read that holds the "corrected data" + -- If we get a parity error here, this is not correctable + perr_ue <= perr_sm_q(4) and + ((perr_direction_q(0) and gpr_do3_par_err_q) or + (perr_direction_q(1) and gpr_do1_par_err_q)); + + perr_ce <= perr_sm_q(4) and not perr_ue; + + err_regfile_parity_d <= gate(perr_tid,perr_ce); + err_regfile_ue_d <= gate(perr_tid,perr_ue); + + --------------------------------------------------------------------- + -- GPR Write-through + --------------------------------------------------------------------- + wthru_r0_w_e_d <= (r0_addr_func = w_e_addr_func) and w_e_act; + wthru_r1_w_e_d <= (r1_addr_func = w_e_addr_func) and w_e_act; + wthru_r2_w_e_d <= (r2_addr_func = w_e_addr_func) and w_e_act; + wthru_r3_w_e_d <= (r3_addr_func = w_e_addr_func) and w_e_act; + + wthru_r0_w_l_d <= (r0_addr_func = w_l_addr_func) and w_l_act; + wthru_r1_w_l_d <= (r1_addr_func = w_l_addr_func) and w_l_act; + wthru_r2_w_l_d <= (r2_addr_func = w_l_addr_func) and w_l_act; + wthru_r3_w_l_d <= (r3_addr_func = w_l_addr_func) and w_l_act; + + r0_byp_r <= not (wthru_r0_w_e_q or wthru_r0_w_l_q); + r1_byp_r <= not (wthru_r1_w_e_q or wthru_r1_w_l_q); + r2_byp_r <= not (wthru_r2_w_e_q or wthru_r2_w_l_q); + r3_byp_r <= not (wthru_r3_w_e_q or wthru_r3_w_l_q); + + + gpr_debug <= perr_sm_q(0 to 3) & perr_direction_q & perr_addr_q(0 to 7) & + wthru_r0_w_e_q & wthru_r0_w_l_q & + wthru_r1_w_e_q & wthru_r1_w_l_q & + wthru_r2_w_e_q & wthru_r2_w_l_q & + wthru_r3_w_e_q & wthru_r3_w_l_q; + + --------------------------------------------------------------------- + -- ABIST Scan Ring + --------------------------------------------------------------------- + xu_gpr_a : entity tri.tri_144x78_2r2w_eco(tri_144x78_2r2w_eco) + generic map( + expand_type => expand_type) + port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + abist_en => abist_en, + lbist_en => lbist_en, + abist_raw_dc_b => abist_raw_dc_b, + r0e_abist_comp_en => r0e_abist_comp_en, + r1e_abist_comp_en => r1e_abist_comp_en, + lcb_act_dis_dc => lcb_act_dis_dc, + lcb_clkoff_dc_b => lcb_clkoff_dc_b, + lcb_d_mode_dc => lcb_d_mode_dc, + lcb_delay_lclkr_dc => arr_delay_lclkr_dc, + lcb_fce_0 => lcb_fce_0, + lcb_mpw1_dc_b => arr_mpw1_dc_b, + lcb_mpw2_dc_b => lcb_mpw2_dc_b, + lcb_scan_diag_dc => lcb_scan_diag_dc, + lcb_scan_dis_dc_b => lcb_scan_dis_dc_b, + lcb_sg_0 => lcb_sg_0, + lcb_abst_sl_thold_0 => lcb_abst_sl_thold_0, + lcb_ary_nsl_thold_0 => lcb_ary_nsl_thold_0, + lcb_time_sl_thold_0 => lcb_time_sl_thold_0, + lcb_obs0_sg_0 => lcb_sg_0, + lcb_obs0_sl_thold_0 => lcb_abst_sl_thold_0, + lcb_time_sg_0 => lcb_sg_0, + obs0_scan_in => siv_abst(0), + obs0_scan_out => sov_abst(0), + lcb_obs1_sg_0 => lcb_sg_0, + lcb_obs1_sl_thold_0 => lcb_abst_sl_thold_0, + obs1_scan_in => siv_abst(1), + obs1_scan_out => sov_abst(1), + time_scan_in => siv_time(0), + time_scan_out => sov_time(0), + r_scan_in => siv_abst(2), + r_scan_out => sov_abst(2), + w_scan_in => siv_abst(3), + w_scan_out => sov_abst(3), + lcb_bolt_sl_thold_0 => lcb_bolt_sl_thold_0, + pc_bo_enable_2 => bo_enable_2, + pc_bo_reset => pc_xu_bo_reset, + pc_bo_unload => pc_xu_bo_unload, + pc_bo_load => pc_xu_bo_load, + pc_bo_shdata => pc_xu_bo_shdata, + pc_bo_select => pc_xu_bo_select(0), + bo_pc_failout => xu_pc_bo_fail(0), + bo_pc_diagloop => xu_pc_bo_diagout(0), + tri_lcb_mpw1_dc_b => mpw1_dc_b, + tri_lcb_mpw2_dc_b => mpw2_dc_b, + tri_lcb_delay_lclkr_dc => delay_lclkr_dc, + tri_lcb_clkoff_dc_b => clkoff_dc_b, + tri_lcb_act_dis_dc => tidn, + r0e_act => r0_read_enable, + r0e_en_func => r0_read_enable, + r0e_en_abist => r0e_en_abist, + r0e_sel_lbist => r0e_sel_lbist, + r0e_addr_func => r0_read_addr, + r0e_addr_abist => r0e_addr_abist, + r0e_data_out => r0_array_data, + r0e_byp_e => wthru_r0_w_e_q, + r0e_byp_l => wthru_r0_w_l_q, + r0e_byp_r => r0_byp_r, + r1e_act => r1_read_enable, + r1e_en_func => r1_read_enable, + r1e_en_abist => r1e_en_abist, + r1e_sel_lbist => r1e_sel_lbist, + r1e_addr_func => r1_read_addr, + r1e_addr_abist => r1e_addr_abist, + r1e_data_out => r1_array_data, + r1e_byp_e => wthru_r1_w_e_q, + r1e_byp_l => wthru_r1_w_l_q, + r1e_byp_r => r1_byp_r, + w0e_act => w_e_enable, + w0e_en_func => w_e_enable, + w0e_en_abist => w0e_en_abist, + w0e_addr_func => w_e_addr, + w0e_addr_abist => w0e_addr_abist, + w0e_data_func => w0e_data, + w0e_data_abist => w0e_data_abist, + w0l_act => w_l_enable, + w0l_en_func => w_l_enable, + w0l_en_abist => w0l_en_abist, + w0l_addr_func => w_l_addr, + w0l_addr_abist => w0l_addr_abist, + w0l_data_func => w_l_data, + w0l_data_abist => w0l_data_abist); + + xu_gpr_b : entity tri.tri_144x78_2r2w_eco(tri_144x78_2r2w_eco) + generic map( + expand_type => expand_type) + port map( + vdd => vdd, + gnd => gnd, + nclk => nclk, + abist_en => abist_en, + lbist_en => lbist_en, + abist_raw_dc_b => abist_raw_dc_b, + r0e_abist_comp_en => r0e_abist_comp_en, + r1e_abist_comp_en => r1e_abist_comp_en, + lcb_act_dis_dc => lcb_act_dis_dc, + lcb_clkoff_dc_b => lcb_clkoff_dc_b, + lcb_d_mode_dc => lcb_d_mode_dc, + lcb_delay_lclkr_dc => arr_delay_lclkr_dc, + lcb_fce_0 => lcb_fce_0, + lcb_mpw1_dc_b => arr_mpw1_dc_b, + lcb_mpw2_dc_b => lcb_mpw2_dc_b, + lcb_scan_diag_dc => lcb_scan_diag_dc, + lcb_scan_dis_dc_b => lcb_scan_dis_dc_b, + lcb_sg_0 => lcb_sg_0, + lcb_abst_sl_thold_0 => lcb_abst_sl_thold_0, + lcb_ary_nsl_thold_0 => lcb_ary_nsl_thold_0, + lcb_time_sg_0 => lcb_sg_0, + lcb_time_sl_thold_0 => lcb_time_sl_thold_0, + lcb_obs0_sg_0 => lcb_sg_0, + lcb_obs0_sl_thold_0 => lcb_abst_sl_thold_0, + obs0_scan_in => siv_abst(4), + obs0_scan_out => sov_abst(4), + lcb_obs1_sg_0 => lcb_sg_0, + lcb_obs1_sl_thold_0 => lcb_abst_sl_thold_0, + obs1_scan_in => siv_abst(5), + obs1_scan_out => sov_abst(5), + time_scan_in => siv_time(1), + time_scan_out => sov_time(1), + r_scan_in => siv_abst(6), + r_scan_out => sov_abst(6), + w_scan_in => siv_abst(7), + w_scan_out => sov_abst(7), + lcb_bolt_sl_thold_0 => lcb_bolt_sl_thold_0, + pc_bo_enable_2 => bo_enable_2, + pc_bo_reset => pc_xu_bo_reset, + pc_bo_unload => pc_xu_bo_unload, + pc_bo_load => pc_xu_bo_load, + pc_bo_shdata => pc_xu_bo_shdata, + pc_bo_select => pc_xu_bo_select(1), + bo_pc_failout => xu_pc_bo_fail(1), + bo_pc_diagloop => xu_pc_bo_diagout(1), + tri_lcb_mpw1_dc_b => mpw1_dc_b, + tri_lcb_mpw2_dc_b => mpw2_dc_b, + tri_lcb_delay_lclkr_dc => delay_lclkr_dc, + tri_lcb_clkoff_dc_b => clkoff_dc_b, + tri_lcb_act_dis_dc => tidn, + r0e_act => r2_read_enable, + r0e_en_func => r2_read_enable, + r0e_en_abist => r0e_en_abist, + r0e_sel_lbist => r0e_sel_lbist, + r0e_addr_func => r2_read_addr, + r0e_addr_abist => r0e_addr_abist, + r0e_data_out => r2_array_data, + r0e_byp_e => wthru_r2_w_e_q, + r0e_byp_l => wthru_r2_w_l_q, + r0e_byp_r => r2_byp_r, + r1e_act => r3_read_enable, + r1e_en_func => r3_read_enable, + r1e_en_abist => r1e_en_abist, + r1e_sel_lbist => r1e_sel_lbist, + r1e_addr_func => r3_read_addr, + r1e_addr_abist => r1e_addr_abist, + r1e_data_out => r3_array_data, + r1e_byp_e => wthru_r3_w_e_q, + r1e_byp_l => wthru_r3_w_l_q, + r1e_byp_r => r3_byp_r, + w0e_act => w_e_enable, + w0e_en_func => w_e_enable, + w0e_en_abist => w0e_en_abist, + w0e_addr_func => w_e_addr, + w0e_addr_abist => w0e_addr_abist, + w0e_data_func => w1e_data, + w0e_data_abist => w0e_data_abist, + w0l_act => w_l_enable, + w0l_en_func => w_l_enable, + w0l_en_abist => w0l_en_abist, + w0l_addr_func => w_l_addr, + w0l_addr_abist => w0l_addr_abist, + w0l_data_func => w_l_data, + w0l_data_abist => w0l_data_abist); + +perv_lcbctrl_regf_0: tri_lcbcntl_array_mac +generic map (expand_type => expand_type) +port map ( + vdd => vdd, + gnd => gnd, + sg => lcb_sg_0, + nclk => nclk, + scan_in => gpr_gptr_scan_in, + scan_diag_dc => an_ac_scan_diag_dc, + thold => lcb_gptr_sl_thold_0, + clkoff_dc_b => lcb_clkoff_dc_b(0), + delay_lclkr_dc => lcb_delay_lclkr_dc, + act_dis_dc => lcb_act_dis_dc, + d_mode_dc => lcb_d_mode_dc, + mpw1_dc_b => lcb_mpw1_dc_b, + mpw2_dc_b => lcb_mpw2_dc_b, + scan_out => gpr_gptr_scan_out); + + lcb_clkoff_dc_b(1) <= lcb_clkoff_dc_b(0); + + arr_delay_lclkr_dc(0) <= lcb_delay_lclkr_dc(0); + arr_delay_lclkr_dc(1) <= lcb_delay_lclkr_dc(1); + arr_delay_lclkr_dc(2) <= lcb_delay_lclkr_dc(0); + arr_delay_lclkr_dc(3) <= lcb_delay_lclkr_dc(1); + arr_delay_lclkr_dc(4) <= lcb_delay_lclkr_dc(2); + arr_delay_lclkr_dc(5) <= lcb_delay_lclkr_dc(3); + arr_delay_lclkr_dc(6) <= lcb_delay_lclkr_dc(4); + arr_delay_lclkr_dc(7) <= lcb_delay_lclkr_dc(4); + arr_delay_lclkr_dc(8) <= lcb_delay_lclkr_dc(3); + arr_delay_lclkr_dc(9) <= lcb_delay_lclkr_dc(3); + + arr_mpw1_dc_b(1) <= lcb_mpw1_dc_b(0); + arr_mpw1_dc_b(2) <= lcb_mpw1_dc_b(0); + arr_mpw1_dc_b(3) <= lcb_mpw1_dc_b(0); + arr_mpw1_dc_b(4) <= lcb_mpw1_dc_b(1); + arr_mpw1_dc_b(5) <= lcb_mpw1_dc_b(2); + arr_mpw1_dc_b(6) <= lcb_mpw1_dc_b(3); + arr_mpw1_dc_b(7) <= lcb_mpw1_dc_b(4); + arr_mpw1_dc_b(8) <= lcb_mpw1_dc_b(2); + arr_mpw1_dc_b(9) <= lcb_mpw1_dc_b(2); + + --------------------------------------------------------------------- + -- Latches + --------------------------------------------------------------------- + ex3_regfile_err_det_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_regfile_err_det_offset), + scout => sov(ex3_regfile_err_det_offset), + din => ex2_regfile_err_det, + dout => ex3_regfile_err_det_q); + gpr_do0_par_err_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(gpr_do0_par_err_offset), + scout => sov(gpr_do0_par_err_offset), + din => gpr_do0_par_err , + dout => gpr_do0_par_err_q); + gpr_do1_par_err_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(gpr_do1_par_err_offset), + scout => sov(gpr_do1_par_err_offset), + din => gpr_do1_par_err , + dout => gpr_do1_par_err_q); + gpr_do2_par_err_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(gpr_do2_par_err_offset), + scout => sov(gpr_do2_par_err_offset), + din => gpr_do2_par_err , + dout => gpr_do2_par_err_q); + gpr_do3_par_err_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(gpr_do3_par_err_offset), + scout => sov(gpr_do3_par_err_offset), + din => gpr_do3_par_err , + dout => gpr_do3_par_err_q); + r0_array_data_latch : tri_rlmreg_p + generic map (width => r0_array_data_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => r0_read_enable_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(r0_array_data_offset to r0_array_data_offset + r0_array_data_q'length-1), + scout => sov(r0_array_data_offset to r0_array_data_offset + r0_array_data_q'length-1), + din => r0_array_data(0 to 63+regsize/8), + dout => r0_array_data_q); + r0_read_addr_latch : tri_regk + generic map (width => r0_read_addr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => r0_read_enable , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => r0_read_addr , + dout => r0_read_addr_q); + r0_read_addr_1_latch : tri_rlmreg_p + generic map (width => r0_read_addr_1_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => r0_read_enable_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(r0_read_addr_1_offset to r0_read_addr_1_offset + r0_read_addr_1_q'length-1), + scout => sov(r0_read_addr_1_offset to r0_read_addr_1_offset + r0_read_addr_1_q'length-1), + din => r0_read_addr_q , + dout => r0_read_addr_1_q); + r0_read_addr_2_latch : tri_regk + generic map (width => r0_read_addr_2_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => r0_read_val_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => r0_read_addr_1_q , + dout => r0_read_addr_2_q); + r0_read_enable_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => r0_read_enable , + dout(0) => r0_read_enable_q); + r0_read_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(r0_read_val_offset), + scout => sov(r0_read_val_offset), + din => r0_read_enable_q , + dout => r0_read_val_q); + r1_array_data_latch : tri_rlmreg_p + generic map (width => r1_array_data_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => r1_read_enable_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(r1_array_data_offset to r1_array_data_offset + r1_array_data_q'length-1), + scout => sov(r1_array_data_offset to r1_array_data_offset + r1_array_data_q'length-1), + din => r1_array_data(0 to 63+regsize/8), + dout => r1_array_data_q); + r1_read_addr_latch : tri_regk + generic map (width => r1_read_addr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => r1_read_enable , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => r1_read_addr , + dout => r1_read_addr_q); + r1_read_addr_1_latch : tri_rlmreg_p + generic map (width => r1_read_addr_1_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => r1_read_enable_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(r1_read_addr_1_offset to r1_read_addr_1_offset + r1_read_addr_1_q'length-1), + scout => sov(r1_read_addr_1_offset to r1_read_addr_1_offset + r1_read_addr_1_q'length-1), + din => r1_read_addr_q , + dout => r1_read_addr_1_q); + r1_read_addr_2_latch : tri_regk + generic map (width => r1_read_addr_2_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => r1_read_val_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => r1_read_addr_1_q , + dout => r1_read_addr_2_q); + r1_read_enable_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => r1_read_enable , + dout(0) => r1_read_enable_q); + r1_read_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(r1_read_val_offset), + scout => sov(r1_read_val_offset), + din => r1_read_enable_q , + dout => r1_read_val_q); + r2_array_data_latch : tri_rlmreg_p + generic map (width => r2_array_data_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => r2_read_enable_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(r2_array_data_offset to r2_array_data_offset + r2_array_data_q'length-1), + scout => sov(r2_array_data_offset to r2_array_data_offset + r2_array_data_q'length-1), + din => r2_array_data(0 to 63+regsize/8), + dout => r2_array_data_q); + r2_read_addr_latch : tri_regk + generic map (width => r2_read_addr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => r2_read_enable , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => r2_read_addr , + dout => r2_read_addr_q); + r2_read_addr_1_latch : tri_rlmreg_p + generic map (width => r2_read_addr_1_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => r2_read_enable_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(r2_read_addr_1_offset to r2_read_addr_1_offset + r2_read_addr_1_q'length-1), + scout => sov(r2_read_addr_1_offset to r2_read_addr_1_offset + r2_read_addr_1_q'length-1), + din => r2_read_addr_q , + dout => r2_read_addr_1_q); + r2_read_addr_2_latch : tri_regk + generic map (width => r2_read_addr_2_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => r2_read_val_q , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => r2_read_addr_1_q , + dout => r2_read_addr_2_q); + r2_read_enable_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => r2_read_enable , + dout(0) => r2_read_enable_q); + r2_read_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(r2_read_val_offset), + scout => sov(r2_read_val_offset), + din => r2_read_enable_q , + dout => r2_read_val_q); + r3_array_data_latch : tri_rlmreg_p + generic map (width => r3_array_data_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => r3_read_enable_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(r3_array_data_offset to r3_array_data_offset + r3_array_data_q'length-1), + scout => sov(r3_array_data_offset to r3_array_data_offset + r3_array_data_q'length-1), + din => r3_array_data(0 to 63+regsize/8), + dout => r3_array_data_q); + r3_read_enable_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => r3_read_enable , + dout(0) => r3_read_enable_q); + r3_read_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(r3_read_val_offset), + scout => sov(r3_read_val_offset), + din => r3_read_enable_q , + dout => r3_read_val_q); + perr_addr_latch : tri_rlmreg_p + generic map (width => perr_addr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(perr_addr_offset to perr_addr_offset + perr_addr_q'length-1), + scout => sov(perr_addr_offset to perr_addr_offset + perr_addr_q'length-1), + din => perr_addr_d, + dout => perr_addr_q); + perr_direction_latch : tri_rlmreg_p + generic map (width => perr_direction_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(perr_direction_offset to perr_direction_offset + perr_direction_q'length-1), + scout => sov(perr_direction_offset to perr_direction_offset + perr_direction_q'length-1), + din => perr_direction_d, + dout => perr_direction_q); + perr_inj_latch : tri_rlmreg_p + generic map (width => perr_inj_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(perr_inj_offset to perr_inj_offset + perr_inj_q'length-1), + scout => sov(perr_inj_offset to perr_inj_offset + perr_inj_q'length-1), + din => pc_xu_inj_regfile_parity , + dout => perr_inj_q); + perr_sm_latch : tri_rlmreg_p + generic map (width => perr_sm_q'length, init => 2**(perr_sm_q'length-1), expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(perr_sm_offset to perr_sm_offset + perr_sm_q'length-1), + scout => sov(perr_sm_offset to perr_sm_offset + perr_sm_q'length-1), + din => perr_sm_d, + dout => perr_sm_q); + perr_write_data_latch : tri_rlmreg_p + generic map (width => perr_write_data_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => perr_sm_q(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(perr_write_data_offset to perr_write_data_offset + perr_write_data_q'length-1), + scout => sov(perr_write_data_offset to perr_write_data_offset + perr_write_data_q'length-1), + din => perr_write_data_d, + dout => perr_write_data_q); + err_regfile_parity_latch : tri_rlmreg_p + generic map (width => err_regfile_parity_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(err_regfile_parity_offset to err_regfile_parity_offset + err_regfile_parity_q'length-1), + scout => sov(err_regfile_parity_offset to err_regfile_parity_offset + err_regfile_parity_q'length-1), + din => err_regfile_parity_d, + dout => err_regfile_parity_q); + err_regfile_ue_latch : tri_rlmreg_p + generic map (width => err_regfile_ue_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(err_regfile_ue_offset to err_regfile_ue_offset + err_regfile_ue_q'length-1), + scout => sov(err_regfile_ue_offset to err_regfile_ue_offset + err_regfile_ue_q'length-1), + din => err_regfile_ue_d, + dout => err_regfile_ue_q); + err_seq_0_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(err_seq_0_offset), + scout => sov(err_seq_0_offset), + din => cpl_gpr_regfile_seq_beg , + dout => err_seq_0_q); + wthru_r0_w_e_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(wthru_r0_w_e_offset), + scout => sov(wthru_r0_w_e_offset), + din => wthru_r0_w_e_d, + dout => wthru_r0_w_e_q); + wthru_r0_w_l_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(wthru_r0_w_l_offset), + scout => sov(wthru_r0_w_l_offset), + din => wthru_r0_w_l_d, + dout => wthru_r0_w_l_q); + wthru_r1_w_e_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(wthru_r1_w_e_offset), + scout => sov(wthru_r1_w_e_offset), + din => wthru_r1_w_e_d, + dout => wthru_r1_w_e_q); + wthru_r1_w_l_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(wthru_r1_w_l_offset), + scout => sov(wthru_r1_w_l_offset), + din => wthru_r1_w_l_d, + dout => wthru_r1_w_l_q); + wthru_r2_w_e_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(wthru_r2_w_e_offset), + scout => sov(wthru_r2_w_e_offset), + din => wthru_r2_w_e_d, + dout => wthru_r2_w_e_q); + wthru_r2_w_l_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(wthru_r2_w_l_offset), + scout => sov(wthru_r2_w_l_offset), + din => wthru_r2_w_l_d, + dout => wthru_r2_w_l_q); + wthru_r3_w_e_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(wthru_r3_w_e_offset), + scout => sov(wthru_r3_w_e_offset), + din => wthru_r3_w_e_d, + dout => wthru_r3_w_e_q); + wthru_r3_w_l_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(wthru_r3_w_l_offset), + scout => sov(wthru_r3_w_l_offset), + din => wthru_r3_w_l_d, + dout => wthru_r3_w_l_q); + + siv(0 to siv'right) <= sov(1 to siv'right) & scan_in; + scan_out <= sov(0); + + siv_abst(0 to siv_abst'right) <= sov_abst(1 to siv_abst'right) & gpr_abst_scan_in; + gpr_abst_scan_out <= sov_abst(0); + + siv_time(0 to siv_time'right) <= sov_time(1 to siv_time'right) & gpr_time_scan_in; + gpr_time_scan_out <= sov_time(0); + + +end architecture xuq_fxu_gpr; diff --git a/rel/src/vhdl/work/xuq_fxu_spr.vhdl b/rel/src/vhdl/work/xuq_fxu_spr.vhdl new file mode 100644 index 0000000..66402a3 --- /dev/null +++ b/rel/src/vhdl/work/xuq_fxu_spr.vhdl @@ -0,0 +1,295 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XU SPR - Wrapper +-- +library ieee,ibm,support,work,tri; +use ieee.std_logic_1164.all; +use support.power_logic_pkg.all; +use ibm.std_ulogic_function_support.all; +use tri.tri_latches_pkg.all; + +entity xuq_fxu_spr is +generic( + hvmode : integer := 1; + a2mode : integer := 1; + expand_type : integer := 2; + threads : integer := 4; + regsize : integer := 64; + eff_ifar : integer := 62); +port( + nclk : in clk_logic; + + d_mode_dc : in std_ulogic; + delay_lclkr_dc : in std_ulogic; + mpw1_dc_b : in std_ulogic; + mpw2_dc_b : in std_ulogic; + + func_sl_force : in std_ulogic; + func_sl_thold_0_b : in std_ulogic; + func_nsl_force : in std_ulogic; + func_nsl_thold_0_b : in std_ulogic; + sg_0 : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + -- Decode + ex1_tid : in std_ulogic_vector(0 to threads-1); + ex1_instr : in std_ulogic_vector(11 to 20); + dec_spr_ex1_is_mfspr : in std_ulogic; + dec_spr_ex1_is_mtspr : in std_ulogic; + + -- Write Interface + ex6_val : in std_ulogic_vector(0 to threads-1); + ex6_spr_wd : in std_ulogic_vector(64-regsize to 63); + + -- Read Data + fspr_byp_ex3_spr_rt : out std_ulogic_vector(64-regsize to 63); + mux_spr_ex2_rt : in std_ulogic_vector(64-regsize to 63); + + ex2_is_any_load_dac : in std_ulogic; + ex2_is_any_store_dac : in std_ulogic; + + -- DAC + xu_lsu_ex4_dvc1_en : out std_ulogic; + xu_lsu_ex4_dvc2_en : out std_ulogic; + -- For Stores only, not gated by dvc*_en + lsu_xu_ex2_dvc1_st_cmp : in std_ulogic_vector(8-regsize/8 to 7); + lsu_xu_ex2_dvc2_st_cmp : in std_ulogic_vector(8-regsize/8 to 7); + -- For load hits only, gated by dvc*_en + lsu_xu_ex8_dvc1_ld_cmp : in std_ulogic_vector(8-regsize/8 to 7); + lsu_xu_ex8_dvc2_ld_cmp : in std_ulogic_vector(8-regsize/8 to 7); + -- For reloads only, all signals are gated by dvc*_en + lsu_xu_rel_dvc1_en : in std_ulogic; + lsu_xu_rel_dvc2_en : in std_ulogic; + lsu_xu_rel_dvc_thrd_id : in std_ulogic_vector(0 to 3); + lsu_xu_rel_dvc1_cmp : in std_ulogic_vector(8-regsize/8 to 7); + lsu_xu_rel_dvc2_cmp : in std_ulogic_vector(8-regsize/8 to 7); + + fxu_cpl_ex3_dac1r_cmpr_async : out std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac2r_cmpr_async : out std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac1r_cmpr : out std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac2r_cmpr : out std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac3r_cmpr : out std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac4r_cmpr : out std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac1w_cmpr : out std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac2w_cmpr : out std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac3w_cmpr : out std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac4w_cmpr : out std_ulogic_vector(0 to threads-1); + + -- SPRs + spr_bit_act : in std_ulogic; + spr_msr_pr : in std_ulogic_vector(0 to threads-1); + spr_msr_ds : in std_ulogic_vector(0 to threads-1); + spr_dbcr0_dac1 : in std_ulogic_vector(0 to 2*threads-1); + spr_dbcr0_dac2 : in std_ulogic_vector(0 to 2*threads-1); + spr_dbcr0_dac3 : in std_ulogic_vector(0 to 2*threads-1); + spr_dbcr0_dac4 : in std_ulogic_vector(0 to 2*threads-1); + + spr_dbcr3_ivc : out std_ulogic_vector(0 to threads-1); + + -- Power + vdd : inout power_logic; + gnd : inout power_logic +); + +-- synopsys translate_off + +-- synopsys translate_on +end xuq_fxu_spr; +architecture xuq_fxu_spr of xuq_fxu_spr is + + +signal siv : std_ulogic_vector(0 to threads); +signal sov : std_ulogic_vector(0 to threads); +-- Signals +signal cspr_tspr_ex6_is_mtspr : std_ulogic; +signal cspr_tspr_ex6_instr : std_ulogic_vector(11 to 20); +signal cspr_tspr_ex2_instr : std_ulogic_vector(11 to 20); +signal tspr_cspr_ex2_tspr_rt : std_ulogic_vector(0 to regsize*threads-1); +signal tspr_cspr_dbcr2_dac1us : std_ulogic_vector(0 to 2*threads-1); +signal tspr_cspr_dbcr2_dac1er : std_ulogic_vector(0 to 2*threads-1); +signal tspr_cspr_dbcr2_dac2us : std_ulogic_vector(0 to 2*threads-1); +signal tspr_cspr_dbcr2_dac2er : std_ulogic_vector(0 to 2*threads-1); +signal tspr_cspr_dbcr3_dac3us : std_ulogic_vector(0 to 2*threads-1); +signal tspr_cspr_dbcr3_dac3er : std_ulogic_vector(0 to 2*threads-1); +signal tspr_cspr_dbcr3_dac4us : std_ulogic_vector(0 to 2*threads-1); +signal tspr_cspr_dbcr3_dac4er : std_ulogic_vector(0 to 2*threads-1); +signal tspr_cspr_dbcr2_dac12m : std_ulogic_vector(0 to threads-1); +signal tspr_cspr_dbcr3_dac34m : std_ulogic_vector(0 to threads-1); +signal tspr_cspr_dbcr2_dvc1m : std_ulogic_vector(0 to 2*threads-1); +signal tspr_cspr_dbcr2_dvc2m : std_ulogic_vector(0 to 2*threads-1); +signal tspr_cspr_dbcr2_dvc1be : std_ulogic_vector(0 to 8*threads-1); +signal tspr_cspr_dbcr2_dvc2be : std_ulogic_vector(0 to 8*threads-1); + +begin + + +xu_fxu_spr_cspr : entity work.xuq_fxu_spr_cspr(xuq_fxu_spr_cspr) +generic map( + hvmode => hvmode, + a2mode => a2mode, + expand_type => expand_type, + threads => threads, + regsize => regsize, + eff_ifar => eff_ifar) +port map( + nclk => nclk, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc, + mpw1_dc_b => mpw1_dc_b, + mpw2_dc_b => mpw2_dc_b, + func_sl_force => func_sl_force, + func_sl_thold_0_b => func_sl_thold_0_b, + func_nsl_force => func_nsl_force, + func_nsl_thold_0_b => func_nsl_thold_0_b, + sg_0 => sg_0, + scan_in => siv(threads), + scan_out => sov(threads), + -- Decode + ex1_instr => ex1_instr, + ex1_tid => ex1_tid, + dec_spr_ex1_is_mfspr => dec_spr_ex1_is_mfspr, + dec_spr_ex1_is_mtspr => dec_spr_ex1_is_mtspr, + -- Write Interface + ex6_valid => ex6_val, + ex6_spr_wd => ex6_spr_wd, + -- SPRT Interface + cspr_tspr_ex6_is_mtspr => cspr_tspr_ex6_is_mtspr, + cspr_tspr_ex6_instr => cspr_tspr_ex6_instr, + cspr_tspr_ex2_instr => cspr_tspr_ex2_instr, + -- Read Data + tspr_cspr_ex2_tspr_rt => tspr_cspr_ex2_tspr_rt, + fspr_byp_ex3_spr_rt => fspr_byp_ex3_spr_rt, + mux_spr_ex2_rt => mux_spr_ex2_rt, + ex2_is_any_load_dac => ex2_is_any_load_dac, + ex2_is_any_store_dac => ex2_is_any_store_dac, + -- DAC + xu_lsu_ex4_dvc1_en => xu_lsu_ex4_dvc1_en, + xu_lsu_ex4_dvc2_en => xu_lsu_ex4_dvc2_en, + lsu_xu_ex2_dvc1_st_cmp => lsu_xu_ex2_dvc1_st_cmp, + lsu_xu_ex2_dvc2_st_cmp => lsu_xu_ex2_dvc2_st_cmp, + lsu_xu_ex8_dvc1_ld_cmp => lsu_xu_ex8_dvc1_ld_cmp, + lsu_xu_ex8_dvc2_ld_cmp => lsu_xu_ex8_dvc2_ld_cmp, + lsu_xu_rel_dvc1_en => lsu_xu_rel_dvc1_en, + lsu_xu_rel_dvc2_en => lsu_xu_rel_dvc2_en, + lsu_xu_rel_dvc_thrd_id => lsu_xu_rel_dvc_thrd_id, + lsu_xu_rel_dvc1_cmp => lsu_xu_rel_dvc1_cmp, + lsu_xu_rel_dvc2_cmp => lsu_xu_rel_dvc2_cmp, + fxu_cpl_ex3_dac1r_cmpr_async => fxu_cpl_ex3_dac1r_cmpr_async, + fxu_cpl_ex3_dac2r_cmpr_async => fxu_cpl_ex3_dac2r_cmpr_async, + fxu_cpl_ex3_dac1r_cmpr => fxu_cpl_ex3_dac1r_cmpr, + fxu_cpl_ex3_dac2r_cmpr => fxu_cpl_ex3_dac2r_cmpr, + fxu_cpl_ex3_dac3r_cmpr => fxu_cpl_ex3_dac3r_cmpr, + fxu_cpl_ex3_dac4r_cmpr => fxu_cpl_ex3_dac4r_cmpr, + fxu_cpl_ex3_dac1w_cmpr => fxu_cpl_ex3_dac1w_cmpr, + fxu_cpl_ex3_dac2w_cmpr => fxu_cpl_ex3_dac2w_cmpr, + fxu_cpl_ex3_dac3w_cmpr => fxu_cpl_ex3_dac3w_cmpr, + fxu_cpl_ex3_dac4w_cmpr => fxu_cpl_ex3_dac4w_cmpr, + -- SPRs + spr_bit_act => spr_bit_act, + spr_msr_pr => spr_msr_pr, + spr_msr_ds => spr_msr_ds, + spr_dbcr0_dac1 => spr_dbcr0_dac1, + spr_dbcr0_dac2 => spr_dbcr0_dac2, + spr_dbcr0_dac3 => spr_dbcr0_dac3, + spr_dbcr0_dac4 => spr_dbcr0_dac4, + tspr_cspr_dbcr2_dac1us => tspr_cspr_dbcr2_dac1us, + tspr_cspr_dbcr2_dac1er => tspr_cspr_dbcr2_dac1er, + tspr_cspr_dbcr2_dac2us => tspr_cspr_dbcr2_dac2us, + tspr_cspr_dbcr2_dac2er => tspr_cspr_dbcr2_dac2er, + tspr_cspr_dbcr3_dac3us => tspr_cspr_dbcr3_dac3us, + tspr_cspr_dbcr3_dac3er => tspr_cspr_dbcr3_dac3er, + tspr_cspr_dbcr3_dac4us => tspr_cspr_dbcr3_dac4us, + tspr_cspr_dbcr3_dac4er => tspr_cspr_dbcr3_dac4er, + tspr_cspr_dbcr2_dac12m => tspr_cspr_dbcr2_dac12m, + tspr_cspr_dbcr3_dac34m => tspr_cspr_dbcr3_dac34m, + tspr_cspr_dbcr2_dvc1m => tspr_cspr_dbcr2_dvc1m, + tspr_cspr_dbcr2_dvc2m => tspr_cspr_dbcr2_dvc2m, + tspr_cspr_dbcr2_dvc1be => tspr_cspr_dbcr2_dvc1be, + tspr_cspr_dbcr2_dvc2be => tspr_cspr_dbcr2_dvc2be, + + -- Power + vdd => vdd, + gnd => gnd +); + +thread : for t in 0 to threads-1 generate +xu_fxu_spr_tspr : entity work.xuq_fxu_spr_tspr(xuq_fxu_spr_tspr) +generic map( + hvmode => hvmode, + a2mode => a2mode, + expand_type => expand_type, + regsize => regsize, + eff_ifar => eff_ifar) +port map( + nclk => nclk, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc, + mpw1_dc_b => mpw1_dc_b, + mpw2_dc_b => mpw2_dc_b, + func_sl_force => func_sl_force, + func_sl_thold_0_b => func_sl_thold_0_b, + sg_0 => sg_0, + scan_in => siv(t), + scan_out => sov(t), + -- Read Interface + cspr_tspr_ex2_instr => cspr_tspr_ex2_instr, + tspr_cspr_ex2_tspr_rt => tspr_cspr_ex2_tspr_rt(regsize*t to regsize*(t+1)-1), + -- Write Interface + ex6_val => ex6_val(t), + cspr_tspr_ex6_is_mtspr => cspr_tspr_ex6_is_mtspr, + cspr_tspr_ex6_instr => cspr_tspr_ex6_instr, + ex6_spr_wd => ex6_spr_wd, + -- SPRs + tspr_cspr_dbcr2_dac1us => tspr_cspr_dbcr2_dac1us(2*t to 2*(t+1)-1), + tspr_cspr_dbcr2_dac1er => tspr_cspr_dbcr2_dac1er(2*t to 2*(t+1)-1), + tspr_cspr_dbcr2_dac2us => tspr_cspr_dbcr2_dac2us(2*t to 2*(t+1)-1), + tspr_cspr_dbcr2_dac2er => tspr_cspr_dbcr2_dac2er(2*t to 2*(t+1)-1), + tspr_cspr_dbcr3_dac3us => tspr_cspr_dbcr3_dac3us(2*t to 2*(t+1)-1), + tspr_cspr_dbcr3_dac3er => tspr_cspr_dbcr3_dac3er(2*t to 2*(t+1)-1), + tspr_cspr_dbcr3_dac4us => tspr_cspr_dbcr3_dac4us(2*t to 2*(t+1)-1), + tspr_cspr_dbcr3_dac4er => tspr_cspr_dbcr3_dac4er(2*t to 2*(t+1)-1), + tspr_cspr_dbcr2_dac12m => tspr_cspr_dbcr2_dac12m(t), + tspr_cspr_dbcr3_dac34m => tspr_cspr_dbcr3_dac34m(t), + tspr_cspr_dbcr2_dvc1m => tspr_cspr_dbcr2_dvc1m(2*t to 2*(t+1)-1), + tspr_cspr_dbcr2_dvc2m => tspr_cspr_dbcr2_dvc2m(2*t to 2*(t+1)-1), + tspr_cspr_dbcr2_dvc1be => tspr_cspr_dbcr2_dvc1be(8*t to 8*(t+1)-1), + tspr_cspr_dbcr2_dvc2be => tspr_cspr_dbcr2_dvc2be(8*t to 8*(t+1)-1), + spr_dbcr3_ivc => spr_dbcr3_ivc(t), + -- Power + vdd => vdd, + gnd => gnd +); +end generate; + +siv(0 to threads) <= sov(1 to threads) & scan_in; +scan_out <= sov(0); + +end architecture xuq_fxu_spr; + diff --git a/rel/src/vhdl/work/xuq_fxu_spr_cspr.vhdl b/rel/src/vhdl/work/xuq_fxu_spr_cspr.vhdl new file mode 100644 index 0000000..487ac6d --- /dev/null +++ b/rel/src/vhdl/work/xuq_fxu_spr_cspr.vhdl @@ -0,0 +1,1270 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XU SPR - per core registers & array +-- +library ieee,ibm,support,work,tri; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use support.power_logic_pkg.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use tri.tri_latches_pkg.all; +use work.xuq_pkg.all; + +entity xuq_fxu_spr_cspr is +generic( + hvmode : integer := 1; + a2mode : integer := 1; + expand_type : integer := 2; + threads : integer := 4; + regsize : integer := 64; + eff_ifar : integer := 62); +port( + nclk : in clk_logic; + + d_mode_dc : in std_ulogic; + delay_lclkr_dc : in std_ulogic; + mpw1_dc_b : in std_ulogic; + mpw2_dc_b : in std_ulogic; + + func_sl_force : in std_ulogic; + func_sl_thold_0_b : in std_ulogic; + func_nsl_force : in std_ulogic; + func_nsl_thold_0_b : in std_ulogic; + sg_0 : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + -- Decode + ex1_instr : in std_ulogic_vector(11 to 20); + ex1_tid : in std_ulogic_vector(0 to threads-1); + dec_spr_ex1_is_mfspr : in std_ulogic; + dec_spr_ex1_is_mtspr : in std_ulogic; + + -- Write Interface + ex6_valid : in std_ulogic_vector(0 to threads-1); + ex6_spr_wd : in std_ulogic_vector(64-regsize to 63); + + -- SPRT Interface + cspr_tspr_ex6_is_mtspr : out std_ulogic; + cspr_tspr_ex6_instr : out std_ulogic_vector(11 to 20); + cspr_tspr_ex2_is_mfspr : out std_ulogic; + cspr_tspr_ex2_instr : out std_ulogic_vector(11 to 20); + + -- Read Data + tspr_cspr_ex2_tspr_rt : in std_ulogic_vector(0 to regsize*threads-1); + fspr_byp_ex3_spr_rt : out std_ulogic_vector(64-regsize to 63); + mux_spr_ex2_rt : in std_ulogic_vector(64-regsize to 63); + + ex2_is_any_load_dac : in std_ulogic; + ex2_is_any_store_dac : in std_ulogic; + + -- DAC + xu_lsu_ex4_dvc1_en : out std_ulogic; + xu_lsu_ex4_dvc2_en : out std_ulogic; + -- For Stores only, not gated by dvc*_en + lsu_xu_ex2_dvc1_st_cmp : in std_ulogic_vector(8-regsize/8 to 7); + lsu_xu_ex2_dvc2_st_cmp : in std_ulogic_vector(8-regsize/8 to 7); + -- For load hits only, gated by dvc*_en + lsu_xu_ex8_dvc1_ld_cmp : in std_ulogic_vector(8-regsize/8 to 7); + lsu_xu_ex8_dvc2_ld_cmp : in std_ulogic_vector(8-regsize/8 to 7); + -- For reloads only, all signals are gated by dvc*_en + lsu_xu_rel_dvc1_en : in std_ulogic; + lsu_xu_rel_dvc2_en : in std_ulogic; + lsu_xu_rel_dvc_thrd_id : in std_ulogic_vector(0 to 3); + lsu_xu_rel_dvc1_cmp : in std_ulogic_vector(8-regsize/8 to 7); + lsu_xu_rel_dvc2_cmp : in std_ulogic_vector(8-regsize/8 to 7); + + fxu_cpl_ex3_dac1r_cmpr_async : out std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac2r_cmpr_async : out std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac1r_cmpr : out std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac2r_cmpr : out std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac3r_cmpr : out std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac4r_cmpr : out std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac1w_cmpr : out std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac2w_cmpr : out std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac3w_cmpr : out std_ulogic_vector(0 to threads-1); + fxu_cpl_ex3_dac4w_cmpr : out std_ulogic_vector(0 to threads-1); + + -- SPRs + spr_bit_act : in std_ulogic; + spr_msr_pr : in std_ulogic_vector(0 to threads-1); + spr_msr_ds : in std_ulogic_vector(0 to threads-1); + + spr_dbcr0_dac1 : in std_ulogic_vector(0 to 2*threads-1); + spr_dbcr0_dac2 : in std_ulogic_vector(0 to 2*threads-1); + spr_dbcr0_dac3 : in std_ulogic_vector(0 to 2*threads-1); + spr_dbcr0_dac4 : in std_ulogic_vector(0 to 2*threads-1); + + tspr_cspr_dbcr2_dac1us : in std_ulogic_vector(0 to 2*threads-1); + tspr_cspr_dbcr2_dac1er : in std_ulogic_vector(0 to 2*threads-1); + tspr_cspr_dbcr2_dac2us : in std_ulogic_vector(0 to 2*threads-1); + tspr_cspr_dbcr2_dac2er : in std_ulogic_vector(0 to 2*threads-1); + tspr_cspr_dbcr3_dac3us : in std_ulogic_vector(0 to 2*threads-1); + tspr_cspr_dbcr3_dac3er : in std_ulogic_vector(0 to 2*threads-1); + tspr_cspr_dbcr3_dac4us : in std_ulogic_vector(0 to 2*threads-1); + tspr_cspr_dbcr3_dac4er : in std_ulogic_vector(0 to 2*threads-1); + + tspr_cspr_dbcr2_dac12m : in std_ulogic_vector(0 to threads-1); + tspr_cspr_dbcr3_dac34m : in std_ulogic_vector(0 to threads-1); + tspr_cspr_dbcr2_dvc1m : in std_ulogic_vector(0 to 2*threads-1); + tspr_cspr_dbcr2_dvc2m : in std_ulogic_vector(0 to 2*threads-1); + tspr_cspr_dbcr2_dvc1be : in std_ulogic_vector(0 to 8*threads-1); + tspr_cspr_dbcr2_dvc2be : in std_ulogic_vector(0 to 8*threads-1); + + + -- Power + vdd : inout power_logic; + gnd : inout power_logic +); + +-- synopsys translate_off + +-- synopsys translate_on +end xuq_fxu_spr_cspr; +architecture xuq_fxu_spr_cspr of xuq_fxu_spr_cspr is + +-- Types +subtype DO is std_ulogic_vector(65-regsize to 64); +-- SPR Registers +signal dac1_d , dac1_q : std_ulogic_vector(64-(regsize) to 63); +signal dac2_d , dac2_q : std_ulogic_vector(64-(regsize) to 63); +signal dac3_d , dac3_q : std_ulogic_vector(64-(regsize) to 63); +signal dac4_d , dac4_q : std_ulogic_vector(64-(regsize) to 63); +-- FUNC Scanchain +constant dac1_offset : natural := 0; +constant dac2_offset : natural := dac1_offset + dac1_q'length*a2mode; +constant dac3_offset : natural := dac2_offset + dac2_q'length*a2mode; +constant dac4_offset : natural := dac3_offset + dac3_q'length; +constant last_reg_offset : natural := dac4_offset + dac4_q'length; +-- Latches +signal exx_act_q, exx_act_d : std_ulogic_vector(2 to 5); -- input=>exx_act_d , act=>tiup , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 +signal ex2_dac12m_q, ex2_dac12m_d : std_ulogic_vector(0 to 7); -- input=>ex2_dac12m_d , act=>exx_act(1) , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 +signal ex2_dac34m_q, ex2_dac34m_d : std_ulogic_vector(0 to 7); -- input=>ex2_dac34m_d , act=>exx_act(1) , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 +signal ex2_instr_q : std_ulogic_vector(11 to 20); -- input=>ex1_instr , act=>exx_act(1) , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 +signal ex2_is_mfspr_q : std_ulogic; -- input=>dec_spr_ex1_is_mfspr , act=>exx_act(1) , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 +signal ex2_is_mtspr_q : std_ulogic; -- input=>dec_spr_ex1_is_mtspr , act=>exx_act(1) , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 +signal ex2_tid_q : std_ulogic_vector(0 to threads-1); -- input=>ex1_tid , act=>exx_act(1) , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 +signal ex3_dac1r_cmpr_q, ex2_dac1r_cmpr : std_ulogic_vector(0 to threads-1); -- input=>ex2_dac1r_cmpr , act=>exx_act(2) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 +signal ex3_dac1w_cmpr_q, ex2_dac1w_cmpr : std_ulogic_vector(0 to threads-1); -- input=>ex2_dac1w_cmpr , act=>exx_act(2) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 +signal ex3_dac2r_cmpr_q, ex2_dac2r_cmpr : std_ulogic_vector(0 to threads-1); -- input=>ex2_dac2r_cmpr , act=>exx_act(2) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 +signal ex3_dac2w_cmpr_q, ex2_dac2w_cmpr : std_ulogic_vector(0 to threads-1); -- input=>ex2_dac2w_cmpr , act=>exx_act(2) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 +signal ex3_dac3r_cmpr_q, ex2_dac3r_cmpr : std_ulogic_vector(0 to threads-1); -- input=>ex2_dac3r_cmpr , act=>exx_act(2) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 +signal ex3_dac3w_cmpr_q, ex2_dac3w_cmpr : std_ulogic_vector(0 to threads-1); -- input=>ex2_dac3w_cmpr , act=>exx_act(2) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 +signal ex3_dac4r_cmpr_q, ex2_dac4r_cmpr : std_ulogic_vector(0 to threads-1); -- input=>ex2_dac4r_cmpr , act=>exx_act(2) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 +signal ex3_dac4w_cmpr_q, ex2_dac4w_cmpr : std_ulogic_vector(0 to threads-1); -- input=>ex2_dac4w_cmpr , act=>exx_act(2) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 +signal ex3_dvc1w_cmpr_q, ex2_dvc1w_cmpr : std_ulogic_vector(0 to threads-1); -- input=>ex2_dvc1w_cmpr , act=>exx_act(2) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 +signal ex3_dvc2w_cmpr_q, ex2_dvc2w_cmpr : std_ulogic_vector(0 to threads-1); -- input=>ex2_dvc2w_cmpr , act=>exx_act(2) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 +signal ex3_instr_q : std_ulogic_vector(11 to 20); -- input=>ex2_instr_q , act=>exx_act(2) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 +signal ex3_is_mtspr_q : std_ulogic; -- input=>ex2_is_mtspr_q , act=>exx_act(2) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 +signal ex3_spr_rt_q, ex3_spr_rt_d : std_ulogic_vector(64-regsize to 63); -- input=>ex3_spr_rt_d , act=>exx_act(2) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 +signal ex4_dvc1_en_q, ex3_dvc1_en : std_ulogic; -- input=>ex3_dvc1_en , act=>exx_act(3) , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 +signal ex4_dvc2_en_q, ex3_dvc2_en : std_ulogic; -- input=>ex3_dvc2_en , act=>exx_act(3) , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 +signal ex4_instr_q : std_ulogic_vector(11 to 20); -- input=>ex3_instr_q , act=>exx_act(3) , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 +signal ex4_is_mtspr_q : std_ulogic; -- input=>ex3_is_mtspr_q , act=>exx_act(3) , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 +signal ex5_dvc1_en_q : std_ulogic; -- input=>ex4_dvc1_en_q , act=>exx_act(4) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 +signal ex5_dvc2_en_q : std_ulogic; -- input=>ex4_dvc2_en_q , act=>exx_act(4) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 +signal ex5_instr_q : std_ulogic_vector(11 to 20); -- input=>ex4_instr_q , act=>exx_act(4) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 +signal ex5_is_mtspr_q : std_ulogic; -- input=>ex4_is_mtspr_q , act=>exx_act(4) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 +signal ex6_dvc1_en_q : std_ulogic; -- input=>ex5_dvc1_en_q , act=>exx_act(5) , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 +signal ex6_dvc2_en_q : std_ulogic; -- input=>ex5_dvc2_en_q , act=>exx_act(5) , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 +signal ex6_instr_q : std_ulogic_vector(11 to 20); -- input=>ex5_instr_q , act=>exx_act(5) , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 +signal ex6_is_mtspr_q : std_ulogic; -- input=>ex5_is_mtspr_q , act=>exx_act(5) , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 +signal ex7_dvc1_en_q : std_ulogic; -- input=>ex6_dvc1_en_q , act=>tiup , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 +signal ex7_dvc2_en_q : std_ulogic; -- input=>ex6_dvc2_en_q , act=>tiup , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 +signal ex7_val_q : std_ulogic_vector(0 to threads-1); -- input=>ex6_valid , act=>tiup , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 +signal ex8_dvc1_en_q : std_ulogic; -- input=>ex7_dvc1_en_q , act=>tiup , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 +signal ex8_dvc2_en_q : std_ulogic; -- input=>ex7_dvc2_en_q , act=>tiup , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 +signal ex8_val_q : std_ulogic_vector(0 to threads-1); -- input=>ex7_val_q , act=>tiup , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 +signal dbcr0_dac1_q : std_ulogic_vector(0 to 2*threads-1); -- input=>spr_dbcr0_dac1 , act=>spr_bit_act_q , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 +signal dbcr0_dac2_q : std_ulogic_vector(0 to 2*threads-1); -- input=>spr_dbcr0_dac2 , act=>spr_bit_act_q , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 +signal dbcr0_dac3_q : std_ulogic_vector(0 to 2*threads-1); -- input=>spr_dbcr0_dac3 , act=>spr_bit_act_q , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 +signal dbcr0_dac4_q : std_ulogic_vector(0 to 2*threads-1); -- input=>spr_dbcr0_dac4 , act=>spr_bit_act_q , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 +signal dbcr2_dvc1m_on_q, dbcr2_dvc1m_on_d : std_ulogic_vector(0 to threads-1); -- input=>dbcr2_dvc1m_on_d , act=>spr_bit_act_q , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 +signal dbcr2_dvc2m_on_q, dbcr2_dvc2m_on_d : std_ulogic_vector(0 to threads-1); -- input=>dbcr2_dvc2m_on_d , act=>spr_bit_act_q , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 +signal dvc1r_cmpr_q, dvc1r_cmpr_d : std_ulogic_vector(0 to threads-1); -- input=>dvc1r_cmpr_d , act=>spr_bit_act_q , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 +signal dvc2r_cmpr_q, dvc2r_cmpr_d : std_ulogic_vector(0 to threads-1); -- input=>dvc2r_cmpr_d , act=>spr_bit_act_q , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 +signal msr_ds_q : std_ulogic_vector(0 to threads-1); -- input=>spr_msr_ds , act=>tiup , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 +signal msr_pr_q : std_ulogic_vector(0 to threads-1); -- input=>spr_msr_pr , act=>tiup , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 +signal spr_bit_act_q : std_ulogic; -- input=>spr_bit_act , act=>tiup , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 +-- Scanchains +constant exx_act_offset : integer := last_reg_offset; +constant ex3_dac1r_cmpr_offset : integer := exx_act_offset + exx_act_q'length; +constant ex3_dac1w_cmpr_offset : integer := ex3_dac1r_cmpr_offset + ex3_dac1r_cmpr_q'length; +constant ex3_dac2r_cmpr_offset : integer := ex3_dac1w_cmpr_offset + ex3_dac1w_cmpr_q'length; +constant ex3_dac2w_cmpr_offset : integer := ex3_dac2r_cmpr_offset + ex3_dac2r_cmpr_q'length; +constant ex3_dac3r_cmpr_offset : integer := ex3_dac2w_cmpr_offset + ex3_dac2w_cmpr_q'length; +constant ex3_dac3w_cmpr_offset : integer := ex3_dac3r_cmpr_offset + ex3_dac3r_cmpr_q'length; +constant ex3_dac4r_cmpr_offset : integer := ex3_dac3w_cmpr_offset + ex3_dac3w_cmpr_q'length; +constant ex3_dac4w_cmpr_offset : integer := ex3_dac4r_cmpr_offset + ex3_dac4r_cmpr_q'length; +constant ex3_dvc1w_cmpr_offset : integer := ex3_dac4w_cmpr_offset + ex3_dac4w_cmpr_q'length; +constant ex3_dvc2w_cmpr_offset : integer := ex3_dvc1w_cmpr_offset + ex3_dvc1w_cmpr_q'length; +constant ex3_instr_offset : integer := ex3_dvc2w_cmpr_offset + ex3_dvc2w_cmpr_q'length; +constant ex3_is_mtspr_offset : integer := ex3_instr_offset + ex3_instr_q'length; +constant ex3_spr_rt_offset : integer := ex3_is_mtspr_offset + 1; +constant ex5_dvc1_en_offset : integer := ex3_spr_rt_offset + ex3_spr_rt_q'length; +constant ex5_dvc2_en_offset : integer := ex5_dvc1_en_offset + 1; +constant ex5_instr_offset : integer := ex5_dvc2_en_offset + 1; +constant ex5_is_mtspr_offset : integer := ex5_instr_offset + ex5_instr_q'length; +constant ex7_dvc1_en_offset : integer := ex5_is_mtspr_offset + 1; +constant ex7_dvc2_en_offset : integer := ex7_dvc1_en_offset + 1; +constant ex7_val_offset : integer := ex7_dvc2_en_offset + 1; +constant ex8_val_offset : integer := ex7_val_offset + ex7_val_q'length; +constant dbcr0_dac1_offset : integer := ex8_val_offset + ex8_val_q'length; +constant dbcr0_dac2_offset : integer := dbcr0_dac1_offset + dbcr0_dac1_q'length; +constant dbcr0_dac3_offset : integer := dbcr0_dac2_offset + dbcr0_dac2_q'length; +constant dbcr0_dac4_offset : integer := dbcr0_dac3_offset + dbcr0_dac3_q'length; +constant dbcr2_dvc1m_on_offset : integer := dbcr0_dac4_offset + dbcr0_dac4_q'length; +constant dbcr2_dvc2m_on_offset : integer := dbcr2_dvc1m_on_offset + dbcr2_dvc1m_on_q'length; +constant dvc1r_cmpr_offset : integer := dbcr2_dvc2m_on_offset + dbcr2_dvc2m_on_q'length; +constant dvc2r_cmpr_offset : integer := dvc1r_cmpr_offset + dvc1r_cmpr_q'length; +constant msr_ds_offset : integer := dvc2r_cmpr_offset + dvc2r_cmpr_q'length; +constant msr_pr_offset : integer := msr_ds_offset + msr_ds_q'length; +constant spr_bit_act_offset : integer := msr_pr_offset + msr_pr_q'length; +constant scan_right : integer := spr_bit_act_offset + 1; +signal siv : std_ulogic_vector(0 to scan_right-1); +signal sov : std_ulogic_vector(0 to scan_right-1); +-- Signals +signal tiup : std_ulogic; +signal tidn : std_ulogic_vector(00 to 63); +signal ex2_instr : std_ulogic_vector(11 to 20); +signal ex6_is_mtspr : std_ulogic; +signal ex6_instr : std_ulogic_vector(11 to 20); +signal ex6_val : std_ulogic; +signal ex2_cspr_rt,ex2_tspr_rt : std_ulogic_vector(64-regsize to 63); +signal ex2_dac2_mask : std_ulogic_vector(64-regsize to 63); +signal ex2_dac4_mask : std_ulogic_vector(64-regsize to 63); +signal ex2_dac1_cmpr, ex2_dac1_cmpr_sel : std_ulogic; +signal ex2_dac2_cmpr, ex2_dac2_cmpr_sel : std_ulogic; +signal ex2_dac3_cmpr, ex2_dac3_cmpr_sel : std_ulogic; +signal ex2_dac4_cmpr, ex2_dac4_cmpr_sel : std_ulogic; +signal ex2_dac1r_en, ex2_dac1w_en : std_ulogic_vector(0 to threads-1); +signal ex2_dac2r_en, ex2_dac2w_en : std_ulogic_vector(0 to threads-1); +signal ex2_dac3r_en, ex2_dac3w_en : std_ulogic_vector(0 to threads-1); +signal ex2_dac4r_en, ex2_dac4w_en : std_ulogic_vector(0 to threads-1); +signal ex8_dvc1r_cmpr,rel_dvc1r_cmpr : std_ulogic_vector(0 to threads-1); +signal ex8_dvc2r_cmpr,rel_dvc2r_cmpr : std_ulogic_vector(0 to threads-1); +signal ex8_dvc1_en, ex8_dvc2_en : std_ulogic_vector(0 to threads-1); +signal rel_dvc1_en, rel_dvc2_en : std_ulogic_vector(0 to threads-1); +signal exx_act : std_ulogic_vector(1 to 5); + +-- Data + +signal ex6_dac1_di : std_ulogic_vector(dac1_q'range); +signal ex6_dac2_di : std_ulogic_vector(dac2_q'range); +signal ex6_dac3_di : std_ulogic_vector(dac3_q'range); +signal ex6_dac4_di : std_ulogic_vector(dac4_q'range); +signal + ex2_dac1_rdec , ex2_dac2_rdec , ex2_dac3_rdec , ex2_dac4_rdec + : std_ulogic; +signal + ex2_dac1_re , ex2_dac2_re , ex2_dac3_re , ex2_dac4_re + : std_ulogic; +signal + ex6_dac1_wdec , ex6_dac2_wdec , ex6_dac3_wdec , ex6_dac4_wdec + : std_ulogic; +signal + ex6_dac1_we , ex6_dac2_we , ex6_dac3_we , ex6_dac4_we + : std_ulogic; +signal + dac1_act , dac2_act , dac3_act , dac4_act + : std_ulogic; +signal + dac1_do , dac2_do , dac3_do , dac4_do + : std_ulogic_vector(0 to 64); + +begin + + +tiup <= '1'; +tidn <= (others=>'0'); + + +exx_act_d <= exx_act(1 to 4); + +exx_act(1) <= or_reduce(ex1_tid); +exx_act(2) <= exx_act_q(2); +exx_act(3) <= exx_act_q(3); +exx_act(4) <= exx_act_q(4); +exx_act(5) <= exx_act_q(5); + +ex2_instr <= ex2_instr_q; +ex6_is_mtspr <= ex6_is_mtspr_q; +ex6_instr <= ex6_instr_q; +ex6_val <= or_reduce(ex6_valid); + +cspr_tspr_ex6_is_mtspr <= ex6_is_mtspr_q; +cspr_tspr_ex6_instr <= ex6_instr_q; +cspr_tspr_ex2_is_mfspr <= ex2_is_mfspr_q; +cspr_tspr_ex2_instr <= ex2_instr_q; + +-- SPR Input Control +-- DAC1 +dac1_act <= ex6_dac1_we; +dac1_d <= ex6_dac1_di; + +-- DAC2 +dac2_act <= ex6_dac2_we; +dac2_d <= ex6_dac2_di; + +-- DAC3 +dac3_act <= ex6_dac3_we; +dac3_d <= ex6_dac3_di; + +-- DAC4 +dac4_act <= ex6_dac4_we; +dac4_d <= ex6_dac4_di; + + +-- Compare Address Against DAC regs +ex2_dac12m_d <= fanout(or_reduce(tspr_cspr_dbcr2_dac12m and ex1_tid),ex2_dac12m_d'length); +ex2_dac34m_d <= fanout(or_reduce(tspr_cspr_dbcr3_dac34m and ex1_tid),ex2_dac34m_d'length); + +ex2_dac2_mask <= dac2_q or not fanout(ex2_dac12m_q,regsize); +ex2_dac4_mask <= dac4_q or not fanout(ex2_dac34m_q,regsize); + +ex2_dac1_cmpr <= and_reduce((mux_spr_ex2_rt xnor dac1_q) or not ex2_dac2_mask); +ex2_dac2_cmpr <= and_reduce((mux_spr_ex2_rt xnor dac2_q) ); +ex2_dac3_cmpr <= and_reduce((mux_spr_ex2_rt xnor dac3_q) or not ex2_dac4_mask); +ex2_dac4_cmpr <= and_reduce((mux_spr_ex2_rt xnor dac4_q) ); + +ex2_dac1_cmpr_sel <= ex2_dac1_cmpr; +ex2_dac2_cmpr_sel <= ex2_dac2_cmpr when ex2_dac12m_q(0)='0' else ex2_dac1_cmpr; +ex2_dac3_cmpr_sel <= ex2_dac3_cmpr; +ex2_dac4_cmpr_sel <= ex2_dac4_cmpr when ex2_dac34m_q(0)='0' else ex2_dac3_cmpr; + +-- Determine if DAC is enabled for this thread +xuq_fxu_spr_dac1en : entity work.xuq_spr_dacen(xuq_spr_dacen) +generic map( + threads => threads) +port map( + spr_msr_pr => msr_pr_q, + spr_msr_ds => msr_ds_q, + spr_dbcr0_dac => dbcr0_dac1_q, + spr_dbcr_dac_us => tspr_cspr_dbcr2_dac1us, + spr_dbcr_dac_er => tspr_cspr_dbcr2_dac1er, + val => ex2_tid_q, + load => ex2_is_any_load_dac, + store => ex2_is_any_store_dac, + dacr_en => ex2_dac1r_en, + dacw_en => ex2_dac1w_en); + +xuq_fxu_spr_dac2en : entity work.xuq_spr_dacen(xuq_spr_dacen) +generic map( + threads => threads) +port map( + spr_msr_pr => msr_pr_q, + spr_msr_ds => msr_ds_q, + spr_dbcr0_dac => dbcr0_dac2_q, + spr_dbcr_dac_us => tspr_cspr_dbcr2_dac2us, + spr_dbcr_dac_er => tspr_cspr_dbcr2_dac2er, + val => ex2_tid_q, + load => ex2_is_any_load_dac, + store => ex2_is_any_store_dac, + dacr_en => ex2_dac2r_en, + dacw_en => ex2_dac2w_en); + + +xuq_fxu_spr_dac3en : entity work.xuq_spr_dacen(xuq_spr_dacen) +generic map( + threads => threads) +port map( + spr_msr_pr => msr_pr_q, + spr_msr_ds => msr_ds_q, + spr_dbcr0_dac => dbcr0_dac3_q, + spr_dbcr_dac_us => tspr_cspr_dbcr3_dac3us, + spr_dbcr_dac_er => tspr_cspr_dbcr3_dac3er, + val => ex2_tid_q, + load => ex2_is_any_load_dac, + store => ex2_is_any_store_dac, + dacr_en => ex2_dac3r_en, + dacw_en => ex2_dac3w_en); + + +xuq_fxu_spr_dac4en : entity work.xuq_spr_dacen(xuq_spr_dacen) +generic map( + threads => threads) +port map( + spr_msr_pr => msr_pr_q, + spr_msr_ds => msr_ds_q, + spr_dbcr0_dac => dbcr0_dac4_q, + spr_dbcr_dac_us => tspr_cspr_dbcr3_dac4us, + spr_dbcr_dac_er => tspr_cspr_dbcr3_dac4er, + val => ex2_tid_q, + load => ex2_is_any_load_dac, + store => ex2_is_any_store_dac, + dacr_en => ex2_dac4r_en, + dacw_en => ex2_dac4w_en); + + +ex8_dvc1_en <= gate(ex8_val_q,ex8_dvc1_en_q); +ex8_dvc2_en <= gate(ex8_val_q,ex8_dvc2_en_q); + +rel_dvc1_en <= gate(lsu_xu_rel_dvc_thrd_id,lsu_xu_rel_dvc1_en); +rel_dvc2_en <= gate(lsu_xu_rel_dvc_thrd_id,lsu_xu_rel_dvc2_en); + +xuq_fxu_spr_dvc_cmp : for t in 0 to threads-1 generate +begin + + dbcr2_dvc1m_on_d(t) <= or_reduce(tspr_cspr_dbcr2_dvc1m(2*t to 2*t+1)) and or_reduce(tspr_cspr_dbcr2_dvc1be(t*8+8-lsu_xu_ex2_dvc1_st_cmp'length to t*8+7)); + dbcr2_dvc2m_on_d(t) <= or_reduce(tspr_cspr_dbcr2_dvc2m(2*t to 2*t+1)) and or_reduce(tspr_cspr_dbcr2_dvc2be(t*8+8-lsu_xu_ex2_dvc2_st_cmp'length to t*8+7)); + + dvc1_st : entity work.xuq_spr_dvccmp(xuq_spr_dvccmp) + generic map(regsize => regsize) + port map( + en => '1', + cmp => lsu_xu_ex2_dvc1_st_cmp, + dvcm => tspr_cspr_dbcr2_dvc1m(2*t to 2*t+1), + dvcbe => tspr_cspr_dbcr2_dvc1be(t*8+8-lsu_xu_ex2_dvc1_st_cmp'length to t*8+7), + dvc_cmpr => ex2_dvc1w_cmpr(t) + ); + + dvc2_st : entity work.xuq_spr_dvccmp(xuq_spr_dvccmp) + generic map(regsize => regsize) + port map( + en => '1', + cmp => lsu_xu_ex2_dvc2_st_cmp, + dvcm => tspr_cspr_dbcr2_dvc2m(2*t to 2*t+1), + dvcbe => tspr_cspr_dbcr2_dvc2be(t*8+8-lsu_xu_ex2_dvc2_st_cmp'length to t*8+7), + dvc_cmpr => ex2_dvc2w_cmpr(t) + ); + + dvc1_ld : entity work.xuq_spr_dvccmp(xuq_spr_dvccmp) + generic map(regsize => regsize) + port map( + en => ex8_dvc1_en(t), + en00 => '0', + cmp => lsu_xu_ex8_dvc1_ld_cmp, + dvcm => tspr_cspr_dbcr2_dvc1m(2*t to 2*t+1), + dvcbe => tspr_cspr_dbcr2_dvc1be(t*8+8-lsu_xu_ex8_dvc1_ld_cmp'length to t*8+7), + dvc_cmpr => ex8_dvc1r_cmpr(t) + ); + + dvc2_ld : entity work.xuq_spr_dvccmp(xuq_spr_dvccmp) + generic map(regsize => regsize) + port map( + en => ex8_dvc2_en(t), + en00 => '0', + cmp => lsu_xu_ex8_dvc2_ld_cmp, + dvcm => tspr_cspr_dbcr2_dvc2m(2*t to 2*t+1), + dvcbe => tspr_cspr_dbcr2_dvc2be(t*8+8-lsu_xu_ex8_dvc2_ld_cmp'length to t*8+7), + dvc_cmpr => ex8_dvc2r_cmpr(t) + ); + + dvc1_rel : entity work.xuq_spr_dvccmp(xuq_spr_dvccmp) + generic map(regsize => regsize) + port map( + en => rel_dvc1_en(t), + en00 => '0', + cmp => lsu_xu_rel_dvc1_cmp, + dvcm => tspr_cspr_dbcr2_dvc1m(2*t to 2*t+1), + dvcbe => tspr_cspr_dbcr2_dvc1be(t*8+8-lsu_xu_rel_dvc1_cmp'length to t*8+7), + dvc_cmpr => rel_dvc1r_cmpr(t) + ); + + dvc2_rel : entity work.xuq_spr_dvccmp(xuq_spr_dvccmp) + generic map(regsize => regsize) + port map( + en => rel_dvc2_en(t), + en00 => '0', + cmp => lsu_xu_rel_dvc2_cmp, + dvcm => tspr_cspr_dbcr2_dvc2m(2*t to 2*t+1), + dvcbe => tspr_cspr_dbcr2_dvc2be(t*8+8-lsu_xu_rel_dvc2_cmp'length to t*8+7), + dvc_cmpr => rel_dvc2r_cmpr(t) + ); + +end generate; + +ex2_dac1r_cmpr <= gate(ex2_dac1r_en,ex2_dac1_cmpr_sel); +ex2_dac2r_cmpr <= gate(ex2_dac2r_en,ex2_dac2_cmpr_sel); +ex2_dac3r_cmpr <= gate(ex2_dac3r_en,ex2_dac3_cmpr_sel); +ex2_dac4r_cmpr <= gate(ex2_dac4r_en,ex2_dac4_cmpr_sel); + +ex2_dac1w_cmpr <= gate(ex2_dac1w_en,ex2_dac1_cmpr_sel); +ex2_dac2w_cmpr <= gate(ex2_dac2w_en,ex2_dac2_cmpr_sel); +ex2_dac3w_cmpr <= gate(ex2_dac3w_en,ex2_dac3_cmpr_sel); +ex2_dac4w_cmpr <= gate(ex2_dac4w_en,ex2_dac4_cmpr_sel); + +dvc1r_cmpr_d <= ex8_dvc1r_cmpr or rel_dvc1r_cmpr; +dvc2r_cmpr_d <= ex8_dvc2r_cmpr or rel_dvc2r_cmpr; + +ex3_dvc1_en <= or_reduce(ex3_dac1r_cmpr_q and dbcr2_dvc1m_on_q); +ex3_dvc2_en <= or_reduce(ex3_dac2r_cmpr_q and dbcr2_dvc2m_on_q); + +fxu_cpl_ex3_dac1r_cmpr_async <= dvc1r_cmpr_q; +fxu_cpl_ex3_dac2r_cmpr_async <= dvc2r_cmpr_q; +fxu_cpl_ex3_dac1r_cmpr <=(ex3_dac1r_cmpr_q and not dbcr2_dvc1m_on_q); +fxu_cpl_ex3_dac2r_cmpr <=(ex3_dac2r_cmpr_q and not dbcr2_dvc2m_on_q); +fxu_cpl_ex3_dac3r_cmpr <= ex3_dac3r_cmpr_q; +fxu_cpl_ex3_dac4r_cmpr <= ex3_dac4r_cmpr_q; + +fxu_cpl_ex3_dac1w_cmpr <= ex3_dac1w_cmpr_q and (ex3_dvc1w_cmpr_q or not dbcr2_dvc1m_on_q); +fxu_cpl_ex3_dac2w_cmpr <= ex3_dac2w_cmpr_q and (ex3_dvc2w_cmpr_q or not dbcr2_dvc2m_on_q); +fxu_cpl_ex3_dac3w_cmpr <= ex3_dac3w_cmpr_q; +fxu_cpl_ex3_dac4w_cmpr <= ex3_dac4w_cmpr_q; + +xu_lsu_ex4_dvc1_en <= ex4_dvc1_en_q; +xu_lsu_ex4_dvc2_en <= ex4_dvc2_en_q; + + +readmux_00 : if a2mode = 0 and hvmode = 0 generate +ex2_cspr_rt <= + (dac3_do(DO'range) and (DO'range => ex2_dac3_re )) or + (dac4_do(DO'range) and (DO'range => ex2_dac4_re )); +end generate; +readmux_01 : if a2mode = 0 and hvmode = 1 generate +ex2_cspr_rt <= + (dac3_do(DO'range) and (DO'range => ex2_dac3_re )) or + (dac4_do(DO'range) and (DO'range => ex2_dac4_re )); +end generate; +readmux_10 : if a2mode = 1 and hvmode = 0 generate +ex2_cspr_rt <= + (dac1_do(DO'range) and (DO'range => ex2_dac1_re )) or + (dac2_do(DO'range) and (DO'range => ex2_dac2_re )) or + (dac3_do(DO'range) and (DO'range => ex2_dac3_re )) or + (dac4_do(DO'range) and (DO'range => ex2_dac4_re )); +end generate; +readmux_11 : if a2mode = 1 and hvmode = 1 generate +ex2_cspr_rt <= + (dac1_do(DO'range) and (DO'range => ex2_dac1_re )) or + (dac2_do(DO'range) and (DO'range => ex2_dac2_re )) or + (dac3_do(DO'range) and (DO'range => ex2_dac3_re )) or + (dac4_do(DO'range) and (DO'range => ex2_dac4_re )); +end generate; + +-- Read Muxing +ex2_tspr_rt <= mux_t(tspr_cspr_ex2_tspr_rt,ex2_tid_q); +ex3_spr_rt_d <= gate((ex2_tspr_rt or ex2_cspr_rt),ex2_is_mfspr_q); +fspr_byp_ex3_spr_rt <= ex3_spr_rt_q; + +mark_unused(tidn); + + +ex2_dac1_rdec <= (ex2_instr(11 to 20) = "1110001001"); -- 316 +ex2_dac2_rdec <= (ex2_instr(11 to 20) = "1110101001"); -- 317 +ex2_dac3_rdec <= (ex2_instr(11 to 20) = "1000111010"); -- 849 +ex2_dac4_rdec <= (ex2_instr(11 to 20) = "1001011010"); -- 850 +ex2_dac1_re <= ex2_dac1_rdec; +ex2_dac2_re <= ex2_dac2_rdec; +ex2_dac3_re <= ex2_dac3_rdec; +ex2_dac4_re <= ex2_dac4_rdec; + +ex6_dac1_wdec <= (ex6_instr(11 to 20) = "1110001001"); -- 316 +ex6_dac2_wdec <= (ex6_instr(11 to 20) = "1110101001"); -- 317 +ex6_dac3_wdec <= (ex6_instr(11 to 20) = "1000111010"); -- 849 +ex6_dac4_wdec <= (ex6_instr(11 to 20) = "1001011010"); -- 850 +ex6_dac1_we <= ex6_val and ex6_is_mtspr and ex6_dac1_wdec; +ex6_dac2_we <= ex6_val and ex6_is_mtspr and ex6_dac2_wdec; +ex6_dac3_we <= ex6_val and ex6_is_mtspr and ex6_dac3_wdec; +ex6_dac4_we <= ex6_val and ex6_is_mtspr and ex6_dac4_wdec; + + + +-- DAC1 +ex6_dac1_di <= ex6_spr_wd(64-(regsize) to 63) ; --DAC1 +dac1_do <= tidn(0 to 64-(regsize)) & + dac1_q(64-(regsize) to 63) ; --DAC1 +-- DAC2 +ex6_dac2_di <= ex6_spr_wd(64-(regsize) to 63) ; --DAC2 +dac2_do <= tidn(0 to 64-(regsize)) & + dac2_q(64-(regsize) to 63) ; --DAC2 +-- DAC3 +ex6_dac3_di <= ex6_spr_wd(64-(regsize) to 63) ; --DAC3 +dac3_do <= tidn(0 to 64-(regsize)) & + dac3_q(64-(regsize) to 63) ; --DAC3 +-- DAC4 +ex6_dac4_di <= ex6_spr_wd(64-(regsize) to 63) ; --DAC4 +dac4_do <= tidn(0 to 64-(regsize)) & + dac4_q(64-(regsize) to 63) ; --DAC4 + +-- Unused Signals +mark_unused(dac1_do(0 to 64-regsize)); +mark_unused(dac2_do(0 to 64-regsize)); +mark_unused(dac3_do(0 to 64-regsize)); +mark_unused(dac4_do(0 to 64-regsize)); + +dac1_latch_gen : if a2mode = 1 generate +dac1_latch : tri_ser_rlmreg_p +generic map(width => dac1_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => dac1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dac1_offset to dac1_offset + dac1_q'length-1), + scout => sov(dac1_offset to dac1_offset + dac1_q'length-1), + din => dac1_d, + dout => dac1_q); +end generate; +dac1_latch_tie : if a2mode = 0 generate + dac1_q <= (others=>'0'); +end generate; +dac2_latch_gen : if a2mode = 1 generate +dac2_latch : tri_ser_rlmreg_p +generic map(width => dac2_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => dac2_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dac2_offset to dac2_offset + dac2_q'length-1), + scout => sov(dac2_offset to dac2_offset + dac2_q'length-1), + din => dac2_d, + dout => dac2_q); +end generate; +dac2_latch_tie : if a2mode = 0 generate + dac2_q <= (others=>'0'); +end generate; +dac3_latch : tri_ser_rlmreg_p +generic map(width => dac3_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => dac3_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dac3_offset to dac3_offset + dac3_q'length-1), + scout => sov(dac3_offset to dac3_offset + dac3_q'length-1), + din => dac3_d, + dout => dac3_q); +dac4_latch : tri_ser_rlmreg_p +generic map(width => dac4_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => dac4_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dac4_offset to dac4_offset + dac4_q'length-1), + scout => sov(dac4_offset to dac4_offset + dac4_q'length-1), + din => dac4_d, + dout => dac4_q); + + +-- Latch Instances +exx_act_latch : tri_rlmreg_p + generic map (width => exx_act_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(exx_act_offset to exx_act_offset + exx_act_q'length-1), + scout => sov(exx_act_offset to exx_act_offset + exx_act_q'length-1), + din => exx_act_d, + dout => exx_act_q); +ex2_dac12m_latch : tri_regk + generic map (width => ex2_dac12m_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex2_dac12m_d, + dout => ex2_dac12m_q); +ex2_dac34m_latch : tri_regk + generic map (width => ex2_dac34m_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex2_dac34m_d, + dout => ex2_dac34m_q); +ex2_instr_latch : tri_regk + generic map (width => ex2_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex1_instr , + dout => ex2_instr_q); +ex2_is_mfspr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => dec_spr_ex1_is_mfspr , + dout(0) => ex2_is_mfspr_q); +ex2_is_mtspr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => dec_spr_ex1_is_mtspr , + dout(0) => ex2_is_mtspr_q); +ex2_tid_latch : tri_regk + generic map (width => ex2_tid_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex1_tid , + dout => ex2_tid_q); +ex3_dac1r_cmpr_latch : tri_rlmreg_p + generic map (width => ex3_dac1r_cmpr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_dac1r_cmpr_offset to ex3_dac1r_cmpr_offset + ex3_dac1r_cmpr_q'length-1), + scout => sov(ex3_dac1r_cmpr_offset to ex3_dac1r_cmpr_offset + ex3_dac1r_cmpr_q'length-1), + din => ex2_dac1r_cmpr, + dout => ex3_dac1r_cmpr_q); +ex3_dac1w_cmpr_latch : tri_rlmreg_p + generic map (width => ex3_dac1w_cmpr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_dac1w_cmpr_offset to ex3_dac1w_cmpr_offset + ex3_dac1w_cmpr_q'length-1), + scout => sov(ex3_dac1w_cmpr_offset to ex3_dac1w_cmpr_offset + ex3_dac1w_cmpr_q'length-1), + din => ex2_dac1w_cmpr, + dout => ex3_dac1w_cmpr_q); +ex3_dac2r_cmpr_latch : tri_rlmreg_p + generic map (width => ex3_dac2r_cmpr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_dac2r_cmpr_offset to ex3_dac2r_cmpr_offset + ex3_dac2r_cmpr_q'length-1), + scout => sov(ex3_dac2r_cmpr_offset to ex3_dac2r_cmpr_offset + ex3_dac2r_cmpr_q'length-1), + din => ex2_dac2r_cmpr, + dout => ex3_dac2r_cmpr_q); +ex3_dac2w_cmpr_latch : tri_rlmreg_p + generic map (width => ex3_dac2w_cmpr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_dac2w_cmpr_offset to ex3_dac2w_cmpr_offset + ex3_dac2w_cmpr_q'length-1), + scout => sov(ex3_dac2w_cmpr_offset to ex3_dac2w_cmpr_offset + ex3_dac2w_cmpr_q'length-1), + din => ex2_dac2w_cmpr, + dout => ex3_dac2w_cmpr_q); +ex3_dac3r_cmpr_latch : tri_rlmreg_p + generic map (width => ex3_dac3r_cmpr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_dac3r_cmpr_offset to ex3_dac3r_cmpr_offset + ex3_dac3r_cmpr_q'length-1), + scout => sov(ex3_dac3r_cmpr_offset to ex3_dac3r_cmpr_offset + ex3_dac3r_cmpr_q'length-1), + din => ex2_dac3r_cmpr, + dout => ex3_dac3r_cmpr_q); +ex3_dac3w_cmpr_latch : tri_rlmreg_p + generic map (width => ex3_dac3w_cmpr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_dac3w_cmpr_offset to ex3_dac3w_cmpr_offset + ex3_dac3w_cmpr_q'length-1), + scout => sov(ex3_dac3w_cmpr_offset to ex3_dac3w_cmpr_offset + ex3_dac3w_cmpr_q'length-1), + din => ex2_dac3w_cmpr, + dout => ex3_dac3w_cmpr_q); +ex3_dac4r_cmpr_latch : tri_rlmreg_p + generic map (width => ex3_dac4r_cmpr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_dac4r_cmpr_offset to ex3_dac4r_cmpr_offset + ex3_dac4r_cmpr_q'length-1), + scout => sov(ex3_dac4r_cmpr_offset to ex3_dac4r_cmpr_offset + ex3_dac4r_cmpr_q'length-1), + din => ex2_dac4r_cmpr, + dout => ex3_dac4r_cmpr_q); +ex3_dac4w_cmpr_latch : tri_rlmreg_p + generic map (width => ex3_dac4w_cmpr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_dac4w_cmpr_offset to ex3_dac4w_cmpr_offset + ex3_dac4w_cmpr_q'length-1), + scout => sov(ex3_dac4w_cmpr_offset to ex3_dac4w_cmpr_offset + ex3_dac4w_cmpr_q'length-1), + din => ex2_dac4w_cmpr, + dout => ex3_dac4w_cmpr_q); +ex3_dvc1w_cmpr_latch : tri_rlmreg_p + generic map (width => ex3_dvc1w_cmpr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_dvc1w_cmpr_offset to ex3_dvc1w_cmpr_offset + ex3_dvc1w_cmpr_q'length-1), + scout => sov(ex3_dvc1w_cmpr_offset to ex3_dvc1w_cmpr_offset + ex3_dvc1w_cmpr_q'length-1), + din => ex2_dvc1w_cmpr, + dout => ex3_dvc1w_cmpr_q); +ex3_dvc2w_cmpr_latch : tri_rlmreg_p + generic map (width => ex3_dvc2w_cmpr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_dvc2w_cmpr_offset to ex3_dvc2w_cmpr_offset + ex3_dvc2w_cmpr_q'length-1), + scout => sov(ex3_dvc2w_cmpr_offset to ex3_dvc2w_cmpr_offset + ex3_dvc2w_cmpr_q'length-1), + din => ex2_dvc2w_cmpr, + dout => ex3_dvc2w_cmpr_q); +ex3_instr_latch : tri_rlmreg_p + generic map (width => ex3_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_instr_offset to ex3_instr_offset + ex3_instr_q'length-1), + scout => sov(ex3_instr_offset to ex3_instr_offset + ex3_instr_q'length-1), + din => ex2_instr_q , + dout => ex3_instr_q); +ex3_is_mtspr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_mtspr_offset), + scout => sov(ex3_is_mtspr_offset), + din => ex2_is_mtspr_q , + dout => ex3_is_mtspr_q); +ex3_spr_rt_latch : tri_rlmreg_p + generic map (width => ex3_spr_rt_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_spr_rt_offset to ex3_spr_rt_offset + ex3_spr_rt_q'length-1), + scout => sov(ex3_spr_rt_offset to ex3_spr_rt_offset + ex3_spr_rt_q'length-1), + din => ex3_spr_rt_d, + dout => ex3_spr_rt_q); +ex4_dvc1_en_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_dvc1_en, + dout(0) => ex4_dvc1_en_q); +ex4_dvc2_en_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_dvc2_en, + dout(0) => ex4_dvc2_en_q); +ex4_instr_latch : tri_regk + generic map (width => ex4_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex3_instr_q , + dout => ex4_instr_q); +ex4_is_mtspr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_is_mtspr_q , + dout(0) => ex4_is_mtspr_q); +ex5_dvc1_en_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_dvc1_en_offset), + scout => sov(ex5_dvc1_en_offset), + din => ex4_dvc1_en_q , + dout => ex5_dvc1_en_q); +ex5_dvc2_en_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_dvc2_en_offset), + scout => sov(ex5_dvc2_en_offset), + din => ex4_dvc2_en_q , + dout => ex5_dvc2_en_q); +ex5_instr_latch : tri_rlmreg_p + generic map (width => ex5_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_instr_offset to ex5_instr_offset + ex5_instr_q'length-1), + scout => sov(ex5_instr_offset to ex5_instr_offset + ex5_instr_q'length-1), + din => ex4_instr_q , + dout => ex5_instr_q); +ex5_is_mtspr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_is_mtspr_offset), + scout => sov(ex5_is_mtspr_offset), + din => ex4_is_mtspr_q , + dout => ex5_is_mtspr_q); +ex6_dvc1_en_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(5) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex5_dvc1_en_q , + dout(0) => ex6_dvc1_en_q); +ex6_dvc2_en_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(5) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex5_dvc2_en_q , + dout(0) => ex6_dvc2_en_q); +ex6_instr_latch : tri_regk + generic map (width => ex6_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(5) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex5_instr_q , + dout => ex6_instr_q); +ex6_is_mtspr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(5) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex5_is_mtspr_q , + dout(0) => ex6_is_mtspr_q); +ex7_dvc1_en_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex7_dvc1_en_offset), + scout => sov(ex7_dvc1_en_offset), + din => ex6_dvc1_en_q , + dout => ex7_dvc1_en_q); +ex7_dvc2_en_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex7_dvc2_en_offset), + scout => sov(ex7_dvc2_en_offset), + din => ex6_dvc2_en_q , + dout => ex7_dvc2_en_q); +ex7_val_latch : tri_rlmreg_p + generic map (width => ex7_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex7_val_offset to ex7_val_offset + ex7_val_q'length-1), + scout => sov(ex7_val_offset to ex7_val_offset + ex7_val_q'length-1), + din => ex6_valid , + dout => ex7_val_q); +ex8_dvc1_en_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex7_dvc1_en_q , + dout(0) => ex8_dvc1_en_q); +ex8_dvc2_en_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex7_dvc2_en_q , + dout(0) => ex8_dvc2_en_q); +ex8_val_latch : tri_rlmreg_p + generic map (width => ex8_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex8_val_offset to ex8_val_offset + ex8_val_q'length-1), + scout => sov(ex8_val_offset to ex8_val_offset + ex8_val_q'length-1), + din => ex7_val_q , + dout => ex8_val_q); +dbcr0_dac1_latch : tri_rlmreg_p + generic map (width => dbcr0_dac1_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dbcr0_dac1_offset to dbcr0_dac1_offset + dbcr0_dac1_q'length-1), + scout => sov(dbcr0_dac1_offset to dbcr0_dac1_offset + dbcr0_dac1_q'length-1), + din => spr_dbcr0_dac1 , + dout => dbcr0_dac1_q); +dbcr0_dac2_latch : tri_rlmreg_p + generic map (width => dbcr0_dac2_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dbcr0_dac2_offset to dbcr0_dac2_offset + dbcr0_dac2_q'length-1), + scout => sov(dbcr0_dac2_offset to dbcr0_dac2_offset + dbcr0_dac2_q'length-1), + din => spr_dbcr0_dac2 , + dout => dbcr0_dac2_q); +dbcr0_dac3_latch : tri_rlmreg_p + generic map (width => dbcr0_dac3_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dbcr0_dac3_offset to dbcr0_dac3_offset + dbcr0_dac3_q'length-1), + scout => sov(dbcr0_dac3_offset to dbcr0_dac3_offset + dbcr0_dac3_q'length-1), + din => spr_dbcr0_dac3 , + dout => dbcr0_dac3_q); +dbcr0_dac4_latch : tri_rlmreg_p + generic map (width => dbcr0_dac4_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dbcr0_dac4_offset to dbcr0_dac4_offset + dbcr0_dac4_q'length-1), + scout => sov(dbcr0_dac4_offset to dbcr0_dac4_offset + dbcr0_dac4_q'length-1), + din => spr_dbcr0_dac4 , + dout => dbcr0_dac4_q); +dbcr2_dvc1m_on_latch : tri_rlmreg_p + generic map (width => dbcr2_dvc1m_on_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dbcr2_dvc1m_on_offset to dbcr2_dvc1m_on_offset + dbcr2_dvc1m_on_q'length-1), + scout => sov(dbcr2_dvc1m_on_offset to dbcr2_dvc1m_on_offset + dbcr2_dvc1m_on_q'length-1), + din => dbcr2_dvc1m_on_d, + dout => dbcr2_dvc1m_on_q); +dbcr2_dvc2m_on_latch : tri_rlmreg_p + generic map (width => dbcr2_dvc2m_on_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dbcr2_dvc2m_on_offset to dbcr2_dvc2m_on_offset + dbcr2_dvc2m_on_q'length-1), + scout => sov(dbcr2_dvc2m_on_offset to dbcr2_dvc2m_on_offset + dbcr2_dvc2m_on_q'length-1), + din => dbcr2_dvc2m_on_d, + dout => dbcr2_dvc2m_on_q); +dvc1r_cmpr_latch : tri_rlmreg_p + generic map (width => dvc1r_cmpr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dvc1r_cmpr_offset to dvc1r_cmpr_offset + dvc1r_cmpr_q'length-1), + scout => sov(dvc1r_cmpr_offset to dvc1r_cmpr_offset + dvc1r_cmpr_q'length-1), + din => dvc1r_cmpr_d, + dout => dvc1r_cmpr_q); +dvc2r_cmpr_latch : tri_rlmreg_p + generic map (width => dvc2r_cmpr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => spr_bit_act_q , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dvc2r_cmpr_offset to dvc2r_cmpr_offset + dvc2r_cmpr_q'length-1), + scout => sov(dvc2r_cmpr_offset to dvc2r_cmpr_offset + dvc2r_cmpr_q'length-1), + din => dvc2r_cmpr_d, + dout => dvc2r_cmpr_q); +msr_ds_latch : tri_rlmreg_p + generic map (width => msr_ds_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(msr_ds_offset to msr_ds_offset + msr_ds_q'length-1), + scout => sov(msr_ds_offset to msr_ds_offset + msr_ds_q'length-1), + din => spr_msr_ds , + dout => msr_ds_q); +msr_pr_latch : tri_rlmreg_p + generic map (width => msr_pr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(msr_pr_offset to msr_pr_offset + msr_pr_q'length-1), + scout => sov(msr_pr_offset to msr_pr_offset + msr_pr_q'length-1), + din => spr_msr_pr , + dout => msr_pr_q); +spr_bit_act_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(spr_bit_act_offset), + scout => sov(spr_bit_act_offset), + din => spr_bit_act, + dout => spr_bit_act_q); + +siv(0 to scan_right-1) <= sov(1 to scan_right-1) & scan_in; +scan_out <= sov(0); + +end architecture xuq_fxu_spr_cspr; diff --git a/rel/src/vhdl/work/xuq_fxu_spr_tspr.vhdl b/rel/src/vhdl/work/xuq_fxu_spr_tspr.vhdl new file mode 100644 index 0000000..73da815 --- /dev/null +++ b/rel/src/vhdl/work/xuq_fxu_spr_tspr.vhdl @@ -0,0 +1,314 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XU SPR - per thread register slice +-- +library ieee,ibm,support,work,tri; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use support.power_logic_pkg.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use tri.tri_latches_pkg.all; +use work.xuq_pkg.all; + +entity xuq_fxu_spr_tspr is +generic( + hvmode : integer := 1; + a2mode : integer := 1; + expand_type : integer := 2; + regsize : integer := 64; + eff_ifar : integer := 62); +port( + nclk : in clk_logic; + d_mode_dc : in std_ulogic; + delay_lclkr_dc : in std_ulogic; + mpw1_dc_b : in std_ulogic; + mpw2_dc_b : in std_ulogic; + func_sl_force : in std_ulogic; + func_sl_thold_0_b : in std_ulogic; + sg_0 : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + -- Read Interface + cspr_tspr_ex2_instr : in std_ulogic_vector(11 to 20); + tspr_cspr_ex2_tspr_rt : out std_ulogic_vector(64-regsize to 63); + + -- Write Interface + ex6_val : in std_ulogic; + cspr_tspr_ex6_is_mtspr : in std_ulogic; + cspr_tspr_ex6_instr : in std_ulogic_vector(11 to 20); + ex6_spr_wd : in std_ulogic_vector(64-regsize to 63); + + -- SPRs + tspr_cspr_dbcr2_dac1us : out std_ulogic_vector(0 to 1); + tspr_cspr_dbcr2_dac1er : out std_ulogic_vector(0 to 1); + tspr_cspr_dbcr2_dac2us : out std_ulogic_vector(0 to 1); + tspr_cspr_dbcr2_dac2er : out std_ulogic_vector(0 to 1); + tspr_cspr_dbcr3_dac3us : out std_ulogic_vector(0 to 1); + tspr_cspr_dbcr3_dac3er : out std_ulogic_vector(0 to 1); + tspr_cspr_dbcr3_dac4us : out std_ulogic_vector(0 to 1); + tspr_cspr_dbcr3_dac4er : out std_ulogic_vector(0 to 1); + tspr_cspr_dbcr2_dac12m : out std_ulogic; + tspr_cspr_dbcr3_dac34m : out std_ulogic; + tspr_cspr_dbcr2_dvc1m : out std_ulogic_vector(0 to 1); + tspr_cspr_dbcr2_dvc2m : out std_ulogic_vector(0 to 1); + tspr_cspr_dbcr2_dvc1be : out std_ulogic_vector(0 to 7); + tspr_cspr_dbcr2_dvc2be : out std_ulogic_vector(0 to 7); + spr_dbcr3_ivc : out std_ulogic; + + -- Power + vdd : inout power_logic; + gnd : inout power_logic +); + +-- synopsys translate_off + +-- synopsys translate_on +end xuq_fxu_spr_tspr; +architecture xuq_fxu_spr_tspr of xuq_fxu_spr_tspr is + +-- Types +subtype DO is std_ulogic_vector(65-regsize to 64); +-- SPR Registers +signal dbcr2_d , dbcr2_q : std_ulogic_vector(35 to 63); +signal dbcr3_d , dbcr3_q : std_ulogic_vector(54 to 63); +-- FUNC Scanchain +constant dbcr2_offset : natural := 0; +constant dbcr3_offset : natural := dbcr2_offset + dbcr2_q'length*a2mode; +constant last_reg_offset : natural := dbcr3_offset + dbcr3_q'length; +constant scan_right : integer := last_reg_offset; +signal siv : std_ulogic_vector(0 to scan_right-1); +signal sov : std_ulogic_vector(0 to scan_right-1); +-- Signals +signal tiup : std_ulogic; +signal tidn : std_ulogic_vector(00 to 63); +signal ex2_instr : std_ulogic_vector(11 to 20); +signal ex6_is_mtspr : std_ulogic; +signal ex6_instr : std_ulogic_vector(11 to 20); +-- Data +signal spr_dbcr2_dac1us : std_ulogic_vector(0 to 1); +signal spr_dbcr2_dac1er : std_ulogic_vector(0 to 1); +signal spr_dbcr2_dac2us : std_ulogic_vector(0 to 1); +signal spr_dbcr2_dac2er : std_ulogic_vector(0 to 1); +signal spr_dbcr2_dac12m : std_ulogic; +signal spr_dbcr2_dvc1m : std_ulogic_vector(0 to 1); +signal spr_dbcr2_dvc2m : std_ulogic_vector(0 to 1); +signal spr_dbcr2_dvc1be : std_ulogic_vector(0 to 7); +signal spr_dbcr2_dvc2be : std_ulogic_vector(0 to 7); +signal spr_dbcr3_dac3us : std_ulogic_vector(0 to 1); +signal spr_dbcr3_dac3er : std_ulogic_vector(0 to 1); +signal spr_dbcr3_dac4us : std_ulogic_vector(0 to 1); +signal spr_dbcr3_dac4er : std_ulogic_vector(0 to 1); +signal spr_dbcr3_dac34m : std_ulogic; +signal ex6_dbcr2_di : std_ulogic_vector(dbcr2_q'range); +signal ex6_dbcr3_di : std_ulogic_vector(dbcr3_q'range); +signal + ex2_dbcr2_rdec , ex2_dbcr3_rdec + : std_ulogic; +signal + ex2_dbcr2_re , ex2_dbcr3_re + : std_ulogic; +signal + ex6_dbcr2_wdec , ex6_dbcr3_wdec + : std_ulogic; +signal + ex6_dbcr2_we , ex6_dbcr3_we + : std_ulogic; +signal + dbcr2_act , dbcr3_act + : std_ulogic; +signal + dbcr2_do , dbcr3_do + : std_ulogic_vector(0 to 64); + +begin + + +tiup <= '1'; +tidn <= (others=>'0'); +ex2_instr <= cspr_tspr_ex2_instr; +ex6_is_mtspr <= cspr_tspr_ex6_is_mtspr; +ex6_instr <= cspr_tspr_ex6_instr; + +-- SPR Input Control +-- DBCR2 +dbcr2_act <= ex6_dbcr2_we; +dbcr2_d <= ex6_dbcr2_di; + +-- DBCR3 +dbcr3_act <= ex6_dbcr3_we; +dbcr3_d <= ex6_dbcr3_di; + +readmux_00 : if a2mode = 0 and hvmode = 0 generate +tspr_cspr_ex2_tspr_rt <= + (dbcr3_do(DO'range) and (DO'range => ex2_dbcr3_re )); +end generate; +readmux_01 : if a2mode = 0 and hvmode = 1 generate +tspr_cspr_ex2_tspr_rt <= + (dbcr3_do(DO'range) and (DO'range => ex2_dbcr3_re )); +end generate; +readmux_10 : if a2mode = 1 and hvmode = 0 generate +tspr_cspr_ex2_tspr_rt <= + (dbcr2_do(DO'range) and (DO'range => ex2_dbcr2_re )) or + (dbcr3_do(DO'range) and (DO'range => ex2_dbcr3_re )); +end generate; +readmux_11 : if a2mode = 1 and hvmode = 1 generate +tspr_cspr_ex2_tspr_rt <= + (dbcr2_do(DO'range) and (DO'range => ex2_dbcr2_re )) or + (dbcr3_do(DO'range) and (DO'range => ex2_dbcr3_re )); +end generate; + +ex2_dbcr2_rdec <= (ex2_instr(11 to 20) = "1011001001"); -- 310 +ex2_dbcr3_rdec <= (ex2_instr(11 to 20) = "1000011010"); -- 848 +ex2_dbcr2_re <= ex2_dbcr2_rdec; +ex2_dbcr3_re <= ex2_dbcr3_rdec; + +ex6_dbcr2_wdec <= (ex6_instr(11 to 20) = "1011001001"); -- 310 +ex6_dbcr3_wdec <= (ex6_instr(11 to 20) = "1000011010"); -- 848 +ex6_dbcr2_we <= ex6_val and ex6_is_mtspr and ex6_dbcr2_wdec; +ex6_dbcr3_we <= ex6_val and ex6_is_mtspr and ex6_dbcr3_wdec; + +spr_dbcr2_dac1us <= dbcr2_q(35 to 36); +spr_dbcr2_dac1er <= dbcr2_q(37 to 38); +spr_dbcr2_dac2us <= dbcr2_q(39 to 40); +spr_dbcr2_dac2er <= dbcr2_q(41 to 42); +spr_dbcr2_dac12m <= dbcr2_q(43); +spr_dbcr2_dvc1m <= dbcr2_q(44 to 45); +spr_dbcr2_dvc2m <= dbcr2_q(46 to 47); +spr_dbcr2_dvc1be <= dbcr2_q(48 to 55); +spr_dbcr2_dvc2be <= dbcr2_q(56 to 63); +spr_dbcr3_dac3us <= dbcr3_q(54 to 55); +spr_dbcr3_dac3er <= dbcr3_q(56 to 57); +spr_dbcr3_dac4us <= dbcr3_q(58 to 59); +spr_dbcr3_dac4er <= dbcr3_q(60 to 61); +spr_dbcr3_dac34m <= dbcr3_q(62); +spr_dbcr3_ivc <= dbcr3_q(63); +tspr_cspr_dbcr2_dac1us <= spr_dbcr2_dac1us; +tspr_cspr_dbcr2_dac1er <= spr_dbcr2_dac1er; +tspr_cspr_dbcr2_dac2us <= spr_dbcr2_dac2us; +tspr_cspr_dbcr2_dac2er <= spr_dbcr2_dac2er; +tspr_cspr_dbcr3_dac3us <= spr_dbcr3_dac3us; +tspr_cspr_dbcr3_dac3er <= spr_dbcr3_dac3er; +tspr_cspr_dbcr3_dac4us <= spr_dbcr3_dac4us; +tspr_cspr_dbcr3_dac4er <= spr_dbcr3_dac4er; +tspr_cspr_dbcr2_dac12m <= spr_dbcr2_dac12m; +tspr_cspr_dbcr3_dac34m <= spr_dbcr3_dac34m; +tspr_cspr_dbcr2_dvc1m <= spr_dbcr2_dvc1m; +tspr_cspr_dbcr2_dvc2m <= spr_dbcr2_dvc2m; +tspr_cspr_dbcr2_dvc1be <= spr_dbcr2_dvc1be; +tspr_cspr_dbcr2_dvc2be <= spr_dbcr2_dvc2be; + +mark_unused(tiup); +mark_unused(tidn); +mark_unused(ex6_spr_wd); + + +-- DBCR2 +ex6_dbcr2_di <= ex6_spr_wd(32 to 33) & --DAC1US + ex6_spr_wd(34 to 35) & --DAC1ER + ex6_spr_wd(36 to 37) & --DAC2US + ex6_spr_wd(38 to 39) & --DAC2ER + ex6_spr_wd(41 to 41) & --DAC12M + ex6_spr_wd(44 to 45) & --DVC1M + ex6_spr_wd(46 to 47) & --DVC2M + ex6_spr_wd(48 to 55) & --DVC1BE + ex6_spr_wd(56 to 63) ; --DVC2BE +dbcr2_do <= tidn(0 to 0) & + tidn(0 to 31) & --/// + dbcr2_q(35 to 36) & --DAC1US + dbcr2_q(37 to 38) & --DAC1ER + dbcr2_q(39 to 40) & --DAC2US + dbcr2_q(41 to 42) & --DAC2ER + tidn(40 to 40) & --/// + dbcr2_q(43 to 43) & --DAC12M + tidn(42 to 43) & --/// + dbcr2_q(44 to 45) & --DVC1M + dbcr2_q(46 to 47) & --DVC2M + dbcr2_q(48 to 55) & --DVC1BE + dbcr2_q(56 to 63) ; --DVC2BE +-- DBCR3 +ex6_dbcr3_di <= ex6_spr_wd(32 to 33) & --DAC3US + ex6_spr_wd(34 to 35) & --DAC3ER + ex6_spr_wd(36 to 37) & --DAC4US + ex6_spr_wd(38 to 39) & --DAC4ER + ex6_spr_wd(41 to 41) & --DAC34M + ex6_spr_wd(63 to 63) ; --IVC +dbcr3_do <= tidn(0 to 0) & + tidn(0 to 31) & --/// + dbcr3_q(54 to 55) & --DAC3US + dbcr3_q(56 to 57) & --DAC3ER + dbcr3_q(58 to 59) & --DAC4US + dbcr3_q(60 to 61) & --DAC4ER + tidn(40 to 40) & --/// + dbcr3_q(62 to 62) & --DAC34M + tidn(42 to 62) & --/// + dbcr3_q(63 to 63) ; --IVC + +-- Unused Signals +mark_unused(dbcr2_do(0 to 64-regsize)); +mark_unused(dbcr3_do(0 to 64-regsize)); + +dbcr2_latch_gen : if a2mode = 1 generate +dbcr2_latch : tri_ser_rlmreg_p +generic map(width => dbcr2_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => dbcr2_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dbcr2_offset to dbcr2_offset + dbcr2_q'length-1), + scout => sov(dbcr2_offset to dbcr2_offset + dbcr2_q'length-1), + din => dbcr2_d, + dout => dbcr2_q); +end generate; +dbcr2_latch_tie : if a2mode = 0 generate + dbcr2_q <= (others=>'0'); +end generate; +dbcr3_latch : tri_ser_rlmreg_p +generic map(width => dbcr3_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => dbcr3_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dbcr3_offset to dbcr3_offset + dbcr3_q'length-1), + scout => sov(dbcr3_offset to dbcr3_offset + dbcr3_q'length-1), + din => dbcr3_d, + dout => dbcr3_q); + + +siv(0 to scan_right-1) <= sov(1 to scan_right-1) & scan_in; +scan_out <= sov(0); + +end architecture xuq_fxu_spr_tspr; diff --git a/rel/src/vhdl/work/xuq_fxua_data.vhdl b/rel/src/vhdl/work/xuq_fxua_data.vhdl new file mode 100644 index 0000000..b76ceb5 --- /dev/null +++ b/rel/src/vhdl/work/xuq_fxua_data.vhdl @@ -0,0 +1,757 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XU Exception Handler +-- +library ieee,ibm,support,work,tri; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use support.power_logic_pkg.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use tri.tri_latches_pkg.all; +use work.xuq_pkg.all; + +entity xuq_fxua_data is +generic(expand_type : integer := 2; -- 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) + regmode : integer := 6; -- Register Mode 5 = 32bit, 6 = 64bit + dc_size : natural := 14; -- 2^14 = 16384 Bytes L1 D$ + cl_size : natural := 6; -- 2^6 = 64 Bytes CacheLines + l_endian_m : integer := 1; + threads : integer := 4; + eff_ifar : integer := 62; + regsize : integer := 64; + a2mode : integer := 1; + hvmode : integer := 1; + real_data_add : integer := 42); +port( + + --------------------------------------------------------------------- + -- Pervasive + --------------------------------------------------------------------- + pc_xu_abist_raddr_0 : in std_ulogic_vector(1 to 9); + pc_xu_abist_raddr_1 : in std_ulogic_vector(2 to 9); + pc_xu_abist_grf_renb_0 : in std_ulogic; + pc_xu_abist_grf_renb_1 : in std_ulogic; + pc_xu_abist_ena_dc : in std_ulogic; + pc_xu_abist_waddr_0 : in std_ulogic_vector(2 to 9); + pc_xu_abist_waddr_1 : in std_ulogic_vector(2 to 9); + pc_xu_abist_grf_wenb_0 : in std_ulogic; + pc_xu_abist_grf_wenb_1 : in std_ulogic; + pc_xu_abist_di_0 : in std_ulogic_vector(0 to 3); + pc_xu_abist_di_1 : in std_ulogic_vector(0 to 3); + pc_xu_abist_wl144_comp_ena : in std_ulogic; + pc_xu_abist_raw_dc_b : in std_ulogic; + pc_xu_ccflush_dc : in std_ulogic; + clkoff_dc_b : in std_ulogic; + d_mode_dc : in std_ulogic; + delay_lclkr_dc : in std_ulogic_vector(4 to 4); + mpw1_dc_b : in std_ulogic_vector(4 to 4); + mpw2_dc_b : in std_ulogic; + g6t_clkoff_dc_b : in std_ulogic; + g6t_d_mode_dc : in std_ulogic; + g6t_delay_lclkr_dc : in std_ulogic_vector(0 to 4); + g6t_mpw1_dc_b : in std_ulogic_vector(0 to 4); + g6t_mpw2_dc_b : in std_ulogic; + an_ac_scan_diag_dc : in std_ulogic; + an_ac_lbist_ary_wrt_thru_dc : in std_ulogic; + sg_2 : in std_ulogic_vector(0 to 2); + fce_2 : in std_ulogic_vector(0 to 0); + func_sl_thold_2 : in std_ulogic_vector(0 to 3); + func_nsl_thold_2 : in std_ulogic; + abst_sl_thold_2 : in std_ulogic; + time_sl_thold_2 : in std_ulogic; + ary_nsl_thold_2 : in std_ulogic; + repr_sl_thold_2 : in std_ulogic; + gptr_sl_thold_2 : in std_ulogic; + bolt_sl_thold_2 : in std_ulogic; + bo_enable_2 : in std_ulogic; + pc_xu_bo_unload : in std_ulogic; + pc_xu_bo_load : in std_ulogic; + pc_xu_bo_repair : in std_ulogic; + pc_xu_bo_reset : in std_ulogic; + pc_xu_bo_shdata : in std_ulogic; + pc_xu_bo_select : in std_ulogic_vector(5 to 8); + xu_pc_bo_fail : out std_ulogic_vector(5 to 8); + xu_pc_bo_diagout : out std_ulogic_vector(5 to 8); + + --------------------------------------------------------------------- + -- Interface with IU + --------------------------------------------------------------------- + iu_xu_is2_vld : in std_ulogic; + iu_xu_is2_ifar : in std_ulogic_vector(62-eff_ifar to 61); + iu_xu_is2_tid : in std_ulogic_vector(0 to threads-1); + iu_xu_is2_instr : in std_ulogic_vector(0 to 31); + iu_xu_is2_ta_vld : in std_ulogic; + iu_xu_is2_ta : in std_ulogic_vector(0 to 5); + iu_xu_is2_s1_vld : in std_ulogic; + iu_xu_is2_s1 : in std_ulogic_vector(0 to 5); + iu_xu_is2_s2_vld : in std_ulogic; + iu_xu_is2_s2 : in std_ulogic_vector(0 to 5); + iu_xu_is2_s3_vld : in std_ulogic; + iu_xu_is2_s3 : in std_ulogic_vector(0 to 5); + iu_xu_is2_axu_ld_or_st : in std_ulogic; + iu_xu_is2_axu_store : in std_ulogic; + iu_xu_is2_axu_ldst_size : in std_ulogic_vector(0 to 5); + iu_xu_is2_axu_ldst_update : in std_ulogic; + iu_xu_is2_axu_ldst_forcealign : in std_ulogic; + iu_xu_is2_axu_ldst_forceexcept : in std_ulogic; + iu_xu_is2_axu_ldst_extpid : in std_ulogic; + iu_xu_is2_axu_ldst_indexed : in std_ulogic; + iu_xu_is2_axu_ldst_tag : in std_ulogic_vector(0 to 8); + iu_xu_is2_axu_mftgpr : in std_ulogic; + iu_xu_is2_axu_mffgpr : in std_ulogic; + iu_xu_is2_axu_movedp : in std_ulogic; + iu_xu_is2_axu_instr_type : in std_ulogic_vector(0 to 2); + iu_xu_is2_pred_update : in std_ulogic; + iu_xu_is2_pred_taken_cnt : in std_ulogic_vector(0 to 1); + iu_xu_is2_error : in std_ulogic_vector(0 to 2); + iu_xu_is2_match : in std_ulogic; + iu_xu_is2_is_ucode : in std_ulogic; + iu_xu_is2_ucode_vld : in std_ulogic; + iu_xu_is2_gshare : in std_ulogic_vector(0 to 3); + xu_iu_multdiv_done : out std_ulogic_vector(0 to threads-1); + xu_iu_membar_tid : out std_ulogic_vector(0 to threads-1); + + --------------------------------------------------------------------- + -- Interface with LSU + --------------------------------------------------------------------- + lsu_xu_ldq_barr_done : in std_ulogic_vector(0 to threads-1); + lsu_xu_barr_done : in std_ulogic_vector(0 to threads-1); + + --------------------------------------------------------------------- + -- Interface with FXU B + --------------------------------------------------------------------- + fxa_fxb_rf0_val : out std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_issued : out std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_ucode_val : out std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_act : out std_ulogic; + fxa_fxb_ex1_hold_ctr_flush : out std_ulogic; + fxa_fxb_rf0_instr : out std_ulogic_vector(0 to 31); + fxa_fxb_rf0_tid : out std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_ta_vld : out std_ulogic; + fxa_fxb_rf0_ta : out std_ulogic_vector(0 to 7); + fxa_fxb_rf0_error : out std_ulogic_vector(0 to 2); + fxa_fxb_rf0_match : out std_ulogic; + fxa_fxb_rf0_is_ucode : out std_ulogic; + fxa_fxb_rf0_gshare : out std_ulogic_vector(0 to 3); + fxa_fxb_rf0_ifar : out std_ulogic_vector(62-eff_ifar to 61); + fxa_fxb_rf0_s1_vld : out std_ulogic; + fxa_fxb_rf0_s1 : out std_ulogic_vector(0 to 7); + fxa_fxb_rf0_s2_vld : out std_ulogic; + fxa_fxb_rf0_s2 : out std_ulogic_vector(0 to 7); + fxa_fxb_rf0_s3_vld : out std_ulogic; + fxa_fxb_rf0_s3 : out std_ulogic_vector(0 to 7); + fxa_fxb_rf0_axu_instr_type : out std_ulogic_vector(0 to 2); + fxa_fxb_rf0_axu_ld_or_st : out std_ulogic; + fxa_fxb_rf0_axu_store : out std_ulogic; + fxa_fxb_rf0_axu_mftgpr : out std_ulogic; + fxa_fxb_rf0_axu_mffgpr : out std_ulogic; + fxa_fxb_rf0_axu_movedp : out std_ulogic; + fxa_fxb_rf0_axu_ldst_size : out std_ulogic_vector(0 to 5); + fxa_fxb_rf0_axu_ldst_update : out std_ulogic; + fxa_fxb_rf0_axu_ldst_forcealign : out std_ulogic; + fxa_fxb_rf0_axu_ldst_forceexcept : out std_ulogic; + fxa_fxb_rf0_axu_ldst_indexed : out std_ulogic; + fxa_fxb_rf0_axu_ldst_tag : out std_ulogic_vector(0 to 8); + fxa_fxb_rf0_pred_update : out std_ulogic; + fxa_fxb_rf0_pred_taken_cnt : out std_ulogic_vector(0 to 1); + fxa_fxb_rf0_mc_dep_chk_val : out std_ulogic_vector(0 to threads-1); + fxa_fxb_rf1_mul_val : out std_ulogic; + fxa_fxb_rf1_muldiv_coll : out std_ulogic; + fxa_fxb_rf1_div_val : out std_ulogic; + fxa_fxb_rf1_div_ctr : out std_ulogic_vector(0 to 7); + fxa_fxb_rf0_xu_epid_instr : out std_ulogic; + fxa_fxb_rf0_axu_is_extload : out std_ulogic; + fxa_fxb_rf0_axu_is_extstore : out std_ulogic; + fxa_fxb_rf0_spr_tid : out std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_cpl_tid : out std_ulogic_vector(0 to threads-1); + fxa_fxb_rf0_cpl_act : out std_ulogic; + fxa_fxb_rf0_is_mfocrf : out std_ulogic; + fxa_fxb_rf0_3src_instr : out std_ulogic; + fxa_fxb_rf0_gpr0_zero : out std_ulogic; + fxa_fxb_rf0_use_imm : out std_ulogic; + dec_cpl_ex3_mc_dep_chk_val : out std_ulogic_vector(0 to threads-1); + fxb_fxa_ex7_we0 : in std_ulogic; + fxb_fxa_ex7_wa0 : in std_ulogic_vector(0 to 7); + fxb_fxa_ex7_wd0 : in std_ulogic_vector(64-regsize to 63); + fxa_fxb_rf1_do0 : out std_ulogic_vector(64-regsize to 63); + fxa_fxb_rf1_do1 : out std_ulogic_vector(64-regsize to 63); + fxa_fxb_rf1_do2 : out std_ulogic_vector(64-regsize to 63); + fxb_fxa_ex6_clear_barrier : in std_ulogic_vector(0 to threads-1); + fxa_perf_muldiv_in_use : out std_ulogic; + + --------------------------------------------------------------------- + -- Flushes + --------------------------------------------------------------------- + xu_is2_flush : in std_ulogic_vector(0 to threads-1); + xu_rf0_flush : in std_ulogic_vector(0 to threads-1); + xu_rf1_flush : in std_ulogic_vector(0 to threads-1); + xu_ex1_flush : in std_ulogic_vector(0 to threads-1); + xu_ex2_flush : in std_ulogic_vector(0 to threads-1); + xu_ex3_flush : in std_ulogic_vector(0 to threads-1); + xu_ex4_flush : in std_ulogic_vector(0 to threads-1); + xu_ex5_flush : in std_ulogic_vector(0 to threads-1); + fxa_cpl_ex2_div_coll : out std_ulogic_vector(0 to threads-1); + cpl_fxa_ex5_set_barr : in std_ulogic_vector(0 to threads-1); + fxa_iu_set_barr_tid : out std_ulogic_vector(0 to threads-1); + spr_xucr4_div_barr_thres : in std_ulogic_vector(0 to 7); + + --------------------------------------------------------------------- + -- ICSWX + --------------------------------------------------------------------- + an_ac_back_inv : in std_ulogic; + an_ac_back_inv_addr : in std_ulogic_vector(62 to 63); + an_ac_back_inv_target_bit3 : in std_ulogic; + + --------------------------------------------------------------------- + -- Interface with SPR + --------------------------------------------------------------------- + dec_spr_rf0_instr : out std_ulogic_vector(0 to 31); + + --------------------------------------------------------------------- + -- Parity + --------------------------------------------------------------------- + pc_xu_inj_regfile_parity : in std_ulogic_vector(0 to 3); + xu_pc_err_regfile_parity : out std_ulogic_vector(0 to threads-1); + xu_pc_err_regfile_ue : out std_ulogic_vector(0 to 3); + gpr_cpl_ex3_regfile_err_det : out std_ulogic; + cpl_gpr_regfile_seq_beg : in std_ulogic; + gpr_cpl_regfile_seq_end : out std_ulogic; + + --------------------------------------------------------------------- + -- Interface with LSU + --------------------------------------------------------------------- + xu_lsu_rf0_derat_is_extload : out std_ulogic; + xu_lsu_rf0_derat_is_extstore : out std_ulogic; + xu_lsu_rf0_derat_val : out std_ulogic_vector(0 to threads-1); + lsu_xu_rel_wren : in std_ulogic; + lsu_xu_rel_ta_gpr : in std_ulogic_vector(0 to 7); + fxa_cpl_debug : out std_ulogic_vector(0 to 272); + + -- Execution Pipe + xu_lsu_rf1_data_act :in std_ulogic; + xu_lsu_rf1_axu_ldst_falign :in std_ulogic; + xu_lsu_ex1_store_data :in std_ulogic_vector(64-(2**REGMODE) to 63); + xu_lsu_ex1_eff_addr :in std_ulogic_vector(64-(dc_size-3) to 63); + xu_lsu_ex1_rotsel_ovrd :in std_ulogic_vector(0 to 4); + ex1_optype32 :in std_ulogic; + ex1_optype16 :in std_ulogic; + ex1_optype8 :in std_ulogic; + ex1_optype4 :in std_ulogic; + ex1_optype2 :in std_ulogic; + ex1_optype1 :in std_ulogic; + ex1_store_instr :in std_ulogic; + ex1_axu_op_val :in std_ulogic; + ex1_saxu_instr :in std_ulogic; + ex1_sdp_instr :in std_ulogic; + ex1_stgpr_instr :in std_ulogic; + + fu_xu_ex2_store_data_val :in std_ulogic; -- EX2 AXU Data is Valid + fu_xu_ex2_store_data :in std_ulogic_vector(0 to 255); -- EX2 AXU Data + + ex3_algebraic :in std_ulogic; -- EX3 Instruction is a Load Algebraic + ex3_data_swap :in std_ulogic; -- EX3 little-endian or byte reversal valid + ex3_thrd_id :in std_ulogic_vector(0 to 3); -- EX3 Thread ID + bx_xu_ex5_dp_data :in std_ulogic_vector(0 to 127); -- EX5 dp data + + -- Debug Data Compare + ex4_load_op_hit :in std_ulogic; + ex4_store_hit :in std_ulogic; + ex4_axu_op_val :in std_ulogic; + spr_dvc1_act :in std_ulogic; + spr_dvc2_act :in std_ulogic; + spr_dvc1_dbg :in std_ulogic_vector(64-(2**regmode) to 63); + spr_dvc2_dbg :in std_ulogic_vector(64-(2**regmode) to 63); + + -- Update Data Array Valid + rel_upd_dcarr_val :in std_ulogic; + + -- Instruction Flush + xu_lsu_ex4_flush_local :in std_ulogic_vector(0 to 3); -- EX4 Local Flush Stage + + -- Error Inject + xu_pc_err_dcache_parity :out std_ulogic; + pc_xu_inj_dcache_parity :in std_ulogic; + + -- Config Bits + xu_lsu_spr_xucr0_dcdis :in std_ulogic; + spr_xucr0_clkg_ctl_b0 :in std_ulogic; + + -- Reload Pipe + ldq_rel_data_val_early :in std_ulogic; + ldq_rel_algebraic :in std_ulogic; -- Reload requires sign extension + ldq_rel_data_val :in std_ulogic; -- Reload Data is Valid + ldq_rel_ci :in std_ulogic; -- Reload Data is for a cache-inhibited request + ldq_rel_thrd_id :in std_ulogic_vector(0 to 3); -- Reload Thread ID for DVC + ldq_rel_axu_val :in std_ulogic; -- Reload Data is the correct Quadword + ldq_rel_256_data :in std_ulogic_vector(0 to 255); -- Reload Data + ldq_rel_rot_sel :in std_ulogic_vector(0 to 4); -- Rotator Select + ldq_rel_op_size :in std_ulogic_vector(0 to 5); -- Reload Size of Original Request + ldq_rel_le_mode :in std_ulogic; -- Reload requires Little Endian Swap + ldq_rel_dvc1_en :in std_ulogic; -- Debug Data Value Compare1 Enable + ldq_rel_dvc2_en :in std_ulogic; -- Debug Data Value Compare2 Enable + ldq_rel_beat_crit_qw :in std_ulogic; -- Reload Data is the correct Quadword + ldq_rel_beat_crit_qw_block :in std_ulogic; -- Reload Data had an ecc error + ldq_rel_addr :in std_ulogic_vector(64-(dc_size-3) to 58); -- Reload Array Address + + -- Data Cache Update + dcarr_up_way_addr :in std_ulogic_vector(0 to 2); -- Upper Address of Data Cache + + -- Execution Pipe Outputs + ex4_256st_data :out std_ulogic_vector(0 to 255); -- EX4 Store Data + ex6_ld_par_err :out std_ulogic; -- EX6 Parity Error Detected on the Load Data + lsu_xu_ex6_datc_par_err :out std_ulogic; -- EX6 Parity Error Detected + + --Rotated Data + ex6_xu_ld_data_b :out std_ulogic_vector(64-(2**regmode) to 63); + rel_xu_ld_data :out std_ulogic_vector(64-(2**regmode) to 63); + xu_fu_ex6_load_data :out std_ulogic_vector(0 to 255); + xu_fu_ex5_load_le :out std_ulogic; -- AXU load/reload was little endian swapped + + -- Debug Data Compare + lsu_xu_rel_dvc_thrd_id :out std_ulogic_vector(0 to 3); -- DVC compared to a Threads Reload + lsu_xu_ex2_dvc1_st_cmp :out std_ulogic_vector(0 to ((2**regmode)/8)-1); + lsu_xu_ex8_dvc1_ld_cmp :out std_ulogic_vector(0 to ((2**regmode)/8)-1); + lsu_xu_rel_dvc1_en :out std_ulogic; + lsu_xu_rel_dvc1_cmp :out std_ulogic_vector(0 to ((2**regmode)/8)-1); + lsu_xu_ex2_dvc2_st_cmp :out std_ulogic_vector(0 to ((2**regmode)/8)-1); + lsu_xu_ex8_dvc2_ld_cmp :out std_ulogic_vector(0 to ((2**regmode)/8)-1); + lsu_xu_rel_dvc2_en :out std_ulogic; + lsu_xu_rel_dvc2_cmp :out std_ulogic_vector(0 to ((2**regmode)/8)-1); + + -- Debug Bus IO + pc_xu_trace_bus_enable :in std_ulogic; + lsudat_debug_mux_ctrls :in std_ulogic_vector(0 to 1); + lsu_xu_data_debug0 :out std_ulogic_vector(0 to 87); + lsu_xu_data_debug1 :out std_ulogic_vector(0 to 87); + lsu_xu_data_debug2 :out std_ulogic_vector(0 to 87); + + --pervasive + vdd :inout power_logic; + gnd :inout power_logic; + vcs :inout power_logic; + nclk :in clk_logic; + an_ac_scan_dis_dc_b :in std_ulogic; + + -- G6T ABIST Control + pc_xu_abist_g6t_bw :in std_ulogic_vector(0 to 1); + pc_xu_abist_di_g6t_2r :in std_ulogic_vector(0 to 3); + pc_xu_abist_wl512_comp_ena :in std_ulogic; + pc_xu_abist_dcomp_g6t_2r :in std_ulogic_vector(0 to 3); + pc_xu_abist_g6t_r_wb :in std_ulogic; + + -- SCAN Ports + abst_scan_in :in std_ulogic_vector(0 to 1); + repr_scan_in :in std_ulogic; + gptr_scan_in :in std_ulogic; + time_scan_in :in std_ulogic; + func_scan_in :in std_ulogic_vector(0 to 3); + abst_scan_out :out std_ulogic_vector(0 to 1); + repr_scan_out :out std_ulogic; + time_scan_out :out std_ulogic; + gptr_scan_out :out std_ulogic; + func_scan_out :out std_ulogic_vector(0 to 3) +); + +-- synopsys translate_off + + +-- synopsys translate_on +end xuq_fxua_data; +architecture xuq_fxua_data of xuq_fxua_data is + +signal rel_xu_ld_data_int :std_ulogic_vector(64-(2**regmode) to 64+((2**regmode)/8)-1); +signal dat_abst_scan_in :std_ulogic; +signal dat_time_scan_in :std_ulogic; + +begin + + xuq_fxu_a : entity work.xuq_fxu_a(xuq_fxu_a) + generic map( + expand_type => expand_type, + threads => threads, + eff_ifar => eff_ifar, + regmode => regmode, + regsize => regsize, + a2mode => a2mode, + hvmode => hvmode, + real_data_add => real_data_add) + port map( + nclk => nclk, + vdd => vdd, + gnd => gnd, + vcs => vcs, + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b, + func_scan_in => func_scan_in(0 to 0), + func_scan_out => func_scan_out(0 to 0), + abst_scan_in => abst_scan_in(0), + abst_scan_out => abst_scan_out(0), + an_ac_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc, + pc_xu_abist_raddr_0 => pc_xu_abist_raddr_0(2 to 9), + pc_xu_abist_raddr_1 => pc_xu_abist_raddr_1(2 to 9), + pc_xu_abist_grf_renb_0 => pc_xu_abist_grf_renb_0, + pc_xu_abist_grf_renb_1 => pc_xu_abist_grf_renb_1, + pc_xu_abist_ena_dc => pc_xu_abist_ena_dc, + pc_xu_abist_waddr_0 => pc_xu_abist_waddr_0(2 to 9), + pc_xu_abist_waddr_1 => pc_xu_abist_waddr_1(2 to 9), + pc_xu_abist_grf_wenb_0 => pc_xu_abist_grf_wenb_0, + pc_xu_abist_grf_wenb_1 => pc_xu_abist_grf_wenb_1, + pc_xu_abist_di_0 => pc_xu_abist_di_0, + pc_xu_abist_di_1 => pc_xu_abist_di_1, + pc_xu_abist_wl144_comp_ena => pc_xu_abist_wl144_comp_ena, + pc_xu_abist_raw_dc_b => pc_xu_abist_raw_dc_b, + pc_xu_ccflush_dc => pc_xu_ccflush_dc, + clkoff_dc_b => clkoff_dc_b, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc(4 to 4), + mpw1_dc_b => mpw1_dc_b(4 to 4), + mpw2_dc_b => mpw2_dc_b, + bolt_sl_thold_2 => bolt_sl_thold_2, + bo_enable_2 => bo_enable_2, + pc_xu_bo_unload => pc_xu_bo_unload, + pc_xu_bo_load => pc_xu_bo_load, + pc_xu_bo_reset => pc_xu_bo_reset, + pc_xu_bo_shdata => pc_xu_bo_shdata, + pc_xu_bo_select => pc_xu_bo_select(7 to 8), + xu_pc_bo_fail => xu_pc_bo_fail(7 to 8), + xu_pc_bo_diagout => xu_pc_bo_diagout(7 to 8), + an_ac_scan_diag_dc => an_ac_scan_diag_dc, + scan_dis_dc_b => an_ac_scan_dis_dc_b, + sg_2 => sg_2(0 to 0), + fce_2 => fce_2(0 to 0), + func_sl_thold_2 => func_sl_thold_2(0 to 0), + func_nsl_thold_2 => func_nsl_thold_2, + abst_sl_thold_2 => abst_sl_thold_2, + time_sl_thold_2 => time_sl_thold_2, + ary_nsl_thold_2 => ary_nsl_thold_2, + gptr_sl_thold_2 => gptr_sl_thold_2, + time_scan_in => time_scan_in, + time_scan_out => dat_time_scan_in, + gptr_scan_in => gptr_scan_in, + gptr_scan_out => gptr_scan_out, + iu_xu_is2_vld => iu_xu_is2_vld, + iu_xu_is2_ifar => iu_xu_is2_ifar, + iu_xu_is2_tid => iu_xu_is2_tid, + iu_xu_is2_instr => iu_xu_is2_instr, + iu_xu_is2_ta_vld => iu_xu_is2_ta_vld, + iu_xu_is2_ta => iu_xu_is2_ta, + iu_xu_is2_s1_vld => iu_xu_is2_s1_vld, + iu_xu_is2_s1 => iu_xu_is2_s1, + iu_xu_is2_s2_vld => iu_xu_is2_s2_vld, + iu_xu_is2_s2 => iu_xu_is2_s2, + iu_xu_is2_s3_vld => iu_xu_is2_s3_vld, + iu_xu_is2_s3 => iu_xu_is2_s3, + iu_xu_is2_axu_ld_or_st => iu_xu_is2_axu_ld_or_st, + iu_xu_is2_axu_store => iu_xu_is2_axu_store, + iu_xu_is2_axu_ldst_size => iu_xu_is2_axu_ldst_size, + iu_xu_is2_axu_ldst_update => iu_xu_is2_axu_ldst_update, + iu_xu_is2_axu_ldst_forcealign => iu_xu_is2_axu_ldst_forcealign, + iu_xu_is2_axu_ldst_forceexcept => iu_xu_is2_axu_ldst_forceexcept, + iu_xu_is2_axu_ldst_extpid => iu_xu_is2_axu_ldst_extpid, + iu_xu_is2_axu_ldst_indexed => iu_xu_is2_axu_ldst_indexed, + iu_xu_is2_axu_ldst_tag => iu_xu_is2_axu_ldst_tag, + iu_xu_is2_axu_mftgpr => iu_xu_is2_axu_mftgpr, + iu_xu_is2_axu_mffgpr => iu_xu_is2_axu_mffgpr, + iu_xu_is2_axu_movedp => iu_xu_is2_axu_movedp, + iu_xu_is2_axu_instr_type => iu_xu_is2_axu_instr_type, + iu_xu_is2_pred_update => iu_xu_is2_pred_update, + iu_xu_is2_pred_taken_cnt => iu_xu_is2_pred_taken_cnt, + iu_xu_is2_error => iu_xu_is2_error, + iu_xu_is2_match => iu_xu_is2_match, + iu_xu_is2_is_ucode => iu_xu_is2_is_ucode, + iu_xu_is2_ucode_vld => iu_xu_is2_ucode_vld, + iu_xu_is2_gshare => iu_xu_is2_gshare, + xu_iu_multdiv_done => xu_iu_multdiv_done, + xu_iu_membar_tid => xu_iu_membar_tid, + lsu_xu_ldq_barr_done => lsu_xu_ldq_barr_done, + lsu_xu_barr_done => lsu_xu_barr_done, + fxa_fxb_rf0_val => fxa_fxb_rf0_val, + fxa_fxb_rf0_issued => fxa_fxb_rf0_issued, + fxa_fxb_rf0_ucode_val => fxa_fxb_rf0_ucode_val, + fxa_fxb_rf0_act => fxa_fxb_rf0_act, + fxa_fxb_ex1_hold_ctr_flush => fxa_fxb_ex1_hold_ctr_flush, + fxa_fxb_rf0_instr => fxa_fxb_rf0_instr, + fxa_fxb_rf0_tid => fxa_fxb_rf0_tid, + fxa_fxb_rf0_ta_vld => fxa_fxb_rf0_ta_vld, + fxa_fxb_rf0_ta => fxa_fxb_rf0_ta, + fxa_fxb_rf0_error => fxa_fxb_rf0_error, + fxa_fxb_rf0_match => fxa_fxb_rf0_match, + fxa_fxb_rf0_is_ucode => fxa_fxb_rf0_is_ucode, + fxa_fxb_rf0_gshare => fxa_fxb_rf0_gshare, + fxa_fxb_rf0_ifar => fxa_fxb_rf0_ifar, + fxa_fxb_rf0_s1_vld => fxa_fxb_rf0_s1_vld, + fxa_fxb_rf0_s1 => fxa_fxb_rf0_s1, + fxa_fxb_rf0_s2_vld => fxa_fxb_rf0_s2_vld, + fxa_fxb_rf0_s2 => fxa_fxb_rf0_s2, + fxa_fxb_rf0_s3_vld => fxa_fxb_rf0_s3_vld, + fxa_fxb_rf0_s3 => fxa_fxb_rf0_s3, + fxa_fxb_rf0_axu_instr_type => fxa_fxb_rf0_axu_instr_type, + fxa_fxb_rf0_axu_ld_or_st => fxa_fxb_rf0_axu_ld_or_st, + fxa_fxb_rf0_axu_store => fxa_fxb_rf0_axu_store, + fxa_fxb_rf0_axu_mftgpr => fxa_fxb_rf0_axu_mftgpr, + fxa_fxb_rf0_axu_mffgpr => fxa_fxb_rf0_axu_mffgpr, + fxa_fxb_rf0_axu_movedp => fxa_fxb_rf0_axu_movedp, + fxa_fxb_rf0_axu_ldst_size => fxa_fxb_rf0_axu_ldst_size, + fxa_fxb_rf0_axu_ldst_update => fxa_fxb_rf0_axu_ldst_update, + fxa_fxb_rf0_axu_ldst_forcealign => fxa_fxb_rf0_axu_ldst_forcealign, + fxa_fxb_rf0_axu_ldst_forceexcept => fxa_fxb_rf0_axu_ldst_forceexcept, + fxa_fxb_rf0_axu_ldst_indexed => fxa_fxb_rf0_axu_ldst_indexed, + fxa_fxb_rf0_axu_ldst_tag => fxa_fxb_rf0_axu_ldst_tag, + fxa_fxb_rf0_pred_update => fxa_fxb_rf0_pred_update, + fxa_fxb_rf0_pred_taken_cnt => fxa_fxb_rf0_pred_taken_cnt, + fxa_fxb_rf0_mc_dep_chk_val => fxa_fxb_rf0_mc_dep_chk_val, + fxa_fxb_rf1_mul_val => fxa_fxb_rf1_mul_val, + fxa_fxb_rf1_muldiv_coll => fxa_fxb_rf1_muldiv_coll, + fxa_fxb_rf1_div_val => fxa_fxb_rf1_div_val, + fxa_fxb_rf1_div_ctr => fxa_fxb_rf1_div_ctr, + fxa_fxb_rf0_xu_epid_instr => fxa_fxb_rf0_xu_epid_instr, + fxa_fxb_rf0_axu_is_extload => fxa_fxb_rf0_axu_is_extload, + fxa_fxb_rf0_axu_is_extstore => fxa_fxb_rf0_axu_is_extstore, + fxa_fxb_rf0_is_mfocrf => fxa_fxb_rf0_is_mfocrf, + fxa_fxb_rf0_3src_instr => fxa_fxb_rf0_3src_instr, + fxa_fxb_rf0_gpr0_zero => fxa_fxb_rf0_gpr0_zero, + fxa_fxb_rf0_use_imm => fxa_fxb_rf0_use_imm, + fxb_fxa_ex7_we0 => fxb_fxa_ex7_we0, + fxb_fxa_ex7_wa0 => fxb_fxa_ex7_wa0, + fxb_fxa_ex7_wd0 => fxb_fxa_ex7_wd0, + fxa_fxb_rf1_do0 => fxa_fxb_rf1_do0, + fxa_fxb_rf1_do1 => fxa_fxb_rf1_do1, + fxa_fxb_rf1_do2 => fxa_fxb_rf1_do2, + fxb_fxa_ex6_clear_barrier => fxb_fxa_ex6_clear_barrier, + fxa_perf_muldiv_in_use => fxa_perf_muldiv_in_use, + dec_cpl_ex3_mc_dep_chk_val => dec_cpl_ex3_mc_dep_chk_val, + xu_is2_flush => xu_is2_flush, + xu_rf0_flush => xu_rf0_flush, + xu_rf1_flush => xu_rf1_flush, + xu_ex1_flush => xu_ex1_flush, + xu_ex2_flush => xu_ex2_flush, + xu_ex3_flush => xu_ex3_flush, + xu_ex4_flush => xu_ex4_flush, + xu_ex5_flush => xu_ex5_flush, + fxa_cpl_ex2_div_coll => fxa_cpl_ex2_div_coll, + cpl_fxa_ex5_set_barr => cpl_fxa_ex5_set_barr, + fxa_iu_set_barr_tid => fxa_iu_set_barr_tid, + spr_xucr4_div_barr_thres => spr_xucr4_div_barr_thres, + an_ac_back_inv => an_ac_back_inv, + an_ac_back_inv_addr => an_ac_back_inv_addr(62 to 63), + an_ac_back_inv_target_bit3 => an_ac_back_inv_target_bit3, + dec_spr_rf0_instr => dec_spr_rf0_instr, + pc_xu_inj_regfile_parity => pc_xu_inj_regfile_parity, + xu_pc_err_regfile_parity => xu_pc_err_regfile_parity, + xu_pc_err_regfile_ue => xu_pc_err_regfile_ue, + gpr_cpl_ex3_regfile_err_det => gpr_cpl_ex3_regfile_err_det, + cpl_gpr_regfile_seq_beg => cpl_gpr_regfile_seq_beg, + gpr_cpl_regfile_seq_end => gpr_cpl_regfile_seq_end, + xu_lsu_rf0_derat_is_extload => xu_lsu_rf0_derat_is_extload, + xu_lsu_rf0_derat_is_extstore => xu_lsu_rf0_derat_is_extstore, + xu_lsu_rf0_derat_val => xu_lsu_rf0_derat_val, + lsu_xu_rel_wren => lsu_xu_rel_wren, + lsu_xu_rel_ta_gpr => lsu_xu_rel_ta_gpr, + lsu_xu_rot_rel_data => rel_xu_ld_data_int, + fxa_fxb_rf0_spr_tid => fxa_fxb_rf0_spr_tid, + fxa_fxb_rf0_cpl_tid => fxa_fxb_rf0_cpl_tid, + fxa_fxb_rf0_cpl_act => fxa_fxb_rf0_cpl_act, + fxa_cpl_debug => fxa_cpl_debug, + spr_xucr0_clkg_ctl_b0 => spr_xucr0_clkg_ctl_b0 + ); + + +lsudata : entity work.xuq_lsu_data(xuq_lsu_data) +generic map(expand_type => expand_type, + regmode => regmode, + dc_size => dc_size, + l_endian_m => l_endian_m) +port map( + + -- Execution Pipe + xu_lsu_rf1_data_act => xu_lsu_rf1_data_act, + xu_lsu_rf1_axu_ldst_falign => xu_lsu_rf1_axu_ldst_falign, + xu_lsu_ex1_store_data => xu_lsu_ex1_store_data, + xu_lsu_ex1_eff_addr => xu_lsu_ex1_eff_addr, + xu_lsu_ex1_rotsel_ovrd => xu_lsu_ex1_rotsel_ovrd, + ex1_optype32 => ex1_optype32, + ex1_optype16 => ex1_optype16, + ex1_optype8 => ex1_optype8, + ex1_optype4 => ex1_optype4, + ex1_optype2 => ex1_optype2, + ex1_optype1 => ex1_optype1, + ex1_store_instr => ex1_store_instr, + ex1_axu_op_val => ex1_axu_op_val, + ex1_saxu_instr => ex1_saxu_instr, + ex1_sdp_instr => ex1_sdp_instr, + ex1_stgpr_instr => ex1_stgpr_instr, + fu_xu_ex2_store_data_val => fu_xu_ex2_store_data_val, + fu_xu_ex2_store_data => fu_xu_ex2_store_data, + + ex3_algebraic => ex3_algebraic, + ex3_data_swap => ex3_data_swap, + ex3_thrd_id => ex3_thrd_id, + ex5_dp_data => bx_xu_ex5_dp_data, + + -- Debug Data Compare + ex4_load_op_hit => ex4_load_op_hit, + ex4_store_hit => ex4_store_hit, + ex4_axu_op_val => ex4_axu_op_val, + spr_dvc1_act => spr_dvc1_act, + spr_dvc2_act => spr_dvc2_act, + spr_dvc1_dbg => spr_dvc1_dbg, + spr_dvc2_dbg => spr_dvc2_dbg, + + -- Update Data Array Valid + rel_upd_dcarr_val => rel_upd_dcarr_val, + + -- Instruction Flush + xu_lsu_ex4_flush => xu_ex4_flush, + xu_lsu_ex4_flush_local => xu_lsu_ex4_flush_local, + xu_lsu_ex5_flush => xu_ex5_flush, + + -- Error Inject + xu_pc_err_dcache_parity => xu_pc_err_dcache_parity, + pc_xu_inj_dcache_parity => pc_xu_inj_dcache_parity, + + -- Config Bits + xu_lsu_spr_xucr0_dcdis => xu_lsu_spr_xucr0_dcdis, + spr_xucr0_clkg_ctl_b0 => spr_xucr0_clkg_ctl_b0, + + -- Reload Pipe + ldq_rel_data_val_early => ldq_rel_data_val_early, + ldq_rel_algebraic => ldq_rel_algebraic, + ldq_rel_data_val => ldq_rel_data_val, + ldq_rel_ci => ldq_rel_ci, + ldq_rel_thrd_id => ldq_rel_thrd_id, + ldq_rel_axu_val => ldq_rel_axu_val, + ldq_rel_data => ldq_rel_256_data, + ldq_rel_rot_sel => ldq_rel_rot_sel, + ldq_rel_op_size => ldq_rel_op_size, + ldq_rel_le_mode => ldq_rel_le_mode, + ldq_rel_dvc1_en => ldq_rel_dvc1_en, + ldq_rel_dvc2_en => ldq_rel_dvc2_en, + ldq_rel_beat_crit_qw => ldq_rel_beat_crit_qw, + ldq_rel_beat_crit_qw_block => ldq_rel_beat_crit_qw_block, + ldq_rel_addr => ldq_rel_addr, + + -- Data Cache Update + dcarr_up_way_addr => dcarr_up_way_addr, + + -- Execution Pipe Outputs + ex4_256st_data => ex4_256st_data, + ex6_ld_par_err => ex6_ld_par_err, + lsu_xu_ex6_datc_par_err => lsu_xu_ex6_datc_par_err, + + --Rotated Data + ex6_xu_ld_data_b => ex6_xu_ld_data_b, + rel_xu_ld_data => rel_xu_ld_data_int, + xu_fu_ex6_load_data => xu_fu_ex6_load_data, + xu_fu_ex5_load_le => xu_fu_ex5_load_le, + + -- Debug Data Compare + lsu_xu_rel_dvc_thrd_id => lsu_xu_rel_dvc_thrd_id, + lsu_xu_ex2_dvc1_st_cmp => lsu_xu_ex2_dvc1_st_cmp, + lsu_xu_ex8_dvc1_ld_cmp => lsu_xu_ex8_dvc1_ld_cmp, + lsu_xu_rel_dvc1_en => lsu_xu_rel_dvc1_en, + lsu_xu_rel_dvc1_cmp => lsu_xu_rel_dvc1_cmp, + lsu_xu_ex2_dvc2_st_cmp => lsu_xu_ex2_dvc2_st_cmp, + lsu_xu_ex8_dvc2_ld_cmp => lsu_xu_ex8_dvc2_ld_cmp, + lsu_xu_rel_dvc2_en => lsu_xu_rel_dvc2_en, + lsu_xu_rel_dvc2_cmp => lsu_xu_rel_dvc2_cmp, + + -- Debug Bus IO + pc_xu_trace_bus_enable => pc_xu_trace_bus_enable, + lsudat_debug_mux_ctrls => lsudat_debug_mux_ctrls, + lsu_xu_data_debug0 => lsu_xu_data_debug0, + lsu_xu_data_debug1 => lsu_xu_data_debug1, + lsu_xu_data_debug2 => lsu_xu_data_debug2, + + --pervasive + vdd => vdd, + gnd => gnd, + vcs => vcs, + nclk => nclk, + pc_xu_ccflush_dc => pc_xu_ccflush_dc, + clkoff_dc_b => clkoff_dc_b, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc(4 to 4), + mpw1_dc_b => mpw1_dc_b(4 to 4), + mpw2_dc_b => mpw2_dc_b, + g6t_clkoff_dc_b => g6t_clkoff_dc_b, + g6t_d_mode_dc => g6t_d_mode_dc, + g6t_delay_lclkr_dc => g6t_delay_lclkr_dc, + g6t_mpw1_dc_b => g6t_mpw1_dc_b, + g6t_mpw2_dc_b => g6t_mpw2_dc_b, + sg_2 => sg_2(2), + fce_2 => fce_2(0), + func_sl_thold_2 => func_sl_thold_2(3), + func_nsl_thold_2 => func_nsl_thold_2, + abst_sl_thold_2 => abst_sl_thold_2, + time_sl_thold_2 => time_sl_thold_2, + ary_nsl_thold_2 => ary_nsl_thold_2, + repr_sl_thold_2 => repr_sl_thold_2, + bolt_sl_thold_2 => bolt_sl_thold_2, + bo_enable_2 => bo_enable_2, + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b, + an_ac_scan_diag_dc => an_ac_scan_diag_dc, + + -- G6T ABIST Control + an_ac_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc, + pc_xu_abist_ena_dc => pc_xu_abist_ena_dc, + pc_xu_abist_g6t_bw => pc_xu_abist_g6t_bw, + pc_xu_abist_di_g6t_2r => pc_xu_abist_di_g6t_2r, + pc_xu_abist_wl512_comp_ena => pc_xu_abist_wl512_comp_ena, + pc_xu_abist_raw_dc_b => pc_xu_abist_raw_dc_b, + pc_xu_abist_dcomp_g6t_2r => pc_xu_abist_dcomp_g6t_2r, + pc_xu_abist_raddr_0 => pc_xu_abist_raddr_0(1 to 9), + pc_xu_abist_g6t_r_wb => pc_xu_abist_g6t_r_wb, + pc_xu_bo_unload => pc_xu_bo_unload, + pc_xu_bo_repair => pc_xu_bo_repair, + pc_xu_bo_reset => pc_xu_bo_reset, + pc_xu_bo_shdata => pc_xu_bo_shdata, + pc_xu_bo_select => pc_xu_bo_select(5 to 6), + xu_pc_bo_fail => xu_pc_bo_fail(5 to 6), + xu_pc_bo_diagout => xu_pc_bo_diagout(5 to 6), + + -- SCAN PORTS + abst_scan_in(0) => abst_scan_in(1), + abst_scan_in(1) => dat_abst_scan_in, + abst_scan_out(0) => dat_abst_scan_in, + abst_scan_out(1) => abst_scan_out(1), + + time_scan_in => dat_time_scan_in, + repr_scan_in => repr_scan_in, + time_scan_out => time_scan_out, + repr_scan_out => repr_scan_out, + func_scan_in => func_scan_in(1 to 3), + func_scan_out => func_scan_out(1 to 3) +); + +rel_xu_ld_data <= rel_xu_ld_data_int(64-(2**regmode) to 63); + +mark_unused(sg_2(1)); +mark_unused(func_sl_thold_2(1 to 2)); + +end xuq_fxua_data; diff --git a/rel/src/vhdl/work/xuq_lsu_cmd.vhdl b/rel/src/vhdl/work/xuq_lsu_cmd.vhdl new file mode 100644 index 0000000..252cab2 --- /dev/null +++ b/rel/src/vhdl/work/xuq_lsu_cmd.vhdl @@ -0,0 +1,2797 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XU LSU L1 Data Directory and L2 Command Queue Wrapper +library ibm, ieee, work, tri, support; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use tri.tri_latches_pkg.all; +use support.power_logic_pkg.all; +use work.xuq_pkg.mark_unused; + +-- ########################################################################################## +-- VHDL Contents +-- 1) L2 Command Queue +-- 2) Valid Register Array +-- 3) LRU Register Array +-- 4) Data Cache Control +-- 5) Flush Generation +-- 6) 8 way tag compare +-- 7) Parity Check +-- 8) Reload Update +-- ########################################################################################## +entity xuq_lsu_cmd is +generic(expand_type : integer := 2; + lmq_entries : integer := 8; + l_endian_m : integer := 1; + regmode : integer := 6; + dc_size : natural := 14; -- 2^14 = 16384 Bytes L1 D$ + cl_size : natural := 6; -- 2^6 = 64 Bytes CacheLines + real_data_add : integer := 42; + a2mode : integer := 1; + load_credits : integer := 4; + store_credits : integer := 20; + st_data_32B_mode : integer := 1; -- 0 = 16B store data to L2, 1 = 32B data + bcfg_epn_0to15 : integer := 0; + bcfg_epn_16to31 : integer := 0; + bcfg_epn_32to47 : integer := (2**16)-1; + bcfg_epn_48to51 : integer := (2**4)-1; + bcfg_rpn_22to31 : integer := (2**10)-1; + bcfg_rpn_32to47 : integer := (2**16)-1; + bcfg_rpn_48to51 : integer := (2**4)-1); +port( + xu_lsu_rf0_act :in std_ulogic; + xu_lsu_rf1_cmd_act :in std_ulogic; + xu_lsu_rf1_axu_op_val :in std_ulogic; + xu_lsu_rf1_axu_ldst_falign :in std_ulogic; + xu_lsu_rf1_axu_ldst_fexcpt :in std_ulogic; -- AXU force alignment exception on misaligned access + xu_lsu_rf1_cache_acc :in std_ulogic; + xu_lsu_rf1_thrd_id :in std_ulogic_vector(0 to 3); + xu_lsu_rf1_optype1 :in std_ulogic; + xu_lsu_rf1_optype2 :in std_ulogic; + xu_lsu_rf1_optype4 :in std_ulogic; + xu_lsu_rf1_optype8 :in std_ulogic; + xu_lsu_rf1_optype16 :in std_ulogic; + xu_lsu_rf1_optype32 :in std_ulogic; + xu_lsu_rf1_target_gpr :in std_ulogic_vector(0 to 8); + xu_lsu_rf1_mtspr_trace :in std_ulogic; -- Operation is a mtspr trace instruction + xu_lsu_rf1_load_instr :in std_ulogic; + xu_lsu_rf1_store_instr :in std_ulogic; + xu_lsu_rf1_dcbf_instr :in std_ulogic; + xu_lsu_rf1_sync_instr :in std_ulogic; + xu_lsu_rf1_l_fld :in std_ulogic_vector(0 to 1); + xu_lsu_rf1_dcbi_instr :in std_ulogic; + xu_lsu_rf1_dcbz_instr :in std_ulogic; + xu_lsu_rf1_dcbt_instr :in std_ulogic; + xu_lsu_rf1_dcbtst_instr :in std_ulogic; + xu_lsu_rf1_th_fld :in std_ulogic_vector(0 to 4); + xu_lsu_rf1_dcbtls_instr :in std_ulogic; + xu_lsu_rf1_dcbtstls_instr :in std_ulogic; + xu_lsu_rf1_dcblc_instr :in std_ulogic; + xu_lsu_rf1_dcbst_instr :in std_ulogic; + xu_lsu_rf1_icbi_instr :in std_ulogic; + xu_lsu_rf1_icblc_instr :in std_ulogic; + xu_lsu_rf1_icbt_instr :in std_ulogic; + xu_lsu_rf1_icbtls_instr :in std_ulogic; + xu_lsu_rf1_icswx_instr :in std_ulogic; + xu_lsu_rf1_icswx_dot_instr :in std_ulogic; + xu_lsu_rf1_icswx_epid :in std_ulogic; + xu_lsu_rf1_tlbsync_instr :in std_ulogic; + xu_lsu_rf1_ldawx_instr :in std_ulogic; + xu_lsu_rf1_wclr_instr :in std_ulogic; + xu_lsu_rf1_wchk_instr :in std_ulogic; + xu_lsu_rf1_lock_instr :in std_ulogic; + xu_lsu_rf1_mutex_hint :in std_ulogic; -- Mutex Hint For larx instructions + xu_lsu_rf1_mbar_instr :in std_ulogic; + xu_lsu_rf1_is_msgsnd :in std_ulogic; + xu_lsu_rf1_dci_instr :in std_ulogic; -- DCI instruction is valid + xu_lsu_rf1_ici_instr :in std_ulogic; -- ICI instruction is valid + xu_lsu_rf1_algebraic :in std_ulogic; + xu_lsu_rf1_byte_rev :in std_ulogic; + xu_lsu_rf1_src_gpr :in std_ulogic; + xu_lsu_rf1_src_axu :in std_ulogic; + xu_lsu_rf1_src_dp :in std_ulogic; + xu_lsu_rf1_targ_gpr :in std_ulogic; + xu_lsu_rf1_targ_axu :in std_ulogic; + xu_lsu_rf1_targ_dp :in std_ulogic; + xu_lsu_ex4_val :in std_ulogic_vector(0 to 3); -- There is a valid Instruction in EX4 + xu_lsu_ex1_add_src0 :in std_ulogic_vector(64-(2**REGMODE) to 63); + xu_lsu_ex1_add_src1 :in std_ulogic_vector(64-(2**REGMODE) to 63); + xu_lsu_ex2_instr_trace_val :in std_ulogic; + + xu_lsu_rf1_src0_vld :in std_ulogic; + xu_lsu_rf1_src0_reg :in std_ulogic_vector(0 to 7); + xu_lsu_rf1_src1_vld :in std_ulogic; + xu_lsu_rf1_src1_reg :in std_ulogic_vector(0 to 7); + xu_lsu_rf1_targ_vld :in std_ulogic; + xu_lsu_rf1_targ_reg :in std_ulogic_vector(0 to 7); + + -- Error Inject + pc_xu_inj_dcachedir_parity :in std_ulogic; + pc_xu_inj_dcachedir_multihit :in std_ulogic; + + ex4_256st_data :in std_ulogic_vector(0 to 255); + xu_lsu_ex4_dvc1_en :in std_ulogic; + xu_lsu_ex4_dvc2_en :in std_ulogic; + + xu_lsu_mtspr_trace_en :in std_ulogic_vector(0 to 3); + spr_xucr0_clkg_ctl_b1 :in std_ulogic; + spr_xucr0_clkg_ctl_b3 :in std_ulogic; + spr_xucr4_mmu_mchk :in std_ulogic; + xu_lsu_spr_xucr0_aflsta :in std_ulogic; + xu_lsu_spr_xucr0_flsta :in std_ulogic; + xu_lsu_spr_xucr0_l2siw :in std_ulogic; + xu_lsu_spr_xucr0_dcdis :in std_ulogic; + xu_lsu_spr_xucr0_wlk :in std_ulogic; + xu_lsu_spr_xucr0_clfc :in std_ulogic; + xu_lsu_spr_xucr0_flh2l2 :in std_ulogic; + xu_lsu_spr_xucr0_cred :in std_ulogic; + xu_lsu_spr_xucr0_rel :in std_ulogic; + xu_lsu_spr_xucr0_mbar_ack :in std_ulogic; + xu_lsu_spr_xucr0_tlbsync :in std_ulogic; -- use sync_ack from L2 for tlbsync when 1 + xu_lsu_spr_xucr0_cls :in std_ulogic; -- Cacheline Size = 1 => 128Byte size, 0 => 64Byte size + xu_lsu_spr_ccr2_dfrat :in std_ulogic; + xu_lsu_spr_ccr2_dfratsc :in std_ulogic_vector(0 to 8); + + an_ac_flh2l2_gate :in std_ulogic; -- Gate L1 Hit forwarding SPR config bit + + xu_lsu_dci :in std_ulogic; + + -- ERAT Operations + xu_lsu_rf0_derat_val :in std_ulogic_vector(0 to 3); -- TLB Valid Operation + xu_lsu_rf1_derat_act :in std_ulogic; -- Derat Operation is Valid + xu_lsu_rf1_derat_ra_eq_ea :in std_ulogic; -- Bypass Erats on specific operations + xu_lsu_rf1_derat_is_load :in std_ulogic; -- Cache access should be treated as a load + xu_lsu_rf1_derat_is_store :in std_ulogic; -- Cache access should be treated as a store + xu_lsu_rf0_derat_is_extload :in std_ulogic; -- Cache access should be treated as an external load + xu_lsu_rf0_derat_is_extstore :in std_ulogic; -- Cache access should be treated as an external store + xu_lsu_rf1_is_eratre :in std_ulogic; -- erat Read Operation + xu_lsu_rf1_is_eratwe :in std_ulogic; -- erat Write Operation + xu_lsu_rf1_is_eratsx :in std_ulogic; -- erat Search Operation + xu_lsu_rf1_is_eratilx :in std_ulogic; -- erat Invalidate Local Operation + xu_lsu_ex1_is_isync :in std_ulogic; -- instr. synch decode + xu_lsu_ex1_is_csync :in std_ulogic; -- context synch decode + xu_lsu_rf1_is_touch :in std_ulogic; -- Instruction is a Touch operation + xu_lsu_rf1_ws :in std_ulogic_vector(0 to 1); -- ERAT WS Field + xu_lsu_rf1_t :in std_ulogic_vector(0 to 2); -- ERAT T Field + xu_lsu_ex1_rs_is :in std_ulogic_vector(0 to 8); -- ERAT invalidate select + xu_lsu_ex1_ra_entry :in std_ulogic_vector(0 to 4); -- ERAT Entry Number + xu_lsu_ex4_rs_data :in std_ulogic_vector(64-(2**REGMODE) to 63); -- ERAT Update Data + xu_lsu_msr_gs :in std_ulogic_vector(0 to 3); -- (MSR.HV) + xu_lsu_msr_pr :in std_ulogic_vector(0 to 3); -- Problem State (MSR.PR) + xu_lsu_msr_ds :in std_ulogic_vector(0 to 3); -- Addr Space (MSR.DS) + xu_lsu_msr_cm :in std_ulogic_vector(0 to 3); -- Comput Mode + xu_lsu_hid_mmu_mode :in std_ulogic; -- MMU mode + ex6_ld_par_err :in std_ulogic; + + xu_lsu_rf0_flush :in std_ulogic_vector(0 to 3); + xu_lsu_rf1_flush :in std_ulogic_vector(0 to 3); + xu_lsu_ex1_flush :in std_ulogic_vector(0 to 3); + xu_lsu_ex2_flush :in std_ulogic_vector(0 to 3); + xu_lsu_ex3_flush :in std_ulogic_vector(0 to 3); + xu_lsu_ex4_flush :in std_ulogic_vector(0 to 3); + xu_lsu_ex5_flush :in std_ulogic_vector(0 to 3); + + lsu_xu_ex4_tlb_data :out std_ulogic_vector(64-(2**REGMODE) to 63); + xu_mm_derat_req :out std_ulogic; + xu_mm_derat_thdid :out std_ulogic_vector(0 to 3); + xu_mm_derat_state :out std_ulogic_vector(0 to 3); + xu_mm_derat_tid :out std_ulogic_vector(0 to 13); + xu_mm_derat_lpid :out std_ulogic_vector(0 to 7); + xu_mm_derat_ttype :out std_ulogic_vector(0 to 1); + mm_xu_derat_rel_val :in std_ulogic_vector(0 to 4); + mm_xu_derat_rel_data :in std_ulogic_vector(0 to 131); + mm_xu_derat_pid0 :in std_ulogic_vector(0 to 13); -- Thread0 PID Number + mm_xu_derat_pid1 :in std_ulogic_vector(0 to 13); -- Thread1 PID Number + mm_xu_derat_pid2 :in std_ulogic_vector(0 to 13); -- Thread2 PID Number + mm_xu_derat_pid3 :in std_ulogic_vector(0 to 13); -- Thread3 PID Number + mm_xu_derat_mmucr0_0 :in std_ulogic_vector(0 to 19); + mm_xu_derat_mmucr0_1 :in std_ulogic_vector(0 to 19); + mm_xu_derat_mmucr0_2 :in std_ulogic_vector(0 to 19); + mm_xu_derat_mmucr0_3 :in std_ulogic_vector(0 to 19); + xu_mm_derat_mmucr0 :out std_ulogic_vector(0 to 17); + xu_mm_derat_mmucr0_we :out std_ulogic_vector(0 to 3); + mm_xu_derat_mmucr1 :in std_ulogic_vector(0 to 9); + xu_mm_derat_mmucr1 :out std_ulogic_vector(0 to 4); + xu_mm_derat_mmucr1_we :out std_ulogic; + mm_xu_derat_snoop_coming :in std_ulogic; + mm_xu_derat_snoop_val :in std_ulogic; + mm_xu_derat_snoop_attr :in std_ulogic_vector(0 to 25); + mm_xu_derat_snoop_vpn :in std_ulogic_vector(64-(2**REGMODE) to 51); + xu_mm_derat_snoop_ack :out std_ulogic; + + xu_lsu_slowspr_val :in std_ulogic; + xu_lsu_slowspr_rw :in std_ulogic; + xu_lsu_slowspr_etid :in std_ulogic_vector(0 to 1); + xu_lsu_slowspr_addr :in std_ulogic_vector(0 to 9); + xu_lsu_slowspr_data :in std_ulogic_vector(64-(2**REGMODE) to 63); + xu_lsu_slowspr_done :in std_ulogic; + slowspr_val_out :out std_ulogic; + slowspr_rw_out :out std_ulogic; + slowspr_etid_out :out std_ulogic_vector(0 to 1); + slowspr_addr_out :out std_ulogic_vector(0 to 9); + slowspr_data_out :out std_ulogic_vector(64-(2**REGMODE) to 63); + slowspr_done_out :out std_ulogic; + + ex1_optype1 :out std_ulogic; + ex1_optype2 :out std_ulogic; + ex1_optype4 :out std_ulogic; + ex1_optype8 :out std_ulogic; + ex1_optype16 :out std_ulogic; + ex1_optype32 :out std_ulogic; + ex1_saxu_instr :out std_ulogic; + ex1_sdp_instr :out std_ulogic; + ex1_stgpr_instr :out std_ulogic; + ex1_store_instr :out std_ulogic; + ex1_axu_op_val :out std_ulogic; + + lsu_xu_ex3_align :out std_ulogic_vector(0 to 3); + lsu_xu_ex3_dsi :out std_ulogic_vector(0 to 3); + lsu_xu_ex3_inval_align_2ucode :out std_ulogic; + lsu_xu_ex3_attr :out std_ulogic_vector(0 to 8); -- Page Attribute Bits + lsu_xu_ex3_derat_vf :out std_ulogic; + + lsu_xu_ex3_n_flush_req :out std_ulogic; + lsu_xu_datc_perr_recovery :out std_ulogic; + lsu_xu_l2_ecc_err_flush :out std_ulogic_vector(0 to 3); + lsu_xu_ex4_ldq_full_flush :out std_ulogic; + lsu_xu_ex3_ldq_hit_flush :out std_ulogic; + lsu_xu_ex3_dep_flush :out std_ulogic; + lsu_xu_ex3_l2_uc_ecc_err :out std_ulogic_vector(0 to 3); + lsu_xu_ex3_derat_par_err :out std_ulogic_vector(0 to 3); -- D-ERAT had a Parity Error + lsu_xu_ex3_derat_multihit_err :out std_ulogic_vector(0 to 3); -- D-ERAT had multiple hits + lsu_xu_ex4_derat_par_err :out std_ulogic_vector(0 to 3); -- D-ERAT had a Parity Error + derat_xu_ex3_miss :out std_ulogic_vector(0 to 3); -- D-ERAT detected an erat miss + derat_xu_ex3_dsi :out std_ulogic_vector(0 to 3); -- D-ERAT detected a data storage interrupt + derat_xu_ex3_n_flush_req :out std_ulogic_vector(0 to 3); -- D-ERAT needs an ex3 flush request + + ex3_algebraic :out std_ulogic; + ex3_data_swap :out std_ulogic; + ex3_thrd_id :out std_ulogic_vector(0 to 3); + xu_fu_ex3_eff_addr :out std_ulogic_vector(59 to 63); + + lsu_xu_ex3_ddir_par_err :out std_ulogic; + lsu_xu_ex4_n_lsu_ddmh_flush :out std_ulogic_vector(0 to 3); + + -- back invalidate + lsu_xu_is2_back_inv :out std_ulogic; + lsu_xu_is2_back_inv_addr :out std_ulogic_vector(64-real_data_add to 63-cl_size); + + -- Update Data Array Valid + rel_upd_dcarr_val :out std_ulogic; + + lsu_xu_ex4_cr_upd :out std_ulogic; + lsu_xu_ex5_cr_rslt :out std_ulogic; + lsu_xu_ex5_wren :out std_ulogic; + lsu_xu_rel_wren :out std_ulogic; + lsu_xu_rel_ta_gpr :out std_ulogic_vector(0 to 7); + lsu_xu_need_hole :out std_ulogic; + xu_fu_ex5_reload_val :out std_ulogic; + xu_fu_ex5_load_val :out std_ulogic_vector(0 to 3); + xu_fu_ex5_load_tag :out std_ulogic_vector(0 to 8); + + -- Data Array Controls + dcarr_up_way_addr :out std_ulogic_vector(0 to 2); + + -- SPR status + lsu_xu_spr_xucr0_cslc_xuop :out std_ulogic; -- Invalidate type instruction invalidated lock + lsu_xu_spr_xucr0_cslc_binv :out std_ulogic; -- Back-Invalidate invalidated lock + lsu_xu_spr_xucr0_clo :out std_ulogic; -- Cache Lock instruction caused an overlock + lsu_xu_spr_xucr0_cul :out std_ulogic; -- Cache Lock unable to lock + lsu_xu_spr_epsc_epr :out std_ulogic_vector(0 to 3); + lsu_xu_spr_epsc_egs :out std_ulogic_vector(0 to 3); + + -- Debug Data Compare + ex4_load_op_hit :out std_ulogic; + ex4_store_hit :out std_ulogic; + ex4_axu_op_val :out std_ulogic; + spr_dvc1_act :out std_ulogic; + spr_dvc2_act :out std_ulogic; + spr_dvc1_dbg :out std_ulogic_vector(64-(2**regmode) to 63); + spr_dvc2_dbg :out std_ulogic_vector(64-(2**regmode) to 63); + + -- Inputs from L2 + an_ac_req_ld_pop :in std_ulogic; + an_ac_req_st_pop :in std_ulogic; + an_ac_req_st_gather :in std_ulogic; + an_ac_req_st_pop_thrd :in std_ulogic_vector(0 to 2); -- decrement outbox credit count + + an_ac_reld_data_val :in std_ulogic; + an_ac_reld_core_tag :in std_ulogic_vector(0 to 4); + an_ac_reld_qw :in std_ulogic_vector(57 to 59); + an_ac_reld_data :in std_ulogic_vector(0 to 127); + an_ac_reld_data_coming :in std_ulogic; + an_ac_reld_ditc :in std_ulogic; + an_ac_reld_crit_qw :in std_ulogic; + an_ac_reld_l1_dump :in std_ulogic; + + an_ac_reld_ecc_err :in std_ulogic; + an_ac_reld_ecc_err_ue :in std_ulogic; + + an_ac_back_inv :in std_ulogic; + an_ac_back_inv_addr :in std_ulogic_vector(64-real_data_add to 63); + an_ac_back_inv_target_bit1 :in std_ulogic; + an_ac_back_inv_target_bit4 :in std_ulogic; + an_ac_req_spare_ctrl_a1 :in std_ulogic_vector(0 to 3); + + an_ac_stcx_complete :in std_ulogic_vector(0 to 3); + xu_iu_stcx_complete : out std_ulogic_vector(0 to 3); + xu_iu_reld_core_tag_clone :out std_ulogic_vector(1 to 4); + xu_iu_reld_data_coming_clone :out std_ulogic; + xu_iu_reld_data_vld_clone :out std_ulogic; + xu_iu_reld_ditc_clone :out std_ulogic; + +-- redrive to boxes logic + lsu_reld_data_vld :out std_ulogic; -- reload data is coming in 2 cycles + lsu_reld_core_tag :out std_ulogic_vector(3 to 4); -- reload data destinatoin tag (thread) + lsu_reld_qw :out std_ulogic_vector(58 to 59); -- reload data destinatoin tag (thread) + lsu_reld_ecc_err :out std_ulogic; -- reload data has ecc error + lsu_reld_ditc :out std_ulogic; -- reload data is for ditc (inbox) + lsu_reld_data :out std_ulogic_vector(0 to 127); -- reload data + + lsu_req_st_pop :out std_ulogic; -- decrement outbox credit count + lsu_req_st_pop_thrd :out std_ulogic_vector(0 to 2); -- decrement outbox credit count + + -- Instruction Fetches + i_x_ra :in std_ulogic_vector(64-real_data_add to 59); + i_x_request :in std_ulogic; + i_x_wimge :in std_ulogic_vector(0 to 4); + i_x_thread :in std_ulogic_vector(0 to 3); + i_x_userdef :in std_ulogic_vector(0 to 3); + + -- MMU instruction interface + mm_xu_lsu_req :in std_ulogic_vector(0 to 3); + mm_xu_lsu_ttype :in std_ulogic_vector(0 to 1); + mm_xu_lsu_wimge :in std_ulogic_vector(0 to 4); + mm_xu_lsu_u :in std_ulogic_vector(0 to 3); + mm_xu_lsu_addr :in std_ulogic_vector(64-real_data_add to 63); + mm_xu_lsu_lpid :in std_ulogic_vector(0 to 7); + mm_xu_lsu_lpidr :in std_ulogic_vector(0 to 7); + mm_xu_lsu_gs :in std_ulogic; + mm_xu_lsu_ind :in std_ulogic; + mm_xu_lsu_lbit :in std_ulogic; -- "L" bit, for large vs. small + xu_mm_lsu_token :out std_ulogic; + lsu_xu_ldq_barr_done :out std_ulogic_vector(0 to 3); + lsu_xu_barr_done :out std_ulogic_vector(0 to 3); + + -- Boxes interface + bx_lsu_ob_pwr_tok :in std_ulogic; + bx_lsu_ob_req_val :in std_ulogic; -- message buffer data is ready to send + bx_lsu_ob_ditc_val :in std_ulogic; -- send dtic command + bx_lsu_ob_thrd :in std_ulogic_vector(0 to 1); -- source thread + bx_lsu_ob_qw :in std_ulogic_vector(58 to 59); -- QW address + bx_lsu_ob_dest :in std_ulogic_vector(0 to 14); -- destination for the packet + bx_lsu_ob_data :in std_ulogic_vector(0 to 127); -- 16B of data from the outbox + bx_lsu_ob_addr :in std_ulogic_vector(64-real_data_add to 57); -- address for boxes message + lsu_bx_cmd_avail :out std_ulogic; + lsu_bx_cmd_sent :out std_ulogic; + lsu_bx_cmd_stall :out std_ulogic; + + -- *** Reload operation Outputs *** + ldq_rel_data_val_early :out std_ulogic; + ldq_rel_op_size :out std_ulogic_vector(0 to 5); + ldq_rel_addr :out std_ulogic_vector(64-(dc_size-3) to 58); + ldq_rel_data_val :out std_ulogic; + ldq_rel_rot_sel :out std_ulogic_vector(0 to 4); + ldq_rel_axu_val :out std_ulogic; + ldq_rel_ci :out std_ulogic; + ldq_rel_thrd_id :out std_ulogic_vector(0 to 3); + ldq_rel_le_mode :out std_ulogic; + ldq_rel_algebraic :out std_ulogic; + ldq_rel_256_data :out std_ulogic_vector(0 to 255); + + ldq_rel_dvc1_en :out std_ulogic; + ldq_rel_dvc2_en :out std_ulogic; + ldq_rel_beat_crit_qw :out std_ulogic; + ldq_rel_beat_crit_qw_block :out std_ulogic; + + xu_iu_ex4_loadmiss_qentry :out std_ulogic_vector(0 to lmq_entries-1); + xu_iu_ex4_loadmiss_target :out std_ulogic_vector(0 to 8); + xu_iu_ex4_loadmiss_target_type :out std_ulogic_vector(0 to 1); + xu_iu_ex4_loadmiss_tid :out std_ulogic_vector(0 to 3); + xu_iu_ex5_loadmiss_qentry :out std_ulogic_vector(0 to lmq_entries-1); + xu_iu_ex5_loadmiss_target :out std_ulogic_vector(0 to 8); + xu_iu_ex5_loadmiss_target_type :out std_ulogic_vector(0 to 1); + xu_iu_ex5_loadmiss_tid :out std_ulogic_vector(0 to 3); + xu_iu_complete_qentry :out std_ulogic_vector(0 to lmq_entries-1); + xu_iu_complete_tid :out std_ulogic_vector(0 to 3); + xu_iu_complete_target_type :out std_ulogic_vector(0 to 1); + + -- ICBI Interface + xu_iu_ex6_icbi_val :out std_ulogic_vector(0 to 3); + xu_iu_ex6_icbi_addr :out std_ulogic_vector(64-real_data_add to 57); + + xu_lsu_ex5_set_barr :in std_ulogic_vector(0 to 3); + xu_iu_larx_done_tid :out std_ulogic_vector(0 to 3); + xu_mm_lmq_stq_empty :out std_ulogic; + lsu_xu_quiesce :out std_ulogic_vector(0 to 3); + lsu_xu_dbell_val :out std_ulogic; + lsu_xu_dbell_type :out std_ulogic_vector(0 to 4); + lsu_xu_dbell_brdcast :out std_ulogic; + lsu_xu_dbell_lpid_match :out std_ulogic; + lsu_xu_dbell_pirtag :out std_ulogic_vector(50 to 63); + + ac_an_req_pwr_token :out std_ulogic; + ac_an_req :out std_ulogic; + ac_an_req_ra :out std_ulogic_vector(64-real_data_add to 63); + ac_an_req_ttype :out std_ulogic_vector(0 to 5); + ac_an_req_thread :out std_ulogic_vector(0 to 2); + ac_an_req_wimg_w :out std_ulogic; + ac_an_req_wimg_i :out std_ulogic; + ac_an_req_wimg_m :out std_ulogic; + ac_an_req_wimg_g :out std_ulogic; + ac_an_req_endian :out std_ulogic; + ac_an_req_user_defined :out std_ulogic_vector(0 to 3); + ac_an_req_spare_ctrl_a0 :out std_ulogic_vector(0 to 3); + ac_an_req_ld_core_tag :out std_ulogic_vector(0 to 4); + ac_an_req_ld_xfr_len :out std_ulogic_vector(0 to 2); + ac_an_st_byte_enbl :out std_ulogic_vector(0 to 15+(st_data_32B_mode*16)); + ac_an_st_data :out std_ulogic_vector(0 to 127+(st_data_32B_mode*128)); + ac_an_st_data_pwr_token :out std_ulogic; + + ac_an_reld_ditc_pop_int : in std_ulogic_vector(0 to 3); + ac_an_reld_ditc_pop_q : out std_ulogic_vector(0 to 3); + bx_ib_empty_int : in std_ulogic_vector(0 to 3); + bx_ib_empty_q : out std_ulogic_vector(0 to 3); + + --pervasive + xu_pc_err_dcachedir_parity :out std_ulogic; + xu_pc_err_dcachedir_multihit :out std_ulogic; + xu_pc_err_l2intrf_ecc :out std_ulogic; + xu_pc_err_l2intrf_ue :out std_ulogic; + xu_pc_err_invld_reld :out std_ulogic; + xu_pc_err_l2credit_overrun :out std_ulogic; + pc_xu_init_reset :in std_ulogic; + + -- Performance Counters + pc_xu_event_bus_enable :in std_ulogic; + pc_xu_event_count_mode :in std_ulogic_vector(0 to 2); + pc_xu_lsu_event_mux_ctrls :in std_ulogic_vector(0 to 47); + pc_xu_cache_par_err_event :in std_ulogic; + xu_pc_lsu_event_data :out std_ulogic_vector(0 to 7); + + -- Debug Trace Bus + pc_xu_trace_bus_enable :in std_ulogic; + lsu_debug_mux_ctrls :in std_ulogic_vector(0 to 15); + trigger_data_in :in std_ulogic_vector(0 to 11); + debug_data_in :in std_ulogic_vector(0 to 87); + trigger_data_out :out std_ulogic_vector(0 to 11); + debug_data_out :out std_ulogic_vector(0 to 87); + lsu_xu_cmd_debug :out std_ulogic_vector(0 to 175); + + -- G8T ABIST Control + an_ac_lbist_ary_wrt_thru_dc :in std_ulogic; + pc_xu_abist_g8t_wenb :in std_ulogic; + pc_xu_abist_g8t1p_renb_0 :in std_ulogic; + pc_xu_abist_di_0 :in std_ulogic_vector(0 to 3); + pc_xu_abist_g8t_bw_1 :in std_ulogic; + pc_xu_abist_g8t_bw_0 :in std_ulogic; + pc_xu_abist_waddr_0 :in std_ulogic_vector(5 to 9); + pc_xu_abist_raddr_0 :in std_ulogic_vector(5 to 9); + pc_xu_abist_ena_dc :in std_ulogic; + pc_xu_abist_wl32_comp_ena :in std_ulogic; + pc_xu_abist_raw_dc_b :in std_ulogic; + pc_xu_abist_g8t_dcomp :in std_ulogic_vector(0 to 3); + pc_xu_bo_unload :in std_ulogic; + pc_xu_bo_repair :in std_ulogic; + pc_xu_bo_reset :in std_ulogic; + pc_xu_bo_shdata :in std_ulogic; + pc_xu_bo_select :in std_ulogic_vector(1 to 4); + xu_pc_bo_fail :out std_ulogic_vector(1 to 4); + xu_pc_bo_diagout :out std_ulogic_vector(1 to 4); + + vcs :inout power_logic; + vdd :inout power_logic; + gnd :inout power_logic; + nclk :in clk_logic; + an_ac_grffence_en_dc :in std_ulogic; + an_ac_coreid :in std_ulogic_vector(6 to 7); + pc_xu_ccflush_dc :in std_ulogic; + an_ac_scan_dis_dc_b :in std_ulogic; + an_ac_atpg_en_dc :in std_ulogic; + an_ac_scan_diag_dc :in std_ulogic; + an_ac_lbist_en_dc :in std_ulogic; + clkoff_dc_b :in std_ulogic; + sg_2 :in std_ulogic_vector(2 to 3); + fce_2 :in std_ulogic; + func_sl_thold_2 :in std_ulogic_vector(2 to 3); + func_nsl_thold_2 :in std_ulogic; + func_slp_sl_thold_2 :in std_ulogic; + func_slp_nsl_thold_2 :in std_ulogic; + cfg_slp_sl_thold_2 :in std_ulogic; + regf_slp_sl_thold_2 :in std_ulogic; + abst_slp_sl_thold_2 :in std_ulogic; + time_sl_thold_2 :in std_ulogic; + ary_slp_nsl_thold_2 :in std_ulogic; + repr_sl_thold_2 :in std_ulogic; + bolt_sl_thold_2 :in std_ulogic; + bo_enable_2 :in std_ulogic; + d_mode_dc :in std_ulogic; + delay_lclkr_dc :in std_ulogic_vector(5 to 9); + mpw1_dc_b :in std_ulogic_vector(5 to 9); + mpw2_dc_b :in std_ulogic; + g8t_clkoff_dc_b :in std_ulogic; + g8t_d_mode_dc :in std_ulogic; + g8t_delay_lclkr_dc :in std_ulogic_vector(0 to 4); + g8t_mpw1_dc_b :in std_ulogic_vector(0 to 4); + g8t_mpw2_dc_b :in std_ulogic; + cam_clkoff_dc_b :in std_ulogic; + cam_d_mode_dc :in std_ulogic; + cam_act_dis_dc :in std_ulogic; + cam_delay_lclkr_dc :in std_ulogic_vector(0 to 4); + cam_mpw1_dc_b :in std_ulogic_vector(0 to 4); + cam_mpw2_dc_b :in std_ulogic; + bcfg_scan_in :in std_ulogic; + bcfg_scan_out :out std_ulogic; + ccfg_scan_in :in std_ulogic; + ccfg_scan_out :out std_ulogic; + dcfg_scan_in :in std_ulogic; + dcfg_scan_out :out std_ulogic; + regf_scan_in :in std_ulogic_vector(0 to 6); + regf_scan_out :out std_ulogic_vector(0 to 6); + abst_scan_in :in std_ulogic; + abst_scan_out :out std_ulogic; + time_scan_in :in std_ulogic; + time_scan_out :out std_ulogic; + repr_scan_in :in std_ulogic; + repr_scan_out :out std_ulogic; + func_scan_in :in std_ulogic_vector(41 to 49); + func_scan_out :out std_ulogic_vector(41 to 49) +); +-- synopsys translate_off +-- synopsys translate_on +end xuq_lsu_cmd; +---- +architecture xuq_lsu_cmd of xuq_lsu_cmd is + +constant uprTagBit :natural := 64-real_data_add; +constant lwrTagBit :natural := 63-(dc_size-3); +constant tagSize :natural := lwrTagBit-uprTagBit+1; +constant parExtCalc :natural := 8 - (tagSize mod 8); +constant parBits :natural := (tagSize+parExtCalc) / 8; +constant wayDataSize :natural := tagSize+parBits; + +signal ex3_req_thrd_id :std_ulogic_vector(0 to 3); +signal ex3_l_s_q_val :std_ulogic; +signal ex3_drop_ld_req :std_ulogic; +signal ex3_drop_touch :std_ulogic; +signal ex3_cache_inh :std_ulogic; +signal ex3_load_instr :std_ulogic; +signal ex3_store_instr :std_ulogic; +signal ex3_cache_acc :std_ulogic; +signal ex2_p_addr_lwr :std_ulogic_vector(52 to 57); +signal ex3_p_addr_lwr :std_ulogic_vector(58 to 63); +signal ex3_opsize :std_ulogic_vector(0 to 5); +signal ex3_target_gpr :std_ulogic_vector(0 to 8); +signal ex3_axu_op_val :std_ulogic; +signal ex3_larx_instr :std_ulogic; +signal ex3_mutex_hint :std_ulogic; +signal ex3_stx_instr :std_ulogic; +signal ex3_dcbt_instr :std_ulogic; +signal ex3_dcbf_instr :std_ulogic; +signal ex3_dcbtst_instr :std_ulogic; +signal ex3_dcbst_instr :std_ulogic; +signal ex3_dcbz_instr :std_ulogic; +signal ex3_dcbi_instr :std_ulogic; +signal ex3_icbi_instr :std_ulogic; +signal ex3_icswx_instr :std_ulogic; +signal ex3_icswx_dot :std_ulogic; +signal ex3_icswx_epid :std_ulogic; +signal ex3_sync_instr :std_ulogic; +signal ex3_mtspr_trace :std_ulogic; +signal ex3_byte_en :std_ulogic_vector(0 to 31); +signal ex3_l_fld :std_ulogic_vector(0 to 1); +signal ex3_mbar_instr :std_ulogic; +signal ex3_msgsnd_instr :std_ulogic; +signal ex3_dci_instr :std_ulogic; +signal ex3_ici_instr :std_ulogic; +signal ex3_flush_stg :std_ulogic; +signal ex4_flush_stg :std_ulogic; +signal ex3_algebraic_op :std_ulogic; +signal ex3_dcbtls_instr :std_ulogic; +signal ex3_dcbtstls_instr :std_ulogic; +signal ex3_dcblc_instr :std_ulogic; +signal ex3_icblc_instr :std_ulogic; +signal ex3_icbt_instr :std_ulogic; +signal ex3_icbtls_instr :std_ulogic; +signal ex3_tlbsync_instr :std_ulogic; +signal ex3_local_dcbf :std_ulogic; +signal ex4_drop_rel :std_ulogic; +signal ex3_load_l1hit :std_ulogic; +signal ex3_rotate_sel :std_ulogic_vector(0 to 4); +signal ex3_lock_en :std_ulogic; +signal ex3_th_fld_l2 :std_ulogic; +signal cmp_flush :std_ulogic; +signal cmp_ldq_fnd_b :std_ulogic; +signal cmp_ldq_fnd :std_ulogic; +signal ex1_src0_vld :std_ulogic; +signal ex1_src0_reg :std_ulogic_vector(0 to 7); +signal ex1_src1_vld :std_ulogic; +signal ex1_src1_reg :std_ulogic_vector(0 to 7); +signal ex1_targ_vld :std_ulogic; +signal ex1_targ_reg :std_ulogic_vector(0 to 7); +signal ex1_check_watch :std_ulogic_vector(0 to 3); +signal ex2_lm_dep_hit :std_ulogic; +signal ldq_rel1_val :std_ulogic; +signal ldq_rel1_early_v :std_ulogic; +signal ldq_rel_mid_val :std_ulogic; +signal ldq_rel_retry_val :std_ulogic; +signal ldq_rel3_val :std_ulogic; +signal ldq_rel3_early_v :std_ulogic; +signal ldq_rel_tag :std_ulogic_vector(1 to 3); +signal ldq_rel_tag_early :std_ulogic_vector(1 to 3); +signal ldq_rel_set_val :std_ulogic; +signal ldq_rel_ecc_err :std_ulogic; +signal ldq_rel_classid :std_ulogic_vector(0 to 1); +signal ldq_rel_lock_en :std_ulogic; +signal ldq_rel_watch_en :std_ulogic; +signal rel_ldq_thrd_id :std_ulogic_vector(0 to 3); +signal ldq_rel_ta_gpr :std_ulogic_vector(0 to 8); +signal ldq_rel_addr_early :std_ulogic_vector(64-real_data_add to 63-cl_size); +signal ldq_rel_back_invalidated :std_ulogic; +signal ldq_recirc_rel_val :std_ulogic; +signal ldq_rel_l1dump_cslc :std_ulogic; +signal ldq_rel3_l1dump_val :std_ulogic; +signal rel_ldq_ci :std_ulogic; +signal rel_ldq_upd_gpr :std_ulogic; +signal rel_ldq_addr :std_ulogic_vector(64-real_data_add to 58); +signal rel_ldq_axu_val :std_ulogic; +signal is2_l2_inv_val :std_ulogic; +signal is2_l2_inv_p_addr :std_ulogic_vector(64-real_data_add to 63-cl_size); +signal l2_data_ecc_err_ue :std_ulogic_vector(0 to 3); +signal gpr_ecc_err_flush_tid :std_ulogic_vector(0 to 3); +signal dcpar_err_flush :std_ulogic; +signal ex4_dir_perr_det :std_ulogic_vector(0 to 0); +signal ex4_dir_multihit_det :std_ulogic_vector(0 to 0); +signal ex4_n_lsu_ddmh_flush :std_ulogic_vector(0 to 3); +signal dcachedir_parity :std_ulogic_vector(0 to 0); +signal dcachedir_multihit :std_ulogic_vector(0 to 0); +signal ex3_watch_en :std_ulogic; +signal ex3_ld_queue_full :std_ulogic; +signal ex3_stq_flush :std_ulogic; +signal ex3_ig_flush :std_ulogic; +signal ex3_cClass_collision :std_ulogic; +signal ex3_cClass_collision_b :std_ulogic; +signal derat_xu_ex2_vf :std_ulogic; +signal derat_xu_ex2_miss :std_ulogic_vector(0 to 3); +signal derat_xu_ex2_attr :std_ulogic_vector(0 to 5); +signal derat_xu_ex4_data :std_ulogic_vector(64-(2**REGMODE) to 63); +signal derat_iu_barrier_done :std_ulogic_vector(0 to 3); +signal derat_fir_par_err :std_ulogic_vector(0 to 3); +signal derat_fir_multihit :std_ulogic_vector(0 to 3); +signal xu_derat_epsc_wr :std_ulogic_vector(0 to 3); +signal xu_derat_eplc_wr :std_ulogic_vector(0 to 3); +signal xu_derat_eplc0_epr :std_ulogic; +signal xu_derat_eplc0_eas :std_ulogic; +signal xu_derat_eplc0_egs :std_ulogic; +signal xu_derat_eplc0_elpid :std_ulogic_vector(40 to 47); +signal xu_derat_eplc0_epid :std_ulogic_vector(50 to 63); +signal xu_derat_eplc1_epr :std_ulogic; +signal xu_derat_eplc1_eas :std_ulogic; +signal xu_derat_eplc1_egs :std_ulogic; +signal xu_derat_eplc1_elpid :std_ulogic_vector(40 to 47); +signal xu_derat_eplc1_epid :std_ulogic_vector(50 to 63); +signal xu_derat_eplc2_epr :std_ulogic; +signal xu_derat_eplc2_eas :std_ulogic; +signal xu_derat_eplc2_egs :std_ulogic; +signal xu_derat_eplc2_elpid :std_ulogic_vector(40 to 47); +signal xu_derat_eplc2_epid :std_ulogic_vector(50 to 63); +signal xu_derat_eplc3_epr :std_ulogic; +signal xu_derat_eplc3_eas :std_ulogic; +signal xu_derat_eplc3_egs :std_ulogic; +signal xu_derat_eplc3_elpid :std_ulogic_vector(40 to 47); +signal xu_derat_eplc3_epid :std_ulogic_vector(50 to 63); +signal xu_derat_epsc0_epr :std_ulogic; +signal xu_derat_epsc0_eas :std_ulogic; +signal xu_derat_epsc0_egs :std_ulogic; +signal xu_derat_epsc0_elpid :std_ulogic_vector(40 to 47); +signal xu_derat_epsc0_epid :std_ulogic_vector(50 to 63); +signal xu_derat_epsc1_epr :std_ulogic; +signal xu_derat_epsc1_eas :std_ulogic; +signal xu_derat_epsc1_egs :std_ulogic; +signal xu_derat_epsc1_elpid :std_ulogic_vector(40 to 47); +signal xu_derat_epsc1_epid :std_ulogic_vector(50 to 63); +signal xu_derat_epsc2_epr :std_ulogic; +signal xu_derat_epsc2_eas :std_ulogic; +signal xu_derat_epsc2_egs :std_ulogic; +signal xu_derat_epsc2_elpid :std_ulogic_vector(40 to 47); +signal xu_derat_epsc2_epid :std_ulogic_vector(50 to 63); +signal xu_derat_epsc3_epr :std_ulogic; +signal xu_derat_epsc3_eas :std_ulogic; +signal xu_derat_epsc3_egs :std_ulogic; +signal xu_derat_epsc3_elpid :std_ulogic_vector(40 to 47); +signal xu_derat_epsc3_epid :std_ulogic_vector(50 to 63); +signal derat_xu_ex2_rpn :std_ulogic_vector(22 to 51); -- derat 32x143 update to 42b RA +signal derat_xu_ex2_wimge :std_ulogic_vector(0 to 4); +signal derat_xu_ex2_u :std_ulogic_vector(0 to 3); +signal derat_xu_ex2_wlc :std_ulogic_vector(0 to 1); +signal xu_derat_ex1_epn_arr :std_ulogic_vector(64-(2**regmode) to 51); +signal xu_derat_ex1_epn_nonarr :std_ulogic_vector(64-(2**regmode) to 51); +signal snoop_addr :std_ulogic_vector(64-(2**regmode) to 51); +signal snoop_addr_sel :std_ulogic; +signal lsu_perf_events :std_ulogic_vector(0 to 46); +signal ex1_stg_act :std_ulogic; +signal ex2_stg_act :std_ulogic; +signal ex3_stg_act :std_ulogic; +signal ex4_stg_act :std_ulogic; +signal binv1_stg_act :std_ulogic; +signal binv2_stg_act :std_ulogic; +signal binv2_ex2_stg_act :std_ulogic; +signal lsu_xu_sync_barr_done :std_ulogic_vector(0 to 3); +signal bcfg_scan_out_int :std_ulogic; +signal ccfg_scan_out_int :std_ulogic; +signal dcfg_scan_out_int :std_ulogic; +signal abist_siv :std_ulogic_vector(0 to 23); +signal abist_sov :std_ulogic_vector(0 to 23); +signal rel_data_val :std_ulogic; +signal rel_data_val_early :std_ulogic; +signal dir_arr_rd_addr_01 :std_ulogic_vector(64-(dc_size-3) to 63-cl_size); +signal dir_arr_rd_addr_23 :std_ulogic_vector(64-(dc_size-3) to 63-cl_size); +signal dir_arr_rd_addr_45 :std_ulogic_vector(64-(dc_size-3) to 63-cl_size); +signal dir_arr_rd_addr_67 :std_ulogic_vector(64-(dc_size-3) to 63-cl_size); +signal dir_arr_rd_data :std_ulogic_vector(0 to 8*wayDataSize-1); +signal dir_wr_enable :std_ulogic_vector(0 to 3); +signal dir_wr_way :std_ulogic_vector(0 to 7); +signal dir_arr_wr_addr :std_ulogic_vector(64-(dc_size-3) to 63-cl_size); +signal dir_arr_wr_data :std_ulogic_vector(64-real_data_add to 64-real_data_add+wayDataSize-1); +signal abst_slp_sl_thold_1 :std_ulogic; +signal time_sl_thold_1 :std_ulogic; +signal ary_slp_nsl_thold_1 :std_ulogic; +signal repr_sl_thold_1 :std_ulogic; +signal regf_slp_sl_thold_1 :std_ulogic; +signal func_slp_nsl_thold_1 :std_ulogic; +signal abst_slp_sl_thold_0 :std_ulogic; +signal time_sl_thold_0 :std_ulogic; +signal ary_slp_nsl_thold_0 :std_ulogic; +signal repr_sl_thold_0 :std_ulogic; +signal regf_slp_sl_thold_0 :std_ulogic; +signal func_slp_nsl_thold_0 :std_ulogic; +signal abst_slp_sl_thold_0_b :std_ulogic; +signal abst_slp_sl_force :std_ulogic; +signal abst_scan_in_q :std_ulogic; +signal abst_scan_out_int :std_ulogic; +signal abst_scan_out_q :std_ulogic; +signal time_scan_in_q :std_ulogic; +signal time_scan_out_int :std_ulogic_vector(0 to 1); +signal time_scan_out_q :std_ulogic; +signal repr_scan_in_q :std_ulogic; +signal repr_scan_out_int :std_ulogic; +signal repr_scan_out_q :std_ulogic; +signal func_scan_in_q :std_ulogic_vector(41 to 49); +signal func_scan_out_int :std_ulogic_vector(41 to 49); +signal func_scan_out_q :std_ulogic_vector(41 to 49); +signal regf_scan_in_q :std_ulogic_vector(0 to 6); +signal regf_scan_out_int :std_ulogic_vector(0 to 6); +signal regf_scan_out_q :std_ulogic_vector(0 to 6); +signal derat_scan_out :std_ulogic_vector(0 to 1); +signal dir_scan_out :std_ulogic_vector(0 to 1); +signal cmp_scan_out :std_ulogic; +signal l2cmdq_scan_out :std_ulogic; +signal tidn :std_ulogic; +signal func_slp_sl_thold_1 :std_ulogic; +signal func_sl_thold_1 :std_ulogic; +signal func_nsl_thold_1 :std_ulogic; +signal cfg_slp_sl_thold_1 :std_ulogic; +signal sg_1 :std_ulogic; +signal fce_1 :std_ulogic; +signal bolt_sl_thold_1 :std_ulogic; +signal func_slp_sl_thold_0 :std_ulogic; +signal func_sl_thold_0 :std_ulogic; +signal func_nsl_thold_0 :std_ulogic; +signal cfg_slp_sl_thold_0 :std_ulogic; +signal sg_0 :std_ulogic; +signal fce_0 :std_ulogic; +signal bolt_sl_thold_0 :std_ulogic; +signal func_sl_force :std_ulogic; +signal func_sl_thold_0_b :std_ulogic; +signal func_nsl_force :std_ulogic; +signal func_nsl_thold_0_b :std_ulogic; +signal cfg_slp_sl_force :std_ulogic; +signal cfg_slp_sl_thold_0_b :std_ulogic; +signal func_slp_sl_force :std_ulogic; +signal func_slp_sl_thold_0_b :std_ulogic; +signal func_slp_nsl_force :std_ulogic; +signal func_slp_nsl_thold_0_b :std_ulogic; +signal pc_xu_abist_g8t_wenb_q :std_ulogic; +signal pc_xu_abist_g8t1p_renb_0_q :std_ulogic; +signal pc_xu_abist_di_0_q :std_ulogic_vector(0 to 3); +signal pc_xu_abist_g8t_bw_1_q :std_ulogic; +signal pc_xu_abist_g8t_bw_0_q :std_ulogic; +signal pc_xu_abist_waddr_0_q :std_ulogic_vector(0 to 4); +signal pc_xu_abist_raddr_0_q :std_ulogic_vector(0 to 4); +signal pc_xu_abist_wl32_comp_ena_q :std_ulogic; +signal pc_xu_abist_g8t_dcomp_q :std_ulogic_vector(0 to 3); +signal slat_force :std_ulogic; +signal abst_slat_thold_b :std_ulogic; +signal abst_slat_d2clk :std_ulogic; +signal abst_slat_lclk :clk_logic; +signal time_slat_thold_b :std_ulogic; +signal time_slat_d2clk :std_ulogic; +signal time_slat_lclk :clk_logic; +signal repr_slat_thold_b :std_ulogic; +signal repr_slat_d2clk :std_ulogic; +signal repr_slat_lclk :clk_logic; +signal func_slat_thold_b :std_ulogic; +signal func_slat_d2clk :std_ulogic; +signal func_slat_lclk :clk_logic; +signal regf_slat_thold_b :std_ulogic; +signal regf_slat_d2clk :std_ulogic; +signal regf_slat_lclk :clk_logic; +signal lmq_pe_recov_state :std_ulogic; +signal lmq_dbg_dcache_pe :std_ulogic_vector(1 to 60); +signal lmq_dbg_l2req :std_ulogic_vector(0 to 212); +signal lmq_dbg_rel :std_ulogic_vector(0 to 140); +signal lmq_dbg_binv :std_ulogic_vector(0 to 44); +signal lmq_dbg_pops :std_ulogic_vector(0 to 5); +signal lmq_dbg_grp0 :std_ulogic_vector(0 to 81); +signal lmq_dbg_grp1 :std_ulogic_vector(0 to 81); +signal lmq_dbg_grp2 :std_ulogic_vector(0 to 87); +signal lmq_dbg_grp3 :std_ulogic_vector(0 to 87); +signal lmq_dbg_grp4 :std_ulogic_vector(0 to 87); +signal lmq_dbg_grp5 :std_ulogic_vector(0 to 87); +signal lmq_dbg_grp6 :std_ulogic_vector(0 to 87); + +signal spr_xucr0_cls :std_ulogic; +signal ex3_data_swap_int :std_ulogic; +signal ex3_blkable_touch :std_ulogic; +signal ex7_targ_match :std_ulogic; +signal ex8_targ_match :std_ulogic; +signal ex4_ld_entry :std_ulogic_vector(0 to 67); +signal ex2_wayA_tag :std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); +signal ex2_wayB_tag :std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); +signal ex2_wayC_tag :std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); +signal ex2_wayD_tag :std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); +signal ex2_wayE_tag :std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); +signal ex2_wayF_tag :std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); +signal ex2_wayG_tag :std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); +signal ex2_wayH_tag :std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); +signal ex3_cClass_upd_way_a :std_ulogic; +signal ex3_cClass_upd_way_b :std_ulogic; +signal ex3_cClass_upd_way_c :std_ulogic; +signal ex3_cClass_upd_way_d :std_ulogic; +signal ex3_cClass_upd_way_e :std_ulogic; +signal ex3_cClass_upd_way_f :std_ulogic; +signal ex3_cClass_upd_way_g :std_ulogic; +signal ex3_cClass_upd_way_h :std_ulogic; +signal ex3_way_cmp_a :std_ulogic; +signal ex3_way_cmp_b :std_ulogic; +signal ex3_way_cmp_c :std_ulogic; +signal ex3_way_cmp_d :std_ulogic; +signal ex3_way_cmp_e :std_ulogic; +signal ex3_way_cmp_f :std_ulogic; +signal ex3_way_cmp_g :std_ulogic; +signal ex3_way_cmp_h :std_ulogic; +signal cmp_lmq_entry_act :std_ulogic; -- act for lmq entries +signal cmp_ldq_comp_val :std_ulogic_vector(0 to 7); -- enable compares against lmq +signal cmp_ldq_match :std_ulogic_vector(0 to 7); -- compare result (without enable) +signal cmp_l_q_wrt_en :std_ulogic_vector(0 to 7); -- load entry, (hold when not loading) +signal cmp_ld_ex7_recov :std_ulogic; +signal cmp_ex3_p_addr_o :std_ulogic_vector(22 to 57); +signal cmp_ex7_ld_recov_addr :std_ulogic_vector(64-real_data_add to 57); +signal cmp_ex4_loadmiss_qentry :std_ulogic_vector(0 to 7); -- mux 3 select +signal cmp_ex4_ld_addr :std_ulogic_vector(64-real_data_add to 57); -- mux 3 +signal cmp_l_q_rd_en :std_ulogic_vector(0 to 7); -- mux 2 select +signal cmp_l_miss_entry_addr :std_ulogic_vector(64-real_data_add to 57); -- mux 2 +signal cmp_rel_tag_1hot :std_ulogic_vector(0 to 7); -- mux 1 select +signal cmp_rel_addr :std_ulogic_vector(64-real_data_add to 57); -- mux 1 +signal cmp_back_inv_addr :std_ulogic_vector(64-real_data_add to 57); -- compare to each ldq entry +signal cmp_back_inv_cmp_val :std_ulogic_vector(0 to 7); -- +signal cmp_back_inv_addr_hit :std_ulogic_vector(0 to 7); -- +signal cmp_s_m_queue0_addr :std_ulogic_vector(64-real_data_add to 57); -- +signal cmp_st_entry0_val :std_ulogic ; -- +signal cmp_ex3addr_hit_stq :std_ulogic ; -- +signal cmp_ex4_st_entry_addr :std_ulogic_vector(64-real_data_add to 57); -- +signal cmp_ex4_st_val :std_ulogic ; -- +signal cmp_ex3addr_hit_ex4st :std_ulogic ; -- +signal dir_rd_stg_act :std_ulogic; +signal xu_derat_rf1_binv_val :std_ulogic; +signal derat_xu_ex3_rpn :std_ulogic_vector(64-real_data_add to 51); +signal derat_xu_ex3_wimge :std_ulogic_vector(0 to 4); +signal derat_xu_ex3_u :std_ulogic_vector(0 to 3); +signal derat_xu_ex3_wlc :std_ulogic_vector(0 to 1); +signal derat_xu_ex3_attr :std_ulogic_vector(0 to 5); +signal derat_xu_ex3_vf :std_ulogic; +signal derat_xu_ex3_noop_touch :std_ulogic_vector(0 to 3); +signal dir_arr_rd_is2_val :std_ulogic; +signal dir_arr_rd_congr_cl :std_ulogic_vector(0 to 4); +signal is2_back_inv_addr :std_ulogic_vector(64-real_data_add to 63-cl_size); +signal ex3_wayA_tag :std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); -- Way Tag +signal ex3_wayB_tag :std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); -- Way Tag +signal ex3_wayC_tag :std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); -- Way Tag +signal ex3_wayD_tag :std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); -- Way Tag +signal ex3_wayE_tag :std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); -- Way Tag +signal ex3_wayF_tag :std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); -- Way Tag +signal ex3_wayG_tag :std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); -- Way Tag +signal ex3_wayH_tag :std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); -- Way Tag +signal dc_fgen_dbg_data :std_ulogic_vector(0 to 1); +signal dc_cntrl_dbg_data :std_ulogic_vector(0 to 66); +signal dc_val_dbg_data :std_ulogic_vector(0 to 293); +signal dc_lru_dbg_data :std_ulogic_vector(0 to 81); +signal dc_dir_dbg_data :std_ulogic_vector(0 to 35); +signal dir_arr_dbg_data :std_ulogic_vector(0 to 60); +signal pe_recov_begin :std_ulogic; +signal derat_xu_debug_group0 :std_ulogic_vector(0 to 87); +signal derat_xu_debug_group1 :std_ulogic_vector(0 to 87); + +begin + +tidn <= '0'; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- L1 Data ERAT's +-- Data Erat/uTLB (Memory Management) +-- 1) Contains a Cam of Memory Management Entries +-- 2) Includes an MMU mode and a TLB mode +-- 3) Translates Effective Address to a Real Address +-- 3) Outputs a Real Address, Memory Attribute Bits, and User Defined Bits +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +lsuderat : entity work.xuq_lsu_derat(xuq_lsu_derat) +generic map( expand_type => expand_type, + rs_data_width => (2**regmode), + data_out_width => (2**regmode), + epn_width => (2**regmode)-12, + bcfg_epn_0to15 => bcfg_epn_0to15, + bcfg_epn_16to31 => bcfg_epn_16to31, + bcfg_epn_32to47 => bcfg_epn_32to47, + bcfg_epn_48to51 => bcfg_epn_48to51, + bcfg_rpn_22to31 => bcfg_rpn_22to31, + bcfg_rpn_32to47 => bcfg_rpn_32to47, + bcfg_rpn_48to51 => bcfg_rpn_48to51) +port map( + vdd => vdd, + gnd => gnd, + vcs => vcs, + nclk => nclk, + pc_xu_init_reset => pc_xu_init_reset, + pc_xu_ccflush_dc => pc_xu_ccflush_dc, + tc_scan_dis_dc_b => an_ac_scan_dis_dc_b, + tc_scan_diag_dc => an_ac_scan_diag_dc, + tc_lbist_en_dc => an_ac_lbist_en_dc, + an_ac_atpg_en_dc => an_ac_atpg_en_dc, + an_ac_grffence_en_dc => an_ac_grffence_en_dc, + + lcb_d_mode_dc => d_mode_dc, + lcb_clkoff_dc_b => clkoff_dc_b, + lcb_act_dis_dc => tidn, + lcb_mpw1_dc_b => mpw1_dc_b, + lcb_mpw2_dc_b => mpw2_dc_b, + lcb_delay_lclkr_dc => delay_lclkr_dc, + + pc_func_sl_thold_2 => func_sl_thold_2(2), + pc_func_slp_sl_thold_2 => func_slp_sl_thold_2, + pc_func_slp_nsl_thold_2 => func_slp_nsl_thold_2, + pc_cfg_slp_sl_thold_2 => cfg_slp_sl_thold_2, + pc_regf_slp_sl_thold_2 => regf_slp_sl_thold_2, + pc_time_sl_thold_2 => time_sl_thold_2, + pc_sg_2 => sg_2(2), + pc_fce_2 => fce_2, + + cam_clkoff_dc_b => cam_clkoff_dc_b, + cam_act_dis_dc => cam_act_dis_dc, + cam_d_mode_dc => cam_d_mode_dc, + cam_delay_lclkr_dc => cam_delay_lclkr_dc, + cam_mpw1_dc_b => cam_mpw1_dc_b, + cam_mpw2_dc_b => cam_mpw2_dc_b, + + + ac_func_scan_in => func_scan_in_q(41 to 42), -- use func_scan_in_q(1) for expansion + ac_func_scan_out => derat_scan_out, + ac_ccfg_scan_in => ccfg_scan_in, + ac_ccfg_scan_out => ccfg_scan_out_int, + time_scan_in => time_scan_out_int(0), + time_scan_out => time_scan_out_int(1), + + regf_scan_in => regf_scan_in_q, + regf_scan_out => regf_scan_out_int, + + spr_xucr4_mmu_mchk => spr_xucr4_mmu_mchk, + spr_xucr0_clkg_ctl_b1 => spr_xucr0_clkg_ctl_b1, + xu_derat_rf0_val => xu_lsu_rf0_derat_val, + xu_derat_rf1_act => xu_lsu_rf1_derat_act, + xu_derat_rf1_ra_eq_ea => xu_lsu_rf1_derat_ra_eq_ea, + xu_derat_rf1_is_load => xu_lsu_rf1_derat_is_load, + xu_derat_rf1_is_store => xu_lsu_rf1_derat_is_store, + xu_derat_rf1_is_eratre => xu_lsu_rf1_is_eratre, + xu_derat_rf1_is_eratwe => xu_lsu_rf1_is_eratwe, + xu_derat_rf1_is_eratsx => xu_lsu_rf1_is_eratsx, + xu_derat_rf1_is_eratilx => xu_lsu_rf1_is_eratilx, + xu_derat_ex1_is_isync => xu_lsu_ex1_is_isync, + xu_derat_ex1_is_csync => xu_lsu_ex1_is_csync, + xu_derat_rf1_is_touch => xu_lsu_rf1_is_touch, + xu_derat_rf1_icbtls_instr => xu_lsu_rf1_icbtls_instr, + xu_derat_rf1_icblc_instr => xu_lsu_rf1_icblc_instr, + xu_derat_rf0_is_extload => xu_lsu_rf0_derat_is_extload, + xu_derat_rf0_is_extstore => xu_lsu_rf0_derat_is_extstore, + xu_derat_rf1_ws => xu_lsu_rf1_ws, + xu_derat_rf1_t => xu_lsu_rf1_t, + xu_derat_rf1_binv_val => xu_derat_rf1_binv_val, + xu_derat_ex1_rs_is => xu_lsu_ex1_rs_is, + xu_derat_ex1_ra_entry => xu_lsu_ex1_ra_entry, + xu_derat_ex1_epn_arr => xu_derat_ex1_epn_arr, + xu_derat_ex1_epn_nonarr => xu_derat_ex1_epn_nonarr, + snoop_addr => snoop_addr, + snoop_addr_sel => snoop_addr_sel, + xu_derat_rf0_n_flush => xu_lsu_rf0_flush, + xu_derat_rf1_n_flush => xu_lsu_rf1_flush, + xu_derat_ex1_n_flush => xu_lsu_ex1_flush, + xu_derat_ex2_n_flush => xu_lsu_ex2_flush, + xu_derat_ex3_n_flush => xu_lsu_ex3_flush, + xu_derat_ex4_n_flush => xu_lsu_ex4_flush, + xu_derat_ex5_n_flush => xu_lsu_ex5_flush, + xu_derat_ex4_rs_data => xu_lsu_ex4_rs_data, + xu_derat_msr_hv => xu_lsu_msr_gs, + xu_derat_msr_pr => xu_lsu_msr_pr, + xu_derat_msr_ds => xu_lsu_msr_ds, + xu_derat_msr_cm => xu_lsu_msr_cm, + xu_derat_hid_mmu_mode => xu_lsu_hid_mmu_mode, + xu_derat_spr_ccr2_dfrat => xu_lsu_spr_ccr2_dfrat, + xu_derat_spr_ccr2_dfratsc => xu_lsu_spr_ccr2_dfratsc, + + derat_xu_ex2_miss => derat_xu_ex2_miss, + derat_xu_ex2_rpn => derat_xu_ex2_rpn, + derat_xu_ex2_wimge => derat_xu_ex2_wimge, + derat_xu_ex2_u => derat_xu_ex2_u, + derat_xu_ex2_wlc => derat_xu_ex2_wlc, + derat_xu_ex2_attr => derat_xu_ex2_attr, + derat_xu_ex2_vf => derat_xu_ex2_vf, + + derat_xu_ex3_rpn => derat_xu_ex3_rpn, + derat_xu_ex3_wimge => derat_xu_ex3_wimge, + derat_xu_ex3_u => derat_xu_ex3_u, + derat_xu_ex3_wlc => derat_xu_ex3_wlc, + derat_xu_ex3_attr => derat_xu_ex3_attr, + derat_xu_ex3_vf => derat_xu_ex3_vf, + derat_xu_ex3_miss => derat_xu_ex3_miss, + derat_xu_ex3_dsi => derat_xu_ex3_dsi, + derat_xu_ex3_multihit_err => lsu_xu_ex3_derat_multihit_err, + derat_xu_ex3_noop_touch => derat_xu_ex3_noop_touch, + derat_xu_ex3_par_err => lsu_xu_ex3_derat_par_err, + + derat_xu_ex3_n_flush_req => derat_xu_ex3_n_flush_req, + derat_xu_ex4_data => derat_xu_ex4_data, + derat_xu_ex4_par_err => lsu_xu_ex4_derat_par_err, + derat_iu_barrier_done => derat_iu_barrier_done, + derat_fir_par_err => derat_fir_par_err, + derat_fir_multihit => derat_fir_multihit, + + -- DERAT SlowSPR Regs + xu_derat_epsc_wr => xu_derat_epsc_wr, + xu_derat_eplc_wr => xu_derat_eplc_wr, + xu_derat_eplc0_epr => xu_derat_eplc0_epr, + xu_derat_eplc0_eas => xu_derat_eplc0_eas, + xu_derat_eplc0_egs => xu_derat_eplc0_egs, + xu_derat_eplc0_elpid => xu_derat_eplc0_elpid, + xu_derat_eplc0_epid => xu_derat_eplc0_epid, + xu_derat_eplc1_epr => xu_derat_eplc1_epr, + xu_derat_eplc1_eas => xu_derat_eplc1_eas, + xu_derat_eplc1_egs => xu_derat_eplc1_egs, + xu_derat_eplc1_elpid => xu_derat_eplc1_elpid, + xu_derat_eplc1_epid => xu_derat_eplc1_epid, + xu_derat_eplc2_epr => xu_derat_eplc2_epr, + xu_derat_eplc2_eas => xu_derat_eplc2_eas, + xu_derat_eplc2_egs => xu_derat_eplc2_egs, + xu_derat_eplc2_elpid => xu_derat_eplc2_elpid, + xu_derat_eplc2_epid => xu_derat_eplc2_epid, + xu_derat_eplc3_epr => xu_derat_eplc3_epr, + xu_derat_eplc3_eas => xu_derat_eplc3_eas, + xu_derat_eplc3_egs => xu_derat_eplc3_egs, + xu_derat_eplc3_elpid => xu_derat_eplc3_elpid, + xu_derat_eplc3_epid => xu_derat_eplc3_epid, + xu_derat_epsc0_epr => xu_derat_epsc0_epr, + xu_derat_epsc0_eas => xu_derat_epsc0_eas, + xu_derat_epsc0_egs => xu_derat_epsc0_egs, + xu_derat_epsc0_elpid => xu_derat_epsc0_elpid, + xu_derat_epsc0_epid => xu_derat_epsc0_epid, + xu_derat_epsc1_epr => xu_derat_epsc1_epr, + xu_derat_epsc1_eas => xu_derat_epsc1_eas, + xu_derat_epsc1_egs => xu_derat_epsc1_egs, + xu_derat_epsc1_elpid => xu_derat_epsc1_elpid, + xu_derat_epsc1_epid => xu_derat_epsc1_epid, + xu_derat_epsc2_epr => xu_derat_epsc2_epr, + xu_derat_epsc2_eas => xu_derat_epsc2_eas, + xu_derat_epsc2_egs => xu_derat_epsc2_egs, + xu_derat_epsc2_elpid => xu_derat_epsc2_elpid, + xu_derat_epsc2_epid => xu_derat_epsc2_epid, + xu_derat_epsc3_epr => xu_derat_epsc3_epr, + xu_derat_epsc3_eas => xu_derat_epsc3_eas, + xu_derat_epsc3_egs => xu_derat_epsc3_egs, + xu_derat_epsc3_elpid => xu_derat_epsc3_elpid, + xu_derat_epsc3_epid => xu_derat_epsc3_epid, + + xu_mm_derat_req => xu_mm_derat_req, + xu_mm_derat_thdid => xu_mm_derat_thdid, + xu_mm_derat_state => xu_mm_derat_state, + xu_mm_derat_tid => xu_mm_derat_tid, + xu_mm_derat_ttype => xu_mm_derat_ttype, + xu_mm_derat_lpid => xu_mm_derat_lpid, + + mm_xu_derat_rel_val => mm_xu_derat_rel_val, + mm_xu_derat_rel_data => mm_xu_derat_rel_data, + + mm_xu_derat_pid0 => mm_xu_derat_pid0, + mm_xu_derat_pid1 => mm_xu_derat_pid1, + mm_xu_derat_pid2 => mm_xu_derat_pid2, + mm_xu_derat_pid3 => mm_xu_derat_pid3, + + mm_xu_derat_mmucr0_0 => mm_xu_derat_mmucr0_0, + mm_xu_derat_mmucr0_1 => mm_xu_derat_mmucr0_1, + mm_xu_derat_mmucr0_2 => mm_xu_derat_mmucr0_2, + mm_xu_derat_mmucr0_3 => mm_xu_derat_mmucr0_3, + xu_mm_derat_mmucr0 => xu_mm_derat_mmucr0, + xu_mm_derat_mmucr0_we => xu_mm_derat_mmucr0_we, + mm_xu_derat_mmucr1 => mm_xu_derat_mmucr1, + xu_mm_derat_mmucr1 => xu_mm_derat_mmucr1, + xu_mm_derat_mmucr1_we => xu_mm_derat_mmucr1_we, + + mm_xu_derat_snoop_coming => mm_xu_derat_snoop_coming, + mm_xu_derat_snoop_val => mm_xu_derat_snoop_val, + mm_xu_derat_snoop_attr => mm_xu_derat_snoop_attr, + mm_xu_derat_snoop_vpn => mm_xu_derat_snoop_vpn, + xu_mm_derat_snoop_ack => xu_mm_derat_snoop_ack, + + pc_xu_trace_bus_enable => pc_xu_trace_bus_enable, + derat_xu_debug_group0 => derat_xu_debug_group0, + derat_xu_debug_group1 => derat_xu_debug_group1, + derat_xu_debug_group2 => lsu_xu_cmd_debug(0 to 87), + derat_xu_debug_group3 => lsu_xu_cmd_debug(88 to 175) +); + +lsu_xu_ex4_tlb_data <= derat_xu_ex4_data(64-(2**REGMODE) to 63); + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- L1 Data Directory +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +lsudir : entity work.xuq_lsu_dir(xuq_lsu_dir) +generic map(expand_type => expand_type, + l_endian_m => l_endian_m, + regmode => regmode, + lmq_entries => lmq_entries, + dc_size => dc_size, + cl_size => cl_size, + wayDataSize => wayDataSize, + real_data_add => real_data_add) +port map( + + xu_lsu_rf0_act => xu_lsu_rf0_act, + xu_lsu_rf1_cmd_act => xu_lsu_rf1_cmd_act, + xu_lsu_rf1_axu_op_val => xu_lsu_rf1_axu_op_val, + xu_lsu_rf1_axu_ldst_falign => xu_lsu_rf1_axu_ldst_falign, + xu_lsu_rf1_axu_ldst_fexcpt => xu_lsu_rf1_axu_ldst_fexcpt, + xu_lsu_rf1_cache_acc => xu_lsu_rf1_cache_acc, + xu_lsu_rf1_thrd_id => xu_lsu_rf1_thrd_id, + xu_lsu_rf1_optype1 => xu_lsu_rf1_optype1, + xu_lsu_rf1_optype2 => xu_lsu_rf1_optype2, + xu_lsu_rf1_optype4 => xu_lsu_rf1_optype4, + xu_lsu_rf1_optype8 => xu_lsu_rf1_optype8, + xu_lsu_rf1_optype16 => xu_lsu_rf1_optype16, + xu_lsu_rf1_optype32 => xu_lsu_rf1_optype32, + xu_lsu_rf1_target_gpr => xu_lsu_rf1_target_gpr, + xu_lsu_rf1_mtspr_trace => xu_lsu_rf1_mtspr_trace, + xu_lsu_rf1_load_instr => xu_lsu_rf1_load_instr, + xu_lsu_rf1_store_instr => xu_lsu_rf1_store_instr, + xu_lsu_rf1_dcbf_instr => xu_lsu_rf1_dcbf_instr, + xu_lsu_rf1_sync_instr => xu_lsu_rf1_sync_instr, + xu_lsu_rf1_l_fld => xu_lsu_rf1_l_fld, + xu_lsu_rf1_dcbi_instr => xu_lsu_rf1_dcbi_instr, + xu_lsu_rf1_dcbz_instr => xu_lsu_rf1_dcbz_instr, + xu_lsu_rf1_dcbt_instr => xu_lsu_rf1_dcbt_instr, + xu_lsu_rf1_dcbtst_instr => xu_lsu_rf1_dcbtst_instr, + xu_lsu_rf1_th_fld => xu_lsu_rf1_th_fld, + xu_lsu_rf1_dcbtls_instr => xu_lsu_rf1_dcbtls_instr, + xu_lsu_rf1_dcbtstls_instr => xu_lsu_rf1_dcbtstls_instr, + xu_lsu_rf1_dcblc_instr => xu_lsu_rf1_dcblc_instr, + xu_lsu_rf1_dcbst_instr => xu_lsu_rf1_dcbst_instr, + xu_lsu_rf1_icbi_instr => xu_lsu_rf1_icbi_instr, + xu_lsu_rf1_icblc_instr => xu_lsu_rf1_icblc_instr, + xu_lsu_rf1_icbt_instr => xu_lsu_rf1_icbt_instr, + xu_lsu_rf1_icbtls_instr => xu_lsu_rf1_icbtls_instr, + xu_lsu_rf1_icswx_instr => xu_lsu_rf1_icswx_instr, + xu_lsu_rf1_icswx_dot_instr => xu_lsu_rf1_icswx_dot_instr, + xu_lsu_rf1_icswx_epid => xu_lsu_rf1_icswx_epid, + xu_lsu_rf1_tlbsync_instr => xu_lsu_rf1_tlbsync_instr, + xu_lsu_rf1_ldawx_instr => xu_lsu_rf1_ldawx_instr, + xu_lsu_rf1_wclr_instr => xu_lsu_rf1_wclr_instr, + xu_lsu_rf1_wchk_instr => xu_lsu_rf1_wchk_instr, + xu_lsu_rf1_lock_instr => xu_lsu_rf1_lock_instr, + xu_lsu_rf1_mutex_hint => xu_lsu_rf1_mutex_hint, + xu_lsu_rf1_mbar_instr => xu_lsu_rf1_mbar_instr, + xu_lsu_rf1_is_msgsnd => xu_lsu_rf1_is_msgsnd, + xu_lsu_rf1_dci_instr => xu_lsu_rf1_dci_instr, + xu_lsu_rf1_ici_instr => xu_lsu_rf1_ici_instr, + xu_lsu_rf1_algebraic => xu_lsu_rf1_algebraic, + xu_lsu_rf1_byte_rev => xu_lsu_rf1_byte_rev, + xu_lsu_rf1_src_gpr => xu_lsu_rf1_src_gpr, + xu_lsu_rf1_src_axu => xu_lsu_rf1_src_axu, + xu_lsu_rf1_src_dp => xu_lsu_rf1_src_dp, + xu_lsu_rf1_targ_gpr => xu_lsu_rf1_targ_gpr, + xu_lsu_rf1_targ_axu => xu_lsu_rf1_targ_axu, + xu_lsu_rf1_targ_dp => xu_lsu_rf1_targ_dp, + xu_lsu_ex4_val => xu_lsu_ex4_val, + xu_lsu_ex1_add_src0 => xu_lsu_ex1_add_src0, + xu_lsu_ex1_add_src1 => xu_lsu_ex1_add_src1, + + xu_lsu_rf1_src0_vld => xu_lsu_rf1_src0_vld, + xu_lsu_rf1_src0_reg => xu_lsu_rf1_src0_reg, + xu_lsu_rf1_src1_vld => xu_lsu_rf1_src1_vld, + xu_lsu_rf1_src1_reg => xu_lsu_rf1_src1_reg, + xu_lsu_rf1_targ_vld => xu_lsu_rf1_targ_vld, + xu_lsu_rf1_targ_reg => xu_lsu_rf1_targ_reg, + + -- Error Inject + pc_xu_inj_dcachedir_parity => pc_xu_inj_dcachedir_parity, + pc_xu_inj_dcachedir_multihit => pc_xu_inj_dcachedir_multihit, + + ex3_wimge_w_bit => derat_xu_ex3_wimge(0), + ex3_wimge_i_bit => derat_xu_ex3_wimge(1), + ex3_wimge_e_bit => derat_xu_ex3_wimge(4), + ex3_p_addr => cmp_ex3_p_addr_o(64-real_data_add to 51), + derat_xu_ex3_noop_touch => derat_xu_ex3_noop_touch, + ex3_ld_queue_full => ex3_ld_queue_full, + ex3_stq_flush => ex3_stq_flush, + ex3_ig_flush => ex3_ig_flush, + + ex2_lm_dep_hit => ex2_lm_dep_hit, + + ex3_way_cmp_a => ex3_way_cmp_a, + ex3_way_cmp_b => ex3_way_cmp_b, + ex3_way_cmp_c => ex3_way_cmp_c, + ex3_way_cmp_d => ex3_way_cmp_d, + ex3_way_cmp_e => ex3_way_cmp_e, + ex3_way_cmp_f => ex3_way_cmp_f, + ex3_way_cmp_g => ex3_way_cmp_g, + ex3_way_cmp_h => ex3_way_cmp_h, + + ex3_wayA_tag => ex3_wayA_tag, + ex3_wayB_tag => ex3_wayB_tag, + ex3_wayC_tag => ex3_wayC_tag, + ex3_wayD_tag => ex3_wayD_tag, + ex3_wayE_tag => ex3_wayE_tag, + ex3_wayF_tag => ex3_wayF_tag, + ex3_wayG_tag => ex3_wayG_tag, + ex3_wayH_tag => ex3_wayH_tag, + + xu_lsu_mtspr_trace_en => xu_lsu_mtspr_trace_en, + spr_xucr0_clkg_ctl_b1 => spr_xucr0_clkg_ctl_b1, + xu_lsu_spr_xucr0_aflsta => xu_lsu_spr_xucr0_aflsta, + xu_lsu_spr_xucr0_flsta => xu_lsu_spr_xucr0_flsta, + xu_lsu_spr_xucr0_l2siw => xu_lsu_spr_xucr0_l2siw, + xu_lsu_spr_xucr0_dcdis => xu_lsu_spr_xucr0_dcdis, + xu_lsu_spr_xucr0_wlk => xu_lsu_spr_xucr0_wlk, + xu_lsu_spr_ccr2_dfrat => xu_lsu_spr_ccr2_dfrat, + xu_lsu_spr_xucr0_clfc => xu_lsu_spr_xucr0_clfc, + xu_lsu_spr_xucr0_flh2l2 => xu_lsu_spr_xucr0_flh2l2, + xu_lsu_spr_xucr0_cls => xu_lsu_spr_xucr0_cls, + xu_lsu_spr_msr_cm => xu_lsu_msr_cm, + xu_lsu_msr_gs => xu_lsu_msr_gs, + xu_lsu_msr_pr => xu_lsu_msr_pr, + + an_ac_flh2l2_gate => an_ac_flh2l2_gate, + + ldq_rel1_early_v => ldq_rel1_early_v, + ldq_rel1_val => ldq_rel1_val, + ldq_rel_mid_val => ldq_rel_mid_val, + ldq_rel_retry_val => ldq_rel_retry_val, + ldq_rel3_early_v => ldq_rel3_early_v, + ldq_rel3_val => ldq_rel3_val, + ldq_rel_back_invalidated => ldq_rel_back_invalidated, + ldq_rel_data_val_early => rel_data_val_early, + rel_data_val => rel_data_val, + ldq_rel_tag => ldq_rel_tag, + ldq_rel_tag_early => ldq_rel_tag_early, + ldq_rel_set_val => ldq_rel_set_val, + ldq_rel_ecc_err => ldq_rel_ecc_err, + ldq_rel_classid => ldq_rel_classid, + ldq_rel_lock_en => ldq_rel_lock_en, + ldq_rel_l1dump_cslc => ldq_rel_l1dump_cslc, + ldq_rel3_l1dump_val => ldq_rel3_l1dump_val, + ldq_rel_watch_en => ldq_rel_watch_en, + ldq_rel_addr => rel_ldq_addr(64-real_data_add to 52), + ldq_rel_addr_early => ldq_rel_addr_early, + ldq_rel_axu_val => rel_ldq_axu_val, + ldq_rel_thrd_id => rel_ldq_thrd_id, + ldq_rel_ta_gpr => ldq_rel_ta_gpr, + ldq_rel_upd_gpr => rel_ldq_upd_gpr, + ldq_rel_ci => rel_ldq_ci, + ldq_recirc_rel_val => ldq_recirc_rel_val, + + xu_lsu_dci => xu_lsu_dci, + + is2_l2_inv_val => is2_l2_inv_val, + + ex6_ld_par_err => ex6_ld_par_err, + + xu_lsu_rf1_flush => xu_lsu_rf1_flush, + xu_lsu_ex1_flush => xu_lsu_ex1_flush, + xu_lsu_ex2_flush => xu_lsu_ex2_flush, + xu_lsu_ex3_flush => xu_lsu_ex3_flush, + xu_lsu_ex4_flush => xu_lsu_ex4_flush, + xu_lsu_ex5_flush => xu_lsu_ex5_flush, + + xu_lsu_slowspr_val => xu_lsu_slowspr_val, + xu_lsu_slowspr_rw => xu_lsu_slowspr_rw, + xu_lsu_slowspr_etid => xu_lsu_slowspr_etid, + xu_lsu_slowspr_addr => xu_lsu_slowspr_addr, + xu_lsu_slowspr_data => xu_lsu_slowspr_data, + xu_lsu_slowspr_done => xu_lsu_slowspr_done, + slowspr_val_out => slowspr_val_out, + slowspr_rw_out => slowspr_rw_out, + slowspr_etid_out => slowspr_etid_out, + slowspr_addr_out => slowspr_addr_out, + slowspr_data_out => slowspr_data_out, + slowspr_done_out => slowspr_done_out, + + dir_arr_rd_addr_01 => dir_arr_rd_addr_01, + dir_arr_rd_addr_23 => dir_arr_rd_addr_23, + dir_arr_rd_addr_45 => dir_arr_rd_addr_45, + dir_arr_rd_addr_67 => dir_arr_rd_addr_67, + dir_arr_rd_data => dir_arr_rd_data, + + dir_wr_enable => dir_wr_enable, + dir_wr_way => dir_wr_way, + dir_arr_wr_addr => dir_arr_wr_addr, + dir_arr_wr_data => dir_arr_wr_data, + + ex1_src0_vld => ex1_src0_vld, + ex1_src0_reg => ex1_src0_reg, + ex1_src1_vld => ex1_src1_vld, + ex1_src1_reg => ex1_src1_reg, + ex1_targ_vld => ex1_targ_vld, + ex1_targ_reg => ex1_targ_reg, + ex1_check_watch => ex1_check_watch, + + xu_derat_ex1_epn_arr => xu_derat_ex1_epn_arr, + xu_derat_ex1_epn_nonarr => xu_derat_ex1_epn_nonarr, + snoop_addr => snoop_addr, + snoop_addr_sel => snoop_addr_sel, + xu_derat_rf1_binv_val => xu_derat_rf1_binv_val, + ex3_cache_acc => ex3_cache_acc, + ex1_optype1 => ex1_optype1, + ex1_optype2 => ex1_optype2, + ex1_optype4 => ex1_optype4, + ex1_optype8 => ex1_optype8, + ex1_optype16 => ex1_optype16, + ex1_optype32 => ex1_optype32, + ex1_saxu_instr => ex1_saxu_instr, + ex1_sdp_instr => ex1_sdp_instr, + ex1_stgpr_instr => ex1_stgpr_instr, + ex1_store_instr => ex1_store_instr, + ex1_axu_op_val => ex1_axu_op_val, + + lsu_xu_ex3_align => lsu_xu_ex3_align, + lsu_xu_ex3_dsi => lsu_xu_ex3_dsi, + lsu_xu_ex3_inval_align_2ucode => lsu_xu_ex3_inval_align_2ucode, + + ex3_stg_flush => ex3_flush_stg, + ex4_stg_flush => ex4_flush_stg, + lsu_xu_ex3_n_flush_req => lsu_xu_ex3_n_flush_req, + lsu_xu_ex4_ldq_full_flush => lsu_xu_ex4_ldq_full_flush, + lsu_xu_ex3_dep_flush => lsu_xu_ex3_dep_flush, + + ex2_p_addr_lwr => ex2_p_addr_lwr, + ex3_p_addr_lwr => ex3_p_addr_lwr, + ex3_req_thrd_id => ex3_req_thrd_id, + ex3_target_gpr => ex3_target_gpr, + ex3_dcbt_instr => ex3_dcbt_instr, + ex3_dcbtst_instr => ex3_dcbtst_instr, + ex3_th_fld_l2 => ex3_th_fld_l2, + ex3_dcbst_instr => ex3_dcbst_instr, + ex3_dcbf_instr => ex3_dcbf_instr, + ex3_sync_instr => ex3_sync_instr, + ex3_mtspr_trace => ex3_mtspr_trace, + ex3_byte_en => ex3_byte_en, + ex3_l_fld => ex3_l_fld, + ex3_dcbi_instr => ex3_dcbi_instr, + ex3_dcbz_instr => ex3_dcbz_instr, + ex3_icbi_instr => ex3_icbi_instr, + ex3_icswx_instr => ex3_icswx_instr, + ex3_icswx_dot => ex3_icswx_dot, + ex3_icswx_epid => ex3_icswx_epid, + ex3_mbar_instr => ex3_mbar_instr, + ex3_msgsnd_instr => ex3_msgsnd_instr, + ex3_dci_instr => ex3_dci_instr, + ex3_ici_instr => ex3_ici_instr, + ex3_load_instr => ex3_load_instr, + ex3_store_instr => ex3_store_instr, + ex3_axu_op_val => ex3_axu_op_val, + ex3_algebraic => ex3_algebraic_op, + ex3_dcbtls_instr => ex3_dcbtls_instr, + ex3_dcbtstls_instr => ex3_dcbtstls_instr, + ex3_dcblc_instr => ex3_dcblc_instr, + ex3_icblc_instr => ex3_icblc_instr, + ex3_icbt_instr => ex3_icbt_instr, + ex3_icbtls_instr => ex3_icbtls_instr, + ex3_tlbsync_instr => ex3_tlbsync_instr, + ex3_local_dcbf => ex3_local_dcbf, + ex3_lock_en => ex3_lock_en, + ex4_drop_rel => ex4_drop_rel, + ex3_load_l1hit => ex3_load_l1hit, + ex3_rotate_sel => ex3_rotate_sel, + ex3_watch_en => ex3_watch_en, + ex3_data_swap => ex3_data_swap_int, + ex3_blkable_touch => ex3_blkable_touch, + ex7_targ_match => ex7_targ_match, + ex8_targ_match => ex8_targ_match, + ex4_ld_entry => ex4_ld_entry, + + ex3_cache_inh => ex3_cache_inh, + ex3_l_s_q_val => ex3_l_s_q_val, + ex3_drop_ld_req => ex3_drop_ld_req, + ex3_drop_touch => ex3_drop_touch, + ex3_stx_instr => ex3_stx_instr, + ex3_larx_instr => ex3_larx_instr, + ex3_mutex_hint => ex3_mutex_hint, + ex3_opsize => ex3_opsize, + ex4_dir_perr_det => ex4_dir_perr_det(0), + ex4_dir_multihit_det => ex4_dir_multihit_det(0), + ex4_n_lsu_ddmh_flush => ex4_n_lsu_ddmh_flush, + + dcpar_err_flush => dcpar_err_flush, + pe_recov_begin => pe_recov_begin, + + lsu_xu_ex3_ddir_par_err => lsu_xu_ex3_ddir_par_err, + ex3_cClass_collision => ex3_cClass_collision, + + ex3_cClass_upd_way_a => ex3_cClass_upd_way_a, + ex3_cClass_upd_way_b => ex3_cClass_upd_way_b, + ex3_cClass_upd_way_c => ex3_cClass_upd_way_c, + ex3_cClass_upd_way_d => ex3_cClass_upd_way_d, + ex3_cClass_upd_way_e => ex3_cClass_upd_way_e, + ex3_cClass_upd_way_f => ex3_cClass_upd_way_f, + ex3_cClass_upd_way_g => ex3_cClass_upd_way_g, + ex3_cClass_upd_way_h => ex3_cClass_upd_way_h, + + -- Directory Read Data + ex2_wayA_tag => ex2_wayA_tag, + ex2_wayB_tag => ex2_wayB_tag, + ex2_wayC_tag => ex2_wayC_tag, + ex2_wayD_tag => ex2_wayD_tag, + ex2_wayE_tag => ex2_wayE_tag, + ex2_wayF_tag => ex2_wayF_tag, + ex2_wayG_tag => ex2_wayG_tag, + ex2_wayH_tag => ex2_wayH_tag, + + -- Update Data Array Valid + rel_upd_dcarr_val => rel_upd_dcarr_val, + + lsu_xu_ex4_cr_upd => lsu_xu_ex4_cr_upd, + lsu_xu_ex5_cr_rslt => lsu_xu_ex5_cr_rslt, + lsu_xu_ex5_wren => lsu_xu_ex5_wren, + lsu_xu_rel_wren => lsu_xu_rel_wren, + lsu_xu_rel_ta_gpr => lsu_xu_rel_ta_gpr, + lsu_xu_perf_events => lsu_perf_events(0 to 37), + lsu_xu_need_hole => lsu_xu_need_hole, + xu_fu_ex5_reload_val => xu_fu_ex5_reload_val, + xu_fu_ex5_load_val => xu_fu_ex5_load_val, + xu_fu_ex5_load_tag => xu_fu_ex5_load_tag, + + -- ICBI Interface + xu_iu_ex6_icbi_val => xu_iu_ex6_icbi_val, + xu_iu_ex6_icbi_addr => xu_iu_ex6_icbi_addr, + + dcarr_up_way_addr => dcarr_up_way_addr, + + -- DERAT SlowSPR Regs + xu_derat_epsc_wr => xu_derat_epsc_wr, + xu_derat_eplc_wr => xu_derat_eplc_wr, + xu_derat_eplc0_epr => xu_derat_eplc0_epr, + xu_derat_eplc0_eas => xu_derat_eplc0_eas, + xu_derat_eplc0_egs => xu_derat_eplc0_egs, + xu_derat_eplc0_elpid => xu_derat_eplc0_elpid, + xu_derat_eplc0_epid => xu_derat_eplc0_epid, + xu_derat_eplc1_epr => xu_derat_eplc1_epr, + xu_derat_eplc1_eas => xu_derat_eplc1_eas, + xu_derat_eplc1_egs => xu_derat_eplc1_egs, + xu_derat_eplc1_elpid => xu_derat_eplc1_elpid, + xu_derat_eplc1_epid => xu_derat_eplc1_epid, + xu_derat_eplc2_epr => xu_derat_eplc2_epr, + xu_derat_eplc2_eas => xu_derat_eplc2_eas, + xu_derat_eplc2_egs => xu_derat_eplc2_egs, + xu_derat_eplc2_elpid => xu_derat_eplc2_elpid, + xu_derat_eplc2_epid => xu_derat_eplc2_epid, + xu_derat_eplc3_epr => xu_derat_eplc3_epr, + xu_derat_eplc3_eas => xu_derat_eplc3_eas, + xu_derat_eplc3_egs => xu_derat_eplc3_egs, + xu_derat_eplc3_elpid => xu_derat_eplc3_elpid, + xu_derat_eplc3_epid => xu_derat_eplc3_epid, + xu_derat_epsc0_epr => xu_derat_epsc0_epr, + xu_derat_epsc0_eas => xu_derat_epsc0_eas, + xu_derat_epsc0_egs => xu_derat_epsc0_egs, + xu_derat_epsc0_elpid => xu_derat_epsc0_elpid, + xu_derat_epsc0_epid => xu_derat_epsc0_epid, + xu_derat_epsc1_epr => xu_derat_epsc1_epr, + xu_derat_epsc1_eas => xu_derat_epsc1_eas, + xu_derat_epsc1_egs => xu_derat_epsc1_egs, + xu_derat_epsc1_elpid => xu_derat_epsc1_elpid, + xu_derat_epsc1_epid => xu_derat_epsc1_epid, + xu_derat_epsc2_epr => xu_derat_epsc2_epr, + xu_derat_epsc2_eas => xu_derat_epsc2_eas, + xu_derat_epsc2_egs => xu_derat_epsc2_egs, + xu_derat_epsc2_elpid => xu_derat_epsc2_elpid, + xu_derat_epsc2_epid => xu_derat_epsc2_epid, + xu_derat_epsc3_epr => xu_derat_epsc3_epr, + xu_derat_epsc3_eas => xu_derat_epsc3_eas, + xu_derat_epsc3_egs => xu_derat_epsc3_egs, + xu_derat_epsc3_elpid => xu_derat_epsc3_elpid, + xu_derat_epsc3_epid => xu_derat_epsc3_epid, + + -- ACT signals + ex1_stg_act => ex1_stg_act, + ex2_stg_act => ex2_stg_act, + ex3_stg_act => ex3_stg_act, + ex4_stg_act => ex4_stg_act, + binv1_stg_act => binv1_stg_act, + binv2_stg_act => binv2_stg_act, + + -- SPR status + lsu_xu_spr_xucr0_cslc_xuop => lsu_xu_spr_xucr0_cslc_xuop, + lsu_xu_spr_xucr0_cslc_binv => lsu_xu_spr_xucr0_cslc_binv, + lsu_xu_spr_xucr0_clo => lsu_xu_spr_xucr0_clo, + lsu_xu_spr_xucr0_cul => lsu_xu_spr_xucr0_cul, + spr_xucr0_cls => spr_xucr0_cls, + + -- Directory Read interface + dir_arr_rd_is2_val => dir_arr_rd_is2_val, + dir_arr_rd_congr_cl => dir_arr_rd_congr_cl, + + ex4_load_op_hit => ex4_load_op_hit, + ex4_store_hit => ex4_store_hit, + ex4_axu_op_val => ex4_axu_op_val, + spr_dvc1_act => spr_dvc1_act, + spr_dvc2_act => spr_dvc2_act, + spr_dvc1_dbg => spr_dvc1_dbg, + spr_dvc2_dbg => spr_dvc2_dbg, + + -- Debug Data + pc_xu_trace_bus_enable => pc_xu_trace_bus_enable, + dc_fgen_dbg_data => dc_fgen_dbg_data, + dc_cntrl_dbg_data => dc_cntrl_dbg_data, + dc_val_dbg_data => dc_val_dbg_data, + dc_lru_dbg_data => dc_lru_dbg_data, + dc_dir_dbg_data => dc_dir_dbg_data, + dir_arr_dbg_data => dir_arr_dbg_data, + + vdd => vdd, + gnd => gnd, + nclk => nclk, + sg_0 => sg_0, + func_sl_thold_0_b => func_sl_thold_0_b, + func_sl_force => func_sl_force, + func_slp_sl_thold_0_b => func_slp_sl_thold_0_b, + func_slp_sl_force => func_slp_sl_force, + func_nsl_thold_0_b => func_nsl_thold_0_b, + func_nsl_force => func_nsl_force, + func_slp_nsl_thold_0_b => func_slp_nsl_thold_0_b, + func_slp_nsl_force => func_slp_nsl_force, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc(5), + mpw1_dc_b => mpw1_dc_b(5), + mpw2_dc_b => mpw2_dc_b, + scan_in => func_scan_in_q(43 to 46), -- use func_scan_in_q(4 to 5) for expansion + scan_out(0 to 1) => func_scan_out_int(43 to 44), + scan_out(2 to 3) => dir_scan_out +); + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Address Compares +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +binv2_ex2_stg_act <= binv2_stg_act or ex2_stg_act; + + lsucmp: entity work.xuq_lsu_cmp(xuq_lsu_cmp) +generic map(expand_type => expand_type) + port map( + vdd => vdd ,--b--@--xuq_lsu_cmp(lsucmp) + gnd => gnd ,--b--@--xuq_lsu_cmp(lsucmp) + nclk => nclk ,--i--@--xuq_lsu_cmp(lsucmp) + --------- seperate perv for sections located large distance apart ---------------------------------- + delay_lclkr (0) => delay_lclkr_dc(5) ,--i--@--xuq_lsu_cmp(lsucmp) for ERAT + delay_lclkr (1) => delay_lclkr_dc(5) ,--i--@--xuq_lsu_cmp(lsucmp) for DIR + delay_lclkr (2) => delay_lclkr_dc(5) ,--i--@--xuq_lsu_cmp(lsucmp) for LoadQ + mpw1_b (0) => mpw1_dc_b(5) ,--i--@--xuq_lsu_cmp(lsucmp) for ERAT + mpw1_b (1) => mpw1_dc_b(5) ,--i--@--xuq_lsu_cmp(lsucmp) for DIR + mpw1_b (2) => mpw1_dc_b(5) ,--i--@--xuq_lsu_cmp(lsucmp) for LoadQ + mpw2_b (0) => mpw2_dc_b ,--i--@--xuq_lsu_cmp(lsucmp) for ERAT + mpw2_b (1) => mpw2_dc_b ,--i--@--xuq_lsu_cmp(lsucmp) for DIR + mpw2_b (2) => mpw2_dc_b ,--i--@--xuq_lsu_cmp(lsucmp) for LoadQ + forcee (0) => func_slp_sl_force ,--i--@--xuq_lsu_cmp(lsucmp) for ERAT + forcee (1) => func_slp_sl_force ,--i--@--xuq_lsu_cmp(lsucmp) for DIR + forcee (2) => func_sl_force ,--i--@--xuq_lsu_cmp(lsucmp) for LoadQ + sg_0 (0) => sg_0 ,--i--@--xuq_lsu_cmp(lsucmp) for ERAT + sg_0 (1) => sg_0 ,--i--@--xuq_lsu_cmp(lsucmp) for DIR + sg_0 (2) => sg_0 ,--i--@--xuq_lsu_cmp(lsucmp) for LoadQ + thold_0_b (0) => func_slp_sl_thold_0_b ,--i--@--xuq_lsu_cmp(lsucmp) for ERAT + thold_0_b (1) => func_slp_sl_thold_0_b ,--i--@--xuq_lsu_cmp(lsucmp) for DIR + thold_0_b (2) => func_sl_thold_0_b ,--i--@--xuq_lsu_cmp(lsucmp) for LoadQ + scan_in (0) => derat_scan_out(0) ,--i--@--xuq_lsu_cmp(lsucmp) for ERAT + scan_in (1) => dir_scan_out(1) ,--i--@--xuq_lsu_cmp(lsucmp) for DIR + scan_in (2) => l2cmdq_scan_out ,--i--@--xuq_lsu_cmp(lsucmp) for LoadQ + scan_out (0) => func_scan_out_int(41) ,--o--@--xuq_lsu_cmp(lsucmp) for ERAT (36) latches + scan_out (1) => cmp_scan_out ,--o--@--xuq_lsu_cmp(lsucmp) for DIR (30 * 8) latches + scan_out (2) => func_scan_out_int(47) ,--o--@--xuq_lsu_cmp(lsucmp) for LoadQ (36 * 8) latches + ------------------------------------------------------------------------- + enable_lsb_lmq_b => spr_xucr0_cls, + enable_lsb_oth_b => spr_xucr0_cls, + enable_lsb_bi_b => spr_xucr0_cls, + ex2_erat_act => binv2_ex2_stg_act ,--i--@--xuq_lsu_cmp(lsucmp) for LoadQ (6) latches + binv2_ex2_stg_act => binv2_ex2_stg_act ,--i--@--xuq_lsu_cmp(lsucmp) for LoadQ (36 * 8) latches + lmq_entry_act => cmp_lmq_entry_act ,--i--@--xuq_lsu_cmp(lsucmp) for LoadQ (36 * 8) latches + ex3_p_addr => derat_xu_ex3_rpn ,--i--@--xuq_lsu_cmp(lsucmp) + ex2_p_addr_lwr => ex2_p_addr_lwr(52 to 57) ,--i--@--xuq_lsu_cmp(lsucmp) + ex3_p_addr_o => cmp_ex3_p_addr_o(22 to 57) ,--i--@--xuq_lsu_cmp(lsucmp) + ex2_wayA_tag(22 to 52) => ex2_wayA_tag(22 to 52) ,--i--@--xuq_lsu_cmp(lsucmp) + ex2_wayB_tag(22 to 52) => ex2_wayB_tag(22 to 52) ,--i--@--xuq_lsu_cmp(lsucmp) + ex2_wayC_tag(22 to 52) => ex2_wayC_tag(22 to 52) ,--i--@--xuq_lsu_cmp(lsucmp) + ex2_wayD_tag(22 to 52) => ex2_wayD_tag(22 to 52) ,--i--@--xuq_lsu_cmp(lsucmp) + ex2_wayE_tag(22 to 52) => ex2_wayE_tag(22 to 52) ,--i--@--xuq_lsu_cmp(lsucmp) + ex2_wayF_tag(22 to 52) => ex2_wayF_tag(22 to 52) ,--i--@--xuq_lsu_cmp(lsucmp) + ex2_wayG_tag(22 to 52) => ex2_wayG_tag(22 to 52) ,--i--@--xuq_lsu_cmp(lsucmp) + ex2_wayH_tag(22 to 52) => ex2_wayH_tag(22 to 52) ,--i--@--xuq_lsu_cmp(lsucmp) + ex3_cClass_upd_way_a => ex3_cClass_upd_way_a ,--i--@--xuq_lsu_cmp(lsucmp) + ex3_cClass_upd_way_b => ex3_cClass_upd_way_b ,--i--@--xuq_lsu_cmp(lsucmp) + ex3_cClass_upd_way_c => ex3_cClass_upd_way_c ,--i--@--xuq_lsu_cmp(lsucmp) + ex3_cClass_upd_way_d => ex3_cClass_upd_way_d ,--i--@--xuq_lsu_cmp(lsucmp) + ex3_cClass_upd_way_e => ex3_cClass_upd_way_e ,--i--@--xuq_lsu_cmp(lsucmp) + ex3_cClass_upd_way_f => ex3_cClass_upd_way_f ,--i--@--xuq_lsu_cmp(lsucmp) + ex3_cClass_upd_way_g => ex3_cClass_upd_way_g ,--i--@--xuq_lsu_cmp(lsucmp) + ex3_cClass_upd_way_h => ex3_cClass_upd_way_h ,--i--@--xuq_lsu_cmp(lsucmp) + ex3_way_cmp_a => ex3_way_cmp_a ,--o--@--xuq_lsu_cmp(lsucmp) + ex3_way_cmp_b => ex3_way_cmp_b ,--o--@--xuq_lsu_cmp(lsucmp) + ex3_way_cmp_c => ex3_way_cmp_c ,--o--@--xuq_lsu_cmp(lsucmp) + ex3_way_cmp_d => ex3_way_cmp_d ,--o--@--xuq_lsu_cmp(lsucmp) + ex3_way_cmp_e => ex3_way_cmp_e ,--o--@--xuq_lsu_cmp(lsucmp) + ex3_way_cmp_f => ex3_way_cmp_f ,--o--@--xuq_lsu_cmp(lsucmp) + ex3_way_cmp_g => ex3_way_cmp_g ,--o--@--xuq_lsu_cmp(lsucmp) + ex3_way_cmp_h => ex3_way_cmp_h ,--o--@--xuq_lsu_cmp(lsucmp) + ex3_wayA_tag => ex3_wayA_tag, + ex3_wayB_tag => ex3_wayB_tag, + ex3_wayC_tag => ex3_wayC_tag, + ex3_wayD_tag => ex3_wayD_tag, + ex3_wayE_tag => ex3_wayE_tag, + ex3_wayF_tag => ex3_wayF_tag, + ex3_wayG_tag => ex3_wayG_tag, + ex3_wayH_tag => ex3_wayH_tag, + + ldq_comp_val(0 to 7) => cmp_ldq_comp_val(0 to 7) ,--i--@--xuq_lsu_cmp(lsucmp) + ldq_match(0 to 7) => cmp_ldq_match(0 to 7) ,--o--@--xuq_lsu_cmp(lsucmp) + ldq_fnd_b => cmp_ldq_fnd_b ,--o--@--xuq_lsu_cmp(lsucmp) + cmp_flush => cmp_flush ,--o--@--xuq_lsu_cmp(lsucmp) + dir_eq_v_or_b => ex3_cClass_collision_b ,--o--@--xuq_lsu_cmp(lsucmp) + l_q_wrt_en(0 to 7) => cmp_l_q_wrt_en(0 to 7) ,--i--@--xuq_lsu_cmp(lsucmp) + ld_ex7_recov => cmp_ld_ex7_recov , + ex7_ld_recov_addr => cmp_ex7_ld_recov_addr , + ex4_loadmiss_qentry(0 to 7) => cmp_ex4_loadmiss_qentry(0 to 7) ,--i--@--xuq_lsu_cmp(lsucmp) + ex4_ld_addr(22 to 57) => cmp_ex4_ld_addr(22 to 57) ,--o--@--xuq_lsu_cmp(lsucmp) + l_q_rd_en(0 to 7) => cmp_l_q_rd_en(0 to 7) ,--i--@--xuq_lsu_cmp(lsucmp) + l_miss_entry_addr(22 to 57) => cmp_l_miss_entry_addr(22 to 57) ,--o--@--xuq_lsu_cmp(lsucmp) + rel_tag_1hot(0 to 7) => cmp_rel_tag_1hot(0 to 7) ,--i--@--xuq_lsu_cmp(lsucmp) + rel_addr => cmp_rel_addr ,--o--@--xuq_lsu_cmp(lsucmp) + back_inv_addr => cmp_back_inv_addr ,--i--@--xuq_lsu_cmp(lsucmp) + back_inv_cmp_val(0 to 7) => cmp_back_inv_cmp_val(0 to 7) ,--i--@--xuq_lsu_cmp(lsucmp) + back_inv_addr_hit(0 to 7) => cmp_back_inv_addr_hit(0 to 7) ,--o--@--xuq_lsu_cmp(lsucmp) + s_m_queue0_addr(22 to 57) => cmp_s_m_queue0_addr(22 to 57) ,--i--@--xuq_lsu_cmp(lsucmp) + st_entry0_val => cmp_st_entry0_val ,--i--@--xuq_lsu_cmp(lsucmp) + ex3addr_hit_stq => cmp_ex3addr_hit_stq ,--o--@--xuq_lsu_cmp(lsucmp) + ex4_st_entry_addr(22 to 57) => cmp_ex4_st_entry_addr(22 to 57) ,--i--@--xuq_lsu_cmp(lsucmp) + ex4_st_val => cmp_ex4_st_val ,--i--@--xuq_lsu_cmp(lsucmp) + ex3addr_hit_ex4st => cmp_ex3addr_hit_ex4st --o--@--xuq_lsu_cmp(lsucmp) +); + +cmp_ldq_fnd <= not cmp_ldq_fnd_b; +ex3_cClass_collision <= not ex3_cClass_collision_b; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Data Cache Directory Array +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +dir_rd_stg_act <= ex1_stg_act or binv1_stg_act; + +dc16Kdir64B : if (2**dc_size) = 16384 and (2**cl_size) = 64 generate begin + tridirarr: entity tri.tri_32x35_8w_1r1w(tri_32x35_8w_1r1w) + GENERIC MAP (addressable_ports => 32, -- number of addressable register in this array + addressbus_width => 5, -- width of the bus to address all ports (2^portadrbus_width >= addressable_ports) + port_bitwidth => wayDataSize, -- bitwidth of ports + ways => 8, -- number of ways + expand_type => expand_type) -- 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) + PORT MAP( + -- POWER PINS + vcs => vcs, + vdd => vdd, + gnd => gnd, + + -- CLOCK AND CLOCKCONTROL PORTS + nclk => nclk, + rd0_act => dir_rd_stg_act, + sg_0 => sg_0, + ary_slp_nsl_thold_0 => ary_slp_nsl_thold_0, + abst_slp_sl_thold_0 => abst_slp_sl_thold_0, + time_sl_thold_0 => time_sl_thold_0, + repr_sl_thold_0 => repr_sl_thold_0, + clkoff_dc_b => g8t_clkoff_dc_b, + ccflush_dc => pc_xu_ccflush_dc, + scan_dis_dc_b => an_ac_scan_dis_dc_b, + scan_diag_dc => an_ac_scan_diag_dc, + d_mode_dc => g8t_d_mode_dc, + mpw1_dc_b => g8t_mpw1_dc_b, + mpw2_dc_b => g8t_mpw2_dc_b, + delay_lclkr_dc => g8t_delay_lclkr_dc, + + -- ABIST + wr_abst_act => pc_xu_abist_g8t_wenb_q, + rd0_abst_act => pc_xu_abist_g8t1p_renb_0_q, + abist_di => pc_xu_abist_di_0_q, + abist_bw_odd => pc_xu_abist_g8t_bw_1_q, + abist_bw_even => pc_xu_abist_g8t_bw_0_q, + abist_wr_adr => pc_xu_abist_waddr_0_q, + abist_rd0_adr => pc_xu_abist_raddr_0_q, + tc_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc, + abist_ena_1 => pc_xu_abist_ena_dc, + abist_g8t_rd0_comp_ena => pc_xu_abist_wl32_comp_ena_q, + abist_raw_dc_b => pc_xu_abist_raw_dc_b, + obs0_abist_cmp => pc_xu_abist_g8t_dcomp_q, + + -- SCAN PORTS + abst_scan_in => abist_siv(0), + time_scan_in => time_scan_in_q, + repr_scan_in => repr_scan_in_q, + abst_scan_out => abist_sov(0), + time_scan_out => time_scan_out_int(0), + repr_scan_out => repr_scan_out_int, + + -- BOLT-ON + lcb_bolt_sl_thold_0 => bolt_sl_thold_0, + pc_bo_enable_2 => bo_enable_2, + pc_bo_reset => pc_xu_bo_reset, + pc_bo_unload => pc_xu_bo_unload, + pc_bo_repair => pc_xu_bo_repair, + pc_bo_shdata => pc_xu_bo_shdata, + pc_bo_select => pc_xu_bo_select, + bo_pc_failout => xu_pc_bo_fail, + bo_pc_diagloop => xu_pc_bo_diagout, + tri_lcb_mpw1_dc_b => mpw1_dc_b(5), + tri_lcb_mpw2_dc_b => mpw2_dc_b, + tri_lcb_delay_lclkr_dc => delay_lclkr_dc(5), + tri_lcb_clkoff_dc_b => clkoff_dc_b, + tri_lcb_act_dis_dc => tidn, + + -- PORTS + write_enable => dir_wr_enable, + way => dir_wr_way, + addr_wr => dir_arr_wr_addr, + data_in => dir_arr_wr_data, + -- Read Ports + addr_rd_01 => dir_arr_rd_addr_01, + addr_rd_23 => dir_arr_rd_addr_23, + addr_rd_45 => dir_arr_rd_addr_45, + addr_rd_67 => dir_arr_rd_addr_67, + data_out => dir_arr_rd_data + ); +end generate dc16Kdir64B; + +dc32Kdir64B : if (2**dc_size) = 32768 and (2**cl_size) = 64 generate begin + tridirarr: entity tri.tri_32x35_8w_1r1w(tri_32x35_8w_1r1w) + GENERIC MAP (addressable_ports => 64, -- number of addressable register in this array + addressbus_width => 6, -- width of the bus to address all ports (2^portadrbus_width >= addressable_ports) + port_bitwidth => wayDataSize, -- bitwidth of ports + ways => 8, -- number of ways + expand_type => expand_type) -- 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) + PORT MAP( + -- POWER PINS + vcs => vcs, + vdd => vdd, + gnd => gnd, + + -- CLOCK AND CLOCKCONTROL PORTS + nclk => nclk, + rd0_act => dir_rd_stg_act, + sg_0 => sg_0, + ary_slp_nsl_thold_0 => ary_slp_nsl_thold_0, + abst_slp_sl_thold_0 => abst_slp_sl_thold_0, + time_sl_thold_0 => time_sl_thold_0, + repr_sl_thold_0 => repr_sl_thold_0, + clkoff_dc_b => g8t_clkoff_dc_b, + ccflush_dc => pc_xu_ccflush_dc, + scan_dis_dc_b => an_ac_scan_dis_dc_b, + scan_diag_dc => an_ac_scan_diag_dc, + d_mode_dc => g8t_d_mode_dc, + mpw1_dc_b => g8t_mpw1_dc_b, + mpw2_dc_b => g8t_mpw2_dc_b, + delay_lclkr_dc => g8t_delay_lclkr_dc, + + -- ABIST + wr_abst_act => pc_xu_abist_g8t_wenb_q, + rd0_abst_act => pc_xu_abist_g8t1p_renb_0_q, + abist_di => pc_xu_abist_di_0_q, + abist_bw_odd => pc_xu_abist_g8t_bw_1_q, + abist_bw_even => pc_xu_abist_g8t_bw_0_q, + abist_wr_adr => pc_xu_abist_waddr_0_q, + abist_rd0_adr => pc_xu_abist_raddr_0_q, + tc_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc, + abist_ena_1 => pc_xu_abist_ena_dc, + abist_g8t_rd0_comp_ena => pc_xu_abist_wl32_comp_ena_q, + abist_raw_dc_b => pc_xu_abist_raw_dc_b, + obs0_abist_cmp => pc_xu_abist_g8t_dcomp_q, + + -- SCAN PORTS + abst_scan_in => abist_siv(0), + time_scan_in => time_scan_in_q, + repr_scan_in => repr_scan_in_q, + abst_scan_out => abist_sov(0), + time_scan_out => time_scan_out_int(0), + repr_scan_out => repr_scan_out_int, + + -- BOLT-ON + lcb_bolt_sl_thold_0 => bolt_sl_thold_0, + pc_bo_enable_2 => bo_enable_2, + pc_bo_reset => pc_xu_bo_reset, + pc_bo_unload => pc_xu_bo_unload, + pc_bo_repair => pc_xu_bo_repair, + pc_bo_shdata => pc_xu_bo_shdata, + pc_bo_select => pc_xu_bo_select, + bo_pc_failout => xu_pc_bo_fail, + bo_pc_diagloop => xu_pc_bo_diagout, + tri_lcb_mpw1_dc_b => mpw1_dc_b(5), + tri_lcb_mpw2_dc_b => mpw2_dc_b, + tri_lcb_delay_lclkr_dc => delay_lclkr_dc(5), + tri_lcb_clkoff_dc_b => clkoff_dc_b, + tri_lcb_act_dis_dc => tidn, + + -- PORTS + write_enable => dir_wr_enable, + way => dir_wr_way, + addr_wr => dir_arr_wr_addr, + data_in => dir_arr_wr_data, + -- Read Ports + addr_rd_01 => dir_arr_rd_addr_01, + addr_rd_23 => dir_arr_rd_addr_23, + addr_rd_45 => dir_arr_rd_addr_45, + addr_rd_67 => dir_arr_rd_addr_67, + data_out => dir_arr_rd_data + ); +end generate dc32Kdir64B; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Load/Store Q +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +-- LWARX +-- 1) Treated as a Load +-- 2) Should bypass the L1D$ and not load from the L1D$ +-- 3) If hit in the L1 D$, L1 D$ should invalidate locally +-- 4) Should Reload into the L1D$ +-- 5) Should update GPR when data is returned + +-- STWCX +-- 1) Treated as a Store +-- 2) STWCX should bypass the L1D$ and not write to the L1D$ +-- 3) If hit in the L1 D$, L1D$ should invalidate locally + +-- DCBZ +-- 1) Treated as a Store +-- 2) Needs to Invalidate the L1 D$ if hit +-- 3) L2 will zero out the data in L2 Cache + +-- DCBT +-- 1) Treated as a load +-- 2) Use the load command type +-- 3) Should Reload into the L1D$ +-- 4) GPR should not be updated + +-- DCBTST +-- 1) Treated as a load +-- 2) Acts like DCBT, but L2 behaves differently +-- 3) Use a DCBTST command type +-- 4) Should Reload into the L1D$ +-- 5) GPR should not be updated + +-- DCBF(l=0,1,2) +-- 1) If hit in the L1 D$, L1 D$ should invalidate locally +-- 2) l=0 => global dcbf, sent to the L2, L2 broadcasts to all cores if found in L2 +-- a) Treated as a Store +-- b) Should not return data +-- 3) l=1 => local dcbf, FLush Cores L1, send to the L2, L2 does not back-invalidate other cores +-- a) Treated as a Store +-- b) Should not return data +-- 4) l=2 => local dcbf, not sent to the L2 + +-- DCBST +-- 1) Treated as a Store +-- 2) Dont do anything in the L1 D$, just send it down +-- 3) L2 will not back invalidate any cores + +-- ICBI +-- 1) Treated as a Store +-- 2) Prism L2 treats it as a noop, Corona L2 will back-invalidate I$ + +-- PTE Update +-- 1) Treated as a Store +-- 2) Comes from the MMU + +-- HW_SYNC (SYNC L=0) +-- 1) Treated as a Store +-- 2) will come down the pipe, if there is a outstanding load for that thread, +-- should flush sync hold flush until all the outstanding loads have returned +-- 3) L2 will send ACK back to IU + +-- LW_SYNC (SYNC L=1) +-- 1) Treated as a Store +-- 2) will come down the pipe, if there is a outstanding load for that thread, +-- should flush sync and hold flush until all the outstanding loads have returned +-- 3) L2 will not send ACK back to IU, LD/STQ will ACK once sent to L2 + +-- EIEIO +-- 1) Treated as a Store +-- 2) will come down the pipe, if there is a outstanding load for that thread, +-- should flush eieio and hold flush until all the outstanding loads have returned +-- 3) L2 will not send ACK back to IU, LD/STQ will ACK once sent to L2 + +-- PTE_SYNC (SYNC L=2) +-- 1) Treated as a Store +-- 2) will act like a HW_SYNC +-- 3) L2 will acknowledge the PTE_SYNC + +-- I=1 Load +-- 1) there can be many oustanding I=1 loads per thread if G=0 +-- 2) need to flush other I=1 G=1 loads for that thread if one is outstanding in the loadmiss queue with I=1 G=1 +-- 3) need to flush any command that hits the loadmiss queue and its an I=1 load + +-- Signals that need to be driven +-- rel_type | ldq_rel_val | ldq_rel_data_val | ldq_rel_upd_gpr +-- -------------|-------------|------------------|----------------- +-- dcbt/dcbtst | X | X | +-- ci_load | | | X +-- ce_load | X | X | X +-- lwarx | X | X | X + +l2cmdq : entity work.xuq_lsu_l2cmdq(xuq_lsu_l2cmdq) +generic map(expand_type => expand_type, + lmq_entries => lmq_entries, + dc_size => dc_size, + cl_size => cl_size, + real_data_add => real_data_add, + a2mode => a2mode, + load_credits => load_credits, + store_credits => store_credits, + st_data_32B_mode => st_data_32B_mode) +PORT map( + -- Load Miss/Store Operation Signals + ex3_thrd_id => ex3_req_thrd_id, + ex3_l_s_q_val => ex3_l_s_q_val, + ex3_drop_ld_req => ex3_drop_ld_req, + ex3_drop_touch => ex3_drop_touch, + ex3_cache_inh => ex3_cache_inh, + ex3_load_instr => ex3_load_instr, + ex3_store_instr => ex3_store_instr, + ex3_cache_acc => ex3_cache_acc, + ex3_p_addr_lwr => ex3_p_addr_lwr(58 to 63), + ex3_opsize => ex3_opsize, + ex3_rot_sel => ex3_rotate_sel, + ex3_byte_en => ex3_byte_en, + ex4_256st_data => ex4_256st_data, + ex3_target_gpr => ex3_target_gpr, + ex3_axu_op_val => ex3_axu_op_val, + ex3_le_mode => ex3_data_swap_int, + ex3_larx_instr => ex3_larx_instr, + ex3_mutex_hint => ex3_mutex_hint, + ex3_stx_instr => ex3_stx_instr, + ex3_dcbt_instr => ex3_dcbt_instr, + ex3_dcbf_instr => ex3_dcbf_instr, + ex3_dcbtst_instr => ex3_dcbtst_instr, + ex3_dcbst_instr => ex3_dcbst_instr, + ex3_dcbz_instr => ex3_dcbz_instr, + ex3_dcbi_instr => ex3_dcbi_instr, + ex3_icbi_instr => ex3_icbi_instr, + ex3_sync_instr => ex3_sync_instr, + ex3_mtspr_trace => ex3_mtspr_trace, + ex3_l_fld => ex3_l_fld, + ex3_mbar_instr => ex3_mbar_instr, + ex3_wimge_bits => derat_xu_ex3_wimge, + ex3_usr_bits => derat_xu_ex3_u, + ex3_stg_flush => ex3_flush_stg, + ex4_stg_flush => ex4_flush_stg, + xu_lsu_ex5_flush => xu_lsu_ex5_flush, + ex3_byp_l1 => '0', + ex3_algebraic => ex3_algebraic_op, + xu_lsu_ex4_dvc1_en => xu_lsu_ex4_dvc1_en, + xu_lsu_ex4_dvc2_en => xu_lsu_ex4_dvc2_en, + ex3_dcbtls_instr => ex3_dcbtls_instr, + ex3_dcbtstls_instr => ex3_dcbtstls_instr, + ex3_dcblc_instr => ex3_dcblc_instr, + ex3_dci_instr => ex3_dci_instr, + ex3_ici_instr => ex3_ici_instr, + ex3_icblc_instr => ex3_icblc_instr, + ex3_icbt_instr => ex3_icbt_instr, + ex3_icbtls_instr => ex3_icbtls_instr, + ex3_tlbsync_instr => ex3_tlbsync_instr, + ex3_local_dcbf => ex3_local_dcbf, + ex3_icswx_instr => ex3_icswx_instr, + ex3_icswx_dot => ex3_icswx_dot, + ex3_icswx_epid => ex3_icswx_epid, + ex3_classid => derat_xu_ex3_wlc, + ex3_lock_en => ex3_lock_en, + ex3_th_fld_l2 => ex3_th_fld_l2, + ex4_drop_rel => ex4_drop_rel, + ex3_load_l1hit => ex3_load_l1hit, + ex3_msgsnd_instr => ex3_msgsnd_instr, + ex3_watch_en => ex3_watch_en, + ex3_stg_act => ex3_stg_act, + ex4_stg_act => ex4_stg_act, + ex7_targ_match => ex7_targ_match, + ex8_targ_match => ex8_targ_match, + ex4_ld_entry => ex4_ld_entry, + + xu_lsu_ex5_set_barr => xu_lsu_ex5_set_barr, + + -- Dependency Checking on loadmisses + ex1_src0_vld => ex1_src0_vld, + ex1_src0_reg => ex1_src0_reg, + ex1_src1_vld => ex1_src1_vld, + ex1_src1_reg => ex1_src1_reg, + ex1_targ_vld => ex1_targ_vld, + ex1_targ_reg => ex1_targ_reg, + ex1_check_watch => ex1_check_watch, + ex2_lm_dep_hit => ex2_lm_dep_hit, + + -- load cmd in ex6 had a parity error, need to clear load in ex4 + ex6_ld_par_err => ex6_ld_par_err, + pe_recov_begin => pe_recov_begin, + + -- inputs from L2 + an_ac_req_ld_pop => an_ac_req_ld_pop, + an_ac_req_st_pop => an_ac_req_st_pop, + an_ac_req_st_gather => an_ac_req_st_gather, + an_ac_req_st_pop_thrd => an_ac_req_st_pop_thrd, + + an_ac_reld_data_val => an_ac_reld_data_val, + an_ac_reld_core_tag => an_ac_reld_core_tag, + an_ac_reld_qw => an_ac_reld_qw, + an_ac_reld_data => an_ac_reld_data, + an_ac_reld_ecc_err => an_ac_reld_ecc_err, + an_ac_reld_ecc_err_ue => an_ac_reld_ecc_err_ue, + an_ac_reld_data_coming => an_ac_reld_data_coming, + an_ac_reld_ditc => an_ac_reld_ditc, + an_ac_reld_crit_qw => an_ac_reld_crit_qw, + an_ac_reld_l1_dump => an_ac_reld_l1_dump, + + an_ac_back_inv => an_ac_back_inv, + an_ac_back_inv_addr => an_ac_back_inv_addr, + an_ac_back_inv_target_bit1 => an_ac_back_inv_target_bit1, + an_ac_back_inv_target_bit4 => an_ac_back_inv_target_bit4, + an_ac_req_spare_ctrl_a1 => an_ac_req_spare_ctrl_a1, + + an_ac_stcx_complete => an_ac_stcx_complete, + xu_iu_stcx_complete => xu_iu_stcx_complete, + xu_iu_reld_core_tag_clone => xu_iu_reld_core_tag_clone, + xu_iu_reld_data_coming_clone => xu_iu_reld_data_coming_clone, + xu_iu_reld_data_vld_clone => xu_iu_reld_data_vld_clone, + xu_iu_reld_ditc_clone => xu_iu_reld_ditc_clone, + + lsu_reld_data_vld => lsu_reld_data_vld, + lsu_reld_core_tag => lsu_reld_core_tag, + lsu_reld_qw => lsu_reld_qw , + lsu_reld_ecc_err => lsu_reld_ecc_err, + lsu_reld_ditc => lsu_reld_ditc, + lsu_reld_data => lsu_reld_data, + lsu_req_st_pop => lsu_req_st_pop, + lsu_req_st_pop_thrd => lsu_req_st_pop_thrd, + + -- Instruction Fetches + -- Instruction Fetch real address + i_x_ra => i_x_ra, + i_x_request => i_x_request, + i_x_wimge => i_x_wimge, + i_x_thread => i_x_thread, + i_x_userdef => i_x_userdef, + + mm_xu_lsu_req => mm_xu_lsu_req, + mm_xu_lsu_ttype => mm_xu_lsu_ttype, + mm_xu_lsu_wimge => mm_xu_lsu_wimge, + mm_xu_lsu_u => mm_xu_lsu_u, + mm_xu_lsu_addr => mm_xu_lsu_addr, + mm_xu_lsu_lpid => mm_xu_lsu_lpid, + mm_xu_lsu_lpidr => mm_xu_lsu_lpidr, + mm_xu_lsu_gs => mm_xu_lsu_gs , + mm_xu_lsu_ind => mm_xu_lsu_ind , + mm_xu_lsu_lbit => mm_xu_lsu_lbit, + + spr_xucr0_clkg_ctl_b3 => spr_xucr0_clkg_ctl_b3, + xu_lsu_spr_xucr0_rel => xu_lsu_spr_xucr0_rel, + xu_lsu_spr_xucr0_l2siw => xu_lsu_spr_xucr0_l2siw, + xu_lsu_spr_xucr0_cred => xu_lsu_spr_xucr0_cred, + xu_lsu_spr_xucr0_mbar_ack => xu_lsu_spr_xucr0_mbar_ack, + xu_lsu_spr_xucr0_tlbsync => xu_lsu_spr_xucr0_tlbsync, + xu_lsu_spr_xucr0_cls => xu_lsu_spr_xucr0_cls, + xu_mm_lsu_token => xu_mm_lsu_token, + lsu_xu_ldq_barr_done => lsu_xu_ldq_barr_done, + lsu_xu_sync_barr_done => lsu_xu_sync_barr_done, + + mm_xu_derat_pid0 => mm_xu_derat_pid0, + mm_xu_derat_pid1 => mm_xu_derat_pid1, + mm_xu_derat_pid2 => mm_xu_derat_pid2, + mm_xu_derat_pid3 => mm_xu_derat_pid3, + xu_lsu_msr_gs => xu_lsu_msr_gs, + xu_lsu_msr_pr => xu_lsu_msr_pr, + xu_lsu_msr_ds => xu_lsu_msr_ds, + xu_derat_epsc0_epr => xu_derat_epsc0_epr, + xu_derat_epsc0_eas => xu_derat_epsc0_eas, + xu_derat_epsc0_egs => xu_derat_epsc0_egs, + xu_derat_epsc0_elpid => xu_derat_epsc0_elpid, + xu_derat_epsc0_epid => xu_derat_epsc0_epid, + xu_derat_epsc1_epr => xu_derat_epsc1_epr, + xu_derat_epsc1_eas => xu_derat_epsc1_eas, + xu_derat_epsc1_egs => xu_derat_epsc1_egs, + xu_derat_epsc1_elpid => xu_derat_epsc1_elpid, + xu_derat_epsc1_epid => xu_derat_epsc1_epid, + xu_derat_epsc2_epr => xu_derat_epsc2_epr, + xu_derat_epsc2_eas => xu_derat_epsc2_eas, + xu_derat_epsc2_egs => xu_derat_epsc2_egs, + xu_derat_epsc2_elpid => xu_derat_epsc2_elpid, + xu_derat_epsc2_epid => xu_derat_epsc2_epid, + xu_derat_epsc3_epr => xu_derat_epsc3_epr, + xu_derat_epsc3_eas => xu_derat_epsc3_eas, + xu_derat_epsc3_egs => xu_derat_epsc3_egs, + xu_derat_epsc3_elpid => xu_derat_epsc3_elpid, + xu_derat_epsc3_epid => xu_derat_epsc3_epid, + + bx_lsu_ob_pwr_tok => bx_lsu_ob_pwr_tok , + bx_lsu_ob_req_val => bx_lsu_ob_req_val , + bx_lsu_ob_ditc_val => bx_lsu_ob_ditc_val , + bx_lsu_ob_thrd => bx_lsu_ob_thrd , + bx_lsu_ob_qw => bx_lsu_ob_qw , + bx_lsu_ob_dest => bx_lsu_ob_dest , + bx_lsu_ob_data => bx_lsu_ob_data , + bx_lsu_ob_addr => bx_lsu_ob_addr , + lsu_bx_cmd_avail => lsu_bx_cmd_avail , + lsu_bx_cmd_sent => lsu_bx_cmd_sent , + lsu_bx_cmd_stall => lsu_bx_cmd_stall , + + -- *** Reload operation Outputs *** + ldq_rel_op_size => ldq_rel_op_size, + ldq_rel_thrd_id => rel_ldq_thrd_id, + ldq_rel_addr => rel_ldq_addr, + ldq_rel_addr_early => ldq_rel_addr_early, + ldq_rel_data_val => rel_data_val, + ldq_rel_data_val_early => rel_data_val_early, + ldq_rel_tag => ldq_rel_tag, + ldq_rel_tag_early => ldq_rel_tag_early, + ldq_rel1_val => ldq_rel1_val, + ldq_rel1_early_v => ldq_rel1_early_v, + ldq_rel_mid_val => ldq_rel_mid_val, + ldq_rel_retry_val => ldq_rel_retry_val, + ldq_rel3_val => ldq_rel3_val, + ldq_rel3_early_v => ldq_rel3_early_v, + ldq_rel_ta_gpr => ldq_rel_ta_gpr, + ldq_rel_rot_sel => ldq_rel_rot_sel, + ldq_rel_axu_val => rel_ldq_axu_val, + ldq_rel_upd_gpr => rel_ldq_upd_gpr, + ldq_rel_le_mode => ldq_rel_le_mode, + ldq_rel_algebraic => ldq_rel_algebraic, + ldq_rel_set_val => ldq_rel_set_val, + ldq_rel_ecc_err => ldq_rel_ecc_err, + ldq_rel_256_data => ldq_rel_256_data, + ldq_rel_classid => ldq_rel_classid, + ldq_rel_lock_en => ldq_rel_lock_en, + ldq_rel_ci => rel_ldq_ci, + ldq_rel_dvc1_en => ldq_rel_dvc1_en, + ldq_rel_dvc2_en => ldq_rel_dvc2_en, + ldq_rel_watch_en => ldq_rel_watch_en, + ldq_rel_back_invalidated => ldq_rel_back_invalidated, + ldq_recirc_rel_val => ldq_recirc_rel_val, + ldq_rel_beat_crit_qw => ldq_rel_beat_crit_qw, + ldq_rel_beat_crit_qw_block => ldq_rel_beat_crit_qw_block, + + l1dump_cslc => ldq_rel_l1dump_cslc, + ldq_rel3_l1dump_val => ldq_rel3_l1dump_val, + + -- Back invalidate signals going to D-Cache + is2_l2_inv_val => is2_l2_inv_val, + is2_l2_inv_p_addr => is2_l2_inv_p_addr, + + -- Flush Signals and signals going to dependency + ex3_ld_queue_full => ex3_ld_queue_full, + ex3_stq_flush => ex3_stq_flush, + ex3_ig_flush => ex3_ig_flush, + gpr_ecc_err_flush_tid => gpr_ecc_err_flush_tid, + + xu_iu_ex4_loadmiss_qentry => xu_iu_ex4_loadmiss_qentry, + xu_iu_ex4_loadmiss_target => xu_iu_ex4_loadmiss_target, + xu_iu_ex4_loadmiss_target_type => xu_iu_ex4_loadmiss_target_type, + xu_iu_ex4_loadmiss_tid => xu_iu_ex4_loadmiss_tid, + xu_iu_ex5_loadmiss_qentry => xu_iu_ex5_loadmiss_qentry, + xu_iu_ex5_loadmiss_target => xu_iu_ex5_loadmiss_target, + xu_iu_ex5_loadmiss_target_type => xu_iu_ex5_loadmiss_target_type, + xu_iu_ex5_loadmiss_tid => xu_iu_ex5_loadmiss_tid, + xu_iu_complete_qentry => xu_iu_complete_qentry, + xu_iu_complete_tid => xu_iu_complete_tid, + xu_iu_complete_target_type => xu_iu_complete_target_type, + + xu_iu_larx_done_tid => xu_iu_larx_done_tid, + xu_mm_lmq_stq_empty => xu_mm_lmq_stq_empty, + lsu_xu_quiesce => lsu_xu_quiesce, + lsu_xu_dbell_val => lsu_xu_dbell_val, + lsu_xu_dbell_type => lsu_xu_dbell_type, + lsu_xu_dbell_brdcast => lsu_xu_dbell_brdcast, + lsu_xu_dbell_lpid_match => lsu_xu_dbell_lpid_match, + lsu_xu_dbell_pirtag => lsu_xu_dbell_pirtag, + + ac_an_req_pwr_token => ac_an_req_pwr_token, + ac_an_req => ac_an_req, + ac_an_req_ra => ac_an_req_ra, + ac_an_req_ttype => ac_an_req_ttype, + ac_an_req_thread => ac_an_req_thread, + ac_an_req_wimg_w => ac_an_req_wimg_w, + ac_an_req_wimg_i => ac_an_req_wimg_i, + ac_an_req_wimg_m => ac_an_req_wimg_m, + ac_an_req_wimg_g => ac_an_req_wimg_g, + ac_an_req_endian => ac_an_req_endian, + ac_an_req_user_defined => ac_an_req_user_defined, + ac_an_req_spare_ctrl_a0 => ac_an_req_spare_ctrl_a0, + ac_an_req_ld_core_tag => ac_an_req_ld_core_tag, + ac_an_req_ld_xfr_len => ac_an_req_ld_xfr_len, + ac_an_st_byte_enbl => ac_an_st_byte_enbl, + ac_an_st_data => ac_an_st_data, + ac_an_st_data_pwr_token => ac_an_st_data_pwr_token, + + cmp_lmq_entry_act => cmp_lmq_entry_act , + cmp_ex3_p_addr_o => cmp_ex3_p_addr_o , + cmp_ldq_comp_val => cmp_ldq_comp_val , + cmp_ldq_match => cmp_ldq_match , + cmp_ldq_fnd => cmp_ldq_fnd , + cmp_l_q_wrt_en => cmp_l_q_wrt_en , + cmp_ld_ex7_recov => cmp_ld_ex7_recov , + cmp_ex7_ld_recov_addr => cmp_ex7_ld_recov_addr , + cmp_ex4_loadmiss_qentry => cmp_ex4_loadmiss_qentry, + cmp_ex4_ld_addr => cmp_ex4_ld_addr , + cmp_l_q_rd_en => cmp_l_q_rd_en , + cmp_l_miss_entry_addr => cmp_l_miss_entry_addr , + cmp_rel_tag_1hot => cmp_rel_tag_1hot , + cmp_rel_addr => cmp_rel_addr , + cmp_back_inv_addr => cmp_back_inv_addr , + cmp_back_inv_cmp_val => cmp_back_inv_cmp_val , + cmp_back_inv_addr_hit => cmp_back_inv_addr_hit , + cmp_s_m_queue0_addr => cmp_s_m_queue0_addr , + cmp_st_entry0_val => cmp_st_entry0_val , + cmp_ex3addr_hit_stq => cmp_ex3addr_hit_stq , + cmp_ex4_st_entry_addr => cmp_ex4_st_entry_addr , + cmp_ex4_st_val => cmp_ex4_st_val , + cmp_ex3addr_hit_ex4st => cmp_ex3addr_hit_ex4st , + + l2_data_ecc_err_ue => l2_data_ecc_err_ue, + xu_pc_err_l2intrf_ecc => xu_pc_err_l2intrf_ecc, + xu_pc_err_l2intrf_ue => xu_pc_err_l2intrf_ue, + xu_pc_err_invld_reld => xu_pc_err_invld_reld, + xu_pc_err_l2credit_overrun => xu_pc_err_l2credit_overrun, + an_ac_coreid => an_ac_coreid, + lsu_xu_perf_events => lsu_perf_events(38 to 46), + + -- latch and redrive for BXQ + ac_an_reld_ditc_pop_int => ac_an_reld_ditc_pop_int, + ac_an_reld_ditc_pop_q => ac_an_reld_ditc_pop_q , + bx_ib_empty_int => bx_ib_empty_int , + bx_ib_empty_q => bx_ib_empty_q , + + lmq_pe_recov_state => lmq_pe_recov_state, + lmq_dbg_dcache_pe => lmq_dbg_dcache_pe, + lmq_dbg_l2req => lmq_dbg_l2req, + lmq_dbg_rel => lmq_dbg_rel , + lmq_dbg_binv => lmq_dbg_binv, + lmq_dbg_pops => lmq_dbg_pops, + lmq_dbg_grp0 => lmq_dbg_grp0, + lmq_dbg_grp1 => lmq_dbg_grp1, + lmq_dbg_grp2 => lmq_dbg_grp2, + lmq_dbg_grp3 => lmq_dbg_grp3, + lmq_dbg_grp4 => lmq_dbg_grp4, + lmq_dbg_grp5 => lmq_dbg_grp5, + lmq_dbg_grp6 => lmq_dbg_grp6, + + vdd => vdd, + gnd => gnd, + nclk => nclk, + sg_0 => sg_0, + func_sl_thold_0_b => func_sl_thold_0_b, + func_sl_force => func_sl_force, + func_slp_sl_thold_0_b => func_slp_sl_thold_0_b, + func_slp_sl_force => func_slp_sl_force, + cfg_slp_sl_thold_0_b => cfg_slp_sl_thold_0_b, + cfg_slp_sl_force => cfg_slp_sl_force, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc(5), + mpw1_dc_b => mpw1_dc_b(5), + mpw2_dc_b => mpw2_dc_b, + scan_dis_dc_b => an_ac_scan_dis_dc_b, + bcfg_scan_in => bcfg_scan_in, + bcfg_scan_out => bcfg_scan_out_int, + scan_in => func_scan_in_q(47 to 49), + scan_out(0) => l2cmdq_scan_out, + scan_out(1 to 2) => func_scan_out_int(48 to 49) +); + +-- Mux Between Directory Read and Back-Invalidate +is2_back_inv_addr(64-real_data_add to 52) <= is2_l2_inv_p_addr(64-real_data_add to 52); + +with is2_l2_inv_val select + is2_back_inv_addr(53 to 63-cl_size) <= is2_l2_inv_p_addr(53 to 63-cl_size) when '1', + dir_arr_rd_congr_cl when others; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Performance Counters +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +lsuperf : entity work.xuq_lsu_perf(xuq_lsu_perf) +generic map(expand_type => expand_type) +PORT map( + + -- LSU Performance Events + lsu_perf_events => lsu_perf_events, + + -- PC Control Interface + pc_xu_event_bus_enable => pc_xu_event_bus_enable, + pc_xu_event_count_mode => pc_xu_event_count_mode, + pc_xu_lsu_event_mux_ctrls => pc_xu_lsu_event_mux_ctrls, + pc_xu_cache_par_err_event => pc_xu_cache_par_err_event, + + -- Perf Event Output + xu_pc_lsu_event_data => xu_pc_lsu_event_data, + + -- SPR Bits + spr_msr_gs => xu_lsu_msr_gs, + spr_msr_pr => xu_lsu_msr_pr, + + vdd => vdd, + gnd => gnd, + nclk => nclk, + sg_0 => sg_0, + func_slp_sl_thold_0_b => func_slp_sl_thold_0_b, + func_slp_sl_force => func_slp_sl_force, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc(5), + mpw1_dc_b => mpw1_dc_b(5), + mpw2_dc_b => mpw2_dc_b, + scan_in => cmp_scan_out, + scan_out => func_scan_out_int(46) +); + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Debug Trace Bus +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +lsudbg : entity work.xuq_lsu_debug(xuq_lsu_debug) +generic map(expand_type => expand_type) +PORT map( + + -- PC Debug Control + pc_xu_trace_bus_enable => pc_xu_trace_bus_enable, + lsu_debug_mux_ctrls => lsu_debug_mux_ctrls, + xu_lsu_ex2_instr_trace_val => xu_lsu_ex2_instr_trace_val, + + -- Pass Thru Debug Trace Bus + trigger_data_in => trigger_data_in, + debug_data_in => debug_data_in, + + -- Debug Data + dc_fgen_dbg_data => dc_fgen_dbg_data, + dc_cntrl_dbg_data => dc_cntrl_dbg_data, + dc_val_dbg_data => dc_val_dbg_data, + dc_lru_dbg_data => dc_lru_dbg_data, + dc_dir_dbg_data => dc_dir_dbg_data, + dir_arr_dbg_data => dir_arr_dbg_data, + lmq_dbg_dcache_pe => lmq_dbg_dcache_pe, + lmq_dbg_l2req => lmq_dbg_l2req, + lmq_dbg_rel => lmq_dbg_rel , + lmq_dbg_binv => lmq_dbg_binv, + lmq_dbg_pops => lmq_dbg_pops, + lmq_dbg_grp0 => lmq_dbg_grp0, + lmq_dbg_grp1 => lmq_dbg_grp1, + lmq_dbg_grp2 => lmq_dbg_grp2, + lmq_dbg_grp3 => lmq_dbg_grp3, + lmq_dbg_grp4 => lmq_dbg_grp4, + lmq_dbg_grp5 => lmq_dbg_grp5, + lmq_dbg_grp6 => lmq_dbg_grp6, + pe_recov_begin => pe_recov_begin, + derat_xu_debug_group0 => derat_xu_debug_group0, + derat_xu_debug_group1 => derat_xu_debug_group1, + + -- Outputs + trigger_data_out => trigger_data_out, + debug_data_out => debug_data_out, + + -- Power + vdd => vdd, + gnd => gnd, + nclk => nclk, + sg_0 => sg_0, + func_slp_sl_thold_0_b => func_slp_sl_thold_0_b, + func_slp_sl_force => func_slp_sl_force, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc(5), + mpw1_dc_b => mpw1_dc_b(5), + mpw2_dc_b => mpw2_dc_b, + scan_in => dir_scan_out(0), + scan_out => func_scan_out_int(45) +); + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- FIR Error Reporting +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +DDPerr: tri_direct_err_rpt +generic map(width => 1, expand_type => expand_type) +port map( + vd => vdd, + gd => gnd, + err_in => ex4_dir_perr_det(0 to 0), + err_out => dcachedir_parity(0 to 0) +); + +DDMulti: tri_direct_err_rpt +generic map(width => 1, expand_type => expand_type) +port map( + vd => vdd, + gd => gnd, + err_in => ex4_dir_multihit_det(0 to 0), + err_out => dcachedir_multihit(0 to 0) +); + +ex3_data_swap <= ex3_data_swap_int; +xu_pc_err_dcachedir_parity <= dcachedir_parity(0); +xu_pc_err_dcachedir_multihit <= dcachedir_multihit(0); +lsu_xu_ex3_derat_vf <= derat_xu_ex3_vf and not ex3_blkable_touch; +ldq_rel_addr <= rel_ldq_addr(64-(dc_size-3) to 58); +ldq_rel_axu_val <= rel_ldq_axu_val; +ldq_rel_ci <= rel_ldq_ci; +ldq_rel_thrd_id <= rel_ldq_thrd_id; +xu_fu_ex3_eff_addr <= ex3_p_addr_lwr(59 to 63); +ex3_algebraic <= ex3_algebraic_op; +ex3_thrd_id <= ex3_req_thrd_id; +lsu_xu_ex3_attr <= derat_xu_ex3_u & derat_xu_ex3_wimge; +lsu_xu_ex3_l2_uc_ecc_err <= l2_data_ecc_err_ue; +lsu_xu_datc_perr_recovery <= lmq_pe_recov_state or dcpar_err_flush; +lsu_xu_l2_ecc_err_flush <= gpr_ecc_err_flush_tid; +lsu_xu_ex3_ldq_hit_flush <= cmp_flush; +lsu_xu_ex4_n_lsu_ddmh_flush <= ex4_n_lsu_ddmh_flush; +lsu_xu_is2_back_inv <= is2_l2_inv_val or dir_arr_rd_is2_val; +lsu_xu_is2_back_inv_addr <= is2_back_inv_addr; +lsu_xu_spr_epsc_epr <= xu_derat_epsc0_epr & xu_derat_epsc1_epr & xu_derat_epsc2_epr & xu_derat_epsc3_epr; +lsu_xu_spr_epsc_egs <= xu_derat_epsc0_egs & xu_derat_epsc1_egs & xu_derat_epsc2_egs & xu_derat_epsc3_egs; +bcfg_scan_out <= bcfg_scan_out_int and an_ac_scan_dis_dc_b; +ccfg_scan_out <= ccfg_scan_out_int and an_ac_scan_dis_dc_b; +abst_scan_out <= abst_scan_out_q and an_ac_scan_dis_dc_b; +time_scan_out <= time_scan_out_q and an_ac_scan_dis_dc_b; +repr_scan_out <= repr_scan_out_q and an_ac_scan_dis_dc_b; +func_scan_out <= gate(func_scan_out_q, an_ac_scan_dis_dc_b); +regf_scan_out <= gate(regf_scan_out_q, an_ac_scan_dis_dc_b); +-- Not Connected Scan +dcfg_scan_out_int <= dcfg_scan_in; +dcfg_scan_out <= dcfg_scan_out_int and an_ac_scan_dis_dc_b; + +lsu_xu_barr_done <= derat_iu_barrier_done or lsu_xu_sync_barr_done; +ldq_rel_data_val <= rel_data_val; +ldq_rel_data_val_early <= rel_data_val_early; + +----------------------------------------------------------------------- +-- abist latches +----------------------------------------------------------------------- +abist_reg: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 23, needs_sreset => 0) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => pc_xu_abist_ena_dc, + thold_b => abst_slp_sl_thold_0_b, + sg => sg_0, + forcee => abst_slp_sl_force, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + d_mode => d_mode_dc, + scin => abist_siv(1 to 23), + scout => abist_sov(1 to 23), + din (0) => pc_xu_abist_g8t_wenb, + din (1) => pc_xu_abist_g8t1p_renb_0, + din (2 to 5) => pc_xu_abist_di_0, + din (6) => pc_xu_abist_g8t_bw_1, + din (7) => pc_xu_abist_g8t_bw_0, + din (8 to 12) => pc_xu_abist_waddr_0, + din (13 to 17) => pc_xu_abist_raddr_0, + din (18) => pc_xu_abist_wl32_comp_ena, + din (19 to 22) => pc_xu_abist_g8t_dcomp, + dout(0) => pc_xu_abist_g8t_wenb_q, + dout(1) => pc_xu_abist_g8t1p_renb_0_q, + dout(2 to 5) => pc_xu_abist_di_0_q, + dout(6) => pc_xu_abist_g8t_bw_1_q, + dout(7) => pc_xu_abist_g8t_bw_0_q, + dout(8 to 12) => pc_xu_abist_waddr_0_q, + dout(13 to 17) => pc_xu_abist_raddr_0_q, + dout(18) => pc_xu_abist_wl32_comp_ena_q, + dout(19 to 22) => pc_xu_abist_g8t_dcomp_q); + +------------------------------------------------- +-- Pervasive +------------------------------------------------- +perv_2to1_reg: tri_plat + generic map (width => 13, expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_xu_ccflush_dc, + din(0) => func_slp_sl_thold_2, + din(1) => func_sl_thold_2(3), + din(2) => func_nsl_thold_2, + din(3) => sg_2(3), + din(4) => cfg_slp_sl_thold_2, + din(5) => ary_slp_nsl_thold_2, + din(6) => abst_slp_sl_thold_2, + din(7) => time_sl_thold_2, + din(8) => repr_sl_thold_2, + din(9) => regf_slp_sl_thold_2, + din(10) => func_slp_nsl_thold_2, + din(11) => fce_2, + din(12) => bolt_sl_thold_2, + q(0) => func_slp_sl_thold_1, + q(1) => func_sl_thold_1, + q(2) => func_nsl_thold_1, + q(3) => sg_1, + q(4) => cfg_slp_sl_thold_1, + q(5) => ary_slp_nsl_thold_1, + q(6) => abst_slp_sl_thold_1, + q(7) => time_sl_thold_1, + q(8) => repr_sl_thold_1, + q(9) => regf_slp_sl_thold_1, + q(10) => func_slp_nsl_thold_1, + q(11) => fce_1, + q(12) => bolt_sl_thold_1); + +perv_1to0_reg: tri_plat + generic map (width => 13, expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_xu_ccflush_dc, + din(0) => func_slp_sl_thold_1, + din(1) => func_sl_thold_1, + din(2) => func_nsl_thold_1, + din(3) => sg_1, + din(4) => cfg_slp_sl_thold_1, + din(5) => ary_slp_nsl_thold_1, + din(6) => abst_slp_sl_thold_1, + din(7) => time_sl_thold_1, + din(8) => repr_sl_thold_1, + din(9) => regf_slp_sl_thold_1, + din(10) => func_slp_nsl_thold_1, + din(11) => fce_1, + din(12) => bolt_sl_thold_1, + q(0) => func_slp_sl_thold_0, + q(1) => func_sl_thold_0, + q(2) => func_nsl_thold_0, + q(3) => sg_0, + q(4) => cfg_slp_sl_thold_0, + q(5) => ary_slp_nsl_thold_0, + q(6) => abst_slp_sl_thold_0, + q(7) => time_sl_thold_0, + q(8) => repr_sl_thold_0, + q(9) => regf_slp_sl_thold_0, + q(10) => func_slp_nsl_thold_0, + q(11) => fce_0, + q(12) => bolt_sl_thold_0); + +perv_lcbor_func_sl: tri_lcbor + generic map (expand_type => expand_type) +port map (clkoff_b => clkoff_dc_b, + thold => func_sl_thold_0, + sg => sg_0, + act_dis => tidn, + forcee => func_sl_force, + thold_b => func_sl_thold_0_b); + +perv_lcbor_func_nsl: tri_lcbor + generic map (expand_type => expand_type) +port map (clkoff_b => clkoff_dc_b, + thold => func_nsl_thold_0, + sg => fce_0, + act_dis => tidn, + forcee => func_nsl_force, + thold_b => func_nsl_thold_0_b); + +perv_lcbor_func_slp_sl: tri_lcbor + generic map (expand_type => expand_type) +port map (clkoff_b => clkoff_dc_b, + thold => func_slp_sl_thold_0, + sg => sg_0, + act_dis => tidn, + forcee => func_slp_sl_force, + thold_b => func_slp_sl_thold_0_b); + +perv_lcbor_cfg_slp_sl: tri_lcbor + generic map (expand_type => expand_type) +port map (clkoff_b => clkoff_dc_b, + thold => cfg_slp_sl_thold_0, + sg => sg_0, + act_dis => tidn, + forcee => cfg_slp_sl_force, + thold_b => cfg_slp_sl_thold_0_b); + +perv_lcbor_abst_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_dc_b, + thold => abst_slp_sl_thold_0, + sg => sg_0, + act_dis => tidn, + forcee => abst_slp_sl_force, + thold_b => abst_slp_sl_thold_0_b); + +perv_lcbor_func_slp_nsl: tri_lcbor + generic map (expand_type => expand_type) +port map (clkoff_b => clkoff_dc_b, + thold => func_slp_nsl_thold_0, + sg => fce_0, + act_dis => tidn, + forcee => func_slp_nsl_force, + thold_b => func_slp_nsl_thold_0_b); + +-- LCBs for scan only staging latches +slat_force <= sg_0; +abst_slat_thold_b <= NOT abst_slp_sl_thold_0; +time_slat_thold_b <= NOT time_sl_thold_0; +repr_slat_thold_b <= NOT repr_sl_thold_0; +func_slat_thold_b <= NOT func_sl_thold_0; +regf_slat_thold_b <= NOT regf_slp_sl_thold_0; + +perv_lcbs_abst: tri_lcbs + generic map (expand_type => expand_type ) + port map ( + vd => vdd, + gd => gnd, + delay_lclkr => delay_lclkr_dc(5), + nclk => nclk, + forcee => slat_force, + thold_b => abst_slat_thold_b, + dclk => abst_slat_d2clk, + lclk => abst_slat_lclk ); + +perv_abst_stg: tri_slat_scan + generic map (width => 2, init => "00", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => abst_slat_d2clk, + lclk => abst_slat_lclk, + scan_in(0) => abst_scan_in, + scan_in(1) => abst_scan_out_int, + scan_out(0) => abst_scan_in_q, + scan_out(1) => abst_scan_out_q ); + +perv_lcbs_time: tri_lcbs + generic map (expand_type => expand_type ) + port map ( + vd => vdd, + gd => gnd, + delay_lclkr => delay_lclkr_dc(5), + nclk => nclk, + forcee => slat_force, + thold_b => time_slat_thold_b, + dclk => time_slat_d2clk, + lclk => time_slat_lclk ); + +perv_time_stg: tri_slat_scan + generic map (width => 2, init => "00", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => time_slat_d2clk, + lclk => time_slat_lclk, + scan_in(0) => time_scan_in, + scan_in(1) => time_scan_out_int(1), + scan_out(0) => time_scan_in_q, + scan_out(1) => time_scan_out_q ); + +perv_lcbs_repr: tri_lcbs + generic map (expand_type => expand_type ) + port map ( + vd => vdd, + gd => gnd, + delay_lclkr => delay_lclkr_dc(5), + nclk => nclk, + forcee => slat_force, + thold_b => repr_slat_thold_b, + dclk => repr_slat_d2clk, + lclk => repr_slat_lclk ); + +perv_repr_stg: tri_slat_scan + generic map (width => 2, init => "00", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => repr_slat_d2clk, + lclk => repr_slat_lclk, + scan_in(0) => repr_scan_in, + scan_in(1) => repr_scan_out_int, + scan_out(0) => repr_scan_in_q, + scan_out(1) => repr_scan_out_q ); + +perv_lcbs_func: tri_lcbs + generic map (expand_type => expand_type ) + port map ( + vd => vdd, + gd => gnd, + delay_lclkr => delay_lclkr_dc(5), + nclk => nclk, + forcee => slat_force, + thold_b => func_slat_thold_b, + dclk => func_slat_d2clk, + lclk => func_slat_lclk ); + +-- pass through un-connected scan rings +func_scan_out_int(42) <= derat_scan_out(1); + +perv_func_stg: tri_slat_scan + generic map (width => 18, init => "0000000000", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => func_slat_d2clk, + lclk => func_slat_lclk, + scan_in(0 to 8) => func_scan_in, + scan_in(9 to 17) => func_scan_out_int, + scan_out(0 to 8) => func_scan_in_q, + scan_out(9 to 17) => func_scan_out_q ); + +perv_lcbs_regf: tri_lcbs + generic map (expand_type => expand_type ) + port map ( + vd => vdd, + gd => gnd, + delay_lclkr => delay_lclkr_dc(5), + nclk => nclk, + forcee => slat_force, + thold_b => regf_slat_thold_b, + dclk => regf_slat_d2clk, + lclk => regf_slat_lclk ); + +perv_regf_stg: tri_slat_scan + generic map (width => 14, init => "00000000000000", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => regf_slat_d2clk, + lclk => regf_slat_lclk, + scan_in(0 to 6) => regf_scan_in, + scan_in(7 to 13) => regf_scan_out_int, + scan_out(0 to 6) => regf_scan_in_q, + scan_out(7 to 13) => regf_scan_out_q ); + +abist_siv <= abist_sov(1 to abist_sov'right) & abst_scan_in_q; +abst_scan_out_int <= abist_sov(0); + +mark_unused(derat_xu_ex2_miss); +mark_unused(derat_xu_ex2_rpn); +mark_unused(derat_xu_ex2_wimge); +mark_unused(derat_xu_ex2_u); +mark_unused(derat_xu_ex2_wlc); +mark_unused(derat_xu_ex2_attr); +mark_unused(derat_xu_ex2_vf); +mark_unused(derat_xu_ex3_attr); +mark_unused(derat_fir_par_err); +mark_unused(derat_fir_multihit); + +end xuq_lsu_cmd; diff --git a/rel/src/vhdl/work/xuq_lsu_cmp.vhdl b/rel/src/vhdl/work/xuq_lsu_cmp.vhdl new file mode 100644 index 0000000..b664736 --- /dev/null +++ b/rel/src/vhdl/work/xuq_lsu_cmp.vhdl @@ -0,0 +1,1018 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XU LSU Compare Logic + +library ieee,ibm,support,tri,work; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + use ibm.std_ulogic_unsigned.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; + use support.power_logic_pkg.all; + use tri.tri_latches_pkg.all; + use ibm.std_ulogic_ao_support.all; + use ibm.std_ulogic_mux_support.all; + +entity xuq_lsu_cmp is +generic( expand_type: integer := 2 ); -- 0 - ibm tech, 1 - other ); +port( + vdd :inout power_logic; + gnd :inout power_logic; + nclk :in clk_logic; + delay_lclkr :in std_ulogic_vector(0 to 2);-- LCB input + mpw1_b :in std_ulogic_vector(0 to 2);-- LCB input + mpw2_b :in std_ulogic_vector(0 to 2);-- LCB input + forcee :in std_ulogic_vector(0 to 2);-- LCB input + sg_0 :in std_ulogic_vector(0 to 2);-- LCB input + thold_0_b :in std_ulogic_vector(0 to 2);-- LCB input + scan_in :in std_ulogic_vector(0 to 2); --perv + scan_out :out std_ulogic_vector(0 to 2); --perv + + enable_lsb_lmq_b :in std_ulogic ;--enable lsb in the compares + enable_lsb_oth_b :in std_ulogic ;--enable lsb in the compares + enable_lsb_bi_b :in std_ulogic ;--enable lsb in the compares + + ex2_erat_act :in std_ulogic; -- erat act + binv2_ex2_stg_act :in std_ulogic; -- directory act + lmq_entry_act :in std_ulogic; -- act for lmq entries + + ex3_p_addr :in std_ulogic_vector(22 to 51); -- erat array output + ex2_p_addr_lwr :in std_ulogic_vector(52 to 57); + ex3_p_addr_o :out std_ulogic_vector(22 to 57);--output-- just a rename + + ex2_wayA_tag :in std_ulogic_vector(22 to 52); -- directory output 0/1 + ex2_wayB_tag :in std_ulogic_vector(22 to 52); -- directory output 0/1 + ex2_wayC_tag :in std_ulogic_vector(22 to 52); -- directory output 2/3 + ex2_wayD_tag :in std_ulogic_vector(22 to 52); -- directory output 2/3 + ex2_wayE_tag :in std_ulogic_vector(22 to 52); -- directory output 4/5 + ex2_wayF_tag :in std_ulogic_vector(22 to 52); -- directory output 4/5 + ex2_wayG_tag :in std_ulogic_vector(22 to 52); -- directory output 6/7 + ex2_wayH_tag :in std_ulogic_vector(22 to 52); -- directory output 6/7 + + ex3_cClass_upd_way_a :in std_ulogic; -- enable compare + ex3_cClass_upd_way_b :in std_ulogic; -- enable compare + ex3_cClass_upd_way_c :in std_ulogic; -- enable compare + ex3_cClass_upd_way_d :in std_ulogic; -- enable compare + ex3_cClass_upd_way_e :in std_ulogic; -- enable compare + ex3_cClass_upd_way_f :in std_ulogic; -- enable compare + ex3_cClass_upd_way_g :in std_ulogic; -- enable compare + ex3_cClass_upd_way_h :in std_ulogic; -- enable compare + + ex3_way_cmp_a :out std_ulogic; -- compare result (without the enable) + ex3_way_cmp_b :out std_ulogic; -- compare result (without the enable) + ex3_way_cmp_c :out std_ulogic; -- compare result (without the enable) + ex3_way_cmp_d :out std_ulogic; -- compare result (without the enable) + ex3_way_cmp_e :out std_ulogic; -- compare result (without the enable) + ex3_way_cmp_f :out std_ulogic; -- compare result (without the enable) + ex3_way_cmp_g :out std_ulogic; -- compare result (without the enable) + ex3_way_cmp_h :out std_ulogic; -- compare result (without the enable) + + ex3_wayA_tag :out std_ulogic_vector(0 to 30); -- Way Tag + ex3_wayB_tag :out std_ulogic_vector(0 to 30); -- Way Tag + ex3_wayC_tag :out std_ulogic_vector(0 to 30); -- Way Tag + ex3_wayD_tag :out std_ulogic_vector(0 to 30); -- Way Tag + ex3_wayE_tag :out std_ulogic_vector(0 to 30); -- Way Tag + ex3_wayF_tag :out std_ulogic_vector(0 to 30); -- Way Tag + ex3_wayG_tag :out std_ulogic_vector(0 to 30); -- Way Tag + ex3_wayH_tag :out std_ulogic_vector(0 to 30); -- Way Tag + + ldq_comp_val :in std_ulogic_vector(0 to 7); -- enable compares against lmq + ldq_match :out std_ulogic_vector(0 to 7); -- compare result (without enable) + + ldq_fnd_b :out std_ulogic; -- or 8 enabled ldq compares + cmp_flush :out std_ulogic; -- or all 16 enabled compares + + dir_eq_v_or_b :out std_ulogic; -- the 8 directory match with valid "OR"ed + + l_q_wrt_en :in std_ulogic_vector(0 to 7); -- load entry, (hold when not loading) + ld_ex7_recov :in std_ulogic ; -- alternate ldq wr select + ex7_ld_recov_addr :in std_ulogic_vector(22 to 57) ;-- alternate ldq wr data + + ex4_loadmiss_qentry :in std_ulogic_vector(0 to 7); -- mux 3 select + ex4_ld_addr :out std_ulogic_vector(22 to 57); -- mux 3 + + l_q_rd_en :in std_ulogic_vector(0 to 7); -- mux 2 select + l_miss_entry_addr :out std_ulogic_vector(22 to 57); -- mux 2 + + rel_tag_1hot :in std_ulogic_vector(0 to 7); -- mux 1 select + rel_addr :out std_ulogic_vector(22 to 57); -- mux 1 + + back_inv_addr :in std_ulogic_vector(22 to 57); -- compare to each ldq entry + back_inv_cmp_val :in std_ulogic_vector(0 to 7); -- + back_inv_addr_hit :out std_ulogic_vector(0 to 7); -- + + s_m_queue0_addr :in std_ulogic_vector(22 to 57); -- + st_entry0_val :in std_ulogic ; -- + ex3addr_hit_stq :out std_ulogic ; -- + + ex4_st_entry_addr :in std_ulogic_vector(22 to 57); -- + ex4_st_val :in std_ulogic ; -- + ex3addr_hit_ex4st :out std_ulogic -- + +); + + + +end xuq_lsu_cmp; -- ENTITY + +architecture xuq_lsu_cmp of xuq_lsu_cmp is + + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal ex3_erat_lclk, dir_lclk , lmq_lclk :clk_logic; + signal ex3_erat_d1clk, dir_d1clk , lmq_d1clk :std_ulogic; + signal ex3_erat_d2clk, dir_d2clk , lmq_d2clk :std_ulogic; + + signal ex3_erat_q :std_ulogic_vector(0 to 35); + signal ex3_erat_q_b :std_ulogic_vector(30 to 35); + signal ex3_erat_si, ex3_erat_so :std_ulogic_vector(0 to 5); + signal dir0_si, dir0_so, dir0_q_b, dir0_q :std_ulogic_vector(0 to 30); + signal dir1_si, dir1_so, dir1_q_b, dir1_q :std_ulogic_vector(0 to 30); + signal dir2_si, dir2_so, dir2_q_b, dir2_q :std_ulogic_vector(0 to 30); + signal dir3_si, dir3_so, dir3_q_b, dir3_q :std_ulogic_vector(0 to 30); + signal dir4_si, dir4_so, dir4_q_b, dir4_q :std_ulogic_vector(0 to 30); + signal dir5_si, dir5_so, dir5_q_b, dir5_q :std_ulogic_vector(0 to 30); + signal dir6_si, dir6_so, dir6_q_b, dir6_q :std_ulogic_vector(0 to 30); + signal dir7_si, dir7_so, dir7_q_b, dir7_q :std_ulogic_vector(0 to 30); + signal lmq0_si, lmq0_so, lmq0_q_b, lmq0_q , lmq0_din , lmq0_new_b , lmq0_fbk_b :std_ulogic_vector(0 to 35); + signal lmq1_si, lmq1_so, lmq1_q_b, lmq1_q , lmq1_din , lmq1_new_b , lmq1_fbk_b :std_ulogic_vector(0 to 35); + signal lmq2_si, lmq2_so, lmq2_q_b, lmq2_q , lmq2_din , lmq2_new_b , lmq2_fbk_b :std_ulogic_vector(0 to 35); + signal lmq3_si, lmq3_so, lmq3_q_b, lmq3_q , lmq3_din , lmq3_new_b , lmq3_fbk_b :std_ulogic_vector(0 to 35); + signal lmq4_si, lmq4_so, lmq4_q_b, lmq4_q , lmq4_din , lmq4_new_b , lmq4_fbk_b :std_ulogic_vector(0 to 35); + signal lmq5_si, lmq5_so, lmq5_q_b, lmq5_q , lmq5_din , lmq5_new_b , lmq5_fbk_b :std_ulogic_vector(0 to 35); + signal lmq6_si, lmq6_so, lmq6_q_b, lmq6_q , lmq6_din , lmq6_new_b , lmq6_fbk_b :std_ulogic_vector(0 to 35); + signal lmq7_si, lmq7_so, lmq7_q_b, lmq7_q , lmq7_din , lmq7_new_b , lmq7_fbk_b :std_ulogic_vector(0 to 35); + + signal l_q_wrt_en_b :std_ulogic_vector(0 to 7); + + + signal ex3_erat_i1_b :std_ulogic_vector(0 to 35); --7p5 HOP OVER dir 23 , hop over dir latches + signal ex3_erat_i2 :std_ulogic_vector(0 to 35); --7p5 drive compare plus terminator + signal ex3_erat_i3_b :std_ulogic_vector(0 to 35); --2 terminator + signal ex3_erat_i4 :std_ulogic_vector(0 to 35); --4 drive out off stack to compares + signal ex3_erat_i5_b :std_ulogic_vector(0 to 35); --4 drive 2 compares + signal ex3_erat_i6 :std_ulogic_vector(0 to 35); --4 output + signal ex3_erat_din :std_ulogic_vector(0 to 35); --4 hop to final comp + signal ld_ex7_recov_b :std_ulogic ; + signal ex3_lmq_wd0_b, ex3_lmq_wd1_b, ex3_lmq_wd, ex3_lmq_wd_b :std_ulogic_vector(0 to 35); + + + signal dir4_q1_b, dir4_q0 :std_ulogic_vector(0 to 30); + signal dir5_q1_b, dir5_q0 :std_ulogic_vector(0 to 30); + signal dir6_q1_b, dir6_q0 :std_ulogic_vector(0 to 30); + signal dir7_q1_b, dir7_q0 :std_ulogic_vector(0 to 30); + + + signal lmq_eq, lmq_eq_b :std_ulogic_vector(0 to 7); + signal dir_eq :std_ulogic_vector(0 to 7); + + + + signal lmq0_i0_b , lmq0_ix , lmq0_ix1_b, lmq0_ix2, lmq0_iy :std_ulogic_vector(0 to 35); + signal lmq1_i0_b , lmq1_ix , lmq1_ix1_b, lmq1_ix2, lmq1_iy :std_ulogic_vector(0 to 35); + signal lmq2_i0_b , lmq2_ix , lmq2_ix1_b, lmq2_ix2, lmq2_iy :std_ulogic_vector(0 to 35); + signal lmq3_i0_b , lmq3_ix , lmq3_ix1_b, lmq3_ix2, lmq3_iy :std_ulogic_vector(0 to 35); + signal lmq4_i0_b , lmq4_ix , lmq4_ix1_b, lmq4_ix2, lmq4_iy :std_ulogic_vector(0 to 35); + signal lmq5_i0_b , lmq5_ix , lmq5_ix1_b, lmq5_ix2, lmq5_iy :std_ulogic_vector(0 to 35); + signal lmq6_i0_b , lmq6_ix , lmq6_ix1_b, lmq6_ix2, lmq6_iy :std_ulogic_vector(0 to 35); + signal lmq7_i0_b , lmq7_ix , lmq7_ix1_b, lmq7_ix2, lmq7_iy :std_ulogic_vector(0 to 35); + + + + signal smq_addr_b, sto_addr_b :std_ulogic_vector(0 to 35); + signal smq_eq, smq_eqv_b, sto_eq, sto_eqv_b :std_ulogic; + + signal binv_addr_b, binv_addr :std_ulogic_vector(0 to 35); + signal binv_eq, binv_eqv_b :std_ulogic_vector(0 to 7); + + + signal mux1_lv1_01_b, mux1_lv1_23_b, mux1_lv1_45_b, mux1_lv1_67_b :std_ulogic_vector(0 to 35); + signal mux1_lv2_03, mux1_lv2_47, mux1_lv3_07_b :std_ulogic_vector(0 to 35); + + signal mux2_lv1_01_b, mux2_lv1_23_b, mux2_lv1_45_b, mux2_lv1_67_b :std_ulogic_vector(0 to 35); + signal mux2_lv2_03, mux2_lv2_47, mux2_lv3_07_b :std_ulogic_vector(0 to 35); + + signal mux3_lv1_01_b, mux3_lv1_23_b, mux3_lv1_45_b, mux3_lv1_67_b :std_ulogic_vector(0 to 35); + signal mux3_lv2_03, mux3_lv2_47, mux3_lv3_07_b :std_ulogic_vector(0 to 35); + + + signal cmpe_36_b :std_ulogic_vector(0 to 7); + signal o2_36 :std_ulogic_vector(0 to 3); + signal o4_36_b :std_ulogic_vector(0 to 1); + signal o8_36 :std_ulogic; + + signal cmpe_30_b :std_ulogic_vector(0 to 7); + signal o2_30 :std_ulogic_vector(0 to 3); + signal o4_30_b :std_ulogic_vector(0 to 1); + signal o8_30 :std_ulogic; + signal hit_b, hit, hit_1_b, hit_2, hit_3_b :std_ulogic ; + + + signal dir_comp_val :std_ulogic_vector(0 to 7); + + + signal enable_lsb_lmq, enable_lsb_oth, enable_lsb_bi :std_ulogic ; + + -----------------//--------------------------------------------------------------- + + +begin + +-- ################################################################ +-- # inverters from array to latches : add later +-- ################################################################ + +-- ################################################################ +-- # redrive networks after Latches +-- ################################################################ + + ex3_erat_q(0 to 29) <= ex3_p_addr; + u_ex3_erat_q : ex3_erat_q (30 to 35) <= not( ex3_erat_q_b (30 to 35)); --7p5 HOP OVER dir 45 + u_ex3_erat_i1 : ex3_erat_i1_b (0 to 35) <= not( ex3_erat_q (0 to 35) ); --7p5 HOP OVER dir 23 , hop over dir latches + u_ex3_erat_i2 : ex3_erat_i2 (0 to 35) <= not( ex3_erat_i1_b (0 to 35) ); --7p5 drive compare plus terminator + u_ex3_erat_i3 : ex3_erat_i3_b (0 to 35) <= not( ex3_erat_i2 (0 to 35) ); --2 terminator + u_ex3_erat_i4 : ex3_erat_i4 (0 to 35) <= not( ex3_erat_i3_b (0 to 35) ); --4 hop to final comp + u_ex3_erat_i5 : ex3_erat_i5_b (0 to 35) <= not( ex3_erat_i4 (0 to 35) ); --4 drive 2 compares + u_ex3_erat_i6 : ex3_erat_i6 (0 to 35) <= not( ex3_erat_i5_b (0 to 35) ); --4 output + ex3_p_addr_o(22 to 57) <= ex3_erat_i6 (0 to 35) ; --output-- just a rename + + ld_ex7_recov_b <= not( ld_ex7_recov ); + + u_ex3_lmq_wd0 : ex3_lmq_wd0_b(0 to 35) <= not( ex3_erat_i4 (0 to 35) and (0 to 35=> ld_ex7_recov_b) ) ; --1 + u_ex3_lmq_wd1 : ex3_lmq_wd1_b(0 to 35) <= not( ex7_ld_recov_addr(22 to 57) and (0 to 35=> ld_ex7_recov ) ) ; --1 + u_ex3_lmq_wd : ex3_lmq_wd (0 to 35) <= not( ex3_lmq_wd0_b(0 to 35) and ex3_lmq_wd1_b(0 to 35) ) ; --2 + u_ex3_lmq_wdi : ex3_lmq_wd_b (0 to 35) <= not( ex3_lmq_wd(0 to 35) ) ; --4 + u_ex3_erat_din : ex3_erat_din (0 to 35) <= not( ex3_lmq_wd_b(0 to 35) ); --6 drive 8 regs in queue + + + + -- also need to drive 8 latch datas + + -- 0/1 4/5 are above + -- 2/3 6/7 are below -- ltches 0123 4567 (4567 have extra distance) + + u_dir0_q: dir0_q (0 to 30) <= not( dir0_q_b (0 to 30) );--4 + u_dir1_q: dir1_q (0 to 30) <= not( dir1_q_b (0 to 30) );--4 + u_dir2_q: dir2_q (0 to 30) <= not( dir2_q_b (0 to 30) );--4 + u_dir3_q: dir3_q (0 to 30) <= not( dir3_q_b (0 to 30) );--4 + + u_dir4_q0: dir4_q0 (0 to 30) <= not( dir4_q_b (0 to 30) );--4 + u_dir5_q0: dir5_q0 (0 to 30) <= not( dir5_q_b (0 to 30) );--4 + u_dir6_q0: dir6_q0 (0 to 30) <= not( dir6_q_b (0 to 30) );--4 + u_dir7_q0: dir7_q0 (0 to 30) <= not( dir7_q_b (0 to 30) );--4 + + u_dir4_q1: dir4_q1_b (0 to 30) <= not( dir4_q0 (0 to 30) );--6 + u_dir5_q1: dir5_q1_b (0 to 30) <= not( dir5_q0 (0 to 30) );--6 + u_dir6_q1: dir6_q1_b (0 to 30) <= not( dir6_q0 (0 to 30) );--6 + u_dir7_q1: dir7_q1_b (0 to 30) <= not( dir7_q0 (0 to 30) );--6 + + u_dir4_q: dir4_q (0 to 30) <= not( dir4_q1_b (0 to 30) );--4 + u_dir5_q: dir5_q (0 to 30) <= not( dir5_q1_b (0 to 30) );--4 + u_dir6_q: dir6_q (0 to 30) <= not( dir6_q1_b (0 to 30) );--4 + u_dir7_q: dir7_q (0 to 30) <= not( dir7_q1_b (0 to 30) );--4 + + +-- ################################################################ +-- # directory compares against erat +-- ################################################################ + + dir0cmp: entity work.xuq_lsu_cmp_cmp31(xuq_lsu_cmp_cmp31) port map( + d0(0 to 30) => ex3_erat_i2(0 to 30) ,--i--xuq_lsu_cmp_cmp31(dir0cmp) + d1(0 to 30) => dir0_q (0 to 30) ,--i--xuq_lsu_cmp_cmp31(dir0cmp) + eq => dir_eq(0) );--o--xuq_lsu_cmp_cmp31(dir0cmp) + + dir1cmp: entity work.xuq_lsu_cmp_cmp31(xuq_lsu_cmp_cmp31) port map( + d0(0 to 30) => ex3_erat_i2(0 to 30) ,--i--xuq_lsu_cmp_cmp31(dir1cmp) + d1(0 to 30) => dir1_q (0 to 30) ,--i--xuq_lsu_cmp_cmp31(dir1cmp) + eq => dir_eq(1) );--o--xuq_lsu_cmp_cmp31(dir1cmp) + + dir2cmp: entity work.xuq_lsu_cmp_cmp31(xuq_lsu_cmp_cmp31) port map( + d0(0 to 30) => ex3_erat_i2(0 to 30) ,--i--xuq_lsu_cmp_cmp31(dir2cmp) + d1(0 to 30) => dir2_q (0 to 30) ,--i--xuq_lsu_cmp_cmp31(dir2cmp) + eq => dir_eq(2) );--o--xuq_lsu_cmp_cmp31(dir2cmp) + + dir3cmp: entity work.xuq_lsu_cmp_cmp31(xuq_lsu_cmp_cmp31) port map( + d0(0 to 30) => ex3_erat_i2(0 to 30) ,--i--xuq_lsu_cmp_cmp31(dir3cmp) + d1(0 to 30) => dir3_q (0 to 30) ,--i--xuq_lsu_cmp_cmp31(dir3cmp) + eq => dir_eq(3) );--o--xuq_lsu_cmp_cmp31(dir3cmp) + + dir4cmp: entity work.xuq_lsu_cmp_cmp31(xuq_lsu_cmp_cmp31) port map( + d0(0 to 30) => ex3_erat_i2(0 to 30) ,--i--xuq_lsu_cmp_cmp31(dir4cmp) + d1(0 to 30) => dir4_q (0 to 30) ,--i--xuq_lsu_cmp_cmp31(dir4cmp) + eq => dir_eq(4) );--o--xuq_lsu_cmp_cmp31(dir4cmp) + + dir5cmp: entity work.xuq_lsu_cmp_cmp31(xuq_lsu_cmp_cmp31) port map( + d0(0 to 30) => ex3_erat_i2(0 to 30) ,--i--xuq_lsu_cmp_cmp31(dir5cmp) + d1(0 to 30) => dir5_q (0 to 30) ,--i--xuq_lsu_cmp_cmp31(dir5cmp) + eq => dir_eq(5) );--o--xuq_lsu_cmp_cmp31(dir5cmp) + + dir6cmp: entity work.xuq_lsu_cmp_cmp31(xuq_lsu_cmp_cmp31) port map( + d0(0 to 30) => ex3_erat_i2(0 to 30) ,--i--xuq_lsu_cmp_cmp31(dir6cmp) + d1(0 to 30) => dir6_q (0 to 30) ,--i--xuq_lsu_cmp_cmp31(dir6cmp) + eq => dir_eq(6) );--o--xuq_lsu_cmp_cmp31(dir6cmp) + + dir7cmp: entity work.xuq_lsu_cmp_cmp31(xuq_lsu_cmp_cmp31) port map( + d0(0 to 30) => ex3_erat_i2(0 to 30) ,--i--xuq_lsu_cmp_cmp31(dir7cmp) + d1(0 to 30) => dir7_q (0 to 30) ,--i--xuq_lsu_cmp_cmp31(dir7cmp) + eq => dir_eq(7) );--o--xuq_lsu_cmp_cmp31(dir7cmp) + + +ex3_way_cmp_a <= dir_eq(0); +ex3_way_cmp_b <= dir_eq(1); +ex3_way_cmp_c <= dir_eq(2); +ex3_way_cmp_d <= dir_eq(3); +ex3_way_cmp_e <= dir_eq(4); +ex3_way_cmp_f <= dir_eq(5); +ex3_way_cmp_g <= dir_eq(6); +ex3_way_cmp_h <= dir_eq(7); + +ex3_wayA_tag <= not dir0_q_b; +ex3_wayB_tag <= not dir1_q_b; +ex3_wayC_tag <= not dir2_q_b; +ex3_wayD_tag <= not dir3_q_b; +ex3_wayE_tag <= not dir4_q_b; +ex3_wayF_tag <= not dir5_q_b; +ex3_wayG_tag <= not dir6_q_b; +ex3_wayH_tag <= not dir7_q_b; + +-- ################################################################ +-- # ldq compares against erat +-- ################################################################ + + lmq0cmp: entity work.xuq_lsu_cmp_cmp36e(xuq_lsu_cmp_cmp36e) port map( + enable_lsb => enable_lsb_lmq ,--i--xuq_lsu_cmp_cmp36e(lmq0cmp) + d0(0 to 35) => ex3_erat_i2(0 to 35) ,--i--xuq_lsu_cmp_cmp36e(lmq0cmp) + d1(0 to 35) => lmq0_iy (0 to 35) ,--i--xuq_lsu_cmp_cmp36e(lmq0cmp) + eq => lmq_eq(0) );--o--xuq_lsu_cmp_cmp36e(lmq0cmp) + + lmq1cmp: entity work.xuq_lsu_cmp_cmp36e(xuq_lsu_cmp_cmp36e) port map( + enable_lsb => enable_lsb_lmq ,--i--xuq_lsu_cmp_cmp36e(lmq1cmp) + d0(0 to 35) => ex3_erat_i2(0 to 35) ,--i--xuq_lsu_cmp_cmp36e(lmq1cmp) + d1(0 to 35) => lmq1_iy (0 to 35) ,--i--xuq_lsu_cmp_cmp36e(lmq1cmp) + eq => lmq_eq(1) );--o--xuq_lsu_cmp_cmp36e(lmq1cmp) + + lmq2cmp: entity work.xuq_lsu_cmp_cmp36e(xuq_lsu_cmp_cmp36e) port map( + enable_lsb => enable_lsb_lmq ,--i--xuq_lsu_cmp_cmp36e(lmq2cmp) + d0(0 to 35) => ex3_erat_i2(0 to 35) ,--i--xuq_lsu_cmp_cmp36e(lmq2cmp) + d1(0 to 35) => lmq2_iy (0 to 35) ,--i--xuq_lsu_cmp_cmp36e(lmq2cmp) + eq => lmq_eq(2) );--o--xuq_lsu_cmp_cmp36e(lmq2cmp) + + lmq3cmp: entity work.xuq_lsu_cmp_cmp36e(xuq_lsu_cmp_cmp36e) port map( + enable_lsb => enable_lsb_lmq ,--i--xuq_lsu_cmp_cmp36e(lmq3cmp) + d0(0 to 35) => ex3_erat_i2(0 to 35) ,--i--xuq_lsu_cmp_cmp36e(lmq3cmp) + d1(0 to 35) => lmq3_iy (0 to 35) ,--i--xuq_lsu_cmp_cmp36e(lmq3cmp) + eq => lmq_eq(3) );--o--xuq_lsu_cmp_cmp36e(lmq3cmp) + + lmq4cmp: entity work.xuq_lsu_cmp_cmp36e(xuq_lsu_cmp_cmp36e) port map( + enable_lsb => enable_lsb_lmq ,--i--xuq_lsu_cmp_cmp36e(lmq4cmp) + d0(0 to 35) => ex3_erat_i2(0 to 35) ,--i--xuq_lsu_cmp_cmp36e(lmq4cmp) + d1(0 to 35) => lmq4_iy (0 to 35) ,--i--xuq_lsu_cmp_cmp36e(lmq4cmp) + eq => lmq_eq(4) );--o--xuq_lsu_cmp_cmp36e(lmq4cmp) + + lmq5cmp: entity work.xuq_lsu_cmp_cmp36e(xuq_lsu_cmp_cmp36e) port map( + enable_lsb => enable_lsb_lmq ,--i--xuq_lsu_cmp_cmp36e(lmq5cmp) + d0(0 to 35) => ex3_erat_i2(0 to 35) ,--i--xuq_lsu_cmp_cmp36e(lmq5cmp) + d1(0 to 35) => lmq5_iy (0 to 35) ,--i--xuq_lsu_cmp_cmp36e(lmq5cmp) + eq => lmq_eq(5) );--o--xuq_lsu_cmp_cmp36e(lmq5cmp) + + lmq6cmp: entity work.xuq_lsu_cmp_cmp36e(xuq_lsu_cmp_cmp36e) port map( + enable_lsb => enable_lsb_lmq ,--i--xuq_lsu_cmp_cmp36e(lmq6cmp) + d0(0 to 35) => ex3_erat_i2(0 to 35) ,--i--xuq_lsu_cmp_cmp36e(lmq6cmp) + d1(0 to 35) => lmq6_iy (0 to 35) ,--i--xuq_lsu_cmp_cmp36e(lmq6cmp) + eq => lmq_eq(6) );--o--xuq_lsu_cmp_cmp36e(lmq6cmp) + + lmq7cmp: entity work.xuq_lsu_cmp_cmp36e(xuq_lsu_cmp_cmp36e) port map( + enable_lsb => enable_lsb_lmq ,--i--xuq_lsu_cmp_cmp36e(lmq7cmp) + d0(0 to 35) => ex3_erat_i2(0 to 35) ,--i--xuq_lsu_cmp_cmp36e(lmq7cmp) + d1(0 to 35) => lmq7_iy (0 to 35) ,--i--xuq_lsu_cmp_cmp36e(lmq7cmp) + eq => lmq_eq(7) );--o--xuq_lsu_cmp_cmp36e(lmq7cmp) + + u_lmq_cmp_cp: lmq_eq_b(0 to 7) <= not( lmq_eq (0 to 7) ); --ungated compare + ldq_match(0 to 7) <= not( lmq_eq_b(0 to 7) ); --output-- --unmapped, match output phase, but allow synth to optimize out + + +-- ############################################################### +-- # or the compares together +-- ############################################################### + + dir_comp_val(0) <= ex3_cClass_upd_way_a ; + dir_comp_val(1) <= ex3_cClass_upd_way_b ; + dir_comp_val(2) <= ex3_cClass_upd_way_c ; + dir_comp_val(3) <= ex3_cClass_upd_way_d ; + dir_comp_val(4) <= ex3_cClass_upd_way_e ; + dir_comp_val(5) <= ex3_cClass_upd_way_f ; + dir_comp_val(6) <= ex3_cClass_upd_way_g ; + dir_comp_val(7) <= ex3_cClass_upd_way_h ; + + + u_cmpe_36: cmpe_36_b(0 to 7) <= not( lmq_eq(0 to 7) and ldq_comp_val(0 to 7) ) ; + + u_o2_36_0: o2_36(0) <= not( cmpe_36_b(0) and cmpe_36_b(1) ); + u_o2_36_1: o2_36(1) <= not( cmpe_36_b(2) and cmpe_36_b(3) ); + u_o2_36_2: o2_36(2) <= not( cmpe_36_b(4) and cmpe_36_b(5) ); + u_o2_36_3: o2_36(3) <= not( cmpe_36_b(6) and cmpe_36_b(7) ); + + u_o4_36_0: o4_36_b(0) <= not( o2_36(0) or o2_36(1) ); + u_o4_36_1: o4_36_b(1) <= not( o2_36(2) or o2_36(3) ); + + u_o8_36: o8_36 <= not( o4_36_b(0) and o4_36_b(1) ); + + + u_cmpe_30: cmpe_30_b(0 to 7) <= not( dir_eq(0 to 7) and dir_comp_val(0 to 7) ) ; + + u_o2_30_0: o2_30(0) <= not( cmpe_30_b(0) and cmpe_30_b(1) ); + u_o2_30_1: o2_30(1) <= not( cmpe_30_b(2) and cmpe_30_b(3) ); + u_o2_30_2: o2_30(2) <= not( cmpe_30_b(4) and cmpe_30_b(5) ); + u_o2_30_3: o2_30(3) <= not( cmpe_30_b(6) and cmpe_30_b(7) ); + + u_o4_30_0: o4_30_b(0) <= not( o2_30(0) or o2_30(1) ); + u_o4_30_1: o4_30_b(1) <= not( o2_30(2) or o2_30(3) ); + + u_o8_30: o8_30 <= not( o4_30_b(0) and o4_30_b(1) ); + + + u_o16i: hit_b <= not( o8_36 ); + u_o16: hit <= not( hit_b ); -- 1 + u_hit_1: hit_1_b <= not( hit ); + u_hit_2: hit_2 <= not( hit_1_b ); + u_hit_3: hit_3_b <= not( hit_2 ); + u_hit_4: cmp_flush <= not( hit_3_b ); --output-- + + + u_o8_dir: dir_eq_v_or_b <= not( o8_30 );--output-- + u_o8_ldq: ldq_fnd_b <= not( o8_36 );--output-- + + + + +-- ################################################################ +-- # 2 miscellaneous compares against erat (above stack) +-- ################################################################ + + smq_addr_b(0 to 35) <= not( s_m_queue0_addr (22 to 57) ); + sto_addr_b(0 to 35) <= not( ex4_st_entry_addr(22 to 57) ); + + smq_cmp: entity work.xuq_lsu_cmp_cmp36e(xuq_lsu_cmp_cmp36e) port map( + enable_lsb => enable_lsb_oth ,--i--xuq_lsu_cmp_cmp36e(smq_cmp) + d0(0 to 35) => ex3_erat_i5_b(0 to 35) ,--i--xuq_lsu_cmp_cmp36e(smq_cmp) + d1(0 to 35) => smq_addr_b (0 to 35) ,--i--xuq_lsu_cmp_cmp36e(smq_cmp) + eq => smq_eq );--o--xuq_lsu_cmp_cmp36e(smq_cmp) + + sto_cmp: entity work.xuq_lsu_cmp_cmp36e(xuq_lsu_cmp_cmp36e) port map( + enable_lsb => enable_lsb_oth ,--i--xuq_lsu_cmp_cmp36e(sto_cmp) + d0(0 to 35) => ex3_erat_i5_b(0 to 35) ,--i--xuq_lsu_cmp_cmp36e(sto_cmp) + d1(0 to 35) => sto_addr_b (0 to 35) ,--i--xuq_lsu_cmp_cmp36e(sto_cmp) + eq => sto_eq );--o--xuq_lsu_cmp_cmp36e(sto_cmp) + + + u_smq_eqv: smq_eqv_b <= not( smq_eq and st_entry0_val ); + u_sto_eqv: sto_eqv_b <= not( sto_eq and ex4_st_val ); + + ex3addr_hit_stq <= not( smq_eqv_b ); --output-- let synth optimize out + ex3addr_hit_ex4st <= not( sto_eqv_b ); --output-- let synth optimize out + + + + +-- ################################################################ +-- # muxes in front of load miss queue , and repower +-- ################################################################ + + l_q_wrt_en_b(0 to 7) <= not l_q_wrt_en(0 to 7); + + u_lmq0_q: lmq0_q (0 to 35) <= not( lmq0_q_b(0 to 35) ); --2 + u_lmq1_q: lmq1_q (0 to 35) <= not( lmq1_q_b(0 to 35) ); --2 + u_lmq2_q: lmq2_q (0 to 35) <= not( lmq2_q_b(0 to 35) ); --2 + u_lmq3_q: lmq3_q (0 to 35) <= not( lmq3_q_b(0 to 35) ); --2 + u_lmq4_q: lmq4_q (0 to 35) <= not( lmq4_q_b(0 to 35) ); --2 + u_lmq5_q: lmq5_q (0 to 35) <= not( lmq5_q_b(0 to 35) ); --2 + u_lmq6_q: lmq6_q (0 to 35) <= not( lmq6_q_b(0 to 35) ); --2 + u_lmq7_q: lmq7_q (0 to 35) <= not( lmq7_q_b(0 to 35) ); --2 + + u_lmq0_i0: lmq0_i0_b(0 to 35) <= not( lmq0_q (0 to 35) ); --4 + u_lmq1_i0: lmq1_i0_b(0 to 35) <= not( lmq1_q (0 to 35) ); --4 + u_lmq2_i0: lmq2_i0_b(0 to 35) <= not( lmq2_q (0 to 35) ); --4 + u_lmq3_i0: lmq3_i0_b(0 to 35) <= not( lmq3_q (0 to 35) ); --4 + u_lmq4_i0: lmq4_i0_b(0 to 35) <= not( lmq4_q (0 to 35) ); --4 + u_lmq5_i0: lmq5_i0_b(0 to 35) <= not( lmq5_q (0 to 35) ); --4 + u_lmq6_i0: lmq6_i0_b(0 to 35) <= not( lmq6_q (0 to 35) ); --4 + u_lmq7_i0: lmq7_i0_b(0 to 35) <= not( lmq7_q (0 to 35) ); --4 + + u_lmq0_iy: lmq0_iy (0 to 35) <= not( lmq0_i0_b(0 to 35) ); --4 drives to left (ERAT compares ) + u_lmq1_iy: lmq1_iy (0 to 35) <= not( lmq1_i0_b(0 to 35) ); --4 drives to left (ERAT compares ) + u_lmq2_iy: lmq2_iy (0 to 35) <= not( lmq2_i0_b(0 to 35) ); --4 drives to left (ERAT compares ) + u_lmq3_iy: lmq3_iy (0 to 35) <= not( lmq3_i0_b(0 to 35) ); --4 drives to left (ERAT compares ) + u_lmq4_iy: lmq4_iy (0 to 35) <= not( lmq4_i0_b(0 to 35) ); --4 drives to left (ERAT compares ) + u_lmq5_iy: lmq5_iy (0 to 35) <= not( lmq5_i0_b(0 to 35) ); --4 drives to left (ERAT compares ) + u_lmq6_iy: lmq6_iy (0 to 35) <= not( lmq6_i0_b(0 to 35) ); --4 drives to left (ERAT compares ) + u_lmq7_iy: lmq7_iy (0 to 35) <= not( lmq7_i0_b(0 to 35) ); --4 drives to left (ERAT compares ) + + u_lmq0_ix: lmq0_ix (0 to 35) <= not( lmq0_i0_b(0 to 35) ); --4 drives to right (other compares) + u_lmq1_ix: lmq1_ix (0 to 35) <= not( lmq1_i0_b(0 to 35) ); --4 drives to right (other compares) + u_lmq2_ix: lmq2_ix (0 to 35) <= not( lmq2_i0_b(0 to 35) ); --4 drives to right (other compares) + u_lmq3_ix: lmq3_ix (0 to 35) <= not( lmq3_i0_b(0 to 35) ); --4 drives to right (other compares) + u_lmq4_ix: lmq4_ix (0 to 35) <= not( lmq4_i0_b(0 to 35) ); --4 drives to right (other compares) + u_lmq5_ix: lmq5_ix (0 to 35) <= not( lmq5_i0_b(0 to 35) ); --4 drives to right (other compares) + u_lmq6_ix: lmq6_ix (0 to 35) <= not( lmq6_i0_b(0 to 35) ); --4 drives to right (other compares) + u_lmq7_ix: lmq7_ix (0 to 35) <= not( lmq7_i0_b(0 to 35) ); --4 drives to right (other compares) + + u_lmq0_ix1: lmq0_ix1_b(0 to 35) <= not( lmq0_ix (0 to 35) ); --1 buffer off + u_lmq1_ix1: lmq1_ix1_b(0 to 35) <= not( lmq1_ix (0 to 35) ); --1 + u_lmq2_ix1: lmq2_ix1_b(0 to 35) <= not( lmq2_ix (0 to 35) ); --1 + u_lmq3_ix1: lmq3_ix1_b(0 to 35) <= not( lmq3_ix (0 to 35) ); --1 + u_lmq4_ix1: lmq4_ix1_b(0 to 35) <= not( lmq4_ix (0 to 35) ); --1 + u_lmq5_ix1: lmq5_ix1_b(0 to 35) <= not( lmq5_ix (0 to 35) ); --1 + u_lmq6_ix1: lmq6_ix1_b(0 to 35) <= not( lmq6_ix (0 to 35) ); --1 + u_lmq7_ix1: lmq7_ix1_b(0 to 35) <= not( lmq7_ix (0 to 35) ); --1 + + u_lmq0_ix2: lmq0_ix2 (0 to 35) <= not( lmq0_ix1_b(0 to 35) ); --2 mux input + u_lmq1_ix2: lmq1_ix2 (0 to 35) <= not( lmq1_ix1_b(0 to 35) ); --2 + u_lmq2_ix2: lmq2_ix2 (0 to 35) <= not( lmq2_ix1_b(0 to 35) ); --2 + u_lmq3_ix2: lmq3_ix2 (0 to 35) <= not( lmq3_ix1_b(0 to 35) ); --2 + u_lmq4_ix2: lmq4_ix2 (0 to 35) <= not( lmq4_ix1_b(0 to 35) ); --2 + u_lmq5_ix2: lmq5_ix2 (0 to 35) <= not( lmq5_ix1_b(0 to 35) ); --2 + u_lmq6_ix2: lmq6_ix2 (0 to 35) <= not( lmq6_ix1_b(0 to 35) ); --2 + u_lmq7_ix2: lmq7_ix2 (0 to 35) <= not( lmq7_ix1_b(0 to 35) ); --2 + + + u_lmq0_new: lmq0_new_b(0 to 35) <= not( ex3_erat_din(0 to 35) and (0 to 35=> l_q_wrt_en (0) ) ); -- 0p5 + u_lmq1_new: lmq1_new_b(0 to 35) <= not( ex3_erat_din(0 to 35) and (0 to 35=> l_q_wrt_en (1) ) ); -- 0p5 + u_lmq2_new: lmq2_new_b(0 to 35) <= not( ex3_erat_din(0 to 35) and (0 to 35=> l_q_wrt_en (2) ) ); -- 0p5 + u_lmq3_new: lmq3_new_b(0 to 35) <= not( ex3_erat_din(0 to 35) and (0 to 35=> l_q_wrt_en (3) ) ); -- 0p5 + u_lmq4_new: lmq4_new_b(0 to 35) <= not( ex3_erat_din(0 to 35) and (0 to 35=> l_q_wrt_en (4) ) ); -- 0p5 + u_lmq5_new: lmq5_new_b(0 to 35) <= not( ex3_erat_din(0 to 35) and (0 to 35=> l_q_wrt_en (5) ) ); -- 0p5 + u_lmq6_new: lmq6_new_b(0 to 35) <= not( ex3_erat_din(0 to 35) and (0 to 35=> l_q_wrt_en (6) ) ); -- 0p5 + u_lmq7_new: lmq7_new_b(0 to 35) <= not( ex3_erat_din(0 to 35) and (0 to 35=> l_q_wrt_en (7) ) ); -- 0p5 + + u_lmq0_fbk: lmq0_fbk_b(0 to 35) <= not( lmq0_ix (0 to 35) and (0 to 35=> l_q_wrt_en_b(0) ) ); -- 0p5 + u_lmq1_fbk: lmq1_fbk_b(0 to 35) <= not( lmq1_ix (0 to 35) and (0 to 35=> l_q_wrt_en_b(1) ) ); -- 0p5 + u_lmq2_fbk: lmq2_fbk_b(0 to 35) <= not( lmq2_ix (0 to 35) and (0 to 35=> l_q_wrt_en_b(2) ) ); -- 0p5 + u_lmq3_fbk: lmq3_fbk_b(0 to 35) <= not( lmq3_ix (0 to 35) and (0 to 35=> l_q_wrt_en_b(3) ) ); -- 0p5 + u_lmq4_fbk: lmq4_fbk_b(0 to 35) <= not( lmq4_ix (0 to 35) and (0 to 35=> l_q_wrt_en_b(4) ) ); -- 0p5 + u_lmq5_fbk: lmq5_fbk_b(0 to 35) <= not( lmq5_ix (0 to 35) and (0 to 35=> l_q_wrt_en_b(5) ) ); -- 0p5 + u_lmq6_fbk: lmq6_fbk_b(0 to 35) <= not( lmq6_ix (0 to 35) and (0 to 35=> l_q_wrt_en_b(6) ) ); -- 0p5 + u_lmq7_fbk: lmq7_fbk_b(0 to 35) <= not( lmq7_ix (0 to 35) and (0 to 35=> l_q_wrt_en_b(7) ) ); -- 0p5 + + u_lmq0_din: lmq0_din (0 to 35) <= not( lmq0_new_b (0 to 35) and lmq0_fbk_b(0 to 35) ); -- 1 + u_lmq1_din: lmq1_din (0 to 35) <= not( lmq1_new_b (0 to 35) and lmq1_fbk_b(0 to 35) ); -- 1 + u_lmq2_din: lmq2_din (0 to 35) <= not( lmq2_new_b (0 to 35) and lmq2_fbk_b(0 to 35) ); -- 1 + u_lmq3_din: lmq3_din (0 to 35) <= not( lmq3_new_b (0 to 35) and lmq3_fbk_b(0 to 35) ); -- 1 + u_lmq4_din: lmq4_din (0 to 35) <= not( lmq4_new_b (0 to 35) and lmq4_fbk_b(0 to 35) ); -- 1 + u_lmq5_din: lmq5_din (0 to 35) <= not( lmq5_new_b (0 to 35) and lmq5_fbk_b(0 to 35) ); -- 1 + u_lmq6_din: lmq6_din (0 to 35) <= not( lmq6_new_b (0 to 35) and lmq6_fbk_b(0 to 35) ); -- 1 + u_lmq7_din: lmq7_din (0 to 35) <= not( lmq7_new_b (0 to 35) and lmq7_fbk_b(0 to 35) ); -- 1 + + + + +-- ################################################################ +-- # 8 compares with the non-ERAT address +-- ################################################################ + + + binv_addr_b(0 to 35) <= not( back_inv_addr(22 to 57) ); -- not mapping + u_binv_addr: binv_addr (0 to 35) <= not( binv_addr_b(0 to 35) ); -- need to place + + binv0cmp: entity work.xuq_lsu_cmp_cmp36e(xuq_lsu_cmp_cmp36e) port map( + enable_lsb => enable_lsb_bi ,--i--xuq_lsu_cmp_cmp36e(binv0cmp) + d0(0 to 35) => binv_addr (0 to 35) ,--i--xuq_lsu_cmp_cmp36e(binv0cmp) + d1(0 to 35) => lmq0_ix (0 to 35) ,--i--xuq_lsu_cmp_cmp36e(binv0cmp) + eq => binv_eq(0) );--o--xuq_lsu_cmp_cmp36e(binv0cmp) + + binv1cmp: entity work.xuq_lsu_cmp_cmp36e(xuq_lsu_cmp_cmp36e) port map( + enable_lsb => enable_lsb_bi ,--i--xuq_lsu_cmp_cmp36e(binv1cmp) + d0(0 to 35) => binv_addr (0 to 35) ,--i--xuq_lsu_cmp_cmp36e(binv1cmp) + d1(0 to 35) => lmq1_ix (0 to 35) ,--i--xuq_lsu_cmp_cmp36e(binv1cmp) + eq => binv_eq(1) );--o--xuq_lsu_cmp_cmp36e(binv1cmp) + + binv2cmp: entity work.xuq_lsu_cmp_cmp36e(xuq_lsu_cmp_cmp36e) port map( + enable_lsb => enable_lsb_bi ,--i--xuq_lsu_cmp_cmp36e(binv2cmp) + d0(0 to 35) => binv_addr (0 to 35) ,--i--xuq_lsu_cmp_cmp36e(binv2cmp) + d1(0 to 35) => lmq2_ix (0 to 35) ,--i--xuq_lsu_cmp_cmp36e(binv2cmp) + eq => binv_eq(2) );--o--xuq_lsu_cmp_cmp36e(binv2cmp) + + binv3cmp: entity work.xuq_lsu_cmp_cmp36e(xuq_lsu_cmp_cmp36e) port map( + enable_lsb => enable_lsb_bi ,--i--xuq_lsu_cmp_cmp36e(binv3cmp) + d0(0 to 35) => binv_addr (0 to 35) ,--i--xuq_lsu_cmp_cmp36e(binv3cmp) + d1(0 to 35) => lmq3_ix (0 to 35) ,--i--xuq_lsu_cmp_cmp36e(binv3cmp) + eq => binv_eq(3) );--o--xuq_lsu_cmp_cmp36e(binv3cmp) + + binv4cmp: entity work.xuq_lsu_cmp_cmp36e(xuq_lsu_cmp_cmp36e) port map( + enable_lsb => enable_lsb_bi ,--i--xuq_lsu_cmp_cmp36e(binv4cmp) + d0(0 to 35) => binv_addr (0 to 35) ,--i--xuq_lsu_cmp_cmp36e(binv4cmp) + d1(0 to 35) => lmq4_ix (0 to 35) ,--i--xuq_lsu_cmp_cmp36e(binv4cmp) + eq => binv_eq(4) );--o--xuq_lsu_cmp_cmp36e(binv4cmp) + + binv5cmp: entity work.xuq_lsu_cmp_cmp36e(xuq_lsu_cmp_cmp36e) port map( + enable_lsb => enable_lsb_bi ,--i--xuq_lsu_cmp_cmp36e(binv5cmp) + d0(0 to 35) => binv_addr (0 to 35) ,--i--xuq_lsu_cmp_cmp36e(binv5cmp) + d1(0 to 35) => lmq5_ix (0 to 35) ,--i--xuq_lsu_cmp_cmp36e(binv5cmp) + eq => binv_eq(5) );--o--xuq_lsu_cmp_cmp36e(binv5cmp) + + binv6cmp: entity work.xuq_lsu_cmp_cmp36e(xuq_lsu_cmp_cmp36e) port map( + enable_lsb => enable_lsb_bi ,--i--xuq_lsu_cmp_cmp36e(binv6cmp) + d0(0 to 35) => binv_addr (0 to 35) ,--i--xuq_lsu_cmp_cmp36e(binv6cmp) + d1(0 to 35) => lmq6_ix (0 to 35) ,--i--xuq_lsu_cmp_cmp36e(binv6cmp) + eq => binv_eq(6) );--o--xuq_lsu_cmp_cmp36e(binv6cmp) + + binv7cmp: entity work.xuq_lsu_cmp_cmp36e(xuq_lsu_cmp_cmp36e) port map( + enable_lsb => enable_lsb_bi ,--i--xuq_lsu_cmp_cmp36e(binv7cmp) + d0(0 to 35) => binv_addr (0 to 35) ,--i--xuq_lsu_cmp_cmp36e(binv7cmp) + d1(0 to 35) => lmq7_ix (0 to 35) ,--i--xuq_lsu_cmp_cmp36e(binv7cmp) + eq => binv_eq(7) );--o--xuq_lsu_cmp_cmp36e(binv7cmp) + + + u_binv_eqv: binv_eqv_b (0 to 7) <= not( binv_eq(0 to 7) and back_inv_cmp_val(0 to 7) ); -- gated compare + back_inv_addr_hit(0 to 7) <= not( binv_eqv_b(0 to 7) ); --output-- --unmapped, match output phase, but allow synth to optimize out + + +-- ################################################################ +-- # output mux 1 +-- ################################################################ + + + u_mux1_lv1_01: mux1_lv1_01_b(0 to 35) <= not( ( lmq0_ix2(0 to 35) and (0 to 35 => rel_tag_1hot(0) ) ) or + ( lmq1_ix2(0 to 35) and (0 to 35 => rel_tag_1hot(1) ) ) ); + u_mux1_lv1_23: mux1_lv1_23_b(0 to 35) <= not( ( lmq2_ix2(0 to 35) and (0 to 35 => rel_tag_1hot(2) ) ) or + ( lmq3_ix2(0 to 35) and (0 to 35 => rel_tag_1hot(3) ) ) ); + u_mux1_lv1_45: mux1_lv1_45_b(0 to 35) <= not( ( lmq4_ix2(0 to 35) and (0 to 35 => rel_tag_1hot(4) ) ) or + ( lmq5_ix2(0 to 35) and (0 to 35 => rel_tag_1hot(5) ) ) ); + u_mux1_lv1_67: mux1_lv1_67_b(0 to 35) <= not( ( lmq6_ix2(0 to 35) and (0 to 35 => rel_tag_1hot(6) ) ) or + ( lmq7_ix2(0 to 35) and (0 to 35 => rel_tag_1hot(7) ) ) ); + + u_mux1_lv2_03: mux1_lv2_03(0 to 35) <= not( mux1_lv1_01_b(0 to 35) and mux1_lv1_23_b(0 to 35) ); + u_mux1_lv2_47: mux1_lv2_47(0 to 35) <= not( mux1_lv1_45_b(0 to 35) and mux1_lv1_67_b(0 to 35) ); + + u_mux1_lv3_07: mux1_lv3_07_b(0 to 35) <= not( mux1_lv2_03(0 to 35) or mux1_lv2_47(0 to 35) ); + + rel_addr(22 to 57) <= not mux1_lv3_07_b(0 to 35) ; -- let synth repower -- + + +-- ################################################################ +-- # output mux 2 +-- ################################################################ + + u_mux2_lv1_01: mux2_lv1_01_b(0 to 35) <= not( ( lmq0_ix2(0 to 35) and (0 to 35 => l_q_rd_en(0) ) ) or + ( lmq1_ix2(0 to 35) and (0 to 35 => l_q_rd_en(1) ) ) ); + u_mux2_lv1_23: mux2_lv1_23_b(0 to 35) <= not( ( lmq2_ix2(0 to 35) and (0 to 35 => l_q_rd_en(2) ) ) or + ( lmq3_ix2(0 to 35) and (0 to 35 => l_q_rd_en(3) ) ) ); + u_mux2_lv1_45: mux2_lv1_45_b(0 to 35) <= not( ( lmq4_ix2(0 to 35) and (0 to 35 => l_q_rd_en(4) ) ) or + ( lmq5_ix2(0 to 35) and (0 to 35 => l_q_rd_en(5) ) ) ); + u_mux2_lv1_67: mux2_lv1_67_b(0 to 35) <= not( ( lmq6_ix2(0 to 35) and (0 to 35 => l_q_rd_en(6) ) ) or + ( lmq7_ix2(0 to 35) and (0 to 35 => l_q_rd_en(7) ) ) ); + + + u_mux2_lv2_03: mux2_lv2_03(0 to 35) <= not( mux2_lv1_01_b(0 to 35) and mux2_lv1_23_b(0 to 35) ); + u_mux2_lv2_47: mux2_lv2_47(0 to 35) <= not( mux2_lv1_45_b(0 to 35) and mux2_lv1_67_b(0 to 35) ); + + u_mux2_lv3_07: mux2_lv3_07_b(0 to 35) <= not( mux2_lv2_03(0 to 35) or mux2_lv2_47(0 to 35) ); + + l_miss_entry_addr(22 to 57) <= not mux2_lv3_07_b(0 to 35) ; -- let synth repower -- + + +-- ################################################################ +-- # output mux 3 +-- ################################################################ + + + u_mux3_lv1_01: mux3_lv1_01_b(0 to 35) <= not( ( lmq0_ix2(0 to 35) and (0 to 35 => ex4_loadmiss_qentry(0) ) ) or + ( lmq1_ix2(0 to 35) and (0 to 35 => ex4_loadmiss_qentry(1) ) ) ); + u_mux3_lv1_23: mux3_lv1_23_b(0 to 35) <= not( ( lmq2_ix2(0 to 35) and (0 to 35 => ex4_loadmiss_qentry(2) ) ) or + ( lmq3_ix2(0 to 35) and (0 to 35 => ex4_loadmiss_qentry(3) ) ) ); + u_mux3_lv1_45: mux3_lv1_45_b(0 to 35) <= not( ( lmq4_ix2(0 to 35) and (0 to 35 => ex4_loadmiss_qentry(4) ) ) or + ( lmq5_ix2(0 to 35) and (0 to 35 => ex4_loadmiss_qentry(5) ) ) ); + u_mux3_lv1_67: mux3_lv1_67_b(0 to 35) <= not( ( lmq6_ix2(0 to 35) and (0 to 35 => ex4_loadmiss_qentry(6) ) ) or + ( lmq7_ix2(0 to 35) and (0 to 35 => ex4_loadmiss_qentry(7) ) ) ); + + + u_mux3_lv2_03: mux3_lv2_03(0 to 35) <= not( mux3_lv1_01_b(0 to 35) and mux3_lv1_23_b(0 to 35) ); + u_mux3_lv2_47: mux3_lv2_47(0 to 35) <= not( mux3_lv1_45_b(0 to 35) and mux3_lv1_67_b(0 to 35) ); + + u_mux3_lv3_07: mux3_lv3_07_b(0 to 35) <= not( mux3_lv2_03(0 to 35) or mux3_lv2_47(0 to 35) ); + + ex4_ld_addr(22 to 57) <= not mux3_lv3_07_b(0 to 35) ; -- let synth repower -- + + + u_en_lsb_lmq: enable_lsb_lmq <= not( enable_lsb_lmq_b ); + u_en_lsb_oth: enable_lsb_oth <= not( enable_lsb_oth_b ); + u_en_lsb_bi: enable_lsb_bi <= not( enable_lsb_bi_b ); + + + +-- ################################################################ +-- # Latches +-- ################################################################ + + lmq0_lat: entity tri.tri_inv_nlats generic map (width => 36, init=> (1 to 36=>'0'), btr=> "NLI0001_X1_A12TH", expand_type => expand_type) port map ( + VD => vdd , + GD => gnd , + LCLK => lmq_lclk , + D1CLK => lmq_d1clk , + D2CLK => lmq_d2clk , + SCANIN => lmq0_si , + SCANOUT => lmq0_so , + D => lmq0_din(0 to 35) , + QB => lmq0_q_b(0 to 35) ); + + lmq1_lat: entity tri.tri_inv_nlats generic map (width => 36, init=> (1 to 36=>'0'), btr=> "NLI0001_X1_A12TH", expand_type => expand_type) port map ( + VD => vdd , + GD => gnd , + LCLK => lmq_lclk , + D1CLK => lmq_d1clk , + D2CLK => lmq_d2clk , + SCANIN => lmq1_si , + SCANOUT => lmq1_so , + D => lmq1_din(0 to 35) , + QB => lmq1_q_b(0 to 35) ); + + lmq2_lat: entity tri.tri_inv_nlats generic map (width => 36, init=> (1 to 36=>'0'), btr=> "NLI0001_X1_A12TH", expand_type => expand_type) port map ( + VD => vdd , + GD => gnd , + LCLK => lmq_lclk , + D1CLK => lmq_d1clk , + D2CLK => lmq_d2clk , + SCANIN => lmq2_si , + SCANOUT => lmq2_so , + D => lmq2_din(0 to 35) , + QB => lmq2_q_b(0 to 35) ); + + lmq3_lat: entity tri.tri_inv_nlats generic map (width => 36, init=> (1 to 36=>'0'), btr=> "NLI0001_X1_A12TH", expand_type => expand_type) port map ( + VD => vdd , + GD => gnd , + LCLK => lmq_lclk , + D1CLK => lmq_d1clk , + D2CLK => lmq_d2clk , + SCANIN => lmq3_si , + SCANOUT => lmq3_so , + D => lmq3_din(0 to 35) , + QB => lmq3_q_b(0 to 35) ); + + lmq4_lat: entity tri.tri_inv_nlats generic map (width => 36, init=> (1 to 36=>'0'), btr=> "NLI0001_X1_A12TH", expand_type => expand_type) port map ( + VD => vdd , + GD => gnd , + LCLK => lmq_lclk , + D1CLK => lmq_d1clk , + D2CLK => lmq_d2clk , + SCANIN => lmq4_si , + SCANOUT => lmq4_so , + D => lmq4_din(0 to 35) , + QB => lmq4_q_b(0 to 35) ); + + lmq5_lat: entity tri.tri_inv_nlats generic map (width => 36, init=> (1 to 36=>'0'), btr=> "NLI0001_X1_A12TH", expand_type => expand_type) port map ( + VD => vdd , + GD => gnd , + LCLK => lmq_lclk , + D1CLK => lmq_d1clk , + D2CLK => lmq_d2clk , + SCANIN => lmq5_si , + SCANOUT => lmq5_so , + D => lmq5_din(0 to 35) , + QB => lmq5_q_b(0 to 35) ); + + lmq6_lat: entity tri.tri_inv_nlats generic map (width => 36, init=> (1 to 36=>'0'), btr=> "NLI0001_X1_A12TH", expand_type => expand_type) port map ( + VD => vdd , + GD => gnd , + LCLK => lmq_lclk , + D1CLK => lmq_d1clk , + D2CLK => lmq_d2clk , + SCANIN => lmq6_si , + SCANOUT => lmq6_so , + D => lmq6_din(0 to 35) , + QB => lmq6_q_b(0 to 35) ); + + lmq7_lat: entity tri.tri_inv_nlats generic map (width => 36, init=> (1 to 36=>'0'), btr=> "NLI0001_X1_A12TH", expand_type => expand_type) port map ( + VD => vdd , + GD => gnd , + LCLK => lmq_lclk , + D1CLK => lmq_d1clk , + D2CLK => lmq_d2clk , + SCANIN => lmq7_si , + SCANOUT => lmq7_so , + D => lmq7_din(0 to 35) , + QB => lmq7_q_b(0 to 35) ); + + ex3_erat_lat: entity tri.tri_inv_nlats generic map (width => 6, init=> (1 to 6=>'0'), btr=> "NLI0001_X4_A12TH", expand_type => expand_type) port map ( + VD => vdd , + GD => gnd , + LCLK => ex3_erat_lclk , + D1CLK => ex3_erat_d1clk , + D2CLK => ex3_erat_d2clk , + SCANIN => ex3_erat_si , + SCANOUT => ex3_erat_so , + D => ex2_p_addr_lwr(52 to 57) , + QB => ex3_erat_q_b(30 to 35) ); + + dir0_lat: entity tri.tri_inv_nlats generic map (width => 31, init=> (1 to 31=>'0'), btr=> "NLI0001_X2_A12TH", expand_type => expand_type) port map ( + VD => vdd , + GD => gnd , + LCLK => dir_lclk , + D1CLK => dir_d1clk , + D2CLK => dir_d2clk , + SCANIN => dir0_si , + SCANOUT => dir0_so , + D => ex2_wayA_tag(22 to 52) , + QB => dir0_q_b(0 to 30) ); + + dir1_lat: entity tri.tri_inv_nlats generic map (width => 31, init=> (1 to 31=>'0'), btr=> "NLI0001_X2_A12TH", expand_type => expand_type) port map ( + VD => vdd , + GD => gnd , + LCLK => dir_lclk , + D1CLK => dir_d1clk , + D2CLK => dir_d2clk , + SCANIN => dir1_si , + SCANOUT => dir1_so , + D => ex2_wayB_tag(22 to 52) , + QB => dir1_q_b(0 to 30) ); + + dir2_lat: entity tri.tri_inv_nlats generic map (width => 31, init=> (1 to 31=>'0'), btr=> "NLI0001_X2_A12TH", expand_type => expand_type) port map ( + VD => vdd , + GD => gnd , + LCLK => dir_lclk , + D1CLK => dir_d1clk , + D2CLK => dir_d2clk , + SCANIN => dir2_si , + SCANOUT => dir2_so , + D => ex2_wayC_tag(22 to 52) , + QB => dir2_q_b(0 to 30) ); + + dir3_lat: entity tri.tri_inv_nlats generic map (width => 31, init=> (1 to 31=>'0'), btr=> "NLI0001_X2_A12TH", expand_type => expand_type) port map ( + VD => vdd , + GD => gnd , + LCLK => dir_lclk , + D1CLK => dir_d1clk , + D2CLK => dir_d2clk , + SCANIN => dir3_si , + SCANOUT => dir3_so , + D => ex2_wayD_tag(22 to 52) , + QB => dir3_q_b(0 to 30) ); + + dir4_lat: entity tri.tri_inv_nlats generic map (width => 31, init=> (1 to 31=>'0'), btr=> "NLI0001_X2_A12TH", expand_type => expand_type) port map ( + VD => vdd , + GD => gnd , + LCLK => dir_lclk , + D1CLK => dir_d1clk , + D2CLK => dir_d2clk , + SCANIN => dir4_si , + SCANOUT => dir4_so , + D => ex2_wayE_tag(22 to 52) , + QB => dir4_q_b(0 to 30) ); + + dir5_lat: entity tri.tri_inv_nlats generic map (width => 31, init=> (1 to 31=>'0'), btr=> "NLI0001_X2_A12TH", expand_type => expand_type) port map ( + VD => vdd , + GD => gnd , + LCLK => dir_lclk , + D1CLK => dir_d1clk , + D2CLK => dir_d2clk , + SCANIN => dir5_si , + SCANOUT => dir5_so , + D => ex2_wayF_tag(22 to 52) , + QB => dir5_q_b(0 to 30) ); + + dir6_lat: entity tri.tri_inv_nlats generic map (width => 31, init=> (1 to 31=>'0'), btr=> "NLI0001_X2_A12TH", expand_type => expand_type) port map ( + VD => vdd , + GD => gnd , + LCLK => dir_lclk , + D1CLK => dir_d1clk , + D2CLK => dir_d2clk , + SCANIN => dir6_si , + SCANOUT => dir6_so , + D => ex2_wayG_tag(22 to 52) , + QB => dir6_q_b(0 to 30) ); + + dir7_lat: entity tri.tri_inv_nlats generic map (width => 31, init=> (1 to 31=>'0'), btr=> "NLI0001_X2_A12TH", expand_type => expand_type) port map ( + VD => vdd , + GD => gnd , + LCLK => dir_lclk , + D1CLK => dir_d1clk , + D2CLK => dir_d2clk , + SCANIN => dir7_si , + SCANOUT => dir7_so , + D => ex2_wayH_tag(22 to 52) , + QB => dir7_q_b(0 to 30) ); + + + + +-- ############################################################### +-- # LCBs +-- ############################################################### + + ex3_erat_lcb : tri_lcbnd generic map (expand_type => expand_type) port map( + nclk => nclk ,--in + vd => vdd ,--inout + gd => gnd ,--inout + act => ex2_erat_act ,--in + delay_lclkr => delay_lclkr (0) ,--in + mpw1_b => mpw1_b (0) ,--in + mpw2_b => mpw2_b (0) ,--in + forcee => forcee (0) ,--in + sg => sg_0 (0) ,--in + thold_b => thold_0_b (0) ,--in + d1clk => ex3_erat_d1clk ,--out + d2clk => ex3_erat_d2clk ,--out + lclk => ex3_erat_lclk );--out + + dir_lcb : tri_lcbnd generic map (expand_type => expand_type) port map( + nclk => nclk ,--in + vd => vdd ,--inout + gd => gnd ,--inout + act => binv2_ex2_stg_act ,--in + delay_lclkr => delay_lclkr (1) ,--in + mpw1_b => mpw1_b (1) ,--in + mpw2_b => mpw2_b (1) ,--in + forcee => forcee (1) ,--in + sg => sg_0 (1) ,--in + thold_b => thold_0_b (1) ,--in + d1clk => dir_d1clk ,--out + d2clk => dir_d2clk ,--out + lclk => dir_lclk );--out + + lmq_lcb : tri_lcbnd generic map (expand_type => expand_type) port map( + nclk => nclk ,--in + vd => vdd ,--inout + gd => gnd ,--inout + act => lmq_entry_act ,--in + delay_lclkr => delay_lclkr (2) ,--in + mpw1_b => mpw1_b (2) ,--in + mpw2_b => mpw2_b (2) ,--in + forcee => forcee (2) ,--in + sg => sg_0 (2) ,--in + thold_b => thold_0_b (2) ,--in + d1clk => lmq_d1clk ,--out + d2clk => lmq_d2clk ,--out + lclk => lmq_lclk );--out + + + +--=############################################################### + + + ex3_erat_si(5) <= scan_in(0); + ex3_erat_si(0 to 4) <= ex3_erat_so(1 to 5); + scan_out(0) <= ex3_erat_so(0); + + dir0_si(0) <= scan_in(1); + dir0_si(1 to 30) <= dir0_so(0 to 29); + dir1_si(30) <= dir0_so(30) ; + dir1_si(0 to 29) <= dir1_so(1 to 30); + dir2_si(0) <= dir1_so(0) ; + dir2_si(1 to 30) <= dir2_so(0 to 29); + dir3_si(30) <= dir2_so(30) ; + dir3_si(0 to 29) <= dir3_so(1 to 30); + dir4_si(0) <= dir3_so(0) ; + dir4_si(1 to 30) <= dir4_so(0 to 29); + dir5_si(30) <= dir4_so(30) ; + dir5_si(0 to 29) <= dir5_so(1 to 30); + dir6_si(0) <= dir5_so(0) ; + dir6_si(1 to 30) <= dir6_so(0 to 29); + dir7_si(30) <= dir6_so(30) ; + dir7_si(0 to 29) <= dir7_so(1 to 30); + scan_out(1) <= dir7_so(0) ; + + lmq0_si(0) <= scan_in(2); + lmq0_si(1 to 35) <= lmq0_so(0 to 34); + lmq1_si(35) <= lmq0_so(35) ; + lmq1_si(0 to 34) <= lmq1_so(1 to 35); + lmq2_si(0) <= lmq1_so(0) ; + lmq2_si(1 to 35) <= lmq2_so(0 to 34); + lmq3_si(35) <= lmq2_so(35) ; + lmq3_si(0 to 34) <= lmq3_so(1 to 35); + lmq4_si(0) <= lmq3_so(0) ; + lmq4_si(1 to 35) <= lmq4_so(0 to 34); + lmq5_si(35) <= lmq4_so(35) ; + lmq5_si(0 to 34) <= lmq5_so(1 to 35); + lmq6_si(0) <= lmq5_so(0) ; + lmq6_si(1 to 35) <= lmq6_so(0 to 34); + lmq7_si(35) <= lmq6_so(35) ; + lmq7_si(0 to 34) <= lmq7_so(1 to 35); + scan_out(2) <= lmq7_so(0) ; + + +end; -- xuq_lsu_cmp ARCHITECTURE diff --git a/rel/src/vhdl/work/xuq_lsu_cmp_cmp31.vhdl b/rel/src/vhdl/work/xuq_lsu_cmp_cmp31.vhdl new file mode 100644 index 0000000..b128329 --- /dev/null +++ b/rel/src/vhdl/work/xuq_lsu_cmp_cmp31.vhdl @@ -0,0 +1,103 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XU LSU Compare Logic + + +-- ################################################################### +-- ## Address decoder +-- ################################################################### + + +LIBRARY ieee; USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY ibm; + USE ibm.std_ulogic_support.all; + USE ibm.std_ulogic_unsigned.all; + USE ibm.std_ulogic_function_support.all; +LIBRARY support; + USE support.power_logic_pkg.all; +LIBRARY tri; USE tri.tri_latches_pkg.all; + +entity xuq_lsu_cmp_cmp31 is +generic( expand_type: integer := 2 ); -- 0 - ibm tech, 1 - other ); +port( + d0 :in std_ulogic_vector(0 to 30); + d1 :in std_ulogic_vector(0 to 30); + eq :out std_ulogic +); + + + + + +end xuq_lsu_cmp_cmp31; -- ENTITY + +architecture xuq_lsu_cmp_cmp31 of xuq_lsu_cmp_cmp31 is + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal eq01 :std_ulogic_vector(0 to 30) ; + signal eq03_b : std_ulogic_vector(0 to 11); + signal eq06 : std_ulogic_vector(0 to 5); + signal eq18_b : std_ulogic_vector(0 to 1); + + +begin + + + u_eq01: eq01(0 to 30) <= not( d0(0 to 30) xor d1(0 to 30) ); + + u_eq03_00: eq03_b( 0) <= not( eq01( 0) and eq01( 1) and eq01( 2) ); + u_eq03_01: eq03_b( 1) <= not( eq01( 3) and eq01( 4) and eq01( 5) ); + u_eq03_02: eq03_b( 2) <= not( eq01( 6) and eq01( 7) and eq01( 8) ); + u_eq03_03: eq03_b( 3) <= not( eq01( 9) and eq01(10) and eq01(11) ); + u_eq03_04: eq03_b( 4) <= not( eq01(12) and eq01(13) and eq01(14) ); + u_eq03_05: eq03_b( 5) <= not( eq01(15) and eq01(16) and eq01(17) ); + u_eq03_06: eq03_b( 6) <= not( eq01(18) and eq01(19) and eq01(20) ); + u_eq03_07: eq03_b( 7) <= not( eq01(21) and eq01(22) ); + u_eq03_08: eq03_b( 8) <= not( eq01(23) and eq01(24) ); + u_eq03_09: eq03_b( 9) <= not( eq01(25) and eq01(26) ); + u_eq03_10: eq03_b(10) <= not( eq01(27) and eq01(28) ); + u_eq03_11: eq03_b(11) <= not( eq01(29) and eq01(30) ); + + u_eq06_00: eq06( 0) <= not( eq03_b( 0) or eq03_b( 1) ); + u_eq06_01: eq06( 1) <= not( eq03_b( 2) or eq03_b( 3) ); + u_eq06_02: eq06( 2) <= not( eq03_b( 4) or eq03_b( 5) ); + u_eq06_03: eq06( 3) <= not( eq03_b( 6) or eq03_b( 7) ); + u_eq06_04: eq06( 4) <= not( eq03_b( 8) or eq03_b( 9) ); + u_eq06_05: eq06( 5) <= not( eq03_b(10) or eq03_b(11) ); + + u_eq18_00: eq18_b( 0) <= not( eq06(0) and eq06(1) and eq06(2) ); + u_eq18_01: eq18_b( 1) <= not( eq06(3) and eq06(4) and eq06(5) ); + + u_eq36_00: eq <= not( eq18_b( 0) or eq18_b( 1) ); -- output + + + +end; -- xuq_lsu_cmp_cmp31 ARCHITECTURE diff --git a/rel/src/vhdl/work/xuq_lsu_cmp_cmp36e.vhdl b/rel/src/vhdl/work/xuq_lsu_cmp_cmp36e.vhdl new file mode 100644 index 0000000..245813a --- /dev/null +++ b/rel/src/vhdl/work/xuq_lsu_cmp_cmp36e.vhdl @@ -0,0 +1,121 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XU LSU Compare Logic + + +-- ################################################################### +-- ## Address decoder +-- ################################################################### + + +LIBRARY ieee; USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY ibm; + USE ibm.std_ulogic_support.all; + USE ibm.std_ulogic_unsigned.all; + USE ibm.std_ulogic_function_support.all; +LIBRARY support; + USE support.power_logic_pkg.all; +LIBRARY tri; USE tri.tri_latches_pkg.all; + +entity xuq_lsu_cmp_cmp36e is +generic( expand_type: integer := 2 ); -- 0 - ibm tech, 1 - other ); +port( + enable_lsb :in std_ulogic; -- when "0" the LSB is disabled + d0 :in std_ulogic_vector(0 to 35); + d1 :in std_ulogic_vector(0 to 35); + eq :out std_ulogic +); + + + + + +end xuq_lsu_cmp_cmp36e; -- ENTITY + +architecture xuq_lsu_cmp_cmp36e of xuq_lsu_cmp_cmp36e is + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal eq01_b :std_ulogic_vector(0 to 35) ; + signal eq02 :std_ulogic_vector(0 to 18) ; + signal eq04_b :std_ulogic_vector(0 to 9); + signal eq08 :std_ulogic_vector(0 to 4); + signal eq24_b :std_ulogic_vector(0 to 1); + + +begin + + + u_eq01: eq01_b(0 to 35) <= ( d0(0 to 35) xor d1(0 to 35) ); + + u_eq_00: eq02 ( 0) <= not( eq01_b( 0) or eq01_b( 1) ); + u_eq_02: eq02 ( 1) <= not( eq01_b( 2) or eq01_b( 3) ); + u_eq_04: eq02 ( 2) <= not( eq01_b( 4) or eq01_b( 5) ); + u_eq_06: eq02 ( 3) <= not( eq01_b( 6) or eq01_b( 7) ); + u_eq_08: eq02 ( 4) <= not( eq01_b( 8) or eq01_b( 9) ); + u_eq_10: eq02 ( 5) <= not( eq01_b(10) or eq01_b(11) ); + u_eq_12: eq02 ( 6) <= not( eq01_b(12) or eq01_b(13) ); + u_eq_14: eq02 ( 7) <= not( eq01_b(14) or eq01_b(15) ); + u_eq_16: eq02 ( 8) <= not( eq01_b(16) or eq01_b(17) ); + u_eq_18: eq02 ( 9) <= not( eq01_b(18) or eq01_b(19) ); + u_eq_20: eq02 (10) <= not( eq01_b(20) or eq01_b(21) ); + u_eq_22: eq02 (11) <= not( eq01_b(22) or eq01_b(23) ); + u_eq_24: eq02 (12) <= not( eq01_b(24) or eq01_b(25) ); + u_eq_26: eq02 (13) <= not( eq01_b(26) or eq01_b(27) ); + u_eq_28: eq02 (14) <= not( eq01_b(28) or eq01_b(29) ); + u_eq_30: eq02 (15) <= not( eq01_b(30) or eq01_b(31) ); + u_eq_31: eq02 (16) <= not( eq01_b(32) or eq01_b(33) ); + u_eq_33: eq02 (17) <= not( eq01_b(34) ); + u_eq_35: eq02 (18) <= not( eq01_b(35) and enable_lsb ); + + u_eq_01: eq04_b( 0) <= not( eq02 ( 0) and eq02 ( 1) ); + u_eq_05: eq04_b( 1) <= not( eq02 ( 2) and eq02 ( 3) ); + u_eq_09: eq04_b( 2) <= not( eq02 ( 4) and eq02 ( 5) ); + u_eq_13: eq04_b( 3) <= not( eq02 ( 6) and eq02 ( 7) ); + u_eq_17: eq04_b( 4) <= not( eq02 ( 8) and eq02 ( 9) ); + u_eq_21: eq04_b( 5) <= not( eq02 (10) and eq02 (11) ); + u_eq_25: eq04_b( 6) <= not( eq02 (12) and eq02 (13) ); + u_eq_29: eq04_b( 7) <= not( eq02 (14) and eq02 (15) ); + u_eq_32: eq04_b( 8) <= not( eq02 (16) and eq02 (17) ); + u_eq_36: eq04_b( 9) <= not( eq02 (18) ); + + u_eq_03: eq08 ( 0) <= not( eq04_b( 0) or eq04_b( 1) ); + u_eq_11: eq08 ( 1) <= not( eq04_b( 2) or eq04_b( 3) ); + u_eq_19: eq08 ( 2) <= not( eq04_b( 4) or eq04_b( 5) ); + u_eq_27: eq08 ( 3) <= not( eq04_b( 6) or eq04_b( 7) ); + u_eq_34: eq08 ( 4) <= not( eq04_b( 8) or eq04_b( 9) ); + + u_eq_07: eq24_b( 0) <= not( eq08 ( 0) and eq08 ( 1) and eq08 ( 2) ); + u_eq_23: eq24_b( 1) <= not( eq08 ( 3) and eq08 ( 4) ); + + u_eq_15: eq <= not( eq24_b( 0) or eq24_b( 1) ); -- output + + +end; -- xuq_lsu_cmp_cmp36e ARCHITECTURE diff --git a/rel/src/vhdl/work/xuq_lsu_data.vhdl b/rel/src/vhdl/work/xuq_lsu_data.vhdl new file mode 100644 index 0000000..8635daa --- /dev/null +++ b/rel/src/vhdl/work/xuq_lsu_data.vhdl @@ -0,0 +1,4423 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XU LSU Data Rotator +-- + +library ibm, ieee, work, tri, support; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use tri.tri_latches_pkg.all; +use support.power_logic_pkg.all; + +-- ########################################################################################## +-- VHDL Contents +-- 1) 32 Byte Reload Bus +-- 2) 32 Byte Unaligned Rotator +-- 3) Little Endian Support for 2,4,8,16,32 Byte Operations +-- 4) Execution Pipe Store data rotation +-- 5) Byte Enable Generation +-- ########################################################################################## +entity xuq_lsu_data is +generic(expand_type : integer := 2; -- 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) + regmode : integer := 6; -- Register Mode 5 = 32bit, 6 = 64bit + dc_size : natural := 14; -- 2^14 = 16384 Bytes L1 D$ + cl_size : natural := 6; -- 2^6 = 64 Bytes CacheLines + l_endian_m : integer := 1); -- 1 = little endian mode enabled, 0 = little endian mode disabled +port( + + -- Execution Pipe + xu_lsu_rf1_data_act :in std_ulogic; + xu_lsu_rf1_axu_ldst_falign :in std_ulogic; + xu_lsu_ex1_store_data :in std_ulogic_vector(64-(2**REGMODE) to 63); + xu_lsu_ex1_eff_addr :in std_ulogic_vector(64-(dc_size-3) to 63); + xu_lsu_ex1_rotsel_ovrd :in std_ulogic_vector(0 to 4); + ex1_optype32 :in std_ulogic; + ex1_optype16 :in std_ulogic; + ex1_optype8 :in std_ulogic; + ex1_optype4 :in std_ulogic; + ex1_optype2 :in std_ulogic; + ex1_optype1 :in std_ulogic; + ex1_store_instr :in std_ulogic; + ex1_axu_op_val :in std_ulogic; + ex1_saxu_instr :in std_ulogic; + ex1_sdp_instr :in std_ulogic; + ex1_stgpr_instr :in std_ulogic; + + fu_xu_ex2_store_data_val :in std_ulogic; -- EX2 AXU Data is Valid + fu_xu_ex2_store_data :in std_ulogic_vector(0 to 255); -- EX2 AXU Data + + ex3_algebraic :in std_ulogic; -- EX3 Instruction is a Load Algebraic + ex3_data_swap :in std_ulogic; -- EX3 little-endian or byte reversal valid + ex3_thrd_id :in std_ulogic_vector(0 to 3); -- EX3 Thread ID + ex5_dp_data :in std_ulogic_vector(0 to 127); -- EX5 dp data + + -- Debug Data Compare + ex4_load_op_hit :in std_ulogic; + ex4_store_hit :in std_ulogic; + ex4_axu_op_val :in std_ulogic; + spr_dvc1_act :in std_ulogic; + spr_dvc2_act :in std_ulogic; + spr_dvc1_dbg :in std_ulogic_vector(64-(2**regmode) to 63); + spr_dvc2_dbg :in std_ulogic_vector(64-(2**regmode) to 63); + + -- Update Data Array Valid + rel_upd_dcarr_val :in std_ulogic; + + -- Instruction Flush + xu_lsu_ex4_flush :in std_ulogic_vector(0 to 3); -- EX4 Flush Stage + xu_lsu_ex4_flush_local :in std_ulogic_vector(0 to 3); -- EX4 Local Flush Stage + xu_lsu_ex5_flush :in std_ulogic_vector(0 to 3); -- EX5 Flush Stage + + -- Error Inject + xu_pc_err_dcache_parity :out std_ulogic; + pc_xu_inj_dcache_parity :in std_ulogic; + + -- Config Bits + xu_lsu_spr_xucr0_dcdis :in std_ulogic; + spr_xucr0_clkg_ctl_b0 :in std_ulogic; + + -- Reload Pipe + ldq_rel_data_val_early :in std_ulogic; + ldq_rel_algebraic :in std_ulogic; -- Reload requires sign extension + ldq_rel_data_val :in std_ulogic; -- Reload Data is Valid + ldq_rel_ci :in std_ulogic; -- Reload Data is for a cache-inhibited request + ldq_rel_thrd_id :in std_ulogic_vector(0 to 3); -- Reload Thread ID for DVC + ldq_rel_axu_val :in std_ulogic; -- Reload Data is the correct Quadword + ldq_rel_data :in std_ulogic_vector(0 to 255); -- Reload Data + ldq_rel_rot_sel :in std_ulogic_vector(0 to 4); -- Rotator Select + ldq_rel_op_size :in std_ulogic_vector(0 to 5); -- Reload Size of Original Request + ldq_rel_le_mode :in std_ulogic; -- Reload requires Little Endian Swap + ldq_rel_dvc1_en :in std_ulogic; -- Debug Data Value Compare1 Enable + ldq_rel_dvc2_en :in std_ulogic; -- Debug Data Value Compare2 Enable + ldq_rel_beat_crit_qw :in std_ulogic; -- Reload Data is the correct Quadword + ldq_rel_beat_crit_qw_block :in std_ulogic; -- Reload Data had an ECC error + ldq_rel_addr :in std_ulogic_vector(64-(dc_size-3) to 58); -- Reload Array Address + + -- Data Cache Update + dcarr_up_way_addr :in std_ulogic_vector(0 to 2); -- Upper Address of Data Cache + + -- Execution Pipe Outputs + ex4_256st_data :out std_ulogic_vector(0 to 255); -- EX4 Store Data + ex6_ld_par_err :out std_ulogic; -- EX6 Parity Error Detected on the Load Data + lsu_xu_ex6_datc_par_err :out std_ulogic; -- EX6 Parity Error Detected per thread + + --Rotated Data + ex6_xu_ld_data_b :out std_ulogic_vector(64-(2**regmode) to 63); + rel_xu_ld_data :out std_ulogic_vector(64-(2**regmode) to 64+((2**regmode)/8)-1); + xu_fu_ex6_load_data :out std_ulogic_vector(0 to 255); + xu_fu_ex5_load_le :out std_ulogic; -- AXU load/reload was little endian swapped + + -- Debug Data Compare + lsu_xu_rel_dvc_thrd_id :out std_ulogic_vector(0 to 3); -- DVC compared to a Threads Reload + lsu_xu_ex2_dvc1_st_cmp :out std_ulogic_vector(0 to ((2**regmode)/8)-1); + lsu_xu_ex8_dvc1_ld_cmp :out std_ulogic_vector(0 to ((2**regmode)/8)-1); + lsu_xu_rel_dvc1_en :out std_ulogic; + lsu_xu_rel_dvc1_cmp :out std_ulogic_vector(0 to ((2**regmode)/8)-1); + lsu_xu_ex2_dvc2_st_cmp :out std_ulogic_vector(0 to ((2**regmode)/8)-1); + lsu_xu_ex8_dvc2_ld_cmp :out std_ulogic_vector(0 to ((2**regmode)/8)-1); + lsu_xu_rel_dvc2_en :out std_ulogic; + lsu_xu_rel_dvc2_cmp :out std_ulogic_vector(0 to ((2**regmode)/8)-1); + + -- Debug Bus IO + pc_xu_trace_bus_enable :in std_ulogic; + lsudat_debug_mux_ctrls :in std_ulogic_vector(0 to 1); + lsu_xu_data_debug0 :out std_ulogic_vector(0 to 87); + lsu_xu_data_debug1 :out std_ulogic_vector(0 to 87); + lsu_xu_data_debug2 :out std_ulogic_vector(0 to 87); + + --pervasive + vdd :inout power_logic; + gnd :inout power_logic; + vcs :inout power_logic; + nclk :in clk_logic; + pc_xu_ccflush_dc :in std_ulogic; + sg_2 :in std_ulogic; + fce_2 :in std_ulogic; + func_sl_thold_2 :in std_ulogic; + func_nsl_thold_2 :in std_ulogic; + clkoff_dc_b :in std_ulogic; + d_mode_dc :in std_ulogic; + delay_lclkr_dc :in std_ulogic_vector(5 to 5); + mpw1_dc_b :in std_ulogic_vector(5 to 5); + mpw2_dc_b :in std_ulogic; + g6t_clkoff_dc_b :in std_ulogic; + g6t_d_mode_dc :in std_ulogic; + g6t_delay_lclkr_dc :in std_ulogic_vector(0 to 4); + g6t_mpw1_dc_b :in std_ulogic_vector(0 to 4); + g6t_mpw2_dc_b :in std_ulogic; + abst_sl_thold_2 :in std_ulogic; + time_sl_thold_2 :in std_ulogic; + ary_nsl_thold_2 :in std_ulogic; + repr_sl_thold_2 :in std_ulogic; + bolt_sl_thold_2 :in std_ulogic; + bo_enable_2 :in std_ulogic; + an_ac_scan_dis_dc_b :in std_ulogic; + an_ac_scan_diag_dc :in std_ulogic; + + -- G6T ABIST Control + an_ac_lbist_ary_wrt_thru_dc :in std_ulogic; + pc_xu_abist_ena_dc :in std_ulogic; + pc_xu_abist_g6t_bw :in std_ulogic_vector(0 to 1); + pc_xu_abist_di_g6t_2r :in std_ulogic_vector(0 to 3); + pc_xu_abist_wl512_comp_ena :in std_ulogic; + pc_xu_abist_raw_dc_b :in std_ulogic; + pc_xu_abist_dcomp_g6t_2r :in std_ulogic_vector(0 to 3); + pc_xu_abist_raddr_0 :in std_ulogic_vector(1 to 9); + pc_xu_abist_g6t_r_wb :in std_ulogic; + pc_xu_bo_unload :in std_ulogic; + pc_xu_bo_repair :in std_ulogic; + pc_xu_bo_reset :in std_ulogic; + pc_xu_bo_shdata :in std_ulogic; + pc_xu_bo_select :in std_ulogic_vector(5 to 6); + xu_pc_bo_fail :out std_ulogic_vector(5 to 6); + xu_pc_bo_diagout :out std_ulogic_vector(5 to 6); + + -- SCAN Ports + abst_scan_in :in std_ulogic_vector(0 to 1); + time_scan_in :in std_ulogic; + repr_scan_in :in std_ulogic; + abst_scan_out :out std_ulogic_vector(0 to 1); + time_scan_out :out std_ulogic; + repr_scan_out :out std_ulogic; + func_scan_in :in std_ulogic_vector(0 to 2); + func_scan_out :out std_ulogic_vector(0 to 2) +); +-- synopsys translate_off + + +-- synopsys translate_on + +end xuq_lsu_data; +---- +architecture xuq_lsu_data of xuq_lsu_data is + +---------------------------- +-- components +---------------------------- + +---------------------------- +-- constants +---------------------------- +constant rot_max_size :std_ulogic_vector(0 to 5) := "100000"; +constant byte16_size :std_ulogic_vector(0 to 5) := "010000"; +constant uprCClassBit :natural := 64-(dc_size-3); +constant lwrCClassBit :natural := 63-cl_size; + +constant ex3_opsize_offset :natural := 0; +constant ex3_ovrd_rot_offset :natural := ex3_opsize_offset + 6; +constant ex4_le_mode_sel_offset :natural := ex3_ovrd_rot_offset + 1; +constant ex4_be_mode_sel_offset :natural := ex4_le_mode_sel_offset + 16; +constant ex5_load_hit_offset :natural := ex4_be_mode_sel_offset + 16; +constant ex7_load_hit_offset :natural := ex5_load_hit_offset + 1; +constant ex2_st_data_offset :natural := ex7_load_hit_offset + 1; +constant axu_rel_upd_offset :natural := ex2_st_data_offset + (2**regmode); +constant rel_data_val_offset :natural := axu_rel_upd_offset + 16; +constant rel_addr_stg_offset :natural := rel_data_val_offset + 16; +constant rel_addr_offset :natural := rel_addr_stg_offset + 58-uprCClassBit+1; +constant ex5_axu_data_sel_offset :natural := rel_addr_offset + 58-uprCClassBit+1; +constant ex3_stgpr_instr_offset :natural := ex5_axu_data_sel_offset + 3; +constant ex4_stgpr_instr_offset :natural := ex3_stgpr_instr_offset + 1; +constant ex3_sdp_instr_offset :natural := ex4_stgpr_instr_offset + 1; +constant ex4_sdp_instr_offset :natural := ex3_sdp_instr_offset + 1; +constant ex5_sdp_instr_offset :natural := ex4_sdp_instr_offset + 1; +constant rot_addr_offset :natural := ex5_sdp_instr_offset + 1; +constant rot_sel_non_le_offset :natural := rot_addr_offset + 5; +constant ex5_dvc1_en_offset :natural := rot_sel_non_le_offset + 5; +constant ex6_dvc1_en_offset :natural := ex5_dvc1_en_offset + 1; +constant ex7_dvc1_en_offset :natural := ex6_dvc1_en_offset + 1; +constant rel_dvc1_val_offset :natural := ex7_dvc1_en_offset + ((2**regmode)/8); +constant ex8_ld_dvc1_cmp_offset :natural := rel_dvc1_val_offset + 1; +constant rel_dvc1_val_stg_offset :natural := ex8_ld_dvc1_cmp_offset + ((2**regmode)/8); +constant rel_dvc1_val_stg2_offset :natural := rel_dvc1_val_stg_offset + 1; +constant rel_dvc2_val_stg_offset :natural := rel_dvc1_val_stg2_offset + 1; +constant rel_dvc2_val_stg2_offset :natural := rel_dvc2_val_stg_offset + 1; +constant ex5_dvc2_en_offset :natural := rel_dvc2_val_stg2_offset + 1; +constant ex6_dvc2_en_offset :natural := ex5_dvc2_en_offset + 1; +constant ex7_dvc2_en_offset :natural := ex6_dvc2_en_offset + 1; +constant rel_dvc2_val_offset :natural := ex7_dvc2_en_offset + ((2**regmode)/8); +constant ex8_ld_dvc2_cmp_offset :natural := rel_dvc2_val_offset + 1; +constant ex2_optype32_offset :natural := ex8_ld_dvc2_cmp_offset + ((2**regmode)/8); +constant ex2_optype16_offset :natural := ex2_optype32_offset + 1; +constant ex2_optype8_offset :natural := ex2_optype16_offset + 1; +constant ex2_optype4_offset :natural := ex2_optype8_offset + 1; +constant ex2_optype2_offset :natural := ex2_optype4_offset + 1; +constant ex2_optype1_offset :natural := ex2_optype2_offset + 1; +constant ex2_p_addr_offset :natural := ex2_optype1_offset + 1; +constant frc_p_addr_offset :natural := ex2_p_addr_offset + 64-uprCClassBit; +constant ex2_store_instr_offset :natural := frc_p_addr_offset + 6; +constant ex2_axu_op_val_offset :natural := ex2_store_instr_offset + 1; +constant ex4_axu_op_val_offset :natural := ex2_axu_op_val_offset + 1; +constant ex2_xu_cmp_val_offset :natural := ex4_axu_op_val_offset + 1; +constant ex2_saxu_instr_offset :natural := ex2_xu_cmp_val_offset + (2**regmode)/8; +constant ex2_sdp_instr_offset :natural := ex2_saxu_instr_offset + 1; +constant ex2_stgpr_instr_offset :natural := ex2_sdp_instr_offset + 1; +constant ex4_saxu_instr_offset :natural := ex2_stgpr_instr_offset + 1; +constant ex4_algebraic_offset :natural := ex4_saxu_instr_offset + 1; +constant ex2_ovrd_rot_sel_offset :natural := ex4_algebraic_offset + 1; +constant ex4_p_addr_offset :natural := ex2_ovrd_rot_sel_offset + 5; +constant spr_xucr0_dcdis_offset :natural := ex4_p_addr_offset + 64-uprCClassBit; +constant clkg_ctl_override_offset :natural := spr_xucr0_dcdis_offset + 1; +constant rel_dvc_tid_stg_offset :natural := clkg_ctl_override_offset + 1; +constant inj_dcache_parity_offset :natural := rel_dvc_tid_stg_offset + 4; +constant ex5_stgpr_dp_instr_offset :natural := inj_dcache_parity_offset + 1; +constant ex6_stgpr_dp_instr_offset :natural := ex5_stgpr_dp_instr_offset + 1; +constant ex6_stgpr_dp_data_offset :natural := ex6_stgpr_dp_instr_offset + 1; +constant ex5_rel_le_mode_offset :natural := ex6_stgpr_dp_data_offset + 128; +constant ex1_ldst_falign_offset :natural := ex5_rel_le_mode_offset + 1; +constant ex5_thrd_id_offset :natural := ex1_ldst_falign_offset + 1; +constant axu_rel_val_stg1_offset :natural := ex5_thrd_id_offset + 4; +constant axu_rel_val_stg2_offset :natural := axu_rel_val_stg1_offset + 1; +constant axu_rel_val_stg3_offset :natural := axu_rel_val_stg2_offset + 1; +constant rel_256ld_data_stg2_offset :natural := axu_rel_val_stg3_offset + 1; +constant rel_axu_le_val_offset :natural := rel_256ld_data_stg2_offset + 256; +constant rel_axu_le_val_stg1_offset :natural := rel_axu_le_val_offset + 1; +constant dcarr_wren_offset :natural := rel_axu_le_val_stg1_offset + 1; +constant dat_dbg_arr_offset :natural := dcarr_wren_offset + 1; +constant ld_alg_le_sel_offset :natural := dat_dbg_arr_offset + 13; +constant ex1_stg_act_offset :natural := ld_alg_le_sel_offset + 5; +constant ex2_stg_act_offset :natural := ex1_stg_act_offset + 1; +constant ex3_stg_act_offset :natural := ex2_stg_act_offset + 1; +constant ex4_stg_act_offset :natural := ex3_stg_act_offset + 1; +constant ex5_stg_act_offset :natural := ex4_stg_act_offset + 1; +constant ex6_stg_act_offset :natural := ex5_stg_act_offset + 1; +constant rel1_stg_act_offset :natural := ex6_stg_act_offset + 1; +constant rel2_stg_act_offset :natural := rel1_stg_act_offset + 1; +constant rel3_stg_act_offset :natural := rel2_stg_act_offset + 1; +constant rel4_stg_act_offset :natural := rel3_stg_act_offset + 1; +constant rel5_stg_act_offset :natural := rel4_stg_act_offset + 1; +constant rel2_ex2_stg_act_offset :natural := rel5_stg_act_offset + 1; +constant rel3_ex3_stg_act_offset :natural := rel2_ex2_stg_act_offset + 1; +constant rel4_ex4_stg_act_offset :natural := rel3_ex3_stg_act_offset + 1; +constant ex8_ld_par_err_offset :natural := rel4_ex4_stg_act_offset + 1; +constant my_spare_latches_offset :natural := ex8_ld_par_err_offset + 1; +constant scan_right0 :natural := my_spare_latches_offset + 8 - 1; +constant l1dcar_offset :natural := 0; +constant l1dcld_offset :natural := l1dcar_offset + 1; +constant rel_data_offset :natural := l1dcld_offset + 1; +constant rel_algebraic_offset :natural := rel_data_offset + 256; +constant rel_rot_sel_offset :natural := rel_algebraic_offset + 1; +constant rel_op_size_offset :natural := rel_rot_sel_offset + 5; +constant rel_le_mode_offset :natural := rel_op_size_offset + 6; +constant rel_dvc1_en_offset :natural := rel_le_mode_offset + 1; +constant rel_dvc2_en_offset :natural := rel_dvc1_en_offset + 1; +constant rel_upd_gpr_offset :natural := rel_dvc2_en_offset + 1; +constant rel_axu_val_offset :natural := rel_upd_gpr_offset + 1; +constant rel_ci_offset :natural := rel_axu_val_offset + 1; +constant rel_thrd_id_offset :natural := rel_ci_offset + 1; +constant rel_data_val_stg_offset :natural := rel_thrd_id_offset + 4; +constant spr_dvc1_dbg_offset :natural := rel_data_val_stg_offset + 1; +constant spr_dvc2_dbg_offset :natural := spr_dvc1_dbg_offset + (2**regmode); +constant trace_bus_enable_offset :natural := spr_dvc2_dbg_offset + (2**regmode); +constant dat_debug_mux_ctrls_offset :natural := trace_bus_enable_offset + 1; +constant dat_dbg_st_dat_offset :natural := dat_debug_mux_ctrls_offset + 2; +constant scan_right1 :natural := dat_dbg_st_dat_offset + 64 - 1; + +---------------------------- +-- signals +---------------------------- +signal op_size :std_ulogic_vector(0 to 5); +signal ex3_opsize_d :std_ulogic_vector(0 to 5); +signal ex3_opsize_q :std_ulogic_vector(0 to 5); +signal rot_addr :std_ulogic_vector(0 to 5); +signal rot_addr_le :std_ulogic_vector(0 to 5); +signal rot_size :std_ulogic_vector(0 to 5); +signal rot_size_le :std_ulogic_vector(0 to 5); +signal ex3_le_mode :std_ulogic; +signal ex3_be_mode :std_ulogic; +signal ex4_le_mode_d :std_ulogic; +signal ex4_le_mode_q :std_ulogic; +signal ex4_le_mode_sel_d :std_ulogic_vector(0 to 15); +signal ex4_le_mode_sel_q :std_ulogic_vector(0 to 15); +signal ex4_be_mode_sel_d :std_ulogic_vector(0 to 15); +signal ex4_be_mode_sel_q :std_ulogic_vector(0 to 15); +signal st_256data :std_ulogic_vector(0 to 255); +signal ex3_byte_en :std_ulogic_vector(0 to 31); +signal ex5_ld_data :std_ulogic_vector(0 to 255); +signal ex5_ld_data_par :std_ulogic_vector(0 to 31); +signal ex6_par_chk_val :std_ulogic; +signal ex2_st_data_fixup :std_ulogic_vector(0 to 127); +signal ex2_st_data_d :std_ulogic_vector(64-(2**regmode) to 63); +signal ex2_st_data_q :std_ulogic_vector(64-(2**regmode) to 63); +signal fu_ex2_store_data_val :std_ulogic; +signal fu_ex2_store_data :std_ulogic_vector(0 to 255); +signal rel_256ld_data :std_ulogic_vector(0 to 255); +signal rel_64ld_data :std_ulogic_vector(64-(2**regmode) to 63); +signal axu_rel_upd_d :std_ulogic_vector(0 to 15); +signal axu_rel_upd_q :std_ulogic_vector(0 to 15); +signal ex6_rot_sel :std_ulogic_vector(0 to 31); +signal rot_sel_non_le :std_ulogic_vector(0 to 5); +signal be_st_rot_sel :std_ulogic_vector(1 to 5); +signal le_st_rot_sel :std_ulogic_vector(0 to 3); +signal ex4_ld_rot_sel :std_ulogic_vector(1 to 5); +signal st_ovrd_rot_sel :std_ulogic_vector(0 to 4); +signal ex3_st_rot_sel_d :std_ulogic_vector(0 to 4); +signal ex3_st_rot_sel_q :std_ulogic_vector(0 to 4); +signal rel_algebraic :std_ulogic; +signal rel_data :std_ulogic_vector(0 to 255); +signal rel_data_val :std_ulogic_vector(0 to 15); +signal rel_upd_gpr_d :std_ulogic; +signal rel_upd_gpr_q :std_ulogic; +signal rel_rot_sel :std_ulogic_vector(0 to 4); +signal rel_op_size :std_ulogic_vector(0 to 5); +signal rel_le_mode :std_ulogic; +signal rel_algebraic_d :std_ulogic; +signal rel_data_val_d :std_ulogic_vector(0 to 15); +signal rel_data_d :std_ulogic_vector(0 to 255); +signal rel_rot_sel_d :std_ulogic_vector(0 to 4); +signal rel_op_size_d :std_ulogic_vector(0 to 5); +signal rel_le_mode_d :std_ulogic; +signal rel_addr_d :std_ulogic_vector(uprCClassBit to 58); +signal rel_algebraic_q :std_ulogic; +signal rel_data_val_q :std_ulogic_vector(0 to 15); +signal rel_data_q :std_ulogic_vector(0 to 255); +signal rel_rot_sel_q :std_ulogic_vector(0 to 4); +signal rel_op_size_q :std_ulogic_vector(0 to 5); +signal rel_le_mode_q :std_ulogic; +signal rel_addr_q :std_ulogic_vector(uprCClassBit to 58); +signal rel_xu_ld_par :std_ulogic_vector(0 to 7); +signal rel_ex2_data :std_ulogic_vector(0 to 255); +signal rel_ex3_data_d :std_ulogic_vector(0 to 255); +signal rel_ex3_data_q :std_ulogic_vector(0 to 255); +signal rel_addr_stg_d :std_ulogic_vector(uprCClassBit to 58); +signal rel_addr_stg_q :std_ulogic_vector(uprCClassBit to 58); +signal rel_data_val_stg_d :std_ulogic; +signal rel_data_val_stg_q :std_ulogic; +signal rel_data_val_stg_dly_d :std_ulogic; +signal rel_data_val_stg_dly_q :std_ulogic; +signal ex4_parity_gen :std_ulogic_vector(0 to 31); +signal non_le_byte_bit0 :std_ulogic_vector(0 to 31); +signal le_byte_bit0 :std_ulogic_vector(0 to 31); +signal alg_bit_sel :std_ulogic_vector(0 to 4); +signal alg_byte :std_ulogic_vector(0 to 31); +signal algebraic_bit :std_ulogic; +signal rel_alg_bit_d :std_ulogic; +signal rel_alg_bit_q :std_ulogic; +signal ex2_ovrd_rot :std_ulogic; +signal ex3_ovrd_rot_d :std_ulogic; +signal ex3_ovrd_rot_q :std_ulogic; +signal ex3_sdp_instr_d :std_ulogic; +signal ex3_sdp_instr_q :std_ulogic; +signal ex4_sdp_instr_d :std_ulogic; +signal ex4_sdp_instr_q :std_ulogic; +signal ex5_sdp_instr_d :std_ulogic; +signal ex5_sdp_instr_q :std_ulogic; +signal ex3_stgpr_instr_d :std_ulogic; +signal ex3_stgpr_instr_q :std_ulogic; +signal ex4_stgpr_instr_d :std_ulogic; +signal ex4_stgpr_instr_q :std_ulogic; +signal ex5_stgpr_dp_instr_d :std_ulogic; +signal ex5_stgpr_dp_instr_q :std_ulogic; +signal ex6_stgpr_dp_instr_d :std_ulogic; +signal ex6_stgpr_dp_instr_q :std_ulogic; +signal ex6_stgpr_dp_instr_q_b :std_ulogic; +signal ex4_stgpr_data :std_ulogic_vector(64-(2**regmode) to 63); +signal ex5_stgpr_data_d :std_ulogic_vector(64-(2**regmode) to 63); +signal ex5_stgpr_data_q :std_ulogic_vector(64-(2**regmode) to 63); +signal ex6_stgpr_dp_data_d :std_ulogic_vector(0 to 127); +signal ex6_stgpr_dp_data_q :std_ulogic_vector(0 to 127); +signal rel_axu_le_mode :std_ulogic; +signal rot_addr_d :std_ulogic_vector(1 to 5); +signal rot_addr_q :std_ulogic_vector(1 to 5); +signal ex4_rot_addr_d :std_ulogic_vector(1 to 5); +signal ex4_rot_addr_q :std_ulogic_vector(1 to 5); +signal rot_sel_non_le_d :std_ulogic_vector(1 to 5); +signal rot_sel_non_le_q :std_ulogic_vector(1 to 5); +signal ex4_rot_sel_non_le_d :std_ulogic_vector(1 to 5); +signal ex4_rot_sel_non_le_q :std_ulogic_vector(1 to 5); +signal rel_axu_val_d :std_ulogic; +signal rel_axu_val_q :std_ulogic; +signal rel_ci_d :std_ulogic; +signal rel_ci_q :std_ulogic; +signal rel_ci_dly_d :std_ulogic; +signal rel_ci_dly_q :std_ulogic; +signal ex2_st_dvc1_cmp_d :std_ulogic_vector((64-(2**regmode))/8 to 7); +signal ex2_st_dvc1_cmp_q :std_ulogic_vector((64-(2**regmode))/8 to 7); +signal ex2_st_dvc2_cmp_d :std_ulogic_vector((64-(2**regmode))/8 to 7); +signal ex2_st_dvc2_cmp_q :std_ulogic_vector((64-(2**regmode))/8 to 7); +signal ex8_ld_dvc1_cmp_d :std_ulogic_vector((64-(2**regmode))/8 to 7); +signal ex8_ld_dvc1_cmp_q :std_ulogic_vector((64-(2**regmode))/8 to 7); +signal ex8_ld_dvc2_cmp_d :std_ulogic_vector((64-(2**regmode))/8 to 7); +signal ex8_ld_dvc2_cmp_q :std_ulogic_vector((64-(2**regmode))/8 to 7); +signal rel_dvc1_cmp_d :std_ulogic_vector((64-(2**regmode))/8 to 7); +signal rel_dvc1_cmp_q :std_ulogic_vector((64-(2**regmode))/8 to 7); +signal rel_dvc2_cmp_d :std_ulogic_vector((64-(2**regmode))/8 to 7); +signal rel_dvc2_cmp_q :std_ulogic_vector((64-(2**regmode))/8 to 7); +signal rel_dvc1_val_stg_d :std_ulogic; +signal rel_dvc1_val_stg_q :std_ulogic; +signal rel_dvc1_val_stg2_d :std_ulogic; +signal rel_dvc1_val_stg2_q :std_ulogic; +signal rel_dvc2_val_stg_d :std_ulogic; +signal rel_dvc2_val_stg_q :std_ulogic; +signal rel_dvc2_val_stg2_d :std_ulogic; +signal rel_dvc2_val_stg2_q :std_ulogic; +signal ex5_dvc1_en_d :std_ulogic; +signal ex5_dvc1_en_q :std_ulogic; +signal ex6_dvc1_en_d :std_ulogic; +signal ex6_dvc1_en_q :std_ulogic; +signal ex7_dvc1_en_d :std_ulogic_vector((64-(2**regmode))/8 to 7); +signal ex7_dvc1_en_q :std_ulogic_vector((64-(2**regmode))/8 to 7); +signal ex5_dvc2_en_d :std_ulogic; +signal ex5_dvc2_en_q :std_ulogic; +signal ex6_dvc2_en_d :std_ulogic; +signal ex6_dvc2_en_q :std_ulogic; +signal ex7_dvc2_en_d :std_ulogic_vector((64-(2**regmode))/8 to 7); +signal ex7_dvc2_en_q :std_ulogic_vector((64-(2**regmode))/8 to 7); +signal rel_dvc1_en_d :std_ulogic; +signal rel_dvc1_en_q :std_ulogic; +signal rel_dvc2_en_d :std_ulogic; +signal rel_dvc2_en_q :std_ulogic; +signal rel_dvc1_val_d :std_ulogic; +signal rel_dvc1_val_q :std_ulogic; +signal rel_dvc2_val_d :std_ulogic; +signal rel_dvc2_val_q :std_ulogic; +signal ex1_op_size :std_ulogic_vector(2 to 5); +signal ex1_st_byte_mask :std_ulogic_vector(0 to 7); +signal ex2_optype32_d :std_ulogic; +signal ex2_optype32_q :std_ulogic; +signal ex2_optype16_d :std_ulogic; +signal ex2_optype16_q :std_ulogic; +signal ex2_optype8_d :std_ulogic; +signal ex2_optype8_q :std_ulogic; +signal ex2_optype4_d :std_ulogic; +signal ex2_optype4_q :std_ulogic; +signal ex2_optype2_d :std_ulogic; +signal ex2_optype2_q :std_ulogic; +signal ex2_optype1_d :std_ulogic; +signal ex2_optype1_q :std_ulogic; +signal ex2_p_addr_d :std_ulogic_vector(uprCClassBit to 63); +signal ex2_p_addr_q :std_ulogic_vector(uprCClassBit to 63); +signal ex3_fu_st_val_d :std_ulogic; +signal ex3_fu_st_val_q :std_ulogic; +signal frc_p_addr_d :std_ulogic_vector(58 to 63); +signal frc_p_addr_q :std_ulogic_vector(58 to 63); +signal ex2_store_instr_d :std_ulogic; +signal ex2_store_instr_q :std_ulogic; +signal ex3_store_instr_d :std_ulogic; +signal ex3_store_instr_q :std_ulogic; +signal ex2_axu_op_val_d :std_ulogic; +signal ex2_axu_op_val_q :std_ulogic; +signal ex3_axu_op_val_d :std_ulogic; +signal ex3_axu_op_val_q :std_ulogic; +signal ex4_axu_op_val_d :std_ulogic; +signal ex4_axu_op_val_q :std_ulogic; +signal ex2_xu_cmp_val_d :std_ulogic_vector((64-(2**regmode))/8 to 7); +signal ex2_xu_cmp_val_q :std_ulogic_vector((64-(2**regmode))/8 to 7); +signal ex2_saxu_instr_d :std_ulogic; +signal ex2_saxu_instr_q :std_ulogic; +signal ex2_sdp_instr_d :std_ulogic; +signal ex2_sdp_instr_q :std_ulogic; +signal ex2_stgpr_instr_d :std_ulogic; +signal ex2_stgpr_instr_q :std_ulogic; +signal ex3_saxu_instr_d :std_ulogic; +signal ex3_saxu_instr_q :std_ulogic; +signal ex4_saxu_instr_d :std_ulogic; +signal ex4_saxu_instr_q :std_ulogic; +signal ex4_algebraic_d :std_ulogic; +signal ex4_algebraic_q :std_ulogic; +signal ex2_ovrd_rot_sel_d :std_ulogic_vector(0 to 4); +signal ex2_ovrd_rot_sel_q :std_ulogic_vector(0 to 4); +signal ex3_p_addr_d :std_ulogic_vector(uprCClassBit to 63); +signal ex3_p_addr_q :std_ulogic_vector(uprCClassBit to 63); +signal ex4_p_addr_d :std_ulogic_vector(uprCClassBit to 63); +signal ex4_p_addr_q :std_ulogic_vector(uprCClassBit to 63); +signal rel_ex2_par_gen :std_ulogic_vector(0 to 31); +signal rel_ex3_par_gen_d :std_ulogic_vector(0 to 31); +signal rel_ex3_par_gen_q :std_ulogic_vector(0 to 31); +signal ex2_fu_data_val :std_ulogic; +signal rel_xu_data :std_ulogic_vector(0 to 255); +signal spr_xucr0_dcdis_d :std_ulogic; +signal spr_xucr0_dcdis_q :std_ulogic; +signal clkg_ctl_override_d :std_ulogic; +signal clkg_ctl_override_q :std_ulogic; +signal rel_data_val_wren :std_ulogic; +signal rel_thrd_id_d :std_ulogic_vector(0 to 3); +signal rel_thrd_id_q :std_ulogic_vector(0 to 3); +signal rel_dvc_thrd_id_d :std_ulogic_vector(0 to 3); +signal rel_dvc_thrd_id_q :std_ulogic_vector(0 to 3); +signal rel_dvc_tid_stg_d :std_ulogic_vector(0 to 3); +signal rel_dvc_tid_stg_q :std_ulogic_vector(0 to 3); +signal rel_dvc_tid_stg2_d :std_ulogic_vector(0 to 3); +signal rel_dvc_tid_stg2_q :std_ulogic_vector(0 to 3); +signal dont_do_this :std_ulogic_vector(0 to 63); +signal ex6_xld_data :std_ulogic_vector(0 to 63); +signal ex6_xld_data_b :std_ulogic_vector(0 to 63); +signal ex6_ld_alg_bit :std_ulogic_vector(0 to 5); +signal ex6_ld_dvc_byte_mask :std_ulogic_vector((64-(2**regmode))/8 to 7); +signal ld_swzl_data :std_ulogic_vector(0 to 255); +signal axu_data_sel :std_ulogic_vector(0 to 1); +signal ex5_axu_data_sel_d :std_ulogic_vector(0 to 2); +signal ex5_axu_data_sel_q :std_ulogic_vector(0 to 2); +signal ex6_axu_data_sel_d :std_ulogic_vector(0 to 47); +signal ex6_axu_data_sel_q :std_ulogic_vector(0 to 47); +signal inj_dcache_parity_d :std_ulogic; +signal inj_dcache_parity_q :std_ulogic; +signal ex5_rel_le_mode_d :std_ulogic; +signal ex5_rel_le_mode_q :std_ulogic; +signal ex1_ldst_falign_d :std_ulogic; +signal ex1_ldst_falign_q :std_ulogic; +signal ex1_frc_align32 :std_ulogic; +signal ex1_frc_align16 :std_ulogic; +signal ex1_frc_align8 :std_ulogic; +signal ex1_frc_align4 :std_ulogic; +signal ex1_frc_align2 :std_ulogic; +signal ex4_stg_flush :std_ulogic; +signal ex5_stg_flush :std_ulogic; +signal ex4_load_hit :std_ulogic; +signal ex5_load_hit_d :std_ulogic; +signal ex5_load_hit_q :std_ulogic; +signal ex6_load_hit_d :std_ulogic; +signal ex6_load_hit_q :std_ulogic; +signal ex7_load_hit_d :std_ulogic; +signal ex7_load_hit_q :std_ulogic; +signal ex4_thrd_id_d :std_ulogic_vector(0 to 3); +signal ex4_thrd_id_q :std_ulogic_vector(0 to 3); +signal ex5_thrd_id_d :std_ulogic_vector(0 to 3); +signal ex5_thrd_id_q :std_ulogic_vector(0 to 3); +signal axu_rel_val_stg1_d :std_ulogic; +signal axu_rel_val_stg1_q :std_ulogic; +signal axu_rel_val_stg2_d :std_ulogic; +signal axu_rel_val_stg2_q :std_ulogic; +signal axu_rel_val_stg3_d :std_ulogic; +signal axu_rel_val_stg3_q :std_ulogic; +signal rel_data_rot_sel :std_ulogic; +signal rel_256ld_data_stg1_d :std_ulogic_vector(0 to 255); +signal rel_256ld_data_stg1_q :std_ulogic_vector(0 to 255); +signal rel_256ld_data_stg2_d :std_ulogic_vector(0 to 255); +signal rel_256ld_data_stg2_q :std_ulogic_vector(0 to 255); +signal rel_axu_le_val_d :std_ulogic; +signal rel_axu_le_val_q :std_ulogic; +signal rel_axu_le_val_stg1_d :std_ulogic; +signal rel_axu_le_val_stg1_q :std_ulogic; +signal dcarr_rd_data :std_ulogic_vector(0 to 287); +signal dcarr_bw :std_ulogic_vector(0 to 287); +signal dcarr_addr :std_ulogic_vector(uprCClassBit to 58); +signal dcarr_wr_data :std_ulogic_vector(0 to 287); +signal dcarr_bw_dly :std_ulogic_vector(0 to 31); +signal dcarr_wren_b :std_ulogic; +signal dcarr_wren :std_ulogic; +signal dcarr_wren_d :std_ulogic; +signal dcarr_wren_q :std_ulogic; +signal ex4_store_hit_early_gate :std_ulogic; +signal rel_ex4_store_hit :std_ulogic; +signal ex4_thrd_id_mask :std_ulogic_vector(0 to 3); +signal dat_dbg_arr_d :std_ulogic_vector(0 to 12); +signal dat_dbg_arr_q :std_ulogic_vector(0 to 12); +signal ex4_256st_dataFixUp :std_ulogic_vector(0 to 255); +signal alg_bit_le_sel :std_ulogic_vector(0 to 5); +signal ex4_ld_alg_sel :std_ulogic_vector(1 to 5); +signal ld_alg_le_sel_d :std_ulogic_vector(1 to 5); +signal ld_alg_le_sel_q :std_ulogic_vector(1 to 5); +signal ex4_ld_alg_le_sel_d :std_ulogic_vector(1 to 5); +signal ex4_ld_alg_le_sel_q :std_ulogic_vector(1 to 5); +signal ex6_axu_rel_gpr_data_sel :std_ulogic_vector(0 to 15); +signal ex6_axu_rel_gpr_data :std_ulogic_vector(0 to 127); +signal ex7_ld_par_err :std_ulogic_vector(0 to 1); +signal ex8_ld_par_err_d :std_ulogic; +signal ex8_ld_par_err_q :std_ulogic; +signal dcache_parity :std_ulogic_vector(0 to 0); +signal ex6_ld_par_err_int :std_ulogic; +signal spr_dvc1_dbg_d :std_ulogic_vector(64-(2**regmode) to 63); +signal spr_dvc1_dbg_q :std_ulogic_vector(64-(2**regmode) to 63); +signal spr_dvc2_dbg_d :std_ulogic_vector(64-(2**regmode) to 63); +signal spr_dvc2_dbg_q :std_ulogic_vector(64-(2**regmode) to 63); +signal ex7_xld_data_d :std_ulogic_vector(64-(2**regmode) to 63); +signal ex7_xld_data_q :std_ulogic_vector(64-(2**regmode) to 63); +signal ex4_stg_flush_lcl_b :std_ulogic_vector(0 to 3); +signal ex4_flush_t01_b :std_ulogic; +signal ex4_flush_t23_b :std_ulogic; +signal rel_ex4_upd_en :std_ulogic; +signal ex1_stg_act_d :std_ulogic; +signal ex1_stg_act_q :std_ulogic; +signal ex2_stg_act_d :std_ulogic; +signal ex2_stg_act_q :std_ulogic; +signal ex3_stg_act_d :std_ulogic; +signal ex3_stg_act_q :std_ulogic; +signal ex4_stg_act_d :std_ulogic; +signal ex4_stg_act_q :std_ulogic; +signal ex5_stg_act_d :std_ulogic; +signal ex5_stg_act_q :std_ulogic; +signal ex6_stg_act_d :std_ulogic; +signal ex6_stg_act_q :std_ulogic; +signal rel1_stg_act_d :std_ulogic; +signal rel1_stg_act_q :std_ulogic; +signal rel2_stg_act_d :std_ulogic; +signal rel2_stg_act_q :std_ulogic; +signal rel3_stg_act_d :std_ulogic; +signal rel3_stg_act_q :std_ulogic; +signal rel4_stg_act_d :std_ulogic; +signal rel4_stg_act_q :std_ulogic; +signal rel5_stg_act_d :std_ulogic; +signal rel5_stg_act_q :std_ulogic; +signal rel2_ex2_stg_act :std_ulogic; +signal rel2_ex2_stg_act_d :std_ulogic; +signal rel2_ex2_stg_act_q :std_ulogic; +signal rel3_ex3_stg_act :std_ulogic; +signal rel3_ex3_stg_act_d :std_ulogic; +signal rel3_ex3_stg_act_q :std_ulogic; +signal rel4_ex4_stg_act :std_ulogic; +signal rel4_ex4_stg_act_d :std_ulogic; +signal rel4_ex4_stg_act_q :std_ulogic; +signal rel_dvc_byte_mask :std_ulogic_vector((64-(2**regmode))/8 to 7); +signal trace_bus_enable_q :std_ulogic; +signal dat_debug_mux_ctrls_q :std_ulogic_vector(0 to 1); +signal rel_ex3_store_data0 :std_ulogic_vector(0 to 63); +signal rel_ex3_store_data1 :std_ulogic_vector(0 to 63); +signal rel_ex3_store_data2 :std_ulogic_vector(0 to 63); +signal rel_ex3_store_data3 :std_ulogic_vector(0 to 63); +signal dat_dbg_st_dat_d :std_ulogic_vector(0 to 63); +signal dat_dbg_st_dat_q :std_ulogic_vector(0 to 63); +signal dat_dbg_ld_dat :std_ulogic_vector(0 to 63); +signal abst_scan_in_q :std_ulogic_vector(0 to 1); +signal abst_scan_out_int :std_ulogic_vector(0 to 1); +signal abst_scan_out_q :std_ulogic_vector(0 to 1); +signal time_scan_in_q :std_ulogic; +signal time_scan_out_int :std_ulogic; +signal time_scan_out_q :std_ulogic; +signal repr_scan_in_q :std_ulogic; +signal repr_scan_out_int :std_ulogic; +signal repr_scan_out_q :std_ulogic; +signal func_scan_in_q :std_ulogic_vector(0 to 2); +signal func_scan_in_2_q :std_ulogic_vector(0 to 2); +signal func_scan_out_int :std_ulogic_vector(0 to 2); +signal func_scan_out_q :std_ulogic_vector(0 to 2); +signal func_scan_out_2_q :std_ulogic_vector(0 to 2); +signal tiup :std_ulogic; +signal tidn :std_ulogic; +signal func_nsl_thold_1 :std_ulogic; +signal func_sl_thold_1 :std_ulogic; +signal sg_1 :std_ulogic; +signal fce_1 :std_ulogic; +signal func_nsl_thold_0 :std_ulogic; +signal func_sl_thold_0 :std_ulogic; +signal sg_0 :std_ulogic; +signal fce_0 :std_ulogic; +signal func_sl_force :std_ulogic; +signal func_sl_thold_0_b :std_ulogic; +signal func_nsl_force :std_ulogic; +signal func_nsl_thold_0_b :std_ulogic; +signal siv0 :std_ulogic_vector(0 to scan_right0); +signal sov0 :std_ulogic_vector(0 to scan_right0); +signal siv1 :std_ulogic_vector(0 to scan_right1); +signal sov1 :std_ulogic_vector(0 to scan_right1); +signal abist_siv :std_ulogic_vector(0 to 21); +signal abist_sov :std_ulogic_vector(0 to 21); +signal abst_sl_thold_1 :std_ulogic; +signal time_sl_thold_1 :std_ulogic; +signal ary_nsl_thold_1 :std_ulogic; +signal repr_sl_thold_1 :std_ulogic; +signal bolt_sl_thold_1 :std_ulogic; +signal abst_sl_thold_0 :std_ulogic; +signal time_sl_thold_0 :std_ulogic; +signal ary_nsl_thold_0 :std_ulogic; +signal repr_sl_thold_0 :std_ulogic; +signal bolt_sl_thold_0 :std_ulogic; +signal abst_sl_thold_0_b :std_ulogic; +signal abst_sl_force :std_ulogic; +signal pc_xu_abist_g6t_bw_q :std_ulogic_vector(0 to 1); +signal pc_xu_abist_di_g6t_2r_q :std_ulogic_vector(0 to 3); +signal pc_xu_abist_wl512_comp_ena_q :std_ulogic; +signal pc_xu_abist_dcomp_g6t_2r_q :std_ulogic_vector(0 to 3); +signal pc_xu_abist_raddr_0_q :std_ulogic_vector(0 to 8); +signal pc_xu_abist_g6t_r_wb_q :std_ulogic; +signal slat_force :std_ulogic; +signal abst_slat_thold_b :std_ulogic; +signal abst_slat_d2clk :std_ulogic; +signal abst_slat_lclk :clk_logic; +signal time_slat_thold_b :std_ulogic; +signal time_slat_d2clk :std_ulogic; +signal time_slat_lclk :clk_logic; +signal repr_slat_thold_b :std_ulogic; +signal repr_slat_d2clk :std_ulogic; +signal repr_slat_lclk :clk_logic; +signal func_slat_thold_b :std_ulogic; +signal func_slat_d2clk :std_ulogic; +signal func_slat_lclk :clk_logic; +signal my_spare_latches_d :std_ulogic_vector(0 to 7); +signal my_spare_latches_q :std_ulogic_vector(0 to 7); +signal my_spare0_lclk :clk_logic; +signal my_spare0_d1clk :std_ulogic; +signal my_spare0_d2clk :std_ulogic; + +signal ex6_frot_b, ex6_fdat, ex6_rot_sel_bus, ex6_axu_oth_b :std_ulogic_vector(0 to 255); +signal ex6_rot_d_b, ex6_rot_d, ex6_xld_rot_b, ex6_xld_oth_b :std_ulogic_vector(0 to 63); +signal ex6_xld_sgnx_b , ex6_xld_sgn_b, ex6_xld_sgn :std_ulogic_vector(0 to 5); + + + + + + + +begin + +tiup <= '1'; +tidn <= '0'; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Act Signals going to all Latches +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +ex1_stg_act_d <= xu_lsu_rf1_data_act or clkg_ctl_override_q; +ex2_stg_act_d <= ex1_stg_act_q; +ex3_stg_act_d <= ex2_stg_act_q; +ex4_stg_act_d <= ex3_stg_act_q; +ex5_stg_act_d <= ex4_stg_act_q; +ex6_stg_act_d <= ex5_stg_act_q; +rel1_stg_act_d <= ldq_rel_data_val_early or clkg_ctl_override_q; +rel2_stg_act_d <= ldq_rel_ci or ldq_rel_data_val or clkg_ctl_override_q; +rel3_stg_act_d <= rel2_stg_act_q; +rel4_stg_act_d <= rel3_stg_act_q; +rel5_stg_act_d <= rel4_stg_act_q; +rel2_ex2_stg_act_d <= rel2_stg_act_d or ex2_stg_act_d; +rel3_ex3_stg_act_d <= rel3_stg_act_d or ex3_stg_act_d; +rel4_ex4_stg_act_d <= rel4_stg_act_d or ex4_stg_act_d; + +rel2_ex2_stg_act <= rel2_ex2_stg_act_q; +rel3_ex3_stg_act <= rel3_ex3_stg_act_q; +rel4_ex4_stg_act <= rel4_ex4_stg_act_q; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Inputs +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +rel_algebraic_d <= ldq_rel_algebraic; +rel_data_d <= ldq_rel_data; +rel_rot_sel_d <= ldq_rel_rot_sel; +rel_op_size_d <= ldq_rel_op_size; +rel_le_mode_d <= ldq_rel_le_mode; +rel_dvc1_en_d <= ldq_rel_dvc1_en; +rel_dvc2_en_d <= ldq_rel_dvc2_en; +rel_upd_gpr_d <= ldq_rel_beat_crit_qw; +rel_axu_val_d <= ldq_rel_axu_val; +rel_ci_d <= ldq_rel_ci; +rel_ci_dly_d <= rel_ci_q; +rel_thrd_id_d <= ldq_rel_thrd_id; +rel_data_val_stg_d <= ldq_rel_data_val; +rel_data_val_stg_dly_d <= rel_data_val_stg_q; + +rel_algebraic <= rel_algebraic_q; +rel_data <= rel_data_q; +rel_rot_sel <= rel_rot_sel_q; +rel_op_size <= rel_op_size_q; +rel_le_mode <= rel_le_mode_q; + +inj_dcache_parity_d <= pc_xu_inj_dcache_parity; + +-- Staging out Data Cache Array Write +-- Cache-Inhibit or Cacheable Reload +rel_data_rot_sel <= rel_ci_q or rel_data_val_stg_q; +rel_data_val_wren <= rel_data_val_stg_q and not spr_xucr0_dcdis_q; +rel_data_val_d(0 to 7) <= (others=>rel_data_val_wren); +rel_data_val_d(8 to 15) <= (others=>(not rel_data_val_wren)); +rel_data_val <= rel_data_val_q; +rel_addr_stg_d <= ldq_rel_addr; +rel_addr_d <= rel_addr_stg_q; + +spr_xucr0_dcdis_d <= xu_lsu_spr_xucr0_dcdis; +clkg_ctl_override_d <= spr_xucr0_clkg_ctl_b0; +ex1_ldst_falign_d <= xu_lsu_rf1_axu_ldst_falign; +ex1_frc_align32 <= ex1_ldst_falign_q and ex1_optype32; +ex1_frc_align16 <= ex1_ldst_falign_q and ex1_optype16; +ex1_frc_align8 <= ex1_ldst_falign_q and ex1_optype8; +ex1_frc_align4 <= ex1_ldst_falign_q and ex1_optype4; +ex1_frc_align2 <= ex1_ldst_falign_q and ex1_optype2; +ex2_p_addr_d <= xu_lsu_ex1_eff_addr(uprCClassBit to 63); +ex3_fu_st_val_d <= fu_xu_ex2_store_data_val; +ex2_optype32_d <= ex1_optype32; +ex2_optype16_d <= ex1_optype16; +ex2_optype8_d <= ex1_optype8; +ex2_optype4_d <= ex1_optype4; +ex2_optype2_d <= ex1_optype2; +ex2_optype1_d <= ex1_optype1; +ex2_store_instr_d <= ex1_store_instr; +ex3_store_instr_d <= ex2_store_instr_q and ex2_stg_act_q; +ex2_axu_op_val_d <= ex1_axu_op_val; +ex3_axu_op_val_d <= ex2_axu_op_val_q; +ex4_axu_op_val_d <= ex3_axu_op_val_q; +ex2_saxu_instr_d <= ex1_saxu_instr; +ex2_sdp_instr_d <= ex1_sdp_instr; +ex2_stgpr_instr_d <= ex1_stgpr_instr; +ex3_saxu_instr_d <= ex2_saxu_instr_q; +ex4_saxu_instr_d <= ex3_saxu_instr_q; +ex4_algebraic_d <= ex3_algebraic; +ex2_ovrd_rot_sel_d <= xu_lsu_ex1_rotsel_ovrd; +ex3_p_addr_d <= ex2_p_addr_q; +ex4_p_addr_d <= ex3_p_addr_q; +ex4_thrd_id_d <= ex3_thrd_id; +ex5_thrd_id_d <= ex4_thrd_id_q; +ex4_load_hit <= ex4_load_op_hit and not ex4_stg_flush; +ex5_load_hit_d <= ex4_load_hit; +ex6_load_hit_d <= ex5_load_hit_q; +ex7_load_hit_d <= ex6_load_hit_q; +spr_dvc1_dbg_d <= spr_dvc1_dbg; +spr_dvc2_dbg_d <= spr_dvc2_dbg; + +ex1_op_size <= ex1_optype8 & ex1_optype4 & ex1_optype2 & ex1_optype1; + +with ex1_op_size(2 to 5) select + ex1_st_byte_mask <= x"01" when "0001", + x"03" when "0010", + x"0F" when "0100", + x"FF" when others; + +ex2_xu_cmp_val_d <= gate(ex1_st_byte_mask((64-(2**regmode))/8 to 7), (not ex1_axu_op_val and ex1_store_instr)); + +-- Forcing Alignment +frc_p_addr_d(58) <= xu_lsu_ex1_eff_addr(58); +frc_p_addr_d(59) <= xu_lsu_ex1_eff_addr(59) and not ex1_frc_align32; +frc_p_addr_d(60) <= xu_lsu_ex1_eff_addr(60) and not (ex1_frc_align32 or ex1_frc_align16); +frc_p_addr_d(61) <= xu_lsu_ex1_eff_addr(61) and not (ex1_frc_align32 or ex1_frc_align16 or ex1_frc_align8); +frc_p_addr_d(62) <= xu_lsu_ex1_eff_addr(62) and not (ex1_frc_align32 or ex1_frc_align16 or ex1_frc_align8 or ex1_frc_align4); +frc_p_addr_d(63) <= xu_lsu_ex1_eff_addr(63) and not (ex1_frc_align32 or ex1_frc_align16 or ex1_frc_align8 or ex1_frc_align4 or ex1_frc_align2); + +axu_rel_val_stg1_d <= rel_axu_val_q; +axu_rel_val_stg2_d <= axu_rel_val_stg1_q and rel_upd_gpr_q; +axu_rel_val_stg3_d <= axu_rel_val_stg2_q; +axu_rel_upd_d <= (others=>axu_rel_val_stg3_q); + +-- Table of op_size, Should be 1-hot enabled +-- op_size(0) => size32 +-- op_size(1) => size16 +-- op_size(2) => size8 +-- op_size(3) => size4 +-- op_size(4) => size2 +-- op_size(5) => size1 +op_size <= ex2_optype32_q & ex2_optype16_q & ex2_optype8_q & ex2_optype4_q & ex2_optype2_q & ex2_optype1_q; +rot_addr <= frc_p_addr_q(58 to 63); +ex3_le_mode <= ex3_data_swap and not (ex3_ovrd_rot_q or rel_data_val(0)); +ex3_be_mode <= ex3_ovrd_rot_q or rel_data_val(0) or (not ex3_data_swap); +ex4_le_mode_sel_d(0 to 15) <= (others=>ex3_le_mode); +ex4_be_mode_sel_d(0 to 15) <= (others=>ex3_be_mode); +ex4_le_mode_d <= ex3_le_mode; + +-- Execution/Reload Pipe Rotator Control Calculations +rot_size <= std_ulogic_vector(unsigned(rot_addr) + unsigned(op_size)); +rot_sel_non_le <= std_ulogic_vector(unsigned(rot_max_size) - unsigned(rot_size)); + +-- STORE PATH LITTLE ENDIAN ROTATOR SELECT CALCULATION +-- st_rot_size = rot_addr + op_size +-- st_rot_sel = (rot_max_size or le_op_size) - rot_size + +-- Little Endian Support Store Data Rotate Select +rot_addr_le <= std_ulogic_vector(unsigned(rot_addr) + unsigned(byte16_size)); +rot_size_le <= std_ulogic_vector(unsigned(rot_max_size) - unsigned(rot_addr_le)); + +with op_size(0) select + le_st_rot_sel <= (others=>'0') when '1', + rot_size_le(2 to 5) when others; + +be_st_rot_sel <= rot_sel_non_le(1 to 5); + +-- Select between Rotate Select Override and D$ rotate select +with ex2_ovrd_rot select + st_ovrd_rot_sel <= ex2_ovrd_rot_sel_q when '1', + be_st_rot_sel when others; + +ex3_st_rot_sel_d <= st_ovrd_rot_sel; + +-- LOAD PATH LITTLE ENDIAN ROTATOR SELECT CALCULATION +-- ld_rot_size = rot_addr + op_size +-- ld_rot_sel_le = rot_addr +-- ld_rot_sel = rot_max_size - ld_rot_size +-- ld_rot_sel = ld_rot_sel_le => le_mode = 1 +-- = ld_rot_sel => le_mode = 0 + +rot_addr_d <= rot_addr(1 to 5); +ex4_rot_addr_d <= rot_addr_q; +rot_sel_non_le_d <= rot_sel_non_le(1 to 5); +ex4_rot_sel_non_le_d <= rot_sel_non_le_q; + +-- Little Endian Support Load Data Rotate Select +with ex4_le_mode_q select + ex4_ld_rot_sel <= ex4_rot_addr_q(1 to 5) when '1', + ex4_rot_sel_non_le_q(1 to 5) when others; + +-- Algebraic Mux select for little-endian +alg_bit_le_sel <= std_ulogic_vector(unsigned(rot_size) - "000001"); +ld_alg_le_sel_d(1 to 5) <= alg_bit_le_sel(1 to 5); +ex4_ld_alg_le_sel_d <= ld_alg_le_sel_q; + +with ex4_le_mode_q select + ex4_ld_alg_sel <= ex4_rot_addr_q when '0', + ex4_ld_alg_le_sel_q when others; + +fu_ex2_store_data_val <= (ex2_axu_op_val_q and ex2_store_instr_q) or ex2_saxu_instr_q; +fu_ex2_store_data <= fu_xu_ex2_store_data; + +ex2_st_data_d <= xu_lsu_ex1_store_data; +ex2_st_data_fixup(0 to 127-(2**regmode)) <= (others=>'0'); +ex2_st_data_fixup(128-(2**regmode) to 127) <= ex2_st_data_q; + +with rel_data_rot_sel select + rel_xu_data <= rel_data when '1', + ex2_st_data_fixup & ex2_st_data_fixup when others; + +ex2_fu_data_val <= fu_ex2_store_data_val and not rel_data_rot_sel; + +with ex2_fu_data_val select + rel_ex2_data <= fu_ex2_store_data when '1', + rel_xu_data when others; + +-- Splitting Out Bits of Store Data +-- Grouping Common Bits together, i.e all bit0's of every byte are grouped and so on +-- should now have all upper nibbles of bytes in the first half of data (0:127) +-- and have the lower nibbles of bytes in the second half of data (128:255) +stDataFrmtBit : for bit in 0 to 7 generate begin + stDataFrmtByte : for byte in 0 to 31 generate begin + rel_ex3_data_d((bit*32)+byte) <= rel_ex2_data((byte*8)+bit); + end generate stDataFrmtByte; +end generate stDataFrmtBit; + + +-- Timing Fixes to Data Cache Array Write Enable +ex4_store_hit_early_gate <= ex4_store_hit and not ex7_ld_par_err(0); +rel_ex4_store_hit <= ex4_store_hit_early_gate or rel_upd_dcarr_val; +ex4_thrd_id_mask <= gate(ex4_thrd_id_q, not rel_upd_dcarr_val); + +ex4Flushb0: ex4_stg_flush_lcl_b(0) <= not (xu_lsu_ex4_flush_local(0) and ex4_thrd_id_mask(0)); +ex4Flushb1: ex4_stg_flush_lcl_b(1) <= not (xu_lsu_ex4_flush_local(1) and ex4_thrd_id_mask(1)); +ex4Flushb2: ex4_stg_flush_lcl_b(2) <= not (xu_lsu_ex4_flush_local(2) and ex4_thrd_id_mask(2)); +ex4Flushb3: ex4_stg_flush_lcl_b(3) <= not (xu_lsu_ex4_flush_local(3) and ex4_thrd_id_mask(3)); + +ex4Flush01b: ex4_flush_t01_b <= not (ex4_stg_flush_lcl_b(0) and ex4_stg_flush_lcl_b(1)); +ex4Flush23b: ex4_flush_t23_b <= not (ex4_stg_flush_lcl_b(2) and ex4_stg_flush_lcl_b(3)); +relex4UpdEn: rel_ex4_upd_en <= not (ex4_flush_t01_b or ex4_flush_t23_b); + +-- EX4 Instruction Flush +ex4_stg_flush <= (xu_lsu_ex4_flush(0) and ex4_thrd_id_q(0)) or + (xu_lsu_ex4_flush(1) and ex4_thrd_id_q(1)) or + (xu_lsu_ex4_flush(2) and ex4_thrd_id_q(2)) or + (xu_lsu_ex4_flush(3) and ex4_thrd_id_q(3)); + +-- EX5 Instruction Flush +ex5_stg_flush <= (xu_lsu_ex5_flush(0) and ex5_thrd_id_q(0)) or + (xu_lsu_ex5_flush(1) and ex5_thrd_id_q(1)) or + (xu_lsu_ex5_flush(2) and ex5_thrd_id_q(2)) or + (xu_lsu_ex5_flush(3) and ex5_thrd_id_q(3)); + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Move To AXU/XU/BOX Instructions +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +-- Move Float To GPR and Move GPR to Float instruction Data +ex2_ovrd_rot <= ex2_saxu_instr_q or ex2_stgpr_instr_q; +ex3_ovrd_rot_d <= ex2_ovrd_rot; +ex3_stgpr_instr_d <= ex2_stgpr_instr_q; +ex4_stgpr_instr_d <= ex3_stgpr_instr_q; + +-- Grabbing bits to form bytes +stDataFixUp : for byte in 0 to 31 generate + ex4_256st_dataFixUp(byte*8 to (byte*8)+7) <= st_256data(byte) & st_256data(byte+32) & st_256data(byte+64) & st_256data(byte+96) & + st_256data(byte+128) & st_256data(byte+160) & st_256data(byte+192) & st_256data(byte+224); +end generate stDataFixUp; + +ex4_stgpr_data <= ex4_256st_dataFixUp(256-(2**regmode) to 255); +ex5_stgpr_data_d <= ex4_stgpr_data; +ex3_sdp_instr_d <= ex2_sdp_instr_q; +ex4_sdp_instr_d <= ex3_sdp_instr_q; +ex5_sdp_instr_d <= ex4_sdp_instr_q; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Execution Pipe Data Parity Generation +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +pargen : for t in 0 to 31 generate begin + rel_ex2_par_gen(t) <= xor_reduce(rel_ex2_data(t*8 to (t*8)+7)); +end generate pargen; + +rel_ex3_par_gen_d <= rel_ex2_par_gen; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Reload Algebraic Mask Generation +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +non_le_byte_bit0 <= rel_data(0) & rel_data(8) & rel_data(16) & rel_data(24) & rel_data(32) & rel_data(40) & rel_data(48) & rel_data(56) & + rel_data(64) & rel_data(72) & rel_data(80) & rel_data(88) & rel_data(96) & rel_data(104) & rel_data(112) & rel_data(120) & + rel_data(128) & rel_data(136) & rel_data(144) & rel_data(152) & rel_data(160) & rel_data(168) & rel_data(176) & rel_data(184) & + rel_data(192) & rel_data(200) & rel_data(208) & rel_data(216) & rel_data(224) & rel_data(232) & rel_data(240) & rel_data(248); + +le_byte_bit0 <= rel_data(248) & rel_data(240) & rel_data(232) & rel_data(224) & rel_data(216) & rel_data(208) & rel_data(200) & rel_data(192) & + rel_data(184) & rel_data(176) & rel_data(168) & rel_data(160) & rel_data(152) & rel_data(144) & rel_data(136) & rel_data(128) & + rel_data(120) & rel_data(112) & rel_data(104) & rel_data(96) & rel_data(88) & rel_data(80) & rel_data(72) & rel_data(64) & + rel_data(56) & rel_data(48) & rel_data(40) & rel_data(32) & rel_data(24) & rel_data(16) & rel_data(8) & rel_data(0); + +-- Select between little endian data or big-endian data +with rel_le_mode select + alg_byte <= le_byte_bit0 when '1', + non_le_byte_bit0 when others; + +-- Calculate Mux control +alg_bit_sel <= std_ulogic_vector(unsigned(rel_rot_sel) - unsigned(rel_op_size(1 to 5))); + +with alg_bit_sel select + algebraic_bit <= alg_byte(0) when "00000", + alg_byte(1) when "00001", + alg_byte(2) when "00010", + alg_byte(3) when "00011", + alg_byte(4) when "00100", + alg_byte(5) when "00101", + alg_byte(6) when "00110", + alg_byte(7) when "00111", + alg_byte(8) when "01000", + alg_byte(9) when "01001", + alg_byte(10) when "01010", + alg_byte(11) when "01011", + alg_byte(12) when "01100", + alg_byte(13) when "01101", + alg_byte(14) when "01110", + alg_byte(15) when "01111", + alg_byte(16) when "10000", + alg_byte(17) when "10001", + alg_byte(18) when "10010", + alg_byte(19) when "10011", + alg_byte(20) when "10100", + alg_byte(21) when "10101", + alg_byte(22) when "10110", + alg_byte(23) when "10111", + alg_byte(24) when "11000", + alg_byte(25) when "11001", + alg_byte(26) when "11010", + alg_byte(27) when "11011", + alg_byte(28) when "11100", + alg_byte(29) when "11101", + alg_byte(30) when "11110", + alg_byte(31) when others; + +rel_alg_bit_d <= algebraic_bit; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Store Data Rotator +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +l1dcst: entity work.xuq_lsu_data_st(xuq_lsu_data_st) +GENERIC MAP(expand_type => expand_type, + regmode => regmode, + l_endian_m => l_endian_m) +PORT MAP( + + -- Acts to latches + ex2_stg_act => ex2_stg_act_q, + ex3_stg_act => ex3_stg_act_q, + rel2_stg_act => rel2_stg_act_q, + rel3_stg_act => rel3_stg_act_q, + rel2_ex2_stg_act => rel2_ex2_stg_act, + rel3_ex3_stg_act => rel3_ex3_stg_act, + + -- Reload Pipe + rel_data_rot_sel => rel_data_rot_sel, + ldq_rel_rot_sel => rel_rot_sel, + ldq_rel_op_size => rel_op_size, + ldq_rel_le_mode => rel_le_mode, + ldq_rel_algebraic => rel_algebraic, + ldq_rel_data_val => rel_data_val, + rel_alg_bit => rel_alg_bit_q, + + -- Execution Pipe Store Data Rotator/BE_Gen Controls + ex2_opsize => op_size, + ex2_rot_sel => st_ovrd_rot_sel, + ex2_rot_sel_le => le_st_rot_sel, + ex2_rot_addr => rot_addr(1 to 5), + ex4_le_mode_sel => ex4_le_mode_sel_q, + ex4_be_mode_sel => ex4_be_mode_sel_q, + + -- Reload/EX3 Data that needs rotating + rel_ex3_data => rel_ex3_data_q, + rel_ex3_par_gen => rel_ex3_par_gen_q, + + -- Rotated Data + rel_256ld_data => rel_256ld_data, + rel_64ld_data => rel_64ld_data, + rel_xu_ld_par => rel_xu_ld_par, + ex4_256st_data => st_256data, + ex3_byte_en => ex3_byte_en, + ex4_parity_gen => ex4_parity_gen, + rel_axu_le_mode => rel_axu_le_mode, + rel_dvc_byte_mask => rel_dvc_byte_mask, + + -- Pervasive + vdd => vdd, + gnd => gnd, + nclk => nclk, + sg_0 => sg_0, + func_sl_thold_0_b => func_sl_thold_0_b, + func_sl_force => func_sl_force, + func_nsl_thold_0_b => func_nsl_thold_0_b, + func_nsl_force => func_nsl_force, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc(5), + mpw1_dc_b => mpw1_dc_b(5), + mpw2_dc_b => mpw2_dc_b, + scan_in => func_scan_in_2_q(2), + scan_out => func_scan_out_int(2) +); + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- L1 D-Cache Array +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +l1dcarr : entity work.xuq_lsu_dc_arr(xuq_lsu_dc_arr) +generic map(expand_type => expand_type, -- 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) + dc_size => dc_size) -- 2^14 = 16384 Bytes L1 D$ +port map( + + -- Acts to latches + ex3_stg_act => ex3_stg_act_q, + ex4_stg_act => ex4_stg_act_q, + rel3_stg_act => rel3_stg_act_q, + rel4_stg_act => rel4_stg_act_q, + + -- XUOP Signals + ex3_p_addr => ex3_p_addr_q(uprCClassBit to 58), + ex3_byte_en => ex3_byte_en, + ex4_256st_data => st_256data, + ex4_parity_gen => ex4_parity_gen, + ex4_load_hit => ex4_load_hit, + ex5_stg_flush => ex5_stg_flush, + + -- Parity Error Inject + inj_dcache_parity => inj_dcache_parity_q, + + -- Reload Signals + ldq_rel_data_val => rel_data_val(0), + ldq_rel_addr => rel_addr_q, + + dcarr_rd_data => dcarr_rd_data, + dcarr_bw => dcarr_bw, + dcarr_addr => dcarr_addr, + dcarr_wr_data => dcarr_wr_data, + dcarr_bw_dly => dcarr_bw_dly, + + -- Execution Pipe + ex5_ld_data => ex5_ld_data, + ex5_ld_data_par => ex5_ld_data_par, + ex6_par_chk_val => ex6_par_chk_val, + + --pervasive + vdd => vdd, + gnd => gnd, + nclk => nclk, + sg_0 => sg_0, + func_sl_thold_0_b => func_sl_thold_0_b, + func_sl_force => func_sl_force, + func_nsl_thold_0_b => func_nsl_thold_0_b, + func_nsl_force => func_nsl_force, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc(5), + mpw1_dc_b => mpw1_dc_b(5), + mpw2_dc_b => mpw2_dc_b, + scan_in => siv1(l1dcar_offset), + scan_out => sov1(l1dcar_offset) +); + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Array +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +dcArrWenb: dcarr_wren_b <= not (rel_ex4_store_hit and rel_ex4_upd_en); +dcArrWen: dcarr_wren <= not (dcarr_wren_b); + +dcarr_wren_d <= dcarr_wren; +dat_dbg_arr_d <= ex4_store_hit & (not rel_ex4_upd_en) & rel_upd_dcarr_val & rel4_ex4_stg_act & + dcarr_up_way_addr & dcarr_addr; + +dc16K: if (2**dc_size) = 16384 generate + tridcarr: entity tri.tri_512x288_9(tri_512x288_9) + GENERIC Map(addressable_ports => 512, -- number of addressable register in this array + addressbus_width => 6, -- width of the bus to address all ports (2^portadrbus_width >= addressable_ports) + port_bitwidth => 288, -- bitwidth of ports (per way) + bit_write_type => 9, -- gives the number of bits that shares one write-enable + ways => 1, -- number of ways + expand_type => expand_type) -- 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) + PORT Map( + -- POWER PINS + vcs => vcs, + vdd => vdd, + gnd => gnd, + + -- CLOCK AND CLOCKCONTROL PORTS + nclk => nclk, + act => rel4_ex4_stg_act, + sg_0 => sg_0, + sg_1 => sg_1, + ary_nsl_thold_0 => ary_nsl_thold_0, + abst_sl_thold_0 => abst_sl_thold_0, + time_sl_thold_0 => time_sl_thold_0, + repr_sl_thold_0 => repr_sl_thold_0, + clkoff_dc_b => g6t_clkoff_dc_b, + ccflush_dc => pc_xu_ccflush_dc, + scan_dis_dc_b => an_ac_scan_dis_dc_b, + scan_diag_dc => an_ac_scan_diag_dc, + d_mode_dc => g6t_d_mode_dc, + act_dis_dc => tidn, + lcb_delay_lclkr_np_dc => g6t_delay_lclkr_dc(0), + lcb_mpw1_pp_dc_b => g6t_mpw1_dc_b(0), + lcb_mpw1_2_pp_dc_b => g6t_mpw1_dc_b(4), + ctrl_lcb_delay_lclkr_np_dc => g6t_delay_lclkr_dc(1), + ctrl_lcb_mpw1_np_dc_b => g6t_mpw1_dc_b(1), + dibw_lcb_delay_lclkr_np_dc => g6t_delay_lclkr_dc(2), + dibw_lcb_mpw1_np_dc_b => g6t_mpw1_dc_b(2), + aodo_lcb_delay_lclkr_dc => g6t_delay_lclkr_dc(3), + aodo_lcb_mpw1_dc_b => g6t_mpw1_dc_b(3), + aodo_lcb_mpw2_dc_b => g6t_mpw2_dc_b, + + -- ABIST + bitw_abist => pc_xu_abist_g6t_bw_q, + tc_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc, + abist_en_1 => pc_xu_abist_ena_dc, + din_abist => pc_xu_abist_di_g6t_2r_q, + abist_cmp_en => pc_xu_abist_wl512_comp_ena_q, + abist_raw_b_dc => pc_xu_abist_raw_dc_b, + data_cmp_abist => pc_xu_abist_dcomp_g6t_2r_q, + addr_abist => pc_xu_abist_raddr_0_q, + r_wb_abist => pc_xu_abist_g6t_r_wb_q, + + -- SCAN PORTS + abst_scan_in(0) => abist_siv(0), + abst_scan_in(1) => abst_scan_in_q(1), + time_scan_in => time_scan_in_q, + repr_scan_in => repr_scan_in_q, + abst_scan_out(0) => abist_sov(0), + abst_scan_out(1) => abst_scan_out_int(1), + time_scan_out => time_scan_out_int, + repr_scan_out => repr_scan_out_int, + + -- BOLT-ON + lcb_bolt_sl_thold_0 => bolt_sl_thold_0, + pc_bo_enable_2 => bo_enable_2, + pc_bo_reset => pc_xu_bo_reset, + pc_bo_unload => pc_xu_bo_unload, + pc_bo_repair => pc_xu_bo_repair, + pc_bo_shdata => pc_xu_bo_shdata, + pc_bo_select => pc_xu_bo_select, + bo_pc_failout => xu_pc_bo_fail, + bo_pc_diagloop => xu_pc_bo_diagout, + tri_lcb_mpw1_dc_b => mpw1_dc_b(5), + tri_lcb_mpw2_dc_b => mpw2_dc_b, + tri_lcb_delay_lclkr_dc => delay_lclkr_dc(5), + tri_lcb_clkoff_dc_b => clkoff_dc_b, + tri_lcb_act_dis_dc => tidn, + + + -- FUNCITONAL PORTS + write_enable => dcarr_wren, + bw => dcarr_bw, + arr_up_addr => dcarr_up_way_addr, + addr => dcarr_addr, + data_in => dcarr_wr_data, + data_out => dcarr_rd_data + ); +end generate dc16K; + +dc32K: if (2**dc_size) = 32768 generate + tridcarr: entity tri.tri_512x288_9(tri_512x288_9) + GENERIC Map(addressable_ports => 1024, -- number of addressable register in this array + addressbus_width => 7, -- width of the bus to address all ports (2^portadrbus_width >= addressable_ports) + port_bitwidth => 288, -- bitwidth of ports (per way) + bit_write_type => 9, -- gives the number of bits that shares one write-enable + ways => 1, -- number of ways + expand_type => expand_type) -- 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) + PORT Map( + -- POWER PINS + vcs => vcs, + vdd => vdd, + gnd => gnd, + + -- CLOCK AND CLOCKCONTROL PORTS + nclk => nclk, + act => rel4_ex4_stg_act, + sg_0 => sg_0, + sg_1 => sg_1, + ary_nsl_thold_0 => ary_nsl_thold_0, + abst_sl_thold_0 => abst_sl_thold_0, + time_sl_thold_0 => time_sl_thold_0, + repr_sl_thold_0 => repr_sl_thold_0, + clkoff_dc_b => g6t_clkoff_dc_b, + ccflush_dc => pc_xu_ccflush_dc, + scan_dis_dc_b => an_ac_scan_dis_dc_b, + scan_diag_dc => an_ac_scan_diag_dc, + d_mode_dc => g6t_d_mode_dc, + act_dis_dc => tidn, + lcb_delay_lclkr_np_dc => g6t_delay_lclkr_dc(0), + lcb_mpw1_pp_dc_b => g6t_mpw1_dc_b(0), + lcb_mpw1_2_pp_dc_b => g6t_mpw1_dc_b(4), + ctrl_lcb_delay_lclkr_np_dc => g6t_delay_lclkr_dc(1), + ctrl_lcb_mpw1_np_dc_b => g6t_mpw1_dc_b(1), + dibw_lcb_delay_lclkr_np_dc => g6t_delay_lclkr_dc(2), + dibw_lcb_mpw1_np_dc_b => g6t_mpw1_dc_b(2), + aodo_lcb_delay_lclkr_dc => g6t_delay_lclkr_dc(3), + aodo_lcb_mpw1_dc_b => g6t_mpw1_dc_b(3), + aodo_lcb_mpw2_dc_b => g6t_mpw2_dc_b, + + -- ABIST + bitw_abist => pc_xu_abist_g6t_bw_q, + tc_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc, + abist_en_1 => pc_xu_abist_ena_dc, + din_abist => pc_xu_abist_di_g6t_2r_q, + abist_cmp_en => pc_xu_abist_wl512_comp_ena_q, + abist_raw_b_dc => pc_xu_abist_raw_dc_b, + data_cmp_abist => pc_xu_abist_dcomp_g6t_2r_q, + addr_abist => pc_xu_abist_raddr_0_q, + r_wb_abist => pc_xu_abist_g6t_r_wb_q, + + -- SCAN PORTS + abst_scan_in(0) => abist_siv(0), + abst_scan_in(1) => abst_scan_in_q(1), + time_scan_in => time_scan_in_q, + repr_scan_in => repr_scan_in_q, + abst_scan_out(0) => abist_sov(0), + abst_scan_out(1) => abst_scan_out_int(1), + time_scan_out => time_scan_out_int, + repr_scan_out => repr_scan_out_int, + + -- BOLT-ON + lcb_bolt_sl_thold_0 => bolt_sl_thold_0, + pc_bo_enable_2 => bo_enable_2, + pc_bo_reset => pc_xu_bo_reset, + pc_bo_unload => pc_xu_bo_unload, + pc_bo_repair => pc_xu_bo_repair, + pc_bo_shdata => pc_xu_bo_shdata, + pc_bo_select => pc_xu_bo_select, + bo_pc_failout => xu_pc_bo_fail, + bo_pc_diagloop => xu_pc_bo_diagout, + tri_lcb_mpw1_dc_b => mpw1_dc_b(5), + tri_lcb_mpw2_dc_b => mpw2_dc_b, + tri_lcb_delay_lclkr_dc => delay_lclkr_dc(5), + tri_lcb_clkoff_dc_b => clkoff_dc_b, + tri_lcb_act_dis_dc => tidn, + + -- FUNCITONAL PORTS + write_enable => dcarr_wren, + bw => dcarr_bw, + arr_up_addr => dcarr_up_way_addr, + addr => dcarr_addr, + data_in => dcarr_wr_data, + data_out => dcarr_rd_data + ); +end generate dc32K; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Load Rotator +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +ex3_opsize_d <= op_size; + +rel_axu_le_val_d <= rel_axu_le_mode and rel_upd_gpr_q; +rel_axu_le_val_stg1_d <= rel_axu_le_val_q; +ex5_rel_le_mode_d <= (ex4_le_mode_q and not rel_axu_le_val_stg1_q) or rel_axu_le_val_stg1_q; + +l1dcld: entity work.xuq_lsu_data_ld(xuq_lsu_data_ld) +GENERIC MAP(expand_type => expand_type, -- 0 = ibm, 1 = xilinx + regmode => regmode, + l_endian_m => l_endian_m) -- 1 = little endian mode enabled, 0 = little endian mode disabled +PORT MAP( + + -- Acts to latches + ex3_stg_act => ex3_stg_act_q, + ex4_stg_act => ex4_stg_act_q, + ex5_stg_act => ex5_stg_act_q, + + -- Execution Pipe Load Data Rotator Controls + ex3_opsize => ex3_opsize_q, + ex3_algebraic => ex3_algebraic, + ex4_ld_rot_sel => ex4_ld_rot_sel, + ex4_ld_alg_sel => ex4_ld_alg_sel, + ex4_le_mode => ex4_le_mode_q, + ex5_ld_data => ex5_ld_data, + ex5_ld_data_par => ex5_ld_data_par, + ex6_par_chk_val => ex6_par_chk_val, + + -- Debug Bus + trace_bus_enable => trace_bus_enable_q, + dat_debug_mux_ctrls => dat_debug_mux_ctrls_q, + dat_dbg_ld_dat => dat_dbg_ld_dat, + + -- Rotated Data + ld_swzl_data (0 to 255) => ld_swzl_data(0 to 255) , + ex6_ld_alg_bit(0 to 5) => ex6_ld_alg_bit(0 to 5) , + ex6_ld_dvc_byte_mask => ex6_ld_dvc_byte_mask, + + + ex6_ld_par_err => ex6_ld_par_err_int, + ex7_ld_par_err => ex7_ld_par_err, + + -- Pervasive + vdd => vdd, + gnd => gnd, + nclk => nclk, + sg_0 => sg_0, + func_sl_thold_0_b => func_sl_thold_0_b, + func_sl_force => func_sl_force, + func_nsl_thold_0_b => func_nsl_thold_0_b, + func_nsl_force => func_nsl_force, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc(5), + mpw1_dc_b => mpw1_dc_b(5), + mpw2_dc_b => mpw2_dc_b, + scan_in => siv1(l1dcld_offset), + scan_out => sov1(l1dcld_offset) +); + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Debug Bus +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +stDbgData : for byte in 0 to 7 generate begin + rel_ex3_store_data0(byte*8 to (byte*8)+7) <= rel_ex3_data_q(byte+0) & rel_ex3_data_q(byte+32) & rel_ex3_data_q(byte+64) & rel_ex3_data_q(byte+96) & + rel_ex3_data_q(byte+128) & rel_ex3_data_q(byte+160) & rel_ex3_data_q(byte+192) & rel_ex3_data_q(byte+224); + rel_ex3_store_data1(byte*8 to (byte*8)+7) <= rel_ex3_data_q(8+byte+0) & rel_ex3_data_q(8+byte+32) & rel_ex3_data_q(8+byte+64) & rel_ex3_data_q(8+byte+96) & + rel_ex3_data_q(8+byte+128) & rel_ex3_data_q(8+byte+160) & rel_ex3_data_q(8+byte+192) & rel_ex3_data_q(8+byte+224); + rel_ex3_store_data2(byte*8 to (byte*8)+7) <= rel_ex3_data_q(16+byte+0) & rel_ex3_data_q(16+byte+32) & rel_ex3_data_q(16+byte+64) & rel_ex3_data_q(16+byte+96) & + rel_ex3_data_q(16+byte+128) & rel_ex3_data_q(16+byte+160) & rel_ex3_data_q(16+byte+192) & rel_ex3_data_q(16+byte+224); + rel_ex3_store_data3(byte*8 to (byte*8)+7) <= rel_ex3_data_q(24+byte+0) & rel_ex3_data_q(24+byte+32) & rel_ex3_data_q(24+byte+64) & rel_ex3_data_q(24+byte+96) & + rel_ex3_data_q(24+byte+128) & rel_ex3_data_q(24+byte+160) & rel_ex3_data_q(24+byte+192) & rel_ex3_data_q(24+byte+224); +end generate stDbgData; + +with dat_debug_mux_ctrls_q select + dat_dbg_st_dat_d <= rel_ex3_store_data0 when "00", + rel_ex3_store_data1 when "01", + rel_ex3_store_data2 when "10", + rel_ex3_store_data3 when others; + + +-- Debug Bus0 +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- ex4_saxu_instr_q 1 +-- ex4_sdp_instr_q 1 +-- ex4_stgpr_instr_q 1 +-- ex4_axu_op_val_q 1 +-- ex4_algebraic_q 1 +-- ex4_le_mode_q 1 +-- ex4_ld_rot_sel 5 +-- ex4_p_addr_q 11 + +-- ex7_load_hit_q 1 +-- ex7_ld_par_err 1 +-- dat_dbg_ld_dat(0:19) 20 + +-- dat_dbg_ld_dat(20:41) 22 + +-- dat_dbg_ld_dat(42:63) 22 + +lsu_xu_data_debug0(0 to 21) <= ex4_saxu_instr_q & ex4_sdp_instr_q & ex4_stgpr_instr_q & ex4_axu_op_val_q & + ex4_algebraic_q & ex4_le_mode_q & ex4_ld_rot_sel & ex4_p_addr_q; +lsu_xu_data_debug0(22 to 43) <= ex7_load_hit_q & ex7_ld_par_err(1) & dat_dbg_ld_dat(0 to 19); +lsu_xu_data_debug0(44 to 65) <= dat_dbg_ld_dat(20 to 41); +lsu_xu_data_debug0(66 to 87) <= dat_dbg_ld_dat(42 to 63); + +-- Debug Bus1 +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- dcarr_wren_q 1 +-- rel_ci_dly_q 1 +-- ex4_saxu_instr_q 1 +-- ex4_stgpr_instr_q 1 +-- ex3_fu_st_val_q 1 +-- ex4_le_mode_q 1 +-- ex3_st_rot_sel_q 5 +-- ex4_p_addr_q 11 + +-- ex7_load_hit_q 1 +-- ex7_ld_par_err 1 +-- dat_dbg_st_dat(0:19) 20 + +-- dat_dbg_st_dat(20:41) 22 + +-- dat_dbg_st_dat(42:63) 22 + +lsu_xu_data_debug1(0 to 21) <= dcarr_wren_q & rel_ci_dly_q & ex4_saxu_instr_q & ex4_stgpr_instr_q & + ex3_fu_st_val_q & ex4_le_mode_q & ex3_st_rot_sel_q & ex4_p_addr_q; +lsu_xu_data_debug1(22 to 43) <= ex3_store_instr_q & rel_data_val_stg_dly_q & dat_dbg_st_dat_q(0 to 19); +lsu_xu_data_debug1(44 to 65) <= dat_dbg_st_dat_q(20 to 41); +lsu_xu_data_debug1(66 to 87) <= dat_dbg_st_dat_q(42 to 63); + +-- Debug Bus2 +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- ex4_store_hit 1 +-- ex4_blk_store 1 +-- rel_upd_dcarr_val 1 +-- dcarr_up_way_addr 3 +-- dcarr_addr 6 +-- dcarr_bw_dly(0:9) 10 + +-- dcarr_bw_dly(10:31) 22 + +-- rel4_ex4_stg_act 1 +-- dat_dbg_st_dat(21:41) 21 + +-- dat_dbg_st_dat(42:63) 22 + +lsu_xu_data_debug2(0 to 21) <= dat_dbg_arr_q(0 to 2) & dat_dbg_arr_q(4 to 12) & dcarr_bw_dly(0 to 9); +lsu_xu_data_debug2(22 to 43) <= dcarr_bw_dly(10 to 31); +lsu_xu_data_debug2(44 to 65) <= dat_dbg_arr_q(3) & dat_dbg_st_dat_q(21 to 41); +lsu_xu_data_debug2(66 to 87) <= dat_dbg_st_dat_q(42 to 63); + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- DEBUG Data Compare +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +-- Store Data Compare +dvcCmpSt : for t in (64-(2**regmode))/8 to 7 generate begin + ex2_st_dvc1_cmp_d(t) <= (xu_lsu_ex1_store_data(t*8 to (t*8)+7) = + spr_dvc1_dbg_q(t*8 to (t*8)+7)); + ex2_st_dvc2_cmp_d(t) <= (xu_lsu_ex1_store_data(t*8 to (t*8)+7) = + spr_dvc2_dbg_q(t*8 to (t*8)+7)); +end generate dvcCmpSt; + +-- Load Data Compare +ex5_dvc1_en_d <= ex4_load_hit and not ex4_axu_op_val; +ex5_dvc2_en_d <= ex4_load_hit and not ex4_axu_op_val; +ex6_dvc1_en_d <= ex5_dvc1_en_q; +ex6_dvc2_en_d <= ex5_dvc2_en_q; +ex7_dvc1_en_d <= gate(ex6_ld_dvc_byte_mask, ex6_dvc1_en_q); +ex7_dvc2_en_d <= gate(ex6_ld_dvc_byte_mask, ex6_dvc2_en_q); + +dvcCmpLd : for t in (64-(2**regmode))/8 to 7 generate begin + ex8_ld_dvc1_cmp_d(t) <= ex7_dvc1_en_q(t) and (ex7_xld_data_q(t*8 to (t*8)+7) = + spr_dvc1_dbg_q(t*8 to (t*8)+7)); + ex8_ld_dvc2_cmp_d(t) <= ex7_dvc2_en_q(t) and (ex7_xld_data_q(t*8 to (t*8)+7) = + spr_dvc2_dbg_q(t*8 to (t*8)+7)); +end generate dvcCmpLd; + +-- Reload Data Compare +-- Need to gate dvc enables with not an axu reload +rel_dvc1_val_d <= rel_dvc1_en_q and not rel_axu_val_q; +rel_dvc1_val_stg_d <= rel_upd_gpr_q and rel_dvc1_val_q and not ldq_rel_beat_crit_qw_block; +rel_dvc1_val_stg2_d <= rel_dvc1_val_stg_q; +rel_dvc2_val_d <= rel_dvc2_en_q and not rel_axu_val_q; +rel_dvc2_val_stg_d <= rel_upd_gpr_q and rel_dvc2_val_q and not ldq_rel_beat_crit_qw_block; +rel_dvc2_val_stg2_d <= rel_dvc2_val_stg_q; +rel_dvc_thrd_id_d <= rel_thrd_id_q; +rel_dvc_tid_stg_d <= rel_dvc_thrd_id_q; +rel_dvc_tid_stg2_d <= rel_dvc_tid_stg_q; + +dvcCmpRl : for t in (64-(2**regmode))/8 to 7 generate begin + rel_dvc1_cmp_d(t) <= (rel_64ld_data(t*8 to (t*8)+7) = + spr_dvc1_dbg_q(t*8 to (t*8)+7)) and rel_dvc_byte_mask(t); + rel_dvc2_cmp_d(t) <= (rel_64ld_data(t*8 to (t*8)+7) = + spr_dvc2_dbg_q(t*8 to (t*8)+7)) and rel_dvc_byte_mask(t); +end generate dvcCmpRl; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Return Data Muxing +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +-- Mux between move from GPR, move to GPR, and Move from DITC +ex6_stgpr_dp_data_d(0 to 127-(2**regmode)) <= ex5_dp_data(0 to 127-(2**regmode)); +ex6_stgpr_dp_data_d(128-(2**regmode) to 127) <= gate(ex5_dp_data(128-(2**regmode) to 127), ex5_sdp_instr_q) or + gate(ex5_stgpr_data_q(64-(2**regmode) to 63), not ex5_sdp_instr_q); + +-- Creating 1-hot mux selects for AXU Data Muxing Control +axu_data_sel <= (ex4_sdp_instr_q or ex4_stgpr_instr_q) & axu_rel_val_stg2_q; + +with axu_data_sel select + ex5_axu_data_sel_d <= "001" when "00", + "100" when "10", + "010" when others; + +selGen : for sel in 0 to 15 generate begin + ex6_axu_data_sel_d(3*sel to (3*sel)+2) <= ex5_axu_data_sel_q; +end generate selGen; + +ex5_stgpr_dp_instr_d <= ex4_sdp_instr_q or ex4_stgpr_instr_q; +ex6_stgpr_dp_instr_d <= ex5_stgpr_dp_instr_q; + +-- AXU Data +-- Mux between move from GPR, move to GPR, Move from DITC, load hit data, and reload data + +-- Staging out AXU Reload Data +rel_256ld_data_stg1_d <= rel_256ld_data; +rel_256ld_data_stg2_d <= rel_256ld_data_stg1_q; + + + ex6_rot_sel(0 to 15) <= not axu_rel_upd_q(0 to 15) ; + + axuldreldata : for t in 0 to 15 generate begin + + ex6_axu_oth_b(t*8 to (t*8)+7) <= not( gate(rel_256ld_data_stg2_q(t*8 to (t*8)+7), axu_rel_upd_q(t)) ); + + end generate axuldreldata; + +axuRelGpr : for byte in 0 to 15 generate + -- Muxing between stagedReloadData and MoveRegisterOps + ex6_axu_rel_gpr_data(8*byte to (8*byte)+7) <= gate(ex6_stgpr_dp_data_q(8*byte to (8*byte)+7), ex6_axu_data_sel_q((byte*3))) or + gate(rel_256ld_data_stg2_q(128+(8*byte) to 128+(8*byte)+7), ex6_axu_data_sel_q((byte*3)+1)); + + -- Muxing between loadHitData and stagedReloadData/MoveRegisterOps + ex6_axu_rel_gpr_data_sel(byte) <= not ex6_axu_data_sel_q((byte*3)+2); + ex6_rot_sel(16 + byte) <= ex6_axu_data_sel_q((byte*3)+2); + + ex6_axu_oth_b(128+(8*byte) to 128+(8*byte)+7) <= not( gate(ex6_axu_rel_gpr_data(8*byte to (8*byte)+7), ex6_axu_rel_gpr_data_sel(byte) ) ); + +end generate axuRelGpr; + + + ex6_rot_sel_bus(0 to 255) <= ( 0 to 7 => ex6_rot_sel( 0) ) & + ( 0 to 7 => ex6_rot_sel( 1) ) & + ( 0 to 7 => ex6_rot_sel( 2) ) & + ( 0 to 7 => ex6_rot_sel( 3) ) & + ( 0 to 7 => ex6_rot_sel( 4) ) & + ( 0 to 7 => ex6_rot_sel( 5) ) & + ( 0 to 7 => ex6_rot_sel( 6) ) & + ( 0 to 7 => ex6_rot_sel( 7) ) & + ( 0 to 7 => ex6_rot_sel( 8) ) & + ( 0 to 7 => ex6_rot_sel( 9) ) & + ( 0 to 7 => ex6_rot_sel(10) ) & + ( 0 to 7 => ex6_rot_sel(11) ) & + ( 0 to 7 => ex6_rot_sel(12) ) & + ( 0 to 7 => ex6_rot_sel(13) ) & + ( 0 to 7 => ex6_rot_sel(14) ) & + ( 0 to 7 => ex6_rot_sel(15) ) & + ( 0 to 7 => ex6_rot_sel(16) ) & + ( 0 to 7 => ex6_rot_sel(17) ) & + ( 0 to 7 => ex6_rot_sel(18) ) & + ( 0 to 7 => ex6_rot_sel(19) ) & + ( 0 to 7 => ex6_rot_sel(20) ) & + ( 0 to 7 => ex6_rot_sel(21) ) & + ( 0 to 7 => ex6_rot_sel(22) ) & + ( 0 to 7 => ex6_rot_sel(23) ) & + ( 0 to 7 => ex6_rot_sel(24) ) & + ( 0 to 7 => ex6_rot_sel(25) ) & + ( 0 to 7 => ex6_rot_sel(26) ) & + ( 0 to 7 => ex6_rot_sel(27) ) & + ( 0 to 7 => ex6_rot_sel(28) ) & + ( 0 to 7 => ex6_rot_sel(29) ) & + ( 0 to 7 => ex6_rot_sel(30) ) & + ( 0 to 7 => ex6_rot_sel(31) ) ; + + + u_axu_rot: ex6_frot_b (0 to 255) <= not( ld_swzl_data (0 to 255) and ex6_rot_sel_bus(0 to 255) ); + u_axu_dat: ex6_fdat (0 to 255) <= not( ex6_frot_b (0 to 255) and ex6_axu_oth_b (0 to 255) ); + + u_axu_dati: xu_fu_ex6_load_data (0 to 255) <= ex6_fdat(0 to 255); + +-- XU Data +-- Mux between move from GPR, move to GPR, Move from DITC, and load hit data + + ex6_stgpr_dp_instr_q_b <= not ex6_stgpr_dp_instr_q ; + + + u_xrot_i: ex6_rot_d_b(0 to 63) <= not( ld_swzl_data(192 to 255) ); + u_xrot_ii: ex6_rot_d (0 to 63) <= not( ex6_rot_d_b(0 to 63) ); + + u_xld_sgn: ex6_xld_sgnx_b(0 to 5) <= not( ex6_ld_alg_bit(0 to 5) and (0 to 5=> ex6_stgpr_dp_instr_q_b) ); + u_xld_sgni: ex6_xld_sgn (0 to 5) <= not( ex6_xld_sgnx_b(0 to 5) ); + u_xld_sgnii: ex6_xld_sgn_b (0 to 5) <= not( ex6_xld_sgn (0 to 5) ); + + u_xld_rot: ex6_xld_rot_b(0 to 63) <= not( ex6_rot_d(0 to 63) and (0 to 63=> ex6_stgpr_dp_instr_q_b) ); + u_xld_oth: ex6_xld_oth_b(0 to 63) <= not( ex6_stgpr_dp_data_q(64 to 127) and (0 to 63=> ex6_stgpr_dp_instr_q ) ); + + u_xld_or_00: ex6_xld_data( 0) <= not( ex6_xld_rot_b( 0) and ex6_xld_sgn_b( 0) and ex6_xld_oth_b( 0) ); + u_xld_or_01: ex6_xld_data( 1) <= not( ex6_xld_rot_b( 1) and ex6_xld_sgn_b( 0) and ex6_xld_oth_b( 1) ); + u_xld_or_02: ex6_xld_data( 2) <= not( ex6_xld_rot_b( 2) and ex6_xld_sgn_b( 1) and ex6_xld_oth_b( 2) ); + u_xld_or_03: ex6_xld_data( 3) <= not( ex6_xld_rot_b( 3) and ex6_xld_sgn_b( 1) and ex6_xld_oth_b( 3) ); + u_xld_or_04: ex6_xld_data( 4) <= not( ex6_xld_rot_b( 4) and ex6_xld_sgn_b( 2) and ex6_xld_oth_b( 4) ); + u_xld_or_05: ex6_xld_data( 5) <= not( ex6_xld_rot_b( 5) and ex6_xld_sgn_b( 2) and ex6_xld_oth_b( 5) ); + u_xld_or_06: ex6_xld_data( 6) <= not( ex6_xld_rot_b( 6) and ex6_xld_sgn_b( 3) and ex6_xld_oth_b( 6) ); + u_xld_or_07: ex6_xld_data( 7) <= not( ex6_xld_rot_b( 7) and ex6_xld_sgn_b( 3) and ex6_xld_oth_b( 7) ); + + u_xld_or_08: ex6_xld_data( 8) <= not( ex6_xld_rot_b( 8) and ex6_xld_sgn_b( 0) and ex6_xld_oth_b( 8) ); + u_xld_or_09: ex6_xld_data( 9) <= not( ex6_xld_rot_b( 9) and ex6_xld_sgn_b( 0) and ex6_xld_oth_b( 9) ); + u_xld_or_10: ex6_xld_data(10) <= not( ex6_xld_rot_b(10) and ex6_xld_sgn_b( 1) and ex6_xld_oth_b(10) ); + u_xld_or_11: ex6_xld_data(11) <= not( ex6_xld_rot_b(11) and ex6_xld_sgn_b( 1) and ex6_xld_oth_b(11) ); + u_xld_or_12: ex6_xld_data(12) <= not( ex6_xld_rot_b(12) and ex6_xld_sgn_b( 2) and ex6_xld_oth_b(12) ); + u_xld_or_13: ex6_xld_data(13) <= not( ex6_xld_rot_b(13) and ex6_xld_sgn_b( 2) and ex6_xld_oth_b(13) ); + u_xld_or_14: ex6_xld_data(14) <= not( ex6_xld_rot_b(14) and ex6_xld_sgn_b( 3) and ex6_xld_oth_b(14) ); + u_xld_or_15: ex6_xld_data(15) <= not( ex6_xld_rot_b(15) and ex6_xld_sgn_b( 3) and ex6_xld_oth_b(15) ); + + u_xld_or_16: ex6_xld_data(16) <= not( ex6_xld_rot_b(16) and ex6_xld_sgn_b( 0) and ex6_xld_oth_b(16) ); + u_xld_or_17: ex6_xld_data(17) <= not( ex6_xld_rot_b(17) and ex6_xld_sgn_b( 0) and ex6_xld_oth_b(17) ); + u_xld_or_18: ex6_xld_data(18) <= not( ex6_xld_rot_b(18) and ex6_xld_sgn_b( 1) and ex6_xld_oth_b(18) ); + u_xld_or_19: ex6_xld_data(19) <= not( ex6_xld_rot_b(19) and ex6_xld_sgn_b( 1) and ex6_xld_oth_b(19) ); + u_xld_or_20: ex6_xld_data(20) <= not( ex6_xld_rot_b(20) and ex6_xld_sgn_b( 2) and ex6_xld_oth_b(20) ); + u_xld_or_21: ex6_xld_data(21) <= not( ex6_xld_rot_b(21) and ex6_xld_sgn_b( 2) and ex6_xld_oth_b(21) ); + u_xld_or_22: ex6_xld_data(22) <= not( ex6_xld_rot_b(22) and ex6_xld_sgn_b( 3) and ex6_xld_oth_b(22) ); + u_xld_or_23: ex6_xld_data(23) <= not( ex6_xld_rot_b(23) and ex6_xld_sgn_b( 3) and ex6_xld_oth_b(23) ); + + u_xld_or_24: ex6_xld_data(24) <= not( ex6_xld_rot_b(24) and ex6_xld_sgn_b( 0) and ex6_xld_oth_b(24) ); + u_xld_or_25: ex6_xld_data(25) <= not( ex6_xld_rot_b(25) and ex6_xld_sgn_b( 0) and ex6_xld_oth_b(25) ); + u_xld_or_26: ex6_xld_data(26) <= not( ex6_xld_rot_b(26) and ex6_xld_sgn_b( 1) and ex6_xld_oth_b(26) ); + u_xld_or_27: ex6_xld_data(27) <= not( ex6_xld_rot_b(27) and ex6_xld_sgn_b( 1) and ex6_xld_oth_b(27) ); + u_xld_or_28: ex6_xld_data(28) <= not( ex6_xld_rot_b(28) and ex6_xld_sgn_b( 2) and ex6_xld_oth_b(28) ); + u_xld_or_29: ex6_xld_data(29) <= not( ex6_xld_rot_b(29) and ex6_xld_sgn_b( 2) and ex6_xld_oth_b(29) ); + u_xld_or_30: ex6_xld_data(30) <= not( ex6_xld_rot_b(30) and ex6_xld_sgn_b( 3) and ex6_xld_oth_b(30) ); + u_xld_or_31: ex6_xld_data(31) <= not( ex6_xld_rot_b(31) and ex6_xld_sgn_b( 3) and ex6_xld_oth_b(31) ); + + u_xld_or_32: ex6_xld_data(32) <= not( ex6_xld_rot_b(32) and ex6_xld_sgn_b( 4) and ex6_xld_oth_b(32) ); + u_xld_or_33: ex6_xld_data(33) <= not( ex6_xld_rot_b(33) and ex6_xld_sgn_b( 4) and ex6_xld_oth_b(33) ); + u_xld_or_34: ex6_xld_data(34) <= not( ex6_xld_rot_b(34) and ex6_xld_sgn_b( 4) and ex6_xld_oth_b(34) ); + u_xld_or_35: ex6_xld_data(35) <= not( ex6_xld_rot_b(35) and ex6_xld_sgn_b( 4) and ex6_xld_oth_b(35) ); + u_xld_or_36: ex6_xld_data(36) <= not( ex6_xld_rot_b(36) and ex6_xld_sgn_b( 5) and ex6_xld_oth_b(36) ); + u_xld_or_37: ex6_xld_data(37) <= not( ex6_xld_rot_b(37) and ex6_xld_sgn_b( 5) and ex6_xld_oth_b(37) ); + u_xld_or_38: ex6_xld_data(38) <= not( ex6_xld_rot_b(38) and ex6_xld_sgn_b( 5) and ex6_xld_oth_b(38) ); + u_xld_or_39: ex6_xld_data(39) <= not( ex6_xld_rot_b(39) and ex6_xld_sgn_b( 5) and ex6_xld_oth_b(39) ); + + u_xld_or_40: ex6_xld_data(40) <= not( ex6_xld_rot_b(40) and ex6_xld_sgn_b( 4) and ex6_xld_oth_b(40) ); + u_xld_or_41: ex6_xld_data(41) <= not( ex6_xld_rot_b(41) and ex6_xld_sgn_b( 4) and ex6_xld_oth_b(41) ); + u_xld_or_42: ex6_xld_data(42) <= not( ex6_xld_rot_b(42) and ex6_xld_sgn_b( 4) and ex6_xld_oth_b(42) ); + u_xld_or_43: ex6_xld_data(43) <= not( ex6_xld_rot_b(43) and ex6_xld_sgn_b( 4) and ex6_xld_oth_b(43) ); + u_xld_or_44: ex6_xld_data(44) <= not( ex6_xld_rot_b(44) and ex6_xld_sgn_b( 5) and ex6_xld_oth_b(44) ); + u_xld_or_45: ex6_xld_data(45) <= not( ex6_xld_rot_b(45) and ex6_xld_sgn_b( 5) and ex6_xld_oth_b(45) ); + u_xld_or_46: ex6_xld_data(46) <= not( ex6_xld_rot_b(46) and ex6_xld_sgn_b( 5) and ex6_xld_oth_b(46) ); + u_xld_or_47: ex6_xld_data(47) <= not( ex6_xld_rot_b(47) and ex6_xld_sgn_b( 5) and ex6_xld_oth_b(47) ); + + u_xld_or_48: ex6_xld_data(48) <= not( ex6_xld_rot_b(48) and ex6_xld_oth_b(48) ); + u_xld_or_49: ex6_xld_data(49) <= not( ex6_xld_rot_b(49) and ex6_xld_oth_b(49) ); + u_xld_or_50: ex6_xld_data(50) <= not( ex6_xld_rot_b(50) and ex6_xld_oth_b(50) ); + u_xld_or_51: ex6_xld_data(51) <= not( ex6_xld_rot_b(51) and ex6_xld_oth_b(51) ); + u_xld_or_52: ex6_xld_data(52) <= not( ex6_xld_rot_b(52) and ex6_xld_oth_b(52) ); + u_xld_or_53: ex6_xld_data(53) <= not( ex6_xld_rot_b(53) and ex6_xld_oth_b(53) ); + u_xld_or_54: ex6_xld_data(54) <= not( ex6_xld_rot_b(54) and ex6_xld_oth_b(54) ); + u_xld_or_55: ex6_xld_data(55) <= not( ex6_xld_rot_b(55) and ex6_xld_oth_b(55) ); + u_xld_or_56: ex6_xld_data(56) <= not( ex6_xld_rot_b(56) and ex6_xld_oth_b(56) ); + u_xld_or_57: ex6_xld_data(57) <= not( ex6_xld_rot_b(57) and ex6_xld_oth_b(57) ); + u_xld_or_58: ex6_xld_data(58) <= not( ex6_xld_rot_b(58) and ex6_xld_oth_b(58) ); + u_xld_or_59: ex6_xld_data(59) <= not( ex6_xld_rot_b(59) and ex6_xld_oth_b(59) ); + u_xld_or_60: ex6_xld_data(60) <= not( ex6_xld_rot_b(60) and ex6_xld_oth_b(60) ); + u_xld_or_61: ex6_xld_data(61) <= not( ex6_xld_rot_b(61) and ex6_xld_oth_b(61) ); + u_xld_or_62: ex6_xld_data(62) <= not( ex6_xld_rot_b(62) and ex6_xld_oth_b(62) ); + u_xld_or_63: ex6_xld_data(63) <= not( ex6_xld_rot_b(63) and ex6_xld_oth_b(63) ); + + + u_xld_oi: ex6_xld_data_b(0 to 63) <= not( ex6_xld_data (0 to 63) ); + u_dont_do_this: dont_do_this <= not( ex6_xld_data_b(0 to 63) ); + +ex7_xld_data_d <= dont_do_this(64-(2**regmode) to 63); + +ex6_xu_ld_data_b(0 to 63) <= ex6_xld_data_b(0 to 63); + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- FIR Error Reporting +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +DCPerr: tri_direct_err_rpt +generic map(width => 1, expand_type => expand_type) +port map( + vd => vdd, + gd => gnd, + err_in => ex7_ld_par_err(0 to 0), + err_out => dcache_parity(0 to 0) +); + +ex8_ld_par_err_d <= ex7_ld_par_err(0); + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Spare Latches +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +my_spare_latches_d <= not my_spare_latches_q; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Outputs +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +-- D$ Parity Error Detected +xu_pc_err_dcache_parity <= dcache_parity(0); + +-- Debug Data Compare Outputs +lsu_xu_ex2_dvc1_st_cmp <= ex2_st_dvc1_cmp_q and ex2_xu_cmp_val_q; +lsu_xu_ex2_dvc2_st_cmp <= ex2_st_dvc2_cmp_q and ex2_xu_cmp_val_q; +lsu_xu_ex8_dvc1_ld_cmp <= gate(ex8_ld_dvc1_cmp_q, not ex8_ld_par_err_q); +lsu_xu_ex8_dvc2_ld_cmp <= gate(ex8_ld_dvc2_cmp_q, not ex8_ld_par_err_q); +lsu_xu_rel_dvc1_en <= rel_dvc1_val_stg2_q; +lsu_xu_rel_dvc1_cmp <= rel_dvc1_cmp_q; +lsu_xu_rel_dvc2_en <= rel_dvc2_val_stg2_q; +lsu_xu_rel_dvc2_cmp <= rel_dvc2_cmp_q; +lsu_xu_rel_dvc_thrd_id <= rel_dvc_tid_stg2_q; + +-- L2CMDQ signals +ex4_256st_data <= ex4_256st_dataFixUp; + +-- XU data +rel_xu_ld_data <= rel_64ld_data(64-(2**regmode) to 63) & rel_xu_ld_par(0 to ((2**regmode)/8)-1); +lsu_xu_ex6_datc_par_err <= ex6_ld_par_err_int; +ex6_ld_par_err <= ex6_ld_par_err_int; + +-- AXU data +xu_fu_ex5_load_le <= ex5_rel_le_mode_q; + +-- SCAN OUT Gate +abst_scan_out <= gate(abst_scan_out_q, an_ac_scan_dis_dc_b); +time_scan_out <= time_scan_out_q and an_ac_scan_dis_dc_b; +repr_scan_out <= repr_scan_out_q and an_ac_scan_dis_dc_b; +func_scan_out(0) <= func_scan_out_2_q(0) and an_ac_scan_dis_dc_b; +func_scan_out(1) <= func_scan_out_2_q(1) and an_ac_scan_dis_dc_b; +func_scan_out(2) <= func_scan_out_2_q(2) and an_ac_scan_dis_dc_b; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Registers +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +ex3_opsize_reg: tri_rlmreg_p + generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex3_opsize_offset to ex3_opsize_offset + ex3_opsize_d'length-1), + scout => sov0(ex3_opsize_offset to ex3_opsize_offset + ex3_opsize_d'length-1), + din => ex3_opsize_d, + dout => ex3_opsize_q); + +ex3_ovrd_rot_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex3_ovrd_rot_offset), + scout => sov0(ex3_ovrd_rot_offset), + din => ex3_ovrd_rot_d, + dout => ex3_ovrd_rot_q); + +ex4_le_mode_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_ex3_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex4_le_mode_d, + dout(0) => ex4_le_mode_q); + +ex4_le_mode_sel_reg: tri_rlmreg_p +generic map (width => 16, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_ex3_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex4_le_mode_sel_offset to ex4_le_mode_sel_offset + ex4_le_mode_sel_d'length-1), + scout => sov0(ex4_le_mode_sel_offset to ex4_le_mode_sel_offset + ex4_le_mode_sel_d'length-1), + din => ex4_le_mode_sel_d, + dout => ex4_le_mode_sel_q); + +ex4_be_mode_sel_reg: tri_rlmreg_p +generic map (width => 16, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_ex3_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex4_be_mode_sel_offset to ex4_be_mode_sel_offset + ex4_be_mode_sel_d'length-1), + scout => sov0(ex4_be_mode_sel_offset to ex4_be_mode_sel_offset + ex4_be_mode_sel_d'length-1), + din => ex4_be_mode_sel_d, + dout => ex4_be_mode_sel_q); + +ex5_load_hit_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex5_load_hit_offset), + scout => sov0(ex5_load_hit_offset), + din => ex5_load_hit_d, + dout => ex5_load_hit_q); + +ex6_load_hit_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex5_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex6_load_hit_d, + dout(0) => ex6_load_hit_q); + +ex7_load_hit_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex6_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex7_load_hit_offset), + scout => sov0(ex7_load_hit_offset), + din => ex7_load_hit_d, + dout => ex7_load_hit_q); + +ex2_st_data_reg: tri_rlmreg_p +generic map (width => (2**regmode), init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex2_st_data_offset to ex2_st_data_offset + ex2_st_data_d'length-1), + scout => sov0(ex2_st_data_offset to ex2_st_data_offset + ex2_st_data_d'length-1), + din => ex2_st_data_d, + dout => ex2_st_data_q); + +axu_rel_upd_reg: tri_rlmreg_p +generic map (width => 16, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(axu_rel_upd_offset to axu_rel_upd_offset + axu_rel_upd_d'length-1), + scout => sov0(axu_rel_upd_offset to axu_rel_upd_offset + axu_rel_upd_d'length-1), + din => axu_rel_upd_d, + dout => axu_rel_upd_q); + +rel_data_val_reg: tri_rlmreg_p +generic map (width => 16, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(rel_data_val_offset to rel_data_val_offset + rel_data_val_d'length-1), + scout => sov0(rel_data_val_offset to rel_data_val_offset + rel_data_val_d'length-1), + din => rel_data_val_d, + dout => rel_data_val_q); + +rel_addr_stg_reg: tri_rlmreg_p +generic map (width => 58-uprCClassBit+1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(rel_addr_stg_offset to rel_addr_stg_offset + rel_addr_stg_d'length-1), + scout => sov0(rel_addr_stg_offset to rel_addr_stg_offset + rel_addr_stg_d'length-1), + din => rel_addr_stg_d, + dout => rel_addr_stg_q); + +rel_addr_reg: tri_rlmreg_p +generic map (width => 58-uprCClassBit+1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(rel_addr_offset to rel_addr_offset + rel_addr_d'length-1), + scout => sov0(rel_addr_offset to rel_addr_offset + rel_addr_d'length-1), + din => rel_addr_d, + dout => rel_addr_q); + +ex5_axu_data_sel_reg: tri_rlmreg_p +generic map (width => 3, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex5_axu_data_sel_offset to ex5_axu_data_sel_offset + ex5_axu_data_sel_d'length-1), + scout => sov0(ex5_axu_data_sel_offset to ex5_axu_data_sel_offset + ex5_axu_data_sel_d'length-1), + din => ex5_axu_data_sel_d, + dout => ex5_axu_data_sel_q); + +-- Non Scannable Latch +rel_ex3_data_reg: tri_regk + generic map (width => 256, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_ex2_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_ex3_data_d, + dout => rel_ex3_data_q); + +rel_alg_bit_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel_alg_bit_d, + dout(0) => rel_alg_bit_q); + +-- Non Scannable Latch +ex5_stgpr_data_reg: tri_regk + generic map (width => (2**regmode), init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex5_stgpr_data_d, + dout => ex5_stgpr_data_q); + +ex6_axu_data_sel_0reg: tri_regk + generic map (width => 24, init => 2396745, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex6_axu_data_sel_d(0 to 23), + dout => ex6_axu_data_sel_q(0 to 23)); + +ex6_axu_data_sel_1reg: tri_regk + generic map (width => 24, init => 2396745, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex6_axu_data_sel_d(24 to 47), + dout => ex6_axu_data_sel_q(24 to 47)); + +ex3_stgpr_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex3_stgpr_instr_offset), + scout => sov0(ex3_stgpr_instr_offset), + din => ex3_stgpr_instr_d, + dout => ex3_stgpr_instr_q); + +ex4_stgpr_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex4_stgpr_instr_offset), + scout => sov0(ex4_stgpr_instr_offset), + din => ex4_stgpr_instr_d, + dout => ex4_stgpr_instr_q); + +ex3_sdp_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex3_sdp_instr_offset), + scout => sov0(ex3_sdp_instr_offset), + din => ex3_sdp_instr_d, + dout => ex3_sdp_instr_q); + +ex4_sdp_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex4_sdp_instr_offset), + scout => sov0(ex4_sdp_instr_offset), + din => ex4_sdp_instr_d, + dout => ex4_sdp_instr_q); + +ex5_sdp_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex5_sdp_instr_offset), + scout => sov0(ex5_sdp_instr_offset), + din => ex5_sdp_instr_d, + dout => ex5_sdp_instr_q); + +rot_addr_reg: tri_rlmreg_p + generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(rot_addr_offset to rot_addr_offset + rot_addr_d'length-1), + scout => sov0(rot_addr_offset to rot_addr_offset + rot_addr_d'length-1), + din => rot_addr_d, + dout => rot_addr_q); + +ex4_rot_addr_reg: tri_regk + generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex4_rot_addr_d, + dout => ex4_rot_addr_q); + +rot_sel_non_le_reg: tri_rlmreg_p + generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(rot_sel_non_le_offset to rot_sel_non_le_offset + rot_sel_non_le_d'length-1), + scout => sov0(rot_sel_non_le_offset to rot_sel_non_le_offset + rot_sel_non_le_d'length-1), + din => rot_sel_non_le_d, + dout => rot_sel_non_le_q); + +ex4_rot_sel_non_le_reg: tri_regk + generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex4_rot_sel_non_le_d, + dout => ex4_rot_sel_non_le_q); + +ex2_st_dvc1_cmp_reg: tri_regk + generic map (width => ((2**regmode)/8), init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex2_st_dvc1_cmp_d, + dout => ex2_st_dvc1_cmp_q); + +ex5_dvc1_en_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex5_dvc1_en_offset), + scout => sov0(ex5_dvc1_en_offset), + din => ex5_dvc1_en_d, + dout => ex5_dvc1_en_q); + +ex6_dvc1_en_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex6_dvc1_en_offset), + scout => sov0(ex6_dvc1_en_offset), + din => ex6_dvc1_en_d, + dout => ex6_dvc1_en_q); + +ex7_dvc1_en_reg: tri_rlmreg_p +generic map (width => ((2**regmode)/8), init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex7_dvc1_en_offset to ex7_dvc1_en_offset + ex7_dvc1_en_d'length-1), + scout => sov0(ex7_dvc1_en_offset to ex7_dvc1_en_offset + ex7_dvc1_en_d'length-1), + din => ex7_dvc1_en_d, + dout => ex7_dvc1_en_q); + +rel_dvc1_val_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(rel_dvc1_val_offset), + scout => sov0(rel_dvc1_val_offset), + din => rel_dvc1_val_d, + dout => rel_dvc1_val_q); + +ex8_ld_dvc1_cmp_reg: tri_rlmreg_p + generic map (width => ((2**regmode)/8), init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex8_ld_dvc1_cmp_offset to ex8_ld_dvc1_cmp_offset + ex8_ld_dvc1_cmp_d'length-1), + scout => sov0(ex8_ld_dvc1_cmp_offset to ex8_ld_dvc1_cmp_offset + ex8_ld_dvc1_cmp_d'length-1), + din => ex8_ld_dvc1_cmp_d, + dout => ex8_ld_dvc1_cmp_q); + +rel_dvc1_val_stg_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(rel_dvc1_val_stg_offset), + scout => sov0(rel_dvc1_val_stg_offset), + din => rel_dvc1_val_stg_d, + dout => rel_dvc1_val_stg_q); + +rel_dvc1_val_stg2_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(rel_dvc1_val_stg2_offset), + scout => sov0(rel_dvc1_val_stg2_offset), + din => rel_dvc1_val_stg2_d, + dout => rel_dvc1_val_stg2_q); + +rel_dvc1_cmp_reg: tri_regk + generic map (width => ((2**regmode)/8), init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel4_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_dvc1_cmp_d, + dout => rel_dvc1_cmp_q); + +rel_dvc2_val_stg_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(rel_dvc2_val_stg_offset), + scout => sov0(rel_dvc2_val_stg_offset), + din => rel_dvc2_val_stg_d, + dout => rel_dvc2_val_stg_q); + +rel_dvc2_val_stg2_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(rel_dvc2_val_stg2_offset), + scout => sov0(rel_dvc2_val_stg2_offset), + din => rel_dvc2_val_stg2_d, + dout => rel_dvc2_val_stg2_q); + +rel_dvc2_cmp_reg: tri_regk + generic map (width => ((2**regmode)/8), init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel4_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_dvc2_cmp_d, + dout => rel_dvc2_cmp_q); + +ex2_st_dvc2_cmp_reg: tri_regk + generic map (width => ((2**regmode)/8), init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex2_st_dvc2_cmp_d, + dout => ex2_st_dvc2_cmp_q); + +ex5_dvc2_en_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex5_dvc2_en_offset), + scout => sov0(ex5_dvc2_en_offset), + din => ex5_dvc2_en_d, + dout => ex5_dvc2_en_q); + +ex6_dvc2_en_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex6_dvc2_en_offset), + scout => sov0(ex6_dvc2_en_offset), + din => ex6_dvc2_en_d, + dout => ex6_dvc2_en_q); + +ex7_dvc2_en_reg: tri_rlmreg_p +generic map (width => ((2**regmode)/8), init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex7_dvc2_en_offset to ex7_dvc2_en_offset + ex7_dvc2_en_d'length-1), + scout => sov0(ex7_dvc2_en_offset to ex7_dvc2_en_offset + ex7_dvc2_en_d'length-1), + din => ex7_dvc2_en_d, + dout => ex7_dvc2_en_q); + +rel_dvc2_val_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(rel_dvc2_val_offset), + scout => sov0(rel_dvc2_val_offset), + din => rel_dvc2_val_d, + dout => rel_dvc2_val_q); + +ex8_ld_dvc2_cmp_reg: tri_rlmreg_p + generic map (width => ((2**regmode)/8), init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex8_ld_dvc2_cmp_offset to ex8_ld_dvc2_cmp_offset + ex8_ld_dvc2_cmp_d'length-1), + scout => sov0(ex8_ld_dvc2_cmp_offset to ex8_ld_dvc2_cmp_offset + ex8_ld_dvc2_cmp_d'length-1), + din => ex8_ld_dvc2_cmp_d, + dout => ex8_ld_dvc2_cmp_q); + +ex2_optype32_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex2_optype32_offset), + scout => sov0(ex2_optype32_offset), + din => ex2_optype32_d, + dout => ex2_optype32_q); + +ex2_optype16_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex2_optype16_offset), + scout => sov0(ex2_optype16_offset), + din => ex2_optype16_d, + dout => ex2_optype16_q); + +ex2_optype8_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex2_optype8_offset), + scout => sov0(ex2_optype8_offset), + din => ex2_optype8_d, + dout => ex2_optype8_q); + +ex2_optype4_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex2_optype4_offset), + scout => sov0(ex2_optype4_offset), + din => ex2_optype4_d, + dout => ex2_optype4_q); + +ex2_optype2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex2_optype2_offset), + scout => sov0(ex2_optype2_offset), + din => ex2_optype2_d, + dout => ex2_optype2_q); + +ex2_optype1_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex2_optype1_offset), + scout => sov0(ex2_optype1_offset), + din => ex2_optype1_d, + dout => ex2_optype1_q); + +ex2_p_addr_reg: tri_rlmreg_p + generic map (width => 64-uprCClassBit, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex2_p_addr_offset to ex2_p_addr_offset + ex2_p_addr_d'length-1), + scout => sov0(ex2_p_addr_offset to ex2_p_addr_offset + ex2_p_addr_d'length-1), + din => ex2_p_addr_d, + dout => ex2_p_addr_q); + +ex3_fu_st_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_fu_st_val_d, + dout(0) => ex3_fu_st_val_q); + +frc_p_addr_reg: tri_rlmreg_p + generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(frc_p_addr_offset to frc_p_addr_offset + frc_p_addr_d'length-1), + scout => sov0(frc_p_addr_offset to frc_p_addr_offset + frc_p_addr_d'length-1), + din => frc_p_addr_d, + dout => frc_p_addr_q); + +ex2_store_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex2_store_instr_offset), + scout => sov0(ex2_store_instr_offset), + din => ex2_store_instr_d, + dout => ex2_store_instr_q); + +ex3_store_instr_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_store_instr_d, + dout(0) => ex3_store_instr_q); + +ex3_st_rot_sel_reg: tri_regk +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex3_st_rot_sel_d, + dout => ex3_st_rot_sel_q); + +ex2_axu_op_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex2_axu_op_val_offset), + scout => sov0(ex2_axu_op_val_offset), + din => ex2_axu_op_val_d, + dout => ex2_axu_op_val_q); + +ex3_axu_op_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_axu_op_val_d, + dout(0) => ex3_axu_op_val_q); + +ex4_axu_op_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex4_axu_op_val_offset), + scout => sov0(ex4_axu_op_val_offset), + din => ex4_axu_op_val_d, + dout => ex4_axu_op_val_q); + +ex2_xu_cmp_val_reg: tri_rlmreg_p + generic map (width => (2**regmode)/8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex2_xu_cmp_val_offset to ex2_xu_cmp_val_offset + ex2_xu_cmp_val_d'length-1), + scout => sov0(ex2_xu_cmp_val_offset to ex2_xu_cmp_val_offset + ex2_xu_cmp_val_d'length-1), + din => ex2_xu_cmp_val_d, + dout => ex2_xu_cmp_val_q); + +ex2_saxu_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex2_saxu_instr_offset), + scout => sov0(ex2_saxu_instr_offset), + din => ex2_saxu_instr_d, + dout => ex2_saxu_instr_q); + +ex2_sdp_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex2_sdp_instr_offset), + scout => sov0(ex2_sdp_instr_offset), + din => ex2_sdp_instr_d, + dout => ex2_sdp_instr_q); + +ex2_stgpr_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex2_stgpr_instr_offset), + scout => sov0(ex2_stgpr_instr_offset), + din => ex2_stgpr_instr_d, + dout => ex2_stgpr_instr_q); + +ex3_saxu_instr_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_saxu_instr_d, + dout(0) => ex3_saxu_instr_q); + +ex4_saxu_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex4_saxu_instr_offset), + scout => sov0(ex4_saxu_instr_offset), + din => ex4_saxu_instr_d, + dout => ex4_saxu_instr_q); + +ex4_algebraic_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex4_algebraic_offset), + scout => sov0(ex4_algebraic_offset), + din => ex4_algebraic_d, + dout => ex4_algebraic_q); + +ex2_ovrd_rot_sel_reg: tri_rlmreg_p + generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex2_ovrd_rot_sel_offset to ex2_ovrd_rot_sel_offset + ex2_ovrd_rot_sel_d'length-1), + scout => sov0(ex2_ovrd_rot_sel_offset to ex2_ovrd_rot_sel_offset + ex2_ovrd_rot_sel_d'length-1), + din => ex2_ovrd_rot_sel_d, + dout => ex2_ovrd_rot_sel_q); + +ex3_p_addr_reg: tri_regk + generic map (width => 64-uprCClassBit, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex3_p_addr_d, + dout => ex3_p_addr_q); + +ex4_p_addr_reg: tri_rlmreg_p + generic map (width => 64-uprCClassBit, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex4_p_addr_offset to ex4_p_addr_offset + ex4_p_addr_d'length-1), + scout => sov0(ex4_p_addr_offset to ex4_p_addr_offset + ex4_p_addr_d'length-1), + din => ex4_p_addr_d, + dout => ex4_p_addr_q); + +rel_ex3_par_gen_reg: tri_regk + generic map (width => 32, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_ex2_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_ex3_par_gen_d, + dout => rel_ex3_par_gen_q); + +spr_xucr0_dcdis_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(spr_xucr0_dcdis_offset), + scout => sov0(spr_xucr0_dcdis_offset), + din => spr_xucr0_dcdis_d, + dout => spr_xucr0_dcdis_q); + +clkg_ctl_override_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(clkg_ctl_override_offset), + scout => sov0(clkg_ctl_override_offset), + din => clkg_ctl_override_d, + dout => clkg_ctl_override_q); + +rel_dvc_thrd_id_reg: tri_regk + generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_dvc_thrd_id_d, + dout => rel_dvc_thrd_id_q); + +rel_dvc_tid_stg_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(rel_dvc_tid_stg_offset to rel_dvc_tid_stg_offset + rel_dvc_tid_stg_d'length-1), + scout => sov0(rel_dvc_tid_stg_offset to rel_dvc_tid_stg_offset + rel_dvc_tid_stg_d'length-1), + din => rel_dvc_tid_stg_d, + dout => rel_dvc_tid_stg_q); + +rel_dvc_tid_stg2_reg: tri_regk + generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_dvc_tid_stg2_d, + dout => rel_dvc_tid_stg2_q); + +inj_dcache_parity_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(inj_dcache_parity_offset), + scout => sov0(inj_dcache_parity_offset), + din => inj_dcache_parity_d, + dout => inj_dcache_parity_q); + +ex5_stgpr_dp_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex5_stgpr_dp_instr_offset), + scout => sov0(ex5_stgpr_dp_instr_offset), + din => ex5_stgpr_dp_instr_d, + dout => ex5_stgpr_dp_instr_q); + +ex6_stgpr_dp_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex6_stgpr_dp_instr_offset), + scout => sov0(ex6_stgpr_dp_instr_offset), + din => ex6_stgpr_dp_instr_d, + dout => ex6_stgpr_dp_instr_q); + +ex6_stgpr_dp_data_reg: tri_rlmreg_p + generic map (width => 128, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex5_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex6_stgpr_dp_data_offset to ex6_stgpr_dp_data_offset + ex6_stgpr_dp_data_d'length-1), + scout => sov0(ex6_stgpr_dp_data_offset to ex6_stgpr_dp_data_offset + ex6_stgpr_dp_data_d'length-1), + din => ex6_stgpr_dp_data_d, + dout => ex6_stgpr_dp_data_q); + +ex5_rel_le_mode_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex5_rel_le_mode_offset), + scout => sov0(ex5_rel_le_mode_offset), + din => ex5_rel_le_mode_d, + dout => ex5_rel_le_mode_q); + +ex1_ldst_falign_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex1_ldst_falign_offset), + scout => sov0(ex1_ldst_falign_offset), + din => ex1_ldst_falign_d, + dout => ex1_ldst_falign_q); + +ex4_thrd_id_reg: tri_regk + generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex4_thrd_id_d, + dout => ex4_thrd_id_q); + +ex5_thrd_id_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex5_thrd_id_offset to ex5_thrd_id_offset + ex5_thrd_id_d'length-1), + scout => sov0(ex5_thrd_id_offset to ex5_thrd_id_offset + ex5_thrd_id_d'length-1), + din => ex5_thrd_id_d, + dout => ex5_thrd_id_q); + +axu_rel_val_stg1_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(axu_rel_val_stg1_offset), + scout => sov0(axu_rel_val_stg1_offset), + din => axu_rel_val_stg1_d, + dout => axu_rel_val_stg1_q); + +axu_rel_val_stg2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(axu_rel_val_stg2_offset), + scout => sov0(axu_rel_val_stg2_offset), + din => axu_rel_val_stg2_d, + dout => axu_rel_val_stg2_q); + +axu_rel_val_stg3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(axu_rel_val_stg3_offset), + scout => sov0(axu_rel_val_stg3_offset), + din => axu_rel_val_stg3_d, + dout => axu_rel_val_stg3_q); + +rel_256ld_data_stg1_reg: tri_regk +generic map (width => 256, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel4_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_256ld_data_stg1_d, + dout => rel_256ld_data_stg1_q); + +rel_256ld_data_stg2_reg: tri_rlmreg_p +generic map (width => 256, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel5_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(rel_256ld_data_stg2_offset to rel_256ld_data_stg2_offset + rel_256ld_data_stg2_d'length-1), + scout => sov0(rel_256ld_data_stg2_offset to rel_256ld_data_stg2_offset + rel_256ld_data_stg2_d'length-1), + din => rel_256ld_data_stg2_d, + dout => rel_256ld_data_stg2_q); + +rel_axu_le_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(rel_axu_le_val_offset), + scout => sov0(rel_axu_le_val_offset), + din => rel_axu_le_val_d, + dout => rel_axu_le_val_q); + +rel_axu_le_val_stg1_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(rel_axu_le_val_stg1_offset), + scout => sov0(rel_axu_le_val_stg1_offset), + din => rel_axu_le_val_stg1_d, + dout => rel_axu_le_val_stg1_q); + +dcarr_wren_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel4_ex4_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(dcarr_wren_offset), + scout => sov0(dcarr_wren_offset), + din => dcarr_wren_d, + dout => dcarr_wren_q); + +dat_dbg_arr_reg: tri_rlmreg_p +generic map (width => 13, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => trace_bus_enable_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(dat_dbg_arr_offset to dat_dbg_arr_offset + dat_dbg_arr_d'length-1), + scout => sov0(dat_dbg_arr_offset to dat_dbg_arr_offset + dat_dbg_arr_d'length-1), + din => dat_dbg_arr_d, + dout => dat_dbg_arr_q); + +ld_alg_le_sel_reg: tri_rlmreg_p +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ld_alg_le_sel_offset to ld_alg_le_sel_offset + ld_alg_le_sel_d'length-1), + scout => sov0(ld_alg_le_sel_offset to ld_alg_le_sel_offset + ld_alg_le_sel_d'length-1), + din => ld_alg_le_sel_d, + dout => ld_alg_le_sel_q); + +ex4_ld_alg_le_sel_reg: tri_regk +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex4_ld_alg_le_sel_d, + dout => ex4_ld_alg_le_sel_q); + +ex1_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex1_stg_act_offset), + scout => sov0(ex1_stg_act_offset), + din => ex1_stg_act_d, + dout => ex1_stg_act_q); + +ex2_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex2_stg_act_offset), + scout => sov0(ex2_stg_act_offset), + din => ex2_stg_act_d, + dout => ex2_stg_act_q); + +ex3_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex3_stg_act_offset), + scout => sov0(ex3_stg_act_offset), + din => ex3_stg_act_d, + dout => ex3_stg_act_q); + +ex4_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex4_stg_act_offset), + scout => sov0(ex4_stg_act_offset), + din => ex4_stg_act_d, + dout => ex4_stg_act_q); + +ex5_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex5_stg_act_offset), + scout => sov0(ex5_stg_act_offset), + din => ex5_stg_act_d, + dout => ex5_stg_act_q); + +ex6_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex6_stg_act_offset), + scout => sov0(ex6_stg_act_offset), + din => ex6_stg_act_d, + dout => ex6_stg_act_q); + +rel1_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(rel1_stg_act_offset), + scout => sov0(rel1_stg_act_offset), + din => rel1_stg_act_d, + dout => rel1_stg_act_q); + +rel2_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(rel2_stg_act_offset), + scout => sov0(rel2_stg_act_offset), + din => rel2_stg_act_d, + dout => rel2_stg_act_q); + +rel3_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(rel3_stg_act_offset), + scout => sov0(rel3_stg_act_offset), + din => rel3_stg_act_d, + dout => rel3_stg_act_q); + +rel4_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(rel4_stg_act_offset), + scout => sov0(rel4_stg_act_offset), + din => rel4_stg_act_d, + dout => rel4_stg_act_q); + +rel5_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(rel5_stg_act_offset), + scout => sov0(rel5_stg_act_offset), + din => rel5_stg_act_d, + dout => rel5_stg_act_q); + +rel2_ex2_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(rel2_ex2_stg_act_offset), + scout => sov0(rel2_ex2_stg_act_offset), + din => rel2_ex2_stg_act_d, + dout => rel2_ex2_stg_act_q); + +rel3_ex3_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(rel3_ex3_stg_act_offset), + scout => sov0(rel3_ex3_stg_act_offset), + din => rel3_ex3_stg_act_d, + dout => rel3_ex3_stg_act_q); + +rel4_ex4_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(rel4_ex4_stg_act_offset), + scout => sov0(rel4_ex4_stg_act_offset), + din => rel4_ex4_stg_act_d, + dout => rel4_ex4_stg_act_q); + +ex8_ld_par_err_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv0(ex8_ld_par_err_offset), + scout => sov0(ex8_ld_par_err_offset), + din => ex8_ld_par_err_d, + dout => ex8_ld_par_err_q); + +my_spare0_lcb : entity tri.tri_lcbnd(tri_lcbnd) +generic map (expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + d1clk => my_spare0_d1clk, + d2clk => my_spare0_d2clk, + lclk => my_spare0_lclk); +my_spare_latches_reg: entity tri.tri_inv_nlats(tri_inv_nlats) +generic map (width => 8, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + lclk => my_spare0_lclk, + d1clk => my_spare0_d1clk, + d2clk => my_spare0_d2clk, + scanin => siv0(my_spare_latches_offset to my_spare_latches_offset + my_spare_latches_d'length-1), + scanout => sov0(my_spare_latches_offset to my_spare_latches_offset + my_spare_latches_d'length-1), + d => my_spare_latches_d, + qb => my_spare_latches_q); + +----------------------------------------------------------------------- +-- Func_Scan1 latches +----------------------------------------------------------------------- +rel_data_reg: tri_rlmreg_p +generic map (width => 256, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv1(rel_data_offset to rel_data_offset + rel_data_d'length-1), + scout => sov1(rel_data_offset to rel_data_offset + rel_data_d'length-1), + din => rel_data_d, + dout => rel_data_q); + +rel_algebraic_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv1(rel_algebraic_offset), + scout => sov1(rel_algebraic_offset), + din => rel_algebraic_d, + dout => rel_algebraic_q); + +rel_rot_sel_reg: tri_rlmreg_p +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv1(rel_rot_sel_offset to rel_rot_sel_offset + rel_rot_sel_d'length-1), + scout => sov1(rel_rot_sel_offset to rel_rot_sel_offset + rel_rot_sel_d'length-1), + din => rel_rot_sel_d, + dout => rel_rot_sel_q); + +rel_op_size_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv1(rel_op_size_offset to rel_op_size_offset + rel_op_size_d'length-1), + scout => sov1(rel_op_size_offset to rel_op_size_offset + rel_op_size_d'length-1), + din => rel_op_size_d, + dout => rel_op_size_q); + +rel_le_mode_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv1(rel_le_mode_offset), + scout => sov1(rel_le_mode_offset), + din => rel_le_mode_d, + dout => rel_le_mode_q); + +rel_dvc1_en_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv1(rel_dvc1_en_offset), + scout => sov1(rel_dvc1_en_offset), + din => rel_dvc1_en_d, + dout => rel_dvc1_en_q); + +rel_dvc2_en_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv1(rel_dvc2_en_offset), + scout => sov1(rel_dvc2_en_offset), + din => rel_dvc2_en_d, + dout => rel_dvc2_en_q); + +rel_upd_gpr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv1(rel_upd_gpr_offset), + scout => sov1(rel_upd_gpr_offset), + din => rel_upd_gpr_d, + dout => rel_upd_gpr_q); + +rel_axu_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv1(rel_axu_val_offset), + scout => sov1(rel_axu_val_offset), + din => rel_axu_val_d, + dout => rel_axu_val_q); + +rel_ci_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv1(rel_ci_offset), + scout => sov1(rel_ci_offset), + din => rel_ci_d, + dout => rel_ci_q); + +rel_ci_dly_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel_ci_dly_d, + dout(0) => rel_ci_dly_q); + +rel_thrd_id_reg: tri_rlmreg_p + generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv1(rel_thrd_id_offset to rel_thrd_id_offset + rel_thrd_id_d'length-1), + scout => sov1(rel_thrd_id_offset to rel_thrd_id_offset + rel_thrd_id_d'length-1), + din => rel_thrd_id_d, + dout => rel_thrd_id_q); + +rel_data_val_stg_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv1(rel_data_val_stg_offset), + scout => sov1(rel_data_val_stg_offset), + din => rel_data_val_stg_d, + dout => rel_data_val_stg_q); + +rel_data_val_stg_dly_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel_data_val_stg_dly_d, + dout(0) => rel_data_val_stg_dly_q); + +spr_dvc1_dbg_reg: tri_ser_rlmreg_p +generic map (width => (2**regmode), init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_dvc1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv1(spr_dvc1_dbg_offset to spr_dvc1_dbg_offset + spr_dvc1_dbg_d'length-1), + scout => sov1(spr_dvc1_dbg_offset to spr_dvc1_dbg_offset + spr_dvc1_dbg_d'length-1), + din => spr_dvc1_dbg_d, + dout => spr_dvc1_dbg_q); + +spr_dvc2_dbg_reg: tri_ser_rlmreg_p +generic map (width => (2**regmode), init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => spr_dvc2_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv1(spr_dvc2_dbg_offset to spr_dvc2_dbg_offset + spr_dvc2_dbg_d'length-1), + scout => sov1(spr_dvc2_dbg_offset to spr_dvc2_dbg_offset + spr_dvc2_dbg_d'length-1), + din => spr_dvc2_dbg_d, + dout => spr_dvc2_dbg_q); + +ex7_xld_data_reg: tri_regk +generic map (width => (2**regmode), init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex6_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex7_xld_data_d, + dout => ex7_xld_data_q); + +trace_bus_enable_latch : tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 0) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv1(trace_bus_enable_offset), + scout => sov1(trace_bus_enable_offset), + din => pc_xu_trace_bus_enable, + dout => trace_bus_enable_q); + +dat_debug_mux_ctrls_reg: tri_rlmreg_p + generic map (width => 2, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv1(dat_debug_mux_ctrls_offset to dat_debug_mux_ctrls_offset + dat_debug_mux_ctrls_q'length-1), + scout => sov1(dat_debug_mux_ctrls_offset to dat_debug_mux_ctrls_offset + dat_debug_mux_ctrls_q'length-1), + din => lsudat_debug_mux_ctrls, + dout => dat_debug_mux_ctrls_q); + +dat_dbg_st_dat_reg: tri_rlmreg_p + generic map (width => 64, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => trace_bus_enable_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv1(dat_dbg_st_dat_offset to dat_dbg_st_dat_offset + dat_dbg_st_dat_d'length-1), + scout => sov1(dat_dbg_st_dat_offset to dat_dbg_st_dat_offset + dat_dbg_st_dat_d'length-1), + din => dat_dbg_st_dat_d, + dout => dat_dbg_st_dat_q); + +----------------------------------------------------------------------- +-- abist latches +----------------------------------------------------------------------- +abist_reg: tri_rlmreg_p + generic map (init => 0, expand_type => expand_type, width => 21, needs_sreset => 0) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => pc_xu_abist_ena_dc, + thold_b => abst_sl_thold_0_b, + sg => sg_0, + forcee => abst_sl_force, + delay_lclkr => delay_lclkr_dc(5), + mpw1_b => mpw1_dc_b(5), + mpw2_b => mpw2_dc_b, + d_mode => d_mode_dc, + scin => abist_siv(1 to 21), + scout => abist_sov(1 to 21), + din(0 to 1) => pc_xu_abist_g6t_bw, + din(2 to 5) => pc_xu_abist_di_g6t_2r, + din(6) => pc_xu_abist_wl512_comp_ena, + din(7 to 10) => pc_xu_abist_dcomp_g6t_2r, + din(11 to 19) => pc_xu_abist_raddr_0, + din(20) => pc_xu_abist_g6t_r_wb, + dout(0 to 1) => pc_xu_abist_g6t_bw_q, + dout(2 to 5) => pc_xu_abist_di_g6t_2r_q, + dout(6) => pc_xu_abist_wl512_comp_ena_q, + dout(7 to 10) => pc_xu_abist_dcomp_g6t_2r_q, + dout(11 to 19) => pc_xu_abist_raddr_0_q, + dout(20) => pc_xu_abist_g6t_r_wb_q); + +------------------------------------------------- +-- Pervasive +------------------------------------------------- +perv_2to1_reg: tri_plat + generic map (width => 9, expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_xu_ccflush_dc, + din(0) => func_nsl_thold_2, + din(1) => func_sl_thold_2, + din(2) => ary_nsl_thold_2, + din(3) => abst_sl_thold_2, + din(4) => time_sl_thold_2, + din(5) => repr_sl_thold_2, + din(6) => bolt_sl_thold_2, + din(7) => sg_2, + din(8) => fce_2, + q(0) => func_nsl_thold_1, + q(1) => func_sl_thold_1, + q(2) => ary_nsl_thold_1, + q(3) => abst_sl_thold_1, + q(4) => time_sl_thold_1, + q(5) => repr_sl_thold_1, + q(6) => bolt_sl_thold_1, + q(7) => sg_1, + q(8) => fce_1); + +perv_1to0_reg: tri_plat + generic map (width => 9, expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_xu_ccflush_dc, + din(0) => func_nsl_thold_1, + din(1) => func_sl_thold_1, + din(2) => ary_nsl_thold_1, + din(3) => abst_sl_thold_1, + din(4) => time_sl_thold_1, + din(5) => repr_sl_thold_1, + din(6) => bolt_sl_thold_1, + din(7) => sg_1, + din(8) => fce_1, + q(0) => func_nsl_thold_0, + q(1) => func_sl_thold_0, + q(2) => ary_nsl_thold_0, + q(3) => abst_sl_thold_0, + q(4) => time_sl_thold_0, + q(5) => repr_sl_thold_0, + q(6) => bolt_sl_thold_0, + q(7) => sg_0, + q(8) => fce_0); + +perv_lcbor_func_sl: tri_lcbor + generic map (expand_type => expand_type) +port map (clkoff_b => clkoff_dc_b, + thold => func_sl_thold_0, + sg => sg_0, + act_dis => tidn, + forcee => func_sl_force, + thold_b => func_sl_thold_0_b); + +perv_lcbor_func_nsl: tri_lcbor + generic map (expand_type => expand_type) +port map (clkoff_b => clkoff_dc_b, + thold => func_nsl_thold_0, + sg => fce_0, + act_dis => tidn, + forcee => func_nsl_force, + thold_b => func_nsl_thold_0_b); + +perv_lcbor_abst_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_dc_b, + thold => abst_sl_thold_0, + sg => sg_0, + act_dis => tidn, + forcee => abst_sl_force, + thold_b => abst_sl_thold_0_b); + +-- LCBs for scan only staging latches +slat_force <= sg_0; +abst_slat_thold_b <= NOT abst_sl_thold_0; +time_slat_thold_b <= NOT time_sl_thold_0; +repr_slat_thold_b <= NOT repr_sl_thold_0; +func_slat_thold_b <= NOT func_sl_thold_0; + +perv_lcbs_abst: tri_lcbs + generic map (expand_type => expand_type ) + port map ( + vd => vdd, + gd => gnd, + delay_lclkr => delay_lclkr_dc(5), + nclk => nclk, + forcee => slat_force, + thold_b => abst_slat_thold_b, + dclk => abst_slat_d2clk, + lclk => abst_slat_lclk ); + +perv_abst_stg: tri_slat_scan + generic map (width => 4, init => "0000", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => abst_slat_d2clk, + lclk => abst_slat_lclk, + scan_in(0 to 1) => abst_scan_in, + scan_in(2 to 3) => abst_scan_out_int, + scan_out(0 to 1) => abst_scan_in_q, + scan_out(2 to 3) => abst_scan_out_q ); + +perv_lcbs_time: tri_lcbs + generic map (expand_type => expand_type ) + port map ( + vd => vdd, + gd => gnd, + delay_lclkr => delay_lclkr_dc(5), + nclk => nclk, + forcee => slat_force, + thold_b => time_slat_thold_b, + dclk => time_slat_d2clk, + lclk => time_slat_lclk ); + +perv_time_stg: tri_slat_scan + generic map (width => 2, init => "00", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => time_slat_d2clk, + lclk => time_slat_lclk, + scan_in(0) => time_scan_in, + scan_in(1) => time_scan_out_int, + scan_out(0) => time_scan_in_q, + scan_out(1) => time_scan_out_q ); + +perv_lcbs_repr: tri_lcbs + generic map (expand_type => expand_type ) + port map ( + vd => vdd, + gd => gnd, + delay_lclkr => delay_lclkr_dc(5), + nclk => nclk, + forcee => slat_force, + thold_b => repr_slat_thold_b, + dclk => repr_slat_d2clk, + lclk => repr_slat_lclk ); + +perv_repr_stg: tri_slat_scan + generic map (width => 2, init => "00", expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => repr_slat_d2clk, + lclk => repr_slat_lclk, + scan_in(0) => repr_scan_in, + scan_in(1) => repr_scan_out_int, + scan_out(0) => repr_scan_in_q, + scan_out(1) => repr_scan_out_q ); + +perv_lcbs_func: tri_lcbs + generic map (expand_type => expand_type ) + port map ( + vd => vdd, + gd => gnd, + delay_lclkr => delay_lclkr_dc(5), + nclk => nclk, + forcee => slat_force, + thold_b => func_slat_thold_b, + dclk => func_slat_d2clk, + lclk => func_slat_lclk ); + +perv_func_stg: tri_slat_scan + generic map (width => 12, init => (1 to 12=>'0'), expand_type => expand_type) + port map ( vd => vdd, + gd => gnd, + dclk => func_slat_d2clk, + lclk => func_slat_lclk, + scan_in(0) => func_scan_in(0), + scan_in(1) => func_scan_in(1), + scan_in(2) => func_scan_in(2), + scan_in(3) => func_scan_out_int(0), + scan_in(4) => func_scan_out_int(1), + scan_in(5) => func_scan_out_int(2), + scan_in(6) => func_scan_in_q(0), + scan_in(7) => func_scan_in_q(1), + scan_in(8) => func_scan_in_q(2), + scan_in(9) => func_scan_out_q(0), + scan_in(10) => func_scan_out_q(1), + scan_in(11) => func_scan_out_q(2), + scan_out(0) => func_scan_in_q(0), + scan_out(1) => func_scan_in_q(1), + scan_out(2) => func_scan_in_q(2), + scan_out(3) => func_scan_out_q(0), + scan_out(4) => func_scan_out_q(1), + scan_out(5) => func_scan_out_q(2), + scan_out(6) => func_scan_in_2_q(0), + scan_out(7) => func_scan_in_2_q(1), + scan_out(8) => func_scan_in_2_q(2), + scan_out(9) => func_scan_out_2_q(0), + scan_out(10)=> func_scan_out_2_q(1), + scan_out(11)=> func_scan_out_2_q(2) + ); + +siv0 <= sov0(1 to scan_right0) & func_scan_in_2_q(0); +func_scan_out_int(0) <= sov0(0); + +siv1 <= sov1(1 to scan_right1) & func_scan_in_2_q(1); +func_scan_out_int(1) <= sov1(0); + +abist_siv <= abist_sov(1 to abist_sov'right) & abst_scan_in_q(0); +abst_scan_out_int(0) <= abist_sov(0); + +end xuq_lsu_data; diff --git a/rel/src/vhdl/work/xuq_lsu_data_ld.vhdl b/rel/src/vhdl/work/xuq_lsu_data_ld.vhdl new file mode 100644 index 0000000..a1d037b --- /dev/null +++ b/rel/src/vhdl/work/xuq_lsu_data_ld.vhdl @@ -0,0 +1,562 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XU LSU Load Data Rotator Wrapper +-- + +library ibm, ieee, work, tri, support; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use tri.tri_latches_pkg.all; +use support.power_logic_pkg.all; + +-- ########################################################################################## +-- VHDL Contents +-- 1) 1 16Byte input (suppose to reflect reading 8 ways of L1 D$, Selection taken place in EX2) +-- 2) 16 Byte Reload Bus +-- 3) 16 Byte Unaligned Rotator +-- 4) Little Endian Support for 2,4,8,16 Byte Operations +-- 5) Contains Fixed Point Unit (FXU) 8 Byte Load Path +-- 6) Contains Auxilary Unit (AXU) 16 Byte Load Path +-- ########################################################################################## + + +entity xuq_lsu_data_ld is +generic(expand_type : integer := 2; -- 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) + regmode : integer := 6; -- Register Mode 5 = 32bit, 6 = 64bit + l_endian_m : integer := 1); -- 1 = little endian mode enabled, 0 = little endian mode disabled +port( + + -- Acts to latches + ex3_stg_act :in std_ulogic; + ex4_stg_act :in std_ulogic; + ex5_stg_act :in std_ulogic; + + -- Execution Pipe Load Data Rotator Controls + ex3_opsize :in std_ulogic_vector(0 to 5); + ex3_algebraic :in std_ulogic; + ex4_ld_rot_sel :in std_ulogic_vector(0 to 4); + ex4_ld_alg_sel :in std_ulogic_vector(0 to 4); + ex4_le_mode :in std_ulogic; + ex5_ld_data :in std_ulogic_vector(0 to 255); + ex5_ld_data_par :in std_ulogic_vector(0 to 31); + ex6_par_chk_val :in std_ulogic; -- EX6 Parity Error Check is Valid + + -- Debug Bus + trace_bus_enable :in std_ulogic; + dat_debug_mux_ctrls :in std_ulogic_vector(2 to 3); + dat_dbg_ld_dat :out std_ulogic_vector(0 to 63); + + -- Rotated Data + ld_swzl_data :out std_ulogic_vector(0 to 255); + ex6_ld_alg_bit :out std_ulogic_vector(0 to 5); + ex6_ld_dvc_byte_mask :out std_ulogic_vector((64-(2**regmode))/8 to 7); + + ex6_ld_par_err :out std_ulogic; -- EX6 Parity Error Detected on the Load Data + ex7_ld_par_err :out std_ulogic_vector(0 to 1); -- EX7 Parity Error Detected on the Load Data + + -- Pervasive + vdd :inout power_logic; + gnd :inout power_logic; + nclk :in clk_logic; + sg_0 :in std_ulogic; + func_sl_thold_0_b :in std_ulogic; + func_sl_force :in std_ulogic; + func_nsl_thold_0_b :in std_ulogic; + func_nsl_force :in std_ulogic; + d_mode_dc :in std_ulogic; + delay_lclkr_dc :in std_ulogic; + mpw1_dc_b :in std_ulogic; + mpw2_dc_b :in std_ulogic; + scan_in :in std_ulogic; + scan_out :out std_ulogic +); +-- synopsys translate_off +-- synopsys translate_on +end xuq_lsu_data_ld; +---- +architecture xuq_lsu_data_ld of xuq_lsu_data_ld is + +---------------------------- +-- components +---------------------------- + +---------------------------- +-- constants +---------------------------- +constant ex5_opsize_offset :natural := 0; +constant ex5_algebraic_offset :natural := ex5_opsize_offset + 6; +constant rotate_select_offset :natural := ex5_algebraic_offset + 1; +constant le_mode_select_offset :natural := rotate_select_offset + 5; +constant ex6_ld_data_par_offset :natural := le_mode_select_offset + 1; +constant ex5_ld_alg_sel_offset :natural := ex6_ld_data_par_offset + 32; +constant ex7_ld_par_err_offset :natural := ex5_ld_alg_sel_offset + 5; +constant my_spare_latches_offset :natural := ex7_ld_par_err_offset + 2; +constant scan_right :natural := my_spare_latches_offset + 14 - 1; + +---------------------------- +-- signals +---------------------------- + +signal le_mode_select_d :std_ulogic; +signal le_mode_select_q :std_ulogic; +signal ex4_opsize_d :std_ulogic_vector(0 to 5); +signal ex4_opsize_q :std_ulogic_vector(0 to 5); +signal ex5_opsize_d :std_ulogic_vector(0 to 5); +signal ex5_opsize_q :std_ulogic_vector(0 to 5); +signal ex6_opsize_d :std_ulogic_vector(2 to 5); +signal ex6_opsize_q :std_ulogic_vector(2 to 5); +signal ex4_algebraic_d :std_ulogic; +signal ex4_algebraic_q :std_ulogic; +signal ex5_algebraic_d :std_ulogic; +signal ex5_algebraic_q :std_ulogic; +signal ex6_ld_data :std_ulogic_vector(0 to 255); +signal ex6_ld_data_rot :std_ulogic_vector(0 to 255); +signal rotate_select_d :std_ulogic_vector(0 to 4); +signal rotate_select_q :std_ulogic_vector(0 to 4); +signal ex6_ld_data_par_d :std_ulogic_vector(0 to 31); +signal ex6_ld_data_par_q :std_ulogic_vector(0 to 31); +signal par_err_byte :std_ulogic_vector(0 to 31); +signal par_err_det :std_ulogic; +signal ex5_ld_alg_sel_d :std_ulogic_vector(0 to 4); +signal ex5_ld_alg_sel_q :std_ulogic_vector(0 to 4); +signal ex7_ld_par_err_d :std_ulogic_vector(0 to 1); +signal ex7_ld_par_err_q :std_ulogic_vector(0 to 1); +signal ex6_par_err_det1_b :std_ulogic; +signal ex6_par_err_det1 :std_ulogic; +signal ex6_par_err_det2_b :std_ulogic; +signal ex6_par_err_det2 :std_ulogic; +signal ld_byte_mask :std_ulogic_vector(0 to 7); +signal my_spare0_lclk :clk_logic; +signal my_spare0_d1clk :std_ulogic; +signal my_spare0_d2clk :std_ulogic; +signal my_spare_latches_d :std_ulogic_vector(0 to 13); +signal my_spare_latches_q :std_ulogic_vector(0 to 13); +signal ex6_load_data0 :std_ulogic_vector(0 to 63); +signal ex6_load_data1 :std_ulogic_vector(0 to 63); +signal ex6_load_data2 :std_ulogic_vector(0 to 63); +signal ex6_load_data3 :std_ulogic_vector(0 to 63); +signal dat_dbg_ld_dat_d :std_ulogic_vector(0 to 63); +signal dat_dbg_ld_dat_q :std_ulogic_vector(0 to 63); + +signal tiup :std_ulogic; +signal siv :std_ulogic_vector(0 to scan_right); +signal sov :std_ulogic_vector(0 to scan_right); +signal rot_scan_in :std_ulogic_vector(0 to 7); +signal rot_scan_out :std_ulogic_vector(0 to 7); + + + +begin + +-- ############################################################################################# +-- Inputs +-- ############################################################################################# + +tiup <= '1'; + +ex4_opsize_d <= ex3_opsize; +ex5_opsize_d <= ex4_opsize_q; +ex6_opsize_d <= ex5_opsize_q(2 to 5); +ex4_algebraic_d <= ex3_algebraic; +ex5_algebraic_d <= ex4_algebraic_q; +rotate_select_d <= ex4_ld_rot_sel; +ex5_ld_alg_sel_d <= ex4_ld_alg_sel; +le_mode_select_d <= ex4_le_mode; +ex6_ld_data_par_d <= ex5_ld_data_par; +-- ############################################################################################# + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Debug Bus +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +ldDbgData : for byte in 0 to 7 generate begin + ex6_load_data0(byte*8 to (byte*8)+7) <= ex6_ld_data(byte+0) & ex6_ld_data(byte+32) & ex6_ld_data(byte+64) & ex6_ld_data(byte+96) & + ex6_ld_data(byte+128) & ex6_ld_data(byte+160) & ex6_ld_data(byte+192) & ex6_ld_data(byte+224); + ex6_load_data1(byte*8 to (byte*8)+7) <= ex6_ld_data(8+byte+0) & ex6_ld_data(8+byte+32) & ex6_ld_data(8+byte+64) & ex6_ld_data(8+byte+96) & + ex6_ld_data(8+byte+128) & ex6_ld_data(8+byte+160) & ex6_ld_data(8+byte+192) & ex6_ld_data(8+byte+224); + ex6_load_data2(byte*8 to (byte*8)+7) <= ex6_ld_data(16+byte+0) & ex6_ld_data(16+byte+32) & ex6_ld_data(16+byte+64) & ex6_ld_data(16+byte+96) & + ex6_ld_data(16+byte+128) & ex6_ld_data(16+byte+160) & ex6_ld_data(16+byte+192) & ex6_ld_data(16+byte+224); + ex6_load_data3(byte*8 to (byte*8)+7) <= ex6_ld_data(24+byte+0) & ex6_ld_data(24+byte+32) & ex6_ld_data(24+byte+64) & ex6_ld_data(24+byte+96) & + ex6_ld_data(24+byte+128) & ex6_ld_data(24+byte+160) & ex6_ld_data(24+byte+192) & ex6_ld_data(24+byte+224); +end generate ldDbgData; + +with dat_debug_mux_ctrls(2 to 3) select + dat_dbg_ld_dat_d <= ex6_load_data0 when "00", + ex6_load_data1 when "01", + ex6_load_data2 when "10", + ex6_load_data3 when others; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Parity Error Check +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +-- Parity Error Check Per Byte +par_Bdet : for t in 0 to 31 generate begin + par_err_byte(t) <= ex6_ld_data(t+0) xor ex6_ld_data(t+32) xor ex6_ld_data(t+64) xor ex6_ld_data(t+96) xor + ex6_ld_data(t+128) xor ex6_ld_data(t+160) xor ex6_ld_data(t+192) xor ex6_ld_data(t+224) xor + ex6_ld_data_par_q(t); +end generate par_Bdet; + +-- Parity Error Detected +par_err_det <= or_reduce(par_err_byte); + +ex6par_err1_nand2 : ex6_par_err_det1_b <= not (par_err_det and ex6_par_chk_val); +ex6par_err1_inv : ex6_par_err_det1 <= not (ex6_par_err_det1_b); + +ex7_ld_par_err_d <= (others=>ex6_par_err_det1); +-- ############################################################################################# + +-- ############################################################################################# +-- 32 Byte Rotator +-- ############################################################################################# + +l1dcrotr : for bit in 0 to 7 generate begin + sgrp : if (bit = 0) generate + begin + bits : entity work.xuq_lsu_data_rot32s_ru(xuq_lsu_data_rot32s_ru) + generic map(expand_type => expand_type) + port map ( + opsize => ex5_opsize_q, + le => le_mode_select_q, + rotate_sel => rotate_select_q, + algebraic => ex5_algebraic_q, + algebraic_sel => ex5_ld_alg_sel_q, + + data => ex5_ld_data(bit*32 to (bit*32)+31), + data_latched => ex6_ld_data(bit*32 to (bit*32)+31), + data_rot => ex6_ld_data_rot(bit*32 to (bit*32)+31), + algebraic_bit => ex6_ld_alg_bit, + + vdd => vdd, + gnd => gnd, + nclk => nclk, + act => ex5_stg_act, + func_sl_force => func_sl_force, + delay_lclkr_dc => delay_lclkr_dc, + mpw1_dc_b => mpw1_dc_b, + mpw2_dc_b => mpw2_dc_b, + func_sl_thold_0_b => func_sl_thold_0_b, + sg_0 => sg_0, + scan_in => rot_scan_in(bit), + scan_out => rot_scan_out(bit) + ); + end generate sgrp; + grp : if (bit /= 0) generate + begin + bits : entity work.xuq_lsu_data_rot32_ru(xuq_lsu_data_rot32_ru) + generic map(expand_type => expand_type) + port map ( + opsize => ex5_opsize_q, + le => le_mode_select_q, + rotate_sel => rotate_select_q, + + data => ex5_ld_data(bit*32 to (bit*32)+31), + data_latched => ex6_ld_data(bit*32 to (bit*32)+31), + data_rot => ex6_ld_data_rot(bit*32 to (bit*32)+31), + + vdd => vdd, + gnd => gnd, + nclk => nclk, + act => ex5_stg_act, + func_sl_force => func_sl_force, + delay_lclkr_dc => delay_lclkr_dc, + mpw1_dc_b => mpw1_dc_b, + mpw2_dc_b => mpw2_dc_b, + func_sl_thold_0_b => func_sl_thold_0_b, + sg_0 => sg_0, + scan_in => rot_scan_in(bit), + scan_out => rot_scan_out(bit) + ); + end generate grp; +end generate l1dcrotr; + +-- ############################################################################################# + +-- ############################################################################################# +-- Op Size Mask Generation +-- ############################################################################################# + +with ex6_opsize_q select + ld_byte_mask <= x"01" when "0001", + x"03" when "0010", + x"0F" when "0100", + x"FF" when others; + +ex6_ld_dvc_byte_mask <= ld_byte_mask((64-(2**regmode))/8 to 7); + +ld256data : for t in 0 to 31 generate begin + ld_swzl_data(t*8 to (t*8)+7) <= ex6_ld_data_rot(t) & ex6_ld_data_rot(t+32) & ex6_ld_data_rot(t+64) & ex6_ld_data_rot(t+96) & + ex6_ld_data_rot(t+128) & ex6_ld_data_rot(t+160) & ex6_ld_data_rot(t+192) & ex6_ld_data_rot(t+224); +end generate ld256data; + +-- ############################################################################################# + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Spare Latches +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +my_spare_latches_d <= not my_spare_latches_q; + +-- ############################################################################################# +-- Outputs +-- ############################################################################################# + + +ex6par_err2_nand2 : ex6_par_err_det2_b <= not (par_err_det and ex6_par_chk_val); +ex6par_err2_inv : ex6_par_err_det2 <= not (ex6_par_err_det2_b); + +ex6_ld_par_err <= ex6_par_err_det2; +ex7_ld_par_err <= ex7_ld_par_err_q; + +dat_dbg_ld_dat <= dat_dbg_ld_dat_q; +-- ############################################################################################# + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Registers +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +ex4_opsize_reg: tri_regk + generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex4_opsize_d, + dout => ex4_opsize_q); + +ex5_opsize_reg: tri_rlmreg_p + generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_opsize_offset to ex5_opsize_offset + ex5_opsize_d'length-1), + scout => sov(ex5_opsize_offset to ex5_opsize_offset + ex5_opsize_d'length-1), + din => ex5_opsize_d, + dout => ex5_opsize_q); + +ex6_opsize_reg: tri_regk + generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex5_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex6_opsize_d, + dout => ex6_opsize_q); + +ex4_algebraic_reg: tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex4_algebraic_d, + dout(0) => ex4_algebraic_q); + +ex5_algebraic_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_algebraic_offset), + scout => sov(ex5_algebraic_offset), + din => ex5_algebraic_d, + dout => ex5_algebraic_q); + +rotate_select_reg: tri_rlmreg_p + generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rotate_select_offset to rotate_select_offset + rotate_select_d'length-1), + scout => sov(rotate_select_offset to rotate_select_offset + rotate_select_d'length-1), + din => rotate_select_d, + dout => rotate_select_q); + +le_mode_select_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(le_mode_select_offset), + scout => sov(le_mode_select_offset), + din => le_mode_select_d, + dout => le_mode_select_q); + +ex6_ld_data_par_reg: tri_rlmreg_p +generic map (width => 32, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex5_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_ld_data_par_offset to ex6_ld_data_par_offset + ex6_ld_data_par_d'length-1), + scout => sov(ex6_ld_data_par_offset to ex6_ld_data_par_offset + ex6_ld_data_par_d'length-1), + din => ex6_ld_data_par_d, + dout => ex6_ld_data_par_q); + +ex5_ld_alg_sel_reg: tri_rlmreg_p +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_ld_alg_sel_offset to ex5_ld_alg_sel_offset + ex5_ld_alg_sel_d'length-1), + scout => sov(ex5_ld_alg_sel_offset to ex5_ld_alg_sel_offset + ex5_ld_alg_sel_d'length-1), + din => ex5_ld_alg_sel_d, + dout => ex5_ld_alg_sel_q); + +ex7_ld_par_err_reg: tri_rlmreg_p + generic map (width => 2, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex7_ld_par_err_offset to ex7_ld_par_err_offset + ex7_ld_par_err_d'length-1), + scout => sov(ex7_ld_par_err_offset to ex7_ld_par_err_offset + ex7_ld_par_err_d'length-1), + din => ex7_ld_par_err_d, + dout => ex7_ld_par_err_q); + +my_spare0_lcb : entity tri.tri_lcbnd(tri_lcbnd) +generic map (expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + d1clk => my_spare0_d1clk, + d2clk => my_spare0_d2clk, + lclk => my_spare0_lclk); +my_spare_latches_reg: entity tri.tri_inv_nlats(tri_inv_nlats) +generic map (width => 14, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + lclk => my_spare0_lclk, + d1clk => my_spare0_d1clk, + d2clk => my_spare0_d2clk, + scanin => siv(my_spare_latches_offset to my_spare_latches_offset + my_spare_latches_d'length-1), + scanout => sov(my_spare_latches_offset to my_spare_latches_offset + my_spare_latches_d'length-1), + d => my_spare_latches_d, + qb => my_spare_latches_q); + +dat_dbg_ld_dat_reg: tri_regk + generic map (width => 64, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => trace_bus_enable, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => dat_dbg_ld_dat_d, + dout => dat_dbg_ld_dat_q); + +siv(0 to scan_right) <= sov(1 to scan_right) & scan_in; +rot_scan_in(0 to 7) <= rot_scan_out(1 to 7) & sov(0); +scan_out <= rot_scan_out(0); + +end xuq_lsu_data_ld; diff --git a/rel/src/vhdl/work/xuq_lsu_data_rot32_lu.vhdl b/rel/src/vhdl/work/xuq_lsu_data_rot32_lu.vhdl new file mode 100644 index 0000000..d9889a5 --- /dev/null +++ b/rel/src/vhdl/work/xuq_lsu_data_rot32_lu.vhdl @@ -0,0 +1,330 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XU LSU Store Data Rotator +-- + +library ibm, ieee, work, tri, support; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use tri.tri_latches_pkg.all; +use support.power_logic_pkg.all; + +-- ########################################################################################## +-- VHDL Contents +-- 1) 1 32Byte input +-- 2) 32 Byte Unaligned Rotate to the Left Rotator +-- ########################################################################################## + +entity xuq_lsu_data_rot32_lu is +generic(l_endian_m : integer := 1); -- 1 = little endian mode enabled, 0 = little endian mode disabled +port( + + vdd :inout power_logic; + gnd :inout power_logic; + + -- Rotator Controls and Data + rot_sel1 :in std_ulogic_vector(0 to 31); + rot_sel2 :in std_ulogic_vector(0 to 31); + rot_sel3 :in std_ulogic_vector(0 to 31); + rot_sel2_le :in std_ulogic_vector(0 to 31); + rot_sel3_le :in std_ulogic_vector(0 to 31); + rot_data :in std_ulogic_vector(0 to 127); + + -- Rotated Data + data256_rot_le :out std_ulogic_vector(0 to 127); + data256_rot :out std_ulogic_vector(0 to 127) +); +-- synopsys translate_off +-- synopsys translate_on +end xuq_lsu_data_rot32_lu; +architecture xuq_lsu_data_rot32_lu of xuq_lsu_data_rot32_lu is + +---------------------------- +-- signals +---------------------------- + +signal rot3210 :std_ulogic_vector(0 to 127); +signal rotC840 :std_ulogic_vector(0 to 127); +signal rot10 :std_ulogic_vector(0 to 127); +signal le_rot_data :std_ulogic_vector(0 to 127); +signal le_rotC840 :std_ulogic_vector(0 to 127); +signal le_rot3210 :std_ulogic_vector(0 to 127); + +begin + +-- ############################################################################################# +-- 32 Byte Rotator +-- B0 => data(0:7) B8 => data(64:71) B16 => data(128:135) B24 => data(192:199) +-- B1 => data(8:15) B9 => data(72:79) B17 => data(136:143) B25 => data(200:207) +-- B2 => data(16:23) B10 => data(80:87) B18 => data(144:151) B26 => data(208:215) +-- B3 => data(24:31) B11 => data(88:95) B19 => data(152:159) B27 => data(216:223) +-- B4 => data(32:39) B12 => data(96:103) B20 => data(160:167) B28 => data(224:231) +-- B5 => data(40:47) B13 => data(104:111) B21 => data(168:175) B29 => data(232:239) +-- B6 => data(48:55) B14 => data(112:119) B22 => data(176:183) B30 => data(240:247) +-- B7 => data(56:63) B15 => data(120:127) B23 => data(184:191) B31 => data(248:255) +-- ############################################################################################# + +---- 0,1,2,3 byte rotation +--rot_data1_0 <= rot_data(0 to 255); +--rot_data1_1 <= rot_data(8 to 255) & rot_data(0 to 7); +--rot_data1_2 <= rot_data(16 to 255) & rot_data(0 to 15); +--rot_data1_3 <= rot_data(24 to 255) & rot_data(0 to 23); +-- +--rot3210(0 to 63) <= gate(rot_data1_0(0 to 63), rot_sel1(0)) or gate(rot_data1_1(0 to 63), rot_sel1(1)) or +-- gate(rot_data1_2(0 to 63), rot_sel1(2)) or gate(rot_data1_3(0 to 63), rot_sel1(3)); +-- +--rot3210(64 to 127) <= gate(rot_data1_0(64 to 127), rot_sel1(4)) or gate(rot_data1_1(64 to 127), rot_sel1(5)) or +-- gate(rot_data1_2(64 to 127), rot_sel1(6)) or gate(rot_data1_3(64 to 127), rot_sel1(7)); +-- +--rot3210(128 to 191) <= gate(rot_data1_0(128 to 191), rot_sel1(8)) or gate(rot_data1_1(128 to 191), rot_sel1(9)) or +-- gate(rot_data1_2(128 to 191), rot_sel1(10)) or gate(rot_data1_3(128 to 191), rot_sel1(11)); +-- +--rot3210(192 to 255) <= gate(rot_data1_0(192 to 255), rot_sel1(12)) or gate(rot_data1_1(192 to 255), rot_sel1(13)) or +-- gate(rot_data1_2(192 to 255), rot_sel1(14)) or gate(rot_data1_3(192 to 255), rot_sel1(15)); +-- +---- 0-3,4,8,12 byte rotation +--rot_data2_0 <= rot3210(0 to 255); +--rot_data2_1 <= rot3210(32 to 255) & rot3210(0 to 31); +--rot_data2_2 <= rot3210(64 to 255) & rot3210(0 to 63); +--rot_data2_3 <= rot3210(96 to 255) & rot3210(0 to 95); +-- +--rotC840(0 to 63) <= gate(rot_data2_0(0 to 63), rot_sel2(0)) or gate(rot_data2_1(0 to 63), rot_sel2(1)) or +-- gate(rot_data2_2(0 to 63), rot_sel2(2)) or gate(rot_data2_3(0 to 63), rot_sel2(3)); +-- +--rotC840(64 to 127) <= gate(rot_data2_0(64 to 127), rot_sel2(4)) or gate(rot_data2_1(64 to 127), rot_sel2(5)) or +-- gate(rot_data2_2(64 to 127), rot_sel2(6)) or gate(rot_data2_3(64 to 127), rot_sel2(7)); +-- +--rotC840(128 to 191) <= gate(rot_data2_0(128 to 191), rot_sel2(8)) or gate(rot_data2_1(128 to 191), rot_sel2(9)) or +-- gate(rot_data2_2(128 to 191), rot_sel2(10)) or gate(rot_data2_3(128 to 191), rot_sel2(11)); +-- +--rotC840(192 to 255) <= gate(rot_data2_0(192 to 255), rot_sel2(12)) or gate(rot_data2_1(192 to 255), rot_sel2(13)) or +-- gate(rot_data2_2(192 to 255), rot_sel2(14)) or gate(rot_data2_3(192 to 255), rot_sel2(15)); +-- +---- 0-12,16 byte rotation +--rot_data3_0 <= rotC840(0 to 255); +--rot_data3_1 <= rotC840(128 to 255) & rotC840(0 to 127); +-- +--rot10(0 to 63) <= gate(rot_data3_0(0 to 63), rot_sel3(0)) or gate(rot_data3_1(0 to 63), rot_sel3(1)); +-- +--rot10(64 to 127) <= gate(rot_data3_0(64 to 127), rot_sel3(2)) or gate(rot_data3_1(64 to 127), rot_sel3(3)); +-- +--rot10(128 to 191) <= gate(rot_data3_0(128 to 191), rot_sel3(4)) or gate(rot_data3_1(128 to 191), rot_sel3(5)); +-- +--rot10(192 to 255) <= gate(rot_data3_0(192 to 255), rot_sel3(6)) or gate(rot_data3_1(192 to 255), rot_sel3(7)); + +le_mode_on : if l_endian_m = 1 generate begin + + ---- LE,16 byte rotation + lvl1rot: for byte in 0 to 31 generate begin + bit: for b in 0 to 3 generate + signal muxIn :std_ulogic_vector(0 to 3); + signal muxSel :std_ulogic_vector(0 to 3); + begin + muxIn <= rot_data(byte+(b*32)) & rot_data((((16+byte) mod 32))+(b*32)) & + rot_data(((31 - byte))+(b*32)) & rot_data(((31 - ((16+byte) mod 32)))+(b*32)); + muxSel <= rot_sel1(4*(byte/4) to (4*(byte/4))+3); + + mux4sel: entity work.xuq_lsu_mux41(xuq_lsu_mux41) + port map ( vdd => vdd, + gnd => gnd, + d0 => muxIn(0), + d1 => muxIn(1), + d2 => muxIn(2), + d3 => muxIn(3), + s0 => muxSel(0), + s1 => muxSel(1), + s2 => muxSel(2), + s3 => muxSel(3), + y => rot10(byte+(b*32))); + end generate; + end generate lvl1rot; + + -- Little-Endian Byte Swap, Specifically for Execution Pipe Stores + bitSwap : for bit in 0 to 3 generate begin + byteSwap : for byte in 0 to 31 generate begin + le_rot_data(byte+(bit*32)) <= rot_data((31-byte)+(bit*32)); + end generate byteSwap; + end generate bitSwap; + + -- 0/LE,4,8,12 byte rotation + lvl2rot: for byte in 0 to 31 generate begin + bit: for b in 0 to 3 generate + signal muxIn :std_ulogic_vector(0 to 3); + signal muxSel :std_ulogic_vector(0 to 3); + begin + muxIn <= le_rot_data(byte+(b*32)) & le_rot_data(((4+byte) mod 32)+(b*32)) & + le_rot_data(((8+byte) mod 32)+(b*32)) & le_rot_data(((12+byte) mod 32)+(b*32)); + muxSel <= rot_sel2_le(4*(byte/4) to (4*(byte/4))+3); + + mux4sel: entity work.xuq_lsu_mux41(xuq_lsu_mux41) + port map ( vdd => vdd, + gnd => gnd, + d0 => muxIn(0), + d1 => muxIn(1), + d2 => muxIn(2), + d3 => muxIn(3), + s0 => muxSel(0), + s1 => muxSel(1), + s2 => muxSel(2), + s3 => muxSel(3), + y => le_rotC840(byte+(b*32))); + end generate; + end generate lvl2rot; + + ---- 0/4/8/12/LE,1,2,3 byte rotation + lvl3rot: for byte in 0 to 31 generate begin + bit: for b in 0 to 3 generate + signal muxIn :std_ulogic_vector(0 to 3); + signal muxSel :std_ulogic_vector(0 to 3); + begin + muxIn <= le_rotC840(byte+(b*32)) & le_rotC840(((1+byte) mod 32)+(b*32)) & + le_rotC840(((2+byte) mod 32)+(b*32)) & le_rotC840(((3+byte) mod 32)+(b*32)); + muxSel <= rot_sel3_le(4*(byte/4) to (4*(byte/4))+3); + + mux4sel: entity work.xuq_lsu_mux41(xuq_lsu_mux41) + port map ( vdd => vdd, + gnd => gnd, + d0 => muxIn(0), + d1 => muxIn(1), + d2 => muxIn(2), + d3 => muxIn(3), + s0 => muxSel(0), + s1 => muxSel(1), + s2 => muxSel(2), + s3 => muxSel(3), + y => le_rot3210(byte+(b*32))); + end generate; + end generate lvl3rot; + data256_rot_le <= le_rot3210; +end generate le_mode_on; + +le_mode_off : if l_endian_m = 0 generate begin + + ---- 16 byte rotation + lvl1rot: for byte in 0 to 31 generate begin + bit: for b in 0 to 3 generate + signal muxIn :std_ulogic_vector(0 to 3); + signal muxSel :std_ulogic_vector(0 to 3); + begin + muxIn <= rot_data(byte+(b*32)) & rot_data(((16+byte) mod 32)+(b*32)) & + rot_data((31 - byte)+(b*32)) & rot_data((31 - ((16+byte) mod 32))+(b*32)); + muxSel <= rot_sel1(4*(byte/4) to (4*(byte/4))+3); + + rot10(byte+(b*32)) <= (rot_data(byte+(b*32)) and rot_sel1(b*4*(byte/16))) or + (rot_data(((16+byte) mod 32)+(b*32)) and rot_sel1((b*4*(byte/16))+1)); + end generate; + end generate lvl1rot; + + le_rot_data <= (others=>'0'); + le_rotC840 <= (others=>'0'); + le_rot3210 <= (others=>'0'); + data256_rot_le <= (others=>'0'); +end generate le_mode_off; + +-- 0/16/LE,4,8,12 byte rotation +lvl2rot: for byte in 0 to 31 generate begin + bit: for b in 0 to 3 generate + signal muxIn :std_ulogic_vector(0 to 3); + signal muxSel :std_ulogic_vector(0 to 3); + begin + muxIn <= rot10(byte+(b*32)) & rot10(((4+byte) mod 32)+(b*32)) & + rot10(((8+byte) mod 32)+(b*32)) & rot10(((12+byte) mod 32)+(b*32)); + muxSel <= rot_sel2(4*(byte/4) to (4*(byte/4))+3); + + mux4sel: entity work.xuq_lsu_mux41(xuq_lsu_mux41) + port map ( vdd => vdd, + gnd => gnd, + d0 => muxIn(0), + d1 => muxIn(1), + d2 => muxIn(2), + d3 => muxIn(3), + s0 => muxSel(0), + s1 => muxSel(1), + s2 => muxSel(2), + s3 => muxSel(3), + y => rotC840(byte+(b*32))); + end generate; +end generate lvl2rot; + +---- 0/4/8/12/16/LE,1,2,3 byte rotation +lvl3rot: for byte in 0 to 31 generate begin + bit: for b in 0 to 3 generate + signal muxIn :std_ulogic_vector(0 to 3); + signal muxSel :std_ulogic_vector(0 to 3); + begin + muxIn <= rotC840(byte+(b*32)) & rotC840(((1+byte) mod 32)+(b*32)) & + rotC840(((2+byte) mod 32)+(b*32)) & rotC840(((3+byte) mod 32)+(b*32)); + muxSel <= rot_sel3(4*(byte/4) to (4*(byte/4))+3); + + mux4sel: entity work.xuq_lsu_mux41(xuq_lsu_mux41) + port map ( vdd => vdd, + gnd => gnd, + d0 => muxIn(0), + d1 => muxIn(1), + d2 => muxIn(2), + d3 => muxIn(3), + s0 => muxSel(0), + s1 => muxSel(1), + s2 => muxSel(2), + s3 => muxSel(3), + y => rot3210(byte+(b*32))); + end generate; +end generate lvl3rot; + +---- 0,1,2,3 byte rotation +--with rot_sel(3 to 4) select +-- rot3210 <= rot_data(24 to 255) & rot_data(0 to 23) when "11", -- sel = 0001 +-- rot_data(16 to 255) & rot_data(0 to 15) when "10", -- sel = 0010 +-- rot_data(8 to 255) & rot_data(0 to 7) when "01", -- sel = 0100 +-- rot_data(0 to 255) when others; -- sel = 1000 +-- +---- 0-3,4,8,12 byte rotation +--with rot_sel(1 to 2) select +-- rotC840 <= rot3210(96 to 255) & rot3210(0 to 95) when "11", +-- rot3210(64 to 255) & rot3210(0 to 63) when "10", +-- rot3210(32 to 255) & rot3210(0 to 31) when "01", +-- rot3210(0 to 255) when others; +-- +---- 0-12,16 byte rotation +--with rot_sel(0) select +-- rot10 <= rotC840(128 to 255) & rotC840(0 to 127) when '1', +-- rotC840(0 to 255) when others; + +-- ############################################################################################# +-- Outputs +-- ############################################################################################# + + +data256_rot <= rot3210; +-- ############################################################################################# + +end xuq_lsu_data_rot32_lu; diff --git a/rel/src/vhdl/work/xuq_lsu_data_rot32_ru.vhdl b/rel/src/vhdl/work/xuq_lsu_data_rot32_ru.vhdl new file mode 100644 index 0000000..f3af514 --- /dev/null +++ b/rel/src/vhdl/work/xuq_lsu_data_rot32_ru.vhdl @@ -0,0 +1,555 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XU LSU Load Data Rotator +-- + +LIBRARY ieee; USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY ibm; + USE ibm.std_ulogic_support.all; + USE ibm.std_ulogic_unsigned.all; + USE ibm.std_ulogic_function_support.all; +LIBRARY support; + USE support.power_logic_pkg.all; +LIBRARY tri; USE tri.tri_latches_pkg.all; + +-- ########################################################################################## +-- VHDL Contents +-- 1) 1 32Byte input +-- 2) 32 Byte Unaligned Rotate to the Right Rotator +-- ########################################################################################## + +entity xuq_lsu_data_rot32_ru is + generic (expand_type : integer := 2 ); + port ( + + opsize :in std_ulogic_vector(0 to 5); -- (0)256 (1)128 (2)64 (3)32 (4)16 (5)8 + le :in std_ulogic; + rotate_sel :in std_ulogic_vector(0 to 4); + + data :in std_ulogic_vector(0 to 31); -- data to rotate + data_latched :out std_ulogic_vector(0 to 31); -- latched data, not rotated + data_rot :out std_ulogic_vector(0 to 31); -- rotated data out + + nclk :in clk_logic; + vdd :inout power_logic; + gnd :inout power_logic; + delay_lclkr_dc :in std_ulogic; + mpw1_dc_b :in std_ulogic; + mpw2_dc_b :in std_ulogic; + func_sl_force :in std_ulogic; + func_sl_thold_0_b :in std_ulogic; + sg_0 :in std_ulogic; + act :in std_ulogic; + scan_in :in std_ulogic; + scan_out :out std_ulogic + ); + + +end xuq_lsu_data_rot32_ru; + +architecture xuq_lsu_data_rot32_ru of xuq_lsu_data_rot32_ru is + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal my_d1clk, my_d2clk :std_ulogic ; + signal my_lclk :clk_logic ; + + signal di_lat_si, di_lat_so, di_q_b, di_q, di_din :std_ulogic_vector(0 to 31); + signal shx16_gp0_lat_si, shx16_gp0_lat_so, shx16_gp0_q_b, shx16_gp0_q, shx16_gp0_din :std_ulogic_vector(0 to 3); + signal shx16_gp1_lat_si, shx16_gp1_lat_so, shx16_gp1_q_b, shx16_gp1_q, shx16_gp1_din :std_ulogic_vector(0 to 3); + signal shx04_gp0_lat_si, shx04_gp0_lat_so, shx04_gp0_q_b, shx04_gp0_q, shx04_gp0_din :std_ulogic_vector(0 to 3); + signal shx04_gp1_lat_si, shx04_gp1_lat_so, shx04_gp1_q_b, shx04_gp1_q, shx04_gp1_din :std_ulogic_vector(0 to 3); + signal shx01_gp0_lat_si, shx01_gp0_lat_so, shx01_gp0_q_b, shx01_gp0_q, shx01_gp0_din :std_ulogic_vector(0 to 3); + signal shx01_gp1_lat_si, shx01_gp1_lat_so, shx01_gp1_q_b, shx01_gp1_q, shx01_gp1_din :std_ulogic_vector(0 to 3); + signal mask_lat_si, mask_lat_so, mask_q_b, mask_q, mask_din :std_ulogic_vector(0 to 5); + + signal mx1_0_b, mx1_1_b, mx1 :std_ulogic_vector(0 to 31); + signal mx2_0_b, mx2_1_b, mx2 :std_ulogic_vector(0 to 31); + signal mx3_0_b, mx3_1_b, mx3 :std_ulogic_vector(0 to 31); + signal do_b :std_ulogic_vector(0 to 31) ; + + signal mx1_d0, mx1_d1, mx1_d2, mx1_d3 :std_ulogic_vector(0 to 31) ; + signal mx2_d0, mx2_d1, mx2_d2, mx2_d3 :std_ulogic_vector(0 to 31) ; + signal mx3_d0, mx3_d1, mx3_d2, mx3_d3 :std_ulogic_vector(0 to 31) ; + + signal mx1_s0, mx1_s1, mx1_s2, mx1_s3 :std_ulogic_vector(0 to 31) ; + signal mx2_s0, mx2_s1, mx2_s2, mx2_s3 :std_ulogic_vector(0 to 31) ; + signal mx3_s0, mx3_s1, mx3_s2, mx3_s3 :std_ulogic_vector(0 to 31) ; + + signal mask_en :std_ulogic_vector(0 to 31); + signal shx16_sel , shx04_sel , shx01_sel :std_ulogic_vector(0 to 3); + + +begin + +-- ############################################################################################# +-- Little Endian Rotate Support +-- Optype2 Optype4 Optype8 +-- B31 => rot_data(248:255) +-- B30 => rot_data(240:247) +-- B29 => rot_data(232:239) +-- B28 => rot_data(224:231) +-- B31 => rot_data(248:255) B27 => rot_data(216:223) +-- B30 => rot_data(240:247) B26 => rot_data(208:215) +-- B31 => rot_data(248:255) B29 => rot_data(232:239) B25 => rot_data(200:207) +-- B30 => rot_data(240:247) B28 => rot_data(224:231) B24 => rot_data(192:199) +-- +-- Optype16 +-- B31 => rot_data(248:255) B23 => rot_data(184:191) +-- B30 => rot_data(240:247) B22 => rot_data(176:183) +-- B29 => rot_data(232:239) B21 => rot_data(168:175) +-- B28 => rot_data(224:231) B20 => rot_data(160:167) +-- B27 => rot_data(216:223) B19 => rot_data(152:159) +-- B26 => rot_data(208:215) B18 => rot_data(144:151) +-- B25 => rot_data(200:207) B17 => rot_data(136:143) +-- B24 => rot_data(192:199) B16 => rot_data(128:135) +-- +-- Optype32 +-- B31 => rot_data(248:255) B23 => rot_data(184:191) B15 => rot_data(120:127) B7 => rot_data(56:63) +-- B30 => rot_data(240:247) B22 => rot_data(176:183) B14 => rot_data(112:119) B6 => rot_data(48:55) +-- B29 => rot_data(232:239) B21 => rot_data(168:175) B13 => rot_data(104:111) B5 => rot_data(40:47) +-- B28 => rot_data(224:231) B20 => rot_data(160:167) B12 => rot_data(96:103) B4 => rot_data(32:39) +-- B27 => rot_data(216:223) B19 => rot_data(152:159) B11 => rot_data(88:95) B3 => rot_data(24:31) +-- B26 => rot_data(208:215) B18 => rot_data(144:151) B10 => rot_data(80:87) B2 => rot_data(16:23) +-- B25 => rot_data(200:207) B17 => rot_data(136:143) B9 => rot_data(72:79) B1 => rot_data(8:15) +-- B24 => rot_data(192:199) B16 => rot_data(128:135) B8 => rot_data(64:71) B0 => rot_data(0:7) +-- ############################################################################################# + +---- 0,1,2,3 byte rotation +--with rot_sel(3 to 4) select +-- rot3210 <= rot_data(232 to 255) & rot_data(0 to 231) when "11", +-- rot_data(240 to 255) & rot_data(0 to 239) when "10", +-- rot_data(248 to 255) & rot_data(0 to 247) when "01", +-- rot_data(0 to 255) when others; +-- +---- 0-3,4,8,12 byte rotation +--with rot_sel(1 to 2) select +-- rotC840 <= rot3210(160 to 255) & rot3210(0 to 159) when "11", +-- rot3210(192 to 255) & rot3210(0 to 191) when "10", +-- rot3210(224 to 255) & rot3210(0 to 223) when "01", +-- rot3210(0 to 255) when others; +-- +----0-12, 16 byte rotation +--with rot_sel(0) select +-- rot10 <= rotC840(128 to 255) & rotC840(0 to 127) when '1', +-- rotC840(0 to 255) when others; + + -- ###################################################################### + -- ## BEFORE ROTATE CYCLE + -- ###################################################################### + + -- Rotate Control + -- ---------------------------------- + shx16_sel(0) <= not le and not rotate_sel(0); + shx16_sel(1) <= not le and rotate_sel(0); + shx16_sel(2) <= le and not rotate_sel(0); + shx16_sel(3) <= le and rotate_sel(0); + + shx04_sel(0) <= not rotate_sel(1) and not rotate_sel(2); + shx04_sel(1) <= not rotate_sel(1) and rotate_sel(2); + shx04_sel(2) <= rotate_sel(1) and not rotate_sel(2); + shx04_sel(3) <= rotate_sel(1) and rotate_sel(2); + + shx01_sel(0) <= not rotate_sel(3) and not rotate_sel(4); + shx01_sel(1) <= not rotate_sel(3) and rotate_sel(4); + shx01_sel(2) <= rotate_sel(3) and not rotate_sel(4); + shx01_sel(3) <= rotate_sel(3) and rotate_sel(4); + + -- Opsize Mask Generation + -- ---------------------------------- + mask_din(0) <= opsize(0) ;-- for 0:15 + mask_din(1) <= opsize(1) or mask_din(0) ;-- for 16:23 + mask_din(2) <= opsize(2) or mask_din(1) ;-- for 24:27 + mask_din(3) <= opsize(3) or mask_din(2) ;-- for 28:29 + mask_din(4) <= opsize(4) or mask_din(3) ;-- for 30 + mask_din(5) <= opsize(5) or mask_din(4) ;-- for 31 + + -- Latch Inputs + -- ---------------------------------- + di_din(0 to 31) <= data(0 to 31); + shx16_gp0_din(0 to 3) <= shx16_sel(0 to 3); + shx16_gp1_din(0 to 3) <= shx16_sel(0 to 3); + shx04_gp0_din(0 to 3) <= shx04_sel(0 to 3); + shx04_gp1_din(0 to 3) <= shx04_sel(0 to 3); + shx01_gp0_din(0 to 3) <= shx01_sel(0 to 3); + shx01_gp1_din(0 to 3) <= shx01_sel(0 to 3); + + -- ###################################################################### + -- ## ROTATE CYCLE + -- ###################################################################### + + -- ------------------------------------------------------------------- + -- local latch inputs + -- ------------------------------------------------------------------- + + u_di_q: di_q(0 to 31) <= not di_q_b(0 to 31) ; + u_shx16_gp0_q: shx16_gp0_q(0 to 3) <= not shx16_gp0_q_b(0 to 3) ; + u_shx16_gp1_q: shx16_gp1_q(0 to 3) <= not shx16_gp1_q_b(0 to 3) ; + u_shx04_gp0_q: shx04_gp0_q(0 to 3) <= not shx04_gp0_q_b(0 to 3) ; + u_shx04_gp1_q: shx04_gp1_q(0 to 3) <= not shx04_gp1_q_b(0 to 3) ; + u_shx01_gp0_q: shx01_gp0_q(0 to 3) <= not shx01_gp0_q_b(0 to 3) ; + u_shx01_gp1_q: shx01_gp1_q(0 to 3) <= not shx01_gp1_q_b(0 to 3) ; + mask_q(0 to 5) <= not mask_q_b(0 to 5) ; + + -- ---------------------------------------------------------------------------------------- + -- first level of muxing + -- ---------------------------------------------------------------------------------------- + + mx1_s0( 0 to 15) <= ( 0 to 15=> shx16_gp0_q(0) ) ; -- name reassign for select + mx1_s1( 0 to 15) <= ( 0 to 15=> shx16_gp0_q(1) ) ; -- name reassign for select + mx1_s2( 0 to 15) <= ( 0 to 15=> shx16_gp0_q(2) ) ; -- name reassign for select + mx1_s3( 0 to 15) <= ( 0 to 15=> shx16_gp0_q(3) ) ; -- name reassign for select + mx1_s0(16 to 31) <= (16 to 31=> shx16_gp1_q(0) ) ; -- name reassign for select + mx1_s1(16 to 31) <= (16 to 31=> shx16_gp1_q(1) ) ; -- name reassign for select + mx1_s2(16 to 31) <= (16 to 31=> shx16_gp1_q(2) ) ; -- name reassign for select + mx1_s3(16 to 31) <= (16 to 31=> shx16_gp1_q(3) ) ; -- name reassign for select + + mx1_d0(0) <= di_q(0) ; mx1_d1(0) <= di_q(16) ; mx1_d2(0) <= di_q(31) ; mx1_d3(0) <= di_q(15) ; + mx1_d0(1) <= di_q(1) ; mx1_d1(1) <= di_q(17) ; mx1_d2(1) <= di_q(30) ; mx1_d3(1) <= di_q(14) ; + mx1_d0(2) <= di_q(2) ; mx1_d1(2) <= di_q(18) ; mx1_d2(2) <= di_q(29) ; mx1_d3(2) <= di_q(13) ; + mx1_d0(3) <= di_q(3) ; mx1_d1(3) <= di_q(19) ; mx1_d2(3) <= di_q(28) ; mx1_d3(3) <= di_q(12) ; + mx1_d0(4) <= di_q(4) ; mx1_d1(4) <= di_q(20) ; mx1_d2(4) <= di_q(27) ; mx1_d3(4) <= di_q(11) ; + mx1_d0(5) <= di_q(5) ; mx1_d1(5) <= di_q(21) ; mx1_d2(5) <= di_q(26) ; mx1_d3(5) <= di_q(10) ; + mx1_d0(6) <= di_q(6) ; mx1_d1(6) <= di_q(22) ; mx1_d2(6) <= di_q(25) ; mx1_d3(6) <= di_q(9) ; + mx1_d0(7) <= di_q(7) ; mx1_d1(7) <= di_q(23) ; mx1_d2(7) <= di_q(24) ; mx1_d3(7) <= di_q(8) ; + mx1_d0(8) <= di_q(8) ; mx1_d1(8) <= di_q(24) ; mx1_d2(8) <= di_q(23) ; mx1_d3(8) <= di_q(7) ; + mx1_d0(9) <= di_q(9) ; mx1_d1(9) <= di_q(25) ; mx1_d2(9) <= di_q(22) ; mx1_d3(9) <= di_q(6) ; + mx1_d0(10) <= di_q(10) ; mx1_d1(10) <= di_q(26) ; mx1_d2(10) <= di_q(21) ; mx1_d3(10) <= di_q(5) ; + mx1_d0(11) <= di_q(11) ; mx1_d1(11) <= di_q(27) ; mx1_d2(11) <= di_q(20) ; mx1_d3(11) <= di_q(4) ; + mx1_d0(12) <= di_q(12) ; mx1_d1(12) <= di_q(28) ; mx1_d2(12) <= di_q(19) ; mx1_d3(12) <= di_q(3) ; + mx1_d0(13) <= di_q(13) ; mx1_d1(13) <= di_q(29) ; mx1_d2(13) <= di_q(18) ; mx1_d3(13) <= di_q(2) ; + mx1_d0(14) <= di_q(14) ; mx1_d1(14) <= di_q(30) ; mx1_d2(14) <= di_q(17) ; mx1_d3(14) <= di_q(1) ; + mx1_d0(15) <= di_q(15) ; mx1_d1(15) <= di_q(31) ; mx1_d2(15) <= di_q(16) ; mx1_d3(15) <= di_q(0) ; + mx1_d0(16) <= di_q(16) ; mx1_d1(16) <= di_q(0) ; mx1_d2(16) <= di_q(15) ; mx1_d3(16) <= di_q(31) ; + mx1_d0(17) <= di_q(17) ; mx1_d1(17) <= di_q(1) ; mx1_d2(17) <= di_q(14) ; mx1_d3(17) <= di_q(30) ; + mx1_d0(18) <= di_q(18) ; mx1_d1(18) <= di_q(2) ; mx1_d2(18) <= di_q(13) ; mx1_d3(18) <= di_q(29) ; + mx1_d0(19) <= di_q(19) ; mx1_d1(19) <= di_q(3) ; mx1_d2(19) <= di_q(12) ; mx1_d3(19) <= di_q(28) ; + mx1_d0(20) <= di_q(20) ; mx1_d1(20) <= di_q(4) ; mx1_d2(20) <= di_q(11) ; mx1_d3(20) <= di_q(27) ; + mx1_d0(21) <= di_q(21) ; mx1_d1(21) <= di_q(5) ; mx1_d2(21) <= di_q(10) ; mx1_d3(21) <= di_q(26) ; + mx1_d0(22) <= di_q(22) ; mx1_d1(22) <= di_q(6) ; mx1_d2(22) <= di_q(9) ; mx1_d3(22) <= di_q(25) ; + mx1_d0(23) <= di_q(23) ; mx1_d1(23) <= di_q(7) ; mx1_d2(23) <= di_q(8) ; mx1_d3(23) <= di_q(24) ; + mx1_d0(24) <= di_q(24) ; mx1_d1(24) <= di_q(8) ; mx1_d2(24) <= di_q(7) ; mx1_d3(24) <= di_q(23) ; + mx1_d0(25) <= di_q(25) ; mx1_d1(25) <= di_q(9) ; mx1_d2(25) <= di_q(6) ; mx1_d3(25) <= di_q(22) ; + mx1_d0(26) <= di_q(26) ; mx1_d1(26) <= di_q(10) ; mx1_d2(26) <= di_q(5) ; mx1_d3(26) <= di_q(21) ; + mx1_d0(27) <= di_q(27) ; mx1_d1(27) <= di_q(11) ; mx1_d2(27) <= di_q(4) ; mx1_d3(27) <= di_q(20) ; + mx1_d0(28) <= di_q(28) ; mx1_d1(28) <= di_q(12) ; mx1_d2(28) <= di_q(3) ; mx1_d3(28) <= di_q(19) ; + mx1_d0(29) <= di_q(29) ; mx1_d1(29) <= di_q(13) ; mx1_d2(29) <= di_q(2) ; mx1_d3(29) <= di_q(18) ; + mx1_d0(30) <= di_q(30) ; mx1_d1(30) <= di_q(14) ; mx1_d2(30) <= di_q(1) ; mx1_d3(30) <= di_q(17) ; + mx1_d0(31) <= di_q(31) ; mx1_d1(31) <= di_q(15) ; mx1_d2(31) <= di_q(0) ; mx1_d3(31) <= di_q(16) ; + + + u_mx1_0: mx1_0_b(0 to 31) <= not( (mx1_s0(0 to 31) and mx1_d0(0 to 31) ) or + (mx1_s1(0 to 31) and mx1_d1(0 to 31) ) ); + + u_mx1_1: mx1_1_b(0 to 31) <= not( (mx1_s2(0 to 31) and mx1_d2(0 to 31) ) or + (mx1_s3(0 to 31) and mx1_d3(0 to 31) ) ); + + u_mx1: mx1(0 to 31) <= not( mx1_0_b(0 to 31) and mx1_1_b(0 to 31) ); + + -- ---------------------------------------------------------------------------------------- + -- second level of muxing <0,4,8,12 bytes> + -- ---------------------------------------------------------------------------------------- + + mx2_s0( 0 to 15) <= ( 0 to 15=> shx04_gp0_q(0) ) ; -- name reassign for select + mx2_s1( 0 to 15) <= ( 0 to 15=> shx04_gp0_q(1) ) ; -- name reassign for select + mx2_s2( 0 to 15) <= ( 0 to 15=> shx04_gp0_q(2) ) ; -- name reassign for select + mx2_s3( 0 to 15) <= ( 0 to 15=> shx04_gp0_q(3) ) ; -- name reassign for select + mx2_s0(16 to 31) <= (16 to 31=> shx04_gp1_q(0) ) ; -- name reassign for select + mx2_s1(16 to 31) <= (16 to 31=> shx04_gp1_q(1) ) ; -- name reassign for select + mx2_s2(16 to 31) <= (16 to 31=> shx04_gp1_q(2) ) ; -- name reassign for select + mx2_s3(16 to 31) <= (16 to 31=> shx04_gp1_q(3) ) ; -- name reassign for select + + mx2_d0(0) <= mx1(0) ; mx2_d1(0) <= mx1(28) ; mx2_d2(0) <= mx1(24) ; mx2_d3(0) <= mx1(20) ; + mx2_d0(1) <= mx1(1) ; mx2_d1(1) <= mx1(29) ; mx2_d2(1) <= mx1(25) ; mx2_d3(1) <= mx1(21) ; + mx2_d0(2) <= mx1(2) ; mx2_d1(2) <= mx1(30) ; mx2_d2(2) <= mx1(26) ; mx2_d3(2) <= mx1(22) ; + mx2_d0(3) <= mx1(3) ; mx2_d1(3) <= mx1(31) ; mx2_d2(3) <= mx1(27) ; mx2_d3(3) <= mx1(23) ; + mx2_d0(4) <= mx1(4) ; mx2_d1(4) <= mx1(0) ; mx2_d2(4) <= mx1(28) ; mx2_d3(4) <= mx1(24) ; + mx2_d0(5) <= mx1(5) ; mx2_d1(5) <= mx1(1) ; mx2_d2(5) <= mx1(29) ; mx2_d3(5) <= mx1(25) ; + mx2_d0(6) <= mx1(6) ; mx2_d1(6) <= mx1(2) ; mx2_d2(6) <= mx1(30) ; mx2_d3(6) <= mx1(26) ; + mx2_d0(7) <= mx1(7) ; mx2_d1(7) <= mx1(3) ; mx2_d2(7) <= mx1(31) ; mx2_d3(7) <= mx1(27) ; + mx2_d0(8) <= mx1(8) ; mx2_d1(8) <= mx1(4) ; mx2_d2(8) <= mx1(0) ; mx2_d3(8) <= mx1(28) ; + mx2_d0(9) <= mx1(9) ; mx2_d1(9) <= mx1(5) ; mx2_d2(9) <= mx1(1) ; mx2_d3(9) <= mx1(29) ; + mx2_d0(10) <= mx1(10) ; mx2_d1(10) <= mx1(6) ; mx2_d2(10) <= mx1(2) ; mx2_d3(10) <= mx1(30) ; + mx2_d0(11) <= mx1(11) ; mx2_d1(11) <= mx1(7) ; mx2_d2(11) <= mx1(3) ; mx2_d3(11) <= mx1(31) ; + mx2_d0(12) <= mx1(12) ; mx2_d1(12) <= mx1(8) ; mx2_d2(12) <= mx1(4) ; mx2_d3(12) <= mx1(0) ; + mx2_d0(13) <= mx1(13) ; mx2_d1(13) <= mx1(9) ; mx2_d2(13) <= mx1(5) ; mx2_d3(13) <= mx1(1) ; + mx2_d0(14) <= mx1(14) ; mx2_d1(14) <= mx1(10) ; mx2_d2(14) <= mx1(6) ; mx2_d3(14) <= mx1(2) ; + mx2_d0(15) <= mx1(15) ; mx2_d1(15) <= mx1(11) ; mx2_d2(15) <= mx1(7) ; mx2_d3(15) <= mx1(3) ; + mx2_d0(16) <= mx1(16) ; mx2_d1(16) <= mx1(12) ; mx2_d2(16) <= mx1(8) ; mx2_d3(16) <= mx1(4) ; + mx2_d0(17) <= mx1(17) ; mx2_d1(17) <= mx1(13) ; mx2_d2(17) <= mx1(9) ; mx2_d3(17) <= mx1(5) ; + mx2_d0(18) <= mx1(18) ; mx2_d1(18) <= mx1(14) ; mx2_d2(18) <= mx1(10) ; mx2_d3(18) <= mx1(6) ; + mx2_d0(19) <= mx1(19) ; mx2_d1(19) <= mx1(15) ; mx2_d2(19) <= mx1(11) ; mx2_d3(19) <= mx1(7) ; + mx2_d0(20) <= mx1(20) ; mx2_d1(20) <= mx1(16) ; mx2_d2(20) <= mx1(12) ; mx2_d3(20) <= mx1(8) ; + mx2_d0(21) <= mx1(21) ; mx2_d1(21) <= mx1(17) ; mx2_d2(21) <= mx1(13) ; mx2_d3(21) <= mx1(9) ; + mx2_d0(22) <= mx1(22) ; mx2_d1(22) <= mx1(18) ; mx2_d2(22) <= mx1(14) ; mx2_d3(22) <= mx1(10) ; + mx2_d0(23) <= mx1(23) ; mx2_d1(23) <= mx1(19) ; mx2_d2(23) <= mx1(15) ; mx2_d3(23) <= mx1(11) ; + mx2_d0(24) <= mx1(24) ; mx2_d1(24) <= mx1(20) ; mx2_d2(24) <= mx1(16) ; mx2_d3(24) <= mx1(12) ; + mx2_d0(25) <= mx1(25) ; mx2_d1(25) <= mx1(21) ; mx2_d2(25) <= mx1(17) ; mx2_d3(25) <= mx1(13) ; + mx2_d0(26) <= mx1(26) ; mx2_d1(26) <= mx1(22) ; mx2_d2(26) <= mx1(18) ; mx2_d3(26) <= mx1(14) ; + mx2_d0(27) <= mx1(27) ; mx2_d1(27) <= mx1(23) ; mx2_d2(27) <= mx1(19) ; mx2_d3(27) <= mx1(15) ; + mx2_d0(28) <= mx1(28) ; mx2_d1(28) <= mx1(24) ; mx2_d2(28) <= mx1(20) ; mx2_d3(28) <= mx1(16) ; + mx2_d0(29) <= mx1(29) ; mx2_d1(29) <= mx1(25) ; mx2_d2(29) <= mx1(21) ; mx2_d3(29) <= mx1(17) ; + mx2_d0(30) <= mx1(30) ; mx2_d1(30) <= mx1(26) ; mx2_d2(30) <= mx1(22) ; mx2_d3(30) <= mx1(18) ; + mx2_d0(31) <= mx1(31) ; mx2_d1(31) <= mx1(27) ; mx2_d2(31) <= mx1(23) ; mx2_d3(31) <= mx1(19) ; + + + u_mx2_0: mx2_0_b(0 to 31) <= not( (mx2_s0(0 to 31) and mx2_d0(0 to 31) ) or + (mx2_s1(0 to 31) and mx2_d1(0 to 31) ) ); + + u_mx2_1: mx2_1_b(0 to 31) <= not( (mx2_s2(0 to 31) and mx2_d2(0 to 31) ) or + (mx2_s3(0 to 31) and mx2_d3(0 to 31) ) ); + + u_mx2: mx2(0 to 31) <= not( mx2_0_b(0 to 31) and mx2_1_b(0 to 31) ); + + + -- ---------------------------------------------------------------------------------------- + -- third level of muxing <0,1,2,3 bytes> , include mask on selects + -- ---------------------------------------------------------------------------------------- + + mask_en( 0 to 15) <= ( 0 to 15=> mask_q(0) ); -- 256 + mask_en(16 to 23) <= (16 to 23=> mask_q(1) ); -- 256,128 + mask_en(24 to 27) <= (24 to 27=> mask_q(2) ); -- 256,128,64 + mask_en(28 to 29) <= (28 to 29=> mask_q(3) ); -- 256,128,64,32 + mask_en(30) <= ( mask_q(4) ); -- 256,128,64,32,16 + mask_en(31) <= ( mask_q(5) ); -- 256,128,64,32,16,8 + + mx3_s0( 0 to 15) <= ( 0 to 15=> shx01_gp0_q(0) ) and mask_en( 0 to 15); -- name reassign for select + mx3_s1( 0 to 15) <= ( 0 to 15=> shx01_gp0_q(1) ) and mask_en( 0 to 15); -- name reassign for select + mx3_s2( 0 to 15) <= ( 0 to 15=> shx01_gp0_q(2) ) and mask_en( 0 to 15); -- name reassign for select + mx3_s3( 0 to 15) <= ( 0 to 15=> shx01_gp0_q(3) ) and mask_en( 0 to 15); -- name reassign for select + mx3_s0(16 to 31) <= (16 to 31=> shx01_gp1_q(0) ) and mask_en(16 to 31); -- name reassign for select + mx3_s1(16 to 31) <= (16 to 31=> shx01_gp1_q(1) ) and mask_en(16 to 31); -- name reassign for select + mx3_s2(16 to 31) <= (16 to 31=> shx01_gp1_q(2) ) and mask_en(16 to 31); -- name reassign for select + mx3_s3(16 to 31) <= (16 to 31=> shx01_gp1_q(3) ) and mask_en(16 to 31); -- name reassign for select + + mx3_d0(0) <= mx2(0) ; mx3_d1(0) <= mx2(31) ; mx3_d2(0) <= mx2(30) ; mx3_d3(0) <= mx2(29) ; + mx3_d0(1) <= mx2(1) ; mx3_d1(1) <= mx2(0) ; mx3_d2(1) <= mx2(31) ; mx3_d3(1) <= mx2(30) ; + mx3_d0(2) <= mx2(2) ; mx3_d1(2) <= mx2(1) ; mx3_d2(2) <= mx2(0) ; mx3_d3(2) <= mx2(31) ; + mx3_d0(3) <= mx2(3) ; mx3_d1(3) <= mx2(2) ; mx3_d2(3) <= mx2(1) ; mx3_d3(3) <= mx2(0) ; + mx3_d0(4) <= mx2(4) ; mx3_d1(4) <= mx2(3) ; mx3_d2(4) <= mx2(2) ; mx3_d3(4) <= mx2(1) ; + mx3_d0(5) <= mx2(5) ; mx3_d1(5) <= mx2(4) ; mx3_d2(5) <= mx2(3) ; mx3_d3(5) <= mx2(2) ; + mx3_d0(6) <= mx2(6) ; mx3_d1(6) <= mx2(5) ; mx3_d2(6) <= mx2(4) ; mx3_d3(6) <= mx2(3) ; + mx3_d0(7) <= mx2(7) ; mx3_d1(7) <= mx2(6) ; mx3_d2(7) <= mx2(5) ; mx3_d3(7) <= mx2(4) ; + mx3_d0(8) <= mx2(8) ; mx3_d1(8) <= mx2(7) ; mx3_d2(8) <= mx2(6) ; mx3_d3(8) <= mx2(5) ; + mx3_d0(9) <= mx2(9) ; mx3_d1(9) <= mx2(8) ; mx3_d2(9) <= mx2(7) ; mx3_d3(9) <= mx2(6) ; + mx3_d0(10) <= mx2(10) ; mx3_d1(10) <= mx2(9) ; mx3_d2(10) <= mx2(8) ; mx3_d3(10) <= mx2(7) ; + mx3_d0(11) <= mx2(11) ; mx3_d1(11) <= mx2(10) ; mx3_d2(11) <= mx2(9) ; mx3_d3(11) <= mx2(8) ; + mx3_d0(12) <= mx2(12) ; mx3_d1(12) <= mx2(11) ; mx3_d2(12) <= mx2(10) ; mx3_d3(12) <= mx2(9) ; + mx3_d0(13) <= mx2(13) ; mx3_d1(13) <= mx2(12) ; mx3_d2(13) <= mx2(11) ; mx3_d3(13) <= mx2(10) ; + mx3_d0(14) <= mx2(14) ; mx3_d1(14) <= mx2(13) ; mx3_d2(14) <= mx2(12) ; mx3_d3(14) <= mx2(11) ; + mx3_d0(15) <= mx2(15) ; mx3_d1(15) <= mx2(14) ; mx3_d2(15) <= mx2(13) ; mx3_d3(15) <= mx2(12) ; + mx3_d0(16) <= mx2(16) ; mx3_d1(16) <= mx2(15) ; mx3_d2(16) <= mx2(14) ; mx3_d3(16) <= mx2(13) ; + mx3_d0(17) <= mx2(17) ; mx3_d1(17) <= mx2(16) ; mx3_d2(17) <= mx2(15) ; mx3_d3(17) <= mx2(14) ; + mx3_d0(18) <= mx2(18) ; mx3_d1(18) <= mx2(17) ; mx3_d2(18) <= mx2(16) ; mx3_d3(18) <= mx2(15) ; + mx3_d0(19) <= mx2(19) ; mx3_d1(19) <= mx2(18) ; mx3_d2(19) <= mx2(17) ; mx3_d3(19) <= mx2(16) ; + mx3_d0(20) <= mx2(20) ; mx3_d1(20) <= mx2(19) ; mx3_d2(20) <= mx2(18) ; mx3_d3(20) <= mx2(17) ; + mx3_d0(21) <= mx2(21) ; mx3_d1(21) <= mx2(20) ; mx3_d2(21) <= mx2(19) ; mx3_d3(21) <= mx2(18) ; + mx3_d0(22) <= mx2(22) ; mx3_d1(22) <= mx2(21) ; mx3_d2(22) <= mx2(20) ; mx3_d3(22) <= mx2(19) ; + mx3_d0(23) <= mx2(23) ; mx3_d1(23) <= mx2(22) ; mx3_d2(23) <= mx2(21) ; mx3_d3(23) <= mx2(20) ; + mx3_d0(24) <= mx2(24) ; mx3_d1(24) <= mx2(23) ; mx3_d2(24) <= mx2(22) ; mx3_d3(24) <= mx2(21) ; + mx3_d0(25) <= mx2(25) ; mx3_d1(25) <= mx2(24) ; mx3_d2(25) <= mx2(23) ; mx3_d3(25) <= mx2(22) ; + mx3_d0(26) <= mx2(26) ; mx3_d1(26) <= mx2(25) ; mx3_d2(26) <= mx2(24) ; mx3_d3(26) <= mx2(23) ; + mx3_d0(27) <= mx2(27) ; mx3_d1(27) <= mx2(26) ; mx3_d2(27) <= mx2(25) ; mx3_d3(27) <= mx2(24) ; + mx3_d0(28) <= mx2(28) ; mx3_d1(28) <= mx2(27) ; mx3_d2(28) <= mx2(26) ; mx3_d3(28) <= mx2(25) ; + mx3_d0(29) <= mx2(29) ; mx3_d1(29) <= mx2(28) ; mx3_d2(29) <= mx2(27) ; mx3_d3(29) <= mx2(26) ; + mx3_d0(30) <= mx2(30) ; mx3_d1(30) <= mx2(29) ; mx3_d2(30) <= mx2(28) ; mx3_d3(30) <= mx2(27) ; + mx3_d0(31) <= mx2(31) ; mx3_d1(31) <= mx2(30) ; mx3_d2(31) <= mx2(29) ; mx3_d3(31) <= mx2(28) ; + + u_mx3_0: mx3_0_b(0 to 31) <= not( (mx3_s0(0 to 31) and mx3_d0(0 to 31) ) or + (mx3_s1(0 to 31) and mx3_d1(0 to 31) ) ); + + u_mx3_1: mx3_1_b(0 to 31) <= not( (mx3_s2(0 to 31) and mx3_d2(0 to 31) ) or + (mx3_s3(0 to 31) and mx3_d3(0 to 31) ) ); + + u_mx3: mx3(0 to 31) <= not( mx3_0_b(0 to 31) and mx3_1_b(0 to 31) ); + + + u_oi1: do_b(0 to 31) <= not( mx3(0 to 31) ) ; + u_oi2: data_rot(0 to 31) <= not( do_b(0 to 31) ) ; + + u_oth_i: data_latched <= not di_q_b; + + -- top funny physical placement to minimize wrap wires ... also nice for LE adjust + ----------- + -- 0 31 + -- 1 30 + -- 2 29 + -- 3 28 + -- 4 27 + -- 5 26 + -- 6 25 + -- 7 24 + ----------- + -- 8 23 + -- 9 22 + -- 10 21 + -- 11 20 + -- 12 19 + -- 13 18 + -- 14 17 + -- 15 16 + ----------- + -- bot + +-- ############################################################### +-- ## Latches +-- ############################################################### + + di_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 32, init=>(1 to 32=>'0'), btr => "NLI0001_X4_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + VD => vdd ,--inout + GD => gnd ,--inout + LCLK => my_lclk ,--lclk.clk + D1CLK => my_d1clk , + D2CLK => my_d2clk , + SCANIN => di_lat_si , + SCANOUT => di_lat_so , + D => di_din(0 to 31) , + QB => di_q_b(0 to 31) ); + + shx16_gp0_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 4, init=>(1 to 4=>'0'),btr => "NLI0001_X4_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + VD => vdd ,--inout + GD => gnd ,--inout + LCLK => my_lclk ,--lclk.clk + D1CLK => my_d1clk , + D2CLK => my_d2clk , + SCANIN => shx16_gp0_lat_si , + SCANOUT => shx16_gp0_lat_so , + D => shx16_gp0_din , + QB => shx16_gp0_q_b(0 to 3) ); + + shx16_gp1_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 4, init=>(1 to 4=>'0'),btr => "NLI0001_X4_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + VD => vdd ,--inout + GD => gnd ,--inout + LCLK => my_lclk ,--lclk.clk + D1CLK => my_d1clk , + D2CLK => my_d2clk , + SCANIN => shx16_gp1_lat_si , + SCANOUT => shx16_gp1_lat_so , + D => shx16_gp1_din , + QB => shx16_gp1_q_b(0 to 3) ); + + shx04_gp0_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 4, init=>(1 to 4=>'0'),btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + VD => vdd ,--inout + GD => gnd ,--inout + LCLK => my_lclk ,--lclk.clk + D1CLK => my_d1clk , + D2CLK => my_d2clk , + SCANIN => shx04_gp0_lat_si , + SCANOUT => shx04_gp0_lat_so , + D => shx04_gp0_din , + QB => shx04_gp0_q_b(0 to 3) ); + + shx04_gp1_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 4, init=>(1 to 4=>'0'),btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + VD => vdd ,--inout + GD => gnd ,--inout + LCLK => my_lclk ,--lclk.clk + D1CLK => my_d1clk , + D2CLK => my_d2clk , + SCANIN => shx04_gp1_lat_si , + SCANOUT => shx04_gp1_lat_so , + D => shx04_gp1_din , + QB => shx04_gp1_q_b(0 to 3) ); + + shx01_gp0_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 4, init=>(1 to 4=>'0'),btr => "NLI0001_X1_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + VD => vdd ,--inout + GD => gnd ,--inout + LCLK => my_lclk ,--lclk.clk + D1CLK => my_d1clk , + D2CLK => my_d2clk , + SCANIN => shx01_gp0_lat_si , + SCANOUT => shx01_gp0_lat_so , + D => shx01_gp0_din , + QB => shx01_gp0_q_b(0 to 3) ); + + shx01_gp1_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 4, init=>(1 to 4=>'0'),btr => "NLI0001_X1_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + VD => vdd ,--inout + GD => gnd ,--inout + LCLK => my_lclk ,--lclk.clk + D1CLK => my_d1clk , + D2CLK => my_d2clk , + SCANIN => shx01_gp1_lat_si , + SCANOUT => shx01_gp1_lat_so , + D => shx01_gp1_din , + QB => shx01_gp1_q_b(0 to 3) ); + + mask_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 6, init=>(1 to 6=>'0'),btr => "NLI0001_X1_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + VD => vdd ,--inout + GD => gnd ,--inout + LCLK => my_lclk ,--lclk.clk + D1CLK => my_d1clk , + D2CLK => my_d2clk , + SCANIN => mask_lat_si , + SCANOUT => mask_lat_so , + D => mask_din , + QB => mask_q_b(0 to 5) ); + +-- ############################################################### +-- ## Scan Chain Hookup +-- ############################################################### + + di_lat_si(0) <= scan_in; + di_lat_si(1 to 31) <= di_lat_so(0 to 30); + shx16_gp0_lat_si(0) <= di_lat_so(31); + shx16_gp0_lat_si(1 to 3) <= shx16_gp0_lat_so(0 to 2); + shx16_gp1_lat_si(0) <= shx16_gp0_lat_so(3); + shx16_gp1_lat_si(1 to 3) <= shx16_gp1_lat_so(0 to 2); + shx04_gp0_lat_si(0) <= shx16_gp1_lat_so(3); + shx04_gp0_lat_si(1 to 3) <= shx04_gp0_lat_so(0 to 2); + shx04_gp1_lat_si(0) <= shx04_gp0_lat_so(3); + shx04_gp1_lat_si(1 to 3) <= shx04_gp1_lat_so(0 to 2); + shx01_gp0_lat_si(0) <= shx04_gp1_lat_so(3); + shx01_gp0_lat_si(1 to 3) <= shx01_gp0_lat_so(0 to 2); + shx01_gp1_lat_si(0) <= shx01_gp0_lat_so(3); + shx01_gp1_lat_si(1 to 3) <= shx01_gp1_lat_so(0 to 2); + mask_lat_si(0) <= shx01_gp1_lat_so(3); + mask_lat_si(1 to 5) <= mask_lat_so(0 to 4); + scan_out <= mask_lat_so(5); + + +-- ############################################################### +-- ## LCBs +-- ############################################################### + + my_lcb: tri_lcbnd generic map (expand_type => expand_type) port map ( + delay_lclkr => delay_lclkr_dc ,--in -- tidn , + mpw1_b => mpw1_dc_b ,--in -- tidn , + mpw2_b => mpw2_dc_b ,--in -- tidn , + forcee => func_sl_force ,--in -- tidn , + nclk => nclk ,--in + vd => vdd ,--inout + gd => gnd ,--inout + act => act ,--in + sg => sg_0 ,--in + thold_b => func_sl_thold_0_b ,--in + d1clk => my_d1clk ,--out + d2clk => my_d2clk ,--out + lclk => my_lclk );--out + +end architecture xuq_lsu_data_rot32_ru; diff --git a/rel/src/vhdl/work/xuq_lsu_data_rot32s_ru.vhdl b/rel/src/vhdl/work/xuq_lsu_data_rot32s_ru.vhdl new file mode 100644 index 0000000..fcf913a --- /dev/null +++ b/rel/src/vhdl/work/xuq_lsu_data_rot32s_ru.vhdl @@ -0,0 +1,718 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XU LSU Load Data Rotator +-- + + +LIBRARY ieee; USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY ibm; + USE ibm.std_ulogic_support.all; + USE ibm.std_ulogic_unsigned.all; + USE ibm.std_ulogic_function_support.all; +LIBRARY support; + USE support.power_logic_pkg.all; +LIBRARY tri; USE tri.tri_latches_pkg.all; + +-- ########################################################################################## +-- VHDL Contents +-- 1) 1 32Byte input +-- 2) 32 Byte Unaligned Rotate to the Right Rotator +-- ########################################################################################## + +entity xuq_lsu_data_rot32s_ru is + generic (expand_type : integer := 2 ); + port ( + + opsize :in std_ulogic_vector(0 to 5); -- (0)256 (1)128 (2)64 (3)32 (4)16 (5)8 + le :in std_ulogic; + rotate_sel :in std_ulogic_vector(0 to 4); + algebraic :in std_ulogic; + algebraic_sel :in std_ulogic_vector(0 to 4); + + data :in std_ulogic_vector(0 to 31); -- data to rotate + data_latched :out std_ulogic_vector(0 to 31); -- latched data, not rotated + data_rot :out std_ulogic_vector(0 to 31); -- rotated data out + algebraic_bit :out std_ulogic_vector(0 to 5); + + nclk :in clk_logic; + vdd :inout power_logic; + gnd :inout power_logic; + delay_lclkr_dc :in std_ulogic; + mpw1_dc_b :in std_ulogic; + mpw2_dc_b :in std_ulogic; + func_sl_force :in std_ulogic; + func_sl_thold_0_b :in std_ulogic; + sg_0 :in std_ulogic; + act :in std_ulogic; + scan_in :in std_ulogic; + scan_out :out std_ulogic + ); + + +end xuq_lsu_data_rot32s_ru; + +architecture xuq_lsu_data_rot32s_ru of xuq_lsu_data_rot32s_ru is + constant tiup : std_ulogic := '1'; + constant tidn : std_ulogic := '0'; + + signal my_d1clk, my_d2clk :std_ulogic ; + signal my_lclk :clk_logic ; + + signal di_lat_si, di_lat_so, di_q_b, di_q, di_din :std_ulogic_vector(0 to 31); + signal shx16_gp0_lat_si, shx16_gp0_lat_so, shx16_gp0_q_b, shx16_gp0_q, shx16_gp0_din :std_ulogic_vector(0 to 3); + signal shx16_gp1_lat_si, shx16_gp1_lat_so, shx16_gp1_q_b, shx16_gp1_q, shx16_gp1_din :std_ulogic_vector(0 to 3); + signal shx04_gp0_lat_si, shx04_gp0_lat_so, shx04_gp0_q_b, shx04_gp0_q, shx04_gp0_din :std_ulogic_vector(0 to 3); + signal shx04_gp1_lat_si, shx04_gp1_lat_so, shx04_gp1_q_b, shx04_gp1_q, shx04_gp1_din :std_ulogic_vector(0 to 3); + signal shx01_gp0_lat_si, shx01_gp0_lat_so, shx01_gp0_q_b, shx01_gp0_q, shx01_gp0_din :std_ulogic_vector(0 to 3); + signal shx01_gp1_lat_si, shx01_gp1_lat_so, shx01_gp1_q_b, shx01_gp1_q, shx01_gp1_din :std_ulogic_vector(0 to 3); + signal mask_lat_si, mask_lat_so, mask_q_b, mask_q, mask_din :std_ulogic_vector(0 to 5); + signal shx16_sgn0_lat_si, shx16_sgn0_lat_so, shx16_sgn0_q_b, shx16_sgn0_q, shx16_sgn0_din :std_ulogic_vector(0 to 1); + signal shx04_sgn0_lat_si, shx04_sgn0_lat_so, shx04_sgn0_q_b, shx04_sgn0_q, shx04_sgn0_din :std_ulogic_vector(0 to 3); + signal shx01_sgn0_lat_si, shx01_sgn0_lat_so, shx01_sgn0_q_b, shx01_sgn0_q, shx01_sgn0_din :std_ulogic_vector(0 to 3); + + + signal mx1_0_b, mx1_1_b, mx1 :std_ulogic_vector(0 to 31); + signal sx1_0_b, sx1_1_b, sx1 :std_ulogic_vector(0 to 15); + signal mx2_0_b, mx2_1_b, mx2 :std_ulogic_vector(0 to 31); + signal sx2_0_b, sx2_1_b, sx2 :std_ulogic_vector(0 to 7); + signal mx3_0_b, mx3_1_b, mx3 :std_ulogic_vector(0 to 31); + signal sx3_0_b, sx3_1_b, sx3 :std_ulogic_vector(0 to 5); + signal do_b :std_ulogic_vector(0 to 31) ; + signal sign_copy_b :std_ulogic_vector(0 to 5) ; + + signal mx1_d0, mx1_d1, mx1_d2, mx1_d3 :std_ulogic_vector(0 to 31) ; + signal mx2_d0, mx2_d1, mx2_d2, mx2_d3 :std_ulogic_vector(0 to 31) ; + signal sx2_d0, sx2_d1, sx2_d2, sx2_d3 :std_ulogic_vector(0 to 7) ; + signal mx3_d0, mx3_d1, mx3_d2, mx3_d3 :std_ulogic_vector(0 to 31) ; + signal sx3_d0, sx3_d1, sx3_d2, sx3_d3 :std_ulogic_vector(0 to 5) ; + + signal mx1_s0, mx1_s1, mx1_s2, mx1_s3 :std_ulogic_vector(0 to 31) ; + signal sx1_s0, sx1_s1 :std_ulogic_vector(0 to 15) ; + signal mx2_s0, mx2_s1, mx2_s2, mx2_s3 :std_ulogic_vector(0 to 31) ; + signal sx2_s0, sx2_s1, sx2_s2, sx2_s3 :std_ulogic_vector(0 to 7) ; + signal mx3_s0, mx3_s1, mx3_s2, mx3_s3 :std_ulogic_vector(0 to 31) ; + signal sx3_s0, sx3_s1, sx3_s2, sx3_s3 :std_ulogic_vector(0 to 5) ; + + signal mask_en :std_ulogic_vector(0 to 31); + signal shx16_sel , shx04_sel , shx01_sel :std_ulogic_vector(0 to 3); + signal sgn_amt :std_ulogic_vector(0 to 4); + signal shx04_sgn, shx01_sgn :std_ulogic_vector(0 to 3); + signal shx16_sgn :std_ulogic_vector(0 to 1); + +begin + +-- ############################################################################################# +-- Little Endian Rotate Support +-- Optype2 Optype4 Optype8 +-- B31 => rot_data(248:255) +-- B30 => rot_data(240:247) +-- B29 => rot_data(232:239) +-- B28 => rot_data(224:231) +-- B31 => rot_data(248:255) B27 => rot_data(216:223) +-- B30 => rot_data(240:247) B26 => rot_data(208:215) +-- B31 => rot_data(248:255) B29 => rot_data(232:239) B25 => rot_data(200:207) +-- B30 => rot_data(240:247) B28 => rot_data(224:231) B24 => rot_data(192:199) +-- +-- Optype16 +-- B31 => rot_data(248:255) B23 => rot_data(184:191) +-- B30 => rot_data(240:247) B22 => rot_data(176:183) +-- B29 => rot_data(232:239) B21 => rot_data(168:175) +-- B28 => rot_data(224:231) B20 => rot_data(160:167) +-- B27 => rot_data(216:223) B19 => rot_data(152:159) +-- B26 => rot_data(208:215) B18 => rot_data(144:151) +-- B25 => rot_data(200:207) B17 => rot_data(136:143) +-- B24 => rot_data(192:199) B16 => rot_data(128:135) +-- +-- Optype32 +-- B31 => rot_data(248:255) B23 => rot_data(184:191) B15 => rot_data(120:127) B7 => rot_data(56:63) +-- B30 => rot_data(240:247) B22 => rot_data(176:183) B14 => rot_data(112:119) B6 => rot_data(48:55) +-- B29 => rot_data(232:239) B21 => rot_data(168:175) B13 => rot_data(104:111) B5 => rot_data(40:47) +-- B28 => rot_data(224:231) B20 => rot_data(160:167) B12 => rot_data(96:103) B4 => rot_data(32:39) +-- B27 => rot_data(216:223) B19 => rot_data(152:159) B11 => rot_data(88:95) B3 => rot_data(24:31) +-- B26 => rot_data(208:215) B18 => rot_data(144:151) B10 => rot_data(80:87) B2 => rot_data(16:23) +-- B25 => rot_data(200:207) B17 => rot_data(136:143) B9 => rot_data(72:79) B1 => rot_data(8:15) +-- B24 => rot_data(192:199) B16 => rot_data(128:135) B8 => rot_data(64:71) B0 => rot_data(0:7) +-- ############################################################################################# + +---- 0,1,2,3 byte rotation +--with rot_sel(3 to 4) select +-- rot3210 <= rot_data(232 to 255) & rot_data(0 to 231) when "11", +-- rot_data(240 to 255) & rot_data(0 to 239) when "10", +-- rot_data(248 to 255) & rot_data(0 to 247) when "01", +-- rot_data(0 to 255) when others; +-- +---- 0-3,4,8,12 byte rotation +--with rot_sel(1 to 2) select +-- rotC840 <= rot3210(160 to 255) & rot3210(0 to 159) when "11", +-- rot3210(192 to 255) & rot3210(0 to 191) when "10", +-- rot3210(224 to 255) & rot3210(0 to 223) when "01", +-- rot3210(0 to 255) when others; +-- +----0-12, 16 byte rotation +--with rot_sel(0) select +-- rot10 <= rotC840(128 to 255) & rotC840(0 to 127) when '1', +-- rotC840(0 to 255) when others; + + -- ###################################################################### + -- ## BEFORE ROTATE CYCLE + -- ###################################################################### + + -- Rotate Control + -- ---------------------------------- + shx16_sel(0) <= not le and not rotate_sel(0); + shx16_sel(1) <= not le and rotate_sel(0); + shx16_sel(2) <= le and not rotate_sel(0); + shx16_sel(3) <= le and rotate_sel(0); + + shx04_sel(0) <= not rotate_sel(1) and not rotate_sel(2); + shx04_sel(1) <= not rotate_sel(1) and rotate_sel(2); + shx04_sel(2) <= rotate_sel(1) and not rotate_sel(2); + shx04_sel(3) <= rotate_sel(1) and rotate_sel(2); + + shx01_sel(0) <= not rotate_sel(3) and not rotate_sel(4); + shx01_sel(1) <= not rotate_sel(3) and rotate_sel(4); + shx01_sel(2) <= rotate_sel(3) and not rotate_sel(4); + shx01_sel(3) <= rotate_sel(3) and rotate_sel(4); + + + -- Algebraic Sign Extension Control + -- ---------------------------------- + -- come up with amount to pick the sign extend bit hw(0->30), wd(0->28) 1_1110,1_1100 + + -- add 28/30 to ampunt for wd/hw -- +-- sgn_amt(0) <= not rotate_sel(0) xor le xor ( rotate_sel(1) or rotate_sel(2) or ( rotate_sel(3) and opsize(4)) ); +-- sgn_amt(1) <= not rotate_sel(1) xor le xor ( rotate_sel(2) or ( rotate_sel(3) and opsize(4)) ); +-- sgn_amt(2) <= not rotate_sel(2) xor le xor ( ( rotate_sel(3) and opsize(4)) ); +-- sgn_amt(3) <= rotate_sel(3) xor le xor opsize(4) ; +-- sgn_amt(4) <= rotate_sel(4) xor le ; + + sgn_amt(0) <= algebraic_sel(0); + sgn_amt(1) <= algebraic_sel(1); + sgn_amt(2) <= algebraic_sel(2); + sgn_amt(3) <= algebraic_sel(3); + sgn_amt(4) <= algebraic_sel(4); + + shx16_sgn(0) <= not sgn_amt(0); + shx16_sgn(1) <= sgn_amt(0); + + shx04_sgn(0) <= not sgn_amt(1) and not sgn_amt(2); + shx04_sgn(1) <= not sgn_amt(1) and sgn_amt(2); + shx04_sgn(2) <= sgn_amt(1) and not sgn_amt(2); + shx04_sgn(3) <= sgn_amt(1) and sgn_amt(2); + + shx01_sgn(0) <= not sgn_amt(3) and not sgn_amt(4) and algebraic ; + shx01_sgn(1) <= not sgn_amt(3) and sgn_amt(4) and algebraic ; + shx01_sgn(2) <= sgn_amt(3) and not sgn_amt(4) and algebraic ; + shx01_sgn(3) <= sgn_amt(3) and sgn_amt(4) and algebraic ; + + -- Opsize Mask Generation + -- ---------------------------------- + mask_din(0) <= opsize(0) ;-- for 0:15 + mask_din(1) <= opsize(1) or mask_din(0) ;-- for 16:23 + mask_din(2) <= opsize(2) or mask_din(1) ;-- for 24:27 + mask_din(3) <= opsize(3) or mask_din(2) ;-- for 28:29 + mask_din(4) <= opsize(4) or mask_din(3) ;-- for 30 + mask_din(5) <= opsize(5) or mask_din(4) ;-- for 31 + + -- Latch Inputs + -- ---------------------------------- + di_din(0 to 31) <= data(0 to 31); + shx16_gp0_din(0 to 3) <= shx16_sel(0 to 3); + shx16_gp1_din(0 to 3) <= shx16_sel(0 to 3); + shx04_gp0_din(0 to 3) <= shx04_sel(0 to 3); + shx04_gp1_din(0 to 3) <= shx04_sel(0 to 3); + shx01_gp0_din(0 to 3) <= shx01_sel(0 to 3); + shx01_gp1_din(0 to 3) <= shx01_sel(0 to 3); + shx16_sgn0_din(0 to 1) <= shx16_sgn(0 to 1); + shx04_sgn0_din(0 to 3) <= shx04_sgn(0 to 3); + shx01_sgn0_din(0 to 3) <= shx01_sgn(0 to 3); + + -- ###################################################################### + -- ## ROTATE CYCLE + -- ###################################################################### + + -- ------------------------------------------------------------------- + -- local latch inputs + -- ------------------------------------------------------------------- + + u_di_q: di_q(0 to 31) <= not di_q_b(0 to 31) ; + u_shx16_gp0_q: shx16_gp0_q(0 to 3) <= not shx16_gp0_q_b(0 to 3) ; + u_shx16_gp1_q: shx16_gp1_q(0 to 3) <= not shx16_gp1_q_b(0 to 3) ; + u_shx04_gp0_q: shx04_gp0_q(0 to 3) <= not shx04_gp0_q_b(0 to 3) ; + u_shx04_gp1_q: shx04_gp1_q(0 to 3) <= not shx04_gp1_q_b(0 to 3) ; + u_shx01_gp0_q: shx01_gp0_q(0 to 3) <= not shx01_gp0_q_b(0 to 3) ; + u_shx01_gp1_q: shx01_gp1_q(0 to 3) <= not shx01_gp1_q_b(0 to 3) ; + u_shx16_sgn0_q: shx16_sgn0_q(0 to 1) <= not shx16_sgn0_q_b(0 to 1) ; + u_shx04_sgn0_q: shx04_sgn0_q(0 to 3) <= not shx04_sgn0_q_b(0 to 3) ; + u_shx01_sgn0_q: shx01_sgn0_q(0 to 3) <= not shx01_sgn0_q_b(0 to 3) ; + mask_q(0 to 5) <= not mask_q_b(0 to 5) ; + + -- ---------------------------------------------------------------------------------------- + -- first level of muxing + -- ---------------------------------------------------------------------------------------- + + mx1_s0( 0 to 15) <= ( 0 to 15=> shx16_gp0_q(0) ) ; -- name reassign for select + mx1_s1( 0 to 15) <= ( 0 to 15=> shx16_gp0_q(1) ) ; -- name reassign for select + mx1_s2( 0 to 15) <= ( 0 to 15=> shx16_gp0_q(2) ) ; -- name reassign for select + mx1_s3( 0 to 15) <= ( 0 to 15=> shx16_gp0_q(3) ) ; -- name reassign for select + mx1_s0(16 to 31) <= (16 to 31=> shx16_gp1_q(0) ) ; -- name reassign for select + mx1_s1(16 to 31) <= (16 to 31=> shx16_gp1_q(1) ) ; -- name reassign for select + mx1_s2(16 to 31) <= (16 to 31=> shx16_gp1_q(2) ) ; -- name reassign for select + mx1_s3(16 to 31) <= (16 to 31=> shx16_gp1_q(3) ) ; -- name reassign for select + + sx1_s0( 0 to 15) <= ( 0 to 15=> shx16_sgn0_q(0) ) ; -- name reassign for select + sx1_s1( 0 to 15) <= ( 0 to 15=> shx16_sgn0_q(1) ) ; -- name reassign for select + + mx1_d0(0) <= di_q(0) ; mx1_d1(0) <= di_q(16) ; mx1_d2(0) <= di_q(31) ; mx1_d3(0) <= di_q(15) ; + mx1_d0(1) <= di_q(1) ; mx1_d1(1) <= di_q(17) ; mx1_d2(1) <= di_q(30) ; mx1_d3(1) <= di_q(14) ; + mx1_d0(2) <= di_q(2) ; mx1_d1(2) <= di_q(18) ; mx1_d2(2) <= di_q(29) ; mx1_d3(2) <= di_q(13) ; + mx1_d0(3) <= di_q(3) ; mx1_d1(3) <= di_q(19) ; mx1_d2(3) <= di_q(28) ; mx1_d3(3) <= di_q(12) ; + mx1_d0(4) <= di_q(4) ; mx1_d1(4) <= di_q(20) ; mx1_d2(4) <= di_q(27) ; mx1_d3(4) <= di_q(11) ; + mx1_d0(5) <= di_q(5) ; mx1_d1(5) <= di_q(21) ; mx1_d2(5) <= di_q(26) ; mx1_d3(5) <= di_q(10) ; + mx1_d0(6) <= di_q(6) ; mx1_d1(6) <= di_q(22) ; mx1_d2(6) <= di_q(25) ; mx1_d3(6) <= di_q(9) ; + mx1_d0(7) <= di_q(7) ; mx1_d1(7) <= di_q(23) ; mx1_d2(7) <= di_q(24) ; mx1_d3(7) <= di_q(8) ; + mx1_d0(8) <= di_q(8) ; mx1_d1(8) <= di_q(24) ; mx1_d2(8) <= di_q(23) ; mx1_d3(8) <= di_q(7) ; + mx1_d0(9) <= di_q(9) ; mx1_d1(9) <= di_q(25) ; mx1_d2(9) <= di_q(22) ; mx1_d3(9) <= di_q(6) ; + mx1_d0(10) <= di_q(10) ; mx1_d1(10) <= di_q(26) ; mx1_d2(10) <= di_q(21) ; mx1_d3(10) <= di_q(5) ; + mx1_d0(11) <= di_q(11) ; mx1_d1(11) <= di_q(27) ; mx1_d2(11) <= di_q(20) ; mx1_d3(11) <= di_q(4) ; + mx1_d0(12) <= di_q(12) ; mx1_d1(12) <= di_q(28) ; mx1_d2(12) <= di_q(19) ; mx1_d3(12) <= di_q(3) ; + mx1_d0(13) <= di_q(13) ; mx1_d1(13) <= di_q(29) ; mx1_d2(13) <= di_q(18) ; mx1_d3(13) <= di_q(2) ; + mx1_d0(14) <= di_q(14) ; mx1_d1(14) <= di_q(30) ; mx1_d2(14) <= di_q(17) ; mx1_d3(14) <= di_q(1) ; + mx1_d0(15) <= di_q(15) ; mx1_d1(15) <= di_q(31) ; mx1_d2(15) <= di_q(16) ; mx1_d3(15) <= di_q(0) ; + mx1_d0(16) <= di_q(16) ; mx1_d1(16) <= di_q(0) ; mx1_d2(16) <= di_q(15) ; mx1_d3(16) <= di_q(31) ; + mx1_d0(17) <= di_q(17) ; mx1_d1(17) <= di_q(1) ; mx1_d2(17) <= di_q(14) ; mx1_d3(17) <= di_q(30) ; + mx1_d0(18) <= di_q(18) ; mx1_d1(18) <= di_q(2) ; mx1_d2(18) <= di_q(13) ; mx1_d3(18) <= di_q(29) ; + mx1_d0(19) <= di_q(19) ; mx1_d1(19) <= di_q(3) ; mx1_d2(19) <= di_q(12) ; mx1_d3(19) <= di_q(28) ; + mx1_d0(20) <= di_q(20) ; mx1_d1(20) <= di_q(4) ; mx1_d2(20) <= di_q(11) ; mx1_d3(20) <= di_q(27) ; + mx1_d0(21) <= di_q(21) ; mx1_d1(21) <= di_q(5) ; mx1_d2(21) <= di_q(10) ; mx1_d3(21) <= di_q(26) ; + mx1_d0(22) <= di_q(22) ; mx1_d1(22) <= di_q(6) ; mx1_d2(22) <= di_q(9) ; mx1_d3(22) <= di_q(25) ; + mx1_d0(23) <= di_q(23) ; mx1_d1(23) <= di_q(7) ; mx1_d2(23) <= di_q(8) ; mx1_d3(23) <= di_q(24) ; + mx1_d0(24) <= di_q(24) ; mx1_d1(24) <= di_q(8) ; mx1_d2(24) <= di_q(7) ; mx1_d3(24) <= di_q(23) ; + mx1_d0(25) <= di_q(25) ; mx1_d1(25) <= di_q(9) ; mx1_d2(25) <= di_q(6) ; mx1_d3(25) <= di_q(22) ; + mx1_d0(26) <= di_q(26) ; mx1_d1(26) <= di_q(10) ; mx1_d2(26) <= di_q(5) ; mx1_d3(26) <= di_q(21) ; + mx1_d0(27) <= di_q(27) ; mx1_d1(27) <= di_q(11) ; mx1_d2(27) <= di_q(4) ; mx1_d3(27) <= di_q(20) ; + mx1_d0(28) <= di_q(28) ; mx1_d1(28) <= di_q(12) ; mx1_d2(28) <= di_q(3) ; mx1_d3(28) <= di_q(19) ; + mx1_d0(29) <= di_q(29) ; mx1_d1(29) <= di_q(13) ; mx1_d2(29) <= di_q(2) ; mx1_d3(29) <= di_q(18) ; + mx1_d0(30) <= di_q(30) ; mx1_d1(30) <= di_q(14) ; mx1_d2(30) <= di_q(1) ; mx1_d3(30) <= di_q(17) ; + mx1_d0(31) <= di_q(31) ; mx1_d1(31) <= di_q(15) ; mx1_d2(31) <= di_q(0) ; mx1_d3(31) <= di_q(16) ; + + + u_mx1_0: mx1_0_b(0 to 31) <= not( (mx1_s0(0 to 31) and mx1_d0(0 to 31) ) or + (mx1_s1(0 to 31) and mx1_d1(0 to 31) ) ); + + u_mx1_1: mx1_1_b(0 to 31) <= not( (mx1_s2(0 to 31) and mx1_d2(0 to 31) ) or + (mx1_s3(0 to 31) and mx1_d3(0 to 31) ) ); + + u_mx1: mx1(0 to 31) <= not( mx1_0_b(0 to 31) and mx1_1_b(0 to 31) ); + + + + + u_sx1_0: sx1_0_b(0 to 15) <= not( sx1_s0(0 to 15) and mx1_d0(0 to 15) ) ; + u_sx1_1: sx1_1_b(0 to 15) <= not( sx1_s1(0 to 15) and mx1_d1(0 to 15) ) ; + u_sx1: sx1(0 to 15) <= not( sx1_0_b(0 to 15) and sx1_1_b(0 to 15) ); + + -- ---------------------------------------------------------------------------------------- + -- second level of muxing <0,4,8,12 bytes> + -- ---------------------------------------------------------------------------------------- + + mx2_s0( 0 to 15) <= ( 0 to 15=> shx04_gp0_q(0) ) ; -- name reassign for select + mx2_s1( 0 to 15) <= ( 0 to 15=> shx04_gp0_q(1) ) ; -- name reassign for select + mx2_s2( 0 to 15) <= ( 0 to 15=> shx04_gp0_q(2) ) ; -- name reassign for select + mx2_s3( 0 to 15) <= ( 0 to 15=> shx04_gp0_q(3) ) ; -- name reassign for select + mx2_s0(16 to 31) <= (16 to 31=> shx04_gp1_q(0) ) ; -- name reassign for select + mx2_s1(16 to 31) <= (16 to 31=> shx04_gp1_q(1) ) ; -- name reassign for select + mx2_s2(16 to 31) <= (16 to 31=> shx04_gp1_q(2) ) ; -- name reassign for select + mx2_s3(16 to 31) <= (16 to 31=> shx04_gp1_q(3) ) ; -- name reassign for select + + + mx2_d0(0) <= mx1(0) ; mx2_d1(0) <= mx1(28) ; mx2_d2(0) <= mx1(24) ; mx2_d3(0) <= mx1(20) ; + mx2_d0(1) <= mx1(1) ; mx2_d1(1) <= mx1(29) ; mx2_d2(1) <= mx1(25) ; mx2_d3(1) <= mx1(21) ; + mx2_d0(2) <= mx1(2) ; mx2_d1(2) <= mx1(30) ; mx2_d2(2) <= mx1(26) ; mx2_d3(2) <= mx1(22) ; + mx2_d0(3) <= mx1(3) ; mx2_d1(3) <= mx1(31) ; mx2_d2(3) <= mx1(27) ; mx2_d3(3) <= mx1(23) ; + mx2_d0(4) <= mx1(4) ; mx2_d1(4) <= mx1(0) ; mx2_d2(4) <= mx1(28) ; mx2_d3(4) <= mx1(24) ; + mx2_d0(5) <= mx1(5) ; mx2_d1(5) <= mx1(1) ; mx2_d2(5) <= mx1(29) ; mx2_d3(5) <= mx1(25) ; + mx2_d0(6) <= mx1(6) ; mx2_d1(6) <= mx1(2) ; mx2_d2(6) <= mx1(30) ; mx2_d3(6) <= mx1(26) ; + mx2_d0(7) <= mx1(7) ; mx2_d1(7) <= mx1(3) ; mx2_d2(7) <= mx1(31) ; mx2_d3(7) <= mx1(27) ; + mx2_d0(8) <= mx1(8) ; mx2_d1(8) <= mx1(4) ; mx2_d2(8) <= mx1(0) ; mx2_d3(8) <= mx1(28) ; + mx2_d0(9) <= mx1(9) ; mx2_d1(9) <= mx1(5) ; mx2_d2(9) <= mx1(1) ; mx2_d3(9) <= mx1(29) ; + mx2_d0(10) <= mx1(10) ; mx2_d1(10) <= mx1(6) ; mx2_d2(10) <= mx1(2) ; mx2_d3(10) <= mx1(30) ; + mx2_d0(11) <= mx1(11) ; mx2_d1(11) <= mx1(7) ; mx2_d2(11) <= mx1(3) ; mx2_d3(11) <= mx1(31) ; + mx2_d0(12) <= mx1(12) ; mx2_d1(12) <= mx1(8) ; mx2_d2(12) <= mx1(4) ; mx2_d3(12) <= mx1(0) ; + mx2_d0(13) <= mx1(13) ; mx2_d1(13) <= mx1(9) ; mx2_d2(13) <= mx1(5) ; mx2_d3(13) <= mx1(1) ; + mx2_d0(14) <= mx1(14) ; mx2_d1(14) <= mx1(10) ; mx2_d2(14) <= mx1(6) ; mx2_d3(14) <= mx1(2) ; + mx2_d0(15) <= mx1(15) ; mx2_d1(15) <= mx1(11) ; mx2_d2(15) <= mx1(7) ; mx2_d3(15) <= mx1(3) ; + mx2_d0(16) <= mx1(16) ; mx2_d1(16) <= mx1(12) ; mx2_d2(16) <= mx1(8) ; mx2_d3(16) <= mx1(4) ; + mx2_d0(17) <= mx1(17) ; mx2_d1(17) <= mx1(13) ; mx2_d2(17) <= mx1(9) ; mx2_d3(17) <= mx1(5) ; + mx2_d0(18) <= mx1(18) ; mx2_d1(18) <= mx1(14) ; mx2_d2(18) <= mx1(10) ; mx2_d3(18) <= mx1(6) ; + mx2_d0(19) <= mx1(19) ; mx2_d1(19) <= mx1(15) ; mx2_d2(19) <= mx1(11) ; mx2_d3(19) <= mx1(7) ; + mx2_d0(20) <= mx1(20) ; mx2_d1(20) <= mx1(16) ; mx2_d2(20) <= mx1(12) ; mx2_d3(20) <= mx1(8) ; + mx2_d0(21) <= mx1(21) ; mx2_d1(21) <= mx1(17) ; mx2_d2(21) <= mx1(13) ; mx2_d3(21) <= mx1(9) ; + mx2_d0(22) <= mx1(22) ; mx2_d1(22) <= mx1(18) ; mx2_d2(22) <= mx1(14) ; mx2_d3(22) <= mx1(10) ; + mx2_d0(23) <= mx1(23) ; mx2_d1(23) <= mx1(19) ; mx2_d2(23) <= mx1(15) ; mx2_d3(23) <= mx1(11) ; + mx2_d0(24) <= mx1(24) ; mx2_d1(24) <= mx1(20) ; mx2_d2(24) <= mx1(16) ; mx2_d3(24) <= mx1(12) ; + mx2_d0(25) <= mx1(25) ; mx2_d1(25) <= mx1(21) ; mx2_d2(25) <= mx1(17) ; mx2_d3(25) <= mx1(13) ; + mx2_d0(26) <= mx1(26) ; mx2_d1(26) <= mx1(22) ; mx2_d2(26) <= mx1(18) ; mx2_d3(26) <= mx1(14) ; + mx2_d0(27) <= mx1(27) ; mx2_d1(27) <= mx1(23) ; mx2_d2(27) <= mx1(19) ; mx2_d3(27) <= mx1(15) ; + mx2_d0(28) <= mx1(28) ; mx2_d1(28) <= mx1(24) ; mx2_d2(28) <= mx1(20) ; mx2_d3(28) <= mx1(16) ; + mx2_d0(29) <= mx1(29) ; mx2_d1(29) <= mx1(25) ; mx2_d2(29) <= mx1(21) ; mx2_d3(29) <= mx1(17) ; + mx2_d0(30) <= mx1(30) ; mx2_d1(30) <= mx1(26) ; mx2_d2(30) <= mx1(22) ; mx2_d3(30) <= mx1(18) ; + mx2_d0(31) <= mx1(31) ; mx2_d1(31) <= mx1(27) ; mx2_d2(31) <= mx1(23) ; mx2_d3(31) <= mx1(19) ; + + + u_mx2_0: mx2_0_b(0 to 31) <= not( (mx2_s0(0 to 31) and mx2_d0(0 to 31) ) or + (mx2_s1(0 to 31) and mx2_d1(0 to 31) ) ); + + u_mx2_1: mx2_1_b(0 to 31) <= not( (mx2_s2(0 to 31) and mx2_d2(0 to 31) ) or + (mx2_s3(0 to 31) and mx2_d3(0 to 31) ) ); + + u_mx2: mx2(0 to 31) <= not( mx2_0_b(0 to 31) and mx2_1_b(0 to 31) ); + + + sx2_s0( 0 to 7) <= ( 0 to 7=> shx04_sgn0_q(0) ) ; -- name reassign for select + sx2_s1( 0 to 7) <= ( 0 to 7=> shx04_sgn0_q(1) ) ; -- name reassign for select + sx2_s2( 0 to 7) <= ( 0 to 7=> shx04_sgn0_q(2) ) ; -- name reassign for select + sx2_s3( 0 to 7) <= ( 0 to 7=> shx04_sgn0_q(3) ) ; -- name reassign for select + + sx2_d0(0) <= sx1(0) ; sx2_d1(0) <= sx1(4) ; sx2_d2(0) <= sx1(8) ; sx2_d3(0) <= sx1(12) ; + sx2_d0(1) <= sx1(1) ; sx2_d1(1) <= sx1(5) ; sx2_d2(1) <= sx1(9) ; sx2_d3(1) <= sx1(13) ; + sx2_d0(2) <= sx1(2) ; sx2_d1(2) <= sx1(6) ; sx2_d2(2) <= sx1(10) ; sx2_d3(2) <= sx1(14) ; + sx2_d0(3) <= sx1(3) ; sx2_d1(3) <= sx1(7) ; sx2_d2(3) <= sx1(11) ; sx2_d3(3) <= sx1(15) ; + sx2_d0(4) <= sx1(0) ; sx2_d1(4) <= sx1(4) ; sx2_d2(4) <= sx1(8) ; sx2_d3(4) <= sx1(12) ; + sx2_d0(5) <= sx1(1) ; sx2_d1(5) <= sx1(5) ; sx2_d2(5) <= sx1(9) ; sx2_d3(5) <= sx1(13) ; + sx2_d0(6) <= sx1(2) ; sx2_d1(6) <= sx1(6) ; sx2_d2(6) <= sx1(10) ; sx2_d3(6) <= sx1(14) ; + sx2_d0(7) <= sx1(3) ; sx2_d1(7) <= sx1(7) ; sx2_d2(7) <= sx1(11) ; sx2_d3(7) <= sx1(15) ; + + + + + u_sx2_0: sx2_0_b(0 to 7) <= not( (sx2_s0(0 to 7) and sx2_d0(0 to 7) ) or + (sx2_s1(0 to 7) and sx2_d1(0 to 7) ) ); + + u_sx2_1: sx2_1_b(0 to 7) <= not( (sx2_s2(0 to 7) and sx2_d2(0 to 7) ) or + (sx2_s3(0 to 7) and sx2_d3(0 to 7) ) ); + + u_sx2: sx2(0 to 7) <= not( sx2_0_b(0 to 7) and sx2_1_b(0 to 7) ); + + -- ---------------------------------------------------------------------------------------- + -- third level of muxing <0,1,2,3 bytes> , include mask on selects + -- ---------------------------------------------------------------------------------------- + + mask_en( 0 to 15) <= ( 0 to 15=> mask_q(0) ); -- 256 + mask_en(16 to 23) <= (16 to 23=> mask_q(1) ); -- 256,128 + mask_en(24 to 27) <= (24 to 27=> mask_q(2) ); -- 256,128,64 + mask_en(28 to 29) <= (28 to 29=> mask_q(3) ); -- 256,128,64,32 + mask_en(30) <= ( mask_q(4) ); -- 256,128,64,32,16 + mask_en(31) <= ( mask_q(5) ); -- 256,128,64,32,16,8 + + mx3_s0( 0 to 15) <= ( 0 to 15=> shx01_gp0_q(0) ) and mask_en( 0 to 15); -- name reassign for select + mx3_s1( 0 to 15) <= ( 0 to 15=> shx01_gp0_q(1) ) and mask_en( 0 to 15); -- name reassign for select + mx3_s2( 0 to 15) <= ( 0 to 15=> shx01_gp0_q(2) ) and mask_en( 0 to 15); -- name reassign for select + mx3_s3( 0 to 15) <= ( 0 to 15=> shx01_gp0_q(3) ) and mask_en( 0 to 15); -- name reassign for select + mx3_s0(16 to 31) <= (16 to 31=> shx01_gp1_q(0) ) and mask_en(16 to 31); -- name reassign for select + mx3_s1(16 to 31) <= (16 to 31=> shx01_gp1_q(1) ) and mask_en(16 to 31); -- name reassign for select + mx3_s2(16 to 31) <= (16 to 31=> shx01_gp1_q(2) ) and mask_en(16 to 31); -- name reassign for select + mx3_s3(16 to 31) <= (16 to 31=> shx01_gp1_q(3) ) and mask_en(16 to 31); -- name reassign for select + + + mx3_d0(0) <= mx2(0) ; mx3_d1(0) <= mx2(31) ; mx3_d2(0) <= mx2(30) ; mx3_d3(0) <= mx2(29) ; + mx3_d0(1) <= mx2(1) ; mx3_d1(1) <= mx2(0) ; mx3_d2(1) <= mx2(31) ; mx3_d3(1) <= mx2(30) ; + mx3_d0(2) <= mx2(2) ; mx3_d1(2) <= mx2(1) ; mx3_d2(2) <= mx2(0) ; mx3_d3(2) <= mx2(31) ; + mx3_d0(3) <= mx2(3) ; mx3_d1(3) <= mx2(2) ; mx3_d2(3) <= mx2(1) ; mx3_d3(3) <= mx2(0) ; + mx3_d0(4) <= mx2(4) ; mx3_d1(4) <= mx2(3) ; mx3_d2(4) <= mx2(2) ; mx3_d3(4) <= mx2(1) ; + mx3_d0(5) <= mx2(5) ; mx3_d1(5) <= mx2(4) ; mx3_d2(5) <= mx2(3) ; mx3_d3(5) <= mx2(2) ; + mx3_d0(6) <= mx2(6) ; mx3_d1(6) <= mx2(5) ; mx3_d2(6) <= mx2(4) ; mx3_d3(6) <= mx2(3) ; + mx3_d0(7) <= mx2(7) ; mx3_d1(7) <= mx2(6) ; mx3_d2(7) <= mx2(5) ; mx3_d3(7) <= mx2(4) ; + mx3_d0(8) <= mx2(8) ; mx3_d1(8) <= mx2(7) ; mx3_d2(8) <= mx2(6) ; mx3_d3(8) <= mx2(5) ; + mx3_d0(9) <= mx2(9) ; mx3_d1(9) <= mx2(8) ; mx3_d2(9) <= mx2(7) ; mx3_d3(9) <= mx2(6) ; + mx3_d0(10) <= mx2(10) ; mx3_d1(10) <= mx2(9) ; mx3_d2(10) <= mx2(8) ; mx3_d3(10) <= mx2(7) ; + mx3_d0(11) <= mx2(11) ; mx3_d1(11) <= mx2(10) ; mx3_d2(11) <= mx2(9) ; mx3_d3(11) <= mx2(8) ; + mx3_d0(12) <= mx2(12) ; mx3_d1(12) <= mx2(11) ; mx3_d2(12) <= mx2(10) ; mx3_d3(12) <= mx2(9) ; + mx3_d0(13) <= mx2(13) ; mx3_d1(13) <= mx2(12) ; mx3_d2(13) <= mx2(11) ; mx3_d3(13) <= mx2(10) ; + mx3_d0(14) <= mx2(14) ; mx3_d1(14) <= mx2(13) ; mx3_d2(14) <= mx2(12) ; mx3_d3(14) <= mx2(11) ; + mx3_d0(15) <= mx2(15) ; mx3_d1(15) <= mx2(14) ; mx3_d2(15) <= mx2(13) ; mx3_d3(15) <= mx2(12) ; + mx3_d0(16) <= mx2(16) ; mx3_d1(16) <= mx2(15) ; mx3_d2(16) <= mx2(14) ; mx3_d3(16) <= mx2(13) ; + mx3_d0(17) <= mx2(17) ; mx3_d1(17) <= mx2(16) ; mx3_d2(17) <= mx2(15) ; mx3_d3(17) <= mx2(14) ; + mx3_d0(18) <= mx2(18) ; mx3_d1(18) <= mx2(17) ; mx3_d2(18) <= mx2(16) ; mx3_d3(18) <= mx2(15) ; + mx3_d0(19) <= mx2(19) ; mx3_d1(19) <= mx2(18) ; mx3_d2(19) <= mx2(17) ; mx3_d3(19) <= mx2(16) ; + mx3_d0(20) <= mx2(20) ; mx3_d1(20) <= mx2(19) ; mx3_d2(20) <= mx2(18) ; mx3_d3(20) <= mx2(17) ; + mx3_d0(21) <= mx2(21) ; mx3_d1(21) <= mx2(20) ; mx3_d2(21) <= mx2(19) ; mx3_d3(21) <= mx2(18) ; + mx3_d0(22) <= mx2(22) ; mx3_d1(22) <= mx2(21) ; mx3_d2(22) <= mx2(20) ; mx3_d3(22) <= mx2(19) ; + mx3_d0(23) <= mx2(23) ; mx3_d1(23) <= mx2(22) ; mx3_d2(23) <= mx2(21) ; mx3_d3(23) <= mx2(20) ; + mx3_d0(24) <= mx2(24) ; mx3_d1(24) <= mx2(23) ; mx3_d2(24) <= mx2(22) ; mx3_d3(24) <= mx2(21) ; + mx3_d0(25) <= mx2(25) ; mx3_d1(25) <= mx2(24) ; mx3_d2(25) <= mx2(23) ; mx3_d3(25) <= mx2(22) ; + mx3_d0(26) <= mx2(26) ; mx3_d1(26) <= mx2(25) ; mx3_d2(26) <= mx2(24) ; mx3_d3(26) <= mx2(23) ; + mx3_d0(27) <= mx2(27) ; mx3_d1(27) <= mx2(26) ; mx3_d2(27) <= mx2(25) ; mx3_d3(27) <= mx2(24) ; + mx3_d0(28) <= mx2(28) ; mx3_d1(28) <= mx2(27) ; mx3_d2(28) <= mx2(26) ; mx3_d3(28) <= mx2(25) ; + mx3_d0(29) <= mx2(29) ; mx3_d1(29) <= mx2(28) ; mx3_d2(29) <= mx2(27) ; mx3_d3(29) <= mx2(26) ; + mx3_d0(30) <= mx2(30) ; mx3_d1(30) <= mx2(29) ; mx3_d2(30) <= mx2(28) ; mx3_d3(30) <= mx2(27) ; + mx3_d0(31) <= mx2(31) ; mx3_d1(31) <= mx2(30) ; mx3_d2(31) <= mx2(29) ; mx3_d3(31) <= mx2(28) ; + + u_mx3_0: mx3_0_b(0 to 31) <= not( (mx3_s0(0 to 31) and mx3_d0(0 to 31) ) or + (mx3_s1(0 to 31) and mx3_d1(0 to 31) ) ); + + u_mx3_1: mx3_1_b(0 to 31) <= not( (mx3_s2(0 to 31) and mx3_d2(0 to 31) ) or + (mx3_s3(0 to 31) and mx3_d3(0 to 31) ) ); + + u_mx3: mx3(0 to 31) <= not( mx3_0_b(0 to 31) and mx3_1_b(0 to 31) ); + + u_oi1: do_b(0 to 31) <= not( mx3(0 to 31) ) ; + u_oi2: data_rot(0 to 31) <= not( do_b(0 to 31) ) ; + + u_oth_i: data_latched <= not di_q_b; + + sx3_s0( 0 to 3) <= ( 0 to 3=> shx01_sgn0_q(0) ) ; -- name reassign for select + sx3_s1( 0 to 3) <= ( 0 to 3=> shx01_sgn0_q(1) ) ; -- name reassign for select + sx3_s2( 0 to 3) <= ( 0 to 3=> shx01_sgn0_q(2) ) ; -- name reassign for select + sx3_s3( 0 to 3) <= ( 0 to 3=> shx01_sgn0_q(3) ) ; -- name reassign for select + + sx3_s0( 4 to 5) <= ( 4 to 5=> shx01_sgn0_q(0) ) and (4 to 5=> not mask_q(3) ); -- name reassign for select + sx3_s1( 4 to 5) <= ( 4 to 5=> shx01_sgn0_q(1) ) and (4 to 5=> not mask_q(3) ); -- name reassign for select + sx3_s2( 4 to 5) <= ( 4 to 5=> shx01_sgn0_q(2) ) and (4 to 5=> not mask_q(3) ); -- name reassign for select + sx3_s3( 4 to 5) <= ( 4 to 5=> shx01_sgn0_q(3) ) and (4 to 5=> not mask_q(3) ); -- name reassign for select + + -- 6 logically identcal copies (1 per byte needing extension) + sx3_d0(0) <= sx2(0) ; sx3_d1(0) <= sx2(1) ; sx3_d2(0) <= sx2(2) ; sx3_d3(0) <= sx2(3) ; + sx3_d0(1) <= sx2(0) ; sx3_d1(1) <= sx2(1) ; sx3_d2(1) <= sx2(2) ; sx3_d3(1) <= sx2(3) ; + sx3_d0(2) <= sx2(0) ; sx3_d1(2) <= sx2(1) ; sx3_d2(2) <= sx2(2) ; sx3_d3(2) <= sx2(3) ; + sx3_d0(3) <= sx2(4) ; sx3_d1(3) <= sx2(5) ; sx3_d2(3) <= sx2(6) ; sx3_d3(3) <= sx2(7) ; + sx3_d0(4) <= sx2(4) ; sx3_d1(4) <= sx2(5) ; sx3_d2(4) <= sx2(6) ; sx3_d3(4) <= sx2(7) ; + sx3_d0(5) <= sx2(4) ; sx3_d1(5) <= sx2(5) ; sx3_d2(5) <= sx2(6) ; sx3_d3(5) <= sx2(7) ; + + + u_sx3_0: sx3_0_b(0 to 5) <= not( (sx3_s0(0 to 5) and sx3_d0(0 to 5) ) or + (sx3_s1(0 to 5) and sx3_d1(0 to 5) ) ); + + u_sx3_1: sx3_1_b(0 to 5) <= not( (sx3_s2(0 to 5) and sx3_d2(0 to 5) ) or + (sx3_s3(0 to 5) and sx3_d3(0 to 5) ) ); + + u_sx3: sx3(0 to 5) <= not( sx3_0_b(0 to 5) and sx3_1_b(0 to 5) ); + + u_oi1s: sign_copy_b(0 to 5) <= not( sx3(0 to 5) ) ; + u_oi2s: algebraic_bit(0 to 5) <= not( sign_copy_b(0 to 5) ) ; + + -- top funny physical placement to minimize wrap wires ... also nice for LE adjust + ----------- + -- 0 31 + -- 1 30 + -- 2 29 + -- 3 28 + -- 4 27 + -- 5 26 + -- 6 25 + -- 7 24 + ----------- + -- 8 23 + -- 9 22 + -- 10 21 + -- 11 20 + -- 12 19 + -- 13 18 + -- 14 17 + -- 15 16 + ----------- + -- bot + +-- ############################################################### +-- ## Latches +-- ############################################################### + + di_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 32, init=>(1 to 32=>'0'), btr => "NLI0001_X4_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + VD => vdd ,--inout + GD => gnd ,--inout + LCLK => my_lclk ,--lclk.clk + D1CLK => my_d1clk , + D2CLK => my_d2clk , + SCANIN => di_lat_si , + SCANOUT => di_lat_so , + D => di_din(0 to 31) , + QB => di_q_b(0 to 31) ); + + shx16_gp0_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 4, init=>(1 to 4=>'0'), btr => "NLI0001_X4_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + VD => vdd ,--inout + GD => gnd ,--inout + LCLK => my_lclk ,--lclk.clk + D1CLK => my_d1clk , + D2CLK => my_d2clk , + SCANIN => shx16_gp0_lat_si , + SCANOUT => shx16_gp0_lat_so , + D => shx16_gp0_din , + QB => shx16_gp0_q_b(0 to 3) ); + + shx16_gp1_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 4, init=>(1 to 4=>'0'), btr => "NLI0001_X4_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + VD => vdd ,--inout + GD => gnd ,--inout + LCLK => my_lclk ,--lclk.clk + D1CLK => my_d1clk , + D2CLK => my_d2clk , + SCANIN => shx16_gp1_lat_si , + SCANOUT => shx16_gp1_lat_so , + D => shx16_gp1_din , + QB => shx16_gp1_q_b(0 to 3) ); + + shx04_gp0_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 4, init=>(1 to 4=>'0'), btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + VD => vdd ,--inout + GD => gnd ,--inout + LCLK => my_lclk ,--lclk.clk + D1CLK => my_d1clk , + D2CLK => my_d2clk , + SCANIN => shx04_gp0_lat_si , + SCANOUT => shx04_gp0_lat_so , + D => shx04_gp0_din , + QB => shx04_gp0_q_b(0 to 3) ); + + shx04_gp1_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 4, init=>(1 to 4=>'0'), btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + VD => vdd ,--inout + GD => gnd ,--inout + LCLK => my_lclk ,--lclk.clk + D1CLK => my_d1clk , + D2CLK => my_d2clk , + SCANIN => shx04_gp1_lat_si , + SCANOUT => shx04_gp1_lat_so , + D => shx04_gp1_din , + QB => shx04_gp1_q_b(0 to 3) ); + + shx01_gp0_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 4, init=>(1 to 4=>'0'), btr => "NLI0001_X1_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + VD => vdd ,--inout + GD => gnd ,--inout + LCLK => my_lclk ,--lclk.clk + D1CLK => my_d1clk , + D2CLK => my_d2clk , + SCANIN => shx01_gp0_lat_si , + SCANOUT => shx01_gp0_lat_so , + D => shx01_gp0_din , + QB => shx01_gp0_q_b(0 to 3) ); + + shx01_gp1_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 4, init=>(1 to 4=>'0'), btr => "NLI0001_X1_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + VD => vdd ,--inout + GD => gnd ,--inout + LCLK => my_lclk ,--lclk.clk + D1CLK => my_d1clk , + D2CLK => my_d2clk , + SCANIN => shx01_gp1_lat_si , + SCANOUT => shx01_gp1_lat_so , + D => shx01_gp1_din , + QB => shx01_gp1_q_b(0 to 3) ); + + mask_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 6, init=>(1 to 6=>'0'), btr => "NLI0001_X1_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + VD => vdd ,--inout + GD => gnd ,--inout + LCLK => my_lclk ,--lclk.clk + D1CLK => my_d1clk , + D2CLK => my_d2clk , + SCANIN => mask_lat_si , + SCANOUT => mask_lat_so , + D => mask_din , + QB => mask_q_b(0 to 5) ); + + + + shx16_sgn0_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 2, init=>(1 to 2=>'0'),btr => "NLI0001_X4_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + VD => vdd ,--inout + GD => gnd ,--inout + LCLK => my_lclk ,--lclk.clk + D1CLK => my_d1clk , + D2CLK => my_d2clk , + SCANIN => shx16_sgn0_lat_si , + SCANOUT => shx16_sgn0_lat_so , + D => shx16_sgn0_din , + QB => shx16_sgn0_q_b(0 to 1) ); + + + shx04_sgn0_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 4, init=>(1 to 4=>'0'),btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + VD => vdd ,--inout + GD => gnd ,--inout + LCLK => my_lclk ,--lclk.clk + D1CLK => my_d1clk , + D2CLK => my_d2clk , + SCANIN => shx04_sgn0_lat_si , + SCANOUT => shx04_sgn0_lat_so , + D => shx04_sgn0_din , + QB => shx04_sgn0_q_b(0 to 3) ); + + shx01_sgn0_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 4, init=>(1 to 4=>'0'),btr => "NLI0001_X1_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( + VD => vdd ,--inout + GD => gnd ,--inout + LCLK => my_lclk ,--lclk.clk + D1CLK => my_d1clk , + D2CLK => my_d2clk , + SCANIN => shx01_sgn0_lat_si , + SCANOUT => shx01_sgn0_lat_so , + D => shx01_sgn0_din , + QB => shx01_sgn0_q_b(0 to 3) ); + +-- ############################################################### +-- ## Scan Chain Hookup +-- ############################################################### + + di_lat_si(0) <= scan_in; + di_lat_si(1 to 31) <= di_lat_so(0 to 30); + shx16_gp0_lat_si(0) <= di_lat_so(31); + shx16_gp0_lat_si(1 to 3) <= shx16_gp0_lat_so(0 to 2); + shx16_gp1_lat_si(0) <= shx16_gp0_lat_so(3); + shx16_gp1_lat_si(1 to 3) <= shx16_gp1_lat_so(0 to 2); + shx04_gp0_lat_si(0) <= shx16_gp1_lat_so(3); + shx04_gp0_lat_si(1 to 3) <= shx04_gp0_lat_so(0 to 2); + shx04_gp1_lat_si(0) <= shx04_gp0_lat_so(3); + shx04_gp1_lat_si(1 to 3) <= shx04_gp1_lat_so(0 to 2); + shx01_gp0_lat_si(0) <= shx04_gp1_lat_so(3); + shx01_gp0_lat_si(1 to 3) <= shx01_gp0_lat_so(0 to 2); + shx01_gp1_lat_si(0) <= shx01_gp0_lat_so(3); + shx01_gp1_lat_si(1 to 3) <= shx01_gp1_lat_so(0 to 2); + mask_lat_si(0) <= shx01_gp1_lat_so(3); + mask_lat_si(1 to 5) <= mask_lat_so(0 to 4); + shx16_sgn0_lat_si(0) <= mask_lat_so(5); + shx16_sgn0_lat_si(1) <= shx16_sgn0_lat_so(0); + shx04_sgn0_lat_si(0) <= shx16_sgn0_lat_so(1); + shx04_sgn0_lat_si(1 to 3) <= shx04_sgn0_lat_so(0 to 2); + shx01_sgn0_lat_si(0) <= shx04_sgn0_lat_so(3); + shx01_sgn0_lat_si(1 to 3) <= shx01_sgn0_lat_so(0 to 2); + scan_out <= shx01_sgn0_lat_so(3); + +-- ############################################################### +-- ## LCBs +-- ############################################################### + + my_lcb: tri_lcbnd generic map (expand_type => expand_type) port map ( + delay_lclkr => delay_lclkr_dc ,--in -- tidn , + mpw1_b => mpw1_dc_b ,--in -- tidn , + mpw2_b => mpw2_dc_b ,--in -- tidn , + forcee => func_sl_force ,--in -- tidn , + nclk => nclk ,--in + vd => vdd ,--inout + gd => gnd ,--inout + act => act ,--in + sg => sg_0 ,--in + thold_b => func_sl_thold_0_b ,--in + d1clk => my_d1clk ,--out + d2clk => my_d2clk ,--out + lclk => my_lclk );--out + +end architecture xuq_lsu_data_rot32s_ru; diff --git a/rel/src/vhdl/work/xuq_lsu_data_st.vhdl b/rel/src/vhdl/work/xuq_lsu_data_st.vhdl new file mode 100644 index 0000000..39322cd --- /dev/null +++ b/rel/src/vhdl/work/xuq_lsu_data_st.vhdl @@ -0,0 +1,1043 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XU LSU Store Data Rotator Wrapper +-- + +library ibm, ieee, work, tri, support; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use tri.tri_latches_pkg.all; +use support.power_logic_pkg.all; + +-- ########################################################################################## +-- VHDL Contents +-- 1) 16 Byte Unaligned Rotator +-- 2) Little Endian Support for 2,4,8,16 Byte Operations +-- 3) Byte Enable Generation +-- ########################################################################################## +entity xuq_lsu_data_st is +generic(expand_type : integer := 2; -- 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) + regmode : integer := 6; -- Register Mode 5 = 32bit, 6 = 64bit + l_endian_m : integer := 1); -- 1 = little endian mode enabled, 0 = little endian mode disabled +port( + + -- Acts to latches + ex2_stg_act :in std_ulogic; + ex3_stg_act :in std_ulogic; + rel2_stg_act :in std_ulogic; + rel3_stg_act :in std_ulogic; + rel2_ex2_stg_act :in std_ulogic; + rel3_ex3_stg_act :in std_ulogic; + + --reload path + rel_data_rot_sel :in std_ulogic; + ldq_rel_rot_sel :in std_ulogic_vector(0 to 4); + ldq_rel_op_size :in std_ulogic_vector(0 to 5); + ldq_rel_le_mode :in std_ulogic; + ldq_rel_algebraic :in std_ulogic; + ldq_rel_data_val :in std_ulogic_vector(0 to 15); -- Reload Data is Valid + rel_alg_bit :in std_ulogic; + + -- Execution Pipe Store Data Rotator/BE_Gen Controls + ex2_opsize :in std_ulogic_vector(0 to 5); + ex2_rot_sel :in std_ulogic_vector(0 to 4); + ex2_rot_sel_le :in std_ulogic_vector(0 to 3); + ex2_rot_addr :in std_ulogic_vector(1 to 5); + ex4_le_mode_sel :in std_ulogic_vector(0 to 15); + ex4_be_mode_sel :in std_ulogic_vector(0 to 15); + + -- Reload/EX3 Data that needs rotating + rel_ex3_data :in std_ulogic_vector(0 to 255); + rel_ex3_par_gen :in std_ulogic_vector(0 to 31); + + -- Rotated Data + rel_256ld_data :out std_ulogic_vector(0 to 255); + rel_64ld_data :out std_ulogic_vector(64-(2**regmode) to 63); + rel_xu_ld_par :out std_ulogic_vector(0 to 7); + ex4_256st_data :out std_ulogic_vector(0 to 255); + ex3_byte_en :out std_ulogic_vector(0 to 31); + ex4_parity_gen :out std_ulogic_vector(0 to 31); + rel_axu_le_mode :out std_ulogic; + rel_dvc_byte_mask :out std_ulogic_vector((64-(2**regmode))/8 to 7); + + -- Pervasive + vdd :inout power_logic; + gnd :inout power_logic; + nclk :in clk_logic; + sg_0 :in std_ulogic; + func_sl_thold_0_b :in std_ulogic; + func_sl_force :in std_ulogic; + func_nsl_thold_0_b :in std_ulogic; + func_nsl_force :in std_ulogic; + d_mode_dc :in std_ulogic; + delay_lclkr_dc :in std_ulogic; + mpw1_dc_b :in std_ulogic; + mpw2_dc_b :in std_ulogic; + scan_in :in std_ulogic; + scan_out :out std_ulogic + ); +-- synopsys translate_off +-- synopsys translate_on +end xuq_lsu_data_st; +---- +architecture xuq_lsu_data_st of xuq_lsu_data_st is + +---------------------------- +-- components +---------------------------- + +---------------------------- +-- constants +---------------------------- +constant ex3_byte_en_offset :natural := 0; +constant rel_opsize_offset :natural := ex3_byte_en_offset + 32; +constant rel_xu_le_mode_offset :natural := rel_opsize_offset + 6; +constant rel_algebraic_offset :natural := rel_xu_le_mode_offset + 1; +constant ex4_wrt_data_offset :natural := rel_algebraic_offset + 1; +constant ex4_wrt_data_le_offset :natural := ex4_wrt_data_offset + 256; +constant rel_256ld_data_offset :natural := ex4_wrt_data_le_offset + 256; +constant rel_dvc_byte_mask_offset :natural := rel_256ld_data_offset + 256; +constant ex4_parity_gen_offset :natural := rel_dvc_byte_mask_offset + (2**regmode)/8; +constant ex4_parity_gen_le_offset :natural := ex4_parity_gen_offset + 32; +constant my_spare_latches_offset :natural := ex4_parity_gen_le_offset + 32; +constant scan_right :natural := my_spare_latches_offset + 12 - 1; + +---------------------------- +-- signals +---------------------------- +signal op_size :std_ulogic_vector(0 to 5); +signal op_sel :std_ulogic_vector(0 to 15); +signal be10_en :std_ulogic_vector(0 to 31); +signal beC840_en :std_ulogic_vector(0 to 31); +signal be3210_en :std_ulogic_vector(0 to 31); +signal byte_en :std_ulogic_vector(0 to 31); +signal ex3_byte_en_d :std_ulogic_vector(0 to 31); +signal ex3_byte_en_q :std_ulogic_vector(0 to 31); +signal rot_addr :std_ulogic_vector(1 to 5); +signal data256_rot :std_ulogic_vector(0 to 255); +signal data256_rot_le :std_ulogic_vector(0 to 255); +signal rot_sel :std_ulogic_vector(0 to 4); +signal rot_sel_le :std_ulogic_vector(0 to 3); +signal rel_upd_gpr :std_ulogic; +signal rel_rot_sel :std_ulogic_vector(0 to 4); +signal rel_le_mode :std_ulogic; +signal rel_opsize_d :std_ulogic_vector(0 to 5); +signal rel_opsize_q :std_ulogic_vector(0 to 5); +signal rel_xu_le_mode_d :std_ulogic; +signal rel_xu_le_mode_q :std_ulogic; +signal rel_xu_opsize :std_ulogic_vector(0 to 5); +signal rel_xu_algebraic :std_ulogic; +signal optype_mask :std_ulogic_vector(0 to 255); +signal bittype_mask :std_ulogic_vector(0 to 31); +signal rel_msk_data :std_ulogic_vector(0 to 255); +signal rel_algebraic_d :std_ulogic; +signal rel_algebraic_q :std_ulogic; +signal lh_algebraic :std_ulogic; +signal lw_algebraic :std_ulogic; +signal lh_algebraic_msk :std_ulogic_vector(0 to 47); +signal lw_algebraic_msk :std_ulogic_vector(0 to 47); +signal algebraic_msk :std_ulogic_vector(0 to 47); +signal algebraic_msk_data :std_ulogic_vector(0 to 255); +signal rel_parity_gen :std_ulogic_vector(0 to 7); +signal rel_xu_data :std_ulogic_vector(0 to 255); +signal rotate_select :std_ulogic_vector(0 to 4); +signal rotate_sel1 :std_ulogic_vector(0 to 3); +signal rotate_sel2 :std_ulogic_vector(0 to 3); +signal rotate_sel3 :std_ulogic_vector(0 to 3); +signal le_rotate_sel2 :std_ulogic_vector(0 to 3); +signal le_rotate_sel3 :std_ulogic_vector(0 to 3); +signal rel_xu_rot_sel1 :std_ulogic_vector(0 to 63); +signal rel_xu_rot_sel1_d :std_ulogic_vector(0 to 63); +signal rel_xu_rot_sel1_q :std_ulogic_vector(0 to 63); +signal rel_xu_rot_sel2 :std_ulogic_vector(0 to 63); +signal rel_xu_rot_sel2_d :std_ulogic_vector(0 to 63); +signal rel_xu_rot_sel2_q :std_ulogic_vector(0 to 63); +signal rel_xu_rot_sel3 :std_ulogic_vector(0 to 63); +signal rel_xu_rot_sel3_d :std_ulogic_vector(0 to 63); +signal rel_xu_rot_sel3_q :std_ulogic_vector(0 to 63); +signal le_xu_rot_sel2 :std_ulogic_vector(0 to 63); +signal le_xu_rot_sel2_d :std_ulogic_vector(0 to 63); +signal le_xu_rot_sel2_q :std_ulogic_vector(0 to 63); +signal le_xu_rot_sel3 :std_ulogic_vector(0 to 63); +signal le_xu_rot_sel3_d :std_ulogic_vector(0 to 63); +signal le_xu_rot_sel3_q :std_ulogic_vector(0 to 63); +signal le_mode_select :std_ulogic; +signal reload_algbit :std_ulogic; +signal lvl1_sel :std_ulogic_vector(0 to 1); +signal lvl2_sel :std_ulogic_vector(0 to 1); +signal lvl3_sel :std_ulogic_vector(0 to 1); +signal le_lvl2_sel :std_ulogic_vector(0 to 1); +signal le_lvl3_sel :std_ulogic_vector(0 to 1); +signal rel_xu_par_gen :std_ulogic_vector(0 to 31); +signal pgrot3210 :std_ulogic_vector(0 to 31); +signal pgrotC840 :std_ulogic_vector(0 to 31); +signal pgrot10 :std_ulogic_vector(0 to 31); +signal ex3_par_rot :std_ulogic_vector(0 to 31); +signal rel_swzl_data :std_ulogic_vector(0 to 255); +signal rel_val_data :std_ulogic_vector(0 to 15); +signal ex3_parity_gen :std_ulogic_vector(0 to 31); +signal ex4_parity_gen_d :std_ulogic_vector(0 to 31); +signal ex4_parity_gen_q :std_ulogic_vector(0 to 31); +signal ex4_parity_gen_le_d :std_ulogic_vector(0 to 31); +signal ex4_parity_gen_le_q :std_ulogic_vector(0 to 31); +signal rel_256ld_data_d :std_ulogic_vector(0 to 255); +signal rel_256ld_data_q :std_ulogic_vector(0 to 255); +signal ex3_wrt_data :std_ulogic_vector(0 to 255); +signal ex4_wrt_data_d :std_ulogic_vector(0 to 255); +signal ex4_wrt_data_q :std_ulogic_vector(0 to 255); +signal ex4_wrt_data_le_d :std_ulogic_vector(0 to 255); +signal ex4_wrt_data_le_q :std_ulogic_vector(0 to 255); +signal le_xu_par_gen :std_ulogic_vector(0 to 31); +signal le_pgrotC840 :std_ulogic_vector(0 to 31); +signal le_pgrot3210 :std_ulogic_vector(0 to 31); +signal ex3_par_rot_le :std_ulogic_vector(0 to 31); +signal rel_byte_mask :std_ulogic_vector(0 to 7); +signal rel_dvc_byte_mask_d :std_ulogic_vector((64-(2**regmode))/8 to 7); +signal rel_dvc_byte_mask_q :std_ulogic_vector((64-(2**regmode))/8 to 7); +signal my_spare0_lclk :clk_logic; +signal my_spare0_d1clk :std_ulogic; +signal my_spare0_d2clk :std_ulogic; +signal my_spare_latches_d :std_ulogic_vector(0 to 11); +signal my_spare_latches_q :std_ulogic_vector(0 to 11); + +signal tiup :std_ulogic; +signal siv :std_ulogic_vector(0 to scan_right); +signal sov :std_ulogic_vector(0 to scan_right); + +begin + +tiup <= '1'; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Inputs +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +rel_upd_gpr <= rel_data_rot_sel; + +-- This signals are not muxed latched, need to latch them only +rel_opsize_d <= ldq_rel_op_size; +rel_algebraic_d <= ldq_rel_algebraic; + +-- This signals are all muxed latched +rel_rot_sel <= ldq_rel_rot_sel; +rel_le_mode <= ldq_rel_le_mode; + +op_size <= ex2_opsize; +rot_sel <= ex2_rot_sel; +rot_sel_le <= ex2_rot_sel_le; +rot_addr <= ex2_rot_addr; + +rel_xu_data <= rel_ex3_data; +rel_xu_par_gen <= rel_ex3_par_gen; +reload_algbit <= rel_alg_bit; + +rel_val_data <= ldq_rel_data_val; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Select Between Reload and Store Data +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +with rel_upd_gpr select + rotate_select <= rot_sel when '0', + rel_rot_sel when others; + +with rel_upd_gpr select + le_mode_select <= '0' when '0', + rel_le_mode when others; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Create 1-hot Rotate Select +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +lvl1_sel <= le_mode_select & rotate_select(0); +lvl2_sel <= rotate_select(1 to 2); +lvl3_sel <= rotate_select(3 to 4); + +with lvl1_sel select + rotate_sel1 <= "1000" when "00", + "0100" when "01", + "0010" when "10", + "0001" when others; + +with lvl2_sel select + rotate_sel2 <= "1000" when "00", + "0100" when "01", + "0010" when "10", + "0001" when others; + +with lvl3_sel select + rotate_sel3 <= "1000" when "00", + "0100" when "01", + "0010" when "10", + "0001" when others; + +rel_xu_le_mode_d <= le_mode_select; + +selGen : for sel in 0 to 15 generate begin + rel_xu_rot_sel1_d(4*sel to (4*sel)+3) <= rotate_sel1; + rel_xu_rot_sel2_d(4*sel to (4*sel)+3) <= rotate_sel2; + rel_xu_rot_sel3_d(4*sel to (4*sel)+3) <= rotate_sel3; +end generate selGen; + +rel_xu_rot_sel1 <= rel_xu_rot_sel1_q; +rel_xu_rot_sel2 <= rel_xu_rot_sel2_q; +rel_xu_rot_sel3 <= rel_xu_rot_sel3_q; +rel_xu_opsize <= rel_opsize_q; +rel_xu_algebraic <= rel_algebraic_q; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Create 1-hot Rotate Select For Little-Endian Rotator +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +le_lvl2_sel <= rot_sel_le(0 to 1); +le_lvl3_sel <= rot_sel_le(2 to 3); + +with le_lvl2_sel select + le_rotate_sel2 <= "1000" when "00", + "0100" when "01", + "0010" when "10", + "0001" when others; + +with le_lvl3_sel select + le_rotate_sel3 <= "1000" when "00", + "0100" when "01", + "0010" when "10", + "0001" when others; + +leSelGen : for sel in 0 to 15 generate begin + le_xu_rot_sel2_d(4*sel to (4*sel)+3) <= le_rotate_sel2; + le_xu_rot_sel3_d(4*sel to (4*sel)+3) <= le_rotate_sel3; +end generate leSelGen; + +le_xu_rot_sel2 <= le_xu_rot_sel2_q; +le_xu_rot_sel3 <= le_xu_rot_sel3_q; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Execution Pipe Data Parity Rotation +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +---- LE,16 byte rotation +pglvl1rot: for byte in 0 to 31 generate +signal muxIn :std_ulogic_vector(0 to 3); +signal muxSel :std_ulogic_vector(0 to 3); +begin + muxIn <= rel_xu_par_gen(byte) & rel_xu_par_gen((16+byte) mod 32) & + rel_xu_par_gen(31 - byte) & rel_xu_par_gen(31 - ((16+byte) mod 32)); + muxSel <= rel_xu_rot_sel1(4*(byte/16) to (4*(byte/16))+3); + + mux4sel: entity work.xuq_lsu_mux41(xuq_lsu_mux41) + port map ( vdd => vdd, + gnd => gnd, + d0 => muxIn(0), + d1 => muxIn(1), + d2 => muxIn(2), + d3 => muxIn(3), + s0 => muxSel(0), + s1 => muxSel(1), + s2 => muxSel(2), + s3 => muxSel(3), + y => pgrot10(byte)); +end generate pglvl1rot; + +-- 0/16/LE,4,8,12 byte rotation +pglvl2rot: for byte in 0 to 31 generate +signal muxIn :std_ulogic_vector(0 to 3); +signal muxSel :std_ulogic_vector(0 to 3); +begin + muxIn <= pgrot10(byte) & pgrot10((4+byte) mod 32) & + pgrot10((8+byte) mod 32) & pgrot10((12+byte) mod 32); + muxSel <= rel_xu_rot_sel2(4*(byte/16) to (4*(byte/16))+3); + + mux4sel: entity work.xuq_lsu_mux41(xuq_lsu_mux41) + port map (vdd => vdd, + gnd => gnd, + d0 => muxIn(0), + d1 => muxIn(1), + d2 => muxIn(2), + d3 => muxIn(3), + s0 => muxSel(0), + s1 => muxSel(1), + s2 => muxSel(2), + s3 => muxSel(3), + y => pgrotC840(byte)); +end generate pglvl2rot; + +---- 0/4/8/12/16/LE,1,2,3 byte rotation +pglvl3rot: for byte in 0 to 31 generate +signal muxIn :std_ulogic_vector(0 to 3); +signal muxSel :std_ulogic_vector(0 to 3); +begin + muxIn <= pgrotC840(byte) & pgrotC840((1+byte) mod 32) & + pgrotC840((2+byte) mod 32) & pgrotC840((3+byte) mod 32); + muxSel <= rel_xu_rot_sel3(4*(byte/16) to (4*(byte/16))+3); + + mux4sel: entity work.xuq_lsu_mux41(xuq_lsu_mux41) + port map ( vdd => vdd, + gnd => gnd, + d0 => muxIn(0), + d1 => muxIn(1), + d2 => muxIn(2), + d3 => muxIn(3), + s0 => muxSel(0), + s1 => muxSel(1), + s2 => muxSel(2), + s3 => muxSel(3), + y => pgrot3210(byte)); +end generate pglvl3rot; + +ex3_par_rot <= pgrot3210; +-- ############################################################################################# + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Execution Pipe Data Parity Rotation +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +ParSwap : for bit in 0 to 31 generate begin + le_xu_par_gen(bit) <= rel_xu_par_gen(31-bit); +end generate ParSwap; + +-- 0,4,8,12 byte rotation +lePglvl2rot: for byte in 0 to 31 generate +signal muxIn :std_ulogic_vector(0 to 3); +signal muxSel :std_ulogic_vector(0 to 3); +begin + muxIn <= le_xu_par_gen(byte) & le_xu_par_gen((4+byte) mod 32) & + le_xu_par_gen((8+byte) mod 32) & le_xu_par_gen((12+byte) mod 32); + muxSel <= le_xu_rot_sel2(4*(byte/16) to (4*(byte/16))+3); + + mux4sel: entity work.xuq_lsu_mux41(xuq_lsu_mux41) + port map (vdd => vdd, + gnd => gnd, + d0 => muxIn(0), + d1 => muxIn(1), + d2 => muxIn(2), + d3 => muxIn(3), + s0 => muxSel(0), + s1 => muxSel(1), + s2 => muxSel(2), + s3 => muxSel(3), + y => le_pgrotC840(byte)); +end generate lePglvl2rot; + +---- 0/4/8/12,1,2,3 byte rotation +lePglvl3rot: for byte in 0 to 31 generate +signal muxIn :std_ulogic_vector(0 to 3); +signal muxSel :std_ulogic_vector(0 to 3); +begin + muxIn <= le_pgrotC840(byte) & le_pgrotC840((1+byte) mod 32) & + le_pgrotC840((2+byte) mod 32) & le_pgrotC840((3+byte) mod 32); + muxSel <= le_xu_rot_sel3(4*(byte/16) to (4*(byte/16))+3); + + mux4sel: entity work.xuq_lsu_mux41(xuq_lsu_mux41) + port map ( vdd => vdd, + gnd => gnd, + d0 => muxIn(0), + d1 => muxIn(1), + d2 => muxIn(2), + d3 => muxIn(3), + s0 => muxSel(0), + s1 => muxSel(1), + s2 => muxSel(2), + s3 => muxSel(3), + y => le_pgrot3210(byte)); +end generate lePglvl3rot; + +ex3_par_rot_le <= le_pgrot3210; +-- ############################################################################################# + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Byte Enable Generation +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +-- Need to generate byte enables for the type of operation +-- size1 => 0x8000 +-- size2 => 0xC000 +-- size4 => 0xF000 +-- size8 => 0xFF00 +-- size16 => 0xFFFF +op_sel(0) <= op_size(1) or op_size(2) or op_size(3) or op_size(4) or op_size(5); +op_sel(1) <= op_size(1) or op_size(2) or op_size(3) or op_size(4); +op_sel(2) <= op_size(1) or op_size(2) or op_size(3); +op_sel(3) <= op_size(1) or op_size(2) or op_size(3); +op_sel(4) <= op_size(1) or op_size(2); +op_sel(5) <= op_size(1) or op_size(2); +op_sel(6) <= op_size(1) or op_size(2); +op_sel(7) <= op_size(1) or op_size(2); +op_sel(8) <= op_size(1); +op_sel(9) <= op_size(1); +op_sel(10) <= op_size(1); +op_sel(11) <= op_size(1); +op_sel(12) <= op_size(1); +op_sel(13) <= op_size(1); +op_sel(14) <= op_size(1); +op_sel(15) <= op_size(1); + +-- 32 Bit Rotator +-- Need to Rotate optype generated byte enables +with rot_addr(1) select + be10_en <= op_sel(0 to 15) & x"0000" when '0', + x"0000" & op_sel(0 to 15) when others; + +-- Selects between Data rotated by 0, 4, 8, or 12 bits +with rot_addr(2 to 3) select + beC840_en <= be10_en(0 to 31) when "00", + x"0" & be10_en(0 to 27) when "01", + x"00" & be10_en(0 to 23) when "10", + x"000" & be10_en(0 to 19) when others; + +-- Selects between Data rotated by 0, 1, 2, or 3 bits +with rot_addr(4 to 5) select + be3210_en <= beC840_en(0 to 31) when "00", + '0' & beC840_en(0 to 30) when "01", + "00" & beC840_en(0 to 29) when "10", + "000" & beC840_en(0 to 28) when others; + +-- Byte Enables Generated using the opsize and physical_addr(60 to 63) +ben_gen : for t in 0 to 31 generate begin + byte_en(t) <= op_size(0) or be3210_en(t); +end generate ben_gen; + +ex3_byte_en_d <= byte_en; + +-- ############################################################################################# +-- 32 Byte Rotator +-- ############################################################################################# + +l1dcrotl0 : entity work.xuq_lsu_data_rot32_lu(xuq_lsu_data_rot32_lu) +generic map(l_endian_m => l_endian_m) +port map ( + + vdd => vdd, + gnd => gnd, + + -- Rotator Controls and Data + rot_sel1 => rel_xu_rot_sel1(0 to 31), + rot_sel2 => rel_xu_rot_sel2(0 to 31), + rot_sel3 => rel_xu_rot_sel3(0 to 31), + rot_sel2_le => le_xu_rot_sel2(0 to 31), + rot_sel3_le => le_xu_rot_sel3(0 to 31), + rot_data => rel_xu_data(0 to 127), + + -- Rotated Data + data256_rot_le => data256_rot_le(0 to 127), + data256_rot => data256_rot(0 to 127) +); + +l1dcrotl1 : entity work.xuq_lsu_data_rot32_lu(xuq_lsu_data_rot32_lu) +generic map(l_endian_m => l_endian_m) +port map ( + + vdd => vdd, + gnd => gnd, + + -- Rotator Controls and Data + rot_sel1 => rel_xu_rot_sel1(32 to 63), + rot_sel2 => rel_xu_rot_sel2(32 to 63), + rot_sel3 => rel_xu_rot_sel3(32 to 63), + rot_sel2_le => le_xu_rot_sel2(32 to 63), + rot_sel3_le => le_xu_rot_sel3(32 to 63), + rot_data => rel_xu_data(128 to 255), + + -- Rotated Data + data256_rot_le => data256_rot_le(128 to 255), + data256_rot => data256_rot(128 to 255) +); + +-- ############################################################################################# +-- Op Size Mask Generation for Reloads +-- ############################################################################################# + +--with rel_xu_opsize select +-- optype_mask <= x"0000000000000000000000000000000F0000000000000000000000000000000F" when "000001", +-- x"000000000000000000000000000000FF000000000000000000000000000000FF" when "000010", +-- x"0000000000000000000000000000FFFF0000000000000000000000000000FFFF" when "000100", +-- x"000000000000000000000000FFFFFFFF000000000000000000000000FFFFFFFF" when "001000", +-- x"0000000000000000FFFFFFFFFFFFFFFF0000000000000000FFFFFFFFFFFFFFFF" when "010000", +-- x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" when others; + +with rel_xu_opsize(2 to 5) select + rel_byte_mask <= x"01" when "0001", + x"03" when "0010", + x"0F" when "0100", + x"FF" when others; + +rel_dvc_byte_mask_d <= rel_byte_mask((64-(2**regmode))/8 to 7); + +with rel_xu_opsize select + bittype_mask <= x"00000001" when "000001", + x"00000003" when "000010", + x"0000000F" when "000100", + x"000000FF" when "001000", + x"0000FFFF" when "010000", + x"FFFFFFFF" when others; + +maskGen : for bit in 0 to 7 generate begin + optype_mask(bit*32 to (bit*32)+31) <= bittype_mask; +end generate maskGen; + +rel_msk_data <= data256_rot and optype_mask; + +lh_algebraic <= rel_xu_opsize(4) and rel_xu_algebraic; +lw_algebraic <= rel_xu_opsize(3) and rel_xu_algebraic; +lh_algebraic_msk <= (0 to 47 => reload_algbit); +lw_algebraic_msk <= (0 to 31 => reload_algbit) & x"0000"; +algebraic_msk <= gate(lh_algebraic_msk,lh_algebraic) or gate(lw_algebraic_msk,lw_algebraic); + +rel256data : for t in 0 to 31 generate begin + rel_swzl_data(t*8 to (t*8)+7) <= rel_msk_data(t) & rel_msk_data(t+32) & rel_msk_data(t+64) & rel_msk_data(t+96) & + rel_msk_data(t+128) & rel_msk_data(t+160) & rel_msk_data(t+192) & rel_msk_data(t+224); +end generate rel256data; + +algebraic_msk_data <= rel_swzl_data(0 to 191) & (rel_swzl_data(192 to 239) or algebraic_msk) & rel_swzl_data(240 to 255); +rel_256ld_data_d <= algebraic_msk_data; + +-- ############################################################################################# +-- Mux Reload and Store Data +-- ############################################################################################# + +-- LE Data +ex4_wrt_data_le_d <= data256_rot_le; +ex4_parity_gen_le_d <= ex3_par_rot_le; + +-- BE Data +ex3_wrt_data <= data256_rot; +ex3_parity_gen <= ex3_par_rot; + +-- Mux between reload and BE store +wrtData : for t in 0 to 7 generate begin + ex4_wrt_data_d(t*32 to (t*32)+31) <= gate(rel_xu_data(t*32 to (t*32)+31),rel_val_data(t)) or gate(ex3_wrt_data(t*32 to (t*32)+31),rel_val_data(t+8)); +end generate wrtData; + +-- Data Write Parity Generation +wrtPar : for t in 0 to 31 generate begin + ex4_parity_gen_d(t) <= (rel_xu_par_gen(t) and rel_val_data(t mod 8)) or (ex3_parity_gen(t) and rel_val_data((t mod 8)+8)); +end generate wrtPar; + +-- Mux between reload/BEstore and LEstore +leSel : for t in 0 to 15 generate begin + ex4_256st_data(t*16 to (t*16)+15) <= gate(ex4_wrt_data_le_q(t*16 to (t*16)+15), ex4_le_mode_sel(t)) or gate(ex4_wrt_data_q(t*16 to (t*16)+15), ex4_be_mode_sel(t)); + ex4_parity_gen(t*2 to (t*2)+1) <= gate(ex4_parity_gen_le_q(t*2 to (t*2)+1), ex4_le_mode_sel(t)) or gate(ex4_parity_gen_q(t*2 to (t*2)+1), ex4_be_mode_sel(t)); +end generate leSel; + +-- ############################################################################################# +-- XU 8 Byte Reload Data Parity Generation +-- ############################################################################################# +-- Array Data Parity Generation +relpar_gen : for t in 0 to 7 generate begin + R0 : if (t < (2**regmode)/8) generate begin + rel_parity_gen(t) <= xor_reduce(rel_256ld_data_q((t*8)+256-(2**regmode) to (t*8)+256-(2**regmode)+7)); + end generate; + R1 : if( t >= (2**regmode)/8) generate begin rel_parity_gen(t) <= '0'; end generate; +end generate relpar_gen; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Spare Latches +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +my_spare_latches_d <= not my_spare_latches_q; + +-- ############################################################################################# +-- Outputs +-- ############################################################################################# +ex3_byte_en <= ex3_byte_en_q; +rel_256ld_data <= rel_256ld_data_q; +rel_64ld_data <= rel_256ld_data_q(256-(2**regmode) to 255); +rel_xu_ld_par <= rel_parity_gen; +rel_axu_le_mode <= rel_xu_le_mode_q; +rel_dvc_byte_mask <= rel_dvc_byte_mask_q; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Registers +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +-- Scan Latches +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +ex3_byte_en_reg: tri_rlmreg_p + generic map (width => 32, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_byte_en_offset to ex3_byte_en_offset + ex3_byte_en_d'length-1), + scout => sov(ex3_byte_en_offset to ex3_byte_en_offset + ex3_byte_en_d'length-1), + din => ex3_byte_en_d, + dout => ex3_byte_en_q); + +rel_opsize_reg: tri_rlmreg_p + generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_opsize_offset to rel_opsize_offset + rel_opsize_d'length-1), + scout => sov(rel_opsize_offset to rel_opsize_offset + rel_opsize_d'length-1), + din => rel_opsize_d, + dout => rel_opsize_q); + +rel_xu_le_mode_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_ex2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_xu_le_mode_offset), + scout => sov(rel_xu_le_mode_offset), + din => rel_xu_le_mode_d, + dout => rel_xu_le_mode_q); + +rel_algebraic_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_algebraic_offset), + scout => sov(rel_algebraic_offset), + din => rel_algebraic_d, + dout => rel_algebraic_q); + +ex4_wrt_data_reg: tri_rlmreg_p + generic map (width => 256, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_ex3_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_wrt_data_offset to ex4_wrt_data_offset + ex4_wrt_data_d'length-1), + scout => sov(ex4_wrt_data_offset to ex4_wrt_data_offset + ex4_wrt_data_d'length-1), + din => ex4_wrt_data_d, + dout => ex4_wrt_data_q); + +ex4_wrt_data_le_reg: tri_rlmreg_p + generic map (width => 256, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_wrt_data_le_offset to ex4_wrt_data_le_offset + ex4_wrt_data_le_d'length-1), + scout => sov(ex4_wrt_data_le_offset to ex4_wrt_data_le_offset + ex4_wrt_data_le_d'length-1), + din => ex4_wrt_data_le_d, + dout => ex4_wrt_data_le_q); + +rel_256ld_data_reg: tri_rlmreg_p + generic map (width => 256, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_256ld_data_offset to rel_256ld_data_offset + rel_256ld_data_d'length-1), + scout => sov(rel_256ld_data_offset to rel_256ld_data_offset + rel_256ld_data_d'length-1), + din => rel_256ld_data_d, + dout => rel_256ld_data_q); + +rel_dvc_byte_mask_reg: tri_rlmreg_p + generic map (width => (2**regmode)/8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_dvc_byte_mask_offset to rel_dvc_byte_mask_offset + rel_dvc_byte_mask_d'length-1), + scout => sov(rel_dvc_byte_mask_offset to rel_dvc_byte_mask_offset + rel_dvc_byte_mask_d'length-1), + din => rel_dvc_byte_mask_d, + dout => rel_dvc_byte_mask_q); + +ex4_parity_gen_reg: tri_rlmreg_p + generic map (width => 32, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_ex3_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_parity_gen_offset to ex4_parity_gen_offset + ex4_parity_gen_d'length-1), + scout => sov(ex4_parity_gen_offset to ex4_parity_gen_offset + ex4_parity_gen_d'length-1), + din => ex4_parity_gen_d, + dout => ex4_parity_gen_q); + +ex4_parity_gen_le_reg: tri_rlmreg_p + generic map (width => 32, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_parity_gen_le_offset to ex4_parity_gen_le_offset + ex4_parity_gen_le_d'length-1), + scout => sov(ex4_parity_gen_le_offset to ex4_parity_gen_le_offset + ex4_parity_gen_le_d'length-1), + din => ex4_parity_gen_le_d, + dout => ex4_parity_gen_le_q); + +my_spare0_lcb : entity tri.tri_lcbnd(tri_lcbnd) +generic map (expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + d1clk => my_spare0_d1clk, + d2clk => my_spare0_d2clk, + lclk => my_spare0_lclk); +my_spare_latches_reg: entity tri.tri_inv_nlats(tri_inv_nlats) +generic map (width => 12, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + lclk => my_spare0_lclk, + d1clk => my_spare0_d1clk, + d2clk => my_spare0_d2clk, + scanin => siv(my_spare_latches_offset to my_spare_latches_offset + my_spare_latches_d'length-1), + scanout => sov(my_spare_latches_offset to my_spare_latches_offset + my_spare_latches_d'length-1), + d => my_spare_latches_d, + qb => my_spare_latches_q); + +-- Non-Scan Latches +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +rel_xu_rot_sel1_0reg: tri_regk + generic map (width => 32, init => 286331153, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_ex2_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_xu_rot_sel1_d(0 to 31), + dout => rel_xu_rot_sel1_q(0 to 31)); + +rel_xu_rot_sel1_1reg: tri_regk + generic map (width => 32, init => 286331153, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_ex2_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_xu_rot_sel1_d(32 to 63), + dout => rel_xu_rot_sel1_q(32 to 63)); + +rel_xu_rot_sel2_0reg: tri_regk + generic map (width => 32, init => 286331153, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_ex2_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_xu_rot_sel2_d(0 to 31), + dout => rel_xu_rot_sel2_q(0 to 31)); + +rel_xu_rot_sel2_1reg: tri_regk + generic map (width => 32, init => 286331153, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_ex2_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_xu_rot_sel2_d(32 to 63), + dout => rel_xu_rot_sel2_q(32 to 63)); + +rel_xu_rot_sel3_0reg: tri_regk + generic map (width => 32, init => 286331153, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_ex2_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_xu_rot_sel3_d(0 to 31), + dout => rel_xu_rot_sel3_q(0 to 31)); + +rel_xu_rot_sel3_1reg: tri_regk + generic map (width => 32, init => 286331153, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_ex2_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_xu_rot_sel3_d(32 to 63), + dout => rel_xu_rot_sel3_q(32 to 63)); + +le_xu_rot_sel2_0reg: tri_regk + generic map (width => 32, init => 286331153, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => le_xu_rot_sel2_d(0 to 31), + dout => le_xu_rot_sel2_q(0 to 31)); + +le_xu_rot_sel2_1reg: tri_regk + generic map (width => 32, init => 286331153, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => le_xu_rot_sel2_d(32 to 63), + dout => le_xu_rot_sel2_q(32 to 63)); + +le_xu_rot_sel3_0reg: tri_regk + generic map (width => 32, init => 286331153, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => le_xu_rot_sel3_d(0 to 31), + dout => le_xu_rot_sel3_q(0 to 31)); + +le_xu_rot_sel3_1reg: tri_regk + generic map (width => 32, init => 286331153, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => le_xu_rot_sel3_d(32 to 63), + dout => le_xu_rot_sel3_q(32 to 63)); + +siv(0 to scan_right) <= sov(1 to scan_right) & scan_in; +scan_out <= sov(0); + +end xuq_lsu_data_st; diff --git a/rel/src/vhdl/work/xuq_lsu_dc.vhdl b/rel/src/vhdl/work/xuq_lsu_dc.vhdl new file mode 100644 index 0000000..617e145 --- /dev/null +++ b/rel/src/vhdl/work/xuq_lsu_dc.vhdl @@ -0,0 +1,1024 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XU LSU L1 Data Cache +-- + +library ibm, ieee, work, tri, support; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use tri.tri_latches_pkg.all; +use support.power_logic_pkg.all; + +-- ########################################################################################## +-- VHDL Contents +-- 1) Staging Latches +-- 2) Exception Handling +-- 3) Flush Generation +-- ########################################################################################## + +entity xuq_lsu_dc is +generic(expand_type : integer := 2; -- 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) + l_endian_m : integer := 1; -- 1 = little endian mode enabled, 0 = little endian mode disabled + regmode : integer := 6; -- Register Mode 5 = 32bit, 6 = 64bit + dc_size : natural := 14; -- 2^14 = 16384 Bytes L1 D$ + parBits : natural := 4; -- Number of Parity Bits + real_data_add : integer := 42); -- 42 bit real address +port( + + -- Execution Pipe Inputs + xu_lsu_rf0_act :in std_ulogic; + xu_lsu_rf1_cmd_act :in std_ulogic; + xu_lsu_rf1_axu_op_val :in std_ulogic; -- Operation is from the AXU + xu_lsu_rf1_axu_ldst_falign :in std_ulogic; -- AXU force alignment indicator + xu_lsu_rf1_axu_ldst_fexcpt :in std_ulogic; -- AXU force alignment exception on misaligned access + xu_lsu_rf1_cache_acc :in std_ulogic; -- Cache Access is Valid, Op that touches directory + xu_lsu_rf1_thrd_id :in std_ulogic_vector(0 to 3); -- Thread ID + xu_lsu_rf1_optype1 :in std_ulogic; -- 1 Byte Load/Store + xu_lsu_rf1_optype2 :in std_ulogic; -- 2 Byte Load/Store + xu_lsu_rf1_optype4 :in std_ulogic; -- 4 Byte Load/Store + xu_lsu_rf1_optype8 :in std_ulogic; -- 8 Byte Load/Store + xu_lsu_rf1_optype16 :in std_ulogic; -- 16 Byte Load/Store + xu_lsu_rf1_optype32 :in std_ulogic; -- 32 Byte Load/Store + xu_lsu_rf1_target_gpr :in std_ulogic_vector(0 to 8); -- Target GPR, needed for reloads + xu_lsu_rf1_mtspr_trace :in std_ulogic; -- Operation is a mtspr trace instruction + xu_lsu_rf1_load_instr :in std_ulogic; -- Operation is a Load instruction + xu_lsu_rf1_store_instr :in std_ulogic; -- Operation is a Store instruction + xu_lsu_rf1_dcbf_instr :in std_ulogic; -- Operation is a DCBF instruction + xu_lsu_rf1_sync_instr :in std_ulogic; -- Operation is a SYNC instruction + xu_lsu_rf1_l_fld :in std_ulogic_vector(0 to 1); -- DCBF/SYNC L Field + xu_lsu_rf1_dcbi_instr :in std_ulogic; -- Operation is a DCBI instruction + xu_lsu_rf1_dcbz_instr :in std_ulogic; -- Operation is a DCBZ instruction + xu_lsu_rf1_dcbt_instr :in std_ulogic; -- Operation is a DCBT instruction + xu_lsu_rf1_dcbtst_instr :in std_ulogic; -- Operation is a DCBTST instruction + xu_lsu_rf1_th_fld :in std_ulogic_vector(0 to 4); -- TH/CT Field for Cache Management instructions + xu_lsu_rf1_dcbtls_instr :in std_ulogic; + xu_lsu_rf1_dcbtstls_instr :in std_ulogic; + xu_lsu_rf1_dcblc_instr :in std_ulogic; + xu_lsu_rf1_dcbst_instr :in std_ulogic; + xu_lsu_rf1_icbi_instr :in std_ulogic; + xu_lsu_rf1_icblc_instr :in std_ulogic; + xu_lsu_rf1_icbt_instr :in std_ulogic; + xu_lsu_rf1_icbtls_instr :in std_ulogic; + xu_lsu_rf1_icswx_instr :in std_ulogic; + xu_lsu_rf1_icswx_dot_instr :in std_ulogic; + xu_lsu_rf1_icswx_epid :in std_ulogic; + xu_lsu_rf1_tlbsync_instr :in std_ulogic; + xu_lsu_rf1_ldawx_instr :in std_ulogic; + xu_lsu_rf1_wclr_instr :in std_ulogic; + xu_lsu_rf1_wchk_instr :in std_ulogic; + xu_lsu_rf1_lock_instr :in std_ulogic; -- Operation is a LOCK instruction + xu_lsu_rf1_mutex_hint :in std_ulogic; -- Mutex Hint For larx instructions + xu_lsu_rf1_mbar_instr :in std_ulogic; -- Operation is an MBAR instruction + xu_lsu_rf1_is_msgsnd :in std_ulogic; + xu_lsu_rf1_dci_instr :in std_ulogic; -- DCI instruction is valid + xu_lsu_rf1_ici_instr :in std_ulogic; -- ICI instruction is valid + xu_lsu_rf1_algebraic :in std_ulogic; -- Operation is an Algebraic Load instruction + xu_lsu_rf1_byte_rev :in std_ulogic; -- Operation is a Byte Reversal Load/Store instruction + xu_lsu_rf1_src_gpr :in std_ulogic; -- Source is the GPR's for mfloat and mDCR ops + xu_lsu_rf1_src_axu :in std_ulogic; -- Source is the AXU's for mfloat and mDCR ops + xu_lsu_rf1_src_dp :in std_ulogic; -- Source is the BOX's for mfloat and mDCR ops + xu_lsu_rf1_targ_gpr :in std_ulogic; -- Target is the GPR's for mfloat and mDCR ops + xu_lsu_rf1_targ_axu :in std_ulogic; -- Target is the AXU's for mfloat and mDCR ops + xu_lsu_rf1_targ_dp :in std_ulogic; -- Target is the BOX's for mfloat and mDCR ops + xu_lsu_ex4_val :in std_ulogic_vector(0 to 3); -- There is a valid Instruction in EX4 + + -- Dependency Checking on loadmisses + xu_lsu_rf1_src0_vld :in std_ulogic; -- Source0 is Valid + xu_lsu_rf1_src0_reg :in std_ulogic_vector(0 to 7); -- Source0 Register + xu_lsu_rf1_src1_vld :in std_ulogic; -- Source1 is Valid + xu_lsu_rf1_src1_reg :in std_ulogic_vector(0 to 7); -- Source1 Register + xu_lsu_rf1_targ_vld :in std_ulogic; -- Target is Valid + xu_lsu_rf1_targ_reg :in std_ulogic_vector(0 to 7); -- Target Register + + -- Physical Address in EX2 + ex2_p_addr_lwr :in std_ulogic_vector(52 to 63); + ex2_lm_dep_hit :in std_ulogic; -- Sources for Op match target in loadmiss queue + + ex3_wimge_w_bit :in std_ulogic; -- WIMGE bits in EX3 + ex3_wimge_i_bit :in std_ulogic; -- WIMGE bits in EX3 + ex3_wimge_e_bit :in std_ulogic; -- WIMGE bits in EX3 + ex3_p_addr :in std_ulogic_vector(64-real_data_add to 51); + ex3_ld_queue_full :in std_ulogic; -- LSQ load queue full + ex3_stq_flush :in std_ulogic; -- LSQ store queue full + ex3_ig_flush :in std_ulogic; -- LSQ I=G=1 flush + ex3_hit :in std_ulogic; -- EX3 Load/Store Hit + ex4_miss :in std_ulogic; -- EX4 Load/Store Miss + ex4_snd_ld_l2 :in std_ulogic; -- Request is being sent to the L2 + derat_xu_ex3_noop_touch :in std_ulogic_vector(0 to 3); + ex3_cClass_collision :in std_ulogic; -- Thread Collision with same Congruence Class and Way + ex2_lockwatchSet_rel_coll :in std_ulogic; -- DCBT[ST]LS or WatchSet instruction collided with Reload Clear Stage + ex3_wclr_all_flush :in std_ulogic; -- Watch clear all in pipe flushing other threads in pipe + rel_dcarr_val_upd :in std_ulogic; -- Reload Data Array Update Valid + + -- Data Cache Config Bits + xu_lsu_mtspr_trace_en :in std_ulogic_vector(0 to 3); + spr_xucr0_clkg_ctl_b1 :in std_ulogic; -- Override Clock Gating + xu_lsu_spr_xucr0_aflsta :in std_ulogic; -- Force load/store Alignment Exception (AXU) + xu_lsu_spr_xucr0_flsta :in std_ulogic; -- Force load/store Alignment Exception (XU) + xu_lsu_spr_xucr0_l2siw :in std_ulogic; -- L2 store interface width + xu_lsu_spr_xucr0_dcdis :in std_ulogic; -- Data Cache Disable + xu_lsu_spr_xucr0_wlk :in std_ulogic; -- Data Cache Way Locking Enable + xu_lsu_spr_ccr2_dfrat :in std_ulogic; -- Force Real Address Translation + xu_lsu_spr_xucr0_flh2l2 :in std_ulogic; -- Force L1 load hits to L2 + xu_lsu_spr_xucr0_cls :in std_ulogic; -- Cacheline Size = 1 => 128Byte size, 0 => 64Byte size + xu_lsu_spr_msr_cm :in std_ulogic_vector(0 to 3); -- 64bit mode enable + + -- MSR[GS,PR] bits, indicates which state we are running in + xu_lsu_msr_gs :in std_ulogic_vector(0 to 3); -- Guest State + xu_lsu_msr_pr :in std_ulogic_vector(0 to 3); -- Problem State + + an_ac_flh2l2_gate :in std_ulogic; -- Gate L1 Hit forwarding SPR config bit + + -- Stage Flush from Instruction Flush Unit + xu_lsu_rf1_flush :in std_ulogic_vector(0 to 3); + xu_lsu_ex1_flush :in std_ulogic_vector(0 to 3); + xu_lsu_ex2_flush :in std_ulogic_vector(0 to 3); + xu_lsu_ex3_flush :in std_ulogic_vector(0 to 3); + xu_lsu_ex4_flush :in std_ulogic_vector(0 to 3); + xu_lsu_ex5_flush :in std_ulogic_vector(0 to 3); + + -- Slow SPR Bus + xu_lsu_slowspr_val :in std_ulogic; + xu_lsu_slowspr_rw :in std_ulogic; + xu_lsu_slowspr_etid :in std_ulogic_vector(0 to 1); + xu_lsu_slowspr_addr :in std_ulogic_vector(0 to 9); + xu_lsu_slowspr_data :in std_ulogic_vector(64-(2**REGMODE) to 63); + xu_lsu_slowspr_done :in std_ulogic; + slowspr_val_out :out std_ulogic; + slowspr_rw_out :out std_ulogic; + slowspr_etid_out :out std_ulogic_vector(0 to 1); + slowspr_addr_out :out std_ulogic_vector(0 to 9); + slowspr_data_out :out std_ulogic_vector(64-(2**REGMODE) to 63); + slowspr_done_out :out std_ulogic; + + -- L2 Operation Flush + ldq_rel_data_val_early :in std_ulogic; -- Reload Interface ACT + ldq_rel_stg24_val :in std_ulogic; -- Reload Stages 2 and 4 are valid + ldq_rel_axu_val :in std_ulogic; -- Reload is for a Vector Register + ldq_rel_thrd_id :in std_ulogic_vector(0 to 3); -- Thread ID of the reload + ldq_rel_ta_gpr :in std_ulogic_vector(0 to 8); + ldq_rel_upd_gpr :in std_ulogic; -- Reload data should be written to GPR (DCB ops don't write to GPRs) + ldq_rel_ci :in std_ulogic; -- Cache-Inhibited Reload is Valid + is2_l2_inv_val :in std_ulogic; -- L2 Back-Invalidate is Valid + + ex3_wayA_tag :in std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex3_wayB_tag :in std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex3_wayC_tag :in std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex3_wayD_tag :in std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex3_wayE_tag :in std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex3_wayF_tag :in std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex3_wayG_tag :in std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex3_wayH_tag :in std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex3_way_tag_par_a :in std_ulogic_vector(0 to parBits-1); + ex3_way_tag_par_b :in std_ulogic_vector(0 to parBits-1); + ex3_way_tag_par_c :in std_ulogic_vector(0 to parBits-1); + ex3_way_tag_par_d :in std_ulogic_vector(0 to parBits-1); + ex3_way_tag_par_e :in std_ulogic_vector(0 to parBits-1); + ex3_way_tag_par_f :in std_ulogic_vector(0 to parBits-1); + ex3_way_tag_par_g :in std_ulogic_vector(0 to parBits-1); + ex3_way_tag_par_h :in std_ulogic_vector(0 to parBits-1); + ex4_way_a_dir :in std_ulogic_vector(0 to 5); + ex4_way_b_dir :in std_ulogic_vector(0 to 5); + ex4_way_c_dir :in std_ulogic_vector(0 to 5); + ex4_way_d_dir :in std_ulogic_vector(0 to 5); + ex4_way_e_dir :in std_ulogic_vector(0 to 5); + ex4_way_f_dir :in std_ulogic_vector(0 to 5); + ex4_way_g_dir :in std_ulogic_vector(0 to 5); + ex4_way_h_dir :in std_ulogic_vector(0 to 5); + ex4_dir_lru :in std_ulogic_vector(0 to 6); + + -- Dependency Checking on loadmisses + ex1_src0_vld :out std_ulogic; -- Source0 is Valid + ex1_src0_reg :out std_ulogic_vector(0 to 7); -- Source0 Register + ex1_src1_vld :out std_ulogic; -- Source1 is Valid + ex1_src1_reg :out std_ulogic_vector(0 to 7); -- Source1 Register + ex1_targ_vld :out std_ulogic; -- Target is Valid + ex1_targ_reg :out std_ulogic_vector(0 to 7); -- Target Register + ex1_check_watch :out std_ulogic_vector(0 to 3); -- Instructions that need to wait for ldawx to complete in loadmiss queue + + -- Execution Pipe Outputs + ex1_lsu_64bit_agen :out std_ulogic; + ex1_frc_align2 :out std_ulogic; + ex1_frc_align4 :out std_ulogic; + ex1_frc_align8 :out std_ulogic; + ex1_frc_align16 :out std_ulogic; + ex1_frc_align32 :out std_ulogic; + ex1_dir_acc_val :out std_ulogic; + ex3_cache_acc :out std_ulogic; + ex1_optype1 :out std_ulogic; + ex1_optype2 :out std_ulogic; + ex1_optype4 :out std_ulogic; + ex1_optype8 :out std_ulogic; + ex1_optype16 :out std_ulogic; + ex1_optype32 :out std_ulogic; + ex1_saxu_instr :out std_ulogic; + ex1_sdp_instr :out std_ulogic; + ex1_stgpr_instr :out std_ulogic; + ex1_store_instr :out std_ulogic; + ex1_axu_op_val :out std_ulogic; + ex2_no_lru_upd :out std_ulogic; + ex2_is_inval_op :out std_ulogic; + ex2_lock_set :out std_ulogic; + ex2_lock_clr :out std_ulogic; + ex2_ddir_acc_instr :out std_ulogic; + + ex3_p_addr_lwr :out std_ulogic_vector(58 to 63); + ex3_req_thrd_id :out std_ulogic_vector(0 to 3); + ex3_target_gpr :out std_ulogic_vector(0 to 8); + ex3_dcbt_instr :out std_ulogic; + ex3_dcbtst_instr :out std_ulogic; + ex3_th_fld_l2 :out std_ulogic; + ex3_dcbst_instr :out std_ulogic; + ex3_dcbf_instr :out std_ulogic; + ex3_sync_instr :out std_ulogic; + ex3_mtspr_trace :out std_ulogic; + ex3_byte_en :out std_ulogic_vector(0 to 31); + ex2_l_fld :out std_ulogic_vector(0 to 1); + ex3_l_fld :out std_ulogic_vector(0 to 1); + ex3_dcbi_instr :out std_ulogic; + ex3_dcbz_instr :out std_ulogic; + ex3_icbi_instr :out std_ulogic; + ex3_icswx_instr :out std_ulogic; + ex3_icswx_dot :out std_ulogic; + ex3_icswx_epid :out std_ulogic; + ex3_mbar_instr :out std_ulogic; + ex3_msgsnd_instr :out std_ulogic; + ex3_dci_instr :out std_ulogic; + ex3_ici_instr :out std_ulogic; + ex3_load_instr :out std_ulogic; + ex2_store_instr :out std_ulogic; + ex3_store_instr :out std_ulogic; + ex3_axu_op_val :out std_ulogic; + ex3_algebraic :out std_ulogic; + ex3_dcbtls_instr :out std_ulogic; + ex3_dcbtstls_instr :out std_ulogic; + ex3_dcblc_instr :out std_ulogic; + ex3_icblc_instr :out std_ulogic; + ex3_icbt_instr :out std_ulogic; + ex3_icbtls_instr :out std_ulogic; + ex3_tlbsync_instr :out std_ulogic; + ex3_local_dcbf :out std_ulogic; + ex4_drop_rel :out std_ulogic; + ex3_load_l1hit :out std_ulogic; + ex3_rotate_sel :out std_ulogic_vector(0 to 4); + ex1_thrd_id :out std_ulogic_vector(0 to 3); + ex2_ldawx_instr :out std_ulogic; + ex2_wclr_instr :out std_ulogic; + ex2_wchk_val :out std_ulogic; + ex3_watch_en :out std_ulogic; + ex3_data_swap :out std_ulogic; + ex3_load_val :out std_ulogic; + ex3_blkable_touch :out std_ulogic; + ex3_l2_request :out std_ulogic; + ex3_ldq_potential_flush :out std_ulogic; + ex7_targ_match :out std_ulogic; -- EX6vsEX5 matched + ex8_targ_match :out std_ulogic; -- EX7vsEX6 or EX7vsEX5 matched + ex4_ld_entry :out std_ulogic_vector(0 to 67); + + -- Physical Address in EX3 + ex3_lock_en :out std_ulogic; + ex3_cache_en :out std_ulogic; + ex3_cache_inh :out std_ulogic; + ex3_l_s_q_val :out std_ulogic; + ex3_drop_ld_req :out std_ulogic; + ex3_drop_touch :out std_ulogic; + ex3_stx_instr :out std_ulogic; + ex3_larx_instr :out std_ulogic; + ex3_mutex_hint :out std_ulogic; + ex3_opsize :out std_ulogic_vector(0 to 5); + ex4_store_hit :out std_ulogic; + ex4_load_op_hit :out std_ulogic; + ex5_load_op_hit :out std_ulogic; + ex4_axu_op_val :out std_ulogic; + + -- SPR's + spr_xucr2_rmt :out std_ulogic_vector(0 to 31); + spr_xucr0_wlck :out std_ulogic; + spr_dvc1_act :out std_ulogic; + spr_dvc2_act :out std_ulogic; + spr_dvc1_dbg :out std_ulogic_vector(64-(2**regmode) to 63); + spr_dvc2_dbg :out std_ulogic_vector(64-(2**regmode) to 63); + + -- SPR status + lsu_xu_spr_xucr0_cul :out std_ulogic; -- Cache Lock unable to lock + spr_xucr0_cls :out std_ulogic; -- Cacheline Size + agen_xucr0_cls :out std_ulogic; + + -- Directory Read interface + dir_arr_rd_is2_val :out std_ulogic; + dir_arr_rd_congr_cl :out std_ulogic_vector(0 to 4); + + -- Interrupt Generation + lsu_xu_ex3_align :out std_ulogic_vector(0 to 3); + lsu_xu_ex3_dsi :out std_ulogic_vector(0 to 3); + lsu_xu_ex3_inval_align_2ucode :out std_ulogic; + + -- Flush Pipe Outputs + ex2_stg_flush :out std_ulogic; -- Flush Instructions in EX2 + ex3_stg_flush :out std_ulogic; -- Flush Instructions in EX3 + ex4_stg_flush :out std_ulogic; -- Flush Instructions in EX4 + ex5_stg_flush :out std_ulogic; -- Flush Instructions in EX5 + lsu_xu_ex3_n_flush_req :out std_ulogic; -- Data Cache Instruction Flush in EX3 + lsu_xu_ex3_dep_flush :out std_ulogic; -- RAW/WAW Dependency Flush + + -- Back-invalidate + rf1_l2_inv_val :out std_ulogic; + ex1_agen_binv_val :out std_ulogic; + ex1_l2_inv_val :out std_ulogic; + + -- Update Data Array Valid + rel_upd_dcarr_val :out std_ulogic; + + lsu_xu_ex4_cr_upd :out std_ulogic; + lsu_xu_ex5_wren :out std_ulogic; + lsu_xu_rel_wren :out std_ulogic; + lsu_xu_rel_ta_gpr :out std_ulogic_vector(0 to 7); + + lsu_xu_perf_events :out std_ulogic_vector(0 to 20); + lsu_xu_need_hole :out std_ulogic; + + xu_fu_ex5_reload_val :out std_ulogic; + xu_fu_ex5_load_val :out std_ulogic_vector(0 to 3); + xu_fu_ex5_load_tag :out std_ulogic_vector(0 to 8); + + -- ICBI Interface + xu_iu_ex6_icbi_val :out std_ulogic_vector(0 to 3); + xu_iu_ex6_icbi_addr :out std_ulogic_vector(64-real_data_add to 57); + + -- DERAT SlowSPR Regs + xu_derat_epsc_wr :out std_ulogic_vector(0 to 3); + xu_derat_eplc_wr :out std_ulogic_vector(0 to 3); + xu_derat_eplc0_epr :out std_ulogic; + xu_derat_eplc0_eas :out std_ulogic; + xu_derat_eplc0_egs :out std_ulogic; + xu_derat_eplc0_elpid :out std_ulogic_vector(40 to 47); + xu_derat_eplc0_epid :out std_ulogic_vector(50 to 63); + xu_derat_eplc1_epr :out std_ulogic; + xu_derat_eplc1_eas :out std_ulogic; + xu_derat_eplc1_egs :out std_ulogic; + xu_derat_eplc1_elpid :out std_ulogic_vector(40 to 47); + xu_derat_eplc1_epid :out std_ulogic_vector(50 to 63); + xu_derat_eplc2_epr :out std_ulogic; + xu_derat_eplc2_eas :out std_ulogic; + xu_derat_eplc2_egs :out std_ulogic; + xu_derat_eplc2_elpid :out std_ulogic_vector(40 to 47); + xu_derat_eplc2_epid :out std_ulogic_vector(50 to 63); + xu_derat_eplc3_epr :out std_ulogic; + xu_derat_eplc3_eas :out std_ulogic; + xu_derat_eplc3_egs :out std_ulogic; + xu_derat_eplc3_elpid :out std_ulogic_vector(40 to 47); + xu_derat_eplc3_epid :out std_ulogic_vector(50 to 63); + xu_derat_epsc0_epr :out std_ulogic; + xu_derat_epsc0_eas :out std_ulogic; + xu_derat_epsc0_egs :out std_ulogic; + xu_derat_epsc0_elpid :out std_ulogic_vector(40 to 47); + xu_derat_epsc0_epid :out std_ulogic_vector(50 to 63); + xu_derat_epsc1_epr :out std_ulogic; + xu_derat_epsc1_eas :out std_ulogic; + xu_derat_epsc1_egs :out std_ulogic; + xu_derat_epsc1_elpid :out std_ulogic_vector(40 to 47); + xu_derat_epsc1_epid :out std_ulogic_vector(50 to 63); + xu_derat_epsc2_epr :out std_ulogic; + xu_derat_epsc2_eas :out std_ulogic; + xu_derat_epsc2_egs :out std_ulogic; + xu_derat_epsc2_elpid :out std_ulogic_vector(40 to 47); + xu_derat_epsc2_epid :out std_ulogic_vector(50 to 63); + xu_derat_epsc3_epr :out std_ulogic; + xu_derat_epsc3_eas :out std_ulogic; + xu_derat_epsc3_egs :out std_ulogic; + xu_derat_epsc3_elpid :out std_ulogic_vector(40 to 47); + xu_derat_epsc3_epid :out std_ulogic_vector(50 to 63); + + -- Debug Data + dc_fgen_dbg_data :out std_ulogic_vector(0 to 1); + dc_cntrl_dbg_data :out std_ulogic_vector(0 to 66); + + -- ACT signals + ex1_stg_act :out std_ulogic; + ex2_stg_act :out std_ulogic; + ex3_stg_act :out std_ulogic; + ex4_stg_act :out std_ulogic; + ex5_stg_act :out std_ulogic; + binv1_stg_act :out std_ulogic; + binv2_stg_act :out std_ulogic; + binv3_stg_act :out std_ulogic; + binv4_stg_act :out std_ulogic; + binv5_stg_act :out std_ulogic; + rel1_stg_act :out std_ulogic; + rel2_stg_act :out std_ulogic; + rel3_stg_act :out std_ulogic; + + -- Pervasive + vdd :inout power_logic; + gnd :inout power_logic; + nclk :in clk_logic; + sg_0 :in std_ulogic; + func_sl_thold_0_b :in std_ulogic; + func_sl_force :in std_ulogic; + func_slp_sl_thold_0_b :in std_ulogic; + func_slp_sl_force :in std_ulogic; + func_nsl_thold_0_b :in std_ulogic; + func_nsl_force :in std_ulogic; + func_slp_nsl_thold_0_b :in std_ulogic; + func_slp_nsl_force :in std_ulogic; + d_mode_dc :in std_ulogic; + delay_lclkr_dc :in std_ulogic; + mpw1_dc_b :in std_ulogic; + mpw2_dc_b :in std_ulogic; + scan_in :in std_ulogic; + scan_out :out std_ulogic +); +-- synopsys translate_off +-- synopsys translate_on +end xuq_lsu_dc; +---- +architecture xuq_lsu_dc of xuq_lsu_dc is + +---------------------------- +-- components +---------------------------- + +---------------------------- +-- constants +---------------------------- +constant dccntrl_offset :natural := 0; +constant dcfgen_offset :natural := dccntrl_offset + 1; +constant scan_right :natural := dcfgen_offset + 1 - 1; + +---------------------------- +-- signals +---------------------------- +signal stg_flush_rf1 :std_ulogic; +signal stg_flush_ex1 :std_ulogic; +signal stg_flush_ex2 :std_ulogic; +signal stg_flush_ex3 :std_ulogic; +signal stg_flush_ex4 :std_ulogic; +signal stg_flush_ex5 :std_ulogic; +signal ex1_thrd_id_int :std_ulogic_vector(0 to 3); +signal ex2_thrd_id :std_ulogic_vector(0 to 3); +signal ex3_thrd_id :std_ulogic_vector(0 to 3); +signal ex4_thrd_id :std_ulogic_vector(0 to 3); +signal ex5_thrd_id :std_ulogic_vector(0 to 3); +signal ex2_cache_acc :std_ulogic; +signal ex2_icswx_type :std_ulogic; +signal ex2_store_instr_int :std_ulogic; +signal ex2_load_instr :std_ulogic; +signal ex2_dcbz_instr :std_ulogic; +signal ex2_lock_instr :std_ulogic; +signal ex2_ldawx_instr_int :std_ulogic; +signal ex3_targ_match_b1 :std_ulogic; +signal ex2_targ_match_b2 :std_ulogic; +signal ex2_mv_reg_op :std_ulogic; +signal ex2_axu_op :std_ulogic; +signal ex3_excp_det :std_ulogic; +signal ex2_optype2 :std_ulogic; +signal ex2_optype4 :std_ulogic; +signal ex2_optype8 :std_ulogic; +signal ex2_optype16 :std_ulogic; +signal ex2_optype32 :std_ulogic; +signal ex2_ldst_fexcpt :std_ulogic; +signal ex3_lsq_flush :std_ulogic; + +signal siv :std_ulogic_vector(0 to scan_right); +signal sov :std_ulogic_vector(0 to scan_right); + +begin + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Inputs +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Data Cache Staging Latches and Control +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +l1dccntrl : entity work.xuq_lsu_dc_cntrl(xuq_lsu_dc_cntrl) +generic map(expand_type => expand_type, + regmode => regmode, + dc_size => dc_size, + parBits => parBits, + real_data_add => real_data_add) +port map( + + -- Execution Pipe Inputs + xu_lsu_rf0_act => xu_lsu_rf0_act, + xu_lsu_rf1_cmd_act => xu_lsu_rf1_cmd_act, + xu_lsu_rf1_axu_op_val => xu_lsu_rf1_axu_op_val, + xu_lsu_rf1_axu_ldst_falign => xu_lsu_rf1_axu_ldst_falign, + xu_lsu_rf1_axu_ldst_fexcpt => xu_lsu_rf1_axu_ldst_fexcpt, + xu_lsu_rf1_cache_acc => xu_lsu_rf1_cache_acc, + xu_lsu_rf1_thrd_id => xu_lsu_rf1_thrd_id, + xu_lsu_rf1_optype1 => xu_lsu_rf1_optype1, + xu_lsu_rf1_optype2 => xu_lsu_rf1_optype2, + xu_lsu_rf1_optype4 => xu_lsu_rf1_optype4, + xu_lsu_rf1_optype8 => xu_lsu_rf1_optype8, + xu_lsu_rf1_optype16 => xu_lsu_rf1_optype16, + xu_lsu_rf1_optype32 => xu_lsu_rf1_optype32, + xu_lsu_rf1_target_gpr => xu_lsu_rf1_target_gpr, + xu_lsu_rf1_mtspr_trace => xu_lsu_rf1_mtspr_trace, + xu_lsu_rf1_load_instr => xu_lsu_rf1_load_instr, + xu_lsu_rf1_store_instr => xu_lsu_rf1_store_instr, + xu_lsu_rf1_dcbf_instr => xu_lsu_rf1_dcbf_instr, + xu_lsu_rf1_sync_instr => xu_lsu_rf1_sync_instr, + xu_lsu_rf1_l_fld => xu_lsu_rf1_l_fld, + xu_lsu_rf1_dcbi_instr => xu_lsu_rf1_dcbi_instr, + xu_lsu_rf1_dcbz_instr => xu_lsu_rf1_dcbz_instr, + xu_lsu_rf1_dcbt_instr => xu_lsu_rf1_dcbt_instr, + xu_lsu_rf1_dcbtst_instr => xu_lsu_rf1_dcbtst_instr, + xu_lsu_rf1_th_fld => xu_lsu_rf1_th_fld, + xu_lsu_rf1_dcbtls_instr => xu_lsu_rf1_dcbtls_instr, + xu_lsu_rf1_dcbtstls_instr => xu_lsu_rf1_dcbtstls_instr, + xu_lsu_rf1_dcblc_instr => xu_lsu_rf1_dcblc_instr, + xu_lsu_rf1_dcbst_instr => xu_lsu_rf1_dcbst_instr, + xu_lsu_rf1_icbi_instr => xu_lsu_rf1_icbi_instr, + xu_lsu_rf1_icblc_instr => xu_lsu_rf1_icblc_instr, + xu_lsu_rf1_icbt_instr => xu_lsu_rf1_icbt_instr, + xu_lsu_rf1_icbtls_instr => xu_lsu_rf1_icbtls_instr, + xu_lsu_rf1_icswx_instr => xu_lsu_rf1_icswx_instr, + xu_lsu_rf1_icswx_dot_instr => xu_lsu_rf1_icswx_dot_instr, + xu_lsu_rf1_icswx_epid => xu_lsu_rf1_icswx_epid, + xu_lsu_rf1_tlbsync_instr => xu_lsu_rf1_tlbsync_instr, + xu_lsu_rf1_ldawx_instr => xu_lsu_rf1_ldawx_instr, + xu_lsu_rf1_wclr_instr => xu_lsu_rf1_wclr_instr, + xu_lsu_rf1_wchk_instr => xu_lsu_rf1_wchk_instr, + xu_lsu_rf1_lock_instr => xu_lsu_rf1_lock_instr, + xu_lsu_rf1_mutex_hint => xu_lsu_rf1_mutex_hint, + xu_lsu_rf1_mbar_instr => xu_lsu_rf1_mbar_instr, + xu_lsu_rf1_is_msgsnd => xu_lsu_rf1_is_msgsnd, + xu_lsu_rf1_dci_instr => xu_lsu_rf1_dci_instr, + xu_lsu_rf1_ici_instr => xu_lsu_rf1_ici_instr, + xu_lsu_rf1_algebraic => xu_lsu_rf1_algebraic, + xu_lsu_rf1_byte_rev => xu_lsu_rf1_byte_rev, + xu_lsu_rf1_src_gpr => xu_lsu_rf1_src_gpr, + xu_lsu_rf1_src_axu => xu_lsu_rf1_src_axu, + xu_lsu_rf1_src_dp => xu_lsu_rf1_src_dp, + xu_lsu_rf1_targ_gpr => xu_lsu_rf1_targ_gpr, + xu_lsu_rf1_targ_axu => xu_lsu_rf1_targ_axu, + xu_lsu_rf1_targ_dp => xu_lsu_rf1_targ_dp, + xu_lsu_ex4_val => xu_lsu_ex4_val, + + -- Dependency Checking on loadmisses + xu_lsu_rf1_src0_vld => xu_lsu_rf1_src0_vld, + xu_lsu_rf1_src0_reg => xu_lsu_rf1_src0_reg, + xu_lsu_rf1_src1_vld => xu_lsu_rf1_src1_vld, + xu_lsu_rf1_src1_reg => xu_lsu_rf1_src1_reg, + xu_lsu_rf1_targ_vld => xu_lsu_rf1_targ_vld, + xu_lsu_rf1_targ_reg => xu_lsu_rf1_targ_reg, + + -- Back-Invalidate + is2_l2_inv_val => is2_l2_inv_val, + + ex3_wayA_tag => ex3_wayA_tag, + ex3_wayB_tag => ex3_wayB_tag, + ex3_wayC_tag => ex3_wayC_tag, + ex3_wayD_tag => ex3_wayD_tag, + ex3_wayE_tag => ex3_wayE_tag, + ex3_wayF_tag => ex3_wayF_tag, + ex3_wayG_tag => ex3_wayG_tag, + ex3_wayH_tag => ex3_wayH_tag, + ex3_way_tag_par_a => ex3_way_tag_par_a, + ex3_way_tag_par_b => ex3_way_tag_par_b, + ex3_way_tag_par_c => ex3_way_tag_par_c, + ex3_way_tag_par_d => ex3_way_tag_par_d, + ex3_way_tag_par_e => ex3_way_tag_par_e, + ex3_way_tag_par_f => ex3_way_tag_par_f, + ex3_way_tag_par_g => ex3_way_tag_par_g, + ex3_way_tag_par_h => ex3_way_tag_par_h, + ex4_way_a_dir => ex4_way_a_dir, + ex4_way_b_dir => ex4_way_b_dir, + ex4_way_c_dir => ex4_way_c_dir, + ex4_way_d_dir => ex4_way_d_dir, + ex4_way_e_dir => ex4_way_e_dir, + ex4_way_f_dir => ex4_way_f_dir, + ex4_way_g_dir => ex4_way_g_dir, + ex4_way_h_dir => ex4_way_h_dir, + ex4_dir_lru => ex4_dir_lru, + + ex2_p_addr_lwr => ex2_p_addr_lwr, + ex3_wimge_i_bit => ex3_wimge_i_bit, + ex3_wimge_e_bit => ex3_wimge_e_bit, + + ex3_p_addr => ex3_p_addr, + ex3_ld_queue_full => ex3_ld_queue_full, + ex3_stq_flush => ex3_stq_flush, + ex3_ig_flush => ex3_ig_flush, + ex3_hit => ex3_hit, + ex4_miss => ex4_miss, + ex4_snd_ld_l2 => ex4_snd_ld_l2, + ex3_excp_det => ex3_excp_det, + + -- Stage Flush + rf1_stg_flush => stg_flush_rf1, + ex1_stg_flush => stg_flush_ex1, + ex2_stg_flush => stg_flush_ex2, + ex3_stg_flush => stg_flush_ex3, + ex4_stg_flush => stg_flush_ex4, + ex5_stg_flush => stg_flush_ex5, + + -- Data Cache Config + xu_lsu_mtspr_trace_en => xu_lsu_mtspr_trace_en, + spr_xucr0_clkg_ctl_b1 => spr_xucr0_clkg_ctl_b1, + xu_lsu_spr_xucr0_wlk => xu_lsu_spr_xucr0_wlk, + xu_lsu_spr_ccr2_dfrat => xu_lsu_spr_ccr2_dfrat, + xu_lsu_spr_xucr0_dcdis => xu_lsu_spr_xucr0_dcdis, + xu_lsu_spr_xucr0_flh2l2 => xu_lsu_spr_xucr0_flh2l2, + xu_lsu_spr_xucr0_cls => xu_lsu_spr_xucr0_cls, + xu_lsu_spr_msr_cm => xu_lsu_spr_msr_cm, + + xu_lsu_msr_gs => xu_lsu_msr_gs, + xu_lsu_msr_pr => xu_lsu_msr_pr, + + an_ac_flh2l2_gate => an_ac_flh2l2_gate, + + -- Slow SPR Bus + xu_lsu_slowspr_val => xu_lsu_slowspr_val, + xu_lsu_slowspr_rw => xu_lsu_slowspr_rw, + xu_lsu_slowspr_etid => xu_lsu_slowspr_etid, + xu_lsu_slowspr_addr => xu_lsu_slowspr_addr, + xu_lsu_slowspr_data => xu_lsu_slowspr_data, + xu_lsu_slowspr_done => xu_lsu_slowspr_done, + slowspr_val_out => slowspr_val_out, + slowspr_rw_out => slowspr_rw_out, + slowspr_etid_out => slowspr_etid_out, + slowspr_addr_out => slowspr_addr_out, + slowspr_data_out => slowspr_data_out, + slowspr_done_out => slowspr_done_out, + + ldq_rel_data_val_early => ldq_rel_data_val_early, + ldq_rel_stg24_val => ldq_rel_stg24_val, + ldq_rel_axu_val => ldq_rel_axu_val, + ldq_rel_thrd_id => ldq_rel_thrd_id, + ldq_rel_ta_gpr => ldq_rel_ta_gpr, + ldq_rel_upd_gpr => ldq_rel_upd_gpr, + + -- Dependency Checking on loadmisses + ex1_src0_vld => ex1_src0_vld, + ex1_src0_reg => ex1_src0_reg, + ex1_src1_vld => ex1_src1_vld, + ex1_src1_reg => ex1_src1_reg, + ex1_targ_vld => ex1_targ_vld, + ex1_targ_reg => ex1_targ_reg, + ex1_check_watch => ex1_check_watch, + + -- Execution Pipe Outputs + ex1_lsu_64bit_agen => ex1_lsu_64bit_agen, + ex1_frc_align2 => ex1_frc_align2, + ex1_frc_align4 => ex1_frc_align4, + ex1_frc_align8 => ex1_frc_align8, + ex1_frc_align16 => ex1_frc_align16, + ex1_frc_align32 => ex1_frc_align32, + ex1_optype1 => ex1_optype1, + ex1_optype2 => ex1_optype2, + ex1_optype4 => ex1_optype4, + ex1_optype8 => ex1_optype8, + ex1_optype16 => ex1_optype16, + ex1_optype32 => ex1_optype32, + ex1_saxu_instr => ex1_saxu_instr, + ex1_sdp_instr => ex1_sdp_instr, + ex1_stgpr_instr => ex1_stgpr_instr, + ex1_store_instr => ex1_store_instr, + ex1_axu_op_val => ex1_axu_op_val, + ex2_optype2 => ex2_optype2, + ex2_optype4 => ex2_optype4, + ex2_optype8 => ex2_optype8, + ex2_optype16 => ex2_optype16, + ex2_optype32 => ex2_optype32, + ex2_icswx_type => ex2_icswx_type, + ex2_store_instr => ex2_store_instr_int, + ex1_dir_acc_val => ex1_dir_acc_val, + ex2_cache_acc => ex2_cache_acc, + ex3_cache_acc => ex3_cache_acc, + ex2_ldst_fexcpt => ex2_ldst_fexcpt, + ex2_axu_op => ex2_axu_op, + ex2_mv_reg_op => ex2_mv_reg_op, + ex1_thrd_id => ex1_thrd_id_int, + ex2_thrd_id => ex2_thrd_id, + ex3_thrd_id => ex3_thrd_id, + ex4_thrd_id => ex4_thrd_id, + ex5_thrd_id => ex5_thrd_id, + ex3_req_thrd_id => ex3_req_thrd_id, + ex3_targ_match_b1 => ex3_targ_match_b1, + ex2_targ_match_b2 => ex2_targ_match_b2, + ex3_target_gpr => ex3_target_gpr, + ex2_load_instr => ex2_load_instr, + ex3_dcbt_instr => ex3_dcbt_instr, + ex3_dcbtst_instr => ex3_dcbtst_instr, + ex3_th_fld_l2 => ex3_th_fld_l2, + ex3_dcbst_instr => ex3_dcbst_instr, + ex3_dcbf_instr => ex3_dcbf_instr, + ex3_sync_instr => ex3_sync_instr, + ex3_mtspr_trace => ex3_mtspr_trace, + ex3_byte_en => ex3_byte_en, + ex2_l_fld => ex2_l_fld, + ex3_l_fld => ex3_l_fld, + ex3_dcbi_instr => ex3_dcbi_instr, + ex2_dcbz_instr => ex2_dcbz_instr, + ex3_dcbz_instr => ex3_dcbz_instr, + ex3_icbi_instr => ex3_icbi_instr, + ex3_icswx_instr => ex3_icswx_instr, + ex3_icswx_dot => ex3_icswx_dot, + ex3_icswx_epid => ex3_icswx_epid, + ex3_mbar_instr => ex3_mbar_instr, + ex3_msgsnd_instr => ex3_msgsnd_instr, + ex3_dci_instr => ex3_dci_instr, + ex3_ici_instr => ex3_ici_instr, + ex2_lock_instr => ex2_lock_instr, + ex3_load_instr => ex3_load_instr, + ex3_store_instr => ex3_store_instr, + ex3_axu_op_val => ex3_axu_op_val, + ex4_drop_rel => ex4_drop_rel, + ex3_load_l1hit => ex3_load_l1hit, + ex3_rotate_sel => ex3_rotate_sel, + ex2_ldawx_instr => ex2_ldawx_instr_int, + ex2_wclr_instr => ex2_wclr_instr, + ex2_wchk_val => ex2_wchk_val, + ex3_watch_en => ex3_watch_en, + ex3_data_swap => ex3_data_swap, + ex3_load_val => ex3_load_val, + ex3_blkable_touch => ex3_blkable_touch, + ex3_l2_request => ex3_l2_request, + ex3_ldq_potential_flush => ex3_ldq_potential_flush, + ex7_targ_match => ex7_targ_match, + ex8_targ_match => ex8_targ_match, + ex4_ld_entry => ex4_ld_entry, + ex3_algebraic => ex3_algebraic, + ex3_dcbtls_instr => ex3_dcbtls_instr, + ex3_dcbtstls_instr => ex3_dcbtstls_instr, + ex3_dcblc_instr => ex3_dcblc_instr, + ex3_icblc_instr => ex3_icblc_instr, + ex3_icbt_instr => ex3_icbt_instr, + ex3_icbtls_instr => ex3_icbtls_instr, + ex3_tlbsync_instr => ex3_tlbsync_instr, + ex3_local_dcbf => ex3_local_dcbf, + rel_dcarr_val_upd => rel_dcarr_val_upd, + + ex2_no_lru_upd => ex2_no_lru_upd, + ex2_is_inval_op => ex2_is_inval_op, + ex2_lock_set => ex2_lock_set, + ex2_lock_clr => ex2_lock_clr, + ex2_ddir_acc_instr => ex2_ddir_acc_instr, + + ex3_lsq_flush => ex3_lsq_flush, + ex3_p_addr_lwr => ex3_p_addr_lwr, + ex3_lock_en => ex3_lock_en, + ex3_cache_en => ex3_cache_en, + ex3_cache_inh => ex3_cache_inh, + ex3_l_s_q_val => ex3_l_s_q_val, + ex3_drop_ld_req => ex3_drop_ld_req, + ex3_drop_touch => ex3_drop_touch, + ex3_stx_instr => ex3_stx_instr, + ex3_larx_instr => ex3_larx_instr, + ex3_mutex_hint => ex3_mutex_hint, + ex3_opsize => ex3_opsize, + ex4_store_hit => ex4_store_hit, + ex4_load_op_hit => ex4_load_op_hit, + ex5_load_op_hit => ex5_load_op_hit, + ex4_axu_op_val => ex4_axu_op_val, + + spr_xucr2_rmt => spr_xucr2_rmt, + spr_xucr0_wlck => spr_xucr0_wlck, + spr_dvc1_act => spr_dvc1_act, + spr_dvc2_act => spr_dvc2_act, + spr_dvc1_dbg => spr_dvc1_dbg, + spr_dvc2_dbg => spr_dvc2_dbg, + + -- SPR status + lsu_xu_spr_xucr0_cul => lsu_xu_spr_xucr0_cul, + spr_xucr0_cls => spr_xucr0_cls, + agen_xucr0_cls => agen_xucr0_cls, + + -- Directory Read interface + dir_arr_rd_is2_val => dir_arr_rd_is2_val, + dir_arr_rd_congr_cl => dir_arr_rd_congr_cl, + + -- Back-invalidate + rf1_l2_inv_val => rf1_l2_inv_val, + ex1_agen_binv_val => ex1_agen_binv_val, + ex1_l2_inv_val => ex1_l2_inv_val, + + -- Update Data Array Valid + rel_upd_dcarr_val => rel_upd_dcarr_val, + + lsu_xu_ex4_cr_upd => lsu_xu_ex4_cr_upd, + lsu_xu_ex5_wren => lsu_xu_ex5_wren, + lsu_xu_rel_wren => lsu_xu_rel_wren, + lsu_xu_rel_ta_gpr => lsu_xu_rel_ta_gpr, + lsu_xu_perf_events => lsu_xu_perf_events(0 to 16), + lsu_xu_need_hole => lsu_xu_need_hole, + + xu_fu_ex5_reload_val => xu_fu_ex5_reload_val, + xu_fu_ex5_load_val => xu_fu_ex5_load_val, + xu_fu_ex5_load_tag => xu_fu_ex5_load_tag, + + -- ICBI Interface + xu_iu_ex6_icbi_val => xu_iu_ex6_icbi_val, + xu_iu_ex6_icbi_addr => xu_iu_ex6_icbi_addr, + + -- DERAT SlowSPR Regs + xu_derat_epsc_wr => xu_derat_epsc_wr, + xu_derat_eplc_wr => xu_derat_eplc_wr, + xu_derat_eplc0_epr => xu_derat_eplc0_epr, + xu_derat_eplc0_eas => xu_derat_eplc0_eas, + xu_derat_eplc0_egs => xu_derat_eplc0_egs, + xu_derat_eplc0_elpid => xu_derat_eplc0_elpid, + xu_derat_eplc0_epid => xu_derat_eplc0_epid, + xu_derat_eplc1_epr => xu_derat_eplc1_epr, + xu_derat_eplc1_eas => xu_derat_eplc1_eas, + xu_derat_eplc1_egs => xu_derat_eplc1_egs, + xu_derat_eplc1_elpid => xu_derat_eplc1_elpid, + xu_derat_eplc1_epid => xu_derat_eplc1_epid, + xu_derat_eplc2_epr => xu_derat_eplc2_epr, + xu_derat_eplc2_eas => xu_derat_eplc2_eas, + xu_derat_eplc2_egs => xu_derat_eplc2_egs, + xu_derat_eplc2_elpid => xu_derat_eplc2_elpid, + xu_derat_eplc2_epid => xu_derat_eplc2_epid, + xu_derat_eplc3_epr => xu_derat_eplc3_epr, + xu_derat_eplc3_eas => xu_derat_eplc3_eas, + xu_derat_eplc3_egs => xu_derat_eplc3_egs, + xu_derat_eplc3_elpid => xu_derat_eplc3_elpid, + xu_derat_eplc3_epid => xu_derat_eplc3_epid, + xu_derat_epsc0_epr => xu_derat_epsc0_epr, + xu_derat_epsc0_eas => xu_derat_epsc0_eas, + xu_derat_epsc0_egs => xu_derat_epsc0_egs, + xu_derat_epsc0_elpid => xu_derat_epsc0_elpid, + xu_derat_epsc0_epid => xu_derat_epsc0_epid, + xu_derat_epsc1_epr => xu_derat_epsc1_epr, + xu_derat_epsc1_eas => xu_derat_epsc1_eas, + xu_derat_epsc1_egs => xu_derat_epsc1_egs, + xu_derat_epsc1_elpid => xu_derat_epsc1_elpid, + xu_derat_epsc1_epid => xu_derat_epsc1_epid, + xu_derat_epsc2_epr => xu_derat_epsc2_epr, + xu_derat_epsc2_eas => xu_derat_epsc2_eas, + xu_derat_epsc2_egs => xu_derat_epsc2_egs, + xu_derat_epsc2_elpid => xu_derat_epsc2_elpid, + xu_derat_epsc2_epid => xu_derat_epsc2_epid, + xu_derat_epsc3_epr => xu_derat_epsc3_epr, + xu_derat_epsc3_eas => xu_derat_epsc3_eas, + xu_derat_epsc3_egs => xu_derat_epsc3_egs, + xu_derat_epsc3_elpid => xu_derat_epsc3_elpid, + xu_derat_epsc3_epid => xu_derat_epsc3_epid, + + dc_cntrl_dbg_data => dc_cntrl_dbg_data, + + -- ACT signals + ex1_stg_act => ex1_stg_act, + ex2_stg_act => ex2_stg_act, + ex3_stg_act => ex3_stg_act, + ex4_stg_act => ex4_stg_act, + ex5_stg_act => ex5_stg_act, + binv1_stg_act => binv1_stg_act, + binv2_stg_act => binv2_stg_act, + binv3_stg_act => binv3_stg_act, + binv4_stg_act => binv4_stg_act, + binv5_stg_act => binv5_stg_act, + rel1_stg_act => rel1_stg_act, + rel2_stg_act => rel2_stg_act, + rel3_stg_act => rel3_stg_act, + + -- Pervasive + vdd => vdd, + gnd => gnd, + nclk => nclk, + sg_0 => sg_0, + func_sl_thold_0_b => func_sl_thold_0_b, + func_sl_force => func_sl_force, + func_slp_sl_thold_0_b => func_slp_sl_thold_0_b, + func_slp_sl_force => func_slp_sl_force, + func_nsl_thold_0_b => func_nsl_thold_0_b, + func_nsl_force => func_nsl_force, + func_slp_nsl_thold_0_b => func_slp_nsl_thold_0_b, + func_slp_nsl_force => func_slp_nsl_force, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc, + mpw1_dc_b => mpw1_dc_b, + mpw2_dc_b => mpw2_dc_b, + scan_in => siv(dccntrl_offset), + scan_out => sov(dccntrl_offset) +); + + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Flush Generation +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +lsufgen : entity work.xuq_lsu_fgen(xuq_lsu_fgen) +generic map(expand_type => expand_type, + real_data_add => real_data_add) +port map( + ex2_cache_acc => ex2_cache_acc, + ex2_ldst_fexcpt => ex2_ldst_fexcpt, + ex2_mv_reg_op => ex2_mv_reg_op, + ex2_axu_op => ex2_axu_op, + rf1_thrd_id => xu_lsu_rf1_thrd_id, + ex1_thrd_id => ex1_thrd_id_int, + ex2_thrd_id => ex2_thrd_id, + ex3_thrd_id => ex3_thrd_id, + ex4_thrd_id => ex4_thrd_id, + ex5_thrd_id => ex5_thrd_id, + ex2_optype2 => ex2_optype2, + ex2_optype4 => ex2_optype4, + ex2_optype8 => ex2_optype8, + ex2_optype16 => ex2_optype16, + ex2_optype32 => ex2_optype32, + ex2_p_addr_lwr => ex2_p_addr_lwr(57 to 63), + ex2_icswx_type => ex2_icswx_type, + ex2_store_instr => ex2_store_instr_int, + ex2_load_instr => ex2_load_instr, + ex2_dcbz_instr => ex2_dcbz_instr, + ex2_lock_instr => ex2_lock_instr, + ex2_ldawx_instr => ex2_ldawx_instr_int, + ex2_lm_dep_hit => ex2_lm_dep_hit, + ex3_lsq_flush => ex3_lsq_flush, + derat_xu_ex3_noop_touch => derat_xu_ex3_noop_touch, + ex3_cClass_collision => ex3_cClass_collision, + ex2_lockwatchSet_rel_coll => ex2_lockwatchSet_rel_coll, + ex3_wclr_all_flush => ex3_wclr_all_flush, + ex3_wimge_w_bit => ex3_wimge_w_bit, + ex3_wimge_i_bit => ex3_wimge_i_bit, + ex3_targ_match_b1 => ex3_targ_match_b1, + ex2_targ_match_b2 => ex2_targ_match_b2, + xu_lsu_spr_xucr0_aflsta => xu_lsu_spr_xucr0_aflsta, + xu_lsu_spr_xucr0_flsta => xu_lsu_spr_xucr0_flsta, + xu_lsu_spr_xucr0_l2siw => xu_lsu_spr_xucr0_l2siw, + ldq_rel_ci => ldq_rel_ci, + ldq_rel_axu_val => ldq_rel_axu_val, + xu_lsu_rf1_flush => xu_lsu_rf1_flush, + xu_lsu_ex1_flush => xu_lsu_ex1_flush, + xu_lsu_ex2_flush => xu_lsu_ex2_flush, + xu_lsu_ex3_flush => xu_lsu_ex3_flush, + xu_lsu_ex4_flush => xu_lsu_ex4_flush, + xu_lsu_ex5_flush => xu_lsu_ex5_flush, + rf1_stg_flush => stg_flush_rf1, + ex1_stg_flush => stg_flush_ex1, + ex2_stg_flush => stg_flush_ex2, + ex3_stg_flush => stg_flush_ex3, + ex4_stg_flush => stg_flush_ex4, + ex5_stg_flush => stg_flush_ex5, + lsu_xu_ex3_n_flush_req => lsu_xu_ex3_n_flush_req, + lsu_xu_ex3_dep_flush => lsu_xu_ex3_dep_flush, + ex3_excp_det => ex3_excp_det, + lsu_xu_perf_events => lsu_xu_perf_events(17 to 20), + lsu_xu_ex3_align => lsu_xu_ex3_align, + lsu_xu_ex3_dsi => lsu_xu_ex3_dsi, + lsu_xu_ex3_inval_align_2ucode => lsu_xu_ex3_inval_align_2ucode, + dc_fgen_dbg_data => dc_fgen_dbg_data, + vdd => vdd, + gnd => gnd, + nclk => nclk, + sg_0 => sg_0, + func_sl_thold_0_b => func_sl_thold_0_b, + func_sl_force => func_sl_force, + func_nsl_thold_0_b => func_nsl_thold_0_b, + func_nsl_force => func_nsl_force, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc, + mpw1_dc_b => mpw1_dc_b, + mpw2_dc_b => mpw2_dc_b, + scan_in => siv(dcfgen_offset), + scan_out => sov(dcfgen_offset) +); + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Outputs +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +ex2_stg_flush <= stg_flush_ex2; +ex3_stg_flush <= stg_flush_ex3; +ex4_stg_flush <= stg_flush_ex4; +ex5_stg_flush <= stg_flush_ex5; + +ex2_store_instr <= ex2_store_instr_int; +ex2_ldawx_instr <= ex2_ldawx_instr_int; +ex1_thrd_id <= ex1_thrd_id_int; + +siv(0 to scan_right) <= sov(1 to scan_right) & scan_in; +scan_out <= sov(0); + +end xuq_lsu_dc; diff --git a/rel/src/vhdl/work/xuq_lsu_dc_arr.vhdl b/rel/src/vhdl/work/xuq_lsu_dc_arr.vhdl new file mode 100644 index 0000000..9361a5e --- /dev/null +++ b/rel/src/vhdl/work/xuq_lsu_dc_arr.vhdl @@ -0,0 +1,342 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XU LSU L1 Data Cache Array +-- + +library ibm, ieee, work, tri, support; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use tri.tri_latches_pkg.all; +use support.power_logic_pkg.all; + +-- ########################################################################################## +-- VHDL Contents +-- 1) L1 D-Cache Array +-- 2) Load Data Way Select Mux +-- 3) Reload/Store Data select +-- ########################################################################################## + +entity xuq_lsu_dc_arr is +generic(expand_type : integer := 2; -- 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) + dc_size : natural := 14); -- 2^14 = 16384 Bytes L1 D$ +port( + + -- Acts to latches + ex3_stg_act :in std_ulogic; + ex4_stg_act :in std_ulogic; + rel3_stg_act :in std_ulogic; + rel4_stg_act :in std_ulogic; + + -- XUOP Signals + ex3_p_addr :in std_ulogic_vector(64-(dc_size-3) to 58); -- EX3 L1 D$ Array Address + ex3_byte_en :in std_ulogic_vector(0 to 31); -- EX3 Store Byte Enables + ex4_256st_data :in std_ulogic_vector(0 to 255); -- EX4 Store Data that will be stored in L1 D$ Array + ex4_parity_gen :in std_ulogic_vector(0 to 31); -- EX4 Parity Bits for XU/AXU store data + ex4_load_hit :in std_ulogic; -- EX4 Instruction is a load hit + ex5_stg_flush :in std_ulogic; -- EX5 Stage Flush + + -- Parity Error Inject + inj_dcache_parity :in std_ulogic; -- Parity Error Inject + + -- Reload Signals + ldq_rel_data_val :in std_ulogic; + ldq_rel_addr :in std_ulogic_vector(64-(dc_size-3) to 58); -- Reload Array Address + + -- D$ Array Inputs + dcarr_rd_data :in std_ulogic_vector(0 to 287); -- D$ Array Read Data + + -- D$ Array Outputs + dcarr_bw :out std_ulogic_vector(0 to 287); -- D$ Array Bit Enables + dcarr_addr :out std_ulogic_vector(64-(dc_size-3) to 58); -- D$ Array Address + dcarr_wr_data :out std_ulogic_vector(0 to 287); -- D$ Array Write Data + dcarr_bw_dly :out std_ulogic_vector(0 to 31); + + -- Execution Pipe + ex5_ld_data :out std_ulogic_vector(0 to 255); -- EX5 Load Data Coming out of L1 D$ Array + ex5_ld_data_par :out std_ulogic_vector(0 to 31); -- EX5 Load Data Parity Bits + ex6_par_chk_val :out std_ulogic; -- EX6 Parity Error Check is Valid + + --pervasive + vdd :inout power_logic; + gnd :inout power_logic; + nclk :in clk_logic; + sg_0 :in std_ulogic; + func_sl_thold_0_b :in std_ulogic; + func_sl_force :in std_ulogic; + func_nsl_thold_0_b :in std_ulogic; + func_nsl_force :in std_ulogic; + d_mode_dc :in std_ulogic; + delay_lclkr_dc :in std_ulogic; + mpw1_dc_b :in std_ulogic; + mpw2_dc_b :in std_ulogic; + scan_in :in std_ulogic; + scan_out :out std_ulogic +); +-- synopsys translate_off +-- synopsys translate_on +end xuq_lsu_dc_arr; +---- +architecture xuq_lsu_dc_arr of xuq_lsu_dc_arr is + +---------------------------- +-- components +---------------------------- + +---------------------------- +-- constants +---------------------------- +constant ex6_par_err_val_offset :natural := 0; +constant ex5_load_op_hit_offset :natural := ex6_par_err_val_offset + 1; +constant arr_addr_offset :natural := ex5_load_op_hit_offset + 1; +constant arr_bw_offset :natural := arr_addr_offset + 58-(64-(dc_size-3))+1; +constant scan_right :natural := arr_bw_offset + 32 - 1; + +---------------------------- +-- signals +---------------------------- + +signal xuop_addr :std_ulogic_vector(64-(dc_size-3) to 58); +signal st_byte_en :std_ulogic_vector(0 to 31); +signal rel_addr :std_ulogic_vector(64-(dc_size-3) to 58); +signal arr_addr_d :std_ulogic_vector(64-(dc_size-3) to 58); +signal arr_addr_q :std_ulogic_vector(64-(dc_size-3) to 58); +signal arr_st_data :std_ulogic_vector(0 to 255); +signal arr_parity :std_ulogic_vector(0 to 31); +signal arr_wr_data :std_ulogic_vector(0 to 287); +signal arr_bw_d :std_ulogic_vector(0 to 31); +signal arr_bw_q :std_ulogic_vector(0 to 31); +signal arr_bw_dly_d :std_ulogic_vector(0 to 31); +signal arr_bw_dly_q :std_ulogic_vector(0 to 31); +signal arr_rd_data :std_ulogic_vector(0 to 287); +signal arr_ld_data :std_ulogic_vector(0 to 255); +signal ld_arr_parity :std_ulogic_vector(0 to 31); +signal rel_val_data :std_ulogic; +signal ex5_load_op_hit_d :std_ulogic; +signal ex5_load_op_hit_q :std_ulogic; +signal ex6_par_err_val_d :std_ulogic; +signal ex6_par_err_val_q :std_ulogic; +signal rel3_ex3_stg_act :std_ulogic; +signal rel4_ex4_stg_act :std_ulogic; +signal inj_dcache_parity_b :std_ulogic; +signal arr_rd_data64_b :std_ulogic; +signal stickBit64 :std_ulogic; + +signal tiup :std_ulogic; +signal siv :std_ulogic_vector(0 to scan_right); +signal sov :std_ulogic_vector(0 to scan_right); +begin + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Act Signals going to all Latches +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +rel3_ex3_stg_act <= rel3_stg_act or ex3_stg_act; +rel4_ex4_stg_act <= rel4_stg_act or ex4_stg_act; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Inputs +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +tiup <= '1'; + +xuop_addr <= ex3_p_addr; +st_byte_en <= ex3_byte_en; +arr_parity <= ex4_parity_gen; +rel_val_data <= ldq_rel_data_val; +rel_addr <= ldq_rel_addr; + +arr_rd_data <= dcarr_rd_data; +arr_st_data <= ex4_256st_data; +ex5_load_op_hit_d <= ex4_load_hit; +inj_dcache_parity_b <= not inj_dcache_parity; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Select between different Operations +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +with rel_val_data select + arr_addr_d <= xuop_addr when '0', + rel_addr when others; + +with rel_val_data select + arr_bw_d <= st_byte_en when '0', + x"FFFFFFFF" when others; + +arr_bw_dly_d <= arr_bw_q; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Array Data Fix Up +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +arr_wr_data <= arr_st_data(0 to 127) & arr_parity(0 to 15) & + arr_st_data(128 to 255) & arr_parity(16 to 31); + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Inject Data Cache Error +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +-- Sticking bit64 of the array when Data Cache Parity Error Inject is on +-- Bit64 will be stuck to 1 +-- Bit64 refers to bit2 of byte0 +arr_rd_data64_b <= not arr_rd_data(64); +stickBit64 <= not (arr_rd_data64_b and inj_dcache_parity_b); + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Array Data Select +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +arr_ld_data <= arr_rd_data(0 to 63) & stickBit64 & arr_rd_data(65 to 127) & arr_rd_data(144 to 271); + +-- Array Parity +ld_arr_parity <= arr_rd_data(128 to 143) & arr_rd_data(272 to 287); + +-- Parity Check is Valid +ex6_par_err_val_d <= ex5_load_op_hit_q and not ex5_stg_flush; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Outputs +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +bw_gen : for bi in 0 to 31 generate begin + dcarr_bw(bi+0) <= arr_bw_q(bi); + dcarr_bw(bi+32) <= arr_bw_q(bi); + dcarr_bw(bi+64) <= arr_bw_q(bi); + dcarr_bw(bi+96) <= arr_bw_q(bi); + dcarr_bw(bi+144) <= arr_bw_q(bi); + dcarr_bw(bi+176) <= arr_bw_q(bi); + dcarr_bw(bi+208) <= arr_bw_q(bi); + dcarr_bw(bi+240) <= arr_bw_q(bi); + -- Parity Bits + dcarr_bw(bi+128+(128*(bi/16))) <= arr_bw_q(bi); +end generate bw_gen; + +dcarr_addr <= arr_addr_q; +dcarr_wr_data <= arr_wr_data; +dcarr_bw_dly <= arr_bw_dly_q; + +ex5_ld_data <= arr_ld_data; +ex5_ld_data_par <= ld_arr_parity; +ex6_par_chk_val <= ex6_par_err_val_q; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Registers +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +ex6_par_err_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_par_err_val_offset), + scout => sov(ex6_par_err_val_offset), + din => ex6_par_err_val_d, + dout => ex6_par_err_val_q); + +ex5_load_op_hit_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_load_op_hit_offset), + scout => sov(ex5_load_op_hit_offset), + din => ex5_load_op_hit_d, + dout => ex5_load_op_hit_q); + +arr_addr_reg: tri_rlmreg_p + generic map (width => 58-(64-(dc_size-3))+1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_ex3_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(arr_addr_offset to arr_addr_offset + arr_addr_d'length-1), + scout => sov(arr_addr_offset to arr_addr_offset + arr_addr_d'length-1), + din => arr_addr_d, + dout => arr_addr_q); + +arr_bw_reg: tri_rlmreg_p + generic map (width => 32, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_ex3_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(arr_bw_offset to arr_bw_offset + arr_bw_d'length-1), + scout => sov(arr_bw_offset to arr_bw_offset + arr_bw_d'length-1), + din => arr_bw_d, + dout => arr_bw_q); + +arr_bw_dly_reg: tri_regk + generic map (width => 32, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel4_ex4_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => arr_bw_dly_d, + dout => arr_bw_dly_q); + +siv(0 to scan_right) <= sov(1 to scan_right) & scan_in; +scan_out <= sov(0); + +end xuq_lsu_dc_arr; diff --git a/rel/src/vhdl/work/xuq_lsu_dc_cntrl.vhdl b/rel/src/vhdl/work/xuq_lsu_dc_cntrl.vhdl new file mode 100644 index 0000000..8cb13ee --- /dev/null +++ b/rel/src/vhdl/work/xuq_lsu_dc_cntrl.vhdl @@ -0,0 +1,8687 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XU LSU L1 Data Cache Control +-- + +library ibm, ieee, work, tri, support; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use tri.tri_latches_pkg.all; +use support.power_logic_pkg.all; + +-- ########################################################################################## +-- VHDL Contents +-- 1) 1 32Byte input (suppose to reflect reading 8 ways of L1 D$, Selection taken place in EX2) +-- 2) 32 Byte Reload Bus +-- 4) 32 Byte Unaligned Rotator +-- 5) Little Endian Support for 2,4,8,16,32 Byte Operations +-- 6) Contains Fixed Point Unit (FXU) 8 Byte Load Path +-- 7) Contains Auxilary Unit (AXU) 32 Byte Load Path +-- 8) Contains Unalignment Error Check +-- ########################################################################################## + +entity xuq_lsu_dc_cntrl is +generic(expand_type : integer := 2; -- 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) + regmode : integer := 6; -- 5 = 32bit mode, 6 = 64bit mode + dc_size : natural := 14; -- 2^14 = 16384 Bytes L1 D$ + parBits : natural := 4; -- Number of Parity Bits + real_data_add : integer := 42); -- 42 bit real address +port( + + -- Execution Pipe Inputs + xu_lsu_rf0_act :in std_ulogic; + xu_lsu_rf1_cmd_act :in std_ulogic; + xu_lsu_rf1_axu_op_val :in std_ulogic; -- Operation is from the AXU + xu_lsu_rf1_axu_ldst_falign :in std_ulogic; -- AXU force alignment indicator + xu_lsu_rf1_axu_ldst_fexcpt :in std_ulogic; -- AXU force alignment exception on misaligned access + xu_lsu_rf1_cache_acc :in std_ulogic; -- Cache Access is Valid, Op that touches directory + xu_lsu_rf1_thrd_id :in std_ulogic_vector(0 to 3); -- Thread ID + xu_lsu_rf1_optype1 :in std_ulogic; -- 1 Byte Load/Store + xu_lsu_rf1_optype2 :in std_ulogic; -- 2 Byte Load/Store + xu_lsu_rf1_optype4 :in std_ulogic; -- 4 Byte Load/Store + xu_lsu_rf1_optype8 :in std_ulogic; -- 8 Byte Load/Store + xu_lsu_rf1_optype16 :in std_ulogic; -- 16 Byte Load/Store + xu_lsu_rf1_optype32 :in std_ulogic; -- 32 Byte Load/Store + xu_lsu_rf1_target_gpr :in std_ulogic_vector(0 to 8); -- Target GPR, needed for reloads + xu_lsu_rf1_mtspr_trace :in std_ulogic; -- Operation is a mtspr trace instruction + xu_lsu_rf1_load_instr :in std_ulogic; -- Operation is a Load instruction + xu_lsu_rf1_store_instr :in std_ulogic; -- Operation is a Store instruction + xu_lsu_rf1_dcbf_instr :in std_ulogic; -- Operation is a DCBF instruction + xu_lsu_rf1_sync_instr :in std_ulogic; -- Operation is a SYNC instruction + xu_lsu_rf1_l_fld :in std_ulogic_vector(0 to 1); -- DCBF/SYNC L Field + xu_lsu_rf1_dcbi_instr :in std_ulogic; -- Operation is a DCBI instruction + xu_lsu_rf1_dcbz_instr :in std_ulogic; -- Operation is a DCBZ instruction + xu_lsu_rf1_dcbt_instr :in std_ulogic; -- Operation is a DCBT instruction + xu_lsu_rf1_dcbtst_instr :in std_ulogic; -- Operation is a DCBTST instruction + xu_lsu_rf1_th_fld :in std_ulogic_vector(0 to 4); -- TH/CT Field for Cache Management instructions + xu_lsu_rf1_dcbtls_instr :in std_ulogic; + xu_lsu_rf1_dcbtstls_instr :in std_ulogic; + xu_lsu_rf1_dcblc_instr :in std_ulogic; + xu_lsu_rf1_dcbst_instr :in std_ulogic; + xu_lsu_rf1_icbi_instr :in std_ulogic; + xu_lsu_rf1_icblc_instr :in std_ulogic; + xu_lsu_rf1_icbt_instr :in std_ulogic; + xu_lsu_rf1_icbtls_instr :in std_ulogic; + xu_lsu_rf1_icswx_instr :in std_ulogic; + xu_lsu_rf1_icswx_dot_instr :in std_ulogic; + xu_lsu_rf1_icswx_epid :in std_ulogic; + xu_lsu_rf1_tlbsync_instr :in std_ulogic; + xu_lsu_rf1_ldawx_instr :in std_ulogic; + xu_lsu_rf1_wclr_instr :in std_ulogic; + xu_lsu_rf1_wchk_instr :in std_ulogic; + xu_lsu_rf1_lock_instr :in std_ulogic; -- Operation is a LOCK instruction + xu_lsu_rf1_mutex_hint :in std_ulogic; -- Mutex Hint For larx instructions + xu_lsu_rf1_mbar_instr :in std_ulogic; -- Operation is an MBAR instruction + xu_lsu_rf1_is_msgsnd :in std_ulogic; + xu_lsu_rf1_dci_instr :in std_ulogic; -- DCI instruction is valid + xu_lsu_rf1_ici_instr :in std_ulogic; -- ICI instruction is valid + xu_lsu_rf1_algebraic :in std_ulogic; -- Operation is an Algebraic Load instruction + xu_lsu_rf1_byte_rev :in std_ulogic; -- Operation is a Byte Reversal Load/Store instruction + xu_lsu_rf1_src_gpr :in std_ulogic; -- Source is the GPR's for mfloat and mDCR ops + xu_lsu_rf1_src_axu :in std_ulogic; -- Source is the AXU's for mfloat and mDCR ops + xu_lsu_rf1_src_dp :in std_ulogic; -- Source is the BOX's for mfloat and mDCR ops + xu_lsu_rf1_targ_gpr :in std_ulogic; -- Target is the GPR's for mfloat and mDCR ops + xu_lsu_rf1_targ_axu :in std_ulogic; -- Target is the AXU's for mfloat and mDCR ops + xu_lsu_rf1_targ_dp :in std_ulogic; -- Target is the BOX's for mfloat and mDCR ops + xu_lsu_ex4_val :in std_ulogic_vector(0 to 3); -- There is a valid Instruction in EX4 + + -- Dependency Checking on loadmisses + xu_lsu_rf1_src0_vld :in std_ulogic; -- Source0 is Valid + xu_lsu_rf1_src0_reg :in std_ulogic_vector(0 to 7); -- Source0 Register + xu_lsu_rf1_src1_vld :in std_ulogic; -- Source1 is Valid + xu_lsu_rf1_src1_reg :in std_ulogic_vector(0 to 7); -- Source1 Register + xu_lsu_rf1_targ_vld :in std_ulogic; -- Target is Valid + xu_lsu_rf1_targ_reg :in std_ulogic_vector(0 to 7); -- Target Register + + -- Back-Invalidate + is2_l2_inv_val :in std_ulogic; -- L2 Back-Invalidate is Valid + + ex3_wayA_tag :in std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex3_wayB_tag :in std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex3_wayC_tag :in std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex3_wayD_tag :in std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex3_wayE_tag :in std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex3_wayF_tag :in std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex3_wayG_tag :in std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex3_wayH_tag :in std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex3_way_tag_par_a :in std_ulogic_vector(0 to parBits-1); + ex3_way_tag_par_b :in std_ulogic_vector(0 to parBits-1); + ex3_way_tag_par_c :in std_ulogic_vector(0 to parBits-1); + ex3_way_tag_par_d :in std_ulogic_vector(0 to parBits-1); + ex3_way_tag_par_e :in std_ulogic_vector(0 to parBits-1); + ex3_way_tag_par_f :in std_ulogic_vector(0 to parBits-1); + ex3_way_tag_par_g :in std_ulogic_vector(0 to parBits-1); + ex3_way_tag_par_h :in std_ulogic_vector(0 to parBits-1); + ex4_way_a_dir :in std_ulogic_vector(0 to 5); + ex4_way_b_dir :in std_ulogic_vector(0 to 5); + ex4_way_c_dir :in std_ulogic_vector(0 to 5); + ex4_way_d_dir :in std_ulogic_vector(0 to 5); + ex4_way_e_dir :in std_ulogic_vector(0 to 5); + ex4_way_f_dir :in std_ulogic_vector(0 to 5); + ex4_way_g_dir :in std_ulogic_vector(0 to 5); + ex4_way_h_dir :in std_ulogic_vector(0 to 5); + ex4_dir_lru :in std_ulogic_vector(0 to 6); + + ex2_p_addr_lwr :in std_ulogic_vector(52 to 63); + ex3_wimge_i_bit :in std_ulogic; -- Memory Attribute Bits from ERAT + ex3_wimge_e_bit :in std_ulogic; -- Memory Attribute Bits from ERAT + + ex3_p_addr :in std_ulogic_vector(64-real_data_add to 51); + ex3_ld_queue_full :in std_ulogic; -- LSQ load queue full + ex3_stq_flush :in std_ulogic; -- LSQ store queue full + ex3_ig_flush :in std_ulogic; -- LSQ I=G=1 flush + ex3_hit :in std_ulogic; -- EX3 Load/Store Hit + ex4_miss :in std_ulogic; -- EX4 Load/Store Miss + ex4_snd_ld_l2 :in std_ulogic; -- Request is being sent to the L2 + ex3_excp_det :in std_ulogic; -- Any Exception was detected + + -- Stage Flush + rf1_stg_flush :in std_ulogic; -- RF1 Stage Flush + ex1_stg_flush :in std_ulogic; -- EX1 Stage Flush + ex2_stg_flush :in std_ulogic; -- EX2 Stage Flush + ex3_stg_flush :in std_ulogic; -- EX3 Stage Flush + ex4_stg_flush :in std_ulogic; -- EX4 Stage Flush + ex5_stg_flush :in std_ulogic; -- EX5 Stage Flush + + rel_dcarr_val_upd :in std_ulogic; -- Reload Data Array Update Valid + + -- Data Cache Config + xu_lsu_mtspr_trace_en :in std_ulogic_vector(0 to 3); + spr_xucr0_clkg_ctl_b1 :in std_ulogic; -- Clock Gating Override + xu_lsu_spr_xucr0_wlk :in std_ulogic; -- Data Cache Way Locking Enable + xu_lsu_spr_ccr2_dfrat :in std_ulogic; -- Force Real Address Translation + xu_lsu_spr_xucr0_flh2l2 :in std_ulogic; -- Force L1 load hits to L2 + xu_lsu_spr_xucr0_cls :in std_ulogic; -- Cacheline Size = 1 => 128Byte size, 0 => 64Byte size + xu_lsu_spr_xucr0_dcdis :in std_ulogic; -- Data Cache Disable + xu_lsu_spr_msr_cm :in std_ulogic_vector(0 to 3); -- 64bit mode enable + + -- MSR[GS,PR] bits, indicates which state we are running in + xu_lsu_msr_gs :in std_ulogic_vector(0 to 3); -- Guest State + xu_lsu_msr_pr :in std_ulogic_vector(0 to 3); -- Problem State + + an_ac_flh2l2_gate :in std_ulogic; -- Gate L1 Hit forwarding SPR config bit + + -- Slow SPR Bus + xu_lsu_slowspr_val :in std_ulogic; + xu_lsu_slowspr_rw :in std_ulogic; + xu_lsu_slowspr_etid :in std_ulogic_vector(0 to 1); + xu_lsu_slowspr_addr :in std_ulogic_vector(0 to 9); + xu_lsu_slowspr_data :in std_ulogic_vector(64-(2**REGMODE) to 63); + xu_lsu_slowspr_done :in std_ulogic; + slowspr_val_out :out std_ulogic; + slowspr_rw_out :out std_ulogic; + slowspr_etid_out :out std_ulogic_vector(0 to 1); + slowspr_addr_out :out std_ulogic_vector(0 to 9); + slowspr_data_out :out std_ulogic_vector(64-(2**REGMODE) to 63); + slowspr_done_out :out std_ulogic; + + ldq_rel_data_val_early :in std_ulogic; -- Reload Interface ACT + ldq_rel_stg24_val :in std_ulogic; -- Reload Stages 2 and 4 are valid + ldq_rel_axu_val :in std_ulogic; -- Reload is for a Vector Register + ldq_rel_thrd_id :in std_ulogic_vector(0 to 3); -- Thread ID of the reload + ldq_rel_ta_gpr :in std_ulogic_vector(0 to 8); + ldq_rel_upd_gpr :in std_ulogic; -- Reload data should be written to GPR (DCB ops don't write to GPRs) + + -- Dependency Checking on loadmisses + ex1_src0_vld :out std_ulogic; -- Source0 is Valid + ex1_src0_reg :out std_ulogic_vector(0 to 7); -- Source0 Register + ex1_src1_vld :out std_ulogic; -- Source1 is Valid + ex1_src1_reg :out std_ulogic_vector(0 to 7); -- Source1 Register + ex1_targ_vld :out std_ulogic; -- Target is Valid + ex1_targ_reg :out std_ulogic_vector(0 to 7); -- Target Register + ex1_check_watch :out std_ulogic_vector(0 to 3); -- Instructions that need to wait for ldawx to complete in loadmiss queue + + -- Execution Pipe Outputs + ex1_lsu_64bit_agen :out std_ulogic; + ex1_frc_align2 :out std_ulogic; + ex1_frc_align4 :out std_ulogic; + ex1_frc_align8 :out std_ulogic; + ex1_frc_align16 :out std_ulogic; + ex1_frc_align32 :out std_ulogic; + ex1_optype1 :out std_ulogic; + ex1_optype2 :out std_ulogic; + ex1_optype4 :out std_ulogic; + ex1_optype8 :out std_ulogic; + ex1_optype16 :out std_ulogic; + ex1_optype32 :out std_ulogic; + ex1_saxu_instr :out std_ulogic; + ex1_sdp_instr :out std_ulogic; + ex1_stgpr_instr :out std_ulogic; + ex1_store_instr :out std_ulogic; + ex1_axu_op_val :out std_ulogic; + + ex2_optype2 :out std_ulogic; + ex2_optype4 :out std_ulogic; + ex2_optype8 :out std_ulogic; + ex2_optype16 :out std_ulogic; + ex2_optype32 :out std_ulogic; + ex2_icswx_type :out std_ulogic; + ex2_store_instr :out std_ulogic; + ex1_dir_acc_val :out std_ulogic; + ex2_cache_acc :out std_ulogic; + ex3_cache_acc :out std_ulogic; + ex2_ldst_fexcpt :out std_ulogic; + ex2_axu_op :out std_ulogic; + ex2_mv_reg_op :out std_ulogic; + ex1_thrd_id :out std_ulogic_vector(0 to 3); + ex2_thrd_id :out std_ulogic_vector(0 to 3); + ex3_thrd_id :out std_ulogic_vector(0 to 3); + ex4_thrd_id :out std_ulogic_vector(0 to 3); + ex5_thrd_id :out std_ulogic_vector(0 to 3); + ex3_req_thrd_id :out std_ulogic_vector(0 to 3); + ex3_targ_match_b1 :out std_ulogic; + ex2_targ_match_b2 :out std_ulogic; + ex3_target_gpr :out std_ulogic_vector(0 to 8); + ex2_load_instr :out std_ulogic; + ex3_dcbt_instr :out std_ulogic; + ex3_dcbtst_instr :out std_ulogic; + ex3_th_fld_l2 :out std_ulogic; + ex3_dcbst_instr :out std_ulogic; + ex3_dcbf_instr :out std_ulogic; + ex3_sync_instr :out std_ulogic; + ex3_mtspr_trace :out std_ulogic; + ex3_byte_en :out std_ulogic_vector(0 to 31); + ex2_l_fld :out std_ulogic_vector(0 to 1); + ex3_l_fld :out std_ulogic_vector(0 to 1); + ex3_dcbi_instr :out std_ulogic; + ex2_dcbz_instr :out std_ulogic; + ex3_dcbz_instr :out std_ulogic; + ex3_icbi_instr :out std_ulogic; + ex3_icswx_instr :out std_ulogic; + ex3_icswx_dot :out std_ulogic; + ex3_icswx_epid :out std_ulogic; + ex3_mbar_instr :out std_ulogic; + ex3_msgsnd_instr :out std_ulogic; + ex3_dci_instr :out std_ulogic; + ex3_ici_instr :out std_ulogic; + ex2_lock_instr :out std_ulogic; + ex3_load_instr :out std_ulogic; + ex3_store_instr :out std_ulogic; + ex3_axu_op_val :out std_ulogic; + ex3_algebraic :out std_ulogic; + ex3_dcbtls_instr :out std_ulogic; + ex3_dcbtstls_instr :out std_ulogic; + ex3_dcblc_instr :out std_ulogic; + ex3_icblc_instr :out std_ulogic; + ex3_icbt_instr :out std_ulogic; + ex3_icbtls_instr :out std_ulogic; + ex3_tlbsync_instr :out std_ulogic; + ex3_local_dcbf :out std_ulogic; + ex4_drop_rel :out std_ulogic; + ex3_load_l1hit :out std_ulogic; + ex3_rotate_sel :out std_ulogic_vector(0 to 4); + ex2_ldawx_instr :out std_ulogic; + ex2_wclr_instr :out std_ulogic; + ex2_wchk_val :out std_ulogic; + ex3_watch_en :out std_ulogic; + ex3_data_swap :out std_ulogic; + ex3_load_val :out std_ulogic; + ex3_blkable_touch :out std_ulogic; + ex3_l2_request :out std_ulogic; + ex3_ldq_potential_flush :out std_ulogic; + ex7_targ_match :out std_ulogic; -- EX6vsEX5 matched + ex8_targ_match :out std_ulogic; -- EX7vsEX6 or EX7vsEX5 matched + ex4_ld_entry :out std_ulogic_vector(0 to 67); + + ex2_no_lru_upd :out std_ulogic; + ex2_is_inval_op :out std_ulogic; + ex2_lock_set :out std_ulogic; + ex2_lock_clr :out std_ulogic; + ex2_ddir_acc_instr :out std_ulogic; + + ex3_lsq_flush :out std_ulogic; + ex3_p_addr_lwr :out std_ulogic_vector(58 to 63); + ex3_lock_en :out std_ulogic; + ex3_cache_en :out std_ulogic; + ex3_cache_inh :out std_ulogic; + ex3_l_s_q_val :out std_ulogic; + ex3_drop_ld_req :out std_ulogic; + ex3_drop_touch :out std_ulogic; + ex3_stx_instr :out std_ulogic; + ex3_larx_instr :out std_ulogic; + ex3_mutex_hint :out std_ulogic; + ex3_opsize :out std_ulogic_vector(0 to 5); + ex4_store_hit :out std_ulogic; + ex4_load_op_hit :out std_ulogic; + ex5_load_op_hit :out std_ulogic; + ex4_axu_op_val :out std_ulogic; + + -- SPR's + spr_xucr2_rmt :out std_ulogic_vector(0 to 31); + spr_xucr0_wlck :out std_ulogic; + spr_dvc1_act :out std_ulogic; + spr_dvc2_act :out std_ulogic; + spr_dvc1_dbg :out std_ulogic_vector(64-(2**regmode) to 63); + spr_dvc2_dbg :out std_ulogic_vector(64-(2**regmode) to 63); + + -- SPR status + lsu_xu_spr_xucr0_cul :out std_ulogic; -- Cache Lock unable to lock + spr_xucr0_cls :out std_ulogic; -- Cacheline Size + agen_xucr0_cls :out std_ulogic; + + -- Directory Read interface + dir_arr_rd_is2_val :out std_ulogic; + dir_arr_rd_congr_cl :out std_ulogic_vector(0 to 4); + + -- Back-invalidate + rf1_l2_inv_val :out std_ulogic; + ex1_agen_binv_val :out std_ulogic; + ex1_l2_inv_val :out std_ulogic; + + -- Update Data Array Valid + rel_upd_dcarr_val :out std_ulogic; + + lsu_xu_ex4_cr_upd :out std_ulogic; + lsu_xu_ex5_wren :out std_ulogic; + lsu_xu_rel_wren :out std_ulogic; + lsu_xu_rel_ta_gpr :out std_ulogic_vector(0 to 7); + lsu_xu_perf_events :out std_ulogic_vector(0 to 16); + lsu_xu_need_hole :out std_ulogic; + + xu_fu_ex5_reload_val :out std_ulogic; + xu_fu_ex5_load_val :out std_ulogic_vector(0 to 3); + xu_fu_ex5_load_tag :out std_ulogic_vector(0 to 8); + + -- ICBI Interface + xu_iu_ex6_icbi_val :out std_ulogic_vector(0 to 3); + xu_iu_ex6_icbi_addr :out std_ulogic_vector(64-real_data_add to 57); + + -- DERAT SlowSPR Regs + xu_derat_epsc_wr :out std_ulogic_vector(0 to 3); + xu_derat_eplc_wr :out std_ulogic_vector(0 to 3); + xu_derat_eplc0_epr :out std_ulogic; + xu_derat_eplc0_eas :out std_ulogic; + xu_derat_eplc0_egs :out std_ulogic; + xu_derat_eplc0_elpid :out std_ulogic_vector(40 to 47); + xu_derat_eplc0_epid :out std_ulogic_vector(50 to 63); + xu_derat_eplc1_epr :out std_ulogic; + xu_derat_eplc1_eas :out std_ulogic; + xu_derat_eplc1_egs :out std_ulogic; + xu_derat_eplc1_elpid :out std_ulogic_vector(40 to 47); + xu_derat_eplc1_epid :out std_ulogic_vector(50 to 63); + xu_derat_eplc2_epr :out std_ulogic; + xu_derat_eplc2_eas :out std_ulogic; + xu_derat_eplc2_egs :out std_ulogic; + xu_derat_eplc2_elpid :out std_ulogic_vector(40 to 47); + xu_derat_eplc2_epid :out std_ulogic_vector(50 to 63); + xu_derat_eplc3_epr :out std_ulogic; + xu_derat_eplc3_eas :out std_ulogic; + xu_derat_eplc3_egs :out std_ulogic; + xu_derat_eplc3_elpid :out std_ulogic_vector(40 to 47); + xu_derat_eplc3_epid :out std_ulogic_vector(50 to 63); + xu_derat_epsc0_epr :out std_ulogic; + xu_derat_epsc0_eas :out std_ulogic; + xu_derat_epsc0_egs :out std_ulogic; + xu_derat_epsc0_elpid :out std_ulogic_vector(40 to 47); + xu_derat_epsc0_epid :out std_ulogic_vector(50 to 63); + xu_derat_epsc1_epr :out std_ulogic; + xu_derat_epsc1_eas :out std_ulogic; + xu_derat_epsc1_egs :out std_ulogic; + xu_derat_epsc1_elpid :out std_ulogic_vector(40 to 47); + xu_derat_epsc1_epid :out std_ulogic_vector(50 to 63); + xu_derat_epsc2_epr :out std_ulogic; + xu_derat_epsc2_eas :out std_ulogic; + xu_derat_epsc2_egs :out std_ulogic; + xu_derat_epsc2_elpid :out std_ulogic_vector(40 to 47); + xu_derat_epsc2_epid :out std_ulogic_vector(50 to 63); + xu_derat_epsc3_epr :out std_ulogic; + xu_derat_epsc3_eas :out std_ulogic; + xu_derat_epsc3_egs :out std_ulogic; + xu_derat_epsc3_elpid :out std_ulogic_vector(40 to 47); + xu_derat_epsc3_epid :out std_ulogic_vector(50 to 63); + + -- Debug Data + dc_cntrl_dbg_data :out std_ulogic_vector(0 to 66); + + -- ACT signals + ex1_stg_act :out std_ulogic; + ex2_stg_act :out std_ulogic; + ex3_stg_act :out std_ulogic; + ex4_stg_act :out std_ulogic; + ex5_stg_act :out std_ulogic; + binv1_stg_act :out std_ulogic; + binv2_stg_act :out std_ulogic; + binv3_stg_act :out std_ulogic; + binv4_stg_act :out std_ulogic; + binv5_stg_act :out std_ulogic; + rel1_stg_act :out std_ulogic; + rel2_stg_act :out std_ulogic; + rel3_stg_act :out std_ulogic; + + -- Pervasive + vdd :inout power_logic; + gnd :inout power_logic; + nclk :in clk_logic; + sg_0 :in std_ulogic; + func_sl_thold_0_b :in std_ulogic; + func_sl_force :in std_ulogic; + func_slp_sl_thold_0_b :in std_ulogic; + func_slp_sl_force :in std_ulogic; + func_nsl_thold_0_b :in std_ulogic; + func_nsl_force :in std_ulogic; + func_slp_nsl_thold_0_b :in std_ulogic; + func_slp_nsl_force :in std_ulogic; + d_mode_dc :in std_ulogic; + delay_lclkr_dc :in std_ulogic; + mpw1_dc_b :in std_ulogic; + mpw2_dc_b :in std_ulogic; + scan_in :in std_ulogic; + scan_out :out std_ulogic +); +-- synopsys translate_off +-- synopsys translate_on +end xuq_lsu_dc_cntrl; +---- +architecture xuq_lsu_dc_cntrl of xuq_lsu_dc_cntrl is + +---------------------------- +-- components +---------------------------- + +---------------------------- +-- constants +---------------------------- +constant tagSize :natural := (63-(dc_size-3))-(64-real_data_add)+1; +constant rot_max_size :std_ulogic_vector(0 to 5) := "100000"; + +constant ex1_optype1_offset :natural := 0; +constant ex1_optype2_offset :natural := ex1_optype1_offset + 1; +constant ex1_optype4_offset :natural := ex1_optype2_offset + 1; +constant ex1_optype8_offset :natural := ex1_optype4_offset + 1; +constant ex1_optype16_offset :natural := ex1_optype8_offset + 1; +constant ex1_optype32_offset :natural := ex1_optype16_offset + 1; +constant ex1_dir_acc_val_offset :natural := ex1_optype32_offset + 1; +constant cache_acc_ex1_offset :natural := ex1_dir_acc_val_offset + 1; +constant cache_acc_ex2_offset :natural := cache_acc_ex1_offset + 1; +constant cache_acc_ex3_offset :natural := cache_acc_ex2_offset + 1; +constant cache_acc_ex4_offset :natural := cache_acc_ex3_offset + 1; +constant cache_acc_ex5_offset :natural := cache_acc_ex4_offset + 1; +constant ex2_cacc_offset :natural := cache_acc_ex5_offset + 1; +constant ex3_cacc_offset :natural := ex2_cacc_offset + 1; +constant ex1_thrd_id_offset :natural := ex3_cacc_offset + 1; +constant ex3_thrd_id_offset :natural := ex1_thrd_id_offset + 4; +constant ex5_thrd_id_offset :natural := ex3_thrd_id_offset + 4; +constant ex1_target_gpr_offset :natural := ex5_thrd_id_offset + 4; +constant ex3_target_gpr_offset :natural := ex1_target_gpr_offset + 9; +constant ex1_dcbt_instr_offset :natural := ex3_target_gpr_offset + 9; +constant ex3_dcbt_instr_offset :natural := ex1_dcbt_instr_offset + 1; +constant ex1_dcbtst_instr_offset :natural := ex3_dcbt_instr_offset + 1; +constant ex3_dcbtst_instr_offset :natural := ex1_dcbtst_instr_offset + 1; +constant ex1_dcbst_instr_offset :natural := ex3_dcbtst_instr_offset + 1; +constant ex3_dcbst_instr_offset :natural := ex1_dcbst_instr_offset + 1; +constant ex1_dcbf_instr_offset :natural := ex3_dcbst_instr_offset + 1; +constant ex3_dcbf_instr_offset :natural := ex1_dcbf_instr_offset + 1; +constant ex1_sync_instr_offset :natural := ex3_dcbf_instr_offset + 1; +constant ex2_sync_instr_offset :natural := ex1_sync_instr_offset + 1; +constant ex3_sync_instr_offset :natural := ex2_sync_instr_offset + 1; +constant ex1_l_fld_offset :natural := ex3_sync_instr_offset + 1; +constant ex3_l_fld_offset :natural := ex1_l_fld_offset + 2; +constant ex1_dcbi_instr_offset :natural := ex3_l_fld_offset + 2; +constant ex3_dcbi_instr_offset :natural := ex1_dcbi_instr_offset + 1; +constant ex1_dcbz_instr_offset :natural := ex3_dcbi_instr_offset + 1; +constant ex3_dcbz_instr_offset :natural := ex1_dcbz_instr_offset + 1; +constant ex1_icbi_instr_offset :natural := ex3_dcbz_instr_offset + 1; +constant ex3_icbi_instr_offset :natural := ex1_icbi_instr_offset + 1; +constant ex5_icbi_instr_offset :natural := ex3_icbi_instr_offset + 1; +constant ex1_mbar_instr_offset :natural := ex5_icbi_instr_offset + 1; +constant ex2_mbar_instr_offset :natural := ex1_mbar_instr_offset + 1; +constant ex3_mbar_instr_offset :natural := ex2_mbar_instr_offset + 1; +constant ex1_algebraic_offset :natural := ex3_mbar_instr_offset + 1; +constant ex3_algebraic_offset :natural := ex1_algebraic_offset + 1; +constant ex1_byte_rev_offset :natural := ex3_algebraic_offset + 1; +constant ex3_byte_rev_offset :natural := ex1_byte_rev_offset + 1; +constant ex1_lock_instr_offset :natural := ex3_byte_rev_offset + 1; +constant ex3_lock_instr_offset :natural := ex1_lock_instr_offset + 1; +constant ex5_lock_instr_offset :natural := ex3_lock_instr_offset + 1; +constant ex1_mutex_hint_offset :natural := ex5_lock_instr_offset + 1; +constant ex3_mutex_hint_offset :natural := ex1_mutex_hint_offset + 1; +constant ex1_load_instr_offset :natural := ex3_mutex_hint_offset + 1; +constant ex3_load_instr_offset :natural := ex1_load_instr_offset + 1; +constant ex5_load_instr_offset :natural := ex3_load_instr_offset + 1; +constant ex1_store_instr_offset :natural := ex5_load_instr_offset + 1; +constant ex3_store_instr_offset :natural := ex1_store_instr_offset + 1; +constant ex3_l2_op_offset :natural := ex3_store_instr_offset + 1; +constant ex5_cache_inh_offset :natural := ex3_l2_op_offset + 1; +constant ex3_opsize_offset :natural := ex5_cache_inh_offset + 1; +constant ex1_axu_op_val_offset :natural := ex3_opsize_offset + 6; +constant ex3_axu_op_val_offset :natural := ex1_axu_op_val_offset + 1; +constant ex5_axu_op_val_offset :natural := ex3_axu_op_val_offset + 1; +constant rel_upd_gpr_offset :natural := ex5_axu_op_val_offset + 1; +constant rel_axu_op_val_offset :natural := rel_upd_gpr_offset + 1; +constant rel_thrd_id_offset :natural := rel_axu_op_val_offset + 1; +constant rel_ta_gpr_offset :natural := rel_thrd_id_offset + 4; +constant ex4_load_commit_offset :natural := rel_ta_gpr_offset + 9; +constant ex5_load_hit_offset :natural := ex4_load_commit_offset + 1; +constant ex5_axu_rel_val_stg1_offset :natural := ex5_load_hit_offset + 1; +constant ex5_axu_rel_val_stg2_offset :natural := ex5_axu_rel_val_stg1_offset + 1; +constant ex5_axu_wren_offset :natural := ex5_axu_rel_val_stg2_offset + 1; +constant ex5_axu_ta_gpr_offset :natural := ex5_axu_wren_offset + 4; +constant rel_xu_ta_gpr_offset :natural := ex5_axu_ta_gpr_offset + 9; +constant lsu_slowspr_val_offset :natural := rel_xu_ta_gpr_offset + 8; +constant lsu_slowspr_rw_offset :natural := lsu_slowspr_val_offset + 1; +constant lsu_slowspr_etid_offset :natural := lsu_slowspr_rw_offset + 1; +constant lsu_slowspr_addr_offset :natural := lsu_slowspr_etid_offset + 2; +constant lsu_slowspr_data_offset :natural := lsu_slowspr_addr_offset + 10; +constant lsu_slowspr_done_offset :natural := lsu_slowspr_data_offset + 2**REGMODE; +constant mm_slowspr_val_offset :natural := lsu_slowspr_done_offset + 1; +constant mm_slowspr_rw_offset :natural := mm_slowspr_val_offset + 1; +constant mm_slowspr_etid_offset :natural := mm_slowspr_rw_offset + 1; +constant mm_slowspr_addr_offset :natural := mm_slowspr_etid_offset + 2; +constant mm_slowspr_data_offset :natural := mm_slowspr_addr_offset + 10; +constant mm_slowspr_done_offset :natural := mm_slowspr_data_offset + 2**REGMODE; +constant ex1_th_fld_c_offset :natural := mm_slowspr_done_offset + 1; +constant ex3_th_fld_c_offset :natural := ex1_th_fld_c_offset + 1; +constant ex1_th_fld_l2_offset :natural := ex3_th_fld_c_offset + 1; +constant ex3_th_fld_l2_offset :natural := ex1_th_fld_l2_offset + 1; +constant ex1_dcbtls_instr_offset :natural := ex3_th_fld_l2_offset + 1; +constant ex3_dcbtls_instr_offset :natural := ex1_dcbtls_instr_offset + 1; +constant ex3_l2_request_offset :natural := ex3_dcbtls_instr_offset + 1; +constant ex1_dcbtstls_instr_offset :natural := ex3_l2_request_offset + 1; +constant ex3_dcbtstls_instr_offset :natural := ex1_dcbtstls_instr_offset + 1; +constant ex1_dcblc_instr_offset :natural := ex3_dcbtstls_instr_offset + 1; +constant ex3_dcblc_instr_offset :natural := ex1_dcblc_instr_offset + 1; +constant ex1_icblc_l2_instr_offset :natural := ex3_dcblc_instr_offset + 1; +constant ex3_icblc_l2_instr_offset :natural := ex1_icblc_l2_instr_offset + 1; +constant ex1_icbt_l2_instr_offset :natural := ex3_icblc_l2_instr_offset + 1; +constant ex3_icbt_l2_instr_offset :natural := ex1_icbt_l2_instr_offset + 1; +constant ex1_icbtls_l2_instr_offset :natural := ex3_icbt_l2_instr_offset + 1; +constant ex3_icbtls_l2_instr_offset :natural := ex1_icbtls_l2_instr_offset + 1; +constant ex1_tlbsync_instr_offset :natural := ex3_icbtls_l2_instr_offset + 1; +constant ex2_tlbsync_instr_offset :natural := ex1_tlbsync_instr_offset + 1; +constant ex3_tlbsync_instr_offset :natural := ex2_tlbsync_instr_offset + 1; +constant ex1_src0_vld_offset :natural := ex3_tlbsync_instr_offset + 1; +constant ex1_src0_reg_offset :natural := ex1_src0_vld_offset + 1; +constant ex1_src1_vld_offset :natural := ex1_src0_reg_offset + 8; +constant ex1_src1_reg_offset :natural := ex1_src1_vld_offset + 1; +constant ex1_targ_vld_offset :natural := ex1_src1_reg_offset + 8; +constant ex1_targ_reg_offset :natural := ex1_targ_vld_offset + 1; +constant ex5_instr_val_offset :natural := ex1_targ_reg_offset + 8; +constant ex2_targ_match_b1_offset :natural := ex5_instr_val_offset + 1; +constant ex3_targ_match_b1_offset :natural := ex2_targ_match_b1_offset + 1; +constant ex4_targ_match_b1_offset :natural := ex3_targ_match_b1_offset + 1; +constant ex5_targ_match_b1_offset :natural := ex4_targ_match_b1_offset + 1; +constant ex6_targ_match_b1_offset :natural := ex5_targ_match_b1_offset + 1; +constant ex2_targ_match_b2_offset :natural := ex6_targ_match_b1_offset + 1; +constant ex3_targ_match_b2_offset :natural := ex2_targ_match_b2_offset + 1; +constant ex4_targ_match_b2_offset :natural := ex3_targ_match_b2_offset + 1; +constant ex5_targ_match_b2_offset :natural := ex4_targ_match_b2_offset + 1; +constant ex7_targ_match_offset :natural := ex5_targ_match_b2_offset + 1; +constant ex8_targ_match_offset :natural := ex7_targ_match_offset + 1; +constant ex1_ldst_falign_offset :natural := ex8_targ_match_offset + 1; +constant ex1_ldst_fexcpt_offset :natural := ex1_ldst_falign_offset + 1; +constant ex5_load_miss_offset :natural := ex1_ldst_fexcpt_offset + 1; +constant xucr2_reg_a_offset :natural := ex5_load_miss_offset + 1; +constant xucr2_reg_b_offset :natural := xucr2_reg_a_offset + 16; +constant dvc1_act_offset :natural := xucr2_reg_b_offset + 16; +constant dvc2_act_offset :natural := dvc1_act_offset + 1; +constant dvc1_reg_offset :natural := dvc2_act_offset + 1; +constant dvc2_reg_offset :natural := dvc1_reg_offset + 2**REGMODE; +constant xudbg0_reg_offset :natural := dvc2_reg_offset + 2**REGMODE; +constant xudbg0_done_reg_offset :natural := xudbg0_reg_offset + 8; +constant xudbg1_dir_reg_offset :natural := xudbg0_done_reg_offset + 1; +constant xudbg1_parity_reg_offset :natural := xudbg1_dir_reg_offset + 13; +constant xudbg2_reg_offset :natural := xudbg1_parity_reg_offset + parBits; +constant ex4_store_commit_offset :natural := xudbg2_reg_offset + 31; +constant ex1_sgpr_instr_offset :natural := ex4_store_commit_offset + 1; +constant ex1_saxu_instr_offset :natural := ex1_sgpr_instr_offset + 1; +constant ex1_sdp_instr_offset :natural := ex1_saxu_instr_offset + 1; +constant ex1_tgpr_instr_offset :natural := ex1_sdp_instr_offset + 1; +constant ex1_taxu_instr_offset :natural := ex1_tgpr_instr_offset + 1; +constant ex1_tdp_instr_offset :natural := ex1_taxu_instr_offset + 1; +constant ex2_tgpr_instr_offset :natural := ex1_tdp_instr_offset + 1; +constant ex2_taxu_instr_offset :natural := ex2_tgpr_instr_offset + 1; +constant ex2_tdp_instr_offset :natural := ex2_taxu_instr_offset + 1; +constant ex3_tgpr_instr_offset :natural := ex2_tdp_instr_offset + 1; +constant ex3_taxu_instr_offset :natural := ex3_tgpr_instr_offset + 1; +constant ex4_tgpr_instr_offset :natural := ex3_taxu_instr_offset + 1; +constant ex4_taxu_instr_offset :natural := ex4_tgpr_instr_offset + 1; +constant ex3_blkable_touch_offset :natural := ex4_taxu_instr_offset + 1; +constant ex3_p_addr_lwr_offset :natural := ex3_blkable_touch_offset + 1; +constant ex5_p_addr_offset :natural := ex3_p_addr_lwr_offset + 12; +constant eplc_wr_offset :natural := ex5_p_addr_offset + real_data_add-6; +constant epsc_wr_offset :natural := eplc_wr_offset + 4; +constant eplc_t0_reg_a_offset :natural := epsc_wr_offset + 4; +constant eplc_t0_reg_b_offset :natural := eplc_t0_reg_a_offset + 2; +constant eplc_t0_reg_c_offset :natural := eplc_t0_reg_b_offset + 9; +constant eplc_t1_reg_a_offset :natural := eplc_t0_reg_c_offset + 14; +constant eplc_t1_reg_b_offset :natural := eplc_t1_reg_a_offset + 2; +constant eplc_t1_reg_c_offset :natural := eplc_t1_reg_b_offset + 9; +constant eplc_t2_reg_a_offset :natural := eplc_t1_reg_c_offset + 14; +constant eplc_t2_reg_b_offset :natural := eplc_t2_reg_a_offset + 2; +constant eplc_t2_reg_c_offset :natural := eplc_t2_reg_b_offset + 9; +constant eplc_t3_reg_a_offset :natural := eplc_t2_reg_c_offset + 14; +constant eplc_t3_reg_b_offset :natural := eplc_t3_reg_a_offset + 2; +constant eplc_t3_reg_c_offset :natural := eplc_t3_reg_b_offset + 9; +constant epsc_t0_reg_a_offset :natural := eplc_t3_reg_c_offset + 14; +constant epsc_t0_reg_b_offset :natural := epsc_t0_reg_a_offset + 2; +constant epsc_t0_reg_c_offset :natural := epsc_t0_reg_b_offset + 9; +constant epsc_t1_reg_a_offset :natural := epsc_t0_reg_c_offset + 14; +constant epsc_t1_reg_b_offset :natural := epsc_t1_reg_a_offset + 2; +constant epsc_t1_reg_c_offset :natural := epsc_t1_reg_b_offset + 9; +constant epsc_t2_reg_a_offset :natural := epsc_t1_reg_c_offset + 14; +constant epsc_t2_reg_b_offset :natural := epsc_t2_reg_a_offset + 2; +constant epsc_t2_reg_c_offset :natural := epsc_t2_reg_b_offset + 9; +constant epsc_t3_reg_a_offset :natural := epsc_t2_reg_c_offset + 14; +constant epsc_t3_reg_b_offset :natural := epsc_t3_reg_a_offset + 2; +constant epsc_t3_reg_c_offset :natural := epsc_t3_reg_b_offset + 9; +constant ex2_undef_lockset_offset :natural := epsc_t3_reg_c_offset + 14; +constant ex3_undef_lockset_offset :natural := ex2_undef_lockset_offset + 1; +constant ex4_unable_2lock_offset :natural := ex3_undef_lockset_offset + 1; +constant ex5_unable_2lock_offset :natural := ex4_unable_2lock_offset + 1; +constant ex3_ldstq_instr_offset :natural := ex5_unable_2lock_offset + 1; +constant ex5_store_instr_offset :natural := ex3_ldstq_instr_offset + 1; +constant ex5_store_miss_offset :natural := ex5_store_instr_offset + 1; +constant ex5_perf_dcbt_offset :natural := ex5_store_miss_offset + 1; +constant perf_lsu_events_offset :natural := ex5_perf_dcbt_offset + 1; +constant clkg_ctl_override_offset :natural := perf_lsu_events_offset + 17; +constant spr_xucr0_wlck_offset :natural := clkg_ctl_override_offset + 1; +constant spr_xucr0_wlck_cpy_offset :natural := spr_xucr0_wlck_offset + 1; +constant spr_xucr0_flh2l2_offset :natural := spr_xucr0_wlck_cpy_offset + 1; +constant ex3_spr_xucr0_flh2l2_offset :natural := spr_xucr0_flh2l2_offset + 1; +constant spr_xucr0_dcdis_offset :natural := ex3_spr_xucr0_flh2l2_offset + 1; +constant spr_xucr0_cls_offset :natural := spr_xucr0_dcdis_offset + 1; +constant agen_xucr0_cls_dly_offset :natural := spr_xucr0_cls_offset + 1; +constant agen_xucr0_cls_offset :natural := agen_xucr0_cls_dly_offset + 1; +constant mtspr_trace_en_offset :natural := agen_xucr0_cls_offset + 1; +constant ex3_local_dcbf_offset :natural := mtspr_trace_en_offset + 4; +constant ex1_msgsnd_instr_offset :natural := ex3_local_dcbf_offset + 1; +constant ex2_msgsnd_instr_offset :natural := ex1_msgsnd_instr_offset + 1; +constant ex3_msgsnd_instr_offset :natural := ex2_msgsnd_instr_offset + 1; +constant ex1_dci_instr_offset :natural := ex3_msgsnd_instr_offset + 1; +constant ex2_dci_instr_offset :natural := ex1_dci_instr_offset + 1; +constant ex3_dci_instr_offset :natural := ex2_dci_instr_offset + 1; +constant ex1_ici_instr_offset :natural := ex3_dci_instr_offset + 1; +constant ex2_ici_instr_offset :natural := ex1_ici_instr_offset + 1; +constant ex3_ici_instr_offset :natural := ex2_ici_instr_offset + 1; +constant ex3_load_type_offset :natural := ex3_ici_instr_offset + 1; +constant ex3_l2load_type_offset :natural := ex3_load_type_offset + 1; +constant flh2l2_gate_offset :natural := ex3_l2load_type_offset + 1; +constant rel_upd_dcarr_offset :natural := flh2l2_gate_offset + 1; +constant ex5_xu_wren_offset :natural := rel_upd_dcarr_offset + 1; +constant ex1_ldawx_instr_offset :natural := ex5_xu_wren_offset + 1; +constant ex3_watch_en_offset :natural := ex1_ldawx_instr_offset + 1; +constant ex5_watch_en_offset :natural := ex3_watch_en_offset + 1; +constant ex1_wclr_instr_offset :natural := ex5_watch_en_offset + 1; +constant ex3_wclr_instr_offset :natural := ex1_wclr_instr_offset + 1; +constant ex5_wclr_instr_offset :natural := ex3_wclr_instr_offset + 1; +constant ex5_wclr_set_offset :natural := ex5_wclr_instr_offset + 1; +constant ex1_wchk_instr_offset :natural := ex5_wclr_set_offset + 1; +constant ex4_cacheable_linelock_offset :natural := ex1_wchk_instr_offset + 1; +constant ex1_icswx_instr_offset :natural := ex4_cacheable_linelock_offset + 1; +constant ex3_icswx_instr_offset :natural := ex1_icswx_instr_offset + 1; +constant ex1_icswx_dot_instr_offset :natural := ex3_icswx_instr_offset + 1; +constant ex3_icswx_dot_instr_offset :natural := ex1_icswx_dot_instr_offset + 1; +constant ex1_icswx_epid_offset :natural := ex3_icswx_dot_instr_offset + 1; +constant ex3_icswx_epid_offset :natural := ex1_icswx_epid_offset + 1; +constant ex3_c_inh_drop_op_offset :natural := ex3_icswx_epid_offset + 1; +constant axu_rel_wren_offset :natural := ex3_c_inh_drop_op_offset + 1; +constant axu_rel_wren_stg1_offset :natural := axu_rel_wren_offset + 1; +constant rel_axu_tid_offset :natural := axu_rel_wren_stg1_offset + 1; +constant rel_axu_tid_stg1_offset :natural := rel_axu_tid_offset + 4; +constant rel_axu_ta_gpr_offset :natural := rel_axu_tid_stg1_offset + 4; +constant rel_axu_ta_gpr_stg1_offset :natural := rel_axu_ta_gpr_offset + 9; +constant rf0_l2_inv_val_offset :natural := rel_axu_ta_gpr_stg1_offset + 9; +constant rf1_l2_inv_val_offset :natural := rf0_l2_inv_val_offset + 1; +constant ex1_agen_binv_val_offset :natural := rf1_l2_inv_val_offset + 1; +constant ex1_l2_inv_val_offset :natural := ex1_agen_binv_val_offset + 1; +constant lsu_msr_gs_offset :natural := ex1_l2_inv_val_offset + 1; +constant lsu_msr_pr_offset :natural := lsu_msr_gs_offset + 4; +constant lsu_msr_cm_offset :natural := lsu_msr_pr_offset + 4; +constant ex1_lsu_64bit_agen_offset :natural := lsu_msr_cm_offset + 4; +constant ex6_icbi_val_offset :natural := ex1_lsu_64bit_agen_offset + 1; +constant ex1_mtspr_trace_offset :natural := ex6_icbi_val_offset + 4; +constant ex2_mtspr_trace_offset :natural := ex1_mtspr_trace_offset + 1; +constant ex3_mtspr_trace_offset :natural := ex2_mtspr_trace_offset + 1; +constant ex3_byte_en_offset :natural := ex3_mtspr_trace_offset + 1; +constant ex3_rot_sel_le_offset :natural := ex3_byte_en_offset + 32; +constant ex3_rot_sel_be_offset :natural := ex3_rot_sel_le_offset + 5; +constant dir_arr_rd_val_offset :natural := ex3_rot_sel_be_offset + 5; +constant dir_arr_rd_is0_val_offset :natural := dir_arr_rd_val_offset + 1; +constant dir_arr_rd_is1_val_offset :natural := dir_arr_rd_is0_val_offset + 1; +constant dir_arr_rd_is2_val_offset :natural := dir_arr_rd_is1_val_offset + 1; +constant dir_arr_rd_rf0_val_offset :natural := dir_arr_rd_is2_val_offset + 1; +constant dir_arr_rd_rf1_val_offset :natural := dir_arr_rd_rf0_val_offset + 1; +constant dir_arr_rd_rf0_done_offset :natural := dir_arr_rd_rf1_val_offset + 1; +constant dir_arr_rd_rf1_done_offset :natural := dir_arr_rd_rf0_done_offset + 1; +constant dir_arr_rd_ex1_done_offset :natural := dir_arr_rd_rf1_done_offset + 1; +constant dir_arr_rd_ex2_done_offset :natural := dir_arr_rd_ex1_done_offset + 1; +constant dir_arr_rd_ex3_done_offset :natural := dir_arr_rd_ex2_done_offset + 1; +constant dir_arr_rd_ex4_done_offset :natural := dir_arr_rd_ex3_done_offset + 1; +constant my_spare0_latches_offset :natural := dir_arr_rd_ex4_done_offset + 1; +constant my_spare1_latches_offset :natural := my_spare0_latches_offset + 3; +constant rf1_stg_act_offset :natural := my_spare1_latches_offset + 20; +constant ex1_stg_act_offset :natural := rf1_stg_act_offset + 1; +constant ex3_stg_act_offset :natural := ex1_stg_act_offset + 1; +constant ex5_stg_act_offset :natural := ex3_stg_act_offset + 1; +constant binv1_stg_act_offset :natural := ex5_stg_act_offset + 1; +constant binv3_stg_act_offset :natural := binv1_stg_act_offset + 1; +constant binv5_stg_act_offset :natural := binv3_stg_act_offset + 1; +constant rel1_stg_act_offset :natural := binv5_stg_act_offset + 1; +constant rel3_stg_act_offset :natural := rel1_stg_act_offset + 1; +constant scan_right :natural := rel3_stg_act_offset + 1 - 1; + +-- SlowSPR addresses +constant XUCR2_ADDR :std_ulogic_vector(0 to 9) := "11" & x"F8"; +constant XUDBG0_ADDR :std_ulogic_vector(0 to 9) := "11" & x"75"; +constant XUDBG1_ADDR :std_ulogic_vector(0 to 9) := "11" & x"76"; +constant XUDBG2_ADDR :std_ulogic_vector(0 to 9) := "11" & x"77"; +constant DVC1_ADDR :std_ulogic_vector(0 to 9) := "01" & x"3E"; +constant DVC2_ADDR :std_ulogic_vector(0 to 9) := "01" & x"3F"; +constant EPLC_ADDR :std_ulogic_vector(0 to 9) := "11" & x"B3"; +constant EPSC_ADDR :std_ulogic_vector(0 to 9) := "11" & x"B4"; + +---------------------------- +-- signals +---------------------------- +signal ex1_optype1_d :std_ulogic; +signal ex2_optype1_d :std_ulogic; +signal ex1_optype2_d :std_ulogic; +signal ex2_optype2_d :std_ulogic; +signal ex1_optype4_d :std_ulogic; +signal ex2_optype4_d :std_ulogic; +signal ex1_optype8_d :std_ulogic; +signal ex2_optype8_d :std_ulogic; +signal ex1_optype16_d :std_ulogic; +signal ex2_optype16_d :std_ulogic; +signal ex1_optype32_d :std_ulogic; +signal ex2_optype32_d :std_ulogic; +signal ex1_dir_acc_val_d :std_ulogic; +signal ex1_dir_acc_val_q :std_ulogic; +signal cache_acc_ex1_d :std_ulogic; +signal cache_acc_ex2_d :std_ulogic; +signal cache_acc_ex3_d :std_ulogic; +signal cache_acc_ex4_d :std_ulogic; +signal cache_acc_ex5_d :std_ulogic; +signal ex2_cacc_d :std_ulogic; +signal ex2_cacc_q :std_ulogic; +signal ex3_cacc_d :std_ulogic; +signal ex3_cacc_q :std_ulogic; +signal ex1_thrd_id_d :std_ulogic_vector(0 to 3); +signal ex2_thrd_id_d :std_ulogic_vector(0 to 3); +signal ex3_thrd_id_d :std_ulogic_vector(0 to 3); +signal ex4_thrd_id_d :std_ulogic_vector(0 to 3); +signal ex5_thrd_id_d :std_ulogic_vector(0 to 3); +signal ex1_target_gpr_d :std_ulogic_vector(0 to 8); +signal ex2_target_gpr_d :std_ulogic_vector(0 to 8); +signal ex3_target_gpr_d :std_ulogic_vector(0 to 8); +signal ex4_target_gpr_d :std_ulogic_vector(0 to 8); +signal ex1_dcbt_instr_d :std_ulogic; +signal ex2_dcbt_instr_d :std_ulogic; +signal ex3_dcbt_instr_d :std_ulogic; +signal ex1_dcbtst_instr_d :std_ulogic; +signal ex2_dcbtst_instr_d :std_ulogic; +signal ex3_dcbtst_instr_d :std_ulogic; +signal ex1_dcbst_instr_d :std_ulogic; +signal ex2_dcbst_instr_d :std_ulogic; +signal ex3_dcbst_instr_d :std_ulogic; +signal ex1_dcbf_instr_d :std_ulogic; +signal ex2_dcbf_instr_d :std_ulogic; +signal ex3_dcbf_instr_d :std_ulogic; +signal ex1_sync_instr_d :std_ulogic; +signal ex2_sync_instr_d :std_ulogic; +signal ex3_sync_instr_d :std_ulogic; +signal ex1_l_fld_d :std_ulogic_vector(0 to 1); +signal ex2_l_fld_d :std_ulogic_vector(0 to 1); +signal ex3_l_fld_d :std_ulogic_vector(0 to 1); +signal ex1_dcbi_instr_d :std_ulogic; +signal ex2_dcbi_instr_d :std_ulogic; +signal ex3_dcbi_instr_d :std_ulogic; +signal ex1_dcbz_instr_d :std_ulogic; +signal ex2_dcbz_instr_d :std_ulogic; +signal ex3_dcbz_instr_d :std_ulogic; +signal ex1_icbi_instr_d :std_ulogic; +signal ex2_icbi_instr_d :std_ulogic; +signal ex3_icbi_instr_d :std_ulogic; +signal ex4_icbi_instr_d :std_ulogic; +signal ex5_icbi_instr_d :std_ulogic; +signal ex1_mbar_instr_d :std_ulogic; +signal ex2_mbar_instr_d :std_ulogic; +signal ex3_mbar_instr_d :std_ulogic; +signal ex1_lock_instr_d :std_ulogic; +signal ex2_lock_instr_d :std_ulogic; +signal ex3_lock_instr_d :std_ulogic; +signal ex4_lock_instr_d :std_ulogic; +signal ex5_lock_instr_d :std_ulogic; +signal ex1_load_instr_d :std_ulogic; +signal ex2_load_instr_d :std_ulogic; +signal ex3_load_instr_d :std_ulogic; +signal ex4_load_instr_d :std_ulogic; +signal ex5_load_instr_d :std_ulogic; +signal ex3_load_type_d :std_ulogic; +signal ex3_load_type_q :std_ulogic; +signal ex4_load_type_d :std_ulogic; +signal ex4_load_type_q :std_ulogic; +signal ex1_store_instr_d :std_ulogic; +signal ex2_store_instr_d :std_ulogic; +signal ex3_store_instr_d :std_ulogic; +signal ex1_optype1_q :std_ulogic; +signal ex2_optype1_q :std_ulogic; +signal ex1_optype2_q :std_ulogic; +signal ex2_optype2_q :std_ulogic; +signal ex1_optype4_q :std_ulogic; +signal ex2_optype4_q :std_ulogic; +signal ex1_optype8_q :std_ulogic; +signal ex2_optype8_q :std_ulogic; +signal ex1_optype16_q :std_ulogic; +signal ex2_optype16_q :std_ulogic; +signal ex1_optype32_q :std_ulogic; +signal ex2_optype32_q :std_ulogic; +signal cache_acc_ex1_q :std_ulogic; +signal cache_acc_ex2_q :std_ulogic; +signal cache_acc_ex3_q :std_ulogic; +signal cache_acc_ex4_q :std_ulogic; +signal cache_acc_ex5_q :std_ulogic; +signal ex1_thrd_id_q :std_ulogic_vector(0 to 3); +signal ex2_thrd_id_q :std_ulogic_vector(0 to 3); +signal ex3_thrd_id_q :std_ulogic_vector(0 to 3); +signal ex4_thrd_id_q :std_ulogic_vector(0 to 3); +signal ex5_thrd_id_q :std_ulogic_vector(0 to 3); +signal ex1_target_gpr_q :std_ulogic_vector(0 to 8); +signal ex2_target_gpr_q :std_ulogic_vector(0 to 8); +signal ex3_target_gpr_q :std_ulogic_vector(0 to 8); +signal ex4_target_gpr_q :std_ulogic_vector(0 to 8); +signal ex1_dcbt_instr_q :std_ulogic; +signal ex2_dcbt_instr_q :std_ulogic; +signal ex3_dcbt_instr_q :std_ulogic; +signal ex1_dcbtst_instr_q :std_ulogic; +signal ex2_dcbtst_instr_q :std_ulogic; +signal ex3_dcbtst_instr_q :std_ulogic; +signal ex1_dcbst_instr_q :std_ulogic; +signal ex2_dcbst_instr_q :std_ulogic; +signal ex3_dcbst_instr_q :std_ulogic; +signal ex1_dcbf_instr_q :std_ulogic; +signal ex2_dcbf_instr_q :std_ulogic; +signal ex3_dcbf_instr_q :std_ulogic; +signal ex1_sync_instr_q :std_ulogic; +signal ex2_sync_instr_q :std_ulogic; +signal ex3_sync_instr_q :std_ulogic; +signal ex1_l_fld_q :std_ulogic_vector(0 to 1); +signal ex2_l_fld_q :std_ulogic_vector(0 to 1); +signal ex3_l_fld_q :std_ulogic_vector(0 to 1); +signal ex1_dcbi_instr_q :std_ulogic; +signal ex2_dcbi_instr_q :std_ulogic; +signal ex3_dcbi_instr_q :std_ulogic; +signal ex1_dcbz_instr_q :std_ulogic; +signal ex2_dcbz_instr_q :std_ulogic; +signal ex3_dcbz_instr_q :std_ulogic; +signal ex1_icbi_instr_q :std_ulogic; +signal ex2_icbi_instr_q :std_ulogic; +signal ex3_icbi_instr_q :std_ulogic; +signal ex4_icbi_instr_q :std_ulogic; +signal ex5_icbi_instr_q :std_ulogic; +signal ex5_icbi_instr :std_ulogic; +signal ex1_mbar_instr_q :std_ulogic; +signal ex2_mbar_instr_q :std_ulogic; +signal ex3_mbar_instr_q :std_ulogic; +signal ex1_lock_instr_q :std_ulogic; +signal ex2_lock_instr_q :std_ulogic; +signal ex3_lock_instr_q :std_ulogic; +signal ex4_lock_instr_q :std_ulogic; +signal ex5_lock_instr_q :std_ulogic; +signal ex1_load_instr_q :std_ulogic; +signal ex2_load_instr_q :std_ulogic; +signal ex3_load_instr_q :std_ulogic; +signal ex4_load_instr_q :std_ulogic; +signal ex5_load_instr_q :std_ulogic; +signal ex1_store_instr_q :std_ulogic; +signal ex2_store_instr_q :std_ulogic; +signal ex3_store_instr_q :std_ulogic; +signal ex4_cache_inh_d :std_ulogic; +signal ex4_cache_inh_q :std_ulogic; +signal ex5_cache_inh_d :std_ulogic; +signal ex5_cache_inh_q :std_ulogic; +signal l_s_q_val :std_ulogic; +signal stx_instr :std_ulogic; +signal larx_instr :std_ulogic; +signal is_mem_bar_op :std_ulogic; +signal is_inval_op :std_ulogic; +signal is_lock_set :std_ulogic; +signal ex3_l2_lock_set :std_ulogic; +signal ex3_c_dcbtls :std_ulogic; +signal ex3_c_dcbtstls :std_ulogic; +signal ex3_c_icbtls :std_ulogic; +signal ex3_l2_dcbtls :std_ulogic; +signal ex3_l2_dcbtstls :std_ulogic; +signal ex3_l2_icbtls :std_ulogic; +signal is_lock_clr :std_ulogic; +signal no_lru_upd :std_ulogic; +signal l2_ctype :std_ulogic; +signal reg_upd_thrd_id :std_ulogic_vector(0 to 3); +signal reg_upd_ta_gpr :std_ulogic_vector(0 to 8); +signal xu_wren :std_ulogic; +signal ex5_xu_wren_d :std_ulogic; +signal ex5_xu_wren_q :std_ulogic; +signal axu_wren :std_ulogic; +signal axu_rel_wren_d :std_ulogic; +signal axu_rel_wren_q :std_ulogic; +signal axu_rel_wren_stg1_d :std_ulogic; +signal axu_rel_wren_stg1_q :std_ulogic; +signal rel_thrd_id_d :std_ulogic_vector(0 to 3); +signal rel_thrd_id_q :std_ulogic_vector(0 to 3); +signal rel_ta_gpr_d :std_ulogic_vector(0 to 8); +signal rel_ta_gpr_q :std_ulogic_vector(0 to 8); +signal rel_upd_gpr_d :std_ulogic; +signal rel_upd_gpr_q :std_ulogic; +signal rel_axu_op_val_d :std_ulogic; +signal rel_axu_op_val_q :std_ulogic; +signal ex4_load_miss :std_ulogic; +signal ex5_load_miss_d :std_ulogic; +signal ex5_load_miss_q :std_ulogic; +signal ex3_l2_op_d :std_ulogic; +signal ex3_l2_op_q :std_ulogic; +signal ex4_load_hit :std_ulogic; +signal ex4_load_commit_d :std_ulogic; +signal ex4_load_commit_q :std_ulogic; +signal ex5_load_hit_d :std_ulogic; +signal ex5_load_hit_q :std_ulogic; +signal ex1_axu_op_val_d :std_ulogic; +signal ex1_axu_op_val_q :std_ulogic; +signal ex2_axu_op_val_d :std_ulogic; +signal ex2_axu_op_val_q :std_ulogic; +signal ex3_axu_op_val_d :std_ulogic; +signal ex3_axu_op_val_q :std_ulogic; +signal ex4_axu_op_val_d :std_ulogic; +signal ex4_axu_op_val_q :std_ulogic; +signal ex5_axu_op_val_d :std_ulogic; +signal ex5_axu_op_val_q :std_ulogic; +signal ex2_op_sel :std_ulogic_vector(0 to 15); +signal ex2_opsize :std_ulogic_vector(0 to 5); +signal ex3_opsize_d :std_ulogic_vector(0 to 5); +signal ex3_opsize_q :std_ulogic_vector(0 to 5); +signal ex5_axu_wren_d :std_ulogic_vector(0 to 3); +signal ex5_axu_wren_q :std_ulogic_vector(0 to 3); +signal ex5_axu_wren_val :std_ulogic; +signal ex5_axu_ta_gpr_d :std_ulogic_vector(0 to 8); +signal ex5_axu_ta_gpr_q :std_ulogic_vector(0 to 8); +signal rel_xu_ta_gpr_d :std_ulogic_vector(0 to 7); +signal rel_xu_ta_gpr_q :std_ulogic_vector(0 to 7); +signal ex1_algebraic_d :std_ulogic; +signal ex1_algebraic_q :std_ulogic; +signal ex2_algebraic_d :std_ulogic; +signal ex2_algebraic_q :std_ulogic; +signal ex3_algebraic_d :std_ulogic; +signal ex3_algebraic_q :std_ulogic; +signal ex1_byte_rev_d :std_ulogic; +signal ex1_byte_rev_q :std_ulogic; +signal ex2_byte_rev_d :std_ulogic; +signal ex2_byte_rev_q :std_ulogic; +signal ex3_byte_rev_d :std_ulogic; +signal ex3_byte_rev_q :std_ulogic; +signal lsu_slowspr_val_d :std_ulogic; +signal lsu_slowspr_rw_d :std_ulogic; +signal lsu_slowspr_etid_d :std_ulogic_vector(0 to 1); +signal lsu_slowspr_addr_d :std_ulogic_vector(0 to 9); +signal lsu_slowspr_data_d :std_ulogic_vector(64-(2**REGMODE) to 63); +signal lsu_slowspr_done_d :std_ulogic; +signal lsu_slowspr_val_q :std_ulogic; +signal lsu_slowspr_rw_q :std_ulogic; +signal lsu_slowspr_etid_q :std_ulogic_vector(0 to 1); +signal lsu_slowspr_addr_q :std_ulogic_vector(0 to 9); +signal lsu_slowspr_data_q :std_ulogic_vector(64-(2**REGMODE) to 63); +signal lsu_slowspr_done_q :std_ulogic; +signal mm_slowspr_val_d :std_ulogic; +signal mm_slowspr_rw_d :std_ulogic; +signal mm_slowspr_etid_d :std_ulogic_vector(0 to 1); +signal mm_slowspr_addr_d :std_ulogic_vector(0 to 9); +signal mm_slowspr_data_d :std_ulogic_vector(64-(2**REGMODE) to 63); +signal mm_slowspr_done_d :std_ulogic; +signal mm_slowspr_val_q :std_ulogic; +signal mm_slowspr_rw_q :std_ulogic; +signal mm_slowspr_etid_q :std_ulogic_vector(0 to 1); +signal mm_slowspr_addr_q :std_ulogic_vector(0 to 9); +signal mm_slowspr_data_q :std_ulogic_vector(64-(2**REGMODE) to 63); +signal mm_slowspr_done_q :std_ulogic; +signal ex3_nogpr_upd :std_ulogic; +signal rf1_th_b0 :std_ulogic; +signal ex1_th_fld_c_d :std_ulogic; +signal ex1_th_fld_c_q :std_ulogic; +signal ex2_th_fld_c_d :std_ulogic; +signal ex2_th_fld_c_q :std_ulogic; +signal ex3_th_fld_c_d :std_ulogic; +signal ex3_th_fld_c_q :std_ulogic; +signal ex1_th_fld_l2_d :std_ulogic; +signal ex1_th_fld_l2_q :std_ulogic; +signal ex2_th_fld_l2_d :std_ulogic; +signal ex2_th_fld_l2_q :std_ulogic; +signal ex3_th_fld_l2_d :std_ulogic; +signal ex3_th_fld_l2_q :std_ulogic; +signal ex1_undef_touch :std_ulogic; +signal ex1_dcbtls_instr_d :std_ulogic; +signal ex1_dcbtls_instr_q :std_ulogic; +signal ex2_dcbtls_instr_d :std_ulogic; +signal ex2_dcbtls_instr_q :std_ulogic; +signal ex3_dcbtls_instr_d :std_ulogic; +signal ex3_dcbtls_instr_q :std_ulogic; +signal ex1_dcbtstls_instr_d :std_ulogic; +signal ex1_dcbtstls_instr_q :std_ulogic; +signal ex2_dcbtstls_instr_d :std_ulogic; +signal ex2_dcbtstls_instr_q :std_ulogic; +signal ex3_dcbtstls_instr_d :std_ulogic; +signal ex3_dcbtstls_instr_q :std_ulogic; +signal ex1_dcblc_instr_d :std_ulogic; +signal ex1_dcblc_instr_q :std_ulogic; +signal ex2_dcblc_instr_d :std_ulogic; +signal ex2_dcblc_instr_q :std_ulogic; +signal ex3_dcblc_instr_d :std_ulogic; +signal ex3_dcblc_instr_q :std_ulogic; +signal ex1_icblc_l2_instr_d :std_ulogic; +signal ex1_icblc_l2_instr_q :std_ulogic; +signal ex2_icblc_l2_instr_d :std_ulogic; +signal ex2_icblc_l2_instr_q :std_ulogic; +signal ex3_icblc_l2_instr_d :std_ulogic; +signal ex3_icblc_l2_instr_q :std_ulogic; +signal ex1_icbt_l2_instr_d :std_ulogic; +signal ex1_icbt_l2_instr_q :std_ulogic; +signal ex2_icbt_l2_instr_d :std_ulogic; +signal ex2_icbt_l2_instr_q :std_ulogic; +signal ex3_icbt_l2_instr_d :std_ulogic; +signal ex3_icbt_l2_instr_q :std_ulogic; +signal ex1_icbtls_l2_instr_d :std_ulogic; +signal ex1_icbtls_l2_instr_q :std_ulogic; +signal ex2_icbtls_l2_instr_d :std_ulogic; +signal ex2_icbtls_l2_instr_q :std_ulogic; +signal ex3_icbtls_l2_instr_d :std_ulogic; +signal ex3_icbtls_l2_instr_q :std_ulogic; +signal ex1_tlbsync_instr_d :std_ulogic; +signal ex1_tlbsync_instr_q :std_ulogic; +signal ex2_tlbsync_instr_d :std_ulogic; +signal ex2_tlbsync_instr_q :std_ulogic; +signal ex3_tlbsync_instr_d :std_ulogic; +signal ex3_tlbsync_instr_q :std_ulogic; +signal ex1_src0_vld_d :std_ulogic; +signal ex1_src0_vld_q :std_ulogic; +signal ex1_src0_reg_d :std_ulogic_vector(0 to 7); +signal ex1_src0_reg_q :std_ulogic_vector(0 to 7); +signal ex1_src1_vld_d :std_ulogic; +signal ex1_src1_vld_q :std_ulogic; +signal ex1_src1_reg_d :std_ulogic_vector(0 to 7); +signal ex1_src1_reg_q :std_ulogic_vector(0 to 7); +signal ex1_targ_vld_d :std_ulogic; +signal ex1_targ_vld_q :std_ulogic; +signal ex1_targ_reg_d :std_ulogic_vector(0 to 7); +signal ex1_targ_reg_q :std_ulogic_vector(0 to 7); +signal ex5_instr_val_d :std_ulogic; +signal ex5_instr_val_q :std_ulogic; +signal ex2_targ_match_b1_d :std_ulogic; +signal ex2_targ_match_b1_q :std_ulogic; +signal ex3_targ_match_b1_d :std_ulogic; +signal ex3_targ_match_b1_q :std_ulogic; +signal ex4_targ_match_b1_d :std_ulogic; +signal ex4_targ_match_b1_q :std_ulogic; +signal ex5_targ_match_b1_d :std_ulogic; +signal ex5_targ_match_b1_q :std_ulogic; +signal ex6_targ_match_b1_d :std_ulogic; +signal ex6_targ_match_b1_q :std_ulogic; +signal ex2_targ_match_b2_d :std_ulogic; +signal ex2_targ_match_b2_q :std_ulogic; +signal ex3_targ_match_b2_d :std_ulogic; +signal ex3_targ_match_b2_q :std_ulogic; +signal ex4_targ_match_b2_d :std_ulogic; +signal ex4_targ_match_b2_q :std_ulogic; +signal ex5_targ_match_b2_d :std_ulogic; +signal ex5_targ_match_b2_q :std_ulogic; +signal ex7_targ_match_d :std_ulogic; +signal ex7_targ_match_q :std_ulogic; +signal ex8_targ_match_d :std_ulogic; +signal ex8_targ_match_q :std_ulogic; +signal ex3_l2_request_d :std_ulogic; +signal ex3_l2_request_q :std_ulogic; +signal ex1_ldst_falign_d :std_ulogic; +signal ex1_ldst_falign_q :std_ulogic; +signal ex1_ldst_fexcpt_d :std_ulogic; +signal ex1_ldst_fexcpt_q :std_ulogic; +signal ex2_ldst_fexcpt_d :std_ulogic; +signal ex2_ldst_fexcpt_q :std_ulogic; +signal xucr2_sel :std_ulogic; +signal dvc1_sel :std_ulogic; +signal dvc2_sel :std_ulogic; +signal eplc_sel :std_ulogic; +signal epsc_sel :std_ulogic; +signal xudbg0_sel :std_ulogic; +signal xudbg1_sel :std_ulogic; +signal xudbg2_sel :std_ulogic; +signal xucr2_wen :std_ulogic; +signal dvc1_wen :std_ulogic; +signal dvc1_act_d :std_ulogic; +signal dvc1_act_q :std_ulogic; +signal dvc2_wen :std_ulogic; +signal dvc2_act_d :std_ulogic; +signal dvc2_act_q :std_ulogic; +signal xudbg0_wen :std_ulogic; +signal eplc_t0_wen :std_ulogic; +signal eplc_t0_hyp_wen :std_ulogic; +signal eplc_t1_wen :std_ulogic; +signal eplc_t1_hyp_wen :std_ulogic; +signal eplc_t2_wen :std_ulogic; +signal eplc_t2_hyp_wen :std_ulogic; +signal eplc_t3_wen :std_ulogic; +signal eplc_t3_hyp_wen :std_ulogic; +signal epsc_t0_wen :std_ulogic; +signal epsc_t0_hyp_wen :std_ulogic; +signal epsc_t1_wen :std_ulogic; +signal epsc_t1_hyp_wen :std_ulogic; +signal epsc_t2_wen :std_ulogic; +signal epsc_t2_hyp_wen :std_ulogic; +signal epsc_t3_wen :std_ulogic; +signal epsc_t3_hyp_wen :std_ulogic; +signal xucr2_reg :std_ulogic_vector((64-(2**REGMODE)) to 63); +signal xucr2_reg_d :std_ulogic_vector(0 to 31); +signal xucr2_reg_q :std_ulogic_vector(0 to 31); +signal dvc1_reg :std_ulogic_vector((64-(2**REGMODE)) to 63); +signal dvc1_reg_d :std_ulogic_vector((64-(2**REGMODE)) to 63); +signal dvc1_reg_q :std_ulogic_vector((64-(2**REGMODE)) to 63); +signal dvc2_reg :std_ulogic_vector((64-(2**REGMODE)) to 63); +signal dvc2_reg_d :std_ulogic_vector((64-(2**REGMODE)) to 63); +signal dvc2_reg_q :std_ulogic_vector((64-(2**REGMODE)) to 63); +signal xudbg0_reg :std_ulogic_vector((64-(2**REGMODE)) to 63); +signal xudbg0_reg_d :std_ulogic_vector(0 to 7); +signal xudbg0_reg_q :std_ulogic_vector(0 to 7); +signal xudbg0_done_reg_d :std_ulogic; +signal xudbg0_done_reg_q :std_ulogic; +signal xudbg1_reg :std_ulogic_vector((64-(2**REGMODE)) to 63); +signal xudbg1_dir_reg_d :std_ulogic_vector(0 to 12); +signal xudbg1_dir_reg_q :std_ulogic_vector(0 to 12); +signal xudbg1_parity_reg_d :std_ulogic_vector(0 to parBits-1); +signal xudbg1_parity_reg_q :std_ulogic_vector(0 to parBits-1); +signal xudbg2_reg :std_ulogic_vector((64-(2**REGMODE)) to 63); +signal xudbg2_reg_d :std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); +signal xudbg2_reg_q :std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); +signal eplc_t0_reg :std_ulogic_vector(0 to 24); +signal eplc_t0_reg_d :std_ulogic_vector(0 to 24); +signal eplc_t0_reg_q :std_ulogic_vector(0 to 24); +signal eplc_t1_reg :std_ulogic_vector(0 to 24); +signal eplc_t1_reg_d :std_ulogic_vector(0 to 24); +signal eplc_t1_reg_q :std_ulogic_vector(0 to 24); +signal eplc_t2_reg :std_ulogic_vector(0 to 24); +signal eplc_t2_reg_d :std_ulogic_vector(0 to 24); +signal eplc_t2_reg_q :std_ulogic_vector(0 to 24); +signal eplc_t3_reg :std_ulogic_vector(0 to 24); +signal eplc_t3_reg_d :std_ulogic_vector(0 to 24); +signal eplc_t3_reg_q :std_ulogic_vector(0 to 24); +signal epsc_t0_reg :std_ulogic_vector(0 to 24); +signal epsc_t0_reg_d :std_ulogic_vector(0 to 24); +signal epsc_t0_reg_q :std_ulogic_vector(0 to 24); +signal epsc_t1_reg :std_ulogic_vector(0 to 24); +signal epsc_t1_reg_d :std_ulogic_vector(0 to 24); +signal epsc_t1_reg_q :std_ulogic_vector(0 to 24); +signal epsc_t2_reg :std_ulogic_vector(0 to 24); +signal epsc_t2_reg_d :std_ulogic_vector(0 to 24); +signal epsc_t2_reg_q :std_ulogic_vector(0 to 24); +signal epsc_t3_reg :std_ulogic_vector(0 to 24); +signal epsc_t3_reg_d :std_ulogic_vector(0 to 24); +signal epsc_t3_reg_q :std_ulogic_vector(0 to 24); +signal eplc_thrd_reg :std_ulogic_vector(0 to 24); +signal epsc_thrd_reg :std_ulogic_vector(0 to 24); +signal eplc_reg :std_ulogic_vector((64-(2**REGMODE)) to 63); +signal epsc_reg :std_ulogic_vector((64-(2**REGMODE)) to 63); +signal eplc_wrt_data :std_ulogic_vector(0 to 24); +signal epsc_wrt_data :std_ulogic_vector(0 to 24); +signal spr_l1dc_rd_val :std_ulogic; +signal spr_l1dc_reg :std_ulogic_vector((64-(2**REGMODE)) to 63); +signal way_lck_rmt :std_ulogic_vector(0 to 31); +signal clkg_ctl_override_d :std_ulogic; +signal clkg_ctl_override_q :std_ulogic; +signal spr_xucr0_wlck_d :std_ulogic; +signal spr_xucr0_wlck_q :std_ulogic; +signal spr_xucr0_wlck_cpy_d :std_ulogic; +signal spr_xucr0_wlck_cpy_q :std_ulogic; +signal spr_xucr0_flh2l2_d :std_ulogic; +signal spr_xucr0_flh2l2_q :std_ulogic; +signal ex2_spr_xucr0_flh2l2 :std_ulogic; +signal ex3_spr_xucr0_flh2l2_d :std_ulogic; +signal ex3_spr_xucr0_flh2l2_q :std_ulogic; +signal spr_xucr0_dcdis_d :std_ulogic; +signal spr_xucr0_dcdis_q :std_ulogic; +signal spr_xucr0_cls_d :std_ulogic; +signal spr_xucr0_cls_q :std_ulogic; +signal agen_xucr0_cls_d :std_ulogic; +signal agen_xucr0_cls_q :std_ulogic; +signal agen_xucr0_cls_dly_d :std_ulogic; +signal agen_xucr0_cls_dly_q :std_ulogic; +signal ex4_store_commit_d :std_ulogic; +signal ex4_store_commit_q :std_ulogic; +signal ex1_sgpr_instr_d :std_ulogic; +signal ex1_sgpr_instr_q :std_ulogic; +signal ex1_saxu_instr_d :std_ulogic; +signal ex1_saxu_instr_q :std_ulogic; +signal ex1_sdp_instr_d :std_ulogic; +signal ex1_sdp_instr_q :std_ulogic; +signal ex1_tgpr_instr_d :std_ulogic; +signal ex1_tgpr_instr_q :std_ulogic; +signal ex1_taxu_instr_d :std_ulogic; +signal ex1_taxu_instr_q :std_ulogic; +signal ex1_tdp_instr_d :std_ulogic; +signal ex1_tdp_instr_q :std_ulogic; +signal ex2_tgpr_instr_d :std_ulogic; +signal ex2_tgpr_instr_q :std_ulogic; +signal ex2_taxu_instr_d :std_ulogic; +signal ex2_taxu_instr_q :std_ulogic; +signal ex2_tdp_instr_d :std_ulogic; +signal ex2_tdp_instr_q :std_ulogic; +signal ex3_tgpr_instr_d :std_ulogic; +signal ex3_tgpr_instr_q :std_ulogic; +signal ex3_taxu_instr_d :std_ulogic; +signal ex3_taxu_instr_q :std_ulogic; +signal ex4_tgpr_instr_d :std_ulogic; +signal ex4_tgpr_instr_q :std_ulogic; +signal ex4_taxu_instr_d :std_ulogic; +signal ex4_taxu_instr_q :std_ulogic; +signal ex4_tgpr_instr :std_ulogic; +signal ex4_taxu_instr :std_ulogic; +signal ex2_dcblc_l1 :std_ulogic; +signal data_touch_op :std_ulogic; +signal inst_touch_op :std_ulogic; +signal all_touch_op :std_ulogic; +signal ddir_acc_instr :std_ulogic; +signal ex2_blkable_touch_d :std_ulogic; +signal ex2_blkable_touch_q :std_ulogic; +signal ex3_blkable_touch_d :std_ulogic; +signal ex3_blkable_touch_q :std_ulogic; +signal ex3_blk_touch :std_ulogic; +signal ex2_l2_dcbf :std_ulogic; +signal ex2_local_dcbf :std_ulogic; +signal ex1_mutex_hint_d :std_ulogic; +signal ex1_mutex_hint_q :std_ulogic; +signal ex2_mutex_hint_d :std_ulogic; +signal ex2_mutex_hint_q :std_ulogic; +signal ex3_mutex_hint_d :std_ulogic; +signal ex3_mutex_hint_q :std_ulogic; +signal ex3_p_addr_lwr_d :std_ulogic_vector(52 to 63); +signal ex3_p_addr_lwr_q :std_ulogic_vector(52 to 63); +signal ex4_p_addr_d :std_ulogic_vector(64-real_data_add to 63); +signal ex4_p_addr_q :std_ulogic_vector(64-real_data_add to 63); +signal ex5_p_addr_d :std_ulogic_vector(64-real_data_add to 57); +signal ex5_p_addr_q :std_ulogic_vector(64-real_data_add to 57); +signal ex6_p_addr_d :std_ulogic_vector(64-real_data_add to 57); +signal ex6_p_addr_q :std_ulogic_vector(64-real_data_add to 57); +signal eplc_wr_d :std_ulogic_vector(0 to 3); +signal eplc_wr_q :std_ulogic_vector(0 to 3); +signal epsc_wr_d :std_ulogic_vector(0 to 3); +signal epsc_wr_q :std_ulogic_vector(0 to 3); +signal ex1_lockset_instr :std_ulogic; +signal ex2_undef_lockset_d :std_ulogic; +signal ex2_undef_lockset_q :std_ulogic; +signal ex3_undef_lockset_d :std_ulogic; +signal ex3_undef_lockset_q :std_ulogic; +signal ex3_cinh_lockset :std_ulogic; +signal ex3_l1dcdis_lockset :std_ulogic; +signal ex4_unable_2lock_d :std_ulogic; +signal ex4_unable_2lock_q :std_ulogic; +signal ex5_unable_2lock_d :std_ulogic; +signal ex5_unable_2lock_q :std_ulogic; +signal ex3_ldstq_instr_d :std_ulogic; +signal ex3_ldstq_instr_q :std_ulogic; +signal ex4_store_instr_d :std_ulogic; +signal ex4_store_instr_q :std_ulogic; +signal ex5_store_instr_d :std_ulogic; +signal ex5_store_instr_q :std_ulogic; +signal ex4_store_miss :std_ulogic; +signal ex5_store_miss_d :std_ulogic; +signal ex5_store_miss_q :std_ulogic; +signal ex4_perf_dcbt_d :std_ulogic; +signal ex4_perf_dcbt_q :std_ulogic; +signal ex5_perf_dcbt_d :std_ulogic; +signal ex5_perf_dcbt_q :std_ulogic; +signal perf_com_stores :std_ulogic; +signal perf_com_store_miss :std_ulogic; +signal perf_com_stcx_exec :std_ulogic; +signal perf_com_loadmiss :std_ulogic; +signal perf_com_cinh_loads :std_ulogic; +signal perf_com_loads :std_ulogic; +signal perf_com_dcbt_sent :std_ulogic; +signal perf_com_dcbt_hit :std_ulogic; +signal perf_com_axu_load :std_ulogic; +signal perf_com_axu_store :std_ulogic; +signal perf_com_watch_clr :std_ulogic; +signal perf_com_wclr_lfld :std_ulogic; +signal perf_com_watch_set :std_ulogic; +signal perf_lsu_events_d :std_ulogic_vector(0 to 16); +signal perf_lsu_events_q :std_ulogic_vector(0 to 16); +signal ex3_local_dcbf_d :std_ulogic; +signal ex3_local_dcbf_q :std_ulogic; +signal ex1_msgsnd_instr_d :std_ulogic; +signal ex1_msgsnd_instr_q :std_ulogic; +signal ex2_msgsnd_instr_d :std_ulogic; +signal ex2_msgsnd_instr_q :std_ulogic; +signal ex3_msgsnd_instr_d :std_ulogic; +signal ex3_msgsnd_instr_q :std_ulogic; +signal ex1_dci_instr_d :std_ulogic; +signal ex1_dci_instr_q :std_ulogic; +signal ex2_dci_instr_d :std_ulogic; +signal ex2_dci_instr_q :std_ulogic; +signal ex3_dci_instr_d :std_ulogic; +signal ex3_dci_instr_q :std_ulogic; +signal ex1_ici_instr_d :std_ulogic; +signal ex1_ici_instr_q :std_ulogic; +signal ex2_ici_instr_d :std_ulogic; +signal ex2_ici_instr_q :std_ulogic; +signal ex3_ici_instr_d :std_ulogic; +signal ex3_ici_instr_q :std_ulogic; +signal ex3_l2load_type_d :std_ulogic; +signal ex3_l2load_type_q :std_ulogic; +signal flh2l2_gate_d :std_ulogic; +signal flh2l2_gate_q :std_ulogic; +signal rel_upd_dcarr_d :std_ulogic; +signal rel_upd_dcarr_q :std_ulogic; +signal ex1_ldawx_instr_d :std_ulogic; +signal ex1_ldawx_instr_q :std_ulogic; +signal ex2_ldawx_instr_d :std_ulogic; +signal ex2_ldawx_instr_q :std_ulogic; +signal ex3_watch_en_d :std_ulogic; +signal ex3_watch_en_q :std_ulogic; +signal ex4_watch_en_d :std_ulogic; +signal ex4_watch_en_q :std_ulogic; +signal ex5_watch_en_d :std_ulogic; +signal ex5_watch_en_q :std_ulogic; +signal ex1_wclr_instr_d :std_ulogic; +signal ex1_wclr_instr_q :std_ulogic; +signal ex2_wclr_instr_d :std_ulogic; +signal ex2_wclr_instr_q :std_ulogic; +signal ex3_wclr_instr_d :std_ulogic; +signal ex3_wclr_instr_q :std_ulogic; +signal ex4_wclr_instr_d :std_ulogic; +signal ex4_wclr_instr_q :std_ulogic; +signal ex5_wclr_instr_d :std_ulogic; +signal ex5_wclr_instr_q :std_ulogic; +signal ex4_wclr_set_d :std_ulogic; +signal ex4_wclr_set_q :std_ulogic; +signal ex5_wclr_set_d :std_ulogic; +signal ex5_wclr_set_q :std_ulogic; +signal ex1_wchk_instr_d :std_ulogic; +signal ex1_wchk_instr_q :std_ulogic; +signal ex2_wchk_instr_d :std_ulogic; +signal ex2_wchk_instr_q :std_ulogic; +signal ex3_stq_full_flush :std_ulogic; +signal ex3_lsq_ig_flush :std_ulogic; +signal ex4_cacheable_linelock_d :std_ulogic; +signal ex4_cacheable_linelock_q :std_ulogic; +signal ex1_icswx_instr_d :std_ulogic; +signal ex1_icswx_instr_q :std_ulogic; +signal ex2_icswx_instr_d :std_ulogic; +signal ex2_icswx_instr_q :std_ulogic; +signal ex3_icswx_instr_d :std_ulogic; +signal ex3_icswx_instr_q :std_ulogic; +signal ex1_icswx_dot_instr_d :std_ulogic; +signal ex1_icswx_dot_instr_q :std_ulogic; +signal ex2_icswx_dot_instr_d :std_ulogic; +signal ex2_icswx_dot_instr_q :std_ulogic; +signal ex3_icswx_dot_instr_d :std_ulogic; +signal ex3_icswx_dot_instr_q :std_ulogic; +signal ex1_icswx_epid_d :std_ulogic; +signal ex1_icswx_epid_q :std_ulogic; +signal ex2_icswx_epid_d :std_ulogic; +signal ex2_icswx_epid_q :std_ulogic; +signal ex3_icswx_epid_d :std_ulogic; +signal ex3_icswx_epid_q :std_ulogic; +signal ex3_c_inh_drop_op_d :std_ulogic; +signal ex3_c_inh_drop_op_q :std_ulogic; +signal ex3_drop_ld_req_b :std_ulogic; +signal ex3_drop_touch_int :std_ulogic; +signal ex3_drop_ld :std_ulogic; +signal ex3_drop_cacheable :std_ulogic; +signal ex3_drop_cacheable_b :std_ulogic; +signal ex3_cache_enabled :std_ulogic; +signal ex3_cache_inhibited :std_ulogic; +signal ex5_axu_rel_val_stg1_d :std_ulogic; +signal ex5_axu_rel_val_stg1_q :std_ulogic; +signal ex5_axu_rel_val_stg2_d :std_ulogic; +signal ex5_axu_rel_val_stg2_q :std_ulogic; +signal rel_axu_tid_d :std_ulogic_vector(0 to 3); +signal rel_axu_tid_q :std_ulogic_vector(0 to 3); +signal rel_axu_tid_stg1_d :std_ulogic_vector(0 to 3); +signal rel_axu_tid_stg1_q :std_ulogic_vector(0 to 3); +signal rel_axu_ta_gpr_d :std_ulogic_vector(0 to 8); +signal rel_axu_ta_gpr_q :std_ulogic_vector(0 to 8); +signal rel_axu_ta_gpr_stg1_d :std_ulogic_vector(0 to 8); +signal rel_axu_ta_gpr_stg1_q :std_ulogic_vector(0 to 8); +signal rf0_l2_inv_val_d :std_ulogic; +signal rf0_l2_inv_val_q :std_ulogic; +signal rf1_l2_inv_val_d :std_ulogic; +signal rf1_l2_inv_val_q :std_ulogic; +signal ex1_agen_binv_val_d :std_ulogic; +signal ex1_agen_binv_val_q :std_ulogic; +signal ex1_l2_inv_val_d :std_ulogic; +signal ex1_l2_inv_val_q :std_ulogic; +signal lsu_msr_gs_d :std_ulogic_vector(0 to 3); +signal lsu_msr_gs_q :std_ulogic_vector(0 to 3); +signal lsu_msr_pr_d :std_ulogic_vector(0 to 3); +signal lsu_msr_pr_q :std_ulogic_vector(0 to 3); +signal hypervisor_state :std_ulogic_vector(0 to 3); +signal lsu_msr_cm_d :std_ulogic_vector(0 to 3); +signal lsu_msr_cm_q :std_ulogic_vector(0 to 3); +signal rf1_lsu_64bit_mode :std_ulogic; +signal ex1_lsu_64bit_agen_d :std_ulogic; +signal ex1_lsu_64bit_agen_q :std_ulogic; +signal ex6_icbi_val_d :std_ulogic_vector(0 to 3); +signal ex6_icbi_val_q :std_ulogic_vector(0 to 3); +signal ex1_mtspr_trace_d :std_ulogic; +signal ex1_mtspr_trace_q :std_ulogic; +signal ex2_mtspr_trace_d :std_ulogic; +signal ex2_mtspr_trace_q :std_ulogic; +signal ex3_mtspr_trace_d :std_ulogic; +signal ex3_mtspr_trace_q :std_ulogic; +signal rf1_stg_act_d :std_ulogic; +signal rf1_stg_act_q :std_ulogic; +signal ex1_stg_act_d :std_ulogic; +signal ex1_stg_act_q :std_ulogic; +signal ex2_stg_act_d :std_ulogic; +signal ex2_stg_act_q :std_ulogic; +signal ex3_stg_act_d :std_ulogic; +signal ex3_stg_act_q :std_ulogic; +signal ex4_stg_act_d :std_ulogic; +signal ex4_stg_act_q :std_ulogic; +signal ex5_stg_act_d :std_ulogic; +signal ex5_stg_act_q :std_ulogic; +signal binv1_stg_act_d :std_ulogic; +signal binv1_stg_act_q :std_ulogic; +signal binv2_stg_act_d :std_ulogic; +signal binv2_stg_act_q :std_ulogic; +signal binv3_stg_act_d :std_ulogic; +signal binv3_stg_act_q :std_ulogic; +signal binv4_stg_act_d :std_ulogic; +signal binv4_stg_act_q :std_ulogic; +signal binv5_stg_act_d :std_ulogic; +signal binv5_stg_act_q :std_ulogic; +signal rel1_stg_act_d :std_ulogic; +signal rel1_stg_act_q :std_ulogic; +signal rel3_stg_act_d :std_ulogic; +signal rel3_stg_act_q :std_ulogic; +signal rel4_stg_act_d :std_ulogic; +signal rel4_stg_act_q :std_ulogic; +signal rel4_ex4_stg_act :std_ulogic; +signal binv2_ex2_stg_act :std_ulogic; +signal mtspr_trace_en_d :std_ulogic_vector(0 to 3); +signal mtspr_trace_en_q :std_ulogic_vector(0 to 3); +signal ex2_be10_en :std_ulogic_vector(0 to 31); +signal ex2_beC840_en :std_ulogic_vector(0 to 31); +signal ex2_be3210_en :std_ulogic_vector(0 to 31); +signal ex2_byte_en :std_ulogic_vector(0 to 31); +signal ex3_byte_en_d :std_ulogic_vector(0 to 31); +signal ex3_byte_en_q :std_ulogic_vector(0 to 31); +signal ex3_data_swap_val :std_ulogic; +signal ex2_rot_sel_be :std_ulogic_vector(0 to 5); +signal ex2_rot_sel_le :std_ulogic_vector(0 to 5); +signal ex3_rot_sel_le_d :std_ulogic_vector(1 to 5); +signal ex3_rot_sel_le_q :std_ulogic_vector(1 to 5); +signal ex3_rot_sel_be_d :std_ulogic_vector(1 to 5); +signal ex3_rot_sel_be_q :std_ulogic_vector(1 to 5); +signal ex3_rot_sel :std_ulogic_vector(0 to 4); +signal ex1_watch_clr_all :std_ulogic; +signal ex2_watch_clr_entry :std_ulogic; +signal dir_arr_rd_done :std_ulogic; +signal dir_arr_rd_cntrl :std_ulogic_vector(0 to 1); +signal dir_arr_rd_val_d :std_ulogic; +signal dir_arr_rd_val_q :std_ulogic; +signal dir_arr_rd_is0_val_d :std_ulogic; +signal dir_arr_rd_is0_val_q :std_ulogic; +signal dir_arr_rd_is1_val_d :std_ulogic; +signal dir_arr_rd_is1_val_q :std_ulogic; +signal dir_arr_rd_is2_val_d :std_ulogic; +signal dir_arr_rd_is2_val_q :std_ulogic; +signal dir_arr_rd_rf0_val_d :std_ulogic; +signal dir_arr_rd_rf0_val_q :std_ulogic; +signal dir_arr_rd_rf1_val_d :std_ulogic; +signal dir_arr_rd_rf1_val_q :std_ulogic; +signal dir_arr_rd_rf0_done_d :std_ulogic; +signal dir_arr_rd_rf0_done_q :std_ulogic; +signal dir_arr_rd_rf1_done_d :std_ulogic; +signal dir_arr_rd_rf1_done_q :std_ulogic; +signal dir_arr_rd_ex1_done_d :std_ulogic; +signal dir_arr_rd_ex1_done_q :std_ulogic; +signal dir_arr_rd_ex2_done_d :std_ulogic; +signal dir_arr_rd_ex2_done_q :std_ulogic; +signal dir_arr_rd_ex3_done_d :std_ulogic; +signal dir_arr_rd_ex3_done_q :std_ulogic; +signal dir_arr_rd_ex4_done_d :std_ulogic; +signal dir_arr_rd_ex4_done_q :std_ulogic; +signal dir_arr_rd_tag :std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); +signal dir_arr_rd_directory :std_ulogic_vector(0 to 5); +signal dir_arr_rd_parity :std_ulogic_vector(0 to parBits-1); +signal dir_arr_rd_lru :std_ulogic_vector(0 to 6); +signal ex2_flh2l2_load :std_ulogic; +signal ex2_l2_lock_clr :std_ulogic; +signal ex4_thrd_enc :std_ulogic_vector(0 to 1); +signal my_spare0_lclk :clk_logic; +signal my_spare0_d1clk :std_ulogic; +signal my_spare0_d2clk :std_ulogic; +signal my_spare0_latches_d :std_ulogic_vector(0 to 2); +signal my_spare0_latches_q :std_ulogic_vector(0 to 2); +signal my_spare1_lclk :clk_logic; +signal my_spare1_d1clk :std_ulogic; +signal my_spare1_d2clk :std_ulogic; +signal my_spare1_latches_d :std_ulogic_vector(0 to 19); +signal my_spare1_latches_q :std_ulogic_vector(0 to 19); +signal ex4_c_inh_d :std_ulogic; +signal ex4_c_inh_q :std_ulogic; +signal ex4_opsize_d :std_ulogic_vector(0 to 5); +signal ex4_opsize_q :std_ulogic_vector(0 to 5); +signal ex4_rot_sel_d :std_ulogic_vector(0 to 4); +signal ex4_rot_sel_q :std_ulogic_vector(0 to 4); +signal ex4_data_swap_val_d :std_ulogic; +signal ex4_data_swap_val_q :std_ulogic; +signal ex4_algebraic_d :std_ulogic; +signal ex4_algebraic_q :std_ulogic; +signal ex4_lock_en_d :std_ulogic; +signal ex4_lock_en_q :std_ulogic; + +signal tiup :std_ulogic; +signal siv :std_ulogic_vector(0 to scan_right); +signal sov :std_ulogic_vector(0 to scan_right); + + + +begin + +tiup <= '1'; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Act Signals going to all Latches +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +rf1_stg_act_d <= xu_lsu_rf0_act or clkg_ctl_override_q; +ex1_stg_act_d <= xu_lsu_rf1_cmd_act or dir_arr_rd_rf1_val_q or clkg_ctl_override_q; +ex2_stg_act_d <= ex1_stg_act_q; +ex3_stg_act_d <= ex2_stg_act_q; +ex4_stg_act_d <= ex3_stg_act_q; +ex5_stg_act_d <= ex4_stg_act_q; + +binv1_stg_act_d <= rf1_l2_inv_val_q or clkg_ctl_override_q; +binv2_stg_act_d <= binv1_stg_act_q; +binv3_stg_act_d <= binv2_stg_act_q; +binv4_stg_act_d <= binv3_stg_act_q; +binv5_stg_act_d <= binv4_stg_act_q; + +rel1_stg_act_d <= ldq_rel_data_val_early or clkg_ctl_override_q; +rel3_stg_act_d <= ldq_rel_stg24_val or clkg_ctl_override_q; +rel4_stg_act_d <= rel3_stg_act_q; + +rel4_ex4_stg_act <= ex4_stg_act_q or rel4_stg_act_q; +binv2_ex2_stg_act <= binv2_stg_act_q or ex2_stg_act_q; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- XU Config Bits +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +flh2l2_gate_d <= an_ac_flh2l2_gate; + +-- Clock Gating Override +clkg_ctl_override_d <= spr_xucr0_clkg_ctl_b1; + +-- XUCR0[WLK] +-- 1 => Way Locking Enabled +-- 0 => Way Locking Disabled +spr_xucr0_wlck_d <= xu_lsu_spr_xucr0_wlk and not xu_lsu_spr_ccr2_dfrat; +spr_xucr0_wlck_cpy_d <= spr_xucr0_wlck_q; + +-- XUCR0[FHL2L2] +-- 1 => Send Load L1hit to L2 +-- 0 => Do not send Load L1hit to L2 +spr_xucr0_flh2l2_d <= xu_lsu_spr_xucr0_flh2l2 and flh2l2_gate_q; +ex2_spr_xucr0_flh2l2 <= spr_xucr0_flh2l2_q; +ex3_spr_xucr0_flh2l2_d <= ex2_spr_xucr0_flh2l2; + +-- XUCR0[DC_DIS] +-- 1 => L1 Data Cache Disabled +-- 0 => L1 Data Cache Enabled +spr_xucr0_dcdis_d <= xu_lsu_spr_xucr0_dcdis; + +-- XUCR0[CLS] +-- 1 => 128 Byte Cacheline +-- 0 => 64 Byte Cacheline +spr_xucr0_cls_d <= xu_lsu_spr_xucr0_cls; +agen_xucr0_cls_dly_d <= spr_xucr0_cls_q; +agen_xucr0_cls_d <= agen_xucr0_cls_dly_q; + +-- MTSPR TRACE Enabled +mtspr_trace_en_d <= xu_lsu_mtspr_trace_en; + +-- Determine threads in hypervisor state +lsu_msr_gs_d <= xu_lsu_msr_gs; +lsu_msr_pr_d <= xu_lsu_msr_pr; +hypervisor_state <= lsu_msr_gs_q nor lsu_msr_pr_q; + +-- 64Bit mode Select +lsu_msr_cm_d <= xu_lsu_spr_msr_cm; +rf1_lsu_64bit_mode <= (xu_lsu_rf1_thrd_id(0) and lsu_msr_cm_q(0)) or (xu_lsu_rf1_thrd_id(1) and lsu_msr_cm_q(1)) or + (xu_lsu_rf1_thrd_id(2) and lsu_msr_cm_q(2)) or (xu_lsu_rf1_thrd_id(3) and lsu_msr_cm_q(3)); +ex1_lsu_64bit_agen_d <= rf1_lsu_64bit_mode or rf1_l2_inv_val_q; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Back-Invalidate Pipe +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +-- Back-Invalidate Address comes from ALU +-- it is provided in IS2 and muxed into bypass in RF1 +-- it is then added with 0 and bypasses the erat translation +rf0_l2_inv_val_d <= is2_l2_inv_val; +rf1_l2_inv_val_d <= rf0_l2_inv_val_q; +ex1_agen_binv_val_d <= rf1_l2_inv_val_q; +ex1_l2_inv_val_d <= rf1_l2_inv_val_q; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Execution Pipe Inputs +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +ex1_optype1_d <= xu_lsu_rf1_optype1; +ex2_optype1_d <= ex1_optype1_q; + +ex1_optype2_d <= xu_lsu_rf1_optype2; +ex2_optype2_d <= ex1_optype2_q; + +ex1_optype4_d <= xu_lsu_rf1_optype4; +ex2_optype4_d <= ex1_optype4_q; + +ex1_optype8_d <= xu_lsu_rf1_optype8; +ex2_optype8_d <= ex1_optype8_q; + +ex1_optype16_d <= xu_lsu_rf1_optype16; +ex2_optype16_d <= ex1_optype16_q; + +ex1_optype32_d <= xu_lsu_rf1_optype32; +ex2_optype32_d <= ex1_optype32_q; + +ex3_p_addr_lwr_d <= ex2_p_addr_lwr; +ex4_p_addr_d <= ex3_p_addr & ex3_p_addr_lwr_q(52 to 63); +ex5_p_addr_d <= ex4_p_addr_q(64-real_data_add to 57); +ex6_p_addr_d <= ex5_p_addr_q; + +-- Directory Access is Valid indicator, used to reject reload write if accessing +-- same congruence class +ex1_dir_acc_val_d <= dir_arr_rd_rf1_done_q or (xu_lsu_rf1_cache_acc and not rf1_stg_flush); + +cache_acc_ex1_d <= xu_lsu_rf1_cache_acc and not rf1_stg_flush; +cache_acc_ex2_d <= cache_acc_ex1_q and not (ex1_undef_touch or ex1_stg_flush); +cache_acc_ex3_d <= cache_acc_ex2_q and not ex2_stg_flush; +cache_acc_ex4_d <= cache_acc_ex3_q and not ex3_stg_flush; +cache_acc_ex5_d <= cache_acc_ex4_q and not ex4_stg_flush; +ex2_cacc_d <= cache_acc_ex1_q; +ex3_cacc_d <= ex2_cacc_q; + +ex1_thrd_id_d <= xu_lsu_rf1_thrd_id; +ex2_thrd_id_d <= ex1_thrd_id_q; +ex3_thrd_id_d <= ex2_thrd_id_q; +ex4_thrd_id_d <= ex3_thrd_id_q; +ex5_thrd_id_d <= ex4_thrd_id_q; + +with ex4_thrd_id_q select + ex4_thrd_enc <= "01" when "0100", + "10" when "0010", + "11" when "0001", + "00" when others; + +ex1_target_gpr_d <= xu_lsu_rf1_target_gpr; +ex2_target_gpr_d <= ex1_target_gpr_q; +ex3_target_gpr_d <= ex2_target_gpr_q; +ex4_target_gpr_d <= ex3_target_gpr_q; + +ex1_dcbt_instr_d <= xu_lsu_rf1_dcbt_instr; +ex2_dcbt_instr_d <= ex1_dcbt_instr_q and (ex1_th_fld_c_q or ex1_th_fld_l2_q); +ex3_dcbt_instr_d <= ex2_dcbt_instr_q; + +ex1_dcbtst_instr_d <= xu_lsu_rf1_dcbtst_instr; +ex2_dcbtst_instr_d <= ex1_dcbtst_instr_q and (ex1_th_fld_c_q or ex1_th_fld_l2_q); +ex3_dcbtst_instr_d <= ex2_dcbtst_instr_q; + +ex4_perf_dcbt_d <= (ex3_th_fld_l2_q or ex3_th_fld_c_q) and (ex3_dcbtst_instr_q or ex3_dcbt_instr_q or ex3_dcbtstls_instr_q or ex3_dcbtls_instr_q) and not ex3_blk_touch; +ex5_perf_dcbt_d <= ex4_perf_dcbt_q; + +rf1_th_b0 <= xu_lsu_rf1_th_fld(0) and (xu_lsu_rf1_dcbt_instr or xu_lsu_rf1_dcbtst_instr); +ex1_th_fld_c_d <= not rf1_th_b0 and (xu_lsu_rf1_th_fld(1 to 4) = "0000"); +ex2_th_fld_c_d <= ex1_th_fld_c_q; +ex3_th_fld_c_d <= ex2_th_fld_c_q; + +ex1_th_fld_l2_d <= not rf1_th_b0 and (xu_lsu_rf1_th_fld(1 to 4) = "0010"); +ex2_th_fld_l2_d <= ex1_th_fld_l2_q; +ex3_th_fld_l2_d <= ex2_th_fld_l2_q; + +-- Need to check the L1 and send to the L2 when th=00000 +-- Need to not check the L1 and send to the L2 when th=00010 +ex1_dcbtls_instr_d <= xu_lsu_rf1_dcbtls_instr; +ex2_dcbtls_instr_d <= ex1_dcbtls_instr_q and (ex1_th_fld_c_q or ex1_th_fld_l2_q); +ex3_dcbtls_instr_d <= ex2_dcbtls_instr_q; + +-- Need to check the L1 and send to the L2 when th=00000 +-- Need to not check the L1 and send to the L2 when th=00010 +ex1_dcbtstls_instr_d <= xu_lsu_rf1_dcbtstls_instr; +ex2_dcbtstls_instr_d <= ex1_dcbtstls_instr_q and (ex1_th_fld_c_q or ex1_th_fld_l2_q); +ex3_dcbtstls_instr_d <= ex2_dcbtstls_instr_q; + +-- Need to check the L1 and not send to the L2 when th=00000 +-- Need to not check the L1 and send to the L2 when th=00010 +ex1_dcblc_instr_d <= xu_lsu_rf1_dcblc_instr; +ex2_dcblc_instr_d <= ex1_dcblc_instr_q and (ex1_th_fld_c_q or ex1_th_fld_l2_q); +ex3_dcblc_instr_d <= ex2_dcblc_instr_q; + +-- Need to not check the L1 and not send to the L2 when th=00000 +-- Need to not check the L1 and send to the L2 when th=00010 +ex1_icblc_l2_instr_d <= xu_lsu_rf1_icblc_instr; +ex2_icblc_l2_instr_d <= ex1_icblc_l2_instr_q and (ex1_th_fld_c_q or ex1_th_fld_l2_q); +ex3_icblc_l2_instr_d <= ex2_icblc_l2_instr_q; + +-- Need to not check the L1 and send to the L2 +ex1_icbt_l2_instr_d <= xu_lsu_rf1_icbt_instr; +ex2_icbt_l2_instr_d <= ex1_icbt_l2_instr_q and (ex1_th_fld_c_q or ex1_th_fld_l2_q); +ex3_icbt_l2_instr_d <= ex2_icbt_l2_instr_q; + +-- Need to not check the L1 and send to the L2 +ex1_icbtls_l2_instr_d <= xu_lsu_rf1_icbtls_instr; +ex2_icbtls_l2_instr_d <= ex1_icbtls_l2_instr_q and (ex1_th_fld_c_q or ex1_th_fld_l2_q); +ex3_icbtls_l2_instr_d <= ex2_icbtls_l2_instr_q; + +ex1_tlbsync_instr_d <= xu_lsu_rf1_tlbsync_instr and not rf1_stg_flush; +ex2_tlbsync_instr_d <= ex1_tlbsync_instr_q and not ex1_stg_flush; +ex3_tlbsync_instr_d <= ex2_tlbsync_instr_q and not ex2_stg_flush; + +-- Load Double and Set Watch Bit +ex1_ldawx_instr_d <= xu_lsu_rf1_ldawx_instr; +ex2_ldawx_instr_d <= ex1_ldawx_instr_q; +ex3_watch_en_d <= ex2_ldawx_instr_q; +ex4_watch_en_d <= ex3_watch_en_q; +ex5_watch_en_d <= ex4_watch_en_q; + +-- ICSWX Non-Record Form Instruction +ex1_icswx_instr_d <= xu_lsu_rf1_icswx_instr; +ex2_icswx_instr_d <= ex1_icswx_instr_q; +ex3_icswx_instr_d <= ex2_icswx_instr_q; + +-- ICSWX Record Form Instruction +ex1_icswx_dot_instr_d <= xu_lsu_rf1_icswx_dot_instr; +ex2_icswx_dot_instr_d <= ex1_icswx_dot_instr_q; +ex3_icswx_dot_instr_d <= ex2_icswx_dot_instr_q; + +-- ICSWX External PID Form Instruction +ex1_icswx_epid_d <= xu_lsu_rf1_icswx_epid; +ex2_icswx_epid_d <= ex1_icswx_epid_q; +ex3_icswx_epid_d <= ex2_icswx_epid_q; + +-- Watch Clear +ex1_wclr_instr_d <= xu_lsu_rf1_wclr_instr; +ex2_wclr_instr_d <= ex1_wclr_instr_q; +ex3_wclr_instr_d <= ex2_wclr_instr_q; +ex4_wclr_instr_d <= ex3_wclr_instr_q; +ex5_wclr_instr_d <= ex4_wclr_instr_q; +ex4_wclr_set_d <= ex3_l_fld_q = "01"; +ex5_wclr_set_d <= ex4_wclr_set_q; + +ex1_watch_clr_all <= ex1_wclr_instr_q and not ex1_l_fld_q(0); + +-- Watch Check +ex1_wchk_instr_d <= xu_lsu_rf1_wchk_instr and not rf1_stg_flush; +ex2_wchk_instr_d <= ex1_wchk_instr_q and not ex1_stg_flush; + +ex1_dcbst_instr_d <= xu_lsu_rf1_dcbst_instr; +ex2_dcbst_instr_d <= ex1_dcbst_instr_q; +ex3_dcbst_instr_d <= ex2_dcbst_instr_q; + +ex1_dcbf_instr_d <= xu_lsu_rf1_dcbf_instr; +ex2_dcbf_instr_d <= ex1_dcbf_instr_q; +ex2_l2_dcbf <= ex2_dcbf_instr_q and not (ex2_l_fld_q = "11"); +ex2_local_dcbf <= ex2_dcbf_instr_q and (ex2_l_fld_q = "11"); +ex3_dcbf_instr_d <= ex2_dcbf_instr_q; + +ex1_mtspr_trace_d <= xu_lsu_rf1_mtspr_trace and not rf1_stg_flush; +ex2_mtspr_trace_d <= ex1_mtspr_trace_q and (or_reduce(mtspr_trace_en_q and ex1_thrd_id_q)) and not ex1_stg_flush; +ex3_mtspr_trace_d <= ex2_mtspr_trace_q and not ex2_stg_flush; + +ex1_sync_instr_d <= xu_lsu_rf1_sync_instr and not rf1_stg_flush; +ex2_sync_instr_d <= ex1_sync_instr_q and not ex1_stg_flush; +ex3_sync_instr_d <= ex2_sync_instr_q and not ex2_stg_flush; + +ex1_l_fld_d <= xu_lsu_rf1_l_fld; +ex2_l_fld_d <= ex1_l_fld_q; +ex3_l_fld_d <= ex2_l_fld_q; + +ex1_dcbi_instr_d <= xu_lsu_rf1_dcbi_instr; +ex2_dcbi_instr_d <= ex1_dcbi_instr_q; +ex3_dcbi_instr_d <= ex2_dcbi_instr_q; + +ex1_dcbz_instr_d <= xu_lsu_rf1_dcbz_instr; +ex2_dcbz_instr_d <= ex1_dcbz_instr_q; +ex3_dcbz_instr_d <= ex2_dcbz_instr_q; + +ex1_icbi_instr_d <= xu_lsu_rf1_icbi_instr; +ex2_icbi_instr_d <= ex1_icbi_instr_q; +ex3_icbi_instr_d <= ex2_icbi_instr_q; +ex4_icbi_instr_d <= ex3_icbi_instr_q; +ex5_icbi_instr_d <= ex4_icbi_instr_q; +ex5_icbi_instr <= ex5_icbi_instr_q and cache_acc_ex5_q and not ex5_stg_flush; +ex6_icbi_val_d <= gate(ex5_thrd_id_q, ex5_icbi_instr); + +ex1_mbar_instr_d <= xu_lsu_rf1_mbar_instr and not rf1_stg_flush; +ex2_mbar_instr_d <= ex1_mbar_instr_q and not ex1_stg_flush; +ex3_mbar_instr_d <= ex2_mbar_instr_q and not ex2_stg_flush; + +ex1_msgsnd_instr_d <= xu_lsu_rf1_is_msgsnd and not rf1_stg_flush; +ex2_msgsnd_instr_d <= ex1_msgsnd_instr_q and not ex1_stg_flush; +ex3_msgsnd_instr_d <= ex2_msgsnd_instr_q and not ex2_stg_flush; + +-- DCI with CT=0 -> invalidate L1 only +-- DCI with CT=2 -> invalidate L1 and send to L2 +-- DCI with CT!=0,2 -> No-Op +ex1_dci_instr_d <= xu_lsu_rf1_dci_instr and not rf1_stg_flush; +ex2_dci_instr_d <= ex1_dci_instr_q and ex1_th_fld_l2_q and not ex1_stg_flush; +ex3_dci_instr_d <= ex2_dci_instr_q and not ex2_stg_flush; + +-- ICI with CT=0 -> invalidate L1 only +-- ICI with CT=2 -> invalidate L1 and send to L2 +-- ICI with CT!=0,2 -> No-Op +ex1_ici_instr_d <= xu_lsu_rf1_ici_instr and not rf1_stg_flush; +ex2_ici_instr_d <= ex1_ici_instr_q and ex1_th_fld_l2_q and not ex1_stg_flush; +ex3_ici_instr_d <= ex2_ici_instr_q and not ex2_stg_flush; + +ex1_algebraic_d <= xu_lsu_rf1_algebraic; +ex2_algebraic_d <= ex1_algebraic_q; +ex3_algebraic_d <= ex2_algebraic_q; + +ex1_byte_rev_d <= xu_lsu_rf1_byte_rev; +ex2_byte_rev_d <= ex1_byte_rev_q; +ex3_byte_rev_d <= ex2_byte_rev_q; + +ex1_lock_instr_d <= xu_lsu_rf1_lock_instr; +ex2_lock_instr_d <= ex1_lock_instr_q; +ex3_lock_instr_d <= ex2_lock_instr_q; +ex4_lock_instr_d <= ex3_lock_instr_q; +ex5_lock_instr_d <= ex4_lock_instr_q; + +ex1_mutex_hint_d <= xu_lsu_rf1_mutex_hint; +ex2_mutex_hint_d <= ex1_mutex_hint_q; +ex3_mutex_hint_d <= ex2_mutex_hint_q; + +ex1_load_instr_d <= xu_lsu_rf1_load_instr; +ex2_load_instr_d <= ex1_load_instr_q; +ex3_load_instr_d <= ex2_load_instr_q; +ex4_load_instr_d <= ex3_load_instr_q; +ex5_load_instr_d <= ex4_load_instr_q; +ex3_load_type_d <= ex2_load_instr_q or ex2_dcbt_instr_q or ex2_dcbtst_instr_q or ex2_dcbtls_instr_q or ex2_dcbtstls_instr_q; +ex4_load_type_d <= ex3_load_type_q; +ex3_l2load_type_d <= ex3_load_type_d or ex2_icbt_l2_instr_q or ex2_icbtls_l2_instr_q; + +ex1_store_instr_d <= xu_lsu_rf1_store_instr; +ex2_store_instr_d <= ex1_store_instr_q; +ex3_store_instr_d <= ex2_store_instr_q; +ex4_store_instr_d <= ex3_store_instr_q; +ex5_store_instr_d <= ex4_store_instr_q; + +ex1_axu_op_val_d <= xu_lsu_rf1_axu_op_val; +ex2_axu_op_val_d <= ex1_axu_op_val_q; +ex3_axu_op_val_d <= ex2_axu_op_val_q; +ex4_axu_op_val_d <= ex3_axu_op_val_q; +ex5_axu_op_val_d <= ex4_axu_op_val_q; + +ex1_src0_vld_d <= xu_lsu_rf1_src0_vld and not rf1_stg_flush; +ex1_src0_reg_d <= xu_lsu_rf1_src0_reg; +ex1_src1_vld_d <= xu_lsu_rf1_src1_vld and not rf1_stg_flush; +ex1_src1_reg_d <= xu_lsu_rf1_src1_reg; +ex1_targ_vld_d <= xu_lsu_rf1_targ_vld and not rf1_stg_flush; +ex1_targ_reg_d <= xu_lsu_rf1_targ_reg; + +ex1_sgpr_instr_d <= xu_lsu_rf1_src_gpr and not rf1_stg_flush; +ex1_saxu_instr_d <= xu_lsu_rf1_src_axu and not rf1_stg_flush; +ex1_sdp_instr_d <= xu_lsu_rf1_src_dp and not rf1_stg_flush; +ex1_tgpr_instr_d <= xu_lsu_rf1_targ_gpr and not rf1_stg_flush; +ex1_taxu_instr_d <= xu_lsu_rf1_targ_axu and not rf1_stg_flush; +ex1_tdp_instr_d <= xu_lsu_rf1_targ_dp and not rf1_stg_flush; + +ex2_tgpr_instr_d <= ex1_tgpr_instr_q and not ex1_stg_flush; +ex2_taxu_instr_d <= ex1_taxu_instr_q and not ex1_stg_flush; +ex2_tdp_instr_d <= ex1_tdp_instr_q and not ex1_stg_flush; + +ex3_tgpr_instr_d <= ex2_tgpr_instr_q and not ex2_stg_flush; +ex3_taxu_instr_d <= ex2_taxu_instr_q and not ex2_stg_flush; + +ex4_tgpr_instr_d <= ex3_tgpr_instr_q and not ex3_stg_flush; +ex4_taxu_instr_d <= ex3_taxu_instr_q and not ex3_stg_flush; +ex4_tgpr_instr <= ex4_tgpr_instr_q and not ex4_stg_flush; +ex4_taxu_instr <= ex4_taxu_instr_q and not ex4_stg_flush; + +ex1_ldst_falign_d <= xu_lsu_rf1_axu_ldst_falign; +ex1_ldst_fexcpt_d <= xu_lsu_rf1_axu_ldst_fexcpt; +ex2_ldst_fexcpt_d <= ex1_ldst_fexcpt_q; + +rel_upd_dcarr_d <= rel_dcarr_val_upd; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Byte Enable Generation +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +-- OpSize +ex2_opsize <= ex2_optype32_q & ex2_optype16_q & ex2_optype8_q & ex2_optype4_q & ex2_optype2_q & ex2_optype1_q; +ex3_opsize_d <= ex2_opsize; + +-- Need to generate byte enables for the type of operation +-- size1 => 0x8000 +-- size2 => 0xC000 +-- size4 => 0xF000 +-- size8 => 0xFF00 +-- size16 => 0xFFFF +ex2_op_sel(0) <= ex2_opsize(1) or ex2_opsize(2) or ex2_opsize(3) or ex2_opsize(4) or ex2_opsize(5); +ex2_op_sel(1) <= ex2_opsize(1) or ex2_opsize(2) or ex2_opsize(3) or ex2_opsize(4); +ex2_op_sel(2) <= ex2_opsize(1) or ex2_opsize(2) or ex2_opsize(3); +ex2_op_sel(3) <= ex2_opsize(1) or ex2_opsize(2) or ex2_opsize(3); +ex2_op_sel(4) <= ex2_opsize(1) or ex2_opsize(2); +ex2_op_sel(5) <= ex2_opsize(1) or ex2_opsize(2); +ex2_op_sel(6) <= ex2_opsize(1) or ex2_opsize(2); +ex2_op_sel(7) <= ex2_opsize(1) or ex2_opsize(2); +ex2_op_sel(8) <= ex2_opsize(1); +ex2_op_sel(9) <= ex2_opsize(1); +ex2_op_sel(10) <= ex2_opsize(1); +ex2_op_sel(11) <= ex2_opsize(1); +ex2_op_sel(12) <= ex2_opsize(1); +ex2_op_sel(13) <= ex2_opsize(1); +ex2_op_sel(14) <= ex2_opsize(1); +ex2_op_sel(15) <= ex2_opsize(1); + +-- 32 Bit Rotator +-- Need to Rotate optype generated byte enables +with ex2_p_addr_lwr(59) select + ex2_be10_en <= ex2_op_sel(0 to 15) & x"0000" when '0', + x"0000" & ex2_op_sel(0 to 15) when others; + +-- Selects between Data rotated by 0, 4, 8, or 12 bits +with ex2_p_addr_lwr(60 to 61) select + ex2_beC840_en <= ex2_be10_en(0 to 31) when "00", + x"0" & ex2_be10_en(0 to 27) when "01", + x"00" & ex2_be10_en(0 to 23) when "10", + x"000" & ex2_be10_en(0 to 19) when others; + +-- Selects between Data rotated by 0, 1, 2, or 3 bits +with ex2_p_addr_lwr(62 to 63) select + ex2_be3210_en <= ex2_beC840_en(0 to 31) when "00", + '0' & ex2_beC840_en(0 to 30) when "01", + "00" & ex2_beC840_en(0 to 29) when "10", + "000" & ex2_beC840_en(0 to 28) when others; + +-- Byte Enables Generated using the opsize and physical_addr(60 to 63) +ben_gen : for t in 0 to 31 generate begin + ex2_byte_en(t) <= ex2_opsize(0) or ex2_be3210_en(t); +end generate ben_gen; + +ex3_byte_en_d <= ex2_byte_en; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Reload Rotate Control Logic +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +-- RELOAD PATH LITTLE ENDIAN ROTATOR SELECT CALCULATION +-- rel_rot_size = rot_addr + op_size +-- rel_rot_sel_le = (rot_max_size or le_op_size) - rel_rot_size +-- rel_rot_sel = rel_rot_sel_le => le_mode = 1 +-- = rel_rot_size => le_mode = 0 +ex2_rot_sel_be <= std_ulogic_vector(unsigned(ex2_p_addr_lwr(58 to 63)) + unsigned(ex2_opsize)); +ex2_rot_sel_le <= std_ulogic_vector(unsigned(rot_max_size) - unsigned(ex2_p_addr_lwr(58 to 63))); +ex3_rot_sel_le_d <= ex2_rot_sel_le(1 to 5); +ex3_rot_sel_be_d <= ex2_rot_sel_be(1 to 5); + +-- Rotate Control Select for Reloads +with ex3_data_swap_val select + ex3_rot_sel <= ex3_rot_sel_le_q when '1', + ex3_rot_sel_be_q when others; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- L1 D-Cache Control Logic +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +-- Touch Ops with unsupported TH fields are no-ops +ex1_undef_touch <= (ex1_dcbt_instr_q or ex1_dcblc_instr_q or ex1_dcbtls_instr_q or ex1_dcbtstls_instr_q or ex1_dcbtst_instr_q or + ex1_icbt_l2_instr_q or ex1_icblc_l2_instr_q or ex1_icbtls_l2_instr_q) and not (ex1_th_fld_c_q or ex1_th_fld_l2_q); + +-- Cache Unable to Lock Detection +ex1_lockset_instr <= ex1_dcbtls_instr_q or ex1_dcbtstls_instr_q or ex1_dcblc_instr_q or ex1_icbtls_l2_instr_q or ex1_icblc_l2_instr_q; +ex2_undef_lockset_d <= (ex1_lockset_instr and cache_acc_ex1_q and not (ex1_th_fld_c_q or ex1_th_fld_l2_q)) and not ex1_stg_flush; +ex3_undef_lockset_d <= ex2_undef_lockset_q and not ex2_stg_flush; +ex3_cinh_lockset <= (ex3_dcbtls_instr_q or ex3_dcbtstls_instr_q or ex3_dcblc_instr_q or ex3_icbtls_l2_instr_q or ex3_icblc_l2_instr_q) and ex3_cache_inhibited; +ex3_l1dcdis_lockset <= (ex3_dcbtls_instr_q or ex3_dcbtstls_instr_q or ex3_dcblc_instr_q) and ex3_th_fld_c_q and spr_xucr0_dcdis_q and ex3_cache_enabled; +ex4_unable_2lock_d <= (ex3_undef_lockset_q or ex3_cinh_lockset or ex3_l1dcdis_lockset) and not ex3_stg_flush; +ex5_unable_2lock_d <= ex4_unable_2lock_q and not ex4_stg_flush; + +-- Type of Hit +ex4_store_commit_d <= ex3_store_instr_q and ex3_cache_enabled and not (ex3_stg_flush or ex3_lock_instr_q or ex3_spr_xucr0_flh2l2_q or spr_xucr0_dcdis_q); +ex4_load_commit_d <= ex3_load_type_q and ex3_cache_enabled and not (ex3_stg_flush or ex3_nogpr_upd or spr_xucr0_dcdis_q); +ex4_load_hit <= ex4_load_commit_q and not ex4_miss and cache_acc_ex4_q and not ex4_stg_flush; +ex5_load_hit_d <= ex4_load_type_q and not ex4_miss and cache_acc_ex4_q and not ex4_cache_inh_q and not ex4_stg_flush; + +-- Type of Miss +ex4_store_miss <= ex4_store_instr_q and ex4_miss and cache_acc_ex4_q and not ex4_cache_inh_q; +ex5_store_miss_d <= ex4_store_miss; +ex4_load_miss <= ex4_load_type_q and ex4_miss and cache_acc_ex4_q and not ex4_cache_inh_q; +ex5_load_miss_d <= ex4_load_miss; + +-- Determine if Reload needs to be dropped +ex4_cacheable_linelock_d <= (ex3_dcbtls_instr_q or ex3_dcbtstls_instr_q) and ex3_cache_enabled; +ex4_cache_inh_d <= ex3_wimge_i_bit; +ex5_cache_inh_d <= ex4_cache_inh_q; + +ex3_cache_enabled <= cache_acc_ex3_q and not ex3_wimge_i_bit; +ex3_cache_inhibited <= cache_acc_ex3_q and ex3_wimge_i_bit; + +-- Data Swap Valid +ex3_data_swap_val <= ex3_wimge_e_bit xor ex3_byte_rev_q; + +-- Directory Access Instructions +ex2_dcblc_l1 <= ex2_dcblc_instr_q and ex2_th_fld_c_q; +ddir_acc_instr <= ex2_load_instr_q or ex2_store_instr_q or data_touch_op or ex2_dcblc_l1 or is_inval_op; + +-- Check for load register target match and previous command target match +-- Need to flush if equal and loadmiss + +ex2_targ_match_b1_d <= (ex2_target_gpr_q(1 to 8) = ex1_targ_reg_q) and ex1_targ_vld_q and cache_acc_ex2_q and ex2_load_instr_q and not (ex1_stg_flush or ex2_axu_op_val_q); +ex3_targ_match_b1_d <= ex2_targ_match_b1_q and not ex2_stg_flush; +ex2_targ_match_b2_d <= (ex3_target_gpr_q(1 to 8) = ex1_targ_reg_q) and ex1_targ_vld_q and cache_acc_ex3_q and ex3_load_instr_q and not (ex1_stg_flush or ex3_axu_op_val_q); + +-- Piping down WAW compares for Data Cache Parity Error Recovery +ex5_instr_val_d <= or_reduce(xu_lsu_ex4_val) and not ex4_stg_flush; +ex4_targ_match_b1_d <= ex3_targ_match_b1_q and not ex3_stg_flush; +ex5_targ_match_b1_d <= ex4_targ_match_b1_q and not ex4_stg_flush; +ex6_targ_match_b1_d <= ex5_targ_match_b1_q and ex5_instr_val_q and not ex5_stg_flush; +ex3_targ_match_b2_d <= ex2_targ_match_b2_q and not ex2_stg_flush; +ex4_targ_match_b2_d <= ex3_targ_match_b2_q and not ex3_stg_flush; +ex5_targ_match_b2_d <= ex4_targ_match_b2_q and not ex4_stg_flush; + +-- load_is_in_stage <= WAW_detected_instruction_in_stage +ex7_targ_match_d <= ex5_targ_match_b1_q and ex5_instr_val_q and not ex5_stg_flush; -- latched version of (EX6vsEX5) WAW hazard +ex8_targ_match_d <= ex6_targ_match_b1_q or (ex5_targ_match_b2_q and ex5_instr_val_q and not ex5_stg_flush); -- latched versions of (EX7vsEX6 and EX7vsEX5) WAW hazard + +-- EX2 Data touch ops, DCBT/DCBTST/DCBTLS/DCBTSTLS +data_touch_op <= ex2_dcbt_instr_q or ex2_dcbtst_instr_q or ex2_dcbtls_instr_q or ex2_dcbtstls_instr_q; +-- EX2 Instruction touch ops, ICBT/ICBTLS +inst_touch_op <= ex2_icbt_l2_instr_q or ex2_icbtls_l2_instr_q; +-- Ops that should not update the LRU if a miss or hit +no_lru_upd <= all_touch_op or is_inval_op or ex2_icbi_instr_q or ex2_dcbst_instr_q or ex2_wclr_instr_q or ex2_icblc_l2_instr_q or ex2_dcblc_instr_q; + +-- All requests that go to the L2 no matter if hit +ex3_l2_request_d <= ((ex2_dcbtls_instr_q or ex2_dcbtstls_instr_q) and ex2_th_fld_l2_q) or ex2_icbt_l2_instr_q or ex2_icbtls_l2_instr_q or ex2_lock_instr_q; +ex3_l2_request <= ex3_l2_request_q or ex3_cache_inhibited; + +-- Ops that should not execute if translated to cache-inh +all_touch_op <= data_touch_op or inst_touch_op; +ex2_l2_lock_clr <= (ex2_icblc_l2_instr_q or ex2_dcblc_instr_q) and ex2_th_fld_l2_q; + +-- EX2 HSYNC/LWSYNC/MBAR/TLBSYNC +is_mem_bar_op <= ex2_sync_instr_q or ex2_mbar_instr_q or ex2_tlbsync_instr_q; + +-- EX2 DCBF/DCBI/LWARX/STWCX/DCBZ/FLH2L2_STORE instruction that should invalidate the L1 Directory if there is a Hit +is_inval_op <= ex2_dcbf_instr_q or ex2_dcbi_instr_q or ex2_lock_instr_q or ex2_dcbz_instr_q or (ex2_spr_xucr0_flh2l2 and ex2_store_instr_q) or ex2_icswx_dot_instr_q or ex2_icswx_instr_q or + ex2_icswx_epid_q; + +-- EX2 DCBTLS/DCBTSTLS instruction that should set the Lock bit for the cacheline +is_lock_set <= (ex2_dcbtstls_instr_q or ex2_dcbtls_instr_q) and ex2_th_fld_c_q; +ex3_l2_lock_set <= (ex3_dcbtstls_instr_q or ex3_dcbtls_instr_q) and ex3_th_fld_l2_q; +ex3_c_dcbtls <= ex3_dcbtls_instr_q and ex3_th_fld_c_q; +ex3_c_dcbtstls <= ex3_dcbtstls_instr_q and ex3_th_fld_c_q; +ex3_c_icbtls <= ex3_icbtls_l2_instr_q and ex3_th_fld_c_q; +ex3_l2_dcbtls <= ex3_dcbtls_instr_q and ex3_th_fld_l2_q; +ex3_l2_dcbtstls <= ex3_dcbtstls_instr_q and ex3_th_fld_l2_q; +ex3_l2_icbtls <= ex3_icbtls_l2_instr_q and ex3_th_fld_l2_q; + +-- EX2 DCBLC/DCBF/DCBI/LWARX/STWCX/DCBZ instruction that should clear the Lock bit for the cacheline +is_lock_clr <= (ex2_dcblc_instr_q and ex2_th_fld_c_q) or is_inval_op; + +l2_ctype <= (ex2_store_instr_q or ex2_l2_dcbf or ex2_dcbi_instr_q or ex2_dcbz_instr_q or ex2_dcbst_instr_q or ex2_icbi_instr_q or ex2_icswx_instr_q or + ex2_icswx_dot_instr_q or ex2_icswx_epid_q or ex2_lock_instr_q or all_touch_op or ex2_l2_lock_clr or ex2_load_instr_q) and cache_acc_ex2_q; +ex3_c_inh_drop_op_d <= (all_touch_op or ex2_l2_lock_clr or ex2_local_dcbf) and cache_acc_ex2_q and not ex2_stg_flush; + +ex3_l2_op_d <= (l2_ctype or is_mem_bar_op or ex2_msgsnd_instr_q or ex2_mtspr_trace_q or ex2_dci_instr_q or ex2_ici_instr_q) and not ex2_stg_flush; + +-- Watch Clear if real address matches +ex2_watch_clr_entry <= ex2_wclr_instr_q and ex2_l_fld_q(0); + +-- EX3 local dcbf is special, need to check against loadmiss queue, +-- but dont want to send request to the L2, since this signal does not set +-- ex3_l_s_q_val, need to do an OR statement for setbarr_tid and ex3_n_flush_req +-- in case it hits against the loadmiss queue +ex3_local_dcbf_d <= (ex2_local_dcbf or ex2_watch_clr_entry) and cache_acc_ex2_q and not ex2_stg_flush; + +-- Ops that flow down the Store Queue +-- Load is added since load hits go to the L2 if xucr0[FLH2L2] = 1 +--ex3_stq_instr_d <= (((ex2_store_instr_q or ex2_l2_dcbf or ex2_dcbi_instr_q or ex2_dcbz_instr_q or ex2_dcbst_instr_q or ex2_icbi_instr_q or ex2_icswx_instr_q or ex2_icswx_dot_instr_q or +-- ex2_icswx_epid_q or ex2_icblc_l2_instr_q or ex2_dcblc_instr_q) and cache_acc_ex2_q) or +-- is_mem_bar_op or ex2_msgsnd_instr_q or ex2_mtspr_trace_q or ex2_dci_instr_q or ex2_ici_instr_q) and not ex2_stg_flush; + +ex2_flh2l2_load <= ex2_load_instr_q and ex2_spr_xucr0_flh2l2; + +ex3_ldstq_instr_d <= (((ex2_store_instr_q or ex2_l2_dcbf or ex2_dcbi_instr_q or ex2_dcbz_instr_q or ex2_dcbst_instr_q or ex2_icbi_instr_q or ex2_icswx_instr_q or ex2_icswx_dot_instr_q or + ex2_icswx_epid_q or ex2_l2_lock_clr or ex2_flh2l2_load) and cache_acc_ex2_q) or + is_mem_bar_op or ex2_msgsnd_instr_q or ex2_mtspr_trace_q or ex2_dci_instr_q or ex2_ici_instr_q) and not ex2_stg_flush; + +-- These instructions should not update the register file but are treated as loads +ex3_nogpr_upd <= ex3_dcbt_instr_q or ex3_dcbtst_instr_q or ex3_lock_instr_q or ex3_dcbtls_instr_q or ex3_dcbtstls_instr_q; + +-- Blockable Touches +ex2_blkable_touch_d <= ex1_dcbt_instr_q or ex1_dcbtst_instr_q or ex1_icbt_l2_instr_q or ex1_undef_touch; +ex3_blkable_touch_d <= ex2_blkable_touch_q; +ex3_blk_touch <= ex3_blkable_touch_q and ex3_excp_det; + +-- Inputs to Load/Store Queue +l_s_q_val <= ex3_l2_op_q; +stx_instr <= ex3_store_instr_q and ex3_lock_instr_q; +larx_instr <= ex3_load_instr_q and ex3_lock_instr_q; +ex3_drop_ld <= ex3_load_type_q and not (ex3_l2_lock_set or ex3_lock_instr_q or spr_xucr0_dcdis_q); +ex3_drop_touch_int <= ex3_l2_op_q and (ex3_blk_touch or (ex3_cache_inhibited and ex3_c_inh_drop_op_q)); + +ex3DropCacheB : ex3_drop_cacheable_b <= not (ex3_drop_ld and ex3_cache_enabled); +ex3DropCache : ex3_drop_cacheable <= not ex3_drop_cacheable_b; +ex3DropLd : ex3_drop_ld_req_b <= not ((ex3_hit and ex3_drop_cacheable) or ex3_drop_touch_int); + +-- LoadMiss Store Queue Flushes +-- Removing blockable touch for timing, this should rarely happen, +-- Will be getting a flush if the load_queue_full and its a touch op +-- that will get dropped next time around +--ex3_ldq_potential_flush <= ex3_ld_queue_full and ex3_l2load_type_q and cache_acc_ex3_q and not ex3_blk_touch; +ex3_ldq_potential_flush <= ex3_ld_queue_full and ex3_l2load_type_q and cache_acc_ex3_q; +ex3_stq_full_flush <= ex3_stq_flush and ex3_ldstq_instr_q; +ex3_lsq_ig_flush <= ex3_ig_flush and cache_acc_ex3_q; +ex3_lsq_flush <= ex3_stq_full_flush or ex3_lsq_ig_flush; + +-- Way Locking +with spr_xucr0_wlck_q select + way_lck_rmt <= x"FFFFFFFF" when '0', + xucr2_reg_q when others; + +-- Parity Error Recovery +-- bit(0 ) = cache_inhibit +-- bit(1:6 ) = opsize(0 to 5 ) +-- bit(7:11 ) = rot_sel(0 to 4 ) +-- bit(12:20 ) = target_gpr(0 to 8 ) +-- bit(21 ) = axu_op_val +-- bit(22 ) = little endian mode +-- bit(23 ) = algebraic op +-- bit(24 ) = way lock +-- bit(25 ) = watch enable +-- bit(26:67 ) = ex4_p_addr(22 to 63 ) + +ex4_c_inh_d <= ex3_cache_inhibited; +ex4_opsize_d <= ex3_opsize_q(0 to 5); +ex4_rot_sel_d <= ex3_rot_sel(0 to 4); +ex4_data_swap_val_d <= ex3_data_swap_val; +ex4_algebraic_d <= ex3_algebraic_q; +ex4_lock_en_d <= ex3_dcbtls_instr_q or ex3_dcbtstls_instr_q; + +ex4_ld_entry <= ex4_c_inh_q & ex4_opsize_q & ex4_rot_sel_q & ex4_target_gpr_q & ex4_axu_op_val_q & ex4_data_swap_val_q & ex4_algebraic_q & ex4_lock_en_q & ex4_watch_en_q & ex4_p_addr_q; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Directory Read Control +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +dir_arr_rd_cntrl <= xudbg0_wen & dir_arr_rd_done; + +with dir_arr_rd_cntrl select + dir_arr_rd_val_d <= lsu_slowspr_data_q(62) when "10", + '0' when "01", + dir_arr_rd_val_q when others; + +-- Piping Down Directory Read indicator to match up with need hole request +dir_arr_rd_is0_val_d <= dir_arr_rd_val_q; +dir_arr_rd_is1_val_d <= dir_arr_rd_is0_val_q; +dir_arr_rd_is2_val_d <= dir_arr_rd_is1_val_q; +dir_arr_rd_rf0_val_d <= dir_arr_rd_is2_val_q; +dir_arr_rd_rf1_val_d <= dir_arr_rd_rf0_val_q; + +-- Directory Read is done when there isnt a back-invalidate in same stage +-- Creating a Pulse, dont want to set done indicator for multiple cycles +dir_arr_rd_done <= dir_arr_rd_is2_val_q and not (is2_l2_inv_val or dir_arr_rd_rf0_done_q or dir_arr_rd_rf1_done_q or + dir_arr_rd_ex1_done_q or dir_arr_rd_ex2_done_q); + +-- Piping Down Done indicator to capture directory contents +dir_arr_rd_rf0_done_d <= dir_arr_rd_done; +dir_arr_rd_rf1_done_d <= dir_arr_rd_rf0_done_q; +dir_arr_rd_ex1_done_d <= dir_arr_rd_rf1_done_q; +dir_arr_rd_ex2_done_d <= dir_arr_rd_ex1_done_q; +dir_arr_rd_ex3_done_d <= dir_arr_rd_ex2_done_q; +dir_arr_rd_ex4_done_d <= dir_arr_rd_ex3_done_q; + +-- Done Bit Control +with dir_arr_rd_cntrl select + xudbg0_done_reg_d <= lsu_slowspr_data_q(63) when "10", + '1' when "01", + xudbg0_done_reg_q when others; + +-- Select Tag +with xudbg0_reg_q(0 to 2) select + dir_arr_rd_tag <= ex3_wayA_tag when "000", + ex3_wayB_tag when "001", + ex3_wayC_tag when "010", + ex3_wayD_tag when "011", + ex3_wayE_tag when "100", + ex3_wayF_tag when "101", + ex3_wayG_tag when "110", + ex3_wayH_tag when others; + +-- Select Directory Contents + with xudbg0_reg_q(0 to 2) select + dir_arr_rd_directory <= ex4_way_a_dir when "000", + ex4_way_b_dir when "001", + ex4_way_c_dir when "010", + ex4_way_d_dir when "011", + ex4_way_e_dir when "100", + ex4_way_f_dir when "101", + ex4_way_g_dir when "110", + ex4_way_h_dir when others; + +-- Select Directory Tag Parity + with xudbg0_reg_q(0 to 2) select + dir_arr_rd_parity <= ex3_way_tag_par_a when "000", + ex3_way_tag_par_b when "001", + ex3_way_tag_par_c when "010", + ex3_way_tag_par_d when "011", + ex3_way_tag_par_e when "100", + ex3_way_tag_par_f when "101", + ex3_way_tag_par_g when "110", + ex3_way_tag_par_h when others; + +dir_arr_rd_lru <= ex4_dir_lru; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Slow SPR's +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +lsu_slowspr_val_d <= xu_lsu_slowspr_val; +lsu_slowspr_rw_d <= xu_lsu_slowspr_rw; +lsu_slowspr_etid_d <= xu_lsu_slowspr_etid; +lsu_slowspr_addr_d <= xu_lsu_slowspr_addr; +lsu_slowspr_data_d <= xu_lsu_slowspr_data; +lsu_slowspr_done_d <= xu_lsu_slowspr_done; + +mm_slowspr_val_d <= lsu_slowspr_val_q; +mm_slowspr_rw_d <= lsu_slowspr_rw_q; +mm_slowspr_etid_d <= lsu_slowspr_etid_q; +mm_slowspr_addr_d <= lsu_slowspr_addr_q; + +xucr2_sel <= (lsu_slowspr_addr_q = XUCR2_ADDR); +dvc1_sel <= (lsu_slowspr_addr_q = DVC1_ADDR); +dvc2_sel <= (lsu_slowspr_addr_q = DVC2_ADDR); +eplc_sel <= (lsu_slowspr_addr_q = EPLC_ADDR); +epsc_sel <= (lsu_slowspr_addr_q = EPSC_ADDR); +xudbg0_sel <= (lsu_slowspr_addr_q = XUDBG0_ADDR); +xudbg1_sel <= (lsu_slowspr_addr_q = XUDBG1_ADDR); +xudbg2_sel <= (lsu_slowspr_addr_q = XUDBG2_ADDR); + +-- SLOWSPR Writes + +-- XUCR2 Register +xucr2_wen <= lsu_slowspr_val_q and xucr2_sel and not lsu_slowspr_rw_q; +xucr2_reg_d <= lsu_slowspr_data_q(32 to 63); + +xucr2_reg(32 to 63) <= xucr2_reg_q; + +-- DVC1 Register +dvc1_wen <= lsu_slowspr_val_q and dvc1_sel and not lsu_slowspr_rw_q; +dvc1_act_d <= dvc1_wen; +dvc1_reg_d <= lsu_slowspr_data_q; + +dvc1_reg <= dvc1_reg_q; + +-- DVC2 Register +dvc2_wen <= lsu_slowspr_val_q and dvc2_sel and not lsu_slowspr_rw_q; +dvc2_act_d <= dvc2_wen; +dvc2_reg_d <= lsu_slowspr_data_q; + +dvc2_reg <= dvc2_reg_q; + +-- XUDBG0 Register +xudbg0_wen <= lsu_slowspr_val_q and xudbg0_sel and not (lsu_slowspr_rw_q or dir_arr_rd_val_q); +xudbg0_reg_d <= lsu_slowspr_data_q(49 to 51) & lsu_slowspr_data_q(53 to 57); + +xudbg0_reg(64-(2**regmode) to 48) <= (others=>'0'); +xudbg0_reg(49 to 63) <= xudbg0_reg_q(0 to 2) & '0' & xudbg0_reg_q(3 to 7) & "00000" & xudbg0_done_reg_q; + +-- XUDBG1 Register +xudbg1_dir_reg_d <= dir_arr_rd_directory & dir_arr_rd_lru; +xudbg1_parity_reg_d <= dir_arr_rd_parity; + +xudbg1_reg(64-(2**regmode) to 44) <= (others=>'0'); +xudbg1_reg(45 to 63) <= xudbg1_dir_reg_q(2 to 12) & xudbg1_parity_reg_q & "00" & xudbg1_dir_reg_q(1) & xudbg1_dir_reg_q(0); + +-- XUDBG2 Register +xudbg2_reg_d <= dir_arr_rd_tag; + +xudbg2_reg(32 to 63) <= '0' & xudbg2_reg_q; + +eplc_wrt_data <= lsu_slowspr_data_q(32 to 34) & lsu_slowspr_data_q(40 to 47) & lsu_slowspr_data_q(50 to 63); +epsc_wrt_data <= lsu_slowspr_data_q(32 to 34) & lsu_slowspr_data_q(40 to 47) & lsu_slowspr_data_q(50 to 63); +-- Thread 0 SlowSPR Registers +-- EPLC Register +eplc_t0_wen <= lsu_slowspr_val_q and eplc_sel and not lsu_slowspr_rw_q and (lsu_slowspr_etid_q = "00"); +eplc_t0_hyp_wen <= eplc_t0_wen and hypervisor_state(0); + +eplc_t0_reg_d(0 to 1) <= eplc_wrt_data(0 to 1); +eplc_t0_reg_d(2 to 10) <= eplc_wrt_data(2 to 10); +eplc_t0_reg_d(11 to 24) <= eplc_wrt_data(11 to 24); + +eplc_t0_reg <= eplc_t0_reg_q; + +-- EPSC Register +epsc_t0_wen <= lsu_slowspr_val_q and epsc_sel and not lsu_slowspr_rw_q and (lsu_slowspr_etid_q = "00"); +epsc_t0_hyp_wen <= epsc_t0_wen and hypervisor_state(0); + +epsc_t0_reg_d(0 to 1) <= epsc_wrt_data(0 to 1); +epsc_t0_reg_d(2 to 10) <= epsc_wrt_data(2 to 10); +epsc_t0_reg_d(11 to 24) <= epsc_wrt_data(11 to 24); + +epsc_t0_reg <= epsc_t0_reg_q; + +-- Thread 1 SlowSPR Registers +-- EPLC Register +eplc_t1_wen <= lsu_slowspr_val_q and eplc_sel and not lsu_slowspr_rw_q and (lsu_slowspr_etid_q = "01"); +eplc_t1_hyp_wen <= eplc_t1_wen and hypervisor_state(1); + +eplc_t1_reg_d(0 to 1) <= eplc_wrt_data(0 to 1); +eplc_t1_reg_d(2 to 10) <= eplc_wrt_data(2 to 10); +eplc_t1_reg_d(11 to 24) <= eplc_wrt_data(11 to 24); + +eplc_t1_reg <= eplc_t1_reg_q; + +-- EPSC Register +epsc_t1_wen <= lsu_slowspr_val_q and epsc_sel and not lsu_slowspr_rw_q and (lsu_slowspr_etid_q = "01"); +epsc_t1_hyp_wen <= epsc_t1_wen and hypervisor_state(1); + +epsc_t1_reg_d(0 to 1) <= epsc_wrt_data(0 to 1); +epsc_t1_reg_d(2 to 10) <= epsc_wrt_data(2 to 10); +epsc_t1_reg_d(11 to 24) <= epsc_wrt_data(11 to 24); + +epsc_t1_reg <= epsc_t1_reg_q; + +-- Thread 2 SlowSPR Registers +-- EPLC Register +eplc_t2_wen <= lsu_slowspr_val_q and eplc_sel and not lsu_slowspr_rw_q and (lsu_slowspr_etid_q = "10"); +eplc_t2_hyp_wen <= eplc_t2_wen and hypervisor_state(2); + +eplc_t2_reg_d(0 to 1) <= eplc_wrt_data(0 to 1); +eplc_t2_reg_d(2 to 10) <= eplc_wrt_data(2 to 10); +eplc_t2_reg_d(11 to 24) <= eplc_wrt_data(11 to 24); + +eplc_t2_reg <= eplc_t2_reg_q; + +-- EPSC Register +epsc_t2_wen <= lsu_slowspr_val_q and epsc_sel and not lsu_slowspr_rw_q and (lsu_slowspr_etid_q = "10"); +epsc_t2_hyp_wen <= epsc_t2_wen and hypervisor_state(2); + +epsc_t2_reg_d(0 to 1) <= epsc_wrt_data(0 to 1); +epsc_t2_reg_d(2 to 10) <= epsc_wrt_data(2 to 10); +epsc_t2_reg_d(11 to 24) <= epsc_wrt_data(11 to 24); + +epsc_t2_reg <= epsc_t2_reg_q; + +-- Thread 3 SlowSPR Registers +-- EPLC Register +eplc_t3_wen <= lsu_slowspr_val_q and eplc_sel and not lsu_slowspr_rw_q and (lsu_slowspr_etid_q = "11"); +eplc_t3_hyp_wen <= eplc_t3_wen and hypervisor_state(3); + +eplc_t3_reg_d(0 to 1) <= eplc_wrt_data(0 to 1); +eplc_t3_reg_d(2 to 10) <= eplc_wrt_data(2 to 10); +eplc_t3_reg_d(11 to 24) <= eplc_wrt_data(11 to 24); + +eplc_t3_reg <= eplc_t3_reg_q; + +-- EPSC Register +epsc_t3_wen <= lsu_slowspr_val_q and epsc_sel and not lsu_slowspr_rw_q and (lsu_slowspr_etid_q = "11"); +epsc_t3_hyp_wen <= epsc_t3_wen and hypervisor_state(3); + +epsc_t3_reg_d(0 to 1) <= epsc_wrt_data(0 to 1); +epsc_t3_reg_d(2 to 10) <= epsc_wrt_data(2 to 10); +epsc_t3_reg_d(11 to 24) <= epsc_wrt_data(11 to 24); + +epsc_t3_reg <= epsc_t3_reg_q; + +eplc_wr_d(0 to 3) <= eplc_t0_wen & eplc_t1_wen & eplc_t2_wen & eplc_t3_wen; +epsc_wr_d(0 to 3) <= epsc_t0_wen & epsc_t1_wen & epsc_t2_wen & epsc_t3_wen; + +-- SLOWSPR Read +-- Thread Register Selection +with lsu_slowspr_etid_q select + eplc_thrd_reg <= eplc_t0_reg when "00", + eplc_t1_reg when "01", + eplc_t2_reg when "10", + eplc_t3_reg when others; + +eplc_reg(32 to 63) <= eplc_thrd_reg(0 to 2) & "00000" & eplc_thrd_reg(3 to 10) & "00" & eplc_thrd_reg(11 to 24); + +with lsu_slowspr_etid_q select + epsc_thrd_reg <= epsc_t0_reg when "00", + epsc_t1_reg when "01", + epsc_t2_reg when "10", + epsc_t3_reg when others; + +epsc_reg(32 to 63) <= epsc_thrd_reg(0 to 2) & "00000" & epsc_thrd_reg(3 to 10) & "00" & epsc_thrd_reg(11 to 24); + +gen64mode : if (2**regmode = 64) generate begin + xudbg2_reg(64-(2**REGMODE) to 31) <= (others=>'0'); + eplc_reg(64-(2**REGMODE) to 31) <= (others=>'0'); + epsc_reg(64-(2**REGMODE) to 31) <= (others=>'0'); + xucr2_reg(64-(2**REGMODE) to 31) <= (others=>'0'); +end generate gen64mode; + +-- SlowSPR Selection +spr_l1dc_rd_val <= (xucr2_sel or dvc1_sel or dvc2_sel or eplc_sel or epsc_sel or xudbg0_sel or xudbg1_sel or xudbg2_sel) and lsu_slowspr_val_q and lsu_slowspr_rw_q; +spr_l1dc_reg <= gate(xucr2_reg, xucr2_sel) or gate(dvc1_reg, dvc1_sel) or gate(dvc2_reg, dvc2_sel) or + gate(eplc_reg, eplc_sel) or gate(epsc_reg, epsc_sel) or gate(xudbg0_reg, xudbg0_sel) or + gate(xudbg1_reg, xudbg1_sel) or gate(xudbg2_reg, xudbg2_sel); + +with spr_l1dc_rd_val select + mm_slowspr_data_d <= spr_l1dc_reg when '1', + lsu_slowspr_data_q when others; + +-- Operation Complete +mm_slowspr_done_d <= xucr2_wen or dvc1_wen or dvc2_wen or xudbg0_wen or spr_l1dc_rd_val or lsu_slowspr_done_q; + +-- XXXXXXXXXXXXXXXXXX +-- Register File updates +-- XXXXXXXXXXXXXXXXXX + +rel_upd_gpr_d <= ldq_rel_upd_gpr; +rel_axu_op_val_d <= ldq_rel_axu_val; +rel_thrd_id_d <= ldq_rel_thrd_id; +rel_ta_gpr_d <= ldq_rel_ta_gpr; + +axu_rel_wren_d <= rel_axu_op_val_q; +axu_rel_wren_stg1_d <= axu_rel_wren_q and rel_upd_gpr_q; +rel_axu_tid_d <= rel_thrd_id_q; +rel_axu_tid_stg1_d <= rel_axu_tid_q; +rel_axu_ta_gpr_d <= rel_ta_gpr_q; +rel_axu_ta_gpr_stg1_d <= rel_axu_ta_gpr_q; + +with axu_rel_wren_stg1_q select + reg_upd_thrd_id <= rel_axu_tid_stg1_q when '1', + ex4_thrd_id_q when others; + +with axu_rel_wren_stg1_q select + reg_upd_ta_gpr <= rel_axu_ta_gpr_stg1_q when '1', + ex4_target_gpr_q when others; + +xu_wren <= (ex4_load_hit and not ex4_axu_op_val_q) or ex4_tgpr_instr; +axu_wren <= axu_rel_wren_stg1_q or (ex4_load_hit and ex4_axu_op_val_q) or ex4_taxu_instr; + +ex5_xu_wren_d <= xu_wren; +rel_xu_ta_gpr_d <= rel_ta_gpr_q(1 to 8); + +ex5_axu_rel_val_stg1_d <= axu_rel_wren_q and rel_upd_gpr_q; +ex5_axu_rel_val_stg2_d <= ex5_axu_rel_val_stg1_q; +ex5_axu_wren_d <= gate(reg_upd_thrd_id,axu_wren); +ex5_axu_wren_val <= or_reduce(ex5_axu_wren_q); +ex5_axu_ta_gpr_d <= reg_upd_ta_gpr; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Performance Events +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +perf_com_loadmiss <= cache_acc_ex5_q and ex5_load_instr_q and ex5_load_miss_q and not ex5_stg_flush; +perf_com_loads <= cache_acc_ex5_q and ex5_load_instr_q and not ex5_cache_inh_q and not ex5_stg_flush; +perf_com_cinh_loads <= cache_acc_ex5_q and ex5_load_instr_q and ex5_cache_inh_q and not ex5_stg_flush; +perf_com_dcbt_hit <= cache_acc_ex5_q and ex5_perf_dcbt_q and ex5_load_hit_q and not ex5_stg_flush; +perf_com_dcbt_sent <= cache_acc_ex5_q and ex5_perf_dcbt_q and ex5_load_miss_q and not ex5_stg_flush; +perf_com_axu_load <= cache_acc_ex5_q and ex5_axu_op_val_q and ex5_load_instr_q and not ex5_stg_flush; +perf_com_stores <= cache_acc_ex5_q and ex5_store_instr_q and not ex5_stg_flush; +perf_com_store_miss <= cache_acc_ex5_q and ex5_store_miss_q and not ex5_stg_flush; +perf_com_stcx_exec <= cache_acc_ex5_q and ex5_store_instr_q and ex5_lock_instr_q and not ex5_stg_flush; +perf_com_axu_store <= cache_acc_ex5_q and ex5_axu_op_val_q and ex5_store_instr_q and not ex5_stg_flush; +perf_com_watch_clr <= cache_acc_ex5_q and ex5_wclr_instr_q and not ex5_stg_flush; +perf_com_wclr_lfld <= cache_acc_ex5_q and ex5_wclr_instr_q and ex5_wclr_set_q and not ex5_stg_flush; +perf_com_watch_set <= cache_acc_ex5_q and ex5_watch_en_q and not ex5_stg_flush; + +perf_lsu_events_d <= ex5_thrd_id_q & perf_com_stores & perf_com_store_miss & perf_com_loadmiss & perf_com_cinh_loads & + perf_com_loads & perf_com_dcbt_sent & perf_com_dcbt_hit & perf_com_axu_load & + perf_com_axu_store & perf_com_stcx_exec & perf_com_watch_clr & perf_com_wclr_lfld & + perf_com_watch_set; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Spare Latches +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +my_spare0_latches_d <= not my_spare0_latches_q; +my_spare1_latches_d <= not my_spare1_latches_q; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Execution Pipe Outputs +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +-- Dependency Loadmiss Checking +ex1_src0_vld <= ex1_src0_vld_q and not ex1_stg_flush; +ex1_src0_reg <= ex1_src0_reg_q; +ex1_src1_vld <= ex1_src1_vld_q and not ex1_stg_flush; +ex1_src1_reg <= ex1_src1_reg_q; +ex1_targ_vld <= ex1_targ_vld_q and not ex1_stg_flush; +ex1_targ_reg <= ex1_targ_reg_q; +ex1_check_watch <= gate((ex1_thrd_id_q), (ex1_watch_clr_all or ex1_wchk_instr_q)); + +ex1_lsu_64bit_agen <= ex1_lsu_64bit_agen_q; +ex1_frc_align32 <= ex1_ldst_falign_q and ex1_optype32_q; +ex1_frc_align16 <= ex1_ldst_falign_q and ex1_optype16_q; +ex1_frc_align8 <= ex1_ldst_falign_q and ex1_optype8_q; +ex1_frc_align4 <= ex1_ldst_falign_q and ex1_optype4_q; +ex1_frc_align2 <= ex1_ldst_falign_q and ex1_optype2_q; +ex1_optype1 <= ex1_optype1_q; +ex1_optype2 <= ex1_optype2_q; +ex1_optype4 <= ex1_optype4_q; +ex1_optype8 <= ex1_optype8_q; +ex1_optype16 <= ex1_optype16_q; +ex1_optype32 <= ex1_optype32_q; +ex1_saxu_instr <= ex1_saxu_instr_q; +ex1_sdp_instr <= ex1_sdp_instr_q; +ex1_stgpr_instr <= ex1_sgpr_instr_q or ex1_tgpr_instr_q; +ex1_store_instr <= ex1_store_instr_q; +ex1_axu_op_val <= ex1_axu_op_val_q; +ex2_optype2 <= ex2_optype2_q; +ex2_optype4 <= ex2_optype4_q; +ex2_optype8 <= ex2_optype8_q; +ex2_optype16 <= ex2_optype16_q; +ex2_optype32 <= ex2_optype32_q; +ex2_icswx_type <= ex2_icswx_instr_q or ex2_icswx_dot_instr_q or ex2_icswx_epid_q; +ex2_store_instr <= ex2_store_instr_q and cache_acc_ex2_q; +ex1_dir_acc_val <= ex1_dir_acc_val_q; +ex2_cache_acc <= cache_acc_ex2_q; +ex3_cache_acc <= cache_acc_ex3_q; +ex2_ldst_fexcpt <= ex2_ldst_fexcpt_q; +ex2_axu_op <= ex2_axu_op_val_q; +ex2_mv_reg_op <= ex2_tgpr_instr_q or ex2_taxu_instr_q or ex2_tdp_instr_q; +ex1_thrd_id <= ex1_thrd_id_q; +ex2_thrd_id <= ex2_thrd_id_q; +ex3_thrd_id <= ex3_thrd_id_q; +ex4_thrd_id <= ex4_thrd_id_q; +ex5_thrd_id <= ex5_thrd_id_q; +ex3_targ_match_b1 <= (ex3_targ_match_b1_q and ex4_snd_ld_l2); +ex2_targ_match_b2 <= (ex2_targ_match_b2_q and ex4_snd_ld_l2); +ex2_load_instr <= ex2_load_instr_q; +ex3_dcbt_instr <= ex3_dcbt_instr_q or ex3_c_dcbtls; +ex3_dcbtst_instr <= ex3_dcbtst_instr_q or ex3_c_dcbtstls; +ex3_th_fld_l2 <= ex3_th_fld_l2_q; +ex3_dcbst_instr <= ex3_dcbst_instr_q; +ex3_dcbf_instr <= ex3_dcbf_instr_q; +ex3_sync_instr <= ex3_sync_instr_q; +ex3_mtspr_trace <= ex3_mtspr_trace_q; +ex3_byte_en <= ex3_byte_en_q; +ex2_l_fld <= ex2_l_fld_q; +ex3_l_fld <= ex3_l_fld_q; +ex3_dcbi_instr <= ex3_dcbi_instr_q; +ex2_dcbz_instr <= ex2_dcbz_instr_q; +ex3_dcbz_instr <= ex3_dcbz_instr_q; +ex3_icbi_instr <= ex3_icbi_instr_q; +ex3_icswx_instr <= ex3_icswx_instr_q; +ex3_icswx_dot <= ex3_icswx_dot_instr_q; +ex3_icswx_epid <= ex3_icswx_epid_q; +ex3_mbar_instr <= ex3_mbar_instr_q; +ex3_msgsnd_instr <= ex3_msgsnd_instr_q; +ex3_dci_instr <= ex3_dci_instr_q; +ex3_ici_instr <= ex3_ici_instr_q; +ex2_lock_instr <= ex2_lock_instr_q and cache_acc_ex2_q; +ex3_load_instr <= ex3_l2load_type_q; +ex3_store_instr <= ex3_store_instr_q; +ex3_dcbtls_instr <= ex3_l2_dcbtls; +ex3_dcbtstls_instr <= ex3_l2_dcbtstls; +ex3_dcblc_instr <= ex3_dcblc_instr_q; +ex3_icblc_instr <= ex3_icblc_l2_instr_q; +ex3_icbt_instr <= ex3_icbt_l2_instr_q or ex3_c_icbtls; +ex3_icbtls_instr <= ex3_l2_icbtls; +ex3_tlbsync_instr <= ex3_tlbsync_instr_q; +ex3_local_dcbf <= ex3_local_dcbf_q; +ex2_no_lru_upd <= no_lru_upd; +ex2_is_inval_op <= is_inval_op and cache_acc_ex2_q; +ex2_lock_set <= is_lock_set and cache_acc_ex2_q; +ex2_lock_clr <= is_lock_clr and cache_acc_ex2_q; +ex2_ddir_acc_instr <= ddir_acc_instr and cache_acc_ex2_q and not ex2_stg_flush; +ex3_cache_inh <= ex3_cache_inhibited; +ex3_cache_en <= ex3_cache_enabled; +ex4_store_hit <= ex4_store_commit_q and not ex4_miss; +ex4_load_op_hit <= ex4_load_commit_q and not ex4_miss; +ex5_load_op_hit <= ex5_load_hit_q; +ex4_axu_op_val <= ex4_axu_op_val_q; +ex4_drop_rel <= ex4_cacheable_linelock_q and not ex4_miss; +ex3_load_l1hit <= ex3_load_instr_q and ex3_spr_xucr0_flh2l2_q and ex3_cache_enabled; +ex3_lock_en <= ex3_dcbtls_instr_q or ex3_dcbtstls_instr_q; +ex3_req_thrd_id <= ex3_thrd_id_q; +ex3_target_gpr <= ex3_target_gpr_q; +ex3_axu_op_val <= ex3_axu_op_val_q; +ex3_algebraic <= ex3_algebraic_q; +ex3_p_addr_lwr <= ex3_p_addr_lwr_q(58 to 63); +ex3_opsize <= ex3_opsize_q; +ex3_rotate_sel <= ex3_rot_sel; +ex2_ldawx_instr <= ex2_ldawx_instr_q and cache_acc_ex2_q; +ex2_wclr_instr <= ex2_wclr_instr_q and cache_acc_ex2_q; +ex2_wchk_val <= ex2_wchk_instr_q; +ex3_watch_en <= ex3_watch_en_q; +ex3_data_swap <= ex3_data_swap_val; +ex3_load_val <= ex3_load_instr_q and cache_acc_ex3_q; +ex3_blkable_touch <= ex3_blkable_touch_q and ex3_cacc_q; +ex7_targ_match <= ex7_targ_match_q; +ex8_targ_match <= ex8_targ_match_q; + +rel_upd_dcarr_val <= rel_upd_dcarr_q; + +lsu_xu_need_hole <= dir_arr_rd_val_q; + +spr_dvc1_act <= dvc1_act_q; +spr_dvc2_act <= dvc2_act_q; +spr_dvc1_dbg <= dvc1_reg_q; +spr_dvc2_dbg <= dvc2_reg_q; +spr_xucr2_rmt <= way_lck_rmt; +spr_xucr0_wlck <= spr_xucr0_wlck_cpy_q; + +ex3_l_s_q_val <= l_s_q_val; +ex3_drop_ld_req <= not ex3_drop_ld_req_b; +ex3_drop_touch <= ex3_drop_touch_int; +ex3_stx_instr <= stx_instr; +ex3_larx_instr <= larx_instr; +ex3_mutex_hint <= ex3_mutex_hint_q; + +lsu_xu_ex4_cr_upd <= cache_acc_ex4_q and ex4_watch_en_q; +lsu_xu_ex5_wren <= ex5_xu_wren_q; +lsu_xu_rel_wren <= rel_upd_gpr_q and not axu_rel_wren_q; +lsu_xu_rel_ta_gpr <= rel_xu_ta_gpr_q; +lsu_xu_perf_events <= perf_lsu_events_q; + +slowspr_val_out <= mm_slowspr_val_q; +slowspr_rw_out <= mm_slowspr_rw_q; +slowspr_etid_out <= mm_slowspr_etid_q; +slowspr_addr_out <= mm_slowspr_addr_q; +slowspr_data_out <= mm_slowspr_data_q; +slowspr_done_out <= mm_slowspr_done_q; + +-- Back-Invalidate +rf1_l2_inv_val <= rf1_l2_inv_val_q or dir_arr_rd_rf1_val_q; +ex1_agen_binv_val <= ex1_agen_binv_val_q; +ex1_l2_inv_val <= ex1_l2_inv_val_q; + +xu_derat_epsc_wr <= epsc_wr_q; +xu_derat_eplc_wr <= eplc_wr_q; +xu_derat_eplc0_epr <= eplc_t0_reg_q(0); +xu_derat_eplc0_eas <= eplc_t0_reg_q(1); +xu_derat_eplc0_egs <= eplc_t0_reg_q(2); +xu_derat_eplc0_elpid <= eplc_t0_reg_q(3 to 10); +xu_derat_eplc0_epid <= eplc_t0_reg_q(11 to 24); +xu_derat_eplc1_epr <= eplc_t1_reg_q(0); +xu_derat_eplc1_eas <= eplc_t1_reg_q(1); +xu_derat_eplc1_egs <= eplc_t1_reg_q(2); +xu_derat_eplc1_elpid <= eplc_t1_reg_q(3 to 10); +xu_derat_eplc1_epid <= eplc_t1_reg_q(11 to 24); +xu_derat_eplc2_epr <= eplc_t2_reg_q(0); +xu_derat_eplc2_eas <= eplc_t2_reg_q(1); +xu_derat_eplc2_egs <= eplc_t2_reg_q(2); +xu_derat_eplc2_elpid <= eplc_t2_reg_q(3 to 10); +xu_derat_eplc2_epid <= eplc_t2_reg_q(11 to 24); +xu_derat_eplc3_epr <= eplc_t3_reg_q(0); +xu_derat_eplc3_eas <= eplc_t3_reg_q(1); +xu_derat_eplc3_egs <= eplc_t3_reg_q(2); +xu_derat_eplc3_elpid <= eplc_t3_reg_q(3 to 10); +xu_derat_eplc3_epid <= eplc_t3_reg_q(11 to 24); +xu_derat_epsc0_epr <= epsc_t0_reg_q(0); +xu_derat_epsc0_eas <= epsc_t0_reg_q(1); +xu_derat_epsc0_egs <= epsc_t0_reg_q(2); +xu_derat_epsc0_elpid <= epsc_t0_reg_q(3 to 10); +xu_derat_epsc0_epid <= epsc_t0_reg_q(11 to 24); +xu_derat_epsc1_epr <= epsc_t1_reg_q(0); +xu_derat_epsc1_eas <= epsc_t1_reg_q(1); +xu_derat_epsc1_egs <= epsc_t1_reg_q(2); +xu_derat_epsc1_elpid <= epsc_t1_reg_q(3 to 10); +xu_derat_epsc1_epid <= epsc_t1_reg_q(11 to 24); +xu_derat_epsc2_epr <= epsc_t2_reg_q(0); +xu_derat_epsc2_eas <= epsc_t2_reg_q(1); +xu_derat_epsc2_egs <= epsc_t2_reg_q(2); +xu_derat_epsc2_elpid <= epsc_t2_reg_q(3 to 10); +xu_derat_epsc2_epid <= epsc_t2_reg_q(11 to 24); +xu_derat_epsc3_epr <= epsc_t3_reg_q(0); +xu_derat_epsc3_eas <= epsc_t3_reg_q(1); +xu_derat_epsc3_egs <= epsc_t3_reg_q(2); +xu_derat_epsc3_elpid <= epsc_t3_reg_q(3 to 10); +xu_derat_epsc3_epid <= epsc_t3_reg_q(11 to 24); + +-- Debug Data +dc_cntrl_dbg_data <= rel_upd_gpr_q & rel_ta_gpr_q & rel_axu_op_val_q & spr_xucr0_dcdis_q & --(0:11) + ex4_miss & ex5_axu_ta_gpr_q & is_mem_bar_op & ex3_l2_op_q & --(12:23) + ex1_ldst_falign_q & ex1_ldst_fexcpt_q & ex5_cache_inh_q & ex3_data_swap_val & --(24:27) + ex5_xu_wren_q & ex5_axu_wren_val & ex4_p_addr_q(64-real_data_add to 52) & --(28:60) + ex4_p_addr_q(58 to 61) & ex4_thrd_enc; --(61:66) + +ex1_stg_act <= ex1_stg_act_q; +ex2_stg_act <= ex2_stg_act_q; +ex3_stg_act <= ex3_stg_act_q; +ex4_stg_act <= ex4_stg_act_q; +ex5_stg_act <= ex5_stg_act_q; +binv1_stg_act <= binv1_stg_act_q; +binv2_stg_act <= binv2_stg_act_q; +binv3_stg_act <= binv3_stg_act_q; +binv4_stg_act <= binv4_stg_act_q; +binv5_stg_act <= binv5_stg_act_q; +rel1_stg_act <= rel1_stg_act_q; +rel2_stg_act <= ldq_rel_stg24_val; +rel3_stg_act <= rel3_stg_act_q; + +-- ############################### +-- SPR Outputs +-- ############################### +lsu_xu_spr_xucr0_cul <= ex5_unable_2lock_q; +spr_xucr0_cls <= spr_xucr0_cls_q; +agen_xucr0_cls <= agen_xucr0_cls_q; +dir_arr_rd_is2_val <= dir_arr_rd_is2_val_q; +dir_arr_rd_congr_cl <= xudbg0_reg_q(3 to 7); + +-- ############################### +-- AXU Outputs +-- ############################### +xu_fu_ex5_reload_val <= ex5_axu_rel_val_stg2_q; +xu_fu_ex5_load_val <= ex5_axu_wren_q; +xu_fu_ex5_load_tag <= ex5_axu_ta_gpr_q; + +-- ############################### +-- ICBI Outputs +-- ############################### +xu_iu_ex6_icbi_val <= ex6_icbi_val_q; +xu_iu_ex6_icbi_addr <= ex6_p_addr_q; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Registers +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +ex1_optype1_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_optype1_offset), + scout => sov(ex1_optype1_offset), + din => ex1_optype1_d, + dout => ex1_optype1_q); + +ex1_optype2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_optype2_offset), + scout => sov(ex1_optype2_offset), + din => ex1_optype2_d, + dout => ex1_optype2_q); + +ex1_optype4_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_optype4_offset), + scout => sov(ex1_optype4_offset), + din => ex1_optype4_d, + dout => ex1_optype4_q); + +ex1_optype8_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_optype8_offset), + scout => sov(ex1_optype8_offset), + din => ex1_optype8_d, + dout => ex1_optype8_q); + +ex1_optype16_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_optype16_offset), + scout => sov(ex1_optype16_offset), + din => ex1_optype16_d, + dout => ex1_optype16_q); + +ex1_optype32_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_optype32_offset), + scout => sov(ex1_optype32_offset), + din => ex1_optype32_d, + dout => ex1_optype32_q); + +ex2_optype1_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_optype1_d, + dout(0) => ex2_optype1_q); + +ex2_optype2_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_optype2_d, + dout(0) => ex2_optype2_q); + +ex2_optype4_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_optype4_d, + dout(0) => ex2_optype4_q); + +ex2_optype8_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_optype8_d, + dout(0) => ex2_optype8_q); + +ex2_optype16_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_optype16_d, + dout(0) => ex2_optype16_q); + +ex2_optype32_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_optype32_d, + dout(0) => ex2_optype32_q); + +ex1_dir_acc_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_dir_acc_val_offset), + scout => sov(ex1_dir_acc_val_offset), + din => ex1_dir_acc_val_d, + dout => ex1_dir_acc_val_q); + +cache_acc_ex1_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(cache_acc_ex1_offset), + scout => sov(cache_acc_ex1_offset), + din => cache_acc_ex1_d, + dout => cache_acc_ex1_q); + +cache_acc_ex2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(cache_acc_ex2_offset), + scout => sov(cache_acc_ex2_offset), + din => cache_acc_ex2_d, + dout => cache_acc_ex2_q); + +cache_acc_ex3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(cache_acc_ex3_offset), + scout => sov(cache_acc_ex3_offset), + din => cache_acc_ex3_d, + dout => cache_acc_ex3_q); + +cache_acc_ex4_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(cache_acc_ex4_offset), + scout => sov(cache_acc_ex4_offset), + din => cache_acc_ex4_d, + dout => cache_acc_ex4_q); + +cache_acc_ex5_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(cache_acc_ex5_offset), + scout => sov(cache_acc_ex5_offset), + din => cache_acc_ex5_d, + dout => cache_acc_ex5_q); + +ex2_cacc_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_cacc_offset), + scout => sov(ex2_cacc_offset), + din => ex2_cacc_d, + dout => ex2_cacc_q); + +ex3_cacc_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_cacc_offset), + scout => sov(ex3_cacc_offset), + din => ex3_cacc_d, + dout => ex3_cacc_q); + +ex1_thrd_id_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_thrd_id_offset to ex1_thrd_id_offset + ex1_thrd_id_d'length-1), + scout => sov(ex1_thrd_id_offset to ex1_thrd_id_offset + ex1_thrd_id_d'length-1), + din => ex1_thrd_id_d, + dout => ex1_thrd_id_q); + +ex2_thrd_id_reg: tri_regk +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex2_thrd_id_d, + dout => ex2_thrd_id_q); + +ex3_thrd_id_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_thrd_id_offset to ex3_thrd_id_offset + ex3_thrd_id_d'length-1), + scout => sov(ex3_thrd_id_offset to ex3_thrd_id_offset + ex3_thrd_id_d'length-1), + din => ex3_thrd_id_d, + dout => ex3_thrd_id_q); + +ex4_thrd_id_reg: tri_regk +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex4_thrd_id_d, + dout => ex4_thrd_id_q); + +ex5_thrd_id_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_thrd_id_offset to ex5_thrd_id_offset + ex5_thrd_id_d'length-1), + scout => sov(ex5_thrd_id_offset to ex5_thrd_id_offset + ex5_thrd_id_d'length-1), + din => ex5_thrd_id_d, + dout => ex5_thrd_id_q); + +ex1_target_gpr_reg: tri_rlmreg_p +generic map (width => 9, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_target_gpr_offset to ex1_target_gpr_offset + ex1_target_gpr_d'length-1), + scout => sov(ex1_target_gpr_offset to ex1_target_gpr_offset + ex1_target_gpr_d'length-1), + din => ex1_target_gpr_d, + dout => ex1_target_gpr_q); + +ex2_target_gpr_reg: tri_regk +generic map (width => 9, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex2_target_gpr_d, + dout => ex2_target_gpr_q); + +ex3_target_gpr_reg: tri_rlmreg_p +generic map (width => 9, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_target_gpr_offset to ex3_target_gpr_offset + ex3_target_gpr_d'length-1), + scout => sov(ex3_target_gpr_offset to ex3_target_gpr_offset + ex3_target_gpr_d'length-1), + din => ex3_target_gpr_d, + dout => ex3_target_gpr_q); + +ex4_target_gpr_reg: tri_regk +generic map (width => 9, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex4_target_gpr_d, + dout => ex4_target_gpr_q); + +ex1_dcbt_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_dcbt_instr_offset), + scout => sov(ex1_dcbt_instr_offset), + din => ex1_dcbt_instr_d, + dout => ex1_dcbt_instr_q); + +ex2_dcbt_instr_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_dcbt_instr_d, + dout(0) => ex2_dcbt_instr_q); + +ex3_dcbt_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_dcbt_instr_offset), + scout => sov(ex3_dcbt_instr_offset), + din => ex3_dcbt_instr_d, + dout => ex3_dcbt_instr_q); + +ex1_dcbtst_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_dcbtst_instr_offset), + scout => sov(ex1_dcbtst_instr_offset), + din => ex1_dcbtst_instr_d, + dout => ex1_dcbtst_instr_q); + +ex2_dcbtst_instr_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_dcbtst_instr_d, + dout(0) => ex2_dcbtst_instr_q); + +ex3_dcbtst_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_dcbtst_instr_offset), + scout => sov(ex3_dcbtst_instr_offset), + din => ex3_dcbtst_instr_d, + dout => ex3_dcbtst_instr_q); + +ex1_dcbst_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_dcbst_instr_offset), + scout => sov(ex1_dcbst_instr_offset), + din => ex1_dcbst_instr_d, + dout => ex1_dcbst_instr_q); + +ex2_dcbst_instr_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_dcbst_instr_d, + dout(0) => ex2_dcbst_instr_q); + +ex3_dcbst_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_dcbst_instr_offset), + scout => sov(ex3_dcbst_instr_offset), + din => ex3_dcbst_instr_d, + dout => ex3_dcbst_instr_q); + +ex1_dcbf_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_dcbf_instr_offset), + scout => sov(ex1_dcbf_instr_offset), + din => ex1_dcbf_instr_d, + dout => ex1_dcbf_instr_q); + +ex2_dcbf_instr_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_dcbf_instr_d, + dout(0) => ex2_dcbf_instr_q); + +ex3_dcbf_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_dcbf_instr_offset), + scout => sov(ex3_dcbf_instr_offset), + din => ex3_dcbf_instr_d, + dout => ex3_dcbf_instr_q); + +ex1_sync_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_sync_instr_offset), + scout => sov(ex1_sync_instr_offset), + din => ex1_sync_instr_d, + dout => ex1_sync_instr_q); + +ex2_sync_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_sync_instr_offset), + scout => sov(ex2_sync_instr_offset), + din => ex2_sync_instr_d, + dout => ex2_sync_instr_q); + +ex3_sync_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_sync_instr_offset), + scout => sov(ex3_sync_instr_offset), + din => ex3_sync_instr_d, + dout => ex3_sync_instr_q); + +ex1_l_fld_reg: tri_rlmreg_p +generic map (width => 2, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_l_fld_offset to ex1_l_fld_offset + ex1_l_fld_d'length-1), + scout => sov(ex1_l_fld_offset to ex1_l_fld_offset + ex1_l_fld_d'length-1), + din => ex1_l_fld_d, + dout => ex1_l_fld_q); + +ex2_l_fld_reg: tri_regk +generic map (width => 2, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex2_l_fld_d, + dout => ex2_l_fld_q); + +ex3_l_fld_reg: tri_rlmreg_p +generic map (width => 2, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_l_fld_offset to ex3_l_fld_offset + ex3_l_fld_d'length-1), + scout => sov(ex3_l_fld_offset to ex3_l_fld_offset + ex3_l_fld_d'length-1), + din => ex3_l_fld_d, + dout => ex3_l_fld_q); + +ex1_dcbi_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_dcbi_instr_offset), + scout => sov(ex1_dcbi_instr_offset), + din => ex1_dcbi_instr_d, + dout => ex1_dcbi_instr_q); + +ex2_dcbi_instr_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_dcbi_instr_d, + dout(0) => ex2_dcbi_instr_q); + +ex3_dcbi_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_dcbi_instr_offset), + scout => sov(ex3_dcbi_instr_offset), + din => ex3_dcbi_instr_d, + dout => ex3_dcbi_instr_q); + +ex1_dcbz_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_dcbz_instr_offset), + scout => sov(ex1_dcbz_instr_offset), + din => ex1_dcbz_instr_d, + dout => ex1_dcbz_instr_q); + +ex2_dcbz_instr_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_dcbz_instr_d, + dout(0) => ex2_dcbz_instr_q); + +ex3_dcbz_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_dcbz_instr_offset), + scout => sov(ex3_dcbz_instr_offset), + din => ex3_dcbz_instr_d, + dout => ex3_dcbz_instr_q); + +ex1_icbi_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_icbi_instr_offset), + scout => sov(ex1_icbi_instr_offset), + din => ex1_icbi_instr_d, + dout => ex1_icbi_instr_q); + +ex2_icbi_instr_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_icbi_instr_d, + dout(0) => ex2_icbi_instr_q); + +ex3_icbi_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_icbi_instr_offset), + scout => sov(ex3_icbi_instr_offset), + din => ex3_icbi_instr_d, + dout => ex3_icbi_instr_q); + +ex4_icbi_instr_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex4_icbi_instr_d, + dout(0) => ex4_icbi_instr_q); + +ex5_icbi_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_icbi_instr_offset), + scout => sov(ex5_icbi_instr_offset), + din => ex5_icbi_instr_d, + dout => ex5_icbi_instr_q); + +ex1_mbar_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_mbar_instr_offset), + scout => sov(ex1_mbar_instr_offset), + din => ex1_mbar_instr_d, + dout => ex1_mbar_instr_q); + +ex2_mbar_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_mbar_instr_offset), + scout => sov(ex2_mbar_instr_offset), + din => ex2_mbar_instr_d, + dout => ex2_mbar_instr_q); + +ex3_mbar_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_mbar_instr_offset), + scout => sov(ex3_mbar_instr_offset), + din => ex3_mbar_instr_d, + dout => ex3_mbar_instr_q); + +ex1_algebraic_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_algebraic_offset), + scout => sov(ex1_algebraic_offset), + din => ex1_algebraic_d, + dout => ex1_algebraic_q); + +ex2_algebraic_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_algebraic_d, + dout(0) => ex2_algebraic_q); + +ex3_algebraic_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_algebraic_offset), + scout => sov(ex3_algebraic_offset), + din => ex3_algebraic_d, + dout => ex3_algebraic_q); + +ex1_byte_rev_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_byte_rev_offset), + scout => sov(ex1_byte_rev_offset), + din => ex1_byte_rev_d, + dout => ex1_byte_rev_q); + +ex2_byte_rev_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_byte_rev_d, + dout(0) => ex2_byte_rev_q); + +ex3_byte_rev_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_byte_rev_offset), + scout => sov(ex3_byte_rev_offset), + din => ex3_byte_rev_d, + dout => ex3_byte_rev_q); + +ex1_lock_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_lock_instr_offset), + scout => sov(ex1_lock_instr_offset), + din => ex1_lock_instr_d, + dout => ex1_lock_instr_q); + +ex2_lock_instr_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_lock_instr_d, + dout(0) => ex2_lock_instr_q); + +ex3_lock_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_lock_instr_offset), + scout => sov(ex3_lock_instr_offset), + din => ex3_lock_instr_d, + dout => ex3_lock_instr_q); + +ex4_lock_instr_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex4_lock_instr_d, + dout(0) => ex4_lock_instr_q); + +ex5_lock_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_lock_instr_offset), + scout => sov(ex5_lock_instr_offset), + din => ex5_lock_instr_d, + dout => ex5_lock_instr_q); + +ex1_mutex_hint_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_mutex_hint_offset), + scout => sov(ex1_mutex_hint_offset), + din => ex1_mutex_hint_d, + dout => ex1_mutex_hint_q); + +ex2_mutex_hint_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_mutex_hint_d, + dout(0) => ex2_mutex_hint_q); + +ex3_mutex_hint_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_mutex_hint_offset), + scout => sov(ex3_mutex_hint_offset), + din => ex3_mutex_hint_d, + dout => ex3_mutex_hint_q); + +ex1_load_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_load_instr_offset), + scout => sov(ex1_load_instr_offset), + din => ex1_load_instr_d, + dout => ex1_load_instr_q); + +ex2_load_instr_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_load_instr_d, + dout(0) => ex2_load_instr_q); + +ex3_load_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_load_instr_offset), + scout => sov(ex3_load_instr_offset), + din => ex3_load_instr_d, + dout => ex3_load_instr_q); + +ex4_load_instr_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex4_load_instr_d, + dout(0) => ex4_load_instr_q); + +ex5_load_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_load_instr_offset), + scout => sov(ex5_load_instr_offset), + din => ex5_load_instr_d, + dout => ex5_load_instr_q); + +ex1_store_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_store_instr_offset), + scout => sov(ex1_store_instr_offset), + din => ex1_store_instr_d, + dout => ex1_store_instr_q); + +ex2_store_instr_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_store_instr_d, + dout(0) => ex2_store_instr_q); + +ex3_store_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_store_instr_offset), + scout => sov(ex3_store_instr_offset), + din => ex3_store_instr_d, + dout => ex3_store_instr_q); + +ex3_l2_op_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_l2_op_offset), + scout => sov(ex3_l2_op_offset), + din => ex3_l2_op_d, + dout => ex3_l2_op_q); + +ex4_cache_inh_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex4_cache_inh_d, + dout(0) => ex4_cache_inh_q); + +ex5_cache_inh_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_cache_inh_offset), + scout => sov(ex5_cache_inh_offset), + din => ex5_cache_inh_d, + dout => ex5_cache_inh_q); + +ex3_opsize_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_opsize_offset to ex3_opsize_offset + ex3_opsize_d'length-1), + scout => sov(ex3_opsize_offset to ex3_opsize_offset + ex3_opsize_d'length-1), + din => ex3_opsize_d, + dout => ex3_opsize_q); + +ex1_axu_op_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_axu_op_val_offset), + scout => sov(ex1_axu_op_val_offset), + din => ex1_axu_op_val_d, + dout => ex1_axu_op_val_q); + +ex2_axu_op_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_axu_op_val_d, + dout(0) => ex2_axu_op_val_q); + +ex3_axu_op_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_axu_op_val_offset), + scout => sov(ex3_axu_op_val_offset), + din => ex3_axu_op_val_d, + dout => ex3_axu_op_val_q); + +ex4_axu_op_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex4_axu_op_val_d, + dout(0) => ex4_axu_op_val_q); + +ex5_axu_op_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_axu_op_val_offset), + scout => sov(ex5_axu_op_val_offset), + din => ex5_axu_op_val_d, + dout => ex5_axu_op_val_q); + +rel_upd_gpr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_upd_gpr_offset), + scout => sov(rel_upd_gpr_offset), + din => rel_upd_gpr_d, + dout => rel_upd_gpr_q); + +rel_axu_op_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_axu_op_val_offset), + scout => sov(rel_axu_op_val_offset), + din => rel_axu_op_val_d, + dout => rel_axu_op_val_q); + +rel_thrd_id_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_thrd_id_offset to rel_thrd_id_offset + rel_thrd_id_d'length-1), + scout => sov(rel_thrd_id_offset to rel_thrd_id_offset + rel_thrd_id_d'length-1), + din => rel_thrd_id_d, + dout => rel_thrd_id_q); + +rel_ta_gpr_reg: tri_rlmreg_p +generic map (width => 9, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_ta_gpr_offset to rel_ta_gpr_offset + rel_ta_gpr_d'length-1), + scout => sov(rel_ta_gpr_offset to rel_ta_gpr_offset + rel_ta_gpr_d'length-1), + din => rel_ta_gpr_d, + dout => rel_ta_gpr_q); + +ex4_load_commit_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_load_commit_offset), + scout => sov(ex4_load_commit_offset), + din => ex4_load_commit_d, + dout => ex4_load_commit_q); + +ex5_load_hit_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_load_hit_offset), + scout => sov(ex5_load_hit_offset), + din => ex5_load_hit_d, + dout => ex5_load_hit_q); + +ex5_axu_rel_val_stg1_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_axu_rel_val_stg1_offset), + scout => sov(ex5_axu_rel_val_stg1_offset), + din => ex5_axu_rel_val_stg1_d, + dout => ex5_axu_rel_val_stg1_q); + +ex5_axu_rel_val_stg2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_axu_rel_val_stg2_offset), + scout => sov(ex5_axu_rel_val_stg2_offset), + din => ex5_axu_rel_val_stg2_d, + dout => ex5_axu_rel_val_stg2_q); + +ex5_axu_wren_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_axu_wren_offset to ex5_axu_wren_offset + ex5_axu_wren_d'length-1), + scout => sov(ex5_axu_wren_offset to ex5_axu_wren_offset + ex5_axu_wren_d'length-1), + din => ex5_axu_wren_d, + dout => ex5_axu_wren_q); + +ex5_axu_ta_gpr_reg: tri_rlmreg_p +generic map (width => 9, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel4_ex4_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_axu_ta_gpr_offset to ex5_axu_ta_gpr_offset + ex5_axu_ta_gpr_d'length-1), + scout => sov(ex5_axu_ta_gpr_offset to ex5_axu_ta_gpr_offset + ex5_axu_ta_gpr_d'length-1), + din => ex5_axu_ta_gpr_d, + dout => ex5_axu_ta_gpr_q); + +rel_xu_ta_gpr_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ldq_rel_stg24_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_xu_ta_gpr_offset to rel_xu_ta_gpr_offset + rel_xu_ta_gpr_d'length-1), + scout => sov(rel_xu_ta_gpr_offset to rel_xu_ta_gpr_offset + rel_xu_ta_gpr_d'length-1), + din => rel_xu_ta_gpr_d, + dout => rel_xu_ta_gpr_q); + +lsu_slowspr_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(lsu_slowspr_val_offset), + scout => sov(lsu_slowspr_val_offset), + din => lsu_slowspr_val_d, + dout => lsu_slowspr_val_q); + +lsu_slowspr_rw_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_lsu_slowspr_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(lsu_slowspr_rw_offset), + scout => sov(lsu_slowspr_rw_offset), + din => lsu_slowspr_rw_d, + dout => lsu_slowspr_rw_q); + +lsu_slowspr_etid_reg: tri_rlmreg_p +generic map (width => 2, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_lsu_slowspr_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(lsu_slowspr_etid_offset to lsu_slowspr_etid_offset + lsu_slowspr_etid_d'length-1), + scout => sov(lsu_slowspr_etid_offset to lsu_slowspr_etid_offset + lsu_slowspr_etid_d'length-1), + din => lsu_slowspr_etid_d, + dout => lsu_slowspr_etid_q); + +lsu_slowspr_addr_reg: tri_rlmreg_p +generic map (width => 10, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_lsu_slowspr_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(lsu_slowspr_addr_offset to lsu_slowspr_addr_offset + lsu_slowspr_addr_d'length-1), + scout => sov(lsu_slowspr_addr_offset to lsu_slowspr_addr_offset + lsu_slowspr_addr_d'length-1), + din => lsu_slowspr_addr_d, + dout => lsu_slowspr_addr_q); + +lsu_slowspr_data_reg: tri_rlmreg_p +generic map (width => 2**REGMODE, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xu_lsu_slowspr_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(lsu_slowspr_data_offset to lsu_slowspr_data_offset + lsu_slowspr_data_d'length-1), + scout => sov(lsu_slowspr_data_offset to lsu_slowspr_data_offset + lsu_slowspr_data_d'length-1), + din => lsu_slowspr_data_d, + dout => lsu_slowspr_data_q); + +lsu_slowspr_done_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(lsu_slowspr_done_offset), + scout => sov(lsu_slowspr_done_offset), + din => lsu_slowspr_done_d, + dout => lsu_slowspr_done_q); + +mm_slowspr_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(mm_slowspr_val_offset), + scout => sov(mm_slowspr_val_offset), + din => mm_slowspr_val_d, + dout => mm_slowspr_val_q); + +mm_slowspr_rw_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lsu_slowspr_val_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(mm_slowspr_rw_offset), + scout => sov(mm_slowspr_rw_offset), + din => mm_slowspr_rw_d, + dout => mm_slowspr_rw_q); + +mm_slowspr_etid_reg: tri_rlmreg_p +generic map (width => 2, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lsu_slowspr_val_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(mm_slowspr_etid_offset to mm_slowspr_etid_offset + mm_slowspr_etid_d'length-1), + scout => sov(mm_slowspr_etid_offset to mm_slowspr_etid_offset + mm_slowspr_etid_d'length-1), + din => mm_slowspr_etid_d, + dout => mm_slowspr_etid_q); + +mm_slowspr_addr_reg: tri_rlmreg_p +generic map (width => 10, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lsu_slowspr_val_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(mm_slowspr_addr_offset to mm_slowspr_addr_offset + mm_slowspr_addr_d'length-1), + scout => sov(mm_slowspr_addr_offset to mm_slowspr_addr_offset + mm_slowspr_addr_d'length-1), + din => mm_slowspr_addr_d, + dout => mm_slowspr_addr_q); + +mm_slowspr_data_reg: tri_rlmreg_p +generic map (width => 2**REGMODE, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lsu_slowspr_val_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(mm_slowspr_data_offset to mm_slowspr_data_offset + mm_slowspr_data_d'length-1), + scout => sov(mm_slowspr_data_offset to mm_slowspr_data_offset + mm_slowspr_data_d'length-1), + din => mm_slowspr_data_d, + dout => mm_slowspr_data_q); + +mm_slowspr_done_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(mm_slowspr_done_offset), + scout => sov(mm_slowspr_done_offset), + din => mm_slowspr_done_d, + dout => mm_slowspr_done_q); + +ex1_th_fld_c_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_th_fld_c_offset), + scout => sov(ex1_th_fld_c_offset), + din => ex1_th_fld_c_d, + dout => ex1_th_fld_c_q); + +ex2_th_fld_c_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_th_fld_c_d, + dout(0) => ex2_th_fld_c_q); + +ex3_th_fld_c_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_th_fld_c_offset), + scout => sov(ex3_th_fld_c_offset), + din => ex3_th_fld_c_d, + dout => ex3_th_fld_c_q); + +ex1_th_fld_l2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_th_fld_l2_offset), + scout => sov(ex1_th_fld_l2_offset), + din => ex1_th_fld_l2_d, + dout => ex1_th_fld_l2_q); + +ex2_th_fld_l2_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_th_fld_l2_d, + dout(0) => ex2_th_fld_l2_q); + +ex3_th_fld_l2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_th_fld_l2_offset), + scout => sov(ex3_th_fld_l2_offset), + din => ex3_th_fld_l2_d, + dout => ex3_th_fld_l2_q); + +ex1_dcbtls_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_dcbtls_instr_offset), + scout => sov(ex1_dcbtls_instr_offset), + din => ex1_dcbtls_instr_d, + dout => ex1_dcbtls_instr_q); + +ex2_dcbtls_instr_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_dcbtls_instr_d, + dout(0) => ex2_dcbtls_instr_q); + +ex3_dcbtls_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_dcbtls_instr_offset), + scout => sov(ex3_dcbtls_instr_offset), + din => ex3_dcbtls_instr_d, + dout => ex3_dcbtls_instr_q); + +ex3_l2_request_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_l2_request_offset), + scout => sov(ex3_l2_request_offset), + din => ex3_l2_request_d, + dout => ex3_l2_request_q); + +ex1_dcbtstls_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_dcbtstls_instr_offset), + scout => sov(ex1_dcbtstls_instr_offset), + din => ex1_dcbtstls_instr_d, + dout => ex1_dcbtstls_instr_q); + +ex2_dcbtstls_instr_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_dcbtstls_instr_d, + dout(0) => ex2_dcbtstls_instr_q); + +ex3_dcbtstls_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_dcbtstls_instr_offset), + scout => sov(ex3_dcbtstls_instr_offset), + din => ex3_dcbtstls_instr_d, + dout => ex3_dcbtstls_instr_q); + +ex1_dcblc_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_dcblc_instr_offset), + scout => sov(ex1_dcblc_instr_offset), + din => ex1_dcblc_instr_d, + dout => ex1_dcblc_instr_q); + +ex2_dcblc_instr_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_dcblc_instr_d, + dout(0) => ex2_dcblc_instr_q); + +ex3_dcblc_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_dcblc_instr_offset), + scout => sov(ex3_dcblc_instr_offset), + din => ex3_dcblc_instr_d, + dout => ex3_dcblc_instr_q); + +ex1_icblc_l2_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_icblc_l2_instr_offset), + scout => sov(ex1_icblc_l2_instr_offset), + din => ex1_icblc_l2_instr_d, + dout => ex1_icblc_l2_instr_q); + +ex2_icblc_l2_instr_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_icblc_l2_instr_d, + dout(0) => ex2_icblc_l2_instr_q); + +ex3_icblc_l2_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_icblc_l2_instr_offset), + scout => sov(ex3_icblc_l2_instr_offset), + din => ex3_icblc_l2_instr_d, + dout => ex3_icblc_l2_instr_q); + +ex1_icbt_l2_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_icbt_l2_instr_offset), + scout => sov(ex1_icbt_l2_instr_offset), + din => ex1_icbt_l2_instr_d, + dout => ex1_icbt_l2_instr_q); + +ex2_icbt_l2_instr_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_icbt_l2_instr_d, + dout(0) => ex2_icbt_l2_instr_q); + +ex3_icbt_l2_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_icbt_l2_instr_offset), + scout => sov(ex3_icbt_l2_instr_offset), + din => ex3_icbt_l2_instr_d, + dout => ex3_icbt_l2_instr_q); + +ex1_icbtls_l2_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_icbtls_l2_instr_offset), + scout => sov(ex1_icbtls_l2_instr_offset), + din => ex1_icbtls_l2_instr_d, + dout => ex1_icbtls_l2_instr_q); + +ex2_icbtls_l2_instr_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_icbtls_l2_instr_d, + dout(0) => ex2_icbtls_l2_instr_q); + +ex3_icbtls_l2_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_icbtls_l2_instr_offset), + scout => sov(ex3_icbtls_l2_instr_offset), + din => ex3_icbtls_l2_instr_d, + dout => ex3_icbtls_l2_instr_q); + +ex1_tlbsync_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_tlbsync_instr_offset), + scout => sov(ex1_tlbsync_instr_offset), + din => ex1_tlbsync_instr_d, + dout => ex1_tlbsync_instr_q); + +ex2_tlbsync_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_tlbsync_instr_offset), + scout => sov(ex2_tlbsync_instr_offset), + din => ex2_tlbsync_instr_d, + dout => ex2_tlbsync_instr_q); + +ex3_tlbsync_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_tlbsync_instr_offset), + scout => sov(ex3_tlbsync_instr_offset), + din => ex3_tlbsync_instr_d, + dout => ex3_tlbsync_instr_q); + +ex1_src0_vld_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_src0_vld_offset), + scout => sov(ex1_src0_vld_offset), + din => ex1_src0_vld_d, + dout => ex1_src0_vld_q); + +ex1_src0_reg_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_src0_reg_offset to ex1_src0_reg_offset + ex1_src0_reg_d'length-1), + scout => sov(ex1_src0_reg_offset to ex1_src0_reg_offset + ex1_src0_reg_d'length-1), + din => ex1_src0_reg_d, + dout => ex1_src0_reg_q); + +ex1_src1_vld_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_src1_vld_offset), + scout => sov(ex1_src1_vld_offset), + din => ex1_src1_vld_d, + dout => ex1_src1_vld_q); + +ex1_src1_reg_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_src1_reg_offset to ex1_src1_reg_offset + ex1_src1_reg_d'length-1), + scout => sov(ex1_src1_reg_offset to ex1_src1_reg_offset + ex1_src1_reg_d'length-1), + din => ex1_src1_reg_d, + dout => ex1_src1_reg_q); + +ex1_targ_vld_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_targ_vld_offset), + scout => sov(ex1_targ_vld_offset), + din => ex1_targ_vld_d, + dout => ex1_targ_vld_q); + +ex1_targ_reg_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_targ_reg_offset to ex1_targ_reg_offset + ex1_targ_reg_d'length-1), + scout => sov(ex1_targ_reg_offset to ex1_targ_reg_offset + ex1_targ_reg_d'length-1), + din => ex1_targ_reg_d, + dout => ex1_targ_reg_q); + +ex5_instr_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_instr_val_offset), + scout => sov(ex5_instr_val_offset), + din => ex5_instr_val_d, + dout => ex5_instr_val_q); + +ex2_targ_match_b1_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_targ_match_b1_offset), + scout => sov(ex2_targ_match_b1_offset), + din => ex2_targ_match_b1_d, + dout => ex2_targ_match_b1_q); + +ex3_targ_match_b1_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_targ_match_b1_offset), + scout => sov(ex3_targ_match_b1_offset), + din => ex3_targ_match_b1_d, + dout => ex3_targ_match_b1_q); + +ex4_targ_match_b1_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_targ_match_b1_offset), + scout => sov(ex4_targ_match_b1_offset), + din => ex4_targ_match_b1_d, + dout => ex4_targ_match_b1_q); + +ex5_targ_match_b1_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_targ_match_b1_offset), + scout => sov(ex5_targ_match_b1_offset), + din => ex5_targ_match_b1_d, + dout => ex5_targ_match_b1_q); + +ex6_targ_match_b1_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_targ_match_b1_offset), + scout => sov(ex6_targ_match_b1_offset), + din => ex6_targ_match_b1_d, + dout => ex6_targ_match_b1_q); + +ex2_targ_match_b2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_targ_match_b2_offset), + scout => sov(ex2_targ_match_b2_offset), + din => ex2_targ_match_b2_d, + dout => ex2_targ_match_b2_q); + +ex3_targ_match_b2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_targ_match_b2_offset), + scout => sov(ex3_targ_match_b2_offset), + din => ex3_targ_match_b2_d, + dout => ex3_targ_match_b2_q); + +ex4_targ_match_b2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_targ_match_b2_offset), + scout => sov(ex4_targ_match_b2_offset), + din => ex4_targ_match_b2_d, + dout => ex4_targ_match_b2_q); + +ex5_targ_match_b2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_targ_match_b2_offset), + scout => sov(ex5_targ_match_b2_offset), + din => ex5_targ_match_b2_d, + dout => ex5_targ_match_b2_q); + +ex7_targ_match_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex7_targ_match_offset), + scout => sov(ex7_targ_match_offset), + din => ex7_targ_match_d, + dout => ex7_targ_match_q); + +ex8_targ_match_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex8_targ_match_offset), + scout => sov(ex8_targ_match_offset), + din => ex8_targ_match_d, + dout => ex8_targ_match_q); + +ex1_ldst_falign_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_ldst_falign_offset), + scout => sov(ex1_ldst_falign_offset), + din => ex1_ldst_falign_d, + dout => ex1_ldst_falign_q); + +ex1_ldst_fexcpt_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_ldst_fexcpt_offset), + scout => sov(ex1_ldst_fexcpt_offset), + din => ex1_ldst_fexcpt_d, + dout => ex1_ldst_fexcpt_q); + +ex2_ldst_fexcpt_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_ldst_fexcpt_d, + dout(0) => ex2_ldst_fexcpt_q); + +ex5_load_miss_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_load_miss_offset), + scout => sov(ex5_load_miss_offset), + din => ex5_load_miss_d, + dout => ex5_load_miss_q); + +xucr2_reg_a_reg : tri_ser_rlmreg_p +generic map (width => 16, init => 65535, expand_type => expand_type, needs_sreset => 1) +port map(vd => vdd, + gd => gnd, + nclk => nclk, + act => xucr2_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xucr2_reg_a_offset to xucr2_reg_a_offset + ((xucr2_reg_d'length)/2)-1), + scout => sov(xucr2_reg_a_offset to xucr2_reg_a_offset + ((xucr2_reg_d'length)/2)-1), + din => xucr2_reg_d(0 to 15), + dout => xucr2_reg_q(0 to 15)); + +xucr2_reg_b_reg: tri_ser_rlmreg_p +generic map (width => 16, init => 65535, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xucr2_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xucr2_reg_b_offset to xucr2_reg_b_offset + ((xucr2_reg_d'length)/2)-1), + scout => sov(xucr2_reg_b_offset to xucr2_reg_b_offset + ((xucr2_reg_d'length)/2)-1), + din => xucr2_reg_d(16 to 31), + dout => xucr2_reg_q(16 to 31)); + +dvc1_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dvc1_act_offset), + scout => sov(dvc1_act_offset), + din => dvc1_act_d, + dout => dvc1_act_q); + +dvc2_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dvc2_act_offset), + scout => sov(dvc2_act_offset), + din => dvc2_act_d, + dout => dvc2_act_q); + +dvc1_reg_reg: tri_ser_rlmreg_p +generic map (width => (2**REGMODE), init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dvc1_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dvc1_reg_offset to dvc1_reg_offset + dvc1_reg_d'length-1), + scout => sov(dvc1_reg_offset to dvc1_reg_offset + dvc1_reg_d'length-1), + din => dvc1_reg_d, + dout => dvc1_reg_q); + +dvc2_reg_reg: tri_ser_rlmreg_p +generic map (width => (2**REGMODE), init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dvc2_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dvc2_reg_offset to dvc2_reg_offset + dvc2_reg_d'length-1), + scout => sov(dvc2_reg_offset to dvc2_reg_offset + dvc2_reg_d'length-1), + din => dvc2_reg_d, + dout => dvc2_reg_q); + +xudbg0_reg_reg: tri_ser_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => xudbg0_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xudbg0_reg_offset to xudbg0_reg_offset + xudbg0_reg_d'length-1), + scout => sov(xudbg0_reg_offset to xudbg0_reg_offset + xudbg0_reg_d'length-1), + din => xudbg0_reg_d, + dout => xudbg0_reg_q); + +xudbg0_done_reg_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xudbg0_done_reg_offset), + scout => sov(xudbg0_done_reg_offset), + din => xudbg0_done_reg_d, + dout => xudbg0_done_reg_q); + +xudbg1_dir_reg_reg: tri_ser_rlmreg_p +generic map (width => 13, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_arr_rd_ex4_done_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xudbg1_dir_reg_offset to xudbg1_dir_reg_offset + xudbg1_dir_reg_d'length-1), + scout => sov(xudbg1_dir_reg_offset to xudbg1_dir_reg_offset + xudbg1_dir_reg_d'length-1), + din => xudbg1_dir_reg_d, + dout => xudbg1_dir_reg_q); + +xudbg1_parity_reg_reg: tri_ser_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_arr_rd_ex3_done_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xudbg1_parity_reg_offset to xudbg1_parity_reg_offset + xudbg1_parity_reg_d'length-1), + scout => sov(xudbg1_parity_reg_offset to xudbg1_parity_reg_offset + xudbg1_parity_reg_d'length-1), + din => xudbg1_parity_reg_d, + dout => xudbg1_parity_reg_q); + +xudbg2_reg_reg: tri_ser_rlmreg_p +generic map (width => 31, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => dir_arr_rd_ex3_done_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xudbg2_reg_offset to xudbg2_reg_offset + xudbg2_reg_d'length-1), + scout => sov(xudbg2_reg_offset to xudbg2_reg_offset + xudbg2_reg_d'length-1), + din => xudbg2_reg_d, + dout => xudbg2_reg_q); + +ex4_store_commit_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_store_commit_offset), + scout => sov(ex4_store_commit_offset), + din => ex4_store_commit_d, + dout => ex4_store_commit_q); + +ex1_sgpr_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_sgpr_instr_offset), + scout => sov(ex1_sgpr_instr_offset), + din => ex1_sgpr_instr_d, + dout => ex1_sgpr_instr_q); + +ex1_saxu_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_saxu_instr_offset), + scout => sov(ex1_saxu_instr_offset), + din => ex1_saxu_instr_d, + dout => ex1_saxu_instr_q); + +ex1_sdp_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_sdp_instr_offset), + scout => sov(ex1_sdp_instr_offset), + din => ex1_sdp_instr_d, + dout => ex1_sdp_instr_q); + +ex1_tgpr_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_tgpr_instr_offset), + scout => sov(ex1_tgpr_instr_offset), + din => ex1_tgpr_instr_d, + dout => ex1_tgpr_instr_q); + +ex1_taxu_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_taxu_instr_offset), + scout => sov(ex1_taxu_instr_offset), + din => ex1_taxu_instr_d, + dout => ex1_taxu_instr_q); + +ex1_tdp_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_tdp_instr_offset), + scout => sov(ex1_tdp_instr_offset), + din => ex1_tdp_instr_d, + dout => ex1_tdp_instr_q); + +ex2_tgpr_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_tgpr_instr_offset), + scout => sov(ex2_tgpr_instr_offset), + din => ex2_tgpr_instr_d, + dout => ex2_tgpr_instr_q); + +ex2_taxu_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_taxu_instr_offset), + scout => sov(ex2_taxu_instr_offset), + din => ex2_taxu_instr_d, + dout => ex2_taxu_instr_q); + +ex2_tdp_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_tdp_instr_offset), + scout => sov(ex2_tdp_instr_offset), + din => ex2_tdp_instr_d, + dout => ex2_tdp_instr_q); + +ex3_tgpr_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_tgpr_instr_offset), + scout => sov(ex3_tgpr_instr_offset), + din => ex3_tgpr_instr_d, + dout => ex3_tgpr_instr_q); + +ex3_taxu_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_taxu_instr_offset), + scout => sov(ex3_taxu_instr_offset), + din => ex3_taxu_instr_d, + dout => ex3_taxu_instr_q); + +ex4_tgpr_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_tgpr_instr_offset), + scout => sov(ex4_tgpr_instr_offset), + din => ex4_tgpr_instr_d, + dout => ex4_tgpr_instr_q); + +ex4_taxu_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_taxu_instr_offset), + scout => sov(ex4_taxu_instr_offset), + din => ex4_taxu_instr_d, + dout => ex4_taxu_instr_q); + +ex2_blkable_touch_reg: tri_regk +generic map (width => 1,init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_blkable_touch_d, + dout(0) => ex2_blkable_touch_q); + +ex3_blkable_touch_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_blkable_touch_offset), + scout => sov(ex3_blkable_touch_offset), + din => ex3_blkable_touch_d, + dout => ex3_blkable_touch_q); + +ex3_p_addr_lwr_reg: tri_rlmreg_p +generic map (width => 12, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_p_addr_lwr_offset to ex3_p_addr_lwr_offset + ex3_p_addr_lwr_d'length-1), + scout => sov(ex3_p_addr_lwr_offset to ex3_p_addr_lwr_offset + ex3_p_addr_lwr_d'length-1), + din => ex3_p_addr_lwr_d, + dout => ex3_p_addr_lwr_q); + +ex4_p_addr_reg: tri_regk +generic map (width => real_data_add, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex4_p_addr_d, + dout => ex4_p_addr_q); + +ex5_p_addr_reg: tri_rlmreg_p +generic map (width => real_data_add-6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_p_addr_offset to ex5_p_addr_offset + ex5_p_addr_d'length-1), + scout => sov(ex5_p_addr_offset to ex5_p_addr_offset + ex5_p_addr_d'length-1), + din => ex5_p_addr_d, + dout => ex5_p_addr_q); + +ex6_p_addr_reg: tri_regk +generic map (width => real_data_add-6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex5_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex6_p_addr_d, + dout => ex6_p_addr_q); + +ex4_c_inh_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex4_c_inh_d, + dout(0) => ex4_c_inh_q); + +ex4_opsize_reg: tri_regk +generic map (width => ex4_opsize_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex4_opsize_d, + dout => ex4_opsize_q); + +ex4_rot_sel_reg: tri_regk +generic map (width => ex4_rot_sel_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex4_rot_sel_d, + dout => ex4_rot_sel_q); + +ex4_data_swap_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex4_data_swap_val_d, + dout(0) => ex4_data_swap_val_q); + +ex4_algebraic_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex4_algebraic_d, + dout(0) => ex4_algebraic_q); + +ex4_lock_en_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex4_lock_en_d, + dout(0) => ex4_lock_en_q); + +eplc_wr_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(eplc_wr_offset to eplc_wr_offset + eplc_wr_d'length-1), + scout => sov(eplc_wr_offset to eplc_wr_offset + eplc_wr_d'length-1), + din => eplc_wr_d, + dout => eplc_wr_q); + +epsc_wr_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(epsc_wr_offset to epsc_wr_offset + epsc_wr_d'length-1), + scout => sov(epsc_wr_offset to epsc_wr_offset + epsc_wr_d'length-1), + din => epsc_wr_d, + dout => epsc_wr_q); + +eplc_t0_reg_a_reg: tri_ser_rlmreg_p +generic map (width => 2, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => eplc_t0_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(eplc_t0_reg_a_offset to eplc_t0_reg_a_offset + (eplc_t0_reg_d'length-23)-1), + scout => sov(eplc_t0_reg_a_offset to eplc_t0_reg_a_offset + (eplc_t0_reg_d'length-23)-1), + din => eplc_t0_reg_d(0 to 1), + dout => eplc_t0_reg_q(0 to 1)); + +eplc_t0_reg_b_reg: tri_ser_rlmreg_p +generic map (width => 9, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => eplc_t0_hyp_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(eplc_t0_reg_b_offset to eplc_t0_reg_b_offset + (eplc_t0_reg_d'length-16)-1), + scout => sov(eplc_t0_reg_b_offset to eplc_t0_reg_b_offset + (eplc_t0_reg_d'length-16)-1), + din => eplc_t0_reg_d(2 to 10), + dout => eplc_t0_reg_q(2 to 10)); + +eplc_t0_reg_c_reg: tri_ser_rlmreg_p +generic map (width => 14, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => eplc_t0_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(eplc_t0_reg_c_offset to eplc_t0_reg_c_offset + (eplc_t0_reg_d'length-11)-1), + scout => sov(eplc_t0_reg_c_offset to eplc_t0_reg_c_offset + (eplc_t0_reg_d'length-11)-1), + din => eplc_t0_reg_d(11 to 24), + dout => eplc_t0_reg_q(11 to 24)); + +eplc_t1_reg_a_reg: tri_ser_rlmreg_p +generic map (width => 2, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => eplc_t1_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(eplc_t1_reg_a_offset to eplc_t1_reg_a_offset + (eplc_t1_reg_d'length-23)-1), + scout => sov(eplc_t1_reg_a_offset to eplc_t1_reg_a_offset + (eplc_t1_reg_d'length-23)-1), + din => eplc_t1_reg_d(0 to 1), + dout => eplc_t1_reg_q(0 to 1)); + +eplc_t1_reg_b_reg: tri_ser_rlmreg_p +generic map (width => 9, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => eplc_t1_hyp_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(eplc_t1_reg_b_offset to eplc_t1_reg_b_offset + (eplc_t1_reg_d'length-16)-1), + scout => sov(eplc_t1_reg_b_offset to eplc_t1_reg_b_offset + (eplc_t1_reg_d'length-16)-1), + din => eplc_t1_reg_d(2 to 10), + dout => eplc_t1_reg_q(2 to 10)); + +eplc_t1_reg_c_reg: tri_ser_rlmreg_p +generic map (width => 14, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => eplc_t1_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(eplc_t1_reg_c_offset to eplc_t1_reg_c_offset + (eplc_t1_reg_d'length-11)-1), + scout => sov(eplc_t1_reg_c_offset to eplc_t1_reg_c_offset + (eplc_t1_reg_d'length-11)-1), + din => eplc_t1_reg_d(11 to 24), + dout => eplc_t1_reg_q(11 to 24)); + +eplc_t2_reg_a_reg: tri_ser_rlmreg_p +generic map (width => 2, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => eplc_t2_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(eplc_t2_reg_a_offset to eplc_t2_reg_a_offset + (eplc_t2_reg_d'length-23)-1), + scout => sov(eplc_t2_reg_a_offset to eplc_t2_reg_a_offset + (eplc_t2_reg_d'length-23)-1), + din => eplc_t2_reg_d(0 to 1), + dout => eplc_t2_reg_q(0 to 1)); + +eplc_t2_reg_b_reg: tri_ser_rlmreg_p +generic map (width => 9, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => eplc_t2_hyp_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(eplc_t2_reg_b_offset to eplc_t2_reg_b_offset + (eplc_t2_reg_d'length-16)-1), + scout => sov(eplc_t2_reg_b_offset to eplc_t2_reg_b_offset + (eplc_t2_reg_d'length-16)-1), + din => eplc_t2_reg_d(2 to 10), + dout => eplc_t2_reg_q(2 to 10)); + +eplc_t2_reg_c_reg: tri_ser_rlmreg_p +generic map (width => 14, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => eplc_t2_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(eplc_t2_reg_c_offset to eplc_t2_reg_c_offset + (eplc_t2_reg_d'length-11)-1), + scout => sov(eplc_t2_reg_c_offset to eplc_t2_reg_c_offset + (eplc_t2_reg_d'length-11)-1), + din => eplc_t2_reg_d(11 to 24), + dout => eplc_t2_reg_q(11 to 24)); + +eplc_t3_reg_a_reg: tri_ser_rlmreg_p +generic map (width => 2, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => eplc_t3_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(eplc_t3_reg_a_offset to eplc_t3_reg_a_offset + (eplc_t3_reg_d'length-23)-1), + scout => sov(eplc_t3_reg_a_offset to eplc_t3_reg_a_offset + (eplc_t3_reg_d'length-23)-1), + din => eplc_t3_reg_d(0 to 1), + dout => eplc_t3_reg_q(0 to 1)); + +eplc_t3_reg_b_reg: tri_ser_rlmreg_p +generic map (width => 9, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => eplc_t3_hyp_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(eplc_t3_reg_b_offset to eplc_t3_reg_b_offset + (eplc_t3_reg_d'length-16)-1), + scout => sov(eplc_t3_reg_b_offset to eplc_t3_reg_b_offset + (eplc_t3_reg_d'length-16)-1), + din => eplc_t3_reg_d(2 to 10), + dout => eplc_t3_reg_q(2 to 10)); + +eplc_t3_reg_c_reg: tri_ser_rlmreg_p +generic map (width => 14, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => eplc_t3_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(eplc_t3_reg_c_offset to eplc_t3_reg_c_offset + (eplc_t3_reg_d'length-11)-1), + scout => sov(eplc_t3_reg_c_offset to eplc_t3_reg_c_offset + (eplc_t3_reg_d'length-11)-1), + din => eplc_t3_reg_d(11 to 24), + dout => eplc_t3_reg_q(11 to 24)); + +epsc_t0_reg_a_reg: tri_ser_rlmreg_p +generic map (width => 2, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => epsc_t0_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(epsc_t0_reg_a_offset to epsc_t0_reg_a_offset + (epsc_t0_reg_d'length-23)-1), + scout => sov(epsc_t0_reg_a_offset to epsc_t0_reg_a_offset + (epsc_t0_reg_d'length-23)-1), + din => epsc_t0_reg_d(0 to 1), + dout => epsc_t0_reg_q(0 to 1)); + +epsc_t0_reg_b_reg: tri_ser_rlmreg_p +generic map (width => 9, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => epsc_t0_hyp_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(epsc_t0_reg_b_offset to epsc_t0_reg_b_offset + (epsc_t0_reg_d'length-16)-1), + scout => sov(epsc_t0_reg_b_offset to epsc_t0_reg_b_offset + (epsc_t0_reg_d'length-16)-1), + din => epsc_t0_reg_d(2 to 10), + dout => epsc_t0_reg_q(2 to 10)); + +epsc_t0_reg_c_reg: tri_ser_rlmreg_p +generic map (width => 14, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => epsc_t0_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(epsc_t0_reg_c_offset to epsc_t0_reg_c_offset + (epsc_t0_reg_d'length-11)-1), + scout => sov(epsc_t0_reg_c_offset to epsc_t0_reg_c_offset + (epsc_t0_reg_d'length-11)-1), + din => epsc_t0_reg_d(11 to 24), + dout => epsc_t0_reg_q(11 to 24)); + +epsc_t1_reg_a_reg: tri_ser_rlmreg_p +generic map (width => 2, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => epsc_t1_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(epsc_t1_reg_a_offset to epsc_t1_reg_a_offset + (epsc_t1_reg_d'length-23)-1), + scout => sov(epsc_t1_reg_a_offset to epsc_t1_reg_a_offset + (epsc_t1_reg_d'length-23)-1), + din => epsc_t1_reg_d(0 to 1), + dout => epsc_t1_reg_q(0 to 1)); + +epsc_t1_reg_b_reg: tri_ser_rlmreg_p +generic map (width => 9, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => epsc_t1_hyp_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(epsc_t1_reg_b_offset to epsc_t1_reg_b_offset + (epsc_t1_reg_d'length-16)-1), + scout => sov(epsc_t1_reg_b_offset to epsc_t1_reg_b_offset + (epsc_t1_reg_d'length-16)-1), + din => epsc_t1_reg_d(2 to 10), + dout => epsc_t1_reg_q(2 to 10)); + +epsc_t1_reg_c_reg: tri_ser_rlmreg_p +generic map (width => 14, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => epsc_t1_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(epsc_t1_reg_c_offset to epsc_t1_reg_c_offset + (epsc_t1_reg_d'length-11)-1), + scout => sov(epsc_t1_reg_c_offset to epsc_t1_reg_c_offset + (epsc_t1_reg_d'length-11)-1), + din => epsc_t1_reg_d(11 to 24), + dout => epsc_t1_reg_q(11 to 24)); + +epsc_t2_reg_a_reg: tri_ser_rlmreg_p +generic map (width => 2, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => epsc_t2_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(epsc_t2_reg_a_offset to epsc_t2_reg_a_offset + (epsc_t2_reg_d'length-23)-1), + scout => sov(epsc_t2_reg_a_offset to epsc_t2_reg_a_offset + (epsc_t2_reg_d'length-23)-1), + din => epsc_t2_reg_d(0 to 1), + dout => epsc_t2_reg_q(0 to 1)); + +epsc_t2_reg_b_reg: tri_ser_rlmreg_p +generic map (width => 9, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => epsc_t2_hyp_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(epsc_t2_reg_b_offset to epsc_t2_reg_b_offset + (epsc_t2_reg_d'length-16)-1), + scout => sov(epsc_t2_reg_b_offset to epsc_t2_reg_b_offset + (epsc_t2_reg_d'length-16)-1), + din => epsc_t2_reg_d(2 to 10), + dout => epsc_t2_reg_q(2 to 10)); + +epsc_t2_reg_c_reg: tri_ser_rlmreg_p +generic map (width => 14, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => epsc_t2_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(epsc_t2_reg_c_offset to epsc_t2_reg_c_offset + (epsc_t2_reg_d'length-11)-1), + scout => sov(epsc_t2_reg_c_offset to epsc_t2_reg_c_offset + (epsc_t2_reg_d'length-11)-1), + din => epsc_t2_reg_d(11 to 24), + dout => epsc_t2_reg_q(11 to 24)); + +epsc_t3_reg_a_reg: tri_ser_rlmreg_p +generic map (width => 2, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => epsc_t3_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(epsc_t3_reg_a_offset to epsc_t3_reg_a_offset + (epsc_t3_reg_d'length-23)-1), + scout => sov(epsc_t3_reg_a_offset to epsc_t3_reg_a_offset + (epsc_t3_reg_d'length-23)-1), + din => epsc_t3_reg_d(0 to 1), + dout => epsc_t3_reg_q(0 to 1)); + +epsc_t3_reg_b_reg: tri_ser_rlmreg_p +generic map (width => 9, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => epsc_t3_hyp_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(epsc_t3_reg_b_offset to epsc_t3_reg_b_offset + (epsc_t3_reg_d'length-16)-1), + scout => sov(epsc_t3_reg_b_offset to epsc_t3_reg_b_offset + (epsc_t3_reg_d'length-16)-1), + din => epsc_t3_reg_d(2 to 10), + dout => epsc_t3_reg_q(2 to 10)); + +epsc_t3_reg_c_reg: tri_ser_rlmreg_p +generic map (width => 14, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => epsc_t3_wen, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(epsc_t3_reg_c_offset to epsc_t3_reg_c_offset + (epsc_t3_reg_d'length-11)-1), + scout => sov(epsc_t3_reg_c_offset to epsc_t3_reg_c_offset + (epsc_t3_reg_d'length-11)-1), + din => epsc_t3_reg_d(11 to 24), + dout => epsc_t3_reg_q(11 to 24)); + +ex2_undef_lockset_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_undef_lockset_offset), + scout => sov(ex2_undef_lockset_offset), + din => ex2_undef_lockset_d, + dout => ex2_undef_lockset_q); + +ex3_undef_lockset_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_undef_lockset_offset), + scout => sov(ex3_undef_lockset_offset), + din => ex3_undef_lockset_d, + dout => ex3_undef_lockset_q); + +ex4_unable_2lock_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_unable_2lock_offset), + scout => sov(ex4_unable_2lock_offset), + din => ex4_unable_2lock_d, + dout => ex4_unable_2lock_q); + +ex5_unable_2lock_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_unable_2lock_offset), + scout => sov(ex5_unable_2lock_offset), + din => ex5_unable_2lock_d, + dout => ex5_unable_2lock_q); + +ex3_ldstq_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_ldstq_instr_offset), + scout => sov(ex3_ldstq_instr_offset), + din => ex3_ldstq_instr_d, + dout => ex3_ldstq_instr_q); + +ex4_store_instr_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex4_store_instr_d, + dout(0) => ex4_store_instr_q); + +ex5_store_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_store_instr_offset), + scout => sov(ex5_store_instr_offset), + din => ex5_store_instr_d, + dout => ex5_store_instr_q); + +ex5_store_miss_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_store_miss_offset), + scout => sov(ex5_store_miss_offset), + din => ex5_store_miss_d, + dout => ex5_store_miss_q); + +ex4_perf_dcbt_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex4_perf_dcbt_d, + dout(0) => ex4_perf_dcbt_q); + +ex5_perf_dcbt_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_perf_dcbt_offset), + scout => sov(ex5_perf_dcbt_offset), + din => ex5_perf_dcbt_d, + dout => ex5_perf_dcbt_q); + +perf_lsu_events_reg: tri_rlmreg_p +generic map (width => 17, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(perf_lsu_events_offset to perf_lsu_events_offset + perf_lsu_events_d'length-1), + scout => sov(perf_lsu_events_offset to perf_lsu_events_offset + perf_lsu_events_d'length-1), + din => perf_lsu_events_d, + dout => perf_lsu_events_q); + +clkg_ctl_override_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(clkg_ctl_override_offset), + scout => sov(clkg_ctl_override_offset), + din => clkg_ctl_override_d, + dout => clkg_ctl_override_q); + +spr_xucr0_wlck_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(spr_xucr0_wlck_offset), + scout => sov(spr_xucr0_wlck_offset), + din => spr_xucr0_wlck_d, + dout => spr_xucr0_wlck_q); + +spr_xucr0_wlck_cpy_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(spr_xucr0_wlck_cpy_offset), + scout => sov(spr_xucr0_wlck_cpy_offset), + din => spr_xucr0_wlck_cpy_d, + dout => spr_xucr0_wlck_cpy_q); + +spr_xucr0_flh2l2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(spr_xucr0_flh2l2_offset), + scout => sov(spr_xucr0_flh2l2_offset), + din => spr_xucr0_flh2l2_d, + dout => spr_xucr0_flh2l2_q); + +ex3_spr_xucr0_flh2l2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_spr_xucr0_flh2l2_offset), + scout => sov(ex3_spr_xucr0_flh2l2_offset), + din => ex3_spr_xucr0_flh2l2_d, + dout => ex3_spr_xucr0_flh2l2_q); + +spr_xucr0_dcdis_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(spr_xucr0_dcdis_offset), + scout => sov(spr_xucr0_dcdis_offset), + din => spr_xucr0_dcdis_d, + dout => spr_xucr0_dcdis_q); + +spr_xucr0_cls_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(spr_xucr0_cls_offset), + scout => sov(spr_xucr0_cls_offset), + din => spr_xucr0_cls_d, + dout => spr_xucr0_cls_q); + +agen_xucr0_cls_dly_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(agen_xucr0_cls_dly_offset), + scout => sov(agen_xucr0_cls_dly_offset), + din => agen_xucr0_cls_dly_d, + dout => agen_xucr0_cls_dly_q); + +agen_xucr0_cls_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(agen_xucr0_cls_offset), + scout => sov(agen_xucr0_cls_offset), + din => agen_xucr0_cls_d, + dout => agen_xucr0_cls_q); + +mtspr_trace_en_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(mtspr_trace_en_offset to mtspr_trace_en_offset + mtspr_trace_en_d'length-1), + scout => sov(mtspr_trace_en_offset to mtspr_trace_en_offset + mtspr_trace_en_d'length-1), + din => mtspr_trace_en_d, + dout => mtspr_trace_en_q); + +ex3_local_dcbf_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_local_dcbf_offset), + scout => sov(ex3_local_dcbf_offset), + din => ex3_local_dcbf_d, + dout => ex3_local_dcbf_q); + +ex1_msgsnd_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_msgsnd_instr_offset), + scout => sov(ex1_msgsnd_instr_offset), + din => ex1_msgsnd_instr_d, + dout => ex1_msgsnd_instr_q); + +ex2_msgsnd_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_msgsnd_instr_offset), + scout => sov(ex2_msgsnd_instr_offset), + din => ex2_msgsnd_instr_d, + dout => ex2_msgsnd_instr_q); + +ex3_msgsnd_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_msgsnd_instr_offset), + scout => sov(ex3_msgsnd_instr_offset), + din => ex3_msgsnd_instr_d, + dout => ex3_msgsnd_instr_q); + +ex1_dci_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_dci_instr_offset), + scout => sov(ex1_dci_instr_offset), + din => ex1_dci_instr_d, + dout => ex1_dci_instr_q); + +ex2_dci_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_dci_instr_offset), + scout => sov(ex2_dci_instr_offset), + din => ex2_dci_instr_d, + dout => ex2_dci_instr_q); + +ex3_dci_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_dci_instr_offset), + scout => sov(ex3_dci_instr_offset), + din => ex3_dci_instr_d, + dout => ex3_dci_instr_q); + +ex1_ici_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_ici_instr_offset), + scout => sov(ex1_ici_instr_offset), + din => ex1_ici_instr_d, + dout => ex1_ici_instr_q); + +ex2_ici_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_ici_instr_offset), + scout => sov(ex2_ici_instr_offset), + din => ex2_ici_instr_d, + dout => ex2_ici_instr_q); + +ex3_ici_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_ici_instr_offset), + scout => sov(ex3_ici_instr_offset), + din => ex3_ici_instr_d, + dout => ex3_ici_instr_q); + +ex3_load_type_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_load_type_offset), + scout => sov(ex3_load_type_offset), + din => ex3_load_type_d, + dout => ex3_load_type_q); + +ex4_load_type_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex4_load_type_d, + dout(0) => ex4_load_type_q); + +ex3_l2load_type_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_l2load_type_offset), + scout => sov(ex3_l2load_type_offset), + din => ex3_l2load_type_d, + dout => ex3_l2load_type_q); + +flh2l2_gate_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(flh2l2_gate_offset), + scout => sov(flh2l2_gate_offset), + din => flh2l2_gate_d, + dout => flh2l2_gate_q); + +rel_upd_dcarr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_upd_dcarr_offset), + scout => sov(rel_upd_dcarr_offset), + din => rel_upd_dcarr_d, + dout => rel_upd_dcarr_q); + +ex5_xu_wren_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_xu_wren_offset), + scout => sov(ex5_xu_wren_offset), + din => ex5_xu_wren_d, + dout => ex5_xu_wren_q); + +ex1_ldawx_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_ldawx_instr_offset), + scout => sov(ex1_ldawx_instr_offset), + din => ex1_ldawx_instr_d, + dout => ex1_ldawx_instr_q); + +ex2_ldawx_instr_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_ldawx_instr_d, + dout(0) => ex2_ldawx_instr_q); + +ex3_watch_en_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_watch_en_offset), + scout => sov(ex3_watch_en_offset), + din => ex3_watch_en_d, + dout => ex3_watch_en_q); + +ex4_watch_en_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex4_watch_en_d, + dout(0) => ex4_watch_en_q); + +ex5_watch_en_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_watch_en_offset), + scout => sov(ex5_watch_en_offset), + din => ex5_watch_en_d, + dout => ex5_watch_en_q); + +ex1_wclr_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_wclr_instr_offset), + scout => sov(ex1_wclr_instr_offset), + din => ex1_wclr_instr_d, + dout => ex1_wclr_instr_q); + +ex2_wclr_instr_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_wclr_instr_d, + dout(0) => ex2_wclr_instr_q); + +ex3_wclr_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wclr_instr_offset), + scout => sov(ex3_wclr_instr_offset), + din => ex3_wclr_instr_d, + dout => ex3_wclr_instr_q); + +ex4_wclr_instr_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex4_wclr_instr_d, + dout(0) => ex4_wclr_instr_q); + +ex5_wclr_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_wclr_instr_offset), + scout => sov(ex5_wclr_instr_offset), + din => ex5_wclr_instr_d, + dout => ex5_wclr_instr_q); + +ex4_wclr_set_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex4_wclr_set_d, + dout(0) => ex4_wclr_set_q); + +ex5_wclr_set_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_wclr_set_offset), + scout => sov(ex5_wclr_set_offset), + din => ex5_wclr_set_d, + dout => ex5_wclr_set_q); + +ex1_wchk_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_wchk_instr_offset), + scout => sov(ex1_wchk_instr_offset), + din => ex1_wchk_instr_d, + dout => ex1_wchk_instr_q); + +ex2_wchk_instr_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_wchk_instr_d, + dout(0) => ex2_wchk_instr_q); + +ex4_cacheable_linelock_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_cacheable_linelock_offset), + scout => sov(ex4_cacheable_linelock_offset), + din => ex4_cacheable_linelock_d, + dout => ex4_cacheable_linelock_q); + +ex1_icswx_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_icswx_instr_offset), + scout => sov(ex1_icswx_instr_offset), + din => ex1_icswx_instr_d, + dout => ex1_icswx_instr_q); + +ex2_icswx_instr_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_icswx_instr_d, + dout(0) => ex2_icswx_instr_q); + +ex3_icswx_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_icswx_instr_offset), + scout => sov(ex3_icswx_instr_offset), + din => ex3_icswx_instr_d, + dout => ex3_icswx_instr_q); + +ex1_icswx_dot_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_icswx_dot_instr_offset), + scout => sov(ex1_icswx_dot_instr_offset), + din => ex1_icswx_dot_instr_d, + dout => ex1_icswx_dot_instr_q); + +ex2_icswx_dot_instr_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_icswx_dot_instr_d, + dout(0) => ex2_icswx_dot_instr_q); + +ex3_icswx_dot_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_icswx_dot_instr_offset), + scout => sov(ex3_icswx_dot_instr_offset), + din => ex3_icswx_dot_instr_d, + dout => ex3_icswx_dot_instr_q); + +ex1_icswx_epid_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_icswx_epid_offset), + scout => sov(ex1_icswx_epid_offset), + din => ex1_icswx_epid_d, + dout => ex1_icswx_epid_q); + +ex2_icswx_epid_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_icswx_epid_d, + dout(0) => ex2_icswx_epid_q); + +ex3_icswx_epid_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_icswx_epid_offset), + scout => sov(ex3_icswx_epid_offset), + din => ex3_icswx_epid_d, + dout => ex3_icswx_epid_q); + +ex3_c_inh_drop_op_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_c_inh_drop_op_offset), + scout => sov(ex3_c_inh_drop_op_offset), + din => ex3_c_inh_drop_op_d, + dout => ex3_c_inh_drop_op_q); + +axu_rel_wren_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ldq_rel_stg24_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(axu_rel_wren_offset), + scout => sov(axu_rel_wren_offset), + din => axu_rel_wren_d, + dout => axu_rel_wren_q); + +axu_rel_wren_stg1_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(axu_rel_wren_stg1_offset), + scout => sov(axu_rel_wren_stg1_offset), + din => axu_rel_wren_stg1_d, + dout => axu_rel_wren_stg1_q); + +rel_axu_tid_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ldq_rel_stg24_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_axu_tid_offset to rel_axu_tid_offset + rel_axu_tid_d'length-1), + scout => sov(rel_axu_tid_offset to rel_axu_tid_offset + rel_axu_tid_d'length-1), + din => rel_axu_tid_d, + dout => rel_axu_tid_q); + +rel_axu_tid_stg1_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_axu_tid_stg1_offset to rel_axu_tid_stg1_offset + rel_axu_tid_stg1_d'length-1), + scout => sov(rel_axu_tid_stg1_offset to rel_axu_tid_stg1_offset + rel_axu_tid_stg1_d'length-1), + din => rel_axu_tid_stg1_d, + dout => rel_axu_tid_stg1_q); + +rel_axu_ta_gpr_reg: tri_rlmreg_p +generic map (width => 9, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ldq_rel_stg24_val, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_axu_ta_gpr_offset to rel_axu_ta_gpr_offset + rel_axu_ta_gpr_d'length-1), + scout => sov(rel_axu_ta_gpr_offset to rel_axu_ta_gpr_offset + rel_axu_ta_gpr_d'length-1), + din => rel_axu_ta_gpr_d, + dout => rel_axu_ta_gpr_q); + +rel_axu_ta_gpr_stg1_reg: tri_rlmreg_p +generic map (width => 9, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_axu_ta_gpr_stg1_offset to rel_axu_ta_gpr_stg1_offset + rel_axu_ta_gpr_stg1_d'length-1), + scout => sov(rel_axu_ta_gpr_stg1_offset to rel_axu_ta_gpr_stg1_offset + rel_axu_ta_gpr_stg1_d'length-1), + din => rel_axu_ta_gpr_stg1_d, + dout => rel_axu_ta_gpr_stg1_q); + +rf0_l2_inv_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(rf0_l2_inv_val_offset), + scout => sov(rf0_l2_inv_val_offset), + din => rf0_l2_inv_val_d, + dout => rf0_l2_inv_val_q); + +rf1_l2_inv_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(rf1_l2_inv_val_offset), + scout => sov(rf1_l2_inv_val_offset), + din => rf1_l2_inv_val_d, + dout => rf1_l2_inv_val_q); + +ex1_agen_binv_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_agen_binv_val_offset), + scout => sov(ex1_agen_binv_val_offset), + din => ex1_agen_binv_val_d, + dout => ex1_agen_binv_val_q); + +ex1_l2_inv_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_l2_inv_val_offset), + scout => sov(ex1_l2_inv_val_offset), + din => ex1_l2_inv_val_d, + dout => ex1_l2_inv_val_q); + +lsu_msr_gs_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(lsu_msr_gs_offset to lsu_msr_gs_offset + lsu_msr_gs_d'length-1), + scout => sov(lsu_msr_gs_offset to lsu_msr_gs_offset + lsu_msr_gs_d'length-1), + din => lsu_msr_gs_d, + dout => lsu_msr_gs_q); + +lsu_msr_pr_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(lsu_msr_pr_offset to lsu_msr_pr_offset + lsu_msr_pr_d'length-1), + scout => sov(lsu_msr_pr_offset to lsu_msr_pr_offset + lsu_msr_pr_d'length-1), + din => lsu_msr_pr_d, + dout => lsu_msr_pr_q); + +lsu_msr_cm_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(lsu_msr_cm_offset to lsu_msr_cm_offset + lsu_msr_cm_d'length-1), + scout => sov(lsu_msr_cm_offset to lsu_msr_cm_offset + lsu_msr_cm_d'length-1), + din => lsu_msr_cm_d, + dout => lsu_msr_cm_q); + +ex1_lsu_64bit_agen_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_lsu_64bit_agen_offset), + scout => sov(ex1_lsu_64bit_agen_offset), + din => ex1_lsu_64bit_agen_d, + dout => ex1_lsu_64bit_agen_q); + +ex6_icbi_val_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_icbi_val_offset to ex6_icbi_val_offset + ex6_icbi_val_d'length-1), + scout => sov(ex6_icbi_val_offset to ex6_icbi_val_offset + ex6_icbi_val_d'length-1), + din => ex6_icbi_val_d, + dout => ex6_icbi_val_q); + +ex1_mtspr_trace_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_mtspr_trace_offset), + scout => sov(ex1_mtspr_trace_offset), + din => ex1_mtspr_trace_d, + dout => ex1_mtspr_trace_q); + +ex2_mtspr_trace_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_mtspr_trace_offset), + scout => sov(ex2_mtspr_trace_offset), + din => ex2_mtspr_trace_d, + dout => ex2_mtspr_trace_q); + +ex3_mtspr_trace_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_mtspr_trace_offset), + scout => sov(ex3_mtspr_trace_offset), + din => ex3_mtspr_trace_d, + dout => ex3_mtspr_trace_q); + +ex3_byte_en_reg: tri_rlmreg_p +generic map (width => 32, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_byte_en_offset to ex3_byte_en_offset + ex3_byte_en_d'length-1), + scout => sov(ex3_byte_en_offset to ex3_byte_en_offset + ex3_byte_en_d'length-1), + din => ex3_byte_en_d, + dout => ex3_byte_en_q); + +ex3_rot_sel_le_reg: tri_rlmreg_p +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_rot_sel_le_offset to ex3_rot_sel_le_offset + ex3_rot_sel_le_d'length-1), + scout => sov(ex3_rot_sel_le_offset to ex3_rot_sel_le_offset + ex3_rot_sel_le_d'length-1), + din => ex3_rot_sel_le_d, + dout => ex3_rot_sel_le_q); + +ex3_rot_sel_be_reg: tri_rlmreg_p +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_rot_sel_be_offset to ex3_rot_sel_be_offset + ex3_rot_sel_be_d'length-1), + scout => sov(ex3_rot_sel_be_offset to ex3_rot_sel_be_offset + ex3_rot_sel_be_d'length-1), + din => ex3_rot_sel_be_d, + dout => ex3_rot_sel_be_q); + +dir_arr_rd_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dir_arr_rd_val_offset), + scout => sov(dir_arr_rd_val_offset), + din => dir_arr_rd_val_d, + dout => dir_arr_rd_val_q); + +dir_arr_rd_is0_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dir_arr_rd_is0_val_offset), + scout => sov(dir_arr_rd_is0_val_offset), + din => dir_arr_rd_is0_val_d, + dout => dir_arr_rd_is0_val_q); + +dir_arr_rd_is1_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dir_arr_rd_is1_val_offset), + scout => sov(dir_arr_rd_is1_val_offset), + din => dir_arr_rd_is1_val_d, + dout => dir_arr_rd_is1_val_q); + +dir_arr_rd_is2_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dir_arr_rd_is2_val_offset), + scout => sov(dir_arr_rd_is2_val_offset), + din => dir_arr_rd_is2_val_d, + dout => dir_arr_rd_is2_val_q); + +dir_arr_rd_rf0_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dir_arr_rd_rf0_val_offset), + scout => sov(dir_arr_rd_rf0_val_offset), + din => dir_arr_rd_rf0_val_d, + dout => dir_arr_rd_rf0_val_q); + +dir_arr_rd_rf1_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dir_arr_rd_rf1_val_offset), + scout => sov(dir_arr_rd_rf1_val_offset), + din => dir_arr_rd_rf1_val_d, + dout => dir_arr_rd_rf1_val_q); + +dir_arr_rd_rf0_done_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dir_arr_rd_rf0_done_offset), + scout => sov(dir_arr_rd_rf0_done_offset), + din => dir_arr_rd_rf0_done_d, + dout => dir_arr_rd_rf0_done_q); + +dir_arr_rd_rf1_done_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dir_arr_rd_rf1_done_offset), + scout => sov(dir_arr_rd_rf1_done_offset), + din => dir_arr_rd_rf1_done_d, + dout => dir_arr_rd_rf1_done_q); + +dir_arr_rd_ex1_done_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dir_arr_rd_ex1_done_offset), + scout => sov(dir_arr_rd_ex1_done_offset), + din => dir_arr_rd_ex1_done_d, + dout => dir_arr_rd_ex1_done_q); + +dir_arr_rd_ex2_done_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dir_arr_rd_ex2_done_offset), + scout => sov(dir_arr_rd_ex2_done_offset), + din => dir_arr_rd_ex2_done_d, + dout => dir_arr_rd_ex2_done_q); + +dir_arr_rd_ex3_done_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dir_arr_rd_ex3_done_offset), + scout => sov(dir_arr_rd_ex3_done_offset), + din => dir_arr_rd_ex3_done_d, + dout => dir_arr_rd_ex3_done_q); + +dir_arr_rd_ex4_done_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dir_arr_rd_ex4_done_offset), + scout => sov(dir_arr_rd_ex4_done_offset), + din => dir_arr_rd_ex4_done_d, + dout => dir_arr_rd_ex4_done_q); + +my_spare0_lcb : entity tri.tri_lcbnd(tri_lcbnd) +generic map (expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + d1clk => my_spare0_d1clk, + d2clk => my_spare0_d2clk, + lclk => my_spare0_lclk); +my_spare0_latches_reg: entity tri.tri_inv_nlats(tri_inv_nlats) +generic map (width => 3, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + lclk => my_spare0_lclk, + d1clk => my_spare0_d1clk, + d2clk => my_spare0_d2clk, + scanin => siv(my_spare0_latches_offset to my_spare0_latches_offset + my_spare0_latches_d'length-1), + scanout => sov(my_spare0_latches_offset to my_spare0_latches_offset + my_spare0_latches_d'length-1), + d => my_spare0_latches_d, + qb => my_spare0_latches_q); + +my_spare1_lcb : entity tri.tri_lcbnd(tri_lcbnd) +generic map (expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + d1clk => my_spare1_d1clk, + d2clk => my_spare1_d2clk, + lclk => my_spare1_lclk); +my_spare1_latches_reg: entity tri.tri_inv_nlats(tri_inv_nlats) +generic map (width => 20, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + lclk => my_spare1_lclk, + d1clk => my_spare1_d1clk, + d2clk => my_spare1_d2clk, + scanin => siv(my_spare1_latches_offset to my_spare1_latches_offset + my_spare1_latches_d'length-1), + scanout => sov(my_spare1_latches_offset to my_spare1_latches_offset + my_spare1_latches_d'length-1), + d => my_spare1_latches_d, + qb => my_spare1_latches_q); + +rf1_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf1_stg_act_offset), + scout => sov(rf1_stg_act_offset), + din => rf1_stg_act_d, + dout => rf1_stg_act_q); + +ex1_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_stg_act_offset), + scout => sov(ex1_stg_act_offset), + din => ex1_stg_act_d, + dout => ex1_stg_act_q); + +ex2_stg_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_stg_act_d, + dout(0) => ex2_stg_act_q); + +ex3_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_stg_act_offset), + scout => sov(ex3_stg_act_offset), + din => ex3_stg_act_d, + dout => ex3_stg_act_q); + +ex4_stg_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex4_stg_act_d, + dout(0) => ex4_stg_act_q); + +ex5_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_stg_act_offset), + scout => sov(ex5_stg_act_offset), + din => ex5_stg_act_d, + dout => ex5_stg_act_q); + +binv1_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv1_stg_act_offset), + scout => sov(binv1_stg_act_offset), + din => binv1_stg_act_d, + dout => binv1_stg_act_q); + +binv2_stg_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => binv2_stg_act_d, + dout(0) => binv2_stg_act_q); + +binv3_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv3_stg_act_offset), + scout => sov(binv3_stg_act_offset), + din => binv3_stg_act_d, + dout => binv3_stg_act_q); + +binv4_stg_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => binv4_stg_act_d, + dout(0) => binv4_stg_act_q); + +binv5_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv5_stg_act_offset), + scout => sov(binv5_stg_act_offset), + din => binv5_stg_act_d, + dout => binv5_stg_act_q); + +rel1_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel1_stg_act_offset), + scout => sov(rel1_stg_act_offset), + din => rel1_stg_act_d, + dout => rel1_stg_act_q); + +rel3_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel3_stg_act_offset), + scout => sov(rel3_stg_act_offset), + din => rel3_stg_act_d, + dout => rel3_stg_act_q); + +rel4_stg_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel4_stg_act_d, + dout(0) => rel4_stg_act_q); + +siv(0 to scan_right) <= sov(1 to scan_right) & scan_in; +scan_out <= sov(0); + + +end xuq_lsu_dc_cntrl; diff --git a/rel/src/vhdl/work/xuq_lsu_debug.vhdl b/rel/src/vhdl/work/xuq_lsu_debug.vhdl new file mode 100644 index 0000000..f37f6e4 --- /dev/null +++ b/rel/src/vhdl/work/xuq_lsu_debug.vhdl @@ -0,0 +1,1494 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: LSU Debug Event Muxing +-- +library ieee,ibm,support,work,tri; +use ieee.std_logic_1164.all; +use support.power_logic_pkg.all; +use tri.tri_latches_pkg.all; + +entity xuq_lsu_debug is +generic(expand_type :integer := 2); +port( + + -- PC Debug Control + pc_xu_trace_bus_enable :in std_ulogic; + lsu_debug_mux_ctrls :in std_ulogic_vector(0 to 15); + xu_lsu_ex2_instr_trace_val :in std_ulogic; + + -- Pass Thru Debug Trace Bus + trigger_data_in :in std_ulogic_vector(0 to 11); + debug_data_in :in std_ulogic_vector(0 to 87); + + -- Debug Data + dc_fgen_dbg_data :in std_ulogic_vector(0 to 1); + dc_cntrl_dbg_data :in std_ulogic_vector(0 to 66); + dc_val_dbg_data :in std_ulogic_vector(0 to 293); + dc_lru_dbg_data :in std_ulogic_vector(0 to 81); + dc_dir_dbg_data :in std_ulogic_vector(0 to 35); + dir_arr_dbg_data :in std_ulogic_vector(0 to 60); + lmq_dbg_dcache_pe :in std_ulogic_vector(1 to 60); + lmq_dbg_l2req :in std_ulogic_vector(0 to 212); + lmq_dbg_rel :in std_ulogic_vector(0 to 140); + lmq_dbg_binv :in std_ulogic_vector(0 to 44); + lmq_dbg_pops :in std_ulogic_vector(0 to 5); + lmq_dbg_grp0 :in std_ulogic_vector(0 to 81); + lmq_dbg_grp1 :in std_ulogic_vector(0 to 81); + lmq_dbg_grp2 :in std_ulogic_vector(0 to 87); + lmq_dbg_grp3 :in std_ulogic_vector(0 to 87); + lmq_dbg_grp4 :in std_ulogic_vector(0 to 87); + lmq_dbg_grp5 :in std_ulogic_vector(0 to 87); + lmq_dbg_grp6 :in std_ulogic_vector(0 to 87); + pe_recov_begin :in std_ulogic; + derat_xu_debug_group0 :in std_ulogic_vector(0 to 87); + derat_xu_debug_group1 :in std_ulogic_vector(0 to 87); + + -- Outputs + trigger_data_out :out std_ulogic_vector(0 to 11); + debug_data_out :out std_ulogic_vector(0 to 87); + + -- Power + vdd :inout power_logic; + gnd :inout power_logic; + nclk :in clk_logic; + sg_0 :in std_ulogic; + func_slp_sl_thold_0_b :in std_ulogic; + func_slp_sl_force :in std_ulogic; + d_mode_dc :in std_ulogic; + delay_lclkr_dc :in std_ulogic; + mpw1_dc_b :in std_ulogic; + mpw2_dc_b :in std_ulogic; + scan_in :in std_ulogic; + scan_out :out std_ulogic +); + +-- synopsys translate_off + +-- synopsys translate_on +end xuq_lsu_debug; +architecture xuq_lsu_debug of xuq_lsu_debug is + +type dbgSize is array (natural range <>) of std_ulogic_vector(0 to 21); + +signal trace_bus_enable_q :std_ulogic; +signal unit_trace_sel_q :std_ulogic_vector(0 to 15); + +signal lsu_dbg_way_0 :dbgSize(0 to 7); +signal lsu_dbg_way_1 :dbgSize(0 to 7); +signal lsu_dbg_way_2 :dbgSize(0 to 7); +signal lsu_dbg_way_3 :dbgSize(0 to 7); +signal l2cmdq_dbg_data_0 :dbgSize(0 to 3); +signal l2cmdq_dbg_data_1 :dbgSize(0 to 3); +signal l2cmdq_dbg_data_2 :dbgSize(0 to 3); +signal l2cmdq_dbg_data_3 :dbgSize(0 to 3); +signal lsu_dbg_group0_0 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group0_1 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group0_2 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group0_3 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group0 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group1_b64 :std_ulogic; +signal lsu_dbg_group1_b67 :std_ulogic; +signal lsu_dbg_group1_0 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group1_1 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group1_2 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group1_3 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group1 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group2_0 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group2_1 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group2_2 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group2_3 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group2 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group3_0 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group3_1 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group3_2 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group3_3 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group3 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group4_0 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group4_1 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group4_2 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group4_3 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group4 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group5_0 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group5_1 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group5_2 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group5_3 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group5 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group6_0 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group6_1 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group6_2 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group6_3 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group6 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group7_0 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group7_1 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group7_2 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group7_3 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group7 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group8_0 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group8_1 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group8_2 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group8_3 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group8 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group9_0 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group9_1 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group9_2 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group9_3 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group9 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group10_0 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group10_1 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group10_2 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group10_3 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group10 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group11_0 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group11_1 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group11_2 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group11_3 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group11 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group12_0 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group12_1 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group12_2 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group12_3 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group12 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group13_0 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group13_1 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group13_2 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group13_3 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group13 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group14_0 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group14_1 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group14_2 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group14_3 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group14 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group15_0 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group15_1 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group15_2 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group15_3 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group15 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group16_0 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group16_1 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group16_2 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group16_3 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group16 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group17_0 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group17_1 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group17_2 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group17_3 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group17 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group18_0 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group18_1 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group18_2 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group18_3 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group18 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group19_0 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group19_1 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group19_2 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group19_3 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group19 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group20_0 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group20_1 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group20_2 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group20_3 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group20 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group21_0 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group21_1 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group21_2 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group21_3 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group21 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group22 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group23 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group24 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group25 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group26 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group27 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group28 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group29_0 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group29_1 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group29_2 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group29_3 :std_ulogic_vector(0 to 21); +signal lsu_dbg_group29 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group30 :std_ulogic_vector(0 to 87); +signal lsu_dbg_group31 :std_ulogic_vector(0 to 87); +signal lsu_trg_group0 :std_ulogic_vector(0 to 11); +signal lsu_trg_group1 :std_ulogic_vector(0 to 11); +signal lsu_trg_group2 :std_ulogic_vector(0 to 11); +signal lsu_trg_group3 :std_ulogic_vector(0 to 11); +signal lmq_dbg_rel_ctrl :std_ulogic_vector(0 to 5); +signal ex3_instr_trace_val_d :std_ulogic; +signal ex3_instr_trace_val_q :std_ulogic; +signal ex4_instr_trace_val_d :std_ulogic; +signal ex4_instr_trace_val_q :std_ulogic; +signal trace_unit_sel :std_ulogic_vector(0 to 15); + +constant trace_bus_enable_offset :integer := 0; +constant ex3_instr_trace_val_offset :integer := trace_bus_enable_offset + 1; +constant ex4_instr_trace_val_offset :integer := ex3_instr_trace_val_offset + 1; +constant unit_trace_sel_offset :integer := ex4_instr_trace_val_offset + 1; +constant scan_right :integer := unit_trace_sel_offset + unit_trace_sel_q'length; + +signal dbg_scan_out :std_ulogic; +signal siv :std_ulogic_vector(0 to scan_right-1); +signal sov :std_ulogic_vector(0 to scan_right-1); +signal tiup :std_ulogic; + +begin + +tiup <= '1'; + + + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Instruction Trace Mode +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Trace Mode selects debug bus 1 +-- bit67 of debug bus 1 becomes ex4_instr_trace_val_q +ex3_instr_trace_val_d <= xu_lsu_ex2_instr_trace_val; +ex4_instr_trace_val_d <= ex3_instr_trace_val_q; + +with ex3_instr_trace_val_q select + trace_unit_sel <= unit_trace_sel_q when '0', + x"09E0" when others; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Debug Bus 0 -> General Instruction +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- ex4_way_hit_q 8 +-- ex4_congr_cl_q 5 +-- binv4_ex4_xuop_upd_q 1 +-- ex4_dir_access_op 4 +-- ex1_ldst_falign_q 1 +-- ex2_ldst_fexcpt_q 1 +-- ex5_cache_inh_q 1 +-- ex3_data_swap_int 1 + +-- rel_lost_watch_upd_q 4 +-- stm_watchlost_state_q 4 +-- ex5_axu_ta_gpr_q 9 +-- ex5_xu_wren_q 1 +-- ex5_axu_wren_q 1 +-- ex4_dir_err_val_q 1 +-- ex4_dir_multihit_val_q 1 +-- ex7_ld_par_err 1 + +-- ex2_is_mem_bar_op 1 +-- ex3_l2_op_q 1 +-- ld_rel_val_l2 8 +-- st_entry0_val_l2 1 +-- load_cmd_count_l2(0) 1 +-- store_cmd_count_l2(0) 1 +-- ex4_p_addr 9 + +-- ex4_p_addr 22 +-- Total 88 + +lsu_dbg_group0_0 <= dc_val_dbg_data(208 to 215) & dc_val_dbg_data(216 to 220) & dc_val_dbg_data(293) & dc_val_dbg_data(226 to 229) & + dc_cntrl_dbg_data(24) & dc_cntrl_dbg_data(25) & dc_cntrl_dbg_data(26) & dc_cntrl_dbg_data(27); + +lsu_dbg_group0_1 <= dc_val_dbg_data(264 to 267) & dc_val_dbg_data(268 to 271) & dc_cntrl_dbg_data(13 to 21) & dc_cntrl_dbg_data(28) & + dc_cntrl_dbg_data(29) & dc_val_dbg_data(263) & dc_val_dbg_data(262) & dc_val_dbg_data(276); + +lsu_dbg_group0_2 <= dc_cntrl_dbg_data(22) & dc_cntrl_dbg_data(23) & lmq_dbg_grp2(27 to 34) & lmq_dbg_grp3(7) & lmq_dbg_grp2(46) & lmq_dbg_grp3(50) & dc_cntrl_dbg_data(30 to 38); + +lsu_dbg_group0_3 <= dc_cntrl_dbg_data(39 to 60); + +lsu_dbg_group0 <= lsu_dbg_group0_0 & lsu_dbg_group0_1 & lsu_dbg_group0_2 & lsu_dbg_group0_3; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Debug Bus 1 -> General Instruction with Reload +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- ex4_way_hit_q 8 +-- ex4_congr_cl_q 5 <-- ex4_p_addr_q(53:57) +-- binv4_ex4_xuop_upd_q 1 +-- ex4_dir_access_op 4 +-- ex4_p_addr(58:61) 4 + +-- ldq_rel_back_invalidated 1 +-- ldq_rel_ci 1 +-- ld_rel_val_l2 8 +-- st_entry0_val_l2 1 +-- ex4_p_addr(22:32) 11 + +-- ex4_p_addr(33:52) 20 +-- load_cmd_count_l2(0) 1 +-- store_cmd_count_l2(0) 1 + +-- ex2_is_mem_bar_op 1 +-- ex3_l2_op_q 1 +-- ex4_n_flush_rq_q 1 +-- ldq_rel1_val 1 +-- ldq_rel_mid_val 1 +-- ldq_rel3_val 1 +-- ldq_rel_retry_val 1 +-- ldq_recirc_rel_val 1 +-- ldq_rel_tag 3 +-- ldq_rel_set_val 1 +-- ldq_rel_ta_gpr(7:8) 2 +-- ldq_rel_lock_en 1 +-- ldq_rel_classid 2 +-- rel_congr_cl_q 5 + +-- Total 88 + +lsu_dbg_group1_b64 <= lmq_dbg_grp2(46) and not ex4_instr_trace_val_q; +lsu_dbg_group1_b67 <= dc_cntrl_dbg_data(23) or ex4_instr_trace_val_q; +lsu_dbg_group1_0 <= dc_val_dbg_data(208 to 215) & dc_val_dbg_data(216 to 220) & dc_val_dbg_data(293) & dc_val_dbg_data(226 to 229) & + dc_cntrl_dbg_data(61 to 64); + +lsu_dbg_group1_1 <= dc_val_dbg_data(274) & dc_fgen_dbg_data(0) & lmq_dbg_grp2(27 to 34) & lmq_dbg_grp3(7) & dc_cntrl_dbg_data(30 to 40); + +lsu_dbg_group1_2 <= dc_cntrl_dbg_data(41 to 60) & lsu_dbg_group1_b64 & lmq_dbg_grp3(50); + +lsu_dbg_group1_3 <= dc_cntrl_dbg_data(22) & lsu_dbg_group1_b67 & dc_fgen_dbg_data(1) & dc_dir_dbg_data(0) & + dc_dir_dbg_data(1) & dc_dir_dbg_data(2) & dc_lru_dbg_data(80) & dc_val_dbg_data(275) & + dc_lru_dbg_data(77 to 79) & dc_dir_dbg_data(4) & dc_cntrl_dbg_data(8 to 9) & dc_val_dbg_data(272) & + dc_lru_dbg_data(75 to 76) & dc_val_dbg_data(221 to 225); + +lsu_dbg_group1 <= lsu_dbg_group1_0 & lsu_dbg_group1_1 & lsu_dbg_group1_2 & lsu_dbg_group1_3; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Debug Bus 2 -> WayA Bypass +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- ex4_wayA_byp_ctrl_fxpipe 1 +-- ex4_wayA_byp_ctrl_relpipe 1 +-- ex4_wayA_val 6 +-- ex4_congr_cl_q 5 +-- ex4_p_addr 9 + +-- ex4_p_addr 22 + +-- ex4_way_hit_q(0) 1 +-- binv4_ex4_xuop_upd_q 1 +-- ex4_dir_access_op 4 +-- binv_wayA_upd2_q 1 +-- flush_wayA_data_q 6 +-- ldq_rel1_val 1 +-- ldq_rel_mid_val 1 +-- ldq_rel3_val 1 +-- ldq_rel_retry_val 1 +-- ldq_recirc_rel_val 1 +-- ldq_rel_set_val 1 +-- rel_way_dwen(0) 1 +-- rel_wayA_byp_ctrl_fxpipe 1 +-- rel_wayA_byp_ctrl_relpipe 1 + +-- ldq_rel_back_invalidated 1 +-- ldq_rel_tag 3 +-- rel_wayA_val 6 +-- rel_congr_cl_q 5 +-- reload_wayA_upd2_q 1 +-- reload_wayA_data_q 6 +-- Total 88 + +wayDbgGen : for w in 0 to 7 generate begin + + lsu_dbg_way_0(w) <= (others=>'0'); + lsu_dbg_way_1(w) <= (others=>'0'); + lsu_dbg_way_2(w) <= (others=>'0'); + lsu_dbg_way_3(w) <= (others=>'0'); +end generate wayDbgGen; + +lsu_dbg_group2_0 <= lsu_dbg_way_0(0); +lsu_dbg_group2_1 <= lsu_dbg_way_1(0); +lsu_dbg_group2_2 <= lsu_dbg_way_2(0); +lsu_dbg_group2_3 <= lsu_dbg_way_3(0); +lsu_dbg_group2 <= lsu_dbg_group2_0 & lsu_dbg_group2_1 & lsu_dbg_group2_2 & lsu_dbg_group2_3; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Debug Bus 3 -> WayB Bypass +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- ex4_wayB_byp_ctrl_fxpipe 1 +-- ex4_wayB_byp_ctrl_relpipe 1 +-- ex4_wayB_val 6 +-- ex4_congr_cl_q 5 +-- ex4_p_addr 9 + +-- ex4_p_addr 22 + +-- ex4_way_hit_q(1) 1 +-- binv4_ex4_xuop_upd_q 1 +-- ex4_dir_access_op 4 +-- binv_wayB_upd2_q 1 +-- flush_wayB_data_q 6 +-- ldq_rel1_val 1 +-- ldq_rel_mid_val 1 +-- ldq_rel3_val 1 +-- ldq_rel_retry_val 1 +-- ldq_recirc_rel_val 1 +-- ldq_rel_set_val 1 +-- rel_way_dwen(1) 1 +-- rel_wayB_byp_ctrl_fxpipe 1 +-- rel_wayB_byp_ctrl_relpipe 1 + +-- ldq_rel_back_invalidated 1 +-- ldq_rel_tag 3 +-- rel_wayB_val 6 +-- rel_congr_cl_q 5 +-- reload_wayB_upd2_q 1 +-- reload_wayB_data_q 6 +-- Total 88 + +lsu_dbg_group3_0 <= lsu_dbg_way_0(1); +lsu_dbg_group3_1 <= lsu_dbg_way_1(1); +lsu_dbg_group3_2 <= lsu_dbg_way_2(1); +lsu_dbg_group3_3 <= lsu_dbg_way_3(1); +lsu_dbg_group3 <= lsu_dbg_group3_0 & lsu_dbg_group3_1 & lsu_dbg_group3_2 & lsu_dbg_group3_3; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Debug Bus 4 -> WayC Bypass +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- ex4_wayC_byp_ctrl_fxpipe 1 +-- ex4_wayC_byp_ctrl_relpipe 1 +-- ex4_wayC_val 6 +-- ex4_congr_cl_q 5 +-- ex4_p_addr 9 + +-- ex4_p_addr 22 + +-- ex4_way_hit_q(2) 1 +-- binv4_ex4_xuop_upd_q 1 +-- ex4_dir_access_op 4 +-- binv_wayC_upd2_q 1 +-- flush_wayC_data_q 6 +-- ldq_rel1_val 1 +-- ldq_rel_mid_val 1 +-- ldq_rel3_val 1 +-- ldq_rel_retry_val 1 +-- ldq_recirc_rel_val 1 +-- ldq_rel_set_val 1 +-- rel_way_dwen(2) 1 +-- rel_wayC_byp_ctrl_fxpipe 1 +-- rel_wayC_byp_ctrl_relpipe 1 + +-- ldq_rel_back_invalidated 1 +-- ldq_rel_tag 3 +-- rel_wayC_val 6 +-- rel_congr_cl_q 5 +-- reload_wayC_upd2_q 1 +-- reload_wayC_data_q 6 +-- Total 88 + +lsu_dbg_group4_0 <= lsu_dbg_way_0(2); +lsu_dbg_group4_1 <= lsu_dbg_way_1(2); +lsu_dbg_group4_2 <= lsu_dbg_way_2(2); +lsu_dbg_group4_3 <= lsu_dbg_way_3(2); +lsu_dbg_group4 <= lsu_dbg_group4_0 & lsu_dbg_group4_1 & lsu_dbg_group4_2 & lsu_dbg_group4_3; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Debug Bus 5 -> WayD Bypass +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- ex4_wayD_byp_ctrl_fxpipe 1 +-- ex4_wayD_byp_ctrl_relpipe 1 +-- ex4_wayD_val 6 +-- ex4_congr_cl_q 5 +-- ex4_p_addr 9 + +-- ex4_p_addr 22 + +-- ex4_way_hit_q(3) 1 +-- binv4_ex4_xuop_upd_q 1 +-- ex4_dir_access_op 4 +-- binv_wayD_upd2_q 1 +-- flush_wayD_data_q 6 +-- ldq_rel1_val 1 +-- ldq_rel_mid_val 1 +-- ldq_rel3_val 1 +-- ldq_rel_retry_val 1 +-- ldq_recirc_rel_val 1 +-- ldq_rel_set_val 1 +-- rel_way_dwen(3) 1 +-- rel_wayD_byp_ctrl_fxpipe 1 +-- rel_wayD_byp_ctrl_relpipe 1 + +-- ldq_rel_back_invalidated 1 +-- ldq_rel_tag 3 +-- rel_wayD_val 6 +-- rel_congr_cl_q 5 +-- reload_wayD_upd2_q 1 +-- reload_wayD_data_q 6 +-- Total 88 + +lsu_dbg_group5_0 <= lsu_dbg_way_0(3); +lsu_dbg_group5_1 <= lsu_dbg_way_1(3); +lsu_dbg_group5_2 <= lsu_dbg_way_2(3); +lsu_dbg_group5_3 <= lsu_dbg_way_3(3); +lsu_dbg_group5 <= lsu_dbg_group5_0 & lsu_dbg_group5_1 & lsu_dbg_group5_2 & lsu_dbg_group5_3; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Debug Bus 6 -> WayE Bypass +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- ex4_wayE_byp_ctrl_fxpipe 1 +-- ex4_wayE_byp_ctrl_relpipe 1 +-- ex4_wayE_val 6 +-- ex4_congr_cl_q 5 +-- ex4_p_addr 9 + +-- ex4_p_addr 22 + +-- ex4_way_hit_q(4) 1 +-- binv4_ex4_xuop_upd_q 1 +-- ex4_dir_access_op 4 +-- binv_wayE_upd2_q 1 +-- flush_wayE_data_q 6 +-- ldq_rel1_val 1 +-- ldq_rel_mid_val 1 +-- ldq_rel3_val 1 +-- ldq_rel_retry_val 1 +-- ldq_recirc_rel_val 1 +-- ldq_rel_set_val 1 +-- rel_way_dwen(4) 1 +-- rel_wayE_byp_ctrl_fxpipe 1 +-- rel_wayE_byp_ctrl_relpipe 1 + +-- ldq_rel_back_invalidated 1 +-- ldq_rel_tag 3 +-- rel_wayE_val 6 +-- rel_congr_cl_q 5 +-- reload_wayE_upd2_q 1 +-- reload_wayE_data_q 6 +-- Total 88 + +lsu_dbg_group6_0 <= lsu_dbg_way_0(4); +lsu_dbg_group6_1 <= lsu_dbg_way_1(4); +lsu_dbg_group6_2 <= lsu_dbg_way_2(4); +lsu_dbg_group6_3 <= lsu_dbg_way_3(4); +lsu_dbg_group6 <= lsu_dbg_group6_0 & lsu_dbg_group6_1 & lsu_dbg_group6_2 & lsu_dbg_group6_3; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Debug Bus 7 -> WayF Bypass +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- ex4_wayF_byp_ctrl_fxpipe 1 +-- ex4_wayF_byp_ctrl_relpipe 1 +-- ex4_wayF_val 6 +-- ex4_congr_cl_q 5 +-- ex4_p_addr 9 + +-- ex4_p_addr 22 + +-- ex4_way_hit_q(5) 1 +-- binv4_ex4_xuop_upd_q 1 +-- ex4_dir_access_op 4 +-- binv_wayF_upd2_q 1 +-- flush_wayF_data_q 6 +-- ldq_rel1_val 1 +-- ldq_rel_mid_val 1 +-- ldq_rel3_val 1 +-- ldq_rel_retry_val 1 +-- ldq_recirc_rel_val 1 +-- ldq_rel_set_val 1 +-- rel_way_dwen(5) 1 +-- rel_wayF_byp_ctrl_fxpipe 1 +-- rel_wayF_byp_ctrl_relpipe 1 + +-- ldq_rel_back_invalidated 1 +-- ldq_rel_tag 3 +-- rel_wayF_val 6 +-- rel_congr_cl_q 5 +-- reload_wayF_upd2_q 1 +-- reload_wayF_data_q 6 +-- Total 88 + +lsu_dbg_group7_0 <= lsu_dbg_way_0(5); +lsu_dbg_group7_1 <= lsu_dbg_way_1(5); +lsu_dbg_group7_2 <= lsu_dbg_way_2(5); +lsu_dbg_group7_3 <= lsu_dbg_way_3(5); +lsu_dbg_group7 <= lsu_dbg_group7_0 & lsu_dbg_group7_1 & lsu_dbg_group7_2 & lsu_dbg_group7_3; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Debug Bus 8 -> WayG Bypass +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- ex4_wayG_byp_ctrl_fxpipe 1 +-- ex4_wayG_byp_ctrl_relpipe 1 +-- ex4_wayG_val 6 +-- ex4_congr_cl_q 5 +-- ex4_p_addr 9 + +-- ex4_p_addr 22 + +-- ex4_way_hit_q(6) 1 +-- binv4_ex4_xuop_upd_q 1 +-- ex4_dir_access_op 4 +-- binv_wayG_upd2_q 1 +-- flush_wayG_data_q 6 +-- ldq_rel1_val 1 +-- ldq_rel_mid_val 1 +-- ldq_rel3_val 1 +-- ldq_rel_retry_val 1 +-- ldq_recirc_rel_val 1 +-- ldq_rel_set_val 1 +-- rel_way_dwen(6) 1 +-- rel_wayG_byp_ctrl_fxpipe 1 +-- rel_wayG_byp_ctrl_relpipe 1 + +-- ldq_rel_back_invalidated 1 +-- ldq_rel_tag 3 +-- rel_wayG_val 6 +-- rel_congr_cl_q 5 +-- reload_wayG_upd2_q 1 +-- reload_wayG_data_q 6 +-- Total 88 + +lsu_dbg_group8_0 <= lsu_dbg_way_0(6); +lsu_dbg_group8_1 <= lsu_dbg_way_1(6); +lsu_dbg_group8_2 <= lsu_dbg_way_2(6); +lsu_dbg_group8_3 <= lsu_dbg_way_3(6); +lsu_dbg_group8 <= lsu_dbg_group8_0 & lsu_dbg_group8_1 & lsu_dbg_group8_2 & lsu_dbg_group8_3; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Debug Bus 9 -> WayH Bypass +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- ex4_wayH_byp_ctrl_fxpipe 1 +-- ex4_wayH_byp_ctrl_relpipe 1 +-- ex4_wayH_val 6 +-- ex4_congr_cl_q 5 +-- ex4_p_addr 9 + +-- ex4_p_addr 22 + +-- ex4_way_hit_q(7) 1 +-- binv4_ex4_xuop_upd_q 1 +-- ex4_dir_access_op 4 +-- binv_wayH_upd2_q 1 +-- flush_wayH_data_q 6 +-- ldq_rel1_val 1 +-- ldq_rel_mid_val 1 +-- ldq_rel3_val 1 +-- ldq_rel_retry_val 1 +-- ldq_recirc_rel_val 1 +-- ldq_rel_set_val 1 +-- rel_way_dwen(7) 1 +-- rel_wayH_byp_ctrl_fxpipe 1 +-- rel_wayH_byp_ctrl_relpipe 1 + +-- ldq_rel_back_invalidated 1 +-- ldq_rel_tag 3 +-- rel_wayH_val 6 +-- rel_congr_cl_q 5 +-- reload_wayH_upd2_q 1 +-- reload_wayH_data_q 6 +-- Total 88 + +lsu_dbg_group9_0 <= lsu_dbg_way_0(7); +lsu_dbg_group9_1 <= lsu_dbg_way_1(7); +lsu_dbg_group9_2 <= lsu_dbg_way_2(7); +lsu_dbg_group9_3 <= lsu_dbg_way_3(7); +lsu_dbg_group9 <= lsu_dbg_group9_0 & lsu_dbg_group9_1 & lsu_dbg_group9_2 & lsu_dbg_group9_3; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Debug Bus 10 -> General Reload +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- ldq_rel1_val 1 +-- ldq_rel_mid_val 1 +-- ldq_rel3_val 1 +-- ldq_rel_retry_val 1 +-- ldq_recirc_rel_val 1 +-- ldq_rel_tag 3 +-- ldq_rel_set_val 1 +-- ldq_rel_ci 1 +-- ldq_rel_back_invalidated 1 +-- ldq_rel_upd_gpr 1 +-- rel_data_val 1 +-- ldq_rel_ta_gpr(0:8) 9 + +-- ldq_rel_lock_en 1 +-- ldq_rel_watch_en 1 +-- ldq_rel_axu_val 1 +-- ldq_rel_classid 2 +-- spr_xucr0_dcdis_q 1 +-- rel24_way_dwen_stg_q 8 +-- rel_val_wen_q 1 +-- rel_lru_val_q 7 + +-- rel_m_q_way_q 8 +-- ldq_rel_addr 14 + +-- ldq_rel_addr 22 +-- Total 88 + +lsu_dbg_group10_0 <= dc_dir_dbg_data(0) & dc_dir_dbg_data(1) & dc_dir_dbg_data(2) & dc_lru_dbg_data(80) & + dc_val_dbg_data(275) & dc_lru_dbg_data(77 to 79) & dc_dir_dbg_data(4) & dc_fgen_dbg_data(0) & + dc_val_dbg_data(274) & dc_cntrl_dbg_data(0) & dc_dir_dbg_data(3) & dc_cntrl_dbg_data(1 to 9); + +lsu_dbg_group10_1 <= dc_val_dbg_data(272) & dc_val_dbg_data(273) & dc_cntrl_dbg_data(10) & dc_lru_dbg_data(75 to 76) & + dc_cntrl_dbg_data(11) & dc_lru_dbg_data(0 to 7) & dc_lru_dbg_data(44) & dc_lru_dbg_data(52 to 58); + +lsu_dbg_group10_2 <= dc_lru_dbg_data(16 to 23) & dc_dir_dbg_data(5 to 18); + +lsu_dbg_group10_3 <= dc_dir_dbg_data(19 to 35) & dc_val_dbg_data(21 to 25); + +lsu_dbg_group10 <= lsu_dbg_group10_0 & lsu_dbg_group10_1 & lsu_dbg_group10_2 & lsu_dbg_group10_3; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Debug Bus 11 -> General Reload Queue +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- ldq_rel1_val 1 +-- ldq_rel_mid_val 1 +-- ldq_rel3_val 1 +-- ldq_rel_retry_val 1 +-- ldq_recirc_rel_val 1 +-- ldq_rel_tag 3 +-- ldq_rel_set_val 1 +-- ldq_rel_ci 1 +-- ldq_rel_back_invalidated 1 +-- ldq_rel_ta_gpr(7:8) 2 +-- ldq_rel_lock_en 1 +-- ldq_rel_classid 2 +-- spr_xucr0_dcdis_q 1 +-- xucr0_clo_q 1 +-- reld_q_val(0:3) 4 + +-- reld_q_val(4:7) 4 +-- rel_m_q_upd 1 <-- Whats up with that +-- reld_q_early_byp 1 <-- Whats up with that +-- rel_m_q_way_q 8 +-- rel2_wlock_q 8 + +-- rel_way_dwen 8 +-- ldq_rel_addr 14 + +-- ldq_rel_addr 22 +-- Total 88 + +lsu_dbg_group11_0 <= dc_dir_dbg_data(0) & dc_dir_dbg_data(1) & dc_dir_dbg_data(2) & dc_lru_dbg_data(80) & + dc_val_dbg_data(275) & dc_lru_dbg_data(77 to 79) & dc_dir_dbg_data(4) & dc_fgen_dbg_data(0) & + dc_val_dbg_data(274) & dc_cntrl_dbg_data(8 to 9) & dc_val_dbg_data(272) & dc_lru_dbg_data(75 to 76) & + dc_cntrl_dbg_data(11) & dc_lru_dbg_data(59) & dc_lru_dbg_data(8 to 11); + +lsu_dbg_group11_1 <= dc_lru_dbg_data(12 to 15) & '0' & '0' & dc_lru_dbg_data(16 to 23) & dc_lru_dbg_data(24 to 31); + +lsu_dbg_group11_2 <= dc_lru_dbg_data(0 to 7) & dc_dir_dbg_data(5 to 18); + +lsu_dbg_group11_3 <= dc_dir_dbg_data(19 to 35) & dc_val_dbg_data(21 to 25); + +lsu_dbg_group11 <= lsu_dbg_group11_0 & lsu_dbg_group11_1 & lsu_dbg_group11_2 & lsu_dbg_group11_3; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Debug Bus 12 -> General LRU +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- ldq_rel1_val 1 +-- ldq_rel_tag 3 +-- ldq_rel_classid 2 +-- rel_fxubyp_val 1 +-- rel_relbyp_val 1 +-- rel_congr_cl_q 5 +-- rel2_wlock_q 8 +-- rel_val_wen_q 1 + +-- way_not_empty 8 +-- rel_op_lru 7 +-- rel_lru_val_q 7 + +-- rel_way_dwen 8 +-- xucr0_clo_q 1 +-- ex4_congr_cl_q 5 +-- xu_op_lru 7 +-- ex6_c_acc_val_q 1 + +-- ex6_lru_upd_q 7 +-- ex4_way_hit_q 8 +-- ex4_c_acc_q 1 +-- spr_xucr0_dcdis_q 1 +-- ex4_fxubyp_val 1 +-- ex4_relbyp_val 1 +-- Total 85 + +lsu_dbg_group12_0 <= dc_dir_dbg_data(0) & dc_lru_dbg_data(77 to 79) & dc_lru_dbg_data(75 to 76) & dc_lru_dbg_data(42 to 43) & + dc_val_dbg_data(221 to 225) & dc_lru_dbg_data(24 to 31) & dc_lru_dbg_data(44); + +lsu_dbg_group12_1 <= dc_lru_dbg_data(32 to 39) & dc_lru_dbg_data(45 to 51) & dc_lru_dbg_data(52 to 58); + +lsu_dbg_group12_2 <= dc_lru_dbg_data(0 to 7) & dc_lru_dbg_data(59) & dc_val_dbg_data(216 to 220) & dc_lru_dbg_data(60 to 66) & + dc_lru_dbg_data(67); + +lsu_dbg_group12_3 <= dc_lru_dbg_data(68 to 74) & dc_val_dbg_data(208 to 215) & dc_lru_dbg_data(81) & dc_cntrl_dbg_data(11) & + dc_lru_dbg_data(40 to 41) & "000"; + +lsu_dbg_group12 <= lsu_dbg_group12_0 & lsu_dbg_group12_1 & lsu_dbg_group12_2 & lsu_dbg_group12_3; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Debug Bus 13 -> Data Cache Parity Error Recovery +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- ex9_ld_par_err_q 1 +-- rel_in_progress 1 +-- dcpar_err_ind_sel 2 +-- dcpar_err_cntr_q 2 +-- dcpar_err_push_queue 1 +-- dcpar_err_way_q 8 +-- dcpar_err_stg2_q 1 +-- ldq_rel1_val 1 +-- ldq_rel_mid_val 1 +-- ldq_rel3_val 1 +-- ldq_rel_tag 3 + +-- rel_congr_cl_q 5 +-- pe_recov_begin 1 +-- l2req_resend_l2 1 +-- l2req_recycle_l2 & 1 +-- ex6_ld_recov_val_l2 & 1 +-- ex6_ld_recov_extra_l2(0) & 1 +-- ex7_ld_recov_val_l2 & 1 +-- ex7_ld_recov_extra_l2(0) & 1 +-- stq_hit_ex6_recov_l2 1 +-- pe_recov_state_l2 1 +-- blk_ld_for_pe_recov_l2 1 +-- ex7_ld_recov_l2(1 to 6) 6 +-- ex7_ld_recov_l2(18) 1 + +-- ex7_ld_recov_l2(19 to 21) 3 +-- ex7_ld_recov_l2(53 to 71) 18 + +-- ex7_ld_recov_l2(72 to 93) 22 +-- Total 88 + +lsu_dbg_group13_0 <= dc_val_dbg_data(277) & dc_val_dbg_data(278) & dc_val_dbg_data(279 to 280) & dc_val_dbg_data(281 to 282) & + dc_val_dbg_data(283) & dc_val_dbg_data(284 to 291) & dc_val_dbg_data(292) & dc_dir_dbg_data(0) & + dc_dir_dbg_data(1) & dc_dir_dbg_data(2) & dc_lru_dbg_data(77 to 79); + +lsu_dbg_group13_1 <= dc_val_dbg_data(221 to 225) & pe_recov_begin & lmq_dbg_dcache_pe(1 to 6) & lmq_dbg_dcache_pe(58 to 60) & + lmq_dbg_dcache_pe(7 to 13); + +lsu_dbg_group13_2 <= lmq_dbg_dcache_pe(14 to 35); + +lsu_dbg_group13_3 <= lmq_dbg_dcache_pe(36 to 57); + +lsu_dbg_group13 <= lsu_dbg_group13_0 & lsu_dbg_group13_1 & lsu_dbg_group13_2 & lsu_dbg_group13_3; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Debug Bus 14 -> L2 Request General +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +-- l2req_l2 1 +-- l2req_ld_core_tag_l2 5 +-- l2req_ttype_l2 6 +-- l2req_wimg_l2 4 +-- l2req_endian_l2 1 +-- l2req_ld_xfr_len_l2 3 +-- l2req_thread_l2(0:1) 2 + +-- l2req_thread_l2(2) 1 +-- l2req_user_l2 4 +-- anaclat_data_coming 1 +-- anaclat_data_val 1 +-- an_ac_reld_crit_qw 1 +-- anaclat_ditc 1 +-- anaclat_l1_dump 1 +-- anaclat_tag 4 +-- anaclat_qw 2 +-- anaclat_ecc_err 1 +-- anaclat_ecc_err_ue 1 +-- anaclat_ld_pop 1 +-- anaclat_st_gather 1 +-- anaclat_st_pop 1 +-- anaclat_st_pop_thrd(0) 1 + +-- anaclat_st_pop_thrd(1:2) 2 +-- l2req_ra_l2(22:41) 19 + +-- l2req_ra_l2(42:63) 22 +-- Total 88 + +lsu_dbg_group14_0 <= lmq_dbg_l2req(0 to 5) & lmq_dbg_l2req(67 to 77) & lmq_dbg_l2req(82 to 84) & lmq_dbg_l2req(64 to 65); + +lsu_dbg_group14_1 <= lmq_dbg_l2req(66) & lmq_dbg_l2req(78 to 81) & lmq_dbg_rel(0 to 12) & lmq_dbg_pops(0 to 3); + +lsu_dbg_group14_2 <= lmq_dbg_pops(4 to 5) & lmq_dbg_l2req(6 to 25); + +lsu_dbg_group14_3 <= lmq_dbg_l2req(26 to 47); + +lsu_dbg_group14 <= lsu_dbg_group14_0 & lsu_dbg_group14_1 & lsu_dbg_group14_2 & lsu_dbg_group14_3; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Debug Bus 15 -> L2 Request Store Data0 +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +-- l2req_l2 1 +-- l2req_ttype_l2 6 +-- l2req_wimg_l2(1) 1 +-- l2req_wimg_l2(3) 1 +-- l2req_endian_l2 1 +-- l2req_st_byte_enbl_l2(0:3) 4 +-- l2req_ra_l2(22:29) 8 + +-- l2req_ra_l2(30:51) 22 + +-- l2req_ra_l2(52:63) 12 +-- ex6_st_data_l2(0:9) 10 + +-- ex6_st_data_l2(10:31) 22 +-- Total 88 + +dataDbgGen : for w in 0 to 3 generate begin + l2cmdq_dbg_data_0(w) <= lmq_dbg_l2req(0) & lmq_dbg_l2req(67 to 72) & lmq_dbg_l2req(74) & lmq_dbg_l2req(76 to 77) & lmq_dbg_l2req(48+(4*w) to 51+(4*w)) & lmq_dbg_l2req(6 to 13); + l2cmdq_dbg_data_1(w) <= lmq_dbg_l2req(14 to 35); + l2cmdq_dbg_data_2(w) <= lmq_dbg_l2req(36 to 47) & lmq_dbg_l2req(85+(32*w) to 94+(32*w)); + l2cmdq_dbg_data_3(w) <= lmq_dbg_l2req(95+(32*w) to 116+(32*w)); +end generate dataDbgGen; + + +lsu_dbg_group15_0 <= l2cmdq_dbg_data_0(0); +lsu_dbg_group15_1 <= l2cmdq_dbg_data_1(0); +lsu_dbg_group15_2 <= l2cmdq_dbg_data_2(0); +lsu_dbg_group15_3 <= l2cmdq_dbg_data_3(0); +lsu_dbg_group15 <= lsu_dbg_group15_0 & lsu_dbg_group15_1 & lsu_dbg_group15_2 & lsu_dbg_group15_3; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Debug Bus 16 -> L2 Request Store Data1 +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +-- l2req_l2 1 +-- l2req_ttype_l2 6 +-- l2req_wimg_l2(1) 1 +-- l2req_wimg_l2(3) 1 +-- l2req_endian_l2 1 +-- l2req_st_byte_enbl_l2(4:7) 4 +-- l2req_ra_l2(22:29) 8 + +-- l2req_ra_l2(30:51) 22 + +-- l2req_ra_l2(52:63) 12 +-- ex6_st_data_l2(32:41) 10 + +-- ex6_st_data_l2(42:63) 22 +-- Total 88 + +lsu_dbg_group16_0 <= l2cmdq_dbg_data_0(1); +lsu_dbg_group16_1 <= l2cmdq_dbg_data_1(1); +lsu_dbg_group16_2 <= l2cmdq_dbg_data_2(1); +lsu_dbg_group16_3 <= l2cmdq_dbg_data_3(1); +lsu_dbg_group16 <= lsu_dbg_group16_0 & lsu_dbg_group16_1 & lsu_dbg_group16_2 & lsu_dbg_group16_3; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Debug Bus 17 -> L2 Request Store Data2 +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +-- l2req_l2 1 +-- l2req_ttype_l2 6 +-- l2req_wimg_l2(1) 1 +-- l2req_wimg_l2(3) 1 +-- l2req_endian_l2 1 +-- l2req_st_byte_enbl_l2(8:11) 4 +-- l2req_ra_l2(22:29) 8 + +-- l2req_ra_l2(30:51) 22 + +-- l2req_ra_l2(52:63) 12 +-- ex6_st_data_l2(64:73) 10 + +-- ex6_st_data_l2(74:95) 22 +-- Total 88 + +lsu_dbg_group17_0 <= l2cmdq_dbg_data_0(2); +lsu_dbg_group17_1 <= l2cmdq_dbg_data_1(2); +lsu_dbg_group17_2 <= l2cmdq_dbg_data_2(2); +lsu_dbg_group17_3 <= l2cmdq_dbg_data_3(2); +lsu_dbg_group17 <= lsu_dbg_group17_0 & lsu_dbg_group17_1 & lsu_dbg_group17_2 & lsu_dbg_group17_3; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Debug Bus 18 -> L2 Request Store Data3 +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +-- l2req_l2 1 +-- l2req_ttype_l2 6 +-- l2req_wimg_l2(1) 1 +-- l2req_wimg_l2(3) 1 +-- l2req_endian_l2 1 +-- l2req_st_byte_enbl_l2(12:15) 4 +-- l2req_ra_l2(22:29) 8 + +-- l2req_ra_l2(30:51) 22 + +-- l2req_ra_l2(52:63) 12 +-- ex6_st_data_l2(96:105) 10 + +-- ex6_st_data_l2(106:127) 22 +-- Total 88 + +lsu_dbg_group18_0 <= l2cmdq_dbg_data_0(3); +lsu_dbg_group18_1 <= l2cmdq_dbg_data_1(3); +lsu_dbg_group18_2 <= l2cmdq_dbg_data_2(3); +lsu_dbg_group18_3 <= l2cmdq_dbg_data_3(3); +lsu_dbg_group18 <= lsu_dbg_group18_0 & lsu_dbg_group18_1 & lsu_dbg_group18_2 & lsu_dbg_group18_3; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Debug Bus 19 -> L2 Reload Interface0 +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +-- l2req_l2 1 +-- l2req_ld_core_tag_l2(1:4) 4 +-- l2req_ttype_l2 6 +-- l2req_wimg_l2(1) 1 +-- anaclat_data_coming 1 +-- anaclat_data_val 1 +-- an_ac_reld_crit_qw 1 +-- anaclat_ditc 1 +-- anaclat_tag 4 +-- anaclat_qw 2 + +-- anaclat_ecc_err 1 +-- anaclat_ecc_err_ue 1 +-- anaclat_data(0:19) 20 + +-- anaclat_data(20:41) 22 + +-- anaclat_data(42:63) 22 +-- Total 88 + +lsu_dbg_group19_0 <= lmq_dbg_l2req(0) & lmq_dbg_l2req(2 to 5) & lmq_dbg_l2req(67 to 72) & lmq_dbg_l2req(74) & lmq_dbg_rel(0 to 3) & lmq_dbg_rel(5 to 10); +lsu_dbg_group19_1 <= lmq_dbg_rel(11 to 12) & lmq_dbg_rel(13 to 32); +lsu_dbg_group19_2 <= lmq_dbg_rel(33 to 54); +lsu_dbg_group19_3 <= lmq_dbg_rel(55 to 76); +lsu_dbg_group19 <= lsu_dbg_group19_0 & lsu_dbg_group19_1 & lsu_dbg_group19_2 & lsu_dbg_group19_3; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Debug Bus 20 -> L2 Reload Interface1 +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +-- l2req_l2 1 +-- l2req_ld_core_tag_l2(1:4) 4 +-- l2req_ttype_l2 6 +-- l2req_wimg_l2(1) 1 +-- anaclat_data_coming 1 +-- anaclat_data_val 1 +-- an_ac_reld_crit_qw 1 +-- anaclat_ditc 1 +-- anaclat_tag 4 +-- anaclat_qw 2 + +-- anaclat_ecc_err 1 +-- anaclat_ecc_err_ue 1 +-- anaclat_data(0:19) 20 + +-- anaclat_data(20:41) 22 + +-- anaclat_data(42:63) 22 +-- Total 88 + +lsu_dbg_group20_0 <= lmq_dbg_l2req(0) & lmq_dbg_l2req(2 to 5) & lmq_dbg_l2req(67 to 72) & lmq_dbg_l2req(74) & lmq_dbg_rel(0 to 3) & lmq_dbg_rel(5 to 10); +lsu_dbg_group20_1 <= lmq_dbg_rel(11 to 12) & lmq_dbg_rel(77 to 96); +lsu_dbg_group20_2 <= lmq_dbg_rel(97 to 118); +lsu_dbg_group20_3 <= lmq_dbg_rel(119 to 140); +lsu_dbg_group20 <= lsu_dbg_group20_0 & lsu_dbg_group20_1 & lsu_dbg_group20_2 & lsu_dbg_group20_3; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Debug Bus 21 -> Back Invalidate Interface +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +-- anaclat_back_inv_addr(22:43) 22 + +-- anaclat_back_inv_addr(44:63) 20 +-- anaclat_back_inv_target_1 1 +-- anaclat_back_inv_target_4 1 + +-- anaclat_back_inv 1 +-- lmq_back_invalidated_l2 8 +-- ex4_way_hit_q 8 +-- ex4_congr_cl_q 5 + +-- binv4_ex4_xuop_upd_q 1 +-- ex4_p_addr 21 +-- Total 88 + +lsu_dbg_group21_0 <= lmq_dbg_binv(1 to 22); +lsu_dbg_group21_1 <= lmq_dbg_binv(23 to 42) & lmq_dbg_binv(43 to 44); +lsu_dbg_group21_2 <= lmq_dbg_binv(0) & lmq_dbg_grp0(40 to 47) & dc_val_dbg_data(208 to 215) & dc_val_dbg_data(216 to 220); +lsu_dbg_group21_3 <= dc_val_dbg_data(293) & dc_cntrl_dbg_data(40 to 60); +lsu_dbg_group21 <= lsu_dbg_group21_0 & lsu_dbg_group21_1 & lsu_dbg_group21_2 & lsu_dbg_group21_3; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Debug Bus 22 -> LoadmissQ Debug Group0 +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +--lmq_dbg_grp0 <= l_m_rel_hit_beat0_l2 & --(0:7) +-- l_m_rel_hit_beat1_l2 & --(8:15) +-- l_m_rel_hit_beat2_l2 & --(16:23) +-- l_m_rel_hit_beat3_l2 & --(24:31) +-- l_m_rel_val_c_i_dly & --(32:39) +-- lmq_back_invalidated_l2(0 to lmq_entries-1) & --(40:47) +-- complete_qentry(0 to lmq_entries-1) & --(48:55) +-- ldq_retry_l2(0 to lmq_entries-1) & --(56:63) +-- retry_started_l2(0 to lmq_entries-1) & --(64:71) +-- gpr_ecc_err_l2(0 to lmq_entries-1) & --(78:85) +-- "00"; --(86:87) + +lmq_dbg_rel_ctrl <= dc_dir_dbg_data(3) & dc_dir_dbg_data(0 to 2) & dc_cntrl_dbg_data(0) & dc_dir_dbg_data(4); + +lsu_dbg_group22 <= lmq_dbg_grp0(0 to 71) & lmq_dbg_rel_ctrl & lmq_dbg_grp0(72 to 81); + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Debug Bus 23 -> LoadmissQ Debug Group1 +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +--lmq_dbg_grp1 <= l_m_rel_hit_beat0_l2 & --(0:7) +-- l_m_rel_hit_beat1_l2 & --(8:15) +-- l_m_rel_hit_beat2_l2 & --(16:23) +-- l_m_rel_hit_beat3_l2 & --(24:31) +-- l_m_rel_val_c_i_dly & --(32:39) +-- gpr_ecc_err_l2(0 to lmq_entries-1) & --(40:47) +-- data_ecc_err_l2(0 to lmq_entries-1) & --(48:55) +-- data_ecc_ue_l2(0 to lmq_entries-1) & --(56:63) +-- gpr_updated_prev_l2(0 to lmq_entries-1) & --(64:71) +-- anaclat_data_val & --(78) +-- anaclat_reld_crit_qw & --(79) +-- anaclat_tag(1 to 4) & --(80:83) +-- anaclat_qw(58 to 59) & --(84:85) +-- anaclat_ecc_err & --(86) +-- anaclat_ecc_err_ue; --(87) + + +lsu_dbg_group23 <= lmq_dbg_grp1(0 to 71) & lmq_dbg_rel_ctrl & lmq_dbg_grp1(72 to 81); + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Debug Bus 24 -> LoadmissQ Debug Group2 +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +--lmq_dbg_grp2 <= I1_G1_flush & --(0) +-- ld_queue_full & --(1) +-- ex4_drop_ld_req & --(2) +-- ex5_flush_l2 & --(3) +-- ex5_stg_flush & --(4) +-- cmd_type_ld(0 to 5) & --(5:10) +-- ex4_loadmiss_qentry(0 to lmq_entries-1) & --(11:18) +-- ld_entry_val_l2(0 to lmq_entries-1) & --(19:26) +-- ld_rel_val_l2(0 to lmq_entries-1) & --(27:34) +-- ex4_lmq_cpy_l2(0 to lmq_entries-1) & --(35:42) +-- send_if_req_l2 & --(43) +-- send_ld_req_l2 & --(44) +-- send_mm_req_l2 & --(45) +-- load_cmd_count_l2 & --(46:49) +-- load_sent & --(50) +-- load_flushed & --(51) +-- selected_entry_flushed & --(52) +-- ex6_load_sent_l2 & --(53) +-- ex6_flush_l2 & --(54) +-- cmd_seq_l2 & --(55:59) +-- l_q_rd_en & --(60:67) +-- rd_seq_num_skip & --(68) +-- lq_rd_en_is_ex5 & --(69) +-- lq_rd_en_is_ex6 & --(70) +-- l_m_q_hit_st_l2(0 to lmq_entries-1) & --(71:78) +-- lmq_drop_rel_l2(0 to lmq_entries-1) & --(79:86) +-- '0'; --(87) + +lsu_dbg_group24 <= lmq_dbg_grp2; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Debug Bus 25 -> LoadmissQ Debug Group3 +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +--lmq_dbg_grp3 <= sync_flush & --(0) +-- flush_if_store & --(1) +-- I1_G1_flush & --(2) +-- l_m_fnd_stg & --(3) +-- ex5_flush_l2 & --(4) +-- ex5_stg_flush & --(5) +-- ex4_st_val_l2 & --(6) +-- st_entry0_val_l2 & --(7) +-- s_m_queue0(0 to 5) & --(8:13) +-- s_m_queue0(58 to (58+real_data_add-6-1)) & --(14:49) +-- store_cmd_count_l2 & --(50:55) +-- ex5_sel_st_req & --(56) +-- store_sent & --(57) +-- ex6_store_sent_l2 & --(58) +-- ex6_flush_l2 & --(59) +-- l2req_l2 & --(60) +-- l2req_thread_l2 & --(61:63) +-- l2req_ttype_l2 & --(64:69) +-- ob_req_val_l2 & --(70) +-- ob_ditc_val_l2 & --(71) +-- "0000000000000000"; --(72:87) + +lsu_dbg_group25 <= lmq_dbg_grp3; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Debug Bus 26 -> LoadmissQ Debug Group4 +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + + +lsu_dbg_group26 <= (others=>'0'); + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Debug Bus 27 -> LoadmissQ Debug Group5 +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +--lmq_dbg_grp5 <= mm_req_val_l2 & --(0) +-- mmu_q_val_l2 & --(1) +-- mmu_q_entry_l2 & --(2:69) +-- send_if_req_l2 & --(70) +-- send_ld_req_l2 & --(71) +-- send_mm_req_l2 & --(72) +-- mmu_sent & --(73) +-- l2req_l2 & --(74) +-- l2req_thread_l2 & --(75:77) +-- l2req_ttype_l2 & --(78:83) +-- "0000"; + +lsu_dbg_group27 <= lmq_dbg_grp5; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Debug Bus 28 -> LoadmissQ Debug Group6 +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +--lmq_dbg_grp6 <= ex3_stg_flush & --(0) +-- I1_G1_flush & --(1) +-- sync_flush & --(2) +-- flush_if_store & --(3) +-- ld_queue_full & --(4) +-- ex4_drop_ld_req & --(5) +-- l_m_fnd_stg & --(6) +-- ex4_stg_flush & --(7) +-- my_ex4_flush_l2 & --(8) +-- ex5_stg_flush & --(9) +-- ex2_lm_dep_hit_buf & --(10) +-- ex3_load_instr & --(11) +-- ex3_thrd_id(0 to 3) & --(12:15) +-- cmd_type_st(0 to 5) & --(16:21) +-- cmd_type_ld(0 to 5) & --(22:27) +-- ex4_lmq_cpy_l2(0 to lmq_entries-1) & --(28:35) +-- lmq_collision_t0_l2(0 to lmq_entries-1) & --(36:43) +-- lmq_collision_t1_l2(0 to lmq_entries-1) & --(44:51) +-- lmq_collision_t2_l2(0 to lmq_entries-1) & --(52:59) +-- lmq_collision_t3_l2(0 to lmq_entries-1) & --(60:67) +-- ldq_barr_active_l2(0 to 3) & --(68:71) +-- ldq_barr_done_l2(0 to 3) & --(72:75) +-- sync_done_tid_l2(0 to 3) & --(76:79) +-- "00000000"; + +lsu_dbg_group28 <= lmq_dbg_grp6; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Debug Bus 29 -> Directory Access +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +-- dir_wr_enable_int 4 +-- dir_wr_way_int 8 +-- dir_arr_wr_addr_int 5 +-- recirc_rel_val_q 1 +-- dir_arr_wr_data_int(31:34) 4 + +-- ex1_dir_acc_val 1 +-- ex1_l2_inv_val 1 +-- binv1_ex1_stg_act 1 +-- lwr_p_addr_q(53:57) 5 +-- dir_arr_wr_data_int(0:13) 14 + +-- dir_arr_wr_data_int(14:30) 17 +-- 0 5 + +-- 0 22 + +--dir_arr_dbg_data <= dir_wr_enable_int & dir_wr_way_int & dir_arr_wr_addr_int & dir_arr_wr_data_int & --(0:51) +-- ex1_dir_acc_val & ex1_l2_inv_val & binv1_ex1_stg_act & recirc_rel_val_q & --(52:55) +-- lwr_p_addr_q(53:57); --(56:60) + + +lsu_dbg_group29_0 <= dir_arr_dbg_data(0 to 16) & dir_arr_dbg_data(55) & dir_arr_dbg_data(48 to 51); +lsu_dbg_group29_1 <= dir_arr_dbg_data(52 to 54) & dir_arr_dbg_data(56 to 60) & dir_arr_dbg_data(17 to 30); +lsu_dbg_group29_2 <= dir_arr_dbg_data(31 to 47) & "00000"; +lsu_dbg_group29_3 <= (others=>'0'); +lsu_dbg_group29 <= lsu_dbg_group29_0 & lsu_dbg_group29_1 & lsu_dbg_group29_2 & lsu_dbg_group29_3; +lsu_dbg_group30 <= derat_xu_debug_group0; +lsu_dbg_group31 <= derat_xu_debug_group1; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Trigger Bus 0 -> Instruction Pipe +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +-- binv4_ex4_xuop_upd_q 1 +-- ex4_enc_thdid 2 +-- ex2_is_mem_bar_op 1 +-- ex3_l2_op_q 1 +-- ex4_n_flush_rq_q 1 +-- ex4_miss 1 +-- ex5_cache_inh_q 1 +-- ex4_dir_access_op 4 + +lsu_trg_group0 <= dc_val_dbg_data(293) & dc_cntrl_dbg_data(65 to 66) & dc_cntrl_dbg_data(22 to 23) & dc_fgen_dbg_data(1) & + dc_cntrl_dbg_data(12) & dc_cntrl_dbg_data(26) & dc_val_dbg_data(226 to 229); + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Trigger Bus 1 -> L2 Request +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +-- l2req_l2 1 +-- l2req_thread_l2(0:1) 2 +-- l2req_ttype_l2 6 +-- l2req_wimg_l2(1:3) 3 + +lsu_trg_group1 <= lmq_dbg_l2req(0) & lmq_dbg_l2req(64 to 65) & lmq_dbg_l2req(67 to 72) & lmq_dbg_l2req(74 to 76); + +lsu_trg_group2 <= (others=>'0'); +lsu_trg_group3 <= (others=>'0'); + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Pass Thru/Swap Muxing +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +dbg : entity work.xuq_debug_mux32(xuq_debug_mux32) +port map( + + -- PC Debug Control + trace_bus_enable => trace_bus_enable_q, + trace_unit_sel => trace_unit_sel, + + -- Pass Thru Debug Trace Bus + debug_data_in => debug_data_in, + trigger_data_in => trigger_data_in, + + -- Debug Data In + dbg_group0 => lsu_dbg_group0, + dbg_group1 => lsu_dbg_group1, + dbg_group2 => lsu_dbg_group2, + dbg_group3 => lsu_dbg_group3, + dbg_group4 => lsu_dbg_group4, + dbg_group5 => lsu_dbg_group5, + dbg_group6 => lsu_dbg_group6, + dbg_group7 => lsu_dbg_group7, + dbg_group8 => lsu_dbg_group8, + dbg_group9 => lsu_dbg_group9, + dbg_group10 => lsu_dbg_group10, + dbg_group11 => lsu_dbg_group11, + dbg_group12 => lsu_dbg_group12, + dbg_group13 => lsu_dbg_group13, + dbg_group14 => lsu_dbg_group14, + dbg_group15 => lsu_dbg_group15, + dbg_group16 => lsu_dbg_group16, + dbg_group17 => lsu_dbg_group17, + dbg_group18 => lsu_dbg_group18, + dbg_group19 => lsu_dbg_group19, + dbg_group20 => lsu_dbg_group20, + dbg_group21 => lsu_dbg_group21, + dbg_group22 => lsu_dbg_group22, + dbg_group23 => lsu_dbg_group23, + dbg_group24 => lsu_dbg_group24, + dbg_group25 => lsu_dbg_group25, + dbg_group26 => lsu_dbg_group26, + dbg_group27 => lsu_dbg_group27, + dbg_group28 => lsu_dbg_group28, + dbg_group29 => lsu_dbg_group29, + dbg_group30 => lsu_dbg_group30, + dbg_group31 => lsu_dbg_group31, + + -- Trigger Data In + trg_group0 => lsu_trg_group0, + trg_group1 => lsu_trg_group1, + trg_group2 => lsu_trg_group2, + trg_group3 => lsu_trg_group3, + + -- Outputs + trigger_data_out => trigger_data_out, + debug_data_out => debug_data_out, + + -- Power + vdd => vdd, + gnd => gnd, + nclk => nclk, + sg_0 => sg_0, + func_slp_sl_thold_0_b => func_slp_sl_thold_0_b, + func_slp_sl_force => func_slp_sl_force, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc, + mpw1_dc_b => mpw1_dc_b, + mpw2_dc_b => mpw2_dc_b, + scan_in => scan_in, + scan_out => dbg_scan_out +); + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Registers +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +trace_bus_enable_latch : tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 0) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(trace_bus_enable_offset), + scout => sov(trace_bus_enable_offset), + din => pc_xu_trace_bus_enable, + dout => trace_bus_enable_q); +ex3_instr_trace_val_latch : tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 0) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_instr_trace_val_offset), + scout => sov(ex3_instr_trace_val_offset), + din => ex3_instr_trace_val_d, + dout => ex3_instr_trace_val_q); +ex4_instr_trace_val_latch : tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 0) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_instr_trace_val_offset), + scout => sov(ex4_instr_trace_val_offset), + din => ex4_instr_trace_val_d, + dout => ex4_instr_trace_val_q); +unit_trace_sel_latch : tri_rlmreg_p +generic map (width => unit_trace_sel_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => trace_bus_enable_q, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(unit_trace_sel_offset to unit_trace_sel_offset + unit_trace_sel_q'length-1), + scout => sov(unit_trace_sel_offset to unit_trace_sel_offset + unit_trace_sel_q'length-1), + din => lsu_debug_mux_ctrls, + dout => unit_trace_sel_q); + +siv(0 to scan_right-1) <= sov(1 to scan_right-1) & dbg_scan_out; +scan_out <= sov(0); + +end architecture xuq_lsu_debug; diff --git a/rel/src/vhdl/work/xuq_lsu_derat.vhdl b/rel/src/vhdl/work/xuq_lsu_derat.vhdl new file mode 100644 index 0000000..1e2bda4 --- /dev/null +++ b/rel/src/vhdl/work/xuq_lsu_derat.vhdl @@ -0,0 +1,10868 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +--******************************************************************** +--* TITLE: Data Side Effective to Real Address Translation +--* NAME: xuq_lsu_derat.vhdl +--********************************************************************* + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library ibm; +use ibm.std_ulogic_unsigned.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_support.all; +library support; +use support.power_logic_pkg.all; +library tri; +use tri.tri_latches_pkg.all; + +entity xuq_lsu_derat is + generic(thdid_width : integer := 4; + ttype_width : integer := 12; + state_width : integer := 4; + lpid_width : integer := 8; + pid_width : integer := 14; + pid_width_erat : integer := 8; + extclass_width : integer := 2; + tlbsel_width : integer := 2; + epn_width : integer := 52; + vpn_width : integer := 61; + rpn_width : integer := 30; + ws_width : integer := 2; + rs_is_width : integer := 9; + ra_entry_width : integer := 5; + rs_data_width : integer := 64; + data_out_width : integer := 64; + error_width : integer := 3; + cam_data_width : natural := 84; + array_data_width : natural := 68; + num_entry : natural := 32; + num_entry_log2 : natural := 5; + por_seq_width : integer := 3; + watermark_width : integer := 5; + eptr_width : integer := 5; + lru_width : integer := 31; + bcfg_width : integer := 123; + ex2_epn_width : integer := 30; + bcfg_epn_0to15 : integer := 0; + bcfg_epn_16to31 : integer := 0; + bcfg_epn_32to47 : integer := (2**16)-1; + bcfg_epn_48to51 : integer := (2**4)-1; + bcfg_rpn_22to31 : integer := (2**10)-1; + bcfg_rpn_32to47 : integer := (2**16)-1; + bcfg_rpn_48to51 : integer := (2**4)-1; + bcfg_rpn2_32to47 : integer := 0; + bcfg_rpn2_48to51 : integer := 0; + bcfg_attr : integer := 0; + check_parity : integer := 1; + expand_type : integer := 2 ); +port( + gnd : inout power_logic; + vdd : inout power_logic; + vcs : inout power_logic; + nclk : in clk_logic; + pc_xu_init_reset : in std_ulogic; + +pc_xu_ccflush_dc : in std_ulogic; +tc_scan_dis_dc_b : in std_ulogic; +tc_scan_diag_dc : in std_ulogic; +tc_lbist_en_dc : in std_ulogic; +an_ac_atpg_en_dc : in std_ulogic; +an_ac_grffence_en_dc : in std_ulogic; +lcb_d_mode_dc : in std_ulogic; +lcb_clkoff_dc_b : in std_ulogic; +lcb_act_dis_dc : in std_ulogic; +lcb_mpw1_dc_b : in std_ulogic_vector(0 to 4); +lcb_mpw2_dc_b : in std_ulogic; +lcb_delay_lclkr_dc : in std_ulogic_vector(0 to 4); +pc_func_sl_thold_2 : in std_ulogic; +pc_func_slp_sl_thold_2 : in std_ulogic; +pc_func_slp_nsl_thold_2 : in std_ulogic; +pc_cfg_slp_sl_thold_2 : in std_ulogic; +pc_regf_slp_sl_thold_2 : in std_ulogic; +pc_time_sl_thold_2 : in std_ulogic; +pc_sg_2 : in std_ulogic; +pc_fce_2 : in std_ulogic; +cam_clkoff_dc_b : in std_ulogic; +cam_act_dis_dc : in std_ulogic; +cam_d_mode_dc : in std_ulogic; +cam_delay_lclkr_dc : in std_ulogic_vector(0 to 4); +cam_mpw1_dc_b : in std_ulogic_vector(0 to 4); +cam_mpw2_dc_b : in std_ulogic; +ac_func_scan_in : in std_ulogic_vector(0 to 1); +ac_func_scan_out : out std_ulogic_vector(0 to 1); +ac_ccfg_scan_in : in std_ulogic; +ac_ccfg_scan_out : out std_ulogic; +time_scan_in : in std_ulogic; +time_scan_out : out std_ulogic; +regf_scan_in : in std_ulogic_vector(0 to 6); +regf_scan_out : out std_ulogic_vector(0 to 6); +spr_xucr0_clkg_ctl_b1 : in std_ulogic; +spr_xucr4_mmu_mchk : in std_ulogic; +xu_derat_rf0_val : in std_ulogic_vector(0 to thdid_width-1); +xu_derat_rf0_is_extload : in std_ulogic; +xu_derat_rf0_is_extstore : in std_ulogic; +xu_derat_rf1_is_load : in std_ulogic; +xu_derat_rf1_is_store : in std_ulogic; +xu_derat_rf1_is_eratre : in std_ulogic; +xu_derat_rf1_is_eratwe : in std_ulogic; +xu_derat_rf1_is_eratsx : in std_ulogic; +xu_derat_rf1_is_eratilx : in std_ulogic; +xu_derat_ex1_is_isync : in std_ulogic; +xu_derat_ex1_is_csync : in std_ulogic; +xu_derat_rf1_is_touch : in std_ulogic; +xu_derat_rf1_icbtls_instr : in std_ulogic; +xu_derat_rf1_icblc_instr : in std_ulogic; +xu_derat_rf1_act : in std_ulogic; +xu_derat_rf1_ra_eq_ea : in std_ulogic; +xu_derat_rf1_ws : in std_ulogic_vector(0 to ws_width-1); +xu_derat_rf1_t : in std_ulogic_vector(0 to 2); +xu_derat_rf1_binv_val : in std_ulogic; +xu_derat_ex1_rs_is : in std_ulogic_vector(0 to rs_is_width-1); +xu_derat_ex1_ra_entry : in std_ulogic_vector(0 to ra_entry_width-1); +xu_derat_ex1_epn_arr : in std_ulogic_vector(64-rs_data_width to 51); +xu_derat_ex1_epn_nonarr : in std_ulogic_vector(64-rs_data_width to 51); +snoop_addr : out std_ulogic_vector(64-rs_data_width to 51); +snoop_addr_sel : out std_ulogic; +xu_derat_rf0_n_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_derat_rf1_n_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_derat_ex1_n_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_derat_ex2_n_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_derat_ex3_n_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_derat_ex4_n_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_derat_ex5_n_flush : in std_ulogic_vector(0 to thdid_width-1); +xu_derat_ex4_rs_data : in std_ulogic_vector(64-rs_data_width to 63); +xu_derat_msr_hv : in std_ulogic_vector(0 to thdid_width-1); +xu_derat_msr_pr : in std_ulogic_vector(0 to thdid_width-1); +xu_derat_msr_ds : in std_ulogic_vector(0 to thdid_width-1); +xu_derat_msr_cm : in std_ulogic_vector(0 to thdid_width-1); +xu_derat_hid_mmu_mode : in std_ulogic; +xu_derat_spr_ccr2_dfrat : in std_ulogic; +xu_derat_spr_ccr2_dfratsc : in std_ulogic_vector(0 to 8); +derat_xu_ex2_miss : out std_ulogic_vector(0 to thdid_width-1); +derat_xu_ex2_rpn : out std_ulogic_vector(22 to 51); +derat_xu_ex2_wimge : out std_ulogic_vector(0 to 4); +derat_xu_ex2_u : out std_ulogic_vector(0 to 3); +derat_xu_ex2_wlc : out std_ulogic_vector(0 to 1); +derat_xu_ex2_attr : out std_ulogic_vector(0 to 5); +derat_xu_ex2_vf : out std_ulogic; +derat_xu_ex3_rpn : out std_ulogic_vector(22 to 51); +derat_xu_ex3_wimge : out std_ulogic_vector(0 to 4); +derat_xu_ex3_u : out std_ulogic_vector(0 to 3); +derat_xu_ex3_wlc : out std_ulogic_vector(0 to 1); +derat_xu_ex3_attr : out std_ulogic_vector(0 to 5); +derat_xu_ex3_vf : out std_ulogic; +derat_xu_ex3_miss : out std_ulogic_vector(0 to thdid_width-1); +derat_xu_ex3_dsi : out std_ulogic_vector(0 to thdid_width-1); +derat_xu_ex3_par_err : out std_ulogic_vector(0 to thdid_width-1); +derat_xu_ex3_multihit_err : out std_ulogic_vector(0 to thdid_width-1); +derat_xu_ex3_noop_touch : out std_ulogic_vector(0 to thdid_width-1); +derat_xu_ex3_n_flush_req : out std_ulogic_vector(0 to thdid_width-1); +derat_xu_ex4_data : out std_ulogic_vector(64-data_out_width to 63); +derat_xu_ex4_par_err : out std_ulogic_vector(0 to thdid_width-1); +derat_iu_barrier_done : out std_ulogic_vector(0 to thdid_width-1); +derat_fir_par_err : out std_ulogic_vector(0 to thdid_width-1); +derat_fir_multihit : out std_ulogic_vector(0 to thdid_width-1); +xu_derat_epsc_wr : in std_ulogic_vector(0 to 3); +xu_derat_eplc_wr : in std_ulogic_vector(0 to 3); +xu_derat_eplc0_epr : in std_ulogic; +xu_derat_eplc0_eas : in std_ulogic; +xu_derat_eplc0_egs : in std_ulogic; +xu_derat_eplc0_elpid : in std_ulogic_vector(40 to 47); +xu_derat_eplc0_epid : in std_ulogic_vector(50 to 63); +xu_derat_eplc1_epr : in std_ulogic; +xu_derat_eplc1_eas : in std_ulogic; +xu_derat_eplc1_egs : in std_ulogic; +xu_derat_eplc1_elpid : in std_ulogic_vector(40 to 47); +xu_derat_eplc1_epid : in std_ulogic_vector(50 to 63); +xu_derat_eplc2_epr : in std_ulogic; +xu_derat_eplc2_eas : in std_ulogic; +xu_derat_eplc2_egs : in std_ulogic; +xu_derat_eplc2_elpid : in std_ulogic_vector(40 to 47); +xu_derat_eplc2_epid : in std_ulogic_vector(50 to 63); +xu_derat_eplc3_epr : in std_ulogic; +xu_derat_eplc3_eas : in std_ulogic; +xu_derat_eplc3_egs : in std_ulogic; +xu_derat_eplc3_elpid : in std_ulogic_vector(40 to 47); +xu_derat_eplc3_epid : in std_ulogic_vector(50 to 63); +xu_derat_epsc0_epr : in std_ulogic; +xu_derat_epsc0_eas : in std_ulogic; +xu_derat_epsc0_egs : in std_ulogic; +xu_derat_epsc0_elpid : in std_ulogic_vector(40 to 47); +xu_derat_epsc0_epid : in std_ulogic_vector(50 to 63); +xu_derat_epsc1_epr : in std_ulogic; +xu_derat_epsc1_eas : in std_ulogic; +xu_derat_epsc1_egs : in std_ulogic; +xu_derat_epsc1_elpid : in std_ulogic_vector(40 to 47); +xu_derat_epsc1_epid : in std_ulogic_vector(50 to 63); +xu_derat_epsc2_epr : in std_ulogic; +xu_derat_epsc2_eas : in std_ulogic; +xu_derat_epsc2_egs : in std_ulogic; +xu_derat_epsc2_elpid : in std_ulogic_vector(40 to 47); +xu_derat_epsc2_epid : in std_ulogic_vector(50 to 63); +xu_derat_epsc3_epr : in std_ulogic; +xu_derat_epsc3_eas : in std_ulogic; +xu_derat_epsc3_egs : in std_ulogic; +xu_derat_epsc3_elpid : in std_ulogic_vector(40 to 47); +xu_derat_epsc3_epid : in std_ulogic_vector(50 to 63); +xu_mm_derat_req : out std_ulogic; +xu_mm_derat_thdid : out std_ulogic_vector(0 to thdid_width-1); +xu_mm_derat_ttype : out std_ulogic_vector(0 to 1); +xu_mm_derat_state : out std_ulogic_vector(0 to state_width-1); +xu_mm_derat_lpid : out std_ulogic_vector(0 to lpid_width-1); +xu_mm_derat_tid : out std_ulogic_vector(0 to pid_width-1); +mm_xu_derat_rel_val : in std_ulogic_vector(0 to 4); +mm_xu_derat_rel_data : in std_ulogic_vector(0 to 131); +mm_xu_derat_pid0 : in std_ulogic_vector(0 to pid_width-1); +mm_xu_derat_pid1 : in std_ulogic_vector(0 to pid_width-1); +mm_xu_derat_pid2 : in std_ulogic_vector(0 to pid_width-1); +mm_xu_derat_pid3 : in std_ulogic_vector(0 to pid_width-1); +mm_xu_derat_mmucr0_0 : in std_ulogic_vector(0 to 19); +mm_xu_derat_mmucr0_1 : in std_ulogic_vector(0 to 19); +mm_xu_derat_mmucr0_2 : in std_ulogic_vector(0 to 19); +mm_xu_derat_mmucr0_3 : in std_ulogic_vector(0 to 19); +xu_mm_derat_mmucr0 : out std_ulogic_vector(0 to 17); +xu_mm_derat_mmucr0_we : out std_ulogic_vector(0 to 3); +mm_xu_derat_mmucr1 : in std_ulogic_vector(0 to 9); +xu_mm_derat_mmucr1 : out std_ulogic_vector(0 to 4); +xu_mm_derat_mmucr1_we : out std_ulogic; +mm_xu_derat_snoop_coming : in std_ulogic; +mm_xu_derat_snoop_val : in std_ulogic; +mm_xu_derat_snoop_attr : in std_ulogic_vector(0 to 25); +mm_xu_derat_snoop_vpn : in std_ulogic_vector(52-epn_width to 51); +xu_mm_derat_snoop_ack : out std_ulogic; +pc_xu_trace_bus_enable : in std_ulogic; +derat_xu_debug_group0 : out std_ulogic_vector(0 to 87); +derat_xu_debug_group1 : out std_ulogic_vector(0 to 87); +derat_xu_debug_group2 : out std_ulogic_vector(0 to 87); +derat_xu_debug_group3 : out std_ulogic_vector(0 to 87) +); +end xuq_lsu_derat; +ARCHITECTURE XUQ_LSU_DERAT + OF XUQ_LSU_DERAT + IS +--@@ Signal Declarations +SIGNAL CAM_MASK_BITS_PT : STD_ULOGIC_VECTOR(1 TO 19) := +(OTHERS=> 'U'); +SIGNAL EX2_FIRST_HIT_ENTRY_PT : STD_ULOGIC_VECTOR(1 TO 31) := +(OTHERS=> 'U'); +SIGNAL EX2_MULTIHIT_B_PT : STD_ULOGIC_VECTOR(1 TO 32) := +(OTHERS=> 'U'); +SIGNAL LRU_RMT_VEC_D_PT : STD_ULOGIC_VECTOR(1 TO 32) := +(OTHERS=> 'U'); +SIGNAL LRU_SET_RESET_VEC_PT : STD_ULOGIC_VECTOR(1 TO 161) := +(OTHERS=> 'U'); +SIGNAL LRU_WAY_ENCODE_PT : STD_ULOGIC_VECTOR(1 TO 31) := +(OTHERS=> 'U'); +---------------------------- +-- components +---------------------------- +-- Data ERAT CAM/Array, 32-entry +component tri_cam_32x143_1r1w1c + generic (expand_type : integer := 2); + port ( + gnd : inout power_logic; + vdd : inout power_logic; + vcs : inout power_logic; + nclk : in clk_logic; + tc_ccflush_dc : in std_ulogic; + tc_scan_dis_dc_b : in std_ulogic; + tc_scan_diag_dc : in std_ulogic; + tc_lbist_en_dc : in std_ulogic; + an_ac_atpg_en_dc : in std_ulogic; + + lcb_d_mode_dc : in std_ulogic; + lcb_clkoff_dc_b : in std_ulogic; + lcb_act_dis_dc : in std_ulogic; + lcb_mpw1_dc_b : in std_ulogic_vector(0 to 3); + lcb_mpw2_dc_b : in std_ulogic; + lcb_delay_lclkr_dc : in std_ulogic_vector(0 to 3); + + pc_sg_2 : in std_ulogic; + pc_func_slp_sl_thold_2 : in std_ulogic; + pc_func_slp_nsl_thold_2 : in std_ulogic; + pc_regf_slp_sl_thold_2 : in std_ulogic; + pc_time_sl_thold_2 : in std_ulogic; + pc_fce_2 : in std_ulogic; + + func_scan_in : in std_ulogic; + func_scan_out : out std_ulogic; + regfile_scan_in : in std_ulogic_vector(0 to 6); + regfile_scan_out : out std_ulogic_vector(0 to 6); + time_scan_in : in std_ulogic; + time_scan_out : out std_ulogic; + + rd_val : in std_ulogic; + rd_val_late : in std_ulogic; + rw_entry : in std_ulogic_vector(0 to 4); + + wr_array_data : in std_ulogic_vector(0 to array_data_width-1); + wr_cam_data : in std_ulogic_vector(0 to cam_data_width-1); + wr_array_val : in std_ulogic_vector(0 to 1); + wr_cam_val : in std_ulogic_vector(0 to 1); + wr_val_early : in std_ulogic; + + comp_request : in std_ulogic; + comp_addr : in std_ulogic_vector(0 to 51); + addr_enable : in std_ulogic_vector(0 to 1); + comp_pgsize : in std_ulogic_vector(0 to 2); + pgsize_enable : in std_ulogic; + comp_class : in std_ulogic_vector(0 to 1); + class_enable : in std_ulogic_vector(0 to 2); + comp_extclass : in std_ulogic_vector(0 to 1); + extclass_enable : in std_ulogic_vector(0 to 1); + comp_state : in std_ulogic_vector(0 to 1); + state_enable : in std_ulogic_vector(0 to 1); + comp_thdid : in std_ulogic_vector(0 to 3); + thdid_enable : in std_ulogic_vector(0 to 1); + comp_pid : in std_ulogic_vector(0 to 7); + pid_enable : in std_ulogic; + comp_invalidate : in std_ulogic; + flash_invalidate : in std_ulogic; + + array_cmp_data : out std_ulogic_vector(0 to array_data_width-1); + rd_array_data : out std_ulogic_vector(0 to array_data_width-1); + + cam_cmp_data : out std_ulogic_vector(0 to cam_data_width-1); + cam_hit : out std_ulogic; + cam_hit_entry : out std_ulogic_vector(0 to 4); + entry_match : out std_ulogic_vector(0 to 31); + entry_valid : out std_ulogic_vector(0 to 31); + rd_cam_data : out std_ulogic_vector(0 to cam_data_width-1); + +----- new ports for IO plus ----------------------- + bypass_mux_enab_np1 : in std_ulogic; + bypass_attr_np1 : in std_ulogic_vector(0 to 20); + attr_np2 : out std_ulogic_vector(0 to 20); + rpn_np2 : out std_ulogic_vector(22 to 51) + + ); +END component; +component tri_cam_parerr_mac + generic (expand_type : integer := 2); + port ( + gnd :inout power_logic; + vdd :inout power_logic; + nclk :in std_ulogic; + lcb_act_dis_dc :in std_ulogic; + lcb_delay_lclkr_dc :in std_ulogic; + lcb_clkoff_dc_b_0 :in std_ulogic; + lcb_mpw1_dc_b :in std_ulogic; + lcb_mpw2_dc_b :in std_ulogic; + act :in std_ulogic; + lcb_sg_0 :in std_ulogic; + lcb_func_sl_thold_0 :in std_ulogic; + + func_scan_in :in std_ulogic; + func_scan_out :out std_ulogic; + + np1_cam_cmp_data :in std_ulogic_vector(0 to 83); + np1_array_cmp_data :in std_ulogic_vector(0 to 67); + + np2_cam_cmp_data :out std_ulogic_vector(0 to 83); + np2_array_cmp_data :out std_ulogic_vector(0 to 67); + np2_cmp_data_parerr_epn :out std_ulogic; + np2_cmp_data_parerr_rpn :out std_ulogic + ); +END component; +---------------------------- +-- constants +---------------------------- +constant MMU_Mode_Value : std_ulogic := '0'; +constant TlbSel_Tlb : std_ulogic_vector(0 to 1) := "00"; +constant TlbSel_IErat : std_ulogic_vector(0 to 1) := "10"; +constant TlbSel_DErat : std_ulogic_vector(0 to 1) := "11"; +constant CAM_PgSize_1GB : std_ulogic_vector(0 to 2) := "110"; +constant CAM_PgSize_16MB : std_ulogic_vector(0 to 2) := "111"; +constant CAM_PgSize_1MB : std_ulogic_vector(0 to 2) := "101"; +constant CAM_PgSize_64KB : std_ulogic_vector(0 to 2) := "011"; +constant CAM_PgSize_4KB : std_ulogic_vector(0 to 2) := "001"; +constant WS0_PgSize_1GB : std_ulogic_vector(0 to 3) := "1010"; +constant WS0_PgSize_16MB : std_ulogic_vector(0 to 3) := "0111"; +constant WS0_PgSize_1MB : std_ulogic_vector(0 to 3) := "0101"; +constant WS0_PgSize_64KB : std_ulogic_vector(0 to 3) := "0011"; +constant WS0_PgSize_4KB : std_ulogic_vector(0 to 3) := "0001"; +constant eratpos_epn : natural := 0; +constant eratpos_x : natural := 52; +constant eratpos_size : natural := 53; +constant eratpos_v : natural := 56; +constant eratpos_thdid : natural := 57; +constant eratpos_class : natural := 61; +constant eratpos_extclass : natural := 63; +constant eratpos_wren : natural := 65; +constant eratpos_rpnrsvd : natural := 66; +constant eratpos_rpn : natural := 70; +constant eratpos_r : natural := 100; +constant eratpos_c : natural := 101; +constant eratpos_relsoon : natural := 102; +constant eratpos_wlc : natural := 103; +constant eratpos_resvattr : natural := 105; +constant eratpos_vf : natural := 106; +constant eratpos_ubits : natural := 107; +constant eratpos_wimge : natural := 111; +constant eratpos_usxwr : natural := 116; +constant eratpos_gs : natural := 122; +constant eratpos_ts : natural := 123; +constant eratpos_tid : natural := 124; +constant PorSeq_Idle : std_ulogic_vector(0 to 2) := "000"; +constant PorSeq_Stg1 : std_ulogic_vector(0 to 2) := "001"; +constant PorSeq_Stg2 : std_ulogic_vector(0 to 2) := "011"; +constant PorSeq_Stg3 : std_ulogic_vector(0 to 2) := "010"; +constant PorSeq_Stg4 : std_ulogic_vector(0 to 2) := "110"; +constant PorSeq_Stg5 : std_ulogic_vector(0 to 2) := "100"; +constant PorSeq_Stg6 : std_ulogic_vector(0 to 2) := "101"; +constant PorSeq_Stg7 : std_ulogic_vector(0 to 2) := "111"; +constant Por_Wr_Entry_Num1 : std_ulogic_vector(0 to num_entry_log2-1) := "11110"; +constant Por_Wr_Entry_Num2 : std_ulogic_vector(0 to num_entry_log2-1) := "11111"; +-- wr_cam_data +-- 0:51 - EPN +-- 52 - X +-- 53:55 - SIZE +-- 56 - V +-- 57:60 - ThdID +-- 61:62 - Class +-- 63:64 - ExtClass | TID_NZ +-- 65 - TGS +-- 66 - TS +-- 67:74 - TID +-- 75:78 - epn_cmpmasks: 34_39, 40_43, 44_47, 48_51 +-- 79:82 - xbit_cmpmasks: 34_51, 40_51, 44_51, 48_51 +-- 83 - parity for 75:82 +constant Por_Wr_Cam_Data1 : std_ulogic_vector(0 to 83) := "0000000000000000000000000000000011111111111111111111" & + '0' & "001" & '1' & "1111" & "00" & "00" & "00" & "00000000" & "11110000" & '0'; +constant Por_Wr_Cam_Data2 : std_ulogic_vector(0 to 83) := "0000000000000000000000000000000000000000000000000000" & + '0' & "001" & '1' & "1111" & "00" & "10" & "00" & "00000000" & "11110000" & '0'; +-- 16x143 version, 42b RA +-- wr_array_data +-- 0:29 - RPN +-- 30:31 - R,C +-- 32:35 - ResvAttr +-- 36:39 - U0-U3 +-- 40:44 - WIMGE +-- 45:46 - UX,SX +-- 47:48 - UW,SW +-- 49:50 - UR,SR +-- 51:60 - CAM parity +-- 61:67 - Array parity +constant Por_Wr_Array_Data1 : std_ulogic_vector(0 to 67) := "111111111111111111111111111111" & + "00" & "0000" & "0000" & "01010" & "01" & "00" & "01" & "0000001000" & "0000000"; +constant Por_Wr_Array_Data2 : std_ulogic_vector(0 to 67) := "000000000000000000000000000000" & + "00" & "0000" & "0000" & "01010" & "01" & "00" & "01" & "0000001010" & "0000000"; +constant rf1_valid_offset : natural := 0; +constant rf1_ttype_offset : natural := rf1_valid_offset + thdid_width; +constant ex1_valid_offset : natural := rf1_ttype_offset + 2; +constant ex1_ttype_offset : natural := ex1_valid_offset + thdid_width; +constant ex1_ws_offset : natural := ex1_ttype_offset + ttype_width; +constant ex1_rs_is_offset : natural := ex1_ws_offset + ws_width; +constant ex1_ra_entry_offset : natural := ex1_rs_is_offset + rs_is_width; +constant ex1_state_offset : natural := ex1_ra_entry_offset + ra_entry_width; +constant ex1_pid_offset : natural := ex1_state_offset + state_width; +constant ex1_extclass_offset : natural := ex1_pid_offset + pid_width; +constant ex1_tlbsel_offset : natural := ex1_extclass_offset + extclass_width; +constant ex2_valid_offset : natural := ex1_tlbsel_offset + tlbsel_width; +constant ex2_ttype_offset : natural := ex2_valid_offset + thdid_width; +constant ex2_ws_offset : natural := ex2_ttype_offset + ttype_width; +constant ex2_rs_is_offset : natural := ex2_ws_offset + ws_width; +constant ex2_ra_entry_offset : natural := ex2_rs_is_offset + rs_is_width; +constant ex2_state_offset : natural := ex2_ra_entry_offset + ra_entry_width; +constant ex2_pid_offset : natural := ex2_state_offset + state_width; +constant ex2_extclass_offset : natural := ex2_pid_offset + pid_width; +constant ex2_tlbsel_offset : natural := ex2_extclass_offset + extclass_width; +constant ex3_valid_offset : natural := ex2_tlbsel_offset + tlbsel_width; +constant ex3_ttype_offset : natural := ex3_valid_offset + thdid_width; +constant ex3_ws_offset : natural := ex3_ttype_offset + ttype_width; +constant ex3_rs_is_offset : natural := ex3_ws_offset + ws_width; +constant ex3_ra_entry_offset : natural := ex3_rs_is_offset + rs_is_width; +constant ex3_state_offset : natural := ex3_ra_entry_offset + ra_entry_width; +constant ex3_pid_offset : natural := ex3_state_offset + state_width; +constant ex3_lpid_offset : natural := ex3_pid_offset + pid_width; +constant ex3_extclass_offset : natural := ex3_lpid_offset + lpid_width; +constant ex3_tlbsel_offset : natural := ex3_extclass_offset + extclass_width; +constant ex4_valid_offset : natural := ex3_tlbsel_offset + tlbsel_width; +constant ex4_ttype_offset : natural := ex4_valid_offset + thdid_width; +constant ex4_ws_offset : natural := ex4_ttype_offset + ttype_width; +constant ex4_rs_is_offset : natural := ex4_ws_offset + ws_width; +constant ex4_ra_entry_offset : natural := ex4_rs_is_offset + rs_is_width; +constant ex4_state_offset : natural := ex4_ra_entry_offset + ra_entry_width; +constant ex4_pid_offset : natural := ex4_state_offset + state_width; +constant ex4_extclass_offset : natural := ex4_pid_offset + pid_width; +constant ex4_tlbsel_offset : natural := ex4_extclass_offset + extclass_width; +constant ex5_valid_offset : natural := ex4_tlbsel_offset + tlbsel_width; +constant ex5_ttype_offset : natural := ex5_valid_offset + thdid_width; +constant ex5_ws_offset : natural := ex5_ttype_offset + ttype_width; +constant ex5_rs_is_offset : natural := ex5_ws_offset + ws_width; +constant ex5_ra_entry_offset : natural := ex5_rs_is_offset + rs_is_width; +constant ex5_state_offset : natural := ex5_ra_entry_offset + ra_entry_width; +constant ex5_pid_offset : natural := ex5_state_offset + state_width; +constant ex5_extclass_offset : natural := ex5_pid_offset + pid_width; +constant ex5_tlbsel_offset : natural := ex5_extclass_offset + extclass_width; +constant ex5_data_in_offset : natural := ex5_tlbsel_offset + tlbsel_width; +constant ex6_valid_offset : natural := ex5_data_in_offset + rs_data_width; +constant ex6_ttype_offset : natural := ex6_valid_offset + thdid_width; +constant ex6_ws_offset : natural := ex6_ttype_offset + ttype_width; +constant ex6_rs_is_offset : natural := ex6_ws_offset + ws_width; +constant ex6_ra_entry_offset : natural := ex6_rs_is_offset + rs_is_width; +constant ex6_state_offset : natural := ex6_ra_entry_offset + ra_entry_width; +constant ex6_pid_offset : natural := ex6_state_offset + state_width; +constant ex6_extclass_offset : natural := ex6_pid_offset + pid_width; +constant ex6_tlbsel_offset : natural := ex6_extclass_offset + extclass_width; +constant ex6_data_in_offset : natural := ex6_tlbsel_offset + tlbsel_width; +constant ex7_valid_offset : natural := ex6_data_in_offset + rs_data_width; +constant ex7_ttype_offset : natural := ex7_valid_offset + thdid_width; +constant ex7_tlbsel_offset : natural := ex7_ttype_offset + ttype_width; +constant ex4_data_out_offset : natural := ex7_tlbsel_offset + tlbsel_width; +constant ex2_n_flush_req_offset : natural := ex4_data_out_offset + data_out_width; +constant ex3_n_flush_req_offset : natural := ex2_n_flush_req_offset + thdid_width; +constant hold_req_reset_offset : natural := ex3_n_flush_req_offset + thdid_width; +constant hold_req_pot_set_offset : natural := hold_req_reset_offset + thdid_width; +constant hold_req_por_offset : natural := hold_req_pot_set_offset + thdid_width; +constant hold_req_offset : natural := hold_req_por_offset + thdid_width; +constant tlb_req_inprogress_offset : natural := hold_req_offset + thdid_width; +constant ex2_dsi_offset : natural := tlb_req_inprogress_offset + thdid_width; +constant ex2_noop_touch_offset : natural := ex2_dsi_offset + 16; +constant ex3_miss_offset : natural := ex2_noop_touch_offset + 16; +constant ex3_dsi_offset : natural := ex3_miss_offset + thdid_width; +constant ex3_noop_touch_offset : natural := ex3_dsi_offset + 16; +constant ex3_multihit_offset : natural := ex3_noop_touch_offset + 16; +constant ex3_multihit_b_pt_offset : natural := ex3_multihit_offset + thdid_width; +constant ex3_first_hit_entry_pt_offset : natural := ex3_multihit_b_pt_offset + num_entry; +constant ex3_parerr_offset : natural := ex3_first_hit_entry_pt_offset + num_entry-1; +constant ex3_attr_offset : natural := ex3_parerr_offset + thdid_width + 2; +constant ex3_tlbreq_offset : natural := ex3_attr_offset + 6; +constant ex3_hit_offset : natural := ex3_tlbreq_offset + 1; +constant ex3_cam_hit_offset : natural := ex3_hit_offset + 1; +constant ex2_debug_offset : natural := ex3_cam_hit_offset + 1; +constant ex3_debug_offset : natural := ex2_debug_offset + 11; +constant spare_a_offset : natural := ex3_debug_offset + 17; +constant scan_right_0 : natural := spare_a_offset + 16 -1; +constant erat_parerr_mac_offset : natural := 0; +constant ex4_rd_cam_data_offset : natural := erat_parerr_mac_offset + 1; +constant ex4_rd_array_data_offset : natural := ex4_rd_cam_data_offset + cam_data_width; +constant ex4_parerr_offset : natural := ex4_rd_array_data_offset + array_data_width; +constant ex4_fir_parerr_offset : natural := ex4_parerr_offset + thdid_width + 2; +constant ex4_fir_multihit_offset : natural := ex4_fir_parerr_offset + thdid_width + 3; +constant ex4_deen_offset : natural := ex4_fir_multihit_offset + thdid_width; +constant ex4_hit_offset : natural := ex4_deen_offset + num_entry_log2 + thdid_width; +constant ex5_deen_offset : natural := ex4_hit_offset + 1; +constant ex5_hit_offset : natural := ex5_deen_offset + num_entry_log2 + thdid_width; +constant ex6_deen_offset : natural := ex5_hit_offset + 1; +constant ex6_hit_offset : natural := ex6_deen_offset + num_entry_log2 + 1; +constant barrier_done_offset : natural := ex6_hit_offset + 1; +constant mmucr1_offset : natural := barrier_done_offset + thdid_width; +constant rpn_holdreg0_offset : natural := mmucr1_offset + 10; +constant rpn_holdreg1_offset : natural := rpn_holdreg0_offset + 64; +constant rpn_holdreg2_offset : natural := rpn_holdreg1_offset + 64; +constant rpn_holdreg3_offset : natural := rpn_holdreg2_offset + 64; +constant entry_valid_offset : natural := rpn_holdreg3_offset + 64; +constant entry_match_offset : natural := entry_valid_offset + 32; +constant watermark_offset : natural := entry_match_offset + 32; +constant mmucr1_b0_cpy_offset : natural := watermark_offset + watermark_width; +constant lru_rmt_vec_offset : natural := mmucr1_b0_cpy_offset + 1; +constant eptr_offset : natural := lru_rmt_vec_offset + lru_width+1; +constant lru_offset : natural := eptr_offset + eptr_width; +constant lru_update_event_offset : natural := lru_offset + lru_width; +constant lru_debug_offset : natural := lru_update_event_offset + 10; +constant snoop_val_offset : natural := lru_debug_offset + 41; +constant snoop_attr_offset : natural := snoop_val_offset + 3; +constant snoop_addr_offset : natural := snoop_attr_offset + 26; +constant ex2_epn_offset : natural := snoop_addr_offset + epn_width; +constant por_seq_offset : natural := ex2_epn_offset + ex2_epn_width; +constant pc_xu_init_reset_offset : natural := por_seq_offset + 3; +constant tlb_rel_val_offset : natural := pc_xu_init_reset_offset + 1; +constant tlb_rel_data_offset : natural := tlb_rel_val_offset + thdid_width + 1; +constant eplc_wr_offset : natural := tlb_rel_data_offset + 132; +constant epsc_wr_offset : natural := eplc_wr_offset + 2*thdid_width + 1; +constant ccr2_frat_paranoia_offset : natural := epsc_wr_offset + 2*thdid_width + 1; +constant ccr2_notlb_offset : natural := ccr2_frat_paranoia_offset + 12; +constant xucr4_mmu_mchk_offset : natural := ccr2_notlb_offset + 1; +constant mchk_flash_inv_offset : natural := xucr4_mmu_mchk_offset + 1; +constant clkg_ctl_override_offset : natural := mchk_flash_inv_offset + 4; +constant rf1_stg_act_offset : natural := clkg_ctl_override_offset + 1; +constant ex1_stg_act_offset : natural := rf1_stg_act_offset + 1; +constant ex2_stg_act_offset : natural := ex1_stg_act_offset + 1; +constant ex3_stg_act_offset : natural := ex2_stg_act_offset + 1; +constant ex4_stg_act_offset : natural := ex3_stg_act_offset + 1; +constant ex5_stg_act_offset : natural := ex4_stg_act_offset + 1; +constant ex6_stg_act_offset : natural := ex5_stg_act_offset + 1; +constant ex7_stg_act_offset : natural := ex6_stg_act_offset + 1; +constant tlb_rel_act_offset : natural := ex7_stg_act_offset + 1; +constant snoop_act_offset : natural := tlb_rel_act_offset + 1; +constant trace_bus_enable_offset : natural := snoop_act_offset + 1; +constant an_ac_grffence_en_dc_offset : natural := trace_bus_enable_offset + 1; +constant spare_b_offset : natural := an_ac_grffence_en_dc_offset + 1; +constant scan_right_1 : natural := spare_b_offset + 16 -1; +constant bcfg_offset : natural := 0; +constant boot_scan_right : natural := bcfg_offset + bcfg_width - 1; +---------------------------- +-- signals +---------------------------- +-- Latch signals +signal rf1_valid_d, rf1_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal rf1_ttype_d, rf1_ttype_q : std_ulogic_vector(10 to 11); +signal ex1_valid_d : std_ulogic_vector(0 to thdid_width-1); +signal ex1_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal ex1_ttype_d : std_ulogic_vector(0 to ttype_width-1); +signal ex1_ttype_q : std_ulogic_vector(0 to ttype_width-1); +signal ex1_ws_d : std_ulogic_vector(0 to ws_width-1); +signal ex1_ws_q : std_ulogic_vector(0 to ws_width-1); +signal ex1_rs_is_d : std_ulogic_vector(0 to rs_is_width-1); +signal ex1_rs_is_q : std_ulogic_vector(0 to rs_is_width-1); +signal ex1_ra_entry_d : std_ulogic_vector(0 to ra_entry_width-1); +signal ex1_ra_entry_q : std_ulogic_vector(0 to ra_entry_width-1); +signal ex1_state_d : std_ulogic_vector(0 to state_width-1); +signal ex1_state_q : std_ulogic_vector(0 to state_width-1); +signal ex1_pid_d : std_ulogic_vector(0 to pid_width-1); +signal ex1_pid_q : std_ulogic_vector(0 to pid_width-1); +signal ex1_extclass_d : std_ulogic_vector(0 to extclass_width-1); +signal ex1_extclass_q : std_ulogic_vector(0 to extclass_width-1); +signal ex1_tlbsel_d : std_ulogic_vector(0 to tlbsel_width-1); +signal ex1_tlbsel_q : std_ulogic_vector(0 to tlbsel_width-1); +signal ex2_valid_d : std_ulogic_vector(0 to thdid_width-1); +signal ex2_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal ex2_ttype_d : std_ulogic_vector(0 to ttype_width-1); +signal ex2_ttype_q : std_ulogic_vector(0 to ttype_width-1); +signal ex2_ws_d : std_ulogic_vector(0 to ws_width-1); +signal ex2_ws_q : std_ulogic_vector(0 to ws_width-1); +signal ex2_rs_is_d : std_ulogic_vector(0 to rs_is_width-1); +signal ex2_rs_is_q : std_ulogic_vector(0 to rs_is_width-1); +signal ex2_ra_entry_d : std_ulogic_vector(0 to ra_entry_width-1); +signal ex2_ra_entry_q : std_ulogic_vector(0 to ra_entry_width-1); +signal ex2_state_d : std_ulogic_vector(0 to state_width-1); +signal ex2_state_q : std_ulogic_vector(0 to state_width-1); +signal ex2_pid_d : std_ulogic_vector(0 to pid_width-1); +signal ex2_pid_q : std_ulogic_vector(0 to pid_width-1); +signal ex2_extclass_d : std_ulogic_vector(0 to extclass_width-1); +signal ex2_extclass_q : std_ulogic_vector(0 to extclass_width-1); +signal ex2_tlbsel_d : std_ulogic_vector(0 to tlbsel_width-1); +signal ex2_tlbsel_q : std_ulogic_vector(0 to tlbsel_width-1); +signal ex3_valid_d : std_ulogic_vector(0 to thdid_width-1); +signal ex3_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal ex3_ttype_d : std_ulogic_vector(0 to ttype_width-1); +signal ex3_ttype_q : std_ulogic_vector(0 to ttype_width-1); +signal ex3_ws_d : std_ulogic_vector(0 to ws_width-1); +signal ex3_ws_q : std_ulogic_vector(0 to ws_width-1); +signal ex3_rs_is_d : std_ulogic_vector(0 to rs_is_width-1); +signal ex3_rs_is_q : std_ulogic_vector(0 to rs_is_width-1); +signal ex3_ra_entry_d : std_ulogic_vector(0 to ra_entry_width-1); +signal ex3_ra_entry_q : std_ulogic_vector(0 to ra_entry_width-1); +signal ex3_state_d : std_ulogic_vector(0 to state_width-1); +signal ex3_state_q : std_ulogic_vector(0 to state_width-1); +signal ex3_pid_d : std_ulogic_vector(0 to pid_width-1); +signal ex3_pid_q : std_ulogic_vector(0 to pid_width-1); +signal ex3_lpid_d : std_ulogic_vector(0 to lpid_width-1); +signal ex3_lpid_q : std_ulogic_vector(0 to lpid_width-1); +signal ex3_extclass_d : std_ulogic_vector(0 to extclass_width-1); +signal ex3_extclass_q : std_ulogic_vector(0 to extclass_width-1); +signal ex3_tlbsel_d : std_ulogic_vector(0 to tlbsel_width-1); +signal ex3_tlbsel_q : std_ulogic_vector(0 to tlbsel_width-1); +signal ex4_valid_d : std_ulogic_vector(0 to thdid_width-1); +signal ex4_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal ex4_ttype_d : std_ulogic_vector(0 to ttype_width-1); +signal ex4_ttype_q : std_ulogic_vector(0 to ttype_width-1); +signal ex4_ws_d : std_ulogic_vector(0 to ws_width-1); +signal ex4_ws_q : std_ulogic_vector(0 to ws_width-1); +signal ex4_rs_is_d : std_ulogic_vector(0 to rs_is_width-1); +signal ex4_rs_is_q : std_ulogic_vector(0 to rs_is_width-1); +signal ex4_ra_entry_d : std_ulogic_vector(0 to ra_entry_width-1); +signal ex4_ra_entry_q : std_ulogic_vector(0 to ra_entry_width-1); +signal ex4_state_d : std_ulogic_vector(0 to state_width-1); +signal ex4_state_q : std_ulogic_vector(0 to state_width-1); +signal ex4_pid_d : std_ulogic_vector(0 to pid_width-1); +signal ex4_pid_q : std_ulogic_vector(0 to pid_width-1); +signal ex4_extclass_d : std_ulogic_vector(0 to extclass_width-1); +signal ex4_extclass_q : std_ulogic_vector(0 to extclass_width-1); +signal ex4_tlbsel_d : std_ulogic_vector(0 to tlbsel_width-1); +signal ex4_tlbsel_q : std_ulogic_vector(0 to tlbsel_width-1); +signal ex5_valid_d, ex5_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal ex5_ttype_d, ex5_ttype_q : std_ulogic_vector(0 to ttype_width-1); +signal ex5_ws_d, ex5_ws_q : std_ulogic_vector(0 to ws_width-1); +signal ex5_rs_is_d, ex5_rs_is_q : std_ulogic_vector(0 to rs_is_width-1); +signal ex5_ra_entry_d, ex5_ra_entry_q : std_ulogic_vector(0 to ra_entry_width-1); +signal ex5_state_d, ex5_state_q : std_ulogic_vector(0 to state_width-1); +signal ex5_pid_d, ex5_pid_q : std_ulogic_vector(0 to pid_width-1); +signal ex5_extclass_d, ex5_extclass_q : std_ulogic_vector(0 to extclass_width-1); +signal ex5_tlbsel_d, ex5_tlbsel_q : std_ulogic_vector(0 to tlbsel_width-1); +signal ex6_valid_d, ex6_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal ex6_ttype_d, ex6_ttype_q : std_ulogic_vector(0 to ttype_width-1); +signal ex6_ws_d, ex6_ws_q : std_ulogic_vector(0 to ws_width-1); +signal ex6_rs_is_d, ex6_rs_is_q : std_ulogic_vector(0 to rs_is_width-1); +signal ex6_ra_entry_d, ex6_ra_entry_q : std_ulogic_vector(0 to ra_entry_width-1); +signal ex6_state_d, ex6_state_q : std_ulogic_vector(0 to state_width-1); +signal ex6_pid_d, ex6_pid_q : std_ulogic_vector(0 to pid_width-1); +signal ex6_extclass_d, ex6_extclass_q : std_ulogic_vector(0 to extclass_width-1); +signal ex6_tlbsel_d, ex6_tlbsel_q : std_ulogic_vector(0 to tlbsel_width-1); +signal ex7_valid_d, ex7_valid_q : std_ulogic_vector(0 to thdid_width-1); +signal ex7_ttype_d, ex7_ttype_q : std_ulogic_vector(0 to ttype_width-1); +signal ex7_tlbsel_d, ex7_tlbsel_q : std_ulogic_vector(0 to tlbsel_width-1); +signal ex5_data_in_d, ex5_data_in_q : std_ulogic_vector(64-rs_data_width to 63); +signal ex6_data_in_d, ex6_data_in_q : std_ulogic_vector(64-rs_data_width to 63); +signal ex4_data_out_d, ex4_data_out_q : std_ulogic_vector(64-data_out_width to 63); +signal ex2_n_flush_req_d, ex2_n_flush_req_q : std_ulogic_vector(0 to thdid_width-1); +signal ex3_n_flush_req_d, ex3_n_flush_req_q : std_ulogic_vector(0 to thdid_width-1); +signal hold_req_d, hold_req_q : std_ulogic_vector(0 to thdid_width-1); +signal hold_req_reset_d, hold_req_reset_q : std_ulogic_vector(0 to thdid_width-1); +signal hold_req_pot_set_d, hold_req_pot_set_q : std_ulogic_vector(0 to thdid_width-1); +signal hold_req_por_d, hold_req_por_q : std_ulogic_vector(0 to thdid_width-1); +signal tlb_req_inprogress_d, tlb_req_inprogress_q : std_ulogic_vector(0 to thdid_width-1); +signal ex1_deratre, ex1_deratwe, ex1_deratsx : std_ulogic; +signal ex2_dsi_d, ex2_dsi_q : std_ulogic_vector(0 to 15); +signal ex2_noop_touch_d, ex2_noop_touch_q : std_ulogic_vector(0 to 15); +signal ex3_miss_d, ex3_miss_q : std_ulogic_vector(0 to thdid_width-1); +signal ex3_dsi_d, ex3_dsi_q : std_ulogic_vector(0 to 15); +signal ex3_noop_touch_d, ex3_noop_touch_q : std_ulogic_vector(0 to 15); +signal ex3_multihit_d, ex3_multihit_q : std_ulogic_vector(0 to thdid_width-1); +signal ex3_multihit_b_pt_d, ex3_multihit_b_pt_q : std_ulogic_vector(1 to num_entry); +signal ex3_first_hit_entry_pt_d, ex3_first_hit_entry_pt_q : std_ulogic_vector(1 to num_entry-1); +signal ex3_parerr_d, ex3_parerr_q : std_ulogic_vector(0 to thdid_width+1); +signal ex3_attr_d, ex3_attr_q : std_ulogic_vector(0 to 5); +signal ex3_tlbreq_d, ex3_tlbreq_q : std_ulogic; +signal ex3_hit_d, ex3_hit_q : std_ulogic; +signal ex3_cam_hit_q : std_ulogic; +signal ex2_debug_d, ex2_debug_q : std_ulogic_vector(0 to 10); +signal ex3_debug_d, ex3_debug_q : std_ulogic_vector(0 to 16); +signal ex3_cam_cmp_data_q : std_ulogic_vector(0 to cam_data_width-1); +signal ex3_array_cmp_data_q : std_ulogic_vector(0 to array_data_width-1); +signal ex4_rd_array_data_d, ex4_rd_array_data_q : std_ulogic_vector(0 to array_data_width-1); +signal ex4_rd_cam_data_d, ex4_rd_cam_data_q : std_ulogic_vector(0 to cam_data_width-1); +signal ex4_parerr_d, ex4_parerr_q : std_ulogic_vector(0 to thdid_width+1); +signal ex4_fir_parerr_d, ex4_fir_parerr_q : std_ulogic_vector(0 to thdid_width+2); +signal ex4_fir_multihit_d, ex4_fir_multihit_q : std_ulogic_vector(0 to thdid_width-1); +signal ex4_deen_d, ex4_deen_q : std_ulogic_vector(0 to thdid_width+num_entry_log2-1); +signal ex4_hit_d, ex4_hit_q : std_ulogic; +signal ex5_deen_d, ex5_deen_q : std_ulogic_vector(0 to thdid_width+num_entry_log2-1); +signal ex5_hit_d, ex5_hit_q : std_ulogic; +signal ex6_deen_d, ex6_deen_q : std_ulogic_vector(0 to num_entry_log2); +signal ex6_hit_d, ex6_hit_q : std_ulogic; +signal ex3_deratwe, ex4_deratwe, ex5_deratwe, ex6_deratwe, ex7_deratwe : std_ulogic; +signal ex6_deratwe_ws3 : std_ulogic; +signal barrier_done_d, barrier_done_q : std_ulogic_vector(0 to thdid_width-1); +signal mmucr1_d, mmucr1_q : std_ulogic_vector(0 to 9); +signal mmucr1_b0_cpy_d, mmucr1_b0_cpy_q : std_ulogic; +signal lru_rmt_vec_d, lru_rmt_vec_q : std_ulogic_vector(0 to lru_width); +signal ex3_dsi : std_ulogic_vector(0 to 7); +signal ex3_noop_touch : std_ulogic_vector(0 to 7); +signal por_seq_d, por_seq_q : std_ulogic_vector(0 to 2); +signal rpn_holdreg0_d, rpn_holdreg0_q : std_ulogic_vector(0 to 63); +signal rpn_holdreg1_d, rpn_holdreg1_q : std_ulogic_vector(0 to 63); +signal rpn_holdreg2_d, rpn_holdreg2_q : std_ulogic_vector(0 to 63); +signal rpn_holdreg3_d, rpn_holdreg3_q : std_ulogic_vector(0 to 63); +signal watermark_d, watermark_q : std_ulogic_vector(0 to watermark_width-1); +signal eptr_d, eptr_q : std_ulogic_vector(0 to eptr_width-1); +signal lru_d, lru_q : std_ulogic_vector(1 to lru_width); +signal lru_update_event_d, lru_update_event_q : std_ulogic_vector(0 to 9); +signal lru_debug_d, lru_debug_q : std_ulogic_vector(0 to 40); +signal snoop_val_d, snoop_val_q : std_ulogic_vector(0 to 2); +signal snoop_attr_d, snoop_attr_q : std_ulogic_vector(0 to 25); +signal snoop_addr_d, snoop_addr_q : std_ulogic_vector(52-epn_width to 51); +signal ex2_epn_d, ex2_epn_q : std_ulogic_vector(52-ex2_epn_width to 51); +signal pc_xu_init_reset_q : std_ulogic; +signal tlb_rel_val_d, tlb_rel_val_q : std_ulogic_vector(0 to 4); +signal tlb_rel_data_d, tlb_rel_data_q : std_ulogic_vector(0 to 131); +signal eplc_wr_d, eplc_wr_q : std_ulogic_vector(0 to 2*thdid_width); +signal epsc_wr_d, epsc_wr_q : std_ulogic_vector(0 to 2*thdid_width); +signal ccr2_frat_paranoia_d, ccr2_frat_paranoia_q : std_ulogic_vector(0 to 11); +signal ccr2_notlb_q, xucr4_mmu_mchk_q : std_ulogic; +signal mchk_flash_inv_d, mchk_flash_inv_q : std_ulogic_vector(0 to 3); +signal mchk_flash_inv_enab : std_ulogic; +signal bcfg_q, bcfg_q_b : std_ulogic_vector(0 to bcfg_width-1); +-- logic signals +signal por_wr_cam_val : std_ulogic_vector(0 to 1); +signal por_wr_array_val : std_ulogic_vector(0 to 1); +signal por_wr_cam_data : std_ulogic_vector(0 to cam_data_width-1); +signal por_wr_array_data : std_ulogic_vector(0 to array_data_width-1); +signal por_wr_entry : std_ulogic_vector(0 to num_entry_log2-1); +signal por_hold_req : std_ulogic_vector(0 to thdid_width-1); +signal ex2_multihit_b : std_ulogic; +signal ex2_first_hit_entry : std_ulogic_vector(0 to num_entry_log2-1); +signal ex3_first_hit_entry : std_ulogic_vector(0 to num_entry_log2-1); +signal ex3_dsi_enab : std_ulogic; +signal ex3_noop_touch_enab : std_ulogic; +signal ex3_multihit_enab : std_ulogic; +signal ex3_parerr_enab : std_ulogic; +-- synopsys translate_off +-- synopsys translate_on +signal ex3_eratsx_data : std_ulogic_vector(0 to 2+num_entry_log2-1); +signal hold_req_set : std_ulogic_vector(0 to thdid_width-1); +signal hold_req : std_ulogic_vector(0 to thdid_width-1); +signal lru_way_encode : std_ulogic_vector(0 to num_entry_log2-1); +signal lru_rmt_vec : std_ulogic_vector(0 to lru_width); +signal lru_reset_vec, lru_set_vec : std_ulogic_vector(1 to lru_width); +signal lru_op_vec, lru_vp_vec : std_ulogic_vector(1 to lru_width); +signal lru_eff : std_ulogic_vector(1 to lru_width); +signal lru_watermark_mask : std_ulogic_vector(0 to lru_width); +signal entry_valid_watermarked : std_ulogic_vector(0 to lru_width); +signal eptr_p1 : std_ulogic_vector(0 to eptr_width-1); +signal xu_derat_rf1_is_icbtlslc : std_ulogic; +signal ex3_cmp_data_parerr_epn_mac : std_ulogic; +signal ex3_cmp_data_parerr_rpn_mac : std_ulogic; +signal ex3_cmp_data_parerr_epn : std_ulogic; +signal ex3_cmp_data_parerr_rpn : std_ulogic; +signal ex4_rd_data_calc_par : std_ulogic_vector(50 to 67); +signal ex4_rd_data_parerr_epn : std_ulogic; +signal ex4_rd_data_parerr_rpn : std_ulogic; +-- synopsys translate_off +-- synopsys translate_on +signal ex4_parerr_enab : std_ulogic; +signal ex4_fir_parerr_enab : std_ulogic; +signal rf1_mmucr0_gs, rf1_mmucr0_ts : std_ulogic; +signal rf1_eplc_epr, rf1_epsc_epr, rf1_eplc_egs, rf1_epsc_egs, rf1_eplc_eas, rf1_epsc_eas: std_ulogic; +signal rf1_pid, rf1_mmucr0_pid, rf1_eplc_epid, rf1_epsc_epid : std_ulogic_vector(0 to pid_width-1); +signal tlb_rel_cmpmask : std_ulogic_vector(0 to 3); +signal tlb_rel_xbitmask : std_ulogic_vector(0 to 3); +signal tlb_rel_maskpar : std_ulogic; +signal ex6_data_cmpmask : std_ulogic_vector(0 to 3); +signal ex6_data_xbitmask : std_ulogic_vector(0 to 3); +signal ex6_data_maskpar : std_ulogic; +-- CAM/Array signals +-- Read Port +signal rd_val : std_ulogic; +signal rw_entry : std_ulogic_vector(0 to 4); +-- Write Port +signal wr_array_par : std_ulogic_vector(51 to 67); +signal wr_array_data_nopar : std_ulogic_vector(0 to array_data_width-1-10-7); +signal wr_array_data : std_ulogic_vector(0 to array_data_width-1); +signal wr_cam_data : std_ulogic_vector(0 to cam_data_width-1); +signal wr_array_val : std_ulogic_vector(0 to 1); +signal wr_cam_val : std_ulogic_vector(0 to 1); +signal wr_val_early : std_ulogic; +-- CAM Port +signal comp_request : std_ulogic; +signal comp_addr : std_ulogic_vector(0 to 51); +signal addr_enable : std_ulogic_vector(0 to 1); +signal comp_pgsize : std_ulogic_vector(0 to 2); +signal pgsize_enable : std_ulogic; +signal comp_class : std_ulogic_vector(0 to 1); +signal class_enable : std_ulogic_vector(0 to 2); +signal comp_extclass : std_ulogic_vector(0 to 1); +signal extclass_enable : std_ulogic_vector(0 to 1); +signal comp_state : std_ulogic_vector(0 to 1); +signal state_enable : std_ulogic_vector(0 to 1); +signal comp_thdid : std_ulogic_vector(0 to 3); +signal thdid_enable : std_ulogic_vector(0 to 1); +signal comp_pid : std_ulogic_vector(0 to 7); +signal pid_enable : std_ulogic; +signal comp_invalidate : std_ulogic; +signal flash_invalidate : std_ulogic; +-- Array Outputs +signal array_cmp_data : std_ulogic_vector(0 to array_data_width-1); +signal rd_array_data : std_ulogic_vector(0 to array_data_width-1); +-- CAM Outputs +signal cam_cmp_data : std_ulogic_vector(0 to cam_data_width-1); +signal cam_hit : std_ulogic; +signal cam_hit_entry : std_ulogic_vector(0 to 4); +signal entry_match, entry_match_q : std_ulogic_vector(0 to 31); +signal entry_valid, entry_valid_q : std_ulogic_vector(0 to 31); +signal rd_cam_data : std_ulogic_vector(0 to cam_data_width-1); +-- synopsys translate_off +-- synopsys translate_on +signal cam_pgsize : std_ulogic_vector(0 to 2); +signal ws0_pgsize : std_ulogic_vector(0 to 3); +signal bypass_mux_enab_np1 : std_ulogic; +signal bypass_attr_np1 : std_ulogic_vector(0 to 20); +signal attr_np2 : std_ulogic_vector(0 to 20); +signal rpn_np2 : std_ulogic_vector(22 to 51); +-- Pervasive +signal pc_sg_1 : std_ulogic; +signal pc_sg_0 : std_ulogic; +signal pc_func_sl_thold_1 : std_ulogic; +signal pc_func_sl_thold_0 : std_ulogic; +signal pc_func_sl_thold_0_b : std_ulogic; +signal pc_func_slp_sl_thold_1 : std_ulogic; +signal pc_func_slp_sl_thold_0 : std_ulogic; +signal pc_func_slp_sl_thold_0_b : std_ulogic; +signal pc_func_sl_force : std_ulogic; +signal pc_func_slp_sl_force : std_ulogic; +signal pc_cfg_slp_sl_thold_1 : std_ulogic; +signal pc_cfg_slp_sl_thold_0 : std_ulogic; +signal pc_cfg_slp_sl_thold_0_b : std_ulogic; +signal pc_cfg_slp_sl_force : std_ulogic; +signal lcb_dclk : std_ulogic; +signal lcb_lclk : clk_logic; +signal init_alias : std_ulogic; +signal clkg_ctl_override_d :std_ulogic; +signal clkg_ctl_override_q :std_ulogic; +signal rf1_stg_act_d, rf1_stg_act_q :std_ulogic; +signal ex1_stg_act_d, ex1_stg_act_q :std_ulogic; +signal ex2_stg_act_d, ex2_stg_act_q :std_ulogic; +signal ex3_stg_act_d, ex3_stg_act_q :std_ulogic; +signal ex4_stg_act_d, ex4_stg_act_q :std_ulogic; +signal ex5_stg_act_d, ex5_stg_act_q :std_ulogic; +signal ex6_stg_act_d, ex6_stg_act_q :std_ulogic; +signal ex7_stg_act_d, ex7_stg_act_q :std_ulogic; +signal tlb_rel_act_d, tlb_rel_act_q, tlb_rel_act :std_ulogic; +signal an_ac_grffence_en_dc_q, trace_bus_enable_q :std_ulogic; +signal ex2_cmp_data_act, ex3_grffence_act, ex2_or_ex3_grffence_act, ex3_to_ex6_grffence_act :std_ulogic; +signal ex3_rd_data_act, ex3_data_out_act :std_ulogic; +signal entry_valid_act, entry_match_act :std_ulogic; +signal snoop_act_q, snoop_act :std_ulogic; +signal not_grffence_act, lru_update_act, notlb_grffence_act, debug_grffence_act :std_ulogic; +signal spare_a_q :std_ulogic_vector(0 to 15); +signal spare_b_q :std_ulogic_vector(0 to 15); +signal unused_dc : std_ulogic_vector(0 to 39); +-- synopsys translate_off +-- synopsys translate_on +signal siv_0 : std_ulogic_vector(0 to scan_right_0); +signal sov_0 : std_ulogic_vector(0 to scan_right_0); +signal siv_1 : std_ulogic_vector(0 to scan_right_1); +signal sov_1 : std_ulogic_vector(0 to scan_right_1); +signal bsiv : std_ulogic_vector(0 to boot_scan_right); +signal bsov : std_ulogic_vector(0 to boot_scan_right); +-- cam component scan chains +signal func_si_cam_int, func_so_cam_int : std_ulogic; +signal tiup : std_ulogic; + BEGIN --@@ START OF EXECUTABLE CODE FOR XUQ_LSU_DERAT + +----------------------------------------------------------------------- +-- ACT Generation +----------------------------------------------------------------------- +clkg_ctl_override_d <= spr_xucr0_clkg_ctl_b1; +rf1_stg_act_d <= or_reduce(xu_derat_rf0_val) or clkg_ctl_override_q; +ex1_stg_act_d <= rf1_stg_act_q or xu_derat_rf1_act or xu_derat_rf1_ra_eq_ea; +ex2_stg_act_d <= ex1_stg_act_q; +ex3_stg_act_d <= ex2_stg_act_q; +ex4_stg_act_d <= ex3_stg_act_q; +ex5_stg_act_d <= ex4_stg_act_q; +ex6_stg_act_d <= ex5_stg_act_q; +ex7_stg_act_d <= ex6_stg_act_q; +ex2_cmp_data_act <= ex2_stg_act_q and not(an_ac_grffence_en_dc); +ex3_rd_data_act <= ex3_stg_act_q and not(an_ac_grffence_en_dc); +ex3_data_out_act <= ex3_stg_act_q and not(an_ac_grffence_en_dc); +ex3_grffence_act <= ex3_stg_act_q and not(an_ac_grffence_en_dc); +ex2_or_ex3_grffence_act <= (ex2_stg_act_q or ex3_stg_act_q) and not(an_ac_grffence_en_dc); +ex3_to_ex6_grffence_act <= (ex3_stg_act_q or ex4_stg_act_q or ex5_stg_act_q or ex6_stg_act_q) and not(an_ac_grffence_en_dc); +entry_valid_act <= not an_ac_grffence_en_dc; +entry_match_act <= not an_ac_grffence_en_dc; +not_grffence_act <= not an_ac_grffence_en_dc; +lru_update_act <= ex6_stg_act_q or ex7_stg_act_q or lru_update_event_q(8) or lru_update_event_q(9) or flash_invalidate or ex6_deratwe_ws3; +snoop_act <= snoop_act_q or clkg_ctl_override_q; +notlb_grffence_act <= (not(ccr2_notlb_q) or clkg_ctl_override_q) and not(an_ac_grffence_en_dc); +debug_grffence_act <= trace_bus_enable_q and not(an_ac_grffence_en_dc); +----------------------------------------------------------------------- +-- Logic +----------------------------------------------------------------------- +tiup <= '1'; +init_alias <= pc_xu_init_reset_q; +-- timing latches for the reloads +tlb_rel_val_d <= mm_xu_derat_rel_val; +tlb_rel_data_d <= mm_xu_derat_rel_data; +tlb_rel_act_d <= mm_xu_derat_rel_data(eratpos_relsoon); +tlb_rel_act <= (tlb_rel_act_q and not(ccr2_notlb_q)) or clkg_ctl_override_q; +-- timing latches for the ifrat delusional paranoia real mode +ccr2_frat_paranoia_d(0 TO 8) <= xu_derat_spr_ccr2_dfratsc; +ccr2_frat_paranoia_d(9) <= xu_derat_spr_ccr2_dfrat; +ccr2_frat_paranoia_d(10) <= xu_derat_rf1_ra_eq_ea; +ccr2_frat_paranoia_d(11) <= ccr2_frat_paranoia_q(10); +xu_derat_rf1_is_icbtlslc <= xu_derat_rf1_icbtls_instr or xu_derat_rf1_icblc_instr; +rf1_valid_d <= xu_derat_rf0_val and not(xu_derat_rf0_n_flush); +rf1_ttype_d <= xu_derat_rf0_is_extload & xu_derat_rf0_is_extstore; +rf1_eplc_epr <= (xu_derat_eplc0_epr and rf1_valid_q(0)) or + (xu_derat_eplc1_epr and rf1_valid_q(1)) or + (xu_derat_eplc2_epr and rf1_valid_q(2)) or + (xu_derat_eplc3_epr and rf1_valid_q(3)); +rf1_epsc_epr <= (xu_derat_epsc0_epr and rf1_valid_q(0)) or + (xu_derat_epsc1_epr and rf1_valid_q(1)) or + (xu_derat_epsc2_epr and rf1_valid_q(2)) or + (xu_derat_epsc3_epr and rf1_valid_q(3)); +rf1_eplc_egs <= (xu_derat_eplc0_egs and rf1_valid_q(0)) or + (xu_derat_eplc1_egs and rf1_valid_q(1)) or + (xu_derat_eplc2_egs and rf1_valid_q(2)) or + (xu_derat_eplc3_egs and rf1_valid_q(3)); +rf1_epsc_egs <= (xu_derat_epsc0_egs and rf1_valid_q(0)) or + (xu_derat_epsc1_egs and rf1_valid_q(1)) or + (xu_derat_epsc2_egs and rf1_valid_q(2)) or + (xu_derat_epsc3_egs and rf1_valid_q(3)); +rf1_eplc_eas <= (xu_derat_eplc0_eas and rf1_valid_q(0)) or + (xu_derat_eplc1_eas and rf1_valid_q(1)) or + (xu_derat_eplc2_eas and rf1_valid_q(2)) or + (xu_derat_eplc3_eas and rf1_valid_q(3)); +rf1_epsc_eas <= (xu_derat_epsc0_eas and rf1_valid_q(0)) or + (xu_derat_epsc1_eas and rf1_valid_q(1)) or + (xu_derat_epsc2_eas and rf1_valid_q(2)) or + (xu_derat_epsc3_eas and rf1_valid_q(3)); +rf1_mmucr0_gs <= (mm_xu_derat_mmucr0_0(2) and rf1_valid_q(0)) or + (mm_xu_derat_mmucr0_1(2) and rf1_valid_q(1)) or + (mm_xu_derat_mmucr0_2(2) and rf1_valid_q(2)) or + (mm_xu_derat_mmucr0_3(2) and rf1_valid_q(3)); +rf1_mmucr0_ts <= (mm_xu_derat_mmucr0_0(3) and rf1_valid_q(0)) or + (mm_xu_derat_mmucr0_1(3) and rf1_valid_q(1)) or + (mm_xu_derat_mmucr0_2(3) and rf1_valid_q(2)) or + (mm_xu_derat_mmucr0_3(3) and rf1_valid_q(3)); +rf1_eplc_epid <= (xu_derat_eplc0_epid(50 to 63) and (0 to 13 => rf1_valid_q(0))) or + (xu_derat_eplc1_epid(50 to 63) and (0 to 13 => rf1_valid_q(1))) or + (xu_derat_eplc2_epid(50 to 63) and (0 to 13 => rf1_valid_q(2))) or + (xu_derat_eplc3_epid(50 to 63) and (0 to 13 => rf1_valid_q(3))); +rf1_epsc_epid <= (xu_derat_epsc0_epid(50 to 63) and (0 to 13 => rf1_valid_q(0))) or + (xu_derat_epsc1_epid(50 to 63) and (0 to 13 => rf1_valid_q(1))) or + (xu_derat_epsc2_epid(50 to 63) and (0 to 13 => rf1_valid_q(2))) or + (xu_derat_epsc3_epid(50 to 63) and (0 to 13 => rf1_valid_q(3))); +rf1_mmucr0_pid <= (mm_xu_derat_mmucr0_0(6 to 19) and (0 to 13 => rf1_valid_q(0))) or + (mm_xu_derat_mmucr0_1(6 to 19) and (0 to 13 => rf1_valid_q(1))) or + (mm_xu_derat_mmucr0_2(6 to 19) and (0 to 13 => rf1_valid_q(2))) or + (mm_xu_derat_mmucr0_3(6 to 19) and (0 to 13 => rf1_valid_q(3))); +rf1_pid <= (mm_xu_derat_pid0 and (0 to 13 => rf1_valid_q(0))) or + (mm_xu_derat_pid1 and (0 to 13 => rf1_valid_q(1))) or + (mm_xu_derat_pid2 and (0 to 13 => rf1_valid_q(2))) or + (mm_xu_derat_pid3 and (0 to 13 => rf1_valid_q(3))); +--------------------------------------- +-- ttype <= 0-eratre 1-eratwe 2-eratsx 3-eratilx 4-load 5-store 6-csync 7-isync 8-icbtlslc 9-touch 10-extload 11-extstore +ex1_valid_d <= rf1_valid_q and not(xu_derat_rf1_n_flush); +ex1_ttype_d <= xu_derat_rf1_is_eratre & xu_derat_rf1_is_eratwe & xu_derat_rf1_is_eratsx & xu_derat_rf1_is_eratilx & + xu_derat_rf1_is_load & xu_derat_rf1_is_store & '0' & '0' & + xu_derat_rf1_is_icbtlslc & xu_derat_rf1_is_touch & rf1_ttype_q(10) & rf1_ttype_q(11); +ex1_ws_d <= xu_derat_rf1_ws; +ex1_rs_is_d <= (others => '0'); +ex1_ra_entry_d <= (others => '0'); +-- state: 0:pr 1:gs 2:ds 3:cm +ex1_state_d(0) <= rf1_eplc_epr when rf1_ttype_q(10)='1' + else rf1_epsc_epr when rf1_ttype_q(11)='1' + else or_reduce(xu_derat_msr_pr and rf1_valid_q); +ex1_state_d(1) <= rf1_eplc_egs when rf1_ttype_q(10)='1' + else rf1_epsc_egs when rf1_ttype_q(11)='1' + else rf1_mmucr0_gs when xu_derat_rf1_is_eratsx='1' + else or_reduce(xu_derat_msr_hv and rf1_valid_q); +ex1_state_d(2) <= rf1_eplc_eas when rf1_ttype_q(10)='1' + else rf1_epsc_eas when rf1_ttype_q(11)='1' + else rf1_mmucr0_ts when xu_derat_rf1_is_eratsx='1' + else or_reduce(xu_derat_msr_ds and rf1_valid_q); +ex1_state_d(3) <= or_reduce(xu_derat_msr_cm and rf1_valid_q); +-- mmucr0: 0:1-ECL|TID_NZ, 2:3-tgs/ts, 4:5-tlbsel, 6:19-tid, +ex1_extclass_d <= mm_xu_derat_mmucr0_1(0 to 1) when rf1_valid_q(1)='1' + else mm_xu_derat_mmucr0_2(0 to 1) when rf1_valid_q(2)='1' + else mm_xu_derat_mmucr0_3(0 to 1) when rf1_valid_q(3)='1' + else mm_xu_derat_mmucr0_0(0 to 1); +ex1_tlbsel_d <= mm_xu_derat_mmucr0_1(4 to 5) when rf1_valid_q(1)='1' + else mm_xu_derat_mmucr0_2(4 to 5) when rf1_valid_q(2)='1' + else mm_xu_derat_mmucr0_3(4 to 5) when rf1_valid_q(3)='1' + else mm_xu_derat_mmucr0_0(4 to 5); +ex1_pid_d <= rf1_eplc_epid when rf1_ttype_q(10)='1' + else rf1_epsc_epid when rf1_ttype_q(11)='1' + else rf1_mmucr0_pid when xu_derat_rf1_is_eratsx='1' + else rf1_pid; +ex1_deratre <= or_reduce(ex1_valid_q) and ex1_ttype_q(0) and ex1_tlbsel_q(0) and ex1_tlbsel_q(1); +ex1_deratwe <= or_reduce(ex1_valid_q) and ex1_ttype_q(1) and ex1_tlbsel_q(0) and ex1_tlbsel_q(1); +ex1_deratsx <= or_reduce(ex1_valid_q) and ex1_ttype_q(2) and ex1_tlbsel_q(0) and ex1_tlbsel_q(1); +--------------------------------------- +ex2_valid_d <= ex1_valid_q and not(xu_derat_ex1_n_flush); +ex2_ttype_d(0 TO ttype_width-7) <= ex1_ttype_q(0 to ttype_width-7); +ex2_ttype_d(ttype_width-6 TO ttype_width-5) <= xu_derat_ex1_is_csync & xu_derat_ex1_is_isync; +ex2_ttype_d(ttype_width-4 TO ttype_width-1) <= ex1_ttype_q(ttype_width-4 to ttype_width-1); +ex2_ws_d <= ex1_ws_q; +ex2_rs_is_d <= xu_derat_ex1_rs_is; +ex2_ra_entry_d <= xu_derat_ex1_ra_entry; +ex2_state_d <= ex1_state_q; +ex2_pid_d <= ex1_pid_q; +ex2_extclass_d <= ex1_extclass_q; +ex2_tlbsel_d <= ex1_tlbsel_q; +--------------------------------------- +-- ttype <= 0-eratre 1-eratwe 2-eratsx 3-eratilx 4-load 5-store 6-csync 7-isync 8-icbtlslc 9-touch 10-extload 11-extstore +ex3_valid_d <= ex2_valid_q and not(xu_derat_ex2_n_flush); +ex3_ttype_d <= ex2_ttype_q; +ex3_ws_d <= ex2_ws_q; +ex3_rs_is_d <= ex2_rs_is_q; +ex3_ra_entry_d <= ex2_ra_entry_q; +ex3_tlbsel_d <= ex2_tlbsel_q; +ex3_extclass_d <= ex2_extclass_q; +-- state: 0:pr 1:gs 2:ds 3:cm +ex3_state_d <= ex2_state_q; +ex3_pid_d <= ex2_pid_q; +ex3_lpid_d(0 TO lpid_width-1) <= + ( xu_derat_eplc0_elpid(40 to 47) and (40 to 47 => (ex2_valid_q(0) and ex2_ttype_q(10))) ) + or ( xu_derat_eplc1_elpid(40 to 47) and (40 to 47 => (ex2_valid_q(1) and ex2_ttype_q(10))) ) + or ( xu_derat_eplc2_elpid(40 to 47) and (40 to 47 => (ex2_valid_q(2) and ex2_ttype_q(10))) ) + or ( xu_derat_eplc3_elpid(40 to 47) and (40 to 47 => (ex2_valid_q(3) and ex2_ttype_q(10))) ) + or ( xu_derat_epsc0_elpid(40 to 47) and (40 to 47 => (ex2_valid_q(0) and ex2_ttype_q(11))) ) + or ( xu_derat_epsc1_elpid(40 to 47) and (40 to 47 => (ex2_valid_q(1) and ex2_ttype_q(11))) ) + or ( xu_derat_epsc2_elpid(40 to 47) and (40 to 47 => (ex2_valid_q(2) and ex2_ttype_q(11))) ) + or ( xu_derat_epsc3_elpid(40 to 47) and (40 to 47 => (ex2_valid_q(3) and ex2_ttype_q(11))) ); +ex3_deratwe <= or_reduce(ex3_valid_q) and ex3_ttype_q(1) and ex3_tlbsel_q(0) and ex3_tlbsel_q(1); +ex4_valid_d <= ex3_valid_q and not(xu_derat_ex3_n_flush) and not(ex3_n_flush_req_q) and not(ex3_miss_q); +ex4_ttype_d <= ex3_ttype_q; +ex4_ws_d <= ex3_ws_q; +ex4_rs_is_d <= ex3_rs_is_q; +ex4_ra_entry_d <= ex3_first_hit_entry when ex3_ttype_q(2 to 5)/="0000" else ex3_ra_entry_q; +ex4_tlbsel_d <= ex3_tlbsel_q; +-- muxes for tlbre and sending mmucr0 ExtClass,State,TID +ex4_extclass_d <= rd_cam_data(63 to 64) when (ex3_valid_q/="0000" and ex3_ttype_q(0)='1' and ex3_ws_q="00") + else ex3_extclass_q; +-- state: 0:pr 1:gs 2:ds 3:cm +ex4_state_d <= ex3_state_q(0) & rd_cam_data(65 to 66) & ex3_state_q(3) when (ex3_valid_q/="0000" and ex3_ttype_q(0)='1' and ex3_ws_q="00") + else ex3_state_q; +ex4_pid_d <= rd_cam_data(61 to 62) & rd_cam_data(57 to 60) & rd_cam_data(67 to 74) + when (ex3_valid_q/="0000" and ex3_ttype_q(0)='1' and ex3_ws_q="00") + else ex3_pid_q; +ex4_deratwe <= or_reduce(ex4_valid_q) and ex4_ttype_q(1) and ex4_tlbsel_q(0) and ex4_tlbsel_q(1); +--------------------------------------- +ex5_valid_d <= ex4_valid_q and not(xu_derat_ex4_n_flush); +ex5_ws_d <= ex4_ws_q; +ex5_rs_is_d <= ex4_rs_is_q; +ex5_ra_entry_d <= ex4_ra_entry_q; +ex5_ttype_d <= ex4_ttype_q; +ex5_extclass_d <= ex4_extclass_q; +-- state: 0:pr 1:gs 2:ds 3:cm +ex5_state_d <= ex4_state_q; +ex5_pid_d <= ex4_pid_q; +ex5_tlbsel_d <= ex4_tlbsel_q; +ex5_data_in_d <= xu_derat_ex4_rs_data; +ex5_deratwe <= or_reduce(ex5_valid_q) and ex5_ttype_q(1) and ex5_tlbsel_q(0) and ex5_tlbsel_q(1); +--------------------------------------- +ex6_valid_d <= ex5_valid_q and not(xu_derat_ex5_n_flush); +ex6_ws_d <= ex5_ws_q; +ex6_rs_is_d <= ex5_rs_is_q; +ex6_ra_entry_d <= ex5_ra_entry_q; +-- mmucr1: 0-DRRE, 1-REE, 2-CEE, +-- 3-Disable any context sync inst from invalidating extclass=0 erat entries, +-- 4-Disable isync inst from invalidating extclass=0 erat entries, +-- 5:6-PEI, 7:8-DCTID|DTTID, 9-DCCD +-- ttype <= 0-eratre & 1-eratwe & 2-eratsx & 3-eratilx & 4-load & 5-store & +-- 6-csync & 7-isync & 8-icbtlslc & 9-touch & 10-extload & 11-extstore; +ex6_ttype_d(0 TO 5) <= ex5_ttype_q(0 to 5); +ex6_ttype_d(6) <= '1' when (ex5_ttype_q(6)='1' and mmucr1_q(3)='0' and ccr2_notlb_q=MMU_Mode_Value) + else '0'; +ex6_ttype_d(7) <= '1' when (ex5_ttype_q(7)='1' and mmucr1_q(4)='0' and ccr2_notlb_q=MMU_Mode_Value) + else '0'; +ex6_ttype_d(8 TO ttype_width-1) <= ex5_ttype_q(8 to ttype_width-1); +-- mmucr0: 0:1-ECL|TID_NZ, 2:3-tgs/ts, 4:5-tlbsel, 6:19-tid, +ex6_extclass_d <= mm_xu_derat_mmucr0_0(0 to 1) + when (ex5_valid_q="1000" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else mm_xu_derat_mmucr0_1(0 to 1) + when (ex5_valid_q="0100" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else mm_xu_derat_mmucr0_2(0 to 1) + when (ex5_valid_q="0010" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else mm_xu_derat_mmucr0_3(0 to 1) + when (ex5_valid_q="0001" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else ex5_extclass_q; +-- state: 0:pr 1:gs 2:ds 3:cm +ex6_state_d <= xu_derat_msr_pr(0) & mm_xu_derat_mmucr0_0(2 to 3) & xu_derat_msr_cm(0) + when (ex5_valid_q="1000" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else xu_derat_msr_pr(1) & mm_xu_derat_mmucr0_1(2 to 3) & xu_derat_msr_cm(1) + when (ex5_valid_q="0100" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else xu_derat_msr_pr(2) & mm_xu_derat_mmucr0_2(2 to 3) & xu_derat_msr_cm(2) + when (ex5_valid_q="0010" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else xu_derat_msr_pr(3) & mm_xu_derat_mmucr0_3(2 to 3) & xu_derat_msr_cm(3) + when (ex5_valid_q="0001" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else ex5_state_q; +ex6_pid_d <= mm_xu_derat_mmucr0_0(6 to 19) + when (ex5_valid_q="1000" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else mm_xu_derat_mmucr0_1(6 to 19) + when (ex5_valid_q="0100" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else mm_xu_derat_mmucr0_2(6 to 19) + when (ex5_valid_q="0010" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else mm_xu_derat_mmucr0_3(6 to 19) + when (ex5_valid_q="0001" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else ex5_pid_q; +ex6_tlbsel_d <= mm_xu_derat_mmucr0_0(4 to 5) + when (ex5_valid_q="1000" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else mm_xu_derat_mmucr0_1(4 to 5) + when (ex5_valid_q="0100" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else mm_xu_derat_mmucr0_2(4 to 5) + when (ex5_valid_q="0010" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else mm_xu_derat_mmucr0_3(4 to 5) + when (ex5_valid_q="0001" and ex5_ttype_q(1)='1' and ex5_ws_q="00") + else ex5_tlbsel_q; +ex6_data_in_d <= ex5_data_in_q; +ex6_deratwe <= or_reduce(ex6_valid_q) and ex6_ttype_q(1) and ex6_tlbsel_q(0) and ex6_tlbsel_q(1); +--------------------------------------- +-- for flushing +ex7_valid_d <= ex6_valid_q; +ex7_ttype_d <= ex6_ttype_q; +ex7_tlbsel_d <= ex6_tlbsel_q; +ex7_deratwe <= or_reduce(ex7_valid_q) and ex7_ttype_q(1) and ex7_tlbsel_q(0) and ex7_tlbsel_q(1); +mmucr1_d <= mm_xu_derat_mmucr1; +-- formation of ex2 phase multihit complement signal +-- +-- Final Table Listing +-- *INPUTS*==============================*OUTPUTS*==========* +-- | | | +-- | entry_match | ex2_multihit_b | +-- | | | | | +-- | | | | | +-- | | | | | +-- | | 1111111111222222222233 | | | +-- | 01234567890123456789012345678901 | | | +-- *TYPE*================================+==================+ +-- | PPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPP | P | +-- *POLARITY*--------------------------->| + | +-- *PHASE*------------------------------>| T | +-- *OPTIMIZE*--------------------------->| A | +-- *TERMS*===============================+==================+ +-- 1 | -0000000000000000000000000000000 | 1 | +-- 2 | 0-000000000000000000000000000000 | 1 | +-- 3 | 00-00000000000000000000000000000 | 1 | +-- 4 | 000-0000000000000000000000000000 | 1 | +-- 5 | 0000-000000000000000000000000000 | 1 | +-- 6 | 00000-00000000000000000000000000 | 1 | +-- 7 | 000000-0000000000000000000000000 | 1 | +-- 8 | 0000000-000000000000000000000000 | 1 | +-- 9 | 00000000-00000000000000000000000 | 1 | +-- 10 | 000000000-0000000000000000000000 | 1 | +-- 11 | 0000000000-000000000000000000000 | 1 | +-- 12 | 00000000000-00000000000000000000 | 1 | +-- 13 | 000000000000-0000000000000000000 | 1 | +-- 14 | 0000000000000-000000000000000000 | 1 | +-- 15 | 00000000000000-00000000000000000 | 1 | +-- 16 | 000000000000000-0000000000000000 | 1 | +-- 17 | 0000000000000000-000000000000000 | 1 | +-- 18 | 00000000000000000-00000000000000 | 1 | +-- 19 | 000000000000000000-0000000000000 | 1 | +-- 20 | 0000000000000000000-000000000000 | 1 | +-- 21 | 00000000000000000000-00000000000 | 1 | +-- 22 | 000000000000000000000-0000000000 | 1 | +-- 23 | 0000000000000000000000-000000000 | 1 | +-- 24 | 00000000000000000000000-00000000 | 1 | +-- 25 | 000000000000000000000000-0000000 | 1 | +-- 26 | 0000000000000000000000000-000000 | 1 | +-- 27 | 00000000000000000000000000-00000 | 1 | +-- 28 | 000000000000000000000000000-0000 | 1 | +-- 29 | 0000000000000000000000000000-000 | 1 | +-- 30 | 00000000000000000000000000000-00 | 1 | +-- 31 | 000000000000000000000000000000-0 | 1 | +-- 32 | 0000000000000000000000000000000- | 1 | +-- *========================================================* +-- +-- Table EX2_MULTIHIT_B Signal Assignments for Product Terms +MQQ1:EX2_MULTIHIT_B_PT(1) <= + Eq(( ENTRY_MATCH(1) & ENTRY_MATCH(2) & + ENTRY_MATCH(3) & ENTRY_MATCH(4) & + ENTRY_MATCH(5) & ENTRY_MATCH(6) & + ENTRY_MATCH(7) & ENTRY_MATCH(8) & + ENTRY_MATCH(9) & ENTRY_MATCH(10) & + ENTRY_MATCH(11) & ENTRY_MATCH(12) & + ENTRY_MATCH(13) & ENTRY_MATCH(14) & + ENTRY_MATCH(15) & ENTRY_MATCH(16) & + ENTRY_MATCH(17) & ENTRY_MATCH(18) & + ENTRY_MATCH(19) & ENTRY_MATCH(20) & + ENTRY_MATCH(21) & ENTRY_MATCH(22) & + ENTRY_MATCH(23) & ENTRY_MATCH(24) & + ENTRY_MATCH(25) & ENTRY_MATCH(26) & + ENTRY_MATCH(27) & ENTRY_MATCH(28) & + ENTRY_MATCH(29) & ENTRY_MATCH(30) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ2:EX2_MULTIHIT_B_PT(2) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(2) & + ENTRY_MATCH(3) & ENTRY_MATCH(4) & + ENTRY_MATCH(5) & ENTRY_MATCH(6) & + ENTRY_MATCH(7) & ENTRY_MATCH(8) & + ENTRY_MATCH(9) & ENTRY_MATCH(10) & + ENTRY_MATCH(11) & ENTRY_MATCH(12) & + ENTRY_MATCH(13) & ENTRY_MATCH(14) & + ENTRY_MATCH(15) & ENTRY_MATCH(16) & + ENTRY_MATCH(17) & ENTRY_MATCH(18) & + ENTRY_MATCH(19) & ENTRY_MATCH(20) & + ENTRY_MATCH(21) & ENTRY_MATCH(22) & + ENTRY_MATCH(23) & ENTRY_MATCH(24) & + ENTRY_MATCH(25) & ENTRY_MATCH(26) & + ENTRY_MATCH(27) & ENTRY_MATCH(28) & + ENTRY_MATCH(29) & ENTRY_MATCH(30) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ3:EX2_MULTIHIT_B_PT(3) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(3) & ENTRY_MATCH(4) & + ENTRY_MATCH(5) & ENTRY_MATCH(6) & + ENTRY_MATCH(7) & ENTRY_MATCH(8) & + ENTRY_MATCH(9) & ENTRY_MATCH(10) & + ENTRY_MATCH(11) & ENTRY_MATCH(12) & + ENTRY_MATCH(13) & ENTRY_MATCH(14) & + ENTRY_MATCH(15) & ENTRY_MATCH(16) & + ENTRY_MATCH(17) & ENTRY_MATCH(18) & + ENTRY_MATCH(19) & ENTRY_MATCH(20) & + ENTRY_MATCH(21) & ENTRY_MATCH(22) & + ENTRY_MATCH(23) & ENTRY_MATCH(24) & + ENTRY_MATCH(25) & ENTRY_MATCH(26) & + ENTRY_MATCH(27) & ENTRY_MATCH(28) & + ENTRY_MATCH(29) & ENTRY_MATCH(30) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ4:EX2_MULTIHIT_B_PT(4) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(4) & + ENTRY_MATCH(5) & ENTRY_MATCH(6) & + ENTRY_MATCH(7) & ENTRY_MATCH(8) & + ENTRY_MATCH(9) & ENTRY_MATCH(10) & + ENTRY_MATCH(11) & ENTRY_MATCH(12) & + ENTRY_MATCH(13) & ENTRY_MATCH(14) & + ENTRY_MATCH(15) & ENTRY_MATCH(16) & + ENTRY_MATCH(17) & ENTRY_MATCH(18) & + ENTRY_MATCH(19) & ENTRY_MATCH(20) & + ENTRY_MATCH(21) & ENTRY_MATCH(22) & + ENTRY_MATCH(23) & ENTRY_MATCH(24) & + ENTRY_MATCH(25) & ENTRY_MATCH(26) & + ENTRY_MATCH(27) & ENTRY_MATCH(28) & + ENTRY_MATCH(29) & ENTRY_MATCH(30) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ5:EX2_MULTIHIT_B_PT(5) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(5) & ENTRY_MATCH(6) & + ENTRY_MATCH(7) & ENTRY_MATCH(8) & + ENTRY_MATCH(9) & ENTRY_MATCH(10) & + ENTRY_MATCH(11) & ENTRY_MATCH(12) & + ENTRY_MATCH(13) & ENTRY_MATCH(14) & + ENTRY_MATCH(15) & ENTRY_MATCH(16) & + ENTRY_MATCH(17) & ENTRY_MATCH(18) & + ENTRY_MATCH(19) & ENTRY_MATCH(20) & + ENTRY_MATCH(21) & ENTRY_MATCH(22) & + ENTRY_MATCH(23) & ENTRY_MATCH(24) & + ENTRY_MATCH(25) & ENTRY_MATCH(26) & + ENTRY_MATCH(27) & ENTRY_MATCH(28) & + ENTRY_MATCH(29) & ENTRY_MATCH(30) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ6:EX2_MULTIHIT_B_PT(6) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(6) & + ENTRY_MATCH(7) & ENTRY_MATCH(8) & + ENTRY_MATCH(9) & ENTRY_MATCH(10) & + ENTRY_MATCH(11) & ENTRY_MATCH(12) & + ENTRY_MATCH(13) & ENTRY_MATCH(14) & + ENTRY_MATCH(15) & ENTRY_MATCH(16) & + ENTRY_MATCH(17) & ENTRY_MATCH(18) & + ENTRY_MATCH(19) & ENTRY_MATCH(20) & + ENTRY_MATCH(21) & ENTRY_MATCH(22) & + ENTRY_MATCH(23) & ENTRY_MATCH(24) & + ENTRY_MATCH(25) & ENTRY_MATCH(26) & + ENTRY_MATCH(27) & ENTRY_MATCH(28) & + ENTRY_MATCH(29) & ENTRY_MATCH(30) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ7:EX2_MULTIHIT_B_PT(7) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(7) & ENTRY_MATCH(8) & + ENTRY_MATCH(9) & ENTRY_MATCH(10) & + ENTRY_MATCH(11) & ENTRY_MATCH(12) & + ENTRY_MATCH(13) & ENTRY_MATCH(14) & + ENTRY_MATCH(15) & ENTRY_MATCH(16) & + ENTRY_MATCH(17) & ENTRY_MATCH(18) & + ENTRY_MATCH(19) & ENTRY_MATCH(20) & + ENTRY_MATCH(21) & ENTRY_MATCH(22) & + ENTRY_MATCH(23) & ENTRY_MATCH(24) & + ENTRY_MATCH(25) & ENTRY_MATCH(26) & + ENTRY_MATCH(27) & ENTRY_MATCH(28) & + ENTRY_MATCH(29) & ENTRY_MATCH(30) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ8:EX2_MULTIHIT_B_PT(8) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(8) & + ENTRY_MATCH(9) & ENTRY_MATCH(10) & + ENTRY_MATCH(11) & ENTRY_MATCH(12) & + ENTRY_MATCH(13) & ENTRY_MATCH(14) & + ENTRY_MATCH(15) & ENTRY_MATCH(16) & + ENTRY_MATCH(17) & ENTRY_MATCH(18) & + ENTRY_MATCH(19) & ENTRY_MATCH(20) & + ENTRY_MATCH(21) & ENTRY_MATCH(22) & + ENTRY_MATCH(23) & ENTRY_MATCH(24) & + ENTRY_MATCH(25) & ENTRY_MATCH(26) & + ENTRY_MATCH(27) & ENTRY_MATCH(28) & + ENTRY_MATCH(29) & ENTRY_MATCH(30) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ9:EX2_MULTIHIT_B_PT(9) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(9) & ENTRY_MATCH(10) & + ENTRY_MATCH(11) & ENTRY_MATCH(12) & + ENTRY_MATCH(13) & ENTRY_MATCH(14) & + ENTRY_MATCH(15) & ENTRY_MATCH(16) & + ENTRY_MATCH(17) & ENTRY_MATCH(18) & + ENTRY_MATCH(19) & ENTRY_MATCH(20) & + ENTRY_MATCH(21) & ENTRY_MATCH(22) & + ENTRY_MATCH(23) & ENTRY_MATCH(24) & + ENTRY_MATCH(25) & ENTRY_MATCH(26) & + ENTRY_MATCH(27) & ENTRY_MATCH(28) & + ENTRY_MATCH(29) & ENTRY_MATCH(30) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ10:EX2_MULTIHIT_B_PT(10) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(10) & + ENTRY_MATCH(11) & ENTRY_MATCH(12) & + ENTRY_MATCH(13) & ENTRY_MATCH(14) & + ENTRY_MATCH(15) & ENTRY_MATCH(16) & + ENTRY_MATCH(17) & ENTRY_MATCH(18) & + ENTRY_MATCH(19) & ENTRY_MATCH(20) & + ENTRY_MATCH(21) & ENTRY_MATCH(22) & + ENTRY_MATCH(23) & ENTRY_MATCH(24) & + ENTRY_MATCH(25) & ENTRY_MATCH(26) & + ENTRY_MATCH(27) & ENTRY_MATCH(28) & + ENTRY_MATCH(29) & ENTRY_MATCH(30) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ11:EX2_MULTIHIT_B_PT(11) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(11) & ENTRY_MATCH(12) & + ENTRY_MATCH(13) & ENTRY_MATCH(14) & + ENTRY_MATCH(15) & ENTRY_MATCH(16) & + ENTRY_MATCH(17) & ENTRY_MATCH(18) & + ENTRY_MATCH(19) & ENTRY_MATCH(20) & + ENTRY_MATCH(21) & ENTRY_MATCH(22) & + ENTRY_MATCH(23) & ENTRY_MATCH(24) & + ENTRY_MATCH(25) & ENTRY_MATCH(26) & + ENTRY_MATCH(27) & ENTRY_MATCH(28) & + ENTRY_MATCH(29) & ENTRY_MATCH(30) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ12:EX2_MULTIHIT_B_PT(12) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(12) & + ENTRY_MATCH(13) & ENTRY_MATCH(14) & + ENTRY_MATCH(15) & ENTRY_MATCH(16) & + ENTRY_MATCH(17) & ENTRY_MATCH(18) & + ENTRY_MATCH(19) & ENTRY_MATCH(20) & + ENTRY_MATCH(21) & ENTRY_MATCH(22) & + ENTRY_MATCH(23) & ENTRY_MATCH(24) & + ENTRY_MATCH(25) & ENTRY_MATCH(26) & + ENTRY_MATCH(27) & ENTRY_MATCH(28) & + ENTRY_MATCH(29) & ENTRY_MATCH(30) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ13:EX2_MULTIHIT_B_PT(13) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(13) & ENTRY_MATCH(14) & + ENTRY_MATCH(15) & ENTRY_MATCH(16) & + ENTRY_MATCH(17) & ENTRY_MATCH(18) & + ENTRY_MATCH(19) & ENTRY_MATCH(20) & + ENTRY_MATCH(21) & ENTRY_MATCH(22) & + ENTRY_MATCH(23) & ENTRY_MATCH(24) & + ENTRY_MATCH(25) & ENTRY_MATCH(26) & + ENTRY_MATCH(27) & ENTRY_MATCH(28) & + ENTRY_MATCH(29) & ENTRY_MATCH(30) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ14:EX2_MULTIHIT_B_PT(14) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(14) & + ENTRY_MATCH(15) & ENTRY_MATCH(16) & + ENTRY_MATCH(17) & ENTRY_MATCH(18) & + ENTRY_MATCH(19) & ENTRY_MATCH(20) & + ENTRY_MATCH(21) & ENTRY_MATCH(22) & + ENTRY_MATCH(23) & ENTRY_MATCH(24) & + ENTRY_MATCH(25) & ENTRY_MATCH(26) & + ENTRY_MATCH(27) & ENTRY_MATCH(28) & + ENTRY_MATCH(29) & ENTRY_MATCH(30) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ15:EX2_MULTIHIT_B_PT(15) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(15) & ENTRY_MATCH(16) & + ENTRY_MATCH(17) & ENTRY_MATCH(18) & + ENTRY_MATCH(19) & ENTRY_MATCH(20) & + ENTRY_MATCH(21) & ENTRY_MATCH(22) & + ENTRY_MATCH(23) & ENTRY_MATCH(24) & + ENTRY_MATCH(25) & ENTRY_MATCH(26) & + ENTRY_MATCH(27) & ENTRY_MATCH(28) & + ENTRY_MATCH(29) & ENTRY_MATCH(30) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ16:EX2_MULTIHIT_B_PT(16) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(16) & + ENTRY_MATCH(17) & ENTRY_MATCH(18) & + ENTRY_MATCH(19) & ENTRY_MATCH(20) & + ENTRY_MATCH(21) & ENTRY_MATCH(22) & + ENTRY_MATCH(23) & ENTRY_MATCH(24) & + ENTRY_MATCH(25) & ENTRY_MATCH(26) & + ENTRY_MATCH(27) & ENTRY_MATCH(28) & + ENTRY_MATCH(29) & ENTRY_MATCH(30) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ17:EX2_MULTIHIT_B_PT(17) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(17) & ENTRY_MATCH(18) & + ENTRY_MATCH(19) & ENTRY_MATCH(20) & + ENTRY_MATCH(21) & ENTRY_MATCH(22) & + ENTRY_MATCH(23) & ENTRY_MATCH(24) & + ENTRY_MATCH(25) & ENTRY_MATCH(26) & + ENTRY_MATCH(27) & ENTRY_MATCH(28) & + ENTRY_MATCH(29) & ENTRY_MATCH(30) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ18:EX2_MULTIHIT_B_PT(18) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) & ENTRY_MATCH(18) & + ENTRY_MATCH(19) & ENTRY_MATCH(20) & + ENTRY_MATCH(21) & ENTRY_MATCH(22) & + ENTRY_MATCH(23) & ENTRY_MATCH(24) & + ENTRY_MATCH(25) & ENTRY_MATCH(26) & + ENTRY_MATCH(27) & ENTRY_MATCH(28) & + ENTRY_MATCH(29) & ENTRY_MATCH(30) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ19:EX2_MULTIHIT_B_PT(19) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) & ENTRY_MATCH(17) & + ENTRY_MATCH(19) & ENTRY_MATCH(20) & + ENTRY_MATCH(21) & ENTRY_MATCH(22) & + ENTRY_MATCH(23) & ENTRY_MATCH(24) & + ENTRY_MATCH(25) & ENTRY_MATCH(26) & + ENTRY_MATCH(27) & ENTRY_MATCH(28) & + ENTRY_MATCH(29) & ENTRY_MATCH(30) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ20:EX2_MULTIHIT_B_PT(20) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) & ENTRY_MATCH(17) & + ENTRY_MATCH(18) & ENTRY_MATCH(20) & + ENTRY_MATCH(21) & ENTRY_MATCH(22) & + ENTRY_MATCH(23) & ENTRY_MATCH(24) & + ENTRY_MATCH(25) & ENTRY_MATCH(26) & + ENTRY_MATCH(27) & ENTRY_MATCH(28) & + ENTRY_MATCH(29) & ENTRY_MATCH(30) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ21:EX2_MULTIHIT_B_PT(21) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) & ENTRY_MATCH(17) & + ENTRY_MATCH(18) & ENTRY_MATCH(19) & + ENTRY_MATCH(21) & ENTRY_MATCH(22) & + ENTRY_MATCH(23) & ENTRY_MATCH(24) & + ENTRY_MATCH(25) & ENTRY_MATCH(26) & + ENTRY_MATCH(27) & ENTRY_MATCH(28) & + ENTRY_MATCH(29) & ENTRY_MATCH(30) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ22:EX2_MULTIHIT_B_PT(22) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) & ENTRY_MATCH(17) & + ENTRY_MATCH(18) & ENTRY_MATCH(19) & + ENTRY_MATCH(20) & ENTRY_MATCH(22) & + ENTRY_MATCH(23) & ENTRY_MATCH(24) & + ENTRY_MATCH(25) & ENTRY_MATCH(26) & + ENTRY_MATCH(27) & ENTRY_MATCH(28) & + ENTRY_MATCH(29) & ENTRY_MATCH(30) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ23:EX2_MULTIHIT_B_PT(23) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) & ENTRY_MATCH(17) & + ENTRY_MATCH(18) & ENTRY_MATCH(19) & + ENTRY_MATCH(20) & ENTRY_MATCH(21) & + ENTRY_MATCH(23) & ENTRY_MATCH(24) & + ENTRY_MATCH(25) & ENTRY_MATCH(26) & + ENTRY_MATCH(27) & ENTRY_MATCH(28) & + ENTRY_MATCH(29) & ENTRY_MATCH(30) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ24:EX2_MULTIHIT_B_PT(24) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) & ENTRY_MATCH(17) & + ENTRY_MATCH(18) & ENTRY_MATCH(19) & + ENTRY_MATCH(20) & ENTRY_MATCH(21) & + ENTRY_MATCH(22) & ENTRY_MATCH(24) & + ENTRY_MATCH(25) & ENTRY_MATCH(26) & + ENTRY_MATCH(27) & ENTRY_MATCH(28) & + ENTRY_MATCH(29) & ENTRY_MATCH(30) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ25:EX2_MULTIHIT_B_PT(25) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) & ENTRY_MATCH(17) & + ENTRY_MATCH(18) & ENTRY_MATCH(19) & + ENTRY_MATCH(20) & ENTRY_MATCH(21) & + ENTRY_MATCH(22) & ENTRY_MATCH(23) & + ENTRY_MATCH(25) & ENTRY_MATCH(26) & + ENTRY_MATCH(27) & ENTRY_MATCH(28) & + ENTRY_MATCH(29) & ENTRY_MATCH(30) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ26:EX2_MULTIHIT_B_PT(26) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) & ENTRY_MATCH(17) & + ENTRY_MATCH(18) & ENTRY_MATCH(19) & + ENTRY_MATCH(20) & ENTRY_MATCH(21) & + ENTRY_MATCH(22) & ENTRY_MATCH(23) & + ENTRY_MATCH(24) & ENTRY_MATCH(26) & + ENTRY_MATCH(27) & ENTRY_MATCH(28) & + ENTRY_MATCH(29) & ENTRY_MATCH(30) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ27:EX2_MULTIHIT_B_PT(27) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) & ENTRY_MATCH(17) & + ENTRY_MATCH(18) & ENTRY_MATCH(19) & + ENTRY_MATCH(20) & ENTRY_MATCH(21) & + ENTRY_MATCH(22) & ENTRY_MATCH(23) & + ENTRY_MATCH(24) & ENTRY_MATCH(25) & + ENTRY_MATCH(27) & ENTRY_MATCH(28) & + ENTRY_MATCH(29) & ENTRY_MATCH(30) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ28:EX2_MULTIHIT_B_PT(28) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) & ENTRY_MATCH(17) & + ENTRY_MATCH(18) & ENTRY_MATCH(19) & + ENTRY_MATCH(20) & ENTRY_MATCH(21) & + ENTRY_MATCH(22) & ENTRY_MATCH(23) & + ENTRY_MATCH(24) & ENTRY_MATCH(25) & + ENTRY_MATCH(26) & ENTRY_MATCH(28) & + ENTRY_MATCH(29) & ENTRY_MATCH(30) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ29:EX2_MULTIHIT_B_PT(29) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) & ENTRY_MATCH(17) & + ENTRY_MATCH(18) & ENTRY_MATCH(19) & + ENTRY_MATCH(20) & ENTRY_MATCH(21) & + ENTRY_MATCH(22) & ENTRY_MATCH(23) & + ENTRY_MATCH(24) & ENTRY_MATCH(25) & + ENTRY_MATCH(26) & ENTRY_MATCH(27) & + ENTRY_MATCH(29) & ENTRY_MATCH(30) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ30:EX2_MULTIHIT_B_PT(30) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) & ENTRY_MATCH(17) & + ENTRY_MATCH(18) & ENTRY_MATCH(19) & + ENTRY_MATCH(20) & ENTRY_MATCH(21) & + ENTRY_MATCH(22) & ENTRY_MATCH(23) & + ENTRY_MATCH(24) & ENTRY_MATCH(25) & + ENTRY_MATCH(26) & ENTRY_MATCH(27) & + ENTRY_MATCH(28) & ENTRY_MATCH(30) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ31:EX2_MULTIHIT_B_PT(31) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) & ENTRY_MATCH(17) & + ENTRY_MATCH(18) & ENTRY_MATCH(19) & + ENTRY_MATCH(20) & ENTRY_MATCH(21) & + ENTRY_MATCH(22) & ENTRY_MATCH(23) & + ENTRY_MATCH(24) & ENTRY_MATCH(25) & + ENTRY_MATCH(26) & ENTRY_MATCH(27) & + ENTRY_MATCH(28) & ENTRY_MATCH(29) & + ENTRY_MATCH(31) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +MQQ32:EX2_MULTIHIT_B_PT(32) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) & ENTRY_MATCH(17) & + ENTRY_MATCH(18) & ENTRY_MATCH(19) & + ENTRY_MATCH(20) & ENTRY_MATCH(21) & + ENTRY_MATCH(22) & ENTRY_MATCH(23) & + ENTRY_MATCH(24) & ENTRY_MATCH(25) & + ENTRY_MATCH(26) & ENTRY_MATCH(27) & + ENTRY_MATCH(28) & ENTRY_MATCH(29) & + ENTRY_MATCH(30) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000000")); +-- Table EX2_MULTIHIT_B Signal Assignments for Outputs +MQQ33:EX2_MULTIHIT_B <= + (EX2_MULTIHIT_B_PT(1) OR EX2_MULTIHIT_B_PT(2) + OR EX2_MULTIHIT_B_PT(3) OR EX2_MULTIHIT_B_PT(4) + OR EX2_MULTIHIT_B_PT(5) OR EX2_MULTIHIT_B_PT(6) + OR EX2_MULTIHIT_B_PT(7) OR EX2_MULTIHIT_B_PT(8) + OR EX2_MULTIHIT_B_PT(9) OR EX2_MULTIHIT_B_PT(10) + OR EX2_MULTIHIT_B_PT(11) OR EX2_MULTIHIT_B_PT(12) + OR EX2_MULTIHIT_B_PT(13) OR EX2_MULTIHIT_B_PT(14) + OR EX2_MULTIHIT_B_PT(15) OR EX2_MULTIHIT_B_PT(16) + OR EX2_MULTIHIT_B_PT(17) OR EX2_MULTIHIT_B_PT(18) + OR EX2_MULTIHIT_B_PT(19) OR EX2_MULTIHIT_B_PT(20) + OR EX2_MULTIHIT_B_PT(21) OR EX2_MULTIHIT_B_PT(22) + OR EX2_MULTIHIT_B_PT(23) OR EX2_MULTIHIT_B_PT(24) + OR EX2_MULTIHIT_B_PT(25) OR EX2_MULTIHIT_B_PT(26) + OR EX2_MULTIHIT_B_PT(27) OR EX2_MULTIHIT_B_PT(28) + OR EX2_MULTIHIT_B_PT(29) OR EX2_MULTIHIT_B_PT(30) + OR EX2_MULTIHIT_B_PT(31) OR EX2_MULTIHIT_B_PT(32) + ); + +ex3_multihit_b_pt_d <= ex2_multihit_b_pt; +ex3_multihit_enab <= not or_reduce(ex3_multihit_b_pt_q); +-- Encoder for the ex2 phase first hit entry number +-- +-- Final Table Listing +-- *INPUTS*==============================*OUTPUTS*==============* +-- | | | +-- | entry_match | ex2_first_hit_entry | +-- | | | | | +-- | | | | | +-- | | | | | +-- | | 1111111111222222222233 | | | +-- | 01234567890123456789012345678901 | 01234 | +-- *TYPE*================================+======================+ +-- | PPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPP | PPPPP | +-- *POLARITY*--------------------------->| +++++ | +-- *PHASE*------------------------------>| TTTTT | +-- *OPTIMIZE*--------------------------->| AAAAA | +-- *TERMS*===============================+======================+ +-- 1 | 00000000000000000000000000000001 | 11111 | +-- 2 | 0000000000000000000000000000001- | 1111. | +-- 3 | 000000000000000000000000000001-- | 111.1 | +-- 4 | 00000000000000000000000000001--- | 111.. | +-- 5 | 0000000000000000000000000001---- | 11.11 | +-- 6 | 000000000000000000000000001----- | 11.1. | +-- 7 | 00000000000000000000000001------ | 11..1 | +-- 8 | 0000000000000000000000001------- | 11... | +-- 9 | 000000000000000000000001-------- | 1.111 | +-- 10 | 00000000000000000000001--------- | 1.11. | +-- 11 | 0000000000000000000001---------- | 1.1.1 | +-- 12 | 000000000000000000001----------- | 1.1.. | +-- 13 | 00000000000000000001------------ | 1..11 | +-- 14 | 0000000000000000001------------- | 1..1. | +-- 15 | 000000000000000001-------------- | 1...1 | +-- 16 | 00000000000000001--------------- | 1.... | +-- 17 | 0000000000000001---------------- | .1111 | +-- 18 | 000000000000001----------------- | .111. | +-- 19 | 00000000000001------------------ | .11.1 | +-- 20 | 0000000000001------------------- | .11.. | +-- 21 | 000000000001-------------------- | .1.11 | +-- 22 | 00000000001--------------------- | .1.1. | +-- 23 | 0000000001---------------------- | .1..1 | +-- 24 | 000000001----------------------- | .1... | +-- 25 | 00000001------------------------ | ..111 | +-- 26 | 0000001------------------------- | ..11. | +-- 27 | 000001-------------------------- | ..1.1 | +-- 28 | 00001--------------------------- | ..1.. | +-- 29 | 0001---------------------------- | ...11 | +-- 30 | 001----------------------------- | ...1. | +-- 31 | 01------------------------------ | ....1 | +-- *============================================================* +-- +-- Table EX2_FIRST_HIT_ENTRY Signal Assignments for Product Terms +MQQ34:EX2_FIRST_HIT_ENTRY_PT(1) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) & ENTRY_MATCH(17) & + ENTRY_MATCH(18) & ENTRY_MATCH(19) & + ENTRY_MATCH(20) & ENTRY_MATCH(21) & + ENTRY_MATCH(22) & ENTRY_MATCH(23) & + ENTRY_MATCH(24) & ENTRY_MATCH(25) & + ENTRY_MATCH(26) & ENTRY_MATCH(27) & + ENTRY_MATCH(28) & ENTRY_MATCH(29) & + ENTRY_MATCH(30) & ENTRY_MATCH(31) + ) , STD_ULOGIC_VECTOR'("00000000000000000000000000000001")); +MQQ35:EX2_FIRST_HIT_ENTRY_PT(2) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) & ENTRY_MATCH(17) & + ENTRY_MATCH(18) & ENTRY_MATCH(19) & + ENTRY_MATCH(20) & ENTRY_MATCH(21) & + ENTRY_MATCH(22) & ENTRY_MATCH(23) & + ENTRY_MATCH(24) & ENTRY_MATCH(25) & + ENTRY_MATCH(26) & ENTRY_MATCH(27) & + ENTRY_MATCH(28) & ENTRY_MATCH(29) & + ENTRY_MATCH(30) ) , STD_ULOGIC_VECTOR'("0000000000000000000000000000001")); +MQQ36:EX2_FIRST_HIT_ENTRY_PT(3) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) & ENTRY_MATCH(17) & + ENTRY_MATCH(18) & ENTRY_MATCH(19) & + ENTRY_MATCH(20) & ENTRY_MATCH(21) & + ENTRY_MATCH(22) & ENTRY_MATCH(23) & + ENTRY_MATCH(24) & ENTRY_MATCH(25) & + ENTRY_MATCH(26) & ENTRY_MATCH(27) & + ENTRY_MATCH(28) & ENTRY_MATCH(29) + ) , STD_ULOGIC_VECTOR'("000000000000000000000000000001")); +MQQ37:EX2_FIRST_HIT_ENTRY_PT(4) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) & ENTRY_MATCH(17) & + ENTRY_MATCH(18) & ENTRY_MATCH(19) & + ENTRY_MATCH(20) & ENTRY_MATCH(21) & + ENTRY_MATCH(22) & ENTRY_MATCH(23) & + ENTRY_MATCH(24) & ENTRY_MATCH(25) & + ENTRY_MATCH(26) & ENTRY_MATCH(27) & + ENTRY_MATCH(28) ) , STD_ULOGIC_VECTOR'("00000000000000000000000000001")); +MQQ38:EX2_FIRST_HIT_ENTRY_PT(5) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) & ENTRY_MATCH(17) & + ENTRY_MATCH(18) & ENTRY_MATCH(19) & + ENTRY_MATCH(20) & ENTRY_MATCH(21) & + ENTRY_MATCH(22) & ENTRY_MATCH(23) & + ENTRY_MATCH(24) & ENTRY_MATCH(25) & + ENTRY_MATCH(26) & ENTRY_MATCH(27) + ) , STD_ULOGIC_VECTOR'("0000000000000000000000000001")); +MQQ39:EX2_FIRST_HIT_ENTRY_PT(6) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) & ENTRY_MATCH(17) & + ENTRY_MATCH(18) & ENTRY_MATCH(19) & + ENTRY_MATCH(20) & ENTRY_MATCH(21) & + ENTRY_MATCH(22) & ENTRY_MATCH(23) & + ENTRY_MATCH(24) & ENTRY_MATCH(25) & + ENTRY_MATCH(26) ) , STD_ULOGIC_VECTOR'("000000000000000000000000001")); +MQQ40:EX2_FIRST_HIT_ENTRY_PT(7) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) & ENTRY_MATCH(17) & + ENTRY_MATCH(18) & ENTRY_MATCH(19) & + ENTRY_MATCH(20) & ENTRY_MATCH(21) & + ENTRY_MATCH(22) & ENTRY_MATCH(23) & + ENTRY_MATCH(24) & ENTRY_MATCH(25) + ) , STD_ULOGIC_VECTOR'("00000000000000000000000001")); +MQQ41:EX2_FIRST_HIT_ENTRY_PT(8) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) & ENTRY_MATCH(17) & + ENTRY_MATCH(18) & ENTRY_MATCH(19) & + ENTRY_MATCH(20) & ENTRY_MATCH(21) & + ENTRY_MATCH(22) & ENTRY_MATCH(23) & + ENTRY_MATCH(24) ) , STD_ULOGIC_VECTOR'("0000000000000000000000001")); +MQQ42:EX2_FIRST_HIT_ENTRY_PT(9) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) & ENTRY_MATCH(17) & + ENTRY_MATCH(18) & ENTRY_MATCH(19) & + ENTRY_MATCH(20) & ENTRY_MATCH(21) & + ENTRY_MATCH(22) & ENTRY_MATCH(23) + ) , STD_ULOGIC_VECTOR'("000000000000000000000001")); +MQQ43:EX2_FIRST_HIT_ENTRY_PT(10) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) & ENTRY_MATCH(17) & + ENTRY_MATCH(18) & ENTRY_MATCH(19) & + ENTRY_MATCH(20) & ENTRY_MATCH(21) & + ENTRY_MATCH(22) ) , STD_ULOGIC_VECTOR'("00000000000000000000001")); +MQQ44:EX2_FIRST_HIT_ENTRY_PT(11) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) & ENTRY_MATCH(17) & + ENTRY_MATCH(18) & ENTRY_MATCH(19) & + ENTRY_MATCH(20) & ENTRY_MATCH(21) + ) , STD_ULOGIC_VECTOR'("0000000000000000000001")); +MQQ45:EX2_FIRST_HIT_ENTRY_PT(12) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) & ENTRY_MATCH(17) & + ENTRY_MATCH(18) & ENTRY_MATCH(19) & + ENTRY_MATCH(20) ) , STD_ULOGIC_VECTOR'("000000000000000000001")); +MQQ46:EX2_FIRST_HIT_ENTRY_PT(13) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) & ENTRY_MATCH(17) & + ENTRY_MATCH(18) & ENTRY_MATCH(19) + ) , STD_ULOGIC_VECTOR'("00000000000000000001")); +MQQ47:EX2_FIRST_HIT_ENTRY_PT(14) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) & ENTRY_MATCH(17) & + ENTRY_MATCH(18) ) , STD_ULOGIC_VECTOR'("0000000000000000001")); +MQQ48:EX2_FIRST_HIT_ENTRY_PT(15) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) & ENTRY_MATCH(17) + ) , STD_ULOGIC_VECTOR'("000000000000000001")); +MQQ49:EX2_FIRST_HIT_ENTRY_PT(16) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) & + ENTRY_MATCH(16) ) , STD_ULOGIC_VECTOR'("00000000000000001")); +MQQ50:EX2_FIRST_HIT_ENTRY_PT(17) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) & ENTRY_MATCH(15) + ) , STD_ULOGIC_VECTOR'("0000000000000001")); +MQQ51:EX2_FIRST_HIT_ENTRY_PT(18) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) & + ENTRY_MATCH(14) ) , STD_ULOGIC_VECTOR'("000000000000001")); +MQQ52:EX2_FIRST_HIT_ENTRY_PT(19) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) & ENTRY_MATCH(13) + ) , STD_ULOGIC_VECTOR'("00000000000001")); +MQQ53:EX2_FIRST_HIT_ENTRY_PT(20) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) & + ENTRY_MATCH(12) ) , STD_ULOGIC_VECTOR'("0000000000001")); +MQQ54:EX2_FIRST_HIT_ENTRY_PT(21) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) & ENTRY_MATCH(11) + ) , STD_ULOGIC_VECTOR'("000000000001")); +MQQ55:EX2_FIRST_HIT_ENTRY_PT(22) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) & + ENTRY_MATCH(10) ) , STD_ULOGIC_VECTOR'("00000000001")); +MQQ56:EX2_FIRST_HIT_ENTRY_PT(23) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) & ENTRY_MATCH(9) + ) , STD_ULOGIC_VECTOR'("0000000001")); +MQQ57:EX2_FIRST_HIT_ENTRY_PT(24) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) & + ENTRY_MATCH(8) ) , STD_ULOGIC_VECTOR'("000000001")); +MQQ58:EX2_FIRST_HIT_ENTRY_PT(25) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) & ENTRY_MATCH(7) + ) , STD_ULOGIC_VECTOR'("00000001")); +MQQ59:EX2_FIRST_HIT_ENTRY_PT(26) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) & + ENTRY_MATCH(6) ) , STD_ULOGIC_VECTOR'("0000001")); +MQQ60:EX2_FIRST_HIT_ENTRY_PT(27) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) & ENTRY_MATCH(5) + ) , STD_ULOGIC_VECTOR'("000001")); +MQQ61:EX2_FIRST_HIT_ENTRY_PT(28) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) & + ENTRY_MATCH(4) ) , STD_ULOGIC_VECTOR'("00001")); +MQQ62:EX2_FIRST_HIT_ENTRY_PT(29) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) & ENTRY_MATCH(3) + ) , STD_ULOGIC_VECTOR'("0001")); +MQQ63:EX2_FIRST_HIT_ENTRY_PT(30) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) & + ENTRY_MATCH(2) ) , STD_ULOGIC_VECTOR'("001")); +MQQ64:EX2_FIRST_HIT_ENTRY_PT(31) <= + Eq(( ENTRY_MATCH(0) & ENTRY_MATCH(1) + ) , STD_ULOGIC_VECTOR'("01")); +-- Table EX2_FIRST_HIT_ENTRY Signal Assignments for Outputs +MQQ65:EX2_FIRST_HIT_ENTRY(0) <= + (EX2_FIRST_HIT_ENTRY_PT(1) OR EX2_FIRST_HIT_ENTRY_PT(2) + OR EX2_FIRST_HIT_ENTRY_PT(3) OR EX2_FIRST_HIT_ENTRY_PT(4) + OR EX2_FIRST_HIT_ENTRY_PT(5) OR EX2_FIRST_HIT_ENTRY_PT(6) + OR EX2_FIRST_HIT_ENTRY_PT(7) OR EX2_FIRST_HIT_ENTRY_PT(8) + OR EX2_FIRST_HIT_ENTRY_PT(9) OR EX2_FIRST_HIT_ENTRY_PT(10) + OR EX2_FIRST_HIT_ENTRY_PT(11) OR EX2_FIRST_HIT_ENTRY_PT(12) + OR EX2_FIRST_HIT_ENTRY_PT(13) OR EX2_FIRST_HIT_ENTRY_PT(14) + OR EX2_FIRST_HIT_ENTRY_PT(15) OR EX2_FIRST_HIT_ENTRY_PT(16) + ); +MQQ66:EX2_FIRST_HIT_ENTRY(1) <= + (EX2_FIRST_HIT_ENTRY_PT(1) OR EX2_FIRST_HIT_ENTRY_PT(2) + OR EX2_FIRST_HIT_ENTRY_PT(3) OR EX2_FIRST_HIT_ENTRY_PT(4) + OR EX2_FIRST_HIT_ENTRY_PT(5) OR EX2_FIRST_HIT_ENTRY_PT(6) + OR EX2_FIRST_HIT_ENTRY_PT(7) OR EX2_FIRST_HIT_ENTRY_PT(8) + OR EX2_FIRST_HIT_ENTRY_PT(17) OR EX2_FIRST_HIT_ENTRY_PT(18) + OR EX2_FIRST_HIT_ENTRY_PT(19) OR EX2_FIRST_HIT_ENTRY_PT(20) + OR EX2_FIRST_HIT_ENTRY_PT(21) OR EX2_FIRST_HIT_ENTRY_PT(22) + OR EX2_FIRST_HIT_ENTRY_PT(23) OR EX2_FIRST_HIT_ENTRY_PT(24) + ); +MQQ67:EX2_FIRST_HIT_ENTRY(2) <= + (EX2_FIRST_HIT_ENTRY_PT(1) OR EX2_FIRST_HIT_ENTRY_PT(2) + OR EX2_FIRST_HIT_ENTRY_PT(3) OR EX2_FIRST_HIT_ENTRY_PT(4) + OR EX2_FIRST_HIT_ENTRY_PT(9) OR EX2_FIRST_HIT_ENTRY_PT(10) + OR EX2_FIRST_HIT_ENTRY_PT(11) OR EX2_FIRST_HIT_ENTRY_PT(12) + OR EX2_FIRST_HIT_ENTRY_PT(17) OR EX2_FIRST_HIT_ENTRY_PT(18) + OR EX2_FIRST_HIT_ENTRY_PT(19) OR EX2_FIRST_HIT_ENTRY_PT(20) + OR EX2_FIRST_HIT_ENTRY_PT(25) OR EX2_FIRST_HIT_ENTRY_PT(26) + OR EX2_FIRST_HIT_ENTRY_PT(27) OR EX2_FIRST_HIT_ENTRY_PT(28) + ); +MQQ68:EX2_FIRST_HIT_ENTRY(3) <= + (EX2_FIRST_HIT_ENTRY_PT(1) OR EX2_FIRST_HIT_ENTRY_PT(2) + OR EX2_FIRST_HIT_ENTRY_PT(5) OR EX2_FIRST_HIT_ENTRY_PT(6) + OR EX2_FIRST_HIT_ENTRY_PT(9) OR EX2_FIRST_HIT_ENTRY_PT(10) + OR EX2_FIRST_HIT_ENTRY_PT(13) OR EX2_FIRST_HIT_ENTRY_PT(14) + OR EX2_FIRST_HIT_ENTRY_PT(17) OR EX2_FIRST_HIT_ENTRY_PT(18) + OR EX2_FIRST_HIT_ENTRY_PT(21) OR EX2_FIRST_HIT_ENTRY_PT(22) + OR EX2_FIRST_HIT_ENTRY_PT(25) OR EX2_FIRST_HIT_ENTRY_PT(26) + OR EX2_FIRST_HIT_ENTRY_PT(29) OR EX2_FIRST_HIT_ENTRY_PT(30) + ); +MQQ69:EX2_FIRST_HIT_ENTRY(4) <= + (EX2_FIRST_HIT_ENTRY_PT(1) OR EX2_FIRST_HIT_ENTRY_PT(3) + OR EX2_FIRST_HIT_ENTRY_PT(5) OR EX2_FIRST_HIT_ENTRY_PT(7) + OR EX2_FIRST_HIT_ENTRY_PT(9) OR EX2_FIRST_HIT_ENTRY_PT(11) + OR EX2_FIRST_HIT_ENTRY_PT(13) OR EX2_FIRST_HIT_ENTRY_PT(15) + OR EX2_FIRST_HIT_ENTRY_PT(17) OR EX2_FIRST_HIT_ENTRY_PT(19) + OR EX2_FIRST_HIT_ENTRY_PT(21) OR EX2_FIRST_HIT_ENTRY_PT(23) + OR EX2_FIRST_HIT_ENTRY_PT(25) OR EX2_FIRST_HIT_ENTRY_PT(27) + OR EX2_FIRST_HIT_ENTRY_PT(29) OR EX2_FIRST_HIT_ENTRY_PT(31) + ); + +ex3_first_hit_entry_pt_d <= ex2_first_hit_entry_pt; +ex3_first_hit_entry(0) <= + (ex3_first_hit_entry_pt_q(1) or ex3_first_hit_entry_pt_q(2) + or ex3_first_hit_entry_pt_q(3) or ex3_first_hit_entry_pt_q(4) + or ex3_first_hit_entry_pt_q(5) or ex3_first_hit_entry_pt_q(6) + or ex3_first_hit_entry_pt_q(7) or ex3_first_hit_entry_pt_q(8) + or ex3_first_hit_entry_pt_q(9) or ex3_first_hit_entry_pt_q(10) + or ex3_first_hit_entry_pt_q(11) or ex3_first_hit_entry_pt_q(12) + or ex3_first_hit_entry_pt_q(13) or ex3_first_hit_entry_pt_q(14) + or ex3_first_hit_entry_pt_q(15) or ex3_first_hit_entry_pt_q(16)); +ex3_first_hit_entry(1) <= + (ex3_first_hit_entry_pt_q(1) or ex3_first_hit_entry_pt_q(2) + or ex3_first_hit_entry_pt_q(3) or ex3_first_hit_entry_pt_q(4) + or ex3_first_hit_entry_pt_q(5) or ex3_first_hit_entry_pt_q(6) + or ex3_first_hit_entry_pt_q(7) or ex3_first_hit_entry_pt_q(8) + or ex3_first_hit_entry_pt_q(17) or ex3_first_hit_entry_pt_q(18) + or ex3_first_hit_entry_pt_q(19) or ex3_first_hit_entry_pt_q(20) + or ex3_first_hit_entry_pt_q(21) or ex3_first_hit_entry_pt_q(22) + or ex3_first_hit_entry_pt_q(23) or ex3_first_hit_entry_pt_q(24)); +ex3_first_hit_entry(2) <= + (ex3_first_hit_entry_pt_q(1) or ex3_first_hit_entry_pt_q(2) + or ex3_first_hit_entry_pt_q(3) or ex3_first_hit_entry_pt_q(4) + or ex3_first_hit_entry_pt_q(9) or ex3_first_hit_entry_pt_q(10) + or ex3_first_hit_entry_pt_q(11) or ex3_first_hit_entry_pt_q(12) + or ex3_first_hit_entry_pt_q(17) or ex3_first_hit_entry_pt_q(18) + or ex3_first_hit_entry_pt_q(19) or ex3_first_hit_entry_pt_q(20) + or ex3_first_hit_entry_pt_q(25) or ex3_first_hit_entry_pt_q(26) + or ex3_first_hit_entry_pt_q(27) or ex3_first_hit_entry_pt_q(28)); +ex3_first_hit_entry(3) <= + (ex3_first_hit_entry_pt_q(1) or ex3_first_hit_entry_pt_q(2) + or ex3_first_hit_entry_pt_q(5) or ex3_first_hit_entry_pt_q(6) + or ex3_first_hit_entry_pt_q(9) or ex3_first_hit_entry_pt_q(10) + or ex3_first_hit_entry_pt_q(13) or ex3_first_hit_entry_pt_q(14) + or ex3_first_hit_entry_pt_q(17) or ex3_first_hit_entry_pt_q(18) + or ex3_first_hit_entry_pt_q(21) or ex3_first_hit_entry_pt_q(22) + or ex3_first_hit_entry_pt_q(25) or ex3_first_hit_entry_pt_q(26) + or ex3_first_hit_entry_pt_q(29) or ex3_first_hit_entry_pt_q(30)); +ex3_first_hit_entry(4) <= + (ex3_first_hit_entry_pt_q(1) or ex3_first_hit_entry_pt_q(3) + or ex3_first_hit_entry_pt_q(5) or ex3_first_hit_entry_pt_q(7) + or ex3_first_hit_entry_pt_q(9) or ex3_first_hit_entry_pt_q(11) + or ex3_first_hit_entry_pt_q(13) or ex3_first_hit_entry_pt_q(15) + or ex3_first_hit_entry_pt_q(17) or ex3_first_hit_entry_pt_q(19) + or ex3_first_hit_entry_pt_q(21) or ex3_first_hit_entry_pt_q(23) + or ex3_first_hit_entry_pt_q(25) or ex3_first_hit_entry_pt_q(27) + or ex3_first_hit_entry_pt_q(29) or ex3_first_hit_entry_pt_q(31) + ); +-- ttype <= 0-eratre 1-eratwe 2-eratsx 3-eratilx 4-load 5-store 6-csync 7-isync 8-icbtlslc 9-touch 10-extload 11-extstore +ex3_miss_d <= (ex2_valid_q and not(xu_derat_ex2_n_flush) and not(ex2_n_flush_req_q)) + when (cam_hit='0' and ex2_ttype_q(4 to 5) /= "00" and ex2_ttype_q(9)='0' and ccr2_frat_paranoia_q(9)='0') + else (others => '0'); +ex3_hit_d <= or_reduce(ex2_valid_q and not(xu_derat_ex2_n_flush) and not(ex2_n_flush_req_q)) + when (cam_hit='1' and ex2_ttype_q(2 to 5) /= "0000") + else '0'; +ex3_eratsx_data <= ex3_multihit_enab & ex3_hit_q & ex3_first_hit_entry; +ex3_tlbreq_d <= '1' when ((ex2_valid_q and not(xu_derat_ex2_n_flush) and not(ex2_n_flush_req_q) and not(hold_req))/="0000" + and ex2_ttype_q(4 to 5) /= "00" and ex2_ttype_q(9)='0' and cam_hit='0' and ccr2_notlb_q=MMU_Mode_Value + and ccr2_frat_paranoia_q(9)='0') + else '0'; +-- Cancel Hold Request +hold_req_reset_d(0) <= ccr2_frat_paranoia_q(9) or xu_derat_ex2_n_flush(0) or xu_derat_ex3_n_flush(0) or xu_derat_ex4_n_flush(0) or + (tlb_rel_val_q(0) and (ccr2_notlb_q=MMU_Mode_Value)); +-- Hold Request due to ERAT MISS +hold_req_pot_set_d(0) <= ex2_valid_q(0) and not xu_derat_ex2_n_flush(0) and not ex2_n_flush_req_q(0) and + (ex2_ttype_q(4 to 5)/="00") and not ex2_ttype_q(9) and (ccr2_notlb_q=MMU_Mode_Value); +-- Hold Request due to POR +hold_req_por_d(0) <= por_hold_req(0); +hold_req_set(0) <= (hold_req_pot_set_q(0) and not ex3_cam_hit_q); +hold_req(0) <= '1' when hold_req_por_q(0) = '1' else + '0' when hold_req_reset_q(0) = '1' else + '1' when hold_req_set(0) = '1' else + hold_req_q(0); +-- Cancel Hold Request +hold_req_reset_d(1) <= ccr2_frat_paranoia_q(9) or xu_derat_ex2_n_flush(1) or xu_derat_ex3_n_flush(1) or xu_derat_ex4_n_flush(1) or + (tlb_rel_val_q(1) and (ccr2_notlb_q=MMU_Mode_Value)); +-- Hold Request due to ERAT MISS +hold_req_pot_set_d(1) <= ex2_valid_q(1) and not xu_derat_ex2_n_flush(1) and not ex2_n_flush_req_q(1) and + (ex2_ttype_q(4 to 5)/="00") and not ex2_ttype_q(9) and (ccr2_notlb_q=MMU_Mode_Value); +-- Hold Request due to POR +hold_req_por_d(1) <= por_hold_req(1); +hold_req_set(1) <= (hold_req_pot_set_q(1) and not ex3_cam_hit_q); +hold_req(1) <= '1' when hold_req_por_q(1) = '1' else + '0' when hold_req_reset_q(1) = '1' else + '1' when hold_req_set(1) = '1' else + hold_req_q(1); +-- Cancel Hold Request +hold_req_reset_d(2) <= ccr2_frat_paranoia_q(9) or xu_derat_ex2_n_flush(2) or xu_derat_ex3_n_flush(2) or xu_derat_ex4_n_flush(2) or + (tlb_rel_val_q(2) and (ccr2_notlb_q=MMU_Mode_Value)); +-- Hold Request due to ERAT MISS +hold_req_pot_set_d(2) <= ex2_valid_q(2) and not xu_derat_ex2_n_flush(2) and not ex2_n_flush_req_q(2) and + (ex2_ttype_q(4 to 5)/="00") and not ex2_ttype_q(9) and (ccr2_notlb_q=MMU_Mode_Value); +-- Hold Request due to POR +hold_req_por_d(2) <= por_hold_req(2); +hold_req_set(2) <= (hold_req_pot_set_q(2) and not ex3_cam_hit_q); +hold_req(2) <= '1' when hold_req_por_q(2) = '1' else + '0' when hold_req_reset_q(2) = '1' else + '1' when hold_req_set(2) = '1' else + hold_req_q(2); +-- Cancel Hold Request +hold_req_reset_d(3) <= ccr2_frat_paranoia_q(9) or xu_derat_ex2_n_flush(3) or xu_derat_ex3_n_flush(3) or xu_derat_ex4_n_flush(3) or + (tlb_rel_val_q(3) and (ccr2_notlb_q=MMU_Mode_Value)); +-- Hold Request due to ERAT MISS +hold_req_pot_set_d(3) <= ex2_valid_q(3) and not xu_derat_ex2_n_flush(3) and not ex2_n_flush_req_q(3) and + (ex2_ttype_q(4 to 5)/="00") and not ex2_ttype_q(9) and (ccr2_notlb_q=MMU_Mode_Value); +-- Hold Request due to POR +hold_req_por_d(3) <= por_hold_req(3); +hold_req_set(3) <= (hold_req_pot_set_q(3) and not ex3_cam_hit_q); +hold_req(3) <= '1' when hold_req_por_q(3) = '1' else + '0' when hold_req_reset_q(3) = '1' else + '1' when hold_req_set(3) = '1' else + hold_req_q(3); +hold_req_d <= hold_req; +tlb_req_inprogress_d(0) <= '0' when (ccr2_frat_paranoia_q(9)='1' or por_hold_req(0)='1' or ccr2_notlb_q/=MMU_Mode_Value or tlb_rel_val_q(0)='1') + else '0' when (xu_derat_ex3_n_flush(0)='0' and ex3_valid_q(0)='1' and hold_req(0)='0') + else '1' when (ex3_tlbreq_q='1' and ex3_valid_q(0)='1' and ccr2_notlb_q=MMU_Mode_Value) + else tlb_req_inprogress_q(0); +tlb_req_inprogress_d(1) <= '0' when (ccr2_frat_paranoia_q(9)='1' or por_hold_req(1)='1' or ccr2_notlb_q/=MMU_Mode_Value or tlb_rel_val_q(1)='1') + else '0' when (xu_derat_ex3_n_flush(1)='0' and ex3_valid_q(1)='1' and hold_req(1)='0') + else '1' when (ex3_tlbreq_q='1' and ex3_valid_q(1)='1' and ccr2_notlb_q=MMU_Mode_Value) + else tlb_req_inprogress_q(1); +tlb_req_inprogress_d(2) <= '0' when (ccr2_frat_paranoia_q(9)='1' or por_hold_req(2)='1' or ccr2_notlb_q/=MMU_Mode_Value or tlb_rel_val_q(2)='1') + else '0' when (xu_derat_ex3_n_flush(2)='0' and ex3_valid_q(2)='1' and hold_req(2)='0') + else '1' when (ex3_tlbreq_q='1' and ex3_valid_q(2)='1' and ccr2_notlb_q=MMU_Mode_Value) + else tlb_req_inprogress_q(2); +tlb_req_inprogress_d(3) <= '0' when (ccr2_frat_paranoia_q(9)='1' or por_hold_req(3)='1' or ccr2_notlb_q/=MMU_Mode_Value or tlb_rel_val_q(3)='1') + else '0' when (xu_derat_ex3_n_flush(3)='0' and ex3_valid_q(3)='1' and hold_req(3)='0') + else '1' when (ex3_tlbreq_q='1' and ex3_valid_q(3)='1' and ccr2_notlb_q=MMU_Mode_Value) + else tlb_req_inprogress_q(3); +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +--ttype: 0-eratre, 1-eratwe, 2-eratsx, 3-eratilx, +-- 4-load, 5-store, 6-csync, 7-isync, +-- 8-icbtlslc, 9-touch, 10-extload, 11-extstore +ex3_multihit_d <= (ex2_valid_q and not(xu_derat_ex2_n_flush) and not(ex2_n_flush_req_q)) when + (cam_hit='1' and ex2_ttype_q(4 to 5) /= "00" and ex2_ttype_q(9)='0' and ccr2_frat_paranoia_q(9)='0') + else (others => '0'); +ex3_parerr_d(0 TO thdid_width-1) <= (ex2_valid_q and not(xu_derat_ex2_n_flush) and not(ex2_n_flush_req_q)); +ex3_parerr_d(thdid_width) <= (cam_hit and (ex2_ttype_q(4) or ex2_ttype_q(5)) and not ex2_ttype_q(9) and not ccr2_frat_paranoia_q(9)); +ex3_parerr_d(thdid_width+1) <= (cam_hit and ex2_ttype_q(2) and ex2_tlbsel_q(0) and ex2_tlbsel_q(1) + and not(ex3_deratwe or ex4_deratwe or ex5_deratwe or ex6_deratwe or ex7_deratwe)); +ex3_parerr_enab <= ((ex3_parerr_q(thdid_width) and (ex3_cmp_data_parerr_epn or ex3_cmp_data_parerr_rpn)) or + (ex3_parerr_q(thdid_width+1) and ex3_cmp_data_parerr_epn)) and not ex3_multihit_enab; +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +ex4_rd_array_data_d <= rd_array_data; +ex4_rd_cam_data_d <= rd_cam_data; +ex4_parerr_d(0 TO thdid_width-1) <= (ex3_valid_q and not(xu_derat_ex3_n_flush) and not(ex3_n_flush_req_q)); +ex4_parerr_d(thdid_width) <= (ex3_ttype_q(0) and not ex3_ws_q(0) and not ex3_ws_q(1) and ex3_tlbsel_q(0) and ex3_tlbsel_q(1) + and not(ex4_deratwe or ex5_deratwe or ex6_deratwe)); +ex4_parerr_d(thdid_width+1) <= (ex3_ttype_q(0) and xor_reduce(ex3_ws_q) and ex3_tlbsel_q(0) and ex3_tlbsel_q(1) + and not(ex4_deratwe or ex5_deratwe or ex6_deratwe)); +ex4_parerr_enab <= (ex4_parerr_q(thdid_width) and ex4_rd_data_parerr_epn) or + (ex4_parerr_q(thdid_width+1) and ex4_rd_data_parerr_rpn); +ex4_fir_parerr_d(0 TO thdid_width-1) <= (ex3_valid_q and not(xu_derat_ex3_n_flush) and not(ex3_n_flush_req_q)); +ex4_fir_parerr_d(thdid_width) <= (ex3_ttype_q(0) and not ex3_ws_q(0) and not ex3_ws_q(1) and ex3_tlbsel_q(0) and ex3_tlbsel_q(1) + and not(ex4_deratwe or ex5_deratwe or ex6_deratwe)); +ex4_fir_parerr_d(thdid_width+1) <= (ex3_ttype_q(0) and xor_reduce(ex3_ws_q) and ex3_tlbsel_q(0) and ex3_tlbsel_q(1) + and not(ex4_deratwe or ex5_deratwe or ex6_deratwe)); +ex4_fir_parerr_d(thdid_width+2) <= ex3_parerr_enab; +ex4_fir_parerr_enab <= (ex4_fir_parerr_q(thdid_width) and ex4_rd_data_parerr_epn) or + (ex4_fir_parerr_q(thdid_width+1) and ex4_rd_data_parerr_rpn) or + ex4_fir_parerr_q(thdid_width+2); +ex4_fir_multihit_d <= (ex3_multihit_q and not(xu_derat_ex3_n_flush) and not(ex3_n_flush_req_q)) when + (ex3_ttype_q(4 to 5) /= "00" and ex3_ttype_q(9)='0' and ex3_multihit_enab='1') + else (others => '0'); +ex4_deen_d(0 TO thdid_width-1) <= (ex3_multihit_q and not(xu_derat_ex3_n_flush) and not(ex3_n_flush_req_q)) + when ((ex3_ttype_q(4)='1' or ex3_ttype_q(5)='1') and ex3_ttype_q(9)='0' and ex3_multihit_enab='1') + else (others => '0'); +ex4_deen_d(thdid_width TO thdid_width+num_entry_log2-1) <= ex3_eratsx_data(2 to 2+num_entry_log2-1) + when ((ex3_ttype_q(2)='1' or ex3_ttype_q(4)='1' or ex3_ttype_q(5)='1') and ex3_ttype_q(9)='0') + else ex3_ra_entry_q + when (ex3_ttype_q(0)='1' and (ex3_ws_q="00" or ex3_ws_q="01" or ex3_ws_q="10") and ex3_tlbsel_q=TlbSel_DErat) + else (others => '0'); +ex4_hit_d <= ex3_hit_q when or_reduce(ex3_valid_q and not(xu_derat_ex3_n_flush))='1' + else '0'; +ex5_deen_d(0 TO thdid_width-1) <= (ex4_deen_q(0 to thdid_width-1) and not(xu_derat_ex4_n_flush)) or + (ex4_fir_parerr_q(0 to thdid_width-1) and not(xu_derat_ex4_n_flush) and (0 to thdid_width-1 => ex4_fir_parerr_enab)); +ex5_deen_d(thdid_width TO thdid_width+num_entry_log2-1) <= ex4_deen_q(thdid_width to thdid_width+num_entry_log2-1); +ex5_hit_d <= ex4_hit_q when or_reduce(ex4_valid_q and not(xu_derat_ex4_n_flush))='1' + else '0'; +ex6_deen_d <= or_reduce(ex5_deen_q(0 to thdid_width-1)) & + ex5_deen_q(thdid_width to thdid_width+num_entry_log2-1); +ex6_hit_d <= ex5_hit_q when or_reduce(ex5_valid_q and not(xu_derat_ex5_n_flush))='1' + else '0'; +barrier_done_d <= ex6_valid_q when (ex6_ttype_q(0)='1') + else (others => '0'); +-- 16x143 version, 42b RA +-- wr_array_data +-- 0:29 - RPN +-- 30:31 - R,C +-- 32:35 - ResvAttr +-- 36:39 - U0-U3 +-- 40:44 - WIMGE +-- 45:46 - UX,SX +-- 47:48 - UW,SW +-- 49:50 - UR,SR +-- 51:60 - CAM parity +-- 61:67 - Array parity +ex2_dsi_d(0) <= (ex1_ttype_q(5) and not ex1_ttype_q(8) and not ex1_ttype_q(9) and ex1_state_q(0) and not ccr2_frat_paranoia_q(9)); +ex2_dsi_d(1) <= (ex1_ttype_q(4) and not ex1_ttype_q(8) and not ex1_ttype_q(9) and ex1_state_q(0) and not ccr2_frat_paranoia_q(9)); +ex2_dsi_d(2) <= (ex1_ttype_q(4) and ex1_ttype_q(8) and not ex1_ttype_q(9) and ex1_state_q(0) and not ccr2_frat_paranoia_q(9)); +ex2_dsi_d(3) <= (ex1_ttype_q(5) and not ex1_ttype_q(8) and not ex1_ttype_q(9) and not ex1_state_q(0) and not ccr2_frat_paranoia_q(9)); +ex2_dsi_d(4) <= (ex1_ttype_q(4) and not ex1_ttype_q(8) and not ex1_ttype_q(9) and not ex1_state_q(0) and not ccr2_frat_paranoia_q(9)); +ex2_dsi_d(5) <= (ex1_ttype_q(4) and ex1_ttype_q(8) and not ex1_ttype_q(9) and not ex1_state_q(0) and not ccr2_frat_paranoia_q(9)); +ex2_dsi_d(6) <= (ex1_ttype_q(5) and not ex1_ttype_q(9) and mmucr1_q(2) and not ccr2_frat_paranoia_q(9)); +ex2_dsi_d(7) <= (ex1_ttype_q(4) and not ex1_ttype_q(9) and mmucr1_q(1) and not ccr2_frat_paranoia_q(9)); +ex2_dsi_d(8 TO 11) <= (ex1_valid_q and not(xu_derat_ex1_n_flush) and not(ex2_n_flush_req_d)); +ex2_dsi_d(12 TO 15) <= (ex1_valid_q and not(xu_derat_ex1_n_flush) and not(ex2_n_flush_req_d)); +ex3_dsi_d(0 TO 7) <= ex2_dsi_q(0 to 7); +ex3_dsi_d(8 TO 11) <= (ex2_dsi_q(8 to 11) and not(xu_derat_ex2_n_flush) and not(ex2_n_flush_req_q)); +ex3_dsi_d(12 TO 15) <= (ex2_dsi_q(12 to 15) and not(xu_derat_ex2_n_flush) and not(ex2_n_flush_req_q)); +ex3_dsi(0) <= ex3_dsi_q(0) and not ex3_array_cmp_data_q(47); +ex3_dsi(1) <= ex3_dsi_q(1) and not ex3_array_cmp_data_q(49); +ex3_dsi(2) <= ex3_dsi_q(2) and not ex3_array_cmp_data_q(45) and not ex3_array_cmp_data_q(49); +ex3_dsi(3) <= ex3_dsi_q(3) and not ex3_array_cmp_data_q(48); +ex3_dsi(4) <= ex3_dsi_q(4) and not ex3_array_cmp_data_q(50); +ex3_dsi(5) <= ex3_dsi_q(5) and not ex3_array_cmp_data_q(46) and not ex3_array_cmp_data_q(50); +ex3_dsi(6) <= ex3_dsi_q(6) and not ex3_array_cmp_data_q(31); +ex3_dsi(7) <= ex3_dsi_q(7) and not ex3_array_cmp_data_q(30); +ex3_dsi_enab <= or_reduce(ex3_dsi) and not(or_reduce(ex3_miss_q)); +ex2_noop_touch_d(0) <= ((ex1_ttype_q(4) or ex1_ttype_q(5)) and ex1_ttype_q(9)); +ex2_noop_touch_d(1) <= ((ex1_ttype_q(4) or ex1_ttype_q(5)) and ex1_ttype_q(9)); +ex2_noop_touch_d(2) <= ((ex1_ttype_q(4) or ex1_ttype_q(5)) and ex1_ttype_q(9)); +ex2_noop_touch_d(3) <= (ex1_ttype_q(4) and not ex1_ttype_q(8) and ex1_ttype_q(9) and ex1_state_q(0)); +ex2_noop_touch_d(4) <= (ex1_ttype_q(4) and not ex1_ttype_q(8) and ex1_ttype_q(9) and not ex1_state_q(0)); +ex2_noop_touch_d(5) <= (ex1_ttype_q(5) and not ex1_ttype_q(8) and ex1_ttype_q(9) and ex1_state_q(0)); +ex2_noop_touch_d(6) <= (ex1_ttype_q(5) and not ex1_ttype_q(8) and ex1_ttype_q(9) and not ex1_state_q(0)); +ex2_noop_touch_d(7) <= (ex1_ttype_q(4) and ex1_ttype_q(8) and ex1_ttype_q(9)); +ex2_noop_touch_d(8 TO 11) <= (ex1_valid_q and not(xu_derat_ex1_n_flush) and not(ex2_n_flush_req_d)); +ex2_noop_touch_d(12 TO 15) <= (ex1_valid_q and not(xu_derat_ex1_n_flush) and not(ex2_n_flush_req_d)); +ex3_noop_touch_d(0) <= ex2_noop_touch_q(0) and not cam_hit; +-- bits 2:3 used to be multihit/parerr, but not needed for noop_touch because they are flushed by xu regardless of noop_touch +ex3_noop_touch_d(1) <= ex2_noop_touch_q(1) and mmucr1_q(1); +ex3_noop_touch_d(2) <= ex2_noop_touch_q(2) and mmucr1_q(2); +ex3_noop_touch_d(3 TO 7) <= ex2_noop_touch_q(3 to 7); +ex3_noop_touch(0) <= ex3_noop_touch_q(0); +ex3_noop_touch(1) <= ex3_noop_touch_q(1) and not ex3_array_cmp_data_q(30); +ex3_noop_touch(2) <= ex3_noop_touch_q(2) and not ex3_array_cmp_data_q(31); +ex3_noop_touch(3) <= ex3_noop_touch_q(3) and not ex3_array_cmp_data_q(49); +ex3_noop_touch(4) <= ex3_noop_touch_q(4) and not ex3_array_cmp_data_q(50); +ex3_noop_touch(5) <= ex3_noop_touch_q(5) and not ex3_array_cmp_data_q(47); +ex3_noop_touch(6) <= ex3_noop_touch_q(6) and not ex3_array_cmp_data_q(48); +ex3_noop_touch(7) <= ex3_noop_touch_q(7); +ex3_noop_touch_d(8 TO 11) <= (ex2_noop_touch_q(8 to 11) and not(xu_derat_ex2_n_flush) and not(ex2_n_flush_req_q)); +ex3_noop_touch_d(12 TO 15) <= (ex2_noop_touch_q(12 to 15) and not(xu_derat_ex2_n_flush) and not(ex2_n_flush_req_q)); +ex3_noop_touch_enab <= or_reduce(ex3_noop_touch(0 to 7)); +ex3_attr_d <= array_cmp_data(45 to 50) or (0 to 5 => ccr2_frat_paranoia_q(9)); +-- This function is controlled by XUCR4.MMU_MCHK and CCR2.NOTLB bits. +mchk_flash_inv_d(0) <= ex3_parerr_q(thdid_width) and (ex3_cmp_data_parerr_epn or ex3_cmp_data_parerr_rpn); +mchk_flash_inv_d(1) <= ex3_parerr_q(thdid_width) and ex3_multihit_enab; +mchk_flash_inv_d(2) <= (mchk_flash_inv_q(0) or mchk_flash_inv_q(1)) and or_reduce(ex4_parerr_q(0 to thdid_width-1) and not(xu_derat_ex4_n_flush)); +mchk_flash_inv_d(3) <= mchk_flash_inv_enab; +mchk_flash_inv_enab <= mchk_flash_inv_q(2) and not(ccr2_notlb_q) and not(xucr4_mmu_mchk_q); +-- 0 1 2 3 4 5 6 7 8 +--ttype: eratre & eratwe & eratsx & eratilx & load & store & csync & isync & icbtlslc; +ex2_n_flush_req_d <= ex1_valid_q and not(xu_derat_ex1_n_flush) + when ( (tlb_rel_val_q(0 to 3)/="0000" and tlb_rel_val_q(4)='1') + or ((epsc_wr_q(8)='1' or eplc_wr_q(8)='1') and mmucr1_q(7)='0') + or snoop_val_q(0 to 1)="11" + or ((ex1_deratre or ex1_deratwe or ex1_deratsx)='1' and tlb_rel_data_q(eratpos_relsoon)='1') ) + else ex1_valid_q when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_ws_q="00" and ex6_tlbsel_q=TlbSel_DErat) + else ex1_valid_q when ((ex6_valid_q/="0000" and ex6_ttype_q(6 to 7)/="00") or mchk_flash_inv_enab='1' or mchk_flash_inv_q(3)='1') + else (others => '0'); +-- 0 1 2 3 4 5 6 7 8 +--ttype: eratre & eratwe & eratsx & eratilx & load & store & csync & isync & icbtlslc; +-- ex3 flush conditions: +-- ex2 flush +-- tlbwe followed by tlbre, to same hw structure, within 4 cycs +-- tlbwe followed by tlbsx, to same hw structure, within 5 cycs +ex3_n_flush_req_d <= (ex2_valid_q and not(xu_derat_ex2_n_flush)) + when ex2_n_flush_req_q /= "0000" or + (ex3_valid_q /= "0000" and ex3_ttype_q(1)='1' and + ex2_valid_q /= "0000" and ex2_ttype_q(0)='1' and + ex3_tlbsel_q=ex2_tlbsel_q) or + (ex4_valid_q /= "0000" and ex4_ttype_q(1)='1' and + ex2_valid_q /= "0000" and ex2_ttype_q(0)='1' and + ex4_tlbsel_q=ex2_tlbsel_q) or + (ex5_valid_q /= "0000" and ex5_ttype_q(1)='1' and + ex2_valid_q /= "0000" and ex2_ttype_q(0)='1' and + ex5_tlbsel_q=ex2_tlbsel_q) or + (ex6_valid_q /= "0000" and ex6_ttype_q(1)='1' and + ex2_valid_q /= "0000" and ex2_ttype_q(0)='1' and + ex6_tlbsel_q=ex2_tlbsel_q) or + (ex3_valid_q /= "0000" and ex3_ttype_q(1)='1' and + ex2_valid_q /= "0000" and ex2_ttype_q(2)='1' and + ex3_tlbsel_q=ex2_tlbsel_q) or + (ex4_valid_q /= "0000" and ex4_ttype_q(1)='1' and + ex2_valid_q /= "0000" and ex2_ttype_q(2)='1' and + ex4_tlbsel_q=ex2_tlbsel_q) or + (ex5_valid_q /= "0000" and ex5_ttype_q(1)='1' and + ex2_valid_q /= "0000" and ex2_ttype_q(2)='1' and + ex5_tlbsel_q=ex2_tlbsel_q) or + (ex6_valid_q /= "0000" and ex6_ttype_q(1)='1' and + ex2_valid_q /= "0000" and ex2_ttype_q(2)='1' and + ex6_tlbsel_q=ex2_tlbsel_q) or + (ex7_valid_q /= "0000" and ex7_ttype_q(1)='1' and + ex2_valid_q /= "0000" and ex2_ttype_q(2)='1' and + ex7_tlbsel_q=ex2_tlbsel_q) or + (ex3_valid_q /= "0000" and ex3_ttype_q(4 to 5)/="00" and + ex2_valid_q /= "0000" and ex2_ttype_q(0)='1' and + ex2_ws_q="11" and ex2_tlbsel_q=TlbSel_DErat) or + (ex4_valid_q /= "0000" and ex4_ttype_q(4 to 5)/="00" and + ex2_valid_q /= "0000" and ex2_ttype_q(0)='1' and + ex2_ws_q="11" and ex2_tlbsel_q=TlbSel_DErat) or + (ex5_valid_q /= "0000" and ex5_ttype_q(4 to 5)/="00" and + ex2_valid_q /= "0000" and ex2_ttype_q(0)='1' and + ex2_ws_q="11" and ex2_tlbsel_q=TlbSel_DErat) or + (ex6_valid_q /= "0000" and ex6_ttype_q(4 to 5)/="00" and + ex2_valid_q /= "0000" and ex2_ttype_q(0)='1' and + ex2_ws_q="11" and ex2_tlbsel_q=TlbSel_DErat) + else (others => '0'); +snoop_val_d(0) <= mm_xu_derat_snoop_val when snoop_val_q(0)='0' + else '0' when (tlb_rel_val_q(4)='0' and epsc_wr_q(8)='0' and eplc_wr_q(8)='0' and snoop_val_q(1)='1') + else snoop_val_q(0); +snoop_val_d(1) <= not xu_derat_rf1_binv_val; +snoop_val_d(2) <= '0' when (tlb_rel_val_q(4)='1' or epsc_wr_q(8)='1' or eplc_wr_q(8)='1' or snoop_val_q(1)='0') + else snoop_val_q(0); +snoop_attr_d <= mm_xu_derat_snoop_attr when snoop_val_q(0)='0' + else snoop_attr_q; +snoop_addr_d <= mm_xu_derat_snoop_vpn when snoop_val_q(0)='0' + else snoop_addr_q; +xu_mm_derat_snoop_ack <= snoop_val_q(2); +gen64_holdreg: if rs_data_width = 64 generate +rpn_holdreg0_d(0 TO 19) <= ex6_data_in_q(0 to 19) when (ex6_valid_q(0)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='1') + else ex6_data_in_q(32 to 51) when (ex6_valid_q(0)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='0') + else rpn_holdreg0_q(0 to 19); +rpn_holdreg0_d(20 TO 31) <= ex6_data_in_q(20 to 31) when (ex6_valid_q(0)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='1') + else ex6_data_in_q(52 to 63) when (ex6_valid_q(0)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='0') + else rpn_holdreg0_q(20 to 31); +rpn_holdreg0_d(32 TO 51) <= ex6_data_in_q(32 to 51) when (ex6_valid_q(0)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='1') + else ex6_data_in_q(32 to 51) when (ex6_valid_q(0)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='0') + else rpn_holdreg0_q(32 to 51); +rpn_holdreg0_d(52 TO 63) <= ex6_data_in_q(52 to 63) when (ex6_valid_q(0)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='1') + else ex6_data_in_q(52 to 63) when (ex6_valid_q(0)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='0') + else rpn_holdreg0_q(52 to 63); +rpn_holdreg1_d(0 TO 19) <= ex6_data_in_q(0 to 19) when (ex6_valid_q(1)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='1') + else ex6_data_in_q(32 to 51) when (ex6_valid_q(1)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='0') + else rpn_holdreg1_q(0 to 19); +rpn_holdreg1_d(20 TO 31) <= ex6_data_in_q(20 to 31) when (ex6_valid_q(1)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='1') + else ex6_data_in_q(52 to 63) when (ex6_valid_q(1)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='0') + else rpn_holdreg1_q(20 to 31); +rpn_holdreg1_d(32 TO 51) <= ex6_data_in_q(32 to 51) when (ex6_valid_q(1)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='1') + else ex6_data_in_q(32 to 51) when (ex6_valid_q(1)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='0') + else rpn_holdreg1_q(32 to 51); +rpn_holdreg1_d(52 TO 63) <= ex6_data_in_q(52 to 63) when (ex6_valid_q(1)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='1') + else ex6_data_in_q(52 to 63) when (ex6_valid_q(1)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='0') + else rpn_holdreg1_q(52 to 63); +rpn_holdreg2_d(0 TO 19) <= ex6_data_in_q(0 to 19) when (ex6_valid_q(2)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='1') + else ex6_data_in_q(32 to 51) when (ex6_valid_q(2)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='0') + else rpn_holdreg2_q(0 to 19); +rpn_holdreg2_d(20 TO 31) <= ex6_data_in_q(20 to 31) when (ex6_valid_q(2)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='1') + else ex6_data_in_q(52 to 63) when (ex6_valid_q(2)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='0') + else rpn_holdreg2_q(20 to 31); +rpn_holdreg2_d(32 TO 51) <= ex6_data_in_q(32 to 51) when (ex6_valid_q(2)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='1') + else ex6_data_in_q(32 to 51) when (ex6_valid_q(2)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='0') + else rpn_holdreg2_q(32 to 51); +rpn_holdreg2_d(52 TO 63) <= ex6_data_in_q(52 to 63) when (ex6_valid_q(2)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='1') + else ex6_data_in_q(52 to 63) when (ex6_valid_q(2)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='0') + else rpn_holdreg2_q(52 to 63); +rpn_holdreg3_d(0 TO 19) <= ex6_data_in_q(0 to 19) when (ex6_valid_q(3)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='1') + else ex6_data_in_q(32 to 51) when (ex6_valid_q(3)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='0') + else rpn_holdreg3_q(0 to 19); +rpn_holdreg3_d(20 TO 31) <= ex6_data_in_q(20 to 31) when (ex6_valid_q(3)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='1') + else ex6_data_in_q(52 to 63) when (ex6_valid_q(3)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='0') + else rpn_holdreg3_q(20 to 31); +rpn_holdreg3_d(32 TO 51) <= ex6_data_in_q(32 to 51) when (ex6_valid_q(3)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='1') + else ex6_data_in_q(32 to 51) when (ex6_valid_q(3)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='0') + else rpn_holdreg3_q(32 to 51); +rpn_holdreg3_d(52 TO 63) <= ex6_data_in_q(52 to 63) when (ex6_valid_q(3)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='1') + else ex6_data_in_q(52 to 63) when (ex6_valid_q(3)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_DErat and ex6_state_q(3)='0') + else rpn_holdreg3_q(52 to 63); +end generate gen64_holdreg; +gen32_holdreg: if rs_data_width = 32 generate +rpn_holdreg0_d(32 TO 51) <= ex6_data_in_q(32 to 51) when (ex6_valid_q(0)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat) + else rpn_holdreg0_q(32 to 51); +rpn_holdreg0_d(20 TO 31) <= ex6_data_in_q(52 to 63) when (ex6_valid_q(0)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat) + else rpn_holdreg0_q(20 to 31); +rpn_holdreg0_d(52 TO 63) <= ex6_data_in_q(52 to 63) when (ex6_valid_q(0)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_DErat) + else rpn_holdreg0_q(52 to 63); +rpn_holdreg0_d(0 TO 19) <= ex6_data_in_q(32 to 51) when (ex6_valid_q(0)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_DErat) + else rpn_holdreg0_q(0 to 19); +rpn_holdreg1_d(32 TO 51) <= ex6_data_in_q(32 to 51) when (ex6_valid_q(1)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat) + else rpn_holdreg1_q(32 to 51); +rpn_holdreg1_d(20 TO 31) <= ex6_data_in_q(52 to 63) when (ex6_valid_q(1)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat) + else rpn_holdreg1_q(20 to 31); +rpn_holdreg1_d(52 TO 63) <= ex6_data_in_q(52 to 63) when (ex6_valid_q(1)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_DErat) + else rpn_holdreg1_q(52 to 63); +rpn_holdreg1_d(0 TO 19) <= ex6_data_in_q(32 to 51) when (ex6_valid_q(1)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_DErat) + else rpn_holdreg1_q(0 to 19); +rpn_holdreg2_d(32 TO 51) <= ex6_data_in_q(32 to 51) when (ex6_valid_q(2)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat) + else rpn_holdreg2_q(32 to 51); +rpn_holdreg2_d(20 TO 31) <= ex6_data_in_q(52 to 63) when (ex6_valid_q(2)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat) + else rpn_holdreg2_q(20 to 31); +rpn_holdreg2_d(52 TO 63) <= ex6_data_in_q(52 to 63) when (ex6_valid_q(2)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_DErat) + else rpn_holdreg2_q(52 to 63); +rpn_holdreg2_d(0 TO 19) <= ex6_data_in_q(32 to 51) when (ex6_valid_q(2)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_DErat) + else rpn_holdreg2_q(0 to 19); +rpn_holdreg3_d(32 TO 51) <= ex6_data_in_q(32 to 51) when (ex6_valid_q(3)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat) + else rpn_holdreg3_q(32 to 51); +rpn_holdreg3_d(20 TO 31) <= ex6_data_in_q(52 to 63) when (ex6_valid_q(3)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="01" and ex6_tlbsel_q=TlbSel_DErat) + else rpn_holdreg3_q(20 to 31); +rpn_holdreg3_d(52 TO 63) <= ex6_data_in_q(52 to 63) when (ex6_valid_q(3)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_DErat) + else rpn_holdreg3_q(52 to 63); +rpn_holdreg3_d(0 TO 19) <= ex6_data_in_q(32 to 51) when (ex6_valid_q(3)='1' and ex6_ttype_q(1)='1' and + ex6_ws_q="10" and ex6_tlbsel_q=TlbSel_DErat) + else rpn_holdreg3_q(0 to 19); +end generate gen32_holdreg; +ex6_deratwe_ws3 <= or_reduce(ex6_valid_q) and ex6_ttype_q(1) and Eq(ex6_ws_q,"11") and Eq(ex6_tlbsel_q,TlbSel_DErat); +watermark_d <= ex6_data_in_q(64-watermark_width to 63) when ex6_deratwe_ws3='1' + else watermark_q; +-- entry pointer for round-robin mode +eptr_d <= (others => '0') when (ex6_deratwe_ws3='1' and mmucr1_q(0)='1') + else (others => '0') when (eptr_q="11111" or eptr_q=watermark_q) and + ( (ex6_valid_q /= "0000" and ex6_ttype_q(1)='1' and + ex6_ws_q="00" and ex6_tlbsel_q=TlbSel_DErat and mmucr1_q(0)='1') or + (tlb_rel_val_q(0 to 3)/="0000" and tlb_rel_val_q(4)='1' and + tlb_rel_data_q(eratpos_wren)='1' and mmucr1_q(0)='1') ) + else eptr_p1 when ( (ex6_valid_q /= "0000" and ex6_ttype_q(1)='1' and + ex6_ws_q="00" and ex6_tlbsel_q=TlbSel_DErat and mmucr1_q(0)='1') or + (tlb_rel_val_q(0 to 3)/="0000" and tlb_rel_val_q(4)='1' and + tlb_rel_data_q(eratpos_wren)='1' and mmucr1_q(0)='1') ) + else eptr_q; +eptr_p1 <= "00001" when eptr_q="00000" + else "00010" when eptr_q="00001" + else "00011" when eptr_q="00010" + else "00100" when eptr_q="00011" + else "00101" when eptr_q="00100" + else "00110" when eptr_q="00101" + else "00111" when eptr_q="00110" + else "01000" when eptr_q="00111" + else "01001" when eptr_q="01000" + else "01010" when eptr_q="01001" + else "01011" when eptr_q="01010" + else "01100" when eptr_q="01011" + else "01101" when eptr_q="01100" + else "01110" when eptr_q="01101" + else "01111" when eptr_q="01110" + else "10000" when eptr_q="01111" + else "10001" when eptr_q="10000" + else "10010" when eptr_q="10001" + else "10011" when eptr_q="10010" + else "10100" when eptr_q="10011" + else "10101" when eptr_q="10100" + else "10110" when eptr_q="10101" + else "10111" when eptr_q="10110" + else "11000" when eptr_q="10111" + else "11001" when eptr_q="11000" + else "11010" when eptr_q="11001" + else "11011" when eptr_q="11010" + else "11100" when eptr_q="11011" + else "11101" when eptr_q="11100" + else "11110" when eptr_q="11101" + else "11111" when eptr_q="11110" + else "00000"; +ex2_epn_d <= xu_derat_ex1_epn_nonarr(52-ex2_epn_width to 51); +-- lru_update_event +-- 0: tlb reload +-- 1: invalidate snoop +-- 2: csync or isync enabled +-- 3: eratwe WS=0 +-- 4: load or store hit +-- 5: ex3 cam write type events +-- 6: ex3 cam invalidate type events +-- 7: ex3 cam translation type events +-- 8: superset, ex2 +-- 9: superset, delayed to ex3 +lru_update_event_d(0) <= (tlb_rel_data_q(eratpos_wren) and or_reduce(tlb_rel_val_q(0 to 3)) and tlb_rel_val_q(4)); +lru_update_event_d(1) <= (snoop_val_q(0) and snoop_val_q(1)); +lru_update_event_d(2) <= (or_reduce(ex6_valid_q) and or_reduce(ex6_ttype_q(6 to 7))); +lru_update_event_d(3) <= (or_reduce(ex6_valid_q) and ex6_ttype_q(1) + and Eq(ex6_ws_q,"00") and Eq(ex6_tlbsel_q,TlbSel_DErat) and Eq(lru_way_encode,ex6_ra_entry_q)); +lru_update_event_d(4) <= (or_reduce(ex6_valid_q) and or_reduce(ex6_ttype_q(4 to 5)) and ex6_hit_q ); +lru_update_event_d(5) <= lru_update_event_q(0) or lru_update_event_q(3); +lru_update_event_d(6) <= lru_update_event_q(1) or lru_update_event_q(2); +lru_update_event_d(7) <= lru_update_event_q(4); +lru_update_event_d(8) <= (tlb_rel_data_q(eratpos_wren) and or_reduce(tlb_rel_val_q(0 to 3)) and tlb_rel_val_q(4)) + or (snoop_val_q(0) and snoop_val_q(1)) + or (or_reduce(ex6_valid_q) and or_reduce(ex6_ttype_q(6 to 7))) + or (or_reduce(ex6_valid_q) and ex6_ttype_q(1) + and Eq(ex6_ws_q,"00") and Eq(ex6_tlbsel_q,TlbSel_DErat) and Eq(lru_way_encode,ex6_ra_entry_q)) + or (or_reduce(ex6_valid_q) and or_reduce(ex6_ttype_q(4 to 5)) and ex6_hit_q ); +lru_update_event_d(9) <= lru_update_event_q(8); +-- LRU next state.. update bits for which override is zero (Op=0) +-- effective LRU is what is used to choose entry to update +-- lru new value is valid 2 clocks after reload, invalidate, eratwe, or fetch hit +lru_d(1) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(1)='1' and lru_op_vec(1)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(1)='1' and lru_op_vec(1)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(1); +lru_eff(1) <= (lru_vp_vec(1) and lru_op_vec(1)) or (lru_q(1) and not lru_op_vec(1)); +lru_d(2) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(2)='1' and lru_op_vec(2)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(2)='1' and lru_op_vec(2)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(2); +lru_eff(2) <= (lru_vp_vec(2) and lru_op_vec(2)) or (lru_q(2) and not lru_op_vec(2)); +lru_d(3) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(3)='1' and lru_op_vec(3)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(3)='1' and lru_op_vec(3)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(3); +lru_eff(3) <= (lru_vp_vec(3) and lru_op_vec(3)) or (lru_q(3) and not lru_op_vec(3)); +lru_d(4) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(4)='1' and lru_op_vec(4)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(4)='1' and lru_op_vec(4)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(4); +lru_eff(4) <= (lru_vp_vec(4) and lru_op_vec(4)) or (lru_q(4) and not lru_op_vec(4)); +lru_d(5) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(5)='1' and lru_op_vec(5)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(5)='1' and lru_op_vec(5)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(5); +lru_eff(5) <= (lru_vp_vec(5) and lru_op_vec(5)) or (lru_q(5) and not lru_op_vec(5)); +lru_d(6) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(6)='1' and lru_op_vec(6)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(6)='1' and lru_op_vec(6)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(6); +lru_eff(6) <= (lru_vp_vec(6) and lru_op_vec(6)) or (lru_q(6) and not lru_op_vec(6)); +lru_d(7) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(7)='1' and lru_op_vec(7)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(7)='1' and lru_op_vec(7)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(7); +lru_eff(7) <= (lru_vp_vec(7) and lru_op_vec(7)) or (lru_q(7) and not lru_op_vec(7)); +lru_d(8) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(8)='1' and lru_op_vec(8)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(8)='1' and lru_op_vec(8)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(8); +lru_eff(8) <= (lru_vp_vec(8) and lru_op_vec(8)) or (lru_q(8) and not lru_op_vec(8)); +lru_d(9) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(9)='1' and lru_op_vec(9)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(9)='1' and lru_op_vec(9)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(9); +lru_eff(9) <= (lru_vp_vec(9) and lru_op_vec(9)) or (lru_q(9) and not lru_op_vec(9)); +lru_d(10) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(10)='1' and lru_op_vec(10)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(10)='1' and lru_op_vec(10)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(10); +lru_eff(10) <= (lru_vp_vec(10) and lru_op_vec(10)) or (lru_q(10) and not lru_op_vec(10)); +lru_d(11) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(11)='1' and lru_op_vec(11)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(11)='1' and lru_op_vec(11)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(11); +lru_eff(11) <= (lru_vp_vec(11) and lru_op_vec(11)) or (lru_q(11) and not lru_op_vec(11)); +lru_d(12) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(12)='1' and lru_op_vec(12)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(12)='1' and lru_op_vec(12)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(12); +lru_eff(12) <= (lru_vp_vec(12) and lru_op_vec(12)) or (lru_q(12) and not lru_op_vec(12)); +lru_d(13) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(13)='1' and lru_op_vec(13)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(13)='1' and lru_op_vec(13)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(13); +lru_eff(13) <= (lru_vp_vec(13) and lru_op_vec(13)) or (lru_q(13) and not lru_op_vec(13)); +lru_d(14) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(14)='1' and lru_op_vec(14)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(14)='1' and lru_op_vec(14)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(14); +lru_eff(14) <= (lru_vp_vec(14) and lru_op_vec(14)) or (lru_q(14) and not lru_op_vec(14)); +lru_d(15) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(15)='1' and lru_op_vec(15)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(15)='1' and lru_op_vec(15)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(15); +lru_eff(15) <= (lru_vp_vec(15) and lru_op_vec(15)) or (lru_q(15) and not lru_op_vec(15)); +lru_d(16) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(16)='1' and lru_op_vec(16)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(16)='1' and lru_op_vec(16)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(16); +lru_eff(16) <= (lru_vp_vec(16) and lru_op_vec(16)) or (lru_q(16) and not lru_op_vec(16)); +lru_d(17) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(17)='1' and lru_op_vec(17)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(17)='1' and lru_op_vec(17)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(17); +lru_eff(17) <= (lru_vp_vec(17) and lru_op_vec(17)) or (lru_q(17) and not lru_op_vec(17)); +lru_d(18) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(18)='1' and lru_op_vec(18)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(18)='1' and lru_op_vec(18)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(18); +lru_eff(18) <= (lru_vp_vec(18) and lru_op_vec(18)) or (lru_q(18) and not lru_op_vec(18)); +lru_d(19) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(19)='1' and lru_op_vec(19)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(19)='1' and lru_op_vec(19)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(19); +lru_eff(19) <= (lru_vp_vec(19) and lru_op_vec(19)) or (lru_q(19) and not lru_op_vec(19)); +lru_d(20) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(20)='1' and lru_op_vec(20)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(20)='1' and lru_op_vec(20)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(20); +lru_eff(20) <= (lru_vp_vec(20) and lru_op_vec(20)) or (lru_q(20) and not lru_op_vec(20)); +lru_d(21) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(21)='1' and lru_op_vec(21)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(21)='1' and lru_op_vec(21)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(21); +lru_eff(21) <= (lru_vp_vec(21) and lru_op_vec(21)) or (lru_q(21) and not lru_op_vec(21)); +lru_d(22) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(22)='1' and lru_op_vec(22)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(22)='1' and lru_op_vec(22)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(22); +lru_eff(22) <= (lru_vp_vec(22) and lru_op_vec(22)) or (lru_q(22) and not lru_op_vec(22)); +lru_d(23) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(23)='1' and lru_op_vec(23)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(23)='1' and lru_op_vec(23)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(23); +lru_eff(23) <= (lru_vp_vec(23) and lru_op_vec(23)) or (lru_q(23) and not lru_op_vec(23)); +lru_d(24) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(24)='1' and lru_op_vec(24)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(24)='1' and lru_op_vec(24)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(24); +lru_eff(24) <= (lru_vp_vec(24) and lru_op_vec(24)) or (lru_q(24) and not lru_op_vec(24)); +lru_d(25) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(25)='1' and lru_op_vec(25)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(25)='1' and lru_op_vec(25)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(25); +lru_eff(25) <= (lru_vp_vec(25) and lru_op_vec(25)) or (lru_q(25) and not lru_op_vec(25)); +lru_d(26) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(26)='1' and lru_op_vec(26)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(26)='1' and lru_op_vec(26)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(26); +lru_eff(26) <= (lru_vp_vec(26) and lru_op_vec(26)) or (lru_q(26) and not lru_op_vec(26)); +lru_d(27) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(27)='1' and lru_op_vec(27)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(27)='1' and lru_op_vec(27)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(27); +lru_eff(27) <= (lru_vp_vec(27) and lru_op_vec(27)) or (lru_q(27) and not lru_op_vec(27)); +lru_d(28) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(28)='1' and lru_op_vec(28)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(28)='1' and lru_op_vec(28)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(28); +lru_eff(28) <= (lru_vp_vec(28) and lru_op_vec(28)) or (lru_q(28) and not lru_op_vec(28)); +lru_d(29) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(29)='1' and lru_op_vec(29)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(29)='1' and lru_op_vec(29)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(29); +lru_eff(29) <= (lru_vp_vec(29) and lru_op_vec(29)) or (lru_q(29) and not lru_op_vec(29)); +lru_d(30) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(30)='1' and lru_op_vec(30)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(30)='1' and lru_op_vec(30)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(30); +lru_eff(30) <= (lru_vp_vec(30) and lru_op_vec(30)) or (lru_q(30) and not lru_op_vec(30)); +lru_d(31) <= '0' when ((ex6_deratwe_ws3='1' and mmucr1_q(0)='0') or flash_invalidate='1') + else '0' when lru_reset_vec(31)='1' and lru_op_vec(31)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else '1' when lru_set_vec(31)='1' and lru_op_vec(31)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + else lru_q(31); +lru_eff(31) <= (lru_vp_vec(31) and lru_op_vec(31)) or (lru_q(31) and not lru_op_vec(31)); +-- RMT override enable: Op= OR(all RMT entries below and left of p) XOR OR(all RMT entries below and right of p) +lru_op_vec(1) <= (lru_rmt_vec(0) or lru_rmt_vec(1) or lru_rmt_vec(2) or lru_rmt_vec(3) or + lru_rmt_vec(4) or lru_rmt_vec(5) or lru_rmt_vec(6) or lru_rmt_vec(7) or + lru_rmt_vec(8) or lru_rmt_vec(9) or lru_rmt_vec(10) or lru_rmt_vec(11) or + lru_rmt_vec(12) or lru_rmt_vec(13) or lru_rmt_vec(14) or lru_rmt_vec(15)) xor + (lru_rmt_vec(16) or lru_rmt_vec(17) or lru_rmt_vec(18) or lru_rmt_vec(19) or + lru_rmt_vec(20) or lru_rmt_vec(21) or lru_rmt_vec(22) or lru_rmt_vec(23) or + lru_rmt_vec(24) or lru_rmt_vec(25) or lru_rmt_vec(26) or lru_rmt_vec(27) or + lru_rmt_vec(28) or lru_rmt_vec(29) or lru_rmt_vec(30) or lru_rmt_vec(31)); +lru_op_vec(2) <= (lru_rmt_vec(0) or lru_rmt_vec(1) or lru_rmt_vec(2) or lru_rmt_vec(3) or + lru_rmt_vec(4) or lru_rmt_vec(5) or lru_rmt_vec(6) or lru_rmt_vec(7)) xor + (lru_rmt_vec(8) or lru_rmt_vec(9) or lru_rmt_vec(10) or lru_rmt_vec(11) or + lru_rmt_vec(12) or lru_rmt_vec(13) or lru_rmt_vec(14) or lru_rmt_vec(15)); +lru_op_vec(3) <= (lru_rmt_vec(16) or lru_rmt_vec(17) or lru_rmt_vec(18) or lru_rmt_vec(19) or + lru_rmt_vec(20) or lru_rmt_vec(21) or lru_rmt_vec(22) or lru_rmt_vec(23)) xor + (lru_rmt_vec(24) or lru_rmt_vec(25) or lru_rmt_vec(26) or lru_rmt_vec(27) or + lru_rmt_vec(28) or lru_rmt_vec(29) or lru_rmt_vec(30) or lru_rmt_vec(31)); +lru_op_vec(4) <= (lru_rmt_vec(0) or lru_rmt_vec(1) or lru_rmt_vec(2) or lru_rmt_vec(3)) xor + (lru_rmt_vec(4) or lru_rmt_vec(5) or lru_rmt_vec(6) or lru_rmt_vec(7)); +lru_op_vec(5) <= (lru_rmt_vec(8) or lru_rmt_vec(9) or lru_rmt_vec(10) or lru_rmt_vec(11)) xor + (lru_rmt_vec(12) or lru_rmt_vec(13) or lru_rmt_vec(14) or lru_rmt_vec(15)); +lru_op_vec(6) <= (lru_rmt_vec(16) or lru_rmt_vec(17) or lru_rmt_vec(18) or lru_rmt_vec(19)) xor + (lru_rmt_vec(20) or lru_rmt_vec(21) or lru_rmt_vec(22) or lru_rmt_vec(23)); +lru_op_vec(7) <= (lru_rmt_vec(24) or lru_rmt_vec(25) or lru_rmt_vec(26) or lru_rmt_vec(27)) xor + (lru_rmt_vec(28) or lru_rmt_vec(29) or lru_rmt_vec(30) or lru_rmt_vec(31)); +lru_op_vec(8) <= (lru_rmt_vec(0) or lru_rmt_vec(1)) xor (lru_rmt_vec(2) or lru_rmt_vec(3)); +lru_op_vec(9) <= (lru_rmt_vec(4) or lru_rmt_vec(5)) xor (lru_rmt_vec(6) or lru_rmt_vec(7)); +lru_op_vec(10) <= (lru_rmt_vec(8) or lru_rmt_vec(9)) xor (lru_rmt_vec(10) or lru_rmt_vec(11)); +lru_op_vec(11) <= (lru_rmt_vec(12) or lru_rmt_vec(13)) xor (lru_rmt_vec(14) or lru_rmt_vec(15)); +lru_op_vec(12) <= (lru_rmt_vec(16) or lru_rmt_vec(17)) xor (lru_rmt_vec(18) or lru_rmt_vec(19)); +lru_op_vec(13) <= (lru_rmt_vec(20) or lru_rmt_vec(21)) xor (lru_rmt_vec(22) or lru_rmt_vec(23)); +lru_op_vec(14) <= (lru_rmt_vec(24) or lru_rmt_vec(25)) xor (lru_rmt_vec(26) or lru_rmt_vec(27)); +lru_op_vec(15) <= (lru_rmt_vec(28) or lru_rmt_vec(29)) xor (lru_rmt_vec(30) or lru_rmt_vec(31)); +lru_op_vec(16) <= lru_rmt_vec(0) xor lru_rmt_vec(1); +lru_op_vec(17) <= lru_rmt_vec(2) xor lru_rmt_vec(3); +lru_op_vec(18) <= lru_rmt_vec(4) xor lru_rmt_vec(5); +lru_op_vec(19) <= lru_rmt_vec(6) xor lru_rmt_vec(7); +lru_op_vec(20) <= lru_rmt_vec(8) xor lru_rmt_vec(9); +lru_op_vec(21) <= lru_rmt_vec(10) xor lru_rmt_vec(11); +lru_op_vec(22) <= lru_rmt_vec(12) xor lru_rmt_vec(13); +lru_op_vec(23) <= lru_rmt_vec(14) xor lru_rmt_vec(15); +lru_op_vec(24) <= lru_rmt_vec(16) xor lru_rmt_vec(17); +lru_op_vec(25) <= lru_rmt_vec(18) xor lru_rmt_vec(19); +lru_op_vec(26) <= lru_rmt_vec(20) xor lru_rmt_vec(21); +lru_op_vec(27) <= lru_rmt_vec(22) xor lru_rmt_vec(23); +lru_op_vec(28) <= lru_rmt_vec(24) xor lru_rmt_vec(25); +lru_op_vec(29) <= lru_rmt_vec(26) xor lru_rmt_vec(27); +lru_op_vec(30) <= lru_rmt_vec(28) xor lru_rmt_vec(29); +lru_op_vec(31) <= lru_rmt_vec(30) xor lru_rmt_vec(31); +-- RMT override value: Vp= OR(all RMT entries below and right of p) +lru_vp_vec(1) <= (lru_rmt_vec(16) or lru_rmt_vec(17) or lru_rmt_vec(18) or lru_rmt_vec(19) or + lru_rmt_vec(20) or lru_rmt_vec(21) or lru_rmt_vec(22) or lru_rmt_vec(23) or + lru_rmt_vec(24) or lru_rmt_vec(25) or lru_rmt_vec(26) or lru_rmt_vec(27) or + lru_rmt_vec(28) or lru_rmt_vec(29) or lru_rmt_vec(30) or lru_rmt_vec(31)); +lru_vp_vec(2) <= (lru_rmt_vec(8) or lru_rmt_vec(9) or lru_rmt_vec(10) or lru_rmt_vec(11) or + lru_rmt_vec(12) or lru_rmt_vec(13) or lru_rmt_vec(14) or lru_rmt_vec(15)); +lru_vp_vec(3) <= (lru_rmt_vec(24) or lru_rmt_vec(25) or lru_rmt_vec(26) or lru_rmt_vec(27) or + lru_rmt_vec(28) or lru_rmt_vec(29) or lru_rmt_vec(30) or lru_rmt_vec(31)); +lru_vp_vec(4) <= (lru_rmt_vec(4) or lru_rmt_vec(5) or lru_rmt_vec(6) or lru_rmt_vec(7)); +lru_vp_vec(5) <= (lru_rmt_vec(12) or lru_rmt_vec(13) or lru_rmt_vec(14) or lru_rmt_vec(15)); +lru_vp_vec(6) <= (lru_rmt_vec(20) or lru_rmt_vec(21) or lru_rmt_vec(22) or lru_rmt_vec(23)); +lru_vp_vec(7) <= (lru_rmt_vec(28) or lru_rmt_vec(29) or lru_rmt_vec(30) or lru_rmt_vec(31)); +lru_vp_vec(8) <= (lru_rmt_vec(2) or lru_rmt_vec(3)); +lru_vp_vec(9) <= (lru_rmt_vec(6) or lru_rmt_vec(7)); +lru_vp_vec(10) <= (lru_rmt_vec(10) or lru_rmt_vec(11)); +lru_vp_vec(11) <= (lru_rmt_vec(14) or lru_rmt_vec(15)); +lru_vp_vec(12) <= (lru_rmt_vec(18) or lru_rmt_vec(19)); +lru_vp_vec(13) <= (lru_rmt_vec(22) or lru_rmt_vec(23)); +lru_vp_vec(14) <= (lru_rmt_vec(26) or lru_rmt_vec(27)); +lru_vp_vec(15) <= (lru_rmt_vec(30) or lru_rmt_vec(31)); +lru_vp_vec(16) <= lru_rmt_vec(1); +lru_vp_vec(17) <= lru_rmt_vec(3); +lru_vp_vec(18) <= lru_rmt_vec(5); +lru_vp_vec(19) <= lru_rmt_vec(7); +lru_vp_vec(20) <= lru_rmt_vec(9); +lru_vp_vec(21) <= lru_rmt_vec(11); +lru_vp_vec(22) <= lru_rmt_vec(13); +lru_vp_vec(23) <= lru_rmt_vec(15); +lru_vp_vec(24) <= lru_rmt_vec(17); +lru_vp_vec(25) <= lru_rmt_vec(19); +lru_vp_vec(26) <= lru_rmt_vec(21); +lru_vp_vec(27) <= lru_rmt_vec(23); +lru_vp_vec(28) <= lru_rmt_vec(25); +lru_vp_vec(29) <= lru_rmt_vec(27); +lru_vp_vec(30) <= lru_rmt_vec(29); +lru_vp_vec(31) <= lru_rmt_vec(31); +-- mmucr1_q: 0-DRRE, 1-REE, 2-CEE, 3-csync, 4-isync, 5:6-DPEI, 7:8-DCTID/DTTID, 9-DCCD +-- Encoder for the LRU watermark psuedo-RMT +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +--?TABLE lru_rmt_vec LISTING(final) OPTIMIZE PARMS(ON-SET, OFF-SET); +--*INPUTS*===================*OUTPUTS*============================* +--| | | +--| mmucr1_q | lru_rmt_vec | +--| | watermark_q | | | +--| | | | | | +--| | | | | | +--| | | | | 1111111111222222222233 | +--| 012345678 01234 | 01234567890123456789012345678901 | +--*TYPE*=====================+====================================+ +--| PPPPPPPPP PPPPP | PPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPP | +--*OPTIMIZE*---------------->| AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA | +--*TERMS*====================+====================================+ +--| 1-------- ----- | 11111111111111111111111111111111 | round-robin enabled +--| 0-------- 00000 | 10000000000000000000000000000000 | +--| 0-------- 00001 | 11000000000000000000000000000000 | +--| 0-------- 00010 | 11100000000000000000000000000000 | +--| 0-------- 00011 | 11110000000000000000000000000000 | +--| 0-------- 00100 | 11111000000000000000000000000000 | +--| 0-------- 00101 | 11111100000000000000000000000000 | +--| 0-------- 00110 | 11111110000000000000000000000000 | +--| 0-------- 00111 | 11111111000000000000000000000000 | +--| 0-------- 01000 | 11111111100000000000000000000000 | +--| 0-------- 01001 | 11111111110000000000000000000000 | +--| 0-------- 01010 | 11111111111000000000000000000000 | +--| 0-------- 01011 | 11111111111100000000000000000000 | +--| 0-------- 01100 | 11111111111110000000000000000000 | +--| 0-------- 01101 | 11111111111111000000000000000000 | +--| 0-------- 01110 | 11111111111111100000000000000000 | +--| 0-------- 01111 | 11111111111111110000000000000000 | +--| 0-------- 10000 | 11111111111111111000000000000000 | +--| 0-------- 10001 | 11111111111111111100000000000000 | +--| 0-------- 10010 | 11111111111111111110000000000000 | +--| 0-------- 10011 | 11111111111111111111000000000000 | +--| 0-------- 10100 | 11111111111111111111100000000000 | +--| 0-------- 10101 | 11111111111111111111110000000000 | +--| 0-------- 10110 | 11111111111111111111111000000000 | +--| 0-------- 10111 | 11111111111111111111111100000000 | +--| 0-------- 11000 | 11111111111111111111111110000000 | +--| 0-------- 11001 | 11111111111111111111111111000000 | +--| 0-------- 11010 | 11111111111111111111111111100000 | +--| 0-------- 11011 | 11111111111111111111111111110000 | +--| 0-------- 11100 | 11111111111111111111111111111000 | +--| 0-------- 11101 | 11111111111111111111111111111100 | +--| 0-------- 11110 | 11111111111111111111111111111110 | +--| 0-------- 11111 | 11111111111111111111111111111111 | +--*END*======================+====================================+ +--?TABLE END lru_rmt_vec; +--?TABLE lru_watermark_mask LISTING(final) OPTIMIZE PARMS(ON-SET, OFF-SET); +--*INPUTS*===================*OUTPUTS*============================* +--| | | +--| mmucr1_q | lru_watermark_mask | +--| | watermark_q | | | +--| | | | | | +--| | | | | | +--| | | | | 1111111111222222222233 | +--| 012345678 01234 | 01234567890123456789012345678901 | +--*TYPE*=====================+====================================+ +--| PPPPPPPPP PPPPP | PPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPP | +--*OPTIMIZE*---------------->| AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA | +--*TERMS*====================+====================================+ +--| --------- 00000 | 01111111111111111111111111111111 | +--| --------- 00001 | 00111111111111111111111111111111 | +--| --------- 00010 | 00011111111111111111111111111111 | +--| --------- 00011 | 00001111111111111111111111111111 | +--| --------- 00100 | 00000111111111111111111111111111 | +--| --------- 00101 | 00000011111111111111111111111111 | +--| --------- 00110 | 00000001111111111111111111111111 | +--| --------- 00111 | 00000000111111111111111111111111 | +--| --------- 01000 | 00000000011111111111111111111111 | +--| --------- 01001 | 00000000001111111111111111111111 | +--| --------- 01010 | 00000000000111111111111111111111 | +--| --------- 01011 | 00000000000011111111111111111111 | +--| --------- 01100 | 00000000000001111111111111111111 | +--| --------- 01101 | 00000000000000111111111111111111 | +--| --------- 01110 | 00000000000000011111111111111111 | +--| --------- 01111 | 00000000000000001111111111111111 | +--| --------- 10000 | 00000000000000000111111111111111 | +--| --------- 10001 | 00000000000000000011111111111111 | +--| --------- 10010 | 00000000000000000001111111111111 | +--| --------- 10011 | 00000000000000000000111111111111 | +--| --------- 10100 | 00000000000000000000011111111111 | +--| --------- 10101 | 00000000000000000000001111111111 | +--| --------- 10110 | 00000000000000000000000111111111 | +--| --------- 10111 | 00000000000000000000000011111111 | +--| --------- 11000 | 00000000000000000000000001111111 | +--| --------- 11001 | 00000000000000000000000000111111 | +--| --------- 11010 | 00000000000000000000000000011111 | +--| --------- 11011 | 00000000000000000000000000001111 | +--| --------- 11100 | 00000000000000000000000000000111 | +--| --------- 11101 | 00000000000000000000000000000011 | +--| --------- 11110 | 00000000000000000000000000000001 | +--| --------- 11111 | 00000000000000000000000000000000 | +--*END*======================+====================================+ +--?TABLE END lru_watermark_mask; +-- +-- Final Table Listing +-- *INPUTS*=========*OUTPUTS*============================* +-- | | | +-- | | lru_rmt_vec_d | +-- | watermark_d | | | +-- | | | | | +-- | | | | | +-- | | | | 1111111111222222222233 | +-- | 01234 | 01234567890123456789012345678901 | +-- *TYPE*===========+====================================+ +-- | PPPPP | PPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPP | +-- *POLARITY*------>| ++++++++++++++++++++++++++++++++ | +-- *PHASE*--------->| TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT | +-- *OPTIMIZE*------>| AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA | +-- *TERMS*==========+====================================+ +-- 1 | 11111 | ...............................1 | +-- 2 | -1111 | ...............1................ | +-- 3 | 1-111 | .......................1........ | +-- 4 | --111 | .......1........................ | +-- 5 | 11-11 | ...........................1.... | +-- 6 | -1-11 | ...........1.................... | +-- 7 | 1--11 | ...................1............ | +-- 8 | ---11 | ...1............................ | +-- 9 | 111-1 | .............................1.. | +-- 10 | -11-1 | .............1.................. | +-- 11 | 1-1-1 | .....................1.......... | +-- 12 | --1-1 | .....1.......................... | +-- 13 | 11--1 | .........................1...... | +-- 14 | -1--1 | .........1...................... | +-- 15 | 1---1 | .................1.............. | +-- 16 | ----1 | .1.............................. | +-- 17 | 1111- | .............................11. | +-- 18 | -111- | .............11................. | +-- 19 | 1-11- | .....................11......... | +-- 20 | --11- | .....11......................... | +-- 21 | 11-1- | .........................11..... | +-- 22 | -1-1- | .........11..................... | +-- 23 | 1--1- | .................11............. | +-- 24 | ---1- | .11............................. | +-- 25 | 111-- | .........................1111... | +-- 26 | -11-- | .........1111................... | +-- 27 | 1-1-- | .................1111........... | +-- 28 | --1-- | .1111........................... | +-- 29 | 11--- | .................11111111....... | +-- 30 | -1--- | .11111111....................... | +-- 31 | 1---- | .1111111111111111............... | +-- 32 | ----- | 1............................... | +-- *=====================================================* +-- +-- Table LRU_RMT_VEC_D Signal Assignments for Product Terms +MQQ70:LRU_RMT_VEC_D_PT(1) <= + Eq(( WATERMARK_D(0) & WATERMARK_D(1) & + WATERMARK_D(2) & WATERMARK_D(3) & + WATERMARK_D(4) ) , STD_ULOGIC_VECTOR'("11111")); +MQQ71:LRU_RMT_VEC_D_PT(2) <= + Eq(( WATERMARK_D(1) & WATERMARK_D(2) & + WATERMARK_D(3) & WATERMARK_D(4) + ) , STD_ULOGIC_VECTOR'("1111")); +MQQ72:LRU_RMT_VEC_D_PT(3) <= + Eq(( WATERMARK_D(0) & WATERMARK_D(2) & + WATERMARK_D(3) & WATERMARK_D(4) + ) , STD_ULOGIC_VECTOR'("1111")); +MQQ73:LRU_RMT_VEC_D_PT(4) <= + Eq(( WATERMARK_D(2) & WATERMARK_D(3) & + WATERMARK_D(4) ) , STD_ULOGIC_VECTOR'("111")); +MQQ74:LRU_RMT_VEC_D_PT(5) <= + Eq(( WATERMARK_D(0) & WATERMARK_D(1) & + WATERMARK_D(3) & WATERMARK_D(4) + ) , STD_ULOGIC_VECTOR'("1111")); +MQQ75:LRU_RMT_VEC_D_PT(6) <= + Eq(( WATERMARK_D(1) & WATERMARK_D(3) & + WATERMARK_D(4) ) , STD_ULOGIC_VECTOR'("111")); +MQQ76:LRU_RMT_VEC_D_PT(7) <= + Eq(( WATERMARK_D(0) & WATERMARK_D(3) & + WATERMARK_D(4) ) , STD_ULOGIC_VECTOR'("111")); +MQQ77:LRU_RMT_VEC_D_PT(8) <= + Eq(( WATERMARK_D(3) & WATERMARK_D(4) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ78:LRU_RMT_VEC_D_PT(9) <= + Eq(( WATERMARK_D(0) & WATERMARK_D(1) & + WATERMARK_D(2) & WATERMARK_D(4) + ) , STD_ULOGIC_VECTOR'("1111")); +MQQ79:LRU_RMT_VEC_D_PT(10) <= + Eq(( WATERMARK_D(1) & WATERMARK_D(2) & + WATERMARK_D(4) ) , STD_ULOGIC_VECTOR'("111")); +MQQ80:LRU_RMT_VEC_D_PT(11) <= + Eq(( WATERMARK_D(0) & WATERMARK_D(2) & + WATERMARK_D(4) ) , STD_ULOGIC_VECTOR'("111")); +MQQ81:LRU_RMT_VEC_D_PT(12) <= + Eq(( WATERMARK_D(2) & WATERMARK_D(4) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ82:LRU_RMT_VEC_D_PT(13) <= + Eq(( WATERMARK_D(0) & WATERMARK_D(1) & + WATERMARK_D(4) ) , STD_ULOGIC_VECTOR'("111")); +MQQ83:LRU_RMT_VEC_D_PT(14) <= + Eq(( WATERMARK_D(1) & WATERMARK_D(4) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ84:LRU_RMT_VEC_D_PT(15) <= + Eq(( WATERMARK_D(0) & WATERMARK_D(4) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ85:LRU_RMT_VEC_D_PT(16) <= + Eq(( WATERMARK_D(4) ) , STD_ULOGIC'('1')); +MQQ86:LRU_RMT_VEC_D_PT(17) <= + Eq(( WATERMARK_D(0) & WATERMARK_D(1) & + WATERMARK_D(2) & WATERMARK_D(3) + ) , STD_ULOGIC_VECTOR'("1111")); +MQQ87:LRU_RMT_VEC_D_PT(18) <= + Eq(( WATERMARK_D(1) & WATERMARK_D(2) & + WATERMARK_D(3) ) , STD_ULOGIC_VECTOR'("111")); +MQQ88:LRU_RMT_VEC_D_PT(19) <= + Eq(( WATERMARK_D(0) & WATERMARK_D(2) & + WATERMARK_D(3) ) , STD_ULOGIC_VECTOR'("111")); +MQQ89:LRU_RMT_VEC_D_PT(20) <= + Eq(( WATERMARK_D(2) & WATERMARK_D(3) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ90:LRU_RMT_VEC_D_PT(21) <= + Eq(( WATERMARK_D(0) & WATERMARK_D(1) & + WATERMARK_D(3) ) , STD_ULOGIC_VECTOR'("111")); +MQQ91:LRU_RMT_VEC_D_PT(22) <= + Eq(( WATERMARK_D(1) & WATERMARK_D(3) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ92:LRU_RMT_VEC_D_PT(23) <= + Eq(( WATERMARK_D(0) & WATERMARK_D(3) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ93:LRU_RMT_VEC_D_PT(24) <= + Eq(( WATERMARK_D(3) ) , STD_ULOGIC'('1')); +MQQ94:LRU_RMT_VEC_D_PT(25) <= + Eq(( WATERMARK_D(0) & WATERMARK_D(1) & + WATERMARK_D(2) ) , STD_ULOGIC_VECTOR'("111")); +MQQ95:LRU_RMT_VEC_D_PT(26) <= + Eq(( WATERMARK_D(1) & WATERMARK_D(2) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ96:LRU_RMT_VEC_D_PT(27) <= + Eq(( WATERMARK_D(0) & WATERMARK_D(2) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ97:LRU_RMT_VEC_D_PT(28) <= + Eq(( WATERMARK_D(2) ) , STD_ULOGIC'('1')); +MQQ98:LRU_RMT_VEC_D_PT(29) <= + Eq(( WATERMARK_D(0) & WATERMARK_D(1) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ99:LRU_RMT_VEC_D_PT(30) <= + Eq(( WATERMARK_D(1) ) , STD_ULOGIC'('1')); +MQQ100:LRU_RMT_VEC_D_PT(31) <= + Eq(( WATERMARK_D(0) ) , STD_ULOGIC'('1')); +MQQ101:LRU_RMT_VEC_D_PT(32) <= + '1'; +-- Table LRU_RMT_VEC_D Signal Assignments for Outputs +MQQ102:LRU_RMT_VEC_D(0) <= + (LRU_RMT_VEC_D_PT(32)); +MQQ103:LRU_RMT_VEC_D(1) <= + (LRU_RMT_VEC_D_PT(16) OR LRU_RMT_VEC_D_PT(24) + OR LRU_RMT_VEC_D_PT(28) OR LRU_RMT_VEC_D_PT(30) + OR LRU_RMT_VEC_D_PT(31)); +MQQ104:LRU_RMT_VEC_D(2) <= + (LRU_RMT_VEC_D_PT(24) OR LRU_RMT_VEC_D_PT(28) + OR LRU_RMT_VEC_D_PT(30) OR LRU_RMT_VEC_D_PT(31) + ); +MQQ105:LRU_RMT_VEC_D(3) <= + (LRU_RMT_VEC_D_PT(8) OR LRU_RMT_VEC_D_PT(28) + OR LRU_RMT_VEC_D_PT(30) OR LRU_RMT_VEC_D_PT(31) + ); +MQQ106:LRU_RMT_VEC_D(4) <= + (LRU_RMT_VEC_D_PT(28) OR LRU_RMT_VEC_D_PT(30) + OR LRU_RMT_VEC_D_PT(31)); +MQQ107:LRU_RMT_VEC_D(5) <= + (LRU_RMT_VEC_D_PT(12) OR LRU_RMT_VEC_D_PT(20) + OR LRU_RMT_VEC_D_PT(30) OR LRU_RMT_VEC_D_PT(31) + ); +MQQ108:LRU_RMT_VEC_D(6) <= + (LRU_RMT_VEC_D_PT(20) OR LRU_RMT_VEC_D_PT(30) + OR LRU_RMT_VEC_D_PT(31)); +MQQ109:LRU_RMT_VEC_D(7) <= + (LRU_RMT_VEC_D_PT(4) OR LRU_RMT_VEC_D_PT(30) + OR LRU_RMT_VEC_D_PT(31)); +MQQ110:LRU_RMT_VEC_D(8) <= + (LRU_RMT_VEC_D_PT(30) OR LRU_RMT_VEC_D_PT(31) + ); +MQQ111:LRU_RMT_VEC_D(9) <= + (LRU_RMT_VEC_D_PT(14) OR LRU_RMT_VEC_D_PT(22) + OR LRU_RMT_VEC_D_PT(26) OR LRU_RMT_VEC_D_PT(31) + ); +MQQ112:LRU_RMT_VEC_D(10) <= + (LRU_RMT_VEC_D_PT(22) OR LRU_RMT_VEC_D_PT(26) + OR LRU_RMT_VEC_D_PT(31)); +MQQ113:LRU_RMT_VEC_D(11) <= + (LRU_RMT_VEC_D_PT(6) OR LRU_RMT_VEC_D_PT(26) + OR LRU_RMT_VEC_D_PT(31)); +MQQ114:LRU_RMT_VEC_D(12) <= + (LRU_RMT_VEC_D_PT(26) OR LRU_RMT_VEC_D_PT(31) + ); +MQQ115:LRU_RMT_VEC_D(13) <= + (LRU_RMT_VEC_D_PT(10) OR LRU_RMT_VEC_D_PT(18) + OR LRU_RMT_VEC_D_PT(31)); +MQQ116:LRU_RMT_VEC_D(14) <= + (LRU_RMT_VEC_D_PT(18) OR LRU_RMT_VEC_D_PT(31) + ); +MQQ117:LRU_RMT_VEC_D(15) <= + (LRU_RMT_VEC_D_PT(2) OR LRU_RMT_VEC_D_PT(31) + ); +MQQ118:LRU_RMT_VEC_D(16) <= + (LRU_RMT_VEC_D_PT(31)); +MQQ119:LRU_RMT_VEC_D(17) <= + (LRU_RMT_VEC_D_PT(15) OR LRU_RMT_VEC_D_PT(23) + OR LRU_RMT_VEC_D_PT(27) OR LRU_RMT_VEC_D_PT(29) + ); +MQQ120:LRU_RMT_VEC_D(18) <= + (LRU_RMT_VEC_D_PT(23) OR LRU_RMT_VEC_D_PT(27) + OR LRU_RMT_VEC_D_PT(29)); +MQQ121:LRU_RMT_VEC_D(19) <= + (LRU_RMT_VEC_D_PT(7) OR LRU_RMT_VEC_D_PT(27) + OR LRU_RMT_VEC_D_PT(29)); +MQQ122:LRU_RMT_VEC_D(20) <= + (LRU_RMT_VEC_D_PT(27) OR LRU_RMT_VEC_D_PT(29) + ); +MQQ123:LRU_RMT_VEC_D(21) <= + (LRU_RMT_VEC_D_PT(11) OR LRU_RMT_VEC_D_PT(19) + OR LRU_RMT_VEC_D_PT(29)); +MQQ124:LRU_RMT_VEC_D(22) <= + (LRU_RMT_VEC_D_PT(19) OR LRU_RMT_VEC_D_PT(29) + ); +MQQ125:LRU_RMT_VEC_D(23) <= + (LRU_RMT_VEC_D_PT(3) OR LRU_RMT_VEC_D_PT(29) + ); +MQQ126:LRU_RMT_VEC_D(24) <= + (LRU_RMT_VEC_D_PT(29)); +MQQ127:LRU_RMT_VEC_D(25) <= + (LRU_RMT_VEC_D_PT(13) OR LRU_RMT_VEC_D_PT(21) + OR LRU_RMT_VEC_D_PT(25)); +MQQ128:LRU_RMT_VEC_D(26) <= + (LRU_RMT_VEC_D_PT(21) OR LRU_RMT_VEC_D_PT(25) + ); +MQQ129:LRU_RMT_VEC_D(27) <= + (LRU_RMT_VEC_D_PT(5) OR LRU_RMT_VEC_D_PT(25) + ); +MQQ130:LRU_RMT_VEC_D(28) <= + (LRU_RMT_VEC_D_PT(25)); +MQQ131:LRU_RMT_VEC_D(29) <= + (LRU_RMT_VEC_D_PT(9) OR LRU_RMT_VEC_D_PT(17) + ); +MQQ132:LRU_RMT_VEC_D(30) <= + (LRU_RMT_VEC_D_PT(17)); +MQQ133:LRU_RMT_VEC_D(31) <= + (LRU_RMT_VEC_D_PT(1)); + +mmucr1_b0_cpy_d <= mmucr1_d(0); +lru_rmt_vec <= lru_rmt_vec_q; +lru_watermark_mask <= not lru_rmt_vec_q; +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +entry_valid_watermarked <= entry_valid_q or lru_watermark_mask; +-- lru_update_event +-- 0: tlb reload +-- 1: invalidate snoop +-- 2: csync or isync enabled +-- 3: eratwe WS=0 +-- 4: load or store hit +-- 5: cam write type events +-- 6: cam invalidate type events +-- 7: cam translation type events +-- 8: superset, ex2 +-- 9: superset, delayed to ex3 +-- logic for the LRU reset and set bit vectors +-- ?TABLE lru_set_reset_vec LISTING(final) OPTIMIZE PARMS(ON-SET, OFF-SET); +-- +-- Final Table Listing +-- *INPUTS*========================================================================================================*OUTPUTS*=============================================================* +-- | | | +-- | lru_update_event_q | lru_reset_vec | +-- | | entry_valid_watermarked | | lru_set_vec | +-- | | | lru_q | | | | +-- | | | | entry_match_q | | | | +-- | | | | | | | | | +-- | | | | | | | | | +-- | | | 1111111111222222222233 | 1111111111222222222233 | 1111111111222222222233 | | 1111111111222222222233 | 1111111111222222222233 | +-- | 012345678 01234567890123456789012345678901 1234567890123456789012345678901 01234567890123456789012345678901 | 1234567890123456789012345678901 1234567890123456789012345678901 | +-- *TYPE*==========================================================================================================+=====================================================================+ +-- | PPPPPPPPP PPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPP PPPPPPPPPPPPPPPPPPPPPPPPPPPPPPP PPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPP | PPPPPPPPPPPPPPPPPPPPPPPPPPPPPPP PPPPPPPPPPPPPPPPPPPPPPPPPPPPPPP | +-- *POLARITY*----------------------------------------------------------------------------------------------------->| +++++++++++++++++++++++++++++++ +++++++++++++++++++++++++++++++ | +-- *PHASE*-------------------------------------------------------------------------------------------------------->| TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT | +-- *OPTIMIZE*----------------------------------------------------------------------------------------------------->| AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB | +-- *TERMS*=========================================================================================================+=====================================================================+ +-- 1 | -----001- 11111111111111111111111111111111 ------------------------------- 00000000000000000000000000000001 | 1.1...1.......1...............1 ............................... | +-- 2 | -----001- 11111111111111111111111111111111 ------------------------------- 0000000000000000000000000000001- | 1.1...1.......1................ ............................... | +-- 3 | -----001- 1111111111111111111111111111111- ------------------------------- 0000000000000000000000000000001- | ............................... ..............................1 | +-- 4 | -----001- 11111111111111111111111111111111 ------------------------------- 000000000000000000000000000001-- | 1.1...1......................1. ............................... | +-- 5 | -----001- 111111111111111111111111111111-- ------------------------------- 0000000000000000000000000000-1-- | ............................... ..............1................ | +-- 6 | -----001- 11111111111111111111111111111111 ------------------------------- 00000000000000000000000000001--- | 1.1...1........................ ..............1..............1. | +-- 7 | -----001- 11111111111111111111111111111111 ------------------------------- 0000000000000000000000000001---- | 1.1..........1..............1.. ............................... | +-- 8 | -----001- 1111111111111111111111111111---- ------------------------------- 000000000000000000000000---1---- | ............................... ......1........................ | +-- 9 | -----001- 11111111111111111111111111111111 ------------------------------- 000000000000000000000000001----- | 1.1..........1................. ......1.....................1.. | +-- 10 | -----001- 11111111111111111111111111111111 ------------------------------- 00000000000000000000000001------ | 1.1........................1... ............................... | +-- 11 | -----001- 11111111111111111111111111111111 ------------------------------- 000000000000000000000000-1------ | ............................... ......1......1................. | +-- 12 | -----001- 11111111111111111111111111111111 ------------------------------- 0000000000000000000000001------- | 1.1............................ ......1......1.............1... | +-- 13 | -----001- 11111111111111111111111111111111 ------------------------------- 000000000000000000000001-------- | 1....1......1.............1.... ............................... | +-- 14 | -----001- 111111111111111111111111-------- ------------------------------- 0000000000000000-------1-------- | ............................... ..1............................ | +-- 15 | -----001- 11111111111111111111111111111111 ------------------------------- 00000000000000000000001--------- | 1....1......1.................. ..1.......................1.... | +-- 16 | -----001- 11111111111111111111111111111111 ------------------------------- 0000000000000000000001---------- | 1....1...................1..... ............................... | +-- 17 | -----001- 11111111111111111111111111111111 ------------------------------- 00000000000000000000-1---------- | ............................... ..1.........1.................. | +-- 18 | -----001- 11111111111111111111111111111111 ------------------------------- 000000000000000000001----------- | 1....1......................... ..1.........1............1..... | +-- 19 | -----001- 11111111111111111111111111111111 ------------------------------- 00000000000000000001------------ | 1..........1............1...... ............................... | +-- 20 | -----001- 11111111111111111111111111111111 ------------------------------- 0000000000000000---1------------ | ............................... ..1..1......................... | +-- 21 | -----001- 11111111111111111111111111111111 ------------------------------- 0000000000000000001------------- | 1..........1................... ..1..1..................1...... | +-- 22 | -----001- 11111111111111111111111111111111 ------------------------------- 000000000000000001-------------- | 1......................1....... ............................... | +-- 23 | -----001- 11111111111111111111111111111111 ------------------------------- 0000000000000000-1-------------- | ............................... ..1..1.....1................... | +-- 24 | -----001- 11111111111111111111111111111111 ------------------------------- 00000000000000001--------------- | ............................... ..1..1.....1...........1....... | +-- 25 | -----001- ----------------1111111111111111 ------------------------------- 00000000000000001--------------- | 1.............................. ............................... | +-- 26 | -----001- 11111111111111111111111111111111 ------------------------------- 0000000000000001---------------- | .1..1.....1...........1........ ............................... | +-- 27 | -----001- 1111111111111111---------------- ------------------------------- ---------------1---------------- | ............................... 1.............................. | +-- 28 | -----001- 11111111111111111111111111111111 ------------------------------- 000000000000001----------------- | .1..1.....1.................... 1.....................1........ | +-- 29 | -----001- 11111111111111111111111111111111 ------------------------------- 00000000000001------------------ | .1..1................1......... ............................... | +-- 30 | -----001- 11111111111111111111111111111111 ------------------------------- 000000000000-1------------------ | ............................... 1.........1.................... | +-- 31 | -----001- 11111111111111111111111111111111 ------------------------------- 0000000000001------------------- | .1..1.......................... 1.........1..........1......... | +-- 32 | -----001- 11111111111111111111111111111111 ------------------------------- 000000000001-------------------- | .1.......1..........1.......... ............................... | +-- 33 | -----001- 11111111111111111111111111111111 ------------------------------- 00000000---1-------------------- | ............................... 1...1.......................... | +-- 34 | -----001- 11111111111111111111111111111111 ------------------------------- 00000000001--------------------- | .1.......1..................... 1...1...............1.......... | +-- 35 | -----001- 11111111111111111111111111111111 ------------------------------- 0000000001---------------------- | .1.................1........... ............................... | +-- 36 | -----001- 11111111111111111111111111111111 ------------------------------- 00000000-1---------------------- | ............................... 1...1....1..................... | +-- 37 | -----001- 11111111111111111111111111111111 ------------------------------- 000000001----------------------- | ............................... 1...1....1.........1........... | +-- 38 | -----001- --------111111111111111111111111 ------------------------------- 000000001----------------------- | .1............................. ............................... | +-- 39 | -----001- 11111111111111111111111111111111 ------------------------------- 00000001------------------------ | ...1....1.........1............ ............................... | +-- 40 | -----001- 11111111111111111111111111111111 ------------------------------- -------1------------------------ | ............................... 11............................. | +-- 41 | -----001- 11111111111111111111111111111111 ------------------------------- 0000001------------------------- | ...1....1...................... 11................1............ | +-- 42 | -----001- 11111111111111111111111111111111 ------------------------------- 000001-------------------------- | ...1.............1............. ............................... | +-- 43 | -----001- 11111111111111111111111111111111 ------------------------------- 0000-1-------------------------- | ............................... 11......1...................... | +-- 44 | -----001- 11111111111111111111111111111111 ------------------------------- 00001--------------------------- | ............................... 11......1........1............. | +-- 45 | -----001- ----1111111111111111111111111111 ------------------------------- 00001--------------------------- | ...1........................... ............................... | +-- 46 | -----001- 11111111111111111111111111111111 ------------------------------- 0001---------------------------- | .......1........1.............. ............................... | +-- 47 | -----001- 11111111111111111111111111111111 ------------------------------- ---1---------------------------- | ............................... 11.1........................... | +-- 48 | -----001- 11111111111111111111111111111111 ------------------------------- 001----------------------------- | ............................... 11.1............1.............. | +-- 49 | -----001- --111111111111111111111111111111 ------------------------------- 001----------------------------- | .......1....................... ............................... | +-- 50 | -----001- -1111111111111111111111111111111 ------------------------------- 01------------------------------ | ...............1............... ............................... | +-- 51 | -----001- 11111111111111111111111111111111 ------------------------------- -1------------------------------ | ............................... 11.1...1....................... | +-- 52 | -----001- 11111111111111111111111111111111 ------------------------------- 1------------------------------- | ............................... 11.1...1.......1............... | +-- 53 | -----1--- 1111111111111111111111111111111- 1-1---1-------1---------------0 -------------------------------- | ............................... ..............................1 | +-- 54 | -----1--- 111111111111111111111111111111-1 1-1---1-------1---------------1 -------------------------------- | ..............................1 ............................... | +-- 55 | -----1--- 11111111111111111111111111111-11 1-1---1-------0--------------0- -------------------------------- | ............................... .............................1. | +-- 56 | -----1--- 1111111111111111111111111111-111 1-1---1-------0--------------1- -------------------------------- | .............................1. ............................... | +-- 57 | -----1--- 111111111111111111111111111-1111 1-1---0------1--------------0-- -------------------------------- | ............................... ............................1.. | +-- 58 | -----1--- 11111111111111111111111111-11111 1-1---0------1--------------1-- -------------------------------- | ............................1.. ............................... | +-- 59 | -----1--- 1111111111111111111111111-111111 1-1---0------0-------------0--- -------------------------------- | ............................... ...........................1... | +-- 60 | -----1--- 111111111111111111111111-1111111 1-1---0------0-------------1--- -------------------------------- | ...........................1... ............................... | +-- 61 | -----1--- 11111111111111111111111-11111111 1-0--1------1-------------0---- -------------------------------- | ............................... ..........................1.... | +-- 62 | -----1--- 1111111111111111111111-111111111 1-0--1------1-------------1---- -------------------------------- | ..........................1.... ............................... | +-- 63 | -----1--- 111111111111111111111-1111111111 1-0--1------0------------0----- -------------------------------- | ............................... .........................1..... | +-- 64 | -----1--- 11111111111111111111-11111111111 1-0--1------0------------1----- -------------------------------- | .........................1..... ............................... | +-- 65 | -----1--- 1111111111111111111-111111111111 1-0--0-----1------------0------ -------------------------------- | ............................... ........................1...... | +-- 66 | -----1--- 111111111111111111-1111111111111 1-0--0-----1------------1------ -------------------------------- | ........................1...... ............................... | +-- 67 | -----1--- 11111111111111111-11111111111111 1-0--0-----0-----------0------- -------------------------------- | ............................... .......................1....... | +-- 68 | -----1--- 1111111111111111-111111111111111 1-0--0-----0-----------1------- -------------------------------- | .......................1....... ............................... | +-- 69 | -----1--- 111111111111111-1111111111111111 01--1-----1-----------0-------- -------------------------------- | ............................... ......................1........ | +-- 70 | -----1--- 11111111111111-11111111111111111 01--1-----1-----------1-------- -------------------------------- | ......................1........ ............................... | +-- 71 | -----1--- 1111111111111-111111111111111111 01--1-----0----------0--------- -------------------------------- | ............................... .....................1......... | +-- 72 | -----1--- 111111111111-1111111111111111111 01--1-----0----------1--------- -------------------------------- | .....................1......... ............................... | +-- 73 | -----1--- 11111111111-11111111111111111111 01--0----1----------0---------- -------------------------------- | ............................... ....................1.......... | +-- 74 | -----1--- 1111111111-111111111111111111111 01--0----1----------1---------- -------------------------------- | ....................1.......... ............................... | +-- 75 | -----1--- 111111111-1111111111111111111111 01--0----0---------0----------- -------------------------------- | ............................... ...................1........... | +-- 76 | -----1--- 11111111-11111111111111111111111 01--0----0---------1----------- -------------------------------- | ...................1........... ............................... | +-- 77 | -----1--- 1111111-111111111111111111111111 00-1----1---------0------------ -------------------------------- | ............................... ..................1............ | +-- 78 | -----1--- 111111-1111111111111111111111111 00-1----1---------1------------ -------------------------------- | ..................1............ ............................... | +-- 79 | -----1--- 11111-11111111111111111111111111 00-1----0--------0------------- -------------------------------- | ............................... .................1............. | +-- 80 | -----1--- 1111-111111111111111111111111111 00-1----0--------1------------- -------------------------------- | .................1............. ............................... | +-- 81 | -----1--- 111-1111111111111111111111111111 00-0---1--------0-------------- -------------------------------- | ............................... ................1.............. | +-- 82 | -----1--- 11-11111111111111111111111111111 00-0---1--------1-------------- -------------------------------- | ................1.............. ............................... | +-- 83 | -----1--- 1-111111111111111111111111111111 00-0---0-------0--------------- -------------------------------- | ............................... ...............1............... | +-- 84 | -----1--- -1111111111111111111111111111111 00-0---0-------1--------------- -------------------------------- | ...............1............... ............................... | +-- 85 | -----1--- 111111111111111111111111111111-- 1-1---1-------0---------------- -------------------------------- | ............................... ..............1................ | +-- 86 | -----1--- 1111111111111111111111111111--11 1-1---1-------1---------------- -------------------------------- | ..............1................ ............................... | +-- 87 | -----1--- 11111111111111111111111111--1111 1-1---0------0----------------- -------------------------------- | ............................... .............1................. | +-- 88 | -----1--- 111111111111111111111111--111111 1-1---0------1----------------- -------------------------------- | .............1................. ............................... | +-- 89 | -----1--- 1111111111111111111111--11111111 1-0--1------0------------------ -------------------------------- | ............................... ............1.................. | +-- 90 | -----1--- 11111111111111111111--1111111111 1-0--1------1------------------ -------------------------------- | ............1.................. ............................... | +-- 91 | -----1--- 111111111111111111--111111111111 1-0--0-----0------------------- -------------------------------- | ............................... ...........1................... | +-- 92 | -----1--- 1111111111111111--11111111111111 1-0--0-----1------------------- -------------------------------- | ...........1................... ............................... | +-- 93 | -----1--- 11111111111111--1111111111111111 01--1-----0-------------------- -------------------------------- | ............................... ..........1.................... | +-- 94 | -----1--- 111111111111--111111111111111111 01--1-----1-------------------- -------------------------------- | ..........1.................... ............................... | +-- 95 | -----1--- 1111111111--11111111111111111111 01--0----0--------------------- -------------------------------- | ............................... .........1..................... | +-- 96 | -----1--- 11111111--1111111111111111111111 01--0----1--------------------- -------------------------------- | .........1..................... ............................... | +-- 97 | -----1--- 111111--111111111111111111111111 00-1----0---------------------- -------------------------------- | ............................... ........1...................... | +-- 98 | -----1--- 1111--11111111111111111111111111 00-1----1---------------------- -------------------------------- | ........1...................... ............................... | +-- 99 | -----1--- 11--1111111111111111111111111111 00-0---0----------------------- -------------------------------- | ............................... .......1....................... | +-- 100 | -----1--- --111111111111111111111111111111 00-0---1----------------------- -------------------------------- | .......1....................... ............................... | +-- 101 | -----1--- 1111111111111111111111111111---- 1-1---0------------------------ -------------------------------- | ............................... ......1........................ | +-- 102 | -----1--- 111111111111111111111111----1111 1-1---1------------------------ -------------------------------- | ......1........................ ............................... | +-- 103 | -----1--- 11111111111111111111----11111111 1-0--0------------------------- -------------------------------- | ............................... .....1......................... | +-- 104 | -----1--- 1111111111111111----111111111111 1-0--1------------------------- -------------------------------- | .....1......................... ............................... | +-- 105 | -----1--- 111111111111----1111111111111111 01--0-------------------------- -------------------------------- | ............................... ....1.......................... | +-- 106 | -----1--- 11111111----11111111111111111111 01--1-------------------------- -------------------------------- | ....1.......................... ............................... | +-- 107 | -----1--- 1111----111111111111111111111111 00-0--------------------------- -------------------------------- | ............................... ...1........................... | +-- 108 | -----1--- ----1111111111111111111111111111 00-1--------------------------- -------------------------------- | ...1........................... ............................... | +-- 109 | -----1--- 111111111111111111111111-------- 1-0---------------------------- -------------------------------- | ............................... ..1............................ | +-- 110 | -----1--- 1111111111111111--------11111111 1-1---------------------------- -------------------------------- | ..1............................ ............................... | +-- 111 | -----1--- 11111111--------1111111111111111 00----------------------------- -------------------------------- | ............................... .1............................. | +-- 112 | -----1--- --------111111111111111111111111 01----------------------------- -------------------------------- | .1............................. ............................... | +-- 113 | -----1--- 1111111111111111---------------- 0------------------------------ -------------------------------- | ............................... 1.............................. | +-- 114 | -----1--- ----------------1111111111111111 1------------------------------ -------------------------------- | 1.............................. ............................... | +-- 115 | --------- 11111111111111111111111111111110 ------------------------------- -------------------------------- | ............................... 1.1...1.......1...............1 | +-- 116 | --------- 1111111111111111111111111111110- ------------------------------- -------------------------------- | ..............................1 1.1...1.......1................ | +-- 117 | --------- 111111111111111111111111111110-- ------------------------------- -------------------------------- | ............................... 1.1...1......................1. | +-- 118 | --------- 1111111111111111111111111111-0-- ------------------------------- -------------------------------- | ..............1................ ............................... | +-- 119 | --------- 11111111111111111111111111110--- ------------------------------- -------------------------------- | ..............1..............1. 1.1...1........................ | +-- 120 | --------- 1111111111111111111111111110---- ------------------------------- -------------------------------- | ............................... 1.1..........1..............1.. | +-- 121 | --------- 111111111111111111111111---0---- ------------------------------- -------------------------------- | ......1........................ ............................... | +-- 122 | --------- 111111111111111111111111110----- ------------------------------- -------------------------------- | ......1.....................1.. 1.1..........1................. | +-- 123 | --------- 11111111111111111111111110------ ------------------------------- -------------------------------- | ............................... 1.1........................1... | +-- 124 | --------- 111111111111111111111111-0------ ------------------------------- -------------------------------- | ......1......1................. ............................... | +-- 125 | --------- 1111111111111111111111110------- ------------------------------- -------------------------------- | ......1......1.............1... 1.1............................ | +-- 126 | --------- 111111111111111111111110-------- ------------------------------- -------------------------------- | ............................... 1....1......1.............1.... | +-- 127 | --------- 1111111111111111-------0-------- ------------------------------- -------------------------------- | ..1............................ ............................... | +-- 128 | --------- 11111111111111111111110--------- ------------------------------- -------------------------------- | ..1.......................1.... 1....1......1.................. | +-- 129 | --------- 1111111111111111111110---------- ------------------------------- -------------------------------- | ............................... 1....1...................1..... | +-- 130 | --------- 11111111111111111111-0---------- ------------------------------- -------------------------------- | ..1.........1.................. ............................... | +-- 131 | --------- 111111111111111111110----------- ------------------------------- -------------------------------- | ..1.........1............1..... 1....1......................... | +-- 132 | --------- 11111111111111111110------------ ------------------------------- -------------------------------- | ............................... 1..........1............1...... | +-- 133 | --------- 1111111111111111---0------------ ------------------------------- -------------------------------- | ..1..1......................... ............................... | +-- 134 | --------- 1111111111111111110------------- ------------------------------- -------------------------------- | ..1..1..................1...... 1..........1................... | +-- 135 | --------- 111111111111111110-------------- ------------------------------- -------------------------------- | ............................... 1......................1....... | +-- 136 | --------- 1111111111111111-0-------------- ------------------------------- -------------------------------- | ..1..1.....1................... ............................... | +-- 137 | --------- 11111111111111110--------------- ------------------------------- -------------------------------- | ..1..1.....1...........1....... 1.............................. | +-- 138 | --------- 1111111111111110---------------- ------------------------------- -------------------------------- | ............................... .1..1.....1...........1........ | +-- 139 | --------- ---------------0---------------- ------------------------------- -------------------------------- | 1.............................. ............................... | +-- 140 | --------- 111111111111110----------------- ------------------------------- -------------------------------- | 1.....................1........ .1..1.....1.................... | +-- 141 | --------- 11111111111110------------------ ------------------------------- -------------------------------- | ............................... .1..1................1......... | +-- 142 | --------- 111111111111-0------------------ ------------------------------- -------------------------------- | 1.........1.................... ............................... | +-- 143 | --------- 1111111111110------------------- ------------------------------- -------------------------------- | 1.........1..........1......... .1..1.......................... | +-- 144 | --------- 111111111110-------------------- ------------------------------- -------------------------------- | ............................... .1.......1..........1.......... | +-- 145 | --------- 11111111---0-------------------- ------------------------------- -------------------------------- | 1...1.......................... ............................... | +-- 146 | --------- 11111111110--------------------- ------------------------------- -------------------------------- | 1...1...............1.......... .1.......1..................... | +-- 147 | --------- 1111111110---------------------- ------------------------------- -------------------------------- | ............................... .1.................1........... | +-- 148 | --------- 11111111-0---------------------- ------------------------------- -------------------------------- | 1...1....1..................... ............................... | +-- 149 | --------- 111111110----------------------- ------------------------------- -------------------------------- | 1...1....1.........1........... .1............................. | +-- 150 | --------- 11111110------------------------ ------------------------------- -------------------------------- | ............................... ...1....1.........1............ | +-- 151 | --------- -------0------------------------ ------------------------------- -------------------------------- | 11............................. ............................... | +-- 152 | --------- 1111110------------------------- ------------------------------- -------------------------------- | 11................1............ ...1....1...................... | +-- 153 | --------- 111110-------------------------- ------------------------------- -------------------------------- | ............................... ...1.............1............. | +-- 154 | --------- 1111-0-------------------------- ------------------------------- -------------------------------- | 11......1...................... ............................... | +-- 155 | --------- 11110--------------------------- ------------------------------- -------------------------------- | 11......1........1............. ...1........................... | +-- 156 | --------- 1110---------------------------- ------------------------------- -------------------------------- | ............................... .......1........1.............. | +-- 157 | --------- ---0---------------------------- ------------------------------- -------------------------------- | 11.1........................... ............................... | +-- 158 | --------- 110----------------------------- ------------------------------- -------------------------------- | 11.1............1.............. .......1....................... | +-- 159 | --------- 10------------------------------ ------------------------------- -------------------------------- | ............................... ...............1............... | +-- 160 | --------- -0------------------------------ ------------------------------- -------------------------------- | 11.1...1....................... ............................... | +-- 161 | --------- 0------------------------------- ------------------------------- -------------------------------- | 11.1...1.......1............... ............................... | +-- *=====================================================================================================================================================================================* +-- +-- Table LRU_SET_RESET_VEC Signal Assignments for Product Terms +MQQ134:LRU_SET_RESET_VEC_PT(1) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) & + ENTRY_MATCH_Q(13) & ENTRY_MATCH_Q(14) & + ENTRY_MATCH_Q(15) & ENTRY_MATCH_Q(16) & + ENTRY_MATCH_Q(17) & ENTRY_MATCH_Q(18) & + ENTRY_MATCH_Q(19) & ENTRY_MATCH_Q(20) & + ENTRY_MATCH_Q(21) & ENTRY_MATCH_Q(22) & + ENTRY_MATCH_Q(23) & ENTRY_MATCH_Q(24) & + ENTRY_MATCH_Q(25) & ENTRY_MATCH_Q(26) & + ENTRY_MATCH_Q(27) & ENTRY_MATCH_Q(28) & + ENTRY_MATCH_Q(29) & ENTRY_MATCH_Q(30) & + ENTRY_MATCH_Q(31) ) , STD_ULOGIC_VECTOR'("0011111111111111111111111111111111100000000000000000000" & +"000000000001")); +MQQ135:LRU_SET_RESET_VEC_PT(2) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) & + ENTRY_MATCH_Q(13) & ENTRY_MATCH_Q(14) & + ENTRY_MATCH_Q(15) & ENTRY_MATCH_Q(16) & + ENTRY_MATCH_Q(17) & ENTRY_MATCH_Q(18) & + ENTRY_MATCH_Q(19) & ENTRY_MATCH_Q(20) & + ENTRY_MATCH_Q(21) & ENTRY_MATCH_Q(22) & + ENTRY_MATCH_Q(23) & ENTRY_MATCH_Q(24) & + ENTRY_MATCH_Q(25) & ENTRY_MATCH_Q(26) & + ENTRY_MATCH_Q(27) & ENTRY_MATCH_Q(28) & + ENTRY_MATCH_Q(29) & ENTRY_MATCH_Q(30) + ) , STD_ULOGIC_VECTOR'("001111111111111111111111111111111110000000000000000000000000000001")); +MQQ136:LRU_SET_RESET_VEC_PT(3) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_MATCH_Q(0) & ENTRY_MATCH_Q(1) & + ENTRY_MATCH_Q(2) & ENTRY_MATCH_Q(3) & + ENTRY_MATCH_Q(4) & ENTRY_MATCH_Q(5) & + ENTRY_MATCH_Q(6) & ENTRY_MATCH_Q(7) & + ENTRY_MATCH_Q(8) & ENTRY_MATCH_Q(9) & + ENTRY_MATCH_Q(10) & ENTRY_MATCH_Q(11) & + ENTRY_MATCH_Q(12) & ENTRY_MATCH_Q(13) & + ENTRY_MATCH_Q(14) & ENTRY_MATCH_Q(15) & + ENTRY_MATCH_Q(16) & ENTRY_MATCH_Q(17) & + ENTRY_MATCH_Q(18) & ENTRY_MATCH_Q(19) & + ENTRY_MATCH_Q(20) & ENTRY_MATCH_Q(21) & + ENTRY_MATCH_Q(22) & ENTRY_MATCH_Q(23) & + ENTRY_MATCH_Q(24) & ENTRY_MATCH_Q(25) & + ENTRY_MATCH_Q(26) & ENTRY_MATCH_Q(27) & + ENTRY_MATCH_Q(28) & ENTRY_MATCH_Q(29) & + ENTRY_MATCH_Q(30) ) , STD_ULOGIC_VECTOR'("0011111111111111111111111111111111000000000000000000000" & +"0000000001")); +MQQ137:LRU_SET_RESET_VEC_PT(4) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) & + ENTRY_MATCH_Q(13) & ENTRY_MATCH_Q(14) & + ENTRY_MATCH_Q(15) & ENTRY_MATCH_Q(16) & + ENTRY_MATCH_Q(17) & ENTRY_MATCH_Q(18) & + ENTRY_MATCH_Q(19) & ENTRY_MATCH_Q(20) & + ENTRY_MATCH_Q(21) & ENTRY_MATCH_Q(22) & + ENTRY_MATCH_Q(23) & ENTRY_MATCH_Q(24) & + ENTRY_MATCH_Q(25) & ENTRY_MATCH_Q(26) & + ENTRY_MATCH_Q(27) & ENTRY_MATCH_Q(28) & + ENTRY_MATCH_Q(29) ) , STD_ULOGIC_VECTOR'("0011111111111111111111111111111111100000000000000000000" & +"0000000001")); +MQQ138:LRU_SET_RESET_VEC_PT(5) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) & + ENTRY_MATCH_Q(13) & ENTRY_MATCH_Q(14) & + ENTRY_MATCH_Q(15) & ENTRY_MATCH_Q(16) & + ENTRY_MATCH_Q(17) & ENTRY_MATCH_Q(18) & + ENTRY_MATCH_Q(19) & ENTRY_MATCH_Q(20) & + ENTRY_MATCH_Q(21) & ENTRY_MATCH_Q(22) & + ENTRY_MATCH_Q(23) & ENTRY_MATCH_Q(24) & + ENTRY_MATCH_Q(25) & ENTRY_MATCH_Q(26) & + ENTRY_MATCH_Q(27) & ENTRY_MATCH_Q(29) + ) , STD_ULOGIC_VECTOR'("00111111111111111111111111111111100000000000000000000000000001")); +MQQ139:LRU_SET_RESET_VEC_PT(6) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) & + ENTRY_MATCH_Q(13) & ENTRY_MATCH_Q(14) & + ENTRY_MATCH_Q(15) & ENTRY_MATCH_Q(16) & + ENTRY_MATCH_Q(17) & ENTRY_MATCH_Q(18) & + ENTRY_MATCH_Q(19) & ENTRY_MATCH_Q(20) & + ENTRY_MATCH_Q(21) & ENTRY_MATCH_Q(22) & + ENTRY_MATCH_Q(23) & ENTRY_MATCH_Q(24) & + ENTRY_MATCH_Q(25) & ENTRY_MATCH_Q(26) & + ENTRY_MATCH_Q(27) & ENTRY_MATCH_Q(28) + ) , STD_ULOGIC_VECTOR'("0011111111111111111111111111111111100000000000000000000000000001")); +MQQ140:LRU_SET_RESET_VEC_PT(7) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) & + ENTRY_MATCH_Q(13) & ENTRY_MATCH_Q(14) & + ENTRY_MATCH_Q(15) & ENTRY_MATCH_Q(16) & + ENTRY_MATCH_Q(17) & ENTRY_MATCH_Q(18) & + ENTRY_MATCH_Q(19) & ENTRY_MATCH_Q(20) & + ENTRY_MATCH_Q(21) & ENTRY_MATCH_Q(22) & + ENTRY_MATCH_Q(23) & ENTRY_MATCH_Q(24) & + ENTRY_MATCH_Q(25) & ENTRY_MATCH_Q(26) & + ENTRY_MATCH_Q(27) ) , STD_ULOGIC_VECTOR'("0011111111111111111111111111111111100000000000000000000" & +"00000001")); +MQQ141:LRU_SET_RESET_VEC_PT(8) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) & + ENTRY_MATCH_Q(13) & ENTRY_MATCH_Q(14) & + ENTRY_MATCH_Q(15) & ENTRY_MATCH_Q(16) & + ENTRY_MATCH_Q(17) & ENTRY_MATCH_Q(18) & + ENTRY_MATCH_Q(19) & ENTRY_MATCH_Q(20) & + ENTRY_MATCH_Q(21) & ENTRY_MATCH_Q(22) & + ENTRY_MATCH_Q(23) & ENTRY_MATCH_Q(27) + ) , STD_ULOGIC_VECTOR'("00111111111111111111111111111110000000000000000000000001")); +MQQ142:LRU_SET_RESET_VEC_PT(9) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) & + ENTRY_MATCH_Q(13) & ENTRY_MATCH_Q(14) & + ENTRY_MATCH_Q(15) & ENTRY_MATCH_Q(16) & + ENTRY_MATCH_Q(17) & ENTRY_MATCH_Q(18) & + ENTRY_MATCH_Q(19) & ENTRY_MATCH_Q(20) & + ENTRY_MATCH_Q(21) & ENTRY_MATCH_Q(22) & + ENTRY_MATCH_Q(23) & ENTRY_MATCH_Q(24) & + ENTRY_MATCH_Q(25) & ENTRY_MATCH_Q(26) + ) , STD_ULOGIC_VECTOR'("00111111111111111111111111111111111000000000000000000000000001")); +MQQ143:LRU_SET_RESET_VEC_PT(10) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) & + ENTRY_MATCH_Q(13) & ENTRY_MATCH_Q(14) & + ENTRY_MATCH_Q(15) & ENTRY_MATCH_Q(16) & + ENTRY_MATCH_Q(17) & ENTRY_MATCH_Q(18) & + ENTRY_MATCH_Q(19) & ENTRY_MATCH_Q(20) & + ENTRY_MATCH_Q(21) & ENTRY_MATCH_Q(22) & + ENTRY_MATCH_Q(23) & ENTRY_MATCH_Q(24) & + ENTRY_MATCH_Q(25) ) , STD_ULOGIC_VECTOR'("0011111111111111111111111111111111100000000000000000000" & +"000001")); +MQQ144:LRU_SET_RESET_VEC_PT(11) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) & + ENTRY_MATCH_Q(13) & ENTRY_MATCH_Q(14) & + ENTRY_MATCH_Q(15) & ENTRY_MATCH_Q(16) & + ENTRY_MATCH_Q(17) & ENTRY_MATCH_Q(18) & + ENTRY_MATCH_Q(19) & ENTRY_MATCH_Q(20) & + ENTRY_MATCH_Q(21) & ENTRY_MATCH_Q(22) & + ENTRY_MATCH_Q(23) & ENTRY_MATCH_Q(25) + ) , STD_ULOGIC_VECTOR'("001111111111111111111111111111111110000000000000000000000001")); +MQQ145:LRU_SET_RESET_VEC_PT(12) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) & + ENTRY_MATCH_Q(13) & ENTRY_MATCH_Q(14) & + ENTRY_MATCH_Q(15) & ENTRY_MATCH_Q(16) & + ENTRY_MATCH_Q(17) & ENTRY_MATCH_Q(18) & + ENTRY_MATCH_Q(19) & ENTRY_MATCH_Q(20) & + ENTRY_MATCH_Q(21) & ENTRY_MATCH_Q(22) & + ENTRY_MATCH_Q(23) & ENTRY_MATCH_Q(24) + ) , STD_ULOGIC_VECTOR'("001111111111111111111111111111111110000000000000000000000001")); +MQQ146:LRU_SET_RESET_VEC_PT(13) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) & + ENTRY_MATCH_Q(13) & ENTRY_MATCH_Q(14) & + ENTRY_MATCH_Q(15) & ENTRY_MATCH_Q(16) & + ENTRY_MATCH_Q(17) & ENTRY_MATCH_Q(18) & + ENTRY_MATCH_Q(19) & ENTRY_MATCH_Q(20) & + ENTRY_MATCH_Q(21) & ENTRY_MATCH_Q(22) & + ENTRY_MATCH_Q(23) ) , STD_ULOGIC_VECTOR'("0011111111111111111111111111111111100000000000000000000" & +"0001")); +MQQ147:LRU_SET_RESET_VEC_PT(14) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) & + ENTRY_MATCH_Q(13) & ENTRY_MATCH_Q(14) & + ENTRY_MATCH_Q(15) & ENTRY_MATCH_Q(23) + ) , STD_ULOGIC_VECTOR'("00111111111111111111111111100000000000000001")); +MQQ148:LRU_SET_RESET_VEC_PT(15) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) & + ENTRY_MATCH_Q(13) & ENTRY_MATCH_Q(14) & + ENTRY_MATCH_Q(15) & ENTRY_MATCH_Q(16) & + ENTRY_MATCH_Q(17) & ENTRY_MATCH_Q(18) & + ENTRY_MATCH_Q(19) & ENTRY_MATCH_Q(20) & + ENTRY_MATCH_Q(21) & ENTRY_MATCH_Q(22) + ) , STD_ULOGIC_VECTOR'("0011111111111111111111111111111111100000000000000000000001")); +MQQ149:LRU_SET_RESET_VEC_PT(16) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) & + ENTRY_MATCH_Q(13) & ENTRY_MATCH_Q(14) & + ENTRY_MATCH_Q(15) & ENTRY_MATCH_Q(16) & + ENTRY_MATCH_Q(17) & ENTRY_MATCH_Q(18) & + ENTRY_MATCH_Q(19) & ENTRY_MATCH_Q(20) & + ENTRY_MATCH_Q(21) ) , STD_ULOGIC_VECTOR'("0011111111111111111111111111111111100000000000000000000" & +"01")); +MQQ150:LRU_SET_RESET_VEC_PT(17) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) & + ENTRY_MATCH_Q(13) & ENTRY_MATCH_Q(14) & + ENTRY_MATCH_Q(15) & ENTRY_MATCH_Q(16) & + ENTRY_MATCH_Q(17) & ENTRY_MATCH_Q(18) & + ENTRY_MATCH_Q(19) & ENTRY_MATCH_Q(21) + ) , STD_ULOGIC_VECTOR'("00111111111111111111111111111111111000000000000000000001")); +MQQ151:LRU_SET_RESET_VEC_PT(18) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) & + ENTRY_MATCH_Q(13) & ENTRY_MATCH_Q(14) & + ENTRY_MATCH_Q(15) & ENTRY_MATCH_Q(16) & + ENTRY_MATCH_Q(17) & ENTRY_MATCH_Q(18) & + ENTRY_MATCH_Q(19) & ENTRY_MATCH_Q(20) + ) , STD_ULOGIC_VECTOR'("00111111111111111111111111111111111000000000000000000001")); +MQQ152:LRU_SET_RESET_VEC_PT(19) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) & + ENTRY_MATCH_Q(13) & ENTRY_MATCH_Q(14) & + ENTRY_MATCH_Q(15) & ENTRY_MATCH_Q(16) & + ENTRY_MATCH_Q(17) & ENTRY_MATCH_Q(18) & + ENTRY_MATCH_Q(19) ) , STD_ULOGIC_VECTOR'("0011111111111111111111111111111111100000000000000000001") +); +MQQ153:LRU_SET_RESET_VEC_PT(20) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) & + ENTRY_MATCH_Q(13) & ENTRY_MATCH_Q(14) & + ENTRY_MATCH_Q(15) & ENTRY_MATCH_Q(19) + ) , STD_ULOGIC_VECTOR'("0011111111111111111111111111111111100000000000000001")); +MQQ154:LRU_SET_RESET_VEC_PT(21) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) & + ENTRY_MATCH_Q(13) & ENTRY_MATCH_Q(14) & + ENTRY_MATCH_Q(15) & ENTRY_MATCH_Q(16) & + ENTRY_MATCH_Q(17) & ENTRY_MATCH_Q(18) + ) , STD_ULOGIC_VECTOR'("001111111111111111111111111111111110000000000000000001")); +MQQ155:LRU_SET_RESET_VEC_PT(22) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) & + ENTRY_MATCH_Q(13) & ENTRY_MATCH_Q(14) & + ENTRY_MATCH_Q(15) & ENTRY_MATCH_Q(16) & + ENTRY_MATCH_Q(17) ) , STD_ULOGIC_VECTOR'("00111111111111111111111111111111111000000000000000001") +); +MQQ156:LRU_SET_RESET_VEC_PT(23) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) & + ENTRY_MATCH_Q(13) & ENTRY_MATCH_Q(14) & + ENTRY_MATCH_Q(15) & ENTRY_MATCH_Q(17) + ) , STD_ULOGIC_VECTOR'("0011111111111111111111111111111111100000000000000001")); +MQQ157:LRU_SET_RESET_VEC_PT(24) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) & + ENTRY_MATCH_Q(13) & ENTRY_MATCH_Q(14) & + ENTRY_MATCH_Q(15) & ENTRY_MATCH_Q(16) + ) , STD_ULOGIC_VECTOR'("0011111111111111111111111111111111100000000000000001")); +MQQ158:LRU_SET_RESET_VEC_PT(25) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) & + ENTRY_MATCH_Q(13) & ENTRY_MATCH_Q(14) & + ENTRY_MATCH_Q(15) & ENTRY_MATCH_Q(16) + ) , STD_ULOGIC_VECTOR'("001111111111111111100000000000000001")); +MQQ159:LRU_SET_RESET_VEC_PT(26) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) & + ENTRY_MATCH_Q(13) & ENTRY_MATCH_Q(14) & + ENTRY_MATCH_Q(15) ) , STD_ULOGIC_VECTOR'("001111111111111111111111111111111110000000000000001")); +MQQ160:LRU_SET_RESET_VEC_PT(27) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_MATCH_Q(15) + ) , STD_ULOGIC_VECTOR'("00111111111111111111")); +MQQ161:LRU_SET_RESET_VEC_PT(28) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) & + ENTRY_MATCH_Q(13) & ENTRY_MATCH_Q(14) + ) , STD_ULOGIC_VECTOR'("00111111111111111111111111111111111000000000000001")); +MQQ162:LRU_SET_RESET_VEC_PT(29) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) & + ENTRY_MATCH_Q(13) ) , STD_ULOGIC_VECTOR'("0011111111111111111111111111111111100000000000001")); +MQQ163:LRU_SET_RESET_VEC_PT(30) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(13) + ) , STD_ULOGIC_VECTOR'("001111111111111111111111111111111110000000000001")); +MQQ164:LRU_SET_RESET_VEC_PT(31) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) & ENTRY_MATCH_Q(12) + ) , STD_ULOGIC_VECTOR'("001111111111111111111111111111111110000000000001")); +MQQ165:LRU_SET_RESET_VEC_PT(32) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) & + ENTRY_MATCH_Q(11) ) , STD_ULOGIC_VECTOR'("00111111111111111111111111111111111000000000001")); +MQQ166:LRU_SET_RESET_VEC_PT(33) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(11) + ) , STD_ULOGIC_VECTOR'("00111111111111111111111111111111111000000001")); +MQQ167:LRU_SET_RESET_VEC_PT(34) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) & ENTRY_MATCH_Q(10) + ) , STD_ULOGIC_VECTOR'("0011111111111111111111111111111111100000000001")); +MQQ168:LRU_SET_RESET_VEC_PT(35) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) & + ENTRY_MATCH_Q(9) ) , STD_ULOGIC_VECTOR'("001111111111111111111111111111111110000000001")); +MQQ169:LRU_SET_RESET_VEC_PT(36) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(9) + ) , STD_ULOGIC_VECTOR'("00111111111111111111111111111111111000000001")); +MQQ170:LRU_SET_RESET_VEC_PT(37) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) + ) , STD_ULOGIC_VECTOR'("00111111111111111111111111111111111000000001")); +MQQ171:LRU_SET_RESET_VEC_PT(38) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) & ENTRY_MATCH_Q(8) + ) , STD_ULOGIC_VECTOR'("001111111111111111111111111000000001")); +MQQ172:LRU_SET_RESET_VEC_PT(39) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) & + ENTRY_MATCH_Q(7) ) , STD_ULOGIC_VECTOR'("0011111111111111111111111111111111100000001")); +MQQ173:LRU_SET_RESET_VEC_PT(40) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(7) + ) , STD_ULOGIC_VECTOR'("001111111111111111111111111111111111")); +MQQ174:LRU_SET_RESET_VEC_PT(41) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) & ENTRY_MATCH_Q(6) + ) , STD_ULOGIC_VECTOR'("001111111111111111111111111111111110000001")); +MQQ175:LRU_SET_RESET_VEC_PT(42) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) & + ENTRY_MATCH_Q(5) ) , STD_ULOGIC_VECTOR'("00111111111111111111111111111111111000001")); +MQQ176:LRU_SET_RESET_VEC_PT(43) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(5) + ) , STD_ULOGIC_VECTOR'("0011111111111111111111111111111111100001")); +MQQ177:LRU_SET_RESET_VEC_PT(44) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) + ) , STD_ULOGIC_VECTOR'("0011111111111111111111111111111111100001")); +MQQ178:LRU_SET_RESET_VEC_PT(45) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) & ENTRY_MATCH_Q(4) + ) , STD_ULOGIC_VECTOR'("001111111111111111111111111111100001")); +MQQ179:LRU_SET_RESET_VEC_PT(46) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) & + ENTRY_MATCH_Q(3) ) , STD_ULOGIC_VECTOR'("001111111111111111111111111111111110001")); +MQQ180:LRU_SET_RESET_VEC_PT(47) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(3) + ) , STD_ULOGIC_VECTOR'("001111111111111111111111111111111111")); +MQQ181:LRU_SET_RESET_VEC_PT(48) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) + ) , STD_ULOGIC_VECTOR'("00111111111111111111111111111111111001")); +MQQ182:LRU_SET_RESET_VEC_PT(49) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) & + ENTRY_MATCH_Q(1) & ENTRY_MATCH_Q(2) + ) , STD_ULOGIC_VECTOR'("001111111111111111111111111111111001")); +MQQ183:LRU_SET_RESET_VEC_PT(50) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + ENTRY_MATCH_Q(0) & ENTRY_MATCH_Q(1) + ) , STD_ULOGIC_VECTOR'("001111111111111111111111111111111101")); +MQQ184:LRU_SET_RESET_VEC_PT(51) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(1) + ) , STD_ULOGIC_VECTOR'("001111111111111111111111111111111111")); +MQQ185:LRU_SET_RESET_VEC_PT(52) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & LRU_UPDATE_EVENT_Q(6) & + LRU_UPDATE_EVENT_Q(7) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & ENTRY_MATCH_Q(0) + ) , STD_ULOGIC_VECTOR'("001111111111111111111111111111111111")); +MQQ186:LRU_SET_RESET_VEC_PT(53) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + LRU_Q(1) & LRU_Q(3) & + LRU_Q(7) & LRU_Q(15) & + LRU_Q(31) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111111110")); +MQQ187:LRU_SET_RESET_VEC_PT(54) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(3) & + LRU_Q(7) & LRU_Q(15) & + LRU_Q(31) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111111111")); +MQQ188:LRU_SET_RESET_VEC_PT(55) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(3) & + LRU_Q(7) & LRU_Q(15) & + LRU_Q(30) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111111100")); +MQQ189:LRU_SET_RESET_VEC_PT(56) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(3) & + LRU_Q(7) & LRU_Q(15) & + LRU_Q(30) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111111101")); +MQQ190:LRU_SET_RESET_VEC_PT(57) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(3) & + LRU_Q(7) & LRU_Q(14) & + LRU_Q(29) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111111010")); +MQQ191:LRU_SET_RESET_VEC_PT(58) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(3) & + LRU_Q(7) & LRU_Q(14) & + LRU_Q(29) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111111011")); +MQQ192:LRU_SET_RESET_VEC_PT(59) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(3) & + LRU_Q(7) & LRU_Q(14) & + LRU_Q(28) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111111000")); +MQQ193:LRU_SET_RESET_VEC_PT(60) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(3) & + LRU_Q(7) & LRU_Q(14) & + LRU_Q(28) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111111001")); +MQQ194:LRU_SET_RESET_VEC_PT(61) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(3) & + LRU_Q(6) & LRU_Q(13) & + LRU_Q(27) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111110110")); +MQQ195:LRU_SET_RESET_VEC_PT(62) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(3) & + LRU_Q(6) & LRU_Q(13) & + LRU_Q(27) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111110111")); +MQQ196:LRU_SET_RESET_VEC_PT(63) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(3) & + LRU_Q(6) & LRU_Q(13) & + LRU_Q(26) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111110100")); +MQQ197:LRU_SET_RESET_VEC_PT(64) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(3) & + LRU_Q(6) & LRU_Q(13) & + LRU_Q(26) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111110101")); +MQQ198:LRU_SET_RESET_VEC_PT(65) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(3) & + LRU_Q(6) & LRU_Q(12) & + LRU_Q(25) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111110010")); +MQQ199:LRU_SET_RESET_VEC_PT(66) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(3) & + LRU_Q(6) & LRU_Q(12) & + LRU_Q(25) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111110011")); +MQQ200:LRU_SET_RESET_VEC_PT(67) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(3) & + LRU_Q(6) & LRU_Q(12) & + LRU_Q(24) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111110000")); +MQQ201:LRU_SET_RESET_VEC_PT(68) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(3) & + LRU_Q(6) & LRU_Q(12) & + LRU_Q(24) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111110001")); +MQQ202:LRU_SET_RESET_VEC_PT(69) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(2) & + LRU_Q(5) & LRU_Q(11) & + LRU_Q(23) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111101110")); +MQQ203:LRU_SET_RESET_VEC_PT(70) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(2) & + LRU_Q(5) & LRU_Q(11) & + LRU_Q(23) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111101111")); +MQQ204:LRU_SET_RESET_VEC_PT(71) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(2) & + LRU_Q(5) & LRU_Q(11) & + LRU_Q(22) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111101100")); +MQQ205:LRU_SET_RESET_VEC_PT(72) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(2) & + LRU_Q(5) & LRU_Q(11) & + LRU_Q(22) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111101101")); +MQQ206:LRU_SET_RESET_VEC_PT(73) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(2) & + LRU_Q(5) & LRU_Q(10) & + LRU_Q(21) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111101010")); +MQQ207:LRU_SET_RESET_VEC_PT(74) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(2) & + LRU_Q(5) & LRU_Q(10) & + LRU_Q(21) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111101011")); +MQQ208:LRU_SET_RESET_VEC_PT(75) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(2) & + LRU_Q(5) & LRU_Q(10) & + LRU_Q(20) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111101000")); +MQQ209:LRU_SET_RESET_VEC_PT(76) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(2) & + LRU_Q(5) & LRU_Q(10) & + LRU_Q(20) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111101001")); +MQQ210:LRU_SET_RESET_VEC_PT(77) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(2) & + LRU_Q(4) & LRU_Q(9) & + LRU_Q(19) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111100110")); +MQQ211:LRU_SET_RESET_VEC_PT(78) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(2) & + LRU_Q(4) & LRU_Q(9) & + LRU_Q(19) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111100111")); +MQQ212:LRU_SET_RESET_VEC_PT(79) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(2) & + LRU_Q(4) & LRU_Q(9) & + LRU_Q(18) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111100100")); +MQQ213:LRU_SET_RESET_VEC_PT(80) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(2) & + LRU_Q(4) & LRU_Q(9) & + LRU_Q(18) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111100101")); +MQQ214:LRU_SET_RESET_VEC_PT(81) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(2) & + LRU_Q(4) & LRU_Q(8) & + LRU_Q(17) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111100010")); +MQQ215:LRU_SET_RESET_VEC_PT(82) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(2) & + LRU_Q(4) & LRU_Q(8) & + LRU_Q(17) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111100011")); +MQQ216:LRU_SET_RESET_VEC_PT(83) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(2) & + LRU_Q(4) & LRU_Q(8) & + LRU_Q(16) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111100000")); +MQQ217:LRU_SET_RESET_VEC_PT(84) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) & + LRU_Q(1) & LRU_Q(2) & + LRU_Q(4) & LRU_Q(8) & + LRU_Q(16) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111111100001")); +MQQ218:LRU_SET_RESET_VEC_PT(85) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & LRU_Q(1) & + LRU_Q(3) & LRU_Q(7) & + LRU_Q(15) ) , STD_ULOGIC_VECTOR'("11111111111111111111111111111111110")); +MQQ219:LRU_SET_RESET_VEC_PT(86) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & LRU_Q(1) & + LRU_Q(3) & LRU_Q(7) & + LRU_Q(15) ) , STD_ULOGIC_VECTOR'("11111111111111111111111111111111111")); +MQQ220:LRU_SET_RESET_VEC_PT(87) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & LRU_Q(1) & + LRU_Q(3) & LRU_Q(7) & + LRU_Q(14) ) , STD_ULOGIC_VECTOR'("11111111111111111111111111111111100")); +MQQ221:LRU_SET_RESET_VEC_PT(88) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & LRU_Q(1) & + LRU_Q(3) & LRU_Q(7) & + LRU_Q(14) ) , STD_ULOGIC_VECTOR'("11111111111111111111111111111111101")); +MQQ222:LRU_SET_RESET_VEC_PT(89) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & LRU_Q(1) & + LRU_Q(3) & LRU_Q(6) & + LRU_Q(13) ) , STD_ULOGIC_VECTOR'("11111111111111111111111111111111010")); +MQQ223:LRU_SET_RESET_VEC_PT(90) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & LRU_Q(1) & + LRU_Q(3) & LRU_Q(6) & + LRU_Q(13) ) , STD_ULOGIC_VECTOR'("11111111111111111111111111111111011")); +MQQ224:LRU_SET_RESET_VEC_PT(91) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & LRU_Q(1) & + LRU_Q(3) & LRU_Q(6) & + LRU_Q(12) ) , STD_ULOGIC_VECTOR'("11111111111111111111111111111111000")); +MQQ225:LRU_SET_RESET_VEC_PT(92) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & LRU_Q(1) & + LRU_Q(3) & LRU_Q(6) & + LRU_Q(12) ) , STD_ULOGIC_VECTOR'("11111111111111111111111111111111001")); +MQQ226:LRU_SET_RESET_VEC_PT(93) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & LRU_Q(1) & + LRU_Q(2) & LRU_Q(5) & + LRU_Q(11) ) , STD_ULOGIC_VECTOR'("11111111111111111111111111111110110")); +MQQ227:LRU_SET_RESET_VEC_PT(94) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & LRU_Q(1) & + LRU_Q(2) & LRU_Q(5) & + LRU_Q(11) ) , STD_ULOGIC_VECTOR'("11111111111111111111111111111110111")); +MQQ228:LRU_SET_RESET_VEC_PT(95) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & LRU_Q(1) & + LRU_Q(2) & LRU_Q(5) & + LRU_Q(10) ) , STD_ULOGIC_VECTOR'("11111111111111111111111111111110100")); +MQQ229:LRU_SET_RESET_VEC_PT(96) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & LRU_Q(1) & + LRU_Q(2) & LRU_Q(5) & + LRU_Q(10) ) , STD_ULOGIC_VECTOR'("11111111111111111111111111111110101")); +MQQ230:LRU_SET_RESET_VEC_PT(97) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & LRU_Q(1) & + LRU_Q(2) & LRU_Q(4) & + LRU_Q(9) ) , STD_ULOGIC_VECTOR'("11111111111111111111111111111110010")); +MQQ231:LRU_SET_RESET_VEC_PT(98) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & LRU_Q(1) & + LRU_Q(2) & LRU_Q(4) & + LRU_Q(9) ) , STD_ULOGIC_VECTOR'("11111111111111111111111111111110011")); +MQQ232:LRU_SET_RESET_VEC_PT(99) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & LRU_Q(1) & + LRU_Q(2) & LRU_Q(4) & + LRU_Q(8) ) , STD_ULOGIC_VECTOR'("11111111111111111111111111111110000")); +MQQ233:LRU_SET_RESET_VEC_PT(100) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & LRU_Q(1) & + LRU_Q(2) & LRU_Q(4) & + LRU_Q(8) ) , STD_ULOGIC_VECTOR'("11111111111111111111111111111110001")); +MQQ234:LRU_SET_RESET_VEC_PT(101) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & LRU_Q(1) & + LRU_Q(3) & LRU_Q(7) + ) , STD_ULOGIC_VECTOR'("11111111111111111111111111111110")); +MQQ235:LRU_SET_RESET_VEC_PT(102) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & LRU_Q(1) & + LRU_Q(3) & LRU_Q(7) + ) , STD_ULOGIC_VECTOR'("11111111111111111111111111111111")); +MQQ236:LRU_SET_RESET_VEC_PT(103) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & LRU_Q(1) & + LRU_Q(3) & LRU_Q(6) + ) , STD_ULOGIC_VECTOR'("11111111111111111111111111111100")); +MQQ237:LRU_SET_RESET_VEC_PT(104) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & LRU_Q(1) & + LRU_Q(3) & LRU_Q(6) + ) , STD_ULOGIC_VECTOR'("11111111111111111111111111111101")); +MQQ238:LRU_SET_RESET_VEC_PT(105) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & LRU_Q(1) & + LRU_Q(2) & LRU_Q(5) + ) , STD_ULOGIC_VECTOR'("11111111111111111111111111111010")); +MQQ239:LRU_SET_RESET_VEC_PT(106) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & LRU_Q(1) & + LRU_Q(2) & LRU_Q(5) + ) , STD_ULOGIC_VECTOR'("11111111111111111111111111111011")); +MQQ240:LRU_SET_RESET_VEC_PT(107) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & LRU_Q(1) & + LRU_Q(2) & LRU_Q(4) + ) , STD_ULOGIC_VECTOR'("11111111111111111111111111111000")); +MQQ241:LRU_SET_RESET_VEC_PT(108) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & LRU_Q(1) & + LRU_Q(2) & LRU_Q(4) + ) , STD_ULOGIC_VECTOR'("11111111111111111111111111111001")); +MQQ242:LRU_SET_RESET_VEC_PT(109) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & LRU_Q(1) & + LRU_Q(3) ) , STD_ULOGIC_VECTOR'("111111111111111111111111110")); +MQQ243:LRU_SET_RESET_VEC_PT(110) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & LRU_Q(1) & + LRU_Q(3) ) , STD_ULOGIC_VECTOR'("111111111111111111111111111")); +MQQ244:LRU_SET_RESET_VEC_PT(111) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & LRU_Q(1) & + LRU_Q(2) ) , STD_ULOGIC_VECTOR'("111111111111111111111111100")); +MQQ245:LRU_SET_RESET_VEC_PT(112) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & LRU_Q(1) & + LRU_Q(2) ) , STD_ULOGIC_VECTOR'("111111111111111111111111101")); +MQQ246:LRU_SET_RESET_VEC_PT(113) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(0) & + ENTRY_VALID_WATERMARKED(1) & ENTRY_VALID_WATERMARKED(2) & + ENTRY_VALID_WATERMARKED(3) & ENTRY_VALID_WATERMARKED(4) & + ENTRY_VALID_WATERMARKED(5) & ENTRY_VALID_WATERMARKED(6) & + ENTRY_VALID_WATERMARKED(7) & ENTRY_VALID_WATERMARKED(8) & + ENTRY_VALID_WATERMARKED(9) & ENTRY_VALID_WATERMARKED(10) & + ENTRY_VALID_WATERMARKED(11) & ENTRY_VALID_WATERMARKED(12) & + ENTRY_VALID_WATERMARKED(13) & ENTRY_VALID_WATERMARKED(14) & + ENTRY_VALID_WATERMARKED(15) & LRU_Q(1) + ) , STD_ULOGIC_VECTOR'("111111111111111110")); +MQQ247:LRU_SET_RESET_VEC_PT(114) <= + Eq(( LRU_UPDATE_EVENT_Q(5) & ENTRY_VALID_WATERMARKED(16) & + ENTRY_VALID_WATERMARKED(17) & ENTRY_VALID_WATERMARKED(18) & + ENTRY_VALID_WATERMARKED(19) & ENTRY_VALID_WATERMARKED(20) & + ENTRY_VALID_WATERMARKED(21) & ENTRY_VALID_WATERMARKED(22) & + ENTRY_VALID_WATERMARKED(23) & ENTRY_VALID_WATERMARKED(24) & + ENTRY_VALID_WATERMARKED(25) & ENTRY_VALID_WATERMARKED(26) & + ENTRY_VALID_WATERMARKED(27) & ENTRY_VALID_WATERMARKED(28) & + ENTRY_VALID_WATERMARKED(29) & ENTRY_VALID_WATERMARKED(30) & + ENTRY_VALID_WATERMARKED(31) & LRU_Q(1) + ) , STD_ULOGIC_VECTOR'("111111111111111111")); +MQQ248:LRU_SET_RESET_VEC_PT(115) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) & ENTRY_VALID_WATERMARKED(31) + ) , STD_ULOGIC_VECTOR'("11111111111111111111111111111110")); +MQQ249:LRU_SET_RESET_VEC_PT(116) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) & + ENTRY_VALID_WATERMARKED(30) ) , STD_ULOGIC_VECTOR'("1111111111111111111111111111110")); +MQQ250:LRU_SET_RESET_VEC_PT(117) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) & ENTRY_VALID_WATERMARKED(29) + ) , STD_ULOGIC_VECTOR'("111111111111111111111111111110")); +MQQ251:LRU_SET_RESET_VEC_PT(118) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(29) ) , STD_ULOGIC_VECTOR'("11111111111111111111111111110")); +MQQ252:LRU_SET_RESET_VEC_PT(119) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) & + ENTRY_VALID_WATERMARKED(28) ) , STD_ULOGIC_VECTOR'("11111111111111111111111111110")); +MQQ253:LRU_SET_RESET_VEC_PT(120) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) & ENTRY_VALID_WATERMARKED(27) + ) , STD_ULOGIC_VECTOR'("1111111111111111111111111110")); +MQQ254:LRU_SET_RESET_VEC_PT(121) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(27) ) , STD_ULOGIC_VECTOR'("1111111111111111111111110")); +MQQ255:LRU_SET_RESET_VEC_PT(122) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) & + ENTRY_VALID_WATERMARKED(26) ) , STD_ULOGIC_VECTOR'("111111111111111111111111110")); +MQQ256:LRU_SET_RESET_VEC_PT(123) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) & ENTRY_VALID_WATERMARKED(25) + ) , STD_ULOGIC_VECTOR'("11111111111111111111111110")); +MQQ257:LRU_SET_RESET_VEC_PT(124) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(25) ) , STD_ULOGIC_VECTOR'("1111111111111111111111110")); +MQQ258:LRU_SET_RESET_VEC_PT(125) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) & + ENTRY_VALID_WATERMARKED(24) ) , STD_ULOGIC_VECTOR'("1111111111111111111111110")); +MQQ259:LRU_SET_RESET_VEC_PT(126) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) & ENTRY_VALID_WATERMARKED(23) + ) , STD_ULOGIC_VECTOR'("111111111111111111111110")); +MQQ260:LRU_SET_RESET_VEC_PT(127) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(23) ) , STD_ULOGIC_VECTOR'("11111111111111110")); +MQQ261:LRU_SET_RESET_VEC_PT(128) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) & + ENTRY_VALID_WATERMARKED(22) ) , STD_ULOGIC_VECTOR'("11111111111111111111110")); +MQQ262:LRU_SET_RESET_VEC_PT(129) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) & ENTRY_VALID_WATERMARKED(21) + ) , STD_ULOGIC_VECTOR'("1111111111111111111110")); +MQQ263:LRU_SET_RESET_VEC_PT(130) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(21) ) , STD_ULOGIC_VECTOR'("111111111111111111110")); +MQQ264:LRU_SET_RESET_VEC_PT(131) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) & + ENTRY_VALID_WATERMARKED(20) ) , STD_ULOGIC_VECTOR'("111111111111111111110")); +MQQ265:LRU_SET_RESET_VEC_PT(132) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) & ENTRY_VALID_WATERMARKED(19) + ) , STD_ULOGIC_VECTOR'("11111111111111111110")); +MQQ266:LRU_SET_RESET_VEC_PT(133) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(19) ) , STD_ULOGIC_VECTOR'("11111111111111110")); +MQQ267:LRU_SET_RESET_VEC_PT(134) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) & + ENTRY_VALID_WATERMARKED(18) ) , STD_ULOGIC_VECTOR'("1111111111111111110")); +MQQ268:LRU_SET_RESET_VEC_PT(135) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) & ENTRY_VALID_WATERMARKED(17) + ) , STD_ULOGIC_VECTOR'("111111111111111110")); +MQQ269:LRU_SET_RESET_VEC_PT(136) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(17) ) , STD_ULOGIC_VECTOR'("11111111111111110")); +MQQ270:LRU_SET_RESET_VEC_PT(137) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) & + ENTRY_VALID_WATERMARKED(16) ) , STD_ULOGIC_VECTOR'("11111111111111110")); +MQQ271:LRU_SET_RESET_VEC_PT(138) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) & ENTRY_VALID_WATERMARKED(15) + ) , STD_ULOGIC_VECTOR'("1111111111111110")); +MQQ272:LRU_SET_RESET_VEC_PT(139) <= + Eq(( ENTRY_VALID_WATERMARKED(15) ) , STD_ULOGIC'('0')); +MQQ273:LRU_SET_RESET_VEC_PT(140) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) & + ENTRY_VALID_WATERMARKED(14) ) , STD_ULOGIC_VECTOR'("111111111111110")); +MQQ274:LRU_SET_RESET_VEC_PT(141) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) & ENTRY_VALID_WATERMARKED(13) + ) , STD_ULOGIC_VECTOR'("11111111111110")); +MQQ275:LRU_SET_RESET_VEC_PT(142) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(13) ) , STD_ULOGIC_VECTOR'("1111111111110")); +MQQ276:LRU_SET_RESET_VEC_PT(143) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) & + ENTRY_VALID_WATERMARKED(12) ) , STD_ULOGIC_VECTOR'("1111111111110")); +MQQ277:LRU_SET_RESET_VEC_PT(144) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) & ENTRY_VALID_WATERMARKED(11) + ) , STD_ULOGIC_VECTOR'("111111111110")); +MQQ278:LRU_SET_RESET_VEC_PT(145) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(11) ) , STD_ULOGIC_VECTOR'("111111110")); +MQQ279:LRU_SET_RESET_VEC_PT(146) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) & + ENTRY_VALID_WATERMARKED(10) ) , STD_ULOGIC_VECTOR'("11111111110")); +MQQ280:LRU_SET_RESET_VEC_PT(147) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) & ENTRY_VALID_WATERMARKED(9) + ) , STD_ULOGIC_VECTOR'("1111111110")); +MQQ281:LRU_SET_RESET_VEC_PT(148) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(9) ) , STD_ULOGIC_VECTOR'("111111110")); +MQQ282:LRU_SET_RESET_VEC_PT(149) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) & + ENTRY_VALID_WATERMARKED(8) ) , STD_ULOGIC_VECTOR'("111111110")); +MQQ283:LRU_SET_RESET_VEC_PT(150) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) & ENTRY_VALID_WATERMARKED(7) + ) , STD_ULOGIC_VECTOR'("11111110")); +MQQ284:LRU_SET_RESET_VEC_PT(151) <= + Eq(( ENTRY_VALID_WATERMARKED(7) ) , STD_ULOGIC'('0')); +MQQ285:LRU_SET_RESET_VEC_PT(152) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) & + ENTRY_VALID_WATERMARKED(6) ) , STD_ULOGIC_VECTOR'("1111110")); +MQQ286:LRU_SET_RESET_VEC_PT(153) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) & ENTRY_VALID_WATERMARKED(5) + ) , STD_ULOGIC_VECTOR'("111110")); +MQQ287:LRU_SET_RESET_VEC_PT(154) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(5) ) , STD_ULOGIC_VECTOR'("11110")); +MQQ288:LRU_SET_RESET_VEC_PT(155) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) & + ENTRY_VALID_WATERMARKED(4) ) , STD_ULOGIC_VECTOR'("11110")); +MQQ289:LRU_SET_RESET_VEC_PT(156) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) & ENTRY_VALID_WATERMARKED(3) + ) , STD_ULOGIC_VECTOR'("1110")); +MQQ290:LRU_SET_RESET_VEC_PT(157) <= + Eq(( ENTRY_VALID_WATERMARKED(3) ) , STD_ULOGIC'('0')); +MQQ291:LRU_SET_RESET_VEC_PT(158) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) & + ENTRY_VALID_WATERMARKED(2) ) , STD_ULOGIC_VECTOR'("110")); +MQQ292:LRU_SET_RESET_VEC_PT(159) <= + Eq(( ENTRY_VALID_WATERMARKED(0) & ENTRY_VALID_WATERMARKED(1) + ) , STD_ULOGIC_VECTOR'("10")); +MQQ293:LRU_SET_RESET_VEC_PT(160) <= + Eq(( ENTRY_VALID_WATERMARKED(1) ) , STD_ULOGIC'('0')); +MQQ294:LRU_SET_RESET_VEC_PT(161) <= + Eq(( ENTRY_VALID_WATERMARKED(0) ) , STD_ULOGIC'('0')); +-- Table LRU_SET_RESET_VEC Signal Assignments for Outputs +MQQ295:LRU_RESET_VEC(1) <= + (LRU_SET_RESET_VEC_PT(1) OR LRU_SET_RESET_VEC_PT(2) + OR LRU_SET_RESET_VEC_PT(4) OR LRU_SET_RESET_VEC_PT(6) + OR LRU_SET_RESET_VEC_PT(7) OR LRU_SET_RESET_VEC_PT(9) + OR LRU_SET_RESET_VEC_PT(10) OR LRU_SET_RESET_VEC_PT(12) + OR LRU_SET_RESET_VEC_PT(13) OR LRU_SET_RESET_VEC_PT(15) + OR LRU_SET_RESET_VEC_PT(16) OR LRU_SET_RESET_VEC_PT(18) + OR LRU_SET_RESET_VEC_PT(19) OR LRU_SET_RESET_VEC_PT(21) + OR LRU_SET_RESET_VEC_PT(22) OR LRU_SET_RESET_VEC_PT(25) + OR LRU_SET_RESET_VEC_PT(114) OR LRU_SET_RESET_VEC_PT(139) + OR LRU_SET_RESET_VEC_PT(140) OR LRU_SET_RESET_VEC_PT(142) + OR LRU_SET_RESET_VEC_PT(143) OR LRU_SET_RESET_VEC_PT(145) + OR LRU_SET_RESET_VEC_PT(146) OR LRU_SET_RESET_VEC_PT(148) + OR LRU_SET_RESET_VEC_PT(149) OR LRU_SET_RESET_VEC_PT(151) + OR LRU_SET_RESET_VEC_PT(152) OR LRU_SET_RESET_VEC_PT(154) + OR LRU_SET_RESET_VEC_PT(155) OR LRU_SET_RESET_VEC_PT(157) + OR LRU_SET_RESET_VEC_PT(158) OR LRU_SET_RESET_VEC_PT(160) + OR LRU_SET_RESET_VEC_PT(161)); +MQQ296:LRU_RESET_VEC(2) <= + (LRU_SET_RESET_VEC_PT(26) OR LRU_SET_RESET_VEC_PT(28) + OR LRU_SET_RESET_VEC_PT(29) OR LRU_SET_RESET_VEC_PT(31) + OR LRU_SET_RESET_VEC_PT(32) OR LRU_SET_RESET_VEC_PT(34) + OR LRU_SET_RESET_VEC_PT(35) OR LRU_SET_RESET_VEC_PT(38) + OR LRU_SET_RESET_VEC_PT(112) OR LRU_SET_RESET_VEC_PT(151) + OR LRU_SET_RESET_VEC_PT(152) OR LRU_SET_RESET_VEC_PT(154) + OR LRU_SET_RESET_VEC_PT(155) OR LRU_SET_RESET_VEC_PT(157) + OR LRU_SET_RESET_VEC_PT(158) OR LRU_SET_RESET_VEC_PT(160) + OR LRU_SET_RESET_VEC_PT(161)); +MQQ297:LRU_RESET_VEC(3) <= + (LRU_SET_RESET_VEC_PT(1) OR LRU_SET_RESET_VEC_PT(2) + OR LRU_SET_RESET_VEC_PT(4) OR LRU_SET_RESET_VEC_PT(6) + OR LRU_SET_RESET_VEC_PT(7) OR LRU_SET_RESET_VEC_PT(9) + OR LRU_SET_RESET_VEC_PT(10) OR LRU_SET_RESET_VEC_PT(12) + OR LRU_SET_RESET_VEC_PT(110) OR LRU_SET_RESET_VEC_PT(127) + OR LRU_SET_RESET_VEC_PT(128) OR LRU_SET_RESET_VEC_PT(130) + OR LRU_SET_RESET_VEC_PT(131) OR LRU_SET_RESET_VEC_PT(133) + OR LRU_SET_RESET_VEC_PT(134) OR LRU_SET_RESET_VEC_PT(136) + OR LRU_SET_RESET_VEC_PT(137)); +MQQ298:LRU_RESET_VEC(4) <= + (LRU_SET_RESET_VEC_PT(39) OR LRU_SET_RESET_VEC_PT(41) + OR LRU_SET_RESET_VEC_PT(42) OR LRU_SET_RESET_VEC_PT(45) + OR LRU_SET_RESET_VEC_PT(108) OR LRU_SET_RESET_VEC_PT(157) + OR LRU_SET_RESET_VEC_PT(158) OR LRU_SET_RESET_VEC_PT(160) + OR LRU_SET_RESET_VEC_PT(161)); +MQQ299:LRU_RESET_VEC(5) <= + (LRU_SET_RESET_VEC_PT(26) OR LRU_SET_RESET_VEC_PT(28) + OR LRU_SET_RESET_VEC_PT(29) OR LRU_SET_RESET_VEC_PT(31) + OR LRU_SET_RESET_VEC_PT(106) OR LRU_SET_RESET_VEC_PT(145) + OR LRU_SET_RESET_VEC_PT(146) OR LRU_SET_RESET_VEC_PT(148) + OR LRU_SET_RESET_VEC_PT(149)); +MQQ300:LRU_RESET_VEC(6) <= + (LRU_SET_RESET_VEC_PT(13) OR LRU_SET_RESET_VEC_PT(15) + OR LRU_SET_RESET_VEC_PT(16) OR LRU_SET_RESET_VEC_PT(18) + OR LRU_SET_RESET_VEC_PT(104) OR LRU_SET_RESET_VEC_PT(133) + OR LRU_SET_RESET_VEC_PT(134) OR LRU_SET_RESET_VEC_PT(136) + OR LRU_SET_RESET_VEC_PT(137)); +MQQ301:LRU_RESET_VEC(7) <= + (LRU_SET_RESET_VEC_PT(1) OR LRU_SET_RESET_VEC_PT(2) + OR LRU_SET_RESET_VEC_PT(4) OR LRU_SET_RESET_VEC_PT(6) + OR LRU_SET_RESET_VEC_PT(102) OR LRU_SET_RESET_VEC_PT(121) + OR LRU_SET_RESET_VEC_PT(122) OR LRU_SET_RESET_VEC_PT(124) + OR LRU_SET_RESET_VEC_PT(125)); +MQQ302:LRU_RESET_VEC(8) <= + (LRU_SET_RESET_VEC_PT(46) OR LRU_SET_RESET_VEC_PT(49) + OR LRU_SET_RESET_VEC_PT(100) OR LRU_SET_RESET_VEC_PT(160) + OR LRU_SET_RESET_VEC_PT(161)); +MQQ303:LRU_RESET_VEC(9) <= + (LRU_SET_RESET_VEC_PT(39) OR LRU_SET_RESET_VEC_PT(41) + OR LRU_SET_RESET_VEC_PT(98) OR LRU_SET_RESET_VEC_PT(154) + OR LRU_SET_RESET_VEC_PT(155)); +MQQ304:LRU_RESET_VEC(10) <= + (LRU_SET_RESET_VEC_PT(32) OR LRU_SET_RESET_VEC_PT(34) + OR LRU_SET_RESET_VEC_PT(96) OR LRU_SET_RESET_VEC_PT(148) + OR LRU_SET_RESET_VEC_PT(149)); +MQQ305:LRU_RESET_VEC(11) <= + (LRU_SET_RESET_VEC_PT(26) OR LRU_SET_RESET_VEC_PT(28) + OR LRU_SET_RESET_VEC_PT(94) OR LRU_SET_RESET_VEC_PT(142) + OR LRU_SET_RESET_VEC_PT(143)); +MQQ306:LRU_RESET_VEC(12) <= + (LRU_SET_RESET_VEC_PT(19) OR LRU_SET_RESET_VEC_PT(21) + OR LRU_SET_RESET_VEC_PT(92) OR LRU_SET_RESET_VEC_PT(136) + OR LRU_SET_RESET_VEC_PT(137)); +MQQ307:LRU_RESET_VEC(13) <= + (LRU_SET_RESET_VEC_PT(13) OR LRU_SET_RESET_VEC_PT(15) + OR LRU_SET_RESET_VEC_PT(90) OR LRU_SET_RESET_VEC_PT(130) + OR LRU_SET_RESET_VEC_PT(131)); +MQQ308:LRU_RESET_VEC(14) <= + (LRU_SET_RESET_VEC_PT(7) OR LRU_SET_RESET_VEC_PT(9) + OR LRU_SET_RESET_VEC_PT(88) OR LRU_SET_RESET_VEC_PT(124) + OR LRU_SET_RESET_VEC_PT(125)); +MQQ309:LRU_RESET_VEC(15) <= + (LRU_SET_RESET_VEC_PT(1) OR LRU_SET_RESET_VEC_PT(2) + OR LRU_SET_RESET_VEC_PT(86) OR LRU_SET_RESET_VEC_PT(118) + OR LRU_SET_RESET_VEC_PT(119)); +MQQ310:LRU_RESET_VEC(16) <= + (LRU_SET_RESET_VEC_PT(50) OR LRU_SET_RESET_VEC_PT(84) + OR LRU_SET_RESET_VEC_PT(161)); +MQQ311:LRU_RESET_VEC(17) <= + (LRU_SET_RESET_VEC_PT(46) OR LRU_SET_RESET_VEC_PT(82) + OR LRU_SET_RESET_VEC_PT(158)); +MQQ312:LRU_RESET_VEC(18) <= + (LRU_SET_RESET_VEC_PT(42) OR LRU_SET_RESET_VEC_PT(80) + OR LRU_SET_RESET_VEC_PT(155)); +MQQ313:LRU_RESET_VEC(19) <= + (LRU_SET_RESET_VEC_PT(39) OR LRU_SET_RESET_VEC_PT(78) + OR LRU_SET_RESET_VEC_PT(152)); +MQQ314:LRU_RESET_VEC(20) <= + (LRU_SET_RESET_VEC_PT(35) OR LRU_SET_RESET_VEC_PT(76) + OR LRU_SET_RESET_VEC_PT(149)); +MQQ315:LRU_RESET_VEC(21) <= + (LRU_SET_RESET_VEC_PT(32) OR LRU_SET_RESET_VEC_PT(74) + OR LRU_SET_RESET_VEC_PT(146)); +MQQ316:LRU_RESET_VEC(22) <= + (LRU_SET_RESET_VEC_PT(29) OR LRU_SET_RESET_VEC_PT(72) + OR LRU_SET_RESET_VEC_PT(143)); +MQQ317:LRU_RESET_VEC(23) <= + (LRU_SET_RESET_VEC_PT(26) OR LRU_SET_RESET_VEC_PT(70) + OR LRU_SET_RESET_VEC_PT(140)); +MQQ318:LRU_RESET_VEC(24) <= + (LRU_SET_RESET_VEC_PT(22) OR LRU_SET_RESET_VEC_PT(68) + OR LRU_SET_RESET_VEC_PT(137)); +MQQ319:LRU_RESET_VEC(25) <= + (LRU_SET_RESET_VEC_PT(19) OR LRU_SET_RESET_VEC_PT(66) + OR LRU_SET_RESET_VEC_PT(134)); +MQQ320:LRU_RESET_VEC(26) <= + (LRU_SET_RESET_VEC_PT(16) OR LRU_SET_RESET_VEC_PT(64) + OR LRU_SET_RESET_VEC_PT(131)); +MQQ321:LRU_RESET_VEC(27) <= + (LRU_SET_RESET_VEC_PT(13) OR LRU_SET_RESET_VEC_PT(62) + OR LRU_SET_RESET_VEC_PT(128)); +MQQ322:LRU_RESET_VEC(28) <= + (LRU_SET_RESET_VEC_PT(10) OR LRU_SET_RESET_VEC_PT(60) + OR LRU_SET_RESET_VEC_PT(125)); +MQQ323:LRU_RESET_VEC(29) <= + (LRU_SET_RESET_VEC_PT(7) OR LRU_SET_RESET_VEC_PT(58) + OR LRU_SET_RESET_VEC_PT(122)); +MQQ324:LRU_RESET_VEC(30) <= + (LRU_SET_RESET_VEC_PT(4) OR LRU_SET_RESET_VEC_PT(56) + OR LRU_SET_RESET_VEC_PT(119)); +MQQ325:LRU_RESET_VEC(31) <= + (LRU_SET_RESET_VEC_PT(1) OR LRU_SET_RESET_VEC_PT(54) + OR LRU_SET_RESET_VEC_PT(116)); +MQQ326:LRU_SET_VEC(1) <= + (LRU_SET_RESET_VEC_PT(27) OR LRU_SET_RESET_VEC_PT(28) + OR LRU_SET_RESET_VEC_PT(30) OR LRU_SET_RESET_VEC_PT(31) + OR LRU_SET_RESET_VEC_PT(33) OR LRU_SET_RESET_VEC_PT(34) + OR LRU_SET_RESET_VEC_PT(36) OR LRU_SET_RESET_VEC_PT(37) + OR LRU_SET_RESET_VEC_PT(40) OR LRU_SET_RESET_VEC_PT(41) + OR LRU_SET_RESET_VEC_PT(43) OR LRU_SET_RESET_VEC_PT(44) + OR LRU_SET_RESET_VEC_PT(47) OR LRU_SET_RESET_VEC_PT(48) + OR LRU_SET_RESET_VEC_PT(51) OR LRU_SET_RESET_VEC_PT(52) + OR LRU_SET_RESET_VEC_PT(113) OR LRU_SET_RESET_VEC_PT(115) + OR LRU_SET_RESET_VEC_PT(116) OR LRU_SET_RESET_VEC_PT(117) + OR LRU_SET_RESET_VEC_PT(119) OR LRU_SET_RESET_VEC_PT(120) + OR LRU_SET_RESET_VEC_PT(122) OR LRU_SET_RESET_VEC_PT(123) + OR LRU_SET_RESET_VEC_PT(125) OR LRU_SET_RESET_VEC_PT(126) + OR LRU_SET_RESET_VEC_PT(128) OR LRU_SET_RESET_VEC_PT(129) + OR LRU_SET_RESET_VEC_PT(131) OR LRU_SET_RESET_VEC_PT(132) + OR LRU_SET_RESET_VEC_PT(134) OR LRU_SET_RESET_VEC_PT(135) + OR LRU_SET_RESET_VEC_PT(137)); +MQQ327:LRU_SET_VEC(2) <= + (LRU_SET_RESET_VEC_PT(40) OR LRU_SET_RESET_VEC_PT(41) + OR LRU_SET_RESET_VEC_PT(43) OR LRU_SET_RESET_VEC_PT(44) + OR LRU_SET_RESET_VEC_PT(47) OR LRU_SET_RESET_VEC_PT(48) + OR LRU_SET_RESET_VEC_PT(51) OR LRU_SET_RESET_VEC_PT(52) + OR LRU_SET_RESET_VEC_PT(111) OR LRU_SET_RESET_VEC_PT(138) + OR LRU_SET_RESET_VEC_PT(140) OR LRU_SET_RESET_VEC_PT(141) + OR LRU_SET_RESET_VEC_PT(143) OR LRU_SET_RESET_VEC_PT(144) + OR LRU_SET_RESET_VEC_PT(146) OR LRU_SET_RESET_VEC_PT(147) + OR LRU_SET_RESET_VEC_PT(149)); +MQQ328:LRU_SET_VEC(3) <= + (LRU_SET_RESET_VEC_PT(14) OR LRU_SET_RESET_VEC_PT(15) + OR LRU_SET_RESET_VEC_PT(17) OR LRU_SET_RESET_VEC_PT(18) + OR LRU_SET_RESET_VEC_PT(20) OR LRU_SET_RESET_VEC_PT(21) + OR LRU_SET_RESET_VEC_PT(23) OR LRU_SET_RESET_VEC_PT(24) + OR LRU_SET_RESET_VEC_PT(109) OR LRU_SET_RESET_VEC_PT(115) + OR LRU_SET_RESET_VEC_PT(116) OR LRU_SET_RESET_VEC_PT(117) + OR LRU_SET_RESET_VEC_PT(119) OR LRU_SET_RESET_VEC_PT(120) + OR LRU_SET_RESET_VEC_PT(122) OR LRU_SET_RESET_VEC_PT(123) + OR LRU_SET_RESET_VEC_PT(125)); +MQQ329:LRU_SET_VEC(4) <= + (LRU_SET_RESET_VEC_PT(47) OR LRU_SET_RESET_VEC_PT(48) + OR LRU_SET_RESET_VEC_PT(51) OR LRU_SET_RESET_VEC_PT(52) + OR LRU_SET_RESET_VEC_PT(107) OR LRU_SET_RESET_VEC_PT(150) + OR LRU_SET_RESET_VEC_PT(152) OR LRU_SET_RESET_VEC_PT(153) + OR LRU_SET_RESET_VEC_PT(155)); +MQQ330:LRU_SET_VEC(5) <= + (LRU_SET_RESET_VEC_PT(33) OR LRU_SET_RESET_VEC_PT(34) + OR LRU_SET_RESET_VEC_PT(36) OR LRU_SET_RESET_VEC_PT(37) + OR LRU_SET_RESET_VEC_PT(105) OR LRU_SET_RESET_VEC_PT(138) + OR LRU_SET_RESET_VEC_PT(140) OR LRU_SET_RESET_VEC_PT(141) + OR LRU_SET_RESET_VEC_PT(143)); +MQQ331:LRU_SET_VEC(6) <= + (LRU_SET_RESET_VEC_PT(20) OR LRU_SET_RESET_VEC_PT(21) + OR LRU_SET_RESET_VEC_PT(23) OR LRU_SET_RESET_VEC_PT(24) + OR LRU_SET_RESET_VEC_PT(103) OR LRU_SET_RESET_VEC_PT(126) + OR LRU_SET_RESET_VEC_PT(128) OR LRU_SET_RESET_VEC_PT(129) + OR LRU_SET_RESET_VEC_PT(131)); +MQQ332:LRU_SET_VEC(7) <= + (LRU_SET_RESET_VEC_PT(8) OR LRU_SET_RESET_VEC_PT(9) + OR LRU_SET_RESET_VEC_PT(11) OR LRU_SET_RESET_VEC_PT(12) + OR LRU_SET_RESET_VEC_PT(101) OR LRU_SET_RESET_VEC_PT(115) + OR LRU_SET_RESET_VEC_PT(116) OR LRU_SET_RESET_VEC_PT(117) + OR LRU_SET_RESET_VEC_PT(119)); +MQQ333:LRU_SET_VEC(8) <= + (LRU_SET_RESET_VEC_PT(51) OR LRU_SET_RESET_VEC_PT(52) + OR LRU_SET_RESET_VEC_PT(99) OR LRU_SET_RESET_VEC_PT(156) + OR LRU_SET_RESET_VEC_PT(158)); +MQQ334:LRU_SET_VEC(9) <= + (LRU_SET_RESET_VEC_PT(43) OR LRU_SET_RESET_VEC_PT(44) + OR LRU_SET_RESET_VEC_PT(97) OR LRU_SET_RESET_VEC_PT(150) + OR LRU_SET_RESET_VEC_PT(152)); +MQQ335:LRU_SET_VEC(10) <= + (LRU_SET_RESET_VEC_PT(36) OR LRU_SET_RESET_VEC_PT(37) + OR LRU_SET_RESET_VEC_PT(95) OR LRU_SET_RESET_VEC_PT(144) + OR LRU_SET_RESET_VEC_PT(146)); +MQQ336:LRU_SET_VEC(11) <= + (LRU_SET_RESET_VEC_PT(30) OR LRU_SET_RESET_VEC_PT(31) + OR LRU_SET_RESET_VEC_PT(93) OR LRU_SET_RESET_VEC_PT(138) + OR LRU_SET_RESET_VEC_PT(140)); +MQQ337:LRU_SET_VEC(12) <= + (LRU_SET_RESET_VEC_PT(23) OR LRU_SET_RESET_VEC_PT(24) + OR LRU_SET_RESET_VEC_PT(91) OR LRU_SET_RESET_VEC_PT(132) + OR LRU_SET_RESET_VEC_PT(134)); +MQQ338:LRU_SET_VEC(13) <= + (LRU_SET_RESET_VEC_PT(17) OR LRU_SET_RESET_VEC_PT(18) + OR LRU_SET_RESET_VEC_PT(89) OR LRU_SET_RESET_VEC_PT(126) + OR LRU_SET_RESET_VEC_PT(128)); +MQQ339:LRU_SET_VEC(14) <= + (LRU_SET_RESET_VEC_PT(11) OR LRU_SET_RESET_VEC_PT(12) + OR LRU_SET_RESET_VEC_PT(87) OR LRU_SET_RESET_VEC_PT(120) + OR LRU_SET_RESET_VEC_PT(122)); +MQQ340:LRU_SET_VEC(15) <= + (LRU_SET_RESET_VEC_PT(5) OR LRU_SET_RESET_VEC_PT(6) + OR LRU_SET_RESET_VEC_PT(85) OR LRU_SET_RESET_VEC_PT(115) + OR LRU_SET_RESET_VEC_PT(116)); +MQQ341:LRU_SET_VEC(16) <= + (LRU_SET_RESET_VEC_PT(52) OR LRU_SET_RESET_VEC_PT(83) + OR LRU_SET_RESET_VEC_PT(159)); +MQQ342:LRU_SET_VEC(17) <= + (LRU_SET_RESET_VEC_PT(48) OR LRU_SET_RESET_VEC_PT(81) + OR LRU_SET_RESET_VEC_PT(156)); +MQQ343:LRU_SET_VEC(18) <= + (LRU_SET_RESET_VEC_PT(44) OR LRU_SET_RESET_VEC_PT(79) + OR LRU_SET_RESET_VEC_PT(153)); +MQQ344:LRU_SET_VEC(19) <= + (LRU_SET_RESET_VEC_PT(41) OR LRU_SET_RESET_VEC_PT(77) + OR LRU_SET_RESET_VEC_PT(150)); +MQQ345:LRU_SET_VEC(20) <= + (LRU_SET_RESET_VEC_PT(37) OR LRU_SET_RESET_VEC_PT(75) + OR LRU_SET_RESET_VEC_PT(147)); +MQQ346:LRU_SET_VEC(21) <= + (LRU_SET_RESET_VEC_PT(34) OR LRU_SET_RESET_VEC_PT(73) + OR LRU_SET_RESET_VEC_PT(144)); +MQQ347:LRU_SET_VEC(22) <= + (LRU_SET_RESET_VEC_PT(31) OR LRU_SET_RESET_VEC_PT(71) + OR LRU_SET_RESET_VEC_PT(141)); +MQQ348:LRU_SET_VEC(23) <= + (LRU_SET_RESET_VEC_PT(28) OR LRU_SET_RESET_VEC_PT(69) + OR LRU_SET_RESET_VEC_PT(138)); +MQQ349:LRU_SET_VEC(24) <= + (LRU_SET_RESET_VEC_PT(24) OR LRU_SET_RESET_VEC_PT(67) + OR LRU_SET_RESET_VEC_PT(135)); +MQQ350:LRU_SET_VEC(25) <= + (LRU_SET_RESET_VEC_PT(21) OR LRU_SET_RESET_VEC_PT(65) + OR LRU_SET_RESET_VEC_PT(132)); +MQQ351:LRU_SET_VEC(26) <= + (LRU_SET_RESET_VEC_PT(18) OR LRU_SET_RESET_VEC_PT(63) + OR LRU_SET_RESET_VEC_PT(129)); +MQQ352:LRU_SET_VEC(27) <= + (LRU_SET_RESET_VEC_PT(15) OR LRU_SET_RESET_VEC_PT(61) + OR LRU_SET_RESET_VEC_PT(126)); +MQQ353:LRU_SET_VEC(28) <= + (LRU_SET_RESET_VEC_PT(12) OR LRU_SET_RESET_VEC_PT(59) + OR LRU_SET_RESET_VEC_PT(123)); +MQQ354:LRU_SET_VEC(29) <= + (LRU_SET_RESET_VEC_PT(9) OR LRU_SET_RESET_VEC_PT(57) + OR LRU_SET_RESET_VEC_PT(120)); +MQQ355:LRU_SET_VEC(30) <= + (LRU_SET_RESET_VEC_PT(6) OR LRU_SET_RESET_VEC_PT(55) + OR LRU_SET_RESET_VEC_PT(117)); +MQQ356:LRU_SET_VEC(31) <= + (LRU_SET_RESET_VEC_PT(3) OR LRU_SET_RESET_VEC_PT(53) + OR LRU_SET_RESET_VEC_PT(115)); + +-- Encoder for the LRU selected entry +-- +-- Final Table Listing +-- *INPUTS*=======================================*OUTPUTS*==========* +-- | | | +-- | mmucr1_q | lru_way_encode | +-- | | lru_eff | | | +-- | | | | | | +-- | | | | | | +-- | | | 1111111111222222222233 | | | +-- | 012345678 1234567890123456789012345678901 | 01234 | +-- *TYPE*=========================================+==================+ +-- | PPPPPPPPP PPPPPPPPPPPPPPPPPPPPPPPPPPPPPPP | PPPPP | +-- *POLARITY*------------------------------------>| +++++ | +-- *PHASE*--------------------------------------->| TTTTT | +-- *OPTIMIZE*------------------------------------>| AAAAA | +-- *TERMS*========================================+==================+ +-- 1 | --------- 1-1---1-------1---------------1 | ....1 | +-- 2 | --------- 1-1---1-------0--------------1- | ....1 | +-- 3 | --------- 1-1---0------1--------------1-- | ....1 | +-- 4 | --------- 1-1---0------0-------------1--- | ....1 | +-- 5 | --------- 1-0--1------1-------------1---- | ....1 | +-- 6 | --------- 1-0--1------0------------1----- | ....1 | +-- 7 | --------- 1-0--0-----1------------1------ | ....1 | +-- 8 | --------- 1-0--0-----0-----------1------- | ....1 | +-- 9 | --------- 01--1-----1-----------1-------- | ....1 | +-- 10 | --------- 01--1-----0----------1--------- | ....1 | +-- 11 | --------- 01--0----1----------1---------- | ....1 | +-- 12 | --------- 01--0----0---------1----------- | ....1 | +-- 13 | --------- 00-1----1---------1------------ | ....1 | +-- 14 | --------- 00-1----0--------1------------- | ....1 | +-- 15 | --------- 00-0---1--------1-------------- | ....1 | +-- 16 | --------- 00-0---0-------1--------------- | ....1 | +-- 17 | --------- 1-1---1-------1---------------- | ...1. | +-- 18 | --------- 1-1---0------1----------------- | ...1. | +-- 19 | --------- 1-0--1------1------------------ | ...1. | +-- 20 | --------- 1-0--0-----1------------------- | ...1. | +-- 21 | --------- 01--1-----1-------------------- | ...1. | +-- 22 | --------- 01--0----1--------------------- | ...1. | +-- 23 | --------- 00-1----1---------------------- | ...1. | +-- 24 | --------- 00-0---1----------------------- | ...1. | +-- 25 | --------- 1-1---1------------------------ | ..1.. | +-- 26 | --------- 1-0--1------------------------- | ..1.. | +-- 27 | --------- 01--1-------------------------- | ..1.. | +-- 28 | --------- 00-1--------------------------- | ..1.. | +-- 29 | --------- 1-1---------------------------- | .1... | +-- 30 | --------- 01----------------------------- | .1... | +-- 31 | --------- 1------------------------------ | 1.... | +-- *=================================================================* +-- +-- Table LRU_WAY_ENCODE Signal Assignments for Product Terms +MQQ357:LRU_WAY_ENCODE_PT(1) <= + Eq(( LRU_EFF(1) & LRU_EFF(3) & + LRU_EFF(7) & LRU_EFF(15) & + LRU_EFF(31) ) , STD_ULOGIC_VECTOR'("11111")); +MQQ358:LRU_WAY_ENCODE_PT(2) <= + Eq(( LRU_EFF(1) & LRU_EFF(3) & + LRU_EFF(7) & LRU_EFF(15) & + LRU_EFF(30) ) , STD_ULOGIC_VECTOR'("11101")); +MQQ359:LRU_WAY_ENCODE_PT(3) <= + Eq(( LRU_EFF(1) & LRU_EFF(3) & + LRU_EFF(7) & LRU_EFF(14) & + LRU_EFF(29) ) , STD_ULOGIC_VECTOR'("11011")); +MQQ360:LRU_WAY_ENCODE_PT(4) <= + Eq(( LRU_EFF(1) & LRU_EFF(3) & + LRU_EFF(7) & LRU_EFF(14) & + LRU_EFF(28) ) , STD_ULOGIC_VECTOR'("11001")); +MQQ361:LRU_WAY_ENCODE_PT(5) <= + Eq(( LRU_EFF(1) & LRU_EFF(3) & + LRU_EFF(6) & LRU_EFF(13) & + LRU_EFF(27) ) , STD_ULOGIC_VECTOR'("10111")); +MQQ362:LRU_WAY_ENCODE_PT(6) <= + Eq(( LRU_EFF(1) & LRU_EFF(3) & + LRU_EFF(6) & LRU_EFF(13) & + LRU_EFF(26) ) , STD_ULOGIC_VECTOR'("10101")); +MQQ363:LRU_WAY_ENCODE_PT(7) <= + Eq(( LRU_EFF(1) & LRU_EFF(3) & + LRU_EFF(6) & LRU_EFF(12) & + LRU_EFF(25) ) , STD_ULOGIC_VECTOR'("10011")); +MQQ364:LRU_WAY_ENCODE_PT(8) <= + Eq(( LRU_EFF(1) & LRU_EFF(3) & + LRU_EFF(6) & LRU_EFF(12) & + LRU_EFF(24) ) , STD_ULOGIC_VECTOR'("10001")); +MQQ365:LRU_WAY_ENCODE_PT(9) <= + Eq(( LRU_EFF(1) & LRU_EFF(2) & + LRU_EFF(5) & LRU_EFF(11) & + LRU_EFF(23) ) , STD_ULOGIC_VECTOR'("01111")); +MQQ366:LRU_WAY_ENCODE_PT(10) <= + Eq(( LRU_EFF(1) & LRU_EFF(2) & + LRU_EFF(5) & LRU_EFF(11) & + LRU_EFF(22) ) , STD_ULOGIC_VECTOR'("01101")); +MQQ367:LRU_WAY_ENCODE_PT(11) <= + Eq(( LRU_EFF(1) & LRU_EFF(2) & + LRU_EFF(5) & LRU_EFF(10) & + LRU_EFF(21) ) , STD_ULOGIC_VECTOR'("01011")); +MQQ368:LRU_WAY_ENCODE_PT(12) <= + Eq(( LRU_EFF(1) & LRU_EFF(2) & + LRU_EFF(5) & LRU_EFF(10) & + LRU_EFF(20) ) , STD_ULOGIC_VECTOR'("01001")); +MQQ369:LRU_WAY_ENCODE_PT(13) <= + Eq(( LRU_EFF(1) & LRU_EFF(2) & + LRU_EFF(4) & LRU_EFF(9) & + LRU_EFF(19) ) , STD_ULOGIC_VECTOR'("00111")); +MQQ370:LRU_WAY_ENCODE_PT(14) <= + Eq(( LRU_EFF(1) & LRU_EFF(2) & + LRU_EFF(4) & LRU_EFF(9) & + LRU_EFF(18) ) , STD_ULOGIC_VECTOR'("00101")); +MQQ371:LRU_WAY_ENCODE_PT(15) <= + Eq(( LRU_EFF(1) & LRU_EFF(2) & + LRU_EFF(4) & LRU_EFF(8) & + LRU_EFF(17) ) , STD_ULOGIC_VECTOR'("00011")); +MQQ372:LRU_WAY_ENCODE_PT(16) <= + Eq(( LRU_EFF(1) & LRU_EFF(2) & + LRU_EFF(4) & LRU_EFF(8) & + LRU_EFF(16) ) , STD_ULOGIC_VECTOR'("00001")); +MQQ373:LRU_WAY_ENCODE_PT(17) <= + Eq(( LRU_EFF(1) & LRU_EFF(3) & + LRU_EFF(7) & LRU_EFF(15) + ) , STD_ULOGIC_VECTOR'("1111")); +MQQ374:LRU_WAY_ENCODE_PT(18) <= + Eq(( LRU_EFF(1) & LRU_EFF(3) & + LRU_EFF(7) & LRU_EFF(14) + ) , STD_ULOGIC_VECTOR'("1101")); +MQQ375:LRU_WAY_ENCODE_PT(19) <= + Eq(( LRU_EFF(1) & LRU_EFF(3) & + LRU_EFF(6) & LRU_EFF(13) + ) , STD_ULOGIC_VECTOR'("1011")); +MQQ376:LRU_WAY_ENCODE_PT(20) <= + Eq(( LRU_EFF(1) & LRU_EFF(3) & + LRU_EFF(6) & LRU_EFF(12) + ) , STD_ULOGIC_VECTOR'("1001")); +MQQ377:LRU_WAY_ENCODE_PT(21) <= + Eq(( LRU_EFF(1) & LRU_EFF(2) & + LRU_EFF(5) & LRU_EFF(11) + ) , STD_ULOGIC_VECTOR'("0111")); +MQQ378:LRU_WAY_ENCODE_PT(22) <= + Eq(( LRU_EFF(1) & LRU_EFF(2) & + LRU_EFF(5) & LRU_EFF(10) + ) , STD_ULOGIC_VECTOR'("0101")); +MQQ379:LRU_WAY_ENCODE_PT(23) <= + Eq(( LRU_EFF(1) & LRU_EFF(2) & + LRU_EFF(4) & LRU_EFF(9) + ) , STD_ULOGIC_VECTOR'("0011")); +MQQ380:LRU_WAY_ENCODE_PT(24) <= + Eq(( LRU_EFF(1) & LRU_EFF(2) & + LRU_EFF(4) & LRU_EFF(8) + ) , STD_ULOGIC_VECTOR'("0001")); +MQQ381:LRU_WAY_ENCODE_PT(25) <= + Eq(( LRU_EFF(1) & LRU_EFF(3) & + LRU_EFF(7) ) , STD_ULOGIC_VECTOR'("111")); +MQQ382:LRU_WAY_ENCODE_PT(26) <= + Eq(( LRU_EFF(1) & LRU_EFF(3) & + LRU_EFF(6) ) , STD_ULOGIC_VECTOR'("101")); +MQQ383:LRU_WAY_ENCODE_PT(27) <= + Eq(( LRU_EFF(1) & LRU_EFF(2) & + LRU_EFF(5) ) , STD_ULOGIC_VECTOR'("011")); +MQQ384:LRU_WAY_ENCODE_PT(28) <= + Eq(( LRU_EFF(1) & LRU_EFF(2) & + LRU_EFF(4) ) , STD_ULOGIC_VECTOR'("001")); +MQQ385:LRU_WAY_ENCODE_PT(29) <= + Eq(( LRU_EFF(1) & LRU_EFF(3) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ386:LRU_WAY_ENCODE_PT(30) <= + Eq(( LRU_EFF(1) & LRU_EFF(2) + ) , STD_ULOGIC_VECTOR'("01")); +MQQ387:LRU_WAY_ENCODE_PT(31) <= + Eq(( LRU_EFF(1) ) , STD_ULOGIC'('1')); +-- Table LRU_WAY_ENCODE Signal Assignments for Outputs +MQQ388:LRU_WAY_ENCODE(0) <= + (LRU_WAY_ENCODE_PT(31)); +MQQ389:LRU_WAY_ENCODE(1) <= + (LRU_WAY_ENCODE_PT(29) OR LRU_WAY_ENCODE_PT(30) + ); +MQQ390:LRU_WAY_ENCODE(2) <= + (LRU_WAY_ENCODE_PT(25) OR LRU_WAY_ENCODE_PT(26) + OR LRU_WAY_ENCODE_PT(27) OR LRU_WAY_ENCODE_PT(28) + ); +MQQ391:LRU_WAY_ENCODE(3) <= + (LRU_WAY_ENCODE_PT(17) OR LRU_WAY_ENCODE_PT(18) + OR LRU_WAY_ENCODE_PT(19) OR LRU_WAY_ENCODE_PT(20) + OR LRU_WAY_ENCODE_PT(21) OR LRU_WAY_ENCODE_PT(22) + OR LRU_WAY_ENCODE_PT(23) OR LRU_WAY_ENCODE_PT(24) + ); +MQQ392:LRU_WAY_ENCODE(4) <= + (LRU_WAY_ENCODE_PT(1) OR LRU_WAY_ENCODE_PT(2) + OR LRU_WAY_ENCODE_PT(3) OR LRU_WAY_ENCODE_PT(4) + OR LRU_WAY_ENCODE_PT(5) OR LRU_WAY_ENCODE_PT(6) + OR LRU_WAY_ENCODE_PT(7) OR LRU_WAY_ENCODE_PT(8) + OR LRU_WAY_ENCODE_PT(9) OR LRU_WAY_ENCODE_PT(10) + OR LRU_WAY_ENCODE_PT(11) OR LRU_WAY_ENCODE_PT(12) + OR LRU_WAY_ENCODE_PT(13) OR LRU_WAY_ENCODE_PT(14) + OR LRU_WAY_ENCODE_PT(15) OR LRU_WAY_ENCODE_PT(16) + ); + +-- power-on reset sequencer to load initial erat entries +Por_Sequencer: PROCESS (por_seq_q, init_alias, bcfg_q(0 to 106)) +BEGIN +por_wr_cam_val <= (others => '0'); +por_wr_array_val <= (others => '0'); +por_wr_cam_data <= (others => '0'); +por_wr_array_data <= (others => '0'); +por_wr_entry <= (others => '0'); +CASE por_seq_q IS + WHEN PorSeq_Idle => + por_wr_cam_val <= (others => '0'); por_wr_array_val <= (others => '0'); + por_hold_req <= (others => init_alias); + + if init_alias ='1' then + por_seq_d <= PorSeq_Stg1; + else + por_seq_d <= PorSeq_Idle; + end if; + WHEN PorSeq_Stg1 => + por_wr_cam_val <= (others => '0'); por_wr_array_val <= (others => '0'); + por_seq_d <= PorSeq_Stg2; por_hold_req <= (others => '1'); + + WHEN PorSeq_Stg2 => + por_wr_cam_val <= (others => '1'); por_wr_array_val <= (others => '1'); + por_wr_entry <= Por_Wr_Entry_Num1; + por_wr_cam_data <= bcfg_q(0 to 51) & Por_Wr_Cam_Data1(52 to 83); +-- 16x143 version, 42b RA +-- wr_array_data +-- 0:29 - RPN +-- 30:31 - R,C +-- 32:35 - ResvAttr +-- 36:39 - U0-U3 +-- 40:44 - WIMGE +-- 45:46 - UX,SX +-- 47:48 - UW,SW +-- 49:50 - UR,SR +-- 51:60 - CAM parity +-- 61:67 - Array parity + por_wr_array_data <= bcfg_q(52 to 81) & Por_Wr_Array_Data1(30 to 35) & bcfg_q(82 to 85) & + Por_Wr_Array_Data1(40 to 43) & bcfg_q(86) & Por_Wr_Array_Data1(45 to 67); + por_hold_req <= (others => '1'); + por_seq_d <= PorSeq_Stg3; + + WHEN PorSeq_Stg3 => + por_wr_cam_val <= (others => '0'); por_wr_array_val <= (others => '0'); + por_hold_req <= (others => '1'); + por_seq_d <= PorSeq_Stg4; + + WHEN PorSeq_Stg4 => + por_wr_cam_val <= (others => '1'); por_wr_array_val <= (others => '1'); + por_wr_entry <= Por_Wr_Entry_Num2; + por_wr_cam_data <= Por_Wr_Cam_Data2; + por_wr_array_data <= bcfg_q(52 to 61) & bcfg_q(87 to 106) & Por_Wr_Array_Data2(30 to 35) & bcfg_q(82 to 85) & + Por_Wr_Array_Data2(40 to 43) & bcfg_q(86) & Por_Wr_Array_Data2(45 to 67); + por_hold_req <= (others => '1'); + por_seq_d <= PorSeq_Stg5; + + WHEN PorSeq_Stg5 => + por_wr_cam_val <= (others => '0'); por_wr_array_val <= (others => '0'); + por_hold_req <= (others => '1'); + por_seq_d <= PorSeq_Stg6; + + WHEN PorSeq_Stg6 => + por_wr_cam_val <= (others => '0'); por_wr_array_val <= (others => '0'); + por_hold_req <= (others => '0'); + por_seq_d <= PorSeq_Stg7; + + WHEN PorSeq_Stg7 => + por_wr_cam_val <= (others => '0'); por_wr_array_val <= (others => '0'); + por_hold_req <= (others => '0'); + if init_alias ='0' then + por_seq_d <= PorSeq_Idle; + else + por_seq_d <= PorSeq_Stg7; + end if; + + WHEN OTHERS => + por_seq_d <= PorSeq_Idle; + END CASE; +END PROCESS Por_Sequencer; +-- page size 4b to 3b swizzles for cam write +cam_pgsize(0 TO 2) <= (CAM_PgSize_1GB and (0 to 2 => Eq(ex6_data_in_q(56 to 59),WS0_PgSize_1GB))) + or (CAM_PgSize_16MB and (0 to 2 => Eq(ex6_data_in_q(56 to 59),WS0_PgSize_16MB))) + or (CAM_PgSize_1MB and (0 to 2 => Eq(ex6_data_in_q(56 to 59),WS0_PgSize_1MB))) + or (CAM_PgSize_64KB and (0 to 2 => Eq(ex6_data_in_q(56 to 59),WS0_PgSize_64KB))) + or (CAM_PgSize_4KB and (0 to 2 => not(Eq(ex6_data_in_q(56 to 59),WS0_PgSize_1GB) or + Eq(ex6_data_in_q(56 to 59),WS0_PgSize_16MB) or + Eq(ex6_data_in_q(56 to 59),WS0_PgSize_1MB) or + Eq(ex6_data_in_q(56 to 59),WS0_PgSize_64KB)))); +-- page size 3b to 4b swizzles for cam read +ws0_pgsize(0 TO 3) <= (WS0_PgSize_1GB and (0 to 3 => Eq(rd_cam_data(53 to 55),CAM_PgSize_1GB))) + or (WS0_PgSize_16MB and (0 to 3 => Eq(rd_cam_data(53 to 55),CAM_PgSize_16MB))) + or (WS0_PgSize_1MB and (0 to 3 => Eq(rd_cam_data(53 to 55),CAM_PgSize_1MB))) + or (WS0_PgSize_64KB and (0 to 3 => Eq(rd_cam_data(53 to 55),CAM_PgSize_64KB))) + or (WS0_PgSize_4KB and (0 to 3 => Eq(rd_cam_data(53 to 55),CAM_PgSize_4KB))); +-- CAM control signal assignments +rd_val <= or_reduce(ex2_valid_q) and ex2_ttype_q(0) and Eq(ex2_tlbsel_q, TlbSel_DErat); +rw_entry <= ( por_wr_entry and (0 to 4 => or_reduce(por_seq_q)) ) + or ( eptr_q and (0 to 4 => (or_reduce(tlb_rel_val_q(0 to 3)) and tlb_rel_val_q(4) and mmucr1_q(0))) ) + or ( lru_way_encode and (0 to 4 => (or_reduce(tlb_rel_val_q(0 to 3)) and tlb_rel_val_q(4) and not mmucr1_q(0))) ) + or ( eptr_q and (0 to 4 => (or_reduce(ex6_valid_q) and ex6_ttype_q(1) and Eq(ex6_tlbsel_q, TlbSel_DErat) and not tlb_rel_val_q(4) and mmucr1_q(0))) ) + or ( ex6_ra_entry_q and (0 to 4 => (or_reduce(ex6_valid_q) and ex6_ttype_q(1) and Eq(ex6_tlbsel_q, TlbSel_DErat) and not tlb_rel_val_q(4) and not mmucr1_q(0))) ) + or ( ex2_ra_entry_q and (0 to 4 => (or_reduce(ex2_valid_q) and ex2_ttype_q(0) and not(or_reduce(ex6_valid_q) and ex6_ttype_q(1) and Eq(ex6_tlbsel_q, TlbSel_DErat)) and not tlb_rel_val_q(4))) ); +-- Write Port +wr_cam_val <= por_wr_cam_val when por_seq_q/=PorSeq_Idle + else (others => '0') when (ex6_valid_q/="0000" and ex6_ttype_q(6 to 7)/="00") + else (others => tlb_rel_data_q(eratpos_wren)) when (tlb_rel_val_q(0 to 3)/="0000" and tlb_rel_val_q(4)='1') + else (others => '1') when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' and ex6_ws_q="00" and ex6_tlbsel_q=TlbSel_DErat) + else (others => '0'); +-- write port act pin +wr_val_early <= or_reduce(por_seq_q) or + or_reduce(tlb_req_inprogress_q) or + (or_reduce(ex5_valid_q) and ex5_ttype_q(1) and Eq(ex5_ws_q,"00") and Eq(ex5_tlbsel_q,TlbSel_DErat)) or + (or_reduce(ex6_valid_q) and ex6_ttype_q(1) and Eq(ex6_ws_q,"00") and Eq(ex6_tlbsel_q,TlbSel_DErat)); +-- state <= PR & GS or mmucr0(8) & IS or mmucr0(9) & CM +-- tlb_low_data +-- 0:51 - EPN +-- 52:55 - SIZE (4b) +-- 56:59 - ThdID +-- 60:61 - Class +-- 62 - ExtClass +-- 63 - TID_NZ +-- 64:65 - reserved (2b) +-- 66:73 - 8b for LPID +-- 74:83 - parity 10bits +-- wr_ws0_data (LO) +-- 0:51 - EPN +-- 52:53 - Class +-- 54 - V +-- 55 - X +-- 56:59 - SIZE +-- 60:63 - ThdID +-- wr_cam_data +-- 0:51 - EPN +-- 52 - X +-- 53:55 - SIZE +-- 56 - V +-- 57:60 - ThdID +-- 61:62 - Class +-- 63:64 - ExtClass | TID_NZ +-- 65 - TGS +-- 66 - TS +-- 67:74 - TID +-- 75:78 - epn_cmpmasks: 34_39, 40_43, 44_47, 48_51 +-- 79:82 - xbit_cmpmasks: 34_51, 40_51, 44_51, 48_51 +-- 83 - parity for 75:82 +----------- this is what the erat expects on reload bus +-- 0:51 - EPN +-- 52 - X +-- 53:55 - SIZE +-- 56 - V +-- 57:60 - ThdID +-- 61:62 - Class +-- 63:64 - ExtClass | TID_NZ +-- 65 - write enable +-- 0:3 66:69 - reserved RPN +-- 4:33 70:99 - RPN +-- 34:35 100:101 - R,C +-- 36 102 - reserved +-- 37:38 103:104 - WLC +-- 39 105 - ResvAttr +-- 40 106 - VF +-- 41:44 107:110 - U0-U3 +-- 45:49 111:115 - WIMGE +-- 50:51 116:117 - UX,SX +-- 52:53 118:119 - UW,SW +-- 54:55 120:121 - UR,SR +-- 56 122 - GS +-- 57 123 - TS +-- 58:65 124:131 - TID lsbs +gen64_wr_cam_data: if rs_data_width = 64 generate +wr_cam_data <= ( por_wr_cam_data and (0 to 83 => (por_seq_q(0) or por_seq_q(1) or por_seq_q(2))) ) + or ( (tlb_rel_data_q(0 to 64) & tlb_rel_data_q(122 to 131) & + tlb_rel_cmpmask(0 to 3) & tlb_rel_xbitmask(0 to 3) & tlb_rel_maskpar) + and (0 to 83 => ((tlb_rel_val_q(0) or tlb_rel_val_q(1) or tlb_rel_val_q(2) or tlb_rel_val_q(3)) and tlb_rel_val_q(4))) ) + or ( ((ex6_data_in_q(0 to 31) and (0 to 31 => ex6_state_q(3))) & ex6_data_in_q(32 to 51) & ex6_data_in_q(55) & + cam_pgsize(0 to 2) & ex6_data_in_q(54) & ex6_data_in_q(60 to 63) & ex6_data_in_q(52 to 53) & + ex6_extclass_q & ex6_state_q(1 to 2) & ex6_pid_q(pid_width-8 to pid_width-1) & + ex6_data_cmpmask(0 to 3) & ex6_data_xbitmask(0 to 3) & ex6_data_maskpar) + and (0 to 83 => ((ex6_valid_q(0) or ex6_valid_q(1) or ex6_valid_q(2) or ex6_valid_q(3)) + and ex6_ttype_q(1) and not ex6_ws_q(0) and not ex6_ws_q(1) and not tlb_rel_val_q(4))) ); +end generate gen64_wr_cam_data; +gen32_wr_cam_data: if rs_data_width = 32 generate +wr_cam_data <= ( por_wr_cam_data and (0 to 83 => (por_seq_q(0) or por_seq_q(1) or por_seq_q(2))) ) + or ( (tlb_rel_data_q(0 to 64) & tlb_rel_data_q(122 to 131) & + tlb_rel_cmpmask(0 to 3) & tlb_rel_xbitmask(0 to 3) & tlb_rel_maskpar) + and (0 to 83 => ((tlb_rel_val_q(0) or tlb_rel_val_q(1) or tlb_rel_val_q(2) or tlb_rel_val_q(3)) and tlb_rel_val_q(4))) ) + or ( ((0 to 31 => '0') & ex6_data_in_q(32 to 51) & ex6_data_in_q(55) & cam_pgsize(0 to 2) & ex6_data_in_q(54) & + ex6_data_in_q(60 to 63) & ex6_data_in_q(52 to 53) & + ex6_extclass_q & ex6_state_q(1 to 2) & ex6_pid_q(pid_width-8 to pid_width-1) & + ex6_data_cmpmask(0 to 3) & ex6_data_xbitmask(0 to 3) & ex6_data_maskpar) + and (0 to 83 => ((ex6_valid_q(0) or ex6_valid_q(1) or ex6_valid_q(2) or ex6_valid_q(3)) + and ex6_ttype_q(1) and not ex6_ws_q(0) and not ex6_ws_q(1) and not tlb_rel_val_q(4))) ); +end generate gen32_wr_cam_data; +-- wr_cam_data(75) (76) (77) (78) (79) (80) (81) (82) +-- cmpmask(0) (1) (2) (3) xbitmask(0) (1) (2) (3) +-- xbit pgsize 34_39 40_43 44_47 48_51 34_39 40_43 44_47 48_51 size +-- 0 001 1 1 1 1 0 0 0 0 4K +-- 0 011 1 1 1 0 0 0 0 0 64K +-- 0 101 1 1 0 0 0 0 0 0 1M +-- 0 111 1 0 0 0 0 0 0 0 16M +-- 0 110 0 0 0 0 0 0 0 0 1G +-- 1 001 1 1 1 1 0 0 0 0 4K +-- 1 011 1 1 1 0 0 0 0 1 64K +-- 1 101 1 1 0 0 0 0 1 0 1M +-- 1 111 1 0 0 0 0 1 0 0 16M +-- 1 110 0 0 0 0 1 0 0 0 1G +-- Encoder for the cam compare mask bits write data +-- +-- Final Table Listing +-- *INPUTS*==================*OUTPUTS*===================================* +-- | | | +-- | tlb_rel_data_q | tlb_rel_cmpmask | +-- | | ex6_data_in_q | | tlb_rel_xbitmask | +-- | | | | | | tlb_rel_maskpar | +-- | | | | | | | ex6_data_cmpmask | +-- | | | | | | | | ex6_data_xbitmask | +-- | | | | | | | | | ex6_data_maskpar | +-- | | | | | | | | | | | +-- | 5555 55555 | | | | | | | | +-- | 2345 56789 | 0123 0123 | 0123 0123 | | +-- *TYPE*====================+===========================================+ +-- | PPPP PPPPP | PPPP PPPP P PPPP PPPP P | +-- *POLARITY*--------------->| ++++ ++++ + ++++ ++++ + | +-- *PHASE*------------------>| TTTT TTTT T TTTT TTTT T | +-- *OPTIMIZE*--------------->| AAAA AAAA A AAAA AAAA A | +-- *TERMS*===================+===========================================+ +-- 1 | ---- 11010 | .... .... . .... 1... 1 | +-- 2 | ---- -0--0 | .... .... . 1111 .... . | +-- 3 | ---- 10101 | .... .... . .... ..1. 1 | +-- 4 | ---- 10011 | .... .... . 1... ...1 . | +-- 5 | ---- 10111 | .... .... . 1... .1.. . | +-- 6 | ---- 00-11 | .... .... . 1... .... 1 | +-- 7 | ---- -1--1 | .... .... . 1111 .... . | +-- 8 | ---- --00- | .... .... . ..11 .... . | +-- 9 | ---- ---0- | .... .... . 11.. .... . | +-- 10 | ---- -00-- | .... .... . .11. .... . | +-- 11 | ---- -11-- | .... .... . 1111 .... . | +-- 12 | 1--0 ----- | .... 1... 1 .... .... . | +-- 13 | 1111 ----- | 1... .1.. . .... .... . | +-- 14 | 0-11 ----- | 1... .... 1 .... .... . | +-- 15 | -00- ----- | ...1 .... . .... .... . | +-- 16 | 110- ----- | .... ..1. 1 .... .... . | +-- 17 | --0- ----- | 11.. .... . .... .... . | +-- 18 | 101- ----- | 1... ...1 . .... .... . | +-- 19 | -0-- ----- | .11. .... . .... .... . | +-- *=====================================================================* +-- +-- Table CAM_MASK_BITS Signal Assignments for Product Terms +MQQ393:CAM_MASK_BITS_PT(1) <= + Eq(( EX6_DATA_IN_Q(55) & EX6_DATA_IN_Q(56) & + EX6_DATA_IN_Q(57) & EX6_DATA_IN_Q(58) & + EX6_DATA_IN_Q(59) ) , STD_ULOGIC_VECTOR'("11010")); +MQQ394:CAM_MASK_BITS_PT(2) <= + Eq(( EX6_DATA_IN_Q(56) & EX6_DATA_IN_Q(59) + ) , STD_ULOGIC_VECTOR'("00")); +MQQ395:CAM_MASK_BITS_PT(3) <= + Eq(( EX6_DATA_IN_Q(55) & EX6_DATA_IN_Q(56) & + EX6_DATA_IN_Q(57) & EX6_DATA_IN_Q(58) & + EX6_DATA_IN_Q(59) ) , STD_ULOGIC_VECTOR'("10101")); +MQQ396:CAM_MASK_BITS_PT(4) <= + Eq(( EX6_DATA_IN_Q(55) & EX6_DATA_IN_Q(56) & + EX6_DATA_IN_Q(57) & EX6_DATA_IN_Q(58) & + EX6_DATA_IN_Q(59) ) , STD_ULOGIC_VECTOR'("10011")); +MQQ397:CAM_MASK_BITS_PT(5) <= + Eq(( EX6_DATA_IN_Q(55) & EX6_DATA_IN_Q(56) & + EX6_DATA_IN_Q(57) & EX6_DATA_IN_Q(58) & + EX6_DATA_IN_Q(59) ) , STD_ULOGIC_VECTOR'("10111")); +MQQ398:CAM_MASK_BITS_PT(6) <= + Eq(( EX6_DATA_IN_Q(55) & EX6_DATA_IN_Q(56) & + EX6_DATA_IN_Q(58) & EX6_DATA_IN_Q(59) + ) , STD_ULOGIC_VECTOR'("0011")); +MQQ399:CAM_MASK_BITS_PT(7) <= + Eq(( EX6_DATA_IN_Q(56) & EX6_DATA_IN_Q(59) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ400:CAM_MASK_BITS_PT(8) <= + Eq(( EX6_DATA_IN_Q(57) & EX6_DATA_IN_Q(58) + ) , STD_ULOGIC_VECTOR'("00")); +MQQ401:CAM_MASK_BITS_PT(9) <= + Eq(( EX6_DATA_IN_Q(58) ) , STD_ULOGIC'('0')); +MQQ402:CAM_MASK_BITS_PT(10) <= + Eq(( EX6_DATA_IN_Q(56) & EX6_DATA_IN_Q(57) + ) , STD_ULOGIC_VECTOR'("00")); +MQQ403:CAM_MASK_BITS_PT(11) <= + Eq(( EX6_DATA_IN_Q(56) & EX6_DATA_IN_Q(57) + ) , STD_ULOGIC_VECTOR'("11")); +MQQ404:CAM_MASK_BITS_PT(12) <= + Eq(( TLB_REL_DATA_Q(52) & TLB_REL_DATA_Q(55) + ) , STD_ULOGIC_VECTOR'("10")); +MQQ405:CAM_MASK_BITS_PT(13) <= + Eq(( TLB_REL_DATA_Q(52) & TLB_REL_DATA_Q(53) & + TLB_REL_DATA_Q(54) & TLB_REL_DATA_Q(55) + ) , STD_ULOGIC_VECTOR'("1111")); +MQQ406:CAM_MASK_BITS_PT(14) <= + Eq(( TLB_REL_DATA_Q(52) & TLB_REL_DATA_Q(54) & + TLB_REL_DATA_Q(55) ) , STD_ULOGIC_VECTOR'("011")); +MQQ407:CAM_MASK_BITS_PT(15) <= + Eq(( TLB_REL_DATA_Q(53) & TLB_REL_DATA_Q(54) + ) , STD_ULOGIC_VECTOR'("00")); +MQQ408:CAM_MASK_BITS_PT(16) <= + Eq(( TLB_REL_DATA_Q(52) & TLB_REL_DATA_Q(53) & + TLB_REL_DATA_Q(54) ) , STD_ULOGIC_VECTOR'("110")); +MQQ409:CAM_MASK_BITS_PT(17) <= + Eq(( TLB_REL_DATA_Q(54) ) , STD_ULOGIC'('0')); +MQQ410:CAM_MASK_BITS_PT(18) <= + Eq(( TLB_REL_DATA_Q(52) & TLB_REL_DATA_Q(53) & + TLB_REL_DATA_Q(54) ) , STD_ULOGIC_VECTOR'("101")); +MQQ411:CAM_MASK_BITS_PT(19) <= + Eq(( TLB_REL_DATA_Q(53) ) , STD_ULOGIC'('0')); +-- Table CAM_MASK_BITS Signal Assignments for Outputs +MQQ412:TLB_REL_CMPMASK(0) <= + (CAM_MASK_BITS_PT(13) OR CAM_MASK_BITS_PT(14) + OR CAM_MASK_BITS_PT(17) OR CAM_MASK_BITS_PT(18) + ); +MQQ413:TLB_REL_CMPMASK(1) <= + (CAM_MASK_BITS_PT(17) OR CAM_MASK_BITS_PT(19) + ); +MQQ414:TLB_REL_CMPMASK(2) <= + (CAM_MASK_BITS_PT(19)); +MQQ415:TLB_REL_CMPMASK(3) <= + (CAM_MASK_BITS_PT(15)); +MQQ416:TLB_REL_XBITMASK(0) <= + (CAM_MASK_BITS_PT(12)); +MQQ417:TLB_REL_XBITMASK(1) <= + (CAM_MASK_BITS_PT(13)); +MQQ418:TLB_REL_XBITMASK(2) <= + (CAM_MASK_BITS_PT(16)); +MQQ419:TLB_REL_XBITMASK(3) <= + (CAM_MASK_BITS_PT(18)); +MQQ420:TLB_REL_MASKPAR <= + (CAM_MASK_BITS_PT(12) OR CAM_MASK_BITS_PT(14) + OR CAM_MASK_BITS_PT(16)); +MQQ421:EX6_DATA_CMPMASK(0) <= + (CAM_MASK_BITS_PT(2) OR CAM_MASK_BITS_PT(4) + OR CAM_MASK_BITS_PT(5) OR CAM_MASK_BITS_PT(6) + OR CAM_MASK_BITS_PT(7) OR CAM_MASK_BITS_PT(9) + OR CAM_MASK_BITS_PT(11)); +MQQ422:EX6_DATA_CMPMASK(1) <= + (CAM_MASK_BITS_PT(2) OR CAM_MASK_BITS_PT(7) + OR CAM_MASK_BITS_PT(9) OR CAM_MASK_BITS_PT(10) + OR CAM_MASK_BITS_PT(11)); +MQQ423:EX6_DATA_CMPMASK(2) <= + (CAM_MASK_BITS_PT(2) OR CAM_MASK_BITS_PT(7) + OR CAM_MASK_BITS_PT(8) OR CAM_MASK_BITS_PT(10) + OR CAM_MASK_BITS_PT(11)); +MQQ424:EX6_DATA_CMPMASK(3) <= + (CAM_MASK_BITS_PT(2) OR CAM_MASK_BITS_PT(7) + OR CAM_MASK_BITS_PT(8) OR CAM_MASK_BITS_PT(11) + ); +MQQ425:EX6_DATA_XBITMASK(0) <= + (CAM_MASK_BITS_PT(1)); +MQQ426:EX6_DATA_XBITMASK(1) <= + (CAM_MASK_BITS_PT(5)); +MQQ427:EX6_DATA_XBITMASK(2) <= + (CAM_MASK_BITS_PT(3)); +MQQ428:EX6_DATA_XBITMASK(3) <= + (CAM_MASK_BITS_PT(4)); +MQQ429:EX6_DATA_MASKPAR <= + (CAM_MASK_BITS_PT(1) OR CAM_MASK_BITS_PT(3) + OR CAM_MASK_BITS_PT(6)); + +wr_array_val <= por_wr_array_val when por_seq_q/=PorSeq_Idle + else (others => '0') when (ex6_valid_q/="0000" and ex6_ttype_q(6 to 7)/="00") + else (others => tlb_rel_data_q(eratpos_wren)) + when (tlb_rel_val_q(0 to 3)/="0000" and tlb_rel_val_q(4)='1') + else (others => '1') when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_ws_q="00" and ex6_tlbsel_q=TlbSel_DErat) + else (others => '0'); +-- tlb_high_data +-- 84 - 0 - X-bit +-- 85:87 - 1:3 - reserved (3b) +-- 88:117 - 4:33 - RPN (30b) +-- 118:119 - 34:35 - R,C +-- 120:121 - 36:37 - WLC (2b) +-- 122 - 38 - ResvAttr +-- 123 - 39 - VF +-- 124 - 40 - IND +-- 125:128 - 41:44 - U0-U3 +-- 129:133 - 45:49 - WIMGE +-- 134:136 - 50:52 - UX,UW,UR +-- 137:139 - 53:55 - SX,SW,SR +-- 140 - 56 - GS +-- 141 - 57 - TS +-- 142:143 - 58:59 - reserved (2b) +-- 144:149 - 60:65 - 6b TID msbs +-- 150:157 - 66:73 - 8b TID lsbs +-- 158:167 - 74:83 - parity 10bits +-- 16x143 version, 42b RA +-- wr_array_data +-- 0:29 - RPN +-- 30:31 - R,C +-- 32:35 - ResvAttr +-- 36:39 - U0-U3 +-- 40:44 - WIMGE +-- 45:46 - UX,SX +-- 47:48 - UW,SW +-- 49:50 - UR,SR +-- 51:60 - CAM parity +-- 61:67 - Array parity +-- wr_ws1_data (HI) +-- 0:7 - unused +-- 8:9 - WLC +-- 10 - ResvAttr +-- 11 - unused +-- 12:15 - U0-U3 +-- 16:17 - R,C +-- 18:21 - unused +-- 22:51 - RPN +-- 52:56 - WIMGE +-- 57 - VF +-- 58:59 - UX,SX +-- 60:61 - UW,SW +-- 62:63 - UR,SR +wr_array_data_nopar <= ( por_wr_array_data(0 to 50) and (0 to 50 => (por_seq_q(0) or por_seq_q(1) or por_seq_q(2))) ) + or ( (tlb_rel_data_q(70 to 101) & tlb_rel_data_q(103 to 121)) + and (0 to 50 => ((tlb_rel_val_q(0) or tlb_rel_val_q(1) or tlb_rel_val_q(2) or tlb_rel_val_q(3)) and tlb_rel_val_q(4))) ) + or ( (rpn_holdreg0_q(22 to 51) & rpn_holdreg0_q(16 to 17) & rpn_holdreg0_q(8 to 10) & rpn_holdreg0_q(57) & + rpn_holdreg0_q(12 to 15) & rpn_holdreg0_q(52 to 56) & rpn_holdreg0_q(58 to 63)) + and (0 to 50 => (ex6_valid_q(0) and ex6_ttype_q(1) and not ex6_ws_q(0) and not ex6_ws_q(1) and not tlb_rel_val_q(4))) ) + or ( (rpn_holdreg1_q(22 to 51) & rpn_holdreg1_q(16 to 17) & rpn_holdreg1_q(8 to 10) & rpn_holdreg1_q(57) & + rpn_holdreg1_q(12 to 15) & rpn_holdreg1_q(52 to 56) & rpn_holdreg1_q(58 to 63)) + and (0 to 50 => (ex6_valid_q(1) and ex6_ttype_q(1) and not ex6_ws_q(0) and not ex6_ws_q(1) and not tlb_rel_val_q(4))) ) + or ( (rpn_holdreg2_q(22 to 51) & rpn_holdreg2_q(16 to 17) & rpn_holdreg2_q(8 to 10) & rpn_holdreg2_q(57) & + rpn_holdreg2_q(12 to 15) & rpn_holdreg2_q(52 to 56) & rpn_holdreg2_q(58 to 63)) + and (0 to 50 => (ex6_valid_q(2) and ex6_ttype_q(1) and not ex6_ws_q(0) and not ex6_ws_q(1) and not tlb_rel_val_q(4))) ) + or ( (rpn_holdreg3_q(22 to 51) & rpn_holdreg3_q(16 to 17) & rpn_holdreg3_q(8 to 10) & rpn_holdreg3_q(57) & + rpn_holdreg3_q(12 to 15) & rpn_holdreg3_q(52 to 56) & rpn_holdreg3_q(58 to 63)) + and (0 to 50 => (ex6_valid_q(3) and ex6_ttype_q(1) and not ex6_ws_q(0) and not ex6_ws_q(1) and not tlb_rel_val_q(4))) ); +wr_array_par(51) <= xor_reduce(wr_cam_data(0 to 7)); +wr_array_par(52) <= xor_reduce(wr_cam_data(8 to 15)); +wr_array_par(53) <= xor_reduce(wr_cam_data(16 to 23)); +wr_array_par(54) <= xor_reduce(wr_cam_data(24 to 31)); +wr_array_par(55) <= xor_reduce(wr_cam_data(32 to 39)); +wr_array_par(56) <= xor_reduce(wr_cam_data(40 to 47)); +wr_array_par(57) <= xor_reduce(wr_cam_data(48 to 55)); +wr_array_par(58) <= xor_reduce(wr_cam_data(57 to 62)); +wr_array_par(59) <= xor_reduce(wr_cam_data(63 to 66)); +wr_array_par(60) <= xor_reduce(wr_cam_data(67 to 74)); +wr_array_par(61) <= xor_reduce(wr_array_data_nopar(0 to 5)); +wr_array_par(62) <= xor_reduce(wr_array_data_nopar(6 to 13)); +wr_array_par(63) <= xor_reduce(wr_array_data_nopar(14 to 21)); +wr_array_par(64) <= xor_reduce(wr_array_data_nopar(22 to 29)); +wr_array_par(65) <= xor_reduce(wr_array_data_nopar(30 to 37)); +wr_array_par(66) <= xor_reduce(wr_array_data_nopar(38 to 44)); +wr_array_par(67) <= xor_reduce(wr_array_data_nopar(45 to 50)); +wr_array_data(0 TO 50) <= wr_array_data_nopar; +wr_array_data(51 TO 67) <= (wr_array_par(51 to 60) & wr_array_par(61 to 67)) + when ((tlb_rel_val_q(0 to 3)/="0000" and tlb_rel_val_q(4)='1') or + por_seq_q/=PorSeq_Idle) + else ((wr_array_par(51) xor mmucr1_q(5)) & wr_array_par(52 to 60) & + (wr_array_par(61) xor mmucr1_q(6)) & wr_array_par(62 to 67)) + when (ex6_valid_q(0 to 3)/="0000" and ex6_ttype_q(1)='1' and ex6_ws_q="00") + else (others => '0'); +-- Parity Checking +ex4_rd_data_calc_par(50) <= xor_reduce(ex4_rd_cam_data_q(75 to 82)); +ex4_rd_data_calc_par(51) <= xor_reduce(ex4_rd_cam_data_q(0 to 7)); +ex4_rd_data_calc_par(52) <= xor_reduce(ex4_rd_cam_data_q(8 to 15)); +ex4_rd_data_calc_par(53) <= xor_reduce(ex4_rd_cam_data_q(16 to 23)); +ex4_rd_data_calc_par(54) <= xor_reduce(ex4_rd_cam_data_q(24 to 31)); +ex4_rd_data_calc_par(55) <= xor_reduce(ex4_rd_cam_data_q(32 to 39)); +ex4_rd_data_calc_par(56) <= xor_reduce(ex4_rd_cam_data_q(40 to 47)); +ex4_rd_data_calc_par(57) <= xor_reduce(ex4_rd_cam_data_q(48 to 55)); +ex4_rd_data_calc_par(58) <= xor_reduce(ex4_rd_cam_data_q(57 to 62)); +ex4_rd_data_calc_par(59) <= xor_reduce(ex4_rd_cam_data_q(63 to 66)); +ex4_rd_data_calc_par(60) <= xor_reduce(ex4_rd_cam_data_q(67 to 74)); +ex4_rd_data_calc_par(61) <= xor_reduce(ex4_rd_array_data_q(0 to 5)); +ex4_rd_data_calc_par(62) <= xor_reduce(ex4_rd_array_data_q(6 to 13)); +ex4_rd_data_calc_par(63) <= xor_reduce(ex4_rd_array_data_q(14 to 21)); +ex4_rd_data_calc_par(64) <= xor_reduce(ex4_rd_array_data_q(22 to 29)); +ex4_rd_data_calc_par(65) <= xor_reduce(ex4_rd_array_data_q(30 to 37)); +ex4_rd_data_calc_par(66) <= xor_reduce(ex4_rd_array_data_q(38 to 44)); +ex4_rd_data_calc_par(67) <= xor_reduce(ex4_rd_array_data_q(45 to 50)); +parerr_gen0: if check_parity = 0 generate +ex3_cmp_data_parerr_epn <= '0'; +ex3_cmp_data_parerr_rpn <= '0'; +end generate parerr_gen0; +parerr_gen1: if check_parity = 1 generate +ex3_cmp_data_parerr_epn <= ex3_cmp_data_parerr_epn_mac; +ex3_cmp_data_parerr_rpn <= ex3_cmp_data_parerr_rpn_mac; +end generate parerr_gen1; +parerr_gen2: if check_parity = 0 generate +ex4_rd_data_parerr_epn <= '0'; +ex4_rd_data_parerr_rpn <= '0'; +end generate parerr_gen2; +parerr_gen3: if check_parity = 1 generate +ex4_rd_data_parerr_epn <= or_reduce(ex4_rd_data_calc_par(50 to 60) xor (ex4_rd_cam_data_q(83) & ex4_rd_array_data_q(51 to 60))); +ex4_rd_data_parerr_rpn <= or_reduce(ex4_rd_data_calc_par(61 to 67) xor ex4_rd_array_data_q(61 to 67)); +end generate parerr_gen3; +-- ttype <= 0-eratre 1-eratwe 2-eratsx 3-eratilx 4-load 5-store 6-csync 7-isync 8-icbtlslc 9-touch 10-extload 11-extstore +-- end of parity checking +-- epsc waits for tlb_reloads +epsc_wr_d(0 TO thdid_width-1) <= xu_derat_epsc_wr and (0 to thdid_width-1 => not bcfg_q(108)); +epsc_wr_d(thdid_width TO 2*thdid_width-1) <= (epsc_wr_q(0 to thdid_width-1) or epsc_wr_q(thdid_width to 2*thdid_width-1)) + when or_reduce(tlb_rel_val_q(0 to 4))='1' + else epsc_wr_q(0 to thdid_width-1); +epsc_wr_d(2*thdid_width) <= (or_reduce(epsc_wr_q(0 to thdid_width-1)) or epsc_wr_q(2*thdid_width)) + when or_reduce(tlb_rel_val_q(0 to 4))='1' + else or_reduce(epsc_wr_q(0 to thdid_width-1)); +-- eplc waits for tlb_reloads and epsc accesses +eplc_wr_d(0 TO thdid_width-1) <= xu_derat_eplc_wr and (0 to thdid_width-1 => not bcfg_q(109)); +eplc_wr_d(thdid_width TO 2*thdid_width-1) <= (eplc_wr_q(0 to thdid_width-1) or eplc_wr_q(thdid_width to 2*thdid_width-1)) + when (or_reduce(tlb_rel_val_q(0 to 4))='1' or epsc_wr_q(2*thdid_width)='1') + else eplc_wr_q(0 to thdid_width-1); +eplc_wr_d(2*thdid_width) <= (or_reduce(eplc_wr_q(0 to thdid_width-1)) or eplc_wr_q(2*thdid_width)) + when (or_reduce(tlb_rel_val_q(0 to 4))='1' or epsc_wr_q(2*thdid_width)='1') + else or_reduce(eplc_wr_q(0 to thdid_width-1)); +-- CAM Port +flash_invalidate <= Eq(por_seq_q,PorSeq_Stg1) or mchk_flash_inv_enab; +comp_invalidate <= '1' when (ex6_valid_q/="0000" and ex6_ttype_q(6 to 7)/="00") + else '0' when (tlb_rel_val_q(0 to 3)/="0000" and tlb_rel_val_q(4)='1') + else '1' when ((eplc_wr_q(8)='1' or epsc_wr_q(8)='1') and tlb_rel_val_q(4)='0' and mmucr1_q(7)='0') + else '1' when snoop_val_q(0 to 1)="11" + else '0'; +comp_request <= '1' when (ex6_valid_q/="0000" and ex6_ttype_q(6 to 7)/="00") + else '1' when ((eplc_wr_q(8)='1' or epsc_wr_q(8)='1') and tlb_rel_val_q(4)='0' and mmucr1_q(7)='0') + else '1' when (snoop_val_q(0 to 1)="11" and (tlb_rel_val_q(0 to 3)="0000" or tlb_rel_val_q(4)='0')) + else '1' when (ex1_valid_q/="0000" and ex1_ttype_q(2)='1' and ex1_tlbsel_q=TlbSel_DErat) + else '1' when (ex1_valid_q/="0000" and ex1_ttype_q(4 to 5)/="00" ) + else '0'; +gen64_comp_addr: if rs_data_width = 64 generate +comp_addr <= xu_derat_ex1_epn_arr; +snoop_addr <= snoop_addr_q; +snoop_addr_sel <= snoop_val_q(0) and snoop_val_q(1); +end generate gen64_comp_addr; +gen32_comp_addr: if rs_data_width = 32 generate +comp_addr <= (0 to 31 => '0') & xu_derat_ex1_epn_arr(32 to 51); +snoop_addr <= (0 to 31 => '0') & snoop_addr_q(32 to 51); +snoop_addr_sel <= snoop_val_q(0) and snoop_val_q(1); +end generate gen32_comp_addr; +-- ex1_rs_is(0 to 9) from erativax instr. +-- RS(55) -> ex1_rs_is(0) -> snoop_attr(0) -> Local +-- RS(56:57) -> ex1_rs_is(1:2) -> snoop_attr(0:1) -> IS +-- RS(58:59) -> ex1_rs_is(3:4) -> snoop_attr(2:3) -> Class +-- n/a -> n/a -> snoop_attr(4:5) -> State +-- n/a -> n/a -> snoop_attr(6:13) -> TID(6:13) +-- RS(60:63) -> ex1_rs_is(5:8) -> snoop_attr(14:17) -> Size +-- n/a -> n/a -> snoop_attr(20:25) -> TID(0:5) +-- snoop_attr: +-- 0 -> Local +-- 1:3 -> IS/Class: 0=all, 1=tid, 2=gs, 3=epn, 4=class0, 5=class1, 6=class2, 7=class3 +-- 4:5 -> GS/TS +-- 6:13 -> TID(6:13) +-- 14:17 -> Size +-- 18 -> reserved for tlb, extclass_enable(0) for erats +-- 19 -> mmucsr0.tlb0fi for tlb, or TID_NZ for erats +-- 20:25 -> TID(0:5) +-- ttype <= 0-eratre 1-eratwe 2-eratsx 3-eratilx 4-load 5-store 6-csync 7-isync 8-icbtlslc 9-touch 10-extload 11-extstore +addr_enable <= "00" when (ex6_valid_q/="0000" and ex6_ttype_q(6 to 7)/="00") + else "00" when (epsc_wr_q(8)='1' or eplc_wr_q(8)='1') + else "00" when (snoop_val_q(0 to 1)="11" and snoop_attr_q(1 to 3)/="011") + else "10" when (snoop_val_q(0 to 1)="11" and snoop_attr_q(0 to 3)="0011") + else "11" when (snoop_val_q(0 to 1)="11" and snoop_attr_q(0 to 3)="1011") + else "11" when (ex1_valid_q/="0000" and ex1_ttype_q(2)='1' and ex1_tlbsel_q=TlbSel_DErat) + else "11" when (ex1_valid_q/="0000" and ex1_ttype_q(4 to 5)/="00" ) + else "00"; +comp_pgsize <= CAM_PgSize_1GB when snoop_attr_q(14 to 17)=WS0_PgSize_1GB + else CAM_PgSize_16MB when snoop_attr_q(14 to 17)=WS0_PgSize_16MB + else CAM_PgSize_1MB when snoop_attr_q(14 to 17)=WS0_PgSize_1MB + else CAM_PgSize_64KB when snoop_attr_q(14 to 17)=WS0_PgSize_64KB + else CAM_PgSize_4KB; +pgsize_enable <= '0' when (ex6_valid_q/="0000" and ex6_ttype_q(6 to 7)/="00") + else '0' when (epsc_wr_q(8)='1' or eplc_wr_q(8)='1') + else '1' when (snoop_val_q(0 to 1)="11" and snoop_attr_q(0 to 3)="0011") + else '0'; +-- ttype <= 0-eratre 1-eratwe 2-eratsx 3-eratilx 4-load 5-store 6-csync 7-isync 8-icbtlslc 9-touch 10-extload 11-extstore +-- mmucr1_q: 0-DRRE, 1-REE, 2-CEE, 3-csync, 4-isync, 5:6-DPEI, 7:8-DCTID/DTTID, 9:DCCD +comp_class <= "11" when (epsc_wr_q(8)='1' and mmucr1_q(7)='0') + else "10" when (epsc_wr_q(8)='0' and eplc_wr_q(8)='1' and mmucr1_q(7)='0') + else snoop_attr_q(20 to 21) when (snoop_val_q(0 to 1)="11" and mmucr1_q(7)='1') + else snoop_attr_q(2 to 3) when (snoop_val_q(0 to 1)="11") + else ex1_pid_q(pid_width-14 to pid_width-13) when mmucr1_q(7)='1' + else ((ex1_ttype_q(10) or ex1_ttype_q(11)) & ex1_ttype_q(11)); +class_enable(0) <= '0' when (mmucr1_q(7)='1') + else '0' when (ex6_valid_q/="0000" and ex6_ttype_q(6 to 7)/="00") + else '1' when ((eplc_wr_q(8)='1' or epsc_wr_q(8)='1') and tlb_rel_val_q(4)='0' and mmucr1_q(7)='0') + else '1' when (snoop_val_q(0 to 1)="11" and snoop_attr_q(1)='1') + else '1' when (ex1_valid_q/="0000" and ex1_ttype_q(10 to 11)/="00" and mmucr1_q(9)='0') + else '1' when (ex1_valid_q/="0000" and ex1_ttype_q(4 to 5)/="00" and mmucr1_q(9)='0') + else '0'; +class_enable(1) <= '0' when (mmucr1_q(7)='1') + else '0' when (ex6_valid_q/="0000" and ex6_ttype_q(6 to 7)/="00") + else '1' when ((eplc_wr_q(8)='1' or epsc_wr_q(8)='1') and tlb_rel_val_q(4)='0' and mmucr1_q(7)='0') + else '1' when (snoop_val_q(0 to 1)="11" and snoop_attr_q(1)='1') + else '1' when (ex1_valid_q/="0000" and ex1_ttype_q(10 to 11)/="00" and mmucr1_q(9)='0') + else '0'; +class_enable(2) <= '0' when (mmucr1_q(7)='0') + else pid_enable; +-- snoop_attr: +-- 0 -> Local +-- 1:3 -> IS/Class: 0=all, 1=tid, 2=gs, 3=epn, 4=class0, 5=class1, 6=class2, 7=class3 +-- 4:5 -> GS/TS +-- 6:13 -> TID(6:13) +-- 14:17 -> Size +-- 18 -> reserved for tlb, extclass_enable(0) for erats +-- 19 -> mmucsr0.tlb0fi for tlb, or TID_NZ for erats +-- 20:25 -> TID(0:5) +--extclass_enable <= 10 when (ex6_valid_q/= 0000 and ex6_ttype_q(6 to 7)/= 00 ) -- csync or isync enabled +-- else 10 when (epsc_wr_q(8)='1' or eplc_wr_q(8)='1') -- write to epsc or eplc +-- else 10 when (snoop_val_q(0 to 1)= 11 ) -- any invalidate snoop +-- else 00 ; -- std_ulogic; +comp_extclass(0) <= '0'; +comp_extclass(1) <= snoop_attr_q(19); +extclass_enable(0) <= ( or_reduce(ex6_valid_q) and or_reduce(ex6_ttype_q(6 to 7)) ) + or ( (eplc_wr_q(8) or epsc_wr_q(8)) and not mmucr1_q(7) ) + or ( snoop_val_q(0) and snoop_attr_q(18) ); +extclass_enable(1) <= ( snoop_val_q(0) and not snoop_attr_q(1) and snoop_attr_q(3) ); +-- state: 0:pr 1:gs 2:is 3:cm +-- cam state bits are 0:HS, 1:AS +comp_state <= snoop_attr_q(4 to 5) when (snoop_val_q(0 to 1)="11" and snoop_attr_q(1 to 2)="01") + else ex1_state_q(1 to 2); +state_enable <= "00" when (ex6_valid_q/="0000" and ex6_ttype_q(6 to 7)/="00") + else "00" when (epsc_wr_q(8)='1' or eplc_wr_q(8)='1') + else "00" when (snoop_val_q(0 to 1)="11" and snoop_attr_q(1 to 2)/="01") + else "10" when (snoop_val_q(0 to 1)="11" and snoop_attr_q(1 to 3)="010") + else "11" when (snoop_val_q(0 to 1)="11" and snoop_attr_q(1 to 3)="011") + else "11" when (ex1_valid_q/="0000" and ex1_ttype_q(2)='1' and ex1_tlbsel_q=TlbSel_DErat) + else "11" when (ex1_valid_q/="0000" and ex1_ttype_q(4 to 5)/="00" ) + else "00"; +-- mmucr1_q: 0-DRRE, 1-REE, 2-CEE, 3-csync, 4-isync, 5:6-DPEI, 7:8-DCTID/DTTID, 9-DCCD +comp_thdid <= snoop_attr_q(22 to 25) when (snoop_val_q(0 to 1)="11" and mmucr1_q(8)='1') + else ex1_pid_q(pid_width-12 to pid_width-9) when (mmucr1_q(8)='1') + else epsc_wr_q(4 to 7) when (epsc_wr_q(8)='1' and mmucr1_q(8)='0') + else eplc_wr_q(4 to 7) when (epsc_wr_q(8)='0' and eplc_wr_q(8)='1' and mmucr1_q(8)='0') + else (others => '1') when (snoop_val_q(0 to 1)="11" and mmucr1_q(8)='0') + else ex1_valid_q; +thdid_enable(0) <= '0' when (mmucr1_q(8)='1') + else '0' when (ex6_valid_q/="0000" and ex6_ttype_q(6 to 7)/="00") + else '1' when (epsc_wr_q(8)='1' and tlb_rel_val_q(4)='0' and mmucr1_q(8)='0') + else '1' when (epsc_wr_q(8)='0' and eplc_wr_q(8)='1' and tlb_rel_val_q(4)='0' and mmucr1_q(8)='0') + else '0' when (snoop_val_q(0 to 1)="11") + else '1' when (ex1_valid_q/="0000" and ((ex1_ttype_q(2)='1' and ex1_tlbsel_q=TlbSel_DErat) or or_reduce(ex1_ttype_q(4 to 5))='1')) + else '0'; +thdid_enable(1) <= '0' when (mmucr1_q(8)='0') + else pid_enable; +comp_pid <= snoop_attr_q(6 to 13) when (snoop_val_q(0 to 1)="11") + else ex1_pid_q(pid_width-8 to pid_width-1); +pid_enable <= '0' when (ex6_valid_q/="0000" and ex6_ttype_q(6 to 7)/="00") + else '0' when (epsc_wr_q(8)='1' or eplc_wr_q(8)='1') + else '0' when (snoop_val_q(0 to 1)="11" and snoop_attr_q(1)='1') + else '0' when (snoop_val_q(0 to 1)="11" and snoop_attr_q(3)='0') + else '1' when (snoop_val_q(0 to 1)="11" and snoop_attr_q(1 to 3)="001") + else '1' when (snoop_val_q(0 to 1)="11" and snoop_attr_q(1 to 3)="011") + else '1' when (ex1_valid_q/="0000" and ex1_ttype_q(2)='1' and ex1_tlbsel_q=TlbSel_DErat) + else '1' when (ex1_valid_q/="0000" and ex1_ttype_q(4 to 5)/="00" ) + else '0'; +-- wr_cam_data +-- 0:51 - EPN +-- 52 - X +-- 53:55 - SIZE +-- 56 - V +-- 57:60 - ThdID +-- 61:62 - Class +-- 63:64 - ExtClass | TID_NZ +-- 65 - TGS +-- 66 - TS +-- 67:74 - TID +-- 75:78 - epn_cmpmasks: 34_39, 40_43, 44_47, 48_51 +-- 79:82 - xbit_cmpmasks: 34_51, 40_51, 44_51, 48_51 +-- 83 - parity for 75:82 +-- 16x143 version, 42b RA +-- wr_array_data +-- 0:29 - RPN +-- 30:31 - R,C +-- 32:35 - ResvAttr +-- 36:39 - U0-U3 +-- 40:44 - WIMGE +-- 45:46 - UX,SX +-- 47:48 - UW,SW +-- 49:50 - UR,SR +-- 51:60 - CAM parity +-- 61:67 - Array parity +-- wr_ws0_data (LO) +-- 0:51 - EPN +-- 52:53 - Class +-- 54 - V +-- 55 - X +-- 56:59 - SIZE +-- 60:63 - ThdID +-- CAM.ExtClass - MMUCR ExtClass +-- CAM.TS - MMUCR TS +-- CAM.TID - MMUCR TID +-- wr_ws1_data (HI) +-- 0:7 - unused +-- 8:9 - WLC +-- 10 - ResvAttr +-- 11 - unused +-- 12:15 - U0-U3 +-- 16:17 - R,C +-- 18:21 - unused +-- 22:51 - RPN +-- 52:56 - WIMGE +-- 57 - VF +-- 58:59 - UX,SX +-- 60:61 - UW,SW +-- 62:63 - UR,SR +-- state: 0:pr 1:gs 2:ds 3:cm +-- ttype <= 0-eratre 1-eratwe 2-eratsx 3-eratilx 4-load 5-store 6-csync 7-isync 8-icbtlslc 9-touch 10-extload 11-extstore +-- EPN Class V +-- X SIZE ThdID +-- Unused ResvAttr U0-U3 R,C +-- RPN WIMGE Unused UX,SW,UW,SW,UR,SR +gen64_data_out: if data_out_width = 64 generate +ex4_data_out_d <= ( ((0 to 31 => '0') & rd_cam_data(32 to 51) & rd_cam_data(61 to 62) & rd_cam_data(56) & + rd_cam_data(52) & ws0_pgsize(0 to 3) & rd_cam_data(57 to 60)) + and (64-data_out_width to 63 => (or_reduce(ex3_valid_q) and ex3_ttype_q(0) and not ex3_ws_q(0) and not ex3_ws_q(1) and not ex3_state_q(3))) ) + or ( ((0 to 31 => '0') & rd_array_data(10 to 29) & "00" & rd_array_data(0 to 9)) + and (64-data_out_width to 63 => (or_reduce(ex3_valid_q) and ex3_ttype_q(0) and not ex3_ws_q(0) and ex3_ws_q(1) and not ex3_state_q(3))) ) + or ( ((0 to 31 => '0') & "00000000" & rd_array_data(32 to 34) & '0' & rd_array_data(36 to 39) & rd_array_data(30 to 31) & + "00" & rd_array_data(40 to 44) & rd_array_data(35) & rd_array_data(45 to 50)) + and (64-data_out_width to 63 => (or_reduce(ex3_valid_q) and ex3_ttype_q(0) and ex3_ws_q(0) and not ex3_ws_q(1) and not ex3_state_q(3))) ) + or ( (rd_cam_data(0 to 51) & rd_cam_data(61 to 62) & rd_cam_data(56) & + rd_cam_data(52) & ws0_pgsize(0 to 3) & rd_cam_data(57 to 60)) + and (64-data_out_width to 63 => (or_reduce(ex3_valid_q) and ex3_ttype_q(0) and not ex3_ws_q(0) and not ex3_ws_q(1) and ex3_state_q(3))) ) + or ( ("00000000" & rd_array_data(32 to 34) & '0' & rd_array_data(36 to 39) & rd_array_data(30 to 31) & + "0000" & rd_array_data(0 to 29) & rd_array_data(40 to 44) & rd_array_data(35) & rd_array_data(45 to 50)) + and (64-data_out_width to 63 => (or_reduce(ex3_valid_q) and ex3_ttype_q(0) and not ex3_ws_q(0) and ex3_ws_q(1) and ex3_state_q(3))) ) + or ( ((0 to 47-watermark_width => '0') & (watermark_q and (48-watermark_width to 47 => bcfg_q(107))) & (48 to 63-eptr_width => '0') & eptr_q) + and (64-data_out_width to 63 => (or_reduce(ex3_valid_q) and ex3_ttype_q(0) and ex3_ws_q(0) and ex3_ws_q(1) and mmucr1_q(0))) ) + or ( ((0 to 47-watermark_width => '0') & (watermark_q and (48-watermark_width to 47 => bcfg_q(107))) & (48 to 63-num_entry_log2 => '0') & lru_way_encode) + and (64-data_out_width to 63 => (or_reduce(ex3_valid_q) and ex3_ttype_q(0) and ex3_ws_q(0) and ex3_ws_q(1) and not mmucr1_q(0))) ) + or ( ((0 to 49 => '0') & ex3_eratsx_data(0 to 1) & (52 to 58 => '0') & ex3_eratsx_data(2 to 2+num_entry_log2-1)) + and (64-data_out_width to 63 => (or_reduce(ex3_valid_q) and ex3_ttype_q(2))) ); +end generate gen64_data_out; +gen32_data_out: if data_out_width = 32 generate +ex4_data_out_d <= ( (rd_cam_data(32 to 51) & rd_cam_data(61 to 62) & rd_cam_data(56) & + rd_cam_data(52) & ws0_pgsize(0 to 3) & rd_cam_data(57 to 60)) + and (64-data_out_width to 63 => (or_reduce(ex3_valid_q) and ex3_ttype_q(0) and not ex3_ws_q(0) and not ex3_ws_q(1))) ) + or ( (rd_array_data(10 to 29) & "00" & rd_array_data(0 to 9)) + and (64-data_out_width to 63 => (or_reduce(ex3_valid_q) and ex3_ttype_q(0) and not ex3_ws_q(0) and ex3_ws_q(1))) ) + or ( ("00000000" & rd_array_data(32 to 34) & '0' & rd_array_data(36 to 39) & rd_array_data(30 to 31) & + "00" & rd_array_data(40 to 44) & rd_array_data(35) & rd_array_data(45 to 50)) + and (64-data_out_width to 63 => (or_reduce(ex3_valid_q) and ex3_ttype_q(0) and ex3_ws_q(0) and not ex3_ws_q(1))) ) + or ( ((32 to 47-watermark_width => '0') & (watermark_q and (48-watermark_width to 47 => bcfg_q(107))) & (48 to 58 => '0') & eptr_q) + and (64-data_out_width to 63 => (or_reduce(ex3_valid_q) and ex3_ttype_q(0) and ex3_ws_q(0) and ex3_ws_q(1) and mmucr1_q(0))) ) + or ( ((32 to 47-watermark_width => '0') & (watermark_q and (48-watermark_width to 47 => bcfg_q(107))) & (48 to 58 => '0') & lru_way_encode) + and (64-data_out_width to 63 => (or_reduce(ex3_valid_q) and ex3_ttype_q(0) and ex3_ws_q(0) and ex3_ws_q(1) and not mmucr1_q(0))) ) + or ( ((32 to 49 => '0') & ex3_eratsx_data(0 to 1) & (52 to 58 => '0') & ex3_eratsx_data(2 to 2+num_entry_log2-1)) + and (64-data_out_width to 63 => (or_reduce(ex3_valid_q) and ex3_ttype_q(2))) ); +end generate gen32_data_out; +-- ERAT outputs +derat_xu_ex2_miss <= ex2_valid_q and (0 to thdid_width-1 => (not cam_hit and or_reduce(ex2_ttype_q(4 to 5)) and not ex2_ttype_q(9) and not ccr2_frat_paranoia_q(9))); +-- 16x143 version +-- pass thru epn offset bits depending on page size from cam entry +-- adding frat paranoia bypass bit 9 for ra=ea... bit 10 also bypass ra=ea for other xu reasons +gen_mcompar_breaks_timing_1: if ex2_epn_width = rpn_width generate +derat_xu_ex2_rpn(22 TO 33) <= ( ex2_epn_q(22 to 33) and (22 to 33 => (ccr2_frat_paranoia_q(9) or ccr2_frat_paranoia_q(11))) ) or + ( array_cmp_data(0 to 11) and (0 to 11 => (not ccr2_frat_paranoia_q(9) and not ccr2_frat_paranoia_q(11))) ); +derat_xu_ex2_rpn(34 TO 39) <= ( ex2_epn_q(34 to 39) and (34 to 39 => (not(cam_cmp_data(75)) or ccr2_frat_paranoia_q(9) or ccr2_frat_paranoia_q(11))) ) or + ( array_cmp_data(12 to 17) and (12 to 17 => (cam_cmp_data(75) and not ccr2_frat_paranoia_q(9) and not ccr2_frat_paranoia_q(11))) ); +derat_xu_ex2_rpn(40 TO 43) <= ( ex2_epn_q(40 to 43) and (40 to 43 => (not(cam_cmp_data(76)) or ccr2_frat_paranoia_q(9) or ccr2_frat_paranoia_q(11))) ) or + ( array_cmp_data(18 to 21) and (18 to 21 => (cam_cmp_data(76) and not ccr2_frat_paranoia_q(9) and not ccr2_frat_paranoia_q(11))) ); +derat_xu_ex2_rpn(44 TO 47) <= ( ex2_epn_q(44 to 47) and (44 to 47 => (not(cam_cmp_data(77)) or ccr2_frat_paranoia_q(9) or ccr2_frat_paranoia_q(11))) ) or + ( array_cmp_data(22 to 25) and (22 to 25 => (cam_cmp_data(77) and not ccr2_frat_paranoia_q(9) and not ccr2_frat_paranoia_q(11))) ); +derat_xu_ex2_rpn(48 TO 51) <= ( ex2_epn_q(48 to 51) and (48 to 51 => (not(cam_cmp_data(78)) or ccr2_frat_paranoia_q(9) or ccr2_frat_paranoia_q(11))) ) or + ( array_cmp_data(26 to 29) and (26 to 29 => (cam_cmp_data(78) and not ccr2_frat_paranoia_q(9) and not ccr2_frat_paranoia_q(11))) ); +derat_xu_ex2_u <= ( ccr2_frat_paranoia_q(5 to 8) and (5 to 8 => ccr2_frat_paranoia_q(9)) ) or + ( array_cmp_data(36 to 39) and (36 to 39 => not ccr2_frat_paranoia_q(9)) ); +derat_xu_ex2_wimge <= ( ccr2_frat_paranoia_q(0 to 4) and (0 to 4 => ccr2_frat_paranoia_q(9)) ) or + ( array_cmp_data(40 to 44) and (40 to 44 => not ccr2_frat_paranoia_q(9)) ); +derat_xu_ex2_wlc <= array_cmp_data(32 to 33) and (32 to 33 => not ccr2_frat_paranoia_q(9)); +derat_xu_ex2_vf <= array_cmp_data(35) and not ccr2_frat_paranoia_q(9); +end generate gen_mcompar_breaks_timing_1; +gen_no_frat_1: if ex2_epn_width = 18 generate +derat_xu_ex2_rpn(22 TO 33) <= array_cmp_data(0 to 11); +derat_xu_ex2_rpn(34 TO 39) <= ( ex2_epn_q(34 to 39) and (34 to 39 => (cam_cmp_data(53) and cam_cmp_data(54) and not cam_cmp_data(55))) ) or + ( array_cmp_data(12 to 17) and (12 to 17 => (not(cam_cmp_data(53)) or not(cam_cmp_data(54)) or cam_cmp_data(55))) ); +derat_xu_ex2_rpn(40 TO 43) <= ( ex2_epn_q(40 to 43) and (40 to 43 => (cam_cmp_data(53) and cam_cmp_data(54))) ) or + ( array_cmp_data(18 to 21) and (18 to 21 => (not cam_cmp_data(53) or not cam_cmp_data(54))) ); +derat_xu_ex2_rpn(44 TO 47) <= ( ex2_epn_q(44 to 47) and (44 to 47 => cam_cmp_data(53)) ) or + ( array_cmp_data(22 to 25) and (22 to 25 => not cam_cmp_data(53)) ); +derat_xu_ex2_rpn(48 TO 51) <= ( ex2_epn_q(48 to 51) and (48 to 51 => (cam_cmp_data(53) or cam_cmp_data(54))) ) or + ( array_cmp_data(26 to 29) and (26 to 29 => (not cam_cmp_data(53) and not cam_cmp_data(54))) ); +derat_xu_ex2_u <= array_cmp_data(36 to 39); +derat_xu_ex2_wimge <= array_cmp_data(40 to 44); +derat_xu_ex2_wlc <= array_cmp_data(32 to 33); +derat_xu_ex2_vf <= array_cmp_data(35); +end generate gen_no_frat_1; +-- new cam _np2 bypass attributes (bit numbering per array) +-- 30:31 - R,C +-- 32:33 - WLC +-- 34 - ResvAttr +-- 35 - VF +-- 36:39 - U0-U3 +-- 40:44 - WIMGE +-- 45:46 - UX,SX +-- 47:48 - UW,SW +-- 49:50 - UR,SR +bypass_mux_enab_np1 <= (ccr2_frat_paranoia_q(9) or ccr2_frat_paranoia_q(11) or an_ac_grffence_en_dc); +bypass_attr_np1(0 TO 5) <= (others => '0'); +bypass_attr_np1(6 TO 9) <= ccr2_frat_paranoia_q(5 to 8); +bypass_attr_np1(10 TO 14) <= ccr2_frat_paranoia_q(0 to 4); +bypass_attr_np1(15 TO 20) <= "111111"; +derat_xu_ex2_attr <= ex3_attr_d; +derat_xu_ex3_miss <= ex3_miss_q; +derat_xu_ex3_dsi <= ex3_dsi_q(12 to 15) and (0 to 3 => ex3_dsi_enab); +derat_xu_ex3_noop_touch <= ex3_noop_touch_q(12 to 15) and (0 to 3 => ex3_noop_touch_enab); +derat_xu_ex3_multihit_err <= ex3_multihit_q and (0 to 3 => ex3_multihit_enab); +derat_xu_ex3_par_err <= ex3_parerr_q(0 to thdid_width-1) and (0 to thdid_width-1 => ex3_parerr_enab); +derat_xu_ex3_n_flush_req <= ex3_n_flush_req_q; +derat_xu_ex4_data <= ex4_data_out_q; +derat_xu_ex4_par_err <= ex4_parerr_q(0 to thdid_width-1) and (0 to thdid_width-1 => ex4_parerr_enab); +derat_fir_par_err <= ex4_fir_parerr_q(0 to thdid_width-1) and (0 to thdid_width-1 => ex4_fir_parerr_enab); +derat_fir_multihit <= ex4_fir_multihit_q; +derat_iu_barrier_done <= barrier_done_q; +xu_mm_derat_req <= ex3_tlbreq_q; +xu_mm_derat_thdid <= ex3_valid_q; +xu_mm_derat_state <= ex3_state_q; +xu_mm_derat_ttype <= "11" when ex3_ttype_q(11)='1' + else "10" when ex3_ttype_q(10)='1' + else "01" when ex3_ttype_q(5)='1' + else "00"; +xu_mm_derat_tid <= ex3_pid_q; +xu_mm_derat_lpid <= ex3_lpid_q; +xu_mm_derat_mmucr0 <= ex6_extclass_q & ex6_state_q(1 to 2) & ex6_pid_q; +xu_mm_derat_mmucr0_we <= ex6_valid_q when (ex6_ttype_q(0)='1' and ex6_ws_q="00" and ex6_tlbsel_q=TlbSel_DErat) + else (others => '0'); +xu_mm_derat_mmucr1 <= ex6_deen_q(1 to num_entry_log2); +xu_mm_derat_mmucr1_we <= ex6_deen_q(0); +-- NOTE: example parity generation/checks in iuq_ic_dir.vhdl or xuq_lsu_dc_arr.vhdl. +----------------------------------------------------------------------- +-- CAM Instantiation +----------------------------------------------------------------------- +derat_cam: entity tri.tri_cam_32x143_1r1w1c + generic map (expand_type => expand_type) + port map ( + gnd => gnd, + vdd => vdd, + vcs => vcs, + nclk => nclk, + + + tc_ccflush_dc => pc_xu_ccflush_dc, + tc_scan_dis_dc_b => tc_scan_dis_dc_b, + tc_scan_diag_dc => tc_scan_diag_dc, + tc_lbist_en_dc => tc_lbist_en_dc, + an_ac_atpg_en_dc => an_ac_atpg_en_dc, + + lcb_d_mode_dc => cam_d_mode_dc, + lcb_clkoff_dc_b => cam_clkoff_dc_b, + lcb_act_dis_dc => cam_act_dis_dc, + lcb_mpw1_dc_b => cam_mpw1_dc_b(0 to 3), + lcb_mpw2_dc_b => cam_mpw2_dc_b, + lcb_delay_lclkr_dc => cam_delay_lclkr_dc(0 to 3), + + pc_sg_2 => pc_sg_2, + pc_func_slp_sl_thold_2 => pc_func_slp_sl_thold_2, + pc_func_slp_nsl_thold_2 => pc_func_slp_nsl_thold_2, + pc_regf_slp_sl_thold_2 => pc_regf_slp_sl_thold_2, + pc_time_sl_thold_2 => pc_time_sl_thold_2, + pc_fce_2 => pc_fce_2, + + func_scan_in => func_si_cam_int, + func_scan_out => func_so_cam_int, + regfile_scan_in => regf_scan_in, + regfile_scan_out => regf_scan_out, + time_scan_in => time_scan_in, + time_scan_out => time_scan_out, + + + rd_val => rd_val, + rd_val_late => tiup, + rw_entry => rw_entry, + + wr_array_data => wr_array_data, + wr_cam_data => wr_cam_data, + wr_array_val => wr_array_val, + wr_cam_val => wr_cam_val, + wr_val_early => wr_val_early, + + comp_request => comp_request, + comp_addr => comp_addr, + addr_enable => addr_enable, + comp_pgsize => comp_pgsize, + pgsize_enable => pgsize_enable, + comp_class => comp_class, + class_enable => class_enable, + comp_extclass => comp_extclass, + extclass_enable => extclass_enable, + comp_state => comp_state, + state_enable => state_enable, + comp_thdid => comp_thdid, + thdid_enable => thdid_enable, + comp_pid => comp_pid, + pid_enable => pid_enable, + comp_invalidate => comp_invalidate, + flash_invalidate => flash_invalidate, + + array_cmp_data => array_cmp_data, + rd_array_data => rd_array_data, + + cam_cmp_data => cam_cmp_data, + cam_hit => cam_hit, + cam_hit_entry => cam_hit_entry, + entry_match => entry_match, + entry_valid => entry_valid, + rd_cam_data => rd_cam_data, + + +----- new ports for IO plus ----------------------- +bypass_mux_enab_np1 => bypass_mux_enab_np1, + bypass_attr_np1 => bypass_attr_np1, + attr_np2 => attr_np2, + rpn_np2 => rpn_np2 + + ); +derat_cmp_parerr_mac: entity tri.tri_cam_parerr_mac + port map ( + gnd => gnd, + vdd => vdd, + + nclk => nclk, + lcb_act_dis_dc => cam_act_dis_dc, + lcb_delay_lclkr_dc => cam_delay_lclkr_dc(4), + lcb_clkoff_dc_b_0 => cam_clkoff_dc_b, + lcb_mpw1_dc_b => cam_mpw1_dc_b(4), + lcb_mpw2_dc_b => cam_mpw2_dc_b, + + act => ex2_cmp_data_act, + lcb_sg_0 => pc_sg_0, + lcb_func_sl_thold_0 => pc_func_slp_sl_thold_0, + + func_scan_in => siv_1(erat_parerr_mac_offset), + func_scan_out => sov_1(erat_parerr_mac_offset), + + np1_cam_cmp_data => cam_cmp_data, + np1_array_cmp_data => array_cmp_data, + + np2_cam_cmp_data => ex3_cam_cmp_data_q, + np2_array_cmp_data => ex3_array_cmp_data_q, + np2_cmp_data_parerr_epn => ex3_cmp_data_parerr_epn_mac, + np2_cmp_data_parerr_rpn => ex3_cmp_data_parerr_rpn_mac + + ); +-- bypass attributes (bit numbering per array) +-- 30:31 - R,C +-- 32:33 - WLC +-- 34 - ResvAttr +-- 35 - VF +-- 36:39 - U0-U3 +-- 40:44 - WIMGE +-- 45:46 - UX,SX +-- 47:48 - UW,SW +-- 49:50 - UR,SR +derat_xu_ex3_rpn <= rpn_np2; +derat_xu_ex3_wimge <= attr_np2(10 to 14); +derat_xu_ex3_u <= attr_np2(6 to 9); +derat_xu_ex3_wlc <= attr_np2(2 to 3); +derat_xu_ex3_attr <= attr_np2(15 to 20); +derat_xu_ex3_vf <= attr_np2(5); +-- debug bus outputs +ex2_debug_d(0) <= comp_request; +ex2_debug_d(1) <= comp_invalidate; +ex2_debug_d(2) <= ( or_reduce(ex6_valid_q) and or_reduce(ex6_ttype_q(6 to 7)) ); +ex2_debug_d(3) <= ( (eplc_wr_q(8) or epsc_wr_q(8)) and not(tlb_rel_val_q(4)) and not(mmucr1_q(7)) ); +ex2_debug_d(4) <= ( snoop_val_q(0) and snoop_val_q(1) and not(or_reduce(tlb_rel_val_q(0 to 3)) and tlb_rel_val_q(4)) ); +ex2_debug_d(5) <= ( or_reduce(ex1_valid_q) and ex1_ttype_q(2) and Eq(ex1_tlbsel_q,TlbSel_DErat)); +ex2_debug_d(6) <= ( or_reduce(ex1_valid_q) and or_reduce(ex1_ttype_q(4 to 5)) ); +ex2_debug_d(7) <= ( or_reduce(tlb_rel_val_q(0 to 3)) and tlb_rel_val_q(4) ); +ex2_debug_d(8) <= ( or_reduce(tlb_rel_val_q(0 to 3)) ); +ex2_debug_d(9) <= ( snoop_val_q(0) and snoop_val_q(1) ); +ex2_debug_d(10) <= ( eplc_wr_q(8) or epsc_wr_q(8) ); +ex3_debug_d(0 TO 10) <= ex2_debug_q(0 to 10); +ex3_debug_d(11 TO 15) <= ex3_first_hit_entry; +ex3_debug_d(16) <= ex3_multihit_enab; +lru_debug_d(0) <= tlb_rel_data_q(eratpos_wren) when (tlb_rel_val_q(0 to 3)/="0000" and tlb_rel_val_q(4)='1') else '0'; +lru_debug_d(1) <= '1' when snoop_val_q(0 to 1)="11" else '0'; +lru_debug_d(2) <= '1' when (ex6_valid_q/="0000" and ex6_ttype_q(6 to 7)/="00") else '0'; +lru_debug_d(3) <= '1' when (ex6_valid_q/="0000" and ex6_ttype_q(1)='1' + and ex6_ws_q="00" and ex6_tlbsel_q=TlbSel_DErat and lru_way_encode=ex6_ra_entry_q) else '0'; +lru_debug_d(4) <= '1' when (ex6_valid_q/="0000" and ex6_ttype_q(4 to 5)/="00" and ex6_hit_q='1' ) else '0'; +lru_debug_d(5 TO 35) <= lru_eff; +lru_debug_d(36 TO 40) <= lru_way_encode; +derat_xu_debug_group0(0 TO 83) <= ex3_cam_cmp_data_q(0 to 83); +derat_xu_debug_group0(84) <= ex3_cam_hit_q; +derat_xu_debug_group0(85) <= ex3_debug_q(0); +derat_xu_debug_group0(86) <= ex3_debug_q(1); +derat_xu_debug_group0(87) <= ex3_debug_q(9); +derat_xu_debug_group1(0 TO 67) <= ex3_array_cmp_data_q(0 to 67); +derat_xu_debug_group1(68) <= ex3_cam_hit_q; +derat_xu_debug_group1(69) <= ex3_debug_q(16); +derat_xu_debug_group1(70 TO 74) <= ex3_debug_q(11 to 15); +derat_xu_debug_group1(75) <= ex3_debug_q(0); +derat_xu_debug_group1(76) <= ex3_debug_q(1); +derat_xu_debug_group1(77) <= ex3_debug_q(2); +derat_xu_debug_group1(78) <= ex3_debug_q(3); +derat_xu_debug_group1(79) <= ex3_debug_q(4); +derat_xu_debug_group1(80) <= ex3_debug_q(5); +derat_xu_debug_group1(81) <= ex3_debug_q(6); +derat_xu_debug_group1(82) <= ex3_debug_q(7); +derat_xu_debug_group1(83) <= ex3_debug_q(8); +derat_xu_debug_group1(84) <= ex3_debug_q(9); +derat_xu_debug_group1(85) <= ex3_debug_q(10); +derat_xu_debug_group1(86) <= ex3_ttype_q(8); +derat_xu_debug_group1(87) <= ex3_ttype_q(9); +derat_xu_debug_group2(0 TO 31) <= entry_valid_q(0 to 31); +derat_xu_debug_group2(32 TO 63) <= entry_match_q(0 to 31); +derat_xu_debug_group2(64 TO 73) <= lru_update_event_q(0 to 9); +derat_xu_debug_group2(74 TO 78) <= lru_debug_q(36 to 40); +derat_xu_debug_group2(79 TO 83) <= watermark_q(0 to 4); +derat_xu_debug_group2(84) <= ex3_cam_hit_q; +derat_xu_debug_group2(85) <= ex3_debug_q(0); +derat_xu_debug_group2(86) <= ex3_debug_q(1); +derat_xu_debug_group2(87) <= ex3_debug_q(9); +derat_xu_debug_group3(0) <= ex3_cam_hit_q; +derat_xu_debug_group3(1) <= ex3_debug_q(0); +derat_xu_debug_group3(2) <= ex3_debug_q(1); +derat_xu_debug_group3(3) <= ex3_debug_q(9); +derat_xu_debug_group3(4 TO 8) <= ex3_debug_q(11 to 15); +derat_xu_debug_group3(9) <= lru_update_event_q(9); +derat_xu_debug_group3(10 TO 14) <= lru_debug_q(0 to 4); +derat_xu_debug_group3(15 TO 19) <= watermark_q(0 to 4); +derat_xu_debug_group3(20) <= '0'; +derat_xu_debug_group3(21 TO 51) <= lru_q(1 to 31); +derat_xu_debug_group3(52 TO 82) <= lru_debug_q(5 to 35); +derat_xu_debug_group3(83 TO 87) <= lru_debug_q(36 to 40); +-- unused spare signal assignments +unused_dc(0) <= or_reduce(LCB_DELAY_LCLKR_DC(1 TO 4)); +unused_dc(1) <= or_reduce(LCB_MPW1_DC_B(1 TO 4)); +unused_dc(2) <= '0'; +unused_dc(3) <= '0'; +unused_dc(4) <= PC_FUNC_SL_FORCE; +unused_dc(5) <= PC_FUNC_SL_THOLD_0_B; +unused_dc(6) <= or_reduce(EX1_TTYPE_Q(6 TO 7)); +unused_dc(7) <= or_reduce(EX1_RS_IS_Q); +unused_dc(8) <= or_reduce(EX1_RA_ENTRY_Q); +unused_dc(9) <= or_reduce(cam_hit_entry); +unused_dc(10) <= or_reduce(ex2_first_hit_entry) or ex2_multihit_b; +unused_dc(11) <= or_reduce(EX3_DSI_Q(8 TO 11)); +unused_dc(12) <= EX3_NOOP_TOUCH_Q(1); +unused_dc(13) <= or_reduce(EX3_NOOP_TOUCH_Q(8 TO 11)); +unused_dc(14) <= or_reduce(EX3_ATTR_Q); +unused_dc(15) <= EX4_RD_CAM_DATA_Q(56); +unused_dc(16) <= or_reduce(EX6_RS_IS_Q); +unused_dc(17) <= EX6_STATE_Q(0); +unused_dc(18) <= EX7_TTYPE_Q(0); +unused_dc(19) <= or_reduce(EX7_TTYPE_Q(2 TO 11)); +unused_dc(20) <= or_reduce(tlb_rel_data_q(eratpos_rpnrsvd TO eratpos_rpnrsvd+3)); +unused_dc(21) <= or_reduce(XU_DERAT_EX1_EPN_NONARR(0 TO 15)); +unused_dc(22) <= or_reduce(XU_DERAT_EX1_EPN_NONARR(16 TO 21)); +unused_dc(23) <= or_reduce(XU_DERAT_RF1_T); +unused_dc(24) <= or_reduce(ATTR_NP2(0 TO 1)); +unused_dc(25) <= ATTR_NP2(4); +unused_dc(26) <= mmucr1_b0_cpy_q; +unused_dc(27) <= or_reduce(BCFG_Q_B(0 to 15)); +unused_dc(28) <= or_reduce(BCFG_Q_B(16 to 31)); +unused_dc(29) <= or_reduce(BCFG_Q_B(32 to 47)); +unused_dc(30) <= or_reduce(BCFG_Q_B(48 to 51)); +unused_dc(31) <= or_reduce(bcfg_q_b(52 to 61)); +unused_dc(32) <= or_reduce(bcfg_q_b(62 to 77)); +unused_dc(33) <= or_reduce(bcfg_q_b(78 to 81)); +unused_dc(34) <= or_reduce(bcfg_q_b(82 to 86)); +unused_dc(35) <= or_reduce(por_wr_array_data(51 to 67)); +unused_dc(36) <= or_reduce(bcfg_q_b(87 to 102)); +unused_dc(37) <= or_reduce(bcfg_q_b(103 to 106)); +unused_dc(38) <= or_reduce(bcfg_q(110 to 122)); +unused_dc(39) <= or_reduce(bcfg_q_b(107 to 122)); +----------------------------------------------------------------------- +-- Latches +----------------------------------------------------------------------- +rf1_valid_latch: tri_rlmreg_p + generic map (width => rf1_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(rf1_valid_offset to rf1_valid_offset+rf1_valid_q'length-1), + scout => sov_0(rf1_valid_offset to rf1_valid_offset+rf1_valid_q'length-1), + din => rf1_valid_d(0 to thdid_width-1), + dout => rf1_valid_q(0 to thdid_width-1) ); +rf1_ttype_latch: tri_rlmreg_p + generic map (width => rf1_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(rf1_ttype_offset to rf1_ttype_offset+rf1_ttype_q'length-1), + scout => sov_0(rf1_ttype_offset to rf1_ttype_offset+rf1_ttype_q'length-1), + din => rf1_ttype_d, + dout => rf1_ttype_q ); +ex1_valid_latch: tri_rlmreg_p + generic map (width => ex1_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex1_valid_offset to ex1_valid_offset+ex1_valid_q'length-1), + scout => sov_0(ex1_valid_offset to ex1_valid_offset+ex1_valid_q'length-1), + din => ex1_valid_d(0 to thdid_width-1), + dout => ex1_valid_q(0 to thdid_width-1) ); +ex1_ttype_latch: tri_rlmreg_p + generic map (width => ex1_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex1_ttype_offset to ex1_ttype_offset+ex1_ttype_q'length-1), + scout => sov_0(ex1_ttype_offset to ex1_ttype_offset+ex1_ttype_q'length-1), + din => ex1_ttype_d, + dout => ex1_ttype_q ); +ex1_ws_latch: tri_rlmreg_p + generic map (width => ex1_ws_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex1_ws_offset to ex1_ws_offset+ex1_ws_q'length-1), + scout => sov_0(ex1_ws_offset to ex1_ws_offset+ex1_ws_q'length-1), + din => ex1_ws_d(0 to ws_width-1), + dout => ex1_ws_q(0 to ws_width-1) ); +ex1_rs_is_latch: tri_rlmreg_p + generic map (width => ex1_rs_is_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex1_rs_is_offset to ex1_rs_is_offset+ex1_rs_is_q'length-1), + scout => sov_0(ex1_rs_is_offset to ex1_rs_is_offset+ex1_rs_is_q'length-1), + din => ex1_rs_is_d(0 to rs_is_width-1), + dout => ex1_rs_is_q(0 to rs_is_width-1) ); +ex1_ra_entry_latch: tri_rlmreg_p + generic map (width => ex1_ra_entry_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex1_ra_entry_offset to ex1_ra_entry_offset+ex1_ra_entry_q'length-1), + scout => sov_0(ex1_ra_entry_offset to ex1_ra_entry_offset+ex1_ra_entry_q'length-1), + din => ex1_ra_entry_d(0 to ra_entry_width-1), + dout => ex1_ra_entry_q(0 to ra_entry_width-1) ); +ex1_state_latch: tri_rlmreg_p + generic map (width => ex1_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex1_state_offset to ex1_state_offset+ex1_state_q'length-1), + scout => sov_0(ex1_state_offset to ex1_state_offset+ex1_state_q'length-1), + din => ex1_state_d(0 to state_width-1), + dout => ex1_state_q(0 to state_width-1) ); +ex1_pid_latch: tri_rlmreg_p + generic map (width => ex1_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex1_pid_offset to ex1_pid_offset+ex1_pid_q'length-1), + scout => sov_0(ex1_pid_offset to ex1_pid_offset+ex1_pid_q'length-1), + din => ex1_pid_d, + dout => ex1_pid_q ); +ex1_extclass_latch: tri_rlmreg_p + generic map (width => ex1_extclass_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex1_extclass_offset to ex1_extclass_offset+ex1_extclass_q'length-1), + scout => sov_0(ex1_extclass_offset to ex1_extclass_offset+ex1_extclass_q'length-1), + din => ex1_extclass_d(0 to extclass_width-1), + dout => ex1_extclass_q(0 to extclass_width-1) ); +ex1_tlbsel_latch: tri_rlmreg_p + generic map (width => ex1_tlbsel_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rf1_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex1_tlbsel_offset to ex1_tlbsel_offset+ex1_tlbsel_q'length-1), + scout => sov_0(ex1_tlbsel_offset to ex1_tlbsel_offset+ex1_tlbsel_q'length-1), + din => ex1_tlbsel_d(0 to tlbsel_width-1), + dout => ex1_tlbsel_q(0 to tlbsel_width-1) ); +------------------------------------------------------------------------------- +ex2_valid_latch: tri_rlmreg_p + generic map (width => ex2_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex2_valid_offset to ex2_valid_offset+ex2_valid_q'length-1), + scout => sov_0(ex2_valid_offset to ex2_valid_offset+ex2_valid_q'length-1), + din => ex2_valid_d(0 to thdid_width-1), + dout => ex2_valid_q(0 to thdid_width-1) ); +ex2_ttype_latch: tri_rlmreg_p + generic map (width => ex2_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex2_ttype_offset to ex2_ttype_offset+ex2_ttype_q'length-1), + scout => sov_0(ex2_ttype_offset to ex2_ttype_offset+ex2_ttype_q'length-1), + din => ex2_ttype_d(0 to ttype_width-1), + dout => ex2_ttype_q(0 to ttype_width-1) ); +ex2_ws_latch: tri_rlmreg_p + generic map (width => ex2_ws_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex2_ws_offset to ex2_ws_offset+ex2_ws_q'length-1), + scout => sov_0(ex2_ws_offset to ex2_ws_offset+ex2_ws_q'length-1), + din => ex2_ws_d(0 to ws_width-1), + dout => ex2_ws_q(0 to ws_width-1) ); +ex2_rs_is_latch: tri_rlmreg_p + generic map (width => ex2_rs_is_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex2_rs_is_offset to ex2_rs_is_offset+ex2_rs_is_q'length-1), + scout => sov_0(ex2_rs_is_offset to ex2_rs_is_offset+ex2_rs_is_q'length-1), + din => ex2_rs_is_d(0 to rs_is_width-1), + dout => ex2_rs_is_q(0 to rs_is_width-1) ); +ex2_ra_entry_latch: tri_rlmreg_p + generic map (width => ex2_ra_entry_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex2_ra_entry_offset to ex2_ra_entry_offset+ex2_ra_entry_q'length-1), + scout => sov_0(ex2_ra_entry_offset to ex2_ra_entry_offset+ex2_ra_entry_q'length-1), + din => ex2_ra_entry_d(0 to ra_entry_width-1), + dout => ex2_ra_entry_q(0 to ra_entry_width-1) ); +ex2_state_latch: tri_rlmreg_p + generic map (width => ex2_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex2_state_offset to ex2_state_offset+ex2_state_q'length-1), + scout => sov_0(ex2_state_offset to ex2_state_offset+ex2_state_q'length-1), + din => ex2_state_d(0 to state_width-1), + dout => ex2_state_q(0 to state_width-1) ); +ex2_pid_latch: tri_rlmreg_p + generic map (width => ex2_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex2_pid_offset to ex2_pid_offset+ex2_pid_q'length-1), + scout => sov_0(ex2_pid_offset to ex2_pid_offset+ex2_pid_q'length-1), + din => ex2_pid_d, + dout => ex2_pid_q ); +ex2_extclass_latch: tri_rlmreg_p + generic map (width => ex2_extclass_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex2_extclass_offset to ex2_extclass_offset+ex2_extclass_q'length-1), + scout => sov_0(ex2_extclass_offset to ex2_extclass_offset+ex2_extclass_q'length-1), + din => ex2_extclass_d(0 to extclass_width-1), + dout => ex2_extclass_q(0 to extclass_width-1) ); +ex2_tlbsel_latch: tri_rlmreg_p + generic map (width => ex2_tlbsel_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex2_tlbsel_offset to ex2_tlbsel_offset+ex2_tlbsel_q'length-1), + scout => sov_0(ex2_tlbsel_offset to ex2_tlbsel_offset+ex2_tlbsel_q'length-1), + din => ex2_tlbsel_d(0 to tlbsel_width-1), + dout => ex2_tlbsel_q(0 to tlbsel_width-1) ); +------------------------------------------------------------------------------- +ex3_valid_latch: tri_rlmreg_p + generic map (width => ex3_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_valid_offset to ex3_valid_offset+ex3_valid_q'length-1), + scout => sov_0(ex3_valid_offset to ex3_valid_offset+ex3_valid_q'length-1), + din => ex3_valid_d(0 to thdid_width-1), + dout => ex3_valid_q(0 to thdid_width-1) ); +ex3_ttype_latch: tri_rlmreg_p + generic map (width => ex3_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_ttype_offset to ex3_ttype_offset+ex3_ttype_q'length-1), + scout => sov_0(ex3_ttype_offset to ex3_ttype_offset+ex3_ttype_q'length-1), + din => ex3_ttype_d(0 to ttype_width-1), + dout => ex3_ttype_q(0 to ttype_width-1) ); +ex3_ws_latch: tri_rlmreg_p + generic map (width => ex3_ws_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_ws_offset to ex3_ws_offset+ex3_ws_q'length-1), + scout => sov_0(ex3_ws_offset to ex3_ws_offset+ex3_ws_q'length-1), + din => ex3_ws_d(0 to ws_width-1), + dout => ex3_ws_q(0 to ws_width-1) ); +ex3_rs_is_latch: tri_rlmreg_p + generic map (width => ex3_rs_is_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_rs_is_offset to ex3_rs_is_offset+ex3_rs_is_q'length-1), + scout => sov_0(ex3_rs_is_offset to ex3_rs_is_offset+ex3_rs_is_q'length-1), + din => ex3_rs_is_d(0 to rs_is_width-1), + dout => ex3_rs_is_q(0 to rs_is_width-1) ); +ex3_ra_entry_latch: tri_rlmreg_p + generic map (width => ex3_ra_entry_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_ra_entry_offset to ex3_ra_entry_offset+ex3_ra_entry_q'length-1), + scout => sov_0(ex3_ra_entry_offset to ex3_ra_entry_offset+ex3_ra_entry_q'length-1), + din => ex3_ra_entry_d(0 to ra_entry_width-1), + dout => ex3_ra_entry_q(0 to ra_entry_width-1) ); +ex3_state_latch: tri_rlmreg_p + generic map (width => ex3_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_state_offset to ex3_state_offset+ex3_state_q'length-1), + scout => sov_0(ex3_state_offset to ex3_state_offset+ex3_state_q'length-1), + din => ex3_state_d(0 to state_width-1), + dout => ex3_state_q(0 to state_width-1) ); +ex3_pid_latch: tri_rlmreg_p + generic map (width => ex3_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_pid_offset to ex3_pid_offset+ex3_pid_q'length-1), + scout => sov_0(ex3_pid_offset to ex3_pid_offset+ex3_pid_q'length-1), + din => ex3_pid_d, + dout => ex3_pid_q ); +ex3_lpid_latch: tri_rlmreg_p + generic map (width => ex3_lpid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_lpid_offset to ex3_lpid_offset+ex3_lpid_q'length-1), + scout => sov_0(ex3_lpid_offset to ex3_lpid_offset+ex3_lpid_q'length-1), + din => ex3_lpid_d, + dout => ex3_lpid_q ); +ex3_extclass_latch: tri_rlmreg_p + generic map (width => ex3_extclass_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_extclass_offset to ex3_extclass_offset+ex3_extclass_q'length-1), + scout => sov_0(ex3_extclass_offset to ex3_extclass_offset+ex3_extclass_q'length-1), + din => ex3_extclass_d(0 to extclass_width-1), + dout => ex3_extclass_q(0 to extclass_width-1) ); +ex3_tlbsel_latch: tri_rlmreg_p + generic map (width => ex3_tlbsel_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_tlbsel_offset to ex3_tlbsel_offset+ex3_tlbsel_q'length-1), + scout => sov_0(ex3_tlbsel_offset to ex3_tlbsel_offset+ex3_tlbsel_q'length-1), + din => ex3_tlbsel_d(0 to tlbsel_width-1), + dout => ex3_tlbsel_q(0 to tlbsel_width-1) ); +------------------------------------------------------------------------------- +ex4_valid_latch: tri_rlmreg_p + generic map (width => ex4_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex4_valid_offset to ex4_valid_offset+ex4_valid_q'length-1), + scout => sov_0(ex4_valid_offset to ex4_valid_offset+ex4_valid_q'length-1), + din => ex4_valid_d(0 to thdid_width-1), + dout => ex4_valid_q(0 to thdid_width-1) ); +ex4_ttype_latch: tri_rlmreg_p + generic map (width => ex4_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex4_ttype_offset to ex4_ttype_offset+ex4_ttype_q'length-1), + scout => sov_0(ex4_ttype_offset to ex4_ttype_offset+ex4_ttype_q'length-1), + din => ex4_ttype_d(0 to ttype_width-1), + dout => ex4_ttype_q(0 to ttype_width-1) ); +ex4_ws_latch: tri_rlmreg_p + generic map (width => ex4_ws_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex4_ws_offset to ex4_ws_offset+ex4_ws_q'length-1), + scout => sov_0(ex4_ws_offset to ex4_ws_offset+ex4_ws_q'length-1), + din => ex4_ws_d(0 to ws_width-1), + dout => ex4_ws_q(0 to ws_width-1) ); +ex4_rs_is_latch: tri_rlmreg_p + generic map (width => ex4_rs_is_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex4_rs_is_offset to ex4_rs_is_offset+ex4_rs_is_q'length-1), + scout => sov_0(ex4_rs_is_offset to ex4_rs_is_offset+ex4_rs_is_q'length-1), + din => ex4_rs_is_d(0 to rs_is_width-1), + dout => ex4_rs_is_q(0 to rs_is_width-1) ); +ex4_ra_entry_latch: tri_rlmreg_p + generic map (width => ex4_ra_entry_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex4_ra_entry_offset to ex4_ra_entry_offset+ex4_ra_entry_q'length-1), + scout => sov_0(ex4_ra_entry_offset to ex4_ra_entry_offset+ex4_ra_entry_q'length-1), + din => ex4_ra_entry_d(0 to ra_entry_width-1), + dout => ex4_ra_entry_q(0 to ra_entry_width-1) ); +ex4_state_latch: tri_rlmreg_p + generic map (width => ex4_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex4_state_offset to ex4_state_offset+ex4_state_q'length-1), + scout => sov_0(ex4_state_offset to ex4_state_offset+ex4_state_q'length-1), + din => ex4_state_d(0 to state_width-1), + dout => ex4_state_q(0 to state_width-1) ); +ex4_pid_latch: tri_rlmreg_p + generic map (width => ex4_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex4_pid_offset to ex4_pid_offset+ex4_pid_q'length-1), + scout => sov_0(ex4_pid_offset to ex4_pid_offset+ex4_pid_q'length-1), + din => ex4_pid_d, + dout => ex4_pid_q ); +ex4_extclass_latch: tri_rlmreg_p + generic map (width => ex4_extclass_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex4_extclass_offset to ex4_extclass_offset+ex4_extclass_q'length-1), + scout => sov_0(ex4_extclass_offset to ex4_extclass_offset+ex4_extclass_q'length-1), + din => ex4_extclass_d(0 to extclass_width-1), + dout => ex4_extclass_q(0 to extclass_width-1) ); +ex4_tlbsel_latch: tri_rlmreg_p + generic map (width => ex4_tlbsel_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex4_tlbsel_offset to ex4_tlbsel_offset+ex4_tlbsel_q'length-1), + scout => sov_0(ex4_tlbsel_offset to ex4_tlbsel_offset+ex4_tlbsel_q'length-1), + din => ex4_tlbsel_d(0 to tlbsel_width-1), + dout => ex4_tlbsel_q(0 to tlbsel_width-1) ); +------------------------------------------------------------------------------- +ex5_valid_latch: tri_rlmreg_p + generic map (width => ex5_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex5_valid_offset to ex5_valid_offset+ex5_valid_q'length-1), + scout => sov_0(ex5_valid_offset to ex5_valid_offset+ex5_valid_q'length-1), + din => ex5_valid_d(0 to thdid_width-1), + dout => ex5_valid_q(0 to thdid_width-1) ); +ex5_ttype_latch: tri_rlmreg_p + generic map (width => ex5_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex5_ttype_offset to ex5_ttype_offset+ex5_ttype_q'length-1), + scout => sov_0(ex5_ttype_offset to ex5_ttype_offset+ex5_ttype_q'length-1), + din => ex5_ttype_d(0 to ttype_width-1), + dout => ex5_ttype_q(0 to ttype_width-1) ); +ex5_ws_latch: tri_rlmreg_p + generic map (width => ex5_ws_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex5_ws_offset to ex5_ws_offset+ex5_ws_q'length-1), + scout => sov_0(ex5_ws_offset to ex5_ws_offset+ex5_ws_q'length-1), + din => ex5_ws_d(0 to ws_width-1), + dout => ex5_ws_q(0 to ws_width-1) ); +ex5_rs_is_latch: tri_rlmreg_p + generic map (width => ex5_rs_is_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex5_rs_is_offset to ex5_rs_is_offset+ex5_rs_is_q'length-1), + scout => sov_0(ex5_rs_is_offset to ex5_rs_is_offset+ex5_rs_is_q'length-1), + din => ex5_rs_is_d(0 to rs_is_width-1), + dout => ex5_rs_is_q(0 to rs_is_width-1) ); +ex5_ra_entry_latch: tri_rlmreg_p + generic map (width => ex5_ra_entry_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex5_ra_entry_offset to ex5_ra_entry_offset+ex5_ra_entry_q'length-1), + scout => sov_0(ex5_ra_entry_offset to ex5_ra_entry_offset+ex5_ra_entry_q'length-1), + din => ex5_ra_entry_d(0 to ra_entry_width-1), + dout => ex5_ra_entry_q(0 to ra_entry_width-1) ); +ex5_state_latch: tri_rlmreg_p + generic map (width => ex5_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex5_state_offset to ex5_state_offset+ex5_state_q'length-1), + scout => sov_0(ex5_state_offset to ex5_state_offset+ex5_state_q'length-1), + din => ex5_state_d(0 to state_width-1), + dout => ex5_state_q(0 to state_width-1) ); +ex5_pid_latch: tri_rlmreg_p + generic map (width => ex5_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex5_pid_offset to ex5_pid_offset+ex5_pid_q'length-1), + scout => sov_0(ex5_pid_offset to ex5_pid_offset+ex5_pid_q'length-1), + din => ex5_pid_d, + dout => ex5_pid_q ); +ex5_extclass_latch: tri_rlmreg_p + generic map (width => ex5_extclass_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex5_extclass_offset to ex5_extclass_offset+ex5_extclass_q'length-1), + scout => sov_0(ex5_extclass_offset to ex5_extclass_offset+ex5_extclass_q'length-1), + din => ex5_extclass_d(0 to extclass_width-1), + dout => ex5_extclass_q(0 to extclass_width-1) ); +ex5_tlbsel_latch: tri_rlmreg_p + generic map (width => ex5_tlbsel_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex5_tlbsel_offset to ex5_tlbsel_offset+ex5_tlbsel_q'length-1), + scout => sov_0(ex5_tlbsel_offset to ex5_tlbsel_offset+ex5_tlbsel_q'length-1), + din => ex5_tlbsel_d(0 to tlbsel_width-1), + dout => ex5_tlbsel_q(0 to tlbsel_width-1) ); +-------------------------------------------------- +ex5_data_in_latch: tri_rlmreg_p + generic map (width => ex5_data_in_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex5_data_in_offset to ex5_data_in_offset+ex5_data_in_q'length-1), + scout => sov_0(ex5_data_in_offset to ex5_data_in_offset+ex5_data_in_q'length-1), + din => ex5_data_in_d(64-rs_data_width to 63), + dout => ex5_data_in_q(64-rs_data_width to 63) ); +------------------------------------------------------------------------------- +ex6_valid_latch: tri_rlmreg_p + generic map (width => ex6_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex6_valid_offset to ex6_valid_offset+ex6_valid_q'length-1), + scout => sov_0(ex6_valid_offset to ex6_valid_offset+ex6_valid_q'length-1), + din => ex6_valid_d(0 to thdid_width-1), + dout => ex6_valid_q(0 to thdid_width-1) ); +ex6_ttype_latch: tri_rlmreg_p + generic map (width => ex6_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex6_ttype_offset to ex6_ttype_offset+ex6_ttype_q'length-1), + scout => sov_0(ex6_ttype_offset to ex6_ttype_offset+ex6_ttype_q'length-1), + din => ex6_ttype_d(0 to ttype_width-1), + dout => ex6_ttype_q(0 to ttype_width-1) ); +ex6_ws_latch: tri_rlmreg_p + generic map (width => ex6_ws_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex5_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex6_ws_offset to ex6_ws_offset+ex6_ws_q'length-1), + scout => sov_0(ex6_ws_offset to ex6_ws_offset+ex6_ws_q'length-1), + din => ex6_ws_d(0 to ws_width-1), + dout => ex6_ws_q(0 to ws_width-1) ); +ex6_rs_is_latch: tri_rlmreg_p + generic map (width => ex6_rs_is_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex5_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex6_rs_is_offset to ex6_rs_is_offset+ex6_rs_is_q'length-1), + scout => sov_0(ex6_rs_is_offset to ex6_rs_is_offset+ex6_rs_is_q'length-1), + din => ex6_rs_is_d(0 to rs_is_width-1), + dout => ex6_rs_is_q(0 to rs_is_width-1) ); +ex6_ra_entry_latch: tri_rlmreg_p + generic map (width => ex6_ra_entry_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex5_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex6_ra_entry_offset to ex6_ra_entry_offset+ex6_ra_entry_q'length-1), + scout => sov_0(ex6_ra_entry_offset to ex6_ra_entry_offset+ex6_ra_entry_q'length-1), + din => ex6_ra_entry_d(0 to ra_entry_width-1), + dout => ex6_ra_entry_q(0 to ra_entry_width-1) ); +ex6_state_latch: tri_rlmreg_p + generic map (width => ex6_state_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex5_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex6_state_offset to ex6_state_offset+ex6_state_q'length-1), + scout => sov_0(ex6_state_offset to ex6_state_offset+ex6_state_q'length-1), + din => ex6_state_d(0 to state_width-1), + dout => ex6_state_q(0 to state_width-1) ); +ex6_pid_latch: tri_rlmreg_p + generic map (width => ex6_pid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex5_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex6_pid_offset to ex6_pid_offset+ex6_pid_q'length-1), + scout => sov_0(ex6_pid_offset to ex6_pid_offset+ex6_pid_q'length-1), + din => ex6_pid_d, + dout => ex6_pid_q ); +ex6_extclass_latch: tri_rlmreg_p + generic map (width => ex6_extclass_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex5_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex6_extclass_offset to ex6_extclass_offset+ex6_extclass_q'length-1), + scout => sov_0(ex6_extclass_offset to ex6_extclass_offset+ex6_extclass_q'length-1), + din => ex6_extclass_d(0 to extclass_width-1), + dout => ex6_extclass_q(0 to extclass_width-1) ); +ex6_tlbsel_latch: tri_rlmreg_p + generic map (width => ex6_tlbsel_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex5_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex6_tlbsel_offset to ex6_tlbsel_offset+ex6_tlbsel_q'length-1), + scout => sov_0(ex6_tlbsel_offset to ex6_tlbsel_offset+ex6_tlbsel_q'length-1), + din => ex6_tlbsel_d(0 to tlbsel_width-1), + dout => ex6_tlbsel_q(0 to tlbsel_width-1) ); +-------------------------------------------------- +ex6_data_in_latch: tri_rlmreg_p + generic map (width => ex6_data_in_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex5_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex6_data_in_offset to ex6_data_in_offset+ex6_data_in_q'length-1), + scout => sov_0(ex6_data_in_offset to ex6_data_in_offset+ex6_data_in_q'length-1), + din => ex6_data_in_d(64-rs_data_width to 63), + dout => ex6_data_in_q(64-rs_data_width to 63) ); +------------------------------------------------------------------------------- +ex7_valid_latch: tri_rlmreg_p + generic map (width => ex7_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex7_valid_offset to ex7_valid_offset+ex7_valid_q'length-1), + scout => sov_0(ex7_valid_offset to ex7_valid_offset+ex7_valid_q'length-1), + din => ex7_valid_d(0 to thdid_width-1), + dout => ex7_valid_q(0 to thdid_width-1) ); +ex7_ttype_latch: tri_rlmreg_p + generic map (width => ex7_ttype_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex7_ttype_offset to ex7_ttype_offset+ex7_ttype_q'length-1), + scout => sov_0(ex7_ttype_offset to ex7_ttype_offset+ex7_ttype_q'length-1), + din => ex7_ttype_d(0 to ttype_width-1), + dout => ex7_ttype_q(0 to ttype_width-1) ); +ex7_tlbsel_latch: tri_rlmreg_p + generic map (width => ex7_tlbsel_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex7_tlbsel_offset to ex7_tlbsel_offset+ex7_tlbsel_q'length-1), + scout => sov_0(ex7_tlbsel_offset to ex7_tlbsel_offset+ex7_tlbsel_q'length-1), + din => ex7_tlbsel_d(0 to tlbsel_width-1), + dout => ex7_tlbsel_q(0 to tlbsel_width-1) ); +-------------------------------------------------- +ex4_data_out_latch: tri_rlmreg_p + generic map (width => ex4_data_out_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_data_out_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex4_data_out_offset to ex4_data_out_offset+ex4_data_out_q'length-1), + scout => sov_0(ex4_data_out_offset to ex4_data_out_offset+ex4_data_out_q'length-1), + din => ex4_data_out_d(64-data_out_width to 63), + dout => ex4_data_out_q(64-data_out_width to 63) ); +ex2_n_flush_req_latch: tri_rlmreg_p + generic map (width => ex2_n_flush_req_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex2_n_flush_req_offset to ex2_n_flush_req_offset+ex2_n_flush_req_q'length-1), + scout => sov_0(ex2_n_flush_req_offset to ex2_n_flush_req_offset+ex2_n_flush_req_q'length-1), + din => ex2_n_flush_req_d(0 to thdid_width-1), + dout => ex2_n_flush_req_q(0 to thdid_width-1) ); +ex3_n_flush_req_latch: tri_rlmreg_p + generic map (width => ex3_n_flush_req_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_n_flush_req_offset to ex3_n_flush_req_offset+ex3_n_flush_req_q'length-1), + scout => sov_0(ex3_n_flush_req_offset to ex3_n_flush_req_offset+ex3_n_flush_req_q'length-1), + din => ex3_n_flush_req_d(0 to thdid_width-1), + dout => ex3_n_flush_req_q(0 to thdid_width-1) ); +hold_req_reset_latch: tri_rlmreg_p + generic map (width => hold_req_reset_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(hold_req_reset_offset to hold_req_reset_offset+hold_req_reset_q'length-1), + scout => sov_0(hold_req_reset_offset to hold_req_reset_offset+hold_req_reset_q'length-1), + din => hold_req_reset_d(0 to thdid_width-1), + dout => hold_req_reset_q(0 to thdid_width-1) ); +hold_req_pot_set_latch: tri_rlmreg_p + generic map (width => hold_req_pot_set_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(hold_req_pot_set_offset to hold_req_pot_set_offset+hold_req_pot_set_q'length-1), + scout => sov_0(hold_req_pot_set_offset to hold_req_pot_set_offset+hold_req_pot_set_q'length-1), + din => hold_req_pot_set_d(0 to thdid_width-1), + dout => hold_req_pot_set_q(0 to thdid_width-1) ); +hold_req_por_latch: tri_rlmreg_p + generic map (width => hold_req_por_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(hold_req_por_offset to hold_req_por_offset+hold_req_por_q'length-1), + scout => sov_0(hold_req_por_offset to hold_req_por_offset+hold_req_por_q'length-1), + din => hold_req_por_d(0 to thdid_width-1), + dout => hold_req_por_q(0 to thdid_width-1) ); +hold_req_latch: tri_rlmreg_p + generic map (width => hold_req_q'length, init => 15, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(hold_req_offset to hold_req_offset+hold_req_q'length-1), + scout => sov_0(hold_req_offset to hold_req_offset+hold_req_q'length-1), + din => hold_req_d(0 to thdid_width-1), + dout => hold_req_q(0 to thdid_width-1) ); +tlb_req_inprogress_latch: tri_rlmreg_p + generic map (width => tlb_req_inprogress_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(tlb_req_inprogress_offset to tlb_req_inprogress_offset+tlb_req_inprogress_q'length-1), + scout => sov_0(tlb_req_inprogress_offset to tlb_req_inprogress_offset+tlb_req_inprogress_q'length-1), + din => tlb_req_inprogress_d(0 to thdid_width-1), + dout => tlb_req_inprogress_q(0 to thdid_width-1) ); +ex2_dsi_latch: tri_rlmreg_p + generic map (width => ex2_dsi_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex2_dsi_offset to ex2_dsi_offset+ex2_dsi_q'length-1), + scout => sov_0(ex2_dsi_offset to ex2_dsi_offset+ex2_dsi_q'length-1), + din => ex2_dsi_d, + dout => ex2_dsi_q); +ex2_noop_touch_latch: tri_rlmreg_p + generic map (width => ex2_noop_touch_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex2_noop_touch_offset to ex2_noop_touch_offset+ex2_noop_touch_q'length-1), + scout => sov_0(ex2_noop_touch_offset to ex2_noop_touch_offset+ex2_noop_touch_q'length-1), + din => ex2_noop_touch_d, + dout => ex2_noop_touch_q); +ex3_miss_latch: tri_rlmreg_p + generic map (width => ex3_miss_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_or_ex3_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_miss_offset to ex3_miss_offset+ex3_miss_q'length-1), + scout => sov_0(ex3_miss_offset to ex3_miss_offset+ex3_miss_q'length-1), + din => ex3_miss_d(0 to thdid_width-1), + dout => ex3_miss_q(0 to thdid_width-1)); +ex3_dsi_latch: tri_rlmreg_p + generic map (width => ex3_dsi_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_dsi_offset to ex3_dsi_offset+ex3_dsi_q'length-1), + scout => sov_0(ex3_dsi_offset to ex3_dsi_offset+ex3_dsi_q'length-1), + din => ex3_dsi_d, + dout => ex3_dsi_q); +ex3_noop_touch_latch: tri_rlmreg_p + generic map (width => ex3_noop_touch_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_or_ex3_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_noop_touch_offset to ex3_noop_touch_offset+ex3_noop_touch_q'length-1), + scout => sov_0(ex3_noop_touch_offset to ex3_noop_touch_offset+ex3_noop_touch_q'length-1), + din => ex3_noop_touch_d, + dout => ex3_noop_touch_q); +ex3_multihit_latch: tri_rlmreg_p + generic map (width => ex3_multihit_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_or_ex3_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_multihit_offset to ex3_multihit_offset+ex3_multihit_q'length-1), + scout => sov_0(ex3_multihit_offset to ex3_multihit_offset+ex3_multihit_q'length-1), + din => ex3_multihit_d(0 to thdid_width-1), + dout => ex3_multihit_q(0 to thdid_width-1)); +ex3_multihit_b_pt_latch: tri_rlmreg_p + generic map (width => ex3_multihit_b_pt_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_or_ex3_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_multihit_b_pt_offset to ex3_multihit_b_pt_offset+ex3_multihit_b_pt_q'length-1), + scout => sov_0(ex3_multihit_b_pt_offset to ex3_multihit_b_pt_offset+ex3_multihit_b_pt_q'length-1), + din => ex3_multihit_b_pt_d, + dout => ex3_multihit_b_pt_q); +ex3_first_hit_entry_pt_latch: tri_rlmreg_p + generic map (width => ex3_first_hit_entry_pt_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_or_ex3_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_first_hit_entry_pt_offset to ex3_first_hit_entry_pt_offset+ex3_first_hit_entry_pt_q'length-1), + scout => sov_0(ex3_first_hit_entry_pt_offset to ex3_first_hit_entry_pt_offset+ex3_first_hit_entry_pt_q'length-1), + din => ex3_first_hit_entry_pt_d, + dout => ex3_first_hit_entry_pt_q); +ex3_parerr_latch: tri_rlmreg_p + generic map (width => ex3_parerr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => not_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_parerr_offset to ex3_parerr_offset+ex3_parerr_q'length-1), + scout => sov_0(ex3_parerr_offset to ex3_parerr_offset+ex3_parerr_q'length-1), + din => ex3_parerr_d, + dout => ex3_parerr_q); +ex3_attr_latch: tri_rlmreg_p + generic map (width => ex3_attr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_attr_offset to ex3_attr_offset+ex3_attr_q'length-1), + scout => sov_0(ex3_attr_offset to ex3_attr_offset+ex3_attr_q'length-1), + din => ex3_attr_q(0 to 5), + dout => ex3_attr_q(0 to 5)); +ex3_tlbreq_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => notlb_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_tlbreq_offset), + scout => sov_0(ex3_tlbreq_offset), + din => ex3_tlbreq_d, + dout => ex3_tlbreq_q); +ex3_cam_hit_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_or_ex3_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_cam_hit_offset), + scout => sov_0(ex3_cam_hit_offset), + din => cam_hit, + dout => ex3_cam_hit_q); +ex3_hit_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_or_ex3_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_hit_offset), + scout => sov_0(ex3_hit_offset), + din => ex3_hit_d, + dout => ex3_hit_q); +ex2_debug_latch: tri_rlmreg_p + generic map (width => ex2_debug_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => trace_bus_enable_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex2_debug_offset to ex2_debug_offset+ex2_debug_q'length-1), + scout => sov_0(ex2_debug_offset to ex2_debug_offset+ex2_debug_q'length-1), + din => ex2_debug_d, + dout => ex2_debug_q); +ex3_debug_latch: tri_rlmreg_p + generic map (width => ex3_debug_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => debug_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(ex3_debug_offset to ex3_debug_offset+ex3_debug_q'length-1), + scout => sov_0(ex3_debug_offset to ex3_debug_offset+ex3_debug_q'length-1), + din => ex3_debug_d, + dout => ex3_debug_q); +ex4_rd_array_data_latch: tri_rlmreg_p + generic map (width => ex4_rd_array_data_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_rd_data_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ex4_rd_array_data_offset to ex4_rd_array_data_offset+ex4_rd_array_data_q'length-1), + scout => sov_1(ex4_rd_array_data_offset to ex4_rd_array_data_offset+ex4_rd_array_data_q'length-1), + din => ex4_rd_array_data_d(0 to array_data_width-1), + dout => ex4_rd_array_data_q(0 to array_data_width-1)); +ex4_rd_cam_data_latch: tri_rlmreg_p + generic map (width => ex4_rd_cam_data_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_rd_data_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ex4_rd_cam_data_offset to ex4_rd_cam_data_offset+ex4_rd_cam_data_q'length-1), + scout => sov_1(ex4_rd_cam_data_offset to ex4_rd_cam_data_offset+ex4_rd_cam_data_q'length-1), + din => ex4_rd_cam_data_d(0 to cam_data_width-1), + dout => ex4_rd_cam_data_q(0 to cam_data_width-1)); +ex4_parerr_latch: tri_rlmreg_p + generic map (width => ex4_parerr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ex4_parerr_offset to ex4_parerr_offset+ex4_parerr_q'length-1), + scout => sov_1(ex4_parerr_offset to ex4_parerr_offset+ex4_parerr_q'length-1), + din => ex4_parerr_d, + dout => ex4_parerr_q); +ex4_fir_parerr_latch: tri_rlmreg_p + generic map (width => ex4_fir_parerr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ex4_fir_parerr_offset to ex4_fir_parerr_offset+ex4_fir_parerr_q'length-1), + scout => sov_1(ex4_fir_parerr_offset to ex4_fir_parerr_offset+ex4_fir_parerr_q'length-1), + din => ex4_fir_parerr_d, + dout => ex4_fir_parerr_q); +ex4_fir_multihit_latch: tri_rlmreg_p + generic map (width => ex4_fir_multihit_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ex4_fir_multihit_offset to ex4_fir_multihit_offset+ex4_fir_multihit_q'length-1), + scout => sov_1(ex4_fir_multihit_offset to ex4_fir_multihit_offset+ex4_fir_multihit_q'length-1), + din => ex4_fir_multihit_d(0 to thdid_width-1), + dout => ex4_fir_multihit_q(0 to thdid_width-1)); +ex4_deen_latch: tri_rlmreg_p + generic map (width => ex4_deen_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ex4_deen_offset to ex4_deen_offset+ex4_deen_q'length-1), + scout => sov_1(ex4_deen_offset to ex4_deen_offset+ex4_deen_q'length-1), + din => ex4_deen_d(0 to ex4_deen_d'length-1), + dout => ex4_deen_q(0 to ex4_deen_q'length-1)); +ex4_hit_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ex4_hit_offset), + scout => sov_1(ex4_hit_offset), + din => ex4_hit_d, + dout => ex4_hit_q); +ex5_deen_latch: tri_rlmreg_p + generic map (width => ex5_deen_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ex5_deen_offset to ex5_deen_offset+ex5_deen_q'length-1), + scout => sov_1(ex5_deen_offset to ex5_deen_offset+ex5_deen_q'length-1), + din => ex5_deen_d(0 to ex5_deen_d'length-1), + dout => ex5_deen_q(0 to ex5_deen_q'length-1)); +ex5_hit_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ex5_hit_offset), + scout => sov_1(ex5_hit_offset), + din => ex5_hit_d, + dout => ex5_hit_q); +ex6_deen_latch: tri_rlmreg_p + generic map (width => ex6_deen_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ex6_deen_offset to ex6_deen_offset+ex6_deen_q'length-1), + scout => sov_1(ex6_deen_offset to ex6_deen_offset+ex6_deen_q'length-1), + din => ex6_deen_d(0 to ex6_deen_d'length-1), + dout => ex6_deen_q(0 to ex6_deen_q'length-1)); +ex6_hit_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ex6_hit_offset), + scout => sov_1(ex6_hit_offset), + din => ex6_hit_d, + dout => ex6_hit_q); +barrier_done_latch: tri_rlmreg_p + generic map (width => barrier_done_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(barrier_done_offset to barrier_done_offset+barrier_done_q'length-1), + scout => sov_1(barrier_done_offset to barrier_done_offset+barrier_done_q'length-1), + din => barrier_done_d(0 to barrier_done_d'length-1), + dout => barrier_done_q(0 to barrier_done_q'length-1)); +mchk_flash_inv_latch: tri_rlmreg_p + generic map (width => mchk_flash_inv_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_to_ex6_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mchk_flash_inv_offset to mchk_flash_inv_offset+mchk_flash_inv_q'length-1), + scout => sov_1(mchk_flash_inv_offset to mchk_flash_inv_offset+mchk_flash_inv_q'length-1), + din => mchk_flash_inv_d(0 to mchk_flash_inv_d'length-1), + dout => mchk_flash_inv_q(0 to mchk_flash_inv_q'length-1)); +mmucr1_latch: tri_rlmreg_p + generic map (width => mmucr1_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mmucr1_offset to mmucr1_offset+mmucr1_q'length-1), + scout => sov_1(mmucr1_offset to mmucr1_offset+mmucr1_q'length-1), + din => mmucr1_d, + dout => mmucr1_q ); +rpn_holdreg0_latch: tri_rlmreg_p + generic map (width => rpn_holdreg0_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex6_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(rpn_holdreg0_offset to rpn_holdreg0_offset+rpn_holdreg0_q'length-1), + scout => sov_1(rpn_holdreg0_offset to rpn_holdreg0_offset+rpn_holdreg0_q'length-1), + din => rpn_holdreg0_d(0 to 63), + dout => rpn_holdreg0_q(0 to 63) ); +rpn_holdreg1_latch: tri_rlmreg_p + generic map (width => rpn_holdreg1_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex6_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(rpn_holdreg1_offset to rpn_holdreg1_offset+rpn_holdreg1_q'length-1), + scout => sov_1(rpn_holdreg1_offset to rpn_holdreg1_offset+rpn_holdreg1_q'length-1), + din => rpn_holdreg1_d(0 to 63), + dout => rpn_holdreg1_q(0 to 63) ); +rpn_holdreg2_latch: tri_rlmreg_p + generic map (width => rpn_holdreg2_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex6_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(rpn_holdreg2_offset to rpn_holdreg2_offset+rpn_holdreg2_q'length-1), + scout => sov_1(rpn_holdreg2_offset to rpn_holdreg2_offset+rpn_holdreg2_q'length-1), + din => rpn_holdreg2_d(0 to 63), + dout => rpn_holdreg2_q(0 to 63) ); +rpn_holdreg3_latch: tri_rlmreg_p + generic map (width => rpn_holdreg3_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex6_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(rpn_holdreg3_offset to rpn_holdreg3_offset+rpn_holdreg3_q'length-1), + scout => sov_1(rpn_holdreg3_offset to rpn_holdreg3_offset+rpn_holdreg3_q'length-1), + din => rpn_holdreg3_d(0 to 63), + dout => rpn_holdreg3_q(0 to 63) ); +entry_valid_latch: tri_rlmreg_p + generic map (width => entry_valid_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => entry_valid_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(entry_valid_offset to entry_valid_offset+entry_valid_q'length-1), + scout => sov_1(entry_valid_offset to entry_valid_offset+entry_valid_q'length-1), + din => entry_valid, + dout => entry_valid_q ); +entry_match_latch: tri_rlmreg_p + generic map (width => entry_match_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => entry_match_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(entry_match_offset to entry_match_offset+entry_match_q'length-1), + scout => sov_1(entry_match_offset to entry_match_offset+entry_match_q'length-1), + din => entry_match, + dout => entry_match_q ); +watermark_latch: tri_rlmreg_p + generic map (width => watermark_q'length, init => 29, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex6_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(watermark_offset to watermark_offset+watermark_q'length-1), + scout => sov_1(watermark_offset to watermark_offset+watermark_q'length-1), + din => watermark_d(0 to watermark_width-1), + dout => watermark_q(0 to watermark_width-1) ); +mmucr1_b0_cpy_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(mmucr1_b0_cpy_offset), + scout => sov_1(mmucr1_b0_cpy_offset), + din => mmucr1_b0_cpy_d, + dout => mmucr1_b0_cpy_q); +lru_rmt_vec_latch: tri_rlmreg_p + generic map (width => lru_rmt_vec_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex6_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(lru_rmt_vec_offset to lru_rmt_vec_offset+lru_rmt_vec_q'length-1), + scout => sov_1(lru_rmt_vec_offset to lru_rmt_vec_offset+lru_rmt_vec_q'length-1), + din => lru_rmt_vec_d, + dout => lru_rmt_vec_q ); +eptr_latch: tri_rlmreg_p + generic map (width => eptr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => mmucr1_q(0), + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(eptr_offset to eptr_offset+eptr_q'length-1), + scout => sov_1(eptr_offset to eptr_offset+eptr_q'length-1), + din => eptr_d(0 to eptr_width-1), + dout => eptr_q(0 to eptr_width-1) ); +lru_latch: tri_rlmreg_p + generic map (width => lru_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => lru_update_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(lru_offset to lru_offset+lru_q'length-1), + scout => sov_1(lru_offset to lru_offset+lru_q'length-1), + din => lru_d(1 to lru_width), + dout => lru_q(1 to lru_width) ); +lru_update_event_latch: tri_rlmreg_p + generic map (width => lru_update_event_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => not_grffence_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(lru_update_event_offset to lru_update_event_offset+lru_update_event_q'length-1), + scout => sov_1(lru_update_event_offset to lru_update_event_offset+lru_update_event_q'length-1), + din => lru_update_event_d, + dout => lru_update_event_q ); +lru_debug_latch: tri_rlmreg_p + generic map (width => lru_debug_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => trace_bus_enable_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(lru_debug_offset to lru_debug_offset+lru_debug_q'length-1), + scout => sov_1(lru_debug_offset to lru_debug_offset+lru_debug_q'length-1), + din => lru_debug_d, + dout => lru_debug_q ); +snoop_val_latch: tri_rlmreg_p + generic map (width => snoop_val_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(snoop_val_offset to snoop_val_offset+snoop_val_q'length-1), + scout => sov_1(snoop_val_offset to snoop_val_offset+snoop_val_q'length-1), + din => snoop_val_d, + dout => snoop_val_q ); +snoop_attr_latch: tri_rlmreg_p + generic map (width => snoop_attr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => snoop_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(snoop_attr_offset to snoop_attr_offset+snoop_attr_q'length-1), + scout => sov_1(snoop_attr_offset to snoop_attr_offset+snoop_attr_q'length-1), + din => snoop_attr_d, + dout => snoop_attr_q ); +snoop_addr_latch: tri_rlmreg_p + generic map (width => snoop_addr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => snoop_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(snoop_addr_offset to snoop_addr_offset+snoop_addr_q'length-1), + scout => sov_1(snoop_addr_offset to snoop_addr_offset+snoop_addr_q'length-1), + din => snoop_addr_d(52-epn_width to 51), + dout => snoop_addr_q(52-epn_width to 51) ); +ex2_epn_latch: tri_rlmreg_p + generic map (width => ex2_epn_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_q, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ex2_epn_offset to ex2_epn_offset+ex2_epn_q'length-1), + scout => sov_1(ex2_epn_offset to ex2_epn_offset+ex2_epn_q'length-1), + din => ex2_epn_d(52-ex2_epn_width to 51), + dout => ex2_epn_q(52-ex2_epn_width to 51) ); +por_seq_latch: tri_rlmreg_p + generic map (width => por_seq_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(por_seq_offset to por_seq_offset+por_seq_q'length-1), + scout => sov_1(por_seq_offset to por_seq_offset+por_seq_q'length-1), + din => por_seq_d(0 to por_seq_width-1), + dout => por_seq_q(0 to por_seq_width-1) ); +pc_xu_init_reset_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(pc_xu_init_reset_offset), + scout => sov_1(pc_xu_init_reset_offset), + din => pc_xu_init_reset, + dout => pc_xu_init_reset_q); +-- timing latches for reloads +tlb_rel_val_latch: tri_rlmreg_p + generic map (width => tlb_rel_val_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(tlb_rel_val_offset to tlb_rel_val_offset+tlb_rel_val_q'length-1), + scout => sov_1(tlb_rel_val_offset to tlb_rel_val_offset+tlb_rel_val_q'length-1), + din => tlb_rel_val_d, + dout => tlb_rel_val_q ); +tlb_rel_data_latch: tri_rlmreg_p + generic map (width => tlb_rel_data_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tlb_rel_act, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(tlb_rel_data_offset to tlb_rel_data_offset+tlb_rel_data_q'length-1), + scout => sov_1(tlb_rel_data_offset to tlb_rel_data_offset+tlb_rel_data_q'length-1), + din => tlb_rel_data_d, + dout => tlb_rel_data_q ); +eplc_wr_latch: tri_rlmreg_p + generic map (width => eplc_wr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(eplc_wr_offset to eplc_wr_offset+eplc_wr_q'length-1), + scout => sov_1(eplc_wr_offset to eplc_wr_offset+eplc_wr_q'length-1), + din => eplc_wr_d, + dout => eplc_wr_q ); +epsc_wr_latch: tri_rlmreg_p + generic map (width => epsc_wr_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(epsc_wr_offset to epsc_wr_offset+epsc_wr_q'length-1), + scout => sov_1(epsc_wr_offset to epsc_wr_offset+epsc_wr_q'length-1), + din => epsc_wr_d, + dout => epsc_wr_q ); +ccr2_frat_paranoia_latch: tri_rlmreg_p + generic map (width => ccr2_frat_paranoia_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ccr2_frat_paranoia_offset to ccr2_frat_paranoia_offset+ccr2_frat_paranoia_q'length-1), + scout => sov_1(ccr2_frat_paranoia_offset to ccr2_frat_paranoia_offset+ccr2_frat_paranoia_q'length-1), + din => ccr2_frat_paranoia_d, + dout => ccr2_frat_paranoia_q ); +ccr2_notlb_latch: tri_rlmlatch_p + generic map (init => 1, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ccr2_notlb_offset), + scout => sov_1(ccr2_notlb_offset), + din => xu_derat_hid_mmu_mode, + dout => ccr2_notlb_q); +xucr4_mmu_mchk_latch: tri_rlmlatch_p + generic map (init => 1, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(xucr4_mmu_mchk_offset), + scout => sov_1(xucr4_mmu_mchk_offset), + din => spr_xucr4_mmu_mchk, + dout => xucr4_mmu_mchk_q); +clkg_ctl_override_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(clkg_ctl_override_offset), + scout => sov_1(clkg_ctl_override_offset), + din => clkg_ctl_override_d, + dout => clkg_ctl_override_q); +rf1_stg_act_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(rf1_stg_act_offset), + scout => sov_1(rf1_stg_act_offset), + din => rf1_stg_act_d, + dout => rf1_stg_act_q); +ex1_stg_act_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ex1_stg_act_offset), + scout => sov_1(ex1_stg_act_offset), + din => ex1_stg_act_d, + dout => ex1_stg_act_q); +ex2_stg_act_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ex2_stg_act_offset), + scout => sov_1(ex2_stg_act_offset), + din => ex2_stg_act_d, + dout => ex2_stg_act_q); +ex3_stg_act_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ex3_stg_act_offset), + scout => sov_1(ex3_stg_act_offset), + din => ex3_stg_act_d, + dout => ex3_stg_act_q); +ex4_stg_act_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ex4_stg_act_offset), + scout => sov_1(ex4_stg_act_offset), + din => ex4_stg_act_d, + dout => ex4_stg_act_q); +ex5_stg_act_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ex5_stg_act_offset), + scout => sov_1(ex5_stg_act_offset), + din => ex5_stg_act_d, + dout => ex5_stg_act_q); +ex6_stg_act_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ex6_stg_act_offset), + scout => sov_1(ex6_stg_act_offset), + din => ex6_stg_act_d, + dout => ex6_stg_act_q); +ex7_stg_act_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(ex7_stg_act_offset), + scout => sov_1(ex7_stg_act_offset), + din => ex7_stg_act_d, + dout => ex7_stg_act_q); +tlb_rel_act_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(tlb_rel_act_offset), + scout => sov_1(tlb_rel_act_offset), + din => tlb_rel_act_d, + dout => tlb_rel_act_q); +snoop_act_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(snoop_act_offset), + scout => sov_1(snoop_act_offset), + din => mm_xu_derat_snoop_coming, + dout => snoop_act_q); +-- for debug trace bus latch act +trace_bus_enable_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(trace_bus_enable_offset), + scout => sov_1(trace_bus_enable_offset), + din => pc_xu_trace_bus_enable, + dout => trace_bus_enable_q); +an_ac_grffence_en_dc_latch: tri_rlmlatch_p + generic map (init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(an_ac_grffence_en_dc_offset), + scout => sov_1(an_ac_grffence_en_dc_offset), + din => an_ac_grffence_en_dc_q, + dout => an_ac_grffence_en_dc_q); +spare_a_latch: tri_rlmreg_p + generic map (width => spare_a_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_0(spare_a_offset to spare_a_offset+spare_a_q'length-1), + scout => sov_0(spare_a_offset to spare_a_offset+spare_a_q'length-1), + din => spare_a_q, + dout => spare_a_q ); +spare_b_latch: tri_rlmreg_p + generic map (width => spare_b_q'length, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_func_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_func_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => siv_1(spare_b_offset to spare_b_offset+spare_b_q'length-1), + scout => sov_1(spare_b_offset to spare_b_offset+spare_b_q'length-1), + din => spare_b_q, + dout => spare_b_q ); +-------------------------------------------------- +-- scan only latches for boot config +-------------------------------------------------- +mpg_bcfg_gen: if expand_type /= 1 generate +bcfg_epn_0to15_latch: tri_slat_scan + generic map (width => 16, init => std_ulogic_vector( to_unsigned( bcfg_epn_0to15, 16 ) ), + reset_inverts_scan => true, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + dclk => lcb_dclk, + lclk => lcb_lclk, + scan_in => bsiv(bcfg_offset to bcfg_offset+15), + scan_out => bsov(bcfg_offset to bcfg_offset+15), + q => bcfg_q(0 to 15), + q_b => bcfg_q_b(0 to 15) ); +bcfg_epn_16to31_latch: tri_slat_scan + generic map (width => 16, init => std_ulogic_vector( to_unsigned( bcfg_epn_16to31, 16 ) ), + reset_inverts_scan => true, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + dclk => lcb_dclk, + lclk => lcb_lclk, + scan_in => bsiv(bcfg_offset+16 to bcfg_offset+31), + scan_out => bsov(bcfg_offset+16 to bcfg_offset+31), + q => bcfg_q(16 to 31), + q_b => bcfg_q_b(16 to 31) ); +bcfg_epn_32to47_latch: tri_slat_scan + generic map (width => 16, init => std_ulogic_vector( to_unsigned( bcfg_epn_32to47, 16 ) ), + reset_inverts_scan => true, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + dclk => lcb_dclk, + lclk => lcb_lclk, + scan_in => bsiv(bcfg_offset+32 to bcfg_offset+47), + scan_out => bsov(bcfg_offset+32 to bcfg_offset+47), + q => bcfg_q(32 to 47), + q_b => bcfg_q_b(32 to 47) ); +bcfg_epn_48to51_latch: tri_slat_scan + generic map (width => 4, init => std_ulogic_vector( to_unsigned( bcfg_epn_48to51, 4 ) ), + reset_inverts_scan => true, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + dclk => lcb_dclk, + lclk => lcb_lclk, + scan_in => bsiv(bcfg_offset+48 to bcfg_offset+51), + scan_out => bsov(bcfg_offset+48 to bcfg_offset+51), + q => bcfg_q(48 to 51), + q_b => bcfg_q_b(48 to 51) ); +bcfg_rpn_22to31_latch: tri_slat_scan + generic map (width => 10, init => std_ulogic_vector( to_unsigned( bcfg_rpn_22to31, 10 ) ), + reset_inverts_scan => true, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + dclk => lcb_dclk, + lclk => lcb_lclk, + scan_in => bsiv(bcfg_offset+52 to bcfg_offset+61), + scan_out => bsov(bcfg_offset+52 to bcfg_offset+61), + q => bcfg_q(52 to 61), + q_b => bcfg_q_b(52 to 61) ); +bcfg_rpn_32to47_latch: tri_slat_scan + generic map (width => 16, init => std_ulogic_vector( to_unsigned( bcfg_rpn_32to47, 16 ) ), + reset_inverts_scan => true, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + dclk => lcb_dclk, + lclk => lcb_lclk, + scan_in => bsiv(bcfg_offset+62 to bcfg_offset+77), + scan_out => bsov(bcfg_offset+62 to bcfg_offset+77), + q => bcfg_q(62 to 77), + q_b => bcfg_q_b(62 to 77) ); +bcfg_rpn_48to51_latch: tri_slat_scan + generic map (width => 4, init => std_ulogic_vector( to_unsigned( bcfg_rpn_48to51, 4 ) ), + reset_inverts_scan => true, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + dclk => lcb_dclk, + lclk => lcb_lclk, + scan_in => bsiv(bcfg_offset+78 to bcfg_offset+81), + scan_out => bsov(bcfg_offset+78 to bcfg_offset+81), + q => bcfg_q(78 to 81), + q_b => bcfg_q_b(78 to 81) ); +bcfg_attr_latch: tri_slat_scan + generic map (width => 5, init => std_ulogic_vector( to_unsigned( bcfg_attr, 5 ) ), + reset_inverts_scan => true, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + dclk => lcb_dclk, + lclk => lcb_lclk, + scan_in => bsiv(bcfg_offset+82 to bcfg_offset+86), + scan_out => bsov(bcfg_offset+82 to bcfg_offset+86), + q => bcfg_q(82 to 86), + q_b => bcfg_q_b(82 to 86) ); +bcfg_rpn2_32to47_latch: tri_slat_scan + generic map (width => 16, init => std_ulogic_vector( to_unsigned( bcfg_rpn2_32to47, 16 ) ), + reset_inverts_scan => true, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + dclk => lcb_dclk, + lclk => lcb_lclk, + scan_in => bsiv(bcfg_offset+87 to bcfg_offset+102), + scan_out => bsov(bcfg_offset+87 to bcfg_offset+102), + q => bcfg_q(87 to 102), + q_b => bcfg_q_b(87 to 102) ); +bcfg_rpn2_48to51_latch: tri_slat_scan + generic map (width => 4, init => std_ulogic_vector( to_unsigned( bcfg_rpn2_48to51, 4 ) ), + reset_inverts_scan => true, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + dclk => lcb_dclk, + lclk => lcb_lclk, + scan_in => bsiv(bcfg_offset+103 to bcfg_offset+106), + scan_out => bsov(bcfg_offset+103 to bcfg_offset+106), + q => bcfg_q(103 to 106), + q_b => bcfg_q_b(103 to 106) ); +bcfg_spare_latch: tri_slat_scan + generic map (width => 16, init => std_ulogic_vector( to_unsigned( 0, 16 ) ), + reset_inverts_scan => true, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + dclk => lcb_dclk, + lclk => lcb_lclk, + scan_in => bsiv(bcfg_offset+107 to bcfg_offset+122), + scan_out => bsov(bcfg_offset+107 to bcfg_offset+122), + q => bcfg_q(107 to 122), + q_b => bcfg_q_b(107 to 122) ); +end generate mpg_bcfg_gen; +fpga_bcfg_gen: if expand_type = 1 generate +bcfg_epn_0to15_latch: tri_rlmreg_p + generic map (width => 16, init => bcfg_epn_0to15, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(0 to 15), + scout => bsov(0 to 15), + din => bcfg_q(0 to 15), + dout => bcfg_q(0 to 15) ); +bcfg_epn_16to31_latch: tri_rlmreg_p + generic map (width => 16, init => bcfg_epn_16to31, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(16 to 31), + scout => bsov(16 to 31), + din => bcfg_q(16 to 31), + dout => bcfg_q(16 to 31) ); +bcfg_epn_32to47_latch: tri_rlmreg_p + generic map (width => 16, init => bcfg_epn_32to47, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(32 to 47), + scout => bsov(32 to 47), + din => bcfg_q(32 to 47), + dout => bcfg_q(32 to 47) ); +bcfg_epn_48to51_latch: tri_rlmreg_p + generic map (width => 4, init => bcfg_epn_48to51, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(48 to 51), + scout => bsov(48 to 51), + din => bcfg_q(48 to 51), + dout => bcfg_q(48 to 51) ); +bcfg_rpn_22to31_latch: tri_rlmreg_p + generic map (width => 10, init => bcfg_rpn_22to31, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(52 to 61), + scout => bsov(52 to 61), + din => bcfg_q(52 to 61), + dout => bcfg_q(52 to 61) ); +bcfg_rpn_32to47_latch: tri_rlmreg_p + generic map (width => 16, init => bcfg_rpn_32to47, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(62 to 77), + scout => bsov(62 to 77), + din => bcfg_q(62 to 77), + dout => bcfg_q(62 to 77) ); +bcfg_rpn_48to51_latch: tri_rlmreg_p + generic map (width => 4, init => bcfg_rpn_48to51, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(78 to 81), + scout => bsov(78 to 81), + din => bcfg_q(78 to 81), + dout => bcfg_q(78 to 81) ); +bcfg_attr_latch: tri_rlmreg_p + generic map (width => 5, init => bcfg_attr, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(82 to 86), + scout => bsov(82 to 86), + din => bcfg_q(82 to 86), + dout => bcfg_q(82 to 86) ); +bcfg_rpn2_32to47_latch: tri_rlmreg_p + generic map (width => 16, init => bcfg_rpn2_32to47, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(87 to 102), + scout => bsov(87 to 102), + din => bcfg_q(87 to 102), + dout => bcfg_q(87 to 102) ); +bcfg_rpn2_48to51_latch: tri_rlmreg_p + generic map (width => 4, init => bcfg_rpn2_48to51, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(103 to 106), + scout => bsov(103 to 106), + din => bcfg_q(103 to 106), + dout => bcfg_q(103 to 106) ); +bcfg_spare_latch: tri_rlmreg_p + generic map (width => 16, init => 0, needs_sreset => 1, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + thold_b => pc_cfg_slp_sl_thold_0_b, + sg => pc_sg_0, + forcee => pc_cfg_slp_sl_force, + delay_lclkr => lcb_delay_lclkr_dc(0), + mpw1_b => lcb_mpw1_dc_b(0), + mpw2_b => lcb_mpw2_dc_b, + d_mode => lcb_d_mode_dc, + scin => bsiv(107 to 122), + scout => bsov(107 to 122), + din => bcfg_q(107 to 122), + dout => bcfg_q(107 to 122) ); +end generate fpga_bcfg_gen; +-------------------------------------------------- +-- thold/sg latches +-------------------------------------------------- +perv_2to1_reg: tri_plat + generic map (width => 4, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_xu_ccflush_dc, + din(0) => pc_func_sl_thold_2, + din(1) => pc_func_slp_sl_thold_2, + din(2) => pc_cfg_slp_sl_thold_2, + din(3) => pc_sg_2, + q(0) => pc_func_sl_thold_1, + q(1) => pc_func_slp_sl_thold_1, + q(2) => pc_cfg_slp_sl_thold_1, + q(3) => pc_sg_1); +perv_1to0_reg: tri_plat + generic map (width => 4, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_xu_ccflush_dc, + din(0) => pc_func_sl_thold_1, + din(1) => pc_func_slp_sl_thold_1, + din(2) => pc_cfg_slp_sl_thold_1, + din(3) => pc_sg_1, + q(0) => pc_func_sl_thold_0, + q(1) => pc_func_slp_sl_thold_0, + q(2) => pc_cfg_slp_sl_thold_0, + q(3) => pc_sg_0); +perv_lcbor_func_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b, + thold => pc_func_sl_thold_0, + sg => pc_sg_0, + act_dis => lcb_act_dis_dc, + forcee => pc_func_sl_force, + thold_b => pc_func_sl_thold_0_b); +perv_lcbor_func_slp_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b, + thold => pc_func_slp_sl_thold_0, + sg => pc_sg_0, + act_dis => lcb_act_dis_dc, + forcee => pc_func_slp_sl_force, + thold_b => pc_func_slp_sl_thold_0_b); +mpg_bcfg_lcb_gen: if expand_type /= 1 generate +-------------------------------------------------- +-- local clock buffer for boot config +-------------------------------------------------- +bcfg_lcb: tri_lcbs + generic map (expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + delay_lclkr => lcb_delay_lclkr_dc(0), + nclk => nclk, + forcee => pc_cfg_slp_sl_force, + thold_b => pc_cfg_slp_sl_thold_0_b, + dclk => lcb_dclk, + lclk => lcb_lclk ); +-- these terms in the absence of another lcbor component +-- that drives the thold_b and force into the bcfg_lcb for slat's +pc_cfg_slp_sl_thold_0_b <= NOT pc_cfg_slp_sl_thold_0; +pc_cfg_slp_sl_force <= pc_sg_0; +end generate mpg_bcfg_lcb_gen; +fpga_bcfg_lcb_gen: if expand_type = 1 generate +perv_lcbor_cfg_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => lcb_clkoff_dc_b, + thold => pc_cfg_slp_sl_thold_0, + sg => pc_sg_0, + act_dis => lcb_act_dis_dc, + forcee => pc_cfg_slp_sl_force, + thold_b => pc_cfg_slp_sl_thold_0_b); +end generate fpga_bcfg_lcb_gen; +----------------------------------------------------------------------- +-- Scan +----------------------------------------------------------------------- +siv_0(0 TO scan_right_0) <= sov_0(1 to scan_right_0) & ac_func_scan_in(0); +func_si_cam_int <= sov_0(0); +ac_func_scan_out(0) <= func_so_cam_int; +siv_1(0 TO scan_right_1) <= sov_1(1 to scan_right_1) & ac_func_scan_in(1); +ac_func_scan_out(1) <= sov_1(0); +bsiv(0 TO boot_scan_right) <= bsov(1 to boot_scan_right) & ac_ccfg_scan_in; +ac_ccfg_scan_out <= bsov(0); +END XUQ_LSU_DERAT; diff --git a/rel/src/vhdl/work/xuq_lsu_dir.vhdl b/rel/src/vhdl/work/xuq_lsu_dir.vhdl new file mode 100644 index 0000000..a6fcf87 --- /dev/null +++ b/rel/src/vhdl/work/xuq_lsu_dir.vhdl @@ -0,0 +1,2228 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XU LSU L1 Data Directory Wrapper + +library ibm, ieee, work, tri, support; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use tri.tri_latches_pkg.all; +use support.power_logic_pkg.all; + +-- ########################################################################################## +-- VHDL Contents +-- 1) L1 D$ Directory Array +-- 2) Valid Register Array +-- 3) LRU Register Array +-- 4) Data Cache Control +-- 5) Flush Generation +-- 6) 8 way tag compare +-- 7) Parity Check +-- 8) Reload Update +-- ########################################################################################## +entity xuq_lsu_dir is +generic(expand_type : integer := 2; + l_endian_m : integer := 1; + regmode : integer := 6; + lmq_entries : integer := 8; + dc_size : natural := 14; -- 2^14 = 16384 Bytes L1 D$ + cl_size : natural := 6; -- 2^6 = 64 Bytes CacheLines + wayDataSize : natural := 35; -- TagSize + Parity Bits + real_data_add : integer := 42); +port( + + xu_lsu_rf0_act :in std_ulogic; + xu_lsu_rf1_cmd_act :in std_ulogic; + xu_lsu_rf1_axu_op_val :in std_ulogic; + xu_lsu_rf1_axu_ldst_falign :in std_ulogic; + xu_lsu_rf1_axu_ldst_fexcpt :in std_ulogic; -- AXU force alignment exception on misaligned access + xu_lsu_rf1_cache_acc :in std_ulogic; + xu_lsu_rf1_thrd_id :in std_ulogic_vector(0 to 3); + xu_lsu_rf1_optype1 :in std_ulogic; + xu_lsu_rf1_optype2 :in std_ulogic; + xu_lsu_rf1_optype4 :in std_ulogic; + xu_lsu_rf1_optype8 :in std_ulogic; + xu_lsu_rf1_optype16 :in std_ulogic; + xu_lsu_rf1_optype32 :in std_ulogic; + xu_lsu_rf1_target_gpr :in std_ulogic_vector(0 to 8); + xu_lsu_rf1_mtspr_trace :in std_ulogic; -- Operation is a mtspr trace instruction + xu_lsu_rf1_load_instr :in std_ulogic; + xu_lsu_rf1_store_instr :in std_ulogic; + xu_lsu_rf1_dcbf_instr :in std_ulogic; + xu_lsu_rf1_sync_instr :in std_ulogic; + xu_lsu_rf1_l_fld :in std_ulogic_vector(0 to 1); + xu_lsu_rf1_dcbi_instr :in std_ulogic; + xu_lsu_rf1_dcbz_instr :in std_ulogic; + xu_lsu_rf1_dcbt_instr :in std_ulogic; + xu_lsu_rf1_dcbtst_instr :in std_ulogic; + xu_lsu_rf1_th_fld :in std_ulogic_vector(0 to 4); + xu_lsu_rf1_dcbtls_instr :in std_ulogic; + xu_lsu_rf1_dcbtstls_instr :in std_ulogic; + xu_lsu_rf1_dcblc_instr :in std_ulogic; + xu_lsu_rf1_dcbst_instr :in std_ulogic; + xu_lsu_rf1_icbi_instr :in std_ulogic; + xu_lsu_rf1_icblc_instr :in std_ulogic; + xu_lsu_rf1_icbt_instr :in std_ulogic; + xu_lsu_rf1_icbtls_instr :in std_ulogic; + xu_lsu_rf1_icswx_instr :in std_ulogic; + xu_lsu_rf1_icswx_dot_instr :in std_ulogic; + xu_lsu_rf1_icswx_epid :in std_ulogic; + xu_lsu_rf1_tlbsync_instr :in std_ulogic; + xu_lsu_rf1_ldawx_instr :in std_ulogic; + xu_lsu_rf1_wclr_instr :in std_ulogic; + xu_lsu_rf1_wchk_instr :in std_ulogic; + xu_lsu_rf1_lock_instr :in std_ulogic; + xu_lsu_rf1_mutex_hint :in std_ulogic; -- Mutex Hint For larx instructions + xu_lsu_rf1_mbar_instr :in std_ulogic; + xu_lsu_rf1_is_msgsnd :in std_ulogic; + xu_lsu_rf1_dci_instr :in std_ulogic; -- DCI instruction is valid + xu_lsu_rf1_ici_instr :in std_ulogic; -- ICI instruction is valid + xu_lsu_rf1_algebraic :in std_ulogic; + xu_lsu_rf1_byte_rev :in std_ulogic; + xu_lsu_rf1_src_gpr :in std_ulogic; + xu_lsu_rf1_src_axu :in std_ulogic; + xu_lsu_rf1_src_dp :in std_ulogic; + xu_lsu_rf1_targ_gpr :in std_ulogic; + xu_lsu_rf1_targ_axu :in std_ulogic; + xu_lsu_rf1_targ_dp :in std_ulogic; + xu_lsu_ex4_val :in std_ulogic_vector(0 to 3); -- There is a valid Instruction in EX4 + xu_lsu_ex1_add_src0 :in std_ulogic_vector(64-(2**REGMODE) to 63); + xu_lsu_ex1_add_src1 :in std_ulogic_vector(64-(2**REGMODE) to 63); + + xu_lsu_rf1_src0_vld :in std_ulogic; + xu_lsu_rf1_src0_reg :in std_ulogic_vector(0 to 7); + xu_lsu_rf1_src1_vld :in std_ulogic; + xu_lsu_rf1_src1_reg :in std_ulogic_vector(0 to 7); + xu_lsu_rf1_targ_vld :in std_ulogic; + xu_lsu_rf1_targ_reg :in std_ulogic_vector(0 to 7); + + -- Error Inject + pc_xu_inj_dcachedir_parity :in std_ulogic; + pc_xu_inj_dcachedir_multihit :in std_ulogic; + + ex3_wimge_w_bit :in std_ulogic; -- WIMGE bits in EX3 + ex3_wimge_i_bit :in std_ulogic; -- WIMGE bits in EX3 + ex3_wimge_e_bit :in std_ulogic; -- WIMGE bits in EX3 + ex3_p_addr :in std_ulogic_vector(64-real_data_add to 51); + derat_xu_ex3_noop_touch :in std_ulogic_vector(0 to 3); + ex3_ld_queue_full :in std_ulogic; -- LSQ load queue full + ex3_stq_flush :in std_ulogic; -- LSQ store queue full + ex3_ig_flush :in std_ulogic; -- LSQ I=G=1 flush + + ex2_lm_dep_hit :in std_ulogic; + + -- Directory Way Tag Compare + ex3_way_cmp_a :in std_ulogic; + ex3_way_cmp_b :in std_ulogic; + ex3_way_cmp_c :in std_ulogic; + ex3_way_cmp_d :in std_ulogic; + ex3_way_cmp_e :in std_ulogic; + ex3_way_cmp_f :in std_ulogic; + ex3_way_cmp_g :in std_ulogic; + ex3_way_cmp_h :in std_ulogic; + + ex3_wayA_tag :in std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex3_wayB_tag :in std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex3_wayC_tag :in std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex3_wayD_tag :in std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex3_wayE_tag :in std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex3_wayF_tag :in std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex3_wayG_tag :in std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex3_wayH_tag :in std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + + xu_lsu_mtspr_trace_en :in std_ulogic_vector(0 to 3); + spr_xucr0_clkg_ctl_b1 :in std_ulogic; + xu_lsu_spr_xucr0_aflsta :in std_ulogic; + xu_lsu_spr_xucr0_flsta :in std_ulogic; + xu_lsu_spr_xucr0_l2siw :in std_ulogic; -- L2 store interface width + xu_lsu_spr_xucr0_dcdis :in std_ulogic; + xu_lsu_spr_xucr0_wlk :in std_ulogic; + xu_lsu_spr_ccr2_dfrat :in std_ulogic; + xu_lsu_spr_xucr0_clfc :in std_ulogic; + xu_lsu_spr_xucr0_flh2l2 :in std_ulogic; + xu_lsu_spr_xucr0_cls :in std_ulogic; -- Cacheline Size = 1 => 128Byte size, 0 => 64Byte size + xu_lsu_spr_msr_cm :in std_ulogic_vector(0 to 3); -- 64bit mode enable + + -- MSR[GS,PR] bits, indicates which state we are running in + xu_lsu_msr_gs :in std_ulogic_vector(0 to 3); -- Guest State + xu_lsu_msr_pr :in std_ulogic_vector(0 to 3); -- Problem State + + an_ac_flh2l2_gate :in std_ulogic; -- Gate L1 Hit forwarding SPR config bit + + ldq_rel1_early_v :in std_ulogic; + ldq_rel1_val :in std_ulogic; + ldq_rel_mid_val :in std_ulogic; -- Reload data is valid for middle 32B beat + ldq_rel_retry_val :in std_ulogic; -- Reload is recirculated, dont update D$ array + ldq_rel3_early_v :in std_ulogic; + ldq_rel3_val :in std_ulogic; + ldq_rel_back_invalidated :in std_ulogic; + ldq_rel_data_val_early :in std_ulogic; -- Reload Interface ACT + rel_data_val :in std_ulogic; + ldq_rel_tag :in std_ulogic_vector(1 to 3); + ldq_rel_tag_early :in std_ulogic_vector(1 to 3); + ldq_rel_set_val :in std_ulogic; + ldq_rel_ecc_err :in std_ulogic; + ldq_rel_classid :in std_ulogic_vector(0 to 1); + ldq_rel_lock_en :in std_ulogic; + ldq_rel_l1dump_cslc :in std_ulogic; + ldq_rel3_l1dump_val :in std_ulogic; + ldq_rel_watch_en :in std_ulogic; + ldq_rel_addr :in std_ulogic_vector(64-real_data_add to 52); + ldq_rel_addr_early :in std_ulogic_vector(64-real_data_add to 63-cl_size); + ldq_recirc_rel_val :out std_ulogic; + + xu_lsu_dci :in std_ulogic; -- Flash invalidate the Directory + + is2_l2_inv_val :in std_ulogic; + + ex6_ld_par_err :in std_ulogic; + + xu_lsu_rf1_flush :in std_ulogic_vector(0 to 3); + xu_lsu_ex1_flush :in std_ulogic_vector(0 to 3); + xu_lsu_ex2_flush :in std_ulogic_vector(0 to 3); + xu_lsu_ex3_flush :in std_ulogic_vector(0 to 3); + xu_lsu_ex4_flush :in std_ulogic_vector(0 to 3); + xu_lsu_ex5_flush :in std_ulogic_vector(0 to 3); + + xu_lsu_slowspr_val :in std_ulogic; + xu_lsu_slowspr_rw :in std_ulogic; + xu_lsu_slowspr_etid :in std_ulogic_vector(0 to 1); + xu_lsu_slowspr_addr :in std_ulogic_vector(0 to 9); + xu_lsu_slowspr_data :in std_ulogic_vector(64-(2**REGMODE) to 63); + xu_lsu_slowspr_done :in std_ulogic; + slowspr_val_out :out std_ulogic; + slowspr_rw_out :out std_ulogic; + slowspr_etid_out :out std_ulogic_vector(0 to 1); + slowspr_addr_out :out std_ulogic_vector(0 to 9); + slowspr_data_out :out std_ulogic_vector(64-(2**REGMODE) to 63); + slowspr_done_out :out std_ulogic; + + ldq_rel_axu_val :in std_ulogic; + ldq_rel_thrd_id :in std_ulogic_vector(0 to 3); + ldq_rel_ta_gpr :in std_ulogic_vector(0 to 8); + ldq_rel_upd_gpr :in std_ulogic; + ldq_rel_ci :in std_ulogic; + + dir_arr_rd_addr_01 :out std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + dir_arr_rd_addr_23 :out std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + dir_arr_rd_addr_45 :out std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + dir_arr_rd_addr_67 :out std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + dir_arr_rd_data :in std_ulogic_vector(0 to 8*wayDataSize-1); + + dir_wr_enable :out std_ulogic_vector(0 to 3); + dir_wr_way :out std_ulogic_vector(0 to 7); + dir_arr_wr_addr :out std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + dir_arr_wr_data :out std_ulogic_vector(64-real_data_add to 64-real_data_add+wayDataSize-1); + + ex1_src0_vld :out std_ulogic; + ex1_src0_reg :out std_ulogic_vector(0 to 7); + ex1_src1_vld :out std_ulogic; + ex1_src1_reg :out std_ulogic_vector(0 to 7); + ex1_targ_vld :out std_ulogic; + ex1_targ_reg :out std_ulogic_vector(0 to 7); + ex1_check_watch :out std_ulogic_vector(0 to 3); -- Instructions that need to wait for ldawx to complete in loadmiss queue + + ex3_cache_acc :out std_ulogic; + ex1_optype1 :out std_ulogic; + ex1_optype2 :out std_ulogic; + ex1_optype4 :out std_ulogic; + ex1_optype8 :out std_ulogic; + ex1_optype16 :out std_ulogic; + ex1_optype32 :out std_ulogic; + ex1_saxu_instr :out std_ulogic; + ex1_sdp_instr :out std_ulogic; + ex1_stgpr_instr :out std_ulogic; + ex1_store_instr :out std_ulogic; + ex1_axu_op_val :out std_ulogic; + + lsu_xu_ex3_align :out std_ulogic_vector(0 to 3); + lsu_xu_ex3_dsi :out std_ulogic_vector(0 to 3); + lsu_xu_ex3_inval_align_2ucode :out std_ulogic; + + ex3_stg_flush :out std_ulogic; + ex4_stg_flush :out std_ulogic; + lsu_xu_ex3_n_flush_req :out std_ulogic; + lsu_xu_ex4_ldq_full_flush :out std_ulogic; + lsu_xu_ex3_dep_flush :out std_ulogic; + + xu_derat_ex1_epn_arr :out std_ulogic_vector(64-(2**regmode) to 51); + xu_derat_ex1_epn_nonarr :out std_ulogic_vector(64-(2**regmode) to 51); + snoop_addr :in std_ulogic_vector(64-(2**regmode) to 51); + snoop_addr_sel :in std_ulogic; + xu_derat_rf1_binv_val :out std_ulogic; + ex3_req_thrd_id :out std_ulogic_vector(0 to 3); + ex3_target_gpr :out std_ulogic_vector(0 to 8); + ex3_dcbt_instr :out std_ulogic; + ex3_dcbtst_instr :out std_ulogic; + ex3_th_fld_l2 :out std_ulogic; + ex3_dcbst_instr :out std_ulogic; + ex3_dcbf_instr :out std_ulogic; + ex3_sync_instr :out std_ulogic; + ex3_mtspr_trace :out std_ulogic; + ex3_byte_en :out std_ulogic_vector(0 to 31); + ex3_l_fld :out std_ulogic_vector(0 to 1); + ex3_dcbi_instr :out std_ulogic; + ex3_dcbz_instr :out std_ulogic; + ex3_icbi_instr :out std_ulogic; + ex3_icswx_instr :out std_ulogic; + ex3_icswx_dot :out std_ulogic; + ex3_icswx_epid :out std_ulogic; + ex3_mbar_instr :out std_ulogic; + ex3_msgsnd_instr :out std_ulogic; + ex3_dci_instr :out std_ulogic; + ex3_ici_instr :out std_ulogic; + ex3_load_instr :out std_ulogic; + ex3_store_instr :out std_ulogic; + ex3_axu_op_val :out std_ulogic; + ex3_algebraic :out std_ulogic; + ex3_dcbtls_instr :out std_ulogic; + ex3_dcbtstls_instr :out std_ulogic; + ex3_dcblc_instr :out std_ulogic; + ex3_icblc_instr :out std_ulogic; + ex3_icbt_instr :out std_ulogic; + ex3_icbtls_instr :out std_ulogic; + ex3_tlbsync_instr :out std_ulogic; + ex3_local_dcbf :out std_ulogic; + ex3_lock_en :out std_ulogic; + ex4_drop_rel :out std_ulogic; + ex3_load_l1hit :out std_ulogic; + ex3_rotate_sel :out std_ulogic_vector(0 to 4); + ex3_watch_en :out std_ulogic; + ex3_data_swap :out std_ulogic; + ex3_blkable_touch :out std_ulogic; + ex7_targ_match :out std_ulogic; -- EX6vsEX5 matched + ex8_targ_match :out std_ulogic; -- EX7vsEX6 or EX7vsEX5 matched + ex4_ld_entry :out std_ulogic_vector(0 to 67); + + ex3_cache_inh :out std_ulogic; + ex3_l_s_q_val :out std_ulogic; + ex3_drop_ld_req :out std_ulogic; + ex3_drop_touch :out std_ulogic; + ex3_stx_instr :out std_ulogic; + ex3_larx_instr :out std_ulogic; + ex3_mutex_hint :out std_ulogic; + ex3_opsize :out std_ulogic_vector(0 to 5); + ex4_dir_perr_det :out std_ulogic; + ex4_dir_multihit_det :out std_ulogic; + ex4_n_lsu_ddmh_flush :out std_ulogic_vector(0 to 3); -- Directory Multihit Flush + + ex2_p_addr_lwr :out std_ulogic_vector(52 to 57); + ex3_p_addr_lwr :out std_ulogic_vector(58 to 63); + dcpar_err_flush :out std_ulogic; + pe_recov_begin :out std_ulogic; + + lsu_xu_ex3_ddir_par_err :out std_ulogic; + ex3_cClass_collision :in std_ulogic; + + -- Inter-Thread Congruence Class Check + ex3_cClass_upd_way_a :out std_ulogic; + ex3_cClass_upd_way_b :out std_ulogic; + ex3_cClass_upd_way_c :out std_ulogic; + ex3_cClass_upd_way_d :out std_ulogic; + ex3_cClass_upd_way_e :out std_ulogic; + ex3_cClass_upd_way_f :out std_ulogic; + ex3_cClass_upd_way_g :out std_ulogic; + ex3_cClass_upd_way_h :out std_ulogic; + + -- Directory Read Data + ex2_wayA_tag :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex2_wayB_tag :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex2_wayC_tag :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex2_wayD_tag :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex2_wayE_tag :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex2_wayF_tag :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex2_wayG_tag :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex2_wayH_tag :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + + -- Update Data Array Valid + rel_upd_dcarr_val :out std_ulogic; + + lsu_xu_ex4_cr_upd :out std_ulogic; + lsu_xu_ex5_cr_rslt :out std_ulogic; + lsu_xu_ex5_wren :out std_ulogic; + lsu_xu_rel_wren :out std_ulogic; + lsu_xu_rel_ta_gpr :out std_ulogic_vector(0 to 7); + lsu_xu_perf_events :out std_ulogic_vector(0 to 37); + lsu_xu_need_hole :out std_ulogic; + xu_fu_ex5_reload_val :out std_ulogic; + xu_fu_ex5_load_val :out std_ulogic_vector(0 to 3); + xu_fu_ex5_load_tag :out std_ulogic_vector(0 to 8); + + -- ICBI Interface + xu_iu_ex6_icbi_val :out std_ulogic_vector(0 to 3); + xu_iu_ex6_icbi_addr :out std_ulogic_vector(64-real_data_add to 57); + + -- Data Array Controls + dcarr_up_way_addr :out std_ulogic_vector(0 to 2); + + -- DERAT SlowSPR Regs + xu_derat_epsc_wr :out std_ulogic_vector(0 to 3); + xu_derat_eplc_wr :out std_ulogic_vector(0 to 3); + xu_derat_eplc0_epr :out std_ulogic; + xu_derat_eplc0_eas :out std_ulogic; + xu_derat_eplc0_egs :out std_ulogic; + xu_derat_eplc0_elpid :out std_ulogic_vector(40 to 47); + xu_derat_eplc0_epid :out std_ulogic_vector(50 to 63); + xu_derat_eplc1_epr :out std_ulogic; + xu_derat_eplc1_eas :out std_ulogic; + xu_derat_eplc1_egs :out std_ulogic; + xu_derat_eplc1_elpid :out std_ulogic_vector(40 to 47); + xu_derat_eplc1_epid :out std_ulogic_vector(50 to 63); + xu_derat_eplc2_epr :out std_ulogic; + xu_derat_eplc2_eas :out std_ulogic; + xu_derat_eplc2_egs :out std_ulogic; + xu_derat_eplc2_elpid :out std_ulogic_vector(40 to 47); + xu_derat_eplc2_epid :out std_ulogic_vector(50 to 63); + xu_derat_eplc3_epr :out std_ulogic; + xu_derat_eplc3_eas :out std_ulogic; + xu_derat_eplc3_egs :out std_ulogic; + xu_derat_eplc3_elpid :out std_ulogic_vector(40 to 47); + xu_derat_eplc3_epid :out std_ulogic_vector(50 to 63); + xu_derat_epsc0_epr :out std_ulogic; + xu_derat_epsc0_eas :out std_ulogic; + xu_derat_epsc0_egs :out std_ulogic; + xu_derat_epsc0_elpid :out std_ulogic_vector(40 to 47); + xu_derat_epsc0_epid :out std_ulogic_vector(50 to 63); + xu_derat_epsc1_epr :out std_ulogic; + xu_derat_epsc1_eas :out std_ulogic; + xu_derat_epsc1_egs :out std_ulogic; + xu_derat_epsc1_elpid :out std_ulogic_vector(40 to 47); + xu_derat_epsc1_epid :out std_ulogic_vector(50 to 63); + xu_derat_epsc2_epr :out std_ulogic; + xu_derat_epsc2_eas :out std_ulogic; + xu_derat_epsc2_egs :out std_ulogic; + xu_derat_epsc2_elpid :out std_ulogic_vector(40 to 47); + xu_derat_epsc2_epid :out std_ulogic_vector(50 to 63); + xu_derat_epsc3_epr :out std_ulogic; + xu_derat_epsc3_eas :out std_ulogic; + xu_derat_epsc3_egs :out std_ulogic; + xu_derat_epsc3_elpid :out std_ulogic_vector(40 to 47); + xu_derat_epsc3_epid :out std_ulogic_vector(50 to 63); + + -- ACT signals + ex1_stg_act :out std_ulogic; + ex2_stg_act :out std_ulogic; + ex3_stg_act :out std_ulogic; + ex4_stg_act :out std_ulogic; + binv1_stg_act :out std_ulogic; + binv2_stg_act :out std_ulogic; + + -- SPR status + lsu_xu_spr_xucr0_cslc_xuop :out std_ulogic; -- Invalidate type instruction invalidated lock + lsu_xu_spr_xucr0_cslc_binv :out std_ulogic; -- Back-Invalidate invalidated lock + lsu_xu_spr_xucr0_clo :out std_ulogic; -- Cache Lock instruction caused an overlock + lsu_xu_spr_xucr0_cul :out std_ulogic; -- Cache Lock unable to lock + spr_xucr0_cls :out std_ulogic; -- Cacheline Size + + -- Directory Read interface + dir_arr_rd_is2_val :out std_ulogic; + dir_arr_rd_congr_cl :out std_ulogic_vector(0 to 4); + + -- Debug Data Compare + ex4_load_op_hit :out std_ulogic; + ex4_store_hit :out std_ulogic; + ex4_axu_op_val :out std_ulogic; + spr_dvc1_act :out std_ulogic; + spr_dvc2_act :out std_ulogic; + spr_dvc1_dbg :out std_ulogic_vector(64-(2**regmode) to 63); + spr_dvc2_dbg :out std_ulogic_vector(64-(2**regmode) to 63); + + -- Debug Data + pc_xu_trace_bus_enable :in std_ulogic; + dc_fgen_dbg_data :out std_ulogic_vector(0 to 1); + dc_cntrl_dbg_data :out std_ulogic_vector(0 to 66); + dc_val_dbg_data :out std_ulogic_vector(0 to 293); + dc_lru_dbg_data :out std_ulogic_vector(0 to 81); + dc_dir_dbg_data :out std_ulogic_vector(0 to 35); + dir_arr_dbg_data :out std_ulogic_vector(0 to 60); + + vdd :inout power_logic; + gnd :inout power_logic; + nclk :in clk_logic; + sg_0 :in std_ulogic; + func_sl_thold_0_b :in std_ulogic; + func_sl_force :in std_ulogic; + func_slp_sl_thold_0_b :in std_ulogic; + func_slp_sl_force :in std_ulogic; + func_nsl_thold_0_b :in std_ulogic; + func_nsl_force :in std_ulogic; + func_slp_nsl_thold_0_b :in std_ulogic; + func_slp_nsl_force :in std_ulogic; + d_mode_dc :in std_ulogic; + delay_lclkr_dc :in std_ulogic; + mpw1_dc_b :in std_ulogic; + mpw2_dc_b :in std_ulogic; + scan_in :in std_ulogic_vector(0 to 3); + scan_out :out std_ulogic_vector(0 to 3) +); +-- synopsys translate_off +-- synopsys translate_on +end xuq_lsu_dir; +---- +architecture xuq_lsu_dir of xuq_lsu_dir is +---------------------------- +-- components +---------------------------- + +---------------------------- +-- constants +---------------------------- + +constant uprCClassBit :natural := 64-(dc_size-3); +constant lwrCClassBit :natural := 63-cl_size; +constant uprTagBit :natural := 64-real_data_add; +constant lwrTagBit :natural := 63-(dc_size-3); +constant tagSize :natural := lwrTagBit-uprTagBit+1; +constant parExtCalc :natural := 8 - (tagSize mod 8); +constant parBits :natural := (tagSize+parExtCalc) / 8; + +constant lwr_p_addr_offset :natural := 0; +constant ldq_rel1_val_stg_offset :natural := lwr_p_addr_offset + 12; +constant ldq_rel_mid_stg_offset :natural := ldq_rel1_val_stg_offset + 1; +constant ldq_rel3_val_stg_offset :natural := ldq_rel_mid_stg_offset + 1; +constant spr_xucr0_dcdis_offset :natural := ldq_rel3_val_stg_offset + 1; +constant ex4_dir_perr_det_offset :natural := spr_xucr0_dcdis_offset + 1; +constant recirc_rel_val_offset :natural := ex4_dir_perr_det_offset + 1; +constant trace_bus_enable_offset :natural := recirc_rel_val_offset + 1; +constant scan_right :natural := trace_bus_enable_offset + 1 - 1; + +---------------------------- +-- signals +---------------------------- +signal ex1_p_addr :std_ulogic_vector(64-(dc_size-3) to 63-cl_size); +signal lwr_p_addr_d :std_ulogic_vector(52 to 63); +signal lwr_p_addr_q :std_ulogic_vector(52 to 63); +signal rel1_val :std_ulogic; +signal rel_mid_val :std_ulogic; +signal rel3_val :std_ulogic; +signal ldq_rel_stg24_val_d :std_ulogic; +signal ldq_rel_stg24_val_q :std_ulogic; +signal rel_st_tag :std_ulogic_vector(1 to 3); +signal rel_st_tag_early :std_ulogic_vector(1 to 3); +signal rel24_addr_d :std_ulogic_vector(64-real_data_add to 52); +signal rel24_addr_q :std_ulogic_vector(64-real_data_add to 52); +signal rel_way_val_a :std_ulogic; +signal rel_way_val_b :std_ulogic; +signal rel_way_val_c :std_ulogic; +signal rel_way_val_d :std_ulogic; +signal rel_way_val_e :std_ulogic; +signal rel_way_val_f :std_ulogic; +signal rel_way_val_g :std_ulogic; +signal rel_way_val_h :std_ulogic; +signal rel_way_lock_a :std_ulogic; +signal rel_way_lock_b :std_ulogic; +signal rel_way_lock_c :std_ulogic; +signal rel_way_lock_d :std_ulogic; +signal rel_way_lock_e :std_ulogic; +signal rel_way_lock_f :std_ulogic; +signal rel_way_lock_g :std_ulogic; +signal rel_way_lock_h :std_ulogic; +signal ex2_is_inval_op :std_ulogic; +signal ex2_lock_set :std_ulogic; +signal ex2_lock_clr :std_ulogic; +signal rel_wayA_wen :std_ulogic; +signal rel_wayB_wen :std_ulogic; +signal rel_wayC_wen :std_ulogic; +signal rel_wayD_wen :std_ulogic; +signal rel_wayE_wen :std_ulogic; +signal rel_wayF_wen :std_ulogic; +signal rel_wayG_wen :std_ulogic; +signal rel_wayH_wen :std_ulogic; +signal ex3_l1hit :std_ulogic; +signal ex4_l1miss :std_ulogic; +signal ex4_way_a_hit :std_ulogic; +signal ex4_way_b_hit :std_ulogic; +signal ex4_way_c_hit :std_ulogic; +signal ex4_way_d_hit :std_ulogic; +signal ex4_way_e_hit :std_ulogic; +signal ex4_way_f_hit :std_ulogic; +signal ex4_way_g_hit :std_ulogic; +signal ex4_way_h_hit :std_ulogic; +signal ex4_way_a_dir :std_ulogic_vector(0 to 5); +signal ex4_way_b_dir :std_ulogic_vector(0 to 5); +signal ex4_way_c_dir :std_ulogic_vector(0 to 5); +signal ex4_way_d_dir :std_ulogic_vector(0 to 5); +signal ex4_way_e_dir :std_ulogic_vector(0 to 5); +signal ex4_way_f_dir :std_ulogic_vector(0 to 5); +signal ex4_way_g_dir :std_ulogic_vector(0 to 5); +signal ex4_way_h_dir :std_ulogic_vector(0 to 5); +signal rel_way_upd_a :std_ulogic; +signal rel_way_upd_b :std_ulogic; +signal rel_way_upd_c :std_ulogic; +signal rel_way_upd_d :std_ulogic; +signal rel_way_upd_e :std_ulogic; +signal rel_way_upd_f :std_ulogic; +signal rel_way_upd_g :std_ulogic; +signal rel_way_upd_h :std_ulogic; +signal rel_way_clr_a :std_ulogic; +signal rel_way_clr_b :std_ulogic; +signal rel_way_clr_c :std_ulogic; +signal rel_way_clr_d :std_ulogic; +signal rel_way_clr_e :std_ulogic; +signal rel_way_clr_f :std_ulogic; +signal rel_way_clr_g :std_ulogic; +signal rel_way_clr_h :std_ulogic; +signal rel4_set_val :std_ulogic; +signal stg_ex2_flush :std_ulogic; +signal stg_ex3_flush :std_ulogic; +signal stg_ex4_flush :std_ulogic; +signal stg_ex5_flush :std_ulogic; +signal ex2_no_lru_upd :std_ulogic; +signal ex3_tag_way_perr :std_ulogic_vector(0 to 7); +signal ex3_cache_en :std_ulogic; +signal rel_lock_en :std_ulogic; +signal rel_l1dump_cslc :std_ulogic; +signal rel3_l1dump_val :std_ulogic; +signal rel1_classid :std_ulogic_vector(0 to 1); +signal dcbtstls_instr_ex3 :std_ulogic; +signal dcbtls_instr_ex3 :std_ulogic; +signal ex1_frc_align2 :std_ulogic; +signal ex1_frc_align4 :std_ulogic; +signal ex1_frc_align8 :std_ulogic; +signal ex1_frc_align16 :std_ulogic; +signal ex1_frc_align32 :std_ulogic; +signal spr_xucr2_rmt :std_ulogic_vector(0 to 31); +signal spr_xucr0_wlck :std_ulogic; +signal ex5_load_op_hit :std_ulogic; +signal ex2_ddir_acc_instr :std_ulogic; +signal ex3_dir_perr_det :std_ulogic; +signal ex4_ldq_full_flush :std_ulogic; +signal rel_up_way_addr_b :std_ulogic_vector(0 to 2); -- Reload upper Address Inverted +signal rel_dcarr_addr_en :std_ulogic; -- Reload Select +signal rel_dcarr_val_upd :std_ulogic; +signal spr_xucr0_dcdis_d :std_ulogic; +signal spr_xucr0_dcdis_q :std_ulogic; +signal ex2_p_addr_lwr_int :std_ulogic_vector(52 to 63); +signal ex1_thrd_id :std_ulogic_vector(0 to 3); +signal ex2_ldawx_instr :std_ulogic; +signal ex2_wclr_instr :std_ulogic; +signal ex2_wchk_val :std_ulogic; +signal ex2_l_fld :std_ulogic_vector(0 to 1); +signal store_instr_ex2 :std_ulogic; +signal rel_watch_en :std_ulogic; +signal rel_thrd_id :std_ulogic_vector(0 to 3); +signal ex1_l2_inv_val :std_ulogic; +signal ex1_l2_inv_val_b :std_ulogic; +signal ex2_frc_align_d :std_ulogic_vector(59 to 63); +signal ex2_frc_align_q :std_ulogic_vector(59 to 63); +signal ex1_lsu_64bit_agen :std_ulogic; +signal ex1_agen_addr :std_ulogic_vector(64-(2**regmode) to 51); +signal ex1_dir01_addr :std_ulogic_vector(64-(dc_size-3) to 63-cl_size); +signal ex1_dir23_addr :std_ulogic_vector(64-(dc_size-3) to 63-cl_size); +signal ex1_dir45_addr :std_ulogic_vector(64-(dc_size-3) to 63-cl_size); +signal ex1_dir67_addr :std_ulogic_vector(64-(dc_size-3) to 63-cl_size); +signal ex1_eff_addr :std_ulogic_vector(64-(2**regmode) to 63); +signal ex4_dir_perr_det_d :std_ulogic; +signal ex4_dir_perr_det_q :std_ulogic; +signal recirc_rel_val :std_ulogic; +signal recirc_rel_val_d :std_ulogic; +signal recirc_rel_val_q :std_ulogic; +signal ex1_dir_acc_val :std_ulogic; +signal ex1_dir_acc_val_b :std_ulogic; +signal rf1_l2_inv_val :std_ulogic; +signal ex1_agen_binv_val :std_ulogic; +signal dir_wr_enable_int :std_ulogic_vector(0 to 3); +signal dir_arr_wr_addr_int :std_ulogic_vector(64-(dc_size-3) to 63-cl_size); +signal dir_wr_way_int :std_ulogic_vector(0 to 7); +signal dir_arr_wr_data_int :std_ulogic_vector(64-real_data_add to 64-real_data_add+wayDataSize-1); +signal ex1_stg_act_int :std_ulogic; +signal ex2_stg_act_int :std_ulogic; +signal ex3_stg_act_int :std_ulogic; +signal ex4_stg_act_int :std_ulogic; +signal ex5_stg_act_int :std_ulogic; +signal binv1_stg_act_int :std_ulogic; +signal binv2_stg_act_int :std_ulogic; +signal binv3_stg_act_int :std_ulogic; +signal binv4_stg_act_int :std_ulogic; +signal binv5_stg_act_int :std_ulogic; +signal rel1_stg_act_int :std_ulogic; +signal rel2_stg_act_int :std_ulogic; +signal rel3_stg_act_int :std_ulogic; +signal binv1_ex1_stg_act :std_ulogic; +signal ex2_lockwatchSet_rel_coll :std_ulogic; +signal ex3_wclr_all_flush :std_ulogic; +signal spr_xucr0_cls_int :std_ulogic; +signal agen_xucr0_cls :std_ulogic; +signal agen_xucr0_cls_b :std_ulogic; +signal tag_scan_out :std_ulogic; +signal lru_scan_out :std_ulogic; +signal dir_scan_out :std_ulogic; +signal ex3_way_tag_par_a :std_ulogic_vector(0 to parBits-1); +signal ex3_way_tag_par_b :std_ulogic_vector(0 to parBits-1); +signal ex3_way_tag_par_c :std_ulogic_vector(0 to parBits-1); +signal ex3_way_tag_par_d :std_ulogic_vector(0 to parBits-1); +signal ex3_way_tag_par_e :std_ulogic_vector(0 to parBits-1); +signal ex3_way_tag_par_f :std_ulogic_vector(0 to parBits-1); +signal ex3_way_tag_par_g :std_ulogic_vector(0 to parBits-1); +signal ex3_way_tag_par_h :std_ulogic_vector(0 to parBits-1); +signal ex4_dir_lru :std_ulogic_vector(0 to 6); +signal ex3_load_val :std_ulogic; +signal ex3_l2_request :std_ulogic; +signal ex3_ldq_potential_flush :std_ulogic; +signal ex4_snd_ld_l2 :std_ulogic; +signal ldq_rel1_val_stg_d :std_ulogic; +signal ldq_rel1_val_stg_q :std_ulogic; +signal ldq_rel_mid_stg_d :std_ulogic; +signal ldq_rel_mid_stg_q :std_ulogic; +signal ldq_rel3_val_stg_d :std_ulogic; +signal ldq_rel3_val_stg_q :std_ulogic; +signal ldq_rel_data_stg_d :std_ulogic; +signal ldq_rel_data_stg_q :std_ulogic; +signal ldq_rel_set_stg_d :std_ulogic; +signal ldq_rel_set_stg_q :std_ulogic; +signal trace_bus_enable_q :std_ulogic; +signal dir_arr_dbg_data_d :std_ulogic_vector(0 to 60); +signal dir_arr_dbg_data_q :std_ulogic_vector(0 to 60); +signal ex3_cache_acc_int :std_ulogic; + +signal tiup :std_ulogic; +signal siv :std_ulogic_vector(0 to scan_right); +signal sov :std_ulogic_vector(0 to scan_right); +begin + + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Inputs +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +tiup <= '1'; + +-- Force Alignment +ex2_frc_align_d(59) <= not ex1_frc_align32; +ex2_frc_align_d(60) <= not (ex1_frc_align32 or ex1_frc_align16); +ex2_frc_align_d(61) <= not (ex1_frc_align32 or ex1_frc_align16 or ex1_frc_align8); +ex2_frc_align_d(62) <= not (ex1_frc_align32 or ex1_frc_align16 or ex1_frc_align8 or ex1_frc_align4); +ex2_frc_align_d(63) <= not (ex1_frc_align32 or ex1_frc_align16 or ex1_frc_align8 or ex1_frc_align4 or ex1_frc_align2); + +spr_xucr0_dcdis_d <= xu_lsu_spr_xucr0_dcdis; +ldq_rel_stg24_val_d <= ldq_rel1_val or ldq_rel3_val or ldq_rel_ci or rel_data_val or ldq_rel_mid_val; + +ldq_rel1_val_stg_d <= ldq_rel1_val; +ldq_rel_mid_stg_d <= ldq_rel_mid_val; +ldq_rel3_val_stg_d <= ldq_rel3_val; +ldq_rel_data_stg_d <= rel_data_val; +ldq_rel_set_stg_d <= ldq_rel_set_val; +rel1_val <= ldq_rel1_val and not spr_xucr0_dcdis_q; +rel_st_tag <= ldq_rel_tag; +rel_st_tag_early <= ldq_rel_tag_early; +rel24_addr_d <= ldq_rel_addr; +rel4_set_val <= ldq_rel_set_val; +rel_lock_en <= ldq_rel_lock_en; +rel_l1dump_cslc <= ldq_rel_l1dump_cslc and not spr_xucr0_dcdis_q; +rel3_l1dump_val <= ldq_rel3_l1dump_val and not spr_xucr0_dcdis_q; +rel_watch_en <= ldq_rel_watch_en; +rel_thrd_id <= ldq_rel_thrd_id; +rel1_classid <= ldq_rel_classid; +rel3_val <= ldq_rel3_val and not spr_xucr0_dcdis_q; +rel_mid_val <= ldq_rel_mid_val and not spr_xucr0_dcdis_q; +ex2_p_addr_lwr_int <= lwr_p_addr_q(52 to 58) & (lwr_p_addr_q(59 to 63) and ex2_frc_align_q); +binv1_ex1_stg_act <= binv1_stg_act_int or ex1_stg_act_int; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Agen Adder +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +agen_xucr0_cls_b <= not agen_xucr0_cls; +ex1_dir_acc_val_b <= not ex1_dir_acc_val; +ex1_l2_inv_val_b <= not ex1_l2_inv_val; + +Mode32b : if regmode = 5 generate begin + ex1_eff_addr <= std_ulogic_vector(unsigned(xu_lsu_ex1_add_src0) + unsigned(xu_lsu_ex1_add_src1)); + ex1_agen_addr <= ex1_eff_addr(64-(2**regmode) to 51); + lwr_p_addr_d <= ex1_eff_addr(52 to 63); + ex1_p_addr <= ex1_eff_addr(64-(dc_size-3) to 63-cl_size); + ex1_dir01_addr(64-(dc_size-3) to 63-cl_size-1) <= ex1_eff_addr(64-(dc_size-3) to 63-cl_size-1); + ex1_dir01_addr(63-cl_size) <= ex1_eff_addr(63-cl_size) or agen_xucr0_cls; + ex1_dir23_addr(64-(dc_size-3) to 63-cl_size-1) <= ex1_eff_addr(64-(dc_size-3) to 63-cl_size-1); + ex1_dir23_addr(63-cl_size) <= ex1_eff_addr(63-cl_size) or agen_xucr0_cls; + ex1_dir45_addr(64-(dc_size-3) to 63-cl_size-1) <= ex1_eff_addr(64-(dc_size-3) to 63-cl_size-1); + ex1_dir45_addr(63-cl_size) <= ex1_eff_addr(63-cl_size) or agen_xucr0_cls; + ex1_dir67_addr(64-(dc_size-3) to 63-cl_size-1) <= ex1_eff_addr(64-(dc_size-3) to 63-cl_size-1); + ex1_dir67_addr(63-cl_size) <= ex1_eff_addr(63-cl_size) or agen_xucr0_cls; +end generate Mode32b; + +Mode64b : if regmode = 6 generate begin + lsuagen : entity work.xuq_agen(xuq_agen) + port map( + x => xu_lsu_ex1_add_src0, + y => xu_lsu_ex1_add_src1, + mode64 => ex1_lsu_64bit_agen, + dir_ig_57_b => agen_xucr0_cls_b, + snoop_addr => snoop_addr(0 to 51), + snoop_sel => snoop_addr_sel, + binv_val => ex1_agen_binv_val, + sum_non_erat => ex1_eff_addr, + sum => ex1_agen_addr(0 to 51), + sum_arr_dir01 => ex1_dir01_addr, + sum_arr_dir23 => ex1_dir23_addr, + sum_arr_dir45 => ex1_dir45_addr, + sum_arr_dir67 => ex1_dir67_addr, + z => dir_arr_wr_addr_int, + way => dir_wr_way_int, + inv1_val_b => ex1_l2_inv_val_b, + ex1_cache_acc_b => ex1_dir_acc_val_b, + rel3_val => rel3_val, + ary_write_act_01 => dir_wr_enable(0), + ary_write_act_23 => dir_wr_enable(1), + ary_write_act_45 => dir_wr_enable(2), + ary_write_act_67 => dir_wr_enable(3), + ary_write_act => dir_wr_enable_int, + match_oth => recirc_rel_val, + vdd => vdd, + gnd => gnd + ); + + lwr_p_addr_d <= ex1_eff_addr(52 to 63); + ex1_p_addr <= ex1_eff_addr(64-(dc_size-3) to 63-cl_size); +end generate Mode64b; + +recirc_rel_val_d <= recirc_rel_val and rel3_val; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- L1 Data Control Logic +-- 1) Contains Staging Latches +-- 2) Flush Generation +-- 3) Exception Handling +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +lsudc : entity work.xuq_lsu_dc(xuq_lsu_dc) +generic map(expand_type => expand_type, + l_endian_m => l_endian_m, + regmode => regmode, + dc_size => dc_size, + parBits => parBits, + real_data_add => real_data_add) +port map( + + xu_lsu_rf0_act => xu_lsu_rf0_act, + xu_lsu_rf1_cmd_act => xu_lsu_rf1_cmd_act, + xu_lsu_rf1_axu_op_val => xu_lsu_rf1_axu_op_val, + xu_lsu_rf1_axu_ldst_falign => xu_lsu_rf1_axu_ldst_falign, + xu_lsu_rf1_axu_ldst_fexcpt => xu_lsu_rf1_axu_ldst_fexcpt, + xu_lsu_rf1_cache_acc => xu_lsu_rf1_cache_acc, + xu_lsu_rf1_thrd_id => xu_lsu_rf1_thrd_id, + xu_lsu_rf1_optype1 => xu_lsu_rf1_optype1, + xu_lsu_rf1_optype2 => xu_lsu_rf1_optype2, + xu_lsu_rf1_optype4 => xu_lsu_rf1_optype4, + xu_lsu_rf1_optype8 => xu_lsu_rf1_optype8, + xu_lsu_rf1_optype16 => xu_lsu_rf1_optype16, + xu_lsu_rf1_optype32 => xu_lsu_rf1_optype32, + xu_lsu_rf1_target_gpr => xu_lsu_rf1_target_gpr, + xu_lsu_rf1_mtspr_trace => xu_lsu_rf1_mtspr_trace, + xu_lsu_rf1_load_instr => xu_lsu_rf1_load_instr, + xu_lsu_rf1_store_instr => xu_lsu_rf1_store_instr, + xu_lsu_rf1_dcbf_instr => xu_lsu_rf1_dcbf_instr, + xu_lsu_rf1_sync_instr => xu_lsu_rf1_sync_instr, + xu_lsu_rf1_l_fld => xu_lsu_rf1_l_fld, + xu_lsu_rf1_dcbi_instr => xu_lsu_rf1_dcbi_instr, + xu_lsu_rf1_dcbz_instr => xu_lsu_rf1_dcbz_instr, + xu_lsu_rf1_dcbt_instr => xu_lsu_rf1_dcbt_instr, + xu_lsu_rf1_dcbtst_instr => xu_lsu_rf1_dcbtst_instr, + xu_lsu_rf1_th_fld => xu_lsu_rf1_th_fld, + xu_lsu_rf1_dcbtls_instr => xu_lsu_rf1_dcbtls_instr, + xu_lsu_rf1_dcbtstls_instr => xu_lsu_rf1_dcbtstls_instr, + xu_lsu_rf1_dcblc_instr => xu_lsu_rf1_dcblc_instr, + xu_lsu_rf1_dcbst_instr => xu_lsu_rf1_dcbst_instr, + xu_lsu_rf1_icbi_instr => xu_lsu_rf1_icbi_instr, + xu_lsu_rf1_icblc_instr => xu_lsu_rf1_icblc_instr, + xu_lsu_rf1_icbt_instr => xu_lsu_rf1_icbt_instr, + xu_lsu_rf1_icbtls_instr => xu_lsu_rf1_icbtls_instr, + xu_lsu_rf1_icswx_instr => xu_lsu_rf1_icswx_instr, + xu_lsu_rf1_icswx_dot_instr => xu_lsu_rf1_icswx_dot_instr, + xu_lsu_rf1_icswx_epid => xu_lsu_rf1_icswx_epid, + xu_lsu_rf1_tlbsync_instr => xu_lsu_rf1_tlbsync_instr, + xu_lsu_rf1_ldawx_instr => xu_lsu_rf1_ldawx_instr, + xu_lsu_rf1_wclr_instr => xu_lsu_rf1_wclr_instr, + xu_lsu_rf1_wchk_instr => xu_lsu_rf1_wchk_instr, + xu_lsu_rf1_lock_instr => xu_lsu_rf1_lock_instr, + xu_lsu_rf1_mutex_hint => xu_lsu_rf1_mutex_hint, + xu_lsu_rf1_mbar_instr => xu_lsu_rf1_mbar_instr, + xu_lsu_rf1_is_msgsnd => xu_lsu_rf1_is_msgsnd, + xu_lsu_rf1_dci_instr => xu_lsu_rf1_dci_instr, + xu_lsu_rf1_ici_instr => xu_lsu_rf1_ici_instr, + xu_lsu_rf1_algebraic => xu_lsu_rf1_algebraic, + xu_lsu_rf1_byte_rev => xu_lsu_rf1_byte_rev, + xu_lsu_rf1_src_gpr => xu_lsu_rf1_src_gpr, + xu_lsu_rf1_src_axu => xu_lsu_rf1_src_axu, + xu_lsu_rf1_src_dp => xu_lsu_rf1_src_dp, + xu_lsu_rf1_targ_gpr => xu_lsu_rf1_targ_gpr, + xu_lsu_rf1_targ_axu => xu_lsu_rf1_targ_axu, + xu_lsu_rf1_targ_dp => xu_lsu_rf1_targ_dp, + xu_lsu_ex4_val => xu_lsu_ex4_val, + + xu_lsu_rf1_src0_vld => xu_lsu_rf1_src0_vld, + xu_lsu_rf1_src0_reg => xu_lsu_rf1_src0_reg, + xu_lsu_rf1_src1_vld => xu_lsu_rf1_src1_vld, + xu_lsu_rf1_src1_reg => xu_lsu_rf1_src1_reg, + xu_lsu_rf1_targ_vld => xu_lsu_rf1_targ_vld, + xu_lsu_rf1_targ_reg => xu_lsu_rf1_targ_reg, + + ex2_p_addr_lwr => ex2_p_addr_lwr_int, + ex3_wimge_w_bit => ex3_wimge_w_bit, + ex3_wimge_i_bit => ex3_wimge_i_bit, + ex3_wimge_e_bit => ex3_wimge_e_bit, + ex2_lm_dep_hit => ex2_lm_dep_hit, + + ex3_p_addr => ex3_p_addr, + ex3_ld_queue_full => ex3_ld_queue_full, + ex3_stq_flush => ex3_stq_flush, + ex3_ig_flush => ex3_ig_flush, + ex3_hit => ex3_l1hit, + ex4_miss => ex4_l1miss, + ex4_snd_ld_l2 => ex4_snd_ld_l2, + derat_xu_ex3_noop_touch => derat_xu_ex3_noop_touch, + ex3_cClass_collision => ex3_cClass_collision, + ex2_lockwatchSet_rel_coll => ex2_lockwatchSet_rel_coll, + ex3_wclr_all_flush => ex3_wclr_all_flush, + + rel_dcarr_val_upd => rel_dcarr_val_upd, + + xu_lsu_mtspr_trace_en => xu_lsu_mtspr_trace_en, + spr_xucr0_clkg_ctl_b1 => spr_xucr0_clkg_ctl_b1, + xu_lsu_spr_xucr0_aflsta => xu_lsu_spr_xucr0_aflsta, + xu_lsu_spr_xucr0_flsta => xu_lsu_spr_xucr0_flsta, + xu_lsu_spr_xucr0_l2siw => xu_lsu_spr_xucr0_l2siw, + xu_lsu_spr_xucr0_dcdis => xu_lsu_spr_xucr0_dcdis, + xu_lsu_spr_xucr0_wlk => xu_lsu_spr_xucr0_wlk, + xu_lsu_spr_ccr2_dfrat => xu_lsu_spr_ccr2_dfrat, + xu_lsu_spr_xucr0_flh2l2 => xu_lsu_spr_xucr0_flh2l2, + xu_lsu_spr_xucr0_cls => xu_lsu_spr_xucr0_cls, + xu_lsu_spr_msr_cm => xu_lsu_spr_msr_cm, + + xu_lsu_msr_gs => xu_lsu_msr_gs, + xu_lsu_msr_pr => xu_lsu_msr_pr, + + an_ac_flh2l2_gate => an_ac_flh2l2_gate, + + xu_lsu_rf1_flush => xu_lsu_rf1_flush, + xu_lsu_ex1_flush => xu_lsu_ex1_flush, + xu_lsu_ex2_flush => xu_lsu_ex2_flush, + xu_lsu_ex3_flush => xu_lsu_ex3_flush, + xu_lsu_ex4_flush => xu_lsu_ex4_flush, + xu_lsu_ex5_flush => xu_lsu_ex5_flush, + + xu_lsu_slowspr_val => xu_lsu_slowspr_val, + xu_lsu_slowspr_rw => xu_lsu_slowspr_rw, + xu_lsu_slowspr_etid => xu_lsu_slowspr_etid, + xu_lsu_slowspr_addr => xu_lsu_slowspr_addr, + xu_lsu_slowspr_data => xu_lsu_slowspr_data, + xu_lsu_slowspr_done => xu_lsu_slowspr_done, + slowspr_val_out => slowspr_val_out, + slowspr_rw_out => slowspr_rw_out, + slowspr_etid_out => slowspr_etid_out, + slowspr_addr_out => slowspr_addr_out, + slowspr_data_out => slowspr_data_out, + slowspr_done_out => slowspr_done_out, + + ldq_rel_data_val_early => ldq_rel_data_val_early, + ldq_rel_stg24_val => ldq_rel_stg24_val_q, + ldq_rel_axu_val => ldq_rel_axu_val, + ldq_rel_thrd_id => ldq_rel_thrd_id, + ldq_rel_ta_gpr => ldq_rel_ta_gpr, + ldq_rel_upd_gpr => ldq_rel_upd_gpr, + ldq_rel_ci => ldq_rel_ci, + is2_l2_inv_val => is2_l2_inv_val, + + ex3_wayA_tag => ex3_wayA_tag, + ex3_wayB_tag => ex3_wayB_tag, + ex3_wayC_tag => ex3_wayC_tag, + ex3_wayD_tag => ex3_wayD_tag, + ex3_wayE_tag => ex3_wayE_tag, + ex3_wayF_tag => ex3_wayF_tag, + ex3_wayG_tag => ex3_wayG_tag, + ex3_wayH_tag => ex3_wayH_tag, + ex3_way_tag_par_a => ex3_way_tag_par_a, + ex3_way_tag_par_b => ex3_way_tag_par_b, + ex3_way_tag_par_c => ex3_way_tag_par_c, + ex3_way_tag_par_d => ex3_way_tag_par_d, + ex3_way_tag_par_e => ex3_way_tag_par_e, + ex3_way_tag_par_f => ex3_way_tag_par_f, + ex3_way_tag_par_g => ex3_way_tag_par_g, + ex3_way_tag_par_h => ex3_way_tag_par_h, + ex4_way_a_dir => ex4_way_a_dir, + ex4_way_b_dir => ex4_way_b_dir, + ex4_way_c_dir => ex4_way_c_dir, + ex4_way_d_dir => ex4_way_d_dir, + ex4_way_e_dir => ex4_way_e_dir, + ex4_way_f_dir => ex4_way_f_dir, + ex4_way_g_dir => ex4_way_g_dir, + ex4_way_h_dir => ex4_way_h_dir, + ex4_dir_lru => ex4_dir_lru, + + ex1_src0_vld => ex1_src0_vld, + ex1_src0_reg => ex1_src0_reg, + ex1_src1_vld => ex1_src1_vld, + ex1_src1_reg => ex1_src1_reg, + ex1_targ_vld => ex1_targ_vld, + ex1_targ_reg => ex1_targ_reg, + ex1_check_watch => ex1_check_watch, + + ex1_dir_acc_val => ex1_dir_acc_val, + ex3_cache_acc => ex3_cache_acc_int, + ex1_lsu_64bit_agen => ex1_lsu_64bit_agen, + ex1_frc_align2 => ex1_frc_align2, + ex1_frc_align4 => ex1_frc_align4, + ex1_frc_align8 => ex1_frc_align8, + ex1_frc_align16 => ex1_frc_align16, + ex1_frc_align32 => ex1_frc_align32, + ex1_optype1 => ex1_optype1, + ex1_optype2 => ex1_optype2, + ex1_optype4 => ex1_optype4, + ex1_optype8 => ex1_optype8, + ex1_optype16 => ex1_optype16, + ex1_optype32 => ex1_optype32, + ex1_saxu_instr => ex1_saxu_instr, + ex1_sdp_instr => ex1_sdp_instr, + ex1_stgpr_instr => ex1_stgpr_instr, + ex1_store_instr => ex1_store_instr, + ex1_axu_op_val => ex1_axu_op_val, + ex2_no_lru_upd => ex2_no_lru_upd, + ex2_is_inval_op => ex2_is_inval_op, + ex2_lock_set => ex2_lock_set, + ex2_lock_clr => ex2_lock_clr, + ex2_ddir_acc_instr => ex2_ddir_acc_instr, + + ex3_p_addr_lwr => ex3_p_addr_lwr, + ex3_req_thrd_id => ex3_req_thrd_id, + ex3_target_gpr => ex3_target_gpr, + ex3_dcbt_instr => ex3_dcbt_instr, + ex3_dcbtst_instr => ex3_dcbtst_instr, + ex3_th_fld_l2 => ex3_th_fld_l2, + ex3_dcbst_instr => ex3_dcbst_instr, + ex3_dcbf_instr => ex3_dcbf_instr, + ex3_sync_instr => ex3_sync_instr, + ex3_mtspr_trace => ex3_mtspr_trace, + ex3_byte_en => ex3_byte_en, + ex2_l_fld => ex2_l_fld, + ex3_l_fld => ex3_l_fld, + ex3_dcbi_instr => ex3_dcbi_instr, + ex3_dcbz_instr => ex3_dcbz_instr, + ex3_icbi_instr => ex3_icbi_instr, + ex3_icswx_instr => ex3_icswx_instr, + ex3_icswx_dot => ex3_icswx_dot, + ex3_icswx_epid => ex3_icswx_epid, + ex3_mbar_instr => ex3_mbar_instr, + ex3_msgsnd_instr => ex3_msgsnd_instr, + ex3_dci_instr => ex3_dci_instr, + ex3_ici_instr => ex3_ici_instr, + ex3_load_instr => ex3_load_instr, + ex2_store_instr => store_instr_ex2, + ex3_store_instr => ex3_store_instr, + ex3_axu_op_val => ex3_axu_op_val, + ex3_algebraic => ex3_algebraic, + ex3_dcbtls_instr => dcbtls_instr_ex3, + ex3_dcbtstls_instr => dcbtstls_instr_ex3, + ex3_dcblc_instr => ex3_dcblc_instr, + ex3_icblc_instr => ex3_icblc_instr, + ex3_icbt_instr => ex3_icbt_instr, + ex3_icbtls_instr => ex3_icbtls_instr, + ex3_tlbsync_instr => ex3_tlbsync_instr, + ex3_local_dcbf => ex3_local_dcbf, + ex4_drop_rel => ex4_drop_rel, + ex3_load_l1hit => ex3_load_l1hit, + ex3_rotate_sel => ex3_rotate_sel, + ex1_thrd_id => ex1_thrd_id, + ex2_ldawx_instr => ex2_ldawx_instr, + ex2_wclr_instr => ex2_wclr_instr, + ex2_wchk_val => ex2_wchk_val, + ex3_watch_en => ex3_watch_en, + ex3_data_swap => ex3_data_swap, + ex3_load_val => ex3_load_val, + ex3_blkable_touch => ex3_blkable_touch, + ex3_l2_request => ex3_l2_request, + ex3_ldq_potential_flush => ex3_ldq_potential_flush, + ex7_targ_match => ex7_targ_match, + ex8_targ_match => ex8_targ_match, + ex4_ld_entry => ex4_ld_entry, + + ex3_lock_en => ex3_lock_en, + ex3_cache_en => ex3_cache_en, + ex3_cache_inh => ex3_cache_inh, + ex3_l_s_q_val => ex3_l_s_q_val, + ex3_drop_ld_req => ex3_drop_ld_req, + ex3_drop_touch => ex3_drop_touch, + ex3_stx_instr => ex3_stx_instr, + ex3_larx_instr => ex3_larx_instr, + ex3_mutex_hint => ex3_mutex_hint, + ex3_opsize => ex3_opsize, + ex4_store_hit => ex4_store_hit, + + spr_xucr2_rmt => spr_xucr2_rmt, + spr_xucr0_wlck => spr_xucr0_wlck, + ex4_load_op_hit => ex4_load_op_hit, + ex5_load_op_hit => ex5_load_op_hit, + ex4_axu_op_val => ex4_axu_op_val, + spr_dvc1_act => spr_dvc1_act, + spr_dvc2_act => spr_dvc2_act, + spr_dvc1_dbg => spr_dvc1_dbg, + spr_dvc2_dbg => spr_dvc2_dbg, + + lsu_xu_spr_xucr0_cul => lsu_xu_spr_xucr0_cul, + spr_xucr0_cls => spr_xucr0_cls_int, + agen_xucr0_cls => agen_xucr0_cls, + + -- Directory Read interface + dir_arr_rd_is2_val => dir_arr_rd_is2_val, + dir_arr_rd_congr_cl => dir_arr_rd_congr_cl, + + lsu_xu_ex3_align => lsu_xu_ex3_align, + lsu_xu_ex3_dsi => lsu_xu_ex3_dsi, + lsu_xu_ex3_inval_align_2ucode => lsu_xu_ex3_inval_align_2ucode, + + ex2_stg_flush => stg_ex2_flush, + ex3_stg_flush => stg_ex3_flush, + ex4_stg_flush => stg_ex4_flush, + ex5_stg_flush => stg_ex5_flush, + lsu_xu_ex3_n_flush_req => lsu_xu_ex3_n_flush_req, + lsu_xu_ex3_dep_flush => lsu_xu_ex3_dep_flush, + + -- Back-invalidate + rf1_l2_inv_val => rf1_l2_inv_val, + ex1_agen_binv_val => ex1_agen_binv_val, + ex1_l2_inv_val => ex1_l2_inv_val, + + -- Update Data Array Valid + rel_upd_dcarr_val => rel_upd_dcarr_val, + + lsu_xu_ex4_cr_upd => lsu_xu_ex4_cr_upd, + lsu_xu_ex5_wren => lsu_xu_ex5_wren, + lsu_xu_rel_wren => lsu_xu_rel_wren, + lsu_xu_rel_ta_gpr => lsu_xu_rel_ta_gpr, + lsu_xu_perf_events => lsu_xu_perf_events(0 to 20), + lsu_xu_need_hole => lsu_xu_need_hole, + + xu_fu_ex5_reload_val => xu_fu_ex5_reload_val, + xu_fu_ex5_load_val => xu_fu_ex5_load_val, + xu_fu_ex5_load_tag => xu_fu_ex5_load_tag, + + -- ICBI Interface + xu_iu_ex6_icbi_val => xu_iu_ex6_icbi_val, + xu_iu_ex6_icbi_addr => xu_iu_ex6_icbi_addr, + + -- DERAT SlowSPR Regs + xu_derat_epsc_wr => xu_derat_epsc_wr, + xu_derat_eplc_wr => xu_derat_eplc_wr, + xu_derat_eplc0_epr => xu_derat_eplc0_epr, + xu_derat_eplc0_eas => xu_derat_eplc0_eas, + xu_derat_eplc0_egs => xu_derat_eplc0_egs, + xu_derat_eplc0_elpid => xu_derat_eplc0_elpid, + xu_derat_eplc0_epid => xu_derat_eplc0_epid, + xu_derat_eplc1_epr => xu_derat_eplc1_epr, + xu_derat_eplc1_eas => xu_derat_eplc1_eas, + xu_derat_eplc1_egs => xu_derat_eplc1_egs, + xu_derat_eplc1_elpid => xu_derat_eplc1_elpid, + xu_derat_eplc1_epid => xu_derat_eplc1_epid, + xu_derat_eplc2_epr => xu_derat_eplc2_epr, + xu_derat_eplc2_eas => xu_derat_eplc2_eas, + xu_derat_eplc2_egs => xu_derat_eplc2_egs, + xu_derat_eplc2_elpid => xu_derat_eplc2_elpid, + xu_derat_eplc2_epid => xu_derat_eplc2_epid, + xu_derat_eplc3_epr => xu_derat_eplc3_epr, + xu_derat_eplc3_eas => xu_derat_eplc3_eas, + xu_derat_eplc3_egs => xu_derat_eplc3_egs, + xu_derat_eplc3_elpid => xu_derat_eplc3_elpid, + xu_derat_eplc3_epid => xu_derat_eplc3_epid, + xu_derat_epsc0_epr => xu_derat_epsc0_epr, + xu_derat_epsc0_eas => xu_derat_epsc0_eas, + xu_derat_epsc0_egs => xu_derat_epsc0_egs, + xu_derat_epsc0_elpid => xu_derat_epsc0_elpid, + xu_derat_epsc0_epid => xu_derat_epsc0_epid, + xu_derat_epsc1_epr => xu_derat_epsc1_epr, + xu_derat_epsc1_eas => xu_derat_epsc1_eas, + xu_derat_epsc1_egs => xu_derat_epsc1_egs, + xu_derat_epsc1_elpid => xu_derat_epsc1_elpid, + xu_derat_epsc1_epid => xu_derat_epsc1_epid, + xu_derat_epsc2_epr => xu_derat_epsc2_epr, + xu_derat_epsc2_eas => xu_derat_epsc2_eas, + xu_derat_epsc2_egs => xu_derat_epsc2_egs, + xu_derat_epsc2_elpid => xu_derat_epsc2_elpid, + xu_derat_epsc2_epid => xu_derat_epsc2_epid, + xu_derat_epsc3_epr => xu_derat_epsc3_epr, + xu_derat_epsc3_eas => xu_derat_epsc3_eas, + xu_derat_epsc3_egs => xu_derat_epsc3_egs, + xu_derat_epsc3_elpid => xu_derat_epsc3_elpid, + xu_derat_epsc3_epid => xu_derat_epsc3_epid, + + -- Debug Data + dc_fgen_dbg_data => dc_fgen_dbg_data, + dc_cntrl_dbg_data => dc_cntrl_dbg_data, + + -- ACT signals + ex1_stg_act => ex1_stg_act_int, + ex2_stg_act => ex2_stg_act_int, + ex3_stg_act => ex3_stg_act_int, + ex4_stg_act => ex4_stg_act_int, + ex5_stg_act => ex5_stg_act_int, + binv1_stg_act => binv1_stg_act_int, + binv2_stg_act => binv2_stg_act_int, + binv3_stg_act => binv3_stg_act_int, + binv4_stg_act => binv4_stg_act_int, + binv5_stg_act => binv5_stg_act_int, + rel1_stg_act => rel1_stg_act_int, + rel2_stg_act => rel2_stg_act_int, + rel3_stg_act => rel3_stg_act_int, + + vdd => vdd, + gnd => gnd, + nclk => nclk, + sg_0 => sg_0, + func_sl_thold_0_b => func_sl_thold_0_b, + func_sl_force => func_sl_force, + func_slp_sl_thold_0_b => func_slp_sl_thold_0_b, + func_slp_sl_force => func_slp_sl_force, + func_nsl_thold_0_b => func_nsl_thold_0_b, + func_nsl_force => func_nsl_force, + func_slp_nsl_thold_0_b => func_slp_nsl_thold_0_b, + func_slp_nsl_force => func_slp_nsl_force, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc, + mpw1_dc_b => mpw1_dc_b, + mpw2_dc_b => mpw2_dc_b, + scan_in => scan_in(0), + scan_out => scan_out(0) +); +dir16k : if (2**dc_size) = 16384 generate begin +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Directory Valids Array +-- 1) Contains an Array of Valids +-- 2) Updates Valid bits on Reloads +-- 3) Invalidates Valid bits for Flush type commands and Back Invalidates +-- 4) Outputs Valids for Congruence Class +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +l1dcdv: entity work.xuq_lsu_dir_val16(xuq_lsu_dir_val16) +GENERIC MAP(expand_type => expand_type, + dc_size => dc_size, + cl_size => cl_size) +PORT MAP ( + + -- Stage Act Signals + ex1_stg_act => ex1_stg_act_int, + ex2_stg_act => ex2_stg_act_int, + ex3_stg_act => ex3_stg_act_int, + ex4_stg_act => ex4_stg_act_int, + ex5_stg_act => ex5_stg_act_int, + binv1_stg_act => binv1_stg_act_int, + binv2_stg_act => binv2_stg_act_int, + binv3_stg_act => binv3_stg_act_int, + binv4_stg_act => binv4_stg_act_int, + binv5_stg_act => binv5_stg_act_int, + rel1_stg_act => rel1_stg_act_int, + rel2_stg_act => rel2_stg_act_int, + + ldq_rel1_early_v => ldq_rel1_early_v, + rel1_val => rel1_val, + rel_addr_early => ldq_rel_addr_early(64-(dc_size-3) to 63-cl_size), + rel_lock_en => rel_lock_en, + rel_l1dump_cslc => rel_l1dump_cslc, + rel3_l1dump_val => rel3_l1dump_val, + rel_watch_en => rel_watch_en, + rel_thrd_id => rel_thrd_id, + rel_way_clr_a => rel_way_clr_a, + rel_way_clr_b => rel_way_clr_b, + rel_way_clr_c => rel_way_clr_c, + rel_way_clr_d => rel_way_clr_d, + rel_way_clr_e => rel_way_clr_e, + rel_way_clr_f => rel_way_clr_f, + rel_way_clr_g => rel_way_clr_g, + rel_way_clr_h => rel_way_clr_h, + + ldq_rel3_early_v => ldq_rel3_early_v, + rel3_val => rel3_val, + rel_back_inval => ldq_rel_back_invalidated, + rel4_set_val => rel4_set_val, + rel4_recirc_val => recirc_rel_val_q, + rel4_ecc_err => ldq_rel_ecc_err, + rel_way_wen_a => rel_wayA_wen, + rel_way_wen_b => rel_wayB_wen, + rel_way_wen_c => rel_wayC_wen, + rel_way_wen_d => rel_wayD_wen, + rel_way_wen_e => rel_wayE_wen, + rel_way_wen_f => rel_wayF_wen, + rel_way_wen_g => rel_wayG_wen, + rel_way_wen_h => rel_wayH_wen, + rel_up_way_addr_b => rel_up_way_addr_b, + rel_dcarr_addr_en => rel_dcarr_addr_en, + + xu_lsu_dci => xu_lsu_dci, + xu_lsu_spr_xucr0_clfc => xu_lsu_spr_xucr0_clfc, + spr_xucr0_dcdis => spr_xucr0_dcdis_q, + spr_xucr0_cls => spr_xucr0_cls_int, + + ex1_thrd_id => ex1_thrd_id, + ex1_p_addr => ex1_p_addr, + ex2_is_inval_op => ex2_is_inval_op, + ex2_lock_set => ex2_lock_set, + ex2_lock_clr => ex2_lock_clr, + ex3_cache_en => ex3_cache_en, + ex3_cache_acc => ex3_cache_acc_int, + ex3_tag_way_perr => ex3_tag_way_perr, + ex5_load_op_hit => ex5_load_op_hit, + ex6_ld_par_err => ex6_ld_par_err, + ex2_ldawx_instr => ex2_ldawx_instr, + ex2_wclr_instr => ex2_wclr_instr, + ex2_wchk_val => ex2_wchk_val, + ex2_l_fld => ex2_l_fld, + ex2_store_instr => store_instr_ex2, + ex3_load_val => ex3_load_val, + ex3_wimge_i_bit => ex3_wimge_i_bit, + ex3_l2_request => ex3_l2_request, + ex3_ldq_potential_flush => ex3_ldq_potential_flush, + + inv1_val => ex1_l2_inv_val, + + ex3_way_cmp_a => ex3_way_cmp_a, + ex3_way_cmp_b => ex3_way_cmp_b, + ex3_way_cmp_c => ex3_way_cmp_c, + ex3_way_cmp_d => ex3_way_cmp_d, + ex3_way_cmp_e => ex3_way_cmp_e, + ex3_way_cmp_f => ex3_way_cmp_f, + ex3_way_cmp_g => ex3_way_cmp_g, + ex3_way_cmp_h => ex3_way_cmp_h, + + ex2_stg_flush => stg_ex2_flush, + ex3_stg_flush => stg_ex3_flush, + ex4_stg_flush => stg_ex4_flush, + ex5_stg_flush => stg_ex5_flush, + + pc_xu_inj_dcachedir_multihit => pc_xu_inj_dcachedir_multihit, + + -- L1 Directory Contents + ex4_way_a_dir => ex4_way_a_dir, + ex4_way_b_dir => ex4_way_b_dir, + ex4_way_c_dir => ex4_way_c_dir, + ex4_way_d_dir => ex4_way_d_dir, + ex4_way_e_dir => ex4_way_e_dir, + ex4_way_f_dir => ex4_way_f_dir, + ex4_way_g_dir => ex4_way_g_dir, + ex4_way_h_dir => ex4_way_h_dir, + + ex4_way_a_hit => ex4_way_a_hit, + ex4_way_b_hit => ex4_way_b_hit, + ex4_way_c_hit => ex4_way_c_hit, + ex4_way_d_hit => ex4_way_d_hit, + ex4_way_e_hit => ex4_way_e_hit, + ex4_way_f_hit => ex4_way_f_hit, + ex4_way_g_hit => ex4_way_g_hit, + ex4_way_h_hit => ex4_way_h_hit, + + ex2_lockwatchSet_rel_coll => ex2_lockwatchSet_rel_coll, + ex3_wclr_all_flush => ex3_wclr_all_flush, + + -- Inter-Thread Congruence Class Check + ex3_cClass_upd_way_a => ex3_cClass_upd_way_a, + ex3_cClass_upd_way_b => ex3_cClass_upd_way_b, + ex3_cClass_upd_way_c => ex3_cClass_upd_way_c, + ex3_cClass_upd_way_d => ex3_cClass_upd_way_d, + ex3_cClass_upd_way_e => ex3_cClass_upd_way_e, + ex3_cClass_upd_way_f => ex3_cClass_upd_way_f, + ex3_cClass_upd_way_g => ex3_cClass_upd_way_g, + ex3_cClass_upd_way_h => ex3_cClass_upd_way_h, + + ex3_hit => ex3_l1hit, + ex3_dir_perr_det => ex3_dir_perr_det, + ex4_dir_multihit_det => ex4_dir_multihit_det, + ex4_n_lsu_ddmh_flush => ex4_n_lsu_ddmh_flush, + ex4_ldq_full_flush => ex4_ldq_full_flush, + ex4_miss => ex4_l1miss, + ex4_snd_ld_l2 => ex4_snd_ld_l2, + dcpar_err_flush => dcpar_err_flush, + pe_recov_begin => pe_recov_begin, + + lsu_xu_ex5_cr_rslt => lsu_xu_ex5_cr_rslt, + + rel_way_val_a => rel_way_val_a, + rel_way_val_b => rel_way_val_b, + rel_way_val_c => rel_way_val_c, + rel_way_val_d => rel_way_val_d, + rel_way_val_e => rel_way_val_e, + rel_way_val_f => rel_way_val_f, + rel_way_val_g => rel_way_val_g, + rel_way_val_h => rel_way_val_h, + + rel_way_lock_a => rel_way_lock_a, + rel_way_lock_b => rel_way_lock_b, + rel_way_lock_c => rel_way_lock_c, + rel_way_lock_d => rel_way_lock_d, + rel_way_lock_e => rel_way_lock_e, + rel_way_lock_f => rel_way_lock_f, + rel_way_lock_g => rel_way_lock_g, + rel_way_lock_h => rel_way_lock_h, + + dcarr_up_way_addr => dcarr_up_way_addr, + + lsu_xu_perf_events => lsu_xu_perf_events(21 to 37), + + lsu_xu_spr_xucr0_cslc_xuop => lsu_xu_spr_xucr0_cslc_xuop, + lsu_xu_spr_xucr0_cslc_binv => lsu_xu_spr_xucr0_cslc_binv, + + dc_val_dbg_data => dc_val_dbg_data, + + vdd => vdd, + gnd => gnd, + nclk => nclk, + sg_0 => sg_0, + func_sl_thold_0_b => func_sl_thold_0_b, + func_sl_force => func_sl_force, + func_slp_sl_thold_0_b => func_slp_sl_thold_0_b, + func_slp_sl_force => func_slp_sl_force, + func_nsl_thold_0_b => func_nsl_thold_0_b, + func_nsl_force => func_nsl_force, + func_slp_nsl_thold_0_b => func_slp_nsl_thold_0_b, + func_slp_nsl_force => func_slp_nsl_force, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc, + mpw1_dc_b => mpw1_dc_b, + mpw2_dc_b => mpw2_dc_b, + scan_in => scan_in(1 to 3), + scan_out(0 to 1) => scan_out(1 to 2), + scan_out(2) => dir_scan_out +); + +ex4_dir_perr_det_d <= ex3_dir_perr_det; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- LRU Register Array +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +l1dcdl : entity work.xuq_lsu_dir_lru16(xuq_lsu_dir_lru16) +GENERIC MAP(expand_type => expand_type, + dc_size => dc_size, + lmq_entries => lmq_entries, + cl_size => cl_size) +PORT MAP( + + -- Stage Act Signals + ex1_stg_act => ex1_stg_act_int, + ex2_stg_act => ex2_stg_act_int, + ex3_stg_act => ex3_stg_act_int, + ex4_stg_act => ex4_stg_act_int, + ex5_stg_act => ex5_stg_act_int, + rel1_stg_act => rel1_stg_act_int, + rel2_stg_act => rel2_stg_act_int, + rel3_stg_act => rel3_stg_act_int, + + rel1_val => rel1_val, + rel1_classid => rel1_classid, + rel_mid_val => rel_mid_val, + rel_retry_val => ldq_rel_retry_val, + rel3_val => rel3_val, + rel_st_tag => rel_st_tag, + rel_st_tag_early => rel_st_tag_early, + rel_addr_early => ldq_rel_addr_early(64-(dc_size-3) to 63-cl_size), + rel_lock_en => rel_lock_en, + rel4_recirc_val => recirc_rel_val_q, + rel4_ecc_err => ldq_rel_ecc_err, + + rel_way_val_a => rel_way_val_a, + rel_way_val_b => rel_way_val_b, + rel_way_val_c => rel_way_val_c, + rel_way_val_d => rel_way_val_d, + rel_way_val_e => rel_way_val_e, + rel_way_val_f => rel_way_val_f, + rel_way_val_g => rel_way_val_g, + rel_way_val_h => rel_way_val_h, + + rel_way_lock_a => rel_way_lock_a, + rel_way_lock_b => rel_way_lock_b, + rel_way_lock_c => rel_way_lock_c, + rel_way_lock_d => rel_way_lock_d, + rel_way_lock_e => rel_way_lock_e, + rel_way_lock_f => rel_way_lock_f, + rel_way_lock_g => rel_way_lock_g, + rel_way_lock_h => rel_way_lock_h, + + ex1_p_addr => ex1_p_addr, + ex2_no_lru_upd => ex2_no_lru_upd, + ex3_cache_en => ex3_cache_en, + + ex4_way_a_hit => ex4_way_a_hit, + ex4_way_b_hit => ex4_way_b_hit, + ex4_way_c_hit => ex4_way_c_hit, + ex4_way_d_hit => ex4_way_d_hit, + ex4_way_e_hit => ex4_way_e_hit, + ex4_way_f_hit => ex4_way_f_hit, + ex4_way_g_hit => ex4_way_g_hit, + ex4_way_h_hit => ex4_way_h_hit, + ex3_hit => ex3_l1hit, + + ex3_stg_flush => stg_ex3_flush, + ex4_stg_flush => stg_ex4_flush, + ex5_stg_flush => stg_ex5_flush, + + spr_xucr2_rmt => spr_xucr2_rmt, + spr_xucr0_wlck => spr_xucr0_wlck, + spr_xucr0_dcdis => spr_xucr0_dcdis_q, + spr_xucr0_cls => spr_xucr0_cls_int, + + rel_way_upd_a => rel_way_upd_a, + rel_way_upd_b => rel_way_upd_b, + rel_way_upd_c => rel_way_upd_c, + rel_way_upd_d => rel_way_upd_d, + rel_way_upd_e => rel_way_upd_e, + rel_way_upd_f => rel_way_upd_f, + rel_way_upd_g => rel_way_upd_g, + rel_way_upd_h => rel_way_upd_h, + + rel_way_wen_a => rel_wayA_wen, + rel_way_wen_b => rel_wayB_wen, + rel_way_wen_c => rel_wayC_wen, + rel_way_wen_d => rel_wayD_wen, + rel_way_wen_e => rel_wayE_wen, + rel_way_wen_f => rel_wayF_wen, + rel_way_wen_g => rel_wayG_wen, + rel_way_wen_h => rel_wayH_wen, + + rel_way_clr_a => rel_way_clr_a, + rel_way_clr_b => rel_way_clr_b, + rel_way_clr_c => rel_way_clr_c, + rel_way_clr_d => rel_way_clr_d, + rel_way_clr_e => rel_way_clr_e, + rel_way_clr_f => rel_way_clr_f, + rel_way_clr_g => rel_way_clr_g, + rel_way_clr_h => rel_way_clr_h, + rel_dcarr_val_upd => rel_dcarr_val_upd, + rel_up_way_addr_b => rel_up_way_addr_b, + rel_dcarr_addr_en => rel_dcarr_addr_en, + + lsu_xu_spr_xucr0_clo => lsu_xu_spr_xucr0_clo, + ex4_dir_lru => ex4_dir_lru, + dc_lru_dbg_data => dc_lru_dbg_data, + + vdd => vdd, + gnd => gnd, + nclk => nclk, + sg_0 => sg_0, + func_sl_thold_0_b => func_sl_thold_0_b, + func_sl_force => func_sl_force, + func_nsl_thold_0_b => func_nsl_thold_0_b, + func_nsl_force => func_nsl_force, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc, + mpw1_dc_b => mpw1_dc_b, + mpw2_dc_b => mpw2_dc_b, + scan_in => dir_scan_out, + scan_out => lru_scan_out + ); +end generate dir16k; + +dir32k : if (2**dc_size) = 32768 generate begin +-- Bugspray Include: xuq_lsu_dir32k +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Directory Valids Array +-- 1) Contains an Array of Valids +-- 2) Updates Valid bits on Reloads +-- 3) Invalidates Valid bits for Flush type commands and Back Invalidates +-- 4) Outputs Valids for Congruence Class +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +l1dcdv: entity work.xuq_lsu_dir_val32(xuq_lsu_dir_val32) +GENERIC MAP(expand_type => expand_type, + dc_size => dc_size, + cl_size => cl_size) +PORT MAP ( + + -- Stage Act Signals + ex1_stg_act => ex1_stg_act_int, + ex2_stg_act => ex2_stg_act_int, + ex3_stg_act => ex3_stg_act_int, + ex4_stg_act => ex4_stg_act_int, + ex5_stg_act => ex5_stg_act_int, + binv1_stg_act => binv1_stg_act_int, + binv2_stg_act => binv2_stg_act_int, + binv3_stg_act => binv3_stg_act_int, + binv4_stg_act => binv4_stg_act_int, + binv5_stg_act => binv5_stg_act_int, + rel1_stg_act => rel1_stg_act_int, + rel2_stg_act => rel2_stg_act_int, + + ldq_rel1_early_v => ldq_rel1_early_v, + rel1_val => rel1_val, + rel_addr_early => ldq_rel_addr_early(64-(dc_size-3) to 63-cl_size), + rel_lock_en => rel_lock_en, + rel_l1dump_cslc => rel_l1dump_cslc, + rel3_l1dump_val => rel3_l1dump_val, + rel_watch_en => rel_watch_en, + rel_thrd_id => rel_thrd_id, + rel_way_clr_a => rel_way_clr_a, + rel_way_clr_b => rel_way_clr_b, + rel_way_clr_c => rel_way_clr_c, + rel_way_clr_d => rel_way_clr_d, + rel_way_clr_e => rel_way_clr_e, + rel_way_clr_f => rel_way_clr_f, + rel_way_clr_g => rel_way_clr_g, + rel_way_clr_h => rel_way_clr_h, + + ldq_rel3_early_v => ldq_rel3_early_v, + rel3_val => rel3_val, + rel_back_inval => ldq_rel_back_invalidated, + rel4_set_val => rel4_set_val, + rel4_recirc_val => recirc_rel_val_q, + rel4_ecc_err => ldq_rel_ecc_err, + rel_way_wen_a => rel_wayA_wen, + rel_way_wen_b => rel_wayB_wen, + rel_way_wen_c => rel_wayC_wen, + rel_way_wen_d => rel_wayD_wen, + rel_way_wen_e => rel_wayE_wen, + rel_way_wen_f => rel_wayF_wen, + rel_way_wen_g => rel_wayG_wen, + rel_way_wen_h => rel_wayH_wen, + rel_up_way_addr_b => rel_up_way_addr_b, + rel_dcarr_addr_en => rel_dcarr_addr_en, + + xu_lsu_dci => xu_lsu_dci, + xu_lsu_spr_xucr0_clfc => xu_lsu_spr_xucr0_clfc, + spr_xucr0_dcdis => spr_xucr0_dcdis_q, + spr_xucr0_cls => spr_xucr0_cls_int, + + ex1_thrd_id => ex1_thrd_id, + ex1_p_addr => ex1_p_addr, + ex2_is_inval_op => ex2_is_inval_op, + ex2_lock_set => ex2_lock_set, + ex2_lock_clr => ex2_lock_clr, + ex3_cache_en => ex3_cache_en, + ex3_cache_acc => ex3_cache_acc_int, + ex3_tag_way_perr => ex3_tag_way_perr, + ex5_load_op_hit => ex5_load_op_hit, + ex6_ld_par_err => ex6_ld_par_err, + ex2_ldawx_instr => ex2_ldawx_instr, + ex2_wclr_instr => ex2_wclr_instr, + ex2_wchk_val => ex2_wchk_val, + ex2_l_fld => ex2_l_fld, + ex2_store_instr => store_instr_ex2, + ex3_load_val => ex3_load_val, + ex3_wimge_i_bit => ex3_wimge_i_bit, + ex3_l2_request => ex3_l2_request, + ex3_ldq_potential_flush => ex3_ldq_potential_flush, + + inv1_val => ex1_l2_inv_val, + + ex3_way_cmp_a => ex3_way_cmp_a, + ex3_way_cmp_b => ex3_way_cmp_b, + ex3_way_cmp_c => ex3_way_cmp_c, + ex3_way_cmp_d => ex3_way_cmp_d, + ex3_way_cmp_e => ex3_way_cmp_e, + ex3_way_cmp_f => ex3_way_cmp_f, + ex3_way_cmp_g => ex3_way_cmp_g, + ex3_way_cmp_h => ex3_way_cmp_h, + + ex2_stg_flush => stg_ex2_flush, + ex3_stg_flush => stg_ex3_flush, + ex4_stg_flush => stg_ex4_flush, + ex5_stg_flush => stg_ex5_flush, + + pc_xu_inj_dcachedir_multihit => pc_xu_inj_dcachedir_multihit, + + -- L1 Directory Contents + ex4_way_a_dir => ex4_way_a_dir, + ex4_way_b_dir => ex4_way_b_dir, + ex4_way_c_dir => ex4_way_c_dir, + ex4_way_d_dir => ex4_way_d_dir, + ex4_way_e_dir => ex4_way_e_dir, + ex4_way_f_dir => ex4_way_f_dir, + ex4_way_g_dir => ex4_way_g_dir, + ex4_way_h_dir => ex4_way_h_dir, + + ex4_way_a_hit => ex4_way_a_hit, + ex4_way_b_hit => ex4_way_b_hit, + ex4_way_c_hit => ex4_way_c_hit, + ex4_way_d_hit => ex4_way_d_hit, + ex4_way_e_hit => ex4_way_e_hit, + ex4_way_f_hit => ex4_way_f_hit, + ex4_way_g_hit => ex4_way_g_hit, + ex4_way_h_hit => ex4_way_h_hit, + + ex2_lockwatchSet_rel_coll => ex2_lockwatchSet_rel_coll, + ex3_wclr_all_flush => ex3_wclr_all_flush, + + -- Inter-Thread Congruence Class Check + ex3_cClass_upd_way_a => ex3_cClass_upd_way_a, + ex3_cClass_upd_way_b => ex3_cClass_upd_way_b, + ex3_cClass_upd_way_c => ex3_cClass_upd_way_c, + ex3_cClass_upd_way_d => ex3_cClass_upd_way_d, + ex3_cClass_upd_way_e => ex3_cClass_upd_way_e, + ex3_cClass_upd_way_f => ex3_cClass_upd_way_f, + ex3_cClass_upd_way_g => ex3_cClass_upd_way_g, + ex3_cClass_upd_way_h => ex3_cClass_upd_way_h, + + ex3_hit => ex3_l1hit, + ex3_dir_perr_det => ex3_dir_perr_det, + ex4_dir_multihit_det => ex4_dir_multihit_det, + ex4_n_lsu_ddmh_flush => ex4_n_lsu_ddmh_flush, + ex4_ldq_full_flush => ex4_ldq_full_flush, + ex4_miss => ex4_l1miss, + ex4_snd_ld_l2 => ex4_snd_ld_l2, + dcpar_err_flush => dcpar_err_flush, + pe_recov_begin => pe_recov_begin, + + lsu_xu_ex5_cr_rslt => lsu_xu_ex5_cr_rslt, + + rel_way_val_a => rel_way_val_a, + rel_way_val_b => rel_way_val_b, + rel_way_val_c => rel_way_val_c, + rel_way_val_d => rel_way_val_d, + rel_way_val_e => rel_way_val_e, + rel_way_val_f => rel_way_val_f, + rel_way_val_g => rel_way_val_g, + rel_way_val_h => rel_way_val_h, + + rel_way_lock_a => rel_way_lock_a, + rel_way_lock_b => rel_way_lock_b, + rel_way_lock_c => rel_way_lock_c, + rel_way_lock_d => rel_way_lock_d, + rel_way_lock_e => rel_way_lock_e, + rel_way_lock_f => rel_way_lock_f, + rel_way_lock_g => rel_way_lock_g, + rel_way_lock_h => rel_way_lock_h, + + dcarr_up_way_addr => dcarr_up_way_addr, + + lsu_xu_perf_events => lsu_xu_perf_events(21 to 37), + + lsu_xu_spr_xucr0_cslc_xuop => lsu_xu_spr_xucr0_cslc_xuop, + lsu_xu_spr_xucr0_cslc_binv => lsu_xu_spr_xucr0_cslc_binv, + + dc_val_dbg_data => dc_val_dbg_data, + + vdd => vdd, + gnd => gnd, + nclk => nclk, + sg_0 => sg_0, + func_sl_thold_0_b => func_sl_thold_0_b, + func_sl_force => func_sl_force, + func_slp_sl_thold_0_b => func_slp_sl_thold_0_b, + func_slp_sl_force => func_slp_sl_force, + func_nsl_thold_0_b => func_nsl_thold_0_b, + func_nsl_force => func_nsl_force, + func_slp_nsl_thold_0_b => func_slp_nsl_thold_0_b, + func_slp_nsl_force => func_slp_nsl_force, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc, + mpw1_dc_b => mpw1_dc_b, + mpw2_dc_b => mpw2_dc_b, + scan_in => scan_in(1 to 3), + scan_out(0 to 1) => scan_out(1 to 2), + scan_out(2) => dir_scan_out +); + +ex4_dir_perr_det_d <= ex3_dir_perr_det; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- LRU Register Array +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +l1dcdl : entity work.xuq_lsu_dir_lru32(xuq_lsu_dir_lru32) +GENERIC MAP(expand_type => expand_type, + dc_size => dc_size, + lmq_entries => lmq_entries, + cl_size => cl_size) +PORT MAP( + + -- Stage Act Signals + ex1_stg_act => ex1_stg_act_int, + ex2_stg_act => ex2_stg_act_int, + ex3_stg_act => ex3_stg_act_int, + ex4_stg_act => ex4_stg_act_int, + ex5_stg_act => ex5_stg_act_int, + rel1_stg_act => rel1_stg_act_int, + rel2_stg_act => rel2_stg_act_int, + rel3_stg_act => rel3_stg_act_int, + + rel1_val => rel1_val, + rel1_classid => rel1_classid, + rel_mid_val => rel_mid_val, + rel_retry_val => ldq_rel_retry_val, + rel3_val => rel3_val, + rel_st_tag => rel_st_tag, + rel_st_tag_early => rel_st_tag_early, + rel_addr_early => ldq_rel_addr_early(64-(dc_size-3) to 63-cl_size), + rel_lock_en => rel_lock_en, + rel4_recirc_val => recirc_rel_val_q, + rel4_ecc_err => ldq_rel_ecc_err, + + rel_way_val_a => rel_way_val_a, + rel_way_val_b => rel_way_val_b, + rel_way_val_c => rel_way_val_c, + rel_way_val_d => rel_way_val_d, + rel_way_val_e => rel_way_val_e, + rel_way_val_f => rel_way_val_f, + rel_way_val_g => rel_way_val_g, + rel_way_val_h => rel_way_val_h, + + rel_way_lock_a => rel_way_lock_a, + rel_way_lock_b => rel_way_lock_b, + rel_way_lock_c => rel_way_lock_c, + rel_way_lock_d => rel_way_lock_d, + rel_way_lock_e => rel_way_lock_e, + rel_way_lock_f => rel_way_lock_f, + rel_way_lock_g => rel_way_lock_g, + rel_way_lock_h => rel_way_lock_h, + + ex1_p_addr => ex1_p_addr, + ex2_no_lru_upd => ex2_no_lru_upd, + ex3_cache_en => ex3_cache_en, + + ex4_way_a_hit => ex4_way_a_hit, + ex4_way_b_hit => ex4_way_b_hit, + ex4_way_c_hit => ex4_way_c_hit, + ex4_way_d_hit => ex4_way_d_hit, + ex4_way_e_hit => ex4_way_e_hit, + ex4_way_f_hit => ex4_way_f_hit, + ex4_way_g_hit => ex4_way_g_hit, + ex4_way_h_hit => ex4_way_h_hit, + ex3_hit => ex3_l1hit, + + ex3_stg_flush => stg_ex3_flush, + ex4_stg_flush => stg_ex4_flush, + ex5_stg_flush => stg_ex5_flush, + + spr_xucr2_rmt => spr_xucr2_rmt, + spr_xucr0_wlck => spr_xucr0_wlck, + spr_xucr0_dcdis => spr_xucr0_dcdis_q, + spr_xucr0_cls => spr_xucr0_cls_int, + + rel_way_upd_a => rel_way_upd_a, + rel_way_upd_b => rel_way_upd_b, + rel_way_upd_c => rel_way_upd_c, + rel_way_upd_d => rel_way_upd_d, + rel_way_upd_e => rel_way_upd_e, + rel_way_upd_f => rel_way_upd_f, + rel_way_upd_g => rel_way_upd_g, + rel_way_upd_h => rel_way_upd_h, + + rel_way_wen_a => rel_wayA_wen, + rel_way_wen_b => rel_wayB_wen, + rel_way_wen_c => rel_wayC_wen, + rel_way_wen_d => rel_wayD_wen, + rel_way_wen_e => rel_wayE_wen, + rel_way_wen_f => rel_wayF_wen, + rel_way_wen_g => rel_wayG_wen, + rel_way_wen_h => rel_wayH_wen, + + rel_way_clr_a => rel_way_clr_a, + rel_way_clr_b => rel_way_clr_b, + rel_way_clr_c => rel_way_clr_c, + rel_way_clr_d => rel_way_clr_d, + rel_way_clr_e => rel_way_clr_e, + rel_way_clr_f => rel_way_clr_f, + rel_way_clr_g => rel_way_clr_g, + rel_way_clr_h => rel_way_clr_h, + rel_dcarr_val_upd => rel_dcarr_val_upd, + rel_up_way_addr_b => rel_up_way_addr_b, + rel_dcarr_addr_en => rel_dcarr_addr_en, + + lsu_xu_spr_xucr0_clo => lsu_xu_spr_xucr0_clo, + ex4_dir_lru => ex4_dir_lru, + dc_lru_dbg_data => dc_lru_dbg_data, + + vdd => vdd, + gnd => gnd, + nclk => nclk, + sg_0 => sg_0, + func_sl_thold_0_b => func_sl_thold_0_b, + func_sl_force => func_sl_force, + func_nsl_thold_0_b => func_nsl_thold_0_b, + func_nsl_force => func_nsl_force, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc, + mpw1_dc_b => mpw1_dc_b, + mpw2_dc_b => mpw2_dc_b, + scan_in => dir_scan_out, + scan_out => lru_scan_out + ); +end generate dir32k; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Directory Tag Array +-- 1) Contains an Array of Tags +-- 2) Updates Tag on Reload +-- 3) Contains Hit Logic +-- 4) Outputs Way Hit indicators +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +l1dcdt : entity work.xuq_lsu_dir_tag(xuq_lsu_dir_tag) +GENERIC MAP(expand_type => expand_type, + dc_size => dc_size, + cl_size => cl_size, + wayDataSize => wayDataSize, + parBits => parBits, + real_data_add => real_data_add) +PORT MAP ( + + ex2_stg_act => ex2_stg_act_int, + binv2_stg_act => binv2_stg_act_int, + + rel_addr_early => ldq_rel_addr_early, + rel_way_upd_a => rel_way_upd_a, + rel_way_upd_b => rel_way_upd_b, + rel_way_upd_c => rel_way_upd_c, + rel_way_upd_d => rel_way_upd_d, + rel_way_upd_e => rel_way_upd_e, + rel_way_upd_f => rel_way_upd_f, + rel_way_upd_g => rel_way_upd_g, + rel_way_upd_h => rel_way_upd_h, + + inv1_val => ex1_l2_inv_val, + + xu_lsu_spr_xucr0_dcdis => xu_lsu_spr_xucr0_dcdis, + + ex1_p_addr_01 => ex1_dir01_addr, + ex1_p_addr_23 => ex1_dir23_addr, + ex1_p_addr_45 => ex1_dir45_addr, + ex1_p_addr_67 => ex1_dir67_addr, + ex2_ddir_acc_instr => ex2_ddir_acc_instr, + + -- Error Inject + pc_xu_inj_dcachedir_parity => pc_xu_inj_dcachedir_parity, + + dir_arr_rd_addr_01 => dir_arr_rd_addr_01, + dir_arr_rd_addr_23 => dir_arr_rd_addr_23, + dir_arr_rd_addr_45 => dir_arr_rd_addr_45, + dir_arr_rd_addr_67 => dir_arr_rd_addr_67, + dir_arr_rd_data => dir_arr_rd_data, + + dir_wr_way => dir_wr_way_int, + dir_arr_wr_addr => dir_arr_wr_addr_int, + dir_arr_wr_data => dir_arr_wr_data_int, + + ex2_wayA_tag => ex2_wayA_tag, + ex2_wayB_tag => ex2_wayB_tag, + ex2_wayC_tag => ex2_wayC_tag, + ex2_wayD_tag => ex2_wayD_tag, + ex2_wayE_tag => ex2_wayE_tag, + ex2_wayF_tag => ex2_wayF_tag, + ex2_wayG_tag => ex2_wayG_tag, + ex2_wayH_tag => ex2_wayH_tag, + + ex3_way_tag_par_a => ex3_way_tag_par_a, + ex3_way_tag_par_b => ex3_way_tag_par_b, + ex3_way_tag_par_c => ex3_way_tag_par_c, + ex3_way_tag_par_d => ex3_way_tag_par_d, + ex3_way_tag_par_e => ex3_way_tag_par_e, + ex3_way_tag_par_f => ex3_way_tag_par_f, + ex3_way_tag_par_g => ex3_way_tag_par_g, + ex3_way_tag_par_h => ex3_way_tag_par_h, + + ex3_tag_way_perr => ex3_tag_way_perr, + + vdd => vdd, + gnd => gnd, + nclk => nclk, + sg_0 => sg_0, + func_sl_thold_0_b => func_sl_thold_0_b, + func_sl_force => func_sl_force, + func_slp_sl_thold_0_b => func_slp_sl_thold_0_b, + func_slp_sl_force => func_slp_sl_force, + d_mode_dc => d_mode_dc, + delay_lclkr_dc => delay_lclkr_dc, + mpw1_dc_b => mpw1_dc_b, + mpw2_dc_b => mpw2_dc_b, + scan_in => lru_scan_out, + scan_out => tag_scan_out + ); +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Debug Data +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +dir_arr_dbg_data_d <= dir_wr_enable_int & dir_wr_way_int & dir_arr_wr_addr_int & dir_arr_wr_data_int & + ex1_dir_acc_val & ex1_l2_inv_val & binv1_ex1_stg_act & recirc_rel_val_q & + lwr_p_addr_q(53 to 57); + +dir_arr_dbg_data <= dir_arr_dbg_data_q; + +dc_dir_dbg_data <= ldq_rel1_val_stg_q & ldq_rel_mid_stg_q & ldq_rel3_val_stg_q & ldq_rel_data_stg_q & + ldq_rel_set_stg_q & rel24_addr_q; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Outputs +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +xu_derat_ex1_epn_arr <= ex1_agen_addr(64-(2**regmode) to 51); +xu_derat_ex1_epn_nonarr <= ex1_eff_addr(64-(2**regmode) to 51); +ex3_dcbtls_instr <= dcbtls_instr_ex3; +ex3_dcbtstls_instr <= dcbtstls_instr_ex3; +ex3_stg_flush <= stg_ex3_flush; +ex4_stg_flush <= stg_ex4_flush; +lsu_xu_ex3_ddir_par_err <= ex3_dir_perr_det; +lsu_xu_ex4_ldq_full_flush <= ex4_ldq_full_flush; +ex4_dir_perr_det <= ex4_dir_perr_det_q; +spr_xucr0_cls <= spr_xucr0_cls_int; +ldq_recirc_rel_val <= recirc_rel_val_q; +xu_derat_rf1_binv_val <= rf1_l2_inv_val; +dir_arr_wr_addr <= dir_arr_wr_addr_int; +dir_arr_wr_data <= dir_arr_wr_data_int; +dir_wr_way <= dir_wr_way_int; +ex2_p_addr_lwr <= ex2_p_addr_lwr_int(52 to 57); +ex3_cache_acc <= ex3_cache_acc_int; + +ex1_stg_act <= ex1_stg_act_int; +ex2_stg_act <= ex2_stg_act_int; +ex3_stg_act <= ex3_stg_act_int; +ex4_stg_act <= ex4_stg_act_int; +binv1_stg_act <= binv1_stg_act_int; +binv2_stg_act <= binv2_stg_act_int; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Registers +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +lwr_p_addr_reg: tri_rlmreg_p +generic map (width => 12, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv1_ex1_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(lwr_p_addr_offset to lwr_p_addr_offset + lwr_p_addr_d'length-1), + scout => sov(lwr_p_addr_offset to lwr_p_addr_offset + lwr_p_addr_d'length-1), + din => lwr_p_addr_d, + dout => lwr_p_addr_q); +ldq_rel1_val_stg_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ldq_rel1_val_stg_offset), + scout => sov(ldq_rel1_val_stg_offset), + din => ldq_rel1_val_stg_d, + dout => ldq_rel1_val_stg_q); +ldq_rel_mid_stg_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ldq_rel_mid_stg_offset), + scout => sov(ldq_rel_mid_stg_offset), + din => ldq_rel_mid_stg_d, + dout => ldq_rel_mid_stg_q); +ldq_rel3_val_stg_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ldq_rel3_val_stg_offset), + scout => sov(ldq_rel3_val_stg_offset), + din => ldq_rel3_val_stg_d, + dout => ldq_rel3_val_stg_q); +ldq_rel_data_stg_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ldq_rel_data_stg_d, + dout(0) => ldq_rel_data_stg_q); +ldq_rel_set_stg_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ldq_rel_set_stg_d, + dout(0) => ldq_rel_set_stg_q); +rel24_addr_reg: tri_regk +generic map (width => real_data_add-11, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act_int, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel24_addr_d, + dout => rel24_addr_q); +spr_xucr0_dcdis_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(spr_xucr0_dcdis_offset), + scout => sov(spr_xucr0_dcdis_offset), + din => spr_xucr0_dcdis_d, + dout => spr_xucr0_dcdis_q); +ex2_frc_align_reg: tri_regk +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act_int, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex2_frc_align_d, + dout => ex2_frc_align_q); + +ldq_rel_stg24_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ldq_rel_stg24_val_d, + dout(0) => ldq_rel_stg24_val_q); + +ex4_dir_perr_det_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_dir_perr_det_offset), + scout => sov(ex4_dir_perr_det_offset), + din => ex4_dir_perr_det_d, + dout => ex4_dir_perr_det_q); + +recirc_rel_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(recirc_rel_val_offset), + scout => sov(recirc_rel_val_offset), + din => recirc_rel_val_d, + dout => recirc_rel_val_q); + +trace_bus_enable_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(trace_bus_enable_offset), + scout => sov(trace_bus_enable_offset), + din => pc_xu_trace_bus_enable, + dout => trace_bus_enable_q); + +dir_arr_dbg_data_reg: tri_regk +generic map (width => 61, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => trace_bus_enable_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => dir_arr_dbg_data_d, + dout => dir_arr_dbg_data_q); + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +siv(0 to scan_right) <= sov(1 to scan_right) & tag_scan_out; +scan_out(3) <= sov(0); +end xuq_lsu_dir; diff --git a/rel/src/vhdl/work/xuq_lsu_dir_lru16.vhdl b/rel/src/vhdl/work/xuq_lsu_dir_lru16.vhdl new file mode 100644 index 0000000..3377bdd --- /dev/null +++ b/rel/src/vhdl/work/xuq_lsu_dir_lru16.vhdl @@ -0,0 +1,4181 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XU LSU L1 Data Directory LRU Register Array + +library ibm, ieee, work, tri, support; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use tri.tri_latches_pkg.all; +use support.power_logic_pkg.all; + +entity xuq_lsu_dir_lru16 is +generic(expand_type : integer := 2; + dc_size : natural := 14; + lmq_entries : integer := 8; + cl_size : natural := 6); +port( + + ex1_stg_act :in std_ulogic; + ex2_stg_act :in std_ulogic; + ex3_stg_act :in std_ulogic; + ex4_stg_act :in std_ulogic; + ex5_stg_act :in std_ulogic; + rel1_stg_act :in std_ulogic; + rel2_stg_act :in std_ulogic; + rel3_stg_act :in std_ulogic; + + rel1_val :in std_ulogic; + rel1_classid :in std_ulogic_vector(0 to 1); + rel_mid_val :in std_ulogic; + rel_retry_val :in std_ulogic; + rel3_val :in std_ulogic; + rel4_recirc_val :in std_ulogic; + rel4_ecc_err :in std_ulogic; + rel_st_tag_early :in std_ulogic_vector(1 to 3); + rel_st_tag :in std_ulogic_vector(1 to 3); + rel_addr_early :in std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + rel_lock_en :in std_ulogic; + + rel_way_val_a :in std_ulogic; + rel_way_val_b :in std_ulogic; + rel_way_val_c :in std_ulogic; + rel_way_val_d :in std_ulogic; + rel_way_val_e :in std_ulogic; + rel_way_val_f :in std_ulogic; + rel_way_val_g :in std_ulogic; + rel_way_val_h :in std_ulogic; + + rel_way_lock_a :in std_ulogic; + rel_way_lock_b :in std_ulogic; + rel_way_lock_c :in std_ulogic; + rel_way_lock_d :in std_ulogic; + rel_way_lock_e :in std_ulogic; + rel_way_lock_f :in std_ulogic; + rel_way_lock_g :in std_ulogic; + rel_way_lock_h :in std_ulogic; + + ex1_p_addr :in std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + ex3_cache_en :in std_ulogic; + ex2_no_lru_upd :in std_ulogic; + + ex4_way_a_hit :in std_ulogic; + ex4_way_b_hit :in std_ulogic; + ex4_way_c_hit :in std_ulogic; + ex4_way_d_hit :in std_ulogic; + ex4_way_e_hit :in std_ulogic; + ex4_way_f_hit :in std_ulogic; + ex4_way_g_hit :in std_ulogic; + ex4_way_h_hit :in std_ulogic; + ex3_hit :in std_ulogic; + + spr_xucr2_rmt :in std_ulogic_vector(0 to 31); + spr_xucr0_wlck :in std_ulogic; + spr_xucr0_dcdis :in std_ulogic; + spr_xucr0_cls :in std_ulogic; + + ex3_stg_flush :in std_ulogic; + ex4_stg_flush :in std_ulogic; + ex5_stg_flush :in std_ulogic; + + rel_way_upd_a :out std_ulogic; + rel_way_upd_b :out std_ulogic; + rel_way_upd_c :out std_ulogic; + rel_way_upd_d :out std_ulogic; + rel_way_upd_e :out std_ulogic; + rel_way_upd_f :out std_ulogic; + rel_way_upd_g :out std_ulogic; + rel_way_upd_h :out std_ulogic; + + rel_way_wen_a :out std_ulogic; + rel_way_wen_b :out std_ulogic; + rel_way_wen_c :out std_ulogic; + rel_way_wen_d :out std_ulogic; + rel_way_wen_e :out std_ulogic; + rel_way_wen_f :out std_ulogic; + rel_way_wen_g :out std_ulogic; + rel_way_wen_h :out std_ulogic; + + rel_way_clr_a :out std_ulogic; + rel_way_clr_b :out std_ulogic; + rel_way_clr_c :out std_ulogic; + rel_way_clr_d :out std_ulogic; + rel_way_clr_e :out std_ulogic; + rel_way_clr_f :out std_ulogic; + rel_way_clr_g :out std_ulogic; + rel_way_clr_h :out std_ulogic; + rel_dcarr_val_upd :out std_ulogic; + rel_up_way_addr_b :out std_ulogic_vector(0 to 2); + rel_dcarr_addr_en :out std_ulogic; + + lsu_xu_spr_xucr0_clo :out std_ulogic; + + ex4_dir_lru :out std_ulogic_vector(0 to 6); + + dc_lru_dbg_data :out std_ulogic_vector(0 to 81); + + vdd :inout power_logic; + gnd :inout power_logic; + nclk :in clk_logic; + sg_0 :in std_ulogic; + func_sl_thold_0_b :in std_ulogic; + func_sl_force :in std_ulogic; + func_nsl_thold_0_b :in std_ulogic; + func_nsl_force :in std_ulogic; + d_mode_dc :in std_ulogic; + delay_lclkr_dc :in std_ulogic; + mpw1_dc_b :in std_ulogic; + mpw2_dc_b :in std_ulogic; + scan_in :in std_ulogic; + scan_out :out std_ulogic + ); +-- synopsys translate_off +-- synopsys translate_on +end xuq_lsu_dir_lru16; +---- +ARCHITECTURE XUQ_LSU_DIR_LRU16 + OF XUQ_LSU_DIR_LRU16 + IS +---------------------------- +-- components +---------------------------- +---------------------------- +-- constants +---------------------------- +constant congr_cl0_lru_offset :natural := 0; +constant congr_cl1_lru_offset :natural := congr_cl0_lru_offset + 7; +constant congr_cl2_lru_offset :natural := congr_cl1_lru_offset + 7; +constant congr_cl3_lru_offset :natural := congr_cl2_lru_offset + 7; +constant congr_cl4_lru_offset :natural := congr_cl3_lru_offset + 7; +constant congr_cl5_lru_offset :natural := congr_cl4_lru_offset + 7; +constant congr_cl6_lru_offset :natural := congr_cl5_lru_offset + 7; +constant congr_cl7_lru_offset :natural := congr_cl6_lru_offset + 7; +constant congr_cl8_lru_offset :natural := congr_cl7_lru_offset + 7; +constant congr_cl9_lru_offset :natural := congr_cl8_lru_offset + 7; +constant congr_cl10_lru_offset :natural := congr_cl9_lru_offset + 7; +constant congr_cl11_lru_offset :natural := congr_cl10_lru_offset + 7; +constant congr_cl12_lru_offset :natural := congr_cl11_lru_offset + 7; +constant congr_cl13_lru_offset :natural := congr_cl12_lru_offset + 7; +constant congr_cl14_lru_offset :natural := congr_cl13_lru_offset + 7; +constant congr_cl15_lru_offset :natural := congr_cl14_lru_offset + 7; +constant congr_cl16_lru_offset :natural := congr_cl15_lru_offset + 7; +constant congr_cl17_lru_offset :natural := congr_cl16_lru_offset + 7; +constant congr_cl18_lru_offset :natural := congr_cl17_lru_offset + 7; +constant congr_cl19_lru_offset :natural := congr_cl18_lru_offset + 7; +constant congr_cl20_lru_offset :natural := congr_cl19_lru_offset + 7; +constant congr_cl21_lru_offset :natural := congr_cl20_lru_offset + 7; +constant congr_cl22_lru_offset :natural := congr_cl21_lru_offset + 7; +constant congr_cl23_lru_offset :natural := congr_cl22_lru_offset + 7; +constant congr_cl24_lru_offset :natural := congr_cl23_lru_offset + 7; +constant congr_cl25_lru_offset :natural := congr_cl24_lru_offset + 7; +constant congr_cl26_lru_offset :natural := congr_cl25_lru_offset + 7; +constant congr_cl27_lru_offset :natural := congr_cl26_lru_offset + 7; +constant congr_cl28_lru_offset :natural := congr_cl27_lru_offset + 7; +constant congr_cl29_lru_offset :natural := congr_cl28_lru_offset + 7; +constant congr_cl30_lru_offset :natural := congr_cl29_lru_offset + 7; +constant congr_cl31_lru_offset :natural := congr_cl30_lru_offset + 7; +constant congr_cl_lru_b_offset :natural := congr_cl31_lru_offset + 7; +constant rel_congr_cl_lru_b_offset :natural := congr_cl_lru_b_offset + 7; +constant reld_q_sel_offset :natural := rel_congr_cl_lru_b_offset + 7; +constant ex5_congr_cl_offset :natural := reld_q_sel_offset + 8; +constant rel_congr_cl_offset :natural := ex5_congr_cl_offset + 5; +constant relu_congr_cl_offset :natural := rel_congr_cl_offset + 5; +constant ex5_lru_upd_offset :natural := relu_congr_cl_offset + 5; +constant rel2_val_offset :natural := ex5_lru_upd_offset + 7; +constant relu_val_wen_offset :natural := rel2_val_offset + 1; +constant ex4_hit_offset :natural := relu_val_wen_offset + 1; +constant ex4_c_acc_offset :natural := ex4_hit_offset + 1; +constant ex5_c_acc_offset :natural := ex4_c_acc_offset + 1; +constant ex6_c_acc_val_offset :natural := ex5_c_acc_offset + 1; +constant ex3_congr_cl_offset :natural := ex6_c_acc_val_offset + 1; +constant rel_val_wen_offset :natural := ex3_congr_cl_offset + 5; +constant relu_lru_upd_offset :natural := rel_val_wen_offset + 1; +constant rel_way_qsel_offset :natural := relu_lru_upd_offset + 7; +constant rel_val_qsel_offset :natural := rel_way_qsel_offset + 8; +constant rel_way_early_qsel_offset :natural := rel_val_qsel_offset + 1; +constant rel_val_early_qsel_offset :natural := rel_way_early_qsel_offset + 8; +constant rel4_val_offset :natural := rel_val_early_qsel_offset + 1; +constant rel2_mid_val_offset :natural := rel4_val_offset + 1; +constant rel4_retry_val_offset :natural := rel2_mid_val_offset + 1; +constant rel2_wlock_offset :natural := rel4_retry_val_offset + 1; +constant reld_q0_congr_cl_offset :natural := rel2_wlock_offset + 8; +constant reld_q1_congr_cl_offset :natural := reld_q0_congr_cl_offset + 5; +constant reld_q2_congr_cl_offset :natural := reld_q1_congr_cl_offset + 5; +constant reld_q3_congr_cl_offset :natural := reld_q2_congr_cl_offset + 5; +constant reld_q4_congr_cl_offset :natural := reld_q3_congr_cl_offset + 5; +constant reld_q5_congr_cl_offset :natural := reld_q4_congr_cl_offset + 5; +constant reld_q6_congr_cl_offset :natural := reld_q5_congr_cl_offset + 5; +constant reld_q7_congr_cl_offset :natural := reld_q6_congr_cl_offset + 5; +constant reld_q0_way_offset :natural := reld_q7_congr_cl_offset + 5; +constant reld_q1_way_offset :natural := reld_q0_way_offset + 8; +constant reld_q2_way_offset :natural := reld_q1_way_offset + 8; +constant reld_q3_way_offset :natural := reld_q2_way_offset + 8; +constant reld_q4_way_offset :natural := reld_q3_way_offset + 8; +constant reld_q5_way_offset :natural := reld_q4_way_offset + 8; +constant reld_q6_way_offset :natural := reld_q5_way_offset + 8; +constant reld_q7_way_offset :natural := reld_q6_way_offset + 8; +constant reld_q0_val_offset :natural := reld_q7_way_offset + 8; +constant reld_q1_val_offset :natural := reld_q0_val_offset + 1; +constant reld_q2_val_offset :natural := reld_q1_val_offset + 1; +constant reld_q3_val_offset :natural := reld_q2_val_offset + 1; +constant reld_q4_val_offset :natural := reld_q3_val_offset + 1; +constant reld_q5_val_offset :natural := reld_q4_val_offset + 1; +constant reld_q6_val_offset :natural := reld_q5_val_offset + 1; +constant reld_q7_val_offset :natural := reld_q6_val_offset + 1; +constant reld_q0_lock_offset :natural := reld_q7_val_offset + 1; +constant reld_q1_lock_offset :natural := reld_q0_lock_offset + 1; +constant reld_q2_lock_offset :natural := reld_q1_lock_offset + 1; +constant reld_q3_lock_offset :natural := reld_q2_lock_offset + 1; +constant reld_q4_lock_offset :natural := reld_q3_lock_offset + 1; +constant reld_q5_lock_offset :natural := reld_q4_lock_offset + 1; +constant reld_q6_lock_offset :natural := reld_q5_lock_offset + 1; +constant reld_q7_lock_offset :natural := reld_q6_lock_offset + 1; +constant rel_m_q_way_offset :natural := reld_q7_lock_offset + 1; +constant ex3_no_lru_upd_offset :natural := rel_m_q_way_offset + 8; +constant rel2_lock_en_offset :natural := ex3_no_lru_upd_offset + 1; +constant xucr0_clo_offset :natural := rel2_lock_en_offset + 1; +constant rel_up_way_addr_offset :natural := xucr0_clo_offset + 1; +constant rel_dcarr_addr_en_offset :natural := rel_up_way_addr_offset + 3; +constant rel_dcarr_val_upd_offset :natural := rel_dcarr_addr_en_offset + 1; +constant congr_cl_ex3_ex4_cmp_offset :natural := rel_dcarr_val_upd_offset + 1; +constant congr_cl_ex3_ex5_cmp_offset :natural := congr_cl_ex3_ex4_cmp_offset + 1; +constant congr_cl_ex3_ex6_cmp_offset :natural := congr_cl_ex3_ex5_cmp_offset + 1; +constant congr_cl_ex3_rel2_cmp_offset :natural := congr_cl_ex3_ex6_cmp_offset + 1; +constant congr_cl_ex3_rel_upd_cmp_offset :natural := congr_cl_ex3_rel2_cmp_offset + 1; +constant congr_cl_rel1_ex4_cmp_offset :natural := congr_cl_ex3_rel_upd_cmp_offset + 1; +constant congr_cl_rel1_ex5_cmp_offset :natural := congr_cl_rel1_ex4_cmp_offset + 1; +constant congr_cl_rel1_ex6_cmp_offset :natural := congr_cl_rel1_ex5_cmp_offset + 1; +constant congr_cl_rel1_rel2_cmp_offset :natural := congr_cl_rel1_ex6_cmp_offset + 1; +constant congr_cl_rel1_relu_cmp_offset :natural := congr_cl_rel1_rel2_cmp_offset + 1; +constant congr_cl_rel1_rel_upd_cmp_offset :natural := congr_cl_rel1_relu_cmp_offset + 1; +constant congr_cl_act_offset :natural := congr_cl_rel1_rel_upd_cmp_offset + 1; +constant scan_right :natural := congr_cl_act_offset + 1 - 1; +---------------------------- +-- signals +---------------------------- +signal congr_cl0_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl0_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl0_lru_wen :std_ulogic; +signal xu_op_cl0_lru_wen :std_ulogic; +signal rel_cl0_lru_wen :std_ulogic; +signal rel_ldst_cl0_lru :std_ulogic_vector(0 to 6); +signal congr_cl1_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl1_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl1_lru_wen :std_ulogic; +signal xu_op_cl1_lru_wen :std_ulogic; +signal rel_cl1_lru_wen :std_ulogic; +signal rel_ldst_cl1_lru :std_ulogic_vector(0 to 6); +signal congr_cl2_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl2_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl2_lru_wen :std_ulogic; +signal xu_op_cl2_lru_wen :std_ulogic; +signal rel_cl2_lru_wen :std_ulogic; +signal rel_ldst_cl2_lru :std_ulogic_vector(0 to 6); +signal congr_cl3_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl3_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl3_lru_wen :std_ulogic; +signal xu_op_cl3_lru_wen :std_ulogic; +signal rel_cl3_lru_wen :std_ulogic; +signal rel_ldst_cl3_lru :std_ulogic_vector(0 to 6); +signal congr_cl4_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl4_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl4_lru_wen :std_ulogic; +signal xu_op_cl4_lru_wen :std_ulogic; +signal rel_cl4_lru_wen :std_ulogic; +signal rel_ldst_cl4_lru :std_ulogic_vector(0 to 6); +signal congr_cl5_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl5_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl5_lru_wen :std_ulogic; +signal xu_op_cl5_lru_wen :std_ulogic; +signal rel_cl5_lru_wen :std_ulogic; +signal rel_ldst_cl5_lru :std_ulogic_vector(0 to 6); +signal congr_cl6_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl6_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl6_lru_wen :std_ulogic; +signal xu_op_cl6_lru_wen :std_ulogic; +signal rel_cl6_lru_wen :std_ulogic; +signal rel_ldst_cl6_lru :std_ulogic_vector(0 to 6); +signal congr_cl7_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl7_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl7_lru_wen :std_ulogic; +signal xu_op_cl7_lru_wen :std_ulogic; +signal rel_cl7_lru_wen :std_ulogic; +signal rel_ldst_cl7_lru :std_ulogic_vector(0 to 6); +signal congr_cl8_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl8_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl8_lru_wen :std_ulogic; +signal xu_op_cl8_lru_wen :std_ulogic; +signal rel_cl8_lru_wen :std_ulogic; +signal rel_ldst_cl8_lru :std_ulogic_vector(0 to 6); +signal congr_cl9_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl9_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl9_lru_wen :std_ulogic; +signal xu_op_cl9_lru_wen :std_ulogic; +signal rel_cl9_lru_wen :std_ulogic; +signal rel_ldst_cl9_lru :std_ulogic_vector(0 to 6); +signal congr_cl10_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl10_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl10_lru_wen :std_ulogic; +signal xu_op_cl10_lru_wen :std_ulogic; +signal rel_cl10_lru_wen :std_ulogic; +signal rel_ldst_cl10_lru :std_ulogic_vector(0 to 6); +signal congr_cl11_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl11_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl11_lru_wen :std_ulogic; +signal xu_op_cl11_lru_wen :std_ulogic; +signal rel_cl11_lru_wen :std_ulogic; +signal rel_ldst_cl11_lru :std_ulogic_vector(0 to 6); +signal congr_cl12_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl12_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl12_lru_wen :std_ulogic; +signal xu_op_cl12_lru_wen :std_ulogic; +signal rel_cl12_lru_wen :std_ulogic; +signal rel_ldst_cl12_lru :std_ulogic_vector(0 to 6); +signal congr_cl13_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl13_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl13_lru_wen :std_ulogic; +signal xu_op_cl13_lru_wen :std_ulogic; +signal rel_cl13_lru_wen :std_ulogic; +signal rel_ldst_cl13_lru :std_ulogic_vector(0 to 6); +signal congr_cl14_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl14_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl14_lru_wen :std_ulogic; +signal xu_op_cl14_lru_wen :std_ulogic; +signal rel_cl14_lru_wen :std_ulogic; +signal rel_ldst_cl14_lru :std_ulogic_vector(0 to 6); +signal congr_cl15_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl15_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl15_lru_wen :std_ulogic; +signal xu_op_cl15_lru_wen :std_ulogic; +signal rel_cl15_lru_wen :std_ulogic; +signal rel_ldst_cl15_lru :std_ulogic_vector(0 to 6); +signal congr_cl16_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl16_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl16_lru_wen :std_ulogic; +signal xu_op_cl16_lru_wen :std_ulogic; +signal rel_cl16_lru_wen :std_ulogic; +signal rel_ldst_cl16_lru :std_ulogic_vector(0 to 6); +signal congr_cl17_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl17_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl17_lru_wen :std_ulogic; +signal xu_op_cl17_lru_wen :std_ulogic; +signal rel_cl17_lru_wen :std_ulogic; +signal rel_ldst_cl17_lru :std_ulogic_vector(0 to 6); +signal congr_cl18_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl18_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl18_lru_wen :std_ulogic; +signal xu_op_cl18_lru_wen :std_ulogic; +signal rel_cl18_lru_wen :std_ulogic; +signal rel_ldst_cl18_lru :std_ulogic_vector(0 to 6); +signal congr_cl19_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl19_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl19_lru_wen :std_ulogic; +signal xu_op_cl19_lru_wen :std_ulogic; +signal rel_cl19_lru_wen :std_ulogic; +signal rel_ldst_cl19_lru :std_ulogic_vector(0 to 6); +signal congr_cl20_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl20_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl20_lru_wen :std_ulogic; +signal xu_op_cl20_lru_wen :std_ulogic; +signal rel_cl20_lru_wen :std_ulogic; +signal rel_ldst_cl20_lru :std_ulogic_vector(0 to 6); +signal congr_cl21_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl21_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl21_lru_wen :std_ulogic; +signal xu_op_cl21_lru_wen :std_ulogic; +signal rel_cl21_lru_wen :std_ulogic; +signal rel_ldst_cl21_lru :std_ulogic_vector(0 to 6); +signal congr_cl22_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl22_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl22_lru_wen :std_ulogic; +signal xu_op_cl22_lru_wen :std_ulogic; +signal rel_cl22_lru_wen :std_ulogic; +signal rel_ldst_cl22_lru :std_ulogic_vector(0 to 6); +signal congr_cl23_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl23_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl23_lru_wen :std_ulogic; +signal xu_op_cl23_lru_wen :std_ulogic; +signal rel_cl23_lru_wen :std_ulogic; +signal rel_ldst_cl23_lru :std_ulogic_vector(0 to 6); +signal congr_cl24_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl24_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl24_lru_wen :std_ulogic; +signal xu_op_cl24_lru_wen :std_ulogic; +signal rel_cl24_lru_wen :std_ulogic; +signal rel_ldst_cl24_lru :std_ulogic_vector(0 to 6); +signal congr_cl25_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl25_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl25_lru_wen :std_ulogic; +signal xu_op_cl25_lru_wen :std_ulogic; +signal rel_cl25_lru_wen :std_ulogic; +signal rel_ldst_cl25_lru :std_ulogic_vector(0 to 6); +signal congr_cl26_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl26_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl26_lru_wen :std_ulogic; +signal xu_op_cl26_lru_wen :std_ulogic; +signal rel_cl26_lru_wen :std_ulogic; +signal rel_ldst_cl26_lru :std_ulogic_vector(0 to 6); +signal congr_cl27_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl27_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl27_lru_wen :std_ulogic; +signal xu_op_cl27_lru_wen :std_ulogic; +signal rel_cl27_lru_wen :std_ulogic; +signal rel_ldst_cl27_lru :std_ulogic_vector(0 to 6); +signal congr_cl28_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl28_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl28_lru_wen :std_ulogic; +signal xu_op_cl28_lru_wen :std_ulogic; +signal rel_cl28_lru_wen :std_ulogic; +signal rel_ldst_cl28_lru :std_ulogic_vector(0 to 6); +signal congr_cl29_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl29_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl29_lru_wen :std_ulogic; +signal xu_op_cl29_lru_wen :std_ulogic; +signal rel_cl29_lru_wen :std_ulogic; +signal rel_ldst_cl29_lru :std_ulogic_vector(0 to 6); +signal congr_cl30_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl30_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl30_lru_wen :std_ulogic; +signal xu_op_cl30_lru_wen :std_ulogic; +signal rel_cl30_lru_wen :std_ulogic; +signal rel_ldst_cl30_lru :std_ulogic_vector(0 to 6); +signal congr_cl31_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl31_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl31_lru_wen :std_ulogic; +signal xu_op_cl31_lru_wen :std_ulogic; +signal rel_cl31_lru_wen :std_ulogic; +signal rel_ldst_cl31_lru :std_ulogic_vector(0 to 6); +signal ex1_congr_cl :std_ulogic_vector(3 to 7); +signal ex2_congr_cl_d :std_ulogic_vector(3 to 7); +signal ex2_congr_cl_q :std_ulogic_vector(3 to 7); +signal ex3_congr_cl_d :std_ulogic_vector(3 to 7); +signal ex3_congr_cl_q :std_ulogic_vector(3 to 7); +signal ex4_congr_cl_d :std_ulogic_vector(3 to 7); +signal ex4_congr_cl_q :std_ulogic_vector(3 to 7); +signal ex5_congr_cl_d :std_ulogic_vector(3 to 7); +signal ex5_congr_cl_q :std_ulogic_vector(3 to 7); +signal ex6_congr_cl_d :std_ulogic_vector(3 to 7); +signal ex6_congr_cl_q :std_ulogic_vector(3 to 7); +signal rel_early_congr_cl :std_ulogic_vector(3 to 7); +signal rel_congr_cl_d :std_ulogic_vector(3 to 7); +signal rel_congr_cl_q :std_ulogic_vector(3 to 7); +signal rel_congr_cl_stg_d :std_ulogic_vector(3 to 7); +signal rel_congr_cl_stg_q :std_ulogic_vector(3 to 7); +signal relu_congr_cl_d :std_ulogic_vector(3 to 7); +signal relu_congr_cl_q :std_ulogic_vector(3 to 7); +signal rel2_val_d :std_ulogic; +signal rel2_val_q :std_ulogic; +signal relu_val_wen_d :std_ulogic; +signal relu_val_wen_q :std_ulogic; +signal rel_val_wen_d :std_ulogic; +signal rel_val_wen_q :std_ulogic; +signal congr_cl_lru_b_q :std_ulogic_vector(0 to 6); +signal rel_wayA_clr :std_ulogic; +signal rel_wayB_clr :std_ulogic; +signal rel_wayC_clr :std_ulogic; +signal rel_wayD_clr :std_ulogic; +signal rel_wayE_clr :std_ulogic; +signal rel_wayF_clr :std_ulogic; +signal rel_wayG_clr :std_ulogic; +signal rel_wayH_clr :std_ulogic; +signal rel_hit_vec :std_ulogic_vector(0 to 7); +signal hit_wayA_upd :std_ulogic_vector(0 to 6); +signal hit_wayB_upd :std_ulogic_vector(0 to 6); +signal hit_wayC_upd :std_ulogic_vector(0 to 6); +signal hit_wayD_upd :std_ulogic_vector(0 to 6); +signal hit_wayE_upd :std_ulogic_vector(0 to 6); +signal hit_wayF_upd :std_ulogic_vector(0 to 6); +signal hit_wayG_upd :std_ulogic_vector(0 to 6); +signal hit_wayh_upd :std_ulogic_vector(0 to 6); +signal rel_hit_wayA_upd :std_ulogic_vector(0 to 6); +signal rel_hit_wayB_upd :std_ulogic_vector(0 to 6); +signal rel_hit_wayC_upd :std_ulogic_vector(0 to 6); +signal rel_hit_wayD_upd :std_ulogic_vector(0 to 6); +signal rel_hit_wayE_upd :std_ulogic_vector(0 to 6); +signal rel_hit_wayF_upd :std_ulogic_vector(0 to 6); +signal rel_hit_wayG_upd :std_ulogic_vector(0 to 6); +signal rel_hit_wayh_upd :std_ulogic_vector(0 to 6); +signal ldst_wayA_hit :std_ulogic; +signal ldst_wayB_hit :std_ulogic; +signal ldst_wayC_hit :std_ulogic; +signal ldst_wayD_hit :std_ulogic; +signal ldst_wayE_hit :std_ulogic; +signal ldst_wayF_hit :std_ulogic; +signal ldst_wayG_hit :std_ulogic; +signal ldst_wayH_hit :std_ulogic; +signal lru_upd :std_ulogic_vector(0 to 6); +signal relu_lru_upd_d :std_ulogic_vector(0 to 6); +signal relu_lru_upd_q :std_ulogic_vector(0 to 6); +signal rel_lru_val_d :std_ulogic_vector(0 to 6); +signal rel_lru_val_q :std_ulogic_vector(0 to 6); +signal ex5_lru_upd_d :std_ulogic_vector(0 to 6); +signal ex5_lru_upd_q :std_ulogic_vector(0 to 6); +signal ex6_lru_upd_d :std_ulogic_vector(0 to 6); +signal ex6_lru_upd_q :std_ulogic_vector(0 to 6); +signal ex4_hit_d :std_ulogic; +signal ex4_hit_q :std_ulogic; +signal ex3_c_acc_val :std_ulogic; +signal ex4_c_acc_val :std_ulogic; +signal ex4_c_acc :std_ulogic; +signal ex4_c_acc_d :std_ulogic; +signal ex4_c_acc_q :std_ulogic; +signal ex5_c_acc_val :std_ulogic; +signal ex5_c_acc_d :std_ulogic; +signal ex5_c_acc_q :std_ulogic; +signal ex6_c_acc_val_d :std_ulogic; +signal ex6_c_acc_val_q :std_ulogic; +signal ex3_flush :std_ulogic; +signal ex4_flush :std_ulogic; +signal ex5_flush :std_ulogic; +signal xu_op_lru :std_ulogic_vector(0 to 6); +signal rel_op_lru :std_ulogic_vector(0 to 6); +signal ldst_hit_vector :std_ulogic_vector(0 to 7); +signal arr_congr_cl_lru :std_ulogic_vector(0 to 6); +signal rel_congr_cl_lru :std_ulogic_vector(0 to 6); +signal p0_arr_lru_rd :std_ulogic_vector(0 to 6); +signal p1_arr_lru_rd :std_ulogic_vector(0 to 6); +signal rel_congr_cl_lru_b_q :std_ulogic_vector(0 to 6); +signal congr_cl_ex3_ex4_m :std_ulogic; +signal congr_cl_ex3_ex5_m :std_ulogic; +signal congr_cl_ex3_p0_m :std_ulogic; +signal congr_cl_ex3_rel2_m :std_ulogic; +signal congr_cl_ex3_p1_m :std_ulogic; +signal congr_cl_ex3_ex4_cmp_d :std_ulogic; +signal congr_cl_ex3_ex4_cmp_q :std_ulogic; +signal congr_cl_ex3_ex5_cmp_d :std_ulogic; +signal congr_cl_ex3_ex5_cmp_q :std_ulogic; +signal congr_cl_ex3_ex6_cmp_d :std_ulogic; +signal congr_cl_ex3_ex6_cmp_q :std_ulogic; +signal congr_cl_ex3_rel2_cmp_d :std_ulogic; +signal congr_cl_ex3_rel2_cmp_q :std_ulogic; +signal congr_cl_ex3_rel_upd_cmp_d :std_ulogic; +signal congr_cl_ex3_rel_upd_cmp_q :std_ulogic; +signal congr_cl_rel1_ex4_cmp_d :std_ulogic; +signal congr_cl_rel1_ex4_cmp_q :std_ulogic; +signal congr_cl_rel1_ex5_cmp_d :std_ulogic; +signal congr_cl_rel1_ex5_cmp_q :std_ulogic; +signal congr_cl_rel1_ex6_cmp_d :std_ulogic; +signal congr_cl_rel1_ex6_cmp_q :std_ulogic; +signal congr_cl_rel1_rel2_cmp_d :std_ulogic; +signal congr_cl_rel1_rel2_cmp_q :std_ulogic; +signal congr_cl_rel1_relu_cmp_d :std_ulogic; +signal congr_cl_rel1_relu_cmp_q :std_ulogic; +signal congr_cl_rel1_rel_upd_cmp_d :std_ulogic; +signal congr_cl_rel1_rel_upd_cmp_q :std_ulogic; +signal ex3_no_lru_upd_d :std_ulogic; +signal ex3_no_lru_upd_q :std_ulogic; +signal ex3_l1hit :std_ulogic; +signal rel2_wayA_val :std_ulogic; +signal rel2_wayB_val :std_ulogic; +signal rel2_wayC_val :std_ulogic; +signal rel2_wayD_val :std_ulogic; +signal rel2_wayE_val :std_ulogic; +signal rel2_wayF_val :std_ulogic; +signal rel2_wayG_val :std_ulogic; +signal rel2_wayH_val :std_ulogic; +signal congr_cl_full :std_ulogic; +signal empty_way :std_ulogic_vector(0 to 7); +signal full_way :std_ulogic_vector(0 to 7); +signal rel_hit :std_ulogic_vector(0 to 7); +signal rel_upd_congr_cl_d :std_ulogic_vector(3 to 7); +signal rel_upd_congr_cl_q :std_ulogic_vector(3 to 7); +signal congr_cl_ex3_byp :std_ulogic_vector(0 to 4); +signal congr_cl_ex3_sel :std_ulogic_vector(1 to 4); +signal congr_cl_rel1_ex4_m :std_ulogic; +signal congr_cl_rel1_ex5_m :std_ulogic; +signal congr_cl_rel1_p0_m :std_ulogic; +signal congr_cl_rel1_rel2_m :std_ulogic; +signal congr_cl_rel1_relu_m :std_ulogic; +signal congr_cl_rel1_p1_m :std_ulogic; +signal rel_lru_early_sel :std_ulogic_vector(0 to 6); +signal rel_lru_early_sel_b :std_ulogic_vector(0 to 6); +signal congr_cl_rel1_byp :std_ulogic_vector(0 to 5); +signal congr_cl_rel1_sel :std_ulogic_vector(1 to 5); +signal rel_way_qsel_d :std_ulogic_vector(0 to 7); +signal rel_way_qsel_q :std_ulogic_vector(0 to 7); +signal rel_tag_d :std_ulogic_vector(0 to 2); +signal rel_tag_q :std_ulogic_vector(0 to 2); +signal rel4_val_d :std_ulogic; +signal rel4_val_q :std_ulogic; +signal rel4_retry_val_d :std_ulogic; +signal rel4_retry_val_q :std_ulogic; +signal rel_wayA_upd :std_ulogic; +signal rel_wayB_upd :std_ulogic; +signal rel_wayC_upd :std_ulogic; +signal rel_wayD_upd :std_ulogic; +signal rel_wayE_upd :std_ulogic; +signal rel_wayF_upd :std_ulogic; +signal rel_wayG_upd :std_ulogic; +signal rel_wayH_upd :std_ulogic; +signal rel_wayA_set :std_ulogic; +signal rel_wayB_set :std_ulogic; +signal rel_wayC_set :std_ulogic; +signal rel_wayD_set :std_ulogic; +signal rel_wayE_set :std_ulogic; +signal rel_wayF_set :std_ulogic; +signal rel_wayG_set :std_ulogic; +signal rel_wayH_set :std_ulogic; +signal rel_wayA_mid :std_ulogic; +signal rel_wayB_mid :std_ulogic; +signal rel_wayC_mid :std_ulogic; +signal rel_wayD_mid :std_ulogic; +signal rel_wayE_mid :std_ulogic; +signal rel_wayF_mid :std_ulogic; +signal rel_wayG_mid :std_ulogic; +signal rel_wayH_mid :std_ulogic; +signal rel1_wlock_b :std_ulogic_vector(0 to 7); +signal rel2_wlock_d :std_ulogic_vector(0 to 7); +signal rel2_wlock_q :std_ulogic_vector(0 to 7); +signal rel2_wayA_lock :std_ulogic; +signal rel2_wayB_lock :std_ulogic; +signal rel2_wayC_lock :std_ulogic; +signal rel2_wayD_lock :std_ulogic; +signal rel2_wayE_lock :std_ulogic; +signal rel2_wayF_lock :std_ulogic; +signal rel2_wayG_lock :std_ulogic; +signal rel2_wayH_lock :std_ulogic; +signal rel_lock_line :std_ulogic_vector(0 to 7); +signal rel_ovrd_lru :std_ulogic_vector(0 to 6); +signal rel_ovrd_wayAB :std_ulogic_vector(0 to 1); +signal rel_ovrd_wayCD :std_ulogic_vector(0 to 1); +signal rel_ovrd_wayEF :std_ulogic_vector(0 to 1); +signal rel_ovrd_wayGH :std_ulogic_vector(0 to 1); +signal rel_ovrd_wayABCD :std_ulogic_vector(0 to 1); +signal rel_ovrd_wayEFGH :std_ulogic_vector(0 to 1); +signal rel_ovrd_wayABCDEFGH :std_ulogic_vector(0 to 1); +signal ovr_lock_det :std_ulogic; +signal ovr_lock_det_wlkon :std_ulogic; +signal ovr_lock_det_wlkoff :std_ulogic; +signal wayA_not_empty :std_ulogic; +signal wayB_not_empty :std_ulogic; +signal wayC_not_empty :std_ulogic; +signal wayD_not_empty :std_ulogic; +signal wayE_not_empty :std_ulogic; +signal wayF_not_empty :std_ulogic; +signal wayg_not_empty :std_ulogic; +signal wayH_not_empty :std_ulogic; +signal rel_way_not_empty_d :std_ulogic_vector(0 to 7); +signal rel_way_not_empty_q :std_ulogic_vector(0 to 7); +signal reld_q0_chk_val :std_ulogic; +signal reld_q0_chk_way :std_ulogic_vector(0 to 7); +signal reld_q0_way_m :std_ulogic; +signal reld_q0_set :std_ulogic; +signal reld_q0_inval :std_ulogic; +signal reld_q0_val_sel :std_ulogic_vector(0 to 1); +signal reld_q0_congr_cl_d :std_ulogic_vector(3 to 7); +signal reld_q0_congr_cl_q :std_ulogic_vector(3 to 7); +signal reld_q0_way_d :std_ulogic_vector(0 to 7); +signal reld_q0_way_q :std_ulogic_vector(0 to 7); +signal reld_q0_val_d :std_ulogic; +signal reld_q0_val_q :std_ulogic; +signal reld_q0_lock_d :std_ulogic; +signal reld_q0_lock_q :std_ulogic; +signal rel_m_q0 :std_ulogic; +signal reld_q1_chk_val :std_ulogic; +signal reld_q1_chk_way :std_ulogic_vector(0 to 7); +signal reld_q1_way_m :std_ulogic; +signal reld_q1_set :std_ulogic; +signal reld_q1_inval :std_ulogic; +signal reld_q1_val_sel :std_ulogic_vector(0 to 1); +signal reld_q1_congr_cl_d :std_ulogic_vector(3 to 7); +signal reld_q1_congr_cl_q :std_ulogic_vector(3 to 7); +signal reld_q1_way_d :std_ulogic_vector(0 to 7); +signal reld_q1_way_q :std_ulogic_vector(0 to 7); +signal reld_q1_val_d :std_ulogic; +signal reld_q1_val_q :std_ulogic; +signal reld_q1_lock_d :std_ulogic; +signal reld_q1_lock_q :std_ulogic; +signal rel_m_q1 :std_ulogic; +signal reld_q2_chk_val :std_ulogic; +signal reld_q2_chk_way :std_ulogic_vector(0 to 7); +signal reld_q2_way_m :std_ulogic; +signal reld_q2_set :std_ulogic; +signal reld_q2_inval :std_ulogic; +signal reld_q2_val_sel :std_ulogic_vector(0 to 1); +signal reld_q2_congr_cl_d :std_ulogic_vector(3 to 7); +signal reld_q2_congr_cl_q :std_ulogic_vector(3 to 7); +signal reld_q2_way_d :std_ulogic_vector(0 to 7); +signal reld_q2_way_q :std_ulogic_vector(0 to 7); +signal reld_q2_val_d :std_ulogic; +signal reld_q2_val_q :std_ulogic; +signal reld_q2_lock_d :std_ulogic; +signal reld_q2_lock_q :std_ulogic; +signal rel_m_q2 :std_ulogic; +signal reld_q3_chk_val :std_ulogic; +signal reld_q3_chk_way :std_ulogic_vector(0 to 7); +signal reld_q3_way_m :std_ulogic; +signal reld_q3_set :std_ulogic; +signal reld_q3_inval :std_ulogic; +signal reld_q3_val_sel :std_ulogic_vector(0 to 1); +signal reld_q3_congr_cl_d :std_ulogic_vector(3 to 7); +signal reld_q3_congr_cl_q :std_ulogic_vector(3 to 7); +signal reld_q3_way_d :std_ulogic_vector(0 to 7); +signal reld_q3_way_q :std_ulogic_vector(0 to 7); +signal reld_q3_val_d :std_ulogic; +signal reld_q3_val_q :std_ulogic; +signal reld_q3_lock_d :std_ulogic; +signal reld_q3_lock_q :std_ulogic; +signal rel_m_q3 :std_ulogic; +signal reld_q4_chk_val :std_ulogic; +signal reld_q4_chk_way :std_ulogic_vector(0 to 7); +signal reld_q4_way_m :std_ulogic; +signal reld_q4_set :std_ulogic; +signal reld_q4_inval :std_ulogic; +signal reld_q4_val_sel :std_ulogic_vector(0 to 1); +signal reld_q4_congr_cl_d :std_ulogic_vector(3 to 7); +signal reld_q4_congr_cl_q :std_ulogic_vector(3 to 7); +signal reld_q4_way_d :std_ulogic_vector(0 to 7); +signal reld_q4_way_q :std_ulogic_vector(0 to 7); +signal reld_q4_val_d :std_ulogic; +signal reld_q4_val_q :std_ulogic; +signal reld_q4_lock_d :std_ulogic; +signal reld_q4_lock_q :std_ulogic; +signal rel_m_q4 :std_ulogic; +signal reld_q5_chk_val :std_ulogic; +signal reld_q5_chk_way :std_ulogic_vector(0 to 7); +signal reld_q5_way_m :std_ulogic; +signal reld_q5_set :std_ulogic; +signal reld_q5_inval :std_ulogic; +signal reld_q5_val_sel :std_ulogic_vector(0 to 1); +signal reld_q5_congr_cl_d :std_ulogic_vector(3 to 7); +signal reld_q5_congr_cl_q :std_ulogic_vector(3 to 7); +signal reld_q5_way_d :std_ulogic_vector(0 to 7); +signal reld_q5_way_q :std_ulogic_vector(0 to 7); +signal reld_q5_val_d :std_ulogic; +signal reld_q5_val_q :std_ulogic; +signal reld_q5_lock_d :std_ulogic; +signal reld_q5_lock_q :std_ulogic; +signal rel_m_q5 :std_ulogic; +signal reld_q6_chk_val :std_ulogic; +signal reld_q6_chk_way :std_ulogic_vector(0 to 7); +signal reld_q6_way_m :std_ulogic; +signal reld_q6_set :std_ulogic; +signal reld_q6_inval :std_ulogic; +signal reld_q6_val_sel :std_ulogic_vector(0 to 1); +signal reld_q6_congr_cl_d :std_ulogic_vector(3 to 7); +signal reld_q6_congr_cl_q :std_ulogic_vector(3 to 7); +signal reld_q6_way_d :std_ulogic_vector(0 to 7); +signal reld_q6_way_q :std_ulogic_vector(0 to 7); +signal reld_q6_val_d :std_ulogic; +signal reld_q6_val_q :std_ulogic; +signal reld_q6_lock_d :std_ulogic; +signal reld_q6_lock_q :std_ulogic; +signal rel_m_q6 :std_ulogic; +signal reld_q7_chk_val :std_ulogic; +signal reld_q7_chk_way :std_ulogic_vector(0 to 7); +signal reld_q7_way_m :std_ulogic; +signal reld_q7_set :std_ulogic; +signal reld_q7_inval :std_ulogic; +signal reld_q7_val_sel :std_ulogic_vector(0 to 1); +signal reld_q7_congr_cl_d :std_ulogic_vector(3 to 7); +signal reld_q7_congr_cl_q :std_ulogic_vector(3 to 7); +signal reld_q7_way_d :std_ulogic_vector(0 to 7); +signal reld_q7_way_q :std_ulogic_vector(0 to 7); +signal reld_q7_val_d :std_ulogic; +signal reld_q7_val_q :std_ulogic; +signal reld_q7_lock_d :std_ulogic; +signal reld_q7_lock_q :std_ulogic; +signal rel_m_q7 :std_ulogic; +signal reld_match :std_ulogic_vector(0 to 7); +signal reld_q_sel_d :std_ulogic_vector(0 to 7); +signal reld_q_sel_q :std_ulogic_vector(0 to 7); +signal rel_val_qsel_d :std_ulogic; +signal rel_val_qsel_q :std_ulogic; +signal spr_rmt_table :std_ulogic_vector(0 to 31); +signal rel_class_id :std_ulogic_vector(0 to 1); +signal rel2_class_id_d :std_ulogic_vector(0 to 1); +signal rel2_class_id_q :std_ulogic_vector(0 to 1); +signal rel_m_q_way_b :std_ulogic_vector(0 to 7); +signal rel_m_q_way_d :std_ulogic_vector(0 to 7); +signal rel_m_q_way_q :std_ulogic_vector(0 to 7); +signal rel_m_q_lock_way :std_ulogic_vector(0 to 7); +signal rel2_lock_en_d :std_ulogic; +signal rel2_lock_en_q :std_ulogic; +signal xucr0_clo_d :std_ulogic; +signal xucr0_clo_q :std_ulogic; +signal rel_way_dwen :std_ulogic_vector(0 to 7); +signal rel24_way_dwen_stg_d :std_ulogic_vector(0 to 7); +signal rel24_way_dwen_stg_q :std_ulogic_vector(0 to 7); +signal rel_up_way_addr_d :std_ulogic_vector(0 to 2); +signal rel_up_way_addr_q :std_ulogic_vector(0 to 2); +signal rel_dcarr_addr_en_d :std_ulogic; +signal rel_dcarr_addr_en_q :std_ulogic; +signal rel_dcarr_val_upd_d :std_ulogic; +signal rel_dcarr_val_upd_q :std_ulogic; +signal rel_lru_late_sel :std_ulogic; +signal rel_lru_late_stg_pri :std_ulogic_vector(0 to 6); +signal rel_lru_late_stg_arr :std_ulogic_vector(0 to 6); +signal lru_late_sel :std_ulogic; +signal lru_late_stg_pri :std_ulogic_vector(0 to 6); +signal lru_late_stg_arr :std_ulogic_vector(0 to 6); +signal lru_early_sel :std_ulogic_vector(0 to 6); +signal lru_early_sel_b :std_ulogic_vector(0 to 6); +signal rel_hit_lru_upd :std_ulogic_vector(0 to 6); +signal ldst_hit_vec_sel :std_ulogic; +signal ldst_hit_lru_upd :std_ulogic_vector(0 to 6); +signal rel_wlock_rmt :std_ulogic_vector(0 to 7); +signal congr_cl_act_d :std_ulogic; +signal congr_cl_act_q :std_ulogic; +signal rel2_mid_val_d :std_ulogic; +signal rel2_mid_val_q :std_ulogic; +signal relq_m_way_val :std_ulogic_vector(0 to 7); +signal rel_m_q_upd :std_ulogic; +signal rel_m_q_upd_way :std_ulogic_vector(0 to 7); +signal rel_m_q_upd_lock_way :std_ulogic_vector(0 to 7); +signal reld_q_early_sel :std_ulogic_vector(0 to 7); +signal rel_way_early_qsel :std_ulogic_vector(0 to 7); +signal rel_way_early_qsel_d :std_ulogic_vector(0 to 7); +signal rel_way_early_qsel_q :std_ulogic_vector(0 to 7); +signal rel_val_early_qsel :std_ulogic; +signal rel_val_early_qsel_d :std_ulogic; +signal rel_val_early_qsel_q :std_ulogic; +signal reld_q_early_byp :std_ulogic; +signal reld_way_early_byp :std_ulogic_vector(0 to 7); +signal reld_q_val :std_ulogic_vector(0 to 7); +signal ex4_fxubyp_val_d :std_ulogic; +signal ex4_fxubyp_val_q :std_ulogic; +signal ex4_relbyp_val_d :std_ulogic; +signal ex4_relbyp_val_q :std_ulogic; +signal ex4_lru_byp_sel :std_ulogic_vector(0 to 1); +signal rel2_fxubyp_val_d :std_ulogic; +signal rel2_fxubyp_val_q :std_ulogic; +signal rel2_relbyp_val_d :std_ulogic; +signal rel2_relbyp_val_q :std_ulogic; +signal rel2_lru_byp_sel :std_ulogic_vector(0 to 1); +signal tiup :std_ulogic; +signal siv :std_ulogic_vector(0 to scan_right); +signal sov :std_ulogic_vector(0 to scan_right); + BEGIN --@@ START OF EXECUTABLE CODE FOR XUQ_LSU_DIR_LRU16 + +-- #################################################### +-- Inputs +-- #################################################### +tiup <= '1'; +rel2_val_d <= rel1_val; +rel2_mid_val_d <= rel_mid_val; +rel4_retry_val_d <= rel_retry_val; +rel4_val_d <= rel3_val; +rel_tag_d <= rel_st_tag; +rel_class_id <= rel1_classid; +rel2_class_id_d <= rel_class_id; +rel2_lock_en_d <= rel_lock_en; +rel2_wayA_val <= rel_way_val_a; +rel2_wayB_val <= rel_way_val_b; +rel2_wayC_val <= rel_way_val_c; +rel2_wayD_val <= rel_way_val_d; +rel2_wayE_val <= rel_way_val_e; +rel2_wayF_val <= rel_way_val_f; +rel2_wayG_val <= rel_way_val_g; +rel2_wayH_val <= rel_way_val_h; +rel2_wayA_lock <= rel_way_lock_a; +rel2_wayB_lock <= rel_way_lock_b; +rel2_wayC_lock <= rel_way_lock_c; +rel2_wayD_lock <= rel_way_lock_d; +rel2_wayE_lock <= rel_way_lock_e; +rel2_wayF_lock <= rel_way_lock_f; +rel2_wayG_lock <= rel_way_lock_g; +rel2_wayH_lock <= rel_way_lock_h; +spr_rmt_table <= spr_xucr2_rmt; +ldst_wayA_hit <= ex4_way_a_hit; +ldst_wayB_hit <= ex4_way_b_hit; +ldst_wayC_hit <= ex4_way_c_hit; +ldst_wayD_hit <= ex4_way_d_hit; +ldst_wayE_hit <= ex4_way_e_hit; +ldst_wayF_hit <= ex4_way_f_hit; +ldst_wayG_hit <= ex4_way_g_hit; +ldst_wayH_hit <= ex4_way_h_hit; +ex3_l1hit <= ex3_hit; +ex3_no_lru_upd_d <= ex2_no_lru_upd; +ex3_flush <= ex3_stg_flush; +ex4_flush <= ex4_stg_flush; +ex5_flush <= ex5_stg_flush; +-- #################################################### +-- Dcache Number of Cachelines Configurations +-- #################################################### +ex1_congr_cl <= ex1_p_addr; +cl64size : if (cl_size=6) generate +begin + rel_early_congr_cl(3 TO 6) <= rel_addr_early(64-(dc_size-3) to 63-cl_size-1); +rel_early_congr_cl(7) <= rel_addr_early(63-cl_size) or spr_xucr0_cls; +end generate cl64size; +cl32size : if (cl_size=5) generate +begin + rel_early_congr_cl(3 TO 5) <= rel_addr_early(64-(dc_size-3) to 63-cl_size-2); +rel_early_congr_cl(6) <= rel_addr_early(63-cl_size-1) or spr_xucr0_cls; +rel_early_congr_cl(7) <= rel_addr_early(63-cl_size); +end generate cl32size; +rel_congr_cl_d <= rel_early_congr_cl; +ex2_congr_cl_d <= ex1_congr_cl; +ex3_congr_cl_d <= ex2_congr_cl_q; +ex4_congr_cl_d <= ex3_congr_cl_q; +ex5_congr_cl_d <= ex4_congr_cl_q; +ex6_congr_cl_d <= ex5_congr_cl_q; +-- #################################################### +-- Select Reload Congruence Class LRU +-- #################################################### +with rel_congr_cl_q select + rel_congr_cl_lru <= + congr_cl0_lru_q when "00000", + congr_cl1_lru_q when "00001", + congr_cl2_lru_q when "00010", + congr_cl3_lru_q when "00011", + congr_cl4_lru_q when "00100", + congr_cl5_lru_q when "00101", + congr_cl6_lru_q when "00110", + congr_cl7_lru_q when "00111", + congr_cl8_lru_q when "01000", + congr_cl9_lru_q when "01001", + congr_cl10_lru_q when "01010", + congr_cl11_lru_q when "01011", + congr_cl12_lru_q when "01100", + congr_cl13_lru_q when "01101", + congr_cl14_lru_q when "01110", + congr_cl15_lru_q when "01111", + congr_cl16_lru_q when "10000", + congr_cl17_lru_q when "10001", + congr_cl18_lru_q when "10010", + congr_cl19_lru_q when "10011", + congr_cl20_lru_q when "10100", + congr_cl21_lru_q when "10101", + congr_cl22_lru_q when "10110", + congr_cl23_lru_q when "10111", + congr_cl24_lru_q when "11000", + congr_cl25_lru_q when "11001", + congr_cl26_lru_q when "11010", + congr_cl27_lru_q when "11011", + congr_cl28_lru_q when "11100", + congr_cl29_lru_q when "11101", + congr_cl30_lru_q when "11110", + congr_cl31_lru_q when others; +p1_arr_lru_rd <= rel_congr_cl_lru; +-- REL1 Stage --> Bypass out of reload Queue +-- Need to merge outstanding reloads to same congruence class +-- Reload updating a way +rel_m_q_upd <= (rel_congr_cl_q = rel_congr_cl_stg_q) and rel2_val_q; +rel_m_q_upd_way <= gate(rel_hit_vec, rel_m_q_upd); +rel_m_q_upd_lock_way <= gate(rel_hit_vec, (rel_m_q_upd and rel2_lock_en_q)); +rel_m_q0 <= (rel_congr_cl_q = reld_q0_congr_cl_q) and reld_q0_val_q; +rel_m_q1 <= (rel_congr_cl_q = reld_q1_congr_cl_q) and reld_q1_val_q; +rel_m_q2 <= (rel_congr_cl_q = reld_q2_congr_cl_q) and reld_q2_val_q; +rel_m_q3 <= (rel_congr_cl_q = reld_q3_congr_cl_q) and reld_q3_val_q; +rel_m_q4 <= (rel_congr_cl_q = reld_q4_congr_cl_q) and reld_q4_val_q; +rel_m_q5 <= (rel_congr_cl_q = reld_q5_congr_cl_q) and reld_q5_val_q; +rel_m_q6 <= (rel_congr_cl_q = reld_q6_congr_cl_q) and reld_q6_val_q; +rel_m_q7 <= (rel_congr_cl_q = reld_q7_congr_cl_q) and reld_q7_val_q; +relq_m_way_val <= gate(reld_q0_way_q, rel_m_q0) or + gate(reld_q1_way_q, rel_m_q1) or + gate(reld_q2_way_q, rel_m_q2) or + gate(reld_q3_way_q, rel_m_q3) or + gate(reld_q4_way_q, rel_m_q4) or + gate(reld_q5_way_q, rel_m_q5) or + gate(reld_q6_way_q, rel_m_q6) or + gate(reld_q7_way_q, rel_m_q7); +relMQWayB: rel_m_q_way_b <= not (relq_m_way_val or rel_m_q_upd_way); +rel_m_q_way_d <= not rel_m_q_way_b; +rel_m_q_lock_way <= gate(gate(reld_q0_way_q, reld_q0_lock_q), rel_m_q0) or + gate(gate(reld_q1_way_q, reld_q1_lock_q), rel_m_q1) or + gate(gate(reld_q2_way_q, reld_q2_lock_q), rel_m_q2) or + gate(gate(reld_q3_way_q, reld_q3_lock_q), rel_m_q3) or + gate(gate(reld_q4_way_q, reld_q4_lock_q), rel_m_q4) or + gate(gate(reld_q5_way_q, reld_q5_lock_q), rel_m_q5) or + gate(gate(reld_q6_way_q, reld_q6_lock_q), rel_m_q6) or + gate(gate(reld_q7_way_q, reld_q7_lock_q), rel_m_q7) or + rel_wlock_rmt; +-- REL0 Stage --> Congruence Class Match +congr_cl_rel1_ex4_cmp_d <= (rel_early_congr_cl = ex3_congr_cl_q); +congr_cl_rel1_ex5_cmp_d <= (rel_early_congr_cl = ex4_congr_cl_q); +congr_cl_rel1_ex6_cmp_d <= (rel_early_congr_cl = ex5_congr_cl_q); +congr_cl_rel1_rel2_cmp_d <= (rel_early_congr_cl = rel_congr_cl_q); +congr_cl_rel1_relu_cmp_d <= (rel_early_congr_cl = rel_congr_cl_stg_q); +congr_cl_rel1_rel_upd_cmp_d <= (rel_early_congr_cl = relu_congr_cl_q); +-- REL1 Stage --> Bypass Logic +congr_cl_rel1_ex4_m <= congr_cl_rel1_ex4_cmp_q and ex4_c_acc; +congr_cl_rel1_ex5_m <= congr_cl_rel1_ex5_cmp_q and ex5_c_acc_q; +congr_cl_rel1_rel2_m <= congr_cl_rel1_rel2_cmp_q and rel2_val_q and not ovr_lock_det; +congr_cl_rel1_relu_m <= congr_cl_rel1_relu_cmp_q and relu_val_wen_q; +congr_cl_rel1_p0_m <= congr_cl_rel1_ex6_cmp_q and ex6_c_acc_val_q; +congr_cl_rel1_p1_m <= congr_cl_rel1_rel_upd_cmp_q and rel_val_wen_q; +-- Bypass REL1 select +congr_cl_rel1_byp(0) <= congr_cl_rel1_rel2_m; +congr_cl_rel1_byp(1) <= congr_cl_rel1_ex4_m; +congr_cl_rel1_byp(2) <= congr_cl_rel1_relu_m; +congr_cl_rel1_byp(3) <= congr_cl_rel1_ex5_m; +congr_cl_rel1_byp(4) <= congr_cl_rel1_p1_m; +congr_cl_rel1_byp(5) <= congr_cl_rel1_p0_m; +-- Bypass Pipe Valid +rel2_fxubyp_val_d <= congr_cl_rel1_byp(1) or congr_cl_rel1_byp(3) or congr_cl_rel1_byp(5); +rel2_relbyp_val_d <= congr_cl_rel1_byp(0) or congr_cl_rel1_byp(2) or congr_cl_rel1_byp(4); +rel2_lru_byp_sel <= rel2_fxubyp_val_q & rel2_relbyp_val_q; +congr_cl_rel1_sel(1) <= congr_cl_rel1_byp(1); +congr_cl_rel1_sel(2) <= congr_cl_rel1_byp(2) and not congr_cl_rel1_byp(1); +congr_cl_rel1_sel(3) <= congr_cl_rel1_byp(3) and not or_reduce(congr_cl_rel1_byp(1 to 2)); +congr_cl_rel1_sel(4) <= congr_cl_rel1_byp(4) and not or_reduce(congr_cl_rel1_byp(1 to 3)); +congr_cl_rel1_sel(5) <= congr_cl_rel1_byp(5) and not or_reduce(congr_cl_rel1_byp(1 to 4)); +-- Late Stage Priority Selection +rel_lru_late_sel <= or_reduce(congr_cl_rel1_byp(1 to 5)); +rel_lru_late_stg_pri <= gate(lru_upd, congr_cl_rel1_sel(1)) or + gate(relu_lru_upd_q, congr_cl_rel1_sel(2)) or + gate(ex5_lru_upd_q, congr_cl_rel1_sel(3)) or + gate(rel_lru_val_q, congr_cl_rel1_sel(4)) or + gate(ex6_lru_upd_q, congr_cl_rel1_sel(5)); +rel_lru_late_stg_arr <= gate(p1_arr_lru_rd, not rel_lru_late_sel) or rel_lru_late_stg_pri; +-- EX3/RELU/LATE Stage Priority Selection +rel_lru_early_sel <= (others=>congr_cl_rel1_byp(0)); +rel_lru_early_sel_b <= (others=>(not congr_cl_rel1_byp(0))); +-- Bypassed LRU for Reloads +rel_op_lru <= not rel_congr_cl_lru_b_q; +rel_congr_cl_stg_d <= rel_congr_cl_q; +relu_congr_cl_d <= rel_congr_cl_stg_q; +rel_upd_congr_cl_d <= relu_congr_cl_q; +relu_val_wen_d <= rel2_val_q and not ovr_lock_det; +rel_val_wen_d <= relu_val_wen_q; +rel_dcarr_addr_en_d <= rel2_val_q or (rel4_val_q and not rel4_retry_val_q) or rel2_mid_val_q; +-- #################################################### +-- Reload Path +-- #################################################### +-- Select which RMT table to use +with rel_class_id select + rel_wlock_rmt <= not spr_rmt_table(0 to 7) when "11", + not spr_rmt_table(8 to 15) when "10", + not spr_rmt_table(16 to 23) when "01", + not spr_rmt_table(24 to 31) when others; +rel1WlockB: rel1_wlock_b <= not (rel_m_q_upd_lock_way or rel_m_q_lock_way); +rel2_wlock_d <= not rel1_wlock_b; +-- Determine which way is locked +rel_lock_line(0) <= rel2_wayA_lock or rel2_wlock_q(0); +rel_lock_line(1) <= rel2_wayB_lock or rel2_wlock_q(1); +rel_lock_line(2) <= rel2_wayC_lock or rel2_wlock_q(2); +rel_lock_line(3) <= rel2_wayD_lock or rel2_wlock_q(3); +rel_lock_line(4) <= rel2_wayE_lock or rel2_wlock_q(4); +rel_lock_line(5) <= rel2_wayF_lock or rel2_wlock_q(5); +rel_lock_line(6) <= rel2_wayG_lock or rel2_wlock_q(6); +rel_lock_line(7) <= rel2_wayH_lock or rel2_wlock_q(7); +-- Override LRU, removing locked ways from replacement +-- Overlocking Detected, do not update Cache +ovr_lock_det <= rel_lock_line(0) and rel_lock_line(1) and rel_lock_line(2) and rel_lock_line(3) and + rel_lock_line(4) and rel_lock_line(5) and rel_lock_line(6) and rel_lock_line(7); +ovr_lock_det_wlkon <= ovr_lock_det and rel2_val_q; +ovr_lock_det_wlkoff <= ovr_lock_det and rel2_lock_en_q and rel2_val_q; +with spr_xucr0_wlck select + xucr0_clo_d <= ovr_lock_det_wlkon when '1', + ovr_lock_det_wlkoff when others; +-- LRU(0) +rel_ovrd_wayABCDEFGH <= (rel_lock_line(0) and rel_lock_line(1) and rel_lock_line(2) and rel_lock_line(3)) & + (rel_lock_line(4) and rel_lock_line(5) and rel_lock_line(6) and rel_lock_line(7)); +rel_ovrd_lru(0) <= (rel_op_lru(0) and not rel_ovrd_wayABCDEFGH(1)) or rel_ovrd_wayABCDEFGH(0); +-- LRU(1) +rel_ovrd_wayABCD <= (rel_lock_line(0) and rel_lock_line(1)) & (rel_lock_line(2) and rel_lock_line(3)); +rel_ovrd_lru(1) <= (rel_op_lru(1) and not rel_ovrd_wayABCD(1)) or rel_ovrd_wayABCD(0); +-- LRU(2) +rel_ovrd_wayEFGH <= (rel_lock_line(4) and rel_lock_line(5)) & (rel_lock_line(6) and rel_lock_line(7)); +rel_ovrd_lru(2) <= (rel_op_lru(2) and not rel_ovrd_wayEFGH(1)) or rel_ovrd_wayEFGH(0); +-- LRU(3) +rel_ovrd_wayAB <= rel_lock_line(0 to 1); +rel_ovrd_lru(3) <= (rel_op_lru(3) and not rel_ovrd_wayAB(1)) or rel_ovrd_wayAB(0); +-- LRU(4) +rel_ovrd_wayCD <= rel_lock_line(2 to 3); +rel_ovrd_lru(4) <= (rel_op_lru(4) and not rel_ovrd_wayCD(1)) or rel_ovrd_wayCD(0); +-- LRU(5) +rel_ovrd_wayEF <= rel_lock_line(4 to 5); +rel_ovrd_lru(5) <= (rel_op_lru(5) and not rel_ovrd_wayEF(1)) or rel_ovrd_wayEF(0); +-- LRU(6) +rel_ovrd_wayGH <= rel_lock_line(6 to 7); +rel_ovrd_lru(6) <= (rel_op_lru(6) and not rel_ovrd_wayGH(1)) or rel_ovrd_wayGH(0); +-- Using LRU to determine which way will be updated +full_way(0) <= not rel_ovrd_lru(0) and not rel_ovrd_lru(1) and not rel_ovrd_lru(3); +full_way(1) <= not rel_ovrd_lru(0) and not rel_ovrd_lru(1) and rel_ovrd_lru(3); +full_way(2) <= not rel_ovrd_lru(0) and rel_ovrd_lru(1) and not rel_ovrd_lru(4); +full_way(3) <= not rel_ovrd_lru(0) and rel_ovrd_lru(1) and rel_ovrd_lru(4); +full_way(4) <= rel_ovrd_lru(0) and not rel_ovrd_lru(2) and not rel_ovrd_lru(5); +full_way(5) <= rel_ovrd_lru(0) and not rel_ovrd_lru(2) and rel_ovrd_lru(5); +full_way(6) <= rel_ovrd_lru(0) and rel_ovrd_lru(2) and not rel_ovrd_lru(6); +full_way(7) <= rel_ovrd_lru(0) and rel_ovrd_lru(2) and rel_ovrd_lru(6); +--?TABLE tbl_rel_lru LISTING(final) OPTIMIZE PARMS(OFF-SET); +--*INPUTS*====================*OUTPUTS*==========* +--| | | +--| rel_lock_line | | +--| | rel_op_lru | full_way | +--| | | | | | +--| | | | | | +--| 01234567 0123456 | 01234567 | +--*TYPE*======================+==================+ +--| ........ ....... | ........ | +--*PHASE*-------------------->| CCCCCCCC | +--*TERMS*=====================+==================+ +--| 0....... 00.0... | 10000000 | WayA -- no locks +--| .0...... 00.1... | 01000000 | WayB +--| ..0..... 01..0.. | 00100000 | WayC +--| ...0.... 01..1.. | 00010000 | WayD +--| ....0... 1.0..0. | 00001000 | WayE +--| .....0.. 1.0..1. | 00000100 | WayF +--| ......0. 1.1...0 | 00000010 | WayG +--| .......0 1.1...1 | 00000001 | WayH +--| 10...... 00..... | 01000000 | WayB -- 1 lock +--| 01...... 00..... | 10000000 | WayA +--| ..10.... 01..... | 00010000 | WayD +--| ..01.... 01..... | 00100000 | WayC +--| ....10.. 1.0.... | 00000100 | WayF +--| ....01.. 1.0.... | 00001000 | WayE +--| ......10 1.1.... | 00000001 | WayH +--| ......01 1.1.... | 00000010 | WayG +--| 110..... 00..0.. | 00100000 | WayC -- 2 locks +--| 11.0.... 00..1.. | 00010000 | WayD +--| 0.11.... 01.0... | 10000000 | WayA +--| .011.... 01.1... | 01000000 | WayB +--| ....110. 1.0...0 | 00000010 | WayG +--| ....11.0 1.0...1 | 00000001 | WayH +--| ....0.11 1.1..0. | 00001000 | WayE +--| .....011 1.1..1. | 00000100 | WayF +--| 1110.... 00..... | 00010000 | WayD -- 3 locks +--| 1101.... 00..... | 00100000 | WayC +--| 1011.... 01..... | 01000000 | WayB +--| 0111.... 01..... | 10000000 | WayA +--| ....1110 1.0.... | 00000001 | WayH +--| ....1101 1.0.... | 00000010 | WayG +--| ....1011 1.1.... | 00000100 | WayF +--| ....0111 1.1.... | 00001000 | WayE +--| 11110... ..0..0. | 00001000 | WayE -- 4 locks +--| 1111.0.. ..0..1. | 00000100 | WayF +--| 1111..0. ..1...0 | 00000010 | WayG +--| 1111...0 ..1...1 | 00000001 | WayH +--| 0...1111 .0.0... | 10000000 | WayA +--| .0..1111 .0.1... | 01000000 | WayB +--| ..0.1111 .1..0.. | 00100000 | WayC +--| ...01111 .1..1.. | 00010000 | WayD +--| 111110.. ..0.... | 00000100 | WayF -- 5 locks +--| 111101.. ..0.... | 00001000 | WayE +--| 1111..10 ..1.... | 00000001 | WayH +--| 1111..01 ..1.... | 00000010 | WayG +--| 10..1111 .0..... | 01000000 | WayB +--| 01..1111 .0..... | 10000000 | WayA +--| ..101111 .1..... | 00010000 | WayD +--| ..011111 .1..... | 00100000 | WayC +--| 1111110. ......0 | 00000010 | WayG -- 6 locks +--| 111111.0 ......1 | 00000001 | WayH +--| 11110.11 .....0. | 00001000 | WayE +--| 1111.011 .....1. | 00000100 | WayF +--| 110.1111 ....0.. | 00100000 | WayC +--| 11.01111 ....1.. | 00010000 | WayD +--| 0.111111 ...0... | 10000000 | WayA +--| .0111111 ...1... | 01000000 | WayB +--| 11111101 ....... | 00000010 | WayG -- 7 locks +--| 11111110 ....... | 00000001 | WayH +--| 11110111 ....... | 00001000 | WayE +--| 11111011 ....... | 00000100 | WayF +--| 11011111 ....... | 00100000 | WayC +--| 11101111 ....... | 00010000 | WayD +--| 01111111 ....... | 10000000 | WayA +--| 10111111 ....... | 01000000 | WayB +--*END*=======================+==================+ +--?TABLE END tbl_rel_lru ; +-- Not Empty way is a valid Way or locked way or reload way in queue +wayA_not_empty <= rel2_wayA_val or rel2_wlock_q(0) or rel_m_q_way_q(0); +wayB_not_empty <= rel2_wayB_val or rel2_wlock_q(1) or rel_m_q_way_q(1); +wayC_not_empty <= rel2_wayC_val or rel2_wlock_q(2) or rel_m_q_way_q(2); +wayD_not_empty <= rel2_wayD_val or rel2_wlock_q(3) or rel_m_q_way_q(3); +wayE_not_empty <= rel2_wayE_val or rel2_wlock_q(4) or rel_m_q_way_q(4); +wayF_not_empty <= rel2_wayF_val or rel2_wlock_q(5) or rel_m_q_way_q(5); +wayG_not_empty <= rel2_wayG_val or rel2_wlock_q(6) or rel_m_q_way_q(6); +wayH_not_empty <= rel2_wayH_val or rel2_wlock_q(7) or rel_m_q_way_q(7); +rel_way_not_empty_d <= wayA_not_empty & wayB_not_empty & wayC_not_empty & wayD_not_empty & + wayE_not_empty & wayF_not_empty & wayG_not_empty & wayH_not_empty; +-- Pseudo LRU needs to be used if all ways contain valid data +congr_cl_full <= wayA_not_empty and wayB_not_empty and wayC_not_empty and wayD_not_empty and + wayE_not_empty and wayF_not_empty and wayG_not_empty and wayH_not_empty; +-- Need to select which non-valid way needs updating, Using leftmost empty Way +empty_way(0) <= not wayA_not_empty; +empty_way(1) <= ( wayA_not_empty and not wayB_not_empty); +empty_way(2) <= ( wayA_not_empty and wayB_not_empty and not wayC_not_empty); +empty_way(3) <= ( wayA_not_empty and wayB_not_empty and wayC_not_empty and not wayD_not_empty); +empty_way(4) <= ( wayA_not_empty and wayB_not_empty and wayC_not_empty and wayD_not_empty and + not wayE_not_empty); +empty_way(5) <= ( wayA_not_empty and wayB_not_empty and wayC_not_empty and wayD_not_empty and + wayE_not_empty and not wayF_not_empty); +empty_way(6) <= ( wayA_not_empty and wayB_not_empty and wayC_not_empty and wayD_not_empty and + wayE_not_empty and wayF_not_empty and not wayG_not_empty); +empty_way(7) <= ( wayA_not_empty and wayB_not_empty and wayC_not_empty and wayD_not_empty and + wayE_not_empty and wayF_not_empty and wayG_not_empty); +-- Selecting between using LRU or Fill in the Empty Ways +rel_hit <= gate(empty_way, not congr_cl_full) or gate(full_way, congr_cl_full); +-- Way that will be updating is determined by the current LRU +-- Dont want to update the directory or the D$ if we have all ways locked in the same congruence class +rel_wayA_clr <= rel_hit(0) and rel2_val_q and not ovr_lock_det; +rel_wayB_clr <= rel_hit(1) and rel2_val_q and not ovr_lock_det; +rel_wayC_clr <= rel_hit(2) and rel2_val_q and not ovr_lock_det; +rel_wayD_clr <= rel_hit(3) and rel2_val_q and not ovr_lock_det; +rel_wayE_clr <= rel_hit(4) and rel2_val_q and not ovr_lock_det; +rel_wayF_clr <= rel_hit(5) and rel2_val_q and not ovr_lock_det; +rel_wayG_clr <= rel_hit(6) and rel2_val_q and not ovr_lock_det; +rel_wayH_clr <= rel_hit(7) and rel2_val_q and not ovr_lock_det; +rel_hit_vec <= rel_wayA_clr & rel_wayB_clr & rel_wayC_clr & rel_wayD_clr & + rel_wayE_clr & rel_wayF_clr & rel_wayG_clr & rel_wayH_clr; +-- #################################################### +-- LRU update calculation due to a Reload +-- #################################################### +-- Locking Enabled +-- Updating the LRU using the Way that is being reloaded as the Way hit +rel_hit_wayA_upd <= "11" & rel_ovrd_lru(2) & "1" & rel_ovrd_lru(4 to 6); +rel_hit_wayB_upd <= "11" & rel_ovrd_lru(2) & "0" & rel_ovrd_lru(4 to 6); +rel_hit_wayC_upd <= "10" & rel_ovrd_lru(2 to 3) & "1" & rel_ovrd_lru(5 to 6); +rel_hit_wayD_upd <= "10" & rel_ovrd_lru(2 to 3) & "0" & rel_ovrd_lru(5 to 6); +rel_hit_wayE_upd <= "0" & rel_ovrd_lru(1) & "1" & rel_ovrd_lru(3 to 4) & "1" & rel_ovrd_lru(6); +rel_hit_wayF_upd <= "0" & rel_ovrd_lru(1) & "1" & rel_ovrd_lru(3 to 4) & "0" & rel_ovrd_lru(6); +rel_hit_wayG_upd <= "0" & rel_ovrd_lru(1) & "0" & rel_ovrd_lru(3 to 5) & "1"; +rel_hit_wayh_upd <= "0" & rel_ovrd_lru(1) & "0" & rel_ovrd_lru(3 to 5) & "0"; +-- #################################################### +-- Selecting which calculated LRU to update with +-- #################################################### +-- Selecting Way Hit Updated LRU +rel_hit_lru_upd <= gate(rel_hit_wayA_upd, rel_hit_vec(0)) or gate(rel_hit_wayB_upd, rel_hit_vec(1)) or + gate(rel_hit_wayC_upd, rel_hit_vec(2)) or gate(rel_hit_wayD_upd, rel_hit_vec(3)) or + gate(rel_hit_wayE_upd, rel_hit_vec(4)) or gate(rel_hit_wayF_upd, rel_hit_vec(5)) or + gate(rel_hit_wayG_upd, rel_hit_vec(6)) or gate(rel_hit_wayH_upd, rel_hit_vec(7)); +relu_lru_upd_d <= rel_hit_lru_upd; +rel_lru_val_d <= relu_lru_upd_q; +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Small Reload Way Enable Queue to Handle Beats with Gaps +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Write Enable Logic for Reload Q0 +reld_q0_chk_val <= (reld_q0_congr_cl_q = rel_congr_cl_stg_q) and reld_q0_val_q and rel2_val_q and not ovr_lock_det; +reld_q0_chk_way <= gate(reld_q0_way_q, reld_q0_chk_val); +reld_q0_way_m <= or_reduce((reld_q0_chk_way and rel_hit)); +reld_match(0) <= reld_q0_way_m; +reld_q0_set <= rel2_val_q and (rel_tag_q = tconv(0,3)); +reld_q0_inval <= (rel4_val_q and (not rel4_recirc_val or rel4_ecc_err) and reld_q_sel_q(0)) or reld_match(0); +reld_q0_val_sel <= reld_q0_set & reld_q0_inval; +-- Congruence Class +with reld_q0_set select + reld_q0_congr_cl_d <= rel_congr_cl_stg_q when '1', + reld_q0_congr_cl_q when others; +-- Reload Way +with reld_q0_set select + reld_q0_way_d <= rel_hit_vec when '1', + reld_q0_way_q when others; +-- Valid +with reld_q0_val_sel select + reld_q0_val_d <= '0' when "01", + reld_q0_val_q when "00", + '1' when others; +reld_q_val(0) <= reld_q0_val_q; +-- Lock Bit +with reld_q0_val_sel select + reld_q0_lock_d <= '0' when "01", + reld_q0_lock_q when "00", + rel2_lock_en_q when others; +-- Reload Queue Early Select +reld_q_early_sel(0) <= (rel_st_tag_early = tconv(0,3)); +-- Reload Queue Select +reld_q_sel_d(0) <= (rel_st_tag = tconv(0,3)); +-- Write Enable Logic for Reload Q1 +reld_q1_chk_val <= (reld_q1_congr_cl_q = rel_congr_cl_stg_q) and reld_q1_val_q and rel2_val_q and not ovr_lock_det; +reld_q1_chk_way <= gate(reld_q1_way_q, reld_q1_chk_val); +reld_q1_way_m <= or_reduce((reld_q1_chk_way and rel_hit)); +reld_match(1) <= reld_q1_way_m; +reld_q1_set <= rel2_val_q and (rel_tag_q = tconv(1,3)); +reld_q1_inval <= (rel4_val_q and (not rel4_recirc_val or rel4_ecc_err) and reld_q_sel_q(1)) or reld_match(1); +reld_q1_val_sel <= reld_q1_set & reld_q1_inval; +-- Congruence Class +with reld_q1_set select + reld_q1_congr_cl_d <= rel_congr_cl_stg_q when '1', + reld_q1_congr_cl_q when others; +-- Reload Way +with reld_q1_set select + reld_q1_way_d <= rel_hit_vec when '1', + reld_q1_way_q when others; +-- Valid +with reld_q1_val_sel select + reld_q1_val_d <= '0' when "01", + reld_q1_val_q when "00", + '1' when others; +reld_q_val(1) <= reld_q1_val_q; +-- Lock Bit +with reld_q1_val_sel select + reld_q1_lock_d <= '0' when "01", + reld_q1_lock_q when "00", + rel2_lock_en_q when others; +-- Reload Queue Early Select +reld_q_early_sel(1) <= (rel_st_tag_early = tconv(1,3)); +-- Reload Queue Select +reld_q_sel_d(1) <= (rel_st_tag = tconv(1,3)); +-- Write Enable Logic for Reload Q2 +reld_q2_chk_val <= (reld_q2_congr_cl_q = rel_congr_cl_stg_q) and reld_q2_val_q and rel2_val_q and not ovr_lock_det; +reld_q2_chk_way <= gate(reld_q2_way_q, reld_q2_chk_val); +reld_q2_way_m <= or_reduce((reld_q2_chk_way and rel_hit)); +reld_match(2) <= reld_q2_way_m; +reld_q2_set <= rel2_val_q and (rel_tag_q = tconv(2,3)); +reld_q2_inval <= (rel4_val_q and (not rel4_recirc_val or rel4_ecc_err) and reld_q_sel_q(2)) or reld_match(2); +reld_q2_val_sel <= reld_q2_set & reld_q2_inval; +-- Congruence Class +with reld_q2_set select + reld_q2_congr_cl_d <= rel_congr_cl_stg_q when '1', + reld_q2_congr_cl_q when others; +-- Reload Way +with reld_q2_set select + reld_q2_way_d <= rel_hit_vec when '1', + reld_q2_way_q when others; +-- Valid +with reld_q2_val_sel select + reld_q2_val_d <= '0' when "01", + reld_q2_val_q when "00", + '1' when others; +reld_q_val(2) <= reld_q2_val_q; +-- Lock Bit +with reld_q2_val_sel select + reld_q2_lock_d <= '0' when "01", + reld_q2_lock_q when "00", + rel2_lock_en_q when others; +-- Reload Queue Early Select +reld_q_early_sel(2) <= (rel_st_tag_early = tconv(2,3)); +-- Reload Queue Select +reld_q_sel_d(2) <= (rel_st_tag = tconv(2,3)); +-- Write Enable Logic for Reload Q3 +reld_q3_chk_val <= (reld_q3_congr_cl_q = rel_congr_cl_stg_q) and reld_q3_val_q and rel2_val_q and not ovr_lock_det; +reld_q3_chk_way <= gate(reld_q3_way_q, reld_q3_chk_val); +reld_q3_way_m <= or_reduce((reld_q3_chk_way and rel_hit)); +reld_match(3) <= reld_q3_way_m; +reld_q3_set <= rel2_val_q and (rel_tag_q = tconv(3,3)); +reld_q3_inval <= (rel4_val_q and (not rel4_recirc_val or rel4_ecc_err) and reld_q_sel_q(3)) or reld_match(3); +reld_q3_val_sel <= reld_q3_set & reld_q3_inval; +-- Congruence Class +with reld_q3_set select + reld_q3_congr_cl_d <= rel_congr_cl_stg_q when '1', + reld_q3_congr_cl_q when others; +-- Reload Way +with reld_q3_set select + reld_q3_way_d <= rel_hit_vec when '1', + reld_q3_way_q when others; +-- Valid +with reld_q3_val_sel select + reld_q3_val_d <= '0' when "01", + reld_q3_val_q when "00", + '1' when others; +reld_q_val(3) <= reld_q3_val_q; +-- Lock Bit +with reld_q3_val_sel select + reld_q3_lock_d <= '0' when "01", + reld_q3_lock_q when "00", + rel2_lock_en_q when others; +-- Reload Queue Early Select +reld_q_early_sel(3) <= (rel_st_tag_early = tconv(3,3)); +-- Reload Queue Select +reld_q_sel_d(3) <= (rel_st_tag = tconv(3,3)); +-- Write Enable Logic for Reload Q4 +reld_q4_chk_val <= (reld_q4_congr_cl_q = rel_congr_cl_stg_q) and reld_q4_val_q and rel2_val_q and not ovr_lock_det; +reld_q4_chk_way <= gate(reld_q4_way_q, reld_q4_chk_val); +reld_q4_way_m <= or_reduce((reld_q4_chk_way and rel_hit)); +reld_match(4) <= reld_q4_way_m; +reld_q4_set <= rel2_val_q and (rel_tag_q = tconv(4,3)); +reld_q4_inval <= (rel4_val_q and (not rel4_recirc_val or rel4_ecc_err) and reld_q_sel_q(4)) or reld_match(4); +reld_q4_val_sel <= reld_q4_set & reld_q4_inval; +-- Congruence Class +with reld_q4_set select + reld_q4_congr_cl_d <= rel_congr_cl_stg_q when '1', + reld_q4_congr_cl_q when others; +-- Reload Way +with reld_q4_set select + reld_q4_way_d <= rel_hit_vec when '1', + reld_q4_way_q when others; +-- Valid +with reld_q4_val_sel select + reld_q4_val_d <= '0' when "01", + reld_q4_val_q when "00", + '1' when others; +reld_q_val(4) <= reld_q4_val_q; +-- Lock Bit +with reld_q4_val_sel select + reld_q4_lock_d <= '0' when "01", + reld_q4_lock_q when "00", + rel2_lock_en_q when others; +-- Reload Queue Early Select +reld_q_early_sel(4) <= (rel_st_tag_early = tconv(4,3)); +-- Reload Queue Select +reld_q_sel_d(4) <= (rel_st_tag = tconv(4,3)); +-- Write Enable Logic for Reload Q5 +reld_q5_chk_val <= (reld_q5_congr_cl_q = rel_congr_cl_stg_q) and reld_q5_val_q and rel2_val_q and not ovr_lock_det; +reld_q5_chk_way <= gate(reld_q5_way_q, reld_q5_chk_val); +reld_q5_way_m <= or_reduce((reld_q5_chk_way and rel_hit)); +reld_match(5) <= reld_q5_way_m; +reld_q5_set <= rel2_val_q and (rel_tag_q = tconv(5,3)); +reld_q5_inval <= (rel4_val_q and (not rel4_recirc_val or rel4_ecc_err) and reld_q_sel_q(5)) or reld_match(5); +reld_q5_val_sel <= reld_q5_set & reld_q5_inval; +-- Congruence Class +with reld_q5_set select + reld_q5_congr_cl_d <= rel_congr_cl_stg_q when '1', + reld_q5_congr_cl_q when others; +-- Reload Way +with reld_q5_set select + reld_q5_way_d <= rel_hit_vec when '1', + reld_q5_way_q when others; +-- Valid +with reld_q5_val_sel select + reld_q5_val_d <= '0' when "01", + reld_q5_val_q when "00", + '1' when others; +reld_q_val(5) <= reld_q5_val_q; +-- Lock Bit +with reld_q5_val_sel select + reld_q5_lock_d <= '0' when "01", + reld_q5_lock_q when "00", + rel2_lock_en_q when others; +-- Reload Queue Early Select +reld_q_early_sel(5) <= (rel_st_tag_early = tconv(5,3)); +-- Reload Queue Select +reld_q_sel_d(5) <= (rel_st_tag = tconv(5,3)); +-- Write Enable Logic for Reload Q6 +reld_q6_chk_val <= (reld_q6_congr_cl_q = rel_congr_cl_stg_q) and reld_q6_val_q and rel2_val_q and not ovr_lock_det; +reld_q6_chk_way <= gate(reld_q6_way_q, reld_q6_chk_val); +reld_q6_way_m <= or_reduce((reld_q6_chk_way and rel_hit)); +reld_match(6) <= reld_q6_way_m; +reld_q6_set <= rel2_val_q and (rel_tag_q = tconv(6,3)); +reld_q6_inval <= (rel4_val_q and (not rel4_recirc_val or rel4_ecc_err) and reld_q_sel_q(6)) or reld_match(6); +reld_q6_val_sel <= reld_q6_set & reld_q6_inval; +-- Congruence Class +with reld_q6_set select + reld_q6_congr_cl_d <= rel_congr_cl_stg_q when '1', + reld_q6_congr_cl_q when others; +-- Reload Way +with reld_q6_set select + reld_q6_way_d <= rel_hit_vec when '1', + reld_q6_way_q when others; +-- Valid +with reld_q6_val_sel select + reld_q6_val_d <= '0' when "01", + reld_q6_val_q when "00", + '1' when others; +reld_q_val(6) <= reld_q6_val_q; +-- Lock Bit +with reld_q6_val_sel select + reld_q6_lock_d <= '0' when "01", + reld_q6_lock_q when "00", + rel2_lock_en_q when others; +-- Reload Queue Early Select +reld_q_early_sel(6) <= (rel_st_tag_early = tconv(6,3)); +-- Reload Queue Select +reld_q_sel_d(6) <= (rel_st_tag = tconv(6,3)); +-- Write Enable Logic for Reload Q7 +reld_q7_chk_val <= (reld_q7_congr_cl_q = rel_congr_cl_stg_q) and reld_q7_val_q and rel2_val_q and not ovr_lock_det; +reld_q7_chk_way <= gate(reld_q7_way_q, reld_q7_chk_val); +reld_q7_way_m <= or_reduce((reld_q7_chk_way and rel_hit)); +reld_match(7) <= reld_q7_way_m; +reld_q7_set <= rel2_val_q and (rel_tag_q = tconv(7,3)); +reld_q7_inval <= (rel4_val_q and (not rel4_recirc_val or rel4_ecc_err) and reld_q_sel_q(7)) or reld_match(7); +reld_q7_val_sel <= reld_q7_set & reld_q7_inval; +-- Congruence Class +with reld_q7_set select + reld_q7_congr_cl_d <= rel_congr_cl_stg_q when '1', + reld_q7_congr_cl_q when others; +-- Reload Way +with reld_q7_set select + reld_q7_way_d <= rel_hit_vec when '1', + reld_q7_way_q when others; +-- Valid +with reld_q7_val_sel select + reld_q7_val_d <= '0' when "01", + reld_q7_val_q when "00", + '1' when others; +reld_q_val(7) <= reld_q7_val_q; +-- Lock Bit +with reld_q7_val_sel select + reld_q7_lock_d <= '0' when "01", + reld_q7_lock_q when "00", + rel2_lock_en_q when others; +-- Reload Queue Early Select +reld_q_early_sel(7) <= (rel_st_tag_early = tconv(7,3)); +-- Reload Queue Select +reld_q_sel_d(7) <= (rel_st_tag = tconv(7,3)); +-- Select Way and Valid +rel_way_early_qsel <= gate(reld_q0_way_q, reld_q_early_sel(0)) or + gate(reld_q1_way_q, reld_q_early_sel(1)) or + gate(reld_q2_way_q, reld_q_early_sel(2)) or + gate(reld_q3_way_q, reld_q_early_sel(3)) or + gate(reld_q4_way_q, reld_q_early_sel(4)) or + gate(reld_q5_way_q, reld_q_early_sel(5)) or + gate(reld_q6_way_q, reld_q_early_sel(6)) or + gate(reld_q7_way_q, reld_q_early_sel(7)); +rel_val_early_qsel <= (reld_q0_val_q and reld_q_early_sel(0)) or + (reld_q1_val_q and reld_q_early_sel(1)) or + (reld_q2_val_q and reld_q_early_sel(2)) or + (reld_q3_val_q and reld_q_early_sel(3)) or + (reld_q4_val_q and reld_q_early_sel(4)) or + (reld_q5_val_q and reld_q_early_sel(5)) or + (reld_q6_val_q and reld_q_early_sel(6)) or + (reld_q7_val_q and reld_q_early_sel(7)); +-- Small Bypass of Reload Clr update +reld_q_early_byp <= (rel_st_tag_early = rel_tag_q) and rel2_val_q; +reld_way_early_byp <= rel_hit_vec; +rel_way_early_qsel_d <= gate(rel_way_early_qsel, not reld_q_early_byp) or gate(reld_way_early_byp, reld_q_early_byp); +rel_val_early_qsel_d <= rel_val_early_qsel or reld_q_early_byp; +-- Select Way and Valid +rel_way_qsel_d <= gate(reld_q0_way_q, reld_q_sel_d(0)) or + gate(reld_q1_way_q, reld_q_sel_d(1)) or + gate(reld_q2_way_q, reld_q_sel_d(2)) or + gate(reld_q3_way_q, reld_q_sel_d(3)) or + gate(reld_q4_way_q, reld_q_sel_d(4)) or + gate(reld_q5_way_q, reld_q_sel_d(5)) or + gate(reld_q6_way_q, reld_q_sel_d(6)) or + gate(reld_q7_way_q, reld_q_sel_d(7)); +rel_val_qsel_d <= (reld_q0_val_q and reld_q_sel_d(0) and not reld_match(0)) or + (reld_q1_val_q and reld_q_sel_d(1) and not reld_match(1)) or + (reld_q2_val_q and reld_q_sel_d(2) and not reld_match(2)) or + (reld_q3_val_q and reld_q_sel_d(3) and not reld_match(3)) or + (reld_q4_val_q and reld_q_sel_d(4) and not reld_match(4)) or + (reld_q5_val_q and reld_q_sel_d(5) and not reld_match(5)) or + (reld_q6_val_q and reld_q_sel_d(6) and not reld_match(6)) or + (reld_q7_val_q and reld_q_sel_d(7) and not reld_match(7)); +-- Reload Way Upd Directory +rel_wayA_upd <= rel_way_early_qsel_q(0) and rel_val_early_qsel_q; +rel_wayB_upd <= rel_way_early_qsel_q(1) and rel_val_early_qsel_q; +rel_wayC_upd <= rel_way_early_qsel_q(2) and rel_val_early_qsel_q; +rel_wayD_upd <= rel_way_early_qsel_q(3) and rel_val_early_qsel_q; +rel_wayE_upd <= rel_way_early_qsel_q(4) and rel_val_early_qsel_q; +rel_wayF_upd <= rel_way_early_qsel_q(5) and rel_val_early_qsel_q; +rel_wayG_upd <= rel_way_early_qsel_q(6) and rel_val_early_qsel_q; +rel_wayH_upd <= rel_way_early_qsel_q(7) and rel_val_early_qsel_q; +-- Reload Way Set +rel_wayA_set <= rel_way_qsel_q(0) and rel4_val_q and rel_val_qsel_q; +rel_wayB_set <= rel_way_qsel_q(1) and rel4_val_q and rel_val_qsel_q; +rel_wayC_set <= rel_way_qsel_q(2) and rel4_val_q and rel_val_qsel_q; +rel_wayD_set <= rel_way_qsel_q(3) and rel4_val_q and rel_val_qsel_q; +rel_wayE_set <= rel_way_qsel_q(4) and rel4_val_q and rel_val_qsel_q; +rel_wayF_set <= rel_way_qsel_q(5) and rel4_val_q and rel_val_qsel_q; +rel_wayG_set <= rel_way_qsel_q(6) and rel4_val_q and rel_val_qsel_q; +rel_wayH_set <= rel_way_qsel_q(7) and rel4_val_q and rel_val_qsel_q; +-- Reload Middle Data Valid +rel_wayA_mid <= rel_way_qsel_q(0) and rel2_mid_val_q and rel_val_qsel_q; +rel_wayB_mid <= rel_way_qsel_q(1) and rel2_mid_val_q and rel_val_qsel_q; +rel_wayC_mid <= rel_way_qsel_q(2) and rel2_mid_val_q and rel_val_qsel_q; +rel_wayD_mid <= rel_way_qsel_q(3) and rel2_mid_val_q and rel_val_qsel_q; +rel_wayE_mid <= rel_way_qsel_q(4) and rel2_mid_val_q and rel_val_qsel_q; +rel_wayF_mid <= rel_way_qsel_q(5) and rel2_mid_val_q and rel_val_qsel_q; +rel_wayG_mid <= rel_way_qsel_q(6) and rel2_mid_val_q and rel_val_qsel_q; +rel_wayH_mid <= rel_way_qsel_q(7) and rel2_mid_val_q and rel_val_qsel_q; +-- #################################################### +-- Select XU Operation Congruence Class LRU +-- #################################################### +with ex3_congr_cl_q select + arr_congr_cl_lru <= + congr_cl0_lru_q when "00000", + congr_cl1_lru_q when "00001", + congr_cl2_lru_q when "00010", + congr_cl3_lru_q when "00011", + congr_cl4_lru_q when "00100", + congr_cl5_lru_q when "00101", + congr_cl6_lru_q when "00110", + congr_cl7_lru_q when "00111", + congr_cl8_lru_q when "01000", + congr_cl9_lru_q when "01001", + congr_cl10_lru_q when "01010", + congr_cl11_lru_q when "01011", + congr_cl12_lru_q when "01100", + congr_cl13_lru_q when "01101", + congr_cl14_lru_q when "01110", + congr_cl15_lru_q when "01111", + congr_cl16_lru_q when "10000", + congr_cl17_lru_q when "10001", + congr_cl18_lru_q when "10010", + congr_cl19_lru_q when "10011", + congr_cl20_lru_q when "10100", + congr_cl21_lru_q when "10101", + congr_cl22_lru_q when "10110", + congr_cl23_lru_q when "10111", + congr_cl24_lru_q when "11000", + congr_cl25_lru_q when "11001", + congr_cl26_lru_q when "11010", + congr_cl27_lru_q when "11011", + congr_cl28_lru_q when "11100", + congr_cl29_lru_q when "11101", + congr_cl30_lru_q when "11110", + congr_cl31_lru_q when others; +p0_arr_lru_rd <= arr_congr_cl_lru; +-- #################################################### +-- Execution Path +-- #################################################### +-- access is valid if its a cache_enabled op and not flushed or not a dcbt instruction +ex3_c_acc_val <= ex3_cache_en and not (ex3_no_lru_upd_q or spr_xucr0_dcdis or ex3_flush); +ex4_hit_d <= ex3_l1hit; +ex4_c_acc_d <= ex3_c_acc_val; +ex4_c_acc <= ex4_c_acc_q and ex4_hit_q; +ex4_c_acc_val <= ex4_c_acc and not ex4_flush; +ex5_c_acc_d <= ex4_c_acc_val; +ex5_c_acc_val <= ex5_c_acc_q and not ex5_flush; +ex6_c_acc_val_d <= ex5_c_acc_val; +-- EX2 Stage --> Congruence Class Match +congr_cl_ex3_ex4_cmp_d <= (ex2_congr_cl_q = ex3_congr_cl_q); +congr_cl_ex3_ex5_cmp_d <= (ex2_congr_cl_q = ex4_congr_cl_q); +congr_cl_ex3_ex6_cmp_d <= (ex2_congr_cl_q = ex5_congr_cl_q); +congr_cl_ex3_rel2_cmp_d <= (ex2_congr_cl_q = rel_congr_cl_q); +congr_cl_ex3_rel_upd_cmp_d <= (ex2_congr_cl_q = relu_congr_cl_q); +-- EX3 Stage --> Bypass Logic +congr_cl_ex3_ex4_m <= congr_cl_ex3_ex4_cmp_q and ex4_c_acc; +congr_cl_ex3_ex5_m <= congr_cl_ex3_ex5_cmp_q and ex5_c_acc_q; +congr_cl_ex3_rel2_m <= congr_cl_ex3_rel2_cmp_q and rel2_val_q and not ovr_lock_det; +congr_cl_ex3_p0_m <= congr_cl_ex3_ex6_cmp_q and ex6_c_acc_val_q; +congr_cl_ex3_p1_m <= congr_cl_ex3_rel_upd_cmp_q and rel_val_wen_q; +-- Bypass EX3 select +-- Whenever reload is in RELU stage (which is xu EX4 stage), +-- no bypass since xu op is a bubble +congr_cl_ex3_byp(0) <= congr_cl_ex3_rel2_m; +congr_cl_ex3_byp(1) <= congr_cl_ex3_ex4_m; +congr_cl_ex3_byp(2) <= congr_cl_ex3_ex5_m; +congr_cl_ex3_byp(3) <= congr_cl_ex3_p1_m; +congr_cl_ex3_byp(4) <= congr_cl_ex3_p0_m; +-- Bypass Pipe Valid +ex4_fxubyp_val_d <= congr_cl_ex3_byp(1) or congr_cl_ex3_byp(2) or congr_cl_ex3_byp(4); +ex4_relbyp_val_d <= congr_cl_ex3_byp(0) or congr_cl_ex3_byp(3); +ex4_lru_byp_sel <= ex4_fxubyp_val_q & ex4_relbyp_val_q; +congr_cl_ex3_sel(1) <= congr_cl_ex3_byp(1); +congr_cl_ex3_sel(2) <= congr_cl_ex3_byp(2) and not congr_cl_ex3_byp(1); +congr_cl_ex3_sel(3) <= congr_cl_ex3_byp(3) and not or_reduce(congr_cl_ex3_byp(1 to 2)); +congr_cl_ex3_sel(4) <= congr_cl_ex3_byp(4) and not or_reduce(congr_cl_ex3_byp(1 to 3)); +-- Late Stage Priority Selection +lru_late_sel <= or_reduce(congr_cl_ex3_byp(1 to 4)); +lru_late_stg_pri <= gate(lru_upd, congr_cl_ex3_sel(1)) or + gate(ex5_lru_upd_q, congr_cl_ex3_sel(2)) or + gate(rel_lru_val_q, congr_cl_ex3_sel(3)) or + gate(ex6_lru_upd_q, congr_cl_ex3_sel(4)); +lru_late_stg_arr <= gate(p0_arr_lru_rd, not lru_late_sel) or lru_late_stg_pri; +-- EX3/RELU/LATE Stage Priority Selection +lru_early_sel <= (others=>congr_cl_ex3_byp(0)); +lru_early_sel_b <= (others=>(not congr_cl_ex3_byp(0))); +-- Bypassed LRU for Execution Pipe +xu_op_lru <= not congr_cl_lru_b_q; +ldst_hit_vector <= ldst_wayA_hit & ldst_wayB_hit & ldst_wayC_hit & ldst_wayD_hit & + ldst_wayE_hit & ldst_wayF_hit & ldst_wayG_hit & ldst_wayH_hit; +-- #################################################### +-- LRU update calculation due to an XU op +-- #################################################### +-- Updating the LRU using the Way that is being reloaded as the Way hit +hit_wayA_upd <= "11" & xu_op_lru(2) & "1" & xu_op_lru(4 to 6); +hit_wayB_upd <= "11" & xu_op_lru(2) & "0" & xu_op_lru(4 to 6); +hit_wayC_upd <= "10" & xu_op_lru(2 to 3) & "1" & xu_op_lru(5 to 6); +hit_wayD_upd <= "10" & xu_op_lru(2 to 3) & "0" & xu_op_lru(5 to 6); +hit_wayE_upd <= "0" & xu_op_lru(1) & "1" & xu_op_lru(3 to 4) & "1" & xu_op_lru(6); +hit_wayF_upd <= "0" & xu_op_lru(1) & "1" & xu_op_lru(3 to 4) & "0" & xu_op_lru(6); +hit_wayG_upd <= "0" & xu_op_lru(1) & "0" & xu_op_lru(3 to 5) & "1"; +hit_wayh_upd <= "0" & xu_op_lru(1) & "0" & xu_op_lru(3 to 5) & "0"; +-- #################################################### +-- Selecting between Execution Pipe +-- #################################################### +-- Selecting Way Hit Updated LRU +ldst_hit_vec_sel <= or_reduce(ldst_hit_vector); +ldst_hit_lru_upd <= gate(hit_wayA_upd, ldst_hit_vector(0)) or gate(hit_wayB_upd, ldst_hit_vector(1)) or + gate(hit_wayC_upd, ldst_hit_vector(2)) or gate(hit_wayD_upd, ldst_hit_vector(3)) or + gate(hit_wayE_upd, ldst_hit_vector(4)) or gate(hit_wayF_upd, ldst_hit_vector(5)) or + gate(hit_wayG_upd, ldst_hit_vector(6)) or gate(hit_wayH_upd, ldst_hit_vector(7)); +with ldst_hit_vec_sel select + lru_upd <= ldst_hit_lru_upd when '1', + xu_op_lru when others; +ex5_lru_upd_d <= lru_upd; +ex6_lru_upd_d <= ex5_lru_upd_q; +-- #################################################### +-- Upper Address Caculation +-- #################################################### +-- Reload Address Calculation +rel_way_dwen <= (rel_wayA_clr or rel_wayA_set or rel_wayA_mid) & (rel_wayB_clr or rel_wayB_set or rel_wayB_mid) & + (rel_wayC_clr or rel_wayC_set or rel_wayC_mid) & (rel_wayD_clr or rel_wayD_set or rel_wayD_mid) & + (rel_wayE_clr or rel_wayE_set or rel_wayE_mid) & (rel_wayF_clr or rel_wayF_set or rel_wayF_mid) & + (rel_wayG_clr or rel_wayG_set or rel_wayG_mid) & (rel_wayH_clr or rel_wayH_set or rel_wayH_mid); +-- Reload is updating either directory or data cache +rel24_way_dwen_stg_d <= rel_way_dwen; +rel_dcarr_val_upd_d <= or_reduce(rel_way_dwen) and not rel4_retry_val_q; +rel_up_way_addr_d <= gate("001", rel_way_dwen(1)) or + gate("010", rel_way_dwen(2)) or gate("011", rel_way_dwen(3)) or + gate("100", rel_way_dwen(4)) or gate("101", rel_way_dwen(5)) or + gate("110", rel_way_dwen(6)) or gate("111", rel_way_dwen(7)); +-- DCARR upper address select +rel_up_way_addr_b <= not rel_up_way_addr_q; +rel_dcarr_addr_en <= rel_dcarr_addr_en_q; +-- #################################################### +-- Directory LRU write enable generations +-- #################################################### +-- Congruence Class Update Act +congr_cl_act_d <= ex5_c_acc_q or relu_val_wen_q; +-- Write on a Reload or on an EX4 XU operation +xu_op_cl0_lru_wen <= (ex6_congr_cl_q = tconv(0,5)) and ex6_c_acc_val_q; +rel_cl0_lru_wen <= (rel_upd_congr_cl_q = tconv(0,5)) and rel_val_wen_q; +congr_cl0_lru_wen <= xu_op_cl0_lru_wen or rel_cl0_lru_wen; +-- Selecting LRU update +with rel_cl0_lru_wen select + rel_ldst_cl0_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl0_lru_wen select + congr_cl0_lru_d <= rel_ldst_cl0_lru when '1', + congr_cl0_lru_q when others; +xu_op_cl1_lru_wen <= (ex6_congr_cl_q = tconv(1,5)) and ex6_c_acc_val_q; +rel_cl1_lru_wen <= (rel_upd_congr_cl_q = tconv(1,5)) and rel_val_wen_q; +congr_cl1_lru_wen <= xu_op_cl1_lru_wen or rel_cl1_lru_wen; +-- Selecting LRU update +with rel_cl1_lru_wen select + rel_ldst_cl1_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl1_lru_wen select + congr_cl1_lru_d <= rel_ldst_cl1_lru when '1', + congr_cl1_lru_q when others; +xu_op_cl2_lru_wen <= (ex6_congr_cl_q = tconv(2,5)) and ex6_c_acc_val_q; +rel_cl2_lru_wen <= (rel_upd_congr_cl_q = tconv(2,5)) and rel_val_wen_q; +congr_cl2_lru_wen <= xu_op_cl2_lru_wen or rel_cl2_lru_wen; +-- Selecting LRU update +with rel_cl2_lru_wen select + rel_ldst_cl2_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl2_lru_wen select + congr_cl2_lru_d <= rel_ldst_cl2_lru when '1', + congr_cl2_lru_q when others; +xu_op_cl3_lru_wen <= (ex6_congr_cl_q = tconv(3,5)) and ex6_c_acc_val_q; +rel_cl3_lru_wen <= (rel_upd_congr_cl_q = tconv(3,5)) and rel_val_wen_q; +congr_cl3_lru_wen <= xu_op_cl3_lru_wen or rel_cl3_lru_wen; +with rel_cl3_lru_wen select + rel_ldst_cl3_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl3_lru_wen select + congr_cl3_lru_d <= rel_ldst_cl3_lru when '1', + congr_cl3_lru_q when others; +xu_op_cl4_lru_wen <= (ex6_congr_cl_q = tconv(4,5)) and ex6_c_acc_val_q; +rel_cl4_lru_wen <= (rel_upd_congr_cl_q = tconv(4,5)) and rel_val_wen_q; +congr_cl4_lru_wen <= xu_op_cl4_lru_wen or rel_cl4_lru_wen; +-- Selecting LRU update +with rel_cl4_lru_wen select + rel_ldst_cl4_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl4_lru_wen select + congr_cl4_lru_d <= rel_ldst_cl4_lru when '1', + congr_cl4_lru_q when others; +xu_op_cl5_lru_wen <= (ex6_congr_cl_q = tconv(5,5)) and ex6_c_acc_val_q; +rel_cl5_lru_wen <= (rel_upd_congr_cl_q = tconv(5,5)) and rel_val_wen_q; +congr_cl5_lru_wen <= xu_op_cl5_lru_wen or rel_cl5_lru_wen; +-- Selecting LRU update +with rel_cl5_lru_wen select + rel_ldst_cl5_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl5_lru_wen select + congr_cl5_lru_d <= rel_ldst_cl5_lru when '1', + congr_cl5_lru_q when others; +xu_op_cl6_lru_wen <= (ex6_congr_cl_q = tconv(6,5)) and ex6_c_acc_val_q; +rel_cl6_lru_wen <= (rel_upd_congr_cl_q = tconv(6,5)) and rel_val_wen_q; +congr_cl6_lru_wen <= xu_op_cl6_lru_wen or rel_cl6_lru_wen; +-- Selecting LRU update +with rel_cl6_lru_wen select + rel_ldst_cl6_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl6_lru_wen select + congr_cl6_lru_d <= rel_ldst_cl6_lru when '1', + congr_cl6_lru_q when others; +xu_op_cl7_lru_wen <= (ex6_congr_cl_q = tconv(7,5)) and ex6_c_acc_val_q; +rel_cl7_lru_wen <= (rel_upd_congr_cl_q = tconv(7,5)) and rel_val_wen_q; +congr_cl7_lru_wen <= xu_op_cl7_lru_wen or rel_cl7_lru_wen; +-- Selecting LRU update +with rel_cl7_lru_wen select + rel_ldst_cl7_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl7_lru_wen select + congr_cl7_lru_d <= rel_ldst_cl7_lru when '1', + congr_cl7_lru_q when others; +xu_op_cl8_lru_wen <= (ex6_congr_cl_q = tconv(8,5)) and ex6_c_acc_val_q; +rel_cl8_lru_wen <= (rel_upd_congr_cl_q = tconv(8,5)) and rel_val_wen_q; +congr_cl8_lru_wen <= xu_op_cl8_lru_wen or rel_cl8_lru_wen; +-- Selecting LRU update +with rel_cl8_lru_wen select + rel_ldst_cl8_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl8_lru_wen select + congr_cl8_lru_d <= rel_ldst_cl8_lru when '1', + congr_cl8_lru_q when others; +xu_op_cl9_lru_wen <= (ex6_congr_cl_q = tconv(9,5)) and ex6_c_acc_val_q; +rel_cl9_lru_wen <= (rel_upd_congr_cl_q = tconv(9,5)) and rel_val_wen_q; +congr_cl9_lru_wen <= xu_op_cl9_lru_wen or rel_cl9_lru_wen; +-- Selecting LRU update +with rel_cl9_lru_wen select + rel_ldst_cl9_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl9_lru_wen select + congr_cl9_lru_d <= rel_ldst_cl9_lru when '1', + congr_cl9_lru_q when others; +xu_op_cl10_lru_wen <= (ex6_congr_cl_q = tconv(10,5)) and ex6_c_acc_val_q; +rel_cl10_lru_wen <= (rel_upd_congr_cl_q = tconv(10,5)) and rel_val_wen_q; +congr_cl10_lru_wen <= xu_op_cl10_lru_wen or rel_cl10_lru_wen; +-- Selecting LRU update +with rel_cl10_lru_wen select + rel_ldst_cl10_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl10_lru_wen select + congr_cl10_lru_d <= rel_ldst_cl10_lru when '1', + congr_cl10_lru_q when others; +xu_op_cl11_lru_wen <= (ex6_congr_cl_q = tconv(11,5)) and ex6_c_acc_val_q; +rel_cl11_lru_wen <= (rel_upd_congr_cl_q = tconv(11,5)) and rel_val_wen_q; +congr_cl11_lru_wen <= xu_op_cl11_lru_wen or rel_cl11_lru_wen; +-- Selecting LRU update +with rel_cl11_lru_wen select + rel_ldst_cl11_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl11_lru_wen select + congr_cl11_lru_d <= rel_ldst_cl11_lru when '1', + congr_cl11_lru_q when others; +xu_op_cl12_lru_wen <= (ex6_congr_cl_q = tconv(12,5)) and ex6_c_acc_val_q; +rel_cl12_lru_wen <= (rel_upd_congr_cl_q = tconv(12,5)) and rel_val_wen_q; +congr_cl12_lru_wen <= xu_op_cl12_lru_wen or rel_cl12_lru_wen; +-- Selecting LRU update +with rel_cl12_lru_wen select + rel_ldst_cl12_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl12_lru_wen select + congr_cl12_lru_d <= rel_ldst_cl12_lru when '1', + congr_cl12_lru_q when others; +xu_op_cl13_lru_wen <= (ex6_congr_cl_q = tconv(13,5)) and ex6_c_acc_val_q; +rel_cl13_lru_wen <= (rel_upd_congr_cl_q = tconv(13,5)) and rel_val_wen_q; +congr_cl13_lru_wen <= xu_op_cl13_lru_wen or rel_cl13_lru_wen; +-- Selecting LRU update +with rel_cl13_lru_wen select + rel_ldst_cl13_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl13_lru_wen select + congr_cl13_lru_d <= rel_ldst_cl13_lru when '1', + congr_cl13_lru_q when others; +xu_op_cl14_lru_wen <= (ex6_congr_cl_q = tconv(14,5)) and ex6_c_acc_val_q; +rel_cl14_lru_wen <= (rel_upd_congr_cl_q = tconv(14,5)) and rel_val_wen_q; +congr_cl14_lru_wen <= xu_op_cl14_lru_wen or rel_cl14_lru_wen; +-- Selecting LRU update +with rel_cl14_lru_wen select + rel_ldst_cl14_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl14_lru_wen select + congr_cl14_lru_d <= rel_ldst_cl14_lru when '1', + congr_cl14_lru_q when others; +xu_op_cl15_lru_wen <= (ex6_congr_cl_q = tconv(15,5)) and ex6_c_acc_val_q; +rel_cl15_lru_wen <= (rel_upd_congr_cl_q = tconv(15,5)) and rel_val_wen_q; +congr_cl15_lru_wen <= xu_op_cl15_lru_wen or rel_cl15_lru_wen; +-- Selecting LRU update +with rel_cl15_lru_wen select + rel_ldst_cl15_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl15_lru_wen select + congr_cl15_lru_d <= rel_ldst_cl15_lru when '1', + congr_cl15_lru_q when others; +xu_op_cl16_lru_wen <= (ex6_congr_cl_q = tconv(16,5)) and ex6_c_acc_val_q; +rel_cl16_lru_wen <= (rel_upd_congr_cl_q = tconv(16,5)) and rel_val_wen_q; +congr_cl16_lru_wen <= xu_op_cl16_lru_wen or rel_cl16_lru_wen; +-- Selecting LRU update +with rel_cl16_lru_wen select + rel_ldst_cl16_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl16_lru_wen select + congr_cl16_lru_d <= rel_ldst_cl16_lru when '1', + congr_cl16_lru_q when others; +xu_op_cl17_lru_wen <= (ex6_congr_cl_q = tconv(17,5)) and ex6_c_acc_val_q; +rel_cl17_lru_wen <= (rel_upd_congr_cl_q = tconv(17,5)) and rel_val_wen_q; +congr_cl17_lru_wen <= xu_op_cl17_lru_wen or rel_cl17_lru_wen; +-- Selecting LRU update +with rel_cl17_lru_wen select + rel_ldst_cl17_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl17_lru_wen select + congr_cl17_lru_d <= rel_ldst_cl17_lru when '1', + congr_cl17_lru_q when others; +xu_op_cl18_lru_wen <= (ex6_congr_cl_q = tconv(18,5)) and ex6_c_acc_val_q; +rel_cl18_lru_wen <= (rel_upd_congr_cl_q = tconv(18,5)) and rel_val_wen_q; +congr_cl18_lru_wen <= xu_op_cl18_lru_wen or rel_cl18_lru_wen; +-- Selecting LRU update +with rel_cl18_lru_wen select + rel_ldst_cl18_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl18_lru_wen select + congr_cl18_lru_d <= rel_ldst_cl18_lru when '1', + congr_cl18_lru_q when others; +xu_op_cl19_lru_wen <= (ex6_congr_cl_q = tconv(19,5)) and ex6_c_acc_val_q; +rel_cl19_lru_wen <= (rel_upd_congr_cl_q = tconv(19,5)) and rel_val_wen_q; +congr_cl19_lru_wen <= xu_op_cl19_lru_wen or rel_cl19_lru_wen; +-- Selecting LRU update +with rel_cl19_lru_wen select + rel_ldst_cl19_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl19_lru_wen select + congr_cl19_lru_d <= rel_ldst_cl19_lru when '1', + congr_cl19_lru_q when others; +xu_op_cl20_lru_wen <= (ex6_congr_cl_q = tconv(20,5)) and ex6_c_acc_val_q; +rel_cl20_lru_wen <= (rel_upd_congr_cl_q = tconv(20,5)) and rel_val_wen_q; +congr_cl20_lru_wen <= xu_op_cl20_lru_wen or rel_cl20_lru_wen; +-- Selecting LRU update +with rel_cl20_lru_wen select + rel_ldst_cl20_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl20_lru_wen select + congr_cl20_lru_d <= rel_ldst_cl20_lru when '1', + congr_cl20_lru_q when others; +xu_op_cl21_lru_wen <= (ex6_congr_cl_q = tconv(21,5)) and ex6_c_acc_val_q; +rel_cl21_lru_wen <= (rel_upd_congr_cl_q = tconv(21,5)) and rel_val_wen_q; +congr_cl21_lru_wen <= xu_op_cl21_lru_wen or rel_cl21_lru_wen; +-- Selecting LRU update +with rel_cl21_lru_wen select + rel_ldst_cl21_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl21_lru_wen select + congr_cl21_lru_d <= rel_ldst_cl21_lru when '1', + congr_cl21_lru_q when others; +xu_op_cl22_lru_wen <= (ex6_congr_cl_q = tconv(22,5)) and ex6_c_acc_val_q; +rel_cl22_lru_wen <= (rel_upd_congr_cl_q = tconv(22,5)) and rel_val_wen_q; +congr_cl22_lru_wen <= xu_op_cl22_lru_wen or rel_cl22_lru_wen; +-- Selecting LRU update +with rel_cl22_lru_wen select + rel_ldst_cl22_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl22_lru_wen select + congr_cl22_lru_d <= rel_ldst_cl22_lru when '1', + congr_cl22_lru_q when others; +xu_op_cl23_lru_wen <= (ex6_congr_cl_q = tconv(23,5)) and ex6_c_acc_val_q; +rel_cl23_lru_wen <= (rel_upd_congr_cl_q = tconv(23,5)) and rel_val_wen_q; +congr_cl23_lru_wen <= xu_op_cl23_lru_wen or rel_cl23_lru_wen; +-- Selecting LRU update +with rel_cl23_lru_wen select + rel_ldst_cl23_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl23_lru_wen select + congr_cl23_lru_d <= rel_ldst_cl23_lru when '1', + congr_cl23_lru_q when others; +xu_op_cl24_lru_wen <= (ex6_congr_cl_q = tconv(24,5)) and ex6_c_acc_val_q; +rel_cl24_lru_wen <= (rel_upd_congr_cl_q = tconv(24,5)) and rel_val_wen_q; +congr_cl24_lru_wen <= xu_op_cl24_lru_wen or rel_cl24_lru_wen; +-- Selecting LRU update +with rel_cl24_lru_wen select + rel_ldst_cl24_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl24_lru_wen select + congr_cl24_lru_d <= rel_ldst_cl24_lru when '1', + congr_cl24_lru_q when others; +xu_op_cl25_lru_wen <= (ex6_congr_cl_q = tconv(25,5)) and ex6_c_acc_val_q; +rel_cl25_lru_wen <= (rel_upd_congr_cl_q = tconv(25,5)) and rel_val_wen_q; +congr_cl25_lru_wen <= xu_op_cl25_lru_wen or rel_cl25_lru_wen; +-- Selecting LRU update +with rel_cl25_lru_wen select + rel_ldst_cl25_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl25_lru_wen select + congr_cl25_lru_d <= rel_ldst_cl25_lru when '1', + congr_cl25_lru_q when others; +xu_op_cl26_lru_wen <= (ex6_congr_cl_q = tconv(26,5)) and ex6_c_acc_val_q; +rel_cl26_lru_wen <= (rel_upd_congr_cl_q = tconv(26,5)) and rel_val_wen_q; +congr_cl26_lru_wen <= xu_op_cl26_lru_wen or rel_cl26_lru_wen; +-- Selecting LRU update +with rel_cl26_lru_wen select + rel_ldst_cl26_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl26_lru_wen select + congr_cl26_lru_d <= rel_ldst_cl26_lru when '1', + congr_cl26_lru_q when others; +xu_op_cl27_lru_wen <= (ex6_congr_cl_q = tconv(27,5)) and ex6_c_acc_val_q; +rel_cl27_lru_wen <= (rel_upd_congr_cl_q = tconv(27,5)) and rel_val_wen_q; +congr_cl27_lru_wen <= xu_op_cl27_lru_wen or rel_cl27_lru_wen; +-- Selecting LRU update +with rel_cl27_lru_wen select + rel_ldst_cl27_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl27_lru_wen select + congr_cl27_lru_d <= rel_ldst_cl27_lru when '1', + congr_cl27_lru_q when others; +xu_op_cl28_lru_wen <= (ex6_congr_cl_q = tconv(28,5)) and ex6_c_acc_val_q; +rel_cl28_lru_wen <= (rel_upd_congr_cl_q = tconv(28,5)) and rel_val_wen_q; +congr_cl28_lru_wen <= xu_op_cl28_lru_wen or rel_cl28_lru_wen; +-- Selecting LRU update +with rel_cl28_lru_wen select + rel_ldst_cl28_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl28_lru_wen select + congr_cl28_lru_d <= rel_ldst_cl28_lru when '1', + congr_cl28_lru_q when others; +xu_op_cl29_lru_wen <= (ex6_congr_cl_q = tconv(29,5)) and ex6_c_acc_val_q; +rel_cl29_lru_wen <= (rel_upd_congr_cl_q = tconv(29,5)) and rel_val_wen_q; +congr_cl29_lru_wen <= xu_op_cl29_lru_wen or rel_cl29_lru_wen; +-- Selecting LRU update +with rel_cl29_lru_wen select + rel_ldst_cl29_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl29_lru_wen select + congr_cl29_lru_d <= rel_ldst_cl29_lru when '1', + congr_cl29_lru_q when others; +xu_op_cl30_lru_wen <= (ex6_congr_cl_q = tconv(30,5)) and ex6_c_acc_val_q; +rel_cl30_lru_wen <= (rel_upd_congr_cl_q = tconv(30,5)) and rel_val_wen_q; +congr_cl30_lru_wen <= xu_op_cl30_lru_wen or rel_cl30_lru_wen; +-- Selecting LRU update +with rel_cl30_lru_wen select + rel_ldst_cl30_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl30_lru_wen select + congr_cl30_lru_d <= rel_ldst_cl30_lru when '1', + congr_cl30_lru_q when others; +xu_op_cl31_lru_wen <= (ex6_congr_cl_q = tconv(31,5)) and ex6_c_acc_val_q; +rel_cl31_lru_wen <= (rel_upd_congr_cl_q = tconv(31,5)) and rel_val_wen_q; +congr_cl31_lru_wen <= xu_op_cl31_lru_wen or rel_cl31_lru_wen; +-- Selecting LRU update +with rel_cl31_lru_wen select + rel_ldst_cl31_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl31_lru_wen select + congr_cl31_lru_d <= rel_ldst_cl31_lru when '1', + congr_cl31_lru_q when others; +-- #################################################### +-- Outputs +-- #################################################### +rel_way_clr_a <= rel_wayA_clr; +rel_way_clr_b <= rel_wayB_clr; +rel_way_clr_c <= rel_wayC_clr; +rel_way_clr_d <= rel_wayD_clr; +rel_way_clr_e <= rel_wayE_clr; +rel_way_clr_f <= rel_wayF_clr; +rel_way_clr_g <= rel_wayG_clr; +rel_way_clr_h <= rel_wayH_clr; +rel_way_upd_a <= rel_wayA_upd; +rel_way_upd_b <= rel_wayB_upd; +rel_way_upd_c <= rel_wayC_upd; +rel_way_upd_d <= rel_wayD_upd; +rel_way_upd_e <= rel_wayE_upd; +rel_way_upd_f <= rel_wayF_upd; +rel_way_upd_g <= rel_wayG_upd; +rel_way_upd_h <= rel_wayH_upd; +rel_way_wen_a <= rel_wayA_set; +rel_way_wen_b <= rel_wayB_set; +rel_way_wen_c <= rel_wayC_set; +rel_way_wen_d <= rel_wayD_set; +rel_way_wen_e <= rel_wayE_set; +rel_way_wen_f <= rel_wayF_set; +rel_way_wen_g <= rel_wayG_set; +rel_way_wen_h <= rel_wayH_set; +rel_dcarr_val_upd <= rel_dcarr_val_upd_q; +lsu_xu_spr_xucr0_clo <= xucr0_clo_q; +ex4_dir_lru <= xu_op_lru; +-- Debug Data +dc_lru_dbg_data <= rel24_way_dwen_stg_q & reld_q_val & rel_m_q_way_q & rel2_wlock_q & + rel_way_not_empty_q & ex4_lru_byp_sel & rel2_lru_byp_sel & rel_val_wen_q & + rel_op_lru & rel_lru_val_q & xucr0_clo_q & xu_op_lru & + ex6_c_acc_val_q & ex6_lru_upd_q & rel2_class_id_q & rel_tag_q & + rel4_retry_val_q & ex4_c_acc; +-- #################################################### +-- Directory LRU Registers +-- #################################################### +-- Congruence Class 0 Way A Register +congr_cl0_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl0_lru_offset to congr_cl0_lru_offset + congr_cl0_lru_d'length-1), + scout => sov(congr_cl0_lru_offset to congr_cl0_lru_offset + congr_cl0_lru_d'length-1), + din => congr_cl0_lru_d, + dout => congr_cl0_lru_q); +-- Congruence Class 1 Way A Register +congr_cl1_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl1_lru_offset to congr_cl1_lru_offset + congr_cl1_lru_d'length-1), + scout => sov(congr_cl1_lru_offset to congr_cl1_lru_offset + congr_cl1_lru_d'length-1), + din => congr_cl1_lru_d, + dout => congr_cl1_lru_q); +-- Congruence Class 2 Way A Register +congr_cl2_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl2_lru_offset to congr_cl2_lru_offset + congr_cl2_lru_d'length-1), + scout => sov(congr_cl2_lru_offset to congr_cl2_lru_offset + congr_cl2_lru_d'length-1), + din => congr_cl2_lru_d, + dout => congr_cl2_lru_q); +-- Congruence Class 3 Way A Register +congr_cl3_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl3_lru_offset to congr_cl3_lru_offset + congr_cl3_lru_d'length-1), + scout => sov(congr_cl3_lru_offset to congr_cl3_lru_offset + congr_cl3_lru_d'length-1), + din => congr_cl3_lru_d, + dout => congr_cl3_lru_q); +-- Congruence Class 4 Way A Register +congr_cl4_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl4_lru_offset to congr_cl4_lru_offset + congr_cl4_lru_d'length-1), + scout => sov(congr_cl4_lru_offset to congr_cl4_lru_offset + congr_cl4_lru_d'length-1), + din => congr_cl4_lru_d, + dout => congr_cl4_lru_q); +-- Congruence Class 5 Way A Register +congr_cl5_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl5_lru_offset to congr_cl5_lru_offset + congr_cl5_lru_d'length-1), + scout => sov(congr_cl5_lru_offset to congr_cl5_lru_offset + congr_cl5_lru_d'length-1), + din => congr_cl5_lru_d, + dout => congr_cl5_lru_q); +-- Congruence Class 6 Way A Register +congr_cl6_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl6_lru_offset to congr_cl6_lru_offset + congr_cl6_lru_d'length-1), + scout => sov(congr_cl6_lru_offset to congr_cl6_lru_offset + congr_cl6_lru_d'length-1), + din => congr_cl6_lru_d, + dout => congr_cl6_lru_q); +-- Congruence Class 7 Way A Register +congr_cl7_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl7_lru_offset to congr_cl7_lru_offset + congr_cl7_lru_d'length-1), + scout => sov(congr_cl7_lru_offset to congr_cl7_lru_offset + congr_cl7_lru_d'length-1), + din => congr_cl7_lru_d, + dout => congr_cl7_lru_q); +-- Congruence Class 8 Way A Register +congr_cl8_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl8_lru_offset to congr_cl8_lru_offset + congr_cl8_lru_d'length-1), + scout => sov(congr_cl8_lru_offset to congr_cl8_lru_offset + congr_cl8_lru_d'length-1), + din => congr_cl8_lru_d, + dout => congr_cl8_lru_q); +-- Congruence Class 9 Way A Register +congr_cl9_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl9_lru_offset to congr_cl9_lru_offset + congr_cl9_lru_d'length-1), + scout => sov(congr_cl9_lru_offset to congr_cl9_lru_offset + congr_cl9_lru_d'length-1), + din => congr_cl9_lru_d, + dout => congr_cl9_lru_q); +-- Congruence Class 10 Way A Register +congr_cl10_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl10_lru_offset to congr_cl10_lru_offset + congr_cl10_lru_d'length-1), + scout => sov(congr_cl10_lru_offset to congr_cl10_lru_offset + congr_cl10_lru_d'length-1), + din => congr_cl10_lru_d, + dout => congr_cl10_lru_q); +-- Congruence Class 11 Way A Register +congr_cl11_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl11_lru_offset to congr_cl11_lru_offset + congr_cl11_lru_d'length-1), + scout => sov(congr_cl11_lru_offset to congr_cl11_lru_offset + congr_cl11_lru_d'length-1), + din => congr_cl11_lru_d, + dout => congr_cl11_lru_q); +-- Congruence Class 12 Way A Register +congr_cl12_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl12_lru_offset to congr_cl12_lru_offset + congr_cl12_lru_d'length-1), + scout => sov(congr_cl12_lru_offset to congr_cl12_lru_offset + congr_cl12_lru_d'length-1), + din => congr_cl12_lru_d, + dout => congr_cl12_lru_q); +-- Congruence Class 13 Way A Register +congr_cl13_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl13_lru_offset to congr_cl13_lru_offset + congr_cl13_lru_d'length-1), + scout => sov(congr_cl13_lru_offset to congr_cl13_lru_offset + congr_cl13_lru_d'length-1), + din => congr_cl13_lru_d, + dout => congr_cl13_lru_q); +-- Congruence Class 14 Way A Register +congr_cl14_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl14_lru_offset to congr_cl14_lru_offset + congr_cl14_lru_d'length-1), + scout => sov(congr_cl14_lru_offset to congr_cl14_lru_offset + congr_cl14_lru_d'length-1), + din => congr_cl14_lru_d, + dout => congr_cl14_lru_q); +-- Congruence Class 15 Way A Register +congr_cl15_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl15_lru_offset to congr_cl15_lru_offset + congr_cl15_lru_d'length-1), + scout => sov(congr_cl15_lru_offset to congr_cl15_lru_offset + congr_cl15_lru_d'length-1), + din => congr_cl15_lru_d, + dout => congr_cl15_lru_q); +-- Congruence Class 16 Way A Register +congr_cl16_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl16_lru_offset to congr_cl16_lru_offset + congr_cl16_lru_d'length-1), + scout => sov(congr_cl16_lru_offset to congr_cl16_lru_offset + congr_cl16_lru_d'length-1), + din => congr_cl16_lru_d, + dout => congr_cl16_lru_q); +-- Congruence Class 17 Way A Register +congr_cl17_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl17_lru_offset to congr_cl17_lru_offset + congr_cl17_lru_d'length-1), + scout => sov(congr_cl17_lru_offset to congr_cl17_lru_offset + congr_cl17_lru_d'length-1), + din => congr_cl17_lru_d, + dout => congr_cl17_lru_q); +-- Congruence Class 18 Way A Register +congr_cl18_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl18_lru_offset to congr_cl18_lru_offset + congr_cl18_lru_d'length-1), + scout => sov(congr_cl18_lru_offset to congr_cl18_lru_offset + congr_cl18_lru_d'length-1), + din => congr_cl18_lru_d, + dout => congr_cl18_lru_q); +-- Congruence Class 19 Way A Register +congr_cl19_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl19_lru_offset to congr_cl19_lru_offset + congr_cl19_lru_d'length-1), + scout => sov(congr_cl19_lru_offset to congr_cl19_lru_offset + congr_cl19_lru_d'length-1), + din => congr_cl19_lru_d, + dout => congr_cl19_lru_q); +-- Congruence Class 20 Way A Register +congr_cl20_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl20_lru_offset to congr_cl20_lru_offset + congr_cl20_lru_d'length-1), + scout => sov(congr_cl20_lru_offset to congr_cl20_lru_offset + congr_cl20_lru_d'length-1), + din => congr_cl20_lru_d, + dout => congr_cl20_lru_q); +-- Congruence Class 21 Way A Register +congr_cl21_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl21_lru_offset to congr_cl21_lru_offset + congr_cl21_lru_d'length-1), + scout => sov(congr_cl21_lru_offset to congr_cl21_lru_offset + congr_cl21_lru_d'length-1), + din => congr_cl21_lru_d, + dout => congr_cl21_lru_q); +-- Congruence Class 22 Way A Register +congr_cl22_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl22_lru_offset to congr_cl22_lru_offset + congr_cl22_lru_d'length-1), + scout => sov(congr_cl22_lru_offset to congr_cl22_lru_offset + congr_cl22_lru_d'length-1), + din => congr_cl22_lru_d, + dout => congr_cl22_lru_q); +-- Congruence Class 23 Way A Register +congr_cl23_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl23_lru_offset to congr_cl23_lru_offset + congr_cl23_lru_d'length-1), + scout => sov(congr_cl23_lru_offset to congr_cl23_lru_offset + congr_cl23_lru_d'length-1), + din => congr_cl23_lru_d, + dout => congr_cl23_lru_q); +-- Congruence Class 24 Way A Register +congr_cl24_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl24_lru_offset to congr_cl24_lru_offset + congr_cl24_lru_d'length-1), + scout => sov(congr_cl24_lru_offset to congr_cl24_lru_offset + congr_cl24_lru_d'length-1), + din => congr_cl24_lru_d, + dout => congr_cl24_lru_q); +-- Congruence Class 25 Way A Register +congr_cl25_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl25_lru_offset to congr_cl25_lru_offset + congr_cl25_lru_d'length-1), + scout => sov(congr_cl25_lru_offset to congr_cl25_lru_offset + congr_cl25_lru_d'length-1), + din => congr_cl25_lru_d, + dout => congr_cl25_lru_q); +-- Congruence Class 26 Way A Register +congr_cl26_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl26_lru_offset to congr_cl26_lru_offset + congr_cl26_lru_d'length-1), + scout => sov(congr_cl26_lru_offset to congr_cl26_lru_offset + congr_cl26_lru_d'length-1), + din => congr_cl26_lru_d, + dout => congr_cl26_lru_q); +-- Congruence Class 27 Way A Register +congr_cl27_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl27_lru_offset to congr_cl27_lru_offset + congr_cl27_lru_d'length-1), + scout => sov(congr_cl27_lru_offset to congr_cl27_lru_offset + congr_cl27_lru_d'length-1), + din => congr_cl27_lru_d, + dout => congr_cl27_lru_q); +-- Congruence Class 28 Way A Register +congr_cl28_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl28_lru_offset to congr_cl28_lru_offset + congr_cl28_lru_d'length-1), + scout => sov(congr_cl28_lru_offset to congr_cl28_lru_offset + congr_cl28_lru_d'length-1), + din => congr_cl28_lru_d, + dout => congr_cl28_lru_q); +-- Congruence Class 29 Way A Register +congr_cl29_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl29_lru_offset to congr_cl29_lru_offset + congr_cl29_lru_d'length-1), + scout => sov(congr_cl29_lru_offset to congr_cl29_lru_offset + congr_cl29_lru_d'length-1), + din => congr_cl29_lru_d, + dout => congr_cl29_lru_q); +-- Congruence Class 30 Way A Register +congr_cl30_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl30_lru_offset to congr_cl30_lru_offset + congr_cl30_lru_d'length-1), + scout => sov(congr_cl30_lru_offset to congr_cl30_lru_offset + congr_cl30_lru_d'length-1), + din => congr_cl30_lru_d, + dout => congr_cl30_lru_q); +-- Congruence Class 31 Way A Register +congr_cl31_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl31_lru_offset to congr_cl31_lru_offset + congr_cl31_lru_d'length-1), + scout => sov(congr_cl31_lru_offset to congr_cl31_lru_offset + congr_cl31_lru_d'length-1), + din => congr_cl31_lru_d, + dout => congr_cl31_lru_q); +congr_cl_lru_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_lru_b_offset to congr_cl_lru_b_offset + congr_cl_lru_b_q'length-1), + scout => sov(congr_cl_lru_b_offset to congr_cl_lru_b_offset + congr_cl_lru_b_q'length-1), + a1 => rel_hit_lru_upd, + a2 => lru_early_sel, + b1 => lru_late_stg_arr, + b2 => lru_early_sel_b, + qb => congr_cl_lru_b_q); +rel_congr_cl_lru_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_congr_cl_lru_b_offset to rel_congr_cl_lru_b_offset + rel_congr_cl_lru_b_q'length-1), + scout => sov(rel_congr_cl_lru_b_offset to rel_congr_cl_lru_b_offset + rel_congr_cl_lru_b_q'length-1), + a1 => rel_hit_lru_upd, + a2 => rel_lru_early_sel, + b1 => rel_lru_late_stg_arr, + b2 => rel_lru_early_sel_b, + qb => rel_congr_cl_lru_b_q); +reld_q_sel_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q_sel_offset to reld_q_sel_offset + reld_q_sel_d'length-1), + scout => sov(reld_q_sel_offset to reld_q_sel_offset + reld_q_sel_d'length-1), + din => reld_q_sel_d, + dout => reld_q_sel_q); +ex4_congr_cl_reg: tri_regk +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex4_congr_cl_d, + dout => ex4_congr_cl_q); +ex5_congr_cl_reg: tri_rlmreg_p +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_congr_cl_offset to ex5_congr_cl_offset + ex5_congr_cl_d'length-1), + scout => sov(ex5_congr_cl_offset to ex5_congr_cl_offset + ex5_congr_cl_d'length-1), + din => ex5_congr_cl_d, + dout => ex5_congr_cl_q); +ex6_congr_cl_reg: tri_regk +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex5_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex6_congr_cl_d, + dout => ex6_congr_cl_q); +rel_congr_cl_reg: tri_rlmreg_p +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_congr_cl_offset to rel_congr_cl_offset + rel_congr_cl_d'length-1), + scout => sov(rel_congr_cl_offset to rel_congr_cl_offset + rel_congr_cl_d'length-1), + din => rel_congr_cl_d, + dout => rel_congr_cl_q); +rel_congr_cl_stg_reg: tri_regk +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_congr_cl_stg_d, + dout => rel_congr_cl_stg_q); +relu_congr_cl_reg: tri_rlmreg_p +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(relu_congr_cl_offset to relu_congr_cl_offset + relu_congr_cl_d'length-1), + scout => sov(relu_congr_cl_offset to relu_congr_cl_offset + relu_congr_cl_d'length-1), + din => relu_congr_cl_d, + dout => relu_congr_cl_q); +ex5_lru_upd_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_lru_upd_offset to ex5_lru_upd_offset + ex5_lru_upd_d'length-1), + scout => sov(ex5_lru_upd_offset to ex5_lru_upd_offset + ex5_lru_upd_d'length-1), + din => ex5_lru_upd_d, + dout => ex5_lru_upd_q); +ex6_lru_upd_reg: tri_regk +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex5_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex6_lru_upd_d, + dout => ex6_lru_upd_q); +rel2_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel2_val_offset), + scout => sov(rel2_val_offset), + din => rel2_val_d, + dout => rel2_val_q); +rel2_class_id_reg: tri_regk +generic map (width => 2, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel2_class_id_d, + dout => rel2_class_id_q); +relu_val_wen_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(relu_val_wen_offset), + scout => sov(relu_val_wen_offset), + din => relu_val_wen_d, + dout => relu_val_wen_q); +ex4_hit_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_hit_offset), + scout => sov(ex4_hit_offset), + din => ex4_hit_d, + dout => ex4_hit_q); +ex4_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex4_fxubyp_val_d, + dout(0) => ex4_fxubyp_val_q); +ex4_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex4_relbyp_val_d, + dout(0) => ex4_relbyp_val_q); +ex4_c_acc_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_c_acc_offset), + scout => sov(ex4_c_acc_offset), + din => ex4_c_acc_d, + dout => ex4_c_acc_q); +ex5_c_acc_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_c_acc_offset), + scout => sov(ex5_c_acc_offset), + din => ex5_c_acc_d, + dout => ex5_c_acc_q); +ex6_c_acc_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_c_acc_val_offset), + scout => sov(ex6_c_acc_val_offset), + din => ex6_c_acc_val_d, + dout => ex6_c_acc_val_q); +ex2_congr_cl_reg: tri_regk +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex2_congr_cl_d, + dout => ex2_congr_cl_q); +ex3_congr_cl_reg: tri_rlmreg_p +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_congr_cl_offset to ex3_congr_cl_offset + ex3_congr_cl_d'length-1), + scout => sov(ex3_congr_cl_offset to ex3_congr_cl_offset + ex3_congr_cl_d'length-1), + din => ex3_congr_cl_d, + dout => ex3_congr_cl_q); +rel_val_wen_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_val_wen_offset), + scout => sov(rel_val_wen_offset), + din => rel_val_wen_d, + dout => rel_val_wen_q); +rel_way_not_empty_reg: tri_regk +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_way_not_empty_d, + dout => rel_way_not_empty_q); +relu_lru_upd_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(relu_lru_upd_offset to relu_lru_upd_offset + relu_lru_upd_d'length-1), + scout => sov(relu_lru_upd_offset to relu_lru_upd_offset + relu_lru_upd_d'length-1), + din => relu_lru_upd_d, + dout => relu_lru_upd_q); +rel_lru_val_reg: tri_regk +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_lru_val_d, + dout => rel_lru_val_q); +rel_upd_congr_cl_reg: tri_regk +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_upd_congr_cl_d, + dout => rel_upd_congr_cl_q); +rel_tag_reg: tri_regk +generic map (width => 3, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_tag_d, + dout => rel_tag_q); +rel_way_qsel_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_way_qsel_offset to rel_way_qsel_offset + rel_way_qsel_d'length-1), + scout => sov(rel_way_qsel_offset to rel_way_qsel_offset + rel_way_qsel_d'length-1), + din => rel_way_qsel_d, + dout => rel_way_qsel_q); +rel_val_qsel_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_val_qsel_offset), + scout => sov(rel_val_qsel_offset), + din => rel_val_qsel_d, + dout => rel_val_qsel_q); +rel_way_early_qsel_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_way_early_qsel_offset to rel_way_early_qsel_offset + rel_way_early_qsel_d'length-1), + scout => sov(rel_way_early_qsel_offset to rel_way_early_qsel_offset + rel_way_early_qsel_d'length-1), + din => rel_way_early_qsel_d, + dout => rel_way_early_qsel_q); +rel_val_early_qsel_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_val_early_qsel_offset), + scout => sov(rel_val_early_qsel_offset), + din => rel_val_early_qsel_d, + dout => rel_val_early_qsel_q); +rel4_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel4_val_offset), + scout => sov(rel4_val_offset), + din => rel4_val_d, + dout => rel4_val_q); +rel2_mid_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel2_mid_val_offset), + scout => sov(rel2_mid_val_offset), + din => rel2_mid_val_d, + dout => rel2_mid_val_q); +rel4_retry_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel4_retry_val_offset), + scout => sov(rel4_retry_val_offset), + din => rel4_retry_val_d, + dout => rel4_retry_val_q); +rel2_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel2_fxubyp_val_d, + dout(0) => rel2_fxubyp_val_q); +rel2_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel2_relbyp_val_d, + dout(0) => rel2_relbyp_val_q); +rel2_wlock_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel2_wlock_offset to rel2_wlock_offset + rel2_wlock_d'length-1), + scout => sov(rel2_wlock_offset to rel2_wlock_offset + rel2_wlock_d'length-1), + din => rel2_wlock_d, + dout => rel2_wlock_q); +reld_q0_congr_cl_reg: tri_rlmreg_p +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q0_congr_cl_offset to reld_q0_congr_cl_offset + reld_q0_congr_cl_d'length-1), + scout => sov(reld_q0_congr_cl_offset to reld_q0_congr_cl_offset + reld_q0_congr_cl_d'length-1), + din => reld_q0_congr_cl_d, + dout => reld_q0_congr_cl_q); +reld_q0_way_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q0_way_offset to reld_q0_way_offset + reld_q0_way_d'length-1), + scout => sov(reld_q0_way_offset to reld_q0_way_offset + reld_q0_way_d'length-1), + din => reld_q0_way_d, + dout => reld_q0_way_q); +reld_q0_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q0_val_offset), + scout => sov(reld_q0_val_offset), + din => reld_q0_val_d, + dout => reld_q0_val_q); +reld_q0_lock_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q0_lock_offset), + scout => sov(reld_q0_lock_offset), + din => reld_q0_lock_d, + dout => reld_q0_lock_q); +reld_q1_congr_cl_reg: tri_rlmreg_p +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q1_congr_cl_offset to reld_q1_congr_cl_offset + reld_q1_congr_cl_d'length-1), + scout => sov(reld_q1_congr_cl_offset to reld_q1_congr_cl_offset + reld_q1_congr_cl_d'length-1), + din => reld_q1_congr_cl_d, + dout => reld_q1_congr_cl_q); +reld_q1_way_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q1_way_offset to reld_q1_way_offset + reld_q1_way_d'length-1), + scout => sov(reld_q1_way_offset to reld_q1_way_offset + reld_q1_way_d'length-1), + din => reld_q1_way_d, + dout => reld_q1_way_q); +reld_q1_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q1_val_offset), + scout => sov(reld_q1_val_offset), + din => reld_q1_val_d, + dout => reld_q1_val_q); +reld_q1_lock_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q1_lock_offset), + scout => sov(reld_q1_lock_offset), + din => reld_q1_lock_d, + dout => reld_q1_lock_q); +reld_q2_congr_cl_reg: tri_rlmreg_p +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q2_congr_cl_offset to reld_q2_congr_cl_offset + reld_q2_congr_cl_d'length-1), + scout => sov(reld_q2_congr_cl_offset to reld_q2_congr_cl_offset + reld_q2_congr_cl_d'length-1), + din => reld_q2_congr_cl_d, + dout => reld_q2_congr_cl_q); +reld_q2_way_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q2_way_offset to reld_q2_way_offset + reld_q2_way_d'length-1), + scout => sov(reld_q2_way_offset to reld_q2_way_offset + reld_q2_way_d'length-1), + din => reld_q2_way_d, + dout => reld_q2_way_q); +reld_q2_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q2_val_offset), + scout => sov(reld_q2_val_offset), + din => reld_q2_val_d, + dout => reld_q2_val_q); +reld_q2_lock_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q2_lock_offset), + scout => sov(reld_q2_lock_offset), + din => reld_q2_lock_d, + dout => reld_q2_lock_q); +reld_q3_congr_cl_reg: tri_rlmreg_p +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q3_congr_cl_offset to reld_q3_congr_cl_offset + reld_q3_congr_cl_d'length-1), + scout => sov(reld_q3_congr_cl_offset to reld_q3_congr_cl_offset + reld_q3_congr_cl_d'length-1), + din => reld_q3_congr_cl_d, + dout => reld_q3_congr_cl_q); +reld_q3_way_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q3_way_offset to reld_q3_way_offset + reld_q3_way_d'length-1), + scout => sov(reld_q3_way_offset to reld_q3_way_offset + reld_q3_way_d'length-1), + din => reld_q3_way_d, + dout => reld_q3_way_q); +reld_q3_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q3_val_offset), + scout => sov(reld_q3_val_offset), + din => reld_q3_val_d, + dout => reld_q3_val_q); +reld_q3_lock_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q3_lock_offset), + scout => sov(reld_q3_lock_offset), + din => reld_q3_lock_d, + dout => reld_q3_lock_q); +reld_q4_congr_cl_reg: tri_rlmreg_p +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q4_congr_cl_offset to reld_q4_congr_cl_offset + reld_q4_congr_cl_d'length-1), + scout => sov(reld_q4_congr_cl_offset to reld_q4_congr_cl_offset + reld_q4_congr_cl_d'length-1), + din => reld_q4_congr_cl_d, + dout => reld_q4_congr_cl_q); +reld_q4_way_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q4_way_offset to reld_q4_way_offset + reld_q4_way_d'length-1), + scout => sov(reld_q4_way_offset to reld_q4_way_offset + reld_q4_way_d'length-1), + din => reld_q4_way_d, + dout => reld_q4_way_q); +reld_q4_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q4_val_offset), + scout => sov(reld_q4_val_offset), + din => reld_q4_val_d, + dout => reld_q4_val_q); +reld_q4_lock_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q4_lock_offset), + scout => sov(reld_q4_lock_offset), + din => reld_q4_lock_d, + dout => reld_q4_lock_q); +reld_q5_congr_cl_reg: tri_rlmreg_p +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q5_congr_cl_offset to reld_q5_congr_cl_offset + reld_q5_congr_cl_d'length-1), + scout => sov(reld_q5_congr_cl_offset to reld_q5_congr_cl_offset + reld_q5_congr_cl_d'length-1), + din => reld_q5_congr_cl_d, + dout => reld_q5_congr_cl_q); +reld_q5_way_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q5_way_offset to reld_q5_way_offset + reld_q5_way_d'length-1), + scout => sov(reld_q5_way_offset to reld_q5_way_offset + reld_q5_way_d'length-1), + din => reld_q5_way_d, + dout => reld_q5_way_q); +reld_q5_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q5_val_offset), + scout => sov(reld_q5_val_offset), + din => reld_q5_val_d, + dout => reld_q5_val_q); +reld_q5_lock_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q5_lock_offset), + scout => sov(reld_q5_lock_offset), + din => reld_q5_lock_d, + dout => reld_q5_lock_q); +reld_q6_congr_cl_reg: tri_rlmreg_p +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q6_congr_cl_offset to reld_q6_congr_cl_offset + reld_q6_congr_cl_d'length-1), + scout => sov(reld_q6_congr_cl_offset to reld_q6_congr_cl_offset + reld_q6_congr_cl_d'length-1), + din => reld_q6_congr_cl_d, + dout => reld_q6_congr_cl_q); +reld_q6_way_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q6_way_offset to reld_q6_way_offset + reld_q6_way_d'length-1), + scout => sov(reld_q6_way_offset to reld_q6_way_offset + reld_q6_way_d'length-1), + din => reld_q6_way_d, + dout => reld_q6_way_q); +reld_q6_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q6_val_offset), + scout => sov(reld_q6_val_offset), + din => reld_q6_val_d, + dout => reld_q6_val_q); +reld_q6_lock_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q6_lock_offset), + scout => sov(reld_q6_lock_offset), + din => reld_q6_lock_d, + dout => reld_q6_lock_q); +reld_q7_congr_cl_reg: tri_rlmreg_p +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q7_congr_cl_offset to reld_q7_congr_cl_offset + reld_q7_congr_cl_d'length-1), + scout => sov(reld_q7_congr_cl_offset to reld_q7_congr_cl_offset + reld_q7_congr_cl_d'length-1), + din => reld_q7_congr_cl_d, + dout => reld_q7_congr_cl_q); +reld_q7_way_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q7_way_offset to reld_q7_way_offset + reld_q7_way_d'length-1), + scout => sov(reld_q7_way_offset to reld_q7_way_offset + reld_q7_way_d'length-1), + din => reld_q7_way_d, + dout => reld_q7_way_q); +reld_q7_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q7_val_offset), + scout => sov(reld_q7_val_offset), + din => reld_q7_val_d, + dout => reld_q7_val_q); +reld_q7_lock_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q7_lock_offset), + scout => sov(reld_q7_lock_offset), + din => reld_q7_lock_d, + dout => reld_q7_lock_q); +rel_m_q_way_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_m_q_way_offset to rel_m_q_way_offset + rel_m_q_way_d'length-1), + scout => sov(rel_m_q_way_offset to rel_m_q_way_offset + rel_m_q_way_d'length-1), + din => rel_m_q_way_d, + dout => rel_m_q_way_q); +ex3_no_lru_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_no_lru_upd_offset), + scout => sov(ex3_no_lru_upd_offset), + din => ex3_no_lru_upd_d, + dout => ex3_no_lru_upd_q); +rel2_lock_en_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel2_lock_en_offset), + scout => sov(rel2_lock_en_offset), + din => rel2_lock_en_d, + dout => rel2_lock_en_q); +xucr0_clo_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xucr0_clo_offset), + scout => sov(xucr0_clo_offset), + din => xucr0_clo_d, + dout => xucr0_clo_q); +rel_up_way_addr_reg: tri_rlmreg_p +generic map (width => 3, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_up_way_addr_offset to rel_up_way_addr_offset + rel_up_way_addr_d'length-1), + scout => sov(rel_up_way_addr_offset to rel_up_way_addr_offset + rel_up_way_addr_d'length-1), + din => rel_up_way_addr_d, + dout => rel_up_way_addr_q); +rel24_way_dwen_stg_reg: tri_regk +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel24_way_dwen_stg_d, + dout => rel24_way_dwen_stg_q); +rel_dcarr_addr_en_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_dcarr_addr_en_offset), + scout => sov(rel_dcarr_addr_en_offset), + din => rel_dcarr_addr_en_d, + dout => rel_dcarr_addr_en_q); +rel_dcarr_val_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_dcarr_val_upd_offset), + scout => sov(rel_dcarr_val_upd_offset), + din => rel_dcarr_val_upd_d, + dout => rel_dcarr_val_upd_q); +congr_cl_ex3_ex4_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex3_ex4_cmp_offset), + scout => sov(congr_cl_ex3_ex4_cmp_offset), + din => congr_cl_ex3_ex4_cmp_d, + dout => congr_cl_ex3_ex4_cmp_q); +congr_cl_ex3_ex5_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex3_ex5_cmp_offset), + scout => sov(congr_cl_ex3_ex5_cmp_offset), + din => congr_cl_ex3_ex5_cmp_d, + dout => congr_cl_ex3_ex5_cmp_q); +congr_cl_ex3_ex6_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex3_ex6_cmp_offset), + scout => sov(congr_cl_ex3_ex6_cmp_offset), + din => congr_cl_ex3_ex6_cmp_d, + dout => congr_cl_ex3_ex6_cmp_q); +congr_cl_ex3_rel2_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex3_rel2_cmp_offset), + scout => sov(congr_cl_ex3_rel2_cmp_offset), + din => congr_cl_ex3_rel2_cmp_d, + dout => congr_cl_ex3_rel2_cmp_q); +congr_cl_ex3_rel_upd_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex3_rel_upd_cmp_offset), + scout => sov(congr_cl_ex3_rel_upd_cmp_offset), + din => congr_cl_ex3_rel_upd_cmp_d, + dout => congr_cl_ex3_rel_upd_cmp_q); +congr_cl_rel1_ex4_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_rel1_ex4_cmp_offset), + scout => sov(congr_cl_rel1_ex4_cmp_offset), + din => congr_cl_rel1_ex4_cmp_d, + dout => congr_cl_rel1_ex4_cmp_q); +congr_cl_rel1_ex5_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_rel1_ex5_cmp_offset), + scout => sov(congr_cl_rel1_ex5_cmp_offset), + din => congr_cl_rel1_ex5_cmp_d, + dout => congr_cl_rel1_ex5_cmp_q); +congr_cl_rel1_ex6_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_rel1_ex6_cmp_offset), + scout => sov(congr_cl_rel1_ex6_cmp_offset), + din => congr_cl_rel1_ex6_cmp_d, + dout => congr_cl_rel1_ex6_cmp_q); +congr_cl_rel1_rel2_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_rel1_rel2_cmp_offset), + scout => sov(congr_cl_rel1_rel2_cmp_offset), + din => congr_cl_rel1_rel2_cmp_d, + dout => congr_cl_rel1_rel2_cmp_q); +congr_cl_rel1_relu_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_rel1_relu_cmp_offset), + scout => sov(congr_cl_rel1_relu_cmp_offset), + din => congr_cl_rel1_relu_cmp_d, + dout => congr_cl_rel1_relu_cmp_q); +congr_cl_rel1_rel_upd_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_rel1_rel_upd_cmp_offset), + scout => sov(congr_cl_rel1_rel_upd_cmp_offset), + din => congr_cl_rel1_rel_upd_cmp_d, + dout => congr_cl_rel1_rel_upd_cmp_q); +congr_cl_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_act_offset), + scout => sov(congr_cl_act_offset), + din => congr_cl_act_d, + dout => congr_cl_act_q); +siv(0 TO scan_right) <= sov(1 to scan_right) & scan_in; +scan_out <= sov(0); +END XUQ_LSU_DIR_LRU16; diff --git a/rel/src/vhdl/work/xuq_lsu_dir_lru32.vhdl b/rel/src/vhdl/work/xuq_lsu_dir_lru32.vhdl new file mode 100644 index 0000000..200b610 --- /dev/null +++ b/rel/src/vhdl/work/xuq_lsu_dir_lru32.vhdl @@ -0,0 +1,5398 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XU LSU L1 Data Directory LRU Register Array + +library ibm, ieee, work, tri, support; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use tri.tri_latches_pkg.all; +use support.power_logic_pkg.all; + +entity xuq_lsu_dir_lru32 is +generic(expand_type : integer := 2; + dc_size : natural := 15; + lmq_entries : integer := 8; + cl_size : natural := 6); +port( + + ex1_stg_act :in std_ulogic; + ex2_stg_act :in std_ulogic; + ex3_stg_act :in std_ulogic; + ex4_stg_act :in std_ulogic; + ex5_stg_act :in std_ulogic; + rel1_stg_act :in std_ulogic; + rel2_stg_act :in std_ulogic; + rel3_stg_act :in std_ulogic; + + rel1_val :in std_ulogic; + rel1_classid :in std_ulogic_vector(0 to 1); + rel_mid_val :in std_ulogic; + rel_retry_val :in std_ulogic; + rel3_val :in std_ulogic; + rel4_recirc_val :in std_ulogic; + rel4_ecc_err :in std_ulogic; + rel_st_tag_early :in std_ulogic_vector(1 to 3); + rel_st_tag :in std_ulogic_vector(1 to 3); + rel_addr_early :in std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + rel_lock_en :in std_ulogic; + + rel_way_val_a :in std_ulogic; + rel_way_val_b :in std_ulogic; + rel_way_val_c :in std_ulogic; + rel_way_val_d :in std_ulogic; + rel_way_val_e :in std_ulogic; + rel_way_val_f :in std_ulogic; + rel_way_val_g :in std_ulogic; + rel_way_val_h :in std_ulogic; + + rel_way_lock_a :in std_ulogic; + rel_way_lock_b :in std_ulogic; + rel_way_lock_c :in std_ulogic; + rel_way_lock_d :in std_ulogic; + rel_way_lock_e :in std_ulogic; + rel_way_lock_f :in std_ulogic; + rel_way_lock_g :in std_ulogic; + rel_way_lock_h :in std_ulogic; + + ex1_p_addr :in std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + ex3_cache_en :in std_ulogic; + ex2_no_lru_upd :in std_ulogic; + + ex4_way_a_hit :in std_ulogic; + ex4_way_b_hit :in std_ulogic; + ex4_way_c_hit :in std_ulogic; + ex4_way_d_hit :in std_ulogic; + ex4_way_e_hit :in std_ulogic; + ex4_way_f_hit :in std_ulogic; + ex4_way_g_hit :in std_ulogic; + ex4_way_h_hit :in std_ulogic; + ex3_hit :in std_ulogic; + + spr_xucr2_rmt :in std_ulogic_vector(0 to 31); + spr_xucr0_wlck :in std_ulogic; + spr_xucr0_dcdis :in std_ulogic; + spr_xucr0_cls :in std_ulogic; + + ex3_stg_flush :in std_ulogic; + ex4_stg_flush :in std_ulogic; + ex5_stg_flush :in std_ulogic; + + rel_way_upd_a :out std_ulogic; + rel_way_upd_b :out std_ulogic; + rel_way_upd_c :out std_ulogic; + rel_way_upd_d :out std_ulogic; + rel_way_upd_e :out std_ulogic; + rel_way_upd_f :out std_ulogic; + rel_way_upd_g :out std_ulogic; + rel_way_upd_h :out std_ulogic; + + rel_way_wen_a :out std_ulogic; + rel_way_wen_b :out std_ulogic; + rel_way_wen_c :out std_ulogic; + rel_way_wen_d :out std_ulogic; + rel_way_wen_e :out std_ulogic; + rel_way_wen_f :out std_ulogic; + rel_way_wen_g :out std_ulogic; + rel_way_wen_h :out std_ulogic; + + rel_way_clr_a :out std_ulogic; + rel_way_clr_b :out std_ulogic; + rel_way_clr_c :out std_ulogic; + rel_way_clr_d :out std_ulogic; + rel_way_clr_e :out std_ulogic; + rel_way_clr_f :out std_ulogic; + rel_way_clr_g :out std_ulogic; + rel_way_clr_h :out std_ulogic; + rel_dcarr_val_upd :out std_ulogic; + rel_up_way_addr_b :out std_ulogic_vector(0 to 2); + rel_dcarr_addr_en :out std_ulogic; + + lsu_xu_spr_xucr0_clo :out std_ulogic; + + ex4_dir_lru :out std_ulogic_vector(0 to 6); + + dc_lru_dbg_data :out std_ulogic_vector(0 to 81); + + vdd :inout power_logic; + gnd :inout power_logic; + nclk :in clk_logic; + sg_0 :in std_ulogic; + func_sl_thold_0_b :in std_ulogic; + func_sl_force :in std_ulogic; + func_nsl_thold_0_b :in std_ulogic; + func_nsl_force :in std_ulogic; + d_mode_dc :in std_ulogic; + delay_lclkr_dc :in std_ulogic; + mpw1_dc_b :in std_ulogic; + mpw2_dc_b :in std_ulogic; + scan_in :in std_ulogic; + scan_out :out std_ulogic + ); +-- synopsys translate_off +-- synopsys translate_on +end xuq_lsu_dir_lru32; +---- +ARCHITECTURE XUQ_LSU_DIR_LRU32 + OF XUQ_LSU_DIR_LRU32 + IS +---------------------------- +-- components +---------------------------- +---------------------------- +-- constants +---------------------------- +constant congr_cl0_lru_offset :natural := 0; +constant congr_cl1_lru_offset :natural := congr_cl0_lru_offset + 7; +constant congr_cl2_lru_offset :natural := congr_cl1_lru_offset + 7; +constant congr_cl3_lru_offset :natural := congr_cl2_lru_offset + 7; +constant congr_cl4_lru_offset :natural := congr_cl3_lru_offset + 7; +constant congr_cl5_lru_offset :natural := congr_cl4_lru_offset + 7; +constant congr_cl6_lru_offset :natural := congr_cl5_lru_offset + 7; +constant congr_cl7_lru_offset :natural := congr_cl6_lru_offset + 7; +constant congr_cl8_lru_offset :natural := congr_cl7_lru_offset + 7; +constant congr_cl9_lru_offset :natural := congr_cl8_lru_offset + 7; +constant congr_cl10_lru_offset :natural := congr_cl9_lru_offset + 7; +constant congr_cl11_lru_offset :natural := congr_cl10_lru_offset + 7; +constant congr_cl12_lru_offset :natural := congr_cl11_lru_offset + 7; +constant congr_cl13_lru_offset :natural := congr_cl12_lru_offset + 7; +constant congr_cl14_lru_offset :natural := congr_cl13_lru_offset + 7; +constant congr_cl15_lru_offset :natural := congr_cl14_lru_offset + 7; +constant congr_cl16_lru_offset :natural := congr_cl15_lru_offset + 7; +constant congr_cl17_lru_offset :natural := congr_cl16_lru_offset + 7; +constant congr_cl18_lru_offset :natural := congr_cl17_lru_offset + 7; +constant congr_cl19_lru_offset :natural := congr_cl18_lru_offset + 7; +constant congr_cl20_lru_offset :natural := congr_cl19_lru_offset + 7; +constant congr_cl21_lru_offset :natural := congr_cl20_lru_offset + 7; +constant congr_cl22_lru_offset :natural := congr_cl21_lru_offset + 7; +constant congr_cl23_lru_offset :natural := congr_cl22_lru_offset + 7; +constant congr_cl24_lru_offset :natural := congr_cl23_lru_offset + 7; +constant congr_cl25_lru_offset :natural := congr_cl24_lru_offset + 7; +constant congr_cl26_lru_offset :natural := congr_cl25_lru_offset + 7; +constant congr_cl27_lru_offset :natural := congr_cl26_lru_offset + 7; +constant congr_cl28_lru_offset :natural := congr_cl27_lru_offset + 7; +constant congr_cl29_lru_offset :natural := congr_cl28_lru_offset + 7; +constant congr_cl30_lru_offset :natural := congr_cl29_lru_offset + 7; +constant congr_cl31_lru_offset :natural := congr_cl30_lru_offset + 7; +constant congr_cl32_lru_offset :natural := congr_cl31_lru_offset + 7; +constant congr_cl33_lru_offset :natural := congr_cl32_lru_offset + 7; +constant congr_cl34_lru_offset :natural := congr_cl33_lru_offset + 7; +constant congr_cl35_lru_offset :natural := congr_cl34_lru_offset + 7; +constant congr_cl36_lru_offset :natural := congr_cl35_lru_offset + 7; +constant congr_cl37_lru_offset :natural := congr_cl36_lru_offset + 7; +constant congr_cl38_lru_offset :natural := congr_cl37_lru_offset + 7; +constant congr_cl39_lru_offset :natural := congr_cl38_lru_offset + 7; +constant congr_cl40_lru_offset :natural := congr_cl39_lru_offset + 7; +constant congr_cl41_lru_offset :natural := congr_cl40_lru_offset + 7; +constant congr_cl42_lru_offset :natural := congr_cl41_lru_offset + 7; +constant congr_cl43_lru_offset :natural := congr_cl42_lru_offset + 7; +constant congr_cl44_lru_offset :natural := congr_cl43_lru_offset + 7; +constant congr_cl45_lru_offset :natural := congr_cl44_lru_offset + 7; +constant congr_cl46_lru_offset :natural := congr_cl45_lru_offset + 7; +constant congr_cl47_lru_offset :natural := congr_cl46_lru_offset + 7; +constant congr_cl48_lru_offset :natural := congr_cl47_lru_offset + 7; +constant congr_cl49_lru_offset :natural := congr_cl48_lru_offset + 7; +constant congr_cl50_lru_offset :natural := congr_cl49_lru_offset + 7; +constant congr_cl51_lru_offset :natural := congr_cl50_lru_offset + 7; +constant congr_cl52_lru_offset :natural := congr_cl51_lru_offset + 7; +constant congr_cl53_lru_offset :natural := congr_cl52_lru_offset + 7; +constant congr_cl54_lru_offset :natural := congr_cl53_lru_offset + 7; +constant congr_cl55_lru_offset :natural := congr_cl54_lru_offset + 7; +constant congr_cl56_lru_offset :natural := congr_cl55_lru_offset + 7; +constant congr_cl57_lru_offset :natural := congr_cl56_lru_offset + 7; +constant congr_cl58_lru_offset :natural := congr_cl57_lru_offset + 7; +constant congr_cl59_lru_offset :natural := congr_cl58_lru_offset + 7; +constant congr_cl60_lru_offset :natural := congr_cl59_lru_offset + 7; +constant congr_cl61_lru_offset :natural := congr_cl60_lru_offset + 7; +constant congr_cl62_lru_offset :natural := congr_cl61_lru_offset + 7; +constant congr_cl63_lru_offset :natural := congr_cl62_lru_offset + 7; +constant congr_cl_lru_b_offset :natural := congr_cl63_lru_offset + 7; +constant rel_congr_cl_lru_b_offset :natural := congr_cl_lru_b_offset + 7; +constant reld_q_sel_offset :natural := rel_congr_cl_lru_b_offset + 7; +constant ex5_congr_cl_offset :natural := reld_q_sel_offset + 8; +constant rel_congr_cl_offset :natural := ex5_congr_cl_offset + 6; +constant relu_congr_cl_offset :natural := rel_congr_cl_offset + 6; +constant ex5_lru_upd_offset :natural := relu_congr_cl_offset + 6; +constant rel2_val_offset :natural := ex5_lru_upd_offset + 7; +constant relu_val_wen_offset :natural := rel2_val_offset + 1; +constant ex4_hit_offset :natural := relu_val_wen_offset + 1; +constant ex4_c_acc_offset :natural := ex4_hit_offset + 1; +constant ex5_c_acc_offset :natural := ex4_c_acc_offset + 1; +constant ex6_c_acc_val_offset :natural := ex5_c_acc_offset + 1; +constant ex3_congr_cl_offset :natural := ex6_c_acc_val_offset + 1; +constant rel_val_wen_offset :natural := ex3_congr_cl_offset + 6; +constant relu_lru_upd_offset :natural := rel_val_wen_offset + 1; +constant rel_way_qsel_offset :natural := relu_lru_upd_offset + 7; +constant rel_val_qsel_offset :natural := rel_way_qsel_offset + 8; +constant rel_way_early_qsel_offset :natural := rel_val_qsel_offset + 1; +constant rel_val_early_qsel_offset :natural := rel_way_early_qsel_offset + 8; +constant rel4_val_offset :natural := rel_val_early_qsel_offset + 1; +constant rel2_mid_val_offset :natural := rel4_val_offset + 1; +constant rel4_retry_val_offset :natural := rel2_mid_val_offset + 1; +constant rel2_wlock_offset :natural := rel4_retry_val_offset + 1; +constant reld_q0_congr_cl_offset :natural := rel2_wlock_offset + 8; +constant reld_q1_congr_cl_offset :natural := reld_q0_congr_cl_offset + 6; +constant reld_q2_congr_cl_offset :natural := reld_q1_congr_cl_offset + 6; +constant reld_q3_congr_cl_offset :natural := reld_q2_congr_cl_offset + 6; +constant reld_q4_congr_cl_offset :natural := reld_q3_congr_cl_offset + 6; +constant reld_q5_congr_cl_offset :natural := reld_q4_congr_cl_offset + 6; +constant reld_q6_congr_cl_offset :natural := reld_q5_congr_cl_offset + 6; +constant reld_q7_congr_cl_offset :natural := reld_q6_congr_cl_offset + 6; +constant reld_q0_way_offset :natural := reld_q7_congr_cl_offset + 6; +constant reld_q1_way_offset :natural := reld_q0_way_offset + 8; +constant reld_q2_way_offset :natural := reld_q1_way_offset + 8; +constant reld_q3_way_offset :natural := reld_q2_way_offset + 8; +constant reld_q4_way_offset :natural := reld_q3_way_offset + 8; +constant reld_q5_way_offset :natural := reld_q4_way_offset + 8; +constant reld_q6_way_offset :natural := reld_q5_way_offset + 8; +constant reld_q7_way_offset :natural := reld_q6_way_offset + 8; +constant reld_q0_val_offset :natural := reld_q7_way_offset + 8; +constant reld_q1_val_offset :natural := reld_q0_val_offset + 1; +constant reld_q2_val_offset :natural := reld_q1_val_offset + 1; +constant reld_q3_val_offset :natural := reld_q2_val_offset + 1; +constant reld_q4_val_offset :natural := reld_q3_val_offset + 1; +constant reld_q5_val_offset :natural := reld_q4_val_offset + 1; +constant reld_q6_val_offset :natural := reld_q5_val_offset + 1; +constant reld_q7_val_offset :natural := reld_q6_val_offset + 1; +constant reld_q0_lock_offset :natural := reld_q7_val_offset + 1; +constant reld_q1_lock_offset :natural := reld_q0_lock_offset + 1; +constant reld_q2_lock_offset :natural := reld_q1_lock_offset + 1; +constant reld_q3_lock_offset :natural := reld_q2_lock_offset + 1; +constant reld_q4_lock_offset :natural := reld_q3_lock_offset + 1; +constant reld_q5_lock_offset :natural := reld_q4_lock_offset + 1; +constant reld_q6_lock_offset :natural := reld_q5_lock_offset + 1; +constant reld_q7_lock_offset :natural := reld_q6_lock_offset + 1; +constant rel_m_q_way_offset :natural := reld_q7_lock_offset + 1; +constant ex3_no_lru_upd_offset :natural := rel_m_q_way_offset + 8; +constant rel2_lock_en_offset :natural := ex3_no_lru_upd_offset + 1; +constant xucr0_clo_offset :natural := rel2_lock_en_offset + 1; +constant rel_up_way_addr_offset :natural := xucr0_clo_offset + 1; +constant rel_dcarr_addr_en_offset :natural := rel_up_way_addr_offset + 3; +constant rel_dcarr_val_upd_offset :natural := rel_dcarr_addr_en_offset + 1; +constant congr_cl_ex3_ex4_cmp_offset :natural := rel_dcarr_val_upd_offset + 1; +constant congr_cl_ex3_ex5_cmp_offset :natural := congr_cl_ex3_ex4_cmp_offset + 1; +constant congr_cl_ex3_ex6_cmp_offset :natural := congr_cl_ex3_ex5_cmp_offset + 1; +constant congr_cl_ex3_rel2_cmp_offset :natural := congr_cl_ex3_ex6_cmp_offset + 1; +constant congr_cl_ex3_rel_upd_cmp_offset :natural := congr_cl_ex3_rel2_cmp_offset + 1; +constant congr_cl_rel1_ex4_cmp_offset :natural := congr_cl_ex3_rel_upd_cmp_offset + 1; +constant congr_cl_rel1_ex5_cmp_offset :natural := congr_cl_rel1_ex4_cmp_offset + 1; +constant congr_cl_rel1_ex6_cmp_offset :natural := congr_cl_rel1_ex5_cmp_offset + 1; +constant congr_cl_rel1_rel2_cmp_offset :natural := congr_cl_rel1_ex6_cmp_offset + 1; +constant congr_cl_rel1_relu_cmp_offset :natural := congr_cl_rel1_rel2_cmp_offset + 1; +constant congr_cl_rel1_rel_upd_cmp_offset :natural := congr_cl_rel1_relu_cmp_offset + 1; +constant congr_cl_act_offset :natural := congr_cl_rel1_rel_upd_cmp_offset + 1; +constant scan_right :natural := congr_cl_act_offset + 1 - 1; +---------------------------- +-- signals +---------------------------- +signal congr_cl0_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl0_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl0_lru_wen :std_ulogic; +signal xu_op_cl0_lru_wen :std_ulogic; +signal rel_cl0_lru_wen :std_ulogic; +signal rel_ldst_cl0_lru :std_ulogic_vector(0 to 6); +signal congr_cl1_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl1_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl1_lru_wen :std_ulogic; +signal xu_op_cl1_lru_wen :std_ulogic; +signal rel_cl1_lru_wen :std_ulogic; +signal rel_ldst_cl1_lru :std_ulogic_vector(0 to 6); +signal congr_cl2_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl2_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl2_lru_wen :std_ulogic; +signal xu_op_cl2_lru_wen :std_ulogic; +signal rel_cl2_lru_wen :std_ulogic; +signal rel_ldst_cl2_lru :std_ulogic_vector(0 to 6); +signal congr_cl3_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl3_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl3_lru_wen :std_ulogic; +signal xu_op_cl3_lru_wen :std_ulogic; +signal rel_cl3_lru_wen :std_ulogic; +signal rel_ldst_cl3_lru :std_ulogic_vector(0 to 6); +signal congr_cl4_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl4_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl4_lru_wen :std_ulogic; +signal xu_op_cl4_lru_wen :std_ulogic; +signal rel_cl4_lru_wen :std_ulogic; +signal rel_ldst_cl4_lru :std_ulogic_vector(0 to 6); +signal congr_cl5_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl5_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl5_lru_wen :std_ulogic; +signal xu_op_cl5_lru_wen :std_ulogic; +signal rel_cl5_lru_wen :std_ulogic; +signal rel_ldst_cl5_lru :std_ulogic_vector(0 to 6); +signal congr_cl6_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl6_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl6_lru_wen :std_ulogic; +signal xu_op_cl6_lru_wen :std_ulogic; +signal rel_cl6_lru_wen :std_ulogic; +signal rel_ldst_cl6_lru :std_ulogic_vector(0 to 6); +signal congr_cl7_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl7_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl7_lru_wen :std_ulogic; +signal xu_op_cl7_lru_wen :std_ulogic; +signal rel_cl7_lru_wen :std_ulogic; +signal rel_ldst_cl7_lru :std_ulogic_vector(0 to 6); +signal congr_cl8_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl8_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl8_lru_wen :std_ulogic; +signal xu_op_cl8_lru_wen :std_ulogic; +signal rel_cl8_lru_wen :std_ulogic; +signal rel_ldst_cl8_lru :std_ulogic_vector(0 to 6); +signal congr_cl9_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl9_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl9_lru_wen :std_ulogic; +signal xu_op_cl9_lru_wen :std_ulogic; +signal rel_cl9_lru_wen :std_ulogic; +signal rel_ldst_cl9_lru :std_ulogic_vector(0 to 6); +signal congr_cl10_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl10_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl10_lru_wen :std_ulogic; +signal xu_op_cl10_lru_wen :std_ulogic; +signal rel_cl10_lru_wen :std_ulogic; +signal rel_ldst_cl10_lru :std_ulogic_vector(0 to 6); +signal congr_cl11_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl11_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl11_lru_wen :std_ulogic; +signal xu_op_cl11_lru_wen :std_ulogic; +signal rel_cl11_lru_wen :std_ulogic; +signal rel_ldst_cl11_lru :std_ulogic_vector(0 to 6); +signal congr_cl12_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl12_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl12_lru_wen :std_ulogic; +signal xu_op_cl12_lru_wen :std_ulogic; +signal rel_cl12_lru_wen :std_ulogic; +signal rel_ldst_cl12_lru :std_ulogic_vector(0 to 6); +signal congr_cl13_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl13_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl13_lru_wen :std_ulogic; +signal xu_op_cl13_lru_wen :std_ulogic; +signal rel_cl13_lru_wen :std_ulogic; +signal rel_ldst_cl13_lru :std_ulogic_vector(0 to 6); +signal congr_cl14_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl14_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl14_lru_wen :std_ulogic; +signal xu_op_cl14_lru_wen :std_ulogic; +signal rel_cl14_lru_wen :std_ulogic; +signal rel_ldst_cl14_lru :std_ulogic_vector(0 to 6); +signal congr_cl15_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl15_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl15_lru_wen :std_ulogic; +signal xu_op_cl15_lru_wen :std_ulogic; +signal rel_cl15_lru_wen :std_ulogic; +signal rel_ldst_cl15_lru :std_ulogic_vector(0 to 6); +signal congr_cl16_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl16_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl16_lru_wen :std_ulogic; +signal xu_op_cl16_lru_wen :std_ulogic; +signal rel_cl16_lru_wen :std_ulogic; +signal rel_ldst_cl16_lru :std_ulogic_vector(0 to 6); +signal congr_cl17_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl17_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl17_lru_wen :std_ulogic; +signal xu_op_cl17_lru_wen :std_ulogic; +signal rel_cl17_lru_wen :std_ulogic; +signal rel_ldst_cl17_lru :std_ulogic_vector(0 to 6); +signal congr_cl18_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl18_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl18_lru_wen :std_ulogic; +signal xu_op_cl18_lru_wen :std_ulogic; +signal rel_cl18_lru_wen :std_ulogic; +signal rel_ldst_cl18_lru :std_ulogic_vector(0 to 6); +signal congr_cl19_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl19_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl19_lru_wen :std_ulogic; +signal xu_op_cl19_lru_wen :std_ulogic; +signal rel_cl19_lru_wen :std_ulogic; +signal rel_ldst_cl19_lru :std_ulogic_vector(0 to 6); +signal congr_cl20_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl20_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl20_lru_wen :std_ulogic; +signal xu_op_cl20_lru_wen :std_ulogic; +signal rel_cl20_lru_wen :std_ulogic; +signal rel_ldst_cl20_lru :std_ulogic_vector(0 to 6); +signal congr_cl21_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl21_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl21_lru_wen :std_ulogic; +signal xu_op_cl21_lru_wen :std_ulogic; +signal rel_cl21_lru_wen :std_ulogic; +signal rel_ldst_cl21_lru :std_ulogic_vector(0 to 6); +signal congr_cl22_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl22_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl22_lru_wen :std_ulogic; +signal xu_op_cl22_lru_wen :std_ulogic; +signal rel_cl22_lru_wen :std_ulogic; +signal rel_ldst_cl22_lru :std_ulogic_vector(0 to 6); +signal congr_cl23_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl23_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl23_lru_wen :std_ulogic; +signal xu_op_cl23_lru_wen :std_ulogic; +signal rel_cl23_lru_wen :std_ulogic; +signal rel_ldst_cl23_lru :std_ulogic_vector(0 to 6); +signal congr_cl24_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl24_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl24_lru_wen :std_ulogic; +signal xu_op_cl24_lru_wen :std_ulogic; +signal rel_cl24_lru_wen :std_ulogic; +signal rel_ldst_cl24_lru :std_ulogic_vector(0 to 6); +signal congr_cl25_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl25_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl25_lru_wen :std_ulogic; +signal xu_op_cl25_lru_wen :std_ulogic; +signal rel_cl25_lru_wen :std_ulogic; +signal rel_ldst_cl25_lru :std_ulogic_vector(0 to 6); +signal congr_cl26_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl26_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl26_lru_wen :std_ulogic; +signal xu_op_cl26_lru_wen :std_ulogic; +signal rel_cl26_lru_wen :std_ulogic; +signal rel_ldst_cl26_lru :std_ulogic_vector(0 to 6); +signal congr_cl27_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl27_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl27_lru_wen :std_ulogic; +signal xu_op_cl27_lru_wen :std_ulogic; +signal rel_cl27_lru_wen :std_ulogic; +signal rel_ldst_cl27_lru :std_ulogic_vector(0 to 6); +signal congr_cl28_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl28_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl28_lru_wen :std_ulogic; +signal xu_op_cl28_lru_wen :std_ulogic; +signal rel_cl28_lru_wen :std_ulogic; +signal rel_ldst_cl28_lru :std_ulogic_vector(0 to 6); +signal congr_cl29_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl29_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl29_lru_wen :std_ulogic; +signal xu_op_cl29_lru_wen :std_ulogic; +signal rel_cl29_lru_wen :std_ulogic; +signal rel_ldst_cl29_lru :std_ulogic_vector(0 to 6); +signal congr_cl30_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl30_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl30_lru_wen :std_ulogic; +signal xu_op_cl30_lru_wen :std_ulogic; +signal rel_cl30_lru_wen :std_ulogic; +signal rel_ldst_cl30_lru :std_ulogic_vector(0 to 6); +signal congr_cl31_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl31_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl31_lru_wen :std_ulogic; +signal xu_op_cl31_lru_wen :std_ulogic; +signal rel_cl31_lru_wen :std_ulogic; +signal rel_ldst_cl31_lru :std_ulogic_vector(0 to 6); +signal congr_cl32_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl32_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl32_lru_wen :std_ulogic; +signal xu_op_cl32_lru_wen :std_ulogic; +signal rel_cl32_lru_wen :std_ulogic; +signal rel_ldst_cl32_lru :std_ulogic_vector(0 to 6); +signal congr_cl33_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl33_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl33_lru_wen :std_ulogic; +signal xu_op_cl33_lru_wen :std_ulogic; +signal rel_cl33_lru_wen :std_ulogic; +signal rel_ldst_cl33_lru :std_ulogic_vector(0 to 6); +signal congr_cl34_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl34_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl34_lru_wen :std_ulogic; +signal xu_op_cl34_lru_wen :std_ulogic; +signal rel_cl34_lru_wen :std_ulogic; +signal rel_ldst_cl34_lru :std_ulogic_vector(0 to 6); +signal congr_cl35_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl35_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl35_lru_wen :std_ulogic; +signal xu_op_cl35_lru_wen :std_ulogic; +signal rel_cl35_lru_wen :std_ulogic; +signal rel_ldst_cl35_lru :std_ulogic_vector(0 to 6); +signal congr_cl36_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl36_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl36_lru_wen :std_ulogic; +signal xu_op_cl36_lru_wen :std_ulogic; +signal rel_cl36_lru_wen :std_ulogic; +signal rel_ldst_cl36_lru :std_ulogic_vector(0 to 6); +signal congr_cl37_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl37_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl37_lru_wen :std_ulogic; +signal xu_op_cl37_lru_wen :std_ulogic; +signal rel_cl37_lru_wen :std_ulogic; +signal rel_ldst_cl37_lru :std_ulogic_vector(0 to 6); +signal congr_cl38_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl38_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl38_lru_wen :std_ulogic; +signal xu_op_cl38_lru_wen :std_ulogic; +signal rel_cl38_lru_wen :std_ulogic; +signal rel_ldst_cl38_lru :std_ulogic_vector(0 to 6); +signal congr_cl39_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl39_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl39_lru_wen :std_ulogic; +signal xu_op_cl39_lru_wen :std_ulogic; +signal rel_cl39_lru_wen :std_ulogic; +signal rel_ldst_cl39_lru :std_ulogic_vector(0 to 6); +signal congr_cl40_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl40_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl40_lru_wen :std_ulogic; +signal xu_op_cl40_lru_wen :std_ulogic; +signal rel_cl40_lru_wen :std_ulogic; +signal rel_ldst_cl40_lru :std_ulogic_vector(0 to 6); +signal congr_cl41_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl41_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl41_lru_wen :std_ulogic; +signal xu_op_cl41_lru_wen :std_ulogic; +signal rel_cl41_lru_wen :std_ulogic; +signal rel_ldst_cl41_lru :std_ulogic_vector(0 to 6); +signal congr_cl42_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl42_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl42_lru_wen :std_ulogic; +signal xu_op_cl42_lru_wen :std_ulogic; +signal rel_cl42_lru_wen :std_ulogic; +signal rel_ldst_cl42_lru :std_ulogic_vector(0 to 6); +signal congr_cl43_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl43_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl43_lru_wen :std_ulogic; +signal xu_op_cl43_lru_wen :std_ulogic; +signal rel_cl43_lru_wen :std_ulogic; +signal rel_ldst_cl43_lru :std_ulogic_vector(0 to 6); +signal congr_cl44_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl44_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl44_lru_wen :std_ulogic; +signal xu_op_cl44_lru_wen :std_ulogic; +signal rel_cl44_lru_wen :std_ulogic; +signal rel_ldst_cl44_lru :std_ulogic_vector(0 to 6); +signal congr_cl45_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl45_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl45_lru_wen :std_ulogic; +signal xu_op_cl45_lru_wen :std_ulogic; +signal rel_cl45_lru_wen :std_ulogic; +signal rel_ldst_cl45_lru :std_ulogic_vector(0 to 6); +signal congr_cl46_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl46_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl46_lru_wen :std_ulogic; +signal xu_op_cl46_lru_wen :std_ulogic; +signal rel_cl46_lru_wen :std_ulogic; +signal rel_ldst_cl46_lru :std_ulogic_vector(0 to 6); +signal congr_cl47_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl47_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl47_lru_wen :std_ulogic; +signal xu_op_cl47_lru_wen :std_ulogic; +signal rel_cl47_lru_wen :std_ulogic; +signal rel_ldst_cl47_lru :std_ulogic_vector(0 to 6); +signal congr_cl48_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl48_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl48_lru_wen :std_ulogic; +signal xu_op_cl48_lru_wen :std_ulogic; +signal rel_cl48_lru_wen :std_ulogic; +signal rel_ldst_cl48_lru :std_ulogic_vector(0 to 6); +signal congr_cl49_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl49_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl49_lru_wen :std_ulogic; +signal xu_op_cl49_lru_wen :std_ulogic; +signal rel_cl49_lru_wen :std_ulogic; +signal rel_ldst_cl49_lru :std_ulogic_vector(0 to 6); +signal congr_cl50_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl50_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl50_lru_wen :std_ulogic; +signal xu_op_cl50_lru_wen :std_ulogic; +signal rel_cl50_lru_wen :std_ulogic; +signal rel_ldst_cl50_lru :std_ulogic_vector(0 to 6); +signal congr_cl51_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl51_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl51_lru_wen :std_ulogic; +signal xu_op_cl51_lru_wen :std_ulogic; +signal rel_cl51_lru_wen :std_ulogic; +signal rel_ldst_cl51_lru :std_ulogic_vector(0 to 6); +signal congr_cl52_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl52_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl52_lru_wen :std_ulogic; +signal xu_op_cl52_lru_wen :std_ulogic; +signal rel_cl52_lru_wen :std_ulogic; +signal rel_ldst_cl52_lru :std_ulogic_vector(0 to 6); +signal congr_cl53_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl53_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl53_lru_wen :std_ulogic; +signal xu_op_cl53_lru_wen :std_ulogic; +signal rel_cl53_lru_wen :std_ulogic; +signal rel_ldst_cl53_lru :std_ulogic_vector(0 to 6); +signal congr_cl54_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl54_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl54_lru_wen :std_ulogic; +signal xu_op_cl54_lru_wen :std_ulogic; +signal rel_cl54_lru_wen :std_ulogic; +signal rel_ldst_cl54_lru :std_ulogic_vector(0 to 6); +signal congr_cl55_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl55_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl55_lru_wen :std_ulogic; +signal xu_op_cl55_lru_wen :std_ulogic; +signal rel_cl55_lru_wen :std_ulogic; +signal rel_ldst_cl55_lru :std_ulogic_vector(0 to 6); +signal congr_cl56_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl56_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl56_lru_wen :std_ulogic; +signal xu_op_cl56_lru_wen :std_ulogic; +signal rel_cl56_lru_wen :std_ulogic; +signal rel_ldst_cl56_lru :std_ulogic_vector(0 to 6); +signal congr_cl57_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl57_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl57_lru_wen :std_ulogic; +signal xu_op_cl57_lru_wen :std_ulogic; +signal rel_cl57_lru_wen :std_ulogic; +signal rel_ldst_cl57_lru :std_ulogic_vector(0 to 6); +signal congr_cl58_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl58_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl58_lru_wen :std_ulogic; +signal xu_op_cl58_lru_wen :std_ulogic; +signal rel_cl58_lru_wen :std_ulogic; +signal rel_ldst_cl58_lru :std_ulogic_vector(0 to 6); +signal congr_cl59_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl59_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl59_lru_wen :std_ulogic; +signal xu_op_cl59_lru_wen :std_ulogic; +signal rel_cl59_lru_wen :std_ulogic; +signal rel_ldst_cl59_lru :std_ulogic_vector(0 to 6); +signal congr_cl60_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl60_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl60_lru_wen :std_ulogic; +signal xu_op_cl60_lru_wen :std_ulogic; +signal rel_cl60_lru_wen :std_ulogic; +signal rel_ldst_cl60_lru :std_ulogic_vector(0 to 6); +signal congr_cl61_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl61_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl61_lru_wen :std_ulogic; +signal xu_op_cl61_lru_wen :std_ulogic; +signal rel_cl61_lru_wen :std_ulogic; +signal rel_ldst_cl61_lru :std_ulogic_vector(0 to 6); +signal congr_cl62_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl62_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl62_lru_wen :std_ulogic; +signal xu_op_cl62_lru_wen :std_ulogic; +signal rel_cl62_lru_wen :std_ulogic; +signal rel_ldst_cl62_lru :std_ulogic_vector(0 to 6); +signal congr_cl63_lru_d :std_ulogic_vector(0 to 6); +signal congr_cl63_lru_q :std_ulogic_vector(0 to 6); +signal congr_cl63_lru_wen :std_ulogic; +signal xu_op_cl63_lru_wen :std_ulogic; +signal rel_cl63_lru_wen :std_ulogic; +signal rel_ldst_cl63_lru :std_ulogic_vector(0 to 6); +signal ex1_congr_cl :std_ulogic_vector(2 to 7); +signal ex2_congr_cl_d :std_ulogic_vector(2 to 7); +signal ex2_congr_cl_q :std_ulogic_vector(2 to 7); +signal ex3_congr_cl_d :std_ulogic_vector(2 to 7); +signal ex3_congr_cl_q :std_ulogic_vector(2 to 7); +signal ex4_congr_cl_d :std_ulogic_vector(2 to 7); +signal ex4_congr_cl_q :std_ulogic_vector(2 to 7); +signal ex5_congr_cl_d :std_ulogic_vector(2 to 7); +signal ex5_congr_cl_q :std_ulogic_vector(2 to 7); +signal ex6_congr_cl_d :std_ulogic_vector(2 to 7); +signal ex6_congr_cl_q :std_ulogic_vector(2 to 7); +signal rel_early_congr_cl :std_ulogic_vector(2 to 7); +signal rel_congr_cl_d :std_ulogic_vector(2 to 7); +signal rel_congr_cl_q :std_ulogic_vector(2 to 7); +signal rel_congr_cl_stg_d :std_ulogic_vector(2 to 7); +signal rel_congr_cl_stg_q :std_ulogic_vector(2 to 7); +signal relu_congr_cl_d :std_ulogic_vector(2 to 7); +signal relu_congr_cl_q :std_ulogic_vector(2 to 7); +signal rel2_val_d :std_ulogic; +signal rel2_val_q :std_ulogic; +signal relu_val_wen_d :std_ulogic; +signal relu_val_wen_q :std_ulogic; +signal rel_val_wen_d :std_ulogic; +signal rel_val_wen_q :std_ulogic; +signal congr_cl_lru_b_q :std_ulogic_vector(0 to 6); +signal rel_wayA_clr :std_ulogic; +signal rel_wayB_clr :std_ulogic; +signal rel_wayC_clr :std_ulogic; +signal rel_wayD_clr :std_ulogic; +signal rel_wayE_clr :std_ulogic; +signal rel_wayF_clr :std_ulogic; +signal rel_wayG_clr :std_ulogic; +signal rel_wayH_clr :std_ulogic; +signal rel_hit_vec :std_ulogic_vector(0 to 7); +signal hit_wayA_upd :std_ulogic_vector(0 to 6); +signal hit_wayB_upd :std_ulogic_vector(0 to 6); +signal hit_wayC_upd :std_ulogic_vector(0 to 6); +signal hit_wayD_upd :std_ulogic_vector(0 to 6); +signal hit_wayE_upd :std_ulogic_vector(0 to 6); +signal hit_wayF_upd :std_ulogic_vector(0 to 6); +signal hit_wayG_upd :std_ulogic_vector(0 to 6); +signal hit_wayh_upd :std_ulogic_vector(0 to 6); +signal rel_hit_wayA_upd :std_ulogic_vector(0 to 6); +signal rel_hit_wayB_upd :std_ulogic_vector(0 to 6); +signal rel_hit_wayC_upd :std_ulogic_vector(0 to 6); +signal rel_hit_wayD_upd :std_ulogic_vector(0 to 6); +signal rel_hit_wayE_upd :std_ulogic_vector(0 to 6); +signal rel_hit_wayF_upd :std_ulogic_vector(0 to 6); +signal rel_hit_wayG_upd :std_ulogic_vector(0 to 6); +signal rel_hit_wayh_upd :std_ulogic_vector(0 to 6); +signal ldst_wayA_hit :std_ulogic; +signal ldst_wayB_hit :std_ulogic; +signal ldst_wayC_hit :std_ulogic; +signal ldst_wayD_hit :std_ulogic; +signal ldst_wayE_hit :std_ulogic; +signal ldst_wayF_hit :std_ulogic; +signal ldst_wayG_hit :std_ulogic; +signal ldst_wayH_hit :std_ulogic; +signal lru_upd :std_ulogic_vector(0 to 6); +signal relu_lru_upd_d :std_ulogic_vector(0 to 6); +signal relu_lru_upd_q :std_ulogic_vector(0 to 6); +signal rel_lru_val_d :std_ulogic_vector(0 to 6); +signal rel_lru_val_q :std_ulogic_vector(0 to 6); +signal ex5_lru_upd_d :std_ulogic_vector(0 to 6); +signal ex5_lru_upd_q :std_ulogic_vector(0 to 6); +signal ex6_lru_upd_d :std_ulogic_vector(0 to 6); +signal ex6_lru_upd_q :std_ulogic_vector(0 to 6); +signal ex4_hit_d :std_ulogic; +signal ex4_hit_q :std_ulogic; +signal ex3_c_acc_val :std_ulogic; +signal ex4_c_acc_val :std_ulogic; +signal ex4_c_acc :std_ulogic; +signal ex4_c_acc_d :std_ulogic; +signal ex4_c_acc_q :std_ulogic; +signal ex5_c_acc_val :std_ulogic; +signal ex5_c_acc_d :std_ulogic; +signal ex5_c_acc_q :std_ulogic; +signal ex6_c_acc_val_d :std_ulogic; +signal ex6_c_acc_val_q :std_ulogic; +signal ex3_flush :std_ulogic; +signal ex4_flush :std_ulogic; +signal ex5_flush :std_ulogic; +signal xu_op_lru :std_ulogic_vector(0 to 6); +signal rel_op_lru :std_ulogic_vector(0 to 6); +signal ldst_hit_vector :std_ulogic_vector(0 to 7); +signal arr_congr_cl_lru :std_ulogic_vector(0 to 6); +signal rel_congr_cl_lru :std_ulogic_vector(0 to 6); +signal p0_arr_lru_rd :std_ulogic_vector(0 to 6); +signal p1_arr_lru_rd :std_ulogic_vector(0 to 6); +signal rel_congr_cl_lru_b_q :std_ulogic_vector(0 to 6); +signal congr_cl_ex3_ex4_m :std_ulogic; +signal congr_cl_ex3_ex5_m :std_ulogic; +signal congr_cl_ex3_p0_m :std_ulogic; +signal congr_cl_ex3_rel2_m :std_ulogic; +signal congr_cl_ex3_p1_m :std_ulogic; +signal congr_cl_ex3_ex4_cmp_d :std_ulogic; +signal congr_cl_ex3_ex4_cmp_q :std_ulogic; +signal congr_cl_ex3_ex5_cmp_d :std_ulogic; +signal congr_cl_ex3_ex5_cmp_q :std_ulogic; +signal congr_cl_ex3_ex6_cmp_d :std_ulogic; +signal congr_cl_ex3_ex6_cmp_q :std_ulogic; +signal congr_cl_ex3_rel2_cmp_d :std_ulogic; +signal congr_cl_ex3_rel2_cmp_q :std_ulogic; +signal congr_cl_ex3_rel_upd_cmp_d :std_ulogic; +signal congr_cl_ex3_rel_upd_cmp_q :std_ulogic; +signal congr_cl_rel1_ex4_cmp_d :std_ulogic; +signal congr_cl_rel1_ex4_cmp_q :std_ulogic; +signal congr_cl_rel1_ex5_cmp_d :std_ulogic; +signal congr_cl_rel1_ex5_cmp_q :std_ulogic; +signal congr_cl_rel1_ex6_cmp_d :std_ulogic; +signal congr_cl_rel1_ex6_cmp_q :std_ulogic; +signal congr_cl_rel1_rel2_cmp_d :std_ulogic; +signal congr_cl_rel1_rel2_cmp_q :std_ulogic; +signal congr_cl_rel1_relu_cmp_d :std_ulogic; +signal congr_cl_rel1_relu_cmp_q :std_ulogic; +signal congr_cl_rel1_rel_upd_cmp_d :std_ulogic; +signal congr_cl_rel1_rel_upd_cmp_q :std_ulogic; +signal ex3_no_lru_upd_d :std_ulogic; +signal ex3_no_lru_upd_q :std_ulogic; +signal ex3_l1hit :std_ulogic; +signal rel2_wayA_val :std_ulogic; +signal rel2_wayB_val :std_ulogic; +signal rel2_wayC_val :std_ulogic; +signal rel2_wayD_val :std_ulogic; +signal rel2_wayE_val :std_ulogic; +signal rel2_wayF_val :std_ulogic; +signal rel2_wayG_val :std_ulogic; +signal rel2_wayH_val :std_ulogic; +signal congr_cl_full :std_ulogic; +signal empty_way :std_ulogic_vector(0 to 7); +signal full_way :std_ulogic_vector(0 to 7); +signal rel_hit :std_ulogic_vector(0 to 7); +signal rel_upd_congr_cl_d :std_ulogic_vector(2 to 7); +signal rel_upd_congr_cl_q :std_ulogic_vector(2 to 7); +signal congr_cl_ex3_byp :std_ulogic_vector(0 to 4); +signal congr_cl_ex3_sel :std_ulogic_vector(1 to 4); +signal congr_cl_rel1_ex4_m :std_ulogic; +signal congr_cl_rel1_ex5_m :std_ulogic; +signal congr_cl_rel1_p0_m :std_ulogic; +signal congr_cl_rel1_rel2_m :std_ulogic; +signal congr_cl_rel1_relu_m :std_ulogic; +signal congr_cl_rel1_p1_m :std_ulogic; +signal rel_lru_early_sel :std_ulogic_vector(0 to 6); +signal rel_lru_early_sel_b :std_ulogic_vector(0 to 6); +signal congr_cl_rel1_byp :std_ulogic_vector(0 to 5); +signal congr_cl_rel1_sel :std_ulogic_vector(1 to 5); +signal rel_way_qsel_d :std_ulogic_vector(0 to 7); +signal rel_way_qsel_q :std_ulogic_vector(0 to 7); +signal rel_tag_d :std_ulogic_vector(0 to 2); +signal rel_tag_q :std_ulogic_vector(0 to 2); +signal rel4_val_d :std_ulogic; +signal rel4_val_q :std_ulogic; +signal rel4_retry_val_d :std_ulogic; +signal rel4_retry_val_q :std_ulogic; +signal rel_wayA_upd :std_ulogic; +signal rel_wayB_upd :std_ulogic; +signal rel_wayC_upd :std_ulogic; +signal rel_wayD_upd :std_ulogic; +signal rel_wayE_upd :std_ulogic; +signal rel_wayF_upd :std_ulogic; +signal rel_wayG_upd :std_ulogic; +signal rel_wayH_upd :std_ulogic; +signal rel_wayA_set :std_ulogic; +signal rel_wayB_set :std_ulogic; +signal rel_wayC_set :std_ulogic; +signal rel_wayD_set :std_ulogic; +signal rel_wayE_set :std_ulogic; +signal rel_wayF_set :std_ulogic; +signal rel_wayG_set :std_ulogic; +signal rel_wayH_set :std_ulogic; +signal rel_wayA_mid :std_ulogic; +signal rel_wayB_mid :std_ulogic; +signal rel_wayC_mid :std_ulogic; +signal rel_wayD_mid :std_ulogic; +signal rel_wayE_mid :std_ulogic; +signal rel_wayF_mid :std_ulogic; +signal rel_wayG_mid :std_ulogic; +signal rel_wayH_mid :std_ulogic; +signal rel1_wlock_b :std_ulogic_vector(0 to 7); +signal rel2_wlock_d :std_ulogic_vector(0 to 7); +signal rel2_wlock_q :std_ulogic_vector(0 to 7); +signal rel2_wayA_lock :std_ulogic; +signal rel2_wayB_lock :std_ulogic; +signal rel2_wayC_lock :std_ulogic; +signal rel2_wayD_lock :std_ulogic; +signal rel2_wayE_lock :std_ulogic; +signal rel2_wayF_lock :std_ulogic; +signal rel2_wayG_lock :std_ulogic; +signal rel2_wayH_lock :std_ulogic; +signal rel_lock_line :std_ulogic_vector(0 to 7); +signal rel_ovrd_lru :std_ulogic_vector(0 to 6); +signal rel_ovrd_wayAB :std_ulogic_vector(0 to 1); +signal rel_ovrd_wayCD :std_ulogic_vector(0 to 1); +signal rel_ovrd_wayEF :std_ulogic_vector(0 to 1); +signal rel_ovrd_wayGH :std_ulogic_vector(0 to 1); +signal rel_ovrd_wayABCD :std_ulogic_vector(0 to 1); +signal rel_ovrd_wayEFGH :std_ulogic_vector(0 to 1); +signal rel_ovrd_wayABCDEFGH :std_ulogic_vector(0 to 1); +signal ovr_lock_det :std_ulogic; +signal ovr_lock_det_wlkon :std_ulogic; +signal ovr_lock_det_wlkoff :std_ulogic; +signal wayA_not_empty :std_ulogic; +signal wayB_not_empty :std_ulogic; +signal wayC_not_empty :std_ulogic; +signal wayD_not_empty :std_ulogic; +signal wayE_not_empty :std_ulogic; +signal wayF_not_empty :std_ulogic; +signal wayg_not_empty :std_ulogic; +signal wayH_not_empty :std_ulogic; +signal rel_way_not_empty_d :std_ulogic_vector(0 to 7); +signal rel_way_not_empty_q :std_ulogic_vector(0 to 7); +signal reld_q0_chk_val :std_ulogic; +signal reld_q0_chk_way :std_ulogic_vector(0 to 7); +signal reld_q0_way_m :std_ulogic; +signal reld_q0_set :std_ulogic; +signal reld_q0_inval :std_ulogic; +signal reld_q0_val_sel :std_ulogic_vector(0 to 1); +signal reld_q0_congr_cl_d :std_ulogic_vector(2 to 7); +signal reld_q0_congr_cl_q :std_ulogic_vector(2 to 7); +signal reld_q0_way_d :std_ulogic_vector(0 to 7); +signal reld_q0_way_q :std_ulogic_vector(0 to 7); +signal reld_q0_val_d :std_ulogic; +signal reld_q0_val_q :std_ulogic; +signal reld_q0_lock_d :std_ulogic; +signal reld_q0_lock_q :std_ulogic; +signal rel_m_q0 :std_ulogic; +signal reld_q1_chk_val :std_ulogic; +signal reld_q1_chk_way :std_ulogic_vector(0 to 7); +signal reld_q1_way_m :std_ulogic; +signal reld_q1_set :std_ulogic; +signal reld_q1_inval :std_ulogic; +signal reld_q1_val_sel :std_ulogic_vector(0 to 1); +signal reld_q1_congr_cl_d :std_ulogic_vector(2 to 7); +signal reld_q1_congr_cl_q :std_ulogic_vector(2 to 7); +signal reld_q1_way_d :std_ulogic_vector(0 to 7); +signal reld_q1_way_q :std_ulogic_vector(0 to 7); +signal reld_q1_val_d :std_ulogic; +signal reld_q1_val_q :std_ulogic; +signal reld_q1_lock_d :std_ulogic; +signal reld_q1_lock_q :std_ulogic; +signal rel_m_q1 :std_ulogic; +signal reld_q2_chk_val :std_ulogic; +signal reld_q2_chk_way :std_ulogic_vector(0 to 7); +signal reld_q2_way_m :std_ulogic; +signal reld_q2_set :std_ulogic; +signal reld_q2_inval :std_ulogic; +signal reld_q2_val_sel :std_ulogic_vector(0 to 1); +signal reld_q2_congr_cl_d :std_ulogic_vector(2 to 7); +signal reld_q2_congr_cl_q :std_ulogic_vector(2 to 7); +signal reld_q2_way_d :std_ulogic_vector(0 to 7); +signal reld_q2_way_q :std_ulogic_vector(0 to 7); +signal reld_q2_val_d :std_ulogic; +signal reld_q2_val_q :std_ulogic; +signal reld_q2_lock_d :std_ulogic; +signal reld_q2_lock_q :std_ulogic; +signal rel_m_q2 :std_ulogic; +signal reld_q3_chk_val :std_ulogic; +signal reld_q3_chk_way :std_ulogic_vector(0 to 7); +signal reld_q3_way_m :std_ulogic; +signal reld_q3_set :std_ulogic; +signal reld_q3_inval :std_ulogic; +signal reld_q3_val_sel :std_ulogic_vector(0 to 1); +signal reld_q3_congr_cl_d :std_ulogic_vector(2 to 7); +signal reld_q3_congr_cl_q :std_ulogic_vector(2 to 7); +signal reld_q3_way_d :std_ulogic_vector(0 to 7); +signal reld_q3_way_q :std_ulogic_vector(0 to 7); +signal reld_q3_val_d :std_ulogic; +signal reld_q3_val_q :std_ulogic; +signal reld_q3_lock_d :std_ulogic; +signal reld_q3_lock_q :std_ulogic; +signal rel_m_q3 :std_ulogic; +signal reld_q4_chk_val :std_ulogic; +signal reld_q4_chk_way :std_ulogic_vector(0 to 7); +signal reld_q4_way_m :std_ulogic; +signal reld_q4_set :std_ulogic; +signal reld_q4_inval :std_ulogic; +signal reld_q4_val_sel :std_ulogic_vector(0 to 1); +signal reld_q4_congr_cl_d :std_ulogic_vector(2 to 7); +signal reld_q4_congr_cl_q :std_ulogic_vector(2 to 7); +signal reld_q4_way_d :std_ulogic_vector(0 to 7); +signal reld_q4_way_q :std_ulogic_vector(0 to 7); +signal reld_q4_val_d :std_ulogic; +signal reld_q4_val_q :std_ulogic; +signal reld_q4_lock_d :std_ulogic; +signal reld_q4_lock_q :std_ulogic; +signal rel_m_q4 :std_ulogic; +signal reld_q5_chk_val :std_ulogic; +signal reld_q5_chk_way :std_ulogic_vector(0 to 7); +signal reld_q5_way_m :std_ulogic; +signal reld_q5_set :std_ulogic; +signal reld_q5_inval :std_ulogic; +signal reld_q5_val_sel :std_ulogic_vector(0 to 1); +signal reld_q5_congr_cl_d :std_ulogic_vector(2 to 7); +signal reld_q5_congr_cl_q :std_ulogic_vector(2 to 7); +signal reld_q5_way_d :std_ulogic_vector(0 to 7); +signal reld_q5_way_q :std_ulogic_vector(0 to 7); +signal reld_q5_val_d :std_ulogic; +signal reld_q5_val_q :std_ulogic; +signal reld_q5_lock_d :std_ulogic; +signal reld_q5_lock_q :std_ulogic; +signal rel_m_q5 :std_ulogic; +signal reld_q6_chk_val :std_ulogic; +signal reld_q6_chk_way :std_ulogic_vector(0 to 7); +signal reld_q6_way_m :std_ulogic; +signal reld_q6_set :std_ulogic; +signal reld_q6_inval :std_ulogic; +signal reld_q6_val_sel :std_ulogic_vector(0 to 1); +signal reld_q6_congr_cl_d :std_ulogic_vector(2 to 7); +signal reld_q6_congr_cl_q :std_ulogic_vector(2 to 7); +signal reld_q6_way_d :std_ulogic_vector(0 to 7); +signal reld_q6_way_q :std_ulogic_vector(0 to 7); +signal reld_q6_val_d :std_ulogic; +signal reld_q6_val_q :std_ulogic; +signal reld_q6_lock_d :std_ulogic; +signal reld_q6_lock_q :std_ulogic; +signal rel_m_q6 :std_ulogic; +signal reld_q7_chk_val :std_ulogic; +signal reld_q7_chk_way :std_ulogic_vector(0 to 7); +signal reld_q7_way_m :std_ulogic; +signal reld_q7_set :std_ulogic; +signal reld_q7_inval :std_ulogic; +signal reld_q7_val_sel :std_ulogic_vector(0 to 1); +signal reld_q7_congr_cl_d :std_ulogic_vector(2 to 7); +signal reld_q7_congr_cl_q :std_ulogic_vector(2 to 7); +signal reld_q7_way_d :std_ulogic_vector(0 to 7); +signal reld_q7_way_q :std_ulogic_vector(0 to 7); +signal reld_q7_val_d :std_ulogic; +signal reld_q7_val_q :std_ulogic; +signal reld_q7_lock_d :std_ulogic; +signal reld_q7_lock_q :std_ulogic; +signal rel_m_q7 :std_ulogic; +signal reld_match :std_ulogic_vector(0 to 7); +signal reld_q_sel_d :std_ulogic_vector(0 to 7); +signal reld_q_sel_q :std_ulogic_vector(0 to 7); +signal rel_val_qsel_d :std_ulogic; +signal rel_val_qsel_q :std_ulogic; +signal spr_rmt_table :std_ulogic_vector(0 to 31); +signal rel_class_id :std_ulogic_vector(0 to 1); +signal rel2_class_id_d :std_ulogic_vector(0 to 1); +signal rel2_class_id_q :std_ulogic_vector(0 to 1); +signal rel_m_q_way_b :std_ulogic_vector(0 to 7); +signal rel_m_q_way_d :std_ulogic_vector(0 to 7); +signal rel_m_q_way_q :std_ulogic_vector(0 to 7); +signal rel_m_q_lock_way :std_ulogic_vector(0 to 7); +signal rel2_lock_en_d :std_ulogic; +signal rel2_lock_en_q :std_ulogic; +signal xucr0_clo_d :std_ulogic; +signal xucr0_clo_q :std_ulogic; +signal rel_way_dwen :std_ulogic_vector(0 to 7); +signal rel24_way_dwen_stg_d :std_ulogic_vector(0 to 7); +signal rel24_way_dwen_stg_q :std_ulogic_vector(0 to 7); +signal rel_up_way_addr_d :std_ulogic_vector(0 to 2); +signal rel_up_way_addr_q :std_ulogic_vector(0 to 2); +signal rel_dcarr_addr_en_d :std_ulogic; +signal rel_dcarr_addr_en_q :std_ulogic; +signal rel_dcarr_val_upd_d :std_ulogic; +signal rel_dcarr_val_upd_q :std_ulogic; +signal rel_lru_late_sel :std_ulogic; +signal rel_lru_late_stg_pri :std_ulogic_vector(0 to 6); +signal rel_lru_late_stg_arr :std_ulogic_vector(0 to 6); +signal lru_late_sel :std_ulogic; +signal lru_late_stg_pri :std_ulogic_vector(0 to 6); +signal lru_late_stg_arr :std_ulogic_vector(0 to 6); +signal lru_early_sel :std_ulogic_vector(0 to 6); +signal lru_early_sel_b :std_ulogic_vector(0 to 6); +signal rel_hit_lru_upd :std_ulogic_vector(0 to 6); +signal ldst_hit_vec_sel :std_ulogic; +signal ldst_hit_lru_upd :std_ulogic_vector(0 to 6); +signal rel_wlock_rmt :std_ulogic_vector(0 to 7); +signal congr_cl_act_d :std_ulogic; +signal congr_cl_act_q :std_ulogic; +signal rel2_mid_val_d :std_ulogic; +signal rel2_mid_val_q :std_ulogic; +signal relq_m_way_val :std_ulogic_vector(0 to 7); +signal rel_m_q_upd :std_ulogic; +signal rel_m_q_upd_way :std_ulogic_vector(0 to 7); +signal rel_m_q_upd_lock_way :std_ulogic_vector(0 to 7); +signal reld_q_early_sel :std_ulogic_vector(0 to 7); +signal rel_way_early_qsel :std_ulogic_vector(0 to 7); +signal rel_way_early_qsel_d :std_ulogic_vector(0 to 7); +signal rel_way_early_qsel_q :std_ulogic_vector(0 to 7); +signal rel_val_early_qsel :std_ulogic; +signal rel_val_early_qsel_d :std_ulogic; +signal rel_val_early_qsel_q :std_ulogic; +signal reld_q_early_byp :std_ulogic; +signal reld_way_early_byp :std_ulogic_vector(0 to 7); +signal reld_q_val :std_ulogic_vector(0 to 7); +signal ex4_fxubyp_val_d :std_ulogic; +signal ex4_fxubyp_val_q :std_ulogic; +signal ex4_relbyp_val_d :std_ulogic; +signal ex4_relbyp_val_q :std_ulogic; +signal ex4_lru_byp_sel :std_ulogic_vector(0 to 1); +signal rel2_fxubyp_val_d :std_ulogic; +signal rel2_fxubyp_val_q :std_ulogic; +signal rel2_relbyp_val_d :std_ulogic; +signal rel2_relbyp_val_q :std_ulogic; +signal rel2_lru_byp_sel :std_ulogic_vector(0 to 1); +signal tiup :std_ulogic; +signal siv :std_ulogic_vector(0 to scan_right); +signal sov :std_ulogic_vector(0 to scan_right); + BEGIN --@@ START OF EXECUTABLE CODE FOR XUQ_LSU_DIR_LRU32 + +-- #################################################### +-- Inputs +-- #################################################### +tiup <= '1'; +rel2_val_d <= rel1_val; +rel2_mid_val_d <= rel_mid_val; +rel4_retry_val_d <= rel_retry_val; +rel4_val_d <= rel3_val; +rel_tag_d <= rel_st_tag; +rel_class_id <= rel1_classid; +rel2_class_id_d <= rel_class_id; +rel2_lock_en_d <= rel_lock_en; +rel2_wayA_val <= rel_way_val_a; +rel2_wayB_val <= rel_way_val_b; +rel2_wayC_val <= rel_way_val_c; +rel2_wayD_val <= rel_way_val_d; +rel2_wayE_val <= rel_way_val_e; +rel2_wayF_val <= rel_way_val_f; +rel2_wayG_val <= rel_way_val_g; +rel2_wayH_val <= rel_way_val_h; +rel2_wayA_lock <= rel_way_lock_a; +rel2_wayB_lock <= rel_way_lock_b; +rel2_wayC_lock <= rel_way_lock_c; +rel2_wayD_lock <= rel_way_lock_d; +rel2_wayE_lock <= rel_way_lock_e; +rel2_wayF_lock <= rel_way_lock_f; +rel2_wayG_lock <= rel_way_lock_g; +rel2_wayH_lock <= rel_way_lock_h; +spr_rmt_table <= spr_xucr2_rmt; +ldst_wayA_hit <= ex4_way_a_hit; +ldst_wayB_hit <= ex4_way_b_hit; +ldst_wayC_hit <= ex4_way_c_hit; +ldst_wayD_hit <= ex4_way_d_hit; +ldst_wayE_hit <= ex4_way_e_hit; +ldst_wayF_hit <= ex4_way_f_hit; +ldst_wayG_hit <= ex4_way_g_hit; +ldst_wayH_hit <= ex4_way_h_hit; +ex3_l1hit <= ex3_hit; +ex3_no_lru_upd_d <= ex2_no_lru_upd; +ex3_flush <= ex3_stg_flush; +ex4_flush <= ex4_stg_flush; +ex5_flush <= ex5_stg_flush; +-- #################################################### +-- Dcache Number of Cachelines Configurations +-- #################################################### +ex1_congr_cl <= ex1_p_addr; +cl64size : if (cl_size=6) generate +begin + rel_early_congr_cl(2 TO 6) <= rel_addr_early(64-(dc_size-3) to 63-cl_size-1); +rel_early_congr_cl(7) <= rel_addr_early(63-cl_size) or spr_xucr0_cls; +end generate cl64size; +cl32size : if (cl_size=5) generate +begin + rel_early_congr_cl(2 TO 5) <= rel_addr_early(64-(dc_size-3) to 63-cl_size-2); +rel_early_congr_cl(6) <= rel_addr_early(63-cl_size-1) or spr_xucr0_cls; +rel_early_congr_cl(7) <= rel_addr_early(63-cl_size); +end generate cl32size; +rel_congr_cl_d <= rel_early_congr_cl; +ex2_congr_cl_d <= ex1_congr_cl; +ex3_congr_cl_d <= ex2_congr_cl_q; +ex4_congr_cl_d <= ex3_congr_cl_q; +ex5_congr_cl_d <= ex4_congr_cl_q; +ex6_congr_cl_d <= ex5_congr_cl_q; +-- #################################################### +-- Select Reload Congruence Class LRU +-- #################################################### +with rel_congr_cl_q select + rel_congr_cl_lru <= + congr_cl0_lru_q when "000000", + congr_cl1_lru_q when "000001", + congr_cl2_lru_q when "000010", + congr_cl3_lru_q when "000011", + congr_cl4_lru_q when "000100", + congr_cl5_lru_q when "000101", + congr_cl6_lru_q when "000110", + congr_cl7_lru_q when "000111", + congr_cl8_lru_q when "001000", + congr_cl9_lru_q when "001001", + congr_cl10_lru_q when "001010", + congr_cl11_lru_q when "001011", + congr_cl12_lru_q when "001100", + congr_cl13_lru_q when "001101", + congr_cl14_lru_q when "001110", + congr_cl15_lru_q when "001111", + congr_cl16_lru_q when "010000", + congr_cl17_lru_q when "010001", + congr_cl18_lru_q when "010010", + congr_cl19_lru_q when "010011", + congr_cl20_lru_q when "010100", + congr_cl21_lru_q when "010101", + congr_cl22_lru_q when "010110", + congr_cl23_lru_q when "010111", + congr_cl24_lru_q when "011000", + congr_cl25_lru_q when "011001", + congr_cl26_lru_q when "011010", + congr_cl27_lru_q when "011011", + congr_cl28_lru_q when "011100", + congr_cl29_lru_q when "011101", + congr_cl30_lru_q when "011110", + congr_cl31_lru_q when "011111", + congr_cl32_lru_q when "100000", + congr_cl33_lru_q when "100001", + congr_cl34_lru_q when "100010", + congr_cl35_lru_q when "100011", + congr_cl36_lru_q when "100100", + congr_cl37_lru_q when "100101", + congr_cl38_lru_q when "100110", + congr_cl39_lru_q when "100111", + congr_cl40_lru_q when "101000", + congr_cl41_lru_q when "101001", + congr_cl42_lru_q when "101010", + congr_cl43_lru_q when "101011", + congr_cl44_lru_q when "101100", + congr_cl45_lru_q when "101101", + congr_cl46_lru_q when "101110", + congr_cl47_lru_q when "101111", + congr_cl48_lru_q when "110000", + congr_cl49_lru_q when "110001", + congr_cl50_lru_q when "110010", + congr_cl51_lru_q when "110011", + congr_cl52_lru_q when "110100", + congr_cl53_lru_q when "110101", + congr_cl54_lru_q when "110110", + congr_cl55_lru_q when "110111", + congr_cl56_lru_q when "111000", + congr_cl57_lru_q when "111001", + congr_cl58_lru_q when "111010", + congr_cl59_lru_q when "111011", + congr_cl60_lru_q when "111100", + congr_cl61_lru_q when "111101", + congr_cl62_lru_q when "111110", + congr_cl63_lru_q when others; +p1_arr_lru_rd <= rel_congr_cl_lru; +-- REL1 Stage --> Bypass out of reload Queue +-- Need to merge outstanding reloads to same congruence class +-- Reload updating a way +rel_m_q_upd <= (rel_congr_cl_q = rel_congr_cl_stg_q) and rel2_val_q; +rel_m_q_upd_way <= gate(rel_hit_vec, rel_m_q_upd); +rel_m_q_upd_lock_way <= gate(rel_hit_vec, (rel_m_q_upd and rel2_lock_en_q)); +rel_m_q0 <= (rel_congr_cl_q = reld_q0_congr_cl_q) and reld_q0_val_q; +rel_m_q1 <= (rel_congr_cl_q = reld_q1_congr_cl_q) and reld_q1_val_q; +rel_m_q2 <= (rel_congr_cl_q = reld_q2_congr_cl_q) and reld_q2_val_q; +rel_m_q3 <= (rel_congr_cl_q = reld_q3_congr_cl_q) and reld_q3_val_q; +rel_m_q4 <= (rel_congr_cl_q = reld_q4_congr_cl_q) and reld_q4_val_q; +rel_m_q5 <= (rel_congr_cl_q = reld_q5_congr_cl_q) and reld_q5_val_q; +rel_m_q6 <= (rel_congr_cl_q = reld_q6_congr_cl_q) and reld_q6_val_q; +rel_m_q7 <= (rel_congr_cl_q = reld_q7_congr_cl_q) and reld_q7_val_q; +relq_m_way_val <= gate(reld_q0_way_q, rel_m_q0) or + gate(reld_q1_way_q, rel_m_q1) or + gate(reld_q2_way_q, rel_m_q2) or + gate(reld_q3_way_q, rel_m_q3) or + gate(reld_q4_way_q, rel_m_q4) or + gate(reld_q5_way_q, rel_m_q5) or + gate(reld_q6_way_q, rel_m_q6) or + gate(reld_q7_way_q, rel_m_q7); +relMQWayB: rel_m_q_way_b <= not (relq_m_way_val or rel_m_q_upd_way); +rel_m_q_way_d <= not rel_m_q_way_b; +rel_m_q_lock_way <= gate(gate(reld_q0_way_q, reld_q0_lock_q), rel_m_q0) or + gate(gate(reld_q1_way_q, reld_q1_lock_q), rel_m_q1) or + gate(gate(reld_q2_way_q, reld_q2_lock_q), rel_m_q2) or + gate(gate(reld_q3_way_q, reld_q3_lock_q), rel_m_q3) or + gate(gate(reld_q4_way_q, reld_q4_lock_q), rel_m_q4) or + gate(gate(reld_q5_way_q, reld_q5_lock_q), rel_m_q5) or + gate(gate(reld_q6_way_q, reld_q6_lock_q), rel_m_q6) or + gate(gate(reld_q7_way_q, reld_q7_lock_q), rel_m_q7) or + rel_wlock_rmt; +-- REL0 Stage --> Congruence Class Match +congr_cl_rel1_ex4_cmp_d <= (rel_early_congr_cl = ex3_congr_cl_q); +congr_cl_rel1_ex5_cmp_d <= (rel_early_congr_cl = ex4_congr_cl_q); +congr_cl_rel1_ex6_cmp_d <= (rel_early_congr_cl = ex5_congr_cl_q); +congr_cl_rel1_rel2_cmp_d <= (rel_early_congr_cl = rel_congr_cl_q); +congr_cl_rel1_relu_cmp_d <= (rel_early_congr_cl = rel_congr_cl_stg_q); +congr_cl_rel1_rel_upd_cmp_d <= (rel_early_congr_cl = relu_congr_cl_q); +-- REL1 Stage --> Bypass Logic +congr_cl_rel1_ex4_m <= congr_cl_rel1_ex4_cmp_q and ex4_c_acc; +congr_cl_rel1_ex5_m <= congr_cl_rel1_ex5_cmp_q and ex5_c_acc_q; +congr_cl_rel1_rel2_m <= congr_cl_rel1_rel2_cmp_q and rel2_val_q and not ovr_lock_det; +congr_cl_rel1_relu_m <= congr_cl_rel1_relu_cmp_q and relu_val_wen_q; +congr_cl_rel1_p0_m <= congr_cl_rel1_ex6_cmp_q and ex6_c_acc_val_q; +congr_cl_rel1_p1_m <= congr_cl_rel1_rel_upd_cmp_q and rel_val_wen_q; +-- Bypass REL1 select +congr_cl_rel1_byp(0) <= congr_cl_rel1_rel2_m; +congr_cl_rel1_byp(1) <= congr_cl_rel1_ex4_m; +congr_cl_rel1_byp(2) <= congr_cl_rel1_relu_m; +congr_cl_rel1_byp(3) <= congr_cl_rel1_ex5_m; +congr_cl_rel1_byp(4) <= congr_cl_rel1_p1_m; +congr_cl_rel1_byp(5) <= congr_cl_rel1_p0_m; +-- Bypass Pipe Valid +rel2_fxubyp_val_d <= congr_cl_rel1_byp(1) or congr_cl_rel1_byp(3) or congr_cl_rel1_byp(5); +rel2_relbyp_val_d <= congr_cl_rel1_byp(0) or congr_cl_rel1_byp(2) or congr_cl_rel1_byp(4); +rel2_lru_byp_sel <= rel2_fxubyp_val_q & rel2_relbyp_val_q; +congr_cl_rel1_sel(1) <= congr_cl_rel1_byp(1); +congr_cl_rel1_sel(2) <= congr_cl_rel1_byp(2) and not congr_cl_rel1_byp(1); +congr_cl_rel1_sel(3) <= congr_cl_rel1_byp(3) and not or_reduce(congr_cl_rel1_byp(1 to 2)); +congr_cl_rel1_sel(4) <= congr_cl_rel1_byp(4) and not or_reduce(congr_cl_rel1_byp(1 to 3)); +congr_cl_rel1_sel(5) <= congr_cl_rel1_byp(5) and not or_reduce(congr_cl_rel1_byp(1 to 4)); +-- Late Stage Priority Selection +rel_lru_late_sel <= or_reduce(congr_cl_rel1_byp(1 to 5)); +rel_lru_late_stg_pri <= gate(lru_upd, congr_cl_rel1_sel(1)) or + gate(relu_lru_upd_q, congr_cl_rel1_sel(2)) or + gate(ex5_lru_upd_q, congr_cl_rel1_sel(3)) or + gate(rel_lru_val_q, congr_cl_rel1_sel(4)) or + gate(ex6_lru_upd_q, congr_cl_rel1_sel(5)); +rel_lru_late_stg_arr <= gate(p1_arr_lru_rd, not rel_lru_late_sel) or rel_lru_late_stg_pri; +-- EX3/RELU/LATE Stage Priority Selection +rel_lru_early_sel <= (others=>congr_cl_rel1_byp(0)); +rel_lru_early_sel_b <= (others=>(not congr_cl_rel1_byp(0))); +-- Bypassed LRU for Reloads +rel_op_lru <= not rel_congr_cl_lru_b_q; +rel_congr_cl_stg_d <= rel_congr_cl_q; +relu_congr_cl_d <= rel_congr_cl_stg_q; +rel_upd_congr_cl_d <= relu_congr_cl_q; +relu_val_wen_d <= rel2_val_q and not ovr_lock_det; +rel_val_wen_d <= relu_val_wen_q; +rel_dcarr_addr_en_d <= rel2_val_q or (rel4_val_q and not rel4_retry_val_q) or rel2_mid_val_q; +-- #################################################### +-- Reload Path +-- #################################################### +-- Select which RMT table to use +with rel_class_id select + rel_wlock_rmt <= not spr_rmt_table(0 to 7) when "11", + not spr_rmt_table(8 to 15) when "10", + not spr_rmt_table(16 to 23) when "01", + not spr_rmt_table(24 to 31) when others; +rel1WlockB: rel1_wlock_b <= not (rel_m_q_upd_lock_way or rel_m_q_lock_way); +rel2_wlock_d <= not rel1_wlock_b; +-- Determine which way is locked +rel_lock_line(0) <= rel2_wayA_lock or rel2_wlock_q(0); +rel_lock_line(1) <= rel2_wayB_lock or rel2_wlock_q(1); +rel_lock_line(2) <= rel2_wayC_lock or rel2_wlock_q(2); +rel_lock_line(3) <= rel2_wayD_lock or rel2_wlock_q(3); +rel_lock_line(4) <= rel2_wayE_lock or rel2_wlock_q(4); +rel_lock_line(5) <= rel2_wayF_lock or rel2_wlock_q(5); +rel_lock_line(6) <= rel2_wayG_lock or rel2_wlock_q(6); +rel_lock_line(7) <= rel2_wayH_lock or rel2_wlock_q(7); +-- Override LRU, removing locked ways from replacement +-- Overlocking Detected, do not update Cache +ovr_lock_det <= rel_lock_line(0) and rel_lock_line(1) and rel_lock_line(2) and rel_lock_line(3) and + rel_lock_line(4) and rel_lock_line(5) and rel_lock_line(6) and rel_lock_line(7); +ovr_lock_det_wlkon <= ovr_lock_det and rel2_val_q; +ovr_lock_det_wlkoff <= ovr_lock_det and rel2_lock_en_q and rel2_val_q; +with spr_xucr0_wlck select + xucr0_clo_d <= ovr_lock_det_wlkon when '1', + ovr_lock_det_wlkoff when others; +-- LRU(0) +rel_ovrd_wayABCDEFGH <= (rel_lock_line(0) and rel_lock_line(1) and rel_lock_line(2) and rel_lock_line(3)) & + (rel_lock_line(4) and rel_lock_line(5) and rel_lock_line(6) and rel_lock_line(7)); +rel_ovrd_lru(0) <= (rel_op_lru(0) and not rel_ovrd_wayABCDEFGH(1)) or rel_ovrd_wayABCDEFGH(0); +-- LRU(1) +rel_ovrd_wayABCD <= (rel_lock_line(0) and rel_lock_line(1)) & (rel_lock_line(2) and rel_lock_line(3)); +rel_ovrd_lru(1) <= (rel_op_lru(1) and not rel_ovrd_wayABCD(1)) or rel_ovrd_wayABCD(0); +-- LRU(2) +rel_ovrd_wayEFGH <= (rel_lock_line(4) and rel_lock_line(5)) & (rel_lock_line(6) and rel_lock_line(7)); +rel_ovrd_lru(2) <= (rel_op_lru(2) and not rel_ovrd_wayEFGH(1)) or rel_ovrd_wayEFGH(0); +-- LRU(3) +rel_ovrd_wayAB <= rel_lock_line(0 to 1); +rel_ovrd_lru(3) <= (rel_op_lru(3) and not rel_ovrd_wayAB(1)) or rel_ovrd_wayAB(0); +-- LRU(4) +rel_ovrd_wayCD <= rel_lock_line(2 to 3); +rel_ovrd_lru(4) <= (rel_op_lru(4) and not rel_ovrd_wayCD(1)) or rel_ovrd_wayCD(0); +-- LRU(5) +rel_ovrd_wayEF <= rel_lock_line(4 to 5); +rel_ovrd_lru(5) <= (rel_op_lru(5) and not rel_ovrd_wayEF(1)) or rel_ovrd_wayEF(0); +-- LRU(6) +rel_ovrd_wayGH <= rel_lock_line(6 to 7); +rel_ovrd_lru(6) <= (rel_op_lru(6) and not rel_ovrd_wayGH(1)) or rel_ovrd_wayGH(0); +-- Using LRU to determine which way will be updated +full_way(0) <= not rel_ovrd_lru(0) and not rel_ovrd_lru(1) and not rel_ovrd_lru(3); +full_way(1) <= not rel_ovrd_lru(0) and not rel_ovrd_lru(1) and rel_ovrd_lru(3); +full_way(2) <= not rel_ovrd_lru(0) and rel_ovrd_lru(1) and not rel_ovrd_lru(4); +full_way(3) <= not rel_ovrd_lru(0) and rel_ovrd_lru(1) and rel_ovrd_lru(4); +full_way(4) <= rel_ovrd_lru(0) and not rel_ovrd_lru(2) and not rel_ovrd_lru(5); +full_way(5) <= rel_ovrd_lru(0) and not rel_ovrd_lru(2) and rel_ovrd_lru(5); +full_way(6) <= rel_ovrd_lru(0) and rel_ovrd_lru(2) and not rel_ovrd_lru(6); +full_way(7) <= rel_ovrd_lru(0) and rel_ovrd_lru(2) and rel_ovrd_lru(6); +--?TABLE tbl_rel_lru LISTING(final) OPTIMIZE PARMS(OFF-SET); +--*INPUTS*====================*OUTPUTS*==========* +--| | | +--| rel_lock_line | | +--| | rel_op_lru | full_way | +--| | | | | | +--| | | | | | +--| 01234567 0123456 | 01234567 | +--*TYPE*======================+==================+ +--| ........ ....... | ........ | +--*PHASE*-------------------->| CCCCCCCC | +--*TERMS*=====================+==================+ +--| 0....... 00.0... | 10000000 | WayA -- no locks +--| .0...... 00.1... | 01000000 | WayB +--| ..0..... 01..0.. | 00100000 | WayC +--| ...0.... 01..1.. | 00010000 | WayD +--| ....0... 1.0..0. | 00001000 | WayE +--| .....0.. 1.0..1. | 00000100 | WayF +--| ......0. 1.1...0 | 00000010 | WayG +--| .......0 1.1...1 | 00000001 | WayH +--| 10...... 00..... | 01000000 | WayB -- 1 lock +--| 01...... 00..... | 10000000 | WayA +--| ..10.... 01..... | 00010000 | WayD +--| ..01.... 01..... | 00100000 | WayC +--| ....10.. 1.0.... | 00000100 | WayF +--| ....01.. 1.0.... | 00001000 | WayE +--| ......10 1.1.... | 00000001 | WayH +--| ......01 1.1.... | 00000010 | WayG +--| 110..... 00..0.. | 00100000 | WayC -- 2 locks +--| 11.0.... 00..1.. | 00010000 | WayD +--| 0.11.... 01.0... | 10000000 | WayA +--| .011.... 01.1... | 01000000 | WayB +--| ....110. 1.0...0 | 00000010 | WayG +--| ....11.0 1.0...1 | 00000001 | WayH +--| ....0.11 1.1..0. | 00001000 | WayE +--| .....011 1.1..1. | 00000100 | WayF +--| 1110.... 00..... | 00010000 | WayD -- 3 locks +--| 1101.... 00..... | 00100000 | WayC +--| 1011.... 01..... | 01000000 | WayB +--| 0111.... 01..... | 10000000 | WayA +--| ....1110 1.0.... | 00000001 | WayH +--| ....1101 1.0.... | 00000010 | WayG +--| ....1011 1.1.... | 00000100 | WayF +--| ....0111 1.1.... | 00001000 | WayE +--| 11110... ..0..0. | 00001000 | WayE -- 4 locks +--| 1111.0.. ..0..1. | 00000100 | WayF +--| 1111..0. ..1...0 | 00000010 | WayG +--| 1111...0 ..1...1 | 00000001 | WayH +--| 0...1111 .0.0... | 10000000 | WayA +--| .0..1111 .0.1... | 01000000 | WayB +--| ..0.1111 .1..0.. | 00100000 | WayC +--| ...01111 .1..1.. | 00010000 | WayD +--| 111110.. ..0.... | 00000100 | WayF -- 5 locks +--| 111101.. ..0.... | 00001000 | WayE +--| 1111..10 ..1.... | 00000001 | WayH +--| 1111..01 ..1.... | 00000010 | WayG +--| 10..1111 .0..... | 01000000 | WayB +--| 01..1111 .0..... | 10000000 | WayA +--| ..101111 .1..... | 00010000 | WayD +--| ..011111 .1..... | 00100000 | WayC +--| 1111110. ......0 | 00000010 | WayG -- 6 locks +--| 111111.0 ......1 | 00000001 | WayH +--| 11110.11 .....0. | 00001000 | WayE +--| 1111.011 .....1. | 00000100 | WayF +--| 110.1111 ....0.. | 00100000 | WayC +--| 11.01111 ....1.. | 00010000 | WayD +--| 0.111111 ...0... | 10000000 | WayA +--| .0111111 ...1... | 01000000 | WayB +--| 11111101 ....... | 00000010 | WayG -- 7 locks +--| 11111110 ....... | 00000001 | WayH +--| 11110111 ....... | 00001000 | WayE +--| 11111011 ....... | 00000100 | WayF +--| 11011111 ....... | 00100000 | WayC +--| 11101111 ....... | 00010000 | WayD +--| 01111111 ....... | 10000000 | WayA +--| 10111111 ....... | 01000000 | WayB +--*END*=======================+==================+ +--?TABLE END tbl_rel_lru ; +-- Not Empty way is a valid Way or locked way or reload way in queue +wayA_not_empty <= rel2_wayA_val or rel2_wlock_q(0) or rel_m_q_way_q(0); +wayB_not_empty <= rel2_wayB_val or rel2_wlock_q(1) or rel_m_q_way_q(1); +wayC_not_empty <= rel2_wayC_val or rel2_wlock_q(2) or rel_m_q_way_q(2); +wayD_not_empty <= rel2_wayD_val or rel2_wlock_q(3) or rel_m_q_way_q(3); +wayE_not_empty <= rel2_wayE_val or rel2_wlock_q(4) or rel_m_q_way_q(4); +wayF_not_empty <= rel2_wayF_val or rel2_wlock_q(5) or rel_m_q_way_q(5); +wayG_not_empty <= rel2_wayG_val or rel2_wlock_q(6) or rel_m_q_way_q(6); +wayH_not_empty <= rel2_wayH_val or rel2_wlock_q(7) or rel_m_q_way_q(7); +rel_way_not_empty_d <= wayA_not_empty & wayB_not_empty & wayC_not_empty & wayD_not_empty & + wayE_not_empty & wayF_not_empty & wayG_not_empty & wayH_not_empty; +-- Pseudo LRU needs to be used if all ways contain valid data +congr_cl_full <= wayA_not_empty and wayB_not_empty and wayC_not_empty and wayD_not_empty and + wayE_not_empty and wayF_not_empty and wayG_not_empty and wayH_not_empty; +-- Need to select which non-valid way needs updating, Using leftmost empty Way +empty_way(0) <= not wayA_not_empty; +empty_way(1) <= ( wayA_not_empty and not wayB_not_empty); +empty_way(2) <= ( wayA_not_empty and wayB_not_empty and not wayC_not_empty); +empty_way(3) <= ( wayA_not_empty and wayB_not_empty and wayC_not_empty and not wayD_not_empty); +empty_way(4) <= ( wayA_not_empty and wayB_not_empty and wayC_not_empty and wayD_not_empty and + not wayE_not_empty); +empty_way(5) <= ( wayA_not_empty and wayB_not_empty and wayC_not_empty and wayD_not_empty and + wayE_not_empty and not wayF_not_empty); +empty_way(6) <= ( wayA_not_empty and wayB_not_empty and wayC_not_empty and wayD_not_empty and + wayE_not_empty and wayF_not_empty and not wayG_not_empty); +empty_way(7) <= ( wayA_not_empty and wayB_not_empty and wayC_not_empty and wayD_not_empty and + wayE_not_empty and wayF_not_empty and wayG_not_empty); +-- Selecting between using LRU or Fill in the Empty Ways +rel_hit <= gate(empty_way, not congr_cl_full) or gate(full_way, congr_cl_full); +-- Way that will be updating is determined by the current LRU +-- Dont want to update the directory or the D$ if we have all ways locked in the same congruence class +rel_wayA_clr <= rel_hit(0) and rel2_val_q and not ovr_lock_det; +rel_wayB_clr <= rel_hit(1) and rel2_val_q and not ovr_lock_det; +rel_wayC_clr <= rel_hit(2) and rel2_val_q and not ovr_lock_det; +rel_wayD_clr <= rel_hit(3) and rel2_val_q and not ovr_lock_det; +rel_wayE_clr <= rel_hit(4) and rel2_val_q and not ovr_lock_det; +rel_wayF_clr <= rel_hit(5) and rel2_val_q and not ovr_lock_det; +rel_wayG_clr <= rel_hit(6) and rel2_val_q and not ovr_lock_det; +rel_wayH_clr <= rel_hit(7) and rel2_val_q and not ovr_lock_det; +rel_hit_vec <= rel_wayA_clr & rel_wayB_clr & rel_wayC_clr & rel_wayD_clr & + rel_wayE_clr & rel_wayF_clr & rel_wayG_clr & rel_wayH_clr; +-- #################################################### +-- LRU update calculation due to a Reload +-- #################################################### +-- Locking Enabled +-- Updating the LRU using the Way that is being reloaded as the Way hit +rel_hit_wayA_upd <= "11" & rel_ovrd_lru(2) & "1" & rel_ovrd_lru(4 to 6); +rel_hit_wayB_upd <= "11" & rel_ovrd_lru(2) & "0" & rel_ovrd_lru(4 to 6); +rel_hit_wayC_upd <= "10" & rel_ovrd_lru(2 to 3) & "1" & rel_ovrd_lru(5 to 6); +rel_hit_wayD_upd <= "10" & rel_ovrd_lru(2 to 3) & "0" & rel_ovrd_lru(5 to 6); +rel_hit_wayE_upd <= "0" & rel_ovrd_lru(1) & "1" & rel_ovrd_lru(3 to 4) & "1" & rel_ovrd_lru(6); +rel_hit_wayF_upd <= "0" & rel_ovrd_lru(1) & "1" & rel_ovrd_lru(3 to 4) & "0" & rel_ovrd_lru(6); +rel_hit_wayG_upd <= "0" & rel_ovrd_lru(1) & "0" & rel_ovrd_lru(3 to 5) & "1"; +rel_hit_wayh_upd <= "0" & rel_ovrd_lru(1) & "0" & rel_ovrd_lru(3 to 5) & "0"; +-- #################################################### +-- Selecting which calculated LRU to update with +-- #################################################### +-- Selecting Way Hit Updated LRU +rel_hit_lru_upd <= gate(rel_hit_wayA_upd, rel_hit_vec(0)) or gate(rel_hit_wayB_upd, rel_hit_vec(1)) or + gate(rel_hit_wayC_upd, rel_hit_vec(2)) or gate(rel_hit_wayD_upd, rel_hit_vec(3)) or + gate(rel_hit_wayE_upd, rel_hit_vec(4)) or gate(rel_hit_wayF_upd, rel_hit_vec(5)) or + gate(rel_hit_wayG_upd, rel_hit_vec(6)) or gate(rel_hit_wayH_upd, rel_hit_vec(7)); +relu_lru_upd_d <= rel_hit_lru_upd; +rel_lru_val_d <= relu_lru_upd_q; +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Small Reload Way Enable Queue to Handle Beats with Gaps +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Write Enable Logic for Reload Q0 +reld_q0_chk_val <= (reld_q0_congr_cl_q = rel_congr_cl_stg_q) and reld_q0_val_q and rel2_val_q and not ovr_lock_det; +reld_q0_chk_way <= gate(reld_q0_way_q, reld_q0_chk_val); +reld_q0_way_m <= or_reduce((reld_q0_chk_way and rel_hit)); +reld_match(0) <= reld_q0_way_m; +reld_q0_set <= rel2_val_q and (rel_tag_q = tconv(0,3)); +reld_q0_inval <= (rel4_val_q and (not rel4_recirc_val or rel4_ecc_err) and reld_q_sel_q(0)) or reld_match(0); +reld_q0_val_sel <= reld_q0_set & reld_q0_inval; +-- Congruence Class +with reld_q0_set select + reld_q0_congr_cl_d <= rel_congr_cl_stg_q when '1', + reld_q0_congr_cl_q when others; +-- Reload Way +with reld_q0_set select + reld_q0_way_d <= rel_hit_vec when '1', + reld_q0_way_q when others; +-- Valid +with reld_q0_val_sel select + reld_q0_val_d <= '0' when "01", + reld_q0_val_q when "00", + '1' when others; +reld_q_val(0) <= reld_q0_val_q; +-- Lock Bit +with reld_q0_val_sel select + reld_q0_lock_d <= '0' when "01", + reld_q0_lock_q when "00", + rel2_lock_en_q when others; +-- Reload Queue Early Select +reld_q_early_sel(0) <= (rel_st_tag_early = tconv(0,3)); +-- Reload Queue Select +reld_q_sel_d(0) <= (rel_st_tag = tconv(0,3)); +-- Write Enable Logic for Reload Q1 +reld_q1_chk_val <= (reld_q1_congr_cl_q = rel_congr_cl_stg_q) and reld_q1_val_q and rel2_val_q and not ovr_lock_det; +reld_q1_chk_way <= gate(reld_q1_way_q, reld_q1_chk_val); +reld_q1_way_m <= or_reduce((reld_q1_chk_way and rel_hit)); +reld_match(1) <= reld_q1_way_m; +reld_q1_set <= rel2_val_q and (rel_tag_q = tconv(1,3)); +reld_q1_inval <= (rel4_val_q and (not rel4_recirc_val or rel4_ecc_err) and reld_q_sel_q(1)) or reld_match(1); +reld_q1_val_sel <= reld_q1_set & reld_q1_inval; +-- Congruence Class +with reld_q1_set select + reld_q1_congr_cl_d <= rel_congr_cl_stg_q when '1', + reld_q1_congr_cl_q when others; +-- Reload Way +with reld_q1_set select + reld_q1_way_d <= rel_hit_vec when '1', + reld_q1_way_q when others; +-- Valid +with reld_q1_val_sel select + reld_q1_val_d <= '0' when "01", + reld_q1_val_q when "00", + '1' when others; +reld_q_val(1) <= reld_q1_val_q; +-- Lock Bit +with reld_q1_val_sel select + reld_q1_lock_d <= '0' when "01", + reld_q1_lock_q when "00", + rel2_lock_en_q when others; +-- Reload Queue Early Select +reld_q_early_sel(1) <= (rel_st_tag_early = tconv(1,3)); +-- Reload Queue Select +reld_q_sel_d(1) <= (rel_st_tag = tconv(1,3)); +-- Write Enable Logic for Reload Q2 +reld_q2_chk_val <= (reld_q2_congr_cl_q = rel_congr_cl_stg_q) and reld_q2_val_q and rel2_val_q and not ovr_lock_det; +reld_q2_chk_way <= gate(reld_q2_way_q, reld_q2_chk_val); +reld_q2_way_m <= or_reduce((reld_q2_chk_way and rel_hit)); +reld_match(2) <= reld_q2_way_m; +reld_q2_set <= rel2_val_q and (rel_tag_q = tconv(2,3)); +reld_q2_inval <= (rel4_val_q and (not rel4_recirc_val or rel4_ecc_err) and reld_q_sel_q(2)) or reld_match(2); +reld_q2_val_sel <= reld_q2_set & reld_q2_inval; +-- Congruence Class +with reld_q2_set select + reld_q2_congr_cl_d <= rel_congr_cl_stg_q when '1', + reld_q2_congr_cl_q when others; +-- Reload Way +with reld_q2_set select + reld_q2_way_d <= rel_hit_vec when '1', + reld_q2_way_q when others; +-- Valid +with reld_q2_val_sel select + reld_q2_val_d <= '0' when "01", + reld_q2_val_q when "00", + '1' when others; +reld_q_val(2) <= reld_q2_val_q; +-- Lock Bit +with reld_q2_val_sel select + reld_q2_lock_d <= '0' when "01", + reld_q2_lock_q when "00", + rel2_lock_en_q when others; +-- Reload Queue Early Select +reld_q_early_sel(2) <= (rel_st_tag_early = tconv(2,3)); +-- Reload Queue Select +reld_q_sel_d(2) <= (rel_st_tag = tconv(2,3)); +-- Write Enable Logic for Reload Q3 +reld_q3_chk_val <= (reld_q3_congr_cl_q = rel_congr_cl_stg_q) and reld_q3_val_q and rel2_val_q and not ovr_lock_det; +reld_q3_chk_way <= gate(reld_q3_way_q, reld_q3_chk_val); +reld_q3_way_m <= or_reduce((reld_q3_chk_way and rel_hit)); +reld_match(3) <= reld_q3_way_m; +reld_q3_set <= rel2_val_q and (rel_tag_q = tconv(3,3)); +reld_q3_inval <= (rel4_val_q and (not rel4_recirc_val or rel4_ecc_err) and reld_q_sel_q(3)) or reld_match(3); +reld_q3_val_sel <= reld_q3_set & reld_q3_inval; +-- Congruence Class +with reld_q3_set select + reld_q3_congr_cl_d <= rel_congr_cl_stg_q when '1', + reld_q3_congr_cl_q when others; +-- Reload Way +with reld_q3_set select + reld_q3_way_d <= rel_hit_vec when '1', + reld_q3_way_q when others; +-- Valid +with reld_q3_val_sel select + reld_q3_val_d <= '0' when "01", + reld_q3_val_q when "00", + '1' when others; +reld_q_val(3) <= reld_q3_val_q; +-- Lock Bit +with reld_q3_val_sel select + reld_q3_lock_d <= '0' when "01", + reld_q3_lock_q when "00", + rel2_lock_en_q when others; +-- Reload Queue Early Select +reld_q_early_sel(3) <= (rel_st_tag_early = tconv(3,3)); +-- Reload Queue Select +reld_q_sel_d(3) <= (rel_st_tag = tconv(3,3)); +-- Write Enable Logic for Reload Q4 +reld_q4_chk_val <= (reld_q4_congr_cl_q = rel_congr_cl_stg_q) and reld_q4_val_q and rel2_val_q and not ovr_lock_det; +reld_q4_chk_way <= gate(reld_q4_way_q, reld_q4_chk_val); +reld_q4_way_m <= or_reduce((reld_q4_chk_way and rel_hit)); +reld_match(4) <= reld_q4_way_m; +reld_q4_set <= rel2_val_q and (rel_tag_q = tconv(4,3)); +reld_q4_inval <= (rel4_val_q and (not rel4_recirc_val or rel4_ecc_err) and reld_q_sel_q(4)) or reld_match(4); +reld_q4_val_sel <= reld_q4_set & reld_q4_inval; +-- Congruence Class +with reld_q4_set select + reld_q4_congr_cl_d <= rel_congr_cl_stg_q when '1', + reld_q4_congr_cl_q when others; +-- Reload Way +with reld_q4_set select + reld_q4_way_d <= rel_hit_vec when '1', + reld_q4_way_q when others; +-- Valid +with reld_q4_val_sel select + reld_q4_val_d <= '0' when "01", + reld_q4_val_q when "00", + '1' when others; +reld_q_val(4) <= reld_q4_val_q; +-- Lock Bit +with reld_q4_val_sel select + reld_q4_lock_d <= '0' when "01", + reld_q4_lock_q when "00", + rel2_lock_en_q when others; +-- Reload Queue Early Select +reld_q_early_sel(4) <= (rel_st_tag_early = tconv(4,3)); +-- Reload Queue Select +reld_q_sel_d(4) <= (rel_st_tag = tconv(4,3)); +-- Write Enable Logic for Reload Q5 +reld_q5_chk_val <= (reld_q5_congr_cl_q = rel_congr_cl_stg_q) and reld_q5_val_q and rel2_val_q and not ovr_lock_det; +reld_q5_chk_way <= gate(reld_q5_way_q, reld_q5_chk_val); +reld_q5_way_m <= or_reduce((reld_q5_chk_way and rel_hit)); +reld_match(5) <= reld_q5_way_m; +reld_q5_set <= rel2_val_q and (rel_tag_q = tconv(5,3)); +reld_q5_inval <= (rel4_val_q and (not rel4_recirc_val or rel4_ecc_err) and reld_q_sel_q(5)) or reld_match(5); +reld_q5_val_sel <= reld_q5_set & reld_q5_inval; +-- Congruence Class +with reld_q5_set select + reld_q5_congr_cl_d <= rel_congr_cl_stg_q when '1', + reld_q5_congr_cl_q when others; +-- Reload Way +with reld_q5_set select + reld_q5_way_d <= rel_hit_vec when '1', + reld_q5_way_q when others; +-- Valid +with reld_q5_val_sel select + reld_q5_val_d <= '0' when "01", + reld_q5_val_q when "00", + '1' when others; +reld_q_val(5) <= reld_q5_val_q; +-- Lock Bit +with reld_q5_val_sel select + reld_q5_lock_d <= '0' when "01", + reld_q5_lock_q when "00", + rel2_lock_en_q when others; +-- Reload Queue Early Select +reld_q_early_sel(5) <= (rel_st_tag_early = tconv(5,3)); +-- Reload Queue Select +reld_q_sel_d(5) <= (rel_st_tag = tconv(5,3)); +-- Write Enable Logic for Reload Q6 +reld_q6_chk_val <= (reld_q6_congr_cl_q = rel_congr_cl_stg_q) and reld_q6_val_q and rel2_val_q and not ovr_lock_det; +reld_q6_chk_way <= gate(reld_q6_way_q, reld_q6_chk_val); +reld_q6_way_m <= or_reduce((reld_q6_chk_way and rel_hit)); +reld_match(6) <= reld_q6_way_m; +reld_q6_set <= rel2_val_q and (rel_tag_q = tconv(6,3)); +reld_q6_inval <= (rel4_val_q and (not rel4_recirc_val or rel4_ecc_err) and reld_q_sel_q(6)) or reld_match(6); +reld_q6_val_sel <= reld_q6_set & reld_q6_inval; +-- Congruence Class +with reld_q6_set select + reld_q6_congr_cl_d <= rel_congr_cl_stg_q when '1', + reld_q6_congr_cl_q when others; +-- Reload Way +with reld_q6_set select + reld_q6_way_d <= rel_hit_vec when '1', + reld_q6_way_q when others; +-- Valid +with reld_q6_val_sel select + reld_q6_val_d <= '0' when "01", + reld_q6_val_q when "00", + '1' when others; +reld_q_val(6) <= reld_q6_val_q; +-- Lock Bit +with reld_q6_val_sel select + reld_q6_lock_d <= '0' when "01", + reld_q6_lock_q when "00", + rel2_lock_en_q when others; +-- Reload Queue Early Select +reld_q_early_sel(6) <= (rel_st_tag_early = tconv(6,3)); +-- Reload Queue Select +reld_q_sel_d(6) <= (rel_st_tag = tconv(6,3)); +-- Write Enable Logic for Reload Q7 +reld_q7_chk_val <= (reld_q7_congr_cl_q = rel_congr_cl_stg_q) and reld_q7_val_q and rel2_val_q and not ovr_lock_det; +reld_q7_chk_way <= gate(reld_q7_way_q, reld_q7_chk_val); +reld_q7_way_m <= or_reduce((reld_q7_chk_way and rel_hit)); +reld_match(7) <= reld_q7_way_m; +reld_q7_set <= rel2_val_q and (rel_tag_q = tconv(7,3)); +reld_q7_inval <= (rel4_val_q and (not rel4_recirc_val or rel4_ecc_err) and reld_q_sel_q(7)) or reld_match(7); +reld_q7_val_sel <= reld_q7_set & reld_q7_inval; +-- Congruence Class +with reld_q7_set select + reld_q7_congr_cl_d <= rel_congr_cl_stg_q when '1', + reld_q7_congr_cl_q when others; +-- Reload Way +with reld_q7_set select + reld_q7_way_d <= rel_hit_vec when '1', + reld_q7_way_q when others; +-- Valid +with reld_q7_val_sel select + reld_q7_val_d <= '0' when "01", + reld_q7_val_q when "00", + '1' when others; +reld_q_val(7) <= reld_q7_val_q; +-- Lock Bit +with reld_q7_val_sel select + reld_q7_lock_d <= '0' when "01", + reld_q7_lock_q when "00", + rel2_lock_en_q when others; +-- Reload Queue Early Select +reld_q_early_sel(7) <= (rel_st_tag_early = tconv(7,3)); +-- Reload Queue Select +reld_q_sel_d(7) <= (rel_st_tag = tconv(7,3)); +-- Select Way and Valid +rel_way_early_qsel <= gate(reld_q0_way_q, reld_q_early_sel(0)) or + gate(reld_q1_way_q, reld_q_early_sel(1)) or + gate(reld_q2_way_q, reld_q_early_sel(2)) or + gate(reld_q3_way_q, reld_q_early_sel(3)) or + gate(reld_q4_way_q, reld_q_early_sel(4)) or + gate(reld_q5_way_q, reld_q_early_sel(5)) or + gate(reld_q6_way_q, reld_q_early_sel(6)) or + gate(reld_q7_way_q, reld_q_early_sel(7)); +rel_val_early_qsel <= (reld_q0_val_q and reld_q_early_sel(0)) or + (reld_q1_val_q and reld_q_early_sel(1)) or + (reld_q2_val_q and reld_q_early_sel(2)) or + (reld_q3_val_q and reld_q_early_sel(3)) or + (reld_q4_val_q and reld_q_early_sel(4)) or + (reld_q5_val_q and reld_q_early_sel(5)) or + (reld_q6_val_q and reld_q_early_sel(6)) or + (reld_q7_val_q and reld_q_early_sel(7)); +-- Small Bypass of Reload Clr update +reld_q_early_byp <= (rel_st_tag_early = rel_tag_q) and rel2_val_q; +reld_way_early_byp <= rel_hit_vec; +rel_way_early_qsel_d <= gate(rel_way_early_qsel, not reld_q_early_byp) or gate(reld_way_early_byp, reld_q_early_byp); +rel_val_early_qsel_d <= rel_val_early_qsel or reld_q_early_byp; +-- Select Way and Valid +rel_way_qsel_d <= gate(reld_q0_way_q, reld_q_sel_d(0)) or + gate(reld_q1_way_q, reld_q_sel_d(1)) or + gate(reld_q2_way_q, reld_q_sel_d(2)) or + gate(reld_q3_way_q, reld_q_sel_d(3)) or + gate(reld_q4_way_q, reld_q_sel_d(4)) or + gate(reld_q5_way_q, reld_q_sel_d(5)) or + gate(reld_q6_way_q, reld_q_sel_d(6)) or + gate(reld_q7_way_q, reld_q_sel_d(7)); +rel_val_qsel_d <= (reld_q0_val_q and reld_q_sel_d(0) and not reld_match(0)) or + (reld_q1_val_q and reld_q_sel_d(1) and not reld_match(1)) or + (reld_q2_val_q and reld_q_sel_d(2) and not reld_match(2)) or + (reld_q3_val_q and reld_q_sel_d(3) and not reld_match(3)) or + (reld_q4_val_q and reld_q_sel_d(4) and not reld_match(4)) or + (reld_q5_val_q and reld_q_sel_d(5) and not reld_match(5)) or + (reld_q6_val_q and reld_q_sel_d(6) and not reld_match(6)) or + (reld_q7_val_q and reld_q_sel_d(7) and not reld_match(7)); +-- Reload Way Upd Directory +rel_wayA_upd <= rel_way_early_qsel_q(0) and rel_val_early_qsel_q; +rel_wayB_upd <= rel_way_early_qsel_q(1) and rel_val_early_qsel_q; +rel_wayC_upd <= rel_way_early_qsel_q(2) and rel_val_early_qsel_q; +rel_wayD_upd <= rel_way_early_qsel_q(3) and rel_val_early_qsel_q; +rel_wayE_upd <= rel_way_early_qsel_q(4) and rel_val_early_qsel_q; +rel_wayF_upd <= rel_way_early_qsel_q(5) and rel_val_early_qsel_q; +rel_wayG_upd <= rel_way_early_qsel_q(6) and rel_val_early_qsel_q; +rel_wayH_upd <= rel_way_early_qsel_q(7) and rel_val_early_qsel_q; +-- Reload Way Set +rel_wayA_set <= rel_way_qsel_q(0) and rel4_val_q and rel_val_qsel_q; +rel_wayB_set <= rel_way_qsel_q(1) and rel4_val_q and rel_val_qsel_q; +rel_wayC_set <= rel_way_qsel_q(2) and rel4_val_q and rel_val_qsel_q; +rel_wayD_set <= rel_way_qsel_q(3) and rel4_val_q and rel_val_qsel_q; +rel_wayE_set <= rel_way_qsel_q(4) and rel4_val_q and rel_val_qsel_q; +rel_wayF_set <= rel_way_qsel_q(5) and rel4_val_q and rel_val_qsel_q; +rel_wayG_set <= rel_way_qsel_q(6) and rel4_val_q and rel_val_qsel_q; +rel_wayH_set <= rel_way_qsel_q(7) and rel4_val_q and rel_val_qsel_q; +-- Reload Middle Data Valid +rel_wayA_mid <= rel_way_qsel_q(0) and rel2_mid_val_q and rel_val_qsel_q; +rel_wayB_mid <= rel_way_qsel_q(1) and rel2_mid_val_q and rel_val_qsel_q; +rel_wayC_mid <= rel_way_qsel_q(2) and rel2_mid_val_q and rel_val_qsel_q; +rel_wayD_mid <= rel_way_qsel_q(3) and rel2_mid_val_q and rel_val_qsel_q; +rel_wayE_mid <= rel_way_qsel_q(4) and rel2_mid_val_q and rel_val_qsel_q; +rel_wayF_mid <= rel_way_qsel_q(5) and rel2_mid_val_q and rel_val_qsel_q; +rel_wayG_mid <= rel_way_qsel_q(6) and rel2_mid_val_q and rel_val_qsel_q; +rel_wayH_mid <= rel_way_qsel_q(7) and rel2_mid_val_q and rel_val_qsel_q; +-- #################################################### +-- Select XU Operation Congruence Class LRU +-- #################################################### +with ex3_congr_cl_q select + arr_congr_cl_lru <= + congr_cl0_lru_q when "000000", + congr_cl1_lru_q when "000001", + congr_cl2_lru_q when "000010", + congr_cl3_lru_q when "000011", + congr_cl4_lru_q when "000100", + congr_cl5_lru_q when "000101", + congr_cl6_lru_q when "000110", + congr_cl7_lru_q when "000111", + congr_cl8_lru_q when "001000", + congr_cl9_lru_q when "001001", + congr_cl10_lru_q when "001010", + congr_cl11_lru_q when "001011", + congr_cl12_lru_q when "001100", + congr_cl13_lru_q when "001101", + congr_cl14_lru_q when "001110", + congr_cl15_lru_q when "001111", + congr_cl16_lru_q when "010000", + congr_cl17_lru_q when "010001", + congr_cl18_lru_q when "010010", + congr_cl19_lru_q when "010011", + congr_cl20_lru_q when "010100", + congr_cl21_lru_q when "010101", + congr_cl22_lru_q when "010110", + congr_cl23_lru_q when "010111", + congr_cl24_lru_q when "011000", + congr_cl25_lru_q when "011001", + congr_cl26_lru_q when "011010", + congr_cl27_lru_q when "011011", + congr_cl28_lru_q when "011100", + congr_cl29_lru_q when "011101", + congr_cl30_lru_q when "011110", + congr_cl31_lru_q when "011111", + congr_cl32_lru_q when "100000", + congr_cl33_lru_q when "100001", + congr_cl34_lru_q when "100010", + congr_cl35_lru_q when "100011", + congr_cl36_lru_q when "100100", + congr_cl37_lru_q when "100101", + congr_cl38_lru_q when "100110", + congr_cl39_lru_q when "100111", + congr_cl40_lru_q when "101000", + congr_cl41_lru_q when "101001", + congr_cl42_lru_q when "101010", + congr_cl43_lru_q when "101011", + congr_cl44_lru_q when "101100", + congr_cl45_lru_q when "101101", + congr_cl46_lru_q when "101110", + congr_cl47_lru_q when "101111", + congr_cl48_lru_q when "110000", + congr_cl49_lru_q when "110001", + congr_cl50_lru_q when "110010", + congr_cl51_lru_q when "110011", + congr_cl52_lru_q when "110100", + congr_cl53_lru_q when "110101", + congr_cl54_lru_q when "110110", + congr_cl55_lru_q when "110111", + congr_cl56_lru_q when "111000", + congr_cl57_lru_q when "111001", + congr_cl58_lru_q when "111010", + congr_cl59_lru_q when "111011", + congr_cl60_lru_q when "111100", + congr_cl61_lru_q when "111101", + congr_cl62_lru_q when "111110", + congr_cl63_lru_q when others; +p0_arr_lru_rd <= arr_congr_cl_lru; +-- #################################################### +-- Execution Path +-- #################################################### +-- access is valid if its a cache_enabled op and not flushed or not a dcbt instruction +ex3_c_acc_val <= ex3_cache_en and not (ex3_no_lru_upd_q or spr_xucr0_dcdis or ex3_flush); +ex4_hit_d <= ex3_l1hit; +ex4_c_acc_d <= ex3_c_acc_val; +ex4_c_acc <= ex4_c_acc_q and ex4_hit_q; +ex4_c_acc_val <= ex4_c_acc and not ex4_flush; +ex5_c_acc_d <= ex4_c_acc_val; +ex5_c_acc_val <= ex5_c_acc_q and not ex5_flush; +ex6_c_acc_val_d <= ex5_c_acc_val; +-- EX2 Stage --> Congruence Class Match +congr_cl_ex3_ex4_cmp_d <= (ex2_congr_cl_q = ex3_congr_cl_q); +congr_cl_ex3_ex5_cmp_d <= (ex2_congr_cl_q = ex4_congr_cl_q); +congr_cl_ex3_ex6_cmp_d <= (ex2_congr_cl_q = ex5_congr_cl_q); +congr_cl_ex3_rel2_cmp_d <= (ex2_congr_cl_q = rel_congr_cl_q); +congr_cl_ex3_rel_upd_cmp_d <= (ex2_congr_cl_q = relu_congr_cl_q); +-- EX3 Stage --> Bypass Logic +congr_cl_ex3_ex4_m <= congr_cl_ex3_ex4_cmp_q and ex4_c_acc; +congr_cl_ex3_ex5_m <= congr_cl_ex3_ex5_cmp_q and ex5_c_acc_q; +congr_cl_ex3_rel2_m <= congr_cl_ex3_rel2_cmp_q and rel2_val_q and not ovr_lock_det; +congr_cl_ex3_p0_m <= congr_cl_ex3_ex6_cmp_q and ex6_c_acc_val_q; +congr_cl_ex3_p1_m <= congr_cl_ex3_rel_upd_cmp_q and rel_val_wen_q; +-- Bypass EX3 select +-- Whenever reload is in RELU stage (which is xu EX4 stage), +-- no bypass since xu op is a bubble +congr_cl_ex3_byp(0) <= congr_cl_ex3_rel2_m; +congr_cl_ex3_byp(1) <= congr_cl_ex3_ex4_m; +congr_cl_ex3_byp(2) <= congr_cl_ex3_ex5_m; +congr_cl_ex3_byp(3) <= congr_cl_ex3_p1_m; +congr_cl_ex3_byp(4) <= congr_cl_ex3_p0_m; +-- Bypass Pipe Valid +ex4_fxubyp_val_d <= congr_cl_ex3_byp(1) or congr_cl_ex3_byp(2) or congr_cl_ex3_byp(4); +ex4_relbyp_val_d <= congr_cl_ex3_byp(0) or congr_cl_ex3_byp(3); +ex4_lru_byp_sel <= ex4_fxubyp_val_q & ex4_relbyp_val_q; +congr_cl_ex3_sel(1) <= congr_cl_ex3_byp(1); +congr_cl_ex3_sel(2) <= congr_cl_ex3_byp(2) and not congr_cl_ex3_byp(1); +congr_cl_ex3_sel(3) <= congr_cl_ex3_byp(3) and not or_reduce(congr_cl_ex3_byp(1 to 2)); +congr_cl_ex3_sel(4) <= congr_cl_ex3_byp(4) and not or_reduce(congr_cl_ex3_byp(1 to 3)); +-- Late Stage Priority Selection +lru_late_sel <= or_reduce(congr_cl_ex3_byp(1 to 4)); +lru_late_stg_pri <= gate(lru_upd, congr_cl_ex3_sel(1)) or + gate(ex5_lru_upd_q, congr_cl_ex3_sel(2)) or + gate(rel_lru_val_q, congr_cl_ex3_sel(3)) or + gate(ex6_lru_upd_q, congr_cl_ex3_sel(4)); +lru_late_stg_arr <= gate(p0_arr_lru_rd, not lru_late_sel) or lru_late_stg_pri; +-- EX3/RELU/LATE Stage Priority Selection +lru_early_sel <= (others=>congr_cl_ex3_byp(0)); +lru_early_sel_b <= (others=>(not congr_cl_ex3_byp(0))); +-- Bypassed LRU for Execution Pipe +xu_op_lru <= not congr_cl_lru_b_q; +ldst_hit_vector <= ldst_wayA_hit & ldst_wayB_hit & ldst_wayC_hit & ldst_wayD_hit & + ldst_wayE_hit & ldst_wayF_hit & ldst_wayG_hit & ldst_wayH_hit; +-- #################################################### +-- LRU update calculation due to an XU op +-- #################################################### +-- Updating the LRU using the Way that is being reloaded as the Way hit +hit_wayA_upd <= "11" & xu_op_lru(2) & "1" & xu_op_lru(4 to 6); +hit_wayB_upd <= "11" & xu_op_lru(2) & "0" & xu_op_lru(4 to 6); +hit_wayC_upd <= "10" & xu_op_lru(2 to 3) & "1" & xu_op_lru(5 to 6); +hit_wayD_upd <= "10" & xu_op_lru(2 to 3) & "0" & xu_op_lru(5 to 6); +hit_wayE_upd <= "0" & xu_op_lru(1) & "1" & xu_op_lru(3 to 4) & "1" & xu_op_lru(6); +hit_wayF_upd <= "0" & xu_op_lru(1) & "1" & xu_op_lru(3 to 4) & "0" & xu_op_lru(6); +hit_wayG_upd <= "0" & xu_op_lru(1) & "0" & xu_op_lru(3 to 5) & "1"; +hit_wayh_upd <= "0" & xu_op_lru(1) & "0" & xu_op_lru(3 to 5) & "0"; +-- #################################################### +-- Selecting between Execution Pipe +-- #################################################### +-- Selecting Way Hit Updated LRU +ldst_hit_vec_sel <= or_reduce(ldst_hit_vector); +ldst_hit_lru_upd <= gate(hit_wayA_upd, ldst_hit_vector(0)) or gate(hit_wayB_upd, ldst_hit_vector(1)) or + gate(hit_wayC_upd, ldst_hit_vector(2)) or gate(hit_wayD_upd, ldst_hit_vector(3)) or + gate(hit_wayE_upd, ldst_hit_vector(4)) or gate(hit_wayF_upd, ldst_hit_vector(5)) or + gate(hit_wayG_upd, ldst_hit_vector(6)) or gate(hit_wayH_upd, ldst_hit_vector(7)); +with ldst_hit_vec_sel select + lru_upd <= ldst_hit_lru_upd when '1', + xu_op_lru when others; +ex5_lru_upd_d <= lru_upd; +ex6_lru_upd_d <= ex5_lru_upd_q; +-- #################################################### +-- Upper Address Caculation +-- #################################################### +-- Reload Address Calculation +rel_way_dwen <= (rel_wayA_clr or rel_wayA_set or rel_wayA_mid) & (rel_wayB_clr or rel_wayB_set or rel_wayB_mid) & + (rel_wayC_clr or rel_wayC_set or rel_wayC_mid) & (rel_wayD_clr or rel_wayD_set or rel_wayD_mid) & + (rel_wayE_clr or rel_wayE_set or rel_wayE_mid) & (rel_wayF_clr or rel_wayF_set or rel_wayF_mid) & + (rel_wayG_clr or rel_wayG_set or rel_wayG_mid) & (rel_wayH_clr or rel_wayH_set or rel_wayH_mid); +-- Reload is updating either directory or data cache +rel24_way_dwen_stg_d <= rel_way_dwen; +rel_dcarr_val_upd_d <= or_reduce(rel_way_dwen) and not rel4_retry_val_q; +rel_up_way_addr_d <= gate("001", rel_way_dwen(1)) or + gate("010", rel_way_dwen(2)) or gate("011", rel_way_dwen(3)) or + gate("100", rel_way_dwen(4)) or gate("101", rel_way_dwen(5)) or + gate("110", rel_way_dwen(6)) or gate("111", rel_way_dwen(7)); +-- DCARR upper address select +rel_up_way_addr_b <= not rel_up_way_addr_q; +rel_dcarr_addr_en <= rel_dcarr_addr_en_q; +-- #################################################### +-- Directory LRU write enable generations +-- #################################################### +-- Congruence Class Update Act +congr_cl_act_d <= ex5_c_acc_q or relu_val_wen_q; +-- Write on a Reload or on an EX4 XU operation +xu_op_cl0_lru_wen <= (ex6_congr_cl_q = tconv(0,6)) and ex6_c_acc_val_q; +rel_cl0_lru_wen <= (rel_upd_congr_cl_q = tconv(0,6)) and rel_val_wen_q; +congr_cl0_lru_wen <= xu_op_cl0_lru_wen or rel_cl0_lru_wen; +-- Selecting LRU update +with rel_cl0_lru_wen select + rel_ldst_cl0_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl0_lru_wen select + congr_cl0_lru_d <= rel_ldst_cl0_lru when '1', + congr_cl0_lru_q when others; +xu_op_cl1_lru_wen <= (ex6_congr_cl_q = tconv(1,6)) and ex6_c_acc_val_q; +rel_cl1_lru_wen <= (rel_upd_congr_cl_q = tconv(1,6)) and rel_val_wen_q; +congr_cl1_lru_wen <= xu_op_cl1_lru_wen or rel_cl1_lru_wen; +-- Selecting LRU update +with rel_cl1_lru_wen select + rel_ldst_cl1_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl1_lru_wen select + congr_cl1_lru_d <= rel_ldst_cl1_lru when '1', + congr_cl1_lru_q when others; +xu_op_cl2_lru_wen <= (ex6_congr_cl_q = tconv(2,6)) and ex6_c_acc_val_q; +rel_cl2_lru_wen <= (rel_upd_congr_cl_q = tconv(2,6)) and rel_val_wen_q; +congr_cl2_lru_wen <= xu_op_cl2_lru_wen or rel_cl2_lru_wen; +-- Selecting LRU update +with rel_cl2_lru_wen select + rel_ldst_cl2_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl2_lru_wen select + congr_cl2_lru_d <= rel_ldst_cl2_lru when '1', + congr_cl2_lru_q when others; +xu_op_cl3_lru_wen <= (ex6_congr_cl_q = tconv(3,6)) and ex6_c_acc_val_q; +rel_cl3_lru_wen <= (rel_upd_congr_cl_q = tconv(3,6)) and rel_val_wen_q; +congr_cl3_lru_wen <= xu_op_cl3_lru_wen or rel_cl3_lru_wen; +-- Selecting LRU update +with rel_cl3_lru_wen select + rel_ldst_cl3_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl3_lru_wen select + congr_cl3_lru_d <= rel_ldst_cl3_lru when '1', + congr_cl3_lru_q when others; +xu_op_cl4_lru_wen <= (ex6_congr_cl_q = tconv(4,6)) and ex6_c_acc_val_q; +rel_cl4_lru_wen <= (rel_upd_congr_cl_q = tconv(4,6)) and rel_val_wen_q; +congr_cl4_lru_wen <= xu_op_cl4_lru_wen or rel_cl4_lru_wen; +-- Selecting LRU update +with rel_cl4_lru_wen select + rel_ldst_cl4_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl4_lru_wen select + congr_cl4_lru_d <= rel_ldst_cl4_lru when '1', + congr_cl4_lru_q when others; +xu_op_cl5_lru_wen <= (ex6_congr_cl_q = tconv(5,6)) and ex6_c_acc_val_q; +rel_cl5_lru_wen <= (rel_upd_congr_cl_q = tconv(5,6)) and rel_val_wen_q; +congr_cl5_lru_wen <= xu_op_cl5_lru_wen or rel_cl5_lru_wen; +-- Selecting LRU update +with rel_cl5_lru_wen select + rel_ldst_cl5_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl5_lru_wen select + congr_cl5_lru_d <= rel_ldst_cl5_lru when '1', + congr_cl5_lru_q when others; +xu_op_cl6_lru_wen <= (ex6_congr_cl_q = tconv(6,6)) and ex6_c_acc_val_q; +rel_cl6_lru_wen <= (rel_upd_congr_cl_q = tconv(6,6)) and rel_val_wen_q; +congr_cl6_lru_wen <= xu_op_cl6_lru_wen or rel_cl6_lru_wen; +-- Selecting LRU update +with rel_cl6_lru_wen select + rel_ldst_cl6_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl6_lru_wen select + congr_cl6_lru_d <= rel_ldst_cl6_lru when '1', + congr_cl6_lru_q when others; +xu_op_cl7_lru_wen <= (ex6_congr_cl_q = tconv(7,6)) and ex6_c_acc_val_q; +rel_cl7_lru_wen <= (rel_upd_congr_cl_q = tconv(7,6)) and rel_val_wen_q; +congr_cl7_lru_wen <= xu_op_cl7_lru_wen or rel_cl7_lru_wen; +-- Selecting LRU update +with rel_cl7_lru_wen select + rel_ldst_cl7_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl7_lru_wen select + congr_cl7_lru_d <= rel_ldst_cl7_lru when '1', + congr_cl7_lru_q when others; +xu_op_cl8_lru_wen <= (ex6_congr_cl_q = tconv(8,6)) and ex6_c_acc_val_q; +rel_cl8_lru_wen <= (rel_upd_congr_cl_q = tconv(8,6)) and rel_val_wen_q; +congr_cl8_lru_wen <= xu_op_cl8_lru_wen or rel_cl8_lru_wen; +-- Selecting LRU update +with rel_cl8_lru_wen select + rel_ldst_cl8_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl8_lru_wen select + congr_cl8_lru_d <= rel_ldst_cl8_lru when '1', + congr_cl8_lru_q when others; +xu_op_cl9_lru_wen <= (ex6_congr_cl_q = tconv(9,6)) and ex6_c_acc_val_q; +rel_cl9_lru_wen <= (rel_upd_congr_cl_q = tconv(9,6)) and rel_val_wen_q; +congr_cl9_lru_wen <= xu_op_cl9_lru_wen or rel_cl9_lru_wen; +-- Selecting LRU update +with rel_cl9_lru_wen select + rel_ldst_cl9_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl9_lru_wen select + congr_cl9_lru_d <= rel_ldst_cl9_lru when '1', + congr_cl9_lru_q when others; +xu_op_cl10_lru_wen <= (ex6_congr_cl_q = tconv(10,6)) and ex6_c_acc_val_q; +rel_cl10_lru_wen <= (rel_upd_congr_cl_q = tconv(10,6)) and rel_val_wen_q; +congr_cl10_lru_wen <= xu_op_cl10_lru_wen or rel_cl10_lru_wen; +-- Selecting LRU update +with rel_cl10_lru_wen select + rel_ldst_cl10_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl10_lru_wen select + congr_cl10_lru_d <= rel_ldst_cl10_lru when '1', + congr_cl10_lru_q when others; +xu_op_cl11_lru_wen <= (ex6_congr_cl_q = tconv(11,6)) and ex6_c_acc_val_q; +rel_cl11_lru_wen <= (rel_upd_congr_cl_q = tconv(11,6)) and rel_val_wen_q; +congr_cl11_lru_wen <= xu_op_cl11_lru_wen or rel_cl11_lru_wen; +-- Selecting LRU update +with rel_cl11_lru_wen select + rel_ldst_cl11_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl11_lru_wen select + congr_cl11_lru_d <= rel_ldst_cl11_lru when '1', + congr_cl11_lru_q when others; +xu_op_cl12_lru_wen <= (ex6_congr_cl_q = tconv(12,6)) and ex6_c_acc_val_q; +rel_cl12_lru_wen <= (rel_upd_congr_cl_q = tconv(12,6)) and rel_val_wen_q; +congr_cl12_lru_wen <= xu_op_cl12_lru_wen or rel_cl12_lru_wen; +-- Selecting LRU update +with rel_cl12_lru_wen select + rel_ldst_cl12_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl12_lru_wen select + congr_cl12_lru_d <= rel_ldst_cl12_lru when '1', + congr_cl12_lru_q when others; +xu_op_cl13_lru_wen <= (ex6_congr_cl_q = tconv(13,6)) and ex6_c_acc_val_q; +rel_cl13_lru_wen <= (rel_upd_congr_cl_q = tconv(13,6)) and rel_val_wen_q; +congr_cl13_lru_wen <= xu_op_cl13_lru_wen or rel_cl13_lru_wen; +-- Selecting LRU update +with rel_cl13_lru_wen select + rel_ldst_cl13_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl13_lru_wen select + congr_cl13_lru_d <= rel_ldst_cl13_lru when '1', + congr_cl13_lru_q when others; +xu_op_cl14_lru_wen <= (ex6_congr_cl_q = tconv(14,6)) and ex6_c_acc_val_q; +rel_cl14_lru_wen <= (rel_upd_congr_cl_q = tconv(14,6)) and rel_val_wen_q; +congr_cl14_lru_wen <= xu_op_cl14_lru_wen or rel_cl14_lru_wen; +-- Selecting LRU update +with rel_cl14_lru_wen select + rel_ldst_cl14_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl14_lru_wen select + congr_cl14_lru_d <= rel_ldst_cl14_lru when '1', + congr_cl14_lru_q when others; +xu_op_cl15_lru_wen <= (ex6_congr_cl_q = tconv(15,6)) and ex6_c_acc_val_q; +rel_cl15_lru_wen <= (rel_upd_congr_cl_q = tconv(15,6)) and rel_val_wen_q; +congr_cl15_lru_wen <= xu_op_cl15_lru_wen or rel_cl15_lru_wen; +-- Selecting LRU update +with rel_cl15_lru_wen select + rel_ldst_cl15_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl15_lru_wen select + congr_cl15_lru_d <= rel_ldst_cl15_lru when '1', + congr_cl15_lru_q when others; +xu_op_cl16_lru_wen <= (ex6_congr_cl_q = tconv(16,6)) and ex6_c_acc_val_q; +rel_cl16_lru_wen <= (rel_upd_congr_cl_q = tconv(16,6)) and rel_val_wen_q; +congr_cl16_lru_wen <= xu_op_cl16_lru_wen or rel_cl16_lru_wen; +-- Selecting LRU update +with rel_cl16_lru_wen select + rel_ldst_cl16_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl16_lru_wen select + congr_cl16_lru_d <= rel_ldst_cl16_lru when '1', + congr_cl16_lru_q when others; +xu_op_cl17_lru_wen <= (ex6_congr_cl_q = tconv(17,6)) and ex6_c_acc_val_q; +rel_cl17_lru_wen <= (rel_upd_congr_cl_q = tconv(17,6)) and rel_val_wen_q; +congr_cl17_lru_wen <= xu_op_cl17_lru_wen or rel_cl17_lru_wen; +-- Selecting LRU update +with rel_cl17_lru_wen select + rel_ldst_cl17_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl17_lru_wen select + congr_cl17_lru_d <= rel_ldst_cl17_lru when '1', + congr_cl17_lru_q when others; +xu_op_cl18_lru_wen <= (ex6_congr_cl_q = tconv(18,6)) and ex6_c_acc_val_q; +rel_cl18_lru_wen <= (rel_upd_congr_cl_q = tconv(18,6)) and rel_val_wen_q; +congr_cl18_lru_wen <= xu_op_cl18_lru_wen or rel_cl18_lru_wen; +-- Selecting LRU update +with rel_cl18_lru_wen select + rel_ldst_cl18_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl18_lru_wen select + congr_cl18_lru_d <= rel_ldst_cl18_lru when '1', + congr_cl18_lru_q when others; +xu_op_cl19_lru_wen <= (ex6_congr_cl_q = tconv(19,6)) and ex6_c_acc_val_q; +rel_cl19_lru_wen <= (rel_upd_congr_cl_q = tconv(19,6)) and rel_val_wen_q; +congr_cl19_lru_wen <= xu_op_cl19_lru_wen or rel_cl19_lru_wen; +-- Selecting LRU update +with rel_cl19_lru_wen select + rel_ldst_cl19_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl19_lru_wen select + congr_cl19_lru_d <= rel_ldst_cl19_lru when '1', + congr_cl19_lru_q when others; +xu_op_cl20_lru_wen <= (ex6_congr_cl_q = tconv(20,6)) and ex6_c_acc_val_q; +rel_cl20_lru_wen <= (rel_upd_congr_cl_q = tconv(20,6)) and rel_val_wen_q; +congr_cl20_lru_wen <= xu_op_cl20_lru_wen or rel_cl20_lru_wen; +-- Selecting LRU update +with rel_cl20_lru_wen select + rel_ldst_cl20_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl20_lru_wen select + congr_cl20_lru_d <= rel_ldst_cl20_lru when '1', + congr_cl20_lru_q when others; +xu_op_cl21_lru_wen <= (ex6_congr_cl_q = tconv(21,6)) and ex6_c_acc_val_q; +rel_cl21_lru_wen <= (rel_upd_congr_cl_q = tconv(21,6)) and rel_val_wen_q; +congr_cl21_lru_wen <= xu_op_cl21_lru_wen or rel_cl21_lru_wen; +-- Selecting LRU update +with rel_cl21_lru_wen select + rel_ldst_cl21_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl21_lru_wen select + congr_cl21_lru_d <= rel_ldst_cl21_lru when '1', + congr_cl21_lru_q when others; +xu_op_cl22_lru_wen <= (ex6_congr_cl_q = tconv(22,6)) and ex6_c_acc_val_q; +rel_cl22_lru_wen <= (rel_upd_congr_cl_q = tconv(22,6)) and rel_val_wen_q; +congr_cl22_lru_wen <= xu_op_cl22_lru_wen or rel_cl22_lru_wen; +-- Selecting LRU update +with rel_cl22_lru_wen select + rel_ldst_cl22_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl22_lru_wen select + congr_cl22_lru_d <= rel_ldst_cl22_lru when '1', + congr_cl22_lru_q when others; +xu_op_cl23_lru_wen <= (ex6_congr_cl_q = tconv(23,6)) and ex6_c_acc_val_q; +rel_cl23_lru_wen <= (rel_upd_congr_cl_q = tconv(23,6)) and rel_val_wen_q; +congr_cl23_lru_wen <= xu_op_cl23_lru_wen or rel_cl23_lru_wen; +-- Selecting LRU update +with rel_cl23_lru_wen select + rel_ldst_cl23_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl23_lru_wen select + congr_cl23_lru_d <= rel_ldst_cl23_lru when '1', + congr_cl23_lru_q when others; +xu_op_cl24_lru_wen <= (ex6_congr_cl_q = tconv(24,6)) and ex6_c_acc_val_q; +rel_cl24_lru_wen <= (rel_upd_congr_cl_q = tconv(24,6)) and rel_val_wen_q; +congr_cl24_lru_wen <= xu_op_cl24_lru_wen or rel_cl24_lru_wen; +-- Selecting LRU update +with rel_cl24_lru_wen select + rel_ldst_cl24_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl24_lru_wen select + congr_cl24_lru_d <= rel_ldst_cl24_lru when '1', + congr_cl24_lru_q when others; +xu_op_cl25_lru_wen <= (ex6_congr_cl_q = tconv(25,6)) and ex6_c_acc_val_q; +rel_cl25_lru_wen <= (rel_upd_congr_cl_q = tconv(25,6)) and rel_val_wen_q; +congr_cl25_lru_wen <= xu_op_cl25_lru_wen or rel_cl25_lru_wen; +-- Selecting LRU update +with rel_cl25_lru_wen select + rel_ldst_cl25_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl25_lru_wen select + congr_cl25_lru_d <= rel_ldst_cl25_lru when '1', + congr_cl25_lru_q when others; +xu_op_cl26_lru_wen <= (ex6_congr_cl_q = tconv(26,6)) and ex6_c_acc_val_q; +rel_cl26_lru_wen <= (rel_upd_congr_cl_q = tconv(26,6)) and rel_val_wen_q; +congr_cl26_lru_wen <= xu_op_cl26_lru_wen or rel_cl26_lru_wen; +-- Selecting LRU update +with rel_cl26_lru_wen select + rel_ldst_cl26_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl26_lru_wen select + congr_cl26_lru_d <= rel_ldst_cl26_lru when '1', + congr_cl26_lru_q when others; +xu_op_cl27_lru_wen <= (ex6_congr_cl_q = tconv(27,6)) and ex6_c_acc_val_q; +rel_cl27_lru_wen <= (rel_upd_congr_cl_q = tconv(27,6)) and rel_val_wen_q; +congr_cl27_lru_wen <= xu_op_cl27_lru_wen or rel_cl27_lru_wen; +-- Selecting LRU update +with rel_cl27_lru_wen select + rel_ldst_cl27_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl27_lru_wen select + congr_cl27_lru_d <= rel_ldst_cl27_lru when '1', + congr_cl27_lru_q when others; +xu_op_cl28_lru_wen <= (ex6_congr_cl_q = tconv(28,6)) and ex6_c_acc_val_q; +rel_cl28_lru_wen <= (rel_upd_congr_cl_q = tconv(28,6)) and rel_val_wen_q; +congr_cl28_lru_wen <= xu_op_cl28_lru_wen or rel_cl28_lru_wen; +-- Selecting LRU update +with rel_cl28_lru_wen select + rel_ldst_cl28_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl28_lru_wen select + congr_cl28_lru_d <= rel_ldst_cl28_lru when '1', + congr_cl28_lru_q when others; +xu_op_cl29_lru_wen <= (ex6_congr_cl_q = tconv(29,6)) and ex6_c_acc_val_q; +rel_cl29_lru_wen <= (rel_upd_congr_cl_q = tconv(29,6)) and rel_val_wen_q; +congr_cl29_lru_wen <= xu_op_cl29_lru_wen or rel_cl29_lru_wen; +-- Selecting LRU update +with rel_cl29_lru_wen select + rel_ldst_cl29_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl29_lru_wen select + congr_cl29_lru_d <= rel_ldst_cl29_lru when '1', + congr_cl29_lru_q when others; +xu_op_cl30_lru_wen <= (ex6_congr_cl_q = tconv(30,6)) and ex6_c_acc_val_q; +rel_cl30_lru_wen <= (rel_upd_congr_cl_q = tconv(30,6)) and rel_val_wen_q; +congr_cl30_lru_wen <= xu_op_cl30_lru_wen or rel_cl30_lru_wen; +-- Selecting LRU update +with rel_cl30_lru_wen select + rel_ldst_cl30_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl30_lru_wen select + congr_cl30_lru_d <= rel_ldst_cl30_lru when '1', + congr_cl30_lru_q when others; +xu_op_cl31_lru_wen <= (ex6_congr_cl_q = tconv(31,6)) and ex6_c_acc_val_q; +rel_cl31_lru_wen <= (rel_upd_congr_cl_q = tconv(31,6)) and rel_val_wen_q; +congr_cl31_lru_wen <= xu_op_cl31_lru_wen or rel_cl31_lru_wen; +-- Selecting LRU update +with rel_cl31_lru_wen select + rel_ldst_cl31_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl31_lru_wen select + congr_cl31_lru_d <= rel_ldst_cl31_lru when '1', + congr_cl31_lru_q when others; +xu_op_cl32_lru_wen <= (ex6_congr_cl_q = tconv(32,6)) and ex6_c_acc_val_q; +rel_cl32_lru_wen <= (rel_upd_congr_cl_q = tconv(32,6)) and rel_val_wen_q; +congr_cl32_lru_wen <= xu_op_cl32_lru_wen or rel_cl32_lru_wen; +-- Selecting LRU update +with rel_cl32_lru_wen select + rel_ldst_cl32_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl32_lru_wen select + congr_cl32_lru_d <= rel_ldst_cl32_lru when '1', + congr_cl32_lru_q when others; +xu_op_cl33_lru_wen <= (ex6_congr_cl_q = tconv(33,6)) and ex6_c_acc_val_q; +rel_cl33_lru_wen <= (rel_upd_congr_cl_q = tconv(33,6)) and rel_val_wen_q; +congr_cl33_lru_wen <= xu_op_cl33_lru_wen or rel_cl33_lru_wen; +-- Selecting LRU update +with rel_cl33_lru_wen select + rel_ldst_cl33_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl33_lru_wen select + congr_cl33_lru_d <= rel_ldst_cl33_lru when '1', + congr_cl33_lru_q when others; +xu_op_cl34_lru_wen <= (ex6_congr_cl_q = tconv(34,6)) and ex6_c_acc_val_q; +rel_cl34_lru_wen <= (rel_upd_congr_cl_q = tconv(34,6)) and rel_val_wen_q; +congr_cl34_lru_wen <= xu_op_cl34_lru_wen or rel_cl34_lru_wen; +-- Selecting LRU update +with rel_cl34_lru_wen select + rel_ldst_cl34_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl34_lru_wen select + congr_cl34_lru_d <= rel_ldst_cl34_lru when '1', + congr_cl34_lru_q when others; +xu_op_cl35_lru_wen <= (ex6_congr_cl_q = tconv(35,6)) and ex6_c_acc_val_q; +rel_cl35_lru_wen <= (rel_upd_congr_cl_q = tconv(35,6)) and rel_val_wen_q; +congr_cl35_lru_wen <= xu_op_cl35_lru_wen or rel_cl35_lru_wen; +-- Selecting LRU update +with rel_cl35_lru_wen select + rel_ldst_cl35_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl35_lru_wen select + congr_cl35_lru_d <= rel_ldst_cl35_lru when '1', + congr_cl35_lru_q when others; +xu_op_cl36_lru_wen <= (ex6_congr_cl_q = tconv(36,6)) and ex6_c_acc_val_q; +rel_cl36_lru_wen <= (rel_upd_congr_cl_q = tconv(36,6)) and rel_val_wen_q; +congr_cl36_lru_wen <= xu_op_cl36_lru_wen or rel_cl36_lru_wen; +-- Selecting LRU update +with rel_cl36_lru_wen select + rel_ldst_cl36_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl36_lru_wen select + congr_cl36_lru_d <= rel_ldst_cl36_lru when '1', + congr_cl36_lru_q when others; +xu_op_cl37_lru_wen <= (ex6_congr_cl_q = tconv(37,6)) and ex6_c_acc_val_q; +rel_cl37_lru_wen <= (rel_upd_congr_cl_q = tconv(37,6)) and rel_val_wen_q; +congr_cl37_lru_wen <= xu_op_cl37_lru_wen or rel_cl37_lru_wen; +-- Selecting LRU update +with rel_cl37_lru_wen select + rel_ldst_cl37_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl37_lru_wen select + congr_cl37_lru_d <= rel_ldst_cl37_lru when '1', + congr_cl37_lru_q when others; +xu_op_cl38_lru_wen <= (ex6_congr_cl_q = tconv(38,6)) and ex6_c_acc_val_q; +rel_cl38_lru_wen <= (rel_upd_congr_cl_q = tconv(38,6)) and rel_val_wen_q; +congr_cl38_lru_wen <= xu_op_cl38_lru_wen or rel_cl38_lru_wen; +-- Selecting LRU update +with rel_cl38_lru_wen select + rel_ldst_cl38_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl38_lru_wen select + congr_cl38_lru_d <= rel_ldst_cl38_lru when '1', + congr_cl38_lru_q when others; +xu_op_cl39_lru_wen <= (ex6_congr_cl_q = tconv(39,6)) and ex6_c_acc_val_q; +rel_cl39_lru_wen <= (rel_upd_congr_cl_q = tconv(39,6)) and rel_val_wen_q; +congr_cl39_lru_wen <= xu_op_cl39_lru_wen or rel_cl39_lru_wen; +-- Selecting LRU update +with rel_cl39_lru_wen select + rel_ldst_cl39_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl39_lru_wen select + congr_cl39_lru_d <= rel_ldst_cl39_lru when '1', + congr_cl39_lru_q when others; +xu_op_cl40_lru_wen <= (ex6_congr_cl_q = tconv(40,6)) and ex6_c_acc_val_q; +rel_cl40_lru_wen <= (rel_upd_congr_cl_q = tconv(40,6)) and rel_val_wen_q; +congr_cl40_lru_wen <= xu_op_cl40_lru_wen or rel_cl40_lru_wen; +-- Selecting LRU update +with rel_cl40_lru_wen select + rel_ldst_cl40_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl40_lru_wen select + congr_cl40_lru_d <= rel_ldst_cl40_lru when '1', + congr_cl40_lru_q when others; +xu_op_cl41_lru_wen <= (ex6_congr_cl_q = tconv(41,6)) and ex6_c_acc_val_q; +rel_cl41_lru_wen <= (rel_upd_congr_cl_q = tconv(41,6)) and rel_val_wen_q; +congr_cl41_lru_wen <= xu_op_cl41_lru_wen or rel_cl41_lru_wen; +-- Selecting LRU update +with rel_cl41_lru_wen select + rel_ldst_cl41_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl41_lru_wen select + congr_cl41_lru_d <= rel_ldst_cl41_lru when '1', + congr_cl41_lru_q when others; +xu_op_cl42_lru_wen <= (ex6_congr_cl_q = tconv(42,6)) and ex6_c_acc_val_q; +rel_cl42_lru_wen <= (rel_upd_congr_cl_q = tconv(42,6)) and rel_val_wen_q; +congr_cl42_lru_wen <= xu_op_cl42_lru_wen or rel_cl42_lru_wen; +-- Selecting LRU update +with rel_cl42_lru_wen select + rel_ldst_cl42_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl42_lru_wen select + congr_cl42_lru_d <= rel_ldst_cl42_lru when '1', + congr_cl42_lru_q when others; +xu_op_cl43_lru_wen <= (ex6_congr_cl_q = tconv(43,6)) and ex6_c_acc_val_q; +rel_cl43_lru_wen <= (rel_upd_congr_cl_q = tconv(43,6)) and rel_val_wen_q; +congr_cl43_lru_wen <= xu_op_cl43_lru_wen or rel_cl43_lru_wen; +-- Selecting LRU update +with rel_cl43_lru_wen select + rel_ldst_cl43_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl43_lru_wen select + congr_cl43_lru_d <= rel_ldst_cl43_lru when '1', + congr_cl43_lru_q when others; +xu_op_cl44_lru_wen <= (ex6_congr_cl_q = tconv(44,6)) and ex6_c_acc_val_q; +rel_cl44_lru_wen <= (rel_upd_congr_cl_q = tconv(44,6)) and rel_val_wen_q; +congr_cl44_lru_wen <= xu_op_cl44_lru_wen or rel_cl44_lru_wen; +-- Selecting LRU update +with rel_cl44_lru_wen select + rel_ldst_cl44_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl44_lru_wen select + congr_cl44_lru_d <= rel_ldst_cl44_lru when '1', + congr_cl44_lru_q when others; +xu_op_cl45_lru_wen <= (ex6_congr_cl_q = tconv(45,6)) and ex6_c_acc_val_q; +rel_cl45_lru_wen <= (rel_upd_congr_cl_q = tconv(45,6)) and rel_val_wen_q; +congr_cl45_lru_wen <= xu_op_cl45_lru_wen or rel_cl45_lru_wen; +-- Selecting LRU update +with rel_cl45_lru_wen select + rel_ldst_cl45_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl45_lru_wen select + congr_cl45_lru_d <= rel_ldst_cl45_lru when '1', + congr_cl45_lru_q when others; +xu_op_cl46_lru_wen <= (ex6_congr_cl_q = tconv(46,6)) and ex6_c_acc_val_q; +rel_cl46_lru_wen <= (rel_upd_congr_cl_q = tconv(46,6)) and rel_val_wen_q; +congr_cl46_lru_wen <= xu_op_cl46_lru_wen or rel_cl46_lru_wen; +-- Selecting LRU update +with rel_cl46_lru_wen select + rel_ldst_cl46_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl46_lru_wen select + congr_cl46_lru_d <= rel_ldst_cl46_lru when '1', + congr_cl46_lru_q when others; +xu_op_cl47_lru_wen <= (ex6_congr_cl_q = tconv(47,6)) and ex6_c_acc_val_q; +rel_cl47_lru_wen <= (rel_upd_congr_cl_q = tconv(47,6)) and rel_val_wen_q; +congr_cl47_lru_wen <= xu_op_cl47_lru_wen or rel_cl47_lru_wen; +-- Selecting LRU update +with rel_cl47_lru_wen select + rel_ldst_cl47_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl47_lru_wen select + congr_cl47_lru_d <= rel_ldst_cl47_lru when '1', + congr_cl47_lru_q when others; +xu_op_cl48_lru_wen <= (ex6_congr_cl_q = tconv(48,6)) and ex6_c_acc_val_q; +rel_cl48_lru_wen <= (rel_upd_congr_cl_q = tconv(48,6)) and rel_val_wen_q; +congr_cl48_lru_wen <= xu_op_cl48_lru_wen or rel_cl48_lru_wen; +-- Selecting LRU update +with rel_cl48_lru_wen select + rel_ldst_cl48_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl48_lru_wen select + congr_cl48_lru_d <= rel_ldst_cl48_lru when '1', + congr_cl48_lru_q when others; +xu_op_cl49_lru_wen <= (ex6_congr_cl_q = tconv(49,6)) and ex6_c_acc_val_q; +rel_cl49_lru_wen <= (rel_upd_congr_cl_q = tconv(49,6)) and rel_val_wen_q; +congr_cl49_lru_wen <= xu_op_cl49_lru_wen or rel_cl49_lru_wen; +-- Selecting LRU update +with rel_cl49_lru_wen select + rel_ldst_cl49_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl49_lru_wen select + congr_cl49_lru_d <= rel_ldst_cl49_lru when '1', + congr_cl49_lru_q when others; +xu_op_cl50_lru_wen <= (ex6_congr_cl_q = tconv(50,6)) and ex6_c_acc_val_q; +rel_cl50_lru_wen <= (rel_upd_congr_cl_q = tconv(50,6)) and rel_val_wen_q; +congr_cl50_lru_wen <= xu_op_cl50_lru_wen or rel_cl50_lru_wen; +-- Selecting LRU update +with rel_cl50_lru_wen select + rel_ldst_cl50_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl50_lru_wen select + congr_cl50_lru_d <= rel_ldst_cl50_lru when '1', + congr_cl50_lru_q when others; +xu_op_cl51_lru_wen <= (ex6_congr_cl_q = tconv(51,6)) and ex6_c_acc_val_q; +rel_cl51_lru_wen <= (rel_upd_congr_cl_q = tconv(51,6)) and rel_val_wen_q; +congr_cl51_lru_wen <= xu_op_cl51_lru_wen or rel_cl51_lru_wen; +-- Selecting LRU update +with rel_cl51_lru_wen select + rel_ldst_cl51_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl51_lru_wen select + congr_cl51_lru_d <= rel_ldst_cl51_lru when '1', + congr_cl51_lru_q when others; +xu_op_cl52_lru_wen <= (ex6_congr_cl_q = tconv(52,6)) and ex6_c_acc_val_q; +rel_cl52_lru_wen <= (rel_upd_congr_cl_q = tconv(52,6)) and rel_val_wen_q; +congr_cl52_lru_wen <= xu_op_cl52_lru_wen or rel_cl52_lru_wen; +-- Selecting LRU update +with rel_cl52_lru_wen select + rel_ldst_cl52_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl52_lru_wen select + congr_cl52_lru_d <= rel_ldst_cl52_lru when '1', + congr_cl52_lru_q when others; +xu_op_cl53_lru_wen <= (ex6_congr_cl_q = tconv(53,6)) and ex6_c_acc_val_q; +rel_cl53_lru_wen <= (rel_upd_congr_cl_q = tconv(53,6)) and rel_val_wen_q; +congr_cl53_lru_wen <= xu_op_cl53_lru_wen or rel_cl53_lru_wen; +-- Selecting LRU update +with rel_cl53_lru_wen select + rel_ldst_cl53_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl53_lru_wen select + congr_cl53_lru_d <= rel_ldst_cl53_lru when '1', + congr_cl53_lru_q when others; +xu_op_cl54_lru_wen <= (ex6_congr_cl_q = tconv(54,6)) and ex6_c_acc_val_q; +rel_cl54_lru_wen <= (rel_upd_congr_cl_q = tconv(54,6)) and rel_val_wen_q; +congr_cl54_lru_wen <= xu_op_cl54_lru_wen or rel_cl54_lru_wen; +-- Selecting LRU update +with rel_cl54_lru_wen select + rel_ldst_cl54_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl54_lru_wen select + congr_cl54_lru_d <= rel_ldst_cl54_lru when '1', + congr_cl54_lru_q when others; +xu_op_cl55_lru_wen <= (ex6_congr_cl_q = tconv(55,6)) and ex6_c_acc_val_q; +rel_cl55_lru_wen <= (rel_upd_congr_cl_q = tconv(55,6)) and rel_val_wen_q; +congr_cl55_lru_wen <= xu_op_cl55_lru_wen or rel_cl55_lru_wen; +-- Selecting LRU update +with rel_cl55_lru_wen select + rel_ldst_cl55_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl55_lru_wen select + congr_cl55_lru_d <= rel_ldst_cl55_lru when '1', + congr_cl55_lru_q when others; +xu_op_cl56_lru_wen <= (ex6_congr_cl_q = tconv(56,6)) and ex6_c_acc_val_q; +rel_cl56_lru_wen <= (rel_upd_congr_cl_q = tconv(56,6)) and rel_val_wen_q; +congr_cl56_lru_wen <= xu_op_cl56_lru_wen or rel_cl56_lru_wen; +-- Selecting LRU update +with rel_cl56_lru_wen select + rel_ldst_cl56_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl56_lru_wen select + congr_cl56_lru_d <= rel_ldst_cl56_lru when '1', + congr_cl56_lru_q when others; +xu_op_cl57_lru_wen <= (ex6_congr_cl_q = tconv(57,6)) and ex6_c_acc_val_q; +rel_cl57_lru_wen <= (rel_upd_congr_cl_q = tconv(57,6)) and rel_val_wen_q; +congr_cl57_lru_wen <= xu_op_cl57_lru_wen or rel_cl57_lru_wen; +-- Selecting LRU update +with rel_cl57_lru_wen select + rel_ldst_cl57_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl57_lru_wen select + congr_cl57_lru_d <= rel_ldst_cl57_lru when '1', + congr_cl57_lru_q when others; +xu_op_cl58_lru_wen <= (ex6_congr_cl_q = tconv(58,6)) and ex6_c_acc_val_q; +rel_cl58_lru_wen <= (rel_upd_congr_cl_q = tconv(58,6)) and rel_val_wen_q; +congr_cl58_lru_wen <= xu_op_cl58_lru_wen or rel_cl58_lru_wen; +-- Selecting LRU update +with rel_cl58_lru_wen select + rel_ldst_cl58_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl58_lru_wen select + congr_cl58_lru_d <= rel_ldst_cl58_lru when '1', + congr_cl58_lru_q when others; +xu_op_cl59_lru_wen <= (ex6_congr_cl_q = tconv(59,6)) and ex6_c_acc_val_q; +rel_cl59_lru_wen <= (rel_upd_congr_cl_q = tconv(59,6)) and rel_val_wen_q; +congr_cl59_lru_wen <= xu_op_cl59_lru_wen or rel_cl59_lru_wen; +-- Selecting LRU update +with rel_cl59_lru_wen select + rel_ldst_cl59_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl59_lru_wen select + congr_cl59_lru_d <= rel_ldst_cl59_lru when '1', + congr_cl59_lru_q when others; +xu_op_cl60_lru_wen <= (ex6_congr_cl_q = tconv(60,6)) and ex6_c_acc_val_q; +rel_cl60_lru_wen <= (rel_upd_congr_cl_q = tconv(60,6)) and rel_val_wen_q; +congr_cl60_lru_wen <= xu_op_cl60_lru_wen or rel_cl60_lru_wen; +-- Selecting LRU update +with rel_cl60_lru_wen select + rel_ldst_cl60_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl60_lru_wen select + congr_cl60_lru_d <= rel_ldst_cl60_lru when '1', + congr_cl60_lru_q when others; +xu_op_cl61_lru_wen <= (ex6_congr_cl_q = tconv(61,6)) and ex6_c_acc_val_q; +rel_cl61_lru_wen <= (rel_upd_congr_cl_q = tconv(61,6)) and rel_val_wen_q; +congr_cl61_lru_wen <= xu_op_cl61_lru_wen or rel_cl61_lru_wen; +-- Selecting LRU update +with rel_cl61_lru_wen select + rel_ldst_cl61_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl61_lru_wen select + congr_cl61_lru_d <= rel_ldst_cl61_lru when '1', + congr_cl61_lru_q when others; +xu_op_cl62_lru_wen <= (ex6_congr_cl_q = tconv(62,6)) and ex6_c_acc_val_q; +rel_cl62_lru_wen <= (rel_upd_congr_cl_q = tconv(62,6)) and rel_val_wen_q; +congr_cl62_lru_wen <= xu_op_cl62_lru_wen or rel_cl62_lru_wen; +-- Selecting LRU update +with rel_cl62_lru_wen select + rel_ldst_cl62_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl62_lru_wen select + congr_cl62_lru_d <= rel_ldst_cl62_lru when '1', + congr_cl62_lru_q when others; +xu_op_cl63_lru_wen <= (ex6_congr_cl_q = tconv(63,6)) and ex6_c_acc_val_q; +rel_cl63_lru_wen <= (rel_upd_congr_cl_q = tconv(63,6)) and rel_val_wen_q; +congr_cl63_lru_wen <= xu_op_cl63_lru_wen or rel_cl63_lru_wen; +-- Selecting LRU update +with rel_cl63_lru_wen select + rel_ldst_cl63_lru <= rel_lru_val_q when '1', + ex6_lru_upd_q when others; +-- LRU update data +with congr_cl63_lru_wen select + congr_cl63_lru_d <= rel_ldst_cl63_lru when '1', + congr_cl63_lru_q when others; +-- #################################################### +-- Outputs +-- #################################################### +rel_way_clr_a <= rel_wayA_clr; +rel_way_clr_b <= rel_wayB_clr; +rel_way_clr_c <= rel_wayC_clr; +rel_way_clr_d <= rel_wayD_clr; +rel_way_clr_e <= rel_wayE_clr; +rel_way_clr_f <= rel_wayF_clr; +rel_way_clr_g <= rel_wayG_clr; +rel_way_clr_h <= rel_wayH_clr; +rel_way_upd_a <= rel_wayA_upd; +rel_way_upd_b <= rel_wayB_upd; +rel_way_upd_c <= rel_wayC_upd; +rel_way_upd_d <= rel_wayD_upd; +rel_way_upd_e <= rel_wayE_upd; +rel_way_upd_f <= rel_wayF_upd; +rel_way_upd_g <= rel_wayG_upd; +rel_way_upd_h <= rel_wayH_upd; +rel_way_wen_a <= rel_wayA_set; +rel_way_wen_b <= rel_wayB_set; +rel_way_wen_c <= rel_wayC_set; +rel_way_wen_d <= rel_wayD_set; +rel_way_wen_e <= rel_wayE_set; +rel_way_wen_f <= rel_wayF_set; +rel_way_wen_g <= rel_wayG_set; +rel_way_wen_h <= rel_wayH_set; +rel_dcarr_val_upd <= rel_dcarr_val_upd_q; +lsu_xu_spr_xucr0_clo <= xucr0_clo_q; +ex4_dir_lru <= xu_op_lru; +-- Debug Data +dc_lru_dbg_data <= rel24_way_dwen_stg_q & reld_q_val & rel_m_q_way_q & rel2_wlock_q & + rel_way_not_empty_q & ex4_lru_byp_sel & rel2_lru_byp_sel & rel_val_wen_q & + rel_op_lru & rel_lru_val_q & xucr0_clo_q & xu_op_lru & + ex6_c_acc_val_q & ex6_lru_upd_q & rel2_class_id_q & rel_tag_q & + rel4_retry_val_q & ex4_c_acc; +-- #################################################### +-- Directory LRU Registers +-- #################################################### +-- Congruence Class 0 Way A Register +congr_cl0_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl0_lru_offset to congr_cl0_lru_offset + congr_cl0_lru_d'length-1), + scout => sov(congr_cl0_lru_offset to congr_cl0_lru_offset + congr_cl0_lru_d'length-1), + din => congr_cl0_lru_d, + dout => congr_cl0_lru_q); +-- Congruence Class 1 Way A Register +congr_cl1_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl1_lru_offset to congr_cl1_lru_offset + congr_cl1_lru_d'length-1), + scout => sov(congr_cl1_lru_offset to congr_cl1_lru_offset + congr_cl1_lru_d'length-1), + din => congr_cl1_lru_d, + dout => congr_cl1_lru_q); +-- Congruence Class 2 Way A Register +congr_cl2_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl2_lru_offset to congr_cl2_lru_offset + congr_cl2_lru_d'length-1), + scout => sov(congr_cl2_lru_offset to congr_cl2_lru_offset + congr_cl2_lru_d'length-1), + din => congr_cl2_lru_d, + dout => congr_cl2_lru_q); +-- Congruence Class 3 Way A Register +congr_cl3_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl3_lru_offset to congr_cl3_lru_offset + congr_cl3_lru_d'length-1), + scout => sov(congr_cl3_lru_offset to congr_cl3_lru_offset + congr_cl3_lru_d'length-1), + din => congr_cl3_lru_d, + dout => congr_cl3_lru_q); +-- Congruence Class 4 Way A Register +congr_cl4_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl4_lru_offset to congr_cl4_lru_offset + congr_cl4_lru_d'length-1), + scout => sov(congr_cl4_lru_offset to congr_cl4_lru_offset + congr_cl4_lru_d'length-1), + din => congr_cl4_lru_d, + dout => congr_cl4_lru_q); +-- Congruence Class 5 Way A Register +congr_cl5_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl5_lru_offset to congr_cl5_lru_offset + congr_cl5_lru_d'length-1), + scout => sov(congr_cl5_lru_offset to congr_cl5_lru_offset + congr_cl5_lru_d'length-1), + din => congr_cl5_lru_d, + dout => congr_cl5_lru_q); +-- Congruence Class 6 Way A Register +congr_cl6_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl6_lru_offset to congr_cl6_lru_offset + congr_cl6_lru_d'length-1), + scout => sov(congr_cl6_lru_offset to congr_cl6_lru_offset + congr_cl6_lru_d'length-1), + din => congr_cl6_lru_d, + dout => congr_cl6_lru_q); +-- Congruence Class 7 Way A Register +congr_cl7_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl7_lru_offset to congr_cl7_lru_offset + congr_cl7_lru_d'length-1), + scout => sov(congr_cl7_lru_offset to congr_cl7_lru_offset + congr_cl7_lru_d'length-1), + din => congr_cl7_lru_d, + dout => congr_cl7_lru_q); +-- Congruence Class 8 Way A Register +congr_cl8_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl8_lru_offset to congr_cl8_lru_offset + congr_cl8_lru_d'length-1), + scout => sov(congr_cl8_lru_offset to congr_cl8_lru_offset + congr_cl8_lru_d'length-1), + din => congr_cl8_lru_d, + dout => congr_cl8_lru_q); +-- Congruence Class 9 Way A Register +congr_cl9_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl9_lru_offset to congr_cl9_lru_offset + congr_cl9_lru_d'length-1), + scout => sov(congr_cl9_lru_offset to congr_cl9_lru_offset + congr_cl9_lru_d'length-1), + din => congr_cl9_lru_d, + dout => congr_cl9_lru_q); +-- Congruence Class 10 Way A Register +congr_cl10_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl10_lru_offset to congr_cl10_lru_offset + congr_cl10_lru_d'length-1), + scout => sov(congr_cl10_lru_offset to congr_cl10_lru_offset + congr_cl10_lru_d'length-1), + din => congr_cl10_lru_d, + dout => congr_cl10_lru_q); +-- Congruence Class 11 Way A Register +congr_cl11_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl11_lru_offset to congr_cl11_lru_offset + congr_cl11_lru_d'length-1), + scout => sov(congr_cl11_lru_offset to congr_cl11_lru_offset + congr_cl11_lru_d'length-1), + din => congr_cl11_lru_d, + dout => congr_cl11_lru_q); +-- Congruence Class 12 Way A Register +congr_cl12_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl12_lru_offset to congr_cl12_lru_offset + congr_cl12_lru_d'length-1), + scout => sov(congr_cl12_lru_offset to congr_cl12_lru_offset + congr_cl12_lru_d'length-1), + din => congr_cl12_lru_d, + dout => congr_cl12_lru_q); +-- Congruence Class 13 Way A Register +congr_cl13_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl13_lru_offset to congr_cl13_lru_offset + congr_cl13_lru_d'length-1), + scout => sov(congr_cl13_lru_offset to congr_cl13_lru_offset + congr_cl13_lru_d'length-1), + din => congr_cl13_lru_d, + dout => congr_cl13_lru_q); +-- Congruence Class 14 Way A Register +congr_cl14_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl14_lru_offset to congr_cl14_lru_offset + congr_cl14_lru_d'length-1), + scout => sov(congr_cl14_lru_offset to congr_cl14_lru_offset + congr_cl14_lru_d'length-1), + din => congr_cl14_lru_d, + dout => congr_cl14_lru_q); +-- Congruence Class 15 Way A Register +congr_cl15_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl15_lru_offset to congr_cl15_lru_offset + congr_cl15_lru_d'length-1), + scout => sov(congr_cl15_lru_offset to congr_cl15_lru_offset + congr_cl15_lru_d'length-1), + din => congr_cl15_lru_d, + dout => congr_cl15_lru_q); +-- Congruence Class 16 Way A Register +congr_cl16_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl16_lru_offset to congr_cl16_lru_offset + congr_cl16_lru_d'length-1), + scout => sov(congr_cl16_lru_offset to congr_cl16_lru_offset + congr_cl16_lru_d'length-1), + din => congr_cl16_lru_d, + dout => congr_cl16_lru_q); +-- Congruence Class 17 Way A Register +congr_cl17_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl17_lru_offset to congr_cl17_lru_offset + congr_cl17_lru_d'length-1), + scout => sov(congr_cl17_lru_offset to congr_cl17_lru_offset + congr_cl17_lru_d'length-1), + din => congr_cl17_lru_d, + dout => congr_cl17_lru_q); +-- Congruence Class 18 Way A Register +congr_cl18_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl18_lru_offset to congr_cl18_lru_offset + congr_cl18_lru_d'length-1), + scout => sov(congr_cl18_lru_offset to congr_cl18_lru_offset + congr_cl18_lru_d'length-1), + din => congr_cl18_lru_d, + dout => congr_cl18_lru_q); +-- Congruence Class 19 Way A Register +congr_cl19_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl19_lru_offset to congr_cl19_lru_offset + congr_cl19_lru_d'length-1), + scout => sov(congr_cl19_lru_offset to congr_cl19_lru_offset + congr_cl19_lru_d'length-1), + din => congr_cl19_lru_d, + dout => congr_cl19_lru_q); +-- Congruence Class 20 Way A Register +congr_cl20_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl20_lru_offset to congr_cl20_lru_offset + congr_cl20_lru_d'length-1), + scout => sov(congr_cl20_lru_offset to congr_cl20_lru_offset + congr_cl20_lru_d'length-1), + din => congr_cl20_lru_d, + dout => congr_cl20_lru_q); +-- Congruence Class 21 Way A Register +congr_cl21_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl21_lru_offset to congr_cl21_lru_offset + congr_cl21_lru_d'length-1), + scout => sov(congr_cl21_lru_offset to congr_cl21_lru_offset + congr_cl21_lru_d'length-1), + din => congr_cl21_lru_d, + dout => congr_cl21_lru_q); +-- Congruence Class 22 Way A Register +congr_cl22_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl22_lru_offset to congr_cl22_lru_offset + congr_cl22_lru_d'length-1), + scout => sov(congr_cl22_lru_offset to congr_cl22_lru_offset + congr_cl22_lru_d'length-1), + din => congr_cl22_lru_d, + dout => congr_cl22_lru_q); +-- Congruence Class 23 Way A Register +congr_cl23_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl23_lru_offset to congr_cl23_lru_offset + congr_cl23_lru_d'length-1), + scout => sov(congr_cl23_lru_offset to congr_cl23_lru_offset + congr_cl23_lru_d'length-1), + din => congr_cl23_lru_d, + dout => congr_cl23_lru_q); +-- Congruence Class 24 Way A Register +congr_cl24_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl24_lru_offset to congr_cl24_lru_offset + congr_cl24_lru_d'length-1), + scout => sov(congr_cl24_lru_offset to congr_cl24_lru_offset + congr_cl24_lru_d'length-1), + din => congr_cl24_lru_d, + dout => congr_cl24_lru_q); +-- Congruence Class 25 Way A Register +congr_cl25_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl25_lru_offset to congr_cl25_lru_offset + congr_cl25_lru_d'length-1), + scout => sov(congr_cl25_lru_offset to congr_cl25_lru_offset + congr_cl25_lru_d'length-1), + din => congr_cl25_lru_d, + dout => congr_cl25_lru_q); +-- Congruence Class 26 Way A Register +congr_cl26_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl26_lru_offset to congr_cl26_lru_offset + congr_cl26_lru_d'length-1), + scout => sov(congr_cl26_lru_offset to congr_cl26_lru_offset + congr_cl26_lru_d'length-1), + din => congr_cl26_lru_d, + dout => congr_cl26_lru_q); +-- Congruence Class 27 Way A Register +congr_cl27_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl27_lru_offset to congr_cl27_lru_offset + congr_cl27_lru_d'length-1), + scout => sov(congr_cl27_lru_offset to congr_cl27_lru_offset + congr_cl27_lru_d'length-1), + din => congr_cl27_lru_d, + dout => congr_cl27_lru_q); +-- Congruence Class 28 Way A Register +congr_cl28_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl28_lru_offset to congr_cl28_lru_offset + congr_cl28_lru_d'length-1), + scout => sov(congr_cl28_lru_offset to congr_cl28_lru_offset + congr_cl28_lru_d'length-1), + din => congr_cl28_lru_d, + dout => congr_cl28_lru_q); +-- Congruence Class 29 Way A Register +congr_cl29_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl29_lru_offset to congr_cl29_lru_offset + congr_cl29_lru_d'length-1), + scout => sov(congr_cl29_lru_offset to congr_cl29_lru_offset + congr_cl29_lru_d'length-1), + din => congr_cl29_lru_d, + dout => congr_cl29_lru_q); +-- Congruence Class 30 Way A Register +congr_cl30_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl30_lru_offset to congr_cl30_lru_offset + congr_cl30_lru_d'length-1), + scout => sov(congr_cl30_lru_offset to congr_cl30_lru_offset + congr_cl30_lru_d'length-1), + din => congr_cl30_lru_d, + dout => congr_cl30_lru_q); +-- Congruence Class 31 Way A Register +congr_cl31_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl31_lru_offset to congr_cl31_lru_offset + congr_cl31_lru_d'length-1), + scout => sov(congr_cl31_lru_offset to congr_cl31_lru_offset + congr_cl31_lru_d'length-1), + din => congr_cl31_lru_d, + dout => congr_cl31_lru_q); +-- Congruence Class 32 Way A Register +congr_cl32_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl32_lru_offset to congr_cl32_lru_offset + congr_cl32_lru_d'length-1), + scout => sov(congr_cl32_lru_offset to congr_cl32_lru_offset + congr_cl32_lru_d'length-1), + din => congr_cl32_lru_d, + dout => congr_cl32_lru_q); +-- Congruence Class 33 Way A Register +congr_cl33_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl33_lru_offset to congr_cl33_lru_offset + congr_cl33_lru_d'length-1), + scout => sov(congr_cl33_lru_offset to congr_cl33_lru_offset + congr_cl33_lru_d'length-1), + din => congr_cl33_lru_d, + dout => congr_cl33_lru_q); +-- Congruence Class 34 Way A Register +congr_cl34_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl34_lru_offset to congr_cl34_lru_offset + congr_cl34_lru_d'length-1), + scout => sov(congr_cl34_lru_offset to congr_cl34_lru_offset + congr_cl34_lru_d'length-1), + din => congr_cl34_lru_d, + dout => congr_cl34_lru_q); +-- Congruence Class 35 Way A Register +congr_cl35_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl35_lru_offset to congr_cl35_lru_offset + congr_cl35_lru_d'length-1), + scout => sov(congr_cl35_lru_offset to congr_cl35_lru_offset + congr_cl35_lru_d'length-1), + din => congr_cl35_lru_d, + dout => congr_cl35_lru_q); +-- Congruence Class 36 Way A Register +congr_cl36_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl36_lru_offset to congr_cl36_lru_offset + congr_cl36_lru_d'length-1), + scout => sov(congr_cl36_lru_offset to congr_cl36_lru_offset + congr_cl36_lru_d'length-1), + din => congr_cl36_lru_d, + dout => congr_cl36_lru_q); +-- Congruence Class 37 Way A Register +congr_cl37_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl37_lru_offset to congr_cl37_lru_offset + congr_cl37_lru_d'length-1), + scout => sov(congr_cl37_lru_offset to congr_cl37_lru_offset + congr_cl37_lru_d'length-1), + din => congr_cl37_lru_d, + dout => congr_cl37_lru_q); +-- Congruence Class 38 Way A Register +congr_cl38_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl38_lru_offset to congr_cl38_lru_offset + congr_cl38_lru_d'length-1), + scout => sov(congr_cl38_lru_offset to congr_cl38_lru_offset + congr_cl38_lru_d'length-1), + din => congr_cl38_lru_d, + dout => congr_cl38_lru_q); +-- Congruence Class 39 Way A Register +congr_cl39_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl39_lru_offset to congr_cl39_lru_offset + congr_cl39_lru_d'length-1), + scout => sov(congr_cl39_lru_offset to congr_cl39_lru_offset + congr_cl39_lru_d'length-1), + din => congr_cl39_lru_d, + dout => congr_cl39_lru_q); +-- Congruence Class 40 Way A Register +congr_cl40_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl40_lru_offset to congr_cl40_lru_offset + congr_cl40_lru_d'length-1), + scout => sov(congr_cl40_lru_offset to congr_cl40_lru_offset + congr_cl40_lru_d'length-1), + din => congr_cl40_lru_d, + dout => congr_cl40_lru_q); +-- Congruence Class 41 Way A Register +congr_cl41_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl41_lru_offset to congr_cl41_lru_offset + congr_cl41_lru_d'length-1), + scout => sov(congr_cl41_lru_offset to congr_cl41_lru_offset + congr_cl41_lru_d'length-1), + din => congr_cl41_lru_d, + dout => congr_cl41_lru_q); +-- Congruence Class 42 Way A Register +congr_cl42_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl42_lru_offset to congr_cl42_lru_offset + congr_cl42_lru_d'length-1), + scout => sov(congr_cl42_lru_offset to congr_cl42_lru_offset + congr_cl42_lru_d'length-1), + din => congr_cl42_lru_d, + dout => congr_cl42_lru_q); +-- Congruence Class 43 Way A Register +congr_cl43_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl43_lru_offset to congr_cl43_lru_offset + congr_cl43_lru_d'length-1), + scout => sov(congr_cl43_lru_offset to congr_cl43_lru_offset + congr_cl43_lru_d'length-1), + din => congr_cl43_lru_d, + dout => congr_cl43_lru_q); +-- Congruence Class 44 Way A Register +congr_cl44_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl44_lru_offset to congr_cl44_lru_offset + congr_cl44_lru_d'length-1), + scout => sov(congr_cl44_lru_offset to congr_cl44_lru_offset + congr_cl44_lru_d'length-1), + din => congr_cl44_lru_d, + dout => congr_cl44_lru_q); +-- Congruence Class 45 Way A Register +congr_cl45_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl45_lru_offset to congr_cl45_lru_offset + congr_cl45_lru_d'length-1), + scout => sov(congr_cl45_lru_offset to congr_cl45_lru_offset + congr_cl45_lru_d'length-1), + din => congr_cl45_lru_d, + dout => congr_cl45_lru_q); +-- Congruence Class 46 Way A Register +congr_cl46_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl46_lru_offset to congr_cl46_lru_offset + congr_cl46_lru_d'length-1), + scout => sov(congr_cl46_lru_offset to congr_cl46_lru_offset + congr_cl46_lru_d'length-1), + din => congr_cl46_lru_d, + dout => congr_cl46_lru_q); +-- Congruence Class 47 Way A Register +congr_cl47_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl47_lru_offset to congr_cl47_lru_offset + congr_cl47_lru_d'length-1), + scout => sov(congr_cl47_lru_offset to congr_cl47_lru_offset + congr_cl47_lru_d'length-1), + din => congr_cl47_lru_d, + dout => congr_cl47_lru_q); +-- Congruence Class 48 Way A Register +congr_cl48_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl48_lru_offset to congr_cl48_lru_offset + congr_cl48_lru_d'length-1), + scout => sov(congr_cl48_lru_offset to congr_cl48_lru_offset + congr_cl48_lru_d'length-1), + din => congr_cl48_lru_d, + dout => congr_cl48_lru_q); +-- Congruence Class 49 Way A Register +congr_cl49_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl49_lru_offset to congr_cl49_lru_offset + congr_cl49_lru_d'length-1), + scout => sov(congr_cl49_lru_offset to congr_cl49_lru_offset + congr_cl49_lru_d'length-1), + din => congr_cl49_lru_d, + dout => congr_cl49_lru_q); +-- Congruence Class 50 Way A Register +congr_cl50_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl50_lru_offset to congr_cl50_lru_offset + congr_cl50_lru_d'length-1), + scout => sov(congr_cl50_lru_offset to congr_cl50_lru_offset + congr_cl50_lru_d'length-1), + din => congr_cl50_lru_d, + dout => congr_cl50_lru_q); +-- Congruence Class 51 Way A Register +congr_cl51_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl51_lru_offset to congr_cl51_lru_offset + congr_cl51_lru_d'length-1), + scout => sov(congr_cl51_lru_offset to congr_cl51_lru_offset + congr_cl51_lru_d'length-1), + din => congr_cl51_lru_d, + dout => congr_cl51_lru_q); +-- Congruence Class 52 Way A Register +congr_cl52_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl52_lru_offset to congr_cl52_lru_offset + congr_cl52_lru_d'length-1), + scout => sov(congr_cl52_lru_offset to congr_cl52_lru_offset + congr_cl52_lru_d'length-1), + din => congr_cl52_lru_d, + dout => congr_cl52_lru_q); +-- Congruence Class 53 Way A Register +congr_cl53_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl53_lru_offset to congr_cl53_lru_offset + congr_cl53_lru_d'length-1), + scout => sov(congr_cl53_lru_offset to congr_cl53_lru_offset + congr_cl53_lru_d'length-1), + din => congr_cl53_lru_d, + dout => congr_cl53_lru_q); +-- Congruence Class 54 Way A Register +congr_cl54_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl54_lru_offset to congr_cl54_lru_offset + congr_cl54_lru_d'length-1), + scout => sov(congr_cl54_lru_offset to congr_cl54_lru_offset + congr_cl54_lru_d'length-1), + din => congr_cl54_lru_d, + dout => congr_cl54_lru_q); +-- Congruence Class 55 Way A Register +congr_cl55_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl55_lru_offset to congr_cl55_lru_offset + congr_cl55_lru_d'length-1), + scout => sov(congr_cl55_lru_offset to congr_cl55_lru_offset + congr_cl55_lru_d'length-1), + din => congr_cl55_lru_d, + dout => congr_cl55_lru_q); +-- Congruence Class 56 Way A Register +congr_cl56_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl56_lru_offset to congr_cl56_lru_offset + congr_cl56_lru_d'length-1), + scout => sov(congr_cl56_lru_offset to congr_cl56_lru_offset + congr_cl56_lru_d'length-1), + din => congr_cl56_lru_d, + dout => congr_cl56_lru_q); +-- Congruence Class 57 Way A Register +congr_cl57_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl57_lru_offset to congr_cl57_lru_offset + congr_cl57_lru_d'length-1), + scout => sov(congr_cl57_lru_offset to congr_cl57_lru_offset + congr_cl57_lru_d'length-1), + din => congr_cl57_lru_d, + dout => congr_cl57_lru_q); +-- Congruence Class 58 Way A Register +congr_cl58_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl58_lru_offset to congr_cl58_lru_offset + congr_cl58_lru_d'length-1), + scout => sov(congr_cl58_lru_offset to congr_cl58_lru_offset + congr_cl58_lru_d'length-1), + din => congr_cl58_lru_d, + dout => congr_cl58_lru_q); +-- Congruence Class 59 Way A Register +congr_cl59_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl59_lru_offset to congr_cl59_lru_offset + congr_cl59_lru_d'length-1), + scout => sov(congr_cl59_lru_offset to congr_cl59_lru_offset + congr_cl59_lru_d'length-1), + din => congr_cl59_lru_d, + dout => congr_cl59_lru_q); +-- Congruence Class 60 Way A Register +congr_cl60_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl60_lru_offset to congr_cl60_lru_offset + congr_cl60_lru_d'length-1), + scout => sov(congr_cl60_lru_offset to congr_cl60_lru_offset + congr_cl60_lru_d'length-1), + din => congr_cl60_lru_d, + dout => congr_cl60_lru_q); +-- Congruence Class 61 Way A Register +congr_cl61_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl61_lru_offset to congr_cl61_lru_offset + congr_cl61_lru_d'length-1), + scout => sov(congr_cl61_lru_offset to congr_cl61_lru_offset + congr_cl61_lru_d'length-1), + din => congr_cl61_lru_d, + dout => congr_cl61_lru_q); +-- Congruence Class 62 Way A Register +congr_cl62_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl62_lru_offset to congr_cl62_lru_offset + congr_cl62_lru_d'length-1), + scout => sov(congr_cl62_lru_offset to congr_cl62_lru_offset + congr_cl62_lru_d'length-1), + din => congr_cl62_lru_d, + dout => congr_cl62_lru_q); +-- Congruence Class 63 Way A Register +congr_cl63_lru_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl63_lru_offset to congr_cl63_lru_offset + congr_cl63_lru_d'length-1), + scout => sov(congr_cl63_lru_offset to congr_cl63_lru_offset + congr_cl63_lru_d'length-1), + din => congr_cl63_lru_d, + dout => congr_cl63_lru_q); +congr_cl_lru_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_lru_b_offset to congr_cl_lru_b_offset + congr_cl_lru_b_q'length-1), + scout => sov(congr_cl_lru_b_offset to congr_cl_lru_b_offset + congr_cl_lru_b_q'length-1), + a1 => rel_hit_lru_upd, + a2 => lru_early_sel, + b1 => lru_late_stg_arr, + b2 => lru_early_sel_b, + qb => congr_cl_lru_b_q); +rel_congr_cl_lru_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_congr_cl_lru_b_offset to rel_congr_cl_lru_b_offset + rel_congr_cl_lru_b_q'length-1), + scout => sov(rel_congr_cl_lru_b_offset to rel_congr_cl_lru_b_offset + rel_congr_cl_lru_b_q'length-1), + a1 => rel_hit_lru_upd, + a2 => rel_lru_early_sel, + b1 => rel_lru_late_stg_arr, + b2 => rel_lru_early_sel_b, + qb => rel_congr_cl_lru_b_q); +reld_q_sel_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q_sel_offset to reld_q_sel_offset + reld_q_sel_d'length-1), + scout => sov(reld_q_sel_offset to reld_q_sel_offset + reld_q_sel_d'length-1), + din => reld_q_sel_d, + dout => reld_q_sel_q); +ex4_congr_cl_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex4_congr_cl_d, + dout => ex4_congr_cl_q); +ex5_congr_cl_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_congr_cl_offset to ex5_congr_cl_offset + ex5_congr_cl_d'length-1), + scout => sov(ex5_congr_cl_offset to ex5_congr_cl_offset + ex5_congr_cl_d'length-1), + din => ex5_congr_cl_d, + dout => ex5_congr_cl_q); +ex6_congr_cl_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex5_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex6_congr_cl_d, + dout => ex6_congr_cl_q); +rel_congr_cl_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_congr_cl_offset to rel_congr_cl_offset + rel_congr_cl_d'length-1), + scout => sov(rel_congr_cl_offset to rel_congr_cl_offset + rel_congr_cl_d'length-1), + din => rel_congr_cl_d, + dout => rel_congr_cl_q); +rel_congr_cl_stg_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_congr_cl_stg_d, + dout => rel_congr_cl_stg_q); +relu_congr_cl_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(relu_congr_cl_offset to relu_congr_cl_offset + relu_congr_cl_d'length-1), + scout => sov(relu_congr_cl_offset to relu_congr_cl_offset + relu_congr_cl_d'length-1), + din => relu_congr_cl_d, + dout => relu_congr_cl_q); +ex5_lru_upd_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_lru_upd_offset to ex5_lru_upd_offset + ex5_lru_upd_d'length-1), + scout => sov(ex5_lru_upd_offset to ex5_lru_upd_offset + ex5_lru_upd_d'length-1), + din => ex5_lru_upd_d, + dout => ex5_lru_upd_q); +ex6_lru_upd_reg: tri_regk +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex5_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex6_lru_upd_d, + dout => ex6_lru_upd_q); +rel2_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel2_val_offset), + scout => sov(rel2_val_offset), + din => rel2_val_d, + dout => rel2_val_q); +rel2_class_id_reg: tri_regk +generic map (width => 2, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel2_class_id_d, + dout => rel2_class_id_q); +relu_val_wen_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(relu_val_wen_offset), + scout => sov(relu_val_wen_offset), + din => relu_val_wen_d, + dout => relu_val_wen_q); +ex4_hit_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_hit_offset), + scout => sov(ex4_hit_offset), + din => ex4_hit_d, + dout => ex4_hit_q); +ex4_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex4_fxubyp_val_d, + dout(0) => ex4_fxubyp_val_q); +ex4_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex4_relbyp_val_d, + dout(0) => ex4_relbyp_val_q); +ex4_c_acc_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_c_acc_offset), + scout => sov(ex4_c_acc_offset), + din => ex4_c_acc_d, + dout => ex4_c_acc_q); +ex5_c_acc_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_c_acc_offset), + scout => sov(ex5_c_acc_offset), + din => ex5_c_acc_d, + dout => ex5_c_acc_q); +ex6_c_acc_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_c_acc_val_offset), + scout => sov(ex6_c_acc_val_offset), + din => ex6_c_acc_val_d, + dout => ex6_c_acc_val_q); +ex2_congr_cl_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex2_congr_cl_d, + dout => ex2_congr_cl_q); +ex3_congr_cl_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_congr_cl_offset to ex3_congr_cl_offset + ex3_congr_cl_d'length-1), + scout => sov(ex3_congr_cl_offset to ex3_congr_cl_offset + ex3_congr_cl_d'length-1), + din => ex3_congr_cl_d, + dout => ex3_congr_cl_q); +rel_val_wen_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_val_wen_offset), + scout => sov(rel_val_wen_offset), + din => rel_val_wen_d, + dout => rel_val_wen_q); +rel_way_not_empty_reg: tri_regk +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_way_not_empty_d, + dout => rel_way_not_empty_q); +relu_lru_upd_reg: tri_rlmreg_p +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(relu_lru_upd_offset to relu_lru_upd_offset + relu_lru_upd_d'length-1), + scout => sov(relu_lru_upd_offset to relu_lru_upd_offset + relu_lru_upd_d'length-1), + din => relu_lru_upd_d, + dout => relu_lru_upd_q); +rel_lru_val_reg: tri_regk +generic map (width => 7, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_lru_val_d, + dout => rel_lru_val_q); +rel_upd_congr_cl_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_upd_congr_cl_d, + dout => rel_upd_congr_cl_q); +rel_tag_reg: tri_regk +generic map (width => 3, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_tag_d, + dout => rel_tag_q); +rel_way_qsel_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_way_qsel_offset to rel_way_qsel_offset + rel_way_qsel_d'length-1), + scout => sov(rel_way_qsel_offset to rel_way_qsel_offset + rel_way_qsel_d'length-1), + din => rel_way_qsel_d, + dout => rel_way_qsel_q); +rel_val_qsel_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_val_qsel_offset), + scout => sov(rel_val_qsel_offset), + din => rel_val_qsel_d, + dout => rel_val_qsel_q); +rel_way_early_qsel_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_way_early_qsel_offset to rel_way_early_qsel_offset + rel_way_early_qsel_d'length-1), + scout => sov(rel_way_early_qsel_offset to rel_way_early_qsel_offset + rel_way_early_qsel_d'length-1), + din => rel_way_early_qsel_d, + dout => rel_way_early_qsel_q); +rel_val_early_qsel_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_val_early_qsel_offset), + scout => sov(rel_val_early_qsel_offset), + din => rel_val_early_qsel_d, + dout => rel_val_early_qsel_q); +rel4_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel4_val_offset), + scout => sov(rel4_val_offset), + din => rel4_val_d, + dout => rel4_val_q); +rel2_mid_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel2_mid_val_offset), + scout => sov(rel2_mid_val_offset), + din => rel2_mid_val_d, + dout => rel2_mid_val_q); +rel4_retry_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel4_retry_val_offset), + scout => sov(rel4_retry_val_offset), + din => rel4_retry_val_d, + dout => rel4_retry_val_q); +rel2_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel2_fxubyp_val_d, + dout(0) => rel2_fxubyp_val_q); +rel2_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel2_relbyp_val_d, + dout(0) => rel2_relbyp_val_q); +rel2_wlock_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel2_wlock_offset to rel2_wlock_offset + rel2_wlock_d'length-1), + scout => sov(rel2_wlock_offset to rel2_wlock_offset + rel2_wlock_d'length-1), + din => rel2_wlock_d, + dout => rel2_wlock_q); +reld_q0_congr_cl_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q0_congr_cl_offset to reld_q0_congr_cl_offset + reld_q0_congr_cl_d'length-1), + scout => sov(reld_q0_congr_cl_offset to reld_q0_congr_cl_offset + reld_q0_congr_cl_d'length-1), + din => reld_q0_congr_cl_d, + dout => reld_q0_congr_cl_q); +reld_q0_way_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q0_way_offset to reld_q0_way_offset + reld_q0_way_d'length-1), + scout => sov(reld_q0_way_offset to reld_q0_way_offset + reld_q0_way_d'length-1), + din => reld_q0_way_d, + dout => reld_q0_way_q); +reld_q0_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q0_val_offset), + scout => sov(reld_q0_val_offset), + din => reld_q0_val_d, + dout => reld_q0_val_q); +reld_q0_lock_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q0_lock_offset), + scout => sov(reld_q0_lock_offset), + din => reld_q0_lock_d, + dout => reld_q0_lock_q); +reld_q1_congr_cl_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q1_congr_cl_offset to reld_q1_congr_cl_offset + reld_q1_congr_cl_d'length-1), + scout => sov(reld_q1_congr_cl_offset to reld_q1_congr_cl_offset + reld_q1_congr_cl_d'length-1), + din => reld_q1_congr_cl_d, + dout => reld_q1_congr_cl_q); +reld_q1_way_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q1_way_offset to reld_q1_way_offset + reld_q1_way_d'length-1), + scout => sov(reld_q1_way_offset to reld_q1_way_offset + reld_q1_way_d'length-1), + din => reld_q1_way_d, + dout => reld_q1_way_q); +reld_q1_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q1_val_offset), + scout => sov(reld_q1_val_offset), + din => reld_q1_val_d, + dout => reld_q1_val_q); +reld_q1_lock_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q1_lock_offset), + scout => sov(reld_q1_lock_offset), + din => reld_q1_lock_d, + dout => reld_q1_lock_q); +reld_q2_congr_cl_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q2_congr_cl_offset to reld_q2_congr_cl_offset + reld_q2_congr_cl_d'length-1), + scout => sov(reld_q2_congr_cl_offset to reld_q2_congr_cl_offset + reld_q2_congr_cl_d'length-1), + din => reld_q2_congr_cl_d, + dout => reld_q2_congr_cl_q); +reld_q2_way_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q2_way_offset to reld_q2_way_offset + reld_q2_way_d'length-1), + scout => sov(reld_q2_way_offset to reld_q2_way_offset + reld_q2_way_d'length-1), + din => reld_q2_way_d, + dout => reld_q2_way_q); +reld_q2_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q2_val_offset), + scout => sov(reld_q2_val_offset), + din => reld_q2_val_d, + dout => reld_q2_val_q); +reld_q2_lock_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q2_lock_offset), + scout => sov(reld_q2_lock_offset), + din => reld_q2_lock_d, + dout => reld_q2_lock_q); +reld_q3_congr_cl_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q3_congr_cl_offset to reld_q3_congr_cl_offset + reld_q3_congr_cl_d'length-1), + scout => sov(reld_q3_congr_cl_offset to reld_q3_congr_cl_offset + reld_q3_congr_cl_d'length-1), + din => reld_q3_congr_cl_d, + dout => reld_q3_congr_cl_q); +reld_q3_way_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q3_way_offset to reld_q3_way_offset + reld_q3_way_d'length-1), + scout => sov(reld_q3_way_offset to reld_q3_way_offset + reld_q3_way_d'length-1), + din => reld_q3_way_d, + dout => reld_q3_way_q); +reld_q3_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q3_val_offset), + scout => sov(reld_q3_val_offset), + din => reld_q3_val_d, + dout => reld_q3_val_q); +reld_q3_lock_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q3_lock_offset), + scout => sov(reld_q3_lock_offset), + din => reld_q3_lock_d, + dout => reld_q3_lock_q); +reld_q4_congr_cl_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q4_congr_cl_offset to reld_q4_congr_cl_offset + reld_q4_congr_cl_d'length-1), + scout => sov(reld_q4_congr_cl_offset to reld_q4_congr_cl_offset + reld_q4_congr_cl_d'length-1), + din => reld_q4_congr_cl_d, + dout => reld_q4_congr_cl_q); +reld_q4_way_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q4_way_offset to reld_q4_way_offset + reld_q4_way_d'length-1), + scout => sov(reld_q4_way_offset to reld_q4_way_offset + reld_q4_way_d'length-1), + din => reld_q4_way_d, + dout => reld_q4_way_q); +reld_q4_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q4_val_offset), + scout => sov(reld_q4_val_offset), + din => reld_q4_val_d, + dout => reld_q4_val_q); +reld_q4_lock_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q4_lock_offset), + scout => sov(reld_q4_lock_offset), + din => reld_q4_lock_d, + dout => reld_q4_lock_q); +reld_q5_congr_cl_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q5_congr_cl_offset to reld_q5_congr_cl_offset + reld_q5_congr_cl_d'length-1), + scout => sov(reld_q5_congr_cl_offset to reld_q5_congr_cl_offset + reld_q5_congr_cl_d'length-1), + din => reld_q5_congr_cl_d, + dout => reld_q5_congr_cl_q); +reld_q5_way_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q5_way_offset to reld_q5_way_offset + reld_q5_way_d'length-1), + scout => sov(reld_q5_way_offset to reld_q5_way_offset + reld_q5_way_d'length-1), + din => reld_q5_way_d, + dout => reld_q5_way_q); +reld_q5_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q5_val_offset), + scout => sov(reld_q5_val_offset), + din => reld_q5_val_d, + dout => reld_q5_val_q); +reld_q5_lock_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q5_lock_offset), + scout => sov(reld_q5_lock_offset), + din => reld_q5_lock_d, + dout => reld_q5_lock_q); +reld_q6_congr_cl_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q6_congr_cl_offset to reld_q6_congr_cl_offset + reld_q6_congr_cl_d'length-1), + scout => sov(reld_q6_congr_cl_offset to reld_q6_congr_cl_offset + reld_q6_congr_cl_d'length-1), + din => reld_q6_congr_cl_d, + dout => reld_q6_congr_cl_q); +reld_q6_way_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q6_way_offset to reld_q6_way_offset + reld_q6_way_d'length-1), + scout => sov(reld_q6_way_offset to reld_q6_way_offset + reld_q6_way_d'length-1), + din => reld_q6_way_d, + dout => reld_q6_way_q); +reld_q6_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q6_val_offset), + scout => sov(reld_q6_val_offset), + din => reld_q6_val_d, + dout => reld_q6_val_q); +reld_q6_lock_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q6_lock_offset), + scout => sov(reld_q6_lock_offset), + din => reld_q6_lock_d, + dout => reld_q6_lock_q); +reld_q7_congr_cl_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q7_congr_cl_offset to reld_q7_congr_cl_offset + reld_q7_congr_cl_d'length-1), + scout => sov(reld_q7_congr_cl_offset to reld_q7_congr_cl_offset + reld_q7_congr_cl_d'length-1), + din => reld_q7_congr_cl_d, + dout => reld_q7_congr_cl_q); +reld_q7_way_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q7_way_offset to reld_q7_way_offset + reld_q7_way_d'length-1), + scout => sov(reld_q7_way_offset to reld_q7_way_offset + reld_q7_way_d'length-1), + din => reld_q7_way_d, + dout => reld_q7_way_q); +reld_q7_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q7_val_offset), + scout => sov(reld_q7_val_offset), + din => reld_q7_val_d, + dout => reld_q7_val_q); +reld_q7_lock_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reld_q7_lock_offset), + scout => sov(reld_q7_lock_offset), + din => reld_q7_lock_d, + dout => reld_q7_lock_q); +rel_m_q_way_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_m_q_way_offset to rel_m_q_way_offset + rel_m_q_way_d'length-1), + scout => sov(rel_m_q_way_offset to rel_m_q_way_offset + rel_m_q_way_d'length-1), + din => rel_m_q_way_d, + dout => rel_m_q_way_q); +ex3_no_lru_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_no_lru_upd_offset), + scout => sov(ex3_no_lru_upd_offset), + din => ex3_no_lru_upd_d, + dout => ex3_no_lru_upd_q); +rel2_lock_en_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel2_lock_en_offset), + scout => sov(rel2_lock_en_offset), + din => rel2_lock_en_d, + dout => rel2_lock_en_q); +xucr0_clo_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xucr0_clo_offset), + scout => sov(xucr0_clo_offset), + din => xucr0_clo_d, + dout => xucr0_clo_q); +rel_up_way_addr_reg: tri_rlmreg_p +generic map (width => 3, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_up_way_addr_offset to rel_up_way_addr_offset + rel_up_way_addr_d'length-1), + scout => sov(rel_up_way_addr_offset to rel_up_way_addr_offset + rel_up_way_addr_d'length-1), + din => rel_up_way_addr_d, + dout => rel_up_way_addr_q); +rel24_way_dwen_stg_reg: tri_regk +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel24_way_dwen_stg_d, + dout => rel24_way_dwen_stg_q); +rel_dcarr_addr_en_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_dcarr_addr_en_offset), + scout => sov(rel_dcarr_addr_en_offset), + din => rel_dcarr_addr_en_d, + dout => rel_dcarr_addr_en_q); +rel_dcarr_val_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_dcarr_val_upd_offset), + scout => sov(rel_dcarr_val_upd_offset), + din => rel_dcarr_val_upd_d, + dout => rel_dcarr_val_upd_q); +congr_cl_ex3_ex4_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex3_ex4_cmp_offset), + scout => sov(congr_cl_ex3_ex4_cmp_offset), + din => congr_cl_ex3_ex4_cmp_d, + dout => congr_cl_ex3_ex4_cmp_q); +congr_cl_ex3_ex5_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex3_ex5_cmp_offset), + scout => sov(congr_cl_ex3_ex5_cmp_offset), + din => congr_cl_ex3_ex5_cmp_d, + dout => congr_cl_ex3_ex5_cmp_q); +congr_cl_ex3_ex6_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex3_ex6_cmp_offset), + scout => sov(congr_cl_ex3_ex6_cmp_offset), + din => congr_cl_ex3_ex6_cmp_d, + dout => congr_cl_ex3_ex6_cmp_q); +congr_cl_ex3_rel2_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex3_rel2_cmp_offset), + scout => sov(congr_cl_ex3_rel2_cmp_offset), + din => congr_cl_ex3_rel2_cmp_d, + dout => congr_cl_ex3_rel2_cmp_q); +congr_cl_ex3_rel_upd_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex3_rel_upd_cmp_offset), + scout => sov(congr_cl_ex3_rel_upd_cmp_offset), + din => congr_cl_ex3_rel_upd_cmp_d, + dout => congr_cl_ex3_rel_upd_cmp_q); +congr_cl_rel1_ex4_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_rel1_ex4_cmp_offset), + scout => sov(congr_cl_rel1_ex4_cmp_offset), + din => congr_cl_rel1_ex4_cmp_d, + dout => congr_cl_rel1_ex4_cmp_q); +congr_cl_rel1_ex5_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_rel1_ex5_cmp_offset), + scout => sov(congr_cl_rel1_ex5_cmp_offset), + din => congr_cl_rel1_ex5_cmp_d, + dout => congr_cl_rel1_ex5_cmp_q); +congr_cl_rel1_ex6_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_rel1_ex6_cmp_offset), + scout => sov(congr_cl_rel1_ex6_cmp_offset), + din => congr_cl_rel1_ex6_cmp_d, + dout => congr_cl_rel1_ex6_cmp_q); +congr_cl_rel1_rel2_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_rel1_rel2_cmp_offset), + scout => sov(congr_cl_rel1_rel2_cmp_offset), + din => congr_cl_rel1_rel2_cmp_d, + dout => congr_cl_rel1_rel2_cmp_q); +congr_cl_rel1_relu_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_rel1_relu_cmp_offset), + scout => sov(congr_cl_rel1_relu_cmp_offset), + din => congr_cl_rel1_relu_cmp_d, + dout => congr_cl_rel1_relu_cmp_q); +congr_cl_rel1_rel_upd_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_rel1_rel_upd_cmp_offset), + scout => sov(congr_cl_rel1_rel_upd_cmp_offset), + din => congr_cl_rel1_rel_upd_cmp_d, + dout => congr_cl_rel1_rel_upd_cmp_q); +congr_cl_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_act_offset), + scout => sov(congr_cl_act_offset), + din => congr_cl_act_d, + dout => congr_cl_act_q); +siv(0 TO scan_right) <= sov(1 to scan_right) & scan_in; +scan_out <= sov(0); +END XUQ_LSU_DIR_LRU32; diff --git a/rel/src/vhdl/work/xuq_lsu_dir_tag.vhdl b/rel/src/vhdl/work/xuq_lsu_dir_tag.vhdl new file mode 100644 index 0000000..09ea7ad --- /dev/null +++ b/rel/src/vhdl/work/xuq_lsu_dir_tag.vhdl @@ -0,0 +1,1111 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XU LSU L1 Data Directory Tag Wrapper + +library ibm, ieee, work, tri, support; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use tri.tri_latches_pkg.all; +use support.power_logic_pkg.all; + +-- ########################################################################################## +-- Tag Compare +-- 1) Contains an Array of Tags +-- 2) Updates Tag on Reload +-- 3) Contains Hit Logic +-- 4) Outputs Way Hit indicators +-- ########################################################################################## +entity xuq_lsu_dir_tag is +generic(expand_type : integer := 2; + dc_size : natural := 14; -- 2^14 = 16384 Bytes L1 D$ + cl_size : natural := 6; -- 2^6 = 64 Bytes CacheLines + wayDataSize : natural := 35; -- TagSize + Parity Bits + parBits : natural := 4; + real_data_add : integer := 42); +port( + + -- Stage ACT Signals + ex2_stg_act :in std_ulogic; + binv2_stg_act :in std_ulogic; + + rel_addr_early :in std_ulogic_vector(64-real_data_add to 63-cl_size); + rel_way_upd_a :in std_ulogic; + rel_way_upd_b :in std_ulogic; + rel_way_upd_c :in std_ulogic; + rel_way_upd_d :in std_ulogic; + rel_way_upd_e :in std_ulogic; + rel_way_upd_f :in std_ulogic; + rel_way_upd_g :in std_ulogic; + rel_way_upd_h :in std_ulogic; + + inv1_val :in std_ulogic; + + xu_lsu_spr_xucr0_dcdis :in std_ulogic; + + ex1_p_addr_01 :in std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + ex1_p_addr_23 :in std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + ex1_p_addr_45 :in std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + ex1_p_addr_67 :in std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + ex2_ddir_acc_instr :in std_ulogic; + + -- Error Inject + pc_xu_inj_dcachedir_parity :in std_ulogic; + + dir_arr_rd_addr_01 :out std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + dir_arr_rd_addr_23 :out std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + dir_arr_rd_addr_45 :out std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + dir_arr_rd_addr_67 :out std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + dir_arr_rd_data :in std_ulogic_vector(0 to 8*wayDataSize-1); + + dir_wr_way :out std_ulogic_vector(0 to 7); + dir_arr_wr_addr :out std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + dir_arr_wr_data :out std_ulogic_vector(64-real_data_add to 64-real_data_add+wayDataSize-1); + + ex2_wayA_tag :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex2_wayB_tag :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex2_wayC_tag :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex2_wayD_tag :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex2_wayE_tag :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex2_wayF_tag :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex2_wayG_tag :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex2_wayH_tag :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + + ex3_way_tag_par_a :out std_ulogic_vector(0 to parBits-1); + ex3_way_tag_par_b :out std_ulogic_vector(0 to parBits-1); + ex3_way_tag_par_c :out std_ulogic_vector(0 to parBits-1); + ex3_way_tag_par_d :out std_ulogic_vector(0 to parBits-1); + ex3_way_tag_par_e :out std_ulogic_vector(0 to parBits-1); + ex3_way_tag_par_f :out std_ulogic_vector(0 to parBits-1); + ex3_way_tag_par_g :out std_ulogic_vector(0 to parBits-1); + ex3_way_tag_par_h :out std_ulogic_vector(0 to parBits-1); + + ex3_tag_way_perr :out std_ulogic_vector(0 to 7); + + vdd :inout power_logic; + gnd :inout power_logic; + nclk :in clk_logic; + sg_0 :in std_ulogic; + func_sl_thold_0_b :in std_ulogic; + func_sl_force :in std_ulogic; + func_slp_sl_thold_0_b :in std_ulogic; + func_slp_sl_force :in std_ulogic; + d_mode_dc :in std_ulogic; + delay_lclkr_dc :in std_ulogic; + mpw1_dc_b :in std_ulogic; + mpw2_dc_b :in std_ulogic; + scan_in :in std_ulogic; + scan_out :out std_ulogic + ); +-- synopsys translate_off +-- synopsys translate_on +end xuq_lsu_dir_tag; +---- +architecture xuq_lsu_dir_tag of xuq_lsu_dir_tag is +---------------------------- +-- components +---------------------------- + +---------------------------- +-- signals +---------------------------- +constant uprTagBit :natural := 64-real_data_add; +constant lwrTagBit :natural := 63-(dc_size-3); +constant tagSize :natural := lwrTagBit-uprTagBit+1; +constant parExtCalc :natural := 8 - (tagSize mod 8); +constant uprCClassBit :natural := 64-(dc_size-3); +constant lwrCClassBit :natural := 63-cl_size; + +signal arr_wr_addr :std_ulogic_vector(uprCClassBit to lwrCClassBit); +signal arr_wr_data :std_ulogic_vector(uprTagBit to lwrTagBit); +signal wayA_wen :std_ulogic; +signal wayB_wen :std_ulogic; +signal wayC_wen :std_ulogic; +signal wayD_wen :std_ulogic; +signal wayE_wen :std_ulogic; +signal wayF_wen :std_ulogic; +signal wayG_wen :std_ulogic; +signal wayH_wen :std_ulogic; +signal arr_wayA_tag :std_ulogic_vector(uprTagBit to lwrTagBit); +signal arr_wayB_tag :std_ulogic_vector(uprTagBit to lwrTagBit); +signal arr_wayC_tag :std_ulogic_vector(uprTagBit to lwrTagBit); +signal arr_wayD_tag :std_ulogic_vector(uprTagBit to lwrTagBit); +signal arr_wayE_tag :std_ulogic_vector(uprTagBit to lwrTagBit); +signal arr_wayF_tag :std_ulogic_vector(uprTagBit to lwrTagBit); +signal arr_wayG_tag :std_ulogic_vector(uprTagBit to lwrTagBit); +signal arr_wayH_tag :std_ulogic_vector(uprTagBit to lwrTagBit); +signal inval_val_d :std_ulogic; +signal inval_val_q :std_ulogic; +signal arr_rd_addr_01 :std_ulogic_vector(uprCClassBit to lwrCClassBit); +signal arr_rd_addr_23 :std_ulogic_vector(uprCClassBit to lwrCClassBit); +signal arr_rd_addr_45 :std_ulogic_vector(uprCClassBit to lwrCClassBit); +signal arr_rd_addr_67 :std_ulogic_vector(uprCClassBit to lwrCClassBit); +signal ex3_en_par_chk_d :std_ulogic_vector(0 to 7); +signal ex3_en_par_chk_q :std_ulogic_vector(0 to 7); +signal spr_xucr0_dcdis_d :std_ulogic; +signal spr_xucr0_dcdis_q :std_ulogic; +signal inj_dcachedir_parity_d :std_ulogic; +signal inj_dcachedir_parity_q :std_ulogic; +signal relu_addr_d :std_ulogic_vector(uprCClassBit to lwrCClassBit); +signal relu_addr_q :std_ulogic_vector(uprCClassBit to lwrCClassBit); +signal ex2_par_gen_a_1b :std_ulogic_vector(0 to parBits-1); +signal ex2_par_gen_a_2b :std_ulogic_vector(0 to parBits-1); +signal ex2_par_gen_b_1b :std_ulogic_vector(0 to parBits-1); +signal ex2_par_gen_b_2b :std_ulogic_vector(0 to parBits-1); +signal ex2_par_gen_c_1b :std_ulogic_vector(0 to parBits-1); +signal ex2_par_gen_c_2b :std_ulogic_vector(0 to parBits-1); +signal ex2_par_gen_d_1b :std_ulogic_vector(0 to parBits-1); +signal ex2_par_gen_d_2b :std_ulogic_vector(0 to parBits-1); +signal ex2_par_gen_e_1b :std_ulogic_vector(0 to parBits-1); +signal ex2_par_gen_e_2b :std_ulogic_vector(0 to parBits-1); +signal ex2_par_gen_f_1b :std_ulogic_vector(0 to parBits-1); +signal ex2_par_gen_f_2b :std_ulogic_vector(0 to parBits-1); +signal ex2_par_gen_g_1b :std_ulogic_vector(0 to parBits-1); +signal ex2_par_gen_g_2b :std_ulogic_vector(0 to parBits-1); +signal ex2_par_gen_h_1b :std_ulogic_vector(0 to parBits-1); +signal ex2_par_gen_h_2b :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_a_1b_d :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_a_2b_d :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_a_1b_q :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_a_2b_q :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_b_1b_d :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_b_2b_d :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_b_1b_q :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_b_2b_q :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_c_1b_d :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_c_2b_d :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_c_1b_q :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_c_2b_q :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_d_1b_d :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_d_2b_d :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_d_1b_q :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_d_2b_q :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_e_1b_d :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_e_2b_d :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_e_1b_q :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_e_2b_q :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_f_1b_d :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_f_2b_d :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_f_1b_q :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_f_2b_q :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_g_1b_d :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_g_2b_d :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_g_1b_q :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_g_2b_q :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_h_1b_d :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_h_2b_d :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_h_1b_q :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_h_2b_q :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_a :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_b :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_c :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_d :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_e :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_f :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_g :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_h :std_ulogic_vector(0 to parBits-1); +signal ex3_perr_det_a :std_ulogic; +signal ex3_perr_det_b :std_ulogic; +signal ex3_perr_det_c :std_ulogic; +signal ex3_perr_det_d :std_ulogic; +signal ex3_perr_det_e :std_ulogic; +signal ex3_perr_det_f :std_ulogic; +signal ex3_perr_det_g :std_ulogic; +signal ex3_perr_det_h :std_ulogic; +signal ex2_binv2_stg_act :std_ulogic; +signal rel_wrt_data_d :std_ulogic_vector(uprTagBit to uprTagBit+wayDataSize-1); +signal rel_wrt_data_q :std_ulogic_vector(uprTagBit to uprTagBit+wayDataSize-1); +signal ex3_way_tag_par_a_d :std_ulogic_vector(0 to parBits-1); +signal ex3_way_tag_par_a_q :std_ulogic_vector(0 to parBits-1); +signal ex3_way_tag_par_b_d :std_ulogic_vector(0 to parBits-1); +signal ex3_way_tag_par_b_q :std_ulogic_vector(0 to parBits-1); +signal ex3_way_tag_par_c_d :std_ulogic_vector(0 to parBits-1); +signal ex3_way_tag_par_c_q :std_ulogic_vector(0 to parBits-1); +signal ex3_way_tag_par_d_d :std_ulogic_vector(0 to parBits-1); +signal ex3_way_tag_par_d_q :std_ulogic_vector(0 to parBits-1); +signal ex3_way_tag_par_e_d :std_ulogic_vector(0 to parBits-1); +signal ex3_way_tag_par_e_q :std_ulogic_vector(0 to parBits-1); +signal ex3_way_tag_par_f_d :std_ulogic_vector(0 to parBits-1); +signal ex3_way_tag_par_f_q :std_ulogic_vector(0 to parBits-1); +signal ex3_way_tag_par_g_d :std_ulogic_vector(0 to parBits-1); +signal ex3_way_tag_par_g_q :std_ulogic_vector(0 to parBits-1); +signal ex3_way_tag_par_h_d :std_ulogic_vector(0 to parBits-1); +signal ex3_way_tag_par_h_q :std_ulogic_vector(0 to parBits-1); +signal my_spare0_lclk :clk_logic; +signal my_spare0_d1clk :std_ulogic; +signal my_spare0_d2clk :std_ulogic; +signal my_spare0_latches_d :std_ulogic_vector(0 to 15); +signal my_spare0_latches_q :std_ulogic_vector(0 to 15); +signal my_spare1_lclk :clk_logic; +signal my_spare1_d1clk :std_ulogic; +signal my_spare1_d2clk :std_ulogic; +signal my_spare1_latches_d :std_ulogic_vector(0 to 15); +signal my_spare1_latches_q :std_ulogic_vector(0 to 15); + +---------------------------- +-- constants +---------------------------- +constant inval_val_offset :natural := 0; +constant ex3_en_par_chk_offset :natural := inval_val_offset + 1; +constant spr_xucr0_dcdis_offset :natural := ex3_en_par_chk_offset + 8; +constant inj_dcachedir_parity_offset :natural := spr_xucr0_dcdis_offset + 1; +constant relu_addr_offset :natural := inj_dcachedir_parity_offset + 1; +constant rel_wrt_data_offset :natural := relu_addr_offset + lwrCClassBit-uprCClassBit+1; +constant ex3_par_gen_a_1b_offset :natural := rel_wrt_data_offset + wayDataSize; +constant ex3_par_gen_a_2b_offset :natural := ex3_par_gen_a_1b_offset + parBits; +constant ex3_par_gen_b_1b_offset :natural := ex3_par_gen_a_2b_offset + parBits; +constant ex3_par_gen_b_2b_offset :natural := ex3_par_gen_b_1b_offset + parBits; +constant ex3_par_gen_c_1b_offset :natural := ex3_par_gen_b_2b_offset + parBits; +constant ex3_par_gen_c_2b_offset :natural := ex3_par_gen_c_1b_offset + parBits; +constant ex3_par_gen_d_1b_offset :natural := ex3_par_gen_c_2b_offset + parBits; +constant ex3_par_gen_d_2b_offset :natural := ex3_par_gen_d_1b_offset + parBits; +constant ex3_par_gen_e_1b_offset :natural := ex3_par_gen_d_2b_offset + parBits; +constant ex3_par_gen_e_2b_offset :natural := ex3_par_gen_e_1b_offset + parBits; +constant ex3_par_gen_f_1b_offset :natural := ex3_par_gen_e_2b_offset + parBits; +constant ex3_par_gen_f_2b_offset :natural := ex3_par_gen_f_1b_offset + parBits; +constant ex3_par_gen_g_1b_offset :natural := ex3_par_gen_f_2b_offset + parBits; +constant ex3_par_gen_g_2b_offset :natural := ex3_par_gen_g_1b_offset + parBits; +constant ex3_par_gen_h_1b_offset :natural := ex3_par_gen_g_2b_offset + parBits; +constant ex3_par_gen_h_2b_offset :natural := ex3_par_gen_h_1b_offset + parBits; +constant ex3_way_tag_par_a_offset :natural := ex3_par_gen_h_2b_offset + parBits; +constant ex3_way_tag_par_b_offset :natural := ex3_way_tag_par_a_offset + parBits; +constant ex3_way_tag_par_c_offset :natural := ex3_way_tag_par_b_offset + parBits; +constant ex3_way_tag_par_d_offset :natural := ex3_way_tag_par_c_offset + parBits; +constant ex3_way_tag_par_e_offset :natural := ex3_way_tag_par_d_offset + parBits; +constant ex3_way_tag_par_f_offset :natural := ex3_way_tag_par_e_offset + parBits; +constant ex3_way_tag_par_g_offset :natural := ex3_way_tag_par_f_offset + parBits; +constant ex3_way_tag_par_h_offset :natural := ex3_way_tag_par_g_offset + parBits; +constant my_spare0_latches_offset :natural := ex3_way_tag_par_h_offset + parBits; +constant my_spare1_latches_offset :natural := my_spare0_latches_offset + 16; +constant scan_right :natural := my_spare1_latches_offset + 16 - 1; + +signal tiup :std_ulogic; +signal siv :std_ulogic_vector(0 to scan_right); +signal sov :std_ulogic_vector(0 to scan_right); + +begin +-- #################################################### +-- Inputs +-- #################################################### + +tiup <= '1'; +ex2_binv2_stg_act <= ex2_stg_act or binv2_stg_act; + +relu_addr_d <= rel_addr_early(uprCClassBit to lwrCClassBit); +wayA_wen <= rel_way_upd_a; +wayB_wen <= rel_way_upd_b; +wayC_wen <= rel_way_upd_c; +wayD_wen <= rel_way_upd_d; +wayE_wen <= rel_way_upd_e; +wayF_wen <= rel_way_upd_f; +wayG_wen <= rel_way_upd_g; +wayH_wen <= rel_way_upd_h; + +inval_val_d <= inv1_val; + +spr_xucr0_dcdis_d <= xu_lsu_spr_xucr0_dcdis; +inj_dcachedir_parity_d <= pc_xu_inj_dcachedir_parity; + +-- #################################################### +-- Dcache Number of Cachelines Configurations +-- #################################################### + +arr_wr_addr <= relu_addr_q(uprCClassBit to lwrCClassBit); +arr_wr_data <= rel_addr_early(uprTagBit to lwrTagBit); + +-- Select Between Back-Invalidate Pipe or Execution Pipe +arr_rd_addr_01 <= ex1_p_addr_01; +arr_rd_addr_23 <= ex1_p_addr_23; +arr_rd_addr_45 <= ex1_p_addr_45; +arr_rd_addr_67 <= ex1_p_addr_67; + +-- #################################################### +-- Tag Array Access +-- 1) Contains the Array of Tags +-- #################################################### + +l1dcta : entity work.xuq_lsu_dir_tag_arr(xuq_lsu_dir_tag_arr) +GENERIC MAP(expand_type => expand_type, + dc_size => dc_size, + cl_size => cl_size, + wayDataSize => wayDataSize, + parityBits => parBits, + real_data_add => real_data_add) +port map( + + waddr => arr_wr_addr, + wdata => arr_wr_data, + way_wen_a => wayA_wen, + way_wen_b => wayB_wen, + way_wen_c => wayC_wen, + way_wen_d => wayD_wen, + way_wen_e => wayE_wen, + way_wen_f => wayF_wen, + way_wen_g => wayG_wen, + way_wen_h => wayH_wen, + + raddr_01 => arr_rd_addr_01, + raddr_23 => arr_rd_addr_23, + raddr_45 => arr_rd_addr_45, + raddr_67 => arr_rd_addr_67, + inj_parity_err => inj_dcachedir_parity_q, + + dir_arr_rd_addr_01 => dir_arr_rd_addr_01, + dir_arr_rd_addr_23 => dir_arr_rd_addr_23, + dir_arr_rd_addr_45 => dir_arr_rd_addr_45, + dir_arr_rd_addr_67 => dir_arr_rd_addr_67, + dir_arr_rd_data => dir_arr_rd_data, + + dir_wr_way => dir_wr_way, + dir_arr_wr_addr => dir_arr_wr_addr, + dir_arr_wr_data => rel_wrt_data_d, + + way_tag_a => arr_wayA_tag, + way_tag_b => arr_wayB_tag, + way_tag_c => arr_wayC_tag, + way_tag_d => arr_wayD_tag, + way_tag_e => arr_wayE_tag, + way_tag_f => arr_wayF_tag, + way_tag_g => arr_wayG_tag, + way_tag_h => arr_wayH_tag, + + way_arr_par_a => ex3_way_tag_par_a_d, + way_arr_par_b => ex3_way_tag_par_b_d, + way_arr_par_c => ex3_way_tag_par_c_d, + way_arr_par_d => ex3_way_tag_par_d_d, + way_arr_par_e => ex3_way_tag_par_e_d, + way_arr_par_f => ex3_way_tag_par_f_d, + way_arr_par_g => ex3_way_tag_par_g_d, + way_arr_par_h => ex3_way_tag_par_h_d, + + par_gen_a_1b => ex2_par_gen_a_1b, + par_gen_a_2b => ex2_par_gen_a_2b, + par_gen_b_1b => ex2_par_gen_b_1b, + par_gen_b_2b => ex2_par_gen_b_2b, + par_gen_c_1b => ex2_par_gen_c_1b, + par_gen_c_2b => ex2_par_gen_c_2b, + par_gen_d_1b => ex2_par_gen_d_1b, + par_gen_d_2b => ex2_par_gen_d_2b, + par_gen_e_1b => ex2_par_gen_e_1b, + par_gen_e_2b => ex2_par_gen_e_2b, + par_gen_f_1b => ex2_par_gen_f_1b, + par_gen_f_2b => ex2_par_gen_f_2b, + par_gen_g_1b => ex2_par_gen_g_1b, + par_gen_g_2b => ex2_par_gen_g_2b, + par_gen_h_1b => ex2_par_gen_h_1b, + par_gen_h_2b => ex2_par_gen_h_2b +); + +-- #################################################### +-- Parity Reporting +-- #################################################### + +-- Parity Check Enable +ex3_en_par_chk_d(0) <= (ex2_ddir_acc_instr or inval_val_q) and not spr_xucr0_dcdis_q; +ex3_en_par_chk_d(1) <= (ex2_ddir_acc_instr or inval_val_q) and not spr_xucr0_dcdis_q; +ex3_en_par_chk_d(2) <= (ex2_ddir_acc_instr or inval_val_q) and not spr_xucr0_dcdis_q; +ex3_en_par_chk_d(3) <= (ex2_ddir_acc_instr or inval_val_q) and not spr_xucr0_dcdis_q; +ex3_en_par_chk_d(4) <= (ex2_ddir_acc_instr or inval_val_q) and not spr_xucr0_dcdis_q; +ex3_en_par_chk_d(5) <= (ex2_ddir_acc_instr or inval_val_q) and not spr_xucr0_dcdis_q; +ex3_en_par_chk_d(6) <= (ex2_ddir_acc_instr or inval_val_q) and not spr_xucr0_dcdis_q; +ex3_en_par_chk_d(7) <= (ex2_ddir_acc_instr or inval_val_q) and not spr_xucr0_dcdis_q; + +-- Latching up Parity Bits +ex3_par_gen_a_1b_d <= ex2_par_gen_a_1b; +ex3_par_gen_a_2b_d <= ex2_par_gen_a_2b; +ex3_par_gen_b_1b_d <= ex2_par_gen_b_1b; +ex3_par_gen_b_2b_d <= ex2_par_gen_b_2b; +ex3_par_gen_c_1b_d <= ex2_par_gen_c_1b; +ex3_par_gen_c_2b_d <= ex2_par_gen_c_2b; +ex3_par_gen_d_1b_d <= ex2_par_gen_d_1b; +ex3_par_gen_d_2b_d <= ex2_par_gen_d_2b; +ex3_par_gen_e_1b_d <= ex2_par_gen_e_1b; +ex3_par_gen_e_2b_d <= ex2_par_gen_e_2b; +ex3_par_gen_f_1b_d <= ex2_par_gen_f_1b; +ex3_par_gen_f_2b_d <= ex2_par_gen_f_2b; +ex3_par_gen_g_1b_d <= ex2_par_gen_g_1b; +ex3_par_gen_g_2b_d <= ex2_par_gen_g_2b; +ex3_par_gen_h_1b_d <= ex2_par_gen_h_1b; +ex3_par_gen_h_2b_d <= ex2_par_gen_h_2b; + +-- Parity Generated +ex3_par_gen_a <= ex3_par_gen_a_1b_q xor ex3_par_gen_a_2b_q; +ex3_par_gen_b <= ex3_par_gen_b_1b_q xor ex3_par_gen_b_2b_q; +ex3_par_gen_c <= ex3_par_gen_c_1b_q xor ex3_par_gen_c_2b_q; +ex3_par_gen_d <= ex3_par_gen_d_1b_q xor ex3_par_gen_d_2b_q; +ex3_par_gen_e <= ex3_par_gen_e_1b_q xor ex3_par_gen_e_2b_q; +ex3_par_gen_f <= ex3_par_gen_f_1b_q xor ex3_par_gen_f_2b_q; +ex3_par_gen_g <= ex3_par_gen_g_1b_q xor ex3_par_gen_g_2b_q; +ex3_par_gen_h <= ex3_par_gen_h_1b_q xor ex3_par_gen_h_2b_q; + +-- Parity Error Detected +ex3_perr_det_a <= or_reduce(ex3_way_tag_par_a_q xor ex3_par_gen_a) and ex3_en_par_chk_q(0); +ex3_perr_det_b <= or_reduce(ex3_way_tag_par_b_q xor ex3_par_gen_b) and ex3_en_par_chk_q(1); +ex3_perr_det_c <= or_reduce(ex3_way_tag_par_c_q xor ex3_par_gen_c) and ex3_en_par_chk_q(2); +ex3_perr_det_d <= or_reduce(ex3_way_tag_par_d_q xor ex3_par_gen_d) and ex3_en_par_chk_q(3); +ex3_perr_det_e <= or_reduce(ex3_way_tag_par_e_q xor ex3_par_gen_e) and ex3_en_par_chk_q(4); +ex3_perr_det_f <= or_reduce(ex3_way_tag_par_f_q xor ex3_par_gen_f) and ex3_en_par_chk_q(5); +ex3_perr_det_g <= or_reduce(ex3_way_tag_par_g_q xor ex3_par_gen_g) and ex3_en_par_chk_q(6); +ex3_perr_det_h <= or_reduce(ex3_way_tag_par_h_q xor ex3_par_gen_h) and ex3_en_par_chk_q(7); + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Spare Latches +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +my_spare0_latches_d <= not my_spare0_latches_q; +my_spare1_latches_d <= not my_spare1_latches_q; + +-- #################################################### +-- Outputs +-- #################################################### +ex2_wayA_tag <= arr_wayA_tag; +ex2_wayB_tag <= arr_wayB_tag; +ex2_wayC_tag <= arr_wayC_tag; +ex2_wayD_tag <= arr_wayD_tag; +ex2_wayE_tag <= arr_wayE_tag; +ex2_wayF_tag <= arr_wayF_tag; +ex2_wayG_tag <= arr_wayG_tag; +ex2_wayH_tag <= arr_wayH_tag; + +dir_arr_wr_data <= rel_wrt_data_q; + +ex3_way_tag_par_a <= ex3_way_tag_par_a_q; +ex3_way_tag_par_b <= ex3_way_tag_par_b_q; +ex3_way_tag_par_c <= ex3_way_tag_par_c_q; +ex3_way_tag_par_d <= ex3_way_tag_par_d_q; +ex3_way_tag_par_e <= ex3_way_tag_par_e_q; +ex3_way_tag_par_f <= ex3_way_tag_par_f_q; +ex3_way_tag_par_g <= ex3_way_tag_par_g_q; +ex3_way_tag_par_h <= ex3_way_tag_par_h_q; + +ex3_tag_way_perr <= ex3_perr_det_a & ex3_perr_det_b & ex3_perr_det_c & ex3_perr_det_d & + ex3_perr_det_e & ex3_perr_det_f & ex3_perr_det_g & ex3_perr_det_h; + +-- #################################################### +-- Back Invalidate Registers +-- #################################################### + +inval_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(inval_val_offset), + scout => sov(inval_val_offset), + din => inval_val_d, + dout => inval_val_q); + +ex3_en_par_chk_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_en_par_chk_offset to ex3_en_par_chk_offset + ex3_en_par_chk_d'length-1), + scout => sov(ex3_en_par_chk_offset to ex3_en_par_chk_offset + ex3_en_par_chk_d'length-1), + din => ex3_en_par_chk_d, + dout => ex3_en_par_chk_q); + +spr_xucr0_dcdis_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(spr_xucr0_dcdis_offset), + scout => sov(spr_xucr0_dcdis_offset), + din => spr_xucr0_dcdis_d, + dout => spr_xucr0_dcdis_q); + +inj_dcachedir_parity_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(inj_dcachedir_parity_offset), + scout => sov(inj_dcachedir_parity_offset), + din => inj_dcachedir_parity_d, + dout => inj_dcachedir_parity_q); + +relu_addr_reg: tri_rlmreg_p +generic map (width => lwrCClassBit-uprCClassBit+1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(relu_addr_offset to relu_addr_offset + relu_addr_d'length-1), + scout => sov(relu_addr_offset to relu_addr_offset + relu_addr_d'length-1), + din => relu_addr_d, + dout => relu_addr_q); + +rel_wrt_data_reg: tri_rlmreg_p +generic map (width => wayDataSize, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_wrt_data_offset to rel_wrt_data_offset + rel_wrt_data_d'length-1), + scout => sov(rel_wrt_data_offset to rel_wrt_data_offset + rel_wrt_data_d'length-1), + din => rel_wrt_data_d, + dout => rel_wrt_data_q); + +ex3_par_gen_a_1b_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_par_gen_a_1b_offset to ex3_par_gen_a_1b_offset + ex3_par_gen_a_1b_d'length-1), + scout => sov(ex3_par_gen_a_1b_offset to ex3_par_gen_a_1b_offset + ex3_par_gen_a_1b_d'length-1), + din => ex3_par_gen_a_1b_d, + dout => ex3_par_gen_a_1b_q); + +ex3_par_gen_a_2b_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_par_gen_a_2b_offset to ex3_par_gen_a_2b_offset + ex3_par_gen_a_2b_d'length-1), + scout => sov(ex3_par_gen_a_2b_offset to ex3_par_gen_a_2b_offset + ex3_par_gen_a_2b_d'length-1), + din => ex3_par_gen_a_2b_d, + dout => ex3_par_gen_a_2b_q); + +ex3_par_gen_b_1b_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_par_gen_b_1b_offset to ex3_par_gen_b_1b_offset + ex3_par_gen_b_1b_d'length-1), + scout => sov(ex3_par_gen_b_1b_offset to ex3_par_gen_b_1b_offset + ex3_par_gen_b_1b_d'length-1), + din => ex3_par_gen_b_1b_d, + dout => ex3_par_gen_b_1b_q); + +ex3_par_gen_b_2b_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_par_gen_b_2b_offset to ex3_par_gen_b_2b_offset + ex3_par_gen_b_2b_d'length-1), + scout => sov(ex3_par_gen_b_2b_offset to ex3_par_gen_b_2b_offset + ex3_par_gen_b_2b_d'length-1), + din => ex3_par_gen_b_2b_d, + dout => ex3_par_gen_b_2b_q); + +ex3_par_gen_c_1b_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_par_gen_c_1b_offset to ex3_par_gen_c_1b_offset + ex3_par_gen_c_1b_d'length-1), + scout => sov(ex3_par_gen_c_1b_offset to ex3_par_gen_c_1b_offset + ex3_par_gen_c_1b_d'length-1), + din => ex3_par_gen_c_1b_d, + dout => ex3_par_gen_c_1b_q); + +ex3_par_gen_c_2b_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_par_gen_c_2b_offset to ex3_par_gen_c_2b_offset + ex3_par_gen_c_2b_d'length-1), + scout => sov(ex3_par_gen_c_2b_offset to ex3_par_gen_c_2b_offset + ex3_par_gen_c_2b_d'length-1), + din => ex3_par_gen_c_2b_d, + dout => ex3_par_gen_c_2b_q); + +ex3_par_gen_d_1b_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_par_gen_d_1b_offset to ex3_par_gen_d_1b_offset + ex3_par_gen_d_1b_d'length-1), + scout => sov(ex3_par_gen_d_1b_offset to ex3_par_gen_d_1b_offset + ex3_par_gen_d_1b_d'length-1), + din => ex3_par_gen_d_1b_d, + dout => ex3_par_gen_d_1b_q); + +ex3_par_gen_d_2b_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_par_gen_d_2b_offset to ex3_par_gen_d_2b_offset + ex3_par_gen_d_2b_d'length-1), + scout => sov(ex3_par_gen_d_2b_offset to ex3_par_gen_d_2b_offset + ex3_par_gen_d_2b_d'length-1), + din => ex3_par_gen_d_2b_d, + dout => ex3_par_gen_d_2b_q); + +ex3_par_gen_e_1b_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_par_gen_e_1b_offset to ex3_par_gen_e_1b_offset + ex3_par_gen_e_1b_d'length-1), + scout => sov(ex3_par_gen_e_1b_offset to ex3_par_gen_e_1b_offset + ex3_par_gen_e_1b_d'length-1), + din => ex3_par_gen_e_1b_d, + dout => ex3_par_gen_e_1b_q); + +ex3_par_gen_e_2b_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_par_gen_e_2b_offset to ex3_par_gen_e_2b_offset + ex3_par_gen_e_2b_d'length-1), + scout => sov(ex3_par_gen_e_2b_offset to ex3_par_gen_e_2b_offset + ex3_par_gen_e_2b_d'length-1), + din => ex3_par_gen_e_2b_d, + dout => ex3_par_gen_e_2b_q); + +ex3_par_gen_f_1b_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_par_gen_f_1b_offset to ex3_par_gen_f_1b_offset + ex3_par_gen_f_1b_d'length-1), + scout => sov(ex3_par_gen_f_1b_offset to ex3_par_gen_f_1b_offset + ex3_par_gen_f_1b_d'length-1), + din => ex3_par_gen_f_1b_d, + dout => ex3_par_gen_f_1b_q); + +ex3_par_gen_f_2b_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_par_gen_f_2b_offset to ex3_par_gen_f_2b_offset + ex3_par_gen_f_2b_d'length-1), + scout => sov(ex3_par_gen_f_2b_offset to ex3_par_gen_f_2b_offset + ex3_par_gen_f_2b_d'length-1), + din => ex3_par_gen_f_2b_d, + dout => ex3_par_gen_f_2b_q); + +ex3_par_gen_g_1b_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_par_gen_g_1b_offset to ex3_par_gen_g_1b_offset + ex3_par_gen_g_1b_d'length-1), + scout => sov(ex3_par_gen_g_1b_offset to ex3_par_gen_g_1b_offset + ex3_par_gen_g_1b_d'length-1), + din => ex3_par_gen_g_1b_d, + dout => ex3_par_gen_g_1b_q); + +ex3_par_gen_g_2b_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_par_gen_g_2b_offset to ex3_par_gen_g_2b_offset + ex3_par_gen_g_2b_d'length-1), + scout => sov(ex3_par_gen_g_2b_offset to ex3_par_gen_g_2b_offset + ex3_par_gen_g_2b_d'length-1), + din => ex3_par_gen_g_2b_d, + dout => ex3_par_gen_g_2b_q); + +ex3_par_gen_h_1b_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_par_gen_h_1b_offset to ex3_par_gen_h_1b_offset + ex3_par_gen_h_1b_d'length-1), + scout => sov(ex3_par_gen_h_1b_offset to ex3_par_gen_h_1b_offset + ex3_par_gen_h_1b_d'length-1), + din => ex3_par_gen_h_1b_d, + dout => ex3_par_gen_h_1b_q); + +ex3_par_gen_h_2b_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_par_gen_h_2b_offset to ex3_par_gen_h_2b_offset + ex3_par_gen_h_2b_d'length-1), + scout => sov(ex3_par_gen_h_2b_offset to ex3_par_gen_h_2b_offset + ex3_par_gen_h_2b_d'length-1), + din => ex3_par_gen_h_2b_d, + dout => ex3_par_gen_h_2b_q); + +ex3_way_tag_par_a_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_way_tag_par_a_offset to ex3_way_tag_par_a_offset + ex3_way_tag_par_a_d'length-1), + scout => sov(ex3_way_tag_par_a_offset to ex3_way_tag_par_a_offset + ex3_way_tag_par_a_d'length-1), + din => ex3_way_tag_par_a_d, + dout => ex3_way_tag_par_a_q); + +ex3_way_tag_par_b_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_way_tag_par_b_offset to ex3_way_tag_par_b_offset + ex3_way_tag_par_b_d'length-1), + scout => sov(ex3_way_tag_par_b_offset to ex3_way_tag_par_b_offset + ex3_way_tag_par_b_d'length-1), + din => ex3_way_tag_par_b_d, + dout => ex3_way_tag_par_b_q); + +ex3_way_tag_par_c_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_way_tag_par_c_offset to ex3_way_tag_par_c_offset + ex3_way_tag_par_c_d'length-1), + scout => sov(ex3_way_tag_par_c_offset to ex3_way_tag_par_c_offset + ex3_way_tag_par_c_d'length-1), + din => ex3_way_tag_par_c_d, + dout => ex3_way_tag_par_c_q); + +ex3_way_tag_par_d_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_way_tag_par_d_offset to ex3_way_tag_par_d_offset + ex3_way_tag_par_d_d'length-1), + scout => sov(ex3_way_tag_par_d_offset to ex3_way_tag_par_d_offset + ex3_way_tag_par_d_d'length-1), + din => ex3_way_tag_par_d_d, + dout => ex3_way_tag_par_d_q); + +ex3_way_tag_par_e_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_way_tag_par_e_offset to ex3_way_tag_par_e_offset + ex3_way_tag_par_e_d'length-1), + scout => sov(ex3_way_tag_par_e_offset to ex3_way_tag_par_e_offset + ex3_way_tag_par_e_d'length-1), + din => ex3_way_tag_par_e_d, + dout => ex3_way_tag_par_e_q); + +ex3_way_tag_par_f_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_way_tag_par_f_offset to ex3_way_tag_par_f_offset + ex3_way_tag_par_f_d'length-1), + scout => sov(ex3_way_tag_par_f_offset to ex3_way_tag_par_f_offset + ex3_way_tag_par_f_d'length-1), + din => ex3_way_tag_par_f_d, + dout => ex3_way_tag_par_f_q); + +ex3_way_tag_par_g_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_way_tag_par_g_offset to ex3_way_tag_par_g_offset + ex3_way_tag_par_g_d'length-1), + scout => sov(ex3_way_tag_par_g_offset to ex3_way_tag_par_g_offset + ex3_way_tag_par_g_d'length-1), + din => ex3_way_tag_par_g_d, + dout => ex3_way_tag_par_g_q); + +ex3_way_tag_par_h_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_way_tag_par_h_offset to ex3_way_tag_par_h_offset + ex3_way_tag_par_h_d'length-1), + scout => sov(ex3_way_tag_par_h_offset to ex3_way_tag_par_h_offset + ex3_way_tag_par_h_d'length-1), + din => ex3_way_tag_par_h_d, + dout => ex3_way_tag_par_h_q); + +my_spare0_lcb : entity tri.tri_lcbnd(tri_lcbnd) +generic map (expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + d1clk => my_spare0_d1clk, + d2clk => my_spare0_d2clk, + lclk => my_spare0_lclk); +my_spare0_latches_reg: entity tri.tri_inv_nlats(tri_inv_nlats) +generic map (width => 16, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + lclk => my_spare0_lclk, + d1clk => my_spare0_d1clk, + d2clk => my_spare0_d2clk, + scanin => siv(my_spare0_latches_offset to my_spare0_latches_offset + my_spare0_latches_d'length-1), + scanout => sov(my_spare0_latches_offset to my_spare0_latches_offset + my_spare0_latches_d'length-1), + d => my_spare0_latches_d, + qb => my_spare0_latches_q); + +my_spare1_lcb : entity tri.tri_lcbnd(tri_lcbnd) +generic map (expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + d1clk => my_spare1_d1clk, + d2clk => my_spare1_d2clk, + lclk => my_spare1_lclk); +my_spare1_latches_reg: entity tri.tri_inv_nlats(tri_inv_nlats) +generic map (width => 16, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + lclk => my_spare1_lclk, + d1clk => my_spare1_d1clk, + d2clk => my_spare1_d2clk, + scanin => siv(my_spare1_latches_offset to my_spare1_latches_offset + my_spare1_latches_d'length-1), + scanout => sov(my_spare1_latches_offset to my_spare1_latches_offset + my_spare1_latches_d'length-1), + d => my_spare1_latches_d, + qb => my_spare1_latches_q); + +siv(0 to scan_right) <= sov(1 to scan_right) & scan_in; +scan_out <= sov(0); +end xuq_lsu_dir_tag; diff --git a/rel/src/vhdl/work/xuq_lsu_dir_tag_arr.vhdl b/rel/src/vhdl/work/xuq_lsu_dir_tag_arr.vhdl new file mode 100644 index 0000000..1c02b42 --- /dev/null +++ b/rel/src/vhdl/work/xuq_lsu_dir_tag_arr.vhdl @@ -0,0 +1,519 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XU LSU L1 Data Directory Tag Array +-- + +library ibm, ieee, work, tri, support; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use tri.tri_latches_pkg.all; +use support.power_logic_pkg.all; + +-- ########################################################################################## +-- Tag Compare +-- 1) Contains an Array of Tags +-- 2) Updates Tag on Reload +-- ########################################################################################## + +entity xuq_lsu_dir_tag_arr is +generic(expand_type : integer := 2; -- 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) + dc_size : natural := 14; -- 2^14 = 16384 Bytes L1 D$ + cl_size : natural := 6; -- 2^6 = 64 Bytes CacheLines + wayDataSize : natural := 35; -- TagSize + Parity Bits + parityBits : natural := 4; -- Parity Bits + real_data_add : integer := 42); -- 42 bit real address + PORT ( + + -- Write Path + waddr :in std_ulogic_vector(64-(dc_size-3) to 63-cl_size); -- Reload Addr, will update a Tag + -- Reload Tag, will update a Tag with this value + wdata :in std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + way_wen_a :in std_ulogic; -- Reload Way A Write Enable + way_wen_b :in std_ulogic; -- Reload Way B Write Enable + way_wen_c :in std_ulogic; -- Reload Way C Write Enable + way_wen_d :in std_ulogic; -- Reload Way D Write Enable + way_wen_e :in std_ulogic; -- Reload Way E Write Enable + way_wen_f :in std_ulogic; -- Reload Way F Write Enable + way_wen_g :in std_ulogic; -- Reload Way G Write Enable + way_wen_h :in std_ulogic; -- Reload Way H Write Enable + + -- Read Path + raddr_01 :in std_ulogic_vector(64-(dc_size-3) to 63-cl_size); -- Addr for Tag Read + raddr_23 :in std_ulogic_vector(64-(dc_size-3) to 63-cl_size); -- Addr for Tag Read + raddr_45 :in std_ulogic_vector(64-(dc_size-3) to 63-cl_size); -- Addr for Tag Read + raddr_67 :in std_ulogic_vector(64-(dc_size-3) to 63-cl_size); -- Addr for Tag Read + inj_parity_err :in std_ulogic; + + -- Directory Array Read Data + dir_arr_rd_addr_01 :out std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + dir_arr_rd_addr_23 :out std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + dir_arr_rd_addr_45 :out std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + dir_arr_rd_addr_67 :out std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + dir_arr_rd_data :in std_ulogic_vector(0 to 8*wayDataSize-1); + + -- Directory Array Write Controls + dir_wr_way :out std_ulogic_vector(0 to 7); + dir_arr_wr_addr :out std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + dir_arr_wr_data :out std_ulogic_vector(64-real_data_add to 64-real_data_add+wayDataSize-1); + + -- Way A Tag Data + way_tag_a :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + -- Way B Tag Data + way_tag_b :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + -- Way C Tag Data + way_tag_c :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + -- Way D Tag Data + way_tag_d :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + -- Way E Tag Data + way_tag_e :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + -- Way F Tag Data + way_tag_f :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + -- Way G Tag Data + way_tag_g :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + -- Way H Tag Data + way_tag_h :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + + -- Way A Tag Parity + way_arr_par_a :out std_ulogic_vector(0 to parityBits-1); + -- Way B Tag Parity + way_arr_par_b :out std_ulogic_vector(0 to parityBits-1); + -- Way C Tag Parity + way_arr_par_c :out std_ulogic_vector(0 to parityBits-1); + -- Way D Tag Parity + way_arr_par_d :out std_ulogic_vector(0 to parityBits-1); + -- Way E Tag Parity + way_arr_par_e :out std_ulogic_vector(0 to parityBits-1); + -- Way F Tag Parity + way_arr_par_f :out std_ulogic_vector(0 to parityBits-1); + -- Way G Tag Parity + way_arr_par_g :out std_ulogic_vector(0 to parityBits-1); + -- Way H Tag Parity + way_arr_par_h :out std_ulogic_vector(0 to parityBits-1); + + -- Parity Error Detected + par_gen_a_1b :out std_ulogic_vector(0 to parityBits-1); + par_gen_a_2b :out std_ulogic_vector(0 to parityBits-1); + par_gen_b_1b :out std_ulogic_vector(0 to parityBits-1); + par_gen_b_2b :out std_ulogic_vector(0 to parityBits-1); + par_gen_c_1b :out std_ulogic_vector(0 to parityBits-1); + par_gen_c_2b :out std_ulogic_vector(0 to parityBits-1); + par_gen_d_1b :out std_ulogic_vector(0 to parityBits-1); + par_gen_d_2b :out std_ulogic_vector(0 to parityBits-1); + par_gen_e_1b :out std_ulogic_vector(0 to parityBits-1); + par_gen_e_2b :out std_ulogic_vector(0 to parityBits-1); + par_gen_f_1b :out std_ulogic_vector(0 to parityBits-1); + par_gen_f_2b :out std_ulogic_vector(0 to parityBits-1); + par_gen_g_1b :out std_ulogic_vector(0 to parityBits-1); + par_gen_g_2b :out std_ulogic_vector(0 to parityBits-1); + par_gen_h_1b :out std_ulogic_vector(0 to parityBits-1); + par_gen_h_2b :out std_ulogic_vector(0 to parityBits-1) + ); +-- synopsys translate_off +-- synopsys translate_on +end xuq_lsu_dir_tag_arr; +---- +architecture xuq_lsu_dir_tag_arr of xuq_lsu_dir_tag_arr is + +---------------------------- +-- components +---------------------------- + +---------------------------- +-- constants +---------------------------- +constant uprTagBit :natural := 64-real_data_add; +constant lwrTagBit :natural := 63-(dc_size-3); +constant tagSize :natural := lwrTagBit-uprTagBit+1; +constant parExtCalc :natural := 8 - (tagSize mod 8); +constant parBits :natural := (tagSize+parExtCalc) / 8; + +---------------------------- +-- signals +---------------------------- +signal wr_data :std_ulogic_vector(uprTagBit to lwrTagBit); +signal wr_wayA :std_ulogic; +signal wr_wayB :std_ulogic; +signal wr_wayC :std_ulogic; +signal wr_wayD :std_ulogic; +signal wr_wayE :std_ulogic; +signal wr_wayF :std_ulogic; +signal wr_wayG :std_ulogic; +signal wr_wayH :std_ulogic; +signal wr_way :std_ulogic_vector(0 to 7); +signal rd_wayA :std_ulogic_vector(uprTagBit to lwrTagBit); +signal rd_wayB :std_ulogic_vector(uprTagBit to lwrTagBit); +signal rd_wayC :std_ulogic_vector(uprTagBit to lwrTagBit); +signal rd_wayD :std_ulogic_vector(uprTagBit to lwrTagBit); +signal rd_wayE :std_ulogic_vector(uprTagBit to lwrTagBit); +signal rd_wayF :std_ulogic_vector(uprTagBit to lwrTagBit); +signal rd_wayG :std_ulogic_vector(uprTagBit to lwrTagBit); +signal rd_wayH :std_ulogic_vector(uprTagBit to lwrTagBit); +signal arr_rd_data :std_ulogic_vector(0 to 8*wayDataSize-1); +signal arr_parity :std_ulogic_vector(0 to parBits-1); +signal extra_byte_par :std_ulogic_vector(0 to 7); +signal arr_wr_data :std_ulogic_vector(uprTagBit to lwrTagBit+parBits); +signal rd_parA :std_ulogic_vector(0 to parBits-1); +signal rd_parB :std_ulogic_vector(0 to parBits-1); +signal rd_parC :std_ulogic_vector(0 to parBits-1); +signal rd_parD :std_ulogic_vector(0 to parBits-1); +signal rd_parE :std_ulogic_vector(0 to parBits-1); +signal rd_parF :std_ulogic_vector(0 to parBits-1); +signal rd_parG :std_ulogic_vector(0 to parBits-1); +signal rd_parH :std_ulogic_vector(0 to parBits-1); +signal extra_tagA_par :std_ulogic_vector(0 to 7); +signal extra_tagB_par :std_ulogic_vector(0 to 7); +signal extra_tagC_par :std_ulogic_vector(0 to 7); +signal extra_tagD_par :std_ulogic_vector(0 to 7); +signal extra_tagE_par :std_ulogic_vector(0 to 7); +signal extra_tagF_par :std_ulogic_vector(0 to 7); +signal extra_tagG_par :std_ulogic_vector(0 to 7); +signal extra_tagH_par :std_ulogic_vector(0 to 7); +signal par_genA_1stlvla :std_ulogic_vector(0 to parBits-1); +signal par_genA_1stlvlb :std_ulogic_vector(0 to parBits-1); +signal par_genA_1stlvlc :std_ulogic_vector(0 to parBits-1); +signal par_genA_1stlvld :std_ulogic_vector(0 to parBits-1); +signal parity_genA_1b :std_ulogic_vector(0 to parBits-1); +signal parity_genA_2b :std_ulogic_vector(0 to parBits-1); +signal par_genB_1stlvla :std_ulogic_vector(0 to parBits-1); +signal par_genB_1stlvlb :std_ulogic_vector(0 to parBits-1); +signal par_genB_1stlvlc :std_ulogic_vector(0 to parBits-1); +signal par_genB_1stlvld :std_ulogic_vector(0 to parBits-1); +signal parity_genB_1b :std_ulogic_vector(0 to parBits-1); +signal parity_genB_2b :std_ulogic_vector(0 to parBits-1); +signal par_genC_1stlvla :std_ulogic_vector(0 to parBits-1); +signal par_genC_1stlvlb :std_ulogic_vector(0 to parBits-1); +signal par_genC_1stlvlc :std_ulogic_vector(0 to parBits-1); +signal par_genC_1stlvld :std_ulogic_vector(0 to parBits-1); +signal parity_genC_1b :std_ulogic_vector(0 to parBits-1); +signal parity_genC_2b :std_ulogic_vector(0 to parBits-1); +signal par_genD_1stlvla :std_ulogic_vector(0 to parBits-1); +signal par_genD_1stlvlb :std_ulogic_vector(0 to parBits-1); +signal par_genD_1stlvlc :std_ulogic_vector(0 to parBits-1); +signal par_genD_1stlvld :std_ulogic_vector(0 to parBits-1); +signal parity_genD_1b :std_ulogic_vector(0 to parBits-1); +signal parity_genD_2b :std_ulogic_vector(0 to parBits-1); +signal par_genE_1stlvla :std_ulogic_vector(0 to parBits-1); +signal par_genE_1stlvlb :std_ulogic_vector(0 to parBits-1); +signal par_genE_1stlvlc :std_ulogic_vector(0 to parBits-1); +signal par_genE_1stlvld :std_ulogic_vector(0 to parBits-1); +signal parity_genE_1b :std_ulogic_vector(0 to parBits-1); +signal parity_genE_2b :std_ulogic_vector(0 to parBits-1); +signal par_genF_1stlvla :std_ulogic_vector(0 to parBits-1); +signal par_genF_1stlvlb :std_ulogic_vector(0 to parBits-1); +signal par_genF_1stlvlc :std_ulogic_vector(0 to parBits-1); +signal par_genF_1stlvld :std_ulogic_vector(0 to parBits-1); +signal parity_genF_1b :std_ulogic_vector(0 to parBits-1); +signal parity_genF_2b :std_ulogic_vector(0 to parBits-1); +signal par_genG_1stlvla :std_ulogic_vector(0 to parBits-1); +signal par_genG_1stlvlb :std_ulogic_vector(0 to parBits-1); +signal par_genG_1stlvlc :std_ulogic_vector(0 to parBits-1); +signal par_genG_1stlvld :std_ulogic_vector(0 to parBits-1); +signal parity_genG_1b :std_ulogic_vector(0 to parBits-1); +signal parity_genG_2b :std_ulogic_vector(0 to parBits-1); +signal par_genH_1stlvla :std_ulogic_vector(0 to parBits-1); +signal par_genH_1stlvlb :std_ulogic_vector(0 to parBits-1); +signal par_genH_1stlvlc :std_ulogic_vector(0 to parBits-1); +signal par_genH_1stlvld :std_ulogic_vector(0 to parBits-1); +signal parity_genH_1b :std_ulogic_vector(0 to parBits-1); +signal parity_genH_2b :std_ulogic_vector(0 to parBits-1); + + +begin + +-- #################################################### +-- Inputs +-- #################################################### + +wr_wayA <= way_wen_a; +wr_wayB <= way_wen_b; +wr_wayC <= way_wen_c; +wr_wayD <= way_wen_d; +wr_wayE <= way_wen_e; +wr_wayF <= way_wen_f; +wr_wayG <= way_wen_g; +wr_wayH <= way_wen_h; +arr_rd_data <= dir_arr_rd_data; +wr_data <= wdata; + +-- #################################################### +-- Array Parity Generation +-- #################################################### + +extra_byte : for t in 0 to 7 generate begin + R0:if(t < (tagSize mod 8)) generate begin extra_byte_par(t) <= wr_data(uprTagBit+(8*(tagSize/8))+t); + end generate; + R1:if(t >= (tagSize mod 8)) generate begin extra_byte_par(t) <= '0'; + end generate; +end generate extra_byte; + +par_gen : for i in 0 to (tagSize/8)-1 generate begin + arr_parity(i) <= xor_reduce(wr_data(8*i+uprTagBit to 8*i+uprTagBit+7)); +end generate par_gen; + +par_gen_x : if (tagSize mod 8) /= 0 generate begin + arr_parity(tagSize/8) <= xor_reduce(extra_byte_par); +end generate par_gen_x; + +arr_wr_data <= wr_data & arr_parity; + +-- #################################################### +-- Array Input Selection +-- #################################################### +wr_way <= wr_wayA & wr_wayB & wr_wayC & wr_wayD & + wr_wayE & wr_wayF & wr_wayG & wr_wayH; + +-- #################################################### +-- Tag Array Read +-- #################################################### + +-- Inject Parity Error +rd_wayA(uprTagBit) <= arr_rd_data(0) xor inj_parity_err; +rd_wayA(uprTagBit+1 to lwrTagBit) <= arr_rd_data(1 to (0*wayDataSize)+tagSize-1); + +rd_wayB <= arr_rd_data((1*wayDataSize) to (1*wayDataSize)+tagSize-1); +rd_wayC <= arr_rd_data((2*wayDataSize) to (2*wayDataSize)+tagSize-1); +rd_wayD <= arr_rd_data((3*wayDataSize) to (3*wayDataSize)+tagSize-1); +rd_wayE <= arr_rd_data((4*wayDataSize) to (4*wayDataSize)+tagSize-1); +rd_wayF <= arr_rd_data((5*wayDataSize) to (5*wayDataSize)+tagSize-1); +rd_wayG <= arr_rd_data((6*wayDataSize) to (6*wayDataSize)+tagSize-1); +rd_wayH <= arr_rd_data((7*wayDataSize) to (7*wayDataSize)+tagSize-1); + +rd_parA <= arr_rd_data((0*wayDataSize)+tagSize to (0*wayDataSize)+tagSize+parBits-1); +rd_parB <= arr_rd_data((1*wayDataSize)+tagSize to (1*wayDataSize)+tagSize+parBits-1); +rd_parC <= arr_rd_data((2*wayDataSize)+tagSize to (2*wayDataSize)+tagSize+parBits-1); +rd_parD <= arr_rd_data((3*wayDataSize)+tagSize to (3*wayDataSize)+tagSize+parBits-1); +rd_parE <= arr_rd_data((4*wayDataSize)+tagSize to (4*wayDataSize)+tagSize+parBits-1); +rd_parF <= arr_rd_data((5*wayDataSize)+tagSize to (5*wayDataSize)+tagSize+parBits-1); +rd_parG <= arr_rd_data((6*wayDataSize)+tagSize to (6*wayDataSize)+tagSize+parBits-1); +rd_parH <= arr_rd_data((7*wayDataSize)+tagSize to (7*wayDataSize)+tagSize+parBits-1); + +-- #################################################### +-- Tag Parity Generation +-- #################################################### + +rdExtraByte : for t in 0 to 7 generate begin + R0: if(t < (tagSize mod 8)) generate + begin + extra_tagA_par(t) <= rd_wayA(uprTagBit+(8*(tagSize/8))+t); + extra_tagB_par(t) <= rd_wayB(uprTagBit+(8*(tagSize/8))+t); + extra_tagC_par(t) <= rd_wayC(uprTagBit+(8*(tagSize/8))+t); + extra_tagD_par(t) <= rd_wayD(uprTagBit+(8*(tagSize/8))+t); + extra_tagE_par(t) <= rd_wayE(uprTagBit+(8*(tagSize/8))+t); + extra_tagF_par(t) <= rd_wayF(uprTagBit+(8*(tagSize/8))+t); + extra_tagG_par(t) <= rd_wayG(uprTagBit+(8*(tagSize/8))+t); + extra_tagH_par(t) <= rd_wayH(uprTagBit+(8*(tagSize/8))+t); + end generate; + R1: if(t >= (tagSize mod 8)) generate + begin + extra_tagA_par(t) <= '0'; + extra_tagB_par(t) <= '0'; + extra_tagC_par(t) <= '0'; + extra_tagD_par(t) <= '0'; + extra_tagE_par(t) <= '0'; + extra_tagF_par(t) <= '0'; + extra_tagG_par(t) <= '0'; + extra_tagH_par(t) <= '0'; + end generate; +end generate rdExtraByte; + +rdParGen : for i in 0 to (tagSize/8)-1 generate +begin + + parA1lvla : par_genA_1stlvla(i) <= not (rd_wayA(8*i+uprTagBit+0) xor rd_wayA(8*i+uprTagBit+1)); + parA1lvlb : par_genA_1stlvlb(i) <= not (rd_wayA(8*i+uprTagBit+2) xor rd_wayA(8*i+uprTagBit+3)); + parA1lvlc : par_genA_1stlvlc(i) <= not (rd_wayA(8*i+uprTagBit+4) xor rd_wayA(8*i+uprTagBit+5)); + parA1lvld : par_genA_1stlvld(i) <= not (rd_wayA(8*i+uprTagBit+6) xor rd_wayA(8*i+uprTagBit+7)); + parGenA1b : parity_genA_1b(i) <= not (par_genA_1stlvla(i) xor par_genA_1stlvlb(i)); + parGenA2b : parity_genA_2b(i) <= not (par_genA_1stlvlc(i) xor par_genA_1stlvld(i)); + + parB1lvla : par_genB_1stlvla(i) <= not (rd_wayB(8*i+uprTagBit+0) xor rd_wayB(8*i+uprTagBit+1)); + parB1lvlb : par_genB_1stlvlb(i) <= not (rd_wayB(8*i+uprTagBit+2) xor rd_wayB(8*i+uprTagBit+3)); + parB1lvlc : par_genB_1stlvlc(i) <= not (rd_wayB(8*i+uprTagBit+4) xor rd_wayB(8*i+uprTagBit+5)); + parB1lvld : par_genB_1stlvld(i) <= not (rd_wayB(8*i+uprTagBit+6) xor rd_wayB(8*i+uprTagBit+7)); + parGenB1b : parity_genB_1b(i) <= not (par_genB_1stlvla(i) xor par_genB_1stlvlb(i)); + parGenB2b : parity_genB_2b(i) <= not (par_genB_1stlvlc(i) xor par_genB_1stlvld(i)); + + parC1lvla : par_genC_1stlvla(i) <= not (rd_wayC(8*i+uprTagBit+0) xor rd_wayC(8*i+uprTagBit+1)); + parC1lvlb : par_genC_1stlvlb(i) <= not (rd_wayC(8*i+uprTagBit+2) xor rd_wayC(8*i+uprTagBit+3)); + parC1lvlc : par_genC_1stlvlc(i) <= not (rd_wayC(8*i+uprTagBit+4) xor rd_wayC(8*i+uprTagBit+5)); + parC1lvld : par_genC_1stlvld(i) <= not (rd_wayC(8*i+uprTagBit+6) xor rd_wayC(8*i+uprTagBit+7)); + parGenC1b : parity_genC_1b(i) <= not (par_genC_1stlvla(i) xor par_genC_1stlvlb(i)); + parGenC2b : parity_genC_2b(i) <= not (par_genC_1stlvlc(i) xor par_genC_1stlvld(i)); + + parD1lvla : par_genD_1stlvla(i) <= not (rd_wayD(8*i+uprTagBit+0) xor rd_wayD(8*i+uprTagBit+1)); + parD1lvlb : par_genD_1stlvlb(i) <= not (rd_wayD(8*i+uprTagBit+2) xor rd_wayD(8*i+uprTagBit+3)); + parD1lvlc : par_genD_1stlvlc(i) <= not (rd_wayD(8*i+uprTagBit+4) xor rd_wayD(8*i+uprTagBit+5)); + parD1lvld : par_genD_1stlvld(i) <= not (rd_wayD(8*i+uprTagBit+6) xor rd_wayD(8*i+uprTagBit+7)); + parGenD1b : parity_genD_1b(i) <= not (par_genD_1stlvla(i) xor par_genD_1stlvlb(i)); + parGenD2b : parity_genD_2b(i) <= not (par_genD_1stlvlc(i) xor par_genD_1stlvld(i)); + + parE1lvla : par_genE_1stlvla(i) <= not (rd_wayE(8*i+uprTagBit+0) xor rd_wayE(8*i+uprTagBit+1)); + parE1lvlb : par_genE_1stlvlb(i) <= not (rd_wayE(8*i+uprTagBit+2) xor rd_wayE(8*i+uprTagBit+3)); + parE1lvlc : par_genE_1stlvlc(i) <= not (rd_wayE(8*i+uprTagBit+4) xor rd_wayE(8*i+uprTagBit+5)); + parE1lvld : par_genE_1stlvld(i) <= not (rd_wayE(8*i+uprTagBit+6) xor rd_wayE(8*i+uprTagBit+7)); + parGenE1b : parity_genE_1b(i) <= not (par_genE_1stlvla(i) xor par_genE_1stlvlb(i)); + parGenE2b : parity_genE_2b(i) <= not (par_genE_1stlvlc(i) xor par_genE_1stlvld(i)); + + parF1lvla : par_genF_1stlvla(i) <= not (rd_wayF(8*i+uprTagBit+0) xor rd_wayF(8*i+uprTagBit+1)); + parF1lvlb : par_genF_1stlvlb(i) <= not (rd_wayF(8*i+uprTagBit+2) xor rd_wayF(8*i+uprTagBit+3)); + parF1lvlc : par_genF_1stlvlc(i) <= not (rd_wayF(8*i+uprTagBit+4) xor rd_wayF(8*i+uprTagBit+5)); + parF1lvld : par_genF_1stlvld(i) <= not (rd_wayF(8*i+uprTagBit+6) xor rd_wayF(8*i+uprTagBit+7)); + parGenF1b : parity_genF_1b(i) <= not (par_genF_1stlvla(i) xor par_genF_1stlvlb(i)); + parGenF2b : parity_genF_2b(i) <= not (par_genF_1stlvlc(i) xor par_genF_1stlvld(i)); + + parG1lvla : par_genG_1stlvla(i) <= not (rd_wayG(8*i+uprTagBit+0) xor rd_wayG(8*i+uprTagBit+1)); + parG1lvlb : par_genG_1stlvlb(i) <= not (rd_wayG(8*i+uprTagBit+2) xor rd_wayG(8*i+uprTagBit+3)); + parG1lvlc : par_genG_1stlvlc(i) <= not (rd_wayG(8*i+uprTagBit+4) xor rd_wayG(8*i+uprTagBit+5)); + parG1lvld : par_genG_1stlvld(i) <= not (rd_wayG(8*i+uprTagBit+6) xor rd_wayG(8*i+uprTagBit+7)); + parGenG1b : parity_genG_1b(i) <= not (par_genG_1stlvla(i) xor par_genG_1stlvlb(i)); + parGenG2b : parity_genG_2b(i) <= not (par_genG_1stlvlc(i) xor par_genG_1stlvld(i)); + + parH1lvla : par_genH_1stlvla(i) <= not (rd_wayH(8*i+uprTagBit+0) xor rd_wayH(8*i+uprTagBit+1)); + parH1lvlb : par_genH_1stlvlb(i) <= not (rd_wayH(8*i+uprTagBit+2) xor rd_wayH(8*i+uprTagBit+3)); + parH1lvlc : par_genH_1stlvlc(i) <= not (rd_wayH(8*i+uprTagBit+4) xor rd_wayH(8*i+uprTagBit+5)); + parH1lvld : par_genH_1stlvld(i) <= not (rd_wayH(8*i+uprTagBit+6) xor rd_wayH(8*i+uprTagBit+7)); + parGenH1b : parity_genH_1b(i) <= not (par_genH_1stlvla(i) xor par_genH_1stlvlb(i)); + parGenH2b : parity_genH_2b(i) <= not (par_genH_1stlvlc(i) xor par_genH_1stlvld(i)); +end generate rdParGen; + +rdParGenx : if (tagSize mod 8) /= 0 generate +begin + EparA1lvla : par_genA_1stlvla(parBits-1) <= not (extra_tagA_par(0) xor extra_tagA_par(1)); + EparA1lvlb : par_genA_1stlvlb(parBits-1) <= not (extra_tagA_par(2) xor extra_tagA_par(3)); + EparA1lvlc : par_genA_1stlvlc(parBits-1) <= not (extra_tagA_par(4) xor extra_tagA_par(5)); + EparA1lvld : par_genA_1stlvld(parBits-1) <= not (extra_tagA_par(6) xor extra_tagA_par(7)); + EparGenA1b : parity_genA_1b(parBits-1) <= not (par_genA_1stlvla(parBits-1) xor par_genA_1stlvlb(parBits-1)); + EparGenA2b : parity_genA_2b(parBits-1) <= not (par_genA_1stlvlc(parBits-1) xor par_genA_1stlvld(parBits-1)); + + EparB1lvla : par_genB_1stlvla(parBits-1) <= not (extra_tagB_par(0) xor extra_tagB_par(1)); + EparB1lvlb : par_genB_1stlvlb(parBits-1) <= not (extra_tagB_par(2) xor extra_tagB_par(3)); + EparB1lvlc : par_genB_1stlvlc(parBits-1) <= not (extra_tagB_par(4) xor extra_tagB_par(5)); + EparB1lvld : par_genB_1stlvld(parBits-1) <= not (extra_tagB_par(6) xor extra_tagB_par(7)); + EparGenB1b : parity_genB_1b(parBits-1) <= not (par_genB_1stlvla(parBits-1) xor par_genB_1stlvlb(parBits-1)); + EparGenB2b : parity_genB_2b(parBits-1) <= not (par_genB_1stlvlc(parBits-1) xor par_genB_1stlvld(parBits-1)); + + EparC1lvla : par_genC_1stlvla(parBits-1) <= not (extra_tagC_par(0) xor extra_tagC_par(1)); + EparC1lvlb : par_genC_1stlvlb(parBits-1) <= not (extra_tagC_par(2) xor extra_tagC_par(3)); + EparC1lvlc : par_genC_1stlvlc(parBits-1) <= not (extra_tagC_par(4) xor extra_tagC_par(5)); + EparC1lvld : par_genC_1stlvld(parBits-1) <= not (extra_tagC_par(6) xor extra_tagC_par(7)); + EparGenC1b : parity_genC_1b(parBits-1) <= not (par_genC_1stlvla(parBits-1) xor par_genC_1stlvlb(parBits-1)); + EparGenC2b : parity_genC_2b(parBits-1) <= not (par_genC_1stlvlc(parBits-1) xor par_genC_1stlvld(parBits-1)); + + EparD1lvla : par_genD_1stlvla(parBits-1) <= not (extra_tagD_par(0) xor extra_tagD_par(1)); + EparD1lvlb : par_genD_1stlvlb(parBits-1) <= not (extra_tagD_par(2) xor extra_tagD_par(3)); + EparD1lvlc : par_genD_1stlvlc(parBits-1) <= not (extra_tagD_par(4) xor extra_tagD_par(5)); + EparD1lvld : par_genD_1stlvld(parBits-1) <= not (extra_tagD_par(6) xor extra_tagD_par(7)); + EparGenD1b : parity_genD_1b(parBits-1) <= not (par_genD_1stlvla(parBits-1) xor par_genD_1stlvlb(parBits-1)); + EparGenD2b : parity_genD_2b(parBits-1) <= not (par_genD_1stlvlc(parBits-1) xor par_genD_1stlvld(parBits-1)); + + EparE1lvla : par_genE_1stlvla(parBits-1) <= not (extra_tagE_par(0) xor extra_tagE_par(1)); + EparE1lvlb : par_genE_1stlvlb(parBits-1) <= not (extra_tagE_par(2) xor extra_tagE_par(3)); + EparE1lvlc : par_genE_1stlvlc(parBits-1) <= not (extra_tagE_par(4) xor extra_tagE_par(5)); + EparE1lvld : par_genE_1stlvld(parBits-1) <= not (extra_tagE_par(6) xor extra_tagE_par(7)); + EparGenE1b : parity_genE_1b(parBits-1) <= not (par_genE_1stlvla(parBits-1) xor par_genE_1stlvlb(parBits-1)); + EparGenE2b : parity_genE_2b(parBits-1) <= not (par_genE_1stlvlc(parBits-1) xor par_genE_1stlvld(parBits-1)); + + EparF1lvla : par_genF_1stlvla(parBits-1) <= not (extra_tagF_par(0) xor extra_tagF_par(1)); + EparF1lvlb : par_genF_1stlvlb(parBits-1) <= not (extra_tagF_par(2) xor extra_tagF_par(3)); + EparF1lvlc : par_genF_1stlvlc(parBits-1) <= not (extra_tagF_par(4) xor extra_tagF_par(5)); + EparF1lvld : par_genF_1stlvld(parBits-1) <= not (extra_tagF_par(6) xor extra_tagF_par(7)); + EparGenF1b : parity_genF_1b(parBits-1) <= not (par_genF_1stlvla(parBits-1) xor par_genF_1stlvlb(parBits-1)); + EparGenF2b : parity_genF_2b(parBits-1) <= not (par_genF_1stlvlc(parBits-1) xor par_genF_1stlvld(parBits-1)); + + EparG1lvla : par_genG_1stlvla(parBits-1) <= not (extra_tagG_par(0) xor extra_tagG_par(1)); + EparG1lvlb : par_genG_1stlvlb(parBits-1) <= not (extra_tagG_par(2) xor extra_tagG_par(3)); + EparG1lvlc : par_genG_1stlvlc(parBits-1) <= not (extra_tagG_par(4) xor extra_tagG_par(5)); + EparG1lvld : par_genG_1stlvld(parBits-1) <= not (extra_tagG_par(6) xor extra_tagG_par(7)); + EparGenG1b : parity_genG_1b(parBits-1) <= not (par_genG_1stlvla(parBits-1) xor par_genG_1stlvlb(parBits-1)); + EparGenG2b : parity_genG_2b(parBits-1) <= not (par_genG_1stlvlc(parBits-1) xor par_genG_1stlvld(parBits-1)); + + EparH1lvla : par_genH_1stlvla(parBits-1) <= not (extra_tagH_par(0) xor extra_tagH_par(1)); + EparH1lvlb : par_genH_1stlvlb(parBits-1) <= not (extra_tagH_par(2) xor extra_tagH_par(3)); + EparH1lvlc : par_genH_1stlvlc(parBits-1) <= not (extra_tagH_par(4) xor extra_tagH_par(5)); + EparH1lvld : par_genH_1stlvld(parBits-1) <= not (extra_tagH_par(6) xor extra_tagH_par(7)); + EparGenH1b : parity_genH_1b(parBits-1) <= not (par_genH_1stlvla(parBits-1) xor par_genH_1stlvlb(parBits-1)); + EparGenH2b : parity_genH_2b(parBits-1) <= not (par_genH_1stlvlc(parBits-1) xor par_genH_1stlvld(parBits-1)); +end generate rdParGenx; + +-- #################################################### +-- Parity Error Check +-- #################################################### + +par_gen_a_1b <= parity_genA_1b; +par_gen_b_1b <= parity_genB_1b; +par_gen_c_1b <= parity_genC_1b; +par_gen_d_1b <= parity_genD_1b; +par_gen_e_1b <= parity_genE_1b; +par_gen_f_1b <= parity_genF_1b; +par_gen_g_1b <= parity_genG_1b; +par_gen_h_1b <= parity_genH_1b; +par_gen_a_2b <= parity_genA_2b; +par_gen_b_2b <= parity_genB_2b; +par_gen_c_2b <= parity_genC_2b; +par_gen_d_2b <= parity_genD_2b; +par_gen_e_2b <= parity_genE_2b; +par_gen_f_2b <= parity_genF_2b; +par_gen_g_2b <= parity_genG_2b; +par_gen_h_2b <= parity_genH_2b; + +-- #################################################### +-- Outputs +-- #################################################### + +-- Directory Array Control and Data +dir_wr_way <= wr_way; +dir_arr_rd_addr_01 <= raddr_01; +dir_arr_rd_addr_23 <= raddr_23; +dir_arr_rd_addr_45 <= raddr_45; +dir_arr_rd_addr_67 <= raddr_67; +dir_arr_wr_addr <= waddr; +dir_arr_wr_data <= arr_wr_data; + +way_tag_a <= rd_wayA; +way_tag_b <= rd_wayB; +way_tag_c <= rd_wayC; +way_tag_d <= rd_wayD; +way_tag_e <= rd_wayE; +way_tag_f <= rd_wayF; +way_tag_g <= rd_wayG; +way_tag_h <= rd_wayH; + +way_arr_par_a <= rd_parA; +way_arr_par_b <= rd_parB; +way_arr_par_c <= rd_parC; +way_arr_par_d <= rd_parD; +way_arr_par_e <= rd_parE; +way_arr_par_f <= rd_parF; +way_arr_par_g <= rd_parG; +way_arr_par_h <= rd_parH; + +end xuq_lsu_dir_tag_arr; diff --git a/rel/src/vhdl/work/xuq_lsu_dir_val16.vhdl b/rel/src/vhdl/work/xuq_lsu_dir_val16.vhdl new file mode 100644 index 0000000..a3b3456 --- /dev/null +++ b/rel/src/vhdl/work/xuq_lsu_dir_val16.vhdl @@ -0,0 +1,27524 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XU LSU L1 Data Directory Valid Register Array + +library ibm, ieee, work, tri, support; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use tri.tri_latches_pkg.all; +use support.power_logic_pkg.all; +-- ########################################################################################## +-- Directory Valids Component +-- 1) Contains an Array of Valids +-- 2) Updates Valid bits on Reloads +-- 3) Invalidates Valid bits for Flush type commands and Back Invalidates +-- 4) Outputs Valids for Congruence Class +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Flush Way Generation +-- Want to flush a Way on the following conditions +-- 1) Invalidate Type Instruction (dcbf,dcbi,dcbz,lwarx,stwcx) +-- 2) L2 Back Invalidate +-- 3) L2 Reload and overwritting a Valid Way +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- ########################################################################################## +entity xuq_lsu_dir_val16 is +generic(expand_type : integer := 2; + dc_size : natural := 14; + cl_size : natural := 6); +port( + + ex1_stg_act :in std_ulogic; + ex2_stg_act :in std_ulogic; + ex3_stg_act :in std_ulogic; + ex4_stg_act :in std_ulogic; + ex5_stg_act :in std_ulogic; + binv1_stg_act :in std_ulogic; + binv2_stg_act :in std_ulogic; + binv3_stg_act :in std_ulogic; + binv4_stg_act :in std_ulogic; + binv5_stg_act :in std_ulogic; + rel1_stg_act :in std_ulogic; + rel2_stg_act :in std_ulogic; + + ldq_rel1_early_v :in std_ulogic; + rel1_val :in std_ulogic; + rel_addr_early :in std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + rel_lock_en :in std_ulogic; + rel_l1dump_cslc :in std_ulogic; + rel3_l1dump_val :in std_ulogic; + rel4_ecc_err :in std_ulogic; + rel_watch_en :in std_ulogic; + rel_thrd_id :in std_ulogic_vector(0 to 3); + rel_way_clr_a :in std_ulogic; + rel_way_clr_b :in std_ulogic; + rel_way_clr_c :in std_ulogic; + rel_way_clr_d :in std_ulogic; + rel_way_clr_e :in std_ulogic; + rel_way_clr_f :in std_ulogic; + rel_way_clr_g :in std_ulogic; + rel_way_clr_h :in std_ulogic; + + ldq_rel3_early_v :in std_ulogic; + rel3_val :in std_ulogic; + rel_back_inval :in std_ulogic; + rel4_set_val :in std_ulogic; + rel4_recirc_val :in std_ulogic; + rel_way_wen_a :in std_ulogic; + rel_way_wen_b :in std_ulogic; + rel_way_wen_c :in std_ulogic; + rel_way_wen_d :in std_ulogic; + rel_way_wen_e :in std_ulogic; + rel_way_wen_f :in std_ulogic; + rel_way_wen_g :in std_ulogic; + rel_way_wen_h :in std_ulogic; + rel_up_way_addr_b :in std_ulogic_vector(0 to 2); + rel_dcarr_addr_en :in std_ulogic; + + xu_lsu_dci :in std_ulogic; + xu_lsu_spr_xucr0_clfc :in std_ulogic; + spr_xucr0_dcdis :in std_ulogic; + spr_xucr0_cls :in std_ulogic; + + ex1_thrd_id :in std_ulogic_vector(0 to 3); + ex1_p_addr :in std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + ex2_is_inval_op :in std_ulogic; + ex2_lock_set :in std_ulogic; + ex2_lock_clr :in std_ulogic; + ex3_cache_acc :in std_ulogic; + ex3_cache_en :in std_ulogic; + ex3_tag_way_perr :in std_ulogic_vector(0 to 7); + ex5_load_op_hit :in std_ulogic; + ex6_ld_par_err :in std_ulogic; + ex2_ldawx_instr :in std_ulogic; + ex2_wclr_instr :in std_ulogic; + ex2_wchk_val :in std_ulogic; + ex2_l_fld :in std_ulogic_vector(0 to 1); + ex2_store_instr :in std_ulogic; + ex3_load_val :in std_ulogic; + ex3_wimge_i_bit :in std_ulogic; + ex3_l2_request :in std_ulogic; + ex3_ldq_potential_flush :in std_ulogic; + + inv1_val :in std_ulogic; + + ex3_way_cmp_a :in std_ulogic; + ex3_way_cmp_b :in std_ulogic; + ex3_way_cmp_c :in std_ulogic; + ex3_way_cmp_d :in std_ulogic; + ex3_way_cmp_e :in std_ulogic; + ex3_way_cmp_f :in std_ulogic; + ex3_way_cmp_g :in std_ulogic; + ex3_way_cmp_h :in std_ulogic; + + ex2_stg_flush :in std_ulogic; + ex3_stg_flush :in std_ulogic; + ex4_stg_flush :in std_ulogic; + ex5_stg_flush :in std_ulogic; + + pc_xu_inj_dcachedir_multihit :in std_ulogic; + + ex4_way_a_dir :out std_ulogic_vector(0 to 5); + ex4_way_b_dir :out std_ulogic_vector(0 to 5); + ex4_way_c_dir :out std_ulogic_vector(0 to 5); + ex4_way_d_dir :out std_ulogic_vector(0 to 5); + ex4_way_e_dir :out std_ulogic_vector(0 to 5); + ex4_way_f_dir :out std_ulogic_vector(0 to 5); + ex4_way_g_dir :out std_ulogic_vector(0 to 5); + ex4_way_h_dir :out std_ulogic_vector(0 to 5); + + ex4_way_a_hit :out std_ulogic; + ex4_way_b_hit :out std_ulogic; + ex4_way_c_hit :out std_ulogic; + ex4_way_d_hit :out std_ulogic; + ex4_way_e_hit :out std_ulogic; + ex4_way_f_hit :out std_ulogic; + ex4_way_g_hit :out std_ulogic; + ex4_way_h_hit :out std_ulogic; + + ex3_cClass_upd_way_a :out std_ulogic; + ex3_cClass_upd_way_b :out std_ulogic; + ex3_cClass_upd_way_c :out std_ulogic; + ex3_cClass_upd_way_d :out std_ulogic; + ex3_cClass_upd_way_e :out std_ulogic; + ex3_cClass_upd_way_f :out std_ulogic; + ex3_cClass_upd_way_g :out std_ulogic; + ex3_cClass_upd_way_h :out std_ulogic; + + ex2_lockwatchSet_rel_coll :out std_ulogic; + ex3_wclr_all_flush :out std_ulogic; + + ex3_hit :out std_ulogic; + ex3_dir_perr_det :out std_ulogic; + ex4_dir_multihit_det :out std_ulogic; + ex4_n_lsu_ddmh_flush :out std_ulogic_vector(0 to 3); + ex4_ldq_full_flush :out std_ulogic; + ex4_miss :out std_ulogic; + ex4_snd_ld_l2 :out std_ulogic; + dcpar_err_flush :out std_ulogic; + pe_recov_begin :out std_ulogic; + + lsu_xu_ex5_cr_rslt :out std_ulogic; + + rel_way_val_a :out std_ulogic; + rel_way_val_b :out std_ulogic; + rel_way_val_c :out std_ulogic; + rel_way_val_d :out std_ulogic; + rel_way_val_e :out std_ulogic; + rel_way_val_f :out std_ulogic; + rel_way_val_g :out std_ulogic; + rel_way_val_h :out std_ulogic; + + rel_way_lock_a :out std_ulogic; + rel_way_lock_b :out std_ulogic; + rel_way_lock_c :out std_ulogic; + rel_way_lock_d :out std_ulogic; + rel_way_lock_e :out std_ulogic; + rel_way_lock_f :out std_ulogic; + rel_way_lock_g :out std_ulogic; + rel_way_lock_h :out std_ulogic; + + dcarr_up_way_addr :out std_ulogic_vector(0 to 2); + + lsu_xu_perf_events :out std_ulogic_vector(0 to 16); + + lsu_xu_spr_xucr0_cslc_xuop :out std_ulogic; + lsu_xu_spr_xucr0_cslc_binv :out std_ulogic; + + dc_val_dbg_data :out std_ulogic_vector(0 to 293); + + vdd :inout power_logic; + gnd :inout power_logic; + nclk :in clk_logic; + sg_0 :in std_ulogic; + func_sl_thold_0_b :in std_ulogic; + func_sl_force :in std_ulogic; + func_slp_sl_thold_0_b :in std_ulogic; + func_slp_sl_force :in std_ulogic; + func_nsl_thold_0_b :in std_ulogic; + func_nsl_force :in std_ulogic; + func_slp_nsl_thold_0_b :in std_ulogic; + func_slp_nsl_force :in std_ulogic; + d_mode_dc :in std_ulogic; + delay_lclkr_dc :in std_ulogic; + mpw1_dc_b :in std_ulogic; + mpw2_dc_b :in std_ulogic; + scan_in :in std_ulogic_vector(0 to 2); + scan_out :out std_ulogic_vector(0 to 2) + ); +-- synopsys translate_off +-- synopsys translate_on +end xuq_lsu_dir_val16; +---- +ARCHITECTURE XUQ_LSU_DIR_VAL16 + OF XUQ_LSU_DIR_VAL16 + IS +---------------------------- +-- components +---------------------------- +---------------------------- +-- constants +---------------------------- +constant congr_cl0_wA_offset :natural := 0; +constant congr_cl0_wB_offset :natural := congr_cl0_wA_offset + 6; +constant congr_cl0_wC_offset :natural := congr_cl0_wB_offset + 6; +constant congr_cl0_wD_offset :natural := congr_cl0_wC_offset + 6; +constant congr_cl0_wE_offset :natural := congr_cl0_wD_offset + 6; +constant congr_cl0_wF_offset :natural := congr_cl0_wE_offset + 6; +constant congr_cl0_wG_offset :natural := congr_cl0_wF_offset + 6; +constant congr_cl0_wH_offset :natural := congr_cl0_wG_offset + 6; +constant congr_cl1_wA_offset :natural := congr_cl0_wH_offset + 6; +constant congr_cl1_wB_offset :natural := congr_cl1_wA_offset + 6; +constant congr_cl1_wC_offset :natural := congr_cl1_wB_offset + 6; +constant congr_cl1_wD_offset :natural := congr_cl1_wC_offset + 6; +constant congr_cl1_wE_offset :natural := congr_cl1_wD_offset + 6; +constant congr_cl1_wF_offset :natural := congr_cl1_wE_offset + 6; +constant congr_cl1_wG_offset :natural := congr_cl1_wF_offset + 6; +constant congr_cl1_wH_offset :natural := congr_cl1_wG_offset + 6; +constant congr_cl2_wA_offset :natural := congr_cl1_wH_offset + 6; +constant congr_cl2_wB_offset :natural := congr_cl2_wA_offset + 6; +constant congr_cl2_wC_offset :natural := congr_cl2_wB_offset + 6; +constant congr_cl2_wD_offset :natural := congr_cl2_wC_offset + 6; +constant congr_cl2_wE_offset :natural := congr_cl2_wD_offset + 6; +constant congr_cl2_wF_offset :natural := congr_cl2_wE_offset + 6; +constant congr_cl2_wG_offset :natural := congr_cl2_wF_offset + 6; +constant congr_cl2_wH_offset :natural := congr_cl2_wG_offset + 6; +constant congr_cl3_wA_offset :natural := congr_cl2_wH_offset + 6; +constant congr_cl3_wB_offset :natural := congr_cl3_wA_offset + 6; +constant congr_cl3_wC_offset :natural := congr_cl3_wB_offset + 6; +constant congr_cl3_wD_offset :natural := congr_cl3_wC_offset + 6; +constant congr_cl3_wE_offset :natural := congr_cl3_wD_offset + 6; +constant congr_cl3_wF_offset :natural := congr_cl3_wE_offset + 6; +constant congr_cl3_wG_offset :natural := congr_cl3_wF_offset + 6; +constant congr_cl3_wH_offset :natural := congr_cl3_wG_offset + 6; +constant congr_cl4_wA_offset :natural := congr_cl3_wH_offset + 6; +constant congr_cl4_wB_offset :natural := congr_cl4_wA_offset + 6; +constant congr_cl4_wC_offset :natural := congr_cl4_wB_offset + 6; +constant congr_cl4_wD_offset :natural := congr_cl4_wC_offset + 6; +constant congr_cl4_wE_offset :natural := congr_cl4_wD_offset + 6; +constant congr_cl4_wF_offset :natural := congr_cl4_wE_offset + 6; +constant congr_cl4_wG_offset :natural := congr_cl4_wF_offset + 6; +constant congr_cl4_wH_offset :natural := congr_cl4_wG_offset + 6; +constant congr_cl5_wA_offset :natural := congr_cl4_wH_offset + 6; +constant congr_cl5_wB_offset :natural := congr_cl5_wA_offset + 6; +constant congr_cl5_wC_offset :natural := congr_cl5_wB_offset + 6; +constant congr_cl5_wD_offset :natural := congr_cl5_wC_offset + 6; +constant congr_cl5_wE_offset :natural := congr_cl5_wD_offset + 6; +constant congr_cl5_wF_offset :natural := congr_cl5_wE_offset + 6; +constant congr_cl5_wG_offset :natural := congr_cl5_wF_offset + 6; +constant congr_cl5_wH_offset :natural := congr_cl5_wG_offset + 6; +constant congr_cl6_wA_offset :natural := congr_cl5_wH_offset + 6; +constant congr_cl6_wB_offset :natural := congr_cl6_wA_offset + 6; +constant congr_cl6_wC_offset :natural := congr_cl6_wB_offset + 6; +constant congr_cl6_wD_offset :natural := congr_cl6_wC_offset + 6; +constant congr_cl6_wE_offset :natural := congr_cl6_wD_offset + 6; +constant congr_cl6_wF_offset :natural := congr_cl6_wE_offset + 6; +constant congr_cl6_wG_offset :natural := congr_cl6_wF_offset + 6; +constant congr_cl6_wH_offset :natural := congr_cl6_wG_offset + 6; +constant congr_cl7_wA_offset :natural := congr_cl6_wH_offset + 6; +constant congr_cl7_wB_offset :natural := congr_cl7_wA_offset + 6; +constant congr_cl7_wC_offset :natural := congr_cl7_wB_offset + 6; +constant congr_cl7_wD_offset :natural := congr_cl7_wC_offset + 6; +constant congr_cl7_wE_offset :natural := congr_cl7_wD_offset + 6; +constant congr_cl7_wF_offset :natural := congr_cl7_wE_offset + 6; +constant congr_cl7_wG_offset :natural := congr_cl7_wF_offset + 6; +constant congr_cl7_wH_offset :natural := congr_cl7_wG_offset + 6; +constant congr_cl8_wA_offset :natural := congr_cl7_wH_offset + 6; +constant congr_cl8_wB_offset :natural := congr_cl8_wA_offset + 6; +constant congr_cl8_wC_offset :natural := congr_cl8_wB_offset + 6; +constant congr_cl8_wD_offset :natural := congr_cl8_wC_offset + 6; +constant congr_cl8_wE_offset :natural := congr_cl8_wD_offset + 6; +constant congr_cl8_wF_offset :natural := congr_cl8_wE_offset + 6; +constant congr_cl8_wG_offset :natural := congr_cl8_wF_offset + 6; +constant congr_cl8_wH_offset :natural := congr_cl8_wG_offset + 6; +constant congr_cl9_wA_offset :natural := congr_cl8_wH_offset + 6; +constant congr_cl9_wB_offset :natural := congr_cl9_wA_offset + 6; +constant congr_cl9_wC_offset :natural := congr_cl9_wB_offset + 6; +constant congr_cl9_wD_offset :natural := congr_cl9_wC_offset + 6; +constant congr_cl9_wE_offset :natural := congr_cl9_wD_offset + 6; +constant congr_cl9_wF_offset :natural := congr_cl9_wE_offset + 6; +constant congr_cl9_wG_offset :natural := congr_cl9_wF_offset + 6; +constant congr_cl9_wH_offset :natural := congr_cl9_wG_offset + 6; +constant congr_cl10_wA_offset :natural := congr_cl9_wH_offset + 6; +constant congr_cl10_wB_offset :natural := congr_cl10_wA_offset + 6; +constant congr_cl10_wC_offset :natural := congr_cl10_wB_offset + 6; +constant congr_cl10_wD_offset :natural := congr_cl10_wC_offset + 6; +constant congr_cl10_wE_offset :natural := congr_cl10_wD_offset + 6; +constant congr_cl10_wF_offset :natural := congr_cl10_wE_offset + 6; +constant congr_cl10_wG_offset :natural := congr_cl10_wF_offset + 6; +constant congr_cl10_wH_offset :natural := congr_cl10_wG_offset + 6; +constant congr_cl11_wA_offset :natural := congr_cl10_wH_offset + 6; +constant congr_cl11_wB_offset :natural := congr_cl11_wA_offset + 6; +constant congr_cl11_wC_offset :natural := congr_cl11_wB_offset + 6; +constant congr_cl11_wD_offset :natural := congr_cl11_wC_offset + 6; +constant congr_cl11_wE_offset :natural := congr_cl11_wD_offset + 6; +constant congr_cl11_wF_offset :natural := congr_cl11_wE_offset + 6; +constant congr_cl11_wG_offset :natural := congr_cl11_wF_offset + 6; +constant congr_cl11_wH_offset :natural := congr_cl11_wG_offset + 6; +constant congr_cl12_wA_offset :natural := congr_cl11_wH_offset + 6; +constant congr_cl12_wB_offset :natural := congr_cl12_wA_offset + 6; +constant congr_cl12_wC_offset :natural := congr_cl12_wB_offset + 6; +constant congr_cl12_wD_offset :natural := congr_cl12_wC_offset + 6; +constant congr_cl12_wE_offset :natural := congr_cl12_wD_offset + 6; +constant congr_cl12_wF_offset :natural := congr_cl12_wE_offset + 6; +constant congr_cl12_wG_offset :natural := congr_cl12_wF_offset + 6; +constant congr_cl12_wH_offset :natural := congr_cl12_wG_offset + 6; +constant congr_cl13_wA_offset :natural := congr_cl12_wH_offset + 6; +constant congr_cl13_wB_offset :natural := congr_cl13_wA_offset + 6; +constant congr_cl13_wC_offset :natural := congr_cl13_wB_offset + 6; +constant congr_cl13_wD_offset :natural := congr_cl13_wC_offset + 6; +constant congr_cl13_wE_offset :natural := congr_cl13_wD_offset + 6; +constant congr_cl13_wF_offset :natural := congr_cl13_wE_offset + 6; +constant congr_cl13_wG_offset :natural := congr_cl13_wF_offset + 6; +constant congr_cl13_wH_offset :natural := congr_cl13_wG_offset + 6; +constant congr_cl14_wA_offset :natural := congr_cl13_wH_offset + 6; +constant congr_cl14_wB_offset :natural := congr_cl14_wA_offset + 6; +constant congr_cl14_wC_offset :natural := congr_cl14_wB_offset + 6; +constant congr_cl14_wD_offset :natural := congr_cl14_wC_offset + 6; +constant congr_cl14_wE_offset :natural := congr_cl14_wD_offset + 6; +constant congr_cl14_wF_offset :natural := congr_cl14_wE_offset + 6; +constant congr_cl14_wG_offset :natural := congr_cl14_wF_offset + 6; +constant congr_cl14_wH_offset :natural := congr_cl14_wG_offset + 6; +constant congr_cl15_wA_offset :natural := congr_cl14_wH_offset + 6; +constant congr_cl15_wB_offset :natural := congr_cl15_wA_offset + 6; +constant congr_cl15_wC_offset :natural := congr_cl15_wB_offset + 6; +constant congr_cl15_wD_offset :natural := congr_cl15_wC_offset + 6; +constant congr_cl15_wE_offset :natural := congr_cl15_wD_offset + 6; +constant congr_cl15_wF_offset :natural := congr_cl15_wE_offset + 6; +constant congr_cl15_wG_offset :natural := congr_cl15_wF_offset + 6; +constant congr_cl15_wH_offset :natural := congr_cl15_wG_offset + 6; +constant congr_cl16_wA_offset :natural := congr_cl15_wH_offset + 6; +constant congr_cl16_wB_offset :natural := congr_cl16_wA_offset + 6; +constant congr_cl16_wC_offset :natural := congr_cl16_wB_offset + 6; +constant congr_cl16_wD_offset :natural := congr_cl16_wC_offset + 6; +constant congr_cl16_wE_offset :natural := congr_cl16_wD_offset + 6; +constant congr_cl16_wF_offset :natural := congr_cl16_wE_offset + 6; +constant congr_cl16_wG_offset :natural := congr_cl16_wF_offset + 6; +constant congr_cl16_wH_offset :natural := congr_cl16_wG_offset + 6; +constant congr_cl17_wA_offset :natural := congr_cl16_wH_offset + 6; +constant congr_cl17_wB_offset :natural := congr_cl17_wA_offset + 6; +constant congr_cl17_wC_offset :natural := congr_cl17_wB_offset + 6; +constant congr_cl17_wD_offset :natural := congr_cl17_wC_offset + 6; +constant congr_cl17_wE_offset :natural := congr_cl17_wD_offset + 6; +constant congr_cl17_wF_offset :natural := congr_cl17_wE_offset + 6; +constant congr_cl17_wG_offset :natural := congr_cl17_wF_offset + 6; +constant congr_cl17_wH_offset :natural := congr_cl17_wG_offset + 6; +constant congr_cl18_wA_offset :natural := congr_cl17_wH_offset + 6; +constant congr_cl18_wB_offset :natural := congr_cl18_wA_offset + 6; +constant congr_cl18_wC_offset :natural := congr_cl18_wB_offset + 6; +constant congr_cl18_wD_offset :natural := congr_cl18_wC_offset + 6; +constant congr_cl18_wE_offset :natural := congr_cl18_wD_offset + 6; +constant congr_cl18_wF_offset :natural := congr_cl18_wE_offset + 6; +constant congr_cl18_wG_offset :natural := congr_cl18_wF_offset + 6; +constant congr_cl18_wH_offset :natural := congr_cl18_wG_offset + 6; +constant congr_cl19_wA_offset :natural := congr_cl18_wH_offset + 6; +constant congr_cl19_wB_offset :natural := congr_cl19_wA_offset + 6; +constant congr_cl19_wC_offset :natural := congr_cl19_wB_offset + 6; +constant congr_cl19_wD_offset :natural := congr_cl19_wC_offset + 6; +constant congr_cl19_wE_offset :natural := congr_cl19_wD_offset + 6; +constant congr_cl19_wF_offset :natural := congr_cl19_wE_offset + 6; +constant congr_cl19_wG_offset :natural := congr_cl19_wF_offset + 6; +constant congr_cl19_wH_offset :natural := congr_cl19_wG_offset + 6; +constant congr_cl20_wA_offset :natural := congr_cl19_wH_offset + 6; +constant congr_cl20_wB_offset :natural := congr_cl20_wA_offset + 6; +constant congr_cl20_wC_offset :natural := congr_cl20_wB_offset + 6; +constant congr_cl20_wD_offset :natural := congr_cl20_wC_offset + 6; +constant congr_cl20_wE_offset :natural := congr_cl20_wD_offset + 6; +constant congr_cl20_wF_offset :natural := congr_cl20_wE_offset + 6; +constant congr_cl20_wG_offset :natural := congr_cl20_wF_offset + 6; +constant congr_cl20_wH_offset :natural := congr_cl20_wG_offset + 6; +constant congr_cl21_wA_offset :natural := congr_cl20_wH_offset + 6; +constant congr_cl21_wB_offset :natural := congr_cl21_wA_offset + 6; +constant congr_cl21_wC_offset :natural := congr_cl21_wB_offset + 6; +constant congr_cl21_wD_offset :natural := congr_cl21_wC_offset + 6; +constant congr_cl21_wE_offset :natural := congr_cl21_wD_offset + 6; +constant congr_cl21_wF_offset :natural := congr_cl21_wE_offset + 6; +constant congr_cl21_wG_offset :natural := congr_cl21_wF_offset + 6; +constant congr_cl21_wH_offset :natural := congr_cl21_wG_offset + 6; +constant congr_cl22_wA_offset :natural := congr_cl21_wH_offset + 6; +constant congr_cl22_wB_offset :natural := congr_cl22_wA_offset + 6; +constant congr_cl22_wC_offset :natural := congr_cl22_wB_offset + 6; +constant congr_cl22_wD_offset :natural := congr_cl22_wC_offset + 6; +constant congr_cl22_wE_offset :natural := congr_cl22_wD_offset + 6; +constant congr_cl22_wF_offset :natural := congr_cl22_wE_offset + 6; +constant congr_cl22_wG_offset :natural := congr_cl22_wF_offset + 6; +constant congr_cl22_wH_offset :natural := congr_cl22_wG_offset + 6; +constant congr_cl23_wA_offset :natural := congr_cl22_wH_offset + 6; +constant congr_cl23_wB_offset :natural := congr_cl23_wA_offset + 6; +constant congr_cl23_wC_offset :natural := congr_cl23_wB_offset + 6; +constant congr_cl23_wD_offset :natural := congr_cl23_wC_offset + 6; +constant congr_cl23_wE_offset :natural := congr_cl23_wD_offset + 6; +constant congr_cl23_wF_offset :natural := congr_cl23_wE_offset + 6; +constant congr_cl23_wG_offset :natural := congr_cl23_wF_offset + 6; +constant congr_cl23_wH_offset :natural := congr_cl23_wG_offset + 6; +constant congr_cl24_wA_offset :natural := congr_cl23_wH_offset + 6; +constant congr_cl24_wB_offset :natural := congr_cl24_wA_offset + 6; +constant congr_cl24_wC_offset :natural := congr_cl24_wB_offset + 6; +constant congr_cl24_wD_offset :natural := congr_cl24_wC_offset + 6; +constant congr_cl24_wE_offset :natural := congr_cl24_wD_offset + 6; +constant congr_cl24_wF_offset :natural := congr_cl24_wE_offset + 6; +constant congr_cl24_wG_offset :natural := congr_cl24_wF_offset + 6; +constant congr_cl24_wH_offset :natural := congr_cl24_wG_offset + 6; +constant congr_cl25_wA_offset :natural := congr_cl24_wH_offset + 6; +constant congr_cl25_wB_offset :natural := congr_cl25_wA_offset + 6; +constant congr_cl25_wC_offset :natural := congr_cl25_wB_offset + 6; +constant congr_cl25_wD_offset :natural := congr_cl25_wC_offset + 6; +constant congr_cl25_wE_offset :natural := congr_cl25_wD_offset + 6; +constant congr_cl25_wF_offset :natural := congr_cl25_wE_offset + 6; +constant congr_cl25_wG_offset :natural := congr_cl25_wF_offset + 6; +constant congr_cl25_wH_offset :natural := congr_cl25_wG_offset + 6; +constant congr_cl26_wA_offset :natural := congr_cl25_wH_offset + 6; +constant congr_cl26_wB_offset :natural := congr_cl26_wA_offset + 6; +constant congr_cl26_wC_offset :natural := congr_cl26_wB_offset + 6; +constant congr_cl26_wD_offset :natural := congr_cl26_wC_offset + 6; +constant congr_cl26_wE_offset :natural := congr_cl26_wD_offset + 6; +constant congr_cl26_wF_offset :natural := congr_cl26_wE_offset + 6; +constant congr_cl26_wG_offset :natural := congr_cl26_wF_offset + 6; +constant congr_cl26_wH_offset :natural := congr_cl26_wG_offset + 6; +constant congr_cl27_wA_offset :natural := congr_cl26_wH_offset + 6; +constant congr_cl27_wB_offset :natural := congr_cl27_wA_offset + 6; +constant congr_cl27_wC_offset :natural := congr_cl27_wB_offset + 6; +constant congr_cl27_wD_offset :natural := congr_cl27_wC_offset + 6; +constant congr_cl27_wE_offset :natural := congr_cl27_wD_offset + 6; +constant congr_cl27_wF_offset :natural := congr_cl27_wE_offset + 6; +constant congr_cl27_wG_offset :natural := congr_cl27_wF_offset + 6; +constant congr_cl27_wH_offset :natural := congr_cl27_wG_offset + 6; +constant congr_cl28_wA_offset :natural := congr_cl27_wH_offset + 6; +constant congr_cl28_wB_offset :natural := congr_cl28_wA_offset + 6; +constant congr_cl28_wC_offset :natural := congr_cl28_wB_offset + 6; +constant congr_cl28_wD_offset :natural := congr_cl28_wC_offset + 6; +constant congr_cl28_wE_offset :natural := congr_cl28_wD_offset + 6; +constant congr_cl28_wF_offset :natural := congr_cl28_wE_offset + 6; +constant congr_cl28_wG_offset :natural := congr_cl28_wF_offset + 6; +constant congr_cl28_wH_offset :natural := congr_cl28_wG_offset + 6; +constant congr_cl29_wA_offset :natural := congr_cl28_wH_offset + 6; +constant congr_cl29_wB_offset :natural := congr_cl29_wA_offset + 6; +constant congr_cl29_wC_offset :natural := congr_cl29_wB_offset + 6; +constant congr_cl29_wD_offset :natural := congr_cl29_wC_offset + 6; +constant congr_cl29_wE_offset :natural := congr_cl29_wD_offset + 6; +constant congr_cl29_wF_offset :natural := congr_cl29_wE_offset + 6; +constant congr_cl29_wG_offset :natural := congr_cl29_wF_offset + 6; +constant congr_cl29_wH_offset :natural := congr_cl29_wG_offset + 6; +constant congr_cl30_wA_offset :natural := congr_cl29_wH_offset + 6; +constant congr_cl30_wB_offset :natural := congr_cl30_wA_offset + 6; +constant congr_cl30_wC_offset :natural := congr_cl30_wB_offset + 6; +constant congr_cl30_wD_offset :natural := congr_cl30_wC_offset + 6; +constant congr_cl30_wE_offset :natural := congr_cl30_wD_offset + 6; +constant congr_cl30_wF_offset :natural := congr_cl30_wE_offset + 6; +constant congr_cl30_wG_offset :natural := congr_cl30_wF_offset + 6; +constant congr_cl30_wH_offset :natural := congr_cl30_wG_offset + 6; +constant congr_cl31_wA_offset :natural := congr_cl30_wH_offset + 6; +constant congr_cl31_wB_offset :natural := congr_cl31_wA_offset + 6; +constant congr_cl31_wC_offset :natural := congr_cl31_wB_offset + 6; +constant congr_cl31_wD_offset :natural := congr_cl31_wC_offset + 6; +constant congr_cl31_wE_offset :natural := congr_cl31_wD_offset + 6; +constant congr_cl31_wF_offset :natural := congr_cl31_wE_offset + 6; +constant congr_cl31_wG_offset :natural := congr_cl31_wF_offset + 6; +constant congr_cl31_wH_offset :natural := congr_cl31_wG_offset + 6; +constant flush_wayA_data_offset :natural := congr_cl31_wH_offset + 6; +constant flush_wayB_data_offset :natural := flush_wayA_data_offset + 6; +constant flush_wayC_data_offset :natural := flush_wayB_data_offset + 6; +constant flush_wayD_data_offset :natural := flush_wayC_data_offset + 6; +constant flush_wayE_data_offset :natural := flush_wayD_data_offset + 6; +constant flush_wayF_data_offset :natural := flush_wayE_data_offset + 6; +constant flush_wayG_data_offset :natural := flush_wayF_data_offset + 6; +constant flush_wayH_data_offset :natural := flush_wayG_data_offset + 6; +constant ex3_flush_cline_offset :natural := flush_wayH_data_offset + 6; +constant ex5_congr_cl_offset :natural := ex3_flush_cline_offset + 1; +constant ex7_congr_cl_offset :natural := ex5_congr_cl_offset + 5; +constant ex8_congr_cl_offset :natural := ex7_congr_cl_offset + 5; +constant ex9_congr_cl_offset :natural := ex8_congr_cl_offset + 5; +constant wayA_val_b_offset :natural := ex9_congr_cl_offset + 5; +constant wayB_val_b_offset :natural := wayA_val_b_offset + 6; +constant wayC_val_b_offset :natural := wayB_val_b_offset + 6; +constant wayD_val_b_offset :natural := wayC_val_b_offset + 6; +constant wayE_val_b_offset :natural := wayD_val_b_offset + 6; +constant wayF_val_b_offset :natural := wayE_val_b_offset + 6; +constant wayG_val_b_offset :natural := wayF_val_b_offset + 6; +constant wayH_val_b_offset :natural := wayG_val_b_offset + 6; +constant ex3_wayA_fxubyp_val_offset :natural := wayH_val_b_offset + 6; +constant ex3_wayB_fxubyp_val_offset :natural := ex3_wayA_fxubyp_val_offset + 1; +constant ex3_wayC_fxubyp_val_offset :natural := ex3_wayB_fxubyp_val_offset + 1; +constant ex3_wayD_fxubyp_val_offset :natural := ex3_wayC_fxubyp_val_offset + 1; +constant ex3_wayE_fxubyp_val_offset :natural := ex3_wayD_fxubyp_val_offset + 1; +constant ex3_wayF_fxubyp_val_offset :natural := ex3_wayE_fxubyp_val_offset + 1; +constant ex3_wayG_fxubyp_val_offset :natural := ex3_wayF_fxubyp_val_offset + 1; +constant ex3_wayH_fxubyp_val_offset :natural := ex3_wayG_fxubyp_val_offset + 1; +constant ex3_wayA_relbyp_val_offset :natural := ex3_wayH_fxubyp_val_offset + 1; +constant ex3_wayB_relbyp_val_offset :natural := ex3_wayA_relbyp_val_offset + 1; +constant ex3_wayC_relbyp_val_offset :natural := ex3_wayB_relbyp_val_offset + 1; +constant ex3_wayD_relbyp_val_offset :natural := ex3_wayC_relbyp_val_offset + 1; +constant ex3_wayE_relbyp_val_offset :natural := ex3_wayD_relbyp_val_offset + 1; +constant ex3_wayF_relbyp_val_offset :natural := ex3_wayE_relbyp_val_offset + 1; +constant ex3_wayG_relbyp_val_offset :natural := ex3_wayF_relbyp_val_offset + 1; +constant ex3_wayH_relbyp_val_offset :natural := ex3_wayG_relbyp_val_offset + 1; +constant ex4_xuop_wayA_upd_offset :natural := ex3_wayH_relbyp_val_offset + 1; +constant ex4_xuop_wayB_upd_offset :natural := ex4_xuop_wayA_upd_offset + 1; +constant ex4_xuop_wayC_upd_offset :natural := ex4_xuop_wayB_upd_offset + 1; +constant ex4_xuop_wayD_upd_offset :natural := ex4_xuop_wayC_upd_offset + 1; +constant ex4_xuop_wayE_upd_offset :natural := ex4_xuop_wayD_upd_offset + 1; +constant ex4_xuop_wayF_upd_offset :natural := ex4_xuop_wayE_upd_offset + 1; +constant ex4_xuop_wayG_upd_offset :natural := ex4_xuop_wayF_upd_offset + 1; +constant ex4_xuop_wayH_upd_offset :natural := ex4_xuop_wayG_upd_offset + 1; +constant ex5_xuop_wayA_upd_offset :natural := ex4_xuop_wayH_upd_offset + 1; +constant ex5_xuop_wayB_upd_offset :natural := ex5_xuop_wayA_upd_offset + 1; +constant ex5_xuop_wayC_upd_offset :natural := ex5_xuop_wayB_upd_offset + 1; +constant ex5_xuop_wayD_upd_offset :natural := ex5_xuop_wayC_upd_offset + 1; +constant ex5_xuop_wayE_upd_offset :natural := ex5_xuop_wayD_upd_offset + 1; +constant ex5_xuop_wayF_upd_offset :natural := ex5_xuop_wayE_upd_offset + 1; +constant ex5_xuop_wayG_upd_offset :natural := ex5_xuop_wayF_upd_offset + 1; +constant ex5_xuop_wayH_upd_offset :natural := ex5_xuop_wayG_upd_offset + 1; +constant inval_clr_lck_wA_offset :natural := ex5_xuop_wayH_upd_offset + 1; +constant inval_clr_lck_wB_offset :natural := inval_clr_lck_wA_offset + 1; +constant inval_clr_lck_wC_offset :natural := inval_clr_lck_wB_offset + 1; +constant inval_clr_lck_wD_offset :natural := inval_clr_lck_wC_offset + 1; +constant inval_clr_lck_wE_offset :natural := inval_clr_lck_wD_offset + 1; +constant inval_clr_lck_wF_offset :natural := inval_clr_lck_wE_offset + 1; +constant inval_clr_lck_wG_offset :natural := inval_clr_lck_wF_offset + 1; +constant inval_clr_lck_wH_offset :natural := inval_clr_lck_wG_offset + 1; +constant congr_cl_m_upd_wayA_offset :natural := inval_clr_lck_wH_offset + 1; +constant congr_cl_m_upd_wayB_offset :natural := congr_cl_m_upd_wayA_offset + 1; +constant congr_cl_m_upd_wayC_offset :natural := congr_cl_m_upd_wayB_offset + 1; +constant congr_cl_m_upd_wayD_offset :natural := congr_cl_m_upd_wayC_offset + 1; +constant congr_cl_m_upd_wayE_offset :natural := congr_cl_m_upd_wayD_offset + 1; +constant congr_cl_m_upd_wayF_offset :natural := congr_cl_m_upd_wayE_offset + 1; +constant congr_cl_m_upd_wayG_offset :natural := congr_cl_m_upd_wayF_offset + 1; +constant congr_cl_m_upd_wayH_offset :natural := congr_cl_m_upd_wayG_offset + 1; +constant ex3_congr_cl_offset :natural := congr_cl_m_upd_wayH_offset + 1; +constant rel24_congr_cl_offset :natural := ex3_congr_cl_offset + 5; +constant relu_s_congr_cl_offset :natural := rel24_congr_cl_offset + 5; +constant reload_way_clr_offset :natural := relu_s_congr_cl_offset + 5; +constant ex4_watchSet_coll_offset :natural := reload_way_clr_offset + 8; +constant rel_wayA_val_b_offset :natural := ex4_watchSet_coll_offset + 1; +constant rel_wayB_val_b_offset :natural := rel_wayA_val_b_offset + 6; +constant rel_wayC_val_b_offset :natural := rel_wayB_val_b_offset + 6; +constant rel_wayD_val_b_offset :natural := rel_wayC_val_b_offset + 6; +constant rel_wayE_val_b_offset :natural := rel_wayD_val_b_offset + 6; +constant rel_wayF_val_b_offset :natural := rel_wayE_val_b_offset + 6; +constant rel_wayG_val_b_offset :natural := rel_wayF_val_b_offset + 6; +constant rel_wayH_val_b_offset :natural := rel_wayG_val_b_offset + 6; +constant rel_val_stg2_offset :natural := rel_wayH_val_b_offset + 6; +constant rel_val_clr_offset :natural := rel_val_stg2_offset + 1; +constant rel_port_upd_offset :natural := rel_val_clr_offset + 1; +constant rel_val_stg4_offset :natural := rel_port_upd_offset + 1; +constant rel_binv_stg4_offset :natural := rel_val_stg4_offset + 1; +constant back_inval_stg3_offset :natural := rel_binv_stg4_offset + 1; +constant back_inval_stg4_offset :natural := back_inval_stg3_offset + 1; +constant back_inval_stg5_offset :natural := back_inval_stg4_offset + 1; +constant binv4_ex4_xuop_upd_offset :natural := back_inval_stg5_offset + 1; +constant binv4_ex4_dir_val_offset :natural := binv4_ex4_xuop_upd_offset + 1; +constant ex4_dir_err_val_offset :natural := binv4_ex4_dir_val_offset + 1; +constant ex5_dir_err_val_offset :natural := ex4_dir_err_val_offset + 1; +constant ex6_dir_err_val_offset :natural := ex5_dir_err_val_offset + 1; +constant derr2_stg_act_offset :natural := ex6_dir_err_val_offset + 1; +constant derr3_stg_act_offset :natural := derr2_stg_act_offset + 1; +constant derr4_stg_act_offset :natural := derr3_stg_act_offset + 1; +constant derr5_stg_act_offset :natural := derr4_stg_act_offset + 1; +constant ex4_dir_multihit_val_b_offset :natural := derr5_stg_act_offset + 1; +constant ex4_n_lsu_ddmh_flush_b_offset :natural := ex4_dir_multihit_val_b_offset + 1; +constant dcarr_up_way_addr_offset :natural := ex4_n_lsu_ddmh_flush_b_offset + 4; +constant reload_wayA_data_offset :natural := dcarr_up_way_addr_offset + 3; +constant reload_wayB_data_offset :natural := reload_wayA_data_offset + 6; +constant reload_wayC_data_offset :natural := reload_wayB_data_offset + 6; +constant reload_wayD_data_offset :natural := reload_wayC_data_offset + 6; +constant reload_wayE_data_offset :natural := reload_wayD_data_offset + 6; +constant reload_wayF_data_offset :natural := reload_wayE_data_offset + 6; +constant reload_wayG_data_offset :natural := reload_wayF_data_offset + 6; +constant reload_wayH_data_offset :natural := reload_wayG_data_offset + 6; +constant binv_wayA_upd_offset :natural := reload_wayH_data_offset + 6; +constant binv_wayB_upd_offset :natural := binv_wayA_upd_offset + 1; +constant binv_wayC_upd_offset :natural := binv_wayB_upd_offset + 1; +constant binv_wayD_upd_offset :natural := binv_wayC_upd_offset + 1; +constant binv_wayE_upd_offset :natural := binv_wayD_upd_offset + 1; +constant binv_wayF_upd_offset :natural := binv_wayE_upd_offset + 1; +constant binv_wayG_upd_offset :natural := binv_wayF_upd_offset + 1; +constant binv_wayH_upd_offset :natural := binv_wayG_upd_offset + 1; +constant binv_wayA_upd2_offset :natural := binv_wayH_upd_offset + 1; +constant binv_wayB_upd2_offset :natural := binv_wayA_upd2_offset + 1; +constant binv_wayC_upd2_offset :natural := binv_wayB_upd2_offset + 1; +constant binv_wayD_upd2_offset :natural := binv_wayC_upd2_offset + 1; +constant binv_wayE_upd2_offset :natural := binv_wayD_upd2_offset + 1; +constant binv_wayF_upd2_offset :natural := binv_wayE_upd2_offset + 1; +constant binv_wayG_upd2_offset :natural := binv_wayF_upd2_offset + 1; +constant binv_wayH_upd2_offset :natural := binv_wayG_upd2_offset + 1; +constant binv_wayA_upd3_offset :natural := binv_wayH_upd2_offset + 1; +constant binv_wayB_upd3_offset :natural := binv_wayA_upd3_offset + 1; +constant binv_wayC_upd3_offset :natural := binv_wayB_upd3_offset + 1; +constant binv_wayD_upd3_offset :natural := binv_wayC_upd3_offset + 1; +constant binv_wayE_upd3_offset :natural := binv_wayD_upd3_offset + 1; +constant binv_wayF_upd3_offset :natural := binv_wayE_upd3_offset + 1; +constant binv_wayG_upd3_offset :natural := binv_wayF_upd3_offset + 1; +constant binv_wayH_upd3_offset :natural := binv_wayG_upd3_offset + 1; +constant reload_wayA_upd_offset :natural := binv_wayH_upd3_offset + 1; +constant reload_wayB_upd_offset :natural := reload_wayA_upd_offset + 1; +constant reload_wayC_upd_offset :natural := reload_wayB_upd_offset + 1; +constant reload_wayD_upd_offset :natural := reload_wayC_upd_offset + 1; +constant reload_wayE_upd_offset :natural := reload_wayD_upd_offset + 1; +constant reload_wayF_upd_offset :natural := reload_wayE_upd_offset + 1; +constant reload_wayG_upd_offset :natural := reload_wayF_upd_offset + 1; +constant reload_wayH_upd_offset :natural := reload_wayG_upd_offset + 1; +constant reload_wayA_upd2_offset :natural := reload_wayH_upd_offset + 1; +constant reload_wayB_upd2_offset :natural := reload_wayA_upd2_offset + 1; +constant reload_wayC_upd2_offset :natural := reload_wayB_upd2_offset + 1; +constant reload_wayD_upd2_offset :natural := reload_wayC_upd2_offset + 1; +constant reload_wayE_upd2_offset :natural := reload_wayD_upd2_offset + 1; +constant reload_wayF_upd2_offset :natural := reload_wayE_upd2_offset + 1; +constant reload_wayG_upd2_offset :natural := reload_wayF_upd2_offset + 1; +constant reload_wayH_upd2_offset :natural := reload_wayG_upd2_offset + 1; +constant reload_wayA_upd3_offset :natural := reload_wayH_upd2_offset + 1; +constant reload_wayB_upd3_offset :natural := reload_wayA_upd3_offset + 1; +constant reload_wayC_upd3_offset :natural := reload_wayB_upd3_offset + 1; +constant reload_wayD_upd3_offset :natural := reload_wayC_upd3_offset + 1; +constant reload_wayE_upd3_offset :natural := reload_wayD_upd3_offset + 1; +constant reload_wayF_upd3_offset :natural := reload_wayE_upd3_offset + 1; +constant reload_wayG_upd3_offset :natural := reload_wayF_upd3_offset + 1; +constant reload_wayH_upd3_offset :natural := reload_wayG_upd3_offset + 1; +constant ex3_store_instr_offset :natural := reload_wayH_upd3_offset + 1; +constant ex3_lock_set_offset :natural := ex3_store_instr_offset + 1; +constant ex4_lock_set_offset :natural := ex3_lock_set_offset + 1; +constant ex5_lock_set_offset :natural := ex4_lock_set_offset + 1; +constant ex3_lock_clr_offset :natural := ex5_lock_set_offset + 1; +constant ex3_xuop_val_offset :natural := ex3_lock_clr_offset + 1; +constant ex4_xuop_val_offset :natural := ex3_xuop_val_offset + 1; +constant ex5_xuop_val_offset :natural := ex4_xuop_val_offset + 1; +constant rel_lock_set_offset :natural := ex5_xuop_val_offset + 1; +constant dcpar_err_stg1_offset :natural := rel_lock_set_offset + 1; +constant dcpar_err_stg2_offset :natural := dcpar_err_stg1_offset + 1; +constant dcpar_err_way_offset :natural := dcpar_err_stg2_offset + 1; +constant dcpar_err_way_inval_offset :natural := dcpar_err_way_offset + 8; +constant dcpar_err_cntr_offset :natural := dcpar_err_way_inval_offset + 8; +constant dcpar_err_ind_sel_offset :natural := dcpar_err_cntr_offset + 2; +constant dcpar_err_push_queue_offset :natural := dcpar_err_ind_sel_offset + 2; +constant ex5_way_hit_offset :natural := dcpar_err_push_queue_offset + 1; +constant ex7_way_hit_offset :natural := ex5_way_hit_offset + 8; +constant ex8_way_hit_offset :natural := ex7_way_hit_offset + 8; +constant ex9_way_hit_offset :natural := ex8_way_hit_offset + 8; +constant ex4_lose_watch_offset :natural := ex9_way_hit_offset + 8; +constant xucr0_cslc_xuop_offset :natural := ex4_lose_watch_offset + 4; +constant xucr0_cslc_binv_offset :natural := xucr0_cslc_xuop_offset + 1; +constant dci_compl_offset :natural := xucr0_cslc_binv_offset + 1; +constant dci_inval_all_offset :natural := dci_compl_offset + 1; +constant inv2_val_offset :natural := dci_inval_all_offset + 1; +constant perf_lsu_evnts_offset :natural := inv2_val_offset + 1; +constant lock_flash_clear_offset :natural := perf_lsu_evnts_offset + 5; +constant lock_flash_clear_val_offset :natural := lock_flash_clear_offset + 1; +constant rel_port_wren_offset :natural := lock_flash_clear_val_offset + 1; +constant ex3_thrd_id_offset :natural := rel_port_wren_offset + 1; +constant ex5_thrd_id_offset :natural := ex3_thrd_id_offset + 4; +constant ex3_l_fld_b1_offset :natural := ex5_thrd_id_offset + 4; +constant ex3_watch_set_offset :natural := ex3_l_fld_b1_offset + 1; +constant ex4_watch_set_offset :natural := ex3_watch_set_offset + 1; +constant ex5_watch_set_offset :natural := ex4_watch_set_offset + 1; +constant ex3_watch_clr_offset :natural := ex5_watch_set_offset + 1; +constant ex3_watch_clr_all_offset :natural := ex3_watch_clr_offset + 1; +constant ex3_watch_chk_offset :natural := ex3_watch_clr_all_offset + 1; +constant ex4_watch_chk_offset :natural := ex3_watch_chk_offset + 1; +constant ex5_watch_chk_offset :natural := ex4_watch_chk_offset + 1; +constant ex3_wclr_all_upd_offset :natural := ex5_watch_chk_offset + 1; +constant ex4_wclr_all_val_offset :natural := ex3_wclr_all_upd_offset + 1; +constant ex5_wclr_all_val_offset :natural := ex4_wclr_all_val_offset + 1; +constant ex6_wclr_all_val_offset :natural := ex5_wclr_all_val_offset + 1; +constant rel_thrd_id_offset :natural := ex6_wclr_all_val_offset + 1; +constant rel_watch_set_offset :natural := rel_thrd_id_offset + 4; +constant ex5_cr_watch_offset :natural := rel_watch_set_offset + 1; +constant ex4_watch_clr_all_offset :natural := ex5_cr_watch_offset + 1; +constant ex5_watch_clr_all_offset :natural := ex4_watch_clr_all_offset + 4; +constant ex6_watch_clr_all_offset :natural := ex5_watch_clr_all_offset + 4; +constant ex5_watch_clr_all_val_offset :natural := ex6_watch_clr_all_offset + 4; +constant ex5_lost_watch_upd_offset :natural := ex5_watch_clr_all_val_offset + 1; +constant ex4_watchlost_set_offset :natural := ex5_lost_watch_upd_offset + 4; +constant ex5_watchlost_set_offset :natural := ex4_watchlost_set_offset + 4; +constant rel_lost_watch_binv_offset :natural := ex5_watchlost_set_offset + 4; +constant lost_watch_evict_ovl_offset :natural := rel_lost_watch_binv_offset + 4; +constant rel_lost_watch_upd_offset :natural := lost_watch_evict_ovl_offset + 4; +constant lost_watch_evict_val_offset :natural := rel_lost_watch_upd_offset + 4; +constant lost_watch_inter_thrd_offset :natural := lost_watch_evict_val_offset + 4; +constant stm_watchlost_state_offset :natural := lost_watch_inter_thrd_offset + 4; +constant ex5_xuop_p0_upd_offset :natural := stm_watchlost_state_offset + 4; +constant rel_val_stgu_offset :natural := ex5_xuop_p0_upd_offset + 1; +constant p0_wren_offset :natural := rel_val_stgu_offset + 1; +constant p0_wren_cpy_offset :natural := p0_wren_offset + 1; +constant p0_wren_stg_offset :natural := p0_wren_cpy_offset + 1; +constant p1_wren_offset :natural := p0_wren_stg_offset + 1; +constant p1_wren_cpy_offset :natural := p1_wren_offset + 1; +constant ex3_thrd_m_offset :natural := p1_wren_cpy_offset + 1; +constant ex4_thrd_m_offset :natural := ex3_thrd_m_offset + 1; +constant ex5_thrd_m_offset :natural := ex4_thrd_m_offset + 1; +constant ex6_thrd_m_offset :natural := ex5_thrd_m_offset + 1; +constant ex7_ld_par_err_offset :natural := ex6_thrd_m_offset + 1; +constant ex8_ld_par_err_offset :natural := ex7_ld_par_err_offset + 1; +constant ex9_ld_par_err_offset :natural := ex8_ld_par_err_offset + 1; +constant ex6_ld_valid_offset :natural := ex9_ld_par_err_offset + 1; +constant ex7_ld_valid_offset :natural := ex6_ld_valid_offset + 1; +constant ex8_ld_valid_offset :natural := ex7_ld_valid_offset + 1; +constant ex9_ld_valid_offset :natural := ex8_ld_valid_offset + 1; +constant rel_in_progress_offset :natural := ex9_ld_valid_offset + 1; +constant inj_dir_multihit_offset :natural := rel_in_progress_offset + 1; +constant congr_cl_ex2_ex3_cmp_offset :natural := inj_dir_multihit_offset + 1; +constant congr_cl_ex2_ex4_cmp_offset :natural := congr_cl_ex2_ex3_cmp_offset + 1; +constant congr_cl_ex2_ex5_cmp_offset :natural := congr_cl_ex2_ex4_cmp_offset + 1; +constant congr_cl_ex2_ex6_cmp_offset :natural := congr_cl_ex2_ex5_cmp_offset + 1; +constant congr_cl_ex3_ex4_cmp_offset :natural := congr_cl_ex2_ex6_cmp_offset + 1; +constant congr_cl_ex3_ex5_cmp_offset :natural := congr_cl_ex3_ex4_cmp_offset + 1; +constant congr_cl_ex3_ex6_cmp_offset :natural := congr_cl_ex3_ex5_cmp_offset + 1; +constant congr_cl_ex4_ex5_cmp_offset :natural := congr_cl_ex3_ex6_cmp_offset + 1; +constant congr_cl_ex4_ex6_cmp_offset :natural := congr_cl_ex4_ex5_cmp_offset + 1; +constant congr_cl_ex4_ex7_cmp_offset :natural := congr_cl_ex4_ex6_cmp_offset + 1; +constant congr_cl_ex2_relu_cmp_offset :natural := congr_cl_ex4_ex7_cmp_offset + 1; +constant congr_cl_ex2_relu_s_cmp_offset :natural := congr_cl_ex2_relu_cmp_offset + 1; +constant congr_cl_ex2_rel_upd_cmp_offset :natural := congr_cl_ex2_relu_s_cmp_offset + 1; +constant congr_cl_rel13_ex3_cmp_offset :natural := congr_cl_ex2_rel_upd_cmp_offset + 1; +constant congr_cl_rel13_ex4_cmp_offset :natural := congr_cl_rel13_ex3_cmp_offset + 1; +constant congr_cl_rel13_ex5_cmp_offset :natural := congr_cl_rel13_ex4_cmp_offset + 1; +constant congr_cl_rel13_ex6_cmp_offset :natural := congr_cl_rel13_ex5_cmp_offset + 1; +constant congr_cl_rel13_relu_cmp_offset :natural := congr_cl_rel13_ex6_cmp_offset + 1; +constant congr_cl_rel13_relu_s_cmp_offset :natural := congr_cl_rel13_relu_cmp_offset + 1; +constant congr_cl_rel13_rel_upd_cmp_offset :natural := congr_cl_rel13_relu_s_cmp_offset + 1; +constant rel24_congr_cl_ex4_cmp_offset :natural := congr_cl_rel13_rel_upd_cmp_offset + 1; +constant rel24_congr_cl_ex5_cmp_offset :natural := rel24_congr_cl_ex4_cmp_offset + 1; +constant rel24_congr_cl_ex6_cmp_offset :natural := rel24_congr_cl_ex5_cmp_offset + 1; +constant relu_congr_cl_ex5_cmp_offset :natural := rel24_congr_cl_ex6_cmp_offset + 1; +constant relu_congr_cl_ex6_cmp_offset :natural := relu_congr_cl_ex5_cmp_offset + 1; +constant relu_congr_cl_ex7_cmp_offset :natural := relu_congr_cl_ex6_cmp_offset + 1; +constant ex4_err_det_way_offset :natural := relu_congr_cl_ex7_cmp_offset + 1; +constant ex4_perr_lck_lost_offset :natural := ex4_err_det_way_offset + 8; +constant ex4_perr_watch_lost_offset :natural := ex4_perr_lck_lost_offset + 1; +constant dcperr_lock_lost_offset :natural := ex4_perr_watch_lost_offset + 4; +constant binv7_ex7_way_upd_offset :natural := dcperr_lock_lost_offset + 1; +constant binv5_ex5_dir_data_offset :natural := binv7_ex7_way_upd_offset + 8; +constant binv7_ex7_dir_data_offset :natural := binv5_ex5_dir_data_offset + 5; +constant binv5_inval_watch_val_offset :natural := binv7_ex7_dir_data_offset + 5; +constant binv5_inval_lock_val_offset :natural := binv5_inval_watch_val_offset + 4; +constant ex4_snd_ld_l2_offset :natural := binv5_inval_lock_val_offset + 1; +constant ex4_ldq_full_flush_b_offset :natural := ex4_snd_ld_l2_offset + 1; +constant ex4_miss_offset :natural := ex4_ldq_full_flush_b_offset + 1; +constant my_spare0_latches_offset :natural := ex4_miss_offset + 1; +constant my_spare1_latches_offset :natural := my_spare0_latches_offset + 17; +constant rel_l1dump_cslc_offset :natural := my_spare1_latches_offset + 16; +constant rel_in_prog_stg1_offset :natural := rel_l1dump_cslc_offset + 1; +constant rel_in_prog_stg2_offset :natural := rel_in_prog_stg1_offset + 1; +constant rel_in_prog_stg3_offset :natural := rel_in_prog_stg2_offset + 1; +constant rel_in_prog_stg4_offset :natural := rel_in_prog_stg3_offset + 1; +constant rel_in_prog_stg5_offset :natural := rel_in_prog_stg4_offset + 1; +constant dcpar_err_stg1_act_offset :natural := rel_in_prog_stg5_offset + 1; +constant dcpar_err_stg2_act_offset :natural := dcpar_err_stg1_act_offset + 1; +constant rel3_perr_stg_act_offset :natural := dcpar_err_stg2_act_offset + 1; +constant rel4_perr_stg_act_offset :natural := rel3_perr_stg_act_offset + 1; +constant scan_right :natural := rel4_perr_stg_act_offset + 1 - 1; +---------------------------- +-- signals +---------------------------- +signal p0_congr_cl0_m :std_ulogic; +signal p1_congr_cl0_m :std_ulogic; +signal p0_congr_cl0_act_d :std_ulogic; +signal p0_congr_cl0_act_q :std_ulogic; +signal p1_congr_cl0_act_d :std_ulogic; +signal p1_congr_cl0_act_q :std_ulogic; +signal congr_cl0_act :std_ulogic; +signal congr_cl0_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl0_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu0_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd0_wayA :std_ulogic; +signal p1_way_data_upd0_wayA :std_ulogic; +signal congr_cl0_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl0_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu0_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd0_wayB :std_ulogic; +signal p1_way_data_upd0_wayB :std_ulogic; +signal congr_cl0_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl0_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu0_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd0_wayC :std_ulogic; +signal p1_way_data_upd0_wayC :std_ulogic; +signal congr_cl0_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl0_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu0_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd0_wayD :std_ulogic; +signal p1_way_data_upd0_wayD :std_ulogic; +signal congr_cl0_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl0_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu0_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd0_wayE :std_ulogic; +signal p1_way_data_upd0_wayE :std_ulogic; +signal congr_cl0_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl0_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu0_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd0_wayF :std_ulogic; +signal p1_way_data_upd0_wayF :std_ulogic; +signal congr_cl0_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl0_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu0_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd0_wayG :std_ulogic; +signal p1_way_data_upd0_wayG :std_ulogic; +signal congr_cl0_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl0_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu0_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd0_wayH :std_ulogic; +signal p1_way_data_upd0_wayH :std_ulogic; +signal p0_congr_cl1_m :std_ulogic; +signal p1_congr_cl1_m :std_ulogic; +signal p0_congr_cl1_act_d :std_ulogic; +signal p0_congr_cl1_act_q :std_ulogic; +signal p1_congr_cl1_act_d :std_ulogic; +signal p1_congr_cl1_act_q :std_ulogic; +signal congr_cl1_act :std_ulogic; +signal congr_cl1_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl1_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu1_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd1_wayA :std_ulogic; +signal p1_way_data_upd1_wayA :std_ulogic; +signal congr_cl1_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl1_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu1_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd1_wayB :std_ulogic; +signal p1_way_data_upd1_wayB :std_ulogic; +signal congr_cl1_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl1_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu1_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd1_wayC :std_ulogic; +signal p1_way_data_upd1_wayC :std_ulogic; +signal congr_cl1_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl1_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu1_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd1_wayD :std_ulogic; +signal p1_way_data_upd1_wayD :std_ulogic; +signal congr_cl1_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl1_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu1_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd1_wayE :std_ulogic; +signal p1_way_data_upd1_wayE :std_ulogic; +signal congr_cl1_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl1_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu1_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd1_wayF :std_ulogic; +signal p1_way_data_upd1_wayF :std_ulogic; +signal congr_cl1_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl1_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu1_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd1_wayG :std_ulogic; +signal p1_way_data_upd1_wayG :std_ulogic; +signal congr_cl1_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl1_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu1_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd1_wayH :std_ulogic; +signal p1_way_data_upd1_wayH :std_ulogic; +signal p0_congr_cl2_m :std_ulogic; +signal p1_congr_cl2_m :std_ulogic; +signal p0_congr_cl2_act_d :std_ulogic; +signal p0_congr_cl2_act_q :std_ulogic; +signal p1_congr_cl2_act_d :std_ulogic; +signal p1_congr_cl2_act_q :std_ulogic; +signal congr_cl2_act :std_ulogic; +signal congr_cl2_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl2_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu2_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd2_wayA :std_ulogic; +signal p1_way_data_upd2_wayA :std_ulogic; +signal congr_cl2_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl2_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu2_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd2_wayB :std_ulogic; +signal p1_way_data_upd2_wayB :std_ulogic; +signal congr_cl2_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl2_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu2_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd2_wayC :std_ulogic; +signal p1_way_data_upd2_wayC :std_ulogic; +signal congr_cl2_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl2_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu2_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd2_wayD :std_ulogic; +signal p1_way_data_upd2_wayD :std_ulogic; +signal congr_cl2_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl2_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu2_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd2_wayE :std_ulogic; +signal p1_way_data_upd2_wayE :std_ulogic; +signal congr_cl2_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl2_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu2_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd2_wayF :std_ulogic; +signal p1_way_data_upd2_wayF :std_ulogic; +signal congr_cl2_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl2_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu2_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd2_wayG :std_ulogic; +signal p1_way_data_upd2_wayG :std_ulogic; +signal congr_cl2_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl2_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu2_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd2_wayH :std_ulogic; +signal p1_way_data_upd2_wayH :std_ulogic; +signal p0_congr_cl3_m :std_ulogic; +signal p1_congr_cl3_m :std_ulogic; +signal p0_congr_cl3_act_d :std_ulogic; +signal p0_congr_cl3_act_q :std_ulogic; +signal p1_congr_cl3_act_d :std_ulogic; +signal p1_congr_cl3_act_q :std_ulogic; +signal congr_cl3_act :std_ulogic; +signal congr_cl3_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl3_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu3_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd3_wayA :std_ulogic; +signal p1_way_data_upd3_wayA :std_ulogic; +signal congr_cl3_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl3_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu3_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd3_wayB :std_ulogic; +signal p1_way_data_upd3_wayB :std_ulogic; +signal congr_cl3_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl3_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu3_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd3_wayC :std_ulogic; +signal p1_way_data_upd3_wayC :std_ulogic; +signal congr_cl3_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl3_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu3_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd3_wayD :std_ulogic; +signal p1_way_data_upd3_wayD :std_ulogic; +signal congr_cl3_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl3_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu3_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd3_wayE :std_ulogic; +signal p1_way_data_upd3_wayE :std_ulogic; +signal congr_cl3_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl3_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu3_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd3_wayF :std_ulogic; +signal p1_way_data_upd3_wayF :std_ulogic; +signal congr_cl3_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl3_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu3_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd3_wayG :std_ulogic; +signal p1_way_data_upd3_wayG :std_ulogic; +signal congr_cl3_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl3_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu3_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd3_wayH :std_ulogic; +signal p1_way_data_upd3_wayH :std_ulogic; +signal p0_congr_cl4_m :std_ulogic; +signal p1_congr_cl4_m :std_ulogic; +signal p0_congr_cl4_act_d :std_ulogic; +signal p0_congr_cl4_act_q :std_ulogic; +signal p1_congr_cl4_act_d :std_ulogic; +signal p1_congr_cl4_act_q :std_ulogic; +signal congr_cl4_act :std_ulogic; +signal congr_cl4_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl4_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu4_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd4_wayA :std_ulogic; +signal p1_way_data_upd4_wayA :std_ulogic; +signal congr_cl4_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl4_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu4_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd4_wayB :std_ulogic; +signal p1_way_data_upd4_wayB :std_ulogic; +signal congr_cl4_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl4_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu4_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd4_wayC :std_ulogic; +signal p1_way_data_upd4_wayC :std_ulogic; +signal congr_cl4_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl4_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu4_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd4_wayD :std_ulogic; +signal p1_way_data_upd4_wayD :std_ulogic; +signal congr_cl4_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl4_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu4_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd4_wayE :std_ulogic; +signal p1_way_data_upd4_wayE :std_ulogic; +signal congr_cl4_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl4_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu4_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd4_wayF :std_ulogic; +signal p1_way_data_upd4_wayF :std_ulogic; +signal congr_cl4_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl4_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu4_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd4_wayG :std_ulogic; +signal p1_way_data_upd4_wayG :std_ulogic; +signal congr_cl4_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl4_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu4_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd4_wayH :std_ulogic; +signal p1_way_data_upd4_wayH :std_ulogic; +signal p0_congr_cl5_m :std_ulogic; +signal p1_congr_cl5_m :std_ulogic; +signal p0_congr_cl5_act_d :std_ulogic; +signal p0_congr_cl5_act_q :std_ulogic; +signal p1_congr_cl5_act_d :std_ulogic; +signal p1_congr_cl5_act_q :std_ulogic; +signal congr_cl5_act :std_ulogic; +signal congr_cl5_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl5_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu5_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd5_wayA :std_ulogic; +signal p1_way_data_upd5_wayA :std_ulogic; +signal congr_cl5_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl5_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu5_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd5_wayB :std_ulogic; +signal p1_way_data_upd5_wayB :std_ulogic; +signal congr_cl5_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl5_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu5_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd5_wayC :std_ulogic; +signal p1_way_data_upd5_wayC :std_ulogic; +signal congr_cl5_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl5_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu5_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd5_wayD :std_ulogic; +signal p1_way_data_upd5_wayD :std_ulogic; +signal congr_cl5_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl5_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu5_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd5_wayE :std_ulogic; +signal p1_way_data_upd5_wayE :std_ulogic; +signal congr_cl5_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl5_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu5_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd5_wayF :std_ulogic; +signal p1_way_data_upd5_wayF :std_ulogic; +signal congr_cl5_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl5_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu5_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd5_wayG :std_ulogic; +signal p1_way_data_upd5_wayG :std_ulogic; +signal congr_cl5_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl5_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu5_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd5_wayH :std_ulogic; +signal p1_way_data_upd5_wayH :std_ulogic; +signal p0_congr_cl6_m :std_ulogic; +signal p1_congr_cl6_m :std_ulogic; +signal p0_congr_cl6_act_d :std_ulogic; +signal p0_congr_cl6_act_q :std_ulogic; +signal p1_congr_cl6_act_d :std_ulogic; +signal p1_congr_cl6_act_q :std_ulogic; +signal congr_cl6_act :std_ulogic; +signal congr_cl6_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl6_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu6_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd6_wayA :std_ulogic; +signal p1_way_data_upd6_wayA :std_ulogic; +signal congr_cl6_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl6_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu6_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd6_wayB :std_ulogic; +signal p1_way_data_upd6_wayB :std_ulogic; +signal congr_cl6_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl6_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu6_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd6_wayC :std_ulogic; +signal p1_way_data_upd6_wayC :std_ulogic; +signal congr_cl6_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl6_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu6_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd6_wayD :std_ulogic; +signal p1_way_data_upd6_wayD :std_ulogic; +signal congr_cl6_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl6_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu6_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd6_wayE :std_ulogic; +signal p1_way_data_upd6_wayE :std_ulogic; +signal congr_cl6_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl6_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu6_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd6_wayF :std_ulogic; +signal p1_way_data_upd6_wayF :std_ulogic; +signal congr_cl6_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl6_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu6_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd6_wayG :std_ulogic; +signal p1_way_data_upd6_wayG :std_ulogic; +signal congr_cl6_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl6_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu6_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd6_wayH :std_ulogic; +signal p1_way_data_upd6_wayH :std_ulogic; +signal p0_congr_cl7_m :std_ulogic; +signal p1_congr_cl7_m :std_ulogic; +signal p0_congr_cl7_act_d :std_ulogic; +signal p0_congr_cl7_act_q :std_ulogic; +signal p1_congr_cl7_act_d :std_ulogic; +signal p1_congr_cl7_act_q :std_ulogic; +signal congr_cl7_act :std_ulogic; +signal congr_cl7_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl7_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu7_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd7_wayA :std_ulogic; +signal p1_way_data_upd7_wayA :std_ulogic; +signal congr_cl7_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl7_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu7_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd7_wayB :std_ulogic; +signal p1_way_data_upd7_wayB :std_ulogic; +signal congr_cl7_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl7_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu7_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd7_wayC :std_ulogic; +signal p1_way_data_upd7_wayC :std_ulogic; +signal congr_cl7_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl7_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu7_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd7_wayD :std_ulogic; +signal p1_way_data_upd7_wayD :std_ulogic; +signal congr_cl7_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl7_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu7_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd7_wayE :std_ulogic; +signal p1_way_data_upd7_wayE :std_ulogic; +signal congr_cl7_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl7_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu7_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd7_wayF :std_ulogic; +signal p1_way_data_upd7_wayF :std_ulogic; +signal congr_cl7_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl7_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu7_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd7_wayG :std_ulogic; +signal p1_way_data_upd7_wayG :std_ulogic; +signal congr_cl7_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl7_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu7_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd7_wayH :std_ulogic; +signal p1_way_data_upd7_wayH :std_ulogic; +signal p0_congr_cl8_m :std_ulogic; +signal p1_congr_cl8_m :std_ulogic; +signal p0_congr_cl8_act_d :std_ulogic; +signal p0_congr_cl8_act_q :std_ulogic; +signal p1_congr_cl8_act_d :std_ulogic; +signal p1_congr_cl8_act_q :std_ulogic; +signal congr_cl8_act :std_ulogic; +signal congr_cl8_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl8_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu8_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd8_wayA :std_ulogic; +signal p1_way_data_upd8_wayA :std_ulogic; +signal congr_cl8_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl8_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu8_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd8_wayB :std_ulogic; +signal p1_way_data_upd8_wayB :std_ulogic; +signal congr_cl8_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl8_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu8_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd8_wayC :std_ulogic; +signal p1_way_data_upd8_wayC :std_ulogic; +signal congr_cl8_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl8_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu8_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd8_wayD :std_ulogic; +signal p1_way_data_upd8_wayD :std_ulogic; +signal congr_cl8_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl8_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu8_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd8_wayE :std_ulogic; +signal p1_way_data_upd8_wayE :std_ulogic; +signal congr_cl8_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl8_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu8_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd8_wayF :std_ulogic; +signal p1_way_data_upd8_wayF :std_ulogic; +signal congr_cl8_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl8_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu8_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd8_wayG :std_ulogic; +signal p1_way_data_upd8_wayG :std_ulogic; +signal congr_cl8_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl8_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu8_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd8_wayH :std_ulogic; +signal p1_way_data_upd8_wayH :std_ulogic; +signal p0_congr_cl9_m :std_ulogic; +signal p1_congr_cl9_m :std_ulogic; +signal p0_congr_cl9_act_d :std_ulogic; +signal p0_congr_cl9_act_q :std_ulogic; +signal p1_congr_cl9_act_d :std_ulogic; +signal p1_congr_cl9_act_q :std_ulogic; +signal congr_cl9_act :std_ulogic; +signal congr_cl9_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl9_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu9_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd9_wayA :std_ulogic; +signal p1_way_data_upd9_wayA :std_ulogic; +signal congr_cl9_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl9_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu9_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd9_wayB :std_ulogic; +signal p1_way_data_upd9_wayB :std_ulogic; +signal congr_cl9_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl9_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu9_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd9_wayC :std_ulogic; +signal p1_way_data_upd9_wayC :std_ulogic; +signal congr_cl9_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl9_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu9_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd9_wayD :std_ulogic; +signal p1_way_data_upd9_wayD :std_ulogic; +signal congr_cl9_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl9_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu9_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd9_wayE :std_ulogic; +signal p1_way_data_upd9_wayE :std_ulogic; +signal congr_cl9_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl9_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu9_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd9_wayF :std_ulogic; +signal p1_way_data_upd9_wayF :std_ulogic; +signal congr_cl9_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl9_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu9_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd9_wayG :std_ulogic; +signal p1_way_data_upd9_wayG :std_ulogic; +signal congr_cl9_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl9_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu9_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd9_wayH :std_ulogic; +signal p1_way_data_upd9_wayH :std_ulogic; +signal p0_congr_cl10_m :std_ulogic; +signal p1_congr_cl10_m :std_ulogic; +signal p0_congr_cl10_act_d :std_ulogic; +signal p0_congr_cl10_act_q :std_ulogic; +signal p1_congr_cl10_act_d :std_ulogic; +signal p1_congr_cl10_act_q :std_ulogic; +signal congr_cl10_act :std_ulogic; +signal congr_cl10_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl10_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu10_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd10_wayA :std_ulogic; +signal p1_way_data_upd10_wayA :std_ulogic; +signal congr_cl10_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl10_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu10_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd10_wayB :std_ulogic; +signal p1_way_data_upd10_wayB :std_ulogic; +signal congr_cl10_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl10_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu10_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd10_wayC :std_ulogic; +signal p1_way_data_upd10_wayC :std_ulogic; +signal congr_cl10_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl10_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu10_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd10_wayD :std_ulogic; +signal p1_way_data_upd10_wayD :std_ulogic; +signal congr_cl10_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl10_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu10_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd10_wayE :std_ulogic; +signal p1_way_data_upd10_wayE :std_ulogic; +signal congr_cl10_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl10_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu10_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd10_wayF :std_ulogic; +signal p1_way_data_upd10_wayF :std_ulogic; +signal congr_cl10_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl10_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu10_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd10_wayG :std_ulogic; +signal p1_way_data_upd10_wayG :std_ulogic; +signal congr_cl10_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl10_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu10_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd10_wayH :std_ulogic; +signal p1_way_data_upd10_wayH :std_ulogic; +signal p0_congr_cl11_m :std_ulogic; +signal p1_congr_cl11_m :std_ulogic; +signal p0_congr_cl11_act_d :std_ulogic; +signal p0_congr_cl11_act_q :std_ulogic; +signal p1_congr_cl11_act_d :std_ulogic; +signal p1_congr_cl11_act_q :std_ulogic; +signal congr_cl11_act :std_ulogic; +signal congr_cl11_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl11_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu11_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd11_wayA :std_ulogic; +signal p1_way_data_upd11_wayA :std_ulogic; +signal congr_cl11_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl11_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu11_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd11_wayB :std_ulogic; +signal p1_way_data_upd11_wayB :std_ulogic; +signal congr_cl11_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl11_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu11_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd11_wayC :std_ulogic; +signal p1_way_data_upd11_wayC :std_ulogic; +signal congr_cl11_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl11_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu11_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd11_wayD :std_ulogic; +signal p1_way_data_upd11_wayD :std_ulogic; +signal congr_cl11_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl11_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu11_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd11_wayE :std_ulogic; +signal p1_way_data_upd11_wayE :std_ulogic; +signal congr_cl11_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl11_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu11_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd11_wayF :std_ulogic; +signal p1_way_data_upd11_wayF :std_ulogic; +signal congr_cl11_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl11_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu11_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd11_wayG :std_ulogic; +signal p1_way_data_upd11_wayG :std_ulogic; +signal congr_cl11_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl11_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu11_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd11_wayH :std_ulogic; +signal p1_way_data_upd11_wayH :std_ulogic; +signal p0_congr_cl12_m :std_ulogic; +signal p1_congr_cl12_m :std_ulogic; +signal p0_congr_cl12_act_d :std_ulogic; +signal p0_congr_cl12_act_q :std_ulogic; +signal p1_congr_cl12_act_d :std_ulogic; +signal p1_congr_cl12_act_q :std_ulogic; +signal congr_cl12_act :std_ulogic; +signal congr_cl12_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl12_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu12_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd12_wayA :std_ulogic; +signal p1_way_data_upd12_wayA :std_ulogic; +signal congr_cl12_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl12_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu12_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd12_wayB :std_ulogic; +signal p1_way_data_upd12_wayB :std_ulogic; +signal congr_cl12_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl12_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu12_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd12_wayC :std_ulogic; +signal p1_way_data_upd12_wayC :std_ulogic; +signal congr_cl12_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl12_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu12_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd12_wayD :std_ulogic; +signal p1_way_data_upd12_wayD :std_ulogic; +signal congr_cl12_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl12_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu12_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd12_wayE :std_ulogic; +signal p1_way_data_upd12_wayE :std_ulogic; +signal congr_cl12_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl12_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu12_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd12_wayF :std_ulogic; +signal p1_way_data_upd12_wayF :std_ulogic; +signal congr_cl12_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl12_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu12_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd12_wayG :std_ulogic; +signal p1_way_data_upd12_wayG :std_ulogic; +signal congr_cl12_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl12_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu12_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd12_wayH :std_ulogic; +signal p1_way_data_upd12_wayH :std_ulogic; +signal p0_congr_cl13_m :std_ulogic; +signal p1_congr_cl13_m :std_ulogic; +signal p0_congr_cl13_act_d :std_ulogic; +signal p0_congr_cl13_act_q :std_ulogic; +signal p1_congr_cl13_act_d :std_ulogic; +signal p1_congr_cl13_act_q :std_ulogic; +signal congr_cl13_act :std_ulogic; +signal congr_cl13_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl13_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu13_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd13_wayA :std_ulogic; +signal p1_way_data_upd13_wayA :std_ulogic; +signal congr_cl13_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl13_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu13_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd13_wayB :std_ulogic; +signal p1_way_data_upd13_wayB :std_ulogic; +signal congr_cl13_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl13_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu13_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd13_wayC :std_ulogic; +signal p1_way_data_upd13_wayC :std_ulogic; +signal congr_cl13_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl13_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu13_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd13_wayD :std_ulogic; +signal p1_way_data_upd13_wayD :std_ulogic; +signal congr_cl13_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl13_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu13_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd13_wayE :std_ulogic; +signal p1_way_data_upd13_wayE :std_ulogic; +signal congr_cl13_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl13_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu13_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd13_wayF :std_ulogic; +signal p1_way_data_upd13_wayF :std_ulogic; +signal congr_cl13_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl13_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu13_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd13_wayG :std_ulogic; +signal p1_way_data_upd13_wayG :std_ulogic; +signal congr_cl13_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl13_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu13_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd13_wayH :std_ulogic; +signal p1_way_data_upd13_wayH :std_ulogic; +signal p0_congr_cl14_m :std_ulogic; +signal p1_congr_cl14_m :std_ulogic; +signal p0_congr_cl14_act_d :std_ulogic; +signal p0_congr_cl14_act_q :std_ulogic; +signal p1_congr_cl14_act_d :std_ulogic; +signal p1_congr_cl14_act_q :std_ulogic; +signal congr_cl14_act :std_ulogic; +signal congr_cl14_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl14_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu14_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd14_wayA :std_ulogic; +signal p1_way_data_upd14_wayA :std_ulogic; +signal congr_cl14_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl14_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu14_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd14_wayB :std_ulogic; +signal p1_way_data_upd14_wayB :std_ulogic; +signal congr_cl14_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl14_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu14_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd14_wayC :std_ulogic; +signal p1_way_data_upd14_wayC :std_ulogic; +signal congr_cl14_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl14_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu14_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd14_wayD :std_ulogic; +signal p1_way_data_upd14_wayD :std_ulogic; +signal congr_cl14_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl14_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu14_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd14_wayE :std_ulogic; +signal p1_way_data_upd14_wayE :std_ulogic; +signal congr_cl14_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl14_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu14_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd14_wayF :std_ulogic; +signal p1_way_data_upd14_wayF :std_ulogic; +signal congr_cl14_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl14_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu14_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd14_wayG :std_ulogic; +signal p1_way_data_upd14_wayG :std_ulogic; +signal congr_cl14_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl14_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu14_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd14_wayH :std_ulogic; +signal p1_way_data_upd14_wayH :std_ulogic; +signal p0_congr_cl15_m :std_ulogic; +signal p1_congr_cl15_m :std_ulogic; +signal p0_congr_cl15_act_d :std_ulogic; +signal p0_congr_cl15_act_q :std_ulogic; +signal p1_congr_cl15_act_d :std_ulogic; +signal p1_congr_cl15_act_q :std_ulogic; +signal congr_cl15_act :std_ulogic; +signal congr_cl15_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl15_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu15_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd15_wayA :std_ulogic; +signal p1_way_data_upd15_wayA :std_ulogic; +signal congr_cl15_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl15_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu15_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd15_wayB :std_ulogic; +signal p1_way_data_upd15_wayB :std_ulogic; +signal congr_cl15_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl15_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu15_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd15_wayC :std_ulogic; +signal p1_way_data_upd15_wayC :std_ulogic; +signal congr_cl15_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl15_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu15_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd15_wayD :std_ulogic; +signal p1_way_data_upd15_wayD :std_ulogic; +signal congr_cl15_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl15_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu15_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd15_wayE :std_ulogic; +signal p1_way_data_upd15_wayE :std_ulogic; +signal congr_cl15_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl15_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu15_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd15_wayF :std_ulogic; +signal p1_way_data_upd15_wayF :std_ulogic; +signal congr_cl15_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl15_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu15_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd15_wayG :std_ulogic; +signal p1_way_data_upd15_wayG :std_ulogic; +signal congr_cl15_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl15_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu15_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd15_wayH :std_ulogic; +signal p1_way_data_upd15_wayH :std_ulogic; +signal p0_congr_cl16_m :std_ulogic; +signal p1_congr_cl16_m :std_ulogic; +signal p0_congr_cl16_act_d :std_ulogic; +signal p0_congr_cl16_act_q :std_ulogic; +signal p1_congr_cl16_act_d :std_ulogic; +signal p1_congr_cl16_act_q :std_ulogic; +signal congr_cl16_act :std_ulogic; +signal congr_cl16_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl16_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu16_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd16_wayA :std_ulogic; +signal p1_way_data_upd16_wayA :std_ulogic; +signal congr_cl16_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl16_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu16_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd16_wayB :std_ulogic; +signal p1_way_data_upd16_wayB :std_ulogic; +signal congr_cl16_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl16_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu16_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd16_wayC :std_ulogic; +signal p1_way_data_upd16_wayC :std_ulogic; +signal congr_cl16_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl16_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu16_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd16_wayD :std_ulogic; +signal p1_way_data_upd16_wayD :std_ulogic; +signal congr_cl16_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl16_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu16_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd16_wayE :std_ulogic; +signal p1_way_data_upd16_wayE :std_ulogic; +signal congr_cl16_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl16_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu16_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd16_wayF :std_ulogic; +signal p1_way_data_upd16_wayF :std_ulogic; +signal congr_cl16_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl16_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu16_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd16_wayG :std_ulogic; +signal p1_way_data_upd16_wayG :std_ulogic; +signal congr_cl16_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl16_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu16_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd16_wayH :std_ulogic; +signal p1_way_data_upd16_wayH :std_ulogic; +signal p0_congr_cl17_m :std_ulogic; +signal p1_congr_cl17_m :std_ulogic; +signal p0_congr_cl17_act_d :std_ulogic; +signal p0_congr_cl17_act_q :std_ulogic; +signal p1_congr_cl17_act_d :std_ulogic; +signal p1_congr_cl17_act_q :std_ulogic; +signal congr_cl17_act :std_ulogic; +signal congr_cl17_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl17_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu17_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd17_wayA :std_ulogic; +signal p1_way_data_upd17_wayA :std_ulogic; +signal congr_cl17_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl17_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu17_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd17_wayB :std_ulogic; +signal p1_way_data_upd17_wayB :std_ulogic; +signal congr_cl17_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl17_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu17_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd17_wayC :std_ulogic; +signal p1_way_data_upd17_wayC :std_ulogic; +signal congr_cl17_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl17_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu17_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd17_wayD :std_ulogic; +signal p1_way_data_upd17_wayD :std_ulogic; +signal congr_cl17_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl17_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu17_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd17_wayE :std_ulogic; +signal p1_way_data_upd17_wayE :std_ulogic; +signal congr_cl17_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl17_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu17_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd17_wayF :std_ulogic; +signal p1_way_data_upd17_wayF :std_ulogic; +signal congr_cl17_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl17_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu17_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd17_wayG :std_ulogic; +signal p1_way_data_upd17_wayG :std_ulogic; +signal congr_cl17_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl17_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu17_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd17_wayH :std_ulogic; +signal p1_way_data_upd17_wayH :std_ulogic; +signal p0_congr_cl18_m :std_ulogic; +signal p1_congr_cl18_m :std_ulogic; +signal p0_congr_cl18_act_d :std_ulogic; +signal p0_congr_cl18_act_q :std_ulogic; +signal p1_congr_cl18_act_d :std_ulogic; +signal p1_congr_cl18_act_q :std_ulogic; +signal congr_cl18_act :std_ulogic; +signal congr_cl18_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl18_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu18_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd18_wayA :std_ulogic; +signal p1_way_data_upd18_wayA :std_ulogic; +signal congr_cl18_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl18_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu18_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd18_wayB :std_ulogic; +signal p1_way_data_upd18_wayB :std_ulogic; +signal congr_cl18_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl18_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu18_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd18_wayC :std_ulogic; +signal p1_way_data_upd18_wayC :std_ulogic; +signal congr_cl18_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl18_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu18_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd18_wayD :std_ulogic; +signal p1_way_data_upd18_wayD :std_ulogic; +signal congr_cl18_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl18_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu18_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd18_wayE :std_ulogic; +signal p1_way_data_upd18_wayE :std_ulogic; +signal congr_cl18_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl18_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu18_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd18_wayF :std_ulogic; +signal p1_way_data_upd18_wayF :std_ulogic; +signal congr_cl18_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl18_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu18_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd18_wayG :std_ulogic; +signal p1_way_data_upd18_wayG :std_ulogic; +signal congr_cl18_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl18_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu18_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd18_wayH :std_ulogic; +signal p1_way_data_upd18_wayH :std_ulogic; +signal p0_congr_cl19_m :std_ulogic; +signal p1_congr_cl19_m :std_ulogic; +signal p0_congr_cl19_act_d :std_ulogic; +signal p0_congr_cl19_act_q :std_ulogic; +signal p1_congr_cl19_act_d :std_ulogic; +signal p1_congr_cl19_act_q :std_ulogic; +signal congr_cl19_act :std_ulogic; +signal congr_cl19_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl19_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu19_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd19_wayA :std_ulogic; +signal p1_way_data_upd19_wayA :std_ulogic; +signal congr_cl19_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl19_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu19_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd19_wayB :std_ulogic; +signal p1_way_data_upd19_wayB :std_ulogic; +signal congr_cl19_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl19_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu19_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd19_wayC :std_ulogic; +signal p1_way_data_upd19_wayC :std_ulogic; +signal congr_cl19_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl19_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu19_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd19_wayD :std_ulogic; +signal p1_way_data_upd19_wayD :std_ulogic; +signal congr_cl19_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl19_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu19_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd19_wayE :std_ulogic; +signal p1_way_data_upd19_wayE :std_ulogic; +signal congr_cl19_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl19_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu19_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd19_wayF :std_ulogic; +signal p1_way_data_upd19_wayF :std_ulogic; +signal congr_cl19_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl19_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu19_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd19_wayG :std_ulogic; +signal p1_way_data_upd19_wayG :std_ulogic; +signal congr_cl19_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl19_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu19_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd19_wayH :std_ulogic; +signal p1_way_data_upd19_wayH :std_ulogic; +signal p0_congr_cl20_m :std_ulogic; +signal p1_congr_cl20_m :std_ulogic; +signal p0_congr_cl20_act_d :std_ulogic; +signal p0_congr_cl20_act_q :std_ulogic; +signal p1_congr_cl20_act_d :std_ulogic; +signal p1_congr_cl20_act_q :std_ulogic; +signal congr_cl20_act :std_ulogic; +signal congr_cl20_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl20_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu20_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd20_wayA :std_ulogic; +signal p1_way_data_upd20_wayA :std_ulogic; +signal congr_cl20_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl20_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu20_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd20_wayB :std_ulogic; +signal p1_way_data_upd20_wayB :std_ulogic; +signal congr_cl20_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl20_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu20_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd20_wayC :std_ulogic; +signal p1_way_data_upd20_wayC :std_ulogic; +signal congr_cl20_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl20_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu20_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd20_wayD :std_ulogic; +signal p1_way_data_upd20_wayD :std_ulogic; +signal congr_cl20_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl20_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu20_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd20_wayE :std_ulogic; +signal p1_way_data_upd20_wayE :std_ulogic; +signal congr_cl20_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl20_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu20_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd20_wayF :std_ulogic; +signal p1_way_data_upd20_wayF :std_ulogic; +signal congr_cl20_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl20_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu20_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd20_wayG :std_ulogic; +signal p1_way_data_upd20_wayG :std_ulogic; +signal congr_cl20_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl20_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu20_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd20_wayH :std_ulogic; +signal p1_way_data_upd20_wayH :std_ulogic; +signal p0_congr_cl21_m :std_ulogic; +signal p1_congr_cl21_m :std_ulogic; +signal p0_congr_cl21_act_d :std_ulogic; +signal p0_congr_cl21_act_q :std_ulogic; +signal p1_congr_cl21_act_d :std_ulogic; +signal p1_congr_cl21_act_q :std_ulogic; +signal congr_cl21_act :std_ulogic; +signal congr_cl21_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl21_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu21_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd21_wayA :std_ulogic; +signal p1_way_data_upd21_wayA :std_ulogic; +signal congr_cl21_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl21_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu21_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd21_wayB :std_ulogic; +signal p1_way_data_upd21_wayB :std_ulogic; +signal congr_cl21_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl21_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu21_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd21_wayC :std_ulogic; +signal p1_way_data_upd21_wayC :std_ulogic; +signal congr_cl21_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl21_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu21_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd21_wayD :std_ulogic; +signal p1_way_data_upd21_wayD :std_ulogic; +signal congr_cl21_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl21_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu21_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd21_wayE :std_ulogic; +signal p1_way_data_upd21_wayE :std_ulogic; +signal congr_cl21_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl21_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu21_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd21_wayF :std_ulogic; +signal p1_way_data_upd21_wayF :std_ulogic; +signal congr_cl21_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl21_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu21_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd21_wayG :std_ulogic; +signal p1_way_data_upd21_wayG :std_ulogic; +signal congr_cl21_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl21_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu21_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd21_wayH :std_ulogic; +signal p1_way_data_upd21_wayH :std_ulogic; +signal p0_congr_cl22_m :std_ulogic; +signal p1_congr_cl22_m :std_ulogic; +signal p0_congr_cl22_act_d :std_ulogic; +signal p0_congr_cl22_act_q :std_ulogic; +signal p1_congr_cl22_act_d :std_ulogic; +signal p1_congr_cl22_act_q :std_ulogic; +signal congr_cl22_act :std_ulogic; +signal congr_cl22_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl22_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu22_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd22_wayA :std_ulogic; +signal p1_way_data_upd22_wayA :std_ulogic; +signal congr_cl22_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl22_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu22_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd22_wayB :std_ulogic; +signal p1_way_data_upd22_wayB :std_ulogic; +signal congr_cl22_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl22_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu22_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd22_wayC :std_ulogic; +signal p1_way_data_upd22_wayC :std_ulogic; +signal congr_cl22_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl22_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu22_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd22_wayD :std_ulogic; +signal p1_way_data_upd22_wayD :std_ulogic; +signal congr_cl22_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl22_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu22_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd22_wayE :std_ulogic; +signal p1_way_data_upd22_wayE :std_ulogic; +signal congr_cl22_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl22_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu22_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd22_wayF :std_ulogic; +signal p1_way_data_upd22_wayF :std_ulogic; +signal congr_cl22_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl22_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu22_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd22_wayG :std_ulogic; +signal p1_way_data_upd22_wayG :std_ulogic; +signal congr_cl22_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl22_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu22_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd22_wayH :std_ulogic; +signal p1_way_data_upd22_wayH :std_ulogic; +signal p0_congr_cl23_m :std_ulogic; +signal p1_congr_cl23_m :std_ulogic; +signal p0_congr_cl23_act_d :std_ulogic; +signal p0_congr_cl23_act_q :std_ulogic; +signal p1_congr_cl23_act_d :std_ulogic; +signal p1_congr_cl23_act_q :std_ulogic; +signal congr_cl23_act :std_ulogic; +signal congr_cl23_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl23_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu23_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd23_wayA :std_ulogic; +signal p1_way_data_upd23_wayA :std_ulogic; +signal congr_cl23_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl23_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu23_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd23_wayB :std_ulogic; +signal p1_way_data_upd23_wayB :std_ulogic; +signal congr_cl23_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl23_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu23_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd23_wayC :std_ulogic; +signal p1_way_data_upd23_wayC :std_ulogic; +signal congr_cl23_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl23_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu23_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd23_wayD :std_ulogic; +signal p1_way_data_upd23_wayD :std_ulogic; +signal congr_cl23_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl23_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu23_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd23_wayE :std_ulogic; +signal p1_way_data_upd23_wayE :std_ulogic; +signal congr_cl23_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl23_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu23_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd23_wayF :std_ulogic; +signal p1_way_data_upd23_wayF :std_ulogic; +signal congr_cl23_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl23_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu23_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd23_wayG :std_ulogic; +signal p1_way_data_upd23_wayG :std_ulogic; +signal congr_cl23_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl23_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu23_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd23_wayH :std_ulogic; +signal p1_way_data_upd23_wayH :std_ulogic; +signal p0_congr_cl24_m :std_ulogic; +signal p1_congr_cl24_m :std_ulogic; +signal p0_congr_cl24_act_d :std_ulogic; +signal p0_congr_cl24_act_q :std_ulogic; +signal p1_congr_cl24_act_d :std_ulogic; +signal p1_congr_cl24_act_q :std_ulogic; +signal congr_cl24_act :std_ulogic; +signal congr_cl24_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl24_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu24_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd24_wayA :std_ulogic; +signal p1_way_data_upd24_wayA :std_ulogic; +signal congr_cl24_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl24_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu24_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd24_wayB :std_ulogic; +signal p1_way_data_upd24_wayB :std_ulogic; +signal congr_cl24_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl24_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu24_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd24_wayC :std_ulogic; +signal p1_way_data_upd24_wayC :std_ulogic; +signal congr_cl24_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl24_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu24_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd24_wayD :std_ulogic; +signal p1_way_data_upd24_wayD :std_ulogic; +signal congr_cl24_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl24_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu24_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd24_wayE :std_ulogic; +signal p1_way_data_upd24_wayE :std_ulogic; +signal congr_cl24_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl24_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu24_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd24_wayF :std_ulogic; +signal p1_way_data_upd24_wayF :std_ulogic; +signal congr_cl24_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl24_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu24_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd24_wayG :std_ulogic; +signal p1_way_data_upd24_wayG :std_ulogic; +signal congr_cl24_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl24_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu24_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd24_wayH :std_ulogic; +signal p1_way_data_upd24_wayH :std_ulogic; +signal p0_congr_cl25_m :std_ulogic; +signal p1_congr_cl25_m :std_ulogic; +signal p0_congr_cl25_act_d :std_ulogic; +signal p0_congr_cl25_act_q :std_ulogic; +signal p1_congr_cl25_act_d :std_ulogic; +signal p1_congr_cl25_act_q :std_ulogic; +signal congr_cl25_act :std_ulogic; +signal congr_cl25_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl25_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu25_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd25_wayA :std_ulogic; +signal p1_way_data_upd25_wayA :std_ulogic; +signal congr_cl25_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl25_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu25_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd25_wayB :std_ulogic; +signal p1_way_data_upd25_wayB :std_ulogic; +signal congr_cl25_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl25_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu25_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd25_wayC :std_ulogic; +signal p1_way_data_upd25_wayC :std_ulogic; +signal congr_cl25_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl25_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu25_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd25_wayD :std_ulogic; +signal p1_way_data_upd25_wayD :std_ulogic; +signal congr_cl25_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl25_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu25_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd25_wayE :std_ulogic; +signal p1_way_data_upd25_wayE :std_ulogic; +signal congr_cl25_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl25_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu25_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd25_wayF :std_ulogic; +signal p1_way_data_upd25_wayF :std_ulogic; +signal congr_cl25_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl25_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu25_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd25_wayG :std_ulogic; +signal p1_way_data_upd25_wayG :std_ulogic; +signal congr_cl25_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl25_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu25_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd25_wayH :std_ulogic; +signal p1_way_data_upd25_wayH :std_ulogic; +signal p0_congr_cl26_m :std_ulogic; +signal p1_congr_cl26_m :std_ulogic; +signal p0_congr_cl26_act_d :std_ulogic; +signal p0_congr_cl26_act_q :std_ulogic; +signal p1_congr_cl26_act_d :std_ulogic; +signal p1_congr_cl26_act_q :std_ulogic; +signal congr_cl26_act :std_ulogic; +signal congr_cl26_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl26_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu26_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd26_wayA :std_ulogic; +signal p1_way_data_upd26_wayA :std_ulogic; +signal congr_cl26_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl26_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu26_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd26_wayB :std_ulogic; +signal p1_way_data_upd26_wayB :std_ulogic; +signal congr_cl26_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl26_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu26_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd26_wayC :std_ulogic; +signal p1_way_data_upd26_wayC :std_ulogic; +signal congr_cl26_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl26_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu26_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd26_wayD :std_ulogic; +signal p1_way_data_upd26_wayD :std_ulogic; +signal congr_cl26_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl26_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu26_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd26_wayE :std_ulogic; +signal p1_way_data_upd26_wayE :std_ulogic; +signal congr_cl26_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl26_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu26_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd26_wayF :std_ulogic; +signal p1_way_data_upd26_wayF :std_ulogic; +signal congr_cl26_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl26_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu26_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd26_wayG :std_ulogic; +signal p1_way_data_upd26_wayG :std_ulogic; +signal congr_cl26_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl26_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu26_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd26_wayH :std_ulogic; +signal p1_way_data_upd26_wayH :std_ulogic; +signal p0_congr_cl27_m :std_ulogic; +signal p1_congr_cl27_m :std_ulogic; +signal p0_congr_cl27_act_d :std_ulogic; +signal p0_congr_cl27_act_q :std_ulogic; +signal p1_congr_cl27_act_d :std_ulogic; +signal p1_congr_cl27_act_q :std_ulogic; +signal congr_cl27_act :std_ulogic; +signal congr_cl27_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl27_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu27_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd27_wayA :std_ulogic; +signal p1_way_data_upd27_wayA :std_ulogic; +signal congr_cl27_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl27_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu27_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd27_wayB :std_ulogic; +signal p1_way_data_upd27_wayB :std_ulogic; +signal congr_cl27_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl27_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu27_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd27_wayC :std_ulogic; +signal p1_way_data_upd27_wayC :std_ulogic; +signal congr_cl27_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl27_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu27_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd27_wayD :std_ulogic; +signal p1_way_data_upd27_wayD :std_ulogic; +signal congr_cl27_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl27_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu27_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd27_wayE :std_ulogic; +signal p1_way_data_upd27_wayE :std_ulogic; +signal congr_cl27_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl27_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu27_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd27_wayF :std_ulogic; +signal p1_way_data_upd27_wayF :std_ulogic; +signal congr_cl27_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl27_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu27_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd27_wayG :std_ulogic; +signal p1_way_data_upd27_wayG :std_ulogic; +signal congr_cl27_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl27_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu27_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd27_wayH :std_ulogic; +signal p1_way_data_upd27_wayH :std_ulogic; +signal p0_congr_cl28_m :std_ulogic; +signal p1_congr_cl28_m :std_ulogic; +signal p0_congr_cl28_act_d :std_ulogic; +signal p0_congr_cl28_act_q :std_ulogic; +signal p1_congr_cl28_act_d :std_ulogic; +signal p1_congr_cl28_act_q :std_ulogic; +signal congr_cl28_act :std_ulogic; +signal congr_cl28_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl28_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu28_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd28_wayA :std_ulogic; +signal p1_way_data_upd28_wayA :std_ulogic; +signal congr_cl28_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl28_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu28_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd28_wayB :std_ulogic; +signal p1_way_data_upd28_wayB :std_ulogic; +signal congr_cl28_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl28_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu28_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd28_wayC :std_ulogic; +signal p1_way_data_upd28_wayC :std_ulogic; +signal congr_cl28_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl28_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu28_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd28_wayD :std_ulogic; +signal p1_way_data_upd28_wayD :std_ulogic; +signal congr_cl28_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl28_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu28_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd28_wayE :std_ulogic; +signal p1_way_data_upd28_wayE :std_ulogic; +signal congr_cl28_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl28_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu28_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd28_wayF :std_ulogic; +signal p1_way_data_upd28_wayF :std_ulogic; +signal congr_cl28_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl28_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu28_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd28_wayG :std_ulogic; +signal p1_way_data_upd28_wayG :std_ulogic; +signal congr_cl28_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl28_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu28_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd28_wayH :std_ulogic; +signal p1_way_data_upd28_wayH :std_ulogic; +signal p0_congr_cl29_m :std_ulogic; +signal p1_congr_cl29_m :std_ulogic; +signal p0_congr_cl29_act_d :std_ulogic; +signal p0_congr_cl29_act_q :std_ulogic; +signal p1_congr_cl29_act_d :std_ulogic; +signal p1_congr_cl29_act_q :std_ulogic; +signal congr_cl29_act :std_ulogic; +signal congr_cl29_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl29_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu29_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd29_wayA :std_ulogic; +signal p1_way_data_upd29_wayA :std_ulogic; +signal congr_cl29_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl29_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu29_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd29_wayB :std_ulogic; +signal p1_way_data_upd29_wayB :std_ulogic; +signal congr_cl29_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl29_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu29_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd29_wayC :std_ulogic; +signal p1_way_data_upd29_wayC :std_ulogic; +signal congr_cl29_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl29_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu29_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd29_wayD :std_ulogic; +signal p1_way_data_upd29_wayD :std_ulogic; +signal congr_cl29_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl29_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu29_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd29_wayE :std_ulogic; +signal p1_way_data_upd29_wayE :std_ulogic; +signal congr_cl29_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl29_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu29_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd29_wayF :std_ulogic; +signal p1_way_data_upd29_wayF :std_ulogic; +signal congr_cl29_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl29_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu29_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd29_wayG :std_ulogic; +signal p1_way_data_upd29_wayG :std_ulogic; +signal congr_cl29_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl29_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu29_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd29_wayH :std_ulogic; +signal p1_way_data_upd29_wayH :std_ulogic; +signal p0_congr_cl30_m :std_ulogic; +signal p1_congr_cl30_m :std_ulogic; +signal p0_congr_cl30_act_d :std_ulogic; +signal p0_congr_cl30_act_q :std_ulogic; +signal p1_congr_cl30_act_d :std_ulogic; +signal p1_congr_cl30_act_q :std_ulogic; +signal congr_cl30_act :std_ulogic; +signal congr_cl30_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl30_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu30_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd30_wayA :std_ulogic; +signal p1_way_data_upd30_wayA :std_ulogic; +signal congr_cl30_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl30_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu30_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd30_wayB :std_ulogic; +signal p1_way_data_upd30_wayB :std_ulogic; +signal congr_cl30_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl30_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu30_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd30_wayC :std_ulogic; +signal p1_way_data_upd30_wayC :std_ulogic; +signal congr_cl30_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl30_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu30_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd30_wayD :std_ulogic; +signal p1_way_data_upd30_wayD :std_ulogic; +signal congr_cl30_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl30_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu30_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd30_wayE :std_ulogic; +signal p1_way_data_upd30_wayE :std_ulogic; +signal congr_cl30_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl30_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu30_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd30_wayF :std_ulogic; +signal p1_way_data_upd30_wayF :std_ulogic; +signal congr_cl30_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl30_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu30_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd30_wayG :std_ulogic; +signal p1_way_data_upd30_wayG :std_ulogic; +signal congr_cl30_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl30_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu30_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd30_wayH :std_ulogic; +signal p1_way_data_upd30_wayH :std_ulogic; +signal p0_congr_cl31_m :std_ulogic; +signal p1_congr_cl31_m :std_ulogic; +signal p0_congr_cl31_act_d :std_ulogic; +signal p0_congr_cl31_act_q :std_ulogic; +signal p1_congr_cl31_act_d :std_ulogic; +signal p1_congr_cl31_act_q :std_ulogic; +signal congr_cl31_act :std_ulogic; +signal congr_cl31_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl31_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu31_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd31_wayA :std_ulogic; +signal p1_way_data_upd31_wayA :std_ulogic; +signal congr_cl31_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl31_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu31_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd31_wayB :std_ulogic; +signal p1_way_data_upd31_wayB :std_ulogic; +signal congr_cl31_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl31_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu31_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd31_wayC :std_ulogic; +signal p1_way_data_upd31_wayC :std_ulogic; +signal congr_cl31_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl31_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu31_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd31_wayD :std_ulogic; +signal p1_way_data_upd31_wayD :std_ulogic; +signal congr_cl31_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl31_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu31_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd31_wayE :std_ulogic; +signal p1_way_data_upd31_wayE :std_ulogic; +signal congr_cl31_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl31_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu31_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd31_wayF :std_ulogic; +signal p1_way_data_upd31_wayF :std_ulogic; +signal congr_cl31_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl31_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu31_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd31_wayG :std_ulogic; +signal p1_way_data_upd31_wayG :std_ulogic; +signal congr_cl31_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl31_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu31_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd31_wayH :std_ulogic; +signal p1_way_data_upd31_wayH :std_ulogic; +signal tagA_hit :std_ulogic; +signal tagA_hit_b :std_ulogic; +signal arr_wayA_val :std_ulogic_vector(0 to 5); +signal p0_arr_wayA_rd :std_ulogic_vector(0 to 5); +signal flush_wayA_d :std_ulogic_vector(0 to 5); +signal flush_wayA_q :std_ulogic_vector(0 to 5); +signal rel_wayA_clr :std_ulogic; +signal rel_wayA_set :std_ulogic; +signal rel_par_wA_clr :std_ulogic; +signal wayA_val :std_ulogic_vector(0 to 5); +signal wayA_val_b_q :std_ulogic_vector(0 to 5); +signal wayA_val_b1 :std_ulogic; +signal congr_cl_ex2_wayA_byp :std_ulogic_vector(1 to 7); +signal congr_cl_ex2_wayA_sel :std_ulogic_vector(2 to 7); +signal rel_arr_wayA_val :std_ulogic_vector(0 to 5); +signal p1_arr_wayA_rd :std_ulogic_vector(0 to 5); +signal rel_wayA_val_b_q :std_ulogic_vector(0 to 5); +signal rel_wayA_val :std_ulogic_vector(0 to 5); +signal congr_cl_rel13_wayA_byp :std_ulogic_vector(1 to 7); +signal congr_cl_rel13_wayA_sel :std_ulogic_vector(2 to 7); +signal reload_wayA_d :std_ulogic_vector(0 to 5); +signal reload_wayA_q :std_ulogic_vector(0 to 5); +signal reload_wayA_data_d :std_ulogic_vector(0 to 5); +signal reload_wayA_data_q :std_ulogic_vector(0 to 5); +signal reload_wayA_data2_d :std_ulogic_vector(0 to 5); +signal reload_wayA_data2_q :std_ulogic_vector(0 to 5); +signal reload_wayA_upd_d :std_ulogic; +signal reload_wayA_upd_q :std_ulogic; +signal reload_wayA_clr :std_ulogic; +signal reload_wayA_upd2_d :std_ulogic; +signal reload_wayA_upd2_q :std_ulogic; +signal reload_wayA_upd3_d :std_ulogic; +signal reload_wayA_upd3_q :std_ulogic; +signal reload_wayA :std_ulogic_vector(0 to 5); +signal binv_wayA_upd_d :std_ulogic; +signal binv_wayA_upd_q :std_ulogic; +signal binv_wayA_upd1 :std_ulogic; +signal binv_wayA_upd2_d :std_ulogic; +signal binv_wayA_upd2_q :std_ulogic; +signal binv_wayA_upd3_d :std_ulogic; +signal binv_wayA_upd3_q :std_ulogic; +signal flush_wayA_data1 :std_ulogic_vector(0 to 5); +signal flush_wayA_data_d :std_ulogic_vector(0 to 5); +signal flush_wayA_data_q :std_ulogic_vector(0 to 5); +signal flush_wayA_data2_d :std_ulogic_vector(0 to 5); +signal flush_wayA_data2_q :std_ulogic_vector(0 to 5); +signal xu_op_hit_wayA_b :std_ulogic; +signal xu_op_hit_wayA :std_ulogic; +signal xu_op_hit_wayA_dly_b :std_ulogic; +signal clr_val_wayA :std_ulogic; +signal upd_lck_wayA :std_ulogic_vector(0 to 1); +signal inval_clr_lck_wA_d :std_ulogic; +signal inval_clr_lck_wA_q :std_ulogic; +signal perr_way_det_wayA :std_ulogic; +signal perr_wayA_watch_lost :std_ulogic_vector(0 to 3); +signal wayA_watch_value :std_ulogic; +signal ex4_lost_wayA :std_ulogic_vector(0 to 3); +signal ex3_xuop_lost_watch_wayA :std_ulogic; +signal ex3_xuop_wayA_upd :std_ulogic; +signal ex4_xuop_wayA_upd_d :std_ulogic; +signal ex4_xuop_wayA_upd_q :std_ulogic; +signal ex4_wayA_val_d :std_ulogic_vector(0 to 5); +signal ex4_wayA_val_q :std_ulogic_vector(0 to 5); +signal rel_wayA_val_stg_d :std_ulogic_vector(0 to 5); +signal rel_wayA_val_stg_q :std_ulogic_vector(0 to 5); +signal ex5_xuop_wayA_upd_d :std_ulogic; +signal ex5_xuop_wayA_upd_q :std_ulogic; +signal congr_cl_ex3_upd_wayA :std_ulogic; +signal congr_cl_ex4_upd_wayA :std_ulogic; +signal congr_cl_ex5_upd_wayA :std_ulogic; +signal congr_cl_m_upd_wayA_d :std_ulogic; +signal congr_cl_m_upd_wayA_q :std_ulogic; +signal ex3_cClass_wayA_hit :std_ulogic; +signal wayA_later_stg_pri :std_ulogic_vector(0 to 5); +signal wayA_early_stg_pri :std_ulogic_vector(0 to 5); +signal wayA_stg_val :std_ulogic_vector(0 to 5); +signal wayA_stg_val_b :std_ulogic_vector(0 to 5); +signal rel_wayA_later_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayA_early_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayA_stg_val :std_ulogic_vector(0 to 5); +signal rel_wayA_stg_val_b :std_ulogic_vector(0 to 5); +signal wayA_early_sel :std_ulogic; +signal wayA_late_sel :std_ulogic; +signal rel_wayA_early_sel :std_ulogic; +signal rel_wayA_late_sel :std_ulogic; +signal ex3_wayA_hit :std_ulogic; +signal rel_lost_watch_wayA_evict :std_ulogic_vector(0 to 3); +signal ex3_wayA_fxubyp_val_d :std_ulogic; +signal ex3_wayA_fxubyp_val_q :std_ulogic; +signal ex4_wayA_fxubyp_val_d :std_ulogic; +signal ex4_wayA_fxubyp_val_q :std_ulogic; +signal ex3_wayA_relbyp_val_d :std_ulogic; +signal ex3_wayA_relbyp_val_q :std_ulogic; +signal ex4_wayA_relbyp_val_d :std_ulogic; +signal ex4_wayA_relbyp_val_q :std_ulogic; +signal ex4_wayA_byp_sel :std_ulogic_vector(0 to 1); +signal rel24_wayA_fxubyp_val_d :std_ulogic; +signal rel24_wayA_fxubyp_val_q :std_ulogic; +signal rel24_wayA_relbyp_val_d :std_ulogic; +signal rel24_wayA_relbyp_val_q :std_ulogic; +signal rel24_wayA_byp_sel :std_ulogic_vector(0 to 1); +signal tagB_hit :std_ulogic; +signal tagB_hit_b :std_ulogic; +signal arr_wayB_val :std_ulogic_vector(0 to 5); +signal p0_arr_wayB_rd :std_ulogic_vector(0 to 5); +signal flush_wayB_d :std_ulogic_vector(0 to 5); +signal flush_wayB_q :std_ulogic_vector(0 to 5); +signal rel_wayB_clr :std_ulogic; +signal rel_wayB_set :std_ulogic; +signal rel_par_wB_clr :std_ulogic; +signal wayB_val :std_ulogic_vector(0 to 5); +signal wayB_val_b_q :std_ulogic_vector(0 to 5); +signal wayB_val_b1 :std_ulogic; +signal congr_cl_ex2_wayB_byp :std_ulogic_vector(1 to 7); +signal congr_cl_ex2_wayB_sel :std_ulogic_vector(2 to 7); +signal rel_arr_wayB_val :std_ulogic_vector(0 to 5); +signal p1_arr_wayB_rd :std_ulogic_vector(0 to 5); +signal rel_wayB_val_b_q :std_ulogic_vector(0 to 5); +signal rel_wayB_val :std_ulogic_vector(0 to 5); +signal congr_cl_rel13_wayB_byp :std_ulogic_vector(1 to 7); +signal congr_cl_rel13_wayB_sel :std_ulogic_vector(2 to 7); +signal reload_wayB_d :std_ulogic_vector(0 to 5); +signal reload_wayB_q :std_ulogic_vector(0 to 5); +signal reload_wayB_data_d :std_ulogic_vector(0 to 5); +signal reload_wayB_data_q :std_ulogic_vector(0 to 5); +signal reload_wayB_data2_d :std_ulogic_vector(0 to 5); +signal reload_wayB_data2_q :std_ulogic_vector(0 to 5); +signal reload_wayB_upd_d :std_ulogic; +signal reload_wayB_upd_q :std_ulogic; +signal reload_wayB_clr :std_ulogic; +signal reload_wayB_upd2_d :std_ulogic; +signal reload_wayB_upd2_q :std_ulogic; +signal reload_wayB_upd3_d :std_ulogic; +signal reload_wayB_upd3_q :std_ulogic; +signal reload_wayB :std_ulogic_vector(0 to 5); +signal binv_wayB_upd_d :std_ulogic; +signal binv_wayB_upd_q :std_ulogic; +signal binv_wayB_upd1 :std_ulogic; +signal binv_wayB_upd2_d :std_ulogic; +signal binv_wayB_upd2_q :std_ulogic; +signal binv_wayB_upd3_d :std_ulogic; +signal binv_wayB_upd3_q :std_ulogic; +signal flush_wayB_data1 :std_ulogic_vector(0 to 5); +signal flush_wayB_data_d :std_ulogic_vector(0 to 5); +signal flush_wayB_data_q :std_ulogic_vector(0 to 5); +signal flush_wayB_data2_d :std_ulogic_vector(0 to 5); +signal flush_wayB_data2_q :std_ulogic_vector(0 to 5); +signal xu_op_hit_wayB_b :std_ulogic; +signal xu_op_hit_wayB :std_ulogic; +signal xu_op_hit_wayB_dly_b :std_ulogic; +signal clr_val_wayB :std_ulogic; +signal upd_lck_wayB :std_ulogic_vector(0 to 1); +signal inval_clr_lck_wB_d :std_ulogic; +signal inval_clr_lck_wB_q :std_ulogic; +signal perr_way_det_wayB :std_ulogic; +signal perr_wayB_watch_lost :std_ulogic_vector(0 to 3); +signal wayB_watch_value :std_ulogic; +signal ex4_lost_wayB :std_ulogic_vector(0 to 3); +signal ex3_xuop_lost_watch_wayB :std_ulogic; +signal ex3_xuop_wayB_upd :std_ulogic; +signal ex4_xuop_wayB_upd_d :std_ulogic; +signal ex4_xuop_wayB_upd_q :std_ulogic; +signal ex4_wayB_val_d :std_ulogic_vector(0 to 5); +signal ex4_wayB_val_q :std_ulogic_vector(0 to 5); +signal rel_wayB_val_stg_d :std_ulogic_vector(0 to 5); +signal rel_wayB_val_stg_q :std_ulogic_vector(0 to 5); +signal ex5_xuop_wayB_upd_d :std_ulogic; +signal ex5_xuop_wayB_upd_q :std_ulogic; +signal congr_cl_ex3_upd_wayB :std_ulogic; +signal congr_cl_ex4_upd_wayB :std_ulogic; +signal congr_cl_ex5_upd_wayB :std_ulogic; +signal congr_cl_m_upd_wayB_d :std_ulogic; +signal congr_cl_m_upd_wayB_q :std_ulogic; +signal ex3_cClass_wayB_hit :std_ulogic; +signal wayB_later_stg_pri :std_ulogic_vector(0 to 5); +signal wayB_early_stg_pri :std_ulogic_vector(0 to 5); +signal wayB_stg_val :std_ulogic_vector(0 to 5); +signal wayB_stg_val_b :std_ulogic_vector(0 to 5); +signal rel_wayB_later_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayB_early_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayB_stg_val :std_ulogic_vector(0 to 5); +signal rel_wayB_stg_val_b :std_ulogic_vector(0 to 5); +signal wayB_early_sel :std_ulogic; +signal wayB_late_sel :std_ulogic; +signal rel_wayB_early_sel :std_ulogic; +signal rel_wayB_late_sel :std_ulogic; +signal ex3_wayB_hit :std_ulogic; +signal rel_lost_watch_wayB_evict :std_ulogic_vector(0 to 3); +signal ex3_wayB_fxubyp_val_d :std_ulogic; +signal ex3_wayB_fxubyp_val_q :std_ulogic; +signal ex4_wayB_fxubyp_val_d :std_ulogic; +signal ex4_wayB_fxubyp_val_q :std_ulogic; +signal ex3_wayB_relbyp_val_d :std_ulogic; +signal ex3_wayB_relbyp_val_q :std_ulogic; +signal ex4_wayB_relbyp_val_d :std_ulogic; +signal ex4_wayB_relbyp_val_q :std_ulogic; +signal ex4_wayB_byp_sel :std_ulogic_vector(0 to 1); +signal rel24_wayB_fxubyp_val_d :std_ulogic; +signal rel24_wayB_fxubyp_val_q :std_ulogic; +signal rel24_wayB_relbyp_val_d :std_ulogic; +signal rel24_wayB_relbyp_val_q :std_ulogic; +signal rel24_wayB_byp_sel :std_ulogic_vector(0 to 1); +signal tagC_hit :std_ulogic; +signal tagC_hit_b :std_ulogic; +signal arr_wayC_val :std_ulogic_vector(0 to 5); +signal p0_arr_wayC_rd :std_ulogic_vector(0 to 5); +signal flush_wayC_d :std_ulogic_vector(0 to 5); +signal flush_wayC_q :std_ulogic_vector(0 to 5); +signal rel_wayC_clr :std_ulogic; +signal rel_wayC_set :std_ulogic; +signal rel_par_wC_clr :std_ulogic; +signal wayC_val :std_ulogic_vector(0 to 5); +signal wayC_val_b_q :std_ulogic_vector(0 to 5); +signal wayC_val_b1 :std_ulogic; +signal congr_cl_ex2_wayC_byp :std_ulogic_vector(1 to 7); +signal congr_cl_ex2_wayC_sel :std_ulogic_vector(2 to 7); +signal rel_arr_wayC_val :std_ulogic_vector(0 to 5); +signal p1_arr_wayC_rd :std_ulogic_vector(0 to 5); +signal rel_wayC_val_b_q :std_ulogic_vector(0 to 5); +signal rel_wayC_val :std_ulogic_vector(0 to 5); +signal congr_cl_rel13_wayC_byp :std_ulogic_vector(1 to 7); +signal congr_cl_rel13_wayC_sel :std_ulogic_vector(2 to 7); +signal reload_wayC_d :std_ulogic_vector(0 to 5); +signal reload_wayC_q :std_ulogic_vector(0 to 5); +signal reload_wayC_data_d :std_ulogic_vector(0 to 5); +signal reload_wayC_data_q :std_ulogic_vector(0 to 5); +signal reload_wayC_data2_d :std_ulogic_vector(0 to 5); +signal reload_wayC_data2_q :std_ulogic_vector(0 to 5); +signal reload_wayC_upd_d :std_ulogic; +signal reload_wayC_upd_q :std_ulogic; +signal reload_wayC_clr :std_ulogic; +signal reload_wayC_upd2_d :std_ulogic; +signal reload_wayC_upd2_q :std_ulogic; +signal reload_wayC_upd3_d :std_ulogic; +signal reload_wayC_upd3_q :std_ulogic; +signal reload_wayC :std_ulogic_vector(0 to 5); +signal binv_wayC_upd_d :std_ulogic; +signal binv_wayC_upd_q :std_ulogic; +signal binv_wayC_upd1 :std_ulogic; +signal binv_wayC_upd2_d :std_ulogic; +signal binv_wayC_upd2_q :std_ulogic; +signal binv_wayC_upd3_d :std_ulogic; +signal binv_wayC_upd3_q :std_ulogic; +signal flush_wayC_data1 :std_ulogic_vector(0 to 5); +signal flush_wayC_data_d :std_ulogic_vector(0 to 5); +signal flush_wayC_data_q :std_ulogic_vector(0 to 5); +signal flush_wayC_data2_d :std_ulogic_vector(0 to 5); +signal flush_wayC_data2_q :std_ulogic_vector(0 to 5); +signal xu_op_hit_wayC_b :std_ulogic; +signal xu_op_hit_wayC :std_ulogic; +signal xu_op_hit_wayC_dly_b :std_ulogic; +signal clr_val_wayC :std_ulogic; +signal upd_lck_wayC :std_ulogic_vector(0 to 1); +signal inval_clr_lck_wC_d :std_ulogic; +signal inval_clr_lck_wC_q :std_ulogic; +signal perr_way_det_wayC :std_ulogic; +signal perr_wayC_watch_lost :std_ulogic_vector(0 to 3); +signal wayC_watch_value :std_ulogic; +signal ex4_lost_wayC :std_ulogic_vector(0 to 3); +signal ex3_xuop_lost_watch_wayC :std_ulogic; +signal ex3_xuop_wayC_upd :std_ulogic; +signal ex4_xuop_wayC_upd_d :std_ulogic; +signal ex4_xuop_wayC_upd_q :std_ulogic; +signal ex4_wayC_val_d :std_ulogic_vector(0 to 5); +signal ex4_wayC_val_q :std_ulogic_vector(0 to 5); +signal rel_wayC_val_stg_d :std_ulogic_vector(0 to 5); +signal rel_wayC_val_stg_q :std_ulogic_vector(0 to 5); +signal ex5_xuop_wayC_upd_d :std_ulogic; +signal ex5_xuop_wayC_upd_q :std_ulogic; +signal congr_cl_ex3_upd_wayC :std_ulogic; +signal congr_cl_ex4_upd_wayC :std_ulogic; +signal congr_cl_ex5_upd_wayC :std_ulogic; +signal congr_cl_m_upd_wayC_d :std_ulogic; +signal congr_cl_m_upd_wayC_q :std_ulogic; +signal ex3_cClass_wayC_hit :std_ulogic; +signal wayC_later_stg_pri :std_ulogic_vector(0 to 5); +signal wayC_early_stg_pri :std_ulogic_vector(0 to 5); +signal wayC_stg_val :std_ulogic_vector(0 to 5); +signal wayC_stg_val_b :std_ulogic_vector(0 to 5); +signal rel_wayC_later_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayC_early_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayC_stg_val :std_ulogic_vector(0 to 5); +signal rel_wayC_stg_val_b :std_ulogic_vector(0 to 5); +signal wayC_early_sel :std_ulogic; +signal wayC_late_sel :std_ulogic; +signal rel_wayC_early_sel :std_ulogic; +signal rel_wayC_late_sel :std_ulogic; +signal ex3_wayC_hit :std_ulogic; +signal rel_lost_watch_wayC_evict :std_ulogic_vector(0 to 3); +signal ex3_wayC_fxubyp_val_d :std_ulogic; +signal ex3_wayC_fxubyp_val_q :std_ulogic; +signal ex4_wayC_fxubyp_val_d :std_ulogic; +signal ex4_wayC_fxubyp_val_q :std_ulogic; +signal ex3_wayC_relbyp_val_d :std_ulogic; +signal ex3_wayC_relbyp_val_q :std_ulogic; +signal ex4_wayC_relbyp_val_d :std_ulogic; +signal ex4_wayC_relbyp_val_q :std_ulogic; +signal ex4_wayC_byp_sel :std_ulogic_vector(0 to 1); +signal rel24_wayC_fxubyp_val_d :std_ulogic; +signal rel24_wayC_fxubyp_val_q :std_ulogic; +signal rel24_wayC_relbyp_val_d :std_ulogic; +signal rel24_wayC_relbyp_val_q :std_ulogic; +signal rel24_wayC_byp_sel :std_ulogic_vector(0 to 1); +signal tagD_hit :std_ulogic; +signal tagD_hit_b :std_ulogic; +signal arr_wayD_val :std_ulogic_vector(0 to 5); +signal p0_arr_wayD_rd :std_ulogic_vector(0 to 5); +signal flush_wayD_d :std_ulogic_vector(0 to 5); +signal flush_wayD_q :std_ulogic_vector(0 to 5); +signal rel_wayD_clr :std_ulogic; +signal rel_wayD_set :std_ulogic; +signal rel_par_wD_clr :std_ulogic; +signal wayD_val :std_ulogic_vector(0 to 5); +signal wayD_val_b_q :std_ulogic_vector(0 to 5); +signal wayD_val_b1 :std_ulogic; +signal congr_cl_ex2_wayD_byp :std_ulogic_vector(1 to 7); +signal congr_cl_ex2_wayD_sel :std_ulogic_vector(2 to 7); +signal rel_arr_wayD_val :std_ulogic_vector(0 to 5); +signal p1_arr_wayD_rd :std_ulogic_vector(0 to 5); +signal rel_wayD_val_b_q :std_ulogic_vector(0 to 5); +signal rel_wayD_val :std_ulogic_vector(0 to 5); +signal congr_cl_rel13_wayD_byp :std_ulogic_vector(1 to 7); +signal congr_cl_rel13_wayD_sel :std_ulogic_vector(2 to 7); +signal reload_wayD_d :std_ulogic_vector(0 to 5); +signal reload_wayD_q :std_ulogic_vector(0 to 5); +signal reload_wayD_data_d :std_ulogic_vector(0 to 5); +signal reload_wayD_data_q :std_ulogic_vector(0 to 5); +signal reload_wayD_data2_d :std_ulogic_vector(0 to 5); +signal reload_wayD_data2_q :std_ulogic_vector(0 to 5); +signal reload_wayD_upd_d :std_ulogic; +signal reload_wayD_upd_q :std_ulogic; +signal reload_wayD_clr :std_ulogic; +signal reload_wayD_upd2_d :std_ulogic; +signal reload_wayD_upd2_q :std_ulogic; +signal reload_wayD_upd3_d :std_ulogic; +signal reload_wayD_upd3_q :std_ulogic; +signal reload_wayD :std_ulogic_vector(0 to 5); +signal binv_wayD_upd_d :std_ulogic; +signal binv_wayD_upd_q :std_ulogic; +signal binv_wayD_upd1 :std_ulogic; +signal binv_wayD_upd2_d :std_ulogic; +signal binv_wayD_upd2_q :std_ulogic; +signal binv_wayD_upd3_d :std_ulogic; +signal binv_wayD_upd3_q :std_ulogic; +signal flush_wayD_data1 :std_ulogic_vector(0 to 5); +signal flush_wayD_data_d :std_ulogic_vector(0 to 5); +signal flush_wayD_data_q :std_ulogic_vector(0 to 5); +signal flush_wayD_data2_d :std_ulogic_vector(0 to 5); +signal flush_wayD_data2_q :std_ulogic_vector(0 to 5); +signal xu_op_hit_wayD_b :std_ulogic; +signal xu_op_hit_wayD :std_ulogic; +signal xu_op_hit_wayD_dly_b :std_ulogic; +signal clr_val_wayD :std_ulogic; +signal upd_lck_wayD :std_ulogic_vector(0 to 1); +signal inval_clr_lck_wD_d :std_ulogic; +signal inval_clr_lck_wD_q :std_ulogic; +signal perr_way_det_wayD :std_ulogic; +signal perr_wayD_watch_lost :std_ulogic_vector(0 to 3); +signal wayD_watch_value :std_ulogic; +signal ex4_lost_wayD :std_ulogic_vector(0 to 3); +signal ex3_xuop_lost_watch_wayD :std_ulogic; +signal ex3_xuop_wayD_upd :std_ulogic; +signal ex4_xuop_wayD_upd_d :std_ulogic; +signal ex4_xuop_wayD_upd_q :std_ulogic; +signal ex4_wayD_val_d :std_ulogic_vector(0 to 5); +signal ex4_wayD_val_q :std_ulogic_vector(0 to 5); +signal rel_wayD_val_stg_d :std_ulogic_vector(0 to 5); +signal rel_wayD_val_stg_q :std_ulogic_vector(0 to 5); +signal ex5_xuop_wayD_upd_d :std_ulogic; +signal ex5_xuop_wayD_upd_q :std_ulogic; +signal congr_cl_ex3_upd_wayD :std_ulogic; +signal congr_cl_ex4_upd_wayD :std_ulogic; +signal congr_cl_ex5_upd_wayD :std_ulogic; +signal congr_cl_m_upd_wayD_d :std_ulogic; +signal congr_cl_m_upd_wayD_q :std_ulogic; +signal ex3_cClass_wayD_hit :std_ulogic; +signal wayD_later_stg_pri :std_ulogic_vector(0 to 5); +signal wayD_early_stg_pri :std_ulogic_vector(0 to 5); +signal wayD_stg_val :std_ulogic_vector(0 to 5); +signal wayD_stg_val_b :std_ulogic_vector(0 to 5); +signal rel_wayD_later_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayD_early_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayD_stg_val :std_ulogic_vector(0 to 5); +signal rel_wayD_stg_val_b :std_ulogic_vector(0 to 5); +signal wayD_early_sel :std_ulogic; +signal wayD_late_sel :std_ulogic; +signal rel_wayD_early_sel :std_ulogic; +signal rel_wayD_late_sel :std_ulogic; +signal ex3_wayD_hit :std_ulogic; +signal rel_lost_watch_wayD_evict :std_ulogic_vector(0 to 3); +signal ex3_wayD_fxubyp_val_d :std_ulogic; +signal ex3_wayD_fxubyp_val_q :std_ulogic; +signal ex4_wayD_fxubyp_val_d :std_ulogic; +signal ex4_wayD_fxubyp_val_q :std_ulogic; +signal ex3_wayD_relbyp_val_d :std_ulogic; +signal ex3_wayD_relbyp_val_q :std_ulogic; +signal ex4_wayD_relbyp_val_d :std_ulogic; +signal ex4_wayD_relbyp_val_q :std_ulogic; +signal ex4_wayD_byp_sel :std_ulogic_vector(0 to 1); +signal rel24_wayD_fxubyp_val_d :std_ulogic; +signal rel24_wayD_fxubyp_val_q :std_ulogic; +signal rel24_wayD_relbyp_val_d :std_ulogic; +signal rel24_wayD_relbyp_val_q :std_ulogic; +signal rel24_wayD_byp_sel :std_ulogic_vector(0 to 1); +signal tagE_hit :std_ulogic; +signal tagE_hit_b :std_ulogic; +signal arr_wayE_val :std_ulogic_vector(0 to 5); +signal p0_arr_wayE_rd :std_ulogic_vector(0 to 5); +signal flush_wayE_d :std_ulogic_vector(0 to 5); +signal flush_wayE_q :std_ulogic_vector(0 to 5); +signal rel_wayE_clr :std_ulogic; +signal rel_wayE_set :std_ulogic; +signal rel_par_wE_clr :std_ulogic; +signal wayE_val :std_ulogic_vector(0 to 5); +signal wayE_val_b_q :std_ulogic_vector(0 to 5); +signal wayE_val_b1 :std_ulogic; +signal congr_cl_ex2_wayE_byp :std_ulogic_vector(1 to 7); +signal congr_cl_ex2_wayE_sel :std_ulogic_vector(2 to 7); +signal rel_arr_wayE_val :std_ulogic_vector(0 to 5); +signal p1_arr_wayE_rd :std_ulogic_vector(0 to 5); +signal rel_wayE_val_b_q :std_ulogic_vector(0 to 5); +signal rel_wayE_val :std_ulogic_vector(0 to 5); +signal congr_cl_rel13_wayE_byp :std_ulogic_vector(1 to 7); +signal congr_cl_rel13_wayE_sel :std_ulogic_vector(2 to 7); +signal reload_wayE_d :std_ulogic_vector(0 to 5); +signal reload_wayE_q :std_ulogic_vector(0 to 5); +signal reload_wayE_data_d :std_ulogic_vector(0 to 5); +signal reload_wayE_data_q :std_ulogic_vector(0 to 5); +signal reload_wayE_data2_d :std_ulogic_vector(0 to 5); +signal reload_wayE_data2_q :std_ulogic_vector(0 to 5); +signal reload_wayE_upd_d :std_ulogic; +signal reload_wayE_upd_q :std_ulogic; +signal reload_wayE_clr :std_ulogic; +signal reload_wayE_upd2_d :std_ulogic; +signal reload_wayE_upd2_q :std_ulogic; +signal reload_wayE_upd3_d :std_ulogic; +signal reload_wayE_upd3_q :std_ulogic; +signal reload_wayE :std_ulogic_vector(0 to 5); +signal binv_wayE_upd_d :std_ulogic; +signal binv_wayE_upd_q :std_ulogic; +signal binv_wayE_upd1 :std_ulogic; +signal binv_wayE_upd2_d :std_ulogic; +signal binv_wayE_upd2_q :std_ulogic; +signal binv_wayE_upd3_d :std_ulogic; +signal binv_wayE_upd3_q :std_ulogic; +signal flush_wayE_data1 :std_ulogic_vector(0 to 5); +signal flush_wayE_data_d :std_ulogic_vector(0 to 5); +signal flush_wayE_data_q :std_ulogic_vector(0 to 5); +signal flush_wayE_data2_d :std_ulogic_vector(0 to 5); +signal flush_wayE_data2_q :std_ulogic_vector(0 to 5); +signal xu_op_hit_wayE_b :std_ulogic; +signal xu_op_hit_wayE :std_ulogic; +signal xu_op_hit_wayE_dly_b :std_ulogic; +signal clr_val_wayE :std_ulogic; +signal upd_lck_wayE :std_ulogic_vector(0 to 1); +signal inval_clr_lck_wE_d :std_ulogic; +signal inval_clr_lck_wE_q :std_ulogic; +signal perr_way_det_wayE :std_ulogic; +signal perr_wayE_watch_lost :std_ulogic_vector(0 to 3); +signal wayE_watch_value :std_ulogic; +signal ex4_lost_wayE :std_ulogic_vector(0 to 3); +signal ex3_xuop_lost_watch_wayE :std_ulogic; +signal ex3_xuop_wayE_upd :std_ulogic; +signal ex4_xuop_wayE_upd_d :std_ulogic; +signal ex4_xuop_wayE_upd_q :std_ulogic; +signal ex4_wayE_val_d :std_ulogic_vector(0 to 5); +signal ex4_wayE_val_q :std_ulogic_vector(0 to 5); +signal rel_wayE_val_stg_d :std_ulogic_vector(0 to 5); +signal rel_wayE_val_stg_q :std_ulogic_vector(0 to 5); +signal ex5_xuop_wayE_upd_d :std_ulogic; +signal ex5_xuop_wayE_upd_q :std_ulogic; +signal congr_cl_ex3_upd_wayE :std_ulogic; +signal congr_cl_ex4_upd_wayE :std_ulogic; +signal congr_cl_ex5_upd_wayE :std_ulogic; +signal congr_cl_m_upd_wayE_d :std_ulogic; +signal congr_cl_m_upd_wayE_q :std_ulogic; +signal ex3_cClass_wayE_hit :std_ulogic; +signal wayE_later_stg_pri :std_ulogic_vector(0 to 5); +signal wayE_early_stg_pri :std_ulogic_vector(0 to 5); +signal wayE_stg_val :std_ulogic_vector(0 to 5); +signal wayE_stg_val_b :std_ulogic_vector(0 to 5); +signal rel_wayE_later_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayE_early_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayE_stg_val :std_ulogic_vector(0 to 5); +signal rel_wayE_stg_val_b :std_ulogic_vector(0 to 5); +signal wayE_early_sel :std_ulogic; +signal wayE_late_sel :std_ulogic; +signal rel_wayE_early_sel :std_ulogic; +signal rel_wayE_late_sel :std_ulogic; +signal ex3_wayE_hit :std_ulogic; +signal rel_lost_watch_wayE_evict :std_ulogic_vector(0 to 3); +signal ex3_wayE_fxubyp_val_d :std_ulogic; +signal ex3_wayE_fxubyp_val_q :std_ulogic; +signal ex4_wayE_fxubyp_val_d :std_ulogic; +signal ex4_wayE_fxubyp_val_q :std_ulogic; +signal ex3_wayE_relbyp_val_d :std_ulogic; +signal ex3_wayE_relbyp_val_q :std_ulogic; +signal ex4_wayE_relbyp_val_d :std_ulogic; +signal ex4_wayE_relbyp_val_q :std_ulogic; +signal ex4_wayE_byp_sel :std_ulogic_vector(0 to 1); +signal rel24_wayE_fxubyp_val_d :std_ulogic; +signal rel24_wayE_fxubyp_val_q :std_ulogic; +signal rel24_wayE_relbyp_val_d :std_ulogic; +signal rel24_wayE_relbyp_val_q :std_ulogic; +signal rel24_wayE_byp_sel :std_ulogic_vector(0 to 1); +signal tagF_hit :std_ulogic; +signal tagF_hit_b :std_ulogic; +signal arr_wayF_val :std_ulogic_vector(0 to 5); +signal p0_arr_wayF_rd :std_ulogic_vector(0 to 5); +signal flush_wayF_d :std_ulogic_vector(0 to 5); +signal flush_wayF_q :std_ulogic_vector(0 to 5); +signal rel_wayF_clr :std_ulogic; +signal rel_wayF_set :std_ulogic; +signal rel_par_wF_clr :std_ulogic; +signal wayF_val :std_ulogic_vector(0 to 5); +signal wayF_val_b_q :std_ulogic_vector(0 to 5); +signal wayF_val_b1 :std_ulogic; +signal congr_cl_ex2_wayF_byp :std_ulogic_vector(1 to 7); +signal congr_cl_ex2_wayF_sel :std_ulogic_vector(2 to 7); +signal rel_arr_wayF_val :std_ulogic_vector(0 to 5); +signal p1_arr_wayF_rd :std_ulogic_vector(0 to 5); +signal rel_wayF_val_b_q :std_ulogic_vector(0 to 5); +signal rel_wayF_val :std_ulogic_vector(0 to 5); +signal congr_cl_rel13_wayF_byp :std_ulogic_vector(1 to 7); +signal congr_cl_rel13_wayF_sel :std_ulogic_vector(2 to 7); +signal reload_wayF_d :std_ulogic_vector(0 to 5); +signal reload_wayF_q :std_ulogic_vector(0 to 5); +signal reload_wayF_data_d :std_ulogic_vector(0 to 5); +signal reload_wayF_data_q :std_ulogic_vector(0 to 5); +signal reload_wayF_data2_d :std_ulogic_vector(0 to 5); +signal reload_wayF_data2_q :std_ulogic_vector(0 to 5); +signal reload_wayF_upd_d :std_ulogic; +signal reload_wayF_upd_q :std_ulogic; +signal reload_wayF_clr :std_ulogic; +signal reload_wayF_upd2_d :std_ulogic; +signal reload_wayF_upd2_q :std_ulogic; +signal reload_wayF_upd3_d :std_ulogic; +signal reload_wayF_upd3_q :std_ulogic; +signal reload_wayF :std_ulogic_vector(0 to 5); +signal binv_wayF_upd_d :std_ulogic; +signal binv_wayF_upd_q :std_ulogic; +signal binv_wayF_upd1 :std_ulogic; +signal binv_wayF_upd2_d :std_ulogic; +signal binv_wayF_upd2_q :std_ulogic; +signal binv_wayF_upd3_d :std_ulogic; +signal binv_wayF_upd3_q :std_ulogic; +signal flush_wayF_data1 :std_ulogic_vector(0 to 5); +signal flush_wayF_data_d :std_ulogic_vector(0 to 5); +signal flush_wayF_data_q :std_ulogic_vector(0 to 5); +signal flush_wayF_data2_d :std_ulogic_vector(0 to 5); +signal flush_wayF_data2_q :std_ulogic_vector(0 to 5); +signal xu_op_hit_wayF_b :std_ulogic; +signal xu_op_hit_wayF :std_ulogic; +signal xu_op_hit_wayF_dly_b :std_ulogic; +signal clr_val_wayF :std_ulogic; +signal upd_lck_wayF :std_ulogic_vector(0 to 1); +signal inval_clr_lck_wF_d :std_ulogic; +signal inval_clr_lck_wF_q :std_ulogic; +signal perr_way_det_wayF :std_ulogic; +signal perr_wayF_watch_lost :std_ulogic_vector(0 to 3); +signal wayF_watch_value :std_ulogic; +signal ex4_lost_wayF :std_ulogic_vector(0 to 3); +signal ex3_xuop_lost_watch_wayF :std_ulogic; +signal ex3_xuop_wayF_upd :std_ulogic; +signal ex4_xuop_wayF_upd_d :std_ulogic; +signal ex4_xuop_wayF_upd_q :std_ulogic; +signal ex4_wayF_val_d :std_ulogic_vector(0 to 5); +signal ex4_wayF_val_q :std_ulogic_vector(0 to 5); +signal rel_wayF_val_stg_d :std_ulogic_vector(0 to 5); +signal rel_wayF_val_stg_q :std_ulogic_vector(0 to 5); +signal ex5_xuop_wayF_upd_d :std_ulogic; +signal ex5_xuop_wayF_upd_q :std_ulogic; +signal congr_cl_ex3_upd_wayF :std_ulogic; +signal congr_cl_ex4_upd_wayF :std_ulogic; +signal congr_cl_ex5_upd_wayF :std_ulogic; +signal congr_cl_m_upd_wayF_d :std_ulogic; +signal congr_cl_m_upd_wayF_q :std_ulogic; +signal ex3_cClass_wayF_hit :std_ulogic; +signal wayF_later_stg_pri :std_ulogic_vector(0 to 5); +signal wayF_early_stg_pri :std_ulogic_vector(0 to 5); +signal wayF_stg_val :std_ulogic_vector(0 to 5); +signal wayF_stg_val_b :std_ulogic_vector(0 to 5); +signal rel_wayF_later_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayF_early_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayF_stg_val :std_ulogic_vector(0 to 5); +signal rel_wayF_stg_val_b :std_ulogic_vector(0 to 5); +signal wayF_early_sel :std_ulogic; +signal wayF_late_sel :std_ulogic; +signal rel_wayF_early_sel :std_ulogic; +signal rel_wayF_late_sel :std_ulogic; +signal ex3_wayF_hit :std_ulogic; +signal rel_lost_watch_wayF_evict :std_ulogic_vector(0 to 3); +signal ex3_wayF_fxubyp_val_d :std_ulogic; +signal ex3_wayF_fxubyp_val_q :std_ulogic; +signal ex4_wayF_fxubyp_val_d :std_ulogic; +signal ex4_wayF_fxubyp_val_q :std_ulogic; +signal ex3_wayF_relbyp_val_d :std_ulogic; +signal ex3_wayF_relbyp_val_q :std_ulogic; +signal ex4_wayF_relbyp_val_d :std_ulogic; +signal ex4_wayF_relbyp_val_q :std_ulogic; +signal ex4_wayF_byp_sel :std_ulogic_vector(0 to 1); +signal rel24_wayF_fxubyp_val_d :std_ulogic; +signal rel24_wayF_fxubyp_val_q :std_ulogic; +signal rel24_wayF_relbyp_val_d :std_ulogic; +signal rel24_wayF_relbyp_val_q :std_ulogic; +signal rel24_wayF_byp_sel :std_ulogic_vector(0 to 1); +signal tagG_hit :std_ulogic; +signal tagG_hit_b :std_ulogic; +signal arr_wayG_val :std_ulogic_vector(0 to 5); +signal p0_arr_wayG_rd :std_ulogic_vector(0 to 5); +signal flush_wayG_d :std_ulogic_vector(0 to 5); +signal flush_wayG_q :std_ulogic_vector(0 to 5); +signal rel_wayG_clr :std_ulogic; +signal rel_wayG_set :std_ulogic; +signal rel_par_wG_clr :std_ulogic; +signal wayG_val :std_ulogic_vector(0 to 5); +signal wayG_val_b_q :std_ulogic_vector(0 to 5); +signal wayG_val_b1 :std_ulogic; +signal congr_cl_ex2_wayG_byp :std_ulogic_vector(1 to 7); +signal congr_cl_ex2_wayG_sel :std_ulogic_vector(2 to 7); +signal rel_arr_wayG_val :std_ulogic_vector(0 to 5); +signal p1_arr_wayG_rd :std_ulogic_vector(0 to 5); +signal rel_wayG_val_b_q :std_ulogic_vector(0 to 5); +signal rel_wayG_val :std_ulogic_vector(0 to 5); +signal congr_cl_rel13_wayG_byp :std_ulogic_vector(1 to 7); +signal congr_cl_rel13_wayG_sel :std_ulogic_vector(2 to 7); +signal reload_wayG_d :std_ulogic_vector(0 to 5); +signal reload_wayG_q :std_ulogic_vector(0 to 5); +signal reload_wayG_data_d :std_ulogic_vector(0 to 5); +signal reload_wayG_data_q :std_ulogic_vector(0 to 5); +signal reload_wayG_data2_d :std_ulogic_vector(0 to 5); +signal reload_wayG_data2_q :std_ulogic_vector(0 to 5); +signal reload_wayG_upd_d :std_ulogic; +signal reload_wayG_upd_q :std_ulogic; +signal reload_wayG_clr :std_ulogic; +signal reload_wayG_upd2_d :std_ulogic; +signal reload_wayG_upd2_q :std_ulogic; +signal reload_wayG_upd3_d :std_ulogic; +signal reload_wayG_upd3_q :std_ulogic; +signal reload_wayG :std_ulogic_vector(0 to 5); +signal binv_wayG_upd_d :std_ulogic; +signal binv_wayG_upd_q :std_ulogic; +signal binv_wayG_upd1 :std_ulogic; +signal binv_wayG_upd2_d :std_ulogic; +signal binv_wayG_upd2_q :std_ulogic; +signal binv_wayG_upd3_d :std_ulogic; +signal binv_wayG_upd3_q :std_ulogic; +signal flush_wayG_data1 :std_ulogic_vector(0 to 5); +signal flush_wayG_data_d :std_ulogic_vector(0 to 5); +signal flush_wayG_data_q :std_ulogic_vector(0 to 5); +signal flush_wayG_data2_d :std_ulogic_vector(0 to 5); +signal flush_wayG_data2_q :std_ulogic_vector(0 to 5); +signal xu_op_hit_wayG_b :std_ulogic; +signal xu_op_hit_wayG :std_ulogic; +signal xu_op_hit_wayG_dly_b :std_ulogic; +signal clr_val_wayG :std_ulogic; +signal upd_lck_wayG :std_ulogic_vector(0 to 1); +signal inval_clr_lck_wG_d :std_ulogic; +signal inval_clr_lck_wG_q :std_ulogic; +signal perr_way_det_wayG :std_ulogic; +signal perr_wayG_watch_lost :std_ulogic_vector(0 to 3); +signal wayG_watch_value :std_ulogic; +signal ex4_lost_wayG :std_ulogic_vector(0 to 3); +signal ex3_xuop_lost_watch_wayG :std_ulogic; +signal ex3_xuop_wayG_upd :std_ulogic; +signal ex4_xuop_wayG_upd_d :std_ulogic; +signal ex4_xuop_wayG_upd_q :std_ulogic; +signal ex4_wayG_val_d :std_ulogic_vector(0 to 5); +signal ex4_wayG_val_q :std_ulogic_vector(0 to 5); +signal rel_wayG_val_stg_d :std_ulogic_vector(0 to 5); +signal rel_wayG_val_stg_q :std_ulogic_vector(0 to 5); +signal ex5_xuop_wayG_upd_d :std_ulogic; +signal ex5_xuop_wayG_upd_q :std_ulogic; +signal congr_cl_ex3_upd_wayG :std_ulogic; +signal congr_cl_ex4_upd_wayG :std_ulogic; +signal congr_cl_ex5_upd_wayG :std_ulogic; +signal congr_cl_m_upd_wayG_d :std_ulogic; +signal congr_cl_m_upd_wayG_q :std_ulogic; +signal ex3_cClass_wayG_hit :std_ulogic; +signal wayG_later_stg_pri :std_ulogic_vector(0 to 5); +signal wayG_early_stg_pri :std_ulogic_vector(0 to 5); +signal wayG_stg_val :std_ulogic_vector(0 to 5); +signal wayG_stg_val_b :std_ulogic_vector(0 to 5); +signal rel_wayG_later_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayG_early_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayG_stg_val :std_ulogic_vector(0 to 5); +signal rel_wayG_stg_val_b :std_ulogic_vector(0 to 5); +signal wayG_early_sel :std_ulogic; +signal wayG_late_sel :std_ulogic; +signal rel_wayG_early_sel :std_ulogic; +signal rel_wayG_late_sel :std_ulogic; +signal ex3_wayG_hit :std_ulogic; +signal rel_lost_watch_wayG_evict :std_ulogic_vector(0 to 3); +signal ex3_wayG_fxubyp_val_d :std_ulogic; +signal ex3_wayG_fxubyp_val_q :std_ulogic; +signal ex4_wayG_fxubyp_val_d :std_ulogic; +signal ex4_wayG_fxubyp_val_q :std_ulogic; +signal ex3_wayG_relbyp_val_d :std_ulogic; +signal ex3_wayG_relbyp_val_q :std_ulogic; +signal ex4_wayG_relbyp_val_d :std_ulogic; +signal ex4_wayG_relbyp_val_q :std_ulogic; +signal ex4_wayG_byp_sel :std_ulogic_vector(0 to 1); +signal rel24_wayG_fxubyp_val_d :std_ulogic; +signal rel24_wayG_fxubyp_val_q :std_ulogic; +signal rel24_wayG_relbyp_val_d :std_ulogic; +signal rel24_wayG_relbyp_val_q :std_ulogic; +signal rel24_wayG_byp_sel :std_ulogic_vector(0 to 1); +signal tagH_hit :std_ulogic; +signal tagH_hit_b :std_ulogic; +signal arr_wayH_val :std_ulogic_vector(0 to 5); +signal p0_arr_wayH_rd :std_ulogic_vector(0 to 5); +signal flush_wayH_d :std_ulogic_vector(0 to 5); +signal flush_wayH_q :std_ulogic_vector(0 to 5); +signal rel_wayH_clr :std_ulogic; +signal rel_wayH_set :std_ulogic; +signal rel_par_wH_clr :std_ulogic; +signal wayH_val :std_ulogic_vector(0 to 5); +signal wayH_val_b_q :std_ulogic_vector(0 to 5); +signal wayH_val_b1 :std_ulogic; +signal congr_cl_ex2_wayH_byp :std_ulogic_vector(1 to 7); +signal congr_cl_ex2_wayH_sel :std_ulogic_vector(2 to 7); +signal rel_arr_wayH_val :std_ulogic_vector(0 to 5); +signal p1_arr_wayH_rd :std_ulogic_vector(0 to 5); +signal rel_wayH_val_b_q :std_ulogic_vector(0 to 5); +signal rel_wayH_val :std_ulogic_vector(0 to 5); +signal congr_cl_rel13_wayH_byp :std_ulogic_vector(1 to 7); +signal congr_cl_rel13_wayH_sel :std_ulogic_vector(2 to 7); +signal reload_wayH_d :std_ulogic_vector(0 to 5); +signal reload_wayH_q :std_ulogic_vector(0 to 5); +signal reload_wayH_data_d :std_ulogic_vector(0 to 5); +signal reload_wayH_data_q :std_ulogic_vector(0 to 5); +signal reload_wayH_data2_d :std_ulogic_vector(0 to 5); +signal reload_wayH_data2_q :std_ulogic_vector(0 to 5); +signal reload_wayH_upd_d :std_ulogic; +signal reload_wayH_upd_q :std_ulogic; +signal reload_wayH_clr :std_ulogic; +signal reload_wayH_upd2_d :std_ulogic; +signal reload_wayH_upd2_q :std_ulogic; +signal reload_wayH_upd3_d :std_ulogic; +signal reload_wayH_upd3_q :std_ulogic; +signal reload_wayH :std_ulogic_vector(0 to 5); +signal binv_wayH_upd_d :std_ulogic; +signal binv_wayH_upd_q :std_ulogic; +signal binv_wayH_upd1 :std_ulogic; +signal binv_wayH_upd2_d :std_ulogic; +signal binv_wayH_upd2_q :std_ulogic; +signal binv_wayH_upd3_d :std_ulogic; +signal binv_wayH_upd3_q :std_ulogic; +signal flush_wayH_data1 :std_ulogic_vector(0 to 5); +signal flush_wayH_data_d :std_ulogic_vector(0 to 5); +signal flush_wayH_data_q :std_ulogic_vector(0 to 5); +signal flush_wayH_data2_d :std_ulogic_vector(0 to 5); +signal flush_wayH_data2_q :std_ulogic_vector(0 to 5); +signal xu_op_hit_wayH_b :std_ulogic; +signal xu_op_hit_wayH :std_ulogic; +signal xu_op_hit_wayH_dly_b :std_ulogic; +signal clr_val_wayH :std_ulogic; +signal upd_lck_wayH :std_ulogic_vector(0 to 1); +signal inval_clr_lck_wH_d :std_ulogic; +signal inval_clr_lck_wH_q :std_ulogic; +signal perr_way_det_wayH :std_ulogic; +signal perr_wayH_watch_lost :std_ulogic_vector(0 to 3); +signal wayH_watch_value :std_ulogic; +signal ex4_lost_wayH :std_ulogic_vector(0 to 3); +signal ex3_xuop_lost_watch_wayH :std_ulogic; +signal ex3_xuop_wayH_upd :std_ulogic; +signal ex4_xuop_wayH_upd_d :std_ulogic; +signal ex4_xuop_wayH_upd_q :std_ulogic; +signal ex4_wayH_val_d :std_ulogic_vector(0 to 5); +signal ex4_wayH_val_q :std_ulogic_vector(0 to 5); +signal rel_wayH_val_stg_d :std_ulogic_vector(0 to 5); +signal rel_wayH_val_stg_q :std_ulogic_vector(0 to 5); +signal ex5_xuop_wayH_upd_d :std_ulogic; +signal ex5_xuop_wayH_upd_q :std_ulogic; +signal congr_cl_ex3_upd_wayH :std_ulogic; +signal congr_cl_ex4_upd_wayH :std_ulogic; +signal congr_cl_ex5_upd_wayH :std_ulogic; +signal congr_cl_m_upd_wayH_d :std_ulogic; +signal congr_cl_m_upd_wayH_q :std_ulogic; +signal ex3_cClass_wayH_hit :std_ulogic; +signal wayH_later_stg_pri :std_ulogic_vector(0 to 5); +signal wayH_early_stg_pri :std_ulogic_vector(0 to 5); +signal wayH_stg_val :std_ulogic_vector(0 to 5); +signal wayH_stg_val_b :std_ulogic_vector(0 to 5); +signal rel_wayH_later_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayH_early_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayH_stg_val :std_ulogic_vector(0 to 5); +signal rel_wayH_stg_val_b :std_ulogic_vector(0 to 5); +signal wayH_early_sel :std_ulogic; +signal wayH_late_sel :std_ulogic; +signal rel_wayH_early_sel :std_ulogic; +signal rel_wayH_late_sel :std_ulogic; +signal ex3_wayH_hit :std_ulogic; +signal rel_lost_watch_wayH_evict :std_ulogic_vector(0 to 3); +signal ex3_wayH_fxubyp_val_d :std_ulogic; +signal ex3_wayH_fxubyp_val_q :std_ulogic; +signal ex4_wayH_fxubyp_val_d :std_ulogic; +signal ex4_wayH_fxubyp_val_q :std_ulogic; +signal ex3_wayH_relbyp_val_d :std_ulogic; +signal ex3_wayH_relbyp_val_q :std_ulogic; +signal ex4_wayH_relbyp_val_d :std_ulogic; +signal ex4_wayH_relbyp_val_q :std_ulogic; +signal ex4_wayH_byp_sel :std_ulogic_vector(0 to 1); +signal rel24_wayH_fxubyp_val_d :std_ulogic; +signal rel24_wayH_fxubyp_val_q :std_ulogic; +signal rel24_wayH_relbyp_val_d :std_ulogic; +signal rel24_wayH_relbyp_val_q :std_ulogic; +signal rel24_wayH_byp_sel :std_ulogic_vector(0 to 1); +signal stm_upd_watchlost_tid0 :std_ulogic_vector(0 to 1); +signal upd_watch_tid0_wayA :std_ulogic_vector(0 to 1); +signal upd_watch_tid0_wayB :std_ulogic_vector(0 to 1); +signal upd_watch_tid0_wayC :std_ulogic_vector(0 to 1); +signal upd_watch_tid0_wayD :std_ulogic_vector(0 to 1); +signal upd_watch_tid0_wayE :std_ulogic_vector(0 to 1); +signal upd_watch_tid0_wayF :std_ulogic_vector(0 to 1); +signal upd_watch_tid0_wayG :std_ulogic_vector(0 to 1); +signal upd_watch_tid0_wayH :std_ulogic_vector(0 to 1); +signal stm_upd_watchlost_tid1 :std_ulogic_vector(0 to 1); +signal upd_watch_tid1_wayA :std_ulogic_vector(0 to 1); +signal upd_watch_tid1_wayB :std_ulogic_vector(0 to 1); +signal upd_watch_tid1_wayC :std_ulogic_vector(0 to 1); +signal upd_watch_tid1_wayD :std_ulogic_vector(0 to 1); +signal upd_watch_tid1_wayE :std_ulogic_vector(0 to 1); +signal upd_watch_tid1_wayF :std_ulogic_vector(0 to 1); +signal upd_watch_tid1_wayG :std_ulogic_vector(0 to 1); +signal upd_watch_tid1_wayH :std_ulogic_vector(0 to 1); +signal stm_upd_watchlost_tid2 :std_ulogic_vector(0 to 1); +signal upd_watch_tid2_wayA :std_ulogic_vector(0 to 1); +signal upd_watch_tid2_wayB :std_ulogic_vector(0 to 1); +signal upd_watch_tid2_wayC :std_ulogic_vector(0 to 1); +signal upd_watch_tid2_wayD :std_ulogic_vector(0 to 1); +signal upd_watch_tid2_wayE :std_ulogic_vector(0 to 1); +signal upd_watch_tid2_wayF :std_ulogic_vector(0 to 1); +signal upd_watch_tid2_wayG :std_ulogic_vector(0 to 1); +signal upd_watch_tid2_wayH :std_ulogic_vector(0 to 1); +signal stm_upd_watchlost_tid3 :std_ulogic_vector(0 to 1); +signal upd_watch_tid3_wayA :std_ulogic_vector(0 to 1); +signal upd_watch_tid3_wayB :std_ulogic_vector(0 to 1); +signal upd_watch_tid3_wayC :std_ulogic_vector(0 to 1); +signal upd_watch_tid3_wayD :std_ulogic_vector(0 to 1); +signal upd_watch_tid3_wayE :std_ulogic_vector(0 to 1); +signal upd_watch_tid3_wayF :std_ulogic_vector(0 to 1); +signal upd_watch_tid3_wayG :std_ulogic_vector(0 to 1); +signal upd_watch_tid3_wayH :std_ulogic_vector(0 to 1); +signal congr_cl_all_act_d :std_ulogic; +signal congr_cl_all_act_q :std_ulogic; +signal ex3_flush_cline_d :std_ulogic; +signal ex3_flush_cline_q :std_ulogic; +signal congr_cl_ex2_ex3_m :std_ulogic; +signal congr_cl_ex2_ex4_m :std_ulogic; +signal congr_cl_ex2_ex5_m :std_ulogic; +signal congr_cl_ex2_relu_m :std_ulogic; +signal congr_cl_ex2_relu_s_m :std_ulogic; +signal congr_cl_ex2_ex3_cmp_d :std_ulogic; +signal congr_cl_ex2_ex3_cmp_q :std_ulogic; +signal congr_cl_ex2_ex4_cmp_d :std_ulogic; +signal congr_cl_ex2_ex4_cmp_q :std_ulogic; +signal congr_cl_ex2_ex5_cmp_d :std_ulogic; +signal congr_cl_ex2_ex5_cmp_q :std_ulogic; +signal congr_cl_ex2_ex6_cmp_d :std_ulogic; +signal congr_cl_ex2_ex6_cmp_q :std_ulogic; +signal congr_cl_ex3_ex4_cmp_d :std_ulogic; +signal congr_cl_ex3_ex4_cmp_q :std_ulogic; +signal congr_cl_ex3_ex5_cmp_d :std_ulogic; +signal congr_cl_ex3_ex5_cmp_q :std_ulogic; +signal congr_cl_ex3_ex6_cmp_d :std_ulogic; +signal congr_cl_ex3_ex6_cmp_q :std_ulogic; +signal congr_cl_ex4_ex5_cmp_d :std_ulogic; +signal congr_cl_ex4_ex5_cmp_q :std_ulogic; +signal congr_cl_ex4_ex6_cmp_d :std_ulogic; +signal congr_cl_ex4_ex6_cmp_q :std_ulogic; +signal congr_cl_ex4_ex7_cmp_d :std_ulogic; +signal congr_cl_ex4_ex7_cmp_q :std_ulogic; +signal congr_cl_ex2_p0_cmp :std_ulogic; +signal congr_cl_ex2_relu_cmp_d :std_ulogic; +signal congr_cl_ex2_relu_cmp_q :std_ulogic; +signal congr_cl_ex2_relu_s_cmp_d :std_ulogic; +signal congr_cl_ex2_relu_s_cmp_q :std_ulogic; +signal congr_cl_ex2_rel_upd_cmp_d :std_ulogic; +signal congr_cl_ex2_rel_upd_cmp_q :std_ulogic; +signal congr_cl_ex2_p1_cmp :std_ulogic; +signal ex4_congr_cl_d :std_ulogic_vector(3 to 7); +signal ex4_congr_cl_q :std_ulogic_vector(3 to 7); +signal ex5_congr_cl_d :std_ulogic_vector(3 to 7); +signal ex5_congr_cl_q :std_ulogic_vector(3 to 7); +signal ex6_congr_cl_d :std_ulogic_vector(3 to 7); +signal ex6_congr_cl_q :std_ulogic_vector(3 to 7); +signal ex7_congr_cl_d :std_ulogic_vector(3 to 7); +signal ex7_congr_cl_q :std_ulogic_vector(3 to 7); +signal ex8_congr_cl_d :std_ulogic_vector(3 to 7); +signal ex8_congr_cl_q :std_ulogic_vector(3 to 7); +signal ex9_congr_cl_d :std_ulogic_vector(3 to 7); +signal ex9_congr_cl_q :std_ulogic_vector(3 to 7); +signal rel_early_congr_cl :std_ulogic_vector(3 to 7); +signal rel_congr_cl_d :std_ulogic_vector(3 to 7); +signal rel_congr_cl_q :std_ulogic_vector(3 to 7); +signal rel_val_stg1 :std_ulogic; +signal rel_val_stg2_d :std_ulogic; +signal rel_val_stg2_q :std_ulogic; +signal rel_val_clr_d :std_ulogic; +signal rel_val_clr_q :std_ulogic; +signal rel_val_stg3 :std_ulogic; +signal rel_val_stg4 :std_ulogic; +signal rel_val_stg4_d :std_ulogic; +signal rel_val_stg4_q :std_ulogic; +signal rel_binv_stg4_d :std_ulogic; +signal rel_binv_stg4_q :std_ulogic; +signal back_inval_stg2 :std_ulogic; +signal back_inval_stg3_d :std_ulogic; +signal back_inval_stg3_q :std_ulogic; +signal back_inval_stg4_d :std_ulogic; +signal back_inval_stg4_q :std_ulogic; +signal back_inval_stg5_d :std_ulogic; +signal back_inval_stg5_q :std_ulogic; +signal ex1_congr_cl :std_ulogic_vector(3 to 7); +signal ex2_congr_cl_d :std_ulogic_vector(3 to 7); +signal ex2_congr_cl_q :std_ulogic_vector(3 to 7); +signal ex3_congr_cl_d :std_ulogic_vector(3 to 7); +signal ex3_congr_cl_q :std_ulogic_vector(3 to 7); +signal rel24_congr_cl_d :std_ulogic_vector(3 to 7); +signal rel24_congr_cl_q :std_ulogic_vector(3 to 7); +signal p0_wren_d :std_ulogic; +signal p0_wren_q :std_ulogic; +signal p0_wren_cpy_d :std_ulogic; +signal p0_wren_cpy_q :std_ulogic; +signal p0_wren_stg_d :std_ulogic; +signal p0_wren_stg_q :std_ulogic; +signal p1_wren_d :std_ulogic; +signal p1_wren_q :std_ulogic; +signal p1_wren_cpy_d :std_ulogic; +signal p1_wren_cpy_q :std_ulogic; +signal congr_cl_rel13_ex3_m :std_ulogic; +signal congr_cl_rel13_ex4_m :std_ulogic; +signal congr_cl_rel13_ex5_m :std_ulogic; +signal congr_cl_rel13_relu_m :std_ulogic; +signal congr_cl_rel13_relu_s_m :std_ulogic; +signal congr_cl_rel13_ex3_cmp_d :std_ulogic; +signal congr_cl_rel13_ex3_cmp_q :std_ulogic; +signal congr_cl_rel13_ex4_cmp_d :std_ulogic; +signal congr_cl_rel13_ex4_cmp_q :std_ulogic; +signal congr_cl_rel13_ex5_cmp_d :std_ulogic; +signal congr_cl_rel13_ex5_cmp_q :std_ulogic; +signal congr_cl_rel13_ex6_cmp_d :std_ulogic; +signal congr_cl_rel13_ex6_cmp_q :std_ulogic; +signal congr_cl_rel13_p0_cmp :std_ulogic; +signal congr_cl_rel13_relu_cmp_d :std_ulogic; +signal congr_cl_rel13_relu_cmp_q :std_ulogic; +signal congr_cl_rel13_relu_s_cmp_d :std_ulogic; +signal congr_cl_rel13_relu_s_cmp_q :std_ulogic; +signal congr_cl_rel13_rel_upd_cmp_d :std_ulogic; +signal congr_cl_rel13_rel_upd_cmp_q :std_ulogic; +signal congr_cl_rel13_p1_cmp :std_ulogic; +signal ex3_c_acc :std_ulogic; +signal fxu_pipe_val :std_ulogic; +signal rel_set_val :std_ulogic; +signal ex3_store_instr_d :std_ulogic; +signal ex3_store_instr_q :std_ulogic; +signal ex3_lock_set_d :std_ulogic; +signal ex3_lock_set_q :std_ulogic; +signal ex4_lock_set_d :std_ulogic; +signal ex4_lock_set_q :std_ulogic; +signal ex5_lock_set_d :std_ulogic; +signal ex5_lock_set_q :std_ulogic; +signal ex3_lock_clr_d :std_ulogic; +signal ex3_lock_clr_q :std_ulogic; +signal clr_val :std_ulogic; +signal clr_lock :std_ulogic; +signal rel_val_set :std_ulogic; +signal rel_lock_set_d :std_ulogic; +signal rel_lock_set_q :std_ulogic; +signal rel_l1dump_cslc_d :std_ulogic; +signal rel_l1dump_cslc_q :std_ulogic; +signal rel_no_ovr_lock :std_ulogic; +signal rel_lock_lost :std_ulogic; +signal ex3_xuop_val :std_ulogic; +signal ex3_xuop_val_d :std_ulogic; +signal ex3_xuop_val_q :std_ulogic; +signal ex4_xuop_val :std_ulogic; +signal ex4_xuop_val_d :std_ulogic; +signal ex4_xuop_val_q :std_ulogic; +signal ex5_xuop_val :std_ulogic; +signal ex5_xuop_val_d :std_ulogic; +signal ex5_xuop_val_q :std_ulogic; +signal ex4_l_fld_b1_d :std_ulogic; +signal ex4_l_fld_b1_q :std_ulogic; +signal rel_in_progress :std_ulogic; +signal rel_in_progress_d :std_ulogic; +signal rel_in_progress_q :std_ulogic; +signal ex4_miss_q :std_ulogic; +signal ex4_way_hit_d :std_ulogic_vector(0 to 7); +signal ex4_way_hit_q :std_ulogic_vector(0 to 7); +signal ex5_way_hit_d :std_ulogic_vector(0 to 7); +signal ex5_way_hit_q :std_ulogic_vector(0 to 7); +signal ex6_way_hit_d :std_ulogic_vector(0 to 7); +signal ex6_way_hit_q :std_ulogic_vector(0 to 7); +signal ex7_way_hit_d :std_ulogic_vector(0 to 7); +signal ex7_way_hit_q :std_ulogic_vector(0 to 7); +signal ex8_way_hit_d :std_ulogic_vector(0 to 7); +signal ex8_way_hit_q :std_ulogic_vector(0 to 7); +signal ex9_way_hit_d :std_ulogic_vector(0 to 7); +signal ex9_way_hit_q :std_ulogic_vector(0 to 7); +signal dcpar_err_congr_cl :std_ulogic_vector(3 to 7); +signal dcpar_err_stg1_d :std_ulogic; +signal dcpar_err_stg1_q :std_ulogic; +signal dcpar_err_stg2_d :std_ulogic; +signal dcpar_err_stg2_q :std_ulogic; +signal dcpar_err_way_d :std_ulogic_vector(0 to 7); +signal dcpar_err_way_q :std_ulogic_vector(0 to 7); +signal dcpar_err_way_inval_d :std_ulogic_vector(0 to 7); +signal dcpar_err_way_inval_q :std_ulogic_vector(0 to 7); +signal dcpar_err_cntr_d :std_ulogic_vector(0 to 1); +signal dcpar_err_cntr_q :std_ulogic_vector(0 to 1); +signal dcpar_err_push :std_ulogic; +signal dcpar_err_rec_cmpl :std_ulogic; +signal dcpar_err_nxt_rec :std_ulogic; +signal dcpar_err_push_queue :std_ulogic; +signal dcpar_err_ind_sel :std_ulogic_vector(0 to 1); +signal dcpar_err_incr_val :std_ulogic; +signal dcpar_err_cntr_sel :std_ulogic_vector(0 to 1); +signal dcpar_err_nxt_cntr :std_ulogic_vector(0 to 1); +signal dcpar_err_rec_inprog :std_ulogic; +signal dcpar_err_ind_sel_d :std_ulogic_vector(0 to 1); +signal dcpar_err_ind_sel_q :std_ulogic_vector(0 to 1); +signal dcpar_err_push_queue_d :std_ulogic; +signal dcpar_err_push_queue_q :std_ulogic; +signal lock_finval :std_ulogic; +signal inval_clr_lck :std_ulogic; +signal xucr0_cslc_xuop_d :std_ulogic; +signal xucr0_cslc_xuop_q :std_ulogic; +signal xucr0_cslc_binv_d :std_ulogic; +signal xucr0_cslc_binv_q :std_ulogic; +signal dci_compl_d :std_ulogic; +signal dci_compl_q :std_ulogic; +signal dci_inval_all_d :std_ulogic; +signal dci_inval_all_q :std_ulogic; +signal inv2_val_d :std_ulogic; +signal inv2_val_q :std_ulogic; +signal perf_binv_hit :std_ulogic; +signal perf_lsu_evnts_d :std_ulogic_vector(0 to 4); +signal perf_lsu_evnts_q :std_ulogic_vector(0 to 4); +signal lock_flash_clear_d :std_ulogic; +signal lock_flash_clear_q :std_ulogic; +signal lock_flash_clear_val_d :std_ulogic; +signal lock_flash_clear_val_q :std_ulogic; +signal rel_port_upd_d :std_ulogic; +signal rel_port_upd_q :std_ulogic; +signal p1_upd_val :std_ulogic; +signal rel_port_wren_d :std_ulogic; +signal rel_port_wren_q :std_ulogic; +signal ex2_thrd_id_d :std_ulogic_vector(0 to 3); +signal ex2_thrd_id_q :std_ulogic_vector(0 to 3); +signal ex3_thrd_id_d :std_ulogic_vector(0 to 3); +signal ex3_thrd_id_q :std_ulogic_vector(0 to 3); +signal ex4_thrd_id_d :std_ulogic_vector(0 to 3); +signal ex4_thrd_id_q :std_ulogic_vector(0 to 3); +signal ex5_thrd_id_d :std_ulogic_vector(0 to 3); +signal ex5_thrd_id_q :std_ulogic_vector(0 to 3); +signal ex3_watch_set_d :std_ulogic; +signal ex3_watch_set_q :std_ulogic; +signal ex4_watch_set_d :std_ulogic; +signal ex4_watch_set_q :std_ulogic; +signal ex5_watch_set_d :std_ulogic; +signal ex5_watch_set_q :std_ulogic; +signal ex3_watch_clr_d :std_ulogic; +signal ex3_watch_clr_q :std_ulogic; +signal ex2_watch_clr_all :std_ulogic; +signal ex2_watch_clr_one :std_ulogic; +signal ex3_watch_clr_all_d :std_ulogic; +signal ex3_watch_clr_all_q :std_ulogic; +signal ex3_watch_clr_all :std_ulogic_vector(0 to 3); +signal ex4_watch_clr_all_d :std_ulogic_vector(0 to 3); +signal ex4_watch_clr_all_q :std_ulogic_vector(0 to 3); +signal ex5_watch_clr_all_d :std_ulogic_vector(0 to 3); +signal ex5_watch_clr_all_q :std_ulogic_vector(0 to 3); +signal ex6_watch_clr_all_d :std_ulogic_vector(0 to 3); +signal ex6_watch_clr_all_q :std_ulogic_vector(0 to 3); +signal ex5_watch_clr_all_val_d :std_ulogic; +signal ex5_watch_clr_all_val_q :std_ulogic; +signal rel_watch_set_d :std_ulogic; +signal rel_watch_set_q :std_ulogic; +signal rel_thrd_id_d :std_ulogic_vector(0 to 3); +signal rel_thrd_id_q :std_ulogic_vector(0 to 3); +signal rel_watch_lost :std_ulogic_vector(0 to 3); +signal lose_watch :std_ulogic_vector(0 to 3); +signal ex4_lose_watch_d :std_ulogic_vector(0 to 3); +signal ex4_lose_watch_q :std_ulogic_vector(0 to 3); +signal clr_watch :std_ulogic_vector(0 to 3); +signal set_watch :std_ulogic_vector(0 to 3); +signal ex4_curr_watch :std_ulogic; +signal stm_watchlost_sel :std_ulogic; +signal ex5_cr_watch_d :std_ulogic; +signal ex5_cr_watch_q :std_ulogic; +signal ex4_lost_watch :std_ulogic_vector(0 to 3); +signal ex4_lost_watch_upd :std_ulogic_vector(0 to 3); +signal ex5_lost_watch_upd_d :std_ulogic_vector(0 to 3); +signal ex5_lost_watch_upd_q :std_ulogic_vector(0 to 3); +signal ex4_watchlost_set_d :std_ulogic_vector(0 to 3); +signal ex4_watchlost_set_q :std_ulogic_vector(0 to 3); +signal ex5_watchlost_set_d :std_ulogic_vector(0 to 3); +signal ex5_watchlost_set_q :std_ulogic_vector(0 to 3); +signal rel_lost_watch_binv_d :std_ulogic_vector(0 to 3); +signal rel_lost_watch_binv_q :std_ulogic_vector(0 to 3); +signal rel_lost_watch_upd_d :std_ulogic_vector(0 to 3); +signal rel_lost_watch_upd_q :std_ulogic_vector(0 to 3); +signal rel_lost_watch_evict :std_ulogic_vector(0 to 3); +signal rel_lost_watch_evict_np :std_ulogic_vector(0 to 3); +signal lost_watch_evict_ovl_d :std_ulogic_vector(0 to 3); +signal lost_watch_evict_ovl_q :std_ulogic_vector(0 to 3); +signal lost_watch_binv :std_ulogic_vector(0 to 3); +signal lost_watch_inter_thrd_d :std_ulogic_vector(0 to 3); +signal lost_watch_inter_thrd_q :std_ulogic_vector(0 to 3); +signal stm_watchlost :std_ulogic_vector(0 to 3); +signal rel_watchlost_upd :std_ulogic_vector(0 to 3); +signal ex5_watchlost_upd :std_ulogic_vector(0 to 3); +signal stm_watchlost_state_d :std_ulogic_vector(0 to 3); +signal stm_watchlost_state_q :std_ulogic_vector(0 to 3); +signal ex5_xuop_p0_upd_d :std_ulogic; +signal ex5_xuop_p0_upd_q :std_ulogic; +signal rel_val_stg24 :std_ulogic; +signal rel_val_stgu_d :std_ulogic; +signal rel_val_stgu_q :std_ulogic; +signal relu_congr_cl_d :std_ulogic_vector(3 to 7); +signal relu_congr_cl_q :std_ulogic_vector(3 to 7); +signal relu_s_congr_cl_d :std_ulogic_vector(3 to 7); +signal relu_s_congr_cl_q :std_ulogic_vector(3 to 7); +signal ex3_thrd_m_d :std_ulogic; +signal ex3_thrd_m_q :std_ulogic; +signal ex4_thrd_m_d :std_ulogic; +signal ex4_thrd_m_q :std_ulogic; +signal ex5_thrd_m_d :std_ulogic; +signal ex5_thrd_m_q :std_ulogic; +signal ex6_thrd_m_d :std_ulogic; +signal ex6_thrd_m_q :std_ulogic; +signal ex7_ld_par_err_d :std_ulogic; +signal ex7_ld_par_err_q :std_ulogic; +signal ex8_ld_par_err_d :std_ulogic; +signal ex8_ld_par_err_q :std_ulogic; +signal ex9_ld_par_err_d :std_ulogic; +signal ex9_ld_par_err_q :std_ulogic; +signal ex6_ld_valid_d :std_ulogic; +signal ex6_ld_valid_q :std_ulogic; +signal ex7_ld_valid_d :std_ulogic; +signal ex7_ld_valid_q :std_ulogic; +signal ex8_ld_valid_d :std_ulogic; +signal ex8_ld_valid_q :std_ulogic; +signal ex9_ld_valid_d :std_ulogic; +signal ex9_ld_valid_q :std_ulogic; +signal inj_dir_multihit_b :std_ulogic; +signal inj_dir_multihit_d :std_ulogic; +signal inj_dir_multihit_q :std_ulogic; +signal binv1_ex1_stg_act :std_ulogic; +signal binv2_ex2_stg_act :std_ulogic; +signal binv3_ex3_stg_act :std_ulogic; +signal binv4_ex4_stg_act :std_ulogic; +signal binv5_ex5_stg_act :std_ulogic; +signal binv2_ex2_val_stg_act :std_ulogic; +signal binv3_ex3_val_stg_act :std_ulogic; +signal binv4_ex4_val_stg_act :std_ulogic; +signal binv5_ex5_val_stg_act :std_ulogic; +signal dcpar_err_stg1_act_d :std_ulogic; +signal dcpar_err_stg1_act_q :std_ulogic; +signal dcpar_err_stg2_act_d :std_ulogic; +signal dcpar_err_stg2_act_q :std_ulogic; +signal rel1_perr_stg_act :std_ulogic; +signal rel2_perr_stg_act :std_ulogic; +signal rel3_perr_stg_act_d :std_ulogic; +signal rel3_perr_stg_act_q :std_ulogic; +signal rel4_perr_stg_act_d :std_ulogic; +signal rel4_perr_stg_act_q :std_ulogic; +signal reload_way_clr_d :std_ulogic_vector(0 to 7); +signal reload_way_clr_q :std_ulogic_vector(0 to 7); +signal ex4_watchSet_coll_d :std_ulogic; +signal ex4_watchSet_coll_q :std_ulogic; +signal watchSet_rel_way_coll :std_ulogic_vector(0 to 7); +signal watchSet_rel_coll_val :std_ulogic_vector(0 to 3); +signal rel24_congr_cl_ex4_cmp_d :std_ulogic; +signal rel24_congr_cl_ex4_cmp_q :std_ulogic; +signal rel24_congr_cl_ex5_cmp_d :std_ulogic; +signal rel24_congr_cl_ex5_cmp_q :std_ulogic; +signal rel24_congr_cl_ex6_cmp_d :std_ulogic; +signal rel24_congr_cl_ex6_cmp_q :std_ulogic; +signal relu_congr_cl_ex5_cmp_d :std_ulogic; +signal relu_congr_cl_ex5_cmp_q :std_ulogic; +signal relu_congr_cl_ex6_cmp_d :std_ulogic; +signal relu_congr_cl_ex6_cmp_q :std_ulogic; +signal relu_congr_cl_ex7_cmp_d :std_ulogic; +signal relu_congr_cl_ex7_cmp_q :std_ulogic; +signal rel_ex5_watchSet_coll :std_ulogic; +signal rel_ex6_watchSet_coll :std_ulogic; +signal rel_ex7_watchSet_coll :std_ulogic; +signal rel_coll_val :std_ulogic; +signal relu_dir_data :std_ulogic_vector(2 to 5); +signal rel_pri_byp_sel :std_ulogic_vector(0 to 2); +signal rel_byp_dir_data :std_ulogic_vector(2 to 5); +signal rel_watchSet_coll_tid :std_ulogic_vector(0 to 3); +signal lost_watch_evict_val_d :std_ulogic_vector(0 to 3); +signal lost_watch_evict_val_q :std_ulogic_vector(0 to 3); +signal dcpar_err_lock_lost :std_ulogic_vector(0 to 7); +signal dirpar_err_lock_lost :std_ulogic_vector(0 to 7); +signal ex3_dir_perr_val :std_ulogic; +signal ex3_dir_multihit_val :std_ulogic; +signal ex4_dir_err_val_d :std_ulogic; +signal ex4_dir_err_val_q :std_ulogic; +signal ex5_dir_err_val_d :std_ulogic; +signal ex5_dir_err_val_q :std_ulogic; +signal ex6_dir_err_val_d :std_ulogic; +signal ex6_dir_err_val_q :std_ulogic; +signal derr2_stg_act_d :std_ulogic; +signal derr2_stg_act_q :std_ulogic; +signal derr3_stg_act_d :std_ulogic; +signal derr3_stg_act_q :std_ulogic; +signal derr4_stg_act_d :std_ulogic; +signal derr4_stg_act_q :std_ulogic; +signal derr5_stg_act_d :std_ulogic; +signal derr5_stg_act_q :std_ulogic; +signal ex4_err_det_way_d :std_ulogic_vector(0 to 7); +signal ex4_err_det_way_q :std_ulogic_vector(0 to 7); +signal ex4_perr_lck_lost_d :std_ulogic; +signal ex4_perr_lck_lost_q :std_ulogic; +signal ex4_perr_watch_lost_d :std_ulogic_vector(0 to 3); +signal ex4_perr_watch_lost_q :std_ulogic_vector(0 to 3); +signal dcperr_lock_lost_d :std_ulogic; +signal dcperr_lock_lost_q :std_ulogic; +signal ex4_dir_multihit_val_b_q :std_ulogic; +signal ex4_dir_multihit_val :std_ulogic; +signal binv4_ex4_lock_set :std_ulogic; +signal binv4_ex4_thrd_watch :std_ulogic_vector(0 to 3); +signal ex4_multihit_watch_lost :std_ulogic_vector(0 to 3); +signal ex4_multihit_lock_lost :std_ulogic; +signal ex3_watch_chk_d :std_ulogic; +signal ex3_watch_chk_q :std_ulogic; +signal ex4_watch_chk_d :std_ulogic; +signal ex4_watch_chk_q :std_ulogic; +signal ex5_watch_chk_d :std_ulogic; +signal ex5_watch_chk_q :std_ulogic; +signal ex5_watch_chk_cplt :std_ulogic; +signal ex5_watch_chk_succ :std_ulogic; +signal ex5_watch_dup_set :std_ulogic; +signal hit_and_01_b :std_ulogic; +signal hit_and_23_b :std_ulogic; +signal hit_and_45_b :std_ulogic; +signal hit_and_67_b :std_ulogic; +signal hit_or_01_b :std_ulogic; +signal hit_or_23_b :std_ulogic; +signal hit_or_45_b :std_ulogic; +signal hit_or_67_b :std_ulogic; +signal hit_or_13_b :std_ulogic; +signal hit_or_57_b :std_ulogic; +signal hit_or_0123 :std_ulogic; +signal hit_or_4567 :std_ulogic; +signal hit_or_1357 :std_ulogic; +signal hit_or_2367 :std_ulogic; +signal hit_and_0123 :std_ulogic; +signal hit_and_4567 :std_ulogic; +signal multi_hit_err2_0 :std_ulogic; +signal multi_hit_err2_1 :std_ulogic; +signal hit_or_01234567_b :std_ulogic; +signal ex3_dir_multihit_val_0 :std_ulogic; +signal ex3_dir_multihit_val_1 :std_ulogic; +signal ex3_dir_multihit_val_b :std_ulogic; +signal multi_hit_err3_b :std_ulogic_vector(0 to 2); +signal hit_enc_b :std_ulogic_vector(0 to 2); +signal ex3_l_fld_b1_d :std_ulogic; +signal ex3_l_fld_b1_q :std_ulogic; +signal binv4_ex4_way_upd :std_ulogic_vector(0 to 7); +signal binv5_ex5_way_upd :std_ulogic_vector(0 to 7); +signal binv6_ex6_way_upd :std_ulogic_vector(0 to 7); +signal binv7_ex7_way_upd_d :std_ulogic_vector(0 to 7); +signal binv7_ex7_way_upd_q :std_ulogic_vector(0 to 7); +signal binv4_ex4_dir_data :std_ulogic_vector(1 to 5); +signal binv5_ex5_dir_data_d :std_ulogic_vector(1 to 5); +signal binv5_ex5_dir_data_q :std_ulogic_vector(1 to 5); +signal binv6_ex6_dir_data_d :std_ulogic_vector(1 to 5); +signal binv6_ex6_dir_data_q :std_ulogic_vector(1 to 5); +signal binv7_ex7_dir_data_d :std_ulogic_vector(1 to 5); +signal binv7_ex7_dir_data_q :std_ulogic_vector(1 to 5); +signal binv4_inval_lck :std_ulogic; +signal binv4_inval_watch :std_ulogic_vector(0 to 3); +signal binv4_coll_val :std_ulogic; +signal binv4_ex5_coll :std_ulogic; +signal binv4_ex6_coll :std_ulogic; +signal binv4_ex7_coll :std_ulogic; +signal binv4_pri_byp_sel :std_ulogic_vector(0 to 2); +signal binv4_byp_dir_data :std_ulogic_vector(1 to 5); +signal binv5_inval_lock_val_d :std_ulogic; +signal binv5_inval_lock_val_q :std_ulogic; +signal binv5_inval_watch_val_d :std_ulogic_vector(0 to 3); +signal binv5_inval_watch_val_q :std_ulogic_vector(0 to 3); +signal binv5_ex5_lost_watch_upd :std_ulogic_vector(0 to 3); +signal dci_watch_lost :std_ulogic_vector(0 to 3); +signal ex3_xuop_upd_dir :std_ulogic; +signal binv3_ex3_xuop_upd :std_ulogic; +signal binv4_ex4_xuop_upd_d :std_ulogic; +signal binv4_ex4_xuop_upd_q :std_ulogic; +signal ex3_dir_acc_val :std_ulogic; +signal binv3_ex3_dir_val :std_ulogic; +signal binv4_ex4_dir_val_d :std_ulogic; +signal binv4_ex4_dir_val_q :std_ulogic; +signal ex3_l1hit :std_ulogic; +signal ex3_l1miss :std_ulogic; +signal ex4_snd_ld_l2_q :std_ulogic; +signal ex4_ldq_full_flush_b_q :std_ulogic; +signal rel_in_prog_stg1_d :std_ulogic; +signal rel_in_prog_stg1_q :std_ulogic; +signal rel_in_prog_stg2_d :std_ulogic; +signal rel_in_prog_stg2_q :std_ulogic; +signal rel_in_prog_stg3_d :std_ulogic; +signal rel_in_prog_stg3_q :std_ulogic; +signal rel_in_prog_stg4_d :std_ulogic; +signal rel_in_prog_stg4_q :std_ulogic; +signal rel_in_prog_stg5_d :std_ulogic; +signal rel_in_prog_stg5_q :std_ulogic; +signal ex4_instr_enc_d :std_ulogic_vector(0 to 3); +signal ex4_instr_enc_q :std_ulogic_vector(0 to 3); +signal ex4_wclr_all_val_d :std_ulogic; +signal ex4_wclr_all_val_q :std_ulogic; +signal ex5_wclr_all_val_d :std_ulogic; +signal ex5_wclr_all_val_q :std_ulogic; +signal ex6_wclr_all_val_d :std_ulogic; +signal ex6_wclr_all_val_q :std_ulogic; +signal ex3_wclr_all_upd_val :std_ulogic; +signal ex4_wclr_all_upd_val :std_ulogic; +signal ex5_wclr_all_upd_val :std_ulogic; +signal ex6_wclr_all_upd_val :std_ulogic; +signal ex3_wclr_all_upd_d :std_ulogic; +signal ex3_wclr_all_upd_q :std_ulogic; +signal ex4_n_lsu_ddmh_flush_b_d :std_ulogic_vector(0 to 3); +signal ex4_n_lsu_ddmh_flush_b_q :std_ulogic_vector(0 to 3); +signal ex3_xuop_up_addr_b :std_ulogic_vector(0 to 2); +signal rel_dcarr_addr_sel :std_ulogic_vector(0 to 2); +signal rel_dcarr_addr_sel_b :std_ulogic_vector(0 to 2); +signal dcarr_up_way_addr_q :std_ulogic_vector(0 to 2); +signal rel4_l1dump_val_q :std_ulogic; +signal rel4_l1dump_watch :std_ulogic; +signal lost_watch_l1dump :std_ulogic_vector(0 to 3); +signal my_lclk :clk_logic; +signal my_d1clk :std_ulogic; +signal my_d2clk :std_ulogic; +signal my_multihit_lclk :clk_logic; +signal my_multihit_d1clk :std_ulogic; +signal my_multihit_d2clk :std_ulogic; +signal my_ddmh_lclk :clk_logic; +signal my_ddmh_d1clk :std_ulogic; +signal my_ddmh_d2clk :std_ulogic; +signal ex4_miss_siv :std_ulogic; +signal ex4_miss_sov :std_ulogic; +signal my_spare0_lclk :clk_logic; +signal my_spare0_d1clk :std_ulogic; +signal my_spare0_d2clk :std_ulogic; +signal my_spare0_latches_d :std_ulogic_vector(0 to 16); +signal my_spare0_latches_q :std_ulogic_vector(0 to 16); +signal my_spare1_lclk :clk_logic; +signal my_spare1_d1clk :std_ulogic; +signal my_spare1_d2clk :std_ulogic; +signal my_spare1_latches_d :std_ulogic_vector(0 to 15); +signal my_spare1_latches_q :std_ulogic_vector(0 to 15); +signal tiup :std_ulogic; +signal siv :std_ulogic_vector(0 to scan_right); +signal sov :std_ulogic_vector(0 to scan_right); + BEGIN --@@ START OF EXECUTABLE CODE FOR XUQ_LSU_DIR_VAL16 + +tiup <= '1'; +inv2_val_d <= inv1_val and not spr_xucr0_dcdis; +back_inval_stg2 <= inv2_val_q; +rel_val_stg1 <= rel1_val; +rel_val_stg3 <= rel3_val; +rel_set_val <= rel4_set_val; +lock_flash_clear_d <= xu_lsu_spr_xucr0_clfc; +lock_flash_clear_val_d <= lock_flash_clear_q; +dci_compl_d <= xu_lsu_dci; +dci_inval_all_d <= dci_compl_q; +lock_finval <= dci_inval_all_q or lock_flash_clear_val_q; +inj_dir_multihit_d <= pc_xu_inj_dcachedir_multihit; +ex3_l_fld_b1_d <= ex2_l_fld(1); +tagA_hit <= ex3_way_cmp_a; +rel_wayA_clr <= rel_way_clr_a; +rel_wayA_set <= rel_way_wen_a; +tagB_hit <= ex3_way_cmp_b; +rel_wayB_clr <= rel_way_clr_b; +rel_wayB_set <= rel_way_wen_b; +tagC_hit <= ex3_way_cmp_c; +rel_wayC_clr <= rel_way_clr_c; +rel_wayC_set <= rel_way_wen_c; +tagD_hit <= ex3_way_cmp_d; +rel_wayD_clr <= rel_way_clr_d; +rel_wayD_set <= rel_way_wen_d; +tagE_hit <= ex3_way_cmp_e; +rel_wayE_clr <= rel_way_clr_e; +rel_wayE_set <= rel_way_wen_e; +tagF_hit <= ex3_way_cmp_f; +rel_wayF_clr <= rel_way_clr_f; +rel_wayF_set <= rel_way_wen_f; +tagG_hit <= ex3_way_cmp_g; +rel_wayG_clr <= rel_way_clr_g; +rel_wayG_set <= rel_way_wen_g; +tagH_hit <= ex3_way_cmp_h; +rel_wayH_clr <= rel_way_clr_h; +rel_wayH_set <= rel_way_wen_h; +ex3_c_acc <= ex3_cache_en; +-- #################################################### +-- Stage ACT Pipes +-- #################################################### +binv1_ex1_stg_act <= binv1_stg_act or ex1_stg_act; +binv2_ex2_stg_act <= binv2_stg_act or ex2_stg_act; +binv3_ex3_stg_act <= binv3_stg_act or ex3_stg_act; +binv4_ex4_stg_act <= binv4_stg_act or ex4_stg_act; +binv5_ex5_stg_act <= binv5_stg_act or ex5_stg_act; +binv2_ex2_val_stg_act <= derr2_stg_act_q or binv2_stg_act or ex2_stg_act; +binv3_ex3_val_stg_act <= derr3_stg_act_q or binv3_stg_act or ex3_stg_act; +binv4_ex4_val_stg_act <= derr4_stg_act_q or binv4_stg_act or ex4_stg_act; +binv5_ex5_val_stg_act <= derr5_stg_act_q or binv5_stg_act or ex5_stg_act; +rel1_perr_stg_act <= rel1_stg_act or dcpar_err_stg1_act_q; +rel2_perr_stg_act <= rel2_stg_act or dcpar_err_stg2_act_q; +rel3_perr_stg_act_d <= rel2_perr_stg_act; +rel4_perr_stg_act_d <= rel3_perr_stg_act_q; +-- #################################################### +-- Dcache Number of Cachelines Configurations +-- #################################################### +-- EX2 Stage +ex1_congr_cl <= ex1_p_addr; +cl64size : if (cl_size=6) generate +begin + rel_early_congr_cl(3 TO 6) <= rel_addr_early(64-(dc_size-3) to 63-cl_size-1); +rel_early_congr_cl(7) <= rel_addr_early(63-cl_size) or spr_xucr0_cls; +end generate cl64size; +cl32size : if (cl_size=5) generate +begin + rel_early_congr_cl(3 TO 5) <= rel_addr_early(64-(dc_size-3) to 63-cl_size-2); +rel_early_congr_cl(6) <= rel_addr_early(63-cl_size-1) or spr_xucr0_cls; +rel_early_congr_cl(7) <= rel_addr_early(63-cl_size); +end generate cl32size; +-- #################################################### +-- Congruence Class Address Select +-- Port0 => Execution Pipe or Back-Invalidate +-- Port1 => Reload or DC Parity Error Recovery +-- #################################################### +-- Port0 +-- = '1' => Select Back-Invalidate +-- = '0' => Select Execution Op +ex2_congr_cl_d <= ex1_congr_cl; +ex3_congr_cl_d <= ex2_congr_cl_q; +ex4_congr_cl_d <= ex3_congr_cl_q; +ex5_congr_cl_d <= ex4_congr_cl_q; +ex6_congr_cl_d <= ex5_congr_cl_q; +-- Port1 +-- = '1' => Select DC Parity Error Recovery +-- = '0' => Select Reload +with rel_in_progress select + rel_congr_cl_d <= rel_early_congr_cl when '1', + dcpar_err_congr_cl when others; +-- Reload Invalidate Stages +rel_val_stg2_d <= rel_val_stg1; +rel_val_clr_d <= rel_val_stg2_q or dcpar_err_stg2_q; +-- Reload Validate Stages +rel_val_stg4_d <= rel_val_stg3; +rel_val_stg4 <= rel_val_stg4_q and not rel4_recirc_val; +rel_val_set <= rel_val_stg4 and rel_set_val; +-- Reload Back-Invalidated +rel_binv_stg4_d <= rel_back_inval; +-- Reload Lock Cache-Line +rel_lock_set_d <= rel_lock_en; +rel_l1dump_cslc_d <= rel_l1dump_cslc; +-- Reload Lost Lock due to Back-Invalidate of loadmissQ entry +rel_no_ovr_lock <= rel_wayA_set or rel_wayB_set or rel_wayC_set or rel_wayD_set or + rel_wayE_set or rel_wayF_set or rel_wayG_set or rel_wayH_set; +rel_lock_lost <= rel_lock_set_q and rel_val_stg4 and rel_no_ovr_lock and rel_binv_stg4_q and not rel_set_val; +-- Reload Watch Cache-Line +rel_watch_set_d <= rel_watch_en; +rel_thrd_id_d <= rel_thrd_id; +-- Reload Lost Watch due to Back-Invalidate of loadmissQ entry +rel_watch_lost <= gate(rel_thrd_id_q, (rel_watch_set_q and rel_val_stg4 and rel_binv_stg4_q and not rel_set_val)); +-- Reload Port is updated when a Reload is invalidating a line, a Reload is setting a line, or Parity Error Recovery +rel_val_stg24 <= rel_val_stg2_q or rel_val_set or dcpar_err_stg2_q; +rel_val_stgu_d <= rel_val_stg24; +rel_port_wren_d <= rel_val_stgu_q; +rel_port_upd_d <= rel_val_stgu_q; +rel_in_prog_stg1_d <= ldq_rel1_early_v or ldq_rel3_early_v; +rel_in_prog_stg2_d <= rel_in_prog_stg1_q; +rel_in_prog_stg3_d <= rel_in_prog_stg2_q; +rel_in_prog_stg4_d <= rel_in_prog_stg3_q; +rel_in_prog_stg5_d <= rel_in_prog_stg4_q; +-- Used to block Parity Recovery +rel_in_progress <= ldq_rel1_early_v or ldq_rel3_early_v or rel_in_prog_stg1_q or rel_in_prog_stg2_q or + rel_in_prog_stg3_q or rel_in_prog_stg4_q or rel_in_prog_stg5_q; +rel_in_progress_d <= rel_in_progress; +-- Back-Invalidate Stages +back_inval_stg3_d <= back_inval_stg2; +back_inval_stg4_d <= back_inval_stg3_q; +back_inval_stg5_d <= back_inval_stg4_q; +-- EX1 STAGE +ex2_thrd_id_d <= ex1_thrd_id; +-- EX2 STAGE +ex3_store_instr_d <= ex2_store_instr and not ex2_stg_flush; +ex3_flush_cline_d <= ex2_is_inval_op and not ex2_stg_flush; +ex3_lock_set_d <= ex2_lock_set and not ex2_stg_flush; +ex4_lock_set_d <= ex3_lock_set_q and not ex3_stg_flush; +ex5_lock_set_d <= ex4_lock_set_q and not ex4_stg_flush; +ex3_lock_clr_d <= ex2_lock_clr and not ex2_stg_flush; +ex3_thrd_id_d <= ex2_thrd_id_q; +ex3_watch_set_d <= ex2_ldawx_instr and not ex2_stg_flush; +ex3_watch_clr_d <= ex2_wclr_instr and not ex2_stg_flush; +ex2_watch_clr_all <= ex2_wclr_instr and not ex2_l_fld(0); +ex2_watch_clr_one <= ex2_wclr_instr and ex2_l_fld(0); +ex3_watch_clr_all_d <= ex2_watch_clr_all and not ex2_stg_flush; +ex3_watch_chk_d <= ex2_wchk_val and not ex2_stg_flush; +ex3_xuop_val_d <= (ex2_lock_clr or ex2_lock_set or ex2_ldawx_instr or ex2_watch_clr_one or ex2_store_instr) and not ex2_stg_flush; +-- EX3 STAGE +ex4_l_fld_b1_d <= ex3_l_fld_b1_q; +ex3_watch_clr_all <= gate(ex3_thrd_id_q, ex3_watch_clr_all_q); +ex4_wclr_all_val_d <= ex3_watch_clr_all_q and not ex3_stg_flush; +ex5_wclr_all_val_d <= ex4_wclr_all_val_q and not ex4_stg_flush; +ex6_wclr_all_val_d <= ex5_wclr_all_val_q and not ex5_stg_flush; +ex3_xuop_val <= ((ex3_xuop_val_q and ex3_c_acc) or ex3_flush_cline_q) and not spr_xucr0_dcdis; +ex4_xuop_val_d <= (ex3_xuop_val or ex3_watch_clr_all_q) and not ex3_stg_flush; +ex4_watch_clr_all_d <= gate(ex3_watch_clr_all, (not (ex3_stg_flush or spr_xucr0_dcdis))); +ex4_watch_chk_d <= ex3_watch_chk_q and not ex3_stg_flush; +ex4_watch_set_d <= ex3_watch_set_q and not ex3_stg_flush; +ex5_watch_set_d <= ex4_watch_set_q and not ex4_stg_flush; +ex3_xuop_upd_dir <= ex3_flush_cline_q or ex3_lock_clr_q or ex3_lock_set_q or ex3_watch_set_q or ex3_watch_clr_q; +binv3_ex3_xuop_upd <= back_inval_stg3_q or ex3_xuop_val; +binv4_ex4_xuop_upd_d <= binv3_ex3_xuop_upd or ((ex3_xuop_val or ex3_watch_clr_all_q) and not ex3_stg_flush); +ex3_dir_acc_val <= ex3_cache_acc and not ex3_watch_clr_all_q; +binv3_ex3_dir_val <= back_inval_stg3_q or ex3_dir_acc_val; +binv4_ex4_dir_val_d <= back_inval_stg3_q or (ex3_dir_acc_val and not ex3_stg_flush); +ex4_instr_enc_d(0) <= ex3_watch_clr_q; +ex4_instr_enc_d(1) <= back_inval_stg3_q or ex3_lock_set_q or ex3_lock_clr_q or ex3_watch_set_q; +ex4_instr_enc_d(2) <= back_inval_stg3_q or ex3_store_instr_q or ex3_watch_set_q; +ex4_instr_enc_d(3) <= back_inval_stg3_q or ex3_lock_clr_q or ex3_flush_cline_q or ex3_watch_clr_all_q; +-- EX4 STAGE +ex4_xuop_val <= ex4_xuop_val_q and not ex4_stg_flush; +ex4_thrd_id_d <= ex3_thrd_id_q; +-- EX5 STAGE +ex5_xuop_val_d <= ex4_xuop_val; +ex5_xuop_val <= ex5_xuop_val_q and not ex5_stg_flush; +ex5_xuop_p0_upd_d <= ex4_xuop_val; +ex5_watch_chk_d <= ex4_watch_chk_q and not ex4_stg_flush; +ex5_thrd_id_d <= ex4_thrd_id_q; +-- Reload Congruence Class +rel24_congr_cl_d <= rel_congr_cl_q; +relu_congr_cl_d <= rel24_congr_cl_q; +relu_s_congr_cl_d <= relu_congr_cl_q; +-- Load Hit Valid +ex6_ld_valid_d <= ex5_load_op_hit and not ex5_stg_flush; +-- #################################################### +-- Execution Directory Read +-- #################################################### +-- Execution Path Directory Valid and Line Lock Bits Muxing +-- Select Congruence Class Way A +with ex2_congr_cl_q select + arr_wayA_val <= + congr_cl0_wA_q when "00000", + congr_cl1_wA_q when "00001", + congr_cl2_wA_q when "00010", + congr_cl3_wA_q when "00011", + congr_cl4_wA_q when "00100", + congr_cl5_wA_q when "00101", + congr_cl6_wA_q when "00110", + congr_cl7_wA_q when "00111", + congr_cl8_wA_q when "01000", + congr_cl9_wA_q when "01001", + congr_cl10_wA_q when "01010", + congr_cl11_wA_q when "01011", + congr_cl12_wA_q when "01100", + congr_cl13_wA_q when "01101", + congr_cl14_wA_q when "01110", + congr_cl15_wA_q when "01111", + congr_cl16_wA_q when "10000", + congr_cl17_wA_q when "10001", + congr_cl18_wA_q when "10010", + congr_cl19_wA_q when "10011", + congr_cl20_wA_q when "10100", + congr_cl21_wA_q when "10101", + congr_cl22_wA_q when "10110", + congr_cl23_wA_q when "10111", + congr_cl24_wA_q when "11000", + congr_cl25_wA_q when "11001", + congr_cl26_wA_q when "11010", + congr_cl27_wA_q when "11011", + congr_cl28_wA_q when "11100", + congr_cl29_wA_q when "11101", + congr_cl30_wA_q when "11110", + congr_cl31_wA_q when others; +p0_arr_wayA_rd <= arr_wayA_val; +-- Select Congruence Class Way B +with ex2_congr_cl_q select + arr_wayB_val <= + congr_cl0_wB_q when "00000", + congr_cl1_wB_q when "00001", + congr_cl2_wB_q when "00010", + congr_cl3_wB_q when "00011", + congr_cl4_wB_q when "00100", + congr_cl5_wB_q when "00101", + congr_cl6_wB_q when "00110", + congr_cl7_wB_q when "00111", + congr_cl8_wB_q when "01000", + congr_cl9_wB_q when "01001", + congr_cl10_wB_q when "01010", + congr_cl11_wB_q when "01011", + congr_cl12_wB_q when "01100", + congr_cl13_wB_q when "01101", + congr_cl14_wB_q when "01110", + congr_cl15_wB_q when "01111", + congr_cl16_wB_q when "10000", + congr_cl17_wB_q when "10001", + congr_cl18_wB_q when "10010", + congr_cl19_wB_q when "10011", + congr_cl20_wB_q when "10100", + congr_cl21_wB_q when "10101", + congr_cl22_wB_q when "10110", + congr_cl23_wB_q when "10111", + congr_cl24_wB_q when "11000", + congr_cl25_wB_q when "11001", + congr_cl26_wB_q when "11010", + congr_cl27_wB_q when "11011", + congr_cl28_wB_q when "11100", + congr_cl29_wB_q when "11101", + congr_cl30_wB_q when "11110", + congr_cl31_wB_q when others; +p0_arr_wayB_rd <= arr_wayB_val; +-- Select Congruence Class Way C +with ex2_congr_cl_q select + arr_wayC_val <= + congr_cl0_wC_q when "00000", + congr_cl1_wC_q when "00001", + congr_cl2_wC_q when "00010", + congr_cl3_wC_q when "00011", + congr_cl4_wC_q when "00100", + congr_cl5_wC_q when "00101", + congr_cl6_wC_q when "00110", + congr_cl7_wC_q when "00111", + congr_cl8_wC_q when "01000", + congr_cl9_wC_q when "01001", + congr_cl10_wC_q when "01010", + congr_cl11_wC_q when "01011", + congr_cl12_wC_q when "01100", + congr_cl13_wC_q when "01101", + congr_cl14_wC_q when "01110", + congr_cl15_wC_q when "01111", + congr_cl16_wC_q when "10000", + congr_cl17_wC_q when "10001", + congr_cl18_wC_q when "10010", + congr_cl19_wC_q when "10011", + congr_cl20_wC_q when "10100", + congr_cl21_wC_q when "10101", + congr_cl22_wC_q when "10110", + congr_cl23_wC_q when "10111", + congr_cl24_wC_q when "11000", + congr_cl25_wC_q when "11001", + congr_cl26_wC_q when "11010", + congr_cl27_wC_q when "11011", + congr_cl28_wC_q when "11100", + congr_cl29_wC_q when "11101", + congr_cl30_wC_q when "11110", + congr_cl31_wC_q when others; +p0_arr_wayC_rd <= arr_wayC_val; +-- Select Congruence Class Way D +with ex2_congr_cl_q select + arr_wayD_val <= + congr_cl0_wD_q when "00000", + congr_cl1_wD_q when "00001", + congr_cl2_wD_q when "00010", + congr_cl3_wD_q when "00011", + congr_cl4_wD_q when "00100", + congr_cl5_wD_q when "00101", + congr_cl6_wD_q when "00110", + congr_cl7_wD_q when "00111", + congr_cl8_wD_q when "01000", + congr_cl9_wD_q when "01001", + congr_cl10_wD_q when "01010", + congr_cl11_wD_q when "01011", + congr_cl12_wD_q when "01100", + congr_cl13_wD_q when "01101", + congr_cl14_wD_q when "01110", + congr_cl15_wD_q when "01111", + congr_cl16_wD_q when "10000", + congr_cl17_wD_q when "10001", + congr_cl18_wD_q when "10010", + congr_cl19_wD_q when "10011", + congr_cl20_wD_q when "10100", + congr_cl21_wD_q when "10101", + congr_cl22_wD_q when "10110", + congr_cl23_wD_q when "10111", + congr_cl24_wD_q when "11000", + congr_cl25_wD_q when "11001", + congr_cl26_wD_q when "11010", + congr_cl27_wD_q when "11011", + congr_cl28_wD_q when "11100", + congr_cl29_wD_q when "11101", + congr_cl30_wD_q when "11110", + congr_cl31_wD_q when others; +p0_arr_wayD_rd <= arr_wayD_val; +-- Select Congruence Class Way E +with ex2_congr_cl_q select + arr_wayE_val <= + congr_cl0_wE_q when "00000", + congr_cl1_wE_q when "00001", + congr_cl2_wE_q when "00010", + congr_cl3_wE_q when "00011", + congr_cl4_wE_q when "00100", + congr_cl5_wE_q when "00101", + congr_cl6_wE_q when "00110", + congr_cl7_wE_q when "00111", + congr_cl8_wE_q when "01000", + congr_cl9_wE_q when "01001", + congr_cl10_wE_q when "01010", + congr_cl11_wE_q when "01011", + congr_cl12_wE_q when "01100", + congr_cl13_wE_q when "01101", + congr_cl14_wE_q when "01110", + congr_cl15_wE_q when "01111", + congr_cl16_wE_q when "10000", + congr_cl17_wE_q when "10001", + congr_cl18_wE_q when "10010", + congr_cl19_wE_q when "10011", + congr_cl20_wE_q when "10100", + congr_cl21_wE_q when "10101", + congr_cl22_wE_q when "10110", + congr_cl23_wE_q when "10111", + congr_cl24_wE_q when "11000", + congr_cl25_wE_q when "11001", + congr_cl26_wE_q when "11010", + congr_cl27_wE_q when "11011", + congr_cl28_wE_q when "11100", + congr_cl29_wE_q when "11101", + congr_cl30_wE_q when "11110", + congr_cl31_wE_q when others; +p0_arr_wayE_rd <= arr_wayE_val; +-- Select Congruence Class Way F +with ex2_congr_cl_q select + arr_wayF_val <= + congr_cl0_wF_q when "00000", + congr_cl1_wF_q when "00001", + congr_cl2_wF_q when "00010", + congr_cl3_wF_q when "00011", + congr_cl4_wF_q when "00100", + congr_cl5_wF_q when "00101", + congr_cl6_wF_q when "00110", + congr_cl7_wF_q when "00111", + congr_cl8_wF_q when "01000", + congr_cl9_wF_q when "01001", + congr_cl10_wF_q when "01010", + congr_cl11_wF_q when "01011", + congr_cl12_wF_q when "01100", + congr_cl13_wF_q when "01101", + congr_cl14_wF_q when "01110", + congr_cl15_wF_q when "01111", + congr_cl16_wF_q when "10000", + congr_cl17_wF_q when "10001", + congr_cl18_wF_q when "10010", + congr_cl19_wF_q when "10011", + congr_cl20_wF_q when "10100", + congr_cl21_wF_q when "10101", + congr_cl22_wF_q when "10110", + congr_cl23_wF_q when "10111", + congr_cl24_wF_q when "11000", + congr_cl25_wF_q when "11001", + congr_cl26_wF_q when "11010", + congr_cl27_wF_q when "11011", + congr_cl28_wF_q when "11100", + congr_cl29_wF_q when "11101", + congr_cl30_wF_q when "11110", + congr_cl31_wF_q when others; +p0_arr_wayF_rd <= arr_wayF_val; +-- Select Congruence Class Way G +with ex2_congr_cl_q select + arr_wayG_val <= + congr_cl0_wG_q when "00000", + congr_cl1_wG_q when "00001", + congr_cl2_wG_q when "00010", + congr_cl3_wG_q when "00011", + congr_cl4_wG_q when "00100", + congr_cl5_wG_q when "00101", + congr_cl6_wG_q when "00110", + congr_cl7_wG_q when "00111", + congr_cl8_wG_q when "01000", + congr_cl9_wG_q when "01001", + congr_cl10_wG_q when "01010", + congr_cl11_wG_q when "01011", + congr_cl12_wG_q when "01100", + congr_cl13_wG_q when "01101", + congr_cl14_wG_q when "01110", + congr_cl15_wG_q when "01111", + congr_cl16_wG_q when "10000", + congr_cl17_wG_q when "10001", + congr_cl18_wG_q when "10010", + congr_cl19_wG_q when "10011", + congr_cl20_wG_q when "10100", + congr_cl21_wG_q when "10101", + congr_cl22_wG_q when "10110", + congr_cl23_wG_q when "10111", + congr_cl24_wG_q when "11000", + congr_cl25_wG_q when "11001", + congr_cl26_wG_q when "11010", + congr_cl27_wG_q when "11011", + congr_cl28_wG_q when "11100", + congr_cl29_wG_q when "11101", + congr_cl30_wG_q when "11110", + congr_cl31_wG_q when others; +p0_arr_wayG_rd <= arr_wayG_val; +-- Select Congruence Class Way H +with ex2_congr_cl_q select + arr_wayH_val <= + congr_cl0_wH_q when "00000", + congr_cl1_wH_q when "00001", + congr_cl2_wH_q when "00010", + congr_cl3_wH_q when "00011", + congr_cl4_wH_q when "00100", + congr_cl5_wH_q when "00101", + congr_cl6_wH_q when "00110", + congr_cl7_wH_q when "00111", + congr_cl8_wH_q when "01000", + congr_cl9_wH_q when "01001", + congr_cl10_wH_q when "01010", + congr_cl11_wH_q when "01011", + congr_cl12_wH_q when "01100", + congr_cl13_wH_q when "01101", + congr_cl14_wH_q when "01110", + congr_cl15_wH_q when "01111", + congr_cl16_wH_q when "10000", + congr_cl17_wH_q when "10001", + congr_cl18_wH_q when "10010", + congr_cl19_wH_q when "10011", + congr_cl20_wH_q when "10100", + congr_cl21_wH_q when "10101", + congr_cl22_wH_q when "10110", + congr_cl23_wH_q when "10111", + congr_cl24_wH_q when "11000", + congr_cl25_wH_q when "11001", + congr_cl26_wH_q when "11010", + congr_cl27_wH_q when "11011", + congr_cl28_wH_q when "11100", + congr_cl29_wH_q when "11101", + congr_cl30_wH_q when "11110", + congr_cl31_wH_q when others; +p0_arr_wayH_rd <= arr_wayH_val; +-- #################################################### +-- Execution/Back-Invalidate Pipe Bypass +-- #################################################### +-- Determine if there is any updates in later stages to the same congruence class +congr_cl_ex2_ex3_cmp_d <= (ex1_congr_cl = ex2_congr_cl_q); +congr_cl_ex2_ex4_cmp_d <= (ex1_congr_cl = ex3_congr_cl_q); +congr_cl_ex2_ex5_cmp_d <= (ex1_congr_cl = ex4_congr_cl_q); +congr_cl_ex2_ex6_cmp_d <= (ex1_congr_cl = ex5_congr_cl_q); +congr_cl_ex2_relu_cmp_d <= (ex1_congr_cl = rel24_congr_cl_q); +congr_cl_ex2_relu_s_cmp_d <= (ex1_congr_cl = relu_congr_cl_q); +congr_cl_ex2_rel_upd_cmp_d <= (ex1_congr_cl = relu_s_congr_cl_q); +congr_cl_ex2_p0_cmp <= congr_cl_ex2_ex6_cmp_q and p0_wren_cpy_q; +congr_cl_ex2_p1_cmp <= congr_cl_ex2_rel_upd_cmp_q and p1_wren_cpy_q; +-- Determine Bypass from later stages +ex3_thrd_m_d <= (ex1_thrd_id = ex2_thrd_id_q); +ex4_thrd_m_d <= (ex1_thrd_id = ex3_thrd_id_q); +ex5_thrd_m_d <= (ex1_thrd_id = ex4_thrd_id_q); +ex6_thrd_m_d <= (ex1_thrd_id = ex5_thrd_id_q); +congr_cl_ex2_ex3_m <= congr_cl_ex2_ex3_cmp_q and ((ex3_xuop_val and ex3_thrd_m_q) or back_inval_stg3_q) and not inv2_val_q; +congr_cl_ex2_ex4_m <= congr_cl_ex2_ex4_cmp_q and ((ex4_xuop_val_q and ex4_thrd_m_q) or back_inval_stg4_q) and not inv2_val_q; +congr_cl_ex2_ex5_m <= congr_cl_ex2_ex5_cmp_q and ((ex5_xuop_p0_upd_q and ex5_thrd_m_q) or back_inval_stg5_q) and not inv2_val_q; +congr_cl_ex2_relu_m <= congr_cl_ex2_relu_cmp_q and rel_val_stgu_q; +congr_cl_ex2_relu_s_m <= congr_cl_ex2_relu_s_cmp_q and p1_upd_val; +-- WayA Bypass Calculation +congr_cl_ex2_wayA_byp(1) <= congr_cl_ex2_ex3_m and ex3_wayA_hit; +congr_cl_ex2_wayA_byp(2) <= congr_cl_ex2_relu_m and reload_wayA_upd_q; +congr_cl_ex2_wayA_byp(3) <= congr_cl_ex2_ex4_m and binv_wayA_upd_q; +congr_cl_ex2_wayA_byp(4) <= congr_cl_ex2_relu_s_m and reload_wayA_upd2_q; +congr_cl_ex2_wayA_byp(5) <= congr_cl_ex2_ex5_m and binv_wayA_upd2_q; +congr_cl_ex2_wayA_byp(6) <= congr_cl_ex2_p1_cmp and reload_wayA_upd3_q; +congr_cl_ex2_wayA_byp(7) <= congr_cl_ex2_p0_cmp and binv_wayA_upd3_q; +-- WayA Bypass Valid +ex3_wayA_fxubyp_val_d <= congr_cl_ex2_wayA_byp(1) or congr_cl_ex2_wayA_byp(3) or + congr_cl_ex2_wayA_byp(5) or congr_cl_ex2_wayA_byp(7); +ex3_wayA_relbyp_val_d <= congr_cl_ex2_wayA_byp(2) or congr_cl_ex2_wayA_byp(4) or + congr_cl_ex2_wayA_byp(6); +ex4_wayA_fxubyp_val_d <= ex3_wayA_fxubyp_val_q; +ex4_wayA_relbyp_val_d <= ex3_wayA_relbyp_val_q; +ex4_wayA_byp_sel <= ex4_wayA_fxubyp_val_q & ex4_wayA_relbyp_val_q; +-- Late Stages Priority Selection +congr_cl_ex2_wayA_sel(2) <= congr_cl_ex2_wayA_byp(2); +congr_cl_ex2_wayA_sel(3) <= congr_cl_ex2_wayA_byp(3) and not congr_cl_ex2_wayA_byp(2); +congr_cl_ex2_wayA_sel(4) <= congr_cl_ex2_wayA_byp(4) and not or_reduce(congr_cl_ex2_wayA_byp(2 to 3)); +congr_cl_ex2_wayA_sel(5) <= congr_cl_ex2_wayA_byp(5) and not or_reduce(congr_cl_ex2_wayA_byp(2 to 4)); +congr_cl_ex2_wayA_sel(6) <= congr_cl_ex2_wayA_byp(6) and not or_reduce(congr_cl_ex2_wayA_byp(2 to 5)); +congr_cl_ex2_wayA_sel(7) <= congr_cl_ex2_wayA_byp(7) and not or_reduce(congr_cl_ex2_wayA_byp(2 to 6)); +-- ArrayRead/LATE Stage Priority Selection +wayA_late_sel <= or_reduce(congr_cl_ex2_wayA_byp(2 to 7)); +wayA_later_stg_pri <= gate(p0_arr_wayA_rd, not wayA_late_sel) or + gate(reload_wayA_q, congr_cl_ex2_wayA_sel(2)) or + gate(flush_wayA_q, congr_cl_ex2_wayA_sel(3)) or + gate(reload_wayA_data_q, congr_cl_ex2_wayA_sel(4)) or + gate(flush_wayA_data_q, congr_cl_ex2_wayA_sel(5)) or + gate(reload_wayA_data2_q, congr_cl_ex2_wayA_sel(6)) or + gate(flush_wayA_data2_q, congr_cl_ex2_wayA_sel(7)); +-- EX3/RELU Stage Priority Selection +wayA_early_sel <= congr_cl_ex2_wayA_byp(1); +wayA_early_stg_pri <= flush_wayA_d; +-- Stage/ARRAY Priority Selection +wayA_stg_val <= (others=>(wayA_early_sel)); +wayA_stg_val_b <= (others=>(not(wayA_early_sel))); +wayA_val(0 TO 1) <= not wayA_val_b_q(0 to 1); +wayA_val(2 TO 5) <= not wayA_val_b_q(2 to 5); +wayA_val_b1 <= not wayA_val(0); +-- WayB Bypass Calculation +congr_cl_ex2_wayB_byp(1) <= congr_cl_ex2_ex3_m and ex3_wayB_hit; +congr_cl_ex2_wayB_byp(2) <= congr_cl_ex2_relu_m and reload_wayB_upd_q; +congr_cl_ex2_wayB_byp(3) <= congr_cl_ex2_ex4_m and binv_wayB_upd_q; +congr_cl_ex2_wayB_byp(4) <= congr_cl_ex2_relu_s_m and reload_wayB_upd2_q; +congr_cl_ex2_wayB_byp(5) <= congr_cl_ex2_ex5_m and binv_wayB_upd2_q; +congr_cl_ex2_wayB_byp(6) <= congr_cl_ex2_p1_cmp and reload_wayB_upd3_q; +congr_cl_ex2_wayB_byp(7) <= congr_cl_ex2_p0_cmp and binv_wayB_upd3_q; +-- WayB Bypass Valid +ex3_wayB_fxubyp_val_d <= congr_cl_ex2_wayB_byp(1) or congr_cl_ex2_wayB_byp(3) or + congr_cl_ex2_wayB_byp(5) or congr_cl_ex2_wayB_byp(7); +ex3_wayB_relbyp_val_d <= congr_cl_ex2_wayB_byp(2) or congr_cl_ex2_wayB_byp(4) or + congr_cl_ex2_wayB_byp(6); +ex4_wayB_fxubyp_val_d <= ex3_wayB_fxubyp_val_q; +ex4_wayB_relbyp_val_d <= ex3_wayB_relbyp_val_q; +ex4_wayB_byp_sel <= ex4_wayB_fxubyp_val_q & ex4_wayB_relbyp_val_q; +-- Late Stages Priority Selection +congr_cl_ex2_wayB_sel(2) <= congr_cl_ex2_wayB_byp(2); +congr_cl_ex2_wayB_sel(3) <= congr_cl_ex2_wayB_byp(3) and not congr_cl_ex2_wayB_byp(2); +congr_cl_ex2_wayB_sel(4) <= congr_cl_ex2_wayB_byp(4) and not or_reduce(congr_cl_ex2_wayB_byp(2 to 3)); +congr_cl_ex2_wayB_sel(5) <= congr_cl_ex2_wayB_byp(5) and not or_reduce(congr_cl_ex2_wayB_byp(2 to 4)); +congr_cl_ex2_wayB_sel(6) <= congr_cl_ex2_wayB_byp(6) and not or_reduce(congr_cl_ex2_wayB_byp(2 to 5)); +congr_cl_ex2_wayB_sel(7) <= congr_cl_ex2_wayB_byp(7) and not or_reduce(congr_cl_ex2_wayB_byp(2 to 6)); +-- ArrayRead/LATE Stage Priority Selection +wayB_late_sel <= or_reduce(congr_cl_ex2_wayB_byp(2 to 7)); +wayB_later_stg_pri <= gate(p0_arr_wayB_rd, not wayB_late_sel) or + gate(reload_wayB_q, congr_cl_ex2_wayB_sel(2)) or + gate(flush_wayB_q, congr_cl_ex2_wayB_sel(3)) or + gate(reload_wayB_data_q, congr_cl_ex2_wayB_sel(4)) or + gate(flush_wayB_data_q, congr_cl_ex2_wayB_sel(5)) or + gate(reload_wayB_data2_q, congr_cl_ex2_wayB_sel(6)) or + gate(flush_wayB_data2_q, congr_cl_ex2_wayB_sel(7)); +-- EX3/RELU Stage Priority Selection +wayB_early_sel <= congr_cl_ex2_wayB_byp(1); +wayB_early_stg_pri <= flush_wayB_d; +-- Stage/ARRAY Priority Selection +wayB_stg_val <= (others=>(wayB_early_sel)); +wayB_stg_val_b <= (others=>(not(wayB_early_sel))); +wayB_val(0 TO 1) <= not wayB_val_b_q(0 to 1); +wayB_val(2 TO 5) <= not wayB_val_b_q(2 to 5); +wayB_val_b1 <= not wayB_val(0); +-- WayC Bypass Calculation +congr_cl_ex2_wayC_byp(1) <= congr_cl_ex2_ex3_m and ex3_wayC_hit; +congr_cl_ex2_wayC_byp(2) <= congr_cl_ex2_relu_m and reload_wayC_upd_q; +congr_cl_ex2_wayC_byp(3) <= congr_cl_ex2_ex4_m and binv_wayC_upd_q; +congr_cl_ex2_wayC_byp(4) <= congr_cl_ex2_relu_s_m and reload_wayC_upd2_q; +congr_cl_ex2_wayC_byp(5) <= congr_cl_ex2_ex5_m and binv_wayC_upd2_q; +congr_cl_ex2_wayC_byp(6) <= congr_cl_ex2_p1_cmp and reload_wayC_upd3_q; +congr_cl_ex2_wayC_byp(7) <= congr_cl_ex2_p0_cmp and binv_wayC_upd3_q; +-- WayC Bypass Valid +ex3_wayC_fxubyp_val_d <= congr_cl_ex2_wayC_byp(1) or congr_cl_ex2_wayC_byp(3) or + congr_cl_ex2_wayC_byp(5) or congr_cl_ex2_wayC_byp(7); +ex3_wayC_relbyp_val_d <= congr_cl_ex2_wayC_byp(2) or congr_cl_ex2_wayC_byp(4) or + congr_cl_ex2_wayC_byp(6); +ex4_wayC_fxubyp_val_d <= ex3_wayC_fxubyp_val_q; +ex4_wayC_relbyp_val_d <= ex3_wayC_relbyp_val_q; +ex4_wayC_byp_sel <= ex4_wayC_fxubyp_val_q & ex4_wayC_relbyp_val_q; +-- Late Stages Priority Selection +congr_cl_ex2_wayC_sel(2) <= congr_cl_ex2_wayC_byp(2); +congr_cl_ex2_wayC_sel(3) <= congr_cl_ex2_wayC_byp(3) and not congr_cl_ex2_wayC_byp(2); +congr_cl_ex2_wayC_sel(4) <= congr_cl_ex2_wayC_byp(4) and not or_reduce(congr_cl_ex2_wayC_byp(2 to 3)); +congr_cl_ex2_wayC_sel(5) <= congr_cl_ex2_wayC_byp(5) and not or_reduce(congr_cl_ex2_wayC_byp(2 to 4)); +congr_cl_ex2_wayC_sel(6) <= congr_cl_ex2_wayC_byp(6) and not or_reduce(congr_cl_ex2_wayC_byp(2 to 5)); +congr_cl_ex2_wayC_sel(7) <= congr_cl_ex2_wayC_byp(7) and not or_reduce(congr_cl_ex2_wayC_byp(2 to 6)); +-- ArrayRead/LATE Stage Priority Selection +wayC_late_sel <= or_reduce(congr_cl_ex2_wayC_byp(2 to 7)); +wayC_later_stg_pri <= gate(p0_arr_wayC_rd, not wayC_late_sel) or + gate(reload_wayC_q, congr_cl_ex2_wayC_sel(2)) or + gate(flush_wayC_q, congr_cl_ex2_wayC_sel(3)) or + gate(reload_wayC_data_q, congr_cl_ex2_wayC_sel(4)) or + gate(flush_wayC_data_q, congr_cl_ex2_wayC_sel(5)) or + gate(reload_wayC_data2_q, congr_cl_ex2_wayC_sel(6)) or + gate(flush_wayC_data2_q, congr_cl_ex2_wayC_sel(7)); +-- EX3/RELU Stage Priority Selection +wayC_early_sel <= congr_cl_ex2_wayC_byp(1); +wayC_early_stg_pri <= flush_wayC_d; +-- Stage/ARRAY Priority Selection +wayC_stg_val <= (others=>(wayC_early_sel)); +wayC_stg_val_b <= (others=>(not(wayC_early_sel))); +wayC_val(0 TO 1) <= not wayC_val_b_q(0 to 1); +wayC_val(2 TO 5) <= not wayC_val_b_q(2 to 5); +wayC_val_b1 <= not wayC_val(0); +-- WayD Bypass Calculation +congr_cl_ex2_wayD_byp(1) <= congr_cl_ex2_ex3_m and ex3_wayD_hit; +congr_cl_ex2_wayD_byp(2) <= congr_cl_ex2_relu_m and reload_wayD_upd_q; +congr_cl_ex2_wayD_byp(3) <= congr_cl_ex2_ex4_m and binv_wayD_upd_q; +congr_cl_ex2_wayD_byp(4) <= congr_cl_ex2_relu_s_m and reload_wayD_upd2_q; +congr_cl_ex2_wayD_byp(5) <= congr_cl_ex2_ex5_m and binv_wayD_upd2_q; +congr_cl_ex2_wayD_byp(6) <= congr_cl_ex2_p1_cmp and reload_wayD_upd3_q; +congr_cl_ex2_wayD_byp(7) <= congr_cl_ex2_p0_cmp and binv_wayD_upd3_q; +-- WayD Bypass Valid +ex3_wayD_fxubyp_val_d <= congr_cl_ex2_wayD_byp(1) or congr_cl_ex2_wayD_byp(3) or + congr_cl_ex2_wayD_byp(5) or congr_cl_ex2_wayD_byp(7); +ex3_wayD_relbyp_val_d <= congr_cl_ex2_wayD_byp(2) or congr_cl_ex2_wayD_byp(4) or + congr_cl_ex2_wayD_byp(6); +ex4_wayD_fxubyp_val_d <= ex3_wayD_fxubyp_val_q; +ex4_wayD_relbyp_val_d <= ex3_wayD_relbyp_val_q; +ex4_wayD_byp_sel <= ex4_wayD_fxubyp_val_q & ex4_wayD_relbyp_val_q; +-- Late Stages Priority Selection +congr_cl_ex2_wayD_sel(2) <= congr_cl_ex2_wayD_byp(2); +congr_cl_ex2_wayD_sel(3) <= congr_cl_ex2_wayD_byp(3) and not congr_cl_ex2_wayD_byp(2); +congr_cl_ex2_wayD_sel(4) <= congr_cl_ex2_wayD_byp(4) and not or_reduce(congr_cl_ex2_wayD_byp(2 to 3)); +congr_cl_ex2_wayD_sel(5) <= congr_cl_ex2_wayD_byp(5) and not or_reduce(congr_cl_ex2_wayD_byp(2 to 4)); +congr_cl_ex2_wayD_sel(6) <= congr_cl_ex2_wayD_byp(6) and not or_reduce(congr_cl_ex2_wayD_byp(2 to 5)); +congr_cl_ex2_wayD_sel(7) <= congr_cl_ex2_wayD_byp(7) and not or_reduce(congr_cl_ex2_wayD_byp(2 to 6)); +-- ArrayRead/LATE Stage Priority Selection +wayD_late_sel <= or_reduce(congr_cl_ex2_wayD_byp(2 to 7)); +wayD_later_stg_pri <= gate(p0_arr_wayD_rd, not wayD_late_sel) or + gate(reload_wayD_q, congr_cl_ex2_wayD_sel(2)) or + gate(flush_wayD_q, congr_cl_ex2_wayD_sel(3)) or + gate(reload_wayD_data_q, congr_cl_ex2_wayD_sel(4)) or + gate(flush_wayD_data_q, congr_cl_ex2_wayD_sel(5)) or + gate(reload_wayD_data2_q, congr_cl_ex2_wayD_sel(6)) or + gate(flush_wayD_data2_q, congr_cl_ex2_wayD_sel(7)); +-- EX3/RELU Stage Priority Selection +wayD_early_sel <= congr_cl_ex2_wayD_byp(1); +wayD_early_stg_pri <= flush_wayD_d; +-- Stage/ARRAY Priority Selection +wayD_stg_val <= (others=>(wayD_early_sel)); +wayD_stg_val_b <= (others=>(not(wayD_early_sel))); +wayD_val(0 TO 1) <= not wayD_val_b_q(0 to 1); +wayD_val(2 TO 5) <= not wayD_val_b_q(2 to 5); +wayD_val_b1 <= not wayD_val(0); +-- WayE Bypass Calculation +congr_cl_ex2_wayE_byp(1) <= congr_cl_ex2_ex3_m and ex3_wayE_hit; +congr_cl_ex2_wayE_byp(2) <= congr_cl_ex2_relu_m and reload_wayE_upd_q; +congr_cl_ex2_wayE_byp(3) <= congr_cl_ex2_ex4_m and binv_wayE_upd_q; +congr_cl_ex2_wayE_byp(4) <= congr_cl_ex2_relu_s_m and reload_wayE_upd2_q; +congr_cl_ex2_wayE_byp(5) <= congr_cl_ex2_ex5_m and binv_wayE_upd2_q; +congr_cl_ex2_wayE_byp(6) <= congr_cl_ex2_p1_cmp and reload_wayE_upd3_q; +congr_cl_ex2_wayE_byp(7) <= congr_cl_ex2_p0_cmp and binv_wayE_upd3_q; +-- WayE Bypass Valid +ex3_wayE_fxubyp_val_d <= congr_cl_ex2_wayE_byp(1) or congr_cl_ex2_wayE_byp(3) or + congr_cl_ex2_wayE_byp(5) or congr_cl_ex2_wayE_byp(7); +ex3_wayE_relbyp_val_d <= congr_cl_ex2_wayE_byp(2) or congr_cl_ex2_wayE_byp(4) or + congr_cl_ex2_wayE_byp(6); +ex4_wayE_fxubyp_val_d <= ex3_wayE_fxubyp_val_q; +ex4_wayE_relbyp_val_d <= ex3_wayE_relbyp_val_q; +ex4_wayE_byp_sel <= ex4_wayE_fxubyp_val_q & ex4_wayE_relbyp_val_q; +-- Late Stages Priority Selection +congr_cl_ex2_wayE_sel(2) <= congr_cl_ex2_wayE_byp(2); +congr_cl_ex2_wayE_sel(3) <= congr_cl_ex2_wayE_byp(3) and not congr_cl_ex2_wayE_byp(2); +congr_cl_ex2_wayE_sel(4) <= congr_cl_ex2_wayE_byp(4) and not or_reduce(congr_cl_ex2_wayE_byp(2 to 3)); +congr_cl_ex2_wayE_sel(5) <= congr_cl_ex2_wayE_byp(5) and not or_reduce(congr_cl_ex2_wayE_byp(2 to 4)); +congr_cl_ex2_wayE_sel(6) <= congr_cl_ex2_wayE_byp(6) and not or_reduce(congr_cl_ex2_wayE_byp(2 to 5)); +congr_cl_ex2_wayE_sel(7) <= congr_cl_ex2_wayE_byp(7) and not or_reduce(congr_cl_ex2_wayE_byp(2 to 6)); +-- ArrayRead/LATE Stage Priority Selection +wayE_late_sel <= or_reduce(congr_cl_ex2_wayE_byp(2 to 7)); +wayE_later_stg_pri <= gate(p0_arr_wayE_rd, not wayE_late_sel) or + gate(reload_wayE_q, congr_cl_ex2_wayE_sel(2)) or + gate(flush_wayE_q, congr_cl_ex2_wayE_sel(3)) or + gate(reload_wayE_data_q, congr_cl_ex2_wayE_sel(4)) or + gate(flush_wayE_data_q, congr_cl_ex2_wayE_sel(5)) or + gate(reload_wayE_data2_q, congr_cl_ex2_wayE_sel(6)) or + gate(flush_wayE_data2_q, congr_cl_ex2_wayE_sel(7)); +-- EX3/RELU Stage Priority Selection +wayE_early_sel <= congr_cl_ex2_wayE_byp(1); +wayE_early_stg_pri <= flush_wayE_d; +-- Stage/ARRAY Priority Selection +wayE_stg_val <= (others=>(wayE_early_sel)); +wayE_stg_val_b <= (others=>(not(wayE_early_sel))); +wayE_val(0 TO 1) <= not wayE_val_b_q(0 to 1); +wayE_val(2 TO 5) <= not wayE_val_b_q(2 to 5); +wayE_val_b1 <= not wayE_val(0); +-- WayF Bypass Calculation +congr_cl_ex2_wayF_byp(1) <= congr_cl_ex2_ex3_m and ex3_wayF_hit; +congr_cl_ex2_wayF_byp(2) <= congr_cl_ex2_relu_m and reload_wayF_upd_q; +congr_cl_ex2_wayF_byp(3) <= congr_cl_ex2_ex4_m and binv_wayF_upd_q; +congr_cl_ex2_wayF_byp(4) <= congr_cl_ex2_relu_s_m and reload_wayF_upd2_q; +congr_cl_ex2_wayF_byp(5) <= congr_cl_ex2_ex5_m and binv_wayF_upd2_q; +congr_cl_ex2_wayF_byp(6) <= congr_cl_ex2_p1_cmp and reload_wayF_upd3_q; +congr_cl_ex2_wayF_byp(7) <= congr_cl_ex2_p0_cmp and binv_wayF_upd3_q; +-- WayF Bypass Valid +ex3_wayF_fxubyp_val_d <= congr_cl_ex2_wayF_byp(1) or congr_cl_ex2_wayF_byp(3) or + congr_cl_ex2_wayF_byp(5) or congr_cl_ex2_wayF_byp(7); +ex3_wayF_relbyp_val_d <= congr_cl_ex2_wayF_byp(2) or congr_cl_ex2_wayF_byp(4) or + congr_cl_ex2_wayF_byp(6); +ex4_wayF_fxubyp_val_d <= ex3_wayF_fxubyp_val_q; +ex4_wayF_relbyp_val_d <= ex3_wayF_relbyp_val_q; +ex4_wayF_byp_sel <= ex4_wayF_fxubyp_val_q & ex4_wayF_relbyp_val_q; +-- Late Stages Priority Selection +congr_cl_ex2_wayF_sel(2) <= congr_cl_ex2_wayF_byp(2); +congr_cl_ex2_wayF_sel(3) <= congr_cl_ex2_wayF_byp(3) and not congr_cl_ex2_wayF_byp(2); +congr_cl_ex2_wayF_sel(4) <= congr_cl_ex2_wayF_byp(4) and not or_reduce(congr_cl_ex2_wayF_byp(2 to 3)); +congr_cl_ex2_wayF_sel(5) <= congr_cl_ex2_wayF_byp(5) and not or_reduce(congr_cl_ex2_wayF_byp(2 to 4)); +congr_cl_ex2_wayF_sel(6) <= congr_cl_ex2_wayF_byp(6) and not or_reduce(congr_cl_ex2_wayF_byp(2 to 5)); +congr_cl_ex2_wayF_sel(7) <= congr_cl_ex2_wayF_byp(7) and not or_reduce(congr_cl_ex2_wayF_byp(2 to 6)); +-- ArrayRead/LATE Stage Priority Selection +wayF_late_sel <= or_reduce(congr_cl_ex2_wayF_byp(2 to 7)); +wayF_later_stg_pri <= gate(p0_arr_wayF_rd, not wayF_late_sel) or + gate(reload_wayF_q, congr_cl_ex2_wayF_sel(2)) or + gate(flush_wayF_q, congr_cl_ex2_wayF_sel(3)) or + gate(reload_wayF_data_q, congr_cl_ex2_wayF_sel(4)) or + gate(flush_wayF_data_q, congr_cl_ex2_wayF_sel(5)) or + gate(reload_wayF_data2_q, congr_cl_ex2_wayF_sel(6)) or + gate(flush_wayF_data2_q, congr_cl_ex2_wayF_sel(7)); +-- EX3/RELU Stage Priority Selection +wayF_early_sel <= congr_cl_ex2_wayF_byp(1); +wayF_early_stg_pri <= flush_wayF_d; +-- Stage/ARRAY Priority Selection +wayF_stg_val <= (others=>(wayF_early_sel)); +wayF_stg_val_b <= (others=>(not(wayF_early_sel))); +wayF_val(0 TO 1) <= not wayF_val_b_q(0 to 1); +wayF_val(2 TO 5) <= not wayF_val_b_q(2 to 5); +wayF_val_b1 <= not wayF_val(0); +-- WayG Bypass Calculation +congr_cl_ex2_wayG_byp(1) <= congr_cl_ex2_ex3_m and ex3_wayG_hit; +congr_cl_ex2_wayG_byp(2) <= congr_cl_ex2_relu_m and reload_wayG_upd_q; +congr_cl_ex2_wayG_byp(3) <= congr_cl_ex2_ex4_m and binv_wayG_upd_q; +congr_cl_ex2_wayG_byp(4) <= congr_cl_ex2_relu_s_m and reload_wayG_upd2_q; +congr_cl_ex2_wayG_byp(5) <= congr_cl_ex2_ex5_m and binv_wayG_upd2_q; +congr_cl_ex2_wayG_byp(6) <= congr_cl_ex2_p1_cmp and reload_wayG_upd3_q; +congr_cl_ex2_wayG_byp(7) <= congr_cl_ex2_p0_cmp and binv_wayG_upd3_q; +-- WayG Bypass Valid +ex3_wayG_fxubyp_val_d <= congr_cl_ex2_wayG_byp(1) or congr_cl_ex2_wayG_byp(3) or + congr_cl_ex2_wayG_byp(5) or congr_cl_ex2_wayG_byp(7); +ex3_wayG_relbyp_val_d <= congr_cl_ex2_wayG_byp(2) or congr_cl_ex2_wayG_byp(4) or + congr_cl_ex2_wayG_byp(6); +ex4_wayG_fxubyp_val_d <= ex3_wayG_fxubyp_val_q; +ex4_wayG_relbyp_val_d <= ex3_wayG_relbyp_val_q; +ex4_wayG_byp_sel <= ex4_wayG_fxubyp_val_q & ex4_wayG_relbyp_val_q; +-- Late Stages Priority Selection +congr_cl_ex2_wayG_sel(2) <= congr_cl_ex2_wayG_byp(2); +congr_cl_ex2_wayG_sel(3) <= congr_cl_ex2_wayG_byp(3) and not congr_cl_ex2_wayG_byp(2); +congr_cl_ex2_wayG_sel(4) <= congr_cl_ex2_wayG_byp(4) and not or_reduce(congr_cl_ex2_wayG_byp(2 to 3)); +congr_cl_ex2_wayG_sel(5) <= congr_cl_ex2_wayG_byp(5) and not or_reduce(congr_cl_ex2_wayG_byp(2 to 4)); +congr_cl_ex2_wayG_sel(6) <= congr_cl_ex2_wayG_byp(6) and not or_reduce(congr_cl_ex2_wayG_byp(2 to 5)); +congr_cl_ex2_wayG_sel(7) <= congr_cl_ex2_wayG_byp(7) and not or_reduce(congr_cl_ex2_wayG_byp(2 to 6)); +-- ArrayRead/LATE Stage Priority Selection +wayG_late_sel <= or_reduce(congr_cl_ex2_wayG_byp(2 to 7)); +wayG_later_stg_pri <= gate(p0_arr_wayG_rd, not wayG_late_sel) or + gate(reload_wayG_q, congr_cl_ex2_wayG_sel(2)) or + gate(flush_wayG_q, congr_cl_ex2_wayG_sel(3)) or + gate(reload_wayG_data_q, congr_cl_ex2_wayG_sel(4)) or + gate(flush_wayG_data_q, congr_cl_ex2_wayG_sel(5)) or + gate(reload_wayG_data2_q, congr_cl_ex2_wayG_sel(6)) or + gate(flush_wayG_data2_q, congr_cl_ex2_wayG_sel(7)); +-- EX3/RELU Stage Priority Selection +wayG_early_sel <= congr_cl_ex2_wayG_byp(1); +wayG_early_stg_pri <= flush_wayG_d; +-- Stage/ARRAY Priority Selection +wayG_stg_val <= (others=>(wayG_early_sel)); +wayG_stg_val_b <= (others=>(not(wayG_early_sel))); +wayG_val(0 TO 1) <= not wayG_val_b_q(0 to 1); +wayG_val(2 TO 5) <= not wayG_val_b_q(2 to 5); +wayG_val_b1 <= not wayG_val(0); +-- WayH Bypass Calculation +congr_cl_ex2_wayH_byp(1) <= congr_cl_ex2_ex3_m and ex3_wayH_hit; +congr_cl_ex2_wayH_byp(2) <= congr_cl_ex2_relu_m and reload_wayH_upd_q; +congr_cl_ex2_wayH_byp(3) <= congr_cl_ex2_ex4_m and binv_wayH_upd_q; +congr_cl_ex2_wayH_byp(4) <= congr_cl_ex2_relu_s_m and reload_wayH_upd2_q; +congr_cl_ex2_wayH_byp(5) <= congr_cl_ex2_ex5_m and binv_wayH_upd2_q; +congr_cl_ex2_wayH_byp(6) <= congr_cl_ex2_p1_cmp and reload_wayH_upd3_q; +congr_cl_ex2_wayH_byp(7) <= congr_cl_ex2_p0_cmp and binv_wayH_upd3_q; +-- WayH Bypass Valid +ex3_wayH_fxubyp_val_d <= congr_cl_ex2_wayH_byp(1) or congr_cl_ex2_wayH_byp(3) or + congr_cl_ex2_wayH_byp(5) or congr_cl_ex2_wayH_byp(7); +ex3_wayH_relbyp_val_d <= congr_cl_ex2_wayH_byp(2) or congr_cl_ex2_wayH_byp(4) or + congr_cl_ex2_wayH_byp(6); +ex4_wayH_fxubyp_val_d <= ex3_wayH_fxubyp_val_q; +ex4_wayH_relbyp_val_d <= ex3_wayH_relbyp_val_q; +ex4_wayH_byp_sel <= ex4_wayH_fxubyp_val_q & ex4_wayH_relbyp_val_q; +-- Late Stages Priority Selection +congr_cl_ex2_wayH_sel(2) <= congr_cl_ex2_wayH_byp(2); +congr_cl_ex2_wayH_sel(3) <= congr_cl_ex2_wayH_byp(3) and not congr_cl_ex2_wayH_byp(2); +congr_cl_ex2_wayH_sel(4) <= congr_cl_ex2_wayH_byp(4) and not or_reduce(congr_cl_ex2_wayH_byp(2 to 3)); +congr_cl_ex2_wayH_sel(5) <= congr_cl_ex2_wayH_byp(5) and not or_reduce(congr_cl_ex2_wayH_byp(2 to 4)); +congr_cl_ex2_wayH_sel(6) <= congr_cl_ex2_wayH_byp(6) and not or_reduce(congr_cl_ex2_wayH_byp(2 to 5)); +congr_cl_ex2_wayH_sel(7) <= congr_cl_ex2_wayH_byp(7) and not or_reduce(congr_cl_ex2_wayH_byp(2 to 6)); +-- ArrayRead/LATE Stage Priority Selection +wayH_late_sel <= or_reduce(congr_cl_ex2_wayH_byp(2 to 7)); +wayH_later_stg_pri <= gate(p0_arr_wayH_rd, not wayH_late_sel) or + gate(reload_wayH_q, congr_cl_ex2_wayH_sel(2)) or + gate(flush_wayH_q, congr_cl_ex2_wayH_sel(3)) or + gate(reload_wayH_data_q, congr_cl_ex2_wayH_sel(4)) or + gate(flush_wayH_data_q, congr_cl_ex2_wayH_sel(5)) or + gate(reload_wayH_data2_q, congr_cl_ex2_wayH_sel(6)) or + gate(flush_wayH_data2_q, congr_cl_ex2_wayH_sel(7)); +-- EX3/RELU Stage Priority Selection +wayH_early_sel <= congr_cl_ex2_wayH_byp(1); +wayH_early_stg_pri <= flush_wayH_d; +-- Stage/ARRAY Priority Selection +wayH_stg_val <= (others=>(wayH_early_sel)); +wayH_stg_val_b <= (others=>(not(wayH_early_sel))); +wayH_val(0 TO 1) <= not wayH_val_b_q(0 to 1); +wayH_val(2 TO 5) <= not wayH_val_b_q(2 to 5); +wayH_val_b1 <= not wayH_val(0); +-- #################################################### +-- Invalidate Pipe and Execution Pipe Hit/Miss Logic +-- #################################################### +-- EX3 stage +fxu_pipe_val <= ex3_c_acc or ex3_flush_cline_q; +-- EX4Invalidate/BINV/RELOAD Bypass Invalidate Pipe +-- #################################################### +-- WayA +ex3WayHitA: ex3_wayA_hit <= not (tagA_hit_b or wayA_val_b1); +-- WayB +ex3WayHitB: ex3_wayB_hit <= not (tagB_hit_b or wayB_val_b1); +-- WayC +ex3WayHitC: ex3_wayC_hit <= not (tagC_hit_b or wayC_val_b1); +-- WayD +ex3WayHitD: ex3_wayD_hit <= not (tagD_hit_b or wayD_val_b1); +-- WayE +ex3WayHitE: ex3_wayE_hit <= not (tagE_hit_b or wayE_val_b1); +-- WayF +ex3WayHitF: ex3_wayF_hit <= not (tagF_hit_b or wayF_val_b1); +-- WayG +ex3WayHitG: ex3_wayG_hit <= not (tagG_hit_b or wayG_val_b1); +-- WayH +ex3WayHitH: ex3_wayH_hit <= not (tagH_hit_b or wayH_val_b1); +-- Invalidate Valid Bit Logic on Port0 +clr_val <= ex3_flush_cline_q or back_inval_stg3_q; +clr_val_wayA <= clr_val; +-- Need to detect if Back-Invalidate or invalidate type instruction invalidated the lock bit +inval_clr_lck_wA_d <= clr_val_wayA and wayA_val(1); +flush_wayA_d(0) <= not clr_val_wayA and wayA_val(0); +clr_val_wayB <= clr_val; +-- Need to detect if Back-Invalidate or invalidate type instruction invalidated the lock bit +inval_clr_lck_wB_d <= clr_val_wayB and wayB_val(1); +flush_wayB_d(0) <= not clr_val_wayB and wayB_val(0); +clr_val_wayC <= clr_val; +-- Need to detect if Back-Invalidate or invalidate type instruction invalidated the lock bit +inval_clr_lck_wC_d <= clr_val_wayC and wayC_val(1); +flush_wayC_d(0) <= not clr_val_wayC and wayC_val(0); +clr_val_wayD <= clr_val; +-- Need to detect if Back-Invalidate or invalidate type instruction invalidated the lock bit +inval_clr_lck_wD_d <= clr_val_wayD and wayD_val(1); +flush_wayD_d(0) <= not clr_val_wayD and wayD_val(0); +clr_val_wayE <= clr_val; +-- Need to detect if Back-Invalidate or invalidate type instruction invalidated the lock bit +inval_clr_lck_wE_d <= clr_val_wayE and wayE_val(1); +flush_wayE_d(0) <= not clr_val_wayE and wayE_val(0); +clr_val_wayF <= clr_val; +-- Need to detect if Back-Invalidate or invalidate type instruction invalidated the lock bit +inval_clr_lck_wF_d <= clr_val_wayF and wayF_val(1); +flush_wayF_d(0) <= not clr_val_wayF and wayF_val(0); +clr_val_wayG <= clr_val; +-- Need to detect if Back-Invalidate or invalidate type instruction invalidated the lock bit +inval_clr_lck_wG_d <= clr_val_wayG and wayG_val(1); +flush_wayG_d(0) <= not clr_val_wayG and wayG_val(0); +clr_val_wayH <= clr_val; +-- Need to detect if Back-Invalidate or invalidate type instruction invalidated the lock bit +inval_clr_lck_wH_d <= clr_val_wayH and wayH_val(1); +flush_wayH_d(0) <= not clr_val_wayH and wayH_val(0); +-- Clear Lock Bit Logic on Port0 +-- Clear Lock Bit on an invalidate type op or a DCBLC +clr_lock <= clr_val or ex3_lock_clr_q; +-- CLEAR LOCK SET LOCK +upd_lck_wayA <= clr_lock & ex3_lock_set_q; +flush_wayA_d(1) <= (wayA_val(1) and not upd_lck_wayA(0)) or + (wayA_val(0) and upd_lck_wayA(1)); +-- Staging out current watch bits +ex4_wayA_val_d <= wayA_val; +-- CLEAR LOCK SET LOCK +upd_lck_wayB <= clr_lock & ex3_lock_set_q; +flush_wayB_d(1) <= (wayB_val(1) and not upd_lck_wayB(0)) or + (wayB_val(0) and upd_lck_wayB(1)); +-- Staging out current watch bits +ex4_wayB_val_d <= wayB_val; +-- CLEAR LOCK SET LOCK +upd_lck_wayC <= clr_lock & ex3_lock_set_q; +flush_wayC_d(1) <= (wayC_val(1) and not upd_lck_wayC(0)) or + (wayC_val(0) and upd_lck_wayC(1)); +-- Staging out current watch bits +ex4_wayC_val_d <= wayC_val; +-- CLEAR LOCK SET LOCK +upd_lck_wayD <= clr_lock & ex3_lock_set_q; +flush_wayD_d(1) <= (wayD_val(1) and not upd_lck_wayD(0)) or + (wayD_val(0) and upd_lck_wayD(1)); +-- Staging out current watch bits +ex4_wayD_val_d <= wayD_val; +-- CLEAR LOCK SET LOCK +upd_lck_wayE <= clr_lock & ex3_lock_set_q; +flush_wayE_d(1) <= (wayE_val(1) and not upd_lck_wayE(0)) or + (wayE_val(0) and upd_lck_wayE(1)); +-- Staging out current watch bits +ex4_wayE_val_d <= wayE_val; +-- CLEAR LOCK SET LOCK +upd_lck_wayF <= clr_lock & ex3_lock_set_q; +flush_wayF_d(1) <= (wayF_val(1) and not upd_lck_wayF(0)) or + (wayF_val(0) and upd_lck_wayF(1)); +-- Staging out current watch bits +ex4_wayF_val_d <= wayF_val; +-- CLEAR LOCK SET LOCK +upd_lck_wayG <= clr_lock & ex3_lock_set_q; +flush_wayG_d(1) <= (wayG_val(1) and not upd_lck_wayG(0)) or + (wayG_val(0) and upd_lck_wayG(1)); +-- Staging out current watch bits +ex4_wayG_val_d <= wayG_val; +-- CLEAR LOCK SET LOCK +upd_lck_wayH <= clr_lock & ex3_lock_set_q; +flush_wayH_d(1) <= (wayH_val(1) and not upd_lck_wayH(0)) or + (wayH_val(0) and upd_lck_wayH(1)); +-- Staging out current watch bits +ex4_wayH_val_d <= wayH_val; +-- Set/Clr Watch Bit for Thread on Port0 +-- Clear Watch Bit on an invalidate type op or WCLR +-- Thread 0 Logic +lose_watch(0) <= clr_val or (ex3_store_instr_q and ex3_c_acc and not ex3_thrd_id_q(0)); +ex4_lose_watch_d(0) <= lose_watch(0); +clr_watch(0) <= (ex3_watch_clr_q and ex3_thrd_id_q(0)) or lose_watch(0); +set_watch(0) <= ex3_watch_set_q and ex3_thrd_id_q(0); +-- Determine if a Watch Bit was lost +ex4_lost_wayA(0) <= ex4_lose_watch_q(0) and ex4_way_hit_q(0) and ex4_wayA_val_q(2); +-- CLEAR Watch SET Watch +upd_watch_tid0_wayA <= (clr_watch(0) or ex3_watch_clr_all(0)) & set_watch(0); +flush_wayA_d(2) <= (wayA_val(2) and not upd_watch_tid0_wayA(0)) or + (wayA_val(0) and upd_watch_tid0_wayA(1)); +-- Determine if a Watch Bit was lost +ex4_lost_wayB(0) <= ex4_lose_watch_q(0) and ex4_way_hit_q(1) and ex4_wayB_val_q(2); +-- CLEAR Watch SET Watch +upd_watch_tid0_wayB <= (clr_watch(0) or ex3_watch_clr_all(0)) & set_watch(0); +flush_wayB_d(2) <= (wayB_val(2) and not upd_watch_tid0_wayB(0)) or + (wayB_val(0) and upd_watch_tid0_wayB(1)); +-- Determine if a Watch Bit was lost +ex4_lost_wayC(0) <= ex4_lose_watch_q(0) and ex4_way_hit_q(2) and ex4_wayC_val_q(2); +-- CLEAR Watch SET Watch +upd_watch_tid0_wayC <= (clr_watch(0) or ex3_watch_clr_all(0)) & set_watch(0); +flush_wayC_d(2) <= (wayC_val(2) and not upd_watch_tid0_wayC(0)) or + (wayC_val(0) and upd_watch_tid0_wayC(1)); +-- Determine if a Watch Bit was lost +ex4_lost_wayD(0) <= ex4_lose_watch_q(0) and ex4_way_hit_q(3) and ex4_wayD_val_q(2); +-- CLEAR Watch SET Watch +upd_watch_tid0_wayD <= (clr_watch(0) or ex3_watch_clr_all(0)) & set_watch(0); +flush_wayD_d(2) <= (wayD_val(2) and not upd_watch_tid0_wayD(0)) or + (wayD_val(0) and upd_watch_tid0_wayD(1)); +-- Determine if a Watch Bit was lost +ex4_lost_wayE(0) <= ex4_lose_watch_q(0) and ex4_way_hit_q(4) and ex4_wayE_val_q(2); +-- CLEAR Watch SET Watch +upd_watch_tid0_wayE <= (clr_watch(0) or ex3_watch_clr_all(0)) & set_watch(0); +flush_wayE_d(2) <= (wayE_val(2) and not upd_watch_tid0_wayE(0)) or + (wayE_val(0) and upd_watch_tid0_wayE(1)); +-- Determine if a Watch Bit was lost +ex4_lost_wayF(0) <= ex4_lose_watch_q(0) and ex4_way_hit_q(5) and ex4_wayF_val_q(2); +-- CLEAR Watch SET Watch +upd_watch_tid0_wayF <= (clr_watch(0) or ex3_watch_clr_all(0)) & set_watch(0); +flush_wayF_d(2) <= (wayF_val(2) and not upd_watch_tid0_wayF(0)) or + (wayF_val(0) and upd_watch_tid0_wayF(1)); +-- Determine if a Watch Bit was lost +ex4_lost_wayG(0) <= ex4_lose_watch_q(0) and ex4_way_hit_q(6) and ex4_wayG_val_q(2); +-- CLEAR Watch SET Watch +upd_watch_tid0_wayG <= (clr_watch(0) or ex3_watch_clr_all(0)) & set_watch(0); +flush_wayG_d(2) <= (wayG_val(2) and not upd_watch_tid0_wayG(0)) or + (wayG_val(0) and upd_watch_tid0_wayG(1)); +-- Determine if a Watch Bit was lost +ex4_lost_wayH(0) <= ex4_lose_watch_q(0) and ex4_way_hit_q(7) and ex4_wayH_val_q(2); +-- CLEAR Watch SET Watch +upd_watch_tid0_wayH <= (clr_watch(0) or ex3_watch_clr_all(0)) & set_watch(0); +flush_wayH_d(2) <= (wayH_val(2) and not upd_watch_tid0_wayH(0)) or + (wayH_val(0) and upd_watch_tid0_wayH(1)); +-- Thread 1 Logic +lose_watch(1) <= clr_val or (ex3_store_instr_q and ex3_c_acc and not ex3_thrd_id_q(1)); +ex4_lose_watch_d(1) <= lose_watch(1); +clr_watch(1) <= (ex3_watch_clr_q and ex3_thrd_id_q(1)) or lose_watch(1); +set_watch(1) <= ex3_watch_set_q and ex3_thrd_id_q(1); +-- Determine if a Watch Bit was lost +ex4_lost_wayA(1) <= ex4_lose_watch_q(1) and ex4_way_hit_q(0) and ex4_wayA_val_q(3); +-- CLEAR Watch SET Watch +upd_watch_tid1_wayA <= (clr_watch(1) or ex3_watch_clr_all(1)) & set_watch(1); +flush_wayA_d(3) <= (wayA_val(3) and not upd_watch_tid1_wayA(0)) or + (wayA_val(0) and upd_watch_tid1_wayA(1)); +-- Determine if a Watch Bit was lost +ex4_lost_wayB(1) <= ex4_lose_watch_q(1) and ex4_way_hit_q(1) and ex4_wayB_val_q(3); +-- CLEAR Watch SET Watch +upd_watch_tid1_wayB <= (clr_watch(1) or ex3_watch_clr_all(1)) & set_watch(1); +flush_wayB_d(3) <= (wayB_val(3) and not upd_watch_tid1_wayB(0)) or + (wayB_val(0) and upd_watch_tid1_wayB(1)); +-- Determine if a Watch Bit was lost +ex4_lost_wayC(1) <= ex4_lose_watch_q(1) and ex4_way_hit_q(2) and ex4_wayC_val_q(3); +-- CLEAR Watch SET Watch +upd_watch_tid1_wayC <= (clr_watch(1) or ex3_watch_clr_all(1)) & set_watch(1); +flush_wayC_d(3) <= (wayC_val(3) and not upd_watch_tid1_wayC(0)) or + (wayC_val(0) and upd_watch_tid1_wayC(1)); +-- Determine if a Watch Bit was lost +ex4_lost_wayD(1) <= ex4_lose_watch_q(1) and ex4_way_hit_q(3) and ex4_wayD_val_q(3); +-- CLEAR Watch SET Watch +upd_watch_tid1_wayD <= (clr_watch(1) or ex3_watch_clr_all(1)) & set_watch(1); +flush_wayD_d(3) <= (wayD_val(3) and not upd_watch_tid1_wayD(0)) or + (wayD_val(0) and upd_watch_tid1_wayD(1)); +-- Determine if a Watch Bit was lost +ex4_lost_wayE(1) <= ex4_lose_watch_q(1) and ex4_way_hit_q(4) and ex4_wayE_val_q(3); +-- CLEAR Watch SET Watch +upd_watch_tid1_wayE <= (clr_watch(1) or ex3_watch_clr_all(1)) & set_watch(1); +flush_wayE_d(3) <= (wayE_val(3) and not upd_watch_tid1_wayE(0)) or + (wayE_val(0) and upd_watch_tid1_wayE(1)); +-- Determine if a Watch Bit was lost +ex4_lost_wayF(1) <= ex4_lose_watch_q(1) and ex4_way_hit_q(5) and ex4_wayF_val_q(3); +-- CLEAR Watch SET Watch +upd_watch_tid1_wayF <= (clr_watch(1) or ex3_watch_clr_all(1)) & set_watch(1); +flush_wayF_d(3) <= (wayF_val(3) and not upd_watch_tid1_wayF(0)) or + (wayF_val(0) and upd_watch_tid1_wayF(1)); +-- Determine if a Watch Bit was lost +ex4_lost_wayG(1) <= ex4_lose_watch_q(1) and ex4_way_hit_q(6) and ex4_wayG_val_q(3); +-- CLEAR Watch SET Watch +upd_watch_tid1_wayG <= (clr_watch(1) or ex3_watch_clr_all(1)) & set_watch(1); +flush_wayG_d(3) <= (wayG_val(3) and not upd_watch_tid1_wayG(0)) or + (wayG_val(0) and upd_watch_tid1_wayG(1)); +-- Determine if a Watch Bit was lost +ex4_lost_wayH(1) <= ex4_lose_watch_q(1) and ex4_way_hit_q(7) and ex4_wayH_val_q(3); +-- CLEAR Watch SET Watch +upd_watch_tid1_wayH <= (clr_watch(1) or ex3_watch_clr_all(1)) & set_watch(1); +flush_wayH_d(3) <= (wayH_val(3) and not upd_watch_tid1_wayH(0)) or + (wayH_val(0) and upd_watch_tid1_wayH(1)); +-- Thread 2 Logic +lose_watch(2) <= clr_val or (ex3_store_instr_q and ex3_c_acc and not ex3_thrd_id_q(2)); +ex4_lose_watch_d(2) <= lose_watch(2); +clr_watch(2) <= (ex3_watch_clr_q and ex3_thrd_id_q(2)) or lose_watch(2); +set_watch(2) <= ex3_watch_set_q and ex3_thrd_id_q(2); +-- Determine if a Watch Bit was lost +ex4_lost_wayA(2) <= ex4_lose_watch_q(2) and ex4_way_hit_q(0) and ex4_wayA_val_q(4); +-- CLEAR Watch SET Watch +upd_watch_tid2_wayA <= (clr_watch(2) or ex3_watch_clr_all(2)) & set_watch(2); +flush_wayA_d(4) <= (wayA_val(4) and not upd_watch_tid2_wayA(0)) or + (wayA_val(0) and upd_watch_tid2_wayA(1)); +-- Determine if a Watch Bit was lost +ex4_lost_wayB(2) <= ex4_lose_watch_q(2) and ex4_way_hit_q(1) and ex4_wayB_val_q(4); +-- CLEAR Watch SET Watch +upd_watch_tid2_wayB <= (clr_watch(2) or ex3_watch_clr_all(2)) & set_watch(2); +flush_wayB_d(4) <= (wayB_val(4) and not upd_watch_tid2_wayB(0)) or + (wayB_val(0) and upd_watch_tid2_wayB(1)); +-- Determine if a Watch Bit was lost +ex4_lost_wayC(2) <= ex4_lose_watch_q(2) and ex4_way_hit_q(2) and ex4_wayC_val_q(4); +-- CLEAR Watch SET Watch +upd_watch_tid2_wayC <= (clr_watch(2) or ex3_watch_clr_all(2)) & set_watch(2); +flush_wayC_d(4) <= (wayC_val(4) and not upd_watch_tid2_wayC(0)) or + (wayC_val(0) and upd_watch_tid2_wayC(1)); +-- Determine if a Watch Bit was lost +ex4_lost_wayD(2) <= ex4_lose_watch_q(2) and ex4_way_hit_q(3) and ex4_wayD_val_q(4); +-- CLEAR Watch SET Watch +upd_watch_tid2_wayD <= (clr_watch(2) or ex3_watch_clr_all(2)) & set_watch(2); +flush_wayD_d(4) <= (wayD_val(4) and not upd_watch_tid2_wayD(0)) or + (wayD_val(0) and upd_watch_tid2_wayD(1)); +-- Determine if a Watch Bit was lost +ex4_lost_wayE(2) <= ex4_lose_watch_q(2) and ex4_way_hit_q(4) and ex4_wayE_val_q(4); +-- CLEAR Watch SET Watch +upd_watch_tid2_wayE <= (clr_watch(2) or ex3_watch_clr_all(2)) & set_watch(2); +flush_wayE_d(4) <= (wayE_val(4) and not upd_watch_tid2_wayE(0)) or + (wayE_val(0) and upd_watch_tid2_wayE(1)); +-- Determine if a Watch Bit was lost +ex4_lost_wayF(2) <= ex4_lose_watch_q(2) and ex4_way_hit_q(5) and ex4_wayF_val_q(4); +-- CLEAR Watch SET Watch +upd_watch_tid2_wayF <= (clr_watch(2) or ex3_watch_clr_all(2)) & set_watch(2); +flush_wayF_d(4) <= (wayF_val(4) and not upd_watch_tid2_wayF(0)) or + (wayF_val(0) and upd_watch_tid2_wayF(1)); +-- Determine if a Watch Bit was lost +ex4_lost_wayG(2) <= ex4_lose_watch_q(2) and ex4_way_hit_q(6) and ex4_wayG_val_q(4); +-- CLEAR Watch SET Watch +upd_watch_tid2_wayG <= (clr_watch(2) or ex3_watch_clr_all(2)) & set_watch(2); +flush_wayG_d(4) <= (wayG_val(4) and not upd_watch_tid2_wayG(0)) or + (wayG_val(0) and upd_watch_tid2_wayG(1)); +-- Determine if a Watch Bit was lost +ex4_lost_wayH(2) <= ex4_lose_watch_q(2) and ex4_way_hit_q(7) and ex4_wayH_val_q(4); +-- CLEAR Watch SET Watch +upd_watch_tid2_wayH <= (clr_watch(2) or ex3_watch_clr_all(2)) & set_watch(2); +flush_wayH_d(4) <= (wayH_val(4) and not upd_watch_tid2_wayH(0)) or + (wayH_val(0) and upd_watch_tid2_wayH(1)); +-- Thread 3 Logic +lose_watch(3) <= clr_val or (ex3_store_instr_q and ex3_c_acc and not ex3_thrd_id_q(3)); +ex4_lose_watch_d(3) <= lose_watch(3); +clr_watch(3) <= (ex3_watch_clr_q and ex3_thrd_id_q(3)) or lose_watch(3); +set_watch(3) <= ex3_watch_set_q and ex3_thrd_id_q(3); +-- Determine if a Watch Bit was lost +ex4_lost_wayA(3) <= ex4_lose_watch_q(3) and ex4_way_hit_q(0) and ex4_wayA_val_q(5); +-- CLEAR Watch SET Watch +upd_watch_tid3_wayA <= (clr_watch(3) or ex3_watch_clr_all(3)) & set_watch(3); +flush_wayA_d(5) <= (wayA_val(5) and not upd_watch_tid3_wayA(0)) or + (wayA_val(0) and upd_watch_tid3_wayA(1)); +-- Determine if a Watch Bit was lost +ex4_lost_wayB(3) <= ex4_lose_watch_q(3) and ex4_way_hit_q(1) and ex4_wayB_val_q(5); +-- CLEAR Watch SET Watch +upd_watch_tid3_wayB <= (clr_watch(3) or ex3_watch_clr_all(3)) & set_watch(3); +flush_wayB_d(5) <= (wayB_val(5) and not upd_watch_tid3_wayB(0)) or + (wayB_val(0) and upd_watch_tid3_wayB(1)); +-- Determine if a Watch Bit was lost +ex4_lost_wayC(3) <= ex4_lose_watch_q(3) and ex4_way_hit_q(2) and ex4_wayC_val_q(5); +-- CLEAR Watch SET Watch +upd_watch_tid3_wayC <= (clr_watch(3) or ex3_watch_clr_all(3)) & set_watch(3); +flush_wayC_d(5) <= (wayC_val(5) and not upd_watch_tid3_wayC(0)) or + (wayC_val(0) and upd_watch_tid3_wayC(1)); +-- Determine if a Watch Bit was lost +ex4_lost_wayD(3) <= ex4_lose_watch_q(3) and ex4_way_hit_q(3) and ex4_wayD_val_q(5); +-- CLEAR Watch SET Watch +upd_watch_tid3_wayD <= (clr_watch(3) or ex3_watch_clr_all(3)) & set_watch(3); +flush_wayD_d(5) <= (wayD_val(5) and not upd_watch_tid3_wayD(0)) or + (wayD_val(0) and upd_watch_tid3_wayD(1)); +-- Determine if a Watch Bit was lost +ex4_lost_wayE(3) <= ex4_lose_watch_q(3) and ex4_way_hit_q(4) and ex4_wayE_val_q(5); +-- CLEAR Watch SET Watch +upd_watch_tid3_wayE <= (clr_watch(3) or ex3_watch_clr_all(3)) & set_watch(3); +flush_wayE_d(5) <= (wayE_val(5) and not upd_watch_tid3_wayE(0)) or + (wayE_val(0) and upd_watch_tid3_wayE(1)); +-- Determine if a Watch Bit was lost +ex4_lost_wayF(3) <= ex4_lose_watch_q(3) and ex4_way_hit_q(5) and ex4_wayF_val_q(5); +-- CLEAR Watch SET Watch +upd_watch_tid3_wayF <= (clr_watch(3) or ex3_watch_clr_all(3)) & set_watch(3); +flush_wayF_d(5) <= (wayF_val(5) and not upd_watch_tid3_wayF(0)) or + (wayF_val(0) and upd_watch_tid3_wayF(1)); +-- Determine if a Watch Bit was lost +ex4_lost_wayG(3) <= ex4_lose_watch_q(3) and ex4_way_hit_q(6) and ex4_wayG_val_q(5); +-- CLEAR Watch SET Watch +upd_watch_tid3_wayG <= (clr_watch(3) or ex3_watch_clr_all(3)) & set_watch(3); +flush_wayG_d(5) <= (wayG_val(5) and not upd_watch_tid3_wayG(0)) or + (wayG_val(0) and upd_watch_tid3_wayG(1)); +-- Determine if a Watch Bit was lost +ex4_lost_wayH(3) <= ex4_lose_watch_q(3) and ex4_way_hit_q(7) and ex4_wayH_val_q(5); +-- CLEAR Watch SET Watch +upd_watch_tid3_wayH <= (clr_watch(3) or ex3_watch_clr_all(3)) & set_watch(3); +flush_wayH_d(5) <= (wayH_val(5) and not upd_watch_tid3_wayH(0)) or + (wayH_val(0) and upd_watch_tid3_wayH(1)); +-- Determine if Updating Directory +binv_wayA_upd_d <= (ex3_wayA_hit and binv3_ex3_xuop_upd); +ex3_xuop_lost_watch_wayA <= or_reduce((wayA_val(2 to 5) and not ex3_thrd_id_q)) and ex3_store_instr_q and ex3_c_acc; +ex3_xuop_wayA_upd <= (ex3_wayA_hit and (ex3_xuop_upd_dir or ex3_xuop_lost_watch_wayA)); +ex4_xuop_wayA_upd_d <= ex3_xuop_wayA_upd; +ex5_xuop_wayA_upd_d <= ex4_xuop_wayA_upd_q; +binv_wayB_upd_d <= (ex3_wayB_hit and binv3_ex3_xuop_upd); +ex3_xuop_lost_watch_wayB <= or_reduce((wayB_val(2 to 5) and not ex3_thrd_id_q)) and ex3_store_instr_q and ex3_c_acc; +ex3_xuop_wayB_upd <= (ex3_wayB_hit and (ex3_xuop_upd_dir or ex3_xuop_lost_watch_wayB)); +ex4_xuop_wayB_upd_d <= ex3_xuop_wayB_upd; +ex5_xuop_wayB_upd_d <= ex4_xuop_wayB_upd_q; +binv_wayC_upd_d <= (ex3_wayC_hit and binv3_ex3_xuop_upd); +ex3_xuop_lost_watch_wayC <= or_reduce((wayC_val(2 to 5) and not ex3_thrd_id_q)) and ex3_store_instr_q and ex3_c_acc; +ex3_xuop_wayC_upd <= (ex3_wayC_hit and (ex3_xuop_upd_dir or ex3_xuop_lost_watch_wayC)); +ex4_xuop_wayC_upd_d <= ex3_xuop_wayC_upd; +ex5_xuop_wayC_upd_d <= ex4_xuop_wayC_upd_q; +binv_wayD_upd_d <= (ex3_wayD_hit and binv3_ex3_xuop_upd); +ex3_xuop_lost_watch_wayD <= or_reduce((wayD_val(2 to 5) and not ex3_thrd_id_q)) and ex3_store_instr_q and ex3_c_acc; +ex3_xuop_wayD_upd <= (ex3_wayD_hit and (ex3_xuop_upd_dir or ex3_xuop_lost_watch_wayD)); +ex4_xuop_wayD_upd_d <= ex3_xuop_wayD_upd; +ex5_xuop_wayD_upd_d <= ex4_xuop_wayD_upd_q; +binv_wayE_upd_d <= (ex3_wayE_hit and binv3_ex3_xuop_upd); +ex3_xuop_lost_watch_wayE <= or_reduce((wayE_val(2 to 5) and not ex3_thrd_id_q)) and ex3_store_instr_q and ex3_c_acc; +ex3_xuop_wayE_upd <= (ex3_wayE_hit and (ex3_xuop_upd_dir or ex3_xuop_lost_watch_wayE)); +ex4_xuop_wayE_upd_d <= ex3_xuop_wayE_upd; +ex5_xuop_wayE_upd_d <= ex4_xuop_wayE_upd_q; +binv_wayF_upd_d <= (ex3_wayF_hit and binv3_ex3_xuop_upd); +ex3_xuop_lost_watch_wayF <= or_reduce((wayF_val(2 to 5) and not ex3_thrd_id_q)) and ex3_store_instr_q and ex3_c_acc; +ex3_xuop_wayF_upd <= (ex3_wayF_hit and (ex3_xuop_upd_dir or ex3_xuop_lost_watch_wayF)); +ex4_xuop_wayF_upd_d <= ex3_xuop_wayF_upd; +ex5_xuop_wayF_upd_d <= ex4_xuop_wayF_upd_q; +binv_wayG_upd_d <= (ex3_wayG_hit and binv3_ex3_xuop_upd); +ex3_xuop_lost_watch_wayG <= or_reduce((wayG_val(2 to 5) and not ex3_thrd_id_q)) and ex3_store_instr_q and ex3_c_acc; +ex3_xuop_wayG_upd <= (ex3_wayG_hit and (ex3_xuop_upd_dir or ex3_xuop_lost_watch_wayG)); +ex4_xuop_wayG_upd_d <= ex3_xuop_wayG_upd; +ex5_xuop_wayG_upd_d <= ex4_xuop_wayG_upd_q; +binv_wayH_upd_d <= (ex3_wayH_hit and binv3_ex3_xuop_upd); +ex3_xuop_lost_watch_wayH <= or_reduce((wayH_val(2 to 5) and not ex3_thrd_id_q)) and ex3_store_instr_q and ex3_c_acc; +ex3_xuop_wayH_upd <= (ex3_wayH_hit and (ex3_xuop_upd_dir or ex3_xuop_lost_watch_wayH)); +ex4_xuop_wayH_upd_d <= ex3_xuop_wayH_upd; +ex5_xuop_wayH_upd_d <= ex4_xuop_wayH_upd_q; +-- One of the Ways has a Lock Bit set +binv4_ex4_lock_set <= ex4_wayA_val_q(1) or ex4_wayB_val_q(1) or ex4_wayC_val_q(1) or ex4_wayD_val_q(1) or + ex4_wayE_val_q(1) or ex4_wayF_val_q(1) or ex4_wayG_val_q(1) or ex4_wayH_val_q(1); +-- Threads Watching one of the ways in EX4/BINV4 +binv4_ex4_thrd_watch <= ex4_wayA_val_q(2 to 5) or ex4_wayB_val_q(2 to 5) or ex4_wayC_val_q(2 to 5) or ex4_wayD_val_q(2 to 5) or + ex4_wayE_val_q(2 to 5) or ex4_wayF_val_q(2 to 5) or ex4_wayG_val_q(2 to 5) or ex4_wayH_val_q(2 to 5); +-- Return Prior Watch Bit Value +wayA_watch_value <= (ex4_thrd_id_q(0) and ex4_wayA_val_q(2)) or (ex4_thrd_id_q(1) and ex4_wayA_val_q(3)) or + (ex4_thrd_id_q(2) and ex4_wayA_val_q(4)) or (ex4_thrd_id_q(3) and ex4_wayA_val_q(5)); +wayB_watch_value <= (ex4_thrd_id_q(0) and ex4_wayB_val_q(2)) or (ex4_thrd_id_q(1) and ex4_wayB_val_q(3)) or + (ex4_thrd_id_q(2) and ex4_wayB_val_q(4)) or (ex4_thrd_id_q(3) and ex4_wayB_val_q(5)); +wayC_watch_value <= (ex4_thrd_id_q(0) and ex4_wayC_val_q(2)) or (ex4_thrd_id_q(1) and ex4_wayC_val_q(3)) or + (ex4_thrd_id_q(2) and ex4_wayC_val_q(4)) or (ex4_thrd_id_q(3) and ex4_wayC_val_q(5)); +wayD_watch_value <= (ex4_thrd_id_q(0) and ex4_wayD_val_q(2)) or (ex4_thrd_id_q(1) and ex4_wayD_val_q(3)) or + (ex4_thrd_id_q(2) and ex4_wayD_val_q(4)) or (ex4_thrd_id_q(3) and ex4_wayD_val_q(5)); +wayE_watch_value <= (ex4_thrd_id_q(0) and ex4_wayE_val_q(2)) or (ex4_thrd_id_q(1) and ex4_wayE_val_q(3)) or + (ex4_thrd_id_q(2) and ex4_wayE_val_q(4)) or (ex4_thrd_id_q(3) and ex4_wayE_val_q(5)); +wayF_watch_value <= (ex4_thrd_id_q(0) and ex4_wayF_val_q(2)) or (ex4_thrd_id_q(1) and ex4_wayF_val_q(3)) or + (ex4_thrd_id_q(2) and ex4_wayF_val_q(4)) or (ex4_thrd_id_q(3) and ex4_wayF_val_q(5)); +wayG_watch_value <= (ex4_thrd_id_q(0) and ex4_wayG_val_q(2)) or (ex4_thrd_id_q(1) and ex4_wayG_val_q(3)) or + (ex4_thrd_id_q(2) and ex4_wayG_val_q(4)) or (ex4_thrd_id_q(3) and ex4_wayG_val_q(5)); +wayH_watch_value <= (ex4_thrd_id_q(0) and ex4_wayH_val_q(2)) or (ex4_thrd_id_q(1) and ex4_wayH_val_q(3)) or + (ex4_thrd_id_q(2) and ex4_wayH_val_q(4)) or (ex4_thrd_id_q(3) and ex4_wayH_val_q(5)); +ex4_curr_watch <= (ex4_way_hit_q(0) and wayA_watch_value) or (ex4_way_hit_q(1) and wayB_watch_value) or + (ex4_way_hit_q(2) and wayC_watch_value) or (ex4_way_hit_q(3) and wayD_watch_value) or + (ex4_way_hit_q(4) and wayE_watch_value) or (ex4_way_hit_q(5) and wayF_watch_value) or + (ex4_way_hit_q(6) and wayG_watch_value) or (ex4_way_hit_q(7) and wayH_watch_value); +stm_watchlost_sel <= (ex4_thrd_id_q(0) and stm_watchlost(0)) or (ex4_thrd_id_q(1) and stm_watchlost(1)) or + (ex4_thrd_id_q(2) and stm_watchlost(2)) or (ex4_thrd_id_q(3) and stm_watchlost(3)); +with ex4_watch_set_q select + ex5_cr_watch_d <= stm_watchlost_sel when '0', + ex4_curr_watch when others; +-- Execution Pipe Watch Lost Indicator Logic +-- #################################################### +ex4_lost_watch(0) <= ex4_lost_wayA(0) or ex4_lost_wayB(0) or ex4_lost_wayC(0) or ex4_lost_wayD(0) or + ex4_lost_wayE(0) or ex4_lost_wayF(0) or ex4_lost_wayG(0) or ex4_lost_wayH(0) or + ex4_perr_watch_lost_q(0); +-- Want to still update the STM_WATCHLOST indicator if the DC_DIS=1 + WITH ex4_watchlost_set_q(0) SELECT ex4_lost_watch_upd(0) <= ex4_lost_watch(0) when '0', + ex4_l_fld_b1_q when others; +ex4_lost_watch(1) <= ex4_lost_wayA(1) or ex4_lost_wayB(1) or ex4_lost_wayC(1) or ex4_lost_wayD(1) or + ex4_lost_wayE(1) or ex4_lost_wayF(1) or ex4_lost_wayG(1) or ex4_lost_wayH(1) or + ex4_perr_watch_lost_q(1); +-- Want to still update the STM_WATCHLOST indicator if the DC_DIS=1 + WITH ex4_watchlost_set_q(1) SELECT ex4_lost_watch_upd(1) <= ex4_lost_watch(1) when '0', + ex4_l_fld_b1_q when others; +ex4_lost_watch(2) <= ex4_lost_wayA(2) or ex4_lost_wayB(2) or ex4_lost_wayC(2) or ex4_lost_wayD(2) or + ex4_lost_wayE(2) or ex4_lost_wayF(2) or ex4_lost_wayG(2) or ex4_lost_wayH(2) or + ex4_perr_watch_lost_q(2); +-- Want to still update the STM_WATCHLOST indicator if the DC_DIS=1 + WITH ex4_watchlost_set_q(2) SELECT ex4_lost_watch_upd(2) <= ex4_lost_watch(2) when '0', + ex4_l_fld_b1_q when others; +ex4_lost_watch(3) <= ex4_lost_wayA(3) or ex4_lost_wayB(3) or ex4_lost_wayC(3) or ex4_lost_wayD(3) or + ex4_lost_wayE(3) or ex4_lost_wayF(3) or ex4_lost_wayG(3) or ex4_lost_wayH(3) or + ex4_perr_watch_lost_q(3); +-- Want to still update the STM_WATCHLOST indicator if the DC_DIS=1 + WITH ex4_watchlost_set_q(3) SELECT ex4_lost_watch_upd(3) <= ex4_lost_watch(3) when '0', + ex4_l_fld_b1_q when others; +-- LDAWX Hit Way collided with Reload Clear of Same Way +ex4_watchSet_coll_d <= rel_val_stg2_q and ex3_watch_set_q and (rel24_congr_cl_q = ex3_congr_cl_q); +watchSet_rel_way_coll <= gate((reload_way_clr_q and ex4_way_hit_q), ex4_watchSet_coll_q); +watchSet_rel_coll_val <= gate(ex4_thrd_id_q, or_reduce(watchSet_rel_way_coll)); +ex5_lost_watch_upd_d <= ex4_lost_watch_upd or watchSet_rel_coll_val or ex4_multihit_watch_lost; +ex4_watchlost_set_d <= ex3_watch_clr_all; +ex5_watchlost_set_d <= ex4_lost_watch or ex4_watchlost_set_q or watchSet_rel_coll_val or ex4_multihit_watch_lost; +ex5_watch_clr_all_d <= gate(ex4_watch_clr_all_q, not ex4_stg_flush); +ex6_watch_clr_all_d <= gate(ex5_watch_clr_all_q, not ex5_stg_flush); +ex5_watch_clr_all_val_d <= or_reduce(ex4_watch_clr_all_q); +-- EX4Invalidate/BINV/RELOAD Bypass Execution Op hit/miss Logic +-- #################################################### +-- Hit Detect +u_th0i: tagA_hit_b <= not tagA_hit; +u_hw0i: xu_op_hit_wayA_b <= not (wayA_val(0) and tagA_hit); +u_hw0: xu_op_hit_wayA <= not xu_op_hit_wayA_b; +u_hw0b: xu_op_hit_wayA_dly_b <= not xu_op_hit_wayA; +-- Hit Detect +u_th1i: tagB_hit_b <= not tagB_hit; +u_hw1i: xu_op_hit_wayB_b <= not (wayB_val(0) and tagB_hit); +u_hw1: xu_op_hit_wayB <= not xu_op_hit_wayB_b; +u_hw1b: xu_op_hit_wayB_dly_b <= not xu_op_hit_wayB; +-- Hit Detect +u_th2i: tagC_hit_b <= not tagC_hit; +u_hw2i: xu_op_hit_wayC_b <= not (wayC_val(0) and tagC_hit); +u_hw2: xu_op_hit_wayC <= not xu_op_hit_wayC_b; +u_hw2b: xu_op_hit_wayC_dly_b <= not xu_op_hit_wayC; +-- Hit Detect +u_th3i: tagD_hit_b <= not tagD_hit; +u_hw3i: xu_op_hit_wayD_b <= not (wayD_val(0) and tagD_hit); +u_hw3: xu_op_hit_wayD <= not xu_op_hit_wayD_b; +u_hw3b: xu_op_hit_wayD_dly_b <= not xu_op_hit_wayD; +-- Hit Detect +u_th4i: tagE_hit_b <= not tagE_hit; +u_hw4i: xu_op_hit_wayE_b <= not (wayE_val(0) and tagE_hit); +u_hw4: xu_op_hit_wayE <= not xu_op_hit_wayE_b; +u_hw4b: xu_op_hit_wayE_dly_b <= not xu_op_hit_wayE; +-- Hit Detect +u_th5i: tagF_hit_b <= not tagF_hit; +u_hw5i: xu_op_hit_wayF_b <= not (wayF_val(0) and tagF_hit); +u_hw5: xu_op_hit_wayF <= not xu_op_hit_wayF_b; +u_hw5b: xu_op_hit_wayF_dly_b <= not xu_op_hit_wayF; +-- Hit Detect +u_th6i: tagG_hit_b <= not tagG_hit; +u_hw6i: xu_op_hit_wayG_b <= not (wayG_val(0) and tagG_hit); +u_hw6: xu_op_hit_wayG <= not xu_op_hit_wayG_b; +u_hw6b: xu_op_hit_wayG_dly_b <= not xu_op_hit_wayG; +-- Hit Detect +u_th7i: tagH_hit_b <= not tagH_hit; +u_hw7i: xu_op_hit_wayH_b <= not (wayH_val(0) and tagH_hit); +u_hw7: xu_op_hit_wayH <= not xu_op_hit_wayH_b; +u_hw7b: xu_op_hit_wayH_dly_b <= not xu_op_hit_wayH; +-- Invalidate Lock Bit Detect +inval_clr_lck <= (inval_clr_lck_wA_q and binv_wayA_upd_q) or (inval_clr_lck_wB_q and binv_wayB_upd_q) or + (inval_clr_lck_wC_q and binv_wayC_upd_q) or (inval_clr_lck_wD_q and binv_wayD_upd_q) or + (inval_clr_lck_wE_q and binv_wayE_upd_q) or (inval_clr_lck_wF_q and binv_wayF_upd_q) or + (inval_clr_lck_wG_q and binv_wayG_upd_q) or (inval_clr_lck_wH_q and binv_wayH_upd_q); +xucr0_cslc_xuop_d <= inval_clr_lck and ex4_xuop_val; +xucr0_cslc_binv_d <= rel_lock_lost or dcperr_lock_lost_q or ex4_perr_lck_lost_q or + ex4_multihit_lock_lost or binv5_inval_lock_val_q or (rel_l1dump_cslc_q and not rel4_ecc_err); +ex3_cClass_upd_way_a <= ex3_cClass_wayA_hit; +ex3_cClass_upd_way_b <= ex3_cClass_wayB_hit; +ex3_cClass_upd_way_c <= ex3_cClass_wayC_hit; +ex3_cClass_upd_way_d <= ex3_cClass_wayD_hit; +ex3_cClass_upd_way_e <= ex3_cClass_wayE_hit; +ex3_cClass_upd_way_f <= ex3_cClass_wayF_hit; +ex3_cClass_upd_way_g <= ex3_cClass_wayG_hit; +ex3_cClass_upd_way_h <= ex3_cClass_wayH_hit; +-- Multihit Error Detected +-- #################################################### +-- Level 1 +u_mh1_a01: hit_and_01_b <= not( xu_op_hit_wayA and xu_op_hit_wayB ); +u_mh1_a23: hit_and_23_b <= not( xu_op_hit_wayC and xu_op_hit_wayD ); +u_mh1_a45: hit_and_45_b <= not( xu_op_hit_wayE and xu_op_hit_wayF ); +u_mh1_a67: hit_and_67_b <= not( xu_op_hit_wayG and xu_op_hit_wayH ); +u_mh1_o01: hit_or_01_b <= not( xu_op_hit_wayA or xu_op_hit_wayB ); +u_mh1_o23: hit_or_23_b <= not( xu_op_hit_wayC or xu_op_hit_wayD ); +u_mh1_o45: hit_or_45_b <= not( xu_op_hit_wayE or xu_op_hit_wayF ); +u_mh1_o67: hit_or_67_b <= not( xu_op_hit_wayG or xu_op_hit_wayH ); +u_mh1_o13: hit_or_13_b <= not( xu_op_hit_wayB or xu_op_hit_wayD ); +u_mh1_o57: hit_or_57_b <= not( xu_op_hit_wayF or xu_op_hit_wayH ); +-- Level 2 +u_mh2_o0123: hit_or_0123 <= not( hit_or_01_b and hit_or_23_b ); +u_mh2_o4567: hit_or_4567 <= not( hit_or_45_b and hit_or_67_b ); +u_mh2_o1357: hit_or_1357 <= not( hit_or_13_b and hit_or_57_b ); +u_mh2_o2367: hit_or_2367 <= not( hit_or_23_b and hit_or_67_b ); +u_mh2_a0123: hit_and_0123 <= not( hit_or_01_b or hit_or_23_b ); +u_mh2_a4567: hit_and_4567 <= not( hit_or_45_b or hit_or_67_b ); +u_mh2_err0: multi_hit_err2_0 <= not( hit_and_01_b and hit_and_23_b ); +u_mh2_err1: multi_hit_err2_1 <= not( hit_and_45_b and hit_and_67_b ); +-- Level 3 +u_mh3_o: hit_or_01234567_b <= not( hit_or_0123 or hit_or_4567 ); +u_mh3_err0: multi_hit_err3_b(0) <= not( hit_or_0123 and hit_or_4567 ); +u_mh3_err1: multi_hit_err3_b(1) <= not( hit_and_0123 or hit_and_4567 ); +u_mh3_err2: multi_hit_err3_b(2) <= not( multi_hit_err2_0 or multi_hit_err2_1 ); +u_henc_0: hit_enc_b(0) <= not( hit_or_4567 ); +u_henc_1: hit_enc_b(1) <= not( hit_or_2367 ); +u_henc_2: hit_enc_b(2) <= not( hit_or_1357 ); +-- Level 4 +-- Multihit Error Detected +u_mh4_0: ex3_dir_multihit_val_0 <= not( multi_hit_err3_b(0) and multi_hit_err3_b(1) ); +u_mh4_1: ex3_dir_multihit_val_1 <= not( multi_hit_err3_b(2) and inj_dir_multihit_b ); +-- Level 5 +u_mh5: ex3_dir_multihit_val_b <= not( ex3_dir_multihit_val_0 or ex3_dir_multihit_val_1 ); +-- Level 6 +u_mh6: ex3_dir_multihit_val <= not ex3_dir_multihit_val_b ; +ex4_n_lsu_ddmh_flush_b_d <= (others=>ex3_dir_multihit_val); +ex4_dir_multihit_val <= binv4_ex4_dir_val_q and not ex4_dir_multihit_val_b_q; +inj_dir_multihit_b <= not (inj_dir_multihit_q and binv3_ex3_dir_val); +ex4_multihit_watch_lost <= gate(binv4_ex4_thrd_watch, ex4_dir_multihit_val); +ex4_multihit_lock_lost <= binv4_ex4_lock_set and ex4_dir_multihit_val; +-- #################################################### +-- Parity Error Detect +-- #################################################### +ex4_err_det_way_d(0) <= perr_way_det_wayA; +perr_way_det_wayA <= wayA_val(0) and ex3_tag_way_perr(0); +dirpar_err_lock_lost(0) <= wayA_val(1) and ex3_tag_way_perr(0); +perr_wayA_watch_lost <= gate(wayA_val(2 to 5),ex3_tag_way_perr(0)); +ex4_err_det_way_d(1) <= perr_way_det_wayB; +perr_way_det_wayB <= wayB_val(0) and ex3_tag_way_perr(1); +dirpar_err_lock_lost(1) <= wayB_val(1) and ex3_tag_way_perr(1); +perr_wayB_watch_lost <= gate(wayB_val(2 to 5),ex3_tag_way_perr(1)); +ex4_err_det_way_d(2) <= perr_way_det_wayC; +perr_way_det_wayC <= wayC_val(0) and ex3_tag_way_perr(2); +dirpar_err_lock_lost(2) <= wayC_val(1) and ex3_tag_way_perr(2); +perr_wayC_watch_lost <= gate(wayC_val(2 to 5),ex3_tag_way_perr(2)); +ex4_err_det_way_d(3) <= perr_way_det_wayD; +perr_way_det_wayD <= wayD_val(0) and ex3_tag_way_perr(3); +dirpar_err_lock_lost(3) <= wayD_val(1) and ex3_tag_way_perr(3); +perr_wayD_watch_lost <= gate(wayD_val(2 to 5),ex3_tag_way_perr(3)); +ex4_err_det_way_d(4) <= perr_way_det_wayE; +perr_way_det_wayE <= wayE_val(0) and ex3_tag_way_perr(4); +dirpar_err_lock_lost(4) <= wayE_val(1) and ex3_tag_way_perr(4); +perr_wayE_watch_lost <= gate(wayE_val(2 to 5),ex3_tag_way_perr(4)); +ex4_err_det_way_d(5) <= perr_way_det_wayF; +perr_way_det_wayF <= wayF_val(0) and ex3_tag_way_perr(5); +dirpar_err_lock_lost(5) <= wayF_val(1) and ex3_tag_way_perr(5); +perr_wayF_watch_lost <= gate(wayF_val(2 to 5),ex3_tag_way_perr(5)); +ex4_err_det_way_d(6) <= perr_way_det_wayG; +perr_way_det_wayG <= wayG_val(0) and ex3_tag_way_perr(6); +dirpar_err_lock_lost(6) <= wayG_val(1) and ex3_tag_way_perr(6); +perr_wayG_watch_lost <= gate(wayG_val(2 to 5),ex3_tag_way_perr(6)); +ex4_err_det_way_d(7) <= perr_way_det_wayH; +perr_way_det_wayH <= wayH_val(0) and ex3_tag_way_perr(7); +dirpar_err_lock_lost(7) <= wayH_val(1) and ex3_tag_way_perr(7); +perr_wayH_watch_lost <= gate(wayH_val(2 to 5),ex3_tag_way_perr(7)); +-- Lock Bit Lost due to Parity Error +ex4_perr_lck_lost_d <= or_reduce(dirpar_err_lock_lost); +-- Watch Lost due to Parity Error +ex4_perr_watch_lost_d <= perr_wayA_watch_lost or perr_wayB_watch_lost or perr_wayC_watch_lost or perr_wayD_watch_lost or + perr_wayE_watch_lost or perr_wayF_watch_lost or perr_wayG_watch_lost or perr_wayH_watch_lost; +-- Parity Error Detected +ex3_dir_perr_val <= perr_way_det_wayA or perr_way_det_wayB or perr_way_det_wayC or perr_way_det_wayD or + perr_way_det_wayE or perr_way_det_wayF or perr_way_det_wayG or perr_way_det_wayH; +-- Staging out Directory Error +ex4_dir_err_val_d <= ex3_dir_perr_val; +ex5_dir_err_val_d <= ex4_dir_err_val_q or ex4_dir_multihit_val; +ex6_dir_err_val_d <= ex5_dir_err_val_q; +derr2_stg_act_d <= ex6_dir_err_val_q; +derr3_stg_act_d <= derr2_stg_act_q; +derr4_stg_act_d <= derr3_stg_act_q; +derr5_stg_act_d <= derr4_stg_act_q; +-- #################################################### +-- Hit/Miss Detect +-- #################################################### +-- Execution Pipe Hit/Miss +ex3L1Hit: ex3_l1hit <= not hit_or_01234567_b; +ex3L1Miss: ex3_l1miss <= not ex3_l1hit; +ex3_hit <= not ex3_l1miss; +--ex4_miss_d <= ex3_l1miss; +ex4_miss <= not ex4_miss_q; +ex4_way_hit_d <= not (xu_op_hit_wayA_dly_b & xu_op_hit_wayB_dly_b & xu_op_hit_wayC_dly_b & xu_op_hit_wayD_dly_b & + xu_op_hit_wayE_dly_b & xu_op_hit_wayF_dly_b & xu_op_hit_wayG_dly_b & xu_op_hit_wayH_dly_b); +ex5_way_hit_d <= ex4_way_hit_q; +ex6_way_hit_d <= ex5_way_hit_q; +-- EX3 Way Hit Encode for upper address into Data Cache Array +ex3_xuop_up_addr_b <= hit_enc_b(0 to 2); +rel_dcarr_addr_sel <= (others=>rel_dcarr_addr_en); +rel_dcarr_addr_sel_b <= (others=>(not rel_dcarr_addr_en)); +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Back-Invalidated Watched/Locked Line detection, +-- I need to do it late since instructions in the ahead of +-- back-invalidate could have set the watch/lost bit +-- Back-Invalidate does not look at instructions ahead of pipe, +-- since they might get flushed and will get bad results +-- Also includes Multihit Error Detect case +-- Staging out congruence class compares +congr_cl_ex3_ex4_cmp_d <= congr_cl_ex2_ex3_cmp_q; +congr_cl_ex3_ex5_cmp_d <= congr_cl_ex2_ex4_cmp_q; +congr_cl_ex3_ex6_cmp_d <= congr_cl_ex2_ex5_cmp_q; +congr_cl_ex4_ex5_cmp_d <= congr_cl_ex3_ex4_cmp_q; +congr_cl_ex4_ex6_cmp_d <= congr_cl_ex3_ex5_cmp_q; +congr_cl_ex4_ex7_cmp_d <= congr_cl_ex3_ex6_cmp_q; +-- Ways updated in other stages +binv4_ex4_way_upd <= binv_wayA_upd1 & binv_wayB_upd1 & binv_wayC_upd1 & binv_wayD_upd1 & + binv_wayE_upd1 & binv_wayF_upd1 & binv_wayG_upd1 & binv_wayH_upd1; +binv5_ex5_way_upd <= binv_wayA_upd2_q & binv_wayB_upd2_q & binv_wayC_upd2_q & binv_wayD_upd2_q & + binv_wayE_upd2_q & binv_wayF_upd2_q & binv_wayG_upd2_q & binv_wayH_upd2_q; +binv6_ex6_way_upd <= binv_wayA_upd3_q & binv_wayB_upd3_q & binv_wayC_upd3_q & binv_wayD_upd3_q & + binv_wayE_upd3_q & binv_wayF_upd3_q & binv_wayG_upd3_q & binv_wayH_upd3_q; +binv7_ex7_way_upd_d <= binv6_ex6_way_upd; +-- Data of ways updated in other stages +binv4_ex4_dir_data <= gate(flush_wayA_data1(1 to 5), binv4_ex4_way_upd(0)) or gate(flush_wayB_data1(1 to 5), binv4_ex4_way_upd(1)) or + gate(flush_wayC_data1(1 to 5), binv4_ex4_way_upd(2)) or gate(flush_wayD_data1(1 to 5), binv4_ex4_way_upd(3)) or + gate(flush_wayE_data1(1 to 5), binv4_ex4_way_upd(4)) or gate(flush_wayF_data1(1 to 5), binv4_ex4_way_upd(5)) or + gate(flush_wayG_data1(1 to 5), binv4_ex4_way_upd(6)) or gate(flush_wayH_data1(1 to 5), binv4_ex4_way_upd(7)); +binv5_ex5_dir_data_d <= binv4_ex4_dir_data; +binv6_ex6_dir_data_d <= binv5_ex5_dir_data_q; +binv7_ex7_dir_data_d <= binv6_ex6_dir_data_q; +-- None Bypass Locked Line lost indicator +binv4_inval_lck <= inval_clr_lck and back_inval_stg4_q and not binv4_coll_val; +-- None Bypass Watch Lost indicator +binv4_inval_watch <= gate(ex4_lost_watch, (back_inval_stg4_q and not binv4_coll_val)); +-- Stage Bypass Select +binv4_ex5_coll <= (back_inval_stg4_q or ex4_dir_multihit_val) and congr_cl_ex4_ex5_cmp_q and or_reduce(ex4_way_hit_q and binv5_ex5_way_upd) and p0_wren_d; +binv4_ex6_coll <= (back_inval_stg4_q or ex4_dir_multihit_val) and congr_cl_ex4_ex6_cmp_q and or_reduce(ex4_way_hit_q and binv6_ex6_way_upd) and p0_wren_q; +binv4_ex7_coll <= (back_inval_stg4_q or ex4_dir_multihit_val) and congr_cl_ex4_ex7_cmp_q and or_reduce(ex4_way_hit_q and binv7_ex7_way_upd_q) and p0_wren_stg_q; +binv4_coll_val <= binv4_ex5_coll or binv4_ex6_coll or binv4_ex7_coll; +-- Priority Calculation +binv4_pri_byp_sel(0) <= binv4_ex5_coll; +binv4_pri_byp_sel(1) <= binv4_ex6_coll and not binv4_ex5_coll; +binv4_pri_byp_sel(2) <= binv4_ex7_coll and not (binv4_ex6_coll or binv4_ex5_coll); +-- Data Bypass +binv4_byp_dir_data <= gate(binv5_ex5_dir_data_q, binv4_pri_byp_sel(0)) or + gate(binv6_ex6_dir_data_q, binv4_pri_byp_sel(1)) or + gate(binv7_ex7_dir_data_q, binv4_pri_byp_sel(2)); +-- Back-Invalidate invalidated a watched line +binv5_inval_watch_val_d <= (binv4_byp_dir_data(2 to 5) and not binv4_ex4_dir_data(2 to 5)) or binv4_inval_watch; +-- Back-Invalidate invalidated a locked line +binv5_inval_lock_val_d <= (binv4_byp_dir_data(1) and not binv4_ex4_dir_data(1)) or binv4_inval_lck; +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Watch Lost due to DCI +dci_watch_lost <= (others=>dci_compl_q); +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- #################################################### +-- Resource Conflict Flushes +-- #################################################### +-- Determine if another thread is modifying any of the Directory bits, Need to flush if this thread targets same congruence class and way +congr_cl_ex3_upd_wayA <= congr_cl_ex2_ex3_cmp_q and not ex3_thrd_m_q and ex3_xuop_wayA_upd and not ex3_stg_flush; +congr_cl_ex4_upd_wayA <= congr_cl_ex2_ex4_cmp_q and not ex4_thrd_m_q and ex4_xuop_wayA_upd_q and not ex4_stg_flush; +congr_cl_ex5_upd_wayA <= congr_cl_ex2_ex5_cmp_q and not ex5_thrd_m_q and ex5_xuop_wayA_upd_q and not ex5_stg_flush; +congr_cl_m_upd_wayA_d <= congr_cl_ex3_upd_wayA or congr_cl_ex4_upd_wayA or congr_cl_ex5_upd_wayA; +-- causing a flush for the thread that matches congruence class and directory way being updated by a different thread +ex3_cClass_wayA_hit <= fxu_pipe_val and congr_cl_m_upd_wayA_q and wayA_val(0); +-- Determine if another thread is modifying any of the Directory bits, Need to flush if this thread targets same congruence class and way +congr_cl_ex3_upd_wayB <= congr_cl_ex2_ex3_cmp_q and not ex3_thrd_m_q and ex3_xuop_wayB_upd and not ex3_stg_flush; +congr_cl_ex4_upd_wayB <= congr_cl_ex2_ex4_cmp_q and not ex4_thrd_m_q and ex4_xuop_wayB_upd_q and not ex4_stg_flush; +congr_cl_ex5_upd_wayB <= congr_cl_ex2_ex5_cmp_q and not ex5_thrd_m_q and ex5_xuop_wayB_upd_q and not ex5_stg_flush; +congr_cl_m_upd_wayB_d <= congr_cl_ex3_upd_wayB or congr_cl_ex4_upd_wayB or congr_cl_ex5_upd_wayB; +-- causing a flush for the thread that matches congruence class and directory way being updated by a different thread +ex3_cClass_wayB_hit <= fxu_pipe_val and congr_cl_m_upd_wayB_q and wayB_val(0); +-- Determine if another thread is modifying any of the Directory bits, Need to flush if this thread targets same congruence class and way +congr_cl_ex3_upd_wayC <= congr_cl_ex2_ex3_cmp_q and not ex3_thrd_m_q and ex3_xuop_wayC_upd and not ex3_stg_flush; +congr_cl_ex4_upd_wayC <= congr_cl_ex2_ex4_cmp_q and not ex4_thrd_m_q and ex4_xuop_wayC_upd_q and not ex4_stg_flush; +congr_cl_ex5_upd_wayC <= congr_cl_ex2_ex5_cmp_q and not ex5_thrd_m_q and ex5_xuop_wayC_upd_q and not ex5_stg_flush; +congr_cl_m_upd_wayC_d <= congr_cl_ex3_upd_wayC or congr_cl_ex4_upd_wayC or congr_cl_ex5_upd_wayC; +-- causing a flush for the thread that matches congruence class and directory way being updated by a different thread +ex3_cClass_wayC_hit <= fxu_pipe_val and congr_cl_m_upd_wayC_q and wayC_val(0); +-- Determine if another thread is modifying any of the Directory bits, Need to flush if this thread targets same congruence class and way +congr_cl_ex3_upd_wayD <= congr_cl_ex2_ex3_cmp_q and not ex3_thrd_m_q and ex3_xuop_wayD_upd and not ex3_stg_flush; +congr_cl_ex4_upd_wayD <= congr_cl_ex2_ex4_cmp_q and not ex4_thrd_m_q and ex4_xuop_wayD_upd_q and not ex4_stg_flush; +congr_cl_ex5_upd_wayD <= congr_cl_ex2_ex5_cmp_q and not ex5_thrd_m_q and ex5_xuop_wayD_upd_q and not ex5_stg_flush; +congr_cl_m_upd_wayD_d <= congr_cl_ex3_upd_wayD or congr_cl_ex4_upd_wayD or congr_cl_ex5_upd_wayD; +-- causing a flush for the thread that matches congruence class and directory way being updated by a different thread +ex3_cClass_wayD_hit <= fxu_pipe_val and congr_cl_m_upd_wayD_q and wayD_val(0); +-- Determine if another thread is modifying any of the Directory bits, Need to flush if this thread targets same congruence class and way +congr_cl_ex3_upd_wayE <= congr_cl_ex2_ex3_cmp_q and not ex3_thrd_m_q and ex3_xuop_wayE_upd and not ex3_stg_flush; +congr_cl_ex4_upd_wayE <= congr_cl_ex2_ex4_cmp_q and not ex4_thrd_m_q and ex4_xuop_wayE_upd_q and not ex4_stg_flush; +congr_cl_ex5_upd_wayE <= congr_cl_ex2_ex5_cmp_q and not ex5_thrd_m_q and ex5_xuop_wayE_upd_q and not ex5_stg_flush; +congr_cl_m_upd_wayE_d <= congr_cl_ex3_upd_wayE or congr_cl_ex4_upd_wayE or congr_cl_ex5_upd_wayE; +-- causing a flush for the thread that matches congruence class and directory way being updated by a different thread +ex3_cClass_wayE_hit <= fxu_pipe_val and congr_cl_m_upd_wayE_q and wayE_val(0); +-- Determine if another thread is modifying any of the Directory bits, Need to flush if this thread targets same congruence class and way +congr_cl_ex3_upd_wayF <= congr_cl_ex2_ex3_cmp_q and not ex3_thrd_m_q and ex3_xuop_wayF_upd and not ex3_stg_flush; +congr_cl_ex4_upd_wayF <= congr_cl_ex2_ex4_cmp_q and not ex4_thrd_m_q and ex4_xuop_wayF_upd_q and not ex4_stg_flush; +congr_cl_ex5_upd_wayF <= congr_cl_ex2_ex5_cmp_q and not ex5_thrd_m_q and ex5_xuop_wayF_upd_q and not ex5_stg_flush; +congr_cl_m_upd_wayF_d <= congr_cl_ex3_upd_wayF or congr_cl_ex4_upd_wayF or congr_cl_ex5_upd_wayF; +-- causing a flush for the thread that matches congruence class and directory way being updated by a different thread +ex3_cClass_wayF_hit <= fxu_pipe_val and congr_cl_m_upd_wayF_q and wayF_val(0); +-- Determine if another thread is modifying any of the Directory bits, Need to flush if this thread targets same congruence class and way +congr_cl_ex3_upd_wayG <= congr_cl_ex2_ex3_cmp_q and not ex3_thrd_m_q and ex3_xuop_wayG_upd and not ex3_stg_flush; +congr_cl_ex4_upd_wayG <= congr_cl_ex2_ex4_cmp_q and not ex4_thrd_m_q and ex4_xuop_wayG_upd_q and not ex4_stg_flush; +congr_cl_ex5_upd_wayG <= congr_cl_ex2_ex5_cmp_q and not ex5_thrd_m_q and ex5_xuop_wayG_upd_q and not ex5_stg_flush; +congr_cl_m_upd_wayG_d <= congr_cl_ex3_upd_wayG or congr_cl_ex4_upd_wayG or congr_cl_ex5_upd_wayG; +-- causing a flush for the thread that matches congruence class and directory way being updated by a different thread +ex3_cClass_wayG_hit <= fxu_pipe_val and congr_cl_m_upd_wayG_q and wayG_val(0); +-- Determine if another thread is modifying any of the Directory bits, Need to flush if this thread targets same congruence class and way +congr_cl_ex3_upd_wayH <= congr_cl_ex2_ex3_cmp_q and not ex3_thrd_m_q and ex3_xuop_wayH_upd and not ex3_stg_flush; +congr_cl_ex4_upd_wayH <= congr_cl_ex2_ex4_cmp_q and not ex4_thrd_m_q and ex4_xuop_wayH_upd_q and not ex4_stg_flush; +congr_cl_ex5_upd_wayH <= congr_cl_ex2_ex5_cmp_q and not ex5_thrd_m_q and ex5_xuop_wayH_upd_q and not ex5_stg_flush; +congr_cl_m_upd_wayH_d <= congr_cl_ex3_upd_wayH or congr_cl_ex4_upd_wayH or congr_cl_ex5_upd_wayH; +-- causing a flush for the thread that matches congruence class and directory way being updated by a different thread +ex3_cClass_wayH_hit <= fxu_pipe_val and congr_cl_m_upd_wayH_q and wayH_val(0); +-- Watch Clear udate in the pipe for a different thread +ex3_wclr_all_upd_val <= ex3_watch_clr_all_q and not ex3_thrd_m_q and not ex3_stg_flush; +ex4_wclr_all_upd_val <= ex4_wclr_all_val_q and not ex4_thrd_m_q and not ex4_stg_flush; +ex5_wclr_all_upd_val <= ex5_wclr_all_val_q and not ex5_thrd_m_q and not ex5_stg_flush; +ex6_wclr_all_upd_val <= ex6_wclr_all_val_q and not ex6_thrd_m_q; +-- causing a flush for the thread that is trying to access the directory when a different thread is doing a watch clear all +ex3_wclr_all_upd_d <= ex3_wclr_all_upd_val or ex4_wclr_all_upd_val or ex5_wclr_all_upd_val or ex6_wclr_all_upd_val; +-- #################################################### +-- Reload Pipe +-- #################################################### +-- Reload Path Directory Valid Bits Muxing +-- Reload Stage 1 +-- Select Congruence Class Way A +with rel_congr_cl_q select + rel_arr_wayA_val <= + congr_cl0_wA_q when "00000", + congr_cl1_wA_q when "00001", + congr_cl2_wA_q when "00010", + congr_cl3_wA_q when "00011", + congr_cl4_wA_q when "00100", + congr_cl5_wA_q when "00101", + congr_cl6_wA_q when "00110", + congr_cl7_wA_q when "00111", + congr_cl8_wA_q when "01000", + congr_cl9_wA_q when "01001", + congr_cl10_wA_q when "01010", + congr_cl11_wA_q when "01011", + congr_cl12_wA_q when "01100", + congr_cl13_wA_q when "01101", + congr_cl14_wA_q when "01110", + congr_cl15_wA_q when "01111", + congr_cl16_wA_q when "10000", + congr_cl17_wA_q when "10001", + congr_cl18_wA_q when "10010", + congr_cl19_wA_q when "10011", + congr_cl20_wA_q when "10100", + congr_cl21_wA_q when "10101", + congr_cl22_wA_q when "10110", + congr_cl23_wA_q when "10111", + congr_cl24_wA_q when "11000", + congr_cl25_wA_q when "11001", + congr_cl26_wA_q when "11010", + congr_cl27_wA_q when "11011", + congr_cl28_wA_q when "11100", + congr_cl29_wA_q when "11101", + congr_cl30_wA_q when "11110", + congr_cl31_wA_q when others; +p1_arr_wayA_rd <= rel_arr_wayA_val; +-- Select Congruence Class Way B +with rel_congr_cl_q select + rel_arr_wayB_val <= + congr_cl0_wB_q when "00000", + congr_cl1_wB_q when "00001", + congr_cl2_wB_q when "00010", + congr_cl3_wB_q when "00011", + congr_cl4_wB_q when "00100", + congr_cl5_wB_q when "00101", + congr_cl6_wB_q when "00110", + congr_cl7_wB_q when "00111", + congr_cl8_wB_q when "01000", + congr_cl9_wB_q when "01001", + congr_cl10_wB_q when "01010", + congr_cl11_wB_q when "01011", + congr_cl12_wB_q when "01100", + congr_cl13_wB_q when "01101", + congr_cl14_wB_q when "01110", + congr_cl15_wB_q when "01111", + congr_cl16_wB_q when "10000", + congr_cl17_wB_q when "10001", + congr_cl18_wB_q when "10010", + congr_cl19_wB_q when "10011", + congr_cl20_wB_q when "10100", + congr_cl21_wB_q when "10101", + congr_cl22_wB_q when "10110", + congr_cl23_wB_q when "10111", + congr_cl24_wB_q when "11000", + congr_cl25_wB_q when "11001", + congr_cl26_wB_q when "11010", + congr_cl27_wB_q when "11011", + congr_cl28_wB_q when "11100", + congr_cl29_wB_q when "11101", + congr_cl30_wB_q when "11110", + congr_cl31_wB_q when others; +p1_arr_wayB_rd <= rel_arr_wayB_val; +-- Select Congruence Class Way C +with rel_congr_cl_q select + rel_arr_wayC_val <= + congr_cl0_wC_q when "00000", + congr_cl1_wC_q when "00001", + congr_cl2_wC_q when "00010", + congr_cl3_wC_q when "00011", + congr_cl4_wC_q when "00100", + congr_cl5_wC_q when "00101", + congr_cl6_wC_q when "00110", + congr_cl7_wC_q when "00111", + congr_cl8_wC_q when "01000", + congr_cl9_wC_q when "01001", + congr_cl10_wC_q when "01010", + congr_cl11_wC_q when "01011", + congr_cl12_wC_q when "01100", + congr_cl13_wC_q when "01101", + congr_cl14_wC_q when "01110", + congr_cl15_wC_q when "01111", + congr_cl16_wC_q when "10000", + congr_cl17_wC_q when "10001", + congr_cl18_wC_q when "10010", + congr_cl19_wC_q when "10011", + congr_cl20_wC_q when "10100", + congr_cl21_wC_q when "10101", + congr_cl22_wC_q when "10110", + congr_cl23_wC_q when "10111", + congr_cl24_wC_q when "11000", + congr_cl25_wC_q when "11001", + congr_cl26_wC_q when "11010", + congr_cl27_wC_q when "11011", + congr_cl28_wC_q when "11100", + congr_cl29_wC_q when "11101", + congr_cl30_wC_q when "11110", + congr_cl31_wC_q when others; +p1_arr_wayC_rd <= rel_arr_wayC_val; +-- Select Congruence Class Way D +with rel_congr_cl_q select + rel_arr_wayD_val <= + congr_cl0_wD_q when "00000", + congr_cl1_wD_q when "00001", + congr_cl2_wD_q when "00010", + congr_cl3_wD_q when "00011", + congr_cl4_wD_q when "00100", + congr_cl5_wD_q when "00101", + congr_cl6_wD_q when "00110", + congr_cl7_wD_q when "00111", + congr_cl8_wD_q when "01000", + congr_cl9_wD_q when "01001", + congr_cl10_wD_q when "01010", + congr_cl11_wD_q when "01011", + congr_cl12_wD_q when "01100", + congr_cl13_wD_q when "01101", + congr_cl14_wD_q when "01110", + congr_cl15_wD_q when "01111", + congr_cl16_wD_q when "10000", + congr_cl17_wD_q when "10001", + congr_cl18_wD_q when "10010", + congr_cl19_wD_q when "10011", + congr_cl20_wD_q when "10100", + congr_cl21_wD_q when "10101", + congr_cl22_wD_q when "10110", + congr_cl23_wD_q when "10111", + congr_cl24_wD_q when "11000", + congr_cl25_wD_q when "11001", + congr_cl26_wD_q when "11010", + congr_cl27_wD_q when "11011", + congr_cl28_wD_q when "11100", + congr_cl29_wD_q when "11101", + congr_cl30_wD_q when "11110", + congr_cl31_wD_q when others; +p1_arr_wayD_rd <= rel_arr_wayD_val; +-- Select Congruence Class Way E +with rel_congr_cl_q select + rel_arr_wayE_val <= + congr_cl0_wE_q when "00000", + congr_cl1_wE_q when "00001", + congr_cl2_wE_q when "00010", + congr_cl3_wE_q when "00011", + congr_cl4_wE_q when "00100", + congr_cl5_wE_q when "00101", + congr_cl6_wE_q when "00110", + congr_cl7_wE_q when "00111", + congr_cl8_wE_q when "01000", + congr_cl9_wE_q when "01001", + congr_cl10_wE_q when "01010", + congr_cl11_wE_q when "01011", + congr_cl12_wE_q when "01100", + congr_cl13_wE_q when "01101", + congr_cl14_wE_q when "01110", + congr_cl15_wE_q when "01111", + congr_cl16_wE_q when "10000", + congr_cl17_wE_q when "10001", + congr_cl18_wE_q when "10010", + congr_cl19_wE_q when "10011", + congr_cl20_wE_q when "10100", + congr_cl21_wE_q when "10101", + congr_cl22_wE_q when "10110", + congr_cl23_wE_q when "10111", + congr_cl24_wE_q when "11000", + congr_cl25_wE_q when "11001", + congr_cl26_wE_q when "11010", + congr_cl27_wE_q when "11011", + congr_cl28_wE_q when "11100", + congr_cl29_wE_q when "11101", + congr_cl30_wE_q when "11110", + congr_cl31_wE_q when others; +p1_arr_wayE_rd <= rel_arr_wayE_val; +-- Select Congruence Class Way F +with rel_congr_cl_q select + rel_arr_wayF_val <= + congr_cl0_wF_q when "00000", + congr_cl1_wF_q when "00001", + congr_cl2_wF_q when "00010", + congr_cl3_wF_q when "00011", + congr_cl4_wF_q when "00100", + congr_cl5_wF_q when "00101", + congr_cl6_wF_q when "00110", + congr_cl7_wF_q when "00111", + congr_cl8_wF_q when "01000", + congr_cl9_wF_q when "01001", + congr_cl10_wF_q when "01010", + congr_cl11_wF_q when "01011", + congr_cl12_wF_q when "01100", + congr_cl13_wF_q when "01101", + congr_cl14_wF_q when "01110", + congr_cl15_wF_q when "01111", + congr_cl16_wF_q when "10000", + congr_cl17_wF_q when "10001", + congr_cl18_wF_q when "10010", + congr_cl19_wF_q when "10011", + congr_cl20_wF_q when "10100", + congr_cl21_wF_q when "10101", + congr_cl22_wF_q when "10110", + congr_cl23_wF_q when "10111", + congr_cl24_wF_q when "11000", + congr_cl25_wF_q when "11001", + congr_cl26_wF_q when "11010", + congr_cl27_wF_q when "11011", + congr_cl28_wF_q when "11100", + congr_cl29_wF_q when "11101", + congr_cl30_wF_q when "11110", + congr_cl31_wF_q when others; +p1_arr_wayF_rd <= rel_arr_wayF_val; +-- Select Congruence Class Way G +with rel_congr_cl_q select + rel_arr_wayG_val <= + congr_cl0_wG_q when "00000", + congr_cl1_wG_q when "00001", + congr_cl2_wG_q when "00010", + congr_cl3_wG_q when "00011", + congr_cl4_wG_q when "00100", + congr_cl5_wG_q when "00101", + congr_cl6_wG_q when "00110", + congr_cl7_wG_q when "00111", + congr_cl8_wG_q when "01000", + congr_cl9_wG_q when "01001", + congr_cl10_wG_q when "01010", + congr_cl11_wG_q when "01011", + congr_cl12_wG_q when "01100", + congr_cl13_wG_q when "01101", + congr_cl14_wG_q when "01110", + congr_cl15_wG_q when "01111", + congr_cl16_wG_q when "10000", + congr_cl17_wG_q when "10001", + congr_cl18_wG_q when "10010", + congr_cl19_wG_q when "10011", + congr_cl20_wG_q when "10100", + congr_cl21_wG_q when "10101", + congr_cl22_wG_q when "10110", + congr_cl23_wG_q when "10111", + congr_cl24_wG_q when "11000", + congr_cl25_wG_q when "11001", + congr_cl26_wG_q when "11010", + congr_cl27_wG_q when "11011", + congr_cl28_wG_q when "11100", + congr_cl29_wG_q when "11101", + congr_cl30_wG_q when "11110", + congr_cl31_wG_q when others; +p1_arr_wayG_rd <= rel_arr_wayG_val; +-- Select Congruence Class Way H +with rel_congr_cl_q select + rel_arr_wayH_val <= + congr_cl0_wH_q when "00000", + congr_cl1_wH_q when "00001", + congr_cl2_wH_q when "00010", + congr_cl3_wH_q when "00011", + congr_cl4_wH_q when "00100", + congr_cl5_wH_q when "00101", + congr_cl6_wH_q when "00110", + congr_cl7_wH_q when "00111", + congr_cl8_wH_q when "01000", + congr_cl9_wH_q when "01001", + congr_cl10_wH_q when "01010", + congr_cl11_wH_q when "01011", + congr_cl12_wH_q when "01100", + congr_cl13_wH_q when "01101", + congr_cl14_wH_q when "01110", + congr_cl15_wH_q when "01111", + congr_cl16_wH_q when "10000", + congr_cl17_wH_q when "10001", + congr_cl18_wH_q when "10010", + congr_cl19_wH_q when "10011", + congr_cl20_wH_q when "10100", + congr_cl21_wH_q when "10101", + congr_cl22_wH_q when "10110", + congr_cl23_wH_q when "10111", + congr_cl24_wH_q when "11000", + congr_cl25_wH_q when "11001", + congr_cl26_wH_q when "11010", + congr_cl27_wH_q when "11011", + congr_cl28_wH_q when "11100", + congr_cl29_wH_q when "11101", + congr_cl30_wH_q when "11110", + congr_cl31_wH_q when others; +p1_arr_wayH_rd <= rel_arr_wayH_val; +-- #################################################### +-- Reload Pipe Bypass +-- #################################################### +-- Reload13 Bypass Stages +-- Determine if there is any updates in later stages to the same congruence class +congr_cl_rel13_ex3_cmp_d <= (rel_early_congr_cl = ex2_congr_cl_q); +congr_cl_rel13_ex4_cmp_d <= (rel_early_congr_cl = ex3_congr_cl_q); +congr_cl_rel13_ex5_cmp_d <= (rel_early_congr_cl = ex4_congr_cl_q); +congr_cl_rel13_ex6_cmp_d <= (rel_early_congr_cl = ex5_congr_cl_q); +congr_cl_rel13_relu_cmp_d <= (rel_early_congr_cl = rel24_congr_cl_q); +congr_cl_rel13_relu_s_cmp_d <= (rel_early_congr_cl = relu_congr_cl_q); +congr_cl_rel13_rel_upd_cmp_d <= (rel_early_congr_cl = relu_s_congr_cl_q); +congr_cl_rel13_p0_cmp <= congr_cl_rel13_ex6_cmp_q and p0_wren_cpy_q; +congr_cl_rel13_p1_cmp <= congr_cl_rel13_rel_upd_cmp_q and p1_wren_cpy_q; +-- Determine if there is any updates in later stages to the same congruence class +congr_cl_rel13_ex3_m <= congr_cl_rel13_ex3_cmp_q and (ex3_lock_set_q or back_inval_stg3_q); +congr_cl_rel13_ex4_m <= congr_cl_rel13_ex4_cmp_q and (ex4_lock_set_q or back_inval_stg4_q); +congr_cl_rel13_ex5_m <= congr_cl_rel13_ex5_cmp_q and (ex5_lock_set_q or back_inval_stg5_q); +congr_cl_rel13_relu_m <= congr_cl_rel13_relu_cmp_q and rel_val_stgu_q; +congr_cl_rel13_relu_s_m <= congr_cl_rel13_relu_s_cmp_q and p1_upd_val; +-- WayA Bypass Calculation +congr_cl_rel13_wayA_byp(1) <= congr_cl_rel13_ex3_m and ex3_wayA_hit; +congr_cl_rel13_wayA_byp(2) <= congr_cl_rel13_relu_m and reload_wayA_upd_q; +congr_cl_rel13_wayA_byp(3) <= congr_cl_rel13_ex4_m and binv_wayA_upd_q; +congr_cl_rel13_wayA_byp(4) <= congr_cl_rel13_relu_s_m and reload_wayA_upd2_q; +congr_cl_rel13_wayA_byp(5) <= congr_cl_rel13_ex5_m and binv_wayA_upd2_q; +congr_cl_rel13_wayA_byp(6) <= congr_cl_rel13_p1_cmp and reload_wayA_upd3_q; +congr_cl_rel13_wayA_byp(7) <= congr_cl_rel13_p0_cmp and binv_wayA_upd3_q; +-- WayA Bypass Valid +rel24_wayA_fxubyp_val_d <= congr_cl_rel13_wayA_byp(1) or congr_cl_rel13_wayA_byp(3) or + congr_cl_rel13_wayA_byp(5) or congr_cl_rel13_wayA_byp(7); +rel24_wayA_relbyp_val_d <= congr_cl_rel13_wayA_byp(2) or congr_cl_rel13_wayA_byp(4) or + congr_cl_rel13_wayA_byp(6); +rel24_wayA_byp_sel <= rel24_wayA_fxubyp_val_q & rel24_wayA_relbyp_val_q; +-- Late Stages Priority Selection +congr_cl_rel13_wayA_sel(2) <= congr_cl_rel13_wayA_byp(2); +congr_cl_rel13_wayA_sel(3) <= congr_cl_rel13_wayA_byp(3) and not congr_cl_rel13_wayA_byp(2); +congr_cl_rel13_wayA_sel(4) <= congr_cl_rel13_wayA_byp(4) and not or_reduce(congr_cl_rel13_wayA_byp(2 to 3)); +congr_cl_rel13_wayA_sel(5) <= congr_cl_rel13_wayA_byp(5) and not or_reduce(congr_cl_rel13_wayA_byp(2 to 4)); +congr_cl_rel13_wayA_sel(6) <= congr_cl_rel13_wayA_byp(6) and not or_reduce(congr_cl_rel13_wayA_byp(2 to 5)); +congr_cl_rel13_wayA_sel(7) <= congr_cl_rel13_wayA_byp(7) and not or_reduce(congr_cl_rel13_wayA_byp(2 to 6)); +-- ArrayRead/LATE Stage Priority Selection +rel_wayA_late_sel <= or_reduce(congr_cl_rel13_wayA_byp(2 to 7)); +rel_wayA_later_stg_pri <= gate(p1_arr_wayA_rd, not rel_wayA_late_sel) or + gate(reload_wayA, congr_cl_rel13_wayA_sel(2)) or + gate(flush_wayA_q, congr_cl_rel13_wayA_sel(3)) or + gate(reload_wayA_data_q, congr_cl_rel13_wayA_sel(4)) or + gate(flush_wayA_data_q, congr_cl_rel13_wayA_sel(5)) or + gate(reload_wayA_data2_q, congr_cl_rel13_wayA_sel(6)) or + gate(flush_wayA_data2_q, congr_cl_rel13_wayA_sel(7)); +-- EX3/RELU Stage Priority Selection +rel_wayA_early_sel <= congr_cl_rel13_wayA_byp(1); +rel_wayA_early_stg_pri <= flush_wayA_d; +-- Stage/ARRAY Priority Selection +rel_wayA_stg_val <= (others=>(rel_wayA_early_sel)); +rel_wayA_stg_val_b <= (others=>(not(rel_wayA_early_sel))); +rel_wayA_val <= not rel_wayA_val_b_q; +rel_wayA_val_stg_d <= rel_wayA_val; +-- WayB Bypass Calculation +congr_cl_rel13_wayB_byp(1) <= congr_cl_rel13_ex3_m and ex3_wayB_hit; +congr_cl_rel13_wayB_byp(2) <= congr_cl_rel13_relu_m and reload_wayB_upd_q; +congr_cl_rel13_wayB_byp(3) <= congr_cl_rel13_ex4_m and binv_wayB_upd_q; +congr_cl_rel13_wayB_byp(4) <= congr_cl_rel13_relu_s_m and reload_wayB_upd2_q; +congr_cl_rel13_wayB_byp(5) <= congr_cl_rel13_ex5_m and binv_wayB_upd2_q; +congr_cl_rel13_wayB_byp(6) <= congr_cl_rel13_p1_cmp and reload_wayB_upd3_q; +congr_cl_rel13_wayB_byp(7) <= congr_cl_rel13_p0_cmp and binv_wayB_upd3_q; +-- WayB Bypass Valid +rel24_wayB_fxubyp_val_d <= congr_cl_rel13_wayB_byp(1) or congr_cl_rel13_wayB_byp(3) or + congr_cl_rel13_wayB_byp(5) or congr_cl_rel13_wayB_byp(7); +rel24_wayB_relbyp_val_d <= congr_cl_rel13_wayB_byp(2) or congr_cl_rel13_wayB_byp(4) or + congr_cl_rel13_wayB_byp(6); +rel24_wayB_byp_sel <= rel24_wayB_fxubyp_val_q & rel24_wayB_relbyp_val_q; +-- Late Stages Priority Selection +congr_cl_rel13_wayB_sel(2) <= congr_cl_rel13_wayB_byp(2); +congr_cl_rel13_wayB_sel(3) <= congr_cl_rel13_wayB_byp(3) and not congr_cl_rel13_wayB_byp(2); +congr_cl_rel13_wayB_sel(4) <= congr_cl_rel13_wayB_byp(4) and not or_reduce(congr_cl_rel13_wayB_byp(2 to 3)); +congr_cl_rel13_wayB_sel(5) <= congr_cl_rel13_wayB_byp(5) and not or_reduce(congr_cl_rel13_wayB_byp(2 to 4)); +congr_cl_rel13_wayB_sel(6) <= congr_cl_rel13_wayB_byp(6) and not or_reduce(congr_cl_rel13_wayB_byp(2 to 5)); +congr_cl_rel13_wayB_sel(7) <= congr_cl_rel13_wayB_byp(7) and not or_reduce(congr_cl_rel13_wayB_byp(2 to 6)); +-- ArrayRead/LATE Stage Priority Selection +rel_wayB_late_sel <= or_reduce(congr_cl_rel13_wayB_byp(2 to 7)); +rel_wayB_later_stg_pri <= gate(p1_arr_wayB_rd, not rel_wayB_late_sel) or + gate(reload_wayB, congr_cl_rel13_wayB_sel(2)) or + gate(flush_wayB_q, congr_cl_rel13_wayB_sel(3)) or + gate(reload_wayB_data_q, congr_cl_rel13_wayB_sel(4)) or + gate(flush_wayB_data_q, congr_cl_rel13_wayB_sel(5)) or + gate(reload_wayB_data2_q, congr_cl_rel13_wayB_sel(6)) or + gate(flush_wayB_data2_q, congr_cl_rel13_wayB_sel(7)); +-- EX3/RELU Stage Priority Selection +rel_wayB_early_sel <= congr_cl_rel13_wayB_byp(1); +rel_wayB_early_stg_pri <= flush_wayB_d; +-- Stage/ARRAY Priority Selection +rel_wayB_stg_val <= (others=>(rel_wayB_early_sel)); +rel_wayB_stg_val_b <= (others=>(not(rel_wayB_early_sel))); +rel_wayB_val <= not rel_wayB_val_b_q; +rel_wayB_val_stg_d <= rel_wayB_val; +-- WayC Bypass Calculation +congr_cl_rel13_wayC_byp(1) <= congr_cl_rel13_ex3_m and ex3_wayC_hit; +congr_cl_rel13_wayC_byp(2) <= congr_cl_rel13_relu_m and reload_wayC_upd_q; +congr_cl_rel13_wayC_byp(3) <= congr_cl_rel13_ex4_m and binv_wayC_upd_q; +congr_cl_rel13_wayC_byp(4) <= congr_cl_rel13_relu_s_m and reload_wayC_upd2_q; +congr_cl_rel13_wayC_byp(5) <= congr_cl_rel13_ex5_m and binv_wayC_upd2_q; +congr_cl_rel13_wayC_byp(6) <= congr_cl_rel13_p1_cmp and reload_wayC_upd3_q; +congr_cl_rel13_wayC_byp(7) <= congr_cl_rel13_p0_cmp and binv_wayC_upd3_q; +-- WayC Bypass Valid +rel24_wayC_fxubyp_val_d <= congr_cl_rel13_wayC_byp(1) or congr_cl_rel13_wayC_byp(3) or + congr_cl_rel13_wayC_byp(5) or congr_cl_rel13_wayC_byp(7); +rel24_wayC_relbyp_val_d <= congr_cl_rel13_wayC_byp(2) or congr_cl_rel13_wayC_byp(4) or + congr_cl_rel13_wayC_byp(6); +rel24_wayC_byp_sel <= rel24_wayC_fxubyp_val_q & rel24_wayC_relbyp_val_q; +-- Late Stages Priority Selection +congr_cl_rel13_wayC_sel(2) <= congr_cl_rel13_wayC_byp(2); +congr_cl_rel13_wayC_sel(3) <= congr_cl_rel13_wayC_byp(3) and not congr_cl_rel13_wayC_byp(2); +congr_cl_rel13_wayC_sel(4) <= congr_cl_rel13_wayC_byp(4) and not or_reduce(congr_cl_rel13_wayC_byp(2 to 3)); +congr_cl_rel13_wayC_sel(5) <= congr_cl_rel13_wayC_byp(5) and not or_reduce(congr_cl_rel13_wayC_byp(2 to 4)); +congr_cl_rel13_wayC_sel(6) <= congr_cl_rel13_wayC_byp(6) and not or_reduce(congr_cl_rel13_wayC_byp(2 to 5)); +congr_cl_rel13_wayC_sel(7) <= congr_cl_rel13_wayC_byp(7) and not or_reduce(congr_cl_rel13_wayC_byp(2 to 6)); +-- ArrayRead/LATE Stage Priority Selection +rel_wayC_late_sel <= or_reduce(congr_cl_rel13_wayC_byp(2 to 7)); +rel_wayC_later_stg_pri <= gate(p1_arr_wayC_rd, not rel_wayC_late_sel) or + gate(reload_wayC, congr_cl_rel13_wayC_sel(2)) or + gate(flush_wayC_q, congr_cl_rel13_wayC_sel(3)) or + gate(reload_wayC_data_q, congr_cl_rel13_wayC_sel(4)) or + gate(flush_wayC_data_q, congr_cl_rel13_wayC_sel(5)) or + gate(reload_wayC_data2_q, congr_cl_rel13_wayC_sel(6)) or + gate(flush_wayC_data2_q, congr_cl_rel13_wayC_sel(7)); +-- EX3/RELU Stage Priority Selection +rel_wayC_early_sel <= congr_cl_rel13_wayC_byp(1); +rel_wayC_early_stg_pri <= flush_wayC_d; +-- Stage/ARRAY Priority Selection +rel_wayC_stg_val <= (others=>(rel_wayC_early_sel)); +rel_wayC_stg_val_b <= (others=>(not(rel_wayC_early_sel))); +rel_wayC_val <= not rel_wayC_val_b_q; +rel_wayC_val_stg_d <= rel_wayC_val; +-- WayD Bypass Calculation +congr_cl_rel13_wayD_byp(1) <= congr_cl_rel13_ex3_m and ex3_wayD_hit; +congr_cl_rel13_wayD_byp(2) <= congr_cl_rel13_relu_m and reload_wayD_upd_q; +congr_cl_rel13_wayD_byp(3) <= congr_cl_rel13_ex4_m and binv_wayD_upd_q; +congr_cl_rel13_wayD_byp(4) <= congr_cl_rel13_relu_s_m and reload_wayD_upd2_q; +congr_cl_rel13_wayD_byp(5) <= congr_cl_rel13_ex5_m and binv_wayD_upd2_q; +congr_cl_rel13_wayD_byp(6) <= congr_cl_rel13_p1_cmp and reload_wayD_upd3_q; +congr_cl_rel13_wayD_byp(7) <= congr_cl_rel13_p0_cmp and binv_wayD_upd3_q; +-- WayD Bypass Valid +rel24_wayD_fxubyp_val_d <= congr_cl_rel13_wayD_byp(1) or congr_cl_rel13_wayD_byp(3) or + congr_cl_rel13_wayD_byp(5) or congr_cl_rel13_wayD_byp(7); +rel24_wayD_relbyp_val_d <= congr_cl_rel13_wayD_byp(2) or congr_cl_rel13_wayD_byp(4) or + congr_cl_rel13_wayD_byp(6); +rel24_wayD_byp_sel <= rel24_wayD_fxubyp_val_q & rel24_wayD_relbyp_val_q; +-- Late Stages Priority Selection +congr_cl_rel13_wayD_sel(2) <= congr_cl_rel13_wayD_byp(2); +congr_cl_rel13_wayD_sel(3) <= congr_cl_rel13_wayD_byp(3) and not congr_cl_rel13_wayD_byp(2); +congr_cl_rel13_wayD_sel(4) <= congr_cl_rel13_wayD_byp(4) and not or_reduce(congr_cl_rel13_wayD_byp(2 to 3)); +congr_cl_rel13_wayD_sel(5) <= congr_cl_rel13_wayD_byp(5) and not or_reduce(congr_cl_rel13_wayD_byp(2 to 4)); +congr_cl_rel13_wayD_sel(6) <= congr_cl_rel13_wayD_byp(6) and not or_reduce(congr_cl_rel13_wayD_byp(2 to 5)); +congr_cl_rel13_wayD_sel(7) <= congr_cl_rel13_wayD_byp(7) and not or_reduce(congr_cl_rel13_wayD_byp(2 to 6)); +-- ArrayRead/LATE Stage Priority Selection +rel_wayD_late_sel <= or_reduce(congr_cl_rel13_wayD_byp(2 to 7)); +rel_wayD_later_stg_pri <= gate(p1_arr_wayD_rd, not rel_wayD_late_sel) or + gate(reload_wayD, congr_cl_rel13_wayD_sel(2)) or + gate(flush_wayD_q, congr_cl_rel13_wayD_sel(3)) or + gate(reload_wayD_data_q, congr_cl_rel13_wayD_sel(4)) or + gate(flush_wayD_data_q, congr_cl_rel13_wayD_sel(5)) or + gate(reload_wayD_data2_q, congr_cl_rel13_wayD_sel(6)) or + gate(flush_wayD_data2_q, congr_cl_rel13_wayD_sel(7)); +-- EX3/RELU Stage Priority Selection +rel_wayD_early_sel <= congr_cl_rel13_wayD_byp(1); +rel_wayD_early_stg_pri <= flush_wayD_d; +-- Stage/ARRAY Priority Selection +rel_wayD_stg_val <= (others=>(rel_wayD_early_sel)); +rel_wayD_stg_val_b <= (others=>(not(rel_wayD_early_sel))); +rel_wayD_val <= not rel_wayD_val_b_q; +rel_wayD_val_stg_d <= rel_wayD_val; +-- WayE Bypass Calculation +congr_cl_rel13_wayE_byp(1) <= congr_cl_rel13_ex3_m and ex3_wayE_hit; +congr_cl_rel13_wayE_byp(2) <= congr_cl_rel13_relu_m and reload_wayE_upd_q; +congr_cl_rel13_wayE_byp(3) <= congr_cl_rel13_ex4_m and binv_wayE_upd_q; +congr_cl_rel13_wayE_byp(4) <= congr_cl_rel13_relu_s_m and reload_wayE_upd2_q; +congr_cl_rel13_wayE_byp(5) <= congr_cl_rel13_ex5_m and binv_wayE_upd2_q; +congr_cl_rel13_wayE_byp(6) <= congr_cl_rel13_p1_cmp and reload_wayE_upd3_q; +congr_cl_rel13_wayE_byp(7) <= congr_cl_rel13_p0_cmp and binv_wayE_upd3_q; +-- WayE Bypass Valid +rel24_wayE_fxubyp_val_d <= congr_cl_rel13_wayE_byp(1) or congr_cl_rel13_wayE_byp(3) or + congr_cl_rel13_wayE_byp(5) or congr_cl_rel13_wayE_byp(7); +rel24_wayE_relbyp_val_d <= congr_cl_rel13_wayE_byp(2) or congr_cl_rel13_wayE_byp(4) or + congr_cl_rel13_wayE_byp(6); +rel24_wayE_byp_sel <= rel24_wayE_fxubyp_val_q & rel24_wayE_relbyp_val_q; +-- Late Stages Priority Selection +congr_cl_rel13_wayE_sel(2) <= congr_cl_rel13_wayE_byp(2); +congr_cl_rel13_wayE_sel(3) <= congr_cl_rel13_wayE_byp(3) and not congr_cl_rel13_wayE_byp(2); +congr_cl_rel13_wayE_sel(4) <= congr_cl_rel13_wayE_byp(4) and not or_reduce(congr_cl_rel13_wayE_byp(2 to 3)); +congr_cl_rel13_wayE_sel(5) <= congr_cl_rel13_wayE_byp(5) and not or_reduce(congr_cl_rel13_wayE_byp(2 to 4)); +congr_cl_rel13_wayE_sel(6) <= congr_cl_rel13_wayE_byp(6) and not or_reduce(congr_cl_rel13_wayE_byp(2 to 5)); +congr_cl_rel13_wayE_sel(7) <= congr_cl_rel13_wayE_byp(7) and not or_reduce(congr_cl_rel13_wayE_byp(2 to 6)); +-- ArrayRead/LATE Stage Priority Selection +rel_wayE_late_sel <= or_reduce(congr_cl_rel13_wayE_byp(2 to 7)); +rel_wayE_later_stg_pri <= gate(p1_arr_wayE_rd, not rel_wayE_late_sel) or + gate(reload_wayE, congr_cl_rel13_wayE_sel(2)) or + gate(flush_wayE_q, congr_cl_rel13_wayE_sel(3)) or + gate(reload_wayE_data_q, congr_cl_rel13_wayE_sel(4)) or + gate(flush_wayE_data_q, congr_cl_rel13_wayE_sel(5)) or + gate(reload_wayE_data2_q, congr_cl_rel13_wayE_sel(6)) or + gate(flush_wayE_data2_q, congr_cl_rel13_wayE_sel(7)); +-- EX3/RELU Stage Priority Selection +rel_wayE_early_sel <= congr_cl_rel13_wayE_byp(1); +rel_wayE_early_stg_pri <= flush_wayE_d; +-- Stage/ARRAY Priority Selection +rel_wayE_stg_val <= (others=>(rel_wayE_early_sel)); +rel_wayE_stg_val_b <= (others=>(not(rel_wayE_early_sel))); +rel_wayE_val <= not rel_wayE_val_b_q; +rel_wayE_val_stg_d <= rel_wayE_val; +-- WayF Bypass Calculation +congr_cl_rel13_wayF_byp(1) <= congr_cl_rel13_ex3_m and ex3_wayF_hit; +congr_cl_rel13_wayF_byp(2) <= congr_cl_rel13_relu_m and reload_wayF_upd_q; +congr_cl_rel13_wayF_byp(3) <= congr_cl_rel13_ex4_m and binv_wayF_upd_q; +congr_cl_rel13_wayF_byp(4) <= congr_cl_rel13_relu_s_m and reload_wayF_upd2_q; +congr_cl_rel13_wayF_byp(5) <= congr_cl_rel13_ex5_m and binv_wayF_upd2_q; +congr_cl_rel13_wayF_byp(6) <= congr_cl_rel13_p1_cmp and reload_wayF_upd3_q; +congr_cl_rel13_wayF_byp(7) <= congr_cl_rel13_p0_cmp and binv_wayF_upd3_q; +-- WayF Bypass Valid +rel24_wayF_fxubyp_val_d <= congr_cl_rel13_wayF_byp(1) or congr_cl_rel13_wayF_byp(3) or + congr_cl_rel13_wayF_byp(5) or congr_cl_rel13_wayF_byp(7); +rel24_wayF_relbyp_val_d <= congr_cl_rel13_wayF_byp(2) or congr_cl_rel13_wayF_byp(4) or + congr_cl_rel13_wayF_byp(6); +rel24_wayF_byp_sel <= rel24_wayF_fxubyp_val_q & rel24_wayF_relbyp_val_q; +-- Late Stages Priority Selection +congr_cl_rel13_wayF_sel(2) <= congr_cl_rel13_wayF_byp(2); +congr_cl_rel13_wayF_sel(3) <= congr_cl_rel13_wayF_byp(3) and not congr_cl_rel13_wayF_byp(2); +congr_cl_rel13_wayF_sel(4) <= congr_cl_rel13_wayF_byp(4) and not or_reduce(congr_cl_rel13_wayF_byp(2 to 3)); +congr_cl_rel13_wayF_sel(5) <= congr_cl_rel13_wayF_byp(5) and not or_reduce(congr_cl_rel13_wayF_byp(2 to 4)); +congr_cl_rel13_wayF_sel(6) <= congr_cl_rel13_wayF_byp(6) and not or_reduce(congr_cl_rel13_wayF_byp(2 to 5)); +congr_cl_rel13_wayF_sel(7) <= congr_cl_rel13_wayF_byp(7) and not or_reduce(congr_cl_rel13_wayF_byp(2 to 6)); +-- ArrayRead/LATE Stage Priority Selection +rel_wayF_late_sel <= or_reduce(congr_cl_rel13_wayF_byp(2 to 7)); +rel_wayF_later_stg_pri <= gate(p1_arr_wayF_rd, not rel_wayF_late_sel) or + gate(reload_wayF, congr_cl_rel13_wayF_sel(2)) or + gate(flush_wayF_q, congr_cl_rel13_wayF_sel(3)) or + gate(reload_wayF_data_q, congr_cl_rel13_wayF_sel(4)) or + gate(flush_wayF_data_q, congr_cl_rel13_wayF_sel(5)) or + gate(reload_wayF_data2_q, congr_cl_rel13_wayF_sel(6)) or + gate(flush_wayF_data2_q, congr_cl_rel13_wayF_sel(7)); +-- EX3/RELU Stage Priority Selection +rel_wayF_early_sel <= congr_cl_rel13_wayF_byp(1); +rel_wayF_early_stg_pri <= flush_wayF_d; +-- Stage/ARRAY Priority Selection +rel_wayF_stg_val <= (others=>(rel_wayF_early_sel)); +rel_wayF_stg_val_b <= (others=>(not(rel_wayF_early_sel))); +rel_wayF_val <= not rel_wayF_val_b_q; +rel_wayF_val_stg_d <= rel_wayF_val; +-- WayG Bypass Calculation +congr_cl_rel13_wayG_byp(1) <= congr_cl_rel13_ex3_m and ex3_wayG_hit; +congr_cl_rel13_wayG_byp(2) <= congr_cl_rel13_relu_m and reload_wayG_upd_q; +congr_cl_rel13_wayG_byp(3) <= congr_cl_rel13_ex4_m and binv_wayG_upd_q; +congr_cl_rel13_wayG_byp(4) <= congr_cl_rel13_relu_s_m and reload_wayG_upd2_q; +congr_cl_rel13_wayG_byp(5) <= congr_cl_rel13_ex5_m and binv_wayG_upd2_q; +congr_cl_rel13_wayG_byp(6) <= congr_cl_rel13_p1_cmp and reload_wayG_upd3_q; +congr_cl_rel13_wayG_byp(7) <= congr_cl_rel13_p0_cmp and binv_wayG_upd3_q; +-- WayG Bypass Valid +rel24_wayG_fxubyp_val_d <= congr_cl_rel13_wayG_byp(1) or congr_cl_rel13_wayG_byp(3) or + congr_cl_rel13_wayG_byp(5) or congr_cl_rel13_wayG_byp(7); +rel24_wayG_relbyp_val_d <= congr_cl_rel13_wayG_byp(2) or congr_cl_rel13_wayG_byp(4) or + congr_cl_rel13_wayG_byp(6); +rel24_wayG_byp_sel <= rel24_wayG_fxubyp_val_q & rel24_wayG_relbyp_val_q; +-- Late Stages Priority Selection +congr_cl_rel13_wayG_sel(2) <= congr_cl_rel13_wayG_byp(2); +congr_cl_rel13_wayG_sel(3) <= congr_cl_rel13_wayG_byp(3) and not congr_cl_rel13_wayG_byp(2); +congr_cl_rel13_wayG_sel(4) <= congr_cl_rel13_wayG_byp(4) and not or_reduce(congr_cl_rel13_wayG_byp(2 to 3)); +congr_cl_rel13_wayG_sel(5) <= congr_cl_rel13_wayG_byp(5) and not or_reduce(congr_cl_rel13_wayG_byp(2 to 4)); +congr_cl_rel13_wayG_sel(6) <= congr_cl_rel13_wayG_byp(6) and not or_reduce(congr_cl_rel13_wayG_byp(2 to 5)); +congr_cl_rel13_wayG_sel(7) <= congr_cl_rel13_wayG_byp(7) and not or_reduce(congr_cl_rel13_wayG_byp(2 to 6)); +-- ArrayRead/LATE Stage Priority Selection +rel_wayG_late_sel <= or_reduce(congr_cl_rel13_wayG_byp(2 to 7)); +rel_wayG_later_stg_pri <= gate(p1_arr_wayG_rd, not rel_wayG_late_sel) or + gate(reload_wayG, congr_cl_rel13_wayG_sel(2)) or + gate(flush_wayG_q, congr_cl_rel13_wayG_sel(3)) or + gate(reload_wayG_data_q, congr_cl_rel13_wayG_sel(4)) or + gate(flush_wayG_data_q, congr_cl_rel13_wayG_sel(5)) or + gate(reload_wayG_data2_q, congr_cl_rel13_wayG_sel(6)) or + gate(flush_wayG_data2_q, congr_cl_rel13_wayG_sel(7)); +-- EX3/RELU Stage Priority Selection +rel_wayG_early_sel <= congr_cl_rel13_wayG_byp(1); +rel_wayG_early_stg_pri <= flush_wayG_d; +-- Stage/ARRAY Priority Selection +rel_wayG_stg_val <= (others=>(rel_wayG_early_sel)); +rel_wayG_stg_val_b <= (others=>(not(rel_wayG_early_sel))); +rel_wayG_val <= not rel_wayG_val_b_q; +rel_wayG_val_stg_d <= rel_wayG_val; +-- WayH Bypass Calculation +congr_cl_rel13_wayH_byp(1) <= congr_cl_rel13_ex3_m and ex3_wayH_hit; +congr_cl_rel13_wayH_byp(2) <= congr_cl_rel13_relu_m and reload_wayH_upd_q; +congr_cl_rel13_wayH_byp(3) <= congr_cl_rel13_ex4_m and binv_wayH_upd_q; +congr_cl_rel13_wayH_byp(4) <= congr_cl_rel13_relu_s_m and reload_wayH_upd2_q; +congr_cl_rel13_wayH_byp(5) <= congr_cl_rel13_ex5_m and binv_wayH_upd2_q; +congr_cl_rel13_wayH_byp(6) <= congr_cl_rel13_p1_cmp and reload_wayH_upd3_q; +congr_cl_rel13_wayH_byp(7) <= congr_cl_rel13_p0_cmp and binv_wayH_upd3_q; +-- WayH Bypass Valid +rel24_wayH_fxubyp_val_d <= congr_cl_rel13_wayH_byp(1) or congr_cl_rel13_wayH_byp(3) or + congr_cl_rel13_wayH_byp(5) or congr_cl_rel13_wayH_byp(7); +rel24_wayH_relbyp_val_d <= congr_cl_rel13_wayH_byp(2) or congr_cl_rel13_wayH_byp(4) or + congr_cl_rel13_wayH_byp(6); +rel24_wayH_byp_sel <= rel24_wayH_fxubyp_val_q & rel24_wayH_relbyp_val_q; +-- Late Stages Priority Selection +congr_cl_rel13_wayH_sel(2) <= congr_cl_rel13_wayH_byp(2); +congr_cl_rel13_wayH_sel(3) <= congr_cl_rel13_wayH_byp(3) and not congr_cl_rel13_wayH_byp(2); +congr_cl_rel13_wayH_sel(4) <= congr_cl_rel13_wayH_byp(4) and not or_reduce(congr_cl_rel13_wayH_byp(2 to 3)); +congr_cl_rel13_wayH_sel(5) <= congr_cl_rel13_wayH_byp(5) and not or_reduce(congr_cl_rel13_wayH_byp(2 to 4)); +congr_cl_rel13_wayH_sel(6) <= congr_cl_rel13_wayH_byp(6) and not or_reduce(congr_cl_rel13_wayH_byp(2 to 5)); +congr_cl_rel13_wayH_sel(7) <= congr_cl_rel13_wayH_byp(7) and not or_reduce(congr_cl_rel13_wayH_byp(2 to 6)); +-- ArrayRead/LATE Stage Priority Selection +rel_wayH_late_sel <= or_reduce(congr_cl_rel13_wayH_byp(2 to 7)); +rel_wayH_later_stg_pri <= gate(p1_arr_wayH_rd, not rel_wayH_late_sel) or + gate(reload_wayH, congr_cl_rel13_wayH_sel(2)) or + gate(flush_wayH_q, congr_cl_rel13_wayH_sel(3)) or + gate(reload_wayH_data_q, congr_cl_rel13_wayH_sel(4)) or + gate(flush_wayH_data_q, congr_cl_rel13_wayH_sel(5)) or + gate(reload_wayH_data2_q, congr_cl_rel13_wayH_sel(6)) or + gate(flush_wayH_data2_q, congr_cl_rel13_wayH_sel(7)); +-- EX3/RELU Stage Priority Selection +rel_wayH_early_sel <= congr_cl_rel13_wayH_byp(1); +rel_wayH_early_stg_pri <= flush_wayH_d; +-- Stage/ARRAY Priority Selection +rel_wayH_stg_val <= (others=>(rel_wayH_early_sel)); +rel_wayH_stg_val_b <= (others=>(not(rel_wayH_early_sel))); +rel_wayH_val <= not rel_wayH_val_b_q; +rel_wayH_val_stg_d <= rel_wayH_val; +-- #################################################### +-- Reload Invalidate/Reload Validate Pipes +-- #################################################### +-- Invalidate Way +rel_par_wA_clr <= rel_wayA_clr or dcpar_err_way_inval_q(0); +-- Invalidate/Reload Logic on Port1 +reload_wayA_d(0) <= (not rel_par_wA_clr and rel_wayA_val(0)) or rel_wayA_set; +-- Lock Clear/Set Logic on Port1 +reload_wayA_d(1) <= (not rel_par_wA_clr and rel_wayA_val(1)) or (rel_lock_set_q and rel_wayA_set); +-- Lost Lock due to Parity Error +dcpar_err_lock_lost(0) <= rel_wayA_val(1) and dcpar_err_way_inval_q(0); +-- Watch Clear/Set Logic on Port1 +reload_wayA_d(2) <= ((not rel_par_wA_clr and rel_wayA_val(2))) or (rel_watch_set_q and rel_wayA_set and rel_thrd_id_q(0)); +reload_wayA_d(3) <= ((not rel_par_wA_clr and rel_wayA_val(3))) or (rel_watch_set_q and rel_wayA_set and rel_thrd_id_q(1)); +reload_wayA_d(4) <= ((not rel_par_wA_clr and rel_wayA_val(4))) or (rel_watch_set_q and rel_wayA_set and rel_thrd_id_q(2)); +reload_wayA_d(5) <= ((not rel_par_wA_clr and rel_wayA_val(5))) or (rel_watch_set_q and rel_wayA_set and rel_thrd_id_q(3)); +-- Updating due to Reload or Data cache Parity error +reload_wayA_upd_d <= rel_par_wA_clr or rel_wayA_set; +-- Updating due to Reload Clear only +reload_wayA_clr <= rel_par_wA_clr; +-- Invalidate Way +rel_par_wB_clr <= rel_wayB_clr or dcpar_err_way_inval_q(1); +-- Invalidate/Reload Logic on Port1 +reload_wayB_d(0) <= (not rel_par_wB_clr and rel_wayB_val(0)) or rel_wayB_set; +-- Lock Clear/Set Logic on Port1 +reload_wayB_d(1) <= (not rel_par_wB_clr and rel_wayB_val(1)) or (rel_lock_set_q and rel_wayB_set); +-- Lost Lock due to Parity Error +dcpar_err_lock_lost(1) <= rel_wayB_val(1) and dcpar_err_way_inval_q(1); +-- Watch Clear/Set Logic on Port1 +reload_wayB_d(2) <= ((not rel_par_wB_clr and rel_wayB_val(2))) or (rel_watch_set_q and rel_wayB_set and rel_thrd_id_q(0)); +reload_wayB_d(3) <= ((not rel_par_wB_clr and rel_wayB_val(3))) or (rel_watch_set_q and rel_wayB_set and rel_thrd_id_q(1)); +reload_wayB_d(4) <= ((not rel_par_wB_clr and rel_wayB_val(4))) or (rel_watch_set_q and rel_wayB_set and rel_thrd_id_q(2)); +reload_wayB_d(5) <= ((not rel_par_wB_clr and rel_wayB_val(5))) or (rel_watch_set_q and rel_wayB_set and rel_thrd_id_q(3)); +-- Updating due to Reload or Data cache Parity error +reload_wayB_upd_d <= rel_par_wB_clr or rel_wayB_set; +-- Updating due to Reload Clear only +reload_wayB_clr <= rel_par_wB_clr; +-- Invalidate Way +rel_par_wC_clr <= rel_wayC_clr or dcpar_err_way_inval_q(2); +-- Invalidate/Reload Logic on Port1 +reload_wayC_d(0) <= (not rel_par_wC_clr and rel_wayC_val(0)) or rel_wayC_set; +-- Lock Clear/Set Logic on Port1 +reload_wayC_d(1) <= (not rel_par_wC_clr and rel_wayC_val(1)) or (rel_lock_set_q and rel_wayC_set); +-- Lost Lock due to Parity Error +dcpar_err_lock_lost(2) <= rel_wayC_val(1) and dcpar_err_way_inval_q(2); +-- Watch Clear/Set Logic on Port1 +reload_wayC_d(2) <= ((not rel_par_wC_clr and rel_wayC_val(2))) or (rel_watch_set_q and rel_wayC_set and rel_thrd_id_q(0)); +reload_wayC_d(3) <= ((not rel_par_wC_clr and rel_wayC_val(3))) or (rel_watch_set_q and rel_wayC_set and rel_thrd_id_q(1)); +reload_wayC_d(4) <= ((not rel_par_wC_clr and rel_wayC_val(4))) or (rel_watch_set_q and rel_wayC_set and rel_thrd_id_q(2)); +reload_wayC_d(5) <= ((not rel_par_wC_clr and rel_wayC_val(5))) or (rel_watch_set_q and rel_wayC_set and rel_thrd_id_q(3)); +-- Updating due to Reload or Data cache Parity error +reload_wayC_upd_d <= rel_par_wC_clr or rel_wayC_set; +-- Updating due to Reload Clear only +reload_wayC_clr <= rel_par_wC_clr; +-- Invalidate Way +rel_par_wD_clr <= rel_wayD_clr or dcpar_err_way_inval_q(3); +-- Invalidate/Reload Logic on Port1 +reload_wayD_d(0) <= (not rel_par_wD_clr and rel_wayD_val(0)) or rel_wayD_set; +-- Lock Clear/Set Logic on Port1 +reload_wayD_d(1) <= (not rel_par_wD_clr and rel_wayD_val(1)) or (rel_lock_set_q and rel_wayD_set); +-- Lost Lock due to Parity Error +dcpar_err_lock_lost(3) <= rel_wayD_val(1) and dcpar_err_way_inval_q(3); +-- Watch Clear/Set Logic on Port1 +reload_wayD_d(2) <= ((not rel_par_wD_clr and rel_wayD_val(2))) or (rel_watch_set_q and rel_wayD_set and rel_thrd_id_q(0)); +reload_wayD_d(3) <= ((not rel_par_wD_clr and rel_wayD_val(3))) or (rel_watch_set_q and rel_wayD_set and rel_thrd_id_q(1)); +reload_wayD_d(4) <= ((not rel_par_wD_clr and rel_wayD_val(4))) or (rel_watch_set_q and rel_wayD_set and rel_thrd_id_q(2)); +reload_wayD_d(5) <= ((not rel_par_wD_clr and rel_wayD_val(5))) or (rel_watch_set_q and rel_wayD_set and rel_thrd_id_q(3)); +-- Updating due to Reload or Data cache Parity error +reload_wayD_upd_d <= rel_par_wD_clr or rel_wayD_set; +-- Updating due to Reload Clear only +reload_wayD_clr <= rel_par_wD_clr; +-- Invalidate Way +rel_par_wE_clr <= rel_wayE_clr or dcpar_err_way_inval_q(4); +-- Invalidate/Reload Logic on Port1 +reload_wayE_d(0) <= (not rel_par_wE_clr and rel_wayE_val(0)) or rel_wayE_set; +-- Lock Clear/Set Logic on Port1 +reload_wayE_d(1) <= (not rel_par_wE_clr and rel_wayE_val(1)) or (rel_lock_set_q and rel_wayE_set); +-- Lost Lock due to Parity Error +dcpar_err_lock_lost(4) <= rel_wayE_val(1) and dcpar_err_way_inval_q(4); +-- Watch Clear/Set Logic on Port1 +reload_wayE_d(2) <= ((not rel_par_wE_clr and rel_wayE_val(2))) or (rel_watch_set_q and rel_wayE_set and rel_thrd_id_q(0)); +reload_wayE_d(3) <= ((not rel_par_wE_clr and rel_wayE_val(3))) or (rel_watch_set_q and rel_wayE_set and rel_thrd_id_q(1)); +reload_wayE_d(4) <= ((not rel_par_wE_clr and rel_wayE_val(4))) or (rel_watch_set_q and rel_wayE_set and rel_thrd_id_q(2)); +reload_wayE_d(5) <= ((not rel_par_wE_clr and rel_wayE_val(5))) or (rel_watch_set_q and rel_wayE_set and rel_thrd_id_q(3)); +-- Updating due to Reload or Data cache Parity error +reload_wayE_upd_d <= rel_par_wE_clr or rel_wayE_set; +-- Updating due to Reload Clear only +reload_wayE_clr <= rel_par_wE_clr; +-- Invalidate Way +rel_par_wF_clr <= rel_wayF_clr or dcpar_err_way_inval_q(5); +-- Invalidate/Reload Logic on Port1 +reload_wayF_d(0) <= (not rel_par_wF_clr and rel_wayF_val(0)) or rel_wayF_set; +-- Lock Clear/Set Logic on Port1 +reload_wayF_d(1) <= (not rel_par_wF_clr and rel_wayF_val(1)) or (rel_lock_set_q and rel_wayF_set); +-- Lost Lock due to Parity Error +dcpar_err_lock_lost(5) <= rel_wayF_val(1) and dcpar_err_way_inval_q(5); +-- Watch Clear/Set Logic on Port1 +reload_wayF_d(2) <= ((not rel_par_wF_clr and rel_wayF_val(2))) or (rel_watch_set_q and rel_wayF_set and rel_thrd_id_q(0)); +reload_wayF_d(3) <= ((not rel_par_wF_clr and rel_wayF_val(3))) or (rel_watch_set_q and rel_wayF_set and rel_thrd_id_q(1)); +reload_wayF_d(4) <= ((not rel_par_wF_clr and rel_wayF_val(4))) or (rel_watch_set_q and rel_wayF_set and rel_thrd_id_q(2)); +reload_wayF_d(5) <= ((not rel_par_wF_clr and rel_wayF_val(5))) or (rel_watch_set_q and rel_wayF_set and rel_thrd_id_q(3)); +-- Updating due to Reload or Data cache Parity error +reload_wayF_upd_d <= rel_par_wF_clr or rel_wayF_set; +-- Updating due to Reload Clear only +reload_wayF_clr <= rel_par_wF_clr; +-- Invalidate Way +rel_par_wG_clr <= rel_wayG_clr or dcpar_err_way_inval_q(6); +-- Invalidate/Reload Logic on Port1 +reload_wayG_d(0) <= (not rel_par_wG_clr and rel_wayG_val(0)) or rel_wayG_set; +-- Lock Clear/Set Logic on Port1 +reload_wayG_d(1) <= (not rel_par_wG_clr and rel_wayG_val(1)) or (rel_lock_set_q and rel_wayG_set); +-- Lost Lock due to Parity Error +dcpar_err_lock_lost(6) <= rel_wayG_val(1) and dcpar_err_way_inval_q(6); +-- Watch Clear/Set Logic on Port1 +reload_wayG_d(2) <= ((not rel_par_wG_clr and rel_wayG_val(2))) or (rel_watch_set_q and rel_wayG_set and rel_thrd_id_q(0)); +reload_wayG_d(3) <= ((not rel_par_wG_clr and rel_wayG_val(3))) or (rel_watch_set_q and rel_wayG_set and rel_thrd_id_q(1)); +reload_wayG_d(4) <= ((not rel_par_wG_clr and rel_wayG_val(4))) or (rel_watch_set_q and rel_wayG_set and rel_thrd_id_q(2)); +reload_wayG_d(5) <= ((not rel_par_wG_clr and rel_wayG_val(5))) or (rel_watch_set_q and rel_wayG_set and rel_thrd_id_q(3)); +-- Updating due to Reload or Data cache Parity error +reload_wayG_upd_d <= rel_par_wG_clr or rel_wayG_set; +-- Updating due to Reload Clear only +reload_wayG_clr <= rel_par_wG_clr; +-- Invalidate Way +rel_par_wH_clr <= rel_wayH_clr or dcpar_err_way_inval_q(7); +-- Invalidate/Reload Logic on Port1 +reload_wayH_d(0) <= (not rel_par_wH_clr and rel_wayH_val(0)) or rel_wayH_set; +-- Lock Clear/Set Logic on Port1 +reload_wayH_d(1) <= (not rel_par_wH_clr and rel_wayH_val(1)) or (rel_lock_set_q and rel_wayH_set); +-- Lost Lock due to Parity Error +dcpar_err_lock_lost(7) <= rel_wayH_val(1) and dcpar_err_way_inval_q(7); +-- Watch Clear/Set Logic on Port1 +reload_wayH_d(2) <= ((not rel_par_wH_clr and rel_wayH_val(2))) or (rel_watch_set_q and rel_wayH_set and rel_thrd_id_q(0)); +reload_wayH_d(3) <= ((not rel_par_wH_clr and rel_wayH_val(3))) or (rel_watch_set_q and rel_wayH_set and rel_thrd_id_q(1)); +reload_wayH_d(4) <= ((not rel_par_wH_clr and rel_wayH_val(4))) or (rel_watch_set_q and rel_wayH_set and rel_thrd_id_q(2)); +reload_wayH_d(5) <= ((not rel_par_wH_clr and rel_wayH_val(5))) or (rel_watch_set_q and rel_wayH_set and rel_thrd_id_q(3)); +-- Updating due to Reload or Data cache Parity error +reload_wayH_upd_d <= rel_par_wH_clr or rel_wayH_set; +-- Updating due to Reload Clear only +reload_wayH_clr <= rel_par_wH_clr; +reload_way_clr_d <= reload_wayA_clr & reload_wayB_clr & reload_wayC_clr & reload_wayD_clr & + reload_wayE_clr & reload_wayF_clr & reload_wayG_clr & reload_wayH_clr; +-- #################################################### +-- Determine if Watch was lost due to a reload or +-- due to a Back-Invalidate of loadmissQ entry +-- #################################################### +-- Watch Lost due to L1DUMP of reload +rel4_l1dump_watch <= rel4_l1dump_val_q and rel_watch_set_q and not rel4_ecc_err; +lost_watch_l1dump <= gate(rel_thrd_id_q, rel4_l1dump_watch); +-- Watch Lost due to Overlock +lost_watch_evict_ovl_d <= (gate(rel_thrd_id_q, (rel_watch_set_q and rel_val_stg4 and not + (rel_wayA_set or rel_wayB_set or rel_wayC_set or rel_wayD_set or + rel_wayE_set or rel_wayF_set or rel_wayG_set or rel_wayH_set)))) or + lost_watch_l1dump; +-- Watch Lost due to Eviction +rel_lost_watch_wayA_evict <= gate(rel_wayA_val_stg_q(2 to 5), reload_way_clr_q(0)); +rel_lost_watch_wayB_evict <= gate(rel_wayB_val_stg_q(2 to 5), reload_way_clr_q(1)); +rel_lost_watch_wayC_evict <= gate(rel_wayC_val_stg_q(2 to 5), reload_way_clr_q(2)); +rel_lost_watch_wayD_evict <= gate(rel_wayD_val_stg_q(2 to 5), reload_way_clr_q(3)); +rel_lost_watch_wayE_evict <= gate(rel_wayE_val_stg_q(2 to 5), reload_way_clr_q(4)); +rel_lost_watch_wayF_evict <= gate(rel_wayF_val_stg_q(2 to 5), reload_way_clr_q(5)); +rel_lost_watch_wayG_evict <= gate(rel_wayG_val_stg_q(2 to 5), reload_way_clr_q(6)); +rel_lost_watch_wayH_evict <= gate(rel_wayH_val_stg_q(2 to 5), reload_way_clr_q(7)); +-- Watch Lost due to back-invalidate +rel_lost_watch_binv_d <= rel_watch_lost; +-- None Bypass Watch Lost indicator +rel_lost_watch_evict_np <= rel_lost_watch_wayA_evict or rel_lost_watch_wayB_evict or rel_lost_watch_wayC_evict or rel_lost_watch_wayD_evict or + rel_lost_watch_wayE_evict or rel_lost_watch_wayF_evict or rel_lost_watch_wayG_evict or rel_lost_watch_wayH_evict; +-- Data Cache Parity error lost Lock Bit +dcperr_lock_lost_d <= or_reduce(dcpar_err_lock_lost); +-- Staging out congruence class compares +rel24_congr_cl_ex4_cmp_d <= congr_cl_rel13_ex3_cmp_q; +rel24_congr_cl_ex5_cmp_d <= congr_cl_rel13_ex4_cmp_q; +rel24_congr_cl_ex6_cmp_d <= congr_cl_rel13_ex5_cmp_q; +relu_congr_cl_ex5_cmp_d <= rel24_congr_cl_ex4_cmp_q; +relu_congr_cl_ex6_cmp_d <= rel24_congr_cl_ex5_cmp_q; +relu_congr_cl_ex7_cmp_d <= rel24_congr_cl_ex6_cmp_q; +-- Data of ways updated in other stages +relu_dir_data <= gate(reload_wayA_q(2 to 5), reload_way_clr_q(0)) or gate(reload_wayB_q(2 to 5), reload_way_clr_q(1)) or + gate(reload_wayC_q(2 to 5), reload_way_clr_q(2)) or gate(reload_wayD_q(2 to 5), reload_way_clr_q(3)) or + gate(reload_wayE_q(2 to 5), reload_way_clr_q(4)) or gate(reload_wayF_q(2 to 5), reload_way_clr_q(5)) or + gate(reload_wayG_q(2 to 5), reload_way_clr_q(6)) or gate(reload_wayH_q(2 to 5), reload_way_clr_q(7)); +-- LDAWX hit way in pipe collided with reload clear of same way in rel1_val stage +rel_ex5_watchSet_coll <= rel_val_clr_q and relu_congr_cl_ex5_cmp_q and or_reduce(reload_way_clr_q and binv5_ex5_way_upd) and p0_wren_d; +rel_ex6_watchSet_coll <= rel_val_clr_q and relu_congr_cl_ex6_cmp_q and or_reduce(reload_way_clr_q and binv6_ex6_way_upd) and p0_wren_q; +rel_ex7_watchSet_coll <= rel_val_clr_q and relu_congr_cl_ex7_cmp_q and or_reduce(reload_way_clr_q and binv7_ex7_way_upd_q) and p0_wren_stg_q; +rel_coll_val <= rel_ex5_watchSet_coll or rel_ex6_watchSet_coll or rel_ex7_watchSet_coll; +-- Priority Calculation +rel_pri_byp_sel(0) <= rel_ex5_watchSet_coll; +rel_pri_byp_sel(1) <= rel_ex6_watchSet_coll and not rel_ex5_watchSet_coll; +rel_pri_byp_sel(2) <= rel_ex7_watchSet_coll and not (rel_ex6_watchSet_coll or rel_ex5_watchSet_coll); +rel_byp_dir_data <= gate(binv5_ex5_dir_data_q(2 to 5), rel_pri_byp_sel(0)) or + gate(binv6_ex6_dir_data_q(2 to 5), rel_pri_byp_sel(1)) or + gate(binv7_ex7_dir_data_q(2 to 5), rel_pri_byp_sel(2)); +-- Reload invalidated a watched line +rel_watchSet_coll_tid <= (rel_byp_dir_data and not relu_dir_data) or gate(rel_lost_watch_evict_np, (rel_val_clr_q and not rel_coll_val)); +-- Watch Lost due to eviction or overlock or pipe collision with ldawx +rel_lost_watch_evict <= lost_watch_evict_ovl_q or rel_watchSet_coll_tid; +-- Watch Lost due to back-invalidate or overlock or eviction or pipe collision with ldawx +rel_lost_watch_upd_d <= rel_lost_watch_binv_q or rel_lost_watch_evict; +-- #################################################### +-- Performance Events +-- #################################################### +-- Performance Event, Back-Invalidate Hit +perf_binv_hit <= back_inval_stg4_q and or_reduce(ex4_way_hit_q); +-- Performance Event, Watch Checks Completed +ex5_watch_chk_cplt <= ex5_watch_chk_q and not ex5_stg_flush; +-- Performance Event, Watch Checked Successfull +ex5_watch_chk_succ <= ex5_watch_chk_q and not (ex5_cr_watch_q or ex5_stg_flush); +-- Performance Event, LDAWX. instruction executed and CR=1 (indicates a duplicate watch set) +ex5_watch_dup_set <= ex5_watch_set_q and ex5_cr_watch_q and not ex5_stg_flush; +-- Performance Event, Watches lost due to other thread +lost_watch_inter_thrd_d <= gate((ex5_watchlost_set_q and not (ex5_thrd_id_q or ex5_watch_clr_all_q)), ex5_xuop_val); +-- Performance Event, Watches lost due to Eviction or Overlock +lost_watch_evict_val_d <= lost_watch_evict_ovl_q or rel_watchSet_coll_tid; +-- Performance Event, Watch Lost due to back-invalidate +lost_watch_binv <= binv5_inval_watch_val_q or rel_lost_watch_binv_q; +-- Performance Event, Latching up Events +perf_lsu_evnts_d <= back_inval_stg4_q & perf_binv_hit & ex5_watch_chk_cplt & ex5_watch_chk_succ & ex5_watch_dup_set; +-- #################################################### +-- Parity Error Recovery Logic +-- #################################################### +-- Parity Error detected in EX6, need to invalidate any +-- Load Hits in EX6, EX5, and EX4 since these requests +-- Will be satisfied by the L2. Parity Error Recovery +-- Sequencer waits for the first parity error to reach EX9 +-- in the Parity Error Recovery Queue before it starts +-- The sequencer will look for a hole in the reload pipe +-- and use it to invalidate the way with the parity error +-- of the load hit including valids,lock,and watch bits. +-- The Queue consists of a Parity Error Indicator, +-- Load Valid Indicator, Congruence Class, and Way Hit +dcpar_err_push <= not ex9_ld_par_err_q; +dcpar_err_rec_cmpl <= (dcpar_err_cntr_q = "10") and dcpar_err_nxt_rec; +dcpar_err_nxt_rec <= ex9_ld_par_err_q and not rel_in_progress; +dcpar_err_push_queue <= dcpar_err_push or dcpar_err_nxt_rec; +dcpar_err_ind_sel <= dcpar_err_push & dcpar_err_rec_cmpl; +dcpar_err_ind_sel_d <= dcpar_err_ind_sel; +dcpar_err_push_queue_d <= dcpar_err_push_queue; +-- Parity Error Recovery Queue +-- #################################################### +-- Parity Error Indicator +with dcpar_err_ind_sel select + ex7_ld_par_err_d <= ex6_ld_par_err when "10", + ex7_ld_par_err_q when "00", + '0' when others; +with dcpar_err_ind_sel select + ex8_ld_par_err_d <= ex7_ld_par_err_q when "10", + ex8_ld_par_err_q when "00", + '0' when others; +with dcpar_err_ind_sel select + ex9_ld_par_err_d <= ex8_ld_par_err_q when "10", + ex9_ld_par_err_q when "00", + '0' when others; +-- Load Hit Valid Indicator +with dcpar_err_push_queue select + ex7_ld_valid_d <= ex6_ld_valid_q when '1', + ex7_ld_valid_q when others; +with dcpar_err_push_queue select + ex8_ld_valid_d <= ex7_ld_valid_q when '1', + ex8_ld_valid_q when others; +with dcpar_err_push_queue select + ex9_ld_valid_d <= ex8_ld_valid_q when '1', + ex9_ld_valid_q when others; +-- Congruence Class +with dcpar_err_push_queue select + ex7_congr_cl_d <= ex6_congr_cl_q when '1', + ex7_congr_cl_q when others; +with dcpar_err_push_queue select + ex8_congr_cl_d <= ex7_congr_cl_q when '1', + ex8_congr_cl_q when others; +with dcpar_err_push_queue select + ex9_congr_cl_d <= ex8_congr_cl_q when '1', + ex9_congr_cl_q when others; +-- Way Hit +with dcpar_err_push_queue select + ex7_way_hit_d <= ex6_way_hit_q when '1', + ex7_way_hit_q when others; +with dcpar_err_push_queue select + ex8_way_hit_d <= ex7_way_hit_q when '1', + ex8_way_hit_q when others; +with dcpar_err_push_queue select + ex9_way_hit_d <= ex8_way_hit_q when '1', + ex9_way_hit_q when others; +-- Parity Error Recovery Counter +dcpar_err_incr_val <= dcpar_err_nxt_rec and not (dcpar_err_cntr_q = "10"); +dcpar_err_cntr_sel <= dcpar_err_push & dcpar_err_incr_val; +dcpar_err_nxt_cntr <= std_ulogic_vector(unsigned(dcpar_err_cntr_q) + "01"); +with dcpar_err_cntr_sel select + dcpar_err_cntr_d <= dcpar_err_nxt_cntr when "01", + dcpar_err_cntr_q when "00", + "00" when others; +-- Generate a Pulse for Parity Error Completion +dcpar_err_stg1_d <= dcpar_err_nxt_rec; +dcpar_err_stg2_d <= dcpar_err_stg1_q; +dcpar_err_congr_cl <= ex9_congr_cl_q; +dcpar_err_way_d <= gate(ex9_way_hit_q, (ex9_ld_valid_q and dcpar_err_nxt_rec)); +dcpar_err_way_inval_d <= dcpar_err_way_q; +dcpar_err_flush <= ex9_ld_par_err_q; +dcpar_err_stg1_act_d <= ex9_ld_par_err_q; +dcpar_err_stg2_act_d <= dcpar_err_stg1_act_q; +dcpar_err_rec_inprog <= ex7_ld_par_err_q or ex8_ld_par_err_q or ex9_ld_par_err_q; +-- #################################################### +-- Directory Valid Bits Write Enable Generation +-- #################################################### +-- Valids are updated for the following operations +-- 1) Reload -> updated the following cycle of the first beat, +-- need to invalidate the way that will be overwritten +-- 2) Reload -> updated on the last data beat when no ECC error was detected, +-- the Way will be validated that was replaced +-- 3) Back-Invalidate -> updated the following cycle +-- 4) DCBF -> Updated in EX4 +-- 5) DCBI -> Updated in EX4 +-- 6) DCBZ -> Updated in EX4 +-- 7) LWARX Hit Invalidate -> Updated in EX4 +-- 8) STWCX Hit Invalidate -> Updated in EX4 +-- Lock Bits are updated for the following operations +-- 1) Reload -> updated the following cycle of the first beat, +-- need to clear the lock bit for the way that will be overwritten +-- 2) Reload -> updated on the last data beat when no ECC error was detected, +-- the Lock bit will be set that was replaced if originally a lock type op +-- 3) Back-Invalidate -> will clear lock bit the following cycle +-- 4) DCBF -> will clear lock bit in EX4 +-- 5) DCBI -> will clear lock bit in EX4 +-- 6) DCBZ -> will clear lock bit in EX4 +-- 7) LWARX Hit Invalidate -> will clear lock bit in EX4 +-- 8) STWCX Hit Invalidate -> will clear lock bit in EX4 +-- 9) DCBLC -> will clear lock bit in EX4 +--10) DCBTLS/DCBTSTLS -> will set lock bit in EX4 if hit +-- Port0 Updates +-- 1) XU Invalidate Op +-- 2) BACK-INV Update +-- 3) XU clear Lock Op +-- 4) XU set Lock Op +p0_wren_d <= back_inval_stg5_q or ex5_xuop_val or ex5_dir_err_val_q; +p0_wren_cpy_d <= back_inval_stg5_q or ex5_xuop_val or ex5_dir_err_val_q; +p0_wren_stg_d <= p0_wren_q; +-- Port1 Updates +-- 1) RELOAD_CLR +-- 2) RELOAD_SEt +-- 3) DC Array Parity Error with Loadhit followed by storehit update - need to invalidate storehit cline +p1_wren_d <= rel_port_wren_q; +p1_wren_cpy_d <= rel_port_wren_q; +p1_upd_val <= rel_port_upd_q; +-- Need to set reload way valid bit when clearing the valid bit of older load +-- in case second reload of interleaved reloads to same congruence class +-- Dont want second reload to overwrite first reload that cleared the valid bit +-- Second reload will choose the same way if not set by first +reload_wayA(0) <= (reload_wayA_upd_q); +reload_wayA(1) <= reload_wayA_q(1); +reload_wayA(2 TO 5) <= reload_wayA_q(2 to 5); +-- Staging out Reload Pipe Updates +reload_wayA_upd2_d <= reload_wayA_upd_q; +reload_wayA_data_d <= reload_wayA_q; +reload_wayA_upd3_d <= reload_wayA_upd2_q; +reload_wayA_data2_d <= reload_wayA_data_q; +-- Staging out Back-Invalidate Pipe Updates +binv_wayA_upd1 <= (binv_wayA_upd_q and ((not ex4_dir_err_val_q) or back_inval_stg4_q)) or ex4_err_det_way_q(0) or ex4_dir_multihit_val; +binv_wayA_upd2_d <= binv_wayA_upd1; +flush_wayA_data1 <= gate(flush_wayA_q, not (ex4_err_det_way_q(0) or ex4_dir_multihit_val)); +flush_wayA_data_d <= flush_wayA_data1; +binv_wayA_upd3_d <= binv_wayA_upd2_q; +flush_wayA_data2_d <= flush_wayA_data_q; +reload_wayB(0) <= (reload_wayB_upd_q); +reload_wayB(1) <= reload_wayB_q(1); +reload_wayB(2 TO 5) <= reload_wayB_q(2 to 5); +-- Staging out Reload Pipe Updates +reload_wayB_upd2_d <= reload_wayB_upd_q; +reload_wayB_data_d <= reload_wayB_q; +reload_wayB_upd3_d <= reload_wayB_upd2_q; +reload_wayB_data2_d <= reload_wayB_data_q; +-- Staging out Back-Invalidate Pipe Updates +binv_wayB_upd1 <= (binv_wayB_upd_q and ((not ex4_dir_err_val_q) or back_inval_stg4_q)) or ex4_err_det_way_q(1) or ex4_dir_multihit_val; +binv_wayB_upd2_d <= binv_wayB_upd1; +flush_wayB_data1 <= gate(flush_wayB_q, not (ex4_err_det_way_q(1) or ex4_dir_multihit_val)); +flush_wayB_data_d <= flush_wayB_data1; +binv_wayB_upd3_d <= binv_wayB_upd2_q; +flush_wayB_data2_d <= flush_wayB_data_q; +reload_wayC(0) <= (reload_wayC_upd_q); +reload_wayC(1) <= reload_wayC_q(1); +reload_wayC(2 TO 5) <= reload_wayC_q(2 to 5); +-- Staging out Reload Pipe Updates +reload_wayC_upd2_d <= reload_wayC_upd_q; +reload_wayC_data_d <= reload_wayC_q; +reload_wayC_upd3_d <= reload_wayC_upd2_q; +reload_wayC_data2_d <= reload_wayC_data_q; +-- Staging out Back-Invalidate Pipe Updates +binv_wayC_upd1 <= (binv_wayC_upd_q and ((not ex4_dir_err_val_q) or back_inval_stg4_q)) or ex4_err_det_way_q(2) or ex4_dir_multihit_val; +binv_wayC_upd2_d <= binv_wayC_upd1; +flush_wayC_data1 <= gate(flush_wayC_q, not (ex4_err_det_way_q(2) or ex4_dir_multihit_val)); +flush_wayC_data_d <= flush_wayC_data1; +binv_wayC_upd3_d <= binv_wayC_upd2_q; +flush_wayC_data2_d <= flush_wayC_data_q; +reload_wayD(0) <= (reload_wayD_upd_q); +reload_wayD(1) <= reload_wayD_q(1); +reload_wayD(2 TO 5) <= reload_wayD_q(2 to 5); +-- Staging out Reload Pipe Updates +reload_wayD_upd2_d <= reload_wayD_upd_q; +reload_wayD_data_d <= reload_wayD_q; +reload_wayD_upd3_d <= reload_wayD_upd2_q; +reload_wayD_data2_d <= reload_wayD_data_q; +-- Staging out Back-Invalidate Pipe Updates +binv_wayD_upd1 <= (binv_wayD_upd_q and ((not ex4_dir_err_val_q) or back_inval_stg4_q)) or ex4_err_det_way_q(3) or ex4_dir_multihit_val; +binv_wayD_upd2_d <= binv_wayD_upd1; +flush_wayD_data1 <= gate(flush_wayD_q, not (ex4_err_det_way_q(3) or ex4_dir_multihit_val)); +flush_wayD_data_d <= flush_wayD_data1; +binv_wayD_upd3_d <= binv_wayD_upd2_q; +flush_wayD_data2_d <= flush_wayD_data_q; +reload_wayE(0) <= (reload_wayE_upd_q); +reload_wayE(1) <= reload_wayE_q(1); +reload_wayE(2 TO 5) <= reload_wayE_q(2 to 5); +-- Staging out Reload Pipe Updates +reload_wayE_upd2_d <= reload_wayE_upd_q; +reload_wayE_data_d <= reload_wayE_q; +reload_wayE_upd3_d <= reload_wayE_upd2_q; +reload_wayE_data2_d <= reload_wayE_data_q; +-- Staging out Back-Invalidate Pipe Updates +binv_wayE_upd1 <= (binv_wayE_upd_q and ((not ex4_dir_err_val_q) or back_inval_stg4_q)) or ex4_err_det_way_q(4) or ex4_dir_multihit_val; +binv_wayE_upd2_d <= binv_wayE_upd1; +flush_wayE_data1 <= gate(flush_wayE_q, not (ex4_err_det_way_q(4) or ex4_dir_multihit_val)); +flush_wayE_data_d <= flush_wayE_data1; +binv_wayE_upd3_d <= binv_wayE_upd2_q; +flush_wayE_data2_d <= flush_wayE_data_q; +reload_wayF(0) <= (reload_wayF_upd_q); +reload_wayF(1) <= reload_wayF_q(1); +reload_wayF(2 TO 5) <= reload_wayF_q(2 to 5); +-- Staging out Reload Pipe Updates +reload_wayF_upd2_d <= reload_wayF_upd_q; +reload_wayF_data_d <= reload_wayF_q; +reload_wayF_upd3_d <= reload_wayF_upd2_q; +reload_wayF_data2_d <= reload_wayF_data_q; +-- Staging out Back-Invalidate Pipe Updates +binv_wayF_upd1 <= (binv_wayF_upd_q and ((not ex4_dir_err_val_q) or back_inval_stg4_q)) or ex4_err_det_way_q(5) or ex4_dir_multihit_val; +binv_wayF_upd2_d <= binv_wayF_upd1; +flush_wayF_data1 <= gate(flush_wayF_q, not (ex4_err_det_way_q(5) or ex4_dir_multihit_val)); +flush_wayF_data_d <= flush_wayF_data1; +binv_wayF_upd3_d <= binv_wayF_upd2_q; +flush_wayF_data2_d <= flush_wayF_data_q; +reload_wayG(0) <= (reload_wayG_upd_q); +reload_wayG(1) <= reload_wayG_q(1); +reload_wayG(2 TO 5) <= reload_wayG_q(2 to 5); +-- Staging out Reload Pipe Updates +reload_wayG_upd2_d <= reload_wayG_upd_q; +reload_wayG_data_d <= reload_wayG_q; +reload_wayG_upd3_d <= reload_wayG_upd2_q; +reload_wayG_data2_d <= reload_wayG_data_q; +-- Staging out Back-Invalidate Pipe Updates +binv_wayG_upd1 <= (binv_wayG_upd_q and ((not ex4_dir_err_val_q) or back_inval_stg4_q)) or ex4_err_det_way_q(6) or ex4_dir_multihit_val; +binv_wayG_upd2_d <= binv_wayG_upd1; +flush_wayG_data1 <= gate(flush_wayG_q, not (ex4_err_det_way_q(6) or ex4_dir_multihit_val)); +flush_wayG_data_d <= flush_wayG_data1; +binv_wayG_upd3_d <= binv_wayG_upd2_q; +flush_wayG_data2_d <= flush_wayG_data_q; +reload_wayH(0) <= (reload_wayH_upd_q); +reload_wayH(1) <= reload_wayH_q(1); +reload_wayH(2 TO 5) <= reload_wayH_q(2 to 5); +-- Staging out Reload Pipe Updates +reload_wayH_upd2_d <= reload_wayH_upd_q; +reload_wayH_data_d <= reload_wayH_q; +reload_wayH_upd3_d <= reload_wayH_upd2_q; +reload_wayH_data2_d <= reload_wayH_data_q; +-- Staging out Back-Invalidate Pipe Updates +binv_wayH_upd1 <= (binv_wayH_upd_q and ((not ex4_dir_err_val_q) or back_inval_stg4_q)) or ex4_err_det_way_q(7) or ex4_dir_multihit_val; +binv_wayH_upd2_d <= binv_wayH_upd1; +flush_wayH_data1 <= gate(flush_wayH_q, not (ex4_err_det_way_q(7) or ex4_dir_multihit_val)); +flush_wayH_data_d <= flush_wayH_data1; +binv_wayH_upd3_d <= binv_wayH_upd2_q; +flush_wayH_data2_d <= flush_wayH_data_q; +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Table for selecting Ports data for +-- updating to the same way and +-- same congruence class +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- P0 P1 | PortSel +-------------------------------------------- +-- binv2 relclr | P1 +-- binv2 relset | P1 +-- binv2 binv2 | P1 <- Impossible +-- flush relclr | P1 +-- flush relset | P1 +-- flush binv2 | P1 <- FlushOp is flushed +-- lckset relclr | P1 +-- lckset relset | P1 +-- lckset binv2 | P1 <- LockSetOp is flushed +-- lckclr relclr | P1 +-- lckclr relset | P1 +-- lckclr binv2 | P1 <- LockClrOp is flushed +-- Act Pin to all Directory Latches +congr_cl_all_act_d <= ex5_watch_clr_all_val_q or dci_compl_q or lock_flash_clear_q; +-- Congruence Class Match +p0_congr_cl0_m <= (ex5_congr_cl_q = tconv(0,5)); +p1_congr_cl0_m <= (relu_s_congr_cl_q = tconv(0,5)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl0_act_d <= p0_congr_cl0_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl0_act_d <= p1_congr_cl0_m and rel_port_wren_q; +congr_cl0_act <= p0_congr_cl0_act_q or p1_congr_cl0_act_q or congr_cl_all_act_q; +p0_way_data_upd0_wayA <= p0_congr_cl0_act_q and binv_wayA_upd3_q; +p1_way_data_upd0_wayA <= p1_congr_cl0_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu0_wayA_upd(0) <= p1_way_data_upd0_wayA and p1_wren_q; +rel_bixu0_wayA_upd(1) <= p0_way_data_upd0_wayA and p0_wren_q; +p0_way_data_upd0_wayB <= p0_congr_cl0_act_q and binv_wayB_upd3_q; +p1_way_data_upd0_wayB <= p1_congr_cl0_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu0_wayB_upd(0) <= p1_way_data_upd0_wayB and p1_wren_q; +rel_bixu0_wayB_upd(1) <= p0_way_data_upd0_wayB and p0_wren_q; +p0_way_data_upd0_wayC <= p0_congr_cl0_act_q and binv_wayC_upd3_q; +p1_way_data_upd0_wayC <= p1_congr_cl0_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu0_wayC_upd(0) <= p1_way_data_upd0_wayC and p1_wren_q; +rel_bixu0_wayC_upd(1) <= p0_way_data_upd0_wayC and p0_wren_q; +p0_way_data_upd0_wayD <= p0_congr_cl0_act_q and binv_wayD_upd3_q; +p1_way_data_upd0_wayD <= p1_congr_cl0_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu0_wayD_upd(0) <= p1_way_data_upd0_wayD and p1_wren_q; +rel_bixu0_wayD_upd(1) <= p0_way_data_upd0_wayD and p0_wren_q; +p0_way_data_upd0_wayE <= p0_congr_cl0_act_q and binv_wayE_upd3_q; +p1_way_data_upd0_wayE <= p1_congr_cl0_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu0_wayE_upd(0) <= p1_way_data_upd0_wayE and p1_wren_q; +rel_bixu0_wayE_upd(1) <= p0_way_data_upd0_wayE and p0_wren_q; +p0_way_data_upd0_wayF <= p0_congr_cl0_act_q and binv_wayF_upd3_q; +p1_way_data_upd0_wayF <= p1_congr_cl0_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu0_wayF_upd(0) <= p1_way_data_upd0_wayF and p1_wren_q; +rel_bixu0_wayF_upd(1) <= p0_way_data_upd0_wayF and p0_wren_q; +p0_way_data_upd0_wayG <= p0_congr_cl0_act_q and binv_wayG_upd3_q; +p1_way_data_upd0_wayG <= p1_congr_cl0_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu0_wayG_upd(0) <= p1_way_data_upd0_wayG and p1_wren_q; +rel_bixu0_wayG_upd(1) <= p0_way_data_upd0_wayG and p0_wren_q; +p0_way_data_upd0_wayH <= p0_congr_cl0_act_q and binv_wayH_upd3_q; +p1_way_data_upd0_wayH <= p1_congr_cl0_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu0_wayH_upd(0) <= p1_way_data_upd0_wayH and p1_wren_q; +rel_bixu0_wayH_upd(1) <= p0_way_data_upd0_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl1_m <= (ex5_congr_cl_q = tconv(1,5)); +p1_congr_cl1_m <= (relu_s_congr_cl_q = tconv(1,5)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl1_act_d <= p0_congr_cl1_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl1_act_d <= p1_congr_cl1_m and rel_port_wren_q; +congr_cl1_act <= p0_congr_cl1_act_q or p1_congr_cl1_act_q or congr_cl_all_act_q; +p0_way_data_upd1_wayA <= p0_congr_cl1_act_q and binv_wayA_upd3_q; +p1_way_data_upd1_wayA <= p1_congr_cl1_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu1_wayA_upd(0) <= p1_way_data_upd1_wayA and p1_wren_q; +rel_bixu1_wayA_upd(1) <= p0_way_data_upd1_wayA and p0_wren_q; +p0_way_data_upd1_wayB <= p0_congr_cl1_act_q and binv_wayB_upd3_q; +p1_way_data_upd1_wayB <= p1_congr_cl1_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu1_wayB_upd(0) <= p1_way_data_upd1_wayB and p1_wren_q; +rel_bixu1_wayB_upd(1) <= p0_way_data_upd1_wayB and p0_wren_q; +p0_way_data_upd1_wayC <= p0_congr_cl1_act_q and binv_wayC_upd3_q; +p1_way_data_upd1_wayC <= p1_congr_cl1_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu1_wayC_upd(0) <= p1_way_data_upd1_wayC and p1_wren_q; +rel_bixu1_wayC_upd(1) <= p0_way_data_upd1_wayC and p0_wren_q; +p0_way_data_upd1_wayD <= p0_congr_cl1_act_q and binv_wayD_upd3_q; +p1_way_data_upd1_wayD <= p1_congr_cl1_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu1_wayD_upd(0) <= p1_way_data_upd1_wayD and p1_wren_q; +rel_bixu1_wayD_upd(1) <= p0_way_data_upd1_wayD and p0_wren_q; +p0_way_data_upd1_wayE <= p0_congr_cl1_act_q and binv_wayE_upd3_q; +p1_way_data_upd1_wayE <= p1_congr_cl1_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu1_wayE_upd(0) <= p1_way_data_upd1_wayE and p1_wren_q; +rel_bixu1_wayE_upd(1) <= p0_way_data_upd1_wayE and p0_wren_q; +p0_way_data_upd1_wayF <= p0_congr_cl1_act_q and binv_wayF_upd3_q; +p1_way_data_upd1_wayF <= p1_congr_cl1_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu1_wayF_upd(0) <= p1_way_data_upd1_wayF and p1_wren_q; +rel_bixu1_wayF_upd(1) <= p0_way_data_upd1_wayF and p0_wren_q; +p0_way_data_upd1_wayG <= p0_congr_cl1_act_q and binv_wayG_upd3_q; +p1_way_data_upd1_wayG <= p1_congr_cl1_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu1_wayG_upd(0) <= p1_way_data_upd1_wayG and p1_wren_q; +rel_bixu1_wayG_upd(1) <= p0_way_data_upd1_wayG and p0_wren_q; +p0_way_data_upd1_wayH <= p0_congr_cl1_act_q and binv_wayH_upd3_q; +p1_way_data_upd1_wayH <= p1_congr_cl1_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu1_wayH_upd(0) <= p1_way_data_upd1_wayH and p1_wren_q; +rel_bixu1_wayH_upd(1) <= p0_way_data_upd1_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl2_m <= (ex5_congr_cl_q = tconv(2,5)); +p1_congr_cl2_m <= (relu_s_congr_cl_q = tconv(2,5)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl2_act_d <= p0_congr_cl2_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl2_act_d <= p1_congr_cl2_m and rel_port_wren_q; +congr_cl2_act <= p0_congr_cl2_act_q or p1_congr_cl2_act_q or congr_cl_all_act_q; +p0_way_data_upd2_wayA <= p0_congr_cl2_act_q and binv_wayA_upd3_q; +p1_way_data_upd2_wayA <= p1_congr_cl2_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu2_wayA_upd(0) <= p1_way_data_upd2_wayA and p1_wren_q; +rel_bixu2_wayA_upd(1) <= p0_way_data_upd2_wayA and p0_wren_q; +p0_way_data_upd2_wayB <= p0_congr_cl2_act_q and binv_wayB_upd3_q; +p1_way_data_upd2_wayB <= p1_congr_cl2_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu2_wayB_upd(0) <= p1_way_data_upd2_wayB and p1_wren_q; +rel_bixu2_wayB_upd(1) <= p0_way_data_upd2_wayB and p0_wren_q; +p0_way_data_upd2_wayC <= p0_congr_cl2_act_q and binv_wayC_upd3_q; +p1_way_data_upd2_wayC <= p1_congr_cl2_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu2_wayC_upd(0) <= p1_way_data_upd2_wayC and p1_wren_q; +rel_bixu2_wayC_upd(1) <= p0_way_data_upd2_wayC and p0_wren_q; +p0_way_data_upd2_wayD <= p0_congr_cl2_act_q and binv_wayD_upd3_q; +p1_way_data_upd2_wayD <= p1_congr_cl2_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu2_wayD_upd(0) <= p1_way_data_upd2_wayD and p1_wren_q; +rel_bixu2_wayD_upd(1) <= p0_way_data_upd2_wayD and p0_wren_q; +p0_way_data_upd2_wayE <= p0_congr_cl2_act_q and binv_wayE_upd3_q; +p1_way_data_upd2_wayE <= p1_congr_cl2_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu2_wayE_upd(0) <= p1_way_data_upd2_wayE and p1_wren_q; +rel_bixu2_wayE_upd(1) <= p0_way_data_upd2_wayE and p0_wren_q; +p0_way_data_upd2_wayF <= p0_congr_cl2_act_q and binv_wayF_upd3_q; +p1_way_data_upd2_wayF <= p1_congr_cl2_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu2_wayF_upd(0) <= p1_way_data_upd2_wayF and p1_wren_q; +rel_bixu2_wayF_upd(1) <= p0_way_data_upd2_wayF and p0_wren_q; +p0_way_data_upd2_wayG <= p0_congr_cl2_act_q and binv_wayG_upd3_q; +p1_way_data_upd2_wayG <= p1_congr_cl2_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu2_wayG_upd(0) <= p1_way_data_upd2_wayG and p1_wren_q; +rel_bixu2_wayG_upd(1) <= p0_way_data_upd2_wayG and p0_wren_q; +p0_way_data_upd2_wayH <= p0_congr_cl2_act_q and binv_wayH_upd3_q; +p1_way_data_upd2_wayH <= p1_congr_cl2_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu2_wayH_upd(0) <= p1_way_data_upd2_wayH and p1_wren_q; +rel_bixu2_wayH_upd(1) <= p0_way_data_upd2_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl3_m <= (ex5_congr_cl_q = tconv(3,5)); +p1_congr_cl3_m <= (relu_s_congr_cl_q = tconv(3,5)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl3_act_d <= p0_congr_cl3_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl3_act_d <= p1_congr_cl3_m and rel_port_wren_q; +congr_cl3_act <= p0_congr_cl3_act_q or p1_congr_cl3_act_q or congr_cl_all_act_q; +p0_way_data_upd3_wayA <= p0_congr_cl3_act_q and binv_wayA_upd3_q; +p1_way_data_upd3_wayA <= p1_congr_cl3_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu3_wayA_upd(0) <= p1_way_data_upd3_wayA and p1_wren_q; +rel_bixu3_wayA_upd(1) <= p0_way_data_upd3_wayA and p0_wren_q; +p0_way_data_upd3_wayB <= p0_congr_cl3_act_q and binv_wayB_upd3_q; +p1_way_data_upd3_wayB <= p1_congr_cl3_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu3_wayB_upd(0) <= p1_way_data_upd3_wayB and p1_wren_q; +rel_bixu3_wayB_upd(1) <= p0_way_data_upd3_wayB and p0_wren_q; +p0_way_data_upd3_wayC <= p0_congr_cl3_act_q and binv_wayC_upd3_q; +p1_way_data_upd3_wayC <= p1_congr_cl3_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu3_wayC_upd(0) <= p1_way_data_upd3_wayC and p1_wren_q; +rel_bixu3_wayC_upd(1) <= p0_way_data_upd3_wayC and p0_wren_q; +p0_way_data_upd3_wayD <= p0_congr_cl3_act_q and binv_wayD_upd3_q; +p1_way_data_upd3_wayD <= p1_congr_cl3_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu3_wayD_upd(0) <= p1_way_data_upd3_wayD and p1_wren_q; +rel_bixu3_wayD_upd(1) <= p0_way_data_upd3_wayD and p0_wren_q; +p0_way_data_upd3_wayE <= p0_congr_cl3_act_q and binv_wayE_upd3_q; +p1_way_data_upd3_wayE <= p1_congr_cl3_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu3_wayE_upd(0) <= p1_way_data_upd3_wayE and p1_wren_q; +rel_bixu3_wayE_upd(1) <= p0_way_data_upd3_wayE and p0_wren_q; +p0_way_data_upd3_wayF <= p0_congr_cl3_act_q and binv_wayF_upd3_q; +p1_way_data_upd3_wayF <= p1_congr_cl3_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu3_wayF_upd(0) <= p1_way_data_upd3_wayF and p1_wren_q; +rel_bixu3_wayF_upd(1) <= p0_way_data_upd3_wayF and p0_wren_q; +p0_way_data_upd3_wayG <= p0_congr_cl3_act_q and binv_wayG_upd3_q; +p1_way_data_upd3_wayG <= p1_congr_cl3_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu3_wayG_upd(0) <= p1_way_data_upd3_wayG and p1_wren_q; +rel_bixu3_wayG_upd(1) <= p0_way_data_upd3_wayG and p0_wren_q; +p0_way_data_upd3_wayH <= p0_congr_cl3_act_q and binv_wayH_upd3_q; +p1_way_data_upd3_wayH <= p1_congr_cl3_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu3_wayH_upd(0) <= p1_way_data_upd3_wayH and p1_wren_q; +rel_bixu3_wayH_upd(1) <= p0_way_data_upd3_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl4_m <= (ex5_congr_cl_q = tconv(4,5)); +p1_congr_cl4_m <= (relu_s_congr_cl_q = tconv(4,5)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl4_act_d <= p0_congr_cl4_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl4_act_d <= p1_congr_cl4_m and rel_port_wren_q; +congr_cl4_act <= p0_congr_cl4_act_q or p1_congr_cl4_act_q or congr_cl_all_act_q; +p0_way_data_upd4_wayA <= p0_congr_cl4_act_q and binv_wayA_upd3_q; +p1_way_data_upd4_wayA <= p1_congr_cl4_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu4_wayA_upd(0) <= p1_way_data_upd4_wayA and p1_wren_q; +rel_bixu4_wayA_upd(1) <= p0_way_data_upd4_wayA and p0_wren_q; +p0_way_data_upd4_wayB <= p0_congr_cl4_act_q and binv_wayB_upd3_q; +p1_way_data_upd4_wayB <= p1_congr_cl4_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu4_wayB_upd(0) <= p1_way_data_upd4_wayB and p1_wren_q; +rel_bixu4_wayB_upd(1) <= p0_way_data_upd4_wayB and p0_wren_q; +p0_way_data_upd4_wayC <= p0_congr_cl4_act_q and binv_wayC_upd3_q; +p1_way_data_upd4_wayC <= p1_congr_cl4_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu4_wayC_upd(0) <= p1_way_data_upd4_wayC and p1_wren_q; +rel_bixu4_wayC_upd(1) <= p0_way_data_upd4_wayC and p0_wren_q; +p0_way_data_upd4_wayD <= p0_congr_cl4_act_q and binv_wayD_upd3_q; +p1_way_data_upd4_wayD <= p1_congr_cl4_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu4_wayD_upd(0) <= p1_way_data_upd4_wayD and p1_wren_q; +rel_bixu4_wayD_upd(1) <= p0_way_data_upd4_wayD and p0_wren_q; +p0_way_data_upd4_wayE <= p0_congr_cl4_act_q and binv_wayE_upd3_q; +p1_way_data_upd4_wayE <= p1_congr_cl4_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu4_wayE_upd(0) <= p1_way_data_upd4_wayE and p1_wren_q; +rel_bixu4_wayE_upd(1) <= p0_way_data_upd4_wayE and p0_wren_q; +p0_way_data_upd4_wayF <= p0_congr_cl4_act_q and binv_wayF_upd3_q; +p1_way_data_upd4_wayF <= p1_congr_cl4_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu4_wayF_upd(0) <= p1_way_data_upd4_wayF and p1_wren_q; +rel_bixu4_wayF_upd(1) <= p0_way_data_upd4_wayF and p0_wren_q; +p0_way_data_upd4_wayG <= p0_congr_cl4_act_q and binv_wayG_upd3_q; +p1_way_data_upd4_wayG <= p1_congr_cl4_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu4_wayG_upd(0) <= p1_way_data_upd4_wayG and p1_wren_q; +rel_bixu4_wayG_upd(1) <= p0_way_data_upd4_wayG and p0_wren_q; +p0_way_data_upd4_wayH <= p0_congr_cl4_act_q and binv_wayH_upd3_q; +p1_way_data_upd4_wayH <= p1_congr_cl4_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu4_wayH_upd(0) <= p1_way_data_upd4_wayH and p1_wren_q; +rel_bixu4_wayH_upd(1) <= p0_way_data_upd4_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl5_m <= (ex5_congr_cl_q = tconv(5,5)); +p1_congr_cl5_m <= (relu_s_congr_cl_q = tconv(5,5)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl5_act_d <= p0_congr_cl5_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl5_act_d <= p1_congr_cl5_m and rel_port_wren_q; +congr_cl5_act <= p0_congr_cl5_act_q or p1_congr_cl5_act_q or congr_cl_all_act_q; +p0_way_data_upd5_wayA <= p0_congr_cl5_act_q and binv_wayA_upd3_q; +p1_way_data_upd5_wayA <= p1_congr_cl5_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu5_wayA_upd(0) <= p1_way_data_upd5_wayA and p1_wren_q; +rel_bixu5_wayA_upd(1) <= p0_way_data_upd5_wayA and p0_wren_q; +p0_way_data_upd5_wayB <= p0_congr_cl5_act_q and binv_wayB_upd3_q; +p1_way_data_upd5_wayB <= p1_congr_cl5_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu5_wayB_upd(0) <= p1_way_data_upd5_wayB and p1_wren_q; +rel_bixu5_wayB_upd(1) <= p0_way_data_upd5_wayB and p0_wren_q; +p0_way_data_upd5_wayC <= p0_congr_cl5_act_q and binv_wayC_upd3_q; +p1_way_data_upd5_wayC <= p1_congr_cl5_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu5_wayC_upd(0) <= p1_way_data_upd5_wayC and p1_wren_q; +rel_bixu5_wayC_upd(1) <= p0_way_data_upd5_wayC and p0_wren_q; +p0_way_data_upd5_wayD <= p0_congr_cl5_act_q and binv_wayD_upd3_q; +p1_way_data_upd5_wayD <= p1_congr_cl5_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu5_wayD_upd(0) <= p1_way_data_upd5_wayD and p1_wren_q; +rel_bixu5_wayD_upd(1) <= p0_way_data_upd5_wayD and p0_wren_q; +p0_way_data_upd5_wayE <= p0_congr_cl5_act_q and binv_wayE_upd3_q; +p1_way_data_upd5_wayE <= p1_congr_cl5_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu5_wayE_upd(0) <= p1_way_data_upd5_wayE and p1_wren_q; +rel_bixu5_wayE_upd(1) <= p0_way_data_upd5_wayE and p0_wren_q; +p0_way_data_upd5_wayF <= p0_congr_cl5_act_q and binv_wayF_upd3_q; +p1_way_data_upd5_wayF <= p1_congr_cl5_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu5_wayF_upd(0) <= p1_way_data_upd5_wayF and p1_wren_q; +rel_bixu5_wayF_upd(1) <= p0_way_data_upd5_wayF and p0_wren_q; +p0_way_data_upd5_wayG <= p0_congr_cl5_act_q and binv_wayG_upd3_q; +p1_way_data_upd5_wayG <= p1_congr_cl5_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu5_wayG_upd(0) <= p1_way_data_upd5_wayG and p1_wren_q; +rel_bixu5_wayG_upd(1) <= p0_way_data_upd5_wayG and p0_wren_q; +p0_way_data_upd5_wayH <= p0_congr_cl5_act_q and binv_wayH_upd3_q; +p1_way_data_upd5_wayH <= p1_congr_cl5_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu5_wayH_upd(0) <= p1_way_data_upd5_wayH and p1_wren_q; +rel_bixu5_wayH_upd(1) <= p0_way_data_upd5_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl6_m <= (ex5_congr_cl_q = tconv(6,5)); +p1_congr_cl6_m <= (relu_s_congr_cl_q = tconv(6,5)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl6_act_d <= p0_congr_cl6_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl6_act_d <= p1_congr_cl6_m and rel_port_wren_q; +congr_cl6_act <= p0_congr_cl6_act_q or p1_congr_cl6_act_q or congr_cl_all_act_q; +p0_way_data_upd6_wayA <= p0_congr_cl6_act_q and binv_wayA_upd3_q; +p1_way_data_upd6_wayA <= p1_congr_cl6_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu6_wayA_upd(0) <= p1_way_data_upd6_wayA and p1_wren_q; +rel_bixu6_wayA_upd(1) <= p0_way_data_upd6_wayA and p0_wren_q; +p0_way_data_upd6_wayB <= p0_congr_cl6_act_q and binv_wayB_upd3_q; +p1_way_data_upd6_wayB <= p1_congr_cl6_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu6_wayB_upd(0) <= p1_way_data_upd6_wayB and p1_wren_q; +rel_bixu6_wayB_upd(1) <= p0_way_data_upd6_wayB and p0_wren_q; +p0_way_data_upd6_wayC <= p0_congr_cl6_act_q and binv_wayC_upd3_q; +p1_way_data_upd6_wayC <= p1_congr_cl6_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu6_wayC_upd(0) <= p1_way_data_upd6_wayC and p1_wren_q; +rel_bixu6_wayC_upd(1) <= p0_way_data_upd6_wayC and p0_wren_q; +p0_way_data_upd6_wayD <= p0_congr_cl6_act_q and binv_wayD_upd3_q; +p1_way_data_upd6_wayD <= p1_congr_cl6_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu6_wayD_upd(0) <= p1_way_data_upd6_wayD and p1_wren_q; +rel_bixu6_wayD_upd(1) <= p0_way_data_upd6_wayD and p0_wren_q; +p0_way_data_upd6_wayE <= p0_congr_cl6_act_q and binv_wayE_upd3_q; +p1_way_data_upd6_wayE <= p1_congr_cl6_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu6_wayE_upd(0) <= p1_way_data_upd6_wayE and p1_wren_q; +rel_bixu6_wayE_upd(1) <= p0_way_data_upd6_wayE and p0_wren_q; +p0_way_data_upd6_wayF <= p0_congr_cl6_act_q and binv_wayF_upd3_q; +p1_way_data_upd6_wayF <= p1_congr_cl6_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu6_wayF_upd(0) <= p1_way_data_upd6_wayF and p1_wren_q; +rel_bixu6_wayF_upd(1) <= p0_way_data_upd6_wayF and p0_wren_q; +p0_way_data_upd6_wayG <= p0_congr_cl6_act_q and binv_wayG_upd3_q; +p1_way_data_upd6_wayG <= p1_congr_cl6_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu6_wayG_upd(0) <= p1_way_data_upd6_wayG and p1_wren_q; +rel_bixu6_wayG_upd(1) <= p0_way_data_upd6_wayG and p0_wren_q; +p0_way_data_upd6_wayH <= p0_congr_cl6_act_q and binv_wayH_upd3_q; +p1_way_data_upd6_wayH <= p1_congr_cl6_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu6_wayH_upd(0) <= p1_way_data_upd6_wayH and p1_wren_q; +rel_bixu6_wayH_upd(1) <= p0_way_data_upd6_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl7_m <= (ex5_congr_cl_q = tconv(7,5)); +p1_congr_cl7_m <= (relu_s_congr_cl_q = tconv(7,5)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl7_act_d <= p0_congr_cl7_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl7_act_d <= p1_congr_cl7_m and rel_port_wren_q; +congr_cl7_act <= p0_congr_cl7_act_q or p1_congr_cl7_act_q or congr_cl_all_act_q; +p0_way_data_upd7_wayA <= p0_congr_cl7_act_q and binv_wayA_upd3_q; +p1_way_data_upd7_wayA <= p1_congr_cl7_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu7_wayA_upd(0) <= p1_way_data_upd7_wayA and p1_wren_q; +rel_bixu7_wayA_upd(1) <= p0_way_data_upd7_wayA and p0_wren_q; +p0_way_data_upd7_wayB <= p0_congr_cl7_act_q and binv_wayB_upd3_q; +p1_way_data_upd7_wayB <= p1_congr_cl7_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu7_wayB_upd(0) <= p1_way_data_upd7_wayB and p1_wren_q; +rel_bixu7_wayB_upd(1) <= p0_way_data_upd7_wayB and p0_wren_q; +p0_way_data_upd7_wayC <= p0_congr_cl7_act_q and binv_wayC_upd3_q; +p1_way_data_upd7_wayC <= p1_congr_cl7_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu7_wayC_upd(0) <= p1_way_data_upd7_wayC and p1_wren_q; +rel_bixu7_wayC_upd(1) <= p0_way_data_upd7_wayC and p0_wren_q; +p0_way_data_upd7_wayD <= p0_congr_cl7_act_q and binv_wayD_upd3_q; +p1_way_data_upd7_wayD <= p1_congr_cl7_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu7_wayD_upd(0) <= p1_way_data_upd7_wayD and p1_wren_q; +rel_bixu7_wayD_upd(1) <= p0_way_data_upd7_wayD and p0_wren_q; +p0_way_data_upd7_wayE <= p0_congr_cl7_act_q and binv_wayE_upd3_q; +p1_way_data_upd7_wayE <= p1_congr_cl7_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu7_wayE_upd(0) <= p1_way_data_upd7_wayE and p1_wren_q; +rel_bixu7_wayE_upd(1) <= p0_way_data_upd7_wayE and p0_wren_q; +p0_way_data_upd7_wayF <= p0_congr_cl7_act_q and binv_wayF_upd3_q; +p1_way_data_upd7_wayF <= p1_congr_cl7_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu7_wayF_upd(0) <= p1_way_data_upd7_wayF and p1_wren_q; +rel_bixu7_wayF_upd(1) <= p0_way_data_upd7_wayF and p0_wren_q; +p0_way_data_upd7_wayG <= p0_congr_cl7_act_q and binv_wayG_upd3_q; +p1_way_data_upd7_wayG <= p1_congr_cl7_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu7_wayG_upd(0) <= p1_way_data_upd7_wayG and p1_wren_q; +rel_bixu7_wayG_upd(1) <= p0_way_data_upd7_wayG and p0_wren_q; +p0_way_data_upd7_wayH <= p0_congr_cl7_act_q and binv_wayH_upd3_q; +p1_way_data_upd7_wayH <= p1_congr_cl7_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu7_wayH_upd(0) <= p1_way_data_upd7_wayH and p1_wren_q; +rel_bixu7_wayH_upd(1) <= p0_way_data_upd7_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl8_m <= (ex5_congr_cl_q = tconv(8,5)); +p1_congr_cl8_m <= (relu_s_congr_cl_q = tconv(8,5)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl8_act_d <= p0_congr_cl8_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl8_act_d <= p1_congr_cl8_m and rel_port_wren_q; +congr_cl8_act <= p0_congr_cl8_act_q or p1_congr_cl8_act_q or congr_cl_all_act_q; +p0_way_data_upd8_wayA <= p0_congr_cl8_act_q and binv_wayA_upd3_q; +p1_way_data_upd8_wayA <= p1_congr_cl8_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu8_wayA_upd(0) <= p1_way_data_upd8_wayA and p1_wren_q; +rel_bixu8_wayA_upd(1) <= p0_way_data_upd8_wayA and p0_wren_q; +p0_way_data_upd8_wayB <= p0_congr_cl8_act_q and binv_wayB_upd3_q; +p1_way_data_upd8_wayB <= p1_congr_cl8_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu8_wayB_upd(0) <= p1_way_data_upd8_wayB and p1_wren_q; +rel_bixu8_wayB_upd(1) <= p0_way_data_upd8_wayB and p0_wren_q; +p0_way_data_upd8_wayC <= p0_congr_cl8_act_q and binv_wayC_upd3_q; +p1_way_data_upd8_wayC <= p1_congr_cl8_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu8_wayC_upd(0) <= p1_way_data_upd8_wayC and p1_wren_q; +rel_bixu8_wayC_upd(1) <= p0_way_data_upd8_wayC and p0_wren_q; +p0_way_data_upd8_wayD <= p0_congr_cl8_act_q and binv_wayD_upd3_q; +p1_way_data_upd8_wayD <= p1_congr_cl8_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu8_wayD_upd(0) <= p1_way_data_upd8_wayD and p1_wren_q; +rel_bixu8_wayD_upd(1) <= p0_way_data_upd8_wayD and p0_wren_q; +p0_way_data_upd8_wayE <= p0_congr_cl8_act_q and binv_wayE_upd3_q; +p1_way_data_upd8_wayE <= p1_congr_cl8_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu8_wayE_upd(0) <= p1_way_data_upd8_wayE and p1_wren_q; +rel_bixu8_wayE_upd(1) <= p0_way_data_upd8_wayE and p0_wren_q; +p0_way_data_upd8_wayF <= p0_congr_cl8_act_q and binv_wayF_upd3_q; +p1_way_data_upd8_wayF <= p1_congr_cl8_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu8_wayF_upd(0) <= p1_way_data_upd8_wayF and p1_wren_q; +rel_bixu8_wayF_upd(1) <= p0_way_data_upd8_wayF and p0_wren_q; +p0_way_data_upd8_wayG <= p0_congr_cl8_act_q and binv_wayG_upd3_q; +p1_way_data_upd8_wayG <= p1_congr_cl8_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu8_wayG_upd(0) <= p1_way_data_upd8_wayG and p1_wren_q; +rel_bixu8_wayG_upd(1) <= p0_way_data_upd8_wayG and p0_wren_q; +p0_way_data_upd8_wayH <= p0_congr_cl8_act_q and binv_wayH_upd3_q; +p1_way_data_upd8_wayH <= p1_congr_cl8_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu8_wayH_upd(0) <= p1_way_data_upd8_wayH and p1_wren_q; +rel_bixu8_wayH_upd(1) <= p0_way_data_upd8_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl9_m <= (ex5_congr_cl_q = tconv(9,5)); +p1_congr_cl9_m <= (relu_s_congr_cl_q = tconv(9,5)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl9_act_d <= p0_congr_cl9_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl9_act_d <= p1_congr_cl9_m and rel_port_wren_q; +congr_cl9_act <= p0_congr_cl9_act_q or p1_congr_cl9_act_q or congr_cl_all_act_q; +p0_way_data_upd9_wayA <= p0_congr_cl9_act_q and binv_wayA_upd3_q; +p1_way_data_upd9_wayA <= p1_congr_cl9_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu9_wayA_upd(0) <= p1_way_data_upd9_wayA and p1_wren_q; +rel_bixu9_wayA_upd(1) <= p0_way_data_upd9_wayA and p0_wren_q; +p0_way_data_upd9_wayB <= p0_congr_cl9_act_q and binv_wayB_upd3_q; +p1_way_data_upd9_wayB <= p1_congr_cl9_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu9_wayB_upd(0) <= p1_way_data_upd9_wayB and p1_wren_q; +rel_bixu9_wayB_upd(1) <= p0_way_data_upd9_wayB and p0_wren_q; +p0_way_data_upd9_wayC <= p0_congr_cl9_act_q and binv_wayC_upd3_q; +p1_way_data_upd9_wayC <= p1_congr_cl9_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu9_wayC_upd(0) <= p1_way_data_upd9_wayC and p1_wren_q; +rel_bixu9_wayC_upd(1) <= p0_way_data_upd9_wayC and p0_wren_q; +p0_way_data_upd9_wayD <= p0_congr_cl9_act_q and binv_wayD_upd3_q; +p1_way_data_upd9_wayD <= p1_congr_cl9_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu9_wayD_upd(0) <= p1_way_data_upd9_wayD and p1_wren_q; +rel_bixu9_wayD_upd(1) <= p0_way_data_upd9_wayD and p0_wren_q; +p0_way_data_upd9_wayE <= p0_congr_cl9_act_q and binv_wayE_upd3_q; +p1_way_data_upd9_wayE <= p1_congr_cl9_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu9_wayE_upd(0) <= p1_way_data_upd9_wayE and p1_wren_q; +rel_bixu9_wayE_upd(1) <= p0_way_data_upd9_wayE and p0_wren_q; +p0_way_data_upd9_wayF <= p0_congr_cl9_act_q and binv_wayF_upd3_q; +p1_way_data_upd9_wayF <= p1_congr_cl9_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu9_wayF_upd(0) <= p1_way_data_upd9_wayF and p1_wren_q; +rel_bixu9_wayF_upd(1) <= p0_way_data_upd9_wayF and p0_wren_q; +p0_way_data_upd9_wayG <= p0_congr_cl9_act_q and binv_wayG_upd3_q; +p1_way_data_upd9_wayG <= p1_congr_cl9_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu9_wayG_upd(0) <= p1_way_data_upd9_wayG and p1_wren_q; +rel_bixu9_wayG_upd(1) <= p0_way_data_upd9_wayG and p0_wren_q; +p0_way_data_upd9_wayH <= p0_congr_cl9_act_q and binv_wayH_upd3_q; +p1_way_data_upd9_wayH <= p1_congr_cl9_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu9_wayH_upd(0) <= p1_way_data_upd9_wayH and p1_wren_q; +rel_bixu9_wayH_upd(1) <= p0_way_data_upd9_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl10_m <= (ex5_congr_cl_q = tconv(10,5)); +p1_congr_cl10_m <= (relu_s_congr_cl_q = tconv(10,5)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl10_act_d <= p0_congr_cl10_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl10_act_d <= p1_congr_cl10_m and rel_port_wren_q; +congr_cl10_act <= p0_congr_cl10_act_q or p1_congr_cl10_act_q or congr_cl_all_act_q; +p0_way_data_upd10_wayA <= p0_congr_cl10_act_q and binv_wayA_upd3_q; +p1_way_data_upd10_wayA <= p1_congr_cl10_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu10_wayA_upd(0) <= p1_way_data_upd10_wayA and p1_wren_q; +rel_bixu10_wayA_upd(1) <= p0_way_data_upd10_wayA and p0_wren_q; +p0_way_data_upd10_wayB <= p0_congr_cl10_act_q and binv_wayB_upd3_q; +p1_way_data_upd10_wayB <= p1_congr_cl10_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu10_wayB_upd(0) <= p1_way_data_upd10_wayB and p1_wren_q; +rel_bixu10_wayB_upd(1) <= p0_way_data_upd10_wayB and p0_wren_q; +p0_way_data_upd10_wayC <= p0_congr_cl10_act_q and binv_wayC_upd3_q; +p1_way_data_upd10_wayC <= p1_congr_cl10_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu10_wayC_upd(0) <= p1_way_data_upd10_wayC and p1_wren_q; +rel_bixu10_wayC_upd(1) <= p0_way_data_upd10_wayC and p0_wren_q; +p0_way_data_upd10_wayD <= p0_congr_cl10_act_q and binv_wayD_upd3_q; +p1_way_data_upd10_wayD <= p1_congr_cl10_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu10_wayD_upd(0) <= p1_way_data_upd10_wayD and p1_wren_q; +rel_bixu10_wayD_upd(1) <= p0_way_data_upd10_wayD and p0_wren_q; +p0_way_data_upd10_wayE <= p0_congr_cl10_act_q and binv_wayE_upd3_q; +p1_way_data_upd10_wayE <= p1_congr_cl10_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu10_wayE_upd(0) <= p1_way_data_upd10_wayE and p1_wren_q; +rel_bixu10_wayE_upd(1) <= p0_way_data_upd10_wayE and p0_wren_q; +p0_way_data_upd10_wayF <= p0_congr_cl10_act_q and binv_wayF_upd3_q; +p1_way_data_upd10_wayF <= p1_congr_cl10_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu10_wayF_upd(0) <= p1_way_data_upd10_wayF and p1_wren_q; +rel_bixu10_wayF_upd(1) <= p0_way_data_upd10_wayF and p0_wren_q; +p0_way_data_upd10_wayG <= p0_congr_cl10_act_q and binv_wayG_upd3_q; +p1_way_data_upd10_wayG <= p1_congr_cl10_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu10_wayG_upd(0) <= p1_way_data_upd10_wayG and p1_wren_q; +rel_bixu10_wayG_upd(1) <= p0_way_data_upd10_wayG and p0_wren_q; +p0_way_data_upd10_wayH <= p0_congr_cl10_act_q and binv_wayH_upd3_q; +p1_way_data_upd10_wayH <= p1_congr_cl10_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu10_wayH_upd(0) <= p1_way_data_upd10_wayH and p1_wren_q; +rel_bixu10_wayH_upd(1) <= p0_way_data_upd10_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl11_m <= (ex5_congr_cl_q = tconv(11,5)); +p1_congr_cl11_m <= (relu_s_congr_cl_q = tconv(11,5)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl11_act_d <= p0_congr_cl11_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl11_act_d <= p1_congr_cl11_m and rel_port_wren_q; +congr_cl11_act <= p0_congr_cl11_act_q or p1_congr_cl11_act_q or congr_cl_all_act_q; +p0_way_data_upd11_wayA <= p0_congr_cl11_act_q and binv_wayA_upd3_q; +p1_way_data_upd11_wayA <= p1_congr_cl11_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu11_wayA_upd(0) <= p1_way_data_upd11_wayA and p1_wren_q; +rel_bixu11_wayA_upd(1) <= p0_way_data_upd11_wayA and p0_wren_q; +p0_way_data_upd11_wayB <= p0_congr_cl11_act_q and binv_wayB_upd3_q; +p1_way_data_upd11_wayB <= p1_congr_cl11_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu11_wayB_upd(0) <= p1_way_data_upd11_wayB and p1_wren_q; +rel_bixu11_wayB_upd(1) <= p0_way_data_upd11_wayB and p0_wren_q; +p0_way_data_upd11_wayC <= p0_congr_cl11_act_q and binv_wayC_upd3_q; +p1_way_data_upd11_wayC <= p1_congr_cl11_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu11_wayC_upd(0) <= p1_way_data_upd11_wayC and p1_wren_q; +rel_bixu11_wayC_upd(1) <= p0_way_data_upd11_wayC and p0_wren_q; +p0_way_data_upd11_wayD <= p0_congr_cl11_act_q and binv_wayD_upd3_q; +p1_way_data_upd11_wayD <= p1_congr_cl11_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu11_wayD_upd(0) <= p1_way_data_upd11_wayD and p1_wren_q; +rel_bixu11_wayD_upd(1) <= p0_way_data_upd11_wayD and p0_wren_q; +p0_way_data_upd11_wayE <= p0_congr_cl11_act_q and binv_wayE_upd3_q; +p1_way_data_upd11_wayE <= p1_congr_cl11_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu11_wayE_upd(0) <= p1_way_data_upd11_wayE and p1_wren_q; +rel_bixu11_wayE_upd(1) <= p0_way_data_upd11_wayE and p0_wren_q; +p0_way_data_upd11_wayF <= p0_congr_cl11_act_q and binv_wayF_upd3_q; +p1_way_data_upd11_wayF <= p1_congr_cl11_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu11_wayF_upd(0) <= p1_way_data_upd11_wayF and p1_wren_q; +rel_bixu11_wayF_upd(1) <= p0_way_data_upd11_wayF and p0_wren_q; +p0_way_data_upd11_wayG <= p0_congr_cl11_act_q and binv_wayG_upd3_q; +p1_way_data_upd11_wayG <= p1_congr_cl11_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu11_wayG_upd(0) <= p1_way_data_upd11_wayG and p1_wren_q; +rel_bixu11_wayG_upd(1) <= p0_way_data_upd11_wayG and p0_wren_q; +p0_way_data_upd11_wayH <= p0_congr_cl11_act_q and binv_wayH_upd3_q; +p1_way_data_upd11_wayH <= p1_congr_cl11_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu11_wayH_upd(0) <= p1_way_data_upd11_wayH and p1_wren_q; +rel_bixu11_wayH_upd(1) <= p0_way_data_upd11_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl12_m <= (ex5_congr_cl_q = tconv(12,5)); +p1_congr_cl12_m <= (relu_s_congr_cl_q = tconv(12,5)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl12_act_d <= p0_congr_cl12_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl12_act_d <= p1_congr_cl12_m and rel_port_wren_q; +congr_cl12_act <= p0_congr_cl12_act_q or p1_congr_cl12_act_q or congr_cl_all_act_q; +p0_way_data_upd12_wayA <= p0_congr_cl12_act_q and binv_wayA_upd3_q; +p1_way_data_upd12_wayA <= p1_congr_cl12_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu12_wayA_upd(0) <= p1_way_data_upd12_wayA and p1_wren_q; +rel_bixu12_wayA_upd(1) <= p0_way_data_upd12_wayA and p0_wren_q; +p0_way_data_upd12_wayB <= p0_congr_cl12_act_q and binv_wayB_upd3_q; +p1_way_data_upd12_wayB <= p1_congr_cl12_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu12_wayB_upd(0) <= p1_way_data_upd12_wayB and p1_wren_q; +rel_bixu12_wayB_upd(1) <= p0_way_data_upd12_wayB and p0_wren_q; +p0_way_data_upd12_wayC <= p0_congr_cl12_act_q and binv_wayC_upd3_q; +p1_way_data_upd12_wayC <= p1_congr_cl12_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu12_wayC_upd(0) <= p1_way_data_upd12_wayC and p1_wren_q; +rel_bixu12_wayC_upd(1) <= p0_way_data_upd12_wayC and p0_wren_q; +p0_way_data_upd12_wayD <= p0_congr_cl12_act_q and binv_wayD_upd3_q; +p1_way_data_upd12_wayD <= p1_congr_cl12_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu12_wayD_upd(0) <= p1_way_data_upd12_wayD and p1_wren_q; +rel_bixu12_wayD_upd(1) <= p0_way_data_upd12_wayD and p0_wren_q; +p0_way_data_upd12_wayE <= p0_congr_cl12_act_q and binv_wayE_upd3_q; +p1_way_data_upd12_wayE <= p1_congr_cl12_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu12_wayE_upd(0) <= p1_way_data_upd12_wayE and p1_wren_q; +rel_bixu12_wayE_upd(1) <= p0_way_data_upd12_wayE and p0_wren_q; +p0_way_data_upd12_wayF <= p0_congr_cl12_act_q and binv_wayF_upd3_q; +p1_way_data_upd12_wayF <= p1_congr_cl12_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu12_wayF_upd(0) <= p1_way_data_upd12_wayF and p1_wren_q; +rel_bixu12_wayF_upd(1) <= p0_way_data_upd12_wayF and p0_wren_q; +p0_way_data_upd12_wayG <= p0_congr_cl12_act_q and binv_wayG_upd3_q; +p1_way_data_upd12_wayG <= p1_congr_cl12_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu12_wayG_upd(0) <= p1_way_data_upd12_wayG and p1_wren_q; +rel_bixu12_wayG_upd(1) <= p0_way_data_upd12_wayG and p0_wren_q; +p0_way_data_upd12_wayH <= p0_congr_cl12_act_q and binv_wayH_upd3_q; +p1_way_data_upd12_wayH <= p1_congr_cl12_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu12_wayH_upd(0) <= p1_way_data_upd12_wayH and p1_wren_q; +rel_bixu12_wayH_upd(1) <= p0_way_data_upd12_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl13_m <= (ex5_congr_cl_q = tconv(13,5)); +p1_congr_cl13_m <= (relu_s_congr_cl_q = tconv(13,5)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl13_act_d <= p0_congr_cl13_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl13_act_d <= p1_congr_cl13_m and rel_port_wren_q; +congr_cl13_act <= p0_congr_cl13_act_q or p1_congr_cl13_act_q or congr_cl_all_act_q; +p0_way_data_upd13_wayA <= p0_congr_cl13_act_q and binv_wayA_upd3_q; +p1_way_data_upd13_wayA <= p1_congr_cl13_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu13_wayA_upd(0) <= p1_way_data_upd13_wayA and p1_wren_q; +rel_bixu13_wayA_upd(1) <= p0_way_data_upd13_wayA and p0_wren_q; +p0_way_data_upd13_wayB <= p0_congr_cl13_act_q and binv_wayB_upd3_q; +p1_way_data_upd13_wayB <= p1_congr_cl13_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu13_wayB_upd(0) <= p1_way_data_upd13_wayB and p1_wren_q; +rel_bixu13_wayB_upd(1) <= p0_way_data_upd13_wayB and p0_wren_q; +p0_way_data_upd13_wayC <= p0_congr_cl13_act_q and binv_wayC_upd3_q; +p1_way_data_upd13_wayC <= p1_congr_cl13_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu13_wayC_upd(0) <= p1_way_data_upd13_wayC and p1_wren_q; +rel_bixu13_wayC_upd(1) <= p0_way_data_upd13_wayC and p0_wren_q; +p0_way_data_upd13_wayD <= p0_congr_cl13_act_q and binv_wayD_upd3_q; +p1_way_data_upd13_wayD <= p1_congr_cl13_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu13_wayD_upd(0) <= p1_way_data_upd13_wayD and p1_wren_q; +rel_bixu13_wayD_upd(1) <= p0_way_data_upd13_wayD and p0_wren_q; +p0_way_data_upd13_wayE <= p0_congr_cl13_act_q and binv_wayE_upd3_q; +p1_way_data_upd13_wayE <= p1_congr_cl13_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu13_wayE_upd(0) <= p1_way_data_upd13_wayE and p1_wren_q; +rel_bixu13_wayE_upd(1) <= p0_way_data_upd13_wayE and p0_wren_q; +p0_way_data_upd13_wayF <= p0_congr_cl13_act_q and binv_wayF_upd3_q; +p1_way_data_upd13_wayF <= p1_congr_cl13_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu13_wayF_upd(0) <= p1_way_data_upd13_wayF and p1_wren_q; +rel_bixu13_wayF_upd(1) <= p0_way_data_upd13_wayF and p0_wren_q; +p0_way_data_upd13_wayG <= p0_congr_cl13_act_q and binv_wayG_upd3_q; +p1_way_data_upd13_wayG <= p1_congr_cl13_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu13_wayG_upd(0) <= p1_way_data_upd13_wayG and p1_wren_q; +rel_bixu13_wayG_upd(1) <= p0_way_data_upd13_wayG and p0_wren_q; +p0_way_data_upd13_wayH <= p0_congr_cl13_act_q and binv_wayH_upd3_q; +p1_way_data_upd13_wayH <= p1_congr_cl13_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu13_wayH_upd(0) <= p1_way_data_upd13_wayH and p1_wren_q; +rel_bixu13_wayH_upd(1) <= p0_way_data_upd13_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl14_m <= (ex5_congr_cl_q = tconv(14,5)); +p1_congr_cl14_m <= (relu_s_congr_cl_q = tconv(14,5)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl14_act_d <= p0_congr_cl14_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl14_act_d <= p1_congr_cl14_m and rel_port_wren_q; +congr_cl14_act <= p0_congr_cl14_act_q or p1_congr_cl14_act_q or congr_cl_all_act_q; +p0_way_data_upd14_wayA <= p0_congr_cl14_act_q and binv_wayA_upd3_q; +p1_way_data_upd14_wayA <= p1_congr_cl14_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu14_wayA_upd(0) <= p1_way_data_upd14_wayA and p1_wren_q; +rel_bixu14_wayA_upd(1) <= p0_way_data_upd14_wayA and p0_wren_q; +p0_way_data_upd14_wayB <= p0_congr_cl14_act_q and binv_wayB_upd3_q; +p1_way_data_upd14_wayB <= p1_congr_cl14_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu14_wayB_upd(0) <= p1_way_data_upd14_wayB and p1_wren_q; +rel_bixu14_wayB_upd(1) <= p0_way_data_upd14_wayB and p0_wren_q; +p0_way_data_upd14_wayC <= p0_congr_cl14_act_q and binv_wayC_upd3_q; +p1_way_data_upd14_wayC <= p1_congr_cl14_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu14_wayC_upd(0) <= p1_way_data_upd14_wayC and p1_wren_q; +rel_bixu14_wayC_upd(1) <= p0_way_data_upd14_wayC and p0_wren_q; +p0_way_data_upd14_wayD <= p0_congr_cl14_act_q and binv_wayD_upd3_q; +p1_way_data_upd14_wayD <= p1_congr_cl14_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu14_wayD_upd(0) <= p1_way_data_upd14_wayD and p1_wren_q; +rel_bixu14_wayD_upd(1) <= p0_way_data_upd14_wayD and p0_wren_q; +p0_way_data_upd14_wayE <= p0_congr_cl14_act_q and binv_wayE_upd3_q; +p1_way_data_upd14_wayE <= p1_congr_cl14_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu14_wayE_upd(0) <= p1_way_data_upd14_wayE and p1_wren_q; +rel_bixu14_wayE_upd(1) <= p0_way_data_upd14_wayE and p0_wren_q; +p0_way_data_upd14_wayF <= p0_congr_cl14_act_q and binv_wayF_upd3_q; +p1_way_data_upd14_wayF <= p1_congr_cl14_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu14_wayF_upd(0) <= p1_way_data_upd14_wayF and p1_wren_q; +rel_bixu14_wayF_upd(1) <= p0_way_data_upd14_wayF and p0_wren_q; +p0_way_data_upd14_wayG <= p0_congr_cl14_act_q and binv_wayG_upd3_q; +p1_way_data_upd14_wayG <= p1_congr_cl14_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu14_wayG_upd(0) <= p1_way_data_upd14_wayG and p1_wren_q; +rel_bixu14_wayG_upd(1) <= p0_way_data_upd14_wayG and p0_wren_q; +p0_way_data_upd14_wayH <= p0_congr_cl14_act_q and binv_wayH_upd3_q; +p1_way_data_upd14_wayH <= p1_congr_cl14_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu14_wayH_upd(0) <= p1_way_data_upd14_wayH and p1_wren_q; +rel_bixu14_wayH_upd(1) <= p0_way_data_upd14_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl15_m <= (ex5_congr_cl_q = tconv(15,5)); +p1_congr_cl15_m <= (relu_s_congr_cl_q = tconv(15,5)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl15_act_d <= p0_congr_cl15_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl15_act_d <= p1_congr_cl15_m and rel_port_wren_q; +congr_cl15_act <= p0_congr_cl15_act_q or p1_congr_cl15_act_q or congr_cl_all_act_q; +p0_way_data_upd15_wayA <= p0_congr_cl15_act_q and binv_wayA_upd3_q; +p1_way_data_upd15_wayA <= p1_congr_cl15_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu15_wayA_upd(0) <= p1_way_data_upd15_wayA and p1_wren_q; +rel_bixu15_wayA_upd(1) <= p0_way_data_upd15_wayA and p0_wren_q; +p0_way_data_upd15_wayB <= p0_congr_cl15_act_q and binv_wayB_upd3_q; +p1_way_data_upd15_wayB <= p1_congr_cl15_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu15_wayB_upd(0) <= p1_way_data_upd15_wayB and p1_wren_q; +rel_bixu15_wayB_upd(1) <= p0_way_data_upd15_wayB and p0_wren_q; +p0_way_data_upd15_wayC <= p0_congr_cl15_act_q and binv_wayC_upd3_q; +p1_way_data_upd15_wayC <= p1_congr_cl15_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu15_wayC_upd(0) <= p1_way_data_upd15_wayC and p1_wren_q; +rel_bixu15_wayC_upd(1) <= p0_way_data_upd15_wayC and p0_wren_q; +p0_way_data_upd15_wayD <= p0_congr_cl15_act_q and binv_wayD_upd3_q; +p1_way_data_upd15_wayD <= p1_congr_cl15_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu15_wayD_upd(0) <= p1_way_data_upd15_wayD and p1_wren_q; +rel_bixu15_wayD_upd(1) <= p0_way_data_upd15_wayD and p0_wren_q; +p0_way_data_upd15_wayE <= p0_congr_cl15_act_q and binv_wayE_upd3_q; +p1_way_data_upd15_wayE <= p1_congr_cl15_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu15_wayE_upd(0) <= p1_way_data_upd15_wayE and p1_wren_q; +rel_bixu15_wayE_upd(1) <= p0_way_data_upd15_wayE and p0_wren_q; +p0_way_data_upd15_wayF <= p0_congr_cl15_act_q and binv_wayF_upd3_q; +p1_way_data_upd15_wayF <= p1_congr_cl15_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu15_wayF_upd(0) <= p1_way_data_upd15_wayF and p1_wren_q; +rel_bixu15_wayF_upd(1) <= p0_way_data_upd15_wayF and p0_wren_q; +p0_way_data_upd15_wayG <= p0_congr_cl15_act_q and binv_wayG_upd3_q; +p1_way_data_upd15_wayG <= p1_congr_cl15_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu15_wayG_upd(0) <= p1_way_data_upd15_wayG and p1_wren_q; +rel_bixu15_wayG_upd(1) <= p0_way_data_upd15_wayG and p0_wren_q; +p0_way_data_upd15_wayH <= p0_congr_cl15_act_q and binv_wayH_upd3_q; +p1_way_data_upd15_wayH <= p1_congr_cl15_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu15_wayH_upd(0) <= p1_way_data_upd15_wayH and p1_wren_q; +rel_bixu15_wayH_upd(1) <= p0_way_data_upd15_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl16_m <= (ex5_congr_cl_q = tconv(16,5)); +p1_congr_cl16_m <= (relu_s_congr_cl_q = tconv(16,5)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl16_act_d <= p0_congr_cl16_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl16_act_d <= p1_congr_cl16_m and rel_port_wren_q; +congr_cl16_act <= p0_congr_cl16_act_q or p1_congr_cl16_act_q or congr_cl_all_act_q; +p0_way_data_upd16_wayA <= p0_congr_cl16_act_q and binv_wayA_upd3_q; +p1_way_data_upd16_wayA <= p1_congr_cl16_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu16_wayA_upd(0) <= p1_way_data_upd16_wayA and p1_wren_q; +rel_bixu16_wayA_upd(1) <= p0_way_data_upd16_wayA and p0_wren_q; +p0_way_data_upd16_wayB <= p0_congr_cl16_act_q and binv_wayB_upd3_q; +p1_way_data_upd16_wayB <= p1_congr_cl16_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu16_wayB_upd(0) <= p1_way_data_upd16_wayB and p1_wren_q; +rel_bixu16_wayB_upd(1) <= p0_way_data_upd16_wayB and p0_wren_q; +p0_way_data_upd16_wayC <= p0_congr_cl16_act_q and binv_wayC_upd3_q; +p1_way_data_upd16_wayC <= p1_congr_cl16_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu16_wayC_upd(0) <= p1_way_data_upd16_wayC and p1_wren_q; +rel_bixu16_wayC_upd(1) <= p0_way_data_upd16_wayC and p0_wren_q; +p0_way_data_upd16_wayD <= p0_congr_cl16_act_q and binv_wayD_upd3_q; +p1_way_data_upd16_wayD <= p1_congr_cl16_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu16_wayD_upd(0) <= p1_way_data_upd16_wayD and p1_wren_q; +rel_bixu16_wayD_upd(1) <= p0_way_data_upd16_wayD and p0_wren_q; +p0_way_data_upd16_wayE <= p0_congr_cl16_act_q and binv_wayE_upd3_q; +p1_way_data_upd16_wayE <= p1_congr_cl16_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu16_wayE_upd(0) <= p1_way_data_upd16_wayE and p1_wren_q; +rel_bixu16_wayE_upd(1) <= p0_way_data_upd16_wayE and p0_wren_q; +p0_way_data_upd16_wayF <= p0_congr_cl16_act_q and binv_wayF_upd3_q; +p1_way_data_upd16_wayF <= p1_congr_cl16_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu16_wayF_upd(0) <= p1_way_data_upd16_wayF and p1_wren_q; +rel_bixu16_wayF_upd(1) <= p0_way_data_upd16_wayF and p0_wren_q; +p0_way_data_upd16_wayG <= p0_congr_cl16_act_q and binv_wayG_upd3_q; +p1_way_data_upd16_wayG <= p1_congr_cl16_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu16_wayG_upd(0) <= p1_way_data_upd16_wayG and p1_wren_q; +rel_bixu16_wayG_upd(1) <= p0_way_data_upd16_wayG and p0_wren_q; +p0_way_data_upd16_wayH <= p0_congr_cl16_act_q and binv_wayH_upd3_q; +p1_way_data_upd16_wayH <= p1_congr_cl16_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu16_wayH_upd(0) <= p1_way_data_upd16_wayH and p1_wren_q; +rel_bixu16_wayH_upd(1) <= p0_way_data_upd16_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl17_m <= (ex5_congr_cl_q = tconv(17,5)); +p1_congr_cl17_m <= (relu_s_congr_cl_q = tconv(17,5)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl17_act_d <= p0_congr_cl17_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl17_act_d <= p1_congr_cl17_m and rel_port_wren_q; +congr_cl17_act <= p0_congr_cl17_act_q or p1_congr_cl17_act_q or congr_cl_all_act_q; +p0_way_data_upd17_wayA <= p0_congr_cl17_act_q and binv_wayA_upd3_q; +p1_way_data_upd17_wayA <= p1_congr_cl17_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu17_wayA_upd(0) <= p1_way_data_upd17_wayA and p1_wren_q; +rel_bixu17_wayA_upd(1) <= p0_way_data_upd17_wayA and p0_wren_q; +p0_way_data_upd17_wayB <= p0_congr_cl17_act_q and binv_wayB_upd3_q; +p1_way_data_upd17_wayB <= p1_congr_cl17_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu17_wayB_upd(0) <= p1_way_data_upd17_wayB and p1_wren_q; +rel_bixu17_wayB_upd(1) <= p0_way_data_upd17_wayB and p0_wren_q; +p0_way_data_upd17_wayC <= p0_congr_cl17_act_q and binv_wayC_upd3_q; +p1_way_data_upd17_wayC <= p1_congr_cl17_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu17_wayC_upd(0) <= p1_way_data_upd17_wayC and p1_wren_q; +rel_bixu17_wayC_upd(1) <= p0_way_data_upd17_wayC and p0_wren_q; +p0_way_data_upd17_wayD <= p0_congr_cl17_act_q and binv_wayD_upd3_q; +p1_way_data_upd17_wayD <= p1_congr_cl17_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu17_wayD_upd(0) <= p1_way_data_upd17_wayD and p1_wren_q; +rel_bixu17_wayD_upd(1) <= p0_way_data_upd17_wayD and p0_wren_q; +p0_way_data_upd17_wayE <= p0_congr_cl17_act_q and binv_wayE_upd3_q; +p1_way_data_upd17_wayE <= p1_congr_cl17_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu17_wayE_upd(0) <= p1_way_data_upd17_wayE and p1_wren_q; +rel_bixu17_wayE_upd(1) <= p0_way_data_upd17_wayE and p0_wren_q; +p0_way_data_upd17_wayF <= p0_congr_cl17_act_q and binv_wayF_upd3_q; +p1_way_data_upd17_wayF <= p1_congr_cl17_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu17_wayF_upd(0) <= p1_way_data_upd17_wayF and p1_wren_q; +rel_bixu17_wayF_upd(1) <= p0_way_data_upd17_wayF and p0_wren_q; +p0_way_data_upd17_wayG <= p0_congr_cl17_act_q and binv_wayG_upd3_q; +p1_way_data_upd17_wayG <= p1_congr_cl17_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu17_wayG_upd(0) <= p1_way_data_upd17_wayG and p1_wren_q; +rel_bixu17_wayG_upd(1) <= p0_way_data_upd17_wayG and p0_wren_q; +p0_way_data_upd17_wayH <= p0_congr_cl17_act_q and binv_wayH_upd3_q; +p1_way_data_upd17_wayH <= p1_congr_cl17_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu17_wayH_upd(0) <= p1_way_data_upd17_wayH and p1_wren_q; +rel_bixu17_wayH_upd(1) <= p0_way_data_upd17_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl18_m <= (ex5_congr_cl_q = tconv(18,5)); +p1_congr_cl18_m <= (relu_s_congr_cl_q = tconv(18,5)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl18_act_d <= p0_congr_cl18_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl18_act_d <= p1_congr_cl18_m and rel_port_wren_q; +congr_cl18_act <= p0_congr_cl18_act_q or p1_congr_cl18_act_q or congr_cl_all_act_q; +p0_way_data_upd18_wayA <= p0_congr_cl18_act_q and binv_wayA_upd3_q; +p1_way_data_upd18_wayA <= p1_congr_cl18_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu18_wayA_upd(0) <= p1_way_data_upd18_wayA and p1_wren_q; +rel_bixu18_wayA_upd(1) <= p0_way_data_upd18_wayA and p0_wren_q; +p0_way_data_upd18_wayB <= p0_congr_cl18_act_q and binv_wayB_upd3_q; +p1_way_data_upd18_wayB <= p1_congr_cl18_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu18_wayB_upd(0) <= p1_way_data_upd18_wayB and p1_wren_q; +rel_bixu18_wayB_upd(1) <= p0_way_data_upd18_wayB and p0_wren_q; +p0_way_data_upd18_wayC <= p0_congr_cl18_act_q and binv_wayC_upd3_q; +p1_way_data_upd18_wayC <= p1_congr_cl18_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu18_wayC_upd(0) <= p1_way_data_upd18_wayC and p1_wren_q; +rel_bixu18_wayC_upd(1) <= p0_way_data_upd18_wayC and p0_wren_q; +p0_way_data_upd18_wayD <= p0_congr_cl18_act_q and binv_wayD_upd3_q; +p1_way_data_upd18_wayD <= p1_congr_cl18_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu18_wayD_upd(0) <= p1_way_data_upd18_wayD and p1_wren_q; +rel_bixu18_wayD_upd(1) <= p0_way_data_upd18_wayD and p0_wren_q; +p0_way_data_upd18_wayE <= p0_congr_cl18_act_q and binv_wayE_upd3_q; +p1_way_data_upd18_wayE <= p1_congr_cl18_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu18_wayE_upd(0) <= p1_way_data_upd18_wayE and p1_wren_q; +rel_bixu18_wayE_upd(1) <= p0_way_data_upd18_wayE and p0_wren_q; +p0_way_data_upd18_wayF <= p0_congr_cl18_act_q and binv_wayF_upd3_q; +p1_way_data_upd18_wayF <= p1_congr_cl18_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu18_wayF_upd(0) <= p1_way_data_upd18_wayF and p1_wren_q; +rel_bixu18_wayF_upd(1) <= p0_way_data_upd18_wayF and p0_wren_q; +p0_way_data_upd18_wayG <= p0_congr_cl18_act_q and binv_wayG_upd3_q; +p1_way_data_upd18_wayG <= p1_congr_cl18_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu18_wayG_upd(0) <= p1_way_data_upd18_wayG and p1_wren_q; +rel_bixu18_wayG_upd(1) <= p0_way_data_upd18_wayG and p0_wren_q; +p0_way_data_upd18_wayH <= p0_congr_cl18_act_q and binv_wayH_upd3_q; +p1_way_data_upd18_wayH <= p1_congr_cl18_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu18_wayH_upd(0) <= p1_way_data_upd18_wayH and p1_wren_q; +rel_bixu18_wayH_upd(1) <= p0_way_data_upd18_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl19_m <= (ex5_congr_cl_q = tconv(19,5)); +p1_congr_cl19_m <= (relu_s_congr_cl_q = tconv(19,5)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl19_act_d <= p0_congr_cl19_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl19_act_d <= p1_congr_cl19_m and rel_port_wren_q; +congr_cl19_act <= p0_congr_cl19_act_q or p1_congr_cl19_act_q or congr_cl_all_act_q; +p0_way_data_upd19_wayA <= p0_congr_cl19_act_q and binv_wayA_upd3_q; +p1_way_data_upd19_wayA <= p1_congr_cl19_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu19_wayA_upd(0) <= p1_way_data_upd19_wayA and p1_wren_q; +rel_bixu19_wayA_upd(1) <= p0_way_data_upd19_wayA and p0_wren_q; +p0_way_data_upd19_wayB <= p0_congr_cl19_act_q and binv_wayB_upd3_q; +p1_way_data_upd19_wayB <= p1_congr_cl19_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu19_wayB_upd(0) <= p1_way_data_upd19_wayB and p1_wren_q; +rel_bixu19_wayB_upd(1) <= p0_way_data_upd19_wayB and p0_wren_q; +p0_way_data_upd19_wayC <= p0_congr_cl19_act_q and binv_wayC_upd3_q; +p1_way_data_upd19_wayC <= p1_congr_cl19_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu19_wayC_upd(0) <= p1_way_data_upd19_wayC and p1_wren_q; +rel_bixu19_wayC_upd(1) <= p0_way_data_upd19_wayC and p0_wren_q; +p0_way_data_upd19_wayD <= p0_congr_cl19_act_q and binv_wayD_upd3_q; +p1_way_data_upd19_wayD <= p1_congr_cl19_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu19_wayD_upd(0) <= p1_way_data_upd19_wayD and p1_wren_q; +rel_bixu19_wayD_upd(1) <= p0_way_data_upd19_wayD and p0_wren_q; +p0_way_data_upd19_wayE <= p0_congr_cl19_act_q and binv_wayE_upd3_q; +p1_way_data_upd19_wayE <= p1_congr_cl19_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu19_wayE_upd(0) <= p1_way_data_upd19_wayE and p1_wren_q; +rel_bixu19_wayE_upd(1) <= p0_way_data_upd19_wayE and p0_wren_q; +p0_way_data_upd19_wayF <= p0_congr_cl19_act_q and binv_wayF_upd3_q; +p1_way_data_upd19_wayF <= p1_congr_cl19_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu19_wayF_upd(0) <= p1_way_data_upd19_wayF and p1_wren_q; +rel_bixu19_wayF_upd(1) <= p0_way_data_upd19_wayF and p0_wren_q; +p0_way_data_upd19_wayG <= p0_congr_cl19_act_q and binv_wayG_upd3_q; +p1_way_data_upd19_wayG <= p1_congr_cl19_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu19_wayG_upd(0) <= p1_way_data_upd19_wayG and p1_wren_q; +rel_bixu19_wayG_upd(1) <= p0_way_data_upd19_wayG and p0_wren_q; +p0_way_data_upd19_wayH <= p0_congr_cl19_act_q and binv_wayH_upd3_q; +p1_way_data_upd19_wayH <= p1_congr_cl19_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu19_wayH_upd(0) <= p1_way_data_upd19_wayH and p1_wren_q; +rel_bixu19_wayH_upd(1) <= p0_way_data_upd19_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl20_m <= (ex5_congr_cl_q = tconv(20,5)); +p1_congr_cl20_m <= (relu_s_congr_cl_q = tconv(20,5)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl20_act_d <= p0_congr_cl20_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl20_act_d <= p1_congr_cl20_m and rel_port_wren_q; +congr_cl20_act <= p0_congr_cl20_act_q or p1_congr_cl20_act_q or congr_cl_all_act_q; +p0_way_data_upd20_wayA <= p0_congr_cl20_act_q and binv_wayA_upd3_q; +p1_way_data_upd20_wayA <= p1_congr_cl20_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu20_wayA_upd(0) <= p1_way_data_upd20_wayA and p1_wren_q; +rel_bixu20_wayA_upd(1) <= p0_way_data_upd20_wayA and p0_wren_q; +p0_way_data_upd20_wayB <= p0_congr_cl20_act_q and binv_wayB_upd3_q; +p1_way_data_upd20_wayB <= p1_congr_cl20_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu20_wayB_upd(0) <= p1_way_data_upd20_wayB and p1_wren_q; +rel_bixu20_wayB_upd(1) <= p0_way_data_upd20_wayB and p0_wren_q; +p0_way_data_upd20_wayC <= p0_congr_cl20_act_q and binv_wayC_upd3_q; +p1_way_data_upd20_wayC <= p1_congr_cl20_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu20_wayC_upd(0) <= p1_way_data_upd20_wayC and p1_wren_q; +rel_bixu20_wayC_upd(1) <= p0_way_data_upd20_wayC and p0_wren_q; +p0_way_data_upd20_wayD <= p0_congr_cl20_act_q and binv_wayD_upd3_q; +p1_way_data_upd20_wayD <= p1_congr_cl20_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu20_wayD_upd(0) <= p1_way_data_upd20_wayD and p1_wren_q; +rel_bixu20_wayD_upd(1) <= p0_way_data_upd20_wayD and p0_wren_q; +p0_way_data_upd20_wayE <= p0_congr_cl20_act_q and binv_wayE_upd3_q; +p1_way_data_upd20_wayE <= p1_congr_cl20_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu20_wayE_upd(0) <= p1_way_data_upd20_wayE and p1_wren_q; +rel_bixu20_wayE_upd(1) <= p0_way_data_upd20_wayE and p0_wren_q; +p0_way_data_upd20_wayF <= p0_congr_cl20_act_q and binv_wayF_upd3_q; +p1_way_data_upd20_wayF <= p1_congr_cl20_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu20_wayF_upd(0) <= p1_way_data_upd20_wayF and p1_wren_q; +rel_bixu20_wayF_upd(1) <= p0_way_data_upd20_wayF and p0_wren_q; +p0_way_data_upd20_wayG <= p0_congr_cl20_act_q and binv_wayG_upd3_q; +p1_way_data_upd20_wayG <= p1_congr_cl20_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu20_wayG_upd(0) <= p1_way_data_upd20_wayG and p1_wren_q; +rel_bixu20_wayG_upd(1) <= p0_way_data_upd20_wayG and p0_wren_q; +p0_way_data_upd20_wayH <= p0_congr_cl20_act_q and binv_wayH_upd3_q; +p1_way_data_upd20_wayH <= p1_congr_cl20_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu20_wayH_upd(0) <= p1_way_data_upd20_wayH and p1_wren_q; +rel_bixu20_wayH_upd(1) <= p0_way_data_upd20_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl21_m <= (ex5_congr_cl_q = tconv(21,5)); +p1_congr_cl21_m <= (relu_s_congr_cl_q = tconv(21,5)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl21_act_d <= p0_congr_cl21_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl21_act_d <= p1_congr_cl21_m and rel_port_wren_q; +congr_cl21_act <= p0_congr_cl21_act_q or p1_congr_cl21_act_q or congr_cl_all_act_q; +p0_way_data_upd21_wayA <= p0_congr_cl21_act_q and binv_wayA_upd3_q; +p1_way_data_upd21_wayA <= p1_congr_cl21_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu21_wayA_upd(0) <= p1_way_data_upd21_wayA and p1_wren_q; +rel_bixu21_wayA_upd(1) <= p0_way_data_upd21_wayA and p0_wren_q; +p0_way_data_upd21_wayB <= p0_congr_cl21_act_q and binv_wayB_upd3_q; +p1_way_data_upd21_wayB <= p1_congr_cl21_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu21_wayB_upd(0) <= p1_way_data_upd21_wayB and p1_wren_q; +rel_bixu21_wayB_upd(1) <= p0_way_data_upd21_wayB and p0_wren_q; +p0_way_data_upd21_wayC <= p0_congr_cl21_act_q and binv_wayC_upd3_q; +p1_way_data_upd21_wayC <= p1_congr_cl21_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu21_wayC_upd(0) <= p1_way_data_upd21_wayC and p1_wren_q; +rel_bixu21_wayC_upd(1) <= p0_way_data_upd21_wayC and p0_wren_q; +p0_way_data_upd21_wayD <= p0_congr_cl21_act_q and binv_wayD_upd3_q; +p1_way_data_upd21_wayD <= p1_congr_cl21_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu21_wayD_upd(0) <= p1_way_data_upd21_wayD and p1_wren_q; +rel_bixu21_wayD_upd(1) <= p0_way_data_upd21_wayD and p0_wren_q; +p0_way_data_upd21_wayE <= p0_congr_cl21_act_q and binv_wayE_upd3_q; +p1_way_data_upd21_wayE <= p1_congr_cl21_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu21_wayE_upd(0) <= p1_way_data_upd21_wayE and p1_wren_q; +rel_bixu21_wayE_upd(1) <= p0_way_data_upd21_wayE and p0_wren_q; +p0_way_data_upd21_wayF <= p0_congr_cl21_act_q and binv_wayF_upd3_q; +p1_way_data_upd21_wayF <= p1_congr_cl21_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu21_wayF_upd(0) <= p1_way_data_upd21_wayF and p1_wren_q; +rel_bixu21_wayF_upd(1) <= p0_way_data_upd21_wayF and p0_wren_q; +p0_way_data_upd21_wayG <= p0_congr_cl21_act_q and binv_wayG_upd3_q; +p1_way_data_upd21_wayG <= p1_congr_cl21_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu21_wayG_upd(0) <= p1_way_data_upd21_wayG and p1_wren_q; +rel_bixu21_wayG_upd(1) <= p0_way_data_upd21_wayG and p0_wren_q; +p0_way_data_upd21_wayH <= p0_congr_cl21_act_q and binv_wayH_upd3_q; +p1_way_data_upd21_wayH <= p1_congr_cl21_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu21_wayH_upd(0) <= p1_way_data_upd21_wayH and p1_wren_q; +rel_bixu21_wayH_upd(1) <= p0_way_data_upd21_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl22_m <= (ex5_congr_cl_q = tconv(22,5)); +p1_congr_cl22_m <= (relu_s_congr_cl_q = tconv(22,5)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl22_act_d <= p0_congr_cl22_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl22_act_d <= p1_congr_cl22_m and rel_port_wren_q; +congr_cl22_act <= p0_congr_cl22_act_q or p1_congr_cl22_act_q or congr_cl_all_act_q; +p0_way_data_upd22_wayA <= p0_congr_cl22_act_q and binv_wayA_upd3_q; +p1_way_data_upd22_wayA <= p1_congr_cl22_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu22_wayA_upd(0) <= p1_way_data_upd22_wayA and p1_wren_q; +rel_bixu22_wayA_upd(1) <= p0_way_data_upd22_wayA and p0_wren_q; +p0_way_data_upd22_wayB <= p0_congr_cl22_act_q and binv_wayB_upd3_q; +p1_way_data_upd22_wayB <= p1_congr_cl22_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu22_wayB_upd(0) <= p1_way_data_upd22_wayB and p1_wren_q; +rel_bixu22_wayB_upd(1) <= p0_way_data_upd22_wayB and p0_wren_q; +p0_way_data_upd22_wayC <= p0_congr_cl22_act_q and binv_wayC_upd3_q; +p1_way_data_upd22_wayC <= p1_congr_cl22_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu22_wayC_upd(0) <= p1_way_data_upd22_wayC and p1_wren_q; +rel_bixu22_wayC_upd(1) <= p0_way_data_upd22_wayC and p0_wren_q; +p0_way_data_upd22_wayD <= p0_congr_cl22_act_q and binv_wayD_upd3_q; +p1_way_data_upd22_wayD <= p1_congr_cl22_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu22_wayD_upd(0) <= p1_way_data_upd22_wayD and p1_wren_q; +rel_bixu22_wayD_upd(1) <= p0_way_data_upd22_wayD and p0_wren_q; +p0_way_data_upd22_wayE <= p0_congr_cl22_act_q and binv_wayE_upd3_q; +p1_way_data_upd22_wayE <= p1_congr_cl22_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu22_wayE_upd(0) <= p1_way_data_upd22_wayE and p1_wren_q; +rel_bixu22_wayE_upd(1) <= p0_way_data_upd22_wayE and p0_wren_q; +p0_way_data_upd22_wayF <= p0_congr_cl22_act_q and binv_wayF_upd3_q; +p1_way_data_upd22_wayF <= p1_congr_cl22_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu22_wayF_upd(0) <= p1_way_data_upd22_wayF and p1_wren_q; +rel_bixu22_wayF_upd(1) <= p0_way_data_upd22_wayF and p0_wren_q; +p0_way_data_upd22_wayG <= p0_congr_cl22_act_q and binv_wayG_upd3_q; +p1_way_data_upd22_wayG <= p1_congr_cl22_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu22_wayG_upd(0) <= p1_way_data_upd22_wayG and p1_wren_q; +rel_bixu22_wayG_upd(1) <= p0_way_data_upd22_wayG and p0_wren_q; +p0_way_data_upd22_wayH <= p0_congr_cl22_act_q and binv_wayH_upd3_q; +p1_way_data_upd22_wayH <= p1_congr_cl22_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu22_wayH_upd(0) <= p1_way_data_upd22_wayH and p1_wren_q; +rel_bixu22_wayH_upd(1) <= p0_way_data_upd22_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl23_m <= (ex5_congr_cl_q = tconv(23,5)); +p1_congr_cl23_m <= (relu_s_congr_cl_q = tconv(23,5)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl23_act_d <= p0_congr_cl23_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl23_act_d <= p1_congr_cl23_m and rel_port_wren_q; +congr_cl23_act <= p0_congr_cl23_act_q or p1_congr_cl23_act_q or congr_cl_all_act_q; +p0_way_data_upd23_wayA <= p0_congr_cl23_act_q and binv_wayA_upd3_q; +p1_way_data_upd23_wayA <= p1_congr_cl23_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu23_wayA_upd(0) <= p1_way_data_upd23_wayA and p1_wren_q; +rel_bixu23_wayA_upd(1) <= p0_way_data_upd23_wayA and p0_wren_q; +p0_way_data_upd23_wayB <= p0_congr_cl23_act_q and binv_wayB_upd3_q; +p1_way_data_upd23_wayB <= p1_congr_cl23_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu23_wayB_upd(0) <= p1_way_data_upd23_wayB and p1_wren_q; +rel_bixu23_wayB_upd(1) <= p0_way_data_upd23_wayB and p0_wren_q; +p0_way_data_upd23_wayC <= p0_congr_cl23_act_q and binv_wayC_upd3_q; +p1_way_data_upd23_wayC <= p1_congr_cl23_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu23_wayC_upd(0) <= p1_way_data_upd23_wayC and p1_wren_q; +rel_bixu23_wayC_upd(1) <= p0_way_data_upd23_wayC and p0_wren_q; +p0_way_data_upd23_wayD <= p0_congr_cl23_act_q and binv_wayD_upd3_q; +p1_way_data_upd23_wayD <= p1_congr_cl23_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu23_wayD_upd(0) <= p1_way_data_upd23_wayD and p1_wren_q; +rel_bixu23_wayD_upd(1) <= p0_way_data_upd23_wayD and p0_wren_q; +p0_way_data_upd23_wayE <= p0_congr_cl23_act_q and binv_wayE_upd3_q; +p1_way_data_upd23_wayE <= p1_congr_cl23_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu23_wayE_upd(0) <= p1_way_data_upd23_wayE and p1_wren_q; +rel_bixu23_wayE_upd(1) <= p0_way_data_upd23_wayE and p0_wren_q; +p0_way_data_upd23_wayF <= p0_congr_cl23_act_q and binv_wayF_upd3_q; +p1_way_data_upd23_wayF <= p1_congr_cl23_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu23_wayF_upd(0) <= p1_way_data_upd23_wayF and p1_wren_q; +rel_bixu23_wayF_upd(1) <= p0_way_data_upd23_wayF and p0_wren_q; +p0_way_data_upd23_wayG <= p0_congr_cl23_act_q and binv_wayG_upd3_q; +p1_way_data_upd23_wayG <= p1_congr_cl23_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu23_wayG_upd(0) <= p1_way_data_upd23_wayG and p1_wren_q; +rel_bixu23_wayG_upd(1) <= p0_way_data_upd23_wayG and p0_wren_q; +p0_way_data_upd23_wayH <= p0_congr_cl23_act_q and binv_wayH_upd3_q; +p1_way_data_upd23_wayH <= p1_congr_cl23_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu23_wayH_upd(0) <= p1_way_data_upd23_wayH and p1_wren_q; +rel_bixu23_wayH_upd(1) <= p0_way_data_upd23_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl24_m <= (ex5_congr_cl_q = tconv(24,5)); +p1_congr_cl24_m <= (relu_s_congr_cl_q = tconv(24,5)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl24_act_d <= p0_congr_cl24_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl24_act_d <= p1_congr_cl24_m and rel_port_wren_q; +congr_cl24_act <= p0_congr_cl24_act_q or p1_congr_cl24_act_q or congr_cl_all_act_q; +p0_way_data_upd24_wayA <= p0_congr_cl24_act_q and binv_wayA_upd3_q; +p1_way_data_upd24_wayA <= p1_congr_cl24_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu24_wayA_upd(0) <= p1_way_data_upd24_wayA and p1_wren_q; +rel_bixu24_wayA_upd(1) <= p0_way_data_upd24_wayA and p0_wren_q; +p0_way_data_upd24_wayB <= p0_congr_cl24_act_q and binv_wayB_upd3_q; +p1_way_data_upd24_wayB <= p1_congr_cl24_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu24_wayB_upd(0) <= p1_way_data_upd24_wayB and p1_wren_q; +rel_bixu24_wayB_upd(1) <= p0_way_data_upd24_wayB and p0_wren_q; +p0_way_data_upd24_wayC <= p0_congr_cl24_act_q and binv_wayC_upd3_q; +p1_way_data_upd24_wayC <= p1_congr_cl24_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu24_wayC_upd(0) <= p1_way_data_upd24_wayC and p1_wren_q; +rel_bixu24_wayC_upd(1) <= p0_way_data_upd24_wayC and p0_wren_q; +p0_way_data_upd24_wayD <= p0_congr_cl24_act_q and binv_wayD_upd3_q; +p1_way_data_upd24_wayD <= p1_congr_cl24_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu24_wayD_upd(0) <= p1_way_data_upd24_wayD and p1_wren_q; +rel_bixu24_wayD_upd(1) <= p0_way_data_upd24_wayD and p0_wren_q; +p0_way_data_upd24_wayE <= p0_congr_cl24_act_q and binv_wayE_upd3_q; +p1_way_data_upd24_wayE <= p1_congr_cl24_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu24_wayE_upd(0) <= p1_way_data_upd24_wayE and p1_wren_q; +rel_bixu24_wayE_upd(1) <= p0_way_data_upd24_wayE and p0_wren_q; +p0_way_data_upd24_wayF <= p0_congr_cl24_act_q and binv_wayF_upd3_q; +p1_way_data_upd24_wayF <= p1_congr_cl24_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu24_wayF_upd(0) <= p1_way_data_upd24_wayF and p1_wren_q; +rel_bixu24_wayF_upd(1) <= p0_way_data_upd24_wayF and p0_wren_q; +p0_way_data_upd24_wayG <= p0_congr_cl24_act_q and binv_wayG_upd3_q; +p1_way_data_upd24_wayG <= p1_congr_cl24_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu24_wayG_upd(0) <= p1_way_data_upd24_wayG and p1_wren_q; +rel_bixu24_wayG_upd(1) <= p0_way_data_upd24_wayG and p0_wren_q; +p0_way_data_upd24_wayH <= p0_congr_cl24_act_q and binv_wayH_upd3_q; +p1_way_data_upd24_wayH <= p1_congr_cl24_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu24_wayH_upd(0) <= p1_way_data_upd24_wayH and p1_wren_q; +rel_bixu24_wayH_upd(1) <= p0_way_data_upd24_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl25_m <= (ex5_congr_cl_q = tconv(25,5)); +p1_congr_cl25_m <= (relu_s_congr_cl_q = tconv(25,5)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl25_act_d <= p0_congr_cl25_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl25_act_d <= p1_congr_cl25_m and rel_port_wren_q; +congr_cl25_act <= p0_congr_cl25_act_q or p1_congr_cl25_act_q or congr_cl_all_act_q; +p0_way_data_upd25_wayA <= p0_congr_cl25_act_q and binv_wayA_upd3_q; +p1_way_data_upd25_wayA <= p1_congr_cl25_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu25_wayA_upd(0) <= p1_way_data_upd25_wayA and p1_wren_q; +rel_bixu25_wayA_upd(1) <= p0_way_data_upd25_wayA and p0_wren_q; +p0_way_data_upd25_wayB <= p0_congr_cl25_act_q and binv_wayB_upd3_q; +p1_way_data_upd25_wayB <= p1_congr_cl25_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu25_wayB_upd(0) <= p1_way_data_upd25_wayB and p1_wren_q; +rel_bixu25_wayB_upd(1) <= p0_way_data_upd25_wayB and p0_wren_q; +p0_way_data_upd25_wayC <= p0_congr_cl25_act_q and binv_wayC_upd3_q; +p1_way_data_upd25_wayC <= p1_congr_cl25_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu25_wayC_upd(0) <= p1_way_data_upd25_wayC and p1_wren_q; +rel_bixu25_wayC_upd(1) <= p0_way_data_upd25_wayC and p0_wren_q; +p0_way_data_upd25_wayD <= p0_congr_cl25_act_q and binv_wayD_upd3_q; +p1_way_data_upd25_wayD <= p1_congr_cl25_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu25_wayD_upd(0) <= p1_way_data_upd25_wayD and p1_wren_q; +rel_bixu25_wayD_upd(1) <= p0_way_data_upd25_wayD and p0_wren_q; +p0_way_data_upd25_wayE <= p0_congr_cl25_act_q and binv_wayE_upd3_q; +p1_way_data_upd25_wayE <= p1_congr_cl25_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu25_wayE_upd(0) <= p1_way_data_upd25_wayE and p1_wren_q; +rel_bixu25_wayE_upd(1) <= p0_way_data_upd25_wayE and p0_wren_q; +p0_way_data_upd25_wayF <= p0_congr_cl25_act_q and binv_wayF_upd3_q; +p1_way_data_upd25_wayF <= p1_congr_cl25_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu25_wayF_upd(0) <= p1_way_data_upd25_wayF and p1_wren_q; +rel_bixu25_wayF_upd(1) <= p0_way_data_upd25_wayF and p0_wren_q; +p0_way_data_upd25_wayG <= p0_congr_cl25_act_q and binv_wayG_upd3_q; +p1_way_data_upd25_wayG <= p1_congr_cl25_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu25_wayG_upd(0) <= p1_way_data_upd25_wayG and p1_wren_q; +rel_bixu25_wayG_upd(1) <= p0_way_data_upd25_wayG and p0_wren_q; +p0_way_data_upd25_wayH <= p0_congr_cl25_act_q and binv_wayH_upd3_q; +p1_way_data_upd25_wayH <= p1_congr_cl25_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu25_wayH_upd(0) <= p1_way_data_upd25_wayH and p1_wren_q; +rel_bixu25_wayH_upd(1) <= p0_way_data_upd25_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl26_m <= (ex5_congr_cl_q = tconv(26,5)); +p1_congr_cl26_m <= (relu_s_congr_cl_q = tconv(26,5)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl26_act_d <= p0_congr_cl26_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl26_act_d <= p1_congr_cl26_m and rel_port_wren_q; +congr_cl26_act <= p0_congr_cl26_act_q or p1_congr_cl26_act_q or congr_cl_all_act_q; +p0_way_data_upd26_wayA <= p0_congr_cl26_act_q and binv_wayA_upd3_q; +p1_way_data_upd26_wayA <= p1_congr_cl26_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu26_wayA_upd(0) <= p1_way_data_upd26_wayA and p1_wren_q; +rel_bixu26_wayA_upd(1) <= p0_way_data_upd26_wayA and p0_wren_q; +p0_way_data_upd26_wayB <= p0_congr_cl26_act_q and binv_wayB_upd3_q; +p1_way_data_upd26_wayB <= p1_congr_cl26_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu26_wayB_upd(0) <= p1_way_data_upd26_wayB and p1_wren_q; +rel_bixu26_wayB_upd(1) <= p0_way_data_upd26_wayB and p0_wren_q; +p0_way_data_upd26_wayC <= p0_congr_cl26_act_q and binv_wayC_upd3_q; +p1_way_data_upd26_wayC <= p1_congr_cl26_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu26_wayC_upd(0) <= p1_way_data_upd26_wayC and p1_wren_q; +rel_bixu26_wayC_upd(1) <= p0_way_data_upd26_wayC and p0_wren_q; +p0_way_data_upd26_wayD <= p0_congr_cl26_act_q and binv_wayD_upd3_q; +p1_way_data_upd26_wayD <= p1_congr_cl26_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu26_wayD_upd(0) <= p1_way_data_upd26_wayD and p1_wren_q; +rel_bixu26_wayD_upd(1) <= p0_way_data_upd26_wayD and p0_wren_q; +p0_way_data_upd26_wayE <= p0_congr_cl26_act_q and binv_wayE_upd3_q; +p1_way_data_upd26_wayE <= p1_congr_cl26_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu26_wayE_upd(0) <= p1_way_data_upd26_wayE and p1_wren_q; +rel_bixu26_wayE_upd(1) <= p0_way_data_upd26_wayE and p0_wren_q; +p0_way_data_upd26_wayF <= p0_congr_cl26_act_q and binv_wayF_upd3_q; +p1_way_data_upd26_wayF <= p1_congr_cl26_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu26_wayF_upd(0) <= p1_way_data_upd26_wayF and p1_wren_q; +rel_bixu26_wayF_upd(1) <= p0_way_data_upd26_wayF and p0_wren_q; +p0_way_data_upd26_wayG <= p0_congr_cl26_act_q and binv_wayG_upd3_q; +p1_way_data_upd26_wayG <= p1_congr_cl26_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu26_wayG_upd(0) <= p1_way_data_upd26_wayG and p1_wren_q; +rel_bixu26_wayG_upd(1) <= p0_way_data_upd26_wayG and p0_wren_q; +p0_way_data_upd26_wayH <= p0_congr_cl26_act_q and binv_wayH_upd3_q; +p1_way_data_upd26_wayH <= p1_congr_cl26_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu26_wayH_upd(0) <= p1_way_data_upd26_wayH and p1_wren_q; +rel_bixu26_wayH_upd(1) <= p0_way_data_upd26_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl27_m <= (ex5_congr_cl_q = tconv(27,5)); +p1_congr_cl27_m <= (relu_s_congr_cl_q = tconv(27,5)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl27_act_d <= p0_congr_cl27_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl27_act_d <= p1_congr_cl27_m and rel_port_wren_q; +congr_cl27_act <= p0_congr_cl27_act_q or p1_congr_cl27_act_q or congr_cl_all_act_q; +p0_way_data_upd27_wayA <= p0_congr_cl27_act_q and binv_wayA_upd3_q; +p1_way_data_upd27_wayA <= p1_congr_cl27_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu27_wayA_upd(0) <= p1_way_data_upd27_wayA and p1_wren_q; +rel_bixu27_wayA_upd(1) <= p0_way_data_upd27_wayA and p0_wren_q; +p0_way_data_upd27_wayB <= p0_congr_cl27_act_q and binv_wayB_upd3_q; +p1_way_data_upd27_wayB <= p1_congr_cl27_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu27_wayB_upd(0) <= p1_way_data_upd27_wayB and p1_wren_q; +rel_bixu27_wayB_upd(1) <= p0_way_data_upd27_wayB and p0_wren_q; +p0_way_data_upd27_wayC <= p0_congr_cl27_act_q and binv_wayC_upd3_q; +p1_way_data_upd27_wayC <= p1_congr_cl27_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu27_wayC_upd(0) <= p1_way_data_upd27_wayC and p1_wren_q; +rel_bixu27_wayC_upd(1) <= p0_way_data_upd27_wayC and p0_wren_q; +p0_way_data_upd27_wayD <= p0_congr_cl27_act_q and binv_wayD_upd3_q; +p1_way_data_upd27_wayD <= p1_congr_cl27_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu27_wayD_upd(0) <= p1_way_data_upd27_wayD and p1_wren_q; +rel_bixu27_wayD_upd(1) <= p0_way_data_upd27_wayD and p0_wren_q; +p0_way_data_upd27_wayE <= p0_congr_cl27_act_q and binv_wayE_upd3_q; +p1_way_data_upd27_wayE <= p1_congr_cl27_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu27_wayE_upd(0) <= p1_way_data_upd27_wayE and p1_wren_q; +rel_bixu27_wayE_upd(1) <= p0_way_data_upd27_wayE and p0_wren_q; +p0_way_data_upd27_wayF <= p0_congr_cl27_act_q and binv_wayF_upd3_q; +p1_way_data_upd27_wayF <= p1_congr_cl27_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu27_wayF_upd(0) <= p1_way_data_upd27_wayF and p1_wren_q; +rel_bixu27_wayF_upd(1) <= p0_way_data_upd27_wayF and p0_wren_q; +p0_way_data_upd27_wayG <= p0_congr_cl27_act_q and binv_wayG_upd3_q; +p1_way_data_upd27_wayG <= p1_congr_cl27_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu27_wayG_upd(0) <= p1_way_data_upd27_wayG and p1_wren_q; +rel_bixu27_wayG_upd(1) <= p0_way_data_upd27_wayG and p0_wren_q; +p0_way_data_upd27_wayH <= p0_congr_cl27_act_q and binv_wayH_upd3_q; +p1_way_data_upd27_wayH <= p1_congr_cl27_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu27_wayH_upd(0) <= p1_way_data_upd27_wayH and p1_wren_q; +rel_bixu27_wayH_upd(1) <= p0_way_data_upd27_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl28_m <= (ex5_congr_cl_q = tconv(28,5)); +p1_congr_cl28_m <= (relu_s_congr_cl_q = tconv(28,5)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl28_act_d <= p0_congr_cl28_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl28_act_d <= p1_congr_cl28_m and rel_port_wren_q; +congr_cl28_act <= p0_congr_cl28_act_q or p1_congr_cl28_act_q or congr_cl_all_act_q; +p0_way_data_upd28_wayA <= p0_congr_cl28_act_q and binv_wayA_upd3_q; +p1_way_data_upd28_wayA <= p1_congr_cl28_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu28_wayA_upd(0) <= p1_way_data_upd28_wayA and p1_wren_q; +rel_bixu28_wayA_upd(1) <= p0_way_data_upd28_wayA and p0_wren_q; +p0_way_data_upd28_wayB <= p0_congr_cl28_act_q and binv_wayB_upd3_q; +p1_way_data_upd28_wayB <= p1_congr_cl28_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu28_wayB_upd(0) <= p1_way_data_upd28_wayB and p1_wren_q; +rel_bixu28_wayB_upd(1) <= p0_way_data_upd28_wayB and p0_wren_q; +p0_way_data_upd28_wayC <= p0_congr_cl28_act_q and binv_wayC_upd3_q; +p1_way_data_upd28_wayC <= p1_congr_cl28_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu28_wayC_upd(0) <= p1_way_data_upd28_wayC and p1_wren_q; +rel_bixu28_wayC_upd(1) <= p0_way_data_upd28_wayC and p0_wren_q; +p0_way_data_upd28_wayD <= p0_congr_cl28_act_q and binv_wayD_upd3_q; +p1_way_data_upd28_wayD <= p1_congr_cl28_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu28_wayD_upd(0) <= p1_way_data_upd28_wayD and p1_wren_q; +rel_bixu28_wayD_upd(1) <= p0_way_data_upd28_wayD and p0_wren_q; +p0_way_data_upd28_wayE <= p0_congr_cl28_act_q and binv_wayE_upd3_q; +p1_way_data_upd28_wayE <= p1_congr_cl28_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu28_wayE_upd(0) <= p1_way_data_upd28_wayE and p1_wren_q; +rel_bixu28_wayE_upd(1) <= p0_way_data_upd28_wayE and p0_wren_q; +p0_way_data_upd28_wayF <= p0_congr_cl28_act_q and binv_wayF_upd3_q; +p1_way_data_upd28_wayF <= p1_congr_cl28_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu28_wayF_upd(0) <= p1_way_data_upd28_wayF and p1_wren_q; +rel_bixu28_wayF_upd(1) <= p0_way_data_upd28_wayF and p0_wren_q; +p0_way_data_upd28_wayG <= p0_congr_cl28_act_q and binv_wayG_upd3_q; +p1_way_data_upd28_wayG <= p1_congr_cl28_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu28_wayG_upd(0) <= p1_way_data_upd28_wayG and p1_wren_q; +rel_bixu28_wayG_upd(1) <= p0_way_data_upd28_wayG and p0_wren_q; +p0_way_data_upd28_wayH <= p0_congr_cl28_act_q and binv_wayH_upd3_q; +p1_way_data_upd28_wayH <= p1_congr_cl28_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu28_wayH_upd(0) <= p1_way_data_upd28_wayH and p1_wren_q; +rel_bixu28_wayH_upd(1) <= p0_way_data_upd28_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl29_m <= (ex5_congr_cl_q = tconv(29,5)); +p1_congr_cl29_m <= (relu_s_congr_cl_q = tconv(29,5)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl29_act_d <= p0_congr_cl29_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl29_act_d <= p1_congr_cl29_m and rel_port_wren_q; +congr_cl29_act <= p0_congr_cl29_act_q or p1_congr_cl29_act_q or congr_cl_all_act_q; +p0_way_data_upd29_wayA <= p0_congr_cl29_act_q and binv_wayA_upd3_q; +p1_way_data_upd29_wayA <= p1_congr_cl29_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu29_wayA_upd(0) <= p1_way_data_upd29_wayA and p1_wren_q; +rel_bixu29_wayA_upd(1) <= p0_way_data_upd29_wayA and p0_wren_q; +p0_way_data_upd29_wayB <= p0_congr_cl29_act_q and binv_wayB_upd3_q; +p1_way_data_upd29_wayB <= p1_congr_cl29_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu29_wayB_upd(0) <= p1_way_data_upd29_wayB and p1_wren_q; +rel_bixu29_wayB_upd(1) <= p0_way_data_upd29_wayB and p0_wren_q; +p0_way_data_upd29_wayC <= p0_congr_cl29_act_q and binv_wayC_upd3_q; +p1_way_data_upd29_wayC <= p1_congr_cl29_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu29_wayC_upd(0) <= p1_way_data_upd29_wayC and p1_wren_q; +rel_bixu29_wayC_upd(1) <= p0_way_data_upd29_wayC and p0_wren_q; +p0_way_data_upd29_wayD <= p0_congr_cl29_act_q and binv_wayD_upd3_q; +p1_way_data_upd29_wayD <= p1_congr_cl29_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu29_wayD_upd(0) <= p1_way_data_upd29_wayD and p1_wren_q; +rel_bixu29_wayD_upd(1) <= p0_way_data_upd29_wayD and p0_wren_q; +p0_way_data_upd29_wayE <= p0_congr_cl29_act_q and binv_wayE_upd3_q; +p1_way_data_upd29_wayE <= p1_congr_cl29_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu29_wayE_upd(0) <= p1_way_data_upd29_wayE and p1_wren_q; +rel_bixu29_wayE_upd(1) <= p0_way_data_upd29_wayE and p0_wren_q; +p0_way_data_upd29_wayF <= p0_congr_cl29_act_q and binv_wayF_upd3_q; +p1_way_data_upd29_wayF <= p1_congr_cl29_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu29_wayF_upd(0) <= p1_way_data_upd29_wayF and p1_wren_q; +rel_bixu29_wayF_upd(1) <= p0_way_data_upd29_wayF and p0_wren_q; +p0_way_data_upd29_wayG <= p0_congr_cl29_act_q and binv_wayG_upd3_q; +p1_way_data_upd29_wayG <= p1_congr_cl29_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu29_wayG_upd(0) <= p1_way_data_upd29_wayG and p1_wren_q; +rel_bixu29_wayG_upd(1) <= p0_way_data_upd29_wayG and p0_wren_q; +p0_way_data_upd29_wayH <= p0_congr_cl29_act_q and binv_wayH_upd3_q; +p1_way_data_upd29_wayH <= p1_congr_cl29_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu29_wayH_upd(0) <= p1_way_data_upd29_wayH and p1_wren_q; +rel_bixu29_wayH_upd(1) <= p0_way_data_upd29_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl30_m <= (ex5_congr_cl_q = tconv(30,5)); +p1_congr_cl30_m <= (relu_s_congr_cl_q = tconv(30,5)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl30_act_d <= p0_congr_cl30_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl30_act_d <= p1_congr_cl30_m and rel_port_wren_q; +congr_cl30_act <= p0_congr_cl30_act_q or p1_congr_cl30_act_q or congr_cl_all_act_q; +p0_way_data_upd30_wayA <= p0_congr_cl30_act_q and binv_wayA_upd3_q; +p1_way_data_upd30_wayA <= p1_congr_cl30_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu30_wayA_upd(0) <= p1_way_data_upd30_wayA and p1_wren_q; +rel_bixu30_wayA_upd(1) <= p0_way_data_upd30_wayA and p0_wren_q; +p0_way_data_upd30_wayB <= p0_congr_cl30_act_q and binv_wayB_upd3_q; +p1_way_data_upd30_wayB <= p1_congr_cl30_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu30_wayB_upd(0) <= p1_way_data_upd30_wayB and p1_wren_q; +rel_bixu30_wayB_upd(1) <= p0_way_data_upd30_wayB and p0_wren_q; +p0_way_data_upd30_wayC <= p0_congr_cl30_act_q and binv_wayC_upd3_q; +p1_way_data_upd30_wayC <= p1_congr_cl30_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu30_wayC_upd(0) <= p1_way_data_upd30_wayC and p1_wren_q; +rel_bixu30_wayC_upd(1) <= p0_way_data_upd30_wayC and p0_wren_q; +p0_way_data_upd30_wayD <= p0_congr_cl30_act_q and binv_wayD_upd3_q; +p1_way_data_upd30_wayD <= p1_congr_cl30_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu30_wayD_upd(0) <= p1_way_data_upd30_wayD and p1_wren_q; +rel_bixu30_wayD_upd(1) <= p0_way_data_upd30_wayD and p0_wren_q; +p0_way_data_upd30_wayE <= p0_congr_cl30_act_q and binv_wayE_upd3_q; +p1_way_data_upd30_wayE <= p1_congr_cl30_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu30_wayE_upd(0) <= p1_way_data_upd30_wayE and p1_wren_q; +rel_bixu30_wayE_upd(1) <= p0_way_data_upd30_wayE and p0_wren_q; +p0_way_data_upd30_wayF <= p0_congr_cl30_act_q and binv_wayF_upd3_q; +p1_way_data_upd30_wayF <= p1_congr_cl30_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu30_wayF_upd(0) <= p1_way_data_upd30_wayF and p1_wren_q; +rel_bixu30_wayF_upd(1) <= p0_way_data_upd30_wayF and p0_wren_q; +p0_way_data_upd30_wayG <= p0_congr_cl30_act_q and binv_wayG_upd3_q; +p1_way_data_upd30_wayG <= p1_congr_cl30_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu30_wayG_upd(0) <= p1_way_data_upd30_wayG and p1_wren_q; +rel_bixu30_wayG_upd(1) <= p0_way_data_upd30_wayG and p0_wren_q; +p0_way_data_upd30_wayH <= p0_congr_cl30_act_q and binv_wayH_upd3_q; +p1_way_data_upd30_wayH <= p1_congr_cl30_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu30_wayH_upd(0) <= p1_way_data_upd30_wayH and p1_wren_q; +rel_bixu30_wayH_upd(1) <= p0_way_data_upd30_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl31_m <= (ex5_congr_cl_q = tconv(31,5)); +p1_congr_cl31_m <= (relu_s_congr_cl_q = tconv(31,5)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl31_act_d <= p0_congr_cl31_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl31_act_d <= p1_congr_cl31_m and rel_port_wren_q; +congr_cl31_act <= p0_congr_cl31_act_q or p1_congr_cl31_act_q or congr_cl_all_act_q; +p0_way_data_upd31_wayA <= p0_congr_cl31_act_q and binv_wayA_upd3_q; +p1_way_data_upd31_wayA <= p1_congr_cl31_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu31_wayA_upd(0) <= p1_way_data_upd31_wayA and p1_wren_q; +rel_bixu31_wayA_upd(1) <= p0_way_data_upd31_wayA and p0_wren_q; +p0_way_data_upd31_wayB <= p0_congr_cl31_act_q and binv_wayB_upd3_q; +p1_way_data_upd31_wayB <= p1_congr_cl31_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu31_wayB_upd(0) <= p1_way_data_upd31_wayB and p1_wren_q; +rel_bixu31_wayB_upd(1) <= p0_way_data_upd31_wayB and p0_wren_q; +p0_way_data_upd31_wayC <= p0_congr_cl31_act_q and binv_wayC_upd3_q; +p1_way_data_upd31_wayC <= p1_congr_cl31_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu31_wayC_upd(0) <= p1_way_data_upd31_wayC and p1_wren_q; +rel_bixu31_wayC_upd(1) <= p0_way_data_upd31_wayC and p0_wren_q; +p0_way_data_upd31_wayD <= p0_congr_cl31_act_q and binv_wayD_upd3_q; +p1_way_data_upd31_wayD <= p1_congr_cl31_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu31_wayD_upd(0) <= p1_way_data_upd31_wayD and p1_wren_q; +rel_bixu31_wayD_upd(1) <= p0_way_data_upd31_wayD and p0_wren_q; +p0_way_data_upd31_wayE <= p0_congr_cl31_act_q and binv_wayE_upd3_q; +p1_way_data_upd31_wayE <= p1_congr_cl31_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu31_wayE_upd(0) <= p1_way_data_upd31_wayE and p1_wren_q; +rel_bixu31_wayE_upd(1) <= p0_way_data_upd31_wayE and p0_wren_q; +p0_way_data_upd31_wayF <= p0_congr_cl31_act_q and binv_wayF_upd3_q; +p1_way_data_upd31_wayF <= p1_congr_cl31_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu31_wayF_upd(0) <= p1_way_data_upd31_wayF and p1_wren_q; +rel_bixu31_wayF_upd(1) <= p0_way_data_upd31_wayF and p0_wren_q; +p0_way_data_upd31_wayG <= p0_congr_cl31_act_q and binv_wayG_upd3_q; +p1_way_data_upd31_wayG <= p1_congr_cl31_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu31_wayG_upd(0) <= p1_way_data_upd31_wayG and p1_wren_q; +rel_bixu31_wayG_upd(1) <= p0_way_data_upd31_wayG and p0_wren_q; +p0_way_data_upd31_wayH <= p0_congr_cl31_act_q and binv_wayH_upd3_q; +p1_way_data_upd31_wayH <= p1_congr_cl31_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu31_wayH_upd(0) <= p1_way_data_upd31_wayH and p1_wren_q; +rel_bixu31_wayH_upd(1) <= p0_way_data_upd31_wayH and p0_wren_q; +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Write Select for WayA +-- WayA Valid Bit Update for Congruence Class 0 +with rel_bixu0_wayA_upd select + congr_cl0_wA_d(0) <= (congr_cl0_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 0 +with rel_bixu0_wayA_upd select + congr_cl0_wA_d(1) <= (congr_cl0_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayA_upd select + congr_cl0_wA_d(2) <= (congr_cl0_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayA_upd select + congr_cl0_wA_d(3) <= (congr_cl0_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayA_upd select + congr_cl0_wA_d(4) <= (congr_cl0_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayA_upd select + congr_cl0_wA_d(5) <= (congr_cl0_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 1 +with rel_bixu1_wayA_upd select + congr_cl1_wA_d(0) <= (congr_cl1_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 1 +with rel_bixu1_wayA_upd select + congr_cl1_wA_d(1) <= (congr_cl1_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayA_upd select + congr_cl1_wA_d(2) <= (congr_cl1_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayA_upd select + congr_cl1_wA_d(3) <= (congr_cl1_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayA_upd select + congr_cl1_wA_d(4) <= (congr_cl1_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayA_upd select + congr_cl1_wA_d(5) <= (congr_cl1_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 2 +with rel_bixu2_wayA_upd select + congr_cl2_wA_d(0) <= (congr_cl2_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 2 +with rel_bixu2_wayA_upd select + congr_cl2_wA_d(1) <= (congr_cl2_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayA_upd select + congr_cl2_wA_d(2) <= (congr_cl2_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayA_upd select + congr_cl2_wA_d(3) <= (congr_cl2_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayA_upd select + congr_cl2_wA_d(4) <= (congr_cl2_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayA_upd select + congr_cl2_wA_d(5) <= (congr_cl2_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 3 +with rel_bixu3_wayA_upd select + congr_cl3_wA_d(0) <= (congr_cl3_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 3 +with rel_bixu3_wayA_upd select + congr_cl3_wA_d(1) <= (congr_cl3_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayA_upd select + congr_cl3_wA_d(2) <= (congr_cl3_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayA_upd select + congr_cl3_wA_d(3) <= (congr_cl3_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayA_upd select + congr_cl3_wA_d(4) <= (congr_cl3_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayA_upd select + congr_cl3_wA_d(5) <= (congr_cl3_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 4 +with rel_bixu4_wayA_upd select + congr_cl4_wA_d(0) <= (congr_cl4_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 4 +with rel_bixu4_wayA_upd select + congr_cl4_wA_d(1) <= (congr_cl4_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayA_upd select + congr_cl4_wA_d(2) <= (congr_cl4_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayA_upd select + congr_cl4_wA_d(3) <= (congr_cl4_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayA_upd select + congr_cl4_wA_d(4) <= (congr_cl4_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayA_upd select + congr_cl4_wA_d(5) <= (congr_cl4_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 5 +with rel_bixu5_wayA_upd select + congr_cl5_wA_d(0) <= (congr_cl5_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 5 +with rel_bixu5_wayA_upd select + congr_cl5_wA_d(1) <= (congr_cl5_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayA_upd select + congr_cl5_wA_d(2) <= (congr_cl5_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayA_upd select + congr_cl5_wA_d(3) <= (congr_cl5_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayA_upd select + congr_cl5_wA_d(4) <= (congr_cl5_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayA_upd select + congr_cl5_wA_d(5) <= (congr_cl5_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 6 +with rel_bixu6_wayA_upd select + congr_cl6_wA_d(0) <= (congr_cl6_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 6 +with rel_bixu6_wayA_upd select + congr_cl6_wA_d(1) <= (congr_cl6_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayA_upd select + congr_cl6_wA_d(2) <= (congr_cl6_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayA_upd select + congr_cl6_wA_d(3) <= (congr_cl6_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayA_upd select + congr_cl6_wA_d(4) <= (congr_cl6_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayA_upd select + congr_cl6_wA_d(5) <= (congr_cl6_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 7 +with rel_bixu7_wayA_upd select + congr_cl7_wA_d(0) <= (congr_cl7_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 7 +with rel_bixu7_wayA_upd select + congr_cl7_wA_d(1) <= (congr_cl7_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayA_upd select + congr_cl7_wA_d(2) <= (congr_cl7_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayA_upd select + congr_cl7_wA_d(3) <= (congr_cl7_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayA_upd select + congr_cl7_wA_d(4) <= (congr_cl7_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayA_upd select + congr_cl7_wA_d(5) <= (congr_cl7_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 8 +with rel_bixu8_wayA_upd select + congr_cl8_wA_d(0) <= (congr_cl8_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 8 +with rel_bixu8_wayA_upd select + congr_cl8_wA_d(1) <= (congr_cl8_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayA_upd select + congr_cl8_wA_d(2) <= (congr_cl8_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayA_upd select + congr_cl8_wA_d(3) <= (congr_cl8_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayA_upd select + congr_cl8_wA_d(4) <= (congr_cl8_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayA_upd select + congr_cl8_wA_d(5) <= (congr_cl8_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 9 +with rel_bixu9_wayA_upd select + congr_cl9_wA_d(0) <= (congr_cl9_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 9 +with rel_bixu9_wayA_upd select + congr_cl9_wA_d(1) <= (congr_cl9_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayA_upd select + congr_cl9_wA_d(2) <= (congr_cl9_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayA_upd select + congr_cl9_wA_d(3) <= (congr_cl9_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayA_upd select + congr_cl9_wA_d(4) <= (congr_cl9_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayA_upd select + congr_cl9_wA_d(5) <= (congr_cl9_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 10 +with rel_bixu10_wayA_upd select + congr_cl10_wA_d(0) <= (congr_cl10_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 10 +with rel_bixu10_wayA_upd select + congr_cl10_wA_d(1) <= (congr_cl10_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayA_upd select + congr_cl10_wA_d(2) <= (congr_cl10_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayA_upd select + congr_cl10_wA_d(3) <= (congr_cl10_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayA_upd select + congr_cl10_wA_d(4) <= (congr_cl10_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayA_upd select + congr_cl10_wA_d(5) <= (congr_cl10_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 11 +with rel_bixu11_wayA_upd select + congr_cl11_wA_d(0) <= (congr_cl11_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 11 +with rel_bixu11_wayA_upd select + congr_cl11_wA_d(1) <= (congr_cl11_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayA_upd select + congr_cl11_wA_d(2) <= (congr_cl11_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayA_upd select + congr_cl11_wA_d(3) <= (congr_cl11_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayA_upd select + congr_cl11_wA_d(4) <= (congr_cl11_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayA_upd select + congr_cl11_wA_d(5) <= (congr_cl11_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 12 +with rel_bixu12_wayA_upd select + congr_cl12_wA_d(0) <= (congr_cl12_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 12 +with rel_bixu12_wayA_upd select + congr_cl12_wA_d(1) <= (congr_cl12_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayA_upd select + congr_cl12_wA_d(2) <= (congr_cl12_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayA_upd select + congr_cl12_wA_d(3) <= (congr_cl12_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayA_upd select + congr_cl12_wA_d(4) <= (congr_cl12_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayA_upd select + congr_cl12_wA_d(5) <= (congr_cl12_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 13 +with rel_bixu13_wayA_upd select + congr_cl13_wA_d(0) <= (congr_cl13_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 13 +with rel_bixu13_wayA_upd select + congr_cl13_wA_d(1) <= (congr_cl13_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayA_upd select + congr_cl13_wA_d(2) <= (congr_cl13_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayA_upd select + congr_cl13_wA_d(3) <= (congr_cl13_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayA_upd select + congr_cl13_wA_d(4) <= (congr_cl13_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayA_upd select + congr_cl13_wA_d(5) <= (congr_cl13_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 14 +with rel_bixu14_wayA_upd select + congr_cl14_wA_d(0) <= (congr_cl14_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 14 +with rel_bixu14_wayA_upd select + congr_cl14_wA_d(1) <= (congr_cl14_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayA_upd select + congr_cl14_wA_d(2) <= (congr_cl14_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayA_upd select + congr_cl14_wA_d(3) <= (congr_cl14_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayA_upd select + congr_cl14_wA_d(4) <= (congr_cl14_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayA_upd select + congr_cl14_wA_d(5) <= (congr_cl14_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 15 +with rel_bixu15_wayA_upd select + congr_cl15_wA_d(0) <= (congr_cl15_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 15 +with rel_bixu15_wayA_upd select + congr_cl15_wA_d(1) <= (congr_cl15_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayA_upd select + congr_cl15_wA_d(2) <= (congr_cl15_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayA_upd select + congr_cl15_wA_d(3) <= (congr_cl15_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayA_upd select + congr_cl15_wA_d(4) <= (congr_cl15_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayA_upd select + congr_cl15_wA_d(5) <= (congr_cl15_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 16 +with rel_bixu16_wayA_upd select + congr_cl16_wA_d(0) <= (congr_cl16_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 16 +with rel_bixu16_wayA_upd select + congr_cl16_wA_d(1) <= (congr_cl16_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayA_upd select + congr_cl16_wA_d(2) <= (congr_cl16_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayA_upd select + congr_cl16_wA_d(3) <= (congr_cl16_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayA_upd select + congr_cl16_wA_d(4) <= (congr_cl16_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayA_upd select + congr_cl16_wA_d(5) <= (congr_cl16_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 17 +with rel_bixu17_wayA_upd select + congr_cl17_wA_d(0) <= (congr_cl17_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 17 +with rel_bixu17_wayA_upd select + congr_cl17_wA_d(1) <= (congr_cl17_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayA_upd select + congr_cl17_wA_d(2) <= (congr_cl17_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayA_upd select + congr_cl17_wA_d(3) <= (congr_cl17_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayA_upd select + congr_cl17_wA_d(4) <= (congr_cl17_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayA_upd select + congr_cl17_wA_d(5) <= (congr_cl17_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 18 +with rel_bixu18_wayA_upd select + congr_cl18_wA_d(0) <= (congr_cl18_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 18 +with rel_bixu18_wayA_upd select + congr_cl18_wA_d(1) <= (congr_cl18_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayA_upd select + congr_cl18_wA_d(2) <= (congr_cl18_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayA_upd select + congr_cl18_wA_d(3) <= (congr_cl18_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayA_upd select + congr_cl18_wA_d(4) <= (congr_cl18_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayA_upd select + congr_cl18_wA_d(5) <= (congr_cl18_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 19 +with rel_bixu19_wayA_upd select + congr_cl19_wA_d(0) <= (congr_cl19_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 19 +with rel_bixu19_wayA_upd select + congr_cl19_wA_d(1) <= (congr_cl19_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayA_upd select + congr_cl19_wA_d(2) <= (congr_cl19_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayA_upd select + congr_cl19_wA_d(3) <= (congr_cl19_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayA_upd select + congr_cl19_wA_d(4) <= (congr_cl19_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayA_upd select + congr_cl19_wA_d(5) <= (congr_cl19_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 20 +with rel_bixu20_wayA_upd select + congr_cl20_wA_d(0) <= (congr_cl20_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 20 +with rel_bixu20_wayA_upd select + congr_cl20_wA_d(1) <= (congr_cl20_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayA_upd select + congr_cl20_wA_d(2) <= (congr_cl20_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayA_upd select + congr_cl20_wA_d(3) <= (congr_cl20_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayA_upd select + congr_cl20_wA_d(4) <= (congr_cl20_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayA_upd select + congr_cl20_wA_d(5) <= (congr_cl20_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 21 +with rel_bixu21_wayA_upd select + congr_cl21_wA_d(0) <= (congr_cl21_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 21 +with rel_bixu21_wayA_upd select + congr_cl21_wA_d(1) <= (congr_cl21_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayA_upd select + congr_cl21_wA_d(2) <= (congr_cl21_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayA_upd select + congr_cl21_wA_d(3) <= (congr_cl21_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayA_upd select + congr_cl21_wA_d(4) <= (congr_cl21_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayA_upd select + congr_cl21_wA_d(5) <= (congr_cl21_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 22 +with rel_bixu22_wayA_upd select + congr_cl22_wA_d(0) <= (congr_cl22_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 22 +with rel_bixu22_wayA_upd select + congr_cl22_wA_d(1) <= (congr_cl22_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayA_upd select + congr_cl22_wA_d(2) <= (congr_cl22_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayA_upd select + congr_cl22_wA_d(3) <= (congr_cl22_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayA_upd select + congr_cl22_wA_d(4) <= (congr_cl22_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayA_upd select + congr_cl22_wA_d(5) <= (congr_cl22_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 23 +with rel_bixu23_wayA_upd select + congr_cl23_wA_d(0) <= (congr_cl23_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 23 +with rel_bixu23_wayA_upd select + congr_cl23_wA_d(1) <= (congr_cl23_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayA_upd select + congr_cl23_wA_d(2) <= (congr_cl23_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayA_upd select + congr_cl23_wA_d(3) <= (congr_cl23_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayA_upd select + congr_cl23_wA_d(4) <= (congr_cl23_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayA_upd select + congr_cl23_wA_d(5) <= (congr_cl23_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 24 +with rel_bixu24_wayA_upd select + congr_cl24_wA_d(0) <= (congr_cl24_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 24 +with rel_bixu24_wayA_upd select + congr_cl24_wA_d(1) <= (congr_cl24_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayA_upd select + congr_cl24_wA_d(2) <= (congr_cl24_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayA_upd select + congr_cl24_wA_d(3) <= (congr_cl24_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayA_upd select + congr_cl24_wA_d(4) <= (congr_cl24_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayA_upd select + congr_cl24_wA_d(5) <= (congr_cl24_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 25 +with rel_bixu25_wayA_upd select + congr_cl25_wA_d(0) <= (congr_cl25_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 25 +with rel_bixu25_wayA_upd select + congr_cl25_wA_d(1) <= (congr_cl25_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayA_upd select + congr_cl25_wA_d(2) <= (congr_cl25_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayA_upd select + congr_cl25_wA_d(3) <= (congr_cl25_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayA_upd select + congr_cl25_wA_d(4) <= (congr_cl25_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayA_upd select + congr_cl25_wA_d(5) <= (congr_cl25_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 26 +with rel_bixu26_wayA_upd select + congr_cl26_wA_d(0) <= (congr_cl26_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 26 +with rel_bixu26_wayA_upd select + congr_cl26_wA_d(1) <= (congr_cl26_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayA_upd select + congr_cl26_wA_d(2) <= (congr_cl26_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayA_upd select + congr_cl26_wA_d(3) <= (congr_cl26_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayA_upd select + congr_cl26_wA_d(4) <= (congr_cl26_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayA_upd select + congr_cl26_wA_d(5) <= (congr_cl26_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 27 +with rel_bixu27_wayA_upd select + congr_cl27_wA_d(0) <= (congr_cl27_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 27 +with rel_bixu27_wayA_upd select + congr_cl27_wA_d(1) <= (congr_cl27_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayA_upd select + congr_cl27_wA_d(2) <= (congr_cl27_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayA_upd select + congr_cl27_wA_d(3) <= (congr_cl27_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayA_upd select + congr_cl27_wA_d(4) <= (congr_cl27_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayA_upd select + congr_cl27_wA_d(5) <= (congr_cl27_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 28 +with rel_bixu28_wayA_upd select + congr_cl28_wA_d(0) <= (congr_cl28_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 28 +with rel_bixu28_wayA_upd select + congr_cl28_wA_d(1) <= (congr_cl28_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayA_upd select + congr_cl28_wA_d(2) <= (congr_cl28_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayA_upd select + congr_cl28_wA_d(3) <= (congr_cl28_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayA_upd select + congr_cl28_wA_d(4) <= (congr_cl28_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayA_upd select + congr_cl28_wA_d(5) <= (congr_cl28_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 29 +with rel_bixu29_wayA_upd select + congr_cl29_wA_d(0) <= (congr_cl29_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 29 +with rel_bixu29_wayA_upd select + congr_cl29_wA_d(1) <= (congr_cl29_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayA_upd select + congr_cl29_wA_d(2) <= (congr_cl29_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayA_upd select + congr_cl29_wA_d(3) <= (congr_cl29_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayA_upd select + congr_cl29_wA_d(4) <= (congr_cl29_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayA_upd select + congr_cl29_wA_d(5) <= (congr_cl29_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 30 +with rel_bixu30_wayA_upd select + congr_cl30_wA_d(0) <= (congr_cl30_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 30 +with rel_bixu30_wayA_upd select + congr_cl30_wA_d(1) <= (congr_cl30_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayA_upd select + congr_cl30_wA_d(2) <= (congr_cl30_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayA_upd select + congr_cl30_wA_d(3) <= (congr_cl30_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayA_upd select + congr_cl30_wA_d(4) <= (congr_cl30_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayA_upd select + congr_cl30_wA_d(5) <= (congr_cl30_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 31 +with rel_bixu31_wayA_upd select + congr_cl31_wA_d(0) <= (congr_cl31_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 31 +with rel_bixu31_wayA_upd select + congr_cl31_wA_d(1) <= (congr_cl31_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayA_upd select + congr_cl31_wA_d(2) <= (congr_cl31_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayA_upd select + congr_cl31_wA_d(3) <= (congr_cl31_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayA_upd select + congr_cl31_wA_d(4) <= (congr_cl31_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayA_upd select + congr_cl31_wA_d(5) <= (congr_cl31_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Write Select for WayB +-- WayB Valid Bit Update for Congruence Class 0 +with rel_bixu0_wayB_upd select + congr_cl0_wB_d(0) <= (congr_cl0_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 0 +with rel_bixu0_wayB_upd select + congr_cl0_wB_d(1) <= (congr_cl0_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayB_upd select + congr_cl0_wB_d(2) <= (congr_cl0_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayB_upd select + congr_cl0_wB_d(3) <= (congr_cl0_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayB_upd select + congr_cl0_wB_d(4) <= (congr_cl0_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayB_upd select + congr_cl0_wB_d(5) <= (congr_cl0_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 1 +with rel_bixu1_wayB_upd select + congr_cl1_wB_d(0) <= (congr_cl1_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 1 +with rel_bixu1_wayB_upd select + congr_cl1_wB_d(1) <= (congr_cl1_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayB_upd select + congr_cl1_wB_d(2) <= (congr_cl1_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayB_upd select + congr_cl1_wB_d(3) <= (congr_cl1_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayB_upd select + congr_cl1_wB_d(4) <= (congr_cl1_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayB_upd select + congr_cl1_wB_d(5) <= (congr_cl1_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 2 +with rel_bixu2_wayB_upd select + congr_cl2_wB_d(0) <= (congr_cl2_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 2 +with rel_bixu2_wayB_upd select + congr_cl2_wB_d(1) <= (congr_cl2_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayB_upd select + congr_cl2_wB_d(2) <= (congr_cl2_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayB_upd select + congr_cl2_wB_d(3) <= (congr_cl2_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayB_upd select + congr_cl2_wB_d(4) <= (congr_cl2_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayB_upd select + congr_cl2_wB_d(5) <= (congr_cl2_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 3 +with rel_bixu3_wayB_upd select + congr_cl3_wB_d(0) <= (congr_cl3_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 3 +with rel_bixu3_wayB_upd select + congr_cl3_wB_d(1) <= (congr_cl3_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayB_upd select + congr_cl3_wB_d(2) <= (congr_cl3_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayB_upd select + congr_cl3_wB_d(3) <= (congr_cl3_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayB_upd select + congr_cl3_wB_d(4) <= (congr_cl3_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayB_upd select + congr_cl3_wB_d(5) <= (congr_cl3_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 4 +with rel_bixu4_wayB_upd select + congr_cl4_wB_d(0) <= (congr_cl4_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 4 +with rel_bixu4_wayB_upd select + congr_cl4_wB_d(1) <= (congr_cl4_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayB_upd select + congr_cl4_wB_d(2) <= (congr_cl4_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayB_upd select + congr_cl4_wB_d(3) <= (congr_cl4_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayB_upd select + congr_cl4_wB_d(4) <= (congr_cl4_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayB_upd select + congr_cl4_wB_d(5) <= (congr_cl4_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 5 +with rel_bixu5_wayB_upd select + congr_cl5_wB_d(0) <= (congr_cl5_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 5 +with rel_bixu5_wayB_upd select + congr_cl5_wB_d(1) <= (congr_cl5_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayB_upd select + congr_cl5_wB_d(2) <= (congr_cl5_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayB_upd select + congr_cl5_wB_d(3) <= (congr_cl5_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayB_upd select + congr_cl5_wB_d(4) <= (congr_cl5_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayB_upd select + congr_cl5_wB_d(5) <= (congr_cl5_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 6 +with rel_bixu6_wayB_upd select + congr_cl6_wB_d(0) <= (congr_cl6_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 6 +with rel_bixu6_wayB_upd select + congr_cl6_wB_d(1) <= (congr_cl6_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayB_upd select + congr_cl6_wB_d(2) <= (congr_cl6_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayB_upd select + congr_cl6_wB_d(3) <= (congr_cl6_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayB_upd select + congr_cl6_wB_d(4) <= (congr_cl6_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayB_upd select + congr_cl6_wB_d(5) <= (congr_cl6_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 7 +with rel_bixu7_wayB_upd select + congr_cl7_wB_d(0) <= (congr_cl7_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 7 +with rel_bixu7_wayB_upd select + congr_cl7_wB_d(1) <= (congr_cl7_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayB_upd select + congr_cl7_wB_d(2) <= (congr_cl7_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayB_upd select + congr_cl7_wB_d(3) <= (congr_cl7_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayB_upd select + congr_cl7_wB_d(4) <= (congr_cl7_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayB_upd select + congr_cl7_wB_d(5) <= (congr_cl7_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 8 +with rel_bixu8_wayB_upd select + congr_cl8_wB_d(0) <= (congr_cl8_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 8 +with rel_bixu8_wayB_upd select + congr_cl8_wB_d(1) <= (congr_cl8_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayB_upd select + congr_cl8_wB_d(2) <= (congr_cl8_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayB_upd select + congr_cl8_wB_d(3) <= (congr_cl8_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayB_upd select + congr_cl8_wB_d(4) <= (congr_cl8_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayB_upd select + congr_cl8_wB_d(5) <= (congr_cl8_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 9 +with rel_bixu9_wayB_upd select + congr_cl9_wB_d(0) <= (congr_cl9_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 9 +with rel_bixu9_wayB_upd select + congr_cl9_wB_d(1) <= (congr_cl9_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayB_upd select + congr_cl9_wB_d(2) <= (congr_cl9_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayB_upd select + congr_cl9_wB_d(3) <= (congr_cl9_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayB_upd select + congr_cl9_wB_d(4) <= (congr_cl9_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayB_upd select + congr_cl9_wB_d(5) <= (congr_cl9_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 10 +with rel_bixu10_wayB_upd select + congr_cl10_wB_d(0) <= (congr_cl10_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 10 +with rel_bixu10_wayB_upd select + congr_cl10_wB_d(1) <= (congr_cl10_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayB_upd select + congr_cl10_wB_d(2) <= (congr_cl10_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayB_upd select + congr_cl10_wB_d(3) <= (congr_cl10_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayB_upd select + congr_cl10_wB_d(4) <= (congr_cl10_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayB_upd select + congr_cl10_wB_d(5) <= (congr_cl10_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 11 +with rel_bixu11_wayB_upd select + congr_cl11_wB_d(0) <= (congr_cl11_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 11 +with rel_bixu11_wayB_upd select + congr_cl11_wB_d(1) <= (congr_cl11_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayB_upd select + congr_cl11_wB_d(2) <= (congr_cl11_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayB_upd select + congr_cl11_wB_d(3) <= (congr_cl11_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayB_upd select + congr_cl11_wB_d(4) <= (congr_cl11_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayB_upd select + congr_cl11_wB_d(5) <= (congr_cl11_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 12 +with rel_bixu12_wayB_upd select + congr_cl12_wB_d(0) <= (congr_cl12_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 12 +with rel_bixu12_wayB_upd select + congr_cl12_wB_d(1) <= (congr_cl12_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayB_upd select + congr_cl12_wB_d(2) <= (congr_cl12_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayB_upd select + congr_cl12_wB_d(3) <= (congr_cl12_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayB_upd select + congr_cl12_wB_d(4) <= (congr_cl12_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayB_upd select + congr_cl12_wB_d(5) <= (congr_cl12_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 13 +with rel_bixu13_wayB_upd select + congr_cl13_wB_d(0) <= (congr_cl13_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 13 +with rel_bixu13_wayB_upd select + congr_cl13_wB_d(1) <= (congr_cl13_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayB_upd select + congr_cl13_wB_d(2) <= (congr_cl13_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayB_upd select + congr_cl13_wB_d(3) <= (congr_cl13_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayB_upd select + congr_cl13_wB_d(4) <= (congr_cl13_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayB_upd select + congr_cl13_wB_d(5) <= (congr_cl13_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 14 +with rel_bixu14_wayB_upd select + congr_cl14_wB_d(0) <= (congr_cl14_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 14 +with rel_bixu14_wayB_upd select + congr_cl14_wB_d(1) <= (congr_cl14_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayB_upd select + congr_cl14_wB_d(2) <= (congr_cl14_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayB_upd select + congr_cl14_wB_d(3) <= (congr_cl14_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayB_upd select + congr_cl14_wB_d(4) <= (congr_cl14_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayB_upd select + congr_cl14_wB_d(5) <= (congr_cl14_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 15 +with rel_bixu15_wayB_upd select + congr_cl15_wB_d(0) <= (congr_cl15_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 15 +with rel_bixu15_wayB_upd select + congr_cl15_wB_d(1) <= (congr_cl15_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayB_upd select + congr_cl15_wB_d(2) <= (congr_cl15_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayB_upd select + congr_cl15_wB_d(3) <= (congr_cl15_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayB_upd select + congr_cl15_wB_d(4) <= (congr_cl15_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayB_upd select + congr_cl15_wB_d(5) <= (congr_cl15_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 16 +with rel_bixu16_wayB_upd select + congr_cl16_wB_d(0) <= (congr_cl16_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 16 +with rel_bixu16_wayB_upd select + congr_cl16_wB_d(1) <= (congr_cl16_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayB_upd select + congr_cl16_wB_d(2) <= (congr_cl16_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayB_upd select + congr_cl16_wB_d(3) <= (congr_cl16_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayB_upd select + congr_cl16_wB_d(4) <= (congr_cl16_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayB_upd select + congr_cl16_wB_d(5) <= (congr_cl16_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 17 +with rel_bixu17_wayB_upd select + congr_cl17_wB_d(0) <= (congr_cl17_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 17 +with rel_bixu17_wayB_upd select + congr_cl17_wB_d(1) <= (congr_cl17_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayB_upd select + congr_cl17_wB_d(2) <= (congr_cl17_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayB_upd select + congr_cl17_wB_d(3) <= (congr_cl17_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayB_upd select + congr_cl17_wB_d(4) <= (congr_cl17_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayB_upd select + congr_cl17_wB_d(5) <= (congr_cl17_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 18 +with rel_bixu18_wayB_upd select + congr_cl18_wB_d(0) <= (congr_cl18_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 18 +with rel_bixu18_wayB_upd select + congr_cl18_wB_d(1) <= (congr_cl18_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayB_upd select + congr_cl18_wB_d(2) <= (congr_cl18_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayB_upd select + congr_cl18_wB_d(3) <= (congr_cl18_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayB_upd select + congr_cl18_wB_d(4) <= (congr_cl18_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayB_upd select + congr_cl18_wB_d(5) <= (congr_cl18_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 19 +with rel_bixu19_wayB_upd select + congr_cl19_wB_d(0) <= (congr_cl19_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 19 +with rel_bixu19_wayB_upd select + congr_cl19_wB_d(1) <= (congr_cl19_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayB_upd select + congr_cl19_wB_d(2) <= (congr_cl19_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayB_upd select + congr_cl19_wB_d(3) <= (congr_cl19_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayB_upd select + congr_cl19_wB_d(4) <= (congr_cl19_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayB_upd select + congr_cl19_wB_d(5) <= (congr_cl19_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 20 +with rel_bixu20_wayB_upd select + congr_cl20_wB_d(0) <= (congr_cl20_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 20 +with rel_bixu20_wayB_upd select + congr_cl20_wB_d(1) <= (congr_cl20_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayB_upd select + congr_cl20_wB_d(2) <= (congr_cl20_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayB_upd select + congr_cl20_wB_d(3) <= (congr_cl20_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayB_upd select + congr_cl20_wB_d(4) <= (congr_cl20_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayB_upd select + congr_cl20_wB_d(5) <= (congr_cl20_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 21 +with rel_bixu21_wayB_upd select + congr_cl21_wB_d(0) <= (congr_cl21_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 21 +with rel_bixu21_wayB_upd select + congr_cl21_wB_d(1) <= (congr_cl21_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayB_upd select + congr_cl21_wB_d(2) <= (congr_cl21_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayB_upd select + congr_cl21_wB_d(3) <= (congr_cl21_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayB_upd select + congr_cl21_wB_d(4) <= (congr_cl21_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayB_upd select + congr_cl21_wB_d(5) <= (congr_cl21_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 22 +with rel_bixu22_wayB_upd select + congr_cl22_wB_d(0) <= (congr_cl22_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 22 +with rel_bixu22_wayB_upd select + congr_cl22_wB_d(1) <= (congr_cl22_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayB_upd select + congr_cl22_wB_d(2) <= (congr_cl22_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayB_upd select + congr_cl22_wB_d(3) <= (congr_cl22_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayB_upd select + congr_cl22_wB_d(4) <= (congr_cl22_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayB_upd select + congr_cl22_wB_d(5) <= (congr_cl22_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 23 +with rel_bixu23_wayB_upd select + congr_cl23_wB_d(0) <= (congr_cl23_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 23 +with rel_bixu23_wayB_upd select + congr_cl23_wB_d(1) <= (congr_cl23_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayB_upd select + congr_cl23_wB_d(2) <= (congr_cl23_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayB_upd select + congr_cl23_wB_d(3) <= (congr_cl23_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayB_upd select + congr_cl23_wB_d(4) <= (congr_cl23_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayB_upd select + congr_cl23_wB_d(5) <= (congr_cl23_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 24 +with rel_bixu24_wayB_upd select + congr_cl24_wB_d(0) <= (congr_cl24_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 24 +with rel_bixu24_wayB_upd select + congr_cl24_wB_d(1) <= (congr_cl24_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayB_upd select + congr_cl24_wB_d(2) <= (congr_cl24_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayB_upd select + congr_cl24_wB_d(3) <= (congr_cl24_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayB_upd select + congr_cl24_wB_d(4) <= (congr_cl24_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayB_upd select + congr_cl24_wB_d(5) <= (congr_cl24_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 25 +with rel_bixu25_wayB_upd select + congr_cl25_wB_d(0) <= (congr_cl25_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 25 +with rel_bixu25_wayB_upd select + congr_cl25_wB_d(1) <= (congr_cl25_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayB_upd select + congr_cl25_wB_d(2) <= (congr_cl25_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayB_upd select + congr_cl25_wB_d(3) <= (congr_cl25_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayB_upd select + congr_cl25_wB_d(4) <= (congr_cl25_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayB_upd select + congr_cl25_wB_d(5) <= (congr_cl25_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 26 +with rel_bixu26_wayB_upd select + congr_cl26_wB_d(0) <= (congr_cl26_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 26 +with rel_bixu26_wayB_upd select + congr_cl26_wB_d(1) <= (congr_cl26_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayB_upd select + congr_cl26_wB_d(2) <= (congr_cl26_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayB_upd select + congr_cl26_wB_d(3) <= (congr_cl26_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayB_upd select + congr_cl26_wB_d(4) <= (congr_cl26_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayB_upd select + congr_cl26_wB_d(5) <= (congr_cl26_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 27 +with rel_bixu27_wayB_upd select + congr_cl27_wB_d(0) <= (congr_cl27_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 27 +with rel_bixu27_wayB_upd select + congr_cl27_wB_d(1) <= (congr_cl27_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayB_upd select + congr_cl27_wB_d(2) <= (congr_cl27_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayB_upd select + congr_cl27_wB_d(3) <= (congr_cl27_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayB_upd select + congr_cl27_wB_d(4) <= (congr_cl27_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayB_upd select + congr_cl27_wB_d(5) <= (congr_cl27_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 28 +with rel_bixu28_wayB_upd select + congr_cl28_wB_d(0) <= (congr_cl28_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 28 +with rel_bixu28_wayB_upd select + congr_cl28_wB_d(1) <= (congr_cl28_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayB_upd select + congr_cl28_wB_d(2) <= (congr_cl28_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayB_upd select + congr_cl28_wB_d(3) <= (congr_cl28_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayB_upd select + congr_cl28_wB_d(4) <= (congr_cl28_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayB_upd select + congr_cl28_wB_d(5) <= (congr_cl28_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 29 +with rel_bixu29_wayB_upd select + congr_cl29_wB_d(0) <= (congr_cl29_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 29 +with rel_bixu29_wayB_upd select + congr_cl29_wB_d(1) <= (congr_cl29_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayB_upd select + congr_cl29_wB_d(2) <= (congr_cl29_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayB_upd select + congr_cl29_wB_d(3) <= (congr_cl29_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayB_upd select + congr_cl29_wB_d(4) <= (congr_cl29_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayB_upd select + congr_cl29_wB_d(5) <= (congr_cl29_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 30 +with rel_bixu30_wayB_upd select + congr_cl30_wB_d(0) <= (congr_cl30_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 30 +with rel_bixu30_wayB_upd select + congr_cl30_wB_d(1) <= (congr_cl30_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayB_upd select + congr_cl30_wB_d(2) <= (congr_cl30_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayB_upd select + congr_cl30_wB_d(3) <= (congr_cl30_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayB_upd select + congr_cl30_wB_d(4) <= (congr_cl30_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayB_upd select + congr_cl30_wB_d(5) <= (congr_cl30_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 31 +with rel_bixu31_wayB_upd select + congr_cl31_wB_d(0) <= (congr_cl31_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 31 +with rel_bixu31_wayB_upd select + congr_cl31_wB_d(1) <= (congr_cl31_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayB_upd select + congr_cl31_wB_d(2) <= (congr_cl31_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayB_upd select + congr_cl31_wB_d(3) <= (congr_cl31_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayB_upd select + congr_cl31_wB_d(4) <= (congr_cl31_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayB_upd select + congr_cl31_wB_d(5) <= (congr_cl31_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Write Select for WayC +-- WayC Valid Bit Update for Congruence Class 0 +with rel_bixu0_wayC_upd select + congr_cl0_wC_d(0) <= (congr_cl0_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 0 +with rel_bixu0_wayC_upd select + congr_cl0_wC_d(1) <= (congr_cl0_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayC_upd select + congr_cl0_wC_d(2) <= (congr_cl0_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayC_upd select + congr_cl0_wC_d(3) <= (congr_cl0_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayC_upd select + congr_cl0_wC_d(4) <= (congr_cl0_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayC_upd select + congr_cl0_wC_d(5) <= (congr_cl0_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 1 +with rel_bixu1_wayC_upd select + congr_cl1_wC_d(0) <= (congr_cl1_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 1 +with rel_bixu1_wayC_upd select + congr_cl1_wC_d(1) <= (congr_cl1_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayC_upd select + congr_cl1_wC_d(2) <= (congr_cl1_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayC_upd select + congr_cl1_wC_d(3) <= (congr_cl1_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayC_upd select + congr_cl1_wC_d(4) <= (congr_cl1_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayC_upd select + congr_cl1_wC_d(5) <= (congr_cl1_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 2 +with rel_bixu2_wayC_upd select + congr_cl2_wC_d(0) <= (congr_cl2_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 2 +with rel_bixu2_wayC_upd select + congr_cl2_wC_d(1) <= (congr_cl2_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayC_upd select + congr_cl2_wC_d(2) <= (congr_cl2_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayC_upd select + congr_cl2_wC_d(3) <= (congr_cl2_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayC_upd select + congr_cl2_wC_d(4) <= (congr_cl2_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayC_upd select + congr_cl2_wC_d(5) <= (congr_cl2_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 3 +with rel_bixu3_wayC_upd select + congr_cl3_wC_d(0) <= (congr_cl3_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 3 +with rel_bixu3_wayC_upd select + congr_cl3_wC_d(1) <= (congr_cl3_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayC_upd select + congr_cl3_wC_d(2) <= (congr_cl3_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayC_upd select + congr_cl3_wC_d(3) <= (congr_cl3_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayC_upd select + congr_cl3_wC_d(4) <= (congr_cl3_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayC_upd select + congr_cl3_wC_d(5) <= (congr_cl3_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 4 +with rel_bixu4_wayC_upd select + congr_cl4_wC_d(0) <= (congr_cl4_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 4 +with rel_bixu4_wayC_upd select + congr_cl4_wC_d(1) <= (congr_cl4_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayC_upd select + congr_cl4_wC_d(2) <= (congr_cl4_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayC_upd select + congr_cl4_wC_d(3) <= (congr_cl4_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayC_upd select + congr_cl4_wC_d(4) <= (congr_cl4_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayC_upd select + congr_cl4_wC_d(5) <= (congr_cl4_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 5 +with rel_bixu5_wayC_upd select + congr_cl5_wC_d(0) <= (congr_cl5_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 5 +with rel_bixu5_wayC_upd select + congr_cl5_wC_d(1) <= (congr_cl5_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayC_upd select + congr_cl5_wC_d(2) <= (congr_cl5_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayC_upd select + congr_cl5_wC_d(3) <= (congr_cl5_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayC_upd select + congr_cl5_wC_d(4) <= (congr_cl5_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayC_upd select + congr_cl5_wC_d(5) <= (congr_cl5_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 6 +with rel_bixu6_wayC_upd select + congr_cl6_wC_d(0) <= (congr_cl6_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 6 +with rel_bixu6_wayC_upd select + congr_cl6_wC_d(1) <= (congr_cl6_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayC_upd select + congr_cl6_wC_d(2) <= (congr_cl6_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayC_upd select + congr_cl6_wC_d(3) <= (congr_cl6_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayC_upd select + congr_cl6_wC_d(4) <= (congr_cl6_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayC_upd select + congr_cl6_wC_d(5) <= (congr_cl6_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 7 +with rel_bixu7_wayC_upd select + congr_cl7_wC_d(0) <= (congr_cl7_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 7 +with rel_bixu7_wayC_upd select + congr_cl7_wC_d(1) <= (congr_cl7_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayC_upd select + congr_cl7_wC_d(2) <= (congr_cl7_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayC_upd select + congr_cl7_wC_d(3) <= (congr_cl7_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayC_upd select + congr_cl7_wC_d(4) <= (congr_cl7_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayC_upd select + congr_cl7_wC_d(5) <= (congr_cl7_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 8 +with rel_bixu8_wayC_upd select + congr_cl8_wC_d(0) <= (congr_cl8_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 8 +with rel_bixu8_wayC_upd select + congr_cl8_wC_d(1) <= (congr_cl8_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayC_upd select + congr_cl8_wC_d(2) <= (congr_cl8_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayC_upd select + congr_cl8_wC_d(3) <= (congr_cl8_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayC_upd select + congr_cl8_wC_d(4) <= (congr_cl8_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayC_upd select + congr_cl8_wC_d(5) <= (congr_cl8_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 9 +with rel_bixu9_wayC_upd select + congr_cl9_wC_d(0) <= (congr_cl9_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 9 +with rel_bixu9_wayC_upd select + congr_cl9_wC_d(1) <= (congr_cl9_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayC_upd select + congr_cl9_wC_d(2) <= (congr_cl9_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayC_upd select + congr_cl9_wC_d(3) <= (congr_cl9_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayC_upd select + congr_cl9_wC_d(4) <= (congr_cl9_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayC_upd select + congr_cl9_wC_d(5) <= (congr_cl9_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 10 +with rel_bixu10_wayC_upd select + congr_cl10_wC_d(0) <= (congr_cl10_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 10 +with rel_bixu10_wayC_upd select + congr_cl10_wC_d(1) <= (congr_cl10_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayC_upd select + congr_cl10_wC_d(2) <= (congr_cl10_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayC_upd select + congr_cl10_wC_d(3) <= (congr_cl10_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayC_upd select + congr_cl10_wC_d(4) <= (congr_cl10_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayC_upd select + congr_cl10_wC_d(5) <= (congr_cl10_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 11 +with rel_bixu11_wayC_upd select + congr_cl11_wC_d(0) <= (congr_cl11_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 11 +with rel_bixu11_wayC_upd select + congr_cl11_wC_d(1) <= (congr_cl11_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayC_upd select + congr_cl11_wC_d(2) <= (congr_cl11_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayC_upd select + congr_cl11_wC_d(3) <= (congr_cl11_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayC_upd select + congr_cl11_wC_d(4) <= (congr_cl11_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayC_upd select + congr_cl11_wC_d(5) <= (congr_cl11_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 12 +with rel_bixu12_wayC_upd select + congr_cl12_wC_d(0) <= (congr_cl12_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 12 +with rel_bixu12_wayC_upd select + congr_cl12_wC_d(1) <= (congr_cl12_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayC_upd select + congr_cl12_wC_d(2) <= (congr_cl12_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayC_upd select + congr_cl12_wC_d(3) <= (congr_cl12_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayC_upd select + congr_cl12_wC_d(4) <= (congr_cl12_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayC_upd select + congr_cl12_wC_d(5) <= (congr_cl12_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 13 +with rel_bixu13_wayC_upd select + congr_cl13_wC_d(0) <= (congr_cl13_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 13 +with rel_bixu13_wayC_upd select + congr_cl13_wC_d(1) <= (congr_cl13_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayC_upd select + congr_cl13_wC_d(2) <= (congr_cl13_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayC_upd select + congr_cl13_wC_d(3) <= (congr_cl13_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayC_upd select + congr_cl13_wC_d(4) <= (congr_cl13_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayC_upd select + congr_cl13_wC_d(5) <= (congr_cl13_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 14 +with rel_bixu14_wayC_upd select + congr_cl14_wC_d(0) <= (congr_cl14_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 14 +with rel_bixu14_wayC_upd select + congr_cl14_wC_d(1) <= (congr_cl14_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayC_upd select + congr_cl14_wC_d(2) <= (congr_cl14_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayC_upd select + congr_cl14_wC_d(3) <= (congr_cl14_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayC_upd select + congr_cl14_wC_d(4) <= (congr_cl14_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayC_upd select + congr_cl14_wC_d(5) <= (congr_cl14_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 15 +with rel_bixu15_wayC_upd select + congr_cl15_wC_d(0) <= (congr_cl15_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 15 +with rel_bixu15_wayC_upd select + congr_cl15_wC_d(1) <= (congr_cl15_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayC_upd select + congr_cl15_wC_d(2) <= (congr_cl15_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayC_upd select + congr_cl15_wC_d(3) <= (congr_cl15_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayC_upd select + congr_cl15_wC_d(4) <= (congr_cl15_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayC_upd select + congr_cl15_wC_d(5) <= (congr_cl15_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 16 +with rel_bixu16_wayC_upd select + congr_cl16_wC_d(0) <= (congr_cl16_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 16 +with rel_bixu16_wayC_upd select + congr_cl16_wC_d(1) <= (congr_cl16_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayC_upd select + congr_cl16_wC_d(2) <= (congr_cl16_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayC_upd select + congr_cl16_wC_d(3) <= (congr_cl16_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayC_upd select + congr_cl16_wC_d(4) <= (congr_cl16_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayC_upd select + congr_cl16_wC_d(5) <= (congr_cl16_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 17 +with rel_bixu17_wayC_upd select + congr_cl17_wC_d(0) <= (congr_cl17_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 17 +with rel_bixu17_wayC_upd select + congr_cl17_wC_d(1) <= (congr_cl17_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayC_upd select + congr_cl17_wC_d(2) <= (congr_cl17_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayC_upd select + congr_cl17_wC_d(3) <= (congr_cl17_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayC_upd select + congr_cl17_wC_d(4) <= (congr_cl17_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayC_upd select + congr_cl17_wC_d(5) <= (congr_cl17_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 18 +with rel_bixu18_wayC_upd select + congr_cl18_wC_d(0) <= (congr_cl18_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 18 +with rel_bixu18_wayC_upd select + congr_cl18_wC_d(1) <= (congr_cl18_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayC_upd select + congr_cl18_wC_d(2) <= (congr_cl18_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayC_upd select + congr_cl18_wC_d(3) <= (congr_cl18_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayC_upd select + congr_cl18_wC_d(4) <= (congr_cl18_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayC_upd select + congr_cl18_wC_d(5) <= (congr_cl18_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 19 +with rel_bixu19_wayC_upd select + congr_cl19_wC_d(0) <= (congr_cl19_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 19 +with rel_bixu19_wayC_upd select + congr_cl19_wC_d(1) <= (congr_cl19_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayC_upd select + congr_cl19_wC_d(2) <= (congr_cl19_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayC_upd select + congr_cl19_wC_d(3) <= (congr_cl19_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayC_upd select + congr_cl19_wC_d(4) <= (congr_cl19_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayC_upd select + congr_cl19_wC_d(5) <= (congr_cl19_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 20 +with rel_bixu20_wayC_upd select + congr_cl20_wC_d(0) <= (congr_cl20_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 20 +with rel_bixu20_wayC_upd select + congr_cl20_wC_d(1) <= (congr_cl20_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayC_upd select + congr_cl20_wC_d(2) <= (congr_cl20_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayC_upd select + congr_cl20_wC_d(3) <= (congr_cl20_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayC_upd select + congr_cl20_wC_d(4) <= (congr_cl20_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayC_upd select + congr_cl20_wC_d(5) <= (congr_cl20_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 21 +with rel_bixu21_wayC_upd select + congr_cl21_wC_d(0) <= (congr_cl21_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 21 +with rel_bixu21_wayC_upd select + congr_cl21_wC_d(1) <= (congr_cl21_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayC_upd select + congr_cl21_wC_d(2) <= (congr_cl21_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayC_upd select + congr_cl21_wC_d(3) <= (congr_cl21_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayC_upd select + congr_cl21_wC_d(4) <= (congr_cl21_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayC_upd select + congr_cl21_wC_d(5) <= (congr_cl21_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 22 +with rel_bixu22_wayC_upd select + congr_cl22_wC_d(0) <= (congr_cl22_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 22 +with rel_bixu22_wayC_upd select + congr_cl22_wC_d(1) <= (congr_cl22_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayC_upd select + congr_cl22_wC_d(2) <= (congr_cl22_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayC_upd select + congr_cl22_wC_d(3) <= (congr_cl22_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayC_upd select + congr_cl22_wC_d(4) <= (congr_cl22_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayC_upd select + congr_cl22_wC_d(5) <= (congr_cl22_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 23 +with rel_bixu23_wayC_upd select + congr_cl23_wC_d(0) <= (congr_cl23_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 23 +with rel_bixu23_wayC_upd select + congr_cl23_wC_d(1) <= (congr_cl23_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayC_upd select + congr_cl23_wC_d(2) <= (congr_cl23_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayC_upd select + congr_cl23_wC_d(3) <= (congr_cl23_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayC_upd select + congr_cl23_wC_d(4) <= (congr_cl23_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayC_upd select + congr_cl23_wC_d(5) <= (congr_cl23_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 24 +with rel_bixu24_wayC_upd select + congr_cl24_wC_d(0) <= (congr_cl24_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 24 +with rel_bixu24_wayC_upd select + congr_cl24_wC_d(1) <= (congr_cl24_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayC_upd select + congr_cl24_wC_d(2) <= (congr_cl24_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayC_upd select + congr_cl24_wC_d(3) <= (congr_cl24_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayC_upd select + congr_cl24_wC_d(4) <= (congr_cl24_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayC_upd select + congr_cl24_wC_d(5) <= (congr_cl24_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 25 +with rel_bixu25_wayC_upd select + congr_cl25_wC_d(0) <= (congr_cl25_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 25 +with rel_bixu25_wayC_upd select + congr_cl25_wC_d(1) <= (congr_cl25_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayC_upd select + congr_cl25_wC_d(2) <= (congr_cl25_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayC_upd select + congr_cl25_wC_d(3) <= (congr_cl25_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayC_upd select + congr_cl25_wC_d(4) <= (congr_cl25_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayC_upd select + congr_cl25_wC_d(5) <= (congr_cl25_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 26 +with rel_bixu26_wayC_upd select + congr_cl26_wC_d(0) <= (congr_cl26_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 26 +with rel_bixu26_wayC_upd select + congr_cl26_wC_d(1) <= (congr_cl26_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayC_upd select + congr_cl26_wC_d(2) <= (congr_cl26_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayC_upd select + congr_cl26_wC_d(3) <= (congr_cl26_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayC_upd select + congr_cl26_wC_d(4) <= (congr_cl26_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayC_upd select + congr_cl26_wC_d(5) <= (congr_cl26_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 27 +with rel_bixu27_wayC_upd select + congr_cl27_wC_d(0) <= (congr_cl27_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 27 +with rel_bixu27_wayC_upd select + congr_cl27_wC_d(1) <= (congr_cl27_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayC_upd select + congr_cl27_wC_d(2) <= (congr_cl27_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayC_upd select + congr_cl27_wC_d(3) <= (congr_cl27_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayC_upd select + congr_cl27_wC_d(4) <= (congr_cl27_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayC_upd select + congr_cl27_wC_d(5) <= (congr_cl27_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 28 +with rel_bixu28_wayC_upd select + congr_cl28_wC_d(0) <= (congr_cl28_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 28 +with rel_bixu28_wayC_upd select + congr_cl28_wC_d(1) <= (congr_cl28_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayC_upd select + congr_cl28_wC_d(2) <= (congr_cl28_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayC_upd select + congr_cl28_wC_d(3) <= (congr_cl28_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayC_upd select + congr_cl28_wC_d(4) <= (congr_cl28_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayC_upd select + congr_cl28_wC_d(5) <= (congr_cl28_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 29 +with rel_bixu29_wayC_upd select + congr_cl29_wC_d(0) <= (congr_cl29_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 29 +with rel_bixu29_wayC_upd select + congr_cl29_wC_d(1) <= (congr_cl29_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayC_upd select + congr_cl29_wC_d(2) <= (congr_cl29_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayC_upd select + congr_cl29_wC_d(3) <= (congr_cl29_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayC_upd select + congr_cl29_wC_d(4) <= (congr_cl29_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayC_upd select + congr_cl29_wC_d(5) <= (congr_cl29_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 30 +with rel_bixu30_wayC_upd select + congr_cl30_wC_d(0) <= (congr_cl30_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 30 +with rel_bixu30_wayC_upd select + congr_cl30_wC_d(1) <= (congr_cl30_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayC_upd select + congr_cl30_wC_d(2) <= (congr_cl30_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayC_upd select + congr_cl30_wC_d(3) <= (congr_cl30_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayC_upd select + congr_cl30_wC_d(4) <= (congr_cl30_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayC_upd select + congr_cl30_wC_d(5) <= (congr_cl30_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 31 +with rel_bixu31_wayC_upd select + congr_cl31_wC_d(0) <= (congr_cl31_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 31 +with rel_bixu31_wayC_upd select + congr_cl31_wC_d(1) <= (congr_cl31_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayC_upd select + congr_cl31_wC_d(2) <= (congr_cl31_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayC_upd select + congr_cl31_wC_d(3) <= (congr_cl31_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayC_upd select + congr_cl31_wC_d(4) <= (congr_cl31_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayC_upd select + congr_cl31_wC_d(5) <= (congr_cl31_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Write Select for WayD +-- WayD Valid Bit Update for Congruence Class 0 +with rel_bixu0_wayD_upd select + congr_cl0_wD_d(0) <= (congr_cl0_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 0 +with rel_bixu0_wayD_upd select + congr_cl0_wD_d(1) <= (congr_cl0_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayD_upd select + congr_cl0_wD_d(2) <= (congr_cl0_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayD_upd select + congr_cl0_wD_d(3) <= (congr_cl0_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayD_upd select + congr_cl0_wD_d(4) <= (congr_cl0_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayD_upd select + congr_cl0_wD_d(5) <= (congr_cl0_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 1 +with rel_bixu1_wayD_upd select + congr_cl1_wD_d(0) <= (congr_cl1_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 1 +with rel_bixu1_wayD_upd select + congr_cl1_wD_d(1) <= (congr_cl1_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayD_upd select + congr_cl1_wD_d(2) <= (congr_cl1_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayD_upd select + congr_cl1_wD_d(3) <= (congr_cl1_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayD_upd select + congr_cl1_wD_d(4) <= (congr_cl1_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayD_upd select + congr_cl1_wD_d(5) <= (congr_cl1_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 2 +with rel_bixu2_wayD_upd select + congr_cl2_wD_d(0) <= (congr_cl2_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 2 +with rel_bixu2_wayD_upd select + congr_cl2_wD_d(1) <= (congr_cl2_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayD_upd select + congr_cl2_wD_d(2) <= (congr_cl2_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayD_upd select + congr_cl2_wD_d(3) <= (congr_cl2_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayD_upd select + congr_cl2_wD_d(4) <= (congr_cl2_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayD_upd select + congr_cl2_wD_d(5) <= (congr_cl2_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 3 +with rel_bixu3_wayD_upd select + congr_cl3_wD_d(0) <= (congr_cl3_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 3 +with rel_bixu3_wayD_upd select + congr_cl3_wD_d(1) <= (congr_cl3_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayD_upd select + congr_cl3_wD_d(2) <= (congr_cl3_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayD_upd select + congr_cl3_wD_d(3) <= (congr_cl3_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayD_upd select + congr_cl3_wD_d(4) <= (congr_cl3_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayD_upd select + congr_cl3_wD_d(5) <= (congr_cl3_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 4 +with rel_bixu4_wayD_upd select + congr_cl4_wD_d(0) <= (congr_cl4_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 4 +with rel_bixu4_wayD_upd select + congr_cl4_wD_d(1) <= (congr_cl4_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayD_upd select + congr_cl4_wD_d(2) <= (congr_cl4_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayD_upd select + congr_cl4_wD_d(3) <= (congr_cl4_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayD_upd select + congr_cl4_wD_d(4) <= (congr_cl4_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayD_upd select + congr_cl4_wD_d(5) <= (congr_cl4_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 5 +with rel_bixu5_wayD_upd select + congr_cl5_wD_d(0) <= (congr_cl5_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 5 +with rel_bixu5_wayD_upd select + congr_cl5_wD_d(1) <= (congr_cl5_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayD_upd select + congr_cl5_wD_d(2) <= (congr_cl5_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayD_upd select + congr_cl5_wD_d(3) <= (congr_cl5_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayD_upd select + congr_cl5_wD_d(4) <= (congr_cl5_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayD_upd select + congr_cl5_wD_d(5) <= (congr_cl5_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 6 +with rel_bixu6_wayD_upd select + congr_cl6_wD_d(0) <= (congr_cl6_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 6 +with rel_bixu6_wayD_upd select + congr_cl6_wD_d(1) <= (congr_cl6_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayD_upd select + congr_cl6_wD_d(2) <= (congr_cl6_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayD_upd select + congr_cl6_wD_d(3) <= (congr_cl6_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayD_upd select + congr_cl6_wD_d(4) <= (congr_cl6_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayD_upd select + congr_cl6_wD_d(5) <= (congr_cl6_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 7 +with rel_bixu7_wayD_upd select + congr_cl7_wD_d(0) <= (congr_cl7_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 7 +with rel_bixu7_wayD_upd select + congr_cl7_wD_d(1) <= (congr_cl7_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayD_upd select + congr_cl7_wD_d(2) <= (congr_cl7_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayD_upd select + congr_cl7_wD_d(3) <= (congr_cl7_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayD_upd select + congr_cl7_wD_d(4) <= (congr_cl7_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayD_upd select + congr_cl7_wD_d(5) <= (congr_cl7_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 8 +with rel_bixu8_wayD_upd select + congr_cl8_wD_d(0) <= (congr_cl8_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 8 +with rel_bixu8_wayD_upd select + congr_cl8_wD_d(1) <= (congr_cl8_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayD_upd select + congr_cl8_wD_d(2) <= (congr_cl8_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayD_upd select + congr_cl8_wD_d(3) <= (congr_cl8_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayD_upd select + congr_cl8_wD_d(4) <= (congr_cl8_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayD_upd select + congr_cl8_wD_d(5) <= (congr_cl8_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 9 +with rel_bixu9_wayD_upd select + congr_cl9_wD_d(0) <= (congr_cl9_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 9 +with rel_bixu9_wayD_upd select + congr_cl9_wD_d(1) <= (congr_cl9_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayD_upd select + congr_cl9_wD_d(2) <= (congr_cl9_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayD_upd select + congr_cl9_wD_d(3) <= (congr_cl9_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayD_upd select + congr_cl9_wD_d(4) <= (congr_cl9_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayD_upd select + congr_cl9_wD_d(5) <= (congr_cl9_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 10 +with rel_bixu10_wayD_upd select + congr_cl10_wD_d(0) <= (congr_cl10_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 10 +with rel_bixu10_wayD_upd select + congr_cl10_wD_d(1) <= (congr_cl10_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayD_upd select + congr_cl10_wD_d(2) <= (congr_cl10_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayD_upd select + congr_cl10_wD_d(3) <= (congr_cl10_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayD_upd select + congr_cl10_wD_d(4) <= (congr_cl10_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayD_upd select + congr_cl10_wD_d(5) <= (congr_cl10_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 11 +with rel_bixu11_wayD_upd select + congr_cl11_wD_d(0) <= (congr_cl11_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 11 +with rel_bixu11_wayD_upd select + congr_cl11_wD_d(1) <= (congr_cl11_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayD_upd select + congr_cl11_wD_d(2) <= (congr_cl11_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayD_upd select + congr_cl11_wD_d(3) <= (congr_cl11_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayD_upd select + congr_cl11_wD_d(4) <= (congr_cl11_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayD_upd select + congr_cl11_wD_d(5) <= (congr_cl11_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 12 +with rel_bixu12_wayD_upd select + congr_cl12_wD_d(0) <= (congr_cl12_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 12 +with rel_bixu12_wayD_upd select + congr_cl12_wD_d(1) <= (congr_cl12_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayD_upd select + congr_cl12_wD_d(2) <= (congr_cl12_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayD_upd select + congr_cl12_wD_d(3) <= (congr_cl12_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayD_upd select + congr_cl12_wD_d(4) <= (congr_cl12_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayD_upd select + congr_cl12_wD_d(5) <= (congr_cl12_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 13 +with rel_bixu13_wayD_upd select + congr_cl13_wD_d(0) <= (congr_cl13_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 13 +with rel_bixu13_wayD_upd select + congr_cl13_wD_d(1) <= (congr_cl13_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayD_upd select + congr_cl13_wD_d(2) <= (congr_cl13_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayD_upd select + congr_cl13_wD_d(3) <= (congr_cl13_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayD_upd select + congr_cl13_wD_d(4) <= (congr_cl13_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayD_upd select + congr_cl13_wD_d(5) <= (congr_cl13_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 14 +with rel_bixu14_wayD_upd select + congr_cl14_wD_d(0) <= (congr_cl14_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 14 +with rel_bixu14_wayD_upd select + congr_cl14_wD_d(1) <= (congr_cl14_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayD_upd select + congr_cl14_wD_d(2) <= (congr_cl14_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayD_upd select + congr_cl14_wD_d(3) <= (congr_cl14_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayD_upd select + congr_cl14_wD_d(4) <= (congr_cl14_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayD_upd select + congr_cl14_wD_d(5) <= (congr_cl14_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 15 +with rel_bixu15_wayD_upd select + congr_cl15_wD_d(0) <= (congr_cl15_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 15 +with rel_bixu15_wayD_upd select + congr_cl15_wD_d(1) <= (congr_cl15_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayD_upd select + congr_cl15_wD_d(2) <= (congr_cl15_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayD_upd select + congr_cl15_wD_d(3) <= (congr_cl15_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayD_upd select + congr_cl15_wD_d(4) <= (congr_cl15_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayD_upd select + congr_cl15_wD_d(5) <= (congr_cl15_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 16 +with rel_bixu16_wayD_upd select + congr_cl16_wD_d(0) <= (congr_cl16_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 16 +with rel_bixu16_wayD_upd select + congr_cl16_wD_d(1) <= (congr_cl16_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayD_upd select + congr_cl16_wD_d(2) <= (congr_cl16_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayD_upd select + congr_cl16_wD_d(3) <= (congr_cl16_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayD_upd select + congr_cl16_wD_d(4) <= (congr_cl16_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayD_upd select + congr_cl16_wD_d(5) <= (congr_cl16_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 17 +with rel_bixu17_wayD_upd select + congr_cl17_wD_d(0) <= (congr_cl17_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 17 +with rel_bixu17_wayD_upd select + congr_cl17_wD_d(1) <= (congr_cl17_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayD_upd select + congr_cl17_wD_d(2) <= (congr_cl17_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayD_upd select + congr_cl17_wD_d(3) <= (congr_cl17_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayD_upd select + congr_cl17_wD_d(4) <= (congr_cl17_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayD_upd select + congr_cl17_wD_d(5) <= (congr_cl17_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 18 +with rel_bixu18_wayD_upd select + congr_cl18_wD_d(0) <= (congr_cl18_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 18 +with rel_bixu18_wayD_upd select + congr_cl18_wD_d(1) <= (congr_cl18_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayD_upd select + congr_cl18_wD_d(2) <= (congr_cl18_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayD_upd select + congr_cl18_wD_d(3) <= (congr_cl18_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayD_upd select + congr_cl18_wD_d(4) <= (congr_cl18_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayD_upd select + congr_cl18_wD_d(5) <= (congr_cl18_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 19 +with rel_bixu19_wayD_upd select + congr_cl19_wD_d(0) <= (congr_cl19_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 19 +with rel_bixu19_wayD_upd select + congr_cl19_wD_d(1) <= (congr_cl19_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayD_upd select + congr_cl19_wD_d(2) <= (congr_cl19_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayD_upd select + congr_cl19_wD_d(3) <= (congr_cl19_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayD_upd select + congr_cl19_wD_d(4) <= (congr_cl19_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayD_upd select + congr_cl19_wD_d(5) <= (congr_cl19_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 20 +with rel_bixu20_wayD_upd select + congr_cl20_wD_d(0) <= (congr_cl20_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 20 +with rel_bixu20_wayD_upd select + congr_cl20_wD_d(1) <= (congr_cl20_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayD_upd select + congr_cl20_wD_d(2) <= (congr_cl20_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayD_upd select + congr_cl20_wD_d(3) <= (congr_cl20_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayD_upd select + congr_cl20_wD_d(4) <= (congr_cl20_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayD_upd select + congr_cl20_wD_d(5) <= (congr_cl20_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 21 +with rel_bixu21_wayD_upd select + congr_cl21_wD_d(0) <= (congr_cl21_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 21 +with rel_bixu21_wayD_upd select + congr_cl21_wD_d(1) <= (congr_cl21_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayD_upd select + congr_cl21_wD_d(2) <= (congr_cl21_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayD_upd select + congr_cl21_wD_d(3) <= (congr_cl21_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayD_upd select + congr_cl21_wD_d(4) <= (congr_cl21_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayD_upd select + congr_cl21_wD_d(5) <= (congr_cl21_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 22 +with rel_bixu22_wayD_upd select + congr_cl22_wD_d(0) <= (congr_cl22_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 22 +with rel_bixu22_wayD_upd select + congr_cl22_wD_d(1) <= (congr_cl22_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayD_upd select + congr_cl22_wD_d(2) <= (congr_cl22_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayD_upd select + congr_cl22_wD_d(3) <= (congr_cl22_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayD_upd select + congr_cl22_wD_d(4) <= (congr_cl22_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayD_upd select + congr_cl22_wD_d(5) <= (congr_cl22_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 23 +with rel_bixu23_wayD_upd select + congr_cl23_wD_d(0) <= (congr_cl23_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 23 +with rel_bixu23_wayD_upd select + congr_cl23_wD_d(1) <= (congr_cl23_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayD_upd select + congr_cl23_wD_d(2) <= (congr_cl23_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayD_upd select + congr_cl23_wD_d(3) <= (congr_cl23_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayD_upd select + congr_cl23_wD_d(4) <= (congr_cl23_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayD_upd select + congr_cl23_wD_d(5) <= (congr_cl23_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 24 +with rel_bixu24_wayD_upd select + congr_cl24_wD_d(0) <= (congr_cl24_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 24 +with rel_bixu24_wayD_upd select + congr_cl24_wD_d(1) <= (congr_cl24_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayD_upd select + congr_cl24_wD_d(2) <= (congr_cl24_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayD_upd select + congr_cl24_wD_d(3) <= (congr_cl24_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayD_upd select + congr_cl24_wD_d(4) <= (congr_cl24_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayD_upd select + congr_cl24_wD_d(5) <= (congr_cl24_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 25 +with rel_bixu25_wayD_upd select + congr_cl25_wD_d(0) <= (congr_cl25_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 25 +with rel_bixu25_wayD_upd select + congr_cl25_wD_d(1) <= (congr_cl25_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayD_upd select + congr_cl25_wD_d(2) <= (congr_cl25_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayD_upd select + congr_cl25_wD_d(3) <= (congr_cl25_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayD_upd select + congr_cl25_wD_d(4) <= (congr_cl25_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayD_upd select + congr_cl25_wD_d(5) <= (congr_cl25_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 26 +with rel_bixu26_wayD_upd select + congr_cl26_wD_d(0) <= (congr_cl26_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 26 +with rel_bixu26_wayD_upd select + congr_cl26_wD_d(1) <= (congr_cl26_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayD_upd select + congr_cl26_wD_d(2) <= (congr_cl26_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayD_upd select + congr_cl26_wD_d(3) <= (congr_cl26_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayD_upd select + congr_cl26_wD_d(4) <= (congr_cl26_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayD_upd select + congr_cl26_wD_d(5) <= (congr_cl26_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 27 +with rel_bixu27_wayD_upd select + congr_cl27_wD_d(0) <= (congr_cl27_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 27 +with rel_bixu27_wayD_upd select + congr_cl27_wD_d(1) <= (congr_cl27_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayD_upd select + congr_cl27_wD_d(2) <= (congr_cl27_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayD_upd select + congr_cl27_wD_d(3) <= (congr_cl27_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayD_upd select + congr_cl27_wD_d(4) <= (congr_cl27_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayD_upd select + congr_cl27_wD_d(5) <= (congr_cl27_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 28 +with rel_bixu28_wayD_upd select + congr_cl28_wD_d(0) <= (congr_cl28_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 28 +with rel_bixu28_wayD_upd select + congr_cl28_wD_d(1) <= (congr_cl28_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayD_upd select + congr_cl28_wD_d(2) <= (congr_cl28_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayD_upd select + congr_cl28_wD_d(3) <= (congr_cl28_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayD_upd select + congr_cl28_wD_d(4) <= (congr_cl28_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayD_upd select + congr_cl28_wD_d(5) <= (congr_cl28_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 29 +with rel_bixu29_wayD_upd select + congr_cl29_wD_d(0) <= (congr_cl29_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 29 +with rel_bixu29_wayD_upd select + congr_cl29_wD_d(1) <= (congr_cl29_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayD_upd select + congr_cl29_wD_d(2) <= (congr_cl29_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayD_upd select + congr_cl29_wD_d(3) <= (congr_cl29_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayD_upd select + congr_cl29_wD_d(4) <= (congr_cl29_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayD_upd select + congr_cl29_wD_d(5) <= (congr_cl29_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 30 +with rel_bixu30_wayD_upd select + congr_cl30_wD_d(0) <= (congr_cl30_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 30 +with rel_bixu30_wayD_upd select + congr_cl30_wD_d(1) <= (congr_cl30_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayD_upd select + congr_cl30_wD_d(2) <= (congr_cl30_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayD_upd select + congr_cl30_wD_d(3) <= (congr_cl30_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayD_upd select + congr_cl30_wD_d(4) <= (congr_cl30_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayD_upd select + congr_cl30_wD_d(5) <= (congr_cl30_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 31 +with rel_bixu31_wayD_upd select + congr_cl31_wD_d(0) <= (congr_cl31_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 31 +with rel_bixu31_wayD_upd select + congr_cl31_wD_d(1) <= (congr_cl31_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayD_upd select + congr_cl31_wD_d(2) <= (congr_cl31_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayD_upd select + congr_cl31_wD_d(3) <= (congr_cl31_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayD_upd select + congr_cl31_wD_d(4) <= (congr_cl31_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayD_upd select + congr_cl31_wD_d(5) <= (congr_cl31_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Write Select for WayE +-- WayE Valid Bit Update for Congruence Class 0 +with rel_bixu0_wayE_upd select + congr_cl0_wE_d(0) <= (congr_cl0_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 0 +with rel_bixu0_wayE_upd select + congr_cl0_wE_d(1) <= (congr_cl0_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayE_upd select + congr_cl0_wE_d(2) <= (congr_cl0_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayE_upd select + congr_cl0_wE_d(3) <= (congr_cl0_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayE_upd select + congr_cl0_wE_d(4) <= (congr_cl0_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayE_upd select + congr_cl0_wE_d(5) <= (congr_cl0_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 1 +with rel_bixu1_wayE_upd select + congr_cl1_wE_d(0) <= (congr_cl1_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 1 +with rel_bixu1_wayE_upd select + congr_cl1_wE_d(1) <= (congr_cl1_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayE_upd select + congr_cl1_wE_d(2) <= (congr_cl1_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayE_upd select + congr_cl1_wE_d(3) <= (congr_cl1_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayE_upd select + congr_cl1_wE_d(4) <= (congr_cl1_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayE_upd select + congr_cl1_wE_d(5) <= (congr_cl1_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 2 +with rel_bixu2_wayE_upd select + congr_cl2_wE_d(0) <= (congr_cl2_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 2 +with rel_bixu2_wayE_upd select + congr_cl2_wE_d(1) <= (congr_cl2_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayE_upd select + congr_cl2_wE_d(2) <= (congr_cl2_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayE_upd select + congr_cl2_wE_d(3) <= (congr_cl2_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayE_upd select + congr_cl2_wE_d(4) <= (congr_cl2_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayE_upd select + congr_cl2_wE_d(5) <= (congr_cl2_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 3 +with rel_bixu3_wayE_upd select + congr_cl3_wE_d(0) <= (congr_cl3_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 3 +with rel_bixu3_wayE_upd select + congr_cl3_wE_d(1) <= (congr_cl3_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayE_upd select + congr_cl3_wE_d(2) <= (congr_cl3_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayE_upd select + congr_cl3_wE_d(3) <= (congr_cl3_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayE_upd select + congr_cl3_wE_d(4) <= (congr_cl3_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayE_upd select + congr_cl3_wE_d(5) <= (congr_cl3_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 4 +with rel_bixu4_wayE_upd select + congr_cl4_wE_d(0) <= (congr_cl4_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 4 +with rel_bixu4_wayE_upd select + congr_cl4_wE_d(1) <= (congr_cl4_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayE_upd select + congr_cl4_wE_d(2) <= (congr_cl4_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayE_upd select + congr_cl4_wE_d(3) <= (congr_cl4_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayE_upd select + congr_cl4_wE_d(4) <= (congr_cl4_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayE_upd select + congr_cl4_wE_d(5) <= (congr_cl4_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 5 +with rel_bixu5_wayE_upd select + congr_cl5_wE_d(0) <= (congr_cl5_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 5 +with rel_bixu5_wayE_upd select + congr_cl5_wE_d(1) <= (congr_cl5_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayE_upd select + congr_cl5_wE_d(2) <= (congr_cl5_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayE_upd select + congr_cl5_wE_d(3) <= (congr_cl5_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayE_upd select + congr_cl5_wE_d(4) <= (congr_cl5_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayE_upd select + congr_cl5_wE_d(5) <= (congr_cl5_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 6 +with rel_bixu6_wayE_upd select + congr_cl6_wE_d(0) <= (congr_cl6_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 6 +with rel_bixu6_wayE_upd select + congr_cl6_wE_d(1) <= (congr_cl6_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayE_upd select + congr_cl6_wE_d(2) <= (congr_cl6_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayE_upd select + congr_cl6_wE_d(3) <= (congr_cl6_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayE_upd select + congr_cl6_wE_d(4) <= (congr_cl6_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayE_upd select + congr_cl6_wE_d(5) <= (congr_cl6_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 7 +with rel_bixu7_wayE_upd select + congr_cl7_wE_d(0) <= (congr_cl7_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 7 +with rel_bixu7_wayE_upd select + congr_cl7_wE_d(1) <= (congr_cl7_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayE_upd select + congr_cl7_wE_d(2) <= (congr_cl7_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayE_upd select + congr_cl7_wE_d(3) <= (congr_cl7_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayE_upd select + congr_cl7_wE_d(4) <= (congr_cl7_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayE_upd select + congr_cl7_wE_d(5) <= (congr_cl7_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 8 +with rel_bixu8_wayE_upd select + congr_cl8_wE_d(0) <= (congr_cl8_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 8 +with rel_bixu8_wayE_upd select + congr_cl8_wE_d(1) <= (congr_cl8_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayE_upd select + congr_cl8_wE_d(2) <= (congr_cl8_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayE_upd select + congr_cl8_wE_d(3) <= (congr_cl8_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayE_upd select + congr_cl8_wE_d(4) <= (congr_cl8_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayE_upd select + congr_cl8_wE_d(5) <= (congr_cl8_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 9 +with rel_bixu9_wayE_upd select + congr_cl9_wE_d(0) <= (congr_cl9_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 9 +with rel_bixu9_wayE_upd select + congr_cl9_wE_d(1) <= (congr_cl9_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayE_upd select + congr_cl9_wE_d(2) <= (congr_cl9_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayE_upd select + congr_cl9_wE_d(3) <= (congr_cl9_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayE_upd select + congr_cl9_wE_d(4) <= (congr_cl9_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayE_upd select + congr_cl9_wE_d(5) <= (congr_cl9_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 10 +with rel_bixu10_wayE_upd select + congr_cl10_wE_d(0) <= (congr_cl10_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 10 +with rel_bixu10_wayE_upd select + congr_cl10_wE_d(1) <= (congr_cl10_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayE_upd select + congr_cl10_wE_d(2) <= (congr_cl10_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayE_upd select + congr_cl10_wE_d(3) <= (congr_cl10_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayE_upd select + congr_cl10_wE_d(4) <= (congr_cl10_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayE_upd select + congr_cl10_wE_d(5) <= (congr_cl10_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 11 +with rel_bixu11_wayE_upd select + congr_cl11_wE_d(0) <= (congr_cl11_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 11 +with rel_bixu11_wayE_upd select + congr_cl11_wE_d(1) <= (congr_cl11_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayE_upd select + congr_cl11_wE_d(2) <= (congr_cl11_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayE_upd select + congr_cl11_wE_d(3) <= (congr_cl11_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayE_upd select + congr_cl11_wE_d(4) <= (congr_cl11_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayE_upd select + congr_cl11_wE_d(5) <= (congr_cl11_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 12 +with rel_bixu12_wayE_upd select + congr_cl12_wE_d(0) <= (congr_cl12_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 12 +with rel_bixu12_wayE_upd select + congr_cl12_wE_d(1) <= (congr_cl12_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayE_upd select + congr_cl12_wE_d(2) <= (congr_cl12_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayE_upd select + congr_cl12_wE_d(3) <= (congr_cl12_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayE_upd select + congr_cl12_wE_d(4) <= (congr_cl12_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayE_upd select + congr_cl12_wE_d(5) <= (congr_cl12_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 13 +with rel_bixu13_wayE_upd select + congr_cl13_wE_d(0) <= (congr_cl13_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 13 +with rel_bixu13_wayE_upd select + congr_cl13_wE_d(1) <= (congr_cl13_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayE_upd select + congr_cl13_wE_d(2) <= (congr_cl13_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayE_upd select + congr_cl13_wE_d(3) <= (congr_cl13_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayE_upd select + congr_cl13_wE_d(4) <= (congr_cl13_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayE_upd select + congr_cl13_wE_d(5) <= (congr_cl13_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 14 +with rel_bixu14_wayE_upd select + congr_cl14_wE_d(0) <= (congr_cl14_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 14 +with rel_bixu14_wayE_upd select + congr_cl14_wE_d(1) <= (congr_cl14_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayE_upd select + congr_cl14_wE_d(2) <= (congr_cl14_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayE_upd select + congr_cl14_wE_d(3) <= (congr_cl14_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayE_upd select + congr_cl14_wE_d(4) <= (congr_cl14_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayE_upd select + congr_cl14_wE_d(5) <= (congr_cl14_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 15 +with rel_bixu15_wayE_upd select + congr_cl15_wE_d(0) <= (congr_cl15_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 15 +with rel_bixu15_wayE_upd select + congr_cl15_wE_d(1) <= (congr_cl15_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayE_upd select + congr_cl15_wE_d(2) <= (congr_cl15_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayE_upd select + congr_cl15_wE_d(3) <= (congr_cl15_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayE_upd select + congr_cl15_wE_d(4) <= (congr_cl15_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayE_upd select + congr_cl15_wE_d(5) <= (congr_cl15_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 16 +with rel_bixu16_wayE_upd select + congr_cl16_wE_d(0) <= (congr_cl16_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 16 +with rel_bixu16_wayE_upd select + congr_cl16_wE_d(1) <= (congr_cl16_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayE_upd select + congr_cl16_wE_d(2) <= (congr_cl16_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayE_upd select + congr_cl16_wE_d(3) <= (congr_cl16_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayE_upd select + congr_cl16_wE_d(4) <= (congr_cl16_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayE_upd select + congr_cl16_wE_d(5) <= (congr_cl16_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 17 +with rel_bixu17_wayE_upd select + congr_cl17_wE_d(0) <= (congr_cl17_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 17 +with rel_bixu17_wayE_upd select + congr_cl17_wE_d(1) <= (congr_cl17_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayE_upd select + congr_cl17_wE_d(2) <= (congr_cl17_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayE_upd select + congr_cl17_wE_d(3) <= (congr_cl17_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayE_upd select + congr_cl17_wE_d(4) <= (congr_cl17_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayE_upd select + congr_cl17_wE_d(5) <= (congr_cl17_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 18 +with rel_bixu18_wayE_upd select + congr_cl18_wE_d(0) <= (congr_cl18_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 18 +with rel_bixu18_wayE_upd select + congr_cl18_wE_d(1) <= (congr_cl18_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayE_upd select + congr_cl18_wE_d(2) <= (congr_cl18_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayE_upd select + congr_cl18_wE_d(3) <= (congr_cl18_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayE_upd select + congr_cl18_wE_d(4) <= (congr_cl18_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayE_upd select + congr_cl18_wE_d(5) <= (congr_cl18_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 19 +with rel_bixu19_wayE_upd select + congr_cl19_wE_d(0) <= (congr_cl19_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 19 +with rel_bixu19_wayE_upd select + congr_cl19_wE_d(1) <= (congr_cl19_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayE_upd select + congr_cl19_wE_d(2) <= (congr_cl19_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayE_upd select + congr_cl19_wE_d(3) <= (congr_cl19_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayE_upd select + congr_cl19_wE_d(4) <= (congr_cl19_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayE_upd select + congr_cl19_wE_d(5) <= (congr_cl19_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 20 +with rel_bixu20_wayE_upd select + congr_cl20_wE_d(0) <= (congr_cl20_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 20 +with rel_bixu20_wayE_upd select + congr_cl20_wE_d(1) <= (congr_cl20_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayE_upd select + congr_cl20_wE_d(2) <= (congr_cl20_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayE_upd select + congr_cl20_wE_d(3) <= (congr_cl20_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayE_upd select + congr_cl20_wE_d(4) <= (congr_cl20_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayE_upd select + congr_cl20_wE_d(5) <= (congr_cl20_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 21 +with rel_bixu21_wayE_upd select + congr_cl21_wE_d(0) <= (congr_cl21_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 21 +with rel_bixu21_wayE_upd select + congr_cl21_wE_d(1) <= (congr_cl21_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayE_upd select + congr_cl21_wE_d(2) <= (congr_cl21_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayE_upd select + congr_cl21_wE_d(3) <= (congr_cl21_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayE_upd select + congr_cl21_wE_d(4) <= (congr_cl21_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayE_upd select + congr_cl21_wE_d(5) <= (congr_cl21_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 22 +with rel_bixu22_wayE_upd select + congr_cl22_wE_d(0) <= (congr_cl22_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 22 +with rel_bixu22_wayE_upd select + congr_cl22_wE_d(1) <= (congr_cl22_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayE_upd select + congr_cl22_wE_d(2) <= (congr_cl22_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayE_upd select + congr_cl22_wE_d(3) <= (congr_cl22_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayE_upd select + congr_cl22_wE_d(4) <= (congr_cl22_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayE_upd select + congr_cl22_wE_d(5) <= (congr_cl22_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 23 +with rel_bixu23_wayE_upd select + congr_cl23_wE_d(0) <= (congr_cl23_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 23 +with rel_bixu23_wayE_upd select + congr_cl23_wE_d(1) <= (congr_cl23_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayE_upd select + congr_cl23_wE_d(2) <= (congr_cl23_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayE_upd select + congr_cl23_wE_d(3) <= (congr_cl23_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayE_upd select + congr_cl23_wE_d(4) <= (congr_cl23_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayE_upd select + congr_cl23_wE_d(5) <= (congr_cl23_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 24 +with rel_bixu24_wayE_upd select + congr_cl24_wE_d(0) <= (congr_cl24_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 24 +with rel_bixu24_wayE_upd select + congr_cl24_wE_d(1) <= (congr_cl24_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayE_upd select + congr_cl24_wE_d(2) <= (congr_cl24_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayE_upd select + congr_cl24_wE_d(3) <= (congr_cl24_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayE_upd select + congr_cl24_wE_d(4) <= (congr_cl24_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayE_upd select + congr_cl24_wE_d(5) <= (congr_cl24_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 25 +with rel_bixu25_wayE_upd select + congr_cl25_wE_d(0) <= (congr_cl25_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 25 +with rel_bixu25_wayE_upd select + congr_cl25_wE_d(1) <= (congr_cl25_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayE_upd select + congr_cl25_wE_d(2) <= (congr_cl25_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayE_upd select + congr_cl25_wE_d(3) <= (congr_cl25_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayE_upd select + congr_cl25_wE_d(4) <= (congr_cl25_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayE_upd select + congr_cl25_wE_d(5) <= (congr_cl25_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 26 +with rel_bixu26_wayE_upd select + congr_cl26_wE_d(0) <= (congr_cl26_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 26 +with rel_bixu26_wayE_upd select + congr_cl26_wE_d(1) <= (congr_cl26_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayE_upd select + congr_cl26_wE_d(2) <= (congr_cl26_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayE_upd select + congr_cl26_wE_d(3) <= (congr_cl26_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayE_upd select + congr_cl26_wE_d(4) <= (congr_cl26_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayE_upd select + congr_cl26_wE_d(5) <= (congr_cl26_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 27 +with rel_bixu27_wayE_upd select + congr_cl27_wE_d(0) <= (congr_cl27_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 27 +with rel_bixu27_wayE_upd select + congr_cl27_wE_d(1) <= (congr_cl27_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayE_upd select + congr_cl27_wE_d(2) <= (congr_cl27_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayE_upd select + congr_cl27_wE_d(3) <= (congr_cl27_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayE_upd select + congr_cl27_wE_d(4) <= (congr_cl27_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayE_upd select + congr_cl27_wE_d(5) <= (congr_cl27_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 28 +with rel_bixu28_wayE_upd select + congr_cl28_wE_d(0) <= (congr_cl28_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 28 +with rel_bixu28_wayE_upd select + congr_cl28_wE_d(1) <= (congr_cl28_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayE_upd select + congr_cl28_wE_d(2) <= (congr_cl28_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayE_upd select + congr_cl28_wE_d(3) <= (congr_cl28_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayE_upd select + congr_cl28_wE_d(4) <= (congr_cl28_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayE_upd select + congr_cl28_wE_d(5) <= (congr_cl28_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 29 +with rel_bixu29_wayE_upd select + congr_cl29_wE_d(0) <= (congr_cl29_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 29 +with rel_bixu29_wayE_upd select + congr_cl29_wE_d(1) <= (congr_cl29_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayE_upd select + congr_cl29_wE_d(2) <= (congr_cl29_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayE_upd select + congr_cl29_wE_d(3) <= (congr_cl29_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayE_upd select + congr_cl29_wE_d(4) <= (congr_cl29_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayE_upd select + congr_cl29_wE_d(5) <= (congr_cl29_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 30 +with rel_bixu30_wayE_upd select + congr_cl30_wE_d(0) <= (congr_cl30_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 30 +with rel_bixu30_wayE_upd select + congr_cl30_wE_d(1) <= (congr_cl30_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayE_upd select + congr_cl30_wE_d(2) <= (congr_cl30_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayE_upd select + congr_cl30_wE_d(3) <= (congr_cl30_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayE_upd select + congr_cl30_wE_d(4) <= (congr_cl30_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayE_upd select + congr_cl30_wE_d(5) <= (congr_cl30_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 31 +with rel_bixu31_wayE_upd select + congr_cl31_wE_d(0) <= (congr_cl31_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 31 +with rel_bixu31_wayE_upd select + congr_cl31_wE_d(1) <= (congr_cl31_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayE_upd select + congr_cl31_wE_d(2) <= (congr_cl31_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayE_upd select + congr_cl31_wE_d(3) <= (congr_cl31_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayE_upd select + congr_cl31_wE_d(4) <= (congr_cl31_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayE_upd select + congr_cl31_wE_d(5) <= (congr_cl31_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Write Select for WayF +-- WayF Valid Bit Update for Congruence Class 0 +with rel_bixu0_wayF_upd select + congr_cl0_wF_d(0) <= (congr_cl0_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 0 +with rel_bixu0_wayF_upd select + congr_cl0_wF_d(1) <= (congr_cl0_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayF_upd select + congr_cl0_wF_d(2) <= (congr_cl0_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayF_upd select + congr_cl0_wF_d(3) <= (congr_cl0_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayF_upd select + congr_cl0_wF_d(4) <= (congr_cl0_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayF_upd select + congr_cl0_wF_d(5) <= (congr_cl0_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 1 +with rel_bixu1_wayF_upd select + congr_cl1_wF_d(0) <= (congr_cl1_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 1 +with rel_bixu1_wayF_upd select + congr_cl1_wF_d(1) <= (congr_cl1_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayF_upd select + congr_cl1_wF_d(2) <= (congr_cl1_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayF_upd select + congr_cl1_wF_d(3) <= (congr_cl1_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayF_upd select + congr_cl1_wF_d(4) <= (congr_cl1_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayF_upd select + congr_cl1_wF_d(5) <= (congr_cl1_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 2 +with rel_bixu2_wayF_upd select + congr_cl2_wF_d(0) <= (congr_cl2_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 2 +with rel_bixu2_wayF_upd select + congr_cl2_wF_d(1) <= (congr_cl2_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayF_upd select + congr_cl2_wF_d(2) <= (congr_cl2_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayF_upd select + congr_cl2_wF_d(3) <= (congr_cl2_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayF_upd select + congr_cl2_wF_d(4) <= (congr_cl2_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayF_upd select + congr_cl2_wF_d(5) <= (congr_cl2_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 3 +with rel_bixu3_wayF_upd select + congr_cl3_wF_d(0) <= (congr_cl3_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 3 +with rel_bixu3_wayF_upd select + congr_cl3_wF_d(1) <= (congr_cl3_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayF_upd select + congr_cl3_wF_d(2) <= (congr_cl3_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayF_upd select + congr_cl3_wF_d(3) <= (congr_cl3_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayF_upd select + congr_cl3_wF_d(4) <= (congr_cl3_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayF_upd select + congr_cl3_wF_d(5) <= (congr_cl3_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 4 +with rel_bixu4_wayF_upd select + congr_cl4_wF_d(0) <= (congr_cl4_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 4 +with rel_bixu4_wayF_upd select + congr_cl4_wF_d(1) <= (congr_cl4_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayF_upd select + congr_cl4_wF_d(2) <= (congr_cl4_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayF_upd select + congr_cl4_wF_d(3) <= (congr_cl4_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayF_upd select + congr_cl4_wF_d(4) <= (congr_cl4_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayF_upd select + congr_cl4_wF_d(5) <= (congr_cl4_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 5 +with rel_bixu5_wayF_upd select + congr_cl5_wF_d(0) <= (congr_cl5_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 5 +with rel_bixu5_wayF_upd select + congr_cl5_wF_d(1) <= (congr_cl5_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayF_upd select + congr_cl5_wF_d(2) <= (congr_cl5_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayF_upd select + congr_cl5_wF_d(3) <= (congr_cl5_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayF_upd select + congr_cl5_wF_d(4) <= (congr_cl5_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayF_upd select + congr_cl5_wF_d(5) <= (congr_cl5_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 6 +with rel_bixu6_wayF_upd select + congr_cl6_wF_d(0) <= (congr_cl6_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 6 +with rel_bixu6_wayF_upd select + congr_cl6_wF_d(1) <= (congr_cl6_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayF_upd select + congr_cl6_wF_d(2) <= (congr_cl6_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayF_upd select + congr_cl6_wF_d(3) <= (congr_cl6_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayF_upd select + congr_cl6_wF_d(4) <= (congr_cl6_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayF_upd select + congr_cl6_wF_d(5) <= (congr_cl6_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 7 +with rel_bixu7_wayF_upd select + congr_cl7_wF_d(0) <= (congr_cl7_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 7 +with rel_bixu7_wayF_upd select + congr_cl7_wF_d(1) <= (congr_cl7_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayF_upd select + congr_cl7_wF_d(2) <= (congr_cl7_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayF_upd select + congr_cl7_wF_d(3) <= (congr_cl7_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayF_upd select + congr_cl7_wF_d(4) <= (congr_cl7_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayF_upd select + congr_cl7_wF_d(5) <= (congr_cl7_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 8 +with rel_bixu8_wayF_upd select + congr_cl8_wF_d(0) <= (congr_cl8_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 8 +with rel_bixu8_wayF_upd select + congr_cl8_wF_d(1) <= (congr_cl8_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayF_upd select + congr_cl8_wF_d(2) <= (congr_cl8_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayF_upd select + congr_cl8_wF_d(3) <= (congr_cl8_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayF_upd select + congr_cl8_wF_d(4) <= (congr_cl8_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayF_upd select + congr_cl8_wF_d(5) <= (congr_cl8_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 9 +with rel_bixu9_wayF_upd select + congr_cl9_wF_d(0) <= (congr_cl9_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 9 +with rel_bixu9_wayF_upd select + congr_cl9_wF_d(1) <= (congr_cl9_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayF_upd select + congr_cl9_wF_d(2) <= (congr_cl9_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayF_upd select + congr_cl9_wF_d(3) <= (congr_cl9_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayF_upd select + congr_cl9_wF_d(4) <= (congr_cl9_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayF_upd select + congr_cl9_wF_d(5) <= (congr_cl9_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 10 +with rel_bixu10_wayF_upd select + congr_cl10_wF_d(0) <= (congr_cl10_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 10 +with rel_bixu10_wayF_upd select + congr_cl10_wF_d(1) <= (congr_cl10_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayF_upd select + congr_cl10_wF_d(2) <= (congr_cl10_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayF_upd select + congr_cl10_wF_d(3) <= (congr_cl10_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayF_upd select + congr_cl10_wF_d(4) <= (congr_cl10_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayF_upd select + congr_cl10_wF_d(5) <= (congr_cl10_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 11 +with rel_bixu11_wayF_upd select + congr_cl11_wF_d(0) <= (congr_cl11_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 11 +with rel_bixu11_wayF_upd select + congr_cl11_wF_d(1) <= (congr_cl11_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayF_upd select + congr_cl11_wF_d(2) <= (congr_cl11_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayF_upd select + congr_cl11_wF_d(3) <= (congr_cl11_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayF_upd select + congr_cl11_wF_d(4) <= (congr_cl11_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayF_upd select + congr_cl11_wF_d(5) <= (congr_cl11_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 12 +with rel_bixu12_wayF_upd select + congr_cl12_wF_d(0) <= (congr_cl12_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 12 +with rel_bixu12_wayF_upd select + congr_cl12_wF_d(1) <= (congr_cl12_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayF_upd select + congr_cl12_wF_d(2) <= (congr_cl12_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayF_upd select + congr_cl12_wF_d(3) <= (congr_cl12_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayF_upd select + congr_cl12_wF_d(4) <= (congr_cl12_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayF_upd select + congr_cl12_wF_d(5) <= (congr_cl12_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 13 +with rel_bixu13_wayF_upd select + congr_cl13_wF_d(0) <= (congr_cl13_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 13 +with rel_bixu13_wayF_upd select + congr_cl13_wF_d(1) <= (congr_cl13_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayF_upd select + congr_cl13_wF_d(2) <= (congr_cl13_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayF_upd select + congr_cl13_wF_d(3) <= (congr_cl13_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayF_upd select + congr_cl13_wF_d(4) <= (congr_cl13_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayF_upd select + congr_cl13_wF_d(5) <= (congr_cl13_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 14 +with rel_bixu14_wayF_upd select + congr_cl14_wF_d(0) <= (congr_cl14_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 14 +with rel_bixu14_wayF_upd select + congr_cl14_wF_d(1) <= (congr_cl14_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayF_upd select + congr_cl14_wF_d(2) <= (congr_cl14_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayF_upd select + congr_cl14_wF_d(3) <= (congr_cl14_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayF_upd select + congr_cl14_wF_d(4) <= (congr_cl14_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayF_upd select + congr_cl14_wF_d(5) <= (congr_cl14_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 15 +with rel_bixu15_wayF_upd select + congr_cl15_wF_d(0) <= (congr_cl15_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 15 +with rel_bixu15_wayF_upd select + congr_cl15_wF_d(1) <= (congr_cl15_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayF_upd select + congr_cl15_wF_d(2) <= (congr_cl15_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayF_upd select + congr_cl15_wF_d(3) <= (congr_cl15_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayF_upd select + congr_cl15_wF_d(4) <= (congr_cl15_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayF_upd select + congr_cl15_wF_d(5) <= (congr_cl15_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 16 +with rel_bixu16_wayF_upd select + congr_cl16_wF_d(0) <= (congr_cl16_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 16 +with rel_bixu16_wayF_upd select + congr_cl16_wF_d(1) <= (congr_cl16_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayF_upd select + congr_cl16_wF_d(2) <= (congr_cl16_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayF_upd select + congr_cl16_wF_d(3) <= (congr_cl16_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayF_upd select + congr_cl16_wF_d(4) <= (congr_cl16_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayF_upd select + congr_cl16_wF_d(5) <= (congr_cl16_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 17 +with rel_bixu17_wayF_upd select + congr_cl17_wF_d(0) <= (congr_cl17_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 17 +with rel_bixu17_wayF_upd select + congr_cl17_wF_d(1) <= (congr_cl17_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayF_upd select + congr_cl17_wF_d(2) <= (congr_cl17_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayF_upd select + congr_cl17_wF_d(3) <= (congr_cl17_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayF_upd select + congr_cl17_wF_d(4) <= (congr_cl17_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayF_upd select + congr_cl17_wF_d(5) <= (congr_cl17_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 18 +with rel_bixu18_wayF_upd select + congr_cl18_wF_d(0) <= (congr_cl18_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 18 +with rel_bixu18_wayF_upd select + congr_cl18_wF_d(1) <= (congr_cl18_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayF_upd select + congr_cl18_wF_d(2) <= (congr_cl18_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayF_upd select + congr_cl18_wF_d(3) <= (congr_cl18_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayF_upd select + congr_cl18_wF_d(4) <= (congr_cl18_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayF_upd select + congr_cl18_wF_d(5) <= (congr_cl18_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 19 +with rel_bixu19_wayF_upd select + congr_cl19_wF_d(0) <= (congr_cl19_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 19 +with rel_bixu19_wayF_upd select + congr_cl19_wF_d(1) <= (congr_cl19_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayF_upd select + congr_cl19_wF_d(2) <= (congr_cl19_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayF_upd select + congr_cl19_wF_d(3) <= (congr_cl19_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayF_upd select + congr_cl19_wF_d(4) <= (congr_cl19_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayF_upd select + congr_cl19_wF_d(5) <= (congr_cl19_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 20 +with rel_bixu20_wayF_upd select + congr_cl20_wF_d(0) <= (congr_cl20_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 20 +with rel_bixu20_wayF_upd select + congr_cl20_wF_d(1) <= (congr_cl20_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayF_upd select + congr_cl20_wF_d(2) <= (congr_cl20_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayF_upd select + congr_cl20_wF_d(3) <= (congr_cl20_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayF_upd select + congr_cl20_wF_d(4) <= (congr_cl20_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayF_upd select + congr_cl20_wF_d(5) <= (congr_cl20_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 21 +with rel_bixu21_wayF_upd select + congr_cl21_wF_d(0) <= (congr_cl21_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 21 +with rel_bixu21_wayF_upd select + congr_cl21_wF_d(1) <= (congr_cl21_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayF_upd select + congr_cl21_wF_d(2) <= (congr_cl21_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayF_upd select + congr_cl21_wF_d(3) <= (congr_cl21_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayF_upd select + congr_cl21_wF_d(4) <= (congr_cl21_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayF_upd select + congr_cl21_wF_d(5) <= (congr_cl21_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 22 +with rel_bixu22_wayF_upd select + congr_cl22_wF_d(0) <= (congr_cl22_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 22 +with rel_bixu22_wayF_upd select + congr_cl22_wF_d(1) <= (congr_cl22_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayF_upd select + congr_cl22_wF_d(2) <= (congr_cl22_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayF_upd select + congr_cl22_wF_d(3) <= (congr_cl22_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayF_upd select + congr_cl22_wF_d(4) <= (congr_cl22_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayF_upd select + congr_cl22_wF_d(5) <= (congr_cl22_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 23 +with rel_bixu23_wayF_upd select + congr_cl23_wF_d(0) <= (congr_cl23_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 23 +with rel_bixu23_wayF_upd select + congr_cl23_wF_d(1) <= (congr_cl23_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayF_upd select + congr_cl23_wF_d(2) <= (congr_cl23_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayF_upd select + congr_cl23_wF_d(3) <= (congr_cl23_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayF_upd select + congr_cl23_wF_d(4) <= (congr_cl23_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayF_upd select + congr_cl23_wF_d(5) <= (congr_cl23_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 24 +with rel_bixu24_wayF_upd select + congr_cl24_wF_d(0) <= (congr_cl24_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 24 +with rel_bixu24_wayF_upd select + congr_cl24_wF_d(1) <= (congr_cl24_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayF_upd select + congr_cl24_wF_d(2) <= (congr_cl24_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayF_upd select + congr_cl24_wF_d(3) <= (congr_cl24_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayF_upd select + congr_cl24_wF_d(4) <= (congr_cl24_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayF_upd select + congr_cl24_wF_d(5) <= (congr_cl24_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 25 +with rel_bixu25_wayF_upd select + congr_cl25_wF_d(0) <= (congr_cl25_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 25 +with rel_bixu25_wayF_upd select + congr_cl25_wF_d(1) <= (congr_cl25_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayF_upd select + congr_cl25_wF_d(2) <= (congr_cl25_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayF_upd select + congr_cl25_wF_d(3) <= (congr_cl25_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayF_upd select + congr_cl25_wF_d(4) <= (congr_cl25_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayF_upd select + congr_cl25_wF_d(5) <= (congr_cl25_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 26 +with rel_bixu26_wayF_upd select + congr_cl26_wF_d(0) <= (congr_cl26_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 26 +with rel_bixu26_wayF_upd select + congr_cl26_wF_d(1) <= (congr_cl26_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayF_upd select + congr_cl26_wF_d(2) <= (congr_cl26_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayF_upd select + congr_cl26_wF_d(3) <= (congr_cl26_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayF_upd select + congr_cl26_wF_d(4) <= (congr_cl26_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayF_upd select + congr_cl26_wF_d(5) <= (congr_cl26_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 27 +with rel_bixu27_wayF_upd select + congr_cl27_wF_d(0) <= (congr_cl27_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 27 +with rel_bixu27_wayF_upd select + congr_cl27_wF_d(1) <= (congr_cl27_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayF_upd select + congr_cl27_wF_d(2) <= (congr_cl27_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayF_upd select + congr_cl27_wF_d(3) <= (congr_cl27_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayF_upd select + congr_cl27_wF_d(4) <= (congr_cl27_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayF_upd select + congr_cl27_wF_d(5) <= (congr_cl27_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 28 +with rel_bixu28_wayF_upd select + congr_cl28_wF_d(0) <= (congr_cl28_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 28 +with rel_bixu28_wayF_upd select + congr_cl28_wF_d(1) <= (congr_cl28_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayF_upd select + congr_cl28_wF_d(2) <= (congr_cl28_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayF_upd select + congr_cl28_wF_d(3) <= (congr_cl28_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayF_upd select + congr_cl28_wF_d(4) <= (congr_cl28_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayF_upd select + congr_cl28_wF_d(5) <= (congr_cl28_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 29 +with rel_bixu29_wayF_upd select + congr_cl29_wF_d(0) <= (congr_cl29_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 29 +with rel_bixu29_wayF_upd select + congr_cl29_wF_d(1) <= (congr_cl29_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayF_upd select + congr_cl29_wF_d(2) <= (congr_cl29_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayF_upd select + congr_cl29_wF_d(3) <= (congr_cl29_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayF_upd select + congr_cl29_wF_d(4) <= (congr_cl29_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayF_upd select + congr_cl29_wF_d(5) <= (congr_cl29_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 30 +with rel_bixu30_wayF_upd select + congr_cl30_wF_d(0) <= (congr_cl30_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 30 +with rel_bixu30_wayF_upd select + congr_cl30_wF_d(1) <= (congr_cl30_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayF_upd select + congr_cl30_wF_d(2) <= (congr_cl30_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayF_upd select + congr_cl30_wF_d(3) <= (congr_cl30_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayF_upd select + congr_cl30_wF_d(4) <= (congr_cl30_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayF_upd select + congr_cl30_wF_d(5) <= (congr_cl30_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 31 +with rel_bixu31_wayF_upd select + congr_cl31_wF_d(0) <= (congr_cl31_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 31 +with rel_bixu31_wayF_upd select + congr_cl31_wF_d(1) <= (congr_cl31_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayF_upd select + congr_cl31_wF_d(2) <= (congr_cl31_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayF_upd select + congr_cl31_wF_d(3) <= (congr_cl31_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayF_upd select + congr_cl31_wF_d(4) <= (congr_cl31_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayF_upd select + congr_cl31_wF_d(5) <= (congr_cl31_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Write Select for WayG +-- WayG Valid Bit Update for Congruence Class 0 +with rel_bixu0_wayG_upd select + congr_cl0_wG_d(0) <= (congr_cl0_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 0 +with rel_bixu0_wayG_upd select + congr_cl0_wG_d(1) <= (congr_cl0_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayG_upd select + congr_cl0_wG_d(2) <= (congr_cl0_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayG_upd select + congr_cl0_wG_d(3) <= (congr_cl0_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayG_upd select + congr_cl0_wG_d(4) <= (congr_cl0_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayG_upd select + congr_cl0_wG_d(5) <= (congr_cl0_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 1 +with rel_bixu1_wayG_upd select + congr_cl1_wG_d(0) <= (congr_cl1_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 1 +with rel_bixu1_wayG_upd select + congr_cl1_wG_d(1) <= (congr_cl1_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayG_upd select + congr_cl1_wG_d(2) <= (congr_cl1_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayG_upd select + congr_cl1_wG_d(3) <= (congr_cl1_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayG_upd select + congr_cl1_wG_d(4) <= (congr_cl1_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayG_upd select + congr_cl1_wG_d(5) <= (congr_cl1_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 2 +with rel_bixu2_wayG_upd select + congr_cl2_wG_d(0) <= (congr_cl2_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 2 +with rel_bixu2_wayG_upd select + congr_cl2_wG_d(1) <= (congr_cl2_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayG_upd select + congr_cl2_wG_d(2) <= (congr_cl2_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayG_upd select + congr_cl2_wG_d(3) <= (congr_cl2_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayG_upd select + congr_cl2_wG_d(4) <= (congr_cl2_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayG_upd select + congr_cl2_wG_d(5) <= (congr_cl2_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 3 +with rel_bixu3_wayG_upd select + congr_cl3_wG_d(0) <= (congr_cl3_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 3 +with rel_bixu3_wayG_upd select + congr_cl3_wG_d(1) <= (congr_cl3_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayG_upd select + congr_cl3_wG_d(2) <= (congr_cl3_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayG_upd select + congr_cl3_wG_d(3) <= (congr_cl3_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayG_upd select + congr_cl3_wG_d(4) <= (congr_cl3_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayG_upd select + congr_cl3_wG_d(5) <= (congr_cl3_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 4 +with rel_bixu4_wayG_upd select + congr_cl4_wG_d(0) <= (congr_cl4_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 4 +with rel_bixu4_wayG_upd select + congr_cl4_wG_d(1) <= (congr_cl4_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayG_upd select + congr_cl4_wG_d(2) <= (congr_cl4_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayG_upd select + congr_cl4_wG_d(3) <= (congr_cl4_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayG_upd select + congr_cl4_wG_d(4) <= (congr_cl4_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayG_upd select + congr_cl4_wG_d(5) <= (congr_cl4_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 5 +with rel_bixu5_wayG_upd select + congr_cl5_wG_d(0) <= (congr_cl5_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 5 +with rel_bixu5_wayG_upd select + congr_cl5_wG_d(1) <= (congr_cl5_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayG_upd select + congr_cl5_wG_d(2) <= (congr_cl5_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayG_upd select + congr_cl5_wG_d(3) <= (congr_cl5_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayG_upd select + congr_cl5_wG_d(4) <= (congr_cl5_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayG_upd select + congr_cl5_wG_d(5) <= (congr_cl5_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 6 +with rel_bixu6_wayG_upd select + congr_cl6_wG_d(0) <= (congr_cl6_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 6 +with rel_bixu6_wayG_upd select + congr_cl6_wG_d(1) <= (congr_cl6_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayG_upd select + congr_cl6_wG_d(2) <= (congr_cl6_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayG_upd select + congr_cl6_wG_d(3) <= (congr_cl6_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayG_upd select + congr_cl6_wG_d(4) <= (congr_cl6_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayG_upd select + congr_cl6_wG_d(5) <= (congr_cl6_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 7 +with rel_bixu7_wayG_upd select + congr_cl7_wG_d(0) <= (congr_cl7_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 7 +with rel_bixu7_wayG_upd select + congr_cl7_wG_d(1) <= (congr_cl7_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayG_upd select + congr_cl7_wG_d(2) <= (congr_cl7_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayG_upd select + congr_cl7_wG_d(3) <= (congr_cl7_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayG_upd select + congr_cl7_wG_d(4) <= (congr_cl7_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayG_upd select + congr_cl7_wG_d(5) <= (congr_cl7_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 8 +with rel_bixu8_wayG_upd select + congr_cl8_wG_d(0) <= (congr_cl8_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 8 +with rel_bixu8_wayG_upd select + congr_cl8_wG_d(1) <= (congr_cl8_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayG_upd select + congr_cl8_wG_d(2) <= (congr_cl8_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayG_upd select + congr_cl8_wG_d(3) <= (congr_cl8_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayG_upd select + congr_cl8_wG_d(4) <= (congr_cl8_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayG_upd select + congr_cl8_wG_d(5) <= (congr_cl8_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 9 +with rel_bixu9_wayG_upd select + congr_cl9_wG_d(0) <= (congr_cl9_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 9 +with rel_bixu9_wayG_upd select + congr_cl9_wG_d(1) <= (congr_cl9_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayG_upd select + congr_cl9_wG_d(2) <= (congr_cl9_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayG_upd select + congr_cl9_wG_d(3) <= (congr_cl9_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayG_upd select + congr_cl9_wG_d(4) <= (congr_cl9_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayG_upd select + congr_cl9_wG_d(5) <= (congr_cl9_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 10 +with rel_bixu10_wayG_upd select + congr_cl10_wG_d(0) <= (congr_cl10_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 10 +with rel_bixu10_wayG_upd select + congr_cl10_wG_d(1) <= (congr_cl10_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayG_upd select + congr_cl10_wG_d(2) <= (congr_cl10_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayG_upd select + congr_cl10_wG_d(3) <= (congr_cl10_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayG_upd select + congr_cl10_wG_d(4) <= (congr_cl10_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayG_upd select + congr_cl10_wG_d(5) <= (congr_cl10_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 11 +with rel_bixu11_wayG_upd select + congr_cl11_wG_d(0) <= (congr_cl11_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 11 +with rel_bixu11_wayG_upd select + congr_cl11_wG_d(1) <= (congr_cl11_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayG_upd select + congr_cl11_wG_d(2) <= (congr_cl11_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayG_upd select + congr_cl11_wG_d(3) <= (congr_cl11_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayG_upd select + congr_cl11_wG_d(4) <= (congr_cl11_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayG_upd select + congr_cl11_wG_d(5) <= (congr_cl11_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 12 +with rel_bixu12_wayG_upd select + congr_cl12_wG_d(0) <= (congr_cl12_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 12 +with rel_bixu12_wayG_upd select + congr_cl12_wG_d(1) <= (congr_cl12_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayG_upd select + congr_cl12_wG_d(2) <= (congr_cl12_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayG_upd select + congr_cl12_wG_d(3) <= (congr_cl12_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayG_upd select + congr_cl12_wG_d(4) <= (congr_cl12_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayG_upd select + congr_cl12_wG_d(5) <= (congr_cl12_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 13 +with rel_bixu13_wayG_upd select + congr_cl13_wG_d(0) <= (congr_cl13_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 13 +with rel_bixu13_wayG_upd select + congr_cl13_wG_d(1) <= (congr_cl13_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayG_upd select + congr_cl13_wG_d(2) <= (congr_cl13_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayG_upd select + congr_cl13_wG_d(3) <= (congr_cl13_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayG_upd select + congr_cl13_wG_d(4) <= (congr_cl13_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayG_upd select + congr_cl13_wG_d(5) <= (congr_cl13_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 14 +with rel_bixu14_wayG_upd select + congr_cl14_wG_d(0) <= (congr_cl14_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 14 +with rel_bixu14_wayG_upd select + congr_cl14_wG_d(1) <= (congr_cl14_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayG_upd select + congr_cl14_wG_d(2) <= (congr_cl14_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayG_upd select + congr_cl14_wG_d(3) <= (congr_cl14_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayG_upd select + congr_cl14_wG_d(4) <= (congr_cl14_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayG_upd select + congr_cl14_wG_d(5) <= (congr_cl14_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 15 +with rel_bixu15_wayG_upd select + congr_cl15_wG_d(0) <= (congr_cl15_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 15 +with rel_bixu15_wayG_upd select + congr_cl15_wG_d(1) <= (congr_cl15_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayG_upd select + congr_cl15_wG_d(2) <= (congr_cl15_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayG_upd select + congr_cl15_wG_d(3) <= (congr_cl15_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayG_upd select + congr_cl15_wG_d(4) <= (congr_cl15_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayG_upd select + congr_cl15_wG_d(5) <= (congr_cl15_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 16 +with rel_bixu16_wayG_upd select + congr_cl16_wG_d(0) <= (congr_cl16_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 16 +with rel_bixu16_wayG_upd select + congr_cl16_wG_d(1) <= (congr_cl16_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayG_upd select + congr_cl16_wG_d(2) <= (congr_cl16_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayG_upd select + congr_cl16_wG_d(3) <= (congr_cl16_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayG_upd select + congr_cl16_wG_d(4) <= (congr_cl16_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayG_upd select + congr_cl16_wG_d(5) <= (congr_cl16_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 17 +with rel_bixu17_wayG_upd select + congr_cl17_wG_d(0) <= (congr_cl17_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 17 +with rel_bixu17_wayG_upd select + congr_cl17_wG_d(1) <= (congr_cl17_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayG_upd select + congr_cl17_wG_d(2) <= (congr_cl17_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayG_upd select + congr_cl17_wG_d(3) <= (congr_cl17_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayG_upd select + congr_cl17_wG_d(4) <= (congr_cl17_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayG_upd select + congr_cl17_wG_d(5) <= (congr_cl17_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 18 +with rel_bixu18_wayG_upd select + congr_cl18_wG_d(0) <= (congr_cl18_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 18 +with rel_bixu18_wayG_upd select + congr_cl18_wG_d(1) <= (congr_cl18_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayG_upd select + congr_cl18_wG_d(2) <= (congr_cl18_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayG_upd select + congr_cl18_wG_d(3) <= (congr_cl18_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayG_upd select + congr_cl18_wG_d(4) <= (congr_cl18_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayG_upd select + congr_cl18_wG_d(5) <= (congr_cl18_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 19 +with rel_bixu19_wayG_upd select + congr_cl19_wG_d(0) <= (congr_cl19_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 19 +with rel_bixu19_wayG_upd select + congr_cl19_wG_d(1) <= (congr_cl19_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayG_upd select + congr_cl19_wG_d(2) <= (congr_cl19_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayG_upd select + congr_cl19_wG_d(3) <= (congr_cl19_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayG_upd select + congr_cl19_wG_d(4) <= (congr_cl19_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayG_upd select + congr_cl19_wG_d(5) <= (congr_cl19_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 20 +with rel_bixu20_wayG_upd select + congr_cl20_wG_d(0) <= (congr_cl20_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 20 +with rel_bixu20_wayG_upd select + congr_cl20_wG_d(1) <= (congr_cl20_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayG_upd select + congr_cl20_wG_d(2) <= (congr_cl20_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayG_upd select + congr_cl20_wG_d(3) <= (congr_cl20_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayG_upd select + congr_cl20_wG_d(4) <= (congr_cl20_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayG_upd select + congr_cl20_wG_d(5) <= (congr_cl20_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 21 +with rel_bixu21_wayG_upd select + congr_cl21_wG_d(0) <= (congr_cl21_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 21 +with rel_bixu21_wayG_upd select + congr_cl21_wG_d(1) <= (congr_cl21_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayG_upd select + congr_cl21_wG_d(2) <= (congr_cl21_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayG_upd select + congr_cl21_wG_d(3) <= (congr_cl21_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayG_upd select + congr_cl21_wG_d(4) <= (congr_cl21_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayG_upd select + congr_cl21_wG_d(5) <= (congr_cl21_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 22 +with rel_bixu22_wayG_upd select + congr_cl22_wG_d(0) <= (congr_cl22_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 22 +with rel_bixu22_wayG_upd select + congr_cl22_wG_d(1) <= (congr_cl22_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayG_upd select + congr_cl22_wG_d(2) <= (congr_cl22_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayG_upd select + congr_cl22_wG_d(3) <= (congr_cl22_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayG_upd select + congr_cl22_wG_d(4) <= (congr_cl22_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayG_upd select + congr_cl22_wG_d(5) <= (congr_cl22_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 23 +with rel_bixu23_wayG_upd select + congr_cl23_wG_d(0) <= (congr_cl23_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 23 +with rel_bixu23_wayG_upd select + congr_cl23_wG_d(1) <= (congr_cl23_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayG_upd select + congr_cl23_wG_d(2) <= (congr_cl23_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayG_upd select + congr_cl23_wG_d(3) <= (congr_cl23_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayG_upd select + congr_cl23_wG_d(4) <= (congr_cl23_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayG_upd select + congr_cl23_wG_d(5) <= (congr_cl23_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 24 +with rel_bixu24_wayG_upd select + congr_cl24_wG_d(0) <= (congr_cl24_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 24 +with rel_bixu24_wayG_upd select + congr_cl24_wG_d(1) <= (congr_cl24_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayG_upd select + congr_cl24_wG_d(2) <= (congr_cl24_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayG_upd select + congr_cl24_wG_d(3) <= (congr_cl24_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayG_upd select + congr_cl24_wG_d(4) <= (congr_cl24_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayG_upd select + congr_cl24_wG_d(5) <= (congr_cl24_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 25 +with rel_bixu25_wayG_upd select + congr_cl25_wG_d(0) <= (congr_cl25_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 25 +with rel_bixu25_wayG_upd select + congr_cl25_wG_d(1) <= (congr_cl25_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayG_upd select + congr_cl25_wG_d(2) <= (congr_cl25_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayG_upd select + congr_cl25_wG_d(3) <= (congr_cl25_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayG_upd select + congr_cl25_wG_d(4) <= (congr_cl25_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayG_upd select + congr_cl25_wG_d(5) <= (congr_cl25_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 26 +with rel_bixu26_wayG_upd select + congr_cl26_wG_d(0) <= (congr_cl26_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 26 +with rel_bixu26_wayG_upd select + congr_cl26_wG_d(1) <= (congr_cl26_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayG_upd select + congr_cl26_wG_d(2) <= (congr_cl26_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayG_upd select + congr_cl26_wG_d(3) <= (congr_cl26_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayG_upd select + congr_cl26_wG_d(4) <= (congr_cl26_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayG_upd select + congr_cl26_wG_d(5) <= (congr_cl26_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 27 +with rel_bixu27_wayG_upd select + congr_cl27_wG_d(0) <= (congr_cl27_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 27 +with rel_bixu27_wayG_upd select + congr_cl27_wG_d(1) <= (congr_cl27_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayG_upd select + congr_cl27_wG_d(2) <= (congr_cl27_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayG_upd select + congr_cl27_wG_d(3) <= (congr_cl27_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayG_upd select + congr_cl27_wG_d(4) <= (congr_cl27_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayG_upd select + congr_cl27_wG_d(5) <= (congr_cl27_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 28 +with rel_bixu28_wayG_upd select + congr_cl28_wG_d(0) <= (congr_cl28_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 28 +with rel_bixu28_wayG_upd select + congr_cl28_wG_d(1) <= (congr_cl28_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayG_upd select + congr_cl28_wG_d(2) <= (congr_cl28_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayG_upd select + congr_cl28_wG_d(3) <= (congr_cl28_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayG_upd select + congr_cl28_wG_d(4) <= (congr_cl28_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayG_upd select + congr_cl28_wG_d(5) <= (congr_cl28_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 29 +with rel_bixu29_wayG_upd select + congr_cl29_wG_d(0) <= (congr_cl29_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 29 +with rel_bixu29_wayG_upd select + congr_cl29_wG_d(1) <= (congr_cl29_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayG_upd select + congr_cl29_wG_d(2) <= (congr_cl29_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayG_upd select + congr_cl29_wG_d(3) <= (congr_cl29_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayG_upd select + congr_cl29_wG_d(4) <= (congr_cl29_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayG_upd select + congr_cl29_wG_d(5) <= (congr_cl29_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 30 +with rel_bixu30_wayG_upd select + congr_cl30_wG_d(0) <= (congr_cl30_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 30 +with rel_bixu30_wayG_upd select + congr_cl30_wG_d(1) <= (congr_cl30_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayG_upd select + congr_cl30_wG_d(2) <= (congr_cl30_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayG_upd select + congr_cl30_wG_d(3) <= (congr_cl30_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayG_upd select + congr_cl30_wG_d(4) <= (congr_cl30_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayG_upd select + congr_cl30_wG_d(5) <= (congr_cl30_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 31 +with rel_bixu31_wayG_upd select + congr_cl31_wG_d(0) <= (congr_cl31_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 31 +with rel_bixu31_wayG_upd select + congr_cl31_wG_d(1) <= (congr_cl31_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayG_upd select + congr_cl31_wG_d(2) <= (congr_cl31_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayG_upd select + congr_cl31_wG_d(3) <= (congr_cl31_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayG_upd select + congr_cl31_wG_d(4) <= (congr_cl31_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayG_upd select + congr_cl31_wG_d(5) <= (congr_cl31_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Write Select for WayH +-- WayH Valid Bit Update for Congruence Class 0 +with rel_bixu0_wayH_upd select + congr_cl0_wH_d(0) <= (congr_cl0_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 0 +with rel_bixu0_wayH_upd select + congr_cl0_wH_d(1) <= (congr_cl0_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayH_upd select + congr_cl0_wH_d(2) <= (congr_cl0_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayH_upd select + congr_cl0_wH_d(3) <= (congr_cl0_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayH_upd select + congr_cl0_wH_d(4) <= (congr_cl0_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayH_upd select + congr_cl0_wH_d(5) <= (congr_cl0_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 1 +with rel_bixu1_wayH_upd select + congr_cl1_wH_d(0) <= (congr_cl1_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 1 +with rel_bixu1_wayH_upd select + congr_cl1_wH_d(1) <= (congr_cl1_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayH_upd select + congr_cl1_wH_d(2) <= (congr_cl1_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayH_upd select + congr_cl1_wH_d(3) <= (congr_cl1_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayH_upd select + congr_cl1_wH_d(4) <= (congr_cl1_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayH_upd select + congr_cl1_wH_d(5) <= (congr_cl1_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 2 +with rel_bixu2_wayH_upd select + congr_cl2_wH_d(0) <= (congr_cl2_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 2 +with rel_bixu2_wayH_upd select + congr_cl2_wH_d(1) <= (congr_cl2_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayH_upd select + congr_cl2_wH_d(2) <= (congr_cl2_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayH_upd select + congr_cl2_wH_d(3) <= (congr_cl2_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayH_upd select + congr_cl2_wH_d(4) <= (congr_cl2_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayH_upd select + congr_cl2_wH_d(5) <= (congr_cl2_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 3 +with rel_bixu3_wayH_upd select + congr_cl3_wH_d(0) <= (congr_cl3_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 3 +with rel_bixu3_wayH_upd select + congr_cl3_wH_d(1) <= (congr_cl3_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayH_upd select + congr_cl3_wH_d(2) <= (congr_cl3_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayH_upd select + congr_cl3_wH_d(3) <= (congr_cl3_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayH_upd select + congr_cl3_wH_d(4) <= (congr_cl3_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayH_upd select + congr_cl3_wH_d(5) <= (congr_cl3_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 4 +with rel_bixu4_wayH_upd select + congr_cl4_wH_d(0) <= (congr_cl4_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 4 +with rel_bixu4_wayH_upd select + congr_cl4_wH_d(1) <= (congr_cl4_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayH_upd select + congr_cl4_wH_d(2) <= (congr_cl4_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayH_upd select + congr_cl4_wH_d(3) <= (congr_cl4_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayH_upd select + congr_cl4_wH_d(4) <= (congr_cl4_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayH_upd select + congr_cl4_wH_d(5) <= (congr_cl4_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 5 +with rel_bixu5_wayH_upd select + congr_cl5_wH_d(0) <= (congr_cl5_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 5 +with rel_bixu5_wayH_upd select + congr_cl5_wH_d(1) <= (congr_cl5_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayH_upd select + congr_cl5_wH_d(2) <= (congr_cl5_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayH_upd select + congr_cl5_wH_d(3) <= (congr_cl5_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayH_upd select + congr_cl5_wH_d(4) <= (congr_cl5_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayH_upd select + congr_cl5_wH_d(5) <= (congr_cl5_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 6 +with rel_bixu6_wayH_upd select + congr_cl6_wH_d(0) <= (congr_cl6_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 6 +with rel_bixu6_wayH_upd select + congr_cl6_wH_d(1) <= (congr_cl6_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayH_upd select + congr_cl6_wH_d(2) <= (congr_cl6_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayH_upd select + congr_cl6_wH_d(3) <= (congr_cl6_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayH_upd select + congr_cl6_wH_d(4) <= (congr_cl6_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayH_upd select + congr_cl6_wH_d(5) <= (congr_cl6_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 7 +with rel_bixu7_wayH_upd select + congr_cl7_wH_d(0) <= (congr_cl7_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 7 +with rel_bixu7_wayH_upd select + congr_cl7_wH_d(1) <= (congr_cl7_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayH_upd select + congr_cl7_wH_d(2) <= (congr_cl7_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayH_upd select + congr_cl7_wH_d(3) <= (congr_cl7_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayH_upd select + congr_cl7_wH_d(4) <= (congr_cl7_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayH_upd select + congr_cl7_wH_d(5) <= (congr_cl7_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 8 +with rel_bixu8_wayH_upd select + congr_cl8_wH_d(0) <= (congr_cl8_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 8 +with rel_bixu8_wayH_upd select + congr_cl8_wH_d(1) <= (congr_cl8_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayH_upd select + congr_cl8_wH_d(2) <= (congr_cl8_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayH_upd select + congr_cl8_wH_d(3) <= (congr_cl8_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayH_upd select + congr_cl8_wH_d(4) <= (congr_cl8_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayH_upd select + congr_cl8_wH_d(5) <= (congr_cl8_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 9 +with rel_bixu9_wayH_upd select + congr_cl9_wH_d(0) <= (congr_cl9_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 9 +with rel_bixu9_wayH_upd select + congr_cl9_wH_d(1) <= (congr_cl9_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayH_upd select + congr_cl9_wH_d(2) <= (congr_cl9_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayH_upd select + congr_cl9_wH_d(3) <= (congr_cl9_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayH_upd select + congr_cl9_wH_d(4) <= (congr_cl9_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayH_upd select + congr_cl9_wH_d(5) <= (congr_cl9_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 10 +with rel_bixu10_wayH_upd select + congr_cl10_wH_d(0) <= (congr_cl10_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 10 +with rel_bixu10_wayH_upd select + congr_cl10_wH_d(1) <= (congr_cl10_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayH_upd select + congr_cl10_wH_d(2) <= (congr_cl10_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayH_upd select + congr_cl10_wH_d(3) <= (congr_cl10_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayH_upd select + congr_cl10_wH_d(4) <= (congr_cl10_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayH_upd select + congr_cl10_wH_d(5) <= (congr_cl10_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 11 +with rel_bixu11_wayH_upd select + congr_cl11_wH_d(0) <= (congr_cl11_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 11 +with rel_bixu11_wayH_upd select + congr_cl11_wH_d(1) <= (congr_cl11_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayH_upd select + congr_cl11_wH_d(2) <= (congr_cl11_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayH_upd select + congr_cl11_wH_d(3) <= (congr_cl11_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayH_upd select + congr_cl11_wH_d(4) <= (congr_cl11_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayH_upd select + congr_cl11_wH_d(5) <= (congr_cl11_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 12 +with rel_bixu12_wayH_upd select + congr_cl12_wH_d(0) <= (congr_cl12_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 12 +with rel_bixu12_wayH_upd select + congr_cl12_wH_d(1) <= (congr_cl12_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayH_upd select + congr_cl12_wH_d(2) <= (congr_cl12_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayH_upd select + congr_cl12_wH_d(3) <= (congr_cl12_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayH_upd select + congr_cl12_wH_d(4) <= (congr_cl12_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayH_upd select + congr_cl12_wH_d(5) <= (congr_cl12_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 13 +with rel_bixu13_wayH_upd select + congr_cl13_wH_d(0) <= (congr_cl13_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 13 +with rel_bixu13_wayH_upd select + congr_cl13_wH_d(1) <= (congr_cl13_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayH_upd select + congr_cl13_wH_d(2) <= (congr_cl13_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayH_upd select + congr_cl13_wH_d(3) <= (congr_cl13_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayH_upd select + congr_cl13_wH_d(4) <= (congr_cl13_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayH_upd select + congr_cl13_wH_d(5) <= (congr_cl13_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 14 +with rel_bixu14_wayH_upd select + congr_cl14_wH_d(0) <= (congr_cl14_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 14 +with rel_bixu14_wayH_upd select + congr_cl14_wH_d(1) <= (congr_cl14_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayH_upd select + congr_cl14_wH_d(2) <= (congr_cl14_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayH_upd select + congr_cl14_wH_d(3) <= (congr_cl14_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayH_upd select + congr_cl14_wH_d(4) <= (congr_cl14_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayH_upd select + congr_cl14_wH_d(5) <= (congr_cl14_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 15 +with rel_bixu15_wayH_upd select + congr_cl15_wH_d(0) <= (congr_cl15_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 15 +with rel_bixu15_wayH_upd select + congr_cl15_wH_d(1) <= (congr_cl15_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayH_upd select + congr_cl15_wH_d(2) <= (congr_cl15_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayH_upd select + congr_cl15_wH_d(3) <= (congr_cl15_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayH_upd select + congr_cl15_wH_d(4) <= (congr_cl15_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayH_upd select + congr_cl15_wH_d(5) <= (congr_cl15_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 16 +with rel_bixu16_wayH_upd select + congr_cl16_wH_d(0) <= (congr_cl16_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 16 +with rel_bixu16_wayH_upd select + congr_cl16_wH_d(1) <= (congr_cl16_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayH_upd select + congr_cl16_wH_d(2) <= (congr_cl16_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayH_upd select + congr_cl16_wH_d(3) <= (congr_cl16_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayH_upd select + congr_cl16_wH_d(4) <= (congr_cl16_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayH_upd select + congr_cl16_wH_d(5) <= (congr_cl16_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 17 +with rel_bixu17_wayH_upd select + congr_cl17_wH_d(0) <= (congr_cl17_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 17 +with rel_bixu17_wayH_upd select + congr_cl17_wH_d(1) <= (congr_cl17_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayH_upd select + congr_cl17_wH_d(2) <= (congr_cl17_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayH_upd select + congr_cl17_wH_d(3) <= (congr_cl17_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayH_upd select + congr_cl17_wH_d(4) <= (congr_cl17_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayH_upd select + congr_cl17_wH_d(5) <= (congr_cl17_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 18 +with rel_bixu18_wayH_upd select + congr_cl18_wH_d(0) <= (congr_cl18_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 18 +with rel_bixu18_wayH_upd select + congr_cl18_wH_d(1) <= (congr_cl18_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayH_upd select + congr_cl18_wH_d(2) <= (congr_cl18_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayH_upd select + congr_cl18_wH_d(3) <= (congr_cl18_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayH_upd select + congr_cl18_wH_d(4) <= (congr_cl18_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayH_upd select + congr_cl18_wH_d(5) <= (congr_cl18_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 19 +with rel_bixu19_wayH_upd select + congr_cl19_wH_d(0) <= (congr_cl19_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 19 +with rel_bixu19_wayH_upd select + congr_cl19_wH_d(1) <= (congr_cl19_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayH_upd select + congr_cl19_wH_d(2) <= (congr_cl19_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayH_upd select + congr_cl19_wH_d(3) <= (congr_cl19_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayH_upd select + congr_cl19_wH_d(4) <= (congr_cl19_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayH_upd select + congr_cl19_wH_d(5) <= (congr_cl19_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 20 +with rel_bixu20_wayH_upd select + congr_cl20_wH_d(0) <= (congr_cl20_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 20 +with rel_bixu20_wayH_upd select + congr_cl20_wH_d(1) <= (congr_cl20_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayH_upd select + congr_cl20_wH_d(2) <= (congr_cl20_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayH_upd select + congr_cl20_wH_d(3) <= (congr_cl20_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayH_upd select + congr_cl20_wH_d(4) <= (congr_cl20_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayH_upd select + congr_cl20_wH_d(5) <= (congr_cl20_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 21 +with rel_bixu21_wayH_upd select + congr_cl21_wH_d(0) <= (congr_cl21_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 21 +with rel_bixu21_wayH_upd select + congr_cl21_wH_d(1) <= (congr_cl21_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayH_upd select + congr_cl21_wH_d(2) <= (congr_cl21_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayH_upd select + congr_cl21_wH_d(3) <= (congr_cl21_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayH_upd select + congr_cl21_wH_d(4) <= (congr_cl21_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayH_upd select + congr_cl21_wH_d(5) <= (congr_cl21_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 22 +with rel_bixu22_wayH_upd select + congr_cl22_wH_d(0) <= (congr_cl22_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 22 +with rel_bixu22_wayH_upd select + congr_cl22_wH_d(1) <= (congr_cl22_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayH_upd select + congr_cl22_wH_d(2) <= (congr_cl22_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayH_upd select + congr_cl22_wH_d(3) <= (congr_cl22_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayH_upd select + congr_cl22_wH_d(4) <= (congr_cl22_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayH_upd select + congr_cl22_wH_d(5) <= (congr_cl22_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 23 +with rel_bixu23_wayH_upd select + congr_cl23_wH_d(0) <= (congr_cl23_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 23 +with rel_bixu23_wayH_upd select + congr_cl23_wH_d(1) <= (congr_cl23_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayH_upd select + congr_cl23_wH_d(2) <= (congr_cl23_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayH_upd select + congr_cl23_wH_d(3) <= (congr_cl23_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayH_upd select + congr_cl23_wH_d(4) <= (congr_cl23_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayH_upd select + congr_cl23_wH_d(5) <= (congr_cl23_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 24 +with rel_bixu24_wayH_upd select + congr_cl24_wH_d(0) <= (congr_cl24_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 24 +with rel_bixu24_wayH_upd select + congr_cl24_wH_d(1) <= (congr_cl24_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayH_upd select + congr_cl24_wH_d(2) <= (congr_cl24_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayH_upd select + congr_cl24_wH_d(3) <= (congr_cl24_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayH_upd select + congr_cl24_wH_d(4) <= (congr_cl24_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayH_upd select + congr_cl24_wH_d(5) <= (congr_cl24_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 25 +with rel_bixu25_wayH_upd select + congr_cl25_wH_d(0) <= (congr_cl25_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 25 +with rel_bixu25_wayH_upd select + congr_cl25_wH_d(1) <= (congr_cl25_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayH_upd select + congr_cl25_wH_d(2) <= (congr_cl25_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayH_upd select + congr_cl25_wH_d(3) <= (congr_cl25_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayH_upd select + congr_cl25_wH_d(4) <= (congr_cl25_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayH_upd select + congr_cl25_wH_d(5) <= (congr_cl25_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 26 +with rel_bixu26_wayH_upd select + congr_cl26_wH_d(0) <= (congr_cl26_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 26 +with rel_bixu26_wayH_upd select + congr_cl26_wH_d(1) <= (congr_cl26_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayH_upd select + congr_cl26_wH_d(2) <= (congr_cl26_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayH_upd select + congr_cl26_wH_d(3) <= (congr_cl26_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayH_upd select + congr_cl26_wH_d(4) <= (congr_cl26_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayH_upd select + congr_cl26_wH_d(5) <= (congr_cl26_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 27 +with rel_bixu27_wayH_upd select + congr_cl27_wH_d(0) <= (congr_cl27_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 27 +with rel_bixu27_wayH_upd select + congr_cl27_wH_d(1) <= (congr_cl27_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayH_upd select + congr_cl27_wH_d(2) <= (congr_cl27_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayH_upd select + congr_cl27_wH_d(3) <= (congr_cl27_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayH_upd select + congr_cl27_wH_d(4) <= (congr_cl27_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayH_upd select + congr_cl27_wH_d(5) <= (congr_cl27_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 28 +with rel_bixu28_wayH_upd select + congr_cl28_wH_d(0) <= (congr_cl28_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 28 +with rel_bixu28_wayH_upd select + congr_cl28_wH_d(1) <= (congr_cl28_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayH_upd select + congr_cl28_wH_d(2) <= (congr_cl28_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayH_upd select + congr_cl28_wH_d(3) <= (congr_cl28_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayH_upd select + congr_cl28_wH_d(4) <= (congr_cl28_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayH_upd select + congr_cl28_wH_d(5) <= (congr_cl28_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 29 +with rel_bixu29_wayH_upd select + congr_cl29_wH_d(0) <= (congr_cl29_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 29 +with rel_bixu29_wayH_upd select + congr_cl29_wH_d(1) <= (congr_cl29_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayH_upd select + congr_cl29_wH_d(2) <= (congr_cl29_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayH_upd select + congr_cl29_wH_d(3) <= (congr_cl29_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayH_upd select + congr_cl29_wH_d(4) <= (congr_cl29_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayH_upd select + congr_cl29_wH_d(5) <= (congr_cl29_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 30 +with rel_bixu30_wayH_upd select + congr_cl30_wH_d(0) <= (congr_cl30_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 30 +with rel_bixu30_wayH_upd select + congr_cl30_wH_d(1) <= (congr_cl30_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayH_upd select + congr_cl30_wH_d(2) <= (congr_cl30_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayH_upd select + congr_cl30_wH_d(3) <= (congr_cl30_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayH_upd select + congr_cl30_wH_d(4) <= (congr_cl30_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayH_upd select + congr_cl30_wH_d(5) <= (congr_cl30_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 31 +with rel_bixu31_wayH_upd select + congr_cl31_wH_d(0) <= (congr_cl31_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 31 +with rel_bixu31_wayH_upd select + congr_cl31_wH_d(1) <= (congr_cl31_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayH_upd select + congr_cl31_wH_d(2) <= (congr_cl31_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayH_upd select + congr_cl31_wH_d(3) <= (congr_cl31_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayH_upd select + congr_cl31_wH_d(4) <= (congr_cl31_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayH_upd select + congr_cl31_wH_d(5) <= (congr_cl31_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Update Watch Lost State Bits per thread +with stm_upd_watchlost_tid0 select + stm_watchlost(0) <= stm_watchlost_state_q(0) when "00", + binv5_ex5_lost_watch_upd(0) when "01", + rel_lost_watch_upd_q(0) when others; +stm_upd_watchlost_tid0 <= rel_watchlost_upd(0) & ex5_watchlost_upd(0); +with stm_upd_watchlost_tid1 select + stm_watchlost(1) <= stm_watchlost_state_q(1) when "00", + binv5_ex5_lost_watch_upd(1) when "01", + rel_lost_watch_upd_q(1) when others; +stm_upd_watchlost_tid1 <= rel_watchlost_upd(1) & ex5_watchlost_upd(1); +with stm_upd_watchlost_tid2 select + stm_watchlost(2) <= stm_watchlost_state_q(2) when "00", + binv5_ex5_lost_watch_upd(2) when "01", + rel_lost_watch_upd_q(2) when others; +stm_upd_watchlost_tid2 <= rel_watchlost_upd(2) & ex5_watchlost_upd(2); +with stm_upd_watchlost_tid3 select + stm_watchlost(3) <= stm_watchlost_state_q(3) when "00", + binv5_ex5_lost_watch_upd(3) when "01", + rel_lost_watch_upd_q(3) when others; +stm_upd_watchlost_tid3 <= rel_watchlost_upd(3) & ex5_watchlost_upd(3); +rel_watchlost_upd <= rel_lost_watch_upd_q; +ex5_watchlost_upd <= gate(ex5_watchlost_set_q, p0_wren_d) or binv5_inval_watch_val_q or dci_watch_lost; +binv5_ex5_lost_watch_upd <= ex5_lost_watch_upd_q or binv5_inval_watch_val_q or dci_watch_lost; +-- Watch Lost Bits +stm_watchlost_state_d <= stm_watchlost; +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Spare Latches +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +my_spare0_latches_d <= not my_spare0_latches_q; + +rel4_l1dump_val_q <= not my_spare1_latches_q(0); +my_spare1_latches_d(0) <= rel3_l1dump_val; +my_spare1_latches_d(1 TO 15) <= not my_spare1_latches_q(1 to 15); + +-- #################################################### +-- Outputs +-- #################################################### +ex4_way_a_hit <= ex4_way_hit_q(0); +ex4_way_b_hit <= ex4_way_hit_q(1); +ex4_way_c_hit <= ex4_way_hit_q(2); +ex4_way_d_hit <= ex4_way_hit_q(3); +ex4_way_e_hit <= ex4_way_hit_q(4); +ex4_way_f_hit <= ex4_way_hit_q(5); +ex4_way_g_hit <= ex4_way_hit_q(6); +ex4_way_h_hit <= ex4_way_hit_q(7); +ex4_way_a_dir <= ex4_wayA_val_q; +ex4_way_b_dir <= ex4_wayB_val_q; +ex4_way_c_dir <= ex4_wayC_val_q; +ex4_way_d_dir <= ex4_wayD_val_q; +ex4_way_e_dir <= ex4_wayE_val_q; +ex4_way_f_dir <= ex4_wayF_val_q; +ex4_way_g_dir <= ex4_wayG_val_q; +ex4_way_h_dir <= ex4_wayH_val_q; +ex4_ldq_full_flush <= not ex4_ldq_full_flush_b_q; +ex4_snd_ld_l2 <= not ex4_snd_ld_l2_q; +dcarr_up_way_addr <= dcarr_up_way_addr_q; +pe_recov_begin <= not dcpar_err_rec_inprog; +lsu_xu_ex5_cr_rslt <= ex5_cr_watch_q; +rel_way_val_a <= rel_wayA_val(0); +rel_way_lock_a <= rel_wayA_val(1); +rel_way_val_b <= rel_wayB_val(0); +rel_way_lock_b <= rel_wayB_val(1); +rel_way_val_c <= rel_wayC_val(0); +rel_way_lock_c <= rel_wayC_val(1); +rel_way_val_d <= rel_wayD_val(0); +rel_way_lock_d <= rel_wayD_val(1); +rel_way_val_e <= rel_wayE_val(0); +rel_way_lock_e <= rel_wayE_val(1); +rel_way_val_f <= rel_wayF_val(0); +rel_way_lock_f <= rel_wayF_val(1); +rel_way_val_g <= rel_wayG_val(0); +rel_way_lock_g <= rel_wayG_val(1); +rel_way_val_h <= rel_wayH_val(0); +rel_way_lock_h <= rel_wayH_val(1); +-- Performance Events +lsu_xu_perf_events <= lost_watch_inter_thrd_q & lost_watch_evict_val_q & lost_watch_binv & perf_lsu_evnts_q; +-- Parity Error Detected +ex3_dir_perr_det <= ex3_dir_perr_val; +-- Directory MultiHit Detected +ex4_dir_multihit_det <= ex4_dir_multihit_val; +ex4_n_lsu_ddmh_flush <= not ex4_n_lsu_ddmh_flush_b_q; +-- DCTB ST LS instruction colliding with reload clear to same congruence class +ex2_lockwatchSet_rel_coll <= rel1_val and (ex2_lock_set or ex2_ldawx_instr) and (rel_congr_cl_q = ex2_congr_cl_q); +-- Watch clear all in pipe flushing other threads in pipe +ex3_wclr_all_flush <= ex3_wclr_all_upd_q and fxu_pipe_val; +-- Debug Data +dc_val_dbg_data <= ex4_wayA_val_q & ex4_wayB_val_q & ex4_wayC_val_q & ex4_wayD_val_q & + ex4_wayE_val_q & ex4_wayF_val_q & ex4_wayG_val_q & ex4_wayH_val_q & + rel_wayA_val_stg_q & rel_wayB_val_stg_q & rel_wayC_val_stg_q & rel_wayD_val_stg_q & + rel_wayE_val_stg_q & rel_wayF_val_stg_q & rel_wayG_val_stg_q & rel_wayH_val_stg_q & + flush_wayA_data_q & flush_wayB_data_q & flush_wayC_data_q & flush_wayD_data_q & + flush_wayE_data_q & flush_wayF_data_q & flush_wayG_data_q & flush_wayH_data_q & + reload_wayA_data_q & reload_wayB_data_q & reload_wayC_data_q & reload_wayD_data_q & + reload_wayE_data_q & reload_wayF_data_q & reload_wayG_data_q & reload_wayH_data_q & + binv_wayA_upd2_q & binv_wayB_upd2_q & binv_wayC_upd2_q & binv_wayD_upd2_q & + binv_wayE_upd2_q & binv_wayF_upd2_q & binv_wayG_upd2_q & binv_wayH_upd2_q & + reload_wayA_upd2_q & reload_wayB_upd2_q & reload_wayC_upd2_q & reload_wayD_upd2_q & + reload_wayE_upd2_q & reload_wayF_upd2_q & reload_wayG_upd2_q & reload_wayH_upd2_q & + ex4_way_hit_q & ex4_congr_cl_q & rel24_congr_cl_q & ex4_instr_enc_q & + rel24_wayA_byp_sel & rel24_wayB_byp_sel & rel24_wayC_byp_sel & rel24_wayD_byp_sel & + rel24_wayE_byp_sel & rel24_wayF_byp_sel & rel24_wayG_byp_sel & rel24_wayH_byp_sel & + ex4_wayA_byp_sel & ex4_wayB_byp_sel & ex4_wayC_byp_sel & ex4_wayD_byp_sel & + ex4_wayE_byp_sel & ex4_wayF_byp_sel & ex4_wayG_byp_sel & ex4_wayH_byp_sel & + ex4_dir_multihit_val & ex4_dir_err_val_q & rel_lost_watch_upd_q & stm_watchlost_state_q & + rel_lock_set_q & rel_watch_set_q & rel_binv_stg4_q & rel4_recirc_val & + ex7_ld_par_err_q & ex9_ld_par_err_q & rel_in_progress_q & dcpar_err_ind_sel_q & + dcpar_err_cntr_q & dcpar_err_push_queue_q & dcpar_err_way_q & dcpar_err_stg2_q & + binv4_ex4_xuop_upd_q; +-- SPR Status +lsu_xu_spr_xucr0_cslc_xuop <= xucr0_cslc_xuop_q; +lsu_xu_spr_xucr0_cslc_binv <= xucr0_cslc_binv_q; +-- #################################################### +-- Directory Valid Bit Registers +-- #################################################### +-- Congruence Class 0 Way A Register +congr_cl0_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl0_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl0_wA_offset to congr_cl0_wA_offset + congr_cl0_wA_d'length-1), + scout => sov(congr_cl0_wA_offset to congr_cl0_wA_offset + congr_cl0_wA_d'length-1), + din => congr_cl0_wA_d, + dout => congr_cl0_wA_q); +-- Congruence Class 0 Way B Register +congr_cl0_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl0_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl0_wB_offset to congr_cl0_wB_offset + congr_cl0_wB_d'length-1), + scout => sov(congr_cl0_wB_offset to congr_cl0_wB_offset + congr_cl0_wB_d'length-1), + din => congr_cl0_wB_d, + dout => congr_cl0_wB_q); +-- Congruence Class 0 Way C Register +congr_cl0_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl0_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl0_wC_offset to congr_cl0_wC_offset + congr_cl0_wC_d'length-1), + scout => sov(congr_cl0_wC_offset to congr_cl0_wC_offset + congr_cl0_wC_d'length-1), + din => congr_cl0_wC_d, + dout => congr_cl0_wC_q); +-- Congruence Class 0 Way D Register +congr_cl0_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl0_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl0_wD_offset to congr_cl0_wD_offset + congr_cl0_wD_d'length-1), + scout => sov(congr_cl0_wD_offset to congr_cl0_wD_offset + congr_cl0_wD_d'length-1), + din => congr_cl0_wD_d, + dout => congr_cl0_wD_q); +-- Congruence Class 0 Way E Register +congr_cl0_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl0_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl0_wE_offset to congr_cl0_wE_offset + congr_cl0_wE_d'length-1), + scout => sov(congr_cl0_wE_offset to congr_cl0_wE_offset + congr_cl0_wE_d'length-1), + din => congr_cl0_wE_d, + dout => congr_cl0_wE_q); +-- Congruence Class 0 Way F Register +congr_cl0_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl0_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl0_wF_offset to congr_cl0_wF_offset + congr_cl0_wF_d'length-1), + scout => sov(congr_cl0_wF_offset to congr_cl0_wF_offset + congr_cl0_wF_d'length-1), + din => congr_cl0_wF_d, + dout => congr_cl0_wF_q); +-- Congruence Class 0 Way G Register +congr_cl0_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl0_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl0_wG_offset to congr_cl0_wG_offset + congr_cl0_wG_d'length-1), + scout => sov(congr_cl0_wG_offset to congr_cl0_wG_offset + congr_cl0_wG_d'length-1), + din => congr_cl0_wG_d, + dout => congr_cl0_wG_q); +-- Congruence Class 0 Way H Register +congr_cl0_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl0_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl0_wH_offset to congr_cl0_wH_offset + congr_cl0_wH_d'length-1), + scout => sov(congr_cl0_wH_offset to congr_cl0_wH_offset + congr_cl0_wH_d'length-1), + din => congr_cl0_wH_d, + dout => congr_cl0_wH_q); +-- Congruence Class 1 Way A Register +congr_cl1_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl1_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl1_wA_offset to congr_cl1_wA_offset + congr_cl1_wA_d'length-1), + scout => sov(congr_cl1_wA_offset to congr_cl1_wA_offset + congr_cl1_wA_d'length-1), + din => congr_cl1_wA_d, + dout => congr_cl1_wA_q); +-- Congruence Class 1 Way B Register +congr_cl1_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl1_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl1_wB_offset to congr_cl1_wB_offset + congr_cl1_wB_d'length-1), + scout => sov(congr_cl1_wB_offset to congr_cl1_wB_offset + congr_cl1_wB_d'length-1), + din => congr_cl1_wB_d, + dout => congr_cl1_wB_q); +-- Congruence Class 1 Way C Register +congr_cl1_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl1_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl1_wC_offset to congr_cl1_wC_offset + congr_cl1_wC_d'length-1), + scout => sov(congr_cl1_wC_offset to congr_cl1_wC_offset + congr_cl1_wC_d'length-1), + din => congr_cl1_wC_d, + dout => congr_cl1_wC_q); +-- Congruence Class 1 Way D Register +congr_cl1_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl1_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl1_wD_offset to congr_cl1_wD_offset + congr_cl1_wD_d'length-1), + scout => sov(congr_cl1_wD_offset to congr_cl1_wD_offset + congr_cl1_wD_d'length-1), + din => congr_cl1_wD_d, + dout => congr_cl1_wD_q); +-- Congruence Class 1 Way E Register +congr_cl1_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl1_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl1_wE_offset to congr_cl1_wE_offset + congr_cl1_wE_d'length-1), + scout => sov(congr_cl1_wE_offset to congr_cl1_wE_offset + congr_cl1_wE_d'length-1), + din => congr_cl1_wE_d, + dout => congr_cl1_wE_q); +-- Congruence Class 1 Way F Register +congr_cl1_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl1_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl1_wF_offset to congr_cl1_wF_offset + congr_cl1_wF_d'length-1), + scout => sov(congr_cl1_wF_offset to congr_cl1_wF_offset + congr_cl1_wF_d'length-1), + din => congr_cl1_wF_d, + dout => congr_cl1_wF_q); +-- Congruence Class 1 Way G Register +congr_cl1_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl1_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl1_wG_offset to congr_cl1_wG_offset + congr_cl1_wG_d'length-1), + scout => sov(congr_cl1_wG_offset to congr_cl1_wG_offset + congr_cl1_wG_d'length-1), + din => congr_cl1_wG_d, + dout => congr_cl1_wG_q); +-- Congruence Class 1 Way H Register +congr_cl1_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl1_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl1_wH_offset to congr_cl1_wH_offset + congr_cl1_wH_d'length-1), + scout => sov(congr_cl1_wH_offset to congr_cl1_wH_offset + congr_cl1_wH_d'length-1), + din => congr_cl1_wH_d, + dout => congr_cl1_wH_q); +-- Congruence Class 2 Way A Register +congr_cl2_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl2_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl2_wA_offset to congr_cl2_wA_offset + congr_cl2_wA_d'length-1), + scout => sov(congr_cl2_wA_offset to congr_cl2_wA_offset + congr_cl2_wA_d'length-1), + din => congr_cl2_wA_d, + dout => congr_cl2_wA_q); +-- Congruence Class 2 Way B Register +congr_cl2_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl2_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl2_wB_offset to congr_cl2_wB_offset + congr_cl2_wB_d'length-1), + scout => sov(congr_cl2_wB_offset to congr_cl2_wB_offset + congr_cl2_wB_d'length-1), + din => congr_cl2_wB_d, + dout => congr_cl2_wB_q); +-- Congruence Class 2 Way C Register +congr_cl2_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl2_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl2_wC_offset to congr_cl2_wC_offset + congr_cl2_wC_d'length-1), + scout => sov(congr_cl2_wC_offset to congr_cl2_wC_offset + congr_cl2_wC_d'length-1), + din => congr_cl2_wC_d, + dout => congr_cl2_wC_q); +-- Congruence Class 2 Way D Register +congr_cl2_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl2_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl2_wD_offset to congr_cl2_wD_offset + congr_cl2_wD_d'length-1), + scout => sov(congr_cl2_wD_offset to congr_cl2_wD_offset + congr_cl2_wD_d'length-1), + din => congr_cl2_wD_d, + dout => congr_cl2_wD_q); +-- Congruence Class 2 Way E Register +congr_cl2_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl2_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl2_wE_offset to congr_cl2_wE_offset + congr_cl2_wE_d'length-1), + scout => sov(congr_cl2_wE_offset to congr_cl2_wE_offset + congr_cl2_wE_d'length-1), + din => congr_cl2_wE_d, + dout => congr_cl2_wE_q); +-- Congruence Class 2 Way F Register +congr_cl2_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl2_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl2_wF_offset to congr_cl2_wF_offset + congr_cl2_wF_d'length-1), + scout => sov(congr_cl2_wF_offset to congr_cl2_wF_offset + congr_cl2_wF_d'length-1), + din => congr_cl2_wF_d, + dout => congr_cl2_wF_q); +-- Congruence Class 2 Way G Register +congr_cl2_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl2_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl2_wG_offset to congr_cl2_wG_offset + congr_cl2_wG_d'length-1), + scout => sov(congr_cl2_wG_offset to congr_cl2_wG_offset + congr_cl2_wG_d'length-1), + din => congr_cl2_wG_d, + dout => congr_cl2_wG_q); +-- Congruence Class 2 Way H Register +congr_cl2_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl2_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl2_wH_offset to congr_cl2_wH_offset + congr_cl2_wH_d'length-1), + scout => sov(congr_cl2_wH_offset to congr_cl2_wH_offset + congr_cl2_wH_d'length-1), + din => congr_cl2_wH_d, + dout => congr_cl2_wH_q); +-- Congruence Class 3 Way A Register +congr_cl3_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl3_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl3_wA_offset to congr_cl3_wA_offset + congr_cl3_wA_d'length-1), + scout => sov(congr_cl3_wA_offset to congr_cl3_wA_offset + congr_cl3_wA_d'length-1), + din => congr_cl3_wA_d, + dout => congr_cl3_wA_q); +-- Congruence Class 3 Way B Register +congr_cl3_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl3_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl3_wB_offset to congr_cl3_wB_offset + congr_cl3_wB_d'length-1), + scout => sov(congr_cl3_wB_offset to congr_cl3_wB_offset + congr_cl3_wB_d'length-1), + din => congr_cl3_wB_d, + dout => congr_cl3_wB_q); +-- Congruence Class 3 Way C Register +congr_cl3_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl3_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl3_wC_offset to congr_cl3_wC_offset + congr_cl3_wC_d'length-1), + scout => sov(congr_cl3_wC_offset to congr_cl3_wC_offset + congr_cl3_wC_d'length-1), + din => congr_cl3_wC_d, + dout => congr_cl3_wC_q); +-- Congruence Class 3 Way D Register +congr_cl3_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl3_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl3_wD_offset to congr_cl3_wD_offset + congr_cl3_wD_d'length-1), + scout => sov(congr_cl3_wD_offset to congr_cl3_wD_offset + congr_cl3_wD_d'length-1), + din => congr_cl3_wD_d, + dout => congr_cl3_wD_q); +-- Congruence Class 3 Way E Register +congr_cl3_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl3_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl3_wE_offset to congr_cl3_wE_offset + congr_cl3_wE_d'length-1), + scout => sov(congr_cl3_wE_offset to congr_cl3_wE_offset + congr_cl3_wE_d'length-1), + din => congr_cl3_wE_d, + dout => congr_cl3_wE_q); +-- Congruence Class 3 Way F Register +congr_cl3_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl3_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl3_wF_offset to congr_cl3_wF_offset + congr_cl3_wF_d'length-1), + scout => sov(congr_cl3_wF_offset to congr_cl3_wF_offset + congr_cl3_wF_d'length-1), + din => congr_cl3_wF_d, + dout => congr_cl3_wF_q); +-- Congruence Class 3 Way G Register +congr_cl3_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl3_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl3_wG_offset to congr_cl3_wG_offset + congr_cl3_wG_d'length-1), + scout => sov(congr_cl3_wG_offset to congr_cl3_wG_offset + congr_cl3_wG_d'length-1), + din => congr_cl3_wG_d, + dout => congr_cl3_wG_q); +-- Congruence Class 3 Way H Register +congr_cl3_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl3_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl3_wH_offset to congr_cl3_wH_offset + congr_cl3_wH_d'length-1), + scout => sov(congr_cl3_wH_offset to congr_cl3_wH_offset + congr_cl3_wH_d'length-1), + din => congr_cl3_wH_d, + dout => congr_cl3_wH_q); +-- Congruence Class 4 Way A Register +congr_cl4_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl4_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl4_wA_offset to congr_cl4_wA_offset + congr_cl4_wA_d'length-1), + scout => sov(congr_cl4_wA_offset to congr_cl4_wA_offset + congr_cl4_wA_d'length-1), + din => congr_cl4_wA_d, + dout => congr_cl4_wA_q); +-- Congruence Class 4 Way B Register +congr_cl4_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl4_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl4_wB_offset to congr_cl4_wB_offset + congr_cl4_wB_d'length-1), + scout => sov(congr_cl4_wB_offset to congr_cl4_wB_offset + congr_cl4_wB_d'length-1), + din => congr_cl4_wB_d, + dout => congr_cl4_wB_q); +-- Congruence Class 4 Way C Register +congr_cl4_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl4_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl4_wC_offset to congr_cl4_wC_offset + congr_cl4_wC_d'length-1), + scout => sov(congr_cl4_wC_offset to congr_cl4_wC_offset + congr_cl4_wC_d'length-1), + din => congr_cl4_wC_d, + dout => congr_cl4_wC_q); +-- Congruence Class 4 Way D Register +congr_cl4_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl4_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl4_wD_offset to congr_cl4_wD_offset + congr_cl4_wD_d'length-1), + scout => sov(congr_cl4_wD_offset to congr_cl4_wD_offset + congr_cl4_wD_d'length-1), + din => congr_cl4_wD_d, + dout => congr_cl4_wD_q); +-- Congruence Class 4 Way E Register +congr_cl4_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl4_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl4_wE_offset to congr_cl4_wE_offset + congr_cl4_wE_d'length-1), + scout => sov(congr_cl4_wE_offset to congr_cl4_wE_offset + congr_cl4_wE_d'length-1), + din => congr_cl4_wE_d, + dout => congr_cl4_wE_q); +-- Congruence Class 4 Way F Register +congr_cl4_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl4_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl4_wF_offset to congr_cl4_wF_offset + congr_cl4_wF_d'length-1), + scout => sov(congr_cl4_wF_offset to congr_cl4_wF_offset + congr_cl4_wF_d'length-1), + din => congr_cl4_wF_d, + dout => congr_cl4_wF_q); +-- Congruence Class 4 Way G Register +congr_cl4_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl4_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl4_wG_offset to congr_cl4_wG_offset + congr_cl4_wG_d'length-1), + scout => sov(congr_cl4_wG_offset to congr_cl4_wG_offset + congr_cl4_wG_d'length-1), + din => congr_cl4_wG_d, + dout => congr_cl4_wG_q); +-- Congruence Class 4 Way H Register +congr_cl4_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl4_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl4_wH_offset to congr_cl4_wH_offset + congr_cl4_wH_d'length-1), + scout => sov(congr_cl4_wH_offset to congr_cl4_wH_offset + congr_cl4_wH_d'length-1), + din => congr_cl4_wH_d, + dout => congr_cl4_wH_q); +-- Congruence Class 5 Way A Register +congr_cl5_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl5_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl5_wA_offset to congr_cl5_wA_offset + congr_cl5_wA_d'length-1), + scout => sov(congr_cl5_wA_offset to congr_cl5_wA_offset + congr_cl5_wA_d'length-1), + din => congr_cl5_wA_d, + dout => congr_cl5_wA_q); +-- Congruence Class 5 Way B Register +congr_cl5_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl5_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl5_wB_offset to congr_cl5_wB_offset + congr_cl5_wB_d'length-1), + scout => sov(congr_cl5_wB_offset to congr_cl5_wB_offset + congr_cl5_wB_d'length-1), + din => congr_cl5_wB_d, + dout => congr_cl5_wB_q); +-- Congruence Class 5 Way C Register +congr_cl5_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl5_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl5_wC_offset to congr_cl5_wC_offset + congr_cl5_wC_d'length-1), + scout => sov(congr_cl5_wC_offset to congr_cl5_wC_offset + congr_cl5_wC_d'length-1), + din => congr_cl5_wC_d, + dout => congr_cl5_wC_q); +-- Congruence Class 5 Way D Register +congr_cl5_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl5_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl5_wD_offset to congr_cl5_wD_offset + congr_cl5_wD_d'length-1), + scout => sov(congr_cl5_wD_offset to congr_cl5_wD_offset + congr_cl5_wD_d'length-1), + din => congr_cl5_wD_d, + dout => congr_cl5_wD_q); +-- Congruence Class 5 Way E Register +congr_cl5_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl5_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl5_wE_offset to congr_cl5_wE_offset + congr_cl5_wE_d'length-1), + scout => sov(congr_cl5_wE_offset to congr_cl5_wE_offset + congr_cl5_wE_d'length-1), + din => congr_cl5_wE_d, + dout => congr_cl5_wE_q); +-- Congruence Class 5 Way F Register +congr_cl5_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl5_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl5_wF_offset to congr_cl5_wF_offset + congr_cl5_wF_d'length-1), + scout => sov(congr_cl5_wF_offset to congr_cl5_wF_offset + congr_cl5_wF_d'length-1), + din => congr_cl5_wF_d, + dout => congr_cl5_wF_q); +-- Congruence Class 5 Way G Register +congr_cl5_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl5_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl5_wG_offset to congr_cl5_wG_offset + congr_cl5_wG_d'length-1), + scout => sov(congr_cl5_wG_offset to congr_cl5_wG_offset + congr_cl5_wG_d'length-1), + din => congr_cl5_wG_d, + dout => congr_cl5_wG_q); +-- Congruence Class 5 Way H Register +congr_cl5_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl5_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl5_wH_offset to congr_cl5_wH_offset + congr_cl5_wH_d'length-1), + scout => sov(congr_cl5_wH_offset to congr_cl5_wH_offset + congr_cl5_wH_d'length-1), + din => congr_cl5_wH_d, + dout => congr_cl5_wH_q); +-- Congruence Class 6 Way A Register +congr_cl6_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl6_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl6_wA_offset to congr_cl6_wA_offset + congr_cl6_wA_d'length-1), + scout => sov(congr_cl6_wA_offset to congr_cl6_wA_offset + congr_cl6_wA_d'length-1), + din => congr_cl6_wA_d, + dout => congr_cl6_wA_q); +-- Congruence Class 6 Way B Register +congr_cl6_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl6_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl6_wB_offset to congr_cl6_wB_offset + congr_cl6_wB_d'length-1), + scout => sov(congr_cl6_wB_offset to congr_cl6_wB_offset + congr_cl6_wB_d'length-1), + din => congr_cl6_wB_d, + dout => congr_cl6_wB_q); +-- Congruence Class 6 Way C Register +congr_cl6_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl6_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl6_wC_offset to congr_cl6_wC_offset + congr_cl6_wC_d'length-1), + scout => sov(congr_cl6_wC_offset to congr_cl6_wC_offset + congr_cl6_wC_d'length-1), + din => congr_cl6_wC_d, + dout => congr_cl6_wC_q); +-- Congruence Class 6 Way D Register +congr_cl6_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl6_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl6_wD_offset to congr_cl6_wD_offset + congr_cl6_wD_d'length-1), + scout => sov(congr_cl6_wD_offset to congr_cl6_wD_offset + congr_cl6_wD_d'length-1), + din => congr_cl6_wD_d, + dout => congr_cl6_wD_q); +-- Congruence Class 6 Way E Register +congr_cl6_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl6_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl6_wE_offset to congr_cl6_wE_offset + congr_cl6_wE_d'length-1), + scout => sov(congr_cl6_wE_offset to congr_cl6_wE_offset + congr_cl6_wE_d'length-1), + din => congr_cl6_wE_d, + dout => congr_cl6_wE_q); +-- Congruence Class 6 Way F Register +congr_cl6_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl6_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl6_wF_offset to congr_cl6_wF_offset + congr_cl6_wF_d'length-1), + scout => sov(congr_cl6_wF_offset to congr_cl6_wF_offset + congr_cl6_wF_d'length-1), + din => congr_cl6_wF_d, + dout => congr_cl6_wF_q); +-- Congruence Class 6 Way G Register +congr_cl6_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl6_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl6_wG_offset to congr_cl6_wG_offset + congr_cl6_wG_d'length-1), + scout => sov(congr_cl6_wG_offset to congr_cl6_wG_offset + congr_cl6_wG_d'length-1), + din => congr_cl6_wG_d, + dout => congr_cl6_wG_q); +-- Congruence Class 6 Way H Register +congr_cl6_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl6_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl6_wH_offset to congr_cl6_wH_offset + congr_cl6_wH_d'length-1), + scout => sov(congr_cl6_wH_offset to congr_cl6_wH_offset + congr_cl6_wH_d'length-1), + din => congr_cl6_wH_d, + dout => congr_cl6_wH_q); +-- Congruence Class 7 Way A Register +congr_cl7_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl7_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl7_wA_offset to congr_cl7_wA_offset + congr_cl7_wA_d'length-1), + scout => sov(congr_cl7_wA_offset to congr_cl7_wA_offset + congr_cl7_wA_d'length-1), + din => congr_cl7_wA_d, + dout => congr_cl7_wA_q); +-- Congruence Class 7 Way B Register +congr_cl7_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl7_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl7_wB_offset to congr_cl7_wB_offset + congr_cl7_wB_d'length-1), + scout => sov(congr_cl7_wB_offset to congr_cl7_wB_offset + congr_cl7_wB_d'length-1), + din => congr_cl7_wB_d, + dout => congr_cl7_wB_q); +-- Congruence Class 7 Way C Register +congr_cl7_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl7_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl7_wC_offset to congr_cl7_wC_offset + congr_cl7_wC_d'length-1), + scout => sov(congr_cl7_wC_offset to congr_cl7_wC_offset + congr_cl7_wC_d'length-1), + din => congr_cl7_wC_d, + dout => congr_cl7_wC_q); +-- Congruence Class 7 Way D Register +congr_cl7_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl7_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl7_wD_offset to congr_cl7_wD_offset + congr_cl7_wD_d'length-1), + scout => sov(congr_cl7_wD_offset to congr_cl7_wD_offset + congr_cl7_wD_d'length-1), + din => congr_cl7_wD_d, + dout => congr_cl7_wD_q); +-- Congruence Class 7 Way E Register +congr_cl7_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl7_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl7_wE_offset to congr_cl7_wE_offset + congr_cl7_wE_d'length-1), + scout => sov(congr_cl7_wE_offset to congr_cl7_wE_offset + congr_cl7_wE_d'length-1), + din => congr_cl7_wE_d, + dout => congr_cl7_wE_q); +-- Congruence Class 7 Way F Register +congr_cl7_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl7_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl7_wF_offset to congr_cl7_wF_offset + congr_cl7_wF_d'length-1), + scout => sov(congr_cl7_wF_offset to congr_cl7_wF_offset + congr_cl7_wF_d'length-1), + din => congr_cl7_wF_d, + dout => congr_cl7_wF_q); +-- Congruence Class 7 Way G Register +congr_cl7_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl7_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl7_wG_offset to congr_cl7_wG_offset + congr_cl7_wG_d'length-1), + scout => sov(congr_cl7_wG_offset to congr_cl7_wG_offset + congr_cl7_wG_d'length-1), + din => congr_cl7_wG_d, + dout => congr_cl7_wG_q); +-- Congruence Class 7 Way H Register +congr_cl7_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl7_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl7_wH_offset to congr_cl7_wH_offset + congr_cl7_wH_d'length-1), + scout => sov(congr_cl7_wH_offset to congr_cl7_wH_offset + congr_cl7_wH_d'length-1), + din => congr_cl7_wH_d, + dout => congr_cl7_wH_q); +-- Congruence Class 8 Way A Register +congr_cl8_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl8_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl8_wA_offset to congr_cl8_wA_offset + congr_cl8_wA_d'length-1), + scout => sov(congr_cl8_wA_offset to congr_cl8_wA_offset + congr_cl8_wA_d'length-1), + din => congr_cl8_wA_d, + dout => congr_cl8_wA_q); +-- Congruence Class 8 Way B Register +congr_cl8_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl8_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl8_wB_offset to congr_cl8_wB_offset + congr_cl8_wB_d'length-1), + scout => sov(congr_cl8_wB_offset to congr_cl8_wB_offset + congr_cl8_wB_d'length-1), + din => congr_cl8_wB_d, + dout => congr_cl8_wB_q); +-- Congruence Class 8 Way C Register +congr_cl8_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl8_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl8_wC_offset to congr_cl8_wC_offset + congr_cl8_wC_d'length-1), + scout => sov(congr_cl8_wC_offset to congr_cl8_wC_offset + congr_cl8_wC_d'length-1), + din => congr_cl8_wC_d, + dout => congr_cl8_wC_q); +-- Congruence Class 8 Way D Register +congr_cl8_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl8_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl8_wD_offset to congr_cl8_wD_offset + congr_cl8_wD_d'length-1), + scout => sov(congr_cl8_wD_offset to congr_cl8_wD_offset + congr_cl8_wD_d'length-1), + din => congr_cl8_wD_d, + dout => congr_cl8_wD_q); +-- Congruence Class 8 Way E Register +congr_cl8_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl8_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl8_wE_offset to congr_cl8_wE_offset + congr_cl8_wE_d'length-1), + scout => sov(congr_cl8_wE_offset to congr_cl8_wE_offset + congr_cl8_wE_d'length-1), + din => congr_cl8_wE_d, + dout => congr_cl8_wE_q); +-- Congruence Class 8 Way F Register +congr_cl8_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl8_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl8_wF_offset to congr_cl8_wF_offset + congr_cl8_wF_d'length-1), + scout => sov(congr_cl8_wF_offset to congr_cl8_wF_offset + congr_cl8_wF_d'length-1), + din => congr_cl8_wF_d, + dout => congr_cl8_wF_q); +-- Congruence Class 8 Way G Register +congr_cl8_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl8_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl8_wG_offset to congr_cl8_wG_offset + congr_cl8_wG_d'length-1), + scout => sov(congr_cl8_wG_offset to congr_cl8_wG_offset + congr_cl8_wG_d'length-1), + din => congr_cl8_wG_d, + dout => congr_cl8_wG_q); +-- Congruence Class 8 Way H Register +congr_cl8_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl8_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl8_wH_offset to congr_cl8_wH_offset + congr_cl8_wH_d'length-1), + scout => sov(congr_cl8_wH_offset to congr_cl8_wH_offset + congr_cl8_wH_d'length-1), + din => congr_cl8_wH_d, + dout => congr_cl8_wH_q); +-- Congruence Class 9 Way A Register +congr_cl9_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl9_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl9_wA_offset to congr_cl9_wA_offset + congr_cl9_wA_d'length-1), + scout => sov(congr_cl9_wA_offset to congr_cl9_wA_offset + congr_cl9_wA_d'length-1), + din => congr_cl9_wA_d, + dout => congr_cl9_wA_q); +-- Congruence Class 9 Way B Register +congr_cl9_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl9_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl9_wB_offset to congr_cl9_wB_offset + congr_cl9_wB_d'length-1), + scout => sov(congr_cl9_wB_offset to congr_cl9_wB_offset + congr_cl9_wB_d'length-1), + din => congr_cl9_wB_d, + dout => congr_cl9_wB_q); +-- Congruence Class 9 Way C Register +congr_cl9_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl9_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl9_wC_offset to congr_cl9_wC_offset + congr_cl9_wC_d'length-1), + scout => sov(congr_cl9_wC_offset to congr_cl9_wC_offset + congr_cl9_wC_d'length-1), + din => congr_cl9_wC_d, + dout => congr_cl9_wC_q); +-- Congruence Class 9 Way D Register +congr_cl9_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl9_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl9_wD_offset to congr_cl9_wD_offset + congr_cl9_wD_d'length-1), + scout => sov(congr_cl9_wD_offset to congr_cl9_wD_offset + congr_cl9_wD_d'length-1), + din => congr_cl9_wD_d, + dout => congr_cl9_wD_q); +-- Congruence Class 9 Way E Register +congr_cl9_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl9_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl9_wE_offset to congr_cl9_wE_offset + congr_cl9_wE_d'length-1), + scout => sov(congr_cl9_wE_offset to congr_cl9_wE_offset + congr_cl9_wE_d'length-1), + din => congr_cl9_wE_d, + dout => congr_cl9_wE_q); +-- Congruence Class 9 Way F Register +congr_cl9_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl9_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl9_wF_offset to congr_cl9_wF_offset + congr_cl9_wF_d'length-1), + scout => sov(congr_cl9_wF_offset to congr_cl9_wF_offset + congr_cl9_wF_d'length-1), + din => congr_cl9_wF_d, + dout => congr_cl9_wF_q); +-- Congruence Class 9 Way G Register +congr_cl9_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl9_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl9_wG_offset to congr_cl9_wG_offset + congr_cl9_wG_d'length-1), + scout => sov(congr_cl9_wG_offset to congr_cl9_wG_offset + congr_cl9_wG_d'length-1), + din => congr_cl9_wG_d, + dout => congr_cl9_wG_q); +-- Congruence Class 9 Way H Register +congr_cl9_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl9_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl9_wH_offset to congr_cl9_wH_offset + congr_cl9_wH_d'length-1), + scout => sov(congr_cl9_wH_offset to congr_cl9_wH_offset + congr_cl9_wH_d'length-1), + din => congr_cl9_wH_d, + dout => congr_cl9_wH_q); +-- Congruence Class 10 Way A Register +congr_cl10_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl10_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl10_wA_offset to congr_cl10_wA_offset + congr_cl10_wA_d'length-1), + scout => sov(congr_cl10_wA_offset to congr_cl10_wA_offset + congr_cl10_wA_d'length-1), + din => congr_cl10_wA_d, + dout => congr_cl10_wA_q); +-- Congruence Class 10 Way B Register +congr_cl10_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl10_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl10_wB_offset to congr_cl10_wB_offset + congr_cl10_wB_d'length-1), + scout => sov(congr_cl10_wB_offset to congr_cl10_wB_offset + congr_cl10_wB_d'length-1), + din => congr_cl10_wB_d, + dout => congr_cl10_wB_q); +-- Congruence Class 10 Way C Register +congr_cl10_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl10_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl10_wC_offset to congr_cl10_wC_offset + congr_cl10_wC_d'length-1), + scout => sov(congr_cl10_wC_offset to congr_cl10_wC_offset + congr_cl10_wC_d'length-1), + din => congr_cl10_wC_d, + dout => congr_cl10_wC_q); +-- Congruence Class 10 Way D Register +congr_cl10_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl10_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl10_wD_offset to congr_cl10_wD_offset + congr_cl10_wD_d'length-1), + scout => sov(congr_cl10_wD_offset to congr_cl10_wD_offset + congr_cl10_wD_d'length-1), + din => congr_cl10_wD_d, + dout => congr_cl10_wD_q); +-- Congruence Class 10 Way E Register +congr_cl10_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl10_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl10_wE_offset to congr_cl10_wE_offset + congr_cl10_wE_d'length-1), + scout => sov(congr_cl10_wE_offset to congr_cl10_wE_offset + congr_cl10_wE_d'length-1), + din => congr_cl10_wE_d, + dout => congr_cl10_wE_q); +-- Congruence Class 10 Way F Register +congr_cl10_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl10_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl10_wF_offset to congr_cl10_wF_offset + congr_cl10_wF_d'length-1), + scout => sov(congr_cl10_wF_offset to congr_cl10_wF_offset + congr_cl10_wF_d'length-1), + din => congr_cl10_wF_d, + dout => congr_cl10_wF_q); +-- Congruence Class 10 Way G Register +congr_cl10_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl10_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl10_wG_offset to congr_cl10_wG_offset + congr_cl10_wG_d'length-1), + scout => sov(congr_cl10_wG_offset to congr_cl10_wG_offset + congr_cl10_wG_d'length-1), + din => congr_cl10_wG_d, + dout => congr_cl10_wG_q); +-- Congruence Class 10 Way H Register +congr_cl10_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl10_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl10_wH_offset to congr_cl10_wH_offset + congr_cl10_wH_d'length-1), + scout => sov(congr_cl10_wH_offset to congr_cl10_wH_offset + congr_cl10_wH_d'length-1), + din => congr_cl10_wH_d, + dout => congr_cl10_wH_q); +-- Congruence Class 11 Way A Register +congr_cl11_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl11_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl11_wA_offset to congr_cl11_wA_offset + congr_cl11_wA_d'length-1), + scout => sov(congr_cl11_wA_offset to congr_cl11_wA_offset + congr_cl11_wA_d'length-1), + din => congr_cl11_wA_d, + dout => congr_cl11_wA_q); +-- Congruence Class 11 Way B Register +congr_cl11_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl11_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl11_wB_offset to congr_cl11_wB_offset + congr_cl11_wB_d'length-1), + scout => sov(congr_cl11_wB_offset to congr_cl11_wB_offset + congr_cl11_wB_d'length-1), + din => congr_cl11_wB_d, + dout => congr_cl11_wB_q); +-- Congruence Class 11 Way C Register +congr_cl11_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl11_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl11_wC_offset to congr_cl11_wC_offset + congr_cl11_wC_d'length-1), + scout => sov(congr_cl11_wC_offset to congr_cl11_wC_offset + congr_cl11_wC_d'length-1), + din => congr_cl11_wC_d, + dout => congr_cl11_wC_q); +-- Congruence Class 11 Way D Register +congr_cl11_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl11_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl11_wD_offset to congr_cl11_wD_offset + congr_cl11_wD_d'length-1), + scout => sov(congr_cl11_wD_offset to congr_cl11_wD_offset + congr_cl11_wD_d'length-1), + din => congr_cl11_wD_d, + dout => congr_cl11_wD_q); +-- Congruence Class 11 Way E Register +congr_cl11_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl11_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl11_wE_offset to congr_cl11_wE_offset + congr_cl11_wE_d'length-1), + scout => sov(congr_cl11_wE_offset to congr_cl11_wE_offset + congr_cl11_wE_d'length-1), + din => congr_cl11_wE_d, + dout => congr_cl11_wE_q); +-- Congruence Class 11 Way F Register +congr_cl11_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl11_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl11_wF_offset to congr_cl11_wF_offset + congr_cl11_wF_d'length-1), + scout => sov(congr_cl11_wF_offset to congr_cl11_wF_offset + congr_cl11_wF_d'length-1), + din => congr_cl11_wF_d, + dout => congr_cl11_wF_q); +-- Congruence Class 11 Way G Register +congr_cl11_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl11_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl11_wG_offset to congr_cl11_wG_offset + congr_cl11_wG_d'length-1), + scout => sov(congr_cl11_wG_offset to congr_cl11_wG_offset + congr_cl11_wG_d'length-1), + din => congr_cl11_wG_d, + dout => congr_cl11_wG_q); +-- Congruence Class 11 Way H Register +congr_cl11_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl11_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl11_wH_offset to congr_cl11_wH_offset + congr_cl11_wH_d'length-1), + scout => sov(congr_cl11_wH_offset to congr_cl11_wH_offset + congr_cl11_wH_d'length-1), + din => congr_cl11_wH_d, + dout => congr_cl11_wH_q); +-- Congruence Class 12 Way A Register +congr_cl12_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl12_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl12_wA_offset to congr_cl12_wA_offset + congr_cl12_wA_d'length-1), + scout => sov(congr_cl12_wA_offset to congr_cl12_wA_offset + congr_cl12_wA_d'length-1), + din => congr_cl12_wA_d, + dout => congr_cl12_wA_q); +-- Congruence Class 12 Way B Register +congr_cl12_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl12_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl12_wB_offset to congr_cl12_wB_offset + congr_cl12_wB_d'length-1), + scout => sov(congr_cl12_wB_offset to congr_cl12_wB_offset + congr_cl12_wB_d'length-1), + din => congr_cl12_wB_d, + dout => congr_cl12_wB_q); +-- Congruence Class 12 Way C Register +congr_cl12_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl12_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl12_wC_offset to congr_cl12_wC_offset + congr_cl12_wC_d'length-1), + scout => sov(congr_cl12_wC_offset to congr_cl12_wC_offset + congr_cl12_wC_d'length-1), + din => congr_cl12_wC_d, + dout => congr_cl12_wC_q); +-- Congruence Class 12 Way D Register +congr_cl12_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl12_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl12_wD_offset to congr_cl12_wD_offset + congr_cl12_wD_d'length-1), + scout => sov(congr_cl12_wD_offset to congr_cl12_wD_offset + congr_cl12_wD_d'length-1), + din => congr_cl12_wD_d, + dout => congr_cl12_wD_q); +-- Congruence Class 12 Way E Register +congr_cl12_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl12_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl12_wE_offset to congr_cl12_wE_offset + congr_cl12_wE_d'length-1), + scout => sov(congr_cl12_wE_offset to congr_cl12_wE_offset + congr_cl12_wE_d'length-1), + din => congr_cl12_wE_d, + dout => congr_cl12_wE_q); +-- Congruence Class 12 Way F Register +congr_cl12_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl12_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl12_wF_offset to congr_cl12_wF_offset + congr_cl12_wF_d'length-1), + scout => sov(congr_cl12_wF_offset to congr_cl12_wF_offset + congr_cl12_wF_d'length-1), + din => congr_cl12_wF_d, + dout => congr_cl12_wF_q); +-- Congruence Class 12 Way G Register +congr_cl12_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl12_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl12_wG_offset to congr_cl12_wG_offset + congr_cl12_wG_d'length-1), + scout => sov(congr_cl12_wG_offset to congr_cl12_wG_offset + congr_cl12_wG_d'length-1), + din => congr_cl12_wG_d, + dout => congr_cl12_wG_q); +-- Congruence Class 12 Way H Register +congr_cl12_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl12_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl12_wH_offset to congr_cl12_wH_offset + congr_cl12_wH_d'length-1), + scout => sov(congr_cl12_wH_offset to congr_cl12_wH_offset + congr_cl12_wH_d'length-1), + din => congr_cl12_wH_d, + dout => congr_cl12_wH_q); +-- Congruence Class 13 Way A Register +congr_cl13_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl13_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl13_wA_offset to congr_cl13_wA_offset + congr_cl13_wA_d'length-1), + scout => sov(congr_cl13_wA_offset to congr_cl13_wA_offset + congr_cl13_wA_d'length-1), + din => congr_cl13_wA_d, + dout => congr_cl13_wA_q); +-- Congruence Class 13 Way B Register +congr_cl13_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl13_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl13_wB_offset to congr_cl13_wB_offset + congr_cl13_wB_d'length-1), + scout => sov(congr_cl13_wB_offset to congr_cl13_wB_offset + congr_cl13_wB_d'length-1), + din => congr_cl13_wB_d, + dout => congr_cl13_wB_q); +-- Congruence Class 13 Way C Register +congr_cl13_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl13_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl13_wC_offset to congr_cl13_wC_offset + congr_cl13_wC_d'length-1), + scout => sov(congr_cl13_wC_offset to congr_cl13_wC_offset + congr_cl13_wC_d'length-1), + din => congr_cl13_wC_d, + dout => congr_cl13_wC_q); +-- Congruence Class 13 Way D Register +congr_cl13_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl13_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl13_wD_offset to congr_cl13_wD_offset + congr_cl13_wD_d'length-1), + scout => sov(congr_cl13_wD_offset to congr_cl13_wD_offset + congr_cl13_wD_d'length-1), + din => congr_cl13_wD_d, + dout => congr_cl13_wD_q); +-- Congruence Class 13 Way E Register +congr_cl13_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl13_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl13_wE_offset to congr_cl13_wE_offset + congr_cl13_wE_d'length-1), + scout => sov(congr_cl13_wE_offset to congr_cl13_wE_offset + congr_cl13_wE_d'length-1), + din => congr_cl13_wE_d, + dout => congr_cl13_wE_q); +-- Congruence Class 13 Way F Register +congr_cl13_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl13_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl13_wF_offset to congr_cl13_wF_offset + congr_cl13_wF_d'length-1), + scout => sov(congr_cl13_wF_offset to congr_cl13_wF_offset + congr_cl13_wF_d'length-1), + din => congr_cl13_wF_d, + dout => congr_cl13_wF_q); +-- Congruence Class 13 Way G Register +congr_cl13_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl13_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl13_wG_offset to congr_cl13_wG_offset + congr_cl13_wG_d'length-1), + scout => sov(congr_cl13_wG_offset to congr_cl13_wG_offset + congr_cl13_wG_d'length-1), + din => congr_cl13_wG_d, + dout => congr_cl13_wG_q); +-- Congruence Class 13 Way H Register +congr_cl13_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl13_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl13_wH_offset to congr_cl13_wH_offset + congr_cl13_wH_d'length-1), + scout => sov(congr_cl13_wH_offset to congr_cl13_wH_offset + congr_cl13_wH_d'length-1), + din => congr_cl13_wH_d, + dout => congr_cl13_wH_q); +-- Congruence Class 14 Way A Register +congr_cl14_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl14_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl14_wA_offset to congr_cl14_wA_offset + congr_cl14_wA_d'length-1), + scout => sov(congr_cl14_wA_offset to congr_cl14_wA_offset + congr_cl14_wA_d'length-1), + din => congr_cl14_wA_d, + dout => congr_cl14_wA_q); +-- Congruence Class 14 Way B Register +congr_cl14_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl14_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl14_wB_offset to congr_cl14_wB_offset + congr_cl14_wB_d'length-1), + scout => sov(congr_cl14_wB_offset to congr_cl14_wB_offset + congr_cl14_wB_d'length-1), + din => congr_cl14_wB_d, + dout => congr_cl14_wB_q); +-- Congruence Class 14 Way C Register +congr_cl14_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl14_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl14_wC_offset to congr_cl14_wC_offset + congr_cl14_wC_d'length-1), + scout => sov(congr_cl14_wC_offset to congr_cl14_wC_offset + congr_cl14_wC_d'length-1), + din => congr_cl14_wC_d, + dout => congr_cl14_wC_q); +-- Congruence Class 14 Way D Register +congr_cl14_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl14_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl14_wD_offset to congr_cl14_wD_offset + congr_cl14_wD_d'length-1), + scout => sov(congr_cl14_wD_offset to congr_cl14_wD_offset + congr_cl14_wD_d'length-1), + din => congr_cl14_wD_d, + dout => congr_cl14_wD_q); +-- Congruence Class 14 Way E Register +congr_cl14_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl14_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl14_wE_offset to congr_cl14_wE_offset + congr_cl14_wE_d'length-1), + scout => sov(congr_cl14_wE_offset to congr_cl14_wE_offset + congr_cl14_wE_d'length-1), + din => congr_cl14_wE_d, + dout => congr_cl14_wE_q); +-- Congruence Class 14 Way F Register +congr_cl14_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl14_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl14_wF_offset to congr_cl14_wF_offset + congr_cl14_wF_d'length-1), + scout => sov(congr_cl14_wF_offset to congr_cl14_wF_offset + congr_cl14_wF_d'length-1), + din => congr_cl14_wF_d, + dout => congr_cl14_wF_q); +-- Congruence Class 14 Way G Register +congr_cl14_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl14_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl14_wG_offset to congr_cl14_wG_offset + congr_cl14_wG_d'length-1), + scout => sov(congr_cl14_wG_offset to congr_cl14_wG_offset + congr_cl14_wG_d'length-1), + din => congr_cl14_wG_d, + dout => congr_cl14_wG_q); +-- Congruence Class 14 Way H Register +congr_cl14_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl14_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl14_wH_offset to congr_cl14_wH_offset + congr_cl14_wH_d'length-1), + scout => sov(congr_cl14_wH_offset to congr_cl14_wH_offset + congr_cl14_wH_d'length-1), + din => congr_cl14_wH_d, + dout => congr_cl14_wH_q); +-- Congruence Class 15 Way A Register +congr_cl15_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl15_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl15_wA_offset to congr_cl15_wA_offset + congr_cl15_wA_d'length-1), + scout => sov(congr_cl15_wA_offset to congr_cl15_wA_offset + congr_cl15_wA_d'length-1), + din => congr_cl15_wA_d, + dout => congr_cl15_wA_q); +-- Congruence Class 15 Way B Register +congr_cl15_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl15_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl15_wB_offset to congr_cl15_wB_offset + congr_cl15_wB_d'length-1), + scout => sov(congr_cl15_wB_offset to congr_cl15_wB_offset + congr_cl15_wB_d'length-1), + din => congr_cl15_wB_d, + dout => congr_cl15_wB_q); +-- Congruence Class 15 Way C Register +congr_cl15_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl15_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl15_wC_offset to congr_cl15_wC_offset + congr_cl15_wC_d'length-1), + scout => sov(congr_cl15_wC_offset to congr_cl15_wC_offset + congr_cl15_wC_d'length-1), + din => congr_cl15_wC_d, + dout => congr_cl15_wC_q); +-- Congruence Class 15 Way D Register +congr_cl15_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl15_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl15_wD_offset to congr_cl15_wD_offset + congr_cl15_wD_d'length-1), + scout => sov(congr_cl15_wD_offset to congr_cl15_wD_offset + congr_cl15_wD_d'length-1), + din => congr_cl15_wD_d, + dout => congr_cl15_wD_q); +-- Congruence Class 15 Way E Register +congr_cl15_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl15_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl15_wE_offset to congr_cl15_wE_offset + congr_cl15_wE_d'length-1), + scout => sov(congr_cl15_wE_offset to congr_cl15_wE_offset + congr_cl15_wE_d'length-1), + din => congr_cl15_wE_d, + dout => congr_cl15_wE_q); +-- Congruence Class 15 Way F Register +congr_cl15_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl15_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl15_wF_offset to congr_cl15_wF_offset + congr_cl15_wF_d'length-1), + scout => sov(congr_cl15_wF_offset to congr_cl15_wF_offset + congr_cl15_wF_d'length-1), + din => congr_cl15_wF_d, + dout => congr_cl15_wF_q); +-- Congruence Class 15 Way G Register +congr_cl15_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl15_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl15_wG_offset to congr_cl15_wG_offset + congr_cl15_wG_d'length-1), + scout => sov(congr_cl15_wG_offset to congr_cl15_wG_offset + congr_cl15_wG_d'length-1), + din => congr_cl15_wG_d, + dout => congr_cl15_wG_q); +-- Congruence Class 15 Way H Register +congr_cl15_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl15_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl15_wH_offset to congr_cl15_wH_offset + congr_cl15_wH_d'length-1), + scout => sov(congr_cl15_wH_offset to congr_cl15_wH_offset + congr_cl15_wH_d'length-1), + din => congr_cl15_wH_d, + dout => congr_cl15_wH_q); +-- Congruence Class 16 Way A Register +congr_cl16_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl16_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl16_wA_offset to congr_cl16_wA_offset + congr_cl16_wA_d'length-1), + scout => sov(congr_cl16_wA_offset to congr_cl16_wA_offset + congr_cl16_wA_d'length-1), + din => congr_cl16_wA_d, + dout => congr_cl16_wA_q); +-- Congruence Class 16 Way B Register +congr_cl16_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl16_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl16_wB_offset to congr_cl16_wB_offset + congr_cl16_wB_d'length-1), + scout => sov(congr_cl16_wB_offset to congr_cl16_wB_offset + congr_cl16_wB_d'length-1), + din => congr_cl16_wB_d, + dout => congr_cl16_wB_q); +-- Congruence Class 16 Way C Register +congr_cl16_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl16_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl16_wC_offset to congr_cl16_wC_offset + congr_cl16_wC_d'length-1), + scout => sov(congr_cl16_wC_offset to congr_cl16_wC_offset + congr_cl16_wC_d'length-1), + din => congr_cl16_wC_d, + dout => congr_cl16_wC_q); +-- Congruence Class 16 Way D Register +congr_cl16_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl16_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl16_wD_offset to congr_cl16_wD_offset + congr_cl16_wD_d'length-1), + scout => sov(congr_cl16_wD_offset to congr_cl16_wD_offset + congr_cl16_wD_d'length-1), + din => congr_cl16_wD_d, + dout => congr_cl16_wD_q); +-- Congruence Class 16 Way E Register +congr_cl16_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl16_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl16_wE_offset to congr_cl16_wE_offset + congr_cl16_wE_d'length-1), + scout => sov(congr_cl16_wE_offset to congr_cl16_wE_offset + congr_cl16_wE_d'length-1), + din => congr_cl16_wE_d, + dout => congr_cl16_wE_q); +-- Congruence Class 16 Way F Register +congr_cl16_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl16_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl16_wF_offset to congr_cl16_wF_offset + congr_cl16_wF_d'length-1), + scout => sov(congr_cl16_wF_offset to congr_cl16_wF_offset + congr_cl16_wF_d'length-1), + din => congr_cl16_wF_d, + dout => congr_cl16_wF_q); +-- Congruence Class 16 Way G Register +congr_cl16_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl16_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl16_wG_offset to congr_cl16_wG_offset + congr_cl16_wG_d'length-1), + scout => sov(congr_cl16_wG_offset to congr_cl16_wG_offset + congr_cl16_wG_d'length-1), + din => congr_cl16_wG_d, + dout => congr_cl16_wG_q); +-- Congruence Class 16 Way H Register +congr_cl16_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl16_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl16_wH_offset to congr_cl16_wH_offset + congr_cl16_wH_d'length-1), + scout => sov(congr_cl16_wH_offset to congr_cl16_wH_offset + congr_cl16_wH_d'length-1), + din => congr_cl16_wH_d, + dout => congr_cl16_wH_q); +-- Congruence Class 17 Way A Register +congr_cl17_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl17_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl17_wA_offset to congr_cl17_wA_offset + congr_cl17_wA_d'length-1), + scout => sov(congr_cl17_wA_offset to congr_cl17_wA_offset + congr_cl17_wA_d'length-1), + din => congr_cl17_wA_d, + dout => congr_cl17_wA_q); +-- Congruence Class 17 Way B Register +congr_cl17_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl17_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl17_wB_offset to congr_cl17_wB_offset + congr_cl17_wB_d'length-1), + scout => sov(congr_cl17_wB_offset to congr_cl17_wB_offset + congr_cl17_wB_d'length-1), + din => congr_cl17_wB_d, + dout => congr_cl17_wB_q); +-- Congruence Class 17 Way C Register +congr_cl17_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl17_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl17_wC_offset to congr_cl17_wC_offset + congr_cl17_wC_d'length-1), + scout => sov(congr_cl17_wC_offset to congr_cl17_wC_offset + congr_cl17_wC_d'length-1), + din => congr_cl17_wC_d, + dout => congr_cl17_wC_q); +-- Congruence Class 17 Way D Register +congr_cl17_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl17_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl17_wD_offset to congr_cl17_wD_offset + congr_cl17_wD_d'length-1), + scout => sov(congr_cl17_wD_offset to congr_cl17_wD_offset + congr_cl17_wD_d'length-1), + din => congr_cl17_wD_d, + dout => congr_cl17_wD_q); +-- Congruence Class 17 Way E Register +congr_cl17_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl17_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl17_wE_offset to congr_cl17_wE_offset + congr_cl17_wE_d'length-1), + scout => sov(congr_cl17_wE_offset to congr_cl17_wE_offset + congr_cl17_wE_d'length-1), + din => congr_cl17_wE_d, + dout => congr_cl17_wE_q); +-- Congruence Class 17 Way F Register +congr_cl17_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl17_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl17_wF_offset to congr_cl17_wF_offset + congr_cl17_wF_d'length-1), + scout => sov(congr_cl17_wF_offset to congr_cl17_wF_offset + congr_cl17_wF_d'length-1), + din => congr_cl17_wF_d, + dout => congr_cl17_wF_q); +-- Congruence Class 17 Way G Register +congr_cl17_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl17_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl17_wG_offset to congr_cl17_wG_offset + congr_cl17_wG_d'length-1), + scout => sov(congr_cl17_wG_offset to congr_cl17_wG_offset + congr_cl17_wG_d'length-1), + din => congr_cl17_wG_d, + dout => congr_cl17_wG_q); +-- Congruence Class 17 Way H Register +congr_cl17_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl17_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl17_wH_offset to congr_cl17_wH_offset + congr_cl17_wH_d'length-1), + scout => sov(congr_cl17_wH_offset to congr_cl17_wH_offset + congr_cl17_wH_d'length-1), + din => congr_cl17_wH_d, + dout => congr_cl17_wH_q); +-- Congruence Class 18 Way A Register +congr_cl18_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl18_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl18_wA_offset to congr_cl18_wA_offset + congr_cl18_wA_d'length-1), + scout => sov(congr_cl18_wA_offset to congr_cl18_wA_offset + congr_cl18_wA_d'length-1), + din => congr_cl18_wA_d, + dout => congr_cl18_wA_q); +-- Congruence Class 18 Way B Register +congr_cl18_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl18_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl18_wB_offset to congr_cl18_wB_offset + congr_cl18_wB_d'length-1), + scout => sov(congr_cl18_wB_offset to congr_cl18_wB_offset + congr_cl18_wB_d'length-1), + din => congr_cl18_wB_d, + dout => congr_cl18_wB_q); +-- Congruence Class 18 Way C Register +congr_cl18_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl18_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl18_wC_offset to congr_cl18_wC_offset + congr_cl18_wC_d'length-1), + scout => sov(congr_cl18_wC_offset to congr_cl18_wC_offset + congr_cl18_wC_d'length-1), + din => congr_cl18_wC_d, + dout => congr_cl18_wC_q); +-- Congruence Class 18 Way D Register +congr_cl18_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl18_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl18_wD_offset to congr_cl18_wD_offset + congr_cl18_wD_d'length-1), + scout => sov(congr_cl18_wD_offset to congr_cl18_wD_offset + congr_cl18_wD_d'length-1), + din => congr_cl18_wD_d, + dout => congr_cl18_wD_q); +-- Congruence Class 18 Way E Register +congr_cl18_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl18_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl18_wE_offset to congr_cl18_wE_offset + congr_cl18_wE_d'length-1), + scout => sov(congr_cl18_wE_offset to congr_cl18_wE_offset + congr_cl18_wE_d'length-1), + din => congr_cl18_wE_d, + dout => congr_cl18_wE_q); +-- Congruence Class 18 Way F Register +congr_cl18_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl18_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl18_wF_offset to congr_cl18_wF_offset + congr_cl18_wF_d'length-1), + scout => sov(congr_cl18_wF_offset to congr_cl18_wF_offset + congr_cl18_wF_d'length-1), + din => congr_cl18_wF_d, + dout => congr_cl18_wF_q); +-- Congruence Class 18 Way G Register +congr_cl18_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl18_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl18_wG_offset to congr_cl18_wG_offset + congr_cl18_wG_d'length-1), + scout => sov(congr_cl18_wG_offset to congr_cl18_wG_offset + congr_cl18_wG_d'length-1), + din => congr_cl18_wG_d, + dout => congr_cl18_wG_q); +-- Congruence Class 18 Way H Register +congr_cl18_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl18_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl18_wH_offset to congr_cl18_wH_offset + congr_cl18_wH_d'length-1), + scout => sov(congr_cl18_wH_offset to congr_cl18_wH_offset + congr_cl18_wH_d'length-1), + din => congr_cl18_wH_d, + dout => congr_cl18_wH_q); +-- Congruence Class 19 Way A Register +congr_cl19_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl19_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl19_wA_offset to congr_cl19_wA_offset + congr_cl19_wA_d'length-1), + scout => sov(congr_cl19_wA_offset to congr_cl19_wA_offset + congr_cl19_wA_d'length-1), + din => congr_cl19_wA_d, + dout => congr_cl19_wA_q); +-- Congruence Class 19 Way B Register +congr_cl19_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl19_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl19_wB_offset to congr_cl19_wB_offset + congr_cl19_wB_d'length-1), + scout => sov(congr_cl19_wB_offset to congr_cl19_wB_offset + congr_cl19_wB_d'length-1), + din => congr_cl19_wB_d, + dout => congr_cl19_wB_q); +-- Congruence Class 19 Way C Register +congr_cl19_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl19_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl19_wC_offset to congr_cl19_wC_offset + congr_cl19_wC_d'length-1), + scout => sov(congr_cl19_wC_offset to congr_cl19_wC_offset + congr_cl19_wC_d'length-1), + din => congr_cl19_wC_d, + dout => congr_cl19_wC_q); +-- Congruence Class 19 Way D Register +congr_cl19_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl19_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl19_wD_offset to congr_cl19_wD_offset + congr_cl19_wD_d'length-1), + scout => sov(congr_cl19_wD_offset to congr_cl19_wD_offset + congr_cl19_wD_d'length-1), + din => congr_cl19_wD_d, + dout => congr_cl19_wD_q); +-- Congruence Class 19 Way E Register +congr_cl19_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl19_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl19_wE_offset to congr_cl19_wE_offset + congr_cl19_wE_d'length-1), + scout => sov(congr_cl19_wE_offset to congr_cl19_wE_offset + congr_cl19_wE_d'length-1), + din => congr_cl19_wE_d, + dout => congr_cl19_wE_q); +-- Congruence Class 19 Way F Register +congr_cl19_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl19_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl19_wF_offset to congr_cl19_wF_offset + congr_cl19_wF_d'length-1), + scout => sov(congr_cl19_wF_offset to congr_cl19_wF_offset + congr_cl19_wF_d'length-1), + din => congr_cl19_wF_d, + dout => congr_cl19_wF_q); +-- Congruence Class 19 Way G Register +congr_cl19_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl19_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl19_wG_offset to congr_cl19_wG_offset + congr_cl19_wG_d'length-1), + scout => sov(congr_cl19_wG_offset to congr_cl19_wG_offset + congr_cl19_wG_d'length-1), + din => congr_cl19_wG_d, + dout => congr_cl19_wG_q); +-- Congruence Class 19 Way H Register +congr_cl19_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl19_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl19_wH_offset to congr_cl19_wH_offset + congr_cl19_wH_d'length-1), + scout => sov(congr_cl19_wH_offset to congr_cl19_wH_offset + congr_cl19_wH_d'length-1), + din => congr_cl19_wH_d, + dout => congr_cl19_wH_q); +-- Congruence Class 20 Way A Register +congr_cl20_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl20_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl20_wA_offset to congr_cl20_wA_offset + congr_cl20_wA_d'length-1), + scout => sov(congr_cl20_wA_offset to congr_cl20_wA_offset + congr_cl20_wA_d'length-1), + din => congr_cl20_wA_d, + dout => congr_cl20_wA_q); +-- Congruence Class 20 Way B Register +congr_cl20_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl20_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl20_wB_offset to congr_cl20_wB_offset + congr_cl20_wB_d'length-1), + scout => sov(congr_cl20_wB_offset to congr_cl20_wB_offset + congr_cl20_wB_d'length-1), + din => congr_cl20_wB_d, + dout => congr_cl20_wB_q); +-- Congruence Class 20 Way C Register +congr_cl20_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl20_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl20_wC_offset to congr_cl20_wC_offset + congr_cl20_wC_d'length-1), + scout => sov(congr_cl20_wC_offset to congr_cl20_wC_offset + congr_cl20_wC_d'length-1), + din => congr_cl20_wC_d, + dout => congr_cl20_wC_q); +-- Congruence Class 20 Way D Register +congr_cl20_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl20_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl20_wD_offset to congr_cl20_wD_offset + congr_cl20_wD_d'length-1), + scout => sov(congr_cl20_wD_offset to congr_cl20_wD_offset + congr_cl20_wD_d'length-1), + din => congr_cl20_wD_d, + dout => congr_cl20_wD_q); +-- Congruence Class 20 Way E Register +congr_cl20_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl20_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl20_wE_offset to congr_cl20_wE_offset + congr_cl20_wE_d'length-1), + scout => sov(congr_cl20_wE_offset to congr_cl20_wE_offset + congr_cl20_wE_d'length-1), + din => congr_cl20_wE_d, + dout => congr_cl20_wE_q); +-- Congruence Class 20 Way F Register +congr_cl20_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl20_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl20_wF_offset to congr_cl20_wF_offset + congr_cl20_wF_d'length-1), + scout => sov(congr_cl20_wF_offset to congr_cl20_wF_offset + congr_cl20_wF_d'length-1), + din => congr_cl20_wF_d, + dout => congr_cl20_wF_q); +-- Congruence Class 20 Way G Register +congr_cl20_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl20_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl20_wG_offset to congr_cl20_wG_offset + congr_cl20_wG_d'length-1), + scout => sov(congr_cl20_wG_offset to congr_cl20_wG_offset + congr_cl20_wG_d'length-1), + din => congr_cl20_wG_d, + dout => congr_cl20_wG_q); +-- Congruence Class 20 Way H Register +congr_cl20_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl20_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl20_wH_offset to congr_cl20_wH_offset + congr_cl20_wH_d'length-1), + scout => sov(congr_cl20_wH_offset to congr_cl20_wH_offset + congr_cl20_wH_d'length-1), + din => congr_cl20_wH_d, + dout => congr_cl20_wH_q); +-- Congruence Class 21 Way A Register +congr_cl21_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl21_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl21_wA_offset to congr_cl21_wA_offset + congr_cl21_wA_d'length-1), + scout => sov(congr_cl21_wA_offset to congr_cl21_wA_offset + congr_cl21_wA_d'length-1), + din => congr_cl21_wA_d, + dout => congr_cl21_wA_q); +-- Congruence Class 21 Way B Register +congr_cl21_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl21_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl21_wB_offset to congr_cl21_wB_offset + congr_cl21_wB_d'length-1), + scout => sov(congr_cl21_wB_offset to congr_cl21_wB_offset + congr_cl21_wB_d'length-1), + din => congr_cl21_wB_d, + dout => congr_cl21_wB_q); +-- Congruence Class 21 Way C Register +congr_cl21_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl21_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl21_wC_offset to congr_cl21_wC_offset + congr_cl21_wC_d'length-1), + scout => sov(congr_cl21_wC_offset to congr_cl21_wC_offset + congr_cl21_wC_d'length-1), + din => congr_cl21_wC_d, + dout => congr_cl21_wC_q); +-- Congruence Class 21 Way D Register +congr_cl21_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl21_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl21_wD_offset to congr_cl21_wD_offset + congr_cl21_wD_d'length-1), + scout => sov(congr_cl21_wD_offset to congr_cl21_wD_offset + congr_cl21_wD_d'length-1), + din => congr_cl21_wD_d, + dout => congr_cl21_wD_q); +-- Congruence Class 21 Way E Register +congr_cl21_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl21_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl21_wE_offset to congr_cl21_wE_offset + congr_cl21_wE_d'length-1), + scout => sov(congr_cl21_wE_offset to congr_cl21_wE_offset + congr_cl21_wE_d'length-1), + din => congr_cl21_wE_d, + dout => congr_cl21_wE_q); +-- Congruence Class 21 Way F Register +congr_cl21_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl21_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl21_wF_offset to congr_cl21_wF_offset + congr_cl21_wF_d'length-1), + scout => sov(congr_cl21_wF_offset to congr_cl21_wF_offset + congr_cl21_wF_d'length-1), + din => congr_cl21_wF_d, + dout => congr_cl21_wF_q); +-- Congruence Class 21 Way G Register +congr_cl21_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl21_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl21_wG_offset to congr_cl21_wG_offset + congr_cl21_wG_d'length-1), + scout => sov(congr_cl21_wG_offset to congr_cl21_wG_offset + congr_cl21_wG_d'length-1), + din => congr_cl21_wG_d, + dout => congr_cl21_wG_q); +-- Congruence Class 21 Way H Register +congr_cl21_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl21_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl21_wH_offset to congr_cl21_wH_offset + congr_cl21_wH_d'length-1), + scout => sov(congr_cl21_wH_offset to congr_cl21_wH_offset + congr_cl21_wH_d'length-1), + din => congr_cl21_wH_d, + dout => congr_cl21_wH_q); +-- Congruence Class 22 Way A Register +congr_cl22_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl22_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl22_wA_offset to congr_cl22_wA_offset + congr_cl22_wA_d'length-1), + scout => sov(congr_cl22_wA_offset to congr_cl22_wA_offset + congr_cl22_wA_d'length-1), + din => congr_cl22_wA_d, + dout => congr_cl22_wA_q); +-- Congruence Class 22 Way B Register +congr_cl22_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl22_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl22_wB_offset to congr_cl22_wB_offset + congr_cl22_wB_d'length-1), + scout => sov(congr_cl22_wB_offset to congr_cl22_wB_offset + congr_cl22_wB_d'length-1), + din => congr_cl22_wB_d, + dout => congr_cl22_wB_q); +-- Congruence Class 22 Way C Register +congr_cl22_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl22_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl22_wC_offset to congr_cl22_wC_offset + congr_cl22_wC_d'length-1), + scout => sov(congr_cl22_wC_offset to congr_cl22_wC_offset + congr_cl22_wC_d'length-1), + din => congr_cl22_wC_d, + dout => congr_cl22_wC_q); +-- Congruence Class 22 Way D Register +congr_cl22_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl22_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl22_wD_offset to congr_cl22_wD_offset + congr_cl22_wD_d'length-1), + scout => sov(congr_cl22_wD_offset to congr_cl22_wD_offset + congr_cl22_wD_d'length-1), + din => congr_cl22_wD_d, + dout => congr_cl22_wD_q); +-- Congruence Class 22 Way E Register +congr_cl22_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl22_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl22_wE_offset to congr_cl22_wE_offset + congr_cl22_wE_d'length-1), + scout => sov(congr_cl22_wE_offset to congr_cl22_wE_offset + congr_cl22_wE_d'length-1), + din => congr_cl22_wE_d, + dout => congr_cl22_wE_q); +-- Congruence Class 22 Way F Register +congr_cl22_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl22_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl22_wF_offset to congr_cl22_wF_offset + congr_cl22_wF_d'length-1), + scout => sov(congr_cl22_wF_offset to congr_cl22_wF_offset + congr_cl22_wF_d'length-1), + din => congr_cl22_wF_d, + dout => congr_cl22_wF_q); +-- Congruence Class 22 Way G Register +congr_cl22_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl22_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl22_wG_offset to congr_cl22_wG_offset + congr_cl22_wG_d'length-1), + scout => sov(congr_cl22_wG_offset to congr_cl22_wG_offset + congr_cl22_wG_d'length-1), + din => congr_cl22_wG_d, + dout => congr_cl22_wG_q); +-- Congruence Class 22 Way H Register +congr_cl22_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl22_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl22_wH_offset to congr_cl22_wH_offset + congr_cl22_wH_d'length-1), + scout => sov(congr_cl22_wH_offset to congr_cl22_wH_offset + congr_cl22_wH_d'length-1), + din => congr_cl22_wH_d, + dout => congr_cl22_wH_q); +-- Congruence Class 23 Way A Register +congr_cl23_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl23_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl23_wA_offset to congr_cl23_wA_offset + congr_cl23_wA_d'length-1), + scout => sov(congr_cl23_wA_offset to congr_cl23_wA_offset + congr_cl23_wA_d'length-1), + din => congr_cl23_wA_d, + dout => congr_cl23_wA_q); +-- Congruence Class 23 Way B Register +congr_cl23_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl23_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl23_wB_offset to congr_cl23_wB_offset + congr_cl23_wB_d'length-1), + scout => sov(congr_cl23_wB_offset to congr_cl23_wB_offset + congr_cl23_wB_d'length-1), + din => congr_cl23_wB_d, + dout => congr_cl23_wB_q); +-- Congruence Class 23 Way C Register +congr_cl23_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl23_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl23_wC_offset to congr_cl23_wC_offset + congr_cl23_wC_d'length-1), + scout => sov(congr_cl23_wC_offset to congr_cl23_wC_offset + congr_cl23_wC_d'length-1), + din => congr_cl23_wC_d, + dout => congr_cl23_wC_q); +-- Congruence Class 23 Way D Register +congr_cl23_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl23_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl23_wD_offset to congr_cl23_wD_offset + congr_cl23_wD_d'length-1), + scout => sov(congr_cl23_wD_offset to congr_cl23_wD_offset + congr_cl23_wD_d'length-1), + din => congr_cl23_wD_d, + dout => congr_cl23_wD_q); +-- Congruence Class 23 Way E Register +congr_cl23_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl23_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl23_wE_offset to congr_cl23_wE_offset + congr_cl23_wE_d'length-1), + scout => sov(congr_cl23_wE_offset to congr_cl23_wE_offset + congr_cl23_wE_d'length-1), + din => congr_cl23_wE_d, + dout => congr_cl23_wE_q); +-- Congruence Class 23 Way F Register +congr_cl23_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl23_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl23_wF_offset to congr_cl23_wF_offset + congr_cl23_wF_d'length-1), + scout => sov(congr_cl23_wF_offset to congr_cl23_wF_offset + congr_cl23_wF_d'length-1), + din => congr_cl23_wF_d, + dout => congr_cl23_wF_q); +-- Congruence Class 23 Way G Register +congr_cl23_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl23_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl23_wG_offset to congr_cl23_wG_offset + congr_cl23_wG_d'length-1), + scout => sov(congr_cl23_wG_offset to congr_cl23_wG_offset + congr_cl23_wG_d'length-1), + din => congr_cl23_wG_d, + dout => congr_cl23_wG_q); +-- Congruence Class 23 Way H Register +congr_cl23_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl23_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl23_wH_offset to congr_cl23_wH_offset + congr_cl23_wH_d'length-1), + scout => sov(congr_cl23_wH_offset to congr_cl23_wH_offset + congr_cl23_wH_d'length-1), + din => congr_cl23_wH_d, + dout => congr_cl23_wH_q); +-- Congruence Class 24 Way A Register +congr_cl24_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl24_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl24_wA_offset to congr_cl24_wA_offset + congr_cl24_wA_d'length-1), + scout => sov(congr_cl24_wA_offset to congr_cl24_wA_offset + congr_cl24_wA_d'length-1), + din => congr_cl24_wA_d, + dout => congr_cl24_wA_q); +-- Congruence Class 24 Way B Register +congr_cl24_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl24_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl24_wB_offset to congr_cl24_wB_offset + congr_cl24_wB_d'length-1), + scout => sov(congr_cl24_wB_offset to congr_cl24_wB_offset + congr_cl24_wB_d'length-1), + din => congr_cl24_wB_d, + dout => congr_cl24_wB_q); +-- Congruence Class 24 Way C Register +congr_cl24_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl24_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl24_wC_offset to congr_cl24_wC_offset + congr_cl24_wC_d'length-1), + scout => sov(congr_cl24_wC_offset to congr_cl24_wC_offset + congr_cl24_wC_d'length-1), + din => congr_cl24_wC_d, + dout => congr_cl24_wC_q); +-- Congruence Class 24 Way D Register +congr_cl24_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl24_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl24_wD_offset to congr_cl24_wD_offset + congr_cl24_wD_d'length-1), + scout => sov(congr_cl24_wD_offset to congr_cl24_wD_offset + congr_cl24_wD_d'length-1), + din => congr_cl24_wD_d, + dout => congr_cl24_wD_q); +-- Congruence Class 24 Way E Register +congr_cl24_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl24_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl24_wE_offset to congr_cl24_wE_offset + congr_cl24_wE_d'length-1), + scout => sov(congr_cl24_wE_offset to congr_cl24_wE_offset + congr_cl24_wE_d'length-1), + din => congr_cl24_wE_d, + dout => congr_cl24_wE_q); +-- Congruence Class 24 Way F Register +congr_cl24_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl24_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl24_wF_offset to congr_cl24_wF_offset + congr_cl24_wF_d'length-1), + scout => sov(congr_cl24_wF_offset to congr_cl24_wF_offset + congr_cl24_wF_d'length-1), + din => congr_cl24_wF_d, + dout => congr_cl24_wF_q); +-- Congruence Class 24 Way G Register +congr_cl24_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl24_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl24_wG_offset to congr_cl24_wG_offset + congr_cl24_wG_d'length-1), + scout => sov(congr_cl24_wG_offset to congr_cl24_wG_offset + congr_cl24_wG_d'length-1), + din => congr_cl24_wG_d, + dout => congr_cl24_wG_q); +-- Congruence Class 24 Way H Register +congr_cl24_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl24_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl24_wH_offset to congr_cl24_wH_offset + congr_cl24_wH_d'length-1), + scout => sov(congr_cl24_wH_offset to congr_cl24_wH_offset + congr_cl24_wH_d'length-1), + din => congr_cl24_wH_d, + dout => congr_cl24_wH_q); +-- Congruence Class 25 Way A Register +congr_cl25_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl25_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl25_wA_offset to congr_cl25_wA_offset + congr_cl25_wA_d'length-1), + scout => sov(congr_cl25_wA_offset to congr_cl25_wA_offset + congr_cl25_wA_d'length-1), + din => congr_cl25_wA_d, + dout => congr_cl25_wA_q); +-- Congruence Class 25 Way B Register +congr_cl25_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl25_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl25_wB_offset to congr_cl25_wB_offset + congr_cl25_wB_d'length-1), + scout => sov(congr_cl25_wB_offset to congr_cl25_wB_offset + congr_cl25_wB_d'length-1), + din => congr_cl25_wB_d, + dout => congr_cl25_wB_q); +-- Congruence Class 25 Way C Register +congr_cl25_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl25_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl25_wC_offset to congr_cl25_wC_offset + congr_cl25_wC_d'length-1), + scout => sov(congr_cl25_wC_offset to congr_cl25_wC_offset + congr_cl25_wC_d'length-1), + din => congr_cl25_wC_d, + dout => congr_cl25_wC_q); +-- Congruence Class 25 Way D Register +congr_cl25_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl25_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl25_wD_offset to congr_cl25_wD_offset + congr_cl25_wD_d'length-1), + scout => sov(congr_cl25_wD_offset to congr_cl25_wD_offset + congr_cl25_wD_d'length-1), + din => congr_cl25_wD_d, + dout => congr_cl25_wD_q); +-- Congruence Class 25 Way E Register +congr_cl25_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl25_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl25_wE_offset to congr_cl25_wE_offset + congr_cl25_wE_d'length-1), + scout => sov(congr_cl25_wE_offset to congr_cl25_wE_offset + congr_cl25_wE_d'length-1), + din => congr_cl25_wE_d, + dout => congr_cl25_wE_q); +-- Congruence Class 25 Way F Register +congr_cl25_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl25_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl25_wF_offset to congr_cl25_wF_offset + congr_cl25_wF_d'length-1), + scout => sov(congr_cl25_wF_offset to congr_cl25_wF_offset + congr_cl25_wF_d'length-1), + din => congr_cl25_wF_d, + dout => congr_cl25_wF_q); +-- Congruence Class 25 Way G Register +congr_cl25_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl25_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl25_wG_offset to congr_cl25_wG_offset + congr_cl25_wG_d'length-1), + scout => sov(congr_cl25_wG_offset to congr_cl25_wG_offset + congr_cl25_wG_d'length-1), + din => congr_cl25_wG_d, + dout => congr_cl25_wG_q); +-- Congruence Class 25 Way H Register +congr_cl25_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl25_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl25_wH_offset to congr_cl25_wH_offset + congr_cl25_wH_d'length-1), + scout => sov(congr_cl25_wH_offset to congr_cl25_wH_offset + congr_cl25_wH_d'length-1), + din => congr_cl25_wH_d, + dout => congr_cl25_wH_q); +-- Congruence Class 26 Way A Register +congr_cl26_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl26_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl26_wA_offset to congr_cl26_wA_offset + congr_cl26_wA_d'length-1), + scout => sov(congr_cl26_wA_offset to congr_cl26_wA_offset + congr_cl26_wA_d'length-1), + din => congr_cl26_wA_d, + dout => congr_cl26_wA_q); +-- Congruence Class 26 Way B Register +congr_cl26_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl26_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl26_wB_offset to congr_cl26_wB_offset + congr_cl26_wB_d'length-1), + scout => sov(congr_cl26_wB_offset to congr_cl26_wB_offset + congr_cl26_wB_d'length-1), + din => congr_cl26_wB_d, + dout => congr_cl26_wB_q); +-- Congruence Class 26 Way C Register +congr_cl26_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl26_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl26_wC_offset to congr_cl26_wC_offset + congr_cl26_wC_d'length-1), + scout => sov(congr_cl26_wC_offset to congr_cl26_wC_offset + congr_cl26_wC_d'length-1), + din => congr_cl26_wC_d, + dout => congr_cl26_wC_q); +-- Congruence Class 26 Way D Register +congr_cl26_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl26_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl26_wD_offset to congr_cl26_wD_offset + congr_cl26_wD_d'length-1), + scout => sov(congr_cl26_wD_offset to congr_cl26_wD_offset + congr_cl26_wD_d'length-1), + din => congr_cl26_wD_d, + dout => congr_cl26_wD_q); +-- Congruence Class 26 Way E Register +congr_cl26_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl26_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl26_wE_offset to congr_cl26_wE_offset + congr_cl26_wE_d'length-1), + scout => sov(congr_cl26_wE_offset to congr_cl26_wE_offset + congr_cl26_wE_d'length-1), + din => congr_cl26_wE_d, + dout => congr_cl26_wE_q); +-- Congruence Class 26 Way F Register +congr_cl26_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl26_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl26_wF_offset to congr_cl26_wF_offset + congr_cl26_wF_d'length-1), + scout => sov(congr_cl26_wF_offset to congr_cl26_wF_offset + congr_cl26_wF_d'length-1), + din => congr_cl26_wF_d, + dout => congr_cl26_wF_q); +-- Congruence Class 26 Way G Register +congr_cl26_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl26_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl26_wG_offset to congr_cl26_wG_offset + congr_cl26_wG_d'length-1), + scout => sov(congr_cl26_wG_offset to congr_cl26_wG_offset + congr_cl26_wG_d'length-1), + din => congr_cl26_wG_d, + dout => congr_cl26_wG_q); +-- Congruence Class 26 Way H Register +congr_cl26_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl26_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl26_wH_offset to congr_cl26_wH_offset + congr_cl26_wH_d'length-1), + scout => sov(congr_cl26_wH_offset to congr_cl26_wH_offset + congr_cl26_wH_d'length-1), + din => congr_cl26_wH_d, + dout => congr_cl26_wH_q); +-- Congruence Class 27 Way A Register +congr_cl27_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl27_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl27_wA_offset to congr_cl27_wA_offset + congr_cl27_wA_d'length-1), + scout => sov(congr_cl27_wA_offset to congr_cl27_wA_offset + congr_cl27_wA_d'length-1), + din => congr_cl27_wA_d, + dout => congr_cl27_wA_q); +-- Congruence Class 27 Way B Register +congr_cl27_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl27_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl27_wB_offset to congr_cl27_wB_offset + congr_cl27_wB_d'length-1), + scout => sov(congr_cl27_wB_offset to congr_cl27_wB_offset + congr_cl27_wB_d'length-1), + din => congr_cl27_wB_d, + dout => congr_cl27_wB_q); +-- Congruence Class 27 Way C Register +congr_cl27_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl27_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl27_wC_offset to congr_cl27_wC_offset + congr_cl27_wC_d'length-1), + scout => sov(congr_cl27_wC_offset to congr_cl27_wC_offset + congr_cl27_wC_d'length-1), + din => congr_cl27_wC_d, + dout => congr_cl27_wC_q); +-- Congruence Class 27 Way D Register +congr_cl27_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl27_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl27_wD_offset to congr_cl27_wD_offset + congr_cl27_wD_d'length-1), + scout => sov(congr_cl27_wD_offset to congr_cl27_wD_offset + congr_cl27_wD_d'length-1), + din => congr_cl27_wD_d, + dout => congr_cl27_wD_q); +-- Congruence Class 27 Way E Register +congr_cl27_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl27_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl27_wE_offset to congr_cl27_wE_offset + congr_cl27_wE_d'length-1), + scout => sov(congr_cl27_wE_offset to congr_cl27_wE_offset + congr_cl27_wE_d'length-1), + din => congr_cl27_wE_d, + dout => congr_cl27_wE_q); +-- Congruence Class 27 Way F Register +congr_cl27_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl27_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl27_wF_offset to congr_cl27_wF_offset + congr_cl27_wF_d'length-1), + scout => sov(congr_cl27_wF_offset to congr_cl27_wF_offset + congr_cl27_wF_d'length-1), + din => congr_cl27_wF_d, + dout => congr_cl27_wF_q); +-- Congruence Class 27 Way G Register +congr_cl27_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl27_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl27_wG_offset to congr_cl27_wG_offset + congr_cl27_wG_d'length-1), + scout => sov(congr_cl27_wG_offset to congr_cl27_wG_offset + congr_cl27_wG_d'length-1), + din => congr_cl27_wG_d, + dout => congr_cl27_wG_q); +-- Congruence Class 27 Way H Register +congr_cl27_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl27_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl27_wH_offset to congr_cl27_wH_offset + congr_cl27_wH_d'length-1), + scout => sov(congr_cl27_wH_offset to congr_cl27_wH_offset + congr_cl27_wH_d'length-1), + din => congr_cl27_wH_d, + dout => congr_cl27_wH_q); +-- Congruence Class 28 Way A Register +congr_cl28_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl28_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl28_wA_offset to congr_cl28_wA_offset + congr_cl28_wA_d'length-1), + scout => sov(congr_cl28_wA_offset to congr_cl28_wA_offset + congr_cl28_wA_d'length-1), + din => congr_cl28_wA_d, + dout => congr_cl28_wA_q); +-- Congruence Class 28 Way B Register +congr_cl28_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl28_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl28_wB_offset to congr_cl28_wB_offset + congr_cl28_wB_d'length-1), + scout => sov(congr_cl28_wB_offset to congr_cl28_wB_offset + congr_cl28_wB_d'length-1), + din => congr_cl28_wB_d, + dout => congr_cl28_wB_q); +-- Congruence Class 28 Way C Register +congr_cl28_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl28_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl28_wC_offset to congr_cl28_wC_offset + congr_cl28_wC_d'length-1), + scout => sov(congr_cl28_wC_offset to congr_cl28_wC_offset + congr_cl28_wC_d'length-1), + din => congr_cl28_wC_d, + dout => congr_cl28_wC_q); +-- Congruence Class 28 Way D Register +congr_cl28_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl28_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl28_wD_offset to congr_cl28_wD_offset + congr_cl28_wD_d'length-1), + scout => sov(congr_cl28_wD_offset to congr_cl28_wD_offset + congr_cl28_wD_d'length-1), + din => congr_cl28_wD_d, + dout => congr_cl28_wD_q); +-- Congruence Class 28 Way E Register +congr_cl28_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl28_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl28_wE_offset to congr_cl28_wE_offset + congr_cl28_wE_d'length-1), + scout => sov(congr_cl28_wE_offset to congr_cl28_wE_offset + congr_cl28_wE_d'length-1), + din => congr_cl28_wE_d, + dout => congr_cl28_wE_q); +-- Congruence Class 28 Way F Register +congr_cl28_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl28_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl28_wF_offset to congr_cl28_wF_offset + congr_cl28_wF_d'length-1), + scout => sov(congr_cl28_wF_offset to congr_cl28_wF_offset + congr_cl28_wF_d'length-1), + din => congr_cl28_wF_d, + dout => congr_cl28_wF_q); +-- Congruence Class 28 Way G Register +congr_cl28_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl28_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl28_wG_offset to congr_cl28_wG_offset + congr_cl28_wG_d'length-1), + scout => sov(congr_cl28_wG_offset to congr_cl28_wG_offset + congr_cl28_wG_d'length-1), + din => congr_cl28_wG_d, + dout => congr_cl28_wG_q); +-- Congruence Class 28 Way H Register +congr_cl28_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl28_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl28_wH_offset to congr_cl28_wH_offset + congr_cl28_wH_d'length-1), + scout => sov(congr_cl28_wH_offset to congr_cl28_wH_offset + congr_cl28_wH_d'length-1), + din => congr_cl28_wH_d, + dout => congr_cl28_wH_q); +-- Congruence Class 29 Way A Register +congr_cl29_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl29_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl29_wA_offset to congr_cl29_wA_offset + congr_cl29_wA_d'length-1), + scout => sov(congr_cl29_wA_offset to congr_cl29_wA_offset + congr_cl29_wA_d'length-1), + din => congr_cl29_wA_d, + dout => congr_cl29_wA_q); +-- Congruence Class 29 Way B Register +congr_cl29_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl29_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl29_wB_offset to congr_cl29_wB_offset + congr_cl29_wB_d'length-1), + scout => sov(congr_cl29_wB_offset to congr_cl29_wB_offset + congr_cl29_wB_d'length-1), + din => congr_cl29_wB_d, + dout => congr_cl29_wB_q); +-- Congruence Class 29 Way C Register +congr_cl29_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl29_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl29_wC_offset to congr_cl29_wC_offset + congr_cl29_wC_d'length-1), + scout => sov(congr_cl29_wC_offset to congr_cl29_wC_offset + congr_cl29_wC_d'length-1), + din => congr_cl29_wC_d, + dout => congr_cl29_wC_q); +-- Congruence Class 29 Way D Register +congr_cl29_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl29_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl29_wD_offset to congr_cl29_wD_offset + congr_cl29_wD_d'length-1), + scout => sov(congr_cl29_wD_offset to congr_cl29_wD_offset + congr_cl29_wD_d'length-1), + din => congr_cl29_wD_d, + dout => congr_cl29_wD_q); +-- Congruence Class 29 Way E Register +congr_cl29_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl29_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl29_wE_offset to congr_cl29_wE_offset + congr_cl29_wE_d'length-1), + scout => sov(congr_cl29_wE_offset to congr_cl29_wE_offset + congr_cl29_wE_d'length-1), + din => congr_cl29_wE_d, + dout => congr_cl29_wE_q); +-- Congruence Class 29 Way F Register +congr_cl29_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl29_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl29_wF_offset to congr_cl29_wF_offset + congr_cl29_wF_d'length-1), + scout => sov(congr_cl29_wF_offset to congr_cl29_wF_offset + congr_cl29_wF_d'length-1), + din => congr_cl29_wF_d, + dout => congr_cl29_wF_q); +-- Congruence Class 29 Way G Register +congr_cl29_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl29_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl29_wG_offset to congr_cl29_wG_offset + congr_cl29_wG_d'length-1), + scout => sov(congr_cl29_wG_offset to congr_cl29_wG_offset + congr_cl29_wG_d'length-1), + din => congr_cl29_wG_d, + dout => congr_cl29_wG_q); +-- Congruence Class 29 Way H Register +congr_cl29_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl29_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl29_wH_offset to congr_cl29_wH_offset + congr_cl29_wH_d'length-1), + scout => sov(congr_cl29_wH_offset to congr_cl29_wH_offset + congr_cl29_wH_d'length-1), + din => congr_cl29_wH_d, + dout => congr_cl29_wH_q); +-- Congruence Class 30 Way A Register +congr_cl30_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl30_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl30_wA_offset to congr_cl30_wA_offset + congr_cl30_wA_d'length-1), + scout => sov(congr_cl30_wA_offset to congr_cl30_wA_offset + congr_cl30_wA_d'length-1), + din => congr_cl30_wA_d, + dout => congr_cl30_wA_q); +-- Congruence Class 30 Way B Register +congr_cl30_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl30_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl30_wB_offset to congr_cl30_wB_offset + congr_cl30_wB_d'length-1), + scout => sov(congr_cl30_wB_offset to congr_cl30_wB_offset + congr_cl30_wB_d'length-1), + din => congr_cl30_wB_d, + dout => congr_cl30_wB_q); +-- Congruence Class 30 Way C Register +congr_cl30_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl30_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl30_wC_offset to congr_cl30_wC_offset + congr_cl30_wC_d'length-1), + scout => sov(congr_cl30_wC_offset to congr_cl30_wC_offset + congr_cl30_wC_d'length-1), + din => congr_cl30_wC_d, + dout => congr_cl30_wC_q); +-- Congruence Class 30 Way D Register +congr_cl30_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl30_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl30_wD_offset to congr_cl30_wD_offset + congr_cl30_wD_d'length-1), + scout => sov(congr_cl30_wD_offset to congr_cl30_wD_offset + congr_cl30_wD_d'length-1), + din => congr_cl30_wD_d, + dout => congr_cl30_wD_q); +-- Congruence Class 30 Way E Register +congr_cl30_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl30_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl30_wE_offset to congr_cl30_wE_offset + congr_cl30_wE_d'length-1), + scout => sov(congr_cl30_wE_offset to congr_cl30_wE_offset + congr_cl30_wE_d'length-1), + din => congr_cl30_wE_d, + dout => congr_cl30_wE_q); +-- Congruence Class 30 Way F Register +congr_cl30_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl30_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl30_wF_offset to congr_cl30_wF_offset + congr_cl30_wF_d'length-1), + scout => sov(congr_cl30_wF_offset to congr_cl30_wF_offset + congr_cl30_wF_d'length-1), + din => congr_cl30_wF_d, + dout => congr_cl30_wF_q); +-- Congruence Class 30 Way G Register +congr_cl30_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl30_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl30_wG_offset to congr_cl30_wG_offset + congr_cl30_wG_d'length-1), + scout => sov(congr_cl30_wG_offset to congr_cl30_wG_offset + congr_cl30_wG_d'length-1), + din => congr_cl30_wG_d, + dout => congr_cl30_wG_q); +-- Congruence Class 30 Way H Register +congr_cl30_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl30_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl30_wH_offset to congr_cl30_wH_offset + congr_cl30_wH_d'length-1), + scout => sov(congr_cl30_wH_offset to congr_cl30_wH_offset + congr_cl30_wH_d'length-1), + din => congr_cl30_wH_d, + dout => congr_cl30_wH_q); +-- Congruence Class 31 Way A Register +congr_cl31_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl31_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl31_wA_offset to congr_cl31_wA_offset + congr_cl31_wA_d'length-1), + scout => sov(congr_cl31_wA_offset to congr_cl31_wA_offset + congr_cl31_wA_d'length-1), + din => congr_cl31_wA_d, + dout => congr_cl31_wA_q); +-- Congruence Class 31 Way B Register +congr_cl31_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl31_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl31_wB_offset to congr_cl31_wB_offset + congr_cl31_wB_d'length-1), + scout => sov(congr_cl31_wB_offset to congr_cl31_wB_offset + congr_cl31_wB_d'length-1), + din => congr_cl31_wB_d, + dout => congr_cl31_wB_q); +-- Congruence Class 31 Way C Register +congr_cl31_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl31_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl31_wC_offset to congr_cl31_wC_offset + congr_cl31_wC_d'length-1), + scout => sov(congr_cl31_wC_offset to congr_cl31_wC_offset + congr_cl31_wC_d'length-1), + din => congr_cl31_wC_d, + dout => congr_cl31_wC_q); +-- Congruence Class 31 Way D Register +congr_cl31_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl31_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl31_wD_offset to congr_cl31_wD_offset + congr_cl31_wD_d'length-1), + scout => sov(congr_cl31_wD_offset to congr_cl31_wD_offset + congr_cl31_wD_d'length-1), + din => congr_cl31_wD_d, + dout => congr_cl31_wD_q); +-- Congruence Class 31 Way E Register +congr_cl31_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl31_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl31_wE_offset to congr_cl31_wE_offset + congr_cl31_wE_d'length-1), + scout => sov(congr_cl31_wE_offset to congr_cl31_wE_offset + congr_cl31_wE_d'length-1), + din => congr_cl31_wE_d, + dout => congr_cl31_wE_q); +-- Congruence Class 31 Way F Register +congr_cl31_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl31_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl31_wF_offset to congr_cl31_wF_offset + congr_cl31_wF_d'length-1), + scout => sov(congr_cl31_wF_offset to congr_cl31_wF_offset + congr_cl31_wF_d'length-1), + din => congr_cl31_wF_d, + dout => congr_cl31_wF_q); +-- Congruence Class 31 Way G Register +congr_cl31_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl31_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl31_wG_offset to congr_cl31_wG_offset + congr_cl31_wG_d'length-1), + scout => sov(congr_cl31_wG_offset to congr_cl31_wG_offset + congr_cl31_wG_d'length-1), + din => congr_cl31_wG_d, + dout => congr_cl31_wG_q); +-- Congruence Class 31 Way H Register +congr_cl31_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl31_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl31_wH_offset to congr_cl31_wH_offset + congr_cl31_wH_d'length-1), + scout => sov(congr_cl31_wH_offset to congr_cl31_wH_offset + congr_cl31_wH_d'length-1), + din => congr_cl31_wH_d, + dout => congr_cl31_wH_q); +congr_cl_all_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => congr_cl_all_act_d, + dout(0) => congr_cl_all_act_q); +-- Port 0 Congruence Class 0 Act +p0_congr_cl0_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl0_act_d, + dout(0) => p0_congr_cl0_act_q); +-- Port 0 Congruence Class 1 Act +p0_congr_cl1_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl1_act_d, + dout(0) => p0_congr_cl1_act_q); +-- Port 0 Congruence Class 2 Act +p0_congr_cl2_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl2_act_d, + dout(0) => p0_congr_cl2_act_q); +-- Port 0 Congruence Class 3 Act +p0_congr_cl3_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl3_act_d, + dout(0) => p0_congr_cl3_act_q); +-- Port 0 Congruence Class 4 Act +p0_congr_cl4_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl4_act_d, + dout(0) => p0_congr_cl4_act_q); +-- Port 0 Congruence Class 5 Act +p0_congr_cl5_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl5_act_d, + dout(0) => p0_congr_cl5_act_q); +-- Port 0 Congruence Class 6 Act +p0_congr_cl6_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl6_act_d, + dout(0) => p0_congr_cl6_act_q); +-- Port 0 Congruence Class 7 Act +p0_congr_cl7_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl7_act_d, + dout(0) => p0_congr_cl7_act_q); +-- Port 0 Congruence Class 8 Act +p0_congr_cl8_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl8_act_d, + dout(0) => p0_congr_cl8_act_q); +-- Port 0 Congruence Class 9 Act +p0_congr_cl9_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl9_act_d, + dout(0) => p0_congr_cl9_act_q); +-- Port 0 Congruence Class 10 Act +p0_congr_cl10_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl10_act_d, + dout(0) => p0_congr_cl10_act_q); +-- Port 0 Congruence Class 11 Act +p0_congr_cl11_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl11_act_d, + dout(0) => p0_congr_cl11_act_q); +-- Port 0 Congruence Class 12 Act +p0_congr_cl12_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl12_act_d, + dout(0) => p0_congr_cl12_act_q); +-- Port 0 Congruence Class 13 Act +p0_congr_cl13_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl13_act_d, + dout(0) => p0_congr_cl13_act_q); +-- Port 0 Congruence Class 14 Act +p0_congr_cl14_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl14_act_d, + dout(0) => p0_congr_cl14_act_q); +-- Port 0 Congruence Class 15 Act +p0_congr_cl15_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl15_act_d, + dout(0) => p0_congr_cl15_act_q); +-- Port 0 Congruence Class 16 Act +p0_congr_cl16_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl16_act_d, + dout(0) => p0_congr_cl16_act_q); +-- Port 0 Congruence Class 17 Act +p0_congr_cl17_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl17_act_d, + dout(0) => p0_congr_cl17_act_q); +-- Port 0 Congruence Class 18 Act +p0_congr_cl18_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl18_act_d, + dout(0) => p0_congr_cl18_act_q); +-- Port 0 Congruence Class 19 Act +p0_congr_cl19_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl19_act_d, + dout(0) => p0_congr_cl19_act_q); +-- Port 0 Congruence Class 20 Act +p0_congr_cl20_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl20_act_d, + dout(0) => p0_congr_cl20_act_q); +-- Port 0 Congruence Class 21 Act +p0_congr_cl21_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl21_act_d, + dout(0) => p0_congr_cl21_act_q); +-- Port 0 Congruence Class 22 Act +p0_congr_cl22_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl22_act_d, + dout(0) => p0_congr_cl22_act_q); +-- Port 0 Congruence Class 23 Act +p0_congr_cl23_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl23_act_d, + dout(0) => p0_congr_cl23_act_q); +-- Port 0 Congruence Class 24 Act +p0_congr_cl24_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl24_act_d, + dout(0) => p0_congr_cl24_act_q); +-- Port 0 Congruence Class 25 Act +p0_congr_cl25_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl25_act_d, + dout(0) => p0_congr_cl25_act_q); +-- Port 0 Congruence Class 26 Act +p0_congr_cl26_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl26_act_d, + dout(0) => p0_congr_cl26_act_q); +-- Port 0 Congruence Class 27 Act +p0_congr_cl27_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl27_act_d, + dout(0) => p0_congr_cl27_act_q); +-- Port 0 Congruence Class 28 Act +p0_congr_cl28_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl28_act_d, + dout(0) => p0_congr_cl28_act_q); +-- Port 0 Congruence Class 29 Act +p0_congr_cl29_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl29_act_d, + dout(0) => p0_congr_cl29_act_q); +-- Port 0 Congruence Class 30 Act +p0_congr_cl30_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl30_act_d, + dout(0) => p0_congr_cl30_act_q); +-- Port 0 Congruence Class 31 Act +p0_congr_cl31_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl31_act_d, + dout(0) => p0_congr_cl31_act_q); +-- Port 1 Congruence Class 0 Act +p1_congr_cl0_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl0_act_d, + dout(0) => p1_congr_cl0_act_q); +-- Port 1 Congruence Class 1 Act +p1_congr_cl1_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl1_act_d, + dout(0) => p1_congr_cl1_act_q); +-- Port 1 Congruence Class 2 Act +p1_congr_cl2_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl2_act_d, + dout(0) => p1_congr_cl2_act_q); +-- Port 1 Congruence Class 3 Act +p1_congr_cl3_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl3_act_d, + dout(0) => p1_congr_cl3_act_q); +-- Port 1 Congruence Class 4 Act +p1_congr_cl4_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl4_act_d, + dout(0) => p1_congr_cl4_act_q); +-- Port 1 Congruence Class 5 Act +p1_congr_cl5_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl5_act_d, + dout(0) => p1_congr_cl5_act_q); +-- Port 1 Congruence Class 6 Act +p1_congr_cl6_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl6_act_d, + dout(0) => p1_congr_cl6_act_q); +-- Port 1 Congruence Class 7 Act +p1_congr_cl7_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl7_act_d, + dout(0) => p1_congr_cl7_act_q); +-- Port 1 Congruence Class 8 Act +p1_congr_cl8_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl8_act_d, + dout(0) => p1_congr_cl8_act_q); +-- Port 1 Congruence Class 9 Act +p1_congr_cl9_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl9_act_d, + dout(0) => p1_congr_cl9_act_q); +-- Port 1 Congruence Class 10 Act +p1_congr_cl10_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl10_act_d, + dout(0) => p1_congr_cl10_act_q); +-- Port 1 Congruence Class 11 Act +p1_congr_cl11_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl11_act_d, + dout(0) => p1_congr_cl11_act_q); +-- Port 1 Congruence Class 12 Act +p1_congr_cl12_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl12_act_d, + dout(0) => p1_congr_cl12_act_q); +-- Port 1 Congruence Class 13 Act +p1_congr_cl13_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl13_act_d, + dout(0) => p1_congr_cl13_act_q); +-- Port 1 Congruence Class 14 Act +p1_congr_cl14_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl14_act_d, + dout(0) => p1_congr_cl14_act_q); +-- Port 1 Congruence Class 15 Act +p1_congr_cl15_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl15_act_d, + dout(0) => p1_congr_cl15_act_q); +-- Port 1 Congruence Class 16 Act +p1_congr_cl16_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl16_act_d, + dout(0) => p1_congr_cl16_act_q); +-- Port 1 Congruence Class 17 Act +p1_congr_cl17_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl17_act_d, + dout(0) => p1_congr_cl17_act_q); +-- Port 1 Congruence Class 18 Act +p1_congr_cl18_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl18_act_d, + dout(0) => p1_congr_cl18_act_q); +-- Port 1 Congruence Class 19 Act +p1_congr_cl19_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl19_act_d, + dout(0) => p1_congr_cl19_act_q); +-- Port 1 Congruence Class 20 Act +p1_congr_cl20_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl20_act_d, + dout(0) => p1_congr_cl20_act_q); +-- Port 1 Congruence Class 21 Act +p1_congr_cl21_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl21_act_d, + dout(0) => p1_congr_cl21_act_q); +-- Port 1 Congruence Class 22 Act +p1_congr_cl22_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl22_act_d, + dout(0) => p1_congr_cl22_act_q); +-- Port 1 Congruence Class 23 Act +p1_congr_cl23_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl23_act_d, + dout(0) => p1_congr_cl23_act_q); +-- Port 1 Congruence Class 24 Act +p1_congr_cl24_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl24_act_d, + dout(0) => p1_congr_cl24_act_q); +-- Port 1 Congruence Class 25 Act +p1_congr_cl25_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl25_act_d, + dout(0) => p1_congr_cl25_act_q); +-- Port 1 Congruence Class 26 Act +p1_congr_cl26_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl26_act_d, + dout(0) => p1_congr_cl26_act_q); +-- Port 1 Congruence Class 27 Act +p1_congr_cl27_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl27_act_d, + dout(0) => p1_congr_cl27_act_q); +-- Port 1 Congruence Class 28 Act +p1_congr_cl28_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl28_act_d, + dout(0) => p1_congr_cl28_act_q); +-- Port 1 Congruence Class 29 Act +p1_congr_cl29_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl29_act_d, + dout(0) => p1_congr_cl29_act_q); +-- Port 1 Congruence Class 30 Act +p1_congr_cl30_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl30_act_d, + dout(0) => p1_congr_cl30_act_q); +-- Port 1 Congruence Class 31 Act +p1_congr_cl31_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl31_act_d, + dout(0) => p1_congr_cl31_act_q); +-- Flush Way A Register +flush_wayA_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayA_d, + dout => flush_wayA_q); +flush_wayA_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv4_ex4_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(flush_wayA_data_offset to flush_wayA_data_offset + flush_wayA_data_d'length-1), + scout => sov(flush_wayA_data_offset to flush_wayA_data_offset + flush_wayA_data_d'length-1), + din => flush_wayA_data_d, + dout => flush_wayA_data_q); +flush_wayA_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv5_ex5_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayA_data2_d, + dout => flush_wayA_data2_q); +-- Flush Way B Register +flush_wayB_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayB_d, + dout => flush_wayB_q); +flush_wayB_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv4_ex4_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(flush_wayB_data_offset to flush_wayB_data_offset + flush_wayB_data_d'length-1), + scout => sov(flush_wayB_data_offset to flush_wayB_data_offset + flush_wayB_data_d'length-1), + din => flush_wayB_data_d, + dout => flush_wayB_data_q); +flush_wayB_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv5_ex5_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayB_data2_d, + dout => flush_wayB_data2_q); +-- Flush Way C Register +flush_wayC_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayC_d, + dout => flush_wayC_q); +flush_wayC_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv4_ex4_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(flush_wayC_data_offset to flush_wayC_data_offset + flush_wayC_data_d'length-1), + scout => sov(flush_wayC_data_offset to flush_wayC_data_offset + flush_wayC_data_d'length-1), + din => flush_wayC_data_d, + dout => flush_wayC_data_q); +flush_wayC_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv5_ex5_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayC_data2_d, + dout => flush_wayC_data2_q); +-- Flush Way D Register +flush_wayD_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayD_d, + dout => flush_wayD_q); +flush_wayD_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv4_ex4_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(flush_wayD_data_offset to flush_wayD_data_offset + flush_wayD_data_d'length-1), + scout => sov(flush_wayD_data_offset to flush_wayD_data_offset + flush_wayD_data_d'length-1), + din => flush_wayD_data_d, + dout => flush_wayD_data_q); +flush_wayD_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv5_ex5_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayD_data2_d, + dout => flush_wayD_data2_q); +-- Flush Way E Register +flush_wayE_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayE_d, + dout => flush_wayE_q); +flush_wayE_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv4_ex4_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(flush_wayE_data_offset to flush_wayE_data_offset + flush_wayE_data_d'length-1), + scout => sov(flush_wayE_data_offset to flush_wayE_data_offset + flush_wayE_data_d'length-1), + din => flush_wayE_data_d, + dout => flush_wayE_data_q); +flush_wayE_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv5_ex5_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayE_data2_d, + dout => flush_wayE_data2_q); +-- Flush Way F Register +flush_wayF_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayF_d, + dout => flush_wayF_q); +flush_wayF_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv4_ex4_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(flush_wayF_data_offset to flush_wayF_data_offset + flush_wayF_data_d'length-1), + scout => sov(flush_wayF_data_offset to flush_wayF_data_offset + flush_wayF_data_d'length-1), + din => flush_wayF_data_d, + dout => flush_wayF_data_q); +flush_wayF_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv5_ex5_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayF_data2_d, + dout => flush_wayF_data2_q); +-- Flush Way G Register +flush_wayG_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayG_d, + dout => flush_wayG_q); +flush_wayG_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv4_ex4_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(flush_wayG_data_offset to flush_wayG_data_offset + flush_wayG_data_d'length-1), + scout => sov(flush_wayG_data_offset to flush_wayG_data_offset + flush_wayG_data_d'length-1), + din => flush_wayG_data_d, + dout => flush_wayG_data_q); +flush_wayG_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv5_ex5_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayG_data2_d, + dout => flush_wayG_data2_q); +-- Flush Way H Register +flush_wayH_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayH_d, + dout => flush_wayH_q); +flush_wayH_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv4_ex4_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(flush_wayH_data_offset to flush_wayH_data_offset + flush_wayH_data_d'length-1), + scout => sov(flush_wayH_data_offset to flush_wayH_data_offset + flush_wayH_data_d'length-1), + din => flush_wayH_data_d, + dout => flush_wayH_data_q); +flush_wayH_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv5_ex5_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayH_data2_d, + dout => flush_wayH_data2_q); +ex3_flush_cline_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_flush_cline_offset), + scout => sov(ex3_flush_cline_offset), + din => ex3_flush_cline_d, + dout => ex3_flush_cline_q); +ex4_congr_cl_reg: tri_regk +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex4_congr_cl_d, + dout => ex4_congr_cl_q); +ex5_congr_cl_reg: tri_rlmreg_p +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv4_ex4_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_congr_cl_offset to ex5_congr_cl_offset + ex5_congr_cl_d'length-1), + scout => sov(ex5_congr_cl_offset to ex5_congr_cl_offset + ex5_congr_cl_d'length-1), + din => ex5_congr_cl_d, + dout => ex5_congr_cl_q); +ex6_congr_cl_reg: tri_regk +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv5_ex5_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex6_congr_cl_d, + dout => ex6_congr_cl_q); +ex7_congr_cl_reg: tri_rlmreg_p +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex7_congr_cl_offset to ex7_congr_cl_offset + ex7_congr_cl_d'length-1), + scout => sov(ex7_congr_cl_offset to ex7_congr_cl_offset + ex7_congr_cl_d'length-1), + din => ex7_congr_cl_d, + dout => ex7_congr_cl_q); +ex8_congr_cl_reg: tri_rlmreg_p +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex8_congr_cl_offset to ex8_congr_cl_offset + ex8_congr_cl_d'length-1), + scout => sov(ex8_congr_cl_offset to ex8_congr_cl_offset + ex8_congr_cl_d'length-1), + din => ex8_congr_cl_d, + dout => ex8_congr_cl_q); +ex9_congr_cl_reg: tri_rlmreg_p +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex9_congr_cl_offset to ex9_congr_cl_offset + ex9_congr_cl_d'length-1), + scout => sov(ex9_congr_cl_offset to ex9_congr_cl_offset + ex9_congr_cl_d'length-1), + din => ex9_congr_cl_d, + dout => ex9_congr_cl_q); +wayA_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(wayA_val_b_offset to wayA_val_b_offset + wayA_val_b_q'length-1), + scout => sov(wayA_val_b_offset to wayA_val_b_offset + wayA_val_b_q'length-1), + a1 => wayA_early_stg_pri, + a2 => wayA_stg_val, + b1 => wayA_later_stg_pri, + b2 => wayA_stg_val_b, + qb => wayA_val_b_q); +wayB_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(wayB_val_b_offset to wayB_val_b_offset + wayB_val_b_q'length-1), + scout => sov(wayB_val_b_offset to wayB_val_b_offset + wayB_val_b_q'length-1), + a1 => wayB_early_stg_pri, + a2 => wayB_stg_val, + b1 => wayB_later_stg_pri, + b2 => wayB_stg_val_b, + qb => wayB_val_b_q); +wayC_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(wayC_val_b_offset to wayC_val_b_offset + wayC_val_b_q'length-1), + scout => sov(wayC_val_b_offset to wayC_val_b_offset + wayC_val_b_q'length-1), + a1 => wayC_early_stg_pri, + a2 => wayC_stg_val, + b1 => wayC_later_stg_pri, + b2 => wayC_stg_val_b, + qb => wayC_val_b_q); +wayD_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(wayD_val_b_offset to wayD_val_b_offset + wayD_val_b_q'length-1), + scout => sov(wayD_val_b_offset to wayD_val_b_offset + wayD_val_b_q'length-1), + a1 => wayD_early_stg_pri, + a2 => wayD_stg_val, + b1 => wayD_later_stg_pri, + b2 => wayD_stg_val_b, + qb => wayD_val_b_q); +wayE_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(wayE_val_b_offset to wayE_val_b_offset + wayE_val_b_q'length-1), + scout => sov(wayE_val_b_offset to wayE_val_b_offset + wayE_val_b_q'length-1), + a1 => wayE_early_stg_pri, + a2 => wayE_stg_val, + b1 => wayE_later_stg_pri, + b2 => wayE_stg_val_b, + qb => wayE_val_b_q); +wayF_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(wayF_val_b_offset to wayF_val_b_offset + wayF_val_b_q'length-1), + scout => sov(wayF_val_b_offset to wayF_val_b_offset + wayF_val_b_q'length-1), + a1 => wayF_early_stg_pri, + a2 => wayF_stg_val, + b1 => wayF_later_stg_pri, + b2 => wayF_stg_val_b, + qb => wayF_val_b_q); +wayG_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(wayG_val_b_offset to wayG_val_b_offset + wayG_val_b_q'length-1), + scout => sov(wayG_val_b_offset to wayG_val_b_offset + wayG_val_b_q'length-1), + a1 => wayG_early_stg_pri, + a2 => wayG_stg_val, + b1 => wayG_later_stg_pri, + b2 => wayG_stg_val_b, + qb => wayG_val_b_q); +wayH_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(wayH_val_b_offset to wayH_val_b_offset + wayH_val_b_q'length-1), + scout => sov(wayH_val_b_offset to wayH_val_b_offset + wayH_val_b_q'length-1), + a1 => wayH_early_stg_pri, + a2 => wayH_stg_val, + b1 => wayH_later_stg_pri, + b2 => wayH_stg_val_b, + qb => wayH_val_b_q); +ex3_wayA_fxubyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayA_fxubyp_val_offset), + scout => sov(ex3_wayA_fxubyp_val_offset), + din => ex3_wayA_fxubyp_val_d, + dout => ex3_wayA_fxubyp_val_q); +ex3_wayB_fxubyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayB_fxubyp_val_offset), + scout => sov(ex3_wayB_fxubyp_val_offset), + din => ex3_wayB_fxubyp_val_d, + dout => ex3_wayB_fxubyp_val_q); +ex3_wayC_fxubyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayC_fxubyp_val_offset), + scout => sov(ex3_wayC_fxubyp_val_offset), + din => ex3_wayC_fxubyp_val_d, + dout => ex3_wayC_fxubyp_val_q); +ex3_wayD_fxubyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayD_fxubyp_val_offset), + scout => sov(ex3_wayD_fxubyp_val_offset), + din => ex3_wayD_fxubyp_val_d, + dout => ex3_wayD_fxubyp_val_q); +ex3_wayE_fxubyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayE_fxubyp_val_offset), + scout => sov(ex3_wayE_fxubyp_val_offset), + din => ex3_wayE_fxubyp_val_d, + dout => ex3_wayE_fxubyp_val_q); +ex3_wayF_fxubyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayF_fxubyp_val_offset), + scout => sov(ex3_wayF_fxubyp_val_offset), + din => ex3_wayF_fxubyp_val_d, + dout => ex3_wayF_fxubyp_val_q); +ex3_wayG_fxubyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayG_fxubyp_val_offset), + scout => sov(ex3_wayG_fxubyp_val_offset), + din => ex3_wayG_fxubyp_val_d, + dout => ex3_wayG_fxubyp_val_q); +ex3_wayH_fxubyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayH_fxubyp_val_offset), + scout => sov(ex3_wayH_fxubyp_val_offset), + din => ex3_wayH_fxubyp_val_d, + dout => ex3_wayH_fxubyp_val_q); +ex4_wayA_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayA_fxubyp_val_d, + dout(0) => ex4_wayA_fxubyp_val_q); +ex4_wayB_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayB_fxubyp_val_d, + dout(0) => ex4_wayB_fxubyp_val_q); +ex4_wayC_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayC_fxubyp_val_d, + dout(0) => ex4_wayC_fxubyp_val_q); +ex4_wayD_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayD_fxubyp_val_d, + dout(0) => ex4_wayD_fxubyp_val_q); +ex4_wayE_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayE_fxubyp_val_d, + dout(0) => ex4_wayE_fxubyp_val_q); +ex4_wayF_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayF_fxubyp_val_d, + dout(0) => ex4_wayF_fxubyp_val_q); +ex4_wayG_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayG_fxubyp_val_d, + dout(0) => ex4_wayG_fxubyp_val_q); +ex4_wayH_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayH_fxubyp_val_d, + dout(0) => ex4_wayH_fxubyp_val_q); +ex3_wayA_relbyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayA_relbyp_val_offset), + scout => sov(ex3_wayA_relbyp_val_offset), + din => ex3_wayA_relbyp_val_d, + dout => ex3_wayA_relbyp_val_q); +ex3_wayB_relbyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayB_relbyp_val_offset), + scout => sov(ex3_wayB_relbyp_val_offset), + din => ex3_wayB_relbyp_val_d, + dout => ex3_wayB_relbyp_val_q); +ex3_wayC_relbyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayC_relbyp_val_offset), + scout => sov(ex3_wayC_relbyp_val_offset), + din => ex3_wayC_relbyp_val_d, + dout => ex3_wayC_relbyp_val_q); +ex3_wayD_relbyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayD_relbyp_val_offset), + scout => sov(ex3_wayD_relbyp_val_offset), + din => ex3_wayD_relbyp_val_d, + dout => ex3_wayD_relbyp_val_q); +ex3_wayE_relbyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayE_relbyp_val_offset), + scout => sov(ex3_wayE_relbyp_val_offset), + din => ex3_wayE_relbyp_val_d, + dout => ex3_wayE_relbyp_val_q); +ex3_wayF_relbyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayF_relbyp_val_offset), + scout => sov(ex3_wayF_relbyp_val_offset), + din => ex3_wayF_relbyp_val_d, + dout => ex3_wayF_relbyp_val_q); +ex3_wayG_relbyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayG_relbyp_val_offset), + scout => sov(ex3_wayG_relbyp_val_offset), + din => ex3_wayG_relbyp_val_d, + dout => ex3_wayG_relbyp_val_q); +ex3_wayH_relbyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayH_relbyp_val_offset), + scout => sov(ex3_wayH_relbyp_val_offset), + din => ex3_wayH_relbyp_val_d, + dout => ex3_wayH_relbyp_val_q); +ex4_wayA_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayA_relbyp_val_d, + dout(0) => ex4_wayA_relbyp_val_q); +ex4_wayB_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayB_relbyp_val_d, + dout(0) => ex4_wayB_relbyp_val_q); +ex4_wayC_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayC_relbyp_val_d, + dout(0) => ex4_wayC_relbyp_val_q); +ex4_wayD_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayD_relbyp_val_d, + dout(0) => ex4_wayD_relbyp_val_q); +ex4_wayE_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayE_relbyp_val_d, + dout(0) => ex4_wayE_relbyp_val_q); +ex4_wayF_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayF_relbyp_val_d, + dout(0) => ex4_wayF_relbyp_val_q); +ex4_wayG_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayG_relbyp_val_d, + dout(0) => ex4_wayG_relbyp_val_q); +ex4_wayH_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayH_relbyp_val_d, + dout(0) => ex4_wayH_relbyp_val_q); +ex4_xuop_wayA_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_xuop_wayA_upd_offset), + scout => sov(ex4_xuop_wayA_upd_offset), + din => ex4_xuop_wayA_upd_d, + dout => ex4_xuop_wayA_upd_q); +ex4_xuop_wayB_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_xuop_wayB_upd_offset), + scout => sov(ex4_xuop_wayB_upd_offset), + din => ex4_xuop_wayB_upd_d, + dout => ex4_xuop_wayB_upd_q); +ex4_xuop_wayC_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_xuop_wayC_upd_offset), + scout => sov(ex4_xuop_wayC_upd_offset), + din => ex4_xuop_wayC_upd_d, + dout => ex4_xuop_wayC_upd_q); +ex4_xuop_wayD_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_xuop_wayD_upd_offset), + scout => sov(ex4_xuop_wayD_upd_offset), + din => ex4_xuop_wayD_upd_d, + dout => ex4_xuop_wayD_upd_q); +ex4_xuop_wayE_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_xuop_wayE_upd_offset), + scout => sov(ex4_xuop_wayE_upd_offset), + din => ex4_xuop_wayE_upd_d, + dout => ex4_xuop_wayE_upd_q); +ex4_xuop_wayF_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_xuop_wayF_upd_offset), + scout => sov(ex4_xuop_wayF_upd_offset), + din => ex4_xuop_wayF_upd_d, + dout => ex4_xuop_wayF_upd_q); +ex4_xuop_wayG_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_xuop_wayG_upd_offset), + scout => sov(ex4_xuop_wayG_upd_offset), + din => ex4_xuop_wayG_upd_d, + dout => ex4_xuop_wayG_upd_q); +ex4_xuop_wayH_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_xuop_wayH_upd_offset), + scout => sov(ex4_xuop_wayH_upd_offset), + din => ex4_xuop_wayH_upd_d, + dout => ex4_xuop_wayH_upd_q); +ex5_xuop_wayA_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_xuop_wayA_upd_offset), + scout => sov(ex5_xuop_wayA_upd_offset), + din => ex5_xuop_wayA_upd_d, + dout => ex5_xuop_wayA_upd_q); +ex5_xuop_wayB_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_xuop_wayB_upd_offset), + scout => sov(ex5_xuop_wayB_upd_offset), + din => ex5_xuop_wayB_upd_d, + dout => ex5_xuop_wayB_upd_q); +ex5_xuop_wayC_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_xuop_wayC_upd_offset), + scout => sov(ex5_xuop_wayC_upd_offset), + din => ex5_xuop_wayC_upd_d, + dout => ex5_xuop_wayC_upd_q); +ex5_xuop_wayD_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_xuop_wayD_upd_offset), + scout => sov(ex5_xuop_wayD_upd_offset), + din => ex5_xuop_wayD_upd_d, + dout => ex5_xuop_wayD_upd_q); +ex5_xuop_wayE_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_xuop_wayE_upd_offset), + scout => sov(ex5_xuop_wayE_upd_offset), + din => ex5_xuop_wayE_upd_d, + dout => ex5_xuop_wayE_upd_q); +ex5_xuop_wayF_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_xuop_wayF_upd_offset), + scout => sov(ex5_xuop_wayF_upd_offset), + din => ex5_xuop_wayF_upd_d, + dout => ex5_xuop_wayF_upd_q); +ex5_xuop_wayG_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_xuop_wayG_upd_offset), + scout => sov(ex5_xuop_wayG_upd_offset), + din => ex5_xuop_wayG_upd_d, + dout => ex5_xuop_wayG_upd_q); +ex5_xuop_wayH_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_xuop_wayH_upd_offset), + scout => sov(ex5_xuop_wayH_upd_offset), + din => ex5_xuop_wayH_upd_d, + dout => ex5_xuop_wayH_upd_q); +inval_clr_lck_wA_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(inval_clr_lck_wA_offset), + scout => sov(inval_clr_lck_wA_offset), + din => inval_clr_lck_wA_d, + dout => inval_clr_lck_wA_q); +inval_clr_lck_wB_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(inval_clr_lck_wB_offset), + scout => sov(inval_clr_lck_wB_offset), + din => inval_clr_lck_wB_d, + dout => inval_clr_lck_wB_q); +inval_clr_lck_wC_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(inval_clr_lck_wC_offset), + scout => sov(inval_clr_lck_wC_offset), + din => inval_clr_lck_wC_d, + dout => inval_clr_lck_wC_q); +inval_clr_lck_wD_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(inval_clr_lck_wD_offset), + scout => sov(inval_clr_lck_wD_offset), + din => inval_clr_lck_wD_d, + dout => inval_clr_lck_wD_q); +inval_clr_lck_wE_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(inval_clr_lck_wE_offset), + scout => sov(inval_clr_lck_wE_offset), + din => inval_clr_lck_wE_d, + dout => inval_clr_lck_wE_q); +inval_clr_lck_wF_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(inval_clr_lck_wF_offset), + scout => sov(inval_clr_lck_wF_offset), + din => inval_clr_lck_wF_d, + dout => inval_clr_lck_wF_q); +inval_clr_lck_wG_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(inval_clr_lck_wG_offset), + scout => sov(inval_clr_lck_wG_offset), + din => inval_clr_lck_wG_d, + dout => inval_clr_lck_wG_q); +inval_clr_lck_wH_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(inval_clr_lck_wH_offset), + scout => sov(inval_clr_lck_wH_offset), + din => inval_clr_lck_wH_d, + dout => inval_clr_lck_wH_q); +ex4_wayA_val_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex4_wayA_val_d, + dout => ex4_wayA_val_q); +ex4_wayB_val_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex4_wayB_val_d, + dout => ex4_wayB_val_q); +ex4_wayC_val_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex4_wayC_val_d, + dout => ex4_wayC_val_q); +ex4_wayD_val_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex4_wayD_val_d, + dout => ex4_wayD_val_q); +ex4_wayE_val_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex4_wayE_val_d, + dout => ex4_wayE_val_q); +ex4_wayF_val_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex4_wayF_val_d, + dout => ex4_wayF_val_q); +ex4_wayG_val_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex4_wayG_val_d, + dout => ex4_wayG_val_q); +ex4_wayH_val_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex4_wayH_val_d, + dout => ex4_wayH_val_q); +congr_cl_m_upd_wayA_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_m_upd_wayA_offset), + scout => sov(congr_cl_m_upd_wayA_offset), + din => congr_cl_m_upd_wayA_d, + dout => congr_cl_m_upd_wayA_q); +congr_cl_m_upd_wayB_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_m_upd_wayB_offset), + scout => sov(congr_cl_m_upd_wayB_offset), + din => congr_cl_m_upd_wayB_d, + dout => congr_cl_m_upd_wayB_q); +congr_cl_m_upd_wayC_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_m_upd_wayC_offset), + scout => sov(congr_cl_m_upd_wayC_offset), + din => congr_cl_m_upd_wayC_d, + dout => congr_cl_m_upd_wayC_q); +congr_cl_m_upd_wayD_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_m_upd_wayD_offset), + scout => sov(congr_cl_m_upd_wayD_offset), + din => congr_cl_m_upd_wayD_d, + dout => congr_cl_m_upd_wayD_q); +congr_cl_m_upd_wayE_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_m_upd_wayE_offset), + scout => sov(congr_cl_m_upd_wayE_offset), + din => congr_cl_m_upd_wayE_d, + dout => congr_cl_m_upd_wayE_q); +congr_cl_m_upd_wayF_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_m_upd_wayF_offset), + scout => sov(congr_cl_m_upd_wayF_offset), + din => congr_cl_m_upd_wayF_d, + dout => congr_cl_m_upd_wayF_q); +congr_cl_m_upd_wayG_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_m_upd_wayG_offset), + scout => sov(congr_cl_m_upd_wayG_offset), + din => congr_cl_m_upd_wayG_d, + dout => congr_cl_m_upd_wayG_q); +congr_cl_m_upd_wayH_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_m_upd_wayH_offset), + scout => sov(congr_cl_m_upd_wayH_offset), + din => congr_cl_m_upd_wayH_d, + dout => congr_cl_m_upd_wayH_q); +ex2_congr_cl_reg: tri_regk +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv1_ex1_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex2_congr_cl_d, + dout => ex2_congr_cl_q); +ex3_congr_cl_reg: tri_rlmreg_p +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_congr_cl_offset to ex3_congr_cl_offset + ex3_congr_cl_d'length-1), + scout => sov(ex3_congr_cl_offset to ex3_congr_cl_offset + ex3_congr_cl_d'length-1), + din => ex3_congr_cl_d, + dout => ex3_congr_cl_q); +rel_congr_cl_reg: tri_regk +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_congr_cl_d, + dout => rel_congr_cl_q); +rel24_congr_cl_reg: tri_rlmreg_p +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel24_congr_cl_offset to rel24_congr_cl_offset + rel24_congr_cl_d'length-1), + scout => sov(rel24_congr_cl_offset to rel24_congr_cl_offset + rel24_congr_cl_d'length-1), + din => rel24_congr_cl_d, + dout => rel24_congr_cl_q); +relu_congr_cl_reg: tri_regk +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => relu_congr_cl_d, + dout => relu_congr_cl_q); +relu_s_congr_cl_reg: tri_rlmreg_p +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_perr_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(relu_s_congr_cl_offset to relu_s_congr_cl_offset + relu_s_congr_cl_d'length-1), + scout => sov(relu_s_congr_cl_offset to relu_s_congr_cl_offset + relu_s_congr_cl_d'length-1), + din => relu_s_congr_cl_d, + dout => relu_s_congr_cl_q); +reload_way_clr_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_way_clr_offset to reload_way_clr_offset + reload_way_clr_d'length-1), + scout => sov(reload_way_clr_offset to reload_way_clr_offset + reload_way_clr_d'length-1), + din => reload_way_clr_d, + dout => reload_way_clr_q); +ex4_watchSet_coll_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_watchSet_coll_offset), + scout => sov(ex4_watchSet_coll_offset), + din => ex4_watchSet_coll_d, + dout => ex4_watchSet_coll_q); +rel_wayA_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_wayA_val_b_offset to rel_wayA_val_b_offset + rel_wayA_val_b_q'length-1), + scout => sov(rel_wayA_val_b_offset to rel_wayA_val_b_offset + rel_wayA_val_b_q'length-1), + a1 => rel_wayA_early_stg_pri, + a2 => rel_wayA_stg_val, + b1 => rel_wayA_later_stg_pri, + b2 => rel_wayA_stg_val_b, + qb => rel_wayA_val_b_q); +rel_wayB_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_wayB_val_b_offset to rel_wayB_val_b_offset + rel_wayB_val_b_q'length-1), + scout => sov(rel_wayB_val_b_offset to rel_wayB_val_b_offset + rel_wayB_val_b_q'length-1), + a1 => rel_wayB_early_stg_pri, + a2 => rel_wayB_stg_val, + b1 => rel_wayB_later_stg_pri, + b2 => rel_wayB_stg_val_b, + qb => rel_wayB_val_b_q); +rel_wayC_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_wayC_val_b_offset to rel_wayC_val_b_offset + rel_wayC_val_b_q'length-1), + scout => sov(rel_wayC_val_b_offset to rel_wayC_val_b_offset + rel_wayC_val_b_q'length-1), + a1 => rel_wayC_early_stg_pri, + a2 => rel_wayC_stg_val, + b1 => rel_wayC_later_stg_pri, + b2 => rel_wayC_stg_val_b, + qb => rel_wayC_val_b_q); +rel_wayD_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_wayD_val_b_offset to rel_wayD_val_b_offset + rel_wayD_val_b_q'length-1), + scout => sov(rel_wayD_val_b_offset to rel_wayD_val_b_offset + rel_wayD_val_b_q'length-1), + a1 => rel_wayD_early_stg_pri, + a2 => rel_wayD_stg_val, + b1 => rel_wayD_later_stg_pri, + b2 => rel_wayD_stg_val_b, + qb => rel_wayD_val_b_q); +rel_wayE_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_wayE_val_b_offset to rel_wayE_val_b_offset + rel_wayE_val_b_q'length-1), + scout => sov(rel_wayE_val_b_offset to rel_wayE_val_b_offset + rel_wayE_val_b_q'length-1), + a1 => rel_wayE_early_stg_pri, + a2 => rel_wayE_stg_val, + b1 => rel_wayE_later_stg_pri, + b2 => rel_wayE_stg_val_b, + qb => rel_wayE_val_b_q); +rel_wayF_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_wayF_val_b_offset to rel_wayF_val_b_offset + rel_wayF_val_b_q'length-1), + scout => sov(rel_wayF_val_b_offset to rel_wayF_val_b_offset + rel_wayF_val_b_q'length-1), + a1 => rel_wayF_early_stg_pri, + a2 => rel_wayF_stg_val, + b1 => rel_wayF_later_stg_pri, + b2 => rel_wayF_stg_val_b, + qb => rel_wayF_val_b_q); +rel_wayG_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_wayG_val_b_offset to rel_wayG_val_b_offset + rel_wayG_val_b_q'length-1), + scout => sov(rel_wayG_val_b_offset to rel_wayG_val_b_offset + rel_wayG_val_b_q'length-1), + a1 => rel_wayG_early_stg_pri, + a2 => rel_wayG_stg_val, + b1 => rel_wayG_later_stg_pri, + b2 => rel_wayG_stg_val_b, + qb => rel_wayG_val_b_q); +rel_wayH_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_wayH_val_b_offset to rel_wayH_val_b_offset + rel_wayH_val_b_q'length-1), + scout => sov(rel_wayH_val_b_offset to rel_wayH_val_b_offset + rel_wayH_val_b_q'length-1), + a1 => rel_wayH_early_stg_pri, + a2 => rel_wayH_stg_val, + b1 => rel_wayH_later_stg_pri, + b2 => rel_wayH_stg_val_b, + qb => rel_wayH_val_b_q); +rel24_wayA_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayA_fxubyp_val_d, + dout(0) => rel24_wayA_fxubyp_val_q); +rel24_wayB_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayB_fxubyp_val_d, + dout(0) => rel24_wayB_fxubyp_val_q); +rel24_wayC_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayC_fxubyp_val_d, + dout(0) => rel24_wayC_fxubyp_val_q); +rel24_wayD_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayD_fxubyp_val_d, + dout(0) => rel24_wayD_fxubyp_val_q); +rel24_wayE_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayE_fxubyp_val_d, + dout(0) => rel24_wayE_fxubyp_val_q); +rel24_wayF_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayF_fxubyp_val_d, + dout(0) => rel24_wayF_fxubyp_val_q); +rel24_wayG_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayG_fxubyp_val_d, + dout(0) => rel24_wayG_fxubyp_val_q); +rel24_wayH_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayH_fxubyp_val_d, + dout(0) => rel24_wayH_fxubyp_val_q); +rel24_wayA_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayA_relbyp_val_d, + dout(0) => rel24_wayA_relbyp_val_q); +rel24_wayB_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayB_relbyp_val_d, + dout(0) => rel24_wayB_relbyp_val_q); +rel24_wayC_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayC_relbyp_val_d, + dout(0) => rel24_wayC_relbyp_val_q); +rel24_wayD_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayD_relbyp_val_d, + dout(0) => rel24_wayD_relbyp_val_q); +rel24_wayE_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayE_relbyp_val_d, + dout(0) => rel24_wayE_relbyp_val_q); +rel24_wayF_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayF_relbyp_val_d, + dout(0) => rel24_wayF_relbyp_val_q); +rel24_wayG_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayG_relbyp_val_d, + dout(0) => rel24_wayG_relbyp_val_q); +rel24_wayH_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayH_relbyp_val_d, + dout(0) => rel24_wayH_relbyp_val_q); +rel_val_stg2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_val_stg2_offset), + scout => sov(rel_val_stg2_offset), + din => rel_val_stg2_d, + dout => rel_val_stg2_q); +rel_val_clr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_val_clr_offset), + scout => sov(rel_val_clr_offset), + din => rel_val_clr_d, + dout => rel_val_clr_q); +rel_port_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_port_upd_offset), + scout => sov(rel_port_upd_offset), + din => rel_port_upd_d, + dout => rel_port_upd_q); +rel_val_stg4_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_val_stg4_offset), + scout => sov(rel_val_stg4_offset), + din => rel_val_stg4_d, + dout => rel_val_stg4_q); +rel_binv_stg4_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_binv_stg4_offset), + scout => sov(rel_binv_stg4_offset), + din => rel_binv_stg4_d, + dout => rel_binv_stg4_q); +back_inval_stg3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(back_inval_stg3_offset), + scout => sov(back_inval_stg3_offset), + din => back_inval_stg3_d, + dout => back_inval_stg3_q); +back_inval_stg4_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(back_inval_stg4_offset), + scout => sov(back_inval_stg4_offset), + din => back_inval_stg4_d, + dout => back_inval_stg4_q); +back_inval_stg5_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(back_inval_stg5_offset), + scout => sov(back_inval_stg5_offset), + din => back_inval_stg5_d, + dout => back_inval_stg5_q); +binv4_ex4_xuop_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv4_ex4_xuop_upd_offset), + scout => sov(binv4_ex4_xuop_upd_offset), + din => binv4_ex4_xuop_upd_d, + dout => binv4_ex4_xuop_upd_q); +binv4_ex4_dir_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv4_ex4_dir_val_offset), + scout => sov(binv4_ex4_dir_val_offset), + din => binv4_ex4_dir_val_d, + dout => binv4_ex4_dir_val_q); +ex4_dir_err_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_dir_err_val_offset), + scout => sov(ex4_dir_err_val_offset), + din => ex4_dir_err_val_d, + dout => ex4_dir_err_val_q); +ex5_dir_err_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_dir_err_val_offset), + scout => sov(ex5_dir_err_val_offset), + din => ex5_dir_err_val_d, + dout => ex5_dir_err_val_q); +ex6_dir_err_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_dir_err_val_offset), + scout => sov(ex6_dir_err_val_offset), + din => ex6_dir_err_val_d, + dout => ex6_dir_err_val_q); +derr2_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(derr2_stg_act_offset), + scout => sov(derr2_stg_act_offset), + din => derr2_stg_act_d, + dout => derr2_stg_act_q); +derr3_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(derr3_stg_act_offset), + scout => sov(derr3_stg_act_offset), + din => derr3_stg_act_d, + dout => derr3_stg_act_q); +derr4_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(derr4_stg_act_offset), + scout => sov(derr4_stg_act_offset), + din => derr4_stg_act_d, + dout => derr4_stg_act_q); +derr5_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(derr5_stg_act_offset), + scout => sov(derr5_stg_act_offset), + din => derr5_stg_act_d, + dout => derr5_stg_act_q); +my_multihit_lcb : entity tri.tri_lcbnd(tri_lcbnd) +generic map (expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + d1clk => my_multihit_d1clk, + d2clk => my_multihit_d2clk, + lclk => my_multihit_lclk); +ex4_dir_multihit_val_b_reg: entity tri.tri_inv_nlats(tri_inv_nlats) +generic map (width => 1, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + lclk => my_multihit_lclk, + d1clk => my_multihit_d1clk, + d2clk => my_multihit_d2clk, + scanin(0) => siv(ex4_dir_multihit_val_b_offset), + scanout(0) => sov(ex4_dir_multihit_val_b_offset), + d(0) => ex3_dir_multihit_val, + qb(0) => ex4_dir_multihit_val_b_q); +my_ddmh_lcb : entity tri.tri_lcbnd(tri_lcbnd) +generic map (expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + d1clk => my_ddmh_d1clk, + d2clk => my_ddmh_d2clk, + lclk => my_ddmh_lclk); +ex4_n_lsu_ddmh_flush_b_reg: entity tri.tri_inv_nlats(tri_inv_nlats) +generic map (width => 4, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + lclk => my_ddmh_lclk, + d1clk => my_ddmh_d1clk, + d2clk => my_ddmh_d2clk, + scanin => siv(ex4_n_lsu_ddmh_flush_b_offset to ex4_n_lsu_ddmh_flush_b_offset + ex4_n_lsu_ddmh_flush_b_d'length-1), + scanout => sov(ex4_n_lsu_ddmh_flush_b_offset to ex4_n_lsu_ddmh_flush_b_offset + ex4_n_lsu_ddmh_flush_b_d'length-1), + d => ex4_n_lsu_ddmh_flush_b_d, + qb => ex4_n_lsu_ddmh_flush_b_q); +dcarr_up_way_addr_reg: entity tri.tri_aoi22_nlats +generic map (width => 3, init => "000", expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + lclk => my_ddmh_lclk, + d1clk => my_ddmh_d1clk, + d2clk => my_ddmh_d2clk, + scanin => siv(dcarr_up_way_addr_offset to dcarr_up_way_addr_offset + dcarr_up_way_addr_q'length-1), + scanout => sov(dcarr_up_way_addr_offset to dcarr_up_way_addr_offset + dcarr_up_way_addr_q'length-1), + a1 => rel_up_way_addr_b, + a2 => rel_dcarr_addr_sel, + b1 => ex3_xuop_up_addr_b, + b2 => rel_dcarr_addr_sel_b, + qb => dcarr_up_way_addr_q); +reload_wayA_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayA_d, + dout => reload_wayA_q); +reload_wayB_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayB_d, + dout => reload_wayB_q); +reload_wayC_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayC_d, + dout => reload_wayC_q); +reload_wayD_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayD_d, + dout => reload_wayD_q); +reload_wayE_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayE_d, + dout => reload_wayE_q); +reload_wayF_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayF_d, + dout => reload_wayF_q); +reload_wayG_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayG_d, + dout => reload_wayG_q); +reload_wayH_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayH_d, + dout => reload_wayH_q); +rel_wayA_val_stg_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_wayA_val_stg_d, + dout => rel_wayA_val_stg_q); +rel_wayB_val_stg_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_wayB_val_stg_d, + dout => rel_wayB_val_stg_q); +rel_wayC_val_stg_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_wayC_val_stg_d, + dout => rel_wayC_val_stg_q); +rel_wayD_val_stg_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_wayD_val_stg_d, + dout => rel_wayD_val_stg_q); +rel_wayE_val_stg_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_wayE_val_stg_d, + dout => rel_wayE_val_stg_q); +rel_wayF_val_stg_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_wayF_val_stg_d, + dout => rel_wayF_val_stg_q); +rel_wayG_val_stg_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_wayG_val_stg_d, + dout => rel_wayG_val_stg_q); +rel_wayH_val_stg_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_wayH_val_stg_d, + dout => rel_wayH_val_stg_q); +reload_wayA_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_perr_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayA_data_offset to reload_wayA_data_offset + reload_wayA_data_d'length-1), + scout => sov(reload_wayA_data_offset to reload_wayA_data_offset + reload_wayA_data_d'length-1), + din => reload_wayA_data_d, + dout => reload_wayA_data_q); +reload_wayB_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_perr_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayB_data_offset to reload_wayB_data_offset + reload_wayB_data_d'length-1), + scout => sov(reload_wayB_data_offset to reload_wayB_data_offset + reload_wayB_data_d'length-1), + din => reload_wayB_data_d, + dout => reload_wayB_data_q); +reload_wayC_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_perr_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayC_data_offset to reload_wayC_data_offset + reload_wayC_data_d'length-1), + scout => sov(reload_wayC_data_offset to reload_wayC_data_offset + reload_wayC_data_d'length-1), + din => reload_wayC_data_d, + dout => reload_wayC_data_q); +reload_wayD_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_perr_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayD_data_offset to reload_wayD_data_offset + reload_wayD_data_d'length-1), + scout => sov(reload_wayD_data_offset to reload_wayD_data_offset + reload_wayD_data_d'length-1), + din => reload_wayD_data_d, + dout => reload_wayD_data_q); +reload_wayE_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_perr_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayE_data_offset to reload_wayE_data_offset + reload_wayE_data_d'length-1), + scout => sov(reload_wayE_data_offset to reload_wayE_data_offset + reload_wayE_data_d'length-1), + din => reload_wayE_data_d, + dout => reload_wayE_data_q); +reload_wayF_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_perr_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayF_data_offset to reload_wayF_data_offset + reload_wayF_data_d'length-1), + scout => sov(reload_wayF_data_offset to reload_wayF_data_offset + reload_wayF_data_d'length-1), + din => reload_wayF_data_d, + dout => reload_wayF_data_q); +reload_wayG_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_perr_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayG_data_offset to reload_wayG_data_offset + reload_wayG_data_d'length-1), + scout => sov(reload_wayG_data_offset to reload_wayG_data_offset + reload_wayG_data_d'length-1), + din => reload_wayG_data_d, + dout => reload_wayG_data_q); +reload_wayH_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_perr_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayH_data_offset to reload_wayH_data_offset + reload_wayH_data_d'length-1), + scout => sov(reload_wayH_data_offset to reload_wayH_data_offset + reload_wayH_data_d'length-1), + din => reload_wayH_data_d, + dout => reload_wayH_data_q); +reload_wayA_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel4_perr_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayA_data2_d, + dout => reload_wayA_data2_q); +reload_wayB_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel4_perr_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayB_data2_d, + dout => reload_wayB_data2_q); +reload_wayC_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel4_perr_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayC_data2_d, + dout => reload_wayC_data2_q); +reload_wayD_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel4_perr_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayD_data2_d, + dout => reload_wayD_data2_q); +reload_wayE_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel4_perr_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayE_data2_d, + dout => reload_wayE_data2_q); +reload_wayF_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel4_perr_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayF_data2_d, + dout => reload_wayF_data2_q); +reload_wayG_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel4_perr_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayG_data2_d, + dout => reload_wayG_data2_q); +reload_wayH_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel4_perr_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayH_data2_d, + dout => reload_wayH_data2_q); +binv_wayA_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayA_upd_offset), + scout => sov(binv_wayA_upd_offset), + din => binv_wayA_upd_d, + dout => binv_wayA_upd_q); +binv_wayB_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayB_upd_offset), + scout => sov(binv_wayB_upd_offset), + din => binv_wayB_upd_d, + dout => binv_wayB_upd_q); +binv_wayC_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayC_upd_offset), + scout => sov(binv_wayC_upd_offset), + din => binv_wayC_upd_d, + dout => binv_wayC_upd_q); +binv_wayD_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayD_upd_offset), + scout => sov(binv_wayD_upd_offset), + din => binv_wayD_upd_d, + dout => binv_wayD_upd_q); +binv_wayE_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayE_upd_offset), + scout => sov(binv_wayE_upd_offset), + din => binv_wayE_upd_d, + dout => binv_wayE_upd_q); +binv_wayF_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayF_upd_offset), + scout => sov(binv_wayF_upd_offset), + din => binv_wayF_upd_d, + dout => binv_wayF_upd_q); +binv_wayG_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayG_upd_offset), + scout => sov(binv_wayG_upd_offset), + din => binv_wayG_upd_d, + dout => binv_wayG_upd_q); +binv_wayH_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayH_upd_offset), + scout => sov(binv_wayH_upd_offset), + din => binv_wayH_upd_d, + dout => binv_wayH_upd_q); +binv_wayA_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayA_upd2_offset), + scout => sov(binv_wayA_upd2_offset), + din => binv_wayA_upd2_d, + dout => binv_wayA_upd2_q); +binv_wayB_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayB_upd2_offset), + scout => sov(binv_wayB_upd2_offset), + din => binv_wayB_upd2_d, + dout => binv_wayB_upd2_q); +binv_wayC_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayC_upd2_offset), + scout => sov(binv_wayC_upd2_offset), + din => binv_wayC_upd2_d, + dout => binv_wayC_upd2_q); +binv_wayD_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayD_upd2_offset), + scout => sov(binv_wayD_upd2_offset), + din => binv_wayD_upd2_d, + dout => binv_wayD_upd2_q); +binv_wayE_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayE_upd2_offset), + scout => sov(binv_wayE_upd2_offset), + din => binv_wayE_upd2_d, + dout => binv_wayE_upd2_q); +binv_wayF_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayF_upd2_offset), + scout => sov(binv_wayF_upd2_offset), + din => binv_wayF_upd2_d, + dout => binv_wayF_upd2_q); +binv_wayG_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayG_upd2_offset), + scout => sov(binv_wayG_upd2_offset), + din => binv_wayG_upd2_d, + dout => binv_wayG_upd2_q); +binv_wayH_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayH_upd2_offset), + scout => sov(binv_wayH_upd2_offset), + din => binv_wayH_upd2_d, + dout => binv_wayH_upd2_q); +binv_wayA_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayA_upd3_offset), + scout => sov(binv_wayA_upd3_offset), + din => binv_wayA_upd3_d, + dout => binv_wayA_upd3_q); +binv_wayB_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayB_upd3_offset), + scout => sov(binv_wayB_upd3_offset), + din => binv_wayB_upd3_d, + dout => binv_wayB_upd3_q); +binv_wayC_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayC_upd3_offset), + scout => sov(binv_wayC_upd3_offset), + din => binv_wayC_upd3_d, + dout => binv_wayC_upd3_q); +binv_wayD_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayD_upd3_offset), + scout => sov(binv_wayD_upd3_offset), + din => binv_wayD_upd3_d, + dout => binv_wayD_upd3_q); +binv_wayE_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayE_upd3_offset), + scout => sov(binv_wayE_upd3_offset), + din => binv_wayE_upd3_d, + dout => binv_wayE_upd3_q); +binv_wayF_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayF_upd3_offset), + scout => sov(binv_wayF_upd3_offset), + din => binv_wayF_upd3_d, + dout => binv_wayF_upd3_q); +binv_wayG_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayG_upd3_offset), + scout => sov(binv_wayG_upd3_offset), + din => binv_wayG_upd3_d, + dout => binv_wayG_upd3_q); +binv_wayH_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayH_upd3_offset), + scout => sov(binv_wayH_upd3_offset), + din => binv_wayH_upd3_d, + dout => binv_wayH_upd3_q); +reload_wayA_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayA_upd_offset), + scout => sov(reload_wayA_upd_offset), + din => reload_wayA_upd_d, + dout => reload_wayA_upd_q); +reload_wayB_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayB_upd_offset), + scout => sov(reload_wayB_upd_offset), + din => reload_wayB_upd_d, + dout => reload_wayB_upd_q); +reload_wayC_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayC_upd_offset), + scout => sov(reload_wayC_upd_offset), + din => reload_wayC_upd_d, + dout => reload_wayC_upd_q); +reload_wayD_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayD_upd_offset), + scout => sov(reload_wayD_upd_offset), + din => reload_wayD_upd_d, + dout => reload_wayD_upd_q); +reload_wayE_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayE_upd_offset), + scout => sov(reload_wayE_upd_offset), + din => reload_wayE_upd_d, + dout => reload_wayE_upd_q); +reload_wayF_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayF_upd_offset), + scout => sov(reload_wayF_upd_offset), + din => reload_wayF_upd_d, + dout => reload_wayF_upd_q); +reload_wayG_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayG_upd_offset), + scout => sov(reload_wayG_upd_offset), + din => reload_wayG_upd_d, + dout => reload_wayG_upd_q); +reload_wayH_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayH_upd_offset), + scout => sov(reload_wayH_upd_offset), + din => reload_wayH_upd_d, + dout => reload_wayH_upd_q); +reload_wayA_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayA_upd2_offset), + scout => sov(reload_wayA_upd2_offset), + din => reload_wayA_upd2_d, + dout => reload_wayA_upd2_q); +reload_wayB_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayB_upd2_offset), + scout => sov(reload_wayB_upd2_offset), + din => reload_wayB_upd2_d, + dout => reload_wayB_upd2_q); +reload_wayC_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayC_upd2_offset), + scout => sov(reload_wayC_upd2_offset), + din => reload_wayC_upd2_d, + dout => reload_wayC_upd2_q); +reload_wayD_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayD_upd2_offset), + scout => sov(reload_wayD_upd2_offset), + din => reload_wayD_upd2_d, + dout => reload_wayD_upd2_q); +reload_wayE_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayE_upd2_offset), + scout => sov(reload_wayE_upd2_offset), + din => reload_wayE_upd2_d, + dout => reload_wayE_upd2_q); +reload_wayF_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayF_upd2_offset), + scout => sov(reload_wayF_upd2_offset), + din => reload_wayF_upd2_d, + dout => reload_wayF_upd2_q); +reload_wayG_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayG_upd2_offset), + scout => sov(reload_wayG_upd2_offset), + din => reload_wayG_upd2_d, + dout => reload_wayG_upd2_q); +reload_wayH_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayH_upd2_offset), + scout => sov(reload_wayH_upd2_offset), + din => reload_wayH_upd2_d, + dout => reload_wayH_upd2_q); +reload_wayA_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayA_upd3_offset), + scout => sov(reload_wayA_upd3_offset), + din => reload_wayA_upd3_d, + dout => reload_wayA_upd3_q); +reload_wayB_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayB_upd3_offset), + scout => sov(reload_wayB_upd3_offset), + din => reload_wayB_upd3_d, + dout => reload_wayB_upd3_q); +reload_wayC_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayC_upd3_offset), + scout => sov(reload_wayC_upd3_offset), + din => reload_wayC_upd3_d, + dout => reload_wayC_upd3_q); +reload_wayD_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayD_upd3_offset), + scout => sov(reload_wayD_upd3_offset), + din => reload_wayD_upd3_d, + dout => reload_wayD_upd3_q); +reload_wayE_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayE_upd3_offset), + scout => sov(reload_wayE_upd3_offset), + din => reload_wayE_upd3_d, + dout => reload_wayE_upd3_q); +reload_wayF_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayF_upd3_offset), + scout => sov(reload_wayF_upd3_offset), + din => reload_wayF_upd3_d, + dout => reload_wayF_upd3_q); +reload_wayG_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayG_upd3_offset), + scout => sov(reload_wayG_upd3_offset), + din => reload_wayG_upd3_d, + dout => reload_wayG_upd3_q); +reload_wayH_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayH_upd3_offset), + scout => sov(reload_wayH_upd3_offset), + din => reload_wayH_upd3_d, + dout => reload_wayH_upd3_q); +ex3_store_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_store_instr_offset), + scout => sov(ex3_store_instr_offset), + din => ex3_store_instr_d, + dout => ex3_store_instr_q); +ex3_lock_set_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_lock_set_offset), + scout => sov(ex3_lock_set_offset), + din => ex3_lock_set_d, + dout => ex3_lock_set_q); +ex4_lock_set_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_lock_set_offset), + scout => sov(ex4_lock_set_offset), + din => ex4_lock_set_d, + dout => ex4_lock_set_q); +ex5_lock_set_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_lock_set_offset), + scout => sov(ex5_lock_set_offset), + din => ex5_lock_set_d, + dout => ex5_lock_set_q); +ex3_lock_clr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_lock_clr_offset), + scout => sov(ex3_lock_clr_offset), + din => ex3_lock_clr_d, + dout => ex3_lock_clr_q); +ex3_xuop_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_xuop_val_offset), + scout => sov(ex3_xuop_val_offset), + din => ex3_xuop_val_d, + dout => ex3_xuop_val_q); +ex4_xuop_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_xuop_val_offset), + scout => sov(ex4_xuop_val_offset), + din => ex4_xuop_val_d, + dout => ex4_xuop_val_q); +ex5_xuop_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_xuop_val_offset), + scout => sov(ex5_xuop_val_offset), + din => ex5_xuop_val_d, + dout => ex5_xuop_val_q); +ex4_l_fld_b1_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex4_l_fld_b1_d, + dout(0) => ex4_l_fld_b1_q); +ex4_instr_enc_reg: tri_regk +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex4_instr_enc_d, + dout => ex4_instr_enc_q); +rel_lock_set_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_lock_set_offset), + scout => sov(rel_lock_set_offset), + din => rel_lock_set_d, + dout => rel_lock_set_q); +dcpar_err_stg1_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dcpar_err_stg1_offset), + scout => sov(dcpar_err_stg1_offset), + din => dcpar_err_stg1_d, + dout => dcpar_err_stg1_q); +dcpar_err_stg2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dcpar_err_stg2_offset), + scout => sov(dcpar_err_stg2_offset), + din => dcpar_err_stg2_d, + dout => dcpar_err_stg2_q); +dcpar_err_way_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dcpar_err_way_offset to dcpar_err_way_offset + dcpar_err_way_d'length-1), + scout => sov(dcpar_err_way_offset to dcpar_err_way_offset + dcpar_err_way_d'length-1), + din => dcpar_err_way_d, + dout => dcpar_err_way_q); +dcpar_err_way_inval_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dcpar_err_way_inval_offset to dcpar_err_way_inval_offset + dcpar_err_way_inval_d'length-1), + scout => sov(dcpar_err_way_inval_offset to dcpar_err_way_inval_offset + dcpar_err_way_inval_d'length-1), + din => dcpar_err_way_inval_d, + dout => dcpar_err_way_inval_q); +dcpar_err_cntr_reg: tri_rlmreg_p +generic map (width => 2, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dcpar_err_cntr_offset to dcpar_err_cntr_offset + dcpar_err_cntr_d'length-1), + scout => sov(dcpar_err_cntr_offset to dcpar_err_cntr_offset + dcpar_err_cntr_d'length-1), + din => dcpar_err_cntr_d, + dout => dcpar_err_cntr_q); +dcpar_err_ind_sel_reg: tri_rlmreg_p +generic map (width => 2, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dcpar_err_ind_sel_offset to dcpar_err_ind_sel_offset + dcpar_err_ind_sel_d'length-1), + scout => sov(dcpar_err_ind_sel_offset to dcpar_err_ind_sel_offset + dcpar_err_ind_sel_d'length-1), + din => dcpar_err_ind_sel_d, + dout => dcpar_err_ind_sel_q); +dcpar_err_push_queue_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dcpar_err_push_queue_offset), + scout => sov(dcpar_err_push_queue_offset), + din => dcpar_err_push_queue_d, + dout => dcpar_err_push_queue_q); +ex4_way_hit_reg: tri_regk +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex4_way_hit_d, + dout => ex4_way_hit_q); +ex5_way_hit_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv4_ex4_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_way_hit_offset to ex5_way_hit_offset + ex5_way_hit_d'length-1), + scout => sov(ex5_way_hit_offset to ex5_way_hit_offset + ex5_way_hit_d'length-1), + din => ex5_way_hit_d, + dout => ex5_way_hit_q); +ex6_way_hit_reg: tri_regk +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex5_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex6_way_hit_d, + dout => ex6_way_hit_q); +ex7_way_hit_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex7_way_hit_offset to ex7_way_hit_offset + ex7_way_hit_d'length-1), + scout => sov(ex7_way_hit_offset to ex7_way_hit_offset + ex7_way_hit_d'length-1), + din => ex7_way_hit_d, + dout => ex7_way_hit_q); +ex8_way_hit_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex8_way_hit_offset to ex8_way_hit_offset + ex8_way_hit_d'length-1), + scout => sov(ex8_way_hit_offset to ex8_way_hit_offset + ex8_way_hit_d'length-1), + din => ex8_way_hit_d, + dout => ex8_way_hit_q); +ex9_way_hit_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex9_way_hit_offset to ex9_way_hit_offset + ex9_way_hit_d'length-1), + scout => sov(ex9_way_hit_offset to ex9_way_hit_offset + ex9_way_hit_d'length-1), + din => ex9_way_hit_d, + dout => ex9_way_hit_q); +ex4_lose_watch_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_lose_watch_offset to ex4_lose_watch_offset + ex4_lose_watch_d'length-1), + scout => sov(ex4_lose_watch_offset to ex4_lose_watch_offset + ex4_lose_watch_d'length-1), + din => ex4_lose_watch_d, + dout => ex4_lose_watch_q); +xucr0_cslc_xuop_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xucr0_cslc_xuop_offset), + scout => sov(xucr0_cslc_xuop_offset), + din => xucr0_cslc_xuop_d, + dout => xucr0_cslc_xuop_q); +xucr0_cslc_binv_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(xucr0_cslc_binv_offset), + scout => sov(xucr0_cslc_binv_offset), + din => xucr0_cslc_binv_d, + dout => xucr0_cslc_binv_q); +dci_compl_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dci_compl_offset), + scout => sov(dci_compl_offset), + din => dci_compl_d, + dout => dci_compl_q); +dci_inval_all_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dci_inval_all_offset), + scout => sov(dci_inval_all_offset), + din => dci_inval_all_d, + dout => dci_inval_all_q); +inv2_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(inv2_val_offset), + scout => sov(inv2_val_offset), + din => inv2_val_d, + dout => inv2_val_q); +perf_lsu_evnts_reg: tri_rlmreg_p +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(perf_lsu_evnts_offset to perf_lsu_evnts_offset + perf_lsu_evnts_d'length-1), + scout => sov(perf_lsu_evnts_offset to perf_lsu_evnts_offset + perf_lsu_evnts_d'length-1), + din => perf_lsu_evnts_d, + dout => perf_lsu_evnts_q); +lock_flash_clear_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(lock_flash_clear_offset), + scout => sov(lock_flash_clear_offset), + din => lock_flash_clear_d, + dout => lock_flash_clear_q); +lock_flash_clear_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(lock_flash_clear_val_offset), + scout => sov(lock_flash_clear_val_offset), + din => lock_flash_clear_val_d, + dout => lock_flash_clear_val_q); +rel_port_wren_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_port_wren_offset), + scout => sov(rel_port_wren_offset), + din => rel_port_wren_d, + dout => rel_port_wren_q); +ex2_thrd_id_reg: tri_regk +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex2_thrd_id_d, + dout => ex2_thrd_id_q); +ex3_thrd_id_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_thrd_id_offset to ex3_thrd_id_offset + ex3_thrd_id_d'length-1), + scout => sov(ex3_thrd_id_offset to ex3_thrd_id_offset + ex3_thrd_id_d'length-1), + din => ex3_thrd_id_d, + dout => ex3_thrd_id_q); +ex4_thrd_id_reg: tri_regk +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex4_thrd_id_d, + dout => ex4_thrd_id_q); +ex5_thrd_id_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_thrd_id_offset to ex5_thrd_id_offset + ex5_thrd_id_d'length-1), + scout => sov(ex5_thrd_id_offset to ex5_thrd_id_offset + ex5_thrd_id_d'length-1), + din => ex5_thrd_id_d, + dout => ex5_thrd_id_q); +ex3_l_fld_b1_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_l_fld_b1_offset), + scout => sov(ex3_l_fld_b1_offset), + din => ex3_l_fld_b1_d, + dout => ex3_l_fld_b1_q); +ex3_watch_set_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_watch_set_offset), + scout => sov(ex3_watch_set_offset), + din => ex3_watch_set_d, + dout => ex3_watch_set_q); +ex4_watch_set_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_watch_set_offset), + scout => sov(ex4_watch_set_offset), + din => ex4_watch_set_d, + dout => ex4_watch_set_q); +ex5_watch_set_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_watch_set_offset), + scout => sov(ex5_watch_set_offset), + din => ex5_watch_set_d, + dout => ex5_watch_set_q); +ex3_watch_clr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_watch_clr_offset), + scout => sov(ex3_watch_clr_offset), + din => ex3_watch_clr_d, + dout => ex3_watch_clr_q); +ex3_watch_clr_all_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_watch_clr_all_offset), + scout => sov(ex3_watch_clr_all_offset), + din => ex3_watch_clr_all_d, + dout => ex3_watch_clr_all_q); +ex3_watch_chk_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_watch_chk_offset), + scout => sov(ex3_watch_chk_offset), + din => ex3_watch_chk_d, + dout => ex3_watch_chk_q); +ex4_watch_chk_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_watch_chk_offset), + scout => sov(ex4_watch_chk_offset), + din => ex4_watch_chk_d, + dout => ex4_watch_chk_q); +ex5_watch_chk_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_watch_chk_offset), + scout => sov(ex5_watch_chk_offset), + din => ex5_watch_chk_d, + dout => ex5_watch_chk_q); +ex3_wclr_all_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wclr_all_upd_offset), + scout => sov(ex3_wclr_all_upd_offset), + din => ex3_wclr_all_upd_d, + dout => ex3_wclr_all_upd_q); +ex4_wclr_all_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_wclr_all_val_offset), + scout => sov(ex4_wclr_all_val_offset), + din => ex4_wclr_all_val_d, + dout => ex4_wclr_all_val_q); +ex5_wclr_all_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_wclr_all_val_offset), + scout => sov(ex5_wclr_all_val_offset), + din => ex5_wclr_all_val_d, + dout => ex5_wclr_all_val_q); +ex6_wclr_all_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_wclr_all_val_offset), + scout => sov(ex6_wclr_all_val_offset), + din => ex6_wclr_all_val_d, + dout => ex6_wclr_all_val_q); +rel_thrd_id_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_thrd_id_offset to rel_thrd_id_offset + rel_thrd_id_d'length-1), + scout => sov(rel_thrd_id_offset to rel_thrd_id_offset + rel_thrd_id_d'length-1), + din => rel_thrd_id_d, + dout => rel_thrd_id_q); +rel_watch_set_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_watch_set_offset), + scout => sov(rel_watch_set_offset), + din => rel_watch_set_d, + dout => rel_watch_set_q); +ex5_cr_watch_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_cr_watch_offset), + scout => sov(ex5_cr_watch_offset), + din => ex5_cr_watch_d, + dout => ex5_cr_watch_q); +ex4_watch_clr_all_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_watch_clr_all_offset to ex4_watch_clr_all_offset + ex4_watch_clr_all_d'length-1), + scout => sov(ex4_watch_clr_all_offset to ex4_watch_clr_all_offset + ex4_watch_clr_all_d'length-1), + din => ex4_watch_clr_all_d, + dout => ex4_watch_clr_all_q); +ex5_watch_clr_all_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_watch_clr_all_offset to ex5_watch_clr_all_offset + ex5_watch_clr_all_d'length-1), + scout => sov(ex5_watch_clr_all_offset to ex5_watch_clr_all_offset + ex5_watch_clr_all_d'length-1), + din => ex5_watch_clr_all_d, + dout => ex5_watch_clr_all_q); +ex6_watch_clr_all_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_watch_clr_all_offset to ex6_watch_clr_all_offset + ex6_watch_clr_all_d'length-1), + scout => sov(ex6_watch_clr_all_offset to ex6_watch_clr_all_offset + ex6_watch_clr_all_d'length-1), + din => ex6_watch_clr_all_d, + dout => ex6_watch_clr_all_q); +ex5_watch_clr_all_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_watch_clr_all_val_offset), + scout => sov(ex5_watch_clr_all_val_offset), + din => ex5_watch_clr_all_val_d, + dout => ex5_watch_clr_all_val_q); +ex5_lost_watch_upd_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_lost_watch_upd_offset to ex5_lost_watch_upd_offset + ex5_lost_watch_upd_d'length-1), + scout => sov(ex5_lost_watch_upd_offset to ex5_lost_watch_upd_offset + ex5_lost_watch_upd_d'length-1), + din => ex5_lost_watch_upd_d, + dout => ex5_lost_watch_upd_q); +ex4_watchlost_set_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_watchlost_set_offset to ex4_watchlost_set_offset + ex4_watchlost_set_d'length-1), + scout => sov(ex4_watchlost_set_offset to ex4_watchlost_set_offset + ex4_watchlost_set_d'length-1), + din => ex4_watchlost_set_d, + dout => ex4_watchlost_set_q); +ex5_watchlost_set_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_watchlost_set_offset to ex5_watchlost_set_offset + ex5_watchlost_set_d'length-1), + scout => sov(ex5_watchlost_set_offset to ex5_watchlost_set_offset + ex5_watchlost_set_d'length-1), + din => ex5_watchlost_set_d, + dout => ex5_watchlost_set_q); +rel_lost_watch_binv_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_lost_watch_binv_offset to rel_lost_watch_binv_offset + rel_lost_watch_binv_d'length-1), + scout => sov(rel_lost_watch_binv_offset to rel_lost_watch_binv_offset + rel_lost_watch_binv_d'length-1), + din => rel_lost_watch_binv_d, + dout => rel_lost_watch_binv_q); +lost_watch_evict_ovl_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(lost_watch_evict_ovl_offset to lost_watch_evict_ovl_offset + lost_watch_evict_ovl_d'length-1), + scout => sov(lost_watch_evict_ovl_offset to lost_watch_evict_ovl_offset + lost_watch_evict_ovl_d'length-1), + din => lost_watch_evict_ovl_d, + dout => lost_watch_evict_ovl_q); +rel_lost_watch_upd_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_lost_watch_upd_offset to rel_lost_watch_upd_offset + rel_lost_watch_upd_d'length-1), + scout => sov(rel_lost_watch_upd_offset to rel_lost_watch_upd_offset + rel_lost_watch_upd_d'length-1), + din => rel_lost_watch_upd_d, + dout => rel_lost_watch_upd_q); +lost_watch_evict_val_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(lost_watch_evict_val_offset to lost_watch_evict_val_offset + lost_watch_evict_val_d'length-1), + scout => sov(lost_watch_evict_val_offset to lost_watch_evict_val_offset + lost_watch_evict_val_d'length-1), + din => lost_watch_evict_val_d, + dout => lost_watch_evict_val_q); +lost_watch_inter_thrd_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(lost_watch_inter_thrd_offset to lost_watch_inter_thrd_offset + lost_watch_inter_thrd_d'length-1), + scout => sov(lost_watch_inter_thrd_offset to lost_watch_inter_thrd_offset + lost_watch_inter_thrd_d'length-1), + din => lost_watch_inter_thrd_d, + dout => lost_watch_inter_thrd_q); +stm_watchlost_state_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(stm_watchlost_state_offset to stm_watchlost_state_offset + stm_watchlost_state_d'length-1), + scout => sov(stm_watchlost_state_offset to stm_watchlost_state_offset + stm_watchlost_state_d'length-1), + din => stm_watchlost_state_d, + dout => stm_watchlost_state_q); +ex5_xuop_p0_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_xuop_p0_upd_offset), + scout => sov(ex5_xuop_p0_upd_offset), + din => ex5_xuop_p0_upd_d, + dout => ex5_xuop_p0_upd_q); +rel_val_stgu_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_val_stgu_offset), + scout => sov(rel_val_stgu_offset), + din => rel_val_stgu_d, + dout => rel_val_stgu_q); +p0_wren_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(p0_wren_offset), + scout => sov(p0_wren_offset), + din => p0_wren_d, + dout => p0_wren_q); +p0_wren_cpy_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(p0_wren_cpy_offset), + scout => sov(p0_wren_cpy_offset), + din => p0_wren_cpy_d, + dout => p0_wren_cpy_q); +p0_wren_stg_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(p0_wren_stg_offset), + scout => sov(p0_wren_stg_offset), + din => p0_wren_stg_d, + dout => p0_wren_stg_q); +p1_wren_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(p1_wren_offset), + scout => sov(p1_wren_offset), + din => p1_wren_d, + dout => p1_wren_q); +p1_wren_cpy_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(p1_wren_cpy_offset), + scout => sov(p1_wren_cpy_offset), + din => p1_wren_cpy_d, + dout => p1_wren_cpy_q); +ex3_thrd_m_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_thrd_m_offset), + scout => sov(ex3_thrd_m_offset), + din => ex3_thrd_m_d, + dout => ex3_thrd_m_q); +ex4_thrd_m_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_thrd_m_offset), + scout => sov(ex4_thrd_m_offset), + din => ex4_thrd_m_d, + dout => ex4_thrd_m_q); +ex5_thrd_m_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_thrd_m_offset), + scout => sov(ex5_thrd_m_offset), + din => ex5_thrd_m_d, + dout => ex5_thrd_m_q); +ex6_thrd_m_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_thrd_m_offset), + scout => sov(ex6_thrd_m_offset), + din => ex6_thrd_m_d, + dout => ex6_thrd_m_q); +ex7_ld_par_err_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex7_ld_par_err_offset), + scout => sov(ex7_ld_par_err_offset), + din => ex7_ld_par_err_d, + dout => ex7_ld_par_err_q); +ex8_ld_par_err_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex8_ld_par_err_offset), + scout => sov(ex8_ld_par_err_offset), + din => ex8_ld_par_err_d, + dout => ex8_ld_par_err_q); +ex9_ld_par_err_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex9_ld_par_err_offset), + scout => sov(ex9_ld_par_err_offset), + din => ex9_ld_par_err_d, + dout => ex9_ld_par_err_q); +ex6_ld_valid_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_ld_valid_offset), + scout => sov(ex6_ld_valid_offset), + din => ex6_ld_valid_d, + dout => ex6_ld_valid_q); +ex7_ld_valid_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex7_ld_valid_offset), + scout => sov(ex7_ld_valid_offset), + din => ex7_ld_valid_d, + dout => ex7_ld_valid_q); +ex8_ld_valid_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex8_ld_valid_offset), + scout => sov(ex8_ld_valid_offset), + din => ex8_ld_valid_d, + dout => ex8_ld_valid_q); +ex9_ld_valid_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex9_ld_valid_offset), + scout => sov(ex9_ld_valid_offset), + din => ex9_ld_valid_d, + dout => ex9_ld_valid_q); +rel_in_progress_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_in_progress_offset), + scout => sov(rel_in_progress_offset), + din => rel_in_progress_d, + dout => rel_in_progress_q); +inj_dir_multihit_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(inj_dir_multihit_offset), + scout => sov(inj_dir_multihit_offset), + din => inj_dir_multihit_d, + dout => inj_dir_multihit_q); +congr_cl_ex2_ex3_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex2_ex3_cmp_offset), + scout => sov(congr_cl_ex2_ex3_cmp_offset), + din => congr_cl_ex2_ex3_cmp_d, + dout => congr_cl_ex2_ex3_cmp_q); +congr_cl_ex2_ex4_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex2_ex4_cmp_offset), + scout => sov(congr_cl_ex2_ex4_cmp_offset), + din => congr_cl_ex2_ex4_cmp_d, + dout => congr_cl_ex2_ex4_cmp_q); +congr_cl_ex2_ex5_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex2_ex5_cmp_offset), + scout => sov(congr_cl_ex2_ex5_cmp_offset), + din => congr_cl_ex2_ex5_cmp_d, + dout => congr_cl_ex2_ex5_cmp_q); +congr_cl_ex2_ex6_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex2_ex6_cmp_offset), + scout => sov(congr_cl_ex2_ex6_cmp_offset), + din => congr_cl_ex2_ex6_cmp_d, + dout => congr_cl_ex2_ex6_cmp_q); +congr_cl_ex3_ex4_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex3_ex4_cmp_offset), + scout => sov(congr_cl_ex3_ex4_cmp_offset), + din => congr_cl_ex3_ex4_cmp_d, + dout => congr_cl_ex3_ex4_cmp_q); +congr_cl_ex3_ex5_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex3_ex5_cmp_offset), + scout => sov(congr_cl_ex3_ex5_cmp_offset), + din => congr_cl_ex3_ex5_cmp_d, + dout => congr_cl_ex3_ex5_cmp_q); +congr_cl_ex3_ex6_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex3_ex6_cmp_offset), + scout => sov(congr_cl_ex3_ex6_cmp_offset), + din => congr_cl_ex3_ex6_cmp_d, + dout => congr_cl_ex3_ex6_cmp_q); +congr_cl_ex4_ex5_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex4_ex5_cmp_offset), + scout => sov(congr_cl_ex4_ex5_cmp_offset), + din => congr_cl_ex4_ex5_cmp_d, + dout => congr_cl_ex4_ex5_cmp_q); +congr_cl_ex4_ex6_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex4_ex6_cmp_offset), + scout => sov(congr_cl_ex4_ex6_cmp_offset), + din => congr_cl_ex4_ex6_cmp_d, + dout => congr_cl_ex4_ex6_cmp_q); +congr_cl_ex4_ex7_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex4_ex7_cmp_offset), + scout => sov(congr_cl_ex4_ex7_cmp_offset), + din => congr_cl_ex4_ex7_cmp_d, + dout => congr_cl_ex4_ex7_cmp_q); +congr_cl_ex2_relu_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex2_relu_cmp_offset), + scout => sov(congr_cl_ex2_relu_cmp_offset), + din => congr_cl_ex2_relu_cmp_d, + dout => congr_cl_ex2_relu_cmp_q); +congr_cl_ex2_relu_s_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex2_relu_s_cmp_offset), + scout => sov(congr_cl_ex2_relu_s_cmp_offset), + din => congr_cl_ex2_relu_s_cmp_d, + dout => congr_cl_ex2_relu_s_cmp_q); +congr_cl_ex2_rel_upd_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex2_rel_upd_cmp_offset), + scout => sov(congr_cl_ex2_rel_upd_cmp_offset), + din => congr_cl_ex2_rel_upd_cmp_d, + dout => congr_cl_ex2_rel_upd_cmp_q); +congr_cl_rel13_ex3_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_rel13_ex3_cmp_offset), + scout => sov(congr_cl_rel13_ex3_cmp_offset), + din => congr_cl_rel13_ex3_cmp_d, + dout => congr_cl_rel13_ex3_cmp_q); +congr_cl_rel13_ex4_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_rel13_ex4_cmp_offset), + scout => sov(congr_cl_rel13_ex4_cmp_offset), + din => congr_cl_rel13_ex4_cmp_d, + dout => congr_cl_rel13_ex4_cmp_q); +congr_cl_rel13_ex5_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_rel13_ex5_cmp_offset), + scout => sov(congr_cl_rel13_ex5_cmp_offset), + din => congr_cl_rel13_ex5_cmp_d, + dout => congr_cl_rel13_ex5_cmp_q); +congr_cl_rel13_ex6_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_rel13_ex6_cmp_offset), + scout => sov(congr_cl_rel13_ex6_cmp_offset), + din => congr_cl_rel13_ex6_cmp_d, + dout => congr_cl_rel13_ex6_cmp_q); +congr_cl_rel13_relu_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_rel13_relu_cmp_offset), + scout => sov(congr_cl_rel13_relu_cmp_offset), + din => congr_cl_rel13_relu_cmp_d, + dout => congr_cl_rel13_relu_cmp_q); +congr_cl_rel13_relu_s_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_rel13_relu_s_cmp_offset), + scout => sov(congr_cl_rel13_relu_s_cmp_offset), + din => congr_cl_rel13_relu_s_cmp_d, + dout => congr_cl_rel13_relu_s_cmp_q); +congr_cl_rel13_rel_upd_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_rel13_rel_upd_cmp_offset), + scout => sov(congr_cl_rel13_rel_upd_cmp_offset), + din => congr_cl_rel13_rel_upd_cmp_d, + dout => congr_cl_rel13_rel_upd_cmp_q); +rel24_congr_cl_ex4_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel24_congr_cl_ex4_cmp_offset), + scout => sov(rel24_congr_cl_ex4_cmp_offset), + din => rel24_congr_cl_ex4_cmp_d, + dout => rel24_congr_cl_ex4_cmp_q); +rel24_congr_cl_ex5_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel24_congr_cl_ex5_cmp_offset), + scout => sov(rel24_congr_cl_ex5_cmp_offset), + din => rel24_congr_cl_ex5_cmp_d, + dout => rel24_congr_cl_ex5_cmp_q); +rel24_congr_cl_ex6_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel24_congr_cl_ex6_cmp_offset), + scout => sov(rel24_congr_cl_ex6_cmp_offset), + din => rel24_congr_cl_ex6_cmp_d, + dout => rel24_congr_cl_ex6_cmp_q); +relu_congr_cl_ex5_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(relu_congr_cl_ex5_cmp_offset), + scout => sov(relu_congr_cl_ex5_cmp_offset), + din => relu_congr_cl_ex5_cmp_d, + dout => relu_congr_cl_ex5_cmp_q); +relu_congr_cl_ex6_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(relu_congr_cl_ex6_cmp_offset), + scout => sov(relu_congr_cl_ex6_cmp_offset), + din => relu_congr_cl_ex6_cmp_d, + dout => relu_congr_cl_ex6_cmp_q); +relu_congr_cl_ex7_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(relu_congr_cl_ex7_cmp_offset), + scout => sov(relu_congr_cl_ex7_cmp_offset), + din => relu_congr_cl_ex7_cmp_d, + dout => relu_congr_cl_ex7_cmp_q); +ex4_err_det_way_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_err_det_way_offset to ex4_err_det_way_offset + ex4_err_det_way_d'length-1), + scout => sov(ex4_err_det_way_offset to ex4_err_det_way_offset + ex4_err_det_way_d'length-1), + din => ex4_err_det_way_d, + dout => ex4_err_det_way_q); +ex4_perr_lck_lost_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_perr_lck_lost_offset), + scout => sov(ex4_perr_lck_lost_offset), + din => ex4_perr_lck_lost_d, + dout => ex4_perr_lck_lost_q); +ex4_perr_watch_lost_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_perr_watch_lost_offset to ex4_perr_watch_lost_offset + ex4_perr_watch_lost_d'length-1), + scout => sov(ex4_perr_watch_lost_offset to ex4_perr_watch_lost_offset + ex4_perr_watch_lost_d'length-1), + din => ex4_perr_watch_lost_d, + dout => ex4_perr_watch_lost_q); +dcperr_lock_lost_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dcperr_lock_lost_offset), + scout => sov(dcperr_lock_lost_offset), + din => dcperr_lock_lost_d, + dout => dcperr_lock_lost_q); +binv7_ex7_way_upd_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv7_ex7_way_upd_offset to binv7_ex7_way_upd_offset + binv7_ex7_way_upd_d'length-1), + scout => sov(binv7_ex7_way_upd_offset to binv7_ex7_way_upd_offset + binv7_ex7_way_upd_d'length-1), + din => binv7_ex7_way_upd_d, + dout => binv7_ex7_way_upd_q); +binv5_ex5_dir_data_reg: tri_rlmreg_p +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv4_ex4_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv5_ex5_dir_data_offset to binv5_ex5_dir_data_offset + binv5_ex5_dir_data_d'length-1), + scout => sov(binv5_ex5_dir_data_offset to binv5_ex5_dir_data_offset + binv5_ex5_dir_data_d'length-1), + din => binv5_ex5_dir_data_d, + dout => binv5_ex5_dir_data_q); +binv6_ex6_dir_data_reg: tri_regk +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv5_ex5_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => binv6_ex6_dir_data_d, + dout => binv6_ex6_dir_data_q); +binv7_ex7_dir_data_reg: tri_rlmreg_p +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv7_ex7_dir_data_offset to binv7_ex7_dir_data_offset + binv7_ex7_dir_data_d'length-1), + scout => sov(binv7_ex7_dir_data_offset to binv7_ex7_dir_data_offset + binv7_ex7_dir_data_d'length-1), + din => binv7_ex7_dir_data_d, + dout => binv7_ex7_dir_data_q); +binv5_inval_watch_val_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv5_inval_watch_val_offset to binv5_inval_watch_val_offset + binv5_inval_watch_val_d'length-1), + scout => sov(binv5_inval_watch_val_offset to binv5_inval_watch_val_offset + binv5_inval_watch_val_d'length-1), + din => binv5_inval_watch_val_d, + dout => binv5_inval_watch_val_q); +binv5_inval_lock_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv5_inval_lock_val_offset), + scout => sov(binv5_inval_lock_val_offset), + din => binv5_inval_lock_val_d, + dout => binv5_inval_lock_val_q); +my_lcb : entity tri.tri_lcbnd(tri_lcbnd) +generic map (expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + d1clk => my_d1clk, + d2clk => my_d2clk, + lclk => my_lclk); +ex4_snd_ld_l2_reg: entity tri.tri_oai22_nlats(tri_oai22_nlats) +generic map (width => 1, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + lclk => my_lclk, + d1clk => my_d1clk, + d2clk => my_d2clk, + scanin(0) => siv(ex4_snd_ld_l2_offset), + scanout(0) => sov(ex4_snd_ld_l2_offset), + a1(0) => ex3_wimge_i_bit, + a2(0) => hit_or_01234567_b, + b1(0) => ex3_load_val, + b2(0) => ex3_load_val, + qb(0) => ex4_snd_ld_l2_q); +ex4_ldq_full_flush_b_reg: entity tri.tri_oai22_nlats(tri_oai22_nlats) +generic map (width => 1, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + lclk => my_lclk, + d1clk => my_d1clk, + d2clk => my_d2clk, + scanin(0) => siv(ex4_ldq_full_flush_b_offset), + scanout(0) => sov(ex4_ldq_full_flush_b_offset), + a1(0) => ex3_l2_request, + a2(0) => hit_or_01234567_b, + b1(0) => ex3_ldq_potential_flush, + b2(0) => ex3_ldq_potential_flush, + qb(0) => ex4_ldq_full_flush_b_q); +ex4_miss_reg: entity tri.tri_inv_nlats(tri_inv_nlats) +generic map (width => 1, init => "1", expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + lclk => my_lclk, + d1clk => my_d1clk, + d2clk => my_d2clk, + scanin(0) => ex4_miss_siv, + scanout(0) => ex4_miss_sov, + d(0) => ex3_l1miss, + qb(0) => ex4_miss_q); +-- Inversion applied to ex4_dir_multihit_val_reg +ex4_miss_siv <= not siv(ex4_miss_offset); +sov(ex4_miss_offset) <= not ex4_miss_sov; +my_spare0_lcb : entity tri.tri_lcbnd(tri_lcbnd) +generic map (expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + d1clk => my_spare0_d1clk, + d2clk => my_spare0_d2clk, + lclk => my_spare0_lclk); +my_spare0_latches_reg: entity tri.tri_inv_nlats(tri_inv_nlats) +generic map (width => 17, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + lclk => my_spare0_lclk, + d1clk => my_spare0_d1clk, + d2clk => my_spare0_d2clk, + scanin => siv(my_spare0_latches_offset to my_spare0_latches_offset + my_spare0_latches_d'length-1), + scanout => sov(my_spare0_latches_offset to my_spare0_latches_offset + my_spare0_latches_d'length-1), + d => my_spare0_latches_d, + qb => my_spare0_latches_q); +my_spare1_lcb : entity tri.tri_lcbnd(tri_lcbnd) +generic map (expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + d1clk => my_spare1_d1clk, + d2clk => my_spare1_d2clk, + lclk => my_spare1_lclk); +my_spare1_latches_reg: entity tri.tri_inv_nlats(tri_inv_nlats) +generic map (width => 16, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + lclk => my_spare1_lclk, + d1clk => my_spare1_d1clk, + d2clk => my_spare1_d2clk, + scanin => siv(my_spare1_latches_offset to my_spare1_latches_offset + my_spare1_latches_d'length-1), + scanout => sov(my_spare1_latches_offset to my_spare1_latches_offset + my_spare1_latches_d'length-1), + d => my_spare1_latches_d, + qb => my_spare1_latches_q); +rel_l1dump_cslc_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_l1dump_cslc_offset), + scout => sov(rel_l1dump_cslc_offset), + din => rel_l1dump_cslc_d, + dout => rel_l1dump_cslc_q); +rel_in_prog_stg1_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_in_prog_stg1_offset), + scout => sov(rel_in_prog_stg1_offset), + din => rel_in_prog_stg1_d, + dout => rel_in_prog_stg1_q); +rel_in_prog_stg2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_in_prog_stg2_offset), + scout => sov(rel_in_prog_stg2_offset), + din => rel_in_prog_stg2_d, + dout => rel_in_prog_stg2_q); +rel_in_prog_stg3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_in_prog_stg3_offset), + scout => sov(rel_in_prog_stg3_offset), + din => rel_in_prog_stg3_d, + dout => rel_in_prog_stg3_q); +rel_in_prog_stg4_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_in_prog_stg4_offset), + scout => sov(rel_in_prog_stg4_offset), + din => rel_in_prog_stg4_d, + dout => rel_in_prog_stg4_q); +rel_in_prog_stg5_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_in_prog_stg5_offset), + scout => sov(rel_in_prog_stg5_offset), + din => rel_in_prog_stg5_d, + dout => rel_in_prog_stg5_q); +dcpar_err_stg1_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dcpar_err_stg1_act_offset), + scout => sov(dcpar_err_stg1_act_offset), + din => dcpar_err_stg1_act_d, + dout => dcpar_err_stg1_act_q); +dcpar_err_stg2_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dcpar_err_stg2_act_offset), + scout => sov(dcpar_err_stg2_act_offset), + din => dcpar_err_stg2_act_d, + dout => dcpar_err_stg2_act_q); +rel3_perr_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel3_perr_stg_act_offset), + scout => sov(rel3_perr_stg_act_offset), + din => rel3_perr_stg_act_d, + dout => rel3_perr_stg_act_q); +rel4_perr_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel4_perr_stg_act_offset), + scout => sov(rel4_perr_stg_act_offset), + din => rel4_perr_stg_act_d, + dout => rel4_perr_stg_act_q); +siv(0 TO 1247) <= sov(1 to 1247) & scan_in(0); +scan_out(0) <= sov(0); +siv(1248 TO scan_right) <= sov(1249 to scan_right) & scan_in(1); +scan_out(1) <= sov(1248); +scan_out(2) <= scan_in(2); +END XUQ_LSU_DIR_VAL16; diff --git a/rel/src/vhdl/work/xuq_lsu_dir_val32.vhdl b/rel/src/vhdl/work/xuq_lsu_dir_val32.vhdl new file mode 100644 index 0000000..3b03f9d --- /dev/null +++ b/rel/src/vhdl/work/xuq_lsu_dir_val32.vhdl @@ -0,0 +1,44524 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XU LSU L1 Data Directory Valid Register Array + +library ibm, ieee, work, tri, support; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use tri.tri_latches_pkg.all; +use support.power_logic_pkg.all; +-- ########################################################################################## +-- Directory Valids Component +-- 1) Contains an Array of Valids +-- 2) Updates Valid bits on Reloads +-- 3) Invalidates Valid bits for Flush type commands and Back Invalidates +-- 4) Outputs Valids for Congruence Class +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Flush Way Generation +-- Want to flush a Way on the following conditions +-- 1) Invalidate Type Instruction (dcbf,dcbi,dcbz,lwarx,stwcx) +-- 2) L2 Back Invalidate +-- 3) L2 Reload and overwritting a Valid Way +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- ########################################################################################## +entity xuq_lsu_dir_val32 is +generic(expand_type : integer := 2; + dc_size : natural := 15; + cl_size : natural := 6); +port( + + ex1_stg_act :in std_ulogic; + ex2_stg_act :in std_ulogic; + ex3_stg_act :in std_ulogic; + ex4_stg_act :in std_ulogic; + ex5_stg_act :in std_ulogic; + binv1_stg_act :in std_ulogic; + binv2_stg_act :in std_ulogic; + binv3_stg_act :in std_ulogic; + binv4_stg_act :in std_ulogic; + binv5_stg_act :in std_ulogic; + rel1_stg_act :in std_ulogic; + rel2_stg_act :in std_ulogic; + + ldq_rel1_early_v :in std_ulogic; + rel1_val :in std_ulogic; + rel_addr_early :in std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + rel_lock_en :in std_ulogic; + rel_l1dump_cslc :in std_ulogic; + rel3_l1dump_val :in std_ulogic; + rel4_ecc_err :in std_ulogic; + rel_watch_en :in std_ulogic; + rel_thrd_id :in std_ulogic_vector(0 to 3); + rel_way_clr_a :in std_ulogic; + rel_way_clr_b :in std_ulogic; + rel_way_clr_c :in std_ulogic; + rel_way_clr_d :in std_ulogic; + rel_way_clr_e :in std_ulogic; + rel_way_clr_f :in std_ulogic; + rel_way_clr_g :in std_ulogic; + rel_way_clr_h :in std_ulogic; + + ldq_rel3_early_v :in std_ulogic; + rel3_val :in std_ulogic; + rel_back_inval :in std_ulogic; + rel4_set_val :in std_ulogic; + rel4_recirc_val :in std_ulogic; + rel_way_wen_a :in std_ulogic; + rel_way_wen_b :in std_ulogic; + rel_way_wen_c :in std_ulogic; + rel_way_wen_d :in std_ulogic; + rel_way_wen_e :in std_ulogic; + rel_way_wen_f :in std_ulogic; + rel_way_wen_g :in std_ulogic; + rel_way_wen_h :in std_ulogic; + rel_up_way_addr_b :in std_ulogic_vector(0 to 2); + rel_dcarr_addr_en :in std_ulogic; + + xu_lsu_dci :in std_ulogic; + xu_lsu_spr_xucr0_clfc :in std_ulogic; + spr_xucr0_dcdis :in std_ulogic; + spr_xucr0_cls :in std_ulogic; + + ex1_thrd_id :in std_ulogic_vector(0 to 3); + ex1_p_addr :in std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + ex2_is_inval_op :in std_ulogic; + ex2_lock_set :in std_ulogic; + ex2_lock_clr :in std_ulogic; + ex3_cache_acc :in std_ulogic; + ex3_cache_en :in std_ulogic; + ex3_tag_way_perr :in std_ulogic_vector(0 to 7); + ex5_load_op_hit :in std_ulogic; + ex6_ld_par_err :in std_ulogic; + ex2_ldawx_instr :in std_ulogic; + ex2_wclr_instr :in std_ulogic; + ex2_wchk_val :in std_ulogic; + ex2_l_fld :in std_ulogic_vector(0 to 1); + ex2_store_instr :in std_ulogic; + ex3_load_val :in std_ulogic; + ex3_wimge_i_bit :in std_ulogic; + ex3_l2_request :in std_ulogic; + ex3_ldq_potential_flush :in std_ulogic; + + inv1_val :in std_ulogic; + + ex3_way_cmp_a :in std_ulogic; + ex3_way_cmp_b :in std_ulogic; + ex3_way_cmp_c :in std_ulogic; + ex3_way_cmp_d :in std_ulogic; + ex3_way_cmp_e :in std_ulogic; + ex3_way_cmp_f :in std_ulogic; + ex3_way_cmp_g :in std_ulogic; + ex3_way_cmp_h :in std_ulogic; + + ex2_stg_flush :in std_ulogic; + ex3_stg_flush :in std_ulogic; + ex4_stg_flush :in std_ulogic; + ex5_stg_flush :in std_ulogic; + + pc_xu_inj_dcachedir_multihit :in std_ulogic; + + ex4_way_a_dir :out std_ulogic_vector(0 to 5); + ex4_way_b_dir :out std_ulogic_vector(0 to 5); + ex4_way_c_dir :out std_ulogic_vector(0 to 5); + ex4_way_d_dir :out std_ulogic_vector(0 to 5); + ex4_way_e_dir :out std_ulogic_vector(0 to 5); + ex4_way_f_dir :out std_ulogic_vector(0 to 5); + ex4_way_g_dir :out std_ulogic_vector(0 to 5); + ex4_way_h_dir :out std_ulogic_vector(0 to 5); + + ex4_way_a_hit :out std_ulogic; + ex4_way_b_hit :out std_ulogic; + ex4_way_c_hit :out std_ulogic; + ex4_way_d_hit :out std_ulogic; + ex4_way_e_hit :out std_ulogic; + ex4_way_f_hit :out std_ulogic; + ex4_way_g_hit :out std_ulogic; + ex4_way_h_hit :out std_ulogic; + + ex3_cClass_upd_way_a :out std_ulogic; + ex3_cClass_upd_way_b :out std_ulogic; + ex3_cClass_upd_way_c :out std_ulogic; + ex3_cClass_upd_way_d :out std_ulogic; + ex3_cClass_upd_way_e :out std_ulogic; + ex3_cClass_upd_way_f :out std_ulogic; + ex3_cClass_upd_way_g :out std_ulogic; + ex3_cClass_upd_way_h :out std_ulogic; + + ex2_lockwatchSet_rel_coll :out std_ulogic; + ex3_wclr_all_flush :out std_ulogic; + + ex3_hit :out std_ulogic; + ex3_dir_perr_det :out std_ulogic; + ex4_dir_multihit_det :out std_ulogic; + ex4_n_lsu_ddmh_flush :out std_ulogic_vector(0 to 3); + ex4_ldq_full_flush :out std_ulogic; + ex4_miss :out std_ulogic; + ex4_snd_ld_l2 :out std_ulogic; + dcpar_err_flush :out std_ulogic; + pe_recov_begin :out std_ulogic; + + lsu_xu_ex5_cr_rslt :out std_ulogic; + + rel_way_val_a :out std_ulogic; + rel_way_val_b :out std_ulogic; + rel_way_val_c :out std_ulogic; + rel_way_val_d :out std_ulogic; + rel_way_val_e :out std_ulogic; + rel_way_val_f :out std_ulogic; + rel_way_val_g :out std_ulogic; + rel_way_val_h :out std_ulogic; + + rel_way_lock_a :out std_ulogic; + rel_way_lock_b :out std_ulogic; + rel_way_lock_c :out std_ulogic; + rel_way_lock_d :out std_ulogic; + rel_way_lock_e :out std_ulogic; + rel_way_lock_f :out std_ulogic; + rel_way_lock_g :out std_ulogic; + rel_way_lock_h :out std_ulogic; + + dcarr_up_way_addr :out std_ulogic_vector(0 to 2); + + lsu_xu_perf_events :out std_ulogic_vector(0 to 16); + + lsu_xu_spr_xucr0_cslc_xuop :out std_ulogic; + lsu_xu_spr_xucr0_cslc_binv :out std_ulogic; + + dc_val_dbg_data :out std_ulogic_vector(0 to 293); + + vdd :inout power_logic; + gnd :inout power_logic; + nclk :in clk_logic; + sg_0 :in std_ulogic; + func_sl_thold_0_b :in std_ulogic; + func_sl_force :in std_ulogic; + func_slp_sl_thold_0_b :in std_ulogic; + func_slp_sl_force :in std_ulogic; + func_nsl_thold_0_b :in std_ulogic; + func_nsl_force :in std_ulogic; + func_slp_nsl_thold_0_b :in std_ulogic; + func_slp_nsl_force :in std_ulogic; + d_mode_dc :in std_ulogic; + delay_lclkr_dc :in std_ulogic; + mpw1_dc_b :in std_ulogic; + mpw2_dc_b :in std_ulogic; + scan_in :in std_ulogic_vector(0 to 2); + scan_out :out std_ulogic_vector(0 to 2) + ); +-- synopsys translate_off +-- synopsys translate_on +end xuq_lsu_dir_val32; +---- +ARCHITECTURE XUQ_LSU_DIR_VAL32 + OF XUQ_LSU_DIR_VAL32 + IS +---------------------------- +-- components +---------------------------- +---------------------------- +-- constants +---------------------------- +constant congr_cl0_wA_offset :natural := 0; +constant congr_cl0_wB_offset :natural := congr_cl0_wA_offset + 6; +constant congr_cl0_wC_offset :natural := congr_cl0_wB_offset + 6; +constant congr_cl0_wD_offset :natural := congr_cl0_wC_offset + 6; +constant congr_cl0_wE_offset :natural := congr_cl0_wD_offset + 6; +constant congr_cl0_wF_offset :natural := congr_cl0_wE_offset + 6; +constant congr_cl0_wG_offset :natural := congr_cl0_wF_offset + 6; +constant congr_cl0_wH_offset :natural := congr_cl0_wG_offset + 6; +constant congr_cl1_wA_offset :natural := congr_cl0_wH_offset + 6; +constant congr_cl1_wB_offset :natural := congr_cl1_wA_offset + 6; +constant congr_cl1_wC_offset :natural := congr_cl1_wB_offset + 6; +constant congr_cl1_wD_offset :natural := congr_cl1_wC_offset + 6; +constant congr_cl1_wE_offset :natural := congr_cl1_wD_offset + 6; +constant congr_cl1_wF_offset :natural := congr_cl1_wE_offset + 6; +constant congr_cl1_wG_offset :natural := congr_cl1_wF_offset + 6; +constant congr_cl1_wH_offset :natural := congr_cl1_wG_offset + 6; +constant congr_cl2_wA_offset :natural := congr_cl1_wH_offset + 6; +constant congr_cl2_wB_offset :natural := congr_cl2_wA_offset + 6; +constant congr_cl2_wC_offset :natural := congr_cl2_wB_offset + 6; +constant congr_cl2_wD_offset :natural := congr_cl2_wC_offset + 6; +constant congr_cl2_wE_offset :natural := congr_cl2_wD_offset + 6; +constant congr_cl2_wF_offset :natural := congr_cl2_wE_offset + 6; +constant congr_cl2_wG_offset :natural := congr_cl2_wF_offset + 6; +constant congr_cl2_wH_offset :natural := congr_cl2_wG_offset + 6; +constant congr_cl3_wA_offset :natural := congr_cl2_wH_offset + 6; +constant congr_cl3_wB_offset :natural := congr_cl3_wA_offset + 6; +constant congr_cl3_wC_offset :natural := congr_cl3_wB_offset + 6; +constant congr_cl3_wD_offset :natural := congr_cl3_wC_offset + 6; +constant congr_cl3_wE_offset :natural := congr_cl3_wD_offset + 6; +constant congr_cl3_wF_offset :natural := congr_cl3_wE_offset + 6; +constant congr_cl3_wG_offset :natural := congr_cl3_wF_offset + 6; +constant congr_cl3_wH_offset :natural := congr_cl3_wG_offset + 6; +constant congr_cl4_wA_offset :natural := congr_cl3_wH_offset + 6; +constant congr_cl4_wB_offset :natural := congr_cl4_wA_offset + 6; +constant congr_cl4_wC_offset :natural := congr_cl4_wB_offset + 6; +constant congr_cl4_wD_offset :natural := congr_cl4_wC_offset + 6; +constant congr_cl4_wE_offset :natural := congr_cl4_wD_offset + 6; +constant congr_cl4_wF_offset :natural := congr_cl4_wE_offset + 6; +constant congr_cl4_wG_offset :natural := congr_cl4_wF_offset + 6; +constant congr_cl4_wH_offset :natural := congr_cl4_wG_offset + 6; +constant congr_cl5_wA_offset :natural := congr_cl4_wH_offset + 6; +constant congr_cl5_wB_offset :natural := congr_cl5_wA_offset + 6; +constant congr_cl5_wC_offset :natural := congr_cl5_wB_offset + 6; +constant congr_cl5_wD_offset :natural := congr_cl5_wC_offset + 6; +constant congr_cl5_wE_offset :natural := congr_cl5_wD_offset + 6; +constant congr_cl5_wF_offset :natural := congr_cl5_wE_offset + 6; +constant congr_cl5_wG_offset :natural := congr_cl5_wF_offset + 6; +constant congr_cl5_wH_offset :natural := congr_cl5_wG_offset + 6; +constant congr_cl6_wA_offset :natural := congr_cl5_wH_offset + 6; +constant congr_cl6_wB_offset :natural := congr_cl6_wA_offset + 6; +constant congr_cl6_wC_offset :natural := congr_cl6_wB_offset + 6; +constant congr_cl6_wD_offset :natural := congr_cl6_wC_offset + 6; +constant congr_cl6_wE_offset :natural := congr_cl6_wD_offset + 6; +constant congr_cl6_wF_offset :natural := congr_cl6_wE_offset + 6; +constant congr_cl6_wG_offset :natural := congr_cl6_wF_offset + 6; +constant congr_cl6_wH_offset :natural := congr_cl6_wG_offset + 6; +constant congr_cl7_wA_offset :natural := congr_cl6_wH_offset + 6; +constant congr_cl7_wB_offset :natural := congr_cl7_wA_offset + 6; +constant congr_cl7_wC_offset :natural := congr_cl7_wB_offset + 6; +constant congr_cl7_wD_offset :natural := congr_cl7_wC_offset + 6; +constant congr_cl7_wE_offset :natural := congr_cl7_wD_offset + 6; +constant congr_cl7_wF_offset :natural := congr_cl7_wE_offset + 6; +constant congr_cl7_wG_offset :natural := congr_cl7_wF_offset + 6; +constant congr_cl7_wH_offset :natural := congr_cl7_wG_offset + 6; +constant congr_cl8_wA_offset :natural := congr_cl7_wH_offset + 6; +constant congr_cl8_wB_offset :natural := congr_cl8_wA_offset + 6; +constant congr_cl8_wC_offset :natural := congr_cl8_wB_offset + 6; +constant congr_cl8_wD_offset :natural := congr_cl8_wC_offset + 6; +constant congr_cl8_wE_offset :natural := congr_cl8_wD_offset + 6; +constant congr_cl8_wF_offset :natural := congr_cl8_wE_offset + 6; +constant congr_cl8_wG_offset :natural := congr_cl8_wF_offset + 6; +constant congr_cl8_wH_offset :natural := congr_cl8_wG_offset + 6; +constant congr_cl9_wA_offset :natural := congr_cl8_wH_offset + 6; +constant congr_cl9_wB_offset :natural := congr_cl9_wA_offset + 6; +constant congr_cl9_wC_offset :natural := congr_cl9_wB_offset + 6; +constant congr_cl9_wD_offset :natural := congr_cl9_wC_offset + 6; +constant congr_cl9_wE_offset :natural := congr_cl9_wD_offset + 6; +constant congr_cl9_wF_offset :natural := congr_cl9_wE_offset + 6; +constant congr_cl9_wG_offset :natural := congr_cl9_wF_offset + 6; +constant congr_cl9_wH_offset :natural := congr_cl9_wG_offset + 6; +constant congr_cl10_wA_offset :natural := congr_cl9_wH_offset + 6; +constant congr_cl10_wB_offset :natural := congr_cl10_wA_offset + 6; +constant congr_cl10_wC_offset :natural := congr_cl10_wB_offset + 6; +constant congr_cl10_wD_offset :natural := congr_cl10_wC_offset + 6; +constant congr_cl10_wE_offset :natural := congr_cl10_wD_offset + 6; +constant congr_cl10_wF_offset :natural := congr_cl10_wE_offset + 6; +constant congr_cl10_wG_offset :natural := congr_cl10_wF_offset + 6; +constant congr_cl10_wH_offset :natural := congr_cl10_wG_offset + 6; +constant congr_cl11_wA_offset :natural := congr_cl10_wH_offset + 6; +constant congr_cl11_wB_offset :natural := congr_cl11_wA_offset + 6; +constant congr_cl11_wC_offset :natural := congr_cl11_wB_offset + 6; +constant congr_cl11_wD_offset :natural := congr_cl11_wC_offset + 6; +constant congr_cl11_wE_offset :natural := congr_cl11_wD_offset + 6; +constant congr_cl11_wF_offset :natural := congr_cl11_wE_offset + 6; +constant congr_cl11_wG_offset :natural := congr_cl11_wF_offset + 6; +constant congr_cl11_wH_offset :natural := congr_cl11_wG_offset + 6; +constant congr_cl12_wA_offset :natural := congr_cl11_wH_offset + 6; +constant congr_cl12_wB_offset :natural := congr_cl12_wA_offset + 6; +constant congr_cl12_wC_offset :natural := congr_cl12_wB_offset + 6; +constant congr_cl12_wD_offset :natural := congr_cl12_wC_offset + 6; +constant congr_cl12_wE_offset :natural := congr_cl12_wD_offset + 6; +constant congr_cl12_wF_offset :natural := congr_cl12_wE_offset + 6; +constant congr_cl12_wG_offset :natural := congr_cl12_wF_offset + 6; +constant congr_cl12_wH_offset :natural := congr_cl12_wG_offset + 6; +constant congr_cl13_wA_offset :natural := congr_cl12_wH_offset + 6; +constant congr_cl13_wB_offset :natural := congr_cl13_wA_offset + 6; +constant congr_cl13_wC_offset :natural := congr_cl13_wB_offset + 6; +constant congr_cl13_wD_offset :natural := congr_cl13_wC_offset + 6; +constant congr_cl13_wE_offset :natural := congr_cl13_wD_offset + 6; +constant congr_cl13_wF_offset :natural := congr_cl13_wE_offset + 6; +constant congr_cl13_wG_offset :natural := congr_cl13_wF_offset + 6; +constant congr_cl13_wH_offset :natural := congr_cl13_wG_offset + 6; +constant congr_cl14_wA_offset :natural := congr_cl13_wH_offset + 6; +constant congr_cl14_wB_offset :natural := congr_cl14_wA_offset + 6; +constant congr_cl14_wC_offset :natural := congr_cl14_wB_offset + 6; +constant congr_cl14_wD_offset :natural := congr_cl14_wC_offset + 6; +constant congr_cl14_wE_offset :natural := congr_cl14_wD_offset + 6; +constant congr_cl14_wF_offset :natural := congr_cl14_wE_offset + 6; +constant congr_cl14_wG_offset :natural := congr_cl14_wF_offset + 6; +constant congr_cl14_wH_offset :natural := congr_cl14_wG_offset + 6; +constant congr_cl15_wA_offset :natural := congr_cl14_wH_offset + 6; +constant congr_cl15_wB_offset :natural := congr_cl15_wA_offset + 6; +constant congr_cl15_wC_offset :natural := congr_cl15_wB_offset + 6; +constant congr_cl15_wD_offset :natural := congr_cl15_wC_offset + 6; +constant congr_cl15_wE_offset :natural := congr_cl15_wD_offset + 6; +constant congr_cl15_wF_offset :natural := congr_cl15_wE_offset + 6; +constant congr_cl15_wG_offset :natural := congr_cl15_wF_offset + 6; +constant congr_cl15_wH_offset :natural := congr_cl15_wG_offset + 6; +constant congr_cl16_wA_offset :natural := congr_cl15_wH_offset + 6; +constant congr_cl16_wB_offset :natural := congr_cl16_wA_offset + 6; +constant congr_cl16_wC_offset :natural := congr_cl16_wB_offset + 6; +constant congr_cl16_wD_offset :natural := congr_cl16_wC_offset + 6; +constant congr_cl16_wE_offset :natural := congr_cl16_wD_offset + 6; +constant congr_cl16_wF_offset :natural := congr_cl16_wE_offset + 6; +constant congr_cl16_wG_offset :natural := congr_cl16_wF_offset + 6; +constant congr_cl16_wH_offset :natural := congr_cl16_wG_offset + 6; +constant congr_cl17_wA_offset :natural := congr_cl16_wH_offset + 6; +constant congr_cl17_wB_offset :natural := congr_cl17_wA_offset + 6; +constant congr_cl17_wC_offset :natural := congr_cl17_wB_offset + 6; +constant congr_cl17_wD_offset :natural := congr_cl17_wC_offset + 6; +constant congr_cl17_wE_offset :natural := congr_cl17_wD_offset + 6; +constant congr_cl17_wF_offset :natural := congr_cl17_wE_offset + 6; +constant congr_cl17_wG_offset :natural := congr_cl17_wF_offset + 6; +constant congr_cl17_wH_offset :natural := congr_cl17_wG_offset + 6; +constant congr_cl18_wA_offset :natural := congr_cl17_wH_offset + 6; +constant congr_cl18_wB_offset :natural := congr_cl18_wA_offset + 6; +constant congr_cl18_wC_offset :natural := congr_cl18_wB_offset + 6; +constant congr_cl18_wD_offset :natural := congr_cl18_wC_offset + 6; +constant congr_cl18_wE_offset :natural := congr_cl18_wD_offset + 6; +constant congr_cl18_wF_offset :natural := congr_cl18_wE_offset + 6; +constant congr_cl18_wG_offset :natural := congr_cl18_wF_offset + 6; +constant congr_cl18_wH_offset :natural := congr_cl18_wG_offset + 6; +constant congr_cl19_wA_offset :natural := congr_cl18_wH_offset + 6; +constant congr_cl19_wB_offset :natural := congr_cl19_wA_offset + 6; +constant congr_cl19_wC_offset :natural := congr_cl19_wB_offset + 6; +constant congr_cl19_wD_offset :natural := congr_cl19_wC_offset + 6; +constant congr_cl19_wE_offset :natural := congr_cl19_wD_offset + 6; +constant congr_cl19_wF_offset :natural := congr_cl19_wE_offset + 6; +constant congr_cl19_wG_offset :natural := congr_cl19_wF_offset + 6; +constant congr_cl19_wH_offset :natural := congr_cl19_wG_offset + 6; +constant congr_cl20_wA_offset :natural := congr_cl19_wH_offset + 6; +constant congr_cl20_wB_offset :natural := congr_cl20_wA_offset + 6; +constant congr_cl20_wC_offset :natural := congr_cl20_wB_offset + 6; +constant congr_cl20_wD_offset :natural := congr_cl20_wC_offset + 6; +constant congr_cl20_wE_offset :natural := congr_cl20_wD_offset + 6; +constant congr_cl20_wF_offset :natural := congr_cl20_wE_offset + 6; +constant congr_cl20_wG_offset :natural := congr_cl20_wF_offset + 6; +constant congr_cl20_wH_offset :natural := congr_cl20_wG_offset + 6; +constant congr_cl21_wA_offset :natural := congr_cl20_wH_offset + 6; +constant congr_cl21_wB_offset :natural := congr_cl21_wA_offset + 6; +constant congr_cl21_wC_offset :natural := congr_cl21_wB_offset + 6; +constant congr_cl21_wD_offset :natural := congr_cl21_wC_offset + 6; +constant congr_cl21_wE_offset :natural := congr_cl21_wD_offset + 6; +constant congr_cl21_wF_offset :natural := congr_cl21_wE_offset + 6; +constant congr_cl21_wG_offset :natural := congr_cl21_wF_offset + 6; +constant congr_cl21_wH_offset :natural := congr_cl21_wG_offset + 6; +constant congr_cl22_wA_offset :natural := congr_cl21_wH_offset + 6; +constant congr_cl22_wB_offset :natural := congr_cl22_wA_offset + 6; +constant congr_cl22_wC_offset :natural := congr_cl22_wB_offset + 6; +constant congr_cl22_wD_offset :natural := congr_cl22_wC_offset + 6; +constant congr_cl22_wE_offset :natural := congr_cl22_wD_offset + 6; +constant congr_cl22_wF_offset :natural := congr_cl22_wE_offset + 6; +constant congr_cl22_wG_offset :natural := congr_cl22_wF_offset + 6; +constant congr_cl22_wH_offset :natural := congr_cl22_wG_offset + 6; +constant congr_cl23_wA_offset :natural := congr_cl22_wH_offset + 6; +constant congr_cl23_wB_offset :natural := congr_cl23_wA_offset + 6; +constant congr_cl23_wC_offset :natural := congr_cl23_wB_offset + 6; +constant congr_cl23_wD_offset :natural := congr_cl23_wC_offset + 6; +constant congr_cl23_wE_offset :natural := congr_cl23_wD_offset + 6; +constant congr_cl23_wF_offset :natural := congr_cl23_wE_offset + 6; +constant congr_cl23_wG_offset :natural := congr_cl23_wF_offset + 6; +constant congr_cl23_wH_offset :natural := congr_cl23_wG_offset + 6; +constant congr_cl24_wA_offset :natural := congr_cl23_wH_offset + 6; +constant congr_cl24_wB_offset :natural := congr_cl24_wA_offset + 6; +constant congr_cl24_wC_offset :natural := congr_cl24_wB_offset + 6; +constant congr_cl24_wD_offset :natural := congr_cl24_wC_offset + 6; +constant congr_cl24_wE_offset :natural := congr_cl24_wD_offset + 6; +constant congr_cl24_wF_offset :natural := congr_cl24_wE_offset + 6; +constant congr_cl24_wG_offset :natural := congr_cl24_wF_offset + 6; +constant congr_cl24_wH_offset :natural := congr_cl24_wG_offset + 6; +constant congr_cl25_wA_offset :natural := congr_cl24_wH_offset + 6; +constant congr_cl25_wB_offset :natural := congr_cl25_wA_offset + 6; +constant congr_cl25_wC_offset :natural := congr_cl25_wB_offset + 6; +constant congr_cl25_wD_offset :natural := congr_cl25_wC_offset + 6; +constant congr_cl25_wE_offset :natural := congr_cl25_wD_offset + 6; +constant congr_cl25_wF_offset :natural := congr_cl25_wE_offset + 6; +constant congr_cl25_wG_offset :natural := congr_cl25_wF_offset + 6; +constant congr_cl25_wH_offset :natural := congr_cl25_wG_offset + 6; +constant congr_cl26_wA_offset :natural := congr_cl25_wH_offset + 6; +constant congr_cl26_wB_offset :natural := congr_cl26_wA_offset + 6; +constant congr_cl26_wC_offset :natural := congr_cl26_wB_offset + 6; +constant congr_cl26_wD_offset :natural := congr_cl26_wC_offset + 6; +constant congr_cl26_wE_offset :natural := congr_cl26_wD_offset + 6; +constant congr_cl26_wF_offset :natural := congr_cl26_wE_offset + 6; +constant congr_cl26_wG_offset :natural := congr_cl26_wF_offset + 6; +constant congr_cl26_wH_offset :natural := congr_cl26_wG_offset + 6; +constant congr_cl27_wA_offset :natural := congr_cl26_wH_offset + 6; +constant congr_cl27_wB_offset :natural := congr_cl27_wA_offset + 6; +constant congr_cl27_wC_offset :natural := congr_cl27_wB_offset + 6; +constant congr_cl27_wD_offset :natural := congr_cl27_wC_offset + 6; +constant congr_cl27_wE_offset :natural := congr_cl27_wD_offset + 6; +constant congr_cl27_wF_offset :natural := congr_cl27_wE_offset + 6; +constant congr_cl27_wG_offset :natural := congr_cl27_wF_offset + 6; +constant congr_cl27_wH_offset :natural := congr_cl27_wG_offset + 6; +constant congr_cl28_wA_offset :natural := congr_cl27_wH_offset + 6; +constant congr_cl28_wB_offset :natural := congr_cl28_wA_offset + 6; +constant congr_cl28_wC_offset :natural := congr_cl28_wB_offset + 6; +constant congr_cl28_wD_offset :natural := congr_cl28_wC_offset + 6; +constant congr_cl28_wE_offset :natural := congr_cl28_wD_offset + 6; +constant congr_cl28_wF_offset :natural := congr_cl28_wE_offset + 6; +constant congr_cl28_wG_offset :natural := congr_cl28_wF_offset + 6; +constant congr_cl28_wH_offset :natural := congr_cl28_wG_offset + 6; +constant congr_cl29_wA_offset :natural := congr_cl28_wH_offset + 6; +constant congr_cl29_wB_offset :natural := congr_cl29_wA_offset + 6; +constant congr_cl29_wC_offset :natural := congr_cl29_wB_offset + 6; +constant congr_cl29_wD_offset :natural := congr_cl29_wC_offset + 6; +constant congr_cl29_wE_offset :natural := congr_cl29_wD_offset + 6; +constant congr_cl29_wF_offset :natural := congr_cl29_wE_offset + 6; +constant congr_cl29_wG_offset :natural := congr_cl29_wF_offset + 6; +constant congr_cl29_wH_offset :natural := congr_cl29_wG_offset + 6; +constant congr_cl30_wA_offset :natural := congr_cl29_wH_offset + 6; +constant congr_cl30_wB_offset :natural := congr_cl30_wA_offset + 6; +constant congr_cl30_wC_offset :natural := congr_cl30_wB_offset + 6; +constant congr_cl30_wD_offset :natural := congr_cl30_wC_offset + 6; +constant congr_cl30_wE_offset :natural := congr_cl30_wD_offset + 6; +constant congr_cl30_wF_offset :natural := congr_cl30_wE_offset + 6; +constant congr_cl30_wG_offset :natural := congr_cl30_wF_offset + 6; +constant congr_cl30_wH_offset :natural := congr_cl30_wG_offset + 6; +constant congr_cl31_wA_offset :natural := congr_cl30_wH_offset + 6; +constant congr_cl31_wB_offset :natural := congr_cl31_wA_offset + 6; +constant congr_cl31_wC_offset :natural := congr_cl31_wB_offset + 6; +constant congr_cl31_wD_offset :natural := congr_cl31_wC_offset + 6; +constant congr_cl31_wE_offset :natural := congr_cl31_wD_offset + 6; +constant congr_cl31_wF_offset :natural := congr_cl31_wE_offset + 6; +constant congr_cl31_wG_offset :natural := congr_cl31_wF_offset + 6; +constant congr_cl31_wH_offset :natural := congr_cl31_wG_offset + 6; +constant congr_cl32_wA_offset :natural := congr_cl31_wH_offset + 6; +constant congr_cl32_wB_offset :natural := congr_cl32_wA_offset + 6; +constant congr_cl32_wC_offset :natural := congr_cl32_wB_offset + 6; +constant congr_cl32_wD_offset :natural := congr_cl32_wC_offset + 6; +constant congr_cl32_wE_offset :natural := congr_cl32_wD_offset + 6; +constant congr_cl32_wF_offset :natural := congr_cl32_wE_offset + 6; +constant congr_cl32_wG_offset :natural := congr_cl32_wF_offset + 6; +constant congr_cl32_wH_offset :natural := congr_cl32_wG_offset + 6; +constant congr_cl33_wA_offset :natural := congr_cl32_wH_offset + 6; +constant congr_cl33_wB_offset :natural := congr_cl33_wA_offset + 6; +constant congr_cl33_wC_offset :natural := congr_cl33_wB_offset + 6; +constant congr_cl33_wD_offset :natural := congr_cl33_wC_offset + 6; +constant congr_cl33_wE_offset :natural := congr_cl33_wD_offset + 6; +constant congr_cl33_wF_offset :natural := congr_cl33_wE_offset + 6; +constant congr_cl33_wG_offset :natural := congr_cl33_wF_offset + 6; +constant congr_cl33_wH_offset :natural := congr_cl33_wG_offset + 6; +constant congr_cl34_wA_offset :natural := congr_cl33_wH_offset + 6; +constant congr_cl34_wB_offset :natural := congr_cl34_wA_offset + 6; +constant congr_cl34_wC_offset :natural := congr_cl34_wB_offset + 6; +constant congr_cl34_wD_offset :natural := congr_cl34_wC_offset + 6; +constant congr_cl34_wE_offset :natural := congr_cl34_wD_offset + 6; +constant congr_cl34_wF_offset :natural := congr_cl34_wE_offset + 6; +constant congr_cl34_wG_offset :natural := congr_cl34_wF_offset + 6; +constant congr_cl34_wH_offset :natural := congr_cl34_wG_offset + 6; +constant congr_cl35_wA_offset :natural := congr_cl34_wH_offset + 6; +constant congr_cl35_wB_offset :natural := congr_cl35_wA_offset + 6; +constant congr_cl35_wC_offset :natural := congr_cl35_wB_offset + 6; +constant congr_cl35_wD_offset :natural := congr_cl35_wC_offset + 6; +constant congr_cl35_wE_offset :natural := congr_cl35_wD_offset + 6; +constant congr_cl35_wF_offset :natural := congr_cl35_wE_offset + 6; +constant congr_cl35_wG_offset :natural := congr_cl35_wF_offset + 6; +constant congr_cl35_wH_offset :natural := congr_cl35_wG_offset + 6; +constant congr_cl36_wA_offset :natural := congr_cl35_wH_offset + 6; +constant congr_cl36_wB_offset :natural := congr_cl36_wA_offset + 6; +constant congr_cl36_wC_offset :natural := congr_cl36_wB_offset + 6; +constant congr_cl36_wD_offset :natural := congr_cl36_wC_offset + 6; +constant congr_cl36_wE_offset :natural := congr_cl36_wD_offset + 6; +constant congr_cl36_wF_offset :natural := congr_cl36_wE_offset + 6; +constant congr_cl36_wG_offset :natural := congr_cl36_wF_offset + 6; +constant congr_cl36_wH_offset :natural := congr_cl36_wG_offset + 6; +constant congr_cl37_wA_offset :natural := congr_cl36_wH_offset + 6; +constant congr_cl37_wB_offset :natural := congr_cl37_wA_offset + 6; +constant congr_cl37_wC_offset :natural := congr_cl37_wB_offset + 6; +constant congr_cl37_wD_offset :natural := congr_cl37_wC_offset + 6; +constant congr_cl37_wE_offset :natural := congr_cl37_wD_offset + 6; +constant congr_cl37_wF_offset :natural := congr_cl37_wE_offset + 6; +constant congr_cl37_wG_offset :natural := congr_cl37_wF_offset + 6; +constant congr_cl37_wH_offset :natural := congr_cl37_wG_offset + 6; +constant congr_cl38_wA_offset :natural := congr_cl37_wH_offset + 6; +constant congr_cl38_wB_offset :natural := congr_cl38_wA_offset + 6; +constant congr_cl38_wC_offset :natural := congr_cl38_wB_offset + 6; +constant congr_cl38_wD_offset :natural := congr_cl38_wC_offset + 6; +constant congr_cl38_wE_offset :natural := congr_cl38_wD_offset + 6; +constant congr_cl38_wF_offset :natural := congr_cl38_wE_offset + 6; +constant congr_cl38_wG_offset :natural := congr_cl38_wF_offset + 6; +constant congr_cl38_wH_offset :natural := congr_cl38_wG_offset + 6; +constant congr_cl39_wA_offset :natural := congr_cl38_wH_offset + 6; +constant congr_cl39_wB_offset :natural := congr_cl39_wA_offset + 6; +constant congr_cl39_wC_offset :natural := congr_cl39_wB_offset + 6; +constant congr_cl39_wD_offset :natural := congr_cl39_wC_offset + 6; +constant congr_cl39_wE_offset :natural := congr_cl39_wD_offset + 6; +constant congr_cl39_wF_offset :natural := congr_cl39_wE_offset + 6; +constant congr_cl39_wG_offset :natural := congr_cl39_wF_offset + 6; +constant congr_cl39_wH_offset :natural := congr_cl39_wG_offset + 6; +constant congr_cl40_wA_offset :natural := congr_cl39_wH_offset + 6; +constant congr_cl40_wB_offset :natural := congr_cl40_wA_offset + 6; +constant congr_cl40_wC_offset :natural := congr_cl40_wB_offset + 6; +constant congr_cl40_wD_offset :natural := congr_cl40_wC_offset + 6; +constant congr_cl40_wE_offset :natural := congr_cl40_wD_offset + 6; +constant congr_cl40_wF_offset :natural := congr_cl40_wE_offset + 6; +constant congr_cl40_wG_offset :natural := congr_cl40_wF_offset + 6; +constant congr_cl40_wH_offset :natural := congr_cl40_wG_offset + 6; +constant congr_cl41_wA_offset :natural := congr_cl40_wH_offset + 6; +constant congr_cl41_wB_offset :natural := congr_cl41_wA_offset + 6; +constant congr_cl41_wC_offset :natural := congr_cl41_wB_offset + 6; +constant congr_cl41_wD_offset :natural := congr_cl41_wC_offset + 6; +constant congr_cl41_wE_offset :natural := congr_cl41_wD_offset + 6; +constant congr_cl41_wF_offset :natural := congr_cl41_wE_offset + 6; +constant congr_cl41_wG_offset :natural := congr_cl41_wF_offset + 6; +constant congr_cl41_wH_offset :natural := congr_cl41_wG_offset + 6; +constant congr_cl42_wA_offset :natural := congr_cl41_wH_offset + 6; +constant congr_cl42_wB_offset :natural := congr_cl42_wA_offset + 6; +constant congr_cl42_wC_offset :natural := congr_cl42_wB_offset + 6; +constant congr_cl42_wD_offset :natural := congr_cl42_wC_offset + 6; +constant congr_cl42_wE_offset :natural := congr_cl42_wD_offset + 6; +constant congr_cl42_wF_offset :natural := congr_cl42_wE_offset + 6; +constant congr_cl42_wG_offset :natural := congr_cl42_wF_offset + 6; +constant congr_cl42_wH_offset :natural := congr_cl42_wG_offset + 6; +constant congr_cl43_wA_offset :natural := congr_cl42_wH_offset + 6; +constant congr_cl43_wB_offset :natural := congr_cl43_wA_offset + 6; +constant congr_cl43_wC_offset :natural := congr_cl43_wB_offset + 6; +constant congr_cl43_wD_offset :natural := congr_cl43_wC_offset + 6; +constant congr_cl43_wE_offset :natural := congr_cl43_wD_offset + 6; +constant congr_cl43_wF_offset :natural := congr_cl43_wE_offset + 6; +constant congr_cl43_wG_offset :natural := congr_cl43_wF_offset + 6; +constant congr_cl43_wH_offset :natural := congr_cl43_wG_offset + 6; +constant congr_cl44_wA_offset :natural := congr_cl43_wH_offset + 6; +constant congr_cl44_wB_offset :natural := congr_cl44_wA_offset + 6; +constant congr_cl44_wC_offset :natural := congr_cl44_wB_offset + 6; +constant congr_cl44_wD_offset :natural := congr_cl44_wC_offset + 6; +constant congr_cl44_wE_offset :natural := congr_cl44_wD_offset + 6; +constant congr_cl44_wF_offset :natural := congr_cl44_wE_offset + 6; +constant congr_cl44_wG_offset :natural := congr_cl44_wF_offset + 6; +constant congr_cl44_wH_offset :natural := congr_cl44_wG_offset + 6; +constant congr_cl45_wA_offset :natural := congr_cl44_wH_offset + 6; +constant congr_cl45_wB_offset :natural := congr_cl45_wA_offset + 6; +constant congr_cl45_wC_offset :natural := congr_cl45_wB_offset + 6; +constant congr_cl45_wD_offset :natural := congr_cl45_wC_offset + 6; +constant congr_cl45_wE_offset :natural := congr_cl45_wD_offset + 6; +constant congr_cl45_wF_offset :natural := congr_cl45_wE_offset + 6; +constant congr_cl45_wG_offset :natural := congr_cl45_wF_offset + 6; +constant congr_cl45_wH_offset :natural := congr_cl45_wG_offset + 6; +constant congr_cl46_wA_offset :natural := congr_cl45_wH_offset + 6; +constant congr_cl46_wB_offset :natural := congr_cl46_wA_offset + 6; +constant congr_cl46_wC_offset :natural := congr_cl46_wB_offset + 6; +constant congr_cl46_wD_offset :natural := congr_cl46_wC_offset + 6; +constant congr_cl46_wE_offset :natural := congr_cl46_wD_offset + 6; +constant congr_cl46_wF_offset :natural := congr_cl46_wE_offset + 6; +constant congr_cl46_wG_offset :natural := congr_cl46_wF_offset + 6; +constant congr_cl46_wH_offset :natural := congr_cl46_wG_offset + 6; +constant congr_cl47_wA_offset :natural := congr_cl46_wH_offset + 6; +constant congr_cl47_wB_offset :natural := congr_cl47_wA_offset + 6; +constant congr_cl47_wC_offset :natural := congr_cl47_wB_offset + 6; +constant congr_cl47_wD_offset :natural := congr_cl47_wC_offset + 6; +constant congr_cl47_wE_offset :natural := congr_cl47_wD_offset + 6; +constant congr_cl47_wF_offset :natural := congr_cl47_wE_offset + 6; +constant congr_cl47_wG_offset :natural := congr_cl47_wF_offset + 6; +constant congr_cl47_wH_offset :natural := congr_cl47_wG_offset + 6; +constant congr_cl48_wA_offset :natural := congr_cl47_wH_offset + 6; +constant congr_cl48_wB_offset :natural := congr_cl48_wA_offset + 6; +constant congr_cl48_wC_offset :natural := congr_cl48_wB_offset + 6; +constant congr_cl48_wD_offset :natural := congr_cl48_wC_offset + 6; +constant congr_cl48_wE_offset :natural := congr_cl48_wD_offset + 6; +constant congr_cl48_wF_offset :natural := congr_cl48_wE_offset + 6; +constant congr_cl48_wG_offset :natural := congr_cl48_wF_offset + 6; +constant congr_cl48_wH_offset :natural := congr_cl48_wG_offset + 6; +constant congr_cl49_wA_offset :natural := congr_cl48_wH_offset + 6; +constant congr_cl49_wB_offset :natural := congr_cl49_wA_offset + 6; +constant congr_cl49_wC_offset :natural := congr_cl49_wB_offset + 6; +constant congr_cl49_wD_offset :natural := congr_cl49_wC_offset + 6; +constant congr_cl49_wE_offset :natural := congr_cl49_wD_offset + 6; +constant congr_cl49_wF_offset :natural := congr_cl49_wE_offset + 6; +constant congr_cl49_wG_offset :natural := congr_cl49_wF_offset + 6; +constant congr_cl49_wH_offset :natural := congr_cl49_wG_offset + 6; +constant congr_cl50_wA_offset :natural := congr_cl49_wH_offset + 6; +constant congr_cl50_wB_offset :natural := congr_cl50_wA_offset + 6; +constant congr_cl50_wC_offset :natural := congr_cl50_wB_offset + 6; +constant congr_cl50_wD_offset :natural := congr_cl50_wC_offset + 6; +constant congr_cl50_wE_offset :natural := congr_cl50_wD_offset + 6; +constant congr_cl50_wF_offset :natural := congr_cl50_wE_offset + 6; +constant congr_cl50_wG_offset :natural := congr_cl50_wF_offset + 6; +constant congr_cl50_wH_offset :natural := congr_cl50_wG_offset + 6; +constant congr_cl51_wA_offset :natural := congr_cl50_wH_offset + 6; +constant congr_cl51_wB_offset :natural := congr_cl51_wA_offset + 6; +constant congr_cl51_wC_offset :natural := congr_cl51_wB_offset + 6; +constant congr_cl51_wD_offset :natural := congr_cl51_wC_offset + 6; +constant congr_cl51_wE_offset :natural := congr_cl51_wD_offset + 6; +constant congr_cl51_wF_offset :natural := congr_cl51_wE_offset + 6; +constant congr_cl51_wG_offset :natural := congr_cl51_wF_offset + 6; +constant congr_cl51_wH_offset :natural := congr_cl51_wG_offset + 6; +constant congr_cl52_wA_offset :natural := congr_cl51_wH_offset + 6; +constant congr_cl52_wB_offset :natural := congr_cl52_wA_offset + 6; +constant congr_cl52_wC_offset :natural := congr_cl52_wB_offset + 6; +constant congr_cl52_wD_offset :natural := congr_cl52_wC_offset + 6; +constant congr_cl52_wE_offset :natural := congr_cl52_wD_offset + 6; +constant congr_cl52_wF_offset :natural := congr_cl52_wE_offset + 6; +constant congr_cl52_wG_offset :natural := congr_cl52_wF_offset + 6; +constant congr_cl52_wH_offset :natural := congr_cl52_wG_offset + 6; +constant congr_cl53_wA_offset :natural := congr_cl52_wH_offset + 6; +constant congr_cl53_wB_offset :natural := congr_cl53_wA_offset + 6; +constant congr_cl53_wC_offset :natural := congr_cl53_wB_offset + 6; +constant congr_cl53_wD_offset :natural := congr_cl53_wC_offset + 6; +constant congr_cl53_wE_offset :natural := congr_cl53_wD_offset + 6; +constant congr_cl53_wF_offset :natural := congr_cl53_wE_offset + 6; +constant congr_cl53_wG_offset :natural := congr_cl53_wF_offset + 6; +constant congr_cl53_wH_offset :natural := congr_cl53_wG_offset + 6; +constant congr_cl54_wA_offset :natural := congr_cl53_wH_offset + 6; +constant congr_cl54_wB_offset :natural := congr_cl54_wA_offset + 6; +constant congr_cl54_wC_offset :natural := congr_cl54_wB_offset + 6; +constant congr_cl54_wD_offset :natural := congr_cl54_wC_offset + 6; +constant congr_cl54_wE_offset :natural := congr_cl54_wD_offset + 6; +constant congr_cl54_wF_offset :natural := congr_cl54_wE_offset + 6; +constant congr_cl54_wG_offset :natural := congr_cl54_wF_offset + 6; +constant congr_cl54_wH_offset :natural := congr_cl54_wG_offset + 6; +constant congr_cl55_wA_offset :natural := congr_cl54_wH_offset + 6; +constant congr_cl55_wB_offset :natural := congr_cl55_wA_offset + 6; +constant congr_cl55_wC_offset :natural := congr_cl55_wB_offset + 6; +constant congr_cl55_wD_offset :natural := congr_cl55_wC_offset + 6; +constant congr_cl55_wE_offset :natural := congr_cl55_wD_offset + 6; +constant congr_cl55_wF_offset :natural := congr_cl55_wE_offset + 6; +constant congr_cl55_wG_offset :natural := congr_cl55_wF_offset + 6; +constant congr_cl55_wH_offset :natural := congr_cl55_wG_offset + 6; +constant congr_cl56_wA_offset :natural := congr_cl55_wH_offset + 6; +constant congr_cl56_wB_offset :natural := congr_cl56_wA_offset + 6; +constant congr_cl56_wC_offset :natural := congr_cl56_wB_offset + 6; +constant congr_cl56_wD_offset :natural := congr_cl56_wC_offset + 6; +constant congr_cl56_wE_offset :natural := congr_cl56_wD_offset + 6; +constant congr_cl56_wF_offset :natural := congr_cl56_wE_offset + 6; +constant congr_cl56_wG_offset :natural := congr_cl56_wF_offset + 6; +constant congr_cl56_wH_offset :natural := congr_cl56_wG_offset + 6; +constant congr_cl57_wA_offset :natural := congr_cl56_wH_offset + 6; +constant congr_cl57_wB_offset :natural := congr_cl57_wA_offset + 6; +constant congr_cl57_wC_offset :natural := congr_cl57_wB_offset + 6; +constant congr_cl57_wD_offset :natural := congr_cl57_wC_offset + 6; +constant congr_cl57_wE_offset :natural := congr_cl57_wD_offset + 6; +constant congr_cl57_wF_offset :natural := congr_cl57_wE_offset + 6; +constant congr_cl57_wG_offset :natural := congr_cl57_wF_offset + 6; +constant congr_cl57_wH_offset :natural := congr_cl57_wG_offset + 6; +constant congr_cl58_wA_offset :natural := congr_cl57_wH_offset + 6; +constant congr_cl58_wB_offset :natural := congr_cl58_wA_offset + 6; +constant congr_cl58_wC_offset :natural := congr_cl58_wB_offset + 6; +constant congr_cl58_wD_offset :natural := congr_cl58_wC_offset + 6; +constant congr_cl58_wE_offset :natural := congr_cl58_wD_offset + 6; +constant congr_cl58_wF_offset :natural := congr_cl58_wE_offset + 6; +constant congr_cl58_wG_offset :natural := congr_cl58_wF_offset + 6; +constant congr_cl58_wH_offset :natural := congr_cl58_wG_offset + 6; +constant congr_cl59_wA_offset :natural := congr_cl58_wH_offset + 6; +constant congr_cl59_wB_offset :natural := congr_cl59_wA_offset + 6; +constant congr_cl59_wC_offset :natural := congr_cl59_wB_offset + 6; +constant congr_cl59_wD_offset :natural := congr_cl59_wC_offset + 6; +constant congr_cl59_wE_offset :natural := congr_cl59_wD_offset + 6; +constant congr_cl59_wF_offset :natural := congr_cl59_wE_offset + 6; +constant congr_cl59_wG_offset :natural := congr_cl59_wF_offset + 6; +constant congr_cl59_wH_offset :natural := congr_cl59_wG_offset + 6; +constant congr_cl60_wA_offset :natural := congr_cl59_wH_offset + 6; +constant congr_cl60_wB_offset :natural := congr_cl60_wA_offset + 6; +constant congr_cl60_wC_offset :natural := congr_cl60_wB_offset + 6; +constant congr_cl60_wD_offset :natural := congr_cl60_wC_offset + 6; +constant congr_cl60_wE_offset :natural := congr_cl60_wD_offset + 6; +constant congr_cl60_wF_offset :natural := congr_cl60_wE_offset + 6; +constant congr_cl60_wG_offset :natural := congr_cl60_wF_offset + 6; +constant congr_cl60_wH_offset :natural := congr_cl60_wG_offset + 6; +constant congr_cl61_wA_offset :natural := congr_cl60_wH_offset + 6; +constant congr_cl61_wB_offset :natural := congr_cl61_wA_offset + 6; +constant congr_cl61_wC_offset :natural := congr_cl61_wB_offset + 6; +constant congr_cl61_wD_offset :natural := congr_cl61_wC_offset + 6; +constant congr_cl61_wE_offset :natural := congr_cl61_wD_offset + 6; +constant congr_cl61_wF_offset :natural := congr_cl61_wE_offset + 6; +constant congr_cl61_wG_offset :natural := congr_cl61_wF_offset + 6; +constant congr_cl61_wH_offset :natural := congr_cl61_wG_offset + 6; +constant congr_cl62_wA_offset :natural := congr_cl61_wH_offset + 6; +constant congr_cl62_wB_offset :natural := congr_cl62_wA_offset + 6; +constant congr_cl62_wC_offset :natural := congr_cl62_wB_offset + 6; +constant congr_cl62_wD_offset :natural := congr_cl62_wC_offset + 6; +constant congr_cl62_wE_offset :natural := congr_cl62_wD_offset + 6; +constant congr_cl62_wF_offset :natural := congr_cl62_wE_offset + 6; +constant congr_cl62_wG_offset :natural := congr_cl62_wF_offset + 6; +constant congr_cl62_wH_offset :natural := congr_cl62_wG_offset + 6; +constant congr_cl63_wA_offset :natural := congr_cl62_wH_offset + 6; +constant congr_cl63_wB_offset :natural := congr_cl63_wA_offset + 6; +constant congr_cl63_wC_offset :natural := congr_cl63_wB_offset + 6; +constant congr_cl63_wD_offset :natural := congr_cl63_wC_offset + 6; +constant congr_cl63_wE_offset :natural := congr_cl63_wD_offset + 6; +constant congr_cl63_wF_offset :natural := congr_cl63_wE_offset + 6; +constant congr_cl63_wG_offset :natural := congr_cl63_wF_offset + 6; +constant congr_cl63_wH_offset :natural := congr_cl63_wG_offset + 6; +constant flush_wayA_data_offset :natural := congr_cl63_wH_offset + 6; +constant flush_wayB_data_offset :natural := flush_wayA_data_offset + 6; +constant flush_wayC_data_offset :natural := flush_wayB_data_offset + 6; +constant flush_wayD_data_offset :natural := flush_wayC_data_offset + 6; +constant flush_wayE_data_offset :natural := flush_wayD_data_offset + 6; +constant flush_wayF_data_offset :natural := flush_wayE_data_offset + 6; +constant flush_wayG_data_offset :natural := flush_wayF_data_offset + 6; +constant flush_wayH_data_offset :natural := flush_wayG_data_offset + 6; +constant ex3_flush_cline_offset :natural := flush_wayH_data_offset + 6; +constant ex5_congr_cl_offset :natural := ex3_flush_cline_offset + 1; +constant ex7_congr_cl_offset :natural := ex5_congr_cl_offset + 6; +constant ex8_congr_cl_offset :natural := ex7_congr_cl_offset + 6; +constant ex9_congr_cl_offset :natural := ex8_congr_cl_offset + 6; +constant wayA_val_b_offset :natural := ex9_congr_cl_offset + 6; +constant wayB_val_b_offset :natural := wayA_val_b_offset + 6; +constant wayC_val_b_offset :natural := wayB_val_b_offset + 6; +constant wayD_val_b_offset :natural := wayC_val_b_offset + 6; +constant wayE_val_b_offset :natural := wayD_val_b_offset + 6; +constant wayF_val_b_offset :natural := wayE_val_b_offset + 6; +constant wayG_val_b_offset :natural := wayF_val_b_offset + 6; +constant wayH_val_b_offset :natural := wayG_val_b_offset + 6; +constant ex3_wayA_fxubyp_val_offset :natural := wayH_val_b_offset + 6; +constant ex3_wayB_fxubyp_val_offset :natural := ex3_wayA_fxubyp_val_offset + 1; +constant ex3_wayC_fxubyp_val_offset :natural := ex3_wayB_fxubyp_val_offset + 1; +constant ex3_wayD_fxubyp_val_offset :natural := ex3_wayC_fxubyp_val_offset + 1; +constant ex3_wayE_fxubyp_val_offset :natural := ex3_wayD_fxubyp_val_offset + 1; +constant ex3_wayF_fxubyp_val_offset :natural := ex3_wayE_fxubyp_val_offset + 1; +constant ex3_wayG_fxubyp_val_offset :natural := ex3_wayF_fxubyp_val_offset + 1; +constant ex3_wayH_fxubyp_val_offset :natural := ex3_wayG_fxubyp_val_offset + 1; +constant ex3_wayA_relbyp_val_offset :natural := ex3_wayH_fxubyp_val_offset + 1; +constant ex3_wayB_relbyp_val_offset :natural := ex3_wayA_relbyp_val_offset + 1; +constant ex3_wayC_relbyp_val_offset :natural := ex3_wayB_relbyp_val_offset + 1; +constant ex3_wayD_relbyp_val_offset :natural := ex3_wayC_relbyp_val_offset + 1; +constant ex3_wayE_relbyp_val_offset :natural := ex3_wayD_relbyp_val_offset + 1; +constant ex3_wayF_relbyp_val_offset :natural := ex3_wayE_relbyp_val_offset + 1; +constant ex3_wayG_relbyp_val_offset :natural := ex3_wayF_relbyp_val_offset + 1; +constant ex3_wayH_relbyp_val_offset :natural := ex3_wayG_relbyp_val_offset + 1; +constant ex4_xuop_wayA_upd_offset :natural := ex3_wayH_relbyp_val_offset + 1; +constant ex4_xuop_wayB_upd_offset :natural := ex4_xuop_wayA_upd_offset + 1; +constant ex4_xuop_wayC_upd_offset :natural := ex4_xuop_wayB_upd_offset + 1; +constant ex4_xuop_wayD_upd_offset :natural := ex4_xuop_wayC_upd_offset + 1; +constant ex4_xuop_wayE_upd_offset :natural := ex4_xuop_wayD_upd_offset + 1; +constant ex4_xuop_wayF_upd_offset :natural := ex4_xuop_wayE_upd_offset + 1; +constant ex4_xuop_wayG_upd_offset :natural := ex4_xuop_wayF_upd_offset + 1; +constant ex4_xuop_wayH_upd_offset :natural := ex4_xuop_wayG_upd_offset + 1; +constant ex5_xuop_wayA_upd_offset :natural := ex4_xuop_wayH_upd_offset + 1; +constant ex5_xuop_wayB_upd_offset :natural := ex5_xuop_wayA_upd_offset + 1; +constant ex5_xuop_wayC_upd_offset :natural := ex5_xuop_wayB_upd_offset + 1; +constant ex5_xuop_wayD_upd_offset :natural := ex5_xuop_wayC_upd_offset + 1; +constant ex5_xuop_wayE_upd_offset :natural := ex5_xuop_wayD_upd_offset + 1; +constant ex5_xuop_wayF_upd_offset :natural := ex5_xuop_wayE_upd_offset + 1; +constant ex5_xuop_wayG_upd_offset :natural := ex5_xuop_wayF_upd_offset + 1; +constant ex5_xuop_wayH_upd_offset :natural := ex5_xuop_wayG_upd_offset + 1; +constant inval_clr_lck_wA_offset :natural := ex5_xuop_wayH_upd_offset + 1; +constant inval_clr_lck_wB_offset :natural := inval_clr_lck_wA_offset + 1; +constant inval_clr_lck_wC_offset :natural := inval_clr_lck_wB_offset + 1; +constant inval_clr_lck_wD_offset :natural := inval_clr_lck_wC_offset + 1; +constant inval_clr_lck_wE_offset :natural := inval_clr_lck_wD_offset + 1; +constant inval_clr_lck_wF_offset :natural := inval_clr_lck_wE_offset + 1; +constant inval_clr_lck_wG_offset :natural := inval_clr_lck_wF_offset + 1; +constant inval_clr_lck_wH_offset :natural := inval_clr_lck_wG_offset + 1; +constant congr_cl_m_upd_wayA_offset :natural := inval_clr_lck_wH_offset + 1; +constant congr_cl_m_upd_wayB_offset :natural := congr_cl_m_upd_wayA_offset + 1; +constant congr_cl_m_upd_wayC_offset :natural := congr_cl_m_upd_wayB_offset + 1; +constant congr_cl_m_upd_wayD_offset :natural := congr_cl_m_upd_wayC_offset + 1; +constant congr_cl_m_upd_wayE_offset :natural := congr_cl_m_upd_wayD_offset + 1; +constant congr_cl_m_upd_wayF_offset :natural := congr_cl_m_upd_wayE_offset + 1; +constant congr_cl_m_upd_wayG_offset :natural := congr_cl_m_upd_wayF_offset + 1; +constant congr_cl_m_upd_wayH_offset :natural := congr_cl_m_upd_wayG_offset + 1; +constant ex3_congr_cl_offset :natural := congr_cl_m_upd_wayH_offset + 1; +constant rel24_congr_cl_offset :natural := ex3_congr_cl_offset + 6; +constant relu_s_congr_cl_offset :natural := rel24_congr_cl_offset + 6; +constant reload_way_clr_offset :natural := relu_s_congr_cl_offset + 6; +constant ex4_watchSet_coll_offset :natural := reload_way_clr_offset + 8; +constant rel_wayA_val_b_offset :natural := ex4_watchSet_coll_offset + 1; +constant rel_wayB_val_b_offset :natural := rel_wayA_val_b_offset + 6; +constant rel_wayC_val_b_offset :natural := rel_wayB_val_b_offset + 6; +constant rel_wayD_val_b_offset :natural := rel_wayC_val_b_offset + 6; +constant rel_wayE_val_b_offset :natural := rel_wayD_val_b_offset + 6; +constant rel_wayF_val_b_offset :natural := rel_wayE_val_b_offset + 6; +constant rel_wayG_val_b_offset :natural := rel_wayF_val_b_offset + 6; +constant rel_wayH_val_b_offset :natural := rel_wayG_val_b_offset + 6; +constant rel_val_stg2_offset :natural := rel_wayH_val_b_offset + 6; +constant rel_val_clr_offset :natural := rel_val_stg2_offset + 1; +constant rel_port_upd_offset :natural := rel_val_clr_offset + 1; +constant rel_val_stg4_offset :natural := rel_port_upd_offset + 1; +constant rel_binv_stg4_offset :natural := rel_val_stg4_offset + 1; +constant back_inval_stg3_offset :natural := rel_binv_stg4_offset + 1; +constant back_inval_stg4_offset :natural := back_inval_stg3_offset + 1; +constant back_inval_stg5_offset :natural := back_inval_stg4_offset + 1; +constant binv4_ex4_xuop_upd_offset :natural := back_inval_stg5_offset + 1; +constant binv4_ex4_dir_val_offset :natural := binv4_ex4_xuop_upd_offset + 1; +constant ex4_dir_err_val_offset :natural := binv4_ex4_dir_val_offset + 1; +constant ex5_dir_err_val_offset :natural := ex4_dir_err_val_offset + 1; +constant ex6_dir_err_val_offset :natural := ex5_dir_err_val_offset + 1; +constant derr2_stg_act_offset :natural := ex6_dir_err_val_offset + 1; +constant derr3_stg_act_offset :natural := derr2_stg_act_offset + 1; +constant derr4_stg_act_offset :natural := derr3_stg_act_offset + 1; +constant derr5_stg_act_offset :natural := derr4_stg_act_offset + 1; +constant ex4_dir_multihit_val_b_offset :natural := derr5_stg_act_offset + 1; +constant ex4_n_lsu_ddmh_flush_b_offset :natural := ex4_dir_multihit_val_b_offset + 1; +constant dcarr_up_way_addr_offset :natural := ex4_n_lsu_ddmh_flush_b_offset + 4; +constant reload_wayA_data_offset :natural := dcarr_up_way_addr_offset + 3; +constant reload_wayB_data_offset :natural := reload_wayA_data_offset + 6; +constant reload_wayC_data_offset :natural := reload_wayB_data_offset + 6; +constant reload_wayD_data_offset :natural := reload_wayC_data_offset + 6; +constant reload_wayE_data_offset :natural := reload_wayD_data_offset + 6; +constant reload_wayF_data_offset :natural := reload_wayE_data_offset + 6; +constant reload_wayG_data_offset :natural := reload_wayF_data_offset + 6; +constant reload_wayH_data_offset :natural := reload_wayG_data_offset + 6; +constant binv_wayA_upd_offset :natural := reload_wayH_data_offset + 6; +constant binv_wayB_upd_offset :natural := binv_wayA_upd_offset + 1; +constant binv_wayC_upd_offset :natural := binv_wayB_upd_offset + 1; +constant binv_wayD_upd_offset :natural := binv_wayC_upd_offset + 1; +constant binv_wayE_upd_offset :natural := binv_wayD_upd_offset + 1; +constant binv_wayF_upd_offset :natural := binv_wayE_upd_offset + 1; +constant binv_wayG_upd_offset :natural := binv_wayF_upd_offset + 1; +constant binv_wayH_upd_offset :natural := binv_wayG_upd_offset + 1; +constant binv_wayA_upd2_offset :natural := binv_wayH_upd_offset + 1; +constant binv_wayB_upd2_offset :natural := binv_wayA_upd2_offset + 1; +constant binv_wayC_upd2_offset :natural := binv_wayB_upd2_offset + 1; +constant binv_wayD_upd2_offset :natural := binv_wayC_upd2_offset + 1; +constant binv_wayE_upd2_offset :natural := binv_wayD_upd2_offset + 1; +constant binv_wayF_upd2_offset :natural := binv_wayE_upd2_offset + 1; +constant binv_wayG_upd2_offset :natural := binv_wayF_upd2_offset + 1; +constant binv_wayH_upd2_offset :natural := binv_wayG_upd2_offset + 1; +constant binv_wayA_upd3_offset :natural := binv_wayH_upd2_offset + 1; +constant binv_wayB_upd3_offset :natural := binv_wayA_upd3_offset + 1; +constant binv_wayC_upd3_offset :natural := binv_wayB_upd3_offset + 1; +constant binv_wayD_upd3_offset :natural := binv_wayC_upd3_offset + 1; +constant binv_wayE_upd3_offset :natural := binv_wayD_upd3_offset + 1; +constant binv_wayF_upd3_offset :natural := binv_wayE_upd3_offset + 1; +constant binv_wayG_upd3_offset :natural := binv_wayF_upd3_offset + 1; +constant binv_wayH_upd3_offset :natural := binv_wayG_upd3_offset + 1; +constant reload_wayA_upd_offset :natural := binv_wayH_upd3_offset + 1; +constant reload_wayB_upd_offset :natural := reload_wayA_upd_offset + 1; +constant reload_wayC_upd_offset :natural := reload_wayB_upd_offset + 1; +constant reload_wayD_upd_offset :natural := reload_wayC_upd_offset + 1; +constant reload_wayE_upd_offset :natural := reload_wayD_upd_offset + 1; +constant reload_wayF_upd_offset :natural := reload_wayE_upd_offset + 1; +constant reload_wayG_upd_offset :natural := reload_wayF_upd_offset + 1; +constant reload_wayH_upd_offset :natural := reload_wayG_upd_offset + 1; +constant reload_wayA_upd2_offset :natural := reload_wayH_upd_offset + 1; +constant reload_wayB_upd2_offset :natural := reload_wayA_upd2_offset + 1; +constant reload_wayC_upd2_offset :natural := reload_wayB_upd2_offset + 1; +constant reload_wayD_upd2_offset :natural := reload_wayC_upd2_offset + 1; +constant reload_wayE_upd2_offset :natural := reload_wayD_upd2_offset + 1; +constant reload_wayF_upd2_offset :natural := reload_wayE_upd2_offset + 1; +constant reload_wayG_upd2_offset :natural := reload_wayF_upd2_offset + 1; +constant reload_wayH_upd2_offset :natural := reload_wayG_upd2_offset + 1; +constant reload_wayA_upd3_offset :natural := reload_wayH_upd2_offset + 1; +constant reload_wayB_upd3_offset :natural := reload_wayA_upd3_offset + 1; +constant reload_wayC_upd3_offset :natural := reload_wayB_upd3_offset + 1; +constant reload_wayD_upd3_offset :natural := reload_wayC_upd3_offset + 1; +constant reload_wayE_upd3_offset :natural := reload_wayD_upd3_offset + 1; +constant reload_wayF_upd3_offset :natural := reload_wayE_upd3_offset + 1; +constant reload_wayG_upd3_offset :natural := reload_wayF_upd3_offset + 1; +constant reload_wayH_upd3_offset :natural := reload_wayG_upd3_offset + 1; +constant ex3_store_instr_offset :natural := reload_wayH_upd3_offset + 1; +constant ex3_lock_set_offset :natural := ex3_store_instr_offset + 1; +constant ex4_lock_set_offset :natural := ex3_lock_set_offset + 1; +constant ex5_lock_set_offset :natural := ex4_lock_set_offset + 1; +constant ex3_lock_clr_offset :natural := ex5_lock_set_offset + 1; +constant ex3_xuop_val_offset :natural := ex3_lock_clr_offset + 1; +constant ex4_xuop_val_offset :natural := ex3_xuop_val_offset + 1; +constant ex5_xuop_val_offset :natural := ex4_xuop_val_offset + 1; +constant rel_lock_set_offset :natural := ex5_xuop_val_offset + 1; +constant dcpar_err_stg1_offset :natural := rel_lock_set_offset + 1; +constant dcpar_err_stg2_offset :natural := dcpar_err_stg1_offset + 1; +constant dcpar_err_way_offset :natural := dcpar_err_stg2_offset + 1; +constant dcpar_err_way_inval_offset :natural := dcpar_err_way_offset + 8; +constant dcpar_err_cntr_offset :natural := dcpar_err_way_inval_offset + 8; +constant dcpar_err_ind_sel_offset :natural := dcpar_err_cntr_offset + 2; +constant dcpar_err_push_queue_offset :natural := dcpar_err_ind_sel_offset + 2; +constant ex5_way_hit_offset :natural := dcpar_err_push_queue_offset + 1; +constant ex7_way_hit_offset :natural := ex5_way_hit_offset + 8; +constant ex8_way_hit_offset :natural := ex7_way_hit_offset + 8; +constant ex9_way_hit_offset :natural := ex8_way_hit_offset + 8; +constant ex4_lose_watch_offset :natural := ex9_way_hit_offset + 8; +constant xucr0_cslc_xuop_offset :natural := ex4_lose_watch_offset + 4; +constant xucr0_cslc_binv_offset :natural := xucr0_cslc_xuop_offset + 1; +constant dci_compl_offset :natural := xucr0_cslc_binv_offset + 1; +constant dci_inval_all_offset :natural := dci_compl_offset + 1; +constant inv2_val_offset :natural := dci_inval_all_offset + 1; +constant perf_lsu_evnts_offset :natural := inv2_val_offset + 1; +constant lock_flash_clear_offset :natural := perf_lsu_evnts_offset + 5; +constant lock_flash_clear_val_offset :natural := lock_flash_clear_offset + 1; +constant rel_port_wren_offset :natural := lock_flash_clear_val_offset + 1; +constant ex3_thrd_id_offset :natural := rel_port_wren_offset + 1; +constant ex5_thrd_id_offset :natural := ex3_thrd_id_offset + 4; +constant ex3_l_fld_b1_offset :natural := ex5_thrd_id_offset + 4; +constant ex3_watch_set_offset :natural := ex3_l_fld_b1_offset + 1; +constant ex4_watch_set_offset :natural := ex3_watch_set_offset + 1; +constant ex5_watch_set_offset :natural := ex4_watch_set_offset + 1; +constant ex3_watch_clr_offset :natural := ex5_watch_set_offset + 1; +constant ex3_watch_clr_all_offset :natural := ex3_watch_clr_offset + 1; +constant ex3_watch_chk_offset :natural := ex3_watch_clr_all_offset + 1; +constant ex4_watch_chk_offset :natural := ex3_watch_chk_offset + 1; +constant ex5_watch_chk_offset :natural := ex4_watch_chk_offset + 1; +constant ex3_wclr_all_upd_offset :natural := ex5_watch_chk_offset + 1; +constant ex4_wclr_all_val_offset :natural := ex3_wclr_all_upd_offset + 1; +constant ex5_wclr_all_val_offset :natural := ex4_wclr_all_val_offset + 1; +constant ex6_wclr_all_val_offset :natural := ex5_wclr_all_val_offset + 1; +constant rel_thrd_id_offset :natural := ex6_wclr_all_val_offset + 1; +constant rel_watch_set_offset :natural := rel_thrd_id_offset + 4; +constant ex5_cr_watch_offset :natural := rel_watch_set_offset + 1; +constant ex4_watch_clr_all_offset :natural := ex5_cr_watch_offset + 1; +constant ex5_watch_clr_all_offset :natural := ex4_watch_clr_all_offset + 4; +constant ex6_watch_clr_all_offset :natural := ex5_watch_clr_all_offset + 4; +constant ex5_watch_clr_all_val_offset :natural := ex6_watch_clr_all_offset + 4; +constant ex5_lost_watch_upd_offset :natural := ex5_watch_clr_all_val_offset + 1; +constant ex4_watchlost_set_offset :natural := ex5_lost_watch_upd_offset + 4; +constant ex5_watchlost_set_offset :natural := ex4_watchlost_set_offset + 4; +constant rel_lost_watch_binv_offset :natural := ex5_watchlost_set_offset + 4; +constant lost_watch_evict_ovl_offset :natural := rel_lost_watch_binv_offset + 4; +constant rel_lost_watch_upd_offset :natural := lost_watch_evict_ovl_offset + 4; +constant lost_watch_evict_val_offset :natural := rel_lost_watch_upd_offset + 4; +constant lost_watch_inter_thrd_offset :natural := lost_watch_evict_val_offset + 4; +constant stm_watchlost_state_offset :natural := lost_watch_inter_thrd_offset + 4; +constant ex5_xuop_p0_upd_offset :natural := stm_watchlost_state_offset + 4; +constant rel_val_stgu_offset :natural := ex5_xuop_p0_upd_offset + 1; +constant p0_wren_offset :natural := rel_val_stgu_offset + 1; +constant p0_wren_cpy_offset :natural := p0_wren_offset + 1; +constant p0_wren_stg_offset :natural := p0_wren_cpy_offset + 1; +constant p1_wren_offset :natural := p0_wren_stg_offset + 1; +constant p1_wren_cpy_offset :natural := p1_wren_offset + 1; +constant ex3_thrd_m_offset :natural := p1_wren_cpy_offset + 1; +constant ex4_thrd_m_offset :natural := ex3_thrd_m_offset + 1; +constant ex5_thrd_m_offset :natural := ex4_thrd_m_offset + 1; +constant ex6_thrd_m_offset :natural := ex5_thrd_m_offset + 1; +constant ex7_ld_par_err_offset :natural := ex6_thrd_m_offset + 1; +constant ex8_ld_par_err_offset :natural := ex7_ld_par_err_offset + 1; +constant ex9_ld_par_err_offset :natural := ex8_ld_par_err_offset + 1; +constant ex6_ld_valid_offset :natural := ex9_ld_par_err_offset + 1; +constant ex7_ld_valid_offset :natural := ex6_ld_valid_offset + 1; +constant ex8_ld_valid_offset :natural := ex7_ld_valid_offset + 1; +constant ex9_ld_valid_offset :natural := ex8_ld_valid_offset + 1; +constant rel_in_progress_offset :natural := ex9_ld_valid_offset + 1; +constant inj_dir_multihit_offset :natural := rel_in_progress_offset + 1; +constant congr_cl_ex2_ex3_cmp_offset :natural := inj_dir_multihit_offset + 1; +constant congr_cl_ex2_ex4_cmp_offset :natural := congr_cl_ex2_ex3_cmp_offset + 1; +constant congr_cl_ex2_ex5_cmp_offset :natural := congr_cl_ex2_ex4_cmp_offset + 1; +constant congr_cl_ex2_ex6_cmp_offset :natural := congr_cl_ex2_ex5_cmp_offset + 1; +constant congr_cl_ex3_ex4_cmp_offset :natural := congr_cl_ex2_ex6_cmp_offset + 1; +constant congr_cl_ex3_ex5_cmp_offset :natural := congr_cl_ex3_ex4_cmp_offset + 1; +constant congr_cl_ex3_ex6_cmp_offset :natural := congr_cl_ex3_ex5_cmp_offset + 1; +constant congr_cl_ex4_ex5_cmp_offset :natural := congr_cl_ex3_ex6_cmp_offset + 1; +constant congr_cl_ex4_ex6_cmp_offset :natural := congr_cl_ex4_ex5_cmp_offset + 1; +constant congr_cl_ex4_ex7_cmp_offset :natural := congr_cl_ex4_ex6_cmp_offset + 1; +constant congr_cl_ex2_relu_cmp_offset :natural := congr_cl_ex4_ex7_cmp_offset + 1; +constant congr_cl_ex2_relu_s_cmp_offset :natural := congr_cl_ex2_relu_cmp_offset + 1; +constant congr_cl_ex2_rel_upd_cmp_offset :natural := congr_cl_ex2_relu_s_cmp_offset + 1; +constant congr_cl_rel13_ex3_cmp_offset :natural := congr_cl_ex2_rel_upd_cmp_offset + 1; +constant congr_cl_rel13_ex4_cmp_offset :natural := congr_cl_rel13_ex3_cmp_offset + 1; +constant congr_cl_rel13_ex5_cmp_offset :natural := congr_cl_rel13_ex4_cmp_offset + 1; +constant congr_cl_rel13_ex6_cmp_offset :natural := congr_cl_rel13_ex5_cmp_offset + 1; +constant congr_cl_rel13_relu_cmp_offset :natural := congr_cl_rel13_ex6_cmp_offset + 1; +constant congr_cl_rel13_relu_s_cmp_offset :natural := congr_cl_rel13_relu_cmp_offset + 1; +constant congr_cl_rel13_rel_upd_cmp_offset :natural := congr_cl_rel13_relu_s_cmp_offset + 1; +constant rel24_congr_cl_ex4_cmp_offset :natural := congr_cl_rel13_rel_upd_cmp_offset + 1; +constant rel24_congr_cl_ex5_cmp_offset :natural := rel24_congr_cl_ex4_cmp_offset + 1; +constant rel24_congr_cl_ex6_cmp_offset :natural := rel24_congr_cl_ex5_cmp_offset + 1; +constant relu_congr_cl_ex5_cmp_offset :natural := rel24_congr_cl_ex6_cmp_offset + 1; +constant relu_congr_cl_ex6_cmp_offset :natural := relu_congr_cl_ex5_cmp_offset + 1; +constant relu_congr_cl_ex7_cmp_offset :natural := relu_congr_cl_ex6_cmp_offset + 1; +constant ex4_err_det_way_offset :natural := relu_congr_cl_ex7_cmp_offset + 1; +constant ex4_perr_lck_lost_offset :natural := ex4_err_det_way_offset + 8; +constant ex4_perr_watch_lost_offset :natural := ex4_perr_lck_lost_offset + 1; +constant dcperr_lock_lost_offset :natural := ex4_perr_watch_lost_offset + 4; +constant binv7_ex7_way_upd_offset :natural := dcperr_lock_lost_offset + 1; +constant binv5_ex5_dir_data_offset :natural := binv7_ex7_way_upd_offset + 8; +constant binv7_ex7_dir_data_offset :natural := binv5_ex5_dir_data_offset + 5; +constant binv5_inval_watch_val_offset :natural := binv7_ex7_dir_data_offset + 5; +constant binv5_inval_lock_val_offset :natural := binv5_inval_watch_val_offset + 4; +constant ex4_snd_ld_l2_offset :natural := binv5_inval_lock_val_offset + 1; +constant ex4_ldq_full_flush_b_offset :natural := ex4_snd_ld_l2_offset + 1; +constant ex4_miss_offset :natural := ex4_ldq_full_flush_b_offset + 1; +constant my_spare0_latches_offset :natural := ex4_miss_offset + 1; +constant my_spare1_latches_offset :natural := my_spare0_latches_offset + 17; +constant rel_l1dump_cslc_offset :natural := my_spare1_latches_offset + 16; +constant rel_in_prog_stg1_offset :natural := rel_l1dump_cslc_offset + 1; +constant rel_in_prog_stg2_offset :natural := rel_in_prog_stg1_offset + 1; +constant rel_in_prog_stg3_offset :natural := rel_in_prog_stg2_offset + 1; +constant rel_in_prog_stg4_offset :natural := rel_in_prog_stg3_offset + 1; +constant rel_in_prog_stg5_offset :natural := rel_in_prog_stg4_offset + 1; +constant dcpar_err_stg1_act_offset :natural := rel_in_prog_stg5_offset + 1; +constant dcpar_err_stg2_act_offset :natural := dcpar_err_stg1_act_offset + 1; +constant rel3_perr_stg_act_offset :natural := dcpar_err_stg2_act_offset + 1; +constant rel4_perr_stg_act_offset :natural := rel3_perr_stg_act_offset + 1; +constant scan_right :natural := rel4_perr_stg_act_offset + 1 - 1; +---------------------------- +-- signals +---------------------------- +signal p0_congr_cl0_m :std_ulogic; +signal p1_congr_cl0_m :std_ulogic; +signal p0_congr_cl0_act_d :std_ulogic; +signal p0_congr_cl0_act_q :std_ulogic; +signal p1_congr_cl0_act_d :std_ulogic; +signal p1_congr_cl0_act_q :std_ulogic; +signal congr_cl0_act :std_ulogic; +signal congr_cl0_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl0_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu0_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd0_wayA :std_ulogic; +signal p1_way_data_upd0_wayA :std_ulogic; +signal congr_cl0_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl0_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu0_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd0_wayB :std_ulogic; +signal p1_way_data_upd0_wayB :std_ulogic; +signal congr_cl0_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl0_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu0_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd0_wayC :std_ulogic; +signal p1_way_data_upd0_wayC :std_ulogic; +signal congr_cl0_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl0_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu0_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd0_wayD :std_ulogic; +signal p1_way_data_upd0_wayD :std_ulogic; +signal congr_cl0_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl0_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu0_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd0_wayE :std_ulogic; +signal p1_way_data_upd0_wayE :std_ulogic; +signal congr_cl0_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl0_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu0_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd0_wayF :std_ulogic; +signal p1_way_data_upd0_wayF :std_ulogic; +signal congr_cl0_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl0_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu0_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd0_wayG :std_ulogic; +signal p1_way_data_upd0_wayG :std_ulogic; +signal congr_cl0_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl0_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu0_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd0_wayH :std_ulogic; +signal p1_way_data_upd0_wayH :std_ulogic; +signal p0_congr_cl1_m :std_ulogic; +signal p1_congr_cl1_m :std_ulogic; +signal p0_congr_cl1_act_d :std_ulogic; +signal p0_congr_cl1_act_q :std_ulogic; +signal p1_congr_cl1_act_d :std_ulogic; +signal p1_congr_cl1_act_q :std_ulogic; +signal congr_cl1_act :std_ulogic; +signal congr_cl1_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl1_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu1_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd1_wayA :std_ulogic; +signal p1_way_data_upd1_wayA :std_ulogic; +signal congr_cl1_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl1_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu1_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd1_wayB :std_ulogic; +signal p1_way_data_upd1_wayB :std_ulogic; +signal congr_cl1_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl1_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu1_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd1_wayC :std_ulogic; +signal p1_way_data_upd1_wayC :std_ulogic; +signal congr_cl1_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl1_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu1_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd1_wayD :std_ulogic; +signal p1_way_data_upd1_wayD :std_ulogic; +signal congr_cl1_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl1_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu1_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd1_wayE :std_ulogic; +signal p1_way_data_upd1_wayE :std_ulogic; +signal congr_cl1_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl1_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu1_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd1_wayF :std_ulogic; +signal p1_way_data_upd1_wayF :std_ulogic; +signal congr_cl1_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl1_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu1_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd1_wayG :std_ulogic; +signal p1_way_data_upd1_wayG :std_ulogic; +signal congr_cl1_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl1_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu1_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd1_wayH :std_ulogic; +signal p1_way_data_upd1_wayH :std_ulogic; +signal p0_congr_cl2_m :std_ulogic; +signal p1_congr_cl2_m :std_ulogic; +signal p0_congr_cl2_act_d :std_ulogic; +signal p0_congr_cl2_act_q :std_ulogic; +signal p1_congr_cl2_act_d :std_ulogic; +signal p1_congr_cl2_act_q :std_ulogic; +signal congr_cl2_act :std_ulogic; +signal congr_cl2_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl2_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu2_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd2_wayA :std_ulogic; +signal p1_way_data_upd2_wayA :std_ulogic; +signal congr_cl2_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl2_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu2_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd2_wayB :std_ulogic; +signal p1_way_data_upd2_wayB :std_ulogic; +signal congr_cl2_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl2_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu2_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd2_wayC :std_ulogic; +signal p1_way_data_upd2_wayC :std_ulogic; +signal congr_cl2_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl2_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu2_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd2_wayD :std_ulogic; +signal p1_way_data_upd2_wayD :std_ulogic; +signal congr_cl2_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl2_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu2_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd2_wayE :std_ulogic; +signal p1_way_data_upd2_wayE :std_ulogic; +signal congr_cl2_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl2_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu2_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd2_wayF :std_ulogic; +signal p1_way_data_upd2_wayF :std_ulogic; +signal congr_cl2_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl2_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu2_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd2_wayG :std_ulogic; +signal p1_way_data_upd2_wayG :std_ulogic; +signal congr_cl2_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl2_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu2_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd2_wayH :std_ulogic; +signal p1_way_data_upd2_wayH :std_ulogic; +signal p0_congr_cl3_m :std_ulogic; +signal p1_congr_cl3_m :std_ulogic; +signal p0_congr_cl3_act_d :std_ulogic; +signal p0_congr_cl3_act_q :std_ulogic; +signal p1_congr_cl3_act_d :std_ulogic; +signal p1_congr_cl3_act_q :std_ulogic; +signal congr_cl3_act :std_ulogic; +signal congr_cl3_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl3_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu3_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd3_wayA :std_ulogic; +signal p1_way_data_upd3_wayA :std_ulogic; +signal congr_cl3_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl3_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu3_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd3_wayB :std_ulogic; +signal p1_way_data_upd3_wayB :std_ulogic; +signal congr_cl3_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl3_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu3_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd3_wayC :std_ulogic; +signal p1_way_data_upd3_wayC :std_ulogic; +signal congr_cl3_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl3_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu3_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd3_wayD :std_ulogic; +signal p1_way_data_upd3_wayD :std_ulogic; +signal congr_cl3_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl3_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu3_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd3_wayE :std_ulogic; +signal p1_way_data_upd3_wayE :std_ulogic; +signal congr_cl3_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl3_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu3_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd3_wayF :std_ulogic; +signal p1_way_data_upd3_wayF :std_ulogic; +signal congr_cl3_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl3_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu3_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd3_wayG :std_ulogic; +signal p1_way_data_upd3_wayG :std_ulogic; +signal congr_cl3_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl3_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu3_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd3_wayH :std_ulogic; +signal p1_way_data_upd3_wayH :std_ulogic; +signal p0_congr_cl4_m :std_ulogic; +signal p1_congr_cl4_m :std_ulogic; +signal p0_congr_cl4_act_d :std_ulogic; +signal p0_congr_cl4_act_q :std_ulogic; +signal p1_congr_cl4_act_d :std_ulogic; +signal p1_congr_cl4_act_q :std_ulogic; +signal congr_cl4_act :std_ulogic; +signal congr_cl4_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl4_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu4_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd4_wayA :std_ulogic; +signal p1_way_data_upd4_wayA :std_ulogic; +signal congr_cl4_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl4_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu4_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd4_wayB :std_ulogic; +signal p1_way_data_upd4_wayB :std_ulogic; +signal congr_cl4_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl4_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu4_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd4_wayC :std_ulogic; +signal p1_way_data_upd4_wayC :std_ulogic; +signal congr_cl4_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl4_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu4_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd4_wayD :std_ulogic; +signal p1_way_data_upd4_wayD :std_ulogic; +signal congr_cl4_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl4_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu4_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd4_wayE :std_ulogic; +signal p1_way_data_upd4_wayE :std_ulogic; +signal congr_cl4_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl4_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu4_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd4_wayF :std_ulogic; +signal p1_way_data_upd4_wayF :std_ulogic; +signal congr_cl4_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl4_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu4_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd4_wayG :std_ulogic; +signal p1_way_data_upd4_wayG :std_ulogic; +signal congr_cl4_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl4_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu4_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd4_wayH :std_ulogic; +signal p1_way_data_upd4_wayH :std_ulogic; +signal p0_congr_cl5_m :std_ulogic; +signal p1_congr_cl5_m :std_ulogic; +signal p0_congr_cl5_act_d :std_ulogic; +signal p0_congr_cl5_act_q :std_ulogic; +signal p1_congr_cl5_act_d :std_ulogic; +signal p1_congr_cl5_act_q :std_ulogic; +signal congr_cl5_act :std_ulogic; +signal congr_cl5_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl5_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu5_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd5_wayA :std_ulogic; +signal p1_way_data_upd5_wayA :std_ulogic; +signal congr_cl5_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl5_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu5_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd5_wayB :std_ulogic; +signal p1_way_data_upd5_wayB :std_ulogic; +signal congr_cl5_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl5_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu5_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd5_wayC :std_ulogic; +signal p1_way_data_upd5_wayC :std_ulogic; +signal congr_cl5_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl5_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu5_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd5_wayD :std_ulogic; +signal p1_way_data_upd5_wayD :std_ulogic; +signal congr_cl5_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl5_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu5_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd5_wayE :std_ulogic; +signal p1_way_data_upd5_wayE :std_ulogic; +signal congr_cl5_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl5_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu5_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd5_wayF :std_ulogic; +signal p1_way_data_upd5_wayF :std_ulogic; +signal congr_cl5_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl5_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu5_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd5_wayG :std_ulogic; +signal p1_way_data_upd5_wayG :std_ulogic; +signal congr_cl5_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl5_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu5_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd5_wayH :std_ulogic; +signal p1_way_data_upd5_wayH :std_ulogic; +signal p0_congr_cl6_m :std_ulogic; +signal p1_congr_cl6_m :std_ulogic; +signal p0_congr_cl6_act_d :std_ulogic; +signal p0_congr_cl6_act_q :std_ulogic; +signal p1_congr_cl6_act_d :std_ulogic; +signal p1_congr_cl6_act_q :std_ulogic; +signal congr_cl6_act :std_ulogic; +signal congr_cl6_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl6_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu6_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd6_wayA :std_ulogic; +signal p1_way_data_upd6_wayA :std_ulogic; +signal congr_cl6_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl6_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu6_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd6_wayB :std_ulogic; +signal p1_way_data_upd6_wayB :std_ulogic; +signal congr_cl6_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl6_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu6_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd6_wayC :std_ulogic; +signal p1_way_data_upd6_wayC :std_ulogic; +signal congr_cl6_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl6_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu6_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd6_wayD :std_ulogic; +signal p1_way_data_upd6_wayD :std_ulogic; +signal congr_cl6_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl6_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu6_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd6_wayE :std_ulogic; +signal p1_way_data_upd6_wayE :std_ulogic; +signal congr_cl6_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl6_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu6_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd6_wayF :std_ulogic; +signal p1_way_data_upd6_wayF :std_ulogic; +signal congr_cl6_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl6_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu6_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd6_wayG :std_ulogic; +signal p1_way_data_upd6_wayG :std_ulogic; +signal congr_cl6_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl6_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu6_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd6_wayH :std_ulogic; +signal p1_way_data_upd6_wayH :std_ulogic; +signal p0_congr_cl7_m :std_ulogic; +signal p1_congr_cl7_m :std_ulogic; +signal p0_congr_cl7_act_d :std_ulogic; +signal p0_congr_cl7_act_q :std_ulogic; +signal p1_congr_cl7_act_d :std_ulogic; +signal p1_congr_cl7_act_q :std_ulogic; +signal congr_cl7_act :std_ulogic; +signal congr_cl7_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl7_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu7_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd7_wayA :std_ulogic; +signal p1_way_data_upd7_wayA :std_ulogic; +signal congr_cl7_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl7_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu7_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd7_wayB :std_ulogic; +signal p1_way_data_upd7_wayB :std_ulogic; +signal congr_cl7_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl7_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu7_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd7_wayC :std_ulogic; +signal p1_way_data_upd7_wayC :std_ulogic; +signal congr_cl7_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl7_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu7_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd7_wayD :std_ulogic; +signal p1_way_data_upd7_wayD :std_ulogic; +signal congr_cl7_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl7_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu7_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd7_wayE :std_ulogic; +signal p1_way_data_upd7_wayE :std_ulogic; +signal congr_cl7_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl7_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu7_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd7_wayF :std_ulogic; +signal p1_way_data_upd7_wayF :std_ulogic; +signal congr_cl7_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl7_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu7_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd7_wayG :std_ulogic; +signal p1_way_data_upd7_wayG :std_ulogic; +signal congr_cl7_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl7_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu7_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd7_wayH :std_ulogic; +signal p1_way_data_upd7_wayH :std_ulogic; +signal p0_congr_cl8_m :std_ulogic; +signal p1_congr_cl8_m :std_ulogic; +signal p0_congr_cl8_act_d :std_ulogic; +signal p0_congr_cl8_act_q :std_ulogic; +signal p1_congr_cl8_act_d :std_ulogic; +signal p1_congr_cl8_act_q :std_ulogic; +signal congr_cl8_act :std_ulogic; +signal congr_cl8_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl8_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu8_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd8_wayA :std_ulogic; +signal p1_way_data_upd8_wayA :std_ulogic; +signal congr_cl8_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl8_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu8_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd8_wayB :std_ulogic; +signal p1_way_data_upd8_wayB :std_ulogic; +signal congr_cl8_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl8_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu8_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd8_wayC :std_ulogic; +signal p1_way_data_upd8_wayC :std_ulogic; +signal congr_cl8_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl8_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu8_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd8_wayD :std_ulogic; +signal p1_way_data_upd8_wayD :std_ulogic; +signal congr_cl8_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl8_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu8_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd8_wayE :std_ulogic; +signal p1_way_data_upd8_wayE :std_ulogic; +signal congr_cl8_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl8_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu8_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd8_wayF :std_ulogic; +signal p1_way_data_upd8_wayF :std_ulogic; +signal congr_cl8_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl8_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu8_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd8_wayG :std_ulogic; +signal p1_way_data_upd8_wayG :std_ulogic; +signal congr_cl8_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl8_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu8_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd8_wayH :std_ulogic; +signal p1_way_data_upd8_wayH :std_ulogic; +signal p0_congr_cl9_m :std_ulogic; +signal p1_congr_cl9_m :std_ulogic; +signal p0_congr_cl9_act_d :std_ulogic; +signal p0_congr_cl9_act_q :std_ulogic; +signal p1_congr_cl9_act_d :std_ulogic; +signal p1_congr_cl9_act_q :std_ulogic; +signal congr_cl9_act :std_ulogic; +signal congr_cl9_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl9_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu9_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd9_wayA :std_ulogic; +signal p1_way_data_upd9_wayA :std_ulogic; +signal congr_cl9_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl9_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu9_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd9_wayB :std_ulogic; +signal p1_way_data_upd9_wayB :std_ulogic; +signal congr_cl9_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl9_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu9_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd9_wayC :std_ulogic; +signal p1_way_data_upd9_wayC :std_ulogic; +signal congr_cl9_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl9_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu9_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd9_wayD :std_ulogic; +signal p1_way_data_upd9_wayD :std_ulogic; +signal congr_cl9_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl9_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu9_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd9_wayE :std_ulogic; +signal p1_way_data_upd9_wayE :std_ulogic; +signal congr_cl9_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl9_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu9_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd9_wayF :std_ulogic; +signal p1_way_data_upd9_wayF :std_ulogic; +signal congr_cl9_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl9_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu9_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd9_wayG :std_ulogic; +signal p1_way_data_upd9_wayG :std_ulogic; +signal congr_cl9_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl9_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu9_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd9_wayH :std_ulogic; +signal p1_way_data_upd9_wayH :std_ulogic; +signal p0_congr_cl10_m :std_ulogic; +signal p1_congr_cl10_m :std_ulogic; +signal p0_congr_cl10_act_d :std_ulogic; +signal p0_congr_cl10_act_q :std_ulogic; +signal p1_congr_cl10_act_d :std_ulogic; +signal p1_congr_cl10_act_q :std_ulogic; +signal congr_cl10_act :std_ulogic; +signal congr_cl10_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl10_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu10_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd10_wayA :std_ulogic; +signal p1_way_data_upd10_wayA :std_ulogic; +signal congr_cl10_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl10_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu10_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd10_wayB :std_ulogic; +signal p1_way_data_upd10_wayB :std_ulogic; +signal congr_cl10_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl10_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu10_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd10_wayC :std_ulogic; +signal p1_way_data_upd10_wayC :std_ulogic; +signal congr_cl10_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl10_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu10_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd10_wayD :std_ulogic; +signal p1_way_data_upd10_wayD :std_ulogic; +signal congr_cl10_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl10_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu10_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd10_wayE :std_ulogic; +signal p1_way_data_upd10_wayE :std_ulogic; +signal congr_cl10_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl10_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu10_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd10_wayF :std_ulogic; +signal p1_way_data_upd10_wayF :std_ulogic; +signal congr_cl10_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl10_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu10_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd10_wayG :std_ulogic; +signal p1_way_data_upd10_wayG :std_ulogic; +signal congr_cl10_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl10_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu10_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd10_wayH :std_ulogic; +signal p1_way_data_upd10_wayH :std_ulogic; +signal p0_congr_cl11_m :std_ulogic; +signal p1_congr_cl11_m :std_ulogic; +signal p0_congr_cl11_act_d :std_ulogic; +signal p0_congr_cl11_act_q :std_ulogic; +signal p1_congr_cl11_act_d :std_ulogic; +signal p1_congr_cl11_act_q :std_ulogic; +signal congr_cl11_act :std_ulogic; +signal congr_cl11_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl11_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu11_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd11_wayA :std_ulogic; +signal p1_way_data_upd11_wayA :std_ulogic; +signal congr_cl11_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl11_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu11_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd11_wayB :std_ulogic; +signal p1_way_data_upd11_wayB :std_ulogic; +signal congr_cl11_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl11_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu11_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd11_wayC :std_ulogic; +signal p1_way_data_upd11_wayC :std_ulogic; +signal congr_cl11_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl11_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu11_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd11_wayD :std_ulogic; +signal p1_way_data_upd11_wayD :std_ulogic; +signal congr_cl11_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl11_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu11_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd11_wayE :std_ulogic; +signal p1_way_data_upd11_wayE :std_ulogic; +signal congr_cl11_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl11_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu11_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd11_wayF :std_ulogic; +signal p1_way_data_upd11_wayF :std_ulogic; +signal congr_cl11_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl11_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu11_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd11_wayG :std_ulogic; +signal p1_way_data_upd11_wayG :std_ulogic; +signal congr_cl11_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl11_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu11_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd11_wayH :std_ulogic; +signal p1_way_data_upd11_wayH :std_ulogic; +signal p0_congr_cl12_m :std_ulogic; +signal p1_congr_cl12_m :std_ulogic; +signal p0_congr_cl12_act_d :std_ulogic; +signal p0_congr_cl12_act_q :std_ulogic; +signal p1_congr_cl12_act_d :std_ulogic; +signal p1_congr_cl12_act_q :std_ulogic; +signal congr_cl12_act :std_ulogic; +signal congr_cl12_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl12_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu12_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd12_wayA :std_ulogic; +signal p1_way_data_upd12_wayA :std_ulogic; +signal congr_cl12_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl12_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu12_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd12_wayB :std_ulogic; +signal p1_way_data_upd12_wayB :std_ulogic; +signal congr_cl12_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl12_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu12_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd12_wayC :std_ulogic; +signal p1_way_data_upd12_wayC :std_ulogic; +signal congr_cl12_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl12_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu12_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd12_wayD :std_ulogic; +signal p1_way_data_upd12_wayD :std_ulogic; +signal congr_cl12_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl12_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu12_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd12_wayE :std_ulogic; +signal p1_way_data_upd12_wayE :std_ulogic; +signal congr_cl12_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl12_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu12_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd12_wayF :std_ulogic; +signal p1_way_data_upd12_wayF :std_ulogic; +signal congr_cl12_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl12_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu12_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd12_wayG :std_ulogic; +signal p1_way_data_upd12_wayG :std_ulogic; +signal congr_cl12_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl12_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu12_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd12_wayH :std_ulogic; +signal p1_way_data_upd12_wayH :std_ulogic; +signal p0_congr_cl13_m :std_ulogic; +signal p1_congr_cl13_m :std_ulogic; +signal p0_congr_cl13_act_d :std_ulogic; +signal p0_congr_cl13_act_q :std_ulogic; +signal p1_congr_cl13_act_d :std_ulogic; +signal p1_congr_cl13_act_q :std_ulogic; +signal congr_cl13_act :std_ulogic; +signal congr_cl13_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl13_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu13_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd13_wayA :std_ulogic; +signal p1_way_data_upd13_wayA :std_ulogic; +signal congr_cl13_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl13_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu13_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd13_wayB :std_ulogic; +signal p1_way_data_upd13_wayB :std_ulogic; +signal congr_cl13_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl13_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu13_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd13_wayC :std_ulogic; +signal p1_way_data_upd13_wayC :std_ulogic; +signal congr_cl13_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl13_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu13_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd13_wayD :std_ulogic; +signal p1_way_data_upd13_wayD :std_ulogic; +signal congr_cl13_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl13_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu13_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd13_wayE :std_ulogic; +signal p1_way_data_upd13_wayE :std_ulogic; +signal congr_cl13_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl13_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu13_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd13_wayF :std_ulogic; +signal p1_way_data_upd13_wayF :std_ulogic; +signal congr_cl13_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl13_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu13_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd13_wayG :std_ulogic; +signal p1_way_data_upd13_wayG :std_ulogic; +signal congr_cl13_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl13_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu13_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd13_wayH :std_ulogic; +signal p1_way_data_upd13_wayH :std_ulogic; +signal p0_congr_cl14_m :std_ulogic; +signal p1_congr_cl14_m :std_ulogic; +signal p0_congr_cl14_act_d :std_ulogic; +signal p0_congr_cl14_act_q :std_ulogic; +signal p1_congr_cl14_act_d :std_ulogic; +signal p1_congr_cl14_act_q :std_ulogic; +signal congr_cl14_act :std_ulogic; +signal congr_cl14_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl14_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu14_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd14_wayA :std_ulogic; +signal p1_way_data_upd14_wayA :std_ulogic; +signal congr_cl14_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl14_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu14_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd14_wayB :std_ulogic; +signal p1_way_data_upd14_wayB :std_ulogic; +signal congr_cl14_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl14_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu14_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd14_wayC :std_ulogic; +signal p1_way_data_upd14_wayC :std_ulogic; +signal congr_cl14_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl14_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu14_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd14_wayD :std_ulogic; +signal p1_way_data_upd14_wayD :std_ulogic; +signal congr_cl14_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl14_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu14_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd14_wayE :std_ulogic; +signal p1_way_data_upd14_wayE :std_ulogic; +signal congr_cl14_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl14_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu14_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd14_wayF :std_ulogic; +signal p1_way_data_upd14_wayF :std_ulogic; +signal congr_cl14_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl14_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu14_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd14_wayG :std_ulogic; +signal p1_way_data_upd14_wayG :std_ulogic; +signal congr_cl14_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl14_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu14_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd14_wayH :std_ulogic; +signal p1_way_data_upd14_wayH :std_ulogic; +signal p0_congr_cl15_m :std_ulogic; +signal p1_congr_cl15_m :std_ulogic; +signal p0_congr_cl15_act_d :std_ulogic; +signal p0_congr_cl15_act_q :std_ulogic; +signal p1_congr_cl15_act_d :std_ulogic; +signal p1_congr_cl15_act_q :std_ulogic; +signal congr_cl15_act :std_ulogic; +signal congr_cl15_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl15_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu15_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd15_wayA :std_ulogic; +signal p1_way_data_upd15_wayA :std_ulogic; +signal congr_cl15_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl15_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu15_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd15_wayB :std_ulogic; +signal p1_way_data_upd15_wayB :std_ulogic; +signal congr_cl15_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl15_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu15_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd15_wayC :std_ulogic; +signal p1_way_data_upd15_wayC :std_ulogic; +signal congr_cl15_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl15_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu15_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd15_wayD :std_ulogic; +signal p1_way_data_upd15_wayD :std_ulogic; +signal congr_cl15_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl15_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu15_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd15_wayE :std_ulogic; +signal p1_way_data_upd15_wayE :std_ulogic; +signal congr_cl15_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl15_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu15_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd15_wayF :std_ulogic; +signal p1_way_data_upd15_wayF :std_ulogic; +signal congr_cl15_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl15_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu15_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd15_wayG :std_ulogic; +signal p1_way_data_upd15_wayG :std_ulogic; +signal congr_cl15_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl15_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu15_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd15_wayH :std_ulogic; +signal p1_way_data_upd15_wayH :std_ulogic; +signal p0_congr_cl16_m :std_ulogic; +signal p1_congr_cl16_m :std_ulogic; +signal p0_congr_cl16_act_d :std_ulogic; +signal p0_congr_cl16_act_q :std_ulogic; +signal p1_congr_cl16_act_d :std_ulogic; +signal p1_congr_cl16_act_q :std_ulogic; +signal congr_cl16_act :std_ulogic; +signal congr_cl16_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl16_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu16_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd16_wayA :std_ulogic; +signal p1_way_data_upd16_wayA :std_ulogic; +signal congr_cl16_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl16_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu16_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd16_wayB :std_ulogic; +signal p1_way_data_upd16_wayB :std_ulogic; +signal congr_cl16_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl16_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu16_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd16_wayC :std_ulogic; +signal p1_way_data_upd16_wayC :std_ulogic; +signal congr_cl16_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl16_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu16_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd16_wayD :std_ulogic; +signal p1_way_data_upd16_wayD :std_ulogic; +signal congr_cl16_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl16_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu16_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd16_wayE :std_ulogic; +signal p1_way_data_upd16_wayE :std_ulogic; +signal congr_cl16_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl16_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu16_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd16_wayF :std_ulogic; +signal p1_way_data_upd16_wayF :std_ulogic; +signal congr_cl16_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl16_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu16_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd16_wayG :std_ulogic; +signal p1_way_data_upd16_wayG :std_ulogic; +signal congr_cl16_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl16_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu16_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd16_wayH :std_ulogic; +signal p1_way_data_upd16_wayH :std_ulogic; +signal p0_congr_cl17_m :std_ulogic; +signal p1_congr_cl17_m :std_ulogic; +signal p0_congr_cl17_act_d :std_ulogic; +signal p0_congr_cl17_act_q :std_ulogic; +signal p1_congr_cl17_act_d :std_ulogic; +signal p1_congr_cl17_act_q :std_ulogic; +signal congr_cl17_act :std_ulogic; +signal congr_cl17_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl17_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu17_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd17_wayA :std_ulogic; +signal p1_way_data_upd17_wayA :std_ulogic; +signal congr_cl17_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl17_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu17_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd17_wayB :std_ulogic; +signal p1_way_data_upd17_wayB :std_ulogic; +signal congr_cl17_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl17_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu17_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd17_wayC :std_ulogic; +signal p1_way_data_upd17_wayC :std_ulogic; +signal congr_cl17_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl17_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu17_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd17_wayD :std_ulogic; +signal p1_way_data_upd17_wayD :std_ulogic; +signal congr_cl17_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl17_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu17_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd17_wayE :std_ulogic; +signal p1_way_data_upd17_wayE :std_ulogic; +signal congr_cl17_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl17_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu17_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd17_wayF :std_ulogic; +signal p1_way_data_upd17_wayF :std_ulogic; +signal congr_cl17_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl17_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu17_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd17_wayG :std_ulogic; +signal p1_way_data_upd17_wayG :std_ulogic; +signal congr_cl17_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl17_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu17_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd17_wayH :std_ulogic; +signal p1_way_data_upd17_wayH :std_ulogic; +signal p0_congr_cl18_m :std_ulogic; +signal p1_congr_cl18_m :std_ulogic; +signal p0_congr_cl18_act_d :std_ulogic; +signal p0_congr_cl18_act_q :std_ulogic; +signal p1_congr_cl18_act_d :std_ulogic; +signal p1_congr_cl18_act_q :std_ulogic; +signal congr_cl18_act :std_ulogic; +signal congr_cl18_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl18_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu18_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd18_wayA :std_ulogic; +signal p1_way_data_upd18_wayA :std_ulogic; +signal congr_cl18_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl18_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu18_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd18_wayB :std_ulogic; +signal p1_way_data_upd18_wayB :std_ulogic; +signal congr_cl18_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl18_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu18_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd18_wayC :std_ulogic; +signal p1_way_data_upd18_wayC :std_ulogic; +signal congr_cl18_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl18_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu18_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd18_wayD :std_ulogic; +signal p1_way_data_upd18_wayD :std_ulogic; +signal congr_cl18_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl18_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu18_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd18_wayE :std_ulogic; +signal p1_way_data_upd18_wayE :std_ulogic; +signal congr_cl18_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl18_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu18_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd18_wayF :std_ulogic; +signal p1_way_data_upd18_wayF :std_ulogic; +signal congr_cl18_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl18_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu18_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd18_wayG :std_ulogic; +signal p1_way_data_upd18_wayG :std_ulogic; +signal congr_cl18_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl18_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu18_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd18_wayH :std_ulogic; +signal p1_way_data_upd18_wayH :std_ulogic; +signal p0_congr_cl19_m :std_ulogic; +signal p1_congr_cl19_m :std_ulogic; +signal p0_congr_cl19_act_d :std_ulogic; +signal p0_congr_cl19_act_q :std_ulogic; +signal p1_congr_cl19_act_d :std_ulogic; +signal p1_congr_cl19_act_q :std_ulogic; +signal congr_cl19_act :std_ulogic; +signal congr_cl19_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl19_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu19_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd19_wayA :std_ulogic; +signal p1_way_data_upd19_wayA :std_ulogic; +signal congr_cl19_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl19_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu19_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd19_wayB :std_ulogic; +signal p1_way_data_upd19_wayB :std_ulogic; +signal congr_cl19_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl19_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu19_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd19_wayC :std_ulogic; +signal p1_way_data_upd19_wayC :std_ulogic; +signal congr_cl19_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl19_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu19_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd19_wayD :std_ulogic; +signal p1_way_data_upd19_wayD :std_ulogic; +signal congr_cl19_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl19_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu19_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd19_wayE :std_ulogic; +signal p1_way_data_upd19_wayE :std_ulogic; +signal congr_cl19_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl19_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu19_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd19_wayF :std_ulogic; +signal p1_way_data_upd19_wayF :std_ulogic; +signal congr_cl19_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl19_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu19_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd19_wayG :std_ulogic; +signal p1_way_data_upd19_wayG :std_ulogic; +signal congr_cl19_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl19_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu19_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd19_wayH :std_ulogic; +signal p1_way_data_upd19_wayH :std_ulogic; +signal p0_congr_cl20_m :std_ulogic; +signal p1_congr_cl20_m :std_ulogic; +signal p0_congr_cl20_act_d :std_ulogic; +signal p0_congr_cl20_act_q :std_ulogic; +signal p1_congr_cl20_act_d :std_ulogic; +signal p1_congr_cl20_act_q :std_ulogic; +signal congr_cl20_act :std_ulogic; +signal congr_cl20_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl20_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu20_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd20_wayA :std_ulogic; +signal p1_way_data_upd20_wayA :std_ulogic; +signal congr_cl20_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl20_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu20_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd20_wayB :std_ulogic; +signal p1_way_data_upd20_wayB :std_ulogic; +signal congr_cl20_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl20_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu20_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd20_wayC :std_ulogic; +signal p1_way_data_upd20_wayC :std_ulogic; +signal congr_cl20_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl20_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu20_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd20_wayD :std_ulogic; +signal p1_way_data_upd20_wayD :std_ulogic; +signal congr_cl20_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl20_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu20_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd20_wayE :std_ulogic; +signal p1_way_data_upd20_wayE :std_ulogic; +signal congr_cl20_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl20_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu20_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd20_wayF :std_ulogic; +signal p1_way_data_upd20_wayF :std_ulogic; +signal congr_cl20_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl20_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu20_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd20_wayG :std_ulogic; +signal p1_way_data_upd20_wayG :std_ulogic; +signal congr_cl20_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl20_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu20_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd20_wayH :std_ulogic; +signal p1_way_data_upd20_wayH :std_ulogic; +signal p0_congr_cl21_m :std_ulogic; +signal p1_congr_cl21_m :std_ulogic; +signal p0_congr_cl21_act_d :std_ulogic; +signal p0_congr_cl21_act_q :std_ulogic; +signal p1_congr_cl21_act_d :std_ulogic; +signal p1_congr_cl21_act_q :std_ulogic; +signal congr_cl21_act :std_ulogic; +signal congr_cl21_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl21_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu21_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd21_wayA :std_ulogic; +signal p1_way_data_upd21_wayA :std_ulogic; +signal congr_cl21_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl21_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu21_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd21_wayB :std_ulogic; +signal p1_way_data_upd21_wayB :std_ulogic; +signal congr_cl21_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl21_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu21_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd21_wayC :std_ulogic; +signal p1_way_data_upd21_wayC :std_ulogic; +signal congr_cl21_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl21_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu21_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd21_wayD :std_ulogic; +signal p1_way_data_upd21_wayD :std_ulogic; +signal congr_cl21_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl21_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu21_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd21_wayE :std_ulogic; +signal p1_way_data_upd21_wayE :std_ulogic; +signal congr_cl21_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl21_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu21_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd21_wayF :std_ulogic; +signal p1_way_data_upd21_wayF :std_ulogic; +signal congr_cl21_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl21_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu21_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd21_wayG :std_ulogic; +signal p1_way_data_upd21_wayG :std_ulogic; +signal congr_cl21_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl21_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu21_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd21_wayH :std_ulogic; +signal p1_way_data_upd21_wayH :std_ulogic; +signal p0_congr_cl22_m :std_ulogic; +signal p1_congr_cl22_m :std_ulogic; +signal p0_congr_cl22_act_d :std_ulogic; +signal p0_congr_cl22_act_q :std_ulogic; +signal p1_congr_cl22_act_d :std_ulogic; +signal p1_congr_cl22_act_q :std_ulogic; +signal congr_cl22_act :std_ulogic; +signal congr_cl22_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl22_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu22_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd22_wayA :std_ulogic; +signal p1_way_data_upd22_wayA :std_ulogic; +signal congr_cl22_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl22_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu22_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd22_wayB :std_ulogic; +signal p1_way_data_upd22_wayB :std_ulogic; +signal congr_cl22_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl22_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu22_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd22_wayC :std_ulogic; +signal p1_way_data_upd22_wayC :std_ulogic; +signal congr_cl22_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl22_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu22_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd22_wayD :std_ulogic; +signal p1_way_data_upd22_wayD :std_ulogic; +signal congr_cl22_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl22_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu22_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd22_wayE :std_ulogic; +signal p1_way_data_upd22_wayE :std_ulogic; +signal congr_cl22_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl22_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu22_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd22_wayF :std_ulogic; +signal p1_way_data_upd22_wayF :std_ulogic; +signal congr_cl22_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl22_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu22_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd22_wayG :std_ulogic; +signal p1_way_data_upd22_wayG :std_ulogic; +signal congr_cl22_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl22_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu22_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd22_wayH :std_ulogic; +signal p1_way_data_upd22_wayH :std_ulogic; +signal p0_congr_cl23_m :std_ulogic; +signal p1_congr_cl23_m :std_ulogic; +signal p0_congr_cl23_act_d :std_ulogic; +signal p0_congr_cl23_act_q :std_ulogic; +signal p1_congr_cl23_act_d :std_ulogic; +signal p1_congr_cl23_act_q :std_ulogic; +signal congr_cl23_act :std_ulogic; +signal congr_cl23_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl23_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu23_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd23_wayA :std_ulogic; +signal p1_way_data_upd23_wayA :std_ulogic; +signal congr_cl23_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl23_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu23_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd23_wayB :std_ulogic; +signal p1_way_data_upd23_wayB :std_ulogic; +signal congr_cl23_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl23_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu23_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd23_wayC :std_ulogic; +signal p1_way_data_upd23_wayC :std_ulogic; +signal congr_cl23_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl23_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu23_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd23_wayD :std_ulogic; +signal p1_way_data_upd23_wayD :std_ulogic; +signal congr_cl23_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl23_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu23_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd23_wayE :std_ulogic; +signal p1_way_data_upd23_wayE :std_ulogic; +signal congr_cl23_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl23_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu23_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd23_wayF :std_ulogic; +signal p1_way_data_upd23_wayF :std_ulogic; +signal congr_cl23_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl23_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu23_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd23_wayG :std_ulogic; +signal p1_way_data_upd23_wayG :std_ulogic; +signal congr_cl23_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl23_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu23_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd23_wayH :std_ulogic; +signal p1_way_data_upd23_wayH :std_ulogic; +signal p0_congr_cl24_m :std_ulogic; +signal p1_congr_cl24_m :std_ulogic; +signal p0_congr_cl24_act_d :std_ulogic; +signal p0_congr_cl24_act_q :std_ulogic; +signal p1_congr_cl24_act_d :std_ulogic; +signal p1_congr_cl24_act_q :std_ulogic; +signal congr_cl24_act :std_ulogic; +signal congr_cl24_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl24_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu24_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd24_wayA :std_ulogic; +signal p1_way_data_upd24_wayA :std_ulogic; +signal congr_cl24_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl24_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu24_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd24_wayB :std_ulogic; +signal p1_way_data_upd24_wayB :std_ulogic; +signal congr_cl24_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl24_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu24_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd24_wayC :std_ulogic; +signal p1_way_data_upd24_wayC :std_ulogic; +signal congr_cl24_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl24_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu24_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd24_wayD :std_ulogic; +signal p1_way_data_upd24_wayD :std_ulogic; +signal congr_cl24_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl24_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu24_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd24_wayE :std_ulogic; +signal p1_way_data_upd24_wayE :std_ulogic; +signal congr_cl24_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl24_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu24_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd24_wayF :std_ulogic; +signal p1_way_data_upd24_wayF :std_ulogic; +signal congr_cl24_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl24_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu24_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd24_wayG :std_ulogic; +signal p1_way_data_upd24_wayG :std_ulogic; +signal congr_cl24_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl24_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu24_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd24_wayH :std_ulogic; +signal p1_way_data_upd24_wayH :std_ulogic; +signal p0_congr_cl25_m :std_ulogic; +signal p1_congr_cl25_m :std_ulogic; +signal p0_congr_cl25_act_d :std_ulogic; +signal p0_congr_cl25_act_q :std_ulogic; +signal p1_congr_cl25_act_d :std_ulogic; +signal p1_congr_cl25_act_q :std_ulogic; +signal congr_cl25_act :std_ulogic; +signal congr_cl25_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl25_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu25_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd25_wayA :std_ulogic; +signal p1_way_data_upd25_wayA :std_ulogic; +signal congr_cl25_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl25_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu25_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd25_wayB :std_ulogic; +signal p1_way_data_upd25_wayB :std_ulogic; +signal congr_cl25_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl25_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu25_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd25_wayC :std_ulogic; +signal p1_way_data_upd25_wayC :std_ulogic; +signal congr_cl25_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl25_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu25_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd25_wayD :std_ulogic; +signal p1_way_data_upd25_wayD :std_ulogic; +signal congr_cl25_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl25_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu25_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd25_wayE :std_ulogic; +signal p1_way_data_upd25_wayE :std_ulogic; +signal congr_cl25_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl25_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu25_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd25_wayF :std_ulogic; +signal p1_way_data_upd25_wayF :std_ulogic; +signal congr_cl25_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl25_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu25_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd25_wayG :std_ulogic; +signal p1_way_data_upd25_wayG :std_ulogic; +signal congr_cl25_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl25_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu25_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd25_wayH :std_ulogic; +signal p1_way_data_upd25_wayH :std_ulogic; +signal p0_congr_cl26_m :std_ulogic; +signal p1_congr_cl26_m :std_ulogic; +signal p0_congr_cl26_act_d :std_ulogic; +signal p0_congr_cl26_act_q :std_ulogic; +signal p1_congr_cl26_act_d :std_ulogic; +signal p1_congr_cl26_act_q :std_ulogic; +signal congr_cl26_act :std_ulogic; +signal congr_cl26_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl26_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu26_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd26_wayA :std_ulogic; +signal p1_way_data_upd26_wayA :std_ulogic; +signal congr_cl26_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl26_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu26_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd26_wayB :std_ulogic; +signal p1_way_data_upd26_wayB :std_ulogic; +signal congr_cl26_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl26_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu26_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd26_wayC :std_ulogic; +signal p1_way_data_upd26_wayC :std_ulogic; +signal congr_cl26_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl26_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu26_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd26_wayD :std_ulogic; +signal p1_way_data_upd26_wayD :std_ulogic; +signal congr_cl26_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl26_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu26_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd26_wayE :std_ulogic; +signal p1_way_data_upd26_wayE :std_ulogic; +signal congr_cl26_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl26_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu26_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd26_wayF :std_ulogic; +signal p1_way_data_upd26_wayF :std_ulogic; +signal congr_cl26_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl26_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu26_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd26_wayG :std_ulogic; +signal p1_way_data_upd26_wayG :std_ulogic; +signal congr_cl26_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl26_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu26_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd26_wayH :std_ulogic; +signal p1_way_data_upd26_wayH :std_ulogic; +signal p0_congr_cl27_m :std_ulogic; +signal p1_congr_cl27_m :std_ulogic; +signal p0_congr_cl27_act_d :std_ulogic; +signal p0_congr_cl27_act_q :std_ulogic; +signal p1_congr_cl27_act_d :std_ulogic; +signal p1_congr_cl27_act_q :std_ulogic; +signal congr_cl27_act :std_ulogic; +signal congr_cl27_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl27_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu27_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd27_wayA :std_ulogic; +signal p1_way_data_upd27_wayA :std_ulogic; +signal congr_cl27_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl27_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu27_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd27_wayB :std_ulogic; +signal p1_way_data_upd27_wayB :std_ulogic; +signal congr_cl27_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl27_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu27_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd27_wayC :std_ulogic; +signal p1_way_data_upd27_wayC :std_ulogic; +signal congr_cl27_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl27_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu27_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd27_wayD :std_ulogic; +signal p1_way_data_upd27_wayD :std_ulogic; +signal congr_cl27_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl27_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu27_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd27_wayE :std_ulogic; +signal p1_way_data_upd27_wayE :std_ulogic; +signal congr_cl27_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl27_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu27_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd27_wayF :std_ulogic; +signal p1_way_data_upd27_wayF :std_ulogic; +signal congr_cl27_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl27_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu27_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd27_wayG :std_ulogic; +signal p1_way_data_upd27_wayG :std_ulogic; +signal congr_cl27_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl27_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu27_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd27_wayH :std_ulogic; +signal p1_way_data_upd27_wayH :std_ulogic; +signal p0_congr_cl28_m :std_ulogic; +signal p1_congr_cl28_m :std_ulogic; +signal p0_congr_cl28_act_d :std_ulogic; +signal p0_congr_cl28_act_q :std_ulogic; +signal p1_congr_cl28_act_d :std_ulogic; +signal p1_congr_cl28_act_q :std_ulogic; +signal congr_cl28_act :std_ulogic; +signal congr_cl28_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl28_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu28_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd28_wayA :std_ulogic; +signal p1_way_data_upd28_wayA :std_ulogic; +signal congr_cl28_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl28_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu28_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd28_wayB :std_ulogic; +signal p1_way_data_upd28_wayB :std_ulogic; +signal congr_cl28_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl28_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu28_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd28_wayC :std_ulogic; +signal p1_way_data_upd28_wayC :std_ulogic; +signal congr_cl28_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl28_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu28_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd28_wayD :std_ulogic; +signal p1_way_data_upd28_wayD :std_ulogic; +signal congr_cl28_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl28_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu28_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd28_wayE :std_ulogic; +signal p1_way_data_upd28_wayE :std_ulogic; +signal congr_cl28_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl28_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu28_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd28_wayF :std_ulogic; +signal p1_way_data_upd28_wayF :std_ulogic; +signal congr_cl28_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl28_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu28_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd28_wayG :std_ulogic; +signal p1_way_data_upd28_wayG :std_ulogic; +signal congr_cl28_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl28_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu28_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd28_wayH :std_ulogic; +signal p1_way_data_upd28_wayH :std_ulogic; +signal p0_congr_cl29_m :std_ulogic; +signal p1_congr_cl29_m :std_ulogic; +signal p0_congr_cl29_act_d :std_ulogic; +signal p0_congr_cl29_act_q :std_ulogic; +signal p1_congr_cl29_act_d :std_ulogic; +signal p1_congr_cl29_act_q :std_ulogic; +signal congr_cl29_act :std_ulogic; +signal congr_cl29_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl29_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu29_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd29_wayA :std_ulogic; +signal p1_way_data_upd29_wayA :std_ulogic; +signal congr_cl29_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl29_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu29_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd29_wayB :std_ulogic; +signal p1_way_data_upd29_wayB :std_ulogic; +signal congr_cl29_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl29_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu29_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd29_wayC :std_ulogic; +signal p1_way_data_upd29_wayC :std_ulogic; +signal congr_cl29_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl29_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu29_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd29_wayD :std_ulogic; +signal p1_way_data_upd29_wayD :std_ulogic; +signal congr_cl29_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl29_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu29_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd29_wayE :std_ulogic; +signal p1_way_data_upd29_wayE :std_ulogic; +signal congr_cl29_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl29_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu29_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd29_wayF :std_ulogic; +signal p1_way_data_upd29_wayF :std_ulogic; +signal congr_cl29_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl29_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu29_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd29_wayG :std_ulogic; +signal p1_way_data_upd29_wayG :std_ulogic; +signal congr_cl29_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl29_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu29_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd29_wayH :std_ulogic; +signal p1_way_data_upd29_wayH :std_ulogic; +signal p0_congr_cl30_m :std_ulogic; +signal p1_congr_cl30_m :std_ulogic; +signal p0_congr_cl30_act_d :std_ulogic; +signal p0_congr_cl30_act_q :std_ulogic; +signal p1_congr_cl30_act_d :std_ulogic; +signal p1_congr_cl30_act_q :std_ulogic; +signal congr_cl30_act :std_ulogic; +signal congr_cl30_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl30_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu30_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd30_wayA :std_ulogic; +signal p1_way_data_upd30_wayA :std_ulogic; +signal congr_cl30_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl30_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu30_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd30_wayB :std_ulogic; +signal p1_way_data_upd30_wayB :std_ulogic; +signal congr_cl30_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl30_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu30_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd30_wayC :std_ulogic; +signal p1_way_data_upd30_wayC :std_ulogic; +signal congr_cl30_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl30_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu30_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd30_wayD :std_ulogic; +signal p1_way_data_upd30_wayD :std_ulogic; +signal congr_cl30_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl30_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu30_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd30_wayE :std_ulogic; +signal p1_way_data_upd30_wayE :std_ulogic; +signal congr_cl30_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl30_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu30_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd30_wayF :std_ulogic; +signal p1_way_data_upd30_wayF :std_ulogic; +signal congr_cl30_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl30_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu30_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd30_wayG :std_ulogic; +signal p1_way_data_upd30_wayG :std_ulogic; +signal congr_cl30_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl30_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu30_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd30_wayH :std_ulogic; +signal p1_way_data_upd30_wayH :std_ulogic; +signal p0_congr_cl31_m :std_ulogic; +signal p1_congr_cl31_m :std_ulogic; +signal p0_congr_cl31_act_d :std_ulogic; +signal p0_congr_cl31_act_q :std_ulogic; +signal p1_congr_cl31_act_d :std_ulogic; +signal p1_congr_cl31_act_q :std_ulogic; +signal congr_cl31_act :std_ulogic; +signal congr_cl31_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl31_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu31_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd31_wayA :std_ulogic; +signal p1_way_data_upd31_wayA :std_ulogic; +signal congr_cl31_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl31_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu31_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd31_wayB :std_ulogic; +signal p1_way_data_upd31_wayB :std_ulogic; +signal congr_cl31_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl31_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu31_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd31_wayC :std_ulogic; +signal p1_way_data_upd31_wayC :std_ulogic; +signal congr_cl31_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl31_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu31_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd31_wayD :std_ulogic; +signal p1_way_data_upd31_wayD :std_ulogic; +signal congr_cl31_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl31_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu31_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd31_wayE :std_ulogic; +signal p1_way_data_upd31_wayE :std_ulogic; +signal congr_cl31_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl31_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu31_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd31_wayF :std_ulogic; +signal p1_way_data_upd31_wayF :std_ulogic; +signal congr_cl31_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl31_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu31_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd31_wayG :std_ulogic; +signal p1_way_data_upd31_wayG :std_ulogic; +signal congr_cl31_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl31_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu31_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd31_wayH :std_ulogic; +signal p1_way_data_upd31_wayH :std_ulogic; +signal p0_congr_cl32_m :std_ulogic; +signal p1_congr_cl32_m :std_ulogic; +signal p0_congr_cl32_act_d :std_ulogic; +signal p0_congr_cl32_act_q :std_ulogic; +signal p1_congr_cl32_act_d :std_ulogic; +signal p1_congr_cl32_act_q :std_ulogic; +signal congr_cl32_act :std_ulogic; +signal congr_cl32_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl32_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu32_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd32_wayA :std_ulogic; +signal p1_way_data_upd32_wayA :std_ulogic; +signal congr_cl32_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl32_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu32_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd32_wayB :std_ulogic; +signal p1_way_data_upd32_wayB :std_ulogic; +signal congr_cl32_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl32_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu32_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd32_wayC :std_ulogic; +signal p1_way_data_upd32_wayC :std_ulogic; +signal congr_cl32_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl32_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu32_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd32_wayD :std_ulogic; +signal p1_way_data_upd32_wayD :std_ulogic; +signal congr_cl32_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl32_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu32_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd32_wayE :std_ulogic; +signal p1_way_data_upd32_wayE :std_ulogic; +signal congr_cl32_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl32_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu32_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd32_wayF :std_ulogic; +signal p1_way_data_upd32_wayF :std_ulogic; +signal congr_cl32_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl32_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu32_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd32_wayG :std_ulogic; +signal p1_way_data_upd32_wayG :std_ulogic; +signal congr_cl32_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl32_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu32_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd32_wayH :std_ulogic; +signal p1_way_data_upd32_wayH :std_ulogic; +signal p0_congr_cl33_m :std_ulogic; +signal p1_congr_cl33_m :std_ulogic; +signal p0_congr_cl33_act_d :std_ulogic; +signal p0_congr_cl33_act_q :std_ulogic; +signal p1_congr_cl33_act_d :std_ulogic; +signal p1_congr_cl33_act_q :std_ulogic; +signal congr_cl33_act :std_ulogic; +signal congr_cl33_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl33_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu33_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd33_wayA :std_ulogic; +signal p1_way_data_upd33_wayA :std_ulogic; +signal congr_cl33_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl33_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu33_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd33_wayB :std_ulogic; +signal p1_way_data_upd33_wayB :std_ulogic; +signal congr_cl33_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl33_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu33_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd33_wayC :std_ulogic; +signal p1_way_data_upd33_wayC :std_ulogic; +signal congr_cl33_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl33_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu33_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd33_wayD :std_ulogic; +signal p1_way_data_upd33_wayD :std_ulogic; +signal congr_cl33_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl33_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu33_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd33_wayE :std_ulogic; +signal p1_way_data_upd33_wayE :std_ulogic; +signal congr_cl33_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl33_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu33_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd33_wayF :std_ulogic; +signal p1_way_data_upd33_wayF :std_ulogic; +signal congr_cl33_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl33_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu33_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd33_wayG :std_ulogic; +signal p1_way_data_upd33_wayG :std_ulogic; +signal congr_cl33_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl33_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu33_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd33_wayH :std_ulogic; +signal p1_way_data_upd33_wayH :std_ulogic; +signal p0_congr_cl34_m :std_ulogic; +signal p1_congr_cl34_m :std_ulogic; +signal p0_congr_cl34_act_d :std_ulogic; +signal p0_congr_cl34_act_q :std_ulogic; +signal p1_congr_cl34_act_d :std_ulogic; +signal p1_congr_cl34_act_q :std_ulogic; +signal congr_cl34_act :std_ulogic; +signal congr_cl34_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl34_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu34_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd34_wayA :std_ulogic; +signal p1_way_data_upd34_wayA :std_ulogic; +signal congr_cl34_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl34_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu34_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd34_wayB :std_ulogic; +signal p1_way_data_upd34_wayB :std_ulogic; +signal congr_cl34_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl34_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu34_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd34_wayC :std_ulogic; +signal p1_way_data_upd34_wayC :std_ulogic; +signal congr_cl34_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl34_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu34_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd34_wayD :std_ulogic; +signal p1_way_data_upd34_wayD :std_ulogic; +signal congr_cl34_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl34_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu34_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd34_wayE :std_ulogic; +signal p1_way_data_upd34_wayE :std_ulogic; +signal congr_cl34_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl34_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu34_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd34_wayF :std_ulogic; +signal p1_way_data_upd34_wayF :std_ulogic; +signal congr_cl34_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl34_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu34_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd34_wayG :std_ulogic; +signal p1_way_data_upd34_wayG :std_ulogic; +signal congr_cl34_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl34_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu34_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd34_wayH :std_ulogic; +signal p1_way_data_upd34_wayH :std_ulogic; +signal p0_congr_cl35_m :std_ulogic; +signal p1_congr_cl35_m :std_ulogic; +signal p0_congr_cl35_act_d :std_ulogic; +signal p0_congr_cl35_act_q :std_ulogic; +signal p1_congr_cl35_act_d :std_ulogic; +signal p1_congr_cl35_act_q :std_ulogic; +signal congr_cl35_act :std_ulogic; +signal congr_cl35_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl35_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu35_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd35_wayA :std_ulogic; +signal p1_way_data_upd35_wayA :std_ulogic; +signal congr_cl35_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl35_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu35_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd35_wayB :std_ulogic; +signal p1_way_data_upd35_wayB :std_ulogic; +signal congr_cl35_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl35_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu35_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd35_wayC :std_ulogic; +signal p1_way_data_upd35_wayC :std_ulogic; +signal congr_cl35_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl35_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu35_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd35_wayD :std_ulogic; +signal p1_way_data_upd35_wayD :std_ulogic; +signal congr_cl35_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl35_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu35_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd35_wayE :std_ulogic; +signal p1_way_data_upd35_wayE :std_ulogic; +signal congr_cl35_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl35_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu35_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd35_wayF :std_ulogic; +signal p1_way_data_upd35_wayF :std_ulogic; +signal congr_cl35_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl35_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu35_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd35_wayG :std_ulogic; +signal p1_way_data_upd35_wayG :std_ulogic; +signal congr_cl35_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl35_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu35_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd35_wayH :std_ulogic; +signal p1_way_data_upd35_wayH :std_ulogic; +signal p0_congr_cl36_m :std_ulogic; +signal p1_congr_cl36_m :std_ulogic; +signal p0_congr_cl36_act_d :std_ulogic; +signal p0_congr_cl36_act_q :std_ulogic; +signal p1_congr_cl36_act_d :std_ulogic; +signal p1_congr_cl36_act_q :std_ulogic; +signal congr_cl36_act :std_ulogic; +signal congr_cl36_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl36_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu36_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd36_wayA :std_ulogic; +signal p1_way_data_upd36_wayA :std_ulogic; +signal congr_cl36_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl36_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu36_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd36_wayB :std_ulogic; +signal p1_way_data_upd36_wayB :std_ulogic; +signal congr_cl36_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl36_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu36_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd36_wayC :std_ulogic; +signal p1_way_data_upd36_wayC :std_ulogic; +signal congr_cl36_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl36_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu36_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd36_wayD :std_ulogic; +signal p1_way_data_upd36_wayD :std_ulogic; +signal congr_cl36_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl36_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu36_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd36_wayE :std_ulogic; +signal p1_way_data_upd36_wayE :std_ulogic; +signal congr_cl36_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl36_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu36_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd36_wayF :std_ulogic; +signal p1_way_data_upd36_wayF :std_ulogic; +signal congr_cl36_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl36_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu36_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd36_wayG :std_ulogic; +signal p1_way_data_upd36_wayG :std_ulogic; +signal congr_cl36_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl36_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu36_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd36_wayH :std_ulogic; +signal p1_way_data_upd36_wayH :std_ulogic; +signal p0_congr_cl37_m :std_ulogic; +signal p1_congr_cl37_m :std_ulogic; +signal p0_congr_cl37_act_d :std_ulogic; +signal p0_congr_cl37_act_q :std_ulogic; +signal p1_congr_cl37_act_d :std_ulogic; +signal p1_congr_cl37_act_q :std_ulogic; +signal congr_cl37_act :std_ulogic; +signal congr_cl37_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl37_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu37_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd37_wayA :std_ulogic; +signal p1_way_data_upd37_wayA :std_ulogic; +signal congr_cl37_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl37_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu37_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd37_wayB :std_ulogic; +signal p1_way_data_upd37_wayB :std_ulogic; +signal congr_cl37_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl37_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu37_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd37_wayC :std_ulogic; +signal p1_way_data_upd37_wayC :std_ulogic; +signal congr_cl37_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl37_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu37_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd37_wayD :std_ulogic; +signal p1_way_data_upd37_wayD :std_ulogic; +signal congr_cl37_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl37_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu37_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd37_wayE :std_ulogic; +signal p1_way_data_upd37_wayE :std_ulogic; +signal congr_cl37_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl37_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu37_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd37_wayF :std_ulogic; +signal p1_way_data_upd37_wayF :std_ulogic; +signal congr_cl37_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl37_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu37_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd37_wayG :std_ulogic; +signal p1_way_data_upd37_wayG :std_ulogic; +signal congr_cl37_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl37_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu37_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd37_wayH :std_ulogic; +signal p1_way_data_upd37_wayH :std_ulogic; +signal p0_congr_cl38_m :std_ulogic; +signal p1_congr_cl38_m :std_ulogic; +signal p0_congr_cl38_act_d :std_ulogic; +signal p0_congr_cl38_act_q :std_ulogic; +signal p1_congr_cl38_act_d :std_ulogic; +signal p1_congr_cl38_act_q :std_ulogic; +signal congr_cl38_act :std_ulogic; +signal congr_cl38_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl38_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu38_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd38_wayA :std_ulogic; +signal p1_way_data_upd38_wayA :std_ulogic; +signal congr_cl38_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl38_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu38_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd38_wayB :std_ulogic; +signal p1_way_data_upd38_wayB :std_ulogic; +signal congr_cl38_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl38_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu38_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd38_wayC :std_ulogic; +signal p1_way_data_upd38_wayC :std_ulogic; +signal congr_cl38_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl38_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu38_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd38_wayD :std_ulogic; +signal p1_way_data_upd38_wayD :std_ulogic; +signal congr_cl38_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl38_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu38_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd38_wayE :std_ulogic; +signal p1_way_data_upd38_wayE :std_ulogic; +signal congr_cl38_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl38_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu38_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd38_wayF :std_ulogic; +signal p1_way_data_upd38_wayF :std_ulogic; +signal congr_cl38_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl38_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu38_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd38_wayG :std_ulogic; +signal p1_way_data_upd38_wayG :std_ulogic; +signal congr_cl38_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl38_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu38_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd38_wayH :std_ulogic; +signal p1_way_data_upd38_wayH :std_ulogic; +signal p0_congr_cl39_m :std_ulogic; +signal p1_congr_cl39_m :std_ulogic; +signal p0_congr_cl39_act_d :std_ulogic; +signal p0_congr_cl39_act_q :std_ulogic; +signal p1_congr_cl39_act_d :std_ulogic; +signal p1_congr_cl39_act_q :std_ulogic; +signal congr_cl39_act :std_ulogic; +signal congr_cl39_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl39_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu39_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd39_wayA :std_ulogic; +signal p1_way_data_upd39_wayA :std_ulogic; +signal congr_cl39_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl39_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu39_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd39_wayB :std_ulogic; +signal p1_way_data_upd39_wayB :std_ulogic; +signal congr_cl39_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl39_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu39_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd39_wayC :std_ulogic; +signal p1_way_data_upd39_wayC :std_ulogic; +signal congr_cl39_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl39_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu39_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd39_wayD :std_ulogic; +signal p1_way_data_upd39_wayD :std_ulogic; +signal congr_cl39_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl39_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu39_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd39_wayE :std_ulogic; +signal p1_way_data_upd39_wayE :std_ulogic; +signal congr_cl39_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl39_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu39_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd39_wayF :std_ulogic; +signal p1_way_data_upd39_wayF :std_ulogic; +signal congr_cl39_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl39_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu39_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd39_wayG :std_ulogic; +signal p1_way_data_upd39_wayG :std_ulogic; +signal congr_cl39_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl39_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu39_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd39_wayH :std_ulogic; +signal p1_way_data_upd39_wayH :std_ulogic; +signal p0_congr_cl40_m :std_ulogic; +signal p1_congr_cl40_m :std_ulogic; +signal p0_congr_cl40_act_d :std_ulogic; +signal p0_congr_cl40_act_q :std_ulogic; +signal p1_congr_cl40_act_d :std_ulogic; +signal p1_congr_cl40_act_q :std_ulogic; +signal congr_cl40_act :std_ulogic; +signal congr_cl40_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl40_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu40_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd40_wayA :std_ulogic; +signal p1_way_data_upd40_wayA :std_ulogic; +signal congr_cl40_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl40_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu40_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd40_wayB :std_ulogic; +signal p1_way_data_upd40_wayB :std_ulogic; +signal congr_cl40_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl40_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu40_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd40_wayC :std_ulogic; +signal p1_way_data_upd40_wayC :std_ulogic; +signal congr_cl40_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl40_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu40_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd40_wayD :std_ulogic; +signal p1_way_data_upd40_wayD :std_ulogic; +signal congr_cl40_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl40_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu40_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd40_wayE :std_ulogic; +signal p1_way_data_upd40_wayE :std_ulogic; +signal congr_cl40_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl40_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu40_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd40_wayF :std_ulogic; +signal p1_way_data_upd40_wayF :std_ulogic; +signal congr_cl40_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl40_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu40_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd40_wayG :std_ulogic; +signal p1_way_data_upd40_wayG :std_ulogic; +signal congr_cl40_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl40_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu40_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd40_wayH :std_ulogic; +signal p1_way_data_upd40_wayH :std_ulogic; +signal p0_congr_cl41_m :std_ulogic; +signal p1_congr_cl41_m :std_ulogic; +signal p0_congr_cl41_act_d :std_ulogic; +signal p0_congr_cl41_act_q :std_ulogic; +signal p1_congr_cl41_act_d :std_ulogic; +signal p1_congr_cl41_act_q :std_ulogic; +signal congr_cl41_act :std_ulogic; +signal congr_cl41_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl41_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu41_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd41_wayA :std_ulogic; +signal p1_way_data_upd41_wayA :std_ulogic; +signal congr_cl41_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl41_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu41_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd41_wayB :std_ulogic; +signal p1_way_data_upd41_wayB :std_ulogic; +signal congr_cl41_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl41_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu41_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd41_wayC :std_ulogic; +signal p1_way_data_upd41_wayC :std_ulogic; +signal congr_cl41_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl41_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu41_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd41_wayD :std_ulogic; +signal p1_way_data_upd41_wayD :std_ulogic; +signal congr_cl41_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl41_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu41_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd41_wayE :std_ulogic; +signal p1_way_data_upd41_wayE :std_ulogic; +signal congr_cl41_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl41_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu41_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd41_wayF :std_ulogic; +signal p1_way_data_upd41_wayF :std_ulogic; +signal congr_cl41_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl41_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu41_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd41_wayG :std_ulogic; +signal p1_way_data_upd41_wayG :std_ulogic; +signal congr_cl41_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl41_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu41_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd41_wayH :std_ulogic; +signal p1_way_data_upd41_wayH :std_ulogic; +signal p0_congr_cl42_m :std_ulogic; +signal p1_congr_cl42_m :std_ulogic; +signal p0_congr_cl42_act_d :std_ulogic; +signal p0_congr_cl42_act_q :std_ulogic; +signal p1_congr_cl42_act_d :std_ulogic; +signal p1_congr_cl42_act_q :std_ulogic; +signal congr_cl42_act :std_ulogic; +signal congr_cl42_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl42_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu42_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd42_wayA :std_ulogic; +signal p1_way_data_upd42_wayA :std_ulogic; +signal congr_cl42_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl42_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu42_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd42_wayB :std_ulogic; +signal p1_way_data_upd42_wayB :std_ulogic; +signal congr_cl42_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl42_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu42_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd42_wayC :std_ulogic; +signal p1_way_data_upd42_wayC :std_ulogic; +signal congr_cl42_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl42_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu42_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd42_wayD :std_ulogic; +signal p1_way_data_upd42_wayD :std_ulogic; +signal congr_cl42_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl42_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu42_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd42_wayE :std_ulogic; +signal p1_way_data_upd42_wayE :std_ulogic; +signal congr_cl42_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl42_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu42_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd42_wayF :std_ulogic; +signal p1_way_data_upd42_wayF :std_ulogic; +signal congr_cl42_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl42_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu42_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd42_wayG :std_ulogic; +signal p1_way_data_upd42_wayG :std_ulogic; +signal congr_cl42_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl42_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu42_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd42_wayH :std_ulogic; +signal p1_way_data_upd42_wayH :std_ulogic; +signal p0_congr_cl43_m :std_ulogic; +signal p1_congr_cl43_m :std_ulogic; +signal p0_congr_cl43_act_d :std_ulogic; +signal p0_congr_cl43_act_q :std_ulogic; +signal p1_congr_cl43_act_d :std_ulogic; +signal p1_congr_cl43_act_q :std_ulogic; +signal congr_cl43_act :std_ulogic; +signal congr_cl43_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl43_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu43_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd43_wayA :std_ulogic; +signal p1_way_data_upd43_wayA :std_ulogic; +signal congr_cl43_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl43_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu43_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd43_wayB :std_ulogic; +signal p1_way_data_upd43_wayB :std_ulogic; +signal congr_cl43_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl43_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu43_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd43_wayC :std_ulogic; +signal p1_way_data_upd43_wayC :std_ulogic; +signal congr_cl43_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl43_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu43_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd43_wayD :std_ulogic; +signal p1_way_data_upd43_wayD :std_ulogic; +signal congr_cl43_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl43_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu43_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd43_wayE :std_ulogic; +signal p1_way_data_upd43_wayE :std_ulogic; +signal congr_cl43_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl43_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu43_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd43_wayF :std_ulogic; +signal p1_way_data_upd43_wayF :std_ulogic; +signal congr_cl43_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl43_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu43_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd43_wayG :std_ulogic; +signal p1_way_data_upd43_wayG :std_ulogic; +signal congr_cl43_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl43_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu43_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd43_wayH :std_ulogic; +signal p1_way_data_upd43_wayH :std_ulogic; +signal p0_congr_cl44_m :std_ulogic; +signal p1_congr_cl44_m :std_ulogic; +signal p0_congr_cl44_act_d :std_ulogic; +signal p0_congr_cl44_act_q :std_ulogic; +signal p1_congr_cl44_act_d :std_ulogic; +signal p1_congr_cl44_act_q :std_ulogic; +signal congr_cl44_act :std_ulogic; +signal congr_cl44_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl44_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu44_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd44_wayA :std_ulogic; +signal p1_way_data_upd44_wayA :std_ulogic; +signal congr_cl44_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl44_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu44_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd44_wayB :std_ulogic; +signal p1_way_data_upd44_wayB :std_ulogic; +signal congr_cl44_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl44_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu44_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd44_wayC :std_ulogic; +signal p1_way_data_upd44_wayC :std_ulogic; +signal congr_cl44_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl44_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu44_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd44_wayD :std_ulogic; +signal p1_way_data_upd44_wayD :std_ulogic; +signal congr_cl44_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl44_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu44_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd44_wayE :std_ulogic; +signal p1_way_data_upd44_wayE :std_ulogic; +signal congr_cl44_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl44_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu44_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd44_wayF :std_ulogic; +signal p1_way_data_upd44_wayF :std_ulogic; +signal congr_cl44_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl44_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu44_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd44_wayG :std_ulogic; +signal p1_way_data_upd44_wayG :std_ulogic; +signal congr_cl44_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl44_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu44_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd44_wayH :std_ulogic; +signal p1_way_data_upd44_wayH :std_ulogic; +signal p0_congr_cl45_m :std_ulogic; +signal p1_congr_cl45_m :std_ulogic; +signal p0_congr_cl45_act_d :std_ulogic; +signal p0_congr_cl45_act_q :std_ulogic; +signal p1_congr_cl45_act_d :std_ulogic; +signal p1_congr_cl45_act_q :std_ulogic; +signal congr_cl45_act :std_ulogic; +signal congr_cl45_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl45_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu45_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd45_wayA :std_ulogic; +signal p1_way_data_upd45_wayA :std_ulogic; +signal congr_cl45_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl45_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu45_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd45_wayB :std_ulogic; +signal p1_way_data_upd45_wayB :std_ulogic; +signal congr_cl45_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl45_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu45_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd45_wayC :std_ulogic; +signal p1_way_data_upd45_wayC :std_ulogic; +signal congr_cl45_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl45_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu45_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd45_wayD :std_ulogic; +signal p1_way_data_upd45_wayD :std_ulogic; +signal congr_cl45_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl45_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu45_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd45_wayE :std_ulogic; +signal p1_way_data_upd45_wayE :std_ulogic; +signal congr_cl45_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl45_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu45_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd45_wayF :std_ulogic; +signal p1_way_data_upd45_wayF :std_ulogic; +signal congr_cl45_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl45_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu45_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd45_wayG :std_ulogic; +signal p1_way_data_upd45_wayG :std_ulogic; +signal congr_cl45_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl45_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu45_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd45_wayH :std_ulogic; +signal p1_way_data_upd45_wayH :std_ulogic; +signal p0_congr_cl46_m :std_ulogic; +signal p1_congr_cl46_m :std_ulogic; +signal p0_congr_cl46_act_d :std_ulogic; +signal p0_congr_cl46_act_q :std_ulogic; +signal p1_congr_cl46_act_d :std_ulogic; +signal p1_congr_cl46_act_q :std_ulogic; +signal congr_cl46_act :std_ulogic; +signal congr_cl46_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl46_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu46_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd46_wayA :std_ulogic; +signal p1_way_data_upd46_wayA :std_ulogic; +signal congr_cl46_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl46_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu46_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd46_wayB :std_ulogic; +signal p1_way_data_upd46_wayB :std_ulogic; +signal congr_cl46_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl46_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu46_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd46_wayC :std_ulogic; +signal p1_way_data_upd46_wayC :std_ulogic; +signal congr_cl46_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl46_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu46_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd46_wayD :std_ulogic; +signal p1_way_data_upd46_wayD :std_ulogic; +signal congr_cl46_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl46_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu46_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd46_wayE :std_ulogic; +signal p1_way_data_upd46_wayE :std_ulogic; +signal congr_cl46_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl46_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu46_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd46_wayF :std_ulogic; +signal p1_way_data_upd46_wayF :std_ulogic; +signal congr_cl46_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl46_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu46_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd46_wayG :std_ulogic; +signal p1_way_data_upd46_wayG :std_ulogic; +signal congr_cl46_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl46_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu46_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd46_wayH :std_ulogic; +signal p1_way_data_upd46_wayH :std_ulogic; +signal p0_congr_cl47_m :std_ulogic; +signal p1_congr_cl47_m :std_ulogic; +signal p0_congr_cl47_act_d :std_ulogic; +signal p0_congr_cl47_act_q :std_ulogic; +signal p1_congr_cl47_act_d :std_ulogic; +signal p1_congr_cl47_act_q :std_ulogic; +signal congr_cl47_act :std_ulogic; +signal congr_cl47_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl47_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu47_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd47_wayA :std_ulogic; +signal p1_way_data_upd47_wayA :std_ulogic; +signal congr_cl47_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl47_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu47_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd47_wayB :std_ulogic; +signal p1_way_data_upd47_wayB :std_ulogic; +signal congr_cl47_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl47_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu47_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd47_wayC :std_ulogic; +signal p1_way_data_upd47_wayC :std_ulogic; +signal congr_cl47_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl47_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu47_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd47_wayD :std_ulogic; +signal p1_way_data_upd47_wayD :std_ulogic; +signal congr_cl47_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl47_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu47_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd47_wayE :std_ulogic; +signal p1_way_data_upd47_wayE :std_ulogic; +signal congr_cl47_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl47_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu47_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd47_wayF :std_ulogic; +signal p1_way_data_upd47_wayF :std_ulogic; +signal congr_cl47_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl47_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu47_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd47_wayG :std_ulogic; +signal p1_way_data_upd47_wayG :std_ulogic; +signal congr_cl47_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl47_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu47_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd47_wayH :std_ulogic; +signal p1_way_data_upd47_wayH :std_ulogic; +signal p0_congr_cl48_m :std_ulogic; +signal p1_congr_cl48_m :std_ulogic; +signal p0_congr_cl48_act_d :std_ulogic; +signal p0_congr_cl48_act_q :std_ulogic; +signal p1_congr_cl48_act_d :std_ulogic; +signal p1_congr_cl48_act_q :std_ulogic; +signal congr_cl48_act :std_ulogic; +signal congr_cl48_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl48_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu48_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd48_wayA :std_ulogic; +signal p1_way_data_upd48_wayA :std_ulogic; +signal congr_cl48_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl48_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu48_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd48_wayB :std_ulogic; +signal p1_way_data_upd48_wayB :std_ulogic; +signal congr_cl48_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl48_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu48_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd48_wayC :std_ulogic; +signal p1_way_data_upd48_wayC :std_ulogic; +signal congr_cl48_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl48_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu48_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd48_wayD :std_ulogic; +signal p1_way_data_upd48_wayD :std_ulogic; +signal congr_cl48_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl48_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu48_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd48_wayE :std_ulogic; +signal p1_way_data_upd48_wayE :std_ulogic; +signal congr_cl48_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl48_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu48_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd48_wayF :std_ulogic; +signal p1_way_data_upd48_wayF :std_ulogic; +signal congr_cl48_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl48_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu48_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd48_wayG :std_ulogic; +signal p1_way_data_upd48_wayG :std_ulogic; +signal congr_cl48_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl48_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu48_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd48_wayH :std_ulogic; +signal p1_way_data_upd48_wayH :std_ulogic; +signal p0_congr_cl49_m :std_ulogic; +signal p1_congr_cl49_m :std_ulogic; +signal p0_congr_cl49_act_d :std_ulogic; +signal p0_congr_cl49_act_q :std_ulogic; +signal p1_congr_cl49_act_d :std_ulogic; +signal p1_congr_cl49_act_q :std_ulogic; +signal congr_cl49_act :std_ulogic; +signal congr_cl49_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl49_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu49_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd49_wayA :std_ulogic; +signal p1_way_data_upd49_wayA :std_ulogic; +signal congr_cl49_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl49_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu49_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd49_wayB :std_ulogic; +signal p1_way_data_upd49_wayB :std_ulogic; +signal congr_cl49_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl49_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu49_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd49_wayC :std_ulogic; +signal p1_way_data_upd49_wayC :std_ulogic; +signal congr_cl49_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl49_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu49_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd49_wayD :std_ulogic; +signal p1_way_data_upd49_wayD :std_ulogic; +signal congr_cl49_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl49_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu49_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd49_wayE :std_ulogic; +signal p1_way_data_upd49_wayE :std_ulogic; +signal congr_cl49_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl49_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu49_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd49_wayF :std_ulogic; +signal p1_way_data_upd49_wayF :std_ulogic; +signal congr_cl49_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl49_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu49_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd49_wayG :std_ulogic; +signal p1_way_data_upd49_wayG :std_ulogic; +signal congr_cl49_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl49_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu49_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd49_wayH :std_ulogic; +signal p1_way_data_upd49_wayH :std_ulogic; +signal p0_congr_cl50_m :std_ulogic; +signal p1_congr_cl50_m :std_ulogic; +signal p0_congr_cl50_act_d :std_ulogic; +signal p0_congr_cl50_act_q :std_ulogic; +signal p1_congr_cl50_act_d :std_ulogic; +signal p1_congr_cl50_act_q :std_ulogic; +signal congr_cl50_act :std_ulogic; +signal congr_cl50_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl50_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu50_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd50_wayA :std_ulogic; +signal p1_way_data_upd50_wayA :std_ulogic; +signal congr_cl50_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl50_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu50_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd50_wayB :std_ulogic; +signal p1_way_data_upd50_wayB :std_ulogic; +signal congr_cl50_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl50_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu50_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd50_wayC :std_ulogic; +signal p1_way_data_upd50_wayC :std_ulogic; +signal congr_cl50_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl50_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu50_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd50_wayD :std_ulogic; +signal p1_way_data_upd50_wayD :std_ulogic; +signal congr_cl50_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl50_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu50_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd50_wayE :std_ulogic; +signal p1_way_data_upd50_wayE :std_ulogic; +signal congr_cl50_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl50_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu50_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd50_wayF :std_ulogic; +signal p1_way_data_upd50_wayF :std_ulogic; +signal congr_cl50_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl50_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu50_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd50_wayG :std_ulogic; +signal p1_way_data_upd50_wayG :std_ulogic; +signal congr_cl50_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl50_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu50_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd50_wayH :std_ulogic; +signal p1_way_data_upd50_wayH :std_ulogic; +signal p0_congr_cl51_m :std_ulogic; +signal p1_congr_cl51_m :std_ulogic; +signal p0_congr_cl51_act_d :std_ulogic; +signal p0_congr_cl51_act_q :std_ulogic; +signal p1_congr_cl51_act_d :std_ulogic; +signal p1_congr_cl51_act_q :std_ulogic; +signal congr_cl51_act :std_ulogic; +signal congr_cl51_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl51_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu51_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd51_wayA :std_ulogic; +signal p1_way_data_upd51_wayA :std_ulogic; +signal congr_cl51_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl51_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu51_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd51_wayB :std_ulogic; +signal p1_way_data_upd51_wayB :std_ulogic; +signal congr_cl51_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl51_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu51_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd51_wayC :std_ulogic; +signal p1_way_data_upd51_wayC :std_ulogic; +signal congr_cl51_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl51_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu51_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd51_wayD :std_ulogic; +signal p1_way_data_upd51_wayD :std_ulogic; +signal congr_cl51_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl51_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu51_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd51_wayE :std_ulogic; +signal p1_way_data_upd51_wayE :std_ulogic; +signal congr_cl51_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl51_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu51_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd51_wayF :std_ulogic; +signal p1_way_data_upd51_wayF :std_ulogic; +signal congr_cl51_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl51_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu51_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd51_wayG :std_ulogic; +signal p1_way_data_upd51_wayG :std_ulogic; +signal congr_cl51_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl51_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu51_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd51_wayH :std_ulogic; +signal p1_way_data_upd51_wayH :std_ulogic; +signal p0_congr_cl52_m :std_ulogic; +signal p1_congr_cl52_m :std_ulogic; +signal p0_congr_cl52_act_d :std_ulogic; +signal p0_congr_cl52_act_q :std_ulogic; +signal p1_congr_cl52_act_d :std_ulogic; +signal p1_congr_cl52_act_q :std_ulogic; +signal congr_cl52_act :std_ulogic; +signal congr_cl52_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl52_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu52_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd52_wayA :std_ulogic; +signal p1_way_data_upd52_wayA :std_ulogic; +signal congr_cl52_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl52_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu52_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd52_wayB :std_ulogic; +signal p1_way_data_upd52_wayB :std_ulogic; +signal congr_cl52_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl52_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu52_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd52_wayC :std_ulogic; +signal p1_way_data_upd52_wayC :std_ulogic; +signal congr_cl52_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl52_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu52_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd52_wayD :std_ulogic; +signal p1_way_data_upd52_wayD :std_ulogic; +signal congr_cl52_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl52_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu52_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd52_wayE :std_ulogic; +signal p1_way_data_upd52_wayE :std_ulogic; +signal congr_cl52_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl52_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu52_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd52_wayF :std_ulogic; +signal p1_way_data_upd52_wayF :std_ulogic; +signal congr_cl52_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl52_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu52_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd52_wayG :std_ulogic; +signal p1_way_data_upd52_wayG :std_ulogic; +signal congr_cl52_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl52_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu52_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd52_wayH :std_ulogic; +signal p1_way_data_upd52_wayH :std_ulogic; +signal p0_congr_cl53_m :std_ulogic; +signal p1_congr_cl53_m :std_ulogic; +signal p0_congr_cl53_act_d :std_ulogic; +signal p0_congr_cl53_act_q :std_ulogic; +signal p1_congr_cl53_act_d :std_ulogic; +signal p1_congr_cl53_act_q :std_ulogic; +signal congr_cl53_act :std_ulogic; +signal congr_cl53_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl53_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu53_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd53_wayA :std_ulogic; +signal p1_way_data_upd53_wayA :std_ulogic; +signal congr_cl53_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl53_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu53_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd53_wayB :std_ulogic; +signal p1_way_data_upd53_wayB :std_ulogic; +signal congr_cl53_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl53_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu53_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd53_wayC :std_ulogic; +signal p1_way_data_upd53_wayC :std_ulogic; +signal congr_cl53_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl53_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu53_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd53_wayD :std_ulogic; +signal p1_way_data_upd53_wayD :std_ulogic; +signal congr_cl53_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl53_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu53_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd53_wayE :std_ulogic; +signal p1_way_data_upd53_wayE :std_ulogic; +signal congr_cl53_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl53_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu53_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd53_wayF :std_ulogic; +signal p1_way_data_upd53_wayF :std_ulogic; +signal congr_cl53_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl53_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu53_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd53_wayG :std_ulogic; +signal p1_way_data_upd53_wayG :std_ulogic; +signal congr_cl53_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl53_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu53_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd53_wayH :std_ulogic; +signal p1_way_data_upd53_wayH :std_ulogic; +signal p0_congr_cl54_m :std_ulogic; +signal p1_congr_cl54_m :std_ulogic; +signal p0_congr_cl54_act_d :std_ulogic; +signal p0_congr_cl54_act_q :std_ulogic; +signal p1_congr_cl54_act_d :std_ulogic; +signal p1_congr_cl54_act_q :std_ulogic; +signal congr_cl54_act :std_ulogic; +signal congr_cl54_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl54_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu54_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd54_wayA :std_ulogic; +signal p1_way_data_upd54_wayA :std_ulogic; +signal congr_cl54_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl54_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu54_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd54_wayB :std_ulogic; +signal p1_way_data_upd54_wayB :std_ulogic; +signal congr_cl54_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl54_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu54_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd54_wayC :std_ulogic; +signal p1_way_data_upd54_wayC :std_ulogic; +signal congr_cl54_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl54_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu54_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd54_wayD :std_ulogic; +signal p1_way_data_upd54_wayD :std_ulogic; +signal congr_cl54_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl54_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu54_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd54_wayE :std_ulogic; +signal p1_way_data_upd54_wayE :std_ulogic; +signal congr_cl54_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl54_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu54_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd54_wayF :std_ulogic; +signal p1_way_data_upd54_wayF :std_ulogic; +signal congr_cl54_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl54_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu54_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd54_wayG :std_ulogic; +signal p1_way_data_upd54_wayG :std_ulogic; +signal congr_cl54_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl54_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu54_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd54_wayH :std_ulogic; +signal p1_way_data_upd54_wayH :std_ulogic; +signal p0_congr_cl55_m :std_ulogic; +signal p1_congr_cl55_m :std_ulogic; +signal p0_congr_cl55_act_d :std_ulogic; +signal p0_congr_cl55_act_q :std_ulogic; +signal p1_congr_cl55_act_d :std_ulogic; +signal p1_congr_cl55_act_q :std_ulogic; +signal congr_cl55_act :std_ulogic; +signal congr_cl55_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl55_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu55_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd55_wayA :std_ulogic; +signal p1_way_data_upd55_wayA :std_ulogic; +signal congr_cl55_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl55_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu55_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd55_wayB :std_ulogic; +signal p1_way_data_upd55_wayB :std_ulogic; +signal congr_cl55_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl55_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu55_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd55_wayC :std_ulogic; +signal p1_way_data_upd55_wayC :std_ulogic; +signal congr_cl55_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl55_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu55_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd55_wayD :std_ulogic; +signal p1_way_data_upd55_wayD :std_ulogic; +signal congr_cl55_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl55_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu55_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd55_wayE :std_ulogic; +signal p1_way_data_upd55_wayE :std_ulogic; +signal congr_cl55_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl55_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu55_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd55_wayF :std_ulogic; +signal p1_way_data_upd55_wayF :std_ulogic; +signal congr_cl55_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl55_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu55_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd55_wayG :std_ulogic; +signal p1_way_data_upd55_wayG :std_ulogic; +signal congr_cl55_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl55_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu55_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd55_wayH :std_ulogic; +signal p1_way_data_upd55_wayH :std_ulogic; +signal p0_congr_cl56_m :std_ulogic; +signal p1_congr_cl56_m :std_ulogic; +signal p0_congr_cl56_act_d :std_ulogic; +signal p0_congr_cl56_act_q :std_ulogic; +signal p1_congr_cl56_act_d :std_ulogic; +signal p1_congr_cl56_act_q :std_ulogic; +signal congr_cl56_act :std_ulogic; +signal congr_cl56_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl56_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu56_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd56_wayA :std_ulogic; +signal p1_way_data_upd56_wayA :std_ulogic; +signal congr_cl56_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl56_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu56_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd56_wayB :std_ulogic; +signal p1_way_data_upd56_wayB :std_ulogic; +signal congr_cl56_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl56_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu56_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd56_wayC :std_ulogic; +signal p1_way_data_upd56_wayC :std_ulogic; +signal congr_cl56_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl56_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu56_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd56_wayD :std_ulogic; +signal p1_way_data_upd56_wayD :std_ulogic; +signal congr_cl56_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl56_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu56_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd56_wayE :std_ulogic; +signal p1_way_data_upd56_wayE :std_ulogic; +signal congr_cl56_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl56_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu56_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd56_wayF :std_ulogic; +signal p1_way_data_upd56_wayF :std_ulogic; +signal congr_cl56_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl56_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu56_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd56_wayG :std_ulogic; +signal p1_way_data_upd56_wayG :std_ulogic; +signal congr_cl56_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl56_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu56_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd56_wayH :std_ulogic; +signal p1_way_data_upd56_wayH :std_ulogic; +signal p0_congr_cl57_m :std_ulogic; +signal p1_congr_cl57_m :std_ulogic; +signal p0_congr_cl57_act_d :std_ulogic; +signal p0_congr_cl57_act_q :std_ulogic; +signal p1_congr_cl57_act_d :std_ulogic; +signal p1_congr_cl57_act_q :std_ulogic; +signal congr_cl57_act :std_ulogic; +signal congr_cl57_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl57_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu57_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd57_wayA :std_ulogic; +signal p1_way_data_upd57_wayA :std_ulogic; +signal congr_cl57_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl57_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu57_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd57_wayB :std_ulogic; +signal p1_way_data_upd57_wayB :std_ulogic; +signal congr_cl57_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl57_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu57_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd57_wayC :std_ulogic; +signal p1_way_data_upd57_wayC :std_ulogic; +signal congr_cl57_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl57_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu57_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd57_wayD :std_ulogic; +signal p1_way_data_upd57_wayD :std_ulogic; +signal congr_cl57_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl57_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu57_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd57_wayE :std_ulogic; +signal p1_way_data_upd57_wayE :std_ulogic; +signal congr_cl57_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl57_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu57_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd57_wayF :std_ulogic; +signal p1_way_data_upd57_wayF :std_ulogic; +signal congr_cl57_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl57_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu57_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd57_wayG :std_ulogic; +signal p1_way_data_upd57_wayG :std_ulogic; +signal congr_cl57_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl57_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu57_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd57_wayH :std_ulogic; +signal p1_way_data_upd57_wayH :std_ulogic; +signal p0_congr_cl58_m :std_ulogic; +signal p1_congr_cl58_m :std_ulogic; +signal p0_congr_cl58_act_d :std_ulogic; +signal p0_congr_cl58_act_q :std_ulogic; +signal p1_congr_cl58_act_d :std_ulogic; +signal p1_congr_cl58_act_q :std_ulogic; +signal congr_cl58_act :std_ulogic; +signal congr_cl58_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl58_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu58_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd58_wayA :std_ulogic; +signal p1_way_data_upd58_wayA :std_ulogic; +signal congr_cl58_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl58_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu58_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd58_wayB :std_ulogic; +signal p1_way_data_upd58_wayB :std_ulogic; +signal congr_cl58_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl58_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu58_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd58_wayC :std_ulogic; +signal p1_way_data_upd58_wayC :std_ulogic; +signal congr_cl58_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl58_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu58_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd58_wayD :std_ulogic; +signal p1_way_data_upd58_wayD :std_ulogic; +signal congr_cl58_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl58_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu58_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd58_wayE :std_ulogic; +signal p1_way_data_upd58_wayE :std_ulogic; +signal congr_cl58_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl58_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu58_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd58_wayF :std_ulogic; +signal p1_way_data_upd58_wayF :std_ulogic; +signal congr_cl58_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl58_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu58_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd58_wayG :std_ulogic; +signal p1_way_data_upd58_wayG :std_ulogic; +signal congr_cl58_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl58_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu58_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd58_wayH :std_ulogic; +signal p1_way_data_upd58_wayH :std_ulogic; +signal p0_congr_cl59_m :std_ulogic; +signal p1_congr_cl59_m :std_ulogic; +signal p0_congr_cl59_act_d :std_ulogic; +signal p0_congr_cl59_act_q :std_ulogic; +signal p1_congr_cl59_act_d :std_ulogic; +signal p1_congr_cl59_act_q :std_ulogic; +signal congr_cl59_act :std_ulogic; +signal congr_cl59_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl59_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu59_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd59_wayA :std_ulogic; +signal p1_way_data_upd59_wayA :std_ulogic; +signal congr_cl59_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl59_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu59_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd59_wayB :std_ulogic; +signal p1_way_data_upd59_wayB :std_ulogic; +signal congr_cl59_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl59_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu59_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd59_wayC :std_ulogic; +signal p1_way_data_upd59_wayC :std_ulogic; +signal congr_cl59_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl59_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu59_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd59_wayD :std_ulogic; +signal p1_way_data_upd59_wayD :std_ulogic; +signal congr_cl59_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl59_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu59_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd59_wayE :std_ulogic; +signal p1_way_data_upd59_wayE :std_ulogic; +signal congr_cl59_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl59_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu59_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd59_wayF :std_ulogic; +signal p1_way_data_upd59_wayF :std_ulogic; +signal congr_cl59_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl59_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu59_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd59_wayG :std_ulogic; +signal p1_way_data_upd59_wayG :std_ulogic; +signal congr_cl59_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl59_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu59_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd59_wayH :std_ulogic; +signal p1_way_data_upd59_wayH :std_ulogic; +signal p0_congr_cl60_m :std_ulogic; +signal p1_congr_cl60_m :std_ulogic; +signal p0_congr_cl60_act_d :std_ulogic; +signal p0_congr_cl60_act_q :std_ulogic; +signal p1_congr_cl60_act_d :std_ulogic; +signal p1_congr_cl60_act_q :std_ulogic; +signal congr_cl60_act :std_ulogic; +signal congr_cl60_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl60_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu60_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd60_wayA :std_ulogic; +signal p1_way_data_upd60_wayA :std_ulogic; +signal congr_cl60_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl60_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu60_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd60_wayB :std_ulogic; +signal p1_way_data_upd60_wayB :std_ulogic; +signal congr_cl60_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl60_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu60_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd60_wayC :std_ulogic; +signal p1_way_data_upd60_wayC :std_ulogic; +signal congr_cl60_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl60_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu60_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd60_wayD :std_ulogic; +signal p1_way_data_upd60_wayD :std_ulogic; +signal congr_cl60_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl60_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu60_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd60_wayE :std_ulogic; +signal p1_way_data_upd60_wayE :std_ulogic; +signal congr_cl60_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl60_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu60_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd60_wayF :std_ulogic; +signal p1_way_data_upd60_wayF :std_ulogic; +signal congr_cl60_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl60_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu60_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd60_wayG :std_ulogic; +signal p1_way_data_upd60_wayG :std_ulogic; +signal congr_cl60_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl60_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu60_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd60_wayH :std_ulogic; +signal p1_way_data_upd60_wayH :std_ulogic; +signal p0_congr_cl61_m :std_ulogic; +signal p1_congr_cl61_m :std_ulogic; +signal p0_congr_cl61_act_d :std_ulogic; +signal p0_congr_cl61_act_q :std_ulogic; +signal p1_congr_cl61_act_d :std_ulogic; +signal p1_congr_cl61_act_q :std_ulogic; +signal congr_cl61_act :std_ulogic; +signal congr_cl61_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl61_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu61_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd61_wayA :std_ulogic; +signal p1_way_data_upd61_wayA :std_ulogic; +signal congr_cl61_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl61_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu61_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd61_wayB :std_ulogic; +signal p1_way_data_upd61_wayB :std_ulogic; +signal congr_cl61_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl61_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu61_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd61_wayC :std_ulogic; +signal p1_way_data_upd61_wayC :std_ulogic; +signal congr_cl61_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl61_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu61_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd61_wayD :std_ulogic; +signal p1_way_data_upd61_wayD :std_ulogic; +signal congr_cl61_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl61_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu61_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd61_wayE :std_ulogic; +signal p1_way_data_upd61_wayE :std_ulogic; +signal congr_cl61_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl61_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu61_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd61_wayF :std_ulogic; +signal p1_way_data_upd61_wayF :std_ulogic; +signal congr_cl61_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl61_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu61_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd61_wayG :std_ulogic; +signal p1_way_data_upd61_wayG :std_ulogic; +signal congr_cl61_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl61_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu61_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd61_wayH :std_ulogic; +signal p1_way_data_upd61_wayH :std_ulogic; +signal p0_congr_cl62_m :std_ulogic; +signal p1_congr_cl62_m :std_ulogic; +signal p0_congr_cl62_act_d :std_ulogic; +signal p0_congr_cl62_act_q :std_ulogic; +signal p1_congr_cl62_act_d :std_ulogic; +signal p1_congr_cl62_act_q :std_ulogic; +signal congr_cl62_act :std_ulogic; +signal congr_cl62_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl62_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu62_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd62_wayA :std_ulogic; +signal p1_way_data_upd62_wayA :std_ulogic; +signal congr_cl62_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl62_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu62_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd62_wayB :std_ulogic; +signal p1_way_data_upd62_wayB :std_ulogic; +signal congr_cl62_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl62_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu62_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd62_wayC :std_ulogic; +signal p1_way_data_upd62_wayC :std_ulogic; +signal congr_cl62_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl62_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu62_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd62_wayD :std_ulogic; +signal p1_way_data_upd62_wayD :std_ulogic; +signal congr_cl62_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl62_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu62_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd62_wayE :std_ulogic; +signal p1_way_data_upd62_wayE :std_ulogic; +signal congr_cl62_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl62_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu62_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd62_wayF :std_ulogic; +signal p1_way_data_upd62_wayF :std_ulogic; +signal congr_cl62_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl62_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu62_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd62_wayG :std_ulogic; +signal p1_way_data_upd62_wayG :std_ulogic; +signal congr_cl62_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl62_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu62_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd62_wayH :std_ulogic; +signal p1_way_data_upd62_wayH :std_ulogic; +signal p0_congr_cl63_m :std_ulogic; +signal p1_congr_cl63_m :std_ulogic; +signal p0_congr_cl63_act_d :std_ulogic; +signal p0_congr_cl63_act_q :std_ulogic; +signal p1_congr_cl63_act_d :std_ulogic; +signal p1_congr_cl63_act_q :std_ulogic; +signal congr_cl63_act :std_ulogic; +signal congr_cl63_wA_d :std_ulogic_vector(0 to 5); +signal congr_cl63_wA_q :std_ulogic_vector(0 to 5); +signal rel_bixu63_wayA_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd63_wayA :std_ulogic; +signal p1_way_data_upd63_wayA :std_ulogic; +signal congr_cl63_wB_d :std_ulogic_vector(0 to 5); +signal congr_cl63_wB_q :std_ulogic_vector(0 to 5); +signal rel_bixu63_wayB_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd63_wayB :std_ulogic; +signal p1_way_data_upd63_wayB :std_ulogic; +signal congr_cl63_wC_d :std_ulogic_vector(0 to 5); +signal congr_cl63_wC_q :std_ulogic_vector(0 to 5); +signal rel_bixu63_wayC_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd63_wayC :std_ulogic; +signal p1_way_data_upd63_wayC :std_ulogic; +signal congr_cl63_wD_d :std_ulogic_vector(0 to 5); +signal congr_cl63_wD_q :std_ulogic_vector(0 to 5); +signal rel_bixu63_wayD_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd63_wayD :std_ulogic; +signal p1_way_data_upd63_wayD :std_ulogic; +signal congr_cl63_wE_d :std_ulogic_vector(0 to 5); +signal congr_cl63_wE_q :std_ulogic_vector(0 to 5); +signal rel_bixu63_wayE_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd63_wayE :std_ulogic; +signal p1_way_data_upd63_wayE :std_ulogic; +signal congr_cl63_wF_d :std_ulogic_vector(0 to 5); +signal congr_cl63_wF_q :std_ulogic_vector(0 to 5); +signal rel_bixu63_wayF_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd63_wayF :std_ulogic; +signal p1_way_data_upd63_wayF :std_ulogic; +signal congr_cl63_wG_d :std_ulogic_vector(0 to 5); +signal congr_cl63_wG_q :std_ulogic_vector(0 to 5); +signal rel_bixu63_wayG_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd63_wayG :std_ulogic; +signal p1_way_data_upd63_wayG :std_ulogic; +signal congr_cl63_wH_d :std_ulogic_vector(0 to 5); +signal congr_cl63_wH_q :std_ulogic_vector(0 to 5); +signal rel_bixu63_wayH_upd :std_ulogic_vector(0 to 1); +signal p0_way_data_upd63_wayH :std_ulogic; +signal p1_way_data_upd63_wayH :std_ulogic; +signal tagA_hit :std_ulogic; +signal tagA_hit_b :std_ulogic; +signal arr_wayA_val :std_ulogic_vector(0 to 5); +signal p0_arr_wayA_rd :std_ulogic_vector(0 to 5); +signal flush_wayA_d :std_ulogic_vector(0 to 5); +signal flush_wayA_q :std_ulogic_vector(0 to 5); +signal rel_wayA_clr :std_ulogic; +signal rel_wayA_set :std_ulogic; +signal rel_par_wA_clr :std_ulogic; +signal wayA_val :std_ulogic_vector(0 to 5); +signal wayA_val_b_q :std_ulogic_vector(0 to 5); +signal wayA_val_b1 :std_ulogic; +signal congr_cl_ex2_wayA_byp :std_ulogic_vector(1 to 7); +signal congr_cl_ex2_wayA_sel :std_ulogic_vector(2 to 7); +signal rel_arr_wayA_val :std_ulogic_vector(0 to 5); +signal p1_arr_wayA_rd :std_ulogic_vector(0 to 5); +signal rel_wayA_val_b_q :std_ulogic_vector(0 to 5); +signal rel_wayA_val :std_ulogic_vector(0 to 5); +signal congr_cl_rel13_wayA_byp :std_ulogic_vector(1 to 7); +signal congr_cl_rel13_wayA_sel :std_ulogic_vector(2 to 7); +signal reload_wayA_d :std_ulogic_vector(0 to 5); +signal reload_wayA_q :std_ulogic_vector(0 to 5); +signal reload_wayA_data_d :std_ulogic_vector(0 to 5); +signal reload_wayA_data_q :std_ulogic_vector(0 to 5); +signal reload_wayA_data2_d :std_ulogic_vector(0 to 5); +signal reload_wayA_data2_q :std_ulogic_vector(0 to 5); +signal reload_wayA_upd_d :std_ulogic; +signal reload_wayA_upd_q :std_ulogic; +signal reload_wayA_clr :std_ulogic; +signal reload_wayA_upd2_d :std_ulogic; +signal reload_wayA_upd2_q :std_ulogic; +signal reload_wayA_upd3_d :std_ulogic; +signal reload_wayA_upd3_q :std_ulogic; +signal reload_wayA :std_ulogic_vector(0 to 5); +signal binv_wayA_upd_d :std_ulogic; +signal binv_wayA_upd_q :std_ulogic; +signal binv_wayA_upd1 :std_ulogic; +signal binv_wayA_upd2_d :std_ulogic; +signal binv_wayA_upd2_q :std_ulogic; +signal binv_wayA_upd3_d :std_ulogic; +signal binv_wayA_upd3_q :std_ulogic; +signal flush_wayA_data1 :std_ulogic_vector(0 to 5); +signal flush_wayA_data_d :std_ulogic_vector(0 to 5); +signal flush_wayA_data_q :std_ulogic_vector(0 to 5); +signal flush_wayA_data2_d :std_ulogic_vector(0 to 5); +signal flush_wayA_data2_q :std_ulogic_vector(0 to 5); +signal xu_op_hit_wayA_b :std_ulogic; +signal xu_op_hit_wayA :std_ulogic; +signal xu_op_hit_wayA_dly_b :std_ulogic; +signal clr_val_wayA :std_ulogic; +signal upd_lck_wayA :std_ulogic_vector(0 to 1); +signal inval_clr_lck_wA_d :std_ulogic; +signal inval_clr_lck_wA_q :std_ulogic; +signal perr_way_det_wayA :std_ulogic; +signal perr_wayA_watch_lost :std_ulogic_vector(0 to 3); +signal wayA_watch_value :std_ulogic; +signal ex4_lost_wayA :std_ulogic_vector(0 to 3); +signal ex3_xuop_lost_watch_wayA :std_ulogic; +signal ex3_xuop_wayA_upd :std_ulogic; +signal ex4_xuop_wayA_upd_d :std_ulogic; +signal ex4_xuop_wayA_upd_q :std_ulogic; +signal ex4_wayA_val_d :std_ulogic_vector(0 to 5); +signal ex4_wayA_val_q :std_ulogic_vector(0 to 5); +signal rel_wayA_val_stg_d :std_ulogic_vector(0 to 5); +signal rel_wayA_val_stg_q :std_ulogic_vector(0 to 5); +signal ex5_xuop_wayA_upd_d :std_ulogic; +signal ex5_xuop_wayA_upd_q :std_ulogic; +signal congr_cl_ex3_upd_wayA :std_ulogic; +signal congr_cl_ex4_upd_wayA :std_ulogic; +signal congr_cl_ex5_upd_wayA :std_ulogic; +signal congr_cl_m_upd_wayA_d :std_ulogic; +signal congr_cl_m_upd_wayA_q :std_ulogic; +signal ex3_cClass_wayA_hit :std_ulogic; +signal wayA_later_stg_pri :std_ulogic_vector(0 to 5); +signal wayA_early_stg_pri :std_ulogic_vector(0 to 5); +signal wayA_stg_val :std_ulogic_vector(0 to 5); +signal wayA_stg_val_b :std_ulogic_vector(0 to 5); +signal rel_wayA_later_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayA_early_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayA_stg_val :std_ulogic_vector(0 to 5); +signal rel_wayA_stg_val_b :std_ulogic_vector(0 to 5); +signal wayA_early_sel :std_ulogic; +signal wayA_late_sel :std_ulogic; +signal rel_wayA_early_sel :std_ulogic; +signal rel_wayA_late_sel :std_ulogic; +signal ex3_wayA_hit :std_ulogic; +signal rel_lost_watch_wayA_evict :std_ulogic_vector(0 to 3); +signal ex3_wayA_fxubyp_val_d :std_ulogic; +signal ex3_wayA_fxubyp_val_q :std_ulogic; +signal ex4_wayA_fxubyp_val_d :std_ulogic; +signal ex4_wayA_fxubyp_val_q :std_ulogic; +signal ex3_wayA_relbyp_val_d :std_ulogic; +signal ex3_wayA_relbyp_val_q :std_ulogic; +signal ex4_wayA_relbyp_val_d :std_ulogic; +signal ex4_wayA_relbyp_val_q :std_ulogic; +signal ex4_wayA_byp_sel :std_ulogic_vector(0 to 1); +signal rel24_wayA_fxubyp_val_d :std_ulogic; +signal rel24_wayA_fxubyp_val_q :std_ulogic; +signal rel24_wayA_relbyp_val_d :std_ulogic; +signal rel24_wayA_relbyp_val_q :std_ulogic; +signal rel24_wayA_byp_sel :std_ulogic_vector(0 to 1); +signal tagB_hit :std_ulogic; +signal tagB_hit_b :std_ulogic; +signal arr_wayB_val :std_ulogic_vector(0 to 5); +signal p0_arr_wayB_rd :std_ulogic_vector(0 to 5); +signal flush_wayB_d :std_ulogic_vector(0 to 5); +signal flush_wayB_q :std_ulogic_vector(0 to 5); +signal rel_wayB_clr :std_ulogic; +signal rel_wayB_set :std_ulogic; +signal rel_par_wB_clr :std_ulogic; +signal wayB_val :std_ulogic_vector(0 to 5); +signal wayB_val_b_q :std_ulogic_vector(0 to 5); +signal wayB_val_b1 :std_ulogic; +signal congr_cl_ex2_wayB_byp :std_ulogic_vector(1 to 7); +signal congr_cl_ex2_wayB_sel :std_ulogic_vector(2 to 7); +signal rel_arr_wayB_val :std_ulogic_vector(0 to 5); +signal p1_arr_wayB_rd :std_ulogic_vector(0 to 5); +signal rel_wayB_val_b_q :std_ulogic_vector(0 to 5); +signal rel_wayB_val :std_ulogic_vector(0 to 5); +signal congr_cl_rel13_wayB_byp :std_ulogic_vector(1 to 7); +signal congr_cl_rel13_wayB_sel :std_ulogic_vector(2 to 7); +signal reload_wayB_d :std_ulogic_vector(0 to 5); +signal reload_wayB_q :std_ulogic_vector(0 to 5); +signal reload_wayB_data_d :std_ulogic_vector(0 to 5); +signal reload_wayB_data_q :std_ulogic_vector(0 to 5); +signal reload_wayB_data2_d :std_ulogic_vector(0 to 5); +signal reload_wayB_data2_q :std_ulogic_vector(0 to 5); +signal reload_wayB_upd_d :std_ulogic; +signal reload_wayB_upd_q :std_ulogic; +signal reload_wayB_clr :std_ulogic; +signal reload_wayB_upd2_d :std_ulogic; +signal reload_wayB_upd2_q :std_ulogic; +signal reload_wayB_upd3_d :std_ulogic; +signal reload_wayB_upd3_q :std_ulogic; +signal reload_wayB :std_ulogic_vector(0 to 5); +signal binv_wayB_upd_d :std_ulogic; +signal binv_wayB_upd_q :std_ulogic; +signal binv_wayB_upd1 :std_ulogic; +signal binv_wayB_upd2_d :std_ulogic; +signal binv_wayB_upd2_q :std_ulogic; +signal binv_wayB_upd3_d :std_ulogic; +signal binv_wayB_upd3_q :std_ulogic; +signal flush_wayB_data1 :std_ulogic_vector(0 to 5); +signal flush_wayB_data_d :std_ulogic_vector(0 to 5); +signal flush_wayB_data_q :std_ulogic_vector(0 to 5); +signal flush_wayB_data2_d :std_ulogic_vector(0 to 5); +signal flush_wayB_data2_q :std_ulogic_vector(0 to 5); +signal xu_op_hit_wayB_b :std_ulogic; +signal xu_op_hit_wayB :std_ulogic; +signal xu_op_hit_wayB_dly_b :std_ulogic; +signal clr_val_wayB :std_ulogic; +signal upd_lck_wayB :std_ulogic_vector(0 to 1); +signal inval_clr_lck_wB_d :std_ulogic; +signal inval_clr_lck_wB_q :std_ulogic; +signal perr_way_det_wayB :std_ulogic; +signal perr_wayB_watch_lost :std_ulogic_vector(0 to 3); +signal wayB_watch_value :std_ulogic; +signal ex4_lost_wayB :std_ulogic_vector(0 to 3); +signal ex3_xuop_lost_watch_wayB :std_ulogic; +signal ex3_xuop_wayB_upd :std_ulogic; +signal ex4_xuop_wayB_upd_d :std_ulogic; +signal ex4_xuop_wayB_upd_q :std_ulogic; +signal ex4_wayB_val_d :std_ulogic_vector(0 to 5); +signal ex4_wayB_val_q :std_ulogic_vector(0 to 5); +signal rel_wayB_val_stg_d :std_ulogic_vector(0 to 5); +signal rel_wayB_val_stg_q :std_ulogic_vector(0 to 5); +signal ex5_xuop_wayB_upd_d :std_ulogic; +signal ex5_xuop_wayB_upd_q :std_ulogic; +signal congr_cl_ex3_upd_wayB :std_ulogic; +signal congr_cl_ex4_upd_wayB :std_ulogic; +signal congr_cl_ex5_upd_wayB :std_ulogic; +signal congr_cl_m_upd_wayB_d :std_ulogic; +signal congr_cl_m_upd_wayB_q :std_ulogic; +signal ex3_cClass_wayB_hit :std_ulogic; +signal wayB_later_stg_pri :std_ulogic_vector(0 to 5); +signal wayB_early_stg_pri :std_ulogic_vector(0 to 5); +signal wayB_stg_val :std_ulogic_vector(0 to 5); +signal wayB_stg_val_b :std_ulogic_vector(0 to 5); +signal rel_wayB_later_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayB_early_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayB_stg_val :std_ulogic_vector(0 to 5); +signal rel_wayB_stg_val_b :std_ulogic_vector(0 to 5); +signal wayB_early_sel :std_ulogic; +signal wayB_late_sel :std_ulogic; +signal rel_wayB_early_sel :std_ulogic; +signal rel_wayB_late_sel :std_ulogic; +signal ex3_wayB_hit :std_ulogic; +signal rel_lost_watch_wayB_evict :std_ulogic_vector(0 to 3); +signal ex3_wayB_fxubyp_val_d :std_ulogic; +signal ex3_wayB_fxubyp_val_q :std_ulogic; +signal ex4_wayB_fxubyp_val_d :std_ulogic; +signal ex4_wayB_fxubyp_val_q :std_ulogic; +signal ex3_wayB_relbyp_val_d :std_ulogic; +signal ex3_wayB_relbyp_val_q :std_ulogic; +signal ex4_wayB_relbyp_val_d :std_ulogic; +signal ex4_wayB_relbyp_val_q :std_ulogic; +signal ex4_wayB_byp_sel :std_ulogic_vector(0 to 1); +signal rel24_wayB_fxubyp_val_d :std_ulogic; +signal rel24_wayB_fxubyp_val_q :std_ulogic; +signal rel24_wayB_relbyp_val_d :std_ulogic; +signal rel24_wayB_relbyp_val_q :std_ulogic; +signal rel24_wayB_byp_sel :std_ulogic_vector(0 to 1); +signal tagC_hit :std_ulogic; +signal tagC_hit_b :std_ulogic; +signal arr_wayC_val :std_ulogic_vector(0 to 5); +signal p0_arr_wayC_rd :std_ulogic_vector(0 to 5); +signal flush_wayC_d :std_ulogic_vector(0 to 5); +signal flush_wayC_q :std_ulogic_vector(0 to 5); +signal rel_wayC_clr :std_ulogic; +signal rel_wayC_set :std_ulogic; +signal rel_par_wC_clr :std_ulogic; +signal wayC_val :std_ulogic_vector(0 to 5); +signal wayC_val_b_q :std_ulogic_vector(0 to 5); +signal wayC_val_b1 :std_ulogic; +signal congr_cl_ex2_wayC_byp :std_ulogic_vector(1 to 7); +signal congr_cl_ex2_wayC_sel :std_ulogic_vector(2 to 7); +signal rel_arr_wayC_val :std_ulogic_vector(0 to 5); +signal p1_arr_wayC_rd :std_ulogic_vector(0 to 5); +signal rel_wayC_val_b_q :std_ulogic_vector(0 to 5); +signal rel_wayC_val :std_ulogic_vector(0 to 5); +signal congr_cl_rel13_wayC_byp :std_ulogic_vector(1 to 7); +signal congr_cl_rel13_wayC_sel :std_ulogic_vector(2 to 7); +signal reload_wayC_d :std_ulogic_vector(0 to 5); +signal reload_wayC_q :std_ulogic_vector(0 to 5); +signal reload_wayC_data_d :std_ulogic_vector(0 to 5); +signal reload_wayC_data_q :std_ulogic_vector(0 to 5); +signal reload_wayC_data2_d :std_ulogic_vector(0 to 5); +signal reload_wayC_data2_q :std_ulogic_vector(0 to 5); +signal reload_wayC_upd_d :std_ulogic; +signal reload_wayC_upd_q :std_ulogic; +signal reload_wayC_clr :std_ulogic; +signal reload_wayC_upd2_d :std_ulogic; +signal reload_wayC_upd2_q :std_ulogic; +signal reload_wayC_upd3_d :std_ulogic; +signal reload_wayC_upd3_q :std_ulogic; +signal reload_wayC :std_ulogic_vector(0 to 5); +signal binv_wayC_upd_d :std_ulogic; +signal binv_wayC_upd_q :std_ulogic; +signal binv_wayC_upd1 :std_ulogic; +signal binv_wayC_upd2_d :std_ulogic; +signal binv_wayC_upd2_q :std_ulogic; +signal binv_wayC_upd3_d :std_ulogic; +signal binv_wayC_upd3_q :std_ulogic; +signal flush_wayC_data1 :std_ulogic_vector(0 to 5); +signal flush_wayC_data_d :std_ulogic_vector(0 to 5); +signal flush_wayC_data_q :std_ulogic_vector(0 to 5); +signal flush_wayC_data2_d :std_ulogic_vector(0 to 5); +signal flush_wayC_data2_q :std_ulogic_vector(0 to 5); +signal xu_op_hit_wayC_b :std_ulogic; +signal xu_op_hit_wayC :std_ulogic; +signal xu_op_hit_wayC_dly_b :std_ulogic; +signal clr_val_wayC :std_ulogic; +signal upd_lck_wayC :std_ulogic_vector(0 to 1); +signal inval_clr_lck_wC_d :std_ulogic; +signal inval_clr_lck_wC_q :std_ulogic; +signal perr_way_det_wayC :std_ulogic; +signal perr_wayC_watch_lost :std_ulogic_vector(0 to 3); +signal wayC_watch_value :std_ulogic; +signal ex4_lost_wayC :std_ulogic_vector(0 to 3); +signal ex3_xuop_lost_watch_wayC :std_ulogic; +signal ex3_xuop_wayC_upd :std_ulogic; +signal ex4_xuop_wayC_upd_d :std_ulogic; +signal ex4_xuop_wayC_upd_q :std_ulogic; +signal ex4_wayC_val_d :std_ulogic_vector(0 to 5); +signal ex4_wayC_val_q :std_ulogic_vector(0 to 5); +signal rel_wayC_val_stg_d :std_ulogic_vector(0 to 5); +signal rel_wayC_val_stg_q :std_ulogic_vector(0 to 5); +signal ex5_xuop_wayC_upd_d :std_ulogic; +signal ex5_xuop_wayC_upd_q :std_ulogic; +signal congr_cl_ex3_upd_wayC :std_ulogic; +signal congr_cl_ex4_upd_wayC :std_ulogic; +signal congr_cl_ex5_upd_wayC :std_ulogic; +signal congr_cl_m_upd_wayC_d :std_ulogic; +signal congr_cl_m_upd_wayC_q :std_ulogic; +signal ex3_cClass_wayC_hit :std_ulogic; +signal wayC_later_stg_pri :std_ulogic_vector(0 to 5); +signal wayC_early_stg_pri :std_ulogic_vector(0 to 5); +signal wayC_stg_val :std_ulogic_vector(0 to 5); +signal wayC_stg_val_b :std_ulogic_vector(0 to 5); +signal rel_wayC_later_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayC_early_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayC_stg_val :std_ulogic_vector(0 to 5); +signal rel_wayC_stg_val_b :std_ulogic_vector(0 to 5); +signal wayC_early_sel :std_ulogic; +signal wayC_late_sel :std_ulogic; +signal rel_wayC_early_sel :std_ulogic; +signal rel_wayC_late_sel :std_ulogic; +signal ex3_wayC_hit :std_ulogic; +signal rel_lost_watch_wayC_evict :std_ulogic_vector(0 to 3); +signal ex3_wayC_fxubyp_val_d :std_ulogic; +signal ex3_wayC_fxubyp_val_q :std_ulogic; +signal ex4_wayC_fxubyp_val_d :std_ulogic; +signal ex4_wayC_fxubyp_val_q :std_ulogic; +signal ex3_wayC_relbyp_val_d :std_ulogic; +signal ex3_wayC_relbyp_val_q :std_ulogic; +signal ex4_wayC_relbyp_val_d :std_ulogic; +signal ex4_wayC_relbyp_val_q :std_ulogic; +signal ex4_wayC_byp_sel :std_ulogic_vector(0 to 1); +signal rel24_wayC_fxubyp_val_d :std_ulogic; +signal rel24_wayC_fxubyp_val_q :std_ulogic; +signal rel24_wayC_relbyp_val_d :std_ulogic; +signal rel24_wayC_relbyp_val_q :std_ulogic; +signal rel24_wayC_byp_sel :std_ulogic_vector(0 to 1); +signal tagD_hit :std_ulogic; +signal tagD_hit_b :std_ulogic; +signal arr_wayD_val :std_ulogic_vector(0 to 5); +signal p0_arr_wayD_rd :std_ulogic_vector(0 to 5); +signal flush_wayD_d :std_ulogic_vector(0 to 5); +signal flush_wayD_q :std_ulogic_vector(0 to 5); +signal rel_wayD_clr :std_ulogic; +signal rel_wayD_set :std_ulogic; +signal rel_par_wD_clr :std_ulogic; +signal wayD_val :std_ulogic_vector(0 to 5); +signal wayD_val_b_q :std_ulogic_vector(0 to 5); +signal wayD_val_b1 :std_ulogic; +signal congr_cl_ex2_wayD_byp :std_ulogic_vector(1 to 7); +signal congr_cl_ex2_wayD_sel :std_ulogic_vector(2 to 7); +signal rel_arr_wayD_val :std_ulogic_vector(0 to 5); +signal p1_arr_wayD_rd :std_ulogic_vector(0 to 5); +signal rel_wayD_val_b_q :std_ulogic_vector(0 to 5); +signal rel_wayD_val :std_ulogic_vector(0 to 5); +signal congr_cl_rel13_wayD_byp :std_ulogic_vector(1 to 7); +signal congr_cl_rel13_wayD_sel :std_ulogic_vector(2 to 7); +signal reload_wayD_d :std_ulogic_vector(0 to 5); +signal reload_wayD_q :std_ulogic_vector(0 to 5); +signal reload_wayD_data_d :std_ulogic_vector(0 to 5); +signal reload_wayD_data_q :std_ulogic_vector(0 to 5); +signal reload_wayD_data2_d :std_ulogic_vector(0 to 5); +signal reload_wayD_data2_q :std_ulogic_vector(0 to 5); +signal reload_wayD_upd_d :std_ulogic; +signal reload_wayD_upd_q :std_ulogic; +signal reload_wayD_clr :std_ulogic; +signal reload_wayD_upd2_d :std_ulogic; +signal reload_wayD_upd2_q :std_ulogic; +signal reload_wayD_upd3_d :std_ulogic; +signal reload_wayD_upd3_q :std_ulogic; +signal reload_wayD :std_ulogic_vector(0 to 5); +signal binv_wayD_upd_d :std_ulogic; +signal binv_wayD_upd_q :std_ulogic; +signal binv_wayD_upd1 :std_ulogic; +signal binv_wayD_upd2_d :std_ulogic; +signal binv_wayD_upd2_q :std_ulogic; +signal binv_wayD_upd3_d :std_ulogic; +signal binv_wayD_upd3_q :std_ulogic; +signal flush_wayD_data1 :std_ulogic_vector(0 to 5); +signal flush_wayD_data_d :std_ulogic_vector(0 to 5); +signal flush_wayD_data_q :std_ulogic_vector(0 to 5); +signal flush_wayD_data2_d :std_ulogic_vector(0 to 5); +signal flush_wayD_data2_q :std_ulogic_vector(0 to 5); +signal xu_op_hit_wayD_b :std_ulogic; +signal xu_op_hit_wayD :std_ulogic; +signal xu_op_hit_wayD_dly_b :std_ulogic; +signal clr_val_wayD :std_ulogic; +signal upd_lck_wayD :std_ulogic_vector(0 to 1); +signal inval_clr_lck_wD_d :std_ulogic; +signal inval_clr_lck_wD_q :std_ulogic; +signal perr_way_det_wayD :std_ulogic; +signal perr_wayD_watch_lost :std_ulogic_vector(0 to 3); +signal wayD_watch_value :std_ulogic; +signal ex4_lost_wayD :std_ulogic_vector(0 to 3); +signal ex3_xuop_lost_watch_wayD :std_ulogic; +signal ex3_xuop_wayD_upd :std_ulogic; +signal ex4_xuop_wayD_upd_d :std_ulogic; +signal ex4_xuop_wayD_upd_q :std_ulogic; +signal ex4_wayD_val_d :std_ulogic_vector(0 to 5); +signal ex4_wayD_val_q :std_ulogic_vector(0 to 5); +signal rel_wayD_val_stg_d :std_ulogic_vector(0 to 5); +signal rel_wayD_val_stg_q :std_ulogic_vector(0 to 5); +signal ex5_xuop_wayD_upd_d :std_ulogic; +signal ex5_xuop_wayD_upd_q :std_ulogic; +signal congr_cl_ex3_upd_wayD :std_ulogic; +signal congr_cl_ex4_upd_wayD :std_ulogic; +signal congr_cl_ex5_upd_wayD :std_ulogic; +signal congr_cl_m_upd_wayD_d :std_ulogic; +signal congr_cl_m_upd_wayD_q :std_ulogic; +signal ex3_cClass_wayD_hit :std_ulogic; +signal wayD_later_stg_pri :std_ulogic_vector(0 to 5); +signal wayD_early_stg_pri :std_ulogic_vector(0 to 5); +signal wayD_stg_val :std_ulogic_vector(0 to 5); +signal wayD_stg_val_b :std_ulogic_vector(0 to 5); +signal rel_wayD_later_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayD_early_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayD_stg_val :std_ulogic_vector(0 to 5); +signal rel_wayD_stg_val_b :std_ulogic_vector(0 to 5); +signal wayD_early_sel :std_ulogic; +signal wayD_late_sel :std_ulogic; +signal rel_wayD_early_sel :std_ulogic; +signal rel_wayD_late_sel :std_ulogic; +signal ex3_wayD_hit :std_ulogic; +signal rel_lost_watch_wayD_evict :std_ulogic_vector(0 to 3); +signal ex3_wayD_fxubyp_val_d :std_ulogic; +signal ex3_wayD_fxubyp_val_q :std_ulogic; +signal ex4_wayD_fxubyp_val_d :std_ulogic; +signal ex4_wayD_fxubyp_val_q :std_ulogic; +signal ex3_wayD_relbyp_val_d :std_ulogic; +signal ex3_wayD_relbyp_val_q :std_ulogic; +signal ex4_wayD_relbyp_val_d :std_ulogic; +signal ex4_wayD_relbyp_val_q :std_ulogic; +signal ex4_wayD_byp_sel :std_ulogic_vector(0 to 1); +signal rel24_wayD_fxubyp_val_d :std_ulogic; +signal rel24_wayD_fxubyp_val_q :std_ulogic; +signal rel24_wayD_relbyp_val_d :std_ulogic; +signal rel24_wayD_relbyp_val_q :std_ulogic; +signal rel24_wayD_byp_sel :std_ulogic_vector(0 to 1); +signal tagE_hit :std_ulogic; +signal tagE_hit_b :std_ulogic; +signal arr_wayE_val :std_ulogic_vector(0 to 5); +signal p0_arr_wayE_rd :std_ulogic_vector(0 to 5); +signal flush_wayE_d :std_ulogic_vector(0 to 5); +signal flush_wayE_q :std_ulogic_vector(0 to 5); +signal rel_wayE_clr :std_ulogic; +signal rel_wayE_set :std_ulogic; +signal rel_par_wE_clr :std_ulogic; +signal wayE_val :std_ulogic_vector(0 to 5); +signal wayE_val_b_q :std_ulogic_vector(0 to 5); +signal wayE_val_b1 :std_ulogic; +signal congr_cl_ex2_wayE_byp :std_ulogic_vector(1 to 7); +signal congr_cl_ex2_wayE_sel :std_ulogic_vector(2 to 7); +signal rel_arr_wayE_val :std_ulogic_vector(0 to 5); +signal p1_arr_wayE_rd :std_ulogic_vector(0 to 5); +signal rel_wayE_val_b_q :std_ulogic_vector(0 to 5); +signal rel_wayE_val :std_ulogic_vector(0 to 5); +signal congr_cl_rel13_wayE_byp :std_ulogic_vector(1 to 7); +signal congr_cl_rel13_wayE_sel :std_ulogic_vector(2 to 7); +signal reload_wayE_d :std_ulogic_vector(0 to 5); +signal reload_wayE_q :std_ulogic_vector(0 to 5); +signal reload_wayE_data_d :std_ulogic_vector(0 to 5); +signal reload_wayE_data_q :std_ulogic_vector(0 to 5); +signal reload_wayE_data2_d :std_ulogic_vector(0 to 5); +signal reload_wayE_data2_q :std_ulogic_vector(0 to 5); +signal reload_wayE_upd_d :std_ulogic; +signal reload_wayE_upd_q :std_ulogic; +signal reload_wayE_clr :std_ulogic; +signal reload_wayE_upd2_d :std_ulogic; +signal reload_wayE_upd2_q :std_ulogic; +signal reload_wayE_upd3_d :std_ulogic; +signal reload_wayE_upd3_q :std_ulogic; +signal reload_wayE :std_ulogic_vector(0 to 5); +signal binv_wayE_upd_d :std_ulogic; +signal binv_wayE_upd_q :std_ulogic; +signal binv_wayE_upd1 :std_ulogic; +signal binv_wayE_upd2_d :std_ulogic; +signal binv_wayE_upd2_q :std_ulogic; +signal binv_wayE_upd3_d :std_ulogic; +signal binv_wayE_upd3_q :std_ulogic; +signal flush_wayE_data1 :std_ulogic_vector(0 to 5); +signal flush_wayE_data_d :std_ulogic_vector(0 to 5); +signal flush_wayE_data_q :std_ulogic_vector(0 to 5); +signal flush_wayE_data2_d :std_ulogic_vector(0 to 5); +signal flush_wayE_data2_q :std_ulogic_vector(0 to 5); +signal xu_op_hit_wayE_b :std_ulogic; +signal xu_op_hit_wayE :std_ulogic; +signal xu_op_hit_wayE_dly_b :std_ulogic; +signal clr_val_wayE :std_ulogic; +signal upd_lck_wayE :std_ulogic_vector(0 to 1); +signal inval_clr_lck_wE_d :std_ulogic; +signal inval_clr_lck_wE_q :std_ulogic; +signal perr_way_det_wayE :std_ulogic; +signal perr_wayE_watch_lost :std_ulogic_vector(0 to 3); +signal wayE_watch_value :std_ulogic; +signal ex4_lost_wayE :std_ulogic_vector(0 to 3); +signal ex3_xuop_lost_watch_wayE :std_ulogic; +signal ex3_xuop_wayE_upd :std_ulogic; +signal ex4_xuop_wayE_upd_d :std_ulogic; +signal ex4_xuop_wayE_upd_q :std_ulogic; +signal ex4_wayE_val_d :std_ulogic_vector(0 to 5); +signal ex4_wayE_val_q :std_ulogic_vector(0 to 5); +signal rel_wayE_val_stg_d :std_ulogic_vector(0 to 5); +signal rel_wayE_val_stg_q :std_ulogic_vector(0 to 5); +signal ex5_xuop_wayE_upd_d :std_ulogic; +signal ex5_xuop_wayE_upd_q :std_ulogic; +signal congr_cl_ex3_upd_wayE :std_ulogic; +signal congr_cl_ex4_upd_wayE :std_ulogic; +signal congr_cl_ex5_upd_wayE :std_ulogic; +signal congr_cl_m_upd_wayE_d :std_ulogic; +signal congr_cl_m_upd_wayE_q :std_ulogic; +signal ex3_cClass_wayE_hit :std_ulogic; +signal wayE_later_stg_pri :std_ulogic_vector(0 to 5); +signal wayE_early_stg_pri :std_ulogic_vector(0 to 5); +signal wayE_stg_val :std_ulogic_vector(0 to 5); +signal wayE_stg_val_b :std_ulogic_vector(0 to 5); +signal rel_wayE_later_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayE_early_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayE_stg_val :std_ulogic_vector(0 to 5); +signal rel_wayE_stg_val_b :std_ulogic_vector(0 to 5); +signal wayE_early_sel :std_ulogic; +signal wayE_late_sel :std_ulogic; +signal rel_wayE_early_sel :std_ulogic; +signal rel_wayE_late_sel :std_ulogic; +signal ex3_wayE_hit :std_ulogic; +signal rel_lost_watch_wayE_evict :std_ulogic_vector(0 to 3); +signal ex3_wayE_fxubyp_val_d :std_ulogic; +signal ex3_wayE_fxubyp_val_q :std_ulogic; +signal ex4_wayE_fxubyp_val_d :std_ulogic; +signal ex4_wayE_fxubyp_val_q :std_ulogic; +signal ex3_wayE_relbyp_val_d :std_ulogic; +signal ex3_wayE_relbyp_val_q :std_ulogic; +signal ex4_wayE_relbyp_val_d :std_ulogic; +signal ex4_wayE_relbyp_val_q :std_ulogic; +signal ex4_wayE_byp_sel :std_ulogic_vector(0 to 1); +signal rel24_wayE_fxubyp_val_d :std_ulogic; +signal rel24_wayE_fxubyp_val_q :std_ulogic; +signal rel24_wayE_relbyp_val_d :std_ulogic; +signal rel24_wayE_relbyp_val_q :std_ulogic; +signal rel24_wayE_byp_sel :std_ulogic_vector(0 to 1); +signal tagF_hit :std_ulogic; +signal tagF_hit_b :std_ulogic; +signal arr_wayF_val :std_ulogic_vector(0 to 5); +signal p0_arr_wayF_rd :std_ulogic_vector(0 to 5); +signal flush_wayF_d :std_ulogic_vector(0 to 5); +signal flush_wayF_q :std_ulogic_vector(0 to 5); +signal rel_wayF_clr :std_ulogic; +signal rel_wayF_set :std_ulogic; +signal rel_par_wF_clr :std_ulogic; +signal wayF_val :std_ulogic_vector(0 to 5); +signal wayF_val_b_q :std_ulogic_vector(0 to 5); +signal wayF_val_b1 :std_ulogic; +signal congr_cl_ex2_wayF_byp :std_ulogic_vector(1 to 7); +signal congr_cl_ex2_wayF_sel :std_ulogic_vector(2 to 7); +signal rel_arr_wayF_val :std_ulogic_vector(0 to 5); +signal p1_arr_wayF_rd :std_ulogic_vector(0 to 5); +signal rel_wayF_val_b_q :std_ulogic_vector(0 to 5); +signal rel_wayF_val :std_ulogic_vector(0 to 5); +signal congr_cl_rel13_wayF_byp :std_ulogic_vector(1 to 7); +signal congr_cl_rel13_wayF_sel :std_ulogic_vector(2 to 7); +signal reload_wayF_d :std_ulogic_vector(0 to 5); +signal reload_wayF_q :std_ulogic_vector(0 to 5); +signal reload_wayF_data_d :std_ulogic_vector(0 to 5); +signal reload_wayF_data_q :std_ulogic_vector(0 to 5); +signal reload_wayF_data2_d :std_ulogic_vector(0 to 5); +signal reload_wayF_data2_q :std_ulogic_vector(0 to 5); +signal reload_wayF_upd_d :std_ulogic; +signal reload_wayF_upd_q :std_ulogic; +signal reload_wayF_clr :std_ulogic; +signal reload_wayF_upd2_d :std_ulogic; +signal reload_wayF_upd2_q :std_ulogic; +signal reload_wayF_upd3_d :std_ulogic; +signal reload_wayF_upd3_q :std_ulogic; +signal reload_wayF :std_ulogic_vector(0 to 5); +signal binv_wayF_upd_d :std_ulogic; +signal binv_wayF_upd_q :std_ulogic; +signal binv_wayF_upd1 :std_ulogic; +signal binv_wayF_upd2_d :std_ulogic; +signal binv_wayF_upd2_q :std_ulogic; +signal binv_wayF_upd3_d :std_ulogic; +signal binv_wayF_upd3_q :std_ulogic; +signal flush_wayF_data1 :std_ulogic_vector(0 to 5); +signal flush_wayF_data_d :std_ulogic_vector(0 to 5); +signal flush_wayF_data_q :std_ulogic_vector(0 to 5); +signal flush_wayF_data2_d :std_ulogic_vector(0 to 5); +signal flush_wayF_data2_q :std_ulogic_vector(0 to 5); +signal xu_op_hit_wayF_b :std_ulogic; +signal xu_op_hit_wayF :std_ulogic; +signal xu_op_hit_wayF_dly_b :std_ulogic; +signal clr_val_wayF :std_ulogic; +signal upd_lck_wayF :std_ulogic_vector(0 to 1); +signal inval_clr_lck_wF_d :std_ulogic; +signal inval_clr_lck_wF_q :std_ulogic; +signal perr_way_det_wayF :std_ulogic; +signal perr_wayF_watch_lost :std_ulogic_vector(0 to 3); +signal wayF_watch_value :std_ulogic; +signal ex4_lost_wayF :std_ulogic_vector(0 to 3); +signal ex3_xuop_lost_watch_wayF :std_ulogic; +signal ex3_xuop_wayF_upd :std_ulogic; +signal ex4_xuop_wayF_upd_d :std_ulogic; +signal ex4_xuop_wayF_upd_q :std_ulogic; +signal ex4_wayF_val_d :std_ulogic_vector(0 to 5); +signal ex4_wayF_val_q :std_ulogic_vector(0 to 5); +signal rel_wayF_val_stg_d :std_ulogic_vector(0 to 5); +signal rel_wayF_val_stg_q :std_ulogic_vector(0 to 5); +signal ex5_xuop_wayF_upd_d :std_ulogic; +signal ex5_xuop_wayF_upd_q :std_ulogic; +signal congr_cl_ex3_upd_wayF :std_ulogic; +signal congr_cl_ex4_upd_wayF :std_ulogic; +signal congr_cl_ex5_upd_wayF :std_ulogic; +signal congr_cl_m_upd_wayF_d :std_ulogic; +signal congr_cl_m_upd_wayF_q :std_ulogic; +signal ex3_cClass_wayF_hit :std_ulogic; +signal wayF_later_stg_pri :std_ulogic_vector(0 to 5); +signal wayF_early_stg_pri :std_ulogic_vector(0 to 5); +signal wayF_stg_val :std_ulogic_vector(0 to 5); +signal wayF_stg_val_b :std_ulogic_vector(0 to 5); +signal rel_wayF_later_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayF_early_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayF_stg_val :std_ulogic_vector(0 to 5); +signal rel_wayF_stg_val_b :std_ulogic_vector(0 to 5); +signal wayF_early_sel :std_ulogic; +signal wayF_late_sel :std_ulogic; +signal rel_wayF_early_sel :std_ulogic; +signal rel_wayF_late_sel :std_ulogic; +signal ex3_wayF_hit :std_ulogic; +signal rel_lost_watch_wayF_evict :std_ulogic_vector(0 to 3); +signal ex3_wayF_fxubyp_val_d :std_ulogic; +signal ex3_wayF_fxubyp_val_q :std_ulogic; +signal ex4_wayF_fxubyp_val_d :std_ulogic; +signal ex4_wayF_fxubyp_val_q :std_ulogic; +signal ex3_wayF_relbyp_val_d :std_ulogic; +signal ex3_wayF_relbyp_val_q :std_ulogic; +signal ex4_wayF_relbyp_val_d :std_ulogic; +signal ex4_wayF_relbyp_val_q :std_ulogic; +signal ex4_wayF_byp_sel :std_ulogic_vector(0 to 1); +signal rel24_wayF_fxubyp_val_d :std_ulogic; +signal rel24_wayF_fxubyp_val_q :std_ulogic; +signal rel24_wayF_relbyp_val_d :std_ulogic; +signal rel24_wayF_relbyp_val_q :std_ulogic; +signal rel24_wayF_byp_sel :std_ulogic_vector(0 to 1); +signal tagG_hit :std_ulogic; +signal tagG_hit_b :std_ulogic; +signal arr_wayG_val :std_ulogic_vector(0 to 5); +signal p0_arr_wayG_rd :std_ulogic_vector(0 to 5); +signal flush_wayG_d :std_ulogic_vector(0 to 5); +signal flush_wayG_q :std_ulogic_vector(0 to 5); +signal rel_wayG_clr :std_ulogic; +signal rel_wayG_set :std_ulogic; +signal rel_par_wG_clr :std_ulogic; +signal wayG_val :std_ulogic_vector(0 to 5); +signal wayG_val_b_q :std_ulogic_vector(0 to 5); +signal wayG_val_b1 :std_ulogic; +signal congr_cl_ex2_wayG_byp :std_ulogic_vector(1 to 7); +signal congr_cl_ex2_wayG_sel :std_ulogic_vector(2 to 7); +signal rel_arr_wayG_val :std_ulogic_vector(0 to 5); +signal p1_arr_wayG_rd :std_ulogic_vector(0 to 5); +signal rel_wayG_val_b_q :std_ulogic_vector(0 to 5); +signal rel_wayG_val :std_ulogic_vector(0 to 5); +signal congr_cl_rel13_wayG_byp :std_ulogic_vector(1 to 7); +signal congr_cl_rel13_wayG_sel :std_ulogic_vector(2 to 7); +signal reload_wayG_d :std_ulogic_vector(0 to 5); +signal reload_wayG_q :std_ulogic_vector(0 to 5); +signal reload_wayG_data_d :std_ulogic_vector(0 to 5); +signal reload_wayG_data_q :std_ulogic_vector(0 to 5); +signal reload_wayG_data2_d :std_ulogic_vector(0 to 5); +signal reload_wayG_data2_q :std_ulogic_vector(0 to 5); +signal reload_wayG_upd_d :std_ulogic; +signal reload_wayG_upd_q :std_ulogic; +signal reload_wayG_clr :std_ulogic; +signal reload_wayG_upd2_d :std_ulogic; +signal reload_wayG_upd2_q :std_ulogic; +signal reload_wayG_upd3_d :std_ulogic; +signal reload_wayG_upd3_q :std_ulogic; +signal reload_wayG :std_ulogic_vector(0 to 5); +signal binv_wayG_upd_d :std_ulogic; +signal binv_wayG_upd_q :std_ulogic; +signal binv_wayG_upd1 :std_ulogic; +signal binv_wayG_upd2_d :std_ulogic; +signal binv_wayG_upd2_q :std_ulogic; +signal binv_wayG_upd3_d :std_ulogic; +signal binv_wayG_upd3_q :std_ulogic; +signal flush_wayG_data1 :std_ulogic_vector(0 to 5); +signal flush_wayG_data_d :std_ulogic_vector(0 to 5); +signal flush_wayG_data_q :std_ulogic_vector(0 to 5); +signal flush_wayG_data2_d :std_ulogic_vector(0 to 5); +signal flush_wayG_data2_q :std_ulogic_vector(0 to 5); +signal xu_op_hit_wayG_b :std_ulogic; +signal xu_op_hit_wayG :std_ulogic; +signal xu_op_hit_wayG_dly_b :std_ulogic; +signal clr_val_wayG :std_ulogic; +signal upd_lck_wayG :std_ulogic_vector(0 to 1); +signal inval_clr_lck_wG_d :std_ulogic; +signal inval_clr_lck_wG_q :std_ulogic; +signal perr_way_det_wayG :std_ulogic; +signal perr_wayG_watch_lost :std_ulogic_vector(0 to 3); +signal wayG_watch_value :std_ulogic; +signal ex4_lost_wayG :std_ulogic_vector(0 to 3); +signal ex3_xuop_lost_watch_wayG :std_ulogic; +signal ex3_xuop_wayG_upd :std_ulogic; +signal ex4_xuop_wayG_upd_d :std_ulogic; +signal ex4_xuop_wayG_upd_q :std_ulogic; +signal ex4_wayG_val_d :std_ulogic_vector(0 to 5); +signal ex4_wayG_val_q :std_ulogic_vector(0 to 5); +signal rel_wayG_val_stg_d :std_ulogic_vector(0 to 5); +signal rel_wayG_val_stg_q :std_ulogic_vector(0 to 5); +signal ex5_xuop_wayG_upd_d :std_ulogic; +signal ex5_xuop_wayG_upd_q :std_ulogic; +signal congr_cl_ex3_upd_wayG :std_ulogic; +signal congr_cl_ex4_upd_wayG :std_ulogic; +signal congr_cl_ex5_upd_wayG :std_ulogic; +signal congr_cl_m_upd_wayG_d :std_ulogic; +signal congr_cl_m_upd_wayG_q :std_ulogic; +signal ex3_cClass_wayG_hit :std_ulogic; +signal wayG_later_stg_pri :std_ulogic_vector(0 to 5); +signal wayG_early_stg_pri :std_ulogic_vector(0 to 5); +signal wayG_stg_val :std_ulogic_vector(0 to 5); +signal wayG_stg_val_b :std_ulogic_vector(0 to 5); +signal rel_wayG_later_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayG_early_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayG_stg_val :std_ulogic_vector(0 to 5); +signal rel_wayG_stg_val_b :std_ulogic_vector(0 to 5); +signal wayG_early_sel :std_ulogic; +signal wayG_late_sel :std_ulogic; +signal rel_wayG_early_sel :std_ulogic; +signal rel_wayG_late_sel :std_ulogic; +signal ex3_wayG_hit :std_ulogic; +signal rel_lost_watch_wayG_evict :std_ulogic_vector(0 to 3); +signal ex3_wayG_fxubyp_val_d :std_ulogic; +signal ex3_wayG_fxubyp_val_q :std_ulogic; +signal ex4_wayG_fxubyp_val_d :std_ulogic; +signal ex4_wayG_fxubyp_val_q :std_ulogic; +signal ex3_wayG_relbyp_val_d :std_ulogic; +signal ex3_wayG_relbyp_val_q :std_ulogic; +signal ex4_wayG_relbyp_val_d :std_ulogic; +signal ex4_wayG_relbyp_val_q :std_ulogic; +signal ex4_wayG_byp_sel :std_ulogic_vector(0 to 1); +signal rel24_wayG_fxubyp_val_d :std_ulogic; +signal rel24_wayG_fxubyp_val_q :std_ulogic; +signal rel24_wayG_relbyp_val_d :std_ulogic; +signal rel24_wayG_relbyp_val_q :std_ulogic; +signal rel24_wayG_byp_sel :std_ulogic_vector(0 to 1); +signal tagH_hit :std_ulogic; +signal tagH_hit_b :std_ulogic; +signal arr_wayH_val :std_ulogic_vector(0 to 5); +signal p0_arr_wayH_rd :std_ulogic_vector(0 to 5); +signal flush_wayH_d :std_ulogic_vector(0 to 5); +signal flush_wayH_q :std_ulogic_vector(0 to 5); +signal rel_wayH_clr :std_ulogic; +signal rel_wayH_set :std_ulogic; +signal rel_par_wH_clr :std_ulogic; +signal wayH_val :std_ulogic_vector(0 to 5); +signal wayH_val_b_q :std_ulogic_vector(0 to 5); +signal wayH_val_b1 :std_ulogic; +signal congr_cl_ex2_wayH_byp :std_ulogic_vector(1 to 7); +signal congr_cl_ex2_wayH_sel :std_ulogic_vector(2 to 7); +signal rel_arr_wayH_val :std_ulogic_vector(0 to 5); +signal p1_arr_wayH_rd :std_ulogic_vector(0 to 5); +signal rel_wayH_val_b_q :std_ulogic_vector(0 to 5); +signal rel_wayH_val :std_ulogic_vector(0 to 5); +signal congr_cl_rel13_wayH_byp :std_ulogic_vector(1 to 7); +signal congr_cl_rel13_wayH_sel :std_ulogic_vector(2 to 7); +signal reload_wayH_d :std_ulogic_vector(0 to 5); +signal reload_wayH_q :std_ulogic_vector(0 to 5); +signal reload_wayH_data_d :std_ulogic_vector(0 to 5); +signal reload_wayH_data_q :std_ulogic_vector(0 to 5); +signal reload_wayH_data2_d :std_ulogic_vector(0 to 5); +signal reload_wayH_data2_q :std_ulogic_vector(0 to 5); +signal reload_wayH_upd_d :std_ulogic; +signal reload_wayH_upd_q :std_ulogic; +signal reload_wayH_clr :std_ulogic; +signal reload_wayH_upd2_d :std_ulogic; +signal reload_wayH_upd2_q :std_ulogic; +signal reload_wayH_upd3_d :std_ulogic; +signal reload_wayH_upd3_q :std_ulogic; +signal reload_wayH :std_ulogic_vector(0 to 5); +signal binv_wayH_upd_d :std_ulogic; +signal binv_wayH_upd_q :std_ulogic; +signal binv_wayH_upd1 :std_ulogic; +signal binv_wayH_upd2_d :std_ulogic; +signal binv_wayH_upd2_q :std_ulogic; +signal binv_wayH_upd3_d :std_ulogic; +signal binv_wayH_upd3_q :std_ulogic; +signal flush_wayH_data1 :std_ulogic_vector(0 to 5); +signal flush_wayH_data_d :std_ulogic_vector(0 to 5); +signal flush_wayH_data_q :std_ulogic_vector(0 to 5); +signal flush_wayH_data2_d :std_ulogic_vector(0 to 5); +signal flush_wayH_data2_q :std_ulogic_vector(0 to 5); +signal xu_op_hit_wayH_b :std_ulogic; +signal xu_op_hit_wayH :std_ulogic; +signal xu_op_hit_wayH_dly_b :std_ulogic; +signal clr_val_wayH :std_ulogic; +signal upd_lck_wayH :std_ulogic_vector(0 to 1); +signal inval_clr_lck_wH_d :std_ulogic; +signal inval_clr_lck_wH_q :std_ulogic; +signal perr_way_det_wayH :std_ulogic; +signal perr_wayH_watch_lost :std_ulogic_vector(0 to 3); +signal wayH_watch_value :std_ulogic; +signal ex4_lost_wayH :std_ulogic_vector(0 to 3); +signal ex3_xuop_lost_watch_wayH :std_ulogic; +signal ex3_xuop_wayH_upd :std_ulogic; +signal ex4_xuop_wayH_upd_d :std_ulogic; +signal ex4_xuop_wayH_upd_q :std_ulogic; +signal ex4_wayH_val_d :std_ulogic_vector(0 to 5); +signal ex4_wayH_val_q :std_ulogic_vector(0 to 5); +signal rel_wayH_val_stg_d :std_ulogic_vector(0 to 5); +signal rel_wayH_val_stg_q :std_ulogic_vector(0 to 5); +signal ex5_xuop_wayH_upd_d :std_ulogic; +signal ex5_xuop_wayH_upd_q :std_ulogic; +signal congr_cl_ex3_upd_wayH :std_ulogic; +signal congr_cl_ex4_upd_wayH :std_ulogic; +signal congr_cl_ex5_upd_wayH :std_ulogic; +signal congr_cl_m_upd_wayH_d :std_ulogic; +signal congr_cl_m_upd_wayH_q :std_ulogic; +signal ex3_cClass_wayH_hit :std_ulogic; +signal wayH_later_stg_pri :std_ulogic_vector(0 to 5); +signal wayH_early_stg_pri :std_ulogic_vector(0 to 5); +signal wayH_stg_val :std_ulogic_vector(0 to 5); +signal wayH_stg_val_b :std_ulogic_vector(0 to 5); +signal rel_wayH_later_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayH_early_stg_pri :std_ulogic_vector(0 to 5); +signal rel_wayH_stg_val :std_ulogic_vector(0 to 5); +signal rel_wayH_stg_val_b :std_ulogic_vector(0 to 5); +signal wayH_early_sel :std_ulogic; +signal wayH_late_sel :std_ulogic; +signal rel_wayH_early_sel :std_ulogic; +signal rel_wayH_late_sel :std_ulogic; +signal ex3_wayH_hit :std_ulogic; +signal rel_lost_watch_wayH_evict :std_ulogic_vector(0 to 3); +signal ex3_wayH_fxubyp_val_d :std_ulogic; +signal ex3_wayH_fxubyp_val_q :std_ulogic; +signal ex4_wayH_fxubyp_val_d :std_ulogic; +signal ex4_wayH_fxubyp_val_q :std_ulogic; +signal ex3_wayH_relbyp_val_d :std_ulogic; +signal ex3_wayH_relbyp_val_q :std_ulogic; +signal ex4_wayH_relbyp_val_d :std_ulogic; +signal ex4_wayH_relbyp_val_q :std_ulogic; +signal ex4_wayH_byp_sel :std_ulogic_vector(0 to 1); +signal rel24_wayH_fxubyp_val_d :std_ulogic; +signal rel24_wayH_fxubyp_val_q :std_ulogic; +signal rel24_wayH_relbyp_val_d :std_ulogic; +signal rel24_wayH_relbyp_val_q :std_ulogic; +signal rel24_wayH_byp_sel :std_ulogic_vector(0 to 1); +signal stm_upd_watchlost_tid0 :std_ulogic_vector(0 to 1); +signal upd_watch_tid0_wayA :std_ulogic_vector(0 to 1); +signal upd_watch_tid0_wayB :std_ulogic_vector(0 to 1); +signal upd_watch_tid0_wayC :std_ulogic_vector(0 to 1); +signal upd_watch_tid0_wayD :std_ulogic_vector(0 to 1); +signal upd_watch_tid0_wayE :std_ulogic_vector(0 to 1); +signal upd_watch_tid0_wayF :std_ulogic_vector(0 to 1); +signal upd_watch_tid0_wayG :std_ulogic_vector(0 to 1); +signal upd_watch_tid0_wayH :std_ulogic_vector(0 to 1); +signal stm_upd_watchlost_tid1 :std_ulogic_vector(0 to 1); +signal upd_watch_tid1_wayA :std_ulogic_vector(0 to 1); +signal upd_watch_tid1_wayB :std_ulogic_vector(0 to 1); +signal upd_watch_tid1_wayC :std_ulogic_vector(0 to 1); +signal upd_watch_tid1_wayD :std_ulogic_vector(0 to 1); +signal upd_watch_tid1_wayE :std_ulogic_vector(0 to 1); +signal upd_watch_tid1_wayF :std_ulogic_vector(0 to 1); +signal upd_watch_tid1_wayG :std_ulogic_vector(0 to 1); +signal upd_watch_tid1_wayH :std_ulogic_vector(0 to 1); +signal stm_upd_watchlost_tid2 :std_ulogic_vector(0 to 1); +signal upd_watch_tid2_wayA :std_ulogic_vector(0 to 1); +signal upd_watch_tid2_wayB :std_ulogic_vector(0 to 1); +signal upd_watch_tid2_wayC :std_ulogic_vector(0 to 1); +signal upd_watch_tid2_wayD :std_ulogic_vector(0 to 1); +signal upd_watch_tid2_wayE :std_ulogic_vector(0 to 1); +signal upd_watch_tid2_wayF :std_ulogic_vector(0 to 1); +signal upd_watch_tid2_wayG :std_ulogic_vector(0 to 1); +signal upd_watch_tid2_wayH :std_ulogic_vector(0 to 1); +signal stm_upd_watchlost_tid3 :std_ulogic_vector(0 to 1); +signal upd_watch_tid3_wayA :std_ulogic_vector(0 to 1); +signal upd_watch_tid3_wayB :std_ulogic_vector(0 to 1); +signal upd_watch_tid3_wayC :std_ulogic_vector(0 to 1); +signal upd_watch_tid3_wayD :std_ulogic_vector(0 to 1); +signal upd_watch_tid3_wayE :std_ulogic_vector(0 to 1); +signal upd_watch_tid3_wayF :std_ulogic_vector(0 to 1); +signal upd_watch_tid3_wayG :std_ulogic_vector(0 to 1); +signal upd_watch_tid3_wayH :std_ulogic_vector(0 to 1); +signal congr_cl_all_act_d :std_ulogic; +signal congr_cl_all_act_q :std_ulogic; +signal ex3_flush_cline_d :std_ulogic; +signal ex3_flush_cline_q :std_ulogic; +signal congr_cl_ex2_ex3_m :std_ulogic; +signal congr_cl_ex2_ex4_m :std_ulogic; +signal congr_cl_ex2_ex5_m :std_ulogic; +signal congr_cl_ex2_relu_m :std_ulogic; +signal congr_cl_ex2_relu_s_m :std_ulogic; +signal congr_cl_ex2_ex3_cmp_d :std_ulogic; +signal congr_cl_ex2_ex3_cmp_q :std_ulogic; +signal congr_cl_ex2_ex4_cmp_d :std_ulogic; +signal congr_cl_ex2_ex4_cmp_q :std_ulogic; +signal congr_cl_ex2_ex5_cmp_d :std_ulogic; +signal congr_cl_ex2_ex5_cmp_q :std_ulogic; +signal congr_cl_ex2_ex6_cmp_d :std_ulogic; +signal congr_cl_ex2_ex6_cmp_q :std_ulogic; +signal congr_cl_ex3_ex4_cmp_d :std_ulogic; +signal congr_cl_ex3_ex4_cmp_q :std_ulogic; +signal congr_cl_ex3_ex5_cmp_d :std_ulogic; +signal congr_cl_ex3_ex5_cmp_q :std_ulogic; +signal congr_cl_ex3_ex6_cmp_d :std_ulogic; +signal congr_cl_ex3_ex6_cmp_q :std_ulogic; +signal congr_cl_ex4_ex5_cmp_d :std_ulogic; +signal congr_cl_ex4_ex5_cmp_q :std_ulogic; +signal congr_cl_ex4_ex6_cmp_d :std_ulogic; +signal congr_cl_ex4_ex6_cmp_q :std_ulogic; +signal congr_cl_ex4_ex7_cmp_d :std_ulogic; +signal congr_cl_ex4_ex7_cmp_q :std_ulogic; +signal congr_cl_ex2_p0_cmp :std_ulogic; +signal congr_cl_ex2_relu_cmp_d :std_ulogic; +signal congr_cl_ex2_relu_cmp_q :std_ulogic; +signal congr_cl_ex2_relu_s_cmp_d :std_ulogic; +signal congr_cl_ex2_relu_s_cmp_q :std_ulogic; +signal congr_cl_ex2_rel_upd_cmp_d :std_ulogic; +signal congr_cl_ex2_rel_upd_cmp_q :std_ulogic; +signal congr_cl_ex2_p1_cmp :std_ulogic; +signal ex4_congr_cl_d :std_ulogic_vector(2 to 7); +signal ex4_congr_cl_q :std_ulogic_vector(2 to 7); +signal ex5_congr_cl_d :std_ulogic_vector(2 to 7); +signal ex5_congr_cl_q :std_ulogic_vector(2 to 7); +signal ex6_congr_cl_d :std_ulogic_vector(2 to 7); +signal ex6_congr_cl_q :std_ulogic_vector(2 to 7); +signal ex7_congr_cl_d :std_ulogic_vector(2 to 7); +signal ex7_congr_cl_q :std_ulogic_vector(2 to 7); +signal ex8_congr_cl_d :std_ulogic_vector(2 to 7); +signal ex8_congr_cl_q :std_ulogic_vector(2 to 7); +signal ex9_congr_cl_d :std_ulogic_vector(2 to 7); +signal ex9_congr_cl_q :std_ulogic_vector(2 to 7); +signal rel_early_congr_cl :std_ulogic_vector(2 to 7); +signal rel_congr_cl_d :std_ulogic_vector(2 to 7); +signal rel_congr_cl_q :std_ulogic_vector(2 to 7); +signal rel_val_stg1 :std_ulogic; +signal rel_val_stg2_d :std_ulogic; +signal rel_val_stg2_q :std_ulogic; +signal rel_val_clr_d :std_ulogic; +signal rel_val_clr_q :std_ulogic; +signal rel_val_stg3 :std_ulogic; +signal rel_val_stg4 :std_ulogic; +signal rel_val_stg4_d :std_ulogic; +signal rel_val_stg4_q :std_ulogic; +signal rel_binv_stg4_d :std_ulogic; +signal rel_binv_stg4_q :std_ulogic; +signal back_inval_stg2 :std_ulogic; +signal back_inval_stg3_d :std_ulogic; +signal back_inval_stg3_q :std_ulogic; +signal back_inval_stg4_d :std_ulogic; +signal back_inval_stg4_q :std_ulogic; +signal back_inval_stg5_d :std_ulogic; +signal back_inval_stg5_q :std_ulogic; +signal ex1_congr_cl :std_ulogic_vector(2 to 7); +signal ex2_congr_cl_d :std_ulogic_vector(2 to 7); +signal ex2_congr_cl_q :std_ulogic_vector(2 to 7); +signal ex3_congr_cl_d :std_ulogic_vector(2 to 7); +signal ex3_congr_cl_q :std_ulogic_vector(2 to 7); +signal rel24_congr_cl_d :std_ulogic_vector(2 to 7); +signal rel24_congr_cl_q :std_ulogic_vector(2 to 7); +signal p0_wren_d :std_ulogic; +signal p0_wren_q :std_ulogic; +signal p0_wren_cpy_d :std_ulogic; +signal p0_wren_cpy_q :std_ulogic; +signal p0_wren_stg_d :std_ulogic; +signal p0_wren_stg_q :std_ulogic; +signal p1_wren_d :std_ulogic; +signal p1_wren_q :std_ulogic; +signal p1_wren_cpy_d :std_ulogic; +signal p1_wren_cpy_q :std_ulogic; +signal congr_cl_rel13_ex3_m :std_ulogic; +signal congr_cl_rel13_ex4_m :std_ulogic; +signal congr_cl_rel13_ex5_m :std_ulogic; +signal congr_cl_rel13_relu_m :std_ulogic; +signal congr_cl_rel13_relu_s_m :std_ulogic; +signal congr_cl_rel13_ex3_cmp_d :std_ulogic; +signal congr_cl_rel13_ex3_cmp_q :std_ulogic; +signal congr_cl_rel13_ex4_cmp_d :std_ulogic; +signal congr_cl_rel13_ex4_cmp_q :std_ulogic; +signal congr_cl_rel13_ex5_cmp_d :std_ulogic; +signal congr_cl_rel13_ex5_cmp_q :std_ulogic; +signal congr_cl_rel13_ex6_cmp_d :std_ulogic; +signal congr_cl_rel13_ex6_cmp_q :std_ulogic; +signal congr_cl_rel13_p0_cmp :std_ulogic; +signal congr_cl_rel13_relu_cmp_d :std_ulogic; +signal congr_cl_rel13_relu_cmp_q :std_ulogic; +signal congr_cl_rel13_relu_s_cmp_d :std_ulogic; +signal congr_cl_rel13_relu_s_cmp_q :std_ulogic; +signal congr_cl_rel13_rel_upd_cmp_d :std_ulogic; +signal congr_cl_rel13_rel_upd_cmp_q :std_ulogic; +signal congr_cl_rel13_p1_cmp :std_ulogic; +signal ex3_c_acc :std_ulogic; +signal fxu_pipe_val :std_ulogic; +signal rel_set_val :std_ulogic; +signal ex3_store_instr_d :std_ulogic; +signal ex3_store_instr_q :std_ulogic; +signal ex3_lock_set_d :std_ulogic; +signal ex3_lock_set_q :std_ulogic; +signal ex4_lock_set_d :std_ulogic; +signal ex4_lock_set_q :std_ulogic; +signal ex5_lock_set_d :std_ulogic; +signal ex5_lock_set_q :std_ulogic; +signal ex3_lock_clr_d :std_ulogic; +signal ex3_lock_clr_q :std_ulogic; +signal clr_val :std_ulogic; +signal clr_lock :std_ulogic; +signal rel_val_set :std_ulogic; +signal rel_lock_set_d :std_ulogic; +signal rel_lock_set_q :std_ulogic; +signal rel_l1dump_cslc_d :std_ulogic; +signal rel_l1dump_cslc_q :std_ulogic; +signal rel_no_ovr_lock :std_ulogic; +signal rel_lock_lost :std_ulogic; +signal ex3_xuop_val :std_ulogic; +signal ex3_xuop_val_d :std_ulogic; +signal ex3_xuop_val_q :std_ulogic; +signal ex4_xuop_val :std_ulogic; +signal ex4_xuop_val_d :std_ulogic; +signal ex4_xuop_val_q :std_ulogic; +signal ex5_xuop_val :std_ulogic; +signal ex5_xuop_val_d :std_ulogic; +signal ex5_xuop_val_q :std_ulogic; +signal ex4_l_fld_b1_d :std_ulogic; +signal ex4_l_fld_b1_q :std_ulogic; +signal rel_in_progress :std_ulogic; +signal rel_in_progress_d :std_ulogic; +signal rel_in_progress_q :std_ulogic; +signal ex4_miss_q :std_ulogic; +signal ex4_way_hit_d :std_ulogic_vector(0 to 7); +signal ex4_way_hit_q :std_ulogic_vector(0 to 7); +signal ex5_way_hit_d :std_ulogic_vector(0 to 7); +signal ex5_way_hit_q :std_ulogic_vector(0 to 7); +signal ex6_way_hit_d :std_ulogic_vector(0 to 7); +signal ex6_way_hit_q :std_ulogic_vector(0 to 7); +signal ex7_way_hit_d :std_ulogic_vector(0 to 7); +signal ex7_way_hit_q :std_ulogic_vector(0 to 7); +signal ex8_way_hit_d :std_ulogic_vector(0 to 7); +signal ex8_way_hit_q :std_ulogic_vector(0 to 7); +signal ex9_way_hit_d :std_ulogic_vector(0 to 7); +signal ex9_way_hit_q :std_ulogic_vector(0 to 7); +signal dcpar_err_congr_cl :std_ulogic_vector(2 to 7); +signal dcpar_err_stg1_d :std_ulogic; +signal dcpar_err_stg1_q :std_ulogic; +signal dcpar_err_stg2_d :std_ulogic; +signal dcpar_err_stg2_q :std_ulogic; +signal dcpar_err_way_d :std_ulogic_vector(0 to 7); +signal dcpar_err_way_q :std_ulogic_vector(0 to 7); +signal dcpar_err_way_inval_d :std_ulogic_vector(0 to 7); +signal dcpar_err_way_inval_q :std_ulogic_vector(0 to 7); +signal dcpar_err_cntr_d :std_ulogic_vector(0 to 1); +signal dcpar_err_cntr_q :std_ulogic_vector(0 to 1); +signal dcpar_err_push :std_ulogic; +signal dcpar_err_rec_cmpl :std_ulogic; +signal dcpar_err_nxt_rec :std_ulogic; +signal dcpar_err_push_queue :std_ulogic; +signal dcpar_err_ind_sel :std_ulogic_vector(0 to 1); +signal dcpar_err_incr_val :std_ulogic; +signal dcpar_err_cntr_sel :std_ulogic_vector(0 to 1); +signal dcpar_err_nxt_cntr :std_ulogic_vector(0 to 1); +signal dcpar_err_rec_inprog :std_ulogic; +signal dcpar_err_ind_sel_d :std_ulogic_vector(0 to 1); +signal dcpar_err_ind_sel_q :std_ulogic_vector(0 to 1); +signal dcpar_err_push_queue_d :std_ulogic; +signal dcpar_err_push_queue_q :std_ulogic; +signal lock_finval :std_ulogic; +signal inval_clr_lck :std_ulogic; +signal xucr0_cslc_xuop_d :std_ulogic; +signal xucr0_cslc_xuop_q :std_ulogic; +signal xucr0_cslc_binv_d :std_ulogic; +signal xucr0_cslc_binv_q :std_ulogic; +signal dci_compl_d :std_ulogic; +signal dci_compl_q :std_ulogic; +signal dci_inval_all_d :std_ulogic; +signal dci_inval_all_q :std_ulogic; +signal inv2_val_d :std_ulogic; +signal inv2_val_q :std_ulogic; +signal perf_binv_hit :std_ulogic; +signal perf_lsu_evnts_d :std_ulogic_vector(0 to 4); +signal perf_lsu_evnts_q :std_ulogic_vector(0 to 4); +signal lock_flash_clear_d :std_ulogic; +signal lock_flash_clear_q :std_ulogic; +signal lock_flash_clear_val_d :std_ulogic; +signal lock_flash_clear_val_q :std_ulogic; +signal rel_port_upd_d :std_ulogic; +signal rel_port_upd_q :std_ulogic; +signal p1_upd_val :std_ulogic; +signal rel_port_wren_d :std_ulogic; +signal rel_port_wren_q :std_ulogic; +signal ex2_thrd_id_d :std_ulogic_vector(0 to 3); +signal ex2_thrd_id_q :std_ulogic_vector(0 to 3); +signal ex3_thrd_id_d :std_ulogic_vector(0 to 3); +signal ex3_thrd_id_q :std_ulogic_vector(0 to 3); +signal ex4_thrd_id_d :std_ulogic_vector(0 to 3); +signal ex4_thrd_id_q :std_ulogic_vector(0 to 3); +signal ex5_thrd_id_d :std_ulogic_vector(0 to 3); +signal ex5_thrd_id_q :std_ulogic_vector(0 to 3); +signal ex3_watch_set_d :std_ulogic; +signal ex3_watch_set_q :std_ulogic; +signal ex4_watch_set_d :std_ulogic; +signal ex4_watch_set_q :std_ulogic; +signal ex5_watch_set_d :std_ulogic; +signal ex5_watch_set_q :std_ulogic; +signal ex3_watch_clr_d :std_ulogic; +signal ex3_watch_clr_q :std_ulogic; +signal ex2_watch_clr_all :std_ulogic; +signal ex2_watch_clr_one :std_ulogic; +signal ex3_watch_clr_all_d :std_ulogic; +signal ex3_watch_clr_all_q :std_ulogic; +signal ex3_watch_clr_all :std_ulogic_vector(0 to 3); +signal ex4_watch_clr_all_d :std_ulogic_vector(0 to 3); +signal ex4_watch_clr_all_q :std_ulogic_vector(0 to 3); +signal ex5_watch_clr_all_d :std_ulogic_vector(0 to 3); +signal ex5_watch_clr_all_q :std_ulogic_vector(0 to 3); +signal ex6_watch_clr_all_d :std_ulogic_vector(0 to 3); +signal ex6_watch_clr_all_q :std_ulogic_vector(0 to 3); +signal ex5_watch_clr_all_val_d :std_ulogic; +signal ex5_watch_clr_all_val_q :std_ulogic; +signal rel_watch_set_d :std_ulogic; +signal rel_watch_set_q :std_ulogic; +signal rel_thrd_id_d :std_ulogic_vector(0 to 3); +signal rel_thrd_id_q :std_ulogic_vector(0 to 3); +signal rel_watch_lost :std_ulogic_vector(0 to 3); +signal lose_watch :std_ulogic_vector(0 to 3); +signal ex4_lose_watch_d :std_ulogic_vector(0 to 3); +signal ex4_lose_watch_q :std_ulogic_vector(0 to 3); +signal clr_watch :std_ulogic_vector(0 to 3); +signal set_watch :std_ulogic_vector(0 to 3); +signal ex4_curr_watch :std_ulogic; +signal stm_watchlost_sel :std_ulogic; +signal ex5_cr_watch_d :std_ulogic; +signal ex5_cr_watch_q :std_ulogic; +signal ex4_lost_watch :std_ulogic_vector(0 to 3); +signal ex4_lost_watch_upd :std_ulogic_vector(0 to 3); +signal ex5_lost_watch_upd_d :std_ulogic_vector(0 to 3); +signal ex5_lost_watch_upd_q :std_ulogic_vector(0 to 3); +signal ex4_watchlost_set_d :std_ulogic_vector(0 to 3); +signal ex4_watchlost_set_q :std_ulogic_vector(0 to 3); +signal ex5_watchlost_set_d :std_ulogic_vector(0 to 3); +signal ex5_watchlost_set_q :std_ulogic_vector(0 to 3); +signal rel_lost_watch_binv_d :std_ulogic_vector(0 to 3); +signal rel_lost_watch_binv_q :std_ulogic_vector(0 to 3); +signal rel_lost_watch_upd_d :std_ulogic_vector(0 to 3); +signal rel_lost_watch_upd_q :std_ulogic_vector(0 to 3); +signal rel_lost_watch_evict :std_ulogic_vector(0 to 3); +signal rel_lost_watch_evict_np :std_ulogic_vector(0 to 3); +signal lost_watch_evict_ovl_d :std_ulogic_vector(0 to 3); +signal lost_watch_evict_ovl_q :std_ulogic_vector(0 to 3); +signal lost_watch_binv :std_ulogic_vector(0 to 3); +signal lost_watch_inter_thrd_d :std_ulogic_vector(0 to 3); +signal lost_watch_inter_thrd_q :std_ulogic_vector(0 to 3); +signal stm_watchlost :std_ulogic_vector(0 to 3); +signal rel_watchlost_upd :std_ulogic_vector(0 to 3); +signal ex5_watchlost_upd :std_ulogic_vector(0 to 3); +signal stm_watchlost_state_d :std_ulogic_vector(0 to 3); +signal stm_watchlost_state_q :std_ulogic_vector(0 to 3); +signal ex5_xuop_p0_upd_d :std_ulogic; +signal ex5_xuop_p0_upd_q :std_ulogic; +signal rel_val_stg24 :std_ulogic; +signal rel_val_stgu_d :std_ulogic; +signal rel_val_stgu_q :std_ulogic; +signal relu_congr_cl_d :std_ulogic_vector(2 to 7); +signal relu_congr_cl_q :std_ulogic_vector(2 to 7); +signal relu_s_congr_cl_d :std_ulogic_vector(2 to 7); +signal relu_s_congr_cl_q :std_ulogic_vector(2 to 7); +signal ex3_thrd_m_d :std_ulogic; +signal ex3_thrd_m_q :std_ulogic; +signal ex4_thrd_m_d :std_ulogic; +signal ex4_thrd_m_q :std_ulogic; +signal ex5_thrd_m_d :std_ulogic; +signal ex5_thrd_m_q :std_ulogic; +signal ex6_thrd_m_d :std_ulogic; +signal ex6_thrd_m_q :std_ulogic; +signal ex7_ld_par_err_d :std_ulogic; +signal ex7_ld_par_err_q :std_ulogic; +signal ex8_ld_par_err_d :std_ulogic; +signal ex8_ld_par_err_q :std_ulogic; +signal ex9_ld_par_err_d :std_ulogic; +signal ex9_ld_par_err_q :std_ulogic; +signal ex6_ld_valid_d :std_ulogic; +signal ex6_ld_valid_q :std_ulogic; +signal ex7_ld_valid_d :std_ulogic; +signal ex7_ld_valid_q :std_ulogic; +signal ex8_ld_valid_d :std_ulogic; +signal ex8_ld_valid_q :std_ulogic; +signal ex9_ld_valid_d :std_ulogic; +signal ex9_ld_valid_q :std_ulogic; +signal inj_dir_multihit_b :std_ulogic; +signal inj_dir_multihit_d :std_ulogic; +signal inj_dir_multihit_q :std_ulogic; +signal binv1_ex1_stg_act :std_ulogic; +signal binv2_ex2_stg_act :std_ulogic; +signal binv3_ex3_stg_act :std_ulogic; +signal binv4_ex4_stg_act :std_ulogic; +signal binv5_ex5_stg_act :std_ulogic; +signal binv2_ex2_val_stg_act :std_ulogic; +signal binv3_ex3_val_stg_act :std_ulogic; +signal binv4_ex4_val_stg_act :std_ulogic; +signal binv5_ex5_val_stg_act :std_ulogic; +signal dcpar_err_stg1_act_d :std_ulogic; +signal dcpar_err_stg1_act_q :std_ulogic; +signal dcpar_err_stg2_act_d :std_ulogic; +signal dcpar_err_stg2_act_q :std_ulogic; +signal rel1_perr_stg_act :std_ulogic; +signal rel2_perr_stg_act :std_ulogic; +signal rel3_perr_stg_act_d :std_ulogic; +signal rel3_perr_stg_act_q :std_ulogic; +signal rel4_perr_stg_act_d :std_ulogic; +signal rel4_perr_stg_act_q :std_ulogic; +signal reload_way_clr_d :std_ulogic_vector(0 to 7); +signal reload_way_clr_q :std_ulogic_vector(0 to 7); +signal ex4_watchSet_coll_d :std_ulogic; +signal ex4_watchSet_coll_q :std_ulogic; +signal watchSet_rel_way_coll :std_ulogic_vector(0 to 7); +signal watchSet_rel_coll_val :std_ulogic_vector(0 to 3); +signal rel24_congr_cl_ex4_cmp_d :std_ulogic; +signal rel24_congr_cl_ex4_cmp_q :std_ulogic; +signal rel24_congr_cl_ex5_cmp_d :std_ulogic; +signal rel24_congr_cl_ex5_cmp_q :std_ulogic; +signal rel24_congr_cl_ex6_cmp_d :std_ulogic; +signal rel24_congr_cl_ex6_cmp_q :std_ulogic; +signal relu_congr_cl_ex5_cmp_d :std_ulogic; +signal relu_congr_cl_ex5_cmp_q :std_ulogic; +signal relu_congr_cl_ex6_cmp_d :std_ulogic; +signal relu_congr_cl_ex6_cmp_q :std_ulogic; +signal relu_congr_cl_ex7_cmp_d :std_ulogic; +signal relu_congr_cl_ex7_cmp_q :std_ulogic; +signal rel_ex5_watchSet_coll :std_ulogic; +signal rel_ex6_watchSet_coll :std_ulogic; +signal rel_ex7_watchSet_coll :std_ulogic; +signal rel_coll_val :std_ulogic; +signal relu_dir_data :std_ulogic_vector(2 to 5); +signal rel_pri_byp_sel :std_ulogic_vector(0 to 2); +signal rel_byp_dir_data :std_ulogic_vector(2 to 5); +signal rel_watchSet_coll_tid :std_ulogic_vector(0 to 3); +signal lost_watch_evict_val_d :std_ulogic_vector(0 to 3); +signal lost_watch_evict_val_q :std_ulogic_vector(0 to 3); +signal dcpar_err_lock_lost :std_ulogic_vector(0 to 7); +signal dirpar_err_lock_lost :std_ulogic_vector(0 to 7); +signal ex3_dir_perr_val :std_ulogic; +signal ex3_dir_multihit_val :std_ulogic; +signal ex4_dir_err_val_d :std_ulogic; +signal ex4_dir_err_val_q :std_ulogic; +signal ex5_dir_err_val_d :std_ulogic; +signal ex5_dir_err_val_q :std_ulogic; +signal ex6_dir_err_val_d :std_ulogic; +signal ex6_dir_err_val_q :std_ulogic; +signal derr2_stg_act_d :std_ulogic; +signal derr2_stg_act_q :std_ulogic; +signal derr3_stg_act_d :std_ulogic; +signal derr3_stg_act_q :std_ulogic; +signal derr4_stg_act_d :std_ulogic; +signal derr4_stg_act_q :std_ulogic; +signal derr5_stg_act_d :std_ulogic; +signal derr5_stg_act_q :std_ulogic; +signal ex4_err_det_way_d :std_ulogic_vector(0 to 7); +signal ex4_err_det_way_q :std_ulogic_vector(0 to 7); +signal ex4_perr_lck_lost_d :std_ulogic; +signal ex4_perr_lck_lost_q :std_ulogic; +signal ex4_perr_watch_lost_d :std_ulogic_vector(0 to 3); +signal ex4_perr_watch_lost_q :std_ulogic_vector(0 to 3); +signal dcperr_lock_lost_d :std_ulogic; +signal dcperr_lock_lost_q :std_ulogic; +signal ex4_dir_multihit_val_b_q :std_ulogic; +signal ex4_dir_multihit_val :std_ulogic; +signal binv4_ex4_lock_set :std_ulogic; +signal binv4_ex4_thrd_watch :std_ulogic_vector(0 to 3); +signal ex4_multihit_watch_lost :std_ulogic_vector(0 to 3); +signal ex4_multihit_lock_lost :std_ulogic; +signal ex3_watch_chk_d :std_ulogic; +signal ex3_watch_chk_q :std_ulogic; +signal ex4_watch_chk_d :std_ulogic; +signal ex4_watch_chk_q :std_ulogic; +signal ex5_watch_chk_d :std_ulogic; +signal ex5_watch_chk_q :std_ulogic; +signal ex5_watch_chk_cplt :std_ulogic; +signal ex5_watch_chk_succ :std_ulogic; +signal ex5_watch_dup_set :std_ulogic; +signal hit_and_01_b :std_ulogic; +signal hit_and_23_b :std_ulogic; +signal hit_and_45_b :std_ulogic; +signal hit_and_67_b :std_ulogic; +signal hit_or_01_b :std_ulogic; +signal hit_or_23_b :std_ulogic; +signal hit_or_45_b :std_ulogic; +signal hit_or_67_b :std_ulogic; +signal hit_or_13_b :std_ulogic; +signal hit_or_57_b :std_ulogic; +signal hit_or_0123 :std_ulogic; +signal hit_or_4567 :std_ulogic; +signal hit_or_1357 :std_ulogic; +signal hit_or_2367 :std_ulogic; +signal hit_and_0123 :std_ulogic; +signal hit_and_4567 :std_ulogic; +signal multi_hit_err2_0 :std_ulogic; +signal multi_hit_err2_1 :std_ulogic; +signal hit_or_01234567_b :std_ulogic; +signal ex3_dir_multihit_val_0 :std_ulogic; +signal ex3_dir_multihit_val_1 :std_ulogic; +signal ex3_dir_multihit_val_b :std_ulogic; +signal multi_hit_err3_b :std_ulogic_vector(0 to 2); +signal hit_enc_b :std_ulogic_vector(0 to 2); +signal ex3_l_fld_b1_d :std_ulogic; +signal ex3_l_fld_b1_q :std_ulogic; +signal binv4_ex4_way_upd :std_ulogic_vector(0 to 7); +signal binv5_ex5_way_upd :std_ulogic_vector(0 to 7); +signal binv6_ex6_way_upd :std_ulogic_vector(0 to 7); +signal binv7_ex7_way_upd_d :std_ulogic_vector(0 to 7); +signal binv7_ex7_way_upd_q :std_ulogic_vector(0 to 7); +signal binv4_ex4_dir_data :std_ulogic_vector(1 to 5); +signal binv5_ex5_dir_data_d :std_ulogic_vector(1 to 5); +signal binv5_ex5_dir_data_q :std_ulogic_vector(1 to 5); +signal binv6_ex6_dir_data_d :std_ulogic_vector(1 to 5); +signal binv6_ex6_dir_data_q :std_ulogic_vector(1 to 5); +signal binv7_ex7_dir_data_d :std_ulogic_vector(1 to 5); +signal binv7_ex7_dir_data_q :std_ulogic_vector(1 to 5); +signal binv4_inval_lck :std_ulogic; +signal binv4_inval_watch :std_ulogic_vector(0 to 3); +signal binv4_coll_val :std_ulogic; +signal binv4_ex5_coll :std_ulogic; +signal binv4_ex6_coll :std_ulogic; +signal binv4_ex7_coll :std_ulogic; +signal binv4_pri_byp_sel :std_ulogic_vector(0 to 2); +signal binv4_byp_dir_data :std_ulogic_vector(1 to 5); +signal binv5_inval_lock_val_d :std_ulogic; +signal binv5_inval_lock_val_q :std_ulogic; +signal binv5_inval_watch_val_d :std_ulogic_vector(0 to 3); +signal binv5_inval_watch_val_q :std_ulogic_vector(0 to 3); +signal binv5_ex5_lost_watch_upd :std_ulogic_vector(0 to 3); +signal dci_watch_lost :std_ulogic_vector(0 to 3); +signal ex3_xuop_upd_dir :std_ulogic; +signal binv3_ex3_xuop_upd :std_ulogic; +signal binv4_ex4_xuop_upd_d :std_ulogic; +signal binv4_ex4_xuop_upd_q :std_ulogic; +signal ex3_dir_acc_val :std_ulogic; +signal binv3_ex3_dir_val :std_ulogic; +signal binv4_ex4_dir_val_d :std_ulogic; +signal binv4_ex4_dir_val_q :std_ulogic; +signal ex3_l1hit :std_ulogic; +signal ex3_l1miss :std_ulogic; +signal ex4_snd_ld_l2_q :std_ulogic; +signal ex4_ldq_full_flush_b_q :std_ulogic; +signal rel_in_prog_stg1_d :std_ulogic; +signal rel_in_prog_stg1_q :std_ulogic; +signal rel_in_prog_stg2_d :std_ulogic; +signal rel_in_prog_stg2_q :std_ulogic; +signal rel_in_prog_stg3_d :std_ulogic; +signal rel_in_prog_stg3_q :std_ulogic; +signal rel_in_prog_stg4_d :std_ulogic; +signal rel_in_prog_stg4_q :std_ulogic; +signal rel_in_prog_stg5_d :std_ulogic; +signal rel_in_prog_stg5_q :std_ulogic; +signal ex4_instr_enc_d :std_ulogic_vector(0 to 3); +signal ex4_instr_enc_q :std_ulogic_vector(0 to 3); +signal ex4_wclr_all_val_d :std_ulogic; +signal ex4_wclr_all_val_q :std_ulogic; +signal ex5_wclr_all_val_d :std_ulogic; +signal ex5_wclr_all_val_q :std_ulogic; +signal ex6_wclr_all_val_d :std_ulogic; +signal ex6_wclr_all_val_q :std_ulogic; +signal ex3_wclr_all_upd_val :std_ulogic; +signal ex4_wclr_all_upd_val :std_ulogic; +signal ex5_wclr_all_upd_val :std_ulogic; +signal ex6_wclr_all_upd_val :std_ulogic; +signal ex3_wclr_all_upd_d :std_ulogic; +signal ex3_wclr_all_upd_q :std_ulogic; +signal ex4_n_lsu_ddmh_flush_b_d :std_ulogic_vector(0 to 3); +signal ex4_n_lsu_ddmh_flush_b_q :std_ulogic_vector(0 to 3); +signal ex3_xuop_up_addr_b :std_ulogic_vector(0 to 2); +signal rel_dcarr_addr_sel :std_ulogic_vector(0 to 2); +signal rel_dcarr_addr_sel_b :std_ulogic_vector(0 to 2); +signal dcarr_up_way_addr_q :std_ulogic_vector(0 to 2); +signal rel4_l1dump_val_q :std_ulogic; +signal rel4_l1dump_watch :std_ulogic; +signal lost_watch_l1dump :std_ulogic_vector(0 to 3); +signal my_lclk :clk_logic; +signal my_d1clk :std_ulogic; +signal my_d2clk :std_ulogic; +signal my_multihit_lclk :clk_logic; +signal my_multihit_d1clk :std_ulogic; +signal my_multihit_d2clk :std_ulogic; +signal my_ddmh_lclk :clk_logic; +signal my_ddmh_d1clk :std_ulogic; +signal my_ddmh_d2clk :std_ulogic; +signal ex4_miss_siv :std_ulogic; +signal ex4_miss_sov :std_ulogic; +signal my_spare0_lclk :clk_logic; +signal my_spare0_d1clk :std_ulogic; +signal my_spare0_d2clk :std_ulogic; +signal my_spare0_latches_d :std_ulogic_vector(0 to 16); +signal my_spare0_latches_q :std_ulogic_vector(0 to 16); +signal my_spare1_lclk :clk_logic; +signal my_spare1_d1clk :std_ulogic; +signal my_spare1_d2clk :std_ulogic; +signal my_spare1_latches_d :std_ulogic_vector(0 to 15); +signal my_spare1_latches_q :std_ulogic_vector(0 to 15); +signal tiup :std_ulogic; +signal siv :std_ulogic_vector(0 to scan_right); +signal sov :std_ulogic_vector(0 to scan_right); + BEGIN --@@ START OF EXECUTABLE CODE FOR XUQ_LSU_DIR_VAL32 + +tiup <= '1'; +inv2_val_d <= inv1_val and not spr_xucr0_dcdis; +back_inval_stg2 <= inv2_val_q; +rel_val_stg1 <= rel1_val; +rel_val_stg3 <= rel3_val; +rel_set_val <= rel4_set_val; +lock_flash_clear_d <= xu_lsu_spr_xucr0_clfc; +lock_flash_clear_val_d <= lock_flash_clear_q; +dci_compl_d <= xu_lsu_dci; +dci_inval_all_d <= dci_compl_q; +lock_finval <= dci_inval_all_q or lock_flash_clear_val_q; +inj_dir_multihit_d <= pc_xu_inj_dcachedir_multihit; +ex3_l_fld_b1_d <= ex2_l_fld(1); +tagA_hit <= ex3_way_cmp_a; +rel_wayA_clr <= rel_way_clr_a; +rel_wayA_set <= rel_way_wen_a; +tagB_hit <= ex3_way_cmp_b; +rel_wayB_clr <= rel_way_clr_b; +rel_wayB_set <= rel_way_wen_b; +tagC_hit <= ex3_way_cmp_c; +rel_wayC_clr <= rel_way_clr_c; +rel_wayC_set <= rel_way_wen_c; +tagD_hit <= ex3_way_cmp_d; +rel_wayD_clr <= rel_way_clr_d; +rel_wayD_set <= rel_way_wen_d; +tagE_hit <= ex3_way_cmp_e; +rel_wayE_clr <= rel_way_clr_e; +rel_wayE_set <= rel_way_wen_e; +tagF_hit <= ex3_way_cmp_f; +rel_wayF_clr <= rel_way_clr_f; +rel_wayF_set <= rel_way_wen_f; +tagG_hit <= ex3_way_cmp_g; +rel_wayG_clr <= rel_way_clr_g; +rel_wayG_set <= rel_way_wen_g; +tagH_hit <= ex3_way_cmp_h; +rel_wayH_clr <= rel_way_clr_h; +rel_wayH_set <= rel_way_wen_h; +ex3_c_acc <= ex3_cache_en; +-- #################################################### +-- Stage ACT Pipes +-- #################################################### +binv1_ex1_stg_act <= binv1_stg_act or ex1_stg_act; +binv2_ex2_stg_act <= binv2_stg_act or ex2_stg_act; +binv3_ex3_stg_act <= binv3_stg_act or ex3_stg_act; +binv4_ex4_stg_act <= binv4_stg_act or ex4_stg_act; +binv5_ex5_stg_act <= binv5_stg_act or ex5_stg_act; +binv2_ex2_val_stg_act <= derr2_stg_act_q or binv2_stg_act or ex2_stg_act; +binv3_ex3_val_stg_act <= derr3_stg_act_q or binv3_stg_act or ex3_stg_act; +binv4_ex4_val_stg_act <= derr4_stg_act_q or binv4_stg_act or ex4_stg_act; +binv5_ex5_val_stg_act <= derr5_stg_act_q or binv5_stg_act or ex5_stg_act; +rel1_perr_stg_act <= rel1_stg_act or dcpar_err_stg1_act_q; +rel2_perr_stg_act <= rel2_stg_act or dcpar_err_stg2_act_q; +rel3_perr_stg_act_d <= rel2_perr_stg_act; +rel4_perr_stg_act_d <= rel3_perr_stg_act_q; +-- #################################################### +-- Dcache Number of Cachelines Configurations +-- #################################################### +-- EX2 Stage +ex1_congr_cl <= ex1_p_addr; +cl64size : if (cl_size=6) generate +begin + rel_early_congr_cl(2 TO 6) <= rel_addr_early(64-(dc_size-3) to 63-cl_size-1); +rel_early_congr_cl(7) <= rel_addr_early(63-cl_size) or spr_xucr0_cls; +end generate cl64size; +cl32size : if (cl_size=5) generate +begin + rel_early_congr_cl(2 TO 5) <= rel_addr_early(64-(dc_size-3) to 63-cl_size-2); +rel_early_congr_cl(6) <= rel_addr_early(63-cl_size-1) or spr_xucr0_cls; +rel_early_congr_cl(7) <= rel_addr_early(63-cl_size); +end generate cl32size; +-- #################################################### +-- Congruence Class Address Select +-- Port0 => Execution Pipe or Back-Invalidate +-- Port1 => Reload or DC Parity Error Recovery +-- #################################################### +-- Port0 +-- = '1' => Select Back-Invalidate +-- = '0' => Select Execution Op +ex2_congr_cl_d <= ex1_congr_cl; +ex3_congr_cl_d <= ex2_congr_cl_q; +ex4_congr_cl_d <= ex3_congr_cl_q; +ex5_congr_cl_d <= ex4_congr_cl_q; +ex6_congr_cl_d <= ex5_congr_cl_q; +-- Port1 +-- = '1' => Select DC Parity Error Recovery +-- = '0' => Select Reload +with rel_in_progress select + rel_congr_cl_d <= rel_early_congr_cl when '1', + dcpar_err_congr_cl when others; +-- Reload Invalidate Stages +rel_val_stg2_d <= rel_val_stg1; +rel_val_clr_d <= rel_val_stg2_q or dcpar_err_stg2_q; +-- Reload Validate Stages +rel_val_stg4_d <= rel_val_stg3; +rel_val_stg4 <= rel_val_stg4_q and not rel4_recirc_val; +rel_val_set <= rel_val_stg4 and rel_set_val; +-- Reload Back-Invalidated +rel_binv_stg4_d <= rel_back_inval; +-- Reload Lock Cache-Line +rel_lock_set_d <= rel_lock_en; +rel_l1dump_cslc_d <= rel_l1dump_cslc; +-- Reload Lost Lock due to Back-Invalidate of loadmissQ entry +rel_no_ovr_lock <= rel_wayA_set or rel_wayB_set or rel_wayC_set or rel_wayD_set or + rel_wayE_set or rel_wayF_set or rel_wayG_set or rel_wayH_set; +rel_lock_lost <= rel_lock_set_q and rel_val_stg4 and rel_no_ovr_lock and rel_binv_stg4_q and not rel_set_val; +-- Reload Watch Cache-Line +rel_watch_set_d <= rel_watch_en; +rel_thrd_id_d <= rel_thrd_id; +-- Reload Lost Watch due to Back-Invalidate of loadmissQ entry +rel_watch_lost <= gate(rel_thrd_id_q, (rel_watch_set_q and rel_val_stg4 and rel_binv_stg4_q and not rel_set_val)); +-- Reload Port is updated when a Reload is invalidating a line, a Reload is setting a line, or Parity Error Recovery +rel_val_stg24 <= rel_val_stg2_q or rel_val_set or dcpar_err_stg2_q; +rel_val_stgu_d <= rel_val_stg24; +rel_port_wren_d <= rel_val_stgu_q; +rel_port_upd_d <= rel_val_stgu_q; +rel_in_prog_stg1_d <= ldq_rel1_early_v or ldq_rel3_early_v; +rel_in_prog_stg2_d <= rel_in_prog_stg1_q; +rel_in_prog_stg3_d <= rel_in_prog_stg2_q; +rel_in_prog_stg4_d <= rel_in_prog_stg3_q; +rel_in_prog_stg5_d <= rel_in_prog_stg4_q; +-- Used to block Parity Recovery +rel_in_progress <= ldq_rel1_early_v or ldq_rel3_early_v or rel_in_prog_stg1_q or rel_in_prog_stg2_q or + rel_in_prog_stg3_q or rel_in_prog_stg4_q or rel_in_prog_stg5_q; +rel_in_progress_d <= rel_in_progress; +-- Back-Invalidate Stages +back_inval_stg3_d <= back_inval_stg2; +back_inval_stg4_d <= back_inval_stg3_q; +back_inval_stg5_d <= back_inval_stg4_q; +-- EX1 STAGE +ex2_thrd_id_d <= ex1_thrd_id; +-- EX2 STAGE +ex3_store_instr_d <= ex2_store_instr and not ex2_stg_flush; +ex3_flush_cline_d <= ex2_is_inval_op and not ex2_stg_flush; +ex3_lock_set_d <= ex2_lock_set and not ex2_stg_flush; +ex4_lock_set_d <= ex3_lock_set_q and not ex3_stg_flush; +ex5_lock_set_d <= ex4_lock_set_q and not ex4_stg_flush; +ex3_lock_clr_d <= ex2_lock_clr and not ex2_stg_flush; +ex3_thrd_id_d <= ex2_thrd_id_q; +ex3_watch_set_d <= ex2_ldawx_instr and not ex2_stg_flush; +ex3_watch_clr_d <= ex2_wclr_instr and not ex2_stg_flush; +ex2_watch_clr_all <= ex2_wclr_instr and not ex2_l_fld(0); +ex2_watch_clr_one <= ex2_wclr_instr and ex2_l_fld(0); +ex3_watch_clr_all_d <= ex2_watch_clr_all and not ex2_stg_flush; +ex3_watch_chk_d <= ex2_wchk_val and not ex2_stg_flush; +ex3_xuop_val_d <= (ex2_lock_clr or ex2_lock_set or ex2_ldawx_instr or ex2_watch_clr_one or ex2_store_instr) and not ex2_stg_flush; +-- EX3 STAGE +ex4_l_fld_b1_d <= ex3_l_fld_b1_q; +ex3_watch_clr_all <= gate(ex3_thrd_id_q, ex3_watch_clr_all_q); +ex4_wclr_all_val_d <= ex3_watch_clr_all_q and not ex3_stg_flush; +ex5_wclr_all_val_d <= ex4_wclr_all_val_q and not ex4_stg_flush; +ex6_wclr_all_val_d <= ex5_wclr_all_val_q and not ex5_stg_flush; +ex3_xuop_val <= ((ex3_xuop_val_q and ex3_c_acc) or ex3_flush_cline_q) and not spr_xucr0_dcdis; +ex4_xuop_val_d <= (ex3_xuop_val or ex3_watch_clr_all_q) and not ex3_stg_flush; +ex4_watch_clr_all_d <= gate(ex3_watch_clr_all, (not (ex3_stg_flush or spr_xucr0_dcdis))); +ex4_watch_chk_d <= ex3_watch_chk_q and not ex3_stg_flush; +ex4_watch_set_d <= ex3_watch_set_q and not ex3_stg_flush; +ex5_watch_set_d <= ex4_watch_set_q and not ex4_stg_flush; +ex3_xuop_upd_dir <= ex3_flush_cline_q or ex3_lock_clr_q or ex3_lock_set_q or ex3_watch_set_q or ex3_watch_clr_q; +binv3_ex3_xuop_upd <= back_inval_stg3_q or ex3_xuop_val; +binv4_ex4_xuop_upd_d <= binv3_ex3_xuop_upd or ((ex3_xuop_val or ex3_watch_clr_all_q) and not ex3_stg_flush); +ex3_dir_acc_val <= ex3_cache_acc and not ex3_watch_clr_all_q; +binv3_ex3_dir_val <= back_inval_stg3_q or ex3_dir_acc_val; +binv4_ex4_dir_val_d <= back_inval_stg3_q or (ex3_dir_acc_val and not ex3_stg_flush); +ex4_instr_enc_d(0) <= ex3_watch_clr_q; +ex4_instr_enc_d(1) <= back_inval_stg3_q or ex3_lock_set_q or ex3_lock_clr_q or ex3_watch_set_q; +ex4_instr_enc_d(2) <= back_inval_stg3_q or ex3_store_instr_q or ex3_watch_set_q; +ex4_instr_enc_d(3) <= back_inval_stg3_q or ex3_lock_clr_q or ex3_flush_cline_q or ex3_watch_clr_all_q; +-- EX4 STAGE +ex4_xuop_val <= ex4_xuop_val_q and not ex4_stg_flush; +ex4_thrd_id_d <= ex3_thrd_id_q; +-- EX5 STAGE +ex5_xuop_val_d <= ex4_xuop_val; +ex5_xuop_val <= ex5_xuop_val_q and not ex5_stg_flush; +ex5_xuop_p0_upd_d <= ex4_xuop_val; +ex5_watch_chk_d <= ex4_watch_chk_q and not ex4_stg_flush; +ex5_thrd_id_d <= ex4_thrd_id_q; +-- Reload Congruence Class +rel24_congr_cl_d <= rel_congr_cl_q; +relu_congr_cl_d <= rel24_congr_cl_q; +relu_s_congr_cl_d <= relu_congr_cl_q; +-- Load Hit Valid +ex6_ld_valid_d <= ex5_load_op_hit and not ex5_stg_flush; +-- #################################################### +-- Execution Directory Read +-- #################################################### +-- Execution Path Directory Valid and Line Lock Bits Muxing +-- Select Congruence Class Way A +with ex2_congr_cl_q select + arr_wayA_val <= + congr_cl0_wA_q when "000000", + congr_cl1_wA_q when "000001", + congr_cl2_wA_q when "000010", + congr_cl3_wA_q when "000011", + congr_cl4_wA_q when "000100", + congr_cl5_wA_q when "000101", + congr_cl6_wA_q when "000110", + congr_cl7_wA_q when "000111", + congr_cl8_wA_q when "001000", + congr_cl9_wA_q when "001001", + congr_cl10_wA_q when "001010", + congr_cl11_wA_q when "001011", + congr_cl12_wA_q when "001100", + congr_cl13_wA_q when "001101", + congr_cl14_wA_q when "001110", + congr_cl15_wA_q when "001111", + congr_cl16_wA_q when "010000", + congr_cl17_wA_q when "010001", + congr_cl18_wA_q when "010010", + congr_cl19_wA_q when "010011", + congr_cl20_wA_q when "010100", + congr_cl21_wA_q when "010101", + congr_cl22_wA_q when "010110", + congr_cl23_wA_q when "010111", + congr_cl24_wA_q when "011000", + congr_cl25_wA_q when "011001", + congr_cl26_wA_q when "011010", + congr_cl27_wA_q when "011011", + congr_cl28_wA_q when "011100", + congr_cl29_wA_q when "011101", + congr_cl30_wA_q when "011110", + congr_cl31_wA_q when "011111", + congr_cl32_wA_q when "100000", + congr_cl33_wA_q when "100001", + congr_cl34_wA_q when "100010", + congr_cl35_wA_q when "100011", + congr_cl36_wA_q when "100100", + congr_cl37_wA_q when "100101", + congr_cl38_wA_q when "100110", + congr_cl39_wA_q when "100111", + congr_cl40_wA_q when "101000", + congr_cl41_wA_q when "101001", + congr_cl42_wA_q when "101010", + congr_cl43_wA_q when "101011", + congr_cl44_wA_q when "101100", + congr_cl45_wA_q when "101101", + congr_cl46_wA_q when "101110", + congr_cl47_wA_q when "101111", + congr_cl48_wA_q when "110000", + congr_cl49_wA_q when "110001", + congr_cl50_wA_q when "110010", + congr_cl51_wA_q when "110011", + congr_cl52_wA_q when "110100", + congr_cl53_wA_q when "110101", + congr_cl54_wA_q when "110110", + congr_cl55_wA_q when "110111", + congr_cl56_wA_q when "111000", + congr_cl57_wA_q when "111001", + congr_cl58_wA_q when "111010", + congr_cl59_wA_q when "111011", + congr_cl60_wA_q when "111100", + congr_cl61_wA_q when "111101", + congr_cl62_wA_q when "111110", + congr_cl63_wA_q when others; +p0_arr_wayA_rd <= arr_wayA_val; +-- Select Congruence Class Way B +with ex2_congr_cl_q select + arr_wayB_val <= + congr_cl0_wB_q when "000000", + congr_cl1_wB_q when "000001", + congr_cl2_wB_q when "000010", + congr_cl3_wB_q when "000011", + congr_cl4_wB_q when "000100", + congr_cl5_wB_q when "000101", + congr_cl6_wB_q when "000110", + congr_cl7_wB_q when "000111", + congr_cl8_wB_q when "001000", + congr_cl9_wB_q when "001001", + congr_cl10_wB_q when "001010", + congr_cl11_wB_q when "001011", + congr_cl12_wB_q when "001100", + congr_cl13_wB_q when "001101", + congr_cl14_wB_q when "001110", + congr_cl15_wB_q when "001111", + congr_cl16_wB_q when "010000", + congr_cl17_wB_q when "010001", + congr_cl18_wB_q when "010010", + congr_cl19_wB_q when "010011", + congr_cl20_wB_q when "010100", + congr_cl21_wB_q when "010101", + congr_cl22_wB_q when "010110", + congr_cl23_wB_q when "010111", + congr_cl24_wB_q when "011000", + congr_cl25_wB_q when "011001", + congr_cl26_wB_q when "011010", + congr_cl27_wB_q when "011011", + congr_cl28_wB_q when "011100", + congr_cl29_wB_q when "011101", + congr_cl30_wB_q when "011110", + congr_cl31_wB_q when "011111", + congr_cl32_wB_q when "100000", + congr_cl33_wB_q when "100001", + congr_cl34_wB_q when "100010", + congr_cl35_wB_q when "100011", + congr_cl36_wB_q when "100100", + congr_cl37_wB_q when "100101", + congr_cl38_wB_q when "100110", + congr_cl39_wB_q when "100111", + congr_cl40_wB_q when "101000", + congr_cl41_wB_q when "101001", + congr_cl42_wB_q when "101010", + congr_cl43_wB_q when "101011", + congr_cl44_wB_q when "101100", + congr_cl45_wB_q when "101101", + congr_cl46_wB_q when "101110", + congr_cl47_wB_q when "101111", + congr_cl48_wB_q when "110000", + congr_cl49_wB_q when "110001", + congr_cl50_wB_q when "110010", + congr_cl51_wB_q when "110011", + congr_cl52_wB_q when "110100", + congr_cl53_wB_q when "110101", + congr_cl54_wB_q when "110110", + congr_cl55_wB_q when "110111", + congr_cl56_wB_q when "111000", + congr_cl57_wB_q when "111001", + congr_cl58_wB_q when "111010", + congr_cl59_wB_q when "111011", + congr_cl60_wB_q when "111100", + congr_cl61_wB_q when "111101", + congr_cl62_wB_q when "111110", + congr_cl63_wB_q when others; +p0_arr_wayB_rd <= arr_wayB_val; +-- Select Congruence Class Way C +with ex2_congr_cl_q select + arr_wayC_val <= + congr_cl0_wC_q when "000000", + congr_cl1_wC_q when "000001", + congr_cl2_wC_q when "000010", + congr_cl3_wC_q when "000011", + congr_cl4_wC_q when "000100", + congr_cl5_wC_q when "000101", + congr_cl6_wC_q when "000110", + congr_cl7_wC_q when "000111", + congr_cl8_wC_q when "001000", + congr_cl9_wC_q when "001001", + congr_cl10_wC_q when "001010", + congr_cl11_wC_q when "001011", + congr_cl12_wC_q when "001100", + congr_cl13_wC_q when "001101", + congr_cl14_wC_q when "001110", + congr_cl15_wC_q when "001111", + congr_cl16_wC_q when "010000", + congr_cl17_wC_q when "010001", + congr_cl18_wC_q when "010010", + congr_cl19_wC_q when "010011", + congr_cl20_wC_q when "010100", + congr_cl21_wC_q when "010101", + congr_cl22_wC_q when "010110", + congr_cl23_wC_q when "010111", + congr_cl24_wC_q when "011000", + congr_cl25_wC_q when "011001", + congr_cl26_wC_q when "011010", + congr_cl27_wC_q when "011011", + congr_cl28_wC_q when "011100", + congr_cl29_wC_q when "011101", + congr_cl30_wC_q when "011110", + congr_cl31_wC_q when "011111", + congr_cl32_wC_q when "100000", + congr_cl33_wC_q when "100001", + congr_cl34_wC_q when "100010", + congr_cl35_wC_q when "100011", + congr_cl36_wC_q when "100100", + congr_cl37_wC_q when "100101", + congr_cl38_wC_q when "100110", + congr_cl39_wC_q when "100111", + congr_cl40_wC_q when "101000", + congr_cl41_wC_q when "101001", + congr_cl42_wC_q when "101010", + congr_cl43_wC_q when "101011", + congr_cl44_wC_q when "101100", + congr_cl45_wC_q when "101101", + congr_cl46_wC_q when "101110", + congr_cl47_wC_q when "101111", + congr_cl48_wC_q when "110000", + congr_cl49_wC_q when "110001", + congr_cl50_wC_q when "110010", + congr_cl51_wC_q when "110011", + congr_cl52_wC_q when "110100", + congr_cl53_wC_q when "110101", + congr_cl54_wC_q when "110110", + congr_cl55_wC_q when "110111", + congr_cl56_wC_q when "111000", + congr_cl57_wC_q when "111001", + congr_cl58_wC_q when "111010", + congr_cl59_wC_q when "111011", + congr_cl60_wC_q when "111100", + congr_cl61_wC_q when "111101", + congr_cl62_wC_q when "111110", + congr_cl63_wC_q when others; +p0_arr_wayC_rd <= arr_wayC_val; +-- Select Congruence Class Way D +with ex2_congr_cl_q select + arr_wayD_val <= + congr_cl0_wD_q when "000000", + congr_cl1_wD_q when "000001", + congr_cl2_wD_q when "000010", + congr_cl3_wD_q when "000011", + congr_cl4_wD_q when "000100", + congr_cl5_wD_q when "000101", + congr_cl6_wD_q when "000110", + congr_cl7_wD_q when "000111", + congr_cl8_wD_q when "001000", + congr_cl9_wD_q when "001001", + congr_cl10_wD_q when "001010", + congr_cl11_wD_q when "001011", + congr_cl12_wD_q when "001100", + congr_cl13_wD_q when "001101", + congr_cl14_wD_q when "001110", + congr_cl15_wD_q when "001111", + congr_cl16_wD_q when "010000", + congr_cl17_wD_q when "010001", + congr_cl18_wD_q when "010010", + congr_cl19_wD_q when "010011", + congr_cl20_wD_q when "010100", + congr_cl21_wD_q when "010101", + congr_cl22_wD_q when "010110", + congr_cl23_wD_q when "010111", + congr_cl24_wD_q when "011000", + congr_cl25_wD_q when "011001", + congr_cl26_wD_q when "011010", + congr_cl27_wD_q when "011011", + congr_cl28_wD_q when "011100", + congr_cl29_wD_q when "011101", + congr_cl30_wD_q when "011110", + congr_cl31_wD_q when "011111", + congr_cl32_wD_q when "100000", + congr_cl33_wD_q when "100001", + congr_cl34_wD_q when "100010", + congr_cl35_wD_q when "100011", + congr_cl36_wD_q when "100100", + congr_cl37_wD_q when "100101", + congr_cl38_wD_q when "100110", + congr_cl39_wD_q when "100111", + congr_cl40_wD_q when "101000", + congr_cl41_wD_q when "101001", + congr_cl42_wD_q when "101010", + congr_cl43_wD_q when "101011", + congr_cl44_wD_q when "101100", + congr_cl45_wD_q when "101101", + congr_cl46_wD_q when "101110", + congr_cl47_wD_q when "101111", + congr_cl48_wD_q when "110000", + congr_cl49_wD_q when "110001", + congr_cl50_wD_q when "110010", + congr_cl51_wD_q when "110011", + congr_cl52_wD_q when "110100", + congr_cl53_wD_q when "110101", + congr_cl54_wD_q when "110110", + congr_cl55_wD_q when "110111", + congr_cl56_wD_q when "111000", + congr_cl57_wD_q when "111001", + congr_cl58_wD_q when "111010", + congr_cl59_wD_q when "111011", + congr_cl60_wD_q when "111100", + congr_cl61_wD_q when "111101", + congr_cl62_wD_q when "111110", + congr_cl63_wD_q when others; +p0_arr_wayD_rd <= arr_wayD_val; +-- Select Congruence Class Way E +with ex2_congr_cl_q select + arr_wayE_val <= + congr_cl0_wE_q when "000000", + congr_cl1_wE_q when "000001", + congr_cl2_wE_q when "000010", + congr_cl3_wE_q when "000011", + congr_cl4_wE_q when "000100", + congr_cl5_wE_q when "000101", + congr_cl6_wE_q when "000110", + congr_cl7_wE_q when "000111", + congr_cl8_wE_q when "001000", + congr_cl9_wE_q when "001001", + congr_cl10_wE_q when "001010", + congr_cl11_wE_q when "001011", + congr_cl12_wE_q when "001100", + congr_cl13_wE_q when "001101", + congr_cl14_wE_q when "001110", + congr_cl15_wE_q when "001111", + congr_cl16_wE_q when "010000", + congr_cl17_wE_q when "010001", + congr_cl18_wE_q when "010010", + congr_cl19_wE_q when "010011", + congr_cl20_wE_q when "010100", + congr_cl21_wE_q when "010101", + congr_cl22_wE_q when "010110", + congr_cl23_wE_q when "010111", + congr_cl24_wE_q when "011000", + congr_cl25_wE_q when "011001", + congr_cl26_wE_q when "011010", + congr_cl27_wE_q when "011011", + congr_cl28_wE_q when "011100", + congr_cl29_wE_q when "011101", + congr_cl30_wE_q when "011110", + congr_cl31_wE_q when "011111", + congr_cl32_wE_q when "100000", + congr_cl33_wE_q when "100001", + congr_cl34_wE_q when "100010", + congr_cl35_wE_q when "100011", + congr_cl36_wE_q when "100100", + congr_cl37_wE_q when "100101", + congr_cl38_wE_q when "100110", + congr_cl39_wE_q when "100111", + congr_cl40_wE_q when "101000", + congr_cl41_wE_q when "101001", + congr_cl42_wE_q when "101010", + congr_cl43_wE_q when "101011", + congr_cl44_wE_q when "101100", + congr_cl45_wE_q when "101101", + congr_cl46_wE_q when "101110", + congr_cl47_wE_q when "101111", + congr_cl48_wE_q when "110000", + congr_cl49_wE_q when "110001", + congr_cl50_wE_q when "110010", + congr_cl51_wE_q when "110011", + congr_cl52_wE_q when "110100", + congr_cl53_wE_q when "110101", + congr_cl54_wE_q when "110110", + congr_cl55_wE_q when "110111", + congr_cl56_wE_q when "111000", + congr_cl57_wE_q when "111001", + congr_cl58_wE_q when "111010", + congr_cl59_wE_q when "111011", + congr_cl60_wE_q when "111100", + congr_cl61_wE_q when "111101", + congr_cl62_wE_q when "111110", + congr_cl63_wE_q when others; +p0_arr_wayE_rd <= arr_wayE_val; +-- Select Congruence Class Way F +with ex2_congr_cl_q select + arr_wayF_val <= + congr_cl0_wF_q when "000000", + congr_cl1_wF_q when "000001", + congr_cl2_wF_q when "000010", + congr_cl3_wF_q when "000011", + congr_cl4_wF_q when "000100", + congr_cl5_wF_q when "000101", + congr_cl6_wF_q when "000110", + congr_cl7_wF_q when "000111", + congr_cl8_wF_q when "001000", + congr_cl9_wF_q when "001001", + congr_cl10_wF_q when "001010", + congr_cl11_wF_q when "001011", + congr_cl12_wF_q when "001100", + congr_cl13_wF_q when "001101", + congr_cl14_wF_q when "001110", + congr_cl15_wF_q when "001111", + congr_cl16_wF_q when "010000", + congr_cl17_wF_q when "010001", + congr_cl18_wF_q when "010010", + congr_cl19_wF_q when "010011", + congr_cl20_wF_q when "010100", + congr_cl21_wF_q when "010101", + congr_cl22_wF_q when "010110", + congr_cl23_wF_q when "010111", + congr_cl24_wF_q when "011000", + congr_cl25_wF_q when "011001", + congr_cl26_wF_q when "011010", + congr_cl27_wF_q when "011011", + congr_cl28_wF_q when "011100", + congr_cl29_wF_q when "011101", + congr_cl30_wF_q when "011110", + congr_cl31_wF_q when "011111", + congr_cl32_wF_q when "100000", + congr_cl33_wF_q when "100001", + congr_cl34_wF_q when "100010", + congr_cl35_wF_q when "100011", + congr_cl36_wF_q when "100100", + congr_cl37_wF_q when "100101", + congr_cl38_wF_q when "100110", + congr_cl39_wF_q when "100111", + congr_cl40_wF_q when "101000", + congr_cl41_wF_q when "101001", + congr_cl42_wF_q when "101010", + congr_cl43_wF_q when "101011", + congr_cl44_wF_q when "101100", + congr_cl45_wF_q when "101101", + congr_cl46_wF_q when "101110", + congr_cl47_wF_q when "101111", + congr_cl48_wF_q when "110000", + congr_cl49_wF_q when "110001", + congr_cl50_wF_q when "110010", + congr_cl51_wF_q when "110011", + congr_cl52_wF_q when "110100", + congr_cl53_wF_q when "110101", + congr_cl54_wF_q when "110110", + congr_cl55_wF_q when "110111", + congr_cl56_wF_q when "111000", + congr_cl57_wF_q when "111001", + congr_cl58_wF_q when "111010", + congr_cl59_wF_q when "111011", + congr_cl60_wF_q when "111100", + congr_cl61_wF_q when "111101", + congr_cl62_wF_q when "111110", + congr_cl63_wF_q when others; +p0_arr_wayF_rd <= arr_wayF_val; +-- Select Congruence Class Way G +with ex2_congr_cl_q select + arr_wayG_val <= + congr_cl0_wG_q when "000000", + congr_cl1_wG_q when "000001", + congr_cl2_wG_q when "000010", + congr_cl3_wG_q when "000011", + congr_cl4_wG_q when "000100", + congr_cl5_wG_q when "000101", + congr_cl6_wG_q when "000110", + congr_cl7_wG_q when "000111", + congr_cl8_wG_q when "001000", + congr_cl9_wG_q when "001001", + congr_cl10_wG_q when "001010", + congr_cl11_wG_q when "001011", + congr_cl12_wG_q when "001100", + congr_cl13_wG_q when "001101", + congr_cl14_wG_q when "001110", + congr_cl15_wG_q when "001111", + congr_cl16_wG_q when "010000", + congr_cl17_wG_q when "010001", + congr_cl18_wG_q when "010010", + congr_cl19_wG_q when "010011", + congr_cl20_wG_q when "010100", + congr_cl21_wG_q when "010101", + congr_cl22_wG_q when "010110", + congr_cl23_wG_q when "010111", + congr_cl24_wG_q when "011000", + congr_cl25_wG_q when "011001", + congr_cl26_wG_q when "011010", + congr_cl27_wG_q when "011011", + congr_cl28_wG_q when "011100", + congr_cl29_wG_q when "011101", + congr_cl30_wG_q when "011110", + congr_cl31_wG_q when "011111", + congr_cl32_wG_q when "100000", + congr_cl33_wG_q when "100001", + congr_cl34_wG_q when "100010", + congr_cl35_wG_q when "100011", + congr_cl36_wG_q when "100100", + congr_cl37_wG_q when "100101", + congr_cl38_wG_q when "100110", + congr_cl39_wG_q when "100111", + congr_cl40_wG_q when "101000", + congr_cl41_wG_q when "101001", + congr_cl42_wG_q when "101010", + congr_cl43_wG_q when "101011", + congr_cl44_wG_q when "101100", + congr_cl45_wG_q when "101101", + congr_cl46_wG_q when "101110", + congr_cl47_wG_q when "101111", + congr_cl48_wG_q when "110000", + congr_cl49_wG_q when "110001", + congr_cl50_wG_q when "110010", + congr_cl51_wG_q when "110011", + congr_cl52_wG_q when "110100", + congr_cl53_wG_q when "110101", + congr_cl54_wG_q when "110110", + congr_cl55_wG_q when "110111", + congr_cl56_wG_q when "111000", + congr_cl57_wG_q when "111001", + congr_cl58_wG_q when "111010", + congr_cl59_wG_q when "111011", + congr_cl60_wG_q when "111100", + congr_cl61_wG_q when "111101", + congr_cl62_wG_q when "111110", + congr_cl63_wG_q when others; +p0_arr_wayG_rd <= arr_wayG_val; +-- Select Congruence Class Way H +with ex2_congr_cl_q select + arr_wayH_val <= + congr_cl0_wH_q when "000000", + congr_cl1_wH_q when "000001", + congr_cl2_wH_q when "000010", + congr_cl3_wH_q when "000011", + congr_cl4_wH_q when "000100", + congr_cl5_wH_q when "000101", + congr_cl6_wH_q when "000110", + congr_cl7_wH_q when "000111", + congr_cl8_wH_q when "001000", + congr_cl9_wH_q when "001001", + congr_cl10_wH_q when "001010", + congr_cl11_wH_q when "001011", + congr_cl12_wH_q when "001100", + congr_cl13_wH_q when "001101", + congr_cl14_wH_q when "001110", + congr_cl15_wH_q when "001111", + congr_cl16_wH_q when "010000", + congr_cl17_wH_q when "010001", + congr_cl18_wH_q when "010010", + congr_cl19_wH_q when "010011", + congr_cl20_wH_q when "010100", + congr_cl21_wH_q when "010101", + congr_cl22_wH_q when "010110", + congr_cl23_wH_q when "010111", + congr_cl24_wH_q when "011000", + congr_cl25_wH_q when "011001", + congr_cl26_wH_q when "011010", + congr_cl27_wH_q when "011011", + congr_cl28_wH_q when "011100", + congr_cl29_wH_q when "011101", + congr_cl30_wH_q when "011110", + congr_cl31_wH_q when "011111", + congr_cl32_wH_q when "100000", + congr_cl33_wH_q when "100001", + congr_cl34_wH_q when "100010", + congr_cl35_wH_q when "100011", + congr_cl36_wH_q when "100100", + congr_cl37_wH_q when "100101", + congr_cl38_wH_q when "100110", + congr_cl39_wH_q when "100111", + congr_cl40_wH_q when "101000", + congr_cl41_wH_q when "101001", + congr_cl42_wH_q when "101010", + congr_cl43_wH_q when "101011", + congr_cl44_wH_q when "101100", + congr_cl45_wH_q when "101101", + congr_cl46_wH_q when "101110", + congr_cl47_wH_q when "101111", + congr_cl48_wH_q when "110000", + congr_cl49_wH_q when "110001", + congr_cl50_wH_q when "110010", + congr_cl51_wH_q when "110011", + congr_cl52_wH_q when "110100", + congr_cl53_wH_q when "110101", + congr_cl54_wH_q when "110110", + congr_cl55_wH_q when "110111", + congr_cl56_wH_q when "111000", + congr_cl57_wH_q when "111001", + congr_cl58_wH_q when "111010", + congr_cl59_wH_q when "111011", + congr_cl60_wH_q when "111100", + congr_cl61_wH_q when "111101", + congr_cl62_wH_q when "111110", + congr_cl63_wH_q when others; +p0_arr_wayH_rd <= arr_wayH_val; +-- #################################################### +-- Execution/Back-Invalidate Pipe Bypass +-- #################################################### +-- Determine if there is any updates in later stages to the same congruence class +congr_cl_ex2_ex3_cmp_d <= (ex1_congr_cl = ex2_congr_cl_q); +congr_cl_ex2_ex4_cmp_d <= (ex1_congr_cl = ex3_congr_cl_q); +congr_cl_ex2_ex5_cmp_d <= (ex1_congr_cl = ex4_congr_cl_q); +congr_cl_ex2_ex6_cmp_d <= (ex1_congr_cl = ex5_congr_cl_q); +congr_cl_ex2_relu_cmp_d <= (ex1_congr_cl = rel24_congr_cl_q); +congr_cl_ex2_relu_s_cmp_d <= (ex1_congr_cl = relu_congr_cl_q); +congr_cl_ex2_rel_upd_cmp_d <= (ex1_congr_cl = relu_s_congr_cl_q); +congr_cl_ex2_p0_cmp <= congr_cl_ex2_ex6_cmp_q and p0_wren_cpy_q; +congr_cl_ex2_p1_cmp <= congr_cl_ex2_rel_upd_cmp_q and p1_wren_cpy_q; +-- Determine Bypass from later stages +ex3_thrd_m_d <= (ex1_thrd_id = ex2_thrd_id_q); +ex4_thrd_m_d <= (ex1_thrd_id = ex3_thrd_id_q); +ex5_thrd_m_d <= (ex1_thrd_id = ex4_thrd_id_q); +ex6_thrd_m_d <= (ex1_thrd_id = ex5_thrd_id_q); +congr_cl_ex2_ex3_m <= congr_cl_ex2_ex3_cmp_q and ((ex3_xuop_val and ex3_thrd_m_q) or back_inval_stg3_q) and not inv2_val_q; +congr_cl_ex2_ex4_m <= congr_cl_ex2_ex4_cmp_q and ((ex4_xuop_val_q and ex4_thrd_m_q) or back_inval_stg4_q) and not inv2_val_q; +congr_cl_ex2_ex5_m <= congr_cl_ex2_ex5_cmp_q and ((ex5_xuop_p0_upd_q and ex5_thrd_m_q) or back_inval_stg5_q) and not inv2_val_q; +congr_cl_ex2_relu_m <= congr_cl_ex2_relu_cmp_q and rel_val_stgu_q; +congr_cl_ex2_relu_s_m <= congr_cl_ex2_relu_s_cmp_q and p1_upd_val; +-- WayA Bypass Calculation +congr_cl_ex2_wayA_byp(1) <= congr_cl_ex2_ex3_m and ex3_wayA_hit; +congr_cl_ex2_wayA_byp(2) <= congr_cl_ex2_relu_m and reload_wayA_upd_q; +congr_cl_ex2_wayA_byp(3) <= congr_cl_ex2_ex4_m and binv_wayA_upd_q; +congr_cl_ex2_wayA_byp(4) <= congr_cl_ex2_relu_s_m and reload_wayA_upd2_q; +congr_cl_ex2_wayA_byp(5) <= congr_cl_ex2_ex5_m and binv_wayA_upd2_q; +congr_cl_ex2_wayA_byp(6) <= congr_cl_ex2_p1_cmp and reload_wayA_upd3_q; +congr_cl_ex2_wayA_byp(7) <= congr_cl_ex2_p0_cmp and binv_wayA_upd3_q; +-- WayA Bypass Valid +ex3_wayA_fxubyp_val_d <= congr_cl_ex2_wayA_byp(1) or congr_cl_ex2_wayA_byp(3) or + congr_cl_ex2_wayA_byp(5) or congr_cl_ex2_wayA_byp(7); +ex3_wayA_relbyp_val_d <= congr_cl_ex2_wayA_byp(2) or congr_cl_ex2_wayA_byp(4) or + congr_cl_ex2_wayA_byp(6); +ex4_wayA_fxubyp_val_d <= ex3_wayA_fxubyp_val_q; +ex4_wayA_relbyp_val_d <= ex3_wayA_relbyp_val_q; +ex4_wayA_byp_sel <= ex4_wayA_fxubyp_val_q & ex4_wayA_relbyp_val_q; +-- Late Stages Priority Selection +congr_cl_ex2_wayA_sel(2) <= congr_cl_ex2_wayA_byp(2); +congr_cl_ex2_wayA_sel(3) <= congr_cl_ex2_wayA_byp(3) and not congr_cl_ex2_wayA_byp(2); +congr_cl_ex2_wayA_sel(4) <= congr_cl_ex2_wayA_byp(4) and not or_reduce(congr_cl_ex2_wayA_byp(2 to 3)); +congr_cl_ex2_wayA_sel(5) <= congr_cl_ex2_wayA_byp(5) and not or_reduce(congr_cl_ex2_wayA_byp(2 to 4)); +congr_cl_ex2_wayA_sel(6) <= congr_cl_ex2_wayA_byp(6) and not or_reduce(congr_cl_ex2_wayA_byp(2 to 5)); +congr_cl_ex2_wayA_sel(7) <= congr_cl_ex2_wayA_byp(7) and not or_reduce(congr_cl_ex2_wayA_byp(2 to 6)); +-- ArrayRead/LATE Stage Priority Selection +wayA_late_sel <= or_reduce(congr_cl_ex2_wayA_byp(2 to 7)); +wayA_later_stg_pri <= gate(p0_arr_wayA_rd, not wayA_late_sel) or + gate(reload_wayA_q, congr_cl_ex2_wayA_sel(2)) or + gate(flush_wayA_q, congr_cl_ex2_wayA_sel(3)) or + gate(reload_wayA_data_q, congr_cl_ex2_wayA_sel(4)) or + gate(flush_wayA_data_q, congr_cl_ex2_wayA_sel(5)) or + gate(reload_wayA_data2_q, congr_cl_ex2_wayA_sel(6)) or + gate(flush_wayA_data2_q, congr_cl_ex2_wayA_sel(7)); +-- EX3/RELU Stage Priority Selection +wayA_early_sel <= congr_cl_ex2_wayA_byp(1); +wayA_early_stg_pri <= flush_wayA_d; +-- Stage/ARRAY Priority Selection +wayA_stg_val <= (others=>(wayA_early_sel)); +wayA_stg_val_b <= (others=>(not(wayA_early_sel))); +wayA_val(0 TO 1) <= not wayA_val_b_q(0 to 1); +wayA_val(2 TO 5) <= not wayA_val_b_q(2 to 5); +wayA_val_b1 <= not wayA_val(0); +-- WayB Bypass Calculation +congr_cl_ex2_wayB_byp(1) <= congr_cl_ex2_ex3_m and ex3_wayB_hit; +congr_cl_ex2_wayB_byp(2) <= congr_cl_ex2_relu_m and reload_wayB_upd_q; +congr_cl_ex2_wayB_byp(3) <= congr_cl_ex2_ex4_m and binv_wayB_upd_q; +congr_cl_ex2_wayB_byp(4) <= congr_cl_ex2_relu_s_m and reload_wayB_upd2_q; +congr_cl_ex2_wayB_byp(5) <= congr_cl_ex2_ex5_m and binv_wayB_upd2_q; +congr_cl_ex2_wayB_byp(6) <= congr_cl_ex2_p1_cmp and reload_wayB_upd3_q; +congr_cl_ex2_wayB_byp(7) <= congr_cl_ex2_p0_cmp and binv_wayB_upd3_q; +-- WayB Bypass Valid +ex3_wayB_fxubyp_val_d <= congr_cl_ex2_wayB_byp(1) or congr_cl_ex2_wayB_byp(3) or + congr_cl_ex2_wayB_byp(5) or congr_cl_ex2_wayB_byp(7); +ex3_wayB_relbyp_val_d <= congr_cl_ex2_wayB_byp(2) or congr_cl_ex2_wayB_byp(4) or + congr_cl_ex2_wayB_byp(6); +ex4_wayB_fxubyp_val_d <= ex3_wayB_fxubyp_val_q; +ex4_wayB_relbyp_val_d <= ex3_wayB_relbyp_val_q; +ex4_wayB_byp_sel <= ex4_wayB_fxubyp_val_q & ex4_wayB_relbyp_val_q; +-- Late Stages Priority Selection +congr_cl_ex2_wayB_sel(2) <= congr_cl_ex2_wayB_byp(2); +congr_cl_ex2_wayB_sel(3) <= congr_cl_ex2_wayB_byp(3) and not congr_cl_ex2_wayB_byp(2); +congr_cl_ex2_wayB_sel(4) <= congr_cl_ex2_wayB_byp(4) and not or_reduce(congr_cl_ex2_wayB_byp(2 to 3)); +congr_cl_ex2_wayB_sel(5) <= congr_cl_ex2_wayB_byp(5) and not or_reduce(congr_cl_ex2_wayB_byp(2 to 4)); +congr_cl_ex2_wayB_sel(6) <= congr_cl_ex2_wayB_byp(6) and not or_reduce(congr_cl_ex2_wayB_byp(2 to 5)); +congr_cl_ex2_wayB_sel(7) <= congr_cl_ex2_wayB_byp(7) and not or_reduce(congr_cl_ex2_wayB_byp(2 to 6)); +-- ArrayRead/LATE Stage Priority Selection +wayB_late_sel <= or_reduce(congr_cl_ex2_wayB_byp(2 to 7)); +wayB_later_stg_pri <= gate(p0_arr_wayB_rd, not wayB_late_sel) or + gate(reload_wayB_q, congr_cl_ex2_wayB_sel(2)) or + gate(flush_wayB_q, congr_cl_ex2_wayB_sel(3)) or + gate(reload_wayB_data_q, congr_cl_ex2_wayB_sel(4)) or + gate(flush_wayB_data_q, congr_cl_ex2_wayB_sel(5)) or + gate(reload_wayB_data2_q, congr_cl_ex2_wayB_sel(6)) or + gate(flush_wayB_data2_q, congr_cl_ex2_wayB_sel(7)); +-- EX3/RELU Stage Priority Selection +wayB_early_sel <= congr_cl_ex2_wayB_byp(1); +wayB_early_stg_pri <= flush_wayB_d; +-- Stage/ARRAY Priority Selection +wayB_stg_val <= (others=>(wayB_early_sel)); +wayB_stg_val_b <= (others=>(not(wayB_early_sel))); +wayB_val(0 TO 1) <= not wayB_val_b_q(0 to 1); +wayB_val(2 TO 5) <= not wayB_val_b_q(2 to 5); +wayB_val_b1 <= not wayB_val(0); +-- WayC Bypass Calculation +congr_cl_ex2_wayC_byp(1) <= congr_cl_ex2_ex3_m and ex3_wayC_hit; +congr_cl_ex2_wayC_byp(2) <= congr_cl_ex2_relu_m and reload_wayC_upd_q; +congr_cl_ex2_wayC_byp(3) <= congr_cl_ex2_ex4_m and binv_wayC_upd_q; +congr_cl_ex2_wayC_byp(4) <= congr_cl_ex2_relu_s_m and reload_wayC_upd2_q; +congr_cl_ex2_wayC_byp(5) <= congr_cl_ex2_ex5_m and binv_wayC_upd2_q; +congr_cl_ex2_wayC_byp(6) <= congr_cl_ex2_p1_cmp and reload_wayC_upd3_q; +congr_cl_ex2_wayC_byp(7) <= congr_cl_ex2_p0_cmp and binv_wayC_upd3_q; +-- WayC Bypass Valid +ex3_wayC_fxubyp_val_d <= congr_cl_ex2_wayC_byp(1) or congr_cl_ex2_wayC_byp(3) or + congr_cl_ex2_wayC_byp(5) or congr_cl_ex2_wayC_byp(7); +ex3_wayC_relbyp_val_d <= congr_cl_ex2_wayC_byp(2) or congr_cl_ex2_wayC_byp(4) or + congr_cl_ex2_wayC_byp(6); +ex4_wayC_fxubyp_val_d <= ex3_wayC_fxubyp_val_q; +ex4_wayC_relbyp_val_d <= ex3_wayC_relbyp_val_q; +ex4_wayC_byp_sel <= ex4_wayC_fxubyp_val_q & ex4_wayC_relbyp_val_q; +-- Late Stages Priority Selection +congr_cl_ex2_wayC_sel(2) <= congr_cl_ex2_wayC_byp(2); +congr_cl_ex2_wayC_sel(3) <= congr_cl_ex2_wayC_byp(3) and not congr_cl_ex2_wayC_byp(2); +congr_cl_ex2_wayC_sel(4) <= congr_cl_ex2_wayC_byp(4) and not or_reduce(congr_cl_ex2_wayC_byp(2 to 3)); +congr_cl_ex2_wayC_sel(5) <= congr_cl_ex2_wayC_byp(5) and not or_reduce(congr_cl_ex2_wayC_byp(2 to 4)); +congr_cl_ex2_wayC_sel(6) <= congr_cl_ex2_wayC_byp(6) and not or_reduce(congr_cl_ex2_wayC_byp(2 to 5)); +congr_cl_ex2_wayC_sel(7) <= congr_cl_ex2_wayC_byp(7) and not or_reduce(congr_cl_ex2_wayC_byp(2 to 6)); +-- ArrayRead/LATE Stage Priority Selection +wayC_late_sel <= or_reduce(congr_cl_ex2_wayC_byp(2 to 7)); +wayC_later_stg_pri <= gate(p0_arr_wayC_rd, not wayC_late_sel) or + gate(reload_wayC_q, congr_cl_ex2_wayC_sel(2)) or + gate(flush_wayC_q, congr_cl_ex2_wayC_sel(3)) or + gate(reload_wayC_data_q, congr_cl_ex2_wayC_sel(4)) or + gate(flush_wayC_data_q, congr_cl_ex2_wayC_sel(5)) or + gate(reload_wayC_data2_q, congr_cl_ex2_wayC_sel(6)) or + gate(flush_wayC_data2_q, congr_cl_ex2_wayC_sel(7)); +-- EX3/RELU Stage Priority Selection +wayC_early_sel <= congr_cl_ex2_wayC_byp(1); +wayC_early_stg_pri <= flush_wayC_d; +-- Stage/ARRAY Priority Selection +wayC_stg_val <= (others=>(wayC_early_sel)); +wayC_stg_val_b <= (others=>(not(wayC_early_sel))); +wayC_val(0 TO 1) <= not wayC_val_b_q(0 to 1); +wayC_val(2 TO 5) <= not wayC_val_b_q(2 to 5); +wayC_val_b1 <= not wayC_val(0); +-- WayD Bypass Calculation +congr_cl_ex2_wayD_byp(1) <= congr_cl_ex2_ex3_m and ex3_wayD_hit; +congr_cl_ex2_wayD_byp(2) <= congr_cl_ex2_relu_m and reload_wayD_upd_q; +congr_cl_ex2_wayD_byp(3) <= congr_cl_ex2_ex4_m and binv_wayD_upd_q; +congr_cl_ex2_wayD_byp(4) <= congr_cl_ex2_relu_s_m and reload_wayD_upd2_q; +congr_cl_ex2_wayD_byp(5) <= congr_cl_ex2_ex5_m and binv_wayD_upd2_q; +congr_cl_ex2_wayD_byp(6) <= congr_cl_ex2_p1_cmp and reload_wayD_upd3_q; +congr_cl_ex2_wayD_byp(7) <= congr_cl_ex2_p0_cmp and binv_wayD_upd3_q; +-- WayD Bypass Valid +ex3_wayD_fxubyp_val_d <= congr_cl_ex2_wayD_byp(1) or congr_cl_ex2_wayD_byp(3) or + congr_cl_ex2_wayD_byp(5) or congr_cl_ex2_wayD_byp(7); +ex3_wayD_relbyp_val_d <= congr_cl_ex2_wayD_byp(2) or congr_cl_ex2_wayD_byp(4) or + congr_cl_ex2_wayD_byp(6); +ex4_wayD_fxubyp_val_d <= ex3_wayD_fxubyp_val_q; +ex4_wayD_relbyp_val_d <= ex3_wayD_relbyp_val_q; +ex4_wayD_byp_sel <= ex4_wayD_fxubyp_val_q & ex4_wayD_relbyp_val_q; +-- Late Stages Priority Selection +congr_cl_ex2_wayD_sel(2) <= congr_cl_ex2_wayD_byp(2); +congr_cl_ex2_wayD_sel(3) <= congr_cl_ex2_wayD_byp(3) and not congr_cl_ex2_wayD_byp(2); +congr_cl_ex2_wayD_sel(4) <= congr_cl_ex2_wayD_byp(4) and not or_reduce(congr_cl_ex2_wayD_byp(2 to 3)); +congr_cl_ex2_wayD_sel(5) <= congr_cl_ex2_wayD_byp(5) and not or_reduce(congr_cl_ex2_wayD_byp(2 to 4)); +congr_cl_ex2_wayD_sel(6) <= congr_cl_ex2_wayD_byp(6) and not or_reduce(congr_cl_ex2_wayD_byp(2 to 5)); +congr_cl_ex2_wayD_sel(7) <= congr_cl_ex2_wayD_byp(7) and not or_reduce(congr_cl_ex2_wayD_byp(2 to 6)); +-- ArrayRead/LATE Stage Priority Selection +wayD_late_sel <= or_reduce(congr_cl_ex2_wayD_byp(2 to 7)); +wayD_later_stg_pri <= gate(p0_arr_wayD_rd, not wayD_late_sel) or + gate(reload_wayD_q, congr_cl_ex2_wayD_sel(2)) or + gate(flush_wayD_q, congr_cl_ex2_wayD_sel(3)) or + gate(reload_wayD_data_q, congr_cl_ex2_wayD_sel(4)) or + gate(flush_wayD_data_q, congr_cl_ex2_wayD_sel(5)) or + gate(reload_wayD_data2_q, congr_cl_ex2_wayD_sel(6)) or + gate(flush_wayD_data2_q, congr_cl_ex2_wayD_sel(7)); +-- EX3/RELU Stage Priority Selection +wayD_early_sel <= congr_cl_ex2_wayD_byp(1); +wayD_early_stg_pri <= flush_wayD_d; +-- Stage/ARRAY Priority Selection +wayD_stg_val <= (others=>(wayD_early_sel)); +wayD_stg_val_b <= (others=>(not(wayD_early_sel))); +wayD_val(0 TO 1) <= not wayD_val_b_q(0 to 1); +wayD_val(2 TO 5) <= not wayD_val_b_q(2 to 5); +wayD_val_b1 <= not wayD_val(0); +-- WayE Bypass Calculation +congr_cl_ex2_wayE_byp(1) <= congr_cl_ex2_ex3_m and ex3_wayE_hit; +congr_cl_ex2_wayE_byp(2) <= congr_cl_ex2_relu_m and reload_wayE_upd_q; +congr_cl_ex2_wayE_byp(3) <= congr_cl_ex2_ex4_m and binv_wayE_upd_q; +congr_cl_ex2_wayE_byp(4) <= congr_cl_ex2_relu_s_m and reload_wayE_upd2_q; +congr_cl_ex2_wayE_byp(5) <= congr_cl_ex2_ex5_m and binv_wayE_upd2_q; +congr_cl_ex2_wayE_byp(6) <= congr_cl_ex2_p1_cmp and reload_wayE_upd3_q; +congr_cl_ex2_wayE_byp(7) <= congr_cl_ex2_p0_cmp and binv_wayE_upd3_q; +-- WayE Bypass Valid +ex3_wayE_fxubyp_val_d <= congr_cl_ex2_wayE_byp(1) or congr_cl_ex2_wayE_byp(3) or + congr_cl_ex2_wayE_byp(5) or congr_cl_ex2_wayE_byp(7); +ex3_wayE_relbyp_val_d <= congr_cl_ex2_wayE_byp(2) or congr_cl_ex2_wayE_byp(4) or + congr_cl_ex2_wayE_byp(6); +ex4_wayE_fxubyp_val_d <= ex3_wayE_fxubyp_val_q; +ex4_wayE_relbyp_val_d <= ex3_wayE_relbyp_val_q; +ex4_wayE_byp_sel <= ex4_wayE_fxubyp_val_q & ex4_wayE_relbyp_val_q; +-- Late Stages Priority Selection +congr_cl_ex2_wayE_sel(2) <= congr_cl_ex2_wayE_byp(2); +congr_cl_ex2_wayE_sel(3) <= congr_cl_ex2_wayE_byp(3) and not congr_cl_ex2_wayE_byp(2); +congr_cl_ex2_wayE_sel(4) <= congr_cl_ex2_wayE_byp(4) and not or_reduce(congr_cl_ex2_wayE_byp(2 to 3)); +congr_cl_ex2_wayE_sel(5) <= congr_cl_ex2_wayE_byp(5) and not or_reduce(congr_cl_ex2_wayE_byp(2 to 4)); +congr_cl_ex2_wayE_sel(6) <= congr_cl_ex2_wayE_byp(6) and not or_reduce(congr_cl_ex2_wayE_byp(2 to 5)); +congr_cl_ex2_wayE_sel(7) <= congr_cl_ex2_wayE_byp(7) and not or_reduce(congr_cl_ex2_wayE_byp(2 to 6)); +-- ArrayRead/LATE Stage Priority Selection +wayE_late_sel <= or_reduce(congr_cl_ex2_wayE_byp(2 to 7)); +wayE_later_stg_pri <= gate(p0_arr_wayE_rd, not wayE_late_sel) or + gate(reload_wayE_q, congr_cl_ex2_wayE_sel(2)) or + gate(flush_wayE_q, congr_cl_ex2_wayE_sel(3)) or + gate(reload_wayE_data_q, congr_cl_ex2_wayE_sel(4)) or + gate(flush_wayE_data_q, congr_cl_ex2_wayE_sel(5)) or + gate(reload_wayE_data2_q, congr_cl_ex2_wayE_sel(6)) or + gate(flush_wayE_data2_q, congr_cl_ex2_wayE_sel(7)); +-- EX3/RELU Stage Priority Selection +wayE_early_sel <= congr_cl_ex2_wayE_byp(1); +wayE_early_stg_pri <= flush_wayE_d; +-- Stage/ARRAY Priority Selection +wayE_stg_val <= (others=>(wayE_early_sel)); +wayE_stg_val_b <= (others=>(not(wayE_early_sel))); +wayE_val(0 TO 1) <= not wayE_val_b_q(0 to 1); +wayE_val(2 TO 5) <= not wayE_val_b_q(2 to 5); +wayE_val_b1 <= not wayE_val(0); +-- WayF Bypass Calculation +congr_cl_ex2_wayF_byp(1) <= congr_cl_ex2_ex3_m and ex3_wayF_hit; +congr_cl_ex2_wayF_byp(2) <= congr_cl_ex2_relu_m and reload_wayF_upd_q; +congr_cl_ex2_wayF_byp(3) <= congr_cl_ex2_ex4_m and binv_wayF_upd_q; +congr_cl_ex2_wayF_byp(4) <= congr_cl_ex2_relu_s_m and reload_wayF_upd2_q; +congr_cl_ex2_wayF_byp(5) <= congr_cl_ex2_ex5_m and binv_wayF_upd2_q; +congr_cl_ex2_wayF_byp(6) <= congr_cl_ex2_p1_cmp and reload_wayF_upd3_q; +congr_cl_ex2_wayF_byp(7) <= congr_cl_ex2_p0_cmp and binv_wayF_upd3_q; +-- WayF Bypass Valid +ex3_wayF_fxubyp_val_d <= congr_cl_ex2_wayF_byp(1) or congr_cl_ex2_wayF_byp(3) or + congr_cl_ex2_wayF_byp(5) or congr_cl_ex2_wayF_byp(7); +ex3_wayF_relbyp_val_d <= congr_cl_ex2_wayF_byp(2) or congr_cl_ex2_wayF_byp(4) or + congr_cl_ex2_wayF_byp(6); +ex4_wayF_fxubyp_val_d <= ex3_wayF_fxubyp_val_q; +ex4_wayF_relbyp_val_d <= ex3_wayF_relbyp_val_q; +ex4_wayF_byp_sel <= ex4_wayF_fxubyp_val_q & ex4_wayF_relbyp_val_q; +-- Late Stages Priority Selection +congr_cl_ex2_wayF_sel(2) <= congr_cl_ex2_wayF_byp(2); +congr_cl_ex2_wayF_sel(3) <= congr_cl_ex2_wayF_byp(3) and not congr_cl_ex2_wayF_byp(2); +congr_cl_ex2_wayF_sel(4) <= congr_cl_ex2_wayF_byp(4) and not or_reduce(congr_cl_ex2_wayF_byp(2 to 3)); +congr_cl_ex2_wayF_sel(5) <= congr_cl_ex2_wayF_byp(5) and not or_reduce(congr_cl_ex2_wayF_byp(2 to 4)); +congr_cl_ex2_wayF_sel(6) <= congr_cl_ex2_wayF_byp(6) and not or_reduce(congr_cl_ex2_wayF_byp(2 to 5)); +congr_cl_ex2_wayF_sel(7) <= congr_cl_ex2_wayF_byp(7) and not or_reduce(congr_cl_ex2_wayF_byp(2 to 6)); +-- ArrayRead/LATE Stage Priority Selection +wayF_late_sel <= or_reduce(congr_cl_ex2_wayF_byp(2 to 7)); +wayF_later_stg_pri <= gate(p0_arr_wayF_rd, not wayF_late_sel) or + gate(reload_wayF_q, congr_cl_ex2_wayF_sel(2)) or + gate(flush_wayF_q, congr_cl_ex2_wayF_sel(3)) or + gate(reload_wayF_data_q, congr_cl_ex2_wayF_sel(4)) or + gate(flush_wayF_data_q, congr_cl_ex2_wayF_sel(5)) or + gate(reload_wayF_data2_q, congr_cl_ex2_wayF_sel(6)) or + gate(flush_wayF_data2_q, congr_cl_ex2_wayF_sel(7)); +-- EX3/RELU Stage Priority Selection +wayF_early_sel <= congr_cl_ex2_wayF_byp(1); +wayF_early_stg_pri <= flush_wayF_d; +-- Stage/ARRAY Priority Selection +wayF_stg_val <= (others=>(wayF_early_sel)); +wayF_stg_val_b <= (others=>(not(wayF_early_sel))); +wayF_val(0 TO 1) <= not wayF_val_b_q(0 to 1); +wayF_val(2 TO 5) <= not wayF_val_b_q(2 to 5); +wayF_val_b1 <= not wayF_val(0); +-- WayG Bypass Calculation +congr_cl_ex2_wayG_byp(1) <= congr_cl_ex2_ex3_m and ex3_wayG_hit; +congr_cl_ex2_wayG_byp(2) <= congr_cl_ex2_relu_m and reload_wayG_upd_q; +congr_cl_ex2_wayG_byp(3) <= congr_cl_ex2_ex4_m and binv_wayG_upd_q; +congr_cl_ex2_wayG_byp(4) <= congr_cl_ex2_relu_s_m and reload_wayG_upd2_q; +congr_cl_ex2_wayG_byp(5) <= congr_cl_ex2_ex5_m and binv_wayG_upd2_q; +congr_cl_ex2_wayG_byp(6) <= congr_cl_ex2_p1_cmp and reload_wayG_upd3_q; +congr_cl_ex2_wayG_byp(7) <= congr_cl_ex2_p0_cmp and binv_wayG_upd3_q; +-- WayG Bypass Valid +ex3_wayG_fxubyp_val_d <= congr_cl_ex2_wayG_byp(1) or congr_cl_ex2_wayG_byp(3) or + congr_cl_ex2_wayG_byp(5) or congr_cl_ex2_wayG_byp(7); +ex3_wayG_relbyp_val_d <= congr_cl_ex2_wayG_byp(2) or congr_cl_ex2_wayG_byp(4) or + congr_cl_ex2_wayG_byp(6); +ex4_wayG_fxubyp_val_d <= ex3_wayG_fxubyp_val_q; +ex4_wayG_relbyp_val_d <= ex3_wayG_relbyp_val_q; +ex4_wayG_byp_sel <= ex4_wayG_fxubyp_val_q & ex4_wayG_relbyp_val_q; +-- Late Stages Priority Selection +congr_cl_ex2_wayG_sel(2) <= congr_cl_ex2_wayG_byp(2); +congr_cl_ex2_wayG_sel(3) <= congr_cl_ex2_wayG_byp(3) and not congr_cl_ex2_wayG_byp(2); +congr_cl_ex2_wayG_sel(4) <= congr_cl_ex2_wayG_byp(4) and not or_reduce(congr_cl_ex2_wayG_byp(2 to 3)); +congr_cl_ex2_wayG_sel(5) <= congr_cl_ex2_wayG_byp(5) and not or_reduce(congr_cl_ex2_wayG_byp(2 to 4)); +congr_cl_ex2_wayG_sel(6) <= congr_cl_ex2_wayG_byp(6) and not or_reduce(congr_cl_ex2_wayG_byp(2 to 5)); +congr_cl_ex2_wayG_sel(7) <= congr_cl_ex2_wayG_byp(7) and not or_reduce(congr_cl_ex2_wayG_byp(2 to 6)); +-- ArrayRead/LATE Stage Priority Selection +wayG_late_sel <= or_reduce(congr_cl_ex2_wayG_byp(2 to 7)); +wayG_later_stg_pri <= gate(p0_arr_wayG_rd, not wayG_late_sel) or + gate(reload_wayG_q, congr_cl_ex2_wayG_sel(2)) or + gate(flush_wayG_q, congr_cl_ex2_wayG_sel(3)) or + gate(reload_wayG_data_q, congr_cl_ex2_wayG_sel(4)) or + gate(flush_wayG_data_q, congr_cl_ex2_wayG_sel(5)) or + gate(reload_wayG_data2_q, congr_cl_ex2_wayG_sel(6)) or + gate(flush_wayG_data2_q, congr_cl_ex2_wayG_sel(7)); +-- EX3/RELU Stage Priority Selection +wayG_early_sel <= congr_cl_ex2_wayG_byp(1); +wayG_early_stg_pri <= flush_wayG_d; +-- Stage/ARRAY Priority Selection +wayG_stg_val <= (others=>(wayG_early_sel)); +wayG_stg_val_b <= (others=>(not(wayG_early_sel))); +wayG_val(0 TO 1) <= not wayG_val_b_q(0 to 1); +wayG_val(2 TO 5) <= not wayG_val_b_q(2 to 5); +wayG_val_b1 <= not wayG_val(0); +-- WayH Bypass Calculation +congr_cl_ex2_wayH_byp(1) <= congr_cl_ex2_ex3_m and ex3_wayH_hit; +congr_cl_ex2_wayH_byp(2) <= congr_cl_ex2_relu_m and reload_wayH_upd_q; +congr_cl_ex2_wayH_byp(3) <= congr_cl_ex2_ex4_m and binv_wayH_upd_q; +congr_cl_ex2_wayH_byp(4) <= congr_cl_ex2_relu_s_m and reload_wayH_upd2_q; +congr_cl_ex2_wayH_byp(5) <= congr_cl_ex2_ex5_m and binv_wayH_upd2_q; +congr_cl_ex2_wayH_byp(6) <= congr_cl_ex2_p1_cmp and reload_wayH_upd3_q; +congr_cl_ex2_wayH_byp(7) <= congr_cl_ex2_p0_cmp and binv_wayH_upd3_q; +-- WayH Bypass Valid +ex3_wayH_fxubyp_val_d <= congr_cl_ex2_wayH_byp(1) or congr_cl_ex2_wayH_byp(3) or + congr_cl_ex2_wayH_byp(5) or congr_cl_ex2_wayH_byp(7); +ex3_wayH_relbyp_val_d <= congr_cl_ex2_wayH_byp(2) or congr_cl_ex2_wayH_byp(4) or + congr_cl_ex2_wayH_byp(6); +ex4_wayH_fxubyp_val_d <= ex3_wayH_fxubyp_val_q; +ex4_wayH_relbyp_val_d <= ex3_wayH_relbyp_val_q; +ex4_wayH_byp_sel <= ex4_wayH_fxubyp_val_q & ex4_wayH_relbyp_val_q; +-- Late Stages Priority Selection +congr_cl_ex2_wayH_sel(2) <= congr_cl_ex2_wayH_byp(2); +congr_cl_ex2_wayH_sel(3) <= congr_cl_ex2_wayH_byp(3) and not congr_cl_ex2_wayH_byp(2); +congr_cl_ex2_wayH_sel(4) <= congr_cl_ex2_wayH_byp(4) and not or_reduce(congr_cl_ex2_wayH_byp(2 to 3)); +congr_cl_ex2_wayH_sel(5) <= congr_cl_ex2_wayH_byp(5) and not or_reduce(congr_cl_ex2_wayH_byp(2 to 4)); +congr_cl_ex2_wayH_sel(6) <= congr_cl_ex2_wayH_byp(6) and not or_reduce(congr_cl_ex2_wayH_byp(2 to 5)); +congr_cl_ex2_wayH_sel(7) <= congr_cl_ex2_wayH_byp(7) and not or_reduce(congr_cl_ex2_wayH_byp(2 to 6)); +-- ArrayRead/LATE Stage Priority Selection +wayH_late_sel <= or_reduce(congr_cl_ex2_wayH_byp(2 to 7)); +wayH_later_stg_pri <= gate(p0_arr_wayH_rd, not wayH_late_sel) or + gate(reload_wayH_q, congr_cl_ex2_wayH_sel(2)) or + gate(flush_wayH_q, congr_cl_ex2_wayH_sel(3)) or + gate(reload_wayH_data_q, congr_cl_ex2_wayH_sel(4)) or + gate(flush_wayH_data_q, congr_cl_ex2_wayH_sel(5)) or + gate(reload_wayH_data2_q, congr_cl_ex2_wayH_sel(6)) or + gate(flush_wayH_data2_q, congr_cl_ex2_wayH_sel(7)); +-- EX3/RELU Stage Priority Selection +wayH_early_sel <= congr_cl_ex2_wayH_byp(1); +wayH_early_stg_pri <= flush_wayH_d; +-- Stage/ARRAY Priority Selection +wayH_stg_val <= (others=>(wayH_early_sel)); +wayH_stg_val_b <= (others=>(not(wayH_early_sel))); +wayH_val(0 TO 1) <= not wayH_val_b_q(0 to 1); +wayH_val(2 TO 5) <= not wayH_val_b_q(2 to 5); +wayH_val_b1 <= not wayH_val(0); +-- #################################################### +-- Invalidate Pipe and Execution Pipe Hit/Miss Logic +-- #################################################### +-- EX3 stage +fxu_pipe_val <= ex3_c_acc or ex3_flush_cline_q; +-- EX4Invalidate/BINV/RELOAD Bypass Invalidate Pipe +-- #################################################### +-- WayA +ex3WayHitA: ex3_wayA_hit <= not (tagA_hit_b or wayA_val_b1); +-- WayB +ex3WayHitB: ex3_wayB_hit <= not (tagB_hit_b or wayB_val_b1); +-- WayC +ex3WayHitC: ex3_wayC_hit <= not (tagC_hit_b or wayC_val_b1); +-- WayD +ex3WayHitD: ex3_wayD_hit <= not (tagD_hit_b or wayD_val_b1); +-- WayE +ex3WayHitE: ex3_wayE_hit <= not (tagE_hit_b or wayE_val_b1); +-- WayF +ex3WayHitF: ex3_wayF_hit <= not (tagF_hit_b or wayF_val_b1); +-- WayG +ex3WayHitG: ex3_wayG_hit <= not (tagG_hit_b or wayG_val_b1); +-- WayH +ex3WayHitH: ex3_wayH_hit <= not (tagH_hit_b or wayH_val_b1); +-- Invalidate Valid Bit Logic on Port0 +clr_val <= ex3_flush_cline_q or back_inval_stg3_q; +clr_val_wayA <= clr_val; +-- Need to detect if Back-Invalidate or invalidate type instruction invalidated the lock bit +inval_clr_lck_wA_d <= clr_val_wayA and wayA_val(1); +flush_wayA_d(0) <= not clr_val_wayA and wayA_val(0); +clr_val_wayB <= clr_val; +-- Need to detect if Back-Invalidate or invalidate type instruction invalidated the lock bit +inval_clr_lck_wB_d <= clr_val_wayB and wayB_val(1); +flush_wayB_d(0) <= not clr_val_wayB and wayB_val(0); +clr_val_wayC <= clr_val; +-- Need to detect if Back-Invalidate or invalidate type instruction invalidated the lock bit +inval_clr_lck_wC_d <= clr_val_wayC and wayC_val(1); +flush_wayC_d(0) <= not clr_val_wayC and wayC_val(0); +clr_val_wayD <= clr_val; +-- Need to detect if Back-Invalidate or invalidate type instruction invalidated the lock bit +inval_clr_lck_wD_d <= clr_val_wayD and wayD_val(1); +flush_wayD_d(0) <= not clr_val_wayD and wayD_val(0); +clr_val_wayE <= clr_val; +-- Need to detect if Back-Invalidate or invalidate type instruction invalidated the lock bit +inval_clr_lck_wE_d <= clr_val_wayE and wayE_val(1); +flush_wayE_d(0) <= not clr_val_wayE and wayE_val(0); +clr_val_wayF <= clr_val; +-- Need to detect if Back-Invalidate or invalidate type instruction invalidated the lock bit +inval_clr_lck_wF_d <= clr_val_wayF and wayF_val(1); +flush_wayF_d(0) <= not clr_val_wayF and wayF_val(0); +clr_val_wayG <= clr_val; +-- Need to detect if Back-Invalidate or invalidate type instruction invalidated the lock bit +inval_clr_lck_wG_d <= clr_val_wayG and wayG_val(1); +flush_wayG_d(0) <= not clr_val_wayG and wayG_val(0); +clr_val_wayH <= clr_val; +-- Need to detect if Back-Invalidate or invalidate type instruction invalidated the lock bit +inval_clr_lck_wH_d <= clr_val_wayH and wayH_val(1); +flush_wayH_d(0) <= not clr_val_wayH and wayH_val(0); +-- Clear Lock Bit Logic on Port0 +-- Clear Lock Bit on an invalidate type op or a DCBLC +clr_lock <= clr_val or ex3_lock_clr_q; +-- CLEAR LOCK SET LOCK +upd_lck_wayA <= clr_lock & ex3_lock_set_q; +flush_wayA_d(1) <= (wayA_val(1) and not upd_lck_wayA(0)) or + (wayA_val(0) and upd_lck_wayA(1)); +-- Staging out current watch bits +ex4_wayA_val_d <= wayA_val; +-- CLEAR LOCK SET LOCK +upd_lck_wayB <= clr_lock & ex3_lock_set_q; +flush_wayB_d(1) <= (wayB_val(1) and not upd_lck_wayB(0)) or + (wayB_val(0) and upd_lck_wayB(1)); +-- Staging out current watch bits +ex4_wayB_val_d <= wayB_val; +-- CLEAR LOCK SET LOCK +upd_lck_wayC <= clr_lock & ex3_lock_set_q; +flush_wayC_d(1) <= (wayC_val(1) and not upd_lck_wayC(0)) or + (wayC_val(0) and upd_lck_wayC(1)); +-- Staging out current watch bits +ex4_wayC_val_d <= wayC_val; +-- CLEAR LOCK SET LOCK +upd_lck_wayD <= clr_lock & ex3_lock_set_q; +flush_wayD_d(1) <= (wayD_val(1) and not upd_lck_wayD(0)) or + (wayD_val(0) and upd_lck_wayD(1)); +-- Staging out current watch bits +ex4_wayD_val_d <= wayD_val; +-- CLEAR LOCK SET LOCK +upd_lck_wayE <= clr_lock & ex3_lock_set_q; +flush_wayE_d(1) <= (wayE_val(1) and not upd_lck_wayE(0)) or + (wayE_val(0) and upd_lck_wayE(1)); +-- Staging out current watch bits +ex4_wayE_val_d <= wayE_val; +-- CLEAR LOCK SET LOCK +upd_lck_wayF <= clr_lock & ex3_lock_set_q; +flush_wayF_d(1) <= (wayF_val(1) and not upd_lck_wayF(0)) or + (wayF_val(0) and upd_lck_wayF(1)); +-- Staging out current watch bits +ex4_wayF_val_d <= wayF_val; +-- CLEAR LOCK SET LOCK +upd_lck_wayG <= clr_lock & ex3_lock_set_q; +flush_wayG_d(1) <= (wayG_val(1) and not upd_lck_wayG(0)) or + (wayG_val(0) and upd_lck_wayG(1)); +-- Staging out current watch bits +ex4_wayG_val_d <= wayG_val; +-- CLEAR LOCK SET LOCK +upd_lck_wayH <= clr_lock & ex3_lock_set_q; +flush_wayH_d(1) <= (wayH_val(1) and not upd_lck_wayH(0)) or + (wayH_val(0) and upd_lck_wayH(1)); +-- Staging out current watch bits +ex4_wayH_val_d <= wayH_val; +-- Set/Clr Watch Bit for Thread on Port0 +-- Clear Watch Bit on an invalidate type op or WCLR +-- Thread 0 Logic +lose_watch(0) <= clr_val or (ex3_store_instr_q and ex3_c_acc and not ex3_thrd_id_q(0)); +ex4_lose_watch_d(0) <= lose_watch(0); +clr_watch(0) <= (ex3_watch_clr_q and ex3_thrd_id_q(0)) or lose_watch(0); +set_watch(0) <= ex3_watch_set_q and ex3_thrd_id_q(0); +-- Determine if a Watch Bit was lost +ex4_lost_wayA(0) <= ex4_lose_watch_q(0) and ex4_way_hit_q(0) and ex4_wayA_val_q(2); +-- CLEAR Watch SET Watch +upd_watch_tid0_wayA <= (clr_watch(0) or ex3_watch_clr_all(0)) & set_watch(0); +flush_wayA_d(2) <= (wayA_val(2) and not upd_watch_tid0_wayA(0)) or + (wayA_val(0) and upd_watch_tid0_wayA(1)); +-- Determine if a Watch Bit was lost +ex4_lost_wayB(0) <= ex4_lose_watch_q(0) and ex4_way_hit_q(1) and ex4_wayB_val_q(2); +-- CLEAR Watch SET Watch +upd_watch_tid0_wayB <= (clr_watch(0) or ex3_watch_clr_all(0)) & set_watch(0); +flush_wayB_d(2) <= (wayB_val(2) and not upd_watch_tid0_wayB(0)) or + (wayB_val(0) and upd_watch_tid0_wayB(1)); +-- Determine if a Watch Bit was lost +ex4_lost_wayC(0) <= ex4_lose_watch_q(0) and ex4_way_hit_q(2) and ex4_wayC_val_q(2); +-- CLEAR Watch SET Watch +upd_watch_tid0_wayC <= (clr_watch(0) or ex3_watch_clr_all(0)) & set_watch(0); +flush_wayC_d(2) <= (wayC_val(2) and not upd_watch_tid0_wayC(0)) or + (wayC_val(0) and upd_watch_tid0_wayC(1)); +-- Determine if a Watch Bit was lost +ex4_lost_wayD(0) <= ex4_lose_watch_q(0) and ex4_way_hit_q(3) and ex4_wayD_val_q(2); +-- CLEAR Watch SET Watch +upd_watch_tid0_wayD <= (clr_watch(0) or ex3_watch_clr_all(0)) & set_watch(0); +flush_wayD_d(2) <= (wayD_val(2) and not upd_watch_tid0_wayD(0)) or + (wayD_val(0) and upd_watch_tid0_wayD(1)); +-- Determine if a Watch Bit was lost +ex4_lost_wayE(0) <= ex4_lose_watch_q(0) and ex4_way_hit_q(4) and ex4_wayE_val_q(2); +-- CLEAR Watch SET Watch +upd_watch_tid0_wayE <= (clr_watch(0) or ex3_watch_clr_all(0)) & set_watch(0); +flush_wayE_d(2) <= (wayE_val(2) and not upd_watch_tid0_wayE(0)) or + (wayE_val(0) and upd_watch_tid0_wayE(1)); +-- Determine if a Watch Bit was lost +ex4_lost_wayF(0) <= ex4_lose_watch_q(0) and ex4_way_hit_q(5) and ex4_wayF_val_q(2); +-- CLEAR Watch SET Watch +upd_watch_tid0_wayF <= (clr_watch(0) or ex3_watch_clr_all(0)) & set_watch(0); +flush_wayF_d(2) <= (wayF_val(2) and not upd_watch_tid0_wayF(0)) or + (wayF_val(0) and upd_watch_tid0_wayF(1)); +-- Determine if a Watch Bit was lost +ex4_lost_wayG(0) <= ex4_lose_watch_q(0) and ex4_way_hit_q(6) and ex4_wayG_val_q(2); +-- CLEAR Watch SET Watch +upd_watch_tid0_wayG <= (clr_watch(0) or ex3_watch_clr_all(0)) & set_watch(0); +flush_wayG_d(2) <= (wayG_val(2) and not upd_watch_tid0_wayG(0)) or + (wayG_val(0) and upd_watch_tid0_wayG(1)); +-- Determine if a Watch Bit was lost +ex4_lost_wayH(0) <= ex4_lose_watch_q(0) and ex4_way_hit_q(7) and ex4_wayH_val_q(2); +-- CLEAR Watch SET Watch +upd_watch_tid0_wayH <= (clr_watch(0) or ex3_watch_clr_all(0)) & set_watch(0); +flush_wayH_d(2) <= (wayH_val(2) and not upd_watch_tid0_wayH(0)) or + (wayH_val(0) and upd_watch_tid0_wayH(1)); +-- Thread 1 Logic +lose_watch(1) <= clr_val or (ex3_store_instr_q and ex3_c_acc and not ex3_thrd_id_q(1)); +ex4_lose_watch_d(1) <= lose_watch(1); +clr_watch(1) <= (ex3_watch_clr_q and ex3_thrd_id_q(1)) or lose_watch(1); +set_watch(1) <= ex3_watch_set_q and ex3_thrd_id_q(1); +-- Determine if a Watch Bit was lost +ex4_lost_wayA(1) <= ex4_lose_watch_q(1) and ex4_way_hit_q(0) and ex4_wayA_val_q(3); +-- CLEAR Watch SET Watch +upd_watch_tid1_wayA <= (clr_watch(1) or ex3_watch_clr_all(1)) & set_watch(1); +flush_wayA_d(3) <= (wayA_val(3) and not upd_watch_tid1_wayA(0)) or + (wayA_val(0) and upd_watch_tid1_wayA(1)); +-- Determine if a Watch Bit was lost +ex4_lost_wayB(1) <= ex4_lose_watch_q(1) and ex4_way_hit_q(1) and ex4_wayB_val_q(3); +-- CLEAR Watch SET Watch +upd_watch_tid1_wayB <= (clr_watch(1) or ex3_watch_clr_all(1)) & set_watch(1); +flush_wayB_d(3) <= (wayB_val(3) and not upd_watch_tid1_wayB(0)) or + (wayB_val(0) and upd_watch_tid1_wayB(1)); +-- Determine if a Watch Bit was lost +ex4_lost_wayC(1) <= ex4_lose_watch_q(1) and ex4_way_hit_q(2) and ex4_wayC_val_q(3); +-- CLEAR Watch SET Watch +upd_watch_tid1_wayC <= (clr_watch(1) or ex3_watch_clr_all(1)) & set_watch(1); +flush_wayC_d(3) <= (wayC_val(3) and not upd_watch_tid1_wayC(0)) or + (wayC_val(0) and upd_watch_tid1_wayC(1)); +-- Determine if a Watch Bit was lost +ex4_lost_wayD(1) <= ex4_lose_watch_q(1) and ex4_way_hit_q(3) and ex4_wayD_val_q(3); +-- CLEAR Watch SET Watch +upd_watch_tid1_wayD <= (clr_watch(1) or ex3_watch_clr_all(1)) & set_watch(1); +flush_wayD_d(3) <= (wayD_val(3) and not upd_watch_tid1_wayD(0)) or + (wayD_val(0) and upd_watch_tid1_wayD(1)); +-- Determine if a Watch Bit was lost +ex4_lost_wayE(1) <= ex4_lose_watch_q(1) and ex4_way_hit_q(4) and ex4_wayE_val_q(3); +-- CLEAR Watch SET Watch +upd_watch_tid1_wayE <= (clr_watch(1) or ex3_watch_clr_all(1)) & set_watch(1); +flush_wayE_d(3) <= (wayE_val(3) and not upd_watch_tid1_wayE(0)) or + (wayE_val(0) and upd_watch_tid1_wayE(1)); +-- Determine if a Watch Bit was lost +ex4_lost_wayF(1) <= ex4_lose_watch_q(1) and ex4_way_hit_q(5) and ex4_wayF_val_q(3); +-- CLEAR Watch SET Watch +upd_watch_tid1_wayF <= (clr_watch(1) or ex3_watch_clr_all(1)) & set_watch(1); +flush_wayF_d(3) <= (wayF_val(3) and not upd_watch_tid1_wayF(0)) or + (wayF_val(0) and upd_watch_tid1_wayF(1)); +-- Determine if a Watch Bit was lost +ex4_lost_wayG(1) <= ex4_lose_watch_q(1) and ex4_way_hit_q(6) and ex4_wayG_val_q(3); +-- CLEAR Watch SET Watch +upd_watch_tid1_wayG <= (clr_watch(1) or ex3_watch_clr_all(1)) & set_watch(1); +flush_wayG_d(3) <= (wayG_val(3) and not upd_watch_tid1_wayG(0)) or + (wayG_val(0) and upd_watch_tid1_wayG(1)); +-- Determine if a Watch Bit was lost +ex4_lost_wayH(1) <= ex4_lose_watch_q(1) and ex4_way_hit_q(7) and ex4_wayH_val_q(3); +-- CLEAR Watch SET Watch +upd_watch_tid1_wayH <= (clr_watch(1) or ex3_watch_clr_all(1)) & set_watch(1); +flush_wayH_d(3) <= (wayH_val(3) and not upd_watch_tid1_wayH(0)) or + (wayH_val(0) and upd_watch_tid1_wayH(1)); +-- Thread 2 Logic +lose_watch(2) <= clr_val or (ex3_store_instr_q and ex3_c_acc and not ex3_thrd_id_q(2)); +ex4_lose_watch_d(2) <= lose_watch(2); +clr_watch(2) <= (ex3_watch_clr_q and ex3_thrd_id_q(2)) or lose_watch(2); +set_watch(2) <= ex3_watch_set_q and ex3_thrd_id_q(2); +-- Determine if a Watch Bit was lost +ex4_lost_wayA(2) <= ex4_lose_watch_q(2) and ex4_way_hit_q(0) and ex4_wayA_val_q(4); +-- CLEAR Watch SET Watch +upd_watch_tid2_wayA <= (clr_watch(2) or ex3_watch_clr_all(2)) & set_watch(2); +flush_wayA_d(4) <= (wayA_val(4) and not upd_watch_tid2_wayA(0)) or + (wayA_val(0) and upd_watch_tid2_wayA(1)); +-- Determine if a Watch Bit was lost +ex4_lost_wayB(2) <= ex4_lose_watch_q(2) and ex4_way_hit_q(1) and ex4_wayB_val_q(4); +-- CLEAR Watch SET Watch +upd_watch_tid2_wayB <= (clr_watch(2) or ex3_watch_clr_all(2)) & set_watch(2); +flush_wayB_d(4) <= (wayB_val(4) and not upd_watch_tid2_wayB(0)) or + (wayB_val(0) and upd_watch_tid2_wayB(1)); +-- Determine if a Watch Bit was lost +ex4_lost_wayC(2) <= ex4_lose_watch_q(2) and ex4_way_hit_q(2) and ex4_wayC_val_q(4); +-- CLEAR Watch SET Watch +upd_watch_tid2_wayC <= (clr_watch(2) or ex3_watch_clr_all(2)) & set_watch(2); +flush_wayC_d(4) <= (wayC_val(4) and not upd_watch_tid2_wayC(0)) or + (wayC_val(0) and upd_watch_tid2_wayC(1)); +-- Determine if a Watch Bit was lost +ex4_lost_wayD(2) <= ex4_lose_watch_q(2) and ex4_way_hit_q(3) and ex4_wayD_val_q(4); +-- CLEAR Watch SET Watch +upd_watch_tid2_wayD <= (clr_watch(2) or ex3_watch_clr_all(2)) & set_watch(2); +flush_wayD_d(4) <= (wayD_val(4) and not upd_watch_tid2_wayD(0)) or + (wayD_val(0) and upd_watch_tid2_wayD(1)); +-- Determine if a Watch Bit was lost +ex4_lost_wayE(2) <= ex4_lose_watch_q(2) and ex4_way_hit_q(4) and ex4_wayE_val_q(4); +-- CLEAR Watch SET Watch +upd_watch_tid2_wayE <= (clr_watch(2) or ex3_watch_clr_all(2)) & set_watch(2); +flush_wayE_d(4) <= (wayE_val(4) and not upd_watch_tid2_wayE(0)) or + (wayE_val(0) and upd_watch_tid2_wayE(1)); +-- Determine if a Watch Bit was lost +ex4_lost_wayF(2) <= ex4_lose_watch_q(2) and ex4_way_hit_q(5) and ex4_wayF_val_q(4); +-- CLEAR Watch SET Watch +upd_watch_tid2_wayF <= (clr_watch(2) or ex3_watch_clr_all(2)) & set_watch(2); +flush_wayF_d(4) <= (wayF_val(4) and not upd_watch_tid2_wayF(0)) or + (wayF_val(0) and upd_watch_tid2_wayF(1)); +-- Determine if a Watch Bit was lost +ex4_lost_wayG(2) <= ex4_lose_watch_q(2) and ex4_way_hit_q(6) and ex4_wayG_val_q(4); +-- CLEAR Watch SET Watch +upd_watch_tid2_wayG <= (clr_watch(2) or ex3_watch_clr_all(2)) & set_watch(2); +flush_wayG_d(4) <= (wayG_val(4) and not upd_watch_tid2_wayG(0)) or + (wayG_val(0) and upd_watch_tid2_wayG(1)); +-- Determine if a Watch Bit was lost +ex4_lost_wayH(2) <= ex4_lose_watch_q(2) and ex4_way_hit_q(7) and ex4_wayH_val_q(4); +-- CLEAR Watch SET Watch +upd_watch_tid2_wayH <= (clr_watch(2) or ex3_watch_clr_all(2)) & set_watch(2); +flush_wayH_d(4) <= (wayH_val(4) and not upd_watch_tid2_wayH(0)) or + (wayH_val(0) and upd_watch_tid2_wayH(1)); +-- Thread 3 Logic +lose_watch(3) <= clr_val or (ex3_store_instr_q and ex3_c_acc and not ex3_thrd_id_q(3)); +ex4_lose_watch_d(3) <= lose_watch(3); +clr_watch(3) <= (ex3_watch_clr_q and ex3_thrd_id_q(3)) or lose_watch(3); +set_watch(3) <= ex3_watch_set_q and ex3_thrd_id_q(3); +-- Determine if a Watch Bit was lost +ex4_lost_wayA(3) <= ex4_lose_watch_q(3) and ex4_way_hit_q(0) and ex4_wayA_val_q(5); +-- CLEAR Watch SET Watch +upd_watch_tid3_wayA <= (clr_watch(3) or ex3_watch_clr_all(3)) & set_watch(3); +flush_wayA_d(5) <= (wayA_val(5) and not upd_watch_tid3_wayA(0)) or + (wayA_val(0) and upd_watch_tid3_wayA(1)); +-- Determine if a Watch Bit was lost +ex4_lost_wayB(3) <= ex4_lose_watch_q(3) and ex4_way_hit_q(1) and ex4_wayB_val_q(5); +-- CLEAR Watch SET Watch +upd_watch_tid3_wayB <= (clr_watch(3) or ex3_watch_clr_all(3)) & set_watch(3); +flush_wayB_d(5) <= (wayB_val(5) and not upd_watch_tid3_wayB(0)) or + (wayB_val(0) and upd_watch_tid3_wayB(1)); +-- Determine if a Watch Bit was lost +ex4_lost_wayC(3) <= ex4_lose_watch_q(3) and ex4_way_hit_q(2) and ex4_wayC_val_q(5); +-- CLEAR Watch SET Watch +upd_watch_tid3_wayC <= (clr_watch(3) or ex3_watch_clr_all(3)) & set_watch(3); +flush_wayC_d(5) <= (wayC_val(5) and not upd_watch_tid3_wayC(0)) or + (wayC_val(0) and upd_watch_tid3_wayC(1)); +-- Determine if a Watch Bit was lost +ex4_lost_wayD(3) <= ex4_lose_watch_q(3) and ex4_way_hit_q(3) and ex4_wayD_val_q(5); +-- CLEAR Watch SET Watch +upd_watch_tid3_wayD <= (clr_watch(3) or ex3_watch_clr_all(3)) & set_watch(3); +flush_wayD_d(5) <= (wayD_val(5) and not upd_watch_tid3_wayD(0)) or + (wayD_val(0) and upd_watch_tid3_wayD(1)); +-- Determine if a Watch Bit was lost +ex4_lost_wayE(3) <= ex4_lose_watch_q(3) and ex4_way_hit_q(4) and ex4_wayE_val_q(5); +-- CLEAR Watch SET Watch +upd_watch_tid3_wayE <= (clr_watch(3) or ex3_watch_clr_all(3)) & set_watch(3); +flush_wayE_d(5) <= (wayE_val(5) and not upd_watch_tid3_wayE(0)) or + (wayE_val(0) and upd_watch_tid3_wayE(1)); +-- Determine if a Watch Bit was lost +ex4_lost_wayF(3) <= ex4_lose_watch_q(3) and ex4_way_hit_q(5) and ex4_wayF_val_q(5); +-- CLEAR Watch SET Watch +upd_watch_tid3_wayF <= (clr_watch(3) or ex3_watch_clr_all(3)) & set_watch(3); +flush_wayF_d(5) <= (wayF_val(5) and not upd_watch_tid3_wayF(0)) or + (wayF_val(0) and upd_watch_tid3_wayF(1)); +-- Determine if a Watch Bit was lost +ex4_lost_wayG(3) <= ex4_lose_watch_q(3) and ex4_way_hit_q(6) and ex4_wayG_val_q(5); +-- CLEAR Watch SET Watch +upd_watch_tid3_wayG <= (clr_watch(3) or ex3_watch_clr_all(3)) & set_watch(3); +flush_wayG_d(5) <= (wayG_val(5) and not upd_watch_tid3_wayG(0)) or + (wayG_val(0) and upd_watch_tid3_wayG(1)); +-- Determine if a Watch Bit was lost +ex4_lost_wayH(3) <= ex4_lose_watch_q(3) and ex4_way_hit_q(7) and ex4_wayH_val_q(5); +-- CLEAR Watch SET Watch +upd_watch_tid3_wayH <= (clr_watch(3) or ex3_watch_clr_all(3)) & set_watch(3); +flush_wayH_d(5) <= (wayH_val(5) and not upd_watch_tid3_wayH(0)) or + (wayH_val(0) and upd_watch_tid3_wayH(1)); +-- Determine if Updating Directory +binv_wayA_upd_d <= (ex3_wayA_hit and binv3_ex3_xuop_upd); +ex3_xuop_lost_watch_wayA <= or_reduce((wayA_val(2 to 5) and not ex3_thrd_id_q)) and ex3_store_instr_q and ex3_c_acc; +ex3_xuop_wayA_upd <= (ex3_wayA_hit and (ex3_xuop_upd_dir or ex3_xuop_lost_watch_wayA)); +ex4_xuop_wayA_upd_d <= ex3_xuop_wayA_upd; +ex5_xuop_wayA_upd_d <= ex4_xuop_wayA_upd_q; +binv_wayB_upd_d <= (ex3_wayB_hit and binv3_ex3_xuop_upd); +ex3_xuop_lost_watch_wayB <= or_reduce((wayB_val(2 to 5) and not ex3_thrd_id_q)) and ex3_store_instr_q and ex3_c_acc; +ex3_xuop_wayB_upd <= (ex3_wayB_hit and (ex3_xuop_upd_dir or ex3_xuop_lost_watch_wayB)); +ex4_xuop_wayB_upd_d <= ex3_xuop_wayB_upd; +ex5_xuop_wayB_upd_d <= ex4_xuop_wayB_upd_q; +binv_wayC_upd_d <= (ex3_wayC_hit and binv3_ex3_xuop_upd); +ex3_xuop_lost_watch_wayC <= or_reduce((wayC_val(2 to 5) and not ex3_thrd_id_q)) and ex3_store_instr_q and ex3_c_acc; +ex3_xuop_wayC_upd <= (ex3_wayC_hit and (ex3_xuop_upd_dir or ex3_xuop_lost_watch_wayC)); +ex4_xuop_wayC_upd_d <= ex3_xuop_wayC_upd; +ex5_xuop_wayC_upd_d <= ex4_xuop_wayC_upd_q; +binv_wayD_upd_d <= (ex3_wayD_hit and binv3_ex3_xuop_upd); +ex3_xuop_lost_watch_wayD <= or_reduce((wayD_val(2 to 5) and not ex3_thrd_id_q)) and ex3_store_instr_q and ex3_c_acc; +ex3_xuop_wayD_upd <= (ex3_wayD_hit and (ex3_xuop_upd_dir or ex3_xuop_lost_watch_wayD)); +ex4_xuop_wayD_upd_d <= ex3_xuop_wayD_upd; +ex5_xuop_wayD_upd_d <= ex4_xuop_wayD_upd_q; +binv_wayE_upd_d <= (ex3_wayE_hit and binv3_ex3_xuop_upd); +ex3_xuop_lost_watch_wayE <= or_reduce((wayE_val(2 to 5) and not ex3_thrd_id_q)) and ex3_store_instr_q and ex3_c_acc; +ex3_xuop_wayE_upd <= (ex3_wayE_hit and (ex3_xuop_upd_dir or ex3_xuop_lost_watch_wayE)); +ex4_xuop_wayE_upd_d <= ex3_xuop_wayE_upd; +ex5_xuop_wayE_upd_d <= ex4_xuop_wayE_upd_q; +binv_wayF_upd_d <= (ex3_wayF_hit and binv3_ex3_xuop_upd); +ex3_xuop_lost_watch_wayF <= or_reduce((wayF_val(2 to 5) and not ex3_thrd_id_q)) and ex3_store_instr_q and ex3_c_acc; +ex3_xuop_wayF_upd <= (ex3_wayF_hit and (ex3_xuop_upd_dir or ex3_xuop_lost_watch_wayF)); +ex4_xuop_wayF_upd_d <= ex3_xuop_wayF_upd; +ex5_xuop_wayF_upd_d <= ex4_xuop_wayF_upd_q; +binv_wayG_upd_d <= (ex3_wayG_hit and binv3_ex3_xuop_upd); +ex3_xuop_lost_watch_wayG <= or_reduce((wayG_val(2 to 5) and not ex3_thrd_id_q)) and ex3_store_instr_q and ex3_c_acc; +ex3_xuop_wayG_upd <= (ex3_wayG_hit and (ex3_xuop_upd_dir or ex3_xuop_lost_watch_wayG)); +ex4_xuop_wayG_upd_d <= ex3_xuop_wayG_upd; +ex5_xuop_wayG_upd_d <= ex4_xuop_wayG_upd_q; +binv_wayH_upd_d <= (ex3_wayH_hit and binv3_ex3_xuop_upd); +ex3_xuop_lost_watch_wayH <= or_reduce((wayH_val(2 to 5) and not ex3_thrd_id_q)) and ex3_store_instr_q and ex3_c_acc; +ex3_xuop_wayH_upd <= (ex3_wayH_hit and (ex3_xuop_upd_dir or ex3_xuop_lost_watch_wayH)); +ex4_xuop_wayH_upd_d <= ex3_xuop_wayH_upd; +ex5_xuop_wayH_upd_d <= ex4_xuop_wayH_upd_q; +-- One of the Ways has a Lock Bit set +binv4_ex4_lock_set <= ex4_wayA_val_q(1) or ex4_wayB_val_q(1) or ex4_wayC_val_q(1) or ex4_wayD_val_q(1) or + ex4_wayE_val_q(1) or ex4_wayF_val_q(1) or ex4_wayG_val_q(1) or ex4_wayH_val_q(1); +-- Threads Watching one of the ways in EX4/BINV4 +binv4_ex4_thrd_watch <= ex4_wayA_val_q(2 to 5) or ex4_wayB_val_q(2 to 5) or ex4_wayC_val_q(2 to 5) or ex4_wayD_val_q(2 to 5) or + ex4_wayE_val_q(2 to 5) or ex4_wayF_val_q(2 to 5) or ex4_wayG_val_q(2 to 5) or ex4_wayH_val_q(2 to 5); +-- Return Prior Watch Bit Value +wayA_watch_value <= (ex4_thrd_id_q(0) and ex4_wayA_val_q(2)) or (ex4_thrd_id_q(1) and ex4_wayA_val_q(3)) or + (ex4_thrd_id_q(2) and ex4_wayA_val_q(4)) or (ex4_thrd_id_q(3) and ex4_wayA_val_q(5)); +wayB_watch_value <= (ex4_thrd_id_q(0) and ex4_wayB_val_q(2)) or (ex4_thrd_id_q(1) and ex4_wayB_val_q(3)) or + (ex4_thrd_id_q(2) and ex4_wayB_val_q(4)) or (ex4_thrd_id_q(3) and ex4_wayB_val_q(5)); +wayC_watch_value <= (ex4_thrd_id_q(0) and ex4_wayC_val_q(2)) or (ex4_thrd_id_q(1) and ex4_wayC_val_q(3)) or + (ex4_thrd_id_q(2) and ex4_wayC_val_q(4)) or (ex4_thrd_id_q(3) and ex4_wayC_val_q(5)); +wayD_watch_value <= (ex4_thrd_id_q(0) and ex4_wayD_val_q(2)) or (ex4_thrd_id_q(1) and ex4_wayD_val_q(3)) or + (ex4_thrd_id_q(2) and ex4_wayD_val_q(4)) or (ex4_thrd_id_q(3) and ex4_wayD_val_q(5)); +wayE_watch_value <= (ex4_thrd_id_q(0) and ex4_wayE_val_q(2)) or (ex4_thrd_id_q(1) and ex4_wayE_val_q(3)) or + (ex4_thrd_id_q(2) and ex4_wayE_val_q(4)) or (ex4_thrd_id_q(3) and ex4_wayE_val_q(5)); +wayF_watch_value <= (ex4_thrd_id_q(0) and ex4_wayF_val_q(2)) or (ex4_thrd_id_q(1) and ex4_wayF_val_q(3)) or + (ex4_thrd_id_q(2) and ex4_wayF_val_q(4)) or (ex4_thrd_id_q(3) and ex4_wayF_val_q(5)); +wayG_watch_value <= (ex4_thrd_id_q(0) and ex4_wayG_val_q(2)) or (ex4_thrd_id_q(1) and ex4_wayG_val_q(3)) or + (ex4_thrd_id_q(2) and ex4_wayG_val_q(4)) or (ex4_thrd_id_q(3) and ex4_wayG_val_q(5)); +wayH_watch_value <= (ex4_thrd_id_q(0) and ex4_wayH_val_q(2)) or (ex4_thrd_id_q(1) and ex4_wayH_val_q(3)) or + (ex4_thrd_id_q(2) and ex4_wayH_val_q(4)) or (ex4_thrd_id_q(3) and ex4_wayH_val_q(5)); +ex4_curr_watch <= (ex4_way_hit_q(0) and wayA_watch_value) or (ex4_way_hit_q(1) and wayB_watch_value) or + (ex4_way_hit_q(2) and wayC_watch_value) or (ex4_way_hit_q(3) and wayD_watch_value) or + (ex4_way_hit_q(4) and wayE_watch_value) or (ex4_way_hit_q(5) and wayF_watch_value) or + (ex4_way_hit_q(6) and wayG_watch_value) or (ex4_way_hit_q(7) and wayH_watch_value); +stm_watchlost_sel <= (ex4_thrd_id_q(0) and stm_watchlost(0)) or (ex4_thrd_id_q(1) and stm_watchlost(1)) or + (ex4_thrd_id_q(2) and stm_watchlost(2)) or (ex4_thrd_id_q(3) and stm_watchlost(3)); +with ex4_watch_set_q select + ex5_cr_watch_d <= stm_watchlost_sel when '0', + ex4_curr_watch when others; +-- Execution Pipe Watch Lost Indicator Logic +-- #################################################### +ex4_lost_watch(0) <= ex4_lost_wayA(0) or ex4_lost_wayB(0) or ex4_lost_wayC(0) or ex4_lost_wayD(0) or + ex4_lost_wayE(0) or ex4_lost_wayF(0) or ex4_lost_wayG(0) or ex4_lost_wayH(0) or + ex4_perr_watch_lost_q(0); +-- Want to still update the STM_WATCHLOST indicator if the DC_DIS=1 + WITH ex4_watchlost_set_q(0) SELECT ex4_lost_watch_upd(0) <= ex4_lost_watch(0) when '0', + ex4_l_fld_b1_q when others; +ex4_lost_watch(1) <= ex4_lost_wayA(1) or ex4_lost_wayB(1) or ex4_lost_wayC(1) or ex4_lost_wayD(1) or + ex4_lost_wayE(1) or ex4_lost_wayF(1) or ex4_lost_wayG(1) or ex4_lost_wayH(1) or + ex4_perr_watch_lost_q(1); +-- Want to still update the STM_WATCHLOST indicator if the DC_DIS=1 + WITH ex4_watchlost_set_q(1) SELECT ex4_lost_watch_upd(1) <= ex4_lost_watch(1) when '0', + ex4_l_fld_b1_q when others; +ex4_lost_watch(2) <= ex4_lost_wayA(2) or ex4_lost_wayB(2) or ex4_lost_wayC(2) or ex4_lost_wayD(2) or + ex4_lost_wayE(2) or ex4_lost_wayF(2) or ex4_lost_wayG(2) or ex4_lost_wayH(2) or + ex4_perr_watch_lost_q(2); +-- Want to still update the STM_WATCHLOST indicator if the DC_DIS=1 + WITH ex4_watchlost_set_q(2) SELECT ex4_lost_watch_upd(2) <= ex4_lost_watch(2) when '0', + ex4_l_fld_b1_q when others; +ex4_lost_watch(3) <= ex4_lost_wayA(3) or ex4_lost_wayB(3) or ex4_lost_wayC(3) or ex4_lost_wayD(3) or + ex4_lost_wayE(3) or ex4_lost_wayF(3) or ex4_lost_wayG(3) or ex4_lost_wayH(3) or + ex4_perr_watch_lost_q(3); +-- Want to still update the STM_WATCHLOST indicator if the DC_DIS=1 + WITH ex4_watchlost_set_q(3) SELECT ex4_lost_watch_upd(3) <= ex4_lost_watch(3) when '0', + ex4_l_fld_b1_q when others; +-- LDAWX Hit Way collided with Reload Clear of Same Way +ex4_watchSet_coll_d <= rel_val_stg2_q and ex3_watch_set_q and (rel24_congr_cl_q = ex3_congr_cl_q); +watchSet_rel_way_coll <= gate((reload_way_clr_q and ex4_way_hit_q), ex4_watchSet_coll_q); +watchSet_rel_coll_val <= gate(ex4_thrd_id_q, or_reduce(watchSet_rel_way_coll)); +ex5_lost_watch_upd_d <= ex4_lost_watch_upd or watchSet_rel_coll_val or ex4_multihit_watch_lost; +ex4_watchlost_set_d <= ex3_watch_clr_all; +ex5_watchlost_set_d <= ex4_lost_watch or ex4_watchlost_set_q or watchSet_rel_coll_val or ex4_multihit_watch_lost; +ex5_watch_clr_all_d <= gate(ex4_watch_clr_all_q, not ex4_stg_flush); +ex6_watch_clr_all_d <= gate(ex5_watch_clr_all_q, not ex5_stg_flush); +ex5_watch_clr_all_val_d <= or_reduce(ex4_watch_clr_all_q); +-- EX4Invalidate/BINV/RELOAD Bypass Execution Op hit/miss Logic +-- #################################################### +-- Hit Detect +u_th0i: tagA_hit_b <= not tagA_hit; +u_hw0i: xu_op_hit_wayA_b <= not (wayA_val(0) and tagA_hit); +u_hw0: xu_op_hit_wayA <= not xu_op_hit_wayA_b; +u_hw0b: xu_op_hit_wayA_dly_b <= not xu_op_hit_wayA; +-- Hit Detect +u_th1i: tagB_hit_b <= not tagB_hit; +u_hw1i: xu_op_hit_wayB_b <= not (wayB_val(0) and tagB_hit); +u_hw1: xu_op_hit_wayB <= not xu_op_hit_wayB_b; +u_hw1b: xu_op_hit_wayB_dly_b <= not xu_op_hit_wayB; +-- Hit Detect +u_th2i: tagC_hit_b <= not tagC_hit; +u_hw2i: xu_op_hit_wayC_b <= not (wayC_val(0) and tagC_hit); +u_hw2: xu_op_hit_wayC <= not xu_op_hit_wayC_b; +u_hw2b: xu_op_hit_wayC_dly_b <= not xu_op_hit_wayC; +-- Hit Detect +u_th3i: tagD_hit_b <= not tagD_hit; +u_hw3i: xu_op_hit_wayD_b <= not (wayD_val(0) and tagD_hit); +u_hw3: xu_op_hit_wayD <= not xu_op_hit_wayD_b; +u_hw3b: xu_op_hit_wayD_dly_b <= not xu_op_hit_wayD; +-- Hit Detect +u_th4i: tagE_hit_b <= not tagE_hit; +u_hw4i: xu_op_hit_wayE_b <= not (wayE_val(0) and tagE_hit); +u_hw4: xu_op_hit_wayE <= not xu_op_hit_wayE_b; +u_hw4b: xu_op_hit_wayE_dly_b <= not xu_op_hit_wayE; +-- Hit Detect +u_th5i: tagF_hit_b <= not tagF_hit; +u_hw5i: xu_op_hit_wayF_b <= not (wayF_val(0) and tagF_hit); +u_hw5: xu_op_hit_wayF <= not xu_op_hit_wayF_b; +u_hw5b: xu_op_hit_wayF_dly_b <= not xu_op_hit_wayF; +-- Hit Detect +u_th6i: tagG_hit_b <= not tagG_hit; +u_hw6i: xu_op_hit_wayG_b <= not (wayG_val(0) and tagG_hit); +u_hw6: xu_op_hit_wayG <= not xu_op_hit_wayG_b; +u_hw6b: xu_op_hit_wayG_dly_b <= not xu_op_hit_wayG; +-- Hit Detect +u_th7i: tagH_hit_b <= not tagH_hit; +u_hw7i: xu_op_hit_wayH_b <= not (wayH_val(0) and tagH_hit); +u_hw7: xu_op_hit_wayH <= not xu_op_hit_wayH_b; +u_hw7b: xu_op_hit_wayH_dly_b <= not xu_op_hit_wayH; +-- Invalidate Lock Bit Detect +inval_clr_lck <= (inval_clr_lck_wA_q and binv_wayA_upd_q) or (inval_clr_lck_wB_q and binv_wayB_upd_q) or + (inval_clr_lck_wC_q and binv_wayC_upd_q) or (inval_clr_lck_wD_q and binv_wayD_upd_q) or + (inval_clr_lck_wE_q and binv_wayE_upd_q) or (inval_clr_lck_wF_q and binv_wayF_upd_q) or + (inval_clr_lck_wG_q and binv_wayG_upd_q) or (inval_clr_lck_wH_q and binv_wayH_upd_q); +xucr0_cslc_xuop_d <= inval_clr_lck and ex4_xuop_val; +xucr0_cslc_binv_d <= rel_lock_lost or dcperr_lock_lost_q or ex4_perr_lck_lost_q or + ex4_multihit_lock_lost or binv5_inval_lock_val_q or (rel_l1dump_cslc_q and not rel4_ecc_err); +ex3_cClass_upd_way_a <= ex3_cClass_wayA_hit; +ex3_cClass_upd_way_b <= ex3_cClass_wayB_hit; +ex3_cClass_upd_way_c <= ex3_cClass_wayC_hit; +ex3_cClass_upd_way_d <= ex3_cClass_wayD_hit; +ex3_cClass_upd_way_e <= ex3_cClass_wayE_hit; +ex3_cClass_upd_way_f <= ex3_cClass_wayF_hit; +ex3_cClass_upd_way_g <= ex3_cClass_wayG_hit; +ex3_cClass_upd_way_h <= ex3_cClass_wayH_hit; +-- Multihit Error Detected +-- #################################################### +-- Level 1 +u_mh1_a01: hit_and_01_b <= not( xu_op_hit_wayA and xu_op_hit_wayB ); +u_mh1_a23: hit_and_23_b <= not( xu_op_hit_wayC and xu_op_hit_wayD ); +u_mh1_a45: hit_and_45_b <= not( xu_op_hit_wayE and xu_op_hit_wayF ); +u_mh1_a67: hit_and_67_b <= not( xu_op_hit_wayG and xu_op_hit_wayH ); +u_mh1_o01: hit_or_01_b <= not( xu_op_hit_wayA or xu_op_hit_wayB ); +u_mh1_o23: hit_or_23_b <= not( xu_op_hit_wayC or xu_op_hit_wayD ); +u_mh1_o45: hit_or_45_b <= not( xu_op_hit_wayE or xu_op_hit_wayF ); +u_mh1_o67: hit_or_67_b <= not( xu_op_hit_wayG or xu_op_hit_wayH ); +u_mh1_o13: hit_or_13_b <= not( xu_op_hit_wayB or xu_op_hit_wayD ); +u_mh1_o57: hit_or_57_b <= not( xu_op_hit_wayF or xu_op_hit_wayH ); +-- Level 2 +u_mh2_o0123: hit_or_0123 <= not( hit_or_01_b and hit_or_23_b ); +u_mh2_o4567: hit_or_4567 <= not( hit_or_45_b and hit_or_67_b ); +u_mh2_o1357: hit_or_1357 <= not( hit_or_13_b and hit_or_57_b ); +u_mh2_o2367: hit_or_2367 <= not( hit_or_23_b and hit_or_67_b ); +u_mh2_a0123: hit_and_0123 <= not( hit_or_01_b or hit_or_23_b ); +u_mh2_a4567: hit_and_4567 <= not( hit_or_45_b or hit_or_67_b ); +u_mh2_err0: multi_hit_err2_0 <= not( hit_and_01_b and hit_and_23_b ); +u_mh2_err1: multi_hit_err2_1 <= not( hit_and_45_b and hit_and_67_b ); +-- Level 3 +u_mh3_o: hit_or_01234567_b <= not( hit_or_0123 or hit_or_4567 ); +u_mh3_err0: multi_hit_err3_b(0) <= not( hit_or_0123 and hit_or_4567 ); +u_mh3_err1: multi_hit_err3_b(1) <= not( hit_and_0123 or hit_and_4567 ); +u_mh3_err2: multi_hit_err3_b(2) <= not( multi_hit_err2_0 or multi_hit_err2_1 ); +u_henc_0: hit_enc_b(0) <= not( hit_or_4567 ); +u_henc_1: hit_enc_b(1) <= not( hit_or_2367 ); +u_henc_2: hit_enc_b(2) <= not( hit_or_1357 ); +-- Level 4 +-- Multihit Error Detected +u_mh4_0: ex3_dir_multihit_val_0 <= not( multi_hit_err3_b(0) and multi_hit_err3_b(1) ); +u_mh4_1: ex3_dir_multihit_val_1 <= not( multi_hit_err3_b(2) and inj_dir_multihit_b ); +-- Level 5 +u_mh5: ex3_dir_multihit_val_b <= not( ex3_dir_multihit_val_0 or ex3_dir_multihit_val_1 ); +-- Level 6 +u_mh6: ex3_dir_multihit_val <= not ex3_dir_multihit_val_b ; +ex4_n_lsu_ddmh_flush_b_d <= (others=>ex3_dir_multihit_val); +ex4_dir_multihit_val <= binv4_ex4_dir_val_q and not ex4_dir_multihit_val_b_q; +inj_dir_multihit_b <= not (inj_dir_multihit_q and binv3_ex3_dir_val); +ex4_multihit_watch_lost <= gate(binv4_ex4_thrd_watch, ex4_dir_multihit_val); +ex4_multihit_lock_lost <= binv4_ex4_lock_set and ex4_dir_multihit_val; +-- #################################################### +-- Parity Error Detect +-- #################################################### +ex4_err_det_way_d(0) <= perr_way_det_wayA; +perr_way_det_wayA <= wayA_val(0) and ex3_tag_way_perr(0); +dirpar_err_lock_lost(0) <= wayA_val(1) and ex3_tag_way_perr(0); +perr_wayA_watch_lost <= gate(wayA_val(2 to 5),ex3_tag_way_perr(0)); +ex4_err_det_way_d(1) <= perr_way_det_wayB; +perr_way_det_wayB <= wayB_val(0) and ex3_tag_way_perr(1); +dirpar_err_lock_lost(1) <= wayB_val(1) and ex3_tag_way_perr(1); +perr_wayB_watch_lost <= gate(wayB_val(2 to 5),ex3_tag_way_perr(1)); +ex4_err_det_way_d(2) <= perr_way_det_wayC; +perr_way_det_wayC <= wayC_val(0) and ex3_tag_way_perr(2); +dirpar_err_lock_lost(2) <= wayC_val(1) and ex3_tag_way_perr(2); +perr_wayC_watch_lost <= gate(wayC_val(2 to 5),ex3_tag_way_perr(2)); +ex4_err_det_way_d(3) <= perr_way_det_wayD; +perr_way_det_wayD <= wayD_val(0) and ex3_tag_way_perr(3); +dirpar_err_lock_lost(3) <= wayD_val(1) and ex3_tag_way_perr(3); +perr_wayD_watch_lost <= gate(wayD_val(2 to 5),ex3_tag_way_perr(3)); +ex4_err_det_way_d(4) <= perr_way_det_wayE; +perr_way_det_wayE <= wayE_val(0) and ex3_tag_way_perr(4); +dirpar_err_lock_lost(4) <= wayE_val(1) and ex3_tag_way_perr(4); +perr_wayE_watch_lost <= gate(wayE_val(2 to 5),ex3_tag_way_perr(4)); +ex4_err_det_way_d(5) <= perr_way_det_wayF; +perr_way_det_wayF <= wayF_val(0) and ex3_tag_way_perr(5); +dirpar_err_lock_lost(5) <= wayF_val(1) and ex3_tag_way_perr(5); +perr_wayF_watch_lost <= gate(wayF_val(2 to 5),ex3_tag_way_perr(5)); +ex4_err_det_way_d(6) <= perr_way_det_wayG; +perr_way_det_wayG <= wayG_val(0) and ex3_tag_way_perr(6); +dirpar_err_lock_lost(6) <= wayG_val(1) and ex3_tag_way_perr(6); +perr_wayG_watch_lost <= gate(wayG_val(2 to 5),ex3_tag_way_perr(6)); +ex4_err_det_way_d(7) <= perr_way_det_wayH; +perr_way_det_wayH <= wayH_val(0) and ex3_tag_way_perr(7); +dirpar_err_lock_lost(7) <= wayH_val(1) and ex3_tag_way_perr(7); +perr_wayH_watch_lost <= gate(wayH_val(2 to 5),ex3_tag_way_perr(7)); +-- Lock Bit Lost due to Parity Error +ex4_perr_lck_lost_d <= or_reduce(dirpar_err_lock_lost); +-- Watch Lost due to Parity Error +ex4_perr_watch_lost_d <= perr_wayA_watch_lost or perr_wayB_watch_lost or perr_wayC_watch_lost or perr_wayD_watch_lost or + perr_wayE_watch_lost or perr_wayF_watch_lost or perr_wayG_watch_lost or perr_wayH_watch_lost; +-- Parity Error Detected +ex3_dir_perr_val <= perr_way_det_wayA or perr_way_det_wayB or perr_way_det_wayC or perr_way_det_wayD or + perr_way_det_wayE or perr_way_det_wayF or perr_way_det_wayG or perr_way_det_wayH; +-- Staging out Directory Error +ex4_dir_err_val_d <= ex3_dir_perr_val; +ex5_dir_err_val_d <= ex4_dir_err_val_q or ex4_dir_multihit_val; +ex6_dir_err_val_d <= ex5_dir_err_val_q; +derr2_stg_act_d <= ex6_dir_err_val_q; +derr3_stg_act_d <= derr2_stg_act_q; +derr4_stg_act_d <= derr3_stg_act_q; +derr5_stg_act_d <= derr4_stg_act_q; +-- #################################################### +-- Hit/Miss Detect +-- #################################################### +-- Execution Pipe Hit/Miss +ex3L1Hit: ex3_l1hit <= not hit_or_01234567_b; +ex3L1Miss: ex3_l1miss <= not ex3_l1hit; +ex3_hit <= not ex3_l1miss; +ex4_miss <= not ex4_miss_q; +ex4_way_hit_d <= not (xu_op_hit_wayA_dly_b & xu_op_hit_wayB_dly_b & xu_op_hit_wayC_dly_b & xu_op_hit_wayD_dly_b & + xu_op_hit_wayE_dly_b & xu_op_hit_wayF_dly_b & xu_op_hit_wayG_dly_b & xu_op_hit_wayH_dly_b); +ex5_way_hit_d <= ex4_way_hit_q; +ex6_way_hit_d <= ex5_way_hit_q; +-- EX3 Way Hit Encode for upper address into Data Cache Array +ex3_xuop_up_addr_b <= hit_enc_b(0 to 2); +rel_dcarr_addr_sel <= (others=>rel_dcarr_addr_en); +rel_dcarr_addr_sel_b <= (others=>(not rel_dcarr_addr_en)); +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Back-Invalidated Watched/Locked Line detection, +-- I need to do it late since instructions in the ahead of +-- back-invalidate could have set the watch/lost bit +-- Back-Invalidate does not look at instructions ahead of pipe, +-- since they might get flushed and will get bad results +-- Also includes Multihit Error Detect case +-- Staging out congruence class compares +congr_cl_ex3_ex4_cmp_d <= congr_cl_ex2_ex3_cmp_q; +congr_cl_ex3_ex5_cmp_d <= congr_cl_ex2_ex4_cmp_q; +congr_cl_ex3_ex6_cmp_d <= congr_cl_ex2_ex5_cmp_q; +congr_cl_ex4_ex5_cmp_d <= congr_cl_ex3_ex4_cmp_q; +congr_cl_ex4_ex6_cmp_d <= congr_cl_ex3_ex5_cmp_q; +congr_cl_ex4_ex7_cmp_d <= congr_cl_ex3_ex6_cmp_q; +-- Ways updated in other stages +binv4_ex4_way_upd <= binv_wayA_upd1 & binv_wayB_upd1 & binv_wayC_upd1 & binv_wayD_upd1 & + binv_wayE_upd1 & binv_wayF_upd1 & binv_wayG_upd1 & binv_wayH_upd1; +binv5_ex5_way_upd <= binv_wayA_upd2_q & binv_wayB_upd2_q & binv_wayC_upd2_q & binv_wayD_upd2_q & + binv_wayE_upd2_q & binv_wayF_upd2_q & binv_wayG_upd2_q & binv_wayH_upd2_q; +binv6_ex6_way_upd <= binv_wayA_upd3_q & binv_wayB_upd3_q & binv_wayC_upd3_q & binv_wayD_upd3_q & + binv_wayE_upd3_q & binv_wayF_upd3_q & binv_wayG_upd3_q & binv_wayH_upd3_q; +binv7_ex7_way_upd_d <= binv6_ex6_way_upd; +-- Data of ways updated in other stages +binv4_ex4_dir_data <= gate(flush_wayA_data1(1 to 5), binv4_ex4_way_upd(0)) or gate(flush_wayB_data1(1 to 5), binv4_ex4_way_upd(1)) or + gate(flush_wayC_data1(1 to 5), binv4_ex4_way_upd(2)) or gate(flush_wayD_data1(1 to 5), binv4_ex4_way_upd(3)) or + gate(flush_wayE_data1(1 to 5), binv4_ex4_way_upd(4)) or gate(flush_wayF_data1(1 to 5), binv4_ex4_way_upd(5)) or + gate(flush_wayG_data1(1 to 5), binv4_ex4_way_upd(6)) or gate(flush_wayH_data1(1 to 5), binv4_ex4_way_upd(7)); +binv5_ex5_dir_data_d <= binv4_ex4_dir_data; +binv6_ex6_dir_data_d <= binv5_ex5_dir_data_q; +binv7_ex7_dir_data_d <= binv6_ex6_dir_data_q; +-- None Bypass Locked Line lost indicator +binv4_inval_lck <= inval_clr_lck and back_inval_stg4_q and not binv4_coll_val; +-- None Bypass Watch Lost indicator +binv4_inval_watch <= gate(ex4_lost_watch, (back_inval_stg4_q and not binv4_coll_val)); +-- Stage Bypass Select +binv4_ex5_coll <= (back_inval_stg4_q or ex4_dir_multihit_val) and congr_cl_ex4_ex5_cmp_q and or_reduce(ex4_way_hit_q and binv5_ex5_way_upd) and p0_wren_d; +binv4_ex6_coll <= (back_inval_stg4_q or ex4_dir_multihit_val) and congr_cl_ex4_ex6_cmp_q and or_reduce(ex4_way_hit_q and binv6_ex6_way_upd) and p0_wren_q; +binv4_ex7_coll <= (back_inval_stg4_q or ex4_dir_multihit_val) and congr_cl_ex4_ex7_cmp_q and or_reduce(ex4_way_hit_q and binv7_ex7_way_upd_q) and p0_wren_stg_q; +binv4_coll_val <= binv4_ex5_coll or binv4_ex6_coll or binv4_ex7_coll; +-- Priority Calculation +binv4_pri_byp_sel(0) <= binv4_ex5_coll; +binv4_pri_byp_sel(1) <= binv4_ex6_coll and not binv4_ex5_coll; +binv4_pri_byp_sel(2) <= binv4_ex7_coll and not (binv4_ex6_coll or binv4_ex5_coll); +-- Data Bypass +binv4_byp_dir_data <= gate(binv5_ex5_dir_data_q, binv4_pri_byp_sel(0)) or + gate(binv6_ex6_dir_data_q, binv4_pri_byp_sel(1)) or + gate(binv7_ex7_dir_data_q, binv4_pri_byp_sel(2)); +-- Back-Invalidate invalidated a watched line +binv5_inval_watch_val_d <= (binv4_byp_dir_data(2 to 5) and not binv4_ex4_dir_data(2 to 5)) or binv4_inval_watch; +-- Back-Invalidate invalidated a locked line +binv5_inval_lock_val_d <= (binv4_byp_dir_data(1) and not binv4_ex4_dir_data(1)) or binv4_inval_lck; +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Watch Lost due to DCI +dci_watch_lost <= (others=>dci_compl_q); +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- #################################################### +-- Resource Conflict Flushes +-- #################################################### +-- Determine if another thread is modifying any of the Directory bits, Need to flush if this thread targets same congruence class and way +congr_cl_ex3_upd_wayA <= congr_cl_ex2_ex3_cmp_q and not ex3_thrd_m_q and ex3_xuop_wayA_upd and not ex3_stg_flush; +congr_cl_ex4_upd_wayA <= congr_cl_ex2_ex4_cmp_q and not ex4_thrd_m_q and ex4_xuop_wayA_upd_q and not ex4_stg_flush; +congr_cl_ex5_upd_wayA <= congr_cl_ex2_ex5_cmp_q and not ex5_thrd_m_q and ex5_xuop_wayA_upd_q and not ex5_stg_flush; +congr_cl_m_upd_wayA_d <= congr_cl_ex3_upd_wayA or congr_cl_ex4_upd_wayA or congr_cl_ex5_upd_wayA; +-- causing a flush for the thread that matches congruence class and directory way being updated by a different thread +ex3_cClass_wayA_hit <= fxu_pipe_val and congr_cl_m_upd_wayA_q and wayA_val(0); +-- Determine if another thread is modifying any of the Directory bits, Need to flush if this thread targets same congruence class and way +congr_cl_ex3_upd_wayB <= congr_cl_ex2_ex3_cmp_q and not ex3_thrd_m_q and ex3_xuop_wayB_upd and not ex3_stg_flush; +congr_cl_ex4_upd_wayB <= congr_cl_ex2_ex4_cmp_q and not ex4_thrd_m_q and ex4_xuop_wayB_upd_q and not ex4_stg_flush; +congr_cl_ex5_upd_wayB <= congr_cl_ex2_ex5_cmp_q and not ex5_thrd_m_q and ex5_xuop_wayB_upd_q and not ex5_stg_flush; +congr_cl_m_upd_wayB_d <= congr_cl_ex3_upd_wayB or congr_cl_ex4_upd_wayB or congr_cl_ex5_upd_wayB; +-- causing a flush for the thread that matches congruence class and directory way being updated by a different thread +ex3_cClass_wayB_hit <= fxu_pipe_val and congr_cl_m_upd_wayB_q and wayB_val(0); +-- Determine if another thread is modifying any of the Directory bits, Need to flush if this thread targets same congruence class and way +congr_cl_ex3_upd_wayC <= congr_cl_ex2_ex3_cmp_q and not ex3_thrd_m_q and ex3_xuop_wayC_upd and not ex3_stg_flush; +congr_cl_ex4_upd_wayC <= congr_cl_ex2_ex4_cmp_q and not ex4_thrd_m_q and ex4_xuop_wayC_upd_q and not ex4_stg_flush; +congr_cl_ex5_upd_wayC <= congr_cl_ex2_ex5_cmp_q and not ex5_thrd_m_q and ex5_xuop_wayC_upd_q and not ex5_stg_flush; +congr_cl_m_upd_wayC_d <= congr_cl_ex3_upd_wayC or congr_cl_ex4_upd_wayC or congr_cl_ex5_upd_wayC; +-- causing a flush for the thread that matches congruence class and directory way being updated by a different thread +ex3_cClass_wayC_hit <= fxu_pipe_val and congr_cl_m_upd_wayC_q and wayC_val(0); +-- Determine if another thread is modifying any of the Directory bits, Need to flush if this thread targets same congruence class and way +congr_cl_ex3_upd_wayD <= congr_cl_ex2_ex3_cmp_q and not ex3_thrd_m_q and ex3_xuop_wayD_upd and not ex3_stg_flush; +congr_cl_ex4_upd_wayD <= congr_cl_ex2_ex4_cmp_q and not ex4_thrd_m_q and ex4_xuop_wayD_upd_q and not ex4_stg_flush; +congr_cl_ex5_upd_wayD <= congr_cl_ex2_ex5_cmp_q and not ex5_thrd_m_q and ex5_xuop_wayD_upd_q and not ex5_stg_flush; +congr_cl_m_upd_wayD_d <= congr_cl_ex3_upd_wayD or congr_cl_ex4_upd_wayD or congr_cl_ex5_upd_wayD; +-- causing a flush for the thread that matches congruence class and directory way being updated by a different thread +ex3_cClass_wayD_hit <= fxu_pipe_val and congr_cl_m_upd_wayD_q and wayD_val(0); +-- Determine if another thread is modifying any of the Directory bits, Need to flush if this thread targets same congruence class and way +congr_cl_ex3_upd_wayE <= congr_cl_ex2_ex3_cmp_q and not ex3_thrd_m_q and ex3_xuop_wayE_upd and not ex3_stg_flush; +congr_cl_ex4_upd_wayE <= congr_cl_ex2_ex4_cmp_q and not ex4_thrd_m_q and ex4_xuop_wayE_upd_q and not ex4_stg_flush; +congr_cl_ex5_upd_wayE <= congr_cl_ex2_ex5_cmp_q and not ex5_thrd_m_q and ex5_xuop_wayE_upd_q and not ex5_stg_flush; +congr_cl_m_upd_wayE_d <= congr_cl_ex3_upd_wayE or congr_cl_ex4_upd_wayE or congr_cl_ex5_upd_wayE; +-- causing a flush for the thread that matches congruence class and directory way being updated by a different thread +ex3_cClass_wayE_hit <= fxu_pipe_val and congr_cl_m_upd_wayE_q and wayE_val(0); +-- Determine if another thread is modifying any of the Directory bits, Need to flush if this thread targets same congruence class and way +congr_cl_ex3_upd_wayF <= congr_cl_ex2_ex3_cmp_q and not ex3_thrd_m_q and ex3_xuop_wayF_upd and not ex3_stg_flush; +congr_cl_ex4_upd_wayF <= congr_cl_ex2_ex4_cmp_q and not ex4_thrd_m_q and ex4_xuop_wayF_upd_q and not ex4_stg_flush; +congr_cl_ex5_upd_wayF <= congr_cl_ex2_ex5_cmp_q and not ex5_thrd_m_q and ex5_xuop_wayF_upd_q and not ex5_stg_flush; +congr_cl_m_upd_wayF_d <= congr_cl_ex3_upd_wayF or congr_cl_ex4_upd_wayF or congr_cl_ex5_upd_wayF; +-- causing a flush for the thread that matches congruence class and directory way being updated by a different thread +ex3_cClass_wayF_hit <= fxu_pipe_val and congr_cl_m_upd_wayF_q and wayF_val(0); +-- Determine if another thread is modifying any of the Directory bits, Need to flush if this thread targets same congruence class and way +congr_cl_ex3_upd_wayG <= congr_cl_ex2_ex3_cmp_q and not ex3_thrd_m_q and ex3_xuop_wayG_upd and not ex3_stg_flush; +congr_cl_ex4_upd_wayG <= congr_cl_ex2_ex4_cmp_q and not ex4_thrd_m_q and ex4_xuop_wayG_upd_q and not ex4_stg_flush; +congr_cl_ex5_upd_wayG <= congr_cl_ex2_ex5_cmp_q and not ex5_thrd_m_q and ex5_xuop_wayG_upd_q and not ex5_stg_flush; +congr_cl_m_upd_wayG_d <= congr_cl_ex3_upd_wayG or congr_cl_ex4_upd_wayG or congr_cl_ex5_upd_wayG; +-- causing a flush for the thread that matches congruence class and directory way being updated by a different thread +ex3_cClass_wayG_hit <= fxu_pipe_val and congr_cl_m_upd_wayG_q and wayG_val(0); +-- Determine if another thread is modifying any of the Directory bits, Need to flush if this thread targets same congruence class and way +congr_cl_ex3_upd_wayH <= congr_cl_ex2_ex3_cmp_q and not ex3_thrd_m_q and ex3_xuop_wayH_upd and not ex3_stg_flush; +congr_cl_ex4_upd_wayH <= congr_cl_ex2_ex4_cmp_q and not ex4_thrd_m_q and ex4_xuop_wayH_upd_q and not ex4_stg_flush; +congr_cl_ex5_upd_wayH <= congr_cl_ex2_ex5_cmp_q and not ex5_thrd_m_q and ex5_xuop_wayH_upd_q and not ex5_stg_flush; +congr_cl_m_upd_wayH_d <= congr_cl_ex3_upd_wayH or congr_cl_ex4_upd_wayH or congr_cl_ex5_upd_wayH; +-- causing a flush for the thread that matches congruence class and directory way being updated by a different thread +ex3_cClass_wayH_hit <= fxu_pipe_val and congr_cl_m_upd_wayH_q and wayH_val(0); +-- Watch Clear udate in the pipe for a different thread +ex3_wclr_all_upd_val <= ex3_watch_clr_all_q and not ex3_thrd_m_q and not ex3_stg_flush; +ex4_wclr_all_upd_val <= ex4_wclr_all_val_q and not ex4_thrd_m_q and not ex4_stg_flush; +ex5_wclr_all_upd_val <= ex5_wclr_all_val_q and not ex5_thrd_m_q and not ex5_stg_flush; +ex6_wclr_all_upd_val <= ex6_wclr_all_val_q and not ex6_thrd_m_q; +-- causing a flush for the thread that is trying to access the directory when a different thread is doing a watch clear all +ex3_wclr_all_upd_d <= ex3_wclr_all_upd_val or ex4_wclr_all_upd_val or ex5_wclr_all_upd_val or ex6_wclr_all_upd_val; +-- #################################################### +-- Reload Pipe +-- #################################################### +-- Reload Path Directory Valid Bits Muxing +-- Reload Stage 1 +-- Select Congruence Class Way A +with rel_congr_cl_q select + rel_arr_wayA_val <= + congr_cl0_wA_q when "000000", + congr_cl1_wA_q when "000001", + congr_cl2_wA_q when "000010", + congr_cl3_wA_q when "000011", + congr_cl4_wA_q when "000100", + congr_cl5_wA_q when "000101", + congr_cl6_wA_q when "000110", + congr_cl7_wA_q when "000111", + congr_cl8_wA_q when "001000", + congr_cl9_wA_q when "001001", + congr_cl10_wA_q when "001010", + congr_cl11_wA_q when "001011", + congr_cl12_wA_q when "001100", + congr_cl13_wA_q when "001101", + congr_cl14_wA_q when "001110", + congr_cl15_wA_q when "001111", + congr_cl16_wA_q when "010000", + congr_cl17_wA_q when "010001", + congr_cl18_wA_q when "010010", + congr_cl19_wA_q when "010011", + congr_cl20_wA_q when "010100", + congr_cl21_wA_q when "010101", + congr_cl22_wA_q when "010110", + congr_cl23_wA_q when "010111", + congr_cl24_wA_q when "011000", + congr_cl25_wA_q when "011001", + congr_cl26_wA_q when "011010", + congr_cl27_wA_q when "011011", + congr_cl28_wA_q when "011100", + congr_cl29_wA_q when "011101", + congr_cl30_wA_q when "011110", + congr_cl31_wA_q when "011111", + congr_cl32_wA_q when "100000", + congr_cl33_wA_q when "100001", + congr_cl34_wA_q when "100010", + congr_cl35_wA_q when "100011", + congr_cl36_wA_q when "100100", + congr_cl37_wA_q when "100101", + congr_cl38_wA_q when "100110", + congr_cl39_wA_q when "100111", + congr_cl40_wA_q when "101000", + congr_cl41_wA_q when "101001", + congr_cl42_wA_q when "101010", + congr_cl43_wA_q when "101011", + congr_cl44_wA_q when "101100", + congr_cl45_wA_q when "101101", + congr_cl46_wA_q when "101110", + congr_cl47_wA_q when "101111", + congr_cl48_wA_q when "110000", + congr_cl49_wA_q when "110001", + congr_cl50_wA_q when "110010", + congr_cl51_wA_q when "110011", + congr_cl52_wA_q when "110100", + congr_cl53_wA_q when "110101", + congr_cl54_wA_q when "110110", + congr_cl55_wA_q when "110111", + congr_cl56_wA_q when "111000", + congr_cl57_wA_q when "111001", + congr_cl58_wA_q when "111010", + congr_cl59_wA_q when "111011", + congr_cl60_wA_q when "111100", + congr_cl61_wA_q when "111101", + congr_cl62_wA_q when "111110", + congr_cl63_wA_q when others; +p1_arr_wayA_rd <= rel_arr_wayA_val; +-- Select Congruence Class Way B +with rel_congr_cl_q select + rel_arr_wayB_val <= + congr_cl0_wB_q when "000000", + congr_cl1_wB_q when "000001", + congr_cl2_wB_q when "000010", + congr_cl3_wB_q when "000011", + congr_cl4_wB_q when "000100", + congr_cl5_wB_q when "000101", + congr_cl6_wB_q when "000110", + congr_cl7_wB_q when "000111", + congr_cl8_wB_q when "001000", + congr_cl9_wB_q when "001001", + congr_cl10_wB_q when "001010", + congr_cl11_wB_q when "001011", + congr_cl12_wB_q when "001100", + congr_cl13_wB_q when "001101", + congr_cl14_wB_q when "001110", + congr_cl15_wB_q when "001111", + congr_cl16_wB_q when "010000", + congr_cl17_wB_q when "010001", + congr_cl18_wB_q when "010010", + congr_cl19_wB_q when "010011", + congr_cl20_wB_q when "010100", + congr_cl21_wB_q when "010101", + congr_cl22_wB_q when "010110", + congr_cl23_wB_q when "010111", + congr_cl24_wB_q when "011000", + congr_cl25_wB_q when "011001", + congr_cl26_wB_q when "011010", + congr_cl27_wB_q when "011011", + congr_cl28_wB_q when "011100", + congr_cl29_wB_q when "011101", + congr_cl30_wB_q when "011110", + congr_cl31_wB_q when "011111", + congr_cl32_wB_q when "100000", + congr_cl33_wB_q when "100001", + congr_cl34_wB_q when "100010", + congr_cl35_wB_q when "100011", + congr_cl36_wB_q when "100100", + congr_cl37_wB_q when "100101", + congr_cl38_wB_q when "100110", + congr_cl39_wB_q when "100111", + congr_cl40_wB_q when "101000", + congr_cl41_wB_q when "101001", + congr_cl42_wB_q when "101010", + congr_cl43_wB_q when "101011", + congr_cl44_wB_q when "101100", + congr_cl45_wB_q when "101101", + congr_cl46_wB_q when "101110", + congr_cl47_wB_q when "101111", + congr_cl48_wB_q when "110000", + congr_cl49_wB_q when "110001", + congr_cl50_wB_q when "110010", + congr_cl51_wB_q when "110011", + congr_cl52_wB_q when "110100", + congr_cl53_wB_q when "110101", + congr_cl54_wB_q when "110110", + congr_cl55_wB_q when "110111", + congr_cl56_wB_q when "111000", + congr_cl57_wB_q when "111001", + congr_cl58_wB_q when "111010", + congr_cl59_wB_q when "111011", + congr_cl60_wB_q when "111100", + congr_cl61_wB_q when "111101", + congr_cl62_wB_q when "111110", + congr_cl63_wB_q when others; +p1_arr_wayB_rd <= rel_arr_wayB_val; +-- Select Congruence Class Way C +with rel_congr_cl_q select + rel_arr_wayC_val <= + congr_cl0_wC_q when "000000", + congr_cl1_wC_q when "000001", + congr_cl2_wC_q when "000010", + congr_cl3_wC_q when "000011", + congr_cl4_wC_q when "000100", + congr_cl5_wC_q when "000101", + congr_cl6_wC_q when "000110", + congr_cl7_wC_q when "000111", + congr_cl8_wC_q when "001000", + congr_cl9_wC_q when "001001", + congr_cl10_wC_q when "001010", + congr_cl11_wC_q when "001011", + congr_cl12_wC_q when "001100", + congr_cl13_wC_q when "001101", + congr_cl14_wC_q when "001110", + congr_cl15_wC_q when "001111", + congr_cl16_wC_q when "010000", + congr_cl17_wC_q when "010001", + congr_cl18_wC_q when "010010", + congr_cl19_wC_q when "010011", + congr_cl20_wC_q when "010100", + congr_cl21_wC_q when "010101", + congr_cl22_wC_q when "010110", + congr_cl23_wC_q when "010111", + congr_cl24_wC_q when "011000", + congr_cl25_wC_q when "011001", + congr_cl26_wC_q when "011010", + congr_cl27_wC_q when "011011", + congr_cl28_wC_q when "011100", + congr_cl29_wC_q when "011101", + congr_cl30_wC_q when "011110", + congr_cl31_wC_q when "011111", + congr_cl32_wC_q when "100000", + congr_cl33_wC_q when "100001", + congr_cl34_wC_q when "100010", + congr_cl35_wC_q when "100011", + congr_cl36_wC_q when "100100", + congr_cl37_wC_q when "100101", + congr_cl38_wC_q when "100110", + congr_cl39_wC_q when "100111", + congr_cl40_wC_q when "101000", + congr_cl41_wC_q when "101001", + congr_cl42_wC_q when "101010", + congr_cl43_wC_q when "101011", + congr_cl44_wC_q when "101100", + congr_cl45_wC_q when "101101", + congr_cl46_wC_q when "101110", + congr_cl47_wC_q when "101111", + congr_cl48_wC_q when "110000", + congr_cl49_wC_q when "110001", + congr_cl50_wC_q when "110010", + congr_cl51_wC_q when "110011", + congr_cl52_wC_q when "110100", + congr_cl53_wC_q when "110101", + congr_cl54_wC_q when "110110", + congr_cl55_wC_q when "110111", + congr_cl56_wC_q when "111000", + congr_cl57_wC_q when "111001", + congr_cl58_wC_q when "111010", + congr_cl59_wC_q when "111011", + congr_cl60_wC_q when "111100", + congr_cl61_wC_q when "111101", + congr_cl62_wC_q when "111110", + congr_cl63_wC_q when others; +p1_arr_wayC_rd <= rel_arr_wayC_val; +-- Select Congruence Class Way D +with rel_congr_cl_q select + rel_arr_wayD_val <= + congr_cl0_wD_q when "000000", + congr_cl1_wD_q when "000001", + congr_cl2_wD_q when "000010", + congr_cl3_wD_q when "000011", + congr_cl4_wD_q when "000100", + congr_cl5_wD_q when "000101", + congr_cl6_wD_q when "000110", + congr_cl7_wD_q when "000111", + congr_cl8_wD_q when "001000", + congr_cl9_wD_q when "001001", + congr_cl10_wD_q when "001010", + congr_cl11_wD_q when "001011", + congr_cl12_wD_q when "001100", + congr_cl13_wD_q when "001101", + congr_cl14_wD_q when "001110", + congr_cl15_wD_q when "001111", + congr_cl16_wD_q when "010000", + congr_cl17_wD_q when "010001", + congr_cl18_wD_q when "010010", + congr_cl19_wD_q when "010011", + congr_cl20_wD_q when "010100", + congr_cl21_wD_q when "010101", + congr_cl22_wD_q when "010110", + congr_cl23_wD_q when "010111", + congr_cl24_wD_q when "011000", + congr_cl25_wD_q when "011001", + congr_cl26_wD_q when "011010", + congr_cl27_wD_q when "011011", + congr_cl28_wD_q when "011100", + congr_cl29_wD_q when "011101", + congr_cl30_wD_q when "011110", + congr_cl31_wD_q when "011111", + congr_cl32_wD_q when "100000", + congr_cl33_wD_q when "100001", + congr_cl34_wD_q when "100010", + congr_cl35_wD_q when "100011", + congr_cl36_wD_q when "100100", + congr_cl37_wD_q when "100101", + congr_cl38_wD_q when "100110", + congr_cl39_wD_q when "100111", + congr_cl40_wD_q when "101000", + congr_cl41_wD_q when "101001", + congr_cl42_wD_q when "101010", + congr_cl43_wD_q when "101011", + congr_cl44_wD_q when "101100", + congr_cl45_wD_q when "101101", + congr_cl46_wD_q when "101110", + congr_cl47_wD_q when "101111", + congr_cl48_wD_q when "110000", + congr_cl49_wD_q when "110001", + congr_cl50_wD_q when "110010", + congr_cl51_wD_q when "110011", + congr_cl52_wD_q when "110100", + congr_cl53_wD_q when "110101", + congr_cl54_wD_q when "110110", + congr_cl55_wD_q when "110111", + congr_cl56_wD_q when "111000", + congr_cl57_wD_q when "111001", + congr_cl58_wD_q when "111010", + congr_cl59_wD_q when "111011", + congr_cl60_wD_q when "111100", + congr_cl61_wD_q when "111101", + congr_cl62_wD_q when "111110", + congr_cl63_wD_q when others; +p1_arr_wayD_rd <= rel_arr_wayD_val; +-- Select Congruence Class Way E +with rel_congr_cl_q select + rel_arr_wayE_val <= + congr_cl0_wE_q when "000000", + congr_cl1_wE_q when "000001", + congr_cl2_wE_q when "000010", + congr_cl3_wE_q when "000011", + congr_cl4_wE_q when "000100", + congr_cl5_wE_q when "000101", + congr_cl6_wE_q when "000110", + congr_cl7_wE_q when "000111", + congr_cl8_wE_q when "001000", + congr_cl9_wE_q when "001001", + congr_cl10_wE_q when "001010", + congr_cl11_wE_q when "001011", + congr_cl12_wE_q when "001100", + congr_cl13_wE_q when "001101", + congr_cl14_wE_q when "001110", + congr_cl15_wE_q when "001111", + congr_cl16_wE_q when "010000", + congr_cl17_wE_q when "010001", + congr_cl18_wE_q when "010010", + congr_cl19_wE_q when "010011", + congr_cl20_wE_q when "010100", + congr_cl21_wE_q when "010101", + congr_cl22_wE_q when "010110", + congr_cl23_wE_q when "010111", + congr_cl24_wE_q when "011000", + congr_cl25_wE_q when "011001", + congr_cl26_wE_q when "011010", + congr_cl27_wE_q when "011011", + congr_cl28_wE_q when "011100", + congr_cl29_wE_q when "011101", + congr_cl30_wE_q when "011110", + congr_cl31_wE_q when "011111", + congr_cl32_wE_q when "100000", + congr_cl33_wE_q when "100001", + congr_cl34_wE_q when "100010", + congr_cl35_wE_q when "100011", + congr_cl36_wE_q when "100100", + congr_cl37_wE_q when "100101", + congr_cl38_wE_q when "100110", + congr_cl39_wE_q when "100111", + congr_cl40_wE_q when "101000", + congr_cl41_wE_q when "101001", + congr_cl42_wE_q when "101010", + congr_cl43_wE_q when "101011", + congr_cl44_wE_q when "101100", + congr_cl45_wE_q when "101101", + congr_cl46_wE_q when "101110", + congr_cl47_wE_q when "101111", + congr_cl48_wE_q when "110000", + congr_cl49_wE_q when "110001", + congr_cl50_wE_q when "110010", + congr_cl51_wE_q when "110011", + congr_cl52_wE_q when "110100", + congr_cl53_wE_q when "110101", + congr_cl54_wE_q when "110110", + congr_cl55_wE_q when "110111", + congr_cl56_wE_q when "111000", + congr_cl57_wE_q when "111001", + congr_cl58_wE_q when "111010", + congr_cl59_wE_q when "111011", + congr_cl60_wE_q when "111100", + congr_cl61_wE_q when "111101", + congr_cl62_wE_q when "111110", + congr_cl63_wE_q when others; +p1_arr_wayE_rd <= rel_arr_wayE_val; +-- Select Congruence Class Way F +with rel_congr_cl_q select + rel_arr_wayF_val <= + congr_cl0_wF_q when "000000", + congr_cl1_wF_q when "000001", + congr_cl2_wF_q when "000010", + congr_cl3_wF_q when "000011", + congr_cl4_wF_q when "000100", + congr_cl5_wF_q when "000101", + congr_cl6_wF_q when "000110", + congr_cl7_wF_q when "000111", + congr_cl8_wF_q when "001000", + congr_cl9_wF_q when "001001", + congr_cl10_wF_q when "001010", + congr_cl11_wF_q when "001011", + congr_cl12_wF_q when "001100", + congr_cl13_wF_q when "001101", + congr_cl14_wF_q when "001110", + congr_cl15_wF_q when "001111", + congr_cl16_wF_q when "010000", + congr_cl17_wF_q when "010001", + congr_cl18_wF_q when "010010", + congr_cl19_wF_q when "010011", + congr_cl20_wF_q when "010100", + congr_cl21_wF_q when "010101", + congr_cl22_wF_q when "010110", + congr_cl23_wF_q when "010111", + congr_cl24_wF_q when "011000", + congr_cl25_wF_q when "011001", + congr_cl26_wF_q when "011010", + congr_cl27_wF_q when "011011", + congr_cl28_wF_q when "011100", + congr_cl29_wF_q when "011101", + congr_cl30_wF_q when "011110", + congr_cl31_wF_q when "011111", + congr_cl32_wF_q when "100000", + congr_cl33_wF_q when "100001", + congr_cl34_wF_q when "100010", + congr_cl35_wF_q when "100011", + congr_cl36_wF_q when "100100", + congr_cl37_wF_q when "100101", + congr_cl38_wF_q when "100110", + congr_cl39_wF_q when "100111", + congr_cl40_wF_q when "101000", + congr_cl41_wF_q when "101001", + congr_cl42_wF_q when "101010", + congr_cl43_wF_q when "101011", + congr_cl44_wF_q when "101100", + congr_cl45_wF_q when "101101", + congr_cl46_wF_q when "101110", + congr_cl47_wF_q when "101111", + congr_cl48_wF_q when "110000", + congr_cl49_wF_q when "110001", + congr_cl50_wF_q when "110010", + congr_cl51_wF_q when "110011", + congr_cl52_wF_q when "110100", + congr_cl53_wF_q when "110101", + congr_cl54_wF_q when "110110", + congr_cl55_wF_q when "110111", + congr_cl56_wF_q when "111000", + congr_cl57_wF_q when "111001", + congr_cl58_wF_q when "111010", + congr_cl59_wF_q when "111011", + congr_cl60_wF_q when "111100", + congr_cl61_wF_q when "111101", + congr_cl62_wF_q when "111110", + congr_cl63_wF_q when others; +p1_arr_wayF_rd <= rel_arr_wayF_val; +-- Select Congruence Class Way G +with rel_congr_cl_q select + rel_arr_wayG_val <= + congr_cl0_wG_q when "000000", + congr_cl1_wG_q when "000001", + congr_cl2_wG_q when "000010", + congr_cl3_wG_q when "000011", + congr_cl4_wG_q when "000100", + congr_cl5_wG_q when "000101", + congr_cl6_wG_q when "000110", + congr_cl7_wG_q when "000111", + congr_cl8_wG_q when "001000", + congr_cl9_wG_q when "001001", + congr_cl10_wG_q when "001010", + congr_cl11_wG_q when "001011", + congr_cl12_wG_q when "001100", + congr_cl13_wG_q when "001101", + congr_cl14_wG_q when "001110", + congr_cl15_wG_q when "001111", + congr_cl16_wG_q when "010000", + congr_cl17_wG_q when "010001", + congr_cl18_wG_q when "010010", + congr_cl19_wG_q when "010011", + congr_cl20_wG_q when "010100", + congr_cl21_wG_q when "010101", + congr_cl22_wG_q when "010110", + congr_cl23_wG_q when "010111", + congr_cl24_wG_q when "011000", + congr_cl25_wG_q when "011001", + congr_cl26_wG_q when "011010", + congr_cl27_wG_q when "011011", + congr_cl28_wG_q when "011100", + congr_cl29_wG_q when "011101", + congr_cl30_wG_q when "011110", + congr_cl31_wG_q when "011111", + congr_cl32_wG_q when "100000", + congr_cl33_wG_q when "100001", + congr_cl34_wG_q when "100010", + congr_cl35_wG_q when "100011", + congr_cl36_wG_q when "100100", + congr_cl37_wG_q when "100101", + congr_cl38_wG_q when "100110", + congr_cl39_wG_q when "100111", + congr_cl40_wG_q when "101000", + congr_cl41_wG_q when "101001", + congr_cl42_wG_q when "101010", + congr_cl43_wG_q when "101011", + congr_cl44_wG_q when "101100", + congr_cl45_wG_q when "101101", + congr_cl46_wG_q when "101110", + congr_cl47_wG_q when "101111", + congr_cl48_wG_q when "110000", + congr_cl49_wG_q when "110001", + congr_cl50_wG_q when "110010", + congr_cl51_wG_q when "110011", + congr_cl52_wG_q when "110100", + congr_cl53_wG_q when "110101", + congr_cl54_wG_q when "110110", + congr_cl55_wG_q when "110111", + congr_cl56_wG_q when "111000", + congr_cl57_wG_q when "111001", + congr_cl58_wG_q when "111010", + congr_cl59_wG_q when "111011", + congr_cl60_wG_q when "111100", + congr_cl61_wG_q when "111101", + congr_cl62_wG_q when "111110", + congr_cl63_wG_q when others; +p1_arr_wayG_rd <= rel_arr_wayG_val; +-- Select Congruence Class Way H +with rel_congr_cl_q select + rel_arr_wayH_val <= + congr_cl0_wH_q when "000000", + congr_cl1_wH_q when "000001", + congr_cl2_wH_q when "000010", + congr_cl3_wH_q when "000011", + congr_cl4_wH_q when "000100", + congr_cl5_wH_q when "000101", + congr_cl6_wH_q when "000110", + congr_cl7_wH_q when "000111", + congr_cl8_wH_q when "001000", + congr_cl9_wH_q when "001001", + congr_cl10_wH_q when "001010", + congr_cl11_wH_q when "001011", + congr_cl12_wH_q when "001100", + congr_cl13_wH_q when "001101", + congr_cl14_wH_q when "001110", + congr_cl15_wH_q when "001111", + congr_cl16_wH_q when "010000", + congr_cl17_wH_q when "010001", + congr_cl18_wH_q when "010010", + congr_cl19_wH_q when "010011", + congr_cl20_wH_q when "010100", + congr_cl21_wH_q when "010101", + congr_cl22_wH_q when "010110", + congr_cl23_wH_q when "010111", + congr_cl24_wH_q when "011000", + congr_cl25_wH_q when "011001", + congr_cl26_wH_q when "011010", + congr_cl27_wH_q when "011011", + congr_cl28_wH_q when "011100", + congr_cl29_wH_q when "011101", + congr_cl30_wH_q when "011110", + congr_cl31_wH_q when "011111", + congr_cl32_wH_q when "100000", + congr_cl33_wH_q when "100001", + congr_cl34_wH_q when "100010", + congr_cl35_wH_q when "100011", + congr_cl36_wH_q when "100100", + congr_cl37_wH_q when "100101", + congr_cl38_wH_q when "100110", + congr_cl39_wH_q when "100111", + congr_cl40_wH_q when "101000", + congr_cl41_wH_q when "101001", + congr_cl42_wH_q when "101010", + congr_cl43_wH_q when "101011", + congr_cl44_wH_q when "101100", + congr_cl45_wH_q when "101101", + congr_cl46_wH_q when "101110", + congr_cl47_wH_q when "101111", + congr_cl48_wH_q when "110000", + congr_cl49_wH_q when "110001", + congr_cl50_wH_q when "110010", + congr_cl51_wH_q when "110011", + congr_cl52_wH_q when "110100", + congr_cl53_wH_q when "110101", + congr_cl54_wH_q when "110110", + congr_cl55_wH_q when "110111", + congr_cl56_wH_q when "111000", + congr_cl57_wH_q when "111001", + congr_cl58_wH_q when "111010", + congr_cl59_wH_q when "111011", + congr_cl60_wH_q when "111100", + congr_cl61_wH_q when "111101", + congr_cl62_wH_q when "111110", + congr_cl63_wH_q when others; +p1_arr_wayH_rd <= rel_arr_wayH_val; +-- #################################################### +-- Reload Pipe Bypass +-- #################################################### +-- Reload13 Bypass Stages +-- Determine if there is any updates in later stages to the same congruence class +congr_cl_rel13_ex3_cmp_d <= (rel_early_congr_cl = ex2_congr_cl_q); +congr_cl_rel13_ex4_cmp_d <= (rel_early_congr_cl = ex3_congr_cl_q); +congr_cl_rel13_ex5_cmp_d <= (rel_early_congr_cl = ex4_congr_cl_q); +congr_cl_rel13_ex6_cmp_d <= (rel_early_congr_cl = ex5_congr_cl_q); +congr_cl_rel13_relu_cmp_d <= (rel_early_congr_cl = rel24_congr_cl_q); +congr_cl_rel13_relu_s_cmp_d <= (rel_early_congr_cl = relu_congr_cl_q); +congr_cl_rel13_rel_upd_cmp_d <= (rel_early_congr_cl = relu_s_congr_cl_q); +congr_cl_rel13_p0_cmp <= congr_cl_rel13_ex6_cmp_q and p0_wren_cpy_q; +congr_cl_rel13_p1_cmp <= congr_cl_rel13_rel_upd_cmp_q and p1_wren_cpy_q; +-- Determine if there is any updates in later stages to the same congruence class +congr_cl_rel13_ex3_m <= congr_cl_rel13_ex3_cmp_q and (ex3_lock_set_q or back_inval_stg3_q); +congr_cl_rel13_ex4_m <= congr_cl_rel13_ex4_cmp_q and (ex4_lock_set_q or back_inval_stg4_q); +congr_cl_rel13_ex5_m <= congr_cl_rel13_ex5_cmp_q and (ex5_lock_set_q or back_inval_stg5_q); +congr_cl_rel13_relu_m <= congr_cl_rel13_relu_cmp_q and rel_val_stgu_q; +congr_cl_rel13_relu_s_m <= congr_cl_rel13_relu_s_cmp_q and p1_upd_val; +-- WayA Bypass Calculation +congr_cl_rel13_wayA_byp(1) <= congr_cl_rel13_ex3_m and ex3_wayA_hit; +congr_cl_rel13_wayA_byp(2) <= congr_cl_rel13_relu_m and reload_wayA_upd_q; +congr_cl_rel13_wayA_byp(3) <= congr_cl_rel13_ex4_m and binv_wayA_upd_q; +congr_cl_rel13_wayA_byp(4) <= congr_cl_rel13_relu_s_m and reload_wayA_upd2_q; +congr_cl_rel13_wayA_byp(5) <= congr_cl_rel13_ex5_m and binv_wayA_upd2_q; +congr_cl_rel13_wayA_byp(6) <= congr_cl_rel13_p1_cmp and reload_wayA_upd3_q; +congr_cl_rel13_wayA_byp(7) <= congr_cl_rel13_p0_cmp and binv_wayA_upd3_q; +-- WayA Bypass Valid +rel24_wayA_fxubyp_val_d <= congr_cl_rel13_wayA_byp(1) or congr_cl_rel13_wayA_byp(3) or + congr_cl_rel13_wayA_byp(5) or congr_cl_rel13_wayA_byp(7); +rel24_wayA_relbyp_val_d <= congr_cl_rel13_wayA_byp(2) or congr_cl_rel13_wayA_byp(4) or + congr_cl_rel13_wayA_byp(6); +rel24_wayA_byp_sel <= rel24_wayA_fxubyp_val_q & rel24_wayA_relbyp_val_q; +-- Late Stages Priority Selection +congr_cl_rel13_wayA_sel(2) <= congr_cl_rel13_wayA_byp(2); +congr_cl_rel13_wayA_sel(3) <= congr_cl_rel13_wayA_byp(3) and not congr_cl_rel13_wayA_byp(2); +congr_cl_rel13_wayA_sel(4) <= congr_cl_rel13_wayA_byp(4) and not or_reduce(congr_cl_rel13_wayA_byp(2 to 3)); +congr_cl_rel13_wayA_sel(5) <= congr_cl_rel13_wayA_byp(5) and not or_reduce(congr_cl_rel13_wayA_byp(2 to 4)); +congr_cl_rel13_wayA_sel(6) <= congr_cl_rel13_wayA_byp(6) and not or_reduce(congr_cl_rel13_wayA_byp(2 to 5)); +congr_cl_rel13_wayA_sel(7) <= congr_cl_rel13_wayA_byp(7) and not or_reduce(congr_cl_rel13_wayA_byp(2 to 6)); +-- ArrayRead/LATE Stage Priority Selection +rel_wayA_late_sel <= or_reduce(congr_cl_rel13_wayA_byp(2 to 7)); +rel_wayA_later_stg_pri <= gate(p1_arr_wayA_rd, not rel_wayA_late_sel) or + gate(reload_wayA, congr_cl_rel13_wayA_sel(2)) or + gate(flush_wayA_q, congr_cl_rel13_wayA_sel(3)) or + gate(reload_wayA_data_q, congr_cl_rel13_wayA_sel(4)) or + gate(flush_wayA_data_q, congr_cl_rel13_wayA_sel(5)) or + gate(reload_wayA_data2_q, congr_cl_rel13_wayA_sel(6)) or + gate(flush_wayA_data2_q, congr_cl_rel13_wayA_sel(7)); +-- EX3/RELU Stage Priority Selection +rel_wayA_early_sel <= congr_cl_rel13_wayA_byp(1); +rel_wayA_early_stg_pri <= flush_wayA_d; +-- Stage/ARRAY Priority Selection +rel_wayA_stg_val <= (others=>(rel_wayA_early_sel)); +rel_wayA_stg_val_b <= (others=>(not(rel_wayA_early_sel))); +rel_wayA_val <= not rel_wayA_val_b_q; +rel_wayA_val_stg_d <= rel_wayA_val; +-- WayB Bypass Calculation +congr_cl_rel13_wayB_byp(1) <= congr_cl_rel13_ex3_m and ex3_wayB_hit; +congr_cl_rel13_wayB_byp(2) <= congr_cl_rel13_relu_m and reload_wayB_upd_q; +congr_cl_rel13_wayB_byp(3) <= congr_cl_rel13_ex4_m and binv_wayB_upd_q; +congr_cl_rel13_wayB_byp(4) <= congr_cl_rel13_relu_s_m and reload_wayB_upd2_q; +congr_cl_rel13_wayB_byp(5) <= congr_cl_rel13_ex5_m and binv_wayB_upd2_q; +congr_cl_rel13_wayB_byp(6) <= congr_cl_rel13_p1_cmp and reload_wayB_upd3_q; +congr_cl_rel13_wayB_byp(7) <= congr_cl_rel13_p0_cmp and binv_wayB_upd3_q; +-- WayB Bypass Valid +rel24_wayB_fxubyp_val_d <= congr_cl_rel13_wayB_byp(1) or congr_cl_rel13_wayB_byp(3) or + congr_cl_rel13_wayB_byp(5) or congr_cl_rel13_wayB_byp(7); +rel24_wayB_relbyp_val_d <= congr_cl_rel13_wayB_byp(2) or congr_cl_rel13_wayB_byp(4) or + congr_cl_rel13_wayB_byp(6); +rel24_wayB_byp_sel <= rel24_wayB_fxubyp_val_q & rel24_wayB_relbyp_val_q; +-- Late Stages Priority Selection +congr_cl_rel13_wayB_sel(2) <= congr_cl_rel13_wayB_byp(2); +congr_cl_rel13_wayB_sel(3) <= congr_cl_rel13_wayB_byp(3) and not congr_cl_rel13_wayB_byp(2); +congr_cl_rel13_wayB_sel(4) <= congr_cl_rel13_wayB_byp(4) and not or_reduce(congr_cl_rel13_wayB_byp(2 to 3)); +congr_cl_rel13_wayB_sel(5) <= congr_cl_rel13_wayB_byp(5) and not or_reduce(congr_cl_rel13_wayB_byp(2 to 4)); +congr_cl_rel13_wayB_sel(6) <= congr_cl_rel13_wayB_byp(6) and not or_reduce(congr_cl_rel13_wayB_byp(2 to 5)); +congr_cl_rel13_wayB_sel(7) <= congr_cl_rel13_wayB_byp(7) and not or_reduce(congr_cl_rel13_wayB_byp(2 to 6)); +-- ArrayRead/LATE Stage Priority Selection +rel_wayB_late_sel <= or_reduce(congr_cl_rel13_wayB_byp(2 to 7)); +rel_wayB_later_stg_pri <= gate(p1_arr_wayB_rd, not rel_wayB_late_sel) or + gate(reload_wayB, congr_cl_rel13_wayB_sel(2)) or + gate(flush_wayB_q, congr_cl_rel13_wayB_sel(3)) or + gate(reload_wayB_data_q, congr_cl_rel13_wayB_sel(4)) or + gate(flush_wayB_data_q, congr_cl_rel13_wayB_sel(5)) or + gate(reload_wayB_data2_q, congr_cl_rel13_wayB_sel(6)) or + gate(flush_wayB_data2_q, congr_cl_rel13_wayB_sel(7)); +-- EX3/RELU Stage Priority Selection +rel_wayB_early_sel <= congr_cl_rel13_wayB_byp(1); +rel_wayB_early_stg_pri <= flush_wayB_d; +-- Stage/ARRAY Priority Selection +rel_wayB_stg_val <= (others=>(rel_wayB_early_sel)); +rel_wayB_stg_val_b <= (others=>(not(rel_wayB_early_sel))); +rel_wayB_val <= not rel_wayB_val_b_q; +rel_wayB_val_stg_d <= rel_wayB_val; +-- WayC Bypass Calculation +congr_cl_rel13_wayC_byp(1) <= congr_cl_rel13_ex3_m and ex3_wayC_hit; +congr_cl_rel13_wayC_byp(2) <= congr_cl_rel13_relu_m and reload_wayC_upd_q; +congr_cl_rel13_wayC_byp(3) <= congr_cl_rel13_ex4_m and binv_wayC_upd_q; +congr_cl_rel13_wayC_byp(4) <= congr_cl_rel13_relu_s_m and reload_wayC_upd2_q; +congr_cl_rel13_wayC_byp(5) <= congr_cl_rel13_ex5_m and binv_wayC_upd2_q; +congr_cl_rel13_wayC_byp(6) <= congr_cl_rel13_p1_cmp and reload_wayC_upd3_q; +congr_cl_rel13_wayC_byp(7) <= congr_cl_rel13_p0_cmp and binv_wayC_upd3_q; +-- WayC Bypass Valid +rel24_wayC_fxubyp_val_d <= congr_cl_rel13_wayC_byp(1) or congr_cl_rel13_wayC_byp(3) or + congr_cl_rel13_wayC_byp(5) or congr_cl_rel13_wayC_byp(7); +rel24_wayC_relbyp_val_d <= congr_cl_rel13_wayC_byp(2) or congr_cl_rel13_wayC_byp(4) or + congr_cl_rel13_wayC_byp(6); +rel24_wayC_byp_sel <= rel24_wayC_fxubyp_val_q & rel24_wayC_relbyp_val_q; +-- Late Stages Priority Selection +congr_cl_rel13_wayC_sel(2) <= congr_cl_rel13_wayC_byp(2); +congr_cl_rel13_wayC_sel(3) <= congr_cl_rel13_wayC_byp(3) and not congr_cl_rel13_wayC_byp(2); +congr_cl_rel13_wayC_sel(4) <= congr_cl_rel13_wayC_byp(4) and not or_reduce(congr_cl_rel13_wayC_byp(2 to 3)); +congr_cl_rel13_wayC_sel(5) <= congr_cl_rel13_wayC_byp(5) and not or_reduce(congr_cl_rel13_wayC_byp(2 to 4)); +congr_cl_rel13_wayC_sel(6) <= congr_cl_rel13_wayC_byp(6) and not or_reduce(congr_cl_rel13_wayC_byp(2 to 5)); +congr_cl_rel13_wayC_sel(7) <= congr_cl_rel13_wayC_byp(7) and not or_reduce(congr_cl_rel13_wayC_byp(2 to 6)); +-- ArrayRead/LATE Stage Priority Selection +rel_wayC_late_sel <= or_reduce(congr_cl_rel13_wayC_byp(2 to 7)); +rel_wayC_later_stg_pri <= gate(p1_arr_wayC_rd, not rel_wayC_late_sel) or + gate(reload_wayC, congr_cl_rel13_wayC_sel(2)) or + gate(flush_wayC_q, congr_cl_rel13_wayC_sel(3)) or + gate(reload_wayC_data_q, congr_cl_rel13_wayC_sel(4)) or + gate(flush_wayC_data_q, congr_cl_rel13_wayC_sel(5)) or + gate(reload_wayC_data2_q, congr_cl_rel13_wayC_sel(6)) or + gate(flush_wayC_data2_q, congr_cl_rel13_wayC_sel(7)); +-- EX3/RELU Stage Priority Selection +rel_wayC_early_sel <= congr_cl_rel13_wayC_byp(1); +rel_wayC_early_stg_pri <= flush_wayC_d; +-- Stage/ARRAY Priority Selection +rel_wayC_stg_val <= (others=>(rel_wayC_early_sel)); +rel_wayC_stg_val_b <= (others=>(not(rel_wayC_early_sel))); +rel_wayC_val <= not rel_wayC_val_b_q; +rel_wayC_val_stg_d <= rel_wayC_val; +-- WayD Bypass Calculation +congr_cl_rel13_wayD_byp(1) <= congr_cl_rel13_ex3_m and ex3_wayD_hit; +congr_cl_rel13_wayD_byp(2) <= congr_cl_rel13_relu_m and reload_wayD_upd_q; +congr_cl_rel13_wayD_byp(3) <= congr_cl_rel13_ex4_m and binv_wayD_upd_q; +congr_cl_rel13_wayD_byp(4) <= congr_cl_rel13_relu_s_m and reload_wayD_upd2_q; +congr_cl_rel13_wayD_byp(5) <= congr_cl_rel13_ex5_m and binv_wayD_upd2_q; +congr_cl_rel13_wayD_byp(6) <= congr_cl_rel13_p1_cmp and reload_wayD_upd3_q; +congr_cl_rel13_wayD_byp(7) <= congr_cl_rel13_p0_cmp and binv_wayD_upd3_q; +-- WayD Bypass Valid +rel24_wayD_fxubyp_val_d <= congr_cl_rel13_wayD_byp(1) or congr_cl_rel13_wayD_byp(3) or + congr_cl_rel13_wayD_byp(5) or congr_cl_rel13_wayD_byp(7); +rel24_wayD_relbyp_val_d <= congr_cl_rel13_wayD_byp(2) or congr_cl_rel13_wayD_byp(4) or + congr_cl_rel13_wayD_byp(6); +rel24_wayD_byp_sel <= rel24_wayD_fxubyp_val_q & rel24_wayD_relbyp_val_q; +-- Late Stages Priority Selection +congr_cl_rel13_wayD_sel(2) <= congr_cl_rel13_wayD_byp(2); +congr_cl_rel13_wayD_sel(3) <= congr_cl_rel13_wayD_byp(3) and not congr_cl_rel13_wayD_byp(2); +congr_cl_rel13_wayD_sel(4) <= congr_cl_rel13_wayD_byp(4) and not or_reduce(congr_cl_rel13_wayD_byp(2 to 3)); +congr_cl_rel13_wayD_sel(5) <= congr_cl_rel13_wayD_byp(5) and not or_reduce(congr_cl_rel13_wayD_byp(2 to 4)); +congr_cl_rel13_wayD_sel(6) <= congr_cl_rel13_wayD_byp(6) and not or_reduce(congr_cl_rel13_wayD_byp(2 to 5)); +congr_cl_rel13_wayD_sel(7) <= congr_cl_rel13_wayD_byp(7) and not or_reduce(congr_cl_rel13_wayD_byp(2 to 6)); +-- ArrayRead/LATE Stage Priority Selection +rel_wayD_late_sel <= or_reduce(congr_cl_rel13_wayD_byp(2 to 7)); +rel_wayD_later_stg_pri <= gate(p1_arr_wayD_rd, not rel_wayD_late_sel) or + gate(reload_wayD, congr_cl_rel13_wayD_sel(2)) or + gate(flush_wayD_q, congr_cl_rel13_wayD_sel(3)) or + gate(reload_wayD_data_q, congr_cl_rel13_wayD_sel(4)) or + gate(flush_wayD_data_q, congr_cl_rel13_wayD_sel(5)) or + gate(reload_wayD_data2_q, congr_cl_rel13_wayD_sel(6)) or + gate(flush_wayD_data2_q, congr_cl_rel13_wayD_sel(7)); +-- EX3/RELU Stage Priority Selection +rel_wayD_early_sel <= congr_cl_rel13_wayD_byp(1); +rel_wayD_early_stg_pri <= flush_wayD_d; +-- Stage/ARRAY Priority Selection +rel_wayD_stg_val <= (others=>(rel_wayD_early_sel)); +rel_wayD_stg_val_b <= (others=>(not(rel_wayD_early_sel))); +rel_wayD_val <= not rel_wayD_val_b_q; +rel_wayD_val_stg_d <= rel_wayD_val; +-- WayE Bypass Calculation +congr_cl_rel13_wayE_byp(1) <= congr_cl_rel13_ex3_m and ex3_wayE_hit; +congr_cl_rel13_wayE_byp(2) <= congr_cl_rel13_relu_m and reload_wayE_upd_q; +congr_cl_rel13_wayE_byp(3) <= congr_cl_rel13_ex4_m and binv_wayE_upd_q; +congr_cl_rel13_wayE_byp(4) <= congr_cl_rel13_relu_s_m and reload_wayE_upd2_q; +congr_cl_rel13_wayE_byp(5) <= congr_cl_rel13_ex5_m and binv_wayE_upd2_q; +congr_cl_rel13_wayE_byp(6) <= congr_cl_rel13_p1_cmp and reload_wayE_upd3_q; +congr_cl_rel13_wayE_byp(7) <= congr_cl_rel13_p0_cmp and binv_wayE_upd3_q; +-- WayE Bypass Valid +rel24_wayE_fxubyp_val_d <= congr_cl_rel13_wayE_byp(1) or congr_cl_rel13_wayE_byp(3) or + congr_cl_rel13_wayE_byp(5) or congr_cl_rel13_wayE_byp(7); +rel24_wayE_relbyp_val_d <= congr_cl_rel13_wayE_byp(2) or congr_cl_rel13_wayE_byp(4) or + congr_cl_rel13_wayE_byp(6); +rel24_wayE_byp_sel <= rel24_wayE_fxubyp_val_q & rel24_wayE_relbyp_val_q; +-- Late Stages Priority Selection +congr_cl_rel13_wayE_sel(2) <= congr_cl_rel13_wayE_byp(2); +congr_cl_rel13_wayE_sel(3) <= congr_cl_rel13_wayE_byp(3) and not congr_cl_rel13_wayE_byp(2); +congr_cl_rel13_wayE_sel(4) <= congr_cl_rel13_wayE_byp(4) and not or_reduce(congr_cl_rel13_wayE_byp(2 to 3)); +congr_cl_rel13_wayE_sel(5) <= congr_cl_rel13_wayE_byp(5) and not or_reduce(congr_cl_rel13_wayE_byp(2 to 4)); +congr_cl_rel13_wayE_sel(6) <= congr_cl_rel13_wayE_byp(6) and not or_reduce(congr_cl_rel13_wayE_byp(2 to 5)); +congr_cl_rel13_wayE_sel(7) <= congr_cl_rel13_wayE_byp(7) and not or_reduce(congr_cl_rel13_wayE_byp(2 to 6)); +-- ArrayRead/LATE Stage Priority Selection +rel_wayE_late_sel <= or_reduce(congr_cl_rel13_wayE_byp(2 to 7)); +rel_wayE_later_stg_pri <= gate(p1_arr_wayE_rd, not rel_wayE_late_sel) or + gate(reload_wayE, congr_cl_rel13_wayE_sel(2)) or + gate(flush_wayE_q, congr_cl_rel13_wayE_sel(3)) or + gate(reload_wayE_data_q, congr_cl_rel13_wayE_sel(4)) or + gate(flush_wayE_data_q, congr_cl_rel13_wayE_sel(5)) or + gate(reload_wayE_data2_q, congr_cl_rel13_wayE_sel(6)) or + gate(flush_wayE_data2_q, congr_cl_rel13_wayE_sel(7)); +-- EX3/RELU Stage Priority Selection +rel_wayE_early_sel <= congr_cl_rel13_wayE_byp(1); +rel_wayE_early_stg_pri <= flush_wayE_d; +-- Stage/ARRAY Priority Selection +rel_wayE_stg_val <= (others=>(rel_wayE_early_sel)); +rel_wayE_stg_val_b <= (others=>(not(rel_wayE_early_sel))); +rel_wayE_val <= not rel_wayE_val_b_q; +rel_wayE_val_stg_d <= rel_wayE_val; +-- WayF Bypass Calculation +congr_cl_rel13_wayF_byp(1) <= congr_cl_rel13_ex3_m and ex3_wayF_hit; +congr_cl_rel13_wayF_byp(2) <= congr_cl_rel13_relu_m and reload_wayF_upd_q; +congr_cl_rel13_wayF_byp(3) <= congr_cl_rel13_ex4_m and binv_wayF_upd_q; +congr_cl_rel13_wayF_byp(4) <= congr_cl_rel13_relu_s_m and reload_wayF_upd2_q; +congr_cl_rel13_wayF_byp(5) <= congr_cl_rel13_ex5_m and binv_wayF_upd2_q; +congr_cl_rel13_wayF_byp(6) <= congr_cl_rel13_p1_cmp and reload_wayF_upd3_q; +congr_cl_rel13_wayF_byp(7) <= congr_cl_rel13_p0_cmp and binv_wayF_upd3_q; +-- WayF Bypass Valid +rel24_wayF_fxubyp_val_d <= congr_cl_rel13_wayF_byp(1) or congr_cl_rel13_wayF_byp(3) or + congr_cl_rel13_wayF_byp(5) or congr_cl_rel13_wayF_byp(7); +rel24_wayF_relbyp_val_d <= congr_cl_rel13_wayF_byp(2) or congr_cl_rel13_wayF_byp(4) or + congr_cl_rel13_wayF_byp(6); +rel24_wayF_byp_sel <= rel24_wayF_fxubyp_val_q & rel24_wayF_relbyp_val_q; +-- Late Stages Priority Selection +congr_cl_rel13_wayF_sel(2) <= congr_cl_rel13_wayF_byp(2); +congr_cl_rel13_wayF_sel(3) <= congr_cl_rel13_wayF_byp(3) and not congr_cl_rel13_wayF_byp(2); +congr_cl_rel13_wayF_sel(4) <= congr_cl_rel13_wayF_byp(4) and not or_reduce(congr_cl_rel13_wayF_byp(2 to 3)); +congr_cl_rel13_wayF_sel(5) <= congr_cl_rel13_wayF_byp(5) and not or_reduce(congr_cl_rel13_wayF_byp(2 to 4)); +congr_cl_rel13_wayF_sel(6) <= congr_cl_rel13_wayF_byp(6) and not or_reduce(congr_cl_rel13_wayF_byp(2 to 5)); +congr_cl_rel13_wayF_sel(7) <= congr_cl_rel13_wayF_byp(7) and not or_reduce(congr_cl_rel13_wayF_byp(2 to 6)); +-- ArrayRead/LATE Stage Priority Selection +rel_wayF_late_sel <= or_reduce(congr_cl_rel13_wayF_byp(2 to 7)); +rel_wayF_later_stg_pri <= gate(p1_arr_wayF_rd, not rel_wayF_late_sel) or + gate(reload_wayF, congr_cl_rel13_wayF_sel(2)) or + gate(flush_wayF_q, congr_cl_rel13_wayF_sel(3)) or + gate(reload_wayF_data_q, congr_cl_rel13_wayF_sel(4)) or + gate(flush_wayF_data_q, congr_cl_rel13_wayF_sel(5)) or + gate(reload_wayF_data2_q, congr_cl_rel13_wayF_sel(6)) or + gate(flush_wayF_data2_q, congr_cl_rel13_wayF_sel(7)); +-- EX3/RELU Stage Priority Selection +rel_wayF_early_sel <= congr_cl_rel13_wayF_byp(1); +rel_wayF_early_stg_pri <= flush_wayF_d; +-- Stage/ARRAY Priority Selection +rel_wayF_stg_val <= (others=>(rel_wayF_early_sel)); +rel_wayF_stg_val_b <= (others=>(not(rel_wayF_early_sel))); +rel_wayF_val <= not rel_wayF_val_b_q; +rel_wayF_val_stg_d <= rel_wayF_val; +-- WayG Bypass Calculation +congr_cl_rel13_wayG_byp(1) <= congr_cl_rel13_ex3_m and ex3_wayG_hit; +congr_cl_rel13_wayG_byp(2) <= congr_cl_rel13_relu_m and reload_wayG_upd_q; +congr_cl_rel13_wayG_byp(3) <= congr_cl_rel13_ex4_m and binv_wayG_upd_q; +congr_cl_rel13_wayG_byp(4) <= congr_cl_rel13_relu_s_m and reload_wayG_upd2_q; +congr_cl_rel13_wayG_byp(5) <= congr_cl_rel13_ex5_m and binv_wayG_upd2_q; +congr_cl_rel13_wayG_byp(6) <= congr_cl_rel13_p1_cmp and reload_wayG_upd3_q; +congr_cl_rel13_wayG_byp(7) <= congr_cl_rel13_p0_cmp and binv_wayG_upd3_q; +-- WayG Bypass Valid +rel24_wayG_fxubyp_val_d <= congr_cl_rel13_wayG_byp(1) or congr_cl_rel13_wayG_byp(3) or + congr_cl_rel13_wayG_byp(5) or congr_cl_rel13_wayG_byp(7); +rel24_wayG_relbyp_val_d <= congr_cl_rel13_wayG_byp(2) or congr_cl_rel13_wayG_byp(4) or + congr_cl_rel13_wayG_byp(6); +rel24_wayG_byp_sel <= rel24_wayG_fxubyp_val_q & rel24_wayG_relbyp_val_q; +-- Late Stages Priority Selection +congr_cl_rel13_wayG_sel(2) <= congr_cl_rel13_wayG_byp(2); +congr_cl_rel13_wayG_sel(3) <= congr_cl_rel13_wayG_byp(3) and not congr_cl_rel13_wayG_byp(2); +congr_cl_rel13_wayG_sel(4) <= congr_cl_rel13_wayG_byp(4) and not or_reduce(congr_cl_rel13_wayG_byp(2 to 3)); +congr_cl_rel13_wayG_sel(5) <= congr_cl_rel13_wayG_byp(5) and not or_reduce(congr_cl_rel13_wayG_byp(2 to 4)); +congr_cl_rel13_wayG_sel(6) <= congr_cl_rel13_wayG_byp(6) and not or_reduce(congr_cl_rel13_wayG_byp(2 to 5)); +congr_cl_rel13_wayG_sel(7) <= congr_cl_rel13_wayG_byp(7) and not or_reduce(congr_cl_rel13_wayG_byp(2 to 6)); +-- ArrayRead/LATE Stage Priority Selection +rel_wayG_late_sel <= or_reduce(congr_cl_rel13_wayG_byp(2 to 7)); +rel_wayG_later_stg_pri <= gate(p1_arr_wayG_rd, not rel_wayG_late_sel) or + gate(reload_wayG, congr_cl_rel13_wayG_sel(2)) or + gate(flush_wayG_q, congr_cl_rel13_wayG_sel(3)) or + gate(reload_wayG_data_q, congr_cl_rel13_wayG_sel(4)) or + gate(flush_wayG_data_q, congr_cl_rel13_wayG_sel(5)) or + gate(reload_wayG_data2_q, congr_cl_rel13_wayG_sel(6)) or + gate(flush_wayG_data2_q, congr_cl_rel13_wayG_sel(7)); +-- EX3/RELU Stage Priority Selection +rel_wayG_early_sel <= congr_cl_rel13_wayG_byp(1); +rel_wayG_early_stg_pri <= flush_wayG_d; +-- Stage/ARRAY Priority Selection +rel_wayG_stg_val <= (others=>(rel_wayG_early_sel)); +rel_wayG_stg_val_b <= (others=>(not(rel_wayG_early_sel))); +rel_wayG_val <= not rel_wayG_val_b_q; +rel_wayG_val_stg_d <= rel_wayG_val; +-- WayH Bypass Calculation +congr_cl_rel13_wayH_byp(1) <= congr_cl_rel13_ex3_m and ex3_wayH_hit; +congr_cl_rel13_wayH_byp(2) <= congr_cl_rel13_relu_m and reload_wayH_upd_q; +congr_cl_rel13_wayH_byp(3) <= congr_cl_rel13_ex4_m and binv_wayH_upd_q; +congr_cl_rel13_wayH_byp(4) <= congr_cl_rel13_relu_s_m and reload_wayH_upd2_q; +congr_cl_rel13_wayH_byp(5) <= congr_cl_rel13_ex5_m and binv_wayH_upd2_q; +congr_cl_rel13_wayH_byp(6) <= congr_cl_rel13_p1_cmp and reload_wayH_upd3_q; +congr_cl_rel13_wayH_byp(7) <= congr_cl_rel13_p0_cmp and binv_wayH_upd3_q; +-- WayH Bypass Valid +rel24_wayH_fxubyp_val_d <= congr_cl_rel13_wayH_byp(1) or congr_cl_rel13_wayH_byp(3) or + congr_cl_rel13_wayH_byp(5) or congr_cl_rel13_wayH_byp(7); +rel24_wayH_relbyp_val_d <= congr_cl_rel13_wayH_byp(2) or congr_cl_rel13_wayH_byp(4) or + congr_cl_rel13_wayH_byp(6); +rel24_wayH_byp_sel <= rel24_wayH_fxubyp_val_q & rel24_wayH_relbyp_val_q; +-- Late Stages Priority Selection +congr_cl_rel13_wayH_sel(2) <= congr_cl_rel13_wayH_byp(2); +congr_cl_rel13_wayH_sel(3) <= congr_cl_rel13_wayH_byp(3) and not congr_cl_rel13_wayH_byp(2); +congr_cl_rel13_wayH_sel(4) <= congr_cl_rel13_wayH_byp(4) and not or_reduce(congr_cl_rel13_wayH_byp(2 to 3)); +congr_cl_rel13_wayH_sel(5) <= congr_cl_rel13_wayH_byp(5) and not or_reduce(congr_cl_rel13_wayH_byp(2 to 4)); +congr_cl_rel13_wayH_sel(6) <= congr_cl_rel13_wayH_byp(6) and not or_reduce(congr_cl_rel13_wayH_byp(2 to 5)); +congr_cl_rel13_wayH_sel(7) <= congr_cl_rel13_wayH_byp(7) and not or_reduce(congr_cl_rel13_wayH_byp(2 to 6)); +-- ArrayRead/LATE Stage Priority Selection +rel_wayH_late_sel <= or_reduce(congr_cl_rel13_wayH_byp(2 to 7)); +rel_wayH_later_stg_pri <= gate(p1_arr_wayH_rd, not rel_wayH_late_sel) or + gate(reload_wayH, congr_cl_rel13_wayH_sel(2)) or + gate(flush_wayH_q, congr_cl_rel13_wayH_sel(3)) or + gate(reload_wayH_data_q, congr_cl_rel13_wayH_sel(4)) or + gate(flush_wayH_data_q, congr_cl_rel13_wayH_sel(5)) or + gate(reload_wayH_data2_q, congr_cl_rel13_wayH_sel(6)) or + gate(flush_wayH_data2_q, congr_cl_rel13_wayH_sel(7)); +-- EX3/RELU Stage Priority Selection +rel_wayH_early_sel <= congr_cl_rel13_wayH_byp(1); +rel_wayH_early_stg_pri <= flush_wayH_d; +-- Stage/ARRAY Priority Selection +rel_wayH_stg_val <= (others=>(rel_wayH_early_sel)); +rel_wayH_stg_val_b <= (others=>(not(rel_wayH_early_sel))); +rel_wayH_val <= not rel_wayH_val_b_q; +rel_wayH_val_stg_d <= rel_wayH_val; +-- #################################################### +-- Reload Invalidate/Reload Validate Pipes +-- #################################################### +-- Invalidate Way +rel_par_wA_clr <= rel_wayA_clr or dcpar_err_way_inval_q(0); +-- Invalidate/Reload Logic on Port1 +reload_wayA_d(0) <= (not rel_par_wA_clr and rel_wayA_val(0)) or rel_wayA_set; +-- Lock Clear/Set Logic on Port1 +reload_wayA_d(1) <= (not rel_par_wA_clr and rel_wayA_val(1)) or (rel_lock_set_q and rel_wayA_set); +-- Lost Lock due to Parity Error +dcpar_err_lock_lost(0) <= rel_wayA_val(1) and dcpar_err_way_inval_q(0); +-- Watch Clear/Set Logic on Port1 +reload_wayA_d(2) <= ((not rel_par_wA_clr and rel_wayA_val(2))) or (rel_watch_set_q and rel_wayA_set and rel_thrd_id_q(0)); +reload_wayA_d(3) <= ((not rel_par_wA_clr and rel_wayA_val(3))) or (rel_watch_set_q and rel_wayA_set and rel_thrd_id_q(1)); +reload_wayA_d(4) <= ((not rel_par_wA_clr and rel_wayA_val(4))) or (rel_watch_set_q and rel_wayA_set and rel_thrd_id_q(2)); +reload_wayA_d(5) <= ((not rel_par_wA_clr and rel_wayA_val(5))) or (rel_watch_set_q and rel_wayA_set and rel_thrd_id_q(3)); +-- Updating due to Reload or Data cache Parity error +reload_wayA_upd_d <= rel_par_wA_clr or rel_wayA_set; +-- Updating due to Reload Clear only +reload_wayA_clr <= rel_par_wA_clr; +-- Invalidate Way +rel_par_wB_clr <= rel_wayB_clr or dcpar_err_way_inval_q(1); +-- Invalidate/Reload Logic on Port1 +reload_wayB_d(0) <= (not rel_par_wB_clr and rel_wayB_val(0)) or rel_wayB_set; +-- Lock Clear/Set Logic on Port1 +reload_wayB_d(1) <= (not rel_par_wB_clr and rel_wayB_val(1)) or (rel_lock_set_q and rel_wayB_set); +-- Lost Lock due to Parity Error +dcpar_err_lock_lost(1) <= rel_wayB_val(1) and dcpar_err_way_inval_q(1); +-- Watch Clear/Set Logic on Port1 +reload_wayB_d(2) <= ((not rel_par_wB_clr and rel_wayB_val(2))) or (rel_watch_set_q and rel_wayB_set and rel_thrd_id_q(0)); +reload_wayB_d(3) <= ((not rel_par_wB_clr and rel_wayB_val(3))) or (rel_watch_set_q and rel_wayB_set and rel_thrd_id_q(1)); +reload_wayB_d(4) <= ((not rel_par_wB_clr and rel_wayB_val(4))) or (rel_watch_set_q and rel_wayB_set and rel_thrd_id_q(2)); +reload_wayB_d(5) <= ((not rel_par_wB_clr and rel_wayB_val(5))) or (rel_watch_set_q and rel_wayB_set and rel_thrd_id_q(3)); +-- Updating due to Reload or Data cache Parity error +reload_wayB_upd_d <= rel_par_wB_clr or rel_wayB_set; +-- Updating due to Reload Clear only +reload_wayB_clr <= rel_par_wB_clr; +-- Invalidate Way +rel_par_wC_clr <= rel_wayC_clr or dcpar_err_way_inval_q(2); +-- Invalidate/Reload Logic on Port1 +reload_wayC_d(0) <= (not rel_par_wC_clr and rel_wayC_val(0)) or rel_wayC_set; +-- Lock Clear/Set Logic on Port1 +reload_wayC_d(1) <= (not rel_par_wC_clr and rel_wayC_val(1)) or (rel_lock_set_q and rel_wayC_set); +-- Lost Lock due to Parity Error +dcpar_err_lock_lost(2) <= rel_wayC_val(1) and dcpar_err_way_inval_q(2); +-- Watch Clear/Set Logic on Port1 +reload_wayC_d(2) <= ((not rel_par_wC_clr and rel_wayC_val(2))) or (rel_watch_set_q and rel_wayC_set and rel_thrd_id_q(0)); +reload_wayC_d(3) <= ((not rel_par_wC_clr and rel_wayC_val(3))) or (rel_watch_set_q and rel_wayC_set and rel_thrd_id_q(1)); +reload_wayC_d(4) <= ((not rel_par_wC_clr and rel_wayC_val(4))) or (rel_watch_set_q and rel_wayC_set and rel_thrd_id_q(2)); +reload_wayC_d(5) <= ((not rel_par_wC_clr and rel_wayC_val(5))) or (rel_watch_set_q and rel_wayC_set and rel_thrd_id_q(3)); +-- Updating due to Reload or Data cache Parity error +reload_wayC_upd_d <= rel_par_wC_clr or rel_wayC_set; +-- Updating due to Reload Clear only +reload_wayC_clr <= rel_par_wC_clr; +-- Invalidate Way +rel_par_wD_clr <= rel_wayD_clr or dcpar_err_way_inval_q(3); +-- Invalidate/Reload Logic on Port1 +reload_wayD_d(0) <= (not rel_par_wD_clr and rel_wayD_val(0)) or rel_wayD_set; +-- Lock Clear/Set Logic on Port1 +reload_wayD_d(1) <= (not rel_par_wD_clr and rel_wayD_val(1)) or (rel_lock_set_q and rel_wayD_set); +-- Lost Lock due to Parity Error +dcpar_err_lock_lost(3) <= rel_wayD_val(1) and dcpar_err_way_inval_q(3); +-- Watch Clear/Set Logic on Port1 +reload_wayD_d(2) <= ((not rel_par_wD_clr and rel_wayD_val(2))) or (rel_watch_set_q and rel_wayD_set and rel_thrd_id_q(0)); +reload_wayD_d(3) <= ((not rel_par_wD_clr and rel_wayD_val(3))) or (rel_watch_set_q and rel_wayD_set and rel_thrd_id_q(1)); +reload_wayD_d(4) <= ((not rel_par_wD_clr and rel_wayD_val(4))) or (rel_watch_set_q and rel_wayD_set and rel_thrd_id_q(2)); +reload_wayD_d(5) <= ((not rel_par_wD_clr and rel_wayD_val(5))) or (rel_watch_set_q and rel_wayD_set and rel_thrd_id_q(3)); +-- Updating due to Reload or Data cache Parity error +reload_wayD_upd_d <= rel_par_wD_clr or rel_wayD_set; +-- Updating due to Reload Clear only +reload_wayD_clr <= rel_par_wD_clr; +-- Invalidate Way +rel_par_wE_clr <= rel_wayE_clr or dcpar_err_way_inval_q(4); +-- Invalidate/Reload Logic on Port1 +reload_wayE_d(0) <= (not rel_par_wE_clr and rel_wayE_val(0)) or rel_wayE_set; +-- Lock Clear/Set Logic on Port1 +reload_wayE_d(1) <= (not rel_par_wE_clr and rel_wayE_val(1)) or (rel_lock_set_q and rel_wayE_set); +-- Lost Lock due to Parity Error +dcpar_err_lock_lost(4) <= rel_wayE_val(1) and dcpar_err_way_inval_q(4); +-- Watch Clear/Set Logic on Port1 +reload_wayE_d(2) <= ((not rel_par_wE_clr and rel_wayE_val(2))) or (rel_watch_set_q and rel_wayE_set and rel_thrd_id_q(0)); +reload_wayE_d(3) <= ((not rel_par_wE_clr and rel_wayE_val(3))) or (rel_watch_set_q and rel_wayE_set and rel_thrd_id_q(1)); +reload_wayE_d(4) <= ((not rel_par_wE_clr and rel_wayE_val(4))) or (rel_watch_set_q and rel_wayE_set and rel_thrd_id_q(2)); +reload_wayE_d(5) <= ((not rel_par_wE_clr and rel_wayE_val(5))) or (rel_watch_set_q and rel_wayE_set and rel_thrd_id_q(3)); +-- Updating due to Reload or Data cache Parity error +reload_wayE_upd_d <= rel_par_wE_clr or rel_wayE_set; +-- Updating due to Reload Clear only +reload_wayE_clr <= rel_par_wE_clr; +-- Invalidate Way +rel_par_wF_clr <= rel_wayF_clr or dcpar_err_way_inval_q(5); +-- Invalidate/Reload Logic on Port1 +reload_wayF_d(0) <= (not rel_par_wF_clr and rel_wayF_val(0)) or rel_wayF_set; +-- Lock Clear/Set Logic on Port1 +reload_wayF_d(1) <= (not rel_par_wF_clr and rel_wayF_val(1)) or (rel_lock_set_q and rel_wayF_set); +-- Lost Lock due to Parity Error +dcpar_err_lock_lost(5) <= rel_wayF_val(1) and dcpar_err_way_inval_q(5); +-- Watch Clear/Set Logic on Port1 +reload_wayF_d(2) <= ((not rel_par_wF_clr and rel_wayF_val(2))) or (rel_watch_set_q and rel_wayF_set and rel_thrd_id_q(0)); +reload_wayF_d(3) <= ((not rel_par_wF_clr and rel_wayF_val(3))) or (rel_watch_set_q and rel_wayF_set and rel_thrd_id_q(1)); +reload_wayF_d(4) <= ((not rel_par_wF_clr and rel_wayF_val(4))) or (rel_watch_set_q and rel_wayF_set and rel_thrd_id_q(2)); +reload_wayF_d(5) <= ((not rel_par_wF_clr and rel_wayF_val(5))) or (rel_watch_set_q and rel_wayF_set and rel_thrd_id_q(3)); +-- Updating due to Reload or Data cache Parity error +reload_wayF_upd_d <= rel_par_wF_clr or rel_wayF_set; +-- Updating due to Reload Clear only +reload_wayF_clr <= rel_par_wF_clr; +-- Invalidate Way +rel_par_wG_clr <= rel_wayG_clr or dcpar_err_way_inval_q(6); +-- Invalidate/Reload Logic on Port1 +reload_wayG_d(0) <= (not rel_par_wG_clr and rel_wayG_val(0)) or rel_wayG_set; +-- Lock Clear/Set Logic on Port1 +reload_wayG_d(1) <= (not rel_par_wG_clr and rel_wayG_val(1)) or (rel_lock_set_q and rel_wayG_set); +-- Lost Lock due to Parity Error +dcpar_err_lock_lost(6) <= rel_wayG_val(1) and dcpar_err_way_inval_q(6); +-- Watch Clear/Set Logic on Port1 +reload_wayG_d(2) <= ((not rel_par_wG_clr and rel_wayG_val(2))) or (rel_watch_set_q and rel_wayG_set and rel_thrd_id_q(0)); +reload_wayG_d(3) <= ((not rel_par_wG_clr and rel_wayG_val(3))) or (rel_watch_set_q and rel_wayG_set and rel_thrd_id_q(1)); +reload_wayG_d(4) <= ((not rel_par_wG_clr and rel_wayG_val(4))) or (rel_watch_set_q and rel_wayG_set and rel_thrd_id_q(2)); +reload_wayG_d(5) <= ((not rel_par_wG_clr and rel_wayG_val(5))) or (rel_watch_set_q and rel_wayG_set and rel_thrd_id_q(3)); +-- Updating due to Reload or Data cache Parity error +reload_wayG_upd_d <= rel_par_wG_clr or rel_wayG_set; +-- Updating due to Reload Clear only +reload_wayG_clr <= rel_par_wG_clr; +-- Invalidate Way +rel_par_wH_clr <= rel_wayH_clr or dcpar_err_way_inval_q(7); +-- Invalidate/Reload Logic on Port1 +reload_wayH_d(0) <= (not rel_par_wH_clr and rel_wayH_val(0)) or rel_wayH_set; +-- Lock Clear/Set Logic on Port1 +reload_wayH_d(1) <= (not rel_par_wH_clr and rel_wayH_val(1)) or (rel_lock_set_q and rel_wayH_set); +-- Lost Lock due to Parity Error +dcpar_err_lock_lost(7) <= rel_wayH_val(1) and dcpar_err_way_inval_q(7); +-- Watch Clear/Set Logic on Port1 +reload_wayH_d(2) <= ((not rel_par_wH_clr and rel_wayH_val(2))) or (rel_watch_set_q and rel_wayH_set and rel_thrd_id_q(0)); +reload_wayH_d(3) <= ((not rel_par_wH_clr and rel_wayH_val(3))) or (rel_watch_set_q and rel_wayH_set and rel_thrd_id_q(1)); +reload_wayH_d(4) <= ((not rel_par_wH_clr and rel_wayH_val(4))) or (rel_watch_set_q and rel_wayH_set and rel_thrd_id_q(2)); +reload_wayH_d(5) <= ((not rel_par_wH_clr and rel_wayH_val(5))) or (rel_watch_set_q and rel_wayH_set and rel_thrd_id_q(3)); +-- Updating due to Reload or Data cache Parity error +reload_wayH_upd_d <= rel_par_wH_clr or rel_wayH_set; +-- Updating due to Reload Clear only +reload_wayH_clr <= rel_par_wH_clr; +reload_way_clr_d <= reload_wayA_clr & reload_wayB_clr & reload_wayC_clr & reload_wayD_clr & + reload_wayE_clr & reload_wayF_clr & reload_wayG_clr & reload_wayH_clr; +-- #################################################### +-- Determine if Watch was lost due to a reload or +-- due to a Back-Invalidate of loadmissQ entry +-- #################################################### +-- Watch Lost due to L1DUMP of reload +rel4_l1dump_watch <= rel4_l1dump_val_q and rel_watch_set_q and not rel4_ecc_err; +lost_watch_l1dump <= gate(rel_thrd_id_q, rel4_l1dump_watch); +-- Watch Lost due to Overlock +lost_watch_evict_ovl_d <= (gate(rel_thrd_id_q, (rel_watch_set_q and rel_val_stg4 and not + (rel_wayA_set or rel_wayB_set or rel_wayC_set or rel_wayD_set or + rel_wayE_set or rel_wayF_set or rel_wayG_set or rel_wayH_set)))) or + lost_watch_l1dump; +-- Watch Lost due to Eviction +rel_lost_watch_wayA_evict <= gate(rel_wayA_val_stg_q(2 to 5), reload_way_clr_q(0)); +rel_lost_watch_wayB_evict <= gate(rel_wayB_val_stg_q(2 to 5), reload_way_clr_q(1)); +rel_lost_watch_wayC_evict <= gate(rel_wayC_val_stg_q(2 to 5), reload_way_clr_q(2)); +rel_lost_watch_wayD_evict <= gate(rel_wayD_val_stg_q(2 to 5), reload_way_clr_q(3)); +rel_lost_watch_wayE_evict <= gate(rel_wayE_val_stg_q(2 to 5), reload_way_clr_q(4)); +rel_lost_watch_wayF_evict <= gate(rel_wayF_val_stg_q(2 to 5), reload_way_clr_q(5)); +rel_lost_watch_wayG_evict <= gate(rel_wayG_val_stg_q(2 to 5), reload_way_clr_q(6)); +rel_lost_watch_wayH_evict <= gate(rel_wayH_val_stg_q(2 to 5), reload_way_clr_q(7)); +-- Watch Lost due to back-invalidate +rel_lost_watch_binv_d <= rel_watch_lost; +-- None Bypass Watch Lost indicator +rel_lost_watch_evict_np <= rel_lost_watch_wayA_evict or rel_lost_watch_wayB_evict or rel_lost_watch_wayC_evict or rel_lost_watch_wayD_evict or + rel_lost_watch_wayE_evict or rel_lost_watch_wayF_evict or rel_lost_watch_wayG_evict or rel_lost_watch_wayH_evict; +-- Data Cache Parity error lost Lock Bit +dcperr_lock_lost_d <= or_reduce(dcpar_err_lock_lost); +-- Staging out congruence class compares +rel24_congr_cl_ex4_cmp_d <= congr_cl_rel13_ex3_cmp_q; +rel24_congr_cl_ex5_cmp_d <= congr_cl_rel13_ex4_cmp_q; +rel24_congr_cl_ex6_cmp_d <= congr_cl_rel13_ex5_cmp_q; +relu_congr_cl_ex5_cmp_d <= rel24_congr_cl_ex4_cmp_q; +relu_congr_cl_ex6_cmp_d <= rel24_congr_cl_ex5_cmp_q; +relu_congr_cl_ex7_cmp_d <= rel24_congr_cl_ex6_cmp_q; +-- Data of ways updated in other stages +relu_dir_data <= gate(reload_wayA_q(2 to 5), reload_way_clr_q(0)) or gate(reload_wayB_q(2 to 5), reload_way_clr_q(1)) or + gate(reload_wayC_q(2 to 5), reload_way_clr_q(2)) or gate(reload_wayD_q(2 to 5), reload_way_clr_q(3)) or + gate(reload_wayE_q(2 to 5), reload_way_clr_q(4)) or gate(reload_wayF_q(2 to 5), reload_way_clr_q(5)) or + gate(reload_wayG_q(2 to 5), reload_way_clr_q(6)) or gate(reload_wayH_q(2 to 5), reload_way_clr_q(7)); +-- LDAWX hit way in pipe collided with reload clear of same way in rel1_val stage +rel_ex5_watchSet_coll <= rel_val_clr_q and relu_congr_cl_ex5_cmp_q and or_reduce(reload_way_clr_q and binv5_ex5_way_upd) and p0_wren_d; +rel_ex6_watchSet_coll <= rel_val_clr_q and relu_congr_cl_ex6_cmp_q and or_reduce(reload_way_clr_q and binv6_ex6_way_upd) and p0_wren_q; +rel_ex7_watchSet_coll <= rel_val_clr_q and relu_congr_cl_ex7_cmp_q and or_reduce(reload_way_clr_q and binv7_ex7_way_upd_q) and p0_wren_stg_q; +rel_coll_val <= rel_ex5_watchSet_coll or rel_ex6_watchSet_coll or rel_ex7_watchSet_coll; +-- Priority Calculation +rel_pri_byp_sel(0) <= rel_ex5_watchSet_coll; +rel_pri_byp_sel(1) <= rel_ex6_watchSet_coll and not rel_ex5_watchSet_coll; +rel_pri_byp_sel(2) <= rel_ex7_watchSet_coll and not (rel_ex6_watchSet_coll or rel_ex5_watchSet_coll); +rel_byp_dir_data <= gate(binv5_ex5_dir_data_q(2 to 5), rel_pri_byp_sel(0)) or + gate(binv6_ex6_dir_data_q(2 to 5), rel_pri_byp_sel(1)) or + gate(binv7_ex7_dir_data_q(2 to 5), rel_pri_byp_sel(2)); +-- Reload invalidated a watched line +rel_watchSet_coll_tid <= (rel_byp_dir_data and not relu_dir_data) or gate(rel_lost_watch_evict_np, (rel_val_clr_q and not rel_coll_val)); +-- Watch Lost due to eviction or overlock or pipe collision with ldawx +rel_lost_watch_evict <= lost_watch_evict_ovl_q or rel_watchSet_coll_tid; +-- Watch Lost due to back-invalidate or overlock or eviction or pipe collision with ldawx +rel_lost_watch_upd_d <= rel_lost_watch_binv_q or rel_lost_watch_evict; +-- #################################################### +-- Performance Events +-- #################################################### +-- Performance Event, Back-Invalidate Hit +perf_binv_hit <= back_inval_stg4_q and or_reduce(ex4_way_hit_q); +-- Performance Event, Watch Checks Completed +ex5_watch_chk_cplt <= ex5_watch_chk_q and not ex5_stg_flush; +-- Performance Event, Watch Checked Successfull +ex5_watch_chk_succ <= ex5_watch_chk_q and not (ex5_cr_watch_q or ex5_stg_flush); +-- Performance Event, LDAWX. instruction executed and CR=1 (indicates a duplicate watch set) +ex5_watch_dup_set <= ex5_watch_set_q and ex5_cr_watch_q and not ex5_stg_flush; +-- Performance Event, Watches lost due to other thread +lost_watch_inter_thrd_d <= gate((ex5_watchlost_set_q and not (ex5_thrd_id_q or ex5_watch_clr_all_q)), ex5_xuop_val); +-- Performance Event, Watches lost due to Eviction or Overlock +lost_watch_evict_val_d <= lost_watch_evict_ovl_q or rel_watchSet_coll_tid; +-- Performance Event, Watch Lost due to back-invalidate +lost_watch_binv <= binv5_inval_watch_val_q or rel_lost_watch_binv_q; +-- Performance Event, Latching up Events +perf_lsu_evnts_d <= back_inval_stg4_q & perf_binv_hit & ex5_watch_chk_cplt & ex5_watch_chk_succ & ex5_watch_dup_set; +-- #################################################### +-- Parity Error Recovery Logic +-- #################################################### +-- Parity Error detected in EX6, need to invalidate any +-- Load Hits in EX6, EX5, and EX4 since these requests +-- Will be satisfied by the L2. Parity Error Recovery +-- Sequencer waits for the first parity error to reach EX9 +-- in the Parity Error Recovery Queue before it starts +-- The sequencer will look for a hole in the reload pipe +-- and use it to invalidate the way with the parity error +-- of the load hit including valids,lock,and watch bits. +-- The Queue consists of a Parity Error Indicator, +-- Load Valid Indicator, Congruence Class, and Way Hit +dcpar_err_push <= not ex9_ld_par_err_q; +dcpar_err_rec_cmpl <= (dcpar_err_cntr_q = "10") and dcpar_err_nxt_rec; +dcpar_err_nxt_rec <= ex9_ld_par_err_q and not rel_in_progress; +dcpar_err_push_queue <= dcpar_err_push or dcpar_err_nxt_rec; +dcpar_err_ind_sel <= dcpar_err_push & dcpar_err_rec_cmpl; +dcpar_err_ind_sel_d <= dcpar_err_ind_sel; +dcpar_err_push_queue_d <= dcpar_err_push_queue; +-- Parity Error Recovery Queue +-- #################################################### +-- Parity Error Indicator +with dcpar_err_ind_sel select + ex7_ld_par_err_d <= ex6_ld_par_err when "10", + ex7_ld_par_err_q when "00", + '0' when others; +with dcpar_err_ind_sel select + ex8_ld_par_err_d <= ex7_ld_par_err_q when "10", + ex8_ld_par_err_q when "00", + '0' when others; +with dcpar_err_ind_sel select + ex9_ld_par_err_d <= ex8_ld_par_err_q when "10", + ex9_ld_par_err_q when "00", + '0' when others; +-- Load Hit Valid Indicator +with dcpar_err_push_queue select + ex7_ld_valid_d <= ex6_ld_valid_q when '1', + ex7_ld_valid_q when others; +with dcpar_err_push_queue select + ex8_ld_valid_d <= ex7_ld_valid_q when '1', + ex8_ld_valid_q when others; +with dcpar_err_push_queue select + ex9_ld_valid_d <= ex8_ld_valid_q when '1', + ex9_ld_valid_q when others; +-- Congruence Class +with dcpar_err_push_queue select + ex7_congr_cl_d <= ex6_congr_cl_q when '1', + ex7_congr_cl_q when others; +with dcpar_err_push_queue select + ex8_congr_cl_d <= ex7_congr_cl_q when '1', + ex8_congr_cl_q when others; +with dcpar_err_push_queue select + ex9_congr_cl_d <= ex8_congr_cl_q when '1', + ex9_congr_cl_q when others; +-- Way Hit +with dcpar_err_push_queue select + ex7_way_hit_d <= ex6_way_hit_q when '1', + ex7_way_hit_q when others; +with dcpar_err_push_queue select + ex8_way_hit_d <= ex7_way_hit_q when '1', + ex8_way_hit_q when others; +with dcpar_err_push_queue select + ex9_way_hit_d <= ex8_way_hit_q when '1', + ex9_way_hit_q when others; +-- Parity Error Recovery Counter +dcpar_err_incr_val <= dcpar_err_nxt_rec and not (dcpar_err_cntr_q = "10"); +dcpar_err_cntr_sel <= dcpar_err_push & dcpar_err_incr_val; +dcpar_err_nxt_cntr <= std_ulogic_vector(unsigned(dcpar_err_cntr_q) + "01"); +with dcpar_err_cntr_sel select + dcpar_err_cntr_d <= dcpar_err_nxt_cntr when "01", + dcpar_err_cntr_q when "00", + "00" when others; +-- Generate a Pulse for Parity Error Completion +dcpar_err_stg1_d <= dcpar_err_nxt_rec; +dcpar_err_stg2_d <= dcpar_err_stg1_q; +dcpar_err_congr_cl <= ex9_congr_cl_q; +dcpar_err_way_d <= gate(ex9_way_hit_q, (ex9_ld_valid_q and dcpar_err_nxt_rec)); +dcpar_err_way_inval_d <= dcpar_err_way_q; +dcpar_err_flush <= ex9_ld_par_err_q; +dcpar_err_stg1_act_d <= ex9_ld_par_err_q; +dcpar_err_stg2_act_d <= dcpar_err_stg1_act_q; +dcpar_err_rec_inprog <= ex7_ld_par_err_q or ex8_ld_par_err_q or ex9_ld_par_err_q; +-- #################################################### +-- Directory Valid Bits Write Enable Generation +-- #################################################### +-- Valids are updated for the following operations +-- 1) Reload -> updated the following cycle of the first beat, +-- need to invalidate the way that will be overwritten +-- 2) Reload -> updated on the last data beat when no ECC error was detected, +-- the Way will be validated that was replaced +-- 3) Back-Invalidate -> updated the following cycle +-- 4) DCBF -> Updated in EX4 +-- 5) DCBI -> Updated in EX4 +-- 6) DCBZ -> Updated in EX4 +-- 7) LWARX Hit Invalidate -> Updated in EX4 +-- 8) STWCX Hit Invalidate -> Updated in EX4 +-- Lock Bits are updated for the following operations +-- 1) Reload -> updated the following cycle of the first beat, +-- need to clear the lock bit for the way that will be overwritten +-- 2) Reload -> updated on the last data beat when no ECC error was detected, +-- the Lock bit will be set that was replaced if originally a lock type op +-- 3) Back-Invalidate -> will clear lock bit the following cycle +-- 4) DCBF -> will clear lock bit in EX4 +-- 5) DCBI -> will clear lock bit in EX4 +-- 6) DCBZ -> will clear lock bit in EX4 +-- 7) LWARX Hit Invalidate -> will clear lock bit in EX4 +-- 8) STWCX Hit Invalidate -> will clear lock bit in EX4 +-- 9) DCBLC -> will clear lock bit in EX4 +--10) DCBTLS/DCBTSTLS -> will set lock bit in EX4 if hit +-- Port0 Updates +-- 1) XU Invalidate Op +-- 2) BACK-INV Update +-- 3) XU clear Lock Op +-- 4) XU set Lock Op +p0_wren_d <= back_inval_stg5_q or ex5_xuop_val or ex5_dir_err_val_q; +p0_wren_cpy_d <= back_inval_stg5_q or ex5_xuop_val or ex5_dir_err_val_q; +p0_wren_stg_d <= p0_wren_q; +-- Port1 Updates +-- 1) RELOAD_CLR +-- 2) RELOAD_SEt +-- 3) DC Array Parity Error with Loadhit followed by storehit update - need to invalidate storehit cline +p1_wren_d <= rel_port_wren_q; +p1_wren_cpy_d <= rel_port_wren_q; +p1_upd_val <= rel_port_upd_q; +-- Need to set reload way valid bit when clearing the valid bit of older load +-- in case second reload of interleaved reloads to same congruence class +-- Dont want second reload to overwrite first reload that cleared the valid bit +-- Second reload will choose the same way if not set by first +reload_wayA(0) <= (reload_wayA_upd_q); +reload_wayA(1) <= reload_wayA_q(1); +reload_wayA(2 TO 5) <= reload_wayA_q(2 to 5); +-- Staging out Reload Pipe Updates +reload_wayA_upd2_d <= reload_wayA_upd_q; +reload_wayA_data_d <= reload_wayA_q; +reload_wayA_upd3_d <= reload_wayA_upd2_q; +reload_wayA_data2_d <= reload_wayA_data_q; +-- Staging out Back-Invalidate Pipe Updates +binv_wayA_upd1 <= (binv_wayA_upd_q and ((not ex4_dir_err_val_q) or back_inval_stg4_q)) or ex4_err_det_way_q(0) or ex4_dir_multihit_val; +binv_wayA_upd2_d <= binv_wayA_upd1; +flush_wayA_data1 <= gate(flush_wayA_q, not (ex4_err_det_way_q(0) or ex4_dir_multihit_val)); +flush_wayA_data_d <= flush_wayA_data1; +binv_wayA_upd3_d <= binv_wayA_upd2_q; +flush_wayA_data2_d <= flush_wayA_data_q; +reload_wayB(0) <= (reload_wayB_upd_q); +reload_wayB(1) <= reload_wayB_q(1); +reload_wayB(2 TO 5) <= reload_wayB_q(2 to 5); +-- Staging out Reload Pipe Updates +reload_wayB_upd2_d <= reload_wayB_upd_q; +reload_wayB_data_d <= reload_wayB_q; +reload_wayB_upd3_d <= reload_wayB_upd2_q; +reload_wayB_data2_d <= reload_wayB_data_q; +-- Staging out Back-Invalidate Pipe Updates +binv_wayB_upd1 <= (binv_wayB_upd_q and ((not ex4_dir_err_val_q) or back_inval_stg4_q)) or ex4_err_det_way_q(1) or ex4_dir_multihit_val; +binv_wayB_upd2_d <= binv_wayB_upd1; +flush_wayB_data1 <= gate(flush_wayB_q, not (ex4_err_det_way_q(1) or ex4_dir_multihit_val)); +flush_wayB_data_d <= flush_wayB_data1; +binv_wayB_upd3_d <= binv_wayB_upd2_q; +flush_wayB_data2_d <= flush_wayB_data_q; +reload_wayC(0) <= (reload_wayC_upd_q); +reload_wayC(1) <= reload_wayC_q(1); +reload_wayC(2 TO 5) <= reload_wayC_q(2 to 5); +-- Staging out Reload Pipe Updates +reload_wayC_upd2_d <= reload_wayC_upd_q; +reload_wayC_data_d <= reload_wayC_q; +reload_wayC_upd3_d <= reload_wayC_upd2_q; +reload_wayC_data2_d <= reload_wayC_data_q; +-- Staging out Back-Invalidate Pipe Updates +binv_wayC_upd1 <= (binv_wayC_upd_q and ((not ex4_dir_err_val_q) or back_inval_stg4_q)) or ex4_err_det_way_q(2) or ex4_dir_multihit_val; +binv_wayC_upd2_d <= binv_wayC_upd1; +flush_wayC_data1 <= gate(flush_wayC_q, not (ex4_err_det_way_q(2) or ex4_dir_multihit_val)); +flush_wayC_data_d <= flush_wayC_data1; +binv_wayC_upd3_d <= binv_wayC_upd2_q; +flush_wayC_data2_d <= flush_wayC_data_q; +reload_wayD(0) <= (reload_wayD_upd_q); +reload_wayD(1) <= reload_wayD_q(1); +reload_wayD(2 TO 5) <= reload_wayD_q(2 to 5); +-- Staging out Reload Pipe Updates +reload_wayD_upd2_d <= reload_wayD_upd_q; +reload_wayD_data_d <= reload_wayD_q; +reload_wayD_upd3_d <= reload_wayD_upd2_q; +reload_wayD_data2_d <= reload_wayD_data_q; +-- Staging out Back-Invalidate Pipe Updates +binv_wayD_upd1 <= (binv_wayD_upd_q and ((not ex4_dir_err_val_q) or back_inval_stg4_q)) or ex4_err_det_way_q(3) or ex4_dir_multihit_val; +binv_wayD_upd2_d <= binv_wayD_upd1; +flush_wayD_data1 <= gate(flush_wayD_q, not (ex4_err_det_way_q(3) or ex4_dir_multihit_val)); +flush_wayD_data_d <= flush_wayD_data1; +binv_wayD_upd3_d <= binv_wayD_upd2_q; +flush_wayD_data2_d <= flush_wayD_data_q; +reload_wayE(0) <= (reload_wayE_upd_q); +reload_wayE(1) <= reload_wayE_q(1); +reload_wayE(2 TO 5) <= reload_wayE_q(2 to 5); +-- Staging out Reload Pipe Updates +reload_wayE_upd2_d <= reload_wayE_upd_q; +reload_wayE_data_d <= reload_wayE_q; +reload_wayE_upd3_d <= reload_wayE_upd2_q; +reload_wayE_data2_d <= reload_wayE_data_q; +-- Staging out Back-Invalidate Pipe Updates +binv_wayE_upd1 <= (binv_wayE_upd_q and ((not ex4_dir_err_val_q) or back_inval_stg4_q)) or ex4_err_det_way_q(4) or ex4_dir_multihit_val; +binv_wayE_upd2_d <= binv_wayE_upd1; +flush_wayE_data1 <= gate(flush_wayE_q, not (ex4_err_det_way_q(4) or ex4_dir_multihit_val)); +flush_wayE_data_d <= flush_wayE_data1; +binv_wayE_upd3_d <= binv_wayE_upd2_q; +flush_wayE_data2_d <= flush_wayE_data_q; +reload_wayF(0) <= (reload_wayF_upd_q); +reload_wayF(1) <= reload_wayF_q(1); +reload_wayF(2 TO 5) <= reload_wayF_q(2 to 5); +-- Staging out Reload Pipe Updates +reload_wayF_upd2_d <= reload_wayF_upd_q; +reload_wayF_data_d <= reload_wayF_q; +reload_wayF_upd3_d <= reload_wayF_upd2_q; +reload_wayF_data2_d <= reload_wayF_data_q; +-- Staging out Back-Invalidate Pipe Updates +binv_wayF_upd1 <= (binv_wayF_upd_q and ((not ex4_dir_err_val_q) or back_inval_stg4_q)) or ex4_err_det_way_q(5) or ex4_dir_multihit_val; +binv_wayF_upd2_d <= binv_wayF_upd1; +flush_wayF_data1 <= gate(flush_wayF_q, not (ex4_err_det_way_q(5) or ex4_dir_multihit_val)); +flush_wayF_data_d <= flush_wayF_data1; +binv_wayF_upd3_d <= binv_wayF_upd2_q; +flush_wayF_data2_d <= flush_wayF_data_q; +reload_wayG(0) <= (reload_wayG_upd_q); +reload_wayG(1) <= reload_wayG_q(1); +reload_wayG(2 TO 5) <= reload_wayG_q(2 to 5); +-- Staging out Reload Pipe Updates +reload_wayG_upd2_d <= reload_wayG_upd_q; +reload_wayG_data_d <= reload_wayG_q; +reload_wayG_upd3_d <= reload_wayG_upd2_q; +reload_wayG_data2_d <= reload_wayG_data_q; +-- Staging out Back-Invalidate Pipe Updates +binv_wayG_upd1 <= (binv_wayG_upd_q and ((not ex4_dir_err_val_q) or back_inval_stg4_q)) or ex4_err_det_way_q(6) or ex4_dir_multihit_val; +binv_wayG_upd2_d <= binv_wayG_upd1; +flush_wayG_data1 <= gate(flush_wayG_q, not (ex4_err_det_way_q(6) or ex4_dir_multihit_val)); +flush_wayG_data_d <= flush_wayG_data1; +binv_wayG_upd3_d <= binv_wayG_upd2_q; +flush_wayG_data2_d <= flush_wayG_data_q; +reload_wayH(0) <= (reload_wayH_upd_q); +reload_wayH(1) <= reload_wayH_q(1); +reload_wayH(2 TO 5) <= reload_wayH_q(2 to 5); +-- Staging out Reload Pipe Updates +reload_wayH_upd2_d <= reload_wayH_upd_q; +reload_wayH_data_d <= reload_wayH_q; +reload_wayH_upd3_d <= reload_wayH_upd2_q; +reload_wayH_data2_d <= reload_wayH_data_q; +-- Staging out Back-Invalidate Pipe Updates +binv_wayH_upd1 <= (binv_wayH_upd_q and ((not ex4_dir_err_val_q) or back_inval_stg4_q)) or ex4_err_det_way_q(7) or ex4_dir_multihit_val; +binv_wayH_upd2_d <= binv_wayH_upd1; +flush_wayH_data1 <= gate(flush_wayH_q, not (ex4_err_det_way_q(7) or ex4_dir_multihit_val)); +flush_wayH_data_d <= flush_wayH_data1; +binv_wayH_upd3_d <= binv_wayH_upd2_q; +flush_wayH_data2_d <= flush_wayH_data_q; +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Table for selecting Ports data for +-- updating to the same way and +-- same congruence class +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- P0 P1 | PortSel +-------------------------------------------- +-- binv2 relclr | P1 +-- binv2 relset | P1 +-- binv2 binv2 | P1 <- Impossible +-- flush relclr | P1 +-- flush relset | P1 +-- flush binv2 | P1 <- FlushOp is flushed +-- lckset relclr | P1 +-- lckset relset | P1 +-- lckset binv2 | P1 <- LockSetOp is flushed +-- lckclr relclr | P1 +-- lckclr relset | P1 +-- lckclr binv2 | P1 <- LockClrOp is flushed +-- Act Pin to all Directory Latches +congr_cl_all_act_d <= ex5_watch_clr_all_val_q or dci_compl_q or lock_flash_clear_q; +-- Congruence Class Match +p0_congr_cl0_m <= (ex5_congr_cl_q = tconv(0,6)); +p1_congr_cl0_m <= (relu_s_congr_cl_q = tconv(0,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl0_act_d <= p0_congr_cl0_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl0_act_d <= p1_congr_cl0_m and rel_port_wren_q; +congr_cl0_act <= p0_congr_cl0_act_q or p1_congr_cl0_act_q or congr_cl_all_act_q; +p0_way_data_upd0_wayA <= p0_congr_cl0_act_q and binv_wayA_upd3_q; +p1_way_data_upd0_wayA <= p1_congr_cl0_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu0_wayA_upd(0) <= p1_way_data_upd0_wayA and p1_wren_q; +rel_bixu0_wayA_upd(1) <= p0_way_data_upd0_wayA and p0_wren_q; +p0_way_data_upd0_wayB <= p0_congr_cl0_act_q and binv_wayB_upd3_q; +p1_way_data_upd0_wayB <= p1_congr_cl0_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu0_wayB_upd(0) <= p1_way_data_upd0_wayB and p1_wren_q; +rel_bixu0_wayB_upd(1) <= p0_way_data_upd0_wayB and p0_wren_q; +p0_way_data_upd0_wayC <= p0_congr_cl0_act_q and binv_wayC_upd3_q; +p1_way_data_upd0_wayC <= p1_congr_cl0_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu0_wayC_upd(0) <= p1_way_data_upd0_wayC and p1_wren_q; +rel_bixu0_wayC_upd(1) <= p0_way_data_upd0_wayC and p0_wren_q; +p0_way_data_upd0_wayD <= p0_congr_cl0_act_q and binv_wayD_upd3_q; +p1_way_data_upd0_wayD <= p1_congr_cl0_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu0_wayD_upd(0) <= p1_way_data_upd0_wayD and p1_wren_q; +rel_bixu0_wayD_upd(1) <= p0_way_data_upd0_wayD and p0_wren_q; +p0_way_data_upd0_wayE <= p0_congr_cl0_act_q and binv_wayE_upd3_q; +p1_way_data_upd0_wayE <= p1_congr_cl0_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu0_wayE_upd(0) <= p1_way_data_upd0_wayE and p1_wren_q; +rel_bixu0_wayE_upd(1) <= p0_way_data_upd0_wayE and p0_wren_q; +p0_way_data_upd0_wayF <= p0_congr_cl0_act_q and binv_wayF_upd3_q; +p1_way_data_upd0_wayF <= p1_congr_cl0_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu0_wayF_upd(0) <= p1_way_data_upd0_wayF and p1_wren_q; +rel_bixu0_wayF_upd(1) <= p0_way_data_upd0_wayF and p0_wren_q; +p0_way_data_upd0_wayG <= p0_congr_cl0_act_q and binv_wayG_upd3_q; +p1_way_data_upd0_wayG <= p1_congr_cl0_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu0_wayG_upd(0) <= p1_way_data_upd0_wayG and p1_wren_q; +rel_bixu0_wayG_upd(1) <= p0_way_data_upd0_wayG and p0_wren_q; +p0_way_data_upd0_wayH <= p0_congr_cl0_act_q and binv_wayH_upd3_q; +p1_way_data_upd0_wayH <= p1_congr_cl0_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu0_wayH_upd(0) <= p1_way_data_upd0_wayH and p1_wren_q; +rel_bixu0_wayH_upd(1) <= p0_way_data_upd0_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl1_m <= (ex5_congr_cl_q = tconv(1,6)); +p1_congr_cl1_m <= (relu_s_congr_cl_q = tconv(1,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl1_act_d <= p0_congr_cl1_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl1_act_d <= p1_congr_cl1_m and rel_port_wren_q; +congr_cl1_act <= p0_congr_cl1_act_q or p1_congr_cl1_act_q or congr_cl_all_act_q; +p0_way_data_upd1_wayA <= p0_congr_cl1_act_q and binv_wayA_upd3_q; +p1_way_data_upd1_wayA <= p1_congr_cl1_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu1_wayA_upd(0) <= p1_way_data_upd1_wayA and p1_wren_q; +rel_bixu1_wayA_upd(1) <= p0_way_data_upd1_wayA and p0_wren_q; +p0_way_data_upd1_wayB <= p0_congr_cl1_act_q and binv_wayB_upd3_q; +p1_way_data_upd1_wayB <= p1_congr_cl1_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu1_wayB_upd(0) <= p1_way_data_upd1_wayB and p1_wren_q; +rel_bixu1_wayB_upd(1) <= p0_way_data_upd1_wayB and p0_wren_q; +p0_way_data_upd1_wayC <= p0_congr_cl1_act_q and binv_wayC_upd3_q; +p1_way_data_upd1_wayC <= p1_congr_cl1_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu1_wayC_upd(0) <= p1_way_data_upd1_wayC and p1_wren_q; +rel_bixu1_wayC_upd(1) <= p0_way_data_upd1_wayC and p0_wren_q; +p0_way_data_upd1_wayD <= p0_congr_cl1_act_q and binv_wayD_upd3_q; +p1_way_data_upd1_wayD <= p1_congr_cl1_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu1_wayD_upd(0) <= p1_way_data_upd1_wayD and p1_wren_q; +rel_bixu1_wayD_upd(1) <= p0_way_data_upd1_wayD and p0_wren_q; +p0_way_data_upd1_wayE <= p0_congr_cl1_act_q and binv_wayE_upd3_q; +p1_way_data_upd1_wayE <= p1_congr_cl1_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu1_wayE_upd(0) <= p1_way_data_upd1_wayE and p1_wren_q; +rel_bixu1_wayE_upd(1) <= p0_way_data_upd1_wayE and p0_wren_q; +p0_way_data_upd1_wayF <= p0_congr_cl1_act_q and binv_wayF_upd3_q; +p1_way_data_upd1_wayF <= p1_congr_cl1_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu1_wayF_upd(0) <= p1_way_data_upd1_wayF and p1_wren_q; +rel_bixu1_wayF_upd(1) <= p0_way_data_upd1_wayF and p0_wren_q; +p0_way_data_upd1_wayG <= p0_congr_cl1_act_q and binv_wayG_upd3_q; +p1_way_data_upd1_wayG <= p1_congr_cl1_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu1_wayG_upd(0) <= p1_way_data_upd1_wayG and p1_wren_q; +rel_bixu1_wayG_upd(1) <= p0_way_data_upd1_wayG and p0_wren_q; +p0_way_data_upd1_wayH <= p0_congr_cl1_act_q and binv_wayH_upd3_q; +p1_way_data_upd1_wayH <= p1_congr_cl1_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu1_wayH_upd(0) <= p1_way_data_upd1_wayH and p1_wren_q; +rel_bixu1_wayH_upd(1) <= p0_way_data_upd1_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl2_m <= (ex5_congr_cl_q = tconv(2,6)); +p1_congr_cl2_m <= (relu_s_congr_cl_q = tconv(2,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl2_act_d <= p0_congr_cl2_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl2_act_d <= p1_congr_cl2_m and rel_port_wren_q; +congr_cl2_act <= p0_congr_cl2_act_q or p1_congr_cl2_act_q or congr_cl_all_act_q; +p0_way_data_upd2_wayA <= p0_congr_cl2_act_q and binv_wayA_upd3_q; +p1_way_data_upd2_wayA <= p1_congr_cl2_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu2_wayA_upd(0) <= p1_way_data_upd2_wayA and p1_wren_q; +rel_bixu2_wayA_upd(1) <= p0_way_data_upd2_wayA and p0_wren_q; +p0_way_data_upd2_wayB <= p0_congr_cl2_act_q and binv_wayB_upd3_q; +p1_way_data_upd2_wayB <= p1_congr_cl2_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu2_wayB_upd(0) <= p1_way_data_upd2_wayB and p1_wren_q; +rel_bixu2_wayB_upd(1) <= p0_way_data_upd2_wayB and p0_wren_q; +p0_way_data_upd2_wayC <= p0_congr_cl2_act_q and binv_wayC_upd3_q; +p1_way_data_upd2_wayC <= p1_congr_cl2_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu2_wayC_upd(0) <= p1_way_data_upd2_wayC and p1_wren_q; +rel_bixu2_wayC_upd(1) <= p0_way_data_upd2_wayC and p0_wren_q; +p0_way_data_upd2_wayD <= p0_congr_cl2_act_q and binv_wayD_upd3_q; +p1_way_data_upd2_wayD <= p1_congr_cl2_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu2_wayD_upd(0) <= p1_way_data_upd2_wayD and p1_wren_q; +rel_bixu2_wayD_upd(1) <= p0_way_data_upd2_wayD and p0_wren_q; +p0_way_data_upd2_wayE <= p0_congr_cl2_act_q and binv_wayE_upd3_q; +p1_way_data_upd2_wayE <= p1_congr_cl2_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu2_wayE_upd(0) <= p1_way_data_upd2_wayE and p1_wren_q; +rel_bixu2_wayE_upd(1) <= p0_way_data_upd2_wayE and p0_wren_q; +p0_way_data_upd2_wayF <= p0_congr_cl2_act_q and binv_wayF_upd3_q; +p1_way_data_upd2_wayF <= p1_congr_cl2_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu2_wayF_upd(0) <= p1_way_data_upd2_wayF and p1_wren_q; +rel_bixu2_wayF_upd(1) <= p0_way_data_upd2_wayF and p0_wren_q; +p0_way_data_upd2_wayG <= p0_congr_cl2_act_q and binv_wayG_upd3_q; +p1_way_data_upd2_wayG <= p1_congr_cl2_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu2_wayG_upd(0) <= p1_way_data_upd2_wayG and p1_wren_q; +rel_bixu2_wayG_upd(1) <= p0_way_data_upd2_wayG and p0_wren_q; +p0_way_data_upd2_wayH <= p0_congr_cl2_act_q and binv_wayH_upd3_q; +p1_way_data_upd2_wayH <= p1_congr_cl2_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu2_wayH_upd(0) <= p1_way_data_upd2_wayH and p1_wren_q; +rel_bixu2_wayH_upd(1) <= p0_way_data_upd2_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl3_m <= (ex5_congr_cl_q = tconv(3,6)); +p1_congr_cl3_m <= (relu_s_congr_cl_q = tconv(3,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl3_act_d <= p0_congr_cl3_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl3_act_d <= p1_congr_cl3_m and rel_port_wren_q; +congr_cl3_act <= p0_congr_cl3_act_q or p1_congr_cl3_act_q or congr_cl_all_act_q; +p0_way_data_upd3_wayA <= p0_congr_cl3_act_q and binv_wayA_upd3_q; +p1_way_data_upd3_wayA <= p1_congr_cl3_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu3_wayA_upd(0) <= p1_way_data_upd3_wayA and p1_wren_q; +rel_bixu3_wayA_upd(1) <= p0_way_data_upd3_wayA and p0_wren_q; +p0_way_data_upd3_wayB <= p0_congr_cl3_act_q and binv_wayB_upd3_q; +p1_way_data_upd3_wayB <= p1_congr_cl3_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu3_wayB_upd(0) <= p1_way_data_upd3_wayB and p1_wren_q; +rel_bixu3_wayB_upd(1) <= p0_way_data_upd3_wayB and p0_wren_q; +p0_way_data_upd3_wayC <= p0_congr_cl3_act_q and binv_wayC_upd3_q; +p1_way_data_upd3_wayC <= p1_congr_cl3_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu3_wayC_upd(0) <= p1_way_data_upd3_wayC and p1_wren_q; +rel_bixu3_wayC_upd(1) <= p0_way_data_upd3_wayC and p0_wren_q; +p0_way_data_upd3_wayD <= p0_congr_cl3_act_q and binv_wayD_upd3_q; +p1_way_data_upd3_wayD <= p1_congr_cl3_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu3_wayD_upd(0) <= p1_way_data_upd3_wayD and p1_wren_q; +rel_bixu3_wayD_upd(1) <= p0_way_data_upd3_wayD and p0_wren_q; +p0_way_data_upd3_wayE <= p0_congr_cl3_act_q and binv_wayE_upd3_q; +p1_way_data_upd3_wayE <= p1_congr_cl3_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu3_wayE_upd(0) <= p1_way_data_upd3_wayE and p1_wren_q; +rel_bixu3_wayE_upd(1) <= p0_way_data_upd3_wayE and p0_wren_q; +p0_way_data_upd3_wayF <= p0_congr_cl3_act_q and binv_wayF_upd3_q; +p1_way_data_upd3_wayF <= p1_congr_cl3_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu3_wayF_upd(0) <= p1_way_data_upd3_wayF and p1_wren_q; +rel_bixu3_wayF_upd(1) <= p0_way_data_upd3_wayF and p0_wren_q; +p0_way_data_upd3_wayG <= p0_congr_cl3_act_q and binv_wayG_upd3_q; +p1_way_data_upd3_wayG <= p1_congr_cl3_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu3_wayG_upd(0) <= p1_way_data_upd3_wayG and p1_wren_q; +rel_bixu3_wayG_upd(1) <= p0_way_data_upd3_wayG and p0_wren_q; +p0_way_data_upd3_wayH <= p0_congr_cl3_act_q and binv_wayH_upd3_q; +p1_way_data_upd3_wayH <= p1_congr_cl3_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu3_wayH_upd(0) <= p1_way_data_upd3_wayH and p1_wren_q; +rel_bixu3_wayH_upd(1) <= p0_way_data_upd3_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl4_m <= (ex5_congr_cl_q = tconv(4,6)); +p1_congr_cl4_m <= (relu_s_congr_cl_q = tconv(4,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl4_act_d <= p0_congr_cl4_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl4_act_d <= p1_congr_cl4_m and rel_port_wren_q; +congr_cl4_act <= p0_congr_cl4_act_q or p1_congr_cl4_act_q or congr_cl_all_act_q; +p0_way_data_upd4_wayA <= p0_congr_cl4_act_q and binv_wayA_upd3_q; +p1_way_data_upd4_wayA <= p1_congr_cl4_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu4_wayA_upd(0) <= p1_way_data_upd4_wayA and p1_wren_q; +rel_bixu4_wayA_upd(1) <= p0_way_data_upd4_wayA and p0_wren_q; +p0_way_data_upd4_wayB <= p0_congr_cl4_act_q and binv_wayB_upd3_q; +p1_way_data_upd4_wayB <= p1_congr_cl4_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu4_wayB_upd(0) <= p1_way_data_upd4_wayB and p1_wren_q; +rel_bixu4_wayB_upd(1) <= p0_way_data_upd4_wayB and p0_wren_q; +p0_way_data_upd4_wayC <= p0_congr_cl4_act_q and binv_wayC_upd3_q; +p1_way_data_upd4_wayC <= p1_congr_cl4_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu4_wayC_upd(0) <= p1_way_data_upd4_wayC and p1_wren_q; +rel_bixu4_wayC_upd(1) <= p0_way_data_upd4_wayC and p0_wren_q; +p0_way_data_upd4_wayD <= p0_congr_cl4_act_q and binv_wayD_upd3_q; +p1_way_data_upd4_wayD <= p1_congr_cl4_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu4_wayD_upd(0) <= p1_way_data_upd4_wayD and p1_wren_q; +rel_bixu4_wayD_upd(1) <= p0_way_data_upd4_wayD and p0_wren_q; +p0_way_data_upd4_wayE <= p0_congr_cl4_act_q and binv_wayE_upd3_q; +p1_way_data_upd4_wayE <= p1_congr_cl4_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu4_wayE_upd(0) <= p1_way_data_upd4_wayE and p1_wren_q; +rel_bixu4_wayE_upd(1) <= p0_way_data_upd4_wayE and p0_wren_q; +p0_way_data_upd4_wayF <= p0_congr_cl4_act_q and binv_wayF_upd3_q; +p1_way_data_upd4_wayF <= p1_congr_cl4_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu4_wayF_upd(0) <= p1_way_data_upd4_wayF and p1_wren_q; +rel_bixu4_wayF_upd(1) <= p0_way_data_upd4_wayF and p0_wren_q; +p0_way_data_upd4_wayG <= p0_congr_cl4_act_q and binv_wayG_upd3_q; +p1_way_data_upd4_wayG <= p1_congr_cl4_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu4_wayG_upd(0) <= p1_way_data_upd4_wayG and p1_wren_q; +rel_bixu4_wayG_upd(1) <= p0_way_data_upd4_wayG and p0_wren_q; +p0_way_data_upd4_wayH <= p0_congr_cl4_act_q and binv_wayH_upd3_q; +p1_way_data_upd4_wayH <= p1_congr_cl4_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu4_wayH_upd(0) <= p1_way_data_upd4_wayH and p1_wren_q; +rel_bixu4_wayH_upd(1) <= p0_way_data_upd4_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl5_m <= (ex5_congr_cl_q = tconv(5,6)); +p1_congr_cl5_m <= (relu_s_congr_cl_q = tconv(5,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl5_act_d <= p0_congr_cl5_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl5_act_d <= p1_congr_cl5_m and rel_port_wren_q; +congr_cl5_act <= p0_congr_cl5_act_q or p1_congr_cl5_act_q or congr_cl_all_act_q; +p0_way_data_upd5_wayA <= p0_congr_cl5_act_q and binv_wayA_upd3_q; +p1_way_data_upd5_wayA <= p1_congr_cl5_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu5_wayA_upd(0) <= p1_way_data_upd5_wayA and p1_wren_q; +rel_bixu5_wayA_upd(1) <= p0_way_data_upd5_wayA and p0_wren_q; +p0_way_data_upd5_wayB <= p0_congr_cl5_act_q and binv_wayB_upd3_q; +p1_way_data_upd5_wayB <= p1_congr_cl5_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu5_wayB_upd(0) <= p1_way_data_upd5_wayB and p1_wren_q; +rel_bixu5_wayB_upd(1) <= p0_way_data_upd5_wayB and p0_wren_q; +p0_way_data_upd5_wayC <= p0_congr_cl5_act_q and binv_wayC_upd3_q; +p1_way_data_upd5_wayC <= p1_congr_cl5_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu5_wayC_upd(0) <= p1_way_data_upd5_wayC and p1_wren_q; +rel_bixu5_wayC_upd(1) <= p0_way_data_upd5_wayC and p0_wren_q; +p0_way_data_upd5_wayD <= p0_congr_cl5_act_q and binv_wayD_upd3_q; +p1_way_data_upd5_wayD <= p1_congr_cl5_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu5_wayD_upd(0) <= p1_way_data_upd5_wayD and p1_wren_q; +rel_bixu5_wayD_upd(1) <= p0_way_data_upd5_wayD and p0_wren_q; +p0_way_data_upd5_wayE <= p0_congr_cl5_act_q and binv_wayE_upd3_q; +p1_way_data_upd5_wayE <= p1_congr_cl5_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu5_wayE_upd(0) <= p1_way_data_upd5_wayE and p1_wren_q; +rel_bixu5_wayE_upd(1) <= p0_way_data_upd5_wayE and p0_wren_q; +p0_way_data_upd5_wayF <= p0_congr_cl5_act_q and binv_wayF_upd3_q; +p1_way_data_upd5_wayF <= p1_congr_cl5_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu5_wayF_upd(0) <= p1_way_data_upd5_wayF and p1_wren_q; +rel_bixu5_wayF_upd(1) <= p0_way_data_upd5_wayF and p0_wren_q; +p0_way_data_upd5_wayG <= p0_congr_cl5_act_q and binv_wayG_upd3_q; +p1_way_data_upd5_wayG <= p1_congr_cl5_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu5_wayG_upd(0) <= p1_way_data_upd5_wayG and p1_wren_q; +rel_bixu5_wayG_upd(1) <= p0_way_data_upd5_wayG and p0_wren_q; +p0_way_data_upd5_wayH <= p0_congr_cl5_act_q and binv_wayH_upd3_q; +p1_way_data_upd5_wayH <= p1_congr_cl5_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu5_wayH_upd(0) <= p1_way_data_upd5_wayH and p1_wren_q; +rel_bixu5_wayH_upd(1) <= p0_way_data_upd5_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl6_m <= (ex5_congr_cl_q = tconv(6,6)); +p1_congr_cl6_m <= (relu_s_congr_cl_q = tconv(6,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl6_act_d <= p0_congr_cl6_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl6_act_d <= p1_congr_cl6_m and rel_port_wren_q; +congr_cl6_act <= p0_congr_cl6_act_q or p1_congr_cl6_act_q or congr_cl_all_act_q; +p0_way_data_upd6_wayA <= p0_congr_cl6_act_q and binv_wayA_upd3_q; +p1_way_data_upd6_wayA <= p1_congr_cl6_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu6_wayA_upd(0) <= p1_way_data_upd6_wayA and p1_wren_q; +rel_bixu6_wayA_upd(1) <= p0_way_data_upd6_wayA and p0_wren_q; +p0_way_data_upd6_wayB <= p0_congr_cl6_act_q and binv_wayB_upd3_q; +p1_way_data_upd6_wayB <= p1_congr_cl6_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu6_wayB_upd(0) <= p1_way_data_upd6_wayB and p1_wren_q; +rel_bixu6_wayB_upd(1) <= p0_way_data_upd6_wayB and p0_wren_q; +p0_way_data_upd6_wayC <= p0_congr_cl6_act_q and binv_wayC_upd3_q; +p1_way_data_upd6_wayC <= p1_congr_cl6_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu6_wayC_upd(0) <= p1_way_data_upd6_wayC and p1_wren_q; +rel_bixu6_wayC_upd(1) <= p0_way_data_upd6_wayC and p0_wren_q; +p0_way_data_upd6_wayD <= p0_congr_cl6_act_q and binv_wayD_upd3_q; +p1_way_data_upd6_wayD <= p1_congr_cl6_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu6_wayD_upd(0) <= p1_way_data_upd6_wayD and p1_wren_q; +rel_bixu6_wayD_upd(1) <= p0_way_data_upd6_wayD and p0_wren_q; +p0_way_data_upd6_wayE <= p0_congr_cl6_act_q and binv_wayE_upd3_q; +p1_way_data_upd6_wayE <= p1_congr_cl6_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu6_wayE_upd(0) <= p1_way_data_upd6_wayE and p1_wren_q; +rel_bixu6_wayE_upd(1) <= p0_way_data_upd6_wayE and p0_wren_q; +p0_way_data_upd6_wayF <= p0_congr_cl6_act_q and binv_wayF_upd3_q; +p1_way_data_upd6_wayF <= p1_congr_cl6_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu6_wayF_upd(0) <= p1_way_data_upd6_wayF and p1_wren_q; +rel_bixu6_wayF_upd(1) <= p0_way_data_upd6_wayF and p0_wren_q; +p0_way_data_upd6_wayG <= p0_congr_cl6_act_q and binv_wayG_upd3_q; +p1_way_data_upd6_wayG <= p1_congr_cl6_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu6_wayG_upd(0) <= p1_way_data_upd6_wayG and p1_wren_q; +rel_bixu6_wayG_upd(1) <= p0_way_data_upd6_wayG and p0_wren_q; +p0_way_data_upd6_wayH <= p0_congr_cl6_act_q and binv_wayH_upd3_q; +p1_way_data_upd6_wayH <= p1_congr_cl6_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu6_wayH_upd(0) <= p1_way_data_upd6_wayH and p1_wren_q; +rel_bixu6_wayH_upd(1) <= p0_way_data_upd6_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl7_m <= (ex5_congr_cl_q = tconv(7,6)); +p1_congr_cl7_m <= (relu_s_congr_cl_q = tconv(7,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl7_act_d <= p0_congr_cl7_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl7_act_d <= p1_congr_cl7_m and rel_port_wren_q; +congr_cl7_act <= p0_congr_cl7_act_q or p1_congr_cl7_act_q or congr_cl_all_act_q; +p0_way_data_upd7_wayA <= p0_congr_cl7_act_q and binv_wayA_upd3_q; +p1_way_data_upd7_wayA <= p1_congr_cl7_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu7_wayA_upd(0) <= p1_way_data_upd7_wayA and p1_wren_q; +rel_bixu7_wayA_upd(1) <= p0_way_data_upd7_wayA and p0_wren_q; +p0_way_data_upd7_wayB <= p0_congr_cl7_act_q and binv_wayB_upd3_q; +p1_way_data_upd7_wayB <= p1_congr_cl7_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu7_wayB_upd(0) <= p1_way_data_upd7_wayB and p1_wren_q; +rel_bixu7_wayB_upd(1) <= p0_way_data_upd7_wayB and p0_wren_q; +p0_way_data_upd7_wayC <= p0_congr_cl7_act_q and binv_wayC_upd3_q; +p1_way_data_upd7_wayC <= p1_congr_cl7_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu7_wayC_upd(0) <= p1_way_data_upd7_wayC and p1_wren_q; +rel_bixu7_wayC_upd(1) <= p0_way_data_upd7_wayC and p0_wren_q; +p0_way_data_upd7_wayD <= p0_congr_cl7_act_q and binv_wayD_upd3_q; +p1_way_data_upd7_wayD <= p1_congr_cl7_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu7_wayD_upd(0) <= p1_way_data_upd7_wayD and p1_wren_q; +rel_bixu7_wayD_upd(1) <= p0_way_data_upd7_wayD and p0_wren_q; +p0_way_data_upd7_wayE <= p0_congr_cl7_act_q and binv_wayE_upd3_q; +p1_way_data_upd7_wayE <= p1_congr_cl7_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu7_wayE_upd(0) <= p1_way_data_upd7_wayE and p1_wren_q; +rel_bixu7_wayE_upd(1) <= p0_way_data_upd7_wayE and p0_wren_q; +p0_way_data_upd7_wayF <= p0_congr_cl7_act_q and binv_wayF_upd3_q; +p1_way_data_upd7_wayF <= p1_congr_cl7_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu7_wayF_upd(0) <= p1_way_data_upd7_wayF and p1_wren_q; +rel_bixu7_wayF_upd(1) <= p0_way_data_upd7_wayF and p0_wren_q; +p0_way_data_upd7_wayG <= p0_congr_cl7_act_q and binv_wayG_upd3_q; +p1_way_data_upd7_wayG <= p1_congr_cl7_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu7_wayG_upd(0) <= p1_way_data_upd7_wayG and p1_wren_q; +rel_bixu7_wayG_upd(1) <= p0_way_data_upd7_wayG and p0_wren_q; +p0_way_data_upd7_wayH <= p0_congr_cl7_act_q and binv_wayH_upd3_q; +p1_way_data_upd7_wayH <= p1_congr_cl7_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu7_wayH_upd(0) <= p1_way_data_upd7_wayH and p1_wren_q; +rel_bixu7_wayH_upd(1) <= p0_way_data_upd7_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl8_m <= (ex5_congr_cl_q = tconv(8,6)); +p1_congr_cl8_m <= (relu_s_congr_cl_q = tconv(8,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl8_act_d <= p0_congr_cl8_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl8_act_d <= p1_congr_cl8_m and rel_port_wren_q; +congr_cl8_act <= p0_congr_cl8_act_q or p1_congr_cl8_act_q or congr_cl_all_act_q; +p0_way_data_upd8_wayA <= p0_congr_cl8_act_q and binv_wayA_upd3_q; +p1_way_data_upd8_wayA <= p1_congr_cl8_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu8_wayA_upd(0) <= p1_way_data_upd8_wayA and p1_wren_q; +rel_bixu8_wayA_upd(1) <= p0_way_data_upd8_wayA and p0_wren_q; +p0_way_data_upd8_wayB <= p0_congr_cl8_act_q and binv_wayB_upd3_q; +p1_way_data_upd8_wayB <= p1_congr_cl8_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu8_wayB_upd(0) <= p1_way_data_upd8_wayB and p1_wren_q; +rel_bixu8_wayB_upd(1) <= p0_way_data_upd8_wayB and p0_wren_q; +p0_way_data_upd8_wayC <= p0_congr_cl8_act_q and binv_wayC_upd3_q; +p1_way_data_upd8_wayC <= p1_congr_cl8_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu8_wayC_upd(0) <= p1_way_data_upd8_wayC and p1_wren_q; +rel_bixu8_wayC_upd(1) <= p0_way_data_upd8_wayC and p0_wren_q; +p0_way_data_upd8_wayD <= p0_congr_cl8_act_q and binv_wayD_upd3_q; +p1_way_data_upd8_wayD <= p1_congr_cl8_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu8_wayD_upd(0) <= p1_way_data_upd8_wayD and p1_wren_q; +rel_bixu8_wayD_upd(1) <= p0_way_data_upd8_wayD and p0_wren_q; +p0_way_data_upd8_wayE <= p0_congr_cl8_act_q and binv_wayE_upd3_q; +p1_way_data_upd8_wayE <= p1_congr_cl8_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu8_wayE_upd(0) <= p1_way_data_upd8_wayE and p1_wren_q; +rel_bixu8_wayE_upd(1) <= p0_way_data_upd8_wayE and p0_wren_q; +p0_way_data_upd8_wayF <= p0_congr_cl8_act_q and binv_wayF_upd3_q; +p1_way_data_upd8_wayF <= p1_congr_cl8_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu8_wayF_upd(0) <= p1_way_data_upd8_wayF and p1_wren_q; +rel_bixu8_wayF_upd(1) <= p0_way_data_upd8_wayF and p0_wren_q; +p0_way_data_upd8_wayG <= p0_congr_cl8_act_q and binv_wayG_upd3_q; +p1_way_data_upd8_wayG <= p1_congr_cl8_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu8_wayG_upd(0) <= p1_way_data_upd8_wayG and p1_wren_q; +rel_bixu8_wayG_upd(1) <= p0_way_data_upd8_wayG and p0_wren_q; +p0_way_data_upd8_wayH <= p0_congr_cl8_act_q and binv_wayH_upd3_q; +p1_way_data_upd8_wayH <= p1_congr_cl8_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu8_wayH_upd(0) <= p1_way_data_upd8_wayH and p1_wren_q; +rel_bixu8_wayH_upd(1) <= p0_way_data_upd8_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl9_m <= (ex5_congr_cl_q = tconv(9,6)); +p1_congr_cl9_m <= (relu_s_congr_cl_q = tconv(9,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl9_act_d <= p0_congr_cl9_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl9_act_d <= p1_congr_cl9_m and rel_port_wren_q; +congr_cl9_act <= p0_congr_cl9_act_q or p1_congr_cl9_act_q or congr_cl_all_act_q; +p0_way_data_upd9_wayA <= p0_congr_cl9_act_q and binv_wayA_upd3_q; +p1_way_data_upd9_wayA <= p1_congr_cl9_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu9_wayA_upd(0) <= p1_way_data_upd9_wayA and p1_wren_q; +rel_bixu9_wayA_upd(1) <= p0_way_data_upd9_wayA and p0_wren_q; +p0_way_data_upd9_wayB <= p0_congr_cl9_act_q and binv_wayB_upd3_q; +p1_way_data_upd9_wayB <= p1_congr_cl9_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu9_wayB_upd(0) <= p1_way_data_upd9_wayB and p1_wren_q; +rel_bixu9_wayB_upd(1) <= p0_way_data_upd9_wayB and p0_wren_q; +p0_way_data_upd9_wayC <= p0_congr_cl9_act_q and binv_wayC_upd3_q; +p1_way_data_upd9_wayC <= p1_congr_cl9_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu9_wayC_upd(0) <= p1_way_data_upd9_wayC and p1_wren_q; +rel_bixu9_wayC_upd(1) <= p0_way_data_upd9_wayC and p0_wren_q; +p0_way_data_upd9_wayD <= p0_congr_cl9_act_q and binv_wayD_upd3_q; +p1_way_data_upd9_wayD <= p1_congr_cl9_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu9_wayD_upd(0) <= p1_way_data_upd9_wayD and p1_wren_q; +rel_bixu9_wayD_upd(1) <= p0_way_data_upd9_wayD and p0_wren_q; +p0_way_data_upd9_wayE <= p0_congr_cl9_act_q and binv_wayE_upd3_q; +p1_way_data_upd9_wayE <= p1_congr_cl9_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu9_wayE_upd(0) <= p1_way_data_upd9_wayE and p1_wren_q; +rel_bixu9_wayE_upd(1) <= p0_way_data_upd9_wayE and p0_wren_q; +p0_way_data_upd9_wayF <= p0_congr_cl9_act_q and binv_wayF_upd3_q; +p1_way_data_upd9_wayF <= p1_congr_cl9_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu9_wayF_upd(0) <= p1_way_data_upd9_wayF and p1_wren_q; +rel_bixu9_wayF_upd(1) <= p0_way_data_upd9_wayF and p0_wren_q; +p0_way_data_upd9_wayG <= p0_congr_cl9_act_q and binv_wayG_upd3_q; +p1_way_data_upd9_wayG <= p1_congr_cl9_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu9_wayG_upd(0) <= p1_way_data_upd9_wayG and p1_wren_q; +rel_bixu9_wayG_upd(1) <= p0_way_data_upd9_wayG and p0_wren_q; +p0_way_data_upd9_wayH <= p0_congr_cl9_act_q and binv_wayH_upd3_q; +p1_way_data_upd9_wayH <= p1_congr_cl9_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu9_wayH_upd(0) <= p1_way_data_upd9_wayH and p1_wren_q; +rel_bixu9_wayH_upd(1) <= p0_way_data_upd9_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl10_m <= (ex5_congr_cl_q = tconv(10,6)); +p1_congr_cl10_m <= (relu_s_congr_cl_q = tconv(10,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl10_act_d <= p0_congr_cl10_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl10_act_d <= p1_congr_cl10_m and rel_port_wren_q; +congr_cl10_act <= p0_congr_cl10_act_q or p1_congr_cl10_act_q or congr_cl_all_act_q; +p0_way_data_upd10_wayA <= p0_congr_cl10_act_q and binv_wayA_upd3_q; +p1_way_data_upd10_wayA <= p1_congr_cl10_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu10_wayA_upd(0) <= p1_way_data_upd10_wayA and p1_wren_q; +rel_bixu10_wayA_upd(1) <= p0_way_data_upd10_wayA and p0_wren_q; +p0_way_data_upd10_wayB <= p0_congr_cl10_act_q and binv_wayB_upd3_q; +p1_way_data_upd10_wayB <= p1_congr_cl10_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu10_wayB_upd(0) <= p1_way_data_upd10_wayB and p1_wren_q; +rel_bixu10_wayB_upd(1) <= p0_way_data_upd10_wayB and p0_wren_q; +p0_way_data_upd10_wayC <= p0_congr_cl10_act_q and binv_wayC_upd3_q; +p1_way_data_upd10_wayC <= p1_congr_cl10_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu10_wayC_upd(0) <= p1_way_data_upd10_wayC and p1_wren_q; +rel_bixu10_wayC_upd(1) <= p0_way_data_upd10_wayC and p0_wren_q; +p0_way_data_upd10_wayD <= p0_congr_cl10_act_q and binv_wayD_upd3_q; +p1_way_data_upd10_wayD <= p1_congr_cl10_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu10_wayD_upd(0) <= p1_way_data_upd10_wayD and p1_wren_q; +rel_bixu10_wayD_upd(1) <= p0_way_data_upd10_wayD and p0_wren_q; +p0_way_data_upd10_wayE <= p0_congr_cl10_act_q and binv_wayE_upd3_q; +p1_way_data_upd10_wayE <= p1_congr_cl10_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu10_wayE_upd(0) <= p1_way_data_upd10_wayE and p1_wren_q; +rel_bixu10_wayE_upd(1) <= p0_way_data_upd10_wayE and p0_wren_q; +p0_way_data_upd10_wayF <= p0_congr_cl10_act_q and binv_wayF_upd3_q; +p1_way_data_upd10_wayF <= p1_congr_cl10_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu10_wayF_upd(0) <= p1_way_data_upd10_wayF and p1_wren_q; +rel_bixu10_wayF_upd(1) <= p0_way_data_upd10_wayF and p0_wren_q; +p0_way_data_upd10_wayG <= p0_congr_cl10_act_q and binv_wayG_upd3_q; +p1_way_data_upd10_wayG <= p1_congr_cl10_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu10_wayG_upd(0) <= p1_way_data_upd10_wayG and p1_wren_q; +rel_bixu10_wayG_upd(1) <= p0_way_data_upd10_wayG and p0_wren_q; +p0_way_data_upd10_wayH <= p0_congr_cl10_act_q and binv_wayH_upd3_q; +p1_way_data_upd10_wayH <= p1_congr_cl10_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu10_wayH_upd(0) <= p1_way_data_upd10_wayH and p1_wren_q; +rel_bixu10_wayH_upd(1) <= p0_way_data_upd10_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl11_m <= (ex5_congr_cl_q = tconv(11,6)); +p1_congr_cl11_m <= (relu_s_congr_cl_q = tconv(11,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl11_act_d <= p0_congr_cl11_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl11_act_d <= p1_congr_cl11_m and rel_port_wren_q; +congr_cl11_act <= p0_congr_cl11_act_q or p1_congr_cl11_act_q or congr_cl_all_act_q; +p0_way_data_upd11_wayA <= p0_congr_cl11_act_q and binv_wayA_upd3_q; +p1_way_data_upd11_wayA <= p1_congr_cl11_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu11_wayA_upd(0) <= p1_way_data_upd11_wayA and p1_wren_q; +rel_bixu11_wayA_upd(1) <= p0_way_data_upd11_wayA and p0_wren_q; +p0_way_data_upd11_wayB <= p0_congr_cl11_act_q and binv_wayB_upd3_q; +p1_way_data_upd11_wayB <= p1_congr_cl11_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu11_wayB_upd(0) <= p1_way_data_upd11_wayB and p1_wren_q; +rel_bixu11_wayB_upd(1) <= p0_way_data_upd11_wayB and p0_wren_q; +p0_way_data_upd11_wayC <= p0_congr_cl11_act_q and binv_wayC_upd3_q; +p1_way_data_upd11_wayC <= p1_congr_cl11_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu11_wayC_upd(0) <= p1_way_data_upd11_wayC and p1_wren_q; +rel_bixu11_wayC_upd(1) <= p0_way_data_upd11_wayC and p0_wren_q; +p0_way_data_upd11_wayD <= p0_congr_cl11_act_q and binv_wayD_upd3_q; +p1_way_data_upd11_wayD <= p1_congr_cl11_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu11_wayD_upd(0) <= p1_way_data_upd11_wayD and p1_wren_q; +rel_bixu11_wayD_upd(1) <= p0_way_data_upd11_wayD and p0_wren_q; +p0_way_data_upd11_wayE <= p0_congr_cl11_act_q and binv_wayE_upd3_q; +p1_way_data_upd11_wayE <= p1_congr_cl11_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu11_wayE_upd(0) <= p1_way_data_upd11_wayE and p1_wren_q; +rel_bixu11_wayE_upd(1) <= p0_way_data_upd11_wayE and p0_wren_q; +p0_way_data_upd11_wayF <= p0_congr_cl11_act_q and binv_wayF_upd3_q; +p1_way_data_upd11_wayF <= p1_congr_cl11_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu11_wayF_upd(0) <= p1_way_data_upd11_wayF and p1_wren_q; +rel_bixu11_wayF_upd(1) <= p0_way_data_upd11_wayF and p0_wren_q; +p0_way_data_upd11_wayG <= p0_congr_cl11_act_q and binv_wayG_upd3_q; +p1_way_data_upd11_wayG <= p1_congr_cl11_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu11_wayG_upd(0) <= p1_way_data_upd11_wayG and p1_wren_q; +rel_bixu11_wayG_upd(1) <= p0_way_data_upd11_wayG and p0_wren_q; +p0_way_data_upd11_wayH <= p0_congr_cl11_act_q and binv_wayH_upd3_q; +p1_way_data_upd11_wayH <= p1_congr_cl11_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu11_wayH_upd(0) <= p1_way_data_upd11_wayH and p1_wren_q; +rel_bixu11_wayH_upd(1) <= p0_way_data_upd11_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl12_m <= (ex5_congr_cl_q = tconv(12,6)); +p1_congr_cl12_m <= (relu_s_congr_cl_q = tconv(12,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl12_act_d <= p0_congr_cl12_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl12_act_d <= p1_congr_cl12_m and rel_port_wren_q; +congr_cl12_act <= p0_congr_cl12_act_q or p1_congr_cl12_act_q or congr_cl_all_act_q; +p0_way_data_upd12_wayA <= p0_congr_cl12_act_q and binv_wayA_upd3_q; +p1_way_data_upd12_wayA <= p1_congr_cl12_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu12_wayA_upd(0) <= p1_way_data_upd12_wayA and p1_wren_q; +rel_bixu12_wayA_upd(1) <= p0_way_data_upd12_wayA and p0_wren_q; +p0_way_data_upd12_wayB <= p0_congr_cl12_act_q and binv_wayB_upd3_q; +p1_way_data_upd12_wayB <= p1_congr_cl12_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu12_wayB_upd(0) <= p1_way_data_upd12_wayB and p1_wren_q; +rel_bixu12_wayB_upd(1) <= p0_way_data_upd12_wayB and p0_wren_q; +p0_way_data_upd12_wayC <= p0_congr_cl12_act_q and binv_wayC_upd3_q; +p1_way_data_upd12_wayC <= p1_congr_cl12_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu12_wayC_upd(0) <= p1_way_data_upd12_wayC and p1_wren_q; +rel_bixu12_wayC_upd(1) <= p0_way_data_upd12_wayC and p0_wren_q; +p0_way_data_upd12_wayD <= p0_congr_cl12_act_q and binv_wayD_upd3_q; +p1_way_data_upd12_wayD <= p1_congr_cl12_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu12_wayD_upd(0) <= p1_way_data_upd12_wayD and p1_wren_q; +rel_bixu12_wayD_upd(1) <= p0_way_data_upd12_wayD and p0_wren_q; +p0_way_data_upd12_wayE <= p0_congr_cl12_act_q and binv_wayE_upd3_q; +p1_way_data_upd12_wayE <= p1_congr_cl12_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu12_wayE_upd(0) <= p1_way_data_upd12_wayE and p1_wren_q; +rel_bixu12_wayE_upd(1) <= p0_way_data_upd12_wayE and p0_wren_q; +p0_way_data_upd12_wayF <= p0_congr_cl12_act_q and binv_wayF_upd3_q; +p1_way_data_upd12_wayF <= p1_congr_cl12_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu12_wayF_upd(0) <= p1_way_data_upd12_wayF and p1_wren_q; +rel_bixu12_wayF_upd(1) <= p0_way_data_upd12_wayF and p0_wren_q; +p0_way_data_upd12_wayG <= p0_congr_cl12_act_q and binv_wayG_upd3_q; +p1_way_data_upd12_wayG <= p1_congr_cl12_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu12_wayG_upd(0) <= p1_way_data_upd12_wayG and p1_wren_q; +rel_bixu12_wayG_upd(1) <= p0_way_data_upd12_wayG and p0_wren_q; +p0_way_data_upd12_wayH <= p0_congr_cl12_act_q and binv_wayH_upd3_q; +p1_way_data_upd12_wayH <= p1_congr_cl12_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu12_wayH_upd(0) <= p1_way_data_upd12_wayH and p1_wren_q; +rel_bixu12_wayH_upd(1) <= p0_way_data_upd12_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl13_m <= (ex5_congr_cl_q = tconv(13,6)); +p1_congr_cl13_m <= (relu_s_congr_cl_q = tconv(13,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl13_act_d <= p0_congr_cl13_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl13_act_d <= p1_congr_cl13_m and rel_port_wren_q; +congr_cl13_act <= p0_congr_cl13_act_q or p1_congr_cl13_act_q or congr_cl_all_act_q; +p0_way_data_upd13_wayA <= p0_congr_cl13_act_q and binv_wayA_upd3_q; +p1_way_data_upd13_wayA <= p1_congr_cl13_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu13_wayA_upd(0) <= p1_way_data_upd13_wayA and p1_wren_q; +rel_bixu13_wayA_upd(1) <= p0_way_data_upd13_wayA and p0_wren_q; +p0_way_data_upd13_wayB <= p0_congr_cl13_act_q and binv_wayB_upd3_q; +p1_way_data_upd13_wayB <= p1_congr_cl13_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu13_wayB_upd(0) <= p1_way_data_upd13_wayB and p1_wren_q; +rel_bixu13_wayB_upd(1) <= p0_way_data_upd13_wayB and p0_wren_q; +p0_way_data_upd13_wayC <= p0_congr_cl13_act_q and binv_wayC_upd3_q; +p1_way_data_upd13_wayC <= p1_congr_cl13_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu13_wayC_upd(0) <= p1_way_data_upd13_wayC and p1_wren_q; +rel_bixu13_wayC_upd(1) <= p0_way_data_upd13_wayC and p0_wren_q; +p0_way_data_upd13_wayD <= p0_congr_cl13_act_q and binv_wayD_upd3_q; +p1_way_data_upd13_wayD <= p1_congr_cl13_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu13_wayD_upd(0) <= p1_way_data_upd13_wayD and p1_wren_q; +rel_bixu13_wayD_upd(1) <= p0_way_data_upd13_wayD and p0_wren_q; +p0_way_data_upd13_wayE <= p0_congr_cl13_act_q and binv_wayE_upd3_q; +p1_way_data_upd13_wayE <= p1_congr_cl13_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu13_wayE_upd(0) <= p1_way_data_upd13_wayE and p1_wren_q; +rel_bixu13_wayE_upd(1) <= p0_way_data_upd13_wayE and p0_wren_q; +p0_way_data_upd13_wayF <= p0_congr_cl13_act_q and binv_wayF_upd3_q; +p1_way_data_upd13_wayF <= p1_congr_cl13_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu13_wayF_upd(0) <= p1_way_data_upd13_wayF and p1_wren_q; +rel_bixu13_wayF_upd(1) <= p0_way_data_upd13_wayF and p0_wren_q; +p0_way_data_upd13_wayG <= p0_congr_cl13_act_q and binv_wayG_upd3_q; +p1_way_data_upd13_wayG <= p1_congr_cl13_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu13_wayG_upd(0) <= p1_way_data_upd13_wayG and p1_wren_q; +rel_bixu13_wayG_upd(1) <= p0_way_data_upd13_wayG and p0_wren_q; +p0_way_data_upd13_wayH <= p0_congr_cl13_act_q and binv_wayH_upd3_q; +p1_way_data_upd13_wayH <= p1_congr_cl13_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu13_wayH_upd(0) <= p1_way_data_upd13_wayH and p1_wren_q; +rel_bixu13_wayH_upd(1) <= p0_way_data_upd13_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl14_m <= (ex5_congr_cl_q = tconv(14,6)); +p1_congr_cl14_m <= (relu_s_congr_cl_q = tconv(14,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl14_act_d <= p0_congr_cl14_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl14_act_d <= p1_congr_cl14_m and rel_port_wren_q; +congr_cl14_act <= p0_congr_cl14_act_q or p1_congr_cl14_act_q or congr_cl_all_act_q; +p0_way_data_upd14_wayA <= p0_congr_cl14_act_q and binv_wayA_upd3_q; +p1_way_data_upd14_wayA <= p1_congr_cl14_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu14_wayA_upd(0) <= p1_way_data_upd14_wayA and p1_wren_q; +rel_bixu14_wayA_upd(1) <= p0_way_data_upd14_wayA and p0_wren_q; +p0_way_data_upd14_wayB <= p0_congr_cl14_act_q and binv_wayB_upd3_q; +p1_way_data_upd14_wayB <= p1_congr_cl14_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu14_wayB_upd(0) <= p1_way_data_upd14_wayB and p1_wren_q; +rel_bixu14_wayB_upd(1) <= p0_way_data_upd14_wayB and p0_wren_q; +p0_way_data_upd14_wayC <= p0_congr_cl14_act_q and binv_wayC_upd3_q; +p1_way_data_upd14_wayC <= p1_congr_cl14_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu14_wayC_upd(0) <= p1_way_data_upd14_wayC and p1_wren_q; +rel_bixu14_wayC_upd(1) <= p0_way_data_upd14_wayC and p0_wren_q; +p0_way_data_upd14_wayD <= p0_congr_cl14_act_q and binv_wayD_upd3_q; +p1_way_data_upd14_wayD <= p1_congr_cl14_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu14_wayD_upd(0) <= p1_way_data_upd14_wayD and p1_wren_q; +rel_bixu14_wayD_upd(1) <= p0_way_data_upd14_wayD and p0_wren_q; +p0_way_data_upd14_wayE <= p0_congr_cl14_act_q and binv_wayE_upd3_q; +p1_way_data_upd14_wayE <= p1_congr_cl14_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu14_wayE_upd(0) <= p1_way_data_upd14_wayE and p1_wren_q; +rel_bixu14_wayE_upd(1) <= p0_way_data_upd14_wayE and p0_wren_q; +p0_way_data_upd14_wayF <= p0_congr_cl14_act_q and binv_wayF_upd3_q; +p1_way_data_upd14_wayF <= p1_congr_cl14_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu14_wayF_upd(0) <= p1_way_data_upd14_wayF and p1_wren_q; +rel_bixu14_wayF_upd(1) <= p0_way_data_upd14_wayF and p0_wren_q; +p0_way_data_upd14_wayG <= p0_congr_cl14_act_q and binv_wayG_upd3_q; +p1_way_data_upd14_wayG <= p1_congr_cl14_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu14_wayG_upd(0) <= p1_way_data_upd14_wayG and p1_wren_q; +rel_bixu14_wayG_upd(1) <= p0_way_data_upd14_wayG and p0_wren_q; +p0_way_data_upd14_wayH <= p0_congr_cl14_act_q and binv_wayH_upd3_q; +p1_way_data_upd14_wayH <= p1_congr_cl14_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu14_wayH_upd(0) <= p1_way_data_upd14_wayH and p1_wren_q; +rel_bixu14_wayH_upd(1) <= p0_way_data_upd14_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl15_m <= (ex5_congr_cl_q = tconv(15,6)); +p1_congr_cl15_m <= (relu_s_congr_cl_q = tconv(15,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl15_act_d <= p0_congr_cl15_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl15_act_d <= p1_congr_cl15_m and rel_port_wren_q; +congr_cl15_act <= p0_congr_cl15_act_q or p1_congr_cl15_act_q or congr_cl_all_act_q; +p0_way_data_upd15_wayA <= p0_congr_cl15_act_q and binv_wayA_upd3_q; +p1_way_data_upd15_wayA <= p1_congr_cl15_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu15_wayA_upd(0) <= p1_way_data_upd15_wayA and p1_wren_q; +rel_bixu15_wayA_upd(1) <= p0_way_data_upd15_wayA and p0_wren_q; +p0_way_data_upd15_wayB <= p0_congr_cl15_act_q and binv_wayB_upd3_q; +p1_way_data_upd15_wayB <= p1_congr_cl15_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu15_wayB_upd(0) <= p1_way_data_upd15_wayB and p1_wren_q; +rel_bixu15_wayB_upd(1) <= p0_way_data_upd15_wayB and p0_wren_q; +p0_way_data_upd15_wayC <= p0_congr_cl15_act_q and binv_wayC_upd3_q; +p1_way_data_upd15_wayC <= p1_congr_cl15_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu15_wayC_upd(0) <= p1_way_data_upd15_wayC and p1_wren_q; +rel_bixu15_wayC_upd(1) <= p0_way_data_upd15_wayC and p0_wren_q; +p0_way_data_upd15_wayD <= p0_congr_cl15_act_q and binv_wayD_upd3_q; +p1_way_data_upd15_wayD <= p1_congr_cl15_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu15_wayD_upd(0) <= p1_way_data_upd15_wayD and p1_wren_q; +rel_bixu15_wayD_upd(1) <= p0_way_data_upd15_wayD and p0_wren_q; +p0_way_data_upd15_wayE <= p0_congr_cl15_act_q and binv_wayE_upd3_q; +p1_way_data_upd15_wayE <= p1_congr_cl15_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu15_wayE_upd(0) <= p1_way_data_upd15_wayE and p1_wren_q; +rel_bixu15_wayE_upd(1) <= p0_way_data_upd15_wayE and p0_wren_q; +p0_way_data_upd15_wayF <= p0_congr_cl15_act_q and binv_wayF_upd3_q; +p1_way_data_upd15_wayF <= p1_congr_cl15_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu15_wayF_upd(0) <= p1_way_data_upd15_wayF and p1_wren_q; +rel_bixu15_wayF_upd(1) <= p0_way_data_upd15_wayF and p0_wren_q; +p0_way_data_upd15_wayG <= p0_congr_cl15_act_q and binv_wayG_upd3_q; +p1_way_data_upd15_wayG <= p1_congr_cl15_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu15_wayG_upd(0) <= p1_way_data_upd15_wayG and p1_wren_q; +rel_bixu15_wayG_upd(1) <= p0_way_data_upd15_wayG and p0_wren_q; +p0_way_data_upd15_wayH <= p0_congr_cl15_act_q and binv_wayH_upd3_q; +p1_way_data_upd15_wayH <= p1_congr_cl15_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu15_wayH_upd(0) <= p1_way_data_upd15_wayH and p1_wren_q; +rel_bixu15_wayH_upd(1) <= p0_way_data_upd15_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl16_m <= (ex5_congr_cl_q = tconv(16,6)); +p1_congr_cl16_m <= (relu_s_congr_cl_q = tconv(16,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl16_act_d <= p0_congr_cl16_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl16_act_d <= p1_congr_cl16_m and rel_port_wren_q; +congr_cl16_act <= p0_congr_cl16_act_q or p1_congr_cl16_act_q or congr_cl_all_act_q; +p0_way_data_upd16_wayA <= p0_congr_cl16_act_q and binv_wayA_upd3_q; +p1_way_data_upd16_wayA <= p1_congr_cl16_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu16_wayA_upd(0) <= p1_way_data_upd16_wayA and p1_wren_q; +rel_bixu16_wayA_upd(1) <= p0_way_data_upd16_wayA and p0_wren_q; +p0_way_data_upd16_wayB <= p0_congr_cl16_act_q and binv_wayB_upd3_q; +p1_way_data_upd16_wayB <= p1_congr_cl16_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu16_wayB_upd(0) <= p1_way_data_upd16_wayB and p1_wren_q; +rel_bixu16_wayB_upd(1) <= p0_way_data_upd16_wayB and p0_wren_q; +p0_way_data_upd16_wayC <= p0_congr_cl16_act_q and binv_wayC_upd3_q; +p1_way_data_upd16_wayC <= p1_congr_cl16_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu16_wayC_upd(0) <= p1_way_data_upd16_wayC and p1_wren_q; +rel_bixu16_wayC_upd(1) <= p0_way_data_upd16_wayC and p0_wren_q; +p0_way_data_upd16_wayD <= p0_congr_cl16_act_q and binv_wayD_upd3_q; +p1_way_data_upd16_wayD <= p1_congr_cl16_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu16_wayD_upd(0) <= p1_way_data_upd16_wayD and p1_wren_q; +rel_bixu16_wayD_upd(1) <= p0_way_data_upd16_wayD and p0_wren_q; +p0_way_data_upd16_wayE <= p0_congr_cl16_act_q and binv_wayE_upd3_q; +p1_way_data_upd16_wayE <= p1_congr_cl16_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu16_wayE_upd(0) <= p1_way_data_upd16_wayE and p1_wren_q; +rel_bixu16_wayE_upd(1) <= p0_way_data_upd16_wayE and p0_wren_q; +p0_way_data_upd16_wayF <= p0_congr_cl16_act_q and binv_wayF_upd3_q; +p1_way_data_upd16_wayF <= p1_congr_cl16_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu16_wayF_upd(0) <= p1_way_data_upd16_wayF and p1_wren_q; +rel_bixu16_wayF_upd(1) <= p0_way_data_upd16_wayF and p0_wren_q; +p0_way_data_upd16_wayG <= p0_congr_cl16_act_q and binv_wayG_upd3_q; +p1_way_data_upd16_wayG <= p1_congr_cl16_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu16_wayG_upd(0) <= p1_way_data_upd16_wayG and p1_wren_q; +rel_bixu16_wayG_upd(1) <= p0_way_data_upd16_wayG and p0_wren_q; +p0_way_data_upd16_wayH <= p0_congr_cl16_act_q and binv_wayH_upd3_q; +p1_way_data_upd16_wayH <= p1_congr_cl16_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu16_wayH_upd(0) <= p1_way_data_upd16_wayH and p1_wren_q; +rel_bixu16_wayH_upd(1) <= p0_way_data_upd16_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl17_m <= (ex5_congr_cl_q = tconv(17,6)); +p1_congr_cl17_m <= (relu_s_congr_cl_q = tconv(17,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl17_act_d <= p0_congr_cl17_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl17_act_d <= p1_congr_cl17_m and rel_port_wren_q; +congr_cl17_act <= p0_congr_cl17_act_q or p1_congr_cl17_act_q or congr_cl_all_act_q; +p0_way_data_upd17_wayA <= p0_congr_cl17_act_q and binv_wayA_upd3_q; +p1_way_data_upd17_wayA <= p1_congr_cl17_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu17_wayA_upd(0) <= p1_way_data_upd17_wayA and p1_wren_q; +rel_bixu17_wayA_upd(1) <= p0_way_data_upd17_wayA and p0_wren_q; +p0_way_data_upd17_wayB <= p0_congr_cl17_act_q and binv_wayB_upd3_q; +p1_way_data_upd17_wayB <= p1_congr_cl17_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu17_wayB_upd(0) <= p1_way_data_upd17_wayB and p1_wren_q; +rel_bixu17_wayB_upd(1) <= p0_way_data_upd17_wayB and p0_wren_q; +p0_way_data_upd17_wayC <= p0_congr_cl17_act_q and binv_wayC_upd3_q; +p1_way_data_upd17_wayC <= p1_congr_cl17_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu17_wayC_upd(0) <= p1_way_data_upd17_wayC and p1_wren_q; +rel_bixu17_wayC_upd(1) <= p0_way_data_upd17_wayC and p0_wren_q; +p0_way_data_upd17_wayD <= p0_congr_cl17_act_q and binv_wayD_upd3_q; +p1_way_data_upd17_wayD <= p1_congr_cl17_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu17_wayD_upd(0) <= p1_way_data_upd17_wayD and p1_wren_q; +rel_bixu17_wayD_upd(1) <= p0_way_data_upd17_wayD and p0_wren_q; +p0_way_data_upd17_wayE <= p0_congr_cl17_act_q and binv_wayE_upd3_q; +p1_way_data_upd17_wayE <= p1_congr_cl17_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu17_wayE_upd(0) <= p1_way_data_upd17_wayE and p1_wren_q; +rel_bixu17_wayE_upd(1) <= p0_way_data_upd17_wayE and p0_wren_q; +p0_way_data_upd17_wayF <= p0_congr_cl17_act_q and binv_wayF_upd3_q; +p1_way_data_upd17_wayF <= p1_congr_cl17_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu17_wayF_upd(0) <= p1_way_data_upd17_wayF and p1_wren_q; +rel_bixu17_wayF_upd(1) <= p0_way_data_upd17_wayF and p0_wren_q; +p0_way_data_upd17_wayG <= p0_congr_cl17_act_q and binv_wayG_upd3_q; +p1_way_data_upd17_wayG <= p1_congr_cl17_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu17_wayG_upd(0) <= p1_way_data_upd17_wayG and p1_wren_q; +rel_bixu17_wayG_upd(1) <= p0_way_data_upd17_wayG and p0_wren_q; +p0_way_data_upd17_wayH <= p0_congr_cl17_act_q and binv_wayH_upd3_q; +p1_way_data_upd17_wayH <= p1_congr_cl17_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu17_wayH_upd(0) <= p1_way_data_upd17_wayH and p1_wren_q; +rel_bixu17_wayH_upd(1) <= p0_way_data_upd17_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl18_m <= (ex5_congr_cl_q = tconv(18,6)); +p1_congr_cl18_m <= (relu_s_congr_cl_q = tconv(18,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl18_act_d <= p0_congr_cl18_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl18_act_d <= p1_congr_cl18_m and rel_port_wren_q; +congr_cl18_act <= p0_congr_cl18_act_q or p1_congr_cl18_act_q or congr_cl_all_act_q; +p0_way_data_upd18_wayA <= p0_congr_cl18_act_q and binv_wayA_upd3_q; +p1_way_data_upd18_wayA <= p1_congr_cl18_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu18_wayA_upd(0) <= p1_way_data_upd18_wayA and p1_wren_q; +rel_bixu18_wayA_upd(1) <= p0_way_data_upd18_wayA and p0_wren_q; +p0_way_data_upd18_wayB <= p0_congr_cl18_act_q and binv_wayB_upd3_q; +p1_way_data_upd18_wayB <= p1_congr_cl18_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu18_wayB_upd(0) <= p1_way_data_upd18_wayB and p1_wren_q; +rel_bixu18_wayB_upd(1) <= p0_way_data_upd18_wayB and p0_wren_q; +p0_way_data_upd18_wayC <= p0_congr_cl18_act_q and binv_wayC_upd3_q; +p1_way_data_upd18_wayC <= p1_congr_cl18_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu18_wayC_upd(0) <= p1_way_data_upd18_wayC and p1_wren_q; +rel_bixu18_wayC_upd(1) <= p0_way_data_upd18_wayC and p0_wren_q; +p0_way_data_upd18_wayD <= p0_congr_cl18_act_q and binv_wayD_upd3_q; +p1_way_data_upd18_wayD <= p1_congr_cl18_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu18_wayD_upd(0) <= p1_way_data_upd18_wayD and p1_wren_q; +rel_bixu18_wayD_upd(1) <= p0_way_data_upd18_wayD and p0_wren_q; +p0_way_data_upd18_wayE <= p0_congr_cl18_act_q and binv_wayE_upd3_q; +p1_way_data_upd18_wayE <= p1_congr_cl18_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu18_wayE_upd(0) <= p1_way_data_upd18_wayE and p1_wren_q; +rel_bixu18_wayE_upd(1) <= p0_way_data_upd18_wayE and p0_wren_q; +p0_way_data_upd18_wayF <= p0_congr_cl18_act_q and binv_wayF_upd3_q; +p1_way_data_upd18_wayF <= p1_congr_cl18_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu18_wayF_upd(0) <= p1_way_data_upd18_wayF and p1_wren_q; +rel_bixu18_wayF_upd(1) <= p0_way_data_upd18_wayF and p0_wren_q; +p0_way_data_upd18_wayG <= p0_congr_cl18_act_q and binv_wayG_upd3_q; +p1_way_data_upd18_wayG <= p1_congr_cl18_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu18_wayG_upd(0) <= p1_way_data_upd18_wayG and p1_wren_q; +rel_bixu18_wayG_upd(1) <= p0_way_data_upd18_wayG and p0_wren_q; +p0_way_data_upd18_wayH <= p0_congr_cl18_act_q and binv_wayH_upd3_q; +p1_way_data_upd18_wayH <= p1_congr_cl18_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu18_wayH_upd(0) <= p1_way_data_upd18_wayH and p1_wren_q; +rel_bixu18_wayH_upd(1) <= p0_way_data_upd18_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl19_m <= (ex5_congr_cl_q = tconv(19,6)); +p1_congr_cl19_m <= (relu_s_congr_cl_q = tconv(19,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl19_act_d <= p0_congr_cl19_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl19_act_d <= p1_congr_cl19_m and rel_port_wren_q; +congr_cl19_act <= p0_congr_cl19_act_q or p1_congr_cl19_act_q or congr_cl_all_act_q; +p0_way_data_upd19_wayA <= p0_congr_cl19_act_q and binv_wayA_upd3_q; +p1_way_data_upd19_wayA <= p1_congr_cl19_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu19_wayA_upd(0) <= p1_way_data_upd19_wayA and p1_wren_q; +rel_bixu19_wayA_upd(1) <= p0_way_data_upd19_wayA and p0_wren_q; +p0_way_data_upd19_wayB <= p0_congr_cl19_act_q and binv_wayB_upd3_q; +p1_way_data_upd19_wayB <= p1_congr_cl19_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu19_wayB_upd(0) <= p1_way_data_upd19_wayB and p1_wren_q; +rel_bixu19_wayB_upd(1) <= p0_way_data_upd19_wayB and p0_wren_q; +p0_way_data_upd19_wayC <= p0_congr_cl19_act_q and binv_wayC_upd3_q; +p1_way_data_upd19_wayC <= p1_congr_cl19_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu19_wayC_upd(0) <= p1_way_data_upd19_wayC and p1_wren_q; +rel_bixu19_wayC_upd(1) <= p0_way_data_upd19_wayC and p0_wren_q; +p0_way_data_upd19_wayD <= p0_congr_cl19_act_q and binv_wayD_upd3_q; +p1_way_data_upd19_wayD <= p1_congr_cl19_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu19_wayD_upd(0) <= p1_way_data_upd19_wayD and p1_wren_q; +rel_bixu19_wayD_upd(1) <= p0_way_data_upd19_wayD and p0_wren_q; +p0_way_data_upd19_wayE <= p0_congr_cl19_act_q and binv_wayE_upd3_q; +p1_way_data_upd19_wayE <= p1_congr_cl19_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu19_wayE_upd(0) <= p1_way_data_upd19_wayE and p1_wren_q; +rel_bixu19_wayE_upd(1) <= p0_way_data_upd19_wayE and p0_wren_q; +p0_way_data_upd19_wayF <= p0_congr_cl19_act_q and binv_wayF_upd3_q; +p1_way_data_upd19_wayF <= p1_congr_cl19_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu19_wayF_upd(0) <= p1_way_data_upd19_wayF and p1_wren_q; +rel_bixu19_wayF_upd(1) <= p0_way_data_upd19_wayF and p0_wren_q; +p0_way_data_upd19_wayG <= p0_congr_cl19_act_q and binv_wayG_upd3_q; +p1_way_data_upd19_wayG <= p1_congr_cl19_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu19_wayG_upd(0) <= p1_way_data_upd19_wayG and p1_wren_q; +rel_bixu19_wayG_upd(1) <= p0_way_data_upd19_wayG and p0_wren_q; +p0_way_data_upd19_wayH <= p0_congr_cl19_act_q and binv_wayH_upd3_q; +p1_way_data_upd19_wayH <= p1_congr_cl19_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu19_wayH_upd(0) <= p1_way_data_upd19_wayH and p1_wren_q; +rel_bixu19_wayH_upd(1) <= p0_way_data_upd19_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl20_m <= (ex5_congr_cl_q = tconv(20,6)); +p1_congr_cl20_m <= (relu_s_congr_cl_q = tconv(20,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl20_act_d <= p0_congr_cl20_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl20_act_d <= p1_congr_cl20_m and rel_port_wren_q; +congr_cl20_act <= p0_congr_cl20_act_q or p1_congr_cl20_act_q or congr_cl_all_act_q; +p0_way_data_upd20_wayA <= p0_congr_cl20_act_q and binv_wayA_upd3_q; +p1_way_data_upd20_wayA <= p1_congr_cl20_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu20_wayA_upd(0) <= p1_way_data_upd20_wayA and p1_wren_q; +rel_bixu20_wayA_upd(1) <= p0_way_data_upd20_wayA and p0_wren_q; +p0_way_data_upd20_wayB <= p0_congr_cl20_act_q and binv_wayB_upd3_q; +p1_way_data_upd20_wayB <= p1_congr_cl20_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu20_wayB_upd(0) <= p1_way_data_upd20_wayB and p1_wren_q; +rel_bixu20_wayB_upd(1) <= p0_way_data_upd20_wayB and p0_wren_q; +p0_way_data_upd20_wayC <= p0_congr_cl20_act_q and binv_wayC_upd3_q; +p1_way_data_upd20_wayC <= p1_congr_cl20_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu20_wayC_upd(0) <= p1_way_data_upd20_wayC and p1_wren_q; +rel_bixu20_wayC_upd(1) <= p0_way_data_upd20_wayC and p0_wren_q; +p0_way_data_upd20_wayD <= p0_congr_cl20_act_q and binv_wayD_upd3_q; +p1_way_data_upd20_wayD <= p1_congr_cl20_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu20_wayD_upd(0) <= p1_way_data_upd20_wayD and p1_wren_q; +rel_bixu20_wayD_upd(1) <= p0_way_data_upd20_wayD and p0_wren_q; +p0_way_data_upd20_wayE <= p0_congr_cl20_act_q and binv_wayE_upd3_q; +p1_way_data_upd20_wayE <= p1_congr_cl20_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu20_wayE_upd(0) <= p1_way_data_upd20_wayE and p1_wren_q; +rel_bixu20_wayE_upd(1) <= p0_way_data_upd20_wayE and p0_wren_q; +p0_way_data_upd20_wayF <= p0_congr_cl20_act_q and binv_wayF_upd3_q; +p1_way_data_upd20_wayF <= p1_congr_cl20_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu20_wayF_upd(0) <= p1_way_data_upd20_wayF and p1_wren_q; +rel_bixu20_wayF_upd(1) <= p0_way_data_upd20_wayF and p0_wren_q; +p0_way_data_upd20_wayG <= p0_congr_cl20_act_q and binv_wayG_upd3_q; +p1_way_data_upd20_wayG <= p1_congr_cl20_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu20_wayG_upd(0) <= p1_way_data_upd20_wayG and p1_wren_q; +rel_bixu20_wayG_upd(1) <= p0_way_data_upd20_wayG and p0_wren_q; +p0_way_data_upd20_wayH <= p0_congr_cl20_act_q and binv_wayH_upd3_q; +p1_way_data_upd20_wayH <= p1_congr_cl20_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu20_wayH_upd(0) <= p1_way_data_upd20_wayH and p1_wren_q; +rel_bixu20_wayH_upd(1) <= p0_way_data_upd20_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl21_m <= (ex5_congr_cl_q = tconv(21,6)); +p1_congr_cl21_m <= (relu_s_congr_cl_q = tconv(21,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl21_act_d <= p0_congr_cl21_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl21_act_d <= p1_congr_cl21_m and rel_port_wren_q; +congr_cl21_act <= p0_congr_cl21_act_q or p1_congr_cl21_act_q or congr_cl_all_act_q; +p0_way_data_upd21_wayA <= p0_congr_cl21_act_q and binv_wayA_upd3_q; +p1_way_data_upd21_wayA <= p1_congr_cl21_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu21_wayA_upd(0) <= p1_way_data_upd21_wayA and p1_wren_q; +rel_bixu21_wayA_upd(1) <= p0_way_data_upd21_wayA and p0_wren_q; +p0_way_data_upd21_wayB <= p0_congr_cl21_act_q and binv_wayB_upd3_q; +p1_way_data_upd21_wayB <= p1_congr_cl21_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu21_wayB_upd(0) <= p1_way_data_upd21_wayB and p1_wren_q; +rel_bixu21_wayB_upd(1) <= p0_way_data_upd21_wayB and p0_wren_q; +p0_way_data_upd21_wayC <= p0_congr_cl21_act_q and binv_wayC_upd3_q; +p1_way_data_upd21_wayC <= p1_congr_cl21_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu21_wayC_upd(0) <= p1_way_data_upd21_wayC and p1_wren_q; +rel_bixu21_wayC_upd(1) <= p0_way_data_upd21_wayC and p0_wren_q; +p0_way_data_upd21_wayD <= p0_congr_cl21_act_q and binv_wayD_upd3_q; +p1_way_data_upd21_wayD <= p1_congr_cl21_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu21_wayD_upd(0) <= p1_way_data_upd21_wayD and p1_wren_q; +rel_bixu21_wayD_upd(1) <= p0_way_data_upd21_wayD and p0_wren_q; +p0_way_data_upd21_wayE <= p0_congr_cl21_act_q and binv_wayE_upd3_q; +p1_way_data_upd21_wayE <= p1_congr_cl21_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu21_wayE_upd(0) <= p1_way_data_upd21_wayE and p1_wren_q; +rel_bixu21_wayE_upd(1) <= p0_way_data_upd21_wayE and p0_wren_q; +p0_way_data_upd21_wayF <= p0_congr_cl21_act_q and binv_wayF_upd3_q; +p1_way_data_upd21_wayF <= p1_congr_cl21_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu21_wayF_upd(0) <= p1_way_data_upd21_wayF and p1_wren_q; +rel_bixu21_wayF_upd(1) <= p0_way_data_upd21_wayF and p0_wren_q; +p0_way_data_upd21_wayG <= p0_congr_cl21_act_q and binv_wayG_upd3_q; +p1_way_data_upd21_wayG <= p1_congr_cl21_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu21_wayG_upd(0) <= p1_way_data_upd21_wayG and p1_wren_q; +rel_bixu21_wayG_upd(1) <= p0_way_data_upd21_wayG and p0_wren_q; +p0_way_data_upd21_wayH <= p0_congr_cl21_act_q and binv_wayH_upd3_q; +p1_way_data_upd21_wayH <= p1_congr_cl21_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu21_wayH_upd(0) <= p1_way_data_upd21_wayH and p1_wren_q; +rel_bixu21_wayH_upd(1) <= p0_way_data_upd21_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl22_m <= (ex5_congr_cl_q = tconv(22,6)); +p1_congr_cl22_m <= (relu_s_congr_cl_q = tconv(22,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl22_act_d <= p0_congr_cl22_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl22_act_d <= p1_congr_cl22_m and rel_port_wren_q; +congr_cl22_act <= p0_congr_cl22_act_q or p1_congr_cl22_act_q or congr_cl_all_act_q; +p0_way_data_upd22_wayA <= p0_congr_cl22_act_q and binv_wayA_upd3_q; +p1_way_data_upd22_wayA <= p1_congr_cl22_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu22_wayA_upd(0) <= p1_way_data_upd22_wayA and p1_wren_q; +rel_bixu22_wayA_upd(1) <= p0_way_data_upd22_wayA and p0_wren_q; +p0_way_data_upd22_wayB <= p0_congr_cl22_act_q and binv_wayB_upd3_q; +p1_way_data_upd22_wayB <= p1_congr_cl22_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu22_wayB_upd(0) <= p1_way_data_upd22_wayB and p1_wren_q; +rel_bixu22_wayB_upd(1) <= p0_way_data_upd22_wayB and p0_wren_q; +p0_way_data_upd22_wayC <= p0_congr_cl22_act_q and binv_wayC_upd3_q; +p1_way_data_upd22_wayC <= p1_congr_cl22_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu22_wayC_upd(0) <= p1_way_data_upd22_wayC and p1_wren_q; +rel_bixu22_wayC_upd(1) <= p0_way_data_upd22_wayC and p0_wren_q; +p0_way_data_upd22_wayD <= p0_congr_cl22_act_q and binv_wayD_upd3_q; +p1_way_data_upd22_wayD <= p1_congr_cl22_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu22_wayD_upd(0) <= p1_way_data_upd22_wayD and p1_wren_q; +rel_bixu22_wayD_upd(1) <= p0_way_data_upd22_wayD and p0_wren_q; +p0_way_data_upd22_wayE <= p0_congr_cl22_act_q and binv_wayE_upd3_q; +p1_way_data_upd22_wayE <= p1_congr_cl22_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu22_wayE_upd(0) <= p1_way_data_upd22_wayE and p1_wren_q; +rel_bixu22_wayE_upd(1) <= p0_way_data_upd22_wayE and p0_wren_q; +p0_way_data_upd22_wayF <= p0_congr_cl22_act_q and binv_wayF_upd3_q; +p1_way_data_upd22_wayF <= p1_congr_cl22_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu22_wayF_upd(0) <= p1_way_data_upd22_wayF and p1_wren_q; +rel_bixu22_wayF_upd(1) <= p0_way_data_upd22_wayF and p0_wren_q; +p0_way_data_upd22_wayG <= p0_congr_cl22_act_q and binv_wayG_upd3_q; +p1_way_data_upd22_wayG <= p1_congr_cl22_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu22_wayG_upd(0) <= p1_way_data_upd22_wayG and p1_wren_q; +rel_bixu22_wayG_upd(1) <= p0_way_data_upd22_wayG and p0_wren_q; +p0_way_data_upd22_wayH <= p0_congr_cl22_act_q and binv_wayH_upd3_q; +p1_way_data_upd22_wayH <= p1_congr_cl22_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu22_wayH_upd(0) <= p1_way_data_upd22_wayH and p1_wren_q; +rel_bixu22_wayH_upd(1) <= p0_way_data_upd22_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl23_m <= (ex5_congr_cl_q = tconv(23,6)); +p1_congr_cl23_m <= (relu_s_congr_cl_q = tconv(23,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl23_act_d <= p0_congr_cl23_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl23_act_d <= p1_congr_cl23_m and rel_port_wren_q; +congr_cl23_act <= p0_congr_cl23_act_q or p1_congr_cl23_act_q or congr_cl_all_act_q; +p0_way_data_upd23_wayA <= p0_congr_cl23_act_q and binv_wayA_upd3_q; +p1_way_data_upd23_wayA <= p1_congr_cl23_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu23_wayA_upd(0) <= p1_way_data_upd23_wayA and p1_wren_q; +rel_bixu23_wayA_upd(1) <= p0_way_data_upd23_wayA and p0_wren_q; +p0_way_data_upd23_wayB <= p0_congr_cl23_act_q and binv_wayB_upd3_q; +p1_way_data_upd23_wayB <= p1_congr_cl23_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu23_wayB_upd(0) <= p1_way_data_upd23_wayB and p1_wren_q; +rel_bixu23_wayB_upd(1) <= p0_way_data_upd23_wayB and p0_wren_q; +p0_way_data_upd23_wayC <= p0_congr_cl23_act_q and binv_wayC_upd3_q; +p1_way_data_upd23_wayC <= p1_congr_cl23_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu23_wayC_upd(0) <= p1_way_data_upd23_wayC and p1_wren_q; +rel_bixu23_wayC_upd(1) <= p0_way_data_upd23_wayC and p0_wren_q; +p0_way_data_upd23_wayD <= p0_congr_cl23_act_q and binv_wayD_upd3_q; +p1_way_data_upd23_wayD <= p1_congr_cl23_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu23_wayD_upd(0) <= p1_way_data_upd23_wayD and p1_wren_q; +rel_bixu23_wayD_upd(1) <= p0_way_data_upd23_wayD and p0_wren_q; +p0_way_data_upd23_wayE <= p0_congr_cl23_act_q and binv_wayE_upd3_q; +p1_way_data_upd23_wayE <= p1_congr_cl23_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu23_wayE_upd(0) <= p1_way_data_upd23_wayE and p1_wren_q; +rel_bixu23_wayE_upd(1) <= p0_way_data_upd23_wayE and p0_wren_q; +p0_way_data_upd23_wayF <= p0_congr_cl23_act_q and binv_wayF_upd3_q; +p1_way_data_upd23_wayF <= p1_congr_cl23_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu23_wayF_upd(0) <= p1_way_data_upd23_wayF and p1_wren_q; +rel_bixu23_wayF_upd(1) <= p0_way_data_upd23_wayF and p0_wren_q; +p0_way_data_upd23_wayG <= p0_congr_cl23_act_q and binv_wayG_upd3_q; +p1_way_data_upd23_wayG <= p1_congr_cl23_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu23_wayG_upd(0) <= p1_way_data_upd23_wayG and p1_wren_q; +rel_bixu23_wayG_upd(1) <= p0_way_data_upd23_wayG and p0_wren_q; +p0_way_data_upd23_wayH <= p0_congr_cl23_act_q and binv_wayH_upd3_q; +p1_way_data_upd23_wayH <= p1_congr_cl23_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu23_wayH_upd(0) <= p1_way_data_upd23_wayH and p1_wren_q; +rel_bixu23_wayH_upd(1) <= p0_way_data_upd23_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl24_m <= (ex5_congr_cl_q = tconv(24,6)); +p1_congr_cl24_m <= (relu_s_congr_cl_q = tconv(24,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl24_act_d <= p0_congr_cl24_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl24_act_d <= p1_congr_cl24_m and rel_port_wren_q; +congr_cl24_act <= p0_congr_cl24_act_q or p1_congr_cl24_act_q or congr_cl_all_act_q; +p0_way_data_upd24_wayA <= p0_congr_cl24_act_q and binv_wayA_upd3_q; +p1_way_data_upd24_wayA <= p1_congr_cl24_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu24_wayA_upd(0) <= p1_way_data_upd24_wayA and p1_wren_q; +rel_bixu24_wayA_upd(1) <= p0_way_data_upd24_wayA and p0_wren_q; +p0_way_data_upd24_wayB <= p0_congr_cl24_act_q and binv_wayB_upd3_q; +p1_way_data_upd24_wayB <= p1_congr_cl24_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu24_wayB_upd(0) <= p1_way_data_upd24_wayB and p1_wren_q; +rel_bixu24_wayB_upd(1) <= p0_way_data_upd24_wayB and p0_wren_q; +p0_way_data_upd24_wayC <= p0_congr_cl24_act_q and binv_wayC_upd3_q; +p1_way_data_upd24_wayC <= p1_congr_cl24_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu24_wayC_upd(0) <= p1_way_data_upd24_wayC and p1_wren_q; +rel_bixu24_wayC_upd(1) <= p0_way_data_upd24_wayC and p0_wren_q; +p0_way_data_upd24_wayD <= p0_congr_cl24_act_q and binv_wayD_upd3_q; +p1_way_data_upd24_wayD <= p1_congr_cl24_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu24_wayD_upd(0) <= p1_way_data_upd24_wayD and p1_wren_q; +rel_bixu24_wayD_upd(1) <= p0_way_data_upd24_wayD and p0_wren_q; +p0_way_data_upd24_wayE <= p0_congr_cl24_act_q and binv_wayE_upd3_q; +p1_way_data_upd24_wayE <= p1_congr_cl24_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu24_wayE_upd(0) <= p1_way_data_upd24_wayE and p1_wren_q; +rel_bixu24_wayE_upd(1) <= p0_way_data_upd24_wayE and p0_wren_q; +p0_way_data_upd24_wayF <= p0_congr_cl24_act_q and binv_wayF_upd3_q; +p1_way_data_upd24_wayF <= p1_congr_cl24_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu24_wayF_upd(0) <= p1_way_data_upd24_wayF and p1_wren_q; +rel_bixu24_wayF_upd(1) <= p0_way_data_upd24_wayF and p0_wren_q; +p0_way_data_upd24_wayG <= p0_congr_cl24_act_q and binv_wayG_upd3_q; +p1_way_data_upd24_wayG <= p1_congr_cl24_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu24_wayG_upd(0) <= p1_way_data_upd24_wayG and p1_wren_q; +rel_bixu24_wayG_upd(1) <= p0_way_data_upd24_wayG and p0_wren_q; +p0_way_data_upd24_wayH <= p0_congr_cl24_act_q and binv_wayH_upd3_q; +p1_way_data_upd24_wayH <= p1_congr_cl24_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu24_wayH_upd(0) <= p1_way_data_upd24_wayH and p1_wren_q; +rel_bixu24_wayH_upd(1) <= p0_way_data_upd24_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl25_m <= (ex5_congr_cl_q = tconv(25,6)); +p1_congr_cl25_m <= (relu_s_congr_cl_q = tconv(25,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl25_act_d <= p0_congr_cl25_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl25_act_d <= p1_congr_cl25_m and rel_port_wren_q; +congr_cl25_act <= p0_congr_cl25_act_q or p1_congr_cl25_act_q or congr_cl_all_act_q; +p0_way_data_upd25_wayA <= p0_congr_cl25_act_q and binv_wayA_upd3_q; +p1_way_data_upd25_wayA <= p1_congr_cl25_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu25_wayA_upd(0) <= p1_way_data_upd25_wayA and p1_wren_q; +rel_bixu25_wayA_upd(1) <= p0_way_data_upd25_wayA and p0_wren_q; +p0_way_data_upd25_wayB <= p0_congr_cl25_act_q and binv_wayB_upd3_q; +p1_way_data_upd25_wayB <= p1_congr_cl25_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu25_wayB_upd(0) <= p1_way_data_upd25_wayB and p1_wren_q; +rel_bixu25_wayB_upd(1) <= p0_way_data_upd25_wayB and p0_wren_q; +p0_way_data_upd25_wayC <= p0_congr_cl25_act_q and binv_wayC_upd3_q; +p1_way_data_upd25_wayC <= p1_congr_cl25_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu25_wayC_upd(0) <= p1_way_data_upd25_wayC and p1_wren_q; +rel_bixu25_wayC_upd(1) <= p0_way_data_upd25_wayC and p0_wren_q; +p0_way_data_upd25_wayD <= p0_congr_cl25_act_q and binv_wayD_upd3_q; +p1_way_data_upd25_wayD <= p1_congr_cl25_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu25_wayD_upd(0) <= p1_way_data_upd25_wayD and p1_wren_q; +rel_bixu25_wayD_upd(1) <= p0_way_data_upd25_wayD and p0_wren_q; +p0_way_data_upd25_wayE <= p0_congr_cl25_act_q and binv_wayE_upd3_q; +p1_way_data_upd25_wayE <= p1_congr_cl25_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu25_wayE_upd(0) <= p1_way_data_upd25_wayE and p1_wren_q; +rel_bixu25_wayE_upd(1) <= p0_way_data_upd25_wayE and p0_wren_q; +p0_way_data_upd25_wayF <= p0_congr_cl25_act_q and binv_wayF_upd3_q; +p1_way_data_upd25_wayF <= p1_congr_cl25_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu25_wayF_upd(0) <= p1_way_data_upd25_wayF and p1_wren_q; +rel_bixu25_wayF_upd(1) <= p0_way_data_upd25_wayF and p0_wren_q; +p0_way_data_upd25_wayG <= p0_congr_cl25_act_q and binv_wayG_upd3_q; +p1_way_data_upd25_wayG <= p1_congr_cl25_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu25_wayG_upd(0) <= p1_way_data_upd25_wayG and p1_wren_q; +rel_bixu25_wayG_upd(1) <= p0_way_data_upd25_wayG and p0_wren_q; +p0_way_data_upd25_wayH <= p0_congr_cl25_act_q and binv_wayH_upd3_q; +p1_way_data_upd25_wayH <= p1_congr_cl25_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu25_wayH_upd(0) <= p1_way_data_upd25_wayH and p1_wren_q; +rel_bixu25_wayH_upd(1) <= p0_way_data_upd25_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl26_m <= (ex5_congr_cl_q = tconv(26,6)); +p1_congr_cl26_m <= (relu_s_congr_cl_q = tconv(26,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl26_act_d <= p0_congr_cl26_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl26_act_d <= p1_congr_cl26_m and rel_port_wren_q; +congr_cl26_act <= p0_congr_cl26_act_q or p1_congr_cl26_act_q or congr_cl_all_act_q; +p0_way_data_upd26_wayA <= p0_congr_cl26_act_q and binv_wayA_upd3_q; +p1_way_data_upd26_wayA <= p1_congr_cl26_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu26_wayA_upd(0) <= p1_way_data_upd26_wayA and p1_wren_q; +rel_bixu26_wayA_upd(1) <= p0_way_data_upd26_wayA and p0_wren_q; +p0_way_data_upd26_wayB <= p0_congr_cl26_act_q and binv_wayB_upd3_q; +p1_way_data_upd26_wayB <= p1_congr_cl26_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu26_wayB_upd(0) <= p1_way_data_upd26_wayB and p1_wren_q; +rel_bixu26_wayB_upd(1) <= p0_way_data_upd26_wayB and p0_wren_q; +p0_way_data_upd26_wayC <= p0_congr_cl26_act_q and binv_wayC_upd3_q; +p1_way_data_upd26_wayC <= p1_congr_cl26_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu26_wayC_upd(0) <= p1_way_data_upd26_wayC and p1_wren_q; +rel_bixu26_wayC_upd(1) <= p0_way_data_upd26_wayC and p0_wren_q; +p0_way_data_upd26_wayD <= p0_congr_cl26_act_q and binv_wayD_upd3_q; +p1_way_data_upd26_wayD <= p1_congr_cl26_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu26_wayD_upd(0) <= p1_way_data_upd26_wayD and p1_wren_q; +rel_bixu26_wayD_upd(1) <= p0_way_data_upd26_wayD and p0_wren_q; +p0_way_data_upd26_wayE <= p0_congr_cl26_act_q and binv_wayE_upd3_q; +p1_way_data_upd26_wayE <= p1_congr_cl26_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu26_wayE_upd(0) <= p1_way_data_upd26_wayE and p1_wren_q; +rel_bixu26_wayE_upd(1) <= p0_way_data_upd26_wayE and p0_wren_q; +p0_way_data_upd26_wayF <= p0_congr_cl26_act_q and binv_wayF_upd3_q; +p1_way_data_upd26_wayF <= p1_congr_cl26_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu26_wayF_upd(0) <= p1_way_data_upd26_wayF and p1_wren_q; +rel_bixu26_wayF_upd(1) <= p0_way_data_upd26_wayF and p0_wren_q; +p0_way_data_upd26_wayG <= p0_congr_cl26_act_q and binv_wayG_upd3_q; +p1_way_data_upd26_wayG <= p1_congr_cl26_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu26_wayG_upd(0) <= p1_way_data_upd26_wayG and p1_wren_q; +rel_bixu26_wayG_upd(1) <= p0_way_data_upd26_wayG and p0_wren_q; +p0_way_data_upd26_wayH <= p0_congr_cl26_act_q and binv_wayH_upd3_q; +p1_way_data_upd26_wayH <= p1_congr_cl26_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu26_wayH_upd(0) <= p1_way_data_upd26_wayH and p1_wren_q; +rel_bixu26_wayH_upd(1) <= p0_way_data_upd26_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl27_m <= (ex5_congr_cl_q = tconv(27,6)); +p1_congr_cl27_m <= (relu_s_congr_cl_q = tconv(27,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl27_act_d <= p0_congr_cl27_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl27_act_d <= p1_congr_cl27_m and rel_port_wren_q; +congr_cl27_act <= p0_congr_cl27_act_q or p1_congr_cl27_act_q or congr_cl_all_act_q; +p0_way_data_upd27_wayA <= p0_congr_cl27_act_q and binv_wayA_upd3_q; +p1_way_data_upd27_wayA <= p1_congr_cl27_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu27_wayA_upd(0) <= p1_way_data_upd27_wayA and p1_wren_q; +rel_bixu27_wayA_upd(1) <= p0_way_data_upd27_wayA and p0_wren_q; +p0_way_data_upd27_wayB <= p0_congr_cl27_act_q and binv_wayB_upd3_q; +p1_way_data_upd27_wayB <= p1_congr_cl27_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu27_wayB_upd(0) <= p1_way_data_upd27_wayB and p1_wren_q; +rel_bixu27_wayB_upd(1) <= p0_way_data_upd27_wayB and p0_wren_q; +p0_way_data_upd27_wayC <= p0_congr_cl27_act_q and binv_wayC_upd3_q; +p1_way_data_upd27_wayC <= p1_congr_cl27_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu27_wayC_upd(0) <= p1_way_data_upd27_wayC and p1_wren_q; +rel_bixu27_wayC_upd(1) <= p0_way_data_upd27_wayC and p0_wren_q; +p0_way_data_upd27_wayD <= p0_congr_cl27_act_q and binv_wayD_upd3_q; +p1_way_data_upd27_wayD <= p1_congr_cl27_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu27_wayD_upd(0) <= p1_way_data_upd27_wayD and p1_wren_q; +rel_bixu27_wayD_upd(1) <= p0_way_data_upd27_wayD and p0_wren_q; +p0_way_data_upd27_wayE <= p0_congr_cl27_act_q and binv_wayE_upd3_q; +p1_way_data_upd27_wayE <= p1_congr_cl27_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu27_wayE_upd(0) <= p1_way_data_upd27_wayE and p1_wren_q; +rel_bixu27_wayE_upd(1) <= p0_way_data_upd27_wayE and p0_wren_q; +p0_way_data_upd27_wayF <= p0_congr_cl27_act_q and binv_wayF_upd3_q; +p1_way_data_upd27_wayF <= p1_congr_cl27_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu27_wayF_upd(0) <= p1_way_data_upd27_wayF and p1_wren_q; +rel_bixu27_wayF_upd(1) <= p0_way_data_upd27_wayF and p0_wren_q; +p0_way_data_upd27_wayG <= p0_congr_cl27_act_q and binv_wayG_upd3_q; +p1_way_data_upd27_wayG <= p1_congr_cl27_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu27_wayG_upd(0) <= p1_way_data_upd27_wayG and p1_wren_q; +rel_bixu27_wayG_upd(1) <= p0_way_data_upd27_wayG and p0_wren_q; +p0_way_data_upd27_wayH <= p0_congr_cl27_act_q and binv_wayH_upd3_q; +p1_way_data_upd27_wayH <= p1_congr_cl27_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu27_wayH_upd(0) <= p1_way_data_upd27_wayH and p1_wren_q; +rel_bixu27_wayH_upd(1) <= p0_way_data_upd27_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl28_m <= (ex5_congr_cl_q = tconv(28,6)); +p1_congr_cl28_m <= (relu_s_congr_cl_q = tconv(28,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl28_act_d <= p0_congr_cl28_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl28_act_d <= p1_congr_cl28_m and rel_port_wren_q; +congr_cl28_act <= p0_congr_cl28_act_q or p1_congr_cl28_act_q or congr_cl_all_act_q; +p0_way_data_upd28_wayA <= p0_congr_cl28_act_q and binv_wayA_upd3_q; +p1_way_data_upd28_wayA <= p1_congr_cl28_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu28_wayA_upd(0) <= p1_way_data_upd28_wayA and p1_wren_q; +rel_bixu28_wayA_upd(1) <= p0_way_data_upd28_wayA and p0_wren_q; +p0_way_data_upd28_wayB <= p0_congr_cl28_act_q and binv_wayB_upd3_q; +p1_way_data_upd28_wayB <= p1_congr_cl28_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu28_wayB_upd(0) <= p1_way_data_upd28_wayB and p1_wren_q; +rel_bixu28_wayB_upd(1) <= p0_way_data_upd28_wayB and p0_wren_q; +p0_way_data_upd28_wayC <= p0_congr_cl28_act_q and binv_wayC_upd3_q; +p1_way_data_upd28_wayC <= p1_congr_cl28_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu28_wayC_upd(0) <= p1_way_data_upd28_wayC and p1_wren_q; +rel_bixu28_wayC_upd(1) <= p0_way_data_upd28_wayC and p0_wren_q; +p0_way_data_upd28_wayD <= p0_congr_cl28_act_q and binv_wayD_upd3_q; +p1_way_data_upd28_wayD <= p1_congr_cl28_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu28_wayD_upd(0) <= p1_way_data_upd28_wayD and p1_wren_q; +rel_bixu28_wayD_upd(1) <= p0_way_data_upd28_wayD and p0_wren_q; +p0_way_data_upd28_wayE <= p0_congr_cl28_act_q and binv_wayE_upd3_q; +p1_way_data_upd28_wayE <= p1_congr_cl28_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu28_wayE_upd(0) <= p1_way_data_upd28_wayE and p1_wren_q; +rel_bixu28_wayE_upd(1) <= p0_way_data_upd28_wayE and p0_wren_q; +p0_way_data_upd28_wayF <= p0_congr_cl28_act_q and binv_wayF_upd3_q; +p1_way_data_upd28_wayF <= p1_congr_cl28_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu28_wayF_upd(0) <= p1_way_data_upd28_wayF and p1_wren_q; +rel_bixu28_wayF_upd(1) <= p0_way_data_upd28_wayF and p0_wren_q; +p0_way_data_upd28_wayG <= p0_congr_cl28_act_q and binv_wayG_upd3_q; +p1_way_data_upd28_wayG <= p1_congr_cl28_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu28_wayG_upd(0) <= p1_way_data_upd28_wayG and p1_wren_q; +rel_bixu28_wayG_upd(1) <= p0_way_data_upd28_wayG and p0_wren_q; +p0_way_data_upd28_wayH <= p0_congr_cl28_act_q and binv_wayH_upd3_q; +p1_way_data_upd28_wayH <= p1_congr_cl28_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu28_wayH_upd(0) <= p1_way_data_upd28_wayH and p1_wren_q; +rel_bixu28_wayH_upd(1) <= p0_way_data_upd28_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl29_m <= (ex5_congr_cl_q = tconv(29,6)); +p1_congr_cl29_m <= (relu_s_congr_cl_q = tconv(29,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl29_act_d <= p0_congr_cl29_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl29_act_d <= p1_congr_cl29_m and rel_port_wren_q; +congr_cl29_act <= p0_congr_cl29_act_q or p1_congr_cl29_act_q or congr_cl_all_act_q; +p0_way_data_upd29_wayA <= p0_congr_cl29_act_q and binv_wayA_upd3_q; +p1_way_data_upd29_wayA <= p1_congr_cl29_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu29_wayA_upd(0) <= p1_way_data_upd29_wayA and p1_wren_q; +rel_bixu29_wayA_upd(1) <= p0_way_data_upd29_wayA and p0_wren_q; +p0_way_data_upd29_wayB <= p0_congr_cl29_act_q and binv_wayB_upd3_q; +p1_way_data_upd29_wayB <= p1_congr_cl29_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu29_wayB_upd(0) <= p1_way_data_upd29_wayB and p1_wren_q; +rel_bixu29_wayB_upd(1) <= p0_way_data_upd29_wayB and p0_wren_q; +p0_way_data_upd29_wayC <= p0_congr_cl29_act_q and binv_wayC_upd3_q; +p1_way_data_upd29_wayC <= p1_congr_cl29_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu29_wayC_upd(0) <= p1_way_data_upd29_wayC and p1_wren_q; +rel_bixu29_wayC_upd(1) <= p0_way_data_upd29_wayC and p0_wren_q; +p0_way_data_upd29_wayD <= p0_congr_cl29_act_q and binv_wayD_upd3_q; +p1_way_data_upd29_wayD <= p1_congr_cl29_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu29_wayD_upd(0) <= p1_way_data_upd29_wayD and p1_wren_q; +rel_bixu29_wayD_upd(1) <= p0_way_data_upd29_wayD and p0_wren_q; +p0_way_data_upd29_wayE <= p0_congr_cl29_act_q and binv_wayE_upd3_q; +p1_way_data_upd29_wayE <= p1_congr_cl29_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu29_wayE_upd(0) <= p1_way_data_upd29_wayE and p1_wren_q; +rel_bixu29_wayE_upd(1) <= p0_way_data_upd29_wayE and p0_wren_q; +p0_way_data_upd29_wayF <= p0_congr_cl29_act_q and binv_wayF_upd3_q; +p1_way_data_upd29_wayF <= p1_congr_cl29_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu29_wayF_upd(0) <= p1_way_data_upd29_wayF and p1_wren_q; +rel_bixu29_wayF_upd(1) <= p0_way_data_upd29_wayF and p0_wren_q; +p0_way_data_upd29_wayG <= p0_congr_cl29_act_q and binv_wayG_upd3_q; +p1_way_data_upd29_wayG <= p1_congr_cl29_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu29_wayG_upd(0) <= p1_way_data_upd29_wayG and p1_wren_q; +rel_bixu29_wayG_upd(1) <= p0_way_data_upd29_wayG and p0_wren_q; +p0_way_data_upd29_wayH <= p0_congr_cl29_act_q and binv_wayH_upd3_q; +p1_way_data_upd29_wayH <= p1_congr_cl29_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu29_wayH_upd(0) <= p1_way_data_upd29_wayH and p1_wren_q; +rel_bixu29_wayH_upd(1) <= p0_way_data_upd29_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl30_m <= (ex5_congr_cl_q = tconv(30,6)); +p1_congr_cl30_m <= (relu_s_congr_cl_q = tconv(30,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl30_act_d <= p0_congr_cl30_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl30_act_d <= p1_congr_cl30_m and rel_port_wren_q; +congr_cl30_act <= p0_congr_cl30_act_q or p1_congr_cl30_act_q or congr_cl_all_act_q; +p0_way_data_upd30_wayA <= p0_congr_cl30_act_q and binv_wayA_upd3_q; +p1_way_data_upd30_wayA <= p1_congr_cl30_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu30_wayA_upd(0) <= p1_way_data_upd30_wayA and p1_wren_q; +rel_bixu30_wayA_upd(1) <= p0_way_data_upd30_wayA and p0_wren_q; +p0_way_data_upd30_wayB <= p0_congr_cl30_act_q and binv_wayB_upd3_q; +p1_way_data_upd30_wayB <= p1_congr_cl30_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu30_wayB_upd(0) <= p1_way_data_upd30_wayB and p1_wren_q; +rel_bixu30_wayB_upd(1) <= p0_way_data_upd30_wayB and p0_wren_q; +p0_way_data_upd30_wayC <= p0_congr_cl30_act_q and binv_wayC_upd3_q; +p1_way_data_upd30_wayC <= p1_congr_cl30_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu30_wayC_upd(0) <= p1_way_data_upd30_wayC and p1_wren_q; +rel_bixu30_wayC_upd(1) <= p0_way_data_upd30_wayC and p0_wren_q; +p0_way_data_upd30_wayD <= p0_congr_cl30_act_q and binv_wayD_upd3_q; +p1_way_data_upd30_wayD <= p1_congr_cl30_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu30_wayD_upd(0) <= p1_way_data_upd30_wayD and p1_wren_q; +rel_bixu30_wayD_upd(1) <= p0_way_data_upd30_wayD and p0_wren_q; +p0_way_data_upd30_wayE <= p0_congr_cl30_act_q and binv_wayE_upd3_q; +p1_way_data_upd30_wayE <= p1_congr_cl30_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu30_wayE_upd(0) <= p1_way_data_upd30_wayE and p1_wren_q; +rel_bixu30_wayE_upd(1) <= p0_way_data_upd30_wayE and p0_wren_q; +p0_way_data_upd30_wayF <= p0_congr_cl30_act_q and binv_wayF_upd3_q; +p1_way_data_upd30_wayF <= p1_congr_cl30_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu30_wayF_upd(0) <= p1_way_data_upd30_wayF and p1_wren_q; +rel_bixu30_wayF_upd(1) <= p0_way_data_upd30_wayF and p0_wren_q; +p0_way_data_upd30_wayG <= p0_congr_cl30_act_q and binv_wayG_upd3_q; +p1_way_data_upd30_wayG <= p1_congr_cl30_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu30_wayG_upd(0) <= p1_way_data_upd30_wayG and p1_wren_q; +rel_bixu30_wayG_upd(1) <= p0_way_data_upd30_wayG and p0_wren_q; +p0_way_data_upd30_wayH <= p0_congr_cl30_act_q and binv_wayH_upd3_q; +p1_way_data_upd30_wayH <= p1_congr_cl30_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu30_wayH_upd(0) <= p1_way_data_upd30_wayH and p1_wren_q; +rel_bixu30_wayH_upd(1) <= p0_way_data_upd30_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl31_m <= (ex5_congr_cl_q = tconv(31,6)); +p1_congr_cl31_m <= (relu_s_congr_cl_q = tconv(31,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl31_act_d <= p0_congr_cl31_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl31_act_d <= p1_congr_cl31_m and rel_port_wren_q; +congr_cl31_act <= p0_congr_cl31_act_q or p1_congr_cl31_act_q or congr_cl_all_act_q; +p0_way_data_upd31_wayA <= p0_congr_cl31_act_q and binv_wayA_upd3_q; +p1_way_data_upd31_wayA <= p1_congr_cl31_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu31_wayA_upd(0) <= p1_way_data_upd31_wayA and p1_wren_q; +rel_bixu31_wayA_upd(1) <= p0_way_data_upd31_wayA and p0_wren_q; +p0_way_data_upd31_wayB <= p0_congr_cl31_act_q and binv_wayB_upd3_q; +p1_way_data_upd31_wayB <= p1_congr_cl31_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu31_wayB_upd(0) <= p1_way_data_upd31_wayB and p1_wren_q; +rel_bixu31_wayB_upd(1) <= p0_way_data_upd31_wayB and p0_wren_q; +p0_way_data_upd31_wayC <= p0_congr_cl31_act_q and binv_wayC_upd3_q; +p1_way_data_upd31_wayC <= p1_congr_cl31_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu31_wayC_upd(0) <= p1_way_data_upd31_wayC and p1_wren_q; +rel_bixu31_wayC_upd(1) <= p0_way_data_upd31_wayC and p0_wren_q; +p0_way_data_upd31_wayD <= p0_congr_cl31_act_q and binv_wayD_upd3_q; +p1_way_data_upd31_wayD <= p1_congr_cl31_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu31_wayD_upd(0) <= p1_way_data_upd31_wayD and p1_wren_q; +rel_bixu31_wayD_upd(1) <= p0_way_data_upd31_wayD and p0_wren_q; +p0_way_data_upd31_wayE <= p0_congr_cl31_act_q and binv_wayE_upd3_q; +p1_way_data_upd31_wayE <= p1_congr_cl31_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu31_wayE_upd(0) <= p1_way_data_upd31_wayE and p1_wren_q; +rel_bixu31_wayE_upd(1) <= p0_way_data_upd31_wayE and p0_wren_q; +p0_way_data_upd31_wayF <= p0_congr_cl31_act_q and binv_wayF_upd3_q; +p1_way_data_upd31_wayF <= p1_congr_cl31_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu31_wayF_upd(0) <= p1_way_data_upd31_wayF and p1_wren_q; +rel_bixu31_wayF_upd(1) <= p0_way_data_upd31_wayF and p0_wren_q; +p0_way_data_upd31_wayG <= p0_congr_cl31_act_q and binv_wayG_upd3_q; +p1_way_data_upd31_wayG <= p1_congr_cl31_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu31_wayG_upd(0) <= p1_way_data_upd31_wayG and p1_wren_q; +rel_bixu31_wayG_upd(1) <= p0_way_data_upd31_wayG and p0_wren_q; +p0_way_data_upd31_wayH <= p0_congr_cl31_act_q and binv_wayH_upd3_q; +p1_way_data_upd31_wayH <= p1_congr_cl31_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu31_wayH_upd(0) <= p1_way_data_upd31_wayH and p1_wren_q; +rel_bixu31_wayH_upd(1) <= p0_way_data_upd31_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl32_m <= (ex5_congr_cl_q = tconv(32,6)); +p1_congr_cl32_m <= (relu_s_congr_cl_q = tconv(32,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl32_act_d <= p0_congr_cl32_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl32_act_d <= p1_congr_cl32_m and rel_port_wren_q; +congr_cl32_act <= p0_congr_cl32_act_q or p1_congr_cl32_act_q or congr_cl_all_act_q; +p0_way_data_upd32_wayA <= p0_congr_cl32_act_q and binv_wayA_upd3_q; +p1_way_data_upd32_wayA <= p1_congr_cl32_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu32_wayA_upd(0) <= p1_way_data_upd32_wayA and p1_wren_q; +rel_bixu32_wayA_upd(1) <= p0_way_data_upd32_wayA and p0_wren_q; +p0_way_data_upd32_wayB <= p0_congr_cl32_act_q and binv_wayB_upd3_q; +p1_way_data_upd32_wayB <= p1_congr_cl32_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu32_wayB_upd(0) <= p1_way_data_upd32_wayB and p1_wren_q; +rel_bixu32_wayB_upd(1) <= p0_way_data_upd32_wayB and p0_wren_q; +p0_way_data_upd32_wayC <= p0_congr_cl32_act_q and binv_wayC_upd3_q; +p1_way_data_upd32_wayC <= p1_congr_cl32_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu32_wayC_upd(0) <= p1_way_data_upd32_wayC and p1_wren_q; +rel_bixu32_wayC_upd(1) <= p0_way_data_upd32_wayC and p0_wren_q; +p0_way_data_upd32_wayD <= p0_congr_cl32_act_q and binv_wayD_upd3_q; +p1_way_data_upd32_wayD <= p1_congr_cl32_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu32_wayD_upd(0) <= p1_way_data_upd32_wayD and p1_wren_q; +rel_bixu32_wayD_upd(1) <= p0_way_data_upd32_wayD and p0_wren_q; +p0_way_data_upd32_wayE <= p0_congr_cl32_act_q and binv_wayE_upd3_q; +p1_way_data_upd32_wayE <= p1_congr_cl32_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu32_wayE_upd(0) <= p1_way_data_upd32_wayE and p1_wren_q; +rel_bixu32_wayE_upd(1) <= p0_way_data_upd32_wayE and p0_wren_q; +p0_way_data_upd32_wayF <= p0_congr_cl32_act_q and binv_wayF_upd3_q; +p1_way_data_upd32_wayF <= p1_congr_cl32_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu32_wayF_upd(0) <= p1_way_data_upd32_wayF and p1_wren_q; +rel_bixu32_wayF_upd(1) <= p0_way_data_upd32_wayF and p0_wren_q; +p0_way_data_upd32_wayG <= p0_congr_cl32_act_q and binv_wayG_upd3_q; +p1_way_data_upd32_wayG <= p1_congr_cl32_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu32_wayG_upd(0) <= p1_way_data_upd32_wayG and p1_wren_q; +rel_bixu32_wayG_upd(1) <= p0_way_data_upd32_wayG and p0_wren_q; +p0_way_data_upd32_wayH <= p0_congr_cl32_act_q and binv_wayH_upd3_q; +p1_way_data_upd32_wayH <= p1_congr_cl32_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu32_wayH_upd(0) <= p1_way_data_upd32_wayH and p1_wren_q; +rel_bixu32_wayH_upd(1) <= p0_way_data_upd32_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl33_m <= (ex5_congr_cl_q = tconv(33,6)); +p1_congr_cl33_m <= (relu_s_congr_cl_q = tconv(33,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl33_act_d <= p0_congr_cl33_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl33_act_d <= p1_congr_cl33_m and rel_port_wren_q; +congr_cl33_act <= p0_congr_cl33_act_q or p1_congr_cl33_act_q or congr_cl_all_act_q; +p0_way_data_upd33_wayA <= p0_congr_cl33_act_q and binv_wayA_upd3_q; +p1_way_data_upd33_wayA <= p1_congr_cl33_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu33_wayA_upd(0) <= p1_way_data_upd33_wayA and p1_wren_q; +rel_bixu33_wayA_upd(1) <= p0_way_data_upd33_wayA and p0_wren_q; +p0_way_data_upd33_wayB <= p0_congr_cl33_act_q and binv_wayB_upd3_q; +p1_way_data_upd33_wayB <= p1_congr_cl33_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu33_wayB_upd(0) <= p1_way_data_upd33_wayB and p1_wren_q; +rel_bixu33_wayB_upd(1) <= p0_way_data_upd33_wayB and p0_wren_q; +p0_way_data_upd33_wayC <= p0_congr_cl33_act_q and binv_wayC_upd3_q; +p1_way_data_upd33_wayC <= p1_congr_cl33_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu33_wayC_upd(0) <= p1_way_data_upd33_wayC and p1_wren_q; +rel_bixu33_wayC_upd(1) <= p0_way_data_upd33_wayC and p0_wren_q; +p0_way_data_upd33_wayD <= p0_congr_cl33_act_q and binv_wayD_upd3_q; +p1_way_data_upd33_wayD <= p1_congr_cl33_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu33_wayD_upd(0) <= p1_way_data_upd33_wayD and p1_wren_q; +rel_bixu33_wayD_upd(1) <= p0_way_data_upd33_wayD and p0_wren_q; +p0_way_data_upd33_wayE <= p0_congr_cl33_act_q and binv_wayE_upd3_q; +p1_way_data_upd33_wayE <= p1_congr_cl33_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu33_wayE_upd(0) <= p1_way_data_upd33_wayE and p1_wren_q; +rel_bixu33_wayE_upd(1) <= p0_way_data_upd33_wayE and p0_wren_q; +p0_way_data_upd33_wayF <= p0_congr_cl33_act_q and binv_wayF_upd3_q; +p1_way_data_upd33_wayF <= p1_congr_cl33_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu33_wayF_upd(0) <= p1_way_data_upd33_wayF and p1_wren_q; +rel_bixu33_wayF_upd(1) <= p0_way_data_upd33_wayF and p0_wren_q; +p0_way_data_upd33_wayG <= p0_congr_cl33_act_q and binv_wayG_upd3_q; +p1_way_data_upd33_wayG <= p1_congr_cl33_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu33_wayG_upd(0) <= p1_way_data_upd33_wayG and p1_wren_q; +rel_bixu33_wayG_upd(1) <= p0_way_data_upd33_wayG and p0_wren_q; +p0_way_data_upd33_wayH <= p0_congr_cl33_act_q and binv_wayH_upd3_q; +p1_way_data_upd33_wayH <= p1_congr_cl33_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu33_wayH_upd(0) <= p1_way_data_upd33_wayH and p1_wren_q; +rel_bixu33_wayH_upd(1) <= p0_way_data_upd33_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl34_m <= (ex5_congr_cl_q = tconv(34,6)); +p1_congr_cl34_m <= (relu_s_congr_cl_q = tconv(34,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl34_act_d <= p0_congr_cl34_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl34_act_d <= p1_congr_cl34_m and rel_port_wren_q; +congr_cl34_act <= p0_congr_cl34_act_q or p1_congr_cl34_act_q or congr_cl_all_act_q; +p0_way_data_upd34_wayA <= p0_congr_cl34_act_q and binv_wayA_upd3_q; +p1_way_data_upd34_wayA <= p1_congr_cl34_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu34_wayA_upd(0) <= p1_way_data_upd34_wayA and p1_wren_q; +rel_bixu34_wayA_upd(1) <= p0_way_data_upd34_wayA and p0_wren_q; +p0_way_data_upd34_wayB <= p0_congr_cl34_act_q and binv_wayB_upd3_q; +p1_way_data_upd34_wayB <= p1_congr_cl34_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu34_wayB_upd(0) <= p1_way_data_upd34_wayB and p1_wren_q; +rel_bixu34_wayB_upd(1) <= p0_way_data_upd34_wayB and p0_wren_q; +p0_way_data_upd34_wayC <= p0_congr_cl34_act_q and binv_wayC_upd3_q; +p1_way_data_upd34_wayC <= p1_congr_cl34_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu34_wayC_upd(0) <= p1_way_data_upd34_wayC and p1_wren_q; +rel_bixu34_wayC_upd(1) <= p0_way_data_upd34_wayC and p0_wren_q; +p0_way_data_upd34_wayD <= p0_congr_cl34_act_q and binv_wayD_upd3_q; +p1_way_data_upd34_wayD <= p1_congr_cl34_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu34_wayD_upd(0) <= p1_way_data_upd34_wayD and p1_wren_q; +rel_bixu34_wayD_upd(1) <= p0_way_data_upd34_wayD and p0_wren_q; +p0_way_data_upd34_wayE <= p0_congr_cl34_act_q and binv_wayE_upd3_q; +p1_way_data_upd34_wayE <= p1_congr_cl34_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu34_wayE_upd(0) <= p1_way_data_upd34_wayE and p1_wren_q; +rel_bixu34_wayE_upd(1) <= p0_way_data_upd34_wayE and p0_wren_q; +p0_way_data_upd34_wayF <= p0_congr_cl34_act_q and binv_wayF_upd3_q; +p1_way_data_upd34_wayF <= p1_congr_cl34_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu34_wayF_upd(0) <= p1_way_data_upd34_wayF and p1_wren_q; +rel_bixu34_wayF_upd(1) <= p0_way_data_upd34_wayF and p0_wren_q; +p0_way_data_upd34_wayG <= p0_congr_cl34_act_q and binv_wayG_upd3_q; +p1_way_data_upd34_wayG <= p1_congr_cl34_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu34_wayG_upd(0) <= p1_way_data_upd34_wayG and p1_wren_q; +rel_bixu34_wayG_upd(1) <= p0_way_data_upd34_wayG and p0_wren_q; +p0_way_data_upd34_wayH <= p0_congr_cl34_act_q and binv_wayH_upd3_q; +p1_way_data_upd34_wayH <= p1_congr_cl34_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu34_wayH_upd(0) <= p1_way_data_upd34_wayH and p1_wren_q; +rel_bixu34_wayH_upd(1) <= p0_way_data_upd34_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl35_m <= (ex5_congr_cl_q = tconv(35,6)); +p1_congr_cl35_m <= (relu_s_congr_cl_q = tconv(35,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl35_act_d <= p0_congr_cl35_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl35_act_d <= p1_congr_cl35_m and rel_port_wren_q; +congr_cl35_act <= p0_congr_cl35_act_q or p1_congr_cl35_act_q or congr_cl_all_act_q; +p0_way_data_upd35_wayA <= p0_congr_cl35_act_q and binv_wayA_upd3_q; +p1_way_data_upd35_wayA <= p1_congr_cl35_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu35_wayA_upd(0) <= p1_way_data_upd35_wayA and p1_wren_q; +rel_bixu35_wayA_upd(1) <= p0_way_data_upd35_wayA and p0_wren_q; +p0_way_data_upd35_wayB <= p0_congr_cl35_act_q and binv_wayB_upd3_q; +p1_way_data_upd35_wayB <= p1_congr_cl35_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu35_wayB_upd(0) <= p1_way_data_upd35_wayB and p1_wren_q; +rel_bixu35_wayB_upd(1) <= p0_way_data_upd35_wayB and p0_wren_q; +p0_way_data_upd35_wayC <= p0_congr_cl35_act_q and binv_wayC_upd3_q; +p1_way_data_upd35_wayC <= p1_congr_cl35_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu35_wayC_upd(0) <= p1_way_data_upd35_wayC and p1_wren_q; +rel_bixu35_wayC_upd(1) <= p0_way_data_upd35_wayC and p0_wren_q; +p0_way_data_upd35_wayD <= p0_congr_cl35_act_q and binv_wayD_upd3_q; +p1_way_data_upd35_wayD <= p1_congr_cl35_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu35_wayD_upd(0) <= p1_way_data_upd35_wayD and p1_wren_q; +rel_bixu35_wayD_upd(1) <= p0_way_data_upd35_wayD and p0_wren_q; +p0_way_data_upd35_wayE <= p0_congr_cl35_act_q and binv_wayE_upd3_q; +p1_way_data_upd35_wayE <= p1_congr_cl35_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu35_wayE_upd(0) <= p1_way_data_upd35_wayE and p1_wren_q; +rel_bixu35_wayE_upd(1) <= p0_way_data_upd35_wayE and p0_wren_q; +p0_way_data_upd35_wayF <= p0_congr_cl35_act_q and binv_wayF_upd3_q; +p1_way_data_upd35_wayF <= p1_congr_cl35_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu35_wayF_upd(0) <= p1_way_data_upd35_wayF and p1_wren_q; +rel_bixu35_wayF_upd(1) <= p0_way_data_upd35_wayF and p0_wren_q; +p0_way_data_upd35_wayG <= p0_congr_cl35_act_q and binv_wayG_upd3_q; +p1_way_data_upd35_wayG <= p1_congr_cl35_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu35_wayG_upd(0) <= p1_way_data_upd35_wayG and p1_wren_q; +rel_bixu35_wayG_upd(1) <= p0_way_data_upd35_wayG and p0_wren_q; +p0_way_data_upd35_wayH <= p0_congr_cl35_act_q and binv_wayH_upd3_q; +p1_way_data_upd35_wayH <= p1_congr_cl35_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu35_wayH_upd(0) <= p1_way_data_upd35_wayH and p1_wren_q; +rel_bixu35_wayH_upd(1) <= p0_way_data_upd35_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl36_m <= (ex5_congr_cl_q = tconv(36,6)); +p1_congr_cl36_m <= (relu_s_congr_cl_q = tconv(36,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl36_act_d <= p0_congr_cl36_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl36_act_d <= p1_congr_cl36_m and rel_port_wren_q; +congr_cl36_act <= p0_congr_cl36_act_q or p1_congr_cl36_act_q or congr_cl_all_act_q; +p0_way_data_upd36_wayA <= p0_congr_cl36_act_q and binv_wayA_upd3_q; +p1_way_data_upd36_wayA <= p1_congr_cl36_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu36_wayA_upd(0) <= p1_way_data_upd36_wayA and p1_wren_q; +rel_bixu36_wayA_upd(1) <= p0_way_data_upd36_wayA and p0_wren_q; +p0_way_data_upd36_wayB <= p0_congr_cl36_act_q and binv_wayB_upd3_q; +p1_way_data_upd36_wayB <= p1_congr_cl36_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu36_wayB_upd(0) <= p1_way_data_upd36_wayB and p1_wren_q; +rel_bixu36_wayB_upd(1) <= p0_way_data_upd36_wayB and p0_wren_q; +p0_way_data_upd36_wayC <= p0_congr_cl36_act_q and binv_wayC_upd3_q; +p1_way_data_upd36_wayC <= p1_congr_cl36_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu36_wayC_upd(0) <= p1_way_data_upd36_wayC and p1_wren_q; +rel_bixu36_wayC_upd(1) <= p0_way_data_upd36_wayC and p0_wren_q; +p0_way_data_upd36_wayD <= p0_congr_cl36_act_q and binv_wayD_upd3_q; +p1_way_data_upd36_wayD <= p1_congr_cl36_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu36_wayD_upd(0) <= p1_way_data_upd36_wayD and p1_wren_q; +rel_bixu36_wayD_upd(1) <= p0_way_data_upd36_wayD and p0_wren_q; +p0_way_data_upd36_wayE <= p0_congr_cl36_act_q and binv_wayE_upd3_q; +p1_way_data_upd36_wayE <= p1_congr_cl36_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu36_wayE_upd(0) <= p1_way_data_upd36_wayE and p1_wren_q; +rel_bixu36_wayE_upd(1) <= p0_way_data_upd36_wayE and p0_wren_q; +p0_way_data_upd36_wayF <= p0_congr_cl36_act_q and binv_wayF_upd3_q; +p1_way_data_upd36_wayF <= p1_congr_cl36_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu36_wayF_upd(0) <= p1_way_data_upd36_wayF and p1_wren_q; +rel_bixu36_wayF_upd(1) <= p0_way_data_upd36_wayF and p0_wren_q; +p0_way_data_upd36_wayG <= p0_congr_cl36_act_q and binv_wayG_upd3_q; +p1_way_data_upd36_wayG <= p1_congr_cl36_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu36_wayG_upd(0) <= p1_way_data_upd36_wayG and p1_wren_q; +rel_bixu36_wayG_upd(1) <= p0_way_data_upd36_wayG and p0_wren_q; +p0_way_data_upd36_wayH <= p0_congr_cl36_act_q and binv_wayH_upd3_q; +p1_way_data_upd36_wayH <= p1_congr_cl36_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu36_wayH_upd(0) <= p1_way_data_upd36_wayH and p1_wren_q; +rel_bixu36_wayH_upd(1) <= p0_way_data_upd36_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl37_m <= (ex5_congr_cl_q = tconv(37,6)); +p1_congr_cl37_m <= (relu_s_congr_cl_q = tconv(37,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl37_act_d <= p0_congr_cl37_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl37_act_d <= p1_congr_cl37_m and rel_port_wren_q; +congr_cl37_act <= p0_congr_cl37_act_q or p1_congr_cl37_act_q or congr_cl_all_act_q; +p0_way_data_upd37_wayA <= p0_congr_cl37_act_q and binv_wayA_upd3_q; +p1_way_data_upd37_wayA <= p1_congr_cl37_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu37_wayA_upd(0) <= p1_way_data_upd37_wayA and p1_wren_q; +rel_bixu37_wayA_upd(1) <= p0_way_data_upd37_wayA and p0_wren_q; +p0_way_data_upd37_wayB <= p0_congr_cl37_act_q and binv_wayB_upd3_q; +p1_way_data_upd37_wayB <= p1_congr_cl37_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu37_wayB_upd(0) <= p1_way_data_upd37_wayB and p1_wren_q; +rel_bixu37_wayB_upd(1) <= p0_way_data_upd37_wayB and p0_wren_q; +p0_way_data_upd37_wayC <= p0_congr_cl37_act_q and binv_wayC_upd3_q; +p1_way_data_upd37_wayC <= p1_congr_cl37_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu37_wayC_upd(0) <= p1_way_data_upd37_wayC and p1_wren_q; +rel_bixu37_wayC_upd(1) <= p0_way_data_upd37_wayC and p0_wren_q; +p0_way_data_upd37_wayD <= p0_congr_cl37_act_q and binv_wayD_upd3_q; +p1_way_data_upd37_wayD <= p1_congr_cl37_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu37_wayD_upd(0) <= p1_way_data_upd37_wayD and p1_wren_q; +rel_bixu37_wayD_upd(1) <= p0_way_data_upd37_wayD and p0_wren_q; +p0_way_data_upd37_wayE <= p0_congr_cl37_act_q and binv_wayE_upd3_q; +p1_way_data_upd37_wayE <= p1_congr_cl37_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu37_wayE_upd(0) <= p1_way_data_upd37_wayE and p1_wren_q; +rel_bixu37_wayE_upd(1) <= p0_way_data_upd37_wayE and p0_wren_q; +p0_way_data_upd37_wayF <= p0_congr_cl37_act_q and binv_wayF_upd3_q; +p1_way_data_upd37_wayF <= p1_congr_cl37_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu37_wayF_upd(0) <= p1_way_data_upd37_wayF and p1_wren_q; +rel_bixu37_wayF_upd(1) <= p0_way_data_upd37_wayF and p0_wren_q; +p0_way_data_upd37_wayG <= p0_congr_cl37_act_q and binv_wayG_upd3_q; +p1_way_data_upd37_wayG <= p1_congr_cl37_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu37_wayG_upd(0) <= p1_way_data_upd37_wayG and p1_wren_q; +rel_bixu37_wayG_upd(1) <= p0_way_data_upd37_wayG and p0_wren_q; +p0_way_data_upd37_wayH <= p0_congr_cl37_act_q and binv_wayH_upd3_q; +p1_way_data_upd37_wayH <= p1_congr_cl37_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu37_wayH_upd(0) <= p1_way_data_upd37_wayH and p1_wren_q; +rel_bixu37_wayH_upd(1) <= p0_way_data_upd37_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl38_m <= (ex5_congr_cl_q = tconv(38,6)); +p1_congr_cl38_m <= (relu_s_congr_cl_q = tconv(38,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl38_act_d <= p0_congr_cl38_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl38_act_d <= p1_congr_cl38_m and rel_port_wren_q; +congr_cl38_act <= p0_congr_cl38_act_q or p1_congr_cl38_act_q or congr_cl_all_act_q; +p0_way_data_upd38_wayA <= p0_congr_cl38_act_q and binv_wayA_upd3_q; +p1_way_data_upd38_wayA <= p1_congr_cl38_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu38_wayA_upd(0) <= p1_way_data_upd38_wayA and p1_wren_q; +rel_bixu38_wayA_upd(1) <= p0_way_data_upd38_wayA and p0_wren_q; +p0_way_data_upd38_wayB <= p0_congr_cl38_act_q and binv_wayB_upd3_q; +p1_way_data_upd38_wayB <= p1_congr_cl38_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu38_wayB_upd(0) <= p1_way_data_upd38_wayB and p1_wren_q; +rel_bixu38_wayB_upd(1) <= p0_way_data_upd38_wayB and p0_wren_q; +p0_way_data_upd38_wayC <= p0_congr_cl38_act_q and binv_wayC_upd3_q; +p1_way_data_upd38_wayC <= p1_congr_cl38_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu38_wayC_upd(0) <= p1_way_data_upd38_wayC and p1_wren_q; +rel_bixu38_wayC_upd(1) <= p0_way_data_upd38_wayC and p0_wren_q; +p0_way_data_upd38_wayD <= p0_congr_cl38_act_q and binv_wayD_upd3_q; +p1_way_data_upd38_wayD <= p1_congr_cl38_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu38_wayD_upd(0) <= p1_way_data_upd38_wayD and p1_wren_q; +rel_bixu38_wayD_upd(1) <= p0_way_data_upd38_wayD and p0_wren_q; +p0_way_data_upd38_wayE <= p0_congr_cl38_act_q and binv_wayE_upd3_q; +p1_way_data_upd38_wayE <= p1_congr_cl38_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu38_wayE_upd(0) <= p1_way_data_upd38_wayE and p1_wren_q; +rel_bixu38_wayE_upd(1) <= p0_way_data_upd38_wayE and p0_wren_q; +p0_way_data_upd38_wayF <= p0_congr_cl38_act_q and binv_wayF_upd3_q; +p1_way_data_upd38_wayF <= p1_congr_cl38_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu38_wayF_upd(0) <= p1_way_data_upd38_wayF and p1_wren_q; +rel_bixu38_wayF_upd(1) <= p0_way_data_upd38_wayF and p0_wren_q; +p0_way_data_upd38_wayG <= p0_congr_cl38_act_q and binv_wayG_upd3_q; +p1_way_data_upd38_wayG <= p1_congr_cl38_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu38_wayG_upd(0) <= p1_way_data_upd38_wayG and p1_wren_q; +rel_bixu38_wayG_upd(1) <= p0_way_data_upd38_wayG and p0_wren_q; +p0_way_data_upd38_wayH <= p0_congr_cl38_act_q and binv_wayH_upd3_q; +p1_way_data_upd38_wayH <= p1_congr_cl38_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu38_wayH_upd(0) <= p1_way_data_upd38_wayH and p1_wren_q; +rel_bixu38_wayH_upd(1) <= p0_way_data_upd38_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl39_m <= (ex5_congr_cl_q = tconv(39,6)); +p1_congr_cl39_m <= (relu_s_congr_cl_q = tconv(39,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl39_act_d <= p0_congr_cl39_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl39_act_d <= p1_congr_cl39_m and rel_port_wren_q; +congr_cl39_act <= p0_congr_cl39_act_q or p1_congr_cl39_act_q or congr_cl_all_act_q; +p0_way_data_upd39_wayA <= p0_congr_cl39_act_q and binv_wayA_upd3_q; +p1_way_data_upd39_wayA <= p1_congr_cl39_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu39_wayA_upd(0) <= p1_way_data_upd39_wayA and p1_wren_q; +rel_bixu39_wayA_upd(1) <= p0_way_data_upd39_wayA and p0_wren_q; +p0_way_data_upd39_wayB <= p0_congr_cl39_act_q and binv_wayB_upd3_q; +p1_way_data_upd39_wayB <= p1_congr_cl39_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu39_wayB_upd(0) <= p1_way_data_upd39_wayB and p1_wren_q; +rel_bixu39_wayB_upd(1) <= p0_way_data_upd39_wayB and p0_wren_q; +p0_way_data_upd39_wayC <= p0_congr_cl39_act_q and binv_wayC_upd3_q; +p1_way_data_upd39_wayC <= p1_congr_cl39_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu39_wayC_upd(0) <= p1_way_data_upd39_wayC and p1_wren_q; +rel_bixu39_wayC_upd(1) <= p0_way_data_upd39_wayC and p0_wren_q; +p0_way_data_upd39_wayD <= p0_congr_cl39_act_q and binv_wayD_upd3_q; +p1_way_data_upd39_wayD <= p1_congr_cl39_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu39_wayD_upd(0) <= p1_way_data_upd39_wayD and p1_wren_q; +rel_bixu39_wayD_upd(1) <= p0_way_data_upd39_wayD and p0_wren_q; +p0_way_data_upd39_wayE <= p0_congr_cl39_act_q and binv_wayE_upd3_q; +p1_way_data_upd39_wayE <= p1_congr_cl39_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu39_wayE_upd(0) <= p1_way_data_upd39_wayE and p1_wren_q; +rel_bixu39_wayE_upd(1) <= p0_way_data_upd39_wayE and p0_wren_q; +p0_way_data_upd39_wayF <= p0_congr_cl39_act_q and binv_wayF_upd3_q; +p1_way_data_upd39_wayF <= p1_congr_cl39_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu39_wayF_upd(0) <= p1_way_data_upd39_wayF and p1_wren_q; +rel_bixu39_wayF_upd(1) <= p0_way_data_upd39_wayF and p0_wren_q; +p0_way_data_upd39_wayG <= p0_congr_cl39_act_q and binv_wayG_upd3_q; +p1_way_data_upd39_wayG <= p1_congr_cl39_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu39_wayG_upd(0) <= p1_way_data_upd39_wayG and p1_wren_q; +rel_bixu39_wayG_upd(1) <= p0_way_data_upd39_wayG and p0_wren_q; +p0_way_data_upd39_wayH <= p0_congr_cl39_act_q and binv_wayH_upd3_q; +p1_way_data_upd39_wayH <= p1_congr_cl39_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu39_wayH_upd(0) <= p1_way_data_upd39_wayH and p1_wren_q; +rel_bixu39_wayH_upd(1) <= p0_way_data_upd39_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl40_m <= (ex5_congr_cl_q = tconv(40,6)); +p1_congr_cl40_m <= (relu_s_congr_cl_q = tconv(40,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl40_act_d <= p0_congr_cl40_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl40_act_d <= p1_congr_cl40_m and rel_port_wren_q; +congr_cl40_act <= p0_congr_cl40_act_q or p1_congr_cl40_act_q or congr_cl_all_act_q; +p0_way_data_upd40_wayA <= p0_congr_cl40_act_q and binv_wayA_upd3_q; +p1_way_data_upd40_wayA <= p1_congr_cl40_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu40_wayA_upd(0) <= p1_way_data_upd40_wayA and p1_wren_q; +rel_bixu40_wayA_upd(1) <= p0_way_data_upd40_wayA and p0_wren_q; +p0_way_data_upd40_wayB <= p0_congr_cl40_act_q and binv_wayB_upd3_q; +p1_way_data_upd40_wayB <= p1_congr_cl40_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu40_wayB_upd(0) <= p1_way_data_upd40_wayB and p1_wren_q; +rel_bixu40_wayB_upd(1) <= p0_way_data_upd40_wayB and p0_wren_q; +p0_way_data_upd40_wayC <= p0_congr_cl40_act_q and binv_wayC_upd3_q; +p1_way_data_upd40_wayC <= p1_congr_cl40_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu40_wayC_upd(0) <= p1_way_data_upd40_wayC and p1_wren_q; +rel_bixu40_wayC_upd(1) <= p0_way_data_upd40_wayC and p0_wren_q; +p0_way_data_upd40_wayD <= p0_congr_cl40_act_q and binv_wayD_upd3_q; +p1_way_data_upd40_wayD <= p1_congr_cl40_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu40_wayD_upd(0) <= p1_way_data_upd40_wayD and p1_wren_q; +rel_bixu40_wayD_upd(1) <= p0_way_data_upd40_wayD and p0_wren_q; +p0_way_data_upd40_wayE <= p0_congr_cl40_act_q and binv_wayE_upd3_q; +p1_way_data_upd40_wayE <= p1_congr_cl40_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu40_wayE_upd(0) <= p1_way_data_upd40_wayE and p1_wren_q; +rel_bixu40_wayE_upd(1) <= p0_way_data_upd40_wayE and p0_wren_q; +p0_way_data_upd40_wayF <= p0_congr_cl40_act_q and binv_wayF_upd3_q; +p1_way_data_upd40_wayF <= p1_congr_cl40_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu40_wayF_upd(0) <= p1_way_data_upd40_wayF and p1_wren_q; +rel_bixu40_wayF_upd(1) <= p0_way_data_upd40_wayF and p0_wren_q; +p0_way_data_upd40_wayG <= p0_congr_cl40_act_q and binv_wayG_upd3_q; +p1_way_data_upd40_wayG <= p1_congr_cl40_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu40_wayG_upd(0) <= p1_way_data_upd40_wayG and p1_wren_q; +rel_bixu40_wayG_upd(1) <= p0_way_data_upd40_wayG and p0_wren_q; +p0_way_data_upd40_wayH <= p0_congr_cl40_act_q and binv_wayH_upd3_q; +p1_way_data_upd40_wayH <= p1_congr_cl40_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu40_wayH_upd(0) <= p1_way_data_upd40_wayH and p1_wren_q; +rel_bixu40_wayH_upd(1) <= p0_way_data_upd40_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl41_m <= (ex5_congr_cl_q = tconv(41,6)); +p1_congr_cl41_m <= (relu_s_congr_cl_q = tconv(41,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl41_act_d <= p0_congr_cl41_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl41_act_d <= p1_congr_cl41_m and rel_port_wren_q; +congr_cl41_act <= p0_congr_cl41_act_q or p1_congr_cl41_act_q or congr_cl_all_act_q; +p0_way_data_upd41_wayA <= p0_congr_cl41_act_q and binv_wayA_upd3_q; +p1_way_data_upd41_wayA <= p1_congr_cl41_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu41_wayA_upd(0) <= p1_way_data_upd41_wayA and p1_wren_q; +rel_bixu41_wayA_upd(1) <= p0_way_data_upd41_wayA and p0_wren_q; +p0_way_data_upd41_wayB <= p0_congr_cl41_act_q and binv_wayB_upd3_q; +p1_way_data_upd41_wayB <= p1_congr_cl41_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu41_wayB_upd(0) <= p1_way_data_upd41_wayB and p1_wren_q; +rel_bixu41_wayB_upd(1) <= p0_way_data_upd41_wayB and p0_wren_q; +p0_way_data_upd41_wayC <= p0_congr_cl41_act_q and binv_wayC_upd3_q; +p1_way_data_upd41_wayC <= p1_congr_cl41_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu41_wayC_upd(0) <= p1_way_data_upd41_wayC and p1_wren_q; +rel_bixu41_wayC_upd(1) <= p0_way_data_upd41_wayC and p0_wren_q; +p0_way_data_upd41_wayD <= p0_congr_cl41_act_q and binv_wayD_upd3_q; +p1_way_data_upd41_wayD <= p1_congr_cl41_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu41_wayD_upd(0) <= p1_way_data_upd41_wayD and p1_wren_q; +rel_bixu41_wayD_upd(1) <= p0_way_data_upd41_wayD and p0_wren_q; +p0_way_data_upd41_wayE <= p0_congr_cl41_act_q and binv_wayE_upd3_q; +p1_way_data_upd41_wayE <= p1_congr_cl41_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu41_wayE_upd(0) <= p1_way_data_upd41_wayE and p1_wren_q; +rel_bixu41_wayE_upd(1) <= p0_way_data_upd41_wayE and p0_wren_q; +p0_way_data_upd41_wayF <= p0_congr_cl41_act_q and binv_wayF_upd3_q; +p1_way_data_upd41_wayF <= p1_congr_cl41_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu41_wayF_upd(0) <= p1_way_data_upd41_wayF and p1_wren_q; +rel_bixu41_wayF_upd(1) <= p0_way_data_upd41_wayF and p0_wren_q; +p0_way_data_upd41_wayG <= p0_congr_cl41_act_q and binv_wayG_upd3_q; +p1_way_data_upd41_wayG <= p1_congr_cl41_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu41_wayG_upd(0) <= p1_way_data_upd41_wayG and p1_wren_q; +rel_bixu41_wayG_upd(1) <= p0_way_data_upd41_wayG and p0_wren_q; +p0_way_data_upd41_wayH <= p0_congr_cl41_act_q and binv_wayH_upd3_q; +p1_way_data_upd41_wayH <= p1_congr_cl41_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu41_wayH_upd(0) <= p1_way_data_upd41_wayH and p1_wren_q; +rel_bixu41_wayH_upd(1) <= p0_way_data_upd41_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl42_m <= (ex5_congr_cl_q = tconv(42,6)); +p1_congr_cl42_m <= (relu_s_congr_cl_q = tconv(42,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl42_act_d <= p0_congr_cl42_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl42_act_d <= p1_congr_cl42_m and rel_port_wren_q; +congr_cl42_act <= p0_congr_cl42_act_q or p1_congr_cl42_act_q or congr_cl_all_act_q; +p0_way_data_upd42_wayA <= p0_congr_cl42_act_q and binv_wayA_upd3_q; +p1_way_data_upd42_wayA <= p1_congr_cl42_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu42_wayA_upd(0) <= p1_way_data_upd42_wayA and p1_wren_q; +rel_bixu42_wayA_upd(1) <= p0_way_data_upd42_wayA and p0_wren_q; +p0_way_data_upd42_wayB <= p0_congr_cl42_act_q and binv_wayB_upd3_q; +p1_way_data_upd42_wayB <= p1_congr_cl42_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu42_wayB_upd(0) <= p1_way_data_upd42_wayB and p1_wren_q; +rel_bixu42_wayB_upd(1) <= p0_way_data_upd42_wayB and p0_wren_q; +p0_way_data_upd42_wayC <= p0_congr_cl42_act_q and binv_wayC_upd3_q; +p1_way_data_upd42_wayC <= p1_congr_cl42_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu42_wayC_upd(0) <= p1_way_data_upd42_wayC and p1_wren_q; +rel_bixu42_wayC_upd(1) <= p0_way_data_upd42_wayC and p0_wren_q; +p0_way_data_upd42_wayD <= p0_congr_cl42_act_q and binv_wayD_upd3_q; +p1_way_data_upd42_wayD <= p1_congr_cl42_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu42_wayD_upd(0) <= p1_way_data_upd42_wayD and p1_wren_q; +rel_bixu42_wayD_upd(1) <= p0_way_data_upd42_wayD and p0_wren_q; +p0_way_data_upd42_wayE <= p0_congr_cl42_act_q and binv_wayE_upd3_q; +p1_way_data_upd42_wayE <= p1_congr_cl42_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu42_wayE_upd(0) <= p1_way_data_upd42_wayE and p1_wren_q; +rel_bixu42_wayE_upd(1) <= p0_way_data_upd42_wayE and p0_wren_q; +p0_way_data_upd42_wayF <= p0_congr_cl42_act_q and binv_wayF_upd3_q; +p1_way_data_upd42_wayF <= p1_congr_cl42_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu42_wayF_upd(0) <= p1_way_data_upd42_wayF and p1_wren_q; +rel_bixu42_wayF_upd(1) <= p0_way_data_upd42_wayF and p0_wren_q; +p0_way_data_upd42_wayG <= p0_congr_cl42_act_q and binv_wayG_upd3_q; +p1_way_data_upd42_wayG <= p1_congr_cl42_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu42_wayG_upd(0) <= p1_way_data_upd42_wayG and p1_wren_q; +rel_bixu42_wayG_upd(1) <= p0_way_data_upd42_wayG and p0_wren_q; +p0_way_data_upd42_wayH <= p0_congr_cl42_act_q and binv_wayH_upd3_q; +p1_way_data_upd42_wayH <= p1_congr_cl42_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu42_wayH_upd(0) <= p1_way_data_upd42_wayH and p1_wren_q; +rel_bixu42_wayH_upd(1) <= p0_way_data_upd42_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl43_m <= (ex5_congr_cl_q = tconv(43,6)); +p1_congr_cl43_m <= (relu_s_congr_cl_q = tconv(43,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl43_act_d <= p0_congr_cl43_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl43_act_d <= p1_congr_cl43_m and rel_port_wren_q; +congr_cl43_act <= p0_congr_cl43_act_q or p1_congr_cl43_act_q or congr_cl_all_act_q; +p0_way_data_upd43_wayA <= p0_congr_cl43_act_q and binv_wayA_upd3_q; +p1_way_data_upd43_wayA <= p1_congr_cl43_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu43_wayA_upd(0) <= p1_way_data_upd43_wayA and p1_wren_q; +rel_bixu43_wayA_upd(1) <= p0_way_data_upd43_wayA and p0_wren_q; +p0_way_data_upd43_wayB <= p0_congr_cl43_act_q and binv_wayB_upd3_q; +p1_way_data_upd43_wayB <= p1_congr_cl43_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu43_wayB_upd(0) <= p1_way_data_upd43_wayB and p1_wren_q; +rel_bixu43_wayB_upd(1) <= p0_way_data_upd43_wayB and p0_wren_q; +p0_way_data_upd43_wayC <= p0_congr_cl43_act_q and binv_wayC_upd3_q; +p1_way_data_upd43_wayC <= p1_congr_cl43_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu43_wayC_upd(0) <= p1_way_data_upd43_wayC and p1_wren_q; +rel_bixu43_wayC_upd(1) <= p0_way_data_upd43_wayC and p0_wren_q; +p0_way_data_upd43_wayD <= p0_congr_cl43_act_q and binv_wayD_upd3_q; +p1_way_data_upd43_wayD <= p1_congr_cl43_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu43_wayD_upd(0) <= p1_way_data_upd43_wayD and p1_wren_q; +rel_bixu43_wayD_upd(1) <= p0_way_data_upd43_wayD and p0_wren_q; +p0_way_data_upd43_wayE <= p0_congr_cl43_act_q and binv_wayE_upd3_q; +p1_way_data_upd43_wayE <= p1_congr_cl43_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu43_wayE_upd(0) <= p1_way_data_upd43_wayE and p1_wren_q; +rel_bixu43_wayE_upd(1) <= p0_way_data_upd43_wayE and p0_wren_q; +p0_way_data_upd43_wayF <= p0_congr_cl43_act_q and binv_wayF_upd3_q; +p1_way_data_upd43_wayF <= p1_congr_cl43_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu43_wayF_upd(0) <= p1_way_data_upd43_wayF and p1_wren_q; +rel_bixu43_wayF_upd(1) <= p0_way_data_upd43_wayF and p0_wren_q; +p0_way_data_upd43_wayG <= p0_congr_cl43_act_q and binv_wayG_upd3_q; +p1_way_data_upd43_wayG <= p1_congr_cl43_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu43_wayG_upd(0) <= p1_way_data_upd43_wayG and p1_wren_q; +rel_bixu43_wayG_upd(1) <= p0_way_data_upd43_wayG and p0_wren_q; +p0_way_data_upd43_wayH <= p0_congr_cl43_act_q and binv_wayH_upd3_q; +p1_way_data_upd43_wayH <= p1_congr_cl43_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu43_wayH_upd(0) <= p1_way_data_upd43_wayH and p1_wren_q; +rel_bixu43_wayH_upd(1) <= p0_way_data_upd43_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl44_m <= (ex5_congr_cl_q = tconv(44,6)); +p1_congr_cl44_m <= (relu_s_congr_cl_q = tconv(44,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl44_act_d <= p0_congr_cl44_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl44_act_d <= p1_congr_cl44_m and rel_port_wren_q; +congr_cl44_act <= p0_congr_cl44_act_q or p1_congr_cl44_act_q or congr_cl_all_act_q; +p0_way_data_upd44_wayA <= p0_congr_cl44_act_q and binv_wayA_upd3_q; +p1_way_data_upd44_wayA <= p1_congr_cl44_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu44_wayA_upd(0) <= p1_way_data_upd44_wayA and p1_wren_q; +rel_bixu44_wayA_upd(1) <= p0_way_data_upd44_wayA and p0_wren_q; +p0_way_data_upd44_wayB <= p0_congr_cl44_act_q and binv_wayB_upd3_q; +p1_way_data_upd44_wayB <= p1_congr_cl44_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu44_wayB_upd(0) <= p1_way_data_upd44_wayB and p1_wren_q; +rel_bixu44_wayB_upd(1) <= p0_way_data_upd44_wayB and p0_wren_q; +p0_way_data_upd44_wayC <= p0_congr_cl44_act_q and binv_wayC_upd3_q; +p1_way_data_upd44_wayC <= p1_congr_cl44_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu44_wayC_upd(0) <= p1_way_data_upd44_wayC and p1_wren_q; +rel_bixu44_wayC_upd(1) <= p0_way_data_upd44_wayC and p0_wren_q; +p0_way_data_upd44_wayD <= p0_congr_cl44_act_q and binv_wayD_upd3_q; +p1_way_data_upd44_wayD <= p1_congr_cl44_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu44_wayD_upd(0) <= p1_way_data_upd44_wayD and p1_wren_q; +rel_bixu44_wayD_upd(1) <= p0_way_data_upd44_wayD and p0_wren_q; +p0_way_data_upd44_wayE <= p0_congr_cl44_act_q and binv_wayE_upd3_q; +p1_way_data_upd44_wayE <= p1_congr_cl44_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu44_wayE_upd(0) <= p1_way_data_upd44_wayE and p1_wren_q; +rel_bixu44_wayE_upd(1) <= p0_way_data_upd44_wayE and p0_wren_q; +p0_way_data_upd44_wayF <= p0_congr_cl44_act_q and binv_wayF_upd3_q; +p1_way_data_upd44_wayF <= p1_congr_cl44_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu44_wayF_upd(0) <= p1_way_data_upd44_wayF and p1_wren_q; +rel_bixu44_wayF_upd(1) <= p0_way_data_upd44_wayF and p0_wren_q; +p0_way_data_upd44_wayG <= p0_congr_cl44_act_q and binv_wayG_upd3_q; +p1_way_data_upd44_wayG <= p1_congr_cl44_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu44_wayG_upd(0) <= p1_way_data_upd44_wayG and p1_wren_q; +rel_bixu44_wayG_upd(1) <= p0_way_data_upd44_wayG and p0_wren_q; +p0_way_data_upd44_wayH <= p0_congr_cl44_act_q and binv_wayH_upd3_q; +p1_way_data_upd44_wayH <= p1_congr_cl44_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu44_wayH_upd(0) <= p1_way_data_upd44_wayH and p1_wren_q; +rel_bixu44_wayH_upd(1) <= p0_way_data_upd44_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl45_m <= (ex5_congr_cl_q = tconv(45,6)); +p1_congr_cl45_m <= (relu_s_congr_cl_q = tconv(45,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl45_act_d <= p0_congr_cl45_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl45_act_d <= p1_congr_cl45_m and rel_port_wren_q; +congr_cl45_act <= p0_congr_cl45_act_q or p1_congr_cl45_act_q or congr_cl_all_act_q; +p0_way_data_upd45_wayA <= p0_congr_cl45_act_q and binv_wayA_upd3_q; +p1_way_data_upd45_wayA <= p1_congr_cl45_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu45_wayA_upd(0) <= p1_way_data_upd45_wayA and p1_wren_q; +rel_bixu45_wayA_upd(1) <= p0_way_data_upd45_wayA and p0_wren_q; +p0_way_data_upd45_wayB <= p0_congr_cl45_act_q and binv_wayB_upd3_q; +p1_way_data_upd45_wayB <= p1_congr_cl45_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu45_wayB_upd(0) <= p1_way_data_upd45_wayB and p1_wren_q; +rel_bixu45_wayB_upd(1) <= p0_way_data_upd45_wayB and p0_wren_q; +p0_way_data_upd45_wayC <= p0_congr_cl45_act_q and binv_wayC_upd3_q; +p1_way_data_upd45_wayC <= p1_congr_cl45_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu45_wayC_upd(0) <= p1_way_data_upd45_wayC and p1_wren_q; +rel_bixu45_wayC_upd(1) <= p0_way_data_upd45_wayC and p0_wren_q; +p0_way_data_upd45_wayD <= p0_congr_cl45_act_q and binv_wayD_upd3_q; +p1_way_data_upd45_wayD <= p1_congr_cl45_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu45_wayD_upd(0) <= p1_way_data_upd45_wayD and p1_wren_q; +rel_bixu45_wayD_upd(1) <= p0_way_data_upd45_wayD and p0_wren_q; +p0_way_data_upd45_wayE <= p0_congr_cl45_act_q and binv_wayE_upd3_q; +p1_way_data_upd45_wayE <= p1_congr_cl45_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu45_wayE_upd(0) <= p1_way_data_upd45_wayE and p1_wren_q; +rel_bixu45_wayE_upd(1) <= p0_way_data_upd45_wayE and p0_wren_q; +p0_way_data_upd45_wayF <= p0_congr_cl45_act_q and binv_wayF_upd3_q; +p1_way_data_upd45_wayF <= p1_congr_cl45_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu45_wayF_upd(0) <= p1_way_data_upd45_wayF and p1_wren_q; +rel_bixu45_wayF_upd(1) <= p0_way_data_upd45_wayF and p0_wren_q; +p0_way_data_upd45_wayG <= p0_congr_cl45_act_q and binv_wayG_upd3_q; +p1_way_data_upd45_wayG <= p1_congr_cl45_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu45_wayG_upd(0) <= p1_way_data_upd45_wayG and p1_wren_q; +rel_bixu45_wayG_upd(1) <= p0_way_data_upd45_wayG and p0_wren_q; +p0_way_data_upd45_wayH <= p0_congr_cl45_act_q and binv_wayH_upd3_q; +p1_way_data_upd45_wayH <= p1_congr_cl45_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu45_wayH_upd(0) <= p1_way_data_upd45_wayH and p1_wren_q; +rel_bixu45_wayH_upd(1) <= p0_way_data_upd45_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl46_m <= (ex5_congr_cl_q = tconv(46,6)); +p1_congr_cl46_m <= (relu_s_congr_cl_q = tconv(46,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl46_act_d <= p0_congr_cl46_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl46_act_d <= p1_congr_cl46_m and rel_port_wren_q; +congr_cl46_act <= p0_congr_cl46_act_q or p1_congr_cl46_act_q or congr_cl_all_act_q; +p0_way_data_upd46_wayA <= p0_congr_cl46_act_q and binv_wayA_upd3_q; +p1_way_data_upd46_wayA <= p1_congr_cl46_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu46_wayA_upd(0) <= p1_way_data_upd46_wayA and p1_wren_q; +rel_bixu46_wayA_upd(1) <= p0_way_data_upd46_wayA and p0_wren_q; +p0_way_data_upd46_wayB <= p0_congr_cl46_act_q and binv_wayB_upd3_q; +p1_way_data_upd46_wayB <= p1_congr_cl46_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu46_wayB_upd(0) <= p1_way_data_upd46_wayB and p1_wren_q; +rel_bixu46_wayB_upd(1) <= p0_way_data_upd46_wayB and p0_wren_q; +p0_way_data_upd46_wayC <= p0_congr_cl46_act_q and binv_wayC_upd3_q; +p1_way_data_upd46_wayC <= p1_congr_cl46_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu46_wayC_upd(0) <= p1_way_data_upd46_wayC and p1_wren_q; +rel_bixu46_wayC_upd(1) <= p0_way_data_upd46_wayC and p0_wren_q; +p0_way_data_upd46_wayD <= p0_congr_cl46_act_q and binv_wayD_upd3_q; +p1_way_data_upd46_wayD <= p1_congr_cl46_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu46_wayD_upd(0) <= p1_way_data_upd46_wayD and p1_wren_q; +rel_bixu46_wayD_upd(1) <= p0_way_data_upd46_wayD and p0_wren_q; +p0_way_data_upd46_wayE <= p0_congr_cl46_act_q and binv_wayE_upd3_q; +p1_way_data_upd46_wayE <= p1_congr_cl46_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu46_wayE_upd(0) <= p1_way_data_upd46_wayE and p1_wren_q; +rel_bixu46_wayE_upd(1) <= p0_way_data_upd46_wayE and p0_wren_q; +p0_way_data_upd46_wayF <= p0_congr_cl46_act_q and binv_wayF_upd3_q; +p1_way_data_upd46_wayF <= p1_congr_cl46_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu46_wayF_upd(0) <= p1_way_data_upd46_wayF and p1_wren_q; +rel_bixu46_wayF_upd(1) <= p0_way_data_upd46_wayF and p0_wren_q; +p0_way_data_upd46_wayG <= p0_congr_cl46_act_q and binv_wayG_upd3_q; +p1_way_data_upd46_wayG <= p1_congr_cl46_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu46_wayG_upd(0) <= p1_way_data_upd46_wayG and p1_wren_q; +rel_bixu46_wayG_upd(1) <= p0_way_data_upd46_wayG and p0_wren_q; +p0_way_data_upd46_wayH <= p0_congr_cl46_act_q and binv_wayH_upd3_q; +p1_way_data_upd46_wayH <= p1_congr_cl46_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu46_wayH_upd(0) <= p1_way_data_upd46_wayH and p1_wren_q; +rel_bixu46_wayH_upd(1) <= p0_way_data_upd46_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl47_m <= (ex5_congr_cl_q = tconv(47,6)); +p1_congr_cl47_m <= (relu_s_congr_cl_q = tconv(47,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl47_act_d <= p0_congr_cl47_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl47_act_d <= p1_congr_cl47_m and rel_port_wren_q; +congr_cl47_act <= p0_congr_cl47_act_q or p1_congr_cl47_act_q or congr_cl_all_act_q; +p0_way_data_upd47_wayA <= p0_congr_cl47_act_q and binv_wayA_upd3_q; +p1_way_data_upd47_wayA <= p1_congr_cl47_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu47_wayA_upd(0) <= p1_way_data_upd47_wayA and p1_wren_q; +rel_bixu47_wayA_upd(1) <= p0_way_data_upd47_wayA and p0_wren_q; +p0_way_data_upd47_wayB <= p0_congr_cl47_act_q and binv_wayB_upd3_q; +p1_way_data_upd47_wayB <= p1_congr_cl47_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu47_wayB_upd(0) <= p1_way_data_upd47_wayB and p1_wren_q; +rel_bixu47_wayB_upd(1) <= p0_way_data_upd47_wayB and p0_wren_q; +p0_way_data_upd47_wayC <= p0_congr_cl47_act_q and binv_wayC_upd3_q; +p1_way_data_upd47_wayC <= p1_congr_cl47_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu47_wayC_upd(0) <= p1_way_data_upd47_wayC and p1_wren_q; +rel_bixu47_wayC_upd(1) <= p0_way_data_upd47_wayC and p0_wren_q; +p0_way_data_upd47_wayD <= p0_congr_cl47_act_q and binv_wayD_upd3_q; +p1_way_data_upd47_wayD <= p1_congr_cl47_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu47_wayD_upd(0) <= p1_way_data_upd47_wayD and p1_wren_q; +rel_bixu47_wayD_upd(1) <= p0_way_data_upd47_wayD and p0_wren_q; +p0_way_data_upd47_wayE <= p0_congr_cl47_act_q and binv_wayE_upd3_q; +p1_way_data_upd47_wayE <= p1_congr_cl47_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu47_wayE_upd(0) <= p1_way_data_upd47_wayE and p1_wren_q; +rel_bixu47_wayE_upd(1) <= p0_way_data_upd47_wayE and p0_wren_q; +p0_way_data_upd47_wayF <= p0_congr_cl47_act_q and binv_wayF_upd3_q; +p1_way_data_upd47_wayF <= p1_congr_cl47_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu47_wayF_upd(0) <= p1_way_data_upd47_wayF and p1_wren_q; +rel_bixu47_wayF_upd(1) <= p0_way_data_upd47_wayF and p0_wren_q; +p0_way_data_upd47_wayG <= p0_congr_cl47_act_q and binv_wayG_upd3_q; +p1_way_data_upd47_wayG <= p1_congr_cl47_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu47_wayG_upd(0) <= p1_way_data_upd47_wayG and p1_wren_q; +rel_bixu47_wayG_upd(1) <= p0_way_data_upd47_wayG and p0_wren_q; +p0_way_data_upd47_wayH <= p0_congr_cl47_act_q and binv_wayH_upd3_q; +p1_way_data_upd47_wayH <= p1_congr_cl47_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu47_wayH_upd(0) <= p1_way_data_upd47_wayH and p1_wren_q; +rel_bixu47_wayH_upd(1) <= p0_way_data_upd47_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl48_m <= (ex5_congr_cl_q = tconv(48,6)); +p1_congr_cl48_m <= (relu_s_congr_cl_q = tconv(48,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl48_act_d <= p0_congr_cl48_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl48_act_d <= p1_congr_cl48_m and rel_port_wren_q; +congr_cl48_act <= p0_congr_cl48_act_q or p1_congr_cl48_act_q or congr_cl_all_act_q; +p0_way_data_upd48_wayA <= p0_congr_cl48_act_q and binv_wayA_upd3_q; +p1_way_data_upd48_wayA <= p1_congr_cl48_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu48_wayA_upd(0) <= p1_way_data_upd48_wayA and p1_wren_q; +rel_bixu48_wayA_upd(1) <= p0_way_data_upd48_wayA and p0_wren_q; +p0_way_data_upd48_wayB <= p0_congr_cl48_act_q and binv_wayB_upd3_q; +p1_way_data_upd48_wayB <= p1_congr_cl48_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu48_wayB_upd(0) <= p1_way_data_upd48_wayB and p1_wren_q; +rel_bixu48_wayB_upd(1) <= p0_way_data_upd48_wayB and p0_wren_q; +p0_way_data_upd48_wayC <= p0_congr_cl48_act_q and binv_wayC_upd3_q; +p1_way_data_upd48_wayC <= p1_congr_cl48_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu48_wayC_upd(0) <= p1_way_data_upd48_wayC and p1_wren_q; +rel_bixu48_wayC_upd(1) <= p0_way_data_upd48_wayC and p0_wren_q; +p0_way_data_upd48_wayD <= p0_congr_cl48_act_q and binv_wayD_upd3_q; +p1_way_data_upd48_wayD <= p1_congr_cl48_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu48_wayD_upd(0) <= p1_way_data_upd48_wayD and p1_wren_q; +rel_bixu48_wayD_upd(1) <= p0_way_data_upd48_wayD and p0_wren_q; +p0_way_data_upd48_wayE <= p0_congr_cl48_act_q and binv_wayE_upd3_q; +p1_way_data_upd48_wayE <= p1_congr_cl48_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu48_wayE_upd(0) <= p1_way_data_upd48_wayE and p1_wren_q; +rel_bixu48_wayE_upd(1) <= p0_way_data_upd48_wayE and p0_wren_q; +p0_way_data_upd48_wayF <= p0_congr_cl48_act_q and binv_wayF_upd3_q; +p1_way_data_upd48_wayF <= p1_congr_cl48_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu48_wayF_upd(0) <= p1_way_data_upd48_wayF and p1_wren_q; +rel_bixu48_wayF_upd(1) <= p0_way_data_upd48_wayF and p0_wren_q; +p0_way_data_upd48_wayG <= p0_congr_cl48_act_q and binv_wayG_upd3_q; +p1_way_data_upd48_wayG <= p1_congr_cl48_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu48_wayG_upd(0) <= p1_way_data_upd48_wayG and p1_wren_q; +rel_bixu48_wayG_upd(1) <= p0_way_data_upd48_wayG and p0_wren_q; +p0_way_data_upd48_wayH <= p0_congr_cl48_act_q and binv_wayH_upd3_q; +p1_way_data_upd48_wayH <= p1_congr_cl48_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu48_wayH_upd(0) <= p1_way_data_upd48_wayH and p1_wren_q; +rel_bixu48_wayH_upd(1) <= p0_way_data_upd48_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl49_m <= (ex5_congr_cl_q = tconv(49,6)); +p1_congr_cl49_m <= (relu_s_congr_cl_q = tconv(49,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl49_act_d <= p0_congr_cl49_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl49_act_d <= p1_congr_cl49_m and rel_port_wren_q; +congr_cl49_act <= p0_congr_cl49_act_q or p1_congr_cl49_act_q or congr_cl_all_act_q; +p0_way_data_upd49_wayA <= p0_congr_cl49_act_q and binv_wayA_upd3_q; +p1_way_data_upd49_wayA <= p1_congr_cl49_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu49_wayA_upd(0) <= p1_way_data_upd49_wayA and p1_wren_q; +rel_bixu49_wayA_upd(1) <= p0_way_data_upd49_wayA and p0_wren_q; +p0_way_data_upd49_wayB <= p0_congr_cl49_act_q and binv_wayB_upd3_q; +p1_way_data_upd49_wayB <= p1_congr_cl49_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu49_wayB_upd(0) <= p1_way_data_upd49_wayB and p1_wren_q; +rel_bixu49_wayB_upd(1) <= p0_way_data_upd49_wayB and p0_wren_q; +p0_way_data_upd49_wayC <= p0_congr_cl49_act_q and binv_wayC_upd3_q; +p1_way_data_upd49_wayC <= p1_congr_cl49_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu49_wayC_upd(0) <= p1_way_data_upd49_wayC and p1_wren_q; +rel_bixu49_wayC_upd(1) <= p0_way_data_upd49_wayC and p0_wren_q; +p0_way_data_upd49_wayD <= p0_congr_cl49_act_q and binv_wayD_upd3_q; +p1_way_data_upd49_wayD <= p1_congr_cl49_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu49_wayD_upd(0) <= p1_way_data_upd49_wayD and p1_wren_q; +rel_bixu49_wayD_upd(1) <= p0_way_data_upd49_wayD and p0_wren_q; +p0_way_data_upd49_wayE <= p0_congr_cl49_act_q and binv_wayE_upd3_q; +p1_way_data_upd49_wayE <= p1_congr_cl49_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu49_wayE_upd(0) <= p1_way_data_upd49_wayE and p1_wren_q; +rel_bixu49_wayE_upd(1) <= p0_way_data_upd49_wayE and p0_wren_q; +p0_way_data_upd49_wayF <= p0_congr_cl49_act_q and binv_wayF_upd3_q; +p1_way_data_upd49_wayF <= p1_congr_cl49_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu49_wayF_upd(0) <= p1_way_data_upd49_wayF and p1_wren_q; +rel_bixu49_wayF_upd(1) <= p0_way_data_upd49_wayF and p0_wren_q; +p0_way_data_upd49_wayG <= p0_congr_cl49_act_q and binv_wayG_upd3_q; +p1_way_data_upd49_wayG <= p1_congr_cl49_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu49_wayG_upd(0) <= p1_way_data_upd49_wayG and p1_wren_q; +rel_bixu49_wayG_upd(1) <= p0_way_data_upd49_wayG and p0_wren_q; +p0_way_data_upd49_wayH <= p0_congr_cl49_act_q and binv_wayH_upd3_q; +p1_way_data_upd49_wayH <= p1_congr_cl49_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu49_wayH_upd(0) <= p1_way_data_upd49_wayH and p1_wren_q; +rel_bixu49_wayH_upd(1) <= p0_way_data_upd49_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl50_m <= (ex5_congr_cl_q = tconv(50,6)); +p1_congr_cl50_m <= (relu_s_congr_cl_q = tconv(50,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl50_act_d <= p0_congr_cl50_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl50_act_d <= p1_congr_cl50_m and rel_port_wren_q; +congr_cl50_act <= p0_congr_cl50_act_q or p1_congr_cl50_act_q or congr_cl_all_act_q; +p0_way_data_upd50_wayA <= p0_congr_cl50_act_q and binv_wayA_upd3_q; +p1_way_data_upd50_wayA <= p1_congr_cl50_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu50_wayA_upd(0) <= p1_way_data_upd50_wayA and p1_wren_q; +rel_bixu50_wayA_upd(1) <= p0_way_data_upd50_wayA and p0_wren_q; +p0_way_data_upd50_wayB <= p0_congr_cl50_act_q and binv_wayB_upd3_q; +p1_way_data_upd50_wayB <= p1_congr_cl50_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu50_wayB_upd(0) <= p1_way_data_upd50_wayB and p1_wren_q; +rel_bixu50_wayB_upd(1) <= p0_way_data_upd50_wayB and p0_wren_q; +p0_way_data_upd50_wayC <= p0_congr_cl50_act_q and binv_wayC_upd3_q; +p1_way_data_upd50_wayC <= p1_congr_cl50_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu50_wayC_upd(0) <= p1_way_data_upd50_wayC and p1_wren_q; +rel_bixu50_wayC_upd(1) <= p0_way_data_upd50_wayC and p0_wren_q; +p0_way_data_upd50_wayD <= p0_congr_cl50_act_q and binv_wayD_upd3_q; +p1_way_data_upd50_wayD <= p1_congr_cl50_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu50_wayD_upd(0) <= p1_way_data_upd50_wayD and p1_wren_q; +rel_bixu50_wayD_upd(1) <= p0_way_data_upd50_wayD and p0_wren_q; +p0_way_data_upd50_wayE <= p0_congr_cl50_act_q and binv_wayE_upd3_q; +p1_way_data_upd50_wayE <= p1_congr_cl50_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu50_wayE_upd(0) <= p1_way_data_upd50_wayE and p1_wren_q; +rel_bixu50_wayE_upd(1) <= p0_way_data_upd50_wayE and p0_wren_q; +p0_way_data_upd50_wayF <= p0_congr_cl50_act_q and binv_wayF_upd3_q; +p1_way_data_upd50_wayF <= p1_congr_cl50_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu50_wayF_upd(0) <= p1_way_data_upd50_wayF and p1_wren_q; +rel_bixu50_wayF_upd(1) <= p0_way_data_upd50_wayF and p0_wren_q; +p0_way_data_upd50_wayG <= p0_congr_cl50_act_q and binv_wayG_upd3_q; +p1_way_data_upd50_wayG <= p1_congr_cl50_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu50_wayG_upd(0) <= p1_way_data_upd50_wayG and p1_wren_q; +rel_bixu50_wayG_upd(1) <= p0_way_data_upd50_wayG and p0_wren_q; +p0_way_data_upd50_wayH <= p0_congr_cl50_act_q and binv_wayH_upd3_q; +p1_way_data_upd50_wayH <= p1_congr_cl50_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu50_wayH_upd(0) <= p1_way_data_upd50_wayH and p1_wren_q; +rel_bixu50_wayH_upd(1) <= p0_way_data_upd50_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl51_m <= (ex5_congr_cl_q = tconv(51,6)); +p1_congr_cl51_m <= (relu_s_congr_cl_q = tconv(51,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl51_act_d <= p0_congr_cl51_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl51_act_d <= p1_congr_cl51_m and rel_port_wren_q; +congr_cl51_act <= p0_congr_cl51_act_q or p1_congr_cl51_act_q or congr_cl_all_act_q; +p0_way_data_upd51_wayA <= p0_congr_cl51_act_q and binv_wayA_upd3_q; +p1_way_data_upd51_wayA <= p1_congr_cl51_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu51_wayA_upd(0) <= p1_way_data_upd51_wayA and p1_wren_q; +rel_bixu51_wayA_upd(1) <= p0_way_data_upd51_wayA and p0_wren_q; +p0_way_data_upd51_wayB <= p0_congr_cl51_act_q and binv_wayB_upd3_q; +p1_way_data_upd51_wayB <= p1_congr_cl51_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu51_wayB_upd(0) <= p1_way_data_upd51_wayB and p1_wren_q; +rel_bixu51_wayB_upd(1) <= p0_way_data_upd51_wayB and p0_wren_q; +p0_way_data_upd51_wayC <= p0_congr_cl51_act_q and binv_wayC_upd3_q; +p1_way_data_upd51_wayC <= p1_congr_cl51_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu51_wayC_upd(0) <= p1_way_data_upd51_wayC and p1_wren_q; +rel_bixu51_wayC_upd(1) <= p0_way_data_upd51_wayC and p0_wren_q; +p0_way_data_upd51_wayD <= p0_congr_cl51_act_q and binv_wayD_upd3_q; +p1_way_data_upd51_wayD <= p1_congr_cl51_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu51_wayD_upd(0) <= p1_way_data_upd51_wayD and p1_wren_q; +rel_bixu51_wayD_upd(1) <= p0_way_data_upd51_wayD and p0_wren_q; +p0_way_data_upd51_wayE <= p0_congr_cl51_act_q and binv_wayE_upd3_q; +p1_way_data_upd51_wayE <= p1_congr_cl51_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu51_wayE_upd(0) <= p1_way_data_upd51_wayE and p1_wren_q; +rel_bixu51_wayE_upd(1) <= p0_way_data_upd51_wayE and p0_wren_q; +p0_way_data_upd51_wayF <= p0_congr_cl51_act_q and binv_wayF_upd3_q; +p1_way_data_upd51_wayF <= p1_congr_cl51_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu51_wayF_upd(0) <= p1_way_data_upd51_wayF and p1_wren_q; +rel_bixu51_wayF_upd(1) <= p0_way_data_upd51_wayF and p0_wren_q; +p0_way_data_upd51_wayG <= p0_congr_cl51_act_q and binv_wayG_upd3_q; +p1_way_data_upd51_wayG <= p1_congr_cl51_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu51_wayG_upd(0) <= p1_way_data_upd51_wayG and p1_wren_q; +rel_bixu51_wayG_upd(1) <= p0_way_data_upd51_wayG and p0_wren_q; +p0_way_data_upd51_wayH <= p0_congr_cl51_act_q and binv_wayH_upd3_q; +p1_way_data_upd51_wayH <= p1_congr_cl51_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu51_wayH_upd(0) <= p1_way_data_upd51_wayH and p1_wren_q; +rel_bixu51_wayH_upd(1) <= p0_way_data_upd51_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl52_m <= (ex5_congr_cl_q = tconv(52,6)); +p1_congr_cl52_m <= (relu_s_congr_cl_q = tconv(52,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl52_act_d <= p0_congr_cl52_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl52_act_d <= p1_congr_cl52_m and rel_port_wren_q; +congr_cl52_act <= p0_congr_cl52_act_q or p1_congr_cl52_act_q or congr_cl_all_act_q; +p0_way_data_upd52_wayA <= p0_congr_cl52_act_q and binv_wayA_upd3_q; +p1_way_data_upd52_wayA <= p1_congr_cl52_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu52_wayA_upd(0) <= p1_way_data_upd52_wayA and p1_wren_q; +rel_bixu52_wayA_upd(1) <= p0_way_data_upd52_wayA and p0_wren_q; +p0_way_data_upd52_wayB <= p0_congr_cl52_act_q and binv_wayB_upd3_q; +p1_way_data_upd52_wayB <= p1_congr_cl52_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu52_wayB_upd(0) <= p1_way_data_upd52_wayB and p1_wren_q; +rel_bixu52_wayB_upd(1) <= p0_way_data_upd52_wayB and p0_wren_q; +p0_way_data_upd52_wayC <= p0_congr_cl52_act_q and binv_wayC_upd3_q; +p1_way_data_upd52_wayC <= p1_congr_cl52_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu52_wayC_upd(0) <= p1_way_data_upd52_wayC and p1_wren_q; +rel_bixu52_wayC_upd(1) <= p0_way_data_upd52_wayC and p0_wren_q; +p0_way_data_upd52_wayD <= p0_congr_cl52_act_q and binv_wayD_upd3_q; +p1_way_data_upd52_wayD <= p1_congr_cl52_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu52_wayD_upd(0) <= p1_way_data_upd52_wayD and p1_wren_q; +rel_bixu52_wayD_upd(1) <= p0_way_data_upd52_wayD and p0_wren_q; +p0_way_data_upd52_wayE <= p0_congr_cl52_act_q and binv_wayE_upd3_q; +p1_way_data_upd52_wayE <= p1_congr_cl52_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu52_wayE_upd(0) <= p1_way_data_upd52_wayE and p1_wren_q; +rel_bixu52_wayE_upd(1) <= p0_way_data_upd52_wayE and p0_wren_q; +p0_way_data_upd52_wayF <= p0_congr_cl52_act_q and binv_wayF_upd3_q; +p1_way_data_upd52_wayF <= p1_congr_cl52_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu52_wayF_upd(0) <= p1_way_data_upd52_wayF and p1_wren_q; +rel_bixu52_wayF_upd(1) <= p0_way_data_upd52_wayF and p0_wren_q; +p0_way_data_upd52_wayG <= p0_congr_cl52_act_q and binv_wayG_upd3_q; +p1_way_data_upd52_wayG <= p1_congr_cl52_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu52_wayG_upd(0) <= p1_way_data_upd52_wayG and p1_wren_q; +rel_bixu52_wayG_upd(1) <= p0_way_data_upd52_wayG and p0_wren_q; +p0_way_data_upd52_wayH <= p0_congr_cl52_act_q and binv_wayH_upd3_q; +p1_way_data_upd52_wayH <= p1_congr_cl52_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu52_wayH_upd(0) <= p1_way_data_upd52_wayH and p1_wren_q; +rel_bixu52_wayH_upd(1) <= p0_way_data_upd52_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl53_m <= (ex5_congr_cl_q = tconv(53,6)); +p1_congr_cl53_m <= (relu_s_congr_cl_q = tconv(53,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl53_act_d <= p0_congr_cl53_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl53_act_d <= p1_congr_cl53_m and rel_port_wren_q; +congr_cl53_act <= p0_congr_cl53_act_q or p1_congr_cl53_act_q or congr_cl_all_act_q; +p0_way_data_upd53_wayA <= p0_congr_cl53_act_q and binv_wayA_upd3_q; +p1_way_data_upd53_wayA <= p1_congr_cl53_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu53_wayA_upd(0) <= p1_way_data_upd53_wayA and p1_wren_q; +rel_bixu53_wayA_upd(1) <= p0_way_data_upd53_wayA and p0_wren_q; +p0_way_data_upd53_wayB <= p0_congr_cl53_act_q and binv_wayB_upd3_q; +p1_way_data_upd53_wayB <= p1_congr_cl53_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu53_wayB_upd(0) <= p1_way_data_upd53_wayB and p1_wren_q; +rel_bixu53_wayB_upd(1) <= p0_way_data_upd53_wayB and p0_wren_q; +p0_way_data_upd53_wayC <= p0_congr_cl53_act_q and binv_wayC_upd3_q; +p1_way_data_upd53_wayC <= p1_congr_cl53_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu53_wayC_upd(0) <= p1_way_data_upd53_wayC and p1_wren_q; +rel_bixu53_wayC_upd(1) <= p0_way_data_upd53_wayC and p0_wren_q; +p0_way_data_upd53_wayD <= p0_congr_cl53_act_q and binv_wayD_upd3_q; +p1_way_data_upd53_wayD <= p1_congr_cl53_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu53_wayD_upd(0) <= p1_way_data_upd53_wayD and p1_wren_q; +rel_bixu53_wayD_upd(1) <= p0_way_data_upd53_wayD and p0_wren_q; +p0_way_data_upd53_wayE <= p0_congr_cl53_act_q and binv_wayE_upd3_q; +p1_way_data_upd53_wayE <= p1_congr_cl53_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu53_wayE_upd(0) <= p1_way_data_upd53_wayE and p1_wren_q; +rel_bixu53_wayE_upd(1) <= p0_way_data_upd53_wayE and p0_wren_q; +p0_way_data_upd53_wayF <= p0_congr_cl53_act_q and binv_wayF_upd3_q; +p1_way_data_upd53_wayF <= p1_congr_cl53_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu53_wayF_upd(0) <= p1_way_data_upd53_wayF and p1_wren_q; +rel_bixu53_wayF_upd(1) <= p0_way_data_upd53_wayF and p0_wren_q; +p0_way_data_upd53_wayG <= p0_congr_cl53_act_q and binv_wayG_upd3_q; +p1_way_data_upd53_wayG <= p1_congr_cl53_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu53_wayG_upd(0) <= p1_way_data_upd53_wayG and p1_wren_q; +rel_bixu53_wayG_upd(1) <= p0_way_data_upd53_wayG and p0_wren_q; +p0_way_data_upd53_wayH <= p0_congr_cl53_act_q and binv_wayH_upd3_q; +p1_way_data_upd53_wayH <= p1_congr_cl53_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu53_wayH_upd(0) <= p1_way_data_upd53_wayH and p1_wren_q; +rel_bixu53_wayH_upd(1) <= p0_way_data_upd53_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl54_m <= (ex5_congr_cl_q = tconv(54,6)); +p1_congr_cl54_m <= (relu_s_congr_cl_q = tconv(54,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl54_act_d <= p0_congr_cl54_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl54_act_d <= p1_congr_cl54_m and rel_port_wren_q; +congr_cl54_act <= p0_congr_cl54_act_q or p1_congr_cl54_act_q or congr_cl_all_act_q; +p0_way_data_upd54_wayA <= p0_congr_cl54_act_q and binv_wayA_upd3_q; +p1_way_data_upd54_wayA <= p1_congr_cl54_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu54_wayA_upd(0) <= p1_way_data_upd54_wayA and p1_wren_q; +rel_bixu54_wayA_upd(1) <= p0_way_data_upd54_wayA and p0_wren_q; +p0_way_data_upd54_wayB <= p0_congr_cl54_act_q and binv_wayB_upd3_q; +p1_way_data_upd54_wayB <= p1_congr_cl54_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu54_wayB_upd(0) <= p1_way_data_upd54_wayB and p1_wren_q; +rel_bixu54_wayB_upd(1) <= p0_way_data_upd54_wayB and p0_wren_q; +p0_way_data_upd54_wayC <= p0_congr_cl54_act_q and binv_wayC_upd3_q; +p1_way_data_upd54_wayC <= p1_congr_cl54_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu54_wayC_upd(0) <= p1_way_data_upd54_wayC and p1_wren_q; +rel_bixu54_wayC_upd(1) <= p0_way_data_upd54_wayC and p0_wren_q; +p0_way_data_upd54_wayD <= p0_congr_cl54_act_q and binv_wayD_upd3_q; +p1_way_data_upd54_wayD <= p1_congr_cl54_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu54_wayD_upd(0) <= p1_way_data_upd54_wayD and p1_wren_q; +rel_bixu54_wayD_upd(1) <= p0_way_data_upd54_wayD and p0_wren_q; +p0_way_data_upd54_wayE <= p0_congr_cl54_act_q and binv_wayE_upd3_q; +p1_way_data_upd54_wayE <= p1_congr_cl54_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu54_wayE_upd(0) <= p1_way_data_upd54_wayE and p1_wren_q; +rel_bixu54_wayE_upd(1) <= p0_way_data_upd54_wayE and p0_wren_q; +p0_way_data_upd54_wayF <= p0_congr_cl54_act_q and binv_wayF_upd3_q; +p1_way_data_upd54_wayF <= p1_congr_cl54_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu54_wayF_upd(0) <= p1_way_data_upd54_wayF and p1_wren_q; +rel_bixu54_wayF_upd(1) <= p0_way_data_upd54_wayF and p0_wren_q; +p0_way_data_upd54_wayG <= p0_congr_cl54_act_q and binv_wayG_upd3_q; +p1_way_data_upd54_wayG <= p1_congr_cl54_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu54_wayG_upd(0) <= p1_way_data_upd54_wayG and p1_wren_q; +rel_bixu54_wayG_upd(1) <= p0_way_data_upd54_wayG and p0_wren_q; +p0_way_data_upd54_wayH <= p0_congr_cl54_act_q and binv_wayH_upd3_q; +p1_way_data_upd54_wayH <= p1_congr_cl54_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu54_wayH_upd(0) <= p1_way_data_upd54_wayH and p1_wren_q; +rel_bixu54_wayH_upd(1) <= p0_way_data_upd54_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl55_m <= (ex5_congr_cl_q = tconv(55,6)); +p1_congr_cl55_m <= (relu_s_congr_cl_q = tconv(55,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl55_act_d <= p0_congr_cl55_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl55_act_d <= p1_congr_cl55_m and rel_port_wren_q; +congr_cl55_act <= p0_congr_cl55_act_q or p1_congr_cl55_act_q or congr_cl_all_act_q; +p0_way_data_upd55_wayA <= p0_congr_cl55_act_q and binv_wayA_upd3_q; +p1_way_data_upd55_wayA <= p1_congr_cl55_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu55_wayA_upd(0) <= p1_way_data_upd55_wayA and p1_wren_q; +rel_bixu55_wayA_upd(1) <= p0_way_data_upd55_wayA and p0_wren_q; +p0_way_data_upd55_wayB <= p0_congr_cl55_act_q and binv_wayB_upd3_q; +p1_way_data_upd55_wayB <= p1_congr_cl55_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu55_wayB_upd(0) <= p1_way_data_upd55_wayB and p1_wren_q; +rel_bixu55_wayB_upd(1) <= p0_way_data_upd55_wayB and p0_wren_q; +p0_way_data_upd55_wayC <= p0_congr_cl55_act_q and binv_wayC_upd3_q; +p1_way_data_upd55_wayC <= p1_congr_cl55_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu55_wayC_upd(0) <= p1_way_data_upd55_wayC and p1_wren_q; +rel_bixu55_wayC_upd(1) <= p0_way_data_upd55_wayC and p0_wren_q; +p0_way_data_upd55_wayD <= p0_congr_cl55_act_q and binv_wayD_upd3_q; +p1_way_data_upd55_wayD <= p1_congr_cl55_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu55_wayD_upd(0) <= p1_way_data_upd55_wayD and p1_wren_q; +rel_bixu55_wayD_upd(1) <= p0_way_data_upd55_wayD and p0_wren_q; +p0_way_data_upd55_wayE <= p0_congr_cl55_act_q and binv_wayE_upd3_q; +p1_way_data_upd55_wayE <= p1_congr_cl55_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu55_wayE_upd(0) <= p1_way_data_upd55_wayE and p1_wren_q; +rel_bixu55_wayE_upd(1) <= p0_way_data_upd55_wayE and p0_wren_q; +p0_way_data_upd55_wayF <= p0_congr_cl55_act_q and binv_wayF_upd3_q; +p1_way_data_upd55_wayF <= p1_congr_cl55_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu55_wayF_upd(0) <= p1_way_data_upd55_wayF and p1_wren_q; +rel_bixu55_wayF_upd(1) <= p0_way_data_upd55_wayF and p0_wren_q; +p0_way_data_upd55_wayG <= p0_congr_cl55_act_q and binv_wayG_upd3_q; +p1_way_data_upd55_wayG <= p1_congr_cl55_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu55_wayG_upd(0) <= p1_way_data_upd55_wayG and p1_wren_q; +rel_bixu55_wayG_upd(1) <= p0_way_data_upd55_wayG and p0_wren_q; +p0_way_data_upd55_wayH <= p0_congr_cl55_act_q and binv_wayH_upd3_q; +p1_way_data_upd55_wayH <= p1_congr_cl55_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu55_wayH_upd(0) <= p1_way_data_upd55_wayH and p1_wren_q; +rel_bixu55_wayH_upd(1) <= p0_way_data_upd55_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl56_m <= (ex5_congr_cl_q = tconv(56,6)); +p1_congr_cl56_m <= (relu_s_congr_cl_q = tconv(56,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl56_act_d <= p0_congr_cl56_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl56_act_d <= p1_congr_cl56_m and rel_port_wren_q; +congr_cl56_act <= p0_congr_cl56_act_q or p1_congr_cl56_act_q or congr_cl_all_act_q; +p0_way_data_upd56_wayA <= p0_congr_cl56_act_q and binv_wayA_upd3_q; +p1_way_data_upd56_wayA <= p1_congr_cl56_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu56_wayA_upd(0) <= p1_way_data_upd56_wayA and p1_wren_q; +rel_bixu56_wayA_upd(1) <= p0_way_data_upd56_wayA and p0_wren_q; +p0_way_data_upd56_wayB <= p0_congr_cl56_act_q and binv_wayB_upd3_q; +p1_way_data_upd56_wayB <= p1_congr_cl56_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu56_wayB_upd(0) <= p1_way_data_upd56_wayB and p1_wren_q; +rel_bixu56_wayB_upd(1) <= p0_way_data_upd56_wayB and p0_wren_q; +p0_way_data_upd56_wayC <= p0_congr_cl56_act_q and binv_wayC_upd3_q; +p1_way_data_upd56_wayC <= p1_congr_cl56_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu56_wayC_upd(0) <= p1_way_data_upd56_wayC and p1_wren_q; +rel_bixu56_wayC_upd(1) <= p0_way_data_upd56_wayC and p0_wren_q; +p0_way_data_upd56_wayD <= p0_congr_cl56_act_q and binv_wayD_upd3_q; +p1_way_data_upd56_wayD <= p1_congr_cl56_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu56_wayD_upd(0) <= p1_way_data_upd56_wayD and p1_wren_q; +rel_bixu56_wayD_upd(1) <= p0_way_data_upd56_wayD and p0_wren_q; +p0_way_data_upd56_wayE <= p0_congr_cl56_act_q and binv_wayE_upd3_q; +p1_way_data_upd56_wayE <= p1_congr_cl56_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu56_wayE_upd(0) <= p1_way_data_upd56_wayE and p1_wren_q; +rel_bixu56_wayE_upd(1) <= p0_way_data_upd56_wayE and p0_wren_q; +p0_way_data_upd56_wayF <= p0_congr_cl56_act_q and binv_wayF_upd3_q; +p1_way_data_upd56_wayF <= p1_congr_cl56_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu56_wayF_upd(0) <= p1_way_data_upd56_wayF and p1_wren_q; +rel_bixu56_wayF_upd(1) <= p0_way_data_upd56_wayF and p0_wren_q; +p0_way_data_upd56_wayG <= p0_congr_cl56_act_q and binv_wayG_upd3_q; +p1_way_data_upd56_wayG <= p1_congr_cl56_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu56_wayG_upd(0) <= p1_way_data_upd56_wayG and p1_wren_q; +rel_bixu56_wayG_upd(1) <= p0_way_data_upd56_wayG and p0_wren_q; +p0_way_data_upd56_wayH <= p0_congr_cl56_act_q and binv_wayH_upd3_q; +p1_way_data_upd56_wayH <= p1_congr_cl56_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu56_wayH_upd(0) <= p1_way_data_upd56_wayH and p1_wren_q; +rel_bixu56_wayH_upd(1) <= p0_way_data_upd56_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl57_m <= (ex5_congr_cl_q = tconv(57,6)); +p1_congr_cl57_m <= (relu_s_congr_cl_q = tconv(57,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl57_act_d <= p0_congr_cl57_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl57_act_d <= p1_congr_cl57_m and rel_port_wren_q; +congr_cl57_act <= p0_congr_cl57_act_q or p1_congr_cl57_act_q or congr_cl_all_act_q; +p0_way_data_upd57_wayA <= p0_congr_cl57_act_q and binv_wayA_upd3_q; +p1_way_data_upd57_wayA <= p1_congr_cl57_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu57_wayA_upd(0) <= p1_way_data_upd57_wayA and p1_wren_q; +rel_bixu57_wayA_upd(1) <= p0_way_data_upd57_wayA and p0_wren_q; +p0_way_data_upd57_wayB <= p0_congr_cl57_act_q and binv_wayB_upd3_q; +p1_way_data_upd57_wayB <= p1_congr_cl57_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu57_wayB_upd(0) <= p1_way_data_upd57_wayB and p1_wren_q; +rel_bixu57_wayB_upd(1) <= p0_way_data_upd57_wayB and p0_wren_q; +p0_way_data_upd57_wayC <= p0_congr_cl57_act_q and binv_wayC_upd3_q; +p1_way_data_upd57_wayC <= p1_congr_cl57_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu57_wayC_upd(0) <= p1_way_data_upd57_wayC and p1_wren_q; +rel_bixu57_wayC_upd(1) <= p0_way_data_upd57_wayC and p0_wren_q; +p0_way_data_upd57_wayD <= p0_congr_cl57_act_q and binv_wayD_upd3_q; +p1_way_data_upd57_wayD <= p1_congr_cl57_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu57_wayD_upd(0) <= p1_way_data_upd57_wayD and p1_wren_q; +rel_bixu57_wayD_upd(1) <= p0_way_data_upd57_wayD and p0_wren_q; +p0_way_data_upd57_wayE <= p0_congr_cl57_act_q and binv_wayE_upd3_q; +p1_way_data_upd57_wayE <= p1_congr_cl57_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu57_wayE_upd(0) <= p1_way_data_upd57_wayE and p1_wren_q; +rel_bixu57_wayE_upd(1) <= p0_way_data_upd57_wayE and p0_wren_q; +p0_way_data_upd57_wayF <= p0_congr_cl57_act_q and binv_wayF_upd3_q; +p1_way_data_upd57_wayF <= p1_congr_cl57_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu57_wayF_upd(0) <= p1_way_data_upd57_wayF and p1_wren_q; +rel_bixu57_wayF_upd(1) <= p0_way_data_upd57_wayF and p0_wren_q; +p0_way_data_upd57_wayG <= p0_congr_cl57_act_q and binv_wayG_upd3_q; +p1_way_data_upd57_wayG <= p1_congr_cl57_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu57_wayG_upd(0) <= p1_way_data_upd57_wayG and p1_wren_q; +rel_bixu57_wayG_upd(1) <= p0_way_data_upd57_wayG and p0_wren_q; +p0_way_data_upd57_wayH <= p0_congr_cl57_act_q and binv_wayH_upd3_q; +p1_way_data_upd57_wayH <= p1_congr_cl57_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu57_wayH_upd(0) <= p1_way_data_upd57_wayH and p1_wren_q; +rel_bixu57_wayH_upd(1) <= p0_way_data_upd57_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl58_m <= (ex5_congr_cl_q = tconv(58,6)); +p1_congr_cl58_m <= (relu_s_congr_cl_q = tconv(58,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl58_act_d <= p0_congr_cl58_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl58_act_d <= p1_congr_cl58_m and rel_port_wren_q; +congr_cl58_act <= p0_congr_cl58_act_q or p1_congr_cl58_act_q or congr_cl_all_act_q; +p0_way_data_upd58_wayA <= p0_congr_cl58_act_q and binv_wayA_upd3_q; +p1_way_data_upd58_wayA <= p1_congr_cl58_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu58_wayA_upd(0) <= p1_way_data_upd58_wayA and p1_wren_q; +rel_bixu58_wayA_upd(1) <= p0_way_data_upd58_wayA and p0_wren_q; +p0_way_data_upd58_wayB <= p0_congr_cl58_act_q and binv_wayB_upd3_q; +p1_way_data_upd58_wayB <= p1_congr_cl58_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu58_wayB_upd(0) <= p1_way_data_upd58_wayB and p1_wren_q; +rel_bixu58_wayB_upd(1) <= p0_way_data_upd58_wayB and p0_wren_q; +p0_way_data_upd58_wayC <= p0_congr_cl58_act_q and binv_wayC_upd3_q; +p1_way_data_upd58_wayC <= p1_congr_cl58_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu58_wayC_upd(0) <= p1_way_data_upd58_wayC and p1_wren_q; +rel_bixu58_wayC_upd(1) <= p0_way_data_upd58_wayC and p0_wren_q; +p0_way_data_upd58_wayD <= p0_congr_cl58_act_q and binv_wayD_upd3_q; +p1_way_data_upd58_wayD <= p1_congr_cl58_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu58_wayD_upd(0) <= p1_way_data_upd58_wayD and p1_wren_q; +rel_bixu58_wayD_upd(1) <= p0_way_data_upd58_wayD and p0_wren_q; +p0_way_data_upd58_wayE <= p0_congr_cl58_act_q and binv_wayE_upd3_q; +p1_way_data_upd58_wayE <= p1_congr_cl58_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu58_wayE_upd(0) <= p1_way_data_upd58_wayE and p1_wren_q; +rel_bixu58_wayE_upd(1) <= p0_way_data_upd58_wayE and p0_wren_q; +p0_way_data_upd58_wayF <= p0_congr_cl58_act_q and binv_wayF_upd3_q; +p1_way_data_upd58_wayF <= p1_congr_cl58_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu58_wayF_upd(0) <= p1_way_data_upd58_wayF and p1_wren_q; +rel_bixu58_wayF_upd(1) <= p0_way_data_upd58_wayF and p0_wren_q; +p0_way_data_upd58_wayG <= p0_congr_cl58_act_q and binv_wayG_upd3_q; +p1_way_data_upd58_wayG <= p1_congr_cl58_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu58_wayG_upd(0) <= p1_way_data_upd58_wayG and p1_wren_q; +rel_bixu58_wayG_upd(1) <= p0_way_data_upd58_wayG and p0_wren_q; +p0_way_data_upd58_wayH <= p0_congr_cl58_act_q and binv_wayH_upd3_q; +p1_way_data_upd58_wayH <= p1_congr_cl58_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu58_wayH_upd(0) <= p1_way_data_upd58_wayH and p1_wren_q; +rel_bixu58_wayH_upd(1) <= p0_way_data_upd58_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl59_m <= (ex5_congr_cl_q = tconv(59,6)); +p1_congr_cl59_m <= (relu_s_congr_cl_q = tconv(59,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl59_act_d <= p0_congr_cl59_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl59_act_d <= p1_congr_cl59_m and rel_port_wren_q; +congr_cl59_act <= p0_congr_cl59_act_q or p1_congr_cl59_act_q or congr_cl_all_act_q; +p0_way_data_upd59_wayA <= p0_congr_cl59_act_q and binv_wayA_upd3_q; +p1_way_data_upd59_wayA <= p1_congr_cl59_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu59_wayA_upd(0) <= p1_way_data_upd59_wayA and p1_wren_q; +rel_bixu59_wayA_upd(1) <= p0_way_data_upd59_wayA and p0_wren_q; +p0_way_data_upd59_wayB <= p0_congr_cl59_act_q and binv_wayB_upd3_q; +p1_way_data_upd59_wayB <= p1_congr_cl59_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu59_wayB_upd(0) <= p1_way_data_upd59_wayB and p1_wren_q; +rel_bixu59_wayB_upd(1) <= p0_way_data_upd59_wayB and p0_wren_q; +p0_way_data_upd59_wayC <= p0_congr_cl59_act_q and binv_wayC_upd3_q; +p1_way_data_upd59_wayC <= p1_congr_cl59_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu59_wayC_upd(0) <= p1_way_data_upd59_wayC and p1_wren_q; +rel_bixu59_wayC_upd(1) <= p0_way_data_upd59_wayC and p0_wren_q; +p0_way_data_upd59_wayD <= p0_congr_cl59_act_q and binv_wayD_upd3_q; +p1_way_data_upd59_wayD <= p1_congr_cl59_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu59_wayD_upd(0) <= p1_way_data_upd59_wayD and p1_wren_q; +rel_bixu59_wayD_upd(1) <= p0_way_data_upd59_wayD and p0_wren_q; +p0_way_data_upd59_wayE <= p0_congr_cl59_act_q and binv_wayE_upd3_q; +p1_way_data_upd59_wayE <= p1_congr_cl59_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu59_wayE_upd(0) <= p1_way_data_upd59_wayE and p1_wren_q; +rel_bixu59_wayE_upd(1) <= p0_way_data_upd59_wayE and p0_wren_q; +p0_way_data_upd59_wayF <= p0_congr_cl59_act_q and binv_wayF_upd3_q; +p1_way_data_upd59_wayF <= p1_congr_cl59_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu59_wayF_upd(0) <= p1_way_data_upd59_wayF and p1_wren_q; +rel_bixu59_wayF_upd(1) <= p0_way_data_upd59_wayF and p0_wren_q; +p0_way_data_upd59_wayG <= p0_congr_cl59_act_q and binv_wayG_upd3_q; +p1_way_data_upd59_wayG <= p1_congr_cl59_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu59_wayG_upd(0) <= p1_way_data_upd59_wayG and p1_wren_q; +rel_bixu59_wayG_upd(1) <= p0_way_data_upd59_wayG and p0_wren_q; +p0_way_data_upd59_wayH <= p0_congr_cl59_act_q and binv_wayH_upd3_q; +p1_way_data_upd59_wayH <= p1_congr_cl59_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu59_wayH_upd(0) <= p1_way_data_upd59_wayH and p1_wren_q; +rel_bixu59_wayH_upd(1) <= p0_way_data_upd59_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl60_m <= (ex5_congr_cl_q = tconv(60,6)); +p1_congr_cl60_m <= (relu_s_congr_cl_q = tconv(60,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl60_act_d <= p0_congr_cl60_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl60_act_d <= p1_congr_cl60_m and rel_port_wren_q; +congr_cl60_act <= p0_congr_cl60_act_q or p1_congr_cl60_act_q or congr_cl_all_act_q; +p0_way_data_upd60_wayA <= p0_congr_cl60_act_q and binv_wayA_upd3_q; +p1_way_data_upd60_wayA <= p1_congr_cl60_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu60_wayA_upd(0) <= p1_way_data_upd60_wayA and p1_wren_q; +rel_bixu60_wayA_upd(1) <= p0_way_data_upd60_wayA and p0_wren_q; +p0_way_data_upd60_wayB <= p0_congr_cl60_act_q and binv_wayB_upd3_q; +p1_way_data_upd60_wayB <= p1_congr_cl60_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu60_wayB_upd(0) <= p1_way_data_upd60_wayB and p1_wren_q; +rel_bixu60_wayB_upd(1) <= p0_way_data_upd60_wayB and p0_wren_q; +p0_way_data_upd60_wayC <= p0_congr_cl60_act_q and binv_wayC_upd3_q; +p1_way_data_upd60_wayC <= p1_congr_cl60_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu60_wayC_upd(0) <= p1_way_data_upd60_wayC and p1_wren_q; +rel_bixu60_wayC_upd(1) <= p0_way_data_upd60_wayC and p0_wren_q; +p0_way_data_upd60_wayD <= p0_congr_cl60_act_q and binv_wayD_upd3_q; +p1_way_data_upd60_wayD <= p1_congr_cl60_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu60_wayD_upd(0) <= p1_way_data_upd60_wayD and p1_wren_q; +rel_bixu60_wayD_upd(1) <= p0_way_data_upd60_wayD and p0_wren_q; +p0_way_data_upd60_wayE <= p0_congr_cl60_act_q and binv_wayE_upd3_q; +p1_way_data_upd60_wayE <= p1_congr_cl60_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu60_wayE_upd(0) <= p1_way_data_upd60_wayE and p1_wren_q; +rel_bixu60_wayE_upd(1) <= p0_way_data_upd60_wayE and p0_wren_q; +p0_way_data_upd60_wayF <= p0_congr_cl60_act_q and binv_wayF_upd3_q; +p1_way_data_upd60_wayF <= p1_congr_cl60_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu60_wayF_upd(0) <= p1_way_data_upd60_wayF and p1_wren_q; +rel_bixu60_wayF_upd(1) <= p0_way_data_upd60_wayF and p0_wren_q; +p0_way_data_upd60_wayG <= p0_congr_cl60_act_q and binv_wayG_upd3_q; +p1_way_data_upd60_wayG <= p1_congr_cl60_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu60_wayG_upd(0) <= p1_way_data_upd60_wayG and p1_wren_q; +rel_bixu60_wayG_upd(1) <= p0_way_data_upd60_wayG and p0_wren_q; +p0_way_data_upd60_wayH <= p0_congr_cl60_act_q and binv_wayH_upd3_q; +p1_way_data_upd60_wayH <= p1_congr_cl60_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu60_wayH_upd(0) <= p1_way_data_upd60_wayH and p1_wren_q; +rel_bixu60_wayH_upd(1) <= p0_way_data_upd60_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl61_m <= (ex5_congr_cl_q = tconv(61,6)); +p1_congr_cl61_m <= (relu_s_congr_cl_q = tconv(61,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl61_act_d <= p0_congr_cl61_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl61_act_d <= p1_congr_cl61_m and rel_port_wren_q; +congr_cl61_act <= p0_congr_cl61_act_q or p1_congr_cl61_act_q or congr_cl_all_act_q; +p0_way_data_upd61_wayA <= p0_congr_cl61_act_q and binv_wayA_upd3_q; +p1_way_data_upd61_wayA <= p1_congr_cl61_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu61_wayA_upd(0) <= p1_way_data_upd61_wayA and p1_wren_q; +rel_bixu61_wayA_upd(1) <= p0_way_data_upd61_wayA and p0_wren_q; +p0_way_data_upd61_wayB <= p0_congr_cl61_act_q and binv_wayB_upd3_q; +p1_way_data_upd61_wayB <= p1_congr_cl61_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu61_wayB_upd(0) <= p1_way_data_upd61_wayB and p1_wren_q; +rel_bixu61_wayB_upd(1) <= p0_way_data_upd61_wayB and p0_wren_q; +p0_way_data_upd61_wayC <= p0_congr_cl61_act_q and binv_wayC_upd3_q; +p1_way_data_upd61_wayC <= p1_congr_cl61_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu61_wayC_upd(0) <= p1_way_data_upd61_wayC and p1_wren_q; +rel_bixu61_wayC_upd(1) <= p0_way_data_upd61_wayC and p0_wren_q; +p0_way_data_upd61_wayD <= p0_congr_cl61_act_q and binv_wayD_upd3_q; +p1_way_data_upd61_wayD <= p1_congr_cl61_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu61_wayD_upd(0) <= p1_way_data_upd61_wayD and p1_wren_q; +rel_bixu61_wayD_upd(1) <= p0_way_data_upd61_wayD and p0_wren_q; +p0_way_data_upd61_wayE <= p0_congr_cl61_act_q and binv_wayE_upd3_q; +p1_way_data_upd61_wayE <= p1_congr_cl61_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu61_wayE_upd(0) <= p1_way_data_upd61_wayE and p1_wren_q; +rel_bixu61_wayE_upd(1) <= p0_way_data_upd61_wayE and p0_wren_q; +p0_way_data_upd61_wayF <= p0_congr_cl61_act_q and binv_wayF_upd3_q; +p1_way_data_upd61_wayF <= p1_congr_cl61_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu61_wayF_upd(0) <= p1_way_data_upd61_wayF and p1_wren_q; +rel_bixu61_wayF_upd(1) <= p0_way_data_upd61_wayF and p0_wren_q; +p0_way_data_upd61_wayG <= p0_congr_cl61_act_q and binv_wayG_upd3_q; +p1_way_data_upd61_wayG <= p1_congr_cl61_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu61_wayG_upd(0) <= p1_way_data_upd61_wayG and p1_wren_q; +rel_bixu61_wayG_upd(1) <= p0_way_data_upd61_wayG and p0_wren_q; +p0_way_data_upd61_wayH <= p0_congr_cl61_act_q and binv_wayH_upd3_q; +p1_way_data_upd61_wayH <= p1_congr_cl61_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu61_wayH_upd(0) <= p1_way_data_upd61_wayH and p1_wren_q; +rel_bixu61_wayH_upd(1) <= p0_way_data_upd61_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl62_m <= (ex5_congr_cl_q = tconv(62,6)); +p1_congr_cl62_m <= (relu_s_congr_cl_q = tconv(62,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl62_act_d <= p0_congr_cl62_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl62_act_d <= p1_congr_cl62_m and rel_port_wren_q; +congr_cl62_act <= p0_congr_cl62_act_q or p1_congr_cl62_act_q or congr_cl_all_act_q; +p0_way_data_upd62_wayA <= p0_congr_cl62_act_q and binv_wayA_upd3_q; +p1_way_data_upd62_wayA <= p1_congr_cl62_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu62_wayA_upd(0) <= p1_way_data_upd62_wayA and p1_wren_q; +rel_bixu62_wayA_upd(1) <= p0_way_data_upd62_wayA and p0_wren_q; +p0_way_data_upd62_wayB <= p0_congr_cl62_act_q and binv_wayB_upd3_q; +p1_way_data_upd62_wayB <= p1_congr_cl62_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu62_wayB_upd(0) <= p1_way_data_upd62_wayB and p1_wren_q; +rel_bixu62_wayB_upd(1) <= p0_way_data_upd62_wayB and p0_wren_q; +p0_way_data_upd62_wayC <= p0_congr_cl62_act_q and binv_wayC_upd3_q; +p1_way_data_upd62_wayC <= p1_congr_cl62_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu62_wayC_upd(0) <= p1_way_data_upd62_wayC and p1_wren_q; +rel_bixu62_wayC_upd(1) <= p0_way_data_upd62_wayC and p0_wren_q; +p0_way_data_upd62_wayD <= p0_congr_cl62_act_q and binv_wayD_upd3_q; +p1_way_data_upd62_wayD <= p1_congr_cl62_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu62_wayD_upd(0) <= p1_way_data_upd62_wayD and p1_wren_q; +rel_bixu62_wayD_upd(1) <= p0_way_data_upd62_wayD and p0_wren_q; +p0_way_data_upd62_wayE <= p0_congr_cl62_act_q and binv_wayE_upd3_q; +p1_way_data_upd62_wayE <= p1_congr_cl62_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu62_wayE_upd(0) <= p1_way_data_upd62_wayE and p1_wren_q; +rel_bixu62_wayE_upd(1) <= p0_way_data_upd62_wayE and p0_wren_q; +p0_way_data_upd62_wayF <= p0_congr_cl62_act_q and binv_wayF_upd3_q; +p1_way_data_upd62_wayF <= p1_congr_cl62_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu62_wayF_upd(0) <= p1_way_data_upd62_wayF and p1_wren_q; +rel_bixu62_wayF_upd(1) <= p0_way_data_upd62_wayF and p0_wren_q; +p0_way_data_upd62_wayG <= p0_congr_cl62_act_q and binv_wayG_upd3_q; +p1_way_data_upd62_wayG <= p1_congr_cl62_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu62_wayG_upd(0) <= p1_way_data_upd62_wayG and p1_wren_q; +rel_bixu62_wayG_upd(1) <= p0_way_data_upd62_wayG and p0_wren_q; +p0_way_data_upd62_wayH <= p0_congr_cl62_act_q and binv_wayH_upd3_q; +p1_way_data_upd62_wayH <= p1_congr_cl62_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu62_wayH_upd(0) <= p1_way_data_upd62_wayH and p1_wren_q; +rel_bixu62_wayH_upd(1) <= p0_way_data_upd62_wayH and p0_wren_q; +-- Congruence Class Match +p0_congr_cl63_m <= (ex5_congr_cl_q = tconv(63,6)); +p1_congr_cl63_m <= (relu_s_congr_cl_q = tconv(63,6)); +-- Act Pin to Directory Latches for specific congruence class +p0_congr_cl63_act_d <= p0_congr_cl63_m and (back_inval_stg5_q or ex5_xuop_val_q or ex5_dir_err_val_q); +p1_congr_cl63_act_d <= p1_congr_cl63_m and rel_port_wren_q; +congr_cl63_act <= p0_congr_cl63_act_q or p1_congr_cl63_act_q or congr_cl_all_act_q; +p0_way_data_upd63_wayA <= p0_congr_cl63_act_q and binv_wayA_upd3_q; +p1_way_data_upd63_wayA <= p1_congr_cl63_act_q and reload_wayA_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu63_wayA_upd(0) <= p1_way_data_upd63_wayA and p1_wren_q; +rel_bixu63_wayA_upd(1) <= p0_way_data_upd63_wayA and p0_wren_q; +p0_way_data_upd63_wayB <= p0_congr_cl63_act_q and binv_wayB_upd3_q; +p1_way_data_upd63_wayB <= p1_congr_cl63_act_q and reload_wayB_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu63_wayB_upd(0) <= p1_way_data_upd63_wayB and p1_wren_q; +rel_bixu63_wayB_upd(1) <= p0_way_data_upd63_wayB and p0_wren_q; +p0_way_data_upd63_wayC <= p0_congr_cl63_act_q and binv_wayC_upd3_q; +p1_way_data_upd63_wayC <= p1_congr_cl63_act_q and reload_wayC_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu63_wayC_upd(0) <= p1_way_data_upd63_wayC and p1_wren_q; +rel_bixu63_wayC_upd(1) <= p0_way_data_upd63_wayC and p0_wren_q; +p0_way_data_upd63_wayD <= p0_congr_cl63_act_q and binv_wayD_upd3_q; +p1_way_data_upd63_wayD <= p1_congr_cl63_act_q and reload_wayD_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu63_wayD_upd(0) <= p1_way_data_upd63_wayD and p1_wren_q; +rel_bixu63_wayD_upd(1) <= p0_way_data_upd63_wayD and p0_wren_q; +p0_way_data_upd63_wayE <= p0_congr_cl63_act_q and binv_wayE_upd3_q; +p1_way_data_upd63_wayE <= p1_congr_cl63_act_q and reload_wayE_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu63_wayE_upd(0) <= p1_way_data_upd63_wayE and p1_wren_q; +rel_bixu63_wayE_upd(1) <= p0_way_data_upd63_wayE and p0_wren_q; +p0_way_data_upd63_wayF <= p0_congr_cl63_act_q and binv_wayF_upd3_q; +p1_way_data_upd63_wayF <= p1_congr_cl63_act_q and reload_wayF_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu63_wayF_upd(0) <= p1_way_data_upd63_wayF and p1_wren_q; +rel_bixu63_wayF_upd(1) <= p0_way_data_upd63_wayF and p0_wren_q; +p0_way_data_upd63_wayG <= p0_congr_cl63_act_q and binv_wayG_upd3_q; +p1_way_data_upd63_wayG <= p1_congr_cl63_act_q and reload_wayG_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu63_wayG_upd(0) <= p1_way_data_upd63_wayG and p1_wren_q; +rel_bixu63_wayG_upd(1) <= p0_way_data_upd63_wayG and p0_wren_q; +p0_way_data_upd63_wayH <= p0_congr_cl63_act_q and binv_wayH_upd3_q; +p1_way_data_upd63_wayH <= p1_congr_cl63_act_q and reload_wayH_upd3_q; +-- Mux Selects for Input to Latches +rel_bixu63_wayH_upd(0) <= p1_way_data_upd63_wayH and p1_wren_q; +rel_bixu63_wayH_upd(1) <= p0_way_data_upd63_wayH and p0_wren_q; +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Write Select for WayA +-- WayA Valid Bit Update for Congruence Class 0 +with rel_bixu0_wayA_upd select + congr_cl0_wA_d(0) <= (congr_cl0_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 0 +with rel_bixu0_wayA_upd select + congr_cl0_wA_d(1) <= (congr_cl0_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayA_upd select + congr_cl0_wA_d(2) <= (congr_cl0_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayA_upd select + congr_cl0_wA_d(3) <= (congr_cl0_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayA_upd select + congr_cl0_wA_d(4) <= (congr_cl0_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayA_upd select + congr_cl0_wA_d(5) <= (congr_cl0_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 1 +with rel_bixu1_wayA_upd select + congr_cl1_wA_d(0) <= (congr_cl1_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 1 +with rel_bixu1_wayA_upd select + congr_cl1_wA_d(1) <= (congr_cl1_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayA_upd select + congr_cl1_wA_d(2) <= (congr_cl1_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayA_upd select + congr_cl1_wA_d(3) <= (congr_cl1_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayA_upd select + congr_cl1_wA_d(4) <= (congr_cl1_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayA_upd select + congr_cl1_wA_d(5) <= (congr_cl1_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 2 +with rel_bixu2_wayA_upd select + congr_cl2_wA_d(0) <= (congr_cl2_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 2 +with rel_bixu2_wayA_upd select + congr_cl2_wA_d(1) <= (congr_cl2_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayA_upd select + congr_cl2_wA_d(2) <= (congr_cl2_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayA_upd select + congr_cl2_wA_d(3) <= (congr_cl2_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayA_upd select + congr_cl2_wA_d(4) <= (congr_cl2_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayA_upd select + congr_cl2_wA_d(5) <= (congr_cl2_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 3 +with rel_bixu3_wayA_upd select + congr_cl3_wA_d(0) <= (congr_cl3_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 3 +with rel_bixu3_wayA_upd select + congr_cl3_wA_d(1) <= (congr_cl3_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayA_upd select + congr_cl3_wA_d(2) <= (congr_cl3_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayA_upd select + congr_cl3_wA_d(3) <= (congr_cl3_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayA_upd select + congr_cl3_wA_d(4) <= (congr_cl3_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayA_upd select + congr_cl3_wA_d(5) <= (congr_cl3_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 4 +with rel_bixu4_wayA_upd select + congr_cl4_wA_d(0) <= (congr_cl4_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 4 +with rel_bixu4_wayA_upd select + congr_cl4_wA_d(1) <= (congr_cl4_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayA_upd select + congr_cl4_wA_d(2) <= (congr_cl4_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayA_upd select + congr_cl4_wA_d(3) <= (congr_cl4_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayA_upd select + congr_cl4_wA_d(4) <= (congr_cl4_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayA_upd select + congr_cl4_wA_d(5) <= (congr_cl4_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 5 +with rel_bixu5_wayA_upd select + congr_cl5_wA_d(0) <= (congr_cl5_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 5 +with rel_bixu5_wayA_upd select + congr_cl5_wA_d(1) <= (congr_cl5_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayA_upd select + congr_cl5_wA_d(2) <= (congr_cl5_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayA_upd select + congr_cl5_wA_d(3) <= (congr_cl5_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayA_upd select + congr_cl5_wA_d(4) <= (congr_cl5_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayA_upd select + congr_cl5_wA_d(5) <= (congr_cl5_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 6 +with rel_bixu6_wayA_upd select + congr_cl6_wA_d(0) <= (congr_cl6_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 6 +with rel_bixu6_wayA_upd select + congr_cl6_wA_d(1) <= (congr_cl6_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayA_upd select + congr_cl6_wA_d(2) <= (congr_cl6_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayA_upd select + congr_cl6_wA_d(3) <= (congr_cl6_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayA_upd select + congr_cl6_wA_d(4) <= (congr_cl6_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayA_upd select + congr_cl6_wA_d(5) <= (congr_cl6_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 7 +with rel_bixu7_wayA_upd select + congr_cl7_wA_d(0) <= (congr_cl7_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 7 +with rel_bixu7_wayA_upd select + congr_cl7_wA_d(1) <= (congr_cl7_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayA_upd select + congr_cl7_wA_d(2) <= (congr_cl7_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayA_upd select + congr_cl7_wA_d(3) <= (congr_cl7_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayA_upd select + congr_cl7_wA_d(4) <= (congr_cl7_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayA_upd select + congr_cl7_wA_d(5) <= (congr_cl7_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 8 +with rel_bixu8_wayA_upd select + congr_cl8_wA_d(0) <= (congr_cl8_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 8 +with rel_bixu8_wayA_upd select + congr_cl8_wA_d(1) <= (congr_cl8_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayA_upd select + congr_cl8_wA_d(2) <= (congr_cl8_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayA_upd select + congr_cl8_wA_d(3) <= (congr_cl8_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayA_upd select + congr_cl8_wA_d(4) <= (congr_cl8_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayA_upd select + congr_cl8_wA_d(5) <= (congr_cl8_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 9 +with rel_bixu9_wayA_upd select + congr_cl9_wA_d(0) <= (congr_cl9_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 9 +with rel_bixu9_wayA_upd select + congr_cl9_wA_d(1) <= (congr_cl9_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayA_upd select + congr_cl9_wA_d(2) <= (congr_cl9_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayA_upd select + congr_cl9_wA_d(3) <= (congr_cl9_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayA_upd select + congr_cl9_wA_d(4) <= (congr_cl9_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayA_upd select + congr_cl9_wA_d(5) <= (congr_cl9_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 10 +with rel_bixu10_wayA_upd select + congr_cl10_wA_d(0) <= (congr_cl10_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 10 +with rel_bixu10_wayA_upd select + congr_cl10_wA_d(1) <= (congr_cl10_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayA_upd select + congr_cl10_wA_d(2) <= (congr_cl10_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayA_upd select + congr_cl10_wA_d(3) <= (congr_cl10_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayA_upd select + congr_cl10_wA_d(4) <= (congr_cl10_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayA_upd select + congr_cl10_wA_d(5) <= (congr_cl10_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 11 +with rel_bixu11_wayA_upd select + congr_cl11_wA_d(0) <= (congr_cl11_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 11 +with rel_bixu11_wayA_upd select + congr_cl11_wA_d(1) <= (congr_cl11_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayA_upd select + congr_cl11_wA_d(2) <= (congr_cl11_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayA_upd select + congr_cl11_wA_d(3) <= (congr_cl11_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayA_upd select + congr_cl11_wA_d(4) <= (congr_cl11_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayA_upd select + congr_cl11_wA_d(5) <= (congr_cl11_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 12 +with rel_bixu12_wayA_upd select + congr_cl12_wA_d(0) <= (congr_cl12_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 12 +with rel_bixu12_wayA_upd select + congr_cl12_wA_d(1) <= (congr_cl12_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayA_upd select + congr_cl12_wA_d(2) <= (congr_cl12_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayA_upd select + congr_cl12_wA_d(3) <= (congr_cl12_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayA_upd select + congr_cl12_wA_d(4) <= (congr_cl12_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayA_upd select + congr_cl12_wA_d(5) <= (congr_cl12_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 13 +with rel_bixu13_wayA_upd select + congr_cl13_wA_d(0) <= (congr_cl13_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 13 +with rel_bixu13_wayA_upd select + congr_cl13_wA_d(1) <= (congr_cl13_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayA_upd select + congr_cl13_wA_d(2) <= (congr_cl13_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayA_upd select + congr_cl13_wA_d(3) <= (congr_cl13_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayA_upd select + congr_cl13_wA_d(4) <= (congr_cl13_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayA_upd select + congr_cl13_wA_d(5) <= (congr_cl13_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 14 +with rel_bixu14_wayA_upd select + congr_cl14_wA_d(0) <= (congr_cl14_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 14 +with rel_bixu14_wayA_upd select + congr_cl14_wA_d(1) <= (congr_cl14_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayA_upd select + congr_cl14_wA_d(2) <= (congr_cl14_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayA_upd select + congr_cl14_wA_d(3) <= (congr_cl14_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayA_upd select + congr_cl14_wA_d(4) <= (congr_cl14_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayA_upd select + congr_cl14_wA_d(5) <= (congr_cl14_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 15 +with rel_bixu15_wayA_upd select + congr_cl15_wA_d(0) <= (congr_cl15_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 15 +with rel_bixu15_wayA_upd select + congr_cl15_wA_d(1) <= (congr_cl15_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayA_upd select + congr_cl15_wA_d(2) <= (congr_cl15_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayA_upd select + congr_cl15_wA_d(3) <= (congr_cl15_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayA_upd select + congr_cl15_wA_d(4) <= (congr_cl15_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayA_upd select + congr_cl15_wA_d(5) <= (congr_cl15_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 16 +with rel_bixu16_wayA_upd select + congr_cl16_wA_d(0) <= (congr_cl16_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 16 +with rel_bixu16_wayA_upd select + congr_cl16_wA_d(1) <= (congr_cl16_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayA_upd select + congr_cl16_wA_d(2) <= (congr_cl16_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayA_upd select + congr_cl16_wA_d(3) <= (congr_cl16_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayA_upd select + congr_cl16_wA_d(4) <= (congr_cl16_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayA_upd select + congr_cl16_wA_d(5) <= (congr_cl16_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 17 +with rel_bixu17_wayA_upd select + congr_cl17_wA_d(0) <= (congr_cl17_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 17 +with rel_bixu17_wayA_upd select + congr_cl17_wA_d(1) <= (congr_cl17_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayA_upd select + congr_cl17_wA_d(2) <= (congr_cl17_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayA_upd select + congr_cl17_wA_d(3) <= (congr_cl17_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayA_upd select + congr_cl17_wA_d(4) <= (congr_cl17_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayA_upd select + congr_cl17_wA_d(5) <= (congr_cl17_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 18 +with rel_bixu18_wayA_upd select + congr_cl18_wA_d(0) <= (congr_cl18_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 18 +with rel_bixu18_wayA_upd select + congr_cl18_wA_d(1) <= (congr_cl18_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayA_upd select + congr_cl18_wA_d(2) <= (congr_cl18_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayA_upd select + congr_cl18_wA_d(3) <= (congr_cl18_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayA_upd select + congr_cl18_wA_d(4) <= (congr_cl18_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayA_upd select + congr_cl18_wA_d(5) <= (congr_cl18_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 19 +with rel_bixu19_wayA_upd select + congr_cl19_wA_d(0) <= (congr_cl19_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 19 +with rel_bixu19_wayA_upd select + congr_cl19_wA_d(1) <= (congr_cl19_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayA_upd select + congr_cl19_wA_d(2) <= (congr_cl19_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayA_upd select + congr_cl19_wA_d(3) <= (congr_cl19_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayA_upd select + congr_cl19_wA_d(4) <= (congr_cl19_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayA_upd select + congr_cl19_wA_d(5) <= (congr_cl19_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 20 +with rel_bixu20_wayA_upd select + congr_cl20_wA_d(0) <= (congr_cl20_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 20 +with rel_bixu20_wayA_upd select + congr_cl20_wA_d(1) <= (congr_cl20_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayA_upd select + congr_cl20_wA_d(2) <= (congr_cl20_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayA_upd select + congr_cl20_wA_d(3) <= (congr_cl20_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayA_upd select + congr_cl20_wA_d(4) <= (congr_cl20_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayA_upd select + congr_cl20_wA_d(5) <= (congr_cl20_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 21 +with rel_bixu21_wayA_upd select + congr_cl21_wA_d(0) <= (congr_cl21_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 21 +with rel_bixu21_wayA_upd select + congr_cl21_wA_d(1) <= (congr_cl21_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayA_upd select + congr_cl21_wA_d(2) <= (congr_cl21_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayA_upd select + congr_cl21_wA_d(3) <= (congr_cl21_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayA_upd select + congr_cl21_wA_d(4) <= (congr_cl21_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayA_upd select + congr_cl21_wA_d(5) <= (congr_cl21_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 22 +with rel_bixu22_wayA_upd select + congr_cl22_wA_d(0) <= (congr_cl22_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 22 +with rel_bixu22_wayA_upd select + congr_cl22_wA_d(1) <= (congr_cl22_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayA_upd select + congr_cl22_wA_d(2) <= (congr_cl22_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayA_upd select + congr_cl22_wA_d(3) <= (congr_cl22_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayA_upd select + congr_cl22_wA_d(4) <= (congr_cl22_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayA_upd select + congr_cl22_wA_d(5) <= (congr_cl22_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 23 +with rel_bixu23_wayA_upd select + congr_cl23_wA_d(0) <= (congr_cl23_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 23 +with rel_bixu23_wayA_upd select + congr_cl23_wA_d(1) <= (congr_cl23_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayA_upd select + congr_cl23_wA_d(2) <= (congr_cl23_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayA_upd select + congr_cl23_wA_d(3) <= (congr_cl23_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayA_upd select + congr_cl23_wA_d(4) <= (congr_cl23_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayA_upd select + congr_cl23_wA_d(5) <= (congr_cl23_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 24 +with rel_bixu24_wayA_upd select + congr_cl24_wA_d(0) <= (congr_cl24_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 24 +with rel_bixu24_wayA_upd select + congr_cl24_wA_d(1) <= (congr_cl24_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayA_upd select + congr_cl24_wA_d(2) <= (congr_cl24_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayA_upd select + congr_cl24_wA_d(3) <= (congr_cl24_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayA_upd select + congr_cl24_wA_d(4) <= (congr_cl24_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayA_upd select + congr_cl24_wA_d(5) <= (congr_cl24_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 25 +with rel_bixu25_wayA_upd select + congr_cl25_wA_d(0) <= (congr_cl25_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 25 +with rel_bixu25_wayA_upd select + congr_cl25_wA_d(1) <= (congr_cl25_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayA_upd select + congr_cl25_wA_d(2) <= (congr_cl25_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayA_upd select + congr_cl25_wA_d(3) <= (congr_cl25_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayA_upd select + congr_cl25_wA_d(4) <= (congr_cl25_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayA_upd select + congr_cl25_wA_d(5) <= (congr_cl25_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 26 +with rel_bixu26_wayA_upd select + congr_cl26_wA_d(0) <= (congr_cl26_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 26 +with rel_bixu26_wayA_upd select + congr_cl26_wA_d(1) <= (congr_cl26_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayA_upd select + congr_cl26_wA_d(2) <= (congr_cl26_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayA_upd select + congr_cl26_wA_d(3) <= (congr_cl26_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayA_upd select + congr_cl26_wA_d(4) <= (congr_cl26_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayA_upd select + congr_cl26_wA_d(5) <= (congr_cl26_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 27 +with rel_bixu27_wayA_upd select + congr_cl27_wA_d(0) <= (congr_cl27_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 27 +with rel_bixu27_wayA_upd select + congr_cl27_wA_d(1) <= (congr_cl27_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayA_upd select + congr_cl27_wA_d(2) <= (congr_cl27_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayA_upd select + congr_cl27_wA_d(3) <= (congr_cl27_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayA_upd select + congr_cl27_wA_d(4) <= (congr_cl27_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayA_upd select + congr_cl27_wA_d(5) <= (congr_cl27_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 28 +with rel_bixu28_wayA_upd select + congr_cl28_wA_d(0) <= (congr_cl28_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 28 +with rel_bixu28_wayA_upd select + congr_cl28_wA_d(1) <= (congr_cl28_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayA_upd select + congr_cl28_wA_d(2) <= (congr_cl28_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayA_upd select + congr_cl28_wA_d(3) <= (congr_cl28_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayA_upd select + congr_cl28_wA_d(4) <= (congr_cl28_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayA_upd select + congr_cl28_wA_d(5) <= (congr_cl28_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 29 +with rel_bixu29_wayA_upd select + congr_cl29_wA_d(0) <= (congr_cl29_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 29 +with rel_bixu29_wayA_upd select + congr_cl29_wA_d(1) <= (congr_cl29_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayA_upd select + congr_cl29_wA_d(2) <= (congr_cl29_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayA_upd select + congr_cl29_wA_d(3) <= (congr_cl29_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayA_upd select + congr_cl29_wA_d(4) <= (congr_cl29_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayA_upd select + congr_cl29_wA_d(5) <= (congr_cl29_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 30 +with rel_bixu30_wayA_upd select + congr_cl30_wA_d(0) <= (congr_cl30_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 30 +with rel_bixu30_wayA_upd select + congr_cl30_wA_d(1) <= (congr_cl30_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayA_upd select + congr_cl30_wA_d(2) <= (congr_cl30_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayA_upd select + congr_cl30_wA_d(3) <= (congr_cl30_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayA_upd select + congr_cl30_wA_d(4) <= (congr_cl30_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayA_upd select + congr_cl30_wA_d(5) <= (congr_cl30_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 31 +with rel_bixu31_wayA_upd select + congr_cl31_wA_d(0) <= (congr_cl31_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 31 +with rel_bixu31_wayA_upd select + congr_cl31_wA_d(1) <= (congr_cl31_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayA_upd select + congr_cl31_wA_d(2) <= (congr_cl31_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayA_upd select + congr_cl31_wA_d(3) <= (congr_cl31_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayA_upd select + congr_cl31_wA_d(4) <= (congr_cl31_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayA_upd select + congr_cl31_wA_d(5) <= (congr_cl31_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 32 +with rel_bixu32_wayA_upd select + congr_cl32_wA_d(0) <= (congr_cl32_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 32 +with rel_bixu32_wayA_upd select + congr_cl32_wA_d(1) <= (congr_cl32_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 32 +with rel_bixu32_wayA_upd select + congr_cl32_wA_d(2) <= (congr_cl32_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 32 +with rel_bixu32_wayA_upd select + congr_cl32_wA_d(3) <= (congr_cl32_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 32 +with rel_bixu32_wayA_upd select + congr_cl32_wA_d(4) <= (congr_cl32_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 32 +with rel_bixu32_wayA_upd select + congr_cl32_wA_d(5) <= (congr_cl32_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 33 +with rel_bixu33_wayA_upd select + congr_cl33_wA_d(0) <= (congr_cl33_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 33 +with rel_bixu33_wayA_upd select + congr_cl33_wA_d(1) <= (congr_cl33_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 33 +with rel_bixu33_wayA_upd select + congr_cl33_wA_d(2) <= (congr_cl33_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 33 +with rel_bixu33_wayA_upd select + congr_cl33_wA_d(3) <= (congr_cl33_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 33 +with rel_bixu33_wayA_upd select + congr_cl33_wA_d(4) <= (congr_cl33_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 33 +with rel_bixu33_wayA_upd select + congr_cl33_wA_d(5) <= (congr_cl33_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 34 +with rel_bixu34_wayA_upd select + congr_cl34_wA_d(0) <= (congr_cl34_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 34 +with rel_bixu34_wayA_upd select + congr_cl34_wA_d(1) <= (congr_cl34_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 34 +with rel_bixu34_wayA_upd select + congr_cl34_wA_d(2) <= (congr_cl34_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 34 +with rel_bixu34_wayA_upd select + congr_cl34_wA_d(3) <= (congr_cl34_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 34 +with rel_bixu34_wayA_upd select + congr_cl34_wA_d(4) <= (congr_cl34_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 34 +with rel_bixu34_wayA_upd select + congr_cl34_wA_d(5) <= (congr_cl34_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 35 +with rel_bixu35_wayA_upd select + congr_cl35_wA_d(0) <= (congr_cl35_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 35 +with rel_bixu35_wayA_upd select + congr_cl35_wA_d(1) <= (congr_cl35_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 35 +with rel_bixu35_wayA_upd select + congr_cl35_wA_d(2) <= (congr_cl35_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 35 +with rel_bixu35_wayA_upd select + congr_cl35_wA_d(3) <= (congr_cl35_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 35 +with rel_bixu35_wayA_upd select + congr_cl35_wA_d(4) <= (congr_cl35_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 35 +with rel_bixu35_wayA_upd select + congr_cl35_wA_d(5) <= (congr_cl35_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 36 +with rel_bixu36_wayA_upd select + congr_cl36_wA_d(0) <= (congr_cl36_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 36 +with rel_bixu36_wayA_upd select + congr_cl36_wA_d(1) <= (congr_cl36_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 36 +with rel_bixu36_wayA_upd select + congr_cl36_wA_d(2) <= (congr_cl36_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 36 +with rel_bixu36_wayA_upd select + congr_cl36_wA_d(3) <= (congr_cl36_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 36 +with rel_bixu36_wayA_upd select + congr_cl36_wA_d(4) <= (congr_cl36_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 36 +with rel_bixu36_wayA_upd select + congr_cl36_wA_d(5) <= (congr_cl36_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 37 +with rel_bixu37_wayA_upd select + congr_cl37_wA_d(0) <= (congr_cl37_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 37 +with rel_bixu37_wayA_upd select + congr_cl37_wA_d(1) <= (congr_cl37_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 37 +with rel_bixu37_wayA_upd select + congr_cl37_wA_d(2) <= (congr_cl37_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 37 +with rel_bixu37_wayA_upd select + congr_cl37_wA_d(3) <= (congr_cl37_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 37 +with rel_bixu37_wayA_upd select + congr_cl37_wA_d(4) <= (congr_cl37_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 37 +with rel_bixu37_wayA_upd select + congr_cl37_wA_d(5) <= (congr_cl37_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 38 +with rel_bixu38_wayA_upd select + congr_cl38_wA_d(0) <= (congr_cl38_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 38 +with rel_bixu38_wayA_upd select + congr_cl38_wA_d(1) <= (congr_cl38_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 38 +with rel_bixu38_wayA_upd select + congr_cl38_wA_d(2) <= (congr_cl38_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 38 +with rel_bixu38_wayA_upd select + congr_cl38_wA_d(3) <= (congr_cl38_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 38 +with rel_bixu38_wayA_upd select + congr_cl38_wA_d(4) <= (congr_cl38_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 38 +with rel_bixu38_wayA_upd select + congr_cl38_wA_d(5) <= (congr_cl38_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 39 +with rel_bixu39_wayA_upd select + congr_cl39_wA_d(0) <= (congr_cl39_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 39 +with rel_bixu39_wayA_upd select + congr_cl39_wA_d(1) <= (congr_cl39_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 39 +with rel_bixu39_wayA_upd select + congr_cl39_wA_d(2) <= (congr_cl39_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 39 +with rel_bixu39_wayA_upd select + congr_cl39_wA_d(3) <= (congr_cl39_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 39 +with rel_bixu39_wayA_upd select + congr_cl39_wA_d(4) <= (congr_cl39_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 39 +with rel_bixu39_wayA_upd select + congr_cl39_wA_d(5) <= (congr_cl39_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 40 +with rel_bixu40_wayA_upd select + congr_cl40_wA_d(0) <= (congr_cl40_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 40 +with rel_bixu40_wayA_upd select + congr_cl40_wA_d(1) <= (congr_cl40_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 40 +with rel_bixu40_wayA_upd select + congr_cl40_wA_d(2) <= (congr_cl40_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 40 +with rel_bixu40_wayA_upd select + congr_cl40_wA_d(3) <= (congr_cl40_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 40 +with rel_bixu40_wayA_upd select + congr_cl40_wA_d(4) <= (congr_cl40_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 40 +with rel_bixu40_wayA_upd select + congr_cl40_wA_d(5) <= (congr_cl40_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 41 +with rel_bixu41_wayA_upd select + congr_cl41_wA_d(0) <= (congr_cl41_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 41 +with rel_bixu41_wayA_upd select + congr_cl41_wA_d(1) <= (congr_cl41_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 41 +with rel_bixu41_wayA_upd select + congr_cl41_wA_d(2) <= (congr_cl41_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 41 +with rel_bixu41_wayA_upd select + congr_cl41_wA_d(3) <= (congr_cl41_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 41 +with rel_bixu41_wayA_upd select + congr_cl41_wA_d(4) <= (congr_cl41_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 41 +with rel_bixu41_wayA_upd select + congr_cl41_wA_d(5) <= (congr_cl41_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 42 +with rel_bixu42_wayA_upd select + congr_cl42_wA_d(0) <= (congr_cl42_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 42 +with rel_bixu42_wayA_upd select + congr_cl42_wA_d(1) <= (congr_cl42_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 42 +with rel_bixu42_wayA_upd select + congr_cl42_wA_d(2) <= (congr_cl42_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 42 +with rel_bixu42_wayA_upd select + congr_cl42_wA_d(3) <= (congr_cl42_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 42 +with rel_bixu42_wayA_upd select + congr_cl42_wA_d(4) <= (congr_cl42_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 42 +with rel_bixu42_wayA_upd select + congr_cl42_wA_d(5) <= (congr_cl42_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 43 +with rel_bixu43_wayA_upd select + congr_cl43_wA_d(0) <= (congr_cl43_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 43 +with rel_bixu43_wayA_upd select + congr_cl43_wA_d(1) <= (congr_cl43_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 43 +with rel_bixu43_wayA_upd select + congr_cl43_wA_d(2) <= (congr_cl43_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 43 +with rel_bixu43_wayA_upd select + congr_cl43_wA_d(3) <= (congr_cl43_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 43 +with rel_bixu43_wayA_upd select + congr_cl43_wA_d(4) <= (congr_cl43_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 43 +with rel_bixu43_wayA_upd select + congr_cl43_wA_d(5) <= (congr_cl43_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 44 +with rel_bixu44_wayA_upd select + congr_cl44_wA_d(0) <= (congr_cl44_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 44 +with rel_bixu44_wayA_upd select + congr_cl44_wA_d(1) <= (congr_cl44_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 44 +with rel_bixu44_wayA_upd select + congr_cl44_wA_d(2) <= (congr_cl44_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 44 +with rel_bixu44_wayA_upd select + congr_cl44_wA_d(3) <= (congr_cl44_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 44 +with rel_bixu44_wayA_upd select + congr_cl44_wA_d(4) <= (congr_cl44_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 44 +with rel_bixu44_wayA_upd select + congr_cl44_wA_d(5) <= (congr_cl44_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 45 +with rel_bixu45_wayA_upd select + congr_cl45_wA_d(0) <= (congr_cl45_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 45 +with rel_bixu45_wayA_upd select + congr_cl45_wA_d(1) <= (congr_cl45_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 45 +with rel_bixu45_wayA_upd select + congr_cl45_wA_d(2) <= (congr_cl45_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 45 +with rel_bixu45_wayA_upd select + congr_cl45_wA_d(3) <= (congr_cl45_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 45 +with rel_bixu45_wayA_upd select + congr_cl45_wA_d(4) <= (congr_cl45_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 45 +with rel_bixu45_wayA_upd select + congr_cl45_wA_d(5) <= (congr_cl45_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 46 +with rel_bixu46_wayA_upd select + congr_cl46_wA_d(0) <= (congr_cl46_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 46 +with rel_bixu46_wayA_upd select + congr_cl46_wA_d(1) <= (congr_cl46_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 46 +with rel_bixu46_wayA_upd select + congr_cl46_wA_d(2) <= (congr_cl46_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 46 +with rel_bixu46_wayA_upd select + congr_cl46_wA_d(3) <= (congr_cl46_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 46 +with rel_bixu46_wayA_upd select + congr_cl46_wA_d(4) <= (congr_cl46_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 46 +with rel_bixu46_wayA_upd select + congr_cl46_wA_d(5) <= (congr_cl46_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 47 +with rel_bixu47_wayA_upd select + congr_cl47_wA_d(0) <= (congr_cl47_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 47 +with rel_bixu47_wayA_upd select + congr_cl47_wA_d(1) <= (congr_cl47_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 47 +with rel_bixu47_wayA_upd select + congr_cl47_wA_d(2) <= (congr_cl47_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 47 +with rel_bixu47_wayA_upd select + congr_cl47_wA_d(3) <= (congr_cl47_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 47 +with rel_bixu47_wayA_upd select + congr_cl47_wA_d(4) <= (congr_cl47_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 47 +with rel_bixu47_wayA_upd select + congr_cl47_wA_d(5) <= (congr_cl47_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 48 +with rel_bixu48_wayA_upd select + congr_cl48_wA_d(0) <= (congr_cl48_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 48 +with rel_bixu48_wayA_upd select + congr_cl48_wA_d(1) <= (congr_cl48_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 48 +with rel_bixu48_wayA_upd select + congr_cl48_wA_d(2) <= (congr_cl48_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 48 +with rel_bixu48_wayA_upd select + congr_cl48_wA_d(3) <= (congr_cl48_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 48 +with rel_bixu48_wayA_upd select + congr_cl48_wA_d(4) <= (congr_cl48_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 48 +with rel_bixu48_wayA_upd select + congr_cl48_wA_d(5) <= (congr_cl48_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 49 +with rel_bixu49_wayA_upd select + congr_cl49_wA_d(0) <= (congr_cl49_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 49 +with rel_bixu49_wayA_upd select + congr_cl49_wA_d(1) <= (congr_cl49_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 49 +with rel_bixu49_wayA_upd select + congr_cl49_wA_d(2) <= (congr_cl49_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 49 +with rel_bixu49_wayA_upd select + congr_cl49_wA_d(3) <= (congr_cl49_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 49 +with rel_bixu49_wayA_upd select + congr_cl49_wA_d(4) <= (congr_cl49_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 49 +with rel_bixu49_wayA_upd select + congr_cl49_wA_d(5) <= (congr_cl49_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 50 +with rel_bixu50_wayA_upd select + congr_cl50_wA_d(0) <= (congr_cl50_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 50 +with rel_bixu50_wayA_upd select + congr_cl50_wA_d(1) <= (congr_cl50_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 50 +with rel_bixu50_wayA_upd select + congr_cl50_wA_d(2) <= (congr_cl50_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 50 +with rel_bixu50_wayA_upd select + congr_cl50_wA_d(3) <= (congr_cl50_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 50 +with rel_bixu50_wayA_upd select + congr_cl50_wA_d(4) <= (congr_cl50_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 50 +with rel_bixu50_wayA_upd select + congr_cl50_wA_d(5) <= (congr_cl50_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 51 +with rel_bixu51_wayA_upd select + congr_cl51_wA_d(0) <= (congr_cl51_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 51 +with rel_bixu51_wayA_upd select + congr_cl51_wA_d(1) <= (congr_cl51_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 51 +with rel_bixu51_wayA_upd select + congr_cl51_wA_d(2) <= (congr_cl51_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 51 +with rel_bixu51_wayA_upd select + congr_cl51_wA_d(3) <= (congr_cl51_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 51 +with rel_bixu51_wayA_upd select + congr_cl51_wA_d(4) <= (congr_cl51_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 51 +with rel_bixu51_wayA_upd select + congr_cl51_wA_d(5) <= (congr_cl51_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 52 +with rel_bixu52_wayA_upd select + congr_cl52_wA_d(0) <= (congr_cl52_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 52 +with rel_bixu52_wayA_upd select + congr_cl52_wA_d(1) <= (congr_cl52_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 52 +with rel_bixu52_wayA_upd select + congr_cl52_wA_d(2) <= (congr_cl52_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 52 +with rel_bixu52_wayA_upd select + congr_cl52_wA_d(3) <= (congr_cl52_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 52 +with rel_bixu52_wayA_upd select + congr_cl52_wA_d(4) <= (congr_cl52_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 52 +with rel_bixu52_wayA_upd select + congr_cl52_wA_d(5) <= (congr_cl52_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 53 +with rel_bixu53_wayA_upd select + congr_cl53_wA_d(0) <= (congr_cl53_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 53 +with rel_bixu53_wayA_upd select + congr_cl53_wA_d(1) <= (congr_cl53_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 53 +with rel_bixu53_wayA_upd select + congr_cl53_wA_d(2) <= (congr_cl53_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 53 +with rel_bixu53_wayA_upd select + congr_cl53_wA_d(3) <= (congr_cl53_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 53 +with rel_bixu53_wayA_upd select + congr_cl53_wA_d(4) <= (congr_cl53_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 53 +with rel_bixu53_wayA_upd select + congr_cl53_wA_d(5) <= (congr_cl53_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 54 +with rel_bixu54_wayA_upd select + congr_cl54_wA_d(0) <= (congr_cl54_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 54 +with rel_bixu54_wayA_upd select + congr_cl54_wA_d(1) <= (congr_cl54_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 54 +with rel_bixu54_wayA_upd select + congr_cl54_wA_d(2) <= (congr_cl54_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 54 +with rel_bixu54_wayA_upd select + congr_cl54_wA_d(3) <= (congr_cl54_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 54 +with rel_bixu54_wayA_upd select + congr_cl54_wA_d(4) <= (congr_cl54_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 54 +with rel_bixu54_wayA_upd select + congr_cl54_wA_d(5) <= (congr_cl54_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 55 +with rel_bixu55_wayA_upd select + congr_cl55_wA_d(0) <= (congr_cl55_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 55 +with rel_bixu55_wayA_upd select + congr_cl55_wA_d(1) <= (congr_cl55_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 55 +with rel_bixu55_wayA_upd select + congr_cl55_wA_d(2) <= (congr_cl55_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 55 +with rel_bixu55_wayA_upd select + congr_cl55_wA_d(3) <= (congr_cl55_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 55 +with rel_bixu55_wayA_upd select + congr_cl55_wA_d(4) <= (congr_cl55_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 55 +with rel_bixu55_wayA_upd select + congr_cl55_wA_d(5) <= (congr_cl55_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 56 +with rel_bixu56_wayA_upd select + congr_cl56_wA_d(0) <= (congr_cl56_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 56 +with rel_bixu56_wayA_upd select + congr_cl56_wA_d(1) <= (congr_cl56_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 56 +with rel_bixu56_wayA_upd select + congr_cl56_wA_d(2) <= (congr_cl56_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 56 +with rel_bixu56_wayA_upd select + congr_cl56_wA_d(3) <= (congr_cl56_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 56 +with rel_bixu56_wayA_upd select + congr_cl56_wA_d(4) <= (congr_cl56_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 56 +with rel_bixu56_wayA_upd select + congr_cl56_wA_d(5) <= (congr_cl56_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 57 +with rel_bixu57_wayA_upd select + congr_cl57_wA_d(0) <= (congr_cl57_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 57 +with rel_bixu57_wayA_upd select + congr_cl57_wA_d(1) <= (congr_cl57_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 57 +with rel_bixu57_wayA_upd select + congr_cl57_wA_d(2) <= (congr_cl57_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 57 +with rel_bixu57_wayA_upd select + congr_cl57_wA_d(3) <= (congr_cl57_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 57 +with rel_bixu57_wayA_upd select + congr_cl57_wA_d(4) <= (congr_cl57_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 57 +with rel_bixu57_wayA_upd select + congr_cl57_wA_d(5) <= (congr_cl57_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 58 +with rel_bixu58_wayA_upd select + congr_cl58_wA_d(0) <= (congr_cl58_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 58 +with rel_bixu58_wayA_upd select + congr_cl58_wA_d(1) <= (congr_cl58_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 58 +with rel_bixu58_wayA_upd select + congr_cl58_wA_d(2) <= (congr_cl58_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 58 +with rel_bixu58_wayA_upd select + congr_cl58_wA_d(3) <= (congr_cl58_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 58 +with rel_bixu58_wayA_upd select + congr_cl58_wA_d(4) <= (congr_cl58_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 58 +with rel_bixu58_wayA_upd select + congr_cl58_wA_d(5) <= (congr_cl58_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 59 +with rel_bixu59_wayA_upd select + congr_cl59_wA_d(0) <= (congr_cl59_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 59 +with rel_bixu59_wayA_upd select + congr_cl59_wA_d(1) <= (congr_cl59_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 59 +with rel_bixu59_wayA_upd select + congr_cl59_wA_d(2) <= (congr_cl59_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 59 +with rel_bixu59_wayA_upd select + congr_cl59_wA_d(3) <= (congr_cl59_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 59 +with rel_bixu59_wayA_upd select + congr_cl59_wA_d(4) <= (congr_cl59_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 59 +with rel_bixu59_wayA_upd select + congr_cl59_wA_d(5) <= (congr_cl59_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 60 +with rel_bixu60_wayA_upd select + congr_cl60_wA_d(0) <= (congr_cl60_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 60 +with rel_bixu60_wayA_upd select + congr_cl60_wA_d(1) <= (congr_cl60_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 60 +with rel_bixu60_wayA_upd select + congr_cl60_wA_d(2) <= (congr_cl60_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 60 +with rel_bixu60_wayA_upd select + congr_cl60_wA_d(3) <= (congr_cl60_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 60 +with rel_bixu60_wayA_upd select + congr_cl60_wA_d(4) <= (congr_cl60_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 60 +with rel_bixu60_wayA_upd select + congr_cl60_wA_d(5) <= (congr_cl60_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 61 +with rel_bixu61_wayA_upd select + congr_cl61_wA_d(0) <= (congr_cl61_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 61 +with rel_bixu61_wayA_upd select + congr_cl61_wA_d(1) <= (congr_cl61_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 61 +with rel_bixu61_wayA_upd select + congr_cl61_wA_d(2) <= (congr_cl61_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 61 +with rel_bixu61_wayA_upd select + congr_cl61_wA_d(3) <= (congr_cl61_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 61 +with rel_bixu61_wayA_upd select + congr_cl61_wA_d(4) <= (congr_cl61_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 61 +with rel_bixu61_wayA_upd select + congr_cl61_wA_d(5) <= (congr_cl61_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 62 +with rel_bixu62_wayA_upd select + congr_cl62_wA_d(0) <= (congr_cl62_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 62 +with rel_bixu62_wayA_upd select + congr_cl62_wA_d(1) <= (congr_cl62_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 62 +with rel_bixu62_wayA_upd select + congr_cl62_wA_d(2) <= (congr_cl62_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 62 +with rel_bixu62_wayA_upd select + congr_cl62_wA_d(3) <= (congr_cl62_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 62 +with rel_bixu62_wayA_upd select + congr_cl62_wA_d(4) <= (congr_cl62_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 62 +with rel_bixu62_wayA_upd select + congr_cl62_wA_d(5) <= (congr_cl62_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayA Valid Bit Update for Congruence Class 63 +with rel_bixu63_wayA_upd select + congr_cl63_wA_d(0) <= (congr_cl63_wA_q(0) and not dci_inval_all_q) when "00", + (flush_wayA_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayA_data2_q(0) and not dci_inval_all_q) when others; +-- WayA Lock Bit Update for Congruence Class 63 +with rel_bixu63_wayA_upd select + congr_cl63_wA_d(1) <= (congr_cl63_wA_q(1) and not lock_finval) when "00", + (flush_wayA_data2_q(1) and not lock_finval) when "01", + (reload_wayA_data2_q(1) and not lock_finval) when others; +-- WayA Thread 0 Watch Bit Update for Congruence Class 63 +with rel_bixu63_wayA_upd select + congr_cl63_wA_d(2) <= (congr_cl63_wA_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayA_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayA Thread 1 Watch Bit Update for Congruence Class 63 +with rel_bixu63_wayA_upd select + congr_cl63_wA_d(3) <= (congr_cl63_wA_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayA_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayA Thread 2 Watch Bit Update for Congruence Class 63 +with rel_bixu63_wayA_upd select + congr_cl63_wA_d(4) <= (congr_cl63_wA_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayA_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayA Thread 3 Watch Bit Update for Congruence Class 63 +with rel_bixu63_wayA_upd select + congr_cl63_wA_d(5) <= (congr_cl63_wA_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayA_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Write Select for WayB +-- WayB Valid Bit Update for Congruence Class 0 +with rel_bixu0_wayB_upd select + congr_cl0_wB_d(0) <= (congr_cl0_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 0 +with rel_bixu0_wayB_upd select + congr_cl0_wB_d(1) <= (congr_cl0_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayB_upd select + congr_cl0_wB_d(2) <= (congr_cl0_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayB_upd select + congr_cl0_wB_d(3) <= (congr_cl0_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayB_upd select + congr_cl0_wB_d(4) <= (congr_cl0_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayB_upd select + congr_cl0_wB_d(5) <= (congr_cl0_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 1 +with rel_bixu1_wayB_upd select + congr_cl1_wB_d(0) <= (congr_cl1_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 1 +with rel_bixu1_wayB_upd select + congr_cl1_wB_d(1) <= (congr_cl1_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayB_upd select + congr_cl1_wB_d(2) <= (congr_cl1_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayB_upd select + congr_cl1_wB_d(3) <= (congr_cl1_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayB_upd select + congr_cl1_wB_d(4) <= (congr_cl1_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayB_upd select + congr_cl1_wB_d(5) <= (congr_cl1_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 2 +with rel_bixu2_wayB_upd select + congr_cl2_wB_d(0) <= (congr_cl2_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 2 +with rel_bixu2_wayB_upd select + congr_cl2_wB_d(1) <= (congr_cl2_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayB_upd select + congr_cl2_wB_d(2) <= (congr_cl2_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayB_upd select + congr_cl2_wB_d(3) <= (congr_cl2_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayB_upd select + congr_cl2_wB_d(4) <= (congr_cl2_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayB_upd select + congr_cl2_wB_d(5) <= (congr_cl2_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 3 +with rel_bixu3_wayB_upd select + congr_cl3_wB_d(0) <= (congr_cl3_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 3 +with rel_bixu3_wayB_upd select + congr_cl3_wB_d(1) <= (congr_cl3_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayB_upd select + congr_cl3_wB_d(2) <= (congr_cl3_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayB_upd select + congr_cl3_wB_d(3) <= (congr_cl3_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayB_upd select + congr_cl3_wB_d(4) <= (congr_cl3_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayB_upd select + congr_cl3_wB_d(5) <= (congr_cl3_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 4 +with rel_bixu4_wayB_upd select + congr_cl4_wB_d(0) <= (congr_cl4_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 4 +with rel_bixu4_wayB_upd select + congr_cl4_wB_d(1) <= (congr_cl4_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayB_upd select + congr_cl4_wB_d(2) <= (congr_cl4_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayB_upd select + congr_cl4_wB_d(3) <= (congr_cl4_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayB_upd select + congr_cl4_wB_d(4) <= (congr_cl4_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayB_upd select + congr_cl4_wB_d(5) <= (congr_cl4_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 5 +with rel_bixu5_wayB_upd select + congr_cl5_wB_d(0) <= (congr_cl5_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 5 +with rel_bixu5_wayB_upd select + congr_cl5_wB_d(1) <= (congr_cl5_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayB_upd select + congr_cl5_wB_d(2) <= (congr_cl5_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayB_upd select + congr_cl5_wB_d(3) <= (congr_cl5_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayB_upd select + congr_cl5_wB_d(4) <= (congr_cl5_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayB_upd select + congr_cl5_wB_d(5) <= (congr_cl5_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 6 +with rel_bixu6_wayB_upd select + congr_cl6_wB_d(0) <= (congr_cl6_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 6 +with rel_bixu6_wayB_upd select + congr_cl6_wB_d(1) <= (congr_cl6_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayB_upd select + congr_cl6_wB_d(2) <= (congr_cl6_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayB_upd select + congr_cl6_wB_d(3) <= (congr_cl6_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayB_upd select + congr_cl6_wB_d(4) <= (congr_cl6_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayB_upd select + congr_cl6_wB_d(5) <= (congr_cl6_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 7 +with rel_bixu7_wayB_upd select + congr_cl7_wB_d(0) <= (congr_cl7_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 7 +with rel_bixu7_wayB_upd select + congr_cl7_wB_d(1) <= (congr_cl7_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayB_upd select + congr_cl7_wB_d(2) <= (congr_cl7_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayB_upd select + congr_cl7_wB_d(3) <= (congr_cl7_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayB_upd select + congr_cl7_wB_d(4) <= (congr_cl7_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayB_upd select + congr_cl7_wB_d(5) <= (congr_cl7_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 8 +with rel_bixu8_wayB_upd select + congr_cl8_wB_d(0) <= (congr_cl8_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 8 +with rel_bixu8_wayB_upd select + congr_cl8_wB_d(1) <= (congr_cl8_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayB_upd select + congr_cl8_wB_d(2) <= (congr_cl8_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayB_upd select + congr_cl8_wB_d(3) <= (congr_cl8_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayB_upd select + congr_cl8_wB_d(4) <= (congr_cl8_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayB_upd select + congr_cl8_wB_d(5) <= (congr_cl8_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 9 +with rel_bixu9_wayB_upd select + congr_cl9_wB_d(0) <= (congr_cl9_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 9 +with rel_bixu9_wayB_upd select + congr_cl9_wB_d(1) <= (congr_cl9_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayB_upd select + congr_cl9_wB_d(2) <= (congr_cl9_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayB_upd select + congr_cl9_wB_d(3) <= (congr_cl9_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayB_upd select + congr_cl9_wB_d(4) <= (congr_cl9_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayB_upd select + congr_cl9_wB_d(5) <= (congr_cl9_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 10 +with rel_bixu10_wayB_upd select + congr_cl10_wB_d(0) <= (congr_cl10_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 10 +with rel_bixu10_wayB_upd select + congr_cl10_wB_d(1) <= (congr_cl10_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayB_upd select + congr_cl10_wB_d(2) <= (congr_cl10_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayB_upd select + congr_cl10_wB_d(3) <= (congr_cl10_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayB_upd select + congr_cl10_wB_d(4) <= (congr_cl10_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayB_upd select + congr_cl10_wB_d(5) <= (congr_cl10_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 11 +with rel_bixu11_wayB_upd select + congr_cl11_wB_d(0) <= (congr_cl11_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 11 +with rel_bixu11_wayB_upd select + congr_cl11_wB_d(1) <= (congr_cl11_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayB_upd select + congr_cl11_wB_d(2) <= (congr_cl11_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayB_upd select + congr_cl11_wB_d(3) <= (congr_cl11_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayB_upd select + congr_cl11_wB_d(4) <= (congr_cl11_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayB_upd select + congr_cl11_wB_d(5) <= (congr_cl11_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 12 +with rel_bixu12_wayB_upd select + congr_cl12_wB_d(0) <= (congr_cl12_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 12 +with rel_bixu12_wayB_upd select + congr_cl12_wB_d(1) <= (congr_cl12_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayB_upd select + congr_cl12_wB_d(2) <= (congr_cl12_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayB_upd select + congr_cl12_wB_d(3) <= (congr_cl12_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayB_upd select + congr_cl12_wB_d(4) <= (congr_cl12_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayB_upd select + congr_cl12_wB_d(5) <= (congr_cl12_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 13 +with rel_bixu13_wayB_upd select + congr_cl13_wB_d(0) <= (congr_cl13_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 13 +with rel_bixu13_wayB_upd select + congr_cl13_wB_d(1) <= (congr_cl13_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayB_upd select + congr_cl13_wB_d(2) <= (congr_cl13_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayB_upd select + congr_cl13_wB_d(3) <= (congr_cl13_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayB_upd select + congr_cl13_wB_d(4) <= (congr_cl13_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayB_upd select + congr_cl13_wB_d(5) <= (congr_cl13_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 14 +with rel_bixu14_wayB_upd select + congr_cl14_wB_d(0) <= (congr_cl14_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 14 +with rel_bixu14_wayB_upd select + congr_cl14_wB_d(1) <= (congr_cl14_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayB_upd select + congr_cl14_wB_d(2) <= (congr_cl14_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayB_upd select + congr_cl14_wB_d(3) <= (congr_cl14_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayB_upd select + congr_cl14_wB_d(4) <= (congr_cl14_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayB_upd select + congr_cl14_wB_d(5) <= (congr_cl14_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 15 +with rel_bixu15_wayB_upd select + congr_cl15_wB_d(0) <= (congr_cl15_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 15 +with rel_bixu15_wayB_upd select + congr_cl15_wB_d(1) <= (congr_cl15_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayB_upd select + congr_cl15_wB_d(2) <= (congr_cl15_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayB_upd select + congr_cl15_wB_d(3) <= (congr_cl15_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayB_upd select + congr_cl15_wB_d(4) <= (congr_cl15_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayB_upd select + congr_cl15_wB_d(5) <= (congr_cl15_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 16 +with rel_bixu16_wayB_upd select + congr_cl16_wB_d(0) <= (congr_cl16_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 16 +with rel_bixu16_wayB_upd select + congr_cl16_wB_d(1) <= (congr_cl16_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayB_upd select + congr_cl16_wB_d(2) <= (congr_cl16_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayB_upd select + congr_cl16_wB_d(3) <= (congr_cl16_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayB_upd select + congr_cl16_wB_d(4) <= (congr_cl16_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayB_upd select + congr_cl16_wB_d(5) <= (congr_cl16_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 17 +with rel_bixu17_wayB_upd select + congr_cl17_wB_d(0) <= (congr_cl17_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 17 +with rel_bixu17_wayB_upd select + congr_cl17_wB_d(1) <= (congr_cl17_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayB_upd select + congr_cl17_wB_d(2) <= (congr_cl17_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayB_upd select + congr_cl17_wB_d(3) <= (congr_cl17_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayB_upd select + congr_cl17_wB_d(4) <= (congr_cl17_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayB_upd select + congr_cl17_wB_d(5) <= (congr_cl17_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 18 +with rel_bixu18_wayB_upd select + congr_cl18_wB_d(0) <= (congr_cl18_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 18 +with rel_bixu18_wayB_upd select + congr_cl18_wB_d(1) <= (congr_cl18_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayB_upd select + congr_cl18_wB_d(2) <= (congr_cl18_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayB_upd select + congr_cl18_wB_d(3) <= (congr_cl18_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayB_upd select + congr_cl18_wB_d(4) <= (congr_cl18_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayB_upd select + congr_cl18_wB_d(5) <= (congr_cl18_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 19 +with rel_bixu19_wayB_upd select + congr_cl19_wB_d(0) <= (congr_cl19_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 19 +with rel_bixu19_wayB_upd select + congr_cl19_wB_d(1) <= (congr_cl19_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayB_upd select + congr_cl19_wB_d(2) <= (congr_cl19_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayB_upd select + congr_cl19_wB_d(3) <= (congr_cl19_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayB_upd select + congr_cl19_wB_d(4) <= (congr_cl19_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayB_upd select + congr_cl19_wB_d(5) <= (congr_cl19_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 20 +with rel_bixu20_wayB_upd select + congr_cl20_wB_d(0) <= (congr_cl20_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 20 +with rel_bixu20_wayB_upd select + congr_cl20_wB_d(1) <= (congr_cl20_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayB_upd select + congr_cl20_wB_d(2) <= (congr_cl20_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayB_upd select + congr_cl20_wB_d(3) <= (congr_cl20_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayB_upd select + congr_cl20_wB_d(4) <= (congr_cl20_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayB_upd select + congr_cl20_wB_d(5) <= (congr_cl20_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 21 +with rel_bixu21_wayB_upd select + congr_cl21_wB_d(0) <= (congr_cl21_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 21 +with rel_bixu21_wayB_upd select + congr_cl21_wB_d(1) <= (congr_cl21_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayB_upd select + congr_cl21_wB_d(2) <= (congr_cl21_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayB_upd select + congr_cl21_wB_d(3) <= (congr_cl21_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayB_upd select + congr_cl21_wB_d(4) <= (congr_cl21_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayB_upd select + congr_cl21_wB_d(5) <= (congr_cl21_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 22 +with rel_bixu22_wayB_upd select + congr_cl22_wB_d(0) <= (congr_cl22_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 22 +with rel_bixu22_wayB_upd select + congr_cl22_wB_d(1) <= (congr_cl22_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayB_upd select + congr_cl22_wB_d(2) <= (congr_cl22_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayB_upd select + congr_cl22_wB_d(3) <= (congr_cl22_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayB_upd select + congr_cl22_wB_d(4) <= (congr_cl22_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayB_upd select + congr_cl22_wB_d(5) <= (congr_cl22_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 23 +with rel_bixu23_wayB_upd select + congr_cl23_wB_d(0) <= (congr_cl23_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 23 +with rel_bixu23_wayB_upd select + congr_cl23_wB_d(1) <= (congr_cl23_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayB_upd select + congr_cl23_wB_d(2) <= (congr_cl23_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayB_upd select + congr_cl23_wB_d(3) <= (congr_cl23_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayB_upd select + congr_cl23_wB_d(4) <= (congr_cl23_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayB_upd select + congr_cl23_wB_d(5) <= (congr_cl23_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 24 +with rel_bixu24_wayB_upd select + congr_cl24_wB_d(0) <= (congr_cl24_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 24 +with rel_bixu24_wayB_upd select + congr_cl24_wB_d(1) <= (congr_cl24_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayB_upd select + congr_cl24_wB_d(2) <= (congr_cl24_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayB_upd select + congr_cl24_wB_d(3) <= (congr_cl24_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayB_upd select + congr_cl24_wB_d(4) <= (congr_cl24_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayB_upd select + congr_cl24_wB_d(5) <= (congr_cl24_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 25 +with rel_bixu25_wayB_upd select + congr_cl25_wB_d(0) <= (congr_cl25_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 25 +with rel_bixu25_wayB_upd select + congr_cl25_wB_d(1) <= (congr_cl25_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayB_upd select + congr_cl25_wB_d(2) <= (congr_cl25_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayB_upd select + congr_cl25_wB_d(3) <= (congr_cl25_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayB_upd select + congr_cl25_wB_d(4) <= (congr_cl25_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayB_upd select + congr_cl25_wB_d(5) <= (congr_cl25_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 26 +with rel_bixu26_wayB_upd select + congr_cl26_wB_d(0) <= (congr_cl26_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 26 +with rel_bixu26_wayB_upd select + congr_cl26_wB_d(1) <= (congr_cl26_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayB_upd select + congr_cl26_wB_d(2) <= (congr_cl26_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayB_upd select + congr_cl26_wB_d(3) <= (congr_cl26_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayB_upd select + congr_cl26_wB_d(4) <= (congr_cl26_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayB_upd select + congr_cl26_wB_d(5) <= (congr_cl26_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 27 +with rel_bixu27_wayB_upd select + congr_cl27_wB_d(0) <= (congr_cl27_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 27 +with rel_bixu27_wayB_upd select + congr_cl27_wB_d(1) <= (congr_cl27_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayB_upd select + congr_cl27_wB_d(2) <= (congr_cl27_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayB_upd select + congr_cl27_wB_d(3) <= (congr_cl27_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayB_upd select + congr_cl27_wB_d(4) <= (congr_cl27_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayB_upd select + congr_cl27_wB_d(5) <= (congr_cl27_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 28 +with rel_bixu28_wayB_upd select + congr_cl28_wB_d(0) <= (congr_cl28_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 28 +with rel_bixu28_wayB_upd select + congr_cl28_wB_d(1) <= (congr_cl28_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayB_upd select + congr_cl28_wB_d(2) <= (congr_cl28_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayB_upd select + congr_cl28_wB_d(3) <= (congr_cl28_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayB_upd select + congr_cl28_wB_d(4) <= (congr_cl28_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayB_upd select + congr_cl28_wB_d(5) <= (congr_cl28_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 29 +with rel_bixu29_wayB_upd select + congr_cl29_wB_d(0) <= (congr_cl29_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 29 +with rel_bixu29_wayB_upd select + congr_cl29_wB_d(1) <= (congr_cl29_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayB_upd select + congr_cl29_wB_d(2) <= (congr_cl29_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayB_upd select + congr_cl29_wB_d(3) <= (congr_cl29_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayB_upd select + congr_cl29_wB_d(4) <= (congr_cl29_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayB_upd select + congr_cl29_wB_d(5) <= (congr_cl29_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 30 +with rel_bixu30_wayB_upd select + congr_cl30_wB_d(0) <= (congr_cl30_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 30 +with rel_bixu30_wayB_upd select + congr_cl30_wB_d(1) <= (congr_cl30_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayB_upd select + congr_cl30_wB_d(2) <= (congr_cl30_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayB_upd select + congr_cl30_wB_d(3) <= (congr_cl30_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayB_upd select + congr_cl30_wB_d(4) <= (congr_cl30_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayB_upd select + congr_cl30_wB_d(5) <= (congr_cl30_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 31 +with rel_bixu31_wayB_upd select + congr_cl31_wB_d(0) <= (congr_cl31_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 31 +with rel_bixu31_wayB_upd select + congr_cl31_wB_d(1) <= (congr_cl31_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayB_upd select + congr_cl31_wB_d(2) <= (congr_cl31_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayB_upd select + congr_cl31_wB_d(3) <= (congr_cl31_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayB_upd select + congr_cl31_wB_d(4) <= (congr_cl31_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayB_upd select + congr_cl31_wB_d(5) <= (congr_cl31_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 32 +with rel_bixu32_wayB_upd select + congr_cl32_wB_d(0) <= (congr_cl32_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 32 +with rel_bixu32_wayB_upd select + congr_cl32_wB_d(1) <= (congr_cl32_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 32 +with rel_bixu32_wayB_upd select + congr_cl32_wB_d(2) <= (congr_cl32_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 32 +with rel_bixu32_wayB_upd select + congr_cl32_wB_d(3) <= (congr_cl32_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 32 +with rel_bixu32_wayB_upd select + congr_cl32_wB_d(4) <= (congr_cl32_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 32 +with rel_bixu32_wayB_upd select + congr_cl32_wB_d(5) <= (congr_cl32_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 33 +with rel_bixu33_wayB_upd select + congr_cl33_wB_d(0) <= (congr_cl33_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 33 +with rel_bixu33_wayB_upd select + congr_cl33_wB_d(1) <= (congr_cl33_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 33 +with rel_bixu33_wayB_upd select + congr_cl33_wB_d(2) <= (congr_cl33_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 33 +with rel_bixu33_wayB_upd select + congr_cl33_wB_d(3) <= (congr_cl33_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 33 +with rel_bixu33_wayB_upd select + congr_cl33_wB_d(4) <= (congr_cl33_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 33 +with rel_bixu33_wayB_upd select + congr_cl33_wB_d(5) <= (congr_cl33_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 34 +with rel_bixu34_wayB_upd select + congr_cl34_wB_d(0) <= (congr_cl34_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 34 +with rel_bixu34_wayB_upd select + congr_cl34_wB_d(1) <= (congr_cl34_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 34 +with rel_bixu34_wayB_upd select + congr_cl34_wB_d(2) <= (congr_cl34_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 34 +with rel_bixu34_wayB_upd select + congr_cl34_wB_d(3) <= (congr_cl34_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 34 +with rel_bixu34_wayB_upd select + congr_cl34_wB_d(4) <= (congr_cl34_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 34 +with rel_bixu34_wayB_upd select + congr_cl34_wB_d(5) <= (congr_cl34_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 35 +with rel_bixu35_wayB_upd select + congr_cl35_wB_d(0) <= (congr_cl35_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 35 +with rel_bixu35_wayB_upd select + congr_cl35_wB_d(1) <= (congr_cl35_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 35 +with rel_bixu35_wayB_upd select + congr_cl35_wB_d(2) <= (congr_cl35_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 35 +with rel_bixu35_wayB_upd select + congr_cl35_wB_d(3) <= (congr_cl35_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 35 +with rel_bixu35_wayB_upd select + congr_cl35_wB_d(4) <= (congr_cl35_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 35 +with rel_bixu35_wayB_upd select + congr_cl35_wB_d(5) <= (congr_cl35_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 36 +with rel_bixu36_wayB_upd select + congr_cl36_wB_d(0) <= (congr_cl36_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 36 +with rel_bixu36_wayB_upd select + congr_cl36_wB_d(1) <= (congr_cl36_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 36 +with rel_bixu36_wayB_upd select + congr_cl36_wB_d(2) <= (congr_cl36_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 36 +with rel_bixu36_wayB_upd select + congr_cl36_wB_d(3) <= (congr_cl36_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 36 +with rel_bixu36_wayB_upd select + congr_cl36_wB_d(4) <= (congr_cl36_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 36 +with rel_bixu36_wayB_upd select + congr_cl36_wB_d(5) <= (congr_cl36_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 37 +with rel_bixu37_wayB_upd select + congr_cl37_wB_d(0) <= (congr_cl37_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 37 +with rel_bixu37_wayB_upd select + congr_cl37_wB_d(1) <= (congr_cl37_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 37 +with rel_bixu37_wayB_upd select + congr_cl37_wB_d(2) <= (congr_cl37_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 37 +with rel_bixu37_wayB_upd select + congr_cl37_wB_d(3) <= (congr_cl37_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 37 +with rel_bixu37_wayB_upd select + congr_cl37_wB_d(4) <= (congr_cl37_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 37 +with rel_bixu37_wayB_upd select + congr_cl37_wB_d(5) <= (congr_cl37_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 38 +with rel_bixu38_wayB_upd select + congr_cl38_wB_d(0) <= (congr_cl38_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 38 +with rel_bixu38_wayB_upd select + congr_cl38_wB_d(1) <= (congr_cl38_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 38 +with rel_bixu38_wayB_upd select + congr_cl38_wB_d(2) <= (congr_cl38_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 38 +with rel_bixu38_wayB_upd select + congr_cl38_wB_d(3) <= (congr_cl38_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 38 +with rel_bixu38_wayB_upd select + congr_cl38_wB_d(4) <= (congr_cl38_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 38 +with rel_bixu38_wayB_upd select + congr_cl38_wB_d(5) <= (congr_cl38_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 39 +with rel_bixu39_wayB_upd select + congr_cl39_wB_d(0) <= (congr_cl39_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 39 +with rel_bixu39_wayB_upd select + congr_cl39_wB_d(1) <= (congr_cl39_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 39 +with rel_bixu39_wayB_upd select + congr_cl39_wB_d(2) <= (congr_cl39_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 39 +with rel_bixu39_wayB_upd select + congr_cl39_wB_d(3) <= (congr_cl39_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 39 +with rel_bixu39_wayB_upd select + congr_cl39_wB_d(4) <= (congr_cl39_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 39 +with rel_bixu39_wayB_upd select + congr_cl39_wB_d(5) <= (congr_cl39_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 40 +with rel_bixu40_wayB_upd select + congr_cl40_wB_d(0) <= (congr_cl40_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 40 +with rel_bixu40_wayB_upd select + congr_cl40_wB_d(1) <= (congr_cl40_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 40 +with rel_bixu40_wayB_upd select + congr_cl40_wB_d(2) <= (congr_cl40_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 40 +with rel_bixu40_wayB_upd select + congr_cl40_wB_d(3) <= (congr_cl40_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 40 +with rel_bixu40_wayB_upd select + congr_cl40_wB_d(4) <= (congr_cl40_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 40 +with rel_bixu40_wayB_upd select + congr_cl40_wB_d(5) <= (congr_cl40_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 41 +with rel_bixu41_wayB_upd select + congr_cl41_wB_d(0) <= (congr_cl41_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 41 +with rel_bixu41_wayB_upd select + congr_cl41_wB_d(1) <= (congr_cl41_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 41 +with rel_bixu41_wayB_upd select + congr_cl41_wB_d(2) <= (congr_cl41_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 41 +with rel_bixu41_wayB_upd select + congr_cl41_wB_d(3) <= (congr_cl41_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 41 +with rel_bixu41_wayB_upd select + congr_cl41_wB_d(4) <= (congr_cl41_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 41 +with rel_bixu41_wayB_upd select + congr_cl41_wB_d(5) <= (congr_cl41_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 42 +with rel_bixu42_wayB_upd select + congr_cl42_wB_d(0) <= (congr_cl42_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 42 +with rel_bixu42_wayB_upd select + congr_cl42_wB_d(1) <= (congr_cl42_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 42 +with rel_bixu42_wayB_upd select + congr_cl42_wB_d(2) <= (congr_cl42_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 42 +with rel_bixu42_wayB_upd select + congr_cl42_wB_d(3) <= (congr_cl42_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 42 +with rel_bixu42_wayB_upd select + congr_cl42_wB_d(4) <= (congr_cl42_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 42 +with rel_bixu42_wayB_upd select + congr_cl42_wB_d(5) <= (congr_cl42_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 43 +with rel_bixu43_wayB_upd select + congr_cl43_wB_d(0) <= (congr_cl43_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 43 +with rel_bixu43_wayB_upd select + congr_cl43_wB_d(1) <= (congr_cl43_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 43 +with rel_bixu43_wayB_upd select + congr_cl43_wB_d(2) <= (congr_cl43_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 43 +with rel_bixu43_wayB_upd select + congr_cl43_wB_d(3) <= (congr_cl43_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 43 +with rel_bixu43_wayB_upd select + congr_cl43_wB_d(4) <= (congr_cl43_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 43 +with rel_bixu43_wayB_upd select + congr_cl43_wB_d(5) <= (congr_cl43_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 44 +with rel_bixu44_wayB_upd select + congr_cl44_wB_d(0) <= (congr_cl44_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 44 +with rel_bixu44_wayB_upd select + congr_cl44_wB_d(1) <= (congr_cl44_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 44 +with rel_bixu44_wayB_upd select + congr_cl44_wB_d(2) <= (congr_cl44_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 44 +with rel_bixu44_wayB_upd select + congr_cl44_wB_d(3) <= (congr_cl44_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 44 +with rel_bixu44_wayB_upd select + congr_cl44_wB_d(4) <= (congr_cl44_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 44 +with rel_bixu44_wayB_upd select + congr_cl44_wB_d(5) <= (congr_cl44_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 45 +with rel_bixu45_wayB_upd select + congr_cl45_wB_d(0) <= (congr_cl45_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 45 +with rel_bixu45_wayB_upd select + congr_cl45_wB_d(1) <= (congr_cl45_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 45 +with rel_bixu45_wayB_upd select + congr_cl45_wB_d(2) <= (congr_cl45_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 45 +with rel_bixu45_wayB_upd select + congr_cl45_wB_d(3) <= (congr_cl45_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 45 +with rel_bixu45_wayB_upd select + congr_cl45_wB_d(4) <= (congr_cl45_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 45 +with rel_bixu45_wayB_upd select + congr_cl45_wB_d(5) <= (congr_cl45_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 46 +with rel_bixu46_wayB_upd select + congr_cl46_wB_d(0) <= (congr_cl46_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 46 +with rel_bixu46_wayB_upd select + congr_cl46_wB_d(1) <= (congr_cl46_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 46 +with rel_bixu46_wayB_upd select + congr_cl46_wB_d(2) <= (congr_cl46_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 46 +with rel_bixu46_wayB_upd select + congr_cl46_wB_d(3) <= (congr_cl46_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 46 +with rel_bixu46_wayB_upd select + congr_cl46_wB_d(4) <= (congr_cl46_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 46 +with rel_bixu46_wayB_upd select + congr_cl46_wB_d(5) <= (congr_cl46_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 47 +with rel_bixu47_wayB_upd select + congr_cl47_wB_d(0) <= (congr_cl47_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 47 +with rel_bixu47_wayB_upd select + congr_cl47_wB_d(1) <= (congr_cl47_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 47 +with rel_bixu47_wayB_upd select + congr_cl47_wB_d(2) <= (congr_cl47_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 47 +with rel_bixu47_wayB_upd select + congr_cl47_wB_d(3) <= (congr_cl47_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 47 +with rel_bixu47_wayB_upd select + congr_cl47_wB_d(4) <= (congr_cl47_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 47 +with rel_bixu47_wayB_upd select + congr_cl47_wB_d(5) <= (congr_cl47_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 48 +with rel_bixu48_wayB_upd select + congr_cl48_wB_d(0) <= (congr_cl48_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 48 +with rel_bixu48_wayB_upd select + congr_cl48_wB_d(1) <= (congr_cl48_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 48 +with rel_bixu48_wayB_upd select + congr_cl48_wB_d(2) <= (congr_cl48_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 48 +with rel_bixu48_wayB_upd select + congr_cl48_wB_d(3) <= (congr_cl48_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 48 +with rel_bixu48_wayB_upd select + congr_cl48_wB_d(4) <= (congr_cl48_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 48 +with rel_bixu48_wayB_upd select + congr_cl48_wB_d(5) <= (congr_cl48_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 49 +with rel_bixu49_wayB_upd select + congr_cl49_wB_d(0) <= (congr_cl49_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 49 +with rel_bixu49_wayB_upd select + congr_cl49_wB_d(1) <= (congr_cl49_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 49 +with rel_bixu49_wayB_upd select + congr_cl49_wB_d(2) <= (congr_cl49_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 49 +with rel_bixu49_wayB_upd select + congr_cl49_wB_d(3) <= (congr_cl49_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 49 +with rel_bixu49_wayB_upd select + congr_cl49_wB_d(4) <= (congr_cl49_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 49 +with rel_bixu49_wayB_upd select + congr_cl49_wB_d(5) <= (congr_cl49_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 50 +with rel_bixu50_wayB_upd select + congr_cl50_wB_d(0) <= (congr_cl50_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 50 +with rel_bixu50_wayB_upd select + congr_cl50_wB_d(1) <= (congr_cl50_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 50 +with rel_bixu50_wayB_upd select + congr_cl50_wB_d(2) <= (congr_cl50_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 50 +with rel_bixu50_wayB_upd select + congr_cl50_wB_d(3) <= (congr_cl50_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 50 +with rel_bixu50_wayB_upd select + congr_cl50_wB_d(4) <= (congr_cl50_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 50 +with rel_bixu50_wayB_upd select + congr_cl50_wB_d(5) <= (congr_cl50_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 51 +with rel_bixu51_wayB_upd select + congr_cl51_wB_d(0) <= (congr_cl51_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 51 +with rel_bixu51_wayB_upd select + congr_cl51_wB_d(1) <= (congr_cl51_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 51 +with rel_bixu51_wayB_upd select + congr_cl51_wB_d(2) <= (congr_cl51_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 51 +with rel_bixu51_wayB_upd select + congr_cl51_wB_d(3) <= (congr_cl51_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 51 +with rel_bixu51_wayB_upd select + congr_cl51_wB_d(4) <= (congr_cl51_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 51 +with rel_bixu51_wayB_upd select + congr_cl51_wB_d(5) <= (congr_cl51_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 52 +with rel_bixu52_wayB_upd select + congr_cl52_wB_d(0) <= (congr_cl52_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 52 +with rel_bixu52_wayB_upd select + congr_cl52_wB_d(1) <= (congr_cl52_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 52 +with rel_bixu52_wayB_upd select + congr_cl52_wB_d(2) <= (congr_cl52_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 52 +with rel_bixu52_wayB_upd select + congr_cl52_wB_d(3) <= (congr_cl52_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 52 +with rel_bixu52_wayB_upd select + congr_cl52_wB_d(4) <= (congr_cl52_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 52 +with rel_bixu52_wayB_upd select + congr_cl52_wB_d(5) <= (congr_cl52_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 53 +with rel_bixu53_wayB_upd select + congr_cl53_wB_d(0) <= (congr_cl53_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 53 +with rel_bixu53_wayB_upd select + congr_cl53_wB_d(1) <= (congr_cl53_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 53 +with rel_bixu53_wayB_upd select + congr_cl53_wB_d(2) <= (congr_cl53_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 53 +with rel_bixu53_wayB_upd select + congr_cl53_wB_d(3) <= (congr_cl53_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 53 +with rel_bixu53_wayB_upd select + congr_cl53_wB_d(4) <= (congr_cl53_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 53 +with rel_bixu53_wayB_upd select + congr_cl53_wB_d(5) <= (congr_cl53_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 54 +with rel_bixu54_wayB_upd select + congr_cl54_wB_d(0) <= (congr_cl54_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 54 +with rel_bixu54_wayB_upd select + congr_cl54_wB_d(1) <= (congr_cl54_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 54 +with rel_bixu54_wayB_upd select + congr_cl54_wB_d(2) <= (congr_cl54_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 54 +with rel_bixu54_wayB_upd select + congr_cl54_wB_d(3) <= (congr_cl54_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 54 +with rel_bixu54_wayB_upd select + congr_cl54_wB_d(4) <= (congr_cl54_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 54 +with rel_bixu54_wayB_upd select + congr_cl54_wB_d(5) <= (congr_cl54_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 55 +with rel_bixu55_wayB_upd select + congr_cl55_wB_d(0) <= (congr_cl55_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 55 +with rel_bixu55_wayB_upd select + congr_cl55_wB_d(1) <= (congr_cl55_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 55 +with rel_bixu55_wayB_upd select + congr_cl55_wB_d(2) <= (congr_cl55_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 55 +with rel_bixu55_wayB_upd select + congr_cl55_wB_d(3) <= (congr_cl55_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 55 +with rel_bixu55_wayB_upd select + congr_cl55_wB_d(4) <= (congr_cl55_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 55 +with rel_bixu55_wayB_upd select + congr_cl55_wB_d(5) <= (congr_cl55_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 56 +with rel_bixu56_wayB_upd select + congr_cl56_wB_d(0) <= (congr_cl56_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 56 +with rel_bixu56_wayB_upd select + congr_cl56_wB_d(1) <= (congr_cl56_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 56 +with rel_bixu56_wayB_upd select + congr_cl56_wB_d(2) <= (congr_cl56_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 56 +with rel_bixu56_wayB_upd select + congr_cl56_wB_d(3) <= (congr_cl56_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 56 +with rel_bixu56_wayB_upd select + congr_cl56_wB_d(4) <= (congr_cl56_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 56 +with rel_bixu56_wayB_upd select + congr_cl56_wB_d(5) <= (congr_cl56_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 57 +with rel_bixu57_wayB_upd select + congr_cl57_wB_d(0) <= (congr_cl57_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 57 +with rel_bixu57_wayB_upd select + congr_cl57_wB_d(1) <= (congr_cl57_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 57 +with rel_bixu57_wayB_upd select + congr_cl57_wB_d(2) <= (congr_cl57_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 57 +with rel_bixu57_wayB_upd select + congr_cl57_wB_d(3) <= (congr_cl57_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 57 +with rel_bixu57_wayB_upd select + congr_cl57_wB_d(4) <= (congr_cl57_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 57 +with rel_bixu57_wayB_upd select + congr_cl57_wB_d(5) <= (congr_cl57_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 58 +with rel_bixu58_wayB_upd select + congr_cl58_wB_d(0) <= (congr_cl58_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 58 +with rel_bixu58_wayB_upd select + congr_cl58_wB_d(1) <= (congr_cl58_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 58 +with rel_bixu58_wayB_upd select + congr_cl58_wB_d(2) <= (congr_cl58_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 58 +with rel_bixu58_wayB_upd select + congr_cl58_wB_d(3) <= (congr_cl58_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 58 +with rel_bixu58_wayB_upd select + congr_cl58_wB_d(4) <= (congr_cl58_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 58 +with rel_bixu58_wayB_upd select + congr_cl58_wB_d(5) <= (congr_cl58_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 59 +with rel_bixu59_wayB_upd select + congr_cl59_wB_d(0) <= (congr_cl59_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 59 +with rel_bixu59_wayB_upd select + congr_cl59_wB_d(1) <= (congr_cl59_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 59 +with rel_bixu59_wayB_upd select + congr_cl59_wB_d(2) <= (congr_cl59_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 59 +with rel_bixu59_wayB_upd select + congr_cl59_wB_d(3) <= (congr_cl59_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 59 +with rel_bixu59_wayB_upd select + congr_cl59_wB_d(4) <= (congr_cl59_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 59 +with rel_bixu59_wayB_upd select + congr_cl59_wB_d(5) <= (congr_cl59_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 60 +with rel_bixu60_wayB_upd select + congr_cl60_wB_d(0) <= (congr_cl60_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 60 +with rel_bixu60_wayB_upd select + congr_cl60_wB_d(1) <= (congr_cl60_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 60 +with rel_bixu60_wayB_upd select + congr_cl60_wB_d(2) <= (congr_cl60_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 60 +with rel_bixu60_wayB_upd select + congr_cl60_wB_d(3) <= (congr_cl60_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 60 +with rel_bixu60_wayB_upd select + congr_cl60_wB_d(4) <= (congr_cl60_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 60 +with rel_bixu60_wayB_upd select + congr_cl60_wB_d(5) <= (congr_cl60_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 61 +with rel_bixu61_wayB_upd select + congr_cl61_wB_d(0) <= (congr_cl61_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 61 +with rel_bixu61_wayB_upd select + congr_cl61_wB_d(1) <= (congr_cl61_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 61 +with rel_bixu61_wayB_upd select + congr_cl61_wB_d(2) <= (congr_cl61_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 61 +with rel_bixu61_wayB_upd select + congr_cl61_wB_d(3) <= (congr_cl61_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 61 +with rel_bixu61_wayB_upd select + congr_cl61_wB_d(4) <= (congr_cl61_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 61 +with rel_bixu61_wayB_upd select + congr_cl61_wB_d(5) <= (congr_cl61_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 62 +with rel_bixu62_wayB_upd select + congr_cl62_wB_d(0) <= (congr_cl62_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 62 +with rel_bixu62_wayB_upd select + congr_cl62_wB_d(1) <= (congr_cl62_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 62 +with rel_bixu62_wayB_upd select + congr_cl62_wB_d(2) <= (congr_cl62_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 62 +with rel_bixu62_wayB_upd select + congr_cl62_wB_d(3) <= (congr_cl62_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 62 +with rel_bixu62_wayB_upd select + congr_cl62_wB_d(4) <= (congr_cl62_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 62 +with rel_bixu62_wayB_upd select + congr_cl62_wB_d(5) <= (congr_cl62_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayB Valid Bit Update for Congruence Class 63 +with rel_bixu63_wayB_upd select + congr_cl63_wB_d(0) <= (congr_cl63_wB_q(0) and not dci_inval_all_q) when "00", + (flush_wayB_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayB_data2_q(0) and not dci_inval_all_q) when others; +-- WayB Lock Bit Update for Congruence Class 63 +with rel_bixu63_wayB_upd select + congr_cl63_wB_d(1) <= (congr_cl63_wB_q(1) and not lock_finval) when "00", + (flush_wayB_data2_q(1) and not lock_finval) when "01", + (reload_wayB_data2_q(1) and not lock_finval) when others; +-- WayB Thread 0 Watch Bit Update for Congruence Class 63 +with rel_bixu63_wayB_upd select + congr_cl63_wB_d(2) <= (congr_cl63_wB_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayB_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayB Thread 1 Watch Bit Update for Congruence Class 63 +with rel_bixu63_wayB_upd select + congr_cl63_wB_d(3) <= (congr_cl63_wB_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayB_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayB Thread 2 Watch Bit Update for Congruence Class 63 +with rel_bixu63_wayB_upd select + congr_cl63_wB_d(4) <= (congr_cl63_wB_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayB_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayB Thread 3 Watch Bit Update for Congruence Class 63 +with rel_bixu63_wayB_upd select + congr_cl63_wB_d(5) <= (congr_cl63_wB_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayB_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Write Select for WayC +-- WayC Valid Bit Update for Congruence Class 0 +with rel_bixu0_wayC_upd select + congr_cl0_wC_d(0) <= (congr_cl0_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 0 +with rel_bixu0_wayC_upd select + congr_cl0_wC_d(1) <= (congr_cl0_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayC_upd select + congr_cl0_wC_d(2) <= (congr_cl0_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayC_upd select + congr_cl0_wC_d(3) <= (congr_cl0_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayC_upd select + congr_cl0_wC_d(4) <= (congr_cl0_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayC_upd select + congr_cl0_wC_d(5) <= (congr_cl0_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 1 +with rel_bixu1_wayC_upd select + congr_cl1_wC_d(0) <= (congr_cl1_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 1 +with rel_bixu1_wayC_upd select + congr_cl1_wC_d(1) <= (congr_cl1_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayC_upd select + congr_cl1_wC_d(2) <= (congr_cl1_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayC_upd select + congr_cl1_wC_d(3) <= (congr_cl1_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayC_upd select + congr_cl1_wC_d(4) <= (congr_cl1_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayC_upd select + congr_cl1_wC_d(5) <= (congr_cl1_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 2 +with rel_bixu2_wayC_upd select + congr_cl2_wC_d(0) <= (congr_cl2_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 2 +with rel_bixu2_wayC_upd select + congr_cl2_wC_d(1) <= (congr_cl2_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayC_upd select + congr_cl2_wC_d(2) <= (congr_cl2_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayC_upd select + congr_cl2_wC_d(3) <= (congr_cl2_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayC_upd select + congr_cl2_wC_d(4) <= (congr_cl2_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayC_upd select + congr_cl2_wC_d(5) <= (congr_cl2_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 3 +with rel_bixu3_wayC_upd select + congr_cl3_wC_d(0) <= (congr_cl3_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 3 +with rel_bixu3_wayC_upd select + congr_cl3_wC_d(1) <= (congr_cl3_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayC_upd select + congr_cl3_wC_d(2) <= (congr_cl3_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayC_upd select + congr_cl3_wC_d(3) <= (congr_cl3_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayC_upd select + congr_cl3_wC_d(4) <= (congr_cl3_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayC_upd select + congr_cl3_wC_d(5) <= (congr_cl3_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 4 +with rel_bixu4_wayC_upd select + congr_cl4_wC_d(0) <= (congr_cl4_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 4 +with rel_bixu4_wayC_upd select + congr_cl4_wC_d(1) <= (congr_cl4_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayC_upd select + congr_cl4_wC_d(2) <= (congr_cl4_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayC_upd select + congr_cl4_wC_d(3) <= (congr_cl4_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayC_upd select + congr_cl4_wC_d(4) <= (congr_cl4_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayC_upd select + congr_cl4_wC_d(5) <= (congr_cl4_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 5 +with rel_bixu5_wayC_upd select + congr_cl5_wC_d(0) <= (congr_cl5_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 5 +with rel_bixu5_wayC_upd select + congr_cl5_wC_d(1) <= (congr_cl5_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayC_upd select + congr_cl5_wC_d(2) <= (congr_cl5_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayC_upd select + congr_cl5_wC_d(3) <= (congr_cl5_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayC_upd select + congr_cl5_wC_d(4) <= (congr_cl5_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayC_upd select + congr_cl5_wC_d(5) <= (congr_cl5_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 6 +with rel_bixu6_wayC_upd select + congr_cl6_wC_d(0) <= (congr_cl6_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 6 +with rel_bixu6_wayC_upd select + congr_cl6_wC_d(1) <= (congr_cl6_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayC_upd select + congr_cl6_wC_d(2) <= (congr_cl6_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayC_upd select + congr_cl6_wC_d(3) <= (congr_cl6_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayC_upd select + congr_cl6_wC_d(4) <= (congr_cl6_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayC_upd select + congr_cl6_wC_d(5) <= (congr_cl6_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 7 +with rel_bixu7_wayC_upd select + congr_cl7_wC_d(0) <= (congr_cl7_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 7 +with rel_bixu7_wayC_upd select + congr_cl7_wC_d(1) <= (congr_cl7_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayC_upd select + congr_cl7_wC_d(2) <= (congr_cl7_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayC_upd select + congr_cl7_wC_d(3) <= (congr_cl7_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayC_upd select + congr_cl7_wC_d(4) <= (congr_cl7_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayC_upd select + congr_cl7_wC_d(5) <= (congr_cl7_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 8 +with rel_bixu8_wayC_upd select + congr_cl8_wC_d(0) <= (congr_cl8_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 8 +with rel_bixu8_wayC_upd select + congr_cl8_wC_d(1) <= (congr_cl8_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayC_upd select + congr_cl8_wC_d(2) <= (congr_cl8_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayC_upd select + congr_cl8_wC_d(3) <= (congr_cl8_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayC_upd select + congr_cl8_wC_d(4) <= (congr_cl8_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayC_upd select + congr_cl8_wC_d(5) <= (congr_cl8_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 9 +with rel_bixu9_wayC_upd select + congr_cl9_wC_d(0) <= (congr_cl9_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 9 +with rel_bixu9_wayC_upd select + congr_cl9_wC_d(1) <= (congr_cl9_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayC_upd select + congr_cl9_wC_d(2) <= (congr_cl9_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayC_upd select + congr_cl9_wC_d(3) <= (congr_cl9_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayC_upd select + congr_cl9_wC_d(4) <= (congr_cl9_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayC_upd select + congr_cl9_wC_d(5) <= (congr_cl9_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 10 +with rel_bixu10_wayC_upd select + congr_cl10_wC_d(0) <= (congr_cl10_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 10 +with rel_bixu10_wayC_upd select + congr_cl10_wC_d(1) <= (congr_cl10_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayC_upd select + congr_cl10_wC_d(2) <= (congr_cl10_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayC_upd select + congr_cl10_wC_d(3) <= (congr_cl10_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayC_upd select + congr_cl10_wC_d(4) <= (congr_cl10_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayC_upd select + congr_cl10_wC_d(5) <= (congr_cl10_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 11 +with rel_bixu11_wayC_upd select + congr_cl11_wC_d(0) <= (congr_cl11_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 11 +with rel_bixu11_wayC_upd select + congr_cl11_wC_d(1) <= (congr_cl11_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayC_upd select + congr_cl11_wC_d(2) <= (congr_cl11_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayC_upd select + congr_cl11_wC_d(3) <= (congr_cl11_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayC_upd select + congr_cl11_wC_d(4) <= (congr_cl11_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayC_upd select + congr_cl11_wC_d(5) <= (congr_cl11_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 12 +with rel_bixu12_wayC_upd select + congr_cl12_wC_d(0) <= (congr_cl12_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 12 +with rel_bixu12_wayC_upd select + congr_cl12_wC_d(1) <= (congr_cl12_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayC_upd select + congr_cl12_wC_d(2) <= (congr_cl12_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayC_upd select + congr_cl12_wC_d(3) <= (congr_cl12_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayC_upd select + congr_cl12_wC_d(4) <= (congr_cl12_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayC_upd select + congr_cl12_wC_d(5) <= (congr_cl12_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 13 +with rel_bixu13_wayC_upd select + congr_cl13_wC_d(0) <= (congr_cl13_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 13 +with rel_bixu13_wayC_upd select + congr_cl13_wC_d(1) <= (congr_cl13_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayC_upd select + congr_cl13_wC_d(2) <= (congr_cl13_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayC_upd select + congr_cl13_wC_d(3) <= (congr_cl13_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayC_upd select + congr_cl13_wC_d(4) <= (congr_cl13_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayC_upd select + congr_cl13_wC_d(5) <= (congr_cl13_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 14 +with rel_bixu14_wayC_upd select + congr_cl14_wC_d(0) <= (congr_cl14_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 14 +with rel_bixu14_wayC_upd select + congr_cl14_wC_d(1) <= (congr_cl14_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayC_upd select + congr_cl14_wC_d(2) <= (congr_cl14_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayC_upd select + congr_cl14_wC_d(3) <= (congr_cl14_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayC_upd select + congr_cl14_wC_d(4) <= (congr_cl14_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayC_upd select + congr_cl14_wC_d(5) <= (congr_cl14_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 15 +with rel_bixu15_wayC_upd select + congr_cl15_wC_d(0) <= (congr_cl15_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 15 +with rel_bixu15_wayC_upd select + congr_cl15_wC_d(1) <= (congr_cl15_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayC_upd select + congr_cl15_wC_d(2) <= (congr_cl15_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayC_upd select + congr_cl15_wC_d(3) <= (congr_cl15_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayC_upd select + congr_cl15_wC_d(4) <= (congr_cl15_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayC_upd select + congr_cl15_wC_d(5) <= (congr_cl15_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 16 +with rel_bixu16_wayC_upd select + congr_cl16_wC_d(0) <= (congr_cl16_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 16 +with rel_bixu16_wayC_upd select + congr_cl16_wC_d(1) <= (congr_cl16_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayC_upd select + congr_cl16_wC_d(2) <= (congr_cl16_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayC_upd select + congr_cl16_wC_d(3) <= (congr_cl16_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayC_upd select + congr_cl16_wC_d(4) <= (congr_cl16_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayC_upd select + congr_cl16_wC_d(5) <= (congr_cl16_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 17 +with rel_bixu17_wayC_upd select + congr_cl17_wC_d(0) <= (congr_cl17_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 17 +with rel_bixu17_wayC_upd select + congr_cl17_wC_d(1) <= (congr_cl17_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayC_upd select + congr_cl17_wC_d(2) <= (congr_cl17_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayC_upd select + congr_cl17_wC_d(3) <= (congr_cl17_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayC_upd select + congr_cl17_wC_d(4) <= (congr_cl17_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayC_upd select + congr_cl17_wC_d(5) <= (congr_cl17_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 18 +with rel_bixu18_wayC_upd select + congr_cl18_wC_d(0) <= (congr_cl18_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 18 +with rel_bixu18_wayC_upd select + congr_cl18_wC_d(1) <= (congr_cl18_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayC_upd select + congr_cl18_wC_d(2) <= (congr_cl18_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayC_upd select + congr_cl18_wC_d(3) <= (congr_cl18_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayC_upd select + congr_cl18_wC_d(4) <= (congr_cl18_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayC_upd select + congr_cl18_wC_d(5) <= (congr_cl18_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 19 +with rel_bixu19_wayC_upd select + congr_cl19_wC_d(0) <= (congr_cl19_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 19 +with rel_bixu19_wayC_upd select + congr_cl19_wC_d(1) <= (congr_cl19_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayC_upd select + congr_cl19_wC_d(2) <= (congr_cl19_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayC_upd select + congr_cl19_wC_d(3) <= (congr_cl19_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayC_upd select + congr_cl19_wC_d(4) <= (congr_cl19_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayC_upd select + congr_cl19_wC_d(5) <= (congr_cl19_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 20 +with rel_bixu20_wayC_upd select + congr_cl20_wC_d(0) <= (congr_cl20_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 20 +with rel_bixu20_wayC_upd select + congr_cl20_wC_d(1) <= (congr_cl20_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayC_upd select + congr_cl20_wC_d(2) <= (congr_cl20_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayC_upd select + congr_cl20_wC_d(3) <= (congr_cl20_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayC_upd select + congr_cl20_wC_d(4) <= (congr_cl20_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayC_upd select + congr_cl20_wC_d(5) <= (congr_cl20_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 21 +with rel_bixu21_wayC_upd select + congr_cl21_wC_d(0) <= (congr_cl21_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 21 +with rel_bixu21_wayC_upd select + congr_cl21_wC_d(1) <= (congr_cl21_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayC_upd select + congr_cl21_wC_d(2) <= (congr_cl21_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayC_upd select + congr_cl21_wC_d(3) <= (congr_cl21_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayC_upd select + congr_cl21_wC_d(4) <= (congr_cl21_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayC_upd select + congr_cl21_wC_d(5) <= (congr_cl21_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 22 +with rel_bixu22_wayC_upd select + congr_cl22_wC_d(0) <= (congr_cl22_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 22 +with rel_bixu22_wayC_upd select + congr_cl22_wC_d(1) <= (congr_cl22_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayC_upd select + congr_cl22_wC_d(2) <= (congr_cl22_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayC_upd select + congr_cl22_wC_d(3) <= (congr_cl22_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayC_upd select + congr_cl22_wC_d(4) <= (congr_cl22_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayC_upd select + congr_cl22_wC_d(5) <= (congr_cl22_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 23 +with rel_bixu23_wayC_upd select + congr_cl23_wC_d(0) <= (congr_cl23_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 23 +with rel_bixu23_wayC_upd select + congr_cl23_wC_d(1) <= (congr_cl23_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayC_upd select + congr_cl23_wC_d(2) <= (congr_cl23_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayC_upd select + congr_cl23_wC_d(3) <= (congr_cl23_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayC_upd select + congr_cl23_wC_d(4) <= (congr_cl23_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayC_upd select + congr_cl23_wC_d(5) <= (congr_cl23_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 24 +with rel_bixu24_wayC_upd select + congr_cl24_wC_d(0) <= (congr_cl24_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 24 +with rel_bixu24_wayC_upd select + congr_cl24_wC_d(1) <= (congr_cl24_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayC_upd select + congr_cl24_wC_d(2) <= (congr_cl24_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayC_upd select + congr_cl24_wC_d(3) <= (congr_cl24_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayC_upd select + congr_cl24_wC_d(4) <= (congr_cl24_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayC_upd select + congr_cl24_wC_d(5) <= (congr_cl24_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 25 +with rel_bixu25_wayC_upd select + congr_cl25_wC_d(0) <= (congr_cl25_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 25 +with rel_bixu25_wayC_upd select + congr_cl25_wC_d(1) <= (congr_cl25_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayC_upd select + congr_cl25_wC_d(2) <= (congr_cl25_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayC_upd select + congr_cl25_wC_d(3) <= (congr_cl25_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayC_upd select + congr_cl25_wC_d(4) <= (congr_cl25_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayC_upd select + congr_cl25_wC_d(5) <= (congr_cl25_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 26 +with rel_bixu26_wayC_upd select + congr_cl26_wC_d(0) <= (congr_cl26_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 26 +with rel_bixu26_wayC_upd select + congr_cl26_wC_d(1) <= (congr_cl26_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayC_upd select + congr_cl26_wC_d(2) <= (congr_cl26_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayC_upd select + congr_cl26_wC_d(3) <= (congr_cl26_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayC_upd select + congr_cl26_wC_d(4) <= (congr_cl26_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayC_upd select + congr_cl26_wC_d(5) <= (congr_cl26_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 27 +with rel_bixu27_wayC_upd select + congr_cl27_wC_d(0) <= (congr_cl27_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 27 +with rel_bixu27_wayC_upd select + congr_cl27_wC_d(1) <= (congr_cl27_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayC_upd select + congr_cl27_wC_d(2) <= (congr_cl27_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayC_upd select + congr_cl27_wC_d(3) <= (congr_cl27_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayC_upd select + congr_cl27_wC_d(4) <= (congr_cl27_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayC_upd select + congr_cl27_wC_d(5) <= (congr_cl27_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 28 +with rel_bixu28_wayC_upd select + congr_cl28_wC_d(0) <= (congr_cl28_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 28 +with rel_bixu28_wayC_upd select + congr_cl28_wC_d(1) <= (congr_cl28_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayC_upd select + congr_cl28_wC_d(2) <= (congr_cl28_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayC_upd select + congr_cl28_wC_d(3) <= (congr_cl28_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayC_upd select + congr_cl28_wC_d(4) <= (congr_cl28_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayC_upd select + congr_cl28_wC_d(5) <= (congr_cl28_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 29 +with rel_bixu29_wayC_upd select + congr_cl29_wC_d(0) <= (congr_cl29_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 29 +with rel_bixu29_wayC_upd select + congr_cl29_wC_d(1) <= (congr_cl29_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayC_upd select + congr_cl29_wC_d(2) <= (congr_cl29_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayC_upd select + congr_cl29_wC_d(3) <= (congr_cl29_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayC_upd select + congr_cl29_wC_d(4) <= (congr_cl29_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayC_upd select + congr_cl29_wC_d(5) <= (congr_cl29_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 30 +with rel_bixu30_wayC_upd select + congr_cl30_wC_d(0) <= (congr_cl30_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 30 +with rel_bixu30_wayC_upd select + congr_cl30_wC_d(1) <= (congr_cl30_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayC_upd select + congr_cl30_wC_d(2) <= (congr_cl30_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayC_upd select + congr_cl30_wC_d(3) <= (congr_cl30_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayC_upd select + congr_cl30_wC_d(4) <= (congr_cl30_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayC_upd select + congr_cl30_wC_d(5) <= (congr_cl30_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 31 +with rel_bixu31_wayC_upd select + congr_cl31_wC_d(0) <= (congr_cl31_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 31 +with rel_bixu31_wayC_upd select + congr_cl31_wC_d(1) <= (congr_cl31_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayC_upd select + congr_cl31_wC_d(2) <= (congr_cl31_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayC_upd select + congr_cl31_wC_d(3) <= (congr_cl31_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayC_upd select + congr_cl31_wC_d(4) <= (congr_cl31_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayC_upd select + congr_cl31_wC_d(5) <= (congr_cl31_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 32 +with rel_bixu32_wayC_upd select + congr_cl32_wC_d(0) <= (congr_cl32_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 32 +with rel_bixu32_wayC_upd select + congr_cl32_wC_d(1) <= (congr_cl32_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 32 +with rel_bixu32_wayC_upd select + congr_cl32_wC_d(2) <= (congr_cl32_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 32 +with rel_bixu32_wayC_upd select + congr_cl32_wC_d(3) <= (congr_cl32_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 32 +with rel_bixu32_wayC_upd select + congr_cl32_wC_d(4) <= (congr_cl32_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 32 +with rel_bixu32_wayC_upd select + congr_cl32_wC_d(5) <= (congr_cl32_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 33 +with rel_bixu33_wayC_upd select + congr_cl33_wC_d(0) <= (congr_cl33_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 33 +with rel_bixu33_wayC_upd select + congr_cl33_wC_d(1) <= (congr_cl33_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 33 +with rel_bixu33_wayC_upd select + congr_cl33_wC_d(2) <= (congr_cl33_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 33 +with rel_bixu33_wayC_upd select + congr_cl33_wC_d(3) <= (congr_cl33_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 33 +with rel_bixu33_wayC_upd select + congr_cl33_wC_d(4) <= (congr_cl33_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 33 +with rel_bixu33_wayC_upd select + congr_cl33_wC_d(5) <= (congr_cl33_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 34 +with rel_bixu34_wayC_upd select + congr_cl34_wC_d(0) <= (congr_cl34_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 34 +with rel_bixu34_wayC_upd select + congr_cl34_wC_d(1) <= (congr_cl34_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 34 +with rel_bixu34_wayC_upd select + congr_cl34_wC_d(2) <= (congr_cl34_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 34 +with rel_bixu34_wayC_upd select + congr_cl34_wC_d(3) <= (congr_cl34_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 34 +with rel_bixu34_wayC_upd select + congr_cl34_wC_d(4) <= (congr_cl34_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 34 +with rel_bixu34_wayC_upd select + congr_cl34_wC_d(5) <= (congr_cl34_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 35 +with rel_bixu35_wayC_upd select + congr_cl35_wC_d(0) <= (congr_cl35_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 35 +with rel_bixu35_wayC_upd select + congr_cl35_wC_d(1) <= (congr_cl35_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 35 +with rel_bixu35_wayC_upd select + congr_cl35_wC_d(2) <= (congr_cl35_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 35 +with rel_bixu35_wayC_upd select + congr_cl35_wC_d(3) <= (congr_cl35_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 35 +with rel_bixu35_wayC_upd select + congr_cl35_wC_d(4) <= (congr_cl35_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 35 +with rel_bixu35_wayC_upd select + congr_cl35_wC_d(5) <= (congr_cl35_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 36 +with rel_bixu36_wayC_upd select + congr_cl36_wC_d(0) <= (congr_cl36_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 36 +with rel_bixu36_wayC_upd select + congr_cl36_wC_d(1) <= (congr_cl36_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 36 +with rel_bixu36_wayC_upd select + congr_cl36_wC_d(2) <= (congr_cl36_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 36 +with rel_bixu36_wayC_upd select + congr_cl36_wC_d(3) <= (congr_cl36_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 36 +with rel_bixu36_wayC_upd select + congr_cl36_wC_d(4) <= (congr_cl36_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 36 +with rel_bixu36_wayC_upd select + congr_cl36_wC_d(5) <= (congr_cl36_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 37 +with rel_bixu37_wayC_upd select + congr_cl37_wC_d(0) <= (congr_cl37_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 37 +with rel_bixu37_wayC_upd select + congr_cl37_wC_d(1) <= (congr_cl37_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 37 +with rel_bixu37_wayC_upd select + congr_cl37_wC_d(2) <= (congr_cl37_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 37 +with rel_bixu37_wayC_upd select + congr_cl37_wC_d(3) <= (congr_cl37_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 37 +with rel_bixu37_wayC_upd select + congr_cl37_wC_d(4) <= (congr_cl37_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 37 +with rel_bixu37_wayC_upd select + congr_cl37_wC_d(5) <= (congr_cl37_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 38 +with rel_bixu38_wayC_upd select + congr_cl38_wC_d(0) <= (congr_cl38_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 38 +with rel_bixu38_wayC_upd select + congr_cl38_wC_d(1) <= (congr_cl38_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 38 +with rel_bixu38_wayC_upd select + congr_cl38_wC_d(2) <= (congr_cl38_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 38 +with rel_bixu38_wayC_upd select + congr_cl38_wC_d(3) <= (congr_cl38_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 38 +with rel_bixu38_wayC_upd select + congr_cl38_wC_d(4) <= (congr_cl38_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 38 +with rel_bixu38_wayC_upd select + congr_cl38_wC_d(5) <= (congr_cl38_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 39 +with rel_bixu39_wayC_upd select + congr_cl39_wC_d(0) <= (congr_cl39_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 39 +with rel_bixu39_wayC_upd select + congr_cl39_wC_d(1) <= (congr_cl39_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 39 +with rel_bixu39_wayC_upd select + congr_cl39_wC_d(2) <= (congr_cl39_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 39 +with rel_bixu39_wayC_upd select + congr_cl39_wC_d(3) <= (congr_cl39_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 39 +with rel_bixu39_wayC_upd select + congr_cl39_wC_d(4) <= (congr_cl39_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 39 +with rel_bixu39_wayC_upd select + congr_cl39_wC_d(5) <= (congr_cl39_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 40 +with rel_bixu40_wayC_upd select + congr_cl40_wC_d(0) <= (congr_cl40_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 40 +with rel_bixu40_wayC_upd select + congr_cl40_wC_d(1) <= (congr_cl40_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 40 +with rel_bixu40_wayC_upd select + congr_cl40_wC_d(2) <= (congr_cl40_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 40 +with rel_bixu40_wayC_upd select + congr_cl40_wC_d(3) <= (congr_cl40_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 40 +with rel_bixu40_wayC_upd select + congr_cl40_wC_d(4) <= (congr_cl40_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 40 +with rel_bixu40_wayC_upd select + congr_cl40_wC_d(5) <= (congr_cl40_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 41 +with rel_bixu41_wayC_upd select + congr_cl41_wC_d(0) <= (congr_cl41_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 41 +with rel_bixu41_wayC_upd select + congr_cl41_wC_d(1) <= (congr_cl41_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 41 +with rel_bixu41_wayC_upd select + congr_cl41_wC_d(2) <= (congr_cl41_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 41 +with rel_bixu41_wayC_upd select + congr_cl41_wC_d(3) <= (congr_cl41_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 41 +with rel_bixu41_wayC_upd select + congr_cl41_wC_d(4) <= (congr_cl41_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 41 +with rel_bixu41_wayC_upd select + congr_cl41_wC_d(5) <= (congr_cl41_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 42 +with rel_bixu42_wayC_upd select + congr_cl42_wC_d(0) <= (congr_cl42_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 42 +with rel_bixu42_wayC_upd select + congr_cl42_wC_d(1) <= (congr_cl42_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 42 +with rel_bixu42_wayC_upd select + congr_cl42_wC_d(2) <= (congr_cl42_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 42 +with rel_bixu42_wayC_upd select + congr_cl42_wC_d(3) <= (congr_cl42_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 42 +with rel_bixu42_wayC_upd select + congr_cl42_wC_d(4) <= (congr_cl42_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 42 +with rel_bixu42_wayC_upd select + congr_cl42_wC_d(5) <= (congr_cl42_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 43 +with rel_bixu43_wayC_upd select + congr_cl43_wC_d(0) <= (congr_cl43_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 43 +with rel_bixu43_wayC_upd select + congr_cl43_wC_d(1) <= (congr_cl43_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 43 +with rel_bixu43_wayC_upd select + congr_cl43_wC_d(2) <= (congr_cl43_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 43 +with rel_bixu43_wayC_upd select + congr_cl43_wC_d(3) <= (congr_cl43_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 43 +with rel_bixu43_wayC_upd select + congr_cl43_wC_d(4) <= (congr_cl43_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 43 +with rel_bixu43_wayC_upd select + congr_cl43_wC_d(5) <= (congr_cl43_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 44 +with rel_bixu44_wayC_upd select + congr_cl44_wC_d(0) <= (congr_cl44_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 44 +with rel_bixu44_wayC_upd select + congr_cl44_wC_d(1) <= (congr_cl44_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 44 +with rel_bixu44_wayC_upd select + congr_cl44_wC_d(2) <= (congr_cl44_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 44 +with rel_bixu44_wayC_upd select + congr_cl44_wC_d(3) <= (congr_cl44_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 44 +with rel_bixu44_wayC_upd select + congr_cl44_wC_d(4) <= (congr_cl44_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 44 +with rel_bixu44_wayC_upd select + congr_cl44_wC_d(5) <= (congr_cl44_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 45 +with rel_bixu45_wayC_upd select + congr_cl45_wC_d(0) <= (congr_cl45_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 45 +with rel_bixu45_wayC_upd select + congr_cl45_wC_d(1) <= (congr_cl45_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 45 +with rel_bixu45_wayC_upd select + congr_cl45_wC_d(2) <= (congr_cl45_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 45 +with rel_bixu45_wayC_upd select + congr_cl45_wC_d(3) <= (congr_cl45_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 45 +with rel_bixu45_wayC_upd select + congr_cl45_wC_d(4) <= (congr_cl45_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 45 +with rel_bixu45_wayC_upd select + congr_cl45_wC_d(5) <= (congr_cl45_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 46 +with rel_bixu46_wayC_upd select + congr_cl46_wC_d(0) <= (congr_cl46_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 46 +with rel_bixu46_wayC_upd select + congr_cl46_wC_d(1) <= (congr_cl46_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 46 +with rel_bixu46_wayC_upd select + congr_cl46_wC_d(2) <= (congr_cl46_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 46 +with rel_bixu46_wayC_upd select + congr_cl46_wC_d(3) <= (congr_cl46_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 46 +with rel_bixu46_wayC_upd select + congr_cl46_wC_d(4) <= (congr_cl46_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 46 +with rel_bixu46_wayC_upd select + congr_cl46_wC_d(5) <= (congr_cl46_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 47 +with rel_bixu47_wayC_upd select + congr_cl47_wC_d(0) <= (congr_cl47_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 47 +with rel_bixu47_wayC_upd select + congr_cl47_wC_d(1) <= (congr_cl47_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 47 +with rel_bixu47_wayC_upd select + congr_cl47_wC_d(2) <= (congr_cl47_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 47 +with rel_bixu47_wayC_upd select + congr_cl47_wC_d(3) <= (congr_cl47_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 47 +with rel_bixu47_wayC_upd select + congr_cl47_wC_d(4) <= (congr_cl47_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 47 +with rel_bixu47_wayC_upd select + congr_cl47_wC_d(5) <= (congr_cl47_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 48 +with rel_bixu48_wayC_upd select + congr_cl48_wC_d(0) <= (congr_cl48_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 48 +with rel_bixu48_wayC_upd select + congr_cl48_wC_d(1) <= (congr_cl48_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 48 +with rel_bixu48_wayC_upd select + congr_cl48_wC_d(2) <= (congr_cl48_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 48 +with rel_bixu48_wayC_upd select + congr_cl48_wC_d(3) <= (congr_cl48_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 48 +with rel_bixu48_wayC_upd select + congr_cl48_wC_d(4) <= (congr_cl48_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 48 +with rel_bixu48_wayC_upd select + congr_cl48_wC_d(5) <= (congr_cl48_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 49 +with rel_bixu49_wayC_upd select + congr_cl49_wC_d(0) <= (congr_cl49_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 49 +with rel_bixu49_wayC_upd select + congr_cl49_wC_d(1) <= (congr_cl49_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 49 +with rel_bixu49_wayC_upd select + congr_cl49_wC_d(2) <= (congr_cl49_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 49 +with rel_bixu49_wayC_upd select + congr_cl49_wC_d(3) <= (congr_cl49_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 49 +with rel_bixu49_wayC_upd select + congr_cl49_wC_d(4) <= (congr_cl49_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 49 +with rel_bixu49_wayC_upd select + congr_cl49_wC_d(5) <= (congr_cl49_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 50 +with rel_bixu50_wayC_upd select + congr_cl50_wC_d(0) <= (congr_cl50_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 50 +with rel_bixu50_wayC_upd select + congr_cl50_wC_d(1) <= (congr_cl50_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 50 +with rel_bixu50_wayC_upd select + congr_cl50_wC_d(2) <= (congr_cl50_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 50 +with rel_bixu50_wayC_upd select + congr_cl50_wC_d(3) <= (congr_cl50_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 50 +with rel_bixu50_wayC_upd select + congr_cl50_wC_d(4) <= (congr_cl50_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 50 +with rel_bixu50_wayC_upd select + congr_cl50_wC_d(5) <= (congr_cl50_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 51 +with rel_bixu51_wayC_upd select + congr_cl51_wC_d(0) <= (congr_cl51_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 51 +with rel_bixu51_wayC_upd select + congr_cl51_wC_d(1) <= (congr_cl51_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 51 +with rel_bixu51_wayC_upd select + congr_cl51_wC_d(2) <= (congr_cl51_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 51 +with rel_bixu51_wayC_upd select + congr_cl51_wC_d(3) <= (congr_cl51_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 51 +with rel_bixu51_wayC_upd select + congr_cl51_wC_d(4) <= (congr_cl51_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 51 +with rel_bixu51_wayC_upd select + congr_cl51_wC_d(5) <= (congr_cl51_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 52 +with rel_bixu52_wayC_upd select + congr_cl52_wC_d(0) <= (congr_cl52_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 52 +with rel_bixu52_wayC_upd select + congr_cl52_wC_d(1) <= (congr_cl52_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 52 +with rel_bixu52_wayC_upd select + congr_cl52_wC_d(2) <= (congr_cl52_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 52 +with rel_bixu52_wayC_upd select + congr_cl52_wC_d(3) <= (congr_cl52_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 52 +with rel_bixu52_wayC_upd select + congr_cl52_wC_d(4) <= (congr_cl52_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 52 +with rel_bixu52_wayC_upd select + congr_cl52_wC_d(5) <= (congr_cl52_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 53 +with rel_bixu53_wayC_upd select + congr_cl53_wC_d(0) <= (congr_cl53_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 53 +with rel_bixu53_wayC_upd select + congr_cl53_wC_d(1) <= (congr_cl53_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 53 +with rel_bixu53_wayC_upd select + congr_cl53_wC_d(2) <= (congr_cl53_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 53 +with rel_bixu53_wayC_upd select + congr_cl53_wC_d(3) <= (congr_cl53_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 53 +with rel_bixu53_wayC_upd select + congr_cl53_wC_d(4) <= (congr_cl53_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 53 +with rel_bixu53_wayC_upd select + congr_cl53_wC_d(5) <= (congr_cl53_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 54 +with rel_bixu54_wayC_upd select + congr_cl54_wC_d(0) <= (congr_cl54_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 54 +with rel_bixu54_wayC_upd select + congr_cl54_wC_d(1) <= (congr_cl54_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 54 +with rel_bixu54_wayC_upd select + congr_cl54_wC_d(2) <= (congr_cl54_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 54 +with rel_bixu54_wayC_upd select + congr_cl54_wC_d(3) <= (congr_cl54_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 54 +with rel_bixu54_wayC_upd select + congr_cl54_wC_d(4) <= (congr_cl54_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 54 +with rel_bixu54_wayC_upd select + congr_cl54_wC_d(5) <= (congr_cl54_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 55 +with rel_bixu55_wayC_upd select + congr_cl55_wC_d(0) <= (congr_cl55_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 55 +with rel_bixu55_wayC_upd select + congr_cl55_wC_d(1) <= (congr_cl55_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 55 +with rel_bixu55_wayC_upd select + congr_cl55_wC_d(2) <= (congr_cl55_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 55 +with rel_bixu55_wayC_upd select + congr_cl55_wC_d(3) <= (congr_cl55_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 55 +with rel_bixu55_wayC_upd select + congr_cl55_wC_d(4) <= (congr_cl55_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 55 +with rel_bixu55_wayC_upd select + congr_cl55_wC_d(5) <= (congr_cl55_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 56 +with rel_bixu56_wayC_upd select + congr_cl56_wC_d(0) <= (congr_cl56_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 56 +with rel_bixu56_wayC_upd select + congr_cl56_wC_d(1) <= (congr_cl56_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 56 +with rel_bixu56_wayC_upd select + congr_cl56_wC_d(2) <= (congr_cl56_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 56 +with rel_bixu56_wayC_upd select + congr_cl56_wC_d(3) <= (congr_cl56_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 56 +with rel_bixu56_wayC_upd select + congr_cl56_wC_d(4) <= (congr_cl56_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 56 +with rel_bixu56_wayC_upd select + congr_cl56_wC_d(5) <= (congr_cl56_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 57 +with rel_bixu57_wayC_upd select + congr_cl57_wC_d(0) <= (congr_cl57_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 57 +with rel_bixu57_wayC_upd select + congr_cl57_wC_d(1) <= (congr_cl57_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 57 +with rel_bixu57_wayC_upd select + congr_cl57_wC_d(2) <= (congr_cl57_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 57 +with rel_bixu57_wayC_upd select + congr_cl57_wC_d(3) <= (congr_cl57_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 57 +with rel_bixu57_wayC_upd select + congr_cl57_wC_d(4) <= (congr_cl57_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 57 +with rel_bixu57_wayC_upd select + congr_cl57_wC_d(5) <= (congr_cl57_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 58 +with rel_bixu58_wayC_upd select + congr_cl58_wC_d(0) <= (congr_cl58_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 58 +with rel_bixu58_wayC_upd select + congr_cl58_wC_d(1) <= (congr_cl58_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 58 +with rel_bixu58_wayC_upd select + congr_cl58_wC_d(2) <= (congr_cl58_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 58 +with rel_bixu58_wayC_upd select + congr_cl58_wC_d(3) <= (congr_cl58_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 58 +with rel_bixu58_wayC_upd select + congr_cl58_wC_d(4) <= (congr_cl58_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 58 +with rel_bixu58_wayC_upd select + congr_cl58_wC_d(5) <= (congr_cl58_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 59 +with rel_bixu59_wayC_upd select + congr_cl59_wC_d(0) <= (congr_cl59_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 59 +with rel_bixu59_wayC_upd select + congr_cl59_wC_d(1) <= (congr_cl59_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 59 +with rel_bixu59_wayC_upd select + congr_cl59_wC_d(2) <= (congr_cl59_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 59 +with rel_bixu59_wayC_upd select + congr_cl59_wC_d(3) <= (congr_cl59_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 59 +with rel_bixu59_wayC_upd select + congr_cl59_wC_d(4) <= (congr_cl59_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 59 +with rel_bixu59_wayC_upd select + congr_cl59_wC_d(5) <= (congr_cl59_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 60 +with rel_bixu60_wayC_upd select + congr_cl60_wC_d(0) <= (congr_cl60_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 60 +with rel_bixu60_wayC_upd select + congr_cl60_wC_d(1) <= (congr_cl60_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 60 +with rel_bixu60_wayC_upd select + congr_cl60_wC_d(2) <= (congr_cl60_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 60 +with rel_bixu60_wayC_upd select + congr_cl60_wC_d(3) <= (congr_cl60_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 60 +with rel_bixu60_wayC_upd select + congr_cl60_wC_d(4) <= (congr_cl60_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 60 +with rel_bixu60_wayC_upd select + congr_cl60_wC_d(5) <= (congr_cl60_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 61 +with rel_bixu61_wayC_upd select + congr_cl61_wC_d(0) <= (congr_cl61_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 61 +with rel_bixu61_wayC_upd select + congr_cl61_wC_d(1) <= (congr_cl61_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 61 +with rel_bixu61_wayC_upd select + congr_cl61_wC_d(2) <= (congr_cl61_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 61 +with rel_bixu61_wayC_upd select + congr_cl61_wC_d(3) <= (congr_cl61_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 61 +with rel_bixu61_wayC_upd select + congr_cl61_wC_d(4) <= (congr_cl61_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 61 +with rel_bixu61_wayC_upd select + congr_cl61_wC_d(5) <= (congr_cl61_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 62 +with rel_bixu62_wayC_upd select + congr_cl62_wC_d(0) <= (congr_cl62_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 62 +with rel_bixu62_wayC_upd select + congr_cl62_wC_d(1) <= (congr_cl62_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 62 +with rel_bixu62_wayC_upd select + congr_cl62_wC_d(2) <= (congr_cl62_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 62 +with rel_bixu62_wayC_upd select + congr_cl62_wC_d(3) <= (congr_cl62_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 62 +with rel_bixu62_wayC_upd select + congr_cl62_wC_d(4) <= (congr_cl62_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 62 +with rel_bixu62_wayC_upd select + congr_cl62_wC_d(5) <= (congr_cl62_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayC Valid Bit Update for Congruence Class 63 +with rel_bixu63_wayC_upd select + congr_cl63_wC_d(0) <= (congr_cl63_wC_q(0) and not dci_inval_all_q) when "00", + (flush_wayC_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayC_data2_q(0) and not dci_inval_all_q) when others; +-- WayC Lock Bit Update for Congruence Class 63 +with rel_bixu63_wayC_upd select + congr_cl63_wC_d(1) <= (congr_cl63_wC_q(1) and not lock_finval) when "00", + (flush_wayC_data2_q(1) and not lock_finval) when "01", + (reload_wayC_data2_q(1) and not lock_finval) when others; +-- WayC Thread 0 Watch Bit Update for Congruence Class 63 +with rel_bixu63_wayC_upd select + congr_cl63_wC_d(2) <= (congr_cl63_wC_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayC_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayC Thread 1 Watch Bit Update for Congruence Class 63 +with rel_bixu63_wayC_upd select + congr_cl63_wC_d(3) <= (congr_cl63_wC_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayC_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayC Thread 2 Watch Bit Update for Congruence Class 63 +with rel_bixu63_wayC_upd select + congr_cl63_wC_d(4) <= (congr_cl63_wC_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayC_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayC Thread 3 Watch Bit Update for Congruence Class 63 +with rel_bixu63_wayC_upd select + congr_cl63_wC_d(5) <= (congr_cl63_wC_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayC_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Write Select for WayD +-- WayD Valid Bit Update for Congruence Class 0 +with rel_bixu0_wayD_upd select + congr_cl0_wD_d(0) <= (congr_cl0_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 0 +with rel_bixu0_wayD_upd select + congr_cl0_wD_d(1) <= (congr_cl0_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayD_upd select + congr_cl0_wD_d(2) <= (congr_cl0_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayD_upd select + congr_cl0_wD_d(3) <= (congr_cl0_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayD_upd select + congr_cl0_wD_d(4) <= (congr_cl0_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayD_upd select + congr_cl0_wD_d(5) <= (congr_cl0_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 1 +with rel_bixu1_wayD_upd select + congr_cl1_wD_d(0) <= (congr_cl1_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 1 +with rel_bixu1_wayD_upd select + congr_cl1_wD_d(1) <= (congr_cl1_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayD_upd select + congr_cl1_wD_d(2) <= (congr_cl1_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayD_upd select + congr_cl1_wD_d(3) <= (congr_cl1_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayD_upd select + congr_cl1_wD_d(4) <= (congr_cl1_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayD_upd select + congr_cl1_wD_d(5) <= (congr_cl1_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 2 +with rel_bixu2_wayD_upd select + congr_cl2_wD_d(0) <= (congr_cl2_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 2 +with rel_bixu2_wayD_upd select + congr_cl2_wD_d(1) <= (congr_cl2_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayD_upd select + congr_cl2_wD_d(2) <= (congr_cl2_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayD_upd select + congr_cl2_wD_d(3) <= (congr_cl2_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayD_upd select + congr_cl2_wD_d(4) <= (congr_cl2_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayD_upd select + congr_cl2_wD_d(5) <= (congr_cl2_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 3 +with rel_bixu3_wayD_upd select + congr_cl3_wD_d(0) <= (congr_cl3_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 3 +with rel_bixu3_wayD_upd select + congr_cl3_wD_d(1) <= (congr_cl3_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayD_upd select + congr_cl3_wD_d(2) <= (congr_cl3_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayD_upd select + congr_cl3_wD_d(3) <= (congr_cl3_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayD_upd select + congr_cl3_wD_d(4) <= (congr_cl3_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayD_upd select + congr_cl3_wD_d(5) <= (congr_cl3_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 4 +with rel_bixu4_wayD_upd select + congr_cl4_wD_d(0) <= (congr_cl4_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 4 +with rel_bixu4_wayD_upd select + congr_cl4_wD_d(1) <= (congr_cl4_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayD_upd select + congr_cl4_wD_d(2) <= (congr_cl4_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayD_upd select + congr_cl4_wD_d(3) <= (congr_cl4_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayD_upd select + congr_cl4_wD_d(4) <= (congr_cl4_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayD_upd select + congr_cl4_wD_d(5) <= (congr_cl4_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 5 +with rel_bixu5_wayD_upd select + congr_cl5_wD_d(0) <= (congr_cl5_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 5 +with rel_bixu5_wayD_upd select + congr_cl5_wD_d(1) <= (congr_cl5_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayD_upd select + congr_cl5_wD_d(2) <= (congr_cl5_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayD_upd select + congr_cl5_wD_d(3) <= (congr_cl5_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayD_upd select + congr_cl5_wD_d(4) <= (congr_cl5_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayD_upd select + congr_cl5_wD_d(5) <= (congr_cl5_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 6 +with rel_bixu6_wayD_upd select + congr_cl6_wD_d(0) <= (congr_cl6_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 6 +with rel_bixu6_wayD_upd select + congr_cl6_wD_d(1) <= (congr_cl6_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayD_upd select + congr_cl6_wD_d(2) <= (congr_cl6_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayD_upd select + congr_cl6_wD_d(3) <= (congr_cl6_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayD_upd select + congr_cl6_wD_d(4) <= (congr_cl6_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayD_upd select + congr_cl6_wD_d(5) <= (congr_cl6_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 7 +with rel_bixu7_wayD_upd select + congr_cl7_wD_d(0) <= (congr_cl7_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 7 +with rel_bixu7_wayD_upd select + congr_cl7_wD_d(1) <= (congr_cl7_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayD_upd select + congr_cl7_wD_d(2) <= (congr_cl7_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayD_upd select + congr_cl7_wD_d(3) <= (congr_cl7_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayD_upd select + congr_cl7_wD_d(4) <= (congr_cl7_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayD_upd select + congr_cl7_wD_d(5) <= (congr_cl7_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 8 +with rel_bixu8_wayD_upd select + congr_cl8_wD_d(0) <= (congr_cl8_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 8 +with rel_bixu8_wayD_upd select + congr_cl8_wD_d(1) <= (congr_cl8_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayD_upd select + congr_cl8_wD_d(2) <= (congr_cl8_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayD_upd select + congr_cl8_wD_d(3) <= (congr_cl8_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayD_upd select + congr_cl8_wD_d(4) <= (congr_cl8_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayD_upd select + congr_cl8_wD_d(5) <= (congr_cl8_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 9 +with rel_bixu9_wayD_upd select + congr_cl9_wD_d(0) <= (congr_cl9_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 9 +with rel_bixu9_wayD_upd select + congr_cl9_wD_d(1) <= (congr_cl9_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayD_upd select + congr_cl9_wD_d(2) <= (congr_cl9_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayD_upd select + congr_cl9_wD_d(3) <= (congr_cl9_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayD_upd select + congr_cl9_wD_d(4) <= (congr_cl9_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayD_upd select + congr_cl9_wD_d(5) <= (congr_cl9_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 10 +with rel_bixu10_wayD_upd select + congr_cl10_wD_d(0) <= (congr_cl10_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 10 +with rel_bixu10_wayD_upd select + congr_cl10_wD_d(1) <= (congr_cl10_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayD_upd select + congr_cl10_wD_d(2) <= (congr_cl10_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayD_upd select + congr_cl10_wD_d(3) <= (congr_cl10_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayD_upd select + congr_cl10_wD_d(4) <= (congr_cl10_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayD_upd select + congr_cl10_wD_d(5) <= (congr_cl10_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 11 +with rel_bixu11_wayD_upd select + congr_cl11_wD_d(0) <= (congr_cl11_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 11 +with rel_bixu11_wayD_upd select + congr_cl11_wD_d(1) <= (congr_cl11_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayD_upd select + congr_cl11_wD_d(2) <= (congr_cl11_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayD_upd select + congr_cl11_wD_d(3) <= (congr_cl11_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayD_upd select + congr_cl11_wD_d(4) <= (congr_cl11_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayD_upd select + congr_cl11_wD_d(5) <= (congr_cl11_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 12 +with rel_bixu12_wayD_upd select + congr_cl12_wD_d(0) <= (congr_cl12_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 12 +with rel_bixu12_wayD_upd select + congr_cl12_wD_d(1) <= (congr_cl12_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayD_upd select + congr_cl12_wD_d(2) <= (congr_cl12_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayD_upd select + congr_cl12_wD_d(3) <= (congr_cl12_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayD_upd select + congr_cl12_wD_d(4) <= (congr_cl12_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayD_upd select + congr_cl12_wD_d(5) <= (congr_cl12_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 13 +with rel_bixu13_wayD_upd select + congr_cl13_wD_d(0) <= (congr_cl13_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 13 +with rel_bixu13_wayD_upd select + congr_cl13_wD_d(1) <= (congr_cl13_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayD_upd select + congr_cl13_wD_d(2) <= (congr_cl13_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayD_upd select + congr_cl13_wD_d(3) <= (congr_cl13_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayD_upd select + congr_cl13_wD_d(4) <= (congr_cl13_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayD_upd select + congr_cl13_wD_d(5) <= (congr_cl13_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 14 +with rel_bixu14_wayD_upd select + congr_cl14_wD_d(0) <= (congr_cl14_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 14 +with rel_bixu14_wayD_upd select + congr_cl14_wD_d(1) <= (congr_cl14_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayD_upd select + congr_cl14_wD_d(2) <= (congr_cl14_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayD_upd select + congr_cl14_wD_d(3) <= (congr_cl14_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayD_upd select + congr_cl14_wD_d(4) <= (congr_cl14_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayD_upd select + congr_cl14_wD_d(5) <= (congr_cl14_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 15 +with rel_bixu15_wayD_upd select + congr_cl15_wD_d(0) <= (congr_cl15_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 15 +with rel_bixu15_wayD_upd select + congr_cl15_wD_d(1) <= (congr_cl15_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayD_upd select + congr_cl15_wD_d(2) <= (congr_cl15_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayD_upd select + congr_cl15_wD_d(3) <= (congr_cl15_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayD_upd select + congr_cl15_wD_d(4) <= (congr_cl15_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayD_upd select + congr_cl15_wD_d(5) <= (congr_cl15_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 16 +with rel_bixu16_wayD_upd select + congr_cl16_wD_d(0) <= (congr_cl16_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 16 +with rel_bixu16_wayD_upd select + congr_cl16_wD_d(1) <= (congr_cl16_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayD_upd select + congr_cl16_wD_d(2) <= (congr_cl16_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayD_upd select + congr_cl16_wD_d(3) <= (congr_cl16_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayD_upd select + congr_cl16_wD_d(4) <= (congr_cl16_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayD_upd select + congr_cl16_wD_d(5) <= (congr_cl16_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 17 +with rel_bixu17_wayD_upd select + congr_cl17_wD_d(0) <= (congr_cl17_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 17 +with rel_bixu17_wayD_upd select + congr_cl17_wD_d(1) <= (congr_cl17_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayD_upd select + congr_cl17_wD_d(2) <= (congr_cl17_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayD_upd select + congr_cl17_wD_d(3) <= (congr_cl17_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayD_upd select + congr_cl17_wD_d(4) <= (congr_cl17_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayD_upd select + congr_cl17_wD_d(5) <= (congr_cl17_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 18 +with rel_bixu18_wayD_upd select + congr_cl18_wD_d(0) <= (congr_cl18_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 18 +with rel_bixu18_wayD_upd select + congr_cl18_wD_d(1) <= (congr_cl18_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayD_upd select + congr_cl18_wD_d(2) <= (congr_cl18_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayD_upd select + congr_cl18_wD_d(3) <= (congr_cl18_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayD_upd select + congr_cl18_wD_d(4) <= (congr_cl18_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayD_upd select + congr_cl18_wD_d(5) <= (congr_cl18_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 19 +with rel_bixu19_wayD_upd select + congr_cl19_wD_d(0) <= (congr_cl19_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 19 +with rel_bixu19_wayD_upd select + congr_cl19_wD_d(1) <= (congr_cl19_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayD_upd select + congr_cl19_wD_d(2) <= (congr_cl19_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayD_upd select + congr_cl19_wD_d(3) <= (congr_cl19_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayD_upd select + congr_cl19_wD_d(4) <= (congr_cl19_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayD_upd select + congr_cl19_wD_d(5) <= (congr_cl19_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 20 +with rel_bixu20_wayD_upd select + congr_cl20_wD_d(0) <= (congr_cl20_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 20 +with rel_bixu20_wayD_upd select + congr_cl20_wD_d(1) <= (congr_cl20_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayD_upd select + congr_cl20_wD_d(2) <= (congr_cl20_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayD_upd select + congr_cl20_wD_d(3) <= (congr_cl20_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayD_upd select + congr_cl20_wD_d(4) <= (congr_cl20_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayD_upd select + congr_cl20_wD_d(5) <= (congr_cl20_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 21 +with rel_bixu21_wayD_upd select + congr_cl21_wD_d(0) <= (congr_cl21_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 21 +with rel_bixu21_wayD_upd select + congr_cl21_wD_d(1) <= (congr_cl21_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayD_upd select + congr_cl21_wD_d(2) <= (congr_cl21_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayD_upd select + congr_cl21_wD_d(3) <= (congr_cl21_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayD_upd select + congr_cl21_wD_d(4) <= (congr_cl21_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayD_upd select + congr_cl21_wD_d(5) <= (congr_cl21_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 22 +with rel_bixu22_wayD_upd select + congr_cl22_wD_d(0) <= (congr_cl22_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 22 +with rel_bixu22_wayD_upd select + congr_cl22_wD_d(1) <= (congr_cl22_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayD_upd select + congr_cl22_wD_d(2) <= (congr_cl22_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayD_upd select + congr_cl22_wD_d(3) <= (congr_cl22_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayD_upd select + congr_cl22_wD_d(4) <= (congr_cl22_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayD_upd select + congr_cl22_wD_d(5) <= (congr_cl22_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 23 +with rel_bixu23_wayD_upd select + congr_cl23_wD_d(0) <= (congr_cl23_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 23 +with rel_bixu23_wayD_upd select + congr_cl23_wD_d(1) <= (congr_cl23_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayD_upd select + congr_cl23_wD_d(2) <= (congr_cl23_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayD_upd select + congr_cl23_wD_d(3) <= (congr_cl23_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayD_upd select + congr_cl23_wD_d(4) <= (congr_cl23_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayD_upd select + congr_cl23_wD_d(5) <= (congr_cl23_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 24 +with rel_bixu24_wayD_upd select + congr_cl24_wD_d(0) <= (congr_cl24_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 24 +with rel_bixu24_wayD_upd select + congr_cl24_wD_d(1) <= (congr_cl24_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayD_upd select + congr_cl24_wD_d(2) <= (congr_cl24_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayD_upd select + congr_cl24_wD_d(3) <= (congr_cl24_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayD_upd select + congr_cl24_wD_d(4) <= (congr_cl24_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayD_upd select + congr_cl24_wD_d(5) <= (congr_cl24_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 25 +with rel_bixu25_wayD_upd select + congr_cl25_wD_d(0) <= (congr_cl25_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 25 +with rel_bixu25_wayD_upd select + congr_cl25_wD_d(1) <= (congr_cl25_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayD_upd select + congr_cl25_wD_d(2) <= (congr_cl25_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayD_upd select + congr_cl25_wD_d(3) <= (congr_cl25_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayD_upd select + congr_cl25_wD_d(4) <= (congr_cl25_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayD_upd select + congr_cl25_wD_d(5) <= (congr_cl25_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 26 +with rel_bixu26_wayD_upd select + congr_cl26_wD_d(0) <= (congr_cl26_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 26 +with rel_bixu26_wayD_upd select + congr_cl26_wD_d(1) <= (congr_cl26_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayD_upd select + congr_cl26_wD_d(2) <= (congr_cl26_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayD_upd select + congr_cl26_wD_d(3) <= (congr_cl26_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayD_upd select + congr_cl26_wD_d(4) <= (congr_cl26_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayD_upd select + congr_cl26_wD_d(5) <= (congr_cl26_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 27 +with rel_bixu27_wayD_upd select + congr_cl27_wD_d(0) <= (congr_cl27_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 27 +with rel_bixu27_wayD_upd select + congr_cl27_wD_d(1) <= (congr_cl27_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayD_upd select + congr_cl27_wD_d(2) <= (congr_cl27_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayD_upd select + congr_cl27_wD_d(3) <= (congr_cl27_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayD_upd select + congr_cl27_wD_d(4) <= (congr_cl27_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayD_upd select + congr_cl27_wD_d(5) <= (congr_cl27_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 28 +with rel_bixu28_wayD_upd select + congr_cl28_wD_d(0) <= (congr_cl28_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 28 +with rel_bixu28_wayD_upd select + congr_cl28_wD_d(1) <= (congr_cl28_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayD_upd select + congr_cl28_wD_d(2) <= (congr_cl28_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayD_upd select + congr_cl28_wD_d(3) <= (congr_cl28_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayD_upd select + congr_cl28_wD_d(4) <= (congr_cl28_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayD_upd select + congr_cl28_wD_d(5) <= (congr_cl28_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 29 +with rel_bixu29_wayD_upd select + congr_cl29_wD_d(0) <= (congr_cl29_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 29 +with rel_bixu29_wayD_upd select + congr_cl29_wD_d(1) <= (congr_cl29_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayD_upd select + congr_cl29_wD_d(2) <= (congr_cl29_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayD_upd select + congr_cl29_wD_d(3) <= (congr_cl29_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayD_upd select + congr_cl29_wD_d(4) <= (congr_cl29_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayD_upd select + congr_cl29_wD_d(5) <= (congr_cl29_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 30 +with rel_bixu30_wayD_upd select + congr_cl30_wD_d(0) <= (congr_cl30_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 30 +with rel_bixu30_wayD_upd select + congr_cl30_wD_d(1) <= (congr_cl30_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayD_upd select + congr_cl30_wD_d(2) <= (congr_cl30_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayD_upd select + congr_cl30_wD_d(3) <= (congr_cl30_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayD_upd select + congr_cl30_wD_d(4) <= (congr_cl30_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayD_upd select + congr_cl30_wD_d(5) <= (congr_cl30_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 31 +with rel_bixu31_wayD_upd select + congr_cl31_wD_d(0) <= (congr_cl31_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 31 +with rel_bixu31_wayD_upd select + congr_cl31_wD_d(1) <= (congr_cl31_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayD_upd select + congr_cl31_wD_d(2) <= (congr_cl31_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayD_upd select + congr_cl31_wD_d(3) <= (congr_cl31_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayD_upd select + congr_cl31_wD_d(4) <= (congr_cl31_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayD_upd select + congr_cl31_wD_d(5) <= (congr_cl31_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 32 +with rel_bixu32_wayD_upd select + congr_cl32_wD_d(0) <= (congr_cl32_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 32 +with rel_bixu32_wayD_upd select + congr_cl32_wD_d(1) <= (congr_cl32_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 32 +with rel_bixu32_wayD_upd select + congr_cl32_wD_d(2) <= (congr_cl32_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 32 +with rel_bixu32_wayD_upd select + congr_cl32_wD_d(3) <= (congr_cl32_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 32 +with rel_bixu32_wayD_upd select + congr_cl32_wD_d(4) <= (congr_cl32_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 32 +with rel_bixu32_wayD_upd select + congr_cl32_wD_d(5) <= (congr_cl32_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 33 +with rel_bixu33_wayD_upd select + congr_cl33_wD_d(0) <= (congr_cl33_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 33 +with rel_bixu33_wayD_upd select + congr_cl33_wD_d(1) <= (congr_cl33_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 33 +with rel_bixu33_wayD_upd select + congr_cl33_wD_d(2) <= (congr_cl33_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 33 +with rel_bixu33_wayD_upd select + congr_cl33_wD_d(3) <= (congr_cl33_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 33 +with rel_bixu33_wayD_upd select + congr_cl33_wD_d(4) <= (congr_cl33_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 33 +with rel_bixu33_wayD_upd select + congr_cl33_wD_d(5) <= (congr_cl33_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 34 +with rel_bixu34_wayD_upd select + congr_cl34_wD_d(0) <= (congr_cl34_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 34 +with rel_bixu34_wayD_upd select + congr_cl34_wD_d(1) <= (congr_cl34_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 34 +with rel_bixu34_wayD_upd select + congr_cl34_wD_d(2) <= (congr_cl34_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 34 +with rel_bixu34_wayD_upd select + congr_cl34_wD_d(3) <= (congr_cl34_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 34 +with rel_bixu34_wayD_upd select + congr_cl34_wD_d(4) <= (congr_cl34_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 34 +with rel_bixu34_wayD_upd select + congr_cl34_wD_d(5) <= (congr_cl34_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 35 +with rel_bixu35_wayD_upd select + congr_cl35_wD_d(0) <= (congr_cl35_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 35 +with rel_bixu35_wayD_upd select + congr_cl35_wD_d(1) <= (congr_cl35_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 35 +with rel_bixu35_wayD_upd select + congr_cl35_wD_d(2) <= (congr_cl35_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 35 +with rel_bixu35_wayD_upd select + congr_cl35_wD_d(3) <= (congr_cl35_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 35 +with rel_bixu35_wayD_upd select + congr_cl35_wD_d(4) <= (congr_cl35_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 35 +with rel_bixu35_wayD_upd select + congr_cl35_wD_d(5) <= (congr_cl35_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 36 +with rel_bixu36_wayD_upd select + congr_cl36_wD_d(0) <= (congr_cl36_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 36 +with rel_bixu36_wayD_upd select + congr_cl36_wD_d(1) <= (congr_cl36_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 36 +with rel_bixu36_wayD_upd select + congr_cl36_wD_d(2) <= (congr_cl36_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 36 +with rel_bixu36_wayD_upd select + congr_cl36_wD_d(3) <= (congr_cl36_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 36 +with rel_bixu36_wayD_upd select + congr_cl36_wD_d(4) <= (congr_cl36_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 36 +with rel_bixu36_wayD_upd select + congr_cl36_wD_d(5) <= (congr_cl36_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 37 +with rel_bixu37_wayD_upd select + congr_cl37_wD_d(0) <= (congr_cl37_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 37 +with rel_bixu37_wayD_upd select + congr_cl37_wD_d(1) <= (congr_cl37_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 37 +with rel_bixu37_wayD_upd select + congr_cl37_wD_d(2) <= (congr_cl37_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 37 +with rel_bixu37_wayD_upd select + congr_cl37_wD_d(3) <= (congr_cl37_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 37 +with rel_bixu37_wayD_upd select + congr_cl37_wD_d(4) <= (congr_cl37_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 37 +with rel_bixu37_wayD_upd select + congr_cl37_wD_d(5) <= (congr_cl37_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 38 +with rel_bixu38_wayD_upd select + congr_cl38_wD_d(0) <= (congr_cl38_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 38 +with rel_bixu38_wayD_upd select + congr_cl38_wD_d(1) <= (congr_cl38_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 38 +with rel_bixu38_wayD_upd select + congr_cl38_wD_d(2) <= (congr_cl38_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 38 +with rel_bixu38_wayD_upd select + congr_cl38_wD_d(3) <= (congr_cl38_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 38 +with rel_bixu38_wayD_upd select + congr_cl38_wD_d(4) <= (congr_cl38_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 38 +with rel_bixu38_wayD_upd select + congr_cl38_wD_d(5) <= (congr_cl38_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 39 +with rel_bixu39_wayD_upd select + congr_cl39_wD_d(0) <= (congr_cl39_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 39 +with rel_bixu39_wayD_upd select + congr_cl39_wD_d(1) <= (congr_cl39_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 39 +with rel_bixu39_wayD_upd select + congr_cl39_wD_d(2) <= (congr_cl39_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 39 +with rel_bixu39_wayD_upd select + congr_cl39_wD_d(3) <= (congr_cl39_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 39 +with rel_bixu39_wayD_upd select + congr_cl39_wD_d(4) <= (congr_cl39_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 39 +with rel_bixu39_wayD_upd select + congr_cl39_wD_d(5) <= (congr_cl39_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 40 +with rel_bixu40_wayD_upd select + congr_cl40_wD_d(0) <= (congr_cl40_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 40 +with rel_bixu40_wayD_upd select + congr_cl40_wD_d(1) <= (congr_cl40_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 40 +with rel_bixu40_wayD_upd select + congr_cl40_wD_d(2) <= (congr_cl40_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 40 +with rel_bixu40_wayD_upd select + congr_cl40_wD_d(3) <= (congr_cl40_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 40 +with rel_bixu40_wayD_upd select + congr_cl40_wD_d(4) <= (congr_cl40_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 40 +with rel_bixu40_wayD_upd select + congr_cl40_wD_d(5) <= (congr_cl40_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 41 +with rel_bixu41_wayD_upd select + congr_cl41_wD_d(0) <= (congr_cl41_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 41 +with rel_bixu41_wayD_upd select + congr_cl41_wD_d(1) <= (congr_cl41_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 41 +with rel_bixu41_wayD_upd select + congr_cl41_wD_d(2) <= (congr_cl41_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 41 +with rel_bixu41_wayD_upd select + congr_cl41_wD_d(3) <= (congr_cl41_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 41 +with rel_bixu41_wayD_upd select + congr_cl41_wD_d(4) <= (congr_cl41_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 41 +with rel_bixu41_wayD_upd select + congr_cl41_wD_d(5) <= (congr_cl41_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 42 +with rel_bixu42_wayD_upd select + congr_cl42_wD_d(0) <= (congr_cl42_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 42 +with rel_bixu42_wayD_upd select + congr_cl42_wD_d(1) <= (congr_cl42_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 42 +with rel_bixu42_wayD_upd select + congr_cl42_wD_d(2) <= (congr_cl42_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 42 +with rel_bixu42_wayD_upd select + congr_cl42_wD_d(3) <= (congr_cl42_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 42 +with rel_bixu42_wayD_upd select + congr_cl42_wD_d(4) <= (congr_cl42_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 42 +with rel_bixu42_wayD_upd select + congr_cl42_wD_d(5) <= (congr_cl42_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 43 +with rel_bixu43_wayD_upd select + congr_cl43_wD_d(0) <= (congr_cl43_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 43 +with rel_bixu43_wayD_upd select + congr_cl43_wD_d(1) <= (congr_cl43_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 43 +with rel_bixu43_wayD_upd select + congr_cl43_wD_d(2) <= (congr_cl43_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 43 +with rel_bixu43_wayD_upd select + congr_cl43_wD_d(3) <= (congr_cl43_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 43 +with rel_bixu43_wayD_upd select + congr_cl43_wD_d(4) <= (congr_cl43_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 43 +with rel_bixu43_wayD_upd select + congr_cl43_wD_d(5) <= (congr_cl43_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 44 +with rel_bixu44_wayD_upd select + congr_cl44_wD_d(0) <= (congr_cl44_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 44 +with rel_bixu44_wayD_upd select + congr_cl44_wD_d(1) <= (congr_cl44_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 44 +with rel_bixu44_wayD_upd select + congr_cl44_wD_d(2) <= (congr_cl44_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 44 +with rel_bixu44_wayD_upd select + congr_cl44_wD_d(3) <= (congr_cl44_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 44 +with rel_bixu44_wayD_upd select + congr_cl44_wD_d(4) <= (congr_cl44_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 44 +with rel_bixu44_wayD_upd select + congr_cl44_wD_d(5) <= (congr_cl44_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 45 +with rel_bixu45_wayD_upd select + congr_cl45_wD_d(0) <= (congr_cl45_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 45 +with rel_bixu45_wayD_upd select + congr_cl45_wD_d(1) <= (congr_cl45_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 45 +with rel_bixu45_wayD_upd select + congr_cl45_wD_d(2) <= (congr_cl45_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 45 +with rel_bixu45_wayD_upd select + congr_cl45_wD_d(3) <= (congr_cl45_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 45 +with rel_bixu45_wayD_upd select + congr_cl45_wD_d(4) <= (congr_cl45_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 45 +with rel_bixu45_wayD_upd select + congr_cl45_wD_d(5) <= (congr_cl45_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 46 +with rel_bixu46_wayD_upd select + congr_cl46_wD_d(0) <= (congr_cl46_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 46 +with rel_bixu46_wayD_upd select + congr_cl46_wD_d(1) <= (congr_cl46_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 46 +with rel_bixu46_wayD_upd select + congr_cl46_wD_d(2) <= (congr_cl46_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 46 +with rel_bixu46_wayD_upd select + congr_cl46_wD_d(3) <= (congr_cl46_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 46 +with rel_bixu46_wayD_upd select + congr_cl46_wD_d(4) <= (congr_cl46_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 46 +with rel_bixu46_wayD_upd select + congr_cl46_wD_d(5) <= (congr_cl46_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 47 +with rel_bixu47_wayD_upd select + congr_cl47_wD_d(0) <= (congr_cl47_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 47 +with rel_bixu47_wayD_upd select + congr_cl47_wD_d(1) <= (congr_cl47_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 47 +with rel_bixu47_wayD_upd select + congr_cl47_wD_d(2) <= (congr_cl47_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 47 +with rel_bixu47_wayD_upd select + congr_cl47_wD_d(3) <= (congr_cl47_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 47 +with rel_bixu47_wayD_upd select + congr_cl47_wD_d(4) <= (congr_cl47_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 47 +with rel_bixu47_wayD_upd select + congr_cl47_wD_d(5) <= (congr_cl47_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 48 +with rel_bixu48_wayD_upd select + congr_cl48_wD_d(0) <= (congr_cl48_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 48 +with rel_bixu48_wayD_upd select + congr_cl48_wD_d(1) <= (congr_cl48_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 48 +with rel_bixu48_wayD_upd select + congr_cl48_wD_d(2) <= (congr_cl48_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 48 +with rel_bixu48_wayD_upd select + congr_cl48_wD_d(3) <= (congr_cl48_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 48 +with rel_bixu48_wayD_upd select + congr_cl48_wD_d(4) <= (congr_cl48_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 48 +with rel_bixu48_wayD_upd select + congr_cl48_wD_d(5) <= (congr_cl48_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 49 +with rel_bixu49_wayD_upd select + congr_cl49_wD_d(0) <= (congr_cl49_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 49 +with rel_bixu49_wayD_upd select + congr_cl49_wD_d(1) <= (congr_cl49_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 49 +with rel_bixu49_wayD_upd select + congr_cl49_wD_d(2) <= (congr_cl49_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 49 +with rel_bixu49_wayD_upd select + congr_cl49_wD_d(3) <= (congr_cl49_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 49 +with rel_bixu49_wayD_upd select + congr_cl49_wD_d(4) <= (congr_cl49_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 49 +with rel_bixu49_wayD_upd select + congr_cl49_wD_d(5) <= (congr_cl49_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 50 +with rel_bixu50_wayD_upd select + congr_cl50_wD_d(0) <= (congr_cl50_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 50 +with rel_bixu50_wayD_upd select + congr_cl50_wD_d(1) <= (congr_cl50_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 50 +with rel_bixu50_wayD_upd select + congr_cl50_wD_d(2) <= (congr_cl50_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 50 +with rel_bixu50_wayD_upd select + congr_cl50_wD_d(3) <= (congr_cl50_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 50 +with rel_bixu50_wayD_upd select + congr_cl50_wD_d(4) <= (congr_cl50_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 50 +with rel_bixu50_wayD_upd select + congr_cl50_wD_d(5) <= (congr_cl50_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 51 +with rel_bixu51_wayD_upd select + congr_cl51_wD_d(0) <= (congr_cl51_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 51 +with rel_bixu51_wayD_upd select + congr_cl51_wD_d(1) <= (congr_cl51_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 51 +with rel_bixu51_wayD_upd select + congr_cl51_wD_d(2) <= (congr_cl51_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 51 +with rel_bixu51_wayD_upd select + congr_cl51_wD_d(3) <= (congr_cl51_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 51 +with rel_bixu51_wayD_upd select + congr_cl51_wD_d(4) <= (congr_cl51_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 51 +with rel_bixu51_wayD_upd select + congr_cl51_wD_d(5) <= (congr_cl51_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 52 +with rel_bixu52_wayD_upd select + congr_cl52_wD_d(0) <= (congr_cl52_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 52 +with rel_bixu52_wayD_upd select + congr_cl52_wD_d(1) <= (congr_cl52_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 52 +with rel_bixu52_wayD_upd select + congr_cl52_wD_d(2) <= (congr_cl52_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 52 +with rel_bixu52_wayD_upd select + congr_cl52_wD_d(3) <= (congr_cl52_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 52 +with rel_bixu52_wayD_upd select + congr_cl52_wD_d(4) <= (congr_cl52_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 52 +with rel_bixu52_wayD_upd select + congr_cl52_wD_d(5) <= (congr_cl52_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 53 +with rel_bixu53_wayD_upd select + congr_cl53_wD_d(0) <= (congr_cl53_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 53 +with rel_bixu53_wayD_upd select + congr_cl53_wD_d(1) <= (congr_cl53_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 53 +with rel_bixu53_wayD_upd select + congr_cl53_wD_d(2) <= (congr_cl53_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 53 +with rel_bixu53_wayD_upd select + congr_cl53_wD_d(3) <= (congr_cl53_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 53 +with rel_bixu53_wayD_upd select + congr_cl53_wD_d(4) <= (congr_cl53_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 53 +with rel_bixu53_wayD_upd select + congr_cl53_wD_d(5) <= (congr_cl53_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 54 +with rel_bixu54_wayD_upd select + congr_cl54_wD_d(0) <= (congr_cl54_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 54 +with rel_bixu54_wayD_upd select + congr_cl54_wD_d(1) <= (congr_cl54_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 54 +with rel_bixu54_wayD_upd select + congr_cl54_wD_d(2) <= (congr_cl54_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 54 +with rel_bixu54_wayD_upd select + congr_cl54_wD_d(3) <= (congr_cl54_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 54 +with rel_bixu54_wayD_upd select + congr_cl54_wD_d(4) <= (congr_cl54_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 54 +with rel_bixu54_wayD_upd select + congr_cl54_wD_d(5) <= (congr_cl54_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 55 +with rel_bixu55_wayD_upd select + congr_cl55_wD_d(0) <= (congr_cl55_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 55 +with rel_bixu55_wayD_upd select + congr_cl55_wD_d(1) <= (congr_cl55_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 55 +with rel_bixu55_wayD_upd select + congr_cl55_wD_d(2) <= (congr_cl55_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 55 +with rel_bixu55_wayD_upd select + congr_cl55_wD_d(3) <= (congr_cl55_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 55 +with rel_bixu55_wayD_upd select + congr_cl55_wD_d(4) <= (congr_cl55_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 55 +with rel_bixu55_wayD_upd select + congr_cl55_wD_d(5) <= (congr_cl55_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 56 +with rel_bixu56_wayD_upd select + congr_cl56_wD_d(0) <= (congr_cl56_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 56 +with rel_bixu56_wayD_upd select + congr_cl56_wD_d(1) <= (congr_cl56_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 56 +with rel_bixu56_wayD_upd select + congr_cl56_wD_d(2) <= (congr_cl56_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 56 +with rel_bixu56_wayD_upd select + congr_cl56_wD_d(3) <= (congr_cl56_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 56 +with rel_bixu56_wayD_upd select + congr_cl56_wD_d(4) <= (congr_cl56_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 56 +with rel_bixu56_wayD_upd select + congr_cl56_wD_d(5) <= (congr_cl56_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 57 +with rel_bixu57_wayD_upd select + congr_cl57_wD_d(0) <= (congr_cl57_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 57 +with rel_bixu57_wayD_upd select + congr_cl57_wD_d(1) <= (congr_cl57_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 57 +with rel_bixu57_wayD_upd select + congr_cl57_wD_d(2) <= (congr_cl57_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 57 +with rel_bixu57_wayD_upd select + congr_cl57_wD_d(3) <= (congr_cl57_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 57 +with rel_bixu57_wayD_upd select + congr_cl57_wD_d(4) <= (congr_cl57_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 57 +with rel_bixu57_wayD_upd select + congr_cl57_wD_d(5) <= (congr_cl57_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 58 +with rel_bixu58_wayD_upd select + congr_cl58_wD_d(0) <= (congr_cl58_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 58 +with rel_bixu58_wayD_upd select + congr_cl58_wD_d(1) <= (congr_cl58_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 58 +with rel_bixu58_wayD_upd select + congr_cl58_wD_d(2) <= (congr_cl58_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 58 +with rel_bixu58_wayD_upd select + congr_cl58_wD_d(3) <= (congr_cl58_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 58 +with rel_bixu58_wayD_upd select + congr_cl58_wD_d(4) <= (congr_cl58_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 58 +with rel_bixu58_wayD_upd select + congr_cl58_wD_d(5) <= (congr_cl58_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 59 +with rel_bixu59_wayD_upd select + congr_cl59_wD_d(0) <= (congr_cl59_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 59 +with rel_bixu59_wayD_upd select + congr_cl59_wD_d(1) <= (congr_cl59_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 59 +with rel_bixu59_wayD_upd select + congr_cl59_wD_d(2) <= (congr_cl59_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 59 +with rel_bixu59_wayD_upd select + congr_cl59_wD_d(3) <= (congr_cl59_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 59 +with rel_bixu59_wayD_upd select + congr_cl59_wD_d(4) <= (congr_cl59_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 59 +with rel_bixu59_wayD_upd select + congr_cl59_wD_d(5) <= (congr_cl59_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 60 +with rel_bixu60_wayD_upd select + congr_cl60_wD_d(0) <= (congr_cl60_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 60 +with rel_bixu60_wayD_upd select + congr_cl60_wD_d(1) <= (congr_cl60_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 60 +with rel_bixu60_wayD_upd select + congr_cl60_wD_d(2) <= (congr_cl60_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 60 +with rel_bixu60_wayD_upd select + congr_cl60_wD_d(3) <= (congr_cl60_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 60 +with rel_bixu60_wayD_upd select + congr_cl60_wD_d(4) <= (congr_cl60_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 60 +with rel_bixu60_wayD_upd select + congr_cl60_wD_d(5) <= (congr_cl60_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 61 +with rel_bixu61_wayD_upd select + congr_cl61_wD_d(0) <= (congr_cl61_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 61 +with rel_bixu61_wayD_upd select + congr_cl61_wD_d(1) <= (congr_cl61_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 61 +with rel_bixu61_wayD_upd select + congr_cl61_wD_d(2) <= (congr_cl61_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 61 +with rel_bixu61_wayD_upd select + congr_cl61_wD_d(3) <= (congr_cl61_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 61 +with rel_bixu61_wayD_upd select + congr_cl61_wD_d(4) <= (congr_cl61_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 61 +with rel_bixu61_wayD_upd select + congr_cl61_wD_d(5) <= (congr_cl61_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 62 +with rel_bixu62_wayD_upd select + congr_cl62_wD_d(0) <= (congr_cl62_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 62 +with rel_bixu62_wayD_upd select + congr_cl62_wD_d(1) <= (congr_cl62_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 62 +with rel_bixu62_wayD_upd select + congr_cl62_wD_d(2) <= (congr_cl62_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 62 +with rel_bixu62_wayD_upd select + congr_cl62_wD_d(3) <= (congr_cl62_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 62 +with rel_bixu62_wayD_upd select + congr_cl62_wD_d(4) <= (congr_cl62_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 62 +with rel_bixu62_wayD_upd select + congr_cl62_wD_d(5) <= (congr_cl62_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayD Valid Bit Update for Congruence Class 63 +with rel_bixu63_wayD_upd select + congr_cl63_wD_d(0) <= (congr_cl63_wD_q(0) and not dci_inval_all_q) when "00", + (flush_wayD_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayD_data2_q(0) and not dci_inval_all_q) when others; +-- WayD Lock Bit Update for Congruence Class 63 +with rel_bixu63_wayD_upd select + congr_cl63_wD_d(1) <= (congr_cl63_wD_q(1) and not lock_finval) when "00", + (flush_wayD_data2_q(1) and not lock_finval) when "01", + (reload_wayD_data2_q(1) and not lock_finval) when others; +-- WayD Thread 0 Watch Bit Update for Congruence Class 63 +with rel_bixu63_wayD_upd select + congr_cl63_wD_d(2) <= (congr_cl63_wD_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayD_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayD Thread 1 Watch Bit Update for Congruence Class 63 +with rel_bixu63_wayD_upd select + congr_cl63_wD_d(3) <= (congr_cl63_wD_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayD_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayD Thread 2 Watch Bit Update for Congruence Class 63 +with rel_bixu63_wayD_upd select + congr_cl63_wD_d(4) <= (congr_cl63_wD_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayD_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayD Thread 3 Watch Bit Update for Congruence Class 63 +with rel_bixu63_wayD_upd select + congr_cl63_wD_d(5) <= (congr_cl63_wD_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayD_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Write Select for WayE +-- WayE Valid Bit Update for Congruence Class 0 +with rel_bixu0_wayE_upd select + congr_cl0_wE_d(0) <= (congr_cl0_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 0 +with rel_bixu0_wayE_upd select + congr_cl0_wE_d(1) <= (congr_cl0_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayE_upd select + congr_cl0_wE_d(2) <= (congr_cl0_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayE_upd select + congr_cl0_wE_d(3) <= (congr_cl0_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayE_upd select + congr_cl0_wE_d(4) <= (congr_cl0_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayE_upd select + congr_cl0_wE_d(5) <= (congr_cl0_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 1 +with rel_bixu1_wayE_upd select + congr_cl1_wE_d(0) <= (congr_cl1_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 1 +with rel_bixu1_wayE_upd select + congr_cl1_wE_d(1) <= (congr_cl1_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayE_upd select + congr_cl1_wE_d(2) <= (congr_cl1_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayE_upd select + congr_cl1_wE_d(3) <= (congr_cl1_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayE_upd select + congr_cl1_wE_d(4) <= (congr_cl1_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayE_upd select + congr_cl1_wE_d(5) <= (congr_cl1_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 2 +with rel_bixu2_wayE_upd select + congr_cl2_wE_d(0) <= (congr_cl2_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 2 +with rel_bixu2_wayE_upd select + congr_cl2_wE_d(1) <= (congr_cl2_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayE_upd select + congr_cl2_wE_d(2) <= (congr_cl2_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayE_upd select + congr_cl2_wE_d(3) <= (congr_cl2_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayE_upd select + congr_cl2_wE_d(4) <= (congr_cl2_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayE_upd select + congr_cl2_wE_d(5) <= (congr_cl2_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 3 +with rel_bixu3_wayE_upd select + congr_cl3_wE_d(0) <= (congr_cl3_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 3 +with rel_bixu3_wayE_upd select + congr_cl3_wE_d(1) <= (congr_cl3_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayE_upd select + congr_cl3_wE_d(2) <= (congr_cl3_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayE_upd select + congr_cl3_wE_d(3) <= (congr_cl3_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayE_upd select + congr_cl3_wE_d(4) <= (congr_cl3_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayE_upd select + congr_cl3_wE_d(5) <= (congr_cl3_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 4 +with rel_bixu4_wayE_upd select + congr_cl4_wE_d(0) <= (congr_cl4_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 4 +with rel_bixu4_wayE_upd select + congr_cl4_wE_d(1) <= (congr_cl4_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayE_upd select + congr_cl4_wE_d(2) <= (congr_cl4_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayE_upd select + congr_cl4_wE_d(3) <= (congr_cl4_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayE_upd select + congr_cl4_wE_d(4) <= (congr_cl4_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayE_upd select + congr_cl4_wE_d(5) <= (congr_cl4_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 5 +with rel_bixu5_wayE_upd select + congr_cl5_wE_d(0) <= (congr_cl5_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 5 +with rel_bixu5_wayE_upd select + congr_cl5_wE_d(1) <= (congr_cl5_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayE_upd select + congr_cl5_wE_d(2) <= (congr_cl5_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayE_upd select + congr_cl5_wE_d(3) <= (congr_cl5_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayE_upd select + congr_cl5_wE_d(4) <= (congr_cl5_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayE_upd select + congr_cl5_wE_d(5) <= (congr_cl5_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 6 +with rel_bixu6_wayE_upd select + congr_cl6_wE_d(0) <= (congr_cl6_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 6 +with rel_bixu6_wayE_upd select + congr_cl6_wE_d(1) <= (congr_cl6_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayE_upd select + congr_cl6_wE_d(2) <= (congr_cl6_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayE_upd select + congr_cl6_wE_d(3) <= (congr_cl6_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayE_upd select + congr_cl6_wE_d(4) <= (congr_cl6_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayE_upd select + congr_cl6_wE_d(5) <= (congr_cl6_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 7 +with rel_bixu7_wayE_upd select + congr_cl7_wE_d(0) <= (congr_cl7_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 7 +with rel_bixu7_wayE_upd select + congr_cl7_wE_d(1) <= (congr_cl7_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayE_upd select + congr_cl7_wE_d(2) <= (congr_cl7_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayE_upd select + congr_cl7_wE_d(3) <= (congr_cl7_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayE_upd select + congr_cl7_wE_d(4) <= (congr_cl7_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayE_upd select + congr_cl7_wE_d(5) <= (congr_cl7_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 8 +with rel_bixu8_wayE_upd select + congr_cl8_wE_d(0) <= (congr_cl8_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 8 +with rel_bixu8_wayE_upd select + congr_cl8_wE_d(1) <= (congr_cl8_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayE_upd select + congr_cl8_wE_d(2) <= (congr_cl8_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayE_upd select + congr_cl8_wE_d(3) <= (congr_cl8_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayE_upd select + congr_cl8_wE_d(4) <= (congr_cl8_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayE_upd select + congr_cl8_wE_d(5) <= (congr_cl8_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 9 +with rel_bixu9_wayE_upd select + congr_cl9_wE_d(0) <= (congr_cl9_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 9 +with rel_bixu9_wayE_upd select + congr_cl9_wE_d(1) <= (congr_cl9_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayE_upd select + congr_cl9_wE_d(2) <= (congr_cl9_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayE_upd select + congr_cl9_wE_d(3) <= (congr_cl9_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayE_upd select + congr_cl9_wE_d(4) <= (congr_cl9_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayE_upd select + congr_cl9_wE_d(5) <= (congr_cl9_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 10 +with rel_bixu10_wayE_upd select + congr_cl10_wE_d(0) <= (congr_cl10_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 10 +with rel_bixu10_wayE_upd select + congr_cl10_wE_d(1) <= (congr_cl10_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayE_upd select + congr_cl10_wE_d(2) <= (congr_cl10_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayE_upd select + congr_cl10_wE_d(3) <= (congr_cl10_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayE_upd select + congr_cl10_wE_d(4) <= (congr_cl10_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayE_upd select + congr_cl10_wE_d(5) <= (congr_cl10_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 11 +with rel_bixu11_wayE_upd select + congr_cl11_wE_d(0) <= (congr_cl11_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 11 +with rel_bixu11_wayE_upd select + congr_cl11_wE_d(1) <= (congr_cl11_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayE_upd select + congr_cl11_wE_d(2) <= (congr_cl11_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayE_upd select + congr_cl11_wE_d(3) <= (congr_cl11_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayE_upd select + congr_cl11_wE_d(4) <= (congr_cl11_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayE_upd select + congr_cl11_wE_d(5) <= (congr_cl11_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 12 +with rel_bixu12_wayE_upd select + congr_cl12_wE_d(0) <= (congr_cl12_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 12 +with rel_bixu12_wayE_upd select + congr_cl12_wE_d(1) <= (congr_cl12_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayE_upd select + congr_cl12_wE_d(2) <= (congr_cl12_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayE_upd select + congr_cl12_wE_d(3) <= (congr_cl12_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayE_upd select + congr_cl12_wE_d(4) <= (congr_cl12_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayE_upd select + congr_cl12_wE_d(5) <= (congr_cl12_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 13 +with rel_bixu13_wayE_upd select + congr_cl13_wE_d(0) <= (congr_cl13_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 13 +with rel_bixu13_wayE_upd select + congr_cl13_wE_d(1) <= (congr_cl13_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayE_upd select + congr_cl13_wE_d(2) <= (congr_cl13_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayE_upd select + congr_cl13_wE_d(3) <= (congr_cl13_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayE_upd select + congr_cl13_wE_d(4) <= (congr_cl13_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayE_upd select + congr_cl13_wE_d(5) <= (congr_cl13_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 14 +with rel_bixu14_wayE_upd select + congr_cl14_wE_d(0) <= (congr_cl14_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 14 +with rel_bixu14_wayE_upd select + congr_cl14_wE_d(1) <= (congr_cl14_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayE_upd select + congr_cl14_wE_d(2) <= (congr_cl14_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayE_upd select + congr_cl14_wE_d(3) <= (congr_cl14_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayE_upd select + congr_cl14_wE_d(4) <= (congr_cl14_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayE_upd select + congr_cl14_wE_d(5) <= (congr_cl14_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 15 +with rel_bixu15_wayE_upd select + congr_cl15_wE_d(0) <= (congr_cl15_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 15 +with rel_bixu15_wayE_upd select + congr_cl15_wE_d(1) <= (congr_cl15_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayE_upd select + congr_cl15_wE_d(2) <= (congr_cl15_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayE_upd select + congr_cl15_wE_d(3) <= (congr_cl15_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayE_upd select + congr_cl15_wE_d(4) <= (congr_cl15_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayE_upd select + congr_cl15_wE_d(5) <= (congr_cl15_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 16 +with rel_bixu16_wayE_upd select + congr_cl16_wE_d(0) <= (congr_cl16_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 16 +with rel_bixu16_wayE_upd select + congr_cl16_wE_d(1) <= (congr_cl16_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayE_upd select + congr_cl16_wE_d(2) <= (congr_cl16_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayE_upd select + congr_cl16_wE_d(3) <= (congr_cl16_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayE_upd select + congr_cl16_wE_d(4) <= (congr_cl16_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayE_upd select + congr_cl16_wE_d(5) <= (congr_cl16_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 17 +with rel_bixu17_wayE_upd select + congr_cl17_wE_d(0) <= (congr_cl17_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 17 +with rel_bixu17_wayE_upd select + congr_cl17_wE_d(1) <= (congr_cl17_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayE_upd select + congr_cl17_wE_d(2) <= (congr_cl17_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayE_upd select + congr_cl17_wE_d(3) <= (congr_cl17_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayE_upd select + congr_cl17_wE_d(4) <= (congr_cl17_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayE_upd select + congr_cl17_wE_d(5) <= (congr_cl17_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 18 +with rel_bixu18_wayE_upd select + congr_cl18_wE_d(0) <= (congr_cl18_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 18 +with rel_bixu18_wayE_upd select + congr_cl18_wE_d(1) <= (congr_cl18_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayE_upd select + congr_cl18_wE_d(2) <= (congr_cl18_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayE_upd select + congr_cl18_wE_d(3) <= (congr_cl18_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayE_upd select + congr_cl18_wE_d(4) <= (congr_cl18_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayE_upd select + congr_cl18_wE_d(5) <= (congr_cl18_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 19 +with rel_bixu19_wayE_upd select + congr_cl19_wE_d(0) <= (congr_cl19_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 19 +with rel_bixu19_wayE_upd select + congr_cl19_wE_d(1) <= (congr_cl19_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayE_upd select + congr_cl19_wE_d(2) <= (congr_cl19_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayE_upd select + congr_cl19_wE_d(3) <= (congr_cl19_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayE_upd select + congr_cl19_wE_d(4) <= (congr_cl19_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayE_upd select + congr_cl19_wE_d(5) <= (congr_cl19_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 20 +with rel_bixu20_wayE_upd select + congr_cl20_wE_d(0) <= (congr_cl20_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 20 +with rel_bixu20_wayE_upd select + congr_cl20_wE_d(1) <= (congr_cl20_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayE_upd select + congr_cl20_wE_d(2) <= (congr_cl20_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayE_upd select + congr_cl20_wE_d(3) <= (congr_cl20_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayE_upd select + congr_cl20_wE_d(4) <= (congr_cl20_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayE_upd select + congr_cl20_wE_d(5) <= (congr_cl20_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 21 +with rel_bixu21_wayE_upd select + congr_cl21_wE_d(0) <= (congr_cl21_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 21 +with rel_bixu21_wayE_upd select + congr_cl21_wE_d(1) <= (congr_cl21_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayE_upd select + congr_cl21_wE_d(2) <= (congr_cl21_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayE_upd select + congr_cl21_wE_d(3) <= (congr_cl21_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayE_upd select + congr_cl21_wE_d(4) <= (congr_cl21_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayE_upd select + congr_cl21_wE_d(5) <= (congr_cl21_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 22 +with rel_bixu22_wayE_upd select + congr_cl22_wE_d(0) <= (congr_cl22_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 22 +with rel_bixu22_wayE_upd select + congr_cl22_wE_d(1) <= (congr_cl22_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayE_upd select + congr_cl22_wE_d(2) <= (congr_cl22_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayE_upd select + congr_cl22_wE_d(3) <= (congr_cl22_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayE_upd select + congr_cl22_wE_d(4) <= (congr_cl22_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayE_upd select + congr_cl22_wE_d(5) <= (congr_cl22_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 23 +with rel_bixu23_wayE_upd select + congr_cl23_wE_d(0) <= (congr_cl23_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 23 +with rel_bixu23_wayE_upd select + congr_cl23_wE_d(1) <= (congr_cl23_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayE_upd select + congr_cl23_wE_d(2) <= (congr_cl23_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayE_upd select + congr_cl23_wE_d(3) <= (congr_cl23_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayE_upd select + congr_cl23_wE_d(4) <= (congr_cl23_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayE_upd select + congr_cl23_wE_d(5) <= (congr_cl23_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 24 +with rel_bixu24_wayE_upd select + congr_cl24_wE_d(0) <= (congr_cl24_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 24 +with rel_bixu24_wayE_upd select + congr_cl24_wE_d(1) <= (congr_cl24_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayE_upd select + congr_cl24_wE_d(2) <= (congr_cl24_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayE_upd select + congr_cl24_wE_d(3) <= (congr_cl24_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayE_upd select + congr_cl24_wE_d(4) <= (congr_cl24_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayE_upd select + congr_cl24_wE_d(5) <= (congr_cl24_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 25 +with rel_bixu25_wayE_upd select + congr_cl25_wE_d(0) <= (congr_cl25_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 25 +with rel_bixu25_wayE_upd select + congr_cl25_wE_d(1) <= (congr_cl25_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayE_upd select + congr_cl25_wE_d(2) <= (congr_cl25_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayE_upd select + congr_cl25_wE_d(3) <= (congr_cl25_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayE_upd select + congr_cl25_wE_d(4) <= (congr_cl25_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayE_upd select + congr_cl25_wE_d(5) <= (congr_cl25_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 26 +with rel_bixu26_wayE_upd select + congr_cl26_wE_d(0) <= (congr_cl26_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 26 +with rel_bixu26_wayE_upd select + congr_cl26_wE_d(1) <= (congr_cl26_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayE_upd select + congr_cl26_wE_d(2) <= (congr_cl26_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayE_upd select + congr_cl26_wE_d(3) <= (congr_cl26_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayE_upd select + congr_cl26_wE_d(4) <= (congr_cl26_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayE_upd select + congr_cl26_wE_d(5) <= (congr_cl26_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 27 +with rel_bixu27_wayE_upd select + congr_cl27_wE_d(0) <= (congr_cl27_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 27 +with rel_bixu27_wayE_upd select + congr_cl27_wE_d(1) <= (congr_cl27_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayE_upd select + congr_cl27_wE_d(2) <= (congr_cl27_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayE_upd select + congr_cl27_wE_d(3) <= (congr_cl27_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayE_upd select + congr_cl27_wE_d(4) <= (congr_cl27_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayE_upd select + congr_cl27_wE_d(5) <= (congr_cl27_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 28 +with rel_bixu28_wayE_upd select + congr_cl28_wE_d(0) <= (congr_cl28_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 28 +with rel_bixu28_wayE_upd select + congr_cl28_wE_d(1) <= (congr_cl28_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayE_upd select + congr_cl28_wE_d(2) <= (congr_cl28_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayE_upd select + congr_cl28_wE_d(3) <= (congr_cl28_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayE_upd select + congr_cl28_wE_d(4) <= (congr_cl28_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayE_upd select + congr_cl28_wE_d(5) <= (congr_cl28_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 29 +with rel_bixu29_wayE_upd select + congr_cl29_wE_d(0) <= (congr_cl29_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 29 +with rel_bixu29_wayE_upd select + congr_cl29_wE_d(1) <= (congr_cl29_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayE_upd select + congr_cl29_wE_d(2) <= (congr_cl29_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayE_upd select + congr_cl29_wE_d(3) <= (congr_cl29_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayE_upd select + congr_cl29_wE_d(4) <= (congr_cl29_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayE_upd select + congr_cl29_wE_d(5) <= (congr_cl29_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 30 +with rel_bixu30_wayE_upd select + congr_cl30_wE_d(0) <= (congr_cl30_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 30 +with rel_bixu30_wayE_upd select + congr_cl30_wE_d(1) <= (congr_cl30_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayE_upd select + congr_cl30_wE_d(2) <= (congr_cl30_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayE_upd select + congr_cl30_wE_d(3) <= (congr_cl30_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayE_upd select + congr_cl30_wE_d(4) <= (congr_cl30_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayE_upd select + congr_cl30_wE_d(5) <= (congr_cl30_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 31 +with rel_bixu31_wayE_upd select + congr_cl31_wE_d(0) <= (congr_cl31_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 31 +with rel_bixu31_wayE_upd select + congr_cl31_wE_d(1) <= (congr_cl31_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayE_upd select + congr_cl31_wE_d(2) <= (congr_cl31_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayE_upd select + congr_cl31_wE_d(3) <= (congr_cl31_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayE_upd select + congr_cl31_wE_d(4) <= (congr_cl31_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayE_upd select + congr_cl31_wE_d(5) <= (congr_cl31_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 32 +with rel_bixu32_wayE_upd select + congr_cl32_wE_d(0) <= (congr_cl32_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 32 +with rel_bixu32_wayE_upd select + congr_cl32_wE_d(1) <= (congr_cl32_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 32 +with rel_bixu32_wayE_upd select + congr_cl32_wE_d(2) <= (congr_cl32_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 32 +with rel_bixu32_wayE_upd select + congr_cl32_wE_d(3) <= (congr_cl32_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 32 +with rel_bixu32_wayE_upd select + congr_cl32_wE_d(4) <= (congr_cl32_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 32 +with rel_bixu32_wayE_upd select + congr_cl32_wE_d(5) <= (congr_cl32_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 33 +with rel_bixu33_wayE_upd select + congr_cl33_wE_d(0) <= (congr_cl33_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 33 +with rel_bixu33_wayE_upd select + congr_cl33_wE_d(1) <= (congr_cl33_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 33 +with rel_bixu33_wayE_upd select + congr_cl33_wE_d(2) <= (congr_cl33_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 33 +with rel_bixu33_wayE_upd select + congr_cl33_wE_d(3) <= (congr_cl33_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 33 +with rel_bixu33_wayE_upd select + congr_cl33_wE_d(4) <= (congr_cl33_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 33 +with rel_bixu33_wayE_upd select + congr_cl33_wE_d(5) <= (congr_cl33_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 34 +with rel_bixu34_wayE_upd select + congr_cl34_wE_d(0) <= (congr_cl34_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 34 +with rel_bixu34_wayE_upd select + congr_cl34_wE_d(1) <= (congr_cl34_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 34 +with rel_bixu34_wayE_upd select + congr_cl34_wE_d(2) <= (congr_cl34_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 34 +with rel_bixu34_wayE_upd select + congr_cl34_wE_d(3) <= (congr_cl34_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 34 +with rel_bixu34_wayE_upd select + congr_cl34_wE_d(4) <= (congr_cl34_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 34 +with rel_bixu34_wayE_upd select + congr_cl34_wE_d(5) <= (congr_cl34_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 35 +with rel_bixu35_wayE_upd select + congr_cl35_wE_d(0) <= (congr_cl35_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 35 +with rel_bixu35_wayE_upd select + congr_cl35_wE_d(1) <= (congr_cl35_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 35 +with rel_bixu35_wayE_upd select + congr_cl35_wE_d(2) <= (congr_cl35_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 35 +with rel_bixu35_wayE_upd select + congr_cl35_wE_d(3) <= (congr_cl35_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 35 +with rel_bixu35_wayE_upd select + congr_cl35_wE_d(4) <= (congr_cl35_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 35 +with rel_bixu35_wayE_upd select + congr_cl35_wE_d(5) <= (congr_cl35_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 36 +with rel_bixu36_wayE_upd select + congr_cl36_wE_d(0) <= (congr_cl36_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 36 +with rel_bixu36_wayE_upd select + congr_cl36_wE_d(1) <= (congr_cl36_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 36 +with rel_bixu36_wayE_upd select + congr_cl36_wE_d(2) <= (congr_cl36_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 36 +with rel_bixu36_wayE_upd select + congr_cl36_wE_d(3) <= (congr_cl36_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 36 +with rel_bixu36_wayE_upd select + congr_cl36_wE_d(4) <= (congr_cl36_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 36 +with rel_bixu36_wayE_upd select + congr_cl36_wE_d(5) <= (congr_cl36_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 37 +with rel_bixu37_wayE_upd select + congr_cl37_wE_d(0) <= (congr_cl37_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 37 +with rel_bixu37_wayE_upd select + congr_cl37_wE_d(1) <= (congr_cl37_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 37 +with rel_bixu37_wayE_upd select + congr_cl37_wE_d(2) <= (congr_cl37_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 37 +with rel_bixu37_wayE_upd select + congr_cl37_wE_d(3) <= (congr_cl37_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 37 +with rel_bixu37_wayE_upd select + congr_cl37_wE_d(4) <= (congr_cl37_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 37 +with rel_bixu37_wayE_upd select + congr_cl37_wE_d(5) <= (congr_cl37_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 38 +with rel_bixu38_wayE_upd select + congr_cl38_wE_d(0) <= (congr_cl38_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 38 +with rel_bixu38_wayE_upd select + congr_cl38_wE_d(1) <= (congr_cl38_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 38 +with rel_bixu38_wayE_upd select + congr_cl38_wE_d(2) <= (congr_cl38_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 38 +with rel_bixu38_wayE_upd select + congr_cl38_wE_d(3) <= (congr_cl38_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 38 +with rel_bixu38_wayE_upd select + congr_cl38_wE_d(4) <= (congr_cl38_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 38 +with rel_bixu38_wayE_upd select + congr_cl38_wE_d(5) <= (congr_cl38_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 39 +with rel_bixu39_wayE_upd select + congr_cl39_wE_d(0) <= (congr_cl39_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 39 +with rel_bixu39_wayE_upd select + congr_cl39_wE_d(1) <= (congr_cl39_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 39 +with rel_bixu39_wayE_upd select + congr_cl39_wE_d(2) <= (congr_cl39_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 39 +with rel_bixu39_wayE_upd select + congr_cl39_wE_d(3) <= (congr_cl39_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 39 +with rel_bixu39_wayE_upd select + congr_cl39_wE_d(4) <= (congr_cl39_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 39 +with rel_bixu39_wayE_upd select + congr_cl39_wE_d(5) <= (congr_cl39_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 40 +with rel_bixu40_wayE_upd select + congr_cl40_wE_d(0) <= (congr_cl40_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 40 +with rel_bixu40_wayE_upd select + congr_cl40_wE_d(1) <= (congr_cl40_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 40 +with rel_bixu40_wayE_upd select + congr_cl40_wE_d(2) <= (congr_cl40_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 40 +with rel_bixu40_wayE_upd select + congr_cl40_wE_d(3) <= (congr_cl40_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 40 +with rel_bixu40_wayE_upd select + congr_cl40_wE_d(4) <= (congr_cl40_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 40 +with rel_bixu40_wayE_upd select + congr_cl40_wE_d(5) <= (congr_cl40_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 41 +with rel_bixu41_wayE_upd select + congr_cl41_wE_d(0) <= (congr_cl41_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 41 +with rel_bixu41_wayE_upd select + congr_cl41_wE_d(1) <= (congr_cl41_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 41 +with rel_bixu41_wayE_upd select + congr_cl41_wE_d(2) <= (congr_cl41_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 41 +with rel_bixu41_wayE_upd select + congr_cl41_wE_d(3) <= (congr_cl41_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 41 +with rel_bixu41_wayE_upd select + congr_cl41_wE_d(4) <= (congr_cl41_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 41 +with rel_bixu41_wayE_upd select + congr_cl41_wE_d(5) <= (congr_cl41_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 42 +with rel_bixu42_wayE_upd select + congr_cl42_wE_d(0) <= (congr_cl42_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 42 +with rel_bixu42_wayE_upd select + congr_cl42_wE_d(1) <= (congr_cl42_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 42 +with rel_bixu42_wayE_upd select + congr_cl42_wE_d(2) <= (congr_cl42_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 42 +with rel_bixu42_wayE_upd select + congr_cl42_wE_d(3) <= (congr_cl42_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 42 +with rel_bixu42_wayE_upd select + congr_cl42_wE_d(4) <= (congr_cl42_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 42 +with rel_bixu42_wayE_upd select + congr_cl42_wE_d(5) <= (congr_cl42_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 43 +with rel_bixu43_wayE_upd select + congr_cl43_wE_d(0) <= (congr_cl43_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 43 +with rel_bixu43_wayE_upd select + congr_cl43_wE_d(1) <= (congr_cl43_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 43 +with rel_bixu43_wayE_upd select + congr_cl43_wE_d(2) <= (congr_cl43_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 43 +with rel_bixu43_wayE_upd select + congr_cl43_wE_d(3) <= (congr_cl43_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 43 +with rel_bixu43_wayE_upd select + congr_cl43_wE_d(4) <= (congr_cl43_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 43 +with rel_bixu43_wayE_upd select + congr_cl43_wE_d(5) <= (congr_cl43_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 44 +with rel_bixu44_wayE_upd select + congr_cl44_wE_d(0) <= (congr_cl44_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 44 +with rel_bixu44_wayE_upd select + congr_cl44_wE_d(1) <= (congr_cl44_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 44 +with rel_bixu44_wayE_upd select + congr_cl44_wE_d(2) <= (congr_cl44_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 44 +with rel_bixu44_wayE_upd select + congr_cl44_wE_d(3) <= (congr_cl44_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 44 +with rel_bixu44_wayE_upd select + congr_cl44_wE_d(4) <= (congr_cl44_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 44 +with rel_bixu44_wayE_upd select + congr_cl44_wE_d(5) <= (congr_cl44_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 45 +with rel_bixu45_wayE_upd select + congr_cl45_wE_d(0) <= (congr_cl45_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 45 +with rel_bixu45_wayE_upd select + congr_cl45_wE_d(1) <= (congr_cl45_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 45 +with rel_bixu45_wayE_upd select + congr_cl45_wE_d(2) <= (congr_cl45_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 45 +with rel_bixu45_wayE_upd select + congr_cl45_wE_d(3) <= (congr_cl45_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 45 +with rel_bixu45_wayE_upd select + congr_cl45_wE_d(4) <= (congr_cl45_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 45 +with rel_bixu45_wayE_upd select + congr_cl45_wE_d(5) <= (congr_cl45_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 46 +with rel_bixu46_wayE_upd select + congr_cl46_wE_d(0) <= (congr_cl46_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 46 +with rel_bixu46_wayE_upd select + congr_cl46_wE_d(1) <= (congr_cl46_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 46 +with rel_bixu46_wayE_upd select + congr_cl46_wE_d(2) <= (congr_cl46_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 46 +with rel_bixu46_wayE_upd select + congr_cl46_wE_d(3) <= (congr_cl46_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 46 +with rel_bixu46_wayE_upd select + congr_cl46_wE_d(4) <= (congr_cl46_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 46 +with rel_bixu46_wayE_upd select + congr_cl46_wE_d(5) <= (congr_cl46_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 47 +with rel_bixu47_wayE_upd select + congr_cl47_wE_d(0) <= (congr_cl47_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 47 +with rel_bixu47_wayE_upd select + congr_cl47_wE_d(1) <= (congr_cl47_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 47 +with rel_bixu47_wayE_upd select + congr_cl47_wE_d(2) <= (congr_cl47_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 47 +with rel_bixu47_wayE_upd select + congr_cl47_wE_d(3) <= (congr_cl47_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 47 +with rel_bixu47_wayE_upd select + congr_cl47_wE_d(4) <= (congr_cl47_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 47 +with rel_bixu47_wayE_upd select + congr_cl47_wE_d(5) <= (congr_cl47_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 48 +with rel_bixu48_wayE_upd select + congr_cl48_wE_d(0) <= (congr_cl48_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 48 +with rel_bixu48_wayE_upd select + congr_cl48_wE_d(1) <= (congr_cl48_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 48 +with rel_bixu48_wayE_upd select + congr_cl48_wE_d(2) <= (congr_cl48_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 48 +with rel_bixu48_wayE_upd select + congr_cl48_wE_d(3) <= (congr_cl48_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 48 +with rel_bixu48_wayE_upd select + congr_cl48_wE_d(4) <= (congr_cl48_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 48 +with rel_bixu48_wayE_upd select + congr_cl48_wE_d(5) <= (congr_cl48_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 49 +with rel_bixu49_wayE_upd select + congr_cl49_wE_d(0) <= (congr_cl49_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 49 +with rel_bixu49_wayE_upd select + congr_cl49_wE_d(1) <= (congr_cl49_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 49 +with rel_bixu49_wayE_upd select + congr_cl49_wE_d(2) <= (congr_cl49_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 49 +with rel_bixu49_wayE_upd select + congr_cl49_wE_d(3) <= (congr_cl49_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 49 +with rel_bixu49_wayE_upd select + congr_cl49_wE_d(4) <= (congr_cl49_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 49 +with rel_bixu49_wayE_upd select + congr_cl49_wE_d(5) <= (congr_cl49_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 50 +with rel_bixu50_wayE_upd select + congr_cl50_wE_d(0) <= (congr_cl50_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 50 +with rel_bixu50_wayE_upd select + congr_cl50_wE_d(1) <= (congr_cl50_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 50 +with rel_bixu50_wayE_upd select + congr_cl50_wE_d(2) <= (congr_cl50_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 50 +with rel_bixu50_wayE_upd select + congr_cl50_wE_d(3) <= (congr_cl50_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 50 +with rel_bixu50_wayE_upd select + congr_cl50_wE_d(4) <= (congr_cl50_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 50 +with rel_bixu50_wayE_upd select + congr_cl50_wE_d(5) <= (congr_cl50_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 51 +with rel_bixu51_wayE_upd select + congr_cl51_wE_d(0) <= (congr_cl51_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 51 +with rel_bixu51_wayE_upd select + congr_cl51_wE_d(1) <= (congr_cl51_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 51 +with rel_bixu51_wayE_upd select + congr_cl51_wE_d(2) <= (congr_cl51_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 51 +with rel_bixu51_wayE_upd select + congr_cl51_wE_d(3) <= (congr_cl51_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 51 +with rel_bixu51_wayE_upd select + congr_cl51_wE_d(4) <= (congr_cl51_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 51 +with rel_bixu51_wayE_upd select + congr_cl51_wE_d(5) <= (congr_cl51_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 52 +with rel_bixu52_wayE_upd select + congr_cl52_wE_d(0) <= (congr_cl52_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 52 +with rel_bixu52_wayE_upd select + congr_cl52_wE_d(1) <= (congr_cl52_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 52 +with rel_bixu52_wayE_upd select + congr_cl52_wE_d(2) <= (congr_cl52_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 52 +with rel_bixu52_wayE_upd select + congr_cl52_wE_d(3) <= (congr_cl52_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 52 +with rel_bixu52_wayE_upd select + congr_cl52_wE_d(4) <= (congr_cl52_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 52 +with rel_bixu52_wayE_upd select + congr_cl52_wE_d(5) <= (congr_cl52_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 53 +with rel_bixu53_wayE_upd select + congr_cl53_wE_d(0) <= (congr_cl53_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 53 +with rel_bixu53_wayE_upd select + congr_cl53_wE_d(1) <= (congr_cl53_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 53 +with rel_bixu53_wayE_upd select + congr_cl53_wE_d(2) <= (congr_cl53_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 53 +with rel_bixu53_wayE_upd select + congr_cl53_wE_d(3) <= (congr_cl53_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 53 +with rel_bixu53_wayE_upd select + congr_cl53_wE_d(4) <= (congr_cl53_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 53 +with rel_bixu53_wayE_upd select + congr_cl53_wE_d(5) <= (congr_cl53_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 54 +with rel_bixu54_wayE_upd select + congr_cl54_wE_d(0) <= (congr_cl54_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 54 +with rel_bixu54_wayE_upd select + congr_cl54_wE_d(1) <= (congr_cl54_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 54 +with rel_bixu54_wayE_upd select + congr_cl54_wE_d(2) <= (congr_cl54_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 54 +with rel_bixu54_wayE_upd select + congr_cl54_wE_d(3) <= (congr_cl54_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 54 +with rel_bixu54_wayE_upd select + congr_cl54_wE_d(4) <= (congr_cl54_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 54 +with rel_bixu54_wayE_upd select + congr_cl54_wE_d(5) <= (congr_cl54_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 55 +with rel_bixu55_wayE_upd select + congr_cl55_wE_d(0) <= (congr_cl55_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 55 +with rel_bixu55_wayE_upd select + congr_cl55_wE_d(1) <= (congr_cl55_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 55 +with rel_bixu55_wayE_upd select + congr_cl55_wE_d(2) <= (congr_cl55_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 55 +with rel_bixu55_wayE_upd select + congr_cl55_wE_d(3) <= (congr_cl55_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 55 +with rel_bixu55_wayE_upd select + congr_cl55_wE_d(4) <= (congr_cl55_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 55 +with rel_bixu55_wayE_upd select + congr_cl55_wE_d(5) <= (congr_cl55_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 56 +with rel_bixu56_wayE_upd select + congr_cl56_wE_d(0) <= (congr_cl56_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 56 +with rel_bixu56_wayE_upd select + congr_cl56_wE_d(1) <= (congr_cl56_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 56 +with rel_bixu56_wayE_upd select + congr_cl56_wE_d(2) <= (congr_cl56_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 56 +with rel_bixu56_wayE_upd select + congr_cl56_wE_d(3) <= (congr_cl56_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 56 +with rel_bixu56_wayE_upd select + congr_cl56_wE_d(4) <= (congr_cl56_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 56 +with rel_bixu56_wayE_upd select + congr_cl56_wE_d(5) <= (congr_cl56_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 57 +with rel_bixu57_wayE_upd select + congr_cl57_wE_d(0) <= (congr_cl57_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 57 +with rel_bixu57_wayE_upd select + congr_cl57_wE_d(1) <= (congr_cl57_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 57 +with rel_bixu57_wayE_upd select + congr_cl57_wE_d(2) <= (congr_cl57_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 57 +with rel_bixu57_wayE_upd select + congr_cl57_wE_d(3) <= (congr_cl57_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 57 +with rel_bixu57_wayE_upd select + congr_cl57_wE_d(4) <= (congr_cl57_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 57 +with rel_bixu57_wayE_upd select + congr_cl57_wE_d(5) <= (congr_cl57_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 58 +with rel_bixu58_wayE_upd select + congr_cl58_wE_d(0) <= (congr_cl58_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 58 +with rel_bixu58_wayE_upd select + congr_cl58_wE_d(1) <= (congr_cl58_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 58 +with rel_bixu58_wayE_upd select + congr_cl58_wE_d(2) <= (congr_cl58_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 58 +with rel_bixu58_wayE_upd select + congr_cl58_wE_d(3) <= (congr_cl58_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 58 +with rel_bixu58_wayE_upd select + congr_cl58_wE_d(4) <= (congr_cl58_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 58 +with rel_bixu58_wayE_upd select + congr_cl58_wE_d(5) <= (congr_cl58_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 59 +with rel_bixu59_wayE_upd select + congr_cl59_wE_d(0) <= (congr_cl59_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 59 +with rel_bixu59_wayE_upd select + congr_cl59_wE_d(1) <= (congr_cl59_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 59 +with rel_bixu59_wayE_upd select + congr_cl59_wE_d(2) <= (congr_cl59_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 59 +with rel_bixu59_wayE_upd select + congr_cl59_wE_d(3) <= (congr_cl59_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 59 +with rel_bixu59_wayE_upd select + congr_cl59_wE_d(4) <= (congr_cl59_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 59 +with rel_bixu59_wayE_upd select + congr_cl59_wE_d(5) <= (congr_cl59_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 60 +with rel_bixu60_wayE_upd select + congr_cl60_wE_d(0) <= (congr_cl60_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 60 +with rel_bixu60_wayE_upd select + congr_cl60_wE_d(1) <= (congr_cl60_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 60 +with rel_bixu60_wayE_upd select + congr_cl60_wE_d(2) <= (congr_cl60_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 60 +with rel_bixu60_wayE_upd select + congr_cl60_wE_d(3) <= (congr_cl60_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 60 +with rel_bixu60_wayE_upd select + congr_cl60_wE_d(4) <= (congr_cl60_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 60 +with rel_bixu60_wayE_upd select + congr_cl60_wE_d(5) <= (congr_cl60_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 61 +with rel_bixu61_wayE_upd select + congr_cl61_wE_d(0) <= (congr_cl61_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 61 +with rel_bixu61_wayE_upd select + congr_cl61_wE_d(1) <= (congr_cl61_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 61 +with rel_bixu61_wayE_upd select + congr_cl61_wE_d(2) <= (congr_cl61_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 61 +with rel_bixu61_wayE_upd select + congr_cl61_wE_d(3) <= (congr_cl61_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 61 +with rel_bixu61_wayE_upd select + congr_cl61_wE_d(4) <= (congr_cl61_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 61 +with rel_bixu61_wayE_upd select + congr_cl61_wE_d(5) <= (congr_cl61_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 62 +with rel_bixu62_wayE_upd select + congr_cl62_wE_d(0) <= (congr_cl62_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 62 +with rel_bixu62_wayE_upd select + congr_cl62_wE_d(1) <= (congr_cl62_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 62 +with rel_bixu62_wayE_upd select + congr_cl62_wE_d(2) <= (congr_cl62_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 62 +with rel_bixu62_wayE_upd select + congr_cl62_wE_d(3) <= (congr_cl62_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 62 +with rel_bixu62_wayE_upd select + congr_cl62_wE_d(4) <= (congr_cl62_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 62 +with rel_bixu62_wayE_upd select + congr_cl62_wE_d(5) <= (congr_cl62_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayE Valid Bit Update for Congruence Class 63 +with rel_bixu63_wayE_upd select + congr_cl63_wE_d(0) <= (congr_cl63_wE_q(0) and not dci_inval_all_q) when "00", + (flush_wayE_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayE_data2_q(0) and not dci_inval_all_q) when others; +-- WayE Lock Bit Update for Congruence Class 63 +with rel_bixu63_wayE_upd select + congr_cl63_wE_d(1) <= (congr_cl63_wE_q(1) and not lock_finval) when "00", + (flush_wayE_data2_q(1) and not lock_finval) when "01", + (reload_wayE_data2_q(1) and not lock_finval) when others; +-- WayE Thread 0 Watch Bit Update for Congruence Class 63 +with rel_bixu63_wayE_upd select + congr_cl63_wE_d(2) <= (congr_cl63_wE_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayE_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayE Thread 1 Watch Bit Update for Congruence Class 63 +with rel_bixu63_wayE_upd select + congr_cl63_wE_d(3) <= (congr_cl63_wE_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayE_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayE Thread 2 Watch Bit Update for Congruence Class 63 +with rel_bixu63_wayE_upd select + congr_cl63_wE_d(4) <= (congr_cl63_wE_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayE_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayE Thread 3 Watch Bit Update for Congruence Class 63 +with rel_bixu63_wayE_upd select + congr_cl63_wE_d(5) <= (congr_cl63_wE_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayE_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Write Select for WayF +-- WayF Valid Bit Update for Congruence Class 0 +with rel_bixu0_wayF_upd select + congr_cl0_wF_d(0) <= (congr_cl0_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 0 +with rel_bixu0_wayF_upd select + congr_cl0_wF_d(1) <= (congr_cl0_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayF_upd select + congr_cl0_wF_d(2) <= (congr_cl0_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayF_upd select + congr_cl0_wF_d(3) <= (congr_cl0_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayF_upd select + congr_cl0_wF_d(4) <= (congr_cl0_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayF_upd select + congr_cl0_wF_d(5) <= (congr_cl0_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 1 +with rel_bixu1_wayF_upd select + congr_cl1_wF_d(0) <= (congr_cl1_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 1 +with rel_bixu1_wayF_upd select + congr_cl1_wF_d(1) <= (congr_cl1_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayF_upd select + congr_cl1_wF_d(2) <= (congr_cl1_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayF_upd select + congr_cl1_wF_d(3) <= (congr_cl1_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayF_upd select + congr_cl1_wF_d(4) <= (congr_cl1_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayF_upd select + congr_cl1_wF_d(5) <= (congr_cl1_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 2 +with rel_bixu2_wayF_upd select + congr_cl2_wF_d(0) <= (congr_cl2_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 2 +with rel_bixu2_wayF_upd select + congr_cl2_wF_d(1) <= (congr_cl2_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayF_upd select + congr_cl2_wF_d(2) <= (congr_cl2_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayF_upd select + congr_cl2_wF_d(3) <= (congr_cl2_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayF_upd select + congr_cl2_wF_d(4) <= (congr_cl2_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayF_upd select + congr_cl2_wF_d(5) <= (congr_cl2_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 3 +with rel_bixu3_wayF_upd select + congr_cl3_wF_d(0) <= (congr_cl3_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 3 +with rel_bixu3_wayF_upd select + congr_cl3_wF_d(1) <= (congr_cl3_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayF_upd select + congr_cl3_wF_d(2) <= (congr_cl3_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayF_upd select + congr_cl3_wF_d(3) <= (congr_cl3_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayF_upd select + congr_cl3_wF_d(4) <= (congr_cl3_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayF_upd select + congr_cl3_wF_d(5) <= (congr_cl3_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 4 +with rel_bixu4_wayF_upd select + congr_cl4_wF_d(0) <= (congr_cl4_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 4 +with rel_bixu4_wayF_upd select + congr_cl4_wF_d(1) <= (congr_cl4_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayF_upd select + congr_cl4_wF_d(2) <= (congr_cl4_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayF_upd select + congr_cl4_wF_d(3) <= (congr_cl4_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayF_upd select + congr_cl4_wF_d(4) <= (congr_cl4_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayF_upd select + congr_cl4_wF_d(5) <= (congr_cl4_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 5 +with rel_bixu5_wayF_upd select + congr_cl5_wF_d(0) <= (congr_cl5_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 5 +with rel_bixu5_wayF_upd select + congr_cl5_wF_d(1) <= (congr_cl5_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayF_upd select + congr_cl5_wF_d(2) <= (congr_cl5_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayF_upd select + congr_cl5_wF_d(3) <= (congr_cl5_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayF_upd select + congr_cl5_wF_d(4) <= (congr_cl5_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayF_upd select + congr_cl5_wF_d(5) <= (congr_cl5_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 6 +with rel_bixu6_wayF_upd select + congr_cl6_wF_d(0) <= (congr_cl6_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 6 +with rel_bixu6_wayF_upd select + congr_cl6_wF_d(1) <= (congr_cl6_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayF_upd select + congr_cl6_wF_d(2) <= (congr_cl6_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayF_upd select + congr_cl6_wF_d(3) <= (congr_cl6_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayF_upd select + congr_cl6_wF_d(4) <= (congr_cl6_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayF_upd select + congr_cl6_wF_d(5) <= (congr_cl6_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 7 +with rel_bixu7_wayF_upd select + congr_cl7_wF_d(0) <= (congr_cl7_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 7 +with rel_bixu7_wayF_upd select + congr_cl7_wF_d(1) <= (congr_cl7_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayF_upd select + congr_cl7_wF_d(2) <= (congr_cl7_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayF_upd select + congr_cl7_wF_d(3) <= (congr_cl7_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayF_upd select + congr_cl7_wF_d(4) <= (congr_cl7_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayF_upd select + congr_cl7_wF_d(5) <= (congr_cl7_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 8 +with rel_bixu8_wayF_upd select + congr_cl8_wF_d(0) <= (congr_cl8_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 8 +with rel_bixu8_wayF_upd select + congr_cl8_wF_d(1) <= (congr_cl8_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayF_upd select + congr_cl8_wF_d(2) <= (congr_cl8_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayF_upd select + congr_cl8_wF_d(3) <= (congr_cl8_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayF_upd select + congr_cl8_wF_d(4) <= (congr_cl8_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayF_upd select + congr_cl8_wF_d(5) <= (congr_cl8_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 9 +with rel_bixu9_wayF_upd select + congr_cl9_wF_d(0) <= (congr_cl9_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 9 +with rel_bixu9_wayF_upd select + congr_cl9_wF_d(1) <= (congr_cl9_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayF_upd select + congr_cl9_wF_d(2) <= (congr_cl9_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayF_upd select + congr_cl9_wF_d(3) <= (congr_cl9_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayF_upd select + congr_cl9_wF_d(4) <= (congr_cl9_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayF_upd select + congr_cl9_wF_d(5) <= (congr_cl9_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 10 +with rel_bixu10_wayF_upd select + congr_cl10_wF_d(0) <= (congr_cl10_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 10 +with rel_bixu10_wayF_upd select + congr_cl10_wF_d(1) <= (congr_cl10_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayF_upd select + congr_cl10_wF_d(2) <= (congr_cl10_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayF_upd select + congr_cl10_wF_d(3) <= (congr_cl10_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayF_upd select + congr_cl10_wF_d(4) <= (congr_cl10_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayF_upd select + congr_cl10_wF_d(5) <= (congr_cl10_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 11 +with rel_bixu11_wayF_upd select + congr_cl11_wF_d(0) <= (congr_cl11_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 11 +with rel_bixu11_wayF_upd select + congr_cl11_wF_d(1) <= (congr_cl11_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayF_upd select + congr_cl11_wF_d(2) <= (congr_cl11_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayF_upd select + congr_cl11_wF_d(3) <= (congr_cl11_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayF_upd select + congr_cl11_wF_d(4) <= (congr_cl11_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayF_upd select + congr_cl11_wF_d(5) <= (congr_cl11_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 12 +with rel_bixu12_wayF_upd select + congr_cl12_wF_d(0) <= (congr_cl12_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 12 +with rel_bixu12_wayF_upd select + congr_cl12_wF_d(1) <= (congr_cl12_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayF_upd select + congr_cl12_wF_d(2) <= (congr_cl12_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayF_upd select + congr_cl12_wF_d(3) <= (congr_cl12_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayF_upd select + congr_cl12_wF_d(4) <= (congr_cl12_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayF_upd select + congr_cl12_wF_d(5) <= (congr_cl12_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 13 +with rel_bixu13_wayF_upd select + congr_cl13_wF_d(0) <= (congr_cl13_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 13 +with rel_bixu13_wayF_upd select + congr_cl13_wF_d(1) <= (congr_cl13_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayF_upd select + congr_cl13_wF_d(2) <= (congr_cl13_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayF_upd select + congr_cl13_wF_d(3) <= (congr_cl13_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayF_upd select + congr_cl13_wF_d(4) <= (congr_cl13_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayF_upd select + congr_cl13_wF_d(5) <= (congr_cl13_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 14 +with rel_bixu14_wayF_upd select + congr_cl14_wF_d(0) <= (congr_cl14_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 14 +with rel_bixu14_wayF_upd select + congr_cl14_wF_d(1) <= (congr_cl14_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayF_upd select + congr_cl14_wF_d(2) <= (congr_cl14_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayF_upd select + congr_cl14_wF_d(3) <= (congr_cl14_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayF_upd select + congr_cl14_wF_d(4) <= (congr_cl14_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayF_upd select + congr_cl14_wF_d(5) <= (congr_cl14_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 15 +with rel_bixu15_wayF_upd select + congr_cl15_wF_d(0) <= (congr_cl15_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 15 +with rel_bixu15_wayF_upd select + congr_cl15_wF_d(1) <= (congr_cl15_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayF_upd select + congr_cl15_wF_d(2) <= (congr_cl15_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayF_upd select + congr_cl15_wF_d(3) <= (congr_cl15_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayF_upd select + congr_cl15_wF_d(4) <= (congr_cl15_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayF_upd select + congr_cl15_wF_d(5) <= (congr_cl15_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 16 +with rel_bixu16_wayF_upd select + congr_cl16_wF_d(0) <= (congr_cl16_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 16 +with rel_bixu16_wayF_upd select + congr_cl16_wF_d(1) <= (congr_cl16_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayF_upd select + congr_cl16_wF_d(2) <= (congr_cl16_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayF_upd select + congr_cl16_wF_d(3) <= (congr_cl16_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayF_upd select + congr_cl16_wF_d(4) <= (congr_cl16_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayF_upd select + congr_cl16_wF_d(5) <= (congr_cl16_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 17 +with rel_bixu17_wayF_upd select + congr_cl17_wF_d(0) <= (congr_cl17_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 17 +with rel_bixu17_wayF_upd select + congr_cl17_wF_d(1) <= (congr_cl17_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayF_upd select + congr_cl17_wF_d(2) <= (congr_cl17_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayF_upd select + congr_cl17_wF_d(3) <= (congr_cl17_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayF_upd select + congr_cl17_wF_d(4) <= (congr_cl17_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayF_upd select + congr_cl17_wF_d(5) <= (congr_cl17_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 18 +with rel_bixu18_wayF_upd select + congr_cl18_wF_d(0) <= (congr_cl18_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 18 +with rel_bixu18_wayF_upd select + congr_cl18_wF_d(1) <= (congr_cl18_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayF_upd select + congr_cl18_wF_d(2) <= (congr_cl18_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayF_upd select + congr_cl18_wF_d(3) <= (congr_cl18_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayF_upd select + congr_cl18_wF_d(4) <= (congr_cl18_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayF_upd select + congr_cl18_wF_d(5) <= (congr_cl18_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 19 +with rel_bixu19_wayF_upd select + congr_cl19_wF_d(0) <= (congr_cl19_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 19 +with rel_bixu19_wayF_upd select + congr_cl19_wF_d(1) <= (congr_cl19_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayF_upd select + congr_cl19_wF_d(2) <= (congr_cl19_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayF_upd select + congr_cl19_wF_d(3) <= (congr_cl19_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayF_upd select + congr_cl19_wF_d(4) <= (congr_cl19_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayF_upd select + congr_cl19_wF_d(5) <= (congr_cl19_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 20 +with rel_bixu20_wayF_upd select + congr_cl20_wF_d(0) <= (congr_cl20_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 20 +with rel_bixu20_wayF_upd select + congr_cl20_wF_d(1) <= (congr_cl20_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayF_upd select + congr_cl20_wF_d(2) <= (congr_cl20_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayF_upd select + congr_cl20_wF_d(3) <= (congr_cl20_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayF_upd select + congr_cl20_wF_d(4) <= (congr_cl20_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayF_upd select + congr_cl20_wF_d(5) <= (congr_cl20_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 21 +with rel_bixu21_wayF_upd select + congr_cl21_wF_d(0) <= (congr_cl21_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 21 +with rel_bixu21_wayF_upd select + congr_cl21_wF_d(1) <= (congr_cl21_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayF_upd select + congr_cl21_wF_d(2) <= (congr_cl21_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayF_upd select + congr_cl21_wF_d(3) <= (congr_cl21_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayF_upd select + congr_cl21_wF_d(4) <= (congr_cl21_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayF_upd select + congr_cl21_wF_d(5) <= (congr_cl21_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 22 +with rel_bixu22_wayF_upd select + congr_cl22_wF_d(0) <= (congr_cl22_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 22 +with rel_bixu22_wayF_upd select + congr_cl22_wF_d(1) <= (congr_cl22_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayF_upd select + congr_cl22_wF_d(2) <= (congr_cl22_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayF_upd select + congr_cl22_wF_d(3) <= (congr_cl22_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayF_upd select + congr_cl22_wF_d(4) <= (congr_cl22_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayF_upd select + congr_cl22_wF_d(5) <= (congr_cl22_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 23 +with rel_bixu23_wayF_upd select + congr_cl23_wF_d(0) <= (congr_cl23_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 23 +with rel_bixu23_wayF_upd select + congr_cl23_wF_d(1) <= (congr_cl23_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayF_upd select + congr_cl23_wF_d(2) <= (congr_cl23_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayF_upd select + congr_cl23_wF_d(3) <= (congr_cl23_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayF_upd select + congr_cl23_wF_d(4) <= (congr_cl23_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayF_upd select + congr_cl23_wF_d(5) <= (congr_cl23_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 24 +with rel_bixu24_wayF_upd select + congr_cl24_wF_d(0) <= (congr_cl24_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 24 +with rel_bixu24_wayF_upd select + congr_cl24_wF_d(1) <= (congr_cl24_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayF_upd select + congr_cl24_wF_d(2) <= (congr_cl24_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayF_upd select + congr_cl24_wF_d(3) <= (congr_cl24_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayF_upd select + congr_cl24_wF_d(4) <= (congr_cl24_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayF_upd select + congr_cl24_wF_d(5) <= (congr_cl24_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 25 +with rel_bixu25_wayF_upd select + congr_cl25_wF_d(0) <= (congr_cl25_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 25 +with rel_bixu25_wayF_upd select + congr_cl25_wF_d(1) <= (congr_cl25_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayF_upd select + congr_cl25_wF_d(2) <= (congr_cl25_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayF_upd select + congr_cl25_wF_d(3) <= (congr_cl25_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayF_upd select + congr_cl25_wF_d(4) <= (congr_cl25_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayF_upd select + congr_cl25_wF_d(5) <= (congr_cl25_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 26 +with rel_bixu26_wayF_upd select + congr_cl26_wF_d(0) <= (congr_cl26_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 26 +with rel_bixu26_wayF_upd select + congr_cl26_wF_d(1) <= (congr_cl26_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayF_upd select + congr_cl26_wF_d(2) <= (congr_cl26_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayF_upd select + congr_cl26_wF_d(3) <= (congr_cl26_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayF_upd select + congr_cl26_wF_d(4) <= (congr_cl26_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayF_upd select + congr_cl26_wF_d(5) <= (congr_cl26_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 27 +with rel_bixu27_wayF_upd select + congr_cl27_wF_d(0) <= (congr_cl27_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 27 +with rel_bixu27_wayF_upd select + congr_cl27_wF_d(1) <= (congr_cl27_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayF_upd select + congr_cl27_wF_d(2) <= (congr_cl27_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayF_upd select + congr_cl27_wF_d(3) <= (congr_cl27_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayF_upd select + congr_cl27_wF_d(4) <= (congr_cl27_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayF_upd select + congr_cl27_wF_d(5) <= (congr_cl27_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 28 +with rel_bixu28_wayF_upd select + congr_cl28_wF_d(0) <= (congr_cl28_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 28 +with rel_bixu28_wayF_upd select + congr_cl28_wF_d(1) <= (congr_cl28_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayF_upd select + congr_cl28_wF_d(2) <= (congr_cl28_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayF_upd select + congr_cl28_wF_d(3) <= (congr_cl28_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayF_upd select + congr_cl28_wF_d(4) <= (congr_cl28_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayF_upd select + congr_cl28_wF_d(5) <= (congr_cl28_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 29 +with rel_bixu29_wayF_upd select + congr_cl29_wF_d(0) <= (congr_cl29_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 29 +with rel_bixu29_wayF_upd select + congr_cl29_wF_d(1) <= (congr_cl29_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayF_upd select + congr_cl29_wF_d(2) <= (congr_cl29_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayF_upd select + congr_cl29_wF_d(3) <= (congr_cl29_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayF_upd select + congr_cl29_wF_d(4) <= (congr_cl29_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayF_upd select + congr_cl29_wF_d(5) <= (congr_cl29_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 30 +with rel_bixu30_wayF_upd select + congr_cl30_wF_d(0) <= (congr_cl30_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 30 +with rel_bixu30_wayF_upd select + congr_cl30_wF_d(1) <= (congr_cl30_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayF_upd select + congr_cl30_wF_d(2) <= (congr_cl30_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayF_upd select + congr_cl30_wF_d(3) <= (congr_cl30_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayF_upd select + congr_cl30_wF_d(4) <= (congr_cl30_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayF_upd select + congr_cl30_wF_d(5) <= (congr_cl30_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 31 +with rel_bixu31_wayF_upd select + congr_cl31_wF_d(0) <= (congr_cl31_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 31 +with rel_bixu31_wayF_upd select + congr_cl31_wF_d(1) <= (congr_cl31_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayF_upd select + congr_cl31_wF_d(2) <= (congr_cl31_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayF_upd select + congr_cl31_wF_d(3) <= (congr_cl31_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayF_upd select + congr_cl31_wF_d(4) <= (congr_cl31_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayF_upd select + congr_cl31_wF_d(5) <= (congr_cl31_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 32 +with rel_bixu32_wayF_upd select + congr_cl32_wF_d(0) <= (congr_cl32_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 32 +with rel_bixu32_wayF_upd select + congr_cl32_wF_d(1) <= (congr_cl32_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 32 +with rel_bixu32_wayF_upd select + congr_cl32_wF_d(2) <= (congr_cl32_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 32 +with rel_bixu32_wayF_upd select + congr_cl32_wF_d(3) <= (congr_cl32_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 32 +with rel_bixu32_wayF_upd select + congr_cl32_wF_d(4) <= (congr_cl32_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 32 +with rel_bixu32_wayF_upd select + congr_cl32_wF_d(5) <= (congr_cl32_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 33 +with rel_bixu33_wayF_upd select + congr_cl33_wF_d(0) <= (congr_cl33_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 33 +with rel_bixu33_wayF_upd select + congr_cl33_wF_d(1) <= (congr_cl33_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 33 +with rel_bixu33_wayF_upd select + congr_cl33_wF_d(2) <= (congr_cl33_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 33 +with rel_bixu33_wayF_upd select + congr_cl33_wF_d(3) <= (congr_cl33_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 33 +with rel_bixu33_wayF_upd select + congr_cl33_wF_d(4) <= (congr_cl33_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 33 +with rel_bixu33_wayF_upd select + congr_cl33_wF_d(5) <= (congr_cl33_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 34 +with rel_bixu34_wayF_upd select + congr_cl34_wF_d(0) <= (congr_cl34_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 34 +with rel_bixu34_wayF_upd select + congr_cl34_wF_d(1) <= (congr_cl34_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 34 +with rel_bixu34_wayF_upd select + congr_cl34_wF_d(2) <= (congr_cl34_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 34 +with rel_bixu34_wayF_upd select + congr_cl34_wF_d(3) <= (congr_cl34_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 34 +with rel_bixu34_wayF_upd select + congr_cl34_wF_d(4) <= (congr_cl34_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 34 +with rel_bixu34_wayF_upd select + congr_cl34_wF_d(5) <= (congr_cl34_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 35 +with rel_bixu35_wayF_upd select + congr_cl35_wF_d(0) <= (congr_cl35_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 35 +with rel_bixu35_wayF_upd select + congr_cl35_wF_d(1) <= (congr_cl35_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 35 +with rel_bixu35_wayF_upd select + congr_cl35_wF_d(2) <= (congr_cl35_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 35 +with rel_bixu35_wayF_upd select + congr_cl35_wF_d(3) <= (congr_cl35_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 35 +with rel_bixu35_wayF_upd select + congr_cl35_wF_d(4) <= (congr_cl35_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 35 +with rel_bixu35_wayF_upd select + congr_cl35_wF_d(5) <= (congr_cl35_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 36 +with rel_bixu36_wayF_upd select + congr_cl36_wF_d(0) <= (congr_cl36_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 36 +with rel_bixu36_wayF_upd select + congr_cl36_wF_d(1) <= (congr_cl36_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 36 +with rel_bixu36_wayF_upd select + congr_cl36_wF_d(2) <= (congr_cl36_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 36 +with rel_bixu36_wayF_upd select + congr_cl36_wF_d(3) <= (congr_cl36_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 36 +with rel_bixu36_wayF_upd select + congr_cl36_wF_d(4) <= (congr_cl36_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 36 +with rel_bixu36_wayF_upd select + congr_cl36_wF_d(5) <= (congr_cl36_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 37 +with rel_bixu37_wayF_upd select + congr_cl37_wF_d(0) <= (congr_cl37_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 37 +with rel_bixu37_wayF_upd select + congr_cl37_wF_d(1) <= (congr_cl37_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 37 +with rel_bixu37_wayF_upd select + congr_cl37_wF_d(2) <= (congr_cl37_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 37 +with rel_bixu37_wayF_upd select + congr_cl37_wF_d(3) <= (congr_cl37_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 37 +with rel_bixu37_wayF_upd select + congr_cl37_wF_d(4) <= (congr_cl37_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 37 +with rel_bixu37_wayF_upd select + congr_cl37_wF_d(5) <= (congr_cl37_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 38 +with rel_bixu38_wayF_upd select + congr_cl38_wF_d(0) <= (congr_cl38_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 38 +with rel_bixu38_wayF_upd select + congr_cl38_wF_d(1) <= (congr_cl38_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 38 +with rel_bixu38_wayF_upd select + congr_cl38_wF_d(2) <= (congr_cl38_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 38 +with rel_bixu38_wayF_upd select + congr_cl38_wF_d(3) <= (congr_cl38_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 38 +with rel_bixu38_wayF_upd select + congr_cl38_wF_d(4) <= (congr_cl38_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 38 +with rel_bixu38_wayF_upd select + congr_cl38_wF_d(5) <= (congr_cl38_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 39 +with rel_bixu39_wayF_upd select + congr_cl39_wF_d(0) <= (congr_cl39_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 39 +with rel_bixu39_wayF_upd select + congr_cl39_wF_d(1) <= (congr_cl39_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 39 +with rel_bixu39_wayF_upd select + congr_cl39_wF_d(2) <= (congr_cl39_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 39 +with rel_bixu39_wayF_upd select + congr_cl39_wF_d(3) <= (congr_cl39_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 39 +with rel_bixu39_wayF_upd select + congr_cl39_wF_d(4) <= (congr_cl39_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 39 +with rel_bixu39_wayF_upd select + congr_cl39_wF_d(5) <= (congr_cl39_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 40 +with rel_bixu40_wayF_upd select + congr_cl40_wF_d(0) <= (congr_cl40_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 40 +with rel_bixu40_wayF_upd select + congr_cl40_wF_d(1) <= (congr_cl40_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 40 +with rel_bixu40_wayF_upd select + congr_cl40_wF_d(2) <= (congr_cl40_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 40 +with rel_bixu40_wayF_upd select + congr_cl40_wF_d(3) <= (congr_cl40_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 40 +with rel_bixu40_wayF_upd select + congr_cl40_wF_d(4) <= (congr_cl40_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 40 +with rel_bixu40_wayF_upd select + congr_cl40_wF_d(5) <= (congr_cl40_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 41 +with rel_bixu41_wayF_upd select + congr_cl41_wF_d(0) <= (congr_cl41_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 41 +with rel_bixu41_wayF_upd select + congr_cl41_wF_d(1) <= (congr_cl41_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 41 +with rel_bixu41_wayF_upd select + congr_cl41_wF_d(2) <= (congr_cl41_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 41 +with rel_bixu41_wayF_upd select + congr_cl41_wF_d(3) <= (congr_cl41_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 41 +with rel_bixu41_wayF_upd select + congr_cl41_wF_d(4) <= (congr_cl41_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 41 +with rel_bixu41_wayF_upd select + congr_cl41_wF_d(5) <= (congr_cl41_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 42 +with rel_bixu42_wayF_upd select + congr_cl42_wF_d(0) <= (congr_cl42_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 42 +with rel_bixu42_wayF_upd select + congr_cl42_wF_d(1) <= (congr_cl42_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 42 +with rel_bixu42_wayF_upd select + congr_cl42_wF_d(2) <= (congr_cl42_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 42 +with rel_bixu42_wayF_upd select + congr_cl42_wF_d(3) <= (congr_cl42_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 42 +with rel_bixu42_wayF_upd select + congr_cl42_wF_d(4) <= (congr_cl42_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 42 +with rel_bixu42_wayF_upd select + congr_cl42_wF_d(5) <= (congr_cl42_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 43 +with rel_bixu43_wayF_upd select + congr_cl43_wF_d(0) <= (congr_cl43_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 43 +with rel_bixu43_wayF_upd select + congr_cl43_wF_d(1) <= (congr_cl43_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 43 +with rel_bixu43_wayF_upd select + congr_cl43_wF_d(2) <= (congr_cl43_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 43 +with rel_bixu43_wayF_upd select + congr_cl43_wF_d(3) <= (congr_cl43_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 43 +with rel_bixu43_wayF_upd select + congr_cl43_wF_d(4) <= (congr_cl43_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 43 +with rel_bixu43_wayF_upd select + congr_cl43_wF_d(5) <= (congr_cl43_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 44 +with rel_bixu44_wayF_upd select + congr_cl44_wF_d(0) <= (congr_cl44_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 44 +with rel_bixu44_wayF_upd select + congr_cl44_wF_d(1) <= (congr_cl44_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 44 +with rel_bixu44_wayF_upd select + congr_cl44_wF_d(2) <= (congr_cl44_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 44 +with rel_bixu44_wayF_upd select + congr_cl44_wF_d(3) <= (congr_cl44_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 44 +with rel_bixu44_wayF_upd select + congr_cl44_wF_d(4) <= (congr_cl44_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 44 +with rel_bixu44_wayF_upd select + congr_cl44_wF_d(5) <= (congr_cl44_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 45 +with rel_bixu45_wayF_upd select + congr_cl45_wF_d(0) <= (congr_cl45_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 45 +with rel_bixu45_wayF_upd select + congr_cl45_wF_d(1) <= (congr_cl45_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 45 +with rel_bixu45_wayF_upd select + congr_cl45_wF_d(2) <= (congr_cl45_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 45 +with rel_bixu45_wayF_upd select + congr_cl45_wF_d(3) <= (congr_cl45_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 45 +with rel_bixu45_wayF_upd select + congr_cl45_wF_d(4) <= (congr_cl45_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 45 +with rel_bixu45_wayF_upd select + congr_cl45_wF_d(5) <= (congr_cl45_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 46 +with rel_bixu46_wayF_upd select + congr_cl46_wF_d(0) <= (congr_cl46_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 46 +with rel_bixu46_wayF_upd select + congr_cl46_wF_d(1) <= (congr_cl46_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 46 +with rel_bixu46_wayF_upd select + congr_cl46_wF_d(2) <= (congr_cl46_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 46 +with rel_bixu46_wayF_upd select + congr_cl46_wF_d(3) <= (congr_cl46_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 46 +with rel_bixu46_wayF_upd select + congr_cl46_wF_d(4) <= (congr_cl46_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 46 +with rel_bixu46_wayF_upd select + congr_cl46_wF_d(5) <= (congr_cl46_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 47 +with rel_bixu47_wayF_upd select + congr_cl47_wF_d(0) <= (congr_cl47_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 47 +with rel_bixu47_wayF_upd select + congr_cl47_wF_d(1) <= (congr_cl47_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 47 +with rel_bixu47_wayF_upd select + congr_cl47_wF_d(2) <= (congr_cl47_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 47 +with rel_bixu47_wayF_upd select + congr_cl47_wF_d(3) <= (congr_cl47_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 47 +with rel_bixu47_wayF_upd select + congr_cl47_wF_d(4) <= (congr_cl47_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 47 +with rel_bixu47_wayF_upd select + congr_cl47_wF_d(5) <= (congr_cl47_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 48 +with rel_bixu48_wayF_upd select + congr_cl48_wF_d(0) <= (congr_cl48_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 48 +with rel_bixu48_wayF_upd select + congr_cl48_wF_d(1) <= (congr_cl48_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 48 +with rel_bixu48_wayF_upd select + congr_cl48_wF_d(2) <= (congr_cl48_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 48 +with rel_bixu48_wayF_upd select + congr_cl48_wF_d(3) <= (congr_cl48_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 48 +with rel_bixu48_wayF_upd select + congr_cl48_wF_d(4) <= (congr_cl48_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 48 +with rel_bixu48_wayF_upd select + congr_cl48_wF_d(5) <= (congr_cl48_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 49 +with rel_bixu49_wayF_upd select + congr_cl49_wF_d(0) <= (congr_cl49_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 49 +with rel_bixu49_wayF_upd select + congr_cl49_wF_d(1) <= (congr_cl49_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 49 +with rel_bixu49_wayF_upd select + congr_cl49_wF_d(2) <= (congr_cl49_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 49 +with rel_bixu49_wayF_upd select + congr_cl49_wF_d(3) <= (congr_cl49_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 49 +with rel_bixu49_wayF_upd select + congr_cl49_wF_d(4) <= (congr_cl49_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 49 +with rel_bixu49_wayF_upd select + congr_cl49_wF_d(5) <= (congr_cl49_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 50 +with rel_bixu50_wayF_upd select + congr_cl50_wF_d(0) <= (congr_cl50_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 50 +with rel_bixu50_wayF_upd select + congr_cl50_wF_d(1) <= (congr_cl50_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 50 +with rel_bixu50_wayF_upd select + congr_cl50_wF_d(2) <= (congr_cl50_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 50 +with rel_bixu50_wayF_upd select + congr_cl50_wF_d(3) <= (congr_cl50_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 50 +with rel_bixu50_wayF_upd select + congr_cl50_wF_d(4) <= (congr_cl50_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 50 +with rel_bixu50_wayF_upd select + congr_cl50_wF_d(5) <= (congr_cl50_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 51 +with rel_bixu51_wayF_upd select + congr_cl51_wF_d(0) <= (congr_cl51_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 51 +with rel_bixu51_wayF_upd select + congr_cl51_wF_d(1) <= (congr_cl51_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 51 +with rel_bixu51_wayF_upd select + congr_cl51_wF_d(2) <= (congr_cl51_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 51 +with rel_bixu51_wayF_upd select + congr_cl51_wF_d(3) <= (congr_cl51_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 51 +with rel_bixu51_wayF_upd select + congr_cl51_wF_d(4) <= (congr_cl51_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 51 +with rel_bixu51_wayF_upd select + congr_cl51_wF_d(5) <= (congr_cl51_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 52 +with rel_bixu52_wayF_upd select + congr_cl52_wF_d(0) <= (congr_cl52_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 52 +with rel_bixu52_wayF_upd select + congr_cl52_wF_d(1) <= (congr_cl52_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 52 +with rel_bixu52_wayF_upd select + congr_cl52_wF_d(2) <= (congr_cl52_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 52 +with rel_bixu52_wayF_upd select + congr_cl52_wF_d(3) <= (congr_cl52_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 52 +with rel_bixu52_wayF_upd select + congr_cl52_wF_d(4) <= (congr_cl52_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 52 +with rel_bixu52_wayF_upd select + congr_cl52_wF_d(5) <= (congr_cl52_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 53 +with rel_bixu53_wayF_upd select + congr_cl53_wF_d(0) <= (congr_cl53_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 53 +with rel_bixu53_wayF_upd select + congr_cl53_wF_d(1) <= (congr_cl53_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 53 +with rel_bixu53_wayF_upd select + congr_cl53_wF_d(2) <= (congr_cl53_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 53 +with rel_bixu53_wayF_upd select + congr_cl53_wF_d(3) <= (congr_cl53_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 53 +with rel_bixu53_wayF_upd select + congr_cl53_wF_d(4) <= (congr_cl53_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 53 +with rel_bixu53_wayF_upd select + congr_cl53_wF_d(5) <= (congr_cl53_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 54 +with rel_bixu54_wayF_upd select + congr_cl54_wF_d(0) <= (congr_cl54_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 54 +with rel_bixu54_wayF_upd select + congr_cl54_wF_d(1) <= (congr_cl54_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 54 +with rel_bixu54_wayF_upd select + congr_cl54_wF_d(2) <= (congr_cl54_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 54 +with rel_bixu54_wayF_upd select + congr_cl54_wF_d(3) <= (congr_cl54_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 54 +with rel_bixu54_wayF_upd select + congr_cl54_wF_d(4) <= (congr_cl54_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 54 +with rel_bixu54_wayF_upd select + congr_cl54_wF_d(5) <= (congr_cl54_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 55 +with rel_bixu55_wayF_upd select + congr_cl55_wF_d(0) <= (congr_cl55_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 55 +with rel_bixu55_wayF_upd select + congr_cl55_wF_d(1) <= (congr_cl55_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 55 +with rel_bixu55_wayF_upd select + congr_cl55_wF_d(2) <= (congr_cl55_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 55 +with rel_bixu55_wayF_upd select + congr_cl55_wF_d(3) <= (congr_cl55_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 55 +with rel_bixu55_wayF_upd select + congr_cl55_wF_d(4) <= (congr_cl55_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 55 +with rel_bixu55_wayF_upd select + congr_cl55_wF_d(5) <= (congr_cl55_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 56 +with rel_bixu56_wayF_upd select + congr_cl56_wF_d(0) <= (congr_cl56_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 56 +with rel_bixu56_wayF_upd select + congr_cl56_wF_d(1) <= (congr_cl56_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 56 +with rel_bixu56_wayF_upd select + congr_cl56_wF_d(2) <= (congr_cl56_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 56 +with rel_bixu56_wayF_upd select + congr_cl56_wF_d(3) <= (congr_cl56_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 56 +with rel_bixu56_wayF_upd select + congr_cl56_wF_d(4) <= (congr_cl56_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 56 +with rel_bixu56_wayF_upd select + congr_cl56_wF_d(5) <= (congr_cl56_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 57 +with rel_bixu57_wayF_upd select + congr_cl57_wF_d(0) <= (congr_cl57_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 57 +with rel_bixu57_wayF_upd select + congr_cl57_wF_d(1) <= (congr_cl57_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 57 +with rel_bixu57_wayF_upd select + congr_cl57_wF_d(2) <= (congr_cl57_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 57 +with rel_bixu57_wayF_upd select + congr_cl57_wF_d(3) <= (congr_cl57_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 57 +with rel_bixu57_wayF_upd select + congr_cl57_wF_d(4) <= (congr_cl57_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 57 +with rel_bixu57_wayF_upd select + congr_cl57_wF_d(5) <= (congr_cl57_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 58 +with rel_bixu58_wayF_upd select + congr_cl58_wF_d(0) <= (congr_cl58_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 58 +with rel_bixu58_wayF_upd select + congr_cl58_wF_d(1) <= (congr_cl58_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 58 +with rel_bixu58_wayF_upd select + congr_cl58_wF_d(2) <= (congr_cl58_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 58 +with rel_bixu58_wayF_upd select + congr_cl58_wF_d(3) <= (congr_cl58_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 58 +with rel_bixu58_wayF_upd select + congr_cl58_wF_d(4) <= (congr_cl58_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 58 +with rel_bixu58_wayF_upd select + congr_cl58_wF_d(5) <= (congr_cl58_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 59 +with rel_bixu59_wayF_upd select + congr_cl59_wF_d(0) <= (congr_cl59_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 59 +with rel_bixu59_wayF_upd select + congr_cl59_wF_d(1) <= (congr_cl59_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 59 +with rel_bixu59_wayF_upd select + congr_cl59_wF_d(2) <= (congr_cl59_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 59 +with rel_bixu59_wayF_upd select + congr_cl59_wF_d(3) <= (congr_cl59_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 59 +with rel_bixu59_wayF_upd select + congr_cl59_wF_d(4) <= (congr_cl59_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 59 +with rel_bixu59_wayF_upd select + congr_cl59_wF_d(5) <= (congr_cl59_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 60 +with rel_bixu60_wayF_upd select + congr_cl60_wF_d(0) <= (congr_cl60_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 60 +with rel_bixu60_wayF_upd select + congr_cl60_wF_d(1) <= (congr_cl60_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 60 +with rel_bixu60_wayF_upd select + congr_cl60_wF_d(2) <= (congr_cl60_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 60 +with rel_bixu60_wayF_upd select + congr_cl60_wF_d(3) <= (congr_cl60_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 60 +with rel_bixu60_wayF_upd select + congr_cl60_wF_d(4) <= (congr_cl60_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 60 +with rel_bixu60_wayF_upd select + congr_cl60_wF_d(5) <= (congr_cl60_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 61 +with rel_bixu61_wayF_upd select + congr_cl61_wF_d(0) <= (congr_cl61_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 61 +with rel_bixu61_wayF_upd select + congr_cl61_wF_d(1) <= (congr_cl61_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 61 +with rel_bixu61_wayF_upd select + congr_cl61_wF_d(2) <= (congr_cl61_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 61 +with rel_bixu61_wayF_upd select + congr_cl61_wF_d(3) <= (congr_cl61_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 61 +with rel_bixu61_wayF_upd select + congr_cl61_wF_d(4) <= (congr_cl61_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 61 +with rel_bixu61_wayF_upd select + congr_cl61_wF_d(5) <= (congr_cl61_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 62 +with rel_bixu62_wayF_upd select + congr_cl62_wF_d(0) <= (congr_cl62_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 62 +with rel_bixu62_wayF_upd select + congr_cl62_wF_d(1) <= (congr_cl62_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 62 +with rel_bixu62_wayF_upd select + congr_cl62_wF_d(2) <= (congr_cl62_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 62 +with rel_bixu62_wayF_upd select + congr_cl62_wF_d(3) <= (congr_cl62_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 62 +with rel_bixu62_wayF_upd select + congr_cl62_wF_d(4) <= (congr_cl62_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 62 +with rel_bixu62_wayF_upd select + congr_cl62_wF_d(5) <= (congr_cl62_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayF Valid Bit Update for Congruence Class 63 +with rel_bixu63_wayF_upd select + congr_cl63_wF_d(0) <= (congr_cl63_wF_q(0) and not dci_inval_all_q) when "00", + (flush_wayF_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayF_data2_q(0) and not dci_inval_all_q) when others; +-- WayF Lock Bit Update for Congruence Class 63 +with rel_bixu63_wayF_upd select + congr_cl63_wF_d(1) <= (congr_cl63_wF_q(1) and not lock_finval) when "00", + (flush_wayF_data2_q(1) and not lock_finval) when "01", + (reload_wayF_data2_q(1) and not lock_finval) when others; +-- WayF Thread 0 Watch Bit Update for Congruence Class 63 +with rel_bixu63_wayF_upd select + congr_cl63_wF_d(2) <= (congr_cl63_wF_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayF_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayF Thread 1 Watch Bit Update for Congruence Class 63 +with rel_bixu63_wayF_upd select + congr_cl63_wF_d(3) <= (congr_cl63_wF_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayF_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayF Thread 2 Watch Bit Update for Congruence Class 63 +with rel_bixu63_wayF_upd select + congr_cl63_wF_d(4) <= (congr_cl63_wF_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayF_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayF Thread 3 Watch Bit Update for Congruence Class 63 +with rel_bixu63_wayF_upd select + congr_cl63_wF_d(5) <= (congr_cl63_wF_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayF_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Write Select for WayG +-- WayG Valid Bit Update for Congruence Class 0 +with rel_bixu0_wayG_upd select + congr_cl0_wG_d(0) <= (congr_cl0_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 0 +with rel_bixu0_wayG_upd select + congr_cl0_wG_d(1) <= (congr_cl0_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayG_upd select + congr_cl0_wG_d(2) <= (congr_cl0_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayG_upd select + congr_cl0_wG_d(3) <= (congr_cl0_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayG_upd select + congr_cl0_wG_d(4) <= (congr_cl0_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayG_upd select + congr_cl0_wG_d(5) <= (congr_cl0_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 1 +with rel_bixu1_wayG_upd select + congr_cl1_wG_d(0) <= (congr_cl1_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 1 +with rel_bixu1_wayG_upd select + congr_cl1_wG_d(1) <= (congr_cl1_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayG_upd select + congr_cl1_wG_d(2) <= (congr_cl1_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayG_upd select + congr_cl1_wG_d(3) <= (congr_cl1_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayG_upd select + congr_cl1_wG_d(4) <= (congr_cl1_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayG_upd select + congr_cl1_wG_d(5) <= (congr_cl1_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 2 +with rel_bixu2_wayG_upd select + congr_cl2_wG_d(0) <= (congr_cl2_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 2 +with rel_bixu2_wayG_upd select + congr_cl2_wG_d(1) <= (congr_cl2_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayG_upd select + congr_cl2_wG_d(2) <= (congr_cl2_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayG_upd select + congr_cl2_wG_d(3) <= (congr_cl2_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayG_upd select + congr_cl2_wG_d(4) <= (congr_cl2_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayG_upd select + congr_cl2_wG_d(5) <= (congr_cl2_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 3 +with rel_bixu3_wayG_upd select + congr_cl3_wG_d(0) <= (congr_cl3_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 3 +with rel_bixu3_wayG_upd select + congr_cl3_wG_d(1) <= (congr_cl3_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayG_upd select + congr_cl3_wG_d(2) <= (congr_cl3_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayG_upd select + congr_cl3_wG_d(3) <= (congr_cl3_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayG_upd select + congr_cl3_wG_d(4) <= (congr_cl3_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayG_upd select + congr_cl3_wG_d(5) <= (congr_cl3_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 4 +with rel_bixu4_wayG_upd select + congr_cl4_wG_d(0) <= (congr_cl4_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 4 +with rel_bixu4_wayG_upd select + congr_cl4_wG_d(1) <= (congr_cl4_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayG_upd select + congr_cl4_wG_d(2) <= (congr_cl4_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayG_upd select + congr_cl4_wG_d(3) <= (congr_cl4_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayG_upd select + congr_cl4_wG_d(4) <= (congr_cl4_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayG_upd select + congr_cl4_wG_d(5) <= (congr_cl4_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 5 +with rel_bixu5_wayG_upd select + congr_cl5_wG_d(0) <= (congr_cl5_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 5 +with rel_bixu5_wayG_upd select + congr_cl5_wG_d(1) <= (congr_cl5_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayG_upd select + congr_cl5_wG_d(2) <= (congr_cl5_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayG_upd select + congr_cl5_wG_d(3) <= (congr_cl5_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayG_upd select + congr_cl5_wG_d(4) <= (congr_cl5_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayG_upd select + congr_cl5_wG_d(5) <= (congr_cl5_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 6 +with rel_bixu6_wayG_upd select + congr_cl6_wG_d(0) <= (congr_cl6_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 6 +with rel_bixu6_wayG_upd select + congr_cl6_wG_d(1) <= (congr_cl6_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayG_upd select + congr_cl6_wG_d(2) <= (congr_cl6_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayG_upd select + congr_cl6_wG_d(3) <= (congr_cl6_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayG_upd select + congr_cl6_wG_d(4) <= (congr_cl6_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayG_upd select + congr_cl6_wG_d(5) <= (congr_cl6_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 7 +with rel_bixu7_wayG_upd select + congr_cl7_wG_d(0) <= (congr_cl7_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 7 +with rel_bixu7_wayG_upd select + congr_cl7_wG_d(1) <= (congr_cl7_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayG_upd select + congr_cl7_wG_d(2) <= (congr_cl7_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayG_upd select + congr_cl7_wG_d(3) <= (congr_cl7_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayG_upd select + congr_cl7_wG_d(4) <= (congr_cl7_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayG_upd select + congr_cl7_wG_d(5) <= (congr_cl7_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 8 +with rel_bixu8_wayG_upd select + congr_cl8_wG_d(0) <= (congr_cl8_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 8 +with rel_bixu8_wayG_upd select + congr_cl8_wG_d(1) <= (congr_cl8_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayG_upd select + congr_cl8_wG_d(2) <= (congr_cl8_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayG_upd select + congr_cl8_wG_d(3) <= (congr_cl8_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayG_upd select + congr_cl8_wG_d(4) <= (congr_cl8_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayG_upd select + congr_cl8_wG_d(5) <= (congr_cl8_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 9 +with rel_bixu9_wayG_upd select + congr_cl9_wG_d(0) <= (congr_cl9_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 9 +with rel_bixu9_wayG_upd select + congr_cl9_wG_d(1) <= (congr_cl9_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayG_upd select + congr_cl9_wG_d(2) <= (congr_cl9_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayG_upd select + congr_cl9_wG_d(3) <= (congr_cl9_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayG_upd select + congr_cl9_wG_d(4) <= (congr_cl9_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayG_upd select + congr_cl9_wG_d(5) <= (congr_cl9_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 10 +with rel_bixu10_wayG_upd select + congr_cl10_wG_d(0) <= (congr_cl10_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 10 +with rel_bixu10_wayG_upd select + congr_cl10_wG_d(1) <= (congr_cl10_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayG_upd select + congr_cl10_wG_d(2) <= (congr_cl10_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayG_upd select + congr_cl10_wG_d(3) <= (congr_cl10_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayG_upd select + congr_cl10_wG_d(4) <= (congr_cl10_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayG_upd select + congr_cl10_wG_d(5) <= (congr_cl10_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 11 +with rel_bixu11_wayG_upd select + congr_cl11_wG_d(0) <= (congr_cl11_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 11 +with rel_bixu11_wayG_upd select + congr_cl11_wG_d(1) <= (congr_cl11_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayG_upd select + congr_cl11_wG_d(2) <= (congr_cl11_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayG_upd select + congr_cl11_wG_d(3) <= (congr_cl11_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayG_upd select + congr_cl11_wG_d(4) <= (congr_cl11_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayG_upd select + congr_cl11_wG_d(5) <= (congr_cl11_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 12 +with rel_bixu12_wayG_upd select + congr_cl12_wG_d(0) <= (congr_cl12_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 12 +with rel_bixu12_wayG_upd select + congr_cl12_wG_d(1) <= (congr_cl12_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayG_upd select + congr_cl12_wG_d(2) <= (congr_cl12_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayG_upd select + congr_cl12_wG_d(3) <= (congr_cl12_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayG_upd select + congr_cl12_wG_d(4) <= (congr_cl12_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayG_upd select + congr_cl12_wG_d(5) <= (congr_cl12_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 13 +with rel_bixu13_wayG_upd select + congr_cl13_wG_d(0) <= (congr_cl13_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 13 +with rel_bixu13_wayG_upd select + congr_cl13_wG_d(1) <= (congr_cl13_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayG_upd select + congr_cl13_wG_d(2) <= (congr_cl13_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayG_upd select + congr_cl13_wG_d(3) <= (congr_cl13_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayG_upd select + congr_cl13_wG_d(4) <= (congr_cl13_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayG_upd select + congr_cl13_wG_d(5) <= (congr_cl13_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 14 +with rel_bixu14_wayG_upd select + congr_cl14_wG_d(0) <= (congr_cl14_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 14 +with rel_bixu14_wayG_upd select + congr_cl14_wG_d(1) <= (congr_cl14_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayG_upd select + congr_cl14_wG_d(2) <= (congr_cl14_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayG_upd select + congr_cl14_wG_d(3) <= (congr_cl14_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayG_upd select + congr_cl14_wG_d(4) <= (congr_cl14_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayG_upd select + congr_cl14_wG_d(5) <= (congr_cl14_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 15 +with rel_bixu15_wayG_upd select + congr_cl15_wG_d(0) <= (congr_cl15_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 15 +with rel_bixu15_wayG_upd select + congr_cl15_wG_d(1) <= (congr_cl15_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayG_upd select + congr_cl15_wG_d(2) <= (congr_cl15_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayG_upd select + congr_cl15_wG_d(3) <= (congr_cl15_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayG_upd select + congr_cl15_wG_d(4) <= (congr_cl15_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayG_upd select + congr_cl15_wG_d(5) <= (congr_cl15_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 16 +with rel_bixu16_wayG_upd select + congr_cl16_wG_d(0) <= (congr_cl16_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 16 +with rel_bixu16_wayG_upd select + congr_cl16_wG_d(1) <= (congr_cl16_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayG_upd select + congr_cl16_wG_d(2) <= (congr_cl16_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayG_upd select + congr_cl16_wG_d(3) <= (congr_cl16_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayG_upd select + congr_cl16_wG_d(4) <= (congr_cl16_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayG_upd select + congr_cl16_wG_d(5) <= (congr_cl16_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 17 +with rel_bixu17_wayG_upd select + congr_cl17_wG_d(0) <= (congr_cl17_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 17 +with rel_bixu17_wayG_upd select + congr_cl17_wG_d(1) <= (congr_cl17_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayG_upd select + congr_cl17_wG_d(2) <= (congr_cl17_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayG_upd select + congr_cl17_wG_d(3) <= (congr_cl17_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayG_upd select + congr_cl17_wG_d(4) <= (congr_cl17_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayG_upd select + congr_cl17_wG_d(5) <= (congr_cl17_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 18 +with rel_bixu18_wayG_upd select + congr_cl18_wG_d(0) <= (congr_cl18_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 18 +with rel_bixu18_wayG_upd select + congr_cl18_wG_d(1) <= (congr_cl18_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayG_upd select + congr_cl18_wG_d(2) <= (congr_cl18_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayG_upd select + congr_cl18_wG_d(3) <= (congr_cl18_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayG_upd select + congr_cl18_wG_d(4) <= (congr_cl18_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayG_upd select + congr_cl18_wG_d(5) <= (congr_cl18_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 19 +with rel_bixu19_wayG_upd select + congr_cl19_wG_d(0) <= (congr_cl19_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 19 +with rel_bixu19_wayG_upd select + congr_cl19_wG_d(1) <= (congr_cl19_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayG_upd select + congr_cl19_wG_d(2) <= (congr_cl19_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayG_upd select + congr_cl19_wG_d(3) <= (congr_cl19_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayG_upd select + congr_cl19_wG_d(4) <= (congr_cl19_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayG_upd select + congr_cl19_wG_d(5) <= (congr_cl19_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 20 +with rel_bixu20_wayG_upd select + congr_cl20_wG_d(0) <= (congr_cl20_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 20 +with rel_bixu20_wayG_upd select + congr_cl20_wG_d(1) <= (congr_cl20_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayG_upd select + congr_cl20_wG_d(2) <= (congr_cl20_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayG_upd select + congr_cl20_wG_d(3) <= (congr_cl20_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayG_upd select + congr_cl20_wG_d(4) <= (congr_cl20_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayG_upd select + congr_cl20_wG_d(5) <= (congr_cl20_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 21 +with rel_bixu21_wayG_upd select + congr_cl21_wG_d(0) <= (congr_cl21_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 21 +with rel_bixu21_wayG_upd select + congr_cl21_wG_d(1) <= (congr_cl21_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayG_upd select + congr_cl21_wG_d(2) <= (congr_cl21_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayG_upd select + congr_cl21_wG_d(3) <= (congr_cl21_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayG_upd select + congr_cl21_wG_d(4) <= (congr_cl21_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayG_upd select + congr_cl21_wG_d(5) <= (congr_cl21_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 22 +with rel_bixu22_wayG_upd select + congr_cl22_wG_d(0) <= (congr_cl22_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 22 +with rel_bixu22_wayG_upd select + congr_cl22_wG_d(1) <= (congr_cl22_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayG_upd select + congr_cl22_wG_d(2) <= (congr_cl22_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayG_upd select + congr_cl22_wG_d(3) <= (congr_cl22_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayG_upd select + congr_cl22_wG_d(4) <= (congr_cl22_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayG_upd select + congr_cl22_wG_d(5) <= (congr_cl22_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 23 +with rel_bixu23_wayG_upd select + congr_cl23_wG_d(0) <= (congr_cl23_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 23 +with rel_bixu23_wayG_upd select + congr_cl23_wG_d(1) <= (congr_cl23_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayG_upd select + congr_cl23_wG_d(2) <= (congr_cl23_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayG_upd select + congr_cl23_wG_d(3) <= (congr_cl23_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayG_upd select + congr_cl23_wG_d(4) <= (congr_cl23_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayG_upd select + congr_cl23_wG_d(5) <= (congr_cl23_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 24 +with rel_bixu24_wayG_upd select + congr_cl24_wG_d(0) <= (congr_cl24_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 24 +with rel_bixu24_wayG_upd select + congr_cl24_wG_d(1) <= (congr_cl24_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayG_upd select + congr_cl24_wG_d(2) <= (congr_cl24_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayG_upd select + congr_cl24_wG_d(3) <= (congr_cl24_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayG_upd select + congr_cl24_wG_d(4) <= (congr_cl24_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayG_upd select + congr_cl24_wG_d(5) <= (congr_cl24_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 25 +with rel_bixu25_wayG_upd select + congr_cl25_wG_d(0) <= (congr_cl25_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 25 +with rel_bixu25_wayG_upd select + congr_cl25_wG_d(1) <= (congr_cl25_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayG_upd select + congr_cl25_wG_d(2) <= (congr_cl25_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayG_upd select + congr_cl25_wG_d(3) <= (congr_cl25_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayG_upd select + congr_cl25_wG_d(4) <= (congr_cl25_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayG_upd select + congr_cl25_wG_d(5) <= (congr_cl25_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 26 +with rel_bixu26_wayG_upd select + congr_cl26_wG_d(0) <= (congr_cl26_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 26 +with rel_bixu26_wayG_upd select + congr_cl26_wG_d(1) <= (congr_cl26_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayG_upd select + congr_cl26_wG_d(2) <= (congr_cl26_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayG_upd select + congr_cl26_wG_d(3) <= (congr_cl26_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayG_upd select + congr_cl26_wG_d(4) <= (congr_cl26_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayG_upd select + congr_cl26_wG_d(5) <= (congr_cl26_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 27 +with rel_bixu27_wayG_upd select + congr_cl27_wG_d(0) <= (congr_cl27_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 27 +with rel_bixu27_wayG_upd select + congr_cl27_wG_d(1) <= (congr_cl27_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayG_upd select + congr_cl27_wG_d(2) <= (congr_cl27_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayG_upd select + congr_cl27_wG_d(3) <= (congr_cl27_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayG_upd select + congr_cl27_wG_d(4) <= (congr_cl27_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayG_upd select + congr_cl27_wG_d(5) <= (congr_cl27_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 28 +with rel_bixu28_wayG_upd select + congr_cl28_wG_d(0) <= (congr_cl28_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 28 +with rel_bixu28_wayG_upd select + congr_cl28_wG_d(1) <= (congr_cl28_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayG_upd select + congr_cl28_wG_d(2) <= (congr_cl28_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayG_upd select + congr_cl28_wG_d(3) <= (congr_cl28_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayG_upd select + congr_cl28_wG_d(4) <= (congr_cl28_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayG_upd select + congr_cl28_wG_d(5) <= (congr_cl28_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 29 +with rel_bixu29_wayG_upd select + congr_cl29_wG_d(0) <= (congr_cl29_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 29 +with rel_bixu29_wayG_upd select + congr_cl29_wG_d(1) <= (congr_cl29_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayG_upd select + congr_cl29_wG_d(2) <= (congr_cl29_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayG_upd select + congr_cl29_wG_d(3) <= (congr_cl29_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayG_upd select + congr_cl29_wG_d(4) <= (congr_cl29_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayG_upd select + congr_cl29_wG_d(5) <= (congr_cl29_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 30 +with rel_bixu30_wayG_upd select + congr_cl30_wG_d(0) <= (congr_cl30_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 30 +with rel_bixu30_wayG_upd select + congr_cl30_wG_d(1) <= (congr_cl30_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayG_upd select + congr_cl30_wG_d(2) <= (congr_cl30_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayG_upd select + congr_cl30_wG_d(3) <= (congr_cl30_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayG_upd select + congr_cl30_wG_d(4) <= (congr_cl30_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayG_upd select + congr_cl30_wG_d(5) <= (congr_cl30_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 31 +with rel_bixu31_wayG_upd select + congr_cl31_wG_d(0) <= (congr_cl31_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 31 +with rel_bixu31_wayG_upd select + congr_cl31_wG_d(1) <= (congr_cl31_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayG_upd select + congr_cl31_wG_d(2) <= (congr_cl31_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayG_upd select + congr_cl31_wG_d(3) <= (congr_cl31_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayG_upd select + congr_cl31_wG_d(4) <= (congr_cl31_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayG_upd select + congr_cl31_wG_d(5) <= (congr_cl31_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 32 +with rel_bixu32_wayG_upd select + congr_cl32_wG_d(0) <= (congr_cl32_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 32 +with rel_bixu32_wayG_upd select + congr_cl32_wG_d(1) <= (congr_cl32_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 32 +with rel_bixu32_wayG_upd select + congr_cl32_wG_d(2) <= (congr_cl32_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 32 +with rel_bixu32_wayG_upd select + congr_cl32_wG_d(3) <= (congr_cl32_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 32 +with rel_bixu32_wayG_upd select + congr_cl32_wG_d(4) <= (congr_cl32_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 32 +with rel_bixu32_wayG_upd select + congr_cl32_wG_d(5) <= (congr_cl32_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 33 +with rel_bixu33_wayG_upd select + congr_cl33_wG_d(0) <= (congr_cl33_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 33 +with rel_bixu33_wayG_upd select + congr_cl33_wG_d(1) <= (congr_cl33_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 33 +with rel_bixu33_wayG_upd select + congr_cl33_wG_d(2) <= (congr_cl33_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 33 +with rel_bixu33_wayG_upd select + congr_cl33_wG_d(3) <= (congr_cl33_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 33 +with rel_bixu33_wayG_upd select + congr_cl33_wG_d(4) <= (congr_cl33_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 33 +with rel_bixu33_wayG_upd select + congr_cl33_wG_d(5) <= (congr_cl33_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 34 +with rel_bixu34_wayG_upd select + congr_cl34_wG_d(0) <= (congr_cl34_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 34 +with rel_bixu34_wayG_upd select + congr_cl34_wG_d(1) <= (congr_cl34_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 34 +with rel_bixu34_wayG_upd select + congr_cl34_wG_d(2) <= (congr_cl34_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 34 +with rel_bixu34_wayG_upd select + congr_cl34_wG_d(3) <= (congr_cl34_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 34 +with rel_bixu34_wayG_upd select + congr_cl34_wG_d(4) <= (congr_cl34_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 34 +with rel_bixu34_wayG_upd select + congr_cl34_wG_d(5) <= (congr_cl34_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 35 +with rel_bixu35_wayG_upd select + congr_cl35_wG_d(0) <= (congr_cl35_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 35 +with rel_bixu35_wayG_upd select + congr_cl35_wG_d(1) <= (congr_cl35_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 35 +with rel_bixu35_wayG_upd select + congr_cl35_wG_d(2) <= (congr_cl35_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 35 +with rel_bixu35_wayG_upd select + congr_cl35_wG_d(3) <= (congr_cl35_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 35 +with rel_bixu35_wayG_upd select + congr_cl35_wG_d(4) <= (congr_cl35_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 35 +with rel_bixu35_wayG_upd select + congr_cl35_wG_d(5) <= (congr_cl35_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 36 +with rel_bixu36_wayG_upd select + congr_cl36_wG_d(0) <= (congr_cl36_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 36 +with rel_bixu36_wayG_upd select + congr_cl36_wG_d(1) <= (congr_cl36_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 36 +with rel_bixu36_wayG_upd select + congr_cl36_wG_d(2) <= (congr_cl36_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 36 +with rel_bixu36_wayG_upd select + congr_cl36_wG_d(3) <= (congr_cl36_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 36 +with rel_bixu36_wayG_upd select + congr_cl36_wG_d(4) <= (congr_cl36_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 36 +with rel_bixu36_wayG_upd select + congr_cl36_wG_d(5) <= (congr_cl36_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 37 +with rel_bixu37_wayG_upd select + congr_cl37_wG_d(0) <= (congr_cl37_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 37 +with rel_bixu37_wayG_upd select + congr_cl37_wG_d(1) <= (congr_cl37_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 37 +with rel_bixu37_wayG_upd select + congr_cl37_wG_d(2) <= (congr_cl37_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 37 +with rel_bixu37_wayG_upd select + congr_cl37_wG_d(3) <= (congr_cl37_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 37 +with rel_bixu37_wayG_upd select + congr_cl37_wG_d(4) <= (congr_cl37_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 37 +with rel_bixu37_wayG_upd select + congr_cl37_wG_d(5) <= (congr_cl37_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 38 +with rel_bixu38_wayG_upd select + congr_cl38_wG_d(0) <= (congr_cl38_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 38 +with rel_bixu38_wayG_upd select + congr_cl38_wG_d(1) <= (congr_cl38_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 38 +with rel_bixu38_wayG_upd select + congr_cl38_wG_d(2) <= (congr_cl38_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 38 +with rel_bixu38_wayG_upd select + congr_cl38_wG_d(3) <= (congr_cl38_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 38 +with rel_bixu38_wayG_upd select + congr_cl38_wG_d(4) <= (congr_cl38_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 38 +with rel_bixu38_wayG_upd select + congr_cl38_wG_d(5) <= (congr_cl38_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 39 +with rel_bixu39_wayG_upd select + congr_cl39_wG_d(0) <= (congr_cl39_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 39 +with rel_bixu39_wayG_upd select + congr_cl39_wG_d(1) <= (congr_cl39_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 39 +with rel_bixu39_wayG_upd select + congr_cl39_wG_d(2) <= (congr_cl39_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 39 +with rel_bixu39_wayG_upd select + congr_cl39_wG_d(3) <= (congr_cl39_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 39 +with rel_bixu39_wayG_upd select + congr_cl39_wG_d(4) <= (congr_cl39_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 39 +with rel_bixu39_wayG_upd select + congr_cl39_wG_d(5) <= (congr_cl39_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 40 +with rel_bixu40_wayG_upd select + congr_cl40_wG_d(0) <= (congr_cl40_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 40 +with rel_bixu40_wayG_upd select + congr_cl40_wG_d(1) <= (congr_cl40_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 40 +with rel_bixu40_wayG_upd select + congr_cl40_wG_d(2) <= (congr_cl40_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 40 +with rel_bixu40_wayG_upd select + congr_cl40_wG_d(3) <= (congr_cl40_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 40 +with rel_bixu40_wayG_upd select + congr_cl40_wG_d(4) <= (congr_cl40_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 40 +with rel_bixu40_wayG_upd select + congr_cl40_wG_d(5) <= (congr_cl40_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 41 +with rel_bixu41_wayG_upd select + congr_cl41_wG_d(0) <= (congr_cl41_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 41 +with rel_bixu41_wayG_upd select + congr_cl41_wG_d(1) <= (congr_cl41_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 41 +with rel_bixu41_wayG_upd select + congr_cl41_wG_d(2) <= (congr_cl41_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 41 +with rel_bixu41_wayG_upd select + congr_cl41_wG_d(3) <= (congr_cl41_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 41 +with rel_bixu41_wayG_upd select + congr_cl41_wG_d(4) <= (congr_cl41_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 41 +with rel_bixu41_wayG_upd select + congr_cl41_wG_d(5) <= (congr_cl41_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 42 +with rel_bixu42_wayG_upd select + congr_cl42_wG_d(0) <= (congr_cl42_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 42 +with rel_bixu42_wayG_upd select + congr_cl42_wG_d(1) <= (congr_cl42_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 42 +with rel_bixu42_wayG_upd select + congr_cl42_wG_d(2) <= (congr_cl42_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 42 +with rel_bixu42_wayG_upd select + congr_cl42_wG_d(3) <= (congr_cl42_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 42 +with rel_bixu42_wayG_upd select + congr_cl42_wG_d(4) <= (congr_cl42_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 42 +with rel_bixu42_wayG_upd select + congr_cl42_wG_d(5) <= (congr_cl42_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 43 +with rel_bixu43_wayG_upd select + congr_cl43_wG_d(0) <= (congr_cl43_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 43 +with rel_bixu43_wayG_upd select + congr_cl43_wG_d(1) <= (congr_cl43_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 43 +with rel_bixu43_wayG_upd select + congr_cl43_wG_d(2) <= (congr_cl43_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 43 +with rel_bixu43_wayG_upd select + congr_cl43_wG_d(3) <= (congr_cl43_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 43 +with rel_bixu43_wayG_upd select + congr_cl43_wG_d(4) <= (congr_cl43_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 43 +with rel_bixu43_wayG_upd select + congr_cl43_wG_d(5) <= (congr_cl43_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 44 +with rel_bixu44_wayG_upd select + congr_cl44_wG_d(0) <= (congr_cl44_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 44 +with rel_bixu44_wayG_upd select + congr_cl44_wG_d(1) <= (congr_cl44_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 44 +with rel_bixu44_wayG_upd select + congr_cl44_wG_d(2) <= (congr_cl44_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 44 +with rel_bixu44_wayG_upd select + congr_cl44_wG_d(3) <= (congr_cl44_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 44 +with rel_bixu44_wayG_upd select + congr_cl44_wG_d(4) <= (congr_cl44_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 44 +with rel_bixu44_wayG_upd select + congr_cl44_wG_d(5) <= (congr_cl44_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 45 +with rel_bixu45_wayG_upd select + congr_cl45_wG_d(0) <= (congr_cl45_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 45 +with rel_bixu45_wayG_upd select + congr_cl45_wG_d(1) <= (congr_cl45_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 45 +with rel_bixu45_wayG_upd select + congr_cl45_wG_d(2) <= (congr_cl45_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 45 +with rel_bixu45_wayG_upd select + congr_cl45_wG_d(3) <= (congr_cl45_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 45 +with rel_bixu45_wayG_upd select + congr_cl45_wG_d(4) <= (congr_cl45_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 45 +with rel_bixu45_wayG_upd select + congr_cl45_wG_d(5) <= (congr_cl45_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 46 +with rel_bixu46_wayG_upd select + congr_cl46_wG_d(0) <= (congr_cl46_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 46 +with rel_bixu46_wayG_upd select + congr_cl46_wG_d(1) <= (congr_cl46_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 46 +with rel_bixu46_wayG_upd select + congr_cl46_wG_d(2) <= (congr_cl46_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 46 +with rel_bixu46_wayG_upd select + congr_cl46_wG_d(3) <= (congr_cl46_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 46 +with rel_bixu46_wayG_upd select + congr_cl46_wG_d(4) <= (congr_cl46_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 46 +with rel_bixu46_wayG_upd select + congr_cl46_wG_d(5) <= (congr_cl46_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 47 +with rel_bixu47_wayG_upd select + congr_cl47_wG_d(0) <= (congr_cl47_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 47 +with rel_bixu47_wayG_upd select + congr_cl47_wG_d(1) <= (congr_cl47_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 47 +with rel_bixu47_wayG_upd select + congr_cl47_wG_d(2) <= (congr_cl47_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 47 +with rel_bixu47_wayG_upd select + congr_cl47_wG_d(3) <= (congr_cl47_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 47 +with rel_bixu47_wayG_upd select + congr_cl47_wG_d(4) <= (congr_cl47_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 47 +with rel_bixu47_wayG_upd select + congr_cl47_wG_d(5) <= (congr_cl47_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 48 +with rel_bixu48_wayG_upd select + congr_cl48_wG_d(0) <= (congr_cl48_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 48 +with rel_bixu48_wayG_upd select + congr_cl48_wG_d(1) <= (congr_cl48_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 48 +with rel_bixu48_wayG_upd select + congr_cl48_wG_d(2) <= (congr_cl48_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 48 +with rel_bixu48_wayG_upd select + congr_cl48_wG_d(3) <= (congr_cl48_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 48 +with rel_bixu48_wayG_upd select + congr_cl48_wG_d(4) <= (congr_cl48_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 48 +with rel_bixu48_wayG_upd select + congr_cl48_wG_d(5) <= (congr_cl48_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 49 +with rel_bixu49_wayG_upd select + congr_cl49_wG_d(0) <= (congr_cl49_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 49 +with rel_bixu49_wayG_upd select + congr_cl49_wG_d(1) <= (congr_cl49_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 49 +with rel_bixu49_wayG_upd select + congr_cl49_wG_d(2) <= (congr_cl49_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 49 +with rel_bixu49_wayG_upd select + congr_cl49_wG_d(3) <= (congr_cl49_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 49 +with rel_bixu49_wayG_upd select + congr_cl49_wG_d(4) <= (congr_cl49_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 49 +with rel_bixu49_wayG_upd select + congr_cl49_wG_d(5) <= (congr_cl49_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 50 +with rel_bixu50_wayG_upd select + congr_cl50_wG_d(0) <= (congr_cl50_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 50 +with rel_bixu50_wayG_upd select + congr_cl50_wG_d(1) <= (congr_cl50_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 50 +with rel_bixu50_wayG_upd select + congr_cl50_wG_d(2) <= (congr_cl50_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 50 +with rel_bixu50_wayG_upd select + congr_cl50_wG_d(3) <= (congr_cl50_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 50 +with rel_bixu50_wayG_upd select + congr_cl50_wG_d(4) <= (congr_cl50_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 50 +with rel_bixu50_wayG_upd select + congr_cl50_wG_d(5) <= (congr_cl50_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 51 +with rel_bixu51_wayG_upd select + congr_cl51_wG_d(0) <= (congr_cl51_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 51 +with rel_bixu51_wayG_upd select + congr_cl51_wG_d(1) <= (congr_cl51_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 51 +with rel_bixu51_wayG_upd select + congr_cl51_wG_d(2) <= (congr_cl51_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 51 +with rel_bixu51_wayG_upd select + congr_cl51_wG_d(3) <= (congr_cl51_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 51 +with rel_bixu51_wayG_upd select + congr_cl51_wG_d(4) <= (congr_cl51_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 51 +with rel_bixu51_wayG_upd select + congr_cl51_wG_d(5) <= (congr_cl51_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 52 +with rel_bixu52_wayG_upd select + congr_cl52_wG_d(0) <= (congr_cl52_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 52 +with rel_bixu52_wayG_upd select + congr_cl52_wG_d(1) <= (congr_cl52_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 52 +with rel_bixu52_wayG_upd select + congr_cl52_wG_d(2) <= (congr_cl52_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 52 +with rel_bixu52_wayG_upd select + congr_cl52_wG_d(3) <= (congr_cl52_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 52 +with rel_bixu52_wayG_upd select + congr_cl52_wG_d(4) <= (congr_cl52_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 52 +with rel_bixu52_wayG_upd select + congr_cl52_wG_d(5) <= (congr_cl52_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 53 +with rel_bixu53_wayG_upd select + congr_cl53_wG_d(0) <= (congr_cl53_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 53 +with rel_bixu53_wayG_upd select + congr_cl53_wG_d(1) <= (congr_cl53_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 53 +with rel_bixu53_wayG_upd select + congr_cl53_wG_d(2) <= (congr_cl53_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 53 +with rel_bixu53_wayG_upd select + congr_cl53_wG_d(3) <= (congr_cl53_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 53 +with rel_bixu53_wayG_upd select + congr_cl53_wG_d(4) <= (congr_cl53_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 53 +with rel_bixu53_wayG_upd select + congr_cl53_wG_d(5) <= (congr_cl53_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 54 +with rel_bixu54_wayG_upd select + congr_cl54_wG_d(0) <= (congr_cl54_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 54 +with rel_bixu54_wayG_upd select + congr_cl54_wG_d(1) <= (congr_cl54_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 54 +with rel_bixu54_wayG_upd select + congr_cl54_wG_d(2) <= (congr_cl54_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 54 +with rel_bixu54_wayG_upd select + congr_cl54_wG_d(3) <= (congr_cl54_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 54 +with rel_bixu54_wayG_upd select + congr_cl54_wG_d(4) <= (congr_cl54_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 54 +with rel_bixu54_wayG_upd select + congr_cl54_wG_d(5) <= (congr_cl54_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 55 +with rel_bixu55_wayG_upd select + congr_cl55_wG_d(0) <= (congr_cl55_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 55 +with rel_bixu55_wayG_upd select + congr_cl55_wG_d(1) <= (congr_cl55_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 55 +with rel_bixu55_wayG_upd select + congr_cl55_wG_d(2) <= (congr_cl55_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 55 +with rel_bixu55_wayG_upd select + congr_cl55_wG_d(3) <= (congr_cl55_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 55 +with rel_bixu55_wayG_upd select + congr_cl55_wG_d(4) <= (congr_cl55_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 55 +with rel_bixu55_wayG_upd select + congr_cl55_wG_d(5) <= (congr_cl55_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 56 +with rel_bixu56_wayG_upd select + congr_cl56_wG_d(0) <= (congr_cl56_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 56 +with rel_bixu56_wayG_upd select + congr_cl56_wG_d(1) <= (congr_cl56_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 56 +with rel_bixu56_wayG_upd select + congr_cl56_wG_d(2) <= (congr_cl56_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 56 +with rel_bixu56_wayG_upd select + congr_cl56_wG_d(3) <= (congr_cl56_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 56 +with rel_bixu56_wayG_upd select + congr_cl56_wG_d(4) <= (congr_cl56_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 56 +with rel_bixu56_wayG_upd select + congr_cl56_wG_d(5) <= (congr_cl56_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 57 +with rel_bixu57_wayG_upd select + congr_cl57_wG_d(0) <= (congr_cl57_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 57 +with rel_bixu57_wayG_upd select + congr_cl57_wG_d(1) <= (congr_cl57_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 57 +with rel_bixu57_wayG_upd select + congr_cl57_wG_d(2) <= (congr_cl57_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 57 +with rel_bixu57_wayG_upd select + congr_cl57_wG_d(3) <= (congr_cl57_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 57 +with rel_bixu57_wayG_upd select + congr_cl57_wG_d(4) <= (congr_cl57_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 57 +with rel_bixu57_wayG_upd select + congr_cl57_wG_d(5) <= (congr_cl57_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 58 +with rel_bixu58_wayG_upd select + congr_cl58_wG_d(0) <= (congr_cl58_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 58 +with rel_bixu58_wayG_upd select + congr_cl58_wG_d(1) <= (congr_cl58_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 58 +with rel_bixu58_wayG_upd select + congr_cl58_wG_d(2) <= (congr_cl58_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 58 +with rel_bixu58_wayG_upd select + congr_cl58_wG_d(3) <= (congr_cl58_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 58 +with rel_bixu58_wayG_upd select + congr_cl58_wG_d(4) <= (congr_cl58_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 58 +with rel_bixu58_wayG_upd select + congr_cl58_wG_d(5) <= (congr_cl58_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 59 +with rel_bixu59_wayG_upd select + congr_cl59_wG_d(0) <= (congr_cl59_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 59 +with rel_bixu59_wayG_upd select + congr_cl59_wG_d(1) <= (congr_cl59_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 59 +with rel_bixu59_wayG_upd select + congr_cl59_wG_d(2) <= (congr_cl59_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 59 +with rel_bixu59_wayG_upd select + congr_cl59_wG_d(3) <= (congr_cl59_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 59 +with rel_bixu59_wayG_upd select + congr_cl59_wG_d(4) <= (congr_cl59_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 59 +with rel_bixu59_wayG_upd select + congr_cl59_wG_d(5) <= (congr_cl59_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 60 +with rel_bixu60_wayG_upd select + congr_cl60_wG_d(0) <= (congr_cl60_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 60 +with rel_bixu60_wayG_upd select + congr_cl60_wG_d(1) <= (congr_cl60_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 60 +with rel_bixu60_wayG_upd select + congr_cl60_wG_d(2) <= (congr_cl60_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 60 +with rel_bixu60_wayG_upd select + congr_cl60_wG_d(3) <= (congr_cl60_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 60 +with rel_bixu60_wayG_upd select + congr_cl60_wG_d(4) <= (congr_cl60_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 60 +with rel_bixu60_wayG_upd select + congr_cl60_wG_d(5) <= (congr_cl60_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 61 +with rel_bixu61_wayG_upd select + congr_cl61_wG_d(0) <= (congr_cl61_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 61 +with rel_bixu61_wayG_upd select + congr_cl61_wG_d(1) <= (congr_cl61_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 61 +with rel_bixu61_wayG_upd select + congr_cl61_wG_d(2) <= (congr_cl61_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 61 +with rel_bixu61_wayG_upd select + congr_cl61_wG_d(3) <= (congr_cl61_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 61 +with rel_bixu61_wayG_upd select + congr_cl61_wG_d(4) <= (congr_cl61_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 61 +with rel_bixu61_wayG_upd select + congr_cl61_wG_d(5) <= (congr_cl61_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 62 +with rel_bixu62_wayG_upd select + congr_cl62_wG_d(0) <= (congr_cl62_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 62 +with rel_bixu62_wayG_upd select + congr_cl62_wG_d(1) <= (congr_cl62_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 62 +with rel_bixu62_wayG_upd select + congr_cl62_wG_d(2) <= (congr_cl62_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 62 +with rel_bixu62_wayG_upd select + congr_cl62_wG_d(3) <= (congr_cl62_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 62 +with rel_bixu62_wayG_upd select + congr_cl62_wG_d(4) <= (congr_cl62_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 62 +with rel_bixu62_wayG_upd select + congr_cl62_wG_d(5) <= (congr_cl62_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayG Valid Bit Update for Congruence Class 63 +with rel_bixu63_wayG_upd select + congr_cl63_wG_d(0) <= (congr_cl63_wG_q(0) and not dci_inval_all_q) when "00", + (flush_wayG_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayG_data2_q(0) and not dci_inval_all_q) when others; +-- WayG Lock Bit Update for Congruence Class 63 +with rel_bixu63_wayG_upd select + congr_cl63_wG_d(1) <= (congr_cl63_wG_q(1) and not lock_finval) when "00", + (flush_wayG_data2_q(1) and not lock_finval) when "01", + (reload_wayG_data2_q(1) and not lock_finval) when others; +-- WayG Thread 0 Watch Bit Update for Congruence Class 63 +with rel_bixu63_wayG_upd select + congr_cl63_wG_d(2) <= (congr_cl63_wG_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayG_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayG Thread 1 Watch Bit Update for Congruence Class 63 +with rel_bixu63_wayG_upd select + congr_cl63_wG_d(3) <= (congr_cl63_wG_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayG_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayG Thread 2 Watch Bit Update for Congruence Class 63 +with rel_bixu63_wayG_upd select + congr_cl63_wG_d(4) <= (congr_cl63_wG_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayG_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayG Thread 3 Watch Bit Update for Congruence Class 63 +with rel_bixu63_wayG_upd select + congr_cl63_wG_d(5) <= (congr_cl63_wG_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayG_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Write Select for WayH +-- WayH Valid Bit Update for Congruence Class 0 +with rel_bixu0_wayH_upd select + congr_cl0_wH_d(0) <= (congr_cl0_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 0 +with rel_bixu0_wayH_upd select + congr_cl0_wH_d(1) <= (congr_cl0_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayH_upd select + congr_cl0_wH_d(2) <= (congr_cl0_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayH_upd select + congr_cl0_wH_d(3) <= (congr_cl0_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayH_upd select + congr_cl0_wH_d(4) <= (congr_cl0_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 0 +with rel_bixu0_wayH_upd select + congr_cl0_wH_d(5) <= (congr_cl0_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 1 +with rel_bixu1_wayH_upd select + congr_cl1_wH_d(0) <= (congr_cl1_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 1 +with rel_bixu1_wayH_upd select + congr_cl1_wH_d(1) <= (congr_cl1_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayH_upd select + congr_cl1_wH_d(2) <= (congr_cl1_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayH_upd select + congr_cl1_wH_d(3) <= (congr_cl1_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayH_upd select + congr_cl1_wH_d(4) <= (congr_cl1_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 1 +with rel_bixu1_wayH_upd select + congr_cl1_wH_d(5) <= (congr_cl1_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 2 +with rel_bixu2_wayH_upd select + congr_cl2_wH_d(0) <= (congr_cl2_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 2 +with rel_bixu2_wayH_upd select + congr_cl2_wH_d(1) <= (congr_cl2_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayH_upd select + congr_cl2_wH_d(2) <= (congr_cl2_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayH_upd select + congr_cl2_wH_d(3) <= (congr_cl2_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayH_upd select + congr_cl2_wH_d(4) <= (congr_cl2_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 2 +with rel_bixu2_wayH_upd select + congr_cl2_wH_d(5) <= (congr_cl2_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 3 +with rel_bixu3_wayH_upd select + congr_cl3_wH_d(0) <= (congr_cl3_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 3 +with rel_bixu3_wayH_upd select + congr_cl3_wH_d(1) <= (congr_cl3_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayH_upd select + congr_cl3_wH_d(2) <= (congr_cl3_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayH_upd select + congr_cl3_wH_d(3) <= (congr_cl3_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayH_upd select + congr_cl3_wH_d(4) <= (congr_cl3_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 3 +with rel_bixu3_wayH_upd select + congr_cl3_wH_d(5) <= (congr_cl3_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 4 +with rel_bixu4_wayH_upd select + congr_cl4_wH_d(0) <= (congr_cl4_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 4 +with rel_bixu4_wayH_upd select + congr_cl4_wH_d(1) <= (congr_cl4_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayH_upd select + congr_cl4_wH_d(2) <= (congr_cl4_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayH_upd select + congr_cl4_wH_d(3) <= (congr_cl4_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayH_upd select + congr_cl4_wH_d(4) <= (congr_cl4_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 4 +with rel_bixu4_wayH_upd select + congr_cl4_wH_d(5) <= (congr_cl4_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 5 +with rel_bixu5_wayH_upd select + congr_cl5_wH_d(0) <= (congr_cl5_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 5 +with rel_bixu5_wayH_upd select + congr_cl5_wH_d(1) <= (congr_cl5_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayH_upd select + congr_cl5_wH_d(2) <= (congr_cl5_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayH_upd select + congr_cl5_wH_d(3) <= (congr_cl5_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayH_upd select + congr_cl5_wH_d(4) <= (congr_cl5_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 5 +with rel_bixu5_wayH_upd select + congr_cl5_wH_d(5) <= (congr_cl5_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 6 +with rel_bixu6_wayH_upd select + congr_cl6_wH_d(0) <= (congr_cl6_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 6 +with rel_bixu6_wayH_upd select + congr_cl6_wH_d(1) <= (congr_cl6_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayH_upd select + congr_cl6_wH_d(2) <= (congr_cl6_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayH_upd select + congr_cl6_wH_d(3) <= (congr_cl6_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayH_upd select + congr_cl6_wH_d(4) <= (congr_cl6_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 6 +with rel_bixu6_wayH_upd select + congr_cl6_wH_d(5) <= (congr_cl6_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 7 +with rel_bixu7_wayH_upd select + congr_cl7_wH_d(0) <= (congr_cl7_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 7 +with rel_bixu7_wayH_upd select + congr_cl7_wH_d(1) <= (congr_cl7_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayH_upd select + congr_cl7_wH_d(2) <= (congr_cl7_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayH_upd select + congr_cl7_wH_d(3) <= (congr_cl7_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayH_upd select + congr_cl7_wH_d(4) <= (congr_cl7_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 7 +with rel_bixu7_wayH_upd select + congr_cl7_wH_d(5) <= (congr_cl7_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 8 +with rel_bixu8_wayH_upd select + congr_cl8_wH_d(0) <= (congr_cl8_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 8 +with rel_bixu8_wayH_upd select + congr_cl8_wH_d(1) <= (congr_cl8_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayH_upd select + congr_cl8_wH_d(2) <= (congr_cl8_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayH_upd select + congr_cl8_wH_d(3) <= (congr_cl8_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayH_upd select + congr_cl8_wH_d(4) <= (congr_cl8_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 8 +with rel_bixu8_wayH_upd select + congr_cl8_wH_d(5) <= (congr_cl8_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 9 +with rel_bixu9_wayH_upd select + congr_cl9_wH_d(0) <= (congr_cl9_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 9 +with rel_bixu9_wayH_upd select + congr_cl9_wH_d(1) <= (congr_cl9_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayH_upd select + congr_cl9_wH_d(2) <= (congr_cl9_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayH_upd select + congr_cl9_wH_d(3) <= (congr_cl9_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayH_upd select + congr_cl9_wH_d(4) <= (congr_cl9_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 9 +with rel_bixu9_wayH_upd select + congr_cl9_wH_d(5) <= (congr_cl9_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 10 +with rel_bixu10_wayH_upd select + congr_cl10_wH_d(0) <= (congr_cl10_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 10 +with rel_bixu10_wayH_upd select + congr_cl10_wH_d(1) <= (congr_cl10_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayH_upd select + congr_cl10_wH_d(2) <= (congr_cl10_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayH_upd select + congr_cl10_wH_d(3) <= (congr_cl10_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayH_upd select + congr_cl10_wH_d(4) <= (congr_cl10_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 10 +with rel_bixu10_wayH_upd select + congr_cl10_wH_d(5) <= (congr_cl10_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 11 +with rel_bixu11_wayH_upd select + congr_cl11_wH_d(0) <= (congr_cl11_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 11 +with rel_bixu11_wayH_upd select + congr_cl11_wH_d(1) <= (congr_cl11_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayH_upd select + congr_cl11_wH_d(2) <= (congr_cl11_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayH_upd select + congr_cl11_wH_d(3) <= (congr_cl11_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayH_upd select + congr_cl11_wH_d(4) <= (congr_cl11_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 11 +with rel_bixu11_wayH_upd select + congr_cl11_wH_d(5) <= (congr_cl11_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 12 +with rel_bixu12_wayH_upd select + congr_cl12_wH_d(0) <= (congr_cl12_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 12 +with rel_bixu12_wayH_upd select + congr_cl12_wH_d(1) <= (congr_cl12_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayH_upd select + congr_cl12_wH_d(2) <= (congr_cl12_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayH_upd select + congr_cl12_wH_d(3) <= (congr_cl12_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayH_upd select + congr_cl12_wH_d(4) <= (congr_cl12_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 12 +with rel_bixu12_wayH_upd select + congr_cl12_wH_d(5) <= (congr_cl12_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 13 +with rel_bixu13_wayH_upd select + congr_cl13_wH_d(0) <= (congr_cl13_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 13 +with rel_bixu13_wayH_upd select + congr_cl13_wH_d(1) <= (congr_cl13_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayH_upd select + congr_cl13_wH_d(2) <= (congr_cl13_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayH_upd select + congr_cl13_wH_d(3) <= (congr_cl13_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayH_upd select + congr_cl13_wH_d(4) <= (congr_cl13_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 13 +with rel_bixu13_wayH_upd select + congr_cl13_wH_d(5) <= (congr_cl13_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 14 +with rel_bixu14_wayH_upd select + congr_cl14_wH_d(0) <= (congr_cl14_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 14 +with rel_bixu14_wayH_upd select + congr_cl14_wH_d(1) <= (congr_cl14_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayH_upd select + congr_cl14_wH_d(2) <= (congr_cl14_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayH_upd select + congr_cl14_wH_d(3) <= (congr_cl14_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayH_upd select + congr_cl14_wH_d(4) <= (congr_cl14_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 14 +with rel_bixu14_wayH_upd select + congr_cl14_wH_d(5) <= (congr_cl14_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 15 +with rel_bixu15_wayH_upd select + congr_cl15_wH_d(0) <= (congr_cl15_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 15 +with rel_bixu15_wayH_upd select + congr_cl15_wH_d(1) <= (congr_cl15_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayH_upd select + congr_cl15_wH_d(2) <= (congr_cl15_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayH_upd select + congr_cl15_wH_d(3) <= (congr_cl15_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayH_upd select + congr_cl15_wH_d(4) <= (congr_cl15_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 15 +with rel_bixu15_wayH_upd select + congr_cl15_wH_d(5) <= (congr_cl15_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 16 +with rel_bixu16_wayH_upd select + congr_cl16_wH_d(0) <= (congr_cl16_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 16 +with rel_bixu16_wayH_upd select + congr_cl16_wH_d(1) <= (congr_cl16_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayH_upd select + congr_cl16_wH_d(2) <= (congr_cl16_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayH_upd select + congr_cl16_wH_d(3) <= (congr_cl16_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayH_upd select + congr_cl16_wH_d(4) <= (congr_cl16_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 16 +with rel_bixu16_wayH_upd select + congr_cl16_wH_d(5) <= (congr_cl16_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 17 +with rel_bixu17_wayH_upd select + congr_cl17_wH_d(0) <= (congr_cl17_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 17 +with rel_bixu17_wayH_upd select + congr_cl17_wH_d(1) <= (congr_cl17_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayH_upd select + congr_cl17_wH_d(2) <= (congr_cl17_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayH_upd select + congr_cl17_wH_d(3) <= (congr_cl17_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayH_upd select + congr_cl17_wH_d(4) <= (congr_cl17_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 17 +with rel_bixu17_wayH_upd select + congr_cl17_wH_d(5) <= (congr_cl17_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 18 +with rel_bixu18_wayH_upd select + congr_cl18_wH_d(0) <= (congr_cl18_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 18 +with rel_bixu18_wayH_upd select + congr_cl18_wH_d(1) <= (congr_cl18_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayH_upd select + congr_cl18_wH_d(2) <= (congr_cl18_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayH_upd select + congr_cl18_wH_d(3) <= (congr_cl18_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayH_upd select + congr_cl18_wH_d(4) <= (congr_cl18_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 18 +with rel_bixu18_wayH_upd select + congr_cl18_wH_d(5) <= (congr_cl18_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 19 +with rel_bixu19_wayH_upd select + congr_cl19_wH_d(0) <= (congr_cl19_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 19 +with rel_bixu19_wayH_upd select + congr_cl19_wH_d(1) <= (congr_cl19_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayH_upd select + congr_cl19_wH_d(2) <= (congr_cl19_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayH_upd select + congr_cl19_wH_d(3) <= (congr_cl19_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayH_upd select + congr_cl19_wH_d(4) <= (congr_cl19_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 19 +with rel_bixu19_wayH_upd select + congr_cl19_wH_d(5) <= (congr_cl19_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 20 +with rel_bixu20_wayH_upd select + congr_cl20_wH_d(0) <= (congr_cl20_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 20 +with rel_bixu20_wayH_upd select + congr_cl20_wH_d(1) <= (congr_cl20_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayH_upd select + congr_cl20_wH_d(2) <= (congr_cl20_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayH_upd select + congr_cl20_wH_d(3) <= (congr_cl20_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayH_upd select + congr_cl20_wH_d(4) <= (congr_cl20_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 20 +with rel_bixu20_wayH_upd select + congr_cl20_wH_d(5) <= (congr_cl20_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 21 +with rel_bixu21_wayH_upd select + congr_cl21_wH_d(0) <= (congr_cl21_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 21 +with rel_bixu21_wayH_upd select + congr_cl21_wH_d(1) <= (congr_cl21_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayH_upd select + congr_cl21_wH_d(2) <= (congr_cl21_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayH_upd select + congr_cl21_wH_d(3) <= (congr_cl21_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayH_upd select + congr_cl21_wH_d(4) <= (congr_cl21_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 21 +with rel_bixu21_wayH_upd select + congr_cl21_wH_d(5) <= (congr_cl21_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 22 +with rel_bixu22_wayH_upd select + congr_cl22_wH_d(0) <= (congr_cl22_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 22 +with rel_bixu22_wayH_upd select + congr_cl22_wH_d(1) <= (congr_cl22_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayH_upd select + congr_cl22_wH_d(2) <= (congr_cl22_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayH_upd select + congr_cl22_wH_d(3) <= (congr_cl22_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayH_upd select + congr_cl22_wH_d(4) <= (congr_cl22_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 22 +with rel_bixu22_wayH_upd select + congr_cl22_wH_d(5) <= (congr_cl22_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 23 +with rel_bixu23_wayH_upd select + congr_cl23_wH_d(0) <= (congr_cl23_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 23 +with rel_bixu23_wayH_upd select + congr_cl23_wH_d(1) <= (congr_cl23_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayH_upd select + congr_cl23_wH_d(2) <= (congr_cl23_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayH_upd select + congr_cl23_wH_d(3) <= (congr_cl23_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayH_upd select + congr_cl23_wH_d(4) <= (congr_cl23_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 23 +with rel_bixu23_wayH_upd select + congr_cl23_wH_d(5) <= (congr_cl23_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 24 +with rel_bixu24_wayH_upd select + congr_cl24_wH_d(0) <= (congr_cl24_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 24 +with rel_bixu24_wayH_upd select + congr_cl24_wH_d(1) <= (congr_cl24_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayH_upd select + congr_cl24_wH_d(2) <= (congr_cl24_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayH_upd select + congr_cl24_wH_d(3) <= (congr_cl24_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayH_upd select + congr_cl24_wH_d(4) <= (congr_cl24_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 24 +with rel_bixu24_wayH_upd select + congr_cl24_wH_d(5) <= (congr_cl24_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 25 +with rel_bixu25_wayH_upd select + congr_cl25_wH_d(0) <= (congr_cl25_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 25 +with rel_bixu25_wayH_upd select + congr_cl25_wH_d(1) <= (congr_cl25_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayH_upd select + congr_cl25_wH_d(2) <= (congr_cl25_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayH_upd select + congr_cl25_wH_d(3) <= (congr_cl25_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayH_upd select + congr_cl25_wH_d(4) <= (congr_cl25_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 25 +with rel_bixu25_wayH_upd select + congr_cl25_wH_d(5) <= (congr_cl25_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 26 +with rel_bixu26_wayH_upd select + congr_cl26_wH_d(0) <= (congr_cl26_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 26 +with rel_bixu26_wayH_upd select + congr_cl26_wH_d(1) <= (congr_cl26_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayH_upd select + congr_cl26_wH_d(2) <= (congr_cl26_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayH_upd select + congr_cl26_wH_d(3) <= (congr_cl26_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayH_upd select + congr_cl26_wH_d(4) <= (congr_cl26_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 26 +with rel_bixu26_wayH_upd select + congr_cl26_wH_d(5) <= (congr_cl26_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 27 +with rel_bixu27_wayH_upd select + congr_cl27_wH_d(0) <= (congr_cl27_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 27 +with rel_bixu27_wayH_upd select + congr_cl27_wH_d(1) <= (congr_cl27_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayH_upd select + congr_cl27_wH_d(2) <= (congr_cl27_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayH_upd select + congr_cl27_wH_d(3) <= (congr_cl27_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayH_upd select + congr_cl27_wH_d(4) <= (congr_cl27_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 27 +with rel_bixu27_wayH_upd select + congr_cl27_wH_d(5) <= (congr_cl27_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 28 +with rel_bixu28_wayH_upd select + congr_cl28_wH_d(0) <= (congr_cl28_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 28 +with rel_bixu28_wayH_upd select + congr_cl28_wH_d(1) <= (congr_cl28_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayH_upd select + congr_cl28_wH_d(2) <= (congr_cl28_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayH_upd select + congr_cl28_wH_d(3) <= (congr_cl28_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayH_upd select + congr_cl28_wH_d(4) <= (congr_cl28_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 28 +with rel_bixu28_wayH_upd select + congr_cl28_wH_d(5) <= (congr_cl28_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 29 +with rel_bixu29_wayH_upd select + congr_cl29_wH_d(0) <= (congr_cl29_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 29 +with rel_bixu29_wayH_upd select + congr_cl29_wH_d(1) <= (congr_cl29_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayH_upd select + congr_cl29_wH_d(2) <= (congr_cl29_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayH_upd select + congr_cl29_wH_d(3) <= (congr_cl29_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayH_upd select + congr_cl29_wH_d(4) <= (congr_cl29_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 29 +with rel_bixu29_wayH_upd select + congr_cl29_wH_d(5) <= (congr_cl29_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 30 +with rel_bixu30_wayH_upd select + congr_cl30_wH_d(0) <= (congr_cl30_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 30 +with rel_bixu30_wayH_upd select + congr_cl30_wH_d(1) <= (congr_cl30_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayH_upd select + congr_cl30_wH_d(2) <= (congr_cl30_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayH_upd select + congr_cl30_wH_d(3) <= (congr_cl30_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayH_upd select + congr_cl30_wH_d(4) <= (congr_cl30_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 30 +with rel_bixu30_wayH_upd select + congr_cl30_wH_d(5) <= (congr_cl30_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 31 +with rel_bixu31_wayH_upd select + congr_cl31_wH_d(0) <= (congr_cl31_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 31 +with rel_bixu31_wayH_upd select + congr_cl31_wH_d(1) <= (congr_cl31_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayH_upd select + congr_cl31_wH_d(2) <= (congr_cl31_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayH_upd select + congr_cl31_wH_d(3) <= (congr_cl31_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayH_upd select + congr_cl31_wH_d(4) <= (congr_cl31_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 31 +with rel_bixu31_wayH_upd select + congr_cl31_wH_d(5) <= (congr_cl31_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 32 +with rel_bixu32_wayH_upd select + congr_cl32_wH_d(0) <= (congr_cl32_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 32 +with rel_bixu32_wayH_upd select + congr_cl32_wH_d(1) <= (congr_cl32_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 32 +with rel_bixu32_wayH_upd select + congr_cl32_wH_d(2) <= (congr_cl32_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 32 +with rel_bixu32_wayH_upd select + congr_cl32_wH_d(3) <= (congr_cl32_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 32 +with rel_bixu32_wayH_upd select + congr_cl32_wH_d(4) <= (congr_cl32_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 32 +with rel_bixu32_wayH_upd select + congr_cl32_wH_d(5) <= (congr_cl32_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 33 +with rel_bixu33_wayH_upd select + congr_cl33_wH_d(0) <= (congr_cl33_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 33 +with rel_bixu33_wayH_upd select + congr_cl33_wH_d(1) <= (congr_cl33_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 33 +with rel_bixu33_wayH_upd select + congr_cl33_wH_d(2) <= (congr_cl33_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 33 +with rel_bixu33_wayH_upd select + congr_cl33_wH_d(3) <= (congr_cl33_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 33 +with rel_bixu33_wayH_upd select + congr_cl33_wH_d(4) <= (congr_cl33_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 33 +with rel_bixu33_wayH_upd select + congr_cl33_wH_d(5) <= (congr_cl33_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 34 +with rel_bixu34_wayH_upd select + congr_cl34_wH_d(0) <= (congr_cl34_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 34 +with rel_bixu34_wayH_upd select + congr_cl34_wH_d(1) <= (congr_cl34_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 34 +with rel_bixu34_wayH_upd select + congr_cl34_wH_d(2) <= (congr_cl34_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 34 +with rel_bixu34_wayH_upd select + congr_cl34_wH_d(3) <= (congr_cl34_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 34 +with rel_bixu34_wayH_upd select + congr_cl34_wH_d(4) <= (congr_cl34_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 34 +with rel_bixu34_wayH_upd select + congr_cl34_wH_d(5) <= (congr_cl34_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 35 +with rel_bixu35_wayH_upd select + congr_cl35_wH_d(0) <= (congr_cl35_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 35 +with rel_bixu35_wayH_upd select + congr_cl35_wH_d(1) <= (congr_cl35_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 35 +with rel_bixu35_wayH_upd select + congr_cl35_wH_d(2) <= (congr_cl35_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 35 +with rel_bixu35_wayH_upd select + congr_cl35_wH_d(3) <= (congr_cl35_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 35 +with rel_bixu35_wayH_upd select + congr_cl35_wH_d(4) <= (congr_cl35_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 35 +with rel_bixu35_wayH_upd select + congr_cl35_wH_d(5) <= (congr_cl35_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 36 +with rel_bixu36_wayH_upd select + congr_cl36_wH_d(0) <= (congr_cl36_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 36 +with rel_bixu36_wayH_upd select + congr_cl36_wH_d(1) <= (congr_cl36_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 36 +with rel_bixu36_wayH_upd select + congr_cl36_wH_d(2) <= (congr_cl36_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 36 +with rel_bixu36_wayH_upd select + congr_cl36_wH_d(3) <= (congr_cl36_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 36 +with rel_bixu36_wayH_upd select + congr_cl36_wH_d(4) <= (congr_cl36_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 36 +with rel_bixu36_wayH_upd select + congr_cl36_wH_d(5) <= (congr_cl36_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 37 +with rel_bixu37_wayH_upd select + congr_cl37_wH_d(0) <= (congr_cl37_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 37 +with rel_bixu37_wayH_upd select + congr_cl37_wH_d(1) <= (congr_cl37_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 37 +with rel_bixu37_wayH_upd select + congr_cl37_wH_d(2) <= (congr_cl37_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 37 +with rel_bixu37_wayH_upd select + congr_cl37_wH_d(3) <= (congr_cl37_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 37 +with rel_bixu37_wayH_upd select + congr_cl37_wH_d(4) <= (congr_cl37_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 37 +with rel_bixu37_wayH_upd select + congr_cl37_wH_d(5) <= (congr_cl37_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 38 +with rel_bixu38_wayH_upd select + congr_cl38_wH_d(0) <= (congr_cl38_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 38 +with rel_bixu38_wayH_upd select + congr_cl38_wH_d(1) <= (congr_cl38_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 38 +with rel_bixu38_wayH_upd select + congr_cl38_wH_d(2) <= (congr_cl38_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 38 +with rel_bixu38_wayH_upd select + congr_cl38_wH_d(3) <= (congr_cl38_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 38 +with rel_bixu38_wayH_upd select + congr_cl38_wH_d(4) <= (congr_cl38_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 38 +with rel_bixu38_wayH_upd select + congr_cl38_wH_d(5) <= (congr_cl38_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 39 +with rel_bixu39_wayH_upd select + congr_cl39_wH_d(0) <= (congr_cl39_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 39 +with rel_bixu39_wayH_upd select + congr_cl39_wH_d(1) <= (congr_cl39_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 39 +with rel_bixu39_wayH_upd select + congr_cl39_wH_d(2) <= (congr_cl39_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 39 +with rel_bixu39_wayH_upd select + congr_cl39_wH_d(3) <= (congr_cl39_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 39 +with rel_bixu39_wayH_upd select + congr_cl39_wH_d(4) <= (congr_cl39_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 39 +with rel_bixu39_wayH_upd select + congr_cl39_wH_d(5) <= (congr_cl39_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 40 +with rel_bixu40_wayH_upd select + congr_cl40_wH_d(0) <= (congr_cl40_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 40 +with rel_bixu40_wayH_upd select + congr_cl40_wH_d(1) <= (congr_cl40_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 40 +with rel_bixu40_wayH_upd select + congr_cl40_wH_d(2) <= (congr_cl40_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 40 +with rel_bixu40_wayH_upd select + congr_cl40_wH_d(3) <= (congr_cl40_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 40 +with rel_bixu40_wayH_upd select + congr_cl40_wH_d(4) <= (congr_cl40_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 40 +with rel_bixu40_wayH_upd select + congr_cl40_wH_d(5) <= (congr_cl40_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 41 +with rel_bixu41_wayH_upd select + congr_cl41_wH_d(0) <= (congr_cl41_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 41 +with rel_bixu41_wayH_upd select + congr_cl41_wH_d(1) <= (congr_cl41_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 41 +with rel_bixu41_wayH_upd select + congr_cl41_wH_d(2) <= (congr_cl41_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 41 +with rel_bixu41_wayH_upd select + congr_cl41_wH_d(3) <= (congr_cl41_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 41 +with rel_bixu41_wayH_upd select + congr_cl41_wH_d(4) <= (congr_cl41_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 41 +with rel_bixu41_wayH_upd select + congr_cl41_wH_d(5) <= (congr_cl41_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 42 +with rel_bixu42_wayH_upd select + congr_cl42_wH_d(0) <= (congr_cl42_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 42 +with rel_bixu42_wayH_upd select + congr_cl42_wH_d(1) <= (congr_cl42_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 42 +with rel_bixu42_wayH_upd select + congr_cl42_wH_d(2) <= (congr_cl42_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 42 +with rel_bixu42_wayH_upd select + congr_cl42_wH_d(3) <= (congr_cl42_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 42 +with rel_bixu42_wayH_upd select + congr_cl42_wH_d(4) <= (congr_cl42_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 42 +with rel_bixu42_wayH_upd select + congr_cl42_wH_d(5) <= (congr_cl42_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 43 +with rel_bixu43_wayH_upd select + congr_cl43_wH_d(0) <= (congr_cl43_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 43 +with rel_bixu43_wayH_upd select + congr_cl43_wH_d(1) <= (congr_cl43_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 43 +with rel_bixu43_wayH_upd select + congr_cl43_wH_d(2) <= (congr_cl43_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 43 +with rel_bixu43_wayH_upd select + congr_cl43_wH_d(3) <= (congr_cl43_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 43 +with rel_bixu43_wayH_upd select + congr_cl43_wH_d(4) <= (congr_cl43_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 43 +with rel_bixu43_wayH_upd select + congr_cl43_wH_d(5) <= (congr_cl43_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 44 +with rel_bixu44_wayH_upd select + congr_cl44_wH_d(0) <= (congr_cl44_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 44 +with rel_bixu44_wayH_upd select + congr_cl44_wH_d(1) <= (congr_cl44_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 44 +with rel_bixu44_wayH_upd select + congr_cl44_wH_d(2) <= (congr_cl44_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 44 +with rel_bixu44_wayH_upd select + congr_cl44_wH_d(3) <= (congr_cl44_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 44 +with rel_bixu44_wayH_upd select + congr_cl44_wH_d(4) <= (congr_cl44_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 44 +with rel_bixu44_wayH_upd select + congr_cl44_wH_d(5) <= (congr_cl44_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 45 +with rel_bixu45_wayH_upd select + congr_cl45_wH_d(0) <= (congr_cl45_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 45 +with rel_bixu45_wayH_upd select + congr_cl45_wH_d(1) <= (congr_cl45_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 45 +with rel_bixu45_wayH_upd select + congr_cl45_wH_d(2) <= (congr_cl45_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 45 +with rel_bixu45_wayH_upd select + congr_cl45_wH_d(3) <= (congr_cl45_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 45 +with rel_bixu45_wayH_upd select + congr_cl45_wH_d(4) <= (congr_cl45_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 45 +with rel_bixu45_wayH_upd select + congr_cl45_wH_d(5) <= (congr_cl45_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 46 +with rel_bixu46_wayH_upd select + congr_cl46_wH_d(0) <= (congr_cl46_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 46 +with rel_bixu46_wayH_upd select + congr_cl46_wH_d(1) <= (congr_cl46_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 46 +with rel_bixu46_wayH_upd select + congr_cl46_wH_d(2) <= (congr_cl46_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 46 +with rel_bixu46_wayH_upd select + congr_cl46_wH_d(3) <= (congr_cl46_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 46 +with rel_bixu46_wayH_upd select + congr_cl46_wH_d(4) <= (congr_cl46_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 46 +with rel_bixu46_wayH_upd select + congr_cl46_wH_d(5) <= (congr_cl46_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 47 +with rel_bixu47_wayH_upd select + congr_cl47_wH_d(0) <= (congr_cl47_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 47 +with rel_bixu47_wayH_upd select + congr_cl47_wH_d(1) <= (congr_cl47_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 47 +with rel_bixu47_wayH_upd select + congr_cl47_wH_d(2) <= (congr_cl47_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 47 +with rel_bixu47_wayH_upd select + congr_cl47_wH_d(3) <= (congr_cl47_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 47 +with rel_bixu47_wayH_upd select + congr_cl47_wH_d(4) <= (congr_cl47_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 47 +with rel_bixu47_wayH_upd select + congr_cl47_wH_d(5) <= (congr_cl47_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 48 +with rel_bixu48_wayH_upd select + congr_cl48_wH_d(0) <= (congr_cl48_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 48 +with rel_bixu48_wayH_upd select + congr_cl48_wH_d(1) <= (congr_cl48_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 48 +with rel_bixu48_wayH_upd select + congr_cl48_wH_d(2) <= (congr_cl48_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 48 +with rel_bixu48_wayH_upd select + congr_cl48_wH_d(3) <= (congr_cl48_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 48 +with rel_bixu48_wayH_upd select + congr_cl48_wH_d(4) <= (congr_cl48_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 48 +with rel_bixu48_wayH_upd select + congr_cl48_wH_d(5) <= (congr_cl48_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 49 +with rel_bixu49_wayH_upd select + congr_cl49_wH_d(0) <= (congr_cl49_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 49 +with rel_bixu49_wayH_upd select + congr_cl49_wH_d(1) <= (congr_cl49_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 49 +with rel_bixu49_wayH_upd select + congr_cl49_wH_d(2) <= (congr_cl49_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 49 +with rel_bixu49_wayH_upd select + congr_cl49_wH_d(3) <= (congr_cl49_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 49 +with rel_bixu49_wayH_upd select + congr_cl49_wH_d(4) <= (congr_cl49_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 49 +with rel_bixu49_wayH_upd select + congr_cl49_wH_d(5) <= (congr_cl49_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 50 +with rel_bixu50_wayH_upd select + congr_cl50_wH_d(0) <= (congr_cl50_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 50 +with rel_bixu50_wayH_upd select + congr_cl50_wH_d(1) <= (congr_cl50_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 50 +with rel_bixu50_wayH_upd select + congr_cl50_wH_d(2) <= (congr_cl50_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 50 +with rel_bixu50_wayH_upd select + congr_cl50_wH_d(3) <= (congr_cl50_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 50 +with rel_bixu50_wayH_upd select + congr_cl50_wH_d(4) <= (congr_cl50_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 50 +with rel_bixu50_wayH_upd select + congr_cl50_wH_d(5) <= (congr_cl50_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 51 +with rel_bixu51_wayH_upd select + congr_cl51_wH_d(0) <= (congr_cl51_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 51 +with rel_bixu51_wayH_upd select + congr_cl51_wH_d(1) <= (congr_cl51_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 51 +with rel_bixu51_wayH_upd select + congr_cl51_wH_d(2) <= (congr_cl51_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 51 +with rel_bixu51_wayH_upd select + congr_cl51_wH_d(3) <= (congr_cl51_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 51 +with rel_bixu51_wayH_upd select + congr_cl51_wH_d(4) <= (congr_cl51_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 51 +with rel_bixu51_wayH_upd select + congr_cl51_wH_d(5) <= (congr_cl51_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 52 +with rel_bixu52_wayH_upd select + congr_cl52_wH_d(0) <= (congr_cl52_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 52 +with rel_bixu52_wayH_upd select + congr_cl52_wH_d(1) <= (congr_cl52_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 52 +with rel_bixu52_wayH_upd select + congr_cl52_wH_d(2) <= (congr_cl52_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 52 +with rel_bixu52_wayH_upd select + congr_cl52_wH_d(3) <= (congr_cl52_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 52 +with rel_bixu52_wayH_upd select + congr_cl52_wH_d(4) <= (congr_cl52_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 52 +with rel_bixu52_wayH_upd select + congr_cl52_wH_d(5) <= (congr_cl52_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 53 +with rel_bixu53_wayH_upd select + congr_cl53_wH_d(0) <= (congr_cl53_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 53 +with rel_bixu53_wayH_upd select + congr_cl53_wH_d(1) <= (congr_cl53_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 53 +with rel_bixu53_wayH_upd select + congr_cl53_wH_d(2) <= (congr_cl53_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 53 +with rel_bixu53_wayH_upd select + congr_cl53_wH_d(3) <= (congr_cl53_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 53 +with rel_bixu53_wayH_upd select + congr_cl53_wH_d(4) <= (congr_cl53_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 53 +with rel_bixu53_wayH_upd select + congr_cl53_wH_d(5) <= (congr_cl53_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 54 +with rel_bixu54_wayH_upd select + congr_cl54_wH_d(0) <= (congr_cl54_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 54 +with rel_bixu54_wayH_upd select + congr_cl54_wH_d(1) <= (congr_cl54_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 54 +with rel_bixu54_wayH_upd select + congr_cl54_wH_d(2) <= (congr_cl54_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 54 +with rel_bixu54_wayH_upd select + congr_cl54_wH_d(3) <= (congr_cl54_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 54 +with rel_bixu54_wayH_upd select + congr_cl54_wH_d(4) <= (congr_cl54_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 54 +with rel_bixu54_wayH_upd select + congr_cl54_wH_d(5) <= (congr_cl54_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 55 +with rel_bixu55_wayH_upd select + congr_cl55_wH_d(0) <= (congr_cl55_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 55 +with rel_bixu55_wayH_upd select + congr_cl55_wH_d(1) <= (congr_cl55_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 55 +with rel_bixu55_wayH_upd select + congr_cl55_wH_d(2) <= (congr_cl55_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 55 +with rel_bixu55_wayH_upd select + congr_cl55_wH_d(3) <= (congr_cl55_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 55 +with rel_bixu55_wayH_upd select + congr_cl55_wH_d(4) <= (congr_cl55_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 55 +with rel_bixu55_wayH_upd select + congr_cl55_wH_d(5) <= (congr_cl55_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 56 +with rel_bixu56_wayH_upd select + congr_cl56_wH_d(0) <= (congr_cl56_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 56 +with rel_bixu56_wayH_upd select + congr_cl56_wH_d(1) <= (congr_cl56_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 56 +with rel_bixu56_wayH_upd select + congr_cl56_wH_d(2) <= (congr_cl56_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 56 +with rel_bixu56_wayH_upd select + congr_cl56_wH_d(3) <= (congr_cl56_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 56 +with rel_bixu56_wayH_upd select + congr_cl56_wH_d(4) <= (congr_cl56_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 56 +with rel_bixu56_wayH_upd select + congr_cl56_wH_d(5) <= (congr_cl56_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 57 +with rel_bixu57_wayH_upd select + congr_cl57_wH_d(0) <= (congr_cl57_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 57 +with rel_bixu57_wayH_upd select + congr_cl57_wH_d(1) <= (congr_cl57_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 57 +with rel_bixu57_wayH_upd select + congr_cl57_wH_d(2) <= (congr_cl57_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 57 +with rel_bixu57_wayH_upd select + congr_cl57_wH_d(3) <= (congr_cl57_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 57 +with rel_bixu57_wayH_upd select + congr_cl57_wH_d(4) <= (congr_cl57_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 57 +with rel_bixu57_wayH_upd select + congr_cl57_wH_d(5) <= (congr_cl57_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 58 +with rel_bixu58_wayH_upd select + congr_cl58_wH_d(0) <= (congr_cl58_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 58 +with rel_bixu58_wayH_upd select + congr_cl58_wH_d(1) <= (congr_cl58_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 58 +with rel_bixu58_wayH_upd select + congr_cl58_wH_d(2) <= (congr_cl58_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 58 +with rel_bixu58_wayH_upd select + congr_cl58_wH_d(3) <= (congr_cl58_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 58 +with rel_bixu58_wayH_upd select + congr_cl58_wH_d(4) <= (congr_cl58_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 58 +with rel_bixu58_wayH_upd select + congr_cl58_wH_d(5) <= (congr_cl58_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 59 +with rel_bixu59_wayH_upd select + congr_cl59_wH_d(0) <= (congr_cl59_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 59 +with rel_bixu59_wayH_upd select + congr_cl59_wH_d(1) <= (congr_cl59_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 59 +with rel_bixu59_wayH_upd select + congr_cl59_wH_d(2) <= (congr_cl59_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 59 +with rel_bixu59_wayH_upd select + congr_cl59_wH_d(3) <= (congr_cl59_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 59 +with rel_bixu59_wayH_upd select + congr_cl59_wH_d(4) <= (congr_cl59_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 59 +with rel_bixu59_wayH_upd select + congr_cl59_wH_d(5) <= (congr_cl59_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 60 +with rel_bixu60_wayH_upd select + congr_cl60_wH_d(0) <= (congr_cl60_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 60 +with rel_bixu60_wayH_upd select + congr_cl60_wH_d(1) <= (congr_cl60_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 60 +with rel_bixu60_wayH_upd select + congr_cl60_wH_d(2) <= (congr_cl60_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 60 +with rel_bixu60_wayH_upd select + congr_cl60_wH_d(3) <= (congr_cl60_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 60 +with rel_bixu60_wayH_upd select + congr_cl60_wH_d(4) <= (congr_cl60_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 60 +with rel_bixu60_wayH_upd select + congr_cl60_wH_d(5) <= (congr_cl60_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 61 +with rel_bixu61_wayH_upd select + congr_cl61_wH_d(0) <= (congr_cl61_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 61 +with rel_bixu61_wayH_upd select + congr_cl61_wH_d(1) <= (congr_cl61_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 61 +with rel_bixu61_wayH_upd select + congr_cl61_wH_d(2) <= (congr_cl61_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 61 +with rel_bixu61_wayH_upd select + congr_cl61_wH_d(3) <= (congr_cl61_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 61 +with rel_bixu61_wayH_upd select + congr_cl61_wH_d(4) <= (congr_cl61_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 61 +with rel_bixu61_wayH_upd select + congr_cl61_wH_d(5) <= (congr_cl61_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 62 +with rel_bixu62_wayH_upd select + congr_cl62_wH_d(0) <= (congr_cl62_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 62 +with rel_bixu62_wayH_upd select + congr_cl62_wH_d(1) <= (congr_cl62_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 62 +with rel_bixu62_wayH_upd select + congr_cl62_wH_d(2) <= (congr_cl62_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 62 +with rel_bixu62_wayH_upd select + congr_cl62_wH_d(3) <= (congr_cl62_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 62 +with rel_bixu62_wayH_upd select + congr_cl62_wH_d(4) <= (congr_cl62_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 62 +with rel_bixu62_wayH_upd select + congr_cl62_wH_d(5) <= (congr_cl62_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- WayH Valid Bit Update for Congruence Class 63 +with rel_bixu63_wayH_upd select + congr_cl63_wH_d(0) <= (congr_cl63_wH_q(0) and not dci_inval_all_q) when "00", + (flush_wayH_data2_q(0) and not dci_inval_all_q) when "01", + (reload_wayH_data2_q(0) and not dci_inval_all_q) when others; +-- WayH Lock Bit Update for Congruence Class 63 +with rel_bixu63_wayH_upd select + congr_cl63_wH_d(1) <= (congr_cl63_wH_q(1) and not lock_finval) when "00", + (flush_wayH_data2_q(1) and not lock_finval) when "01", + (reload_wayH_data2_q(1) and not lock_finval) when others; +-- WayH Thread 0 Watch Bit Update for Congruence Class 63 +with rel_bixu63_wayH_upd select + congr_cl63_wH_d(2) <= (congr_cl63_wH_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "00", + (flush_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when "01", + (reload_wayH_data2_q(2) and not (dci_inval_all_q or ex6_watch_clr_all_q(0))) when others; +-- WayH Thread 1 Watch Bit Update for Congruence Class 63 +with rel_bixu63_wayH_upd select + congr_cl63_wH_d(3) <= (congr_cl63_wH_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "00", + (flush_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when "01", + (reload_wayH_data2_q(3) and not (dci_inval_all_q or ex6_watch_clr_all_q(1))) when others; +-- WayH Thread 2 Watch Bit Update for Congruence Class 63 +with rel_bixu63_wayH_upd select + congr_cl63_wH_d(4) <= (congr_cl63_wH_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "00", + (flush_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when "01", + (reload_wayH_data2_q(4) and not (dci_inval_all_q or ex6_watch_clr_all_q(2))) when others; +-- WayH Thread 3 Watch Bit Update for Congruence Class 63 +with rel_bixu63_wayH_upd select + congr_cl63_wH_d(5) <= (congr_cl63_wH_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "00", + (flush_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when "01", + (reload_wayH_data2_q(5) and not (dci_inval_all_q or ex6_watch_clr_all_q(3))) when others; +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Update Watch Lost State Bits per thread +with stm_upd_watchlost_tid0 select + stm_watchlost(0) <= stm_watchlost_state_q(0) when "00", + binv5_ex5_lost_watch_upd(0) when "01", + rel_lost_watch_upd_q(0) when others; +stm_upd_watchlost_tid0 <= rel_watchlost_upd(0) & ex5_watchlost_upd(0); +with stm_upd_watchlost_tid1 select + stm_watchlost(1) <= stm_watchlost_state_q(1) when "00", + binv5_ex5_lost_watch_upd(1) when "01", + rel_lost_watch_upd_q(1) when others; +stm_upd_watchlost_tid1 <= rel_watchlost_upd(1) & ex5_watchlost_upd(1); +with stm_upd_watchlost_tid2 select + stm_watchlost(2) <= stm_watchlost_state_q(2) when "00", + binv5_ex5_lost_watch_upd(2) when "01", + rel_lost_watch_upd_q(2) when others; +stm_upd_watchlost_tid2 <= rel_watchlost_upd(2) & ex5_watchlost_upd(2); +with stm_upd_watchlost_tid3 select + stm_watchlost(3) <= stm_watchlost_state_q(3) when "00", + binv5_ex5_lost_watch_upd(3) when "01", + rel_lost_watch_upd_q(3) when others; +stm_upd_watchlost_tid3 <= rel_watchlost_upd(3) & ex5_watchlost_upd(3); +rel_watchlost_upd <= rel_lost_watch_upd_q; +ex5_watchlost_upd <= gate(ex5_watchlost_set_q, p0_wren_d) or binv5_inval_watch_val_q or dci_watch_lost; +binv5_ex5_lost_watch_upd <= ex5_lost_watch_upd_q or binv5_inval_watch_val_q or dci_watch_lost; +-- Watch Lost Bits +stm_watchlost_state_d <= stm_watchlost; +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Spare Latches +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +rel4_l1dump_val_q <= not my_spare0_latches_q(0); +my_spare0_latches_d(0) <= rel3_l1dump_val; +my_spare0_latches_d(1 TO 16) <= not my_spare0_latches_q(1 to 16); +my_spare1_latches_d <= not my_spare1_latches_q; +-- #################################################### +-- Outputs +-- #################################################### +ex4_way_a_hit <= ex4_way_hit_q(0); +ex4_way_b_hit <= ex4_way_hit_q(1); +ex4_way_c_hit <= ex4_way_hit_q(2); +ex4_way_d_hit <= ex4_way_hit_q(3); +ex4_way_e_hit <= ex4_way_hit_q(4); +ex4_way_f_hit <= ex4_way_hit_q(5); +ex4_way_g_hit <= ex4_way_hit_q(6); +ex4_way_h_hit <= ex4_way_hit_q(7); +ex4_way_a_dir <= ex4_wayA_val_q; +ex4_way_b_dir <= ex4_wayB_val_q; +ex4_way_c_dir <= ex4_wayC_val_q; +ex4_way_d_dir <= ex4_wayD_val_q; +ex4_way_e_dir <= ex4_wayE_val_q; +ex4_way_f_dir <= ex4_wayF_val_q; +ex4_way_g_dir <= ex4_wayG_val_q; +ex4_way_h_dir <= ex4_wayH_val_q; +ex4_ldq_full_flush <= not ex4_ldq_full_flush_b_q; +ex4_snd_ld_l2 <= not ex4_snd_ld_l2_q; +dcarr_up_way_addr <= dcarr_up_way_addr_q; +pe_recov_begin <= not dcpar_err_rec_inprog; +lsu_xu_ex5_cr_rslt <= ex5_cr_watch_q; +rel_way_val_a <= rel_wayA_val(0); +rel_way_lock_a <= rel_wayA_val(1); +rel_way_val_b <= rel_wayB_val(0); +rel_way_lock_b <= rel_wayB_val(1); +rel_way_val_c <= rel_wayC_val(0); +rel_way_lock_c <= rel_wayC_val(1); +rel_way_val_d <= rel_wayD_val(0); +rel_way_lock_d <= rel_wayD_val(1); +rel_way_val_e <= rel_wayE_val(0); +rel_way_lock_e <= rel_wayE_val(1); +rel_way_val_f <= rel_wayF_val(0); +rel_way_lock_f <= rel_wayF_val(1); +rel_way_val_g <= rel_wayG_val(0); +rel_way_lock_g <= rel_wayG_val(1); +rel_way_val_h <= rel_wayH_val(0); +rel_way_lock_h <= rel_wayH_val(1); +-- Performance Events +lsu_xu_perf_events <= lost_watch_inter_thrd_q & lost_watch_evict_val_q & lost_watch_binv & perf_lsu_evnts_q; +-- Parity Error Detected +ex3_dir_perr_det <= ex3_dir_perr_val; +-- Directory MultiHit Detected +ex4_dir_multihit_det <= ex4_dir_multihit_val; +ex4_n_lsu_ddmh_flush <= not ex4_n_lsu_ddmh_flush_b_q; +-- DCTB ST LS instruction colliding with reload clear to same congruence class +ex2_lockwatchSet_rel_coll <= rel1_val and (ex2_lock_set or ex2_ldawx_instr) and (rel_congr_cl_q = ex2_congr_cl_q); +-- Watch clear all in pipe flushing other threads in pipe +ex3_wclr_all_flush <= ex3_wclr_all_upd_q and fxu_pipe_val; +-- Debug Data +dc_val_dbg_data <= (others=>'0'); +-- SPR Status +lsu_xu_spr_xucr0_cslc_xuop <= xucr0_cslc_xuop_q; +lsu_xu_spr_xucr0_cslc_binv <= xucr0_cslc_binv_q; +-- #################################################### +-- Directory Valid Bit Registers +-- #################################################### +-- Congruence Class 0 Way A Register +congr_cl0_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl0_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl0_wA_offset to congr_cl0_wA_offset + congr_cl0_wA_d'length-1), + scout => sov(congr_cl0_wA_offset to congr_cl0_wA_offset + congr_cl0_wA_d'length-1), + din => congr_cl0_wA_d, + dout => congr_cl0_wA_q); +-- Congruence Class 0 Way B Register +congr_cl0_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl0_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl0_wB_offset to congr_cl0_wB_offset + congr_cl0_wB_d'length-1), + scout => sov(congr_cl0_wB_offset to congr_cl0_wB_offset + congr_cl0_wB_d'length-1), + din => congr_cl0_wB_d, + dout => congr_cl0_wB_q); +-- Congruence Class 0 Way C Register +congr_cl0_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl0_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl0_wC_offset to congr_cl0_wC_offset + congr_cl0_wC_d'length-1), + scout => sov(congr_cl0_wC_offset to congr_cl0_wC_offset + congr_cl0_wC_d'length-1), + din => congr_cl0_wC_d, + dout => congr_cl0_wC_q); +-- Congruence Class 0 Way D Register +congr_cl0_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl0_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl0_wD_offset to congr_cl0_wD_offset + congr_cl0_wD_d'length-1), + scout => sov(congr_cl0_wD_offset to congr_cl0_wD_offset + congr_cl0_wD_d'length-1), + din => congr_cl0_wD_d, + dout => congr_cl0_wD_q); +-- Congruence Class 0 Way E Register +congr_cl0_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl0_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl0_wE_offset to congr_cl0_wE_offset + congr_cl0_wE_d'length-1), + scout => sov(congr_cl0_wE_offset to congr_cl0_wE_offset + congr_cl0_wE_d'length-1), + din => congr_cl0_wE_d, + dout => congr_cl0_wE_q); +-- Congruence Class 0 Way F Register +congr_cl0_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl0_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl0_wF_offset to congr_cl0_wF_offset + congr_cl0_wF_d'length-1), + scout => sov(congr_cl0_wF_offset to congr_cl0_wF_offset + congr_cl0_wF_d'length-1), + din => congr_cl0_wF_d, + dout => congr_cl0_wF_q); +-- Congruence Class 0 Way G Register +congr_cl0_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl0_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl0_wG_offset to congr_cl0_wG_offset + congr_cl0_wG_d'length-1), + scout => sov(congr_cl0_wG_offset to congr_cl0_wG_offset + congr_cl0_wG_d'length-1), + din => congr_cl0_wG_d, + dout => congr_cl0_wG_q); +-- Congruence Class 0 Way H Register +congr_cl0_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl0_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl0_wH_offset to congr_cl0_wH_offset + congr_cl0_wH_d'length-1), + scout => sov(congr_cl0_wH_offset to congr_cl0_wH_offset + congr_cl0_wH_d'length-1), + din => congr_cl0_wH_d, + dout => congr_cl0_wH_q); +-- Congruence Class 1 Way A Register +congr_cl1_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl1_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl1_wA_offset to congr_cl1_wA_offset + congr_cl1_wA_d'length-1), + scout => sov(congr_cl1_wA_offset to congr_cl1_wA_offset + congr_cl1_wA_d'length-1), + din => congr_cl1_wA_d, + dout => congr_cl1_wA_q); +-- Congruence Class 1 Way B Register +congr_cl1_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl1_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl1_wB_offset to congr_cl1_wB_offset + congr_cl1_wB_d'length-1), + scout => sov(congr_cl1_wB_offset to congr_cl1_wB_offset + congr_cl1_wB_d'length-1), + din => congr_cl1_wB_d, + dout => congr_cl1_wB_q); +-- Congruence Class 1 Way C Register +congr_cl1_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl1_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl1_wC_offset to congr_cl1_wC_offset + congr_cl1_wC_d'length-1), + scout => sov(congr_cl1_wC_offset to congr_cl1_wC_offset + congr_cl1_wC_d'length-1), + din => congr_cl1_wC_d, + dout => congr_cl1_wC_q); +-- Congruence Class 1 Way D Register +congr_cl1_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl1_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl1_wD_offset to congr_cl1_wD_offset + congr_cl1_wD_d'length-1), + scout => sov(congr_cl1_wD_offset to congr_cl1_wD_offset + congr_cl1_wD_d'length-1), + din => congr_cl1_wD_d, + dout => congr_cl1_wD_q); +-- Congruence Class 1 Way E Register +congr_cl1_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl1_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl1_wE_offset to congr_cl1_wE_offset + congr_cl1_wE_d'length-1), + scout => sov(congr_cl1_wE_offset to congr_cl1_wE_offset + congr_cl1_wE_d'length-1), + din => congr_cl1_wE_d, + dout => congr_cl1_wE_q); +-- Congruence Class 1 Way F Register +congr_cl1_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl1_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl1_wF_offset to congr_cl1_wF_offset + congr_cl1_wF_d'length-1), + scout => sov(congr_cl1_wF_offset to congr_cl1_wF_offset + congr_cl1_wF_d'length-1), + din => congr_cl1_wF_d, + dout => congr_cl1_wF_q); +-- Congruence Class 1 Way G Register +congr_cl1_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl1_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl1_wG_offset to congr_cl1_wG_offset + congr_cl1_wG_d'length-1), + scout => sov(congr_cl1_wG_offset to congr_cl1_wG_offset + congr_cl1_wG_d'length-1), + din => congr_cl1_wG_d, + dout => congr_cl1_wG_q); +-- Congruence Class 1 Way H Register +congr_cl1_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl1_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl1_wH_offset to congr_cl1_wH_offset + congr_cl1_wH_d'length-1), + scout => sov(congr_cl1_wH_offset to congr_cl1_wH_offset + congr_cl1_wH_d'length-1), + din => congr_cl1_wH_d, + dout => congr_cl1_wH_q); +-- Congruence Class 2 Way A Register +congr_cl2_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl2_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl2_wA_offset to congr_cl2_wA_offset + congr_cl2_wA_d'length-1), + scout => sov(congr_cl2_wA_offset to congr_cl2_wA_offset + congr_cl2_wA_d'length-1), + din => congr_cl2_wA_d, + dout => congr_cl2_wA_q); +-- Congruence Class 2 Way B Register +congr_cl2_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl2_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl2_wB_offset to congr_cl2_wB_offset + congr_cl2_wB_d'length-1), + scout => sov(congr_cl2_wB_offset to congr_cl2_wB_offset + congr_cl2_wB_d'length-1), + din => congr_cl2_wB_d, + dout => congr_cl2_wB_q); +-- Congruence Class 2 Way C Register +congr_cl2_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl2_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl2_wC_offset to congr_cl2_wC_offset + congr_cl2_wC_d'length-1), + scout => sov(congr_cl2_wC_offset to congr_cl2_wC_offset + congr_cl2_wC_d'length-1), + din => congr_cl2_wC_d, + dout => congr_cl2_wC_q); +-- Congruence Class 2 Way D Register +congr_cl2_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl2_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl2_wD_offset to congr_cl2_wD_offset + congr_cl2_wD_d'length-1), + scout => sov(congr_cl2_wD_offset to congr_cl2_wD_offset + congr_cl2_wD_d'length-1), + din => congr_cl2_wD_d, + dout => congr_cl2_wD_q); +-- Congruence Class 2 Way E Register +congr_cl2_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl2_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl2_wE_offset to congr_cl2_wE_offset + congr_cl2_wE_d'length-1), + scout => sov(congr_cl2_wE_offset to congr_cl2_wE_offset + congr_cl2_wE_d'length-1), + din => congr_cl2_wE_d, + dout => congr_cl2_wE_q); +-- Congruence Class 2 Way F Register +congr_cl2_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl2_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl2_wF_offset to congr_cl2_wF_offset + congr_cl2_wF_d'length-1), + scout => sov(congr_cl2_wF_offset to congr_cl2_wF_offset + congr_cl2_wF_d'length-1), + din => congr_cl2_wF_d, + dout => congr_cl2_wF_q); +-- Congruence Class 2 Way G Register +congr_cl2_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl2_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl2_wG_offset to congr_cl2_wG_offset + congr_cl2_wG_d'length-1), + scout => sov(congr_cl2_wG_offset to congr_cl2_wG_offset + congr_cl2_wG_d'length-1), + din => congr_cl2_wG_d, + dout => congr_cl2_wG_q); +-- Congruence Class 2 Way H Register +congr_cl2_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl2_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl2_wH_offset to congr_cl2_wH_offset + congr_cl2_wH_d'length-1), + scout => sov(congr_cl2_wH_offset to congr_cl2_wH_offset + congr_cl2_wH_d'length-1), + din => congr_cl2_wH_d, + dout => congr_cl2_wH_q); +-- Congruence Class 3 Way A Register +congr_cl3_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl3_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl3_wA_offset to congr_cl3_wA_offset + congr_cl3_wA_d'length-1), + scout => sov(congr_cl3_wA_offset to congr_cl3_wA_offset + congr_cl3_wA_d'length-1), + din => congr_cl3_wA_d, + dout => congr_cl3_wA_q); +-- Congruence Class 3 Way B Register +congr_cl3_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl3_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl3_wB_offset to congr_cl3_wB_offset + congr_cl3_wB_d'length-1), + scout => sov(congr_cl3_wB_offset to congr_cl3_wB_offset + congr_cl3_wB_d'length-1), + din => congr_cl3_wB_d, + dout => congr_cl3_wB_q); +-- Congruence Class 3 Way C Register +congr_cl3_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl3_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl3_wC_offset to congr_cl3_wC_offset + congr_cl3_wC_d'length-1), + scout => sov(congr_cl3_wC_offset to congr_cl3_wC_offset + congr_cl3_wC_d'length-1), + din => congr_cl3_wC_d, + dout => congr_cl3_wC_q); +-- Congruence Class 3 Way D Register +congr_cl3_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl3_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl3_wD_offset to congr_cl3_wD_offset + congr_cl3_wD_d'length-1), + scout => sov(congr_cl3_wD_offset to congr_cl3_wD_offset + congr_cl3_wD_d'length-1), + din => congr_cl3_wD_d, + dout => congr_cl3_wD_q); +-- Congruence Class 3 Way E Register +congr_cl3_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl3_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl3_wE_offset to congr_cl3_wE_offset + congr_cl3_wE_d'length-1), + scout => sov(congr_cl3_wE_offset to congr_cl3_wE_offset + congr_cl3_wE_d'length-1), + din => congr_cl3_wE_d, + dout => congr_cl3_wE_q); +-- Congruence Class 3 Way F Register +congr_cl3_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl3_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl3_wF_offset to congr_cl3_wF_offset + congr_cl3_wF_d'length-1), + scout => sov(congr_cl3_wF_offset to congr_cl3_wF_offset + congr_cl3_wF_d'length-1), + din => congr_cl3_wF_d, + dout => congr_cl3_wF_q); +-- Congruence Class 3 Way G Register +congr_cl3_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl3_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl3_wG_offset to congr_cl3_wG_offset + congr_cl3_wG_d'length-1), + scout => sov(congr_cl3_wG_offset to congr_cl3_wG_offset + congr_cl3_wG_d'length-1), + din => congr_cl3_wG_d, + dout => congr_cl3_wG_q); +-- Congruence Class 3 Way H Register +congr_cl3_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl3_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl3_wH_offset to congr_cl3_wH_offset + congr_cl3_wH_d'length-1), + scout => sov(congr_cl3_wH_offset to congr_cl3_wH_offset + congr_cl3_wH_d'length-1), + din => congr_cl3_wH_d, + dout => congr_cl3_wH_q); +-- Congruence Class 4 Way A Register +congr_cl4_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl4_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl4_wA_offset to congr_cl4_wA_offset + congr_cl4_wA_d'length-1), + scout => sov(congr_cl4_wA_offset to congr_cl4_wA_offset + congr_cl4_wA_d'length-1), + din => congr_cl4_wA_d, + dout => congr_cl4_wA_q); +-- Congruence Class 4 Way B Register +congr_cl4_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl4_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl4_wB_offset to congr_cl4_wB_offset + congr_cl4_wB_d'length-1), + scout => sov(congr_cl4_wB_offset to congr_cl4_wB_offset + congr_cl4_wB_d'length-1), + din => congr_cl4_wB_d, + dout => congr_cl4_wB_q); +-- Congruence Class 4 Way C Register +congr_cl4_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl4_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl4_wC_offset to congr_cl4_wC_offset + congr_cl4_wC_d'length-1), + scout => sov(congr_cl4_wC_offset to congr_cl4_wC_offset + congr_cl4_wC_d'length-1), + din => congr_cl4_wC_d, + dout => congr_cl4_wC_q); +-- Congruence Class 4 Way D Register +congr_cl4_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl4_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl4_wD_offset to congr_cl4_wD_offset + congr_cl4_wD_d'length-1), + scout => sov(congr_cl4_wD_offset to congr_cl4_wD_offset + congr_cl4_wD_d'length-1), + din => congr_cl4_wD_d, + dout => congr_cl4_wD_q); +-- Congruence Class 4 Way E Register +congr_cl4_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl4_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl4_wE_offset to congr_cl4_wE_offset + congr_cl4_wE_d'length-1), + scout => sov(congr_cl4_wE_offset to congr_cl4_wE_offset + congr_cl4_wE_d'length-1), + din => congr_cl4_wE_d, + dout => congr_cl4_wE_q); +-- Congruence Class 4 Way F Register +congr_cl4_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl4_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl4_wF_offset to congr_cl4_wF_offset + congr_cl4_wF_d'length-1), + scout => sov(congr_cl4_wF_offset to congr_cl4_wF_offset + congr_cl4_wF_d'length-1), + din => congr_cl4_wF_d, + dout => congr_cl4_wF_q); +-- Congruence Class 4 Way G Register +congr_cl4_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl4_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl4_wG_offset to congr_cl4_wG_offset + congr_cl4_wG_d'length-1), + scout => sov(congr_cl4_wG_offset to congr_cl4_wG_offset + congr_cl4_wG_d'length-1), + din => congr_cl4_wG_d, + dout => congr_cl4_wG_q); +-- Congruence Class 4 Way H Register +congr_cl4_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl4_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl4_wH_offset to congr_cl4_wH_offset + congr_cl4_wH_d'length-1), + scout => sov(congr_cl4_wH_offset to congr_cl4_wH_offset + congr_cl4_wH_d'length-1), + din => congr_cl4_wH_d, + dout => congr_cl4_wH_q); +-- Congruence Class 5 Way A Register +congr_cl5_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl5_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl5_wA_offset to congr_cl5_wA_offset + congr_cl5_wA_d'length-1), + scout => sov(congr_cl5_wA_offset to congr_cl5_wA_offset + congr_cl5_wA_d'length-1), + din => congr_cl5_wA_d, + dout => congr_cl5_wA_q); +-- Congruence Class 5 Way B Register +congr_cl5_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl5_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl5_wB_offset to congr_cl5_wB_offset + congr_cl5_wB_d'length-1), + scout => sov(congr_cl5_wB_offset to congr_cl5_wB_offset + congr_cl5_wB_d'length-1), + din => congr_cl5_wB_d, + dout => congr_cl5_wB_q); +-- Congruence Class 5 Way C Register +congr_cl5_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl5_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl5_wC_offset to congr_cl5_wC_offset + congr_cl5_wC_d'length-1), + scout => sov(congr_cl5_wC_offset to congr_cl5_wC_offset + congr_cl5_wC_d'length-1), + din => congr_cl5_wC_d, + dout => congr_cl5_wC_q); +-- Congruence Class 5 Way D Register +congr_cl5_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl5_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl5_wD_offset to congr_cl5_wD_offset + congr_cl5_wD_d'length-1), + scout => sov(congr_cl5_wD_offset to congr_cl5_wD_offset + congr_cl5_wD_d'length-1), + din => congr_cl5_wD_d, + dout => congr_cl5_wD_q); +-- Congruence Class 5 Way E Register +congr_cl5_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl5_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl5_wE_offset to congr_cl5_wE_offset + congr_cl5_wE_d'length-1), + scout => sov(congr_cl5_wE_offset to congr_cl5_wE_offset + congr_cl5_wE_d'length-1), + din => congr_cl5_wE_d, + dout => congr_cl5_wE_q); +-- Congruence Class 5 Way F Register +congr_cl5_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl5_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl5_wF_offset to congr_cl5_wF_offset + congr_cl5_wF_d'length-1), + scout => sov(congr_cl5_wF_offset to congr_cl5_wF_offset + congr_cl5_wF_d'length-1), + din => congr_cl5_wF_d, + dout => congr_cl5_wF_q); +-- Congruence Class 5 Way G Register +congr_cl5_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl5_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl5_wG_offset to congr_cl5_wG_offset + congr_cl5_wG_d'length-1), + scout => sov(congr_cl5_wG_offset to congr_cl5_wG_offset + congr_cl5_wG_d'length-1), + din => congr_cl5_wG_d, + dout => congr_cl5_wG_q); +-- Congruence Class 5 Way H Register +congr_cl5_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl5_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl5_wH_offset to congr_cl5_wH_offset + congr_cl5_wH_d'length-1), + scout => sov(congr_cl5_wH_offset to congr_cl5_wH_offset + congr_cl5_wH_d'length-1), + din => congr_cl5_wH_d, + dout => congr_cl5_wH_q); +-- Congruence Class 6 Way A Register +congr_cl6_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl6_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl6_wA_offset to congr_cl6_wA_offset + congr_cl6_wA_d'length-1), + scout => sov(congr_cl6_wA_offset to congr_cl6_wA_offset + congr_cl6_wA_d'length-1), + din => congr_cl6_wA_d, + dout => congr_cl6_wA_q); +-- Congruence Class 6 Way B Register +congr_cl6_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl6_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl6_wB_offset to congr_cl6_wB_offset + congr_cl6_wB_d'length-1), + scout => sov(congr_cl6_wB_offset to congr_cl6_wB_offset + congr_cl6_wB_d'length-1), + din => congr_cl6_wB_d, + dout => congr_cl6_wB_q); +-- Congruence Class 6 Way C Register +congr_cl6_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl6_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl6_wC_offset to congr_cl6_wC_offset + congr_cl6_wC_d'length-1), + scout => sov(congr_cl6_wC_offset to congr_cl6_wC_offset + congr_cl6_wC_d'length-1), + din => congr_cl6_wC_d, + dout => congr_cl6_wC_q); +-- Congruence Class 6 Way D Register +congr_cl6_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl6_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl6_wD_offset to congr_cl6_wD_offset + congr_cl6_wD_d'length-1), + scout => sov(congr_cl6_wD_offset to congr_cl6_wD_offset + congr_cl6_wD_d'length-1), + din => congr_cl6_wD_d, + dout => congr_cl6_wD_q); +-- Congruence Class 6 Way E Register +congr_cl6_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl6_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl6_wE_offset to congr_cl6_wE_offset + congr_cl6_wE_d'length-1), + scout => sov(congr_cl6_wE_offset to congr_cl6_wE_offset + congr_cl6_wE_d'length-1), + din => congr_cl6_wE_d, + dout => congr_cl6_wE_q); +-- Congruence Class 6 Way F Register +congr_cl6_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl6_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl6_wF_offset to congr_cl6_wF_offset + congr_cl6_wF_d'length-1), + scout => sov(congr_cl6_wF_offset to congr_cl6_wF_offset + congr_cl6_wF_d'length-1), + din => congr_cl6_wF_d, + dout => congr_cl6_wF_q); +-- Congruence Class 6 Way G Register +congr_cl6_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl6_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl6_wG_offset to congr_cl6_wG_offset + congr_cl6_wG_d'length-1), + scout => sov(congr_cl6_wG_offset to congr_cl6_wG_offset + congr_cl6_wG_d'length-1), + din => congr_cl6_wG_d, + dout => congr_cl6_wG_q); +-- Congruence Class 6 Way H Register +congr_cl6_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl6_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl6_wH_offset to congr_cl6_wH_offset + congr_cl6_wH_d'length-1), + scout => sov(congr_cl6_wH_offset to congr_cl6_wH_offset + congr_cl6_wH_d'length-1), + din => congr_cl6_wH_d, + dout => congr_cl6_wH_q); +-- Congruence Class 7 Way A Register +congr_cl7_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl7_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl7_wA_offset to congr_cl7_wA_offset + congr_cl7_wA_d'length-1), + scout => sov(congr_cl7_wA_offset to congr_cl7_wA_offset + congr_cl7_wA_d'length-1), + din => congr_cl7_wA_d, + dout => congr_cl7_wA_q); +-- Congruence Class 7 Way B Register +congr_cl7_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl7_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl7_wB_offset to congr_cl7_wB_offset + congr_cl7_wB_d'length-1), + scout => sov(congr_cl7_wB_offset to congr_cl7_wB_offset + congr_cl7_wB_d'length-1), + din => congr_cl7_wB_d, + dout => congr_cl7_wB_q); +-- Congruence Class 7 Way C Register +congr_cl7_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl7_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl7_wC_offset to congr_cl7_wC_offset + congr_cl7_wC_d'length-1), + scout => sov(congr_cl7_wC_offset to congr_cl7_wC_offset + congr_cl7_wC_d'length-1), + din => congr_cl7_wC_d, + dout => congr_cl7_wC_q); +-- Congruence Class 7 Way D Register +congr_cl7_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl7_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl7_wD_offset to congr_cl7_wD_offset + congr_cl7_wD_d'length-1), + scout => sov(congr_cl7_wD_offset to congr_cl7_wD_offset + congr_cl7_wD_d'length-1), + din => congr_cl7_wD_d, + dout => congr_cl7_wD_q); +-- Congruence Class 7 Way E Register +congr_cl7_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl7_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl7_wE_offset to congr_cl7_wE_offset + congr_cl7_wE_d'length-1), + scout => sov(congr_cl7_wE_offset to congr_cl7_wE_offset + congr_cl7_wE_d'length-1), + din => congr_cl7_wE_d, + dout => congr_cl7_wE_q); +-- Congruence Class 7 Way F Register +congr_cl7_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl7_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl7_wF_offset to congr_cl7_wF_offset + congr_cl7_wF_d'length-1), + scout => sov(congr_cl7_wF_offset to congr_cl7_wF_offset + congr_cl7_wF_d'length-1), + din => congr_cl7_wF_d, + dout => congr_cl7_wF_q); +-- Congruence Class 7 Way G Register +congr_cl7_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl7_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl7_wG_offset to congr_cl7_wG_offset + congr_cl7_wG_d'length-1), + scout => sov(congr_cl7_wG_offset to congr_cl7_wG_offset + congr_cl7_wG_d'length-1), + din => congr_cl7_wG_d, + dout => congr_cl7_wG_q); +-- Congruence Class 7 Way H Register +congr_cl7_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl7_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl7_wH_offset to congr_cl7_wH_offset + congr_cl7_wH_d'length-1), + scout => sov(congr_cl7_wH_offset to congr_cl7_wH_offset + congr_cl7_wH_d'length-1), + din => congr_cl7_wH_d, + dout => congr_cl7_wH_q); +-- Congruence Class 8 Way A Register +congr_cl8_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl8_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl8_wA_offset to congr_cl8_wA_offset + congr_cl8_wA_d'length-1), + scout => sov(congr_cl8_wA_offset to congr_cl8_wA_offset + congr_cl8_wA_d'length-1), + din => congr_cl8_wA_d, + dout => congr_cl8_wA_q); +-- Congruence Class 8 Way B Register +congr_cl8_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl8_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl8_wB_offset to congr_cl8_wB_offset + congr_cl8_wB_d'length-1), + scout => sov(congr_cl8_wB_offset to congr_cl8_wB_offset + congr_cl8_wB_d'length-1), + din => congr_cl8_wB_d, + dout => congr_cl8_wB_q); +-- Congruence Class 8 Way C Register +congr_cl8_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl8_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl8_wC_offset to congr_cl8_wC_offset + congr_cl8_wC_d'length-1), + scout => sov(congr_cl8_wC_offset to congr_cl8_wC_offset + congr_cl8_wC_d'length-1), + din => congr_cl8_wC_d, + dout => congr_cl8_wC_q); +-- Congruence Class 8 Way D Register +congr_cl8_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl8_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl8_wD_offset to congr_cl8_wD_offset + congr_cl8_wD_d'length-1), + scout => sov(congr_cl8_wD_offset to congr_cl8_wD_offset + congr_cl8_wD_d'length-1), + din => congr_cl8_wD_d, + dout => congr_cl8_wD_q); +-- Congruence Class 8 Way E Register +congr_cl8_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl8_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl8_wE_offset to congr_cl8_wE_offset + congr_cl8_wE_d'length-1), + scout => sov(congr_cl8_wE_offset to congr_cl8_wE_offset + congr_cl8_wE_d'length-1), + din => congr_cl8_wE_d, + dout => congr_cl8_wE_q); +-- Congruence Class 8 Way F Register +congr_cl8_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl8_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl8_wF_offset to congr_cl8_wF_offset + congr_cl8_wF_d'length-1), + scout => sov(congr_cl8_wF_offset to congr_cl8_wF_offset + congr_cl8_wF_d'length-1), + din => congr_cl8_wF_d, + dout => congr_cl8_wF_q); +-- Congruence Class 8 Way G Register +congr_cl8_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl8_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl8_wG_offset to congr_cl8_wG_offset + congr_cl8_wG_d'length-1), + scout => sov(congr_cl8_wG_offset to congr_cl8_wG_offset + congr_cl8_wG_d'length-1), + din => congr_cl8_wG_d, + dout => congr_cl8_wG_q); +-- Congruence Class 8 Way H Register +congr_cl8_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl8_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl8_wH_offset to congr_cl8_wH_offset + congr_cl8_wH_d'length-1), + scout => sov(congr_cl8_wH_offset to congr_cl8_wH_offset + congr_cl8_wH_d'length-1), + din => congr_cl8_wH_d, + dout => congr_cl8_wH_q); +-- Congruence Class 9 Way A Register +congr_cl9_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl9_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl9_wA_offset to congr_cl9_wA_offset + congr_cl9_wA_d'length-1), + scout => sov(congr_cl9_wA_offset to congr_cl9_wA_offset + congr_cl9_wA_d'length-1), + din => congr_cl9_wA_d, + dout => congr_cl9_wA_q); +-- Congruence Class 9 Way B Register +congr_cl9_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl9_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl9_wB_offset to congr_cl9_wB_offset + congr_cl9_wB_d'length-1), + scout => sov(congr_cl9_wB_offset to congr_cl9_wB_offset + congr_cl9_wB_d'length-1), + din => congr_cl9_wB_d, + dout => congr_cl9_wB_q); +-- Congruence Class 9 Way C Register +congr_cl9_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl9_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl9_wC_offset to congr_cl9_wC_offset + congr_cl9_wC_d'length-1), + scout => sov(congr_cl9_wC_offset to congr_cl9_wC_offset + congr_cl9_wC_d'length-1), + din => congr_cl9_wC_d, + dout => congr_cl9_wC_q); +-- Congruence Class 9 Way D Register +congr_cl9_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl9_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl9_wD_offset to congr_cl9_wD_offset + congr_cl9_wD_d'length-1), + scout => sov(congr_cl9_wD_offset to congr_cl9_wD_offset + congr_cl9_wD_d'length-1), + din => congr_cl9_wD_d, + dout => congr_cl9_wD_q); +-- Congruence Class 9 Way E Register +congr_cl9_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl9_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl9_wE_offset to congr_cl9_wE_offset + congr_cl9_wE_d'length-1), + scout => sov(congr_cl9_wE_offset to congr_cl9_wE_offset + congr_cl9_wE_d'length-1), + din => congr_cl9_wE_d, + dout => congr_cl9_wE_q); +-- Congruence Class 9 Way F Register +congr_cl9_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl9_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl9_wF_offset to congr_cl9_wF_offset + congr_cl9_wF_d'length-1), + scout => sov(congr_cl9_wF_offset to congr_cl9_wF_offset + congr_cl9_wF_d'length-1), + din => congr_cl9_wF_d, + dout => congr_cl9_wF_q); +-- Congruence Class 9 Way G Register +congr_cl9_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl9_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl9_wG_offset to congr_cl9_wG_offset + congr_cl9_wG_d'length-1), + scout => sov(congr_cl9_wG_offset to congr_cl9_wG_offset + congr_cl9_wG_d'length-1), + din => congr_cl9_wG_d, + dout => congr_cl9_wG_q); +-- Congruence Class 9 Way H Register +congr_cl9_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl9_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl9_wH_offset to congr_cl9_wH_offset + congr_cl9_wH_d'length-1), + scout => sov(congr_cl9_wH_offset to congr_cl9_wH_offset + congr_cl9_wH_d'length-1), + din => congr_cl9_wH_d, + dout => congr_cl9_wH_q); +-- Congruence Class 10 Way A Register +congr_cl10_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl10_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl10_wA_offset to congr_cl10_wA_offset + congr_cl10_wA_d'length-1), + scout => sov(congr_cl10_wA_offset to congr_cl10_wA_offset + congr_cl10_wA_d'length-1), + din => congr_cl10_wA_d, + dout => congr_cl10_wA_q); +-- Congruence Class 10 Way B Register +congr_cl10_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl10_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl10_wB_offset to congr_cl10_wB_offset + congr_cl10_wB_d'length-1), + scout => sov(congr_cl10_wB_offset to congr_cl10_wB_offset + congr_cl10_wB_d'length-1), + din => congr_cl10_wB_d, + dout => congr_cl10_wB_q); +-- Congruence Class 10 Way C Register +congr_cl10_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl10_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl10_wC_offset to congr_cl10_wC_offset + congr_cl10_wC_d'length-1), + scout => sov(congr_cl10_wC_offset to congr_cl10_wC_offset + congr_cl10_wC_d'length-1), + din => congr_cl10_wC_d, + dout => congr_cl10_wC_q); +-- Congruence Class 10 Way D Register +congr_cl10_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl10_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl10_wD_offset to congr_cl10_wD_offset + congr_cl10_wD_d'length-1), + scout => sov(congr_cl10_wD_offset to congr_cl10_wD_offset + congr_cl10_wD_d'length-1), + din => congr_cl10_wD_d, + dout => congr_cl10_wD_q); +-- Congruence Class 10 Way E Register +congr_cl10_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl10_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl10_wE_offset to congr_cl10_wE_offset + congr_cl10_wE_d'length-1), + scout => sov(congr_cl10_wE_offset to congr_cl10_wE_offset + congr_cl10_wE_d'length-1), + din => congr_cl10_wE_d, + dout => congr_cl10_wE_q); +-- Congruence Class 10 Way F Register +congr_cl10_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl10_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl10_wF_offset to congr_cl10_wF_offset + congr_cl10_wF_d'length-1), + scout => sov(congr_cl10_wF_offset to congr_cl10_wF_offset + congr_cl10_wF_d'length-1), + din => congr_cl10_wF_d, + dout => congr_cl10_wF_q); +-- Congruence Class 10 Way G Register +congr_cl10_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl10_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl10_wG_offset to congr_cl10_wG_offset + congr_cl10_wG_d'length-1), + scout => sov(congr_cl10_wG_offset to congr_cl10_wG_offset + congr_cl10_wG_d'length-1), + din => congr_cl10_wG_d, + dout => congr_cl10_wG_q); +-- Congruence Class 10 Way H Register +congr_cl10_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl10_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl10_wH_offset to congr_cl10_wH_offset + congr_cl10_wH_d'length-1), + scout => sov(congr_cl10_wH_offset to congr_cl10_wH_offset + congr_cl10_wH_d'length-1), + din => congr_cl10_wH_d, + dout => congr_cl10_wH_q); +-- Congruence Class 11 Way A Register +congr_cl11_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl11_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl11_wA_offset to congr_cl11_wA_offset + congr_cl11_wA_d'length-1), + scout => sov(congr_cl11_wA_offset to congr_cl11_wA_offset + congr_cl11_wA_d'length-1), + din => congr_cl11_wA_d, + dout => congr_cl11_wA_q); +-- Congruence Class 11 Way B Register +congr_cl11_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl11_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl11_wB_offset to congr_cl11_wB_offset + congr_cl11_wB_d'length-1), + scout => sov(congr_cl11_wB_offset to congr_cl11_wB_offset + congr_cl11_wB_d'length-1), + din => congr_cl11_wB_d, + dout => congr_cl11_wB_q); +-- Congruence Class 11 Way C Register +congr_cl11_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl11_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl11_wC_offset to congr_cl11_wC_offset + congr_cl11_wC_d'length-1), + scout => sov(congr_cl11_wC_offset to congr_cl11_wC_offset + congr_cl11_wC_d'length-1), + din => congr_cl11_wC_d, + dout => congr_cl11_wC_q); +-- Congruence Class 11 Way D Register +congr_cl11_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl11_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl11_wD_offset to congr_cl11_wD_offset + congr_cl11_wD_d'length-1), + scout => sov(congr_cl11_wD_offset to congr_cl11_wD_offset + congr_cl11_wD_d'length-1), + din => congr_cl11_wD_d, + dout => congr_cl11_wD_q); +-- Congruence Class 11 Way E Register +congr_cl11_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl11_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl11_wE_offset to congr_cl11_wE_offset + congr_cl11_wE_d'length-1), + scout => sov(congr_cl11_wE_offset to congr_cl11_wE_offset + congr_cl11_wE_d'length-1), + din => congr_cl11_wE_d, + dout => congr_cl11_wE_q); +-- Congruence Class 11 Way F Register +congr_cl11_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl11_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl11_wF_offset to congr_cl11_wF_offset + congr_cl11_wF_d'length-1), + scout => sov(congr_cl11_wF_offset to congr_cl11_wF_offset + congr_cl11_wF_d'length-1), + din => congr_cl11_wF_d, + dout => congr_cl11_wF_q); +-- Congruence Class 11 Way G Register +congr_cl11_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl11_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl11_wG_offset to congr_cl11_wG_offset + congr_cl11_wG_d'length-1), + scout => sov(congr_cl11_wG_offset to congr_cl11_wG_offset + congr_cl11_wG_d'length-1), + din => congr_cl11_wG_d, + dout => congr_cl11_wG_q); +-- Congruence Class 11 Way H Register +congr_cl11_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl11_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl11_wH_offset to congr_cl11_wH_offset + congr_cl11_wH_d'length-1), + scout => sov(congr_cl11_wH_offset to congr_cl11_wH_offset + congr_cl11_wH_d'length-1), + din => congr_cl11_wH_d, + dout => congr_cl11_wH_q); +-- Congruence Class 12 Way A Register +congr_cl12_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl12_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl12_wA_offset to congr_cl12_wA_offset + congr_cl12_wA_d'length-1), + scout => sov(congr_cl12_wA_offset to congr_cl12_wA_offset + congr_cl12_wA_d'length-1), + din => congr_cl12_wA_d, + dout => congr_cl12_wA_q); +-- Congruence Class 12 Way B Register +congr_cl12_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl12_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl12_wB_offset to congr_cl12_wB_offset + congr_cl12_wB_d'length-1), + scout => sov(congr_cl12_wB_offset to congr_cl12_wB_offset + congr_cl12_wB_d'length-1), + din => congr_cl12_wB_d, + dout => congr_cl12_wB_q); +-- Congruence Class 12 Way C Register +congr_cl12_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl12_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl12_wC_offset to congr_cl12_wC_offset + congr_cl12_wC_d'length-1), + scout => sov(congr_cl12_wC_offset to congr_cl12_wC_offset + congr_cl12_wC_d'length-1), + din => congr_cl12_wC_d, + dout => congr_cl12_wC_q); +-- Congruence Class 12 Way D Register +congr_cl12_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl12_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl12_wD_offset to congr_cl12_wD_offset + congr_cl12_wD_d'length-1), + scout => sov(congr_cl12_wD_offset to congr_cl12_wD_offset + congr_cl12_wD_d'length-1), + din => congr_cl12_wD_d, + dout => congr_cl12_wD_q); +-- Congruence Class 12 Way E Register +congr_cl12_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl12_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl12_wE_offset to congr_cl12_wE_offset + congr_cl12_wE_d'length-1), + scout => sov(congr_cl12_wE_offset to congr_cl12_wE_offset + congr_cl12_wE_d'length-1), + din => congr_cl12_wE_d, + dout => congr_cl12_wE_q); +-- Congruence Class 12 Way F Register +congr_cl12_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl12_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl12_wF_offset to congr_cl12_wF_offset + congr_cl12_wF_d'length-1), + scout => sov(congr_cl12_wF_offset to congr_cl12_wF_offset + congr_cl12_wF_d'length-1), + din => congr_cl12_wF_d, + dout => congr_cl12_wF_q); +-- Congruence Class 12 Way G Register +congr_cl12_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl12_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl12_wG_offset to congr_cl12_wG_offset + congr_cl12_wG_d'length-1), + scout => sov(congr_cl12_wG_offset to congr_cl12_wG_offset + congr_cl12_wG_d'length-1), + din => congr_cl12_wG_d, + dout => congr_cl12_wG_q); +-- Congruence Class 12 Way H Register +congr_cl12_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl12_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl12_wH_offset to congr_cl12_wH_offset + congr_cl12_wH_d'length-1), + scout => sov(congr_cl12_wH_offset to congr_cl12_wH_offset + congr_cl12_wH_d'length-1), + din => congr_cl12_wH_d, + dout => congr_cl12_wH_q); +-- Congruence Class 13 Way A Register +congr_cl13_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl13_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl13_wA_offset to congr_cl13_wA_offset + congr_cl13_wA_d'length-1), + scout => sov(congr_cl13_wA_offset to congr_cl13_wA_offset + congr_cl13_wA_d'length-1), + din => congr_cl13_wA_d, + dout => congr_cl13_wA_q); +-- Congruence Class 13 Way B Register +congr_cl13_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl13_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl13_wB_offset to congr_cl13_wB_offset + congr_cl13_wB_d'length-1), + scout => sov(congr_cl13_wB_offset to congr_cl13_wB_offset + congr_cl13_wB_d'length-1), + din => congr_cl13_wB_d, + dout => congr_cl13_wB_q); +-- Congruence Class 13 Way C Register +congr_cl13_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl13_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl13_wC_offset to congr_cl13_wC_offset + congr_cl13_wC_d'length-1), + scout => sov(congr_cl13_wC_offset to congr_cl13_wC_offset + congr_cl13_wC_d'length-1), + din => congr_cl13_wC_d, + dout => congr_cl13_wC_q); +-- Congruence Class 13 Way D Register +congr_cl13_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl13_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl13_wD_offset to congr_cl13_wD_offset + congr_cl13_wD_d'length-1), + scout => sov(congr_cl13_wD_offset to congr_cl13_wD_offset + congr_cl13_wD_d'length-1), + din => congr_cl13_wD_d, + dout => congr_cl13_wD_q); +-- Congruence Class 13 Way E Register +congr_cl13_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl13_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl13_wE_offset to congr_cl13_wE_offset + congr_cl13_wE_d'length-1), + scout => sov(congr_cl13_wE_offset to congr_cl13_wE_offset + congr_cl13_wE_d'length-1), + din => congr_cl13_wE_d, + dout => congr_cl13_wE_q); +-- Congruence Class 13 Way F Register +congr_cl13_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl13_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl13_wF_offset to congr_cl13_wF_offset + congr_cl13_wF_d'length-1), + scout => sov(congr_cl13_wF_offset to congr_cl13_wF_offset + congr_cl13_wF_d'length-1), + din => congr_cl13_wF_d, + dout => congr_cl13_wF_q); +-- Congruence Class 13 Way G Register +congr_cl13_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl13_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl13_wG_offset to congr_cl13_wG_offset + congr_cl13_wG_d'length-1), + scout => sov(congr_cl13_wG_offset to congr_cl13_wG_offset + congr_cl13_wG_d'length-1), + din => congr_cl13_wG_d, + dout => congr_cl13_wG_q); +-- Congruence Class 13 Way H Register +congr_cl13_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl13_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl13_wH_offset to congr_cl13_wH_offset + congr_cl13_wH_d'length-1), + scout => sov(congr_cl13_wH_offset to congr_cl13_wH_offset + congr_cl13_wH_d'length-1), + din => congr_cl13_wH_d, + dout => congr_cl13_wH_q); +-- Congruence Class 14 Way A Register +congr_cl14_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl14_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl14_wA_offset to congr_cl14_wA_offset + congr_cl14_wA_d'length-1), + scout => sov(congr_cl14_wA_offset to congr_cl14_wA_offset + congr_cl14_wA_d'length-1), + din => congr_cl14_wA_d, + dout => congr_cl14_wA_q); +-- Congruence Class 14 Way B Register +congr_cl14_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl14_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl14_wB_offset to congr_cl14_wB_offset + congr_cl14_wB_d'length-1), + scout => sov(congr_cl14_wB_offset to congr_cl14_wB_offset + congr_cl14_wB_d'length-1), + din => congr_cl14_wB_d, + dout => congr_cl14_wB_q); +-- Congruence Class 14 Way C Register +congr_cl14_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl14_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl14_wC_offset to congr_cl14_wC_offset + congr_cl14_wC_d'length-1), + scout => sov(congr_cl14_wC_offset to congr_cl14_wC_offset + congr_cl14_wC_d'length-1), + din => congr_cl14_wC_d, + dout => congr_cl14_wC_q); +-- Congruence Class 14 Way D Register +congr_cl14_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl14_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl14_wD_offset to congr_cl14_wD_offset + congr_cl14_wD_d'length-1), + scout => sov(congr_cl14_wD_offset to congr_cl14_wD_offset + congr_cl14_wD_d'length-1), + din => congr_cl14_wD_d, + dout => congr_cl14_wD_q); +-- Congruence Class 14 Way E Register +congr_cl14_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl14_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl14_wE_offset to congr_cl14_wE_offset + congr_cl14_wE_d'length-1), + scout => sov(congr_cl14_wE_offset to congr_cl14_wE_offset + congr_cl14_wE_d'length-1), + din => congr_cl14_wE_d, + dout => congr_cl14_wE_q); +-- Congruence Class 14 Way F Register +congr_cl14_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl14_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl14_wF_offset to congr_cl14_wF_offset + congr_cl14_wF_d'length-1), + scout => sov(congr_cl14_wF_offset to congr_cl14_wF_offset + congr_cl14_wF_d'length-1), + din => congr_cl14_wF_d, + dout => congr_cl14_wF_q); +-- Congruence Class 14 Way G Register +congr_cl14_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl14_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl14_wG_offset to congr_cl14_wG_offset + congr_cl14_wG_d'length-1), + scout => sov(congr_cl14_wG_offset to congr_cl14_wG_offset + congr_cl14_wG_d'length-1), + din => congr_cl14_wG_d, + dout => congr_cl14_wG_q); +-- Congruence Class 14 Way H Register +congr_cl14_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl14_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl14_wH_offset to congr_cl14_wH_offset + congr_cl14_wH_d'length-1), + scout => sov(congr_cl14_wH_offset to congr_cl14_wH_offset + congr_cl14_wH_d'length-1), + din => congr_cl14_wH_d, + dout => congr_cl14_wH_q); +-- Congruence Class 15 Way A Register +congr_cl15_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl15_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl15_wA_offset to congr_cl15_wA_offset + congr_cl15_wA_d'length-1), + scout => sov(congr_cl15_wA_offset to congr_cl15_wA_offset + congr_cl15_wA_d'length-1), + din => congr_cl15_wA_d, + dout => congr_cl15_wA_q); +-- Congruence Class 15 Way B Register +congr_cl15_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl15_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl15_wB_offset to congr_cl15_wB_offset + congr_cl15_wB_d'length-1), + scout => sov(congr_cl15_wB_offset to congr_cl15_wB_offset + congr_cl15_wB_d'length-1), + din => congr_cl15_wB_d, + dout => congr_cl15_wB_q); +-- Congruence Class 15 Way C Register +congr_cl15_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl15_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl15_wC_offset to congr_cl15_wC_offset + congr_cl15_wC_d'length-1), + scout => sov(congr_cl15_wC_offset to congr_cl15_wC_offset + congr_cl15_wC_d'length-1), + din => congr_cl15_wC_d, + dout => congr_cl15_wC_q); +-- Congruence Class 15 Way D Register +congr_cl15_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl15_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl15_wD_offset to congr_cl15_wD_offset + congr_cl15_wD_d'length-1), + scout => sov(congr_cl15_wD_offset to congr_cl15_wD_offset + congr_cl15_wD_d'length-1), + din => congr_cl15_wD_d, + dout => congr_cl15_wD_q); +-- Congruence Class 15 Way E Register +congr_cl15_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl15_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl15_wE_offset to congr_cl15_wE_offset + congr_cl15_wE_d'length-1), + scout => sov(congr_cl15_wE_offset to congr_cl15_wE_offset + congr_cl15_wE_d'length-1), + din => congr_cl15_wE_d, + dout => congr_cl15_wE_q); +-- Congruence Class 15 Way F Register +congr_cl15_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl15_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl15_wF_offset to congr_cl15_wF_offset + congr_cl15_wF_d'length-1), + scout => sov(congr_cl15_wF_offset to congr_cl15_wF_offset + congr_cl15_wF_d'length-1), + din => congr_cl15_wF_d, + dout => congr_cl15_wF_q); +-- Congruence Class 15 Way G Register +congr_cl15_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl15_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl15_wG_offset to congr_cl15_wG_offset + congr_cl15_wG_d'length-1), + scout => sov(congr_cl15_wG_offset to congr_cl15_wG_offset + congr_cl15_wG_d'length-1), + din => congr_cl15_wG_d, + dout => congr_cl15_wG_q); +-- Congruence Class 15 Way H Register +congr_cl15_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl15_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl15_wH_offset to congr_cl15_wH_offset + congr_cl15_wH_d'length-1), + scout => sov(congr_cl15_wH_offset to congr_cl15_wH_offset + congr_cl15_wH_d'length-1), + din => congr_cl15_wH_d, + dout => congr_cl15_wH_q); +-- Congruence Class 16 Way A Register +congr_cl16_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl16_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl16_wA_offset to congr_cl16_wA_offset + congr_cl16_wA_d'length-1), + scout => sov(congr_cl16_wA_offset to congr_cl16_wA_offset + congr_cl16_wA_d'length-1), + din => congr_cl16_wA_d, + dout => congr_cl16_wA_q); +-- Congruence Class 16 Way B Register +congr_cl16_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl16_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl16_wB_offset to congr_cl16_wB_offset + congr_cl16_wB_d'length-1), + scout => sov(congr_cl16_wB_offset to congr_cl16_wB_offset + congr_cl16_wB_d'length-1), + din => congr_cl16_wB_d, + dout => congr_cl16_wB_q); +-- Congruence Class 16 Way C Register +congr_cl16_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl16_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl16_wC_offset to congr_cl16_wC_offset + congr_cl16_wC_d'length-1), + scout => sov(congr_cl16_wC_offset to congr_cl16_wC_offset + congr_cl16_wC_d'length-1), + din => congr_cl16_wC_d, + dout => congr_cl16_wC_q); +-- Congruence Class 16 Way D Register +congr_cl16_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl16_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl16_wD_offset to congr_cl16_wD_offset + congr_cl16_wD_d'length-1), + scout => sov(congr_cl16_wD_offset to congr_cl16_wD_offset + congr_cl16_wD_d'length-1), + din => congr_cl16_wD_d, + dout => congr_cl16_wD_q); +-- Congruence Class 16 Way E Register +congr_cl16_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl16_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl16_wE_offset to congr_cl16_wE_offset + congr_cl16_wE_d'length-1), + scout => sov(congr_cl16_wE_offset to congr_cl16_wE_offset + congr_cl16_wE_d'length-1), + din => congr_cl16_wE_d, + dout => congr_cl16_wE_q); +-- Congruence Class 16 Way F Register +congr_cl16_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl16_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl16_wF_offset to congr_cl16_wF_offset + congr_cl16_wF_d'length-1), + scout => sov(congr_cl16_wF_offset to congr_cl16_wF_offset + congr_cl16_wF_d'length-1), + din => congr_cl16_wF_d, + dout => congr_cl16_wF_q); +-- Congruence Class 16 Way G Register +congr_cl16_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl16_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl16_wG_offset to congr_cl16_wG_offset + congr_cl16_wG_d'length-1), + scout => sov(congr_cl16_wG_offset to congr_cl16_wG_offset + congr_cl16_wG_d'length-1), + din => congr_cl16_wG_d, + dout => congr_cl16_wG_q); +-- Congruence Class 16 Way H Register +congr_cl16_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl16_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl16_wH_offset to congr_cl16_wH_offset + congr_cl16_wH_d'length-1), + scout => sov(congr_cl16_wH_offset to congr_cl16_wH_offset + congr_cl16_wH_d'length-1), + din => congr_cl16_wH_d, + dout => congr_cl16_wH_q); +-- Congruence Class 17 Way A Register +congr_cl17_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl17_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl17_wA_offset to congr_cl17_wA_offset + congr_cl17_wA_d'length-1), + scout => sov(congr_cl17_wA_offset to congr_cl17_wA_offset + congr_cl17_wA_d'length-1), + din => congr_cl17_wA_d, + dout => congr_cl17_wA_q); +-- Congruence Class 17 Way B Register +congr_cl17_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl17_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl17_wB_offset to congr_cl17_wB_offset + congr_cl17_wB_d'length-1), + scout => sov(congr_cl17_wB_offset to congr_cl17_wB_offset + congr_cl17_wB_d'length-1), + din => congr_cl17_wB_d, + dout => congr_cl17_wB_q); +-- Congruence Class 17 Way C Register +congr_cl17_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl17_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl17_wC_offset to congr_cl17_wC_offset + congr_cl17_wC_d'length-1), + scout => sov(congr_cl17_wC_offset to congr_cl17_wC_offset + congr_cl17_wC_d'length-1), + din => congr_cl17_wC_d, + dout => congr_cl17_wC_q); +-- Congruence Class 17 Way D Register +congr_cl17_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl17_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl17_wD_offset to congr_cl17_wD_offset + congr_cl17_wD_d'length-1), + scout => sov(congr_cl17_wD_offset to congr_cl17_wD_offset + congr_cl17_wD_d'length-1), + din => congr_cl17_wD_d, + dout => congr_cl17_wD_q); +-- Congruence Class 17 Way E Register +congr_cl17_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl17_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl17_wE_offset to congr_cl17_wE_offset + congr_cl17_wE_d'length-1), + scout => sov(congr_cl17_wE_offset to congr_cl17_wE_offset + congr_cl17_wE_d'length-1), + din => congr_cl17_wE_d, + dout => congr_cl17_wE_q); +-- Congruence Class 17 Way F Register +congr_cl17_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl17_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl17_wF_offset to congr_cl17_wF_offset + congr_cl17_wF_d'length-1), + scout => sov(congr_cl17_wF_offset to congr_cl17_wF_offset + congr_cl17_wF_d'length-1), + din => congr_cl17_wF_d, + dout => congr_cl17_wF_q); +-- Congruence Class 17 Way G Register +congr_cl17_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl17_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl17_wG_offset to congr_cl17_wG_offset + congr_cl17_wG_d'length-1), + scout => sov(congr_cl17_wG_offset to congr_cl17_wG_offset + congr_cl17_wG_d'length-1), + din => congr_cl17_wG_d, + dout => congr_cl17_wG_q); +-- Congruence Class 17 Way H Register +congr_cl17_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl17_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl17_wH_offset to congr_cl17_wH_offset + congr_cl17_wH_d'length-1), + scout => sov(congr_cl17_wH_offset to congr_cl17_wH_offset + congr_cl17_wH_d'length-1), + din => congr_cl17_wH_d, + dout => congr_cl17_wH_q); +-- Congruence Class 18 Way A Register +congr_cl18_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl18_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl18_wA_offset to congr_cl18_wA_offset + congr_cl18_wA_d'length-1), + scout => sov(congr_cl18_wA_offset to congr_cl18_wA_offset + congr_cl18_wA_d'length-1), + din => congr_cl18_wA_d, + dout => congr_cl18_wA_q); +-- Congruence Class 18 Way B Register +congr_cl18_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl18_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl18_wB_offset to congr_cl18_wB_offset + congr_cl18_wB_d'length-1), + scout => sov(congr_cl18_wB_offset to congr_cl18_wB_offset + congr_cl18_wB_d'length-1), + din => congr_cl18_wB_d, + dout => congr_cl18_wB_q); +-- Congruence Class 18 Way C Register +congr_cl18_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl18_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl18_wC_offset to congr_cl18_wC_offset + congr_cl18_wC_d'length-1), + scout => sov(congr_cl18_wC_offset to congr_cl18_wC_offset + congr_cl18_wC_d'length-1), + din => congr_cl18_wC_d, + dout => congr_cl18_wC_q); +-- Congruence Class 18 Way D Register +congr_cl18_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl18_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl18_wD_offset to congr_cl18_wD_offset + congr_cl18_wD_d'length-1), + scout => sov(congr_cl18_wD_offset to congr_cl18_wD_offset + congr_cl18_wD_d'length-1), + din => congr_cl18_wD_d, + dout => congr_cl18_wD_q); +-- Congruence Class 18 Way E Register +congr_cl18_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl18_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl18_wE_offset to congr_cl18_wE_offset + congr_cl18_wE_d'length-1), + scout => sov(congr_cl18_wE_offset to congr_cl18_wE_offset + congr_cl18_wE_d'length-1), + din => congr_cl18_wE_d, + dout => congr_cl18_wE_q); +-- Congruence Class 18 Way F Register +congr_cl18_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl18_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl18_wF_offset to congr_cl18_wF_offset + congr_cl18_wF_d'length-1), + scout => sov(congr_cl18_wF_offset to congr_cl18_wF_offset + congr_cl18_wF_d'length-1), + din => congr_cl18_wF_d, + dout => congr_cl18_wF_q); +-- Congruence Class 18 Way G Register +congr_cl18_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl18_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl18_wG_offset to congr_cl18_wG_offset + congr_cl18_wG_d'length-1), + scout => sov(congr_cl18_wG_offset to congr_cl18_wG_offset + congr_cl18_wG_d'length-1), + din => congr_cl18_wG_d, + dout => congr_cl18_wG_q); +-- Congruence Class 18 Way H Register +congr_cl18_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl18_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl18_wH_offset to congr_cl18_wH_offset + congr_cl18_wH_d'length-1), + scout => sov(congr_cl18_wH_offset to congr_cl18_wH_offset + congr_cl18_wH_d'length-1), + din => congr_cl18_wH_d, + dout => congr_cl18_wH_q); +-- Congruence Class 19 Way A Register +congr_cl19_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl19_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl19_wA_offset to congr_cl19_wA_offset + congr_cl19_wA_d'length-1), + scout => sov(congr_cl19_wA_offset to congr_cl19_wA_offset + congr_cl19_wA_d'length-1), + din => congr_cl19_wA_d, + dout => congr_cl19_wA_q); +-- Congruence Class 19 Way B Register +congr_cl19_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl19_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl19_wB_offset to congr_cl19_wB_offset + congr_cl19_wB_d'length-1), + scout => sov(congr_cl19_wB_offset to congr_cl19_wB_offset + congr_cl19_wB_d'length-1), + din => congr_cl19_wB_d, + dout => congr_cl19_wB_q); +-- Congruence Class 19 Way C Register +congr_cl19_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl19_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl19_wC_offset to congr_cl19_wC_offset + congr_cl19_wC_d'length-1), + scout => sov(congr_cl19_wC_offset to congr_cl19_wC_offset + congr_cl19_wC_d'length-1), + din => congr_cl19_wC_d, + dout => congr_cl19_wC_q); +-- Congruence Class 19 Way D Register +congr_cl19_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl19_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl19_wD_offset to congr_cl19_wD_offset + congr_cl19_wD_d'length-1), + scout => sov(congr_cl19_wD_offset to congr_cl19_wD_offset + congr_cl19_wD_d'length-1), + din => congr_cl19_wD_d, + dout => congr_cl19_wD_q); +-- Congruence Class 19 Way E Register +congr_cl19_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl19_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl19_wE_offset to congr_cl19_wE_offset + congr_cl19_wE_d'length-1), + scout => sov(congr_cl19_wE_offset to congr_cl19_wE_offset + congr_cl19_wE_d'length-1), + din => congr_cl19_wE_d, + dout => congr_cl19_wE_q); +-- Congruence Class 19 Way F Register +congr_cl19_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl19_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl19_wF_offset to congr_cl19_wF_offset + congr_cl19_wF_d'length-1), + scout => sov(congr_cl19_wF_offset to congr_cl19_wF_offset + congr_cl19_wF_d'length-1), + din => congr_cl19_wF_d, + dout => congr_cl19_wF_q); +-- Congruence Class 19 Way G Register +congr_cl19_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl19_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl19_wG_offset to congr_cl19_wG_offset + congr_cl19_wG_d'length-1), + scout => sov(congr_cl19_wG_offset to congr_cl19_wG_offset + congr_cl19_wG_d'length-1), + din => congr_cl19_wG_d, + dout => congr_cl19_wG_q); +-- Congruence Class 19 Way H Register +congr_cl19_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl19_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl19_wH_offset to congr_cl19_wH_offset + congr_cl19_wH_d'length-1), + scout => sov(congr_cl19_wH_offset to congr_cl19_wH_offset + congr_cl19_wH_d'length-1), + din => congr_cl19_wH_d, + dout => congr_cl19_wH_q); +-- Congruence Class 20 Way A Register +congr_cl20_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl20_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl20_wA_offset to congr_cl20_wA_offset + congr_cl20_wA_d'length-1), + scout => sov(congr_cl20_wA_offset to congr_cl20_wA_offset + congr_cl20_wA_d'length-1), + din => congr_cl20_wA_d, + dout => congr_cl20_wA_q); +-- Congruence Class 20 Way B Register +congr_cl20_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl20_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl20_wB_offset to congr_cl20_wB_offset + congr_cl20_wB_d'length-1), + scout => sov(congr_cl20_wB_offset to congr_cl20_wB_offset + congr_cl20_wB_d'length-1), + din => congr_cl20_wB_d, + dout => congr_cl20_wB_q); +-- Congruence Class 20 Way C Register +congr_cl20_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl20_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl20_wC_offset to congr_cl20_wC_offset + congr_cl20_wC_d'length-1), + scout => sov(congr_cl20_wC_offset to congr_cl20_wC_offset + congr_cl20_wC_d'length-1), + din => congr_cl20_wC_d, + dout => congr_cl20_wC_q); +-- Congruence Class 20 Way D Register +congr_cl20_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl20_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl20_wD_offset to congr_cl20_wD_offset + congr_cl20_wD_d'length-1), + scout => sov(congr_cl20_wD_offset to congr_cl20_wD_offset + congr_cl20_wD_d'length-1), + din => congr_cl20_wD_d, + dout => congr_cl20_wD_q); +-- Congruence Class 20 Way E Register +congr_cl20_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl20_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl20_wE_offset to congr_cl20_wE_offset + congr_cl20_wE_d'length-1), + scout => sov(congr_cl20_wE_offset to congr_cl20_wE_offset + congr_cl20_wE_d'length-1), + din => congr_cl20_wE_d, + dout => congr_cl20_wE_q); +-- Congruence Class 20 Way F Register +congr_cl20_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl20_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl20_wF_offset to congr_cl20_wF_offset + congr_cl20_wF_d'length-1), + scout => sov(congr_cl20_wF_offset to congr_cl20_wF_offset + congr_cl20_wF_d'length-1), + din => congr_cl20_wF_d, + dout => congr_cl20_wF_q); +-- Congruence Class 20 Way G Register +congr_cl20_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl20_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl20_wG_offset to congr_cl20_wG_offset + congr_cl20_wG_d'length-1), + scout => sov(congr_cl20_wG_offset to congr_cl20_wG_offset + congr_cl20_wG_d'length-1), + din => congr_cl20_wG_d, + dout => congr_cl20_wG_q); +-- Congruence Class 20 Way H Register +congr_cl20_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl20_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl20_wH_offset to congr_cl20_wH_offset + congr_cl20_wH_d'length-1), + scout => sov(congr_cl20_wH_offset to congr_cl20_wH_offset + congr_cl20_wH_d'length-1), + din => congr_cl20_wH_d, + dout => congr_cl20_wH_q); +-- Congruence Class 21 Way A Register +congr_cl21_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl21_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl21_wA_offset to congr_cl21_wA_offset + congr_cl21_wA_d'length-1), + scout => sov(congr_cl21_wA_offset to congr_cl21_wA_offset + congr_cl21_wA_d'length-1), + din => congr_cl21_wA_d, + dout => congr_cl21_wA_q); +-- Congruence Class 21 Way B Register +congr_cl21_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl21_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl21_wB_offset to congr_cl21_wB_offset + congr_cl21_wB_d'length-1), + scout => sov(congr_cl21_wB_offset to congr_cl21_wB_offset + congr_cl21_wB_d'length-1), + din => congr_cl21_wB_d, + dout => congr_cl21_wB_q); +-- Congruence Class 21 Way C Register +congr_cl21_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl21_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl21_wC_offset to congr_cl21_wC_offset + congr_cl21_wC_d'length-1), + scout => sov(congr_cl21_wC_offset to congr_cl21_wC_offset + congr_cl21_wC_d'length-1), + din => congr_cl21_wC_d, + dout => congr_cl21_wC_q); +-- Congruence Class 21 Way D Register +congr_cl21_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl21_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl21_wD_offset to congr_cl21_wD_offset + congr_cl21_wD_d'length-1), + scout => sov(congr_cl21_wD_offset to congr_cl21_wD_offset + congr_cl21_wD_d'length-1), + din => congr_cl21_wD_d, + dout => congr_cl21_wD_q); +-- Congruence Class 21 Way E Register +congr_cl21_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl21_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl21_wE_offset to congr_cl21_wE_offset + congr_cl21_wE_d'length-1), + scout => sov(congr_cl21_wE_offset to congr_cl21_wE_offset + congr_cl21_wE_d'length-1), + din => congr_cl21_wE_d, + dout => congr_cl21_wE_q); +-- Congruence Class 21 Way F Register +congr_cl21_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl21_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl21_wF_offset to congr_cl21_wF_offset + congr_cl21_wF_d'length-1), + scout => sov(congr_cl21_wF_offset to congr_cl21_wF_offset + congr_cl21_wF_d'length-1), + din => congr_cl21_wF_d, + dout => congr_cl21_wF_q); +-- Congruence Class 21 Way G Register +congr_cl21_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl21_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl21_wG_offset to congr_cl21_wG_offset + congr_cl21_wG_d'length-1), + scout => sov(congr_cl21_wG_offset to congr_cl21_wG_offset + congr_cl21_wG_d'length-1), + din => congr_cl21_wG_d, + dout => congr_cl21_wG_q); +-- Congruence Class 21 Way H Register +congr_cl21_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl21_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl21_wH_offset to congr_cl21_wH_offset + congr_cl21_wH_d'length-1), + scout => sov(congr_cl21_wH_offset to congr_cl21_wH_offset + congr_cl21_wH_d'length-1), + din => congr_cl21_wH_d, + dout => congr_cl21_wH_q); +-- Congruence Class 22 Way A Register +congr_cl22_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl22_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl22_wA_offset to congr_cl22_wA_offset + congr_cl22_wA_d'length-1), + scout => sov(congr_cl22_wA_offset to congr_cl22_wA_offset + congr_cl22_wA_d'length-1), + din => congr_cl22_wA_d, + dout => congr_cl22_wA_q); +-- Congruence Class 22 Way B Register +congr_cl22_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl22_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl22_wB_offset to congr_cl22_wB_offset + congr_cl22_wB_d'length-1), + scout => sov(congr_cl22_wB_offset to congr_cl22_wB_offset + congr_cl22_wB_d'length-1), + din => congr_cl22_wB_d, + dout => congr_cl22_wB_q); +-- Congruence Class 22 Way C Register +congr_cl22_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl22_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl22_wC_offset to congr_cl22_wC_offset + congr_cl22_wC_d'length-1), + scout => sov(congr_cl22_wC_offset to congr_cl22_wC_offset + congr_cl22_wC_d'length-1), + din => congr_cl22_wC_d, + dout => congr_cl22_wC_q); +-- Congruence Class 22 Way D Register +congr_cl22_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl22_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl22_wD_offset to congr_cl22_wD_offset + congr_cl22_wD_d'length-1), + scout => sov(congr_cl22_wD_offset to congr_cl22_wD_offset + congr_cl22_wD_d'length-1), + din => congr_cl22_wD_d, + dout => congr_cl22_wD_q); +-- Congruence Class 22 Way E Register +congr_cl22_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl22_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl22_wE_offset to congr_cl22_wE_offset + congr_cl22_wE_d'length-1), + scout => sov(congr_cl22_wE_offset to congr_cl22_wE_offset + congr_cl22_wE_d'length-1), + din => congr_cl22_wE_d, + dout => congr_cl22_wE_q); +-- Congruence Class 22 Way F Register +congr_cl22_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl22_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl22_wF_offset to congr_cl22_wF_offset + congr_cl22_wF_d'length-1), + scout => sov(congr_cl22_wF_offset to congr_cl22_wF_offset + congr_cl22_wF_d'length-1), + din => congr_cl22_wF_d, + dout => congr_cl22_wF_q); +-- Congruence Class 22 Way G Register +congr_cl22_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl22_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl22_wG_offset to congr_cl22_wG_offset + congr_cl22_wG_d'length-1), + scout => sov(congr_cl22_wG_offset to congr_cl22_wG_offset + congr_cl22_wG_d'length-1), + din => congr_cl22_wG_d, + dout => congr_cl22_wG_q); +-- Congruence Class 22 Way H Register +congr_cl22_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl22_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl22_wH_offset to congr_cl22_wH_offset + congr_cl22_wH_d'length-1), + scout => sov(congr_cl22_wH_offset to congr_cl22_wH_offset + congr_cl22_wH_d'length-1), + din => congr_cl22_wH_d, + dout => congr_cl22_wH_q); +-- Congruence Class 23 Way A Register +congr_cl23_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl23_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl23_wA_offset to congr_cl23_wA_offset + congr_cl23_wA_d'length-1), + scout => sov(congr_cl23_wA_offset to congr_cl23_wA_offset + congr_cl23_wA_d'length-1), + din => congr_cl23_wA_d, + dout => congr_cl23_wA_q); +-- Congruence Class 23 Way B Register +congr_cl23_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl23_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl23_wB_offset to congr_cl23_wB_offset + congr_cl23_wB_d'length-1), + scout => sov(congr_cl23_wB_offset to congr_cl23_wB_offset + congr_cl23_wB_d'length-1), + din => congr_cl23_wB_d, + dout => congr_cl23_wB_q); +-- Congruence Class 23 Way C Register +congr_cl23_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl23_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl23_wC_offset to congr_cl23_wC_offset + congr_cl23_wC_d'length-1), + scout => sov(congr_cl23_wC_offset to congr_cl23_wC_offset + congr_cl23_wC_d'length-1), + din => congr_cl23_wC_d, + dout => congr_cl23_wC_q); +-- Congruence Class 23 Way D Register +congr_cl23_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl23_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl23_wD_offset to congr_cl23_wD_offset + congr_cl23_wD_d'length-1), + scout => sov(congr_cl23_wD_offset to congr_cl23_wD_offset + congr_cl23_wD_d'length-1), + din => congr_cl23_wD_d, + dout => congr_cl23_wD_q); +-- Congruence Class 23 Way E Register +congr_cl23_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl23_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl23_wE_offset to congr_cl23_wE_offset + congr_cl23_wE_d'length-1), + scout => sov(congr_cl23_wE_offset to congr_cl23_wE_offset + congr_cl23_wE_d'length-1), + din => congr_cl23_wE_d, + dout => congr_cl23_wE_q); +-- Congruence Class 23 Way F Register +congr_cl23_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl23_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl23_wF_offset to congr_cl23_wF_offset + congr_cl23_wF_d'length-1), + scout => sov(congr_cl23_wF_offset to congr_cl23_wF_offset + congr_cl23_wF_d'length-1), + din => congr_cl23_wF_d, + dout => congr_cl23_wF_q); +-- Congruence Class 23 Way G Register +congr_cl23_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl23_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl23_wG_offset to congr_cl23_wG_offset + congr_cl23_wG_d'length-1), + scout => sov(congr_cl23_wG_offset to congr_cl23_wG_offset + congr_cl23_wG_d'length-1), + din => congr_cl23_wG_d, + dout => congr_cl23_wG_q); +-- Congruence Class 23 Way H Register +congr_cl23_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl23_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl23_wH_offset to congr_cl23_wH_offset + congr_cl23_wH_d'length-1), + scout => sov(congr_cl23_wH_offset to congr_cl23_wH_offset + congr_cl23_wH_d'length-1), + din => congr_cl23_wH_d, + dout => congr_cl23_wH_q); +-- Congruence Class 24 Way A Register +congr_cl24_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl24_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl24_wA_offset to congr_cl24_wA_offset + congr_cl24_wA_d'length-1), + scout => sov(congr_cl24_wA_offset to congr_cl24_wA_offset + congr_cl24_wA_d'length-1), + din => congr_cl24_wA_d, + dout => congr_cl24_wA_q); +-- Congruence Class 24 Way B Register +congr_cl24_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl24_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl24_wB_offset to congr_cl24_wB_offset + congr_cl24_wB_d'length-1), + scout => sov(congr_cl24_wB_offset to congr_cl24_wB_offset + congr_cl24_wB_d'length-1), + din => congr_cl24_wB_d, + dout => congr_cl24_wB_q); +-- Congruence Class 24 Way C Register +congr_cl24_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl24_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl24_wC_offset to congr_cl24_wC_offset + congr_cl24_wC_d'length-1), + scout => sov(congr_cl24_wC_offset to congr_cl24_wC_offset + congr_cl24_wC_d'length-1), + din => congr_cl24_wC_d, + dout => congr_cl24_wC_q); +-- Congruence Class 24 Way D Register +congr_cl24_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl24_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl24_wD_offset to congr_cl24_wD_offset + congr_cl24_wD_d'length-1), + scout => sov(congr_cl24_wD_offset to congr_cl24_wD_offset + congr_cl24_wD_d'length-1), + din => congr_cl24_wD_d, + dout => congr_cl24_wD_q); +-- Congruence Class 24 Way E Register +congr_cl24_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl24_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl24_wE_offset to congr_cl24_wE_offset + congr_cl24_wE_d'length-1), + scout => sov(congr_cl24_wE_offset to congr_cl24_wE_offset + congr_cl24_wE_d'length-1), + din => congr_cl24_wE_d, + dout => congr_cl24_wE_q); +-- Congruence Class 24 Way F Register +congr_cl24_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl24_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl24_wF_offset to congr_cl24_wF_offset + congr_cl24_wF_d'length-1), + scout => sov(congr_cl24_wF_offset to congr_cl24_wF_offset + congr_cl24_wF_d'length-1), + din => congr_cl24_wF_d, + dout => congr_cl24_wF_q); +-- Congruence Class 24 Way G Register +congr_cl24_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl24_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl24_wG_offset to congr_cl24_wG_offset + congr_cl24_wG_d'length-1), + scout => sov(congr_cl24_wG_offset to congr_cl24_wG_offset + congr_cl24_wG_d'length-1), + din => congr_cl24_wG_d, + dout => congr_cl24_wG_q); +-- Congruence Class 24 Way H Register +congr_cl24_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl24_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl24_wH_offset to congr_cl24_wH_offset + congr_cl24_wH_d'length-1), + scout => sov(congr_cl24_wH_offset to congr_cl24_wH_offset + congr_cl24_wH_d'length-1), + din => congr_cl24_wH_d, + dout => congr_cl24_wH_q); +-- Congruence Class 25 Way A Register +congr_cl25_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl25_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl25_wA_offset to congr_cl25_wA_offset + congr_cl25_wA_d'length-1), + scout => sov(congr_cl25_wA_offset to congr_cl25_wA_offset + congr_cl25_wA_d'length-1), + din => congr_cl25_wA_d, + dout => congr_cl25_wA_q); +-- Congruence Class 25 Way B Register +congr_cl25_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl25_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl25_wB_offset to congr_cl25_wB_offset + congr_cl25_wB_d'length-1), + scout => sov(congr_cl25_wB_offset to congr_cl25_wB_offset + congr_cl25_wB_d'length-1), + din => congr_cl25_wB_d, + dout => congr_cl25_wB_q); +-- Congruence Class 25 Way C Register +congr_cl25_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl25_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl25_wC_offset to congr_cl25_wC_offset + congr_cl25_wC_d'length-1), + scout => sov(congr_cl25_wC_offset to congr_cl25_wC_offset + congr_cl25_wC_d'length-1), + din => congr_cl25_wC_d, + dout => congr_cl25_wC_q); +-- Congruence Class 25 Way D Register +congr_cl25_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl25_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl25_wD_offset to congr_cl25_wD_offset + congr_cl25_wD_d'length-1), + scout => sov(congr_cl25_wD_offset to congr_cl25_wD_offset + congr_cl25_wD_d'length-1), + din => congr_cl25_wD_d, + dout => congr_cl25_wD_q); +-- Congruence Class 25 Way E Register +congr_cl25_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl25_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl25_wE_offset to congr_cl25_wE_offset + congr_cl25_wE_d'length-1), + scout => sov(congr_cl25_wE_offset to congr_cl25_wE_offset + congr_cl25_wE_d'length-1), + din => congr_cl25_wE_d, + dout => congr_cl25_wE_q); +-- Congruence Class 25 Way F Register +congr_cl25_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl25_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl25_wF_offset to congr_cl25_wF_offset + congr_cl25_wF_d'length-1), + scout => sov(congr_cl25_wF_offset to congr_cl25_wF_offset + congr_cl25_wF_d'length-1), + din => congr_cl25_wF_d, + dout => congr_cl25_wF_q); +-- Congruence Class 25 Way G Register +congr_cl25_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl25_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl25_wG_offset to congr_cl25_wG_offset + congr_cl25_wG_d'length-1), + scout => sov(congr_cl25_wG_offset to congr_cl25_wG_offset + congr_cl25_wG_d'length-1), + din => congr_cl25_wG_d, + dout => congr_cl25_wG_q); +-- Congruence Class 25 Way H Register +congr_cl25_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl25_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl25_wH_offset to congr_cl25_wH_offset + congr_cl25_wH_d'length-1), + scout => sov(congr_cl25_wH_offset to congr_cl25_wH_offset + congr_cl25_wH_d'length-1), + din => congr_cl25_wH_d, + dout => congr_cl25_wH_q); +-- Congruence Class 26 Way A Register +congr_cl26_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl26_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl26_wA_offset to congr_cl26_wA_offset + congr_cl26_wA_d'length-1), + scout => sov(congr_cl26_wA_offset to congr_cl26_wA_offset + congr_cl26_wA_d'length-1), + din => congr_cl26_wA_d, + dout => congr_cl26_wA_q); +-- Congruence Class 26 Way B Register +congr_cl26_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl26_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl26_wB_offset to congr_cl26_wB_offset + congr_cl26_wB_d'length-1), + scout => sov(congr_cl26_wB_offset to congr_cl26_wB_offset + congr_cl26_wB_d'length-1), + din => congr_cl26_wB_d, + dout => congr_cl26_wB_q); +-- Congruence Class 26 Way C Register +congr_cl26_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl26_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl26_wC_offset to congr_cl26_wC_offset + congr_cl26_wC_d'length-1), + scout => sov(congr_cl26_wC_offset to congr_cl26_wC_offset + congr_cl26_wC_d'length-1), + din => congr_cl26_wC_d, + dout => congr_cl26_wC_q); +-- Congruence Class 26 Way D Register +congr_cl26_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl26_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl26_wD_offset to congr_cl26_wD_offset + congr_cl26_wD_d'length-1), + scout => sov(congr_cl26_wD_offset to congr_cl26_wD_offset + congr_cl26_wD_d'length-1), + din => congr_cl26_wD_d, + dout => congr_cl26_wD_q); +-- Congruence Class 26 Way E Register +congr_cl26_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl26_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl26_wE_offset to congr_cl26_wE_offset + congr_cl26_wE_d'length-1), + scout => sov(congr_cl26_wE_offset to congr_cl26_wE_offset + congr_cl26_wE_d'length-1), + din => congr_cl26_wE_d, + dout => congr_cl26_wE_q); +-- Congruence Class 26 Way F Register +congr_cl26_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl26_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl26_wF_offset to congr_cl26_wF_offset + congr_cl26_wF_d'length-1), + scout => sov(congr_cl26_wF_offset to congr_cl26_wF_offset + congr_cl26_wF_d'length-1), + din => congr_cl26_wF_d, + dout => congr_cl26_wF_q); +-- Congruence Class 26 Way G Register +congr_cl26_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl26_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl26_wG_offset to congr_cl26_wG_offset + congr_cl26_wG_d'length-1), + scout => sov(congr_cl26_wG_offset to congr_cl26_wG_offset + congr_cl26_wG_d'length-1), + din => congr_cl26_wG_d, + dout => congr_cl26_wG_q); +-- Congruence Class 26 Way H Register +congr_cl26_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl26_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl26_wH_offset to congr_cl26_wH_offset + congr_cl26_wH_d'length-1), + scout => sov(congr_cl26_wH_offset to congr_cl26_wH_offset + congr_cl26_wH_d'length-1), + din => congr_cl26_wH_d, + dout => congr_cl26_wH_q); +-- Congruence Class 27 Way A Register +congr_cl27_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl27_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl27_wA_offset to congr_cl27_wA_offset + congr_cl27_wA_d'length-1), + scout => sov(congr_cl27_wA_offset to congr_cl27_wA_offset + congr_cl27_wA_d'length-1), + din => congr_cl27_wA_d, + dout => congr_cl27_wA_q); +-- Congruence Class 27 Way B Register +congr_cl27_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl27_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl27_wB_offset to congr_cl27_wB_offset + congr_cl27_wB_d'length-1), + scout => sov(congr_cl27_wB_offset to congr_cl27_wB_offset + congr_cl27_wB_d'length-1), + din => congr_cl27_wB_d, + dout => congr_cl27_wB_q); +-- Congruence Class 27 Way C Register +congr_cl27_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl27_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl27_wC_offset to congr_cl27_wC_offset + congr_cl27_wC_d'length-1), + scout => sov(congr_cl27_wC_offset to congr_cl27_wC_offset + congr_cl27_wC_d'length-1), + din => congr_cl27_wC_d, + dout => congr_cl27_wC_q); +-- Congruence Class 27 Way D Register +congr_cl27_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl27_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl27_wD_offset to congr_cl27_wD_offset + congr_cl27_wD_d'length-1), + scout => sov(congr_cl27_wD_offset to congr_cl27_wD_offset + congr_cl27_wD_d'length-1), + din => congr_cl27_wD_d, + dout => congr_cl27_wD_q); +-- Congruence Class 27 Way E Register +congr_cl27_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl27_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl27_wE_offset to congr_cl27_wE_offset + congr_cl27_wE_d'length-1), + scout => sov(congr_cl27_wE_offset to congr_cl27_wE_offset + congr_cl27_wE_d'length-1), + din => congr_cl27_wE_d, + dout => congr_cl27_wE_q); +-- Congruence Class 27 Way F Register +congr_cl27_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl27_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl27_wF_offset to congr_cl27_wF_offset + congr_cl27_wF_d'length-1), + scout => sov(congr_cl27_wF_offset to congr_cl27_wF_offset + congr_cl27_wF_d'length-1), + din => congr_cl27_wF_d, + dout => congr_cl27_wF_q); +-- Congruence Class 27 Way G Register +congr_cl27_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl27_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl27_wG_offset to congr_cl27_wG_offset + congr_cl27_wG_d'length-1), + scout => sov(congr_cl27_wG_offset to congr_cl27_wG_offset + congr_cl27_wG_d'length-1), + din => congr_cl27_wG_d, + dout => congr_cl27_wG_q); +-- Congruence Class 27 Way H Register +congr_cl27_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl27_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl27_wH_offset to congr_cl27_wH_offset + congr_cl27_wH_d'length-1), + scout => sov(congr_cl27_wH_offset to congr_cl27_wH_offset + congr_cl27_wH_d'length-1), + din => congr_cl27_wH_d, + dout => congr_cl27_wH_q); +-- Congruence Class 28 Way A Register +congr_cl28_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl28_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl28_wA_offset to congr_cl28_wA_offset + congr_cl28_wA_d'length-1), + scout => sov(congr_cl28_wA_offset to congr_cl28_wA_offset + congr_cl28_wA_d'length-1), + din => congr_cl28_wA_d, + dout => congr_cl28_wA_q); +-- Congruence Class 28 Way B Register +congr_cl28_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl28_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl28_wB_offset to congr_cl28_wB_offset + congr_cl28_wB_d'length-1), + scout => sov(congr_cl28_wB_offset to congr_cl28_wB_offset + congr_cl28_wB_d'length-1), + din => congr_cl28_wB_d, + dout => congr_cl28_wB_q); +-- Congruence Class 28 Way C Register +congr_cl28_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl28_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl28_wC_offset to congr_cl28_wC_offset + congr_cl28_wC_d'length-1), + scout => sov(congr_cl28_wC_offset to congr_cl28_wC_offset + congr_cl28_wC_d'length-1), + din => congr_cl28_wC_d, + dout => congr_cl28_wC_q); +-- Congruence Class 28 Way D Register +congr_cl28_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl28_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl28_wD_offset to congr_cl28_wD_offset + congr_cl28_wD_d'length-1), + scout => sov(congr_cl28_wD_offset to congr_cl28_wD_offset + congr_cl28_wD_d'length-1), + din => congr_cl28_wD_d, + dout => congr_cl28_wD_q); +-- Congruence Class 28 Way E Register +congr_cl28_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl28_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl28_wE_offset to congr_cl28_wE_offset + congr_cl28_wE_d'length-1), + scout => sov(congr_cl28_wE_offset to congr_cl28_wE_offset + congr_cl28_wE_d'length-1), + din => congr_cl28_wE_d, + dout => congr_cl28_wE_q); +-- Congruence Class 28 Way F Register +congr_cl28_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl28_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl28_wF_offset to congr_cl28_wF_offset + congr_cl28_wF_d'length-1), + scout => sov(congr_cl28_wF_offset to congr_cl28_wF_offset + congr_cl28_wF_d'length-1), + din => congr_cl28_wF_d, + dout => congr_cl28_wF_q); +-- Congruence Class 28 Way G Register +congr_cl28_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl28_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl28_wG_offset to congr_cl28_wG_offset + congr_cl28_wG_d'length-1), + scout => sov(congr_cl28_wG_offset to congr_cl28_wG_offset + congr_cl28_wG_d'length-1), + din => congr_cl28_wG_d, + dout => congr_cl28_wG_q); +-- Congruence Class 28 Way H Register +congr_cl28_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl28_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl28_wH_offset to congr_cl28_wH_offset + congr_cl28_wH_d'length-1), + scout => sov(congr_cl28_wH_offset to congr_cl28_wH_offset + congr_cl28_wH_d'length-1), + din => congr_cl28_wH_d, + dout => congr_cl28_wH_q); +-- Congruence Class 29 Way A Register +congr_cl29_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl29_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl29_wA_offset to congr_cl29_wA_offset + congr_cl29_wA_d'length-1), + scout => sov(congr_cl29_wA_offset to congr_cl29_wA_offset + congr_cl29_wA_d'length-1), + din => congr_cl29_wA_d, + dout => congr_cl29_wA_q); +-- Congruence Class 29 Way B Register +congr_cl29_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl29_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl29_wB_offset to congr_cl29_wB_offset + congr_cl29_wB_d'length-1), + scout => sov(congr_cl29_wB_offset to congr_cl29_wB_offset + congr_cl29_wB_d'length-1), + din => congr_cl29_wB_d, + dout => congr_cl29_wB_q); +-- Congruence Class 29 Way C Register +congr_cl29_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl29_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl29_wC_offset to congr_cl29_wC_offset + congr_cl29_wC_d'length-1), + scout => sov(congr_cl29_wC_offset to congr_cl29_wC_offset + congr_cl29_wC_d'length-1), + din => congr_cl29_wC_d, + dout => congr_cl29_wC_q); +-- Congruence Class 29 Way D Register +congr_cl29_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl29_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl29_wD_offset to congr_cl29_wD_offset + congr_cl29_wD_d'length-1), + scout => sov(congr_cl29_wD_offset to congr_cl29_wD_offset + congr_cl29_wD_d'length-1), + din => congr_cl29_wD_d, + dout => congr_cl29_wD_q); +-- Congruence Class 29 Way E Register +congr_cl29_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl29_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl29_wE_offset to congr_cl29_wE_offset + congr_cl29_wE_d'length-1), + scout => sov(congr_cl29_wE_offset to congr_cl29_wE_offset + congr_cl29_wE_d'length-1), + din => congr_cl29_wE_d, + dout => congr_cl29_wE_q); +-- Congruence Class 29 Way F Register +congr_cl29_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl29_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl29_wF_offset to congr_cl29_wF_offset + congr_cl29_wF_d'length-1), + scout => sov(congr_cl29_wF_offset to congr_cl29_wF_offset + congr_cl29_wF_d'length-1), + din => congr_cl29_wF_d, + dout => congr_cl29_wF_q); +-- Congruence Class 29 Way G Register +congr_cl29_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl29_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl29_wG_offset to congr_cl29_wG_offset + congr_cl29_wG_d'length-1), + scout => sov(congr_cl29_wG_offset to congr_cl29_wG_offset + congr_cl29_wG_d'length-1), + din => congr_cl29_wG_d, + dout => congr_cl29_wG_q); +-- Congruence Class 29 Way H Register +congr_cl29_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl29_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl29_wH_offset to congr_cl29_wH_offset + congr_cl29_wH_d'length-1), + scout => sov(congr_cl29_wH_offset to congr_cl29_wH_offset + congr_cl29_wH_d'length-1), + din => congr_cl29_wH_d, + dout => congr_cl29_wH_q); +-- Congruence Class 30 Way A Register +congr_cl30_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl30_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl30_wA_offset to congr_cl30_wA_offset + congr_cl30_wA_d'length-1), + scout => sov(congr_cl30_wA_offset to congr_cl30_wA_offset + congr_cl30_wA_d'length-1), + din => congr_cl30_wA_d, + dout => congr_cl30_wA_q); +-- Congruence Class 30 Way B Register +congr_cl30_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl30_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl30_wB_offset to congr_cl30_wB_offset + congr_cl30_wB_d'length-1), + scout => sov(congr_cl30_wB_offset to congr_cl30_wB_offset + congr_cl30_wB_d'length-1), + din => congr_cl30_wB_d, + dout => congr_cl30_wB_q); +-- Congruence Class 30 Way C Register +congr_cl30_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl30_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl30_wC_offset to congr_cl30_wC_offset + congr_cl30_wC_d'length-1), + scout => sov(congr_cl30_wC_offset to congr_cl30_wC_offset + congr_cl30_wC_d'length-1), + din => congr_cl30_wC_d, + dout => congr_cl30_wC_q); +-- Congruence Class 30 Way D Register +congr_cl30_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl30_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl30_wD_offset to congr_cl30_wD_offset + congr_cl30_wD_d'length-1), + scout => sov(congr_cl30_wD_offset to congr_cl30_wD_offset + congr_cl30_wD_d'length-1), + din => congr_cl30_wD_d, + dout => congr_cl30_wD_q); +-- Congruence Class 30 Way E Register +congr_cl30_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl30_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl30_wE_offset to congr_cl30_wE_offset + congr_cl30_wE_d'length-1), + scout => sov(congr_cl30_wE_offset to congr_cl30_wE_offset + congr_cl30_wE_d'length-1), + din => congr_cl30_wE_d, + dout => congr_cl30_wE_q); +-- Congruence Class 30 Way F Register +congr_cl30_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl30_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl30_wF_offset to congr_cl30_wF_offset + congr_cl30_wF_d'length-1), + scout => sov(congr_cl30_wF_offset to congr_cl30_wF_offset + congr_cl30_wF_d'length-1), + din => congr_cl30_wF_d, + dout => congr_cl30_wF_q); +-- Congruence Class 30 Way G Register +congr_cl30_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl30_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl30_wG_offset to congr_cl30_wG_offset + congr_cl30_wG_d'length-1), + scout => sov(congr_cl30_wG_offset to congr_cl30_wG_offset + congr_cl30_wG_d'length-1), + din => congr_cl30_wG_d, + dout => congr_cl30_wG_q); +-- Congruence Class 30 Way H Register +congr_cl30_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl30_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl30_wH_offset to congr_cl30_wH_offset + congr_cl30_wH_d'length-1), + scout => sov(congr_cl30_wH_offset to congr_cl30_wH_offset + congr_cl30_wH_d'length-1), + din => congr_cl30_wH_d, + dout => congr_cl30_wH_q); +-- Congruence Class 31 Way A Register +congr_cl31_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl31_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl31_wA_offset to congr_cl31_wA_offset + congr_cl31_wA_d'length-1), + scout => sov(congr_cl31_wA_offset to congr_cl31_wA_offset + congr_cl31_wA_d'length-1), + din => congr_cl31_wA_d, + dout => congr_cl31_wA_q); +-- Congruence Class 31 Way B Register +congr_cl31_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl31_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl31_wB_offset to congr_cl31_wB_offset + congr_cl31_wB_d'length-1), + scout => sov(congr_cl31_wB_offset to congr_cl31_wB_offset + congr_cl31_wB_d'length-1), + din => congr_cl31_wB_d, + dout => congr_cl31_wB_q); +-- Congruence Class 31 Way C Register +congr_cl31_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl31_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl31_wC_offset to congr_cl31_wC_offset + congr_cl31_wC_d'length-1), + scout => sov(congr_cl31_wC_offset to congr_cl31_wC_offset + congr_cl31_wC_d'length-1), + din => congr_cl31_wC_d, + dout => congr_cl31_wC_q); +-- Congruence Class 31 Way D Register +congr_cl31_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl31_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl31_wD_offset to congr_cl31_wD_offset + congr_cl31_wD_d'length-1), + scout => sov(congr_cl31_wD_offset to congr_cl31_wD_offset + congr_cl31_wD_d'length-1), + din => congr_cl31_wD_d, + dout => congr_cl31_wD_q); +-- Congruence Class 31 Way E Register +congr_cl31_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl31_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl31_wE_offset to congr_cl31_wE_offset + congr_cl31_wE_d'length-1), + scout => sov(congr_cl31_wE_offset to congr_cl31_wE_offset + congr_cl31_wE_d'length-1), + din => congr_cl31_wE_d, + dout => congr_cl31_wE_q); +-- Congruence Class 31 Way F Register +congr_cl31_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl31_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl31_wF_offset to congr_cl31_wF_offset + congr_cl31_wF_d'length-1), + scout => sov(congr_cl31_wF_offset to congr_cl31_wF_offset + congr_cl31_wF_d'length-1), + din => congr_cl31_wF_d, + dout => congr_cl31_wF_q); +-- Congruence Class 31 Way G Register +congr_cl31_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl31_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl31_wG_offset to congr_cl31_wG_offset + congr_cl31_wG_d'length-1), + scout => sov(congr_cl31_wG_offset to congr_cl31_wG_offset + congr_cl31_wG_d'length-1), + din => congr_cl31_wG_d, + dout => congr_cl31_wG_q); +-- Congruence Class 31 Way H Register +congr_cl31_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl31_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl31_wH_offset to congr_cl31_wH_offset + congr_cl31_wH_d'length-1), + scout => sov(congr_cl31_wH_offset to congr_cl31_wH_offset + congr_cl31_wH_d'length-1), + din => congr_cl31_wH_d, + dout => congr_cl31_wH_q); +-- Congruence Class 32 Way A Register +congr_cl32_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl32_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl32_wA_offset to congr_cl32_wA_offset + congr_cl32_wA_d'length-1), + scout => sov(congr_cl32_wA_offset to congr_cl32_wA_offset + congr_cl32_wA_d'length-1), + din => congr_cl32_wA_d, + dout => congr_cl32_wA_q); +-- Congruence Class 32 Way B Register +congr_cl32_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl32_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl32_wB_offset to congr_cl32_wB_offset + congr_cl32_wB_d'length-1), + scout => sov(congr_cl32_wB_offset to congr_cl32_wB_offset + congr_cl32_wB_d'length-1), + din => congr_cl32_wB_d, + dout => congr_cl32_wB_q); +-- Congruence Class 32 Way C Register +congr_cl32_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl32_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl32_wC_offset to congr_cl32_wC_offset + congr_cl32_wC_d'length-1), + scout => sov(congr_cl32_wC_offset to congr_cl32_wC_offset + congr_cl32_wC_d'length-1), + din => congr_cl32_wC_d, + dout => congr_cl32_wC_q); +-- Congruence Class 32 Way D Register +congr_cl32_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl32_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl32_wD_offset to congr_cl32_wD_offset + congr_cl32_wD_d'length-1), + scout => sov(congr_cl32_wD_offset to congr_cl32_wD_offset + congr_cl32_wD_d'length-1), + din => congr_cl32_wD_d, + dout => congr_cl32_wD_q); +-- Congruence Class 32 Way E Register +congr_cl32_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl32_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl32_wE_offset to congr_cl32_wE_offset + congr_cl32_wE_d'length-1), + scout => sov(congr_cl32_wE_offset to congr_cl32_wE_offset + congr_cl32_wE_d'length-1), + din => congr_cl32_wE_d, + dout => congr_cl32_wE_q); +-- Congruence Class 32 Way F Register +congr_cl32_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl32_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl32_wF_offset to congr_cl32_wF_offset + congr_cl32_wF_d'length-1), + scout => sov(congr_cl32_wF_offset to congr_cl32_wF_offset + congr_cl32_wF_d'length-1), + din => congr_cl32_wF_d, + dout => congr_cl32_wF_q); +-- Congruence Class 32 Way G Register +congr_cl32_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl32_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl32_wG_offset to congr_cl32_wG_offset + congr_cl32_wG_d'length-1), + scout => sov(congr_cl32_wG_offset to congr_cl32_wG_offset + congr_cl32_wG_d'length-1), + din => congr_cl32_wG_d, + dout => congr_cl32_wG_q); +-- Congruence Class 32 Way H Register +congr_cl32_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl32_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl32_wH_offset to congr_cl32_wH_offset + congr_cl32_wH_d'length-1), + scout => sov(congr_cl32_wH_offset to congr_cl32_wH_offset + congr_cl32_wH_d'length-1), + din => congr_cl32_wH_d, + dout => congr_cl32_wH_q); +-- Congruence Class 33 Way A Register +congr_cl33_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl33_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl33_wA_offset to congr_cl33_wA_offset + congr_cl33_wA_d'length-1), + scout => sov(congr_cl33_wA_offset to congr_cl33_wA_offset + congr_cl33_wA_d'length-1), + din => congr_cl33_wA_d, + dout => congr_cl33_wA_q); +-- Congruence Class 33 Way B Register +congr_cl33_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl33_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl33_wB_offset to congr_cl33_wB_offset + congr_cl33_wB_d'length-1), + scout => sov(congr_cl33_wB_offset to congr_cl33_wB_offset + congr_cl33_wB_d'length-1), + din => congr_cl33_wB_d, + dout => congr_cl33_wB_q); +-- Congruence Class 33 Way C Register +congr_cl33_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl33_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl33_wC_offset to congr_cl33_wC_offset + congr_cl33_wC_d'length-1), + scout => sov(congr_cl33_wC_offset to congr_cl33_wC_offset + congr_cl33_wC_d'length-1), + din => congr_cl33_wC_d, + dout => congr_cl33_wC_q); +-- Congruence Class 33 Way D Register +congr_cl33_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl33_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl33_wD_offset to congr_cl33_wD_offset + congr_cl33_wD_d'length-1), + scout => sov(congr_cl33_wD_offset to congr_cl33_wD_offset + congr_cl33_wD_d'length-1), + din => congr_cl33_wD_d, + dout => congr_cl33_wD_q); +-- Congruence Class 33 Way E Register +congr_cl33_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl33_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl33_wE_offset to congr_cl33_wE_offset + congr_cl33_wE_d'length-1), + scout => sov(congr_cl33_wE_offset to congr_cl33_wE_offset + congr_cl33_wE_d'length-1), + din => congr_cl33_wE_d, + dout => congr_cl33_wE_q); +-- Congruence Class 33 Way F Register +congr_cl33_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl33_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl33_wF_offset to congr_cl33_wF_offset + congr_cl33_wF_d'length-1), + scout => sov(congr_cl33_wF_offset to congr_cl33_wF_offset + congr_cl33_wF_d'length-1), + din => congr_cl33_wF_d, + dout => congr_cl33_wF_q); +-- Congruence Class 33 Way G Register +congr_cl33_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl33_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl33_wG_offset to congr_cl33_wG_offset + congr_cl33_wG_d'length-1), + scout => sov(congr_cl33_wG_offset to congr_cl33_wG_offset + congr_cl33_wG_d'length-1), + din => congr_cl33_wG_d, + dout => congr_cl33_wG_q); +-- Congruence Class 33 Way H Register +congr_cl33_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl33_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl33_wH_offset to congr_cl33_wH_offset + congr_cl33_wH_d'length-1), + scout => sov(congr_cl33_wH_offset to congr_cl33_wH_offset + congr_cl33_wH_d'length-1), + din => congr_cl33_wH_d, + dout => congr_cl33_wH_q); +-- Congruence Class 34 Way A Register +congr_cl34_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl34_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl34_wA_offset to congr_cl34_wA_offset + congr_cl34_wA_d'length-1), + scout => sov(congr_cl34_wA_offset to congr_cl34_wA_offset + congr_cl34_wA_d'length-1), + din => congr_cl34_wA_d, + dout => congr_cl34_wA_q); +-- Congruence Class 34 Way B Register +congr_cl34_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl34_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl34_wB_offset to congr_cl34_wB_offset + congr_cl34_wB_d'length-1), + scout => sov(congr_cl34_wB_offset to congr_cl34_wB_offset + congr_cl34_wB_d'length-1), + din => congr_cl34_wB_d, + dout => congr_cl34_wB_q); +-- Congruence Class 34 Way C Register +congr_cl34_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl34_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl34_wC_offset to congr_cl34_wC_offset + congr_cl34_wC_d'length-1), + scout => sov(congr_cl34_wC_offset to congr_cl34_wC_offset + congr_cl34_wC_d'length-1), + din => congr_cl34_wC_d, + dout => congr_cl34_wC_q); +-- Congruence Class 34 Way D Register +congr_cl34_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl34_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl34_wD_offset to congr_cl34_wD_offset + congr_cl34_wD_d'length-1), + scout => sov(congr_cl34_wD_offset to congr_cl34_wD_offset + congr_cl34_wD_d'length-1), + din => congr_cl34_wD_d, + dout => congr_cl34_wD_q); +-- Congruence Class 34 Way E Register +congr_cl34_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl34_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl34_wE_offset to congr_cl34_wE_offset + congr_cl34_wE_d'length-1), + scout => sov(congr_cl34_wE_offset to congr_cl34_wE_offset + congr_cl34_wE_d'length-1), + din => congr_cl34_wE_d, + dout => congr_cl34_wE_q); +-- Congruence Class 34 Way F Register +congr_cl34_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl34_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl34_wF_offset to congr_cl34_wF_offset + congr_cl34_wF_d'length-1), + scout => sov(congr_cl34_wF_offset to congr_cl34_wF_offset + congr_cl34_wF_d'length-1), + din => congr_cl34_wF_d, + dout => congr_cl34_wF_q); +-- Congruence Class 34 Way G Register +congr_cl34_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl34_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl34_wG_offset to congr_cl34_wG_offset + congr_cl34_wG_d'length-1), + scout => sov(congr_cl34_wG_offset to congr_cl34_wG_offset + congr_cl34_wG_d'length-1), + din => congr_cl34_wG_d, + dout => congr_cl34_wG_q); +-- Congruence Class 34 Way H Register +congr_cl34_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl34_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl34_wH_offset to congr_cl34_wH_offset + congr_cl34_wH_d'length-1), + scout => sov(congr_cl34_wH_offset to congr_cl34_wH_offset + congr_cl34_wH_d'length-1), + din => congr_cl34_wH_d, + dout => congr_cl34_wH_q); +-- Congruence Class 35 Way A Register +congr_cl35_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl35_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl35_wA_offset to congr_cl35_wA_offset + congr_cl35_wA_d'length-1), + scout => sov(congr_cl35_wA_offset to congr_cl35_wA_offset + congr_cl35_wA_d'length-1), + din => congr_cl35_wA_d, + dout => congr_cl35_wA_q); +-- Congruence Class 35 Way B Register +congr_cl35_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl35_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl35_wB_offset to congr_cl35_wB_offset + congr_cl35_wB_d'length-1), + scout => sov(congr_cl35_wB_offset to congr_cl35_wB_offset + congr_cl35_wB_d'length-1), + din => congr_cl35_wB_d, + dout => congr_cl35_wB_q); +-- Congruence Class 35 Way C Register +congr_cl35_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl35_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl35_wC_offset to congr_cl35_wC_offset + congr_cl35_wC_d'length-1), + scout => sov(congr_cl35_wC_offset to congr_cl35_wC_offset + congr_cl35_wC_d'length-1), + din => congr_cl35_wC_d, + dout => congr_cl35_wC_q); +-- Congruence Class 35 Way D Register +congr_cl35_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl35_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl35_wD_offset to congr_cl35_wD_offset + congr_cl35_wD_d'length-1), + scout => sov(congr_cl35_wD_offset to congr_cl35_wD_offset + congr_cl35_wD_d'length-1), + din => congr_cl35_wD_d, + dout => congr_cl35_wD_q); +-- Congruence Class 35 Way E Register +congr_cl35_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl35_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl35_wE_offset to congr_cl35_wE_offset + congr_cl35_wE_d'length-1), + scout => sov(congr_cl35_wE_offset to congr_cl35_wE_offset + congr_cl35_wE_d'length-1), + din => congr_cl35_wE_d, + dout => congr_cl35_wE_q); +-- Congruence Class 35 Way F Register +congr_cl35_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl35_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl35_wF_offset to congr_cl35_wF_offset + congr_cl35_wF_d'length-1), + scout => sov(congr_cl35_wF_offset to congr_cl35_wF_offset + congr_cl35_wF_d'length-1), + din => congr_cl35_wF_d, + dout => congr_cl35_wF_q); +-- Congruence Class 35 Way G Register +congr_cl35_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl35_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl35_wG_offset to congr_cl35_wG_offset + congr_cl35_wG_d'length-1), + scout => sov(congr_cl35_wG_offset to congr_cl35_wG_offset + congr_cl35_wG_d'length-1), + din => congr_cl35_wG_d, + dout => congr_cl35_wG_q); +-- Congruence Class 35 Way H Register +congr_cl35_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl35_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl35_wH_offset to congr_cl35_wH_offset + congr_cl35_wH_d'length-1), + scout => sov(congr_cl35_wH_offset to congr_cl35_wH_offset + congr_cl35_wH_d'length-1), + din => congr_cl35_wH_d, + dout => congr_cl35_wH_q); +-- Congruence Class 36 Way A Register +congr_cl36_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl36_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl36_wA_offset to congr_cl36_wA_offset + congr_cl36_wA_d'length-1), + scout => sov(congr_cl36_wA_offset to congr_cl36_wA_offset + congr_cl36_wA_d'length-1), + din => congr_cl36_wA_d, + dout => congr_cl36_wA_q); +-- Congruence Class 36 Way B Register +congr_cl36_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl36_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl36_wB_offset to congr_cl36_wB_offset + congr_cl36_wB_d'length-1), + scout => sov(congr_cl36_wB_offset to congr_cl36_wB_offset + congr_cl36_wB_d'length-1), + din => congr_cl36_wB_d, + dout => congr_cl36_wB_q); +-- Congruence Class 36 Way C Register +congr_cl36_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl36_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl36_wC_offset to congr_cl36_wC_offset + congr_cl36_wC_d'length-1), + scout => sov(congr_cl36_wC_offset to congr_cl36_wC_offset + congr_cl36_wC_d'length-1), + din => congr_cl36_wC_d, + dout => congr_cl36_wC_q); +-- Congruence Class 36 Way D Register +congr_cl36_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl36_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl36_wD_offset to congr_cl36_wD_offset + congr_cl36_wD_d'length-1), + scout => sov(congr_cl36_wD_offset to congr_cl36_wD_offset + congr_cl36_wD_d'length-1), + din => congr_cl36_wD_d, + dout => congr_cl36_wD_q); +-- Congruence Class 36 Way E Register +congr_cl36_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl36_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl36_wE_offset to congr_cl36_wE_offset + congr_cl36_wE_d'length-1), + scout => sov(congr_cl36_wE_offset to congr_cl36_wE_offset + congr_cl36_wE_d'length-1), + din => congr_cl36_wE_d, + dout => congr_cl36_wE_q); +-- Congruence Class 36 Way F Register +congr_cl36_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl36_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl36_wF_offset to congr_cl36_wF_offset + congr_cl36_wF_d'length-1), + scout => sov(congr_cl36_wF_offset to congr_cl36_wF_offset + congr_cl36_wF_d'length-1), + din => congr_cl36_wF_d, + dout => congr_cl36_wF_q); +-- Congruence Class 36 Way G Register +congr_cl36_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl36_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl36_wG_offset to congr_cl36_wG_offset + congr_cl36_wG_d'length-1), + scout => sov(congr_cl36_wG_offset to congr_cl36_wG_offset + congr_cl36_wG_d'length-1), + din => congr_cl36_wG_d, + dout => congr_cl36_wG_q); +-- Congruence Class 36 Way H Register +congr_cl36_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl36_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl36_wH_offset to congr_cl36_wH_offset + congr_cl36_wH_d'length-1), + scout => sov(congr_cl36_wH_offset to congr_cl36_wH_offset + congr_cl36_wH_d'length-1), + din => congr_cl36_wH_d, + dout => congr_cl36_wH_q); +-- Congruence Class 37 Way A Register +congr_cl37_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl37_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl37_wA_offset to congr_cl37_wA_offset + congr_cl37_wA_d'length-1), + scout => sov(congr_cl37_wA_offset to congr_cl37_wA_offset + congr_cl37_wA_d'length-1), + din => congr_cl37_wA_d, + dout => congr_cl37_wA_q); +-- Congruence Class 37 Way B Register +congr_cl37_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl37_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl37_wB_offset to congr_cl37_wB_offset + congr_cl37_wB_d'length-1), + scout => sov(congr_cl37_wB_offset to congr_cl37_wB_offset + congr_cl37_wB_d'length-1), + din => congr_cl37_wB_d, + dout => congr_cl37_wB_q); +-- Congruence Class 37 Way C Register +congr_cl37_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl37_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl37_wC_offset to congr_cl37_wC_offset + congr_cl37_wC_d'length-1), + scout => sov(congr_cl37_wC_offset to congr_cl37_wC_offset + congr_cl37_wC_d'length-1), + din => congr_cl37_wC_d, + dout => congr_cl37_wC_q); +-- Congruence Class 37 Way D Register +congr_cl37_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl37_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl37_wD_offset to congr_cl37_wD_offset + congr_cl37_wD_d'length-1), + scout => sov(congr_cl37_wD_offset to congr_cl37_wD_offset + congr_cl37_wD_d'length-1), + din => congr_cl37_wD_d, + dout => congr_cl37_wD_q); +-- Congruence Class 37 Way E Register +congr_cl37_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl37_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl37_wE_offset to congr_cl37_wE_offset + congr_cl37_wE_d'length-1), + scout => sov(congr_cl37_wE_offset to congr_cl37_wE_offset + congr_cl37_wE_d'length-1), + din => congr_cl37_wE_d, + dout => congr_cl37_wE_q); +-- Congruence Class 37 Way F Register +congr_cl37_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl37_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl37_wF_offset to congr_cl37_wF_offset + congr_cl37_wF_d'length-1), + scout => sov(congr_cl37_wF_offset to congr_cl37_wF_offset + congr_cl37_wF_d'length-1), + din => congr_cl37_wF_d, + dout => congr_cl37_wF_q); +-- Congruence Class 37 Way G Register +congr_cl37_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl37_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl37_wG_offset to congr_cl37_wG_offset + congr_cl37_wG_d'length-1), + scout => sov(congr_cl37_wG_offset to congr_cl37_wG_offset + congr_cl37_wG_d'length-1), + din => congr_cl37_wG_d, + dout => congr_cl37_wG_q); +-- Congruence Class 37 Way H Register +congr_cl37_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl37_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl37_wH_offset to congr_cl37_wH_offset + congr_cl37_wH_d'length-1), + scout => sov(congr_cl37_wH_offset to congr_cl37_wH_offset + congr_cl37_wH_d'length-1), + din => congr_cl37_wH_d, + dout => congr_cl37_wH_q); +-- Congruence Class 38 Way A Register +congr_cl38_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl38_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl38_wA_offset to congr_cl38_wA_offset + congr_cl38_wA_d'length-1), + scout => sov(congr_cl38_wA_offset to congr_cl38_wA_offset + congr_cl38_wA_d'length-1), + din => congr_cl38_wA_d, + dout => congr_cl38_wA_q); +-- Congruence Class 38 Way B Register +congr_cl38_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl38_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl38_wB_offset to congr_cl38_wB_offset + congr_cl38_wB_d'length-1), + scout => sov(congr_cl38_wB_offset to congr_cl38_wB_offset + congr_cl38_wB_d'length-1), + din => congr_cl38_wB_d, + dout => congr_cl38_wB_q); +-- Congruence Class 38 Way C Register +congr_cl38_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl38_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl38_wC_offset to congr_cl38_wC_offset + congr_cl38_wC_d'length-1), + scout => sov(congr_cl38_wC_offset to congr_cl38_wC_offset + congr_cl38_wC_d'length-1), + din => congr_cl38_wC_d, + dout => congr_cl38_wC_q); +-- Congruence Class 38 Way D Register +congr_cl38_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl38_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl38_wD_offset to congr_cl38_wD_offset + congr_cl38_wD_d'length-1), + scout => sov(congr_cl38_wD_offset to congr_cl38_wD_offset + congr_cl38_wD_d'length-1), + din => congr_cl38_wD_d, + dout => congr_cl38_wD_q); +-- Congruence Class 38 Way E Register +congr_cl38_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl38_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl38_wE_offset to congr_cl38_wE_offset + congr_cl38_wE_d'length-1), + scout => sov(congr_cl38_wE_offset to congr_cl38_wE_offset + congr_cl38_wE_d'length-1), + din => congr_cl38_wE_d, + dout => congr_cl38_wE_q); +-- Congruence Class 38 Way F Register +congr_cl38_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl38_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl38_wF_offset to congr_cl38_wF_offset + congr_cl38_wF_d'length-1), + scout => sov(congr_cl38_wF_offset to congr_cl38_wF_offset + congr_cl38_wF_d'length-1), + din => congr_cl38_wF_d, + dout => congr_cl38_wF_q); +-- Congruence Class 38 Way G Register +congr_cl38_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl38_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl38_wG_offset to congr_cl38_wG_offset + congr_cl38_wG_d'length-1), + scout => sov(congr_cl38_wG_offset to congr_cl38_wG_offset + congr_cl38_wG_d'length-1), + din => congr_cl38_wG_d, + dout => congr_cl38_wG_q); +-- Congruence Class 38 Way H Register +congr_cl38_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl38_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl38_wH_offset to congr_cl38_wH_offset + congr_cl38_wH_d'length-1), + scout => sov(congr_cl38_wH_offset to congr_cl38_wH_offset + congr_cl38_wH_d'length-1), + din => congr_cl38_wH_d, + dout => congr_cl38_wH_q); +-- Congruence Class 39 Way A Register +congr_cl39_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl39_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl39_wA_offset to congr_cl39_wA_offset + congr_cl39_wA_d'length-1), + scout => sov(congr_cl39_wA_offset to congr_cl39_wA_offset + congr_cl39_wA_d'length-1), + din => congr_cl39_wA_d, + dout => congr_cl39_wA_q); +-- Congruence Class 39 Way B Register +congr_cl39_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl39_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl39_wB_offset to congr_cl39_wB_offset + congr_cl39_wB_d'length-1), + scout => sov(congr_cl39_wB_offset to congr_cl39_wB_offset + congr_cl39_wB_d'length-1), + din => congr_cl39_wB_d, + dout => congr_cl39_wB_q); +-- Congruence Class 39 Way C Register +congr_cl39_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl39_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl39_wC_offset to congr_cl39_wC_offset + congr_cl39_wC_d'length-1), + scout => sov(congr_cl39_wC_offset to congr_cl39_wC_offset + congr_cl39_wC_d'length-1), + din => congr_cl39_wC_d, + dout => congr_cl39_wC_q); +-- Congruence Class 39 Way D Register +congr_cl39_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl39_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl39_wD_offset to congr_cl39_wD_offset + congr_cl39_wD_d'length-1), + scout => sov(congr_cl39_wD_offset to congr_cl39_wD_offset + congr_cl39_wD_d'length-1), + din => congr_cl39_wD_d, + dout => congr_cl39_wD_q); +-- Congruence Class 39 Way E Register +congr_cl39_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl39_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl39_wE_offset to congr_cl39_wE_offset + congr_cl39_wE_d'length-1), + scout => sov(congr_cl39_wE_offset to congr_cl39_wE_offset + congr_cl39_wE_d'length-1), + din => congr_cl39_wE_d, + dout => congr_cl39_wE_q); +-- Congruence Class 39 Way F Register +congr_cl39_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl39_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl39_wF_offset to congr_cl39_wF_offset + congr_cl39_wF_d'length-1), + scout => sov(congr_cl39_wF_offset to congr_cl39_wF_offset + congr_cl39_wF_d'length-1), + din => congr_cl39_wF_d, + dout => congr_cl39_wF_q); +-- Congruence Class 39 Way G Register +congr_cl39_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl39_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl39_wG_offset to congr_cl39_wG_offset + congr_cl39_wG_d'length-1), + scout => sov(congr_cl39_wG_offset to congr_cl39_wG_offset + congr_cl39_wG_d'length-1), + din => congr_cl39_wG_d, + dout => congr_cl39_wG_q); +-- Congruence Class 39 Way H Register +congr_cl39_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl39_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl39_wH_offset to congr_cl39_wH_offset + congr_cl39_wH_d'length-1), + scout => sov(congr_cl39_wH_offset to congr_cl39_wH_offset + congr_cl39_wH_d'length-1), + din => congr_cl39_wH_d, + dout => congr_cl39_wH_q); +-- Congruence Class 40 Way A Register +congr_cl40_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl40_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl40_wA_offset to congr_cl40_wA_offset + congr_cl40_wA_d'length-1), + scout => sov(congr_cl40_wA_offset to congr_cl40_wA_offset + congr_cl40_wA_d'length-1), + din => congr_cl40_wA_d, + dout => congr_cl40_wA_q); +-- Congruence Class 40 Way B Register +congr_cl40_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl40_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl40_wB_offset to congr_cl40_wB_offset + congr_cl40_wB_d'length-1), + scout => sov(congr_cl40_wB_offset to congr_cl40_wB_offset + congr_cl40_wB_d'length-1), + din => congr_cl40_wB_d, + dout => congr_cl40_wB_q); +-- Congruence Class 40 Way C Register +congr_cl40_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl40_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl40_wC_offset to congr_cl40_wC_offset + congr_cl40_wC_d'length-1), + scout => sov(congr_cl40_wC_offset to congr_cl40_wC_offset + congr_cl40_wC_d'length-1), + din => congr_cl40_wC_d, + dout => congr_cl40_wC_q); +-- Congruence Class 40 Way D Register +congr_cl40_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl40_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl40_wD_offset to congr_cl40_wD_offset + congr_cl40_wD_d'length-1), + scout => sov(congr_cl40_wD_offset to congr_cl40_wD_offset + congr_cl40_wD_d'length-1), + din => congr_cl40_wD_d, + dout => congr_cl40_wD_q); +-- Congruence Class 40 Way E Register +congr_cl40_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl40_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl40_wE_offset to congr_cl40_wE_offset + congr_cl40_wE_d'length-1), + scout => sov(congr_cl40_wE_offset to congr_cl40_wE_offset + congr_cl40_wE_d'length-1), + din => congr_cl40_wE_d, + dout => congr_cl40_wE_q); +-- Congruence Class 40 Way F Register +congr_cl40_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl40_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl40_wF_offset to congr_cl40_wF_offset + congr_cl40_wF_d'length-1), + scout => sov(congr_cl40_wF_offset to congr_cl40_wF_offset + congr_cl40_wF_d'length-1), + din => congr_cl40_wF_d, + dout => congr_cl40_wF_q); +-- Congruence Class 40 Way G Register +congr_cl40_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl40_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl40_wG_offset to congr_cl40_wG_offset + congr_cl40_wG_d'length-1), + scout => sov(congr_cl40_wG_offset to congr_cl40_wG_offset + congr_cl40_wG_d'length-1), + din => congr_cl40_wG_d, + dout => congr_cl40_wG_q); +-- Congruence Class 40 Way H Register +congr_cl40_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl40_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl40_wH_offset to congr_cl40_wH_offset + congr_cl40_wH_d'length-1), + scout => sov(congr_cl40_wH_offset to congr_cl40_wH_offset + congr_cl40_wH_d'length-1), + din => congr_cl40_wH_d, + dout => congr_cl40_wH_q); +-- Congruence Class 41 Way A Register +congr_cl41_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl41_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl41_wA_offset to congr_cl41_wA_offset + congr_cl41_wA_d'length-1), + scout => sov(congr_cl41_wA_offset to congr_cl41_wA_offset + congr_cl41_wA_d'length-1), + din => congr_cl41_wA_d, + dout => congr_cl41_wA_q); +-- Congruence Class 41 Way B Register +congr_cl41_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl41_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl41_wB_offset to congr_cl41_wB_offset + congr_cl41_wB_d'length-1), + scout => sov(congr_cl41_wB_offset to congr_cl41_wB_offset + congr_cl41_wB_d'length-1), + din => congr_cl41_wB_d, + dout => congr_cl41_wB_q); +-- Congruence Class 41 Way C Register +congr_cl41_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl41_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl41_wC_offset to congr_cl41_wC_offset + congr_cl41_wC_d'length-1), + scout => sov(congr_cl41_wC_offset to congr_cl41_wC_offset + congr_cl41_wC_d'length-1), + din => congr_cl41_wC_d, + dout => congr_cl41_wC_q); +-- Congruence Class 41 Way D Register +congr_cl41_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl41_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl41_wD_offset to congr_cl41_wD_offset + congr_cl41_wD_d'length-1), + scout => sov(congr_cl41_wD_offset to congr_cl41_wD_offset + congr_cl41_wD_d'length-1), + din => congr_cl41_wD_d, + dout => congr_cl41_wD_q); +-- Congruence Class 41 Way E Register +congr_cl41_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl41_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl41_wE_offset to congr_cl41_wE_offset + congr_cl41_wE_d'length-1), + scout => sov(congr_cl41_wE_offset to congr_cl41_wE_offset + congr_cl41_wE_d'length-1), + din => congr_cl41_wE_d, + dout => congr_cl41_wE_q); +-- Congruence Class 41 Way F Register +congr_cl41_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl41_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl41_wF_offset to congr_cl41_wF_offset + congr_cl41_wF_d'length-1), + scout => sov(congr_cl41_wF_offset to congr_cl41_wF_offset + congr_cl41_wF_d'length-1), + din => congr_cl41_wF_d, + dout => congr_cl41_wF_q); +-- Congruence Class 41 Way G Register +congr_cl41_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl41_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl41_wG_offset to congr_cl41_wG_offset + congr_cl41_wG_d'length-1), + scout => sov(congr_cl41_wG_offset to congr_cl41_wG_offset + congr_cl41_wG_d'length-1), + din => congr_cl41_wG_d, + dout => congr_cl41_wG_q); +-- Congruence Class 41 Way H Register +congr_cl41_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl41_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl41_wH_offset to congr_cl41_wH_offset + congr_cl41_wH_d'length-1), + scout => sov(congr_cl41_wH_offset to congr_cl41_wH_offset + congr_cl41_wH_d'length-1), + din => congr_cl41_wH_d, + dout => congr_cl41_wH_q); +-- Congruence Class 42 Way A Register +congr_cl42_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl42_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl42_wA_offset to congr_cl42_wA_offset + congr_cl42_wA_d'length-1), + scout => sov(congr_cl42_wA_offset to congr_cl42_wA_offset + congr_cl42_wA_d'length-1), + din => congr_cl42_wA_d, + dout => congr_cl42_wA_q); +-- Congruence Class 42 Way B Register +congr_cl42_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl42_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl42_wB_offset to congr_cl42_wB_offset + congr_cl42_wB_d'length-1), + scout => sov(congr_cl42_wB_offset to congr_cl42_wB_offset + congr_cl42_wB_d'length-1), + din => congr_cl42_wB_d, + dout => congr_cl42_wB_q); +-- Congruence Class 42 Way C Register +congr_cl42_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl42_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl42_wC_offset to congr_cl42_wC_offset + congr_cl42_wC_d'length-1), + scout => sov(congr_cl42_wC_offset to congr_cl42_wC_offset + congr_cl42_wC_d'length-1), + din => congr_cl42_wC_d, + dout => congr_cl42_wC_q); +-- Congruence Class 42 Way D Register +congr_cl42_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl42_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl42_wD_offset to congr_cl42_wD_offset + congr_cl42_wD_d'length-1), + scout => sov(congr_cl42_wD_offset to congr_cl42_wD_offset + congr_cl42_wD_d'length-1), + din => congr_cl42_wD_d, + dout => congr_cl42_wD_q); +-- Congruence Class 42 Way E Register +congr_cl42_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl42_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl42_wE_offset to congr_cl42_wE_offset + congr_cl42_wE_d'length-1), + scout => sov(congr_cl42_wE_offset to congr_cl42_wE_offset + congr_cl42_wE_d'length-1), + din => congr_cl42_wE_d, + dout => congr_cl42_wE_q); +-- Congruence Class 42 Way F Register +congr_cl42_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl42_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl42_wF_offset to congr_cl42_wF_offset + congr_cl42_wF_d'length-1), + scout => sov(congr_cl42_wF_offset to congr_cl42_wF_offset + congr_cl42_wF_d'length-1), + din => congr_cl42_wF_d, + dout => congr_cl42_wF_q); +-- Congruence Class 42 Way G Register +congr_cl42_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl42_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl42_wG_offset to congr_cl42_wG_offset + congr_cl42_wG_d'length-1), + scout => sov(congr_cl42_wG_offset to congr_cl42_wG_offset + congr_cl42_wG_d'length-1), + din => congr_cl42_wG_d, + dout => congr_cl42_wG_q); +-- Congruence Class 42 Way H Register +congr_cl42_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl42_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl42_wH_offset to congr_cl42_wH_offset + congr_cl42_wH_d'length-1), + scout => sov(congr_cl42_wH_offset to congr_cl42_wH_offset + congr_cl42_wH_d'length-1), + din => congr_cl42_wH_d, + dout => congr_cl42_wH_q); +-- Congruence Class 43 Way A Register +congr_cl43_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl43_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl43_wA_offset to congr_cl43_wA_offset + congr_cl43_wA_d'length-1), + scout => sov(congr_cl43_wA_offset to congr_cl43_wA_offset + congr_cl43_wA_d'length-1), + din => congr_cl43_wA_d, + dout => congr_cl43_wA_q); +-- Congruence Class 43 Way B Register +congr_cl43_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl43_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl43_wB_offset to congr_cl43_wB_offset + congr_cl43_wB_d'length-1), + scout => sov(congr_cl43_wB_offset to congr_cl43_wB_offset + congr_cl43_wB_d'length-1), + din => congr_cl43_wB_d, + dout => congr_cl43_wB_q); +-- Congruence Class 43 Way C Register +congr_cl43_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl43_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl43_wC_offset to congr_cl43_wC_offset + congr_cl43_wC_d'length-1), + scout => sov(congr_cl43_wC_offset to congr_cl43_wC_offset + congr_cl43_wC_d'length-1), + din => congr_cl43_wC_d, + dout => congr_cl43_wC_q); +-- Congruence Class 43 Way D Register +congr_cl43_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl43_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl43_wD_offset to congr_cl43_wD_offset + congr_cl43_wD_d'length-1), + scout => sov(congr_cl43_wD_offset to congr_cl43_wD_offset + congr_cl43_wD_d'length-1), + din => congr_cl43_wD_d, + dout => congr_cl43_wD_q); +-- Congruence Class 43 Way E Register +congr_cl43_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl43_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl43_wE_offset to congr_cl43_wE_offset + congr_cl43_wE_d'length-1), + scout => sov(congr_cl43_wE_offset to congr_cl43_wE_offset + congr_cl43_wE_d'length-1), + din => congr_cl43_wE_d, + dout => congr_cl43_wE_q); +-- Congruence Class 43 Way F Register +congr_cl43_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl43_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl43_wF_offset to congr_cl43_wF_offset + congr_cl43_wF_d'length-1), + scout => sov(congr_cl43_wF_offset to congr_cl43_wF_offset + congr_cl43_wF_d'length-1), + din => congr_cl43_wF_d, + dout => congr_cl43_wF_q); +-- Congruence Class 43 Way G Register +congr_cl43_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl43_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl43_wG_offset to congr_cl43_wG_offset + congr_cl43_wG_d'length-1), + scout => sov(congr_cl43_wG_offset to congr_cl43_wG_offset + congr_cl43_wG_d'length-1), + din => congr_cl43_wG_d, + dout => congr_cl43_wG_q); +-- Congruence Class 43 Way H Register +congr_cl43_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl43_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl43_wH_offset to congr_cl43_wH_offset + congr_cl43_wH_d'length-1), + scout => sov(congr_cl43_wH_offset to congr_cl43_wH_offset + congr_cl43_wH_d'length-1), + din => congr_cl43_wH_d, + dout => congr_cl43_wH_q); +-- Congruence Class 44 Way A Register +congr_cl44_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl44_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl44_wA_offset to congr_cl44_wA_offset + congr_cl44_wA_d'length-1), + scout => sov(congr_cl44_wA_offset to congr_cl44_wA_offset + congr_cl44_wA_d'length-1), + din => congr_cl44_wA_d, + dout => congr_cl44_wA_q); +-- Congruence Class 44 Way B Register +congr_cl44_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl44_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl44_wB_offset to congr_cl44_wB_offset + congr_cl44_wB_d'length-1), + scout => sov(congr_cl44_wB_offset to congr_cl44_wB_offset + congr_cl44_wB_d'length-1), + din => congr_cl44_wB_d, + dout => congr_cl44_wB_q); +-- Congruence Class 44 Way C Register +congr_cl44_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl44_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl44_wC_offset to congr_cl44_wC_offset + congr_cl44_wC_d'length-1), + scout => sov(congr_cl44_wC_offset to congr_cl44_wC_offset + congr_cl44_wC_d'length-1), + din => congr_cl44_wC_d, + dout => congr_cl44_wC_q); +-- Congruence Class 44 Way D Register +congr_cl44_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl44_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl44_wD_offset to congr_cl44_wD_offset + congr_cl44_wD_d'length-1), + scout => sov(congr_cl44_wD_offset to congr_cl44_wD_offset + congr_cl44_wD_d'length-1), + din => congr_cl44_wD_d, + dout => congr_cl44_wD_q); +-- Congruence Class 44 Way E Register +congr_cl44_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl44_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl44_wE_offset to congr_cl44_wE_offset + congr_cl44_wE_d'length-1), + scout => sov(congr_cl44_wE_offset to congr_cl44_wE_offset + congr_cl44_wE_d'length-1), + din => congr_cl44_wE_d, + dout => congr_cl44_wE_q); +-- Congruence Class 44 Way F Register +congr_cl44_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl44_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl44_wF_offset to congr_cl44_wF_offset + congr_cl44_wF_d'length-1), + scout => sov(congr_cl44_wF_offset to congr_cl44_wF_offset + congr_cl44_wF_d'length-1), + din => congr_cl44_wF_d, + dout => congr_cl44_wF_q); +-- Congruence Class 44 Way G Register +congr_cl44_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl44_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl44_wG_offset to congr_cl44_wG_offset + congr_cl44_wG_d'length-1), + scout => sov(congr_cl44_wG_offset to congr_cl44_wG_offset + congr_cl44_wG_d'length-1), + din => congr_cl44_wG_d, + dout => congr_cl44_wG_q); +-- Congruence Class 44 Way H Register +congr_cl44_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl44_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl44_wH_offset to congr_cl44_wH_offset + congr_cl44_wH_d'length-1), + scout => sov(congr_cl44_wH_offset to congr_cl44_wH_offset + congr_cl44_wH_d'length-1), + din => congr_cl44_wH_d, + dout => congr_cl44_wH_q); +-- Congruence Class 45 Way A Register +congr_cl45_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl45_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl45_wA_offset to congr_cl45_wA_offset + congr_cl45_wA_d'length-1), + scout => sov(congr_cl45_wA_offset to congr_cl45_wA_offset + congr_cl45_wA_d'length-1), + din => congr_cl45_wA_d, + dout => congr_cl45_wA_q); +-- Congruence Class 45 Way B Register +congr_cl45_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl45_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl45_wB_offset to congr_cl45_wB_offset + congr_cl45_wB_d'length-1), + scout => sov(congr_cl45_wB_offset to congr_cl45_wB_offset + congr_cl45_wB_d'length-1), + din => congr_cl45_wB_d, + dout => congr_cl45_wB_q); +-- Congruence Class 45 Way C Register +congr_cl45_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl45_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl45_wC_offset to congr_cl45_wC_offset + congr_cl45_wC_d'length-1), + scout => sov(congr_cl45_wC_offset to congr_cl45_wC_offset + congr_cl45_wC_d'length-1), + din => congr_cl45_wC_d, + dout => congr_cl45_wC_q); +-- Congruence Class 45 Way D Register +congr_cl45_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl45_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl45_wD_offset to congr_cl45_wD_offset + congr_cl45_wD_d'length-1), + scout => sov(congr_cl45_wD_offset to congr_cl45_wD_offset + congr_cl45_wD_d'length-1), + din => congr_cl45_wD_d, + dout => congr_cl45_wD_q); +-- Congruence Class 45 Way E Register +congr_cl45_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl45_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl45_wE_offset to congr_cl45_wE_offset + congr_cl45_wE_d'length-1), + scout => sov(congr_cl45_wE_offset to congr_cl45_wE_offset + congr_cl45_wE_d'length-1), + din => congr_cl45_wE_d, + dout => congr_cl45_wE_q); +-- Congruence Class 45 Way F Register +congr_cl45_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl45_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl45_wF_offset to congr_cl45_wF_offset + congr_cl45_wF_d'length-1), + scout => sov(congr_cl45_wF_offset to congr_cl45_wF_offset + congr_cl45_wF_d'length-1), + din => congr_cl45_wF_d, + dout => congr_cl45_wF_q); +-- Congruence Class 45 Way G Register +congr_cl45_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl45_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl45_wG_offset to congr_cl45_wG_offset + congr_cl45_wG_d'length-1), + scout => sov(congr_cl45_wG_offset to congr_cl45_wG_offset + congr_cl45_wG_d'length-1), + din => congr_cl45_wG_d, + dout => congr_cl45_wG_q); +-- Congruence Class 45 Way H Register +congr_cl45_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl45_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl45_wH_offset to congr_cl45_wH_offset + congr_cl45_wH_d'length-1), + scout => sov(congr_cl45_wH_offset to congr_cl45_wH_offset + congr_cl45_wH_d'length-1), + din => congr_cl45_wH_d, + dout => congr_cl45_wH_q); +-- Congruence Class 46 Way A Register +congr_cl46_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl46_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl46_wA_offset to congr_cl46_wA_offset + congr_cl46_wA_d'length-1), + scout => sov(congr_cl46_wA_offset to congr_cl46_wA_offset + congr_cl46_wA_d'length-1), + din => congr_cl46_wA_d, + dout => congr_cl46_wA_q); +-- Congruence Class 46 Way B Register +congr_cl46_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl46_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl46_wB_offset to congr_cl46_wB_offset + congr_cl46_wB_d'length-1), + scout => sov(congr_cl46_wB_offset to congr_cl46_wB_offset + congr_cl46_wB_d'length-1), + din => congr_cl46_wB_d, + dout => congr_cl46_wB_q); +-- Congruence Class 46 Way C Register +congr_cl46_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl46_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl46_wC_offset to congr_cl46_wC_offset + congr_cl46_wC_d'length-1), + scout => sov(congr_cl46_wC_offset to congr_cl46_wC_offset + congr_cl46_wC_d'length-1), + din => congr_cl46_wC_d, + dout => congr_cl46_wC_q); +-- Congruence Class 46 Way D Register +congr_cl46_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl46_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl46_wD_offset to congr_cl46_wD_offset + congr_cl46_wD_d'length-1), + scout => sov(congr_cl46_wD_offset to congr_cl46_wD_offset + congr_cl46_wD_d'length-1), + din => congr_cl46_wD_d, + dout => congr_cl46_wD_q); +-- Congruence Class 46 Way E Register +congr_cl46_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl46_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl46_wE_offset to congr_cl46_wE_offset + congr_cl46_wE_d'length-1), + scout => sov(congr_cl46_wE_offset to congr_cl46_wE_offset + congr_cl46_wE_d'length-1), + din => congr_cl46_wE_d, + dout => congr_cl46_wE_q); +-- Congruence Class 46 Way F Register +congr_cl46_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl46_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl46_wF_offset to congr_cl46_wF_offset + congr_cl46_wF_d'length-1), + scout => sov(congr_cl46_wF_offset to congr_cl46_wF_offset + congr_cl46_wF_d'length-1), + din => congr_cl46_wF_d, + dout => congr_cl46_wF_q); +-- Congruence Class 46 Way G Register +congr_cl46_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl46_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl46_wG_offset to congr_cl46_wG_offset + congr_cl46_wG_d'length-1), + scout => sov(congr_cl46_wG_offset to congr_cl46_wG_offset + congr_cl46_wG_d'length-1), + din => congr_cl46_wG_d, + dout => congr_cl46_wG_q); +-- Congruence Class 46 Way H Register +congr_cl46_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl46_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl46_wH_offset to congr_cl46_wH_offset + congr_cl46_wH_d'length-1), + scout => sov(congr_cl46_wH_offset to congr_cl46_wH_offset + congr_cl46_wH_d'length-1), + din => congr_cl46_wH_d, + dout => congr_cl46_wH_q); +-- Congruence Class 47 Way A Register +congr_cl47_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl47_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl47_wA_offset to congr_cl47_wA_offset + congr_cl47_wA_d'length-1), + scout => sov(congr_cl47_wA_offset to congr_cl47_wA_offset + congr_cl47_wA_d'length-1), + din => congr_cl47_wA_d, + dout => congr_cl47_wA_q); +-- Congruence Class 47 Way B Register +congr_cl47_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl47_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl47_wB_offset to congr_cl47_wB_offset + congr_cl47_wB_d'length-1), + scout => sov(congr_cl47_wB_offset to congr_cl47_wB_offset + congr_cl47_wB_d'length-1), + din => congr_cl47_wB_d, + dout => congr_cl47_wB_q); +-- Congruence Class 47 Way C Register +congr_cl47_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl47_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl47_wC_offset to congr_cl47_wC_offset + congr_cl47_wC_d'length-1), + scout => sov(congr_cl47_wC_offset to congr_cl47_wC_offset + congr_cl47_wC_d'length-1), + din => congr_cl47_wC_d, + dout => congr_cl47_wC_q); +-- Congruence Class 47 Way D Register +congr_cl47_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl47_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl47_wD_offset to congr_cl47_wD_offset + congr_cl47_wD_d'length-1), + scout => sov(congr_cl47_wD_offset to congr_cl47_wD_offset + congr_cl47_wD_d'length-1), + din => congr_cl47_wD_d, + dout => congr_cl47_wD_q); +-- Congruence Class 47 Way E Register +congr_cl47_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl47_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl47_wE_offset to congr_cl47_wE_offset + congr_cl47_wE_d'length-1), + scout => sov(congr_cl47_wE_offset to congr_cl47_wE_offset + congr_cl47_wE_d'length-1), + din => congr_cl47_wE_d, + dout => congr_cl47_wE_q); +-- Congruence Class 47 Way F Register +congr_cl47_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl47_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl47_wF_offset to congr_cl47_wF_offset + congr_cl47_wF_d'length-1), + scout => sov(congr_cl47_wF_offset to congr_cl47_wF_offset + congr_cl47_wF_d'length-1), + din => congr_cl47_wF_d, + dout => congr_cl47_wF_q); +-- Congruence Class 47 Way G Register +congr_cl47_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl47_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl47_wG_offset to congr_cl47_wG_offset + congr_cl47_wG_d'length-1), + scout => sov(congr_cl47_wG_offset to congr_cl47_wG_offset + congr_cl47_wG_d'length-1), + din => congr_cl47_wG_d, + dout => congr_cl47_wG_q); +-- Congruence Class 47 Way H Register +congr_cl47_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl47_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl47_wH_offset to congr_cl47_wH_offset + congr_cl47_wH_d'length-1), + scout => sov(congr_cl47_wH_offset to congr_cl47_wH_offset + congr_cl47_wH_d'length-1), + din => congr_cl47_wH_d, + dout => congr_cl47_wH_q); +-- Congruence Class 48 Way A Register +congr_cl48_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl48_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl48_wA_offset to congr_cl48_wA_offset + congr_cl48_wA_d'length-1), + scout => sov(congr_cl48_wA_offset to congr_cl48_wA_offset + congr_cl48_wA_d'length-1), + din => congr_cl48_wA_d, + dout => congr_cl48_wA_q); +-- Congruence Class 48 Way B Register +congr_cl48_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl48_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl48_wB_offset to congr_cl48_wB_offset + congr_cl48_wB_d'length-1), + scout => sov(congr_cl48_wB_offset to congr_cl48_wB_offset + congr_cl48_wB_d'length-1), + din => congr_cl48_wB_d, + dout => congr_cl48_wB_q); +-- Congruence Class 48 Way C Register +congr_cl48_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl48_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl48_wC_offset to congr_cl48_wC_offset + congr_cl48_wC_d'length-1), + scout => sov(congr_cl48_wC_offset to congr_cl48_wC_offset + congr_cl48_wC_d'length-1), + din => congr_cl48_wC_d, + dout => congr_cl48_wC_q); +-- Congruence Class 48 Way D Register +congr_cl48_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl48_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl48_wD_offset to congr_cl48_wD_offset + congr_cl48_wD_d'length-1), + scout => sov(congr_cl48_wD_offset to congr_cl48_wD_offset + congr_cl48_wD_d'length-1), + din => congr_cl48_wD_d, + dout => congr_cl48_wD_q); +-- Congruence Class 48 Way E Register +congr_cl48_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl48_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl48_wE_offset to congr_cl48_wE_offset + congr_cl48_wE_d'length-1), + scout => sov(congr_cl48_wE_offset to congr_cl48_wE_offset + congr_cl48_wE_d'length-1), + din => congr_cl48_wE_d, + dout => congr_cl48_wE_q); +-- Congruence Class 48 Way F Register +congr_cl48_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl48_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl48_wF_offset to congr_cl48_wF_offset + congr_cl48_wF_d'length-1), + scout => sov(congr_cl48_wF_offset to congr_cl48_wF_offset + congr_cl48_wF_d'length-1), + din => congr_cl48_wF_d, + dout => congr_cl48_wF_q); +-- Congruence Class 48 Way G Register +congr_cl48_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl48_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl48_wG_offset to congr_cl48_wG_offset + congr_cl48_wG_d'length-1), + scout => sov(congr_cl48_wG_offset to congr_cl48_wG_offset + congr_cl48_wG_d'length-1), + din => congr_cl48_wG_d, + dout => congr_cl48_wG_q); +-- Congruence Class 48 Way H Register +congr_cl48_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl48_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl48_wH_offset to congr_cl48_wH_offset + congr_cl48_wH_d'length-1), + scout => sov(congr_cl48_wH_offset to congr_cl48_wH_offset + congr_cl48_wH_d'length-1), + din => congr_cl48_wH_d, + dout => congr_cl48_wH_q); +-- Congruence Class 49 Way A Register +congr_cl49_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl49_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl49_wA_offset to congr_cl49_wA_offset + congr_cl49_wA_d'length-1), + scout => sov(congr_cl49_wA_offset to congr_cl49_wA_offset + congr_cl49_wA_d'length-1), + din => congr_cl49_wA_d, + dout => congr_cl49_wA_q); +-- Congruence Class 49 Way B Register +congr_cl49_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl49_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl49_wB_offset to congr_cl49_wB_offset + congr_cl49_wB_d'length-1), + scout => sov(congr_cl49_wB_offset to congr_cl49_wB_offset + congr_cl49_wB_d'length-1), + din => congr_cl49_wB_d, + dout => congr_cl49_wB_q); +-- Congruence Class 49 Way C Register +congr_cl49_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl49_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl49_wC_offset to congr_cl49_wC_offset + congr_cl49_wC_d'length-1), + scout => sov(congr_cl49_wC_offset to congr_cl49_wC_offset + congr_cl49_wC_d'length-1), + din => congr_cl49_wC_d, + dout => congr_cl49_wC_q); +-- Congruence Class 49 Way D Register +congr_cl49_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl49_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl49_wD_offset to congr_cl49_wD_offset + congr_cl49_wD_d'length-1), + scout => sov(congr_cl49_wD_offset to congr_cl49_wD_offset + congr_cl49_wD_d'length-1), + din => congr_cl49_wD_d, + dout => congr_cl49_wD_q); +-- Congruence Class 49 Way E Register +congr_cl49_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl49_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl49_wE_offset to congr_cl49_wE_offset + congr_cl49_wE_d'length-1), + scout => sov(congr_cl49_wE_offset to congr_cl49_wE_offset + congr_cl49_wE_d'length-1), + din => congr_cl49_wE_d, + dout => congr_cl49_wE_q); +-- Congruence Class 49 Way F Register +congr_cl49_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl49_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl49_wF_offset to congr_cl49_wF_offset + congr_cl49_wF_d'length-1), + scout => sov(congr_cl49_wF_offset to congr_cl49_wF_offset + congr_cl49_wF_d'length-1), + din => congr_cl49_wF_d, + dout => congr_cl49_wF_q); +-- Congruence Class 49 Way G Register +congr_cl49_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl49_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl49_wG_offset to congr_cl49_wG_offset + congr_cl49_wG_d'length-1), + scout => sov(congr_cl49_wG_offset to congr_cl49_wG_offset + congr_cl49_wG_d'length-1), + din => congr_cl49_wG_d, + dout => congr_cl49_wG_q); +-- Congruence Class 49 Way H Register +congr_cl49_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl49_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl49_wH_offset to congr_cl49_wH_offset + congr_cl49_wH_d'length-1), + scout => sov(congr_cl49_wH_offset to congr_cl49_wH_offset + congr_cl49_wH_d'length-1), + din => congr_cl49_wH_d, + dout => congr_cl49_wH_q); +-- Congruence Class 50 Way A Register +congr_cl50_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl50_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl50_wA_offset to congr_cl50_wA_offset + congr_cl50_wA_d'length-1), + scout => sov(congr_cl50_wA_offset to congr_cl50_wA_offset + congr_cl50_wA_d'length-1), + din => congr_cl50_wA_d, + dout => congr_cl50_wA_q); +-- Congruence Class 50 Way B Register +congr_cl50_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl50_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl50_wB_offset to congr_cl50_wB_offset + congr_cl50_wB_d'length-1), + scout => sov(congr_cl50_wB_offset to congr_cl50_wB_offset + congr_cl50_wB_d'length-1), + din => congr_cl50_wB_d, + dout => congr_cl50_wB_q); +-- Congruence Class 50 Way C Register +congr_cl50_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl50_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl50_wC_offset to congr_cl50_wC_offset + congr_cl50_wC_d'length-1), + scout => sov(congr_cl50_wC_offset to congr_cl50_wC_offset + congr_cl50_wC_d'length-1), + din => congr_cl50_wC_d, + dout => congr_cl50_wC_q); +-- Congruence Class 50 Way D Register +congr_cl50_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl50_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl50_wD_offset to congr_cl50_wD_offset + congr_cl50_wD_d'length-1), + scout => sov(congr_cl50_wD_offset to congr_cl50_wD_offset + congr_cl50_wD_d'length-1), + din => congr_cl50_wD_d, + dout => congr_cl50_wD_q); +-- Congruence Class 50 Way E Register +congr_cl50_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl50_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl50_wE_offset to congr_cl50_wE_offset + congr_cl50_wE_d'length-1), + scout => sov(congr_cl50_wE_offset to congr_cl50_wE_offset + congr_cl50_wE_d'length-1), + din => congr_cl50_wE_d, + dout => congr_cl50_wE_q); +-- Congruence Class 50 Way F Register +congr_cl50_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl50_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl50_wF_offset to congr_cl50_wF_offset + congr_cl50_wF_d'length-1), + scout => sov(congr_cl50_wF_offset to congr_cl50_wF_offset + congr_cl50_wF_d'length-1), + din => congr_cl50_wF_d, + dout => congr_cl50_wF_q); +-- Congruence Class 50 Way G Register +congr_cl50_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl50_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl50_wG_offset to congr_cl50_wG_offset + congr_cl50_wG_d'length-1), + scout => sov(congr_cl50_wG_offset to congr_cl50_wG_offset + congr_cl50_wG_d'length-1), + din => congr_cl50_wG_d, + dout => congr_cl50_wG_q); +-- Congruence Class 50 Way H Register +congr_cl50_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl50_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl50_wH_offset to congr_cl50_wH_offset + congr_cl50_wH_d'length-1), + scout => sov(congr_cl50_wH_offset to congr_cl50_wH_offset + congr_cl50_wH_d'length-1), + din => congr_cl50_wH_d, + dout => congr_cl50_wH_q); +-- Congruence Class 51 Way A Register +congr_cl51_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl51_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl51_wA_offset to congr_cl51_wA_offset + congr_cl51_wA_d'length-1), + scout => sov(congr_cl51_wA_offset to congr_cl51_wA_offset + congr_cl51_wA_d'length-1), + din => congr_cl51_wA_d, + dout => congr_cl51_wA_q); +-- Congruence Class 51 Way B Register +congr_cl51_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl51_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl51_wB_offset to congr_cl51_wB_offset + congr_cl51_wB_d'length-1), + scout => sov(congr_cl51_wB_offset to congr_cl51_wB_offset + congr_cl51_wB_d'length-1), + din => congr_cl51_wB_d, + dout => congr_cl51_wB_q); +-- Congruence Class 51 Way C Register +congr_cl51_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl51_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl51_wC_offset to congr_cl51_wC_offset + congr_cl51_wC_d'length-1), + scout => sov(congr_cl51_wC_offset to congr_cl51_wC_offset + congr_cl51_wC_d'length-1), + din => congr_cl51_wC_d, + dout => congr_cl51_wC_q); +-- Congruence Class 51 Way D Register +congr_cl51_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl51_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl51_wD_offset to congr_cl51_wD_offset + congr_cl51_wD_d'length-1), + scout => sov(congr_cl51_wD_offset to congr_cl51_wD_offset + congr_cl51_wD_d'length-1), + din => congr_cl51_wD_d, + dout => congr_cl51_wD_q); +-- Congruence Class 51 Way E Register +congr_cl51_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl51_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl51_wE_offset to congr_cl51_wE_offset + congr_cl51_wE_d'length-1), + scout => sov(congr_cl51_wE_offset to congr_cl51_wE_offset + congr_cl51_wE_d'length-1), + din => congr_cl51_wE_d, + dout => congr_cl51_wE_q); +-- Congruence Class 51 Way F Register +congr_cl51_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl51_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl51_wF_offset to congr_cl51_wF_offset + congr_cl51_wF_d'length-1), + scout => sov(congr_cl51_wF_offset to congr_cl51_wF_offset + congr_cl51_wF_d'length-1), + din => congr_cl51_wF_d, + dout => congr_cl51_wF_q); +-- Congruence Class 51 Way G Register +congr_cl51_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl51_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl51_wG_offset to congr_cl51_wG_offset + congr_cl51_wG_d'length-1), + scout => sov(congr_cl51_wG_offset to congr_cl51_wG_offset + congr_cl51_wG_d'length-1), + din => congr_cl51_wG_d, + dout => congr_cl51_wG_q); +-- Congruence Class 51 Way H Register +congr_cl51_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl51_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl51_wH_offset to congr_cl51_wH_offset + congr_cl51_wH_d'length-1), + scout => sov(congr_cl51_wH_offset to congr_cl51_wH_offset + congr_cl51_wH_d'length-1), + din => congr_cl51_wH_d, + dout => congr_cl51_wH_q); +-- Congruence Class 52 Way A Register +congr_cl52_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl52_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl52_wA_offset to congr_cl52_wA_offset + congr_cl52_wA_d'length-1), + scout => sov(congr_cl52_wA_offset to congr_cl52_wA_offset + congr_cl52_wA_d'length-1), + din => congr_cl52_wA_d, + dout => congr_cl52_wA_q); +-- Congruence Class 52 Way B Register +congr_cl52_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl52_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl52_wB_offset to congr_cl52_wB_offset + congr_cl52_wB_d'length-1), + scout => sov(congr_cl52_wB_offset to congr_cl52_wB_offset + congr_cl52_wB_d'length-1), + din => congr_cl52_wB_d, + dout => congr_cl52_wB_q); +-- Congruence Class 52 Way C Register +congr_cl52_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl52_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl52_wC_offset to congr_cl52_wC_offset + congr_cl52_wC_d'length-1), + scout => sov(congr_cl52_wC_offset to congr_cl52_wC_offset + congr_cl52_wC_d'length-1), + din => congr_cl52_wC_d, + dout => congr_cl52_wC_q); +-- Congruence Class 52 Way D Register +congr_cl52_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl52_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl52_wD_offset to congr_cl52_wD_offset + congr_cl52_wD_d'length-1), + scout => sov(congr_cl52_wD_offset to congr_cl52_wD_offset + congr_cl52_wD_d'length-1), + din => congr_cl52_wD_d, + dout => congr_cl52_wD_q); +-- Congruence Class 52 Way E Register +congr_cl52_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl52_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl52_wE_offset to congr_cl52_wE_offset + congr_cl52_wE_d'length-1), + scout => sov(congr_cl52_wE_offset to congr_cl52_wE_offset + congr_cl52_wE_d'length-1), + din => congr_cl52_wE_d, + dout => congr_cl52_wE_q); +-- Congruence Class 52 Way F Register +congr_cl52_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl52_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl52_wF_offset to congr_cl52_wF_offset + congr_cl52_wF_d'length-1), + scout => sov(congr_cl52_wF_offset to congr_cl52_wF_offset + congr_cl52_wF_d'length-1), + din => congr_cl52_wF_d, + dout => congr_cl52_wF_q); +-- Congruence Class 52 Way G Register +congr_cl52_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl52_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl52_wG_offset to congr_cl52_wG_offset + congr_cl52_wG_d'length-1), + scout => sov(congr_cl52_wG_offset to congr_cl52_wG_offset + congr_cl52_wG_d'length-1), + din => congr_cl52_wG_d, + dout => congr_cl52_wG_q); +-- Congruence Class 52 Way H Register +congr_cl52_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl52_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl52_wH_offset to congr_cl52_wH_offset + congr_cl52_wH_d'length-1), + scout => sov(congr_cl52_wH_offset to congr_cl52_wH_offset + congr_cl52_wH_d'length-1), + din => congr_cl52_wH_d, + dout => congr_cl52_wH_q); +-- Congruence Class 53 Way A Register +congr_cl53_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl53_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl53_wA_offset to congr_cl53_wA_offset + congr_cl53_wA_d'length-1), + scout => sov(congr_cl53_wA_offset to congr_cl53_wA_offset + congr_cl53_wA_d'length-1), + din => congr_cl53_wA_d, + dout => congr_cl53_wA_q); +-- Congruence Class 53 Way B Register +congr_cl53_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl53_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl53_wB_offset to congr_cl53_wB_offset + congr_cl53_wB_d'length-1), + scout => sov(congr_cl53_wB_offset to congr_cl53_wB_offset + congr_cl53_wB_d'length-1), + din => congr_cl53_wB_d, + dout => congr_cl53_wB_q); +-- Congruence Class 53 Way C Register +congr_cl53_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl53_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl53_wC_offset to congr_cl53_wC_offset + congr_cl53_wC_d'length-1), + scout => sov(congr_cl53_wC_offset to congr_cl53_wC_offset + congr_cl53_wC_d'length-1), + din => congr_cl53_wC_d, + dout => congr_cl53_wC_q); +-- Congruence Class 53 Way D Register +congr_cl53_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl53_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl53_wD_offset to congr_cl53_wD_offset + congr_cl53_wD_d'length-1), + scout => sov(congr_cl53_wD_offset to congr_cl53_wD_offset + congr_cl53_wD_d'length-1), + din => congr_cl53_wD_d, + dout => congr_cl53_wD_q); +-- Congruence Class 53 Way E Register +congr_cl53_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl53_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl53_wE_offset to congr_cl53_wE_offset + congr_cl53_wE_d'length-1), + scout => sov(congr_cl53_wE_offset to congr_cl53_wE_offset + congr_cl53_wE_d'length-1), + din => congr_cl53_wE_d, + dout => congr_cl53_wE_q); +-- Congruence Class 53 Way F Register +congr_cl53_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl53_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl53_wF_offset to congr_cl53_wF_offset + congr_cl53_wF_d'length-1), + scout => sov(congr_cl53_wF_offset to congr_cl53_wF_offset + congr_cl53_wF_d'length-1), + din => congr_cl53_wF_d, + dout => congr_cl53_wF_q); +-- Congruence Class 53 Way G Register +congr_cl53_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl53_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl53_wG_offset to congr_cl53_wG_offset + congr_cl53_wG_d'length-1), + scout => sov(congr_cl53_wG_offset to congr_cl53_wG_offset + congr_cl53_wG_d'length-1), + din => congr_cl53_wG_d, + dout => congr_cl53_wG_q); +-- Congruence Class 53 Way H Register +congr_cl53_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl53_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl53_wH_offset to congr_cl53_wH_offset + congr_cl53_wH_d'length-1), + scout => sov(congr_cl53_wH_offset to congr_cl53_wH_offset + congr_cl53_wH_d'length-1), + din => congr_cl53_wH_d, + dout => congr_cl53_wH_q); +-- Congruence Class 54 Way A Register +congr_cl54_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl54_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl54_wA_offset to congr_cl54_wA_offset + congr_cl54_wA_d'length-1), + scout => sov(congr_cl54_wA_offset to congr_cl54_wA_offset + congr_cl54_wA_d'length-1), + din => congr_cl54_wA_d, + dout => congr_cl54_wA_q); +-- Congruence Class 54 Way B Register +congr_cl54_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl54_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl54_wB_offset to congr_cl54_wB_offset + congr_cl54_wB_d'length-1), + scout => sov(congr_cl54_wB_offset to congr_cl54_wB_offset + congr_cl54_wB_d'length-1), + din => congr_cl54_wB_d, + dout => congr_cl54_wB_q); +-- Congruence Class 54 Way C Register +congr_cl54_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl54_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl54_wC_offset to congr_cl54_wC_offset + congr_cl54_wC_d'length-1), + scout => sov(congr_cl54_wC_offset to congr_cl54_wC_offset + congr_cl54_wC_d'length-1), + din => congr_cl54_wC_d, + dout => congr_cl54_wC_q); +-- Congruence Class 54 Way D Register +congr_cl54_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl54_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl54_wD_offset to congr_cl54_wD_offset + congr_cl54_wD_d'length-1), + scout => sov(congr_cl54_wD_offset to congr_cl54_wD_offset + congr_cl54_wD_d'length-1), + din => congr_cl54_wD_d, + dout => congr_cl54_wD_q); +-- Congruence Class 54 Way E Register +congr_cl54_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl54_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl54_wE_offset to congr_cl54_wE_offset + congr_cl54_wE_d'length-1), + scout => sov(congr_cl54_wE_offset to congr_cl54_wE_offset + congr_cl54_wE_d'length-1), + din => congr_cl54_wE_d, + dout => congr_cl54_wE_q); +-- Congruence Class 54 Way F Register +congr_cl54_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl54_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl54_wF_offset to congr_cl54_wF_offset + congr_cl54_wF_d'length-1), + scout => sov(congr_cl54_wF_offset to congr_cl54_wF_offset + congr_cl54_wF_d'length-1), + din => congr_cl54_wF_d, + dout => congr_cl54_wF_q); +-- Congruence Class 54 Way G Register +congr_cl54_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl54_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl54_wG_offset to congr_cl54_wG_offset + congr_cl54_wG_d'length-1), + scout => sov(congr_cl54_wG_offset to congr_cl54_wG_offset + congr_cl54_wG_d'length-1), + din => congr_cl54_wG_d, + dout => congr_cl54_wG_q); +-- Congruence Class 54 Way H Register +congr_cl54_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl54_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl54_wH_offset to congr_cl54_wH_offset + congr_cl54_wH_d'length-1), + scout => sov(congr_cl54_wH_offset to congr_cl54_wH_offset + congr_cl54_wH_d'length-1), + din => congr_cl54_wH_d, + dout => congr_cl54_wH_q); +-- Congruence Class 55 Way A Register +congr_cl55_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl55_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl55_wA_offset to congr_cl55_wA_offset + congr_cl55_wA_d'length-1), + scout => sov(congr_cl55_wA_offset to congr_cl55_wA_offset + congr_cl55_wA_d'length-1), + din => congr_cl55_wA_d, + dout => congr_cl55_wA_q); +-- Congruence Class 55 Way B Register +congr_cl55_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl55_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl55_wB_offset to congr_cl55_wB_offset + congr_cl55_wB_d'length-1), + scout => sov(congr_cl55_wB_offset to congr_cl55_wB_offset + congr_cl55_wB_d'length-1), + din => congr_cl55_wB_d, + dout => congr_cl55_wB_q); +-- Congruence Class 55 Way C Register +congr_cl55_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl55_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl55_wC_offset to congr_cl55_wC_offset + congr_cl55_wC_d'length-1), + scout => sov(congr_cl55_wC_offset to congr_cl55_wC_offset + congr_cl55_wC_d'length-1), + din => congr_cl55_wC_d, + dout => congr_cl55_wC_q); +-- Congruence Class 55 Way D Register +congr_cl55_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl55_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl55_wD_offset to congr_cl55_wD_offset + congr_cl55_wD_d'length-1), + scout => sov(congr_cl55_wD_offset to congr_cl55_wD_offset + congr_cl55_wD_d'length-1), + din => congr_cl55_wD_d, + dout => congr_cl55_wD_q); +-- Congruence Class 55 Way E Register +congr_cl55_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl55_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl55_wE_offset to congr_cl55_wE_offset + congr_cl55_wE_d'length-1), + scout => sov(congr_cl55_wE_offset to congr_cl55_wE_offset + congr_cl55_wE_d'length-1), + din => congr_cl55_wE_d, + dout => congr_cl55_wE_q); +-- Congruence Class 55 Way F Register +congr_cl55_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl55_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl55_wF_offset to congr_cl55_wF_offset + congr_cl55_wF_d'length-1), + scout => sov(congr_cl55_wF_offset to congr_cl55_wF_offset + congr_cl55_wF_d'length-1), + din => congr_cl55_wF_d, + dout => congr_cl55_wF_q); +-- Congruence Class 55 Way G Register +congr_cl55_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl55_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl55_wG_offset to congr_cl55_wG_offset + congr_cl55_wG_d'length-1), + scout => sov(congr_cl55_wG_offset to congr_cl55_wG_offset + congr_cl55_wG_d'length-1), + din => congr_cl55_wG_d, + dout => congr_cl55_wG_q); +-- Congruence Class 55 Way H Register +congr_cl55_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl55_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl55_wH_offset to congr_cl55_wH_offset + congr_cl55_wH_d'length-1), + scout => sov(congr_cl55_wH_offset to congr_cl55_wH_offset + congr_cl55_wH_d'length-1), + din => congr_cl55_wH_d, + dout => congr_cl55_wH_q); +-- Congruence Class 56 Way A Register +congr_cl56_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl56_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl56_wA_offset to congr_cl56_wA_offset + congr_cl56_wA_d'length-1), + scout => sov(congr_cl56_wA_offset to congr_cl56_wA_offset + congr_cl56_wA_d'length-1), + din => congr_cl56_wA_d, + dout => congr_cl56_wA_q); +-- Congruence Class 56 Way B Register +congr_cl56_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl56_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl56_wB_offset to congr_cl56_wB_offset + congr_cl56_wB_d'length-1), + scout => sov(congr_cl56_wB_offset to congr_cl56_wB_offset + congr_cl56_wB_d'length-1), + din => congr_cl56_wB_d, + dout => congr_cl56_wB_q); +-- Congruence Class 56 Way C Register +congr_cl56_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl56_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl56_wC_offset to congr_cl56_wC_offset + congr_cl56_wC_d'length-1), + scout => sov(congr_cl56_wC_offset to congr_cl56_wC_offset + congr_cl56_wC_d'length-1), + din => congr_cl56_wC_d, + dout => congr_cl56_wC_q); +-- Congruence Class 56 Way D Register +congr_cl56_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl56_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl56_wD_offset to congr_cl56_wD_offset + congr_cl56_wD_d'length-1), + scout => sov(congr_cl56_wD_offset to congr_cl56_wD_offset + congr_cl56_wD_d'length-1), + din => congr_cl56_wD_d, + dout => congr_cl56_wD_q); +-- Congruence Class 56 Way E Register +congr_cl56_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl56_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl56_wE_offset to congr_cl56_wE_offset + congr_cl56_wE_d'length-1), + scout => sov(congr_cl56_wE_offset to congr_cl56_wE_offset + congr_cl56_wE_d'length-1), + din => congr_cl56_wE_d, + dout => congr_cl56_wE_q); +-- Congruence Class 56 Way F Register +congr_cl56_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl56_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl56_wF_offset to congr_cl56_wF_offset + congr_cl56_wF_d'length-1), + scout => sov(congr_cl56_wF_offset to congr_cl56_wF_offset + congr_cl56_wF_d'length-1), + din => congr_cl56_wF_d, + dout => congr_cl56_wF_q); +-- Congruence Class 56 Way G Register +congr_cl56_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl56_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl56_wG_offset to congr_cl56_wG_offset + congr_cl56_wG_d'length-1), + scout => sov(congr_cl56_wG_offset to congr_cl56_wG_offset + congr_cl56_wG_d'length-1), + din => congr_cl56_wG_d, + dout => congr_cl56_wG_q); +-- Congruence Class 56 Way H Register +congr_cl56_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl56_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl56_wH_offset to congr_cl56_wH_offset + congr_cl56_wH_d'length-1), + scout => sov(congr_cl56_wH_offset to congr_cl56_wH_offset + congr_cl56_wH_d'length-1), + din => congr_cl56_wH_d, + dout => congr_cl56_wH_q); +-- Congruence Class 57 Way A Register +congr_cl57_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl57_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl57_wA_offset to congr_cl57_wA_offset + congr_cl57_wA_d'length-1), + scout => sov(congr_cl57_wA_offset to congr_cl57_wA_offset + congr_cl57_wA_d'length-1), + din => congr_cl57_wA_d, + dout => congr_cl57_wA_q); +-- Congruence Class 57 Way B Register +congr_cl57_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl57_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl57_wB_offset to congr_cl57_wB_offset + congr_cl57_wB_d'length-1), + scout => sov(congr_cl57_wB_offset to congr_cl57_wB_offset + congr_cl57_wB_d'length-1), + din => congr_cl57_wB_d, + dout => congr_cl57_wB_q); +-- Congruence Class 57 Way C Register +congr_cl57_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl57_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl57_wC_offset to congr_cl57_wC_offset + congr_cl57_wC_d'length-1), + scout => sov(congr_cl57_wC_offset to congr_cl57_wC_offset + congr_cl57_wC_d'length-1), + din => congr_cl57_wC_d, + dout => congr_cl57_wC_q); +-- Congruence Class 57 Way D Register +congr_cl57_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl57_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl57_wD_offset to congr_cl57_wD_offset + congr_cl57_wD_d'length-1), + scout => sov(congr_cl57_wD_offset to congr_cl57_wD_offset + congr_cl57_wD_d'length-1), + din => congr_cl57_wD_d, + dout => congr_cl57_wD_q); +-- Congruence Class 57 Way E Register +congr_cl57_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl57_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl57_wE_offset to congr_cl57_wE_offset + congr_cl57_wE_d'length-1), + scout => sov(congr_cl57_wE_offset to congr_cl57_wE_offset + congr_cl57_wE_d'length-1), + din => congr_cl57_wE_d, + dout => congr_cl57_wE_q); +-- Congruence Class 57 Way F Register +congr_cl57_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl57_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl57_wF_offset to congr_cl57_wF_offset + congr_cl57_wF_d'length-1), + scout => sov(congr_cl57_wF_offset to congr_cl57_wF_offset + congr_cl57_wF_d'length-1), + din => congr_cl57_wF_d, + dout => congr_cl57_wF_q); +-- Congruence Class 57 Way G Register +congr_cl57_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl57_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl57_wG_offset to congr_cl57_wG_offset + congr_cl57_wG_d'length-1), + scout => sov(congr_cl57_wG_offset to congr_cl57_wG_offset + congr_cl57_wG_d'length-1), + din => congr_cl57_wG_d, + dout => congr_cl57_wG_q); +-- Congruence Class 57 Way H Register +congr_cl57_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl57_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl57_wH_offset to congr_cl57_wH_offset + congr_cl57_wH_d'length-1), + scout => sov(congr_cl57_wH_offset to congr_cl57_wH_offset + congr_cl57_wH_d'length-1), + din => congr_cl57_wH_d, + dout => congr_cl57_wH_q); +-- Congruence Class 58 Way A Register +congr_cl58_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl58_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl58_wA_offset to congr_cl58_wA_offset + congr_cl58_wA_d'length-1), + scout => sov(congr_cl58_wA_offset to congr_cl58_wA_offset + congr_cl58_wA_d'length-1), + din => congr_cl58_wA_d, + dout => congr_cl58_wA_q); +-- Congruence Class 58 Way B Register +congr_cl58_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl58_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl58_wB_offset to congr_cl58_wB_offset + congr_cl58_wB_d'length-1), + scout => sov(congr_cl58_wB_offset to congr_cl58_wB_offset + congr_cl58_wB_d'length-1), + din => congr_cl58_wB_d, + dout => congr_cl58_wB_q); +-- Congruence Class 58 Way C Register +congr_cl58_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl58_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl58_wC_offset to congr_cl58_wC_offset + congr_cl58_wC_d'length-1), + scout => sov(congr_cl58_wC_offset to congr_cl58_wC_offset + congr_cl58_wC_d'length-1), + din => congr_cl58_wC_d, + dout => congr_cl58_wC_q); +-- Congruence Class 58 Way D Register +congr_cl58_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl58_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl58_wD_offset to congr_cl58_wD_offset + congr_cl58_wD_d'length-1), + scout => sov(congr_cl58_wD_offset to congr_cl58_wD_offset + congr_cl58_wD_d'length-1), + din => congr_cl58_wD_d, + dout => congr_cl58_wD_q); +-- Congruence Class 58 Way E Register +congr_cl58_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl58_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl58_wE_offset to congr_cl58_wE_offset + congr_cl58_wE_d'length-1), + scout => sov(congr_cl58_wE_offset to congr_cl58_wE_offset + congr_cl58_wE_d'length-1), + din => congr_cl58_wE_d, + dout => congr_cl58_wE_q); +-- Congruence Class 58 Way F Register +congr_cl58_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl58_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl58_wF_offset to congr_cl58_wF_offset + congr_cl58_wF_d'length-1), + scout => sov(congr_cl58_wF_offset to congr_cl58_wF_offset + congr_cl58_wF_d'length-1), + din => congr_cl58_wF_d, + dout => congr_cl58_wF_q); +-- Congruence Class 58 Way G Register +congr_cl58_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl58_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl58_wG_offset to congr_cl58_wG_offset + congr_cl58_wG_d'length-1), + scout => sov(congr_cl58_wG_offset to congr_cl58_wG_offset + congr_cl58_wG_d'length-1), + din => congr_cl58_wG_d, + dout => congr_cl58_wG_q); +-- Congruence Class 58 Way H Register +congr_cl58_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl58_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl58_wH_offset to congr_cl58_wH_offset + congr_cl58_wH_d'length-1), + scout => sov(congr_cl58_wH_offset to congr_cl58_wH_offset + congr_cl58_wH_d'length-1), + din => congr_cl58_wH_d, + dout => congr_cl58_wH_q); +-- Congruence Class 59 Way A Register +congr_cl59_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl59_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl59_wA_offset to congr_cl59_wA_offset + congr_cl59_wA_d'length-1), + scout => sov(congr_cl59_wA_offset to congr_cl59_wA_offset + congr_cl59_wA_d'length-1), + din => congr_cl59_wA_d, + dout => congr_cl59_wA_q); +-- Congruence Class 59 Way B Register +congr_cl59_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl59_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl59_wB_offset to congr_cl59_wB_offset + congr_cl59_wB_d'length-1), + scout => sov(congr_cl59_wB_offset to congr_cl59_wB_offset + congr_cl59_wB_d'length-1), + din => congr_cl59_wB_d, + dout => congr_cl59_wB_q); +-- Congruence Class 59 Way C Register +congr_cl59_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl59_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl59_wC_offset to congr_cl59_wC_offset + congr_cl59_wC_d'length-1), + scout => sov(congr_cl59_wC_offset to congr_cl59_wC_offset + congr_cl59_wC_d'length-1), + din => congr_cl59_wC_d, + dout => congr_cl59_wC_q); +-- Congruence Class 59 Way D Register +congr_cl59_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl59_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl59_wD_offset to congr_cl59_wD_offset + congr_cl59_wD_d'length-1), + scout => sov(congr_cl59_wD_offset to congr_cl59_wD_offset + congr_cl59_wD_d'length-1), + din => congr_cl59_wD_d, + dout => congr_cl59_wD_q); +-- Congruence Class 59 Way E Register +congr_cl59_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl59_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl59_wE_offset to congr_cl59_wE_offset + congr_cl59_wE_d'length-1), + scout => sov(congr_cl59_wE_offset to congr_cl59_wE_offset + congr_cl59_wE_d'length-1), + din => congr_cl59_wE_d, + dout => congr_cl59_wE_q); +-- Congruence Class 59 Way F Register +congr_cl59_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl59_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl59_wF_offset to congr_cl59_wF_offset + congr_cl59_wF_d'length-1), + scout => sov(congr_cl59_wF_offset to congr_cl59_wF_offset + congr_cl59_wF_d'length-1), + din => congr_cl59_wF_d, + dout => congr_cl59_wF_q); +-- Congruence Class 59 Way G Register +congr_cl59_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl59_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl59_wG_offset to congr_cl59_wG_offset + congr_cl59_wG_d'length-1), + scout => sov(congr_cl59_wG_offset to congr_cl59_wG_offset + congr_cl59_wG_d'length-1), + din => congr_cl59_wG_d, + dout => congr_cl59_wG_q); +-- Congruence Class 59 Way H Register +congr_cl59_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl59_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl59_wH_offset to congr_cl59_wH_offset + congr_cl59_wH_d'length-1), + scout => sov(congr_cl59_wH_offset to congr_cl59_wH_offset + congr_cl59_wH_d'length-1), + din => congr_cl59_wH_d, + dout => congr_cl59_wH_q); +-- Congruence Class 60 Way A Register +congr_cl60_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl60_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl60_wA_offset to congr_cl60_wA_offset + congr_cl60_wA_d'length-1), + scout => sov(congr_cl60_wA_offset to congr_cl60_wA_offset + congr_cl60_wA_d'length-1), + din => congr_cl60_wA_d, + dout => congr_cl60_wA_q); +-- Congruence Class 60 Way B Register +congr_cl60_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl60_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl60_wB_offset to congr_cl60_wB_offset + congr_cl60_wB_d'length-1), + scout => sov(congr_cl60_wB_offset to congr_cl60_wB_offset + congr_cl60_wB_d'length-1), + din => congr_cl60_wB_d, + dout => congr_cl60_wB_q); +-- Congruence Class 60 Way C Register +congr_cl60_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl60_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl60_wC_offset to congr_cl60_wC_offset + congr_cl60_wC_d'length-1), + scout => sov(congr_cl60_wC_offset to congr_cl60_wC_offset + congr_cl60_wC_d'length-1), + din => congr_cl60_wC_d, + dout => congr_cl60_wC_q); +-- Congruence Class 60 Way D Register +congr_cl60_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl60_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl60_wD_offset to congr_cl60_wD_offset + congr_cl60_wD_d'length-1), + scout => sov(congr_cl60_wD_offset to congr_cl60_wD_offset + congr_cl60_wD_d'length-1), + din => congr_cl60_wD_d, + dout => congr_cl60_wD_q); +-- Congruence Class 60 Way E Register +congr_cl60_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl60_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl60_wE_offset to congr_cl60_wE_offset + congr_cl60_wE_d'length-1), + scout => sov(congr_cl60_wE_offset to congr_cl60_wE_offset + congr_cl60_wE_d'length-1), + din => congr_cl60_wE_d, + dout => congr_cl60_wE_q); +-- Congruence Class 60 Way F Register +congr_cl60_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl60_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl60_wF_offset to congr_cl60_wF_offset + congr_cl60_wF_d'length-1), + scout => sov(congr_cl60_wF_offset to congr_cl60_wF_offset + congr_cl60_wF_d'length-1), + din => congr_cl60_wF_d, + dout => congr_cl60_wF_q); +-- Congruence Class 60 Way G Register +congr_cl60_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl60_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl60_wG_offset to congr_cl60_wG_offset + congr_cl60_wG_d'length-1), + scout => sov(congr_cl60_wG_offset to congr_cl60_wG_offset + congr_cl60_wG_d'length-1), + din => congr_cl60_wG_d, + dout => congr_cl60_wG_q); +-- Congruence Class 60 Way H Register +congr_cl60_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl60_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl60_wH_offset to congr_cl60_wH_offset + congr_cl60_wH_d'length-1), + scout => sov(congr_cl60_wH_offset to congr_cl60_wH_offset + congr_cl60_wH_d'length-1), + din => congr_cl60_wH_d, + dout => congr_cl60_wH_q); +-- Congruence Class 61 Way A Register +congr_cl61_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl61_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl61_wA_offset to congr_cl61_wA_offset + congr_cl61_wA_d'length-1), + scout => sov(congr_cl61_wA_offset to congr_cl61_wA_offset + congr_cl61_wA_d'length-1), + din => congr_cl61_wA_d, + dout => congr_cl61_wA_q); +-- Congruence Class 61 Way B Register +congr_cl61_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl61_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl61_wB_offset to congr_cl61_wB_offset + congr_cl61_wB_d'length-1), + scout => sov(congr_cl61_wB_offset to congr_cl61_wB_offset + congr_cl61_wB_d'length-1), + din => congr_cl61_wB_d, + dout => congr_cl61_wB_q); +-- Congruence Class 61 Way C Register +congr_cl61_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl61_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl61_wC_offset to congr_cl61_wC_offset + congr_cl61_wC_d'length-1), + scout => sov(congr_cl61_wC_offset to congr_cl61_wC_offset + congr_cl61_wC_d'length-1), + din => congr_cl61_wC_d, + dout => congr_cl61_wC_q); +-- Congruence Class 61 Way D Register +congr_cl61_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl61_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl61_wD_offset to congr_cl61_wD_offset + congr_cl61_wD_d'length-1), + scout => sov(congr_cl61_wD_offset to congr_cl61_wD_offset + congr_cl61_wD_d'length-1), + din => congr_cl61_wD_d, + dout => congr_cl61_wD_q); +-- Congruence Class 61 Way E Register +congr_cl61_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl61_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl61_wE_offset to congr_cl61_wE_offset + congr_cl61_wE_d'length-1), + scout => sov(congr_cl61_wE_offset to congr_cl61_wE_offset + congr_cl61_wE_d'length-1), + din => congr_cl61_wE_d, + dout => congr_cl61_wE_q); +-- Congruence Class 61 Way F Register +congr_cl61_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl61_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl61_wF_offset to congr_cl61_wF_offset + congr_cl61_wF_d'length-1), + scout => sov(congr_cl61_wF_offset to congr_cl61_wF_offset + congr_cl61_wF_d'length-1), + din => congr_cl61_wF_d, + dout => congr_cl61_wF_q); +-- Congruence Class 61 Way G Register +congr_cl61_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl61_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl61_wG_offset to congr_cl61_wG_offset + congr_cl61_wG_d'length-1), + scout => sov(congr_cl61_wG_offset to congr_cl61_wG_offset + congr_cl61_wG_d'length-1), + din => congr_cl61_wG_d, + dout => congr_cl61_wG_q); +-- Congruence Class 61 Way H Register +congr_cl61_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl61_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl61_wH_offset to congr_cl61_wH_offset + congr_cl61_wH_d'length-1), + scout => sov(congr_cl61_wH_offset to congr_cl61_wH_offset + congr_cl61_wH_d'length-1), + din => congr_cl61_wH_d, + dout => congr_cl61_wH_q); +-- Congruence Class 62 Way A Register +congr_cl62_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl62_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl62_wA_offset to congr_cl62_wA_offset + congr_cl62_wA_d'length-1), + scout => sov(congr_cl62_wA_offset to congr_cl62_wA_offset + congr_cl62_wA_d'length-1), + din => congr_cl62_wA_d, + dout => congr_cl62_wA_q); +-- Congruence Class 62 Way B Register +congr_cl62_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl62_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl62_wB_offset to congr_cl62_wB_offset + congr_cl62_wB_d'length-1), + scout => sov(congr_cl62_wB_offset to congr_cl62_wB_offset + congr_cl62_wB_d'length-1), + din => congr_cl62_wB_d, + dout => congr_cl62_wB_q); +-- Congruence Class 62 Way C Register +congr_cl62_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl62_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl62_wC_offset to congr_cl62_wC_offset + congr_cl62_wC_d'length-1), + scout => sov(congr_cl62_wC_offset to congr_cl62_wC_offset + congr_cl62_wC_d'length-1), + din => congr_cl62_wC_d, + dout => congr_cl62_wC_q); +-- Congruence Class 62 Way D Register +congr_cl62_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl62_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl62_wD_offset to congr_cl62_wD_offset + congr_cl62_wD_d'length-1), + scout => sov(congr_cl62_wD_offset to congr_cl62_wD_offset + congr_cl62_wD_d'length-1), + din => congr_cl62_wD_d, + dout => congr_cl62_wD_q); +-- Congruence Class 62 Way E Register +congr_cl62_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl62_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl62_wE_offset to congr_cl62_wE_offset + congr_cl62_wE_d'length-1), + scout => sov(congr_cl62_wE_offset to congr_cl62_wE_offset + congr_cl62_wE_d'length-1), + din => congr_cl62_wE_d, + dout => congr_cl62_wE_q); +-- Congruence Class 62 Way F Register +congr_cl62_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl62_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl62_wF_offset to congr_cl62_wF_offset + congr_cl62_wF_d'length-1), + scout => sov(congr_cl62_wF_offset to congr_cl62_wF_offset + congr_cl62_wF_d'length-1), + din => congr_cl62_wF_d, + dout => congr_cl62_wF_q); +-- Congruence Class 62 Way G Register +congr_cl62_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl62_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl62_wG_offset to congr_cl62_wG_offset + congr_cl62_wG_d'length-1), + scout => sov(congr_cl62_wG_offset to congr_cl62_wG_offset + congr_cl62_wG_d'length-1), + din => congr_cl62_wG_d, + dout => congr_cl62_wG_q); +-- Congruence Class 62 Way H Register +congr_cl62_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl62_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl62_wH_offset to congr_cl62_wH_offset + congr_cl62_wH_d'length-1), + scout => sov(congr_cl62_wH_offset to congr_cl62_wH_offset + congr_cl62_wH_d'length-1), + din => congr_cl62_wH_d, + dout => congr_cl62_wH_q); +-- Congruence Class 63 Way A Register +congr_cl63_wA_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl63_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl63_wA_offset to congr_cl63_wA_offset + congr_cl63_wA_d'length-1), + scout => sov(congr_cl63_wA_offset to congr_cl63_wA_offset + congr_cl63_wA_d'length-1), + din => congr_cl63_wA_d, + dout => congr_cl63_wA_q); +-- Congruence Class 63 Way B Register +congr_cl63_wB_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl63_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl63_wB_offset to congr_cl63_wB_offset + congr_cl63_wB_d'length-1), + scout => sov(congr_cl63_wB_offset to congr_cl63_wB_offset + congr_cl63_wB_d'length-1), + din => congr_cl63_wB_d, + dout => congr_cl63_wB_q); +-- Congruence Class 63 Way C Register +congr_cl63_wC_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl63_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl63_wC_offset to congr_cl63_wC_offset + congr_cl63_wC_d'length-1), + scout => sov(congr_cl63_wC_offset to congr_cl63_wC_offset + congr_cl63_wC_d'length-1), + din => congr_cl63_wC_d, + dout => congr_cl63_wC_q); +-- Congruence Class 63 Way D Register +congr_cl63_wD_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl63_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl63_wD_offset to congr_cl63_wD_offset + congr_cl63_wD_d'length-1), + scout => sov(congr_cl63_wD_offset to congr_cl63_wD_offset + congr_cl63_wD_d'length-1), + din => congr_cl63_wD_d, + dout => congr_cl63_wD_q); +-- Congruence Class 63 Way E Register +congr_cl63_wE_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl63_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl63_wE_offset to congr_cl63_wE_offset + congr_cl63_wE_d'length-1), + scout => sov(congr_cl63_wE_offset to congr_cl63_wE_offset + congr_cl63_wE_d'length-1), + din => congr_cl63_wE_d, + dout => congr_cl63_wE_q); +-- Congruence Class 63 Way F Register +congr_cl63_wF_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl63_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl63_wF_offset to congr_cl63_wF_offset + congr_cl63_wF_d'length-1), + scout => sov(congr_cl63_wF_offset to congr_cl63_wF_offset + congr_cl63_wF_d'length-1), + din => congr_cl63_wF_d, + dout => congr_cl63_wF_q); +-- Congruence Class 63 Way G Register +congr_cl63_wG_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl63_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl63_wG_offset to congr_cl63_wG_offset + congr_cl63_wG_d'length-1), + scout => sov(congr_cl63_wG_offset to congr_cl63_wG_offset + congr_cl63_wG_d'length-1), + din => congr_cl63_wG_d, + dout => congr_cl63_wG_q); +-- Congruence Class 63 Way H Register +congr_cl63_wH_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => congr_cl63_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl63_wH_offset to congr_cl63_wH_offset + congr_cl63_wH_d'length-1), + scout => sov(congr_cl63_wH_offset to congr_cl63_wH_offset + congr_cl63_wH_d'length-1), + din => congr_cl63_wH_d, + dout => congr_cl63_wH_q); +congr_cl_all_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => congr_cl_all_act_d, + dout(0) => congr_cl_all_act_q); +-- Port 0 Congruence Class 0 Act +p0_congr_cl0_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl0_act_d, + dout(0) => p0_congr_cl0_act_q); +-- Port 0 Congruence Class 1 Act +p0_congr_cl1_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl1_act_d, + dout(0) => p0_congr_cl1_act_q); +-- Port 0 Congruence Class 2 Act +p0_congr_cl2_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl2_act_d, + dout(0) => p0_congr_cl2_act_q); +-- Port 0 Congruence Class 3 Act +p0_congr_cl3_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl3_act_d, + dout(0) => p0_congr_cl3_act_q); +-- Port 0 Congruence Class 4 Act +p0_congr_cl4_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl4_act_d, + dout(0) => p0_congr_cl4_act_q); +-- Port 0 Congruence Class 5 Act +p0_congr_cl5_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl5_act_d, + dout(0) => p0_congr_cl5_act_q); +-- Port 0 Congruence Class 6 Act +p0_congr_cl6_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl6_act_d, + dout(0) => p0_congr_cl6_act_q); +-- Port 0 Congruence Class 7 Act +p0_congr_cl7_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl7_act_d, + dout(0) => p0_congr_cl7_act_q); +-- Port 0 Congruence Class 8 Act +p0_congr_cl8_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl8_act_d, + dout(0) => p0_congr_cl8_act_q); +-- Port 0 Congruence Class 9 Act +p0_congr_cl9_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl9_act_d, + dout(0) => p0_congr_cl9_act_q); +-- Port 0 Congruence Class 10 Act +p0_congr_cl10_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl10_act_d, + dout(0) => p0_congr_cl10_act_q); +-- Port 0 Congruence Class 11 Act +p0_congr_cl11_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl11_act_d, + dout(0) => p0_congr_cl11_act_q); +-- Port 0 Congruence Class 12 Act +p0_congr_cl12_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl12_act_d, + dout(0) => p0_congr_cl12_act_q); +-- Port 0 Congruence Class 13 Act +p0_congr_cl13_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl13_act_d, + dout(0) => p0_congr_cl13_act_q); +-- Port 0 Congruence Class 14 Act +p0_congr_cl14_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl14_act_d, + dout(0) => p0_congr_cl14_act_q); +-- Port 0 Congruence Class 15 Act +p0_congr_cl15_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl15_act_d, + dout(0) => p0_congr_cl15_act_q); +-- Port 0 Congruence Class 16 Act +p0_congr_cl16_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl16_act_d, + dout(0) => p0_congr_cl16_act_q); +-- Port 0 Congruence Class 17 Act +p0_congr_cl17_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl17_act_d, + dout(0) => p0_congr_cl17_act_q); +-- Port 0 Congruence Class 18 Act +p0_congr_cl18_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl18_act_d, + dout(0) => p0_congr_cl18_act_q); +-- Port 0 Congruence Class 19 Act +p0_congr_cl19_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl19_act_d, + dout(0) => p0_congr_cl19_act_q); +-- Port 0 Congruence Class 20 Act +p0_congr_cl20_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl20_act_d, + dout(0) => p0_congr_cl20_act_q); +-- Port 0 Congruence Class 21 Act +p0_congr_cl21_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl21_act_d, + dout(0) => p0_congr_cl21_act_q); +-- Port 0 Congruence Class 22 Act +p0_congr_cl22_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl22_act_d, + dout(0) => p0_congr_cl22_act_q); +-- Port 0 Congruence Class 23 Act +p0_congr_cl23_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl23_act_d, + dout(0) => p0_congr_cl23_act_q); +-- Port 0 Congruence Class 24 Act +p0_congr_cl24_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl24_act_d, + dout(0) => p0_congr_cl24_act_q); +-- Port 0 Congruence Class 25 Act +p0_congr_cl25_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl25_act_d, + dout(0) => p0_congr_cl25_act_q); +-- Port 0 Congruence Class 26 Act +p0_congr_cl26_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl26_act_d, + dout(0) => p0_congr_cl26_act_q); +-- Port 0 Congruence Class 27 Act +p0_congr_cl27_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl27_act_d, + dout(0) => p0_congr_cl27_act_q); +-- Port 0 Congruence Class 28 Act +p0_congr_cl28_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl28_act_d, + dout(0) => p0_congr_cl28_act_q); +-- Port 0 Congruence Class 29 Act +p0_congr_cl29_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl29_act_d, + dout(0) => p0_congr_cl29_act_q); +-- Port 0 Congruence Class 30 Act +p0_congr_cl30_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl30_act_d, + dout(0) => p0_congr_cl30_act_q); +-- Port 0 Congruence Class 31 Act +p0_congr_cl31_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl31_act_d, + dout(0) => p0_congr_cl31_act_q); +-- Port 0 Congruence Class 32 Act +p0_congr_cl32_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl32_act_d, + dout(0) => p0_congr_cl32_act_q); +-- Port 0 Congruence Class 33 Act +p0_congr_cl33_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl33_act_d, + dout(0) => p0_congr_cl33_act_q); +-- Port 0 Congruence Class 34 Act +p0_congr_cl34_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl34_act_d, + dout(0) => p0_congr_cl34_act_q); +-- Port 0 Congruence Class 35 Act +p0_congr_cl35_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl35_act_d, + dout(0) => p0_congr_cl35_act_q); +-- Port 0 Congruence Class 36 Act +p0_congr_cl36_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl36_act_d, + dout(0) => p0_congr_cl36_act_q); +-- Port 0 Congruence Class 37 Act +p0_congr_cl37_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl37_act_d, + dout(0) => p0_congr_cl37_act_q); +-- Port 0 Congruence Class 38 Act +p0_congr_cl38_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl38_act_d, + dout(0) => p0_congr_cl38_act_q); +-- Port 0 Congruence Class 39 Act +p0_congr_cl39_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl39_act_d, + dout(0) => p0_congr_cl39_act_q); +-- Port 0 Congruence Class 40 Act +p0_congr_cl40_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl40_act_d, + dout(0) => p0_congr_cl40_act_q); +-- Port 0 Congruence Class 41 Act +p0_congr_cl41_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl41_act_d, + dout(0) => p0_congr_cl41_act_q); +-- Port 0 Congruence Class 42 Act +p0_congr_cl42_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl42_act_d, + dout(0) => p0_congr_cl42_act_q); +-- Port 0 Congruence Class 43 Act +p0_congr_cl43_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl43_act_d, + dout(0) => p0_congr_cl43_act_q); +-- Port 0 Congruence Class 44 Act +p0_congr_cl44_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl44_act_d, + dout(0) => p0_congr_cl44_act_q); +-- Port 0 Congruence Class 45 Act +p0_congr_cl45_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl45_act_d, + dout(0) => p0_congr_cl45_act_q); +-- Port 0 Congruence Class 46 Act +p0_congr_cl46_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl46_act_d, + dout(0) => p0_congr_cl46_act_q); +-- Port 0 Congruence Class 47 Act +p0_congr_cl47_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl47_act_d, + dout(0) => p0_congr_cl47_act_q); +-- Port 0 Congruence Class 48 Act +p0_congr_cl48_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl48_act_d, + dout(0) => p0_congr_cl48_act_q); +-- Port 0 Congruence Class 49 Act +p0_congr_cl49_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl49_act_d, + dout(0) => p0_congr_cl49_act_q); +-- Port 0 Congruence Class 50 Act +p0_congr_cl50_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl50_act_d, + dout(0) => p0_congr_cl50_act_q); +-- Port 0 Congruence Class 51 Act +p0_congr_cl51_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl51_act_d, + dout(0) => p0_congr_cl51_act_q); +-- Port 0 Congruence Class 52 Act +p0_congr_cl52_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl52_act_d, + dout(0) => p0_congr_cl52_act_q); +-- Port 0 Congruence Class 53 Act +p0_congr_cl53_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl53_act_d, + dout(0) => p0_congr_cl53_act_q); +-- Port 0 Congruence Class 54 Act +p0_congr_cl54_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl54_act_d, + dout(0) => p0_congr_cl54_act_q); +-- Port 0 Congruence Class 55 Act +p0_congr_cl55_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl55_act_d, + dout(0) => p0_congr_cl55_act_q); +-- Port 0 Congruence Class 56 Act +p0_congr_cl56_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl56_act_d, + dout(0) => p0_congr_cl56_act_q); +-- Port 0 Congruence Class 57 Act +p0_congr_cl57_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl57_act_d, + dout(0) => p0_congr_cl57_act_q); +-- Port 0 Congruence Class 58 Act +p0_congr_cl58_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl58_act_d, + dout(0) => p0_congr_cl58_act_q); +-- Port 0 Congruence Class 59 Act +p0_congr_cl59_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl59_act_d, + dout(0) => p0_congr_cl59_act_q); +-- Port 0 Congruence Class 60 Act +p0_congr_cl60_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl60_act_d, + dout(0) => p0_congr_cl60_act_q); +-- Port 0 Congruence Class 61 Act +p0_congr_cl61_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl61_act_d, + dout(0) => p0_congr_cl61_act_q); +-- Port 0 Congruence Class 62 Act +p0_congr_cl62_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl62_act_d, + dout(0) => p0_congr_cl62_act_q); +-- Port 0 Congruence Class 63 Act +p0_congr_cl63_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => p0_congr_cl63_act_d, + dout(0) => p0_congr_cl63_act_q); +-- Port 1 Congruence Class 0 Act +p1_congr_cl0_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl0_act_d, + dout(0) => p1_congr_cl0_act_q); +-- Port 1 Congruence Class 1 Act +p1_congr_cl1_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl1_act_d, + dout(0) => p1_congr_cl1_act_q); +-- Port 1 Congruence Class 2 Act +p1_congr_cl2_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl2_act_d, + dout(0) => p1_congr_cl2_act_q); +-- Port 1 Congruence Class 3 Act +p1_congr_cl3_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl3_act_d, + dout(0) => p1_congr_cl3_act_q); +-- Port 1 Congruence Class 4 Act +p1_congr_cl4_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl4_act_d, + dout(0) => p1_congr_cl4_act_q); +-- Port 1 Congruence Class 5 Act +p1_congr_cl5_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl5_act_d, + dout(0) => p1_congr_cl5_act_q); +-- Port 1 Congruence Class 6 Act +p1_congr_cl6_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl6_act_d, + dout(0) => p1_congr_cl6_act_q); +-- Port 1 Congruence Class 7 Act +p1_congr_cl7_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl7_act_d, + dout(0) => p1_congr_cl7_act_q); +-- Port 1 Congruence Class 8 Act +p1_congr_cl8_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl8_act_d, + dout(0) => p1_congr_cl8_act_q); +-- Port 1 Congruence Class 9 Act +p1_congr_cl9_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl9_act_d, + dout(0) => p1_congr_cl9_act_q); +-- Port 1 Congruence Class 10 Act +p1_congr_cl10_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl10_act_d, + dout(0) => p1_congr_cl10_act_q); +-- Port 1 Congruence Class 11 Act +p1_congr_cl11_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl11_act_d, + dout(0) => p1_congr_cl11_act_q); +-- Port 1 Congruence Class 12 Act +p1_congr_cl12_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl12_act_d, + dout(0) => p1_congr_cl12_act_q); +-- Port 1 Congruence Class 13 Act +p1_congr_cl13_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl13_act_d, + dout(0) => p1_congr_cl13_act_q); +-- Port 1 Congruence Class 14 Act +p1_congr_cl14_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl14_act_d, + dout(0) => p1_congr_cl14_act_q); +-- Port 1 Congruence Class 15 Act +p1_congr_cl15_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl15_act_d, + dout(0) => p1_congr_cl15_act_q); +-- Port 1 Congruence Class 16 Act +p1_congr_cl16_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl16_act_d, + dout(0) => p1_congr_cl16_act_q); +-- Port 1 Congruence Class 17 Act +p1_congr_cl17_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl17_act_d, + dout(0) => p1_congr_cl17_act_q); +-- Port 1 Congruence Class 18 Act +p1_congr_cl18_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl18_act_d, + dout(0) => p1_congr_cl18_act_q); +-- Port 1 Congruence Class 19 Act +p1_congr_cl19_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl19_act_d, + dout(0) => p1_congr_cl19_act_q); +-- Port 1 Congruence Class 20 Act +p1_congr_cl20_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl20_act_d, + dout(0) => p1_congr_cl20_act_q); +-- Port 1 Congruence Class 21 Act +p1_congr_cl21_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl21_act_d, + dout(0) => p1_congr_cl21_act_q); +-- Port 1 Congruence Class 22 Act +p1_congr_cl22_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl22_act_d, + dout(0) => p1_congr_cl22_act_q); +-- Port 1 Congruence Class 23 Act +p1_congr_cl23_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl23_act_d, + dout(0) => p1_congr_cl23_act_q); +-- Port 1 Congruence Class 24 Act +p1_congr_cl24_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl24_act_d, + dout(0) => p1_congr_cl24_act_q); +-- Port 1 Congruence Class 25 Act +p1_congr_cl25_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl25_act_d, + dout(0) => p1_congr_cl25_act_q); +-- Port 1 Congruence Class 26 Act +p1_congr_cl26_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl26_act_d, + dout(0) => p1_congr_cl26_act_q); +-- Port 1 Congruence Class 27 Act +p1_congr_cl27_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl27_act_d, + dout(0) => p1_congr_cl27_act_q); +-- Port 1 Congruence Class 28 Act +p1_congr_cl28_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl28_act_d, + dout(0) => p1_congr_cl28_act_q); +-- Port 1 Congruence Class 29 Act +p1_congr_cl29_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl29_act_d, + dout(0) => p1_congr_cl29_act_q); +-- Port 1 Congruence Class 30 Act +p1_congr_cl30_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl30_act_d, + dout(0) => p1_congr_cl30_act_q); +-- Port 1 Congruence Class 31 Act +p1_congr_cl31_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl31_act_d, + dout(0) => p1_congr_cl31_act_q); +-- Port 1 Congruence Class 32 Act +p1_congr_cl32_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl32_act_d, + dout(0) => p1_congr_cl32_act_q); +-- Port 1 Congruence Class 33 Act +p1_congr_cl33_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl33_act_d, + dout(0) => p1_congr_cl33_act_q); +-- Port 1 Congruence Class 34 Act +p1_congr_cl34_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl34_act_d, + dout(0) => p1_congr_cl34_act_q); +-- Port 1 Congruence Class 35 Act +p1_congr_cl35_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl35_act_d, + dout(0) => p1_congr_cl35_act_q); +-- Port 1 Congruence Class 36 Act +p1_congr_cl36_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl36_act_d, + dout(0) => p1_congr_cl36_act_q); +-- Port 1 Congruence Class 37 Act +p1_congr_cl37_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl37_act_d, + dout(0) => p1_congr_cl37_act_q); +-- Port 1 Congruence Class 38 Act +p1_congr_cl38_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl38_act_d, + dout(0) => p1_congr_cl38_act_q); +-- Port 1 Congruence Class 39 Act +p1_congr_cl39_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl39_act_d, + dout(0) => p1_congr_cl39_act_q); +-- Port 1 Congruence Class 40 Act +p1_congr_cl40_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl40_act_d, + dout(0) => p1_congr_cl40_act_q); +-- Port 1 Congruence Class 41 Act +p1_congr_cl41_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl41_act_d, + dout(0) => p1_congr_cl41_act_q); +-- Port 1 Congruence Class 42 Act +p1_congr_cl42_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl42_act_d, + dout(0) => p1_congr_cl42_act_q); +-- Port 1 Congruence Class 43 Act +p1_congr_cl43_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl43_act_d, + dout(0) => p1_congr_cl43_act_q); +-- Port 1 Congruence Class 44 Act +p1_congr_cl44_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl44_act_d, + dout(0) => p1_congr_cl44_act_q); +-- Port 1 Congruence Class 45 Act +p1_congr_cl45_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl45_act_d, + dout(0) => p1_congr_cl45_act_q); +-- Port 1 Congruence Class 46 Act +p1_congr_cl46_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl46_act_d, + dout(0) => p1_congr_cl46_act_q); +-- Port 1 Congruence Class 47 Act +p1_congr_cl47_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl47_act_d, + dout(0) => p1_congr_cl47_act_q); +-- Port 1 Congruence Class 48 Act +p1_congr_cl48_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl48_act_d, + dout(0) => p1_congr_cl48_act_q); +-- Port 1 Congruence Class 49 Act +p1_congr_cl49_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl49_act_d, + dout(0) => p1_congr_cl49_act_q); +-- Port 1 Congruence Class 50 Act +p1_congr_cl50_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl50_act_d, + dout(0) => p1_congr_cl50_act_q); +-- Port 1 Congruence Class 51 Act +p1_congr_cl51_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl51_act_d, + dout(0) => p1_congr_cl51_act_q); +-- Port 1 Congruence Class 52 Act +p1_congr_cl52_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl52_act_d, + dout(0) => p1_congr_cl52_act_q); +-- Port 1 Congruence Class 53 Act +p1_congr_cl53_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl53_act_d, + dout(0) => p1_congr_cl53_act_q); +-- Port 1 Congruence Class 54 Act +p1_congr_cl54_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl54_act_d, + dout(0) => p1_congr_cl54_act_q); +-- Port 1 Congruence Class 55 Act +p1_congr_cl55_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl55_act_d, + dout(0) => p1_congr_cl55_act_q); +-- Port 1 Congruence Class 56 Act +p1_congr_cl56_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl56_act_d, + dout(0) => p1_congr_cl56_act_q); +-- Port 1 Congruence Class 57 Act +p1_congr_cl57_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl57_act_d, + dout(0) => p1_congr_cl57_act_q); +-- Port 1 Congruence Class 58 Act +p1_congr_cl58_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl58_act_d, + dout(0) => p1_congr_cl58_act_q); +-- Port 1 Congruence Class 59 Act +p1_congr_cl59_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl59_act_d, + dout(0) => p1_congr_cl59_act_q); +-- Port 1 Congruence Class 60 Act +p1_congr_cl60_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl60_act_d, + dout(0) => p1_congr_cl60_act_q); +-- Port 1 Congruence Class 61 Act +p1_congr_cl61_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl61_act_d, + dout(0) => p1_congr_cl61_act_q); +-- Port 1 Congruence Class 62 Act +p1_congr_cl62_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl62_act_d, + dout(0) => p1_congr_cl62_act_q); +-- Port 1 Congruence Class 63 Act +p1_congr_cl63_act_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => p1_congr_cl63_act_d, + dout(0) => p1_congr_cl63_act_q); +-- Flush Way A Register +flush_wayA_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayA_d, + dout => flush_wayA_q); +flush_wayA_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv4_ex4_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(flush_wayA_data_offset to flush_wayA_data_offset + flush_wayA_data_d'length-1), + scout => sov(flush_wayA_data_offset to flush_wayA_data_offset + flush_wayA_data_d'length-1), + din => flush_wayA_data_d, + dout => flush_wayA_data_q); +flush_wayA_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv5_ex5_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayA_data2_d, + dout => flush_wayA_data2_q); +-- Flush Way B Register +flush_wayB_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayB_d, + dout => flush_wayB_q); +flush_wayB_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv4_ex4_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(flush_wayB_data_offset to flush_wayB_data_offset + flush_wayB_data_d'length-1), + scout => sov(flush_wayB_data_offset to flush_wayB_data_offset + flush_wayB_data_d'length-1), + din => flush_wayB_data_d, + dout => flush_wayB_data_q); +flush_wayB_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv5_ex5_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayB_data2_d, + dout => flush_wayB_data2_q); +-- Flush Way C Register +flush_wayC_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayC_d, + dout => flush_wayC_q); +flush_wayC_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv4_ex4_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(flush_wayC_data_offset to flush_wayC_data_offset + flush_wayC_data_d'length-1), + scout => sov(flush_wayC_data_offset to flush_wayC_data_offset + flush_wayC_data_d'length-1), + din => flush_wayC_data_d, + dout => flush_wayC_data_q); +flush_wayC_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv5_ex5_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayC_data2_d, + dout => flush_wayC_data2_q); +-- Flush Way D Register +flush_wayD_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayD_d, + dout => flush_wayD_q); +flush_wayD_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv4_ex4_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(flush_wayD_data_offset to flush_wayD_data_offset + flush_wayD_data_d'length-1), + scout => sov(flush_wayD_data_offset to flush_wayD_data_offset + flush_wayD_data_d'length-1), + din => flush_wayD_data_d, + dout => flush_wayD_data_q); +flush_wayD_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv5_ex5_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayD_data2_d, + dout => flush_wayD_data2_q); +-- Flush Way E Register +flush_wayE_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayE_d, + dout => flush_wayE_q); +flush_wayE_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv4_ex4_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(flush_wayE_data_offset to flush_wayE_data_offset + flush_wayE_data_d'length-1), + scout => sov(flush_wayE_data_offset to flush_wayE_data_offset + flush_wayE_data_d'length-1), + din => flush_wayE_data_d, + dout => flush_wayE_data_q); +flush_wayE_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv5_ex5_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayE_data2_d, + dout => flush_wayE_data2_q); +-- Flush Way F Register +flush_wayF_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayF_d, + dout => flush_wayF_q); +flush_wayF_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv4_ex4_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(flush_wayF_data_offset to flush_wayF_data_offset + flush_wayF_data_d'length-1), + scout => sov(flush_wayF_data_offset to flush_wayF_data_offset + flush_wayF_data_d'length-1), + din => flush_wayF_data_d, + dout => flush_wayF_data_q); +flush_wayF_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv5_ex5_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayF_data2_d, + dout => flush_wayF_data2_q); +-- Flush Way G Register +flush_wayG_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayG_d, + dout => flush_wayG_q); +flush_wayG_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv4_ex4_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(flush_wayG_data_offset to flush_wayG_data_offset + flush_wayG_data_d'length-1), + scout => sov(flush_wayG_data_offset to flush_wayG_data_offset + flush_wayG_data_d'length-1), + din => flush_wayG_data_d, + dout => flush_wayG_data_q); +flush_wayG_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv5_ex5_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayG_data2_d, + dout => flush_wayG_data2_q); +-- Flush Way H Register +flush_wayH_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayH_d, + dout => flush_wayH_q); +flush_wayH_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv4_ex4_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(flush_wayH_data_offset to flush_wayH_data_offset + flush_wayH_data_d'length-1), + scout => sov(flush_wayH_data_offset to flush_wayH_data_offset + flush_wayH_data_d'length-1), + din => flush_wayH_data_d, + dout => flush_wayH_data_q); +flush_wayH_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv5_ex5_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => flush_wayH_data2_d, + dout => flush_wayH_data2_q); +ex3_flush_cline_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_flush_cline_offset), + scout => sov(ex3_flush_cline_offset), + din => ex3_flush_cline_d, + dout => ex3_flush_cline_q); +ex4_congr_cl_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex4_congr_cl_d, + dout => ex4_congr_cl_q); +ex5_congr_cl_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv4_ex4_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_congr_cl_offset to ex5_congr_cl_offset + ex5_congr_cl_d'length-1), + scout => sov(ex5_congr_cl_offset to ex5_congr_cl_offset + ex5_congr_cl_d'length-1), + din => ex5_congr_cl_d, + dout => ex5_congr_cl_q); +ex6_congr_cl_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv5_ex5_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex6_congr_cl_d, + dout => ex6_congr_cl_q); +ex7_congr_cl_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex7_congr_cl_offset to ex7_congr_cl_offset + ex7_congr_cl_d'length-1), + scout => sov(ex7_congr_cl_offset to ex7_congr_cl_offset + ex7_congr_cl_d'length-1), + din => ex7_congr_cl_d, + dout => ex7_congr_cl_q); +ex8_congr_cl_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex8_congr_cl_offset to ex8_congr_cl_offset + ex8_congr_cl_d'length-1), + scout => sov(ex8_congr_cl_offset to ex8_congr_cl_offset + ex8_congr_cl_d'length-1), + din => ex8_congr_cl_d, + dout => ex8_congr_cl_q); +ex9_congr_cl_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex9_congr_cl_offset to ex9_congr_cl_offset + ex9_congr_cl_d'length-1), + scout => sov(ex9_congr_cl_offset to ex9_congr_cl_offset + ex9_congr_cl_d'length-1), + din => ex9_congr_cl_d, + dout => ex9_congr_cl_q); +wayA_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(wayA_val_b_offset to wayA_val_b_offset + wayA_val_b_q'length-1), + scout => sov(wayA_val_b_offset to wayA_val_b_offset + wayA_val_b_q'length-1), + a1 => wayA_early_stg_pri, + a2 => wayA_stg_val, + b1 => wayA_later_stg_pri, + b2 => wayA_stg_val_b, + qb => wayA_val_b_q); +wayB_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(wayB_val_b_offset to wayB_val_b_offset + wayB_val_b_q'length-1), + scout => sov(wayB_val_b_offset to wayB_val_b_offset + wayB_val_b_q'length-1), + a1 => wayB_early_stg_pri, + a2 => wayB_stg_val, + b1 => wayB_later_stg_pri, + b2 => wayB_stg_val_b, + qb => wayB_val_b_q); +wayC_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(wayC_val_b_offset to wayC_val_b_offset + wayC_val_b_q'length-1), + scout => sov(wayC_val_b_offset to wayC_val_b_offset + wayC_val_b_q'length-1), + a1 => wayC_early_stg_pri, + a2 => wayC_stg_val, + b1 => wayC_later_stg_pri, + b2 => wayC_stg_val_b, + qb => wayC_val_b_q); +wayD_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(wayD_val_b_offset to wayD_val_b_offset + wayD_val_b_q'length-1), + scout => sov(wayD_val_b_offset to wayD_val_b_offset + wayD_val_b_q'length-1), + a1 => wayD_early_stg_pri, + a2 => wayD_stg_val, + b1 => wayD_later_stg_pri, + b2 => wayD_stg_val_b, + qb => wayD_val_b_q); +wayE_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(wayE_val_b_offset to wayE_val_b_offset + wayE_val_b_q'length-1), + scout => sov(wayE_val_b_offset to wayE_val_b_offset + wayE_val_b_q'length-1), + a1 => wayE_early_stg_pri, + a2 => wayE_stg_val, + b1 => wayE_later_stg_pri, + b2 => wayE_stg_val_b, + qb => wayE_val_b_q); +wayF_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(wayF_val_b_offset to wayF_val_b_offset + wayF_val_b_q'length-1), + scout => sov(wayF_val_b_offset to wayF_val_b_offset + wayF_val_b_q'length-1), + a1 => wayF_early_stg_pri, + a2 => wayF_stg_val, + b1 => wayF_later_stg_pri, + b2 => wayF_stg_val_b, + qb => wayF_val_b_q); +wayG_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(wayG_val_b_offset to wayG_val_b_offset + wayG_val_b_q'length-1), + scout => sov(wayG_val_b_offset to wayG_val_b_offset + wayG_val_b_q'length-1), + a1 => wayG_early_stg_pri, + a2 => wayG_stg_val, + b1 => wayG_later_stg_pri, + b2 => wayG_stg_val_b, + qb => wayG_val_b_q); +wayH_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(wayH_val_b_offset to wayH_val_b_offset + wayH_val_b_q'length-1), + scout => sov(wayH_val_b_offset to wayH_val_b_offset + wayH_val_b_q'length-1), + a1 => wayH_early_stg_pri, + a2 => wayH_stg_val, + b1 => wayH_later_stg_pri, + b2 => wayH_stg_val_b, + qb => wayH_val_b_q); +ex3_wayA_fxubyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayA_fxubyp_val_offset), + scout => sov(ex3_wayA_fxubyp_val_offset), + din => ex3_wayA_fxubyp_val_d, + dout => ex3_wayA_fxubyp_val_q); +ex3_wayB_fxubyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayB_fxubyp_val_offset), + scout => sov(ex3_wayB_fxubyp_val_offset), + din => ex3_wayB_fxubyp_val_d, + dout => ex3_wayB_fxubyp_val_q); +ex3_wayC_fxubyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayC_fxubyp_val_offset), + scout => sov(ex3_wayC_fxubyp_val_offset), + din => ex3_wayC_fxubyp_val_d, + dout => ex3_wayC_fxubyp_val_q); +ex3_wayD_fxubyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayD_fxubyp_val_offset), + scout => sov(ex3_wayD_fxubyp_val_offset), + din => ex3_wayD_fxubyp_val_d, + dout => ex3_wayD_fxubyp_val_q); +ex3_wayE_fxubyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayE_fxubyp_val_offset), + scout => sov(ex3_wayE_fxubyp_val_offset), + din => ex3_wayE_fxubyp_val_d, + dout => ex3_wayE_fxubyp_val_q); +ex3_wayF_fxubyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayF_fxubyp_val_offset), + scout => sov(ex3_wayF_fxubyp_val_offset), + din => ex3_wayF_fxubyp_val_d, + dout => ex3_wayF_fxubyp_val_q); +ex3_wayG_fxubyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayG_fxubyp_val_offset), + scout => sov(ex3_wayG_fxubyp_val_offset), + din => ex3_wayG_fxubyp_val_d, + dout => ex3_wayG_fxubyp_val_q); +ex3_wayH_fxubyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayH_fxubyp_val_offset), + scout => sov(ex3_wayH_fxubyp_val_offset), + din => ex3_wayH_fxubyp_val_d, + dout => ex3_wayH_fxubyp_val_q); +ex4_wayA_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayA_fxubyp_val_d, + dout(0) => ex4_wayA_fxubyp_val_q); +ex4_wayB_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayB_fxubyp_val_d, + dout(0) => ex4_wayB_fxubyp_val_q); +ex4_wayC_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayC_fxubyp_val_d, + dout(0) => ex4_wayC_fxubyp_val_q); +ex4_wayD_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayD_fxubyp_val_d, + dout(0) => ex4_wayD_fxubyp_val_q); +ex4_wayE_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayE_fxubyp_val_d, + dout(0) => ex4_wayE_fxubyp_val_q); +ex4_wayF_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayF_fxubyp_val_d, + dout(0) => ex4_wayF_fxubyp_val_q); +ex4_wayG_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayG_fxubyp_val_d, + dout(0) => ex4_wayG_fxubyp_val_q); +ex4_wayH_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayH_fxubyp_val_d, + dout(0) => ex4_wayH_fxubyp_val_q); +ex3_wayA_relbyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayA_relbyp_val_offset), + scout => sov(ex3_wayA_relbyp_val_offset), + din => ex3_wayA_relbyp_val_d, + dout => ex3_wayA_relbyp_val_q); +ex3_wayB_relbyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayB_relbyp_val_offset), + scout => sov(ex3_wayB_relbyp_val_offset), + din => ex3_wayB_relbyp_val_d, + dout => ex3_wayB_relbyp_val_q); +ex3_wayC_relbyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayC_relbyp_val_offset), + scout => sov(ex3_wayC_relbyp_val_offset), + din => ex3_wayC_relbyp_val_d, + dout => ex3_wayC_relbyp_val_q); +ex3_wayD_relbyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayD_relbyp_val_offset), + scout => sov(ex3_wayD_relbyp_val_offset), + din => ex3_wayD_relbyp_val_d, + dout => ex3_wayD_relbyp_val_q); +ex3_wayE_relbyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayE_relbyp_val_offset), + scout => sov(ex3_wayE_relbyp_val_offset), + din => ex3_wayE_relbyp_val_d, + dout => ex3_wayE_relbyp_val_q); +ex3_wayF_relbyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayF_relbyp_val_offset), + scout => sov(ex3_wayF_relbyp_val_offset), + din => ex3_wayF_relbyp_val_d, + dout => ex3_wayF_relbyp_val_q); +ex3_wayG_relbyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayG_relbyp_val_offset), + scout => sov(ex3_wayG_relbyp_val_offset), + din => ex3_wayG_relbyp_val_d, + dout => ex3_wayG_relbyp_val_q); +ex3_wayH_relbyp_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wayH_relbyp_val_offset), + scout => sov(ex3_wayH_relbyp_val_offset), + din => ex3_wayH_relbyp_val_d, + dout => ex3_wayH_relbyp_val_q); +ex4_wayA_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayA_relbyp_val_d, + dout(0) => ex4_wayA_relbyp_val_q); +ex4_wayB_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayB_relbyp_val_d, + dout(0) => ex4_wayB_relbyp_val_q); +ex4_wayC_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayC_relbyp_val_d, + dout(0) => ex4_wayC_relbyp_val_q); +ex4_wayD_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayD_relbyp_val_d, + dout(0) => ex4_wayD_relbyp_val_q); +ex4_wayE_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayE_relbyp_val_d, + dout(0) => ex4_wayE_relbyp_val_q); +ex4_wayF_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayF_relbyp_val_d, + dout(0) => ex4_wayF_relbyp_val_q); +ex4_wayG_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayG_relbyp_val_d, + dout(0) => ex4_wayG_relbyp_val_q); +ex4_wayH_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex4_wayH_relbyp_val_d, + dout(0) => ex4_wayH_relbyp_val_q); +ex4_xuop_wayA_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_xuop_wayA_upd_offset), + scout => sov(ex4_xuop_wayA_upd_offset), + din => ex4_xuop_wayA_upd_d, + dout => ex4_xuop_wayA_upd_q); +ex4_xuop_wayB_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_xuop_wayB_upd_offset), + scout => sov(ex4_xuop_wayB_upd_offset), + din => ex4_xuop_wayB_upd_d, + dout => ex4_xuop_wayB_upd_q); +ex4_xuop_wayC_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_xuop_wayC_upd_offset), + scout => sov(ex4_xuop_wayC_upd_offset), + din => ex4_xuop_wayC_upd_d, + dout => ex4_xuop_wayC_upd_q); +ex4_xuop_wayD_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_xuop_wayD_upd_offset), + scout => sov(ex4_xuop_wayD_upd_offset), + din => ex4_xuop_wayD_upd_d, + dout => ex4_xuop_wayD_upd_q); +ex4_xuop_wayE_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_xuop_wayE_upd_offset), + scout => sov(ex4_xuop_wayE_upd_offset), + din => ex4_xuop_wayE_upd_d, + dout => ex4_xuop_wayE_upd_q); +ex4_xuop_wayF_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_xuop_wayF_upd_offset), + scout => sov(ex4_xuop_wayF_upd_offset), + din => ex4_xuop_wayF_upd_d, + dout => ex4_xuop_wayF_upd_q); +ex4_xuop_wayG_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_xuop_wayG_upd_offset), + scout => sov(ex4_xuop_wayG_upd_offset), + din => ex4_xuop_wayG_upd_d, + dout => ex4_xuop_wayG_upd_q); +ex4_xuop_wayH_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_xuop_wayH_upd_offset), + scout => sov(ex4_xuop_wayH_upd_offset), + din => ex4_xuop_wayH_upd_d, + dout => ex4_xuop_wayH_upd_q); +ex5_xuop_wayA_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_xuop_wayA_upd_offset), + scout => sov(ex5_xuop_wayA_upd_offset), + din => ex5_xuop_wayA_upd_d, + dout => ex5_xuop_wayA_upd_q); +ex5_xuop_wayB_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_xuop_wayB_upd_offset), + scout => sov(ex5_xuop_wayB_upd_offset), + din => ex5_xuop_wayB_upd_d, + dout => ex5_xuop_wayB_upd_q); +ex5_xuop_wayC_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_xuop_wayC_upd_offset), + scout => sov(ex5_xuop_wayC_upd_offset), + din => ex5_xuop_wayC_upd_d, + dout => ex5_xuop_wayC_upd_q); +ex5_xuop_wayD_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_xuop_wayD_upd_offset), + scout => sov(ex5_xuop_wayD_upd_offset), + din => ex5_xuop_wayD_upd_d, + dout => ex5_xuop_wayD_upd_q); +ex5_xuop_wayE_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_xuop_wayE_upd_offset), + scout => sov(ex5_xuop_wayE_upd_offset), + din => ex5_xuop_wayE_upd_d, + dout => ex5_xuop_wayE_upd_q); +ex5_xuop_wayF_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_xuop_wayF_upd_offset), + scout => sov(ex5_xuop_wayF_upd_offset), + din => ex5_xuop_wayF_upd_d, + dout => ex5_xuop_wayF_upd_q); +ex5_xuop_wayG_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_xuop_wayG_upd_offset), + scout => sov(ex5_xuop_wayG_upd_offset), + din => ex5_xuop_wayG_upd_d, + dout => ex5_xuop_wayG_upd_q); +ex5_xuop_wayH_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_xuop_wayH_upd_offset), + scout => sov(ex5_xuop_wayH_upd_offset), + din => ex5_xuop_wayH_upd_d, + dout => ex5_xuop_wayH_upd_q); +inval_clr_lck_wA_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(inval_clr_lck_wA_offset), + scout => sov(inval_clr_lck_wA_offset), + din => inval_clr_lck_wA_d, + dout => inval_clr_lck_wA_q); +inval_clr_lck_wB_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(inval_clr_lck_wB_offset), + scout => sov(inval_clr_lck_wB_offset), + din => inval_clr_lck_wB_d, + dout => inval_clr_lck_wB_q); +inval_clr_lck_wC_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(inval_clr_lck_wC_offset), + scout => sov(inval_clr_lck_wC_offset), + din => inval_clr_lck_wC_d, + dout => inval_clr_lck_wC_q); +inval_clr_lck_wD_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(inval_clr_lck_wD_offset), + scout => sov(inval_clr_lck_wD_offset), + din => inval_clr_lck_wD_d, + dout => inval_clr_lck_wD_q); +inval_clr_lck_wE_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(inval_clr_lck_wE_offset), + scout => sov(inval_clr_lck_wE_offset), + din => inval_clr_lck_wE_d, + dout => inval_clr_lck_wE_q); +inval_clr_lck_wF_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(inval_clr_lck_wF_offset), + scout => sov(inval_clr_lck_wF_offset), + din => inval_clr_lck_wF_d, + dout => inval_clr_lck_wF_q); +inval_clr_lck_wG_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(inval_clr_lck_wG_offset), + scout => sov(inval_clr_lck_wG_offset), + din => inval_clr_lck_wG_d, + dout => inval_clr_lck_wG_q); +inval_clr_lck_wH_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(inval_clr_lck_wH_offset), + scout => sov(inval_clr_lck_wH_offset), + din => inval_clr_lck_wH_d, + dout => inval_clr_lck_wH_q); +ex4_wayA_val_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex4_wayA_val_d, + dout => ex4_wayA_val_q); +ex4_wayB_val_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex4_wayB_val_d, + dout => ex4_wayB_val_q); +ex4_wayC_val_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex4_wayC_val_d, + dout => ex4_wayC_val_q); +ex4_wayD_val_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex4_wayD_val_d, + dout => ex4_wayD_val_q); +ex4_wayE_val_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex4_wayE_val_d, + dout => ex4_wayE_val_q); +ex4_wayF_val_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex4_wayF_val_d, + dout => ex4_wayF_val_q); +ex4_wayG_val_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex4_wayG_val_d, + dout => ex4_wayG_val_q); +ex4_wayH_val_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex4_wayH_val_d, + dout => ex4_wayH_val_q); +congr_cl_m_upd_wayA_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_m_upd_wayA_offset), + scout => sov(congr_cl_m_upd_wayA_offset), + din => congr_cl_m_upd_wayA_d, + dout => congr_cl_m_upd_wayA_q); +congr_cl_m_upd_wayB_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_m_upd_wayB_offset), + scout => sov(congr_cl_m_upd_wayB_offset), + din => congr_cl_m_upd_wayB_d, + dout => congr_cl_m_upd_wayB_q); +congr_cl_m_upd_wayC_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_m_upd_wayC_offset), + scout => sov(congr_cl_m_upd_wayC_offset), + din => congr_cl_m_upd_wayC_d, + dout => congr_cl_m_upd_wayC_q); +congr_cl_m_upd_wayD_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_m_upd_wayD_offset), + scout => sov(congr_cl_m_upd_wayD_offset), + din => congr_cl_m_upd_wayD_d, + dout => congr_cl_m_upd_wayD_q); +congr_cl_m_upd_wayE_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_m_upd_wayE_offset), + scout => sov(congr_cl_m_upd_wayE_offset), + din => congr_cl_m_upd_wayE_d, + dout => congr_cl_m_upd_wayE_q); +congr_cl_m_upd_wayF_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_m_upd_wayF_offset), + scout => sov(congr_cl_m_upd_wayF_offset), + din => congr_cl_m_upd_wayF_d, + dout => congr_cl_m_upd_wayF_q); +congr_cl_m_upd_wayG_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_m_upd_wayG_offset), + scout => sov(congr_cl_m_upd_wayG_offset), + din => congr_cl_m_upd_wayG_d, + dout => congr_cl_m_upd_wayG_q); +congr_cl_m_upd_wayH_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_m_upd_wayH_offset), + scout => sov(congr_cl_m_upd_wayH_offset), + din => congr_cl_m_upd_wayH_d, + dout => congr_cl_m_upd_wayH_q); +ex2_congr_cl_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv1_ex1_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex2_congr_cl_d, + dout => ex2_congr_cl_q); +ex3_congr_cl_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv2_ex2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_congr_cl_offset to ex3_congr_cl_offset + ex3_congr_cl_d'length-1), + scout => sov(ex3_congr_cl_offset to ex3_congr_cl_offset + ex3_congr_cl_d'length-1), + din => ex3_congr_cl_d, + dout => ex3_congr_cl_q); +rel_congr_cl_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_congr_cl_d, + dout => rel_congr_cl_q); +rel24_congr_cl_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel24_congr_cl_offset to rel24_congr_cl_offset + rel24_congr_cl_d'length-1), + scout => sov(rel24_congr_cl_offset to rel24_congr_cl_offset + rel24_congr_cl_d'length-1), + din => rel24_congr_cl_d, + dout => rel24_congr_cl_q); +relu_congr_cl_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => relu_congr_cl_d, + dout => relu_congr_cl_q); +relu_s_congr_cl_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_perr_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(relu_s_congr_cl_offset to relu_s_congr_cl_offset + relu_s_congr_cl_d'length-1), + scout => sov(relu_s_congr_cl_offset to relu_s_congr_cl_offset + relu_s_congr_cl_d'length-1), + din => relu_s_congr_cl_d, + dout => relu_s_congr_cl_q); +reload_way_clr_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_way_clr_offset to reload_way_clr_offset + reload_way_clr_d'length-1), + scout => sov(reload_way_clr_offset to reload_way_clr_offset + reload_way_clr_d'length-1), + din => reload_way_clr_d, + dout => reload_way_clr_q); +ex4_watchSet_coll_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_watchSet_coll_offset), + scout => sov(ex4_watchSet_coll_offset), + din => ex4_watchSet_coll_d, + dout => ex4_watchSet_coll_q); +rel_wayA_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_wayA_val_b_offset to rel_wayA_val_b_offset + rel_wayA_val_b_q'length-1), + scout => sov(rel_wayA_val_b_offset to rel_wayA_val_b_offset + rel_wayA_val_b_q'length-1), + a1 => rel_wayA_early_stg_pri, + a2 => rel_wayA_stg_val, + b1 => rel_wayA_later_stg_pri, + b2 => rel_wayA_stg_val_b, + qb => rel_wayA_val_b_q); +rel_wayB_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_wayB_val_b_offset to rel_wayB_val_b_offset + rel_wayB_val_b_q'length-1), + scout => sov(rel_wayB_val_b_offset to rel_wayB_val_b_offset + rel_wayB_val_b_q'length-1), + a1 => rel_wayB_early_stg_pri, + a2 => rel_wayB_stg_val, + b1 => rel_wayB_later_stg_pri, + b2 => rel_wayB_stg_val_b, + qb => rel_wayB_val_b_q); +rel_wayC_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_wayC_val_b_offset to rel_wayC_val_b_offset + rel_wayC_val_b_q'length-1), + scout => sov(rel_wayC_val_b_offset to rel_wayC_val_b_offset + rel_wayC_val_b_q'length-1), + a1 => rel_wayC_early_stg_pri, + a2 => rel_wayC_stg_val, + b1 => rel_wayC_later_stg_pri, + b2 => rel_wayC_stg_val_b, + qb => rel_wayC_val_b_q); +rel_wayD_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_wayD_val_b_offset to rel_wayD_val_b_offset + rel_wayD_val_b_q'length-1), + scout => sov(rel_wayD_val_b_offset to rel_wayD_val_b_offset + rel_wayD_val_b_q'length-1), + a1 => rel_wayD_early_stg_pri, + a2 => rel_wayD_stg_val, + b1 => rel_wayD_later_stg_pri, + b2 => rel_wayD_stg_val_b, + qb => rel_wayD_val_b_q); +rel_wayE_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_wayE_val_b_offset to rel_wayE_val_b_offset + rel_wayE_val_b_q'length-1), + scout => sov(rel_wayE_val_b_offset to rel_wayE_val_b_offset + rel_wayE_val_b_q'length-1), + a1 => rel_wayE_early_stg_pri, + a2 => rel_wayE_stg_val, + b1 => rel_wayE_later_stg_pri, + b2 => rel_wayE_stg_val_b, + qb => rel_wayE_val_b_q); +rel_wayF_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_wayF_val_b_offset to rel_wayF_val_b_offset + rel_wayF_val_b_q'length-1), + scout => sov(rel_wayF_val_b_offset to rel_wayF_val_b_offset + rel_wayF_val_b_q'length-1), + a1 => rel_wayF_early_stg_pri, + a2 => rel_wayF_stg_val, + b1 => rel_wayF_later_stg_pri, + b2 => rel_wayF_stg_val_b, + qb => rel_wayF_val_b_q); +rel_wayG_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_wayG_val_b_offset to rel_wayG_val_b_offset + rel_wayG_val_b_q'length-1), + scout => sov(rel_wayG_val_b_offset to rel_wayG_val_b_offset + rel_wayG_val_b_q'length-1), + a1 => rel_wayG_early_stg_pri, + a2 => rel_wayG_stg_val, + b1 => rel_wayG_later_stg_pri, + b2 => rel_wayG_stg_val_b, + qb => rel_wayG_val_b_q); +rel_wayH_val_b_reg: tri_aoi22_nlats_wlcb +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_wayH_val_b_offset to rel_wayH_val_b_offset + rel_wayH_val_b_q'length-1), + scout => sov(rel_wayH_val_b_offset to rel_wayH_val_b_offset + rel_wayH_val_b_q'length-1), + a1 => rel_wayH_early_stg_pri, + a2 => rel_wayH_stg_val, + b1 => rel_wayH_later_stg_pri, + b2 => rel_wayH_stg_val_b, + qb => rel_wayH_val_b_q); +rel24_wayA_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayA_fxubyp_val_d, + dout(0) => rel24_wayA_fxubyp_val_q); +rel24_wayB_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayB_fxubyp_val_d, + dout(0) => rel24_wayB_fxubyp_val_q); +rel24_wayC_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayC_fxubyp_val_d, + dout(0) => rel24_wayC_fxubyp_val_q); +rel24_wayD_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayD_fxubyp_val_d, + dout(0) => rel24_wayD_fxubyp_val_q); +rel24_wayE_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayE_fxubyp_val_d, + dout(0) => rel24_wayE_fxubyp_val_q); +rel24_wayF_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayF_fxubyp_val_d, + dout(0) => rel24_wayF_fxubyp_val_q); +rel24_wayG_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayG_fxubyp_val_d, + dout(0) => rel24_wayG_fxubyp_val_q); +rel24_wayH_fxubyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayH_fxubyp_val_d, + dout(0) => rel24_wayH_fxubyp_val_q); +rel24_wayA_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayA_relbyp_val_d, + dout(0) => rel24_wayA_relbyp_val_q); +rel24_wayB_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayB_relbyp_val_d, + dout(0) => rel24_wayB_relbyp_val_q); +rel24_wayC_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayC_relbyp_val_d, + dout(0) => rel24_wayC_relbyp_val_q); +rel24_wayD_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayD_relbyp_val_d, + dout(0) => rel24_wayD_relbyp_val_q); +rel24_wayE_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayE_relbyp_val_d, + dout(0) => rel24_wayE_relbyp_val_q); +rel24_wayF_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayF_relbyp_val_d, + dout(0) => rel24_wayF_relbyp_val_q); +rel24_wayG_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayG_relbyp_val_d, + dout(0) => rel24_wayG_relbyp_val_q); +rel24_wayH_relbyp_val_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => rel24_wayH_relbyp_val_d, + dout(0) => rel24_wayH_relbyp_val_q); +rel_val_stg2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_val_stg2_offset), + scout => sov(rel_val_stg2_offset), + din => rel_val_stg2_d, + dout => rel_val_stg2_q); +rel_val_clr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_val_clr_offset), + scout => sov(rel_val_clr_offset), + din => rel_val_clr_d, + dout => rel_val_clr_q); +rel_port_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_port_upd_offset), + scout => sov(rel_port_upd_offset), + din => rel_port_upd_d, + dout => rel_port_upd_q); +rel_val_stg4_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_val_stg4_offset), + scout => sov(rel_val_stg4_offset), + din => rel_val_stg4_d, + dout => rel_val_stg4_q); +rel_binv_stg4_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_binv_stg4_offset), + scout => sov(rel_binv_stg4_offset), + din => rel_binv_stg4_d, + dout => rel_binv_stg4_q); +back_inval_stg3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(back_inval_stg3_offset), + scout => sov(back_inval_stg3_offset), + din => back_inval_stg3_d, + dout => back_inval_stg3_q); +back_inval_stg4_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(back_inval_stg4_offset), + scout => sov(back_inval_stg4_offset), + din => back_inval_stg4_d, + dout => back_inval_stg4_q); +back_inval_stg5_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(back_inval_stg5_offset), + scout => sov(back_inval_stg5_offset), + din => back_inval_stg5_d, + dout => back_inval_stg5_q); +binv4_ex4_xuop_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv4_ex4_xuop_upd_offset), + scout => sov(binv4_ex4_xuop_upd_offset), + din => binv4_ex4_xuop_upd_d, + dout => binv4_ex4_xuop_upd_q); +binv4_ex4_dir_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv4_ex4_dir_val_offset), + scout => sov(binv4_ex4_dir_val_offset), + din => binv4_ex4_dir_val_d, + dout => binv4_ex4_dir_val_q); +ex4_dir_err_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_dir_err_val_offset), + scout => sov(ex4_dir_err_val_offset), + din => ex4_dir_err_val_d, + dout => ex4_dir_err_val_q); +ex5_dir_err_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_dir_err_val_offset), + scout => sov(ex5_dir_err_val_offset), + din => ex5_dir_err_val_d, + dout => ex5_dir_err_val_q); +ex6_dir_err_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_dir_err_val_offset), + scout => sov(ex6_dir_err_val_offset), + din => ex6_dir_err_val_d, + dout => ex6_dir_err_val_q); +derr2_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(derr2_stg_act_offset), + scout => sov(derr2_stg_act_offset), + din => derr2_stg_act_d, + dout => derr2_stg_act_q); +derr3_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(derr3_stg_act_offset), + scout => sov(derr3_stg_act_offset), + din => derr3_stg_act_d, + dout => derr3_stg_act_q); +derr4_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(derr4_stg_act_offset), + scout => sov(derr4_stg_act_offset), + din => derr4_stg_act_d, + dout => derr4_stg_act_q); +derr5_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(derr5_stg_act_offset), + scout => sov(derr5_stg_act_offset), + din => derr5_stg_act_d, + dout => derr5_stg_act_q); +my_multihit_lcb : entity tri.tri_lcbnd(tri_lcbnd) +generic map (expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + d1clk => my_multihit_d1clk, + d2clk => my_multihit_d2clk, + lclk => my_multihit_lclk); +ex4_dir_multihit_val_b_reg: entity tri.tri_inv_nlats(tri_inv_nlats) +generic map (width => 1, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + lclk => my_multihit_lclk, + d1clk => my_multihit_d1clk, + d2clk => my_multihit_d2clk, + scanin(0) => siv(ex4_dir_multihit_val_b_offset), + scanout(0) => sov(ex4_dir_multihit_val_b_offset), + d(0) => ex3_dir_multihit_val, + qb(0) => ex4_dir_multihit_val_b_q); +my_ddmh_lcb : entity tri.tri_lcbnd(tri_lcbnd) +generic map (expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + d1clk => my_ddmh_d1clk, + d2clk => my_ddmh_d2clk, + lclk => my_ddmh_lclk); +ex4_n_lsu_ddmh_flush_b_reg: entity tri.tri_inv_nlats(tri_inv_nlats) +generic map (width => 4, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + lclk => my_ddmh_lclk, + d1clk => my_ddmh_d1clk, + d2clk => my_ddmh_d2clk, + scanin => siv(ex4_n_lsu_ddmh_flush_b_offset to ex4_n_lsu_ddmh_flush_b_offset + ex4_n_lsu_ddmh_flush_b_d'length-1), + scanout => sov(ex4_n_lsu_ddmh_flush_b_offset to ex4_n_lsu_ddmh_flush_b_offset + ex4_n_lsu_ddmh_flush_b_d'length-1), + d => ex4_n_lsu_ddmh_flush_b_d, + qb => ex4_n_lsu_ddmh_flush_b_q); +dcarr_up_way_addr_reg: entity tri.tri_aoi22_nlats +generic map (width => 3, init => "000", expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + lclk => my_ddmh_lclk, + d1clk => my_ddmh_d1clk, + d2clk => my_ddmh_d2clk, + scanin => siv(dcarr_up_way_addr_offset to dcarr_up_way_addr_offset + dcarr_up_way_addr_q'length-1), + scanout => sov(dcarr_up_way_addr_offset to dcarr_up_way_addr_offset + dcarr_up_way_addr_q'length-1), + a1 => rel_up_way_addr_b, + a2 => rel_dcarr_addr_sel, + b1 => ex3_xuop_up_addr_b, + b2 => rel_dcarr_addr_sel_b, + qb => dcarr_up_way_addr_q); +reload_wayA_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayA_d, + dout => reload_wayA_q); +reload_wayB_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayB_d, + dout => reload_wayB_q); +reload_wayC_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayC_d, + dout => reload_wayC_q); +reload_wayD_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayD_d, + dout => reload_wayD_q); +reload_wayE_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayE_d, + dout => reload_wayE_q); +reload_wayF_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayF_d, + dout => reload_wayF_q); +reload_wayG_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayG_d, + dout => reload_wayG_q); +reload_wayH_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayH_d, + dout => reload_wayH_q); +rel_wayA_val_stg_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_wayA_val_stg_d, + dout => rel_wayA_val_stg_q); +rel_wayB_val_stg_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_wayB_val_stg_d, + dout => rel_wayB_val_stg_q); +rel_wayC_val_stg_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_wayC_val_stg_d, + dout => rel_wayC_val_stg_q); +rel_wayD_val_stg_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_wayD_val_stg_d, + dout => rel_wayD_val_stg_q); +rel_wayE_val_stg_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_wayE_val_stg_d, + dout => rel_wayE_val_stg_q); +rel_wayF_val_stg_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_wayF_val_stg_d, + dout => rel_wayF_val_stg_q); +rel_wayG_val_stg_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_wayG_val_stg_d, + dout => rel_wayG_val_stg_q); +rel_wayH_val_stg_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel2_perr_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => rel_wayH_val_stg_d, + dout => rel_wayH_val_stg_q); +reload_wayA_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_perr_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayA_data_offset to reload_wayA_data_offset + reload_wayA_data_d'length-1), + scout => sov(reload_wayA_data_offset to reload_wayA_data_offset + reload_wayA_data_d'length-1), + din => reload_wayA_data_d, + dout => reload_wayA_data_q); +reload_wayB_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_perr_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayB_data_offset to reload_wayB_data_offset + reload_wayB_data_d'length-1), + scout => sov(reload_wayB_data_offset to reload_wayB_data_offset + reload_wayB_data_d'length-1), + din => reload_wayB_data_d, + dout => reload_wayB_data_q); +reload_wayC_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_perr_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayC_data_offset to reload_wayC_data_offset + reload_wayC_data_d'length-1), + scout => sov(reload_wayC_data_offset to reload_wayC_data_offset + reload_wayC_data_d'length-1), + din => reload_wayC_data_d, + dout => reload_wayC_data_q); +reload_wayD_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_perr_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayD_data_offset to reload_wayD_data_offset + reload_wayD_data_d'length-1), + scout => sov(reload_wayD_data_offset to reload_wayD_data_offset + reload_wayD_data_d'length-1), + din => reload_wayD_data_d, + dout => reload_wayD_data_q); +reload_wayE_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_perr_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayE_data_offset to reload_wayE_data_offset + reload_wayE_data_d'length-1), + scout => sov(reload_wayE_data_offset to reload_wayE_data_offset + reload_wayE_data_d'length-1), + din => reload_wayE_data_d, + dout => reload_wayE_data_q); +reload_wayF_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_perr_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayF_data_offset to reload_wayF_data_offset + reload_wayF_data_d'length-1), + scout => sov(reload_wayF_data_offset to reload_wayF_data_offset + reload_wayF_data_d'length-1), + din => reload_wayF_data_d, + dout => reload_wayF_data_q); +reload_wayG_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_perr_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayG_data_offset to reload_wayG_data_offset + reload_wayG_data_d'length-1), + scout => sov(reload_wayG_data_offset to reload_wayG_data_offset + reload_wayG_data_d'length-1), + din => reload_wayG_data_d, + dout => reload_wayG_data_q); +reload_wayH_data_reg: tri_rlmreg_p +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel3_perr_stg_act_q, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayH_data_offset to reload_wayH_data_offset + reload_wayH_data_d'length-1), + scout => sov(reload_wayH_data_offset to reload_wayH_data_offset + reload_wayH_data_d'length-1), + din => reload_wayH_data_d, + dout => reload_wayH_data_q); +reload_wayA_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel4_perr_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayA_data2_d, + dout => reload_wayA_data2_q); +reload_wayB_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel4_perr_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayB_data2_d, + dout => reload_wayB_data2_q); +reload_wayC_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel4_perr_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayC_data2_d, + dout => reload_wayC_data2_q); +reload_wayD_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel4_perr_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayD_data2_d, + dout => reload_wayD_data2_q); +reload_wayE_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel4_perr_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayE_data2_d, + dout => reload_wayE_data2_q); +reload_wayF_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel4_perr_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayF_data2_d, + dout => reload_wayF_data2_q); +reload_wayG_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel4_perr_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayG_data2_d, + dout => reload_wayG_data2_q); +reload_wayH_data2_reg: tri_regk +generic map (width => 6, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel4_perr_stg_act_q, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => reload_wayH_data2_d, + dout => reload_wayH_data2_q); +binv_wayA_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayA_upd_offset), + scout => sov(binv_wayA_upd_offset), + din => binv_wayA_upd_d, + dout => binv_wayA_upd_q); +binv_wayB_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayB_upd_offset), + scout => sov(binv_wayB_upd_offset), + din => binv_wayB_upd_d, + dout => binv_wayB_upd_q); +binv_wayC_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayC_upd_offset), + scout => sov(binv_wayC_upd_offset), + din => binv_wayC_upd_d, + dout => binv_wayC_upd_q); +binv_wayD_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayD_upd_offset), + scout => sov(binv_wayD_upd_offset), + din => binv_wayD_upd_d, + dout => binv_wayD_upd_q); +binv_wayE_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayE_upd_offset), + scout => sov(binv_wayE_upd_offset), + din => binv_wayE_upd_d, + dout => binv_wayE_upd_q); +binv_wayF_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayF_upd_offset), + scout => sov(binv_wayF_upd_offset), + din => binv_wayF_upd_d, + dout => binv_wayF_upd_q); +binv_wayG_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayG_upd_offset), + scout => sov(binv_wayG_upd_offset), + din => binv_wayG_upd_d, + dout => binv_wayG_upd_q); +binv_wayH_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayH_upd_offset), + scout => sov(binv_wayH_upd_offset), + din => binv_wayH_upd_d, + dout => binv_wayH_upd_q); +binv_wayA_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayA_upd2_offset), + scout => sov(binv_wayA_upd2_offset), + din => binv_wayA_upd2_d, + dout => binv_wayA_upd2_q); +binv_wayB_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayB_upd2_offset), + scout => sov(binv_wayB_upd2_offset), + din => binv_wayB_upd2_d, + dout => binv_wayB_upd2_q); +binv_wayC_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayC_upd2_offset), + scout => sov(binv_wayC_upd2_offset), + din => binv_wayC_upd2_d, + dout => binv_wayC_upd2_q); +binv_wayD_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayD_upd2_offset), + scout => sov(binv_wayD_upd2_offset), + din => binv_wayD_upd2_d, + dout => binv_wayD_upd2_q); +binv_wayE_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayE_upd2_offset), + scout => sov(binv_wayE_upd2_offset), + din => binv_wayE_upd2_d, + dout => binv_wayE_upd2_q); +binv_wayF_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayF_upd2_offset), + scout => sov(binv_wayF_upd2_offset), + din => binv_wayF_upd2_d, + dout => binv_wayF_upd2_q); +binv_wayG_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayG_upd2_offset), + scout => sov(binv_wayG_upd2_offset), + din => binv_wayG_upd2_d, + dout => binv_wayG_upd2_q); +binv_wayH_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayH_upd2_offset), + scout => sov(binv_wayH_upd2_offset), + din => binv_wayH_upd2_d, + dout => binv_wayH_upd2_q); +binv_wayA_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayA_upd3_offset), + scout => sov(binv_wayA_upd3_offset), + din => binv_wayA_upd3_d, + dout => binv_wayA_upd3_q); +binv_wayB_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayB_upd3_offset), + scout => sov(binv_wayB_upd3_offset), + din => binv_wayB_upd3_d, + dout => binv_wayB_upd3_q); +binv_wayC_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayC_upd3_offset), + scout => sov(binv_wayC_upd3_offset), + din => binv_wayC_upd3_d, + dout => binv_wayC_upd3_q); +binv_wayD_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayD_upd3_offset), + scout => sov(binv_wayD_upd3_offset), + din => binv_wayD_upd3_d, + dout => binv_wayD_upd3_q); +binv_wayE_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayE_upd3_offset), + scout => sov(binv_wayE_upd3_offset), + din => binv_wayE_upd3_d, + dout => binv_wayE_upd3_q); +binv_wayF_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayF_upd3_offset), + scout => sov(binv_wayF_upd3_offset), + din => binv_wayF_upd3_d, + dout => binv_wayF_upd3_q); +binv_wayG_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayG_upd3_offset), + scout => sov(binv_wayG_upd3_offset), + din => binv_wayG_upd3_d, + dout => binv_wayG_upd3_q); +binv_wayH_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv_wayH_upd3_offset), + scout => sov(binv_wayH_upd3_offset), + din => binv_wayH_upd3_d, + dout => binv_wayH_upd3_q); +reload_wayA_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayA_upd_offset), + scout => sov(reload_wayA_upd_offset), + din => reload_wayA_upd_d, + dout => reload_wayA_upd_q); +reload_wayB_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayB_upd_offset), + scout => sov(reload_wayB_upd_offset), + din => reload_wayB_upd_d, + dout => reload_wayB_upd_q); +reload_wayC_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayC_upd_offset), + scout => sov(reload_wayC_upd_offset), + din => reload_wayC_upd_d, + dout => reload_wayC_upd_q); +reload_wayD_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayD_upd_offset), + scout => sov(reload_wayD_upd_offset), + din => reload_wayD_upd_d, + dout => reload_wayD_upd_q); +reload_wayE_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayE_upd_offset), + scout => sov(reload_wayE_upd_offset), + din => reload_wayE_upd_d, + dout => reload_wayE_upd_q); +reload_wayF_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayF_upd_offset), + scout => sov(reload_wayF_upd_offset), + din => reload_wayF_upd_d, + dout => reload_wayF_upd_q); +reload_wayG_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayG_upd_offset), + scout => sov(reload_wayG_upd_offset), + din => reload_wayG_upd_d, + dout => reload_wayG_upd_q); +reload_wayH_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayH_upd_offset), + scout => sov(reload_wayH_upd_offset), + din => reload_wayH_upd_d, + dout => reload_wayH_upd_q); +reload_wayA_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayA_upd2_offset), + scout => sov(reload_wayA_upd2_offset), + din => reload_wayA_upd2_d, + dout => reload_wayA_upd2_q); +reload_wayB_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayB_upd2_offset), + scout => sov(reload_wayB_upd2_offset), + din => reload_wayB_upd2_d, + dout => reload_wayB_upd2_q); +reload_wayC_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayC_upd2_offset), + scout => sov(reload_wayC_upd2_offset), + din => reload_wayC_upd2_d, + dout => reload_wayC_upd2_q); +reload_wayD_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayD_upd2_offset), + scout => sov(reload_wayD_upd2_offset), + din => reload_wayD_upd2_d, + dout => reload_wayD_upd2_q); +reload_wayE_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayE_upd2_offset), + scout => sov(reload_wayE_upd2_offset), + din => reload_wayE_upd2_d, + dout => reload_wayE_upd2_q); +reload_wayF_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayF_upd2_offset), + scout => sov(reload_wayF_upd2_offset), + din => reload_wayF_upd2_d, + dout => reload_wayF_upd2_q); +reload_wayG_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayG_upd2_offset), + scout => sov(reload_wayG_upd2_offset), + din => reload_wayG_upd2_d, + dout => reload_wayG_upd2_q); +reload_wayH_upd2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayH_upd2_offset), + scout => sov(reload_wayH_upd2_offset), + din => reload_wayH_upd2_d, + dout => reload_wayH_upd2_q); +reload_wayA_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayA_upd3_offset), + scout => sov(reload_wayA_upd3_offset), + din => reload_wayA_upd3_d, + dout => reload_wayA_upd3_q); +reload_wayB_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayB_upd3_offset), + scout => sov(reload_wayB_upd3_offset), + din => reload_wayB_upd3_d, + dout => reload_wayB_upd3_q); +reload_wayC_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayC_upd3_offset), + scout => sov(reload_wayC_upd3_offset), + din => reload_wayC_upd3_d, + dout => reload_wayC_upd3_q); +reload_wayD_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayD_upd3_offset), + scout => sov(reload_wayD_upd3_offset), + din => reload_wayD_upd3_d, + dout => reload_wayD_upd3_q); +reload_wayE_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayE_upd3_offset), + scout => sov(reload_wayE_upd3_offset), + din => reload_wayE_upd3_d, + dout => reload_wayE_upd3_q); +reload_wayF_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayF_upd3_offset), + scout => sov(reload_wayF_upd3_offset), + din => reload_wayF_upd3_d, + dout => reload_wayF_upd3_q); +reload_wayG_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayG_upd3_offset), + scout => sov(reload_wayG_upd3_offset), + din => reload_wayG_upd3_d, + dout => reload_wayG_upd3_q); +reload_wayH_upd3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(reload_wayH_upd3_offset), + scout => sov(reload_wayH_upd3_offset), + din => reload_wayH_upd3_d, + dout => reload_wayH_upd3_q); +ex3_store_instr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_store_instr_offset), + scout => sov(ex3_store_instr_offset), + din => ex3_store_instr_d, + dout => ex3_store_instr_q); +ex3_lock_set_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_lock_set_offset), + scout => sov(ex3_lock_set_offset), + din => ex3_lock_set_d, + dout => ex3_lock_set_q); +ex4_lock_set_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_lock_set_offset), + scout => sov(ex4_lock_set_offset), + din => ex4_lock_set_d, + dout => ex4_lock_set_q); +ex5_lock_set_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_lock_set_offset), + scout => sov(ex5_lock_set_offset), + din => ex5_lock_set_d, + dout => ex5_lock_set_q); +ex3_lock_clr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_lock_clr_offset), + scout => sov(ex3_lock_clr_offset), + din => ex3_lock_clr_d, + dout => ex3_lock_clr_q); +ex3_xuop_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_xuop_val_offset), + scout => sov(ex3_xuop_val_offset), + din => ex3_xuop_val_d, + dout => ex3_xuop_val_q); +ex4_xuop_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_xuop_val_offset), + scout => sov(ex4_xuop_val_offset), + din => ex4_xuop_val_d, + dout => ex4_xuop_val_q); +ex5_xuop_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_xuop_val_offset), + scout => sov(ex5_xuop_val_offset), + din => ex5_xuop_val_d, + dout => ex5_xuop_val_q); +ex4_l_fld_b1_reg: tri_regk +generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex4_l_fld_b1_d, + dout(0) => ex4_l_fld_b1_q); +ex4_instr_enc_reg: tri_regk +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex4_instr_enc_d, + dout => ex4_instr_enc_q); +rel_lock_set_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_lock_set_offset), + scout => sov(rel_lock_set_offset), + din => rel_lock_set_d, + dout => rel_lock_set_q); +dcpar_err_stg1_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dcpar_err_stg1_offset), + scout => sov(dcpar_err_stg1_offset), + din => dcpar_err_stg1_d, + dout => dcpar_err_stg1_q); +dcpar_err_stg2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dcpar_err_stg2_offset), + scout => sov(dcpar_err_stg2_offset), + din => dcpar_err_stg2_d, + dout => dcpar_err_stg2_q); +dcpar_err_way_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dcpar_err_way_offset to dcpar_err_way_offset + dcpar_err_way_d'length-1), + scout => sov(dcpar_err_way_offset to dcpar_err_way_offset + dcpar_err_way_d'length-1), + din => dcpar_err_way_d, + dout => dcpar_err_way_q); +dcpar_err_way_inval_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dcpar_err_way_inval_offset to dcpar_err_way_inval_offset + dcpar_err_way_inval_d'length-1), + scout => sov(dcpar_err_way_inval_offset to dcpar_err_way_inval_offset + dcpar_err_way_inval_d'length-1), + din => dcpar_err_way_inval_d, + dout => dcpar_err_way_inval_q); +dcpar_err_cntr_reg: tri_rlmreg_p +generic map (width => 2, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dcpar_err_cntr_offset to dcpar_err_cntr_offset + dcpar_err_cntr_d'length-1), + scout => sov(dcpar_err_cntr_offset to dcpar_err_cntr_offset + dcpar_err_cntr_d'length-1), + din => dcpar_err_cntr_d, + dout => dcpar_err_cntr_q); +dcpar_err_ind_sel_reg: tri_rlmreg_p +generic map (width => 2, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dcpar_err_ind_sel_offset to dcpar_err_ind_sel_offset + dcpar_err_ind_sel_d'length-1), + scout => sov(dcpar_err_ind_sel_offset to dcpar_err_ind_sel_offset + dcpar_err_ind_sel_d'length-1), + din => dcpar_err_ind_sel_d, + dout => dcpar_err_ind_sel_q); +dcpar_err_push_queue_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dcpar_err_push_queue_offset), + scout => sov(dcpar_err_push_queue_offset), + din => dcpar_err_push_queue_d, + dout => dcpar_err_push_queue_q); +ex4_way_hit_reg: tri_regk +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv3_ex3_val_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => ex4_way_hit_d, + dout => ex4_way_hit_q); +ex5_way_hit_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv4_ex4_val_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_way_hit_offset to ex5_way_hit_offset + ex5_way_hit_d'length-1), + scout => sov(ex5_way_hit_offset to ex5_way_hit_offset + ex5_way_hit_d'length-1), + din => ex5_way_hit_d, + dout => ex5_way_hit_q); +ex6_way_hit_reg: tri_regk +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex5_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex6_way_hit_d, + dout => ex6_way_hit_q); +ex7_way_hit_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex7_way_hit_offset to ex7_way_hit_offset + ex7_way_hit_d'length-1), + scout => sov(ex7_way_hit_offset to ex7_way_hit_offset + ex7_way_hit_d'length-1), + din => ex7_way_hit_d, + dout => ex7_way_hit_q); +ex8_way_hit_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex8_way_hit_offset to ex8_way_hit_offset + ex8_way_hit_d'length-1), + scout => sov(ex8_way_hit_offset to ex8_way_hit_offset + ex8_way_hit_d'length-1), + din => ex8_way_hit_d, + dout => ex8_way_hit_q); +ex9_way_hit_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex9_way_hit_offset to ex9_way_hit_offset + ex9_way_hit_d'length-1), + scout => sov(ex9_way_hit_offset to ex9_way_hit_offset + ex9_way_hit_d'length-1), + din => ex9_way_hit_d, + dout => ex9_way_hit_q); +ex4_lose_watch_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_lose_watch_offset to ex4_lose_watch_offset + ex4_lose_watch_d'length-1), + scout => sov(ex4_lose_watch_offset to ex4_lose_watch_offset + ex4_lose_watch_d'length-1), + din => ex4_lose_watch_d, + dout => ex4_lose_watch_q); +xucr0_cslc_xuop_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(xucr0_cslc_xuop_offset), + scout => sov(xucr0_cslc_xuop_offset), + din => xucr0_cslc_xuop_d, + dout => xucr0_cslc_xuop_q); +xucr0_cslc_binv_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(xucr0_cslc_binv_offset), + scout => sov(xucr0_cslc_binv_offset), + din => xucr0_cslc_binv_d, + dout => xucr0_cslc_binv_q); +dci_compl_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dci_compl_offset), + scout => sov(dci_compl_offset), + din => dci_compl_d, + dout => dci_compl_q); +dci_inval_all_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dci_inval_all_offset), + scout => sov(dci_inval_all_offset), + din => dci_inval_all_d, + dout => dci_inval_all_q); +inv2_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(inv2_val_offset), + scout => sov(inv2_val_offset), + din => inv2_val_d, + dout => inv2_val_q); +perf_lsu_evnts_reg: tri_rlmreg_p +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(perf_lsu_evnts_offset to perf_lsu_evnts_offset + perf_lsu_evnts_d'length-1), + scout => sov(perf_lsu_evnts_offset to perf_lsu_evnts_offset + perf_lsu_evnts_d'length-1), + din => perf_lsu_evnts_d, + dout => perf_lsu_evnts_q); +lock_flash_clear_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(lock_flash_clear_offset), + scout => sov(lock_flash_clear_offset), + din => lock_flash_clear_d, + dout => lock_flash_clear_q); +lock_flash_clear_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(lock_flash_clear_val_offset), + scout => sov(lock_flash_clear_val_offset), + din => lock_flash_clear_val_d, + dout => lock_flash_clear_val_q); +rel_port_wren_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_port_wren_offset), + scout => sov(rel_port_wren_offset), + din => rel_port_wren_d, + dout => rel_port_wren_q); +ex2_thrd_id_reg: tri_regk +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex1_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex2_thrd_id_d, + dout => ex2_thrd_id_q); +ex3_thrd_id_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_thrd_id_offset to ex3_thrd_id_offset + ex3_thrd_id_d'length-1), + scout => sov(ex3_thrd_id_offset to ex3_thrd_id_offset + ex3_thrd_id_d'length-1), + din => ex3_thrd_id_d, + dout => ex3_thrd_id_q); +ex4_thrd_id_reg: tri_regk +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex3_stg_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex4_thrd_id_d, + dout => ex4_thrd_id_q); +ex5_thrd_id_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex4_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_thrd_id_offset to ex5_thrd_id_offset + ex5_thrd_id_d'length-1), + scout => sov(ex5_thrd_id_offset to ex5_thrd_id_offset + ex5_thrd_id_d'length-1), + din => ex5_thrd_id_d, + dout => ex5_thrd_id_q); +ex3_l_fld_b1_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_l_fld_b1_offset), + scout => sov(ex3_l_fld_b1_offset), + din => ex3_l_fld_b1_d, + dout => ex3_l_fld_b1_q); +ex3_watch_set_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_watch_set_offset), + scout => sov(ex3_watch_set_offset), + din => ex3_watch_set_d, + dout => ex3_watch_set_q); +ex4_watch_set_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_watch_set_offset), + scout => sov(ex4_watch_set_offset), + din => ex4_watch_set_d, + dout => ex4_watch_set_q); +ex5_watch_set_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_watch_set_offset), + scout => sov(ex5_watch_set_offset), + din => ex5_watch_set_d, + dout => ex5_watch_set_q); +ex3_watch_clr_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_watch_clr_offset), + scout => sov(ex3_watch_clr_offset), + din => ex3_watch_clr_d, + dout => ex3_watch_clr_q); +ex3_watch_clr_all_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_watch_clr_all_offset), + scout => sov(ex3_watch_clr_all_offset), + din => ex3_watch_clr_all_d, + dout => ex3_watch_clr_all_q); +ex3_watch_chk_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_watch_chk_offset), + scout => sov(ex3_watch_chk_offset), + din => ex3_watch_chk_d, + dout => ex3_watch_chk_q); +ex4_watch_chk_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_watch_chk_offset), + scout => sov(ex4_watch_chk_offset), + din => ex4_watch_chk_d, + dout => ex4_watch_chk_q); +ex5_watch_chk_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_watch_chk_offset), + scout => sov(ex5_watch_chk_offset), + din => ex5_watch_chk_d, + dout => ex5_watch_chk_q); +ex3_wclr_all_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wclr_all_upd_offset), + scout => sov(ex3_wclr_all_upd_offset), + din => ex3_wclr_all_upd_d, + dout => ex3_wclr_all_upd_q); +ex4_wclr_all_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_wclr_all_val_offset), + scout => sov(ex4_wclr_all_val_offset), + din => ex4_wclr_all_val_d, + dout => ex4_wclr_all_val_q); +ex5_wclr_all_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_wclr_all_val_offset), + scout => sov(ex5_wclr_all_val_offset), + din => ex5_wclr_all_val_d, + dout => ex5_wclr_all_val_q); +ex6_wclr_all_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_wclr_all_val_offset), + scout => sov(ex6_wclr_all_val_offset), + din => ex6_wclr_all_val_d, + dout => ex6_wclr_all_val_q); +rel_thrd_id_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_thrd_id_offset to rel_thrd_id_offset + rel_thrd_id_d'length-1), + scout => sov(rel_thrd_id_offset to rel_thrd_id_offset + rel_thrd_id_d'length-1), + din => rel_thrd_id_d, + dout => rel_thrd_id_q); +rel_watch_set_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => rel1_perr_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_watch_set_offset), + scout => sov(rel_watch_set_offset), + din => rel_watch_set_d, + dout => rel_watch_set_q); +ex5_cr_watch_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_cr_watch_offset), + scout => sov(ex5_cr_watch_offset), + din => ex5_cr_watch_d, + dout => ex5_cr_watch_q); +ex4_watch_clr_all_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_watch_clr_all_offset to ex4_watch_clr_all_offset + ex4_watch_clr_all_d'length-1), + scout => sov(ex4_watch_clr_all_offset to ex4_watch_clr_all_offset + ex4_watch_clr_all_d'length-1), + din => ex4_watch_clr_all_d, + dout => ex4_watch_clr_all_q); +ex5_watch_clr_all_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_watch_clr_all_offset to ex5_watch_clr_all_offset + ex5_watch_clr_all_d'length-1), + scout => sov(ex5_watch_clr_all_offset to ex5_watch_clr_all_offset + ex5_watch_clr_all_d'length-1), + din => ex5_watch_clr_all_d, + dout => ex5_watch_clr_all_q); +ex6_watch_clr_all_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_watch_clr_all_offset to ex6_watch_clr_all_offset + ex6_watch_clr_all_d'length-1), + scout => sov(ex6_watch_clr_all_offset to ex6_watch_clr_all_offset + ex6_watch_clr_all_d'length-1), + din => ex6_watch_clr_all_d, + dout => ex6_watch_clr_all_q); +ex5_watch_clr_all_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_watch_clr_all_val_offset), + scout => sov(ex5_watch_clr_all_val_offset), + din => ex5_watch_clr_all_val_d, + dout => ex5_watch_clr_all_val_q); +ex5_lost_watch_upd_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_lost_watch_upd_offset to ex5_lost_watch_upd_offset + ex5_lost_watch_upd_d'length-1), + scout => sov(ex5_lost_watch_upd_offset to ex5_lost_watch_upd_offset + ex5_lost_watch_upd_d'length-1), + din => ex5_lost_watch_upd_d, + dout => ex5_lost_watch_upd_q); +ex4_watchlost_set_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_watchlost_set_offset to ex4_watchlost_set_offset + ex4_watchlost_set_d'length-1), + scout => sov(ex4_watchlost_set_offset to ex4_watchlost_set_offset + ex4_watchlost_set_d'length-1), + din => ex4_watchlost_set_d, + dout => ex4_watchlost_set_q); +ex5_watchlost_set_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_watchlost_set_offset to ex5_watchlost_set_offset + ex5_watchlost_set_d'length-1), + scout => sov(ex5_watchlost_set_offset to ex5_watchlost_set_offset + ex5_watchlost_set_d'length-1), + din => ex5_watchlost_set_d, + dout => ex5_watchlost_set_q); +rel_lost_watch_binv_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_lost_watch_binv_offset to rel_lost_watch_binv_offset + rel_lost_watch_binv_d'length-1), + scout => sov(rel_lost_watch_binv_offset to rel_lost_watch_binv_offset + rel_lost_watch_binv_d'length-1), + din => rel_lost_watch_binv_d, + dout => rel_lost_watch_binv_q); +lost_watch_evict_ovl_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(lost_watch_evict_ovl_offset to lost_watch_evict_ovl_offset + lost_watch_evict_ovl_d'length-1), + scout => sov(lost_watch_evict_ovl_offset to lost_watch_evict_ovl_offset + lost_watch_evict_ovl_d'length-1), + din => lost_watch_evict_ovl_d, + dout => lost_watch_evict_ovl_q); +rel_lost_watch_upd_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_lost_watch_upd_offset to rel_lost_watch_upd_offset + rel_lost_watch_upd_d'length-1), + scout => sov(rel_lost_watch_upd_offset to rel_lost_watch_upd_offset + rel_lost_watch_upd_d'length-1), + din => rel_lost_watch_upd_d, + dout => rel_lost_watch_upd_q); +lost_watch_evict_val_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(lost_watch_evict_val_offset to lost_watch_evict_val_offset + lost_watch_evict_val_d'length-1), + scout => sov(lost_watch_evict_val_offset to lost_watch_evict_val_offset + lost_watch_evict_val_d'length-1), + din => lost_watch_evict_val_d, + dout => lost_watch_evict_val_q); +lost_watch_inter_thrd_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(lost_watch_inter_thrd_offset to lost_watch_inter_thrd_offset + lost_watch_inter_thrd_d'length-1), + scout => sov(lost_watch_inter_thrd_offset to lost_watch_inter_thrd_offset + lost_watch_inter_thrd_d'length-1), + din => lost_watch_inter_thrd_d, + dout => lost_watch_inter_thrd_q); +stm_watchlost_state_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(stm_watchlost_state_offset to stm_watchlost_state_offset + stm_watchlost_state_d'length-1), + scout => sov(stm_watchlost_state_offset to stm_watchlost_state_offset + stm_watchlost_state_d'length-1), + din => stm_watchlost_state_d, + dout => stm_watchlost_state_q); +ex5_xuop_p0_upd_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_xuop_p0_upd_offset), + scout => sov(ex5_xuop_p0_upd_offset), + din => ex5_xuop_p0_upd_d, + dout => ex5_xuop_p0_upd_q); +rel_val_stgu_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_val_stgu_offset), + scout => sov(rel_val_stgu_offset), + din => rel_val_stgu_d, + dout => rel_val_stgu_q); +p0_wren_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(p0_wren_offset), + scout => sov(p0_wren_offset), + din => p0_wren_d, + dout => p0_wren_q); +p0_wren_cpy_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(p0_wren_cpy_offset), + scout => sov(p0_wren_cpy_offset), + din => p0_wren_cpy_d, + dout => p0_wren_cpy_q); +p0_wren_stg_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(p0_wren_stg_offset), + scout => sov(p0_wren_stg_offset), + din => p0_wren_stg_d, + dout => p0_wren_stg_q); +p1_wren_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(p1_wren_offset), + scout => sov(p1_wren_offset), + din => p1_wren_d, + dout => p1_wren_q); +p1_wren_cpy_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(p1_wren_cpy_offset), + scout => sov(p1_wren_cpy_offset), + din => p1_wren_cpy_d, + dout => p1_wren_cpy_q); +ex3_thrd_m_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_thrd_m_offset), + scout => sov(ex3_thrd_m_offset), + din => ex3_thrd_m_d, + dout => ex3_thrd_m_q); +ex4_thrd_m_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_thrd_m_offset), + scout => sov(ex4_thrd_m_offset), + din => ex4_thrd_m_d, + dout => ex4_thrd_m_q); +ex5_thrd_m_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_thrd_m_offset), + scout => sov(ex5_thrd_m_offset), + din => ex5_thrd_m_d, + dout => ex5_thrd_m_q); +ex6_thrd_m_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_thrd_m_offset), + scout => sov(ex6_thrd_m_offset), + din => ex6_thrd_m_d, + dout => ex6_thrd_m_q); +ex7_ld_par_err_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex7_ld_par_err_offset), + scout => sov(ex7_ld_par_err_offset), + din => ex7_ld_par_err_d, + dout => ex7_ld_par_err_q); +ex8_ld_par_err_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex8_ld_par_err_offset), + scout => sov(ex8_ld_par_err_offset), + din => ex8_ld_par_err_d, + dout => ex8_ld_par_err_q); +ex9_ld_par_err_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex9_ld_par_err_offset), + scout => sov(ex9_ld_par_err_offset), + din => ex9_ld_par_err_d, + dout => ex9_ld_par_err_q); +ex6_ld_valid_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_ld_valid_offset), + scout => sov(ex6_ld_valid_offset), + din => ex6_ld_valid_d, + dout => ex6_ld_valid_q); +ex7_ld_valid_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex7_ld_valid_offset), + scout => sov(ex7_ld_valid_offset), + din => ex7_ld_valid_d, + dout => ex7_ld_valid_q); +ex8_ld_valid_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex8_ld_valid_offset), + scout => sov(ex8_ld_valid_offset), + din => ex8_ld_valid_d, + dout => ex8_ld_valid_q); +ex9_ld_valid_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex9_ld_valid_offset), + scout => sov(ex9_ld_valid_offset), + din => ex9_ld_valid_d, + dout => ex9_ld_valid_q); +rel_in_progress_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_in_progress_offset), + scout => sov(rel_in_progress_offset), + din => rel_in_progress_d, + dout => rel_in_progress_q); +inj_dir_multihit_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(inj_dir_multihit_offset), + scout => sov(inj_dir_multihit_offset), + din => inj_dir_multihit_d, + dout => inj_dir_multihit_q); +congr_cl_ex2_ex3_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex2_ex3_cmp_offset), + scout => sov(congr_cl_ex2_ex3_cmp_offset), + din => congr_cl_ex2_ex3_cmp_d, + dout => congr_cl_ex2_ex3_cmp_q); +congr_cl_ex2_ex4_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex2_ex4_cmp_offset), + scout => sov(congr_cl_ex2_ex4_cmp_offset), + din => congr_cl_ex2_ex4_cmp_d, + dout => congr_cl_ex2_ex4_cmp_q); +congr_cl_ex2_ex5_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex2_ex5_cmp_offset), + scout => sov(congr_cl_ex2_ex5_cmp_offset), + din => congr_cl_ex2_ex5_cmp_d, + dout => congr_cl_ex2_ex5_cmp_q); +congr_cl_ex2_ex6_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex2_ex6_cmp_offset), + scout => sov(congr_cl_ex2_ex6_cmp_offset), + din => congr_cl_ex2_ex6_cmp_d, + dout => congr_cl_ex2_ex6_cmp_q); +congr_cl_ex3_ex4_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex3_ex4_cmp_offset), + scout => sov(congr_cl_ex3_ex4_cmp_offset), + din => congr_cl_ex3_ex4_cmp_d, + dout => congr_cl_ex3_ex4_cmp_q); +congr_cl_ex3_ex5_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex3_ex5_cmp_offset), + scout => sov(congr_cl_ex3_ex5_cmp_offset), + din => congr_cl_ex3_ex5_cmp_d, + dout => congr_cl_ex3_ex5_cmp_q); +congr_cl_ex3_ex6_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex3_ex6_cmp_offset), + scout => sov(congr_cl_ex3_ex6_cmp_offset), + din => congr_cl_ex3_ex6_cmp_d, + dout => congr_cl_ex3_ex6_cmp_q); +congr_cl_ex4_ex5_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex4_ex5_cmp_offset), + scout => sov(congr_cl_ex4_ex5_cmp_offset), + din => congr_cl_ex4_ex5_cmp_d, + dout => congr_cl_ex4_ex5_cmp_q); +congr_cl_ex4_ex6_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex4_ex6_cmp_offset), + scout => sov(congr_cl_ex4_ex6_cmp_offset), + din => congr_cl_ex4_ex6_cmp_d, + dout => congr_cl_ex4_ex6_cmp_q); +congr_cl_ex4_ex7_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex4_ex7_cmp_offset), + scout => sov(congr_cl_ex4_ex7_cmp_offset), + din => congr_cl_ex4_ex7_cmp_d, + dout => congr_cl_ex4_ex7_cmp_q); +congr_cl_ex2_relu_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex2_relu_cmp_offset), + scout => sov(congr_cl_ex2_relu_cmp_offset), + din => congr_cl_ex2_relu_cmp_d, + dout => congr_cl_ex2_relu_cmp_q); +congr_cl_ex2_relu_s_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex2_relu_s_cmp_offset), + scout => sov(congr_cl_ex2_relu_s_cmp_offset), + din => congr_cl_ex2_relu_s_cmp_d, + dout => congr_cl_ex2_relu_s_cmp_q); +congr_cl_ex2_rel_upd_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_ex2_rel_upd_cmp_offset), + scout => sov(congr_cl_ex2_rel_upd_cmp_offset), + din => congr_cl_ex2_rel_upd_cmp_d, + dout => congr_cl_ex2_rel_upd_cmp_q); +congr_cl_rel13_ex3_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_rel13_ex3_cmp_offset), + scout => sov(congr_cl_rel13_ex3_cmp_offset), + din => congr_cl_rel13_ex3_cmp_d, + dout => congr_cl_rel13_ex3_cmp_q); +congr_cl_rel13_ex4_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_rel13_ex4_cmp_offset), + scout => sov(congr_cl_rel13_ex4_cmp_offset), + din => congr_cl_rel13_ex4_cmp_d, + dout => congr_cl_rel13_ex4_cmp_q); +congr_cl_rel13_ex5_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_rel13_ex5_cmp_offset), + scout => sov(congr_cl_rel13_ex5_cmp_offset), + din => congr_cl_rel13_ex5_cmp_d, + dout => congr_cl_rel13_ex5_cmp_q); +congr_cl_rel13_ex6_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_rel13_ex6_cmp_offset), + scout => sov(congr_cl_rel13_ex6_cmp_offset), + din => congr_cl_rel13_ex6_cmp_d, + dout => congr_cl_rel13_ex6_cmp_q); +congr_cl_rel13_relu_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_rel13_relu_cmp_offset), + scout => sov(congr_cl_rel13_relu_cmp_offset), + din => congr_cl_rel13_relu_cmp_d, + dout => congr_cl_rel13_relu_cmp_q); +congr_cl_rel13_relu_s_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_rel13_relu_s_cmp_offset), + scout => sov(congr_cl_rel13_relu_s_cmp_offset), + din => congr_cl_rel13_relu_s_cmp_d, + dout => congr_cl_rel13_relu_s_cmp_q); +congr_cl_rel13_rel_upd_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(congr_cl_rel13_rel_upd_cmp_offset), + scout => sov(congr_cl_rel13_rel_upd_cmp_offset), + din => congr_cl_rel13_rel_upd_cmp_d, + dout => congr_cl_rel13_rel_upd_cmp_q); +rel24_congr_cl_ex4_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel24_congr_cl_ex4_cmp_offset), + scout => sov(rel24_congr_cl_ex4_cmp_offset), + din => rel24_congr_cl_ex4_cmp_d, + dout => rel24_congr_cl_ex4_cmp_q); +rel24_congr_cl_ex5_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel24_congr_cl_ex5_cmp_offset), + scout => sov(rel24_congr_cl_ex5_cmp_offset), + din => rel24_congr_cl_ex5_cmp_d, + dout => rel24_congr_cl_ex5_cmp_q); +rel24_congr_cl_ex6_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel24_congr_cl_ex6_cmp_offset), + scout => sov(rel24_congr_cl_ex6_cmp_offset), + din => rel24_congr_cl_ex6_cmp_d, + dout => rel24_congr_cl_ex6_cmp_q); +relu_congr_cl_ex5_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(relu_congr_cl_ex5_cmp_offset), + scout => sov(relu_congr_cl_ex5_cmp_offset), + din => relu_congr_cl_ex5_cmp_d, + dout => relu_congr_cl_ex5_cmp_q); +relu_congr_cl_ex6_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(relu_congr_cl_ex6_cmp_offset), + scout => sov(relu_congr_cl_ex6_cmp_offset), + din => relu_congr_cl_ex6_cmp_d, + dout => relu_congr_cl_ex6_cmp_q); +relu_congr_cl_ex7_cmp_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(relu_congr_cl_ex7_cmp_offset), + scout => sov(relu_congr_cl_ex7_cmp_offset), + din => relu_congr_cl_ex7_cmp_d, + dout => relu_congr_cl_ex7_cmp_q); +ex4_err_det_way_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_err_det_way_offset to ex4_err_det_way_offset + ex4_err_det_way_d'length-1), + scout => sov(ex4_err_det_way_offset to ex4_err_det_way_offset + ex4_err_det_way_d'length-1), + din => ex4_err_det_way_d, + dout => ex4_err_det_way_q); +ex4_perr_lck_lost_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_perr_lck_lost_offset), + scout => sov(ex4_perr_lck_lost_offset), + din => ex4_perr_lck_lost_d, + dout => ex4_perr_lck_lost_q); +ex4_perr_watch_lost_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_perr_watch_lost_offset to ex4_perr_watch_lost_offset + ex4_perr_watch_lost_d'length-1), + scout => sov(ex4_perr_watch_lost_offset to ex4_perr_watch_lost_offset + ex4_perr_watch_lost_d'length-1), + din => ex4_perr_watch_lost_d, + dout => ex4_perr_watch_lost_q); +dcperr_lock_lost_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dcperr_lock_lost_offset), + scout => sov(dcperr_lock_lost_offset), + din => dcperr_lock_lost_d, + dout => dcperr_lock_lost_q); +binv7_ex7_way_upd_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv7_ex7_way_upd_offset to binv7_ex7_way_upd_offset + binv7_ex7_way_upd_d'length-1), + scout => sov(binv7_ex7_way_upd_offset to binv7_ex7_way_upd_offset + binv7_ex7_way_upd_d'length-1), + din => binv7_ex7_way_upd_d, + dout => binv7_ex7_way_upd_q); +binv5_ex5_dir_data_reg: tri_rlmreg_p +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv4_ex4_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv5_ex5_dir_data_offset to binv5_ex5_dir_data_offset + binv5_ex5_dir_data_d'length-1), + scout => sov(binv5_ex5_dir_data_offset to binv5_ex5_dir_data_offset + binv5_ex5_dir_data_d'length-1), + din => binv5_ex5_dir_data_d, + dout => binv5_ex5_dir_data_q); +binv6_ex6_dir_data_reg: tri_regk +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => binv5_ex5_stg_act, + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din => binv6_ex6_dir_data_d, + dout => binv6_ex6_dir_data_q); +binv7_ex7_dir_data_reg: tri_rlmreg_p +generic map (width => 5, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv7_ex7_dir_data_offset to binv7_ex7_dir_data_offset + binv7_ex7_dir_data_d'length-1), + scout => sov(binv7_ex7_dir_data_offset to binv7_ex7_dir_data_offset + binv7_ex7_dir_data_d'length-1), + din => binv7_ex7_dir_data_d, + dout => binv7_ex7_dir_data_q); +binv5_inval_watch_val_reg: tri_rlmreg_p +generic map (width => 4, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv5_inval_watch_val_offset to binv5_inval_watch_val_offset + binv5_inval_watch_val_d'length-1), + scout => sov(binv5_inval_watch_val_offset to binv5_inval_watch_val_offset + binv5_inval_watch_val_d'length-1), + din => binv5_inval_watch_val_d, + dout => binv5_inval_watch_val_q); +binv5_inval_lock_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(binv5_inval_lock_val_offset), + scout => sov(binv5_inval_lock_val_offset), + din => binv5_inval_lock_val_d, + dout => binv5_inval_lock_val_q); +my_lcb : entity tri.tri_lcbnd(tri_lcbnd) +generic map (expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + d1clk => my_d1clk, + d2clk => my_d2clk, + lclk => my_lclk); +ex4_snd_ld_l2_reg: entity tri.tri_oai22_nlats(tri_oai22_nlats) +generic map (width => 1, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + lclk => my_lclk, + d1clk => my_d1clk, + d2clk => my_d2clk, + scanin(0) => siv(ex4_snd_ld_l2_offset), + scanout(0) => sov(ex4_snd_ld_l2_offset), + a1(0) => ex3_wimge_i_bit, + a2(0) => hit_or_01234567_b, + b1(0) => ex3_load_val, + b2(0) => ex3_load_val, + qb(0) => ex4_snd_ld_l2_q); +ex4_ldq_full_flush_b_reg: entity tri.tri_oai22_nlats(tri_oai22_nlats) +generic map (width => 1, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + lclk => my_lclk, + d1clk => my_d1clk, + d2clk => my_d2clk, + scanin(0) => siv(ex4_ldq_full_flush_b_offset), + scanout(0) => sov(ex4_ldq_full_flush_b_offset), + a1(0) => ex3_l2_request, + a2(0) => hit_or_01234567_b, + b1(0) => ex3_ldq_potential_flush, + b2(0) => ex3_ldq_potential_flush, + qb(0) => ex4_ldq_full_flush_b_q); +ex4_miss_reg: entity tri.tri_inv_nlats(tri_inv_nlats) +generic map (width => 1, init => "1", expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + lclk => my_lclk, + d1clk => my_d1clk, + d2clk => my_d2clk, + scanin(0) => ex4_miss_siv, + scanout(0) => ex4_miss_sov, + d(0) => ex3_l1miss, + qb(0) => ex4_miss_q); +-- Inversion applied to ex4_dir_multihit_val_reg +ex4_miss_siv <= not siv(ex4_miss_offset); +sov(ex4_miss_offset) <= not ex4_miss_sov; +my_spare0_lcb : entity tri.tri_lcbnd(tri_lcbnd) +generic map (expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + d1clk => my_spare0_d1clk, + d2clk => my_spare0_d2clk, + lclk => my_spare0_lclk); +my_spare0_latches_reg: entity tri.tri_inv_nlats(tri_inv_nlats) +generic map (width => 17, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + lclk => my_spare0_lclk, + d1clk => my_spare0_d1clk, + d2clk => my_spare0_d2clk, + scanin => siv(my_spare0_latches_offset to my_spare0_latches_offset + my_spare0_latches_d'length-1), + scanout => sov(my_spare0_latches_offset to my_spare0_latches_offset + my_spare0_latches_d'length-1), + d => my_spare0_latches_d, + qb => my_spare0_latches_q); +my_spare1_lcb : entity tri.tri_lcbnd(tri_lcbnd) +generic map (expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + d1clk => my_spare1_d1clk, + d2clk => my_spare1_d2clk, + lclk => my_spare1_lclk); +my_spare1_latches_reg: entity tri.tri_inv_nlats(tri_inv_nlats) +generic map (width => 16, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + lclk => my_spare1_lclk, + d1clk => my_spare1_d1clk, + d2clk => my_spare1_d2clk, + scanin => siv(my_spare1_latches_offset to my_spare1_latches_offset + my_spare1_latches_d'length-1), + scanout => sov(my_spare1_latches_offset to my_spare1_latches_offset + my_spare1_latches_d'length-1), + d => my_spare1_latches_d, + qb => my_spare1_latches_q); +rel_l1dump_cslc_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_l1dump_cslc_offset), + scout => sov(rel_l1dump_cslc_offset), + din => rel_l1dump_cslc_d, + dout => rel_l1dump_cslc_q); +rel_in_prog_stg1_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_in_prog_stg1_offset), + scout => sov(rel_in_prog_stg1_offset), + din => rel_in_prog_stg1_d, + dout => rel_in_prog_stg1_q); +rel_in_prog_stg2_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_in_prog_stg2_offset), + scout => sov(rel_in_prog_stg2_offset), + din => rel_in_prog_stg2_d, + dout => rel_in_prog_stg2_q); +rel_in_prog_stg3_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_in_prog_stg3_offset), + scout => sov(rel_in_prog_stg3_offset), + din => rel_in_prog_stg3_d, + dout => rel_in_prog_stg3_q); +rel_in_prog_stg4_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_in_prog_stg4_offset), + scout => sov(rel_in_prog_stg4_offset), + din => rel_in_prog_stg4_d, + dout => rel_in_prog_stg4_q); +rel_in_prog_stg5_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_in_prog_stg5_offset), + scout => sov(rel_in_prog_stg5_offset), + din => rel_in_prog_stg5_d, + dout => rel_in_prog_stg5_q); +dcpar_err_stg1_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dcpar_err_stg1_act_offset), + scout => sov(dcpar_err_stg1_act_offset), + din => dcpar_err_stg1_act_d, + dout => dcpar_err_stg1_act_q); +dcpar_err_stg2_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dcpar_err_stg2_act_offset), + scout => sov(dcpar_err_stg2_act_offset), + din => dcpar_err_stg2_act_d, + dout => dcpar_err_stg2_act_q); +rel3_perr_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel3_perr_stg_act_offset), + scout => sov(rel3_perr_stg_act_offset), + din => rel3_perr_stg_act_d, + dout => rel3_perr_stg_act_q); +rel4_perr_stg_act_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel4_perr_stg_act_offset), + scout => sov(rel4_perr_stg_act_offset), + din => rel4_perr_stg_act_d, + dout => rel4_perr_stg_act_q); +siv(0 TO 1247) <= sov(1 to 1247) & scan_in(0); +scan_out(0) <= sov(0); +siv(1248 TO scan_right) <= sov(1249 to scan_right) & scan_in(1); +scan_out(1) <= sov(1248); +scan_out(2) <= scan_in(2); +END XUQ_LSU_DIR_VAL32; diff --git a/rel/src/vhdl/work/xuq_lsu_fgen.vhdl b/rel/src/vhdl/work/xuq_lsu_fgen.vhdl new file mode 100644 index 0000000..3c5ae3d --- /dev/null +++ b/rel/src/vhdl/work/xuq_lsu_fgen.vhdl @@ -0,0 +1,1070 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XU LSU Flush Generation +-- + +library ibm, ieee, work, tri, support; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use tri.tri_latches_pkg.all; +use support.power_logic_pkg.all; + +-- ########################################################################################## +-- VHDL Contents +-- 1) Reload Flush generation +-- 2) Back-Invalidate Flush generation +-- 4) Instruction Flush Handling +-- ########################################################################################## + +entity xuq_lsu_fgen is +generic(expand_type : integer := 2; -- 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) + real_data_add : integer := 42); -- 42 bit real address +port( + + -- Execution Pipe + ex2_cache_acc :in std_ulogic; -- Cache Access is Valid in EX2 + ex2_ldst_fexcpt :in std_ulogic; -- Force Exception on misaligned AXU access + ex2_mv_reg_op :in std_ulogic; + ex2_axu_op :in std_ulogic; -- EX2 AXU operation is valid + rf1_thrd_id :in std_ulogic_vector(0 to 3); -- Thread Id in EX1 + ex1_thrd_id :in std_ulogic_vector(0 to 3); -- Thread Id in EX1 + ex2_thrd_id :in std_ulogic_vector(0 to 3); -- Thread Id in EX2 + ex3_thrd_id :in std_ulogic_vector(0 to 3); -- Thread Id in EX3 + ex4_thrd_id :in std_ulogic_vector(0 to 3); -- Thread Id in EX4 + ex5_thrd_id :in std_ulogic_vector(0 to 3); -- Thread Id in EX5 + ex2_optype32 :in std_ulogic; -- Operation is 32 Byte Access + ex2_optype16 :in std_ulogic; -- Operation is 16 Byte Access + ex2_optype8 :in std_ulogic; -- Operation is 8 Byte Access + ex2_optype4 :in std_ulogic; -- Operation is 4 Byte Access + ex2_optype2 :in std_ulogic; -- Operation is 2 Byte Access + -- Physical Address in EX2 + ex2_p_addr_lwr :in std_ulogic_vector(57 to 63); + ex2_icswx_type :in std_ulogic; + ex2_store_instr :in std_ulogic; -- STORE instruction is valid in EX2 + ex2_load_instr :in std_ulogic; -- LOAD instruction is valid in EX2 + ex2_dcbz_instr :in std_ulogic; -- DCBZ instruction is valid in EX2 + ex2_lock_instr :in std_ulogic; -- lwarx, ldarx, stwcx, and stdcx operations + ex2_ldawx_instr :in std_ulogic; -- ldawx operation + ex2_lm_dep_hit :in std_ulogic; -- Sources for Op match target in loadmiss queue + ex3_lsq_flush :in std_ulogic; -- Store Q full or I=G=1 Flush + derat_xu_ex3_noop_touch :in std_ulogic_vector(0 to 3); + ex3_wimge_w_bit :in std_ulogic; -- WIMG bits in EX3 + ex3_wimge_i_bit :in std_ulogic; -- WIMG bits in EX3 + ex3_targ_match_b1 :in std_ulogic; -- Ex4 Target matched with a load in EX3 + ex2_targ_match_b2 :in std_ulogic; -- Ex5 Target matched with a load in EX3 + + -- D$ Parity Error Detected + ex3_cClass_collision :in std_ulogic; -- Thread Collision with same Congruence Class and Way + ex2_lockwatchSet_rel_coll :in std_ulogic; -- DCBT[ST]LS or WatchSet instruction collided with Reload Clear Stage + ex3_wclr_all_flush :in std_ulogic; -- Watch clear all in pipe flushing other threads in pipe + + xu_lsu_spr_xucr0_aflsta :in std_ulogic; + xu_lsu_spr_xucr0_flsta :in std_ulogic; + xu_lsu_spr_xucr0_l2siw :in std_ulogic; + + -- L2 Operation Flush + ldq_rel_ci :in std_ulogic; -- Cache-Inhibited Reload is Valid + ldq_rel_axu_val :in std_ulogic; -- Reload is for a Vector Register + + -- Instruction Flush + xu_lsu_rf1_flush :in std_ulogic_vector(0 to 3); + xu_lsu_ex1_flush :in std_ulogic_vector(0 to 3); + xu_lsu_ex2_flush :in std_ulogic_vector(0 to 3); + xu_lsu_ex3_flush :in std_ulogic_vector(0 to 3); + xu_lsu_ex4_flush :in std_ulogic_vector(0 to 3); + xu_lsu_ex5_flush :in std_ulogic_vector(0 to 3); + + -- Flush Pipe Outputs + rf1_stg_flush :out std_ulogic; -- Flush Instructions in RF1 + ex1_stg_flush :out std_ulogic; -- Flush Instructions in EX1 + ex2_stg_flush :out std_ulogic; -- Flush Instructions in EX2 + ex3_stg_flush :out std_ulogic; -- Flush Instructions in EX3 + ex4_stg_flush :out std_ulogic; -- Flush Instructions in EX4 + ex5_stg_flush :out std_ulogic; -- Flush Instructions in EX5 + ex3_excp_det :out std_ulogic; -- Any Exception was detected + lsu_xu_ex3_dep_flush :out std_ulogic; -- RAW/WAW Dependency Flush + lsu_xu_ex3_n_flush_req :out std_ulogic; -- Data Cache Instruction Flush in EX3 + + -- Performance Events + lsu_xu_perf_events :out std_ulogic_vector(0 to 3); + + -- Interrupt Generation + lsu_xu_ex3_align :out std_ulogic_vector(0 to 3); + lsu_xu_ex3_dsi :out std_ulogic_vector(0 to 3); + lsu_xu_ex3_inval_align_2ucode :out std_ulogic; + + -- Debug Data + dc_fgen_dbg_data :out std_ulogic_vector(0 to 1); + + --pervasive + vdd :inout power_logic; + gnd :inout power_logic; + nclk :in clk_logic; + sg_0 :in std_ulogic; + func_sl_thold_0_b :in std_ulogic; + func_sl_force :in std_ulogic; + func_nsl_thold_0_b :in std_ulogic; + func_nsl_force :in std_ulogic; + d_mode_dc :in std_ulogic; + delay_lclkr_dc :in std_ulogic; + mpw1_dc_b :in std_ulogic; + mpw2_dc_b :in std_ulogic; + scan_in :in std_ulogic; + scan_out :out std_ulogic +); +-- synopsys translate_off +-- synopsys translate_on +end xuq_lsu_fgen; +---- +architecture xuq_lsu_fgen of xuq_lsu_fgen is + +---------------------------- +-- components +---------------------------- + +---------------------------- +-- constants +---------------------------- + +constant ex3_flush_cond_offset :natural := 0; +constant ex3_valid_lock_offset :natural := ex3_flush_cond_offset + 1; +constant ex3_prealign_int_offset :natural := ex3_valid_lock_offset + 1; +constant ex3_prealign_int_ld_offset :natural := ex3_prealign_int_offset + 1; +constant ex3_preflush_2ucode_offset :natural := ex3_prealign_int_ld_offset + 1; +constant ex3_preflush_2ucode_ld_offset :natural := ex3_preflush_2ucode_offset + 1; +constant rel_is_ci_offset :natural := ex3_preflush_2ucode_ld_offset + 1; +constant rel_is_axu_offset :natural := rel_is_ci_offset + 1; +constant ex3_is_dcbz_offset :natural := rel_is_axu_offset + 1; +constant ex5_misalign_flush_offset :natural := ex3_is_dcbz_offset + 1; +constant spr_xucr0_aflsta_offset :natural := ex5_misalign_flush_offset + 1; +constant spr_xucr0_flsta_offset :natural := spr_xucr0_aflsta_offset + 1; +constant spr_xucr0_l2siw_offset :natural := spr_xucr0_flsta_offset + 1; +constant ex3_dep_flush_offset :natural := spr_xucr0_l2siw_offset + 1; +constant ex5_dep_flush_offset :natural := ex3_dep_flush_offset + 1; +constant ex3_rel_collision_offset :natural := ex5_dep_flush_offset + 1; +constant ex5_rel_collision_offset :natural := ex3_rel_collision_offset + 1; +constant ex5_cClass_collision_offset :natural := ex5_rel_collision_offset + 1; +constant scan_right :natural := ex5_cClass_collision_offset + 1 - 1; + +---------------------------- +-- signals +---------------------------- +signal optype32 :std_ulogic; +signal optype16 :std_ulogic; +signal optype8 :std_ulogic; +signal optype4 :std_ulogic; +signal optype2 :std_ulogic; +signal ex2_32Bop32_unal :std_ulogic; +signal ex2_32Bop16_unal :std_ulogic; +signal ex2_32Bop8_unal :std_ulogic; +signal ex2_32Bop4_unal :std_ulogic; +signal ex2_32Bop2_unal :std_ulogic; +signal ex2_32Bunal_op :std_ulogic; +signal ex2_32Bop16_unal_ld :std_ulogic; +signal ex2_32Bop8_unal_ld :std_ulogic; +signal ex2_32Bop4_unal_ld :std_ulogic; +signal ex2_32Bop2_unal_ld :std_ulogic; +signal ex2_unal_ld_op :std_ulogic; +signal ex2_is_store :std_ulogic; +signal ex2_is_load :std_ulogic; +signal ex2_phy_addr :std_ulogic_vector(57 to 63); +signal rf1_th_id :std_ulogic_vector(0 to 3); +signal ex1_th_id :std_ulogic_vector(0 to 3); +signal ex2_th_id :std_ulogic_vector(0 to 3); +signal ex3_th_id :std_ulogic_vector(0 to 3); +signal ex4_th_id :std_ulogic_vector(0 to 3); +signal ex5_th_id :std_ulogic_vector(0 to 3); +signal ex2_is_lock :std_ulogic; +signal wt_ci_trans :std_ulogic; +signal ex2_valid_lock :std_ulogic; +signal rf1_if_flush_val :std_ulogic; +signal ex1_if_flush_val :std_ulogic; +signal ex2_if_flush_val :std_ulogic; +signal ex3_if_flush_val :std_ulogic; +signal ex4_if_flush_val :std_ulogic; +signal ex5_if_flush_val :std_ulogic; +signal ex3_flush_cond_d :std_ulogic; +signal ex3_flush_cond_q :std_ulogic; +signal ex2_rel_val_flush :std_ulogic; +signal ex2_rel_collision :std_ulogic; +signal ex3_rel_collision_d :std_ulogic; +signal ex3_rel_collision_q :std_ulogic; +signal ex4_rel_collision_d :std_ulogic; +signal ex4_rel_collision_q :std_ulogic; +signal ex5_rel_collision_d :std_ulogic; +signal ex5_rel_collision_q :std_ulogic; +signal ex6_rel_collision_d :std_ulogic; +signal ex6_rel_collision_q :std_ulogic; +signal ex2_is_dcbz :std_ulogic; +signal ex3_valid_lock_d :std_ulogic; +signal ex3_valid_lock_q :std_ulogic; +signal ex3_prealign_int_d :std_ulogic; +signal ex3_prealign_int_q :std_ulogic; +signal ex3_prealign_int_ld_d :std_ulogic; +signal ex3_prealign_int_ld_q :std_ulogic; +signal force_align_int :std_ulogic; +signal ex3_flush_2ucode :std_ulogic; +signal ex3_preflush_2ucode_d :std_ulogic; +signal ex3_preflush_2ucode_q :std_ulogic; +signal ex3_preflush_2ucode_ld_d :std_ulogic; +signal ex3_preflush_2ucode_ld_q :std_ulogic; +signal interface_16B :std_ulogic; +signal ex2_waw_haz :std_ulogic; +signal ex2_raw_haz :std_ulogic; +signal force_align_int_a :std_ulogic; +signal force_align_int_x :std_ulogic; +signal ex2_op32_unal :std_ulogic; +signal ex2_op16_unal :std_ulogic; +signal ex2_op8_unal :std_ulogic; +signal ex2_op4_unal :std_ulogic; +signal ex2_op2_unal :std_ulogic; +signal ex2_unal_op :std_ulogic; +signal ex3_resrc_collision :std_ulogic; +signal ex3_dir_collision :std_ulogic; +signal rel_is_ci_d :std_ulogic; +signal rel_is_ci_q :std_ulogic; +signal rel_is_axu_d :std_ulogic; +signal rel_is_axu_q :std_ulogic; +signal rel_ci_st_collision :std_ulogic; +signal rel_ci_ld_collision :std_ulogic; +signal ex4_misalign_flush_d :std_ulogic; +signal ex4_misalign_flush_q :std_ulogic; +signal ex5_misalign_flush_d :std_ulogic; +signal ex5_misalign_flush_q :std_ulogic; +signal ex6_misalign_flush_d :std_ulogic; +signal ex6_misalign_flush_q :std_ulogic; +signal spr_xucr0_aflsta_d :std_ulogic; +signal spr_xucr0_aflsta_q :std_ulogic; +signal spr_xucr0_flsta_d :std_ulogic; +signal spr_xucr0_flsta_q :std_ulogic; +signal spr_xucr0_l2siw_d :std_ulogic; +signal spr_xucr0_l2siw_q :std_ulogic; +signal ex3_noop_touch :std_ulogic; +signal ex3_dep_flush :std_ulogic; +signal ex3_dep_flush_d :std_ulogic; +signal ex3_dep_flush_q :std_ulogic; +signal ex4_dep_flush_d :std_ulogic; +signal ex4_dep_flush_q :std_ulogic; +signal ex5_dep_flush_d :std_ulogic; +signal ex5_dep_flush_q :std_ulogic; +signal ex6_dep_flush_d :std_ulogic; +signal ex6_dep_flush_q :std_ulogic; +signal ex3_n_flush_rq_b :std_ulogic; +signal ex3_n_flush_rq :std_ulogic; +signal ex4_n_flush_rq_d :std_ulogic; +signal ex4_n_flush_rq_q :std_ulogic; +signal ex2_icswx_unal :std_ulogic; +signal ex3_is_dcbz_d :std_ulogic; +signal ex3_is_dcbz_q :std_ulogic; +signal ex3_dsi_int :std_ulogic; +signal ex3_align_int :std_ulogic; +signal ex3_dcbz_err :std_ulogic; +signal ex2_store_cross :std_ulogic; +signal ex4_cClass_collision_d :std_ulogic; +signal ex4_cClass_collision_q :std_ulogic; +signal ex5_cClass_collision_d :std_ulogic; +signal ex5_cClass_collision_q :std_ulogic; +signal ex6_cClass_collision_d :std_ulogic; +signal ex6_cClass_collision_q :std_ulogic; +signal ex3_n_flush_oth1_b :std_ulogic; +signal ex3_n_flush_oth1 :std_ulogic; + +signal tiup :std_ulogic; +signal siv :std_ulogic_vector(0 to scan_right); +signal sov :std_ulogic_vector(0 to scan_right); + + + +begin + +-- ############################################# +-- Inputs +-- ############################################# +tiup <= '1'; + +ex3_noop_touch <= or_reduce(derat_xu_ex3_noop_touch); +ex2_phy_addr <= ex2_p_addr_lwr; + +optype32 <= ex2_optype32; +optype16 <= ex2_optype16; +optype8 <= ex2_optype8; +optype4 <= ex2_optype4; +optype2 <= ex2_optype2; + +ex2_is_load <= ex2_load_instr; +ex2_is_store <= ex2_store_instr; +ex2_is_dcbz <= ex2_dcbz_instr; +ex2_is_lock <= ex2_lock_instr; +ex3_is_dcbz_d <= ex2_is_dcbz and ex2_cache_acc and not ex2_if_flush_val; + +rf1_th_id <= rf1_thrd_id; +ex1_th_id <= ex1_thrd_id; +ex2_th_id <= ex2_thrd_id; +ex3_th_id <= ex3_thrd_id; +ex4_th_id <= ex4_thrd_id; +ex5_th_id <= ex5_thrd_id; + +ex2_waw_haz <= ex2_targ_match_b2; +ex2_raw_haz <= ex2_lm_dep_hit; + +rel_is_ci_d <= ldq_rel_ci; +rel_is_axu_d <= ldq_rel_axu_val; +rel_ci_st_collision <= rel_is_ci_q and (((ex2_is_store or ex2_icswx_type) and ex2_cache_acc) or ex2_mv_reg_op); +rel_ci_ld_collision <= rel_is_ci_q and rel_is_axu_q and ex2_is_load and ex2_axu_op and ex2_cache_acc; + +spr_xucr0_aflsta_d <= xu_lsu_spr_xucr0_aflsta; +spr_xucr0_flsta_d <= xu_lsu_spr_xucr0_flsta; +spr_xucr0_l2siw_d <= xu_lsu_spr_xucr0_l2siw; + +-- XUCR[FLSTA] = '0' => Flush to ucode +-- XUCR[FLSTA] = '1' => Flush to Alignment Interrupt +-- XUCR[AFLSTA] = '0' => Flush to ucode (AXUop) +-- XUCR[AFLSTA] = '1' => Flush to Alignment Interrupt (AXUop) +force_align_int_a <= ex2_cache_acc and ex2_axu_op and (spr_xucr0_aflsta_q or ex2_ldst_fexcpt); +force_align_int_x <= ex2_cache_acc and not ex2_axu_op and spr_xucr0_flsta_q; +force_align_int <= force_align_int_x or force_align_int_a or ex2_is_lock or ex2_ldawx_instr; + +-- This needs to be tied to XUCR[L2SIW] <<< 16B L2 interface +-- XUCR[L2SIW] = '1' => 32B L2 interface +interface_16B <= not spr_xucr0_l2siw_q; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Exception Calculations +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +-- Operation translated to either Write-Through or Cache-Inhibited +wt_ci_trans <= ex3_wimge_w_bit or ex3_wimge_i_bit; + +-- ################################################################################################################ +-- Alignment Interrupt +-- 1) Operand of a floating-point Load/Store is not word-aligned or crosses a virtual page boundary +-- 2) lq,stq,lmw,stmw,lwarx,ldarx,stwcx,stdcx,eciwx, or ecowx is not aligned +-- 3) load/store is not aligned and in Little-Endian mode +-- 4) lq,stq,lmw,stmw,lswi,lswx,stswi or stswx translates to write through required, cache-inhibited, or in Little Endian +-- 5) load/store crosses a segment boundary or crosses a boundary between virtual pages that have different storage control attributes +-- 6) load/store is not aligned and translates to write through or cache-inhibit +-- 7) dcbz,lwarx,ldarx,stwcx, or stdcx translates to write through required or cache-inhibit +-- ################################################################################################################ + +-- ######################## +-- Unaligned Operation crossing the operand's size +-- ######################## +-- Crossing the Operand Size boundary, only used to determine alignment interrupt if FLSTA = 1 or is_lock_instruction +ex2_op32_unal <= optype32 and (ex2_phy_addr(59) or ex2_phy_addr(60) or ex2_phy_addr(61) or ex2_phy_addr(62) or ex2_phy_addr(63)); +ex2_op16_unal <= optype16 and (ex2_phy_addr(60) or ex2_phy_addr(61) or ex2_phy_addr(62) or ex2_phy_addr(63)); +ex2_op8_unal <= optype8 and (ex2_phy_addr(61) or ex2_phy_addr(62) or ex2_phy_addr(63)); +ex2_op4_unal <= optype4 and (ex2_phy_addr(62) or ex2_phy_addr(63)); +ex2_op2_unal <= optype2 and ex2_phy_addr(63); +ex2_unal_op <= ex2_op32_unal or ex2_op16_unal or ex2_op8_unal or ex2_op4_unal or ex2_op2_unal; +-- ######################## + +-- ######################## +-- Unaligned ICSWX crossing the 64Byte boundary +-- ######################## +-- icswx crossing the 128 byte boundary +ex2_icswx_unal <= ex2_icswx_type and or_reduce(ex2_phy_addr); + +-- ######################## +-- Unaligned Store crossing a 16 Byte boundary in 16B L2 interface mode or cache-inhibited load +-- ######################## +ex2_store_cross <= interface_16B and ex2_is_store; + +-- ######################## +-- Unaligned Operation crossing a 32 Byte boundary +-- ######################## +ex2_32Bop32_unal <= optype32 and (ex2_phy_addr(59) or ex2_phy_addr(60) or ex2_phy_addr(61) or ex2_phy_addr(62) or ex2_phy_addr(63)); +ex2_32Bop16_unal <= optype16 and (ex2_store_cross or ex2_phy_addr(59)) and (ex2_phy_addr(60) or ex2_phy_addr(61) or ex2_phy_addr(62) or ex2_phy_addr(63)); +ex2_32Bop8_unal <= optype8 and (ex2_store_cross or ex2_phy_addr(59)) and ex2_phy_addr(60) and (ex2_phy_addr(61) or ex2_phy_addr(62) or ex2_phy_addr(63)); +ex2_32Bop4_unal <= optype4 and (ex2_store_cross or ex2_phy_addr(59)) and ex2_phy_addr(60) and ex2_phy_addr(61) and (ex2_phy_addr(62) or ex2_phy_addr(63)); +ex2_32Bop2_unal <= optype2 and (ex2_store_cross or ex2_phy_addr(59)) and ex2_phy_addr(60) and ex2_phy_addr(61) and ex2_phy_addr(62) and ex2_phy_addr(63); +ex2_32Bunal_op <= ex2_32Bop32_unal or ex2_32Bop16_unal or ex2_32Bop8_unal or ex2_32Bop4_unal or ex2_32Bop2_unal; + +-- Potential Unaligned Cache-Inhibited Load Crossing the 16Byte boundary +ex2_32Bop16_unal_ld <= optype16 and ex2_is_load and (ex2_phy_addr(60) or ex2_phy_addr(61) or ex2_phy_addr(62) or ex2_phy_addr(63)); +ex2_32Bop8_unal_ld <= optype8 and ex2_is_load and ex2_phy_addr(60) and (ex2_phy_addr(61) or ex2_phy_addr(62) or ex2_phy_addr(63)); +ex2_32Bop4_unal_ld <= optype4 and ex2_is_load and ex2_phy_addr(60) and ex2_phy_addr(61) and (ex2_phy_addr(62) or ex2_phy_addr(63)); +ex2_32Bop2_unal_ld <= optype2 and ex2_is_load and ex2_phy_addr(60) and ex2_phy_addr(61) and ex2_phy_addr(62) and ex2_phy_addr(63); +ex2_unal_ld_op <= ex2_32Bop16_unal_ld or ex2_32Bop8_unal_ld or ex2_32Bop4_unal_ld or ex2_32Bop2_unal_ld; + +-- Flush to uCode if ucode supports unalignment +ex3_preflush_2ucode_d <= (not (ex2_is_lock or ex2_ldawx_instr or ex2_icswx_type)) and ex2_32Bunal_op and ex2_cache_acc and not ex2_if_flush_val; +ex3_preflush_2ucode_ld_d <= (not (ex2_is_lock or ex2_ldawx_instr or ex2_icswx_type)) and ex2_unal_ld_op and ex2_cache_acc and not ex2_if_flush_val; +ex3_flush_2ucode <= ex3_preflush_2ucode_q or (ex3_preflush_2ucode_ld_q and ex3_wimge_i_bit); + +-- Alignment Interrupt Collected +ex3_prealign_int_d <= (ex2_icswx_unal or (force_align_int and (ex2_unal_op or ex2_32Bunal_op))) and ex2_cache_acc and not ex2_if_flush_val; +ex3_prealign_int_ld_d <= force_align_int and ex2_unal_ld_op and ex2_cache_acc and not ex2_if_flush_val; + +-- DCBZ translated to Write-Through or Cache-Inhibited. +ex3_dcbz_err <= ex3_is_dcbz_q and wt_ci_trans; +ex3_align_int <= ex3_prealign_int_q or (ex3_prealign_int_ld_q and ex3_wimge_i_bit) or ex3_dcbz_err; +-- ######################## + +ex4_misalign_flush_d <= ex3_flush_2ucode or ex3_prealign_int_q or (ex3_prealign_int_ld_q and ex3_wimge_i_bit); +ex5_misalign_flush_d <= ex4_misalign_flush_q; +ex6_misalign_flush_d <= ex5_misalign_flush_q; +-- ################################################################################################################ + +-- ################################################################################################################ +-- Data Storage Interrupt +-- 2) lq,stq,lwarx,ldarx,stwcx, or stdcx translate to write through required or cache-inhibit +-- 3) the access violates the storage protection +-- 4) Data Address Compare matches address or Data Address Breakpoint match occurs +-- 5) eciwx or ecowx is not allowed by EAR[E]=0 +-- ################################################################################################################ + +-- ######################## +-- Invalid Write-Through or Cache Inhibit Translation +-- ######################## + +-- lwarx,ldarx,stwcx,stdcx translate to write-through or cache-inhibit +ex2_valid_lock <= ex2_is_lock and ex2_cache_acc and not ex2_if_flush_val; + +ex3_valid_lock_d <= ex2_valid_lock; +ex3_dsi_int <= ex3_valid_lock_q and wt_ci_trans; +-- ################################################################################################################ + +ex3_dep_flush_d <= (ex2_raw_haz or ex2_waw_haz) and not ex2_if_flush_val; +ex3_dep_flush <= ex3_dep_flush_q or ex3_targ_match_b1; +ex4_dep_flush_d <= ex3_dep_flush; +ex5_dep_flush_d <= ex4_dep_flush_q; +ex6_dep_flush_d <= ex5_dep_flush_q; + +-- Any Exception detected, Need to block Touch Op if an exception was detected +ex3_excp_det <= ex3_noop_touch; + +-- ############################################# +-- FLUSH CONDITIONS +-- ############################################# + +-- RF1 Instruction Flush +rf1_if_flush_val <= (xu_lsu_rf1_flush(0) and rf1_th_id(0)) or + (xu_lsu_rf1_flush(1) and rf1_th_id(1)) or + (xu_lsu_rf1_flush(2) and rf1_th_id(2)) or + (xu_lsu_rf1_flush(3) and rf1_th_id(3)); + +-- EX1 Instruction Flush +ex1_if_flush_val <= (xu_lsu_ex1_flush(0) and ex1_th_id(0)) or + (xu_lsu_ex1_flush(1) and ex1_th_id(1)) or + (xu_lsu_ex1_flush(2) and ex1_th_id(2)) or + (xu_lsu_ex1_flush(3) and ex1_th_id(3)); + +-- EX2 Instruction Flush +ex2_if_flush_val <= (xu_lsu_ex2_flush(0) and ex2_th_id(0)) or + (xu_lsu_ex2_flush(1) and ex2_th_id(1)) or + (xu_lsu_ex2_flush(2) and ex2_th_id(2)) or + (xu_lsu_ex2_flush(3) and ex2_th_id(3)); + +-- EX3 Instruction Flush +ex3_if_flush_val <= (xu_lsu_ex3_flush(0) and ex3_th_id(0)) or + (xu_lsu_ex3_flush(1) and ex3_th_id(1)) or + (xu_lsu_ex3_flush(2) and ex3_th_id(2)) or + (xu_lsu_ex3_flush(3) and ex3_th_id(3)); + +-- EX4 Instruction Flush +ex4_if_flush_val <= (xu_lsu_ex4_flush(0) and ex4_th_id(0)) or + (xu_lsu_ex4_flush(1) and ex4_th_id(1)) or + (xu_lsu_ex4_flush(2) and ex4_th_id(2)) or + (xu_lsu_ex4_flush(3) and ex4_th_id(3)); + +-- EX5 Instruction Flush +ex5_if_flush_val <= (xu_lsu_ex5_flush(0) and ex5_th_id(0)) or + (xu_lsu_ex5_flush(1) and ex5_th_id(1)) or + (xu_lsu_ex5_flush(2) and ex5_th_id(2)) or + (xu_lsu_ex5_flush(3) and ex5_th_id(3)); + +--xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +-- Reload Flush Conditions +--xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +ex2_rel_val_flush <= rel_ci_st_collision or rel_ci_ld_collision or ex2_lockwatchSet_rel_coll; +ex2_rel_collision <= ex2_rel_val_flush and not ex2_if_flush_val; +ex3_rel_collision_d <= ex2_rel_collision; +ex4_rel_collision_d <= ex3_rel_collision_q; +ex5_rel_collision_d <= ex4_rel_collision_q; +ex6_rel_collision_d <= ex5_rel_collision_q; + +--xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +-- Force L1 Load Hits to L2 Flush Conditions +--xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +--ex2_flh2l2_flush <= (ex3_0stores_left or (ex3_1store_left and ex3_ldstq_instr)) and ex2_is_load and ex2_cache_acc and spr_xucr0_flh2l2; +--ex3_flh2l2_flush_d <= ex2_flh2l2_flush; +--ex4_flh2l2_flush_d <= ex3_flh2l2_flush_q; +--ex5_flh2l2_flush_d <= ex4_flh2l2_flush_q; +--ex6_flh2l2_flush_d <= ex5_flh2l2_flush_q; + +--xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +-- RF1 Flush Stage +-- 1) Instruction Flush from FXU +--xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +rf1_stg_flush <= rf1_if_flush_val; + +--xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +-- EX1 Flush Stage +-- 1) Instruction Flush from FXU +--xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +ex1_stg_flush <= ex1_if_flush_val; + +--xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +-- EX2 Flush Stage +-- 1) Back-Invalidate from L2 +-- 2) Reload from L2 +-- 3) L1 load hit with FLH2L2 and no credits +-- 4) Instruction Flush from FXU +--xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +ex2_stg_flush <= ex2_if_flush_val; + +--xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +-- EX3 Flush Stage takes into account the following +-- L1 D$ -> reload valid and D$ op comes down the pipe +-- L1 D$ -> invalidate valid and D$ op comes down the pipe +-- L1 D$ -> loadmiss queue is full and D$ op comes down the pipe +-- L1 D$ -> store queue is full and D$ op comes down the pipe +-- L1 D$ -> D$ op maps to and entry in the loadmiss queue +-- L1 D$ -> D$ op maps to and entry that will be put into the loadmiss queue +-- FXU -> BTA miscompare flush needs to flush D$ op in EX3, this is an FXU internal flush +-- IF -> Instruction Flush +-- WAW -> loadmiss in EX3 with a target that matches the target of the op in EX2 +-- RAW -> Outstandin loadmiss with a target that matches the sources of the op in EX2 +--xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +ex3_flush_cond_d <= ex2_rel_collision; +ex3_resrc_collision <= ex3_flush_cond_q; +ex3_dir_collision <= ex3_cClass_collision or ex3_wclr_all_flush; +ex4_cClass_collision_d <= ex3_dir_collision; +ex5_cClass_collision_d <= ex4_cClass_collision_q; +ex6_cClass_collision_d <= ex5_cClass_collision_q; + +ex3NFlushoth1B: ex3_n_flush_oth1_b <= not (ex3_resrc_collision or ex3_lsq_flush); +ex3NFlushoth1: ex3_n_flush_oth1 <= not ex3_n_flush_oth1_b; +ex3NFlushRqB: ex3_n_flush_rq_b <= not (ex3_n_flush_oth1 or ex3_dir_collision); +ex3NFlushRq: ex3_n_flush_rq <= not ex3_n_flush_rq_b; + +ex4_n_flush_rq_d <= ex3_n_flush_rq; + +-- Shouldnt need my own flush generation in the equation +-- Completions ex5 flush should cover everything +ex3_stg_flush <= ex3_if_flush_val; + +lsu_xu_ex3_n_flush_req <= ex3_n_flush_rq; +lsu_xu_ex3_inval_align_2ucode <= ex3_flush_2ucode and not ex3_flush_cond_q; +lsu_xu_ex3_dep_flush <= ex3_dep_flush; +lsu_xu_ex3_dsi <= gate(ex3_th_id, ex3_dsi_int); +lsu_xu_ex3_align <= gate(ex3_th_id, ex3_align_int); + +-- Debug Data +dc_fgen_dbg_data <= rel_is_ci_q & ex4_n_flush_rq_q; + +-- xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +-- Performance Events +-- xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +lsu_xu_perf_events <= ex6_misalign_flush_q & ex6_rel_collision_q & + ex6_cClass_collision_q & ex6_dep_flush_q; + +--xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +-- EX4 Flush Stage takes into account the following +-- IF -> Instruction Flush +--xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +ex4_stg_flush <= ex4_if_flush_val; + +--xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +-- EX5 Flush Stage takes into account the following +-- IF -> Instruction Flush +--xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +ex5_stg_flush <= ex5_if_flush_val; + +--xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +-- Registers +--xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + +ex3_flush_cond_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_flush_cond_offset), + scout => sov(ex3_flush_cond_offset), + din => ex3_flush_cond_d, + dout => ex3_flush_cond_q); + +ex4_n_flush_rq_reg: tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex4_n_flush_rq_d, + dout(0) => ex4_n_flush_rq_q); + +ex3_valid_lock_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_valid_lock_offset), + scout => sov(ex3_valid_lock_offset), + din => ex3_valid_lock_d, + dout => ex3_valid_lock_q); + +ex3_prealign_int_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_prealign_int_offset), + scout => sov(ex3_prealign_int_offset), + din => ex3_prealign_int_d, + dout => ex3_prealign_int_q); + +ex3_prealign_int_ld_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_prealign_int_ld_offset), + scout => sov(ex3_prealign_int_ld_offset), + din => ex3_prealign_int_ld_d, + dout => ex3_prealign_int_ld_q); + +ex3_preflush_2ucode_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_preflush_2ucode_offset), + scout => sov(ex3_preflush_2ucode_offset), + din => ex3_preflush_2ucode_d, + dout => ex3_preflush_2ucode_q); + +ex3_preflush_2ucode_ld_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_preflush_2ucode_ld_offset), + scout => sov(ex3_preflush_2ucode_ld_offset), + din => ex3_preflush_2ucode_ld_d, + dout => ex3_preflush_2ucode_ld_q); + +rel_is_ci_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_is_ci_offset), + scout => sov(rel_is_ci_offset), + din => rel_is_ci_d, + dout => rel_is_ci_q); + +rel_is_axu_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_is_axu_offset), + scout => sov(rel_is_axu_offset), + din => rel_is_axu_d, + dout => rel_is_axu_q); + +ex3_is_dcbz_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_dcbz_offset), + scout => sov(ex3_is_dcbz_offset), + din => ex3_is_dcbz_d, + dout => ex3_is_dcbz_q); + +ex4_misalign_flush_reg: tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex4_misalign_flush_d, + dout(0) => ex4_misalign_flush_q); + +ex5_misalign_flush_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_misalign_flush_offset), + scout => sov(ex5_misalign_flush_offset), + din => ex5_misalign_flush_d, + dout => ex5_misalign_flush_q); + +ex6_misalign_flush_reg: tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex6_misalign_flush_d, + dout(0) => ex6_misalign_flush_q); + +spr_xucr0_aflsta_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(spr_xucr0_aflsta_offset), + scout => sov(spr_xucr0_aflsta_offset), + din => spr_xucr0_aflsta_d, + dout => spr_xucr0_aflsta_q); + +spr_xucr0_flsta_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(spr_xucr0_flsta_offset), + scout => sov(spr_xucr0_flsta_offset), + din => spr_xucr0_flsta_d, + dout => spr_xucr0_flsta_q); + +spr_xucr0_l2siw_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(spr_xucr0_l2siw_offset), + scout => sov(spr_xucr0_l2siw_offset), + din => spr_xucr0_l2siw_d, + dout => spr_xucr0_l2siw_q); + +ex3_dep_flush_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_dep_flush_offset), + scout => sov(ex3_dep_flush_offset), + din => ex3_dep_flush_d, + dout => ex3_dep_flush_q); + +ex4_dep_flush_reg: tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex4_dep_flush_d, + dout(0) => ex4_dep_flush_q); + +ex5_dep_flush_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_dep_flush_offset), + scout => sov(ex5_dep_flush_offset), + din => ex5_dep_flush_d, + dout => ex5_dep_flush_q); + +ex6_dep_flush_reg: tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex6_dep_flush_d, + dout(0) => ex6_dep_flush_q); + +ex3_rel_collision_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_rel_collision_offset), + scout => sov(ex3_rel_collision_offset), + din => ex3_rel_collision_d, + dout => ex3_rel_collision_q); + +ex4_rel_collision_reg: tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex4_rel_collision_d, + dout(0) => ex4_rel_collision_q); + +ex5_rel_collision_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_rel_collision_offset), + scout => sov(ex5_rel_collision_offset), + din => ex5_rel_collision_d, + dout => ex5_rel_collision_q); + +ex6_rel_collision_reg: tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex6_rel_collision_d, + dout(0) => ex6_rel_collision_q); + +ex4_cClass_collision_reg: tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex4_cClass_collision_d, + dout(0) => ex4_cClass_collision_q); + +ex5_cClass_collision_reg: tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_cClass_collision_offset), + scout => sov(ex5_cClass_collision_offset), + din => ex5_cClass_collision_d, + dout => ex5_cClass_collision_q); + +ex6_cClass_collision_reg: tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex6_cClass_collision_d, + dout(0) => ex6_cClass_collision_q); + +siv(0 to scan_right) <= sov(1 to scan_right) & scan_in; +scan_out <= sov(0); + +end xuq_lsu_fgen; diff --git a/rel/src/vhdl/work/xuq_lsu_l2cmdq.vhdl b/rel/src/vhdl/work/xuq_lsu_l2cmdq.vhdl new file mode 100644 index 0000000..a99fffb --- /dev/null +++ b/rel/src/vhdl/work/xuq_lsu_l2cmdq.vhdl @@ -0,0 +1,9244 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XU LSU L2 Command Queue +-- + +LIBRARY ieee; +LIBRARY ibm; +USE ieee.std_logic_1164.all ; +use ieee.numeric_std.all; +USE ibm.std_ulogic_support.all ; +USE ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; + +library support; +use support.power_logic_pkg.all; + +library tri; +use tri.tri_latches_pkg.all; + + +ENTITY xuq_lsu_l2cmdq IS + generic(expand_type : integer := 2; -- 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) + lmq_entries : integer := 8; -- 8 Loadmiss Queue Entries. + dc_size : natural := 14; -- 2^14 = 16384 Bytes L1 D$ + cl_size : natural := 6; -- 2^6 = 64 Bytes CacheLines + real_data_add : integer := 42; -- 42 bit real address + a2mode : integer := 1; + load_credits : integer := 4; + store_credits : integer := 20; + st_data_32B_mode : integer := 1 ); -- 0 = 16B store data to L2, 1 = 32B data + PORT ( + -- Load Miss/Store Operation Signals + ex3_thrd_id :in std_ulogic_vector(0 to 3); -- Thread ID + ex3_l_s_q_val :in std_ulogic; -- load/store miss valid or store valid + ex3_drop_ld_req :in std_ulogic; -- load miss + ex3_drop_touch :in std_ulogic; -- drop blockable touch + ex3_cache_inh :in std_ulogic; -- Cache Inhibit Mode is on + ex3_load_instr :in std_ulogic; -- load operation + ex3_store_instr :in std_ulogic; -- store operation + ex3_cache_acc :in std_ulogic; -- op in ex2 is a cache access + ex3_p_addr_lwr :in std_ulogic_vector(58 to 63); -- physical address of load/store miss + ex3_opsize :in std_ulogic_vector(0 to 5); -- Load/Store Size + -- 100000 = 32 bytes + -- 010000 = 16 bytes + -- 001000 = 8 bytes + -- 000100 = 4 bytes + -- 000010 = 2 bytes + -- 000001 = 1 byte + ex3_rot_sel :in std_ulogic_vector(0 to 4); -- rotator select bits for data cache + ex3_byte_en :in std_ulogic_vector(0 to 31); -- Store Data Byte Enables + ex4_256st_data :in std_ulogic_vector(0 to 255); -- Store Data + ex3_target_gpr :in std_ulogic_vector(0 to 8); -- Target GPR, needed for reloads + ex3_axu_op_val :in std_ulogic; -- Operation was to an AXU register or from a AXU operation + ex3_le_mode :in std_ulogic; -- little endian mode + ex3_larx_instr :in std_ulogic; -- Load is a lwarx + ex3_stx_instr :in std_ulogic; -- Store is a stwcx + ex3_dcbt_instr :in std_ulogic; -- DCBT instruction is valid + ex3_dcbf_instr :in std_ulogic; -- DCBF instruction is valid + ex3_dcbtst_instr :in std_ulogic; -- DCBTST instruction is valid + ex3_dcbst_instr :in std_ulogic; -- DCBST instruction is valid + ex3_dcbz_instr :in std_ulogic; -- DCBZ instruction is valid + ex3_dcbi_instr :in std_ulogic; -- DCBI instruction is valid + ex3_icbi_instr :in std_ulogic; -- ICBI instruction is valid + ex3_sync_instr :in std_ulogic; -- SYNC instruction is valid + ex3_l_fld :in std_ulogic_vector(0 to 1); -- L field of sync: 00=hwsync, 01=lwsync, 10=ptesync + ex3_mbar_instr :in std_ulogic; -- mbar instruction is valid + ex3_wimge_bits :in std_ulogic_vector(0 to 4); -- WIMG bits + ex3_usr_bits :in std_ulogic_vector(0 to 3); -- WIMG bits + ex3_stg_flush :in std_ulogic; -- EX3 Flush instruction + ex4_stg_flush :in std_ulogic; -- EX4 Flush instruction + xu_lsu_ex5_flush :in std_ulogic_vector(0 to 3); + ex3_byp_l1 :in std_ulogic; -- Bypass L1 D$ indication if a loadmiss + ex3_algebraic :in std_ulogic; -- command is algebraic type + xu_lsu_ex4_dvc1_en :in std_ulogic; + xu_lsu_ex4_dvc2_en :in std_ulogic; + + ex3_dcbtls_instr :in std_ulogic; + ex3_dcbtstls_instr :in std_ulogic; + ex3_dcblc_instr :in std_ulogic; + ex3_dci_instr :in std_ulogic; + ex3_ici_instr :in std_ulogic; + ex3_icblc_instr :in std_ulogic; + ex3_icbt_instr :in std_ulogic; + ex3_icbtls_instr :in std_ulogic; + ex3_tlbsync_instr :in std_ulogic; + ex3_local_dcbf :in std_ulogic; + ex3_icswx_instr :in std_ulogic; + ex3_icswx_dot :in std_ulogic; + ex3_icswx_epid :in std_ulogic; + ex3_classid :in std_ulogic_vector(0 to 1); + ex3_lock_en :in std_ulogic; + ex3_th_fld_l2 :in std_ulogic; + ex4_drop_rel :in std_ulogic; -- active for dcbtls and dcbtstls when L1 hit (treat as L2 only) + ex3_load_l1hit :in std_ulogic; -- used for debug to see L1 hits on bus + ex3_mutex_hint :in std_ulogic; + ex3_msgsnd_instr :in std_ulogic; + ex3_watch_en :in std_ulogic; + ex3_mtspr_trace :in std_ulogic; + ex3_stg_act :in std_ulogic; + ex4_stg_act :in std_ulogic; + + ex4_ld_entry :in std_ulogic_vector(0 to (26+(real_data_add-1))); + + -- Dependency Checking on loadmisses + ex1_src0_vld :in std_ulogic; -- Source0 is Valid + ex1_src0_reg :in std_ulogic_vector(0 to 7); -- Source0 Register + ex1_src1_vld :in std_ulogic; -- Source1 is Valid + ex1_src1_reg :in std_ulogic_vector(0 to 7); -- Source1 Register + ex1_targ_vld :in std_ulogic; -- Target is Valid + ex1_targ_reg :in std_ulogic_vector(0 to 7); -- Target Register + ex1_check_watch :in std_ulogic_vector(0 to 3); + ex2_lm_dep_hit :out std_ulogic; -- dependency hit in lm q + + ex6_ld_par_err :in std_ulogic; + pe_recov_begin :in std_ulogic; + ex7_targ_match :in std_ulogic; + ex8_targ_match :in std_ulogic; + + + -- inputs from L2 + an_ac_req_ld_pop :in std_ulogic; -- credit for a load (L2 can take a load command) + an_ac_req_st_pop :in std_ulogic; -- credit for a store (L2 can take a store command) + an_ac_req_st_pop_thrd :in std_ulogic_vector(0 to 2); -- decrement outbox credit count + an_ac_req_st_gather :in std_ulogic; -- credit for a store due to L2 gathering of store commands + + an_ac_reld_data_coming :in std_ulogic; -- reload data is coming in 3 cycles + an_ac_reld_data_val :in std_ulogic; -- reload data is coming in 2 cycles + an_ac_reld_core_tag :in std_ulogic_vector(0 to 4); -- reload data destinatoin tag (which load queue) + an_ac_reld_qw :in std_ulogic_vector(57 to 59); -- quadword address of reload data beat + an_ac_reld_data :in std_ulogic_vector(0 to 127); -- reload data + an_ac_reld_ditc :in std_ulogic; -- reload data is for ditc (inbox) + an_ac_reld_crit_qw :in std_ulogic; -- the transfer assoicated with data_val is the critical QW + an_ac_reld_l1_dump :in std_ulogic; -- the transfer assoicated with data_val is the critical QW + + an_ac_reld_ecc_err :in std_ulogic; -- correctable ecc error on the data transfer + an_ac_reld_ecc_err_ue :in std_ulogic; -- un-correctable ecc error on the data transfer + + an_ac_back_inv :in std_ulogic; -- back invalidate (cycle before inv_addr) + an_ac_back_inv_addr :in std_ulogic_vector(64-real_data_add to 63); -- address for back invalidate + an_ac_back_inv_target_bit1 :in std_ulogic; -- target of back invalidate (cycle before inv_addr) + an_ac_back_inv_target_bit4 :in std_ulogic; -- XU just gets bits 1 (D side) and 4 (IPI) + + an_ac_req_spare_ctrl_a1 :in std_ulogic_vector(0 to 3); -- spare control bits from L2 + an_ac_stcx_complete :in std_ulogic_vector(0 to 3); + xu_iu_stcx_complete :out std_ulogic_vector(0 to 3); + xu_iu_reld_core_tag_clone :out std_ulogic_vector(1 to 4); + xu_iu_reld_data_coming_clone :out std_ulogic; + xu_iu_reld_data_vld_clone :out std_ulogic; + xu_iu_reld_ditc_clone :out std_ulogic; + +-- redrive to boxes logic + lsu_reld_data_vld :out std_ulogic; -- reload data is coming in 2 cycles + lsu_reld_core_tag :out std_ulogic_vector(3 to 4); -- reload data destinatoin tag (thread) + lsu_reld_qw :out std_ulogic_vector(58 to 59); -- reload data quadword pointer + lsu_reld_ditc :out std_ulogic; -- reload data is for ditc (inbox) + lsu_reld_ecc_err :out std_ulogic; -- reload data has ecc error + lsu_reld_data :out std_ulogic_vector(0 to 127); -- reload data + + lsu_req_st_pop :out std_ulogic; -- decrement outbox credit count + lsu_req_st_pop_thrd :out std_ulogic_vector(0 to 2); -- decrement outbox credit count + + -- Instruction Fetches + -- Instruction Fetch real address + i_x_ra :in std_ulogic_vector(64-real_data_add to 59); + i_x_request :in std_ulogic; -- Instruction Fetch is Valid + i_x_wimge :in std_ulogic_vector(0 to 4); -- Instruction Fetch WIMG bits + i_x_thread :in std_ulogic_vector(0 to 3); -- Instruction Fetch Thread ID + i_x_userdef :in std_ulogic_vector(0 to 3); -- + + -- MMU instruction interface + mm_xu_lsu_req :in std_ulogic_vector(0 to 3); -- will only pulse when mm has at least 1 token (1 bit per thread) + mm_xu_lsu_ttype :in std_ulogic_vector(0 to 1); -- 0=TLBIVAX, 1=TLBI_COMPLETE, 2=LOAD (tag=01100), 3=LOAD (tag=01101) + mm_xu_lsu_wimge :in std_ulogic_vector(0 to 4); + mm_xu_lsu_u :in std_ulogic_vector(0 to 3); -- user defined bits + mm_xu_lsu_addr :in std_ulogic_vector(64-real_data_add to 63); -- address for TLBI (or loads, maybe), + -- TLBI_COMPLETE is address-less + mm_xu_lsu_lpid :in std_ulogic_vector(0 to 7); -- muxed LPID for the thread of the mmu command + mm_xu_lsu_gs :in std_ulogic; + mm_xu_lsu_ind :in std_ulogic; + mm_xu_lsu_lbit :in std_ulogic; -- "L" bit, for large vs. small + + mm_xu_lsu_lpidr :in std_ulogic_vector(0 to 7); -- the LPIDR register + xu_lsu_msr_gs :in std_ulogic_vector(0 to 3); -- (MSR.HV) + xu_lsu_msr_pr :in std_ulogic_vector(0 to 3); -- Problem State (MSR.PR) + xu_lsu_msr_ds :in std_ulogic_vector(0 to 3); -- Addr Space (MSR.DS) + mm_xu_derat_pid0 :in std_ulogic_vector(0 to 13); -- Thread0 PID Number + mm_xu_derat_pid1 :in std_ulogic_vector(0 to 13); -- Thread1 PID Number + mm_xu_derat_pid2 :in std_ulogic_vector(0 to 13); -- Thread2 PID Number + mm_xu_derat_pid3 :in std_ulogic_vector(0 to 13); -- Thread3 PID Number + xu_derat_epsc0_epr :in std_ulogic; + xu_derat_epsc0_eas :in std_ulogic; + xu_derat_epsc0_egs :in std_ulogic; + xu_derat_epsc0_elpid :in std_ulogic_vector(40 to 47); + xu_derat_epsc0_epid :in std_ulogic_vector(50 to 63); + xu_derat_epsc1_epr :in std_ulogic; + xu_derat_epsc1_eas :in std_ulogic; + xu_derat_epsc1_egs :in std_ulogic; + xu_derat_epsc1_elpid :in std_ulogic_vector(40 to 47); + xu_derat_epsc1_epid :in std_ulogic_vector(50 to 63); + xu_derat_epsc2_epr :in std_ulogic; + xu_derat_epsc2_eas :in std_ulogic; + xu_derat_epsc2_egs :in std_ulogic; + xu_derat_epsc2_elpid :in std_ulogic_vector(40 to 47); + xu_derat_epsc2_epid :in std_ulogic_vector(50 to 63); + xu_derat_epsc3_epr :in std_ulogic; + xu_derat_epsc3_eas :in std_ulogic; + xu_derat_epsc3_egs :in std_ulogic; + xu_derat_epsc3_elpid :in std_ulogic_vector(40 to 47); + xu_derat_epsc3_epid :in std_ulogic_vector(50 to 63); + + + -- Boxes interface + bx_lsu_ob_pwr_tok :in std_ulogic; -- message buffer data is ready to send + bx_lsu_ob_req_val :in std_ulogic; -- message buffer data is ready to send + bx_lsu_ob_ditc_val :in std_ulogic; -- send dtic command + bx_lsu_ob_thrd :in std_ulogic_vector(0 to 1); -- source thread + bx_lsu_ob_qw :in std_ulogic_vector(58 to 59); -- QW address + bx_lsu_ob_dest :in std_ulogic_vector(0 to 14); -- destination node/core/thread for the packet + bx_lsu_ob_data :in std_ulogic_vector(0 to 127); -- 16B of data from the outbox + bx_lsu_ob_addr :in std_ulogic_vector(64-real_data_add to 57); -- address for boxes message + lsu_bx_cmd_avail :out std_ulogic; + lsu_bx_cmd_sent :out std_ulogic; + lsu_bx_cmd_stall :out std_ulogic; + + spr_xucr0_clkg_ctl_b3 :in std_ulogic; -- Clock Gating Override + xu_lsu_spr_xucr0_rel :in std_ulogic; -- L2 Reload Mode Control (0=gaps, 1=back to back) + xu_lsu_spr_xucr0_l2siw :in std_ulogic; -- L2 Store Interface Width (0=16B, 1=32B) + xu_lsu_spr_xucr0_cred :in std_ulogic; -- L2 credit debug mode (0=normal, 1=need both load and store credit to send anything) + xu_lsu_spr_xucr0_mbar_ack :in std_ulogic; -- use sync_ack from L2 for lwsync and mbar when 1 + xu_lsu_spr_xucr0_tlbsync :in std_ulogic; -- use sync_ack from L2 for tlbsync when 1 + xu_lsu_spr_xucr0_cls :in std_ulogic; -- cache line size (1=128 byte, 0=64 byte) + + xu_mm_lsu_token :out std_ulogic; -- pulse for 1 clk when mm queue entry has been sent (i.e. mmu can request again) + + + -- Memory Barrier Complete for lwsync/mbar signals going to IU + lsu_xu_ldq_barr_done :out std_ulogic_vector(0 to 3); -- Memory Barrier for ldq hit complete thread id, should be on when true + lsu_xu_sync_barr_done :out std_ulogic_vector(0 to 3); -- Memory Barrier (lwsync/mbar) complete thread id, should be on when true + + -- *** Reload operation Outputs *** + -- Reload Address + ldq_rel_op_size :out std_ulogic_vector(0 to 5); -- Reload Size, used to determine the data write in gpr reg file + ldq_rel_thrd_id :out std_ulogic_vector(0 to 3); -- Thread ID of the reload + -- goes with ldq_rel_val + ldq_rel_addr_early :out std_ulogic_vector(64-real_data_add to 57); -- 1 cycle before ldq_rel_addr + ldq_rel_addr :out std_ulogic_vector(64-real_data_add to 58); -- d-cache reload physical address in cycle before data + ldq_rel_data_val_early :out std_ulogic; -- 1 cycle before reload data - use for act + ldq_rel_data_val :out std_ulogic; -- Reload data is valid, active for 2 32B beats of data + ldq_rel_tag_early :out std_ulogic_vector(2 to 4); -- tag of the reload, 1 cycle early + ldq_rel_tag :out std_ulogic_vector(2 to 4); -- tag of the reload + ldq_rel1_val :out std_ulogic; -- Reload data is valid for 1st 32B beat + ldq_rel1_early_v :out std_ulogic; + ldq_rel_mid_val :out std_ulogic; -- Reload data is valid for middle 32B beat + ldq_rel_retry_val :out std_ulogic; -- Reload is recirculated, dont update D$ array + ldq_rel3_val :out std_ulogic; -- Reload data is valid for last 32B beat + ldq_rel3_early_v :out std_ulogic; + ldq_rel_ta_gpr :out std_ulogic_vector(0 to 8); -- Reload Target Register + ldq_rel_rot_sel :out std_ulogic_vector(0 to 4); -- Reload rotator select + ldq_rel_axu_val :out std_ulogic; -- Reload is for a Vector Register + ldq_rel_upd_gpr :out std_ulogic; -- Reload data should be written to GPR (DCB ops don't write to GPRs) + ldq_rel_le_mode :out std_ulogic; -- Reload data is in little endian mode + ldq_rel_algebraic :out std_ulogic; + ldq_rel_set_val :out std_ulogic; -- all 4 data beats have transferred without error, set valid in dir + ldq_rel_256_data :out std_ulogic_vector(0 to 255); -- 32 bytes of reload data + ldq_rel_ecc_err :out std_ulogic; -- all 4 data beats have transferred without error, set valid in dir + + + ldq_rel_classid :out std_ulogic_vector(0 to 1); + ldq_rel_lock_en :out std_ulogic; + ldq_rel_ci :out std_ulogic; + ldq_rel_dvc1_en :out std_ulogic; + ldq_rel_dvc2_en :out std_ulogic; + ldq_rel_watch_en :out std_ulogic; + ldq_rel_back_invalidated :out std_ulogic; + + ldq_recirc_rel_val :in std_ulogic; + + ldq_rel_beat_crit_qw :out std_ulogic; -- critical QW being sent on the reload data + ldq_rel_beat_crit_qw_block :out std_ulogic; -- critical QW blocked due to ecc error + + l1dump_cslc :out std_ulogic; + ldq_rel3_l1dump_val :out std_ulogic; -- reload had l1dump set + + -- Back invalidate signals going to D-Cache + is2_l2_inv_val :out std_ulogic; + is2_l2_inv_p_addr :out std_ulogic_vector(64-real_data_add to 63-cl_size); + + + -- Flush Signals and signals going to dependency + ex3_stq_flush :out std_ulogic; -- Store Queue Full flush + ex3_ig_flush :out std_ulogic; -- 2nd load to I=1, G=1 flush + ex3_ld_queue_full :out std_ulogic; + + gpr_ecc_err_flush_tid :out std_ulogic_vector(0 to 3); -- all cmds to this thread need to be flushed + -- because GPR got bad ecc on a reload + xu_iu_ex4_loadmiss_qentry :out std_ulogic_vector(0 to lmq_entries-1); -- Load Miss Queue entry + xu_iu_ex4_loadmiss_target :out std_ulogic_vector(0 to 8); -- target gpr + xu_iu_ex4_loadmiss_target_type :out std_ulogic_vector(0 to 1); + xu_iu_ex4_loadmiss_tid :out std_ulogic_vector(0 to 3); + xu_iu_ex5_loadmiss_qentry :out std_ulogic_vector(0 to lmq_entries-1); -- Load Miss Queue entry + xu_iu_ex5_loadmiss_target :out std_ulogic_vector(0 to 8); -- target gpr + xu_iu_ex5_loadmiss_target_type :out std_ulogic_vector(0 to 1); + xu_iu_ex5_loadmiss_tid :out std_ulogic_vector(0 to 3); + xu_iu_complete_qentry :out std_ulogic_vector(0 to lmq_entries-1); -- Load Miss Complete, Reload came backld_m_rel0_done + xu_iu_complete_tid :out std_ulogic_vector(0 to 3); + xu_iu_complete_target_type :out std_ulogic_vector(0 to 1); + + xu_iu_larx_done_tid :out std_ulogic_vector(0 to 3); + + xu_lsu_ex5_set_barr :in std_ulogic_vector(0 to 3); + + xu_mm_lmq_stq_empty :out std_ulogic; + + lsu_xu_quiesce :out std_ulogic_vector(0 to 3); + + + lsu_xu_dbell_val :out std_ulogic; + lsu_xu_dbell_type :out std_ulogic_vector(0 to 4); + lsu_xu_dbell_brdcast :out std_ulogic; + lsu_xu_dbell_lpid_match :out std_ulogic; + lsu_xu_dbell_pirtag :out std_ulogic_vector(50 to 63); + + ac_an_req_pwr_token :out std_ulogic; -- power token for command coming next cycle + ac_an_req :out std_ulogic; -- command request valid + ac_an_req_ra :out std_ulogic_vector(64-real_data_add to 63); -- real address for request + ac_an_req_ttype :out std_ulogic_vector(0 to 5); -- command (transaction) type + ac_an_req_thread :out std_ulogic_vector(0 to 2); -- encoded thread ID + ac_an_req_wimg_w :out std_ulogic; -- write-through + ac_an_req_wimg_i :out std_ulogic; -- cache-inhibited + ac_an_req_wimg_m :out std_ulogic; -- memory coherence required + ac_an_req_wimg_g :out std_ulogic; -- guarded memory + ac_an_req_endian :out std_ulogic; -- endian mode (0=big endian, 1=little endian) + ac_an_req_user_defined :out std_ulogic_vector(0 to 3); -- user defined bits + ac_an_req_spare_ctrl_a0 :out std_ulogic_vector(0 to 3); -- spare control bits to L2 + ac_an_req_ld_core_tag :out std_ulogic_vector(0 to 4); -- load command tag (which load Q) + ac_an_req_ld_xfr_len :out std_ulogic_vector(0 to 2); -- transfer length for non-cacheable load + -- 000 = reserved 100 = 4 bytes + -- 001 = 1 byte 101 = 8 bytes + -- 010 = 2 bytes 110 = 16 bytes + -- 011 = 3 bytes 111 = 32 bytes + ac_an_st_byte_enbl :out std_ulogic_vector(0 to 15+(st_data_32B_mode*16)); -- byte enables for store data + ac_an_st_data :out std_ulogic_vector(0 to 127+(st_data_32B_mode*128)); -- store data (Prism uses bits 0 to 127 only) + ac_an_st_data_pwr_token :out std_ulogic; -- store data power token + + -- connect to the compare logic + + cmp_lmq_entry_act :out std_ulogic; -- act for lmq entries + cmp_ex3_p_addr_o :in std_ulogic_vector(64-real_data_add to 57); -- erat array output + cmp_ldq_comp_val :out std_ulogic_vector(0 to 7); -- enable compares against lmq + cmp_ldq_match :in std_ulogic_vector(0 to 7); -- compare result (without enable) + cmp_ldq_fnd :in std_ulogic; -- all the enabled compares "OR"ed together + + cmp_l_q_wrt_en :out std_ulogic_vector(0 to 7); -- load entry, (hold when not loading) + cmp_ld_ex7_recov :out std_ulogic; + cmp_ex7_ld_recov_addr :out std_ulogic_vector(64-real_data_add to 57); + + cmp_ex4_loadmiss_qentry :out std_ulogic_vector(0 to 7); -- mux 3 select + cmp_ex4_ld_addr :in std_ulogic_vector(64-real_data_add to 57); -- mux 3 + + cmp_l_q_rd_en :out std_ulogic_vector(0 to 7); -- mux 2 select + cmp_l_miss_entry_addr :in std_ulogic_vector(64-real_data_add to 57); -- mux 2 + + cmp_rel_tag_1hot :out std_ulogic_vector(0 to 7); -- mux 1 select + cmp_rel_addr :in std_ulogic_vector(64-real_data_add to 57); -- mux 1 + + cmp_back_inv_addr :out std_ulogic_vector(64-real_data_add to 57); -- compare to each ldq entry + cmp_back_inv_cmp_val :out std_ulogic_vector(0 to 7); + cmp_back_inv_addr_hit :in std_ulogic_vector(0 to 7); + + cmp_s_m_queue0_addr :out std_ulogic_vector(64-real_data_add to 57); + cmp_st_entry0_val :out std_ulogic ; + cmp_ex3addr_hit_stq :in std_ulogic ; + + cmp_ex4_st_entry_addr :out std_ulogic_vector(64-real_data_add to 57); + cmp_ex4_st_val :out std_ulogic ; + cmp_ex3addr_hit_ex4st :in std_ulogic ; + + -- latch and redrive for BXQ + ac_an_reld_ditc_pop_int : in std_ulogic_vector(0 to 3); + ac_an_reld_ditc_pop_q : out std_ulogic_vector(0 to 3); + bx_ib_empty_int : in std_ulogic_vector(0 to 3); + bx_ib_empty_q : out std_ulogic_vector(0 to 3); + + + + -- Performance Events + lsu_xu_perf_events :out std_ulogic_vector(0 to 8); + + lmq_pe_recov_state :out std_ulogic; + + -- Debug Data Bus + lmq_dbg_dcache_pe :out std_ulogic_vector(1 to 60); + lmq_dbg_l2req :out std_ulogic_vector(0 to 212); + lmq_dbg_rel :out std_ulogic_vector(0 to 140); + lmq_dbg_binv :out std_ulogic_vector(0 to 44); + lmq_dbg_pops :out std_ulogic_vector(0 to 5); + lmq_dbg_grp0 :out std_ulogic_vector(0 to 81); + lmq_dbg_grp1 :out std_ulogic_vector(0 to 81); + lmq_dbg_grp2 :out std_ulogic_vector(0 to 87); + lmq_dbg_grp3 :out std_ulogic_vector(0 to 87); + lmq_dbg_grp4 :out std_ulogic_vector(0 to 87); + lmq_dbg_grp5 :out std_ulogic_vector(0 to 87); + lmq_dbg_grp6 :out std_ulogic_vector(0 to 87); + + -- power + vdd : inout power_logic; + gnd : inout power_logic; + + --pervasive + l2_data_ecc_err_ue :out std_ulogic_vector(0 to 3); + xu_pc_err_l2intrf_ecc :out std_ulogic; + xu_pc_err_l2intrf_ue :out std_ulogic; + xu_pc_err_invld_reld :out std_ulogic; + xu_pc_err_l2credit_overrun :out std_ulogic; + + an_ac_coreid :in std_ulogic_vector(6 to 7); + + nclk :in clk_logic; + sg_0 :in std_ulogic; + func_sl_thold_0_b :in std_ulogic; + func_sl_force :in std_ulogic; + func_slp_sl_thold_0_b :in std_ulogic; + func_slp_sl_force :in std_ulogic; + cfg_slp_sl_thold_0_b :in std_ulogic; + cfg_slp_sl_force :in std_ulogic; + d_mode_dc :in std_ulogic; + delay_lclkr_dc :in std_ulogic; + mpw1_dc_b :in std_ulogic; + mpw2_dc_b :in std_ulogic; + scan_dis_dc_b :in std_ulogic; + bcfg_scan_in :in std_ulogic; + bcfg_scan_out :out std_ulogic; + scan_in :in std_ulogic_vector(0 to 2); + scan_out :out std_ulogic_vector(0 to 2) + ); + + + + +END ; + +ARCHITECTURE xuq_lsu_l2cmdq OF xuq_lsu_l2cmdq IS + +constant REAL_IFAR_length : integer := (real_data_add-4); + +signal c_inh :std_ulogic; +signal ctrl_incr_cmdseq :std_ulogic; +signal ctrl_decr_cmdseq :std_ulogic; +signal ctrl_hold_cmdseq :std_ulogic; +signal cmd_seq_incr :std_ulogic_vector(0 to 4); +signal cmd_seq_decr :std_ulogic_vector(0 to 4); +signal cmd_seq_d :std_ulogic_vector(0 to 4); +signal cmd_seq_l2 :std_ulogic_vector(0 to 4); +signal new_ld_cmd_seq :std_ulogic_vector(0 to 4); +signal cmd_seq_rd_incr :std_ulogic_vector(0 to 4); +signal cmd_seq_rd_d :std_ulogic_vector(0 to 4); +signal cmd_seq_rd_l2 :std_ulogic_vector(0 to 4); +signal ld_q_seq_wrap :std_ulogic; + +signal ld_queue_entry :std_ulogic_vector(0 to 53); +signal ld_queue_addrlo :std_ulogic_vector(57 to 63); +signal st_val :std_ulogic; +signal st_flush :std_ulogic; +signal flush_if_store :std_ulogic; +signal nxt_st_cred_tkn :std_ulogic; +signal sync_flush :std_ulogic; +signal s_m_queue0_d :std_ulogic_vector(0 to (58+(real_data_add-1))); +signal s_m_queue0 :std_ulogic_vector(0 to (58+(real_data_add-1))); +signal ex3_st_entry :std_ulogic_vector(0 to (58+(real_data_add-1))); +signal ex4_st_entry_act :std_ulogic; +signal ex4_st_entry_l2 :std_ulogic_vector(0 to (58+(real_data_add-1))); +signal st_entry0_val_d :std_ulogic; +signal st_entry0_val_l2 :std_ulogic; +signal st_entry0_val_clone_l2 :std_ulogic; +signal ex4_st_val_d :std_ulogic; +signal ex4_st_val_l2 :std_ulogic; +signal ex4_st_valid :std_ulogic; +signal ex5_st_val_l2 :std_ulogic; +signal ex5_st_val_for_flush :std_ulogic; +signal ex6_st_val_l2 :std_ulogic; +signal ex4_st_addr :std_ulogic_vector(64-real_data_add to 63); + +signal ld_m_val :std_ulogic; +signal ex4_ld_m_val :std_ulogic; +signal ex4_ld_m_val_not_fl :std_ulogic; +signal ex4_drop_ld_req :std_ulogic; +signal ex4_drop_touch :std_ulogic; + + +signal my_ex4_flush_l2 :std_ulogic; +signal ld_flush :std_ulogic; +signal ld_queue_full :std_ulogic; +signal comp_val :std_ulogic_vector(0 to lmq_entries-1); +signal l_m_q_cpy :std_ulogic_vector(0 to lmq_entries-1); +signal l_m_q_cpy_nofl :std_ulogic_vector(0 to lmq_entries-1); +signal ex4_lmq_cpy_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal ex5_lmq_cpy_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal l_m_fnd_nofl :std_ulogic; +signal l_q_wrt_en :std_ulogic_vector(0 to lmq_entries-1); +signal ld_entry_val_d :std_ulogic_vector(0 to lmq_entries-1); +signal ld_entry_val_l2 :std_ulogic_vector(0 to lmq_entries-1); + +type load_queue_array is array(0 to lmq_entries-1) of std_ulogic_vector(0 to 53); +signal l_m_queue_d :load_queue_array; +signal l_m_queue :load_queue_array; +type load_queue_addrlo_array is array(0 to lmq_entries-1) of std_ulogic_vector(57 to 63); +signal l_m_queue_addrlo_d :load_queue_addrlo_array; +signal l_m_queue_addrlo :load_queue_addrlo_array; +signal ex4_ld_recov_entry :std_ulogic_vector(0 to 53); +signal ex4_ld_recov_addrlo :std_ulogic_vector(58 to 63); +signal ex4_ld_entry_d :std_ulogic_vector(0 to 14); +signal ex4_ld_entry_l2 :std_ulogic_vector(0 to 14); +signal ex4_classid_l2 :std_ulogic_vector(0 to 1); +signal ex4_ld_recov :std_ulogic_vector(0 to (54+(real_data_add-1))); +signal ex5_ld_recov_d :std_ulogic_vector(0 to (54+(real_data_add-1))); +signal ex6_ld_recov_d :std_ulogic_vector(0 to (54+(real_data_add-1))); +signal ex7_ld_recov_d :std_ulogic_vector(0 to (54+(real_data_add-1))); +signal ex5_ld_recov_l2 :std_ulogic_vector(0 to (54+(real_data_add-1))); +signal ex6_ld_recov_l2 :std_ulogic_vector(0 to (54+(real_data_add-1))); +signal ex7_ld_recov_l2 :std_ulogic_vector(0 to (54+(real_data_add-1))); +signal ex4_ld_entry_hit_st_d :std_ulogic; +signal ex4_ld_entry_hit_st_l2 :std_ulogic; +signal ex4_touch :std_ulogic; +signal ex4_l2only :std_ulogic; +signal ex4_ld_recov_val_d :std_ulogic; +signal ex4_ld_recov_val_l2 :std_ulogic; +signal ex5_ld_recov_val_d :std_ulogic; +signal ex5_ld_recov_val_l2 :std_ulogic; +signal ex5_ld_recov_val_not_fl :std_ulogic; +signal ex6_ld_recov_val_l2 :std_ulogic; +signal ex6_ld_recov_val_not_fl :std_ulogic; +signal ex7_ld_recov_val_l2 :std_ulogic; +signal ex4_ld_recov_ld_hit_st :std_ulogic; +signal ex4_ld_recov_extra :std_ulogic_vector(0 to 3); +signal ex5_ld_recov_extra_d :std_ulogic_vector(0 to 3); +signal ex6_ld_recov_extra_d :std_ulogic_vector(0 to 3); +signal ex7_ld_recov_extra_d :std_ulogic_vector(0 to 3); +signal ex5_ld_recov_extra_l2 :std_ulogic_vector(0 to 3); +signal ex6_ld_recov_extra_l2 :std_ulogic_vector(0 to 3); +signal ex7_ld_recov_extra_l2 :std_ulogic_vector(0 to 3); +signal ex8_ld_recov_extra_l2 :std_ulogic_vector(1 to 3); +signal pe_recov_state_d :std_ulogic; +signal pe_recov_state_l2 :std_ulogic; +signal pe_recov_state_dly_l2 :std_ulogic; +signal pe_recov_ld_num_d :std_ulogic_vector(1 to 3); +signal pe_recov_ld_num_l2 :std_ulogic_vector(1 to 3); +signal pe_recov_ld_val_d :std_ulogic; +signal pe_recov_ld_val_l2 :std_ulogic; +signal pe_recov_stall :std_ulogic; +signal recov_ignr_flush_d :std_ulogic; +signal set_st_hit_recov_ld :std_ulogic; +signal reset_st_hit_recov_ld :std_ulogic; +signal stq_hit_ex6_recov :std_ulogic; +signal ex4st_hit_ex6_recov :std_ulogic; +signal st_hit_recov_ld_d :std_ulogic; +signal st_hit_recov_ld_l2 :std_ulogic; +signal blk_st_for_pe_recov :std_ulogic; +signal blk_st_cred_pop :std_ulogic; + + + +type rel_queue_array is array(0 to lmq_entries-1) of std_ulogic_vector(0 to 33); +signal rel_entry :rel_queue_array; + +signal rel_addr_d :std_ulogic_vector(64-real_data_add to 58); +signal rel_size_d :std_ulogic_vector(0 to 5); +signal rel_rot_sel_d :std_ulogic_vector(0 to 4); +signal rel_th_id_d :std_ulogic_vector(0 to 3); +signal l_m_rel_c_i_beat0_d :std_ulogic_vector(0 to lmq_entries-1); +signal l_m_rel_c_i_val :std_ulogic_vector(0 to lmq_entries-1); +signal l_m_rel_hit_beat0_d :std_ulogic_vector(0 to lmq_entries-1); +signal l_m_rel_hit_beat1_d :std_ulogic_vector(0 to lmq_entries-1); +signal l_m_rel_hit_beat2_d :std_ulogic_vector(0 to lmq_entries-1); +signal l_m_rel_hit_beat3_d :std_ulogic_vector(0 to lmq_entries-1); +signal l_m_rel_hit_beat4_d :std_ulogic_vector(0 to lmq_entries-1); +signal l_m_rel_hit_beat5_d :std_ulogic_vector(0 to lmq_entries-1); +signal l_m_rel_hit_beat6_d :std_ulogic_vector(0 to lmq_entries-1); +signal l_m_rel_hit_beat7_d :std_ulogic_vector(0 to lmq_entries-1); +signal l_m_rel_inprog_d :std_ulogic_vector(0 to lmq_entries-1); +signal l_m_rel_c_i_beat0_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal l_m_rel_hit_beat0_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal l_m_rel_hit_beat1_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal l_m_rel_hit_beat2_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal l_m_rel_hit_beat3_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal l_m_rel_hit_beat4_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal l_m_rel_hit_beat5_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal l_m_rel_hit_beat6_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal l_m_rel_hit_beat7_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal l_m_rel_inprog_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal rel_done_ecc_err :std_ulogic; +signal ld_m_rel_done_d :std_ulogic_vector(0 to lmq_entries-1); +signal ld_m_rel_done_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal ld_m_rel_done_no_retry :std_ulogic_vector(0 to lmq_entries-1); +signal ld_m_rel_done_dly_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal ld_m_rel_done_dly2_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal reset_lmq_entry_rel :std_ulogic_vector(0 to lmq_entries-1); +signal reset_lmq_entry :std_ulogic_vector(0 to lmq_entries-1); +signal reset_ldq_hit_barr :std_ulogic_vector(0 to lmq_entries-1); +signal ldq_retry_d :std_ulogic_vector(0 to lmq_entries-1); +signal ldq_retry_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal ldq_retry_ready :std_ulogic_vector(0 to lmq_entries-1); +signal start_ldq_retry :std_ulogic_vector(0 to lmq_entries-1); +signal retry_started_d :std_ulogic_vector(0 to lmq_entries-1); +signal retry_started_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal ldq_retry_or :std_ulogic; + +signal any_ld_entry_val :std_ulogic; +signal selected_ld_entry_val :std_ulogic; +signal selected_entry_flushed :std_ulogic; +signal cmd_seq_rd_incr_val :std_ulogic; +signal ldq_rd_seq_match_next :std_ulogic_vector(0 to lmq_entries-1); +signal ldq_rd_seq_match_curr :std_ulogic_vector(0 to lmq_entries-1); +signal ldq_rd_seq_match_d :std_ulogic_vector(0 to lmq_entries-1); +signal ldq_rd_seq_match_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal l_q_rd_en :std_ulogic_vector(0 to lmq_entries-1); +signal rd_seq_hit :std_ulogic_vector(0 to lmq_entries-1); +signal rd_seq_num_exits :std_ulogic; +signal rd_seq_num_skip :std_ulogic; +signal blk_ld_for_pe_recov_d :std_ulogic; +signal blk_ld_for_pe_recov_l2 :std_ulogic; + + +signal l_miss_entry :std_ulogic_vector(0 to 53); +signal l_miss_addrlo :std_ulogic_vector(58 to 63); +signal store_sent :std_ulogic; +signal ex5_store_sent :std_ulogic; +signal ex4_sel_st_req :std_ulogic; +signal cred_pop :std_ulogic; +signal ex5_sel_st_req :std_ulogic; +signal load_sent :std_ulogic; +signal load_sent_dbglat_l2 :std_ulogic; +signal load_flushed :std_ulogic; +signal mmu_sent :std_ulogic; +signal mmu_sent_l2 :std_ulogic; +signal mmu_ld_sent :std_ulogic; +signal mmu_st_sent :std_ulogic; +signal l_m_tag :std_ulogic_vector(2 to 4); +signal iu_thrd :std_ulogic_vector(0 to 1); +signal ld_tag :std_ulogic_vector(1 to 4); + + +signal l_m_rel_val_c_i_dly :std_ulogic_vector(0 to lmq_entries-1); + +signal rel_addr_l2 :std_ulogic_vector(64-real_data_add to 58); +signal rel_size_l2 :std_ulogic_vector(0 to 5); +signal rel_rot_sel_l2 :std_ulogic_vector(0 to 4); +signal rel_th_id_l2 :std_ulogic_vector(0 to 3); +signal rel_tar_gpr_d :std_ulogic_vector(0 to 8); +signal rel_tar_gpr_l2 :std_ulogic_vector(0 to 8); + + +signal rel_cache_inh_d :std_ulogic; +signal rel_cache_inh_l2 :std_ulogic; +signal rel_le_mode_d :std_ulogic; +signal rel_vpr_val_d :std_ulogic; +signal rel_vpr_val_l2 :std_ulogic; +signal dcbt_instr :std_ulogic; +signal touch_instr :std_ulogic; +signal l2only_instr :std_ulogic; +signal rel_dcbt_d :std_ulogic; +signal rel_dcbt_l2 :std_ulogic; +signal rel_le_mode_l2 :std_ulogic; +signal rel_algebraic_d :std_ulogic; +signal rel_algebraic_l2 :std_ulogic; +signal rel_lock_en_d :std_ulogic; +signal rel_lock_en_l2 :std_ulogic; +signal rel_classid_d :std_ulogic_vector(0 to 1); +signal rel_classid_l2 :std_ulogic_vector(0 to 1); +signal rel_l2only_d :std_ulogic; +signal rel_l2only_l2 :std_ulogic; +signal rel_l2only_dly_l2 :std_ulogic; +signal rel_dvc1_d :std_ulogic; +signal rel_dvc1_l2 :std_ulogic; +signal rel_dvc2_d :std_ulogic; +signal rel_dvc2_l2 :std_ulogic; +signal rel_watch_en_d :std_ulogic; +signal rel_watch_en_l2 :std_ulogic; +signal lmq_drop_rel_d :std_ulogic_vector(0 to lmq_entries-1); +signal lmq_drop_rel_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal lmq_dvc1_en_d :std_ulogic_vector(0 to lmq_entries-1); +signal lmq_dvc2_en_d :std_ulogic_vector(0 to lmq_entries-1); +signal lmq_dvc1_en_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal lmq_dvc2_en_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal ldq_rel1_val_buf :std_ulogic; +signal ldq_rel_mid_val_buf :std_ulogic; +signal ldq_rel3_val_buf :std_ulogic; +signal ldq_rel_retry_val_buf :std_ulogic; +signal ldq_rel_data_val_buf :std_ulogic; +signal ldq_rel_upd_gpr_buf :std_ulogic; +signal ldq_rel_set_val_buf :std_ulogic; +signal l2only_from_queue :std_ulogic; + + +signal rel_q_entry :std_ulogic_vector(0 to 33); +signal rel_q_addrlo_58 :std_ulogic; + +signal l_m_fnd_stg :std_ulogic; + +signal ld_rel_val_d :std_ulogic_vector(0 to lmq_entries-1); +signal ld_rel_val_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal l_m_q_hit_st_d :std_ulogic_vector(0 to lmq_entries-1); +signal l_m_q_hit_st_l2 :std_ulogic_vector(0 to lmq_entries-1); + +signal ex3_new_target_gpr :std_ulogic_vector(0 to 8); +signal cmd_type_ld :std_ulogic_vector(0 to 5); +signal cmd_type_st :std_ulogic_vector(0 to 5); +signal load_val :std_ulogic; +signal load_l1hit_val :std_ulogic; +signal ex4_load_l1hit_val :std_ulogic; +signal hwsync_val :std_ulogic; +signal lwsync_val :std_ulogic; +signal mbar_val :std_ulogic; +signal ldq_barr_done :std_ulogic_vector(0 to 3); +signal ldq_barr_done_l2 :std_ulogic_vector(0 to 3); +signal sync_done_tid :std_ulogic_vector(0 to 3); +signal sync_done_tid_l2 :std_ulogic_vector(0 to 3); +signal lmq_barr_done_tid :std_ulogic_vector(0 to 3); +signal ldq_barr_active_d :std_ulogic_vector(0 to 3); +signal ldq_barr_active_l2 :std_ulogic_vector(0 to 3); +signal lmq_collision_t0_d :std_ulogic_vector(0 to lmq_entries-1); +signal lmq_collision_t0_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal lmq_collision_t1_d :std_ulogic_vector(0 to lmq_entries-1); +signal lmq_collision_t1_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal lmq_collision_t2_d :std_ulogic_vector(0 to lmq_entries-1); +signal lmq_collision_t2_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal lmq_collision_t3_d :std_ulogic_vector(0 to lmq_entries-1); +signal lmq_collision_t3_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal dcbf_l_val :std_ulogic; +signal dcbf_g_val :std_ulogic; +signal dcbt_l2only_val :std_ulogic; +signal dcbt_l1l2_val :std_ulogic; +signal dcbtls_l2only_val :std_ulogic; +signal dcbtls_l1l2_val :std_ulogic; +signal dcbtst_l2only_val :std_ulogic; +signal dcbtst_l1l2_val :std_ulogic; +signal dcbtstls_l2only_val :std_ulogic; +signal dcbtstls_l1l2_val :std_ulogic; + + +signal ifetch_req_l2 :std_ulogic; +signal ifetch_ra_l2 :std_ulogic_vector(64-real_data_add to 59); +signal ifetch_thread_l2 :std_ulogic_vector(0 to 3); +signal ifetch_userdef_l2 :std_ulogic_vector(0 to 3); +signal ifetch_wimge_l2 :std_ulogic_vector(0 to 4); +signal iu_f_tid0_val :std_ulogic; +signal iu_f_tid1_val :std_ulogic; +signal iu_f_tid2_val :std_ulogic; +signal iu_f_tid3_val :std_ulogic; +signal iu_seq_rd_incr :std_ulogic_vector(0 to 2); +signal iu_seq_rd_d :std_ulogic_vector(0 to 2); +signal iu_seq_rd_l2 :std_ulogic_vector(0 to 2); +signal iu_seq_incr :std_ulogic_vector(0 to 2); +signal iu_seq_d :std_ulogic_vector(0 to 2); +signal iu_seq_l2 :std_ulogic_vector(0 to 2); +signal iu_queue_entry :std_ulogic_vector(0 to (REAL_IFAR_length+11)); +signal iu_f_q0_val_upd :std_ulogic_vector(0 to 1); +signal i_f_q0_val_d :std_ulogic; +signal i_f_q0_val_l2 :std_ulogic; +signal i_f_q0_d :std_ulogic_vector(0 to (REAL_IFAR_length+11)); +signal i_f_q0_l2 :std_ulogic_vector(0 to (REAL_IFAR_length+11)); +signal iu_f_q1_val_upd :std_ulogic_vector(0 to 1); +signal i_f_q1_val_d :std_ulogic; +signal i_f_q1_val_l2 :std_ulogic; +signal i_f_q1_d :std_ulogic_vector(0 to (REAL_IFAR_length+11)); +signal i_f_q1_l2 :std_ulogic_vector(0 to (REAL_IFAR_length+11)); +signal iu_f_q2_val_upd :std_ulogic_vector(0 to 1); +signal i_f_q2_val_d :std_ulogic; +signal i_f_q2_val_l2 :std_ulogic; +signal i_f_q2_d :std_ulogic_vector(0 to (REAL_IFAR_length+11)); +signal i_f_q2_l2 :std_ulogic_vector(0 to (REAL_IFAR_length+11)); +signal iu_f_q3_val_upd :std_ulogic_vector(0 to 1); +signal i_f_q3_val_d :std_ulogic; +signal i_f_q3_val_l2 :std_ulogic; +signal i_f_q3_d :std_ulogic_vector(0 to (REAL_IFAR_length+11)); +signal i_f_q3_l2 :std_ulogic_vector(0 to (REAL_IFAR_length+11)); +signal iu_f_q0_sel :std_ulogic; +signal iu_f_q1_sel :std_ulogic; +signal iu_f_q2_sel :std_ulogic; +signal iu_f_q3_sel :std_ulogic; +signal iu_f_q_sel :std_ulogic_vector(0 to 1); +signal iu_f_sel_entry :std_ulogic_vector(0 to (9+REAL_IFAR_length-1)); +signal i_f_q0_sent :std_ulogic; +signal i_f_q1_sent :std_ulogic; +signal i_f_q2_sent :std_ulogic; +signal i_f_q3_sent :std_ulogic; +signal iu_val_req :std_ulogic; +signal iu_sent_val :std_ulogic; +signal sel_if_req :std_ulogic; +signal sel_ld_req :std_ulogic; +signal sel_mm_req :std_ulogic; +signal send_if_req_d :std_ulogic; +signal send_if_req_l2 :std_ulogic; +signal send_ld_req_d :std_ulogic; +signal send_ld_req_l2 :std_ulogic; +signal send_mm_req_d :std_ulogic; +signal send_mm_req_l2 :std_ulogic; +signal iu_f_entry :std_ulogic_vector(0 to (real_data_add-1+54)); +signal iu_mmu_entry :std_ulogic_vector(0 to (real_data_add-1+54)); +signal ldmq_entry :std_ulogic_vector(0 to (real_data_add-1+54)); +signal store_entry :std_ulogic_vector(0 to (real_data_add-1+54)); +signal st_req :std_ulogic_vector(0 to (real_data_add-1+54)); +signal ob_store :std_ulogic_vector(0 to (real_data_add-1+54)); +signal st_recycle_entry :std_ulogic_vector(0 to (real_data_add-1+54)); +signal st_recycle_d :std_ulogic_vector(0 to (real_data_add-1+54)); +signal st_recycle_l2 :std_ulogic_vector(0 to (real_data_add-1+54)); +signal st_recycle_act :std_ulogic; +signal st_recycle_v_d :std_ulogic; +signal st_recycle_v_l2 :std_ulogic; +signal ld_st_request :std_ulogic_vector(0 to (real_data_add-1+54)); +signal mmuq_req :std_ulogic_vector(0 to (real_data_add-1+54)); +signal iu_val :std_ulogic; +signal ld_q_val :std_ulogic; +signal ld_q_req :std_ulogic; +signal state_trans :std_ulogic; +signal mmu_q_val :std_ulogic; +signal reld_data_vld_l2 :std_ulogic; +signal reld_data_vld_dplus1_l2 :std_ulogic; + +signal load_credit :std_ulogic; +signal store_credit :std_ulogic; +signal one_st_cred :std_ulogic; +signal ld_credit_pre :std_ulogic; +signal st_credit_pre :std_ulogic; +signal load_credit_used :std_ulogic; +signal decr_load_cnt_lcu0 :std_ulogic; +signal dec_by2_ld_cnt_lcu0 :std_ulogic; +signal hold_load_cnt_lcu0 :std_ulogic; +signal incr_load_cnt_lcu1 :std_ulogic; +signal decr_load_cnt_lcu1 :std_ulogic; +signal hold_load_cnt_lcu1 :std_ulogic; +signal load_cmd_count_incr :std_ulogic_vector(0 to 3); +signal load_cmd_count_decr :std_ulogic_vector(0 to 3); +signal load_cmd_count_decrby2 :std_ulogic_vector(0 to 3); +signal load_cmd_count_lcu0 :std_ulogic_vector(0 to 3); +signal load_cmd_count_lcu1 :std_ulogic_vector(0 to 3); +signal load_cmd_count_d :std_ulogic_vector(0 to 3); +signal load_cmd_count_l2 :std_ulogic_vector(0 to 3); +signal store_cmd_count_incr :std_ulogic_vector(0 to 5); +signal store_cmd_count_decr :std_ulogic_vector(0 to 5); +signal store_cmd_count_decby2 :std_ulogic_vector(0 to 5); +signal store_cmd_count_decby3 :std_ulogic_vector(0 to 5); +signal store_cmd_count_d :std_ulogic_vector(0 to 5); +signal store_cmd_count_l2 :std_ulogic_vector(0 to 5); +signal incr_store_cmd :std_ulogic; +signal decr_store_cmd :std_ulogic; +signal dec_by2_st_cmd :std_ulogic; +signal dec_by3_st_cmd :std_ulogic; +signal hold_store_cmd :std_ulogic; +signal st_count_ctrl :std_ulogic_vector(0 to 3); +signal err_cred_overrun_d :std_ulogic; +signal err_cred_overrun_l2 :std_ulogic; + +signal l2req_resend_d :std_ulogic; +signal l2req_resend_l2 :std_ulogic; +signal l2req_recycle_d :std_ulogic; +signal l2req_recycle_l2 :std_ulogic; +signal l2req_pwr_token :std_ulogic; +signal l2req_pwr_token_l2 :std_ulogic; +signal l2req :std_ulogic; +signal l2req_gated :std_ulogic; +signal l2req_l2 :std_ulogic; +signal l2req_st_data_ptoken :std_ulogic; +signal l2req_st_data_ptoken_l2 :std_ulogic; +signal l2req_ra :std_ulogic_vector(64-real_data_add to 63); +signal l2req_ra_l2 :std_ulogic_vector(64-real_data_add to 63); +signal l2req_st_byte_enbl :std_ulogic_vector(0 to 15+(st_data_32B_mode*16)); +signal l2req_st_byte_enbl_l2 :std_ulogic_vector(0 to 15+(st_data_32B_mode*16)); +signal l2req_ld_core_tag :std_ulogic_vector(0 to 4); +signal l2req_ld_core_tag_l2 :std_ulogic_vector(0 to 4); +signal l2req_thread :std_ulogic_vector(0 to 2); +signal l2req_thread_l2 :std_ulogic_vector(0 to 2); +signal l2req_ttype :std_ulogic_vector(0 to 5); +signal l2req_ttype_l2 :std_ulogic_vector(0 to 5); +signal l2req_wimg :std_ulogic_vector(0 to 3); +signal l2req_wimg_l2 :std_ulogic_vector(0 to 3); +signal l2req_ld_xfr_len :std_ulogic_vector(0 to 2); +signal l2req_ld_xfr_len_l2 :std_ulogic_vector(0 to 2); +signal l2req_endian :std_ulogic; +signal l2req_endian_l2 :std_ulogic; +signal l2req_user :std_ulogic_vector(0 to 3); +signal l2req_user_l2 :std_ulogic_vector(0 to 3); +signal ex4_st_data_mux :std_ulogic_vector(0 to 127+(st_data_32B_mode*128)); +signal ex4_st_data_mux2 :std_ulogic_vector(0 to 127+(st_data_32B_mode*128)); +signal ex5_st_data_mux1 :std_ulogic_vector(0 to 127); +signal ex5_st_data_mux2 :std_ulogic_vector(0 to 127); +signal ex5_st_data_mux :std_ulogic_vector(0 to 127+(st_data_32B_mode*128)); +signal ex5_st_data_l2 :std_ulogic_vector(0 to 127+(st_data_32B_mode*128)); +signal ex6_st_data_l2 :std_ulogic_vector(0 to 127+(st_data_32B_mode*128)); + +signal sync_done :std_ulogic; +signal rel_tag_l2 :std_ulogic_vector(1 to 4); +signal rel_tag_dplus1_l2 :std_ulogic_vector(1 to 4); +signal rel_data_val :std_ulogic_vector(0 to lmq_entries-1); +signal start_rel :std_ulogic_vector(0 to lmq_entries-1); +signal rel_data_val_dplus1 :std_ulogic_vector(0 to lmq_entries-1); +signal set_data_ecc_err :std_ulogic_vector(0 to lmq_entries-1); +signal data_ecc_err_d :std_ulogic_vector(0 to lmq_entries-1); +signal data_ecc_err_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal set_data_ecc_ue :std_ulogic_vector(0 to lmq_entries-1); +signal data_ecc_ue_d :std_ulogic_vector(0 to lmq_entries-1); +signal data_ecc_ue_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal rel_tag_1hot :std_ulogic_vector(0 to lmq_entries-1); +signal I1_G1_thrd0 :std_ulogic; +signal I1_G1_thrd1 :std_ulogic; +signal I1_G1_thrd2 :std_ulogic; +signal I1_G1_thrd3 :std_ulogic; +signal I1_G1_flush :std_ulogic; +signal ex4_l2cmdq_flush_d :std_ulogic_vector(0 to 4); +signal ex4_l2cmdq_flush_l2 :std_ulogic_vector(0 to 4); +signal ex4_st_I1_G1_val :std_ulogic; +signal st_entry_I1_G1_val :std_ulogic; +signal ex3_wimg_g_gated :std_ulogic; +signal ecc_err :std_ulogic_vector(0 to lmq_entries-1); +signal rel_vpr_compl :std_ulogic; +signal rel_compl :std_ulogic; +signal update_gpr :std_ulogic; +signal update_gpr_l2 :std_ulogic; +signal set_gpr_updated_prev :std_ulogic_vector(0 to lmq_entries-1); +signal selectedQ_gpr_update_prev :std_ulogic; +signal selectedQ_ecc_err :std_ulogic; +signal rel_beat_crit_qw_block_d :std_ulogic; +signal gpr_updated_prev_d :std_ulogic_vector(0 to lmq_entries-1); +signal gpr_updated_prev_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal gpr_updated_dly1_d :std_ulogic_vector(0 to lmq_entries-1); +signal gpr_updated_dly2_d :std_ulogic_vector(0 to lmq_entries-1); +signal gpr_updated_dly1_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal gpr_updated_dly2_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal set_gpr_ecc_err :std_ulogic_vector(0 to lmq_entries-1); +signal reset_gpr_ecc_err :std_ulogic_vector(0 to lmq_entries-1); +signal gpr_ecc_err_d :std_ulogic_vector(0 to lmq_entries-1); +signal gpr_ecc_err_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal complete_qentry :std_ulogic_vector(0 to lmq_entries-1); +signal even_beat :std_ulogic_vector(0 to lmq_entries-1); +signal ldm_complete_qentry :std_ulogic_vector(0 to lmq_entries-1); +signal ldm_comp_qentry_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal ci_16B_comp_qentry :std_ulogic_vector(0 to lmq_entries-1); +signal larx_done :std_ulogic_vector(0 to lmq_entries-1); +signal complete_tid_d :std_ulogic_vector(0 to 3); +signal larx_done_tid_d :std_ulogic_vector(0 to 3); +signal larx_done_tid_l2 :std_ulogic_vector(0 to 3); +signal complete_target_type_d :std_ulogic_vector(0 to 1); + +signal mmq_act :std_ulogic; +signal mmu_q_val_d :std_ulogic; +signal mmu_q_val_l2 :std_ulogic; +signal mm_req_val_d :std_ulogic; +signal mm_req_val_l2 :std_ulogic; +signal mmu_command :std_ulogic_vector(0 to (25+real_data_add)); +signal mmu_q_entry_d :std_ulogic_vector(0 to (25+real_data_add)); +signal mmu_q_entry_l2 :std_ulogic_vector(0 to (25+real_data_add)); + +signal my_beat1 :std_ulogic; +signal my_beat1_early :std_ulogic; +signal my_beat_last_d :std_ulogic; +signal my_beat_last_l2 :std_ulogic; +signal my_beat_mid :std_ulogic; +signal my_beat_odd :std_ulogic; +signal my_noncache_beat :std_ulogic; +signal my_ldq_retry :std_ulogic; + +signal rel_A_data_d :std_ulogic_vector(0 to 127); +signal rel_A_data_l2 :std_ulogic_vector(0 to 127); +signal rel_B_data_d :std_ulogic_vector(0 to 127); +signal rel_B_data_l2 :std_ulogic_vector(0 to 127); +signal set_rel_A_data :std_ulogic; +signal set_rel_B_data :std_ulogic; +signal send_rel_A_data_d :std_ulogic; +signal send_rel_A_data_l2 :std_ulogic; + +signal anaclat_data_coming :std_ulogic; +signal anaclat_reld_crit_qw :std_ulogic; +signal anaclat_data_val :std_ulogic; +signal anaclat_ditc :std_ulogic; +signal anaclat_tag :std_ulogic_vector(0 to 4); +signal anaclat_qw :std_ulogic_vector(57 to 59); +signal anaclat_data :std_ulogic_vector(0 to 127); +signal anaclat_ecc_err :std_ulogic; +signal anaclat_ecc_err_ue :std_ulogic; +signal beat_ecc_err :std_ulogic; +signal ue_mchk_v :std_ulogic; +signal ue_mchk_valid_d :std_ulogic_vector(0 to 3); +signal ue_mchk_valid_l2 :std_ulogic_vector(0 to 3); +signal anaclat_l1_dump :std_ulogic; +signal dminus1_l1_dump :std_ulogic; +signal dminus1_l1_dump_gated :std_ulogic; +signal l1_dump :std_ulogic; +signal anaclat_back_inv :std_ulogic; +signal anaclat_back_inv_addr :std_ulogic_vector(64-real_data_add to 63); +signal anaclat_back_inv_target_1 :std_ulogic; +signal anaclat_back_inv_target_4 :std_ulogic; +signal anaclat_ld_pop :std_ulogic; +signal anaclat_st_pop :std_ulogic; +signal anaclat_st_pop_thrd :std_ulogic_vector(0 to 2); +signal anaclat_st_gather :std_ulogic; +signal anaclat_coreid :std_ulogic_vector(6 to 7); +signal data_val_for_rel :std_ulogic; +signal data_val_dminus2 :std_ulogic; +signal data_val_dminus1_l2 :std_ulogic; +signal ldq_rel_retry_val_l2 :std_ulogic; +signal ldq_rel_retry_val_dly_l2 :std_ulogic; +signal rel_intf_v_dminus1_l2 :std_ulogic; +signal rel_intf_v_l2 :std_ulogic; +signal rel_intf_v_dplus1_l2 :std_ulogic; +signal tag_dminus2 :std_ulogic_vector(1 to 4); +signal ldq_retry_tag :std_ulogic_vector(1 to 4); +signal tag_dminus1_l2 :std_ulogic_vector(1 to 4); +signal tag_dminus1_cpy_l2 :std_ulogic_vector(2 to 4); +signal tag_dminus1_act :std_ulogic; +signal tag_dminus1_1hot_d :std_ulogic_vector(0 to lmq_entries-1); +signal tag_dminus1_1hot_l2 :std_ulogic_vector(0 to lmq_entries-1); +signal qw_dminus1_l2 :std_ulogic_vector(57 to 59); +signal qw_l2 :std_ulogic_vector(57 to 59); +signal back_inv_val_d :std_ulogic; +signal back_inv_val_l2 :std_ulogic; +signal dbell_val_d :std_ulogic; +signal dbell_val_l2 :std_ulogic; +signal lpidr_l2 :std_ulogic_vector(0 to 7); +signal rel_set_val :std_ulogic_vector(0 to lmq_entries-1); +signal rel_cacheable :std_ulogic_vector(0 to lmq_entries-1); +signal rel_set_val_or :std_ulogic; +signal lmq_back_invalidated_d :std_ulogic_vector(0 to lmq_entries-1); +signal lmq_back_invalidated_l2 :std_ulogic_vector(0 to lmq_entries-1); + +signal ex3_loadmiss_qentry :std_ulogic_vector(0 to lmq_entries-1); -- Load Miss Queue entry +signal ex4_loadmiss_qentry :std_ulogic_vector(0 to lmq_entries-1); -- Load Miss Queue entry +signal ex5_loadmiss_qentry_d :std_ulogic_vector(0 to lmq_entries-1); -- Load Miss Queue entry +signal ex6_loadmiss_qentry_d :std_ulogic_vector(0 to lmq_entries-1); -- Load Miss Queue entry +signal ex7_loadmiss_qentry_d :std_ulogic_vector(0 to lmq_entries-1); -- Load Miss Queue entry +signal ex5_loadmiss_qentry :std_ulogic_vector(0 to lmq_entries-1); -- Load Miss Queue entry +signal ex6_loadmiss_qentry :std_ulogic_vector(0 to lmq_entries-1); -- Load Miss Queue entry +signal ex7_loadmiss_qentry :std_ulogic_vector(0 to lmq_entries-1); -- Load Miss Queue entry +signal ex3_loadmiss_target :std_ulogic_vector(0 to 8); -- target gpr +signal ex3_loadmiss_target_type :std_ulogic_vector(0 to 1); +signal ex3_loadmiss_tid :std_ulogic_vector(0 to 3); +signal ex4_loadmiss_tid :std_ulogic_vector(0 to 3); +signal ex4_loadmiss_target :std_ulogic_vector(0 to 8); -- target gpr +signal ex4_loadmiss_target_type :std_ulogic_vector(0 to 1); +signal ex4_loadmiss_tid_gated1 :std_ulogic_vector(0 to 3); +signal ex4_loadmiss_tid_gated :std_ulogic_vector(0 to 3); +signal ex5_loadmiss_tid :std_ulogic_vector(0 to 3); + +signal xu_mm_lmq_stq_empty_d :std_ulogic; +signal lmq_empty :std_ulogic; +signal pe_recov_empty_d :std_ulogic; +signal pe_recov_empty_l2 :std_ulogic; + +signal err_l2intrf_ecc_d :std_ulogic; +signal err_l2intrf_ue_d :std_ulogic; +signal err_l2intrf_ecc_l2 :std_ulogic; +signal err_l2intrf_ue_l2 :std_ulogic; + +signal src0_hit :std_ulogic_vector(0 to lmq_entries-1); +signal src1_hit :std_ulogic_vector(0 to lmq_entries-1); +signal targ_hit :std_ulogic_vector(0 to lmq_entries-1); +signal watch_bit_v_t0 :std_ulogic_vector(0 to lmq_entries-1); +signal watch_bit_v_t1 :std_ulogic_vector(0 to lmq_entries-1); +signal watch_bit_v_t2 :std_ulogic_vector(0 to lmq_entries-1); +signal watch_bit_v_t3 :std_ulogic_vector(0 to lmq_entries-1); +signal ex1_lm_dep_hit :std_ulogic; +signal ex2_lm_dep_hit_buf :std_ulogic; +signal watch_hit_t0 :std_ulogic; +signal watch_hit_t1 :std_ulogic; +signal watch_hit_t2 :std_ulogic; +signal watch_hit_t3 :std_ulogic; +signal watch_hit :std_ulogic; + +signal lq_rd_en_is_ex5 :std_ulogic; +signal lq_rd_en_is_ex6 :std_ulogic; + + +signal lmq_quiesce :std_ulogic_vector(0 to 3); +signal mmu_quiesce :std_ulogic_vector(0 to 3); +signal stq_quiesce :std_ulogic_vector(0 to 3); +signal quiesce_d :std_ulogic_vector(0 to 3); + +signal ex3_flush_all :std_ulogic; +signal ex4_flush_load :std_ulogic; +signal ex4_flush_load_wo_drop :std_ulogic; +signal ex4_flush_store :std_ulogic; +signal ex5_load :std_ulogic; +signal ex6_load_sent_l2 :std_ulogic; +signal ex6_store_sent_l2 :std_ulogic; +signal ex5_flush_d :std_ulogic; +signal ex5_flush_l2 :std_ulogic; +signal my_ex5_flush :std_ulogic; +signal ex5_flush_load_all :std_ulogic; +signal ex5_flush_load_local :std_ulogic; +signal ex4_p_addr_59 :std_ulogic; +signal ex5_stg_flush :std_ulogic; +signal ex5_flush_store :std_ulogic; +signal my_ex5_flush_store :std_ulogic; +signal ex6_flush_l2 :std_ulogic; + + +signal copy_st_be_for_16B_mode :std_ulogic; +signal copy_st_data_for_16B_mode :std_ulogic; + +signal err_invld_reld_d :std_ulogic; +signal err_invld_reld_l2 :std_ulogic; + +signal ex7_ld_par_err :std_ulogic; +signal ex8_ld_par_err_l2 :std_ulogic; +signal ex4_ld_queue_full :std_ulogic; +signal ex4_ld_queue_full_l2 :std_ulogic; +signal ex5_ld_queue_full_d :std_ulogic; +signal ex5_ld_queue_full_l2 :std_ulogic; +signal ex4_st_queue_full :std_ulogic; +signal ex4_st_queue_full_l2 :std_ulogic; +signal ex5_st_queue_full_l2 :std_ulogic; +signal ex4_ldhld_sthld_coll :std_ulogic; +signal ex5_ldhld_sthld_coll_l2 :std_ulogic; +signal ex3_i1_g1_coll :std_ulogic; +signal ex4_i1_g1_coll_l2 :std_ulogic; +signal ex5_i1_g1_coll_l2 :std_ulogic; +signal ld_miss_latency_d :std_ulogic; +signal ld_miss_latency_l2 :std_ulogic; +signal lsu_perf_events :std_ulogic_vector(0 to 3); +signal lsu_perf_events_l2 :std_ulogic_vector(0 to 3); +signal ex3_val_req :std_ulogic; +signal ex4_val_req :std_ulogic; +signal ex4_thrd_encode :std_ulogic_vector(0 to 1); +signal ex4_thrd_id :std_ulogic_vector(0 to 3); +signal ex5_thrd_id :std_ulogic_vector(0 to 3); + +signal ob_pwr_tok_l2 :std_ulogic; +signal ob_req_val_mux :std_ulogic; +signal ob_req_val_l2 :std_ulogic; +signal ob_req_val_clone_l2 :std_ulogic; +signal ob_ditc_val_mux :std_ulogic; +signal ob_ditc_val_l2 :std_ulogic; +signal ob_ditc_val_clone_l2 :std_ulogic; +signal ob_thrd_mux :std_ulogic_vector(0 to 1); +signal ob_thrd_l2 :std_ulogic_vector(0 to 1); +signal ob_qw_mux :std_ulogic_vector(58 to 59); +signal ob_qw_l2 :std_ulogic_vector(58 to 59); +signal ob_dest_mux :std_ulogic_vector(0 to 14); +signal ob_dest_l2 :std_ulogic_vector(0 to 14); +signal ob_addr_mux :std_ulogic_vector(64-real_data_add to 57); +signal ob_addr_l2 :std_ulogic_vector(64-real_data_add to 57); +signal ob_data_mux :std_ulogic_vector(0 to 127); +signal ob_data_l2 :std_ulogic_vector(0 to 127); +signal bx_cmd_sent_d :std_ulogic; +signal bx_cmd_sent_l2 :std_ulogic; +signal bx_cmd_stall_d :std_ulogic; +signal bx_cmd_stall_l2 :std_ulogic; +signal bx_stall_dly_or :std_ulogic; +signal bx_stall_dly_d :std_ulogic_vector(0 to 3); +signal bx_stall_dly_l2 :std_ulogic_vector(0 to 3); +signal msr_gs_l2 :std_ulogic_vector(0 to 3); +signal msr_pr_l2 :std_ulogic_vector(0 to 3); +signal msr_ds_l2 :std_ulogic_vector(0 to 3); +signal msr_hv :std_ulogic; +signal msr_pr :std_ulogic; +signal msr_ds :std_ulogic; +signal pid :std_ulogic_vector(0 to 13); +signal pid0_l2 :std_ulogic_vector(0 to 13); +signal pid1_l2 :std_ulogic_vector(0 to 13); +signal pid2_l2 :std_ulogic_vector(0 to 13); +signal pid3_l2 :std_ulogic_vector(0 to 13); +signal ditc_dat :std_ulogic_vector(0 to 127); +signal ex4_icswx_extra_data :std_ulogic_vector(0 to 24); +signal stq_icswx_extra_data_d :std_ulogic_vector(0 to 24); +signal stq_icswx_extra_data_l2 :std_ulogic_vector(0 to 24); +signal icswx_dat :std_ulogic_vector(0 to 127); +signal epsc_epr :std_ulogic; +signal epsc_eas :std_ulogic; +signal epsc_egs :std_ulogic; +signal epsc_elpid :std_ulogic_vector(40 to 47); +signal epsc_epid :std_ulogic_vector(50 to 63); + +signal my_xucr0_d :std_ulogic_vector(0 to 5); +signal my_xucr0_l2 :std_ulogic_vector(0 to 5); +signal my_xucr0_rel :std_ulogic; +signal my_xucr0_l2siw :std_ulogic; +signal my_xucr0_cred :std_ulogic; +signal my_xucr0_mbar_ack :std_ulogic; +signal my_xucr0_tlbsync :std_ulogic; +signal my_xucr0_cls :std_ulogic; + +signal ex3_p_addr :std_ulogic_vector(64-real_data_add to 63); + +signal clkg_ctl_override_q :std_ulogic; +signal ldq_active_d :std_ulogic; +signal ldq_active_l2 :std_ulogic; +signal ldq_active_dly_d :std_ulogic; +signal ldq_active_dly_l2 :std_ulogic; +signal ldq_act :std_ulogic; +signal stq_active_d :std_ulogic; +signal stq_active_l2 :std_ulogic; +signal stq_act :std_ulogic; +signal lmq_entry_act :std_ulogic; +signal ifetch_act :std_ulogic; +signal iuq_act :std_ulogic; +signal ob_act :std_ulogic; +signal pe_act :std_ulogic; +signal dminus1_act :std_ulogic; +signal dplus1_act :std_ulogic; +signal rel_data_act :std_ulogic; +signal bi_act :std_ulogic; +signal ex6_ld_recov_act :std_ulogic; +signal ex7_ld_recov_act :std_ulogic; +signal ex8_ld_recov_act :std_ulogic; +signal l2req_act :std_ulogic; +signal st_data_act :std_ulogic; + +signal data_val_for_drel :std_ulogic; +signal data_val_for_recirc :std_ulogic; + +signal spare_0_lclk :clk_logic; +signal spare_1_lclk :clk_logic; +signal spare_4_lclk :clk_logic; +signal spare_0_d1clk :std_ulogic; +signal spare_1_d1clk :std_ulogic; +signal spare_4_d1clk :std_ulogic; +signal spare_0_d2clk :std_ulogic; +signal spare_1_d2clk :std_ulogic; +signal spare_4_d2clk :std_ulogic; +signal spare_0_d :std_ulogic_vector(0 to 7); +signal spare_1_d :std_ulogic_vector(0 to 4); +signal spare_4_d :std_ulogic_vector(0 to 7); +signal spare_0_l2 :std_ulogic_vector(0 to 7); +signal spare_1_l2 :std_ulogic_vector(0 to 4); +signal spare_4_l2 :std_ulogic_vector(0 to 7); + +signal dbg_d :std_ulogic_vector(0 to 40+lmq_entries-1); +signal dbg_L2 :std_ulogic_vector(0 to 40+lmq_entries-1); + + +signal unused :std_ulogic_vector(0 to 3); + +constant clkg_ctl_override_offset : natural := 0; +constant ldq_active_offset : natural :=clkg_ctl_override_offset + 1; +constant ldq_active_dly_offset : natural :=ldq_active_offset + 1; +constant stq_active_offset : natural :=ldq_active_dly_offset + 1; +constant ex7_ld_par_err_offset : natural :=stq_active_offset + 1; +constant ex8_ld_par_err_offset : natural :=ex7_ld_par_err_offset + 1; +constant my_ex4_flush_offset : natural :=ex8_ld_par_err_offset + 1; +constant pe_recov_empty_offset : natural :=my_ex4_flush_offset + 1; +constant pe_recov_state_offset : natural :=pe_recov_empty_offset + 1; + +constant pe_recov_state_dly_offset : natural :=pe_recov_state_offset + 1; +constant pe_recov_ld_num_offset : natural :=pe_recov_state_dly_offset + 1; + +constant pe_recov_ld_val_offset : natural :=pe_recov_ld_num_offset + pe_recov_ld_num_l2'length; +constant my_xucr0_offset : natural :=pe_recov_ld_val_offset + 1; +constant anac_data_coming_offset : natural :=my_xucr0_offset + my_xucr0_l2'length; +constant anac_reld_crit_qw_offset : natural :=anac_data_coming_offset + 1; +constant anac_data_val_offset : natural :=anac_reld_crit_qw_offset + 1; +constant anac_ditc_offset : natural :=anac_data_val_offset + 1; +constant anac_tag_offset : natural :=anac_ditc_offset + 1; +constant anac_qw_offset : natural :=anac_tag_offset + anaclat_tag'length; +constant anac_data_offset : natural :=anac_qw_offset + anaclat_qw'length; +constant anac_ecc_err_offset : natural :=anac_data_offset + anaclat_data'length; +constant anac_ecc_err_ue_offset : natural :=anac_ecc_err_offset + 1; +constant ue_mchk_val_offset : natural := anac_ecc_err_ue_offset + 1; +constant anac_l1_dump_offset : natural := ue_mchk_val_offset + ue_mchk_valid_l2'length; +constant dminus1_l1_dump_offset : natural := anac_l1_dump_offset + 1; +constant l1_dump_offset : natural := dminus1_l1_dump_offset + 1; +constant anac_back_inv_offset : natural := l1_dump_offset + 1; +constant anac_back_inv_addr_offset : natural := anac_back_inv_offset + 1; +constant anac_back_inv_target1_offset : natural := anac_back_inv_addr_offset + anaclat_back_inv_addr'length; +constant anac_back_inv_target4_offset : natural :=anac_back_inv_target1_offset + 1; +constant data_val_dminus1_offset : natural :=anac_back_inv_target4_offset + 1; +constant spare_0_offset : natural :=data_val_dminus1_offset + 1; +constant ldq_rel_retry_val_offset : natural :=spare_0_offset + spare_0_l2'length; +constant ldq_rel_retry_val_dly_offset : natural :=ldq_rel_retry_val_offset + 1; +constant rel_intf_v_dminus1_offset : natural :=ldq_rel_retry_val_dly_offset + 1; +constant rel_intf_v_offset : natural :=rel_intf_v_dminus1_offset + 1; +constant rel_intf_v_dplus1_offset : natural :=rel_intf_v_offset + 1; +constant retry_started_offset : natural :=rel_intf_v_dplus1_offset + 1; + +constant tag_dminus1_offset : natural :=retry_started_offset + retry_started_l2'length; +constant tag_dminus1_cpy_offset : natural :=tag_dminus1_offset + tag_dminus1_l2'length; +constant tag_dminus1_1hot_offset : natural :=tag_dminus1_cpy_offset + tag_dminus1_cpy_l2'length; +constant qw_dminus1_offset : natural :=tag_dminus1_1hot_offset + tag_dminus1_1hot_l2'length; + +constant qw_offset : natural :=qw_dminus1_offset + qw_dminus1_l2'length; +constant back_inv_val_offset : natural :=qw_offset + qw_l2'length; +constant dbell_val_offset : natural :=back_inv_val_offset + 1; +constant anac_ld_pop_offset : natural :=dbell_val_offset + 1; +constant anac_st_pop_offset : natural :=anac_ld_pop_offset + 1; +constant anac_st_pop_thrd_offset : natural :=anac_st_pop_offset + 1; +constant anac_st_gather_offset : natural :=anac_st_pop_thrd_offset + anaclat_st_pop_thrd'length; +constant coreid_offset : natural :=anac_st_gather_offset + 1; +constant stcx_complete_offset : natural :=coreid_offset + anaclat_coreid'length; +constant xu_iu_reld_core_tag_offset : natural :=stcx_complete_offset + xu_iu_stcx_complete'length; +constant xu_iu_reld_data_vld_offset : natural :=xu_iu_reld_core_tag_offset + xu_iu_reld_core_tag_clone'length; +constant xu_iu_reld_data_coming_offset : natural :=xu_iu_reld_data_vld_offset + 1; +constant xu_iu_reld_ditc_offset : natural :=xu_iu_reld_data_coming_offset + 1; +constant lpidr_offset : natural :=xu_iu_reld_ditc_offset + 1; +constant cmd_seq_offset : natural :=lpidr_offset + lpidr_l2'length; +constant cmd_seq_rd_offset : natural :=cmd_seq_offset + cmd_seq_l2'length; +constant ex4_load_l1hit_val_offset : natural :=cmd_seq_rd_offset + cmd_seq_rd_l2'length; +constant ex4_st_val_offset : natural :=ex4_load_l1hit_val_offset + 1; +constant ex5_st_val_offset : natural :=ex4_st_val_offset + 1; +constant ex6_st_val_offset : natural :=ex5_st_val_offset + 1; +constant st_entry0_val_offset : natural :=ex6_st_val_offset + 1; +constant st_entry0_val_clone_offset : natural :=st_entry0_val_offset + 1; +constant ex4_st_entry_offset : natural :=st_entry0_val_clone_offset + 1; +constant s_m_queue0_offset : natural :=ex4_st_entry_offset + ex4_st_entry_l2'length; + + +constant ex4_ld_m_val_offset : natural :=s_m_queue0_offset + s_m_queue0'length; + +constant spare_1_offset : natural :=ex4_ld_m_val_offset + 1; +constant ex4_classid_offset : natural :=spare_1_offset + spare_1_l2'length; +constant ex4_ld_entry_hit_st_offset : natural :=ex4_classid_offset + ex4_classid_l2'length; +constant ex4_drop_ld_req_offset : natural :=ex4_ld_entry_hit_st_offset + 1; + +constant ex4_drop_touch_offset : natural :=ex4_drop_ld_req_offset + 1; +constant lmq_drop_rel_offset : natural :=ex4_drop_touch_offset + 1; + +constant lmq_dvc1_en_offset : natural :=lmq_drop_rel_offset + lmq_drop_rel_l2'length; +constant lmq_dvc2_en_offset : natural :=lmq_dvc1_en_offset + lmq_dvc1_en_l2'length; +constant l_m_queue_offset : natural :=lmq_dvc2_en_offset + lmq_dvc2_en_l2'length; +-- scan 1 +constant l_m_queue_addrlo_offset : natural :=l_m_queue_offset + lmq_entries * l_m_queue(0)'length; +constant ex4_ld_recov_offset : natural :=l_m_queue_addrlo_offset + lmq_entries * l_m_queue_addrlo(0)'length; +constant ex4_ld_recov_val_offset : natural :=ex4_ld_recov_offset + ex4_ld_entry_l2'length; +constant ex5_ld_recov_offset : natural :=ex4_ld_recov_val_offset + 1; +constant ex6_ld_recov_offset : natural :=ex5_ld_recov_offset + ex5_ld_recov_l2'length; +constant ex7_ld_recov_offset : natural :=ex6_ld_recov_offset + ex6_ld_recov_l2'length; +constant ex5_ld_recov_extra_offset : natural :=ex7_ld_recov_offset + ex7_ld_recov_l2'length; +constant ex6_ld_recov_extra_offset : natural :=ex5_ld_recov_extra_offset + ex5_ld_recov_extra_l2'length; +constant ex7_ld_recov_extra_offset : natural :=ex6_ld_recov_extra_offset + ex6_ld_recov_extra_l2'length; +constant ex8_ld_recov_extra_offset : natural :=ex7_ld_recov_extra_offset + ex7_ld_recov_extra_l2'length; +constant ex5_ld_recov_val_offset : natural :=ex8_ld_recov_extra_offset + ex8_ld_recov_extra_l2'length; +constant ex6_ld_recov_val_offset : natural :=ex5_ld_recov_val_offset + 1; +constant ex7_ld_recov_val_offset : natural :=ex6_ld_recov_val_offset + 1; +constant st_hit_recov_ld_offset : natural :=ex7_ld_recov_val_offset + 1; +constant l_m_fnd_offset : natural :=st_hit_recov_ld_offset + 1; +constant ex4_lmq_cpy_offset : natural :=l_m_fnd_offset + 1; +constant ex5_lmq_cpy_offset : natural :=ex4_lmq_cpy_offset + ex4_lmq_cpy_l2'length; +constant lm_dep_hit_offset : natural :=ex5_lmq_cpy_offset + ex5_lmq_cpy_l2'length; +constant lmq_back_invalidated_offset : natural :=lm_dep_hit_offset + 1; +constant ld_entry_val_offset : natural :=lmq_back_invalidated_offset + lmq_back_invalidated_l2'length; +constant ld_rel_val_offset : natural :=ld_entry_val_offset + ld_entry_val_l2'length; +constant l_m_q_hit_st_offset : natural :=ld_rel_val_offset + ld_rel_val_l2'length; +constant ifetch_req_offset : natural :=l_m_q_hit_st_offset + l_m_q_hit_st_l2'length; +constant ifetch_ra_offset : natural :=ifetch_req_offset + 1; +constant ifetch_wimge_offset : natural :=ifetch_ra_offset + ifetch_ra_l2'length; +constant ifetch_thread_offset : natural :=ifetch_wimge_offset + ifetch_wimge_l2'length; +constant ifetch_userdef_offset : natural :=ifetch_thread_offset + ifetch_thread_l2'length; +constant iu_seq_offset : natural :=ifetch_userdef_offset + ifetch_userdef_l2'length; +constant iu_seq_rd_offset : natural :=iu_seq_offset + iu_seq_l2'length; +constant i_f_q0_val_offset : natural :=iu_seq_rd_offset + iu_seq_rd_l2'length; +constant i_f_q0_offset : natural :=i_f_q0_val_offset + 1; +constant i_f_q1_val_offset : natural :=i_f_q0_offset + i_f_q0_l2'length; +constant i_f_q1_offset : natural :=i_f_q1_val_offset + 1; +constant i_f_q2_val_offset : natural :=i_f_q1_offset + i_f_q1_l2'length; +constant i_f_q2_offset : natural :=i_f_q2_val_offset + 1; +constant i_f_q3_val_offset : natural :=i_f_q2_offset + i_f_q2_l2'length; +constant i_f_q3_offset : natural :=i_f_q3_val_offset + 1; +constant mm_req_val_offset : natural :=i_f_q3_offset + i_f_q3_l2'length; +constant mmu_q_val_offset : natural :=mm_req_val_offset + 1; +constant mmu_q_entry_offset : natural :=mmu_q_val_offset + 1; +constant cred_overrun_offset : natural :=mmu_q_entry_offset + mmu_q_entry_l2'length; +constant reld_ditc_pop_offset : natural :=cred_overrun_offset + 1; +constant bx_ib_empty_offset : natural :=reld_ditc_pop_offset + ac_an_reld_ditc_pop_q'length; +constant send_if_req_offset : natural :=bx_ib_empty_offset + bx_ib_empty_q'length; +constant send_ld_req_offset : natural :=send_if_req_offset + 1; +constant send_mm_req_offset : natural :=send_ld_req_offset + 1; +constant l_m_rel_hit_beat0_offset : natural :=send_mm_req_offset + 1; +constant l_m_rel_hit_beat1_offset : natural :=l_m_rel_hit_beat0_offset + l_m_rel_hit_beat0_l2'length; +constant l_m_rel_hit_beat2_offset : natural :=l_m_rel_hit_beat1_offset + l_m_rel_hit_beat1_l2'length; +constant l_m_rel_hit_beat3_offset : natural :=l_m_rel_hit_beat2_offset + l_m_rel_hit_beat2_l2'length; +constant l_m_rel_hit_beat4_offset : natural :=l_m_rel_hit_beat3_offset + l_m_rel_hit_beat3_l2'length; +constant l_m_rel_hit_beat5_offset : natural :=l_m_rel_hit_beat4_offset + l_m_rel_hit_beat4_l2'length; +constant l_m_rel_hit_beat6_offset : natural :=l_m_rel_hit_beat5_offset + l_m_rel_hit_beat5_l2'length; +constant l_m_rel_hit_beat7_offset : natural :=l_m_rel_hit_beat6_offset + l_m_rel_hit_beat6_l2'length; +constant l_m_rel_inprog_offset : natural :=l_m_rel_hit_beat7_offset + l_m_rel_hit_beat7_l2'length; +constant l_m_rel_c_i_beat0_offset : natural :=l_m_rel_inprog_offset + l_m_rel_inprog_l2'length; +constant l_m_rel_c_i_val_offset : natural :=l_m_rel_c_i_beat0_offset + l_m_rel_c_i_beat0_l2'length; +constant rel_addr_offset : natural :=l_m_rel_c_i_val_offset + l_m_rel_val_c_i_dly'length; +constant rel_size_offset : natural :=rel_addr_offset + rel_addr_l2'length; +constant rel_cache_inh_offset : natural :=rel_size_offset + rel_size_l2'length; +constant rel_rot_sel_offset : natural :=rel_cache_inh_offset + 1; +constant rel_th_id_offset : natural :=rel_rot_sel_offset + rel_rot_sel_l2'length; +constant rel_tar_gpr_offset : natural :=rel_th_id_offset + rel_th_id_l2'length; +constant rel_vpr_val_offset : natural :=rel_tar_gpr_offset + rel_tar_gpr_l2'length; +constant rel_le_mode_offset : natural :=rel_vpr_val_offset + 1; +constant rel_dcbt_offset : natural :=rel_le_mode_offset + 1; +constant rel_algebraic_offset : natural :=rel_dcbt_offset + 1; +constant rel_l2only_offset : natural :=rel_algebraic_offset + 1; +constant rel_l2only_dly_offset : natural :=rel_l2only_offset + 1; +constant rel_lock_en_offset : natural :=rel_l2only_dly_offset + 1; +constant rel_classid_offset : natural :=rel_lock_en_offset + 1; +constant rel_dvc1_offset : natural :=rel_classid_offset + rel_classid_l2'length; +constant rel_dvc2_offset : natural :=rel_dvc1_offset + 1; +constant rel_watch_en_offset : natural :=rel_dvc2_offset + 1; +constant reld_data_vld_offset : natural :=rel_watch_en_offset + 1; +constant rel_tag_offset : natural :=reld_data_vld_offset + 1; +constant reld_data_vld_dplus1_offset : natural :=rel_tag_offset + rel_tag_l2'length; +constant rel_tag_dplus1_offset : natural :=reld_data_vld_dplus1_offset + 1; +constant data_ecc_err_offset : natural :=rel_tag_dplus1_offset + rel_tag_dplus1_l2'length; +constant data_ecc_ue_offset : natural :=data_ecc_err_offset + data_ecc_err_l2'length; +constant ld_m_rel_done_offset : natural :=data_ecc_ue_offset + data_ecc_ue_l2'length; +constant ldq_retry_offset : natural :=ld_m_rel_done_offset + ld_m_rel_done_l2'length; +constant ld_m_rel_done_dly_offset : natural :=ldq_retry_offset + ldq_retry_l2'length; +constant ld_m_rel_done_dly2_offset : natural :=ld_m_rel_done_dly_offset + ld_m_rel_done_dly_l2'length; +constant blk_ld_for_pe_recov_offset : natural :=ld_m_rel_done_dly2_offset + ld_m_rel_done_dly2_l2'length; +constant ldq_rd_seq_match_offset : natural :=blk_ld_for_pe_recov_offset + 1; +constant ob_pwr_tok_offset : natural :=ldq_rd_seq_match_offset + ldq_rd_seq_match_l2'length; +constant ob_req_val_offset : natural :=ob_pwr_tok_offset + 1; +constant ob_req_val_clone_offset : natural :=ob_req_val_offset + 1; +constant ob_ditc_val_offset : natural :=ob_req_val_clone_offset + 1; +constant ob_ditc_val_clone_offset : natural :=ob_ditc_val_offset + 1; +constant ob_thrd_offset : natural :=ob_ditc_val_clone_offset + 1; +constant ob_qw_offset : natural :=ob_thrd_offset + ob_thrd_l2'length; +constant ob_dest_offset : natural :=ob_qw_offset + ob_qw_l2'length; +constant ob_addr_offset : natural :=ob_dest_offset + ob_dest_l2'length; +constant ob_data_offset : natural :=ob_addr_offset + ob_addr_l2'length; +constant ex5_sel_st_req_offset : natural :=ob_data_offset + ob_data_l2'length; +constant bx_cmd_sent_offset : natural :=ex5_sel_st_req_offset + 1; +constant bx_cmd_stall_offset : natural :=bx_cmd_sent_offset + 1; +constant bx_stall_dly_offset : natural :=bx_cmd_stall_offset + 1; +constant xu_mm_lsu_token_offset : natural :=bx_stall_dly_offset + bx_stall_dly_l2'length; +constant ex4_val_req_offset : natural :=xu_mm_lsu_token_offset + 1; +constant ex4_thrd_id_offset : natural :=ex4_val_req_offset + 1; +constant ex5_thrd_id_offset : natural :=ex4_thrd_id_offset + ex4_thrd_id'length; +constant lmq_collision_t0_offset : natural :=ex5_thrd_id_offset + ex5_thrd_id'length; +constant lmq_collision_t1_offset : natural :=lmq_collision_t0_offset + lmq_collision_t0_l2'length; +constant lmq_collision_t2_offset : natural :=lmq_collision_t1_offset + lmq_collision_t1_l2'length; +constant lmq_collision_t3_offset : natural :=lmq_collision_t2_offset + lmq_collision_t2_l2'length; +constant ldq_barr_active_offset : natural :=lmq_collision_t3_offset + lmq_collision_t3_l2'length; +constant l2req_resend_offset : natural :=ldq_barr_active_offset + ldq_barr_active_l2'length; +constant l2req_recycle_offset : natural :=l2req_resend_offset + 1; +constant l2req_pwr_token_offset : natural :=l2req_recycle_offset + 1; +constant l2req_st_data_ptoken_offset : natural :=l2req_pwr_token_offset + 1; +constant l2req_ttype_offset : natural :=l2req_st_data_ptoken_offset+ 1; +constant l2req_wimg_offset : natural :=l2req_ttype_offset + l2req_ttype'length; +constant l2req_user_offset : natural :=l2req_wimg_offset + l2req_wimg'length; +constant l2req_offset : natural :=l2req_user_offset + l2req_user'length; +constant l2req_ld_core_tag_offset : natural :=l2req_offset + 1; +constant l2req_ra_offset : natural :=l2req_ld_core_tag_offset + l2req_ld_core_tag'length; +constant l2req_st_byte_enbl_offset : natural :=l2req_ra_offset + l2req_ra'length; +constant l2req_thread_offset : natural :=l2req_st_byte_enbl_offset + l2req_st_byte_enbl'length; +constant l2req_endian_offset : natural :=l2req_thread_offset + l2req_thread'length; +constant l2req_ld_xfr_len_offset : natural :=l2req_endian_offset + 1; +constant spare_ctrl_a0_offset : natural :=l2req_ld_xfr_len_offset + l2req_ld_xfr_len'length; +constant spare_ctrl_a1_offset : natural :=spare_ctrl_a0_offset + ac_an_req_spare_ctrl_a0'length; +constant st_recycle_offset : natural :=spare_ctrl_a1_offset + an_ac_req_spare_ctrl_a1'length; +constant st_recycle_v_offset : natural :=st_recycle_offset + st_recycle_l2'length; +constant ex6_load_sent_offset : natural :=st_recycle_v_offset + 1; +constant load_sent_dbglat_offset : natural :=ex6_load_sent_offset + 1; +constant ex6_store_sent_offset : natural :=load_sent_dbglat_offset + 1; +constant ex5_flush_offset : natural :=ex6_store_sent_offset + 1; +constant ex6_flush_offset : natural :=ex5_flush_offset + 1; +constant msr_gs_offset : natural :=ex6_flush_offset + 1; +constant msr_pr_offset : natural :=msr_gs_offset + msr_gs_l2'length; +constant msr_ds_offset : natural :=msr_pr_offset + msr_pr_l2'length; +constant pid0_offset : natural :=msr_ds_offset + msr_ds_l2'length; +constant pid1_offset : natural :=pid0_offset + pid0_l2'length; +constant pid2_offset : natural :=pid1_offset + pid1_l2'length; +constant pid3_offset : natural :=pid2_offset + pid2_l2'length; +constant stq_icswx_extra_data_offset : natural :=pid3_offset + pid3_l2'length; +constant ex4_p_addr_59_offset : natural :=stq_icswx_extra_data_offset + stq_icswx_extra_data_l2'length; +constant ex5_st_data_offset : natural :=ex4_p_addr_59_offset + 1; +constant ex6_st_data_offset : natural :=ex5_st_data_offset + ex5_st_data_l2'length; +constant ex4_l2cmdq_flush_offset : natural :=ex6_st_data_offset + ac_an_st_data'length; +constant my_beat_last_offset : natural :=ex4_l2cmdq_flush_offset + ex4_l2cmdq_flush_l2'length; +constant loadmiss_qentry_offset : natural :=my_beat_last_offset + 1; +constant ex5_loadmiss_qentry_offset : natural :=loadmiss_qentry_offset + ex4_loadmiss_qentry'length; +constant ex6_loadmiss_qentry_offset : natural :=ex5_loadmiss_qentry_offset + ex5_loadmiss_qentry'length; +constant ex7_loadmiss_qentry_offset : natural :=ex6_loadmiss_qentry_offset + ex6_loadmiss_qentry'length; +constant ex4_loadmiss_target_offset : natural :=ex7_loadmiss_qentry_offset + ex7_loadmiss_qentry'length; +constant loadmiss_target_offset : natural :=ex4_loadmiss_target_offset + xu_iu_ex5_loadmiss_target'length; +constant ex4_loadmiss_target_type_offset : natural :=loadmiss_target_offset + xu_iu_ex5_loadmiss_target'length; +constant loadmiss_target_type_offset : natural :=ex4_loadmiss_target_type_offset + ex4_loadmiss_target_type'length; +constant ex4_loadmiss_tid_offset : natural :=loadmiss_target_type_offset + xu_iu_ex5_loadmiss_target_type'length; +constant loadmiss_tid_offset : natural :=ex4_loadmiss_tid_offset + ex4_loadmiss_tid'length; +constant ldm_comp_qentry_offset : natural :=loadmiss_tid_offset + xu_iu_ex5_loadmiss_tid'length; +constant complete_qentry_offset : natural :=ldm_comp_qentry_offset + ldm_comp_qentry_l2'length; +constant complete_tid_offset : natural :=complete_qentry_offset + xu_iu_complete_qentry'length; +constant complete_target_type_offset : natural :=complete_tid_offset + xu_iu_complete_tid'length; +constant larx_done_tid_offset : natural :=complete_target_type_offset + xu_iu_complete_target_type'length; +constant update_gpr_offset : natural :=larx_done_tid_offset + xu_iu_larx_done_tid'length; +constant rel_beat_crit_qw_offset : natural :=update_gpr_offset + 1; +constant rel_beat_crit_qw_block_offset : natural :=rel_beat_crit_qw_offset + 1; +constant gpr_updated_prev_offset : natural :=rel_beat_crit_qw_block_offset + 1; +constant gpr_updated_dly1_offset : natural :=gpr_updated_prev_offset + gpr_updated_prev_l2'length; +constant gpr_updated_dly2_offset : natural :=gpr_updated_dly1_offset + gpr_updated_dly1_l2'length; +constant gpr_ecc_err_offset : natural :=gpr_updated_dly2_offset + gpr_updated_dly2_l2'length; +constant spare_4_offset : natural :=gpr_ecc_err_offset + gpr_ecc_err_l2'length; +constant rel_A_data_offset : natural :=spare_4_offset + spare_4_l2'length; +constant rel_B_data_offset : natural :=rel_A_data_offset + rel_A_data_l2'length; +constant send_rel_A_data_offset : natural :=rel_B_data_offset + rel_B_data_l2'length * a2mode; +constant ldq_barr_done_offset : natural :=send_rel_A_data_offset + 1 * a2mode; +constant sync_done_tid_offset : natural :=ldq_barr_done_offset + ldq_barr_done'length; +constant lmq_stq_empty_offset : natural :=sync_done_tid_offset + sync_done_tid'length; +constant quiesce_offset : natural :=lmq_stq_empty_offset + 1; +constant err_l2intrf_ecc_offset : natural :=quiesce_offset + lsu_xu_quiesce'length; +constant err_l2intrf_ue_offset : natural :=err_l2intrf_ecc_offset + 1; +constant err_invld_reld_offset : natural :=err_l2intrf_ue_offset + 1; +constant ex4_ld_queue_full_offset : natural :=err_invld_reld_offset + 1; +constant ex5_ld_queue_full_offset : natural :=ex4_ld_queue_full_offset + 1; +constant ex4_st_queue_full_offset : natural :=ex5_ld_queue_full_offset + 1; +constant ex5_st_queue_full_offset : natural :=ex4_st_queue_full_offset + 1; +constant ex5_ldhld_sthld_coll_offset : natural :=ex5_st_queue_full_offset + 1; +constant ex4_i1_g1_coll_offset : natural :=ex5_ldhld_sthld_coll_offset + 1; +constant ex5_i1_g1_coll_offset : natural :=ex4_i1_g1_coll_offset + 1; +constant ld_miss_latency_offset : natural :=ex5_i1_g1_coll_offset + 1; +constant lsu_perf_events_offset : natural :=ld_miss_latency_offset + 1; +constant dbg_offset : natural :=lsu_perf_events_offset + lsu_perf_events_l2'length; +constant scan_right : natural :=dbg_offset + dbg_l2'length; + +signal siv : std_ulogic_vector(0 to scan_right-1); +signal sov : std_ulogic_vector(0 to scan_right-1); + + +constant load_cmd_count_offset : natural :=0; +constant store_cmd_count_offset : natural :=load_cmd_count_offset + load_cmd_count_l2'length; +constant bcfg_scan_right : natural :=store_cmd_count_offset + store_cmd_count_l2'length; + +signal bcfg_siv : std_ulogic_vector(0 to bcfg_scan_right-1); +signal bcfg_sov : std_ulogic_vector(0 to bcfg_scan_right-1); + + +-- Get rid of sinkless net messages +signal unused_signals : std_ulogic; + +begin + +unused_signals <= or_reduce(unused & ex4_ld_recov_entry(48) & ex7_ld_recov_l2(22 to 26) & l_miss_entry(0) & l_miss_entry(13 to 17) & l_miss_entry(22 to 38) & l_miss_entry(47 to 52) & ld_st_request(38) & anaclat_data_coming & anaclat_reld_crit_qw & anaclat_tag(0)); + +ex3_p_addr <= cmp_ex3_p_addr_o & ex3_p_addr_lwr; + +--************************************************************************************************* +-- Load/Store Queue logic act: power up ldq logic when there is a valid lsu op in ex3 and leave +-- it on until the ldq is empty. Same for stq except use ex4 store to power up. +--************************************************************************************************* + +ldq_active_d <= ex3_stg_act or pe_recov_ld_val_l2 or + (ldq_active_l2 and not lmq_empty); + +latch_clkg_ctl_override : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(clkg_ctl_override_offset to clkg_ctl_override_offset), + scout => sov(clkg_ctl_override_offset to clkg_ctl_override_offset), + din(0) => spr_xucr0_clkg_ctl_b3, + dout(0) => clkg_ctl_override_q); +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +latch_ldq_active : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ldq_active_offset to ldq_active_offset), + scout => sov(ldq_active_offset to ldq_active_offset), + din(0) => ldq_active_d, + dout(0) => ldq_active_l2); + +ldq_active_dly_d <= ldq_active_l2; + +latch_ldq_active_dly : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ldq_active_dly_offset to ldq_active_dly_offset), + scout => sov(ldq_active_dly_offset to ldq_active_dly_offset), + din(0) => ldq_active_dly_d, + dout(0) => ldq_active_dly_l2); + +ldq_act <= ex3_stg_act or pe_recov_ld_val_l2 or ldq_active_l2 or ldq_active_dly_l2 or clkg_ctl_override_q; +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +stq_active_d <= ex4_st_val_l2 or (l2req_recycle_l2 and ex7_ld_par_err) or + (stq_active_l2 and st_entry0_val_l2); + +latch_stq_active : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => stq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(stq_active_offset to stq_active_offset), + scout => sov(stq_active_offset to stq_active_offset), + din(0) => stq_active_d, + dout(0) => stq_active_l2); + +stq_act <= ex4_st_val_l2 or stq_active_l2 or (l2req_recycle_l2 and ex7_ld_par_err) or st_recycle_act or clkg_ctl_override_q; + + +--****************************************************** +-- Inputs +--****************************************************** + +-- new user defined attribute bit -> Bypass L1 if a loadmiss +c_inh <= ex3_cache_inh or ex3_byp_l1; + +dcbt_instr <= ex3_dcbt_instr or ex3_dcbtst_instr or ex3_dcbtls_instr or ex3_dcbtstls_instr; -- these touch instructions don't load a GPR + +touch_instr <= ex3_dcbt_instr or ex3_dcbtst_instr or ex3_dcbtls_instr or ex3_dcbtstls_instr or -- these touch instructions don't load a GPR + ex3_icbt_instr or ex3_icbtls_instr; + +l2only_instr <= (dcbt_instr and ex3_th_fld_l2) or ex3_icbt_instr or ex3_icbtls_instr; + +latch_ex7_ld_par_err : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex7_ld_par_err_offset to ex7_ld_par_err_offset), + scout => sov(ex7_ld_par_err_offset to ex7_ld_par_err_offset), + din(0) => ex6_ld_par_err, + dout(0) => ex7_ld_par_err); + +latch_ex8_ld_par_err : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex8_ld_par_err_offset to ex8_ld_par_err_offset), + scout => sov(ex8_ld_par_err_offset to ex8_ld_par_err_offset), + din(0) => ex7_ld_par_err, + dout(0) => ex8_ld_par_err_l2); + +latch_my_ex4_flush : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(my_ex4_flush_offset to my_ex4_flush_offset), + scout => sov(my_ex4_flush_offset to my_ex4_flush_offset), + din(0) => ex3_flush_all, + dout(0) => my_ex4_flush_l2); + + +-- track parity error recovery state + +pe_recov_empty_d <= lmq_empty and pe_recov_state_l2; + +latch_pe_recov_empty : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(pe_recov_empty_offset to pe_recov_empty_offset), + scout => sov(pe_recov_empty_offset to pe_recov_empty_offset), + din(0) => pe_recov_empty_d, + dout(0) => pe_recov_empty_l2); + +pe_recov_state_d <= ex7_ld_par_err or + (pe_recov_state_l2 and not (pe_recov_ld_num_l2(3) and lmq_empty and pe_recov_empty_l2 and not pe_recov_ld_val_l2)); + +latch_pe_recov_state : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(pe_recov_state_offset to pe_recov_state_offset), + scout => sov(pe_recov_state_offset to pe_recov_state_offset), + din(0) => pe_recov_state_d, + dout(0) => pe_recov_state_l2); + +latch_pe_recov_state_dly : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(pe_recov_state_dly_offset to pe_recov_state_dly_offset), + scout => sov(pe_recov_state_dly_offset to pe_recov_state_dly_offset), + din(0) => pe_recov_state_l2, + dout(0) => pe_recov_state_dly_l2); + +lmq_pe_recov_state <= pe_recov_state_l2; + +pe_recov_ld_num_d(1) <= (pe_recov_state_l2 and lmq_empty and pe_recov_empty_l2 and (pe_recov_ld_num_l2="000")) or + (pe_recov_ld_num_l2(1) and not (lmq_empty and pe_recov_empty_l2)); +pe_recov_ld_num_d(2) <= (pe_recov_ld_num_l2(1) and lmq_empty and pe_recov_empty_l2) or + (pe_recov_ld_num_l2(2) and not (lmq_empty and pe_recov_empty_l2 and not pe_recov_ld_val_l2)); +pe_recov_ld_num_d(3) <= (pe_recov_ld_num_l2(2) and lmq_empty and pe_recov_empty_l2 and not pe_recov_ld_val_l2) or + (pe_recov_ld_num_l2(3) and not (lmq_empty and pe_recov_empty_l2 and not pe_recov_ld_val_l2)); + +pe_act <= pe_recov_state_l2 or clkg_ctl_override_q; + +latch_pe_recov_ld_num : tri_rlmreg_p + generic map (width => pe_recov_ld_num_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => pe_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(pe_recov_ld_num_offset to pe_recov_ld_num_offset + pe_recov_ld_num_l2'length-1), + scout => sov(pe_recov_ld_num_offset to pe_recov_ld_num_offset + pe_recov_ld_num_l2'length-1), + din => pe_recov_ld_num_d(1 to 3), + dout => pe_recov_ld_num_l2(1 to 3)); + +pe_recov_stall <= (ex7_ld_par_err or pe_recov_state_l2) and not (lmq_empty and pe_recov_empty_l2); + + +pe_recov_ld_val_d <= pe_recov_state_l2 and lmq_empty and not ld_m_val and + (ex7_ld_recov_val_l2 or (ex6_ld_recov_val_l2 and not pe_recov_stall)); + +latch_pe_recov_ld_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(pe_recov_ld_val_offset to pe_recov_ld_val_offset), + scout => sov(pe_recov_ld_val_offset to pe_recov_ld_val_offset), + din(0) => pe_recov_ld_val_d, + dout(0) => pe_recov_ld_val_l2); + + +recov_ignr_flush_d <= or_reduce(pe_recov_ld_num_l2); + + + + +ex3_flush_all <= ex3_stg_flush or I1_G1_flush; + +ex4_flush_load <= (ex7_ld_par_err or ex8_ld_par_err_l2 or ex4_drop_ld_req or l_m_fnd_stg or my_ex4_flush_l2) and not recov_ignr_flush_d; + +ex4_flush_load_wo_drop <= ex7_ld_par_err or l_m_fnd_stg or my_ex4_flush_l2 or + (ex4_drop_touch and ex4_ld_recov(38)); +ex4_flush_store <= (ex7_ld_par_err or ex8_ld_par_err_l2 or l_m_fnd_stg or (ex4_load_l1hit_val and not ex4_drop_ld_req) or my_ex4_flush_l2) or + ((ex4_st_entry_l2(0 to 4) = "10010") and ex4_drop_ld_req); -- icblc/dcblc and drop due to I=1 + +ex5_flush_load_all <= my_ex5_flush and not recov_ignr_flush_d; +ex5_flush_load_local <= ex5_flush_l2 and not recov_ignr_flush_d; + +my_xucr0_d <= xu_lsu_spr_xucr0_rel & xu_lsu_spr_xucr0_l2siw & xu_lsu_spr_xucr0_cred & + xu_lsu_spr_xucr0_mbar_ack & xu_lsu_spr_xucr0_tlbsync & xu_lsu_spr_xucr0_cls; + +latch_my_xucr0 : tri_rlmreg_p + generic map (width => my_xucr0_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(my_xucr0_offset to my_xucr0_offset + my_xucr0_l2'length-1), + scout => sov(my_xucr0_offset to my_xucr0_offset + my_xucr0_l2'length-1), + din => my_xucr0_d, + dout => my_xucr0_l2); + +my_xucr0_rel <= my_xucr0_l2(0); +my_xucr0_l2siw <= my_xucr0_l2(1); +my_xucr0_cred <= my_xucr0_l2(2); +my_xucr0_mbar_ack <= my_xucr0_l2(3); +my_xucr0_tlbsync <= my_xucr0_l2(4); +my_xucr0_cls <= my_xucr0_l2(5); + +--****************************************************** +-- Latch the L2 interface Inputs +--****************************************************** + + +latch_anac_data_coming : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(anac_data_coming_offset to anac_data_coming_offset), + scout => sov(anac_data_coming_offset to anac_data_coming_offset), + din(0) => an_ac_reld_data_coming, + dout(0) => anaclat_data_coming); + +latch_anac_reld_crit_qw : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(anac_reld_crit_qw_offset to anac_reld_crit_qw_offset), + scout => sov(anac_reld_crit_qw_offset to anac_reld_crit_qw_offset), + din(0) => an_ac_reld_crit_qw, + dout(0) => anaclat_reld_crit_qw); + +latch_anac_ditc : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(anac_ditc_offset to anac_ditc_offset), + scout => sov(anac_ditc_offset to anac_ditc_offset), + din(0) => an_ac_reld_ditc, + dout(0) => anaclat_ditc); + +latch_anac_data_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(anac_data_val_offset to anac_data_val_offset), + scout => sov(anac_data_val_offset to anac_data_val_offset), + din(0) => an_ac_reld_data_val, + dout(0) => anaclat_data_val); + +ldqretry: process (ldq_retry_l2, retry_started_l2) + variable b: std_ulogic; +begin + b := '0'; + for i in 0 to lmq_entries-1 loop + b := (ldq_retry_l2(i) and not retry_started_l2(i)) or b; + end loop; + ldq_retry_or <= b; +end process; + +data_val_for_rel <= anaclat_data_val and not anaclat_ditc; +data_val_dminus2 <= data_val_for_rel or ldq_retry_or; +data_val_for_drel <= anaclat_data_val and not (anaclat_ditc or anaclat_tag(1)); +data_val_for_recirc <= ldq_retry_or and not data_val_for_drel; + +latch_data_val_dminus1 : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(data_val_dminus1_offset to data_val_dminus1_offset), + scout => sov(data_val_dminus1_offset to data_val_dminus1_offset), + din(0) => data_val_dminus2, + dout(0) => data_val_dminus1_l2); + +latch_ldq_rel_retry_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ldq_rel_retry_val_offset to ldq_rel_retry_val_offset), + scout => sov(ldq_rel_retry_val_offset to ldq_rel_retry_val_offset), + din(0) => data_val_for_recirc, + dout(0) => ldq_rel_retry_val_l2); + +latch_ldq_rel_retry_val_dly : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ldq_rel_retry_val_dly_offset to ldq_rel_retry_val_dly_offset), + scout => sov(ldq_rel_retry_val_dly_offset to ldq_rel_retry_val_dly_offset), + din(0) => ldq_rel_retry_val_l2, + dout(0) => ldq_rel_retry_val_dly_l2); + +latch_rel_intf_v_dminus1 : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(rel_intf_v_dminus1_offset to rel_intf_v_dminus1_offset), + scout => sov(rel_intf_v_dminus1_offset to rel_intf_v_dminus1_offset), + din(0) => anaclat_data_val, + dout(0) => rel_intf_v_dminus1_l2); +latch_rel_intf_v : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(rel_intf_v_offset to rel_intf_v_offset), + scout => sov(rel_intf_v_offset to rel_intf_v_offset), + din(0) => rel_intf_v_dminus1_l2, + dout(0) => rel_intf_v_l2); +latch_rel_intf_v_dplus1 : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(rel_intf_v_dplus1_offset to rel_intf_v_dplus1_offset), + scout => sov(rel_intf_v_dplus1_offset to rel_intf_v_dplus1_offset), + din(0) => rel_intf_v_l2, + dout(0) => rel_intf_v_dplus1_l2); + +latch_anac_tag : tri_rlmreg_p + generic map (width => anaclat_tag'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(anac_tag_offset to anac_tag_offset + anaclat_tag'length-1), + scout => sov(anac_tag_offset to anac_tag_offset + anaclat_tag'length-1), + din => an_ac_reld_core_tag, + dout => anaclat_tag); + +ldq_retry_tag(1) <= '0'; + +ldq_retry_tag4: if lmq_entries=4 generate begin + ldq_retry_tag(2 to 4) <= "000" when ldq_retry_ready(0)='1' else + "001" when ldq_retry_ready(1)='1' else + "010" when ldq_retry_ready(2)='1' else + "011"; -- when ldq_retry_ready(3)='1' +end generate; + +ldq_retry_tag8: if lmq_entries=8 generate begin + ldq_retry_tag(2 to 4) <= "000" when ldq_retry_ready(0)='1' else + "001" when ldq_retry_ready(1)='1' else + "010" when ldq_retry_ready(2)='1' else + "011" when ldq_retry_ready(3)='1' else + "100" when ldq_retry_ready(4)='1' else + "101" when ldq_retry_ready(5)='1' else + "110" when ldq_retry_ready(6)='1' else + "111"; -- when ldq_retry_ready(7)='1' +end generate; + +ldq_retry_ready(0) <= ldq_retry_l2(0) and not retry_started_l2(0); +start_ldq_retry(0) <= ldq_retry_ready(0) and not data_val_for_rel; +retry_started_d(0) <= start_ldq_retry(0) or + (retry_started_l2(0) and not ld_m_rel_done_l2(0)); +start_ldq_retry(1) <= ldq_retry_ready(1) and not data_val_for_rel and not ldq_retry_ready(0); + +retry_started: for i in 1 to lmq_entries-1 generate begin + ldq_retry_ready(i) <= ldq_retry_l2(i) and not retry_started_l2(i); + igt1: if i > 1 generate begin + start_ldq_retry(i) <= ldq_retry_ready(i) and not data_val_for_rel and + not or_reduce(ldq_retry_ready(0 to i-1)); + end generate; + retry_started_d(i) <= start_ldq_retry(i) or + (retry_started_l2(i) and not ld_m_rel_done_l2(i)); +end generate; + +latch_retry_started : tri_rlmreg_p + generic map (width => retry_started_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(retry_started_offset to retry_started_offset + retry_started_l2'length-1), + scout => sov(retry_started_offset to retry_started_offset + retry_started_l2'length-1), + din => retry_started_d(0 to lmq_entries-1), + dout => retry_started_l2(0 to lmq_entries-1)); + +tag_dminus2 <= ldq_retry_tag when (ldq_retry_or and not data_val_for_rel)='1' else + anaclat_tag(1 to 4); + +tag_dminus1_act <= anaclat_data_val or ldq_retry_or or clkg_ctl_override_q; + +tag_dminus1_1hot_n8gen: if lmq_entries /= 8 generate begin + tag_dminus1_1hot_gen : for i in 0 to lmq_entries-1 generate begin + tag_dminus1_1hot_d(i) <= (tag_dminus2(1 to 4) = tconv(i, 4)); + end generate tag_dminus1_1hot_gen; +end generate tag_dminus1_1hot_n8gen; + +tag_dminus1_1hot_8gen: if lmq_entries=8 generate begin + tag_dminus1_1hot_d(0) <= not tag_dminus2(1) and not tag_dminus2(2) and not tag_dminus2(3) and not tag_dminus2(4); + tag_dminus1_1hot_d(1) <= not tag_dminus2(1) and not tag_dminus2(2) and not tag_dminus2(3) and tag_dminus2(4); + tag_dminus1_1hot_d(2) <= not tag_dminus2(1) and not tag_dminus2(2) and tag_dminus2(3) and not tag_dminus2(4); + tag_dminus1_1hot_d(3) <= not tag_dminus2(1) and not tag_dminus2(2) and tag_dminus2(3) and tag_dminus2(4); + tag_dminus1_1hot_d(4) <= not tag_dminus2(1) and tag_dminus2(2) and not tag_dminus2(3) and not tag_dminus2(4); + tag_dminus1_1hot_d(5) <= not tag_dminus2(1) and tag_dminus2(2) and not tag_dminus2(3) and tag_dminus2(4); + tag_dminus1_1hot_d(6) <= not tag_dminus2(1) and tag_dminus2(2) and tag_dminus2(3) and not tag_dminus2(4); + tag_dminus1_1hot_d(7) <= not tag_dminus2(1) and tag_dminus2(2) and tag_dminus2(3) and tag_dminus2(4); +end generate tag_dminus1_1hot_8gen; + + +latch_tag_dminus1 : tri_rlmreg_p + generic map (width => tag_dminus1_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => tag_dminus1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(tag_dminus1_offset to tag_dminus1_offset + tag_dminus1_l2'length-1), + scout => sov(tag_dminus1_offset to tag_dminus1_offset + tag_dminus1_l2'length-1), + din => tag_dminus2, + dout => tag_dminus1_l2); + +latch_tag_dminus1_cpy : tri_rlmreg_p + generic map (width => tag_dminus1_cpy_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => tag_dminus1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(tag_dminus1_cpy_offset to tag_dminus1_cpy_offset + tag_dminus1_cpy_l2'length-1), + scout => sov(tag_dminus1_cpy_offset to tag_dminus1_cpy_offset + tag_dminus1_cpy_l2'length-1), + din => tag_dminus2(2 to 4), + dout => tag_dminus1_cpy_l2); +latch_tag_dminus1_1hot : tri_rlmreg_p + generic map (width => tag_dminus1_1hot_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => tag_dminus1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(tag_dminus1_1hot_offset to tag_dminus1_1hot_offset + tag_dminus1_1hot_l2'length-1), + scout => sov(tag_dminus1_1hot_offset to tag_dminus1_1hot_offset + tag_dminus1_1hot_l2'length-1), + din => tag_dminus1_1hot_d, + dout => tag_dminus1_1hot_l2); + +latch_anac_qw : tri_rlmreg_p + generic map (width => anaclat_qw'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(anac_qw_offset to anac_qw_offset + anaclat_qw'length-1), + scout => sov(anac_qw_offset to anac_qw_offset + anaclat_qw'length-1), + din => an_ac_reld_qw, + dout => anaclat_qw); + +latch_qw_dminus1 : tri_rlmreg_p + generic map (width => qw_dminus1_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => tag_dminus1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(qw_dminus1_offset to qw_dminus1_offset + qw_dminus1_l2'length-1), + scout => sov(qw_dminus1_offset to qw_dminus1_offset + qw_dminus1_l2'length-1), + din => anaclat_qw, + dout => qw_dminus1_l2); + +dminus1_act <= data_val_dminus1_l2 or clkg_ctl_override_q; + +latch_qw : tri_rlmreg_p + generic map (width => qw_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dminus1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(qw_offset to qw_offset + qw_l2'length-1), + scout => sov(qw_offset to qw_offset + qw_l2'length-1), + din => qw_dminus1_l2, + dout => qw_l2); + +rel_data_act <= rel_intf_v_dminus1_l2 or clkg_ctl_override_q; + +latch_anac_data : tri_rlmreg_p + generic map (width => anaclat_data'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => rel_data_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(anac_data_offset to anac_data_offset + anaclat_data'length-1), + scout => sov(anac_data_offset to anac_data_offset + anaclat_data'length-1), + din => an_ac_reld_data, + dout => anaclat_data); + +latch_anac_ecc_err : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(anac_ecc_err_offset to anac_ecc_err_offset), + scout => sov(anac_ecc_err_offset to anac_ecc_err_offset), + din(0) => an_ac_reld_ecc_err, + dout(0) => anaclat_ecc_err); + +latch_anac_ecc_err_ue : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(anac_ecc_err_ue_offset to anac_ecc_err_ue_offset), + scout => sov(anac_ecc_err_ue_offset to anac_ecc_err_ue_offset), + din(0) => an_ac_reld_ecc_err_ue, + dout(0) => anaclat_ecc_err_ue); + + +beat_ecc_err <= anaclat_ecc_err and rel_intf_v_dplus1_l2; + +ue_mchk_v <= (rel_addr_l2(58) = qw_l2(58)) and reld_data_vld_l2 and not ldq_rel_retry_val_dly_l2 and not rel_tag_l2(1) and + ((rel_addr_l2(57) = qw_l2(57)) or not my_xucr0_cls); + +ue_mchk_valid_d(0 to 3) <= gate_and(ue_mchk_v, rel_th_id_l2(0 to 3)); + +l2_data_ecc_err_ue <= gate_and((anaclat_ecc_err_ue and rel_intf_v_dplus1_l2), ue_mchk_valid_l2(0 to 3)); + +latch_ue_mchk_val : tri_rlmreg_p + generic map (width => ue_mchk_valid_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ue_mchk_val_offset to ue_mchk_val_offset + ue_mchk_valid_l2'length-1), + scout => sov(ue_mchk_val_offset to ue_mchk_val_offset + ue_mchk_valid_l2'length-1), + din => ue_mchk_valid_d, + dout => ue_mchk_valid_l2); + +latch_anac_l1_dump : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(anac_l1_dump_offset to anac_l1_dump_offset), + scout => sov(anac_l1_dump_offset to anac_l1_dump_offset), + din(0) => an_ac_reld_l1_dump, + dout(0) => anaclat_l1_dump); +latch_dminus1_l1_dump : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => tag_dminus1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(dminus1_l1_dump_offset to dminus1_l1_dump_offset), + scout => sov(dminus1_l1_dump_offset to dminus1_l1_dump_offset), + din(0) => anaclat_l1_dump, + dout(0) => dminus1_l1_dump); + +dminus1_l1_dump_gated <= dminus1_l1_dump and rel_intf_v_dminus1_l2; + +latch_l1_dump : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dminus1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(l1_dump_offset to l1_dump_offset), + scout => sov(l1_dump_offset to l1_dump_offset), + din(0) => dminus1_l1_dump_gated, + dout(0) => l1_dump); + +latch_anac_back_inv : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(anac_back_inv_offset to anac_back_inv_offset), + scout => sov(anac_back_inv_offset to anac_back_inv_offset), + din(0) => an_ac_back_inv, + dout(0) => anaclat_back_inv); + +bi_act <= anaclat_back_inv or clkg_ctl_override_q; + +latch_anac_back_inv_addr : tri_rlmreg_p + generic map (width => anaclat_back_inv_addr'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => bi_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(anac_back_inv_addr_offset to anac_back_inv_addr_offset + anaclat_back_inv_addr'length-1), + scout => sov(anac_back_inv_addr_offset to anac_back_inv_addr_offset + anaclat_back_inv_addr'length-1), + din => an_ac_back_inv_addr, + dout => anaclat_back_inv_addr); + +latch_anac_back_inv_target1 : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(anac_back_inv_target1_offset to anac_back_inv_target1_offset), + scout => sov(anac_back_inv_target1_offset to anac_back_inv_target1_offset), + din(0) => an_ac_back_inv_target_bit1, + dout(0) => anaclat_back_inv_target_1); + +latch_anac_back_inv_target4 : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(anac_back_inv_target4_offset to anac_back_inv_target4_offset), + scout => sov(anac_back_inv_target4_offset to anac_back_inv_target4_offset), + din(0) => an_ac_back_inv_target_bit4, + dout(0) => anaclat_back_inv_target_4); + +back_inv_val_d <= anaclat_back_inv and anaclat_back_inv_target_1; +dbell_val_d <= anaclat_back_inv and anaclat_back_inv_target_4; + +latch_back_inv_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(back_inv_val_offset to back_inv_val_offset), + scout => sov(back_inv_val_offset to back_inv_val_offset), + din(0) => back_inv_val_d, + dout(0) => back_inv_val_l2); + +latch_dbell_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(dbell_val_offset to dbell_val_offset), + scout => sov(dbell_val_offset to dbell_val_offset), + din(0) => dbell_val_d, + dout(0) => dbell_val_l2); + +latch_anac_ld_pop : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(anac_ld_pop_offset to anac_ld_pop_offset), + scout => sov(anac_ld_pop_offset to anac_ld_pop_offset), + din(0) => an_ac_req_ld_pop, + dout(0) => anaclat_ld_pop); +latch_anac_st_pop : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(anac_st_pop_offset to anac_st_pop_offset), + scout => sov(anac_st_pop_offset to anac_st_pop_offset), + din(0) => an_ac_req_st_pop, + dout(0) => anaclat_st_pop); +latch_anac_st_pop_thrd : tri_rlmreg_p + generic map (width => anaclat_st_pop_thrd'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(anac_st_pop_thrd_offset to anac_st_pop_thrd_offset + anaclat_st_pop_thrd'length-1), + scout => sov(anac_st_pop_thrd_offset to anac_st_pop_thrd_offset + anaclat_st_pop_thrd'length-1), + din => an_ac_req_st_pop_thrd, + dout => anaclat_st_pop_thrd); +latch_anac_st_gather : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(anac_st_gather_offset to anac_st_gather_offset), + scout => sov(anac_st_gather_offset to anac_st_gather_offset), + din(0) => an_ac_req_st_gather, + dout(0) => anaclat_st_gather); + +latch_coreid : tri_rlmreg_p + generic map (width => anaclat_coreid'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(coreid_offset to coreid_offset + anaclat_coreid'length-1), + scout => sov(coreid_offset to coreid_offset + anaclat_coreid'length-1), + din => an_ac_coreid, + dout => anaclat_coreid); + +latch_stcx_complete : tri_rlmreg_p + generic map (width => xu_iu_stcx_complete'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(stcx_complete_offset to stcx_complete_offset + xu_iu_stcx_complete'length-1), + scout => sov(stcx_complete_offset to stcx_complete_offset + xu_iu_stcx_complete'length-1), + din => an_ac_stcx_complete, + dout => xu_iu_stcx_complete); + +latch_xu_iu_reld_core_tag : tri_rlmreg_p + generic map (width => xu_iu_reld_core_tag_clone'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(xu_iu_reld_core_tag_offset to xu_iu_reld_core_tag_offset + xu_iu_reld_core_tag_clone'length-1), + scout => sov(xu_iu_reld_core_tag_offset to xu_iu_reld_core_tag_offset + xu_iu_reld_core_tag_clone'length-1), + din => an_ac_reld_core_tag(1 to 4), + dout => xu_iu_reld_core_tag_clone); +latch_xu_iu_reld_data_vld : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(xu_iu_reld_data_vld_offset to xu_iu_reld_data_vld_offset), + scout => sov(xu_iu_reld_data_vld_offset to xu_iu_reld_data_vld_offset), + din(0) => an_ac_reld_data_val, + dout(0) => xu_iu_reld_data_vld_clone); +latch_xu_iu_reld_data_coming : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(xu_iu_reld_data_coming_offset to xu_iu_reld_data_coming_offset), + scout => sov(xu_iu_reld_data_coming_offset to xu_iu_reld_data_coming_offset), + din(0) => an_ac_reld_data_coming, + dout(0) => xu_iu_reld_data_coming_clone); +latch_xu_iu_reld_ditc : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(xu_iu_reld_ditc_offset to xu_iu_reld_ditc_offset), + scout => sov(xu_iu_reld_ditc_offset to xu_iu_reld_ditc_offset), + din(0) => an_ac_reld_ditc, + dout(0) => xu_iu_reld_ditc_clone); + + +-- redrive latch outputs to boxes logic + + lsu_reld_data_vld <= anaclat_data_val; + lsu_reld_core_tag <= anaclat_tag(3 to 4); + lsu_reld_qw <= anaclat_qw(58 to 59); + lsu_reld_ditc <= anaclat_ditc; + lsu_reld_data <= anaclat_data; + lsu_req_st_pop <= anaclat_st_pop; + lsu_req_st_pop_thrd <= anaclat_st_pop_thrd; + lsu_reld_ecc_err <= anaclat_ecc_err or anaclat_ecc_err_ue; + +--****************************************************** +-- Send DBell info to xu +--****************************************************** + +latch_lpidr : tri_rlmreg_p + generic map (width => lpidr_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(lpidr_offset to lpidr_offset + lpidr_l2'length-1), + scout => sov(lpidr_offset to lpidr_offset + lpidr_l2'length-1), + din => mm_xu_lsu_lpidr(0 to 7), + dout => lpidr_l2(0 to 7)); + +lsu_xu_dbell_val <= dbell_val_l2; +lsu_xu_dbell_type(0 to 4) <= anaclat_back_inv_addr(32 to 36); +lsu_xu_dbell_brdcast <= anaclat_back_inv_addr(37); +lsu_xu_dbell_lpid_match <= (anaclat_back_inv_addr(42 to 49) = lpidr_l2(0 to 7)) or + (anaclat_back_inv_addr(42 to 49) = x"00"); +lsu_xu_dbell_pirtag(50 to 63) <= anaclat_back_inv_addr(50 to 63); + +--****************************************************** +-- Command Sequence Write +--****************************************************** + +cmd_seq_incr(0 to 4) <= std_ulogic_vector(unsigned(cmd_seq_l2) + 1); +cmd_seq_decr(0 to 4) <= std_ulogic_vector(unsigned(cmd_seq_l2) - 1); + +ctrl_incr_cmdseq <= ld_m_val and not (ex4_flush_load and ex4_ld_m_val); +ctrl_decr_cmdseq <= (not ld_m_val and (ex4_flush_load and ex4_ld_m_val)); +ctrl_hold_cmdseq <= ( ld_m_val and (ex4_flush_load and ex4_ld_m_val)) or + (not ld_m_val and not (ex4_flush_load and ex4_ld_m_val)); + + +cmd_seq_d(0 to 4) <= gate_and(ctrl_incr_cmdseq , cmd_seq_incr(0 to 4)) or + gate_and(ctrl_decr_cmdseq , cmd_seq_decr(0 to 4)) or + gate_and(ctrl_hold_cmdseq , cmd_seq_l2(0 to 4)); + +latch_cmd_seq : tri_rlmreg_p + generic map (width => cmd_seq_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(cmd_seq_offset to cmd_seq_offset + cmd_seq_l2'length-1), + scout => sov(cmd_seq_offset to cmd_seq_offset + cmd_seq_l2'length-1), + din => cmd_seq_d(0 to 4), + dout => cmd_seq_l2(0 to 4)); + +new_ld_cmd_seq(0 to 4) <= cmd_seq_decr(0 to 4) when (ld_m_val and ex4_flush_load and ex4_ld_m_val) = '1' else + cmd_seq_l2(0 to 4); + + +ld_q_seq_wrap <= (cmd_seq_l2 = cmd_seq_rd_l2) and or_reduce(ld_entry_val_l2); + +--****************************************************** +-- Command Sequence Read +--****************************************************** + +cmd_seq_rd_incr(0 to 4) <= std_ulogic_vector(unsigned(cmd_seq_rd_l2) + 1); + +cmd_seq_rd_d(0 to 4) <= cmd_seq_rd_incr(0 to 4) when (load_sent or selected_entry_flushed or rd_seq_num_skip)='1' else + cmd_seq_rd_l2(0 to 4); + +latch_cmd_seq_rd : tri_rlmreg_p + generic map (width => cmd_seq_rd_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(cmd_seq_rd_offset to cmd_seq_rd_offset + cmd_seq_rd_l2'length-1), + scout => sov(cmd_seq_rd_offset to cmd_seq_rd_offset + cmd_seq_rd_l2'length-1), + din => cmd_seq_rd_d(0 to 4), + dout => cmd_seq_rd_l2(0 to 4)); + +--****************************************************** +-- Queue Entry +--****************************************************** + +ex3_new_target_gpr <= ex3_target_gpr or (0 to 8 => touch_instr); + +-- bit(0) = c_inh +-- bit(1:6) = encoded command type(0 to 5) +-- bit(7:12) = opsize(0 to 5) +-- bit(13:17) = rot_sel(0 to 4) +-- bit(18:21) = th_id(0 to 3) +-- bit(22:26) = cmd_seq_l2(0 to 4) +-- bit(27:35) = target_gpr(0 to 8) +-- bit(36) = axu_op_val +-- bit(37) = little endian mode +-- bit(38) = dcbt is valid +-- bit(39:42) = wimg bits +-- bit(43:46) = user defined bits +-- bit(47) = algebraic op +-- bit(48) = L2 only touch (do not write reload data to cache) +-- bit(49) = way lock +-- bit(50:51) = way lock bits table select bit (classid) +-- bit(52) = watch enable +-- bit(53) = litle endian bit (from erat) +-- bit(53:xx) = ex3_p_addr(22 to 63) +ld_queue_entry <= c_inh & cmd_type_ld(0 to 5) & ex3_opsize(0 to 5) & ex3_rot_sel(0 to 4) & + ex3_thrd_id(0 to 3) & new_ld_cmd_seq(0 to 4) & ex3_new_target_gpr(0 to 8) & + ex3_axu_op_val & ex3_le_mode & touch_instr & + ex3_wimge_bits(0 to 3) & ex3_usr_bits(0 to 3) & ex3_algebraic & l2only_instr & + ex3_lock_en & ex3_classid & ex3_watch_en & ex3_wimge_bits(4) when pe_recov_ld_val_l2='0' else + ex7_ld_recov_l2(0 to 21) & new_ld_cmd_seq(0 to 4) & + ex7_ld_recov_l2(27 to 53); + +ld_queue_addrlo <= ex3_p_addr(57 to 63) when pe_recov_ld_val_l2='0' else + ex7_ld_recov_l2((54+real_data_add-6-1) to (54+real_data_add-1)); + +cmp_ld_ex7_recov <= pe_recov_ld_val_l2; + +load_val <= ex3_load_instr and not (ex3_dcbt_instr or ex3_dcbtst_instr or + ex3_dcbtls_instr or ex3_dcbtstls_instr or + ex3_larx_instr or ex3_icbt_instr or ex3_icbtls_instr); + +load_l1hit_val <= ex3_load_l1hit and not ex3_larx_instr; + +latch_ex4_load_l1hit_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_load_l1hit_val_offset to ex4_load_l1hit_val_offset), + scout => sov(ex4_load_l1hit_val_offset to ex4_load_l1hit_val_offset), + din(0) => load_l1hit_val, + dout(0) => ex4_load_l1hit_val); + +dcbf_l_val <= ex3_dcbf_instr and (ex3_l_fld="01"); +dcbf_g_val <= ex3_dcbf_instr and ((ex3_l_fld="00") or (ex3_l_fld="10")); +hwsync_val <= (ex3_sync_instr and ((ex3_l_fld /= "01") or my_xucr0_mbar_ack) ) or + (ex3_mbar_instr and my_xucr0_mbar_ack); +lwsync_val <= ex3_sync_instr and (ex3_l_fld = "01") and not my_xucr0_mbar_ack; +mbar_val <= ex3_mbar_instr and not my_xucr0_mbar_ack; + +dcbt_l2only_val <= ex3_dcbt_instr and ex3_th_fld_l2; +dcbt_l1l2_val <= ex3_dcbt_instr and not ex3_th_fld_l2; +dcbtls_l2only_val <= ex3_dcbtls_instr and ex3_th_fld_l2; +dcbtls_l1l2_val <= ex3_dcbtls_instr and not ex3_th_fld_l2; +dcbtst_l2only_val <= ex3_dcbtst_instr and ex3_th_fld_l2; +dcbtst_l1l2_val <= ex3_dcbtst_instr and not ex3_th_fld_l2; +dcbtstls_l2only_val <= ex3_dcbtstls_instr and ex3_th_fld_l2; +dcbtstls_l1l2_val <= ex3_dcbtstls_instr and not ex3_th_fld_l2; + + +cmd_type_ld(0 to 5) <= gate_and( load_val , "001000") or + gate_and( ex3_larx_instr , ("0010" & ex3_mutex_hint & "1") ) or + gate_and( dcbt_l1l2_val , "001111") or + gate_and( dcbt_l2only_val , "000111") or + gate_and( dcbtls_l1l2_val , "011111") or + gate_and( dcbtls_l2only_val , "010111") or + gate_and( dcbtst_l1l2_val , "001101") or + gate_and( dcbtst_l2only_val , "000101") or + gate_and( dcbtstls_l1l2_val , "011101") or + gate_and( dcbtstls_l2only_val, "010101") or + gate_and( ex3_icbt_instr , "000100") or + gate_and( ex3_icbtls_instr , "010100"); + +cmd_type_st(0 to 5) <= gate_and( ex3_store_instr , "100000") or + gate_and( ex3_stx_instr , "101001") or + gate_and( ex3_icbi_instr , "111110") or + gate_and( dcbf_l_val , "110110") or + gate_and( dcbf_g_val , "110111") or + gate_and( ex3_dcbi_instr , "111111") or + gate_and( ex3_dcbz_instr , "100001") or + gate_and( ex3_dcbst_instr , "110101") or + gate_and( hwsync_val , "101011") or + gate_and( mbar_val , "110010") or + gate_and( lwsync_val , "101010") or + gate_and( ex3_tlbsync_instr , "111010") or + gate_and( ex3_icblc_instr , "100100") or + gate_and( ex3_dcblc_instr , "100101") or + gate_and( ex3_dci_instr , "101111") or + gate_and( ex3_ici_instr , "101110") or + gate_and( ex3_msgsnd_instr , "101101") or + gate_and( ex3_icswx_instr , "100110") or + gate_and( ex3_icswx_dot , "100111") or + gate_and( ex3_mtspr_trace , "101100") or + gate_and( load_l1hit_val , "110100"); + + +ex3_st_entry <= cmd_type_st(0 to 5) & -- bit(0:5) = encoded command type(0 to 5) + ex3_byte_en(0 to 31) & -- bit(6:37) = byte enables(0 to 15) + ex3_thrd_id(0 to 3) & -- bit(38:41) = th_id(0 to 3) + ex3_wimge_bits(4) & -- bit(42) = little endian + ex3_wimge_bits(0 to 3) & -- bit(43:46) = wimg bits + ex3_usr_bits(0 to 3) & -- bit(47:50) = user defined bits + ex3_opsize(0 to 5) & -- bit(51:56) = transfer length + ex3_icswx_epid & -- bit 57 = icswx is for external pid + ex3_p_addr; -- bit(58:xx) = ex3_p_addr(0 to 63) + +ex4_thrd_encode(0) <= ex4_thrd_id(2) or ex4_thrd_id(3); +ex4_thrd_encode(1) <= ex4_thrd_id(1) or ex4_thrd_id(3); + +ex4_st_addr <= ex4_st_entry_l2(58 to (58+real_data_add-1)) when ex4_st_entry_l2(0 to 5)/="101100" else -- /mtspr_trace + (0 to real_data_add-35 => '0') & -- zeros + anaclat_coreid(6 to 7) & -- 30:31 core ID + ex4_thrd_encode(0 to 1) & -- 32:33 thread ID + ex4_st_entry_l2(58+real_data_add-14 to 58+real_data_add-5) & -- 34:43 mark type (from 50:59) + '0' & -- 44 + ex4_st_entry_l2(58+real_data_add-4) & -- 45 mark valid (from 60) + ex4_st_entry_l2(58+real_data_add-1) & -- 46 start trig (from 63) + ex4_st_entry_l2(58+real_data_add-2) & -- 47 stop trig (from 62) + ex4_st_entry_l2(58+real_data_add-3) & -- 48 pause trig (from 61) + "000000000000000"; -- 49:63 + + +s_m_queue0_d <= s_m_queue0 when (st_entry0_val_l2 and (not (store_credit and ex5_sel_st_req) or + st_recycle_V_l2 or + (l2req_recycle_l2 and ex7_ld_par_err)))='1' else + ex4_st_entry_l2(0 to 57) & ex4_st_addr; + +--************************************************************************************************************ +--************************************************************************************************************ +-- STORE QUEUE LOGIC +-- Store Miss Queue Entry - 4 store miss entries +--************************************************************************************************************ +--************************************************************************************************************ + +st_val <= (((ex3_l_s_q_val and not ex3_load_instr) or load_l1hit_val) and -- not ex3_sync_instr and not ex3_eieio_instr and + not flush_if_store and not ex3_stg_flush and not I1_G1_flush); -- or ex3_dci_instr or ex3_ici_instr; + + +thrd_hit_p: process (l_m_queue(0)(18 to 21), l_m_queue(1)(18 to 21), l_m_queue(2)(18 to 21), l_m_queue(3)(18 to 21), l_m_queue(4)(18 to 21), l_m_queue(5)(18 to 21), l_m_queue(6)(18 to 21), l_m_queue(7)(18 to 21), ld_rel_val_l2, ex3_thrd_id, ex3_sync_instr, ex3_mbar_instr, ex3_tlbsync_instr) + variable b0, b1, b2, b3: std_ulogic; +begin + b0 := '0'; + b1 := '0'; + b2 := '0'; + b3 := '0'; + for i in 0 to lmq_entries-1 loop + b0 := (l_m_queue(i)(18) and ld_rel_val_l2(i)) or b0; -- thread 0 and entry is valid + b1 := (l_m_queue(i)(19) and ld_rel_val_l2(i)) or b1; -- thread 1 and entry is valid + b2 := (l_m_queue(i)(20) and ld_rel_val_l2(i)) or b2; -- thread 2 and entry is valid + b3 := (l_m_queue(i)(21) and ld_rel_val_l2(i)) or b3; -- thread 3 and entry is valid + end loop; + sync_flush <= ((ex3_thrd_id(0) and b0) or + (ex3_thrd_id(1) and b1) or + (ex3_thrd_id(2) and b2) or + (ex3_thrd_id(3) and b3)) and + (ex3_sync_instr or ex3_mbar_instr or ex3_tlbsync_instr); +end process; + + + +-- since this eq does not include xu_lsu_ex5_flush, it might be wrong and cause a new store to be flushed (if +-- there is only 1 st credit left) +nxt_st_cred_tkn <= (st_entry0_val_l2 and not (ex5_flush_store and ex5_st_val_l2)) or ob_req_val_l2 or ob_ditc_val_l2 or + (mmu_q_val and not mmu_q_entry_l2(0)); +flush_if_store <= (one_st_cred and nxt_st_cred_tkn and ex4_st_val_l2) or + (not store_credit and (st_entry0_val_l2 or ex4_st_val_l2)) or + (my_xucr0_cred and (st_entry0_val_l2 or ex4_st_val_l2)); + +st_flush <= (not ex3_load_instr and flush_if_store) or sync_flush; + +st_entry0_val_d <= (ex4_st_val_l2 and not ex4_flush_store) or + (st_entry0_val_l2 and not (store_credit and ex5_sel_st_req) and not (my_ex5_flush_store and ex5_st_val_l2 and not ex8_ld_par_err_l2)) or + (((l2req_recycle_l2 and ex7_ld_par_err and not (my_ex5_flush_store and ex5_st_val_l2)) or st_recycle_V_l2) and + st_entry0_val_l2 and not (my_ex5_flush_store and ex5_st_val_l2 and not ex8_ld_par_err_l2)); +ex4_st_val_d <= st_val; + + + +latch_ex4_st_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_st_val_offset to ex4_st_val_offset), + scout => sov(ex4_st_val_offset to ex4_st_val_offset), + din(0) => ex4_st_val_d, + dout(0) => ex4_st_val_l2); + +ex4_st_valid <= ex4_st_val_l2 and not ex4_flush_store; + +latch_ex5_st_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex5_st_val_offset to ex5_st_val_offset), + scout => sov(ex5_st_val_offset to ex5_st_val_offset), + din(0) => ex4_st_valid, + dout(0) => ex5_st_val_l2); + +latch_ex6_st_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex6_st_val_offset to ex6_st_val_offset), + scout => sov(ex6_st_val_offset to ex6_st_val_offset), + din(0) => ex5_st_val_l2, + dout(0) => ex6_st_val_l2); + +latch_s_m_queue0_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(st_entry0_val_offset to st_entry0_val_offset), + scout => sov(st_entry0_val_offset to st_entry0_val_offset), + din(0) => st_entry0_val_d, + dout(0) => st_entry0_val_l2); + +latch_s_m_queue0_val_clone : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(st_entry0_val_clone_offset to st_entry0_val_clone_offset), + scout => sov(st_entry0_val_clone_offset to st_entry0_val_clone_offset), + din(0) => st_entry0_val_d, + dout(0) => st_entry0_val_clone_l2); + +ex4_st_entry_act <= ex3_stg_act or ex3_dci_instr or ex3_ici_instr or clkg_ctl_override_q; + +latch_ex4_st_entry : tri_rlmreg_p + generic map (width => ex4_st_entry_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ex4_st_entry_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_st_entry_offset to ex4_st_entry_offset + ex4_st_entry_l2'length-1), + scout => sov(ex4_st_entry_offset to ex4_st_entry_offset + ex4_st_entry_l2'length-1), + din => ex3_st_entry, + dout => ex4_st_entry_l2); + +latch_s_m_queue0 : tri_rlmreg_p + generic map (width => s_m_queue0'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => stq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(s_m_queue0_offset to s_m_queue0_offset + s_m_queue0'length-1), + scout => sov(s_m_queue0_offset to s_m_queue0_offset + s_m_queue0'length-1), + din => s_m_queue0_d, + dout => s_m_queue0); + + +--************************************************************************************************************ +--************************************************************************************************************ +-- END: STORE QUEUE LOGIC +--************************************************************************************************************ +--************************************************************************************************************ + +--************************************************************************************************************ +--************************************************************************************************************ +-- LOAD QUEUE LOGIC +-- Load Miss Queue Entry - 4 load miss entries +--************************************************************************************************************ +--************************************************************************************************************ +ld_m_val <= (ex3_l_s_q_val and ex3_load_instr and not ld_queue_full and not ld_q_seq_wrap) or + pe_recov_ld_val_l2; + +ld_flush <= ex3_load_instr and (ld_queue_full or ld_q_seq_wrap); +ex4_ld_queue_full <= ld_flush and ex3_l_s_q_val; +ex4_st_queue_full <= st_flush and ex3_l_s_q_val; +ex4_ldhld_sthld_coll <= l_m_fnd_stg and ex4_val_req; +ex3_i1_g1_coll <= I1_G1_flush and ex3_l_s_q_val; + +ld_miss_latency_d <= (ld_entry_val_l2(0) and ex6_loadmiss_qentry(0) and not ex6_flush_l2) or + (ld_miss_latency_l2 and ld_entry_val_l2(0)); + + +lsu_perf_events <= ex5_ld_queue_full_l2 & ex5_st_queue_full_l2 & ex5_ldhld_sthld_coll_l2 & ex5_i1_g1_coll_l2; +lsu_xu_perf_events <= lsu_perf_events_l2 & larx_done_tid_l2 & ld_miss_latency_l2; + + + + + +latch_ex4_ld_m_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_ld_m_val_offset to ex4_ld_m_val_offset), + scout => sov(ex4_ld_m_val_offset to ex4_ld_m_val_offset), + din(0) => ld_m_val, + dout(0) => ex4_ld_m_val); + +ex4_ld_m_val_not_fl <= ex4_ld_m_val and not ex4_flush_load; + + +latch_ex4_drop_ld_req : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_drop_ld_req_offset to ex4_drop_ld_req_offset), + scout => sov(ex4_drop_ld_req_offset to ex4_drop_ld_req_offset), + din(0) => ex3_drop_ld_req, + dout(0) => ex4_drop_ld_req); + +latch_ex4_drop_touch : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_drop_touch_offset to ex4_drop_touch_offset), + scout => sov(ex4_drop_touch_offset to ex4_drop_touch_offset), + din(0) => ex3_drop_touch, + dout(0) => ex4_drop_touch); + + + +latch_ex4_ld_queue_full : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_ld_queue_full_offset to ex4_ld_queue_full_offset), + scout => sov(ex4_ld_queue_full_offset to ex4_ld_queue_full_offset), + din(0) => ex4_ld_queue_full, + dout(0) => ex4_ld_queue_full_l2); + +ex5_ld_queue_full_d <= ex4_ld_queue_full_l2 and not ex4_drop_ld_req; + +latch_ex5_ld_queue_full : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex5_ld_queue_full_offset to ex5_ld_queue_full_offset), + scout => sov(ex5_ld_queue_full_offset to ex5_ld_queue_full_offset), + din(0) => ex5_ld_queue_full_d, + dout(0) => ex5_ld_queue_full_l2); + +latch_ex4_st_queue_full : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_st_queue_full_offset to ex4_st_queue_full_offset), + scout => sov(ex4_st_queue_full_offset to ex4_st_queue_full_offset), + din(0) => ex4_st_queue_full, + dout(0) => ex4_st_queue_full_l2); + +latch_ex5_st_queue_full : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex5_st_queue_full_offset to ex5_st_queue_full_offset), + scout => sov(ex5_st_queue_full_offset to ex5_st_queue_full_offset), + din(0) => ex4_st_queue_full_l2, + dout(0) => ex5_st_queue_full_l2); + +latch_ex5_ldhld_sthld_coll : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex5_ldhld_sthld_coll_offset to ex5_ldhld_sthld_coll_offset), + scout => sov(ex5_ldhld_sthld_coll_offset to ex5_ldhld_sthld_coll_offset), + din(0) => ex4_ldhld_sthld_coll, + dout(0) => ex5_ldhld_sthld_coll_l2); + +latch_ex4_i1_g1_coll : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_i1_g1_coll_offset to ex4_i1_g1_coll_offset), + scout => sov(ex4_i1_g1_coll_offset to ex4_i1_g1_coll_offset), + din(0) => ex3_i1_g1_coll, + dout(0) => ex4_i1_g1_coll_l2); + +latch_ex5_i1_g1_coll : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex5_i1_g1_coll_offset to ex5_i1_g1_coll_offset), + scout => sov(ex5_i1_g1_coll_offset to ex5_i1_g1_coll_offset), + din(0) => ex4_i1_g1_coll_l2, + dout(0) => ex5_i1_g1_coll_l2); + +latch_ld_miss_latency : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ld_miss_latency_offset to ld_miss_latency_offset), + scout => sov(ld_miss_latency_offset to ld_miss_latency_offset), + din(0) => ld_miss_latency_d, + dout(0) => ld_miss_latency_l2); + +latch_lsu_perf_events : tri_rlmreg_p + generic map (width => lsu_perf_events_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(lsu_perf_events_offset to lsu_perf_events_offset + lsu_perf_events_l2'length-1), + scout => sov(lsu_perf_events_offset to lsu_perf_events_offset + lsu_perf_events_l2'length-1), + din => lsu_perf_events, + dout => lsu_perf_events_l2); + +ldqfull: process (ld_rel_val_l2) + variable b: std_ulogic; +begin + b := '1'; + for i in 0 to lmq_entries-1 loop + b := ld_rel_val_l2(i) and b; + end loop; + ld_queue_full <= b; +end process; + +ex3_ld_queue_full <= ld_queue_full or ld_q_seq_wrap; + +-- ***************************************************** +-- Need to flush if command is I=1, G=1 load and there already is one in the load Q for that thread + +ex4_st_I1_G1_val <= ex4_st_entry_l2(44) and ex4_st_entry_l2(46) and ex4_st_val_l2; +st_entry_I1_G1_val <= s_m_queue0(44) and s_m_queue0(46) and st_entry0_val_l2; + +I1_G1_p: process (l_m_queue(0)(18 to 21), l_m_queue(1)(18 to 21), l_m_queue(2)(18 to 21), l_m_queue(3)(18 to 21), l_m_queue(4)(18 to 21), l_m_queue(5)(18 to 21), l_m_queue(6)(18 to 21), l_m_queue(7)(18 to 21), l_m_queue(0)(40), l_m_queue(1)(40), l_m_queue(2)(40), l_m_queue(3)(40), l_m_queue(4)(40), l_m_queue(5)(40), l_m_queue(6)(40), l_m_queue(7)(40), l_m_queue(0)(42), l_m_queue(1)(42), l_m_queue(2)(42), l_m_queue(3)(42), l_m_queue(4)(42), l_m_queue(5)(42), l_m_queue(6)(42), l_m_queue(7)(42), ld_rel_val_l2, st_entry_I1_G1_val, s_m_queue0(38 to 41), ex4_st_I1_G1_val, ex4_st_entry_l2(38 to 41)) + variable b0, b1, b2, b3: std_ulogic; +begin + b0 := '0'; + b1 := '0'; + b2 := '0'; + b3 := '0'; + for i in 0 to lmq_entries-1 loop + b0 := (l_m_queue(i)(40) and l_m_queue(i)(42) and l_m_queue(i)(18) and ld_rel_val_l2(i)) or b0; -- I=1, G=1 for thread 0 and entry is valid + b1 := (l_m_queue(i)(40) and l_m_queue(i)(42) and l_m_queue(i)(19) and ld_rel_val_l2(i)) or b1; -- I=1, G=1 for thread 1 and entry is valid + b2 := (l_m_queue(i)(40) and l_m_queue(i)(42) and l_m_queue(i)(20) and ld_rel_val_l2(i)) or b2; -- I=1, G=1 for thread 2 and entry is valid + b3 := (l_m_queue(i)(40) and l_m_queue(i)(42) and l_m_queue(i)(21) and ld_rel_val_l2(i)) or b3; -- I=1, G=1 for thread 3 and entry is valid + end loop; + I1_G1_thrd0 <= b0 or (ex4_st_I1_G1_val and ex4_st_entry_l2(38)) or (st_entry_I1_G1_val and s_m_queue0(38)); + I1_G1_thrd1 <= b1 or (ex4_st_I1_G1_val and ex4_st_entry_l2(39)) or (st_entry_I1_G1_val and s_m_queue0(39)); + I1_G1_thrd2 <= b2 or (ex4_st_I1_G1_val and ex4_st_entry_l2(40)) or (st_entry_I1_G1_val and s_m_queue0(40)); + I1_G1_thrd3 <= b3 or (ex4_st_I1_G1_val and ex4_st_entry_l2(41)) or (st_entry_I1_G1_val and s_m_queue0(41)); +end process; + +ex3_wimg_g_gated <= ex3_wimge_bits(3) and not (ex3_msgsnd_instr or ex3_dci_instr or ex3_ici_instr or ex3_mtspr_trace or + ex3_sync_instr or ex3_mbar_instr or ex3_tlbsync_instr); + +I1_G1_flush <= (ex3_wimge_bits(1) and ex3_wimg_g_gated and ex3_thrd_id(0) and I1_G1_thrd0) or + (ex3_wimge_bits(1) and ex3_wimg_g_gated and ex3_thrd_id(1) and I1_G1_thrd1) or + (ex3_wimge_bits(1) and ex3_wimg_g_gated and ex3_thrd_id(2) and I1_G1_thrd2) or + (ex3_wimge_bits(1) and ex3_wimg_g_gated and ex3_thrd_id(3) and I1_G1_thrd3); + + +--****************************************************** +-- Check to see if command is already in the load/store miss CAM +--****************************************************** +-- Want to flush if we have a cacheable load op accessing the same cacheline as an op +-- already in the load miss queue or if we have a store going to the same cacheline and +-- a load op is waiting for data to be returned + +addr_comp: for i in 0 to lmq_entries-1 generate begin + comp_val(i) <= ld_rel_val_l2(i) and ex3_cache_acc and not(ex4_drop_ld_req and ex4_loadmiss_qentry(i)) and not(my_ex4_flush_l2 and ex4_loadmiss_qentry(i)); + cmp_ldq_comp_val(i) <= comp_val(i); + l_m_q_cpy(i) <= cmp_ldq_match(i); + l_m_q_cpy_nofl(i) <= l_m_q_cpy(i) and comp_val(i) and not ex3_stg_flush; +end generate; + + + + + +l_m_fnd_nofl <= cmp_ldq_fnd and not ex3_stg_flush; + +entry_found_latch : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(l_m_fnd_offset to l_m_fnd_offset), + scout => sov(l_m_fnd_offset to l_m_fnd_offset), + din(0) => l_m_fnd_nofl, + dout(0) => l_m_fnd_stg); + + +latch_ex4_lmq_cpy : tri_rlmreg_p + generic map (width => ex4_lmq_cpy_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_lmq_cpy_offset to ex4_lmq_cpy_offset + ex4_lmq_cpy_l2'length-1), + scout => sov(ex4_lmq_cpy_offset to ex4_lmq_cpy_offset + ex4_lmq_cpy_l2'length-1), + din => l_m_q_cpy_nofl(0 to lmq_entries-1), + dout => ex4_lmq_cpy_l2(0 to lmq_entries-1)); +latch_ex5_lmq_cpy : tri_rlmreg_p + generic map (width => ex5_lmq_cpy_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex5_lmq_cpy_offset to ex5_lmq_cpy_offset + ex5_lmq_cpy_l2'length-1), + scout => sov(ex5_lmq_cpy_offset to ex5_lmq_cpy_offset + ex5_lmq_cpy_l2'length-1), + din => ex4_lmq_cpy_l2(0 to lmq_entries-1), + dout => ex5_lmq_cpy_l2(0 to lmq_entries-1)); + + +-- ************************************************************************* +-- check gpr source for new ops to look for dependency on loadmiss target + +targetgpr_comp: for i in 0 to lmq_entries-1 generate begin + src0_hit(i) <= (ex1_src0_reg(0 to 7) = l_m_queue(i)(28 to 35)) and ld_rel_val_l2(i) and not (ex4_drop_ld_req and ex4_loadmiss_qentry(i)) and + not l_m_queue(i)(36) and not l_m_queue(i)(38) and not gpr_updated_dly2_l2(i); + src1_hit(i) <= (ex1_src1_reg(0 to 7) = l_m_queue(i)(28 to 35)) and ld_rel_val_l2(i) and not (ex4_drop_ld_req and ex4_loadmiss_qentry(i)) and + not l_m_queue(i)(36) and not l_m_queue(i)(38) and not gpr_updated_dly2_l2(i); + targ_hit(i) <= (ex1_targ_reg(0 to 7) = l_m_queue(i)(28 to 35)) and ld_rel_val_l2(i) and not (ex4_drop_ld_req and ex4_loadmiss_qentry(i)) and + not l_m_queue(i)(36) and not l_m_queue(i)(38) and not gpr_updated_dly2_l2(i); + + watch_bit_v_t0(i) <= ld_rel_val_l2(i) and l_m_queue(i)(52) and l_m_queue(i)(18); + watch_bit_v_t1(i) <= ld_rel_val_l2(i) and l_m_queue(i)(52) and l_m_queue(i)(19); + watch_bit_v_t2(i) <= ld_rel_val_l2(i) and l_m_queue(i)(52) and l_m_queue(i)(20); + watch_bit_v_t3(i) <= ld_rel_val_l2(i) and l_m_queue(i)(52) and l_m_queue(i)(21); +end generate; + +watch_hit_t0 <= or_reduce(watch_bit_v_t0) and ex1_check_watch(0); +watch_hit_t1 <= or_reduce(watch_bit_v_t1) and ex1_check_watch(1); +watch_hit_t2 <= or_reduce(watch_bit_v_t2) and ex1_check_watch(2); +watch_hit_t3 <= or_reduce(watch_bit_v_t3) and ex1_check_watch(3); + +watch_hit <= watch_hit_t0 or watch_hit_t1 or watch_hit_t2 or watch_hit_t3; + +lm_dep_hit_or: process (src0_hit, src1_hit, targ_hit, ex1_src0_vld, ex1_src1_vld, ex1_targ_vld, watch_hit) + variable src0_hit_or: std_ulogic; + variable src1_hit_or: std_ulogic; + variable targ_hit_or: std_ulogic; +begin + src0_hit_or := '0'; + src1_hit_or := '0'; + targ_hit_or := '0'; + for i in 0 to lmq_entries-1 loop + src0_hit_or := src0_hit(i) or src0_hit_or; + src1_hit_or := src1_hit(i) or src1_hit_or; + targ_hit_or := targ_hit(i) or targ_hit_or; + end loop; + ex1_lm_dep_hit <= (src0_hit_or and ex1_src0_vld) or + (src1_hit_or and ex1_src1_vld) or + (targ_hit_or and ex1_targ_vld) or watch_hit; +end process; + +lm_dep_hit_latch : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(lm_dep_hit_offset to lm_dep_hit_offset), + scout => sov(lm_dep_hit_offset to lm_dep_hit_offset), + din(0) => ex1_lm_dep_hit, + dout(0) => ex2_lm_dep_hit_buf); + +ex2_lm_dep_hit <= ex2_lm_dep_hit_buf; + +-- ************************************************************************* +-- Compare back invalidate address to each entry in the load miss queue and +-- set a bit to remember that this address has been invalidated and cannot +-- be written valid in the directory when the reload in finished. + +cmp_back_inv_addr <= anaclat_back_inv_addr(64-real_data_add to 57); + +back_inv_addr_comp: for i in 0 to lmq_entries-1 generate begin +cmp_back_inv_cmp_val(i) <= back_inv_val_l2 and + ld_rel_val_l2(i) and not ld_entry_val_l2(i) and not ex4_loadmiss_qentry(i); + +lmq_back_invalidated_d(i) <= (cmp_back_inv_addr_hit(i) and not reset_lmq_entry(i) ) or + (lmq_back_invalidated_l2(i) and not reset_lmq_entry(i) ); + +end generate; + +latch_lmq_back_invalidated : tri_rlmreg_p + generic map (width => lmq_back_invalidated_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(lmq_back_invalidated_offset to lmq_back_invalidated_offset + lmq_back_invalidated_l2'length-1), + scout => sov(lmq_back_invalidated_offset to lmq_back_invalidated_offset + lmq_back_invalidated_l2'length-1), + din => lmq_back_invalidated_d(0 to lmq_entries-1), + dout => lmq_back_invalidated_l2(0 to lmq_entries-1)); + + + +--****************************************************** +-- Use a first slot open method for the load +-- Override a Reload Queue entry when the reload has returned +--****************************************************** +-- Select which ld miss entry to write to +--l_q0_wrt_en <= not ld_entry0_val_l2 and ld_m_val; +--l_q1_wrt_en <= ld_entry0_val_l2 and not ld_entry1_val_l2 and ld_m_val; +--l_q2_wrt_en <= ld_entry0_val_l2 and ld_entry1_val_l2 and not ld_entry2_val_l2 and ld_m_val; +--l_q3_wrt_en <= ld_entry0_val_l2 and ld_entry1_val_l2 and ld_entry2_val_l2 and not ld_entry3_val_l2 and ld_m_val; + +-- Select which ld miss entry to write to +--l_q0_wrt_en <= not ld_rel0_val_l2 and ld_m_val; +--l_q1_wrt_en <= ld_rel0_val_l2 and not ld_rel1_val_l2 and ld_m_val; +--l_q2_wrt_en <= ld_rel0_val_l2 and ld_rel1_val_l2 and not ld_rel2_val_l2 and ld_m_val; +--l_q3_wrt_en <= ld_rel0_val_l2 and ld_rel1_val_l2 and ld_rel2_val_l2 and not ld_rel3_val_l2 and ld_m_val; + +-- see above commented out logic to see what this is building: + +l_q_wrt_en(0) <= ld_m_val and ((not ld_rel_val_l2(0) and not pe_recov_ld_val_l2) or + (ex7_loadmiss_qentry(0) and pe_recov_ld_val_l2)); + +wrten: for i in 1 to lmq_entries-1 generate begin + wrten_p: process (ld_rel_val_l2(0 to i), ld_m_val, ex7_loadmiss_qentry(i), pe_recov_ld_val_l2) + variable b: std_ulogic; + begin + b := '1'; + for j in 0 to i-1 loop + b := ld_rel_val_l2(j) and b; + end loop; + l_q_wrt_en(i) <= ld_m_val and ((not ld_rel_val_l2(i) and b and not pe_recov_ld_val_l2) or + (ex7_loadmiss_qentry(i) and pe_recov_ld_val_l2)); + end process; +end generate; +cmp_l_q_wrt_en <= l_q_wrt_en; + +--****************************************************** +-- Load Miss Queue entry0 +--****************************************************** + + +rel_done_ecc_err_p: process (ld_m_rel_done_l2, data_ecc_err_l2) + variable b: std_ulogic; +begin + b := '0'; + for i in 0 to lmq_entries-1 loop + b := (ld_m_rel_done_l2(i) and data_ecc_err_l2(i)) or b; + end loop; + rel_done_ecc_err <= b; +end process; + + +cmp_s_m_queue0_addr <= s_m_queue0(58 to (58+real_data_add-6-1)); +cmp_st_entry0_val <= st_entry0_val_l2; +cmp_ex4_st_entry_addr <= ex4_st_entry_l2(58 to (58+real_data_add-6-1)); +cmp_ex4_st_val <= ex4_st_val_l2; + +lmq_entry_act <= ex3_stg_act or pe_recov_ld_val_l2 or clkg_ctl_override_q; +cmp_lmq_entry_act <= lmq_entry_act; + +ldqueue: for i in 0 to lmq_entries-1 generate begin + + + + ld_entry_val_d(i) <= (ex4_loadmiss_qentry(i) and not ex4_flush_load) or + (ld_entry_val_l2(i) and not (load_sent and l_q_rd_en(i)) and + not(ex5_loadmiss_qentry(i) and (ex7_ld_par_err or ex5_flush_load_local)) and + not(ex6_loadmiss_qentry(i) and (ex7_ld_par_err or ex6_flush_l2))); + + + +-- Want to update ld_rel_valid_l2 when either of the following conditions are met +-- 1) When its the next queue entry to update +-- 2) When the reload is done for that queue entry +-- 3) When this load queue entry has been sent to the L2/BFM and its a lock instruction and caused a hit in the L1 +-- 4) When this load queue entry has been sent to the L2/BFM and its encoded command type bit0 was high +-- encoded_cmd_type(0) <= indicates command is a dcbf or dcbi or icbi and is not expecting a reload + +-- all lock instr are cache miss now and all instr that do not get a reload go to the store Q + + reset_lmq_entry(i) <= reset_lmq_entry_rel(i) or + (ex4_loadmiss_qentry(i) and ex4_flush_load) or + (ex5_loadmiss_qentry(i) and ex5_flush_load_local) or + (ex5_loadmiss_qentry(i) and pe_recov_stall and ex6_flush_l2) or + (ex5_loadmiss_qentry(i) and ex7_ld_par_err) or + (ex6_loadmiss_qentry(i) and ex7_ld_par_err) or + (ex6_loadmiss_qentry(i) and not ex4_loadmiss_qentry(i) and ex6_flush_l2); -- don't reset on an ex6 flush if the entry has already been reloaded + + reset_ldq_hit_barr(i) <= ld_m_rel_done_no_retry(i) or ld_m_rel_done_dly_l2(i) or reset_lmq_entry(i); + + + ld_rel_val_d(i) <= l_q_wrt_en(i) or + (ld_rel_val_l2(i) and not reset_lmq_entry(i)); + + + with l_q_wrt_en(i) select + l_m_queue_d(i) <= ld_queue_entry when '1', + l_m_queue(i) when others; + + with l_q_wrt_en(i) select + l_m_queue_addrlo_d(i) <= ld_queue_addrlo(57 to 63) when '1', + l_m_queue_addrlo(i) when others; + + + latch_l_m_queue : tri_rlmreg_p + generic map (width => l_m_queue(i)'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => lmq_entry_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(l_m_queue_offset+(i*l_m_queue(i)'length) to l_m_queue_offset+(i*l_m_queue(i)'length) + l_m_queue(i)'length-1), + scout => sov(l_m_queue_offset+(i*l_m_queue(i)'length) to l_m_queue_offset+(i*l_m_queue(i)'length) + l_m_queue(i)'length-1), + din => l_m_queue_d(i), + dout => l_m_queue(i)); + + latch_l_m_queue_addrlo : tri_rlmreg_p + generic map (width => l_m_queue_addrlo(i)'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => lmq_entry_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(l_m_queue_addrlo_offset+(i*l_m_queue_addrlo(i)'length) to l_m_queue_addrlo_offset+(i*l_m_queue_addrlo(i)'length) + l_m_queue_addrlo(i)'length-1), + scout => sov(l_m_queue_addrlo_offset+(i*l_m_queue_addrlo(i)'length) to l_m_queue_addrlo_offset+(i*l_m_queue_addrlo(i)'length) + l_m_queue_addrlo(i)'length-1), + din => l_m_queue_addrlo_d(i), + dout => l_m_queue_addrlo(i)); + + + l_m_q_hit_st_d(i) <= (cmp_ex3addr_hit_stq and l_q_wrt_en(i) and not store_sent and not pe_recov_ld_val_l2) or + (cmp_ex3addr_hit_ex4st and l_q_wrt_en(i) and not pe_recov_ld_val_l2) or + (ex7_ld_recov_extra_l2(0) and not store_sent and l_q_wrt_en(i) and pe_recov_ld_val_l2) or + (l_m_q_hit_st_l2(i) and (not store_sent and st_entry0_val_l2) and not reset_lmq_entry(i)); + + lmq_drop_rel_d(i) <= (ex4_drop_rel and (ex4_loadmiss_qentry(i) and not pe_recov_state_l2)) or + (ex8_ld_recov_extra_l2(1) and (ex4_loadmiss_qentry(i) and pe_recov_state_l2)) or + (lmq_drop_rel_l2(i) and not ex4_loadmiss_qentry(i)); + + lmq_dvc1_en_d(i) <= (xu_lsu_ex4_dvc1_en and (ex4_loadmiss_qentry(i) and not pe_recov_state_l2)) or + (ex8_ld_recov_extra_l2(2) and (ex4_loadmiss_qentry(i) and pe_recov_state_l2)) or + (lmq_dvc1_en_l2(i) and not ex4_loadmiss_qentry(i)); + + lmq_dvc2_en_d(i) <= (xu_lsu_ex4_dvc2_en and (ex4_loadmiss_qentry(i) and not pe_recov_state_l2)) or + (ex8_ld_recov_extra_l2(3) and (ex4_loadmiss_qentry(i) and pe_recov_state_l2)) or + (lmq_dvc2_en_l2(i) and not ex4_loadmiss_qentry(i)); + +end generate; + +latch_l_m_entry_val : tri_rlmreg_p + generic map (width => ld_entry_val_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ld_entry_val_offset to ld_entry_val_offset + ld_entry_val_l2'length-1), + scout => sov(ld_entry_val_offset to ld_entry_val_offset + ld_entry_val_l2'length-1), + din => ld_entry_val_d, + dout => ld_entry_val_l2); +latch_l_m_rel_val : tri_rlmreg_p + generic map (width => ld_rel_val_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ld_rel_val_offset to ld_rel_val_offset + ld_rel_val_l2'length-1), + scout => sov(ld_rel_val_offset to ld_rel_val_offset + ld_rel_val_l2'length-1), + din => ld_rel_val_d, + dout => ld_rel_val_l2); +latch_l_m_q_hit_st : tri_rlmreg_p + generic map (width => l_m_q_hit_st_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(l_m_q_hit_st_offset to l_m_q_hit_st_offset + l_m_q_hit_st_l2'length-1), + scout => sov(l_m_q_hit_st_offset to l_m_q_hit_st_offset + l_m_q_hit_st_l2'length-1), + din => l_m_q_hit_st_d, + dout => l_m_q_hit_st_l2); + +latch_lmq_drop_rel : tri_rlmreg_p + generic map (width => lmq_drop_rel_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(lmq_drop_rel_offset to lmq_drop_rel_offset + lmq_drop_rel_l2'length-1), + scout => sov(lmq_drop_rel_offset to lmq_drop_rel_offset + lmq_drop_rel_l2'length-1), + din => lmq_drop_rel_d, + dout => lmq_drop_rel_l2); + +latch_lmq_dvc1_en : tri_rlmreg_p + generic map (width => lmq_dvc1_en_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(lmq_dvc1_en_offset to lmq_dvc1_en_offset + lmq_dvc1_en_l2'length-1), + scout => sov(lmq_dvc1_en_offset to lmq_dvc1_en_offset + lmq_dvc1_en_l2'length-1), + din => lmq_dvc1_en_d, + dout => lmq_dvc1_en_l2); + +latch_lmq_dvc2_en : tri_rlmreg_p + generic map (width => lmq_dvc2_en_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(lmq_dvc2_en_offset to lmq_dvc2_en_offset + lmq_dvc2_en_l2'length-1), + scout => sov(lmq_dvc2_en_offset to lmq_dvc2_en_offset + lmq_dvc2_en_l2'length-1), + din => lmq_dvc2_en_d, + dout => lmq_dvc2_en_l2); + +--************************************************************************************************************ +-- Load parity error recovery pipe - load commands are kept unitl ex7 so that if the load got a parity error +-- it can be re-inserted into the load queue from this pipe. The load +-- command behind it (ex6) must also be re-inserted into the load queue +-- in order behind the ex7 load. The rest of the loads (ex4 and ex5) will +-- be flushed. +--************************************************************************************************************ + +ex4_ld_entry_d <= cmd_type_ld(0 to 5) & + ex3_wimge_bits(0 to 4) & + ex3_usr_bits(0 to 3); + +latch_ex4_ld_recov : tri_rlmreg_p + generic map (width => ex4_ld_entry_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => lmq_entry_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_ld_recov_offset to ex4_ld_recov_offset + ex4_ld_entry_l2'length-1), + scout => sov(ex4_ld_recov_offset to ex4_ld_recov_offset + ex4_ld_entry_l2'length-1), + din => ex4_ld_entry_d, + dout => ex4_ld_entry_l2); + +latch_ex4_classid : tri_rlmreg_p + generic map (width => ex4_classid_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => lmq_entry_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_classid_offset to ex4_classid_offset + ex4_classid_l2'length-1), + scout => sov(ex4_classid_offset to ex4_classid_offset + ex4_classid_l2'length-1), + din => ex3_classid(0 to 1), + dout => ex4_classid_l2); + +ex4_ld_recov_val_d <= ex3_l_s_q_val and ex3_load_instr; + +latch_ex4_ld_recov_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_ld_recov_val_offset to ex4_ld_recov_val_offset), + scout => sov(ex4_ld_recov_val_offset to ex4_ld_recov_val_offset), + din(0) => ex4_ld_recov_val_d, + dout(0) => ex4_ld_recov_val_l2); + +ex4_ld_entry_hit_st_d <= (cmp_ex3addr_hit_stq and not store_sent and not pe_recov_ld_val_l2) or + (cmp_ex3addr_hit_ex4st and not pe_recov_ld_val_l2); + +latch_ex4_ld_entry_hit_st : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_ld_entry_hit_st_offset to ex4_ld_entry_hit_st_offset), + scout => sov(ex4_ld_entry_hit_st_offset to ex4_ld_entry_hit_st_offset), + din(0) => ex4_ld_entry_hit_st_d, + dout(0) => ex4_ld_entry_hit_st_l2); + +ex4_ld_recov_mux: process(ex4_loadmiss_qentry, l_m_queue, l_m_queue_addrlo(0)(58 to 63), l_m_queue_addrlo(1)(58 to 63), l_m_queue_addrlo(2)(58 to 63), l_m_queue_addrlo(3)(58 to 63), l_m_queue_addrlo(4)(58 to 63), l_m_queue_addrlo(5)(58 to 63), l_m_queue_addrlo(6)(58 to 63), l_m_queue_addrlo(7)(58 to 63), l_m_q_hit_st_l2) + variable b: std_ulogic_vector(0 to 53); + variable c: std_ulogic; + variable d: std_ulogic_vector(58 to 63); +begin + b := (others => '0') ; + d := (others => '0') ; + c := '0'; + for i in 0 to lmq_entries-1 loop + b := gate_and(ex4_loadmiss_qentry(i), l_m_queue(i)) or b; + d := gate_and(ex4_loadmiss_qentry(i), l_m_queue_addrlo(i)(58 to 63)) or d; + c := (ex4_loadmiss_qentry(i) and l_m_q_hit_st_l2(i)) or c; + end loop; + ex4_ld_recov_entry <= b; + ex4_ld_recov_addrlo <= d; + ex4_ld_recov_ld_hit_st <= c; +end process; + +ex4_touch <= ( ex4_ld_entry_l2(0 to 5) = "001111") or -- dcbt + ( ex4_ld_entry_l2(0 to 5) = "000111") or -- dcbt_l2only + ( ex4_ld_entry_l2(0 to 5) = "011111") or -- dcbtls_l1l2 + ( ex4_ld_entry_l2(0 to 5) = "010111") or -- dcbtls_l2only + ( ex4_ld_entry_l2(0 to 5) = "001101") or -- dcbtst_l1l2 + ( ex4_ld_entry_l2(0 to 5) = "000101") or -- dcbtst_l2only + ( ex4_ld_entry_l2(0 to 5) = "011101") or -- dcbtstls_l1l2 + ( ex4_ld_entry_l2(0 to 5) = "010101") or -- dcbtstls_l2only + ( ex4_ld_entry_l2(0 to 5) = "000100") or -- icbt + ( ex4_ld_entry_l2(0 to 5) = "010100"); -- icbtls + +ex4_l2only <=( ex4_ld_entry_l2(0 to 5) = "000111") or -- dcbt_l2only + ( ex4_ld_entry_l2(0 to 5) = "010111") or -- dcbtls_l2only + ( ex4_ld_entry_l2(0 to 5) = "000101") or -- dcbtst_l2only + ( ex4_ld_entry_l2(0 to 5) = "010101") or -- dcbtstls_l2only + ( ex4_ld_entry_l2(0 to 5) = "000100") or -- icbt + ( ex4_ld_entry_l2(0 to 5) = "010100"); -- icbtls + +ex4_ld_recov <= ex4_ld_recov_entry(0 to 53) & cmp_ex4_ld_addr & ex4_ld_recov_addrlo(58 to 63) when ex4_ld_m_val='1' else + ex4_ld_entry(0) & -- cache inhibit + ex4_ld_entry_l2(0 to 5) & -- ttype + ex4_ld_entry(1 to 6) & -- opsize + ex4_ld_entry(7 to 11) & -- rot sel + ex4_thrd_id(0 to 3) & + cmd_seq_l2(0 to 4) & + ex4_ld_entry(12 to 20) & -- target gpr + ex4_ld_entry(21) & -- axu op + ex4_ld_entry(22) & -- little endian mode + ex4_touch & -- dcbt is valid + ex4_ld_entry_l2(6 to 9) & -- wimg bits + ex4_ld_entry_l2(11 to 14) & -- user defined bits + ex4_ld_entry(23) & -- algebraic + ex4_l2only & -- L2 only + ex4_ld_entry(24) & -- way lock + ex4_classid_l2(0 to 1) & -- way lock bits table select bit (classid) + ex4_ld_entry(25) & -- watch enable + ex4_ld_entry_l2(10) & -- le bit from erat + ex4_ld_entry(26 to (26+(real_data_add-1))); -- p_addr + + +ex5_ld_recov_d <= ex4_ld_recov when pe_recov_stall='0' else + ex5_ld_recov_l2; + +latch_ex5_ld_recov : tri_rlmreg_p + generic map (width => ex5_ld_recov_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ex4_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex5_ld_recov_offset to ex5_ld_recov_offset + ex5_ld_recov_l2'length-1), + scout => sov(ex5_ld_recov_offset to ex5_ld_recov_offset + ex5_ld_recov_l2'length-1), + din => ex5_ld_recov_d, + dout => ex5_ld_recov_l2); + + +ex6_ld_recov_d <= ex5_ld_recov_l2 when pe_recov_stall='0' else + ex6_ld_recov_l2(0 to 37) & '1' & ex6_ld_recov_l2(39 to (54+(real_data_add-1))) when (pe_recov_state_l2 and not pe_recov_state_dly_l2 and ex7_targ_match)='1' else + ex6_ld_recov_l2; + +ex6_ld_recov_act <= ex5_ld_recov_val_l2 or clkg_ctl_override_q or ex6_ld_recov_val_l2; + +latch_ex6_ld_recov : tri_rlmreg_p + generic map (width => ex6_ld_recov_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ex6_ld_recov_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex6_ld_recov_offset to ex6_ld_recov_offset + ex6_ld_recov_l2'length-1), + scout => sov(ex6_ld_recov_offset to ex6_ld_recov_offset + ex6_ld_recov_l2'length-1), + din => ex6_ld_recov_d, + dout => ex6_ld_recov_l2); + + +ex7_ld_recov_d <= ex6_ld_recov_l2 when pe_recov_stall='0' else + ex7_ld_recov_l2(0 to 37) & '1' & ex7_ld_recov_l2(39 to (54+(real_data_add-1))) when (pe_recov_state_l2 and not pe_recov_state_dly_l2 and ex8_targ_match)='1' else + ex7_ld_recov_l2; + +ex7_ld_recov_act <= ex6_ld_recov_val_l2 or clkg_ctl_override_q or ex7_ld_recov_val_l2; + +latch_ex7_ld_recov : tri_rlmreg_p + generic map (width => ex7_ld_recov_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ex7_ld_recov_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex7_ld_recov_offset to ex7_ld_recov_offset + ex7_ld_recov_l2'length-1), + scout => sov(ex7_ld_recov_offset to ex7_ld_recov_offset + ex7_ld_recov_l2'length-1), + din => ex7_ld_recov_d, + dout => ex7_ld_recov_l2); + +cmp_ex7_ld_recov_addr <= ex7_ld_recov_l2((54) to (54+real_data_add-6-1)); + +ex4_ld_recov_extra(0) <= ex4_ld_recov_ld_hit_st when ex4_ld_m_val='1' else + ex4_ld_entry_hit_st_l2; + +ex4_ld_recov_extra(1) <= '0'; +ex4_ld_recov_extra(2) <= xu_lsu_ex4_dvc1_en; +ex4_ld_recov_extra(3) <= xu_lsu_ex4_dvc2_en; + +ex5_ld_recov_extra_d(0) <= ex4_ld_recov_extra(0) and (not store_sent and st_entry0_val_l2) when pe_recov_stall='0' else + (ex5_ld_recov_extra_l2(0) and (not store_sent and st_entry0_val_l2)) or +-- when the 1st pe is detected, ex5 will have the last op that needs to be executed. By setting this bit, it ensures that +-- any stores are done before it executes so that it will be the last op and remain in order + (ex7_ld_par_err and not pe_recov_state_l2); + +ex5_ld_recov_extra_d(1 to 3) <= ex4_ld_recov_extra(1 to 3) when pe_recov_stall='0' else + ex5_ld_recov_extra_l2(1 to 3); + +latch_ex5_ld_recov_extra : tri_rlmreg_p + generic map (width => ex5_ld_recov_extra_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ex4_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex5_ld_recov_extra_offset to ex5_ld_recov_extra_offset + ex5_ld_recov_extra_l2'length-1), + scout => sov(ex5_ld_recov_extra_offset to ex5_ld_recov_extra_offset + ex5_ld_recov_extra_l2'length-1), + din => ex5_ld_recov_extra_d, + dout => ex5_ld_recov_extra_l2); + +ex6_ld_recov_extra_d(0) <= ex5_ld_recov_extra_l2(0) and (not store_sent and st_entry0_val_l2) when pe_recov_stall='0' else + ex6_ld_recov_extra_l2(0) and (not store_sent and st_entry0_val_l2); + +ex6_ld_recov_extra_d(1 to 3) <= ex5_ld_recov_extra_l2(1 to 3) when pe_recov_stall='0' else + ex6_ld_recov_extra_l2(1 to 3); + +latch_ex6_ld_recov_extra : tri_rlmreg_p + generic map (width => ex6_ld_recov_extra_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ex6_ld_recov_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex6_ld_recov_extra_offset to ex6_ld_recov_extra_offset + ex6_ld_recov_extra_l2'length-1), + scout => sov(ex6_ld_recov_extra_offset to ex6_ld_recov_extra_offset + ex6_ld_recov_extra_l2'length-1), + din => ex6_ld_recov_extra_d, + dout => ex6_ld_recov_extra_l2); + +ex7_ld_recov_extra_d(0) <= ex6_ld_recov_extra_l2(0) and (not store_sent and st_entry0_val_l2) when pe_recov_stall='0' else + ex7_ld_recov_extra_l2(0) and (not store_sent and st_entry0_val_l2); + +ex7_ld_recov_extra_d(1 to 3) <= ex6_ld_recov_extra_l2(1 to 3) when pe_recov_stall='0' else + ex7_ld_recov_extra_l2(1 to 3); + +latch_ex7_ld_recov_extra : tri_rlmreg_p + generic map (width => ex7_ld_recov_extra_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ex7_ld_recov_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex7_ld_recov_extra_offset to ex7_ld_recov_extra_offset + ex7_ld_recov_extra_l2'length-1), + scout => sov(ex7_ld_recov_extra_offset to ex7_ld_recov_extra_offset + ex7_ld_recov_extra_l2'length-1), + din => ex7_ld_recov_extra_d, + dout => ex7_ld_recov_extra_l2); + +ex8_ld_recov_act <= ex7_ld_recov_val_l2 or clkg_ctl_override_q; + +latch_ex8_ld_recov_extra : tri_rlmreg_p + generic map (width => ex8_ld_recov_extra_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ex8_ld_recov_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex8_ld_recov_extra_offset to ex8_ld_recov_extra_offset + ex8_ld_recov_extra_l2'length-1), + scout => sov(ex8_ld_recov_extra_offset to ex8_ld_recov_extra_offset + ex8_ld_recov_extra_l2'length-1), + din => ex7_ld_recov_extra_l2(1 to 3), + dout => ex8_ld_recov_extra_l2); + + + + +ex5_ld_recov_val_d <= ((ex4_ld_m_val or ex4_ld_recov_val_l2) and not ex4_flush_load_wo_drop and not pe_recov_stall) or + (ex5_ld_recov_val_l2 and pe_recov_stall and pe_recov_state_l2 and not ex6_flush_l2) or + (ex5_ld_recov_val_l2 and pe_recov_stall and ex7_ld_par_err and not pe_recov_state_l2 and not ex5_flush_load_local); + +latch_ex5_ld_recov_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex5_ld_recov_val_offset to ex5_ld_recov_val_offset), + scout => sov(ex5_ld_recov_val_offset to ex5_ld_recov_val_offset), + din(0) => ex5_ld_recov_val_d, + dout(0) => ex5_ld_recov_val_l2); + +ex5_ld_recov_val_not_fl <= (ex5_ld_recov_val_l2 and not ex5_flush_load_local and not ex7_ld_par_err and not pe_recov_state_l2) or + (ex5_ld_recov_val_l2 and not pe_recov_stall and pe_recov_state_l2) or + (ex6_ld_recov_val_l2 and pe_recov_stall and not (ex6_flush_l2 and not pe_recov_state_l2)); + +latch_ex6_ld_recov_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex6_ld_recov_val_offset to ex6_ld_recov_val_offset), + scout => sov(ex6_ld_recov_val_offset to ex6_ld_recov_val_offset), + din(0) => ex5_ld_recov_val_not_fl, + dout(0) => ex6_ld_recov_val_l2); + +ex6_ld_recov_val_not_fl <= (ex6_ld_recov_val_l2 and not ex6_flush_l2 and not ex7_ld_par_err and not pe_recov_state_l2) or + (ex6_ld_recov_val_l2 and not pe_recov_stall and pe_recov_state_l2) or + (ex7_ld_recov_val_l2 and pe_recov_stall); + + +latch_ex7_ld_recov_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex7_ld_recov_val_offset to ex7_ld_recov_val_offset), + scout => sov(ex7_ld_recov_val_offset to ex7_ld_recov_val_offset), + din(0) => ex6_ld_recov_val_not_fl, + dout(0) => ex7_ld_recov_val_l2); + + +-- Compare store queue to the ex6 recovery load and if they match and ex6 load has ld_hit_st=0, then +-- the load was 1st and will neeed to set a bit to block the store until the ld queue is empty when +-- in parity error recovery. If ex6 ld_hit_st=1, then the store was 1st and does not need to be blocked. +-- The load will wait in the load queue because of the ld_hit_st bit. + +stq_hit_ex6_recov <= (ex6_ld_recov_l2((54) to (54+real_data_add-7-1)) = s_m_queue0(58 to (58+real_data_add-7-1))) and + ((ex6_ld_recov_l2(54+real_data_add-6-1) = s_m_queue0(58+real_data_add-6-1)) or my_xucr0_cls) and + st_entry0_val_l2 and ex6_ld_recov_val_not_fl; + +ex4st_hit_ex6_recov <= (ex6_ld_recov_l2((54) to (54+real_data_add-7-1)) = ex4_st_entry_l2(58 to (58+real_data_add-7-1))) and + ((ex6_ld_recov_l2(54+real_data_add-6-1) = ex4_st_entry_l2(58+real_data_add-6-1)) or my_xucr0_cls) and + ex4_st_val_l2 and ex6_ld_recov_val_not_fl; + +set_st_hit_recov_ld <= stq_hit_ex6_recov or ex4st_hit_ex6_recov; + +reset_st_hit_recov_ld <= not (pe_recov_state_l2 or ex7_ld_par_err) or + (pe_recov_ld_num_l2(1) and lmq_empty and not ex7_ld_recov_val_l2) or + ((pe_recov_ld_num_l2(1) or pe_recov_ld_num_l2(2)) and lmq_empty and ex7_ld_recov_val_l2 and ex7_ld_recov_extra_l2(0)); -- next load is v and will wait for st + +st_hit_recov_ld_d <= (set_st_hit_recov_ld and not ex6_ld_recov_extra_l2(0)) or + (st_recycle_v_l2 and st_entry0_val_l2 and store_sent) or + (st_hit_recov_ld_l2 and not reset_st_hit_recov_ld); + +blk_st_for_pe_recov <= ex7_ld_par_err or (pe_recov_state_l2 and st_hit_recov_ld_l2); + +blk_st_cred_pop <= blk_st_for_pe_recov and not pe_recov_state_d; + +latch_st_hit_recov_ld : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(st_hit_recov_ld_offset to st_hit_recov_ld_offset), + scout => sov(st_hit_recov_ld_offset to st_hit_recov_ld_offset), + din(0) => st_hit_recov_ld_d, + dout(0) => st_hit_recov_ld_l2); + +--************************************************************************************************************ +--************************************************************************************************************ +-- END: LOAD QUEUE LOGIC +--************************************************************************************************************ +--************************************************************************************************************ + +--************************************************************************************************************ +--************************************************************************************************************ +-- INSTRUCTION FETCH QUEUE LOGIC +-- Instruction Fetch Queue Entry - 4 entries, 1 per thread +--************************************************************************************************************ +--************************************************************************************************************ + +ifetch_act <= i_x_request or clkg_ctl_override_q; + +latch_ifetch_req : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ifetch_req_offset to ifetch_req_offset), + scout => sov(ifetch_req_offset to ifetch_req_offset), + din(0) => i_x_request, + dout(0) => ifetch_req_l2); + +latch_ifetch_ra : tri_rlmreg_p + generic map (width => ifetch_ra_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ifetch_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ifetch_ra_offset to ifetch_ra_offset + ifetch_ra_l2'length-1), + scout => sov(ifetch_ra_offset to ifetch_ra_offset + ifetch_ra_l2'length-1), + din => i_x_ra, + dout => ifetch_ra_l2); + +latch_ifetch_wimge : tri_rlmreg_p + generic map (width => ifetch_wimge_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ifetch_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ifetch_wimge_offset to ifetch_wimge_offset + ifetch_wimge_l2'length-1), + scout => sov(ifetch_wimge_offset to ifetch_wimge_offset + ifetch_wimge_l2'length-1), + din => i_x_wimge, + dout => ifetch_wimge_l2); + +latch_ifetch_thread : tri_rlmreg_p + generic map (width => ifetch_thread_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ifetch_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ifetch_thread_offset to ifetch_thread_offset + ifetch_thread_l2'length-1), + scout => sov(ifetch_thread_offset to ifetch_thread_offset + ifetch_thread_l2'length-1), + din => i_x_thread, + dout => ifetch_thread_l2); + +latch_ifetch_userdef : tri_rlmreg_p + generic map (width => ifetch_userdef_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ifetch_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ifetch_userdef_offset to ifetch_userdef_offset + ifetch_userdef_l2'length-1), + scout => sov(ifetch_userdef_offset to ifetch_userdef_offset + ifetch_userdef_l2'length-1), + din => i_x_userdef, + dout => ifetch_userdef_l2); + +iu_f_tid0_val <= ifetch_req_l2 and ifetch_thread_l2(0); +iu_f_tid1_val <= ifetch_req_l2 and ifetch_thread_l2(1); +iu_f_tid2_val <= ifetch_req_l2 and ifetch_thread_l2(2); +iu_f_tid3_val <= ifetch_req_l2 and ifetch_thread_l2(3); + +--****************************************************** +-- Instruction Fetch Sequence Write +--****************************************************** +iu_seq_incr <= std_ulogic_vector(unsigned(iu_seq_l2) + 1); + +iu_seq_d <= iu_seq_incr when ifetch_req_l2 = '1' else + iu_seq_l2; + +latch_iu_seq : tri_rlmreg_p + generic map (width => iu_seq_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => iuq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(iu_seq_offset to iu_seq_offset + iu_seq_l2'length-1), + scout => sov(iu_seq_offset to iu_seq_offset + iu_seq_l2'length-1), + din => iu_seq_d(0 to 2), + dout => iu_seq_l2(0 to 2)); + +--****************************************************** +-- Instruction Fetch Sequence Read +--****************************************************** +iu_seq_rd_incr <= std_ulogic_vector(unsigned(iu_seq_rd_l2) + 1); + +iu_seq_rd_d <= iu_seq_rd_incr when iu_sent_val = '1' else + iu_seq_rd_l2; + +latch_iu_seq_rd : tri_rlmreg_p + generic map (width => iu_seq_rd_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => iuq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(iu_seq_rd_offset to iu_seq_rd_offset + iu_seq_rd_l2'length-1), + scout => sov(iu_seq_rd_offset to iu_seq_rd_offset + iu_seq_rd_l2'length-1), + din => iu_seq_rd_d, + dout => iu_seq_rd_l2); + +-- Instruction Fetch Queue Entry - 4 Queue Entries +-- bit(0:4) = wimge +-- bit(5:xx) = real address +-- bit(xx:xx+3) = instruction fetch sequence number + +iu_queue_entry <= ifetch_wimge_l2(0 to 4) & ifetch_userdef_l2(0 to 3) & ifetch_ra_l2 & iu_seq_l2; + +--****************************************************** +-- Instruction Fetch Queue0 -TID0 +--****************************************************** + +iuq_act <= ifetch_req_l2 or iu_val_req or clkg_ctl_override_q; + +iu_f_q0_val_upd <= iu_f_tid0_val & i_f_q0_sent; + +with iu_f_q0_val_upd select + i_f_q0_val_d <= '1' when "10", + '0' when "01", + i_f_q0_val_l2 when others; + +with iu_f_tid0_val select + i_f_q0_d <= iu_queue_entry when '1', + i_f_q0_l2 when others; + +latch_iu_q0_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => iuq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(i_f_q0_val_offset to i_f_q0_val_offset), + scout => sov(i_f_q0_val_offset to i_f_q0_val_offset), + din(0) => i_f_q0_val_d, + dout(0) => i_f_q0_val_l2); + +latch_iu_q0 : tri_rlmreg_p + generic map (width => i_f_q0_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => iuq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(i_f_q0_offset to i_f_q0_offset + i_f_q0_l2'length-1), + scout => sov(i_f_q0_offset to i_f_q0_offset + i_f_q0_l2'length-1), + din => i_f_q0_d, + dout => i_f_q0_l2); + +--****************************************************** +-- Instruction Fetch Queue1 -TID1 +--****************************************************** + +iu_f_q1_val_upd <= iu_f_tid1_val & i_f_q1_sent; + +with iu_f_q1_val_upd select + i_f_q1_val_d <= '1' when "10", + '0' when "01", + i_f_q1_val_l2 when others; + +with iu_f_tid1_val select + i_f_q1_d <= iu_queue_entry when '1', + i_f_q1_l2 when others; + +latch_iu_q1_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => iuq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(i_f_q1_val_offset to i_f_q1_val_offset), + scout => sov(i_f_q1_val_offset to i_f_q1_val_offset), + din(0) => i_f_q1_val_d, + dout(0) => i_f_q1_val_l2); + +latch_iu_q1 : tri_rlmreg_p + generic map (width => i_f_q1_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => iuq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(i_f_q1_offset to i_f_q1_offset + i_f_q1_l2'length-1), + scout => sov(i_f_q1_offset to i_f_q1_offset + i_f_q1_l2'length-1), + din => i_f_q1_d, + dout => i_f_q1_l2); + +--****************************************************** +-- Instruction Fetch Queue2 -TID2 +--****************************************************** + +iu_f_q2_val_upd <= iu_f_tid2_val & i_f_q2_sent; + +with iu_f_q2_val_upd select + i_f_q2_val_d <= '1' when "10", + '0' when "01", + i_f_q2_val_l2 when others; + +with iu_f_tid2_val select + i_f_q2_d <= iu_queue_entry when '1', + i_f_q2_l2 when others; + +latch_iu_q2_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => iuq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(i_f_q2_val_offset to i_f_q2_val_offset), + scout => sov(i_f_q2_val_offset to i_f_q2_val_offset), + din(0) => i_f_q2_val_d, + dout(0) => i_f_q2_val_l2); + +latch_iu_q2 : tri_rlmreg_p + generic map (width => i_f_q2_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => iuq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(i_f_q2_offset to i_f_q2_offset + i_f_q2_l2'length-1), + scout => sov(i_f_q2_offset to i_f_q2_offset + i_f_q2_l2'length-1), + din => i_f_q2_d, + dout => i_f_q2_l2); + +--****************************************************** +-- Instruction Fetch Queue3 -TID3 +--****************************************************** + +iu_f_q3_val_upd <= iu_f_tid3_val & i_f_q3_sent; + +with iu_f_q3_val_upd select + i_f_q3_val_d <= '1' when "10", + '0' when "01", + i_f_q3_val_l2 when others; + +with iu_f_tid3_val select + i_f_q3_d <= iu_queue_entry when '1', + i_f_q3_l2 when others; + +latch_iu_q3_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => iuq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(i_f_q3_val_offset to i_f_q3_val_offset), + scout => sov(i_f_q3_val_offset to i_f_q3_val_offset), + din(0) => i_f_q3_val_d, + dout(0) => i_f_q3_val_l2); + +latch_iu_q3 : tri_rlmreg_p + generic map (width => i_f_q3_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => iuq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(i_f_q3_offset to i_f_q3_offset + i_f_q3_l2'length-1), + scout => sov(i_f_q3_offset to i_f_q3_offset + i_f_q3_l2'length-1), + din => i_f_q3_d, + dout => i_f_q3_l2); + +--************************************************************************************************************ +--************************************************************************************************************ +-- END: INSTRUCTION FETCH QUEUE LOGIC +--************************************************************************************************************ +--************************************************************************************************************ + +--************************************************************************************************************ +-- MMU QUEUE +--************************************************************************************************************ + +mm_req_val_d <= not (mm_xu_lsu_req(0 to 3) = "0000"); + +mmq_act <= mm_req_val_d or clkg_ctl_override_q; + +mmu_q_val_d <= (not (mm_xu_lsu_req(0 to 3) = "0000")) or + (not mmu_sent and mmu_q_val_l2); + +mmu_command <= mm_xu_lsu_ttype(0 to 1) & -- (0:1) command type + mm_xu_lsu_req(0 to 3) & -- (2:5) thread ID + mm_xu_lsu_wimge(0 to 4) & -- (6:10) wimg and endian bits + mm_xu_lsu_u(0 to 3) & -- (11:14) user defined bits + mm_xu_lsu_lpid(0 to 7) & -- (15:22) lpid + mm_xu_lsu_ind & -- (23) ind + mm_xu_lsu_gs & -- (24) gs + mm_xu_lsu_lbit & -- (25) "L" bit, for large vs. small) + mm_xu_lsu_addr(64-real_data_add to 63); -- (26:??) address field for command + +mmu_q_entry_d <= mmu_command when mmu_q_val_l2 = '0' else + mmu_q_entry_l2; + +latch_mm_req_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(mm_req_val_offset to mm_req_val_offset), + scout => sov(mm_req_val_offset to mm_req_val_offset), + din(0) => mm_req_val_d, + dout(0) => mm_req_val_l2); + +latch_mmu_q_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(mmu_q_val_offset to mmu_q_val_offset), + scout => sov(mmu_q_val_offset to mmu_q_val_offset), + din(0) => mmu_q_val_d, + dout(0) => mmu_q_val_l2); + +latch_mmu_q_entry : tri_rlmreg_p + generic map (width => mmu_q_entry_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => mmq_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(mmu_q_entry_offset to mmu_q_entry_offset + mmu_q_entry_l2'length-1), + scout => sov(mmu_q_entry_offset to mmu_q_entry_offset + mmu_q_entry_l2'length-1), + din => mmu_q_entry_d, + dout => mmu_q_entry_l2); + + + + + +--************************************************************************************************************ +--************************************************************************************************************ +-- LOAD QUEUE COMMAND COUNT (used to determine credits) +--************************************************************************************************************ +--************************************************************************************************************ +load_cmd_count_incr(0 to 3) <= std_ulogic_vector(unsigned(load_cmd_count_l2) + 1); +load_cmd_count_decr(0 to 3) <= std_ulogic_vector(unsigned(load_cmd_count_l2) - 1); +load_cmd_count_decrby2(0 to 3) <= std_ulogic_vector(unsigned(load_cmd_count_l2) - 2); + +load_credit_used <= load_sent or iu_sent_val or mmu_ld_sent; + + +-- break apart mux control to fix timing +decr_load_cnt_lcu0 <= ( anaclat_ld_pop and not (ex6_load_sent_l2 and (ex6_flush_l2 or ex7_ld_par_err))) or -- when load_credit_used=0 + (not anaclat_ld_pop and (ex6_load_sent_l2 and (ex6_flush_l2 or ex7_ld_par_err))); +dec_by2_ld_cnt_lcu0 <= anaclat_ld_pop and (ex6_load_sent_l2 and (ex6_flush_l2 or ex7_ld_par_err)); +hold_load_cnt_lcu0 <= (not anaclat_ld_pop and not (ex6_load_sent_l2 and (ex6_flush_l2 or ex7_ld_par_err))); + +incr_load_cnt_lcu1 <= not anaclat_ld_pop and not (ex6_load_sent_l2 and (ex6_flush_l2 or ex7_ld_par_err)); -- when load_credit_used=1 +decr_load_cnt_lcu1 <= ( anaclat_ld_pop and (ex6_load_sent_l2 and (ex6_flush_l2 or ex7_ld_par_err))); +hold_load_cnt_lcu1 <= (not anaclat_ld_pop and (ex6_load_sent_l2 and (ex6_flush_l2 or ex7_ld_par_err))) or + ( anaclat_ld_pop and not (ex6_load_sent_l2 and (ex6_flush_l2 or ex7_ld_par_err))); + + +load_cmd_count_lcu0(0 to 3) <= gate_and(decr_load_cnt_lcu0, load_cmd_count_decr(0 to 3)) or -- when load_credit_used=0 + gate_and(dec_by2_ld_cnt_lcu0, load_cmd_count_decrby2(0 to 3)) or + gate_and(hold_load_cnt_lcu0, load_cmd_count_l2); +load_cmd_count_lcu1(0 to 3) <= gate_and(incr_load_cnt_lcu1, load_cmd_count_incr(0 to 3)) or -- when load_credit_used=1 + gate_and(decr_load_cnt_lcu1, load_cmd_count_decr(0 to 3)) or + gate_and(hold_load_cnt_lcu1, load_cmd_count_l2); + +load_cmd_count_d(0 to 3) <= gate_and(not load_credit_used, load_cmd_count_lcu0) or + gate_and( load_credit_used, load_cmd_count_lcu1); + +latch_load_cmd_count : tri_rlmreg_p + generic map (width => load_cmd_count_l2'length, init => 6, expand_type => expand_type) -- init to 4 to leave 4 credits left + port map (nclk => nclk, + act => '1', + forcee => cfg_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => cfg_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => bcfg_siv(load_cmd_count_offset to load_cmd_count_offset + load_cmd_count_l2'length-1), + scout => bcfg_sov(load_cmd_count_offset to load_cmd_count_offset + load_cmd_count_l2'length-1), + din => load_cmd_count_d(0 to 3), + dout => load_cmd_count_l2(0 to 3) ); + +ld_credit_pre <= not load_cmd_count_l2(0); -- when cmd count gets to 8, there are no load credits left + +load_credit <= ld_credit_pre and not (my_xucr0_cred and not st_credit_pre); + + +--************************************************************************************************************ +--************************************************************************************************************ +-- STORE QUEUE COMMAND COUNT (used to determine credits) +--************************************************************************************************************ +--************************************************************************************************************ +store_cmd_count_incr(0 to 5) <= std_ulogic_vector(unsigned(store_cmd_count_l2) + 1); +store_cmd_count_decr(0 to 5) <= std_ulogic_vector(unsigned(store_cmd_count_l2) - 1); +store_cmd_count_decby2(0 to 5) <= std_ulogic_vector(unsigned(store_cmd_count_l2) - 2); +store_cmd_count_decby3(0 to 5) <= std_ulogic_vector(unsigned(store_cmd_count_l2) - 3); + + +st_count_ctrl(0) <= store_sent or mmu_st_sent; -- +1 +st_count_ctrl(1) <= anaclat_st_pop; -- -1 +st_count_ctrl(2) <= anaclat_st_gather; -- -1 +st_count_ctrl(3) <= (ex6_store_sent_l2 and ex6_flush_l2) or + (l2req_recycle_l2 and ex7_ld_par_err); -- -1 + +incr_store_cmd <= st_count_ctrl="1000"; + +decr_store_cmd <= (st_count_ctrl="0001") or + (st_count_ctrl="0010") or + (st_count_ctrl="0100") or + (st_count_ctrl="1011") or + (st_count_ctrl="1101") or + (st_count_ctrl="1110"); + +dec_by2_st_cmd <= (st_count_ctrl="0011") or + (st_count_ctrl="0101") or + (st_count_ctrl="0110") or + (st_count_ctrl="1111"); + +dec_by3_st_cmd <= (st_count_ctrl="0111"); + +hold_store_cmd <= (st_count_ctrl="0000") or + (st_count_ctrl="1001") or + (st_count_ctrl="1100") or + (st_count_ctrl="1010"); + + +store_cmd_count_d(0 to 5) <= gate_and(incr_store_cmd, store_cmd_count_incr(0 to 5)) or + gate_and(decr_store_cmd, store_cmd_count_decr(0 to 5)) or + gate_and(dec_by2_st_cmd, store_cmd_count_decby2(0 to 5)) or + gate_and(dec_by3_st_cmd, store_cmd_count_decby3(0 to 5)) or + gate_and(hold_store_cmd, store_cmd_count_l2(0 to 5)); + +latch_store_cmd_count : tri_rlmreg_p + generic map (width => store_cmd_count_l2'length, init => 28, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => cfg_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => cfg_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => bcfg_siv(store_cmd_count_offset to store_cmd_count_offset + store_cmd_count_l2'length-1), + scout => bcfg_sov(store_cmd_count_offset to store_cmd_count_offset + store_cmd_count_l2'length-1), + din => store_cmd_count_d(0 to 5), + dout => store_cmd_count_l2(0 to 5) ); + + +st_credit_pre <= not store_cmd_count_l2(0); -- When cmd count gets to 32, there are no store credits left. + +store_credit <= st_credit_pre and not (my_xucr0_cred and not ld_credit_pre ) and not blk_st_for_pe_recov; +one_st_cred <= store_cmd_count_l2="011111"; + +--************************************************************************************************************ +--************************************************************************************************************ +-- INSTRUCTION FETCH QUEUE SELECT LOGIC +--************************************************************************************************************ +--************************************************************************************************************ +iu_f_q0_sel <= (iu_seq_rd_l2 = i_f_q0_l2((REAL_IFAR_length+9) to (REAL_IFAR_length+11))) and i_f_q0_val_l2; +iu_f_q1_sel <= (iu_seq_rd_l2 = i_f_q1_l2((REAL_IFAR_length+9) to (REAL_IFAR_length+11))) and i_f_q1_val_l2; +iu_f_q2_sel <= (iu_seq_rd_l2 = i_f_q2_l2((REAL_IFAR_length+9) to (REAL_IFAR_length+11))) and i_f_q2_val_l2; +iu_f_q3_sel <= (iu_seq_rd_l2 = i_f_q3_l2((REAL_IFAR_length+9) to (REAL_IFAR_length+11))) and i_f_q3_val_l2; + +iu_f_q_sel(0) <= (not iu_f_q0_sel and not iu_f_q1_sel and not iu_f_q2_sel and iu_f_q3_sel) or + (not iu_f_q0_sel and not iu_f_q1_sel and iu_f_q2_sel and not iu_f_q3_sel); + +iu_f_q_sel(1) <= (not iu_f_q0_sel and not iu_f_q1_sel and not iu_f_q2_sel and iu_f_q3_sel) or + (not iu_f_q0_sel and iu_f_q1_sel and not iu_f_q2_sel and not iu_f_q3_sel); + +with iu_f_q_sel select + iu_f_sel_entry <= i_f_q3_l2(0 to (9+REAL_IFAR_length-1)) when "11", + i_f_q2_l2(0 to (9+REAL_IFAR_length-1)) when "10", + i_f_q1_l2(0 to (9+REAL_IFAR_length-1)) when "01", + i_f_q0_l2(0 to (9+REAL_IFAR_length-1)) when others; + +i_f_q0_sent <= iu_f_q0_sel and load_credit and send_if_req_l2 and not (ex5_sel_st_req or ((ob_req_val_l2 or ob_ditc_val_l2 or st_recycle_v_l2) and store_credit)) and + not (l2req_resend_l2 and ex7_ld_par_err); +i_f_q1_sent <= iu_f_q1_sel and load_credit and send_if_req_l2 and not (ex5_sel_st_req or ((ob_req_val_l2 or ob_ditc_val_l2 or st_recycle_v_l2) and store_credit)) and + not (l2req_resend_l2 and ex7_ld_par_err); +i_f_q2_sent <= iu_f_q2_sel and load_credit and send_if_req_l2 and not (ex5_sel_st_req or ((ob_req_val_l2 or ob_ditc_val_l2 or st_recycle_v_l2) and store_credit)) and + not (l2req_resend_l2 and ex7_ld_par_err); +i_f_q3_sent <= iu_f_q3_sel and load_credit and send_if_req_l2 and not (ex5_sel_st_req or ((ob_req_val_l2 or ob_ditc_val_l2 or st_recycle_v_l2) and store_credit)) and + not (l2req_resend_l2 and ex7_ld_par_err); + +-- valid IU request is in the Instruction Fetch Queue +iu_val_req <= i_f_q0_val_l2 or i_f_q1_val_l2 or i_f_q2_val_l2 or i_f_q3_val_l2; + +iu_sent_val <= iu_val_req and load_credit and send_if_req_l2 and + not (ex5_sel_st_req or ((ob_req_val_l2 or ob_ditc_val_l2 or st_recycle_v_l2) and store_credit)) and + not (l2req_resend_l2 and ex7_ld_par_err); + +iu_val <= iu_val_req or ifetch_req_l2; +ld_q_val <= ex4_ld_m_val_not_fl or + (selected_ld_entry_val and not (lq_rd_en_is_ex5 and ex5_flush_load_local) and not (lq_rd_en_is_ex6 and ex6_flush_l2) ); + +ld_q_req <= ex4_ld_m_val_not_fl; + +mmu_q_val <= mmu_q_val_l2 and not mm_req_val_l2; + +-- Round Robin State Machine +-- Want to update Request Selection when +-- 1) there are no requests in LDQ, MMUQ or IUQ and received a IU/LD/MMU request +-- 2) when a Request is sent +state_trans <= ((ifetch_req_l2 or ld_q_req or mm_req_val_l2) and not (iu_val_req or selected_ld_entry_val or mmu_q_val_l2)) or + (load_sent or load_flushed or iu_sent_val or mmu_sent) or + (send_if_req_l2 and not iu_val) or (send_ld_req_l2 and not ld_q_val) or (send_mm_req_l2 and not mmu_q_val_l2); + + +-- select the next state based on this table: +-- +-- request val | prev state: | prev state: | prev state: | +-- I L M | sel I | sel L | sel M | +-- =============|===============|==============|===============| +-- 0 0 0 | I | L | M | +-- 0 0 1 | M | M | M | +-- 0 1 0 | L | L | L | +-- 0 1 1 | L | M | L | +-- 1 0 0 | I | I | I | +-- 1 0 1 | M | M | I | +-- 1 1 0 | L | I | I | +-- 1 1 1 | L | M | I | +-- +-- these next state bits should always be 1-hot (init to I=1, L=0, M=0) + +sel_if_req <= ( iu_val and not ld_q_val and not mmu_q_val_l2 ) or + ( iu_val and not ld_q_val and mmu_q_val_l2 and send_mm_req_l2) or + ( iu_val and ld_q_val and not mmu_q_val_l2 and send_ld_req_l2) or + ( iu_val and ld_q_val and not mmu_q_val_l2 and send_mm_req_l2) or + ( iu_val and ld_q_val and mmu_q_val_l2 and send_mm_req_l2) or + (not iu_val and not ld_q_val and not mmu_q_val_l2 and send_if_req_l2); + +sel_ld_req <= (not iu_val and ld_q_val and not mmu_q_val_l2 ) or + (not iu_val and ld_q_val and mmu_q_val_l2 and send_if_req_l2) or + (not iu_val and ld_q_val and mmu_q_val_l2 and send_mm_req_l2) or + ( iu_val and ld_q_val and not mmu_q_val_l2 and send_if_req_l2) or + ( iu_val and ld_q_val and mmu_q_val_l2 and send_if_req_l2) or + (not iu_val and not ld_q_val and not mmu_q_val_l2 and send_ld_req_l2); + +sel_mm_req <= (not iu_val and not ld_q_val and mmu_q_val_l2 ) or + (not iu_val and ld_q_val and mmu_q_val_l2 and send_ld_req_l2) or + ( iu_val and not ld_q_val and mmu_q_val_l2 and send_if_req_l2) or + ( iu_val and not ld_q_val and mmu_q_val_l2 and send_ld_req_l2) or + ( iu_val and ld_q_val and mmu_q_val_l2 and send_ld_req_l2) or + (not iu_val and not ld_q_val and not mmu_q_val_l2 and send_mm_req_l2); + + +with state_trans select + send_if_req_d <= sel_if_req when '1', + send_if_req_l2 when others; + +with state_trans select + send_ld_req_d <= sel_ld_req when '1', + send_ld_req_l2 when others; + +with state_trans select + send_mm_req_d <= sel_mm_req when '1', + send_mm_req_l2 when others; + +latch_send_if_req : tri_rlmreg_p + generic map (width => 1, init => 1, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(send_if_req_offset to send_if_req_offset), + scout => sov(send_if_req_offset to send_if_req_offset), + din(0) => send_if_req_d, + dout(0) => send_if_req_l2); + +latch_send_ld_req : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(send_ld_req_offset to send_ld_req_offset), + scout => sov(send_ld_req_offset to send_ld_req_offset), + din(0) => send_ld_req_d, + dout(0) => send_ld_req_l2); + +latch_send_mm_req : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(send_mm_req_offset to send_mm_req_offset), + scout => sov(send_mm_req_offset to send_mm_req_offset), + din(0) => send_mm_req_d, + dout(0) => send_mm_req_l2); + +--************************************************************************************************************ +--************************************************************************************************************ +-- END: INSTRUCTION FETCH QUEUE SELECT LOGIC +--************************************************************************************************************ +--************************************************************************************************************ + +--************************************************************************************************************ +--************************************************************************************************************ +-- Reload Operation +--************************************************************************************************************ +--************************************************************************************************************ +-- reload is complete when all the data has been stored into the cache array +-- different number of beats of data are given depending if cache inhibit or +-- cache enabled +-- +-- ex. cache inhibit load +-- __ __ __ __ __ __ __ __ __ __ __ __ __ +-- clk | |__| |__| |__| |__| |__| |__| |__| |__| |__| |__| |__| |__| | +-- +-- rel_val ____________________________________________________________________________ +-- +-- rel_data_val ____________________________________________________________________________ +-- _____ +-- rel_upd_gpr ____________| |_________________________________________________________ +-- +-- rel_data XXXXXXXXXXXX|Beat0|XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- +-- ex. cache enabled load +-- __ __ __ __ __ __ __ __ __ __ __ __ __ +-- clk | |__| |__| |__| |__| |__| |__| |__| |__| |__| |__| |__| |__| | +-- _____ +-- rel_val ______| |_______________________________________________________________ +-- _______________________ +-- rel_data_val ____________| |_______________________________________ +-- _____ +-- rel_upd_gpr ____________| |_________________________________________________________ +-- +-- rel_data XXXXXXXXXXXX|Beat0|Beat1|Beat2|Beat3|XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- +-- ex. cache enabled DCBT/DCBTST +-- __ __ __ __ __ __ __ __ __ __ __ __ __ +-- clk | |__| |__| |__| |__| |__| |__| |__| |__| |__| |__| |__| |__| | +-- _____ +-- rel_val ______| |_______________________________________________________________ +-- _______________________ +-- rel_data_val ____________| |_______________________________________ +-- +-- rel_upd_gpr ____________________________________________________________________________ +-- +-- rel_data XXXXXXXXXXXX|Beat0|Beat1|Beat2|Beat3|XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +--****************************************************** +-- Reload Operation +--****************************************************** + +-- latch reload valid and tag to be active the cycle of the data + +latch_reld_data_vld : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(reld_data_vld_offset to reld_data_vld_offset), + scout => sov(reld_data_vld_offset to reld_data_vld_offset), + din(0) => data_val_dminus1_l2, + dout(0) => reld_data_vld_l2); + +latch_rel_tag : tri_rlmreg_p + generic map (width => rel_tag_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dminus1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(rel_tag_offset to rel_tag_offset + rel_tag_l2'length-1), + scout => sov(rel_tag_offset to rel_tag_offset + rel_tag_l2'length-1), + din => tag_dminus1_l2, + dout => rel_tag_l2 ); + + +-- latch reload valid and tag to be active the cycle after the data (when ecc errors are signaled) + +latch_reld_data_vld_dplus1 : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(reld_data_vld_dplus1_offset to reld_data_vld_dplus1_offset), + scout => sov(reld_data_vld_dplus1_offset to reld_data_vld_dplus1_offset), + din(0) => reld_data_vld_l2, + dout(0) => reld_data_vld_dplus1_l2); + +dplus1_act <= reld_data_vld_l2 or clkg_ctl_override_q; + +latch_rel_tag_dplus1 : tri_rlmreg_p + generic map (width => rel_tag_dplus1_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dplus1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(rel_tag_dplus1_offset to rel_tag_dplus1_offset + rel_tag_dplus1_l2'length-1), + scout => sov(rel_tag_dplus1_offset to rel_tag_dplus1_offset + rel_tag_dplus1_l2'length-1), + din => rel_tag_l2, + dout => rel_tag_dplus1_l2); + + + +rel_entry_gen: for i in 0 to lmq_entries-1 generate begin + rel_entry(i) <= l_m_queue(i)(0) & -- (0) cache inhibit + l_m_queue(i)(7 to 12) & -- (1:6) op_size + l_m_queue(i)(13 to 17) & -- (7:11) rot_sel + l_m_queue(i)(18 to 21) & -- (12:15) thread id + l_m_queue(i)(27 to 35) & -- (16:24) target_gpr + l_m_queue(i)(36) & -- (25) ex3_axu_op_val + l_m_queue(i)(37) & -- (26) le_mode + l_m_queue(i)(38) & -- (27) upd_gpr(dcbt) + l_m_queue(i)(47) & -- (28) algebraic op + (l_m_queue(i)(48) or lmq_drop_rel_l2(i)) & -- (29) L2 only mode + l_m_queue(i)(49) & -- (30) way lock enable + l_m_queue(i)(50 to 51) & -- (31) way lock table select bit +-- l_m_queue(i)(52) & -- (33) dvc1 +-- l_m_queue(i)(53) & -- (34) dvc2 + l_m_queue(i)(52); -- (33) watch enable +-- l_m_queue(i)((54) to (54+real_data_add-4-1)); -- (34:xx) real address + + rel_tag_1hot(i) <= tag_dminus1_1hot_l2(i); + + cmp_rel_tag_1hot(i) <= rel_tag_1hot(i); + + rel_data_val(i) <= data_val_dminus1_l2 and rel_tag_1hot(i); + + start_rel(i) <= rel_data_val(i) and not l_m_rel_inprog_l2(i); + + + + + + + + rel_data_val_dplus1(i) <= reld_data_vld_dplus1_l2 and (rel_tag_dplus1_l2(1 to 4) = tconv(i, 4)) and rel_intf_v_dplus1_l2; + + set_data_ecc_err(i) <= beat_ecc_err and rel_data_val_dplus1(i); + + data_ecc_err_d(i) <= set_data_ecc_err(i) or + (not ld_m_rel_done_dly2_l2(i) and data_ecc_err_l2(i) ); + + set_data_ecc_ue(i) <= anaclat_ecc_err_ue and rel_data_val_dplus1(i); + + data_ecc_ue_d(i) <= set_data_ecc_ue(i) or + (not ld_m_rel_done_dly2_l2(i) and data_ecc_ue_l2(i) ); + +end generate; + + +latch_data_ecc_err : tri_rlmreg_p + generic map (width => data_ecc_err_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(data_ecc_err_offset to data_ecc_err_offset + data_ecc_err_l2'length-1), + scout => sov(data_ecc_err_offset to data_ecc_err_offset + data_ecc_err_l2'length-1), + din => data_ecc_err_d, + dout => data_ecc_err_l2 ); + +latch_data_ecc_ue : tri_rlmreg_p + generic map (width => data_ecc_ue_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(data_ecc_ue_offset to data_ecc_ue_offset + data_ecc_ue_l2'length-1), + scout => sov(data_ecc_ue_offset to data_ecc_ue_offset + data_ecc_ue_l2'length-1), + din => data_ecc_ue_d, + dout => data_ecc_ue_l2 ); + + + + + +q4: if lmq_entries=4 generate begin + with tag_dminus1_l2(1 to 4) select + rel_q_entry <= rel_entry(0) when "0000", + rel_entry(1) when "0001", + rel_entry(2) when "0010", + rel_entry(3) when "0011", + (others => '0') when others; + with tag_dminus1_l2(1 to 4) select + rel_q_addrlo_58 <= l_m_queue_addrlo(0)(58) when "0000", + l_m_queue_addrlo(1)(58) when "0001", + l_m_queue_addrlo(2)(58) when "0010", + l_m_queue_addrlo(3)(58) when "0011", + '0' when others; + + with tag_dminus1_l2(1 to 4) select + rel_dvc1_d <= lmq_dvc1_en_l2(0) when "0000", + lmq_dvc1_en_l2(1) when "0001", + lmq_dvc1_en_l2(2) when "0010", + lmq_dvc1_en_l2(3) when "0011", + '0' when others; + + with tag_dminus1_l2(1 to 4) select + rel_dvc2_d <= lmq_dvc2_en_l2(0) when "0000", + lmq_dvc2_en_l2(1) when "0001", + lmq_dvc2_en_l2(2) when "0010", + lmq_dvc2_en_l2(3) when "0011", + '0' when others; + +end generate; + +q8: if lmq_entries=8 generate begin + with tag_dminus1_l2(1 to 4) select + rel_q_entry <= rel_entry(0) when "0000", + rel_entry(1) when "0001", + rel_entry(2) when "0010", + rel_entry(3) when "0011", + rel_entry(4) when "0100", + rel_entry(5) when "0101", + rel_entry(6) when "0110", + rel_entry(7) when "0111", + (others => '0') when others; + with tag_dminus1_l2(1 to 4) select + rel_q_addrlo_58 <= l_m_queue_addrlo(0)(58) when "0000", + l_m_queue_addrlo(1)(58) when "0001", + l_m_queue_addrlo(2)(58) when "0010", + l_m_queue_addrlo(3)(58) when "0011", + l_m_queue_addrlo(4)(58) when "0100", + l_m_queue_addrlo(5)(58) when "0101", + l_m_queue_addrlo(6)(58) when "0110", + l_m_queue_addrlo(7)(58) when "0111", + '0' when others; + + with tag_dminus1_l2(1 to 4) select + rel_dvc1_d <= lmq_dvc1_en_l2(0) when "0000", + lmq_dvc1_en_l2(1) when "0001", + lmq_dvc1_en_l2(2) when "0010", + lmq_dvc1_en_l2(3) when "0011", + lmq_dvc1_en_l2(4) when "0100", + lmq_dvc1_en_l2(5) when "0101", + lmq_dvc1_en_l2(6) when "0110", + lmq_dvc1_en_l2(7) when "0111", + '0' when others; + + with tag_dminus1_l2(1 to 4) select + rel_dvc2_d <= lmq_dvc2_en_l2(0) when "0000", + lmq_dvc2_en_l2(1) when "0001", + lmq_dvc2_en_l2(2) when "0010", + lmq_dvc2_en_l2(3) when "0011", + lmq_dvc2_en_l2(4) when "0100", + lmq_dvc2_en_l2(5) when "0101", + lmq_dvc2_en_l2(6) when "0110", + lmq_dvc2_en_l2(7) when "0111", + '0' when others; + +end generate; + +rel_cache_inh_d <= rel_q_entry(0) and data_val_dminus1_l2 and not tag_dminus1_l2(1); +rel_size_d(0 to 5) <= rel_q_entry(1 to 6); +rel_rot_sel_d(0 to 4) <= rel_q_entry(7 to 11); +rel_th_id_d(0 to 3) <= rel_q_entry(12 to 15); +rel_tar_gpr_d(0 to 8) <= rel_q_entry(16 to 24); +rel_vpr_val_d <= rel_q_entry(25); +rel_le_mode_d <= rel_q_entry(26); +rel_dcbt_d <= rel_q_entry(27); +rel_algebraic_d <= rel_q_entry(28); +rel_l2only_d <= rel_q_entry(29) or (dminus1_l1_dump and rel_intf_v_dminus1_l2); +rel_lock_en_d <= rel_q_entry(30); +rel_classid_d <= rel_q_entry(31 to 32); +rel_watch_en_d <= rel_q_entry(33); +rel_addr_d <= cmp_rel_addr & rel_q_addrlo_58; + + + + +rel_beats_gen: for i in 0 to lmq_entries-1 generate begin + + l_m_rel_c_i_beat0_d(i) <= (start_rel(i) and rel_cache_inh_d and rel_size_d(0)) or -- start cache inh 32B reload + (l_m_rel_c_i_beat0_l2(i) and not rel_data_val(i)); -- reset on next data valid + + l_m_rel_c_i_val(i) <= (start_rel(i) and rel_cache_inh_d and not rel_size_d(0)) or -- start cache inh non 32B reload + (l_m_rel_c_i_beat0_l2(i) and rel_data_val(i) ); -- 2nd beat for 32B reloads + + + + + l_m_rel_hit_beat0_d(i) <= (start_rel(i) and not rel_cache_inh_d ) or (l_m_rel_hit_beat0_l2(i) and not rel_data_val(i)); + l_m_rel_hit_beat1_d(i) <= (l_m_rel_hit_beat0_l2(i) and rel_data_val(i) ) or (l_m_rel_hit_beat1_l2(i) and not rel_data_val(i) ); + l_m_rel_hit_beat2_d(i) <= (l_m_rel_hit_beat1_l2(i) and rel_data_val(i) ) or (l_m_rel_hit_beat2_l2(i) and not rel_data_val(i) ) or + (ld_m_rel_done_l2(i) and ldq_recirc_rel_val and not ecc_err(i) and not my_xucr0_cls); + l_m_rel_hit_beat3_d(i) <= (l_m_rel_hit_beat2_l2(i) and rel_data_val(i) ) or (l_m_rel_hit_beat3_l2(i) and not rel_data_val(i) and my_xucr0_cls); + l_m_rel_hit_beat4_d(i) <= (l_m_rel_hit_beat3_l2(i) and rel_data_val(i) and my_xucr0_cls) or (l_m_rel_hit_beat4_l2(i) and not rel_data_val(i) ); + l_m_rel_hit_beat5_d(i) <= (l_m_rel_hit_beat4_l2(i) and rel_data_val(i) ) or (l_m_rel_hit_beat5_l2(i) and not rel_data_val(i) ); + l_m_rel_hit_beat6_d(i) <= (l_m_rel_hit_beat5_l2(i) and rel_data_val(i) ) or (l_m_rel_hit_beat6_l2(i) and not rel_data_val(i) ) or + (ld_m_rel_done_l2(i) and ldq_recirc_rel_val and not ecc_err(i) and my_xucr0_cls); + l_m_rel_hit_beat7_d(i) <= (l_m_rel_hit_beat6_l2(i) and rel_data_val(i) ); + l_m_rel_inprog_d(i) <= l_m_rel_hit_beat0_d(i) or l_m_rel_c_i_beat0_d(i) or + (ld_m_rel_done_l2(i) and ldq_recirc_rel_val and not ecc_err(i)) or + (l_m_rel_inprog_l2(i) and not (l_m_rel_hit_beat3_l2(i) and not my_xucr0_cls) and + not (l_m_rel_hit_beat7_l2(i) and my_xucr0_cls) and + not l_m_rel_val_c_i_dly(i)); -- active through beats 0, 1, 2, and 3 + +end generate; + +latch_rel_hit_beat0 : tri_rlmreg_p + generic map (width => l_m_rel_hit_beat0_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(l_m_rel_hit_beat0_offset to l_m_rel_hit_beat0_offset + l_m_rel_hit_beat0_l2'length-1), + scout => sov(l_m_rel_hit_beat0_offset to l_m_rel_hit_beat0_offset + l_m_rel_hit_beat0_l2'length-1), + din => l_m_rel_hit_beat0_d, + dout => l_m_rel_hit_beat0_l2); +latch_rel_hit_beat1 : tri_rlmreg_p + generic map (width => l_m_rel_hit_beat1_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(l_m_rel_hit_beat1_offset to l_m_rel_hit_beat1_offset + l_m_rel_hit_beat1_l2'length-1), + scout => sov(l_m_rel_hit_beat1_offset to l_m_rel_hit_beat1_offset + l_m_rel_hit_beat1_l2'length-1), + din => l_m_rel_hit_beat1_d, + dout => l_m_rel_hit_beat1_l2); +latch_rel_hit_beat2 : tri_rlmreg_p + generic map (width => l_m_rel_hit_beat2_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(l_m_rel_hit_beat2_offset to l_m_rel_hit_beat2_offset + l_m_rel_hit_beat2_l2'length-1), + scout => sov(l_m_rel_hit_beat2_offset to l_m_rel_hit_beat2_offset + l_m_rel_hit_beat2_l2'length-1), + din => l_m_rel_hit_beat2_d, + dout => l_m_rel_hit_beat2_l2); +latch_rel_hit_beat3 : tri_rlmreg_p + generic map (width => l_m_rel_hit_beat3_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(l_m_rel_hit_beat3_offset to l_m_rel_hit_beat3_offset + l_m_rel_hit_beat3_l2'length-1), + scout => sov(l_m_rel_hit_beat3_offset to l_m_rel_hit_beat3_offset + l_m_rel_hit_beat3_l2'length-1), + din => l_m_rel_hit_beat3_d, + dout => l_m_rel_hit_beat3_l2); + + latch_rel_hit_beat4 : tri_rlmreg_p + generic map (width => l_m_rel_hit_beat4_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(l_m_rel_hit_beat4_offset to l_m_rel_hit_beat4_offset + l_m_rel_hit_beat4_l2'length-1), + scout => sov(l_m_rel_hit_beat4_offset to l_m_rel_hit_beat4_offset + l_m_rel_hit_beat4_l2'length-1), + din => l_m_rel_hit_beat4_d, + dout => l_m_rel_hit_beat4_l2); + latch_rel_hit_beat5 : tri_rlmreg_p + generic map (width => l_m_rel_hit_beat5_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(l_m_rel_hit_beat5_offset to l_m_rel_hit_beat5_offset + l_m_rel_hit_beat5_l2'length-1), + scout => sov(l_m_rel_hit_beat5_offset to l_m_rel_hit_beat5_offset + l_m_rel_hit_beat5_l2'length-1), + din => l_m_rel_hit_beat5_d, + dout => l_m_rel_hit_beat5_l2); + latch_rel_hit_beat6 : tri_rlmreg_p + generic map (width => l_m_rel_hit_beat6_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(l_m_rel_hit_beat6_offset to l_m_rel_hit_beat6_offset + l_m_rel_hit_beat6_l2'length-1), + scout => sov(l_m_rel_hit_beat6_offset to l_m_rel_hit_beat6_offset + l_m_rel_hit_beat6_l2'length-1), + din => l_m_rel_hit_beat6_d, + dout => l_m_rel_hit_beat6_l2); + latch_rel_hit_beat7 : tri_rlmreg_p + generic map (width => l_m_rel_hit_beat7_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(l_m_rel_hit_beat7_offset to l_m_rel_hit_beat7_offset + l_m_rel_hit_beat7_l2'length-1), + scout => sov(l_m_rel_hit_beat7_offset to l_m_rel_hit_beat7_offset + l_m_rel_hit_beat7_l2'length-1), + din => l_m_rel_hit_beat7_d, + dout => l_m_rel_hit_beat7_l2); + +latch_rel_inprog : tri_rlmreg_p + generic map (width => l_m_rel_inprog_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(l_m_rel_inprog_offset to l_m_rel_inprog_offset + l_m_rel_inprog_l2'length-1), + scout => sov(l_m_rel_inprog_offset to l_m_rel_inprog_offset + l_m_rel_inprog_l2'length-1), + din => l_m_rel_inprog_d, + dout => l_m_rel_inprog_l2); + +latch_rel_c_i_beat0 : tri_rlmreg_p + generic map (width => l_m_rel_c_i_beat0_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(l_m_rel_c_i_beat0_offset to l_m_rel_c_i_beat0_offset + l_m_rel_c_i_beat0_l2'length-1), + scout => sov(l_m_rel_c_i_beat0_offset to l_m_rel_c_i_beat0_offset + l_m_rel_c_i_beat0_l2'length-1), + din => l_m_rel_c_i_beat0_d, + dout => l_m_rel_c_i_beat0_l2); + +latch_rel_c_i_val : tri_rlmreg_p + generic map (width => l_m_rel_val_c_i_dly'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(l_m_rel_c_i_val_offset to l_m_rel_c_i_val_offset + l_m_rel_val_c_i_dly'length-1), + scout => sov(l_m_rel_c_i_val_offset to l_m_rel_c_i_val_offset + l_m_rel_val_c_i_dly'length-1), + din => l_m_rel_c_i_val, + dout => l_m_rel_val_c_i_dly); + + + +latch_rel_addr : tri_rlmreg_p + generic map (width => rel_addr_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dminus1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(rel_addr_offset to rel_addr_offset + rel_addr_l2'length-1), + scout => sov(rel_addr_offset to rel_addr_offset + rel_addr_l2'length-1), + din => rel_addr_d, + dout => rel_addr_l2); +latch_rel_cache_inh : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(rel_cache_inh_offset to rel_cache_inh_offset), + scout => sov(rel_cache_inh_offset to rel_cache_inh_offset), + din(0) => rel_cache_inh_d, + dout(0) => rel_cache_inh_l2); +latch_rel_size : tri_rlmreg_p + generic map (width => rel_size_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dminus1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(rel_size_offset to rel_size_offset + rel_size_l2'length-1), + scout => sov(rel_size_offset to rel_size_offset + rel_size_l2'length-1), + din => rel_size_d, + dout => rel_size_l2); +latch_rel_rot_sel : tri_rlmreg_p + generic map (width => rel_rot_sel_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dminus1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(rel_rot_sel_offset to rel_rot_sel_offset + rel_rot_sel_l2'length-1), + scout => sov(rel_rot_sel_offset to rel_rot_sel_offset + rel_rot_sel_l2'length-1), + din => rel_rot_sel_d, + dout => rel_rot_sel_l2); +latch_rel_th_id : tri_rlmreg_p + generic map (width => rel_th_id_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dminus1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(rel_th_id_offset to rel_th_id_offset + rel_th_id_l2'length-1), + scout => sov(rel_th_id_offset to rel_th_id_offset + rel_th_id_l2'length-1), + din => rel_th_id_d, + dout => rel_th_id_l2); +latch_rel_tar_gpr : tri_rlmreg_p + generic map (width => rel_tar_gpr_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dminus1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(rel_tar_gpr_offset to rel_tar_gpr_offset + rel_tar_gpr_l2'length-1), + scout => sov(rel_tar_gpr_offset to rel_tar_gpr_offset + rel_tar_gpr_l2'length-1), + din => rel_tar_gpr_d, + dout => rel_tar_gpr_l2); +latch_rel_vpr_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dminus1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(rel_vpr_val_offset to rel_vpr_val_offset), + scout => sov(rel_vpr_val_offset to rel_vpr_val_offset), + din(0) => rel_vpr_val_d, + dout(0) => rel_vpr_val_l2); +latch_rel_le_mode : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(rel_le_mode_offset to rel_le_mode_offset), + scout => sov(rel_le_mode_offset to rel_le_mode_offset), + din(0) => rel_le_mode_d, + dout(0) => rel_le_mode_l2); +latch_rel_dcbt : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dminus1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(rel_dcbt_offset to rel_dcbt_offset), + scout => sov(rel_dcbt_offset to rel_dcbt_offset), + din(0) => rel_dcbt_d, + dout(0) => rel_dcbt_l2); +latch_rel_algebraic : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dminus1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(rel_algebraic_offset to rel_algebraic_offset), + scout => sov(rel_algebraic_offset to rel_algebraic_offset), + din(0) => rel_algebraic_d, + dout(0) => rel_algebraic_l2); +latch_rel_l2only : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dminus1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(rel_l2only_offset to rel_l2only_offset), + scout => sov(rel_l2only_offset to rel_l2only_offset), + din(0) => rel_l2only_d, + dout(0) => rel_l2only_l2); +latch_rel_l2only_dly : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(rel_l2only_dly_offset to rel_l2only_dly_offset), + scout => sov(rel_l2only_dly_offset to rel_l2only_dly_offset), + din(0) => rel_l2only_l2, + dout(0) => rel_l2only_dly_l2); +latch_rel_lock_en : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dminus1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(rel_lock_en_offset to rel_lock_en_offset), + scout => sov(rel_lock_en_offset to rel_lock_en_offset), + din(0) => rel_lock_en_d, + dout(0) => rel_lock_en_l2); +latch_rel_classid : tri_rlmreg_p + generic map (width => rel_classid_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dminus1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(rel_classid_offset to rel_classid_offset + rel_classid_l2'length-1), + scout => sov(rel_classid_offset to rel_classid_offset + rel_classid_l2'length-1), + din => rel_classid_d, + dout => rel_classid_l2); +latch_rel_dvc1 : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dminus1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(rel_dvc1_offset to rel_dvc1_offset), + scout => sov(rel_dvc1_offset to rel_dvc1_offset), + din(0) => rel_dvc1_d, + dout(0) => rel_dvc1_l2); +latch_rel_dvc2 : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dminus1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(rel_dvc2_offset to rel_dvc2_offset), + scout => sov(rel_dvc2_offset to rel_dvc2_offset), + din(0) => rel_dvc2_d, + dout(0) => rel_dvc2_l2); +latch_rel_watch_en : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dminus1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(rel_watch_en_offset to rel_watch_en_offset), + scout => sov(rel_watch_en_offset to rel_watch_en_offset), + din(0) => rel_watch_en_d, + dout(0) => rel_watch_en_l2); + +---------------------------------------------- +---- Reload Complete pulse +---------------------------------------------- +---- Reload is complete +---- 1) cacheable reload is complete +---- 2) uncacheable reload is complete +---- Reload Complete pulse + +rel_done_g: for i in 0 to lmq_entries-1 generate begin + ld_m_rel_done_d(i) <= (l_m_rel_hit_beat3_l2(i) and not my_xucr0_cls) or + (l_m_rel_hit_beat7_l2(i) and my_xucr0_cls) or + l_m_rel_val_c_i_dly(i); + + ldq_retry_d(i) <= (ld_m_rel_done_l2(i) and ldq_recirc_rel_val and not ecc_err(i)) or + (ldq_retry_l2(i) and not ld_m_rel_done_l2(i)); +end generate; + + +latch_ld_m_rel_done : tri_rlmreg_p + generic map (width => ld_m_rel_done_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ld_m_rel_done_offset to ld_m_rel_done_offset + ld_m_rel_done_l2'length-1), + scout => sov(ld_m_rel_done_offset to ld_m_rel_done_offset + ld_m_rel_done_l2'length-1), + din => ld_m_rel_done_d(0 to lmq_entries-1), + dout => ld_m_rel_done_l2(0 to lmq_entries-1)); + +ld_m_rel_done_no_retry <= not gate_and(ldq_recirc_rel_val, not ecc_err) and ld_m_rel_done_l2; + +latch_ldq_retry : tri_rlmreg_p + generic map (width => ldq_retry_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ldq_retry_offset to ldq_retry_offset + ldq_retry_l2'length-1), + scout => sov(ldq_retry_offset to ldq_retry_offset + ldq_retry_l2'length-1), + din => ldq_retry_d(0 to lmq_entries-1), + dout => ldq_retry_l2(0 to lmq_entries-1)); + +latch_ld_m_rel_done_dly : tri_rlmreg_p + generic map (width => ld_m_rel_done_dly_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ld_m_rel_done_dly_offset to ld_m_rel_done_dly_offset + ld_m_rel_done_dly_l2'length-1), + scout => sov(ld_m_rel_done_dly_offset to ld_m_rel_done_dly_offset + ld_m_rel_done_dly_l2'length-1), + din => ld_m_rel_done_no_retry(0 to lmq_entries-1), + dout => ld_m_rel_done_dly_l2(0 to lmq_entries-1)); + +latch_ld_m_rel_done_dly2 : tri_rlmreg_p + generic map (width => ld_m_rel_done_dly2_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ld_m_rel_done_dly2_offset to ld_m_rel_done_dly2_offset + ld_m_rel_done_dly2_l2'length-1), + scout => sov(ld_m_rel_done_dly2_offset to ld_m_rel_done_dly2_offset + ld_m_rel_done_dly2_l2'length-1), + din => ld_m_rel_done_dly_l2(0 to lmq_entries-1), + dout => ld_m_rel_done_dly2_l2(0 to lmq_entries-1)); + +reset_lmq_gen: for i in 0 to lmq_entries-1 generate begin + reset_lmq_entry_rel(i) <= ld_m_rel_done_dly2_l2(i) and not data_ecc_err_l2(i); +end generate; + +--************************************************************************************************************ +--************************************************************************************************************ +-- END: Reload Operation +--************************************************************************************************************ +--************************************************************************************************************ + + +any_ld_val_p: process (ld_entry_val_l2) + variable b: std_ulogic; +begin + b := '0'; + for i in 0 to lmq_entries-1 loop + b := ld_entry_val_l2(i) or b; + end loop; + any_ld_entry_val <= b; +end process; + + + + +blk_ld_for_pe_recov_d <= ex7_ld_par_err or + (blk_ld_for_pe_recov_l2 and not pe_recov_begin); +latch_blk_ld_for_pe_recov : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(blk_ld_for_pe_recov_offset to blk_ld_for_pe_recov_offset), + scout => sov(blk_ld_for_pe_recov_offset to blk_ld_for_pe_recov_offset), + din(0) => blk_ld_for_pe_recov_d, + dout(0) => blk_ld_for_pe_recov_l2 ); + +lq_rd_en_gen: for i in 0 to lmq_entries-1 generate begin + + ldq_rd_seq_match_curr(i) <= l_m_queue(i)(22 to 26) = cmd_seq_rd_l2(0 to 4); + ldq_rd_seq_match_next(i) <= l_m_queue(i)(22 to 26) = cmd_seq_rd_incr(0 to 4); + + l_q_rd_en(i) <= ldq_rd_seq_match_l2(i) and ld_entry_val_l2(i) and not l_m_q_hit_st_l2(i) and not ex7_ld_par_err and not blk_ld_for_pe_recov_l2; + rd_seq_hit(i) <= ldq_rd_seq_match_l2(i) and ld_entry_val_l2(i); +end generate; + +cmp_l_q_rd_en <= l_q_rd_en; + +cmd_seq_rd_incr_val <= load_sent or selected_entry_flushed or rd_seq_num_skip; + +with cmd_seq_rd_incr_val select + ldq_rd_seq_match_d <= ldq_rd_seq_match_next when '1', + ldq_rd_seq_match_curr when others; + +latch_ldq_rd_seq_match : tri_rlmreg_p + generic map (width => ldq_rd_seq_match_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ldq_rd_seq_match_offset to ldq_rd_seq_match_offset + ldq_rd_seq_match_l2'length-1), + scout => sov(ldq_rd_seq_match_offset to ldq_rd_seq_match_offset + ldq_rd_seq_match_l2'length-1), + din => ldq_rd_seq_match_d(0 to lmq_entries-1), + dout => ldq_rd_seq_match_l2(0 to lmq_entries-1)); + +selected_ld_val_p: process (l_q_rd_en, rd_seq_hit) + variable b,c : std_ulogic; +begin + b := '0'; + c := '0'; + for i in 0 to lmq_entries-1 loop + b := l_q_rd_en(i) or b; + c := rd_seq_hit(i) or c; + end loop; + selected_ld_entry_val <= b; + rd_seq_num_exits <= c; +end process; + +rd_seq_num_skip <= any_ld_entry_val and not rd_seq_num_exits; + + + +q4_lmentry: if lmq_entries=4 generate begin + l_miss_entry <= gate_and(l_q_rd_en(0), l_m_queue(0)) or + gate_and(l_q_rd_en(1), l_m_queue(1)) or + gate_and(l_q_rd_en(2), l_m_queue(2)) or + gate_and(l_q_rd_en(3), l_m_queue(3)); + l_miss_addrlo <= gate_and(l_q_rd_en(0), l_m_queue_addrlo(0)(58 to 63)) or + gate_and(l_q_rd_en(1), l_m_queue_addrlo(1)(58 to 63)) or + gate_and(l_q_rd_en(2), l_m_queue_addrlo(2)(58 to 63)) or + gate_and(l_q_rd_en(3), l_m_queue_addrlo(3)(58 to 63)); + + lq_rd_en_is_ex5 <= (rd_seq_hit(0) and ex5_loadmiss_qentry(0)) or + (rd_seq_hit(1) and ex5_loadmiss_qentry(1)) or + (rd_seq_hit(2) and ex5_loadmiss_qentry(2)) or + (rd_seq_hit(3) and ex5_loadmiss_qentry(3)); + lq_rd_en_is_ex6 <= (rd_seq_hit(0) and ex6_loadmiss_qentry(0)) or + (rd_seq_hit(1) and ex6_loadmiss_qentry(1)) or + (rd_seq_hit(2) and ex6_loadmiss_qentry(2)) or + (rd_seq_hit(3) and ex6_loadmiss_qentry(3)); +end generate; + +q8_lmentry: if lmq_entries=8 generate begin + l_miss_entry <= gate_and(l_q_rd_en(0), l_m_queue(0)) or + gate_and(l_q_rd_en(1), l_m_queue(1)) or + gate_and(l_q_rd_en(2), l_m_queue(2)) or + gate_and(l_q_rd_en(3), l_m_queue(3)) or + gate_and(l_q_rd_en(4), l_m_queue(4)) or + gate_and(l_q_rd_en(5), l_m_queue(5)) or + gate_and(l_q_rd_en(6), l_m_queue(6)) or + gate_and(l_q_rd_en(7), l_m_queue(7)); + l_miss_addrlo <= gate_and(l_q_rd_en(0), l_m_queue_addrlo(0)(58 to 63)) or + gate_and(l_q_rd_en(1), l_m_queue_addrlo(1)(58 to 63)) or + gate_and(l_q_rd_en(2), l_m_queue_addrlo(2)(58 to 63)) or + gate_and(l_q_rd_en(3), l_m_queue_addrlo(3)(58 to 63)) or + gate_and(l_q_rd_en(4), l_m_queue_addrlo(4)(58 to 63)) or + gate_and(l_q_rd_en(5), l_m_queue_addrlo(5)(58 to 63)) or + gate_and(l_q_rd_en(6), l_m_queue_addrlo(6)(58 to 63)) or + gate_and(l_q_rd_en(7), l_m_queue_addrlo(7)(58 to 63)); + + lq_rd_en_is_ex5 <= (rd_seq_hit(0) and ex5_loadmiss_qentry(0)) or + (rd_seq_hit(1) and ex5_loadmiss_qentry(1)) or + (rd_seq_hit(2) and ex5_loadmiss_qentry(2)) or + (rd_seq_hit(3) and ex5_loadmiss_qentry(3)) or + (rd_seq_hit(4) and ex5_loadmiss_qentry(4)) or + (rd_seq_hit(5) and ex5_loadmiss_qentry(5)) or + (rd_seq_hit(6) and ex5_loadmiss_qentry(6)) or + (rd_seq_hit(7) and ex5_loadmiss_qentry(7)); + lq_rd_en_is_ex6 <= (rd_seq_hit(0) and ex6_loadmiss_qentry(0)) or + (rd_seq_hit(1) and ex6_loadmiss_qentry(1)) or + (rd_seq_hit(2) and ex6_loadmiss_qentry(2)) or + (rd_seq_hit(3) and ex6_loadmiss_qentry(3)) or + (rd_seq_hit(4) and ex6_loadmiss_qentry(4)) or + (rd_seq_hit(5) and ex6_loadmiss_qentry(5)) or + (rd_seq_hit(6) and ex6_loadmiss_qentry(6)) or + (rd_seq_hit(7) and ex6_loadmiss_qentry(7)); +end generate; + +-- above logic could be replaced with this process if you want a more general and elegant (but harder to read) version +--lmentry_p: process (l_q_rd_en, l_m_queue) +-- variable b: std_ulogic_vector(0 to (69+(real_data_add-1))); +--begin +-- b := (others => '0'); +-- for i in 0 to lmq_entries-1 loop +-- b := gate_and(l_q_rd_en(i), l_m_queue(i)) or b; +-- end loop; +-- l_miss_entry <= b; +--end process; + + +--****************************************************** +-- Setting up Instruction Fetch +--****************************************************** +-- Need to match ld/st Q entry that is sent to L2 +iu_f_entry(0 to 5) <= "000000"; -- ctype +iu_f_entry(6 to 37) <= x"00000000"; -- byte enables +iu_f_entry(38 to 41) <= iu_f_q0_sel & iu_f_q1_sel & iu_f_q2_sel & iu_f_q3_sel; -- thread_id +iu_f_entry(42 to 46) <= iu_f_sel_entry(0 to 4); -- wimge +iu_f_entry(47 to 49) <= "110"; -- transfer length + +iu_f_entry(50 to 53) <= iu_f_sel_entry(5 to 8); -- user defined bits +iu_f_entry(54 to (54+real_data_add-1)) <= iu_f_sel_entry(9 to (9+REAL_IFAR_length-1)) & "0000"; -- real address + +iu_thrd(0) <= iu_f_q2_sel or iu_f_q3_sel; +iu_thrd(1) <= iu_f_q1_sel or iu_f_q3_sel; + +--****************************************************** +-- Setting up ld request +--****************************************************** +ldmq_entry(0 to 5) <= l_miss_entry(1 to 6); -- ctype +ldmq_entry(6 to 37) <= x"00000000"; -- byte enables +ldmq_entry(38 to 41) <= l_miss_entry(18 to 21); -- thread_id +ldmq_entry(42 to 45) <= l_miss_entry(39 to 42); -- wimg +ldmq_entry(46) <= l_miss_entry(53); -- Little Endian +--ldmq_entry(47 to 49) <= "011" when l_miss_entry(0) = '0' else -- transfer length: full cache line +ldmq_entry(47 to 49) <= "001" when l_miss_entry(12) = '1' else -- 1 byte + "010" when l_miss_entry(11) = '1' else -- 2 bytes + "100" when l_miss_entry(10) = '1' else -- 4 bytes + "101" when l_miss_entry(9) = '1' else -- 8 bytes + "110" when l_miss_entry(8) = '1' else -- 16 bytes + "111" when l_miss_entry(7) = '1' else -- 32 bytes + "000"; +ldmq_entry(50 to 53) <= l_miss_entry(43 to 46); -- user defined bits +--ldmq_entry(54 to (54+real_data_add-1)) <= l_miss_entry(54 to (54+real_data_add-1)); -- real address +ldmq_entry(54 to (54+real_data_add-1)) <= cmp_l_miss_entry_addr & l_miss_addrlo; -- real address + +--****************************************************** +-- Setting up mmu request +--****************************************************** +with mmu_q_entry_l2(0 to 1) select -- ctype + mmuq_req(0 to 5) <= "111100" when "00", -- TLBIVAX + "111011" when "01", -- TBLI Complete + "000010" when "10", -- mmu load (tag=01100) + "000010" when others; -- mmu load (tag=01101) + +mmuq_req(6 to 37) <= x"00000000"; -- byte enables +mmuq_req(38 to 41) <= mmu_q_entry_l2(2 to 5); -- thread_id +mmuq_req(42 to 45) <= mmu_q_entry_l2(6 to 9); -- wimg +mmuq_req(46) <= mmu_q_entry_l2(10); -- Little Endian +mmuq_req(47 to 49) <= "000"; -- transfer length +mmuq_req(50 to 53) <= mmu_q_entry_l2(11 to 14); -- user defined bits +mmuq_req(54 to (54+real_data_add-1)) <= mmu_q_entry_l2(26 to (26+real_data_add-1)); -- real address + + +iu_mmu_entry <= gate_and(send_if_req_l2, iu_f_entry) or + gate_and(send_mm_req_l2, mmuq_req); + +ld_tag(1 to 4) <= gate_and(send_if_req_l2, "10" & iu_thrd) or + gate_and(send_ld_req_l2, '0' & l_m_tag) or + gate_and(send_mm_req_l2, "110" & mmu_q_entry_l2(1) ); + +--****************************************************** +-- Setting up store request +--****************************************************** +store_entry(0 to 5) <= s_m_queue0(0 to 5); -- ctype +store_entry(6 to 37) <= s_m_queue0(6 to 37); -- byte enables +store_entry(38 to 41) <= s_m_queue0(38 to 41); -- thread_id +store_entry(42 to 45) <= s_m_queue0(43 to 46); -- wimg +store_entry(46) <= s_m_queue0(42); -- Little Endian +store_entry(47 to 49) <= "001" when s_m_queue0(56) = '1' else -- transfer length 1 byte + "010" when s_m_queue0(55) = '1' else -- 2 bytes + "100" when s_m_queue0(54) = '1' else -- 4 bytes + "101" when s_m_queue0(53) = '1' else -- 8 bytes + "110" when s_m_queue0(52) = '1' else -- 16 bytes + "111" when s_m_queue0(51) = '1' else -- 32 bytes + "000"; +store_entry(50 to 53) <= s_m_queue0(47 to 50); -- user defined bits +store_entry(54 to (54+real_data_add-1)) <= s_m_queue0(58 to (58+real_data_add-1)); -- real address + + +--****************************************************** +-- Store requests from Boxes +--****************************************************** +latch_ob_pwr_tok : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_pwr_tok_offset to ob_pwr_tok_offset), + scout => sov(ob_pwr_tok_offset to ob_pwr_tok_offset), + din(0) => bx_lsu_ob_pwr_tok, + dout(0) => ob_pwr_tok_l2 ); + +ob_act <= ob_pwr_tok_l2 or ob_req_val_l2 or ob_ditc_val_l2 or clkg_ctl_override_q; + +ob_req_val_mux <= ob_req_val_l2 when bx_cmd_stall_d='1' else + bx_lsu_ob_req_val and not bx_stall_dly_or; +latch_ob_req_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_req_val_offset to ob_req_val_offset), + scout => sov(ob_req_val_offset to ob_req_val_offset), + din(0) => ob_req_val_mux, + dout(0) => ob_req_val_l2 ); +latch_ob_req_val_clone : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_req_val_clone_offset to ob_req_val_clone_offset), + scout => sov(ob_req_val_clone_offset to ob_req_val_clone_offset), + din(0) => ob_req_val_mux, + dout(0) => ob_req_val_clone_l2 ); + +ob_ditc_val_mux <= ob_ditc_val_l2 when bx_cmd_stall_d='1' else + bx_lsu_ob_ditc_val and not bx_stall_dly_or; +latch_ob_ditc_val : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_ditc_val_offset to ob_ditc_val_offset), + scout => sov(ob_ditc_val_offset to ob_ditc_val_offset), + din(0) => ob_ditc_val_mux, + dout(0) => ob_ditc_val_l2 ); +latch_ob_ditc_val_clone : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_ditc_val_clone_offset to ob_ditc_val_clone_offset), + scout => sov(ob_ditc_val_clone_offset to ob_ditc_val_clone_offset), + din(0) => ob_ditc_val_mux, + dout(0) => ob_ditc_val_clone_l2 ); + +lsu_bx_cmd_avail <= not (ob_req_val_l2 or ob_ditc_val_l2); + +ob_thrd_mux <= ob_thrd_l2 when bx_cmd_stall_d='1' else + bx_lsu_ob_thrd; +latch_ob_thrd : tri_rlmreg_p + generic map (width => ob_thrd_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_thrd_offset to ob_thrd_offset + ob_thrd_l2'length-1), + scout => sov(ob_thrd_offset to ob_thrd_offset + ob_thrd_l2'length-1), + din => ob_thrd_mux, + dout => ob_thrd_l2 ); + +ob_qw_mux <= ob_qw_l2 when bx_cmd_stall_d='1' else + bx_lsu_ob_qw; +latch_ob_qw : tri_rlmreg_p + generic map (width => ob_qw_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_qw_offset to ob_qw_offset + ob_qw_l2'length-1), + scout => sov(ob_qw_offset to ob_qw_offset + ob_qw_l2'length-1), + din => ob_qw_mux, + dout => ob_qw_l2 ); + +ob_dest_mux <= ob_dest_l2 when bx_cmd_stall_d='1' else + bx_lsu_ob_dest; +latch_ob_dest : tri_rlmreg_p + generic map (width => ob_dest_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_dest_offset to ob_dest_offset + ob_dest_l2'length-1), + scout => sov(ob_dest_offset to ob_dest_offset + ob_dest_l2'length-1), + din => ob_dest_mux, + dout => ob_dest_l2 ); + +ob_addr_mux <= ob_addr_l2 when bx_cmd_stall_d='1' else + bx_lsu_ob_addr; +latch_ob_addr : tri_rlmreg_p + generic map (width => ob_addr_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_addr_offset to ob_addr_offset + ob_addr_l2'length-1), + scout => sov(ob_addr_offset to ob_addr_offset + ob_addr_l2'length-1), + din => ob_addr_mux, + dout => ob_addr_l2 ); + +ob_data_mux <= ob_data_l2 when bx_cmd_stall_d='1' else + bx_lsu_ob_data; +latch_ob_data : tri_rlmreg_p + generic map (width => ob_data_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ob_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ob_data_offset to ob_data_offset + ob_data_l2'length-1), + scout => sov(ob_data_offset to ob_data_offset + ob_data_l2'length-1), + din => ob_data_mux, + dout => ob_data_l2 ); + +ob_store(0 to 5) <= "100000" when ob_req_val_l2='1' else -- ctype for store + "100010"; -- ctype for ditc + +ob_store(6 to 37) <= x"00000000" when ob_ditc_val_l2='1' else -- byte enables + x"FFFF0000" when ob_qw_l2(59)='0' else + x"0000FFFF"; +ob_store(38) <= ob_thrd_l2(0 to 1)="00"; -- thread_id +ob_store(39) <= ob_thrd_l2(0 to 1)="01"; -- thread_id +ob_store(40) <= ob_thrd_l2(0 to 1)="10"; -- thread_id +ob_store(41) <= ob_thrd_l2(0 to 1)="11"; -- thread_id +ob_store(42 to 45) <= "1010"; -- wimg +ob_store(46) <= '0'; -- Little Endian +ob_store(47 to 49) <= "110"; -- len = 16 bytes +ob_store(50 to 53) <= "0000"; -- user defined bits +ob_store(54 to (54+real_data_add-7)) <= ob_addr_l2; -- real address +ob_store((54+real_data_add-6) to (54+real_data_add-5)) <= ob_qw_l2(58 to 59); +ob_store((54+real_data_add-4) to (54+real_data_add-1)) <= "0000"; + + +st_req <= st_recycle_l2 when st_recycle_v_l2='1' else + store_entry when st_entry0_val_l2='1' else + ob_store; + +ld_st_request <= st_req when (ex5_sel_st_req or ((ob_req_val_l2 or ob_ditc_val_l2 or st_recycle_v_l2) and store_credit)) = '1' else + ldmq_entry when send_ld_req_l2 = '1' else + iu_mmu_entry; + + +cred_pop <= anaclat_st_pop or anaclat_st_gather or (my_xucr0_cred and anaclat_ld_pop) or blk_st_cred_pop; +ex4_sel_st_req <= ( ( (ex4_st_val_l2 and not ex4_flush_store) and + ( (store_credit and not one_st_cred ) or + (one_st_cred and not nxt_st_cred_tkn) or + (one_st_cred and nxt_st_cred_tkn and cred_pop) or + (not store_credit and not st_entry0_val_l2 and cred_pop) ) ) or + (st_entry0_val_l2 and not (ex5_flush_store and ex5_st_val_l2) and (store_credit or cred_pop)) ); + +latch_ex5_sel_st_req : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => stq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex5_sel_st_req_offset to ex5_sel_st_req_offset), + scout => sov(ex5_sel_st_req_offset to ex5_sel_st_req_offset), + din(0) => ex4_sel_st_req, + dout(0) => ex5_sel_st_req ); + + +store_sent <= (st_entry0_val_l2 and store_credit and not (ex5_flush_store and ex5_st_val_l2) and ex5_sel_st_req) or + ((ob_req_val_l2 or ob_ditc_val_l2) and store_credit and not st_entry0_val_l2 and not st_recycle_v_l2 and not (l2req_resend_l2 and ex7_ld_par_err)) or + (st_recycle_v_l2 and store_credit); + + +load_sent <= not ex5_sel_st_req and send_ld_req_l2 and load_credit and selected_ld_entry_val and + not (lq_rd_en_is_ex5 and ex5_flush_load_local) and + not (lq_rd_en_is_ex6 and ex6_flush_l2) and + not ((ob_req_val_l2 or ob_ditc_val_l2 or st_recycle_v_l2) and store_credit); + +load_flushed <= send_ld_req_l2 and selected_ld_entry_val and + ((lq_rd_en_is_ex5 and ex5_flush_load_local) or (lq_rd_en_is_ex6 and ex6_flush_l2)); + +selected_entry_flushed <= selected_ld_entry_val and + ((lq_rd_en_is_ex5 and ex5_flush_load_local) or (lq_rd_en_is_ex6 and ex6_flush_l2)); + +mmu_st_sent <= store_credit and not st_entry0_val_l2 and not ob_req_val_l2 and not ob_ditc_val_l2 and + send_mm_req_l2 and mmu_q_val and not mmu_q_entry_l2(0) and not (l2req_resend_l2 and ex7_ld_par_err) and + not ex5_sel_st_req and not st_recycle_v_l2; + + +mmu_ld_sent <= load_credit and not ex5_sel_st_req and send_mm_req_l2 and mmu_q_val and mmu_q_entry_l2(0) and + not (l2req_resend_l2 and ex7_ld_par_err) and + not ((ob_req_val_l2 or ob_ditc_val_l2 or st_recycle_v_l2) and store_credit); +mmu_sent <= mmu_st_sent or mmu_ld_sent or (l2req_resend_l2 and ex7_ld_par_err and mmu_sent_l2); + +-- resend or recycle the L2 request if it will be blocked by a load data parity error (resend goes back on the L2 +-- interface the next cycle and recycle will go back to the store queue). + +l2req_resend_d <= mmu_sent or bx_cmd_sent_d or iu_sent_val or + (load_sent and not lq_rd_en_is_ex5 and not (ex5_flush_load_all and lq_rd_en_is_ex5)) or + (l2req_resend_l2 and ex7_ld_par_err); +l2req_recycle_d <= store_sent and not (ob_req_val_l2 or ob_ditc_val_l2); + + + +bx_cmd_sent_d <= (ob_req_val_l2 or ob_ditc_val_l2) and store_credit and + not (st_entry0_val_l2 ) and not st_recycle_v_l2 and + not (l2req_resend_l2 and ex7_ld_par_err); + + +bx_cmd_stall_d <= (ob_req_val_l2 or ob_ditc_val_l2) and + (not store_credit or (st_entry0_val_l2 ) or st_recycle_v_l2 or + (l2req_resend_l2 and ex7_ld_par_err)); + +latch_bx_cmd_sent : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(bx_cmd_sent_offset to bx_cmd_sent_offset), + scout => sov(bx_cmd_sent_offset to bx_cmd_sent_offset), + din(0) => bx_cmd_sent_d, + dout(0) => bx_cmd_sent_l2 ); + +lsu_bx_cmd_sent <= bx_cmd_sent_l2; + +latch_bx_cmd_stall : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(bx_cmd_stall_offset to bx_cmd_stall_offset), + scout => sov(bx_cmd_stall_offset to bx_cmd_stall_offset), + din(0) => bx_cmd_stall_d, + dout(0) => bx_cmd_stall_l2 ); + +lsu_bx_cmd_stall <= bx_cmd_stall_l2; + +bx_stall_dly_d(0) <= bx_cmd_stall_l2; +bx_stall_dly_d(1) <= bx_stall_dly_l2(0); +bx_stall_dly_d(2) <= bx_stall_dly_l2(1); +bx_stall_dly_d(3) <= bx_stall_dly_l2(3); + +bx_stall_dly_or <= not(bx_stall_dly_l2(0 to 2)="000") or bx_cmd_stall_l2; + +latch_bx_stall_dly : tri_rlmreg_p + generic map (width => bx_stall_dly_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(bx_stall_dly_offset to bx_stall_dly_offset + bx_stall_dly_l2'length-1), + scout => sov(bx_stall_dly_offset to bx_stall_dly_offset + bx_stall_dly_l2'length-1), + din => bx_stall_dly_d(0 to 3), + dout => bx_stall_dly_l2(0 to 3) ); + +latch_xu_mm_lsu_token : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(xu_mm_lsu_token_offset to xu_mm_lsu_token_offset), + scout => sov(xu_mm_lsu_token_offset to xu_mm_lsu_token_offset), + din(0) => mmu_sent, + dout(0) => mmu_sent_l2 ); + +xu_mm_lsu_token <= mmu_sent_l2 and not ex7_ld_par_err; + +-- set bit to indicate that an op was flushed due to a lmq address hit (use to set and release barrior to IU) + + +ex3_val_req <= (ex3_local_dcbf or ex3_l_s_q_val) and not ex3_stg_flush; + +-- latch into ex4 +latch_ex4_val_req : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_val_req_offset to ex4_val_req_offset), + scout => sov(ex4_val_req_offset to ex4_val_req_offset), + din(0) => ex3_val_req, + dout(0) => ex4_val_req ); +latch_ex4_thrd_id : tri_rlmreg_p + generic map (width => ex4_thrd_id'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ex4_st_entry_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_thrd_id_offset to ex4_thrd_id_offset + ex4_thrd_id'length-1), + scout => sov(ex4_thrd_id_offset to ex4_thrd_id_offset + ex4_thrd_id'length-1), + din => ex3_thrd_id(0 to 3), + dout => ex4_thrd_id(0 to 3) ); +latch_ex5_thrd_id : tri_rlmreg_p + generic map (width => ex5_thrd_id'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex5_thrd_id_offset to ex5_thrd_id_offset + ex5_thrd_id'length-1), + scout => sov(ex5_thrd_id_offset to ex5_thrd_id_offset + ex5_thrd_id'length-1), + din => ex4_thrd_id(0 to 3), + dout => ex5_thrd_id(0 to 3) ); + + + + +lmq_collision: for i in 0 to lmq_entries-1 generate begin + lmq_collision_t0_d(i) <= ( (ex5_lmq_cpy_l2(i) and ld_rel_val_l2(i) and not ex4_loadmiss_qentry(i) and xu_lsu_ex5_set_barr(0)) or + lmq_collision_t0_l2(i)) and not reset_ldq_hit_barr(i); + lmq_collision_t1_d(i) <= ( (ex5_lmq_cpy_l2(i) and ld_rel_val_l2(i) and not ex4_loadmiss_qentry(i) and xu_lsu_ex5_set_barr(1)) or + lmq_collision_t1_l2(i)) and not reset_ldq_hit_barr(i); + lmq_collision_t2_d(i) <= ( (ex5_lmq_cpy_l2(i) and ld_rel_val_l2(i) and not ex4_loadmiss_qentry(i) and xu_lsu_ex5_set_barr(2)) or + lmq_collision_t2_l2(i)) and not reset_ldq_hit_barr(i); + lmq_collision_t3_d(i) <= ( (ex5_lmq_cpy_l2(i) and ld_rel_val_l2(i) and not ex4_loadmiss_qentry(i) and xu_lsu_ex5_set_barr(3)) or + lmq_collision_t3_l2(i)) and not reset_ldq_hit_barr(i); +end generate; + + +lmq_barr_done_p: process (reset_ldq_hit_barr, lmq_collision_t0_l2, lmq_collision_t1_l2, lmq_collision_t2_l2, lmq_collision_t3_l2, ex5_lmq_cpy_l2, xu_lsu_ex5_set_barr, ld_rel_val_l2, ex4_loadmiss_qentry ) + variable b: std_ulogic_vector(0 to 3); +begin + b := "0000"; + for i in 0 to lmq_entries-1 loop + b(0) := (reset_ldq_hit_barr(i) and lmq_collision_t0_l2(i)) or + (ex5_lmq_cpy_l2(i) and xu_lsu_ex5_set_barr(0) and (not ld_rel_val_l2(i) or reset_ldq_hit_barr(i) or (ld_rel_val_l2(i) and ex4_loadmiss_qentry(i)))) or b(0); + b(1) := (reset_ldq_hit_barr(i) and lmq_collision_t1_l2(i)) or + (ex5_lmq_cpy_l2(i) and xu_lsu_ex5_set_barr(1) and (not ld_rel_val_l2(i) or reset_ldq_hit_barr(i) or (ld_rel_val_l2(i) and ex4_loadmiss_qentry(i)))) or b(1); + b(2) := (reset_ldq_hit_barr(i) and lmq_collision_t2_l2(i)) or + (ex5_lmq_cpy_l2(i) and xu_lsu_ex5_set_barr(2) and (not ld_rel_val_l2(i) or reset_ldq_hit_barr(i) or (ld_rel_val_l2(i) and ex4_loadmiss_qentry(i)))) or b(2); + b(3) := (reset_ldq_hit_barr(i) and lmq_collision_t3_l2(i)) or + (ex5_lmq_cpy_l2(i) and xu_lsu_ex5_set_barr(3) and (not ld_rel_val_l2(i) or reset_ldq_hit_barr(i) or (ld_rel_val_l2(i) and ex4_loadmiss_qentry(i)))) or b(3); + end loop; + lmq_barr_done_tid(0 to 3) <= b; +end process; + + +latch_lmq_collision_t0 : tri_rlmreg_p + generic map (width => lmq_collision_t0_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(lmq_collision_t0_offset to lmq_collision_t0_offset + lmq_collision_t0_l2'length-1), + scout => sov(lmq_collision_t0_offset to lmq_collision_t0_offset + lmq_collision_t0_l2'length-1), + din => lmq_collision_t0_d, + dout => lmq_collision_t0_l2 ); + +latch_lmq_collision_t1 : tri_rlmreg_p + generic map (width => lmq_collision_t1_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(lmq_collision_t1_offset to lmq_collision_t1_offset + lmq_collision_t1_l2'length-1), + scout => sov(lmq_collision_t1_offset to lmq_collision_t1_offset + lmq_collision_t1_l2'length-1), + din => lmq_collision_t1_d, + dout => lmq_collision_t1_l2 ); + +latch_lmq_collision_t2 : tri_rlmreg_p + generic map (width => lmq_collision_t2_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(lmq_collision_t2_offset to lmq_collision_t2_offset + lmq_collision_t2_l2'length-1), + scout => sov(lmq_collision_t2_offset to lmq_collision_t2_offset + lmq_collision_t2_l2'length-1), + din => lmq_collision_t2_d, + dout => lmq_collision_t2_l2 ); + +latch_lmq_collision_t3 : tri_rlmreg_p + generic map (width => lmq_collision_t3_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(lmq_collision_t3_offset to lmq_collision_t3_offset + lmq_collision_t3_l2'length-1), + scout => sov(lmq_collision_t3_offset to lmq_collision_t3_offset + lmq_collision_t3_l2'length-1), + din => lmq_collision_t3_d, + dout => lmq_collision_t3_l2 ); + +ldq_barr_active_d(0 to 3) <= (xu_lsu_ex5_set_barr(0 to 3) and not lmq_barr_done_tid(0 to 3)) or + (ldq_barr_active_l2(0 to 3) and not lmq_barr_done_tid(0 to 3)); + +latch_ldq_barr_active : tri_rlmreg_p + generic map (width => ldq_barr_active_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ldq_barr_active_offset to ldq_barr_active_offset + ldq_barr_active_l2'length-1), + scout => sov(ldq_barr_active_offset to ldq_barr_active_offset + ldq_barr_active_l2'length-1), + din => ldq_barr_active_d(0 to 3), + dout => ldq_barr_active_l2(0 to 3) ); + +sync_done <= store_sent and ( ((s_m_queue0(0 to 5) = "110010") or (s_m_queue0(0 to 5) = "101010")) or -- mbar,lwsync + (not my_xucr0_tlbsync and ( s_m_queue0(0 to 5) = "111010"))) and -- tlbsync + not (ex5_stg_flush and ex5_st_val_for_flush) and st_entry0_val_l2; + + +sync_done_tid <= gate_and(sync_done, s_m_queue0(38 to 41)); +ldq_barr_done <= lmq_barr_done_tid(0 to 3) and (ldq_barr_active_l2(0 to 3) or xu_lsu_ex5_set_barr(0 to 3)); + + +-- Signals Going to IU, Need to flag when the L2 has acknowledged an lwsync or eieio +latch_ldq_barr_done : tri_rlmreg_p + generic map (width => ldq_barr_done'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ldq_barr_done_offset to ldq_barr_done_offset + ldq_barr_done'length-1), + scout => sov(ldq_barr_done_offset to ldq_barr_done_offset + ldq_barr_done'length-1), + din => ldq_barr_done(0 to 3), + dout => ldq_barr_done_l2(0 to 3) ); + +lsu_xu_ldq_barr_done <= ldq_barr_done_l2; + +latch_sync_done_tid : tri_rlmreg_p + generic map (width => sync_done_tid'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(sync_done_tid_offset to sync_done_tid_offset + sync_done_tid'length-1), + scout => sov(sync_done_tid_offset to sync_done_tid_offset + sync_done_tid'length-1), + din => sync_done_tid(0 to 3), + dout => sync_done_tid_l2(0 to 3) ); + +lsu_xu_sync_barr_done <= sync_done_tid_l2; + + +q4_tag: if lmq_entries=4 generate begin + l_m_tag(2) <= '0'; + l_m_tag(3) <= l_q_rd_en(2) or l_q_rd_en(3); + l_m_tag(4) <= l_q_rd_en(1) or l_q_rd_en(3); +end generate; + +q8_tag: if lmq_entries=8 generate begin + l_m_tag(2) <= l_q_rd_en(4) or l_q_rd_en(5) or l_q_rd_en(6) or l_q_rd_en(7); + l_m_tag(3) <= l_q_rd_en(2) or l_q_rd_en(3) or l_q_rd_en(6) or l_q_rd_en(7); + l_m_tag(4) <= l_q_rd_en(1) or l_q_rd_en(3) or l_q_rd_en(5) or l_q_rd_en(7); +end generate; + + + + +--****************************************************** +-- Outputs +--****************************************************** + +-- bit(0:5) => ctype +-- bit(6:21) => byte enables +-- bit(22:25) => thread_id +-- bit(26:29) => wimg +-- bit(30) => little endian +-- bit(31:33) => transfer length +-- bit(34:62) => real address + +-- *************************************************************************************************** +-- Signals Going to L2 + +l2req_pwr_token <= iu_val or any_ld_entry_val or st_entry0_val_l2 or ex4_ld_m_val or ex4_st_val_l2 or + mmu_q_val_l2 or + ob_req_val_l2 or ob_ditc_val_l2 or ob_pwr_tok_l2 or l2req_resend_d or st_recycle_v_l2 or (l2req_recycle_l2 and ex7_ld_par_err); + + +ex5_st_val_for_flush <= ex5_st_val_l2; + +l2req <= (load_sent and not (lq_rd_en_is_ex5 and ex5_flush_load_all) ) or + (store_sent and not (ex5_stg_flush and ex5_st_val_for_flush)) or + iu_sent_val or mmu_sent when (l2req_resend_l2 and ex7_ld_par_err) = '0' else + '1'; + +l2req_gated <= l2req and not ex6_ld_par_err; + +l2req_st_data_ptoken <= (ex4_st_val_l2 and not ex4_flush_store and + ((ex4_st_entry_l2(0 to 5)="100000") or (ex4_st_entry_l2(0 to 4)="10011") or (ex4_st_entry_l2(0 to 5)="101001"))) or + (st_entry0_val_l2 and ((s_m_queue0(0 to 5)="100000") or (s_m_queue0(0 to 4)="10011") or (s_m_queue0(0 to 5)="101001"))) or + ob_req_val_l2 or ob_ditc_val_l2 or ob_pwr_tok_l2 or mmu_st_sent or bx_cmd_sent_d or + (mmu_q_val_l2 and (mmu_q_entry_l2(0 to 1)="00")) or st_recycle_v_l2 or + ((l2req_resend_l2 or l2req_recycle_l2) and ex7_ld_par_err); + +l2req_ld_core_tag(0) <= '0'; +l2req_ld_core_tag(1 to 4) <= ld_tag(1 to 4) when (l2req_resend_l2 and ex7_ld_par_err) = '0' else + l2req_ld_core_tag_l2(1 to 4); + +l2req_ra <= ld_st_request(54 to (54+real_data_add-1)) when (l2req_resend_l2 and ex7_ld_par_err) = '0' else + l2req_ra_l2; + +std_be_16: if st_data_32B_mode=0 generate begin + l2req_st_byte_enbl <= l2req_st_byte_enbl_l2 when (l2req_resend_l2 and ex7_ld_par_err) = '1' else + ld_st_request(6 to 21) when st_req(54+real_data_add-1-4) = '0' else + ld_st_request(22 to 37); + + st_recycle_entry(6 to 37) <= l2req_st_byte_enbl_l2(0 to 15) & l2req_st_byte_enbl_l2(0 to 15); + +end generate; + +copy_st_be_for_16B_mode <= st_req(54+real_data_add-1-4) and not my_xucr0_l2siw; + +std_be_32: if st_data_32B_mode=1 generate begin + l2req_st_byte_enbl(0 to 15) <= l2req_st_byte_enbl_l2(0 to 15) when (l2req_resend_l2 and ex7_ld_par_err) = '1' else + ld_st_request(6 to 21) when copy_st_be_for_16B_mode = '0' else + ld_st_request(22 to 37); + l2req_st_byte_enbl(16 to 31) <= l2req_st_byte_enbl_l2(16 to 31) when (l2req_resend_l2 and ex7_ld_par_err) = '1' else + ld_st_request(22 to 37); + + st_recycle_entry(6 to 37) <= l2req_st_byte_enbl_l2(0 to 31); +end generate; + +-- encode thread ID that is 1-hot in 38:41 +l2req_thread(0) <= ld_st_request(40) or ld_st_request(41) when (l2req_resend_l2 and ex7_ld_par_err) = '0' else + l2req_thread_l2(0); +l2req_thread(1) <= ld_st_request(39) or ld_st_request(41) when (l2req_resend_l2 and ex7_ld_par_err) = '0' else + l2req_thread_l2(1); + +l2req_thread(2) <= not st_entry0_val_l2 and (ob_req_val_l2 or ob_ditc_val_l2) and store_credit when (l2req_resend_l2 and ex7_ld_par_err) = '0' else + l2req_thread_l2(2); +l2req_ttype(0 to 5) <= ld_st_request(0 to 5) when (l2req_resend_l2 and ex7_ld_par_err) = '0' else + l2req_ttype_l2(0 to 5); +l2req_wimg <= ld_st_request(42 to 45) when (l2req_resend_l2 and ex7_ld_par_err) = '0' else + l2req_wimg_l2; +l2req_user <= ld_st_request(50 to 53) when (l2req_resend_l2 and ex7_ld_par_err) = '0' else + l2req_user_l2; +l2req_endian <= ld_st_request(46) when (l2req_resend_l2 and ex7_ld_par_err) = '0' else + l2req_endian_l2; +l2req_ld_xfr_len <= ld_st_request(47 to 49) when (l2req_resend_l2 and ex7_ld_par_err) = '0' else + l2req_ld_xfr_len_l2; + + + +latch_l2req_resend : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(l2req_resend_offset to l2req_resend_offset), + scout => sov(l2req_resend_offset to l2req_resend_offset), + din(0) => l2req_resend_d, + dout(0) => l2req_resend_l2); + +latch_l2req_recycle : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(l2req_recycle_offset to l2req_recycle_offset), + scout => sov(l2req_recycle_offset to l2req_recycle_offset), + din(0) => l2req_recycle_d, + dout(0) => l2req_recycle_l2); + +latch_l2req_pwr_token : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(l2req_pwr_token_offset to l2req_pwr_token_offset), + scout => sov(l2req_pwr_token_offset to l2req_pwr_token_offset), + din(0) => l2req_pwr_token, + dout(0) => l2req_pwr_token_l2 ); + +ac_an_req_pwr_token <= l2req_pwr_token_l2; + +latch_l2req_st_data_ptoken : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(l2req_st_data_ptoken_offset to l2req_st_data_ptoken_offset), + scout => sov(l2req_st_data_ptoken_offset to l2req_st_data_ptoken_offset), + din(0) => l2req_st_data_ptoken, + dout(0) => l2req_st_data_ptoken_l2 ); + +ac_an_st_data_pwr_token <= l2req_st_data_ptoken_l2; + +latch_l2req : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(l2req_offset to l2req_offset), + scout => sov(l2req_offset to l2req_offset), + din(0) => l2req_gated, + dout(0) => l2req_l2 ); +ac_an_req <= l2req_l2; + +l2req_act <= l2req_pwr_token_l2 or clkg_ctl_override_q; + +latch_l2req_ld_core_tag : tri_rlmreg_p + generic map (width => l2req_ld_core_tag'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => l2req_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(l2req_ld_core_tag_offset to l2req_ld_core_tag_offset + l2req_ld_core_tag'length-1), + scout => sov(l2req_ld_core_tag_offset to l2req_ld_core_tag_offset + l2req_ld_core_tag'length-1), + din => l2req_ld_core_tag, + dout => l2req_ld_core_tag_l2 ); +ac_an_req_ld_core_tag <= l2req_ld_core_tag_l2; + +latch_l2req_ra : tri_rlmreg_p + generic map (width => l2req_ra'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => l2req_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(l2req_ra_offset to l2req_ra_offset + l2req_ra'length-1), + scout => sov(l2req_ra_offset to l2req_ra_offset + l2req_ra'length-1), + din => l2req_ra, + dout => l2req_ra_l2 ); +ac_an_req_ra <= l2req_ra_l2; + +latch_l2req_st_byte_enbl : tri_rlmreg_p + generic map (width => l2req_st_byte_enbl'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => l2req_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(l2req_st_byte_enbl_offset to l2req_st_byte_enbl_offset + l2req_st_byte_enbl'length-1), + scout => sov(l2req_st_byte_enbl_offset to l2req_st_byte_enbl_offset + l2req_st_byte_enbl'length-1), + din => l2req_st_byte_enbl, + dout => l2req_st_byte_enbl_l2 ); +ac_an_st_byte_enbl <= l2req_st_byte_enbl_l2; + +latch_l2req_thread : tri_rlmreg_p + generic map (width => l2req_thread'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => l2req_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(l2req_thread_offset to l2req_thread_offset + l2req_thread'length-1), + scout => sov(l2req_thread_offset to l2req_thread_offset + l2req_thread'length-1), + din => l2req_thread(0 to 2), + dout => l2req_thread_l2(0 to 2) ); +ac_an_req_thread(0 to 2) <= l2req_thread_l2(0 to 2); + +latch_l2req_ttype : tri_rlmreg_p + generic map (width => l2req_ttype'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => l2req_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(l2req_ttype_offset to l2req_ttype_offset + l2req_ttype'length-1), + scout => sov(l2req_ttype_offset to l2req_ttype_offset + l2req_ttype'length-1), + din => l2req_ttype(0 to 5), + dout => l2req_ttype_l2(0 to 5) ); +ac_an_req_ttype <= l2req_ttype_l2; + +latch_l2req_wimg : tri_rlmreg_p + generic map (width => l2req_wimg'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => l2req_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(l2req_wimg_offset to l2req_wimg_offset + l2req_wimg'length-1), + scout => sov(l2req_wimg_offset to l2req_wimg_offset + l2req_wimg'length-1), + din => l2req_wimg(0 to 3), + dout => l2req_wimg_l2(0 to 3) ); +ac_an_req_wimg_w <= l2req_wimg_l2(0); +ac_an_req_wimg_i <= l2req_wimg_l2(1); +ac_an_req_wimg_m <= l2req_wimg_l2(2); +ac_an_req_wimg_g <= l2req_wimg_l2(3); + + +latch_l2req_endian : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => l2req_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(l2req_endian_offset to l2req_endian_offset), + scout => sov(l2req_endian_offset to l2req_endian_offset), + din(0) => l2req_endian, + dout(0) => l2req_endian_l2 ); +ac_an_req_endian <= l2req_endian_l2; + + +latch_l2req_user : tri_rlmreg_p + generic map (width => l2req_user'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => l2req_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(l2req_user_offset to l2req_user_offset + l2req_user'length-1), + scout => sov(l2req_user_offset to l2req_user_offset + l2req_user'length-1), + din => l2req_user(0 to 3), + dout => l2req_user_l2(0 to 3) ); +ac_an_req_user_defined <= l2req_user_l2; + +latch_l2req_ld_xfr_len : tri_rlmreg_p + generic map (width => l2req_ld_xfr_len'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => l2req_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(l2req_ld_xfr_len_offset to l2req_ld_xfr_len_offset + l2req_ld_xfr_len'length-1), + scout => sov(l2req_ld_xfr_len_offset to l2req_ld_xfr_len_offset + l2req_ld_xfr_len'length-1), + din => l2req_ld_xfr_len(0 to 2), + dout => l2req_ld_xfr_len_l2 ); +ac_an_req_ld_xfr_len <= l2req_ld_xfr_len_l2; + +latch_spare_ctrl_a0 : tri_rlmreg_p + generic map (width => ac_an_req_spare_ctrl_a0'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '0', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(spare_ctrl_a0_offset to spare_ctrl_a0_offset + ac_an_req_spare_ctrl_a0'length-1), + scout => sov(spare_ctrl_a0_offset to spare_ctrl_a0_offset + ac_an_req_spare_ctrl_a0'length-1), + din => "0000", + dout => ac_an_req_spare_ctrl_a0 ); + +latch_spare_ctrl_a1 : tri_rlmreg_p + generic map (width => an_ac_req_spare_ctrl_a1'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '0', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(spare_ctrl_a1_offset to spare_ctrl_a1_offset + an_ac_req_spare_ctrl_a1'length-1), + scout => sov(spare_ctrl_a1_offset to spare_ctrl_a1_offset + an_ac_req_spare_ctrl_a1'length-1), + din => an_ac_req_spare_ctrl_a1, + dout => unused(0 to 3) ); + + + +-- format l2 request back into a store entry for recycling after a dcache parity error +st_recycle_entry(0 to 5) <= l2req_ttype_l2; + +-- byte enables set above + +st_recycle_entry(38) <= l2req_thread_l2(0 to 1) = "00"; +st_recycle_entry(39) <= l2req_thread_l2(0 to 1) = "01"; +st_recycle_entry(40) <= l2req_thread_l2(0 to 1) = "10"; +st_recycle_entry(41) <= l2req_thread_l2(0 to 1) = "11"; +st_recycle_entry(42 to 45) <= l2req_wimg_l2; +st_recycle_entry(46) <= l2req_endian_l2; +st_recycle_entry(47 to 49) <= l2req_ld_xfr_len_l2; +st_recycle_entry(50 to 53) <= l2req_user_l2; +st_recycle_entry(54 to (54+real_data_add-1)) <= l2req_ra_l2; + +st_recycle_d <= st_recycle_entry when st_recycle_v_l2='0' else + st_recycle_l2; + +st_recycle_act <= l2req_l2 or st_recycle_v_l2 or ex7_ld_par_err or clkg_ctl_override_q; + +latch_st_recycle : tri_rlmreg_p + generic map (width => st_recycle_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => st_recycle_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(st_recycle_offset to st_recycle_offset + st_recycle_l2'length-1), + scout => sov(st_recycle_offset to st_recycle_offset + st_recycle_l2'length-1), + din => st_recycle_d, + dout => st_recycle_l2 ); + +st_recycle_v_d <= (l2req_recycle_l2 and ex7_ld_par_err and not (ex6_flush_l2 and ex6_st_val_l2)) or + (st_recycle_v_l2 and not store_sent); + +latch_st_recycle_v : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => st_recycle_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(st_recycle_v_offset to st_recycle_v_offset), + scout => sov(st_recycle_v_offset to st_recycle_v_offset), + din(0) => st_recycle_v_d, + dout(0) => st_recycle_v_l2 ); + +-- ************************************************************************* +-- latch info about late ex5 flush into ex6 + +ex5_load <= load_sent and lq_rd_en_is_ex5; + +latch_ex6_load_sent : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex6_load_sent_offset to ex6_load_sent_offset), + scout => sov(ex6_load_sent_offset to ex6_load_sent_offset), + din(0) => ex5_load, + dout(0) => ex6_load_sent_l2 ); + +latch_load_sent_dbglat : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(load_sent_dbglat_offset to load_sent_dbglat_offset), + scout => sov(load_sent_dbglat_offset to load_sent_dbglat_offset), + din(0) => load_sent, + dout(0) => load_sent_dbglat_l2 ); + +ex5_store_sent <= store_sent and ex5_st_val_for_flush; + +latch_ex6_store_sent : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => stq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex6_store_sent_offset to ex6_store_sent_offset), + scout => sov(ex6_store_sent_offset to ex6_store_sent_offset), + din(0) => ex5_store_sent, + dout(0) => ex6_store_sent_l2 ); + + +ex5_flush_d <= ex4_stg_flush; + +latch_ex5_flush : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex5_flush_offset to ex5_flush_offset), + scout => sov(ex5_flush_offset to ex5_flush_offset), + din(0) => ex5_flush_d, + dout(0) => ex5_flush_l2 ); + +ex5_stg_flush <= ((xu_lsu_ex5_flush(0) and ex5_thrd_id(0)) or -- thread 0 flush + (xu_lsu_ex5_flush(1) and ex5_thrd_id(1)) or -- thread 1 flush + (xu_lsu_ex5_flush(2) and ex5_thrd_id(2)) or -- thread 2 flush + (xu_lsu_ex5_flush(3) and ex5_thrd_id(3))) and -- thread 3 flush + not pe_recov_state_l2; +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +my_ex5_flush <= ex5_stg_flush or ex5_flush_l2; + +ex5_flush_store <= ex5_flush_l2; -- and not (s_m_queue0(0 to 4) = "10111"); -- dci & ici aren't flushed +my_ex5_flush_store <= (ex5_stg_flush or ex5_flush_l2); -- and not (s_m_queue0(0 to 4) = "10111"); -- dci & ici aren't flushed + +latch_ex6_flush : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex6_flush_offset to ex6_flush_offset), + scout => sov(ex6_flush_offset to ex6_flush_offset), + din(0) => ex5_stg_flush, + dout(0) => ex6_flush_l2 ); + + +-- ************************************************************************* +-- latch msr and pid inputs + +latch_msr_gs : tri_rlmreg_p + generic map (width => msr_gs_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ex4_st_entry_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(msr_gs_offset to msr_gs_offset + msr_gs_l2'length-1), + scout => sov(msr_gs_offset to msr_gs_offset + msr_gs_l2'length-1), + din => xu_lsu_msr_gs(0 to 3), + dout => msr_gs_l2 ); + +latch_msr_pr : tri_rlmreg_p + generic map (width => msr_pr_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ex4_st_entry_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(msr_pr_offset to msr_pr_offset + msr_pr_l2'length-1), + scout => sov(msr_pr_offset to msr_pr_offset + msr_pr_l2'length-1), + din => xu_lsu_msr_pr(0 to 3), + dout => msr_pr_l2 ); + +latch_msr_ds : tri_rlmreg_p + generic map (width => msr_ds_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ex4_st_entry_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(msr_ds_offset to msr_ds_offset + msr_ds_l2'length-1), + scout => sov(msr_ds_offset to msr_ds_offset + msr_ds_l2'length-1), + din => xu_lsu_msr_ds(0 to 3), + dout => msr_ds_l2 ); + +latch_pid0 : tri_rlmreg_p + generic map (width => pid0_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ex4_st_entry_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(pid0_offset to pid0_offset + pid0_l2'length-1), + scout => sov(pid0_offset to pid0_offset + pid0_l2'length-1), + din => mm_xu_derat_pid0(0 to 13), + dout => pid0_l2 ); + +latch_pid1 : tri_rlmreg_p + generic map (width => pid1_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ex4_st_entry_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(pid1_offset to pid1_offset + pid1_l2'length-1), + scout => sov(pid1_offset to pid1_offset + pid1_l2'length-1), + din => mm_xu_derat_pid1(0 to 13), + dout => pid1_l2 ); + +latch_pid2 : tri_rlmreg_p + generic map (width => pid2_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ex4_st_entry_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(pid2_offset to pid2_offset + pid2_l2'length-1), + scout => sov(pid2_offset to pid2_offset + pid2_l2'length-1), + din => mm_xu_derat_pid2(0 to 13), + dout => pid2_l2 ); + +latch_pid3 : tri_rlmreg_p + generic map (width => pid3_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ex4_st_entry_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(pid3_offset to pid3_offset + pid3_l2'length-1), + scout => sov(pid3_offset to pid3_offset + pid3_l2'length-1), + din => mm_xu_derat_pid3(0 to 13), + dout => pid3_l2 ); + +-- ************************************************************************* +-- STORE DATA + +msr_hv <= or_reduce(not msr_gs_l2(0 to 3) and ex4_st_entry_l2(38 to 41)); -- use thread of req to select msr bit +msr_pr <= or_reduce(msr_pr_l2(0 to 3) and ex4_st_entry_l2(38 to 41)); -- use thread of req to select msr bit +msr_ds <= or_reduce(msr_ds_l2(0 to 3) and ex4_st_entry_l2(38 to 41)); -- use thread of req to select msr bit +pid(0 to 13) <= gate_and(ex4_st_entry_l2(38) , pid0_l2(0 to 13)) or + gate_and(ex4_st_entry_l2(39) , pid1_l2(0 to 13)) or + gate_and(ex4_st_entry_l2(40) , pid2_l2(0 to 13)) or + gate_and(ex4_st_entry_l2(41) , pid3_l2(0 to 13)); + +ditc_dat <= "00000000" & -- MSR byte + "00" & -- reserved + "000001" & -- CT=1 for DITC + ob_dest_l2(0 to 14) & '0' & -- dest + "00000000" & -- LPID + "0000000000000000" & -- PID + x"000000000000000000"; + +epsc_epr <= (xu_derat_epsc0_epr and ex4_st_entry_l2(38)) or + (xu_derat_epsc1_epr and ex4_st_entry_l2(39)) or + (xu_derat_epsc2_epr and ex4_st_entry_l2(40)) or + (xu_derat_epsc3_epr and ex4_st_entry_l2(41)); + +epsc_eas <= (xu_derat_epsc0_eas and ex4_st_entry_l2(38)) or + (xu_derat_epsc1_eas and ex4_st_entry_l2(39)) or + (xu_derat_epsc2_eas and ex4_st_entry_l2(40)) or + (xu_derat_epsc3_eas and ex4_st_entry_l2(41)); + +epsc_egs <= (xu_derat_epsc0_egs and ex4_st_entry_l2(38)) or + (xu_derat_epsc1_egs and ex4_st_entry_l2(39)) or + (xu_derat_epsc2_egs and ex4_st_entry_l2(40)) or + (xu_derat_epsc3_egs and ex4_st_entry_l2(41)); + +epsc_elpid <= (gate_and(ex4_st_entry_l2(38), xu_derat_epsc0_elpid)) or + (gate_and(ex4_st_entry_l2(39), xu_derat_epsc1_elpid)) or + (gate_and(ex4_st_entry_l2(40), xu_derat_epsc2_elpid)) or + (gate_and(ex4_st_entry_l2(41), xu_derat_epsc3_elpid)); + +epsc_epid <= (gate_and(ex4_st_entry_l2(38), xu_derat_epsc0_epid)) or + (gate_and(ex4_st_entry_l2(39), xu_derat_epsc1_epid)) or + (gate_and(ex4_st_entry_l2(40), xu_derat_epsc2_epid)) or + (gate_and(ex4_st_entry_l2(41), xu_derat_epsc3_epid)); + +ex4_icswx_extra_data(0 to 2) <= not epsc_egs & epsc_epr & epsc_eas when ex4_st_entry_l2(57)='1' else -- for icswepx + msr_hv & msr_pr & msr_ds; + +ex4_icswx_extra_data(3 to 24) <= epsc_elpid & epsc_epid when ex4_st_entry_l2(57)='1' else -- for icswepx + lpidr_l2(0 to 7) & pid(0 to 13); + +stq_icswx_extra_data_d <= stq_icswx_extra_data_l2 when (st_entry0_val_l2 and not (store_credit and ex5_sel_st_req))='1' else + ex4_icswx_extra_data; + +latch_stq_icswx_extra_data : tri_rlmreg_p + generic map (width => stq_icswx_extra_data_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => stq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(stq_icswx_extra_data_offset to stq_icswx_extra_data_offset + stq_icswx_extra_data_l2'length-1), + scout => sov(stq_icswx_extra_data_offset to stq_icswx_extra_data_offset + stq_icswx_extra_data_l2'length-1), + din => stq_icswx_extra_data_d, + dout => stq_icswx_extra_data_l2 ); + +icswx_dat(0 to 31) <= stq_icswx_extra_data_l2(0 to 2) & "0000000" & ex5_st_data_l2(10 to 31); + +icswx_dat(32 to 55) <= stq_icswx_extra_data_l2(3 to 10) & "00" & stq_icswx_extra_data_l2(11 to 24); + +icswx_dat(56 to 127) <= ex5_st_data_l2(56 to 127); + +latch_ex4_p_addr_59 : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ex3_stg_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_p_addr_59_offset to ex4_p_addr_59_offset), + scout => sov(ex4_p_addr_59_offset to ex4_p_addr_59_offset), + din(0) => ex3_p_addr(59), + dout(0) => ex4_p_addr_59 ); + +std16B: if st_data_32B_mode=0 generate begin + + ex4_st_data_mux(0 to 127) <= + ex4_256st_data(0 to 127) when ex4_p_addr_59 = '0' else + ex4_256st_data(128 to 255); +end generate; + +copy_st_data_for_16B_mode <= ex4_p_addr_59 and not my_xucr0_l2siw; + +std32B: if st_data_32B_mode=1 generate begin + ex4_st_data_mux(0 to 127) <= ex4_256st_data(0 to 127) when copy_st_data_for_16B_mode = '0' else + ex4_256st_data(128 to 255); + ex4_st_data_mux(128 to 255) <= ex4_256st_data(128 to 255); + + ex5_st_data_mux(128 to 255) <= ex6_st_data_l2(128 to 255) when (((l2req_resend_l2 or l2req_recycle_l2) and ex7_ld_par_err) or + st_recycle_v_l2) = '1' else + ex5_st_data_l2(128 to 255) when st_entry0_val_clone_l2='1' else + ob_data_l2(0 to 127); -- when ob_req_val_l2='1' + +end generate; + + + +ex4_st_data_mux2 <= ex5_st_data_l2 when ((l2req_recycle_l2 and ex7_ld_par_err) or st_recycle_v_l2) = '1' else + ex4_st_data_mux when (st_entry0_val_l2 and not (store_credit and ex5_sel_st_req))='0' else + ex5_st_data_l2; + +latch_ex5_st_data : tri_rlmreg_p + generic map (width => ex5_st_data_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => stq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex5_st_data_offset to ex5_st_data_offset + ex5_st_data_l2'length-1), + scout => sov(ex5_st_data_offset to ex5_st_data_offset + ex5_st_data_l2'length-1), + din => ex4_st_data_mux2, + dout => ex5_st_data_l2 ); + + +ex5_st_data_mux1(0 to 127) <= icswx_dat(0 to 127) when s_m_queue0(0 to 4)="10011" else + ex5_st_data_l2(0 to 127); + +ex5_st_data_mux2(0 to 127) <= ob_data_l2(0 to 127) when ob_req_val_clone_l2='1' else + ditc_dat(0 to 127) when ob_ditc_val_clone_l2='1' else + ex5_st_data_l2(0 to 31) & + mmu_q_entry_l2(15 to 22) & -- lpid + "00000" & -- reserved + mmu_q_entry_l2(23 to 25) & -- IND,GS,L + ex5_st_data_l2(48 to 127); + +ex5_st_data_mux(0 to 127) <= ex6_st_data_l2(0 to 127) when (((l2req_resend_l2 or l2req_recycle_l2) and ex7_ld_par_err) or + st_recycle_v_l2) = '1' else + ex5_st_data_mux1 when st_entry0_val_clone_l2='1' else + ex5_st_data_mux2; + +st_data_act <= l2req_st_data_ptoken_l2 or clkg_ctl_override_q; + +latch_ex6_st_data : tri_rlmreg_p + generic map (width => ac_an_st_data'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => st_data_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex6_st_data_offset to ex6_st_data_offset + ac_an_st_data'length-1), + scout => sov(ex6_st_data_offset to ex6_st_data_offset + ac_an_st_data'length-1), + din => ex5_st_data_mux, + dout => ex6_st_data_l2 ); +ac_an_st_data <= ex6_st_data_l2; + +-- *************************************************************************************************** +-- Flush Conditions +ex3_stq_flush <= flush_if_store or sync_flush; +ex3_ig_flush <= I1_G1_flush; +ex4_l2cmdq_flush_d <= I1_G1_flush & flush_if_store & sync_flush & ld_queue_full & ld_q_seq_wrap; +latch_ex4_l2cmdq_flush : tri_rlmreg_p + generic map (width => ex4_l2cmdq_flush_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_l2cmdq_flush_offset to ex4_l2cmdq_flush_offset + ex4_l2cmdq_flush_l2'length-1), + scout => sov(ex4_l2cmdq_flush_offset to ex4_l2cmdq_flush_offset + ex4_l2cmdq_flush_l2'length-1), + din => ex4_l2cmdq_flush_d, + dout => ex4_l2cmdq_flush_l2 ); + + +-- *************************************************************************************************** +-- Reload outputs +ldq_rel_op_size(0 to 5) <= rel_size_l2(0 to 5); +ldq_rel_thrd_id(0 to 3) <= rel_th_id_l2(0 to 3); +ldq_rel_ci <= rel_cache_inh_l2; + + + +my_beat1_p: process (l_m_rel_hit_beat0_l2, l_m_rel_hit_beat1_l2, rel_tag_l2, rel_data_val) + variable b: std_ulogic; + variable c: std_ulogic; +begin + b := '0'; + c := '0'; + for i in 0 to lmq_entries-1 loop + b := (l_m_rel_hit_beat1_l2(i) and (rel_tag_l2(1 to 4) = tconv(i, 4)) ) or b; + c := (l_m_rel_hit_beat0_l2(i) and rel_data_val(i)) or c; + end loop; + my_beat1 <= b; + my_beat1_early <= c; +end process; + + + +my_beat_mid_p: process (l_m_rel_hit_beat3_l2, l_m_rel_hit_beat5_l2, rel_tag_l2, my_xucr0_cls) + variable b: std_ulogic; +begin + b := '0'; + for i in 0 to lmq_entries-1 loop + b := ((l_m_rel_hit_beat3_l2(i) or l_m_rel_hit_beat5_l2(i)) and + (rel_tag_l2(1 to 4) = tconv(i, 4)) and my_xucr0_cls ) or b; + end loop; + my_beat_mid <= b; +end process; + +my_beat_last_p: process (l_m_rel_hit_beat2_l2, l_m_rel_hit_beat6_l2, rel_data_val, my_xucr0_cls, rel_tag_l2, ldq_retry_l2) + variable b: std_ulogic; + variable c: std_ulogic; +begin + b := '0'; + c := '0'; + for i in 0 to lmq_entries-1 loop + b := (((l_m_rel_hit_beat2_l2(i) and rel_data_val(i) and not my_xucr0_cls) or (l_m_rel_hit_beat6_l2(i) and rel_data_val(i) and my_xucr0_cls)) ) or b; + c := (ldq_retry_l2(i) and (rel_tag_l2(1 to 4) = tconv(i, 4))) or c; + end loop; + my_beat_last_d <= b; + my_ldq_retry <= c; +end process; + +latch_my_beat_last : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(my_beat_last_offset to my_beat_last_offset), + scout => sov(my_beat_last_offset to my_beat_last_offset), + din(0) => my_beat_last_d, + dout(0) => my_beat_last_l2 ); + +my_beat_odd_p: process (l_m_rel_hit_beat1_l2, l_m_rel_hit_beat3_l2, l_m_rel_hit_beat5_l2, l_m_rel_hit_beat7_l2, rel_tag_l2) + variable b: std_ulogic; +begin + b := '0'; + for i in 0 to lmq_entries-1 loop + b := ((l_m_rel_hit_beat1_l2(i) or l_m_rel_hit_beat3_l2(i) or l_m_rel_hit_beat5_l2(i) or l_m_rel_hit_beat7_l2(i)) and + (rel_tag_l2(1 to 4) = tconv(i, 4)) ) or b; + end loop; + my_beat_odd <= b; +end process; + +ldq_rel1_val_buf <= reld_data_vld_l2 and not rel_cache_inh_l2 and not rel_l2only_l2 and + not rel_tag_l2(1) and my_beat1; +ldq_rel1_val <= ldq_rel1_val_buf; + +ldq_rel1_early_v <= my_beat1_early; + +ldq_rel_mid_val_buf <= reld_data_vld_l2 and not rel_cache_inh_l2 and not rel_l2only_l2 and + not rel_tag_l2(1) and my_beat_mid; +ldq_rel_mid_val <= ldq_rel_mid_val_buf; + +ldq_rel3_val_buf <= reld_data_vld_l2 and not rel_cache_inh_l2 and not rel_l2only_l2 and + not rel_tag_l2(1) and my_beat_last_l2; +ldq_rel3_val <= ldq_rel3_val_buf; + +ldq_rel3_early_v <= my_beat_last_d; + +l2only_from_queue_p: process (l_m_queue(0)(48), l_m_queue(1)(48), l_m_queue(2)(48), l_m_queue(3)(48), l_m_queue(4)(48), l_m_queue(5)(48), l_m_queue(6)(48), l_m_queue(7)(48), rel_tag_l2) + variable b: std_ulogic; +begin + b := '0'; + for i in 0 to lmq_entries-1 loop + b := (l_m_queue(i)(48) and (rel_tag_l2(1 to 4) = tconv(i, 4)) ) or b; + end loop; + l2only_from_queue <= b; +end process; + +l1dump_cslc <= reld_data_vld_l2 and not rel_cache_inh_l2 and not rel_tag_l2(1) and my_beat_last_l2 and + l1_dump and rel_lock_en_l2 and not l2only_from_queue; + +ldq_rel3_l1dump_val <= reld_data_vld_l2 and not rel_cache_inh_l2 and not rel_tag_l2(1) and my_beat_last_l2 and l1_dump; + + + +ldq_rel_data_val_buf <= reld_data_vld_l2 and not rel_cache_inh_l2 and not (rel_l2only_l2 and not (l1_dump and rel_intf_v_l2)) and + my_beat_odd and not my_ldq_retry; +ldq_rel_data_val <= ldq_rel_data_val_buf; + +ldq_rel_data_val_early <= data_val_dminus1_l2; + +ldq_rel_retry_val_buf <= ldq_rel_retry_val_dly_l2 and not rel_cache_inh_l2 and not rel_l2only_l2 and + not rel_tag_l2(1) and my_beat_last_l2; +ldq_rel_retry_val <= ldq_rel_retry_val_buf; + + + +ldq_rel_ta_gpr(0 to 8) <= rel_tar_gpr_l2(0 to 8); + +ex3_loadmiss_qentry(0 to lmq_entries-1) <= l_q_wrt_en(0 to lmq_entries-1); +ex3_loadmiss_target(0 to 8) <= ex3_new_target_gpr(0 to 8); +ex3_loadmiss_target_type(0 to 1) <= "01" when (ld_m_val and ex3_axu_op_val) = '1' else + "10" when ld_m_val = '1' else + "00"; +ex3_loadmiss_tid(0 to 3) <= gate_and(ld_m_val, ex3_thrd_id(0 to 3)); + + +latch_loadmiss_qentry : tri_rlmreg_p + generic map (width => ex4_loadmiss_qentry'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(loadmiss_qentry_offset to loadmiss_qentry_offset + ex4_loadmiss_qentry'length-1), + scout => sov(loadmiss_qentry_offset to loadmiss_qentry_offset + ex4_loadmiss_qentry'length-1), + din => ex3_loadmiss_qentry(0 to lmq_entries-1), + dout => ex4_loadmiss_qentry(0 to lmq_entries-1) ); + +cmp_ex4_loadmiss_qentry <= ex4_loadmiss_qentry; +xu_iu_ex4_loadmiss_qentry(0 to lmq_entries-1) <= gate_and(not ex4_drop_ld_req, ex4_loadmiss_qentry(0 to lmq_entries-1)); + +ex5_loadmiss_qentry_d <= ex4_loadmiss_qentry when pe_recov_stall='0' else + ex5_loadmiss_qentry; + +latch_ex5_loadmiss_qentry : tri_rlmreg_p + generic map (width => ex5_loadmiss_qentry'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex5_loadmiss_qentry_offset to ex5_loadmiss_qentry_offset + ex5_loadmiss_qentry'length-1), + scout => sov(ex5_loadmiss_qentry_offset to ex5_loadmiss_qentry_offset + ex5_loadmiss_qentry'length-1), + din => ex5_loadmiss_qentry_d(0 to lmq_entries-1), + dout => ex5_loadmiss_qentry(0 to lmq_entries-1) ); + +xu_iu_ex5_loadmiss_qentry(0 to lmq_entries-1) <= ex5_loadmiss_qentry(0 to lmq_entries-1); + +ex6_loadmiss_qentry_d <= ex5_loadmiss_qentry when pe_recov_stall='0' else + ex6_loadmiss_qentry; + +latch_ex6_loadmiss_qentry : tri_rlmreg_p + generic map (width => ex6_loadmiss_qentry'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex6_loadmiss_qentry_offset to ex6_loadmiss_qentry_offset + ex6_loadmiss_qentry'length-1), + scout => sov(ex6_loadmiss_qentry_offset to ex6_loadmiss_qentry_offset + ex6_loadmiss_qentry'length-1), + din => ex6_loadmiss_qentry_d(0 to lmq_entries-1), + dout => ex6_loadmiss_qentry(0 to lmq_entries-1) ); + +ex7_loadmiss_qentry_d <= "10000000" when (ex6_loadmiss_qentry="00000000") and (pe_recov_stall='0') else + ex6_loadmiss_qentry when pe_recov_stall='0' else + ex7_loadmiss_qentry; + +latch_ex7_loadmiss_qentry : tri_rlmreg_p + generic map (width => ex7_loadmiss_qentry'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex7_loadmiss_qentry_offset to ex7_loadmiss_qentry_offset + ex7_loadmiss_qentry'length-1), + scout => sov(ex7_loadmiss_qentry_offset to ex7_loadmiss_qentry_offset + ex7_loadmiss_qentry'length-1), + din => ex7_loadmiss_qentry_d(0 to lmq_entries-1), + dout => ex7_loadmiss_qentry(0 to lmq_entries-1) ); + +latch_ex4_loadmiss_target : tri_rlmreg_p + generic map (width => ex4_loadmiss_target'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_loadmiss_target_offset to ex4_loadmiss_target_offset + ex4_loadmiss_target'length-1), + scout => sov(ex4_loadmiss_target_offset to ex4_loadmiss_target_offset + ex4_loadmiss_target'length-1), + din => ex3_loadmiss_target(0 to 8), + dout => ex4_loadmiss_target(0 to 8) ); + +xu_iu_ex4_loadmiss_target(0 to 8) <= ex4_loadmiss_target(0 to 8); + +latch_loadmiss_target : tri_rlmreg_p + generic map (width => xu_iu_ex5_loadmiss_target'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(loadmiss_target_offset to loadmiss_target_offset + xu_iu_ex5_loadmiss_target'length-1), + scout => sov(loadmiss_target_offset to loadmiss_target_offset + xu_iu_ex5_loadmiss_target'length-1), + din => ex4_loadmiss_target(0 to 8), + dout => xu_iu_ex5_loadmiss_target(0 to 8) ); + +latch_ex4_loadmiss_target_type : tri_rlmreg_p + generic map (width => ex4_loadmiss_target_type'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_loadmiss_target_type_offset to ex4_loadmiss_target_type_offset + ex4_loadmiss_target_type'length-1), + scout => sov(ex4_loadmiss_target_type_offset to ex4_loadmiss_target_type_offset + ex4_loadmiss_target_type'length-1), + din => ex3_loadmiss_target_type(0 to 1), + dout => ex4_loadmiss_target_type(0 to 1) ); + +xu_iu_ex4_loadmiss_target_type(0 to 1) <= ex4_loadmiss_target_type(0 to 1); + +latch_loadmiss_target_type : tri_rlmreg_p + generic map (width => xu_iu_ex5_loadmiss_target_type'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(loadmiss_target_type_offset to loadmiss_target_type_offset + xu_iu_ex5_loadmiss_target_type'length-1), + scout => sov(loadmiss_target_type_offset to loadmiss_target_type_offset + xu_iu_ex5_loadmiss_target_type'length-1), + din => ex4_loadmiss_target_type(0 to 1), + dout => xu_iu_ex5_loadmiss_target_type(0 to 1) ); + +latch_ex4_loadmiss_tid : tri_rlmreg_p + generic map (width => ex4_loadmiss_tid'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ex4_loadmiss_tid_offset to ex4_loadmiss_tid_offset + ex4_loadmiss_tid'length-1), + scout => sov(ex4_loadmiss_tid_offset to ex4_loadmiss_tid_offset + ex4_loadmiss_tid'length-1), + din => ex3_loadmiss_tid(0 to 3), + dout => ex4_loadmiss_tid(0 to 3) ); + + +xu_iu_ex4_loadmiss_tid(0 to 3) <= gate_and(not ex4_drop_ld_req, ex4_loadmiss_tid(0 to 3)); + +ex4_loadmiss_tid_gated1(0 to 3) <= gate_and(not ex4_flush_load, ex4_loadmiss_tid(0 to 3)); +ex4_loadmiss_tid_gated(0 to 3) <= gate_and(not ex4_stg_flush, ex4_loadmiss_tid_gated1(0 to 3)); + +latch_loadmiss_tid : tri_rlmreg_p + generic map (width => xu_iu_ex5_loadmiss_tid'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(loadmiss_tid_offset to loadmiss_tid_offset + xu_iu_ex5_loadmiss_tid'length-1), + scout => sov(loadmiss_tid_offset to loadmiss_tid_offset + xu_iu_ex5_loadmiss_tid'length-1), + din => ex4_loadmiss_tid_gated(0 to 3), + dout => ex5_loadmiss_tid(0 to 3) ); + +xu_iu_ex5_loadmiss_tid(0 to 3) <= ex5_loadmiss_tid(0 to 3); + +-- **************************************************************************************************** +-- Signal command completion to the IU +-- **************************************************************************************************** + + + + +complete_q: for i in 0 to lmq_entries-1 generate begin + ecc_err(i) <= beat_ecc_err or data_ecc_err_l2(i); + + + ci_16B_comp_qentry(i) <= data_val_for_rel and (anaclat_tag(1 to 4) = tconv(i, 4)) and l_m_queue(i)(0) and not l_m_queue(i)(7) and not gpr_ecc_err_l2(i); + + even_beat(i) <= l_m_rel_hit_beat0_l2(i) or l_m_rel_hit_beat2_l2(i) or l_m_rel_c_i_beat0_l2(i) or + l_m_rel_hit_beat4_l2(i) or l_m_rel_hit_beat6_l2(i); + + ldm_complete_qentry(i) <= (data_val_dminus1_l2 and (tag_dminus1_l2(1 to 4) = tconv(i, 4))) and + not even_beat(i) and + (l_m_queue_addrlo(i)(58) = qw_dminus1_l2(58)) and + ((l_m_queue_addrlo(i)(57) = qw_dminus1_l2(57)) or not my_xucr0_cls) and + not gpr_updated_prev_l2(i) and not gpr_ecc_err_l2(i) and + not (l_m_queue(i)(0) and not l_m_queue(i)(7)); -- not 16B I=1 ld + + + larx_done(i) <= (l_m_queue(i)(1 to 4) = "0010") and l_m_queue(i)(6) and -- Q entry is for larx + ld_m_rel_done_no_retry(i) and not ecc_err(i); + + + complete_qentry(i) <= (ldm_complete_qentry(i) and my_xucr0_rel) or -- L2 reload in back 2 back mode + (ldm_comp_qentry_l2(i) and not my_xucr0_rel) or -- L2 reload in gap mode + ci_16B_comp_qentry(i); + +end generate; + + +latch_ldm_comp_qentry : tri_rlmreg_p + generic map (width => ldm_comp_qentry_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(ldm_comp_qentry_offset to ldm_comp_qentry_offset + ldm_comp_qentry_l2'length-1), + scout => sov(ldm_comp_qentry_offset to ldm_comp_qentry_offset + ldm_comp_qentry_l2'length-1), + din => ldm_complete_qentry(0 to lmq_entries-1), + dout => ldm_comp_qentry_l2(0 to lmq_entries-1) ); + + +compl_tid_q4: if lmq_entries=4 generate begin + complete_tid_d(0 to 3) <= gate_and(complete_qentry(0), rel_entry(0)(12 to 15)) or + gate_and(complete_qentry(1), rel_entry(1)(12 to 15)) or + gate_and(complete_qentry(2), rel_entry(2)(12 to 15)) or + gate_and(complete_qentry(3), rel_entry(3)(12 to 15)); + + larx_done_tid_d(0 to 3) <= gate_and(larx_done(0), rel_entry(0)(12 to 15)) or + gate_and(larx_done(1), rel_entry(1)(12 to 15)) or + gate_and(larx_done(2), rel_entry(2)(12 to 15)) or + gate_and(larx_done(3), rel_entry(3)(12 to 15)); + + rel_vpr_compl <= (complete_qentry(0) and rel_entry(0)(25)) or + (complete_qentry(1) and rel_entry(1)(25)) or + (complete_qentry(2) and rel_entry(2)(25)) or + (complete_qentry(3) and rel_entry(3)(25)); + + rel_compl <= complete_qentry(0) or complete_qentry(1) or complete_qentry(2) or complete_qentry(3); + +end generate; + +compl_tid_q8: if lmq_entries=8 generate begin + complete_tid_d(0 to 3) <= gate_and(complete_qentry(0), rel_entry(0)(12 to 15)) or + gate_and(complete_qentry(1), rel_entry(1)(12 to 15)) or + gate_and(complete_qentry(2), rel_entry(2)(12 to 15)) or + gate_and(complete_qentry(3), rel_entry(3)(12 to 15)) or + gate_and(complete_qentry(4), rel_entry(4)(12 to 15)) or + gate_and(complete_qentry(5), rel_entry(5)(12 to 15)) or + gate_and(complete_qentry(6), rel_entry(6)(12 to 15)) or + gate_and(complete_qentry(7), rel_entry(7)(12 to 15)); + + larx_done_tid_d(0 to 3) <= gate_and(larx_done(0), rel_entry(0)(12 to 15)) or + gate_and(larx_done(1), rel_entry(1)(12 to 15)) or + gate_and(larx_done(2), rel_entry(2)(12 to 15)) or + gate_and(larx_done(3), rel_entry(3)(12 to 15)) or + gate_and(larx_done(4), rel_entry(4)(12 to 15)) or + gate_and(larx_done(5), rel_entry(5)(12 to 15)) or + gate_and(larx_done(6), rel_entry(6)(12 to 15)) or + gate_and(larx_done(7), rel_entry(7)(12 to 15)); + + rel_vpr_compl <= (complete_qentry(0) and rel_entry(0)(25)) or + (complete_qentry(1) and rel_entry(1)(25)) or + (complete_qentry(2) and rel_entry(2)(25)) or + (complete_qentry(3) and rel_entry(3)(25)) or + (complete_qentry(4) and rel_entry(4)(25)) or + (complete_qentry(5) and rel_entry(5)(25)) or + (complete_qentry(6) and rel_entry(6)(25)) or + (complete_qentry(7) and rel_entry(7)(25)); + + rel_compl <= complete_qentry(0) or complete_qentry(1) or complete_qentry(2) or complete_qentry(3) or + complete_qentry(4) or complete_qentry(5) or complete_qentry(6) or complete_qentry(7); + +end generate; + +complete_target_type_d(0 to 1) <= "01" when rel_vpr_compl = '1' else + "10" when rel_compl = '1' else + "00"; + +latch_complete_qentry : tri_rlmreg_p + generic map (width => xu_iu_complete_qentry'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(complete_qentry_offset to complete_qentry_offset + xu_iu_complete_qentry'length-1), + scout => sov(complete_qentry_offset to complete_qentry_offset + xu_iu_complete_qentry'length-1), + din => complete_qentry(0 to lmq_entries-1), + dout => xu_iu_complete_qentry(0 to lmq_entries-1) ); + +latch_complete_tid : tri_rlmreg_p + generic map (width => xu_iu_complete_tid'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(complete_tid_offset to complete_tid_offset + xu_iu_complete_tid'length-1), + scout => sov(complete_tid_offset to complete_tid_offset + xu_iu_complete_tid'length-1), + din => complete_tid_d(0 to 3), + dout => xu_iu_complete_tid(0 to 3) ); + +latch_complete_target_type : tri_rlmreg_p + generic map (width => xu_iu_complete_target_type'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(complete_target_type_offset to complete_target_type_offset + xu_iu_complete_target_type'length-1), + scout => sov(complete_target_type_offset to complete_target_type_offset + xu_iu_complete_target_type'length-1), + din => complete_target_type_d(0 to 1), + dout => xu_iu_complete_target_type(0 to 1) ); + +latch_larx_done_tid : tri_rlmreg_p + generic map (width => xu_iu_larx_done_tid'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(larx_done_tid_offset to larx_done_tid_offset + xu_iu_larx_done_tid'length-1), + scout => sov(larx_done_tid_offset to larx_done_tid_offset + xu_iu_larx_done_tid'length-1), + din => larx_done_tid_d(0 to 3), + dout => larx_done_tid_l2(0 to 3) ); + +xu_iu_larx_done_tid <= larx_done_tid_l2; + +-- **************************************************************************************************** +-- Reload interface to the L1 D-Cache +-- **************************************************************************************************** + + + +ldq_rel_addr_early(64-real_data_add to 57) <= rel_addr_d(64-real_data_add to 57); + +ldq_rel_addr(64-real_data_add to 57) <= rel_addr_l2(64-real_data_add to 57); +ldq_rel_addr(58) <= qw_l2(58); + + +ldq_rel_tag_early(2 to 4) <= tag_dminus1_cpy_l2(2 to 4); +ldq_rel_tag(2 to 4) <= rel_tag_l2(2 to 4); + +ldq_rel_axu_val <= rel_vpr_val_l2; + + +my_noncache_beat_p: process (l_m_rel_val_c_i_dly, rel_tag_l2) + variable b: std_ulogic; +begin + b := '0'; + for i in 0 to lmq_entries-1 loop + b := (l_m_rel_val_c_i_dly(i) and (rel_tag_l2(1 to 4) = tconv(i, 4)) ) or b; + end loop; + my_noncache_beat <= b; +end process; + +update_gpr <= not rel_dcbt_l2 and (rel_addr_l2(58) = qw_l2(58)) and reld_data_vld_l2 and not ldq_rel_retry_val_dly_l2 and not rel_tag_l2(1) and + (my_beat1 or my_beat_last_l2 or my_beat_mid or my_noncache_beat) and + ((rel_addr_l2(57) = qw_l2(57)) or not my_xucr0_cls); + +-- latch update_gpr into the next cycle so that ecc error can be checked +latch_update_gpr : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(update_gpr_offset to update_gpr_offset), + scout => sov(update_gpr_offset to update_gpr_offset), + din(0) => update_gpr, + dout(0) => update_gpr_l2 ); +latch_rel_beat_crit_qw : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(rel_beat_crit_qw_offset to rel_beat_crit_qw_offset), + scout => sov(rel_beat_crit_qw_offset to rel_beat_crit_qw_offset), + din(0) => update_gpr, + dout(0) => ldq_rel_beat_crit_qw ); + +gpr_updated: for i in 0 to lmq_entries-1 generate begin + set_gpr_updated_prev(i) <= update_gpr_l2 and not ecc_err(i) and + (rel_tag_dplus1_l2(1 to 4) = tconv(i, 4)) and + not (ld_m_rel_done_l2(i) and not rel_done_ecc_err); -- don't set if in last cycle of data xfer + -- and no previous ecc errors + + gpr_updated_prev_d(i) <= set_gpr_updated_prev(i) or + (gpr_updated_prev_l2(i) and not reset_lmq_entry(i) ); + + gpr_updated_dly1_d(i) <= gpr_updated_prev_l2(i) and not reset_lmq_entry(i); + + gpr_updated_dly2_d(i) <= gpr_updated_dly1_l2(i) and not reset_lmq_entry(i); + + + set_gpr_ecc_err(i) <= update_gpr_l2 and ecc_err(i) and + (rel_tag_dplus1_l2(1 to 4) = tconv(i, 4)); + + reset_gpr_ecc_err(i) <= update_gpr_l2 and (not ecc_err(i) or ld_m_rel_done_dly2_l2(i)) and + (rel_tag_dplus1_l2(1 to 4) = tconv(i, 4)); + + gpr_ecc_err_d(i) <= (set_gpr_ecc_err(i) and not reset_gpr_ecc_err(i)) or + (not reset_gpr_ecc_err(i) and gpr_ecc_err_l2(i)); + +end generate; + +-- set a latch to remember that the gpr has been updated previously +latch_gpr_updated_prev : tri_rlmreg_p + generic map (width => gpr_updated_prev_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(gpr_updated_prev_offset to gpr_updated_prev_offset + gpr_updated_prev_l2'length-1), + scout => sov(gpr_updated_prev_offset to gpr_updated_prev_offset + gpr_updated_prev_l2'length-1), + din => gpr_updated_prev_d(0 to lmq_entries-1), + dout => gpr_updated_prev_l2(0 to lmq_entries-1) ); + +latch_gpr_updated_dly1 : tri_rlmreg_p + generic map (width => gpr_updated_dly1_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(gpr_updated_dly1_offset to gpr_updated_dly1_offset + gpr_updated_dly1_l2'length-1), + scout => sov(gpr_updated_dly1_offset to gpr_updated_dly1_offset + gpr_updated_dly1_l2'length-1), + din => gpr_updated_dly1_d(0 to lmq_entries-1), + dout => gpr_updated_dly1_l2(0 to lmq_entries-1) ); + +latch_gpr_updated_dly2 : tri_rlmreg_p + generic map (width => gpr_updated_dly2_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(gpr_updated_dly2_offset to gpr_updated_dly2_offset + gpr_updated_dly2_l2'length-1), + scout => sov(gpr_updated_dly2_offset to gpr_updated_dly2_offset + gpr_updated_dly2_l2'length-1), + din => gpr_updated_dly2_d(0 to lmq_entries-1), + dout => gpr_updated_dly2_l2(0 to lmq_entries-1) ); + +latch_gpr_ecc_err : tri_rlmreg_p + generic map (width => gpr_ecc_err_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(gpr_ecc_err_offset to gpr_ecc_err_offset + gpr_ecc_err_l2'length-1), + scout => sov(gpr_ecc_err_offset to gpr_ecc_err_offset + gpr_ecc_err_l2'length-1), + din => gpr_ecc_err_d(0 to lmq_entries-1), + dout => gpr_ecc_err_l2(0 to lmq_entries-1) ); + + +sel_gpr_upd_q4: if lmq_entries=4 generate begin + selectedQ_gpr_update_prev <= (gpr_updated_prev_l2(0) and (rel_tag_dplus1_l2(1 to 4) = "0000")) or + (gpr_updated_prev_l2(1) and (rel_tag_dplus1_l2(1 to 4) = "0001")) or + (gpr_updated_prev_l2(2) and (rel_tag_dplus1_l2(1 to 4) = "0010")) or + (gpr_updated_prev_l2(3) and (rel_tag_dplus1_l2(1 to 4) = "0011")); + + selectedQ_ecc_err <= (data_ecc_err_l2(0) and not ld_m_rel_done_dly2_l2(0) and (rel_tag_dplus1_l2(1 to 4) = "0000")) or + (data_ecc_err_l2(1) and not ld_m_rel_done_dly2_l2(1) and (rel_tag_dplus1_l2(1 to 4) = "0001")) or + (data_ecc_err_l2(2) and not ld_m_rel_done_dly2_l2(2) and (rel_tag_dplus1_l2(1 to 4) = "0010")) or + (data_ecc_err_l2(3) and not ld_m_rel_done_dly2_l2(3) and (rel_tag_dplus1_l2(1 to 4) = "0011")); +end generate; + +sel_gpr_upd_q8: if lmq_entries=8 generate begin + selectedQ_gpr_update_prev <= (gpr_updated_prev_l2(0) and (rel_tag_dplus1_l2(1 to 4) = "0000")) or + (gpr_updated_prev_l2(1) and (rel_tag_dplus1_l2(1 to 4) = "0001")) or + (gpr_updated_prev_l2(2) and (rel_tag_dplus1_l2(1 to 4) = "0010")) or + (gpr_updated_prev_l2(3) and (rel_tag_dplus1_l2(1 to 4) = "0011")) or + (gpr_updated_prev_l2(4) and (rel_tag_dplus1_l2(1 to 4) = "0100")) or + (gpr_updated_prev_l2(5) and (rel_tag_dplus1_l2(1 to 4) = "0101")) or + (gpr_updated_prev_l2(6) and (rel_tag_dplus1_l2(1 to 4) = "0110")) or + (gpr_updated_prev_l2(7) and (rel_tag_dplus1_l2(1 to 4) = "0111")); + + selectedQ_ecc_err <= (data_ecc_err_l2(0) and not ld_m_rel_done_dly2_l2(0) and (rel_tag_dplus1_l2(1 to 4) = "0000")) or + (data_ecc_err_l2(1) and not ld_m_rel_done_dly2_l2(1) and (rel_tag_dplus1_l2(1 to 4) = "0001")) or + (data_ecc_err_l2(2) and not ld_m_rel_done_dly2_l2(2) and (rel_tag_dplus1_l2(1 to 4) = "0010")) or + (data_ecc_err_l2(3) and not ld_m_rel_done_dly2_l2(3) and (rel_tag_dplus1_l2(1 to 4) = "0011")) or + (data_ecc_err_l2(4) and not ld_m_rel_done_dly2_l2(4) and (rel_tag_dplus1_l2(1 to 4) = "0100")) or + (data_ecc_err_l2(5) and not ld_m_rel_done_dly2_l2(5) and (rel_tag_dplus1_l2(1 to 4) = "0101")) or + (data_ecc_err_l2(6) and not ld_m_rel_done_dly2_l2(6) and (rel_tag_dplus1_l2(1 to 4) = "0110")) or + (data_ecc_err_l2(7) and not ld_m_rel_done_dly2_l2(7) and (rel_tag_dplus1_l2(1 to 4) = "0111")); +end generate; + +ldq_rel_upd_gpr_buf <= update_gpr_l2 and not beat_ecc_err and + not selectedQ_ecc_err and + not selectedQ_gpr_update_prev; +ldq_rel_upd_gpr <= ldq_rel_upd_gpr_buf; + +ldq_rel_ecc_err <= beat_ecc_err or rel_done_ecc_err; + +rel_beat_crit_qw_block_d <= beat_ecc_err or selectedQ_ecc_err or selectedQ_gpr_update_prev; +latch_rel_beat_crit_qw_block : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => ldq_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(rel_beat_crit_qw_block_offset to rel_beat_crit_qw_block_offset), + scout => sov(rel_beat_crit_qw_block_offset to rel_beat_crit_qw_block_offset), + din(0) => rel_beat_crit_qw_block_d, + dout(0) => ldq_rel_beat_crit_qw_block ); + +flush_gpr_ecc_err: process(gpr_ecc_err_l2, l_m_queue(0)(18 to 21), l_m_queue(1)(18 to 21), l_m_queue(2)(18 to 21), l_m_queue(3)(18 to 21), l_m_queue(4)(18 to 21), l_m_queue(5)(18 to 21), l_m_queue(6)(18 to 21), l_m_queue(7)(18 to 21)) + variable b: std_ulogic_vector(0 to 3); +begin + b := "0000"; + for i in 0 to lmq_entries-1 loop + b := gate_and(gpr_ecc_err_l2(i), l_m_queue(i)(18 to 21)) or b; + end loop; + gpr_ecc_err_flush_tid(0 to 3) <= b; +end process; + + + + +rel_cacheable_p: for i in 0 to lmq_entries-1 generate begin + rel_cacheable(i) <= not rel_entry(i)(0) and not rel_entry(i)(29) and not lmq_back_invalidated_l2(i); + + rel_set_val(i) <= ld_m_rel_done_l2(i) and -- reload is done + not data_ecc_err_l2(i) and not data_ecc_ue_l2(i) and -- no previous ecc errors + rel_cacheable(i); -- entry is for cacheable data +end generate; + +rel_set_val_or_p: process (rel_set_val) + variable b: std_ulogic; +begin + b := '0'; + for i in 0 to lmq_entries-1 loop + b := rel_set_val(i) or b; + end loop; + rel_set_val_or <= b; +end process; + + +ldq_rel_set_val_buf <= rel_set_val_or and -- reload is done + not beat_ecc_err and not (anaclat_ecc_err_ue and rel_intf_v_dplus1_l2) and -- no ecc errors on last transfer + not rel_l2only_dly_l2 and not pe_recov_state_l2; + +ldq_rel_set_val <= ldq_rel_set_val_buf; + +ldq_rel_le_mode <= rel_le_mode_l2; +ldq_rel_rot_sel <= rel_rot_sel_l2; +ldq_rel_algebraic <= rel_algebraic_l2; +ldq_rel_lock_en <= rel_lock_en_l2; +ldq_rel_classid <= rel_classid_l2; +ldq_rel_dvc1_en <= rel_dvc1_l2; +ldq_rel_dvc2_en <= rel_dvc2_l2; +ldq_rel_watch_en <= rel_watch_en_l2; + + + +rel_bi_p: process (lmq_back_invalidated_l2, rel_tag_l2) + variable b: std_ulogic; +begin + b := '0'; + for i in 0 to lmq_entries-1 loop + b := (lmq_back_invalidated_l2(i) and (rel_tag_l2(1 to 4) = tconv(i, 4)) ) or b; + end loop; + ldq_rel_back_invalidated <= b; +end process; + + + + + + +-- ***************************************************************** +-- gather 16 byte reload data to give 32 bytes to the L1 D-cache + +rel_data_a2mode: if a2mode=1 generate begin + set_rel_A_data <= reld_data_vld_l2 and send_rel_A_data_l2; + set_rel_B_data <= reld_data_vld_l2 and not send_rel_A_data_l2; + + rel_A_data_d(0 to 127) <= anaclat_data(0 to 127) when set_rel_A_data = '1' else + rel_A_data_l2(0 to 127); + + rel_B_data_d(0 to 127) <= anaclat_data(0 to 127) when set_rel_B_data = '1' else + rel_B_data_l2(0 to 127); +end generate; + +rel_data_nota2mode: if a2mode=0 generate begin + rel_A_data_d(0 to 127) <= anaclat_data(0 to 127); + + -- tie unused signals + set_rel_A_data <= '0'; + set_rel_B_data <= '0'; + rel_B_data_d(0 to 127) <= (others=>'0'); + rel_B_data_l2(0 to 127) <= (others=>'0'); + +end generate; + +latch_rel_A_data : tri_rlmreg_p + generic map (width => rel_A_data_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dplus1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(rel_A_data_offset to rel_A_data_offset + rel_A_data_l2'length-1), + scout => sov(rel_A_data_offset to rel_A_data_offset + rel_A_data_l2'length-1), + din => rel_A_data_d(0 to 127), + dout => rel_A_data_l2(0 to 127) ); + +rel_B_data_a2mode: if a2mode=1 generate begin + latch_rel_B_data : tri_rlmreg_p + generic map (width => rel_B_data_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => dplus1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(rel_B_data_offset to rel_B_data_offset + rel_B_data_l2'length-1), + scout => sov(rel_B_data_offset to rel_B_data_offset + rel_B_data_l2'length-1), + din => rel_B_data_d(0 to 127), + dout => rel_B_data_l2(0 to 127) ); +end generate; + +rel_data_256_a2mode: if a2mode=1 generate begin + send_rel_A_data_d <= not send_rel_A_data_l2 or my_xucr0_rel; -- always use rel_A when in back to back l2 mode + -- otherwise toggle between A and B + + latch_send_rel_A_data : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(send_rel_A_data_offset to send_rel_A_data_offset), + scout => sov(send_rel_A_data_offset to send_rel_A_data_offset), + din(0) => send_rel_A_data_d, + dout(0) => send_rel_A_data_l2 ); + + ldq_rel_256_data(0 to 127) <= anaclat_data(0 to 127) when qw_l2(59) = '0' else + rel_A_data_l2(0 to 127) when send_rel_A_data_l2 = '1' else + rel_B_data_l2(0 to 127); + + ldq_rel_256_data(128 to 255) <= anaclat_data(0 to 127) when qw_l2(59) = '1' else + rel_A_data_l2(0 to 127) when send_rel_A_data_l2 = '1' else + rel_B_data_l2(0 to 127); +end generate; + + +rel_data_256_nota2mode: if a2mode=0 generate begin + send_rel_A_data_d <= '0'; -- tie unused signals + send_rel_A_data_l2 <= '0'; -- tie unused signals + + ldq_rel_256_data(0 to 127) <= anaclat_data(0 to 127) when qw_l2(59) = '0' else + rel_A_data_l2(0 to 127); + + ldq_rel_256_data(128 to 255) <= rel_A_data_l2(0 to 127) when qw_l2(59) = '0' else + anaclat_data(0 to 127); +end generate; + +-- signal to MMU when the load miss queue is empty + +lmq_empty <= ld_rel_val_l2(0 to lmq_entries-1) = (0 to lmq_entries-1 => '0'); + +xu_mm_lmq_stq_empty_d <= lmq_empty and not st_entry0_val_l2 and not ex4_st_val_l2 and not pe_recov_state_l2; + +latch_lmq_stq_empty : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(lmq_stq_empty_offset to lmq_stq_empty_offset), + scout => sov(lmq_stq_empty_offset to lmq_stq_empty_offset), + din(0) => xu_mm_lmq_stq_empty_d, + dout(0) => xu_mm_lmq_stq_empty ); + +-- signal when each thread is quiesced + +lmq_q: process(ld_rel_val_l2, l_m_queue(0)(18 to 21), l_m_queue(1)(18 to 21), l_m_queue(2)(18 to 21), l_m_queue(3)(18 to 21), l_m_queue(4)(18 to 21), l_m_queue(5)(18 to 21), l_m_queue(6)(18 to 21), l_m_queue(7)(18 to 21)) + variable b: std_ulogic_vector(0 to 3); +begin + b := "1111"; + for i in 0 to lmq_entries-1 loop + b := not (gate_and(ld_rel_val_l2(i), l_m_queue(i)(18 to 21)) ) and b; + end loop; + lmq_quiesce(0 to 3) <= b; +end process; + +mmu_quiesce(0 to 3) <= not (gate_and(mmu_q_val_l2, mmu_q_entry_l2(2 to 5)) ); + +stq_quiesce(0 to 3) <= not (gate_and(st_entry0_val_l2, s_m_queue0(38 to 41)) ); + +quiesce_d(0 to 3) <= gate_and(not pe_recov_state_l2, stq_quiesce(0 to 3) and lmq_quiesce(0 to 3) and mmu_quiesce(0 to 3)); + +latch_quiesce : tri_rlmreg_p + generic map (width => lsu_xu_quiesce'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(quiesce_offset to quiesce_offset + lsu_xu_quiesce'length-1), + scout => sov(quiesce_offset to quiesce_offset + lsu_xu_quiesce'length-1), + din => quiesce_d(0 to 3), + dout => lsu_xu_quiesce(0 to 3) ); + +-- send back invalidates to the D-Cache + +is2_l2_inv_val <= back_inv_val_l2; + +is2_l2_inv_p_addr <= anaclat_back_inv_addr(64-real_data_add to 63-cl_size); + + +-- ********************************************************************************8 +-- send L2 ecc errors to pervasive: + + +err_l2intrf_ecc_d <= beat_ecc_err and rel_intf_v_dplus1_l2; + +err_l2intrf_ue_d <= anaclat_ecc_err_ue and rel_intf_v_dplus1_l2; + +latch_err_l2intrf_ecc : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(err_l2intrf_ecc_offset to err_l2intrf_ecc_offset), + scout => sov(err_l2intrf_ecc_offset to err_l2intrf_ecc_offset), + din(0) => err_l2intrf_ecc_d, + dout(0) => err_l2intrf_ecc_l2 ); + +latch_err_l2intrf_ue : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(err_l2intrf_ue_offset to err_l2intrf_ue_offset), + scout => sov(err_l2intrf_ue_offset to err_l2intrf_ue_offset), + din(0) => err_l2intrf_ue_d, + dout(0) => err_l2intrf_ue_l2 ); + +invld_reld: process(ld_rel_val_l2, tag_dminus1_l2, data_val_dminus1_l2) + variable b: std_ulogic; +begin + b := '0'; + for i in 0 to lmq_entries-1 loop + b := (data_val_dminus1_l2 and (tag_dminus1_l2(1 to 4)=tconv(i,4)) and not ld_rel_val_l2(i)) or b; + end loop; + err_invld_reld_d <= b; +end process; + +latch_err_invld_reld : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(err_invld_reld_offset to err_invld_reld_offset), + scout => sov(err_invld_reld_offset to err_invld_reld_offset), + din(0) => err_invld_reld_d, + dout(0) => err_invld_reld_l2 ); + +-- create error signal we get too many load or store credit pops + +err_cred_overrun_d <= store_cmd_count_l2(0 to 1)="11" or load_cmd_count_l2(0 to 1)="11"; + +latch_cred_overrun : tri_rlmreg_p + generic map (width => 1, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(cred_overrun_offset to cred_overrun_offset), + scout => sov(cred_overrun_offset to cred_overrun_offset), + din(0) => err_cred_overrun_d, + dout(0) => err_cred_overrun_l2); + + +err_rpt : tri_direct_err_rpt + generic map (width => 4) + port map (vd => vdd, + gd => gnd, + err_in(0) => err_l2intrf_ecc_l2, + err_in(1) => err_l2intrf_ue_l2, + err_in(2) => err_invld_reld_l2, + err_in(3) => err_cred_overrun_l2, + err_out(0) => xu_pc_err_l2intrf_ecc, + err_out(1) => xu_pc_err_l2intrf_ue, + err_out(2) => xu_pc_err_invld_reld, + err_out(3) => xu_pc_err_l2credit_overrun); + + +-- ********************************************************************************* +-- Repower Latches for BXQ + +latch_reld_ditc_pop : tri_rlmreg_p + generic map (width => ac_an_reld_ditc_pop_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(reld_ditc_pop_offset to reld_ditc_pop_offset + ac_an_reld_ditc_pop_q'length-1), + scout => sov(reld_ditc_pop_offset to reld_ditc_pop_offset + ac_an_reld_ditc_pop_q'length-1), + din => ac_an_reld_ditc_pop_int(0 to 3), + dout => ac_an_reld_ditc_pop_q(0 to 3) ); + +latch_bx_ib_empty : tri_rlmreg_p + generic map (width => bx_ib_empty_q'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(bx_ib_empty_offset to bx_ib_empty_offset + bx_ib_empty_q'length-1), + scout => sov(bx_ib_empty_offset to bx_ib_empty_offset + bx_ib_empty_q'length-1), + din => bx_ib_empty_int(0 to 3), + dout => bx_ib_empty_q(0 to 3) ); + + + +-- ********************************************************************************* +-- Spare latches + +spare_0_lcb: entity tri.tri_lcbnd(tri_lcbnd) + port map(vd => vdd, + gd => gnd, + act => '0', + nclk => nclk, + forcee => func_sl_force, + thold_b => func_sl_thold_0_b, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + sg => sg_0, + lclk => spare_0_lclk, + d1clk => spare_0_d1clk, + d2clk => spare_0_d2clk); +spare_0_latch : entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width => spare_0_l2'length, expand_type => expand_type, btr => "NLI0001_X2_A12TH", init=>(spare_0_l2'range=>'0')) + port map (vd => vdd, gd => gnd, + LCLK => spare_0_lclk, + D1CLK => spare_0_d1clk, + D2CLK => spare_0_d2clk, + SCANIN => siv(spare_0_offset to spare_0_offset + spare_0_l2'length-1), + SCANOUT => sov(spare_0_offset to spare_0_offset + spare_0_l2'length-1), + D => spare_0_d, + QB => spare_0_l2); +spare_0_d <= not spare_0_l2; + +spare_1_lcb: entity tri.tri_lcbnd(tri_lcbnd) + port map(vd => vdd, + gd => gnd, + act => '0', + nclk => nclk, + forcee => func_sl_force, + thold_b => func_sl_thold_0_b, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + sg => sg_0, + lclk => spare_1_lclk, + d1clk => spare_1_d1clk, + d2clk => spare_1_d2clk); +spare_1_latch : entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width => spare_1_l2'length, expand_type => expand_type, btr => "NLI0001_X2_A12TH", init=>(spare_1_l2'range=>'0')) + port map (vd => vdd, gd => gnd, + LCLK => spare_1_lclk, + D1CLK => spare_1_d1clk, + D2CLK => spare_1_d2clk, + SCANIN => siv(spare_1_offset to spare_1_offset + spare_1_l2'length-1), + SCANOUT => sov(spare_1_offset to spare_1_offset + spare_1_l2'length-1), + D => spare_1_d, + QB => spare_1_l2); +spare_1_d <= not spare_1_l2; + + +spare_4_lcb: entity tri.tri_lcbnd(tri_lcbnd) + port map(vd => vdd, + gd => gnd, + act => '0', + nclk => nclk, + forcee => func_sl_force, + thold_b => func_sl_thold_0_b, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + sg => sg_0, + lclk => spare_4_lclk, + d1clk => spare_4_d1clk, + d2clk => spare_4_d2clk); +spare_4_latch : entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width => spare_4_l2'length, expand_type => expand_type, btr => "NLI0001_X2_A12TH", init=>(spare_4_l2'range=>'0')) + port map (vd => vdd, gd => gnd, + LCLK => spare_4_lclk, + D1CLK => spare_4_d1clk, + D2CLK => spare_4_d2clk, + SCANIN => siv(spare_4_offset to spare_4_offset + spare_4_l2'length-1), + SCANOUT => sov(spare_4_offset to spare_4_offset + spare_4_l2'length-1), + D => spare_4_d, + QB => spare_4_l2); +spare_4_d <= not spare_4_l2; + + + +-- ********************************************************************************* +-- Debug signals + +dbg_d(0 to 7) <= l_q_rd_en; +dbg_d(8 to 11) <= ex4st_hit_ex6_recov & + stq_hit_ex6_recov & + blk_st_for_pe_recov & + blk_st_cred_pop; +dbg_d(12 to 13) <= lq_rd_en_is_ex5 & lq_rd_en_is_ex6; +dbg_d(14) <= selected_entry_flushed; +dbg_d(15 to 26) <= cmd_type_st(0 to 5) & cmd_type_ld(0 to 5); +dbg_d(27) <= load_flushed; +dbg_d(28) <= rd_seq_num_skip; +dbg_d(29) <= nxt_st_cred_tkn; +dbg_d(30) <= cred_pop; +dbg_d(31) <= store_sent; +dbg_d(32) <= ex4_flush_store; +dbg_d(33) <= mmu_st_sent; +dbg_d(34 to 37) <= i_f_q0_sent & i_f_q1_sent & i_f_q2_sent & i_f_q3_sent; +dbg_d(38) <= iu_sent_val; +dbg_d(39) <= mmu_sent; +dbg_d(40 to 40+lmq_entries-1) <= complete_qentry; + +latch_dbg : tri_rlmreg_p + generic map (width => dbg_l2'length, init => 0, expand_type => expand_type) + port map (nclk => nclk, + act => '1', + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + vd => vdd, + gd => gnd, + scin => siv(dbg_offset to dbg_offset + dbg_l2'length-1), + scout => sov(dbg_offset to dbg_offset + dbg_l2'length-1), + din => dbg_d, + dout => dbg_l2 ); + +lmq_dbg_l2req <= l2req_l2 & --(0) + l2req_ld_core_tag_l2 & --(1:5) + l2req_ra_l2 & --(6:47) + l2req_st_byte_enbl_l2(0 to 15) & --(48:63) + l2req_thread_l2 & --(64:66) + l2req_ttype_l2 & --(67:72) + l2req_wimg_l2 & --(73:76) + l2req_endian_l2 & --(77) + l2req_user_l2 & --(78:81) + l2req_ld_xfr_len_l2 & --(82:84) + ex6_st_data_l2(0 to 127); --(85:212) + +lmq_dbg_rel <= anaclat_data_coming & --(0) + anaclat_data_val & --(1) + anaclat_reld_crit_qw & --(2) + anaclat_ditc & --(3) + anaclat_l1_dump & --(4) + anaclat_tag(1 to 4) & --(5:8) + anaclat_qw(58 to 59) & --(9:10) + anaclat_ecc_err & --(11) + anaclat_ecc_err_ue & --(12) + anaclat_data(0 to 127); --(13:140) + +lmq_dbg_binv <= anaclat_back_inv & --(0) + anaclat_back_inv_addr & --(1:42) + anaclat_back_inv_target_1 & --(43) + anaclat_back_inv_target_4; --(44) + +lmq_dbg_pops <= anaclat_ld_pop & --(0) + anaclat_st_gather & --(1) + anaclat_st_pop & --(2) + anaclat_st_pop_thrd; --(3:5) + +lmq_dbg_dcache_pe <= l2req_resend_l2 & -- 1 + l2req_recycle_l2 & -- 2 + ex6_ld_recov_val_l2 & -- 3 + ex6_ld_recov_extra_l2(0) & -- 4 + ex7_ld_recov_val_l2 & -- 5 + ex7_ld_recov_extra_l2(0) & -- 6 + ex7_ld_recov_l2(1 to 6) & -- 7:12 + ex7_ld_recov_l2(18 to 21) & -- 13:16 + ex7_ld_recov_l2(53 to (53+(real_data_add-2))) & -- 17:57 + st_hit_recov_ld_l2 & -- 58 + pe_recov_state_l2 & -- 59 + blk_ld_for_pe_recov_l2; -- 60 + +lmq_dbg_grp0 <= l_m_rel_hit_beat0_l2 & --(0:7) + l_m_rel_hit_beat1_l2 & --(8:15) + l_m_rel_hit_beat2_l2 & --(16:23) + l_m_rel_hit_beat3_l2 & --(24:31) + l_m_rel_val_c_i_dly & --(32:39) + lmq_back_invalidated_l2(0 to lmq_entries-1) & --(40:47) + dbg_l2(40 to 40+lmq_entries-1) & --(48:55) + ldq_retry_l2(0 to lmq_entries-1) & --(56:63) + retry_started_l2(0 to lmq_entries-1) & --(64:71) + gpr_ecc_err_l2(0 to lmq_entries-1) & --(78:85) + "00"; --(86:87) + +lmq_dbg_grp1 <= l_m_rel_hit_beat0_l2 & --(0:7) + l_m_rel_hit_beat1_l2 & --(8:15) + l_m_rel_hit_beat2_l2 & --(16:23) + l_m_rel_hit_beat3_l2 & --(24:31) + l_m_rel_val_c_i_dly & --(32:39) + gpr_ecc_err_l2(0 to lmq_entries-1) & --(40:47) + data_ecc_err_l2(0 to lmq_entries-1) & --(48:55) + data_ecc_ue_l2(0 to lmq_entries-1) & --(56:63) + gpr_updated_prev_l2(0 to lmq_entries-1) & --(64:71) + anaclat_data_val & --(78) + anaclat_reld_crit_qw & --(79) + anaclat_tag(1 to 4) & --(80:83) + anaclat_qw(58 to 59) & --(84:85) + anaclat_ecc_err & --(86) + anaclat_ecc_err_ue; --(87) + +lmq_dbg_grp2 <= ex4_l2cmdq_flush_l2(0) & --(0) + ex4_l2cmdq_flush_l2(3) & --(1) + ex4_drop_ld_req & --(2) + ex5_flush_l2 & --(3) + ex5_stg_flush & --(4) + dbg_l2(21 to 26) & --(5:10) + ex4_loadmiss_qentry(0 to lmq_entries-1) & --(11:18) + ld_entry_val_l2(0 to lmq_entries-1) & --(19:26) + ld_rel_val_l2(0 to lmq_entries-1) & --(27:34) + ex4_lmq_cpy_l2(0 to lmq_entries-1) & --(35:42) + send_if_req_l2 & --(43) + send_ld_req_l2 & --(44) + send_mm_req_l2 & --(45) + load_cmd_count_l2 & --(46:49) + load_sent_dbglat_l2 & --(50) + dbg_l2(27) & --(51) + dbg_l2(14) & --(52) + ex6_load_sent_l2 & --(53) + ex6_flush_l2 & --(54) + cmd_seq_l2 & --(55:59) + dbg_l2(0 to 7) & --(60:67) l_q_rd_en + dbg_l2(28) & --(68) + dbg_l2(12) & --(69) + dbg_l2(13) & --(70) + l_m_q_hit_st_l2(0 to lmq_entries-1) & --(71:78) + lmq_drop_rel_l2(0 to lmq_entries-1) & --(79:86) + ex4_l2cmdq_flush_l2(4); --(87) + +lmq_dbg_grp3 <= ex4_l2cmdq_flush_l2(2) & --(0) + ex4_l2cmdq_flush_l2(1) & --(1) + ex4_l2cmdq_flush_l2(0) & --(2) + l_m_fnd_stg & --(3) + ex5_flush_l2 & --(4) + ex5_stg_flush & --(5) + ex4_st_val_l2 & --(6) + st_entry0_val_l2 & --(7) + s_m_queue0(0 to 5) & --(8:13) + s_m_queue0(58 to (58+real_data_add-6-1)) & --(14:49) + store_cmd_count_l2 & --(50:55) + dbg_l2(29) & --(56) + dbg_l2(30) & --(57) + ex5_sel_st_req & --(58) + dbg_l2(31) & --(59) + dbg_l2(32) & --(60) + ex5_flush_store & --(61) + ex6_store_sent_l2 & --(62) + ex6_flush_l2 & --(63) + l2req_l2 & --(64) + l2req_thread_l2 & --(65:67) + l2req_ttype_l2 & --(68:73) + ob_req_val_l2 & --(74) + ob_ditc_val_l2 & --(75) + bx_cmd_stall_l2 & --(76) + bx_cmd_sent_l2 & --(77) + dbg_l2(8 to 11) & + st_recycle_v_l2 & --(82) + l2req_resend_l2 & --(83) + l2req_recycle_l2 & --(84) + dbg_l2(33) & --(85) + mmu_q_val & --(86) + mmu_q_entry_l2(0); --(87) + +lmq_dbg_grp4 <= ifetch_req_l2 & --(0) + ifetch_ra_l2 & --(1:38) + ifetch_thread_l2 & --(39:42) + i_f_q0_val_l2 & --(43) + i_f_q1_val_l2 & --(44) + i_f_q2_val_l2 & --(45) + i_f_q3_val_l2 & --(46) + send_if_req_l2 & --(47) + send_ld_req_l2 & --(48) + send_mm_req_l2 & --(49) + dbg_l2(34 to 37) & --(50:53) + dbg_l2(38) & --(54) + l2req_l2 & --(55) + l2req_thread_l2 & --(56:58) + l2req_ttype_l2 & --(59:64) + l2req_ld_core_tag_l2 & --(65:69) + l2req_wimg_l2 & --(70:73) + anaclat_data_val & --(74) + anaclat_reld_crit_qw & --(75) + anaclat_tag(1 to 4) & --(76:79) + anaclat_qw(58 to 59) & --(80:81) + anaclat_ecc_err & --(82) + anaclat_ecc_err_ue & --(83) + load_credit & --(84) + store_credit & --(85) + ex5_sel_st_req & --(86) + '0' ; --(87) + +lmq_dbg_grp5 <= mm_req_val_l2 & --(0) + mmu_q_val_l2 & --(1) + mmu_q_entry_l2 & --(2:69) + send_if_req_l2 & --(70) + send_ld_req_l2 & --(71) + send_mm_req_l2 & --(72) + dbg_l2(39) & --(73) + l2req_l2 & --(74) + l2req_thread_l2 & --(75:77) + l2req_ttype_l2 & --(78:83) + "0000"; + +lmq_dbg_grp6 <= ex3_stg_flush & --(0) + ex4_l2cmdq_flush_l2(0) & --(1) + ex4_l2cmdq_flush_l2(2) & --(2) + ex4_l2cmdq_flush_l2(1) & --(3) + ex4_l2cmdq_flush_l2(3) & --(4) + ex4_drop_ld_req & --(5) + l_m_fnd_stg & --(6) + ex4_stg_flush & --(7) + my_ex4_flush_l2 & --(8) + ex5_stg_flush & --(9) + ex2_lm_dep_hit_buf & --(10) + ex3_thrd_id(0 to 3) & --(11:14) + dbg_l2(15 to 20) & --(15:20) + dbg_l2(21 to 26) & --(21:26) + ex4_lmq_cpy_l2(0 to lmq_entries-1) & --(27:34) + lmq_collision_t0_l2(0 to lmq_entries-1) & --(35:42) + lmq_collision_t1_l2(0 to lmq_entries-1) & --(43:50) + lmq_collision_t2_l2(0 to lmq_entries-1) & --(51:58) + lmq_collision_t3_l2(0 to lmq_entries-1) & --(59:66) + ldq_barr_active_l2(0 to 3) & --(67:70) + ldq_barr_done_l2(0 to 3) & --(71:74) + sync_done_tid_l2(0 to 3) & --(75:78) + ld_rel_val_l2 & --(79:86) + st_entry0_val_l2; --(87) + + +-- scan in and scan out connections + +siv(0 to l_m_queue_addrlo_offset-1) <= sov(1 to l_m_queue_addrlo_offset-1) & scan_in(0); +scan_out(0) <= sov(0) and scan_dis_dc_b; + + +siv(l_m_queue_addrlo_offset to l2req_ld_core_tag_offset-1) <= sov(l_m_queue_addrlo_offset+1 to l2req_ld_core_tag_offset-1) & scan_in(1); +scan_out(1) <= sov(l_m_queue_addrlo_offset) and scan_dis_dc_b; + + +siv(l2req_ld_core_tag_offset to siv'right) <= sov(l2req_ld_core_tag_offset+1 to siv'right) & scan_in(2); +scan_out(2) <= sov(l2req_ld_core_tag_offset) and scan_dis_dc_b; + +bcfg_siv(0 to bcfg_siv'right) <= bcfg_sov(1 to bcfg_siv'right) & bcfg_scan_in; +bcfg_scan_out <= bcfg_sov(0) and scan_dis_dc_b; + +end xuq_lsu_l2cmdq; diff --git a/rel/src/vhdl/work/xuq_lsu_mux41.vhdl b/rel/src/vhdl/work/xuq_lsu_mux41.vhdl new file mode 100644 index 0000000..f539f66 --- /dev/null +++ b/rel/src/vhdl/work/xuq_lsu_mux41.vhdl @@ -0,0 +1,70 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- *!**************************************************************** +-- *! FILENAME : xuq_lsu_mux41.vhdl +-- *! DESCRIPTION : Tri-State 4-to-1 Mux +-- *! +-- *!**************************************************************** + +library ieee; use ieee.std_logic_1164.all; +library support; + use support.power_logic_pkg.all; + +entity xuq_lsu_mux41 is + port ( + vdd :inout power_logic; + gnd :inout power_logic; + D0 :in std_ulogic; + D1 :in std_ulogic; + D2 :in std_ulogic; + D3 :in std_ulogic; + S0 :in std_ulogic; + S1 :in std_ulogic; + S2 :in std_ulogic; + S3 :in std_ulogic; + Y :out std_ulogic + ); + + + +end entity xuq_lsu_mux41; + +architecture xuq_lsu_mux41 of xuq_lsu_mux41 is + +signal y0_b :std_ulogic; +signal y1_b :std_ulogic; + + +begin + +u_y0: y0_b <= not( (D0 and S0) or (D1 and S1) ); +u_y1: y1_b <= not( (D2 and S2) or (D3 and S3) ); +u_y: Y <= not(y0_b and y1_b); + +end xuq_lsu_mux41; diff --git a/rel/src/vhdl/work/xuq_lsu_perf.vhdl b/rel/src/vhdl/work/xuq_lsu_perf.vhdl new file mode 100644 index 0000000..0d05392 --- /dev/null +++ b/rel/src/vhdl/work/xuq_lsu_perf.vhdl @@ -0,0 +1,343 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: LSU Performance Event Muxing +-- +library ieee,ibm,support,work,tri,clib; +use ieee.std_logic_1164.all; +use support.power_logic_pkg.all; +use tri.tri_latches_pkg.all; + +entity xuq_lsu_perf is +generic( expand_type :integer := 2); +port( + + -- LSU Performance Events + lsu_perf_events :in std_ulogic_vector(0 to 46); + + -- PC Control Interface + pc_xu_event_bus_enable :in std_ulogic; + pc_xu_event_count_mode :in std_ulogic_vector(0 to 2); + pc_xu_lsu_event_mux_ctrls :in std_ulogic_vector(0 to 47); + pc_xu_cache_par_err_event :in std_ulogic; + + -- SPR Bits + spr_msr_gs :in std_ulogic_vector(0 to 3); + spr_msr_pr :in std_ulogic_vector(0 to 3); + + -- Perf Event Output + xu_pc_lsu_event_data :out std_ulogic_vector(0 to 7); + + -- Power + vdd :inout power_logic; + gnd :inout power_logic; + nclk :in clk_logic; + sg_0 :in std_ulogic; + func_slp_sl_thold_0_b :in std_ulogic; + func_slp_sl_force :in std_ulogic; + d_mode_dc :in std_ulogic; + delay_lclkr_dc :in std_ulogic; + mpw1_dc_b :in std_ulogic; + mpw2_dc_b :in std_ulogic; + scan_in :in std_ulogic; + scan_out :out std_ulogic +); + +-- synopsys translate_off + +-- synopsys translate_on +end xuq_lsu_perf; +architecture xuq_lsu_perf of xuq_lsu_perf is + +---------------------------- +-- signals +---------------------------- + +signal t0_events : std_ulogic_vector(0 to 31); +signal t1_events : std_ulogic_vector(0 to 31); +signal t2_events : std_ulogic_vector(0 to 31); +signal t3_events : std_ulogic_vector(0 to 31); +signal t0_lsu_events : std_ulogic_vector(0 to 31); +signal t1_lsu_events : std_ulogic_vector(0 to 31); +signal t2_lsu_events : std_ulogic_vector(0 to 31); +signal t3_lsu_events : std_ulogic_vector(0 to 31); +signal t0_lsu_events_tmp : std_ulogic_vector(0 to 23); +signal t1_lsu_events_tmp : std_ulogic_vector(0 to 23); +signal t2_lsu_events_tmp : std_ulogic_vector(0 to 23); +signal t3_lsu_events_tmp : std_ulogic_vector(0 to 23); +signal event_en_q, event_en_d : std_ulogic_vector(0 to 3); +signal event_data_q, event_data_d : std_ulogic_vector(xu_pc_lsu_event_data'range); +signal event_mux_ctrls_q, event_mux_ctrls_d : std_ulogic_vector(0 to 47); +signal lsu_perf_events_q : std_ulogic_vector(0 to 46); +signal pc_event_count_mode_q : std_ulogic_vector(0 to 2); +signal pc_cache_par_err_event_q : std_ulogic; +signal pc_event_bus_enable_q : std_ulogic; + +---------------------------- +-- constants +---------------------------- +constant event_en_offset : integer := 0; +constant event_data_offset : integer := event_en_offset + event_en_q'length; +constant event_mux_ctrls_offset : integer := event_data_offset + event_data_q'length; +constant lsu_perf_events_offset : integer := event_mux_ctrls_offset + event_mux_ctrls_q'length; +constant pc_event_count_mode_offset : integer := lsu_perf_events_offset + lsu_perf_events_q'length; +constant pc_cache_par_err_event_offset : integer := pc_event_count_mode_offset + pc_event_count_mode_q'length; +constant pc_event_bus_enable_offset : integer := pc_cache_par_err_event_offset + 1; +constant scan_right : integer := pc_event_bus_enable_offset + 1; + +signal siv : std_ulogic_vector(0 to scan_right-1); +signal sov : std_ulogic_vector(0 to scan_right-1); +signal tiup : std_ulogic; + +begin + +tiup <= '1'; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- State the Processor is in +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +event_en_d <= ( spr_msr_pr and (0 to 3=>pc_event_count_mode_q(0))) or -- User + (not spr_msr_pr and spr_msr_gs and (0 to 3=>pc_event_count_mode_q(1))) or -- Guest Supervisor + (not spr_msr_pr and not spr_msr_gs and (0 to 3=>pc_event_count_mode_q(2))); -- Hypervisor + +event_mux_ctrls_d <= pc_xu_lsu_event_mux_ctrls; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Event Listing +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +-- (0) => perf_com_stores => perf_event(4) +-- (1) => perf_com_store_miss => perf_event(5) +-- (2) => perf_com_loadmiss => perf_event(6) +-- (3) => perf_com_cinh_loads => perf_event(7) +-- (4) => perf_com_loads => perf_event(8) +-- (5) => perf_com_dcbt_sent => perf_event(9) +-- (6) => perf_com_dcbt_hit => perf_event(10) +-- (7) => perf_com_axu_load => perf_event(11) +-- (8) => perf_com_axu_store => perf_event(12) +-- (9) => perf_com_stcx_exec => perf_event(13) +-- (10) => perf_com_watch_clr => perf_event(14) +-- (11) => perf_com_wclr_lfld => perf_event(15) +-- (12) => perf_com_watch_set => perf_event(16) +-- (13) => perf_misalign_flush => perf_event(17) +-- (14) => perf_reload_collision_flush => perf_event(18) +-- (15) => perf_com_watch_duplicate => perf_event(37) +-- (16) => perf_inter_thrd_dir_update_flush => perf_event(19) +-- (17) => perf_dependency_flush => perf_event(20) +-- (18) => perf_com_watch_chk => perf_event(35) +-- (19) => perf_com_watch_chk_successful => perf_event(36) +-- (20) => perf_ld_queue_full_flush => perf_event(38) +-- (21) => perf_st_queue_full_flush => perf_event(39) +-- (22) => perf_ldst_hit_ld_flush => perf_event(40) +-- (23) => perf_ig_equal_one_flush => perf_event(41) +-- (24) => perf_com_larx_finished => perf_event(42:45) +-- (25) => perf_lost_watch_inter_thrd_store => perf_event(21:24) +-- (26) => perf_lost_watch_evicted => perf_event(25:28) +-- (27) => perf_lost_watch_back_invalidate => perf_event(29:32) +-- (28) => perf_back_invalidate => perf_event(33) +-- (29) => perf_back_invalidate_hit => perf_event(34) +-- (30) => perf_cache_par_err +-- (31) => perf_load_latency_memory_subsystem => perf_event(46) + +-- (0 to 16) (17 to 23) +t0_lsu_events_tmp <= (lsu_perf_events_q(4 to 20) & lsu_perf_events_q(35 to 41)) and (0 to 23=>lsu_perf_events_q(0)); +t1_lsu_events_tmp <= (lsu_perf_events_q(4 to 20) & lsu_perf_events_q(35 to 41)) and (0 to 23=>lsu_perf_events_q(1)); +t2_lsu_events_tmp <= (lsu_perf_events_q(4 to 20) & lsu_perf_events_q(35 to 41)) and (0 to 23=>lsu_perf_events_q(2)); +t3_lsu_events_tmp <= (lsu_perf_events_q(4 to 20) & lsu_perf_events_q(35 to 41)) and (0 to 23=>lsu_perf_events_q(3)); + +-- (0 to 23) (24) (25) (26) (27) (28 to 29) (30) (31) +t0_lsu_events <= t0_lsu_events_tmp & lsu_perf_events_q(42) & lsu_perf_events_q(21) & lsu_perf_events_q(25) & lsu_perf_events_q(29) & + lsu_perf_events_q(33 to 34) & pc_cache_par_err_event_q & lsu_perf_events_q(46); +t1_lsu_events <= t1_lsu_events_tmp & lsu_perf_events_q(43) & lsu_perf_events_q(22) & lsu_perf_events_q(26) & lsu_perf_events_q(30) & + lsu_perf_events_q(33 to 34) & pc_cache_par_err_event_q & lsu_perf_events_q(46); +t2_lsu_events <= t2_lsu_events_tmp & lsu_perf_events_q(44) & lsu_perf_events_q(23) & lsu_perf_events_q(27) & lsu_perf_events_q(31) & + lsu_perf_events_q(33 to 34) & pc_cache_par_err_event_q & lsu_perf_events_q(46); +t3_lsu_events <= t3_lsu_events_tmp & lsu_perf_events_q(45) & lsu_perf_events_q(24) & lsu_perf_events_q(28) & lsu_perf_events_q(32) & + lsu_perf_events_q(33 to 34) & pc_cache_par_err_event_q & lsu_perf_events_q(46); + +t0_events(0 to 31) <= t0_lsu_events and (0 to 31=>event_en_q(0)); +t1_events(0 to 31) <= t1_lsu_events and (0 to 31=>event_en_q(1)); +t2_events(0 to 31) <= t2_lsu_events and (0 to 31=>event_en_q(2)); +t3_events(0 to 31) <= t3_lsu_events and (0 to 31=>event_en_q(3)); + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Muxing +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +xuq_lsu_perf_mux1 : entity clib.c_event_mux(c_event_mux) +generic map(events_in => 128) +port map( + vd => vdd, + gd => gnd, + t0_events => t0_events, + t1_events => t1_events, + t2_events => t2_events, + t3_events => t3_events, + select_bits => event_mux_ctrls_q, + event_bits => event_data_d +); + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Outputs +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +xu_pc_lsu_event_data <= event_data_q; + +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +-- Registers +-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +event_en_latch : tri_rlmreg_p +generic map (width => event_en_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => pc_event_bus_enable_q, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(event_en_offset to event_en_offset + event_en_q'length-1), + scout => sov(event_en_offset to event_en_offset + event_en_q'length-1), + din => event_en_d, + dout => event_en_q); + +event_data_latch : tri_rlmreg_p +generic map (width => event_data_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => pc_event_bus_enable_q, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(event_data_offset to event_data_offset + event_data_q'length-1), + scout => sov(event_data_offset to event_data_offset + event_data_q'length-1), + din => event_data_d, + dout => event_data_q); + +event_mux_ctrls_latch : tri_rlmreg_p +generic map (width => event_mux_ctrls_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => pc_event_bus_enable_q, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(event_mux_ctrls_offset to event_mux_ctrls_offset + event_mux_ctrls_q'length-1), + scout => sov(event_mux_ctrls_offset to event_mux_ctrls_offset + event_mux_ctrls_q'length-1), + din => event_mux_ctrls_d, + dout => event_mux_ctrls_q); + +lsu_perf_events_latch : tri_rlmreg_p +generic map (width => lsu_perf_events_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => pc_event_bus_enable_q, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(lsu_perf_events_offset to lsu_perf_events_offset + lsu_perf_events_q'length-1), + scout => sov(lsu_perf_events_offset to lsu_perf_events_offset + lsu_perf_events_q'length-1), + din => lsu_perf_events, + dout => lsu_perf_events_q); + +pc_event_count_mode_latch : tri_rlmreg_p +generic map (width => pc_event_count_mode_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => pc_event_bus_enable_q, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(pc_event_count_mode_offset to pc_event_count_mode_offset + pc_event_count_mode_q'length-1), + scout => sov(pc_event_count_mode_offset to pc_event_count_mode_offset + pc_event_count_mode_q'length-1), + din => pc_xu_event_count_mode, + dout => pc_event_count_mode_q); + +pc_cache_par_err_event_latch : tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => pc_event_bus_enable_q, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(pc_cache_par_err_event_offset), + scout => sov(pc_cache_par_err_event_offset), + din => pc_xu_cache_par_err_event, + dout => pc_cache_par_err_event_q); + +pc_event_bus_enable_latch : tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (nclk => nclk, + vd => vdd, + gd => gnd, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(pc_event_bus_enable_offset), + scout => sov(pc_event_bus_enable_offset), + din => pc_xu_event_bus_enable, + dout => pc_event_bus_enable_q); + +siv(0 to siv'right) <= sov(1 to siv'right) & scan_in; +scan_out <= sov(0); + +end architecture xuq_lsu_perf; diff --git a/rel/src/vhdl/work/xuq_perf.vhdl b/rel/src/vhdl/work/xuq_perf.vhdl new file mode 100644 index 0000000..d7df454 --- /dev/null +++ b/rel/src/vhdl/work/xuq_perf.vhdl @@ -0,0 +1,416 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XU Performance Event Muxing +-- +library ieee,ibm,support,work,tri,clib; +use ieee.std_logic_1164.all; +use support.power_logic_pkg.all; +use tri.tri_latches_pkg.all; + +entity xuq_perf is +generic( + expand_type : integer := 2); +port( + -- Clocks + nclk : in clk_logic; + + -- Pervasive + func_sl_thold_2 : in std_ulogic; + sg_2 : in std_ulogic; + clkoff_dc_b : in std_ulogic; + d_mode_dc : in std_ulogic; + delay_lclkr_dc : in std_ulogic; + mpw1_dc_b : in std_ulogic; + mpw2_dc_b : in std_ulogic; + pc_xu_ccflush_dc : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + + -- Event Inputs + cpl_perf_tx_events : in std_ulogic_vector(0 to 75); + spr_perf_tx_events : in std_ulogic_vector(0 to 31); + byp_perf_tx_events : in std_ulogic_vector(0 to 11); + fxa_perf_muldiv_in_use : in std_ulogic; + + -- PC Control Interface + pc_xu_event_bus_enable : in std_ulogic; + pc_xu_event_count_mode : in std_ulogic_vector(0 to 2); + pc_xu_event_mux_ctrls : in std_ulogic_vector(0 to 47); + + -- Perf Event Output + xu_pc_event_data : out std_ulogic_vector(0 to 7); + + -- SPR Bits + spr_msr_gs : in std_ulogic_vector(0 to 3); + spr_msr_pr : in std_ulogic_vector(0 to 3); + + -- Power + vdd : inout power_logic; + gnd : inout power_logic +); + +-- synopsys translate_off + +-- synopsys translate_on +end xuq_perf; +architecture xuq_perf of xuq_perf is + +-- Latches +signal event_en_q, event_en_d : std_ulogic_vector(0 to 3); +signal event_data_q, event_data_d : std_ulogic_vector(xu_pc_event_data'range); +signal event_mux_ctrls_q, event_mux_ctrls_d : std_ulogic_vector(0 to 47); +signal cpl_perf_tx_events_q : std_ulogic_vector(0 to 75); -- input=>cpl_perf_tx_events +signal spr_perf_tx_events_q : std_ulogic_vector(0 to 31); -- input=>spr_perf_tx_events +signal byp_perf_tx_events_q : std_ulogic_vector(0 to 11); -- input=>byp_perf_tx_events +signal muldiv_in_use_q : std_ulogic; -- input=>fxa_perf_muldiv_in_use +signal processor_busy_q, processor_busy_d : std_ulogic; +signal br_commit_q, br_commit_d : std_ulogic; -- act=>pc_event_bus_enable_q +signal br_mispred_q, br_mispred_d : std_ulogic; -- act=>pc_event_bus_enable_q +signal br_ta_mispred_q, br_ta_mispred_d : std_ulogic; -- act=>pc_event_bus_enable_q +signal pc_event_count_mode_q : std_ulogic_vector(0 to 2); -- input=>pc_xu_event_count_mode +signal pc_event_bus_enable_q : std_ulogic; +-- Scanchains +constant event_en_offset : integer := 0; +constant event_data_offset : integer := event_en_offset + event_en_q'length; +constant event_mux_ctrls_offset : integer := event_data_offset + event_data_q'length; +constant cpl_perf_tx_events_offset : integer := event_mux_ctrls_offset + event_mux_ctrls_q'length; +constant spr_perf_tx_events_offset : integer := cpl_perf_tx_events_offset + cpl_perf_tx_events_q'length; +constant byp_perf_tx_events_offset : integer := spr_perf_tx_events_offset + spr_perf_tx_events_q'length; +constant muldiv_in_use_offset : integer := byp_perf_tx_events_offset + byp_perf_tx_events_q'length; +constant processor_busy_offset : integer := muldiv_in_use_offset + 1; +constant br_commit_offset : integer := processor_busy_offset + 1; +constant br_mispred_offset : integer := br_commit_offset + 1; +constant br_ta_mispred_offset : integer := br_mispred_offset + 1; +constant pc_event_count_mode_offset : integer := br_ta_mispred_offset + 1; +constant pc_event_bus_enable_offset : integer := pc_event_count_mode_offset + pc_event_count_mode_q'length; +constant scan_right : integer := pc_event_bus_enable_offset + 1; +signal siv : std_ulogic_vector(0 to scan_right-1); +signal sov : std_ulogic_vector(0 to scan_right-1); + +-- Signals +signal tiup : std_ulogic; +signal func_sl_thold_1 : std_ulogic; +signal sg_1 : std_ulogic; +signal func_sl_thold_0 : std_ulogic; +signal sg_0 : std_ulogic; +signal func_sl_force : std_ulogic; +signal func_sl_thold_0_b : std_ulogic; +signal t0_events, t0_events_in : std_ulogic_vector(0 to 31); +signal t1_events, t1_events_in : std_ulogic_vector(0 to 31); +signal t2_events, t2_events_in : std_ulogic_vector(0 to 31); +signal t3_events, t3_events_in : std_ulogic_vector(0 to 31); + +begin + +tiup <= '1'; + +-- Processor Busy / Br Commit / Br Mispred / Br TA Mispred +------------------------------------------ SPR +-- Thread Running +-- TB Tick +-- SPR read +-- SPR write +-- Cycles Stalled on waitrsv +-- External Int Asserted +-- Critical Ext Int Asserted +-- Perf Mon Int Asserted +------------------------------------------ CPL +-- PPE Commit +-- Integer Commit +-- uCode Commit +-- Any Flush +-- Branch Commit +-- Branch Mispredict Commit +-- Branch Taken Commit +-- Branch TA Mispredict Commit +-- Mult/Div collision +-- External Interrupt Pending +-- Critical External Interrupt Pending +-- Performance Mon Interrupt Pending +-- Opcode Match +-- Concurrent Run Instructions +-- External, Critical, Perf Interrupts Taken (any thread) +-- External Interrupt Taken +-- Critical External Interrupt Taken +-- Performance Mon Interrupt Taken +-- Processor Doorbell or Critical Doorbell Taken +------------------------------------------ BYP +-- STCX Fail +-- icswx failed +-- icswx finished +------------------------------------------ DEC +-- Mult/Div Busy + +processor_busy_d <= spr_perf_tx_events_q(00) or spr_perf_tx_events_q(08) or spr_perf_tx_events_q(16) or spr_perf_tx_events_q(24); + +br_commit_d <= cpl_perf_tx_events_q(04) or cpl_perf_tx_events_q(04+19) or cpl_perf_tx_events_q(04+38) or cpl_perf_tx_events_q(04+57); +br_mispred_d <= cpl_perf_tx_events_q(05) or cpl_perf_tx_events_q(05+19) or cpl_perf_tx_events_q(05+38) or cpl_perf_tx_events_q(05+57); +br_ta_mispred_d <= cpl_perf_tx_events_q(07) or cpl_perf_tx_events_q(07+19) or cpl_perf_tx_events_q(07+38) or cpl_perf_tx_events_q(07+57); + +t0_events_in <= processor_busy_q & spr_perf_tx_events_q(00 to 07) & cpl_perf_tx_events_q(00 to 18) & byp_perf_tx_events_q(00 to 02) & muldiv_in_use_q; +t1_events_in <= br_commit_q & spr_perf_tx_events_q(08 to 15) & cpl_perf_tx_events_q(19 to 37) & byp_perf_tx_events_q(03 to 05) & muldiv_in_use_q; +t2_events_in <= br_mispred_q & spr_perf_tx_events_q(16 to 23) & cpl_perf_tx_events_q(38 to 56) & byp_perf_tx_events_q(06 to 08) & muldiv_in_use_q; +t3_events_in <= br_ta_mispred_q & spr_perf_tx_events_q(24 to 31) & cpl_perf_tx_events_q(57 to 75) & byp_perf_tx_events_q(09 to 11) & muldiv_in_use_q; + +t0_events <= t0_events_in and (0 to 31=>event_en_q(0)); +t1_events <= t1_events_in and (0 to 31=>event_en_q(1)); +t2_events <= t2_events_in and (0 to 31=>event_en_q(2)); +t3_events <= t3_events_in and (0 to 31=>event_en_q(3)); + +xu_pc_event_data <= event_data_q; + +event_mux_ctrls_d <= pc_xu_event_mux_ctrls; + +event_en_d <= ( spr_msr_pr and (0 to 3=>pc_event_count_mode_q(0))) or -- User + (not spr_msr_pr and spr_msr_gs and (0 to 3=>pc_event_count_mode_q(1))) or -- Guest Supervisor + (not spr_msr_pr and not spr_msr_gs and (0 to 3=>pc_event_count_mode_q(2))); -- Hypervisor + +xuq_perf_mux1 : entity clib.c_event_mux(c_event_mux) +generic map(events_in => 128) +port map( + vd => vdd, + gd => gnd, + t0_events => t0_events, + t1_events => t1_events, + t2_events => t2_events, + t3_events => t3_events, + select_bits => event_mux_ctrls_q, + event_bits => event_data_d +); + +-- Latch Instances +event_en_latch : tri_rlmreg_p + generic map (width => event_en_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => pc_event_bus_enable_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(event_en_offset to event_en_offset + event_en_q'length-1), + scout => sov(event_en_offset to event_en_offset + event_en_q'length-1), + din => event_en_d, + dout => event_en_q); +event_data_latch : tri_rlmreg_p + generic map (width => event_data_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => pc_event_bus_enable_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(event_data_offset to event_data_offset + event_data_q'length-1), + scout => sov(event_data_offset to event_data_offset + event_data_q'length-1), + din => event_data_d, + dout => event_data_q); +event_mux_ctrls_latch : tri_rlmreg_p + generic map (width => event_mux_ctrls_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => pc_event_bus_enable_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(event_mux_ctrls_offset to event_mux_ctrls_offset + event_mux_ctrls_q'length-1), + scout => sov(event_mux_ctrls_offset to event_mux_ctrls_offset + event_mux_ctrls_q'length-1), + din => event_mux_ctrls_d, + dout => event_mux_ctrls_q); +cpl_perf_tx_events_latch : tri_rlmreg_p + generic map (width => cpl_perf_tx_events_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => pc_event_bus_enable_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(cpl_perf_tx_events_offset to cpl_perf_tx_events_offset + cpl_perf_tx_events_q'length-1), + scout => sov(cpl_perf_tx_events_offset to cpl_perf_tx_events_offset + cpl_perf_tx_events_q'length-1), + din => cpl_perf_tx_events, + dout => cpl_perf_tx_events_q); +spr_perf_tx_events_latch : tri_rlmreg_p + generic map (width => spr_perf_tx_events_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => pc_event_bus_enable_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(spr_perf_tx_events_offset to spr_perf_tx_events_offset + spr_perf_tx_events_q'length-1), + scout => sov(spr_perf_tx_events_offset to spr_perf_tx_events_offset + spr_perf_tx_events_q'length-1), + din => spr_perf_tx_events, + dout => spr_perf_tx_events_q); +byp_perf_tx_events_latch : tri_rlmreg_p + generic map (width => byp_perf_tx_events_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => pc_event_bus_enable_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(byp_perf_tx_events_offset to byp_perf_tx_events_offset + byp_perf_tx_events_q'length-1), + scout => sov(byp_perf_tx_events_offset to byp_perf_tx_events_offset + byp_perf_tx_events_q'length-1), + din => byp_perf_tx_events, + dout => byp_perf_tx_events_q); +muldiv_in_use_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => pc_event_bus_enable_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(muldiv_in_use_offset), + scout => sov(muldiv_in_use_offset), + din => fxa_perf_muldiv_in_use, + dout => muldiv_in_use_q); +processor_busy_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => pc_event_bus_enable_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(processor_busy_offset), + scout => sov(processor_busy_offset), + din => processor_busy_d, + dout => processor_busy_q); +br_commit_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => pc_event_bus_enable_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(br_commit_offset), + scout => sov(br_commit_offset), + din => br_commit_d, + dout => br_commit_q); +br_mispred_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => pc_event_bus_enable_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(br_mispred_offset), + scout => sov(br_mispred_offset), + din => br_mispred_d, + dout => br_mispred_q); +br_ta_mispred_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => pc_event_bus_enable_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(br_ta_mispred_offset), + scout => sov(br_ta_mispred_offset), + din => br_ta_mispred_d, + dout => br_ta_mispred_q); +pc_event_count_mode_latch : tri_rlmreg_p + generic map (width => pc_event_count_mode_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => pc_event_bus_enable_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(pc_event_count_mode_offset to pc_event_count_mode_offset + pc_event_count_mode_q'length-1), + scout => sov(pc_event_count_mode_offset to pc_event_count_mode_offset + pc_event_count_mode_q'length-1), + din => pc_xu_event_count_mode, + dout => pc_event_count_mode_q); +pc_event_bus_enable_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(pc_event_bus_enable_offset), + scout => sov(pc_event_bus_enable_offset), + din => pc_xu_event_bus_enable, + dout => pc_event_bus_enable_q); + +------------------------------------------------- +-- Pervasive +------------------------------------------------- +perv_2to1_reg: tri_plat + generic map (width => 2, expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_xu_ccflush_dc, + din(0) => func_sl_thold_2, + din(1) => sg_2, + q(0) => func_sl_thold_1, + q(1) => sg_1); + +perv_1to0_reg: tri_plat + generic map (width => 2, expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_xu_ccflush_dc, + din(0) => func_sl_thold_1, + din(1) => sg_1, + q(0) => func_sl_thold_0, + q(1) => sg_0); + +perv_lcbor_func_sl: tri_lcbor + generic map (expand_type => expand_type) +port map (clkoff_b => clkoff_dc_b, + thold => func_sl_thold_0, + sg => sg_0, + act_dis => '0', + forcee => func_sl_force, + thold_b => func_sl_thold_0_b); + + +siv(0 to siv'right) <= sov(1 to siv'right) & scan_in; +scan_out <= sov(0); + +end architecture xuq_perf; diff --git a/rel/src/vhdl/work/xuq_perv.vhdl b/rel/src/vhdl/work/xuq_perv.vhdl new file mode 100644 index 0000000..3288922 --- /dev/null +++ b/rel/src/vhdl/work/xuq_perv.vhdl @@ -0,0 +1,397 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XU Pervasive +-- +library ieee,ibm,support,tri,work; +use ieee.std_logic_1164.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; +use support.power_logic_pkg.all; +use tri.tri_latches_pkg.all; +use work.xuq_pkg.all; + +entity xuq_perv is +generic(expand_type : integer := 2 ); -- 0 = ibm umbra, 1 = xilinx, 2 = ibm mpg +port( + vdd : inout power_logic; + gnd : inout power_logic; + nclk : in clk_logic; + an_ac_scan_dis_dc_b : in std_ulogic; + pc_xu_sg_3 : in std_ulogic_vector(0 to 4); + pc_xu_func_sl_thold_3 : in std_ulogic_vector(0 to 4); + pc_xu_func_slp_sl_thold_3 : in std_ulogic_vector(0 to 4); + pc_xu_func_nsl_thold_3 : in std_ulogic; + pc_xu_func_slp_nsl_thold_3 : in std_ulogic; + pc_xu_gptr_sl_thold_3 : in std_ulogic; + pc_xu_abst_sl_thold_3 : in std_ulogic; + pc_xu_abst_slp_sl_thold_3 : in std_ulogic; + pc_xu_regf_sl_thold_3 : in std_ulogic; + pc_xu_regf_slp_sl_thold_3 : in std_ulogic; + pc_xu_time_sl_thold_3 : in std_ulogic; + pc_xu_cfg_sl_thold_3 : in std_ulogic; + pc_xu_cfg_slp_sl_thold_3 : in std_ulogic; + pc_xu_ary_nsl_thold_3 : in std_ulogic; + pc_xu_ary_slp_nsl_thold_3 : in std_ulogic; + pc_xu_repr_sl_thold_3 : in std_ulogic; + pc_xu_bolt_sl_thold_3 : in std_ulogic; + pc_xu_bo_enable_3 : in std_ulogic; + pc_xu_fce_3 : in std_ulogic_vector(0 to 1); + pc_xu_ccflush_dc : in std_ulogic; + an_ac_scan_diag_dc : in std_ulogic; + sg_2 : out std_ulogic_vector(0 to 3); + fce_2 : out std_ulogic_vector(0 to 1); + func_sl_thold_2 : out std_ulogic_vector(0 to 3); + func_slp_sl_thold_2 : out std_ulogic_vector(0 to 1); + func_nsl_thold_2 : out std_ulogic; + func_slp_nsl_thold_2 : out std_ulogic; + abst_sl_thold_2 : out std_ulogic; + abst_slp_sl_thold_2 : out std_ulogic; + regf_sl_thold_2 : out std_ulogic; + regf_slp_sl_thold_2 : out std_ulogic; + time_sl_thold_2 : out std_ulogic; + gptr_sl_thold_2 : out std_ulogic; + ary_nsl_thold_2 : out std_ulogic; + ary_slp_nsl_thold_2 : out std_ulogic; + repr_sl_thold_2 : out std_ulogic; + cfg_sl_thold_2 : out std_ulogic; + cfg_slp_sl_thold_2 : out std_ulogic; + bolt_sl_thold_2 : out std_ulogic; + bo_enable_2 : out std_ulogic; + sg_0 : out std_ulogic; + sg_1 : out std_ulogic; + ary_nsl_thold_0 : out std_ulogic; + abst_sl_thold_0 : out std_ulogic; + time_sl_thold_0 : out std_ulogic; + repr_sl_thold_0 : out std_ulogic; + clkoff_dc_b : out std_ulogic; + d_mode_dc : out std_ulogic; + delay_lclkr_dc : out std_ulogic_vector(0 to 4); + mpw1_dc_b : out std_ulogic_vector(0 to 4); + mpw2_dc_b : out std_ulogic; + g6t_clkoff_dc_b : out std_ulogic; + g6t_d_mode_dc : out std_ulogic; + g6t_delay_lclkr_dc : out std_ulogic_vector(0 to 4); + g6t_mpw1_dc_b : out std_ulogic_vector(0 to 4); + g6t_mpw2_dc_b : out std_ulogic; + g8t_clkoff_dc_b : out std_ulogic; + g8t_d_mode_dc : out std_ulogic; + g8t_delay_lclkr_dc : out std_ulogic_vector(0 to 4); + g8t_mpw1_dc_b : out std_ulogic_vector(0 to 4); + g8t_mpw2_dc_b : out std_ulogic; + cam_clkoff_dc_b : out std_ulogic; + cam_d_mode_dc : out std_ulogic; + cam_delay_lclkr_dc : out std_ulogic_vector(0 to 4); + cam_act_dis_dc : out std_ulogic; + cam_mpw1_dc_b : out std_ulogic_vector(0 to 4); + cam_mpw2_dc_b : out std_ulogic; + gptr_scan_in : in std_ulogic; + gptr_scan_out : out std_ulogic +); + +-- synopsys translate_off +-- synopsys translate_on + +end xuq_perv; +architecture xuq_perv of xuq_perv is + +signal gptr_sov, gptr_siv : std_ulogic_vector(0 to 3); +signal perv_sg_2 : std_ulogic_vector(0 to 3); +signal perv_sg_2_b : std_ulogic_vector(0 to 3); +signal gptr_sl_thold_2_int : std_ulogic; +signal gptr_sl_thold_2_int_b : std_ulogic; +signal gptr_sl_thold_1, sg_1_int : std_ulogic; +signal gptr_sl_thold_0, sg_0_int : std_ulogic; +signal time_sl_thold_0_int : std_ulogic; +signal ary_nsl_thold_2_int : std_ulogic; +signal ary_nsl_thold_2_int_b : std_ulogic; +signal ary_slp_nsl_thold_2_int : std_ulogic; +signal abst_sl_thold_2_int : std_ulogic; +signal abst_sl_thold_2_int_b : std_ulogic; +signal abst_slp_sl_thold_2_int : std_ulogic; +signal regf_sl_thold_2_int : std_ulogic; +signal regf_slp_sl_thold_2_int : std_ulogic; +signal func_slp_nsl_thold_2_int : std_ulogic; +signal time_sl_thold_2_int : std_ulogic; +signal time_sl_thold_2_int_b : std_ulogic; +signal repr_sl_thold_2_int : std_ulogic; +signal repr_sl_thold_2_int_b : std_ulogic; +signal ary_nsl_thold_1 : std_ulogic; +signal abst_sl_thold_1 : std_ulogic; +signal time_sl_thold_1 : std_ulogic; +signal repr_sl_thold_1 : std_ulogic; +signal func_sl_thold_2_int : std_ulogic_vector(0 to 3); +signal bolt_sl_thold_2_int : std_ulogic; +signal bo_enable_2_int : std_ulogic; +signal fce_2_int : std_ulogic_vector(0 to 1); +signal func_slp_sl_thold_2_int : std_ulogic_vector(0 to 1); +signal cfg_sl_thold_2_int : std_ulogic; +signal cfg_slp_sl_thold_2_int : std_ulogic; +signal func_nsl_thold_2_int : std_ulogic; +signal clkoff_dc_b_int : std_ulogic; +signal d_mode_dc_int : std_ulogic; +signal delay_lclkr_dc_int : std_ulogic_vector(0 to 4); +signal mpw1_dc_b_int : std_ulogic_vector(0 to 4); +signal mpw2_dc_b_int : std_ulogic; +signal g6t_clkoff_dc_b_int : std_ulogic; +signal g6t_d_mode_dc_int : std_ulogic; +signal g6t_delay_lclkr_dc_int : std_ulogic_vector(0 to 4); +signal g6t_mpw1_dc_b_int : std_ulogic_vector(0 to 4); +signal g6t_mpw2_dc_b_int : std_ulogic; +signal g8t_clkoff_dc_b_int : std_ulogic; +signal g8t_d_mode_dc_int : std_ulogic; +signal g8t_delay_lclkr_dc_int : std_ulogic_vector(0 to 4); +signal g8t_mpw1_dc_b_int : std_ulogic_vector(0 to 4); +signal g8t_mpw2_dc_b_int : std_ulogic; +signal cam_clkoff_dc_b_int : std_ulogic; +signal cam_d_mode_dc_int : std_ulogic; +signal cam_delay_lclkr_dc_int : std_ulogic_vector(0 to 4); +signal cam_mpw1_dc_b_int : std_ulogic_vector(0 to 4); +signal cam_mpw2_dc_b_int : std_ulogic; + +begin + +perv_3to2_reg: tri_plat + generic map (width => 27, expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_xu_ccflush_dc, + din(0 to 3) => pc_xu_func_sl_thold_3(0 to 3), + din(4 to 5) => pc_xu_func_slp_sl_thold_3(0 to 1), + din(6) => pc_xu_gptr_sl_thold_3, + din(7 to 10) => pc_xu_sg_3(0 to 3), + din(11 to 12) => pc_xu_fce_3(0 to 1), + din(13) => pc_xu_func_nsl_thold_3, + din(14) => pc_xu_abst_sl_thold_3, + din(15) => pc_xu_abst_slp_sl_thold_3, + din(16) => pc_xu_time_sl_thold_3, + din(17) => pc_xu_ary_nsl_thold_3, + din(18) => pc_xu_ary_slp_nsl_thold_3, + din(19) => pc_xu_cfg_sl_thold_3, + din(20) => pc_xu_cfg_slp_sl_thold_3, + din(21) => pc_xu_repr_sl_thold_3, + din(22) => pc_xu_regf_sl_thold_3, + din(23) => pc_xu_regf_slp_sl_thold_3, + din(24) => pc_xu_func_slp_nsl_thold_3, + din(25) => pc_xu_bolt_sl_thold_3, + din(26) => pc_xu_bo_enable_3, + q(0 to 3) => func_sl_thold_2_int(0 to 3), + q(4 to 5) => func_slp_sl_thold_2_int(0 to 1), + q(6) => gptr_sl_thold_2_int, + q(7 to 10) => perv_sg_2(0 to 3), + q(11 to 12) => fce_2_int(0 to 1), + q(13) => func_nsl_thold_2_int, + q(14) => abst_sl_thold_2_int, + q(15) => abst_slp_sl_thold_2_int, + q(16) => time_sl_thold_2_int, + q(17) => ary_nsl_thold_2_int, + q(18) => ary_slp_nsl_thold_2_int, + q(19) => cfg_sl_thold_2_int, + q(20) => cfg_slp_sl_thold_2_int, + q(21) => repr_sl_thold_2_int, + q(22) => regf_sl_thold_2_int, + q(23) => regf_slp_sl_thold_2_int, + q(24) => func_slp_nsl_thold_2_int, + q(25) => bolt_sl_thold_2_int, + q(26) => bo_enable_2_int); + +sg_2 <= perv_sg_2; +perv_sg_2_b <= perv_sg_2; +sg_1 <= sg_1_int; +sg_0 <= sg_0_int; + +ary_nsl_thold_2 <= ary_nsl_thold_2_int; +ary_nsl_thold_2_int_b<= ary_nsl_thold_2_int; +ary_slp_nsl_thold_2 <= ary_slp_nsl_thold_2_int; +abst_sl_thold_2 <= abst_sl_thold_2_int; +abst_sl_thold_2_int_b <= abst_sl_thold_2_int; +abst_slp_sl_thold_2 <= abst_slp_sl_thold_2_int; +regf_sl_thold_2 <= regf_sl_thold_2_int; +regf_slp_sl_thold_2 <= regf_slp_sl_thold_2_int; +time_sl_thold_2 <= time_sl_thold_2_int; +time_sl_thold_2_int_b <= time_sl_thold_2_int; +repr_sl_thold_2 <= repr_sl_thold_2_int; +repr_sl_thold_2_int_b <= repr_sl_thold_2_int; +func_sl_thold_2 <= func_sl_thold_2_int; +bolt_sl_thold_2 <= bolt_sl_thold_2_int; +bo_enable_2 <= bo_enable_2_int; +fce_2 <= fce_2_int; +func_slp_sl_thold_2 <= func_slp_sl_thold_2_int; +cfg_sl_thold_2 <= cfg_sl_thold_2_int; +cfg_slp_sl_thold_2 <= cfg_slp_sl_thold_2_int; +func_nsl_thold_2 <= func_nsl_thold_2_int; +func_slp_nsl_thold_2 <= func_slp_nsl_thold_2_int; +clkoff_dc_b <= clkoff_dc_b_int; +d_mode_dc <= d_mode_dc_int; +delay_lclkr_dc <= delay_lclkr_dc_int; +mpw1_dc_b <= mpw1_dc_b_int; +mpw2_dc_b <= mpw2_dc_b_int; +time_sl_thold_0 <= time_sl_thold_0_int; + +g6t_clkoff_dc_b <= g6t_clkoff_dc_b_int; +g6t_d_mode_dc <= g6t_d_mode_dc_int; +g6t_delay_lclkr_dc <= g6t_delay_lclkr_dc_int; +g6t_mpw1_dc_b <= g6t_mpw1_dc_b_int; +g6t_mpw2_dc_b <= g6t_mpw2_dc_b_int; + +g8t_clkoff_dc_b <= g8t_clkoff_dc_b_int; +g8t_d_mode_dc <= g8t_d_mode_dc_int; +g8t_delay_lclkr_dc <= g8t_delay_lclkr_dc_int; +g8t_mpw1_dc_b <= g8t_mpw1_dc_b_int; +g8t_mpw2_dc_b <= g8t_mpw2_dc_b_int; + +cam_clkoff_dc_b <= cam_clkoff_dc_b_int; +cam_delay_lclkr_dc <= cam_delay_lclkr_dc_int; +cam_act_dis_dc <= '0'; +cam_d_mode_dc <= cam_d_mode_dc_int; +cam_mpw1_dc_b <= cam_mpw1_dc_b_int; +cam_mpw2_dc_b <= cam_mpw2_dc_b_int; + +gptr_sl_thold_2 <= gptr_sl_thold_2_int; +gptr_sl_thold_2_int_b <= gptr_sl_thold_2_int; + +perv_2to1_reg: tri_plat + generic map (width => 6, expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_xu_ccflush_dc, + din(0) => gptr_sl_thold_2_int_b, + din(1) => perv_sg_2_b(0), + din(2) => ary_nsl_thold_2_int_b, + din(3) => abst_sl_thold_2_int_b, + din(4) => time_sl_thold_2_int_b, + din(5) => repr_sl_thold_2_int_b, + q(0) => gptr_sl_thold_1, + q(1) => sg_1_int, + q(2) => ary_nsl_thold_1, + q(3) => abst_sl_thold_1, + q(4) => time_sl_thold_1, + q(5) => repr_sl_thold_1); + +perv_1to0_reg: tri_plat + generic map (width => 6, expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_xu_ccflush_dc, + din(0) => gptr_sl_thold_1, + din(1) => sg_1_int, + din(2) => ary_nsl_thold_1, + din(3) => abst_sl_thold_1, + din(4) => time_sl_thold_1, + din(5) => repr_sl_thold_1, + q(0) => gptr_sl_thold_0, + q(1) => sg_0_int, + q(2) => ary_nsl_thold_0, + q(3) => abst_sl_thold_0, + q(4) => time_sl_thold_0_int, + q(5) => repr_sl_thold_0); + +perv_lcbctrl_0: tri_lcbcntl_mac + generic map (expand_type => expand_type) +port map ( + vdd => vdd, + gnd => gnd, + sg => sg_0_int, + nclk => nclk, + scan_in => gptr_siv(3), + scan_diag_dc => an_ac_scan_diag_dc, + thold => gptr_sl_thold_0, + clkoff_dc_b => clkoff_dc_b_int, + delay_lclkr_dc => delay_lclkr_dc_int(0 to 4), + act_dis_dc => open, + d_mode_dc => d_mode_dc_int, + mpw1_dc_b => mpw1_dc_b_int(0 to 4), + mpw2_dc_b => mpw2_dc_b_int, + scan_out => gptr_sov(3)); + +perv_lcbctrl_g6t_0: tri_lcbcntl_array_mac + generic map (expand_type => expand_type) +port map ( + vdd => vdd, + gnd => gnd, + sg => sg_0_int, + nclk => nclk, + scan_in => gptr_siv(0), + scan_diag_dc => an_ac_scan_diag_dc, + thold => gptr_sl_thold_0, + clkoff_dc_b => g6t_clkoff_dc_b_int, + delay_lclkr_dc => g6t_delay_lclkr_dc_int(0 to 4), + act_dis_dc => open, + d_mode_dc => g6t_d_mode_dc_int, + mpw1_dc_b => g6t_mpw1_dc_b_int(0 to 4), + mpw2_dc_b => g6t_mpw2_dc_b_int, + scan_out => gptr_sov(0)); + +perv_lcbctrl_g8t_0: tri_lcbcntl_array_mac + generic map (expand_type => expand_type) +port map ( + vdd => vdd, + gnd => gnd, + sg => sg_0_int, + nclk => nclk, + scan_in => gptr_siv(1), + scan_diag_dc => an_ac_scan_diag_dc, + thold => gptr_sl_thold_0, + clkoff_dc_b => g8t_clkoff_dc_b_int, + delay_lclkr_dc => g8t_delay_lclkr_dc_int(0 to 4), + act_dis_dc => open, + d_mode_dc => g8t_d_mode_dc_int, + mpw1_dc_b => g8t_mpw1_dc_b_int(0 to 4), + mpw2_dc_b => g8t_mpw2_dc_b_int, + scan_out => gptr_sov(1)); + +perv_lcbctrl_cam_0: tri_lcbcntl_array_mac + generic map (expand_type => expand_type) +port map ( + vdd => vdd, + gnd => gnd, + sg => sg_0_int, + nclk => nclk, + scan_in => gptr_siv(2), + scan_diag_dc => an_ac_scan_diag_dc, + thold => gptr_sl_thold_0, + clkoff_dc_b => cam_clkoff_dc_b_int, + delay_lclkr_dc => cam_delay_lclkr_dc_int(0 to 4), + act_dis_dc => open, + d_mode_dc => cam_d_mode_dc_int, + mpw1_dc_b => cam_mpw1_dc_b_int(0 to 4), + mpw2_dc_b => cam_mpw2_dc_b_int, + scan_out => gptr_sov(2)); + +gptr_siv(0 to gptr_siv'right) <= gptr_sov(1 to gptr_siv'right) & gptr_scan_in; +gptr_scan_out <= gptr_sov(0) and an_ac_scan_dis_dc_b; + +mark_unused(pc_xu_func_sl_thold_3(4)); +mark_unused(pc_xu_func_slp_sl_thold_3(2 to 4)); +mark_unused(pc_xu_sg_3(4)); + +end xuq_perv; diff --git a/rel/src/vhdl/work/xuq_pkg.vhdl b/rel/src/vhdl/work/xuq_pkg.vhdl new file mode 100644 index 0000000..408fbc3 --- /dev/null +++ b/rel/src/vhdl/work/xuq_pkg.vhdl @@ -0,0 +1,145 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XU Package +-- +library ieee; +use ieee.std_logic_1164.all; + +package xuq_pkg is + subtype s1 is std_ulogic; + subtype s2 is std_ulogic_vector(0 to 1); + subtype s3 is std_ulogic_vector(0 to 2); + subtype s4 is std_ulogic_vector(0 to 3); + subtype s5 is std_ulogic_vector(0 to 4); + subtype s6 is std_ulogic_vector(0 to 5); + subtype s7 is std_ulogic_vector(0 to 6); + + function fanout(in0 : std_ulogic; size : natural) return std_ulogic_vector; + function fanout(in0 : std_ulogic_vector; size : natural) return std_ulogic_vector; + function encode( input : std_ulogic_vector) return std_ulogic_vector; + function or_reduce_t(in0 : std_ulogic_vector; threads : integer) return std_ulogic_vector; + function mux_t(in0 : std_ulogic_vector; gate : std_ulogic_vector) return std_ulogic_vector; + procedure mark_unused(input : std_ulogic); + procedure mark_unused(input : std_ulogic_vector); + + +end xuq_pkg; + +package body xuq_pkg is + + procedure mark_unused(input : std_ulogic) is + variable unused : std_ulogic; + -- synopsys translate_off + -- synopsys translate_on + begin + unused := input; + end mark_unused; + + procedure mark_unused(input : std_ulogic_vector) is + variable unused : std_ulogic_vector(input'range); + -- synopsys translate_off + -- synopsys translate_on + begin + unused := input; + end mark_unused; + + + function fanout(in0 : std_ulogic_vector; size : natural) return std_ulogic_vector is + variable result : std_ulogic_vector(0 to size-1); + variable fan : natural; + begin + fan := in0'length; + for i in 0 to size-1 loop + result(i) := in0(i mod fan); + end loop; + return result; + end fanout; + + function fanout(in0 : std_ulogic; size : natural) return std_ulogic_vector is + variable result : std_ulogic_vector(0 to size-1); + begin + result := (others=>in0); + return result; + end fanout; + + + function mux_t(in0 : std_ulogic_vector; gate : std_ulogic_vector) return std_ulogic_vector is + variable in1 : std_ulogic_vector(0 to in0'length-1); + variable result : std_ulogic_vector(0 to in0'length/gate'length-1); + begin + + in1 := in0; + result := (others=>'0'); + for i in 0 to result'length-1 loop + for t in 0 to gate'length-1 loop + result(i) := result(i) or (in1(i+t*result'length) and gate(t)); + end loop; + end loop; + return result; + end mux_t; + + function or_reduce_t(in0 : std_ulogic_vector; threads : integer) return std_ulogic_vector is + variable in1 : std_ulogic_vector(0 to in0'length-1); + variable result : std_ulogic_vector(0 to in0'length/threads-1); + begin + in1 := in0; + result := (others=>'0'); + for i in 0 to result'length-1 loop + for t in 0 to threads-1 loop + result(i) := result(i) or in1(i+t*result'length); + end loop; + end loop; + return result; + end or_reduce_t; + + + function encode( input : std_ulogic_vector) return std_ulogic_vector is + variable result : std_ulogic_vector(3 downto 0); + begin + if (input'length = 1) then + return("0"); + elsif (input'length = 2) then + return(input(input'right to input'right)); + elsif (input'length = 4) then + case s4'(input) is + when "0001" => result := "0011"; + when "0010" => result := "0010"; + when "0100" => result := "0001"; + when others => result := "0000"; + end case; + return(result(1 downto 0)); + else + assert (TRUE) + report "Length field is too large" + severity error; + return("X"); + end if; + end; + +end xuq_pkg; diff --git a/rel/src/vhdl/work/xuq_spr.vhdl b/rel/src/vhdl/work/xuq_spr.vhdl new file mode 100644 index 0000000..bbe37da --- /dev/null +++ b/rel/src/vhdl/work/xuq_spr.vhdl @@ -0,0 +1,1695 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XU SPR - Wrapper +-- +library ieee,ibm,support,work,tri,clib; +use ieee.std_logic_1164.all; +use support.power_logic_pkg.all; +use ibm.std_ulogic_function_support.all; +use tri.tri_latches_pkg.all; + +entity xuq_spr is +generic( + hvmode : integer := 1; + a2mode : integer := 1; + expand_type : integer := 2; + threads : integer := 4; + regsize : integer := 64; + eff_ifar : integer := 62; + spr_xucr0_init_mod : integer := 0); +port( + nclk : in clk_logic; + + -- CHIP IO + an_ac_coreid : in std_ulogic_vector(54 to 61); + spr_pvr_version_dc : in std_ulogic_vector(8 to 15); + spr_pvr_revision_dc : in std_ulogic_vector(12 to 15); + an_ac_ext_interrupt : in std_ulogic_vector(0 to threads-1); + an_ac_crit_interrupt : in std_ulogic_vector(0 to threads-1); + an_ac_perf_interrupt : in std_ulogic_vector(0 to threads-1); + an_ac_reservation_vld : in std_ulogic_vector(0 to threads-1); + an_ac_tb_update_pulse : in std_ulogic; + an_ac_tb_update_enable : in std_ulogic; + an_ac_sleep_en : in std_ulogic_vector(0 to threads-1); + an_ac_hang_pulse : in std_ulogic_vector(0 to threads-1); + ac_tc_machine_check : out std_ulogic_vector(0 to threads-1); + an_ac_external_mchk : in std_ulogic_vector(0 to threads-1); + pc_xu_instr_trace_mode : in std_ulogic; + pc_xu_instr_trace_tid : in std_ulogic_vector(0 to 1); + + an_ac_scan_dis_dc_b : in std_ulogic; + an_ac_scan_diag_dc : in std_ulogic; + pc_xu_ccflush_dc : in std_ulogic; + clkoff_dc_b : in std_ulogic; + d_mode_dc : in std_ulogic; + delay_lclkr_dc : in std_ulogic; + mpw1_dc_b : in std_ulogic; + mpw2_dc_b : in std_ulogic; + func_sl_thold_2 : in std_ulogic; + func_slp_sl_thold_2 : in std_ulogic; + func_nsl_thold_2 : in std_ulogic; + func_slp_nsl_thold_2 : in std_ulogic; + cfg_sl_thold_2 : in std_ulogic; + cfg_slp_sl_thold_2 : in std_ulogic; + ary_nsl_thold_2 : in std_ulogic; + time_sl_thold_2 : in std_ulogic; + abst_sl_thold_2 : in std_ulogic; + repr_sl_thold_2 : in std_ulogic; + gptr_sl_thold_2 : in std_ulogic; + bolt_sl_thold_2 : in std_ulogic; + sg_2 : in std_ulogic; + fce_2 : in std_ulogic; + func_scan_in : in std_ulogic_vector(0 to threads+1); + func_scan_out : out std_ulogic_vector(0 to threads+1); + bcfg_scan_in : in std_ulogic; + bcfg_scan_out : out std_ulogic; + ccfg_scan_in : in std_ulogic; + ccfg_scan_out : out std_ulogic; + dcfg_scan_in : in std_ulogic; + dcfg_scan_out : out std_ulogic; + time_scan_in : in std_ulogic; + time_scan_out : out std_ulogic; + abst_scan_in : in std_ulogic; + abst_scan_out : out std_ulogic; + repr_scan_in : in std_ulogic; + repr_scan_out : out std_ulogic; + gptr_scan_in : in std_ulogic; + gptr_scan_out : out std_ulogic; + + -- Decode + dec_spr_rf0_tid : in std_ulogic_vector(0 to threads-1); + dec_spr_rf0_instr : in std_ulogic_vector(0 to 31); + dec_spr_rf1_val : in std_ulogic_vector(0 to threads-1); + dec_spr_ex1_epid_instr : in std_ulogic; + dec_spr_ex4_val : in std_ulogic_vector(0 to threads-1); + + -- Read Data + spr_byp_ex3_spr_rt : out std_ulogic_vector(64-regsize to 63); + + fxu_spr_ex1_rs2 : in std_ulogic_vector(42 to 55); + + -- Write Data + fxu_spr_ex1_rs0 : in std_ulogic_vector(52 to 63); + fxu_spr_ex1_rs1 : in std_ulogic_vector(54 to 63); + mux_spr_ex2_rt : in std_ulogic_vector(64-regsize to 63); + + -- Interrupt Interface + cpl_spr_ex5_act : in std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_int : in std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_gint : in std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_cint : in std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_mcint : in std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_nia : in std_ulogic_vector(0 to eff_ifar*threads-1); + cpl_spr_ex5_esr : in std_ulogic_vector(0 to 17*threads-1); + cpl_spr_ex5_mcsr : in std_ulogic_vector(0 to 15*threads-1); + cpl_spr_ex5_dbsr : in std_ulogic_vector(0 to 19*threads-1); + cpl_spr_ex5_dear_update : in std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_dear_update_saved : in std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_dear_save : in std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_dbsr_update : in std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_esr_update : in std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_srr0_dec : in std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_force_gsrr : in std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_dbsr_ide : in std_ulogic_vector(0 to threads-1); + spr_cpl_dbsr_ide : out std_ulogic_vector(0 to threads-1); + + -- Async Interrupt Req Interface + spr_cpl_external_mchk : out std_ulogic_vector(0 to threads-1); + spr_cpl_ext_interrupt : out std_ulogic_vector(0 to threads-1); + spr_cpl_dec_interrupt : out std_ulogic_vector(0 to threads-1); + spr_cpl_udec_interrupt : out std_ulogic_vector(0 to threads-1); + spr_cpl_perf_interrupt : out std_ulogic_vector(0 to threads-1); + spr_cpl_fit_interrupt : out std_ulogic_vector(0 to threads-1); + spr_cpl_crit_interrupt : out std_ulogic_vector(0 to threads-1); + spr_cpl_wdog_interrupt : out std_ulogic_vector(0 to threads-1); + spr_cpl_dbell_interrupt : out std_ulogic_vector(0 to threads-1); + spr_cpl_cdbell_interrupt : out std_ulogic_vector(0 to threads-1); + spr_cpl_gdbell_interrupt : out std_ulogic_vector(0 to threads-1); + spr_cpl_gcdbell_interrupt : out std_ulogic_vector(0 to threads-1); + spr_cpl_gmcdbell_interrupt : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_dbell_taken : in std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_cdbell_taken : in std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_gdbell_taken : in std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_gcdbell_taken : in std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_gmcdbell_taken : in std_ulogic_vector(0 to threads-1); + + -- DBELL Int + lsu_xu_dbell_val : in std_ulogic; + lsu_xu_dbell_type : in std_ulogic_vector(0 to 4); + lsu_xu_dbell_brdcast : in std_ulogic; + lsu_xu_dbell_lpid_match : in std_ulogic; + lsu_xu_dbell_pirtag : in std_ulogic_vector(50 to 63); + + -- Slow SPR Bus + xu_lsu_slowspr_val : out std_ulogic; + xu_lsu_slowspr_rw : out std_ulogic; + xu_lsu_slowspr_etid : out std_ulogic_vector(0 to 1); + xu_lsu_slowspr_addr : out std_ulogic_vector(11 to 20); + xu_lsu_slowspr_data : out std_ulogic_vector(64-regsize to 63); + + -- DCR Bus + ac_an_dcr_act : out std_ulogic; + ac_an_dcr_val : out std_ulogic; + ac_an_dcr_read : out std_ulogic; + ac_an_dcr_user : out std_ulogic; + ac_an_dcr_etid : out std_ulogic_vector(0 to 1); + ac_an_dcr_addr : out std_ulogic_vector(11 to 20); + ac_an_dcr_data : out std_ulogic_vector(64-regsize to 63); + + -- Flush + xu_ex4_flush : in std_ulogic_vector(0 to threads-1); + xu_ex5_flush : in std_ulogic_vector(0 to threads-1); + + -- Trap + spr_cpl_fp_precise : out std_ulogic_vector(0 to threads-1); + spr_cpl_ex3_spr_hypv : out std_ulogic; + spr_cpl_ex3_spr_illeg : out std_ulogic; + spr_cpl_ex3_spr_priv : out std_ulogic; + spr_cpl_ex3_ct_le : out std_ulogic_vector(0 to threads-1); + spr_cpl_ex3_ct_be : out std_ulogic_vector(0 to threads-1); + + -- Run State + cpl_spr_stop : in std_ulogic_vector(0 to threads-1); + xu_pc_running : out std_ulogic_vector(0 to threads-1); + xu_iu_run_thread : out std_ulogic_vector(0 to threads-1); + xu_iu_single_instr_mode : out std_ulogic_vector(0 to threads-1); + xu_iu_raise_iss_pri : out std_ulogic_vector(0 to threads-1); + spr_cpl_ex2_run_ctl_flush : out std_ulogic_vector(0 to threads-1); + xu_pc_spr_ccr0_we : out std_ulogic_vector(0 to threads-1); + + -- Quiesce + iu_xu_quiesce : in std_ulogic_vector(0 to threads-1); + lsu_xu_quiesce : in std_ulogic_vector(0 to threads-1); + mm_xu_quiesce : in std_ulogic_vector(0 to threads-1); + bx_xu_quiesce : in std_ulogic_vector(0 to threads-1); + cpl_spr_quiesce : in std_ulogic_vector(0 to threads-1); + spr_cpl_quiesce : out std_ulogic_vector(0 to threads-1); + + -- PCCR0 + pc_xu_extirpts_dis_on_stop : in std_ulogic; + pc_xu_timebase_dis_on_stop : in std_ulogic; + pc_xu_decrem_dis_on_stop : in std_ulogic; + + -- MSR Override + pc_xu_ram_mode : in std_ulogic; + pc_xu_ram_thread : in std_ulogic_vector(0 to 1); + pc_xu_msrovride_enab : in std_ulogic; + pc_xu_msrovride_pr : in std_ulogic; + pc_xu_msrovride_gs : in std_ulogic; + pc_xu_msrovride_de : in std_ulogic; + + -- LiveLock + cpl_spr_ex5_instr_cpl : in std_ulogic_vector(0 to threads-1); + xu_pc_err_llbust_attempt : out std_ulogic_vector(0 to threads-1); + xu_pc_err_llbust_failed : out std_ulogic_vector(0 to threads-1); + + -- XER + spr_byp_ex4_is_mtxer : out std_ulogic_vector(0 to threads-1); + spr_byp_ex4_is_mfxer : out std_ulogic_vector(0 to threads-1); + + -- Resets + pc_xu_reset_wd_complete : in std_ulogic; + pc_xu_reset_1_complete : in std_ulogic; + pc_xu_reset_2_complete : in std_ulogic; + pc_xu_reset_3_complete : in std_ulogic; + ac_tc_reset_1_request : out std_ulogic; + ac_tc_reset_2_request : out std_ulogic; + ac_tc_reset_3_request : out std_ulogic; + ac_tc_reset_wd_request : out std_ulogic; + + -- Err Inject + pc_xu_inj_llbust_attempt : in std_ulogic_vector(0 to threads-1); + pc_xu_inj_llbust_failed : in std_ulogic_vector(0 to threads-1); + pc_xu_inj_wdt_reset : in std_ulogic_vector(0 to threads-1); + xu_pc_err_wdt_reset : out std_ulogic_vector(0 to threads-1); + + -- Parity + spr_cpl_ex3_sprg_ce : out std_ulogic; + spr_cpl_ex3_sprg_ue : out std_ulogic; + pc_xu_inj_sprg_ecc : in std_ulogic_vector(0 to threads-1); + xu_pc_err_sprg_ecc : out std_ulogic_vector(0 to threads-1); + + -- Perf + spr_perf_tx_events : out std_ulogic_vector(0 to 8*threads-1); + xu_lsu_mtspr_trace_en : out std_ulogic_vector(0 to threads-1); + + -- SPRs + cpl_spr_dbcr0_edm : in std_ulogic_vector(0 to threads-1); + spr_bit_act : out std_ulogic; + spr_xucr0_clkg_ctl : out std_ulogic_vector(0 to 3); + spr_cpl_iac1_en : out std_ulogic_vector(0 to threads-1); + spr_cpl_iac2_en : out std_ulogic_vector(0 to threads-1); + spr_cpl_iac3_en : out std_ulogic_vector(0 to threads-1); + spr_cpl_iac4_en : out std_ulogic_vector(0 to threads-1); + lsu_xu_spr_xucr0_cslc_xuop : in std_ulogic; + lsu_xu_spr_xucr0_cslc_binv : in std_ulogic; + lsu_xu_spr_xucr0_clo : in std_ulogic; + lsu_xu_spr_xucr0_cul : in std_ulogic; + lsu_xu_spr_epsc_egs : in std_ulogic_vector(0 to threads-1); + lsu_xu_spr_epsc_epr : in std_ulogic_vector(0 to threads-1); + spr_epcr_extgs : out std_ulogic_vector(0 to threads-1); + spr_msr_de : out std_ulogic_vector(0 to threads-1); + spr_msr_pr : out std_ulogic_vector(0 to threads-1); + spr_msr_is : out std_ulogic_vector(0 to threads-1); + spr_msr_cm : out std_ulogic_vector(0 to threads-1); + spr_msr_gs : out std_ulogic_vector(0 to threads-1); + spr_msr_ee : out std_ulogic_vector(0 to threads-1); + spr_msr_ce : out std_ulogic_vector(0 to threads-1); + spr_msr_me : out std_ulogic_vector(0 to threads-1); + xu_lsu_spr_xucr0_clfc : out std_ulogic; + xu_pc_spr_ccr0_pme : out std_ulogic_vector(0 to 1); + spr_ccr2_en_dcr : out std_ulogic; + spr_ccr2_en_pc : out std_ulogic; + xu_iu_spr_ccr2_ifratsc : out std_ulogic_vector(0 to 8); + xu_iu_spr_ccr2_ifrat : out std_ulogic; + xu_lsu_spr_ccr2_dfratsc : out std_ulogic_vector(0 to 8); + xu_lsu_spr_ccr2_dfrat : out std_ulogic; + spr_ccr2_ucode_dis : out std_ulogic; + spr_ccr2_ap : out std_ulogic_vector(0 to 3); + spr_ccr2_en_attn : out std_ulogic; + spr_ccr2_en_ditc : out std_ulogic; + spr_ccr2_en_icswx : out std_ulogic; + spr_ccr2_notlb : out std_ulogic; + xu_lsu_spr_xucr0_mbar_ack : out std_ulogic; + xu_lsu_spr_xucr0_tlbsync : out std_ulogic; + spr_dec_spr_xucr0_ssdly : out std_ulogic_vector(0 to 4); + spr_xucr0_cls : out std_ulogic; + xu_lsu_spr_xucr0_aflsta : out std_ulogic; + spr_xucr0_mddp : out std_ulogic; + xu_lsu_spr_xucr0_cred : out std_ulogic; + xu_lsu_spr_xucr0_rel : out std_ulogic; + spr_xucr0_mdcp : out std_ulogic; + xu_lsu_spr_xucr0_flsta : out std_ulogic; + xu_lsu_spr_xucr0_l2siw : out std_ulogic; + xu_lsu_spr_xucr0_flh2l2 : out std_ulogic; + xu_lsu_spr_xucr0_dcdis : out std_ulogic; + xu_lsu_spr_xucr0_wlk : out std_ulogic; + spr_dbcr0_idm : out std_ulogic_vector(0 to threads-1); + spr_dbcr0_icmp : out std_ulogic_vector(0 to threads-1); + spr_dbcr0_brt : out std_ulogic_vector(0 to threads-1); + spr_dbcr0_irpt : out std_ulogic_vector(0 to threads-1); + spr_dbcr0_trap : out std_ulogic_vector(0 to threads-1); + spr_dbcr0_dac1 : out std_ulogic_vector(0 to 2*threads-1); + spr_dbcr0_dac2 : out std_ulogic_vector(0 to 2*threads-1); + spr_dbcr0_ret : out std_ulogic_vector(0 to threads-1); + spr_dbcr0_dac3 : out std_ulogic_vector(0 to 2*threads-1); + spr_dbcr0_dac4 : out std_ulogic_vector(0 to 2*threads-1); + spr_dbcr1_iac12m : out std_ulogic_vector(0 to threads-1); + spr_dbcr1_iac34m : out std_ulogic_vector(0 to threads-1); + spr_epcr_dtlbgs : out std_ulogic_vector(0 to threads-1); + spr_epcr_itlbgs : out std_ulogic_vector(0 to threads-1); + spr_epcr_dsigs : out std_ulogic_vector(0 to threads-1); + spr_epcr_isigs : out std_ulogic_vector(0 to threads-1); + spr_epcr_duvd : out std_ulogic_vector(0 to threads-1); + spr_epcr_dgtmi : out std_ulogic_vector(0 to threads-1); + xu_mm_spr_epcr_dmiuh : out std_ulogic_vector(0 to threads-1); + spr_msr_ucle : out std_ulogic_vector(0 to threads-1); + spr_msr_spv : out std_ulogic_vector(0 to threads-1); + spr_msr_fp : out std_ulogic_vector(0 to threads-1); + spr_msr_ds : out std_ulogic_vector(0 to threads-1); + spr_msrp_uclep : out std_ulogic_vector(0 to threads-1); + + -- BOLT-ON + bo_enable_2 : in std_ulogic; -- general bolt-on enable + pc_xu_bo_reset : in std_ulogic; -- reset + pc_xu_bo_unload : in std_ulogic; -- unload sticky bits + pc_xu_bo_repair : in std_ulogic; -- execute sticky bit decode + pc_xu_bo_shdata : in std_ulogic; -- shift data for timing write and diag loop + pc_xu_bo_select : in std_ulogic; -- select for mask and hier writes + xu_pc_bo_fail : out std_ulogic; -- fail/no-fix reg + xu_pc_bo_diagout : out std_ulogic; + -- ABIST + an_ac_lbist_ary_wrt_thru_dc : in std_ulogic; + pc_xu_abist_ena_dc : in std_ulogic; + pc_xu_abist_g8t_wenb : in std_ulogic; + pc_xu_abist_waddr_0 : in std_ulogic_vector(4 to 9); + pc_xu_abist_di_0 : in std_ulogic_vector(0 to 3); + pc_xu_abist_g8t1p_renb_0 : in std_ulogic; + pc_xu_abist_raddr_0 : in std_ulogic_vector(4 to 9); + pc_xu_abist_wl32_comp_ena : in std_ulogic; + pc_xu_abist_raw_dc_b : in std_ulogic; + pc_xu_abist_g8t_dcomp : in std_ulogic_vector(0 to 3); + pc_xu_abist_g8t_bw_1 : in std_ulogic; + pc_xu_abist_g8t_bw_0 : in std_ulogic; + + -- Debug + lsu_xu_cmd_debug : in std_ulogic_vector(0 to 175); + pc_xu_trace_bus_enable : in std_ulogic; + spr_debug_mux_ctrls : in std_ulogic_vector(0 to 15); + spr_debug_data_in : in std_ulogic_vector(0 to 87); + spr_debug_data_out : out std_ulogic_vector(0 to 87); + spr_trigger_data_in : in std_ulogic_vector(0 to 11); + spr_trigger_data_out : out std_ulogic_vector(0 to 11); + + -- Power + vcs : inout power_logic; + vdd : inout power_logic; + gnd : inout power_logic +); + +-- synopsys translate_off + +-- synopsys translate_on +end xuq_spr; +architecture xuq_spr of xuq_spr is + + +-- FUNC Latches +signal reset_1_request_q, reset_1_request_d : std_ulogic; +signal reset_2_request_q, reset_2_request_d : std_ulogic; +signal reset_3_request_q, reset_3_request_d : std_ulogic; +signal reset_wd_request_q,reset_wd_request_d : std_ulogic; +signal trace_bus_enable_q : std_ulogic; -- input=>pc_xu_trace_bus_enable , act=>tiup , scan=>Y, sleep=>Y, needs_sreset=>0 +signal debug_mux_ctrls_q : std_ulogic_vector(0 to 15); -- input=>spr_debug_mux_ctrls , act=>trace_bus_enable_q , scan=>Y, sleep=>Y, needs_sreset=>0 +signal debug_data_out_q, debug_data_out_d : std_ulogic_vector(0 to 87); -- input=>debug_data_out_d , act=>trace_bus_enable_q , scan=>Y, sleep=>Y, needs_sreset=>0 +signal trigger_data_out_q, trigger_data_out_d : std_ulogic_vector(0 to 11); -- input=>trigger_data_out_d , act=>trace_bus_enable_q , scan=>Y, sleep=>Y, needs_sreset=>0 +-- Scanchains +constant trace_bus_enable_offset : integer := 0; +constant debug_mux_ctrls_offset : integer := trace_bus_enable_offset + 1; +constant debug_data_out_offset : integer := debug_mux_ctrls_offset + debug_mux_ctrls_q'length; +constant trigger_data_out_offset : integer := debug_data_out_offset + debug_data_out_q'length; +constant xu_spr_cspr_offset : integer := trigger_data_out_offset + trigger_data_out_q'length; +constant scan_right : integer := xu_spr_cspr_offset + 1; +signal siv : std_ulogic_vector(0 to scan_right-1); +signal sov : std_ulogic_vector(0 to scan_right-1); +-- ABST Latches +signal abist_g8t_wenb_q : std_ulogic; -- pc_xu_abist_g8t_wenb +signal abist_waddr_0_q : std_ulogic_vector(4 to 9); -- pc_xu_abist_waddr_0 +signal abist_di_0_q : std_ulogic_vector(0 to 3); -- pc_xu_abist_di_0 +signal abist_g8t1p_renb_0_q : std_ulogic; -- pc_xu_abist_g8t1p_renb_0 +signal abist_raddr_0_q : std_ulogic_vector(4 to 9); -- pc_xu_abist_raddr_0 +signal abist_wl32_comp_ena_q : std_ulogic; -- pc_xu_abist_wl32_comp_ena +signal abist_g8t_dcomp_q : std_ulogic_vector(0 to 3); -- pc_xu_abist_g8t_dcomp +signal abist_g8t_bw_1_q : std_ulogic; -- pc_xu_abist_g8t_bw_1 +signal abist_g8t_bw_0_q : std_ulogic; -- pc_xu_abist_g8t_bw_0 +-- Scanchains +constant xu_spr_aspr_offset_abst : integer := 1; +constant abist_g8t_wenb_offset_abst : integer := xu_spr_aspr_offset_abst + 1; +constant abist_waddr_0_offset_abst : integer := abist_g8t_wenb_offset_abst + 1; +constant abist_di_0_offset_abst : integer := abist_waddr_0_offset_abst + abist_waddr_0_q'length; +constant abist_g8t1p_renb_0_offset_abst : integer := abist_di_0_offset_abst + abist_di_0_q'length; +constant abist_raddr_0_offset_abst : integer := abist_g8t1p_renb_0_offset_abst + 1; +constant abist_wl32_comp_ena_offset_abst : integer := abist_raddr_0_offset_abst + abist_raddr_0_q'length; +constant abist_g8t_dcomp_offset_abst : integer := abist_wl32_comp_ena_offset_abst + 1; +constant abist_g8t_bw_1_offset_abst : integer := abist_g8t_dcomp_offset_abst + abist_g8t_dcomp_q'length; +constant abist_g8t_bw_0_offset_abst : integer := abist_g8t_bw_1_offset_abst + 1; +constant scan_right_abst : integer := abist_g8t_bw_0_offset_abst + 2; +-- Scanchain Repower +signal siv_abst : std_ulogic_vector(0 to scan_right_abst-1); +signal sov_abst : std_ulogic_vector(0 to scan_right_abst-1); +signal siv_bcfg : std_ulogic_vector(0 to 2); +signal sov_bcfg : std_ulogic_vector(0 to 2); +signal siv_ccfg : std_ulogic_vector(0 to threads+2); +signal sov_ccfg : std_ulogic_vector(0 to threads+2); +signal siv_dcfg : std_ulogic_vector(0 to threads+1); +signal sov_dcfg : std_ulogic_vector(0 to threads+1); +signal siv_time : std_ulogic_vector(0 to 2); +signal sov_time : std_ulogic_vector(0 to 2); +signal siv_gptr : std_ulogic_vector(0 to 2); +signal sov_gptr : std_ulogic_vector(0 to 2); +signal siv_repr : std_ulogic_vector(0 to 2); +signal sov_repr : std_ulogic_vector(0 to 2); +signal func_scan_rpwr_in : std_ulogic_vector(0 to threads+1); +signal func_scan_rpwr_out : std_ulogic_vector(0 to threads+1); +signal func_scan_gate_out : std_ulogic_vector(0 to threads+1); +-- Signals +signal g8t_clkoff_dc_b : std_ulogic; +signal g8t_d_mode_dc : std_ulogic; +signal g8t_mpw1_dc_b : std_ulogic_vector(0 to 4); +signal g8t_mpw2_dc_b : std_ulogic; +signal g8t_delay_lclkr_dc : std_ulogic_vector(0 to 4); +signal func_slp_nsl_thold_1 : std_ulogic; +signal func_nsl_thold_1 : std_ulogic; +signal func_slp_sl_thold_1 : std_ulogic; +signal func_sl_thold_1 : std_ulogic; +signal time_sl_thold_1 : std_ulogic; +signal abst_sl_thold_1 : std_ulogic; +signal repr_sl_thold_1 : std_ulogic; +signal gptr_sl_thold_1 : std_ulogic; +signal bolt_sl_thold_1 : std_ulogic; +signal ary_nsl_thold_1 : std_ulogic; +signal cfg_sl_thold_1 : std_ulogic; +signal cfg_slp_sl_thold_1 : std_ulogic; +signal fce_1 : std_ulogic; +signal sg_1 : std_ulogic; +signal func_slp_nsl_thold_0 : std_ulogic; +signal func_nsl_thold_0 : std_ulogic_vector(0 to threads); +signal func_slp_sl_thold_0 : std_ulogic_vector(0 to threads); +signal func_sl_thold_0 : std_ulogic_vector(0 to threads); +signal cfg_sl_thold_0 : std_ulogic_vector(0 to threads); +signal cfg_slp_sl_thold_0 : std_ulogic; +signal fce_0 : std_ulogic_vector(0 to threads); +signal sg_0 : std_ulogic_vector(0 to threads); +signal cfg_slp_sl_force : std_ulogic; +signal cfg_slp_sl_thold_0_b : std_ulogic; +signal bcfg_slp_sl_force : std_ulogic; +signal bcfg_slp_sl_thold_0_b : std_ulogic; +signal cfg_sl_force : std_ulogic_vector(0 to threads); +signal cfg_sl_thold_0_b : std_ulogic_vector(0 to threads); +signal bcfg_sl_force : std_ulogic_vector(0 to 0); +signal bcfg_sl_thold_0_b : std_ulogic_vector(0 to 0); +signal ccfg_sl_force : std_ulogic_vector(0 to threads); +signal ccfg_sl_thold_0_b : std_ulogic_vector(0 to threads); +signal dcfg_sl_force : std_ulogic_vector(1 to threads); +signal dcfg_sl_thold_0_b : std_ulogic_vector(1 to threads); +signal func_sl_force : std_ulogic_vector(0 to threads); +signal func_sl_thold_0_b : std_ulogic_vector(0 to threads); +signal func_slp_sl_force : std_ulogic_vector(0 to threads); +signal func_slp_sl_thold_0_b : std_ulogic_vector(0 to threads); +signal func_nsl_force : std_ulogic_vector(0 to threads); +signal func_nsl_thold_0_b : std_ulogic_vector(0 to threads); +signal func_slp_nsl_force : std_ulogic; +signal func_slp_nsl_thold_0_b : std_ulogic; +signal repr_sl_thold_0 : std_ulogic; +signal gptr_sl_thold_0 : std_ulogic; +signal bolt_sl_thold_0 : std_ulogic; +signal time_sl_thold_0 : std_ulogic; +signal abst_sl_force : std_ulogic; +signal abst_sl_thold_0 : std_ulogic; +signal abst_sl_thold_0_b : std_ulogic; +signal ary_nsl_thold_0 : std_ulogic; +signal so_force : std_ulogic; +signal abst_so_thold_0_b : std_ulogic; +signal bcfg_so_thold_0_b : std_ulogic; +signal ccfg_so_thold_0_b : std_ulogic; +signal dcfg_so_thold_0_b : std_ulogic; +signal time_so_thold_0_b : std_ulogic; +signal repr_so_thold_0_b : std_ulogic; +signal gptr_so_thold_0_b : std_ulogic; +signal func_so_thold_0_b : std_ulogic; +signal cspr_tspr_ex1_instr : std_ulogic_vector(0 to 31); +signal cspr_tspr_ex2_tid : std_ulogic_vector(0 to threads-1); +signal cspr_tspr_ex5_is_mtmsr : std_ulogic; +signal cspr_tspr_ex5_is_mtspr : std_ulogic; +signal cspr_tspr_ex5_instr : std_ulogic_vector(11 to 20); +signal cspr_tspr_ex5_is_wrtee : std_ulogic; +signal cspr_tspr_ex5_is_wrteei : std_ulogic; +signal cspr_tspr_timebase_taps : std_ulogic_vector(0 to 9); +signal tspr_cspr_ex3_tspr_rt : std_ulogic_vector(0 to regsize*threads-1); +signal tspr_cspr_illeg_mtspr_b : std_ulogic_vector(0 to threads-1); +signal tspr_cspr_illeg_mfspr_b : std_ulogic_vector(0 to threads-1); +signal tspr_cspr_hypv_mtspr : std_ulogic_vector(0 to threads-1); +signal tspr_cspr_hypv_mfspr : std_ulogic_vector(0 to threads-1); +signal tspr_cspr_freeze_timers : std_ulogic_vector(0 to threads-1); +signal cspr_aspr_ex5_we : std_ulogic; +signal cspr_aspr_ex5_waddr : std_ulogic_vector(0 to 5); +signal cspr_aspr_rf1_re : std_ulogic; +signal cspr_aspr_rf1_raddr : std_ulogic_vector(0 to 5); +signal aspr_cspr_ex1_rdata : std_ulogic_vector(64-regsize to 72-(64/regsize)); +signal cspr_tspr_msrovride_en : std_ulogic_vector(0 to threads-1); +signal cspr_tspr_ram_mode : std_ulogic_vector(0 to threads-1); +signal tspr_epcr_extgs : std_ulogic_vector(0 to threads-1); +signal tspr_msr_de : std_ulogic_vector(0 to threads-1); +signal tspr_msr_pr : std_ulogic_vector(0 to threads-1); +signal tspr_msr_is : std_ulogic_vector(0 to threads-1); +signal tspr_msr_cm : std_ulogic_vector(0 to threads-1); +signal tspr_msr_gs : std_ulogic_vector(0 to threads-1); +signal tspr_msr_ee : std_ulogic_vector(0 to threads-1); +signal tspr_msr_ce : std_ulogic_vector(0 to threads-1); +signal tspr_msr_me : std_ulogic_vector(0 to threads-1); +signal tspr_fp_precise : std_ulogic_vector(0 to threads-1); +signal cspr_tspr_llen : std_ulogic_vector(0 to threads-1); +signal cspr_tspr_llpri : std_ulogic_vector(0 to threads-1); +signal tspr_cspr_lldet : std_ulogic_vector(0 to threads-1); +signal tspr_cspr_llpulse : std_ulogic_vector(0 to threads-1); +signal cspr_tspr_dec_dbg_dis : std_ulogic_vector(0 to threads-1); +signal reset_1_request : std_ulogic_vector(0 to threads-1); +signal reset_2_request : std_ulogic_vector(0 to threads-1); +signal reset_3_request : std_ulogic_vector(0 to threads-1); +signal reset_wd_request : std_ulogic_vector(0 to threads-1); +signal cspr_tspr_crit_mask : std_ulogic_vector(0 to threads-1); +signal cspr_tspr_ext_mask : std_ulogic_vector(0 to threads-1); +signal cspr_tspr_dec_mask : std_ulogic_vector(0 to threads-1); +signal cspr_tspr_fit_mask : std_ulogic_vector(0 to threads-1); +signal cspr_tspr_wdog_mask : std_ulogic_vector(0 to threads-1); +signal cspr_tspr_udec_mask : std_ulogic_vector(0 to threads-1); +signal cspr_tspr_perf_mask : std_ulogic_vector(0 to threads-1); +signal tspr_cspr_pm_wake_up : std_ulogic_vector(0 to threads-1); +signal tspr_cspr_async_int : std_ulogic_vector(0 to 3*threads-1); +signal reset_wd_complete : std_ulogic; +signal reset_1_complete : std_ulogic; +signal reset_2_complete : std_ulogic; +signal reset_3_complete : std_ulogic; +signal timer_update : std_ulogic; +signal cspr_tspr_dbell_pirtag : std_ulogic_vector(50 to 63); +signal tspr_cspr_gpir_match : std_ulogic_vector(0 to threads-1); +signal ex5_spr_wd : std_ulogic_vector(64-regsize to 64+8-(64/regsize)); +signal cspr_tspr_rf1_act : std_ulogic; +signal cspr_xucr0_clkg_ctl : std_ulogic_vector(0 to 4); +signal instr_trace_mode : std_ulogic_vector(0 to threads-1); +signal tspr_debug : std_ulogic_vector(0 to 12*threads-1); +signal cspr_debug0 : std_ulogic_vector(0 to 39); +signal cspr_debug1 : std_ulogic_vector(0 to 87); +signal dbg_group0, dbg_group1 : std_ulogic_vector(0 to 87); +signal dbg_group2, dbg_group3 : std_ulogic_vector(0 to 87); +signal trg_group0, trg_group1 : std_ulogic_vector(0 to 11); +signal trg_group2, trg_group3 : std_ulogic_vector(0 to 11); +signal tidn, tiup : std_ulogic; + +begin + +tidn <= '0'; +tiup <= '1'; + + +spr_epcr_extgs <= tspr_epcr_extgs; +spr_msr_de <= tspr_msr_de; +spr_msr_pr <= tspr_msr_pr; +spr_msr_is <= tspr_msr_is; +spr_msr_cm <= tspr_msr_cm; +spr_msr_gs <= tspr_msr_gs; +spr_msr_ee <= tspr_msr_ee; +spr_msr_ce <= tspr_msr_ce; +spr_msr_me <= tspr_msr_me; +spr_cpl_fp_precise <= tspr_fp_precise; +reset_1_request_d <= or_reduce(reset_1_request); +reset_2_request_d <= or_reduce(reset_2_request); +reset_3_request_d <= or_reduce(reset_3_request); +reset_wd_request_d <= or_reduce(reset_wd_request); +ac_tc_reset_1_request <= reset_1_request_q; +ac_tc_reset_2_request <= reset_2_request_q; +ac_tc_reset_3_request <= reset_3_request_q; +ac_tc_reset_wd_request <= reset_wd_request_q; +spr_xucr0_clkg_ctl <= cspr_xucr0_clkg_ctl(0 to 3); + + +xu_spr_cspr : entity work.xuq_spr_cspr(xuq_spr_cspr) +generic map( + hvmode => hvmode, + a2mode => a2mode, + expand_type => expand_type, + threads => threads, + regsize => regsize, + eff_ifar => eff_ifar, + spr_xucr0_init_mod => spr_xucr0_init_mod) +port map( + nclk => nclk, + -- CHIP IO + an_ac_sleep_en => an_ac_sleep_en, + an_ac_reservation_vld => an_ac_reservation_vld, + an_ac_tb_update_enable => an_ac_tb_update_enable, + an_ac_tb_update_pulse => an_ac_tb_update_pulse, + an_ac_coreid => an_ac_coreid, + pc_xu_instr_trace_mode => pc_xu_instr_trace_mode, + pc_xu_instr_trace_tid => pc_xu_instr_trace_tid, + instr_trace_mode => instr_trace_mode, + spr_pvr_version_dc => spr_pvr_version_dc, + spr_pvr_revision_dc => spr_pvr_revision_dc, + d_mode_dc => d_mode_dc, + delay_lclkr_dc(0) => delay_lclkr_dc, + mpw1_dc_b(0) => mpw1_dc_b, + mpw2_dc_b => mpw2_dc_b, + bcfg_sl_force => bcfg_sl_force(0), + bcfg_sl_thold_0_b => bcfg_sl_thold_0_b(0), + bcfg_slp_sl_force => bcfg_slp_sl_force, + bcfg_slp_sl_thold_0_b => bcfg_slp_sl_thold_0_b, + ccfg_sl_force => ccfg_sl_force(0), + ccfg_sl_thold_0_b => ccfg_sl_thold_0_b(0), + func_sl_force => func_sl_force(0), + func_sl_thold_0_b => func_sl_thold_0_b(0), + func_slp_sl_force => func_slp_sl_force(0), + func_slp_sl_thold_0_b => func_slp_sl_thold_0_b(0), + + func_nsl_force => func_nsl_force(0), + func_nsl_thold_0_b => func_nsl_thold_0_b(0), + func_slp_nsl_force => func_slp_nsl_force, + func_slp_nsl_thold_0_b => func_slp_nsl_thold_0_b, + + sg_0 => sg_0(0), + scan_in(0) => func_scan_rpwr_in(threads), + scan_in(1) => siv(xu_spr_cspr_offset), + scan_out(0) => func_scan_rpwr_out(threads), + scan_out(1) => sov(xu_spr_cspr_offset), + bcfg_scan_in => siv_bcfg(1), + bcfg_scan_out => sov_bcfg(1), + ccfg_scan_in => siv_ccfg(1), + ccfg_scan_out => sov_ccfg(1), + cspr_tspr_rf1_act => cspr_tspr_rf1_act, + -- Decode + dec_spr_rf0_tid => dec_spr_rf0_tid, + dec_spr_rf0_instr => dec_spr_rf0_instr, + dec_spr_rf1_val => dec_spr_rf1_val, + dec_spr_ex4_val => dec_spr_ex4_val, + -- Read Data + tspr_cspr_ex3_tspr_rt => tspr_cspr_ex3_tspr_rt, + spr_byp_ex3_spr_rt => spr_byp_ex3_spr_rt, + -- Write Data + mux_spr_ex2_rt => mux_spr_ex2_rt, + fxu_spr_ex1_rs0 => fxu_spr_ex1_rs0, + fxu_spr_ex1_rs1 => fxu_spr_ex1_rs1, + ex5_spr_wd => ex5_spr_wd, + -- SPRT Interface + cspr_tspr_ex1_instr => cspr_tspr_ex1_instr, + cspr_tspr_ex2_tid => cspr_tspr_ex2_tid, + cspr_tspr_ex5_is_mtmsr => cspr_tspr_ex5_is_mtmsr, + cspr_tspr_ex5_is_mtspr => cspr_tspr_ex5_is_mtspr, + cspr_tspr_ex5_is_wrtee => cspr_tspr_ex5_is_wrtee, + cspr_tspr_ex5_is_wrteei => cspr_tspr_ex5_is_wrteei, + cspr_tspr_ex5_instr => cspr_tspr_ex5_instr, + cspr_tspr_timebase_taps => cspr_tspr_timebase_taps, + timer_update => timer_update, + cspr_tspr_dec_dbg_dis => cspr_tspr_dec_dbg_dis, + -- Illegal SPR + tspr_cspr_illeg_mtspr_b => tspr_cspr_illeg_mtspr_b, + tspr_cspr_illeg_mfspr_b => tspr_cspr_illeg_mfspr_b, + tspr_cspr_hypv_mtspr => tspr_cspr_hypv_mtspr, + tspr_cspr_hypv_mfspr => tspr_cspr_hypv_mfspr, + -- Array SPRs + cspr_aspr_ex5_we => cspr_aspr_ex5_we, + cspr_aspr_ex5_waddr => cspr_aspr_ex5_waddr, + cspr_aspr_rf1_re => cspr_aspr_rf1_re, + cspr_aspr_rf1_raddr => cspr_aspr_rf1_raddr, + aspr_cspr_ex1_rdata => aspr_cspr_ex1_rdata(64-regsize to 72-(64/regsize)), + -- Slow SPR Bus + xu_lsu_slowspr_val => xu_lsu_slowspr_val, + xu_lsu_slowspr_rw => xu_lsu_slowspr_rw, + xu_lsu_slowspr_etid => xu_lsu_slowspr_etid, + xu_lsu_slowspr_addr => xu_lsu_slowspr_addr, + xu_lsu_slowspr_data => xu_lsu_slowspr_data, + -- DCR Bus + ac_an_dcr_act => ac_an_dcr_act, + ac_an_dcr_val => ac_an_dcr_val, + ac_an_dcr_read => ac_an_dcr_read, + ac_an_dcr_user => ac_an_dcr_user, + ac_an_dcr_etid => ac_an_dcr_etid, + ac_an_dcr_addr => ac_an_dcr_addr, + ac_an_dcr_data => ac_an_dcr_data, + -- Flush + xu_ex4_flush => xu_ex4_flush, + xu_ex5_flush => xu_ex5_flush, + -- Trap + spr_cpl_ex3_spr_hypv => spr_cpl_ex3_spr_hypv, + spr_cpl_ex3_spr_illeg => spr_cpl_ex3_spr_illeg, + spr_cpl_ex3_spr_priv => spr_cpl_ex3_spr_priv, + -- Run State + cpl_spr_stop => cpl_spr_stop, + xu_iu_run_thread => xu_iu_run_thread, + spr_cpl_ex2_run_ctl_flush => spr_cpl_ex2_run_ctl_flush, + xu_pc_spr_ccr0_we => xu_pc_spr_ccr0_we, + -- Quiesce + iu_xu_quiesce => iu_xu_quiesce, + lsu_xu_quiesce => lsu_xu_quiesce, + mm_xu_quiesce => mm_xu_quiesce, + bx_xu_quiesce => bx_xu_quiesce, + cpl_spr_quiesce => cpl_spr_quiesce, + xu_pc_running => xu_pc_running, + spr_cpl_quiesce => spr_cpl_quiesce, + -- PCCR0 + pc_xu_extirpts_dis_on_stop => pc_xu_extirpts_dis_on_stop, + pc_xu_timebase_dis_on_stop => pc_xu_timebase_dis_on_stop, + pc_xu_decrem_dis_on_stop => pc_xu_decrem_dis_on_stop, + -- MSR Override + pc_xu_ram_mode => pc_xu_ram_mode, + pc_xu_ram_thread => pc_xu_ram_thread, + pc_xu_msrovride_enab => pc_xu_msrovride_enab, + cspr_tspr_msrovride_en => cspr_tspr_msrovride_en, + cspr_tspr_ram_mode => cspr_tspr_ram_mode, + -- LiveLock + cspr_tspr_llen => cspr_tspr_llen, + cspr_tspr_llpri => cspr_tspr_llpri, + tspr_cspr_lldet => tspr_cspr_lldet, + tspr_cspr_llpulse => tspr_cspr_llpulse, + -- Reset + pc_xu_reset_wd_complete => pc_xu_reset_wd_complete, + pc_xu_reset_1_complete => pc_xu_reset_1_complete, + pc_xu_reset_2_complete => pc_xu_reset_2_complete, + pc_xu_reset_3_complete => pc_xu_reset_3_complete, + reset_wd_complete => reset_wd_complete, + reset_1_complete => reset_1_complete, + reset_2_complete => reset_2_complete, + reset_3_complete => reset_3_complete, + -- Async Interrupt Req Interface + cspr_tspr_crit_mask => cspr_tspr_crit_mask, + cspr_tspr_ext_mask => cspr_tspr_ext_mask, + cspr_tspr_dec_mask => cspr_tspr_dec_mask, + cspr_tspr_fit_mask => cspr_tspr_fit_mask, + cspr_tspr_wdog_mask => cspr_tspr_wdog_mask, + cspr_tspr_udec_mask => cspr_tspr_udec_mask, + cspr_tspr_perf_mask => cspr_tspr_perf_mask, + tspr_cspr_pm_wake_up => tspr_cspr_pm_wake_up, + -- DBELL + spr_cpl_dbell_interrupt => spr_cpl_dbell_interrupt, + spr_cpl_cdbell_interrupt => spr_cpl_cdbell_interrupt, + spr_cpl_gdbell_interrupt => spr_cpl_gdbell_interrupt, + spr_cpl_gcdbell_interrupt => spr_cpl_gcdbell_interrupt, + spr_cpl_gmcdbell_interrupt => spr_cpl_gmcdbell_interrupt, + cpl_spr_ex5_dbell_taken => cpl_spr_ex5_dbell_taken, + cpl_spr_ex5_cdbell_taken => cpl_spr_ex5_cdbell_taken, + cpl_spr_ex5_gdbell_taken => cpl_spr_ex5_gdbell_taken, + cpl_spr_ex5_gcdbell_taken => cpl_spr_ex5_gcdbell_taken, + cpl_spr_ex5_gmcdbell_taken => cpl_spr_ex5_gmcdbell_taken, + cspr_tspr_dbell_pirtag => cspr_tspr_dbell_pirtag, + tspr_cspr_gpir_match => tspr_cspr_gpir_match, + lsu_xu_dbell_val => lsu_xu_dbell_val, + lsu_xu_dbell_type => lsu_xu_dbell_type, + lsu_xu_dbell_brdcast => lsu_xu_dbell_brdcast, + lsu_xu_dbell_lpid_match => lsu_xu_dbell_lpid_match, + lsu_xu_dbell_pirtag => lsu_xu_dbell_pirtag, + -- Parity + spr_cpl_ex3_sprg_ce => spr_cpl_ex3_sprg_ce, + spr_cpl_ex3_sprg_ue => spr_cpl_ex3_sprg_ue, + pc_xu_inj_sprg_ecc => pc_xu_inj_sprg_ecc, + xu_pc_err_sprg_ecc => xu_pc_err_sprg_ecc, + -- Debug + tspr_cspr_freeze_timers => tspr_cspr_freeze_timers, + tspr_cspr_async_int => tspr_cspr_async_int, + -- Perf + spr_perf_tx_events => spr_perf_tx_events, + xu_lsu_mtspr_trace_en => xu_lsu_mtspr_trace_en, + -- SPRs + lsu_xu_spr_xucr0_cslc_xuop => lsu_xu_spr_xucr0_cslc_xuop, + lsu_xu_spr_xucr0_cslc_binv => lsu_xu_spr_xucr0_cslc_binv, + lsu_xu_spr_xucr0_clo => lsu_xu_spr_xucr0_clo, + lsu_xu_spr_xucr0_cul => lsu_xu_spr_xucr0_cul, + tspr_msr_gs => tspr_msr_gs, + tspr_msr_pr => tspr_msr_pr, + tspr_msr_ee => tspr_msr_ee, + tspr_msr_ce => tspr_msr_ce, + tspr_msr_me => tspr_msr_me, + cspr_xucr0_clkg_ctl => cspr_xucr0_clkg_ctl, + xu_lsu_spr_xucr0_clfc => xu_lsu_spr_xucr0_clfc, + spr_bit_act => spr_bit_act, + xu_pc_spr_ccr0_pme => xu_pc_spr_ccr0_pme, + spr_ccr2_en_dcr => spr_ccr2_en_dcr, + spr_ccr2_en_pc => spr_ccr2_en_pc, + xu_iu_spr_ccr2_ifratsc => xu_iu_spr_ccr2_ifratsc, + xu_iu_spr_ccr2_ifrat => xu_iu_spr_ccr2_ifrat, + xu_lsu_spr_ccr2_dfratsc => xu_lsu_spr_ccr2_dfratsc, + xu_lsu_spr_ccr2_dfrat => xu_lsu_spr_ccr2_dfrat, + spr_ccr2_ucode_dis => spr_ccr2_ucode_dis, + spr_ccr2_ap => spr_ccr2_ap, + spr_ccr2_en_attn => spr_ccr2_en_attn, + spr_ccr2_en_ditc => spr_ccr2_en_ditc, + spr_ccr2_en_icswx => spr_ccr2_en_icswx, + spr_ccr2_notlb => spr_ccr2_notlb, + xu_lsu_spr_xucr0_mbar_ack => xu_lsu_spr_xucr0_mbar_ack, + xu_lsu_spr_xucr0_tlbsync => xu_lsu_spr_xucr0_tlbsync, + spr_dec_spr_xucr0_ssdly => spr_dec_spr_xucr0_ssdly, + spr_xucr0_cls => spr_xucr0_cls, + xu_lsu_spr_xucr0_aflsta => xu_lsu_spr_xucr0_aflsta, + spr_xucr0_mddp => spr_xucr0_mddp, + xu_lsu_spr_xucr0_cred => xu_lsu_spr_xucr0_cred, + xu_lsu_spr_xucr0_rel => xu_lsu_spr_xucr0_rel, + spr_xucr0_mdcp => spr_xucr0_mdcp, + xu_lsu_spr_xucr0_flsta => xu_lsu_spr_xucr0_flsta, + xu_lsu_spr_xucr0_l2siw => xu_lsu_spr_xucr0_l2siw, + xu_lsu_spr_xucr0_flh2l2 => xu_lsu_spr_xucr0_flh2l2, + xu_lsu_spr_xucr0_dcdis => xu_lsu_spr_xucr0_dcdis, + xu_lsu_spr_xucr0_wlk => xu_lsu_spr_xucr0_wlk, + cspr_debug0 => cspr_debug0, + cspr_debug1 => cspr_debug1, + -- Power + vdd => vdd, + gnd => gnd +); + +thread : for t in 0 to threads-1 generate +xu_spr_tspr : entity work.xuq_spr_tspr(xuq_spr_tspr) +generic map( + hvmode => hvmode, + a2mode => a2mode, + expand_type => expand_type, + regsize => regsize, + eff_ifar => eff_ifar) +port map( + nclk => nclk, + -- CHIP IO + an_ac_ext_interrupt => an_ac_ext_interrupt(t), + an_ac_crit_interrupt => an_ac_crit_interrupt(t), + an_ac_perf_interrupt => an_ac_perf_interrupt(t), + an_ac_hang_pulse => an_ac_hang_pulse(t), + ac_tc_machine_check => ac_tc_machine_check(t), + an_ac_external_mchk => an_ac_external_mchk(t), + instr_trace_mode => instr_trace_mode(t), + -- Act + d_mode_dc => d_mode_dc, + delay_lclkr_dc(0) => delay_lclkr_dc, + mpw1_dc_b(0) => mpw1_dc_b, + mpw2_dc_b => mpw2_dc_b, + func_sl_force => func_sl_force(1+t), + func_sl_thold_0_b => func_sl_thold_0_b(1+t), + func_nsl_force => func_nsl_force(1+t), + func_nsl_thold_0_b => func_nsl_thold_0_b(1+t), + func_slp_sl_force => func_slp_sl_force(1+t), + func_slp_sl_thold_0_b => func_slp_sl_thold_0_b(1+t), + ccfg_sl_force => ccfg_sl_force(1+t), + ccfg_sl_thold_0_b => ccfg_sl_thold_0_b(1+t), + dcfg_sl_force => dcfg_sl_force(1+t), + dcfg_sl_thold_0_b => dcfg_sl_thold_0_b(1+t), + sg_0 => sg_0(1+t), + scan_in => func_scan_rpwr_in(t), + scan_out => func_scan_rpwr_out(t), + ccfg_scan_in => siv_ccfg(2+t), + ccfg_scan_out => sov_ccfg(2+t), + dcfg_scan_in => siv_dcfg(1+t), + dcfg_scan_out => sov_dcfg(1+t), + cspr_tspr_rf1_act => cspr_tspr_rf1_act, + -- Read Interface + cspr_tspr_ex1_instr => cspr_tspr_ex1_instr, + cspr_tspr_ex2_tid => cspr_tspr_ex2_tid(t), + tspr_cspr_ex3_tspr_rt => tspr_cspr_ex3_tspr_rt(regsize*t to regsize*(t+1)-1), + -- Write Interface + dec_spr_ex4_val => dec_spr_ex4_val(t), + cspr_tspr_ex5_is_mtmsr => cspr_tspr_ex5_is_mtmsr, + cspr_tspr_ex5_is_mtspr => cspr_tspr_ex5_is_mtspr, + cspr_tspr_ex5_is_wrtee => cspr_tspr_ex5_is_wrtee, + cspr_tspr_ex5_is_wrteei => cspr_tspr_ex5_is_wrteei, + cspr_tspr_ex5_instr => cspr_tspr_ex5_instr, + ex5_spr_wd => ex5_spr_wd(64-regsize to 63), + cspr_tspr_dec_dbg_dis => cspr_tspr_dec_dbg_dis(t), + -- Illegal SPR + tspr_cspr_illeg_mtspr_b => tspr_cspr_illeg_mtspr_b(t), + tspr_cspr_illeg_mfspr_b => tspr_cspr_illeg_mfspr_b(t), + tspr_cspr_hypv_mtspr => tspr_cspr_hypv_mtspr(t), + tspr_cspr_hypv_mfspr => tspr_cspr_hypv_mfspr(t), + -- Interrupt Interface + cpl_spr_ex5_act => cpl_spr_ex5_act(t), + cpl_spr_ex5_int => cpl_spr_ex5_int(t), + cpl_spr_ex5_gint => cpl_spr_ex5_gint(t), + cpl_spr_ex5_cint => cpl_spr_ex5_cint(t), + cpl_spr_ex5_mcint => cpl_spr_ex5_mcint(t), + cpl_spr_ex5_nia => cpl_spr_ex5_nia(eff_ifar*t to eff_ifar*(t+1)-1), + cpl_spr_ex5_esr => cpl_spr_ex5_esr(17*t to 17*(t+1)-1), + cpl_spr_ex5_mcsr => cpl_spr_ex5_mcsr(15*t to 15*(t+1)-1), + cpl_spr_ex5_dbsr => cpl_spr_ex5_dbsr(19*t to 19*(t+1)-1), + cpl_spr_ex5_dear_update => cpl_spr_ex5_dear_update(t), + cpl_spr_ex5_dear_update_saved => cpl_spr_ex5_dear_update_saved(t), + cpl_spr_ex5_dear_save => cpl_spr_ex5_dear_save(t), + cpl_spr_ex5_dbsr_update => cpl_spr_ex5_dbsr_update(t), + cpl_spr_ex5_esr_update => cpl_spr_ex5_esr_update(t), + cpl_spr_ex5_srr0_dec => cpl_spr_ex5_srr0_dec(t), + cpl_spr_ex5_force_gsrr => cpl_spr_ex5_force_gsrr(t), + cpl_spr_ex5_dbsr_ide => cpl_spr_ex5_dbsr_ide(t), + spr_cpl_dbsr_ide => spr_cpl_dbsr_ide(t), + -- Async Interrupt Req Interface + spr_cpl_external_mchk => spr_cpl_external_mchk(t), + spr_cpl_ext_interrupt => spr_cpl_ext_interrupt(t), + spr_cpl_dec_interrupt => spr_cpl_dec_interrupt(t), + spr_cpl_udec_interrupt => spr_cpl_udec_interrupt(t), + spr_cpl_perf_interrupt => spr_cpl_perf_interrupt(t), + spr_cpl_fit_interrupt => spr_cpl_fit_interrupt(t), + spr_cpl_crit_interrupt => spr_cpl_crit_interrupt(t), + spr_cpl_wdog_interrupt => spr_cpl_wdog_interrupt(t), + cspr_tspr_crit_mask => cspr_tspr_crit_mask(t), + cspr_tspr_ext_mask => cspr_tspr_ext_mask(t), + cspr_tspr_dec_mask => cspr_tspr_dec_mask(t), + cspr_tspr_fit_mask => cspr_tspr_fit_mask(t), + cspr_tspr_wdog_mask => cspr_tspr_wdog_mask(t), + cspr_tspr_udec_mask => cspr_tspr_udec_mask(t), + cspr_tspr_perf_mask => cspr_tspr_perf_mask(t), + tspr_cspr_pm_wake_up => tspr_cspr_pm_wake_up(t), + tspr_cspr_async_int => tspr_cspr_async_int(3*t to 3*(t+1)-1), + -- ICSWX + dec_spr_ex1_epid_instr => dec_spr_ex1_epid_instr, + fxu_spr_ex1_rs2 => fxu_spr_ex1_rs2, + spr_cpl_ex3_ct_be => spr_cpl_ex3_ct_be(t), + spr_cpl_ex3_ct_le => spr_cpl_ex3_ct_le(t), + -- DBELL Int + cspr_tspr_dbell_pirtag => cspr_tspr_dbell_pirtag, + tspr_cspr_gpir_match => tspr_cspr_gpir_match(t), + cspr_tspr_timebase_taps => cspr_tspr_timebase_taps, + timer_update => timer_update, + -- Debug + spr_cpl_iac1_en => spr_cpl_iac1_en(t), + spr_cpl_iac2_en => spr_cpl_iac2_en(t), + spr_cpl_iac3_en => spr_cpl_iac3_en(t), + spr_cpl_iac4_en => spr_cpl_iac4_en(t), + tspr_cspr_freeze_timers => tspr_cspr_freeze_timers(t), + -- Flush + xu_ex4_flush => xu_ex4_flush(t), + xu_ex5_flush => xu_ex5_flush(t), + -- Run State + xu_iu_single_instr_mode => xu_iu_single_instr_mode(t), + xu_iu_raise_iss_pri => xu_iu_raise_iss_pri(t), + -- LiveLock + cpl_spr_ex5_instr_cpl => cpl_spr_ex5_instr_cpl(t), + cspr_tspr_llen => cspr_tspr_llen(t), + cspr_tspr_llpri => cspr_tspr_llpri(t), + tspr_cspr_lldet => tspr_cspr_lldet(t), + tspr_cspr_llpulse => tspr_cspr_llpulse(t), + xu_pc_err_llbust_attempt => xu_pc_err_llbust_attempt(t), + xu_pc_err_llbust_failed => xu_pc_err_llbust_failed(t), + pc_xu_inj_llbust_attempt => pc_xu_inj_llbust_attempt(t), + pc_xu_inj_llbust_failed => pc_xu_inj_llbust_failed(t), + pc_xu_inj_wdt_reset => pc_xu_inj_wdt_reset(t), + -- XER + spr_byp_ex4_is_mtxer => spr_byp_ex4_is_mtxer(t), + spr_byp_ex4_is_mfxer => spr_byp_ex4_is_mfxer(t), + -- Resets + reset_wd_complete => reset_wd_complete, + reset_1_complete => reset_1_complete, + reset_2_complete => reset_2_complete, + reset_3_complete => reset_3_complete, + reset_1_request => reset_1_request(t), + reset_2_request => reset_2_request(t), + reset_3_request => reset_3_request(t), + reset_wd_request => reset_wd_request(t), + xu_pc_err_wdt_reset => xu_pc_err_wdt_reset(t), + -- MSR Override + cspr_tspr_ram_mode => cspr_tspr_ram_mode(t), + cspr_tspr_msrovride_en => cspr_tspr_msrovride_en(t), + pc_xu_msrovride_pr => pc_xu_msrovride_pr, + pc_xu_msrovride_gs => pc_xu_msrovride_gs, + pc_xu_msrovride_de => pc_xu_msrovride_de, + -- SPRs + cpl_spr_dbcr0_edm => cpl_spr_dbcr0_edm(t), + lsu_xu_spr_epsc_egs => lsu_xu_spr_epsc_egs(t), + lsu_xu_spr_epsc_epr => lsu_xu_spr_epsc_epr(t), + tspr_epcr_extgs => tspr_epcr_extgs(t), + tspr_fp_precise => tspr_fp_precise(t), + tspr_msr_de => tspr_msr_de(t), + tspr_msr_pr => tspr_msr_pr(t), + tspr_msr_is => tspr_msr_is(t), + tspr_msr_cm => tspr_msr_cm(t), + tspr_msr_gs => tspr_msr_gs(t), + tspr_msr_ee => tspr_msr_ee(t), + tspr_msr_ce => tspr_msr_ce(t), + tspr_msr_me => tspr_msr_me(t), + cspr_xucr0_clkg_ctl => cspr_xucr0_clkg_ctl(4 to 4), + spr_dbcr0_idm => spr_dbcr0_idm(t), + spr_dbcr0_icmp => spr_dbcr0_icmp(t), + spr_dbcr0_brt => spr_dbcr0_brt(t), + spr_dbcr0_irpt => spr_dbcr0_irpt(t), + spr_dbcr0_trap => spr_dbcr0_trap(t), + spr_dbcr0_dac1 => spr_dbcr0_dac1(2*t to 2*(t+1)-1), + spr_dbcr0_dac2 => spr_dbcr0_dac2(2*t to 2*(t+1)-1), + spr_dbcr0_ret => spr_dbcr0_ret(t), + spr_dbcr0_dac3 => spr_dbcr0_dac3(2*t to 2*(t+1)-1), + spr_dbcr0_dac4 => spr_dbcr0_dac4(2*t to 2*(t+1)-1), + spr_dbcr1_iac12m => spr_dbcr1_iac12m(t), + spr_dbcr1_iac34m => spr_dbcr1_iac34m(t), + spr_epcr_dtlbgs => spr_epcr_dtlbgs(t), + spr_epcr_itlbgs => spr_epcr_itlbgs(t), + spr_epcr_dsigs => spr_epcr_dsigs(t), + spr_epcr_isigs => spr_epcr_isigs(t), + spr_epcr_duvd => spr_epcr_duvd(t), + spr_epcr_dgtmi => spr_epcr_dgtmi(t), + xu_mm_spr_epcr_dmiuh => xu_mm_spr_epcr_dmiuh(t), + spr_msr_ucle => spr_msr_ucle(t), + spr_msr_spv => spr_msr_spv(t), + spr_msr_fp => spr_msr_fp(t), + spr_msr_ds => spr_msr_ds(t), + spr_msrp_uclep => spr_msrp_uclep(t), + tspr_debug => tspr_debug(12*t to 12*(t+1)-1), + -- Power + vdd => vdd, + gnd => gnd +); +end generate; + + +xu_spr_aspr : entity tri.tri_64x72_1r1w(tri_64x72_1r1w) +generic map( + expand_type => expand_type, + regsize => regsize) +port map ( + vdd => vdd, + vcs => vcs, + gnd => gnd, + nclk => nclk, + sg_0 => sg_0(0), + abst_sl_thold_0 => abst_sl_thold_0, + ary_nsl_thold_0 => ary_nsl_thold_0, + time_sl_thold_0 => time_sl_thold_0, + repr_sl_thold_0 => repr_sl_thold_0, + -- Reads + rd0_act => cspr_aspr_rf1_re, + rd0_adr => cspr_aspr_rf1_raddr, + do0 => aspr_cspr_ex1_rdata, + -- Writes + wr_act => cspr_aspr_ex5_we, + wr_adr => cspr_aspr_ex5_waddr, + di => ex5_spr_wd, + -- Scan + abst_scan_in => siv_abst(xu_spr_aspr_offset_abst), + abst_scan_out => sov_abst(xu_spr_aspr_offset_abst), + time_scan_in => siv_time(1), + time_scan_out => sov_time(1), + repr_scan_in => siv_repr(1), + repr_scan_out => sov_repr(1), + -- Misc Pervasive + scan_dis_dc_b => an_ac_scan_dis_dc_b, + scan_diag_dc => an_ac_scan_diag_dc, + ccflush_dc => pc_xu_ccflush_dc, + clkoff_dc_b => g8t_clkoff_dc_b, + d_mode_dc => g8t_d_mode_dc, + mpw1_dc_b => g8t_mpw1_dc_b, + mpw2_dc_b => g8t_mpw2_dc_b, + delay_lclkr_dc => g8t_delay_lclkr_dc, + -- BOLT-ON + lcb_bolt_sl_thold_0 => bolt_sl_thold_0, + pc_bo_enable_2 => bo_enable_2, -- general bolt-on enable + pc_bo_reset => pc_xu_bo_reset, -- reset + pc_bo_unload => pc_xu_bo_unload, -- unload sticky bits + pc_bo_repair => pc_xu_bo_repair, -- execute sticky bit decode + pc_bo_shdata => pc_xu_bo_shdata, -- shift data for timing write and diag loop + pc_bo_select => pc_xu_bo_select, -- select for mask and hier writes + bo_pc_failout => xu_pc_bo_fail, -- fail/no-fix reg + bo_pc_diagloop => xu_pc_bo_diagout, + tri_lcb_mpw1_dc_b => mpw1_dc_b, + tri_lcb_mpw2_dc_b => mpw2_dc_b, + tri_lcb_delay_lclkr_dc => delay_lclkr_dc, + tri_lcb_clkoff_dc_b => clkoff_dc_b, + tri_lcb_act_dis_dc => tidn, + -- ABIST + abist_bw_odd => abist_g8t_bw_1_q, + abist_bw_even => abist_g8t_bw_0_q, + tc_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc, + abist_ena_1 => pc_xu_abist_ena_dc, + wr_abst_act => abist_g8t_wenb_q, + abist_wr_adr => abist_waddr_0_q, + abist_di => abist_di_0_q, + rd0_abst_act => abist_g8t1p_renb_0_q, + abist_rd0_adr => abist_raddr_0_q, + abist_g8t_rd0_comp_ena => abist_wl32_comp_ena_q, + abist_raw_dc_b => pc_xu_abist_raw_dc_b, + obs0_abist_cmp => abist_g8t_dcomp_q + ); + +xu_debug_mux : entity clib.c_debug_mux4(c_debug_mux4) +port map( + vd => vdd, + gd => gnd, + select_bits => debug_mux_ctrls_q, + trace_data_in => spr_debug_data_in, + trigger_data_in => spr_trigger_data_in, + dbg_group0 => dbg_group0, + dbg_group1 => dbg_group1, + dbg_group2 => dbg_group2, + dbg_group3 => dbg_group3, + trg_group0 => trg_group0, + trg_group1 => trg_group1, + trg_group2 => trg_group2, + trg_group3 => trg_group3, + trigger_data_out => trigger_data_out_d, + trace_data_out => debug_data_out_d); + +dbg_group0 <= cspr_debug0 & tspr_debug; +dbg_group1 <= cspr_debug1; +dbg_group2 <= lsu_xu_cmd_debug(0 to 87); +dbg_group3 <= lsu_xu_cmd_debug(88 to 175); +trg_group0 <= (others=>'0'); +trg_group1 <= (others=>'0'); +trg_group2 <= (others=>'0'); +trg_group3 <= (others=>'0'); + +spr_trigger_data_out <= trigger_data_out_q; +spr_debug_data_out <= debug_data_out_q; + + +-- FUNC Latch Instances +reset_1_request_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_nsl_force(0), + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b(0), + din(0) => reset_1_request_d, + dout(0) => reset_1_request_q); +reset_2_request_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_nsl_force(0), + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b(0), + din(0) => reset_2_request_d, + dout(0) => reset_2_request_q); +reset_3_request_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_nsl_force(0), + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b(0), + din(0) => reset_3_request_d, + dout(0) => reset_3_request_q); +reset_wd_request_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_nsl_force(0), + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b(0), + din(0) => reset_wd_request_d, + dout(0) => reset_wd_request_q); +trace_bus_enable_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force(0), + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b(0), + sg => sg_0(0), + scin => siv(trace_bus_enable_offset), + scout => sov(trace_bus_enable_offset), + din => pc_xu_trace_bus_enable , + dout => trace_bus_enable_q); +debug_mux_ctrls_latch : tri_rlmreg_p + generic map (width => debug_mux_ctrls_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_slp_sl_force(0), + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b(0), + sg => sg_0(0), + scin => siv(debug_mux_ctrls_offset to debug_mux_ctrls_offset + debug_mux_ctrls_q'length-1), + scout => sov(debug_mux_ctrls_offset to debug_mux_ctrls_offset + debug_mux_ctrls_q'length-1), + din => spr_debug_mux_ctrls , + dout => debug_mux_ctrls_q); +debug_data_out_latch : tri_rlmreg_p + generic map (width => debug_data_out_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_slp_sl_force(0), + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b(0), + sg => sg_0(0), + scin => siv(debug_data_out_offset to debug_data_out_offset + debug_data_out_q'length-1), + scout => sov(debug_data_out_offset to debug_data_out_offset + debug_data_out_q'length-1), + din => debug_data_out_d, + dout => debug_data_out_q); +trigger_data_out_latch : tri_rlmreg_p + generic map (width => trigger_data_out_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => trace_bus_enable_q , + forcee => func_slp_sl_force(0), + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b(0), + sg => sg_0(0), + scin => siv(trigger_data_out_offset to trigger_data_out_offset + trigger_data_out_q'length-1), + scout => sov(trigger_data_out_offset to trigger_data_out_offset + trigger_data_out_q'length-1), + din => trigger_data_out_d, + dout => trigger_data_out_q); +-- ABST Latch Instances +abist_g8t_wenb_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => pc_xu_abist_ena_dc, + forcee => abst_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => abst_sl_thold_0_b, + sg => sg_0(0), + scin => siv_abst(abist_g8t_wenb_offset_abst), + scout => sov_abst(abist_g8t_wenb_offset_abst), + din => pc_xu_abist_g8t_wenb, + dout => abist_g8t_wenb_q); +abist_waddr_0_latch : tri_rlmreg_p + generic map (width => abist_waddr_0_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => pc_xu_abist_ena_dc, + forcee => abst_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => abst_sl_thold_0_b, + sg => sg_0(0), + scin => siv_abst(abist_waddr_0_offset_abst to abist_waddr_0_offset_abst + abist_waddr_0_q'length-1), + scout => sov_abst(abist_waddr_0_offset_abst to abist_waddr_0_offset_abst + abist_waddr_0_q'length-1), + din => pc_xu_abist_waddr_0, + dout => abist_waddr_0_q); +abist_di_0_latch : tri_rlmreg_p + generic map (width => abist_di_0_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => pc_xu_abist_ena_dc, + forcee => abst_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => abst_sl_thold_0_b, + sg => sg_0(0), + scin => siv_abst(abist_di_0_offset_abst to abist_di_0_offset_abst + abist_di_0_q'length-1), + scout => sov_abst(abist_di_0_offset_abst to abist_di_0_offset_abst + abist_di_0_q'length-1), + din => pc_xu_abist_di_0, + dout => abist_di_0_q); +abist_g8t1p_renb_0_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => pc_xu_abist_ena_dc, + forcee => abst_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => abst_sl_thold_0_b, + sg => sg_0(0), + scin => siv_abst(abist_g8t1p_renb_0_offset_abst), + scout => sov_abst(abist_g8t1p_renb_0_offset_abst), + din => pc_xu_abist_g8t1p_renb_0, + dout => abist_g8t1p_renb_0_q); +abist_raddr_0_latch : tri_rlmreg_p + generic map (width => abist_raddr_0_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => pc_xu_abist_ena_dc, + forcee => abst_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => abst_sl_thold_0_b, + sg => sg_0(0), + scin => siv_abst(abist_raddr_0_offset_abst to abist_raddr_0_offset_abst + abist_raddr_0_q'length-1), + scout => sov_abst(abist_raddr_0_offset_abst to abist_raddr_0_offset_abst + abist_raddr_0_q'length-1), + din => pc_xu_abist_raddr_0, + dout => abist_raddr_0_q); +abist_wl32_comp_ena_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => pc_xu_abist_ena_dc, + forcee => abst_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => abst_sl_thold_0_b, + sg => sg_0(0), + scin => siv_abst(abist_wl32_comp_ena_offset_abst), + scout => sov_abst(abist_wl32_comp_ena_offset_abst), + din => pc_xu_abist_wl32_comp_ena, + dout => abist_wl32_comp_ena_q); +abist_g8t_dcomp_latch : tri_rlmreg_p + generic map (width => abist_g8t_dcomp_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => pc_xu_abist_ena_dc, + forcee => abst_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => abst_sl_thold_0_b, + sg => sg_0(0), + scin => siv_abst(abist_g8t_dcomp_offset_abst to abist_g8t_dcomp_offset_abst + abist_g8t_dcomp_q'length-1), + scout => sov_abst(abist_g8t_dcomp_offset_abst to abist_g8t_dcomp_offset_abst + abist_g8t_dcomp_q'length-1), + din => pc_xu_abist_g8t_dcomp, + dout => abist_g8t_dcomp_q); +abist_g8t_bw_1_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => pc_xu_abist_ena_dc, + forcee => abst_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => abst_sl_thold_0_b, + sg => sg_0(0), + scin => siv_abst(abist_g8t_bw_1_offset_abst), + scout => sov_abst(abist_g8t_bw_1_offset_abst), + din => pc_xu_abist_g8t_bw_1, + dout => abist_g8t_bw_1_q); +abist_g8t_bw_0_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => pc_xu_abist_ena_dc, + forcee => abst_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b, + thold_b => abst_sl_thold_0_b, + sg => sg_0(0), + scin => siv_abst(abist_g8t_bw_0_offset_abst), + scout => sov_abst(abist_g8t_bw_0_offset_abst), + din => pc_xu_abist_g8t_bw_0, + dout => abist_g8t_bw_0_q); +abst_scan_in_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc, + thold_b => abst_so_thold_0_b, + scin => siv_abst(siv_abst'left to siv_abst'left), + scout => sov_abst(siv_abst'left to siv_abst'left), + dout => open); +abst_scan_out_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc, + thold_b => abst_so_thold_0_b, + scin => siv_abst(siv_abst'right to siv_abst'right), + scout => sov_abst(siv_abst'right to siv_abst'right), + dout => open); +bcfg_scan_in_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc, + thold_b => bcfg_so_thold_0_b, + scin => siv_bcfg(siv_bcfg'left to siv_bcfg'left), + scout => sov_bcfg(siv_bcfg'left to siv_bcfg'left), + dout => open); +bcfg_scan_out_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc, + thold_b => bcfg_so_thold_0_b, + scin => siv_bcfg(siv_bcfg'right to siv_bcfg'right), + scout => sov_bcfg(siv_bcfg'right to siv_bcfg'right), + dout => open); +ccfg_scan_in_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc, + thold_b => ccfg_so_thold_0_b, + scin => siv_ccfg(siv_ccfg'left to siv_ccfg'left), + scout => sov_ccfg(siv_ccfg'left to siv_ccfg'left), + dout => open); +ccfg_scan_out_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc, + thold_b => ccfg_so_thold_0_b, + scin => siv_ccfg(siv_ccfg'right to siv_ccfg'right), + scout => sov_ccfg(siv_ccfg'right to siv_ccfg'right), + dout => open); +dcfg_scan_in_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc, + thold_b => dcfg_so_thold_0_b, + scin => siv_dcfg(siv_dcfg'left to siv_dcfg'left), + scout => sov_dcfg(siv_dcfg'left to siv_dcfg'left), + dout => open); +dcfg_scan_out_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc, + thold_b => dcfg_so_thold_0_b, + scin => siv_dcfg(siv_dcfg'right to siv_dcfg'right), + scout => sov_dcfg(siv_dcfg'right to siv_dcfg'right), + dout => open); +time_scan_in_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc, + thold_b => time_so_thold_0_b, + scin => siv_time(siv_time'left to siv_time'left), + scout => sov_time(siv_time'left to siv_time'left), + dout => open); +time_scan_out_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc, + thold_b => time_so_thold_0_b, + scin => siv_time(siv_time'right to siv_time'right), + scout => sov_time(siv_time'right to siv_time'right), + dout => open); +repr_scan_in_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc, + thold_b => repr_so_thold_0_b, + scin => siv_repr(siv_repr'left to siv_repr'left), + scout => sov_repr(siv_repr'left to siv_repr'left), + dout => open); +repr_scan_out_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc, + thold_b => repr_so_thold_0_b, + scin => siv_repr(siv_repr'right to siv_repr'right), + scout => sov_repr(siv_repr'right to siv_repr'right), + dout => open); +gptr_scan_in_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => tiup, + thold_b => gptr_so_thold_0_b, + scin => siv_gptr(siv_gptr'left to siv_gptr'left), + scout => sov_gptr(siv_gptr'left to siv_gptr'left), + dout => open); +gptr_scan_out_latch : tri_regs + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => tiup, + thold_b => gptr_so_thold_0_b, + scin => siv_gptr(siv_gptr'right to siv_gptr'right), + scout => sov_gptr(siv_gptr'right to siv_gptr'right), + dout => open); +func_scan_in_latch : tri_regs + generic map (width => func_scan_in'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc, + thold_b => func_so_thold_0_b, + scin => func_scan_in, + scout => func_scan_rpwr_in, + dout => open); +func_scan_out_latch : tri_regs + generic map (width => func_scan_rpwr_out'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => so_force, + delay_lclkr => delay_lclkr_dc, + thold_b => func_so_thold_0_b, + scin => func_scan_rpwr_out, + scout => func_scan_gate_out, + dout => open); + +------------------------------------------------- +-- Pervasive +------------------------------------------------- +lcbctrl_g8t: tri_lcbcntl_array_mac + generic map (expand_type => expand_type) +port map ( + vdd => vdd, + gnd => gnd, + sg => sg_0(0), + nclk => nclk, + scan_in => siv_gptr(1), + scan_diag_dc => an_ac_scan_diag_dc, + thold => gptr_sl_thold_0, + clkoff_dc_b => g8t_clkoff_dc_b, + delay_lclkr_dc => g8t_delay_lclkr_dc(0 to 4), + act_dis_dc => open, + d_mode_dc => g8t_d_mode_dc, + mpw1_dc_b => g8t_mpw1_dc_b(0 to 4), + mpw2_dc_b => g8t_mpw2_dc_b, + scan_out => sov_gptr(1)); + +perv_2to1_reg: tri_plat + generic map (width => 14, expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_xu_ccflush_dc, + din(0) => func_slp_sl_thold_2, + din(1) => func_sl_thold_2, + din(2) => func_slp_nsl_thold_2, + din(3) => func_nsl_thold_2, + din(4) => time_sl_thold_2, + din(5) => repr_sl_thold_2, + din(6) => gptr_sl_thold_2, + din(7) => bolt_sl_thold_2, + din(8) => abst_sl_thold_2, + din(9) => ary_nsl_thold_2, + din(10) => cfg_sl_thold_2, + din(11) => cfg_slp_sl_thold_2, + din(12) => sg_2, + din(13) => fce_2, + q(0) => func_slp_sl_thold_1, + q(1) => func_sl_thold_1, + q(2) => func_slp_nsl_thold_1, + q(3) => func_nsl_thold_1, + q(4) => time_sl_thold_1, + q(5) => repr_sl_thold_1, + q(6) => gptr_sl_thold_1, + q(7) => bolt_sl_thold_1, + q(8) => abst_sl_thold_1, + q(9) => ary_nsl_thold_1, + q(10) => cfg_sl_thold_1, + q(11) => cfg_slp_sl_thold_1, + q(12) => sg_1, + q(13) => fce_1); + + +perv_1to0_reg_gen : for t in 0 to threads generate + perv_1to0_reg: tri_plat + generic map (width => 6, expand_type => expand_type) + port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_xu_ccflush_dc, + din(0) => func_slp_sl_thold_1, + din(1) => func_sl_thold_1, + din(2) => func_nsl_thold_1, + din(3) => cfg_sl_thold_1, + din(4) => sg_1, + din(5) => fce_1, + q(0) => func_slp_sl_thold_0(t), + q(1) => func_sl_thold_0(t), + q(2) => func_nsl_thold_0(t), + q(3) => cfg_sl_thold_0(t), + q(4) => sg_0(t), + q(5) => fce_0(t)); + + perv_lcbor_cfg_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_dc_b, + thold => cfg_sl_thold_0(t), + sg => sg_0(t), + act_dis => tidn, + forcee => cfg_sl_force(t), + thold_b => cfg_sl_thold_0_b(t)); + + perv_lcbor_func_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_dc_b, + thold => func_sl_thold_0(t), + sg => sg_0(t), + act_dis => tidn, + forcee => func_sl_force(t), + thold_b => func_sl_thold_0_b(t)); + + perv_lcbor_func_slp_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_dc_b, + thold => func_slp_sl_thold_0(t), + sg => sg_0(t), + act_dis => tidn, + forcee => func_slp_sl_force(t), + thold_b => func_slp_sl_thold_0_b(t)); + + perv_lcbor_func_nsl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_dc_b, + thold => func_nsl_thold_0(t), + sg => fce_0(t), + act_dis => tidn, + forcee => func_nsl_force(t), + thold_b => func_nsl_thold_0_b(t)); +end generate; + + ccfg_sl_force <= cfg_sl_force; + ccfg_sl_thold_0_b <= cfg_sl_thold_0_b; + dcfg_sl_force(1 to 4) <= cfg_sl_force(1 to 4); + dcfg_sl_thold_0_b(1 to 4) <= cfg_sl_thold_0_b(1 to 4); + + bcfg_sl_force(0) <= cfg_sl_force(0); + bcfg_sl_thold_0_b(0) <= cfg_sl_thold_0_b(0); + + bcfg_slp_sl_force <= cfg_slp_sl_force; + bcfg_slp_sl_thold_0_b <= cfg_slp_sl_thold_0_b; + + perv_lcbor_cfg_slp_sl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_dc_b, + thold => cfg_slp_sl_thold_0, + sg => sg_0(0), + act_dis => tidn, + forcee => cfg_slp_sl_force, + thold_b => cfg_slp_sl_thold_0_b); + + perv_lcbor_func_slp_nsl: tri_lcbor + generic map (expand_type => expand_type) + port map (clkoff_b => clkoff_dc_b, + thold => func_slp_nsl_thold_0, + sg => fce_0(0), + act_dis => tidn, + forcee => func_slp_nsl_force, + thold_b => func_slp_nsl_thold_0_b); + +perv_1to0_reg: tri_plat + generic map (width => 8, expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + flush => pc_xu_ccflush_dc, + din(0) => abst_sl_thold_1, + din(1) => ary_nsl_thold_1, + din(2) => time_sl_thold_1, + din(3) => repr_sl_thold_1, + din(4) => gptr_sl_thold_1, + din(5) => bolt_sl_thold_1, + din(6) => func_slp_nsl_thold_1, + din(7) => cfg_slp_sl_thold_1, + q(0) => abst_sl_thold_0, + q(1) => ary_nsl_thold_0, + q(2) => time_sl_thold_0, + q(3) => repr_sl_thold_0, + q(4) => gptr_sl_thold_0, + q(5) => bolt_sl_thold_0, + q(6) => func_slp_nsl_thold_0, + q(7) => cfg_slp_sl_thold_0); + +perv_lcbor_abst_sl: tri_lcbor + generic map (expand_type => expand_type) +port map (clkoff_b => clkoff_dc_b, + thold => abst_sl_thold_0, + sg => sg_0(0), + act_dis => tidn, + forcee => abst_sl_force, + thold_b => abst_sl_thold_0_b); + + + so_force <= sg_0(0); +abst_so_thold_0_b <= not abst_sl_thold_0; +bcfg_so_thold_0_b <= not cfg_sl_thold_0(0); +ccfg_so_thold_0_b <= not cfg_sl_thold_0(0); +dcfg_so_thold_0_b <= not cfg_sl_thold_0(0); +time_so_thold_0_b <= not time_sl_thold_0; +repr_so_thold_0_b <= not repr_sl_thold_0; +gptr_so_thold_0_b <= not gptr_sl_thold_0; +func_so_thold_0_b <= not func_sl_thold_0(0); + + +func_scan_out <= gate(func_scan_gate_out,an_ac_scan_dis_dc_b); + +siv(0 to siv'right) <= sov(1 to siv'right) & func_scan_rpwr_in(threads+1); +func_scan_rpwr_out(threads+1) <= sov(0); + +siv_abst(0 to siv_abst'right) <= sov_abst(1 to sov_abst'right) & abst_scan_in; +abst_scan_out <= sov_abst(0) and an_ac_scan_dis_dc_b; + +siv_bcfg(0 to siv_bcfg'right) <= sov_bcfg(1 to siv_bcfg'right) & bcfg_scan_in; +bcfg_scan_out <= sov_bcfg(0) and an_ac_scan_dis_dc_b; + +siv_ccfg(0 to siv_ccfg'right) <= sov_ccfg(1 to siv_ccfg'right) & ccfg_scan_in; +ccfg_scan_out <= sov_ccfg(0) and an_ac_scan_dis_dc_b; + +siv_dcfg(0 to siv_dcfg'right) <= sov_dcfg(1 to siv_dcfg'right) & dcfg_scan_in; +dcfg_scan_out <= sov_dcfg(0) and an_ac_scan_dis_dc_b; + +siv_time(0 to siv_time'right) <= sov_time(1 to siv_time'right) & time_scan_in; +time_scan_out <= sov_time(0) and an_ac_scan_dis_dc_b; + +siv_repr(0 to siv_repr'right) <= sov_repr(1 to siv_repr'right) & repr_scan_in; +repr_scan_out <= sov_repr(0) and an_ac_scan_dis_dc_b; + +siv_gptr(0 to siv_gptr'right) <= sov_gptr(1 to siv_gptr'right) & gptr_scan_in; +gptr_scan_out <= sov_gptr(0) and an_ac_scan_dis_dc_b; + +end architecture xuq_spr; diff --git a/rel/src/vhdl/work/xuq_spr_cspr.vhdl b/rel/src/vhdl/work/xuq_spr_cspr.vhdl new file mode 100644 index 0000000..ccfc042 --- /dev/null +++ b/rel/src/vhdl/work/xuq_spr_cspr.vhdl @@ -0,0 +1,4875 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XU SPR - per core registers & array +-- +library ieee,ibm,support,work,tri; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use support.power_logic_pkg.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use tri.tri_latches_pkg.all; +use work.xuq_pkg.all; + +entity xuq_spr_cspr is +generic( + hvmode : integer := 1; + a2mode : integer := 1; + expand_type : integer := 2; + threads : integer := 4; + regsize : integer := 64; + eff_ifar : integer := 62; + spr_xucr0_init_mod : integer := 0); +port( + nclk : in clk_logic; + + -- CHIP IO + an_ac_reservation_vld : in std_ulogic_vector(0 to threads-1); + an_ac_tb_update_enable : in std_ulogic; + an_ac_tb_update_pulse : in std_ulogic; + an_ac_sleep_en : in std_ulogic_vector(0 to threads-1); + an_ac_coreid : in std_ulogic_vector(54 to 61); + spr_pvr_version_dc : in std_ulogic_vector(8 to 15); + spr_pvr_revision_dc : in std_ulogic_vector(12 to 15); + pc_xu_instr_trace_mode : in std_ulogic; + pc_xu_instr_trace_tid : in std_ulogic_vector(0 to 1); + instr_trace_mode : out std_ulogic_vector(0 to threads-1); + + d_mode_dc : in std_ulogic; + delay_lclkr_dc : in std_ulogic_vector(0 to 0); + mpw1_dc_b : in std_ulogic_vector(0 to 0); + mpw2_dc_b : in std_ulogic; + + bcfg_sl_force : in std_ulogic; + bcfg_sl_thold_0_b : in std_ulogic; + bcfg_slp_sl_force : in std_ulogic; + bcfg_slp_sl_thold_0_b : in std_ulogic; + ccfg_sl_force : in std_ulogic; + ccfg_sl_thold_0_b : in std_ulogic; + func_sl_force : in std_ulogic; + func_sl_thold_0_b : in std_ulogic; + func_slp_sl_force : in std_ulogic; + func_slp_sl_thold_0_b : in std_ulogic; + func_nsl_force : in std_ulogic; + func_nsl_thold_0_b : in std_ulogic; + func_slp_nsl_force : in std_ulogic; + func_slp_nsl_thold_0_b : in std_ulogic; + sg_0 : in std_ulogic; + scan_in : in std_ulogic_vector(0 to 1); + scan_out : out std_ulogic_vector(0 to 1); + bcfg_scan_in : in std_ulogic; + bcfg_scan_out : out std_ulogic; + ccfg_scan_in : in std_ulogic; + ccfg_scan_out : out std_ulogic; + + cspr_tspr_rf1_act : out std_ulogic; + + -- Decode + dec_spr_rf0_tid : in std_ulogic_vector(0 to threads-1); + dec_spr_rf0_instr : in std_ulogic_vector(0 to 31); + dec_spr_rf1_val : in std_ulogic_vector(0 to 3); + dec_spr_ex4_val : in std_ulogic_vector(0 to threads-1); + + -- Read Data + tspr_cspr_ex3_tspr_rt : in std_ulogic_vector(0 to regsize*threads-1); + spr_byp_ex3_spr_rt : out std_ulogic_vector(64-regsize to 63); + + -- Write Data + fxu_spr_ex1_rs0 : in std_ulogic_vector(52 to 63); + fxu_spr_ex1_rs1 : in std_ulogic_vector(54 to 63); + mux_spr_ex2_rt : in std_ulogic_vector(64-regsize to 63); + ex5_spr_wd : out std_ulogic_vector(64-regsize to 64+8-(64/regsize)); + + -- SPRT Interface + cspr_tspr_ex2_tid : out std_ulogic_vector(0 to threads-1); + cspr_tspr_ex1_instr : out std_ulogic_vector(0 to 31); + cspr_tspr_ex5_is_mtmsr : out std_ulogic; + cspr_tspr_ex5_is_mtspr : out std_ulogic; + cspr_tspr_ex5_is_wrtee : out std_ulogic; + cspr_tspr_ex5_is_wrteei : out std_ulogic; + cspr_tspr_ex5_instr : out std_ulogic_vector(11 to 20); + cspr_tspr_dec_dbg_dis : out std_ulogic_vector(0 to threads-1); + + -- Illegal SPR + tspr_cspr_illeg_mtspr_b : in std_ulogic_vector(0 to threads-1); + tspr_cspr_illeg_mfspr_b : in std_ulogic_vector(0 to threads-1); + tspr_cspr_hypv_mtspr : in std_ulogic_vector(0 to threads-1); + tspr_cspr_hypv_mfspr : in std_ulogic_vector(0 to threads-1); + + -- Array SPRs + cspr_aspr_ex5_we : out std_ulogic; + cspr_aspr_ex5_waddr : out std_ulogic_vector(0 to 5); + cspr_aspr_rf1_re : out std_ulogic; + cspr_aspr_rf1_raddr : out std_ulogic_vector(0 to 5); + aspr_cspr_ex1_rdata : in std_ulogic_vector(64-regsize to 72-(64/regsize)); + + -- Slow SPR Bus + xu_lsu_slowspr_val : out std_ulogic; + xu_lsu_slowspr_rw : out std_ulogic; + xu_lsu_slowspr_etid : out std_ulogic_vector(0 to 1); + xu_lsu_slowspr_addr : out std_ulogic_vector(11 to 20); + xu_lsu_slowspr_data : out std_ulogic_vector(64-regsize to 63); + + -- DCR Bus + ac_an_dcr_act : out std_ulogic; + ac_an_dcr_val : out std_ulogic; + ac_an_dcr_read : out std_ulogic; + ac_an_dcr_user : out std_ulogic; + ac_an_dcr_etid : out std_ulogic_vector(0 to 1); + ac_an_dcr_addr : out std_ulogic_vector(11 to 20); + ac_an_dcr_data : out std_ulogic_vector(64-regsize to 63); + + -- Flush + xu_ex4_flush : in std_ulogic_vector(0 to threads-1); + xu_ex5_flush : in std_ulogic_vector(0 to threads-1); + + -- Trap + spr_cpl_ex3_spr_hypv : out std_ulogic; + spr_cpl_ex3_spr_illeg : out std_ulogic; + spr_cpl_ex3_spr_priv : out std_ulogic; + + cspr_tspr_timebase_taps : out std_ulogic_vector(0 to 9); + timer_update : out std_ulogic; + + -- Run State + cpl_spr_stop : in std_ulogic_vector(0 to threads-1); + xu_iu_run_thread : out std_ulogic_vector(0 to threads-1); + spr_cpl_ex2_run_ctl_flush : out std_ulogic_vector(0 to threads-1); + xu_pc_spr_ccr0_we : out std_ulogic_vector(0 to threads-1); + + -- Quiesce + iu_xu_quiesce : in std_ulogic_vector(0 to threads-1); + lsu_xu_quiesce : in std_ulogic_vector(0 to threads-1); + mm_xu_quiesce : in std_ulogic_vector(0 to threads-1); + bx_xu_quiesce : in std_ulogic_vector(0 to threads-1); + cpl_spr_quiesce : in std_ulogic_vector(0 to threads-1); + xu_pc_running : out std_ulogic_vector(0 to threads-1); + spr_cpl_quiesce : out std_ulogic_vector(0 to threads-1); + + -- PCCR0 + pc_xu_extirpts_dis_on_stop : in std_ulogic; + pc_xu_timebase_dis_on_stop : in std_ulogic; + pc_xu_decrem_dis_on_stop : in std_ulogic; + + -- MSR Override + pc_xu_ram_mode : in std_ulogic; + pc_xu_ram_thread : in std_ulogic_vector(0 to 1); + pc_xu_msrovride_enab : in std_ulogic; + cspr_tspr_msrovride_en : out std_ulogic_vector(0 to threads-1); + cspr_tspr_ram_mode : out std_ulogic_vector(0 to threads-1); + + -- LiveLock + cspr_tspr_llen : out std_ulogic_vector(0 to threads-1); + cspr_tspr_llpri : out std_ulogic_vector(0 to threads-1); + tspr_cspr_lldet : in std_ulogic_vector(0 to threads-1); + tspr_cspr_llpulse : in std_ulogic_vector(0 to threads-1); + + -- Reset + pc_xu_reset_wd_complete : in std_ulogic; + pc_xu_reset_3_complete : in std_ulogic; + pc_xu_reset_2_complete : in std_ulogic; + pc_xu_reset_1_complete : in std_ulogic; + reset_wd_complete : out std_ulogic; + reset_3_complete : out std_ulogic; + reset_2_complete : out std_ulogic; + reset_1_complete : out std_ulogic; + + -- Async Interrupt Masking + cspr_tspr_crit_mask : out std_ulogic_vector(0 to threads-1); + cspr_tspr_ext_mask : out std_ulogic_vector(0 to threads-1); + cspr_tspr_dec_mask : out std_ulogic_vector(0 to threads-1); + cspr_tspr_fit_mask : out std_ulogic_vector(0 to threads-1); + cspr_tspr_wdog_mask : out std_ulogic_vector(0 to threads-1); + cspr_tspr_udec_mask : out std_ulogic_vector(0 to threads-1); + cspr_tspr_perf_mask : out std_ulogic_vector(0 to threads-1); + + tspr_cspr_pm_wake_up : in std_ulogic_vector(0 to threads-1); + + -- More Async Interrupts + spr_cpl_dbell_interrupt : out std_ulogic_vector(0 to threads-1); + spr_cpl_cdbell_interrupt : out std_ulogic_vector(0 to threads-1); + spr_cpl_gdbell_interrupt : out std_ulogic_vector(0 to threads-1); + spr_cpl_gcdbell_interrupt : out std_ulogic_vector(0 to threads-1); + spr_cpl_gmcdbell_interrupt : out std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_dbell_taken : in std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_cdbell_taken : in std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_gdbell_taken : in std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_gcdbell_taken : in std_ulogic_vector(0 to threads-1); + cpl_spr_ex5_gmcdbell_taken : in std_ulogic_vector(0 to threads-1); + + -- DBELL Int + lsu_xu_dbell_val : in std_ulogic; + lsu_xu_dbell_type : in std_ulogic_vector(0 to 4); + lsu_xu_dbell_brdcast : in std_ulogic; + lsu_xu_dbell_lpid_match : in std_ulogic; + lsu_xu_dbell_pirtag : in std_ulogic_vector(50 to 63); + cspr_tspr_dbell_pirtag : out std_ulogic_vector(50 to 63); + tspr_cspr_gpir_match : in std_ulogic_vector(0 to threads-1); + + -- Parity + xu_pc_err_sprg_ecc : out std_ulogic_vector(0 to threads-1); + spr_cpl_ex3_sprg_ce : out std_ulogic; + spr_cpl_ex3_sprg_ue : out std_ulogic; + pc_xu_inj_sprg_ecc : in std_ulogic_vector(0 to threads-1); + + -- Debug + tspr_cspr_freeze_timers : in std_ulogic_vector(0 to threads-1); + tspr_cspr_async_int : in std_ulogic_vector(0 to 3*threads-1); + + + -- Perf + spr_perf_tx_events : out std_ulogic_vector(0 to 8*threads-1); + + xu_lsu_mtspr_trace_en : out std_ulogic_vector(0 to threads-1); + + lsu_xu_spr_xucr0_cslc_xuop : in std_ulogic; + lsu_xu_spr_xucr0_cslc_binv : in std_ulogic; + lsu_xu_spr_xucr0_clo : in std_ulogic; + lsu_xu_spr_xucr0_cul : in std_ulogic; + tspr_msr_ee : in std_ulogic_vector(0 to threads-1); + tspr_msr_ce : in std_ulogic_vector(0 to threads-1); + tspr_msr_me : in std_ulogic_vector(0 to threads-1); + tspr_msr_gs : in std_ulogic_vector(0 to threads-1); + tspr_msr_pr : in std_ulogic_vector(0 to threads-1); + cspr_xucr0_clkg_ctl : out std_ulogic_vector(0 to 4); + xu_lsu_spr_xucr0_clfc : out std_ulogic; + spr_bit_act : out std_ulogic; + xu_pc_spr_ccr0_pme : out std_ulogic_vector(0 to 1); + spr_ccr2_en_dcr : out std_ulogic; + spr_ccr2_en_pc : out std_ulogic; + xu_iu_spr_ccr2_ifratsc : out std_ulogic_vector(0 to 8); + xu_iu_spr_ccr2_ifrat : out std_ulogic; + xu_lsu_spr_ccr2_dfratsc : out std_ulogic_vector(0 to 8); + xu_lsu_spr_ccr2_dfrat : out std_ulogic; + spr_ccr2_ucode_dis : out std_ulogic; + spr_ccr2_ap : out std_ulogic_vector(0 to 3); + spr_ccr2_en_attn : out std_ulogic; + spr_ccr2_en_ditc : out std_ulogic; + spr_ccr2_en_icswx : out std_ulogic; + spr_ccr2_notlb : out std_ulogic; + xu_lsu_spr_xucr0_mbar_ack : out std_ulogic; + xu_lsu_spr_xucr0_tlbsync : out std_ulogic; + spr_dec_spr_xucr0_ssdly : out std_ulogic_vector(0 to 4); + spr_xucr0_cls : out std_ulogic; + xu_lsu_spr_xucr0_aflsta : out std_ulogic; + spr_xucr0_mddp : out std_ulogic; + xu_lsu_spr_xucr0_cred : out std_ulogic; + xu_lsu_spr_xucr0_rel : out std_ulogic; + spr_xucr0_mdcp : out std_ulogic; + xu_lsu_spr_xucr0_flsta : out std_ulogic; + xu_lsu_spr_xucr0_l2siw : out std_ulogic; + xu_lsu_spr_xucr0_flh2l2 : out std_ulogic; + xu_lsu_spr_xucr0_dcdis : out std_ulogic; + xu_lsu_spr_xucr0_wlk : out std_ulogic; + + cspr_debug0 : out std_ulogic_vector(0 to 39); + cspr_debug1 : out std_ulogic_vector(0 to 87); + + -- Power + vdd : inout power_logic; + gnd : inout power_logic +); + +-- synopsys translate_off + +-- synopsys translate_on +end xuq_spr_cspr; +architecture xuq_spr_cspr of xuq_spr_cspr is + +-- Constants +constant DRF1 : natural := 0; +constant DEX1 : natural := 0; +constant DEX2 : natural := 0; +constant DEX3 : natural := 0; +constant DEX4 : natural := 0; +constant DEX5 : natural := 0; +constant DEX6 : natural := 0; +constant DWR : natural := 0; +constant DX : natural := 0; +constant a2hvmode : natural := ((a2mode+hvmode) mod 1); +-- Types +subtype TID is std_ulogic_vector(0 to threads-1); +subtype DO is std_ulogic_vector(65-regsize to 64); +-- SPR Registers +signal ccr0_d , ccr0_q : std_ulogic_vector(58 to 63); +signal ccr1_d , ccr1_q : std_ulogic_vector(40 to 63); +signal ccr2_d , ccr2_q : std_ulogic_vector(32 to 63); +signal tbl_d , tbl_q : std_ulogic_vector(32 to 63); +signal tbu_d , tbu_q : std_ulogic_vector(32 to 63); +signal tens_d , tens_q : std_ulogic_vector(60 to 63); +signal xucr0_d , xucr0_q : std_ulogic_vector(33 to 63); +-- FUNC Scanchain +constant ccr1_offset : natural := 0; +constant tbl_offset : natural := ccr1_offset + ccr1_q'length; +constant tbu_offset : natural := tbl_offset + tbl_q'length; +constant last_reg_offset : natural := tbu_offset + tbu_q'length; +-- BCFG Scanchain +constant ccr0_offset_bcfg : natural := 0; +constant tens_offset_bcfg : natural := ccr0_offset_bcfg + ccr0_q'length; +constant last_reg_offset_bcfg : natural := tens_offset_bcfg + tens_q'length; +-- CCFG Scanchain +constant ccr2_offset_ccfg : natural := 0; +constant xucr0_offset_ccfg : natural := ccr2_offset_ccfg + ccr2_q'length; +constant last_reg_offset_ccfg : natural := xucr0_offset_ccfg + xucr0_q'length; +-- DCFG Scanchain +constant last_reg_offset_dcfg : natural := 1; +-- Latches +signal exx_act_q, exx_act_d : std_ulogic_vector(0 to 5); -- input=>exx_act_d , act=>tiup , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 +signal rf1_instr_q : std_ulogic_vector(0 to 31); -- input=>dec_spr_rf0_instr , act=>rf0_act , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal rf1_aspr_act_q, rf1_aspr_act_d : std_ulogic; -- input=>rf1_aspr_act_d , act=>tiup , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal rf1_aspr_tid_q, rf1_aspr_tid_d : std_ulogic_vector(0 to 1); -- input=>rf1_aspr_tid_d , act=>rf0_act , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal rf1_msr_gs_q, rf1_msr_gs_d : std_ulogic; -- input=>rf1_msr_gs_d , act=>tiup , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 +signal ex1_tid_q, rf1_tid : std_ulogic_vector(0 to 1); -- input=>rf1_tid , act=>exx_act(0) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex1_is_mfspr_q, rf1_is_mfspr : std_ulogic; -- input=>rf1_is_mfspr , act=>exx_act(0) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex1_is_mtspr_q, rf1_is_mtspr : std_ulogic; -- input=>rf1_is_mtspr , act=>exx_act(0) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex1_instr_q : std_ulogic_vector(0 to 31); -- input=>rf1_instr_q , act=>exx_act(0) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex1_aspr_re_q, rf1_aspr_re : std_ulogic_vector(2-regsize/32 to 1); -- input=>rf1_aspr_re , act=>exx_act(0) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex1_aspr_ce_addr_q, rf1_aspr_addr : std_ulogic_vector(0 to 3); -- input=>rf1_aspr_addr , act=>exx_act(0) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex2_tid_q : std_ulogic_vector(0 to 1); -- input=>ex1_tid_q , act=>exx_act(1) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex2_is_mfmsr_q, ex1_is_mfmsr : std_ulogic; -- input=>ex1_is_mfmsr , act=>exx_act(1) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex2_is_mfspr_q : std_ulogic; -- input=>ex1_is_mfspr_q , act=>exx_act(1) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex2_is_mftb_q, ex1_is_mftb : std_ulogic; -- input=>ex1_is_mftb , act=>exx_act(1) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex2_is_mtmsr_q, ex1_is_mtmsr : std_ulogic; -- input=>ex1_is_mtmsr , act=>exx_act(1) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex2_is_mtspr_q : std_ulogic; -- input=>ex1_is_mtspr_q , act=>exx_act(1) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex2_is_wait_q, ex1_is_wait : std_ulogic; -- input=>ex1_is_wait , act=>exx_act(1) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex2_wait_wc_q : std_ulogic_vector(9 to 10); -- input=>ex1_instr_q(9 to 10) , act=>exx_act_data(1), scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex2_is_msgclr_q, ex1_is_msgclr : std_ulogic; -- input=>ex1_is_msgclr , act=>exx_act(1) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex2_instr_q, ex2_instr_d : std_ulogic_vector(11 to 20); -- input=>ex2_instr_d , act=>exx_act(1) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex2_rs0_q : std_ulogic_vector(52 to 63); -- input=>fxu_spr_ex1_rs0 , act=>exx_act(1) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex2_msr_gs_q, ex2_msr_gs_d : std_ulogic_vector(0 to 0); -- input=>ex2_msr_gs_d , act=>tiup , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex2_tenc_we_q, ex1_tenc_we : std_ulogic; -- input=>ex1_tenc_we , act=>exx_act(1) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex2_ccr0_we_q, ex1_ccr0_we : std_ulogic; -- input=>ex1_ccr0_we , act=>exx_act(1) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex2_aspr_rdata_q, ex2_aspr_rdata_d : std_ulogic_vector(aspr_cspr_ex1_rdata'range);-- input=>ex2_aspr_rdata_d , act=>exx_act_data(1), scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex2_dcrn_q : std_ulogic_vector(54 to 63); -- input=>fxu_spr_ex1_rs1 , act=>exx_act_data(1), scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex2_dcr_val_q, ex1_dcr_val : std_ulogic; -- input=>ex1_dcr_val , act=>exx_act(1) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex2_aspr_ce_addr_q : std_ulogic_vector(0 to 3); -- input=>ex1_aspr_ce_addr_q , act=>exx_act(1) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex2_aspr_re_q : std_ulogic_vector(2-regsize/32 to 1); -- input=>ex1_aspr_re_q , act=>exx_act(1) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex2_dcr_read_q, ex1_dcr_read : std_ulogic; -- input=>ex1_dcr_read , act=>exx_act(1) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex2_dcr_user_q, ex1_dcr_user : std_ulogic; -- input=>ex1_dcr_user , act=>exx_act(1) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex2_is_wrtee_q, ex1_is_wrtee : std_ulogic; -- input=>ex1_is_wrtee , act=>exx_act(1) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex2_is_wrteei_q, ex1_is_wrteei : std_ulogic; -- input=>ex1_is_wrteei , act=>exx_act(1) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex3_tid_q : std_ulogic_vector(0 to 1); -- input=>ex2_tid_q , act=>exx_act(2) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex3_is_mtmsr_q : std_ulogic; -- input=>ex2_is_mtmsr_q , act=>exx_act(2) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex3_is_mtspr_q : std_ulogic; -- input=>ex2_is_mtspr_q , act=>exx_act(2) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex3_wait_wc_q : std_ulogic_vector(9 to 10); -- input=>ex2_wait_wc_q , act=>exx_act_data(2), scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex3_is_msgclr_q : std_ulogic; -- input=>ex2_is_msgclr_q , act=>exx_act(2) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex3_instr_q, ex3_instr_d : std_ulogic_vector(11 to 20); -- input=>ex3_instr_d , act=>exx_act(2) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex3_cspr_rt_q, ex2_cspr_rt : std_ulogic_vector(64-regsize to 63); -- input=>ex2_cspr_rt , act=>exx_act_data(2), scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex3_hypv_spr_q, ex3_hypv_spr_d : std_ulogic; -- input=>ex3_hypv_spr_d , act=>exx_act(2) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex3_illeg_spr_q, ex3_illeg_spr_d : std_ulogic; -- input=>ex3_illeg_spr_d , act=>exx_act(2) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex3_priv_spr_q, ex3_priv_spr_d : std_ulogic; -- input=>ex3_priv_spr_d , act=>exx_act(2) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex3_sspr_val_q, ex2_sspr_val : std_ulogic; -- input=>ex2_sspr_val , act=>exx_act(2) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex3_rt_q : std_ulogic_vector(64-regsize to 63); -- input=>mux_spr_ex2_rt , act=>exx_act_data(2), scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex3_is_mfspr_q : std_ulogic; -- input=>ex2_is_mfspr_q , act=>exx_act(2) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex3_wait_q, ex2_wait : std_ulogic; -- input=>ex2_wait , act=>exx_act(2) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex3_corr_rdata_q, ex2_corr_rdata : std_ulogic_vector(64-regsize to 63); -- input=>ex2_corr_rdata , act=>exx_act_data(2), scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex3_sprg_ce_q, ex2_sprg_ce : std_ulogic; -- input=>ex2_sprg_ce , act=>exx_act(2) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex3_sprg_ue_q, ex2_sprg_ue : std_ulogic; -- input=>ex2_sprg_ue , act=>exx_act(2) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex3_aspr_ce_addr_q : std_ulogic_vector(0 to 3); -- input=>ex2_aspr_ce_addr_q , act=>exx_act(2) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex3_dcr_read_q : std_ulogic; -- input=>ex2_dcr_read_q , act=>exx_act(2) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex3_aspr_re_q : std_ulogic_vector(2-regsize/32 to 1); -- input=>ex2_aspr_re_q , act=>exx_act(2) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex3_dcr_val_q : std_ulogic; -- input=>ex2_dcr_val_q , act=>exx_act(2) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex3_dcr_user_q : std_ulogic; -- input=>ex2_dcr_user_q , act=>exx_act(2) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex3_is_wrtee_q : std_ulogic; -- input=>ex2_is_wrtee_q , act=>exx_act(2) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex3_is_wrteei_q : std_ulogic; -- input=>ex2_is_wrteei_q , act=>exx_act(2) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex3_msr_gs_q, ex3_msr_gs_d : std_ulogic; -- input=>ex3_msr_gs_d , act=>tiup , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex4_tid_q : std_ulogic_vector(0 to 1); -- input=>ex3_tid_q , act=>exx_act(3) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex4_is_mtmsr_q : std_ulogic; -- input=>ex3_is_mtmsr_q , act=>exx_act(3) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex4_is_mtspr_q : std_ulogic; -- input=>ex3_is_mtspr_q , act=>exx_act(3) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex4_wait_wc_q : std_ulogic_vector(9 to 10); -- input=>ex3_wait_wc_q , act=>exx_act(3) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex4_is_msgclr_q : std_ulogic; -- input=>ex3_is_msgclr_q , act=>exx_act(3) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex4_instr_q : std_ulogic_vector(11 to 20); -- input=>ex3_instr_q , act=>exx_act(3) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex4_sspr_val_q : std_ulogic; -- input=>ex3_sspr_val_q , act=>exx_act(3) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex4_rt_q : std_ulogic_vector(64-regsize to 63); -- input=>ex3_rt_q , act=>exx_act_data(3), scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex4_is_mfspr_q : std_ulogic; -- input=>ex3_is_mfspr_q , act=>exx_act(3) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex4_dcr_read_q : std_ulogic; -- input=>ex3_dcr_read_q , act=>exx_act(3) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex4_wait_q : std_ulogic; -- input=>ex3_wait_q , act=>exx_act(3) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex4_corr_rdata_q : std_ulogic_vector(64-regsize to 63); -- input=>ex3_corr_rdata_q , act=>exx_act_data(3), scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex4_sprg_ce_q, ex4_sprg_ce_d : std_ulogic_vector(0 to regsize/8); -- input=>ex4_sprg_ce_d , act=>exx_act_data(3), scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex4_aspr_ce_addr_q : std_ulogic_vector(0 to 3); -- input=>ex3_aspr_ce_addr_q , act=>ex3_sprg_ce , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex4_dcr_val_q : std_ulogic; -- input=>ex3_dcr_val_q , act=>exx_act(3) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex4_dcr_user_q : std_ulogic; -- input=>ex3_dcr_user_q , act=>exx_act(3) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex4_is_wrtee_q : std_ulogic; -- input=>ex3_is_wrtee_q , act=>exx_act(3) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex4_is_wrteei_q : std_ulogic; -- input=>ex3_is_wrteei_q , act=>exx_act(3) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex4_aspr_we_q, ex3_aspr_we : std_ulogic; -- input=>ex3_aspr_we , act=>tiup , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex4_aspr_addr_q, ex3_aspr_addr : std_ulogic_vector(0 to 3); -- input=>ex3_aspr_addr , act=>exx_act(3) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex5_val_q, ex5_val_d : std_ulogic_vector(0 to threads-1); -- input=>ex5_val_d , act=>tiup , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 +signal ex5_tid_q : std_ulogic_vector(0 to 1); -- input=>ex4_tid_q , act=>exx_act(4) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex5_is_mtmsr_q : std_ulogic; -- input=>ex4_is_mtmsr_q , act=>exx_act(4) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex5_is_mtspr_q : std_ulogic; -- input=>ex4_is_mtspr_q , act=>exx_act(4) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex5_wait_wc_q : std_ulogic_vector(9 to 10); -- input=>ex4_wait_wc_q , act=>exx_act_data(4), scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex5_is_msgclr_q : std_ulogic; -- input=>ex4_is_msgclr_q , act=>exx_act(4) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex5_instr_q : std_ulogic_vector(11 to 20); -- input=>ex4_instr_q , act=>exx_act(4) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex5_sspr_val_q : std_ulogic; -- input=>ex4_sspr_val_q , act=>exx_act(4) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex5_aspr_we_q, ex5_aspr_we_d : std_ulogic_vector(0 to threads-1); -- input=>ex5_aspr_we_d , act=>tiup , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex5_rt_q, ex5_rt_d : std_ulogic_vector(64-regsize to 64+8-(64/regsize));-- input=>ex5_rt_d , act=>exx_act_data(4), scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex5_rt_q_b : std_ulogic_vector(64-regsize to 64+8-(64/regsize)); +signal ex5_wait_q : std_ulogic; -- input=>ex4_wait_q , act=>exx_act(4) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex5_sprg_ce_q : std_ulogic; -- input=>ex4_sprg_ce_q(0) , act=>exx_act(4) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex5_dcr_val_q, ex4_dcr_val : std_ulogic; -- input=>ex4_dcr_val , act=>exx_act(4) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex5_dcr_read_q : std_ulogic; -- input=>ex4_dcr_read_q , act=>exx_act(4) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex5_dcr_user_q : std_ulogic; -- input=>ex4_dcr_user_q , act=>exx_act(4) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex5_aspr_addr_q, ex5_aspr_addr_d : std_ulogic_vector(0 to 3); -- input=>ex5_aspr_addr_d , act=>exx_act(4) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex5_is_wrtee_q : std_ulogic; -- input=>ex4_is_wrtee_q , act=>exx_act(4) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex5_is_wrteei_q : std_ulogic; -- input=>ex4_is_wrteei_q , act=>exx_act(4) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex6_valid_q, ex5_valid : std_ulogic_vector(0 to threads-1); -- input=>ex5_valid , act=>tiup , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 +signal ex6_val_q, ex5_val : std_ulogic; -- input=>ex5_val , act=>tiup , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 +signal ex6_tid_q : std_ulogic_vector(0 to 1); -- input=>ex5_tid_q , act=>exx_act(5) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex6_dbell_taken_q : std_ulogic_vector(0 to threads-1); -- input=>cpl_spr_ex5_dbell_taken , act=>tiup , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex6_cdbell_taken_q : std_ulogic_vector(0 to threads-1); -- input=>cpl_spr_ex5_cdbell_taken , act=>tiup , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex6_gdbell_taken_q : std_ulogic_vector(0 to threads-1); -- input=>cpl_spr_ex5_gdbell_taken , act=>tiup , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex6_gcdbell_taken_q : std_ulogic_vector(0 to threads-1); -- input=>cpl_spr_ex5_gcdbell_taken , act=>tiup , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex6_gmcdbell_taken_q : std_ulogic_vector(0 to threads-1); -- input=>cpl_spr_ex5_gmcdbell_taken , act=>tiup , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex6_rt_q : std_ulogic_vector(64-regsize to 63); -- input=>ex5_rt_q(64-regsize to 63) , act=>exx_act_data(5), scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex6_instr_q : std_ulogic_vector(11 to 20); -- input=>ex5_instr_q , act=>exx_act(5) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex6_is_mtspr_q : std_ulogic; -- input=>ex5_is_mtspr_q , act=>exx_act(5) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex6_wait_wc_q : std_ulogic_vector(9 to 10); -- input=>ex5_wait_wc_q , act=>exx_act_data(5), scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex6_is_msgclr_q : std_ulogic; -- input=>ex5_is_msgclr_q , act=>exx_act(5) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex6_sspr_val_q : std_ulogic; -- input=>ex5_sspr_val_q , act=>exx_act(5) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex6_set_xucr0_cslc_q, ex6_set_xucr0_cslc_d : std_ulogic; -- input=>ex6_set_xucr0_cslc_d , act=>tiup , scan=>N, sleep=>Y, ring=>func, needs_sreset=>0 +signal ex6_set_xucr0_cul_q, ex6_set_xucr0_cul_d : std_ulogic; -- input=>ex6_set_xucr0_cul_d , act=>tiup , scan=>N, sleep=>Y, ring=>func, needs_sreset=>0 +signal ex6_set_xucr0_clo_q, ex6_set_xucr0_clo_d : std_ulogic; -- input=>ex6_set_xucr0_clo_d , act=>tiup , scan=>N, sleep=>Y, ring=>func, needs_sreset=>0 +signal ex6_wait_q : std_ulogic; -- input=>ex5_wait_q , act=>exx_act(5) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex6_sprg_ce_q, ex5_sprg_ce : std_ulogic_vector(0 to threads-1); -- input=>ex5_sprg_ce , act=>exx_act(5) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex6_dcr_val_q, ex5_dcr_val : std_ulogic; -- input=>ex5_dcr_val , act=>exx_act(5) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex6_dcr_read_q : std_ulogic; -- input=>ex5_dcr_read_q , act=>exx_act(5) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex6_dcr_user_q : std_ulogic; -- input=>ex5_dcr_user_q , act=>exx_act(5) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex2_any_mfspr_q, ex2_any_mfspr_d : std_ulogic; -- input=>ex2_any_mfspr_d , act=>exx_act(1) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex2_any_mtspr_q, ex2_any_mtspr_d : std_ulogic; -- input=>ex2_any_mtspr_d , act=>exx_act(1) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex3_any_mfspr_q : std_ulogic; -- input=>ex2_any_mfspr_q , act=>exx_act(2) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex3_any_mtspr_q : std_ulogic; -- input=>ex2_any_mtspr_q , act=>exx_act(2) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex4_any_mfspr_q : std_ulogic; -- input=>ex3_any_mfspr_q , act=>exx_act(3) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex4_any_mtspr_q : std_ulogic; -- input=>ex3_any_mtspr_q , act=>exx_act(3) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex5_any_mfspr_q : std_ulogic; -- input=>ex4_any_mfspr_q , act=>exx_act(4) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex5_any_mtspr_q : std_ulogic; -- input=>ex4_any_mtspr_q , act=>exx_act(4) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal running_q, running_d : std_ulogic_vector(0 to threads-1); -- input=>running_d , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal llpri_q, llpri_d : std_ulogic_vector(0 to threads-1); -- input=>llpri_d , act=>llpri_inc , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1, init=>8 +signal dec_dbg_dis_q, dec_dbg_dis_d : std_ulogic_vector(0 to threads-1); -- input=>dec_dbg_dis_d , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal tb_dbg_dis_q, tb_dbg_dis_d : std_ulogic; -- input=>tb_dbg_dis_d , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal tb_act_q, tb_act_d : std_ulogic; -- input=>tb_act_d , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal ext_dbg_dis_q, ext_dbg_dis_d : std_ulogic_vector(0 to threads-1); -- input=>ext_dbg_dis_d , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal ram_mode_q : std_ulogic; -- input=>pc_xu_ram_mode , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal ram_thread_q : std_ulogic_vector(0 to 1); -- input=>pc_xu_ram_thread , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal msrovride_enab_q : std_ulogic; -- input=>pc_xu_msrovride_enab , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal waitimpl_val_q, waitimpl_val_d : std_ulogic_vector(0 to threads-1); -- input=>waitimpl_val_d , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal waitrsv_val_q, waitrsv_val_d : std_ulogic_vector(0 to threads-1); -- input=>waitrsv_val_d , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal an_ac_reservation_vld_q : std_ulogic_vector(0 to threads-1); -- input=>an_ac_reservation_vld , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal an_ac_sleep_en_q : std_ulogic_vector(0 to threads-1); -- input=>an_ac_sleep_en , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal an_ac_coreid_q : std_ulogic_vector(54 to 61); -- input=>an_ac_coreid , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal tb_update_enable_q : std_ulogic; -- input=>an_ac_tb_update_enable , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal tb_update_pulse_q : std_ulogic; -- input=>an_ac_tb_update_pulse , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal tb_update_pulse_1_q : std_ulogic; -- input=>tb_update_pulse_q , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal pc_xu_reset_wd_complete_q : std_ulogic; -- input=>pc_xu_reset_wd_complete , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal pc_xu_reset_3_complete_q : std_ulogic; -- input=>pc_xu_reset_3_complete , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal pc_xu_reset_2_complete_q : std_ulogic; -- input=>pc_xu_reset_2_complete , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal pc_xu_reset_1_complete_q : std_ulogic; -- input=>pc_xu_reset_1_complete , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal lsu_xu_dbell_val_q : std_ulogic; -- input=>lsu_xu_dbell_val , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal lsu_xu_dbell_type_q : std_ulogic_vector(0 to 4); -- input=>lsu_xu_dbell_type , act=>dbell_act , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal lsu_xu_dbell_brdcast_q : std_ulogic; -- input=>lsu_xu_dbell_brdcast , act=>dbell_act , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal lsu_xu_dbell_lpid_match_q : std_ulogic; -- input=>lsu_xu_dbell_lpid_match , act=>dbell_act , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal lsu_xu_dbell_pirtag_q : std_ulogic_vector(50 to 63); -- input=>lsu_xu_dbell_pirtag , act=>dbell_act , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal dbell_present_q, dbell_present_d : std_ulogic_vector(0 to threads-1); -- input=>dbell_present_d , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal cdbell_present_q, cdbell_present_d : std_ulogic_vector(0 to threads-1); -- input=>cdbell_present_d , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal gdbell_present_q, gdbell_present_d : std_ulogic_vector(0 to threads-1); -- input=>gdbell_present_d , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal gcdbell_present_q, gcdbell_present_d : std_ulogic_vector(0 to threads-1); -- input=>gcdbell_present_d , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal gmcdbell_present_q, gmcdbell_present_d : std_ulogic_vector(0 to threads-1); -- input=>gmcdbell_present_d , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal xucr0_clfc_q, xucr0_clfc_d : std_ulogic; -- input=>xucr0_clfc_d , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal iu_run_thread_q, iu_run_thread_d : std_ulogic_vector(0 to threads-1); -- input=>iu_run_thread_d , act=>tiup , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 +signal perf_event_q, perf_event_d : std_ulogic_vector(0 to 3*threads-1); -- input=>perf_event_d , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal inj_sprg_ecc_q : std_ulogic_vector(0 to threads-1); -- input=>pc_xu_inj_sprg_ecc , act=>tiup , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 +signal dbell_interrupt_q, dbell_interrupt : std_ulogic_vector(0 to threads-1); -- input=>dbell_interrupt , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal cdbell_interrupt_q, cdbell_interrupt : std_ulogic_vector(0 to threads-1); -- input=>cdbell_interrupt , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal gdbell_interrupt_q, gdbell_interrupt : std_ulogic_vector(0 to threads-1); -- input=>gdbell_interrupt , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal gcdbell_interrupt_q, gcdbell_interrupt : std_ulogic_vector(0 to threads-1); -- input=>gcdbell_interrupt , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal gmcdbell_interrupt_q, gmcdbell_interrupt : std_ulogic_vector(0 to threads-1); -- input=>gmcdbell_interrupt , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal iu_quiesce_q : std_ulogic_vector(0 to threads-1); -- input=>iu_xu_quiesce , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal lsu_quiesce_q : std_ulogic_vector(0 to threads-1); -- input=>lsu_xu_quiesce , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal mm_quiesce_q : std_ulogic_vector(0 to threads-1); -- input=>mm_xu_quiesce , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal bx_quiesce_q : std_ulogic_vector(0 to threads-1); -- input=>bx_xu_quiesce , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal quiesce_q, quiesce_d : std_ulogic_vector(0 to threads-1); -- input=>quiesce_d , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal cpl_quiesce_q, cpl_quiesce_d : std_ulogic_vector(0 to threads-1); -- input=>cpl_quiesce_d , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal quiesced_4cpl_q, quiesced_4cpl_d : std_ulogic_vector(0 to threads-1); -- input=>quiesced_4cpl_d , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal quiesced_q, quiesced_d : std_ulogic_vector(0 to threads-1); -- input=>quiesced_d , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal instr_trace_mode_q : std_ulogic; -- input=>pc_xu_instr_trace_mode , act=>tiup , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 +signal instr_trace_tid_q : std_ulogic_vector(0 to 1); -- input=>pc_xu_instr_trace_tid , act=>tiup , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 +signal timer_update_q : std_ulogic; -- input=>timer_update_int , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal spare_0_q, spare_0_d : std_ulogic_vector(0 to 15); -- input=>spare_0_d, act=>tiup, +-- Scanchains +constant exx_act_offset : integer := last_reg_offset; +constant rf1_instr_offset : integer := exx_act_offset + exx_act_q'length; +constant rf1_aspr_act_offset : integer := rf1_instr_offset + rf1_instr_q'length; +constant rf1_aspr_tid_offset : integer := rf1_aspr_act_offset + 1; +constant rf1_msr_gs_offset : integer := rf1_aspr_tid_offset + rf1_aspr_tid_q'length; +constant ex1_tid_offset : integer := rf1_msr_gs_offset + 1; +constant ex1_is_mfspr_offset : integer := ex1_tid_offset + ex1_tid_q'length; +constant ex1_is_mtspr_offset : integer := ex1_is_mfspr_offset + 1; +constant ex1_instr_offset : integer := ex1_is_mtspr_offset + 1; +constant ex1_aspr_re_offset : integer := ex1_instr_offset + ex1_instr_q'length; +constant ex1_aspr_ce_addr_offset : integer := ex1_aspr_re_offset + ex1_aspr_re_q'length; +constant ex2_aspr_rdata_offset : integer := ex1_aspr_ce_addr_offset + ex1_aspr_ce_addr_q'length; +constant ex3_tid_offset : integer := ex2_aspr_rdata_offset + ex2_aspr_rdata_q'length; +constant ex3_is_mtmsr_offset : integer := ex3_tid_offset + ex3_tid_q'length; +constant ex3_is_mtspr_offset : integer := ex3_is_mtmsr_offset + 1; +constant ex3_wait_wc_offset : integer := ex3_is_mtspr_offset + 1; +constant ex3_is_msgclr_offset : integer := ex3_wait_wc_offset + ex3_wait_wc_q'length; +constant ex3_instr_offset : integer := ex3_is_msgclr_offset + 1; +constant ex3_cspr_rt_offset : integer := ex3_instr_offset + ex3_instr_q'length; +constant ex3_hypv_spr_offset : integer := ex3_cspr_rt_offset + ex3_cspr_rt_q'length; +constant ex3_illeg_spr_offset : integer := ex3_hypv_spr_offset + 1; +constant ex3_priv_spr_offset : integer := ex3_illeg_spr_offset + 1; +constant ex3_sspr_val_offset : integer := ex3_priv_spr_offset + 1; +constant ex3_rt_offset : integer := ex3_sspr_val_offset + 1; +constant ex3_is_mfspr_offset : integer := ex3_rt_offset + ex3_rt_q'length; +constant ex3_wait_offset : integer := ex3_is_mfspr_offset + 1; +constant ex3_corr_rdata_offset : integer := ex3_wait_offset + 1; +constant ex3_sprg_ce_offset : integer := ex3_corr_rdata_offset + ex3_corr_rdata_q'length; +constant ex3_sprg_ue_offset : integer := ex3_sprg_ce_offset + 1; +constant ex3_aspr_ce_addr_offset : integer := ex3_sprg_ue_offset + 1; +constant ex3_dcr_read_offset : integer := ex3_aspr_ce_addr_offset + ex3_aspr_ce_addr_q'length; +constant ex3_aspr_re_offset : integer := ex3_dcr_read_offset + 1; +constant ex3_dcr_val_offset : integer := ex3_aspr_re_offset + ex3_aspr_re_q'length; +constant ex3_dcr_user_offset : integer := ex3_dcr_val_offset + 1; +constant ex3_is_wrtee_offset : integer := ex3_dcr_user_offset + 1; +constant ex3_is_wrteei_offset : integer := ex3_is_wrtee_offset + 1; +constant ex3_msr_gs_offset : integer := ex3_is_wrteei_offset + 1; +constant ex4_aspr_we_offset : integer := ex3_msr_gs_offset + 1; +constant ex4_aspr_addr_offset : integer := ex4_aspr_we_offset + 1; +constant ex5_val_offset : integer := ex4_aspr_addr_offset + ex4_aspr_addr_q'length; +constant ex5_tid_offset : integer := ex5_val_offset + ex5_val_q'length; +constant ex5_is_mtmsr_offset : integer := ex5_tid_offset + ex5_tid_q'length; +constant ex5_is_mtspr_offset : integer := ex5_is_mtmsr_offset + 1; +constant ex5_wait_wc_offset : integer := ex5_is_mtspr_offset + 1; +constant ex5_is_msgclr_offset : integer := ex5_wait_wc_offset + ex5_wait_wc_q'length; +constant ex5_instr_offset : integer := ex5_is_msgclr_offset + 1; +constant ex5_sspr_val_offset : integer := ex5_instr_offset + ex5_instr_q'length; +constant ex5_aspr_we_offset : integer := ex5_sspr_val_offset + 1; +constant ex5_rt_offset : integer := ex5_aspr_we_offset + ex5_aspr_we_q'length; +constant ex5_wait_offset : integer := ex5_rt_offset + ex5_rt_q'length; +constant ex5_sprg_ce_offset : integer := ex5_wait_offset + 1; +constant ex5_dcr_val_offset : integer := ex5_sprg_ce_offset + 1; +constant ex5_dcr_read_offset : integer := ex5_dcr_val_offset + 1; +constant ex5_dcr_user_offset : integer := ex5_dcr_read_offset + 1; +constant ex5_aspr_addr_offset : integer := ex5_dcr_user_offset + 1; +constant ex5_is_wrtee_offset : integer := ex5_aspr_addr_offset + ex5_aspr_addr_q'length; +constant ex5_is_wrteei_offset : integer := ex5_is_wrtee_offset + 1; +constant ex3_any_mfspr_offset : integer := ex5_is_wrteei_offset + 1; +constant ex3_any_mtspr_offset : integer := ex3_any_mfspr_offset + 1; +constant ex5_any_mfspr_offset : integer := ex3_any_mtspr_offset + 1; +constant ex5_any_mtspr_offset : integer := ex5_any_mfspr_offset + 1; +constant ex6_valid_offset : integer := ex5_any_mtspr_offset + 1; +constant ex6_val_offset : integer := ex6_valid_offset + ex6_valid_q'length; +constant running_offset : integer := ex6_val_offset + 1; +constant llpri_offset : integer := running_offset + running_q'length; +constant dec_dbg_dis_offset : integer := llpri_offset + llpri_q'length; +constant tb_dbg_dis_offset : integer := dec_dbg_dis_offset + dec_dbg_dis_q'length; +constant tb_act_offset : integer := tb_dbg_dis_offset + 1; +constant ext_dbg_dis_offset : integer := tb_act_offset + 1; +constant ram_mode_offset : integer := ext_dbg_dis_offset + ext_dbg_dis_q'length; +constant ram_thread_offset : integer := ram_mode_offset + 1; +constant msrovride_enab_offset : integer := ram_thread_offset + ram_thread_q'length; +constant waitimpl_val_offset : integer := msrovride_enab_offset + 1; +constant waitrsv_val_offset : integer := waitimpl_val_offset + waitimpl_val_q'length; +constant an_ac_reservation_vld_offset : integer := waitrsv_val_offset + waitrsv_val_q'length; +constant an_ac_sleep_en_offset : integer := an_ac_reservation_vld_offset + an_ac_reservation_vld_q'length; +constant an_ac_coreid_offset : integer := an_ac_sleep_en_offset + an_ac_sleep_en_q'length; +constant tb_update_enable_offset : integer := an_ac_coreid_offset + an_ac_coreid_q'length; +constant tb_update_pulse_offset : integer := tb_update_enable_offset + 1; +constant tb_update_pulse_1_offset : integer := tb_update_pulse_offset + 1; +constant pc_xu_reset_wd_complete_offset : integer := tb_update_pulse_1_offset + 1; +constant pc_xu_reset_3_complete_offset : integer := pc_xu_reset_wd_complete_offset + 1; +constant pc_xu_reset_2_complete_offset : integer := pc_xu_reset_3_complete_offset + 1; +constant pc_xu_reset_1_complete_offset : integer := pc_xu_reset_2_complete_offset + 1; +constant lsu_xu_dbell_val_offset : integer := pc_xu_reset_1_complete_offset + 1; +constant lsu_xu_dbell_type_offset : integer := lsu_xu_dbell_val_offset + 1; +constant lsu_xu_dbell_brdcast_offset : integer := lsu_xu_dbell_type_offset + lsu_xu_dbell_type_q'length; +constant lsu_xu_dbell_lpid_match_offset : integer := lsu_xu_dbell_brdcast_offset + 1; +constant lsu_xu_dbell_pirtag_offset : integer := lsu_xu_dbell_lpid_match_offset + 1; +constant dbell_present_offset : integer := lsu_xu_dbell_pirtag_offset + lsu_xu_dbell_pirtag_q'length; +constant cdbell_present_offset : integer := dbell_present_offset + dbell_present_q'length; +constant gdbell_present_offset : integer := cdbell_present_offset + cdbell_present_q'length; +constant gcdbell_present_offset : integer := gdbell_present_offset + gdbell_present_q'length; +constant gmcdbell_present_offset : integer := gcdbell_present_offset + gcdbell_present_q'length; +constant xucr0_clfc_offset : integer := gmcdbell_present_offset + gmcdbell_present_q'length; +constant iu_run_thread_offset : integer := xucr0_clfc_offset + 1; +constant perf_event_offset : integer := iu_run_thread_offset + iu_run_thread_q'length; +constant inj_sprg_ecc_offset : integer := perf_event_offset + perf_event_q'length; +constant dbell_interrupt_offset : integer := inj_sprg_ecc_offset + inj_sprg_ecc_q'length; +constant cdbell_interrupt_offset : integer := dbell_interrupt_offset + dbell_interrupt_q'length; +constant gdbell_interrupt_offset : integer := cdbell_interrupt_offset + cdbell_interrupt_q'length; +constant gcdbell_interrupt_offset : integer := gdbell_interrupt_offset + gdbell_interrupt_q'length; +constant gmcdbell_interrupt_offset : integer := gcdbell_interrupt_offset + gcdbell_interrupt_q'length; +constant iu_quiesce_offset : integer := gmcdbell_interrupt_offset + gmcdbell_interrupt_q'length; +constant lsu_quiesce_offset : integer := iu_quiesce_offset + iu_quiesce_q'length; +constant mm_quiesce_offset : integer := lsu_quiesce_offset + lsu_quiesce_q'length; +constant bx_quiesce_offset : integer := mm_quiesce_offset + mm_quiesce_q'length; +constant quiesce_offset : integer := bx_quiesce_offset + bx_quiesce_q'length; +constant cpl_quiesce_offset : integer := quiesce_offset + quiesce_q'length; +constant quiesced_4cpl_offset : integer := cpl_quiesce_offset + cpl_quiesce_q'length; +constant quiesced_offset : integer := quiesced_4cpl_offset + quiesced_4cpl_q'length; +constant instr_trace_mode_offset : integer := quiesced_offset + quiesced_q'length; +constant instr_trace_tid_offset : integer := instr_trace_mode_offset + 1; +constant timer_update_offset : integer := instr_trace_tid_offset + instr_trace_tid_q'length; +constant spare_0_offset : integer := timer_update_offset + 1; +constant quiesced_ctr_offset : integer := spare_0_offset + spare_0_q'length; +constant quiesced_4cpl_ctr_offset : integer := quiesced_ctr_offset + 1; +constant scan_right : integer := quiesced_4cpl_ctr_offset + 1; +signal siv : std_ulogic_vector(0 to scan_right-1); +signal sov : std_ulogic_vector(0 to scan_right-1); +constant scan_right_bcfg : integer := last_reg_offset_bcfg; +signal siv_bcfg : std_ulogic_vector(0 to scan_right_bcfg-1); +signal sov_bcfg : std_ulogic_vector(0 to scan_right_bcfg-1); +constant scan_right_ccfg : integer := last_reg_offset_ccfg; +signal siv_ccfg : std_ulogic_vector(0 to scan_right_ccfg-1); +signal sov_ccfg : std_ulogic_vector(0 to scan_right_ccfg-1); +-- Signals +signal tiup : std_ulogic; +signal tidn : std_ulogic_vector(00 to 61); +signal spare_0_lclk : clk_logic; +signal spare_0_d1clk, spare_0_d2clk : std_ulogic; +signal tb : std_ulogic_vector(00 to 63); +signal rf1_opcode_is_31, ex1_opcode_is_31 : boolean; +signal rf1_instr : std_ulogic_vector(11 to 20); +signal ex1_tid : std_ulogic_vector(0 to threads-1); +signal ex1_is_mtdcr, ex1_is_mtdcrux, ex1_is_mtdcrx : std_ulogic; +signal ex1_is_mfdcr, ex1_is_mfdcrux, ex1_is_mfdcrx : std_ulogic; +signal ex1_is_mfcr, ex1_is_mtcrf : std_ulogic; +signal ex1_dcr_instr : std_ulogic; +signal ex2_tid : std_ulogic_vector(0 to threads-1); +signal ex2_illeg_mfspr : std_ulogic; +signal ex2_illeg_mtspr : std_ulogic; +signal ex2_illeg_mftb : std_ulogic; +signal ex2_hypv_mfspr : std_ulogic; +signal ex2_hypv_mtspr : std_ulogic; +signal ex2_instr : std_ulogic_vector(11 to 20); +signal ex2_slowspr_range_priv : std_ulogic; +signal ex2_slowspr_range_hypv : std_ulogic; +signal ex2_slowspr_range : std_ulogic; +signal ex2_wait_flush : std_ulogic_vector(0 to threads-1); +signal ex2_ccr0_flush : std_ulogic_vector(0 to threads-1); +signal ex2_tenc_flush : std_ulogic_vector(0 to threads-1); +signal ex3_tspr_rt : std_ulogic_vector(64-regsize to 63); +signal ex4_rt, ex4_rt_inj : std_ulogic_vector(64-regsize to 63); +signal ex4_tid : std_ulogic_vector(0 to threads-1); +signal ex5_tid : std_ulogic_vector(0 to threads-1); +signal ex3_instr : std_ulogic_vector(11 to 20); +signal llunmasked,llmasked : std_ulogic; +signal llpulse,llpres,llpri_inc : std_ulogic; +signal llmask : std_ulogic_vector(0 to threads-1); +signal ram_tid : std_ulogic_vector(0 to threads-1); +signal pm_wake_up : std_ulogic_vector(0 to threads-1); +signal ccr0_di, ccr0_wen : std_ulogic_vector(ccr0_q'range); +signal dbell_pir_match : std_ulogic; +signal dbell_pir_thread : std_ulogic_vector(0 to threads-1); +signal spr_ccr0_we_rev, spr_tens_ten_rev : std_ulogic_vector(0 to threads-1); +signal set_dbell, clr_dbell : std_ulogic_vector(0 to threads-1); +signal set_cdbell, clr_cdbell : std_ulogic_vector(0 to threads-1); +signal set_gdbell, clr_gdbell : std_ulogic_vector(0 to threads-1); +signal set_gcdbell, clr_gcdbell : std_ulogic_vector(0 to threads-1); +signal set_gmcdbell, clr_gmcdbell : std_ulogic_vector(0 to threads-1); +signal tb_update_pulse : std_ulogic; +signal spr_tensr : std_ulogic_vector(0 to threads-1); +signal ex6_instr : std_ulogic_vector(11 to 20); +signal ex6_is_mtspr : std_ulogic; +signal ex6_val : std_ulogic; +signal ex6_tid : std_ulogic_vector(0 to threads-1); +signal tb_q : std_ulogic_vector(0 to 63); +signal crit_mask, base_mask, dec_mask, fit_mask : std_ulogic_vector(0 to threads-1); +signal ex6_wait : std_ulogic_vector(0 to threads-1); +signal ex6_any_valid : std_ulogic; +signal ex5_flush : std_ulogic; +signal xucr0_di : std_ulogic_vector(xucr0_q'range); +signal ex4_eccgen_data : std_ulogic_vector(64-regsize to 72-(64/regsize)); +signal ex4_eccgen_syn : std_ulogic_vector(64 to 72-(64/regsize)); +signal ex2_eccchk_syn, ex2_eccchk_syn_b : std_ulogic_vector(64 to 72-(64/regsize)); +signal ram_mode : std_ulogic_vector(0 to threads-1); +signal ex4_is_mfsspr_b : std_ulogic; +signal encorr : std_ulogic; +signal ex3_sprg_ce : std_ulogic; +signal ex3_aspr_rt : std_ulogic_vector(64-regsize to 63); +signal ex6_spr_wd : std_ulogic_vector(64-regsize to 63); +signal quiesce_ctr_zero_b, cpl_quiesce_ctr_zero_b : std_ulogic_vector(0 to threads-1); +signal quiesce_b_q, cpl_quiesce_b_q : std_ulogic_vector(0 to threads-1); +signal running : std_ulogic_vector(0 to threads-1); +signal timer_update_int : std_ulogic; +signal exx_act : std_ulogic_vector(0 to 5); +signal exx_act_data : std_ulogic_vector(1 to 5); +signal rf0_act : std_ulogic; +signal ex4_inj_ecc : std_ulogic; +signal version : std_ulogic_vector(32 to 47); +signal revision : std_ulogic_vector(48 to 63); +signal revision_minor : std_ulogic_vector(0 to 3); +signal instr_trace_tid : std_ulogic_vector(0 to threads-1); +signal ex3_sprg_ue : std_ulogic; +signal dbell_act : std_ulogic; + +-- Data +signal spr_ccr0_we : std_ulogic_vector(0 to 3); +signal spr_ccr2_en_dcr_int : std_ulogic; +signal spr_ccr2_en_trace : std_ulogic; +signal spr_tens_ten : std_ulogic_vector(0 to 3); +signal spr_xucr0_clkg_ctl : std_ulogic_vector(0 to 4); +signal spr_xucr0_trace_um : std_ulogic_vector(0 to 3); +signal spr_xucr0_tcs : std_ulogic; +signal ex6_ccr0_di : std_ulogic_vector(ccr0_q'range); +signal ex6_ccr1_di : std_ulogic_vector(ccr1_q'range); +signal ex6_ccr2_di : std_ulogic_vector(ccr2_q'range); +signal ex6_tbl_di : std_ulogic_vector(tbl_q'range); +signal ex6_tbu_di : std_ulogic_vector(tbu_q'range); +signal ex6_tens_di : std_ulogic_vector(tens_q'range); +signal ex6_xucr0_di : std_ulogic_vector(xucr0_q'range); +signal + rf1_gsprg0_re , rf1_gsprg1_re , rf1_gsprg2_re , rf1_gsprg3_re + , rf1_sprg0_re , rf1_sprg1_re , rf1_sprg2_re , rf1_sprg3_re + , rf1_sprg4_re , rf1_sprg5_re , rf1_sprg6_re , rf1_sprg7_re + , rf1_sprg8_re , rf1_vrsave_re + : std_ulogic; +signal + rf1_gsprg0_rdec, rf1_gsprg1_rdec, rf1_gsprg2_rdec, rf1_gsprg3_rdec + , rf1_sprg0_rdec , rf1_sprg1_rdec , rf1_sprg2_rdec , rf1_sprg3_rdec + , rf1_sprg4_rdec , rf1_sprg5_rdec , rf1_sprg6_rdec , rf1_sprg7_rdec + , rf1_sprg8_rdec , rf1_vrsave_rdec + : std_ulogic; +signal + ex2_ccr0_re , ex2_ccr1_re , ex2_ccr2_re , ex2_dac1_re + , ex2_dac2_re , ex2_dac3_re , ex2_dac4_re , ex2_givpr_re + , ex2_iac1_re , ex2_iac2_re , ex2_iac3_re , ex2_iac4_re + , ex2_ivpr_re , ex2_pir_re , ex2_pvr_re , ex2_tb_re + , ex2_tbu_re , ex2_tenc_re , ex2_tens_re , ex2_tensr_re + , ex2_tir_re , ex2_xucr0_re , ex2_xucr3_re , ex2_xucr4_re + : std_ulogic; +signal + ex2_dvc1_re , ex2_dvc2_re , ex2_eplc_re , ex2_epsc_re + , ex2_eptcfg_re , ex2_immr_re , ex2_imr_re , ex2_iucr0_re + , ex2_iucr1_re , ex2_iucr2_re , ex2_iudbg0_re , ex2_iudbg1_re + , ex2_iudbg2_re , ex2_iulfsr_re , ex2_iullcr_re , ex2_lper_re + , ex2_lperu_re , ex2_lpidr_re , ex2_lratcfg_re , ex2_lratps_re + , ex2_mas0_re , ex2_mas0_mas1_re, ex2_mas1_re , ex2_mas2_re + , ex2_mas2u_re , ex2_mas3_re , ex2_mas4_re , ex2_mas5_re + , ex2_mas5_mas6_re, ex2_mas6_re , ex2_mas7_re , ex2_mas7_mas3_re + , ex2_mas8_re , ex2_mas8_mas1_re, ex2_mmucfg_re , ex2_mmucr0_re + , ex2_mmucr1_re , ex2_mmucr2_re , ex2_mmucr3_re , ex2_mmucsr0_re + , ex2_pid_re , ex2_ppr32_re , ex2_tlb0cfg_re , ex2_tlb0ps_re + , ex2_xucr2_re , ex2_xudbg0_re , ex2_xudbg1_re , ex2_xudbg2_re + : std_ulogic; +signal ex2_sprg8_re, ex2_sprg8_we : std_ulogic; +signal + ex2_ccr0_we , ex2_ccr1_we , ex2_ccr2_we , ex2_dac1_we + , ex2_dac2_we , ex2_dac3_we , ex2_dac4_we , ex2_givpr_we + , ex2_iac1_we , ex2_iac2_we , ex2_iac3_we , ex2_iac4_we + , ex2_ivpr_we , ex2_tbl_we , ex2_tbu_we , ex2_tenc_we + , ex2_tens_we , ex2_trace_we , ex2_xucr0_we , ex2_xucr3_we + , ex2_xucr4_we + : std_ulogic; +signal + ex2_dvc1_we , ex2_dvc2_we , ex2_eplc_we , ex2_epsc_we + , ex2_immr_we , ex2_imr_we , ex2_iucr0_we , ex2_iucr1_we + , ex2_iucr2_we , ex2_iudbg0_we , ex2_iulfsr_we , ex2_iullcr_we + , ex2_lper_we , ex2_lperu_we , ex2_lpidr_we , ex2_mas0_we + , ex2_mas0_mas1_we, ex2_mas1_we , ex2_mas2_we , ex2_mas2u_we + , ex2_mas3_we , ex2_mas4_we , ex2_mas5_we , ex2_mas5_mas6_we + , ex2_mas6_we , ex2_mas7_we , ex2_mas7_mas3_we, ex2_mas8_we + , ex2_mas8_mas1_we, ex2_mmucr0_we , ex2_mmucr1_we , ex2_mmucr2_we + , ex2_mmucr3_we , ex2_mmucsr0_we , ex2_pid_we , ex2_ppr32_we + , ex2_xucr2_we , ex2_xudbg0_we + : std_ulogic; +signal + ex2_ccr0_rdec , ex2_ccr1_rdec , ex2_ccr2_rdec , ex2_dac1_rdec + , ex2_dac2_rdec , ex2_dac3_rdec , ex2_dac4_rdec , ex2_givpr_rdec + , ex2_iac1_rdec , ex2_iac2_rdec , ex2_iac3_rdec , ex2_iac4_rdec + , ex2_ivpr_rdec , ex2_pir_rdec , ex2_pvr_rdec , ex2_tb_rdec + , ex2_tbu_rdec , ex2_tenc_rdec , ex2_tens_rdec , ex2_tensr_rdec + , ex2_tir_rdec , ex2_xucr0_rdec , ex2_xucr3_rdec , ex2_xucr4_rdec + : std_ulogic; +signal + ex2_dvc1_rdec , ex2_dvc2_rdec , ex2_eplc_rdec , ex2_epsc_rdec + , ex2_eptcfg_rdec, ex2_immr_rdec , ex2_imr_rdec , ex2_iucr0_rdec + , ex2_iucr1_rdec , ex2_iucr2_rdec , ex2_iudbg0_rdec, ex2_iudbg1_rdec + , ex2_iudbg2_rdec, ex2_iulfsr_rdec, ex2_iullcr_rdec, ex2_lper_rdec + , ex2_lperu_rdec , ex2_lpidr_rdec , ex2_lratcfg_rdec, ex2_lratps_rdec + , ex2_mas0_rdec , ex2_mas0_mas1_rdec, ex2_mas1_rdec , ex2_mas2_rdec + , ex2_mas2u_rdec , ex2_mas3_rdec , ex2_mas4_rdec , ex2_mas5_rdec + , ex2_mas5_mas6_rdec, ex2_mas6_rdec , ex2_mas7_rdec , ex2_mas7_mas3_rdec + , ex2_mas8_rdec , ex2_mas8_mas1_rdec, ex2_mmucfg_rdec, ex2_mmucr0_rdec + , ex2_mmucr1_rdec, ex2_mmucr2_rdec, ex2_mmucr3_rdec, ex2_mmucsr0_rdec + , ex2_pid_rdec , ex2_ppr32_rdec , ex2_tlb0cfg_rdec, ex2_tlb0ps_rdec + , ex2_xucr2_rdec , ex2_xudbg0_rdec, ex2_xudbg1_rdec, ex2_xudbg2_rdec + : std_ulogic; +signal + ex2_gsprg0_rdec, ex2_gsprg1_rdec, ex2_gsprg2_rdec, ex2_gsprg3_rdec + , ex2_sprg0_rdec , ex2_sprg1_rdec , ex2_sprg2_rdec , ex2_sprg3_rdec + , ex2_sprg4_rdec , ex2_sprg5_rdec , ex2_sprg6_rdec , ex2_sprg7_rdec + , ex2_sprg8_rdec , ex2_vrsave_rdec + : std_ulogic; +signal + ex2_ccr0_wdec , ex2_ccr1_wdec , ex2_ccr2_wdec , ex2_dac1_wdec + , ex2_dac2_wdec , ex2_dac3_wdec , ex2_dac4_wdec , ex2_givpr_wdec + , ex2_iac1_wdec , ex2_iac2_wdec , ex2_iac3_wdec , ex2_iac4_wdec + , ex2_ivpr_wdec , ex2_tbl_wdec , ex2_tbu_wdec , ex2_tenc_wdec + , ex2_tens_wdec , ex2_trace_wdec , ex2_xucr0_wdec , ex2_xucr3_wdec + , ex2_xucr4_wdec + : std_ulogic; +signal + ex2_gsprg0_wdec, ex2_gsprg1_wdec, ex2_gsprg2_wdec, ex2_gsprg3_wdec + , ex2_sprg0_wdec , ex2_sprg1_wdec , ex2_sprg2_wdec , ex2_sprg3_wdec + , ex2_sprg4_wdec , ex2_sprg5_wdec , ex2_sprg6_wdec , ex2_sprg7_wdec + , ex2_sprg8_wdec , ex2_vrsave_wdec + : std_ulogic; +signal + ex2_dvc1_wdec , ex2_dvc2_wdec , ex2_eplc_wdec , ex2_epsc_wdec + , ex2_immr_wdec , ex2_imr_wdec , ex2_iucr0_wdec , ex2_iucr1_wdec + , ex2_iucr2_wdec , ex2_iudbg0_wdec, ex2_iulfsr_wdec, ex2_iullcr_wdec + , ex2_lper_wdec , ex2_lperu_wdec , ex2_lpidr_wdec , ex2_mas0_wdec + , ex2_mas0_mas1_wdec, ex2_mas1_wdec , ex2_mas2_wdec , ex2_mas2u_wdec + , ex2_mas3_wdec , ex2_mas4_wdec , ex2_mas5_wdec , ex2_mas5_mas6_wdec + , ex2_mas6_wdec , ex2_mas7_wdec , ex2_mas7_mas3_wdec, ex2_mas8_wdec + , ex2_mas8_mas1_wdec, ex2_mmucr0_wdec, ex2_mmucr1_wdec, ex2_mmucr2_wdec + , ex2_mmucr3_wdec, ex2_mmucsr0_wdec, ex2_pid_wdec , ex2_ppr32_wdec + , ex2_xucr2_wdec , ex2_xudbg0_wdec + : std_ulogic; +signal + ex3_gsprg0_wdec, ex3_gsprg1_wdec, ex3_gsprg2_wdec, ex3_gsprg3_wdec + , ex3_sprg0_wdec , ex3_sprg1_wdec , ex3_sprg2_wdec , ex3_sprg3_wdec + , ex3_sprg4_wdec , ex3_sprg5_wdec , ex3_sprg6_wdec , ex3_sprg7_wdec + , ex3_sprg8_wdec , ex3_vrsave_wdec + : std_ulogic; +signal + ex3_gsprg0_we , ex3_gsprg1_we , ex3_gsprg2_we , ex3_gsprg3_we + , ex3_sprg0_we , ex3_sprg1_we , ex3_sprg2_we , ex3_sprg3_we + , ex3_sprg4_we , ex3_sprg5_we , ex3_sprg6_we , ex3_sprg7_we + , ex3_sprg8_we , ex3_vrsave_we + : std_ulogic; +signal + ex6_ccr0_wdec , ex6_ccr1_wdec , ex6_ccr2_wdec , ex6_tbl_wdec + , ex6_tbu_wdec , ex6_tenc_wdec , ex6_tens_wdec , ex6_xucr0_wdec + : std_ulogic; +signal + ex6_ccr0_we , ex6_ccr1_we , ex6_ccr2_we , ex6_tbl_we + , ex6_tbu_we , ex6_tenc_we , ex6_tens_we , ex6_xucr0_we + : std_ulogic; +signal + ccr0_act , ccr1_act , ccr2_act , pir_act + , pvr_act , tb_act , tbl_act , tbu_act + , tenc_act , tens_act , tensr_act , tir_act + , xucr0_act + : std_ulogic; +signal + ccr0_do , ccr1_do , ccr2_do , pir_do + , pvr_do , tb_do , tbl_do , tbu_do + , tenc_do , tens_do , tensr_do , tir_do + , xucr0_do + : std_ulogic_vector(0 to 64); + +begin + + +tiup <= '1'; +tidn <= (others=>'0'); + +cspr_xucr0_clkg_ctl <= spr_xucr0_clkg_ctl; + +rf1_aspr_act_d <= rf0_act; + +rf0_act <= or_reduce(dec_spr_rf0_tid) or spr_xucr0_clkg_ctl(4); +exx_act_d <= rf0_act & exx_act(0 to 4); + +exx_act(0) <= (exx_act_q(0) and or_reduce(dec_spr_rf1_val)) or spr_xucr0_clkg_ctl(4); +exx_act(1) <= exx_act_q(1); +exx_act(2) <= exx_act_q(2); +exx_act(3) <= exx_act_q(3); +exx_act(4) <= exx_act_q(4); +exx_act(5) <= exx_act_q(5); + +-- Needs to be on for loads and stores, for the DEAR... +exx_act_data(1) <= exx_act(1); +exx_act_data(2) <= exx_act(2); +exx_act_data(3) <= exx_act(3); +exx_act_data(4) <= exx_act(4); +exx_act_data(5) <= exx_act(5); + +cspr_tspr_rf1_act <= exx_act(0); + +dbell_act <= lsu_xu_dbell_val or spr_xucr0_clkg_ctl(4); + +spr_bit_act <= '1'; + +-- Decode +rf1_opcode_is_31 <= rf1_instr_q(0 to 5) = "011111"; +ex1_opcode_is_31 <= ex1_instr_q(0 to 5) = "011111"; +rf1_is_mfspr <= '1' when rf1_opcode_is_31 and rf1_instr_q(21 to 30) = "0101010011" else '0'; -- 31/339 +rf1_is_mtspr <= '1' when rf1_opcode_is_31 and rf1_instr_q(21 to 30) = "0111010011" else '0'; -- 31/467 +ex1_is_mfmsr <= '1' when ex1_opcode_is_31 and ex1_instr_q(21 to 30) = "0001010011" else '0'; -- 31/083 +ex1_is_mtmsr <= '1' when ex1_opcode_is_31 and ex1_instr_q(21 to 30) = "0010010010" else '0'; -- 31/146 +ex1_is_mftb <= '1' when ex1_opcode_is_31 and ex1_instr_q(21 to 30) = "0101110011" else '0'; -- 31/371 +ex1_is_wait <= '1' when ex1_opcode_is_31 and ex1_instr_q(21 to 30) = "0000111110" else '0'; -- 31/062 +ex1_is_msgclr <= '1' when ex1_opcode_is_31 and ex1_instr_q(21 to 30) = "0011101110" else '0'; -- 31/238 +ex1_is_wrtee <= '1' when ex1_opcode_is_31 and ex1_instr_q(21 to 30) = "0010000011" else '0'; -- 31/131 +ex1_is_wrteei <= '1' when ex1_opcode_is_31 and ex1_instr_q(21 to 30) = "0010100011" else '0'; -- 31/163 +ex1_is_mtdcr <= '1' when ex1_opcode_is_31 and ex1_instr_q(21 to 30) = "0111000011" else '0'; -- 31/451 +ex1_is_mtdcrux <= '1' when ex1_opcode_is_31 and ex1_instr_q(21 to 30) = "0110100011" else '0'; -- 31/419 +ex1_is_mtdcrx <= '1' when ex1_opcode_is_31 and ex1_instr_q(21 to 30) = "0110000011" else '0'; -- 31/387 +ex1_is_mfdcr <= '1' when ex1_opcode_is_31 and ex1_instr_q(21 to 30) = "0101000011" else '0'; -- 31/323 +ex1_is_mfdcrux <= '1' when ex1_opcode_is_31 and ex1_instr_q(21 to 30) = "0100100011" else '0'; -- 31/291 +ex1_is_mfdcrx <= '1' when ex1_opcode_is_31 and ex1_instr_q(21 to 30) = "0100000011" else '0'; -- 31/259 +ex1_is_mfcr <= '1' when ex1_opcode_is_31 and ex1_instr_q(21 to 30) = "0000010011" else '0'; -- 31/19 +ex1_is_mtcrf <= '1' when ex1_opcode_is_31 and ex1_instr_q(21 to 30) = "0010010000" else '0'; -- 31/144 + +ex1_dcr_instr <= ex1_is_mtdcrux or ex1_is_mtdcrx or ex1_is_mtdcr or ex1_dcr_read; +ex1_dcr_read <= ex1_is_mfdcrux or ex1_is_mfdcrx or ex1_is_mfdcr; +ex1_dcr_user <= ex1_is_mtdcrux or ex1_is_mfdcrux; +ex1_dcr_val <= ex1_dcr_instr and spr_ccr2_en_dcr_int; + +ex2_any_mfspr_d <= ex1_is_mfspr_q or ex1_is_mfmsr or ex1_is_mftb or ex1_is_mfcr; +ex2_any_mtspr_d <= ex1_is_mtspr_q or ex1_is_mtmsr or ex1_is_mtcrf or ex1_is_wrtee or ex1_is_wrteei; + +-- Run State +xu_pc_spr_ccr0_we <= spr_ccr0_we_rev and quiesced_q; +spr_ccr0_we_rev <= reverse(spr_ccr0_we); +spr_tens_ten_rev <= reverse(spr_tens_ten); + +quiesce_b_q <= not (quiesce_q and not running_q); +quiesce_d <= iu_quiesce_q and + lsu_quiesce_q and + mm_quiesce_q and + bx_quiesce_q; + +cpl_quiesce_b_q <= not cpl_quiesce_q; +cpl_quiesce_d <= cpl_spr_quiesce and not running_q; + +-- CPL needs a seperate copy that doesn't include its own signals +quiesced_d <= quiesce_q and not quiesce_ctr_zero_b and + cpl_quiesce_q and not cpl_quiesce_ctr_zero_b; + +xu_pc_running <= running; + +quiesced_4cpl_d <= lsu_quiesce_q; +spr_cpl_quiesce <= quiesced_4cpl_q; + +running <= running_q or not quiesced_q; +running_d <= (cpl_spr_stop nor spr_ccr0_we_rev) and spr_tens_ten_rev; +iu_run_thread_d <= running_q and llmask; +xu_iu_run_thread <= iu_run_thread_q; + +spr_tensr <= spr_tens_ten or reverse(running); + +ex6_any_valid <= or_reduce(ex6_valid_q); +ex1_tenc_we <= (ex1_instr_q(11 to 20) = "1011101101"); -- 439 +ex1_ccr0_we <= (ex1_instr_q(11 to 20) = "1000011111"); -- 1008 + +-- Wakeup Condition Masking +pm_wake_up_gen : for t in 0 to threads-1 generate + +-- Reset the mask when running +-- Set the mask on a valid wait instruction +-- Otherwise hold + +-- WAIT[WC](0) = Resume on Imp. Specific +-- WAIT[WC](1) = Resume on no reservation +waitimpl_val_d(t) <= '0' when pm_wake_up(t) ='1' else + ex6_wait_wc_q(9) when ex6_wait(t) ='1' else + waitimpl_val_q(t); + +waitrsv_val_d(t) <= '0' when pm_wake_up(t) ='1' else + ex6_wait_wc_q(10) when ex6_wait(t) ='1' else + waitrsv_val_q(t); + +-- Block interrupts (mask=0) if: +-- Stopped via (HW Debug and pc_xu_extirpts_dis_on_stop)=1 +-- Stopped via TEN=0 +-- Stopped via CCR0=1, unless overriden by CCR1=1 (and wait, if applicable) +crit_mask(t) <= not(ext_dbg_dis_q(t) or not spr_tens_ten_rev(t) or (spr_ccr0_we_rev(t) and not ccr1_q(60-6*t))); +base_mask(t) <= not(ext_dbg_dis_q(t) or not spr_tens_ten_rev(t) or (spr_ccr0_we_rev(t) and not ccr1_q(61-6*t))); +dec_mask(t) <= not(ext_dbg_dis_q(t) or not spr_tens_ten_rev(t) or (spr_ccr0_we_rev(t) and not ccr1_q(62-6*t))); +fit_mask(t) <= not(ext_dbg_dis_q(t) or not spr_tens_ten_rev(t) or (spr_ccr0_we_rev(t) and not ccr1_q(63-6*t))); + +cspr_tspr_crit_mask(t) <= crit_mask(t); +cspr_tspr_ext_mask(t) <= base_mask(t); +cspr_tspr_dec_mask(t) <= dec_mask(t); +cspr_tspr_fit_mask(t) <= fit_mask(t); +cspr_tspr_wdog_mask(t) <= crit_mask(t); +cspr_tspr_udec_mask(t) <= dec_mask(t); +cspr_tspr_perf_mask(t) <= base_mask(t); + +-- Generate Conditional Wait flush +ex2_wait_flush(t) <= ex2_tid(t) and ex2_is_wait_q and + ((ex2_wait_wc_q = "00") or -- Unconditional Wait + (ex2_wait_wc_q = "01" and an_ac_reservation_vld_q(t) and not ccr1_q(58-6*t)) or -- Reservation Exists + (ex2_wait_wc_q = "10" and an_ac_sleep_en_q(t) and not ccr1_q(59-6*t))); -- Impl. Specific Exists (Sleep enabled) + +ex2_ccr0_flush(t) <= ex2_is_mtspr_q and ex2_ccr0_we_q and ex2_rs0_q(55-t) and ex2_rs0_q(63-t); + +ex2_tenc_flush(t) <= ex2_is_mtspr_q and ex2_tenc_we_q and ex2_rs0_q(63-t); + + +end generate; + +ex2_wait <= or_reduce(ex2_wait_flush); + +with s3'(ex2_is_wait_q & ex2_ccr0_we_q & ex2_tenc_we_q) select + spr_cpl_ex2_run_ctl_flush <= ex2_wait_flush when "100", + ex2_ccr0_flush when "010", + ex2_tenc_flush when "001", + (others=>'0') when others; + +pm_wake_up <= (not an_ac_reservation_vld_q and waitrsv_val_q ) or + ( not an_ac_sleep_en_q and waitimpl_val_q) or + tspr_cspr_pm_wake_up or + dbell_interrupt_q or + cdbell_interrupt_q or + gdbell_interrupt_q or + gcdbell_interrupt_q or + gmcdbell_interrupt_q; + +ex6_wait <= gate(ex6_tid,(ex6_any_valid and ex6_wait_q)); + + +-- Debug Timer Disable +tb_dbg_dis_d <= and_reduce(cpl_spr_stop) and pc_xu_timebase_dis_on_stop; +dec_dbg_dis_d <= gate(cpl_spr_stop,pc_xu_decrem_dis_on_stop); +ext_dbg_dis_d <= gate(cpl_spr_stop,pc_xu_extirpts_dis_on_stop); + +-- LiveLock Priority +cspr_tspr_llen <= running_q; +cspr_tspr_llpri <= llpri_q; +llpres <= or_reduce( tspr_cspr_lldet); +llunmasked <= or_reduce( llpri_q and tspr_cspr_lldet); +llmasked <= or_reduce(not llpri_q and tspr_cspr_lldet); +llpulse <= or_reduce( llpri_q and tspr_cspr_llpulse); + +-- Increment the hang priority if: +-- There is a hang present, but the priority is masking it. +-- There is another hang present, and there is a hang pulse. +llpri_inc <= (llpres and not llunmasked) or + (llpulse and llmasked and llunmasked); + +llpri_d <= llpri_q(threads-1) & llpri_q(0 to threads-2); + +llmask <= (llpri_q and tspr_cspr_lldet) or not (0 to threads-1=>llpres); + + + +with s2'(instr_trace_tid_q) select + instr_trace_tid <= "1000" when "00", + "0100" when "01", + "0010" when "10", + "0001" when others; + +instr_trace_mode <= gate(instr_trace_tid,instr_trace_mode_q); + +with s4'(dec_spr_rf0_tid) select + rf1_aspr_tid_d <= "00" when "1000", + "01" when "0100", + "10" when "0010", + "11" when others; + +with dec_spr_rf1_val select + rf1_tid <= "00" when "1000", + "01" when "0100", + "10" when "0010", + "11" when others; +with ex1_tid_q select + ex1_tid <= "1000" when "00", + "0100" when "01", + "0010" when "10", + "0001" when others; +with ex2_tid_q select + ex2_tid <= "1000" when "00", + "0100" when "01", + "0010" when "10", + "0001" when others; + +with ex4_tid_q select + ex4_tid <= "1000" when "00", + "0100" when "01", + "0010" when "10", + "0001" when others; + +with ex5_tid_q select + ex5_tid <= "1000" when "00", + "0100" when "01", + "0010" when "10", + "0001" when others; + +with ex6_tid_q select + ex6_tid <= "1000" when "00", + "0100" when "01", + "0010" when "10", + "0001" when others; +with ram_thread_q select + ram_tid <= "1000" when "00", + "0100" when "01", + "0010" when "10", + "0001" when others; + +rf1_instr <= rf1_instr_q(11 to 20); +ex2_instr_d <= gate(ex1_instr_q(11 to 20),(ex1_is_mfspr_q or ex1_is_mtspr_q or ex1_is_wrteei or ex1_is_wait or ex1_is_mftb)); +ex2_instr <= ex2_instr_q(11 to 20); +ex3_instr_d <= ex2_instr_q or gate(ex2_dcrn_q,ex2_dcr_val_q); + +rf1_msr_gs_d <= or_reduce(tspr_msr_gs and dec_spr_rf0_tid); +ex2_msr_gs_d <= (others=>or_reduce(tspr_msr_gs and ex1_tid)); +ex3_msr_gs_d <= or_reduce(tspr_msr_gs and ex2_tid); + +ex5_val_d <= dec_spr_ex4_val and not xu_ex4_flush; +ex5_valid <= ex5_val_q and not xu_ex5_flush; +ex5_val <= or_reduce(ex5_valid); +ex5_spr_wd <= ex5_rt_q; +ex5_rt_q_b <= ex5_rt_q; +ex3_instr <= ex3_instr_q; + +ex6_val <= ex6_val_q; +ex6_spr_wd <= ex6_rt_q; +ex6_instr <= ex6_instr_q; +ex6_is_mtspr <= ex6_is_mtspr_q; + +ram_mode <= gate(ram_tid,ram_mode_q); +cspr_tspr_ram_mode <= ram_mode; + +cspr_tspr_msrovride_en <= gate(ram_mode,msrovride_enab_q); + +-- Perf Events +perf_count : for t in 0 to threads-1 generate + perf_event_d(0+3*t) <= running(t); + perf_event_d(1+3*t) <= ex5_valid(t) and ex5_any_mfspr_q; + perf_event_d(2+3*t) <= ex5_valid(t) and ex5_any_mtspr_q; + + spr_perf_tx_events(0+8*t) <= perf_event_q(0+3*t); + spr_perf_tx_events(1+8*t) <= tb_act_q; + spr_perf_tx_events(2+8*t) <= perf_event_q(1+3*t); + spr_perf_tx_events(3+8*t) <= perf_event_q(2+3*t); + spr_perf_tx_events(4+8*t) <= waitrsv_val_q(t); + spr_perf_tx_events(5+8*t) <= tspr_cspr_async_int(0+3*t); + spr_perf_tx_events(6+8*t) <= tspr_cspr_async_int(1+3*t); + spr_perf_tx_events(7+8*t) <= tspr_cspr_async_int(2+3*t); +end generate; + +-- SPR Input Control +-- CCR0 +ccr0_act <= spr_xucr0_clkg_ctl(4) or ex6_ccr0_we or or_reduce(pm_wake_up) or ex6_wait_q; + +ccr0_wen <= (0 to 1=>ex6_ccr0_we) & gate(ex6_spr_wd(56-threads to 55),ex6_ccr0_we); + +ccr0_di <= (ex6_ccr0_di and ccr0_wen) or + ( ccr0_q and not ccr0_wen); + +ccr0_d(62-threads to 63-threads) <= ccr0_di(62-threads to 63-threads); +ccr0_d(64-threads to 63) <= (ccr0_di(64-threads to 63) or reverse(ex6_wait)) and not reverse(pm_wake_up); + +-- CCR1 +ccr1_act <= ex6_ccr1_we; +ccr1_d <= ex6_ccr1_di; + +-- CCR2 +ccr2_act <= ex6_ccr2_we; +ccr2_d <= ex6_ccr2_di; + +-- PIR +pir_act <= tiup; + +-- PVR +pvr_act <= tiup; + +version <= x"00" & spr_pvr_version_dc(8 to 15); +revision <= x"0" & spr_pvr_revision_dc(12 to 15) & x"0" & revision_minor; +revision_minor <= x"0"; + +-- TB +tb_update_pulse <= (tb_update_pulse_q xor tb_update_pulse_1_q); -- Any Edge + +timer_update_int <= tb_update_enable_q and (tb_update_pulse or not spr_xucr0_tcs); -- Update on external signal selected by XUCR0[TCS] +timer_update <= timer_update_q; + +tb_act_d <= not tb_dbg_dis_q and -- Not Stopped via HW DBG (if enabled) + not or_reduce(tspr_cspr_freeze_timers) and -- Timers not frozen due to debug event + timer_update_int; + +tb_act <= tb_act_q; +tb_q <= tbu_q & tbl_q; +tb <= std_ulogic_vector(unsigned(tb_q)+1); + +-- TBL +tbl_act <= tb_act or ex6_tbl_we; +with (ex6_tbl_we) select + tbl_d <= ex6_tbl_di when '1', + tb(32 to 63) when others; + +-- TBU +tbu_act <= tb_act or ex6_tbu_we; +with (ex6_tbu_we) select + tbu_d <= ex6_tbu_di when '1', + tb(0 to 31) when others; + +-- TENC +tenc_act <= tiup; + +-- TENS +tens_act <= ex6_tenc_we or ex6_tens_we; +tens_d <= (tens_q and not ex6_tens_di) when ex6_tenc_we='1' else + (tens_q or ex6_tens_di); +-- TENSR +tensr_act <= tiup; + +-- TIR +tir_act <= tiup; + +-- XUCR0 +ex5_flush <= or_reduce(xu_ex5_flush and ex5_tid); + +ex6_set_xucr0_cslc_d <=(lsu_xu_spr_xucr0_cslc_xuop and not ex5_flush) or + lsu_xu_spr_xucr0_cslc_binv; + +ex6_set_xucr0_cul_d <=(lsu_xu_spr_xucr0_cul and not ex5_flush); + +ex6_set_xucr0_clo_d <= lsu_xu_spr_xucr0_clo; + +xucr0_act <= spr_xucr0_clkg_ctl(4) or ex6_xucr0_we or + ex6_set_xucr0_cslc_q or ex6_set_xucr0_cul_q or ex6_set_xucr0_clo_q; + +xucr0_d <= xucr0_di(xucr0_q'left to 60) & + (xucr0_di(61) or ex6_set_xucr0_cslc_q) & + (xucr0_di(62) or ex6_set_xucr0_cul_q) & + (xucr0_di(63) or ex6_set_xucr0_clo_q); + +with (ex6_xucr0_we) select + xucr0_di <= ex6_xucr0_di when '1', + xucr0_q when others; + +-- IO signal assignments + + -- FIT LL WDOG +cspr_tspr_timebase_taps(8) <= tbl_q(32+23); -- 9 x +cspr_tspr_timebase_taps(7) <= tbl_q(32+11); -- 21 x +cspr_tspr_timebase_taps(6) <= tbl_q(32+ 7); -- 25 x +cspr_tspr_timebase_taps(5) <= tbl_q(32+21); -- 11 x x +cspr_tspr_timebase_taps(4) <= tbl_q(32+17); -- 15 x x +cspr_tspr_timebase_taps(3) <= tbl_q(32+13); -- 19 x x x +cspr_tspr_timebase_taps(2) <= tbl_q(32+ 9); -- 23 x x x +cspr_tspr_timebase_taps(1) <= tbl_q(32+ 5); -- 27 x +cspr_tspr_timebase_taps(0) <= tbl_q(32+ 1); -- 31 x + +cspr_tspr_timebase_taps(9) <= tbl_q(32+ 7); -- 29 x -- Replaced 1 for wdog + + +cspr_tspr_ex2_tid <= ex2_tid; +cspr_tspr_ex1_instr <= ex1_instr_q; +cspr_tspr_ex5_is_mtmsr <= ex5_is_mtmsr_q; +cspr_tspr_ex5_is_mtspr <= ex5_is_mtspr_q; +cspr_tspr_ex5_instr <= ex5_instr_q; +cspr_tspr_dec_dbg_dis <= dec_dbg_dis_q; + +reset_wd_complete <= pc_xu_reset_wd_complete_q; +reset_3_complete <= pc_xu_reset_3_complete_q; +reset_2_complete <= pc_xu_reset_2_complete_q; +reset_1_complete <= pc_xu_reset_1_complete_q; + +cspr_tspr_ex5_is_wrtee <= ex5_is_wrtee_q; +cspr_tspr_ex5_is_wrteei <= ex5_is_wrteei_q; + +cspr_aspr_ex5_we <= or_reduce(ex5_aspr_we_q and not xu_ex5_flush); +cspr_aspr_ex5_waddr <= ex5_aspr_addr_q & ex5_tid_q; +cspr_aspr_rf1_re <= rf1_aspr_re(1) and rf1_aspr_act_q; +cspr_aspr_rf1_raddr <= rf1_aspr_addr & rf1_aspr_tid_q; + +xu_lsu_slowspr_val <= ex6_val_q and ex6_sspr_val_q; +xu_lsu_slowspr_rw <= not ex6_is_mtspr_q; +xu_lsu_slowspr_etid <= ex6_tid_q; +xu_lsu_slowspr_addr <= ex6_instr_q(16 to 20) & ex6_instr_q(11 to 15); +xu_lsu_slowspr_data <= ex6_spr_wd; + +ex4_dcr_val <= exx_act(4) and ex4_dcr_val_q; +ex5_dcr_val <= ex5_val and ex5_dcr_val_q; + +ac_an_dcr_act <= ex5_dcr_val_q; +ac_an_dcr_val <= ex6_dcr_val_q; +ac_an_dcr_read <= ex6_dcr_read_q; +ac_an_dcr_user <= ex6_dcr_user_q; +ac_an_dcr_etid <= ex6_tid_q; +ac_an_dcr_addr <= ex6_instr_q(11 to 20); +ac_an_dcr_data <= ex6_spr_wd; + +spr_cpl_ex3_spr_hypv <= ex3_hypv_spr_q; +spr_cpl_ex3_spr_illeg <= ex3_illeg_spr_q; +spr_cpl_ex3_spr_priv <= ex3_priv_spr_q; + +xu_lsu_mtspr_trace_en <= gate((spr_xucr0_trace_um or not tspr_msr_pr),spr_ccr2_en_trace); + +dbell_pir_match <= (lsu_xu_dbell_pirtag_q(50 to 61) = pir_do(51 to 62)); + +with lsu_xu_dbell_pirtag_q(62 to 63) select + dbell_pir_thread <= "1000" when "00", + "0100" when "01", + "0010" when "10", + "0001" when "11", + "0000" when others; + +cspr_tspr_dbell_pirtag <= lsu_xu_dbell_pirtag_q; + +dbell : for t in 0 to threads-1 generate + +set_dbell(t) <= lsu_xu_dbell_val_q and lsu_xu_dbell_type_q = "00000" and lsu_xu_dbell_lpid_match_q and (lsu_xu_dbell_brdcast_q or (dbell_pir_match and dbell_pir_thread(t))); +set_cdbell(t) <= lsu_xu_dbell_val_q and lsu_xu_dbell_type_q = "00001" and lsu_xu_dbell_lpid_match_q and (lsu_xu_dbell_brdcast_q or (dbell_pir_match and dbell_pir_thread(t))); +set_gdbell(t) <= lsu_xu_dbell_val_q and lsu_xu_dbell_type_q = "00010" and lsu_xu_dbell_lpid_match_q and (lsu_xu_dbell_brdcast_q or tspr_cspr_gpir_match(t)); +set_gcdbell(t) <= lsu_xu_dbell_val_q and lsu_xu_dbell_type_q = "00011" and lsu_xu_dbell_lpid_match_q and (lsu_xu_dbell_brdcast_q or tspr_cspr_gpir_match(t)); +set_gmcdbell(t) <= lsu_xu_dbell_val_q and lsu_xu_dbell_type_q = "00100" and lsu_xu_dbell_lpid_match_q and (lsu_xu_dbell_brdcast_q or tspr_cspr_gpir_match(t)); + +clr_dbell(t) <= ex6_valid_q(t) and ex6_is_msgclr_q and (ex6_spr_wd(32 to 36) = "00000"); +clr_cdbell(t) <= ex6_valid_q(t) and ex6_is_msgclr_q and (ex6_spr_wd(32 to 36) = "00001"); +clr_gdbell(t) <= ex6_valid_q(t) and ex6_is_msgclr_q and (ex6_spr_wd(32 to 36) = "00010"); +clr_gcdbell(t) <= ex6_valid_q(t) and ex6_is_msgclr_q and (ex6_spr_wd(32 to 36) = "00011"); +clr_gmcdbell(t) <= ex6_valid_q(t) and ex6_is_msgclr_q and (ex6_spr_wd(32 to 36) = "00100"); + +end generate; + +dbell_present_d <= set_dbell or (dbell_present_q and not (clr_dbell or ex6_dbell_taken_q )); +cdbell_present_d <= set_cdbell or (cdbell_present_q and not (clr_cdbell or ex6_cdbell_taken_q )); +gdbell_present_d <= set_gdbell or (gdbell_present_q and not (clr_gdbell or ex6_gdbell_taken_q )); +gcdbell_present_d <= set_gcdbell or (gcdbell_present_q and not (clr_gcdbell or ex6_gcdbell_taken_q )); +gmcdbell_present_d <= set_gmcdbell or (gmcdbell_present_q and not (clr_gmcdbell or ex6_gmcdbell_taken_q)); + +dbell_interrupt <= dbell_present_q and base_mask and (tspr_msr_ee or tspr_msr_gs); +cdbell_interrupt <= cdbell_present_q and crit_mask and (tspr_msr_ce or tspr_msr_gs); +gdbell_interrupt <= gdbell_present_q and base_mask and tspr_msr_ee and tspr_msr_gs; +gcdbell_interrupt <= gcdbell_present_q and crit_mask and tspr_msr_ce and tspr_msr_gs; +gmcdbell_interrupt <= gmcdbell_present_q and crit_mask and tspr_msr_me and tspr_msr_gs; + +spr_cpl_dbell_interrupt <= dbell_interrupt_q; +spr_cpl_cdbell_interrupt <= cdbell_interrupt_q; +spr_cpl_gdbell_interrupt <= gdbell_interrupt_q; +spr_cpl_gcdbell_interrupt <= gcdbell_interrupt_q; +spr_cpl_gmcdbell_interrupt <= gmcdbell_interrupt_q; + +-- Debug +cspr_debug0 <= ex6_valid_q & + ex1_instr_q & -- 36 + ex3_hypv_spr_q & + ex3_illeg_spr_q & + ex3_priv_spr_q & + timer_update_q ; -- 4 + +cspr_debug1 <= lsu_xu_dbell_val_q & + lsu_xu_dbell_type_q & + lsu_xu_dbell_lpid_match_q & + lsu_xu_dbell_brdcast_q & + lsu_xu_dbell_pirtag_q & -- 25 + spr_ccr0_we_rev & + quiesced_q & + iu_quiesce_q & + lsu_quiesce_q & + mm_quiesce_q & + bx_quiesce_q & + cpl_quiesce_q & + running & + iu_run_thread_q & + pm_wake_up & + an_ac_reservation_vld_q & + an_ac_sleep_en_q & + waitimpl_val_q & + waitrsv_val_q & + llpri_q & + tspr_cspr_lldet & "00"; -- 64 + +-- Array ECC Check +spr_cpl_ex3_sprg_ce <= ex3_sprg_ce; +spr_cpl_ex3_sprg_ue <= ex3_sprg_ue; + +ex2_aspr_rdata_d(64-regsize) <= aspr_cspr_ex1_rdata(64-regsize); +ex2_aspr_rdata_d(65-regsize to 72-(64/regsize)) <= aspr_cspr_ex1_rdata(65-regsize to 72-(64/regsize)); + +ex2_eccchk_syn_b <= not ex2_eccchk_syn; + +xuq_spr_rd_eccgen : entity work.xuq_eccgen(xuq_eccgen) +generic map(regsize => regsize) +port map(din => ex2_aspr_rdata_q, + Syn => ex2_eccchk_syn); + +xuq_spr_eccchk : entity work.xuq_eccchk(xuq_eccchk) +generic map(regsize => regsize) +port map(din => ex2_aspr_rdata_q(64-regsize to 63), + EnCorr => encorr, + NSyn => ex2_eccchk_syn_b, + Corrd => ex2_corr_rdata, + SBE => ex2_sprg_ce, + UE => ex2_sprg_ue); + +encorr <= '1'; + +ex5_sprg_ce <= gate(ex5_valid,ex5_sprg_ce_q); + +xu_spr_cspr_ce_err_rpt : entity tri.tri_direct_err_rpt(tri_direct_err_rpt) +generic map(width => threads, expand_type => expand_type) +port map ( vd => vdd, gd => gnd, + err_in => ex6_sprg_ce_q, + err_out => xu_pc_err_sprg_ecc); + +ex3_aspr_rt(32 to 63) <= gate(ex3_corr_rdata_q(32 to 63), ex3_aspr_re_q(1)); +aspr_rt : if regsize > 32 generate +ex3_aspr_rt(64-regsize to 31) <= gate(ex3_corr_rdata_q(64-regsize to 31),ex3_aspr_re_q(0)); +end generate; + +ex3_tspr_rt <= or_reduce_t(tspr_cspr_ex3_tspr_rt,threads); + +spr_byp_ex3_spr_rt <= (ex3_cspr_rt_q and not (64-regsize to 63=>ex3_sspr_val_q)) or ex3_tspr_rt or ex3_aspr_rt; + +-- Fast SPR Read +ex2_ccr0_rdec <= (ex2_instr(11 to 20) = "1000011111"); -- 1008 +ex2_ccr1_rdec <= (ex2_instr(11 to 20) = "1000111111"); -- 1009 +ex2_ccr2_rdec <= (ex2_instr(11 to 20) = "1001011111"); -- 1010 +ex2_dac1_rdec <= (ex2_instr(11 to 20) = "1110001001"); -- 316 +ex2_dac2_rdec <= (ex2_instr(11 to 20) = "1110101001"); -- 317 +ex2_dac3_rdec <= (ex2_instr(11 to 20) = "1000111010"); -- 849 +ex2_dac4_rdec <= (ex2_instr(11 to 20) = "1001011010"); -- 850 +ex2_givpr_rdec <= (ex2_instr(11 to 20) = "1111101101"); -- 447 +ex2_iac1_rdec <= (ex2_instr(11 to 20) = "1100001001"); -- 312 +ex2_iac2_rdec <= (ex2_instr(11 to 20) = "1100101001"); -- 313 +ex2_iac3_rdec <= (ex2_instr(11 to 20) = "1101001001"); -- 314 +ex2_iac4_rdec <= (ex2_instr(11 to 20) = "1101101001"); -- 315 +ex2_ivpr_rdec <= (ex2_instr(11 to 20) = "1111100001"); -- 63 +ex2_pir_rdec <= (ex2_instr(11 to 20) = "1111001000"); -- 286 +ex2_pvr_rdec <= (ex2_instr(11 to 20) = "1111101000"); -- 287 +ex2_tb_rdec <= (ex2_instr(11 to 20) = "0110001000"); -- 268 +ex2_tbu_rdec <= ((ex2_instr(11 to 20) = "0110101000")); -- 269 +ex2_tenc_rdec <= (ex2_instr(11 to 20) = "1011101101"); -- 439 +ex2_tens_rdec <= (ex2_instr(11 to 20) = "1011001101"); -- 438 +ex2_tensr_rdec <= (ex2_instr(11 to 20) = "1010101101"); -- 437 +ex2_tir_rdec <= (ex2_instr(11 to 20) = "1111001101"); -- 446 +ex2_xucr0_rdec <= (ex2_instr(11 to 20) = "1011011111"); -- 1014 +ex2_xucr3_rdec <= (ex2_instr(11 to 20) = "1010011010"); -- 852 +ex2_xucr4_rdec <= (ex2_instr(11 to 20) = "1010111010"); -- 853 +ex2_ccr0_re <= ex2_ccr0_rdec; +ex2_ccr1_re <= ex2_ccr1_rdec; +ex2_ccr2_re <= ex2_ccr2_rdec; +ex2_dac1_re <= ex2_dac1_rdec; +ex2_dac2_re <= ex2_dac2_rdec; +ex2_dac3_re <= ex2_dac3_rdec; +ex2_dac4_re <= ex2_dac4_rdec; +ex2_givpr_re <= ex2_givpr_rdec; +ex2_iac1_re <= ex2_iac1_rdec; +ex2_iac2_re <= ex2_iac2_rdec; +ex2_iac3_re <= ex2_iac3_rdec; +ex2_iac4_re <= ex2_iac4_rdec; +ex2_ivpr_re <= ex2_ivpr_rdec; +ex2_pir_re <= ex2_pir_rdec and not ex2_msr_gs_q(0); +ex2_pvr_re <= ex2_pvr_rdec; +ex2_tb_re <= ex2_tb_rdec; +ex2_tbu_re <= ex2_tbu_rdec; +ex2_tenc_re <= ex2_tenc_rdec; +ex2_tens_re <= ex2_tens_rdec; +ex2_tensr_re <= ex2_tensr_rdec; +ex2_tir_re <= ex2_tir_rdec; +ex2_xucr0_re <= ex2_xucr0_rdec; +ex2_xucr3_re <= ex2_xucr3_rdec; +ex2_xucr4_re <= ex2_xucr4_rdec; + +readmux_00 : if a2mode = 0 and hvmode = 0 generate +ex2_cspr_rt <= + (ccr0_do(DO'range) and (DO'range => ex2_ccr0_re )) or + (ccr1_do(DO'range) and (DO'range => ex2_ccr1_re )) or + (ccr2_do(DO'range) and (DO'range => ex2_ccr2_re )) or + (pir_do(DO'range) and (DO'range => ex2_pir_re )) or + (pvr_do(DO'range) and (DO'range => ex2_pvr_re )) or + (tb_do(DO'range) and (DO'range => ex2_tb_re )) or + (tbu_do(DO'range) and (DO'range => ex2_tbu_re )) or + (tenc_do(DO'range) and (DO'range => ex2_tenc_re )) or + (tens_do(DO'range) and (DO'range => ex2_tens_re )) or + (tensr_do(DO'range) and (DO'range => ex2_tensr_re )) or + (tir_do(DO'range) and (DO'range => ex2_tir_re )) or + (xucr0_do(DO'range) and (DO'range => ex2_xucr0_re )); +end generate; +readmux_01 : if a2mode = 0 and hvmode = 1 generate +ex2_cspr_rt <= + (ccr0_do(DO'range) and (DO'range => ex2_ccr0_re )) or + (ccr1_do(DO'range) and (DO'range => ex2_ccr1_re )) or + (ccr2_do(DO'range) and (DO'range => ex2_ccr2_re )) or + (pir_do(DO'range) and (DO'range => ex2_pir_re )) or + (pvr_do(DO'range) and (DO'range => ex2_pvr_re )) or + (tb_do(DO'range) and (DO'range => ex2_tb_re )) or + (tbu_do(DO'range) and (DO'range => ex2_tbu_re )) or + (tenc_do(DO'range) and (DO'range => ex2_tenc_re )) or + (tens_do(DO'range) and (DO'range => ex2_tens_re )) or + (tensr_do(DO'range) and (DO'range => ex2_tensr_re )) or + (tir_do(DO'range) and (DO'range => ex2_tir_re )) or + (xucr0_do(DO'range) and (DO'range => ex2_xucr0_re )); +end generate; +readmux_10 : if a2mode = 1 and hvmode = 0 generate +ex2_cspr_rt <= + (ccr0_do(DO'range) and (DO'range => ex2_ccr0_re )) or + (ccr1_do(DO'range) and (DO'range => ex2_ccr1_re )) or + (ccr2_do(DO'range) and (DO'range => ex2_ccr2_re )) or + (pir_do(DO'range) and (DO'range => ex2_pir_re )) or + (pvr_do(DO'range) and (DO'range => ex2_pvr_re )) or + (tb_do(DO'range) and (DO'range => ex2_tb_re )) or + (tbu_do(DO'range) and (DO'range => ex2_tbu_re )) or + (tenc_do(DO'range) and (DO'range => ex2_tenc_re )) or + (tens_do(DO'range) and (DO'range => ex2_tens_re )) or + (tensr_do(DO'range) and (DO'range => ex2_tensr_re )) or + (tir_do(DO'range) and (DO'range => ex2_tir_re )) or + (xucr0_do(DO'range) and (DO'range => ex2_xucr0_re )); +end generate; +readmux_11 : if a2mode = 1 and hvmode = 1 generate +ex2_cspr_rt <= + (ccr0_do(DO'range) and (DO'range => ex2_ccr0_re )) or + (ccr1_do(DO'range) and (DO'range => ex2_ccr1_re )) or + (ccr2_do(DO'range) and (DO'range => ex2_ccr2_re )) or + (pir_do(DO'range) and (DO'range => ex2_pir_re )) or + (pvr_do(DO'range) and (DO'range => ex2_pvr_re )) or + (tb_do(DO'range) and (DO'range => ex2_tb_re )) or + (tbu_do(DO'range) and (DO'range => ex2_tbu_re )) or + (tenc_do(DO'range) and (DO'range => ex2_tenc_re )) or + (tens_do(DO'range) and (DO'range => ex2_tens_re )) or + (tensr_do(DO'range) and (DO'range => ex2_tensr_re )) or + (tir_do(DO'range) and (DO'range => ex2_tir_re )) or + (xucr0_do(DO'range) and (DO'range => ex2_xucr0_re )); +end generate; + +-- Fast SPR Write +ex6_ccr0_wdec <= (ex6_instr(11 to 20) = "1000011111"); -- 1008 +ex6_ccr1_wdec <= (ex6_instr(11 to 20) = "1000111111"); -- 1009 +ex6_ccr2_wdec <= (ex6_instr(11 to 20) = "1001011111"); -- 1010 +ex6_tbl_wdec <= (ex6_instr(11 to 20) = "1110001000"); -- 284 +ex6_tbu_wdec <= ((ex6_instr(11 to 20) = "1110101000")); -- 285 +ex6_tenc_wdec <= (ex6_instr(11 to 20) = "1011101101"); -- 439 +ex6_tens_wdec <= (ex6_instr(11 to 20) = "1011001101"); -- 438 +ex6_xucr0_wdec <= (ex6_instr(11 to 20) = "1011011111"); -- 1014 +ex6_ccr0_we <= ex6_val and ex6_is_mtspr and ex6_ccr0_wdec; +ex6_ccr1_we <= ex6_val and ex6_is_mtspr and ex6_ccr1_wdec; +ex6_ccr2_we <= ex6_val and ex6_is_mtspr and ex6_ccr2_wdec; +ex6_tbl_we <= ex6_val and ex6_is_mtspr and ex6_tbl_wdec; +ex6_tbu_we <= ex6_val and ex6_is_mtspr and ex6_tbu_wdec; +ex6_tenc_we <= ex6_val and ex6_is_mtspr and ex6_tenc_wdec; +ex6_tens_we <= ex6_val and ex6_is_mtspr and ex6_tens_wdec; +ex6_xucr0_we <= ex6_val and ex6_is_mtspr and ex6_xucr0_wdec; + +-- Array Read +rf1_gsprg0_rdec <= (rf1_instr(11 to 20) = "1000001011"); -- 368 +rf1_gsprg1_rdec <= (rf1_instr(11 to 20) = "1000101011"); -- 369 +rf1_gsprg2_rdec <= (rf1_instr(11 to 20) = "1001001011"); -- 370 +rf1_gsprg3_rdec <= (rf1_instr(11 to 20) = "1001101011"); -- 371 +rf1_sprg0_rdec <= (rf1_instr(11 to 20) = "1000001000"); -- 272 +rf1_sprg1_rdec <= (rf1_instr(11 to 20) = "1000101000"); -- 273 +rf1_sprg2_rdec <= (rf1_instr(11 to 20) = "1001001000"); -- 274 +rf1_sprg3_rdec <= ((rf1_instr(11 to 20) = "1001101000") or -- 275 + (rf1_instr(11 to 20) = "0001101000")); -- 259 +rf1_sprg4_rdec <= ((rf1_instr(11 to 20) = "1010001000") or -- 276 + (rf1_instr(11 to 20) = "0010001000")); -- 260 +rf1_sprg5_rdec <= ((rf1_instr(11 to 20) = "1010101000") or -- 277 + (rf1_instr(11 to 20) = "0010101000")); -- 261 +rf1_sprg6_rdec <= ((rf1_instr(11 to 20) = "1011001000") or -- 278 + (rf1_instr(11 to 20) = "0011001000")); -- 262 +rf1_sprg7_rdec <= ((rf1_instr(11 to 20) = "1011101000") or -- 279 + (rf1_instr(11 to 20) = "0011101000")); -- 263 +rf1_sprg8_rdec <= (rf1_instr(11 to 20) = "1110010010"); -- 604 +rf1_vrsave_rdec <= (rf1_instr(11 to 20) = "0000001000"); -- 256 +rf1_gsprg0_re <= (rf1_gsprg0_rdec or (rf1_sprg0_rdec and rf1_msr_gs_q)); +rf1_gsprg1_re <= (rf1_gsprg1_rdec or (rf1_sprg1_rdec and rf1_msr_gs_q)); +rf1_gsprg2_re <= (rf1_gsprg2_rdec or (rf1_sprg2_rdec and rf1_msr_gs_q)); +rf1_gsprg3_re <= (rf1_gsprg3_rdec or (rf1_sprg3_rdec and rf1_msr_gs_q)); +rf1_sprg0_re <= rf1_sprg0_rdec and not rf1_msr_gs_q; +rf1_sprg1_re <= rf1_sprg1_rdec and not rf1_msr_gs_q; +rf1_sprg2_re <= rf1_sprg2_rdec and not rf1_msr_gs_q; +rf1_sprg3_re <= rf1_sprg3_rdec and not rf1_msr_gs_q; +rf1_sprg4_re <= rf1_sprg4_rdec; +rf1_sprg5_re <= rf1_sprg5_rdec; +rf1_sprg6_re <= rf1_sprg6_rdec; +rf1_sprg7_re <= rf1_sprg7_rdec; +rf1_sprg8_re <= rf1_sprg8_rdec; +rf1_vrsave_re <= rf1_vrsave_rdec; + +rf1_aspr_re(1) <= rf1_is_mfspr and ( + rf1_gsprg0_re or rf1_gsprg1_re or rf1_gsprg2_re + or rf1_gsprg3_re or rf1_sprg0_re or rf1_sprg1_re + or rf1_sprg2_re or rf1_sprg3_re or rf1_sprg4_re + or rf1_sprg5_re or rf1_sprg6_re or rf1_sprg7_re + or rf1_sprg8_re or rf1_vrsave_re ); + +rf1_aspr_re0_gen : if regsize > 32 generate +rf1_aspr_re(0) <= rf1_aspr_re(1) and not ( + rf1_vrsave_re ); +end generate; + +rf1_aspr_addr <= + ("0000" and (0 to 3=> rf1_gsprg0_re )) or + ("0001" and (0 to 3=> rf1_gsprg1_re )) or + ("0010" and (0 to 3=> rf1_gsprg2_re )) or + ("0011" and (0 to 3=> rf1_gsprg3_re )) or + ("0100" and (0 to 3=> rf1_sprg0_re )) or + ("0101" and (0 to 3=> rf1_sprg1_re )) or + ("0110" and (0 to 3=> rf1_sprg2_re )) or + ("0111" and (0 to 3=> rf1_sprg3_re )) or + ("1000" and (0 to 3=> rf1_sprg4_re )) or + ("1001" and (0 to 3=> rf1_sprg5_re )) or + ("1010" and (0 to 3=> rf1_sprg6_re )) or + ("1011" and (0 to 3=> rf1_sprg7_re )) or + ("1100" and (0 to 3=> rf1_sprg8_re )) or + ("1101" and (0 to 3=> rf1_vrsave_re )); + +-- Array Writes + +-- Generate ECC +ex3_sprg_ue <= ex3_sprg_ue_q and ex3_aspr_re_q(0); +ex3_sprg_ce <= ex3_sprg_ce_q and ex3_aspr_re_q(0); +ex4_sprg_ce_d <= (others=>ex3_sprg_ce); + +ex4_inj_ecc <= or_reduce(inj_sprg_ecc_q and ex4_tid) and ex4_aspr_we_q and not ex4_sprg_ce_q(0); + +ex4_rt <= (ex4_corr_rdata_q and fanout(ex4_sprg_ce_q(0 to regsize/8-1),regsize)) or + (ex4_rt_q and not fanout(ex4_sprg_ce_q(0 to regsize/8-1),regsize)); + +ex4_rt_inj(63) <= ex4_rt(63) xor ex4_inj_ecc; +ex4_rt_inj(64-regsize to 62) <= ex4_rt(64-regsize to 62); + +ex4_eccgen_data <= ex4_rt & tidn(0 to 8-(64/regsize)); + +xuq_spr_wr_eccgen : entity work.xuq_eccgen(xuq_eccgen) +generic map(regsize => regsize) +port map(din => ex4_eccgen_data, + Syn => ex4_eccgen_syn); + +ex4_is_mfsspr_b <= not (ex4_sspr_val_q and ex4_is_mfspr_q); + +ex5_rt_d <= gate(ex4_rt_inj,ex4_is_mfsspr_b) & ex4_eccgen_syn; + +ex5_aspr_we_d <= dec_spr_ex4_val and not xu_ex4_flush and (0 to threads-1=>(ex4_aspr_we_q or ex4_sprg_ce_q(0))); + +ex3_aspr_we <= ex3_is_mtspr_q and ( + ex3_gsprg0_we or ex3_gsprg1_we or ex3_gsprg2_we + or ex3_gsprg3_we or ex3_sprg0_we or ex3_sprg1_we + or ex3_sprg2_we or ex3_sprg3_we or ex3_sprg4_we + or ex3_sprg5_we or ex3_sprg6_we or ex3_sprg7_we + or ex3_sprg8_we or ex3_vrsave_we ); + +ex3_gsprg0_wdec <= (ex3_instr(11 to 20) = "1000001011"); -- 368 +ex3_gsprg1_wdec <= (ex3_instr(11 to 20) = "1000101011"); -- 369 +ex3_gsprg2_wdec <= (ex3_instr(11 to 20) = "1001001011"); -- 370 +ex3_gsprg3_wdec <= (ex3_instr(11 to 20) = "1001101011"); -- 371 +ex3_sprg0_wdec <= (ex3_instr(11 to 20) = "1000001000"); -- 272 +ex3_sprg1_wdec <= (ex3_instr(11 to 20) = "1000101000"); -- 273 +ex3_sprg2_wdec <= (ex3_instr(11 to 20) = "1001001000"); -- 274 +ex3_sprg3_wdec <= ((ex3_instr(11 to 20) = "1001101000")); -- 275 +ex3_sprg4_wdec <= ((ex3_instr(11 to 20) = "1010001000")); -- 276 +ex3_sprg5_wdec <= ((ex3_instr(11 to 20) = "1010101000")); -- 277 +ex3_sprg6_wdec <= ((ex3_instr(11 to 20) = "1011001000")); -- 278 +ex3_sprg7_wdec <= ((ex3_instr(11 to 20) = "1011101000")); -- 279 +ex3_sprg8_wdec <= (ex3_instr(11 to 20) = "1110010010"); -- 604 +ex3_vrsave_wdec <= (ex3_instr(11 to 20) = "0000001000"); -- 256 +ex3_gsprg0_we <= (ex3_gsprg0_wdec or (ex3_sprg0_wdec and ex3_msr_gs_q)); +ex3_gsprg1_we <= (ex3_gsprg1_wdec or (ex3_sprg1_wdec and ex3_msr_gs_q)); +ex3_gsprg2_we <= (ex3_gsprg2_wdec or (ex3_sprg2_wdec and ex3_msr_gs_q)); +ex3_gsprg3_we <= (ex3_gsprg3_wdec or (ex3_sprg3_wdec and ex3_msr_gs_q)); +ex3_sprg0_we <= ex3_sprg0_wdec and not ex3_msr_gs_q; +ex3_sprg1_we <= ex3_sprg1_wdec and not ex3_msr_gs_q; +ex3_sprg2_we <= ex3_sprg2_wdec and not ex3_msr_gs_q; +ex3_sprg3_we <= ex3_sprg3_wdec and not ex3_msr_gs_q; +ex3_sprg4_we <= ex3_sprg4_wdec; +ex3_sprg5_we <= ex3_sprg5_wdec; +ex3_sprg6_we <= ex3_sprg6_wdec; +ex3_sprg7_we <= ex3_sprg7_wdec; +ex3_sprg8_we <= ex3_sprg8_wdec; +ex3_vrsave_we <= ex3_vrsave_wdec; +ex3_aspr_addr <= + ("0000" and (0 to 3=> ex3_gsprg0_we )) or + ("0001" and (0 to 3=> ex3_gsprg1_we )) or + ("0010" and (0 to 3=> ex3_gsprg2_we )) or + ("0011" and (0 to 3=> ex3_gsprg3_we )) or + ("0100" and (0 to 3=> ex3_sprg0_we )) or + ("0101" and (0 to 3=> ex3_sprg1_we )) or + ("0110" and (0 to 3=> ex3_sprg2_we )) or + ("0111" and (0 to 3=> ex3_sprg3_we )) or + ("1000" and (0 to 3=> ex3_sprg4_we )) or + ("1001" and (0 to 3=> ex3_sprg5_we )) or + ("1010" and (0 to 3=> ex3_sprg6_we )) or + ("1011" and (0 to 3=> ex3_sprg7_we )) or + ("1100" and (0 to 3=> ex3_sprg8_we )) or + ("1101" and (0 to 3=> ex3_vrsave_we )); + +with ex4_sprg_ce_q(regsize/8) select + ex5_aspr_addr_d <= ex4_aspr_ce_addr_q when '1', + ex4_aspr_addr_q when others; + +-- Slow SPR +ex2_dvc1_rdec <= (ex2_instr(11 to 20) = "1111001001"); -- 318 +ex2_dvc2_rdec <= (ex2_instr(11 to 20) = "1111101001"); -- 319 +ex2_eplc_rdec <= (ex2_instr(11 to 20) = "1001111101"); -- 947 +ex2_epsc_rdec <= (ex2_instr(11 to 20) = "1010011101"); -- 948 +ex2_eptcfg_rdec <= (ex2_instr(11 to 20) = "1111001010"); -- 350 +ex2_immr_rdec <= (ex2_instr(11 to 20) = "1000111011"); -- 881 +ex2_imr_rdec <= (ex2_instr(11 to 20) = "1000011011"); -- 880 +ex2_iucr0_rdec <= (ex2_instr(11 to 20) = "1001111111"); -- 1011 +ex2_iucr1_rdec <= (ex2_instr(11 to 20) = "1001111011"); -- 883 +ex2_iucr2_rdec <= (ex2_instr(11 to 20) = "1010011011"); -- 884 +ex2_iudbg0_rdec <= (ex2_instr(11 to 20) = "1100011011"); -- 888 +ex2_iudbg1_rdec <= (ex2_instr(11 to 20) = "1100111011"); -- 889 +ex2_iudbg2_rdec <= (ex2_instr(11 to 20) = "1101011011"); -- 890 +ex2_iulfsr_rdec <= (ex2_instr(11 to 20) = "1101111011"); -- 891 +ex2_iullcr_rdec <= (ex2_instr(11 to 20) = "1110011011"); -- 892 +ex2_lper_rdec <= (ex2_instr(11 to 20) = "1100000001"); -- 56 +ex2_lperu_rdec <= (ex2_instr(11 to 20) = "1100100001"); -- 57 +ex2_lpidr_rdec <= (ex2_instr(11 to 20) = "1001001010"); -- 338 +ex2_lratcfg_rdec <= (ex2_instr(11 to 20) = "1011001010"); -- 342 +ex2_lratps_rdec <= (ex2_instr(11 to 20) = "1011101010"); -- 343 +ex2_mas0_rdec <= (ex2_instr(11 to 20) = "1000010011"); -- 624 +ex2_mas0_mas1_rdec<= (ex2_instr(11 to 20) = "1010101011"); -- 373 +ex2_mas1_rdec <= (ex2_instr(11 to 20) = "1000110011"); -- 625 +ex2_mas2_rdec <= (ex2_instr(11 to 20) = "1001010011"); -- 626 +ex2_mas2u_rdec <= (ex2_instr(11 to 20) = "1011110011"); -- 631 +ex2_mas3_rdec <= (ex2_instr(11 to 20) = "1001110011"); -- 627 +ex2_mas4_rdec <= (ex2_instr(11 to 20) = "1010010011"); -- 628 +ex2_mas5_rdec <= (ex2_instr(11 to 20) = "1001101010"); -- 339 +ex2_mas5_mas6_rdec<= (ex2_instr(11 to 20) = "1110001010"); -- 348 +ex2_mas6_rdec <= (ex2_instr(11 to 20) = "1011010011"); -- 630 +ex2_mas7_rdec <= (ex2_instr(11 to 20) = "1000011101"); -- 944 +ex2_mas7_mas3_rdec<= (ex2_instr(11 to 20) = "1010001011"); -- 372 +ex2_mas8_rdec <= (ex2_instr(11 to 20) = "1010101010"); -- 341 +ex2_mas8_mas1_rdec<= (ex2_instr(11 to 20) = "1110101010"); -- 349 +ex2_mmucfg_rdec <= (ex2_instr(11 to 20) = "1011111111"); -- 1015 +ex2_mmucr0_rdec <= (ex2_instr(11 to 20) = "1110011111"); -- 1020 +ex2_mmucr1_rdec <= (ex2_instr(11 to 20) = "1110111111"); -- 1021 +ex2_mmucr2_rdec <= (ex2_instr(11 to 20) = "1111011111"); -- 1022 +ex2_mmucr3_rdec <= (ex2_instr(11 to 20) = "1111111111"); -- 1023 +ex2_mmucsr0_rdec <= (ex2_instr(11 to 20) = "1010011111"); -- 1012 +ex2_pid_rdec <= (ex2_instr(11 to 20) = "1000000001"); -- 48 +ex2_ppr32_rdec <= (ex2_instr(11 to 20) = "0001011100"); -- 898 +ex2_tlb0cfg_rdec <= (ex2_instr(11 to 20) = "1000010101"); -- 688 +ex2_tlb0ps_rdec <= (ex2_instr(11 to 20) = "1100001010"); -- 344 +ex2_xucr2_rdec <= (ex2_instr(11 to 20) = "1100011111"); -- 1016 +ex2_xudbg0_rdec <= (ex2_instr(11 to 20) = "1010111011"); -- 885 +ex2_xudbg1_rdec <= (ex2_instr(11 to 20) = "1011011011"); -- 886 +ex2_xudbg2_rdec <= (ex2_instr(11 to 20) = "1011111011"); -- 887 +ex2_dvc1_re <= ex2_dvc1_rdec; +ex2_dvc2_re <= ex2_dvc2_rdec; +ex2_eplc_re <= ex2_eplc_rdec; +ex2_epsc_re <= ex2_epsc_rdec; +ex2_eptcfg_re <= ex2_eptcfg_rdec; +ex2_immr_re <= ex2_immr_rdec; +ex2_imr_re <= ex2_imr_rdec; +ex2_iucr0_re <= ex2_iucr0_rdec; +ex2_iucr1_re <= ex2_iucr1_rdec; +ex2_iucr2_re <= ex2_iucr2_rdec; +ex2_iudbg0_re <= ex2_iudbg0_rdec; +ex2_iudbg1_re <= ex2_iudbg1_rdec; +ex2_iudbg2_re <= ex2_iudbg2_rdec; +ex2_iulfsr_re <= ex2_iulfsr_rdec; +ex2_iullcr_re <= ex2_iullcr_rdec; +ex2_lper_re <= ex2_lper_rdec; +ex2_lperu_re <= ex2_lperu_rdec; +ex2_lpidr_re <= ex2_lpidr_rdec; +ex2_lratcfg_re <= ex2_lratcfg_rdec; +ex2_lratps_re <= ex2_lratps_rdec; +ex2_mas0_re <= ex2_mas0_rdec; +ex2_mas0_mas1_re <= ex2_mas0_mas1_rdec; +ex2_mas1_re <= ex2_mas1_rdec; +ex2_mas2_re <= ex2_mas2_rdec; +ex2_mas2u_re <= ex2_mas2u_rdec; +ex2_mas3_re <= ex2_mas3_rdec; +ex2_mas4_re <= ex2_mas4_rdec; +ex2_mas5_re <= ex2_mas5_rdec; +ex2_mas5_mas6_re <= ex2_mas5_mas6_rdec; +ex2_mas6_re <= ex2_mas6_rdec; +ex2_mas7_re <= ex2_mas7_rdec; +ex2_mas7_mas3_re <= ex2_mas7_mas3_rdec; +ex2_mas8_re <= ex2_mas8_rdec; +ex2_mas8_mas1_re <= ex2_mas8_mas1_rdec; +ex2_mmucfg_re <= ex2_mmucfg_rdec; +ex2_mmucr0_re <= ex2_mmucr0_rdec; +ex2_mmucr1_re <= ex2_mmucr1_rdec; +ex2_mmucr2_re <= ex2_mmucr2_rdec; +ex2_mmucr3_re <= ex2_mmucr3_rdec; +ex2_mmucsr0_re <= ex2_mmucsr0_rdec; +ex2_pid_re <= ex2_pid_rdec; +ex2_ppr32_re <= ex2_ppr32_rdec; +ex2_tlb0cfg_re <= ex2_tlb0cfg_rdec; +ex2_tlb0ps_re <= ex2_tlb0ps_rdec; +ex2_xucr2_re <= ex2_xucr2_rdec; +ex2_xudbg0_re <= ex2_xudbg0_rdec; +ex2_xudbg1_re <= ex2_xudbg1_rdec; +ex2_xudbg2_re <= ex2_xudbg2_rdec; +ex2_dvc1_wdec <= ex2_dvc1_rdec; +ex2_dvc2_wdec <= ex2_dvc2_rdec; +ex2_eplc_wdec <= ex2_eplc_rdec; +ex2_epsc_wdec <= ex2_epsc_rdec; +ex2_immr_wdec <= ex2_immr_rdec; +ex2_imr_wdec <= ex2_imr_rdec; +ex2_iucr0_wdec <= ex2_iucr0_rdec; +ex2_iucr1_wdec <= ex2_iucr1_rdec; +ex2_iucr2_wdec <= ex2_iucr2_rdec; +ex2_iudbg0_wdec <= ex2_iudbg0_rdec; +ex2_iulfsr_wdec <= ex2_iulfsr_rdec; +ex2_iullcr_wdec <= ex2_iullcr_rdec; +ex2_lper_wdec <= ex2_lper_rdec; +ex2_lperu_wdec <= ex2_lperu_rdec; +ex2_lpidr_wdec <= ex2_lpidr_rdec; +ex2_mas0_wdec <= ex2_mas0_rdec; +ex2_mas0_mas1_wdec<= ex2_mas0_mas1_rdec; +ex2_mas1_wdec <= ex2_mas1_rdec; +ex2_mas2_wdec <= ex2_mas2_rdec; +ex2_mas2u_wdec <= ex2_mas2u_rdec; +ex2_mas3_wdec <= ex2_mas3_rdec; +ex2_mas4_wdec <= ex2_mas4_rdec; +ex2_mas5_wdec <= ex2_mas5_rdec; +ex2_mas5_mas6_wdec<= ex2_mas5_mas6_rdec; +ex2_mas6_wdec <= ex2_mas6_rdec; +ex2_mas7_wdec <= ex2_mas7_rdec; +ex2_mas7_mas3_wdec<= ex2_mas7_mas3_rdec; +ex2_mas8_wdec <= ex2_mas8_rdec; +ex2_mas8_mas1_wdec<= ex2_mas8_mas1_rdec; +ex2_mmucr0_wdec <= ex2_mmucr0_rdec; +ex2_mmucr1_wdec <= ex2_mmucr1_rdec; +ex2_mmucr2_wdec <= ex2_mmucr2_rdec; +ex2_mmucr3_wdec <= ex2_mmucr3_rdec; +ex2_mmucsr0_wdec <= ex2_mmucsr0_rdec; +ex2_pid_wdec <= ex2_pid_rdec; +ex2_ppr32_wdec <= ex2_ppr32_rdec; +ex2_xucr2_wdec <= ex2_xucr2_rdec; +ex2_xudbg0_wdec <= ex2_xudbg0_rdec; +ex2_dvc1_we <= ex2_dvc1_wdec; +ex2_dvc2_we <= ex2_dvc2_wdec; +ex2_eplc_we <= ex2_eplc_wdec; +ex2_epsc_we <= ex2_epsc_wdec; +ex2_immr_we <= ex2_immr_wdec; +ex2_imr_we <= ex2_imr_wdec; +ex2_iucr0_we <= ex2_iucr0_wdec; +ex2_iucr1_we <= ex2_iucr1_wdec; +ex2_iucr2_we <= ex2_iucr2_wdec; +ex2_iudbg0_we <= ex2_iudbg0_wdec; +ex2_iulfsr_we <= ex2_iulfsr_wdec; +ex2_iullcr_we <= ex2_iullcr_wdec; +ex2_lper_we <= ex2_lper_wdec; +ex2_lperu_we <= ex2_lperu_wdec; +ex2_lpidr_we <= ex2_lpidr_wdec; +ex2_mas0_we <= ex2_mas0_wdec; +ex2_mas0_mas1_we <= ex2_mas0_mas1_wdec; +ex2_mas1_we <= ex2_mas1_wdec; +ex2_mas2_we <= ex2_mas2_wdec; +ex2_mas2u_we <= ex2_mas2u_wdec; +ex2_mas3_we <= ex2_mas3_wdec; +ex2_mas4_we <= ex2_mas4_wdec; +ex2_mas5_we <= ex2_mas5_wdec; +ex2_mas5_mas6_we <= ex2_mas5_mas6_wdec; +ex2_mas6_we <= ex2_mas6_wdec; +ex2_mas7_we <= ex2_mas7_wdec; +ex2_mas7_mas3_we <= ex2_mas7_mas3_wdec; +ex2_mas8_we <= ex2_mas8_wdec; +ex2_mas8_mas1_we <= ex2_mas8_mas1_wdec; +ex2_mmucr0_we <= ex2_mmucr0_wdec; +ex2_mmucr1_we <= ex2_mmucr1_wdec; +ex2_mmucr2_we <= ex2_mmucr2_wdec; +ex2_mmucr3_we <= ex2_mmucr3_wdec; +ex2_mmucsr0_we <= ex2_mmucsr0_wdec; +ex2_pid_we <= ex2_pid_wdec; +ex2_ppr32_we <= ex2_ppr32_wdec; +ex2_xucr2_we <= ex2_xucr2_wdec; +ex2_xudbg0_we <= ex2_xudbg0_wdec; +ex2_slowspr_range_hypv <= ex2_instr(11) and ex2_instr(16 to 20) = "11110"; -- 976-991 +ex2_slowspr_range_priv <= ex2_instr(11) and ex2_instr(16 to 20) = "11100"; -- 912-927 +ex2_slowspr_range <= ex2_slowspr_range_priv or ex2_slowspr_range_hypv; + +-- mftb encode is only legal for tbr=268,269 -- "0110-01000" +ex2_illeg_mftb <= ex2_is_mftb_q and not (ex2_instr(11 to 14) = "0110" and + ex2_instr(16 to 20) = "01000"); + +ex2_sspr_val <=(ex2_is_mtspr_q and (ex2_slowspr_range or + ex2_dvc1_we or ex2_dvc2_we or ex2_eplc_we + or ex2_epsc_we or ex2_immr_we or ex2_imr_we + or ex2_iucr0_we or ex2_iucr1_we or ex2_iucr2_we + or ex2_iudbg0_we or ex2_iulfsr_we or ex2_iullcr_we + or ex2_lper_we or ex2_lperu_we or ex2_lpidr_we + or ex2_mas0_we or ex2_mas0_mas1_we or ex2_mas1_we + or ex2_mas2_we or ex2_mas2u_we or ex2_mas3_we + or ex2_mas4_we or ex2_mas5_we or ex2_mas5_mas6_we + or ex2_mas6_we or ex2_mas7_we or ex2_mas7_mas3_we + or ex2_mas8_we or ex2_mas8_mas1_we or ex2_mmucr0_we + or ex2_mmucr1_we or ex2_mmucr2_we or ex2_mmucr3_we + or ex2_mmucsr0_we or ex2_pid_we or ex2_ppr32_we + or ex2_xucr2_we or ex2_xudbg0_we )) or + (ex2_is_mfspr_q and (ex2_slowspr_range or + ex2_dvc1_re or ex2_dvc2_re or ex2_eplc_re + or ex2_epsc_re or ex2_eptcfg_re or ex2_immr_re + or ex2_imr_re or ex2_iucr0_re or ex2_iucr1_re + or ex2_iucr2_re or ex2_iudbg0_re or ex2_iudbg1_re + or ex2_iudbg2_re or ex2_iulfsr_re or ex2_iullcr_re + or ex2_lper_re or ex2_lperu_re or ex2_lpidr_re + or ex2_lratcfg_re or ex2_lratps_re or ex2_mas0_re + or ex2_mas0_mas1_re or ex2_mas1_re or ex2_mas2_re + or ex2_mas2u_re or ex2_mas3_re or ex2_mas4_re + or ex2_mas5_re or ex2_mas5_mas6_re or ex2_mas6_re + or ex2_mas7_re or ex2_mas7_mas3_re or ex2_mas8_re + or ex2_mas8_mas1_re or ex2_mmucfg_re or ex2_mmucr0_re + or ex2_mmucr1_re or ex2_mmucr2_re or ex2_mmucr3_re + or ex2_mmucsr0_re or ex2_pid_re or ex2_ppr32_re + or ex2_tlb0cfg_re or ex2_tlb0ps_re or ex2_xucr2_re + or ex2_xudbg0_re or ex2_xudbg1_re or ex2_xudbg2_re )); + +-- Illegal SPR checks +ex2_gsprg0_rdec <= (ex2_instr(11 to 20) = "1000001011"); -- 368 +ex2_gsprg1_rdec <= (ex2_instr(11 to 20) = "1000101011"); -- 369 +ex2_gsprg2_rdec <= (ex2_instr(11 to 20) = "1001001011"); -- 370 +ex2_gsprg3_rdec <= (ex2_instr(11 to 20) = "1001101011"); -- 371 +ex2_sprg0_rdec <= (ex2_instr(11 to 20) = "1000001000"); -- 272 +ex2_sprg1_rdec <= (ex2_instr(11 to 20) = "1000101000"); -- 273 +ex2_sprg2_rdec <= (ex2_instr(11 to 20) = "1001001000"); -- 274 +ex2_sprg3_rdec <= ((ex2_instr(11 to 20) = "1001101000") or -- 275 + (ex2_instr(11 to 20) = "0001101000")); -- 259 +ex2_sprg4_rdec <= ((ex2_instr(11 to 20) = "1010001000") or -- 276 + (ex2_instr(11 to 20) = "0010001000")); -- 260 +ex2_sprg5_rdec <= ((ex2_instr(11 to 20) = "1010101000") or -- 277 + (ex2_instr(11 to 20) = "0010101000")); -- 261 +ex2_sprg6_rdec <= ((ex2_instr(11 to 20) = "1011001000") or -- 278 + (ex2_instr(11 to 20) = "0011001000")); -- 262 +ex2_sprg7_rdec <= ((ex2_instr(11 to 20) = "1011101000") or -- 279 + (ex2_instr(11 to 20) = "0011101000")); -- 263 +ex2_sprg8_rdec <= (ex2_instr(11 to 20) = "1110010010"); -- 604 +ex2_vrsave_rdec <= (ex2_instr(11 to 20) = "0000001000"); -- 256 +ex2_gsprg0_wdec <= (ex2_instr(11 to 20) = "1000001011"); -- 368 +ex2_gsprg1_wdec <= (ex2_instr(11 to 20) = "1000101011"); -- 369 +ex2_gsprg2_wdec <= (ex2_instr(11 to 20) = "1001001011"); -- 370 +ex2_gsprg3_wdec <= (ex2_instr(11 to 20) = "1001101011"); -- 371 +ex2_sprg0_wdec <= (ex2_instr(11 to 20) = "1000001000"); -- 272 +ex2_sprg1_wdec <= (ex2_instr(11 to 20) = "1000101000"); -- 273 +ex2_sprg2_wdec <= (ex2_instr(11 to 20) = "1001001000"); -- 274 +ex2_sprg3_wdec <= ((ex2_instr(11 to 20) = "1001101000")); -- 275 +ex2_sprg4_wdec <= ((ex2_instr(11 to 20) = "1010001000")); -- 276 +ex2_sprg5_wdec <= ((ex2_instr(11 to 20) = "1010101000")); -- 277 +ex2_sprg6_wdec <= ((ex2_instr(11 to 20) = "1011001000")); -- 278 +ex2_sprg7_wdec <= ((ex2_instr(11 to 20) = "1011101000")); -- 279 +ex2_sprg8_wdec <= (ex2_instr(11 to 20) = "1110010010"); -- 604 +ex2_vrsave_wdec <= (ex2_instr(11 to 20) = "0000001000"); -- 256 +ex2_sprg8_re <= ex2_sprg8_rdec; +ex2_sprg8_we <= ex2_sprg8_wdec; +ex2_ccr0_wdec <= ex2_ccr0_rdec; +ex2_ccr1_wdec <= ex2_ccr1_rdec; +ex2_ccr2_wdec <= ex2_ccr2_rdec; +ex2_dac1_wdec <= ex2_dac1_rdec; +ex2_dac2_wdec <= ex2_dac2_rdec; +ex2_dac3_wdec <= ex2_dac3_rdec; +ex2_dac4_wdec <= ex2_dac4_rdec; +ex2_givpr_wdec <= (ex2_instr(11 to 20) = "1111101101"); -- 447 +ex2_iac1_wdec <= ex2_iac1_rdec; +ex2_iac2_wdec <= ex2_iac2_rdec; +ex2_iac3_wdec <= ex2_iac3_rdec; +ex2_iac4_wdec <= ex2_iac4_rdec; +ex2_ivpr_wdec <= ex2_ivpr_rdec; +ex2_tbl_wdec <= (ex2_instr(11 to 20) = "1110001000"); -- 284 +ex2_tbu_wdec <= ((ex2_instr(11 to 20) = "1110101000")); -- 285 +ex2_tenc_wdec <= ex2_tenc_rdec; +ex2_tens_wdec <= ex2_tens_rdec; +ex2_trace_wdec <= (ex2_instr(11 to 20) = "0111011111"); -- 1006 +ex2_xucr0_wdec <= ex2_xucr0_rdec; +ex2_xucr3_wdec <= ex2_xucr3_rdec; +ex2_xucr4_wdec <= ex2_xucr4_rdec; +ex2_ccr0_we <= ex2_ccr0_wdec; +ex2_ccr1_we <= ex2_ccr1_wdec; +ex2_ccr2_we <= ex2_ccr2_wdec; +ex2_dac1_we <= ex2_dac1_wdec; +ex2_dac2_we <= ex2_dac2_wdec; +ex2_dac3_we <= ex2_dac3_wdec; +ex2_dac4_we <= ex2_dac4_wdec; +ex2_givpr_we <= ex2_givpr_wdec; +ex2_iac1_we <= ex2_iac1_wdec; +ex2_iac2_we <= ex2_iac2_wdec; +ex2_iac3_we <= ex2_iac3_wdec; +ex2_iac4_we <= ex2_iac4_wdec; +ex2_ivpr_we <= ex2_ivpr_wdec; +ex2_tbl_we <= ex2_tbl_wdec; +ex2_tbu_we <= ex2_tbu_wdec; +ex2_tenc_we <= ex2_tenc_wdec; +ex2_tens_we <= ex2_tens_wdec; +ex2_trace_we <= ex2_trace_wdec; +ex2_xucr0_we <= ex2_xucr0_wdec; +ex2_xucr3_we <= ex2_xucr3_wdec; +ex2_xucr4_we <= ex2_xucr4_wdec; + + +ill_spr_00 : if a2mode = 0 and hvmode = 0 generate +ex2_illeg_mfspr <= ex2_is_mfspr_q and not ( + ex2_ccr0_rdec or ex2_ccr1_rdec or ex2_ccr2_rdec + or ex2_dac3_rdec or ex2_dac4_rdec or ex2_iac1_rdec + or ex2_iac2_rdec or ex2_ivpr_rdec or ex2_pir_rdec + or ex2_pvr_rdec or ex2_tb_rdec or ex2_tbu_rdec + or ex2_tenc_rdec or ex2_tens_rdec or ex2_tensr_rdec + or ex2_tir_rdec or ex2_xucr0_rdec or ex2_xucr3_rdec + or ex2_xucr4_rdec or + ex2_sprg0_rdec or ex2_sprg1_rdec or ex2_sprg2_rdec + or ex2_sprg3_rdec or ex2_sprg4_rdec or ex2_sprg5_rdec + or ex2_sprg6_rdec or ex2_sprg7_rdec or ex2_sprg8_rdec + or ex2_vrsave_rdec or + ex2_iucr0_rdec or ex2_iucr1_rdec or ex2_iucr2_rdec + or ex2_iudbg0_rdec or ex2_iudbg1_rdec or ex2_iudbg2_rdec + or ex2_iulfsr_rdec or ex2_iullcr_rdec or ex2_lpidr_rdec + or ex2_pid_rdec or ex2_ppr32_rdec or ex2_xucr2_rdec + or ex2_xudbg0_rdec or ex2_xudbg1_rdec or ex2_xudbg2_rdec or + ex2_slowspr_range or + or_reduce(tspr_cspr_illeg_mfspr_b and ex2_tid)); + +ex2_illeg_mtspr <= ex2_is_mtspr_q and not ( + ex2_ccr0_wdec or ex2_ccr1_wdec or ex2_ccr2_wdec + or ex2_dac3_wdec or ex2_dac4_wdec or ex2_iac1_wdec + or ex2_iac2_wdec or ex2_ivpr_wdec or ex2_tbl_wdec + or ex2_tbu_wdec or ex2_tenc_wdec or ex2_tens_wdec + or ex2_trace_wdec or ex2_xucr0_wdec or ex2_xucr3_wdec + or ex2_xucr4_wdec or + ex2_sprg0_wdec or ex2_sprg1_wdec or ex2_sprg2_wdec + or ex2_sprg3_wdec or ex2_sprg4_wdec or ex2_sprg5_wdec + or ex2_sprg6_wdec or ex2_sprg7_wdec or ex2_sprg8_wdec + or ex2_vrsave_wdec or + ex2_iucr0_wdec or ex2_iucr1_wdec or ex2_iucr2_wdec + or ex2_iudbg0_wdec or ex2_iulfsr_wdec or ex2_iullcr_wdec + or ex2_lpidr_wdec or ex2_pid_wdec or ex2_ppr32_wdec + or ex2_xucr2_wdec or ex2_xudbg0_wdec or + ex2_slowspr_range or + or_reduce(tspr_cspr_illeg_mtspr_b and ex2_tid)); + +ex2_hypv_mfspr <= ex2_is_mfspr_q and ( + ex2_ccr0_re or ex2_ccr1_re or ex2_ccr2_re + or ex2_dac3_re or ex2_dac4_re or ex2_iac1_re + or ex2_iac2_re or ex2_ivpr_re or ex2_tenc_re + or ex2_tens_re or ex2_tensr_re or ex2_tir_re + or ex2_xucr0_re or ex2_xucr3_re or ex2_xucr4_re or + ex2_sprg8_re or + ex2_iucr0_re or ex2_iucr1_re or ex2_iucr2_re + or ex2_iudbg0_re or ex2_iudbg1_re or ex2_iudbg2_re + or ex2_iulfsr_re or ex2_iullcr_re or ex2_lpidr_re + or ex2_xucr2_re or ex2_xudbg0_re or ex2_xudbg1_re + or ex2_xudbg2_re or + ex2_slowspr_range_hypv or + or_reduce(tspr_cspr_hypv_mfspr and ex2_tid)); + +ex2_hypv_mtspr <= ex2_is_mtspr_q and ( + ex2_ccr0_we or ex2_ccr1_we or ex2_ccr2_we + or ex2_dac3_we or ex2_dac4_we or ex2_iac1_we + or ex2_iac2_we or ex2_ivpr_we or ex2_tbl_we + or ex2_tbu_we or ex2_tenc_we or ex2_tens_we + or ex2_xucr0_we or ex2_xucr3_we or ex2_xucr4_we or + ex2_sprg8_we or + ex2_iucr0_we or ex2_iucr1_we or ex2_iucr2_we + or ex2_iudbg0_we or ex2_iulfsr_we or ex2_iullcr_we + or ex2_lpidr_we or ex2_xucr2_we or ex2_xudbg0_we or + ex2_slowspr_range_hypv or + or_reduce(tspr_cspr_hypv_mtspr and ex2_tid)); + +end generate; +ill_spr_01 : if a2mode = 0 and hvmode = 1 generate +ex2_illeg_mfspr <= ex2_is_mfspr_q and not ( + ex2_ccr0_rdec or ex2_ccr1_rdec or ex2_ccr2_rdec + or ex2_dac3_rdec or ex2_dac4_rdec or ex2_givpr_rdec + or ex2_iac1_rdec or ex2_iac2_rdec or ex2_ivpr_rdec + or ex2_pir_rdec or ex2_pvr_rdec or ex2_tb_rdec + or ex2_tbu_rdec or ex2_tenc_rdec or ex2_tens_rdec + or ex2_tensr_rdec or ex2_tir_rdec or ex2_xucr0_rdec + or ex2_xucr3_rdec or ex2_xucr4_rdec or + ex2_gsprg0_rdec or ex2_gsprg1_rdec or ex2_gsprg2_rdec + or ex2_gsprg3_rdec or ex2_sprg0_rdec or ex2_sprg1_rdec + or ex2_sprg2_rdec or ex2_sprg3_rdec or ex2_sprg4_rdec + or ex2_sprg5_rdec or ex2_sprg6_rdec or ex2_sprg7_rdec + or ex2_sprg8_rdec or ex2_vrsave_rdec or + ex2_eplc_rdec or ex2_epsc_rdec or ex2_eptcfg_rdec + or ex2_iucr0_rdec or ex2_iucr1_rdec or ex2_iucr2_rdec + or ex2_iudbg0_rdec or ex2_iudbg1_rdec or ex2_iudbg2_rdec + or ex2_iulfsr_rdec or ex2_iullcr_rdec or ex2_lper_rdec + or ex2_lperu_rdec or ex2_lpidr_rdec or ex2_lratcfg_rdec + or ex2_lratps_rdec or ex2_mas0_rdec or ex2_mas0_mas1_rdec + or ex2_mas1_rdec or ex2_mas2_rdec or ex2_mas2u_rdec + or ex2_mas3_rdec or ex2_mas4_rdec or ex2_mas5_rdec + or ex2_mas5_mas6_rdec or ex2_mas6_rdec or ex2_mas7_rdec + or ex2_mas7_mas3_rdec or ex2_mas8_rdec or ex2_mas8_mas1_rdec + or ex2_mmucfg_rdec or ex2_mmucr3_rdec or ex2_mmucsr0_rdec + or ex2_pid_rdec or ex2_ppr32_rdec or ex2_tlb0cfg_rdec + or ex2_tlb0ps_rdec or ex2_xucr2_rdec or ex2_xudbg0_rdec + or ex2_xudbg1_rdec or ex2_xudbg2_rdec or + ex2_slowspr_range or + or_reduce(tspr_cspr_illeg_mfspr_b and ex2_tid)); + +ex2_illeg_mtspr <= ex2_is_mtspr_q and not ( + ex2_ccr0_wdec or ex2_ccr1_wdec or ex2_ccr2_wdec + or ex2_dac3_wdec or ex2_dac4_wdec or ex2_givpr_wdec + or ex2_iac1_wdec or ex2_iac2_wdec or ex2_ivpr_wdec + or ex2_tbl_wdec or ex2_tbu_wdec or ex2_tenc_wdec + or ex2_tens_wdec or ex2_trace_wdec or ex2_xucr0_wdec + or ex2_xucr3_wdec or ex2_xucr4_wdec or + ex2_gsprg0_wdec or ex2_gsprg1_wdec or ex2_gsprg2_wdec + or ex2_gsprg3_wdec or ex2_sprg0_wdec or ex2_sprg1_wdec + or ex2_sprg2_wdec or ex2_sprg3_wdec or ex2_sprg4_wdec + or ex2_sprg5_wdec or ex2_sprg6_wdec or ex2_sprg7_wdec + or ex2_sprg8_wdec or ex2_vrsave_wdec or + ex2_eplc_wdec or ex2_epsc_wdec or ex2_iucr0_wdec + or ex2_iucr1_wdec or ex2_iucr2_wdec or ex2_iudbg0_wdec + or ex2_iulfsr_wdec or ex2_iullcr_wdec or ex2_lper_wdec + or ex2_lperu_wdec or ex2_lpidr_wdec or ex2_mas0_wdec + or ex2_mas0_mas1_wdec or ex2_mas1_wdec or ex2_mas2_wdec + or ex2_mas2u_wdec or ex2_mas3_wdec or ex2_mas4_wdec + or ex2_mas5_wdec or ex2_mas5_mas6_wdec or ex2_mas6_wdec + or ex2_mas7_wdec or ex2_mas7_mas3_wdec or ex2_mas8_wdec + or ex2_mas8_mas1_wdec or ex2_mmucr3_wdec or ex2_mmucsr0_wdec + or ex2_pid_wdec or ex2_ppr32_wdec or ex2_xucr2_wdec + or ex2_xudbg0_wdec or + ex2_slowspr_range or + or_reduce(tspr_cspr_illeg_mtspr_b and ex2_tid)); + +ex2_hypv_mfspr <= ex2_is_mfspr_q and ( + ex2_ccr0_re or ex2_ccr1_re or ex2_ccr2_re + or ex2_dac3_re or ex2_dac4_re or ex2_iac1_re + or ex2_iac2_re or ex2_ivpr_re or ex2_tenc_re + or ex2_tens_re or ex2_tensr_re or ex2_tir_re + or ex2_xucr0_re or ex2_xucr3_re or ex2_xucr4_re or + ex2_sprg8_re or + ex2_eptcfg_re or ex2_iucr0_re or ex2_iucr1_re + or ex2_iucr2_re or ex2_iudbg0_re or ex2_iudbg1_re + or ex2_iudbg2_re or ex2_iulfsr_re or ex2_iullcr_re + or ex2_lper_re or ex2_lperu_re or ex2_lpidr_re + or ex2_lratcfg_re or ex2_lratps_re or ex2_mas5_re + or ex2_mas5_mas6_re or ex2_mas8_re or ex2_mas8_mas1_re + or ex2_mmucfg_re or ex2_mmucsr0_re or ex2_tlb0cfg_re + or ex2_tlb0ps_re or ex2_xucr2_re or ex2_xudbg0_re + or ex2_xudbg1_re or ex2_xudbg2_re or + ex2_slowspr_range_hypv or + or_reduce(tspr_cspr_hypv_mfspr and ex2_tid)); + +ex2_hypv_mtspr <= ex2_is_mtspr_q and ( + ex2_ccr0_we or ex2_ccr1_we or ex2_ccr2_we + or ex2_dac3_we or ex2_dac4_we or ex2_givpr_we + or ex2_iac1_we or ex2_iac2_we or ex2_ivpr_we + or ex2_tbl_we or ex2_tbu_we or ex2_tenc_we + or ex2_tens_we or ex2_xucr0_we or ex2_xucr3_we + or ex2_xucr4_we or + ex2_sprg8_we or + ex2_iucr0_we or ex2_iucr1_we or ex2_iucr2_we + or ex2_iudbg0_we or ex2_iulfsr_we or ex2_iullcr_we + or ex2_lper_we or ex2_lperu_we or ex2_lpidr_we + or ex2_mas5_we or ex2_mas5_mas6_we or ex2_mas8_we + or ex2_mas8_mas1_we or ex2_mmucsr0_we or ex2_xucr2_we + or ex2_xudbg0_we or + ex2_slowspr_range_hypv or + or_reduce(tspr_cspr_hypv_mtspr and ex2_tid)); + +end generate; +ill_spr_10 : if a2mode = 1 and hvmode = 0 generate +ex2_illeg_mfspr <= ex2_is_mfspr_q and not ( + ex2_ccr0_rdec or ex2_ccr1_rdec or ex2_ccr2_rdec + or ex2_dac1_rdec or ex2_dac2_rdec or ex2_dac3_rdec + or ex2_dac4_rdec or ex2_iac1_rdec or ex2_iac2_rdec + or ex2_iac3_rdec or ex2_iac4_rdec or ex2_ivpr_rdec + or ex2_pir_rdec or ex2_pvr_rdec or ex2_tb_rdec + or ex2_tbu_rdec or ex2_tenc_rdec or ex2_tens_rdec + or ex2_tensr_rdec or ex2_tir_rdec or ex2_xucr0_rdec + or ex2_xucr3_rdec or ex2_xucr4_rdec or + ex2_sprg0_rdec or ex2_sprg1_rdec or ex2_sprg2_rdec + or ex2_sprg3_rdec or ex2_sprg4_rdec or ex2_sprg5_rdec + or ex2_sprg6_rdec or ex2_sprg7_rdec or ex2_sprg8_rdec + or ex2_vrsave_rdec or + ex2_dvc1_rdec or ex2_dvc2_rdec or ex2_immr_rdec + or ex2_imr_rdec or ex2_iucr0_rdec or ex2_iucr1_rdec + or ex2_iucr2_rdec or ex2_iudbg0_rdec or ex2_iudbg1_rdec + or ex2_iudbg2_rdec or ex2_iulfsr_rdec or ex2_iullcr_rdec + or ex2_lpidr_rdec or ex2_mmucr0_rdec or ex2_mmucr1_rdec + or ex2_mmucr2_rdec or ex2_pid_rdec or ex2_ppr32_rdec + or ex2_xucr2_rdec or ex2_xudbg0_rdec or ex2_xudbg1_rdec + or ex2_xudbg2_rdec or + ex2_slowspr_range or + or_reduce(tspr_cspr_illeg_mfspr_b and ex2_tid)); + +ex2_illeg_mtspr <= ex2_is_mtspr_q and not ( + ex2_ccr0_wdec or ex2_ccr1_wdec or ex2_ccr2_wdec + or ex2_dac1_wdec or ex2_dac2_wdec or ex2_dac3_wdec + or ex2_dac4_wdec or ex2_iac1_wdec or ex2_iac2_wdec + or ex2_iac3_wdec or ex2_iac4_wdec or ex2_ivpr_wdec + or ex2_tbl_wdec or ex2_tbu_wdec or ex2_tenc_wdec + or ex2_tens_wdec or ex2_trace_wdec or ex2_xucr0_wdec + or ex2_xucr3_wdec or ex2_xucr4_wdec or + ex2_sprg0_wdec or ex2_sprg1_wdec or ex2_sprg2_wdec + or ex2_sprg3_wdec or ex2_sprg4_wdec or ex2_sprg5_wdec + or ex2_sprg6_wdec or ex2_sprg7_wdec or ex2_sprg8_wdec + or ex2_vrsave_wdec or + ex2_dvc1_wdec or ex2_dvc2_wdec or ex2_immr_wdec + or ex2_imr_wdec or ex2_iucr0_wdec or ex2_iucr1_wdec + or ex2_iucr2_wdec or ex2_iudbg0_wdec or ex2_iulfsr_wdec + or ex2_iullcr_wdec or ex2_lpidr_wdec or ex2_mmucr0_wdec + or ex2_mmucr1_wdec or ex2_mmucr2_wdec or ex2_pid_wdec + or ex2_ppr32_wdec or ex2_xucr2_wdec or ex2_xudbg0_wdec or + ex2_slowspr_range or + or_reduce(tspr_cspr_illeg_mtspr_b and ex2_tid)); + +ex2_hypv_mfspr <= ex2_is_mfspr_q and ( + ex2_ccr0_re or ex2_ccr1_re or ex2_ccr2_re + or ex2_dac1_re or ex2_dac2_re or ex2_dac3_re + or ex2_dac4_re or ex2_iac1_re or ex2_iac2_re + or ex2_iac3_re or ex2_iac4_re or ex2_ivpr_re + or ex2_tenc_re or ex2_tens_re or ex2_tensr_re + or ex2_tir_re or ex2_xucr0_re or ex2_xucr3_re + or ex2_xucr4_re or + ex2_sprg8_re or + ex2_dvc1_re or ex2_dvc2_re or ex2_immr_re + or ex2_imr_re or ex2_iucr0_re or ex2_iucr1_re + or ex2_iucr2_re or ex2_iudbg0_re or ex2_iudbg1_re + or ex2_iudbg2_re or ex2_iulfsr_re or ex2_iullcr_re + or ex2_lpidr_re or ex2_mmucr0_re or ex2_mmucr1_re + or ex2_mmucr2_re or ex2_xucr2_re or ex2_xudbg0_re + or ex2_xudbg1_re or ex2_xudbg2_re or + ex2_slowspr_range_hypv or + or_reduce(tspr_cspr_hypv_mfspr and ex2_tid)); + +ex2_hypv_mtspr <= ex2_is_mtspr_q and ( + ex2_ccr0_we or ex2_ccr1_we or ex2_ccr2_we + or ex2_dac1_we or ex2_dac2_we or ex2_dac3_we + or ex2_dac4_we or ex2_iac1_we or ex2_iac2_we + or ex2_iac3_we or ex2_iac4_we or ex2_ivpr_we + or ex2_tbl_we or ex2_tbu_we or ex2_tenc_we + or ex2_tens_we or ex2_xucr0_we or ex2_xucr3_we + or ex2_xucr4_we or + ex2_sprg8_we or + ex2_dvc1_we or ex2_dvc2_we or ex2_immr_we + or ex2_imr_we or ex2_iucr0_we or ex2_iucr1_we + or ex2_iucr2_we or ex2_iudbg0_we or ex2_iulfsr_we + or ex2_iullcr_we or ex2_lpidr_we or ex2_mmucr0_we + or ex2_mmucr1_we or ex2_mmucr2_we or ex2_xucr2_we + or ex2_xudbg0_we or + ex2_slowspr_range_hypv or + or_reduce(tspr_cspr_hypv_mtspr and ex2_tid)); + +end generate; +ill_spr_11 : if a2mode = 1 and hvmode = 1 generate +ex2_illeg_mfspr <= ex2_is_mfspr_q and not ( + ex2_ccr0_rdec or ex2_ccr1_rdec or ex2_ccr2_rdec + or ex2_dac1_rdec or ex2_dac2_rdec or ex2_dac3_rdec + or ex2_dac4_rdec or ex2_givpr_rdec or ex2_iac1_rdec + or ex2_iac2_rdec or ex2_iac3_rdec or ex2_iac4_rdec + or ex2_ivpr_rdec or ex2_pir_rdec or ex2_pvr_rdec + or ex2_tb_rdec or ex2_tbu_rdec or ex2_tenc_rdec + or ex2_tens_rdec or ex2_tensr_rdec or ex2_tir_rdec + or ex2_xucr0_rdec or ex2_xucr3_rdec or ex2_xucr4_rdec or + ex2_gsprg0_rdec or ex2_gsprg1_rdec or ex2_gsprg2_rdec + or ex2_gsprg3_rdec or ex2_sprg0_rdec or ex2_sprg1_rdec + or ex2_sprg2_rdec or ex2_sprg3_rdec or ex2_sprg4_rdec + or ex2_sprg5_rdec or ex2_sprg6_rdec or ex2_sprg7_rdec + or ex2_sprg8_rdec or ex2_vrsave_rdec or + ex2_dvc1_rdec or ex2_dvc2_rdec or ex2_eplc_rdec + or ex2_epsc_rdec or ex2_eptcfg_rdec or ex2_immr_rdec + or ex2_imr_rdec or ex2_iucr0_rdec or ex2_iucr1_rdec + or ex2_iucr2_rdec or ex2_iudbg0_rdec or ex2_iudbg1_rdec + or ex2_iudbg2_rdec or ex2_iulfsr_rdec or ex2_iullcr_rdec + or ex2_lper_rdec or ex2_lperu_rdec or ex2_lpidr_rdec + or ex2_lratcfg_rdec or ex2_lratps_rdec or ex2_mas0_rdec + or ex2_mas0_mas1_rdec or ex2_mas1_rdec or ex2_mas2_rdec + or ex2_mas2u_rdec or ex2_mas3_rdec or ex2_mas4_rdec + or ex2_mas5_rdec or ex2_mas5_mas6_rdec or ex2_mas6_rdec + or ex2_mas7_rdec or ex2_mas7_mas3_rdec or ex2_mas8_rdec + or ex2_mas8_mas1_rdec or ex2_mmucfg_rdec or ex2_mmucr0_rdec + or ex2_mmucr1_rdec or ex2_mmucr2_rdec or ex2_mmucr3_rdec + or ex2_mmucsr0_rdec or ex2_pid_rdec or ex2_ppr32_rdec + or ex2_tlb0cfg_rdec or ex2_tlb0ps_rdec or ex2_xucr2_rdec + or ex2_xudbg0_rdec or ex2_xudbg1_rdec or ex2_xudbg2_rdec or + ex2_slowspr_range or + or_reduce(tspr_cspr_illeg_mfspr_b and ex2_tid)); + +ex2_illeg_mtspr <= ex2_is_mtspr_q and not ( + ex2_ccr0_wdec or ex2_ccr1_wdec or ex2_ccr2_wdec + or ex2_dac1_wdec or ex2_dac2_wdec or ex2_dac3_wdec + or ex2_dac4_wdec or ex2_givpr_wdec or ex2_iac1_wdec + or ex2_iac2_wdec or ex2_iac3_wdec or ex2_iac4_wdec + or ex2_ivpr_wdec or ex2_tbl_wdec or ex2_tbu_wdec + or ex2_tenc_wdec or ex2_tens_wdec or ex2_trace_wdec + or ex2_xucr0_wdec or ex2_xucr3_wdec or ex2_xucr4_wdec or + ex2_gsprg0_wdec or ex2_gsprg1_wdec or ex2_gsprg2_wdec + or ex2_gsprg3_wdec or ex2_sprg0_wdec or ex2_sprg1_wdec + or ex2_sprg2_wdec or ex2_sprg3_wdec or ex2_sprg4_wdec + or ex2_sprg5_wdec or ex2_sprg6_wdec or ex2_sprg7_wdec + or ex2_sprg8_wdec or ex2_vrsave_wdec or + ex2_dvc1_wdec or ex2_dvc2_wdec or ex2_eplc_wdec + or ex2_epsc_wdec or ex2_immr_wdec or ex2_imr_wdec + or ex2_iucr0_wdec or ex2_iucr1_wdec or ex2_iucr2_wdec + or ex2_iudbg0_wdec or ex2_iulfsr_wdec or ex2_iullcr_wdec + or ex2_lper_wdec or ex2_lperu_wdec or ex2_lpidr_wdec + or ex2_mas0_wdec or ex2_mas0_mas1_wdec or ex2_mas1_wdec + or ex2_mas2_wdec or ex2_mas2u_wdec or ex2_mas3_wdec + or ex2_mas4_wdec or ex2_mas5_wdec or ex2_mas5_mas6_wdec + or ex2_mas6_wdec or ex2_mas7_wdec or ex2_mas7_mas3_wdec + or ex2_mas8_wdec or ex2_mas8_mas1_wdec or ex2_mmucr0_wdec + or ex2_mmucr1_wdec or ex2_mmucr2_wdec or ex2_mmucr3_wdec + or ex2_mmucsr0_wdec or ex2_pid_wdec or ex2_ppr32_wdec + or ex2_xucr2_wdec or ex2_xudbg0_wdec or + ex2_slowspr_range or + or_reduce(tspr_cspr_illeg_mtspr_b and ex2_tid)); + +ex2_hypv_mfspr <= ex2_is_mfspr_q and ( + ex2_ccr0_re or ex2_ccr1_re or ex2_ccr2_re + or ex2_dac1_re or ex2_dac2_re or ex2_dac3_re + or ex2_dac4_re or ex2_iac1_re or ex2_iac2_re + or ex2_iac3_re or ex2_iac4_re or ex2_ivpr_re + or ex2_tenc_re or ex2_tens_re or ex2_tensr_re + or ex2_tir_re or ex2_xucr0_re or ex2_xucr3_re + or ex2_xucr4_re or + ex2_sprg8_re or + ex2_dvc1_re or ex2_dvc2_re or ex2_eptcfg_re + or ex2_immr_re or ex2_imr_re or ex2_iucr0_re + or ex2_iucr1_re or ex2_iucr2_re or ex2_iudbg0_re + or ex2_iudbg1_re or ex2_iudbg2_re or ex2_iulfsr_re + or ex2_iullcr_re or ex2_lper_re or ex2_lperu_re + or ex2_lpidr_re or ex2_lratcfg_re or ex2_lratps_re + or ex2_mas5_re or ex2_mas5_mas6_re or ex2_mas8_re + or ex2_mas8_mas1_re or ex2_mmucfg_re or ex2_mmucr0_re + or ex2_mmucr1_re or ex2_mmucr2_re or ex2_mmucsr0_re + or ex2_tlb0cfg_re or ex2_tlb0ps_re or ex2_xucr2_re + or ex2_xudbg0_re or ex2_xudbg1_re or ex2_xudbg2_re or + ex2_slowspr_range_hypv or + or_reduce(tspr_cspr_hypv_mfspr and ex2_tid)); + +ex2_hypv_mtspr <= ex2_is_mtspr_q and ( + ex2_ccr0_we or ex2_ccr1_we or ex2_ccr2_we + or ex2_dac1_we or ex2_dac2_we or ex2_dac3_we + or ex2_dac4_we or ex2_givpr_we or ex2_iac1_we + or ex2_iac2_we or ex2_iac3_we or ex2_iac4_we + or ex2_ivpr_we or ex2_tbl_we or ex2_tbu_we + or ex2_tenc_we or ex2_tens_we or ex2_xucr0_we + or ex2_xucr3_we or ex2_xucr4_we or + ex2_sprg8_we or + ex2_dvc1_we or ex2_dvc2_we or ex2_immr_we + or ex2_imr_we or ex2_iucr0_we or ex2_iucr1_we + or ex2_iucr2_we or ex2_iudbg0_we or ex2_iulfsr_we + or ex2_iullcr_we or ex2_lper_we or ex2_lperu_we + or ex2_lpidr_we or ex2_mas5_we or ex2_mas5_mas6_we + or ex2_mas8_we or ex2_mas8_mas1_we or ex2_mmucr0_we + or ex2_mmucr1_we or ex2_mmucr2_we or ex2_mmucsr0_we + or ex2_xucr2_we or ex2_xudbg0_we or + ex2_slowspr_range_hypv or + or_reduce(tspr_cspr_hypv_mtspr and ex2_tid)); + +end generate; + +ex3_hypv_spr_d <= ex2_hypv_mfspr or ex2_hypv_mtspr; + +ex3_illeg_spr_d <= ex2_illeg_mfspr or ex2_illeg_mtspr or ex2_illeg_mftb; + +ex3_priv_spr_d <= (ex2_instr_q(11) and (ex2_is_mtspr_q or ex2_is_mfspr_q)) or + ex2_is_mtmsr_q or ex2_is_mfmsr_q; + +xu_pc_spr_ccr0_pme <= ccr0_q(58 to 59); +spr_ccr0_we <= ccr0_q(60 to 63); +spr_ccr2_en_dcr <= spr_ccr2_en_dcr_int; +spr_ccr2_en_dcr_int <= ccr2_q(32); +spr_ccr2_en_trace <= ccr2_q(33); +spr_ccr2_en_pc <= ccr2_q(34); +xu_iu_spr_ccr2_ifratsc <= ccr2_q(35 to 43); +xu_iu_spr_ccr2_ifrat <= ccr2_q(44); +xu_lsu_spr_ccr2_dfratsc <= ccr2_q(45 to 53); +xu_lsu_spr_ccr2_dfrat <= ccr2_q(54); +spr_ccr2_ucode_dis <= ccr2_q(55); +spr_ccr2_ap <= ccr2_q(56 to 59); +spr_ccr2_en_attn <= ccr2_q(60); +spr_ccr2_en_ditc <= ccr2_q(61); +spr_ccr2_en_icswx <= ccr2_q(62); +spr_ccr2_notlb <= ccr2_q(63); +spr_tens_ten <= tens_q(60 to 63); +spr_xucr0_clkg_ctl <= xucr0_q(33 to 37); +spr_xucr0_trace_um <= xucr0_q(38 to 41); +xu_lsu_spr_xucr0_mbar_ack <= xucr0_q(42); +xu_lsu_spr_xucr0_tlbsync <= xucr0_q(43); +spr_dec_spr_xucr0_ssdly <= xucr0_q(44 to 48); +spr_xucr0_cls <= xucr0_q(49); +xu_lsu_spr_xucr0_aflsta <= xucr0_q(50); +spr_xucr0_mddp <= xucr0_q(51); +xu_lsu_spr_xucr0_cred <= xucr0_q(52); +xu_lsu_spr_xucr0_rel <= xucr0_q(53); +spr_xucr0_mdcp <= xucr0_q(54); +spr_xucr0_tcs <= xucr0_q(55); +xu_lsu_spr_xucr0_flsta <= xucr0_q(56); +xu_lsu_spr_xucr0_l2siw <= xucr0_q(57); +xu_lsu_spr_xucr0_flh2l2 <= xucr0_q(58); +xu_lsu_spr_xucr0_dcdis <= xucr0_q(59); +xu_lsu_spr_xucr0_wlk <= xucr0_q(60); +xucr0_clfc_d <= ex6_xucr0_we and ex6_spr_wd(63); +xu_lsu_spr_xucr0_clfc <= xucr0_clfc_q; + +-- CCR0 +ex6_ccr0_di <= ex6_spr_wd(32 to 33) & --PME + ex6_spr_wd(60 to 63) ; --WE +ccr0_do <= tidn(0 to 0) & + tidn(0 to 31) & --/// + ccr0_q(58 to 59) & --PME + tidn(34 to 51) & --/// + "0000" & --WEM + tidn(56 to 59) & --/// + ccr0_q(60 to 63) ; --WE +-- CCR1 +ex6_ccr1_di <= ex6_spr_wd(34 to 39) & --WC3 + ex6_spr_wd(42 to 47) & --WC2 + ex6_spr_wd(50 to 55) & --WC1 + ex6_spr_wd(58 to 63) ; --WC0 +ccr1_do <= tidn(0 to 0) & + tidn(0 to 31) & --/// + tidn(32 to 33) & --/// + ccr1_q(40 to 45) & --WC3 + tidn(40 to 41) & --/// + ccr1_q(46 to 51) & --WC2 + tidn(48 to 49) & --/// + ccr1_q(52 to 57) & --WC1 + tidn(56 to 57) & --/// + ccr1_q(58 to 63) ; --WC0 +-- CCR2 +ex6_ccr2_di <= ex6_spr_wd(32 to 32) & --EN_DCR + ex6_spr_wd(33 to 33) & --EN_TRACE + ex6_spr_wd(34 to 34) & --EN_PC + ex6_spr_wd(35 to 43) & --IFRATSC + ex6_spr_wd(44 to 44) & --IFRAT + ex6_spr_wd(45 to 53) & --DFRATSC + ex6_spr_wd(54 to 54) & --DFRAT + ex6_spr_wd(55 to 55) & --UCODE_DIS + ex6_spr_wd(56 to 59) & --AP + ex6_spr_wd(60 to 60) & --EN_ATTN + ex6_spr_wd(61 to 61) & --EN_DITC + ex6_spr_wd(62 to 62) & --EN_ICSWX + ex6_spr_wd(63 to 63) ; --NOTLB +ccr2_do <= tidn(0 to 0) & + tidn(0 to 31) & --/// + ccr2_q(32 to 32) & --EN_DCR + ccr2_q(33 to 33) & --EN_TRACE + ccr2_q(34 to 34) & --EN_PC + ccr2_q(35 to 43) & --IFRATSC + ccr2_q(44 to 44) & --IFRAT + ccr2_q(45 to 53) & --DFRATSC + ccr2_q(54 to 54) & --DFRAT + ccr2_q(55 to 55) & --UCODE_DIS + ccr2_q(56 to 59) & --AP + ccr2_q(60 to 60) & --EN_ATTN + ccr2_q(61 to 61) & --EN_DITC + ccr2_q(62 to 62) & --EN_ICSWX + ccr2_q(63 to 63) ; --NOTLB +-- PIR +pir_do <= tidn(0 to 0) & + tidn(0 to 31) & --/// + tidn(32 to 53) & --/// + an_ac_coreid_q(54 to 61) & --CID + ex2_tid_q(0 to 1) ; --TID +-- PVR +pvr_do <= tidn(0 to 0) & + tidn(0 to 31) & --/// + version(32 to 47) & --VERSION + revision(48 to 63) ; --REVISION +-- TB +tb_do <= tidn(0 to 0) & + tbu_q(32 to 63) & --TBU + tbl_q(32 to 63) ; --TBL +-- TBL +ex6_tbl_di <= ex6_spr_wd(32 to 63) ; --TBL +tbl_do <= tidn(0 to 0) & + tidn(0 to 31) & --/// + tbl_q(32 to 63) ; --TBL +-- TBU +ex6_tbu_di <= ex6_spr_wd(32 to 63) ; --TBU +tbu_do <= tidn(0 to 0) & + tidn(0 to 31) & --/// + tbu_q(32 to 63) ; --TBU +-- TENC +tenc_do <= tidn(0 to 0) & + tidn(0 to 31) & --/// + tidn(32 to 59) & --/// + tens_q(60 to 63) ; --TEN +-- TENS +ex6_tens_di <= ex6_spr_wd(60 to 63) ; --TEN +tens_do <= tidn(0 to 0) & + tidn(0 to 31) & --/// + tidn(32 to 59) & --/// + tens_q(60 to 63) ; --TEN +-- TENSR +tensr_do <= tidn(0 to 0) & + tidn(0 to 31) & --/// + tidn(32 to 59) & --/// + spr_tensr(0 to 3) ; --TENSR +-- TIR +tir_do <= tidn(0 to 0) & + tidn(0 to 31) & --/// + tidn(32 to 61) & --/// + ex2_tid_q(0 to 1) ; --TID +-- XUCR0 +ex6_xucr0_di <= ex6_spr_wd(32 to 36) & --CLKG_CTL + ex6_spr_wd(37 to 40) & --TRACE_UM + ex6_spr_wd(41 to 41) & --MBAR_ACK + ex6_spr_wd(42 to 42) & --TLBSYNC + xucr0_q(44 to 48) & --SSDLY + xucr0_q(49 to 49) & --CLS + ex6_spr_wd(49 to 49) & --AFLSTA + ex6_spr_wd(50 to 50) & --MDDP + ex6_spr_wd(51 to 51) & --CRED + xucr0_q(53 to 53) & --REL + ex6_spr_wd(53 to 53) & --MDCP + ex6_spr_wd(54 to 54) & --TCS + ex6_spr_wd(55 to 55) & --FLSTA + xucr0_q(57 to 57) & --L2SIW + xucr0_q(58 to 58) & --FLH2L2 + ex6_spr_wd(58 to 58) & --DCDIS + ex6_spr_wd(59 to 59) & --WLK + ex6_spr_wd(60 to 60) & --CSLC + ex6_spr_wd(61 to 61) & --CUL + ex6_spr_wd(62 to 62) ; --CLO +xucr0_do <= tidn(0 to 0) & + tidn(0 to 31) & --/// + xucr0_q(33 to 37) & --CLKG_CTL + xucr0_q(38 to 41) & --TRACE_UM + xucr0_q(42 to 42) & --MBAR_ACK + xucr0_q(43 to 43) & --TLBSYNC + xucr0_q(44 to 48) & --SSDLY + xucr0_q(49 to 49) & --CLS + xucr0_q(50 to 50) & --AFLSTA + xucr0_q(51 to 51) & --MDDP + xucr0_q(52 to 52) & --CRED + xucr0_q(53 to 53) & --REL + xucr0_q(54 to 54) & --MDCP + xucr0_q(55 to 55) & --TCS + xucr0_q(56 to 56) & --FLSTA + xucr0_q(57 to 57) & --L2SIW + xucr0_q(58 to 58) & --FLH2L2 + xucr0_q(59 to 59) & --DCDIS + xucr0_q(60 to 60) & --WLK + xucr0_q(61 to 61) & --CSLC + xucr0_q(62 to 62) & --CUL + xucr0_q(63 to 63) & --CLO + '0' ; --CLFC + +-- Unused Signals +mark_unused(ccr0_do(0 to 64-regsize)); +mark_unused(ccr1_do(0 to 64-regsize)); +mark_unused(ccr2_do(0 to 64-regsize)); +mark_unused(pir_do(0 to 64-regsize)); +mark_unused(pvr_do(0 to 64-regsize)); +mark_unused(tb_do(0 to 64-regsize)); +mark_unused(tbl_do(0 to 64-regsize)); +mark_unused(tbu_do(0 to 64-regsize)); +mark_unused(tenc_do(0 to 64-regsize)); +mark_unused(tens_do(0 to 64-regsize)); +mark_unused(tensr_do(0 to 64-regsize)); +mark_unused(tir_do(0 to 64-regsize)); +mark_unused(xucr0_do(0 to 64-regsize)); +mark_unused(ex2_rs0_q(56 to 59)); +mark_unused(tbl_do(1 to 64)); +mark_unused(ex2_trace_we); +mark_unused(ex2_givpr_re); +mark_unused(pir_act); +mark_unused(pvr_act); +mark_unused(tenc_act); +mark_unused(tensr_act); +mark_unused(tir_act); +mark_unused(exx_act_data(1)); + +ccr0_latch : tri_ser_rlmreg_p +generic map(width => ccr0_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => ccr0_act, + forcee => bcfg_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => bcfg_slp_sl_thold_0_b, + sg => sg_0, + scin => siv_bcfg(ccr0_offset_bcfg to ccr0_offset_bcfg + ccr0_q'length-1), + scout => sov_bcfg(ccr0_offset_bcfg to ccr0_offset_bcfg + ccr0_q'length-1), + din => ccr0_d, + dout => ccr0_q); +ccr1_latch : tri_ser_rlmreg_p +generic map(width => ccr1_q'length, init => 3994575, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => ccr1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ccr1_offset to ccr1_offset + ccr1_q'length-1), + scout => sov(ccr1_offset to ccr1_offset + ccr1_q'length-1), + din => ccr1_d, + dout => ccr1_q); +ccr2_latch : tri_ser_rlmreg_p +generic map(width => ccr2_q'length, init => 1, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => ccr2_act, + forcee => ccfg_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => ccfg_sl_thold_0_b, + sg => sg_0, + scin => siv_ccfg(ccr2_offset_ccfg to ccr2_offset_ccfg + ccr2_q'length-1), + scout => sov_ccfg(ccr2_offset_ccfg to ccr2_offset_ccfg + ccr2_q'length-1), + din => ccr2_d, + dout => ccr2_q); +tbl_latch : tri_ser_rlmreg_p +generic map(width => tbl_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => tbl_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(tbl_offset to tbl_offset + tbl_q'length-1), + scout => sov(tbl_offset to tbl_offset + tbl_q'length-1), + din => tbl_d, + dout => tbl_q); +tbu_latch : tri_ser_rlmreg_p +generic map(width => tbu_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => tbu_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(tbu_offset to tbu_offset + tbu_q'length-1), + scout => sov(tbu_offset to tbu_offset + tbu_q'length-1), + din => tbu_d, + dout => tbu_q); +tens_latch : tri_ser_rlmreg_p +generic map(width => tens_q'length, init => 1, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => tens_act, + forcee => bcfg_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => bcfg_sl_thold_0_b, + sg => sg_0, + scin => siv_bcfg(tens_offset_bcfg to tens_offset_bcfg + tens_q'length-1), + scout => sov_bcfg(tens_offset_bcfg to tens_offset_bcfg + tens_q'length-1), + din => tens_d, + dout => tens_q); +xucr0_latch : tri_ser_rlmreg_p +generic map(width => xucr0_q'length, init => (230496 + spr_xucr0_init_mod), expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => xucr0_act, + forcee => ccfg_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => ccfg_sl_thold_0_b, + sg => sg_0, + scin => siv_ccfg(xucr0_offset_ccfg to xucr0_offset_ccfg + xucr0_q'length-1), + scout => sov_ccfg(xucr0_offset_ccfg to xucr0_offset_ccfg + xucr0_q'length-1), + din => xucr0_d, + dout => xucr0_q); + + +-- Latch Instances +exx_act_latch : tri_rlmreg_p + generic map (width => exx_act_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(exx_act_offset to exx_act_offset + exx_act_q'length-1), + scout => sov(exx_act_offset to exx_act_offset + exx_act_q'length-1), + din => exx_act_d, + dout => exx_act_q); +rf1_instr_latch : tri_rlmreg_p + generic map (width => rf1_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DRF1), + mpw1_b => mpw1_dc_b(DRF1), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf1_instr_offset to rf1_instr_offset + rf1_instr_q'length-1), + scout => sov(rf1_instr_offset to rf1_instr_offset + rf1_instr_q'length-1), + din => dec_spr_rf0_instr , + dout => rf1_instr_q); +rf1_aspr_act_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DRF1), + mpw1_b => mpw1_dc_b(DRF1), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf1_aspr_act_offset), + scout => sov(rf1_aspr_act_offset), + din => rf1_aspr_act_d, + dout => rf1_aspr_act_q); +rf1_aspr_tid_latch : tri_rlmreg_p + generic map (width => rf1_aspr_tid_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => rf0_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DRF1), + mpw1_b => mpw1_dc_b(DRF1), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf1_aspr_tid_offset to rf1_aspr_tid_offset + rf1_aspr_tid_q'length-1), + scout => sov(rf1_aspr_tid_offset to rf1_aspr_tid_offset + rf1_aspr_tid_q'length-1), + din => rf1_aspr_tid_d, + dout => rf1_aspr_tid_q); +rf1_msr_gs_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DRF1), + mpw1_b => mpw1_dc_b(DRF1), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rf1_msr_gs_offset), + scout => sov(rf1_msr_gs_offset), + din => rf1_msr_gs_d, + dout => rf1_msr_gs_q); +ex1_tid_latch : tri_rlmreg_p + generic map (width => ex1_tid_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX1), + mpw1_b => mpw1_dc_b(DEX1), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_tid_offset to ex1_tid_offset + ex1_tid_q'length-1), + scout => sov(ex1_tid_offset to ex1_tid_offset + ex1_tid_q'length-1), + din => rf1_tid, + dout => ex1_tid_q); +ex1_is_mfspr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX1), + mpw1_b => mpw1_dc_b(DEX1), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_mfspr_offset), + scout => sov(ex1_is_mfspr_offset), + din => rf1_is_mfspr, + dout => ex1_is_mfspr_q); +ex1_is_mtspr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX1), + mpw1_b => mpw1_dc_b(DEX1), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_is_mtspr_offset), + scout => sov(ex1_is_mtspr_offset), + din => rf1_is_mtspr, + dout => ex1_is_mtspr_q); +ex1_instr_latch : tri_rlmreg_p + generic map (width => ex1_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX1), + mpw1_b => mpw1_dc_b(DEX1), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_instr_offset to ex1_instr_offset + ex1_instr_q'length-1), + scout => sov(ex1_instr_offset to ex1_instr_offset + ex1_instr_q'length-1), + din => rf1_instr_q , + dout => ex1_instr_q); +ex1_aspr_re_latch : tri_rlmreg_p + generic map (width => ex1_aspr_re_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX1), + mpw1_b => mpw1_dc_b(DEX1), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_aspr_re_offset to ex1_aspr_re_offset + ex1_aspr_re_q'length-1), + scout => sov(ex1_aspr_re_offset to ex1_aspr_re_offset + ex1_aspr_re_q'length-1), + din => rf1_aspr_re, + dout => ex1_aspr_re_q); +ex1_aspr_ce_addr_latch : tri_rlmreg_p + generic map (width => ex1_aspr_ce_addr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(0) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX1), + mpw1_b => mpw1_dc_b(DEX1), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex1_aspr_ce_addr_offset to ex1_aspr_ce_addr_offset + ex1_aspr_ce_addr_q'length-1), + scout => sov(ex1_aspr_ce_addr_offset to ex1_aspr_ce_addr_offset + ex1_aspr_ce_addr_q'length-1), + din => rf1_aspr_addr, + dout => ex1_aspr_ce_addr_q); +ex2_tid_latch : tri_regk + generic map (width => ex2_tid_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex1_tid_q , + dout => ex2_tid_q); +ex2_is_mfmsr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_mfmsr, + dout(0) => ex2_is_mfmsr_q); +ex2_is_mfspr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_mfspr_q , + dout(0) => ex2_is_mfspr_q); +ex2_is_mftb_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_mftb, + dout(0) => ex2_is_mftb_q); +ex2_is_mtmsr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_mtmsr, + dout(0) => ex2_is_mtmsr_q); +ex2_is_mtspr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_mtspr_q , + dout(0) => ex2_is_mtspr_q); +ex2_is_wait_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_wait, + dout(0) => ex2_is_wait_q); +ex2_wait_wc_latch : tri_regk + generic map (width => ex2_wait_wc_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act_data(1), + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex1_instr_q(9 to 10) , + dout => ex2_wait_wc_q); +ex2_is_msgclr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_msgclr, + dout(0) => ex2_is_msgclr_q); +ex2_instr_latch : tri_regk + generic map (width => ex2_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex2_instr_d, + dout => ex2_instr_q); +ex2_rs0_latch : tri_regk + generic map (width => ex2_rs0_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => fxu_spr_ex1_rs0 , + dout => ex2_rs0_q); +ex2_msr_gs_latch : tri_regk + generic map (width => ex2_msr_gs_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex2_msr_gs_d, + dout => ex2_msr_gs_q); +ex2_tenc_we_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_tenc_we, + dout(0) => ex2_tenc_we_q); +ex2_ccr0_we_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_ccr0_we, + dout(0) => ex2_ccr0_we_q); +ex2_aspr_rdata_latch : tri_rlmreg_p + generic map (width => ex2_aspr_rdata_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act_data(1), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex2_aspr_rdata_offset to ex2_aspr_rdata_offset + ex2_aspr_rdata_q'length-1), + scout => sov(ex2_aspr_rdata_offset to ex2_aspr_rdata_offset + ex2_aspr_rdata_q'length-1), + din => ex2_aspr_rdata_d, + dout => ex2_aspr_rdata_q); +ex2_dcrn_latch : tri_regk + generic map (width => ex2_dcrn_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act_data(1), + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => fxu_spr_ex1_rs1 , + dout => ex2_dcrn_q); +ex2_dcr_val_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_dcr_val, + dout(0) => ex2_dcr_val_q); +ex2_aspr_ce_addr_latch : tri_regk + generic map (width => ex2_aspr_ce_addr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex1_aspr_ce_addr_q , + dout => ex2_aspr_ce_addr_q); +ex2_aspr_re_latch : tri_regk + generic map (width => ex2_aspr_re_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex1_aspr_re_q , + dout => ex2_aspr_re_q); +ex2_dcr_read_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_dcr_read, + dout(0) => ex2_dcr_read_q); +ex2_dcr_user_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_dcr_user, + dout(0) => ex2_dcr_user_q); +ex2_is_wrtee_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_wrtee, + dout(0) => ex2_is_wrtee_q); +ex2_is_wrteei_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_wrteei, + dout(0) => ex2_is_wrteei_q); +ex3_tid_latch : tri_rlmreg_p + generic map (width => ex3_tid_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_tid_offset to ex3_tid_offset + ex3_tid_q'length-1), + scout => sov(ex3_tid_offset to ex3_tid_offset + ex3_tid_q'length-1), + din => ex2_tid_q , + dout => ex3_tid_q); +ex3_is_mtmsr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_mtmsr_offset), + scout => sov(ex3_is_mtmsr_offset), + din => ex2_is_mtmsr_q , + dout => ex3_is_mtmsr_q); +ex3_is_mtspr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_mtspr_offset), + scout => sov(ex3_is_mtspr_offset), + din => ex2_is_mtspr_q , + dout => ex3_is_mtspr_q); +ex3_wait_wc_latch : tri_rlmreg_p + generic map (width => ex3_wait_wc_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act_data(2), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wait_wc_offset to ex3_wait_wc_offset + ex3_wait_wc_q'length-1), + scout => sov(ex3_wait_wc_offset to ex3_wait_wc_offset + ex3_wait_wc_q'length-1), + din => ex2_wait_wc_q , + dout => ex3_wait_wc_q); +ex3_is_msgclr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_msgclr_offset), + scout => sov(ex3_is_msgclr_offset), + din => ex2_is_msgclr_q , + dout => ex3_is_msgclr_q); +ex3_instr_latch : tri_rlmreg_p + generic map (width => ex3_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_instr_offset to ex3_instr_offset + ex3_instr_q'length-1), + scout => sov(ex3_instr_offset to ex3_instr_offset + ex3_instr_q'length-1), + din => ex3_instr_d, + dout => ex3_instr_q); +ex3_cspr_rt_latch : tri_rlmreg_p + generic map (width => ex3_cspr_rt_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act_data(2), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_cspr_rt_offset to ex3_cspr_rt_offset + ex3_cspr_rt_q'length-1), + scout => sov(ex3_cspr_rt_offset to ex3_cspr_rt_offset + ex3_cspr_rt_q'length-1), + din => ex2_cspr_rt, + dout => ex3_cspr_rt_q); +ex3_hypv_spr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_hypv_spr_offset), + scout => sov(ex3_hypv_spr_offset), + din => ex3_hypv_spr_d, + dout => ex3_hypv_spr_q); +ex3_illeg_spr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_illeg_spr_offset), + scout => sov(ex3_illeg_spr_offset), + din => ex3_illeg_spr_d, + dout => ex3_illeg_spr_q); +ex3_priv_spr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_priv_spr_offset), + scout => sov(ex3_priv_spr_offset), + din => ex3_priv_spr_d, + dout => ex3_priv_spr_q); +ex3_sspr_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_sspr_val_offset), + scout => sov(ex3_sspr_val_offset), + din => ex2_sspr_val, + dout => ex3_sspr_val_q); +ex3_rt_latch : tri_rlmreg_p + generic map (width => ex3_rt_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act_data(2), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_rt_offset to ex3_rt_offset + ex3_rt_q'length-1), + scout => sov(ex3_rt_offset to ex3_rt_offset + ex3_rt_q'length-1), + din => mux_spr_ex2_rt , + dout => ex3_rt_q); +ex3_is_mfspr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_mfspr_offset), + scout => sov(ex3_is_mfspr_offset), + din => ex2_is_mfspr_q , + dout => ex3_is_mfspr_q); +ex3_wait_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_wait_offset), + scout => sov(ex3_wait_offset), + din => ex2_wait, + dout => ex3_wait_q); +ex3_corr_rdata_latch : tri_rlmreg_p + generic map (width => ex3_corr_rdata_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act_data(2), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_corr_rdata_offset to ex3_corr_rdata_offset + ex3_corr_rdata_q'length-1), + scout => sov(ex3_corr_rdata_offset to ex3_corr_rdata_offset + ex3_corr_rdata_q'length-1), + din => ex2_corr_rdata, + dout => ex3_corr_rdata_q); +ex3_sprg_ce_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_sprg_ce_offset), + scout => sov(ex3_sprg_ce_offset), + din => ex2_sprg_ce, + dout => ex3_sprg_ce_q); +ex3_sprg_ue_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_sprg_ue_offset), + scout => sov(ex3_sprg_ue_offset), + din => ex2_sprg_ue, + dout => ex3_sprg_ue_q); +ex3_aspr_ce_addr_latch : tri_rlmreg_p + generic map (width => ex3_aspr_ce_addr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_aspr_ce_addr_offset to ex3_aspr_ce_addr_offset + ex3_aspr_ce_addr_q'length-1), + scout => sov(ex3_aspr_ce_addr_offset to ex3_aspr_ce_addr_offset + ex3_aspr_ce_addr_q'length-1), + din => ex2_aspr_ce_addr_q , + dout => ex3_aspr_ce_addr_q); +ex3_dcr_read_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_dcr_read_offset), + scout => sov(ex3_dcr_read_offset), + din => ex2_dcr_read_q , + dout => ex3_dcr_read_q); +ex3_aspr_re_latch : tri_rlmreg_p + generic map (width => ex3_aspr_re_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_aspr_re_offset to ex3_aspr_re_offset + ex3_aspr_re_q'length-1), + scout => sov(ex3_aspr_re_offset to ex3_aspr_re_offset + ex3_aspr_re_q'length-1), + din => ex2_aspr_re_q , + dout => ex3_aspr_re_q); +ex3_dcr_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_dcr_val_offset), + scout => sov(ex3_dcr_val_offset), + din => ex2_dcr_val_q , + dout => ex3_dcr_val_q); +ex3_dcr_user_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_dcr_user_offset), + scout => sov(ex3_dcr_user_offset), + din => ex2_dcr_user_q , + dout => ex3_dcr_user_q); +ex3_is_wrtee_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_wrtee_offset), + scout => sov(ex3_is_wrtee_offset), + din => ex2_is_wrtee_q , + dout => ex3_is_wrtee_q); +ex3_is_wrteei_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_wrteei_offset), + scout => sov(ex3_is_wrteei_offset), + din => ex2_is_wrteei_q , + dout => ex3_is_wrteei_q); +ex3_msr_gs_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_msr_gs_offset), + scout => sov(ex3_msr_gs_offset), + din => ex3_msr_gs_d, + dout => ex3_msr_gs_q); +ex4_tid_latch : tri_regk + generic map (width => ex4_tid_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX4), + mpw1_b => mpw1_dc_b(DEX4), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex3_tid_q , + dout => ex4_tid_q); +ex4_is_mtmsr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX4), + mpw1_b => mpw1_dc_b(DEX4), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_is_mtmsr_q , + dout(0) => ex4_is_mtmsr_q); +ex4_is_mtspr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX4), + mpw1_b => mpw1_dc_b(DEX4), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_is_mtspr_q , + dout(0) => ex4_is_mtspr_q); +ex4_wait_wc_latch : tri_regk + generic map (width => ex4_wait_wc_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX4), + mpw1_b => mpw1_dc_b(DEX4), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex3_wait_wc_q , + dout => ex4_wait_wc_q); +ex4_is_msgclr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX4), + mpw1_b => mpw1_dc_b(DEX4), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_is_msgclr_q , + dout(0) => ex4_is_msgclr_q); +ex4_instr_latch : tri_regk + generic map (width => ex4_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX4), + mpw1_b => mpw1_dc_b(DEX4), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex3_instr_q , + dout => ex4_instr_q); +ex4_sspr_val_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX4), + mpw1_b => mpw1_dc_b(DEX4), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_sspr_val_q , + dout(0) => ex4_sspr_val_q); +ex4_rt_latch : tri_regk + generic map (width => ex4_rt_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act_data(3), + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX4), + mpw1_b => mpw1_dc_b(DEX4), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex3_rt_q , + dout => ex4_rt_q); +ex4_is_mfspr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX4), + mpw1_b => mpw1_dc_b(DEX4), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_is_mfspr_q , + dout(0) => ex4_is_mfspr_q); +ex4_dcr_read_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX4), + mpw1_b => mpw1_dc_b(DEX4), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_dcr_read_q , + dout(0) => ex4_dcr_read_q); +ex4_wait_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX4), + mpw1_b => mpw1_dc_b(DEX4), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_wait_q , + dout(0) => ex4_wait_q); +ex4_corr_rdata_latch : tri_regk + generic map (width => ex4_corr_rdata_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act_data(3), + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX4), + mpw1_b => mpw1_dc_b(DEX4), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex3_corr_rdata_q , + dout => ex4_corr_rdata_q); +ex4_sprg_ce_latch : tri_regk + generic map (width => ex4_sprg_ce_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act_data(3), + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX4), + mpw1_b => mpw1_dc_b(DEX4), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex4_sprg_ce_d, + dout => ex4_sprg_ce_q); +ex4_aspr_ce_addr_latch : tri_regk + generic map (width => ex4_aspr_ce_addr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex3_sprg_ce , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX4), + mpw1_b => mpw1_dc_b(DEX4), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex3_aspr_ce_addr_q , + dout => ex4_aspr_ce_addr_q); +ex4_dcr_val_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX4), + mpw1_b => mpw1_dc_b(DEX4), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_dcr_val_q , + dout(0) => ex4_dcr_val_q); +ex4_dcr_user_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX4), + mpw1_b => mpw1_dc_b(DEX4), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_dcr_user_q , + dout(0) => ex4_dcr_user_q); +ex4_is_wrtee_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX4), + mpw1_b => mpw1_dc_b(DEX4), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_is_wrtee_q , + dout(0) => ex4_is_wrtee_q); +ex4_is_wrteei_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX4), + mpw1_b => mpw1_dc_b(DEX4), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_is_wrteei_q , + dout(0) => ex4_is_wrteei_q); +ex4_aspr_we_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX4), + mpw1_b => mpw1_dc_b(DEX4), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_aspr_we_offset), + scout => sov(ex4_aspr_we_offset), + din => ex3_aspr_we, + dout => ex4_aspr_we_q); +ex4_aspr_addr_latch : tri_rlmreg_p + generic map (width => ex4_aspr_addr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX4), + mpw1_b => mpw1_dc_b(DEX4), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex4_aspr_addr_offset to ex4_aspr_addr_offset + ex4_aspr_addr_q'length-1), + scout => sov(ex4_aspr_addr_offset to ex4_aspr_addr_offset + ex4_aspr_addr_q'length-1), + din => ex3_aspr_addr, + dout => ex4_aspr_addr_q); +ex5_val_latch : tri_rlmreg_p + generic map (width => ex5_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX5), + mpw1_b => mpw1_dc_b(DEX5), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_val_offset to ex5_val_offset + ex5_val_q'length-1), + scout => sov(ex5_val_offset to ex5_val_offset + ex5_val_q'length-1), + din => ex5_val_d, + dout => ex5_val_q); +ex5_tid_latch : tri_rlmreg_p + generic map (width => ex5_tid_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX5), + mpw1_b => mpw1_dc_b(DEX5), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_tid_offset to ex5_tid_offset + ex5_tid_q'length-1), + scout => sov(ex5_tid_offset to ex5_tid_offset + ex5_tid_q'length-1), + din => ex4_tid_q , + dout => ex5_tid_q); +ex5_is_mtmsr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX5), + mpw1_b => mpw1_dc_b(DEX5), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_is_mtmsr_offset), + scout => sov(ex5_is_mtmsr_offset), + din => ex4_is_mtmsr_q , + dout => ex5_is_mtmsr_q); +ex5_is_mtspr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX5), + mpw1_b => mpw1_dc_b(DEX5), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_is_mtspr_offset), + scout => sov(ex5_is_mtspr_offset), + din => ex4_is_mtspr_q , + dout => ex5_is_mtspr_q); +ex5_wait_wc_latch : tri_rlmreg_p + generic map (width => ex5_wait_wc_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act_data(4), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX5), + mpw1_b => mpw1_dc_b(DEX5), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_wait_wc_offset to ex5_wait_wc_offset + ex5_wait_wc_q'length-1), + scout => sov(ex5_wait_wc_offset to ex5_wait_wc_offset + ex5_wait_wc_q'length-1), + din => ex4_wait_wc_q , + dout => ex5_wait_wc_q); +ex5_is_msgclr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX5), + mpw1_b => mpw1_dc_b(DEX5), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_is_msgclr_offset), + scout => sov(ex5_is_msgclr_offset), + din => ex4_is_msgclr_q , + dout => ex5_is_msgclr_q); +ex5_instr_latch : tri_rlmreg_p + generic map (width => ex5_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX5), + mpw1_b => mpw1_dc_b(DEX5), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_instr_offset to ex5_instr_offset + ex5_instr_q'length-1), + scout => sov(ex5_instr_offset to ex5_instr_offset + ex5_instr_q'length-1), + din => ex4_instr_q , + dout => ex5_instr_q); +ex5_sspr_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX5), + mpw1_b => mpw1_dc_b(DEX5), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_sspr_val_offset), + scout => sov(ex5_sspr_val_offset), + din => ex4_sspr_val_q , + dout => ex5_sspr_val_q); +ex5_aspr_we_latch : tri_rlmreg_p + generic map (width => ex5_aspr_we_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX5), + mpw1_b => mpw1_dc_b(DEX5), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_aspr_we_offset to ex5_aspr_we_offset + ex5_aspr_we_q'length-1), + scout => sov(ex5_aspr_we_offset to ex5_aspr_we_offset + ex5_aspr_we_q'length-1), + din => ex5_aspr_we_d, + dout => ex5_aspr_we_q); +ex5_rt_latch : tri_rlmreg_p + generic map (width => ex5_rt_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act_data(4), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX5), + mpw1_b => mpw1_dc_b(DEX5), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_rt_offset to ex5_rt_offset + ex5_rt_q'length-1), + scout => sov(ex5_rt_offset to ex5_rt_offset + ex5_rt_q'length-1), + din => ex5_rt_d, + dout => ex5_rt_q); +ex5_wait_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX5), + mpw1_b => mpw1_dc_b(DEX5), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_wait_offset), + scout => sov(ex5_wait_offset), + din => ex4_wait_q , + dout => ex5_wait_q); +ex5_sprg_ce_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX5), + mpw1_b => mpw1_dc_b(DEX5), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_sprg_ce_offset), + scout => sov(ex5_sprg_ce_offset), + din => ex4_sprg_ce_q(0) , + dout => ex5_sprg_ce_q); +ex5_dcr_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX5), + mpw1_b => mpw1_dc_b(DEX5), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_dcr_val_offset), + scout => sov(ex5_dcr_val_offset), + din => ex4_dcr_val, + dout => ex5_dcr_val_q); +ex5_dcr_read_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX5), + mpw1_b => mpw1_dc_b(DEX5), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_dcr_read_offset), + scout => sov(ex5_dcr_read_offset), + din => ex4_dcr_read_q , + dout => ex5_dcr_read_q); +ex5_dcr_user_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX5), + mpw1_b => mpw1_dc_b(DEX5), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_dcr_user_offset), + scout => sov(ex5_dcr_user_offset), + din => ex4_dcr_user_q , + dout => ex5_dcr_user_q); +ex5_aspr_addr_latch : tri_rlmreg_p + generic map (width => ex5_aspr_addr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX5), + mpw1_b => mpw1_dc_b(DEX5), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_aspr_addr_offset to ex5_aspr_addr_offset + ex5_aspr_addr_q'length-1), + scout => sov(ex5_aspr_addr_offset to ex5_aspr_addr_offset + ex5_aspr_addr_q'length-1), + din => ex5_aspr_addr_d, + dout => ex5_aspr_addr_q); +ex5_is_wrtee_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX5), + mpw1_b => mpw1_dc_b(DEX5), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_is_wrtee_offset), + scout => sov(ex5_is_wrtee_offset), + din => ex4_is_wrtee_q , + dout => ex5_is_wrtee_q); +ex5_is_wrteei_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX5), + mpw1_b => mpw1_dc_b(DEX5), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_is_wrteei_offset), + scout => sov(ex5_is_wrteei_offset), + din => ex4_is_wrteei_q , + dout => ex5_is_wrteei_q); +ex6_valid_latch : tri_rlmreg_p + generic map (width => ex6_valid_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_valid_offset to ex6_valid_offset + ex6_valid_q'length-1), + scout => sov(ex6_valid_offset to ex6_valid_offset + ex6_valid_q'length-1), + din => ex5_valid, + dout => ex6_valid_q); +ex6_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_val_offset), + scout => sov(ex6_val_offset), + din => ex5_val, + dout => ex6_val_q); +ex6_tid_latch : tri_regk + generic map (width => ex6_tid_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(5) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex5_tid_q , + dout => ex6_tid_q); +ex6_dbell_taken_latch : tri_regk + generic map (width => ex6_dbell_taken_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => cpl_spr_ex5_dbell_taken , + dout => ex6_dbell_taken_q); +ex6_cdbell_taken_latch : tri_regk + generic map (width => ex6_cdbell_taken_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => cpl_spr_ex5_cdbell_taken , + dout => ex6_cdbell_taken_q); +ex6_gdbell_taken_latch : tri_regk + generic map (width => ex6_gdbell_taken_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => cpl_spr_ex5_gdbell_taken , + dout => ex6_gdbell_taken_q); +ex6_gcdbell_taken_latch : tri_regk + generic map (width => ex6_gcdbell_taken_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => cpl_spr_ex5_gcdbell_taken , + dout => ex6_gcdbell_taken_q); +ex6_gmcdbell_taken_latch : tri_regk + generic map (width => ex6_gmcdbell_taken_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => cpl_spr_ex5_gmcdbell_taken , + dout => ex6_gmcdbell_taken_q); +ex6_rt_latch : tri_regk + generic map (width => ex6_rt_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act_data(5), + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex5_rt_q_b(64-regsize to 63) , + dout => ex6_rt_q); +ex6_instr_latch : tri_regk + generic map (width => ex6_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(5) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex5_instr_q , + dout => ex6_instr_q); +ex6_is_mtspr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(5) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex5_is_mtspr_q , + dout(0) => ex6_is_mtspr_q); +ex6_wait_wc_latch : tri_regk + generic map (width => ex6_wait_wc_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act_data(5), + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex5_wait_wc_q , + dout => ex6_wait_wc_q); +ex6_is_msgclr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(5) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex5_is_msgclr_q , + dout(0) => ex6_is_msgclr_q); +ex6_sspr_val_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(5) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex5_sspr_val_q , + dout(0) => ex6_sspr_val_q); +ex6_set_xucr0_cslc_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex6_set_xucr0_cslc_d, + dout(0) => ex6_set_xucr0_cslc_q); +ex6_set_xucr0_cul_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex6_set_xucr0_cul_d, + dout(0) => ex6_set_xucr0_cul_q); +ex6_set_xucr0_clo_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_slp_nsl_thold_0_b, + din(0) => ex6_set_xucr0_clo_d, + dout(0) => ex6_set_xucr0_clo_q); +ex6_wait_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(5) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex5_wait_q , + dout(0) => ex6_wait_q); +ex6_sprg_ce_latch : tri_regk + generic map (width => ex6_sprg_ce_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(5) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex5_sprg_ce, + dout => ex6_sprg_ce_q); +ex6_dcr_val_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(5) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex5_dcr_val, + dout(0) => ex6_dcr_val_q); +ex6_dcr_read_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(5) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex5_dcr_read_q , + dout(0) => ex6_dcr_read_q); +ex6_dcr_user_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(5) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex5_dcr_user_q , + dout(0) => ex6_dcr_user_q); +ex2_any_mfspr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_any_mfspr_d, + dout(0) => ex2_any_mfspr_q); +ex2_any_mtspr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_any_mtspr_d, + dout(0) => ex2_any_mtspr_q); +ex3_any_mfspr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_any_mfspr_offset), + scout => sov(ex3_any_mfspr_offset), + din => ex2_any_mfspr_q , + dout => ex3_any_mfspr_q); +ex3_any_mtspr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_any_mtspr_offset), + scout => sov(ex3_any_mtspr_offset), + din => ex2_any_mtspr_q , + dout => ex3_any_mtspr_q); +ex4_any_mfspr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX4), + mpw1_b => mpw1_dc_b(DEX4), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_any_mfspr_q , + dout(0) => ex4_any_mfspr_q); +ex4_any_mtspr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX4), + mpw1_b => mpw1_dc_b(DEX4), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_any_mtspr_q , + dout(0) => ex4_any_mtspr_q); +ex5_any_mfspr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX5), + mpw1_b => mpw1_dc_b(DEX5), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_any_mfspr_offset), + scout => sov(ex5_any_mfspr_offset), + din => ex4_any_mfspr_q , + dout => ex5_any_mfspr_q); +ex5_any_mtspr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX5), + mpw1_b => mpw1_dc_b(DEX5), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_any_mtspr_offset), + scout => sov(ex5_any_mtspr_offset), + din => ex4_any_mtspr_q , + dout => ex5_any_mtspr_q); +running_latch : tri_rlmreg_p + generic map (width => running_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(running_offset to running_offset + running_q'length-1), + scout => sov(running_offset to running_offset + running_q'length-1), + din => running_d, + dout => running_q); +llpri_latch : tri_rlmreg_p + generic map (width => llpri_q'length, init => 8, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => llpri_inc , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(llpri_offset to llpri_offset + llpri_q'length-1), + scout => sov(llpri_offset to llpri_offset + llpri_q'length-1), + din => llpri_d, + dout => llpri_q); +dec_dbg_dis_latch : tri_rlmreg_p + generic map (width => dec_dbg_dis_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(dec_dbg_dis_offset to dec_dbg_dis_offset + dec_dbg_dis_q'length-1), + scout => sov(dec_dbg_dis_offset to dec_dbg_dis_offset + dec_dbg_dis_q'length-1), + din => dec_dbg_dis_d, + dout => dec_dbg_dis_q); +tb_dbg_dis_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(tb_dbg_dis_offset), + scout => sov(tb_dbg_dis_offset), + din => tb_dbg_dis_d, + dout => tb_dbg_dis_q); +tb_act_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(tb_act_offset), + scout => sov(tb_act_offset), + din => tb_act_d, + dout => tb_act_q); +ext_dbg_dis_latch : tri_rlmreg_p + generic map (width => ext_dbg_dis_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ext_dbg_dis_offset to ext_dbg_dis_offset + ext_dbg_dis_q'length-1), + scout => sov(ext_dbg_dis_offset to ext_dbg_dis_offset + ext_dbg_dis_q'length-1), + din => ext_dbg_dis_d, + dout => ext_dbg_dis_q); +ram_mode_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ram_mode_offset), + scout => sov(ram_mode_offset), + din => pc_xu_ram_mode , + dout => ram_mode_q); +ram_thread_latch : tri_rlmreg_p + generic map (width => ram_thread_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ram_thread_offset to ram_thread_offset + ram_thread_q'length-1), + scout => sov(ram_thread_offset to ram_thread_offset + ram_thread_q'length-1), + din => pc_xu_ram_thread , + dout => ram_thread_q); +msrovride_enab_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(msrovride_enab_offset), + scout => sov(msrovride_enab_offset), + din => pc_xu_msrovride_enab , + dout => msrovride_enab_q); +waitimpl_val_latch : tri_rlmreg_p + generic map (width => waitimpl_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(waitimpl_val_offset to waitimpl_val_offset + waitimpl_val_q'length-1), + scout => sov(waitimpl_val_offset to waitimpl_val_offset + waitimpl_val_q'length-1), + din => waitimpl_val_d, + dout => waitimpl_val_q); +waitrsv_val_latch : tri_rlmreg_p + generic map (width => waitrsv_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(waitrsv_val_offset to waitrsv_val_offset + waitrsv_val_q'length-1), + scout => sov(waitrsv_val_offset to waitrsv_val_offset + waitrsv_val_q'length-1), + din => waitrsv_val_d, + dout => waitrsv_val_q); +an_ac_reservation_vld_latch : tri_rlmreg_p + generic map (width => an_ac_reservation_vld_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(an_ac_reservation_vld_offset to an_ac_reservation_vld_offset + an_ac_reservation_vld_q'length-1), + scout => sov(an_ac_reservation_vld_offset to an_ac_reservation_vld_offset + an_ac_reservation_vld_q'length-1), + din => an_ac_reservation_vld , + dout => an_ac_reservation_vld_q); +an_ac_sleep_en_latch : tri_rlmreg_p + generic map (width => an_ac_sleep_en_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(an_ac_sleep_en_offset to an_ac_sleep_en_offset + an_ac_sleep_en_q'length-1), + scout => sov(an_ac_sleep_en_offset to an_ac_sleep_en_offset + an_ac_sleep_en_q'length-1), + din => an_ac_sleep_en , + dout => an_ac_sleep_en_q); +an_ac_coreid_latch : tri_rlmreg_p + generic map (width => an_ac_coreid_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(an_ac_coreid_offset to an_ac_coreid_offset + an_ac_coreid_q'length-1), + scout => sov(an_ac_coreid_offset to an_ac_coreid_offset + an_ac_coreid_q'length-1), + din => an_ac_coreid , + dout => an_ac_coreid_q); +tb_update_enable_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(tb_update_enable_offset), + scout => sov(tb_update_enable_offset), + din => an_ac_tb_update_enable , + dout => tb_update_enable_q); +tb_update_pulse_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(tb_update_pulse_offset), + scout => sov(tb_update_pulse_offset), + din => an_ac_tb_update_pulse , + dout => tb_update_pulse_q); +tb_update_pulse_1_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(tb_update_pulse_1_offset), + scout => sov(tb_update_pulse_1_offset), + din => tb_update_pulse_q , + dout => tb_update_pulse_1_q); +pc_xu_reset_wd_complete_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(pc_xu_reset_wd_complete_offset), + scout => sov(pc_xu_reset_wd_complete_offset), + din => pc_xu_reset_wd_complete , + dout => pc_xu_reset_wd_complete_q); +pc_xu_reset_3_complete_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(pc_xu_reset_3_complete_offset), + scout => sov(pc_xu_reset_3_complete_offset), + din => pc_xu_reset_3_complete , + dout => pc_xu_reset_3_complete_q); +pc_xu_reset_2_complete_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(pc_xu_reset_2_complete_offset), + scout => sov(pc_xu_reset_2_complete_offset), + din => pc_xu_reset_2_complete , + dout => pc_xu_reset_2_complete_q); +pc_xu_reset_1_complete_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(pc_xu_reset_1_complete_offset), + scout => sov(pc_xu_reset_1_complete_offset), + din => pc_xu_reset_1_complete , + dout => pc_xu_reset_1_complete_q); +lsu_xu_dbell_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(lsu_xu_dbell_val_offset), + scout => sov(lsu_xu_dbell_val_offset), + din => lsu_xu_dbell_val , + dout => lsu_xu_dbell_val_q); +lsu_xu_dbell_type_latch : tri_rlmreg_p + generic map (width => lsu_xu_dbell_type_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => dbell_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(lsu_xu_dbell_type_offset to lsu_xu_dbell_type_offset + lsu_xu_dbell_type_q'length-1), + scout => sov(lsu_xu_dbell_type_offset to lsu_xu_dbell_type_offset + lsu_xu_dbell_type_q'length-1), + din => lsu_xu_dbell_type , + dout => lsu_xu_dbell_type_q); +lsu_xu_dbell_brdcast_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => dbell_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(lsu_xu_dbell_brdcast_offset), + scout => sov(lsu_xu_dbell_brdcast_offset), + din => lsu_xu_dbell_brdcast , + dout => lsu_xu_dbell_brdcast_q); +lsu_xu_dbell_lpid_match_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => dbell_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(lsu_xu_dbell_lpid_match_offset), + scout => sov(lsu_xu_dbell_lpid_match_offset), + din => lsu_xu_dbell_lpid_match , + dout => lsu_xu_dbell_lpid_match_q); +lsu_xu_dbell_pirtag_latch : tri_rlmreg_p + generic map (width => lsu_xu_dbell_pirtag_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => dbell_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(lsu_xu_dbell_pirtag_offset to lsu_xu_dbell_pirtag_offset + lsu_xu_dbell_pirtag_q'length-1), + scout => sov(lsu_xu_dbell_pirtag_offset to lsu_xu_dbell_pirtag_offset + lsu_xu_dbell_pirtag_q'length-1), + din => lsu_xu_dbell_pirtag , + dout => lsu_xu_dbell_pirtag_q); +dbell_present_latch : tri_rlmreg_p + generic map (width => dbell_present_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(dbell_present_offset to dbell_present_offset + dbell_present_q'length-1), + scout => sov(dbell_present_offset to dbell_present_offset + dbell_present_q'length-1), + din => dbell_present_d, + dout => dbell_present_q); +cdbell_present_latch : tri_rlmreg_p + generic map (width => cdbell_present_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(cdbell_present_offset to cdbell_present_offset + cdbell_present_q'length-1), + scout => sov(cdbell_present_offset to cdbell_present_offset + cdbell_present_q'length-1), + din => cdbell_present_d, + dout => cdbell_present_q); +gdbell_present_latch : tri_rlmreg_p + generic map (width => gdbell_present_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(gdbell_present_offset to gdbell_present_offset + gdbell_present_q'length-1), + scout => sov(gdbell_present_offset to gdbell_present_offset + gdbell_present_q'length-1), + din => gdbell_present_d, + dout => gdbell_present_q); +gcdbell_present_latch : tri_rlmreg_p + generic map (width => gcdbell_present_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(gcdbell_present_offset to gcdbell_present_offset + gcdbell_present_q'length-1), + scout => sov(gcdbell_present_offset to gcdbell_present_offset + gcdbell_present_q'length-1), + din => gcdbell_present_d, + dout => gcdbell_present_q); +gmcdbell_present_latch : tri_rlmreg_p + generic map (width => gmcdbell_present_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(gmcdbell_present_offset to gmcdbell_present_offset + gmcdbell_present_q'length-1), + scout => sov(gmcdbell_present_offset to gmcdbell_present_offset + gmcdbell_present_q'length-1), + din => gmcdbell_present_d, + dout => gmcdbell_present_q); +xucr0_clfc_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(xucr0_clfc_offset), + scout => sov(xucr0_clfc_offset), + din => xucr0_clfc_d, + dout => xucr0_clfc_q); +iu_run_thread_latch : tri_rlmreg_p + generic map (width => iu_run_thread_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(iu_run_thread_offset to iu_run_thread_offset + iu_run_thread_q'length-1), + scout => sov(iu_run_thread_offset to iu_run_thread_offset + iu_run_thread_q'length-1), + din => iu_run_thread_d, + dout => iu_run_thread_q); +perf_event_latch : tri_rlmreg_p + generic map (width => perf_event_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(perf_event_offset to perf_event_offset + perf_event_q'length-1), + scout => sov(perf_event_offset to perf_event_offset + perf_event_q'length-1), + din => perf_event_d, + dout => perf_event_q); +inj_sprg_ecc_latch : tri_rlmreg_p + generic map (width => inj_sprg_ecc_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(inj_sprg_ecc_offset to inj_sprg_ecc_offset + inj_sprg_ecc_q'length-1), + scout => sov(inj_sprg_ecc_offset to inj_sprg_ecc_offset + inj_sprg_ecc_q'length-1), + din => pc_xu_inj_sprg_ecc , + dout => inj_sprg_ecc_q); +dbell_interrupt_latch : tri_rlmreg_p + generic map (width => dbell_interrupt_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(dbell_interrupt_offset to dbell_interrupt_offset + dbell_interrupt_q'length-1), + scout => sov(dbell_interrupt_offset to dbell_interrupt_offset + dbell_interrupt_q'length-1), + din => dbell_interrupt, + dout => dbell_interrupt_q); +cdbell_interrupt_latch : tri_rlmreg_p + generic map (width => cdbell_interrupt_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(cdbell_interrupt_offset to cdbell_interrupt_offset + cdbell_interrupt_q'length-1), + scout => sov(cdbell_interrupt_offset to cdbell_interrupt_offset + cdbell_interrupt_q'length-1), + din => cdbell_interrupt, + dout => cdbell_interrupt_q); +gdbell_interrupt_latch : tri_rlmreg_p + generic map (width => gdbell_interrupt_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(gdbell_interrupt_offset to gdbell_interrupt_offset + gdbell_interrupt_q'length-1), + scout => sov(gdbell_interrupt_offset to gdbell_interrupt_offset + gdbell_interrupt_q'length-1), + din => gdbell_interrupt, + dout => gdbell_interrupt_q); +gcdbell_interrupt_latch : tri_rlmreg_p + generic map (width => gcdbell_interrupt_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(gcdbell_interrupt_offset to gcdbell_interrupt_offset + gcdbell_interrupt_q'length-1), + scout => sov(gcdbell_interrupt_offset to gcdbell_interrupt_offset + gcdbell_interrupt_q'length-1), + din => gcdbell_interrupt, + dout => gcdbell_interrupt_q); +gmcdbell_interrupt_latch : tri_rlmreg_p + generic map (width => gmcdbell_interrupt_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(gmcdbell_interrupt_offset to gmcdbell_interrupt_offset + gmcdbell_interrupt_q'length-1), + scout => sov(gmcdbell_interrupt_offset to gmcdbell_interrupt_offset + gmcdbell_interrupt_q'length-1), + din => gmcdbell_interrupt, + dout => gmcdbell_interrupt_q); +iu_quiesce_latch : tri_rlmreg_p + generic map (width => iu_quiesce_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(iu_quiesce_offset to iu_quiesce_offset + iu_quiesce_q'length-1), + scout => sov(iu_quiesce_offset to iu_quiesce_offset + iu_quiesce_q'length-1), + din => iu_xu_quiesce , + dout => iu_quiesce_q); +lsu_quiesce_latch : tri_rlmreg_p + generic map (width => lsu_quiesce_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(lsu_quiesce_offset to lsu_quiesce_offset + lsu_quiesce_q'length-1), + scout => sov(lsu_quiesce_offset to lsu_quiesce_offset + lsu_quiesce_q'length-1), + din => lsu_xu_quiesce , + dout => lsu_quiesce_q); +mm_quiesce_latch : tri_rlmreg_p + generic map (width => mm_quiesce_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(mm_quiesce_offset to mm_quiesce_offset + mm_quiesce_q'length-1), + scout => sov(mm_quiesce_offset to mm_quiesce_offset + mm_quiesce_q'length-1), + din => mm_xu_quiesce , + dout => mm_quiesce_q); +bx_quiesce_latch : tri_rlmreg_p + generic map (width => bx_quiesce_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(bx_quiesce_offset to bx_quiesce_offset + bx_quiesce_q'length-1), + scout => sov(bx_quiesce_offset to bx_quiesce_offset + bx_quiesce_q'length-1), + din => bx_xu_quiesce , + dout => bx_quiesce_q); +quiesce_latch : tri_rlmreg_p + generic map (width => quiesce_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(quiesce_offset to quiesce_offset + quiesce_q'length-1), + scout => sov(quiesce_offset to quiesce_offset + quiesce_q'length-1), + din => quiesce_d, + dout => quiesce_q); +cpl_quiesce_latch : tri_rlmreg_p + generic map (width => cpl_quiesce_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(cpl_quiesce_offset to cpl_quiesce_offset + cpl_quiesce_q'length-1), + scout => sov(cpl_quiesce_offset to cpl_quiesce_offset + cpl_quiesce_q'length-1), + din => cpl_quiesce_d, + dout => cpl_quiesce_q); +quiesced_4cpl_latch : tri_rlmreg_p + generic map (width => quiesced_4cpl_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(quiesced_4cpl_offset to quiesced_4cpl_offset + quiesced_4cpl_q'length-1), + scout => sov(quiesced_4cpl_offset to quiesced_4cpl_offset + quiesced_4cpl_q'length-1), + din => quiesced_4cpl_d, + dout => quiesced_4cpl_q); +quiesced_latch : tri_rlmreg_p + generic map (width => quiesced_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(quiesced_offset to quiesced_offset + quiesced_q'length-1), + scout => sov(quiesced_offset to quiesced_offset + quiesced_q'length-1), + din => quiesced_d, + dout => quiesced_q); +instr_trace_mode_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(instr_trace_mode_offset), + scout => sov(instr_trace_mode_offset), + din => pc_xu_instr_trace_mode , + dout => instr_trace_mode_q); +instr_trace_tid_latch : tri_rlmreg_p + generic map (width => instr_trace_tid_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(instr_trace_tid_offset to instr_trace_tid_offset + instr_trace_tid_q'length-1), + scout => sov(instr_trace_tid_offset to instr_trace_tid_offset + instr_trace_tid_q'length-1), + din => pc_xu_instr_trace_tid , + dout => instr_trace_tid_q); +timer_update_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(timer_update_offset), + scout => sov(timer_update_offset), + din => timer_update_int, + dout => timer_update_q); + +spare_0_lcb: entity tri.tri_lcbnd(tri_lcbnd) + port map(vd => vdd, + gd => gnd, + act => tidn(0), + nclk => nclk, + forcee => func_sl_force, + thold_b => func_sl_thold_0_b, + delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), + mpw2_b => mpw2_dc_b, + sg => sg_0, + lclk => spare_0_lclk, + d1clk => spare_0_d1clk, + d2clk => spare_0_d2clk); +spare_0_latch : entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width => spare_0_q'length, expand_type => expand_type, btr => "NLI0001_X2_A12TH", init=>(spare_0_q'range=>'0')) + port map (vd => vdd, gd => gnd, + LCLK => spare_0_lclk, + D1CLK => spare_0_d1clk, + D2CLK => spare_0_d2clk, + SCANIN => siv(spare_0_offset to spare_0_offset + spare_0_q'length-1), + SCANOUT => sov(spare_0_offset to spare_0_offset + spare_0_q'length-1), + D => spare_0_d, + QB => spare_0_q); +spare_0_d <= not spare_0_q; +mark_unused(spare_0_q); + + +quiesced_fctr : entity work.xuq_cpl_fctr(xuq_cpl_fctr) +generic map (threads => threads, expand_type => expand_type, passthru => 0) +port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(quiesced_ctr_offset), + scout => sov(quiesced_ctr_offset), + delay => "1111", + din => quiesce_b_q, + dout => quiesce_ctr_zero_b); +quiesced_4cpl_fctr : entity work.xuq_cpl_fctr(xuq_cpl_fctr) +generic map (threads => threads, expand_type => expand_type, passthru => 0) +port map (nclk => nclk, vd => vdd, gd => gnd, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(quiesced_4cpl_ctr_offset), + scout => sov(quiesced_4cpl_ctr_offset), + delay => "1111", + din => cpl_quiesce_b_q, + dout => cpl_quiesce_ctr_zero_b); + + +siv( 0 to 399) <= sov( 1 to 399) & scan_in(0); +scan_out(0) <= sov( 0); + +siv(400 to siv'right) <= sov(401 to siv'right) & scan_in(1); +scan_out(1) <= sov(400); + + +bcfg_l : if sov_bcfg'length > 1 generate +siv_bcfg(0 to scan_right_bcfg-1) <= sov_bcfg(1 to scan_right_bcfg-1) & bcfg_scan_in; +bcfg_scan_out <= sov_bcfg(0); +end generate; +bcfg_s : if sov_bcfg'length <= 1 generate +bcfg_scan_out <= bcfg_scan_in; +sov_bcfg <= (others=>'0'); +siv_bcfg <= (others=>'0'); +end generate; + +ccfg_l : if sov_ccfg'length > 1 generate +siv_ccfg(0 to scan_right_ccfg-1) <= sov_ccfg(1 to scan_right_ccfg-1) & ccfg_scan_in; +ccfg_scan_out <= sov_ccfg(0); +end generate; +ccfg_s : if sov_ccfg'length <= 1 generate +ccfg_scan_out <= ccfg_scan_in; +sov_ccfg <= (others=>'0'); +siv_ccfg <= (others=>'0'); +end generate; + + +end architecture xuq_spr_cspr; diff --git a/rel/src/vhdl/work/xuq_spr_dacen.vhdl b/rel/src/vhdl/work/xuq_spr_dacen.vhdl new file mode 100644 index 0000000..640d3a8 --- /dev/null +++ b/rel/src/vhdl/work/xuq_spr_dacen.vhdl @@ -0,0 +1,82 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XU SPR - DAC Enable Component +-- + +library ieee; +use ieee.std_logic_1164.all; + +entity xuq_spr_dacen is +generic( + threads : integer := 4); +port( + spr_msr_pr : in std_ulogic_vector(0 to threads-1); + spr_msr_ds : in std_ulogic_vector(0 to threads-1); + + spr_dbcr0_dac : in std_ulogic_vector(0 to 2*threads-1); + spr_dbcr_dac_us : in std_ulogic_vector(0 to 2*threads-1); + spr_dbcr_dac_er : in std_ulogic_vector(0 to 2*threads-1); + + val : in std_ulogic_vector(0 to threads-1); + load : in std_ulogic; + store : in std_ulogic; + + dacr_en : out std_ulogic_vector(0 to threads-1); + dacw_en : out std_ulogic_vector(0 to threads-1) +); + +-- synopsys translate_off +-- synopsys translate_on + +end xuq_spr_dacen; +architecture xuq_spr_dacen of xuq_spr_dacen is + +-- Signals +signal dac_ld_en,dac_st_en : std_ulogic_vector(0 to threads-1); +signal dac_us_en,dac_er_en : std_ulogic_vector(0 to threads-1); + +begin + +dacen_gen : for t in 0 to threads-1 generate + + dac_ld_en(t) <= spr_dbcr0_dac(0+2*t) and load; + dac_st_en(t) <= spr_dbcr0_dac(1+2*t) and store; + + dac_us_en(t) <= (not spr_dbcr_dac_us(0+2*t) and not spr_dbcr_dac_us(1+2*t)) or + ( spr_dbcr_dac_us(0+2*t) and (spr_dbcr_dac_us(1+2*t) xnor spr_msr_pr(t))); + + dac_er_en(t) <= (not spr_dbcr_dac_er(0+2*t) and not spr_dbcr_dac_er(1+2*t)) or + ( spr_dbcr_dac_er(0+2*t) and (spr_dbcr_dac_er(1+2*t) xnor spr_msr_ds(t))); + + dacr_en(t) <= val(t) and dac_ld_en(t) and dac_us_en(t) and dac_er_en(t); + dacw_en(t) <= val(t) and dac_st_en(t) and dac_us_en(t) and dac_er_en(t); + +end generate; + +end architecture xuq_spr_dacen; diff --git a/rel/src/vhdl/work/xuq_spr_dvccmp.vhdl b/rel/src/vhdl/work/xuq_spr_dvccmp.vhdl new file mode 100644 index 0000000..d1fdfcf --- /dev/null +++ b/rel/src/vhdl/work/xuq_spr_dvccmp.vhdl @@ -0,0 +1,86 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XU SPR - DVC compare component +-- + +library ieee,ibm; +use ieee.std_logic_1164.all; +use ibm.std_ulogic_function_support.all; + +library tri; +use tri.tri_latches_pkg.all; +entity xuq_spr_dvccmp is +generic( + regsize : integer := 64); +port( + en : in std_ulogic; + en00 : in std_ulogic := '1'; + cmp : in std_ulogic_vector(8-regsize/8 to 7); + dvcm : in std_ulogic_vector(0 to 1); + dvcbe : in std_ulogic_vector(8-regsize/8 to 7); + dvc_cmpr : out std_ulogic +); + + +-- synopsys translate_off +-- synopsys translate_on +end xuq_spr_dvccmp; +architecture xuq_spr_dvccmp of xuq_spr_dvccmp is + +-- Signals +signal cmp_mask_or,cmp_mask_and : std_ulogic_vector(8-regsize/8 to 7); +signal cmp_and,cmp_or,cmp_andor : std_ulogic; + +begin + + cmp_mask_or <= gate((cmp or not dvcbe),or_reduce(dvcbe)); + cmp_mask_and <= (cmp and dvcbe); + + cmp_and <= and_reduce(cmp_mask_or); + + cmp_or <= or_reduce(cmp_mask_and); + + cmp_andor_gen32 : if regsize = 32 generate + cmp_andor <= (and_reduce(cmp_mask_or(4 to 5)) and or_reduce(dvcbe(4 to 5))) or + (and_reduce(cmp_mask_or(6 to 7)) and or_reduce(dvcbe(6 to 7))); + end generate; + cmp_andor_gen64 : if regsize = 64 generate + cmp_andor <= (and_reduce(cmp_mask_or(0 to 1)) and or_reduce(dvcbe(0 to 1))) or + (and_reduce(cmp_mask_or(2 to 3)) and or_reduce(dvcbe(2 to 3))) or + (and_reduce(cmp_mask_or(4 to 5)) and or_reduce(dvcbe(4 to 5))) or + (and_reduce(cmp_mask_or(6 to 7)) and or_reduce(dvcbe(6 to 7))); + end generate; + + with dvcm(0 to 1) select + dvc_cmpr <= en and en00 when "00", + en and cmp_and when "01", + en and cmp_or when "10", + en and cmp_andor when others; + +end architecture xuq_spr_dvccmp; diff --git a/rel/src/vhdl/work/xuq_spr_tspr.vhdl b/rel/src/vhdl/work/xuq_spr_tspr.vhdl new file mode 100644 index 0000000..b4d3905 --- /dev/null +++ b/rel/src/vhdl/work/xuq_spr_tspr.vhdl @@ -0,0 +1,4378 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- Description: XU SPR - per thread register slice +-- +library ieee,ibm,support,work,tri; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use support.power_logic_pkg.all; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use tri.tri_latches_pkg.all; +use work.xuq_pkg.all; + +entity xuq_spr_tspr is +generic( + hvmode : integer := 1; + a2mode : integer := 1; + expand_type : integer := 2; + regsize : integer := 64; + eff_ifar : integer := 62); +port( + nclk : in clk_logic; + + -- CHIP IO + an_ac_ext_interrupt : in std_ulogic; + an_ac_crit_interrupt : in std_ulogic; + an_ac_perf_interrupt : in std_ulogic; + an_ac_hang_pulse : in std_ulogic; + ac_tc_machine_check : out std_ulogic; + an_ac_external_mchk : in std_ulogic; + instr_trace_mode : in std_ulogic; + + d_mode_dc : in std_ulogic; + delay_lclkr_dc : in std_ulogic_vector(0 to 0); + mpw1_dc_b : in std_ulogic_vector(0 to 0); + mpw2_dc_b : in std_ulogic; + ccfg_sl_force : in std_ulogic; + ccfg_sl_thold_0_b : in std_ulogic; + dcfg_sl_force : in std_ulogic; + dcfg_sl_thold_0_b : in std_ulogic; + func_sl_force : in std_ulogic; + func_sl_thold_0_b : in std_ulogic; + func_slp_sl_force : in std_ulogic; + func_slp_sl_thold_0_b : in std_ulogic; + func_nsl_force : in std_ulogic; + func_nsl_thold_0_b : in std_ulogic; + sg_0 : in std_ulogic; + scan_in : in std_ulogic; + scan_out : out std_ulogic; + ccfg_scan_in : in std_ulogic; + ccfg_scan_out : out std_ulogic; + dcfg_scan_in : in std_ulogic; + dcfg_scan_out : out std_ulogic; + + cspr_tspr_rf1_act : in std_ulogic; + + -- Read Interface + cspr_tspr_ex1_instr : in std_ulogic_vector(0 to 31); + cspr_tspr_ex2_tid : in std_ulogic; + tspr_cspr_ex3_tspr_rt : out std_ulogic_vector(64-regsize to 63); + + -- Write Interface + dec_spr_ex4_val : in std_ulogic; + cspr_tspr_ex5_is_mtmsr : in std_ulogic; + cspr_tspr_ex5_is_mtspr : in std_ulogic; + cspr_tspr_ex5_is_wrtee : in std_ulogic; + cspr_tspr_ex5_is_wrteei : in std_ulogic; + cspr_tspr_ex5_instr : in std_ulogic_vector(11 to 20); + ex5_spr_wd : in std_ulogic_vector(64-regsize to 63); + + cspr_tspr_dec_dbg_dis : in std_ulogic; + + dec_spr_ex1_epid_instr : in std_ulogic; + fxu_spr_ex1_rs2 : in std_ulogic_vector(42 to 55); + spr_cpl_ex3_ct_be : out std_ulogic; + spr_cpl_ex3_ct_le : out std_ulogic; + + -- Illegal SPR + tspr_cspr_illeg_mtspr_b : out std_ulogic; + tspr_cspr_illeg_mfspr_b : out std_ulogic; + tspr_cspr_hypv_mtspr : out std_ulogic; + tspr_cspr_hypv_mfspr : out std_ulogic; + + -- Interrupt Interface + cpl_spr_ex5_act : in std_ulogic; + cpl_spr_ex5_int : in std_ulogic; + cpl_spr_ex5_gint : in std_ulogic; + cpl_spr_ex5_cint : in std_ulogic; + cpl_spr_ex5_mcint : in std_ulogic; + cpl_spr_ex5_nia : in std_ulogic_vector(62-eff_ifar to 61); + cpl_spr_ex5_esr : in std_ulogic_vector(0 to 16); + cpl_spr_ex5_mcsr : in std_ulogic_vector(0 to 14); + cpl_spr_ex5_dbsr : in std_ulogic_vector(0 to 18); + cpl_spr_ex5_dear_save : in std_ulogic; + cpl_spr_ex5_dear_update : in std_ulogic; + cpl_spr_ex5_dear_update_saved : in std_ulogic; + cpl_spr_ex5_dbsr_update : in std_ulogic; + cpl_spr_ex5_esr_update : in std_ulogic; + cpl_spr_ex5_srr0_dec : in std_ulogic; + cpl_spr_ex5_force_gsrr : in std_ulogic; + cpl_spr_ex5_dbsr_ide : in std_ulogic; + spr_cpl_dbsr_ide : out std_ulogic; + + -- Async Interrupt Req Interface + spr_cpl_external_mchk : out std_ulogic; + spr_cpl_ext_interrupt : out std_ulogic; + spr_cpl_dec_interrupt : out std_ulogic; + spr_cpl_udec_interrupt : out std_ulogic; + spr_cpl_perf_interrupt : out std_ulogic; + spr_cpl_fit_interrupt : out std_ulogic; + spr_cpl_crit_interrupt : out std_ulogic; + spr_cpl_wdog_interrupt : out std_ulogic; + + cspr_tspr_crit_mask : in std_ulogic; + cspr_tspr_wdog_mask : in std_ulogic; + cspr_tspr_dec_mask : in std_ulogic; + cspr_tspr_udec_mask : in std_ulogic; + cspr_tspr_perf_mask : in std_ulogic; + cspr_tspr_fit_mask : in std_ulogic; + cspr_tspr_ext_mask : in std_ulogic; + + tspr_cspr_pm_wake_up : out std_ulogic; + tspr_cspr_async_int : out std_ulogic_vector(0 to 2); + + -- DBELL Int + cspr_tspr_dbell_pirtag : in std_ulogic_vector(50 to 63); + tspr_cspr_gpir_match : out std_ulogic; + + cspr_tspr_timebase_taps : in std_ulogic_vector(0 to 9); + timer_update : in std_ulogic; + + -- Debug + spr_cpl_iac1_en : out std_ulogic; + spr_cpl_iac2_en : out std_ulogic; + spr_cpl_iac3_en : out std_ulogic; + spr_cpl_iac4_en : out std_ulogic; + tspr_cspr_freeze_timers : out std_ulogic; + + -- Flush + xu_ex4_flush : in std_ulogic; + xu_ex5_flush : in std_ulogic; + + -- Run State + xu_iu_single_instr_mode : out std_ulogic; + xu_iu_raise_iss_pri : out std_ulogic; + + -- LiveLock + cpl_spr_ex5_instr_cpl : in std_ulogic; + cspr_tspr_llen : in std_ulogic; + cspr_tspr_llpri : in std_ulogic; + tspr_cspr_lldet : out std_ulogic; + tspr_cspr_llpulse : out std_ulogic; + xu_pc_err_llbust_attempt : out std_ulogic; + xu_pc_err_llbust_failed : out std_ulogic; + pc_xu_inj_llbust_attempt : in std_ulogic; + pc_xu_inj_llbust_failed : in std_ulogic; + + -- Resets + pc_xu_inj_wdt_reset : in std_ulogic; + reset_wd_complete : in std_ulogic; + reset_1_complete : in std_ulogic; + reset_2_complete : in std_ulogic; + reset_3_complete : in std_ulogic; + reset_1_request : out std_ulogic; + reset_2_request : out std_ulogic; + reset_3_request : out std_ulogic; + reset_wd_request : out std_ulogic; + xu_pc_err_wdt_reset : out std_ulogic; + + -- XER + spr_byp_ex4_is_mtxer : out std_ulogic; + spr_byp_ex4_is_mfxer : out std_ulogic; + + -- MSR Override + cspr_tspr_ram_mode : in std_ulogic; + cspr_tspr_msrovride_en : in std_ulogic; + pc_xu_msrovride_pr : in std_ulogic; + pc_xu_msrovride_gs : in std_ulogic; + pc_xu_msrovride_de : in std_ulogic; + + -- SPRs + cpl_spr_dbcr0_edm : in std_ulogic; + lsu_xu_spr_epsc_egs : in std_ulogic; + lsu_xu_spr_epsc_epr : in std_ulogic; + tspr_msr_de : out std_ulogic; + tspr_msr_cm : out std_ulogic; + tspr_msr_pr : out std_ulogic; + tspr_msr_is : out std_ulogic; + tspr_msr_gs : out std_ulogic; + tspr_msr_ee : out std_ulogic; + tspr_msr_ce : out std_ulogic; + tspr_msr_me : out std_ulogic; + tspr_fp_precise : out std_ulogic; + tspr_epcr_extgs : out std_ulogic; + cspr_xucr0_clkg_ctl : in std_ulogic_vector(4 to 4); + spr_dbcr0_idm : out std_ulogic; + spr_dbcr0_icmp : out std_ulogic; + spr_dbcr0_brt : out std_ulogic; + spr_dbcr0_irpt : out std_ulogic; + spr_dbcr0_trap : out std_ulogic; + spr_dbcr0_dac1 : out std_ulogic_vector(0 to 1); + spr_dbcr0_dac2 : out std_ulogic_vector(0 to 1); + spr_dbcr0_ret : out std_ulogic; + spr_dbcr0_dac3 : out std_ulogic_vector(0 to 1); + spr_dbcr0_dac4 : out std_ulogic_vector(0 to 1); + spr_dbcr1_iac12m : out std_ulogic; + spr_dbcr1_iac34m : out std_ulogic; + spr_epcr_dtlbgs : out std_ulogic; + spr_epcr_itlbgs : out std_ulogic; + spr_epcr_dsigs : out std_ulogic; + spr_epcr_isigs : out std_ulogic; + spr_epcr_duvd : out std_ulogic; + spr_epcr_dgtmi : out std_ulogic; + xu_mm_spr_epcr_dmiuh : out std_ulogic; + spr_msr_ucle : out std_ulogic; + spr_msr_spv : out std_ulogic; + spr_msr_fp : out std_ulogic; + spr_msr_ds : out std_ulogic; + spr_msrp_uclep : out std_ulogic; + + tspr_debug : out std_ulogic_vector(0 to 11); + + -- Power + vdd : inout power_logic; + gnd : inout power_logic +); + +-- synopsys translate_off + +-- synopsys translate_on +end xuq_spr_tspr; +architecture xuq_spr_tspr of xuq_spr_tspr is + +constant DEX2 : natural := 0; +constant DEX3 : natural := 0; +constant DEX4 : natural := 0; +constant DEX5 : natural := 0; +constant DEX6 : natural := 0; +constant DWR : natural := 0; +constant DX : natural := 0; +-- Types +subtype s2 is std_ulogic_vector(0 to 1); +subtype s3 is std_ulogic_vector(0 to 2); +subtype s4 is std_ulogic_vector(0 to 3); +subtype s5 is std_ulogic_vector(0 to 4); +subtype DO is std_ulogic_vector(65-regsize to 64); +-- SPR Bit Constants +constant MSR_CM : natural := 50; +constant MSR_GS : natural := 51; +constant MSR_UCLE : natural := 52; +constant MSR_SPV : natural := 53; +constant MSR_CE : natural := 54; +constant MSR_EE : natural := 55; +constant MSR_PR : natural := 56; +constant MSR_FP : natural := 57; +constant MSR_ME : natural := 58; +constant MSR_FE0 : natural := 59; +constant MSR_DE : natural := 60; +constant MSR_FE1 : natural := 61; +constant MSR_IS : natural := 62; +constant MSR_DS : natural := 63; +constant MSRP_UCLEP : natural := 62; +constant MSRP_DEP : natural := 63; +-- SPR Registers +signal acop_d , acop_q : std_ulogic_vector(32 to 63); +signal ccr3_d , ccr3_q : std_ulogic_vector(62 to 63); +signal csrr0_d , csrr0_q : std_ulogic_vector(64-(eff_ifar) to 63); +signal csrr1_d , csrr1_q : std_ulogic_vector(50 to 63); +signal dbcr0_d , dbcr0_q : std_ulogic_vector(43 to 63); +signal dbcr1_d , dbcr1_q : std_ulogic_vector(46 to 63); +signal dbsr_d , dbsr_q : std_ulogic_vector(44 to 63); +signal dear_d , dear_q : std_ulogic_vector(64-(regsize) to 63); +signal dec_d , dec_q : std_ulogic_vector(32 to 63); +signal decar_d , decar_q : std_ulogic_vector(32 to 63); +signal epcr_d , epcr_q : std_ulogic_vector(54 to 63); +signal esr_d , esr_q : std_ulogic_vector(47 to 63); +signal gdear_d , gdear_q : std_ulogic_vector(64-(regsize) to 63); +signal gesr_d , gesr_q : std_ulogic_vector(47 to 63); +signal gpir_d , gpir_q : std_ulogic_vector(32 to 63); +signal gsrr0_d , gsrr0_q : std_ulogic_vector(64-(eff_ifar) to 63); +signal gsrr1_d , gsrr1_q : std_ulogic_vector(50 to 63); +signal hacop_d , hacop_q : std_ulogic_vector(32 to 63); +signal mcsr_d , mcsr_q : std_ulogic_vector(49 to 63); +signal mcsrr0_d , mcsrr0_q : std_ulogic_vector(64-(eff_ifar) to 63); +signal mcsrr1_d , mcsrr1_q : std_ulogic_vector(50 to 63); +signal msr_d , msr_q : std_ulogic_vector(50 to 63); +signal msrp_d , msrp_q : std_ulogic_vector(62 to 63); +signal srr0_d , srr0_q : std_ulogic_vector(64-(eff_ifar) to 63); +signal srr1_d , srr1_q : std_ulogic_vector(50 to 63); +signal tcr_d , tcr_q : std_ulogic_vector(52 to 63); +signal tsr_d , tsr_q : std_ulogic_vector(59 to 63); +signal udec_d , udec_q : std_ulogic_vector(32 to 63); +signal xucr1_d , xucr1_q : std_ulogic_vector(59 to 63); +-- FUNC Scanchain +constant acop_offset : natural := 0; +constant csrr0_offset : natural := acop_offset + acop_q'length*a2mode; +constant csrr1_offset : natural := csrr0_offset + csrr0_q'length*a2mode; +constant dbcr1_offset : natural := csrr1_offset + csrr1_q'length*a2mode; +constant dbsr_offset : natural := dbcr1_offset + dbcr1_q'length; +constant dear_offset : natural := dbsr_offset + dbsr_q'length; +constant dec_offset : natural := dear_offset + dear_q'length; +constant decar_offset : natural := dec_offset + dec_q'length; +constant epcr_offset : natural := decar_offset + decar_q'length*a2mode; +constant esr_offset : natural := epcr_offset + epcr_q'length*hvmode; +constant gdear_offset : natural := esr_offset + esr_q'length; +constant gesr_offset : natural := gdear_offset + gdear_q'length*hvmode; +constant gpir_offset : natural := gesr_offset + gesr_q'length*hvmode; +constant gsrr0_offset : natural := gpir_offset + gpir_q'length*hvmode; +constant gsrr1_offset : natural := gsrr0_offset + gsrr0_q'length*hvmode; +constant hacop_offset : natural := gsrr1_offset + gsrr1_q'length*hvmode; +constant mcsr_offset : natural := hacop_offset + hacop_q'length*hvmode; +constant mcsrr0_offset : natural := mcsr_offset + mcsr_q'length*a2mode; +constant mcsrr1_offset : natural := mcsrr0_offset + mcsrr0_q'length*a2mode; +constant msrp_offset : natural := mcsrr1_offset + mcsrr1_q'length*a2mode; +constant srr0_offset : natural := msrp_offset + msrp_q'length*hvmode; +constant srr1_offset : natural := srr0_offset + srr0_q'length; +constant tcr_offset : natural := srr1_offset + srr1_q'length; +constant tsr_offset : natural := tcr_offset + tcr_q'length*a2mode; +constant udec_offset : natural := tsr_offset + tsr_q'length*a2mode; +constant last_reg_offset : natural := udec_offset + udec_q'length*a2mode; +-- BCFG Scanchain +constant last_reg_offset_bcfg : natural := 1; +-- CCFG Scanchain +constant ccr3_offset_ccfg : natural := 0; +constant msr_offset_ccfg : natural := ccr3_offset_ccfg + ccr3_q'length; +constant xucr1_offset_ccfg : natural := msr_offset_ccfg + msr_q'length; +constant last_reg_offset_ccfg : natural := xucr1_offset_ccfg + xucr1_q'length; +-- DCFG Scanchain +constant dbcr0_offset_dcfg : natural := 0; +constant last_reg_offset_dcfg : natural := dbcr0_offset_dcfg + dbcr0_q'length; +-- Latches +signal exx_act_q, exx_act_d : std_ulogic_vector(1 to 5); -- input=>exx_act_d , act=>tiup , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex2_is_mfspr_q, ex1_is_mfspr : std_ulogic; -- input=>ex1_is_mfspr , act=>exx_act(1) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex2_is_mtspr_q, ex1_is_mtspr : std_ulogic; -- input=>ex1_is_mtspr , act=>exx_act(1) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex2_is_mfmsr_q, ex1_is_mfmsr : std_ulogic; -- input=>ex1_is_mfmsr , act=>exx_act(1) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex2_instr_q, ex2_instr_d : std_ulogic_vector(11 to 20); -- input=>ex2_instr_d , act=>exx_act(1) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex3_is_mtxer_q, ex3_is_mtxer_d : std_ulogic; -- input=>ex3_is_mtxer_d , act=>exx_act(2) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex3_is_mfxer_q, ex3_is_mfxer_d : std_ulogic; -- input=>ex3_is_mfxer_d , act=>exx_act(2) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex2_rfi_q, ex2_rfi_d : std_ulogic; -- input=>ex2_rfi_d , act=>exx_act(1) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex2_rfgi_q, ex2_rfgi_d : std_ulogic; -- input=>ex2_rfgi_d , act=>exx_act(1) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex2_rfci_q, ex1_is_rfci : std_ulogic; -- input=>ex1_is_rfci , act=>exx_act(1) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex2_rfmci_q, ex1_is_rfmci : std_ulogic; -- input=>ex1_is_rfmci , act=>exx_act(1) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex3_rfi_q : std_ulogic; -- input=>ex2_rfi_q , act=>exx_act(2) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex3_rfgi_q : std_ulogic; -- input=>ex2_rfgi_q , act=>exx_act(2) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex3_rfci_q : std_ulogic; -- input=>ex2_rfci_q , act=>exx_act(2) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex3_rfmci_q : std_ulogic; -- input=>ex2_rfmci_q , act=>exx_act(2) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex4_is_mfxer_q : std_ulogic; -- input=>ex3_is_mfxer_q , act=>exx_act(3) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex4_is_mtxer_q : std_ulogic; -- input=>ex3_is_mtxer_q , act=>exx_act(3) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex4_rfi_q : std_ulogic; -- input=>ex3_rfi_q , act=>exx_act(3) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex4_rfgi_q : std_ulogic; -- input=>ex3_rfgi_q , act=>exx_act(3) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex4_rfci_q : std_ulogic; -- input=>ex3_rfci_q , act=>exx_act(3) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex4_rfmci_q : std_ulogic; -- input=>ex3_rfmci_q , act=>exx_act(3) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex5_val_q, ex4_val : std_ulogic; -- input=>ex4_val , act=>tiup , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex5_rfi_q : std_ulogic; -- input=>ex4_rfi_q , act=>exx_act(4) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex5_rfgi_q : std_ulogic; -- input=>ex4_rfgi_q , act=>exx_act(4) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex5_rfci_q : std_ulogic; -- input=>ex4_rfci_q , act=>exx_act(4) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex5_rfmci_q : std_ulogic; -- input=>ex4_rfmci_q , act=>exx_act(4) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex6_val_q, ex5_val : std_ulogic; -- input=>ex5_val , act=>tiup , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex6_rfi_q : std_ulogic; -- input=>ex5_rfi_q , act=>exx_act(5) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex6_rfgi_q : std_ulogic; -- input=>ex5_rfgi_q , act=>exx_act(5) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex6_rfci_q : std_ulogic; -- input=>ex5_rfci_q , act=>exx_act(5) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex6_rfmci_q : std_ulogic; -- input=>ex5_rfmci_q , act=>exx_act(5) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex6_wrtee_q : std_ulogic; -- input=>cspr_tspr_ex5_is_wrtee , act=>exx_act(5) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex6_wrteei_q : std_ulogic; -- input=>cspr_tspr_ex5_is_wrteei , act=>exx_act(5) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex6_is_mtmsr_q : std_ulogic; -- input=>cspr_tspr_ex5_is_mtmsr , act=>exx_act(5) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex6_is_mtspr_q : std_ulogic; -- input=>cspr_tspr_ex5_is_mtspr , act=>exx_act(5) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex6_instr_q : std_ulogic_vector(11 to 20); -- input=>cspr_tspr_ex5_instr , act=>exx_act(5) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex6_int_q : std_ulogic; -- input=>cpl_spr_ex5_int , act=>ex5_int_act , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 +signal ex6_gint_q : std_ulogic; -- input=>cpl_spr_ex5_gint , act=>ex5_int_act , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 +signal ex6_cint_q : std_ulogic; -- input=>cpl_spr_ex5_cint , act=>ex5_int_act , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 +signal ex6_mcint_q : std_ulogic; -- input=>cpl_spr_ex5_mcint , act=>ex5_int_act , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 +signal ex6_nia_q : std_ulogic_vector(62-eff_ifar to 61); -- input=>cpl_spr_ex5_nia , act=>ex5_int_act , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 +signal ex6_esr_q : std_ulogic_vector(0 to 16); -- input=>cpl_spr_ex5_esr , act=>cpl_spr_ex5_esr_update , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 +signal ex6_mcsr_q : std_ulogic_vector(0 to 14); -- input=>cpl_spr_ex5_mcsr , act=>ex5_int_act , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 +signal ex6_dbsr_q : std_ulogic_vector(0 to 18); -- input=>cpl_spr_ex5_dbsr , act=>cpl_spr_ex5_dbsr_update , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 +signal ex6_dear_save_q : std_ulogic; -- input=>cpl_spr_ex5_dear_save , act=>tiup , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 +signal ex6_dear_update_q : std_ulogic; -- input=>cpl_spr_ex5_dear_update , act=>tiup , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 +signal ex6_dear_update_saved_q : std_ulogic; -- input=>cpl_spr_ex5_dear_update_saved, act=>tiup , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 +signal ex6_dbsr_update_q : std_ulogic; -- input=>cpl_spr_ex5_dbsr_update , act=>tiup , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 +signal ex6_esr_update_q : std_ulogic; -- input=>cpl_spr_ex5_esr_update , act=>tiup , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 +signal ex6_srr0_dec_q : std_ulogic; -- input=>cpl_spr_ex5_srr0_dec , act=>tiup , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 +signal ex6_force_gsrr_q : std_ulogic; -- input=>cpl_spr_ex5_force_gsrr , act=>ex5_int_act , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 +signal ex6_dbsr_ide_q : std_ulogic; -- input=>cpl_spr_ex5_dbsr_ide , act=>ex5_int_act , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 +signal ex6_spr_wd_q : std_ulogic_vector(64-regsize to 63); -- input=>ex5_spr_wd , act=>exx_act_data(5), scan=>N, sleep=>N, ring=>func, needs_sreset=>1 +signal fit_tb_tap_q, fit_tb_tap_d : std_ulogic; -- input=>fit_tb_tap_d , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal wdog_tb_tap_q, wdog_tb_tap_d : std_ulogic; -- input=>wdog_tb_tap_d , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal hang_pulse_q, hang_pulse_d : std_ulogic_vector(0 to 3); -- input=>hang_pulse_d , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal lltap_q, lltap_d : std_ulogic; -- input=>lltap_d , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal llcnt_q, llcnt_d : std_ulogic_vector(0 to 1); -- input=>llcnt_d , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal msrovride_pr_q : std_ulogic; -- input=>pc_xu_msrovride_pr , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal msrovride_gs_q : std_ulogic; -- input=>pc_xu_msrovride_gs , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal msrovride_de_q : std_ulogic; -- input=>pc_xu_msrovride_de , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal an_ac_ext_interrupt_q : std_ulogic; -- input=>an_ac_ext_interrupt , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal an_ac_crit_interrupt_q : std_ulogic; -- input=>an_ac_crit_interrupt , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal an_ac_perf_interrupt_q : std_ulogic; -- input=>an_ac_perf_interrupt , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal dear_tmp_q, dear_tmp_d : std_ulogic_vector(dear_q'range); -- input=>dear_tmp_d , act=>ex6_dear_save_q, scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal mux_msr_gs_q, mux_msr_gs_d : std_ulogic_vector(0 to 3); -- input=>mux_msr_gs_d , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>0 +signal mux_msr_pr_q, mux_msr_pr_d : std_ulogic_vector(0 to 0); -- input=>mux_msr_pr_d , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>0 +signal ex3_tspr_rt_q, ex3_tspr_rt_d : std_ulogic_vector(64-regsize to 63); -- input=>ex3_tspr_rt_d , act=>exx_act_data(2), scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal err_llbust_attempt_q, err_llbust_attempt_d : std_ulogic; -- input=>err_llbust_attempt_d , act=>tiup , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal err_llbust_failed_q, err_llbust_failed_d : std_ulogic; -- input=>err_llbust_failed_d , act=>tiup , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal inj_llbust_attempt_q : std_ulogic; -- input=>pc_xu_inj_llbust_attempt , act=>tiup , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal inj_llbust_failed_q : std_ulogic; -- input=>pc_xu_inj_llbust_failed , act=>tiup , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex2_rs2_q : std_ulogic_vector(42 to 55); -- input=>fxu_spr_ex1_rs2 , act=>exx_act(1) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal ex3_ct_q, ex3_ct_d : std_ulogic_vector(0 to 1); -- input=>ex3_ct_d , act=>exx_act(2) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal an_ac_external_mchk_q : std_ulogic; -- input=>an_ac_external_mchk , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal mchk_int_q, mchk_int : std_ulogic; -- input=>mchk_int , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal mchk_interrupt_q, mchk_interrupt : std_ulogic; -- input=>mchk_interrupt , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal crit_interrupt_q, crit_interrupt : std_ulogic; -- input=>crit_interrupt , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal wdog_interrupt_q, wdog_interrupt : std_ulogic; -- input=>wdog_interrupt , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal dec_interrupt_q, dec_interrupt : std_ulogic; -- input=>dec_interrupt , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal udec_interrupt_q, udec_interrupt : std_ulogic; -- input=>udec_interrupt , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal perf_interrupt_q, perf_interrupt : std_ulogic; -- input=>perf_interrupt , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal fit_interrupt_q, fit_interrupt : std_ulogic; -- input=>fit_interrupt , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal ext_interrupt_q, ext_interrupt : std_ulogic; -- input=>ext_interrupt , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal single_instr_mode_q, single_instr_mode_d : std_ulogic; -- input=>single_instr_mode_d , act=>tiup , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 +signal single_instr_mode_2_q : std_ulogic; -- input=>single_instr_mode_q , act=>tiup , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 +signal machine_check_q, machine_check_d : std_ulogic; -- input=>machine_check_d , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal raise_iss_pri_q, raise_iss_pri_d : std_ulogic; -- input=>raise_iss_pri_d , act=>tiup , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 +signal raise_iss_pri_2_q : std_ulogic; -- input=>raise_iss_pri_q , act=>tiup , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 +signal epsc_egs_q : std_ulogic; -- input=>lsu_xu_spr_epsc_egs , act=>tiup , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal epsc_epr_q : std_ulogic; -- input=>lsu_xu_spr_epsc_epr , act=>tiup , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ex2_epid_instr_q : std_ulogic; -- input=>dec_spr_ex1_epid_instr , act=>exx_act(1) , scan=>N, sleep=>N, ring=>func, needs_sreset=>0 +signal pc_xu_inj_wdt_reset_q : std_ulogic; -- input=>pc_xu_inj_wdt_reset , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal err_wdt_reset_q, err_wdt_reset_d : std_ulogic; -- input=>err_wdt_reset_d , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 +signal ex3_tid_rpwr_q, ex3_tid_rpwr_d : std_ulogic_vector(0 to regsize/8-1); -- input=>ex3_tid_rpwr_d , act=>exx_act(2) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>0 +signal ram_mode_q : std_ulogic; -- input=>cspr_tspr_ram_mode , act=>tiup , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 +signal timebase_taps_q : std_ulogic_vector(cspr_tspr_timebase_taps'range);-- input=>cspr_tspr_timebase_taps , act=>tiup , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>0 +signal dbsr_mrr_q, dbsr_mrr_d : std_ulogic_vector(0 to 1); -- input=>dbsr_mrr_d , act=>dbsr_mrr_act , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 +signal tsr_wrs_q, tsr_wrs_d : std_ulogic_vector(0 to 1); -- input=>tsr_wrs_d , act=>tsr_wrs_act , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 +signal iac1_en_q, iac1_en_d : std_ulogic; -- input=>iac1_en_d , act=>tiup , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 +signal iac2_en_q, iac2_en_d : std_ulogic; -- input=>iac2_en_d , act=>tiup , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 +signal iac3_en_q, iac3_en_d : std_ulogic; -- input=>iac3_en_d , act=>tiup , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 +signal iac4_en_q, iac4_en_d : std_ulogic; -- input=>iac4_en_d , act=>tiup , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 +signal spare_0_q, spare_0_d : std_ulogic_vector(0 to 13); -- input=>spare_0_d, act=>tiup, +-- Scanchain +constant exx_act_offset : integer := last_reg_offset; +constant ex3_is_mtxer_offset : integer := exx_act_offset + exx_act_q'length; +constant ex3_is_mfxer_offset : integer := ex3_is_mtxer_offset + 1; +constant ex3_rfi_offset : integer := ex3_is_mfxer_offset + 1; +constant ex3_rfgi_offset : integer := ex3_rfi_offset + 1; +constant ex3_rfci_offset : integer := ex3_rfgi_offset + 1; +constant ex3_rfmci_offset : integer := ex3_rfci_offset + 1; +constant ex5_val_offset : integer := ex3_rfmci_offset + 1; +constant ex5_rfi_offset : integer := ex5_val_offset + 1; +constant ex5_rfgi_offset : integer := ex5_rfi_offset + 1; +constant ex5_rfci_offset : integer := ex5_rfgi_offset + 1; +constant ex5_rfmci_offset : integer := ex5_rfci_offset + 1; +constant ex6_val_offset : integer := ex5_rfmci_offset + 1; +constant fit_tb_tap_offset : integer := ex6_val_offset + 1; +constant wdog_tb_tap_offset : integer := fit_tb_tap_offset + 1; +constant hang_pulse_offset : integer := wdog_tb_tap_offset + 1; +constant lltap_offset : integer := hang_pulse_offset + hang_pulse_q'length; +constant llcnt_offset : integer := lltap_offset + 1; +constant msrovride_pr_offset : integer := llcnt_offset + llcnt_q'length; +constant msrovride_gs_offset : integer := msrovride_pr_offset + 1; +constant msrovride_de_offset : integer := msrovride_gs_offset + 1; +constant an_ac_ext_interrupt_offset : integer := msrovride_de_offset + 1; +constant an_ac_crit_interrupt_offset : integer := an_ac_ext_interrupt_offset + 1; +constant an_ac_perf_interrupt_offset : integer := an_ac_crit_interrupt_offset + 1; +constant dear_tmp_offset : integer := an_ac_perf_interrupt_offset + 1; +constant mux_msr_gs_offset : integer := dear_tmp_offset + dear_tmp_q'length; +constant mux_msr_pr_offset : integer := mux_msr_gs_offset + mux_msr_gs_q'length; +constant ex3_tspr_rt_offset : integer := mux_msr_pr_offset + mux_msr_pr_q'length; +constant err_llbust_attempt_offset : integer := ex3_tspr_rt_offset + ex3_tspr_rt_q'length; +constant err_llbust_failed_offset : integer := err_llbust_attempt_offset + 1; +constant inj_llbust_attempt_offset : integer := err_llbust_failed_offset + 1; +constant inj_llbust_failed_offset : integer := inj_llbust_attempt_offset + 1; +constant ex3_ct_offset : integer := inj_llbust_failed_offset + 1; +constant an_ac_external_mchk_offset : integer := ex3_ct_offset + ex3_ct_q'length; +constant mchk_int_offset : integer := an_ac_external_mchk_offset + 1; +constant mchk_interrupt_offset : integer := mchk_int_offset + 1; +constant crit_interrupt_offset : integer := mchk_interrupt_offset + 1; +constant wdog_interrupt_offset : integer := crit_interrupt_offset + 1; +constant dec_interrupt_offset : integer := wdog_interrupt_offset + 1; +constant udec_interrupt_offset : integer := dec_interrupt_offset + 1; +constant perf_interrupt_offset : integer := udec_interrupt_offset + 1; +constant fit_interrupt_offset : integer := perf_interrupt_offset + 1; +constant ext_interrupt_offset : integer := fit_interrupt_offset + 1; +constant single_instr_mode_offset : integer := ext_interrupt_offset + 1; +constant single_instr_mode_2_offset : integer := single_instr_mode_offset + 1; +constant machine_check_offset : integer := single_instr_mode_2_offset + 1; +constant raise_iss_pri_offset : integer := machine_check_offset + 1; +constant raise_iss_pri_2_offset : integer := raise_iss_pri_offset + 1; +constant epsc_egs_offset : integer := raise_iss_pri_2_offset + 1; +constant epsc_epr_offset : integer := epsc_egs_offset + 1; +constant pc_xu_inj_wdt_reset_offset : integer := epsc_epr_offset + 1; +constant err_wdt_reset_offset : integer := pc_xu_inj_wdt_reset_offset + 1; +constant ex3_tid_rpwr_offset : integer := err_wdt_reset_offset + 1; +constant ram_mode_offset : integer := ex3_tid_rpwr_offset + ex3_tid_rpwr_q'length; +constant timebase_taps_offset : integer := ram_mode_offset + 1; +constant dbsr_mrr_offset : integer := timebase_taps_offset + timebase_taps_q'length; +constant tsr_wrs_offset : integer := dbsr_mrr_offset + dbsr_mrr_q'length; +constant iac1_en_offset : integer := tsr_wrs_offset + tsr_wrs_q'length; +constant iac2_en_offset : integer := iac1_en_offset + 1; +constant iac3_en_offset : integer := iac2_en_offset + 1; +constant iac4_en_offset : integer := iac3_en_offset + 1; +constant spare_0_offset : integer := iac4_en_offset + 1; +constant scan_right : integer := spare_0_offset + spare_0_q'length; +signal siv : std_ulogic_vector(0 to scan_right-1); +signal sov : std_ulogic_vector(0 to scan_right-1); +constant scan_right_ccfg : integer := last_reg_offset_ccfg; +signal siv_ccfg : std_ulogic_vector(0 to scan_right_ccfg-1); +signal sov_ccfg : std_ulogic_vector(0 to scan_right_ccfg-1); +constant scan_right_dcfg : integer := last_reg_offset_dcfg; +signal siv_dcfg : std_ulogic_vector(0 to scan_right_dcfg-1); +signal sov_dcfg : std_ulogic_vector(0 to scan_right_dcfg-1); +-- Signals +signal tiup : std_ulogic; +signal tidn : std_ulogic_vector(00 to 63); +signal spare_0_lclk : clk_logic; +signal spare_0_d1clk, spare_0_d2clk : std_ulogic; +signal ex1_opcode_is_31 : boolean; +signal ex1_opcode_is_19 : boolean; +signal ex1_is_rfi, ex1_is_rfgi : std_ulogic; +signal ex2_is_mfmsr : std_ulogic; +signal ex2_is_mfspr : std_ulogic; +signal ex2_is_mtspr : std_ulogic; +signal ex2_instr : std_ulogic_vector(11 to 20); +signal ex6_val : std_ulogic; +signal ex6_is_mtmsr : std_ulogic; +signal ex6_is_mtspr : std_ulogic; +signal ex6_instr : std_ulogic_vector(11 to 20); +signal ex6_any_int, ex6_any_hint : std_ulogic; +signal ex6_msr_di2 : std_ulogic_vector(msr_q'range); +signal ex6_msr_mask : std_ulogic_vector(msr_q'range); +signal ex6_msr_mux : std_ulogic_vector(msr_q'range); +signal ex6_msr_in : std_ulogic_vector(msr_q'range); +signal ex6_csrr1_d,ex6_mcsrr1_d : std_ulogic_vector(msr_q'range); +signal ex6_gsrr1_d,ex6_srr1_d : std_ulogic_vector(msr_q'range); +signal ex6_rfgi_msr : std_ulogic_vector(msr_q'range); +signal ex6_nia_srr0 : std_ulogic_vector(srr0_q'range); +signal ex6_nia_srr0_dec : std_ulogic_vector(srr0_q'range); +signal ex6_dec_zero,ex6_dec_upper_zero : std_ulogic; +signal ex6_udec_zero,ex6_udec_upper_zero : std_ulogic; +signal ex6_set_tsr_udis : std_ulogic; +signal ex6_set_tsr_dis : std_ulogic; +signal ex6_set_tsr_fis : std_ulogic; +signal ex6_set_tsr_wis : std_ulogic; +signal ex6_set_tsr_enw : std_ulogic; +signal ex6_set_tsr : std_ulogic_vector(tsr_q'range); +signal ex6_spr_wd : std_ulogic_vector(64-regsize to 63); +signal wdog_pulse : std_ulogic; +signal lltbtap, llpulse, llreset : std_ulogic; +signal llstate : std_ulogic_vector(0 to 1); +signal set_dbsr_ide : std_ulogic; +signal set_dbsr : std_ulogic_vector(dbsr_q'range); +signal dec_running, udec_running : std_ulogic; +signal dbcr0_freeze_timers : std_ulogic; +signal dbsr_event : std_ulogic; +signal mux_msr_gs, mux_msr_pr : std_ulogic; +signal mux_msr_de : std_ulogic; +signal hang_pulse : std_ulogic; +signal dear_di : std_ulogic_vector(dear_q'range); +signal ex2_srr0_re2, ex2_gsrr0_re2 : std_ulogic; +signal ex2_csrr0_re2, ex2_mcsrr0_re2 : std_ulogic; +signal ex2_icswx_gs, ex2_icswx_pr : std_ulogic; +signal ex2_acop_ct, ex2_cop_ct : std_ulogic_vector(32 to 63); +signal iac_us_en, iac_er_en : std_ulogic_vector(1 to 4); +signal udec_en : std_ulogic; +signal ex2_ct : std_ulogic_vector(0 to 1); +signal ex6_rfi, ex6_rfgi : std_ulogic; +signal ex6_rfci, ex6_rfmci : std_ulogic; +signal ex6_wrteei, ex6_wrtee : std_ulogic; +signal reset_complete : std_ulogic_vector(0 to 1); +signal wdog_reset_1 : std_ulogic; +signal wdog_reset_2 : std_ulogic; +signal wdog_reset_3 : std_ulogic; +signal tb_tap_edge : std_ulogic_vector(cspr_tspr_timebase_taps'range); +signal exx_act, exx_act_data : std_ulogic_vector(1 to 5); +signal ex5_int_act : std_ulogic; +signal ex1_is_wrteei : std_ulogic; +signal dbsr_mrr_act, tsr_wrs_act : std_ulogic; +signal reset_complete_act : std_ulogic; +signal ex6_gint_nia_sel : std_ulogic; +signal fp_precise : std_ulogic; +signal dbsr_di : std_ulogic_vector(dbsr_q'range); + +-- Data +signal spr_acop_ct : std_ulogic_vector(0 to 31); +signal spr_ccr3_en_eepri : std_ulogic; +signal spr_ccr3_si : std_ulogic; +signal spr_dbcr0_rst : std_ulogic_vector(0 to 1); +signal spr_dbcr0_iac1 : std_ulogic; +signal spr_dbcr0_iac2 : std_ulogic; +signal spr_dbcr0_iac3 : std_ulogic; +signal spr_dbcr0_iac4 : std_ulogic; +signal spr_dbcr0_ft : std_ulogic; +signal spr_dbcr1_iac1us : std_ulogic_vector(0 to 1); +signal spr_dbcr1_iac1er : std_ulogic_vector(0 to 1); +signal spr_dbcr1_iac2us : std_ulogic_vector(0 to 1); +signal spr_dbcr1_iac2er : std_ulogic_vector(0 to 1); +signal spr_dbcr1_iac3us : std_ulogic_vector(0 to 1); +signal spr_dbcr1_iac3er : std_ulogic_vector(0 to 1); +signal spr_dbcr1_iac4us : std_ulogic_vector(0 to 1); +signal spr_dbcr1_iac4er : std_ulogic_vector(0 to 1); +signal spr_dbsr_ide : std_ulogic; +signal spr_epcr_extgs : std_ulogic; +signal spr_epcr_icm : std_ulogic; +signal spr_epcr_gicm : std_ulogic; +signal spr_hacop_ct : std_ulogic_vector(0 to 31); +signal spr_msr_cm : std_ulogic; +signal spr_msr_gs : std_ulogic; +signal spr_msr_ce : std_ulogic; +signal spr_msr_ee : std_ulogic; +signal spr_msr_pr : std_ulogic; +signal spr_msr_me : std_ulogic; +signal spr_msr_fe0 : std_ulogic; +signal spr_msr_de : std_ulogic; +signal spr_msr_fe1 : std_ulogic; +signal spr_msr_is : std_ulogic; +signal spr_tcr_wp : std_ulogic_vector(0 to 1); +signal spr_tcr_wrc : std_ulogic_vector(0 to 1); +signal spr_tcr_wie : std_ulogic; +signal spr_tcr_die : std_ulogic; +signal spr_tcr_fp : std_ulogic_vector(0 to 1); +signal spr_tcr_fie : std_ulogic; +signal spr_tcr_are : std_ulogic; +signal spr_tcr_udie : std_ulogic; +signal spr_tcr_ud : std_ulogic; +signal spr_tsr_enw : std_ulogic; +signal spr_tsr_wis : std_ulogic; +signal spr_tsr_dis : std_ulogic; +signal spr_tsr_fis : std_ulogic; +signal spr_tsr_udis : std_ulogic; +signal spr_xucr1_ll_tb_sel : std_ulogic_vector(0 to 2); +signal spr_xucr1_ll_sel : std_ulogic; +signal spr_xucr1_ll_en : std_ulogic; +signal ex6_acop_di : std_ulogic_vector(acop_q'range); +signal ex6_ccr3_di : std_ulogic_vector(ccr3_q'range); +signal ex6_csrr0_di : std_ulogic_vector(csrr0_q'range); +signal ex6_csrr1_di : std_ulogic_vector(csrr1_q'range); +signal ex6_dbcr0_di : std_ulogic_vector(dbcr0_q'range); +signal ex6_dbcr1_di : std_ulogic_vector(dbcr1_q'range); +signal ex6_dbsr_di : std_ulogic_vector(dbsr_q'range); +signal ex6_dear_di : std_ulogic_vector(dear_q'range); +signal ex6_dec_di : std_ulogic_vector(dec_q'range); +signal ex6_decar_di : std_ulogic_vector(decar_q'range); +signal ex6_epcr_di : std_ulogic_vector(epcr_q'range); +signal ex6_esr_di : std_ulogic_vector(esr_q'range); +signal ex6_gdear_di : std_ulogic_vector(gdear_q'range); +signal ex6_gesr_di : std_ulogic_vector(gesr_q'range); +signal ex6_gpir_di : std_ulogic_vector(gpir_q'range); +signal ex6_gsrr0_di : std_ulogic_vector(gsrr0_q'range); +signal ex6_gsrr1_di : std_ulogic_vector(gsrr1_q'range); +signal ex6_hacop_di : std_ulogic_vector(hacop_q'range); +signal ex6_mcsr_di : std_ulogic_vector(mcsr_q'range); +signal ex6_mcsrr0_di : std_ulogic_vector(mcsrr0_q'range); +signal ex6_mcsrr1_di : std_ulogic_vector(mcsrr1_q'range); +signal ex6_msr_di : std_ulogic_vector(msr_q'range); +signal ex6_msrp_di : std_ulogic_vector(msrp_q'range); +signal ex6_srr0_di : std_ulogic_vector(srr0_q'range); +signal ex6_srr1_di : std_ulogic_vector(srr1_q'range); +signal ex6_tcr_di : std_ulogic_vector(tcr_q'range); +signal ex6_tsr_di : std_ulogic_vector(tsr_q'range); +signal ex6_udec_di : std_ulogic_vector(udec_q'range); +signal ex6_xucr1_di : std_ulogic_vector(xucr1_q'range); +signal + ex2_acop_rdec , ex2_ccr3_rdec , ex2_csrr0_rdec , ex2_csrr1_rdec + , ex2_ctr_rdec , ex2_dbcr0_rdec , ex2_dbcr1_rdec , ex2_dbcr2_rdec + , ex2_dbcr3_rdec , ex2_dbsr_rdec , ex2_dear_rdec , ex2_dec_rdec + , ex2_decar_rdec , ex2_epcr_rdec , ex2_esr_rdec , ex2_gdear_rdec + , ex2_gesr_rdec , ex2_gpir_rdec , ex2_gsrr0_rdec , ex2_gsrr1_rdec + , ex2_hacop_rdec , ex2_iar_rdec , ex2_lr_rdec , ex2_mcsr_rdec + , ex2_mcsrr0_rdec, ex2_mcsrr1_rdec, ex2_msrp_rdec , ex2_srr0_rdec + , ex2_srr1_rdec , ex2_tcr_rdec , ex2_tsr_rdec , ex2_udec_rdec + , ex2_xer_rdec , ex2_xucr1_rdec + : std_ulogic; +signal + ex2_acop_re , ex2_ccr3_re , ex2_csrr0_re , ex2_csrr1_re + , ex2_ctr_re , ex2_dbcr0_re , ex2_dbcr1_re , ex2_dbcr2_re + , ex2_dbcr3_re , ex2_dbsr_re , ex2_dear_re , ex2_dec_re + , ex2_decar_re , ex2_epcr_re , ex2_esr_re , ex2_gdear_re + , ex2_gesr_re , ex2_gpir_re , ex2_gsrr0_re , ex2_gsrr1_re + , ex2_hacop_re , ex2_iar_re , ex2_lr_re , ex2_mcsr_re + , ex2_mcsrr0_re , ex2_mcsrr1_re , ex2_msrp_re , ex2_srr0_re + , ex2_srr1_re , ex2_tcr_re , ex2_tsr_re , ex2_udec_re + , ex2_xer_re , ex2_xucr1_re + : std_ulogic; +signal ex2_pir_rdec : std_ulogic; +signal + ex2_acop_we , ex2_ccr3_we , ex2_csrr0_we , ex2_csrr1_we + , ex2_ctr_we , ex2_dbcr0_we , ex2_dbcr1_we , ex2_dbcr2_we + , ex2_dbcr3_we , ex2_dbsr_we , ex2_dbsrwr_we , ex2_dear_we + , ex2_dec_we , ex2_decar_we , ex2_epcr_we , ex2_esr_we + , ex2_gdear_we , ex2_gesr_we , ex2_gpir_we , ex2_gsrr0_we + , ex2_gsrr1_we , ex2_hacop_we , ex2_iar_we , ex2_lr_we + , ex2_mcsr_we , ex2_mcsrr0_we , ex2_mcsrr1_we , ex2_msrp_we + , ex2_srr0_we , ex2_srr1_we , ex2_tcr_we , ex2_tsr_we + , ex2_udec_we , ex2_xer_we , ex2_xucr1_we + : std_ulogic; +signal + ex2_acop_wdec , ex2_ccr3_wdec , ex2_csrr0_wdec , ex2_csrr1_wdec + , ex2_ctr_wdec , ex2_dbcr0_wdec , ex2_dbcr1_wdec , ex2_dbcr2_wdec + , ex2_dbcr3_wdec , ex2_dbsr_wdec , ex2_dbsrwr_wdec, ex2_dear_wdec + , ex2_dec_wdec , ex2_decar_wdec , ex2_epcr_wdec , ex2_esr_wdec + , ex2_gdear_wdec , ex2_gesr_wdec , ex2_gpir_wdec , ex2_gsrr0_wdec + , ex2_gsrr1_wdec , ex2_hacop_wdec , ex2_iar_wdec , ex2_lr_wdec + , ex2_mcsr_wdec , ex2_mcsrr0_wdec, ex2_mcsrr1_wdec, ex2_msrp_wdec + , ex2_srr0_wdec , ex2_srr1_wdec , ex2_tcr_wdec , ex2_tsr_wdec + , ex2_udec_wdec , ex2_xer_wdec , ex2_xucr1_wdec + : std_ulogic; +signal + ex6_acop_wdec , ex6_ccr3_wdec , ex6_csrr0_wdec , ex6_csrr1_wdec + , ex6_dbcr0_wdec , ex6_dbcr1_wdec , ex6_dbsr_wdec , ex6_dbsrwr_wdec + , ex6_dear_wdec , ex6_dec_wdec , ex6_decar_wdec , ex6_epcr_wdec + , ex6_esr_wdec , ex6_gdear_wdec , ex6_gesr_wdec , ex6_gpir_wdec + , ex6_gsrr0_wdec , ex6_gsrr1_wdec , ex6_hacop_wdec , ex6_mcsr_wdec + , ex6_mcsrr0_wdec, ex6_mcsrr1_wdec, ex6_msr_wdec , ex6_msrp_wdec + , ex6_srr0_wdec , ex6_srr1_wdec , ex6_tcr_wdec , ex6_tsr_wdec + , ex6_udec_wdec , ex6_xucr1_wdec + : std_ulogic; +signal + ex6_acop_we , ex6_ccr3_we , ex6_csrr0_we , ex6_csrr1_we + , ex6_dbcr0_we , ex6_dbcr1_we , ex6_dbsr_we , ex6_dbsrwr_we + , ex6_dear_we , ex6_dec_we , ex6_decar_we , ex6_epcr_we + , ex6_esr_we , ex6_gdear_we , ex6_gesr_we , ex6_gpir_we + , ex6_gsrr0_we , ex6_gsrr1_we , ex6_hacop_we , ex6_mcsr_we + , ex6_mcsrr0_we , ex6_mcsrr1_we , ex6_msr_we , ex6_msrp_we + , ex6_srr0_we , ex6_srr1_we , ex6_tcr_we , ex6_tsr_we + , ex6_udec_we , ex6_xucr1_we + : std_ulogic; +signal + acop_act , ccr3_act , csrr0_act , csrr1_act + , dbcr0_act , dbcr1_act , dbsr_act , dear_act + , dec_act , decar_act , epcr_act , esr_act + , gdear_act , gesr_act , gpir_act , gsrr0_act + , gsrr1_act , hacop_act , mcsr_act , mcsrr0_act + , mcsrr1_act , msr_act , msrp_act , srr0_act + , srr1_act , tcr_act , tsr_act , udec_act + , xucr1_act + : std_ulogic; +signal + acop_do , ccr3_do , csrr0_do , csrr1_do + , dbcr0_do , dbcr1_do , dbsr_do , dear_do + , dec_do , decar_do , epcr_do , esr_do + , gdear_do , gesr_do , gpir_do , gsrr0_do + , gsrr1_do , hacop_do , mcsr_do , mcsrr0_do + , mcsrr1_do , msr_do , msrp_do , srr0_do + , srr1_do , tcr_do , tsr_do , udec_do + , xucr1_do + : std_ulogic_vector(0 to 64); + +begin + + +tiup <= '1'; +tidn <= (others=>'0'); + +exx_act_d <= cspr_tspr_rf1_act & exx_act(1 to 4); + +exx_act(1) <= exx_act_q(1); +exx_act(2) <= exx_act_q(2); +exx_act(3) <= exx_act_q(3); +exx_act(4) <= exx_act_q(4); +exx_act(5) <= exx_act_q(5); + +exx_act_data(1) <= exx_act(1); +exx_act_data(2) <= exx_act(2); +exx_act_data(3) <= exx_act(3); +exx_act_data(4) <= exx_act(4); +exx_act_data(5) <= exx_act(5); + +ex5_int_act <= cpl_spr_ex5_act or cspr_xucr0_clkg_ctl(4); + +-- Decode +ex1_opcode_is_31 <= cspr_tspr_ex1_instr(0 to 5) = "011111"; +ex1_opcode_is_19 <= cspr_tspr_ex1_instr(0 to 5) = "010011"; +ex1_is_mfspr <= '1' when ex1_opcode_is_31 and cspr_tspr_ex1_instr(21 to 30) = "0101010011" else '0'; -- 31/339 +ex1_is_mtspr <= '1' when ex1_opcode_is_31 and cspr_tspr_ex1_instr(21 to 30) = "0111010011" else '0'; -- 31/467 +ex1_is_mfmsr <= '1' when ex1_opcode_is_31 and cspr_tspr_ex1_instr(21 to 30) = "0001010011" else '0'; -- 31/083 +ex1_is_rfi <= '1' when ex1_opcode_is_19 and cspr_tspr_ex1_instr(21 to 30) = "0000110010" else '0'; -- 19/050 +ex1_is_rfgi <= '1' when ex1_opcode_is_19 and cspr_tspr_ex1_instr(21 to 30) = "0001100110" else '0'; -- 19/102 +ex1_is_rfci <= '1' when ex1_opcode_is_19 and cspr_tspr_ex1_instr(21 to 30) = "0000110011" else '0'; -- 19/051 +ex1_is_rfmci <= '1' when ex1_opcode_is_19 and cspr_tspr_ex1_instr(21 to 30) = "0000100110" else '0'; -- 19/038 +ex1_is_wrteei <= '1' when ex1_opcode_is_31 and cspr_tspr_ex1_instr(21 to 30) = "0010100011" else '0'; -- 31/163 + +ex2_instr_d <= gate(cspr_tspr_ex1_instr(11 to 20),(ex1_is_mfspr or ex1_is_mtspr or ex1_is_wrteei)); + +ex2_is_mfmsr <= ex2_is_mfmsr_q; +ex2_is_mfspr <= ex2_is_mfspr_q; +ex2_is_mtspr <= ex2_is_mtspr_q; +ex2_instr <= ex2_instr_q; +ex6_is_mtmsr <= ex6_is_mtmsr_q; +ex6_is_mtspr <= ex6_is_mtspr_q; +ex6_instr <= ex6_instr_q; +ex6_spr_wd <= ex6_spr_wd_q; + +ex4_val <= dec_spr_ex4_val and not xu_ex4_flush; +ex5_val <= ex5_val_q and not xu_ex5_flush; +ex6_val <= ex6_val_q; +ex2_rfgi_d <=(ex1_is_rfi and mux_msr_gs_q(0)) or ex1_is_rfgi; +ex2_rfi_d <= ex1_is_rfi and not mux_msr_gs_q(0); +ex6_any_int <= ex6_int_q or ex6_cint_q or ex6_mcint_q or ex6_gint_q; +ex6_any_hint <= ex6_int_q or ex6_cint_q or ex6_mcint_q; +ex6_rfi <= ex6_val and ex6_rfi_q; +ex6_rfgi <= ex6_val and ex6_rfgi_q; +ex6_rfci <= ex6_val and ex6_rfci_q; +ex6_rfmci <= ex6_val and ex6_rfmci_q; +ex6_wrteei <= ex6_val and ex6_wrteei_q; +ex6_wrtee <= ex6_val and ex6_wrtee_q; + +ex3_tid_rpwr_d <= (others=>cspr_tspr_ex2_tid); + +tb_tap_edge <= cspr_tspr_timebase_taps and not timebase_taps_q; + + +-- SPR Input Control +-- ACOP +acop_act <= ex6_acop_we; +acop_d <= ex6_acop_di; + +-- CCR3 +ccr3_act <= ex6_ccr3_we; +ccr3_d <= ex6_ccr3_di; + +-- CSRR0 +csrr0_act <= ex6_csrr0_we or ex6_cint_q; + +with ex6_cint_q select + csrr0_d <= ex6_nia_srr0 when '1', + ex6_csrr0_di when others; + +-- CSRR1 +csrr1_act <= ex6_csrr1_we or ex6_cint_q; + +csrr1_gen_64 : if regsize = 64 generate + ex6_csrr1_d <= ex6_csrr1_di; +end generate; +csrr1_gen_32 : if regsize = 32 generate + ex6_csrr1_d(MSR_CM) <= '0'; + ex6_csrr1_d(MSR_GS to MSR_DS) <= ex6_csrr1_di(MSR_GS to MSR_DS); +end generate; + +with ex6_cint_q select + csrr1_d <= msr_q when '1', + ex6_csrr1_d when others; + +-- DBCR0 +dbcr0_act <= ex6_dbcr0_we; +dbcr0_d <= ex6_dbcr0_di; + +-- DBCR1 +dbcr1_act <= ex6_dbcr1_we; +dbcr1_d <= ex6_dbcr1_di; + +-- DBSR +reset_complete_act <= or_reduce(reset_complete); + +dbsr_mrr_act <= reset_complete_act or ex6_dbsr_we or ex6_dbsrwr_we; + +dbsr_mrr_d <= reset_complete when reset_complete_act ='1' else + ex6_spr_wd(34 to 35) when ex6_dbsrwr_we ='1' else + (dbsr_mrr_q and not ex6_spr_wd(34 to 35)); + +dbsr_act <= ex6_dbsr_we or ex6_dbsrwr_we or ex6_dbsr_update_q; + +-- BRT and ICMP event can never set IDE. +set_dbsr_ide <= ((ex6_dbsr_q(0) or or_reduce(ex6_dbsr_q(3 to 18))) and not msr_q(60)) or ex6_dbsr_ide_q; +set_dbsr <= set_dbsr_ide & ex6_dbsr_q(0 to 18); + +dbsr_d <= dbsr_di or gate(set_dbsr,ex6_dbsr_update_q); +dbsr_di <= ex6_dbsr_di when ex6_dbsrwr_we ='1' else + (dbsr_q and not ex6_dbsr_di) when ex6_dbsr_we ='1' else + dbsr_q; + +-- DEAR +dear_act <= ex6_dear_we or (ex6_dear_update_q and not ex6_gint_q); + +dear_tmp_d(32 to 63) <= ex6_dear_di(32 to 63); +dear_di(32 to 63) <= ex6_dear_di(32 to 63); +xuq_cpl_dear_mask_gen0 : if (64-regsize) < 32 generate + dear_di(dear_d'left to 31) <= ex6_dear_di(dear_d'left to 31) and (dear_d'left to 31=>(spr_msr_cm or not ex6_dear_update_q)); + dear_tmp_d(dear_d'left to 31) <= ex6_dear_di(dear_d'left to 31) and (dear_d'left to 31=> spr_msr_cm); +end generate; + +with ex6_dear_update_saved_q select + dear_d <= dear_tmp_q when '1', + dear_di when others; + +-- GDEAR +gdear_act <= ex6_gdear_we or (ex6_dear_update_q and ex6_gint_q); + +gdear_d <= dear_d; + +-- DEC +dec_running <= timer_update and not (not spr_tcr_are and ex6_dec_zero) and not cspr_tspr_dec_dbg_dis and not dbcr0_freeze_timers; + +dec_act <= ex6_dec_we or dec_running; + +dec_d <= ex6_dec_di when ex6_dec_we ='1' else + decar_q when (ex6_set_tsr_dis and spr_tcr_are) ='1' else + std_ulogic_vector(unsigned(dec_q) - 1); + +-- UDEC +udec_running <= timer_update and not ex6_udec_zero and not cspr_tspr_dec_dbg_dis and not dbcr0_freeze_timers; + +udec_act <= ex6_udec_we or udec_running; + +udec_d <= ex6_udec_di when ex6_udec_we ='1' else + std_ulogic_vector(unsigned(udec_q) - 1); + +-- DECAR +decar_act <= ex6_decar_we; +decar_d <= ex6_decar_di; + +-- EPCR +epcr_act <= ex6_epcr_we; +epcr_d <= ex6_epcr_di; + +-- ESR +esr_act <= ex6_esr_we or (ex6_esr_update_q and ex6_int_q); + +esr_d <= ex6_esr_q when ex6_esr_update_q ='1' else + ex6_esr_di when ex6_esr_we ='1' else + esr_q; + +-- GESR +gesr_act <= ex6_gesr_we or (ex6_esr_update_q and ex6_gint_q); + +gesr_d <= ex6_esr_q when ex6_esr_update_q ='1' else + ex6_gesr_di when ex6_gesr_we ='1' else + gesr_q; + +-- GPIR +gpir_act <= ex6_gpir_we; +gpir_d <= ex6_gpir_di; + +-- HACOP +hacop_act <= ex6_hacop_we; +hacop_d <= ex6_hacop_di; + +-- MCSR +mcsr_act <= ex6_mcsr_we or ex6_mcint_q; + +mcsr_d <= ex6_mcsr_q when ex6_mcint_q ='1' else + ex6_mcsr_di when ex6_mcsr_we ='1' else + mcsr_q; + +-- MCSRR0 +mcsrr0_act <= ex6_mcsrr0_we or ex6_mcint_q; + +with ex6_mcint_q select + mcsrr0_d <= ex6_nia_srr0 when '1', + ex6_mcsrr0_di when others; + +-- MCSRR1 +mcsrr1_act <= ex6_mcsrr1_we or ex6_mcint_q; + +mcsrr1_gen_64 : if regsize = 64 generate + ex6_mcsrr1_d <= ex6_mcsrr1_di; +end generate; +mcsrr1_gen_32 : if regsize = 32 generate + ex6_mcsrr1_d(MSR_CM) <= '0'; + ex6_mcsrr1_d(MSR_GS to MSR_DS) <= ex6_mcsrr1_di(MSR_GS to MSR_DS); +end generate; + +with ex6_mcint_q select + mcsrr1_d <= msr_q when '1', + ex6_mcsrr1_d when others; + +-- MSR +msr_act <= cspr_xucr0_clkg_ctl(4) or + ex6_any_int or ex6_msr_we or + ex6_wrteei_q or ex6_wrtee_q or + ex6_rfi_q or ex6_rfgi_q or ex6_rfci_q or ex6_rfmci_q; + +-- CM GS UCLE SPV CE EE PR FP ME FE0 DE FE1 IS DS +-- 50 51 52 53 54 55 56 57 58 59 60 61 62 63 +-- X X MSRP + +with (msrp_q(MSRP_UCLEP) and msr_q(MSR_GS)) select + ex6_msr_di2(MSR_UCLE) <= msr_q(MSR_UCLE) when '1', + ex6_msr_di(MSR_UCLE) when others; + +with (msrp_q(MSRP_DEP) and msr_q(MSR_GS)) select + ex6_msr_di2(MSR_DE) <= msr_q(MSR_DE) when '1', + ex6_msr_di(MSR_DE) when others; + +ex6_msr_di2(MSR_CM) <= ex6_msr_di(MSR_CM); +ex6_msr_di2(MSR_GS) <= ex6_msr_di(MSR_GS) or msr_q(MSR_GS); +ex6_msr_di2(MSR_SPV to MSR_FE0) <= ex6_msr_di(MSR_SPV to MSR_FE0); +ex6_msr_di2(MSR_FE1 to MSR_DS) <= ex6_msr_di(MSR_FE1 to MSR_DS); + + +-- 0 leave unchanged +-- 1 clear +ex6_msr_mask(MSR_CM) <= '0'; -- CM +ex6_msr_mask(MSR_GS) <= ex6_any_hint; -- GS +ex6_msr_mask(MSR_UCLE) <= ex6_any_hint or (ex6_gint_q and not msrp_q(MSRP_UCLEP)); -- UCLE +ex6_msr_mask(MSR_SPV) <= ex6_any_int; -- SPV +ex6_msr_mask(MSR_CE) <= ex6_mcint_q or ex6_cint_q; -- CE +ex6_msr_mask(MSR_EE) <= ex6_any_int; -- EE +ex6_msr_mask(MSR_PR to MSR_FP) <= (others=>ex6_any_int); -- PR,FP +ex6_msr_mask(MSR_ME) <= ex6_mcint_q; -- ME +ex6_msr_mask(MSR_FE0) <= ex6_any_int; -- FE0 +ex6_msr_mask(MSR_DE) <= ex6_mcint_q or ex6_cint_q; -- DE +ex6_msr_mask(MSR_FE1 to MSR_DS) <= (others=>ex6_any_int); -- FE1,IS,DS + +with s5'(ex6_rfi & ex6_rfgi & ex6_rfci & ex6_rfmci & ex6_msr_we) select + ex6_msr_mux <= srr1_q when "10000", + ex6_rfgi_msr when "01000", + csrr1_q when "00100", + mcsrr1_q when "00010", + ex6_msr_di2 when "00001", + msr_q when others; + +ex6_msr_in(51 to 54) <= ex6_msr_mux(51 to 54); +ex6_msr_in(56 to 63) <= ex6_msr_mux(56 to 63); + +with s2'(ex6_any_hint & ex6_gint_q) select + ex6_msr_in(MSR_CM) <= spr_epcr_icm when "10", -- ICM + spr_epcr_gicm when "01", -- GICM + ex6_msr_mux(MSR_CM) when others; -- CM + +with s2'(ex6_wrteei & ex6_wrtee) select + ex6_msr_in(MSR_EE) <= ex6_instr_q(16) when "10", + ex6_spr_wd(48) when "01", + ex6_msr_mux(MSR_EE) when others; + +msr_gen_64 : if regsize = 64 generate + msr_d <= ex6_msr_in and not ex6_msr_mask; +end generate; +msr_gen_32 : if regsize = 32 generate + msr_d(MSR_CM) <= '0'; + msr_d(MSR_GS to MSR_DS) <= ex6_msr_in(MSR_GS to MSR_DS) and not ex6_msr_mask(MSR_GS to MSR_DS); +end generate; + +-- rfgi msr +ex6_rfgi_msr(MSR_CM) <= gsrr1_q(MSR_CM); +ex6_rfgi_msr(MSR_SPV to MSR_FE0) <= gsrr1_q(MSR_SPV to MSR_FE0); +ex6_rfgi_msr(MSR_FE1 to MSR_DS) <= gsrr1_q(MSR_FE1 to MSR_DS); + +with (msr_q(MSR_GS)) select + ex6_rfgi_msr(MSR_GS) <= msr_q(MSR_GS) when '1', + gsrr1_q(MSR_GS) when others; + +with (msrp_q(MSRP_UCLEP) and msr_q(MSR_GS)) select + ex6_rfgi_msr(MSR_UCLE) <= msr_q(MSR_UCLE) when '1', + gsrr1_q(MSR_UCLE) when others; + +with (msrp_q(MSRP_DEP) and msr_q(MSR_GS)) select + ex6_rfgi_msr(MSR_DE) <= msr_q(MSR_DE) when '1', + gsrr1_q(MSR_DE) when others; + +-- MSRP +msrp_act <= ex6_msrp_we; +msrp_d <= ex6_msrp_di; + +-- SRR0 +srr0_act <= ex6_srr0_we or (ex6_int_q and not ex6_force_gsrr_q); + +-- Subtract one for enabled program interrupts +ex6_nia_srr0_dec <= (ex6_nia_q'left to 60=>'0') & ex6_srr0_dec_q; +ex6_nia_srr0 <= std_ulogic_vector(unsigned(ex6_nia_q) - unsigned(ex6_nia_srr0_dec)); + +with ex6_int_q select + srr0_d <= ex6_nia_srr0 when '1', + ex6_srr0_di when others; + +-- SRR1 +srr1_act <= ex6_srr1_we or (ex6_int_q and not ex6_force_gsrr_q); + +srr1_gen_64 : if regsize = 64 generate + ex6_srr1_d <= ex6_srr1_di; +end generate; +srr1_gen_32 : if regsize = 32 generate + ex6_srr1_d(MSR_CM) <= '0'; + ex6_srr1_d(MSR_GS to MSR_DS) <= ex6_srr1_di(MSR_GS to MSR_DS); +end generate; + +with ex6_int_q select + srr1_d <= msr_q when '1', + ex6_srr1_d when others; + + +-- GSRR0 +ex6_gint_nia_sel <= ex6_gint_q or (ex6_int_q and ex6_force_gsrr_q); + +gsrr0_act <= ex6_gsrr0_we or ex6_gint_nia_sel; + + +with ex6_gint_nia_sel select + gsrr0_d <= ex6_nia_srr0 when '1', + ex6_gsrr0_di when others; + +-- GSRR1 +gsrr1_act <= ex6_gsrr1_we or ex6_gint_nia_sel; + +gsrr1_gen_64 : if regsize = 64 generate + ex6_gsrr1_d <= ex6_gsrr1_di; +end generate; +gsrr1_gen_32 : if regsize = 32 generate + ex6_gsrr1_d(MSR_CM) <= '0'; + ex6_gsrr1_d(MSR_GS to MSR_DS) <= ex6_gsrr1_di(MSR_GS to MSR_DS); +end generate; + +with ex6_gint_nia_sel select + gsrr1_d <= msr_q when '1', + ex6_gsrr1_d when others; + +-- TCR +tcr_act <= ex6_tcr_we; +tcr_d <= ex6_tcr_di; + +-- TSR +tsr_wrs_act <= (reset_wd_complete and reset_complete_act) or ex6_tsr_we; + +tsr_wrs_d <= reset_complete when (reset_wd_complete and reset_complete_act) ='1' else + (tsr_wrs_q and not ex6_spr_wd(34 to 35)); + +tsr_act <= cspr_xucr0_clkg_ctl(4) or ex6_tsr_we or or_reduce(ex6_set_tsr); + +tsr_d <= ex6_set_tsr or (tsr_q and not (ex6_tsr_di and (tsr_q'range=>ex6_tsr_we))); + +-- XUCR1 +xucr1_act <= ex6_xucr1_we; +xucr1_d <= ex6_xucr1_di; + +-- LiveLock Buster! +with spr_xucr1_ll_tb_sel select + lltbtap <= tb_tap_edge(8) when "000", + tb_tap_edge(5) when "001", + tb_tap_edge(4) when "010", + tb_tap_edge(3) when "011", + tb_tap_edge(7) when "100", + tb_tap_edge(2) when "101", + tb_tap_edge(6) when "110", + tb_tap_edge(1) when others; + +hang_pulse_d <= an_ac_hang_pulse & hang_pulse_q(0 to 2); +hang_pulse <= hang_pulse_q(2) and not hang_pulse_q(3); + + +with spr_xucr1_ll_sel select + lltap_d <= hang_pulse when '1', + lltbtap when others; + +llpulse <= not llcnt_q(0) and -- Stop if counter == "10" + cspr_tspr_llen and -- Don't pulse if stopped + spr_xucr1_ll_en and -- Gate off if disabled + lltap_q; + +llreset <= (cpl_spr_ex5_instr_cpl and not ((inj_llbust_attempt_q and not llcnt_q(0)) or inj_llbust_failed_q)) or not cspr_tspr_llen; + +with s2'(llpulse & llreset) select + llcnt_d <= "00" when "01", + "00" when "11", +std_ulogic_vector(signed(llcnt_q) + 1) when "10", + llcnt_q when others; + +tspr_cspr_lldet <= llcnt_q(0) and spr_xucr1_ll_en; +tspr_cspr_llpulse <= llpulse; + +llstate(0) <= llcnt_q(0); +llstate(1) <= llcnt_q(1) or (llcnt_q(0) and not cspr_tspr_llpri); + +-- Raise the priority for threads that are in livelock +-- Raise the priroity for threads with EE=0 +raise_iss_pri_d <= (not spr_msr_ee and spr_ccr3_en_eepri) or + (llcnt_q(0) and spr_xucr1_ll_en); +xu_iu_raise_iss_pri <= raise_iss_pri_2_q; + +err_llbust_attempt_d <= llstate(0) and not llstate(1); +err_llbust_failed_d <= llstate(0) and cspr_tspr_llen and spr_xucr1_ll_en and lltap_q and cspr_tspr_llpri; + +xu_spr_tspr_llbust_err_rpt : entity tri.tri_direct_err_rpt(tri_direct_err_rpt) +generic map(width => 2, expand_type => expand_type) +port map ( vd => vdd, gd => gnd, + err_in(0) => err_llbust_attempt_q, + err_in(1) => err_llbust_failed_q, + err_out(0) => xu_pc_err_llbust_attempt, + err_out(1) => xu_pc_err_llbust_failed); + +-- Decrementer Logic +ex6_dec_upper_zero <= not or_reduce(dec_q(32 to 62)); +ex6_set_tsr_dis <= dec_running and ex6_dec_upper_zero and dec_q(63); +ex6_dec_zero <= ex6_dec_upper_zero and not dec_q(63); + +ex6_udec_upper_zero <= not or_reduce(udec_q(32 to 62)); +ex6_set_tsr_udis <= udec_running and ex6_udec_upper_zero and udec_q(63); +ex6_udec_zero <= ex6_udec_upper_zero and not udec_q(63); + +-- Fixed Interval Timer logic +with spr_tcr_fp select + fit_tb_tap_d <= tb_tap_edge(5) when "00", + tb_tap_edge(4) when "01", + tb_tap_edge(3) when "10", + tb_tap_edge(2) when others; + +ex6_set_tsr_fis <= fit_tb_tap_q; + +-- Watchdog Timer Logic +with spr_tcr_wp select + wdog_tb_tap_d <= tb_tap_edge(3) when "00", + tb_tap_edge(2) when "01", + tb_tap_edge(9) when "10", + tb_tap_edge(0) when others; + +wdog_pulse <= wdog_tb_tap_q or pc_xu_inj_wdt_reset_q; + +ex6_set_tsr_enw <= wdog_pulse and not spr_tsr_enw; +ex6_set_tsr_wis <= wdog_pulse and spr_tsr_enw and not spr_tsr_wis; + +ex6_set_tsr <= ex6_set_tsr_enw & + ex6_set_tsr_wis & + ex6_set_tsr_dis & + ex6_set_tsr_fis & + ex6_set_tsr_udis; + + +-- Resets +reset_complete <= "11" when reset_3_complete='1' else + "10" when reset_2_complete='1' else + "01" when reset_1_complete='1' else + "00"; + +wdog_reset_1 <= spr_tsr_enw and spr_tsr_wis and (spr_tcr_wrc="01"); +wdog_reset_2 <= spr_tsr_enw and spr_tsr_wis and (spr_tcr_wrc="10"); +wdog_reset_3 <= spr_tsr_enw and spr_tsr_wis and (spr_tcr_wrc="11"); +reset_wd_request <= spr_tsr_enw and spr_tsr_wis and not (spr_tcr_wrc="00"); + +reset_1_request <= wdog_reset_1 or (spr_dbcr0_rst="01"); +reset_2_request <= wdog_reset_2 or (spr_dbcr0_rst="10"); +reset_3_request <= wdog_reset_3 or (spr_dbcr0_rst="11"); +err_wdt_reset_d <= spr_tsr_enw and spr_tsr_wis and or_reduce(spr_tcr_wrc); + +xu_spr_tspr_wdt_err_rpt : entity tri.tri_direct_err_rpt(tri_direct_err_rpt) +generic map (width => 1, expand_type => expand_type) +port map (vd => vdd, gd => gnd, + err_in(0) => err_wdt_reset_q, + err_out(0) => xu_pc_err_wdt_reset); + +-- DBCR0[FT] Freeze timers +dbcr0_freeze_timers <= spr_dbcr0_ft and (spr_dbsr_ide or dbsr_event); +tspr_cspr_freeze_timers <= dbcr0_freeze_timers; + + +-- ICSWX +ex2_icswx_gs <= epsc_egs_q when ex2_epid_instr_q='1' else spr_msr_gs; +ex2_icswx_pr <= epsc_epr_q when ex2_epid_instr_q='1' else spr_msr_pr; + +-- Only Check ACOP in problem state (PR=1) +ex2_acop_ct <= gate_or(not ex2_icswx_pr,spr_acop_ct); + +ex2_cop_ct <= spr_hacop_ct and ex2_acop_ct; + +-- Only Check ACOP/HACOP if not in Hypervisor +ex3_ct_d(0) <= ex2_ct(0) or (not ex2_icswx_pr and not ex2_icswx_gs); -- Big Endian +ex3_ct_d(1) <= ex2_ct(1) or (not ex2_icswx_pr and not ex2_icswx_gs); -- Little Endian + +with ex2_rs2_q(42 to 47) select -- Big Endian + ex2_ct(0)<= ex2_cop_ct(32) when "100000", + ex2_cop_ct(33) when "100001", + ex2_cop_ct(34) when "100010", + ex2_cop_ct(35) when "100011", + ex2_cop_ct(36) when "100100", + ex2_cop_ct(37) when "100101", + ex2_cop_ct(38) when "100110", + ex2_cop_ct(39) when "100111", + ex2_cop_ct(40) when "101000", + ex2_cop_ct(41) when "101001", + ex2_cop_ct(42) when "101010", + ex2_cop_ct(43) when "101011", + ex2_cop_ct(44) when "101100", + ex2_cop_ct(45) when "101101", + ex2_cop_ct(46) when "101110", + ex2_cop_ct(47) when "101111", + ex2_cop_ct(48) when "110000", + ex2_cop_ct(49) when "110001", + ex2_cop_ct(50) when "110010", + ex2_cop_ct(51) when "110011", + ex2_cop_ct(52) when "110100", + ex2_cop_ct(53) when "110101", + ex2_cop_ct(54) when "110110", + ex2_cop_ct(55) when "110111", + ex2_cop_ct(56) when "111000", + ex2_cop_ct(57) when "111001", + ex2_cop_ct(58) when "111010", + ex2_cop_ct(59) when "111011", + ex2_cop_ct(60) when "111100", + ex2_cop_ct(61) when "111101", + ex2_cop_ct(62) when "111110", + ex2_cop_ct(63) when "111111", + '0' when others; + +with ex2_rs2_q(50 to 55) select -- Little Endian + ex2_ct(1)<= ex2_cop_ct(32) when "100000", + ex2_cop_ct(33) when "100001", + ex2_cop_ct(34) when "100010", + ex2_cop_ct(35) when "100011", + ex2_cop_ct(36) when "100100", + ex2_cop_ct(37) when "100101", + ex2_cop_ct(38) when "100110", + ex2_cop_ct(39) when "100111", + ex2_cop_ct(40) when "101000", + ex2_cop_ct(41) when "101001", + ex2_cop_ct(42) when "101010", + ex2_cop_ct(43) when "101011", + ex2_cop_ct(44) when "101100", + ex2_cop_ct(45) when "101101", + ex2_cop_ct(46) when "101110", + ex2_cop_ct(47) when "101111", + ex2_cop_ct(48) when "110000", + ex2_cop_ct(49) when "110001", + ex2_cop_ct(50) when "110010", + ex2_cop_ct(51) when "110011", + ex2_cop_ct(52) when "110100", + ex2_cop_ct(53) when "110101", + ex2_cop_ct(54) when "110110", + ex2_cop_ct(55) when "110111", + ex2_cop_ct(56) when "111000", + ex2_cop_ct(57) when "111001", + ex2_cop_ct(58) when "111010", + ex2_cop_ct(59) when "111011", + ex2_cop_ct(60) when "111100", + ex2_cop_ct(61) when "111101", + ex2_cop_ct(62) when "111110", + ex2_cop_ct(63) when "111111", + '0' when others; + +spr_cpl_ex3_ct_be <= ex3_ct_q(0); +spr_cpl_ex3_ct_le <= ex3_ct_q(1); + +-- Debug Enables + +iac_us_en(1) <= (not spr_dbcr1_iac1us(0) and not spr_dbcr1_iac1us(1)) or + ( spr_dbcr1_iac1us(0) and (spr_dbcr1_iac1us(1) xnor spr_msr_pr)); + +iac_us_en(2) <= (not spr_dbcr1_iac2us(0) and not spr_dbcr1_iac2us(1)) or + ( spr_dbcr1_iac2us(0) and (spr_dbcr1_iac2us(1) xnor spr_msr_pr)); + +iac_us_en(3) <= (not spr_dbcr1_iac3us(0) and not spr_dbcr1_iac3us(1)) or + ( spr_dbcr1_iac3us(0) and (spr_dbcr1_iac3us(1) xnor spr_msr_pr)); + +iac_us_en(4) <= (not spr_dbcr1_iac4us(0) and not spr_dbcr1_iac4us(1)) or + ( spr_dbcr1_iac4us(0) and (spr_dbcr1_iac4us(1) xnor spr_msr_pr)); + +iac_er_en(1) <= (not spr_dbcr1_iac1er(0) and not spr_dbcr1_iac1er(1)) or + ( spr_dbcr1_iac1er(0) and (spr_dbcr1_iac1er(1) xnor spr_msr_is)); + +iac_er_en(2) <= (not spr_dbcr1_iac2er(0) and not spr_dbcr1_iac2er(1)) or + ( spr_dbcr1_iac2er(0) and (spr_dbcr1_iac2er(1) xnor spr_msr_is)); + +iac_er_en(3) <= (not spr_dbcr1_iac3er(0) and not spr_dbcr1_iac3er(1)) or + ( spr_dbcr1_iac3er(0) and (spr_dbcr1_iac3er(1) xnor spr_msr_is)); + +iac_er_en(4) <= (not spr_dbcr1_iac4er(0) and not spr_dbcr1_iac4er(1)) or + ( spr_dbcr1_iac4er(0) and (spr_dbcr1_iac4er(1) xnor spr_msr_is)); + +iac1_en_d <= spr_dbcr0_iac1 and iac_us_en(1) and iac_er_en(1); +iac2_en_d <= spr_dbcr0_iac2 and iac_us_en(2) and iac_er_en(2); +iac3_en_d <= spr_dbcr0_iac3 and iac_us_en(3) and iac_er_en(3); +iac4_en_d <= spr_dbcr0_iac4 and iac_us_en(4) and iac_er_en(4); +spr_cpl_iac1_en <= iac1_en_q; +spr_cpl_iac2_en <= iac2_en_q; +spr_cpl_iac3_en <= iac3_en_q; +spr_cpl_iac4_en <= iac4_en_q; + +-- Async Interrupts +spr_cpl_crit_interrupt <= crit_interrupt_q; +spr_cpl_wdog_interrupt <= wdog_interrupt_q; +spr_cpl_dec_interrupt <= dec_interrupt_q; +spr_cpl_udec_interrupt <= udec_interrupt_q; +spr_cpl_perf_interrupt <= perf_interrupt_q; +spr_cpl_fit_interrupt <= fit_interrupt_q; +spr_cpl_ext_interrupt <= ext_interrupt_q; +spr_cpl_external_mchk <= mchk_interrupt_q; + +-- Ungated version for CPL +-- Gating for gs|me done at ex5_ivo_sel, which also gates mcsr write. +mchk_int <= cspr_tspr_crit_mask and an_ac_external_mchk_q; + +mchk_interrupt <= cspr_tspr_crit_mask and an_ac_external_mchk_q and (spr_msr_gs or spr_msr_me); +crit_interrupt <= cspr_tspr_crit_mask and an_ac_crit_interrupt_q and (spr_msr_gs or spr_msr_ce); +wdog_interrupt <= cspr_tspr_wdog_mask and spr_tsr_wis and (spr_msr_gs or spr_msr_ce) and spr_tcr_wie; +dec_interrupt <= cspr_tspr_dec_mask and spr_tsr_dis and (spr_msr_gs or spr_msr_ee) and spr_tcr_die; +udec_interrupt <= cspr_tspr_udec_mask and spr_tsr_udis and (spr_msr_gs or spr_msr_ee) and spr_tcr_udie; +perf_interrupt <= cspr_tspr_perf_mask and an_ac_perf_interrupt_q and (spr_msr_gs or spr_msr_ee); +fit_interrupt <= cspr_tspr_fit_mask and spr_tsr_fis and (spr_msr_gs or spr_msr_ee) and spr_tcr_fie; +ext_interrupt <= cspr_tspr_ext_mask and an_ac_ext_interrupt_q and (( spr_epcr_extgs and spr_msr_gs and spr_msr_ee) or + (not spr_epcr_extgs and (spr_msr_gs or spr_msr_ee))); +tspr_cspr_pm_wake_up <= ex6_any_int or + mchk_interrupt_q or + crit_interrupt_q or + wdog_interrupt_q or + dec_interrupt_q or + udec_interrupt_q or + perf_interrupt_q or + fit_interrupt_q or + ext_interrupt_q; + +tspr_cspr_async_int <= an_ac_ext_interrupt_q & an_ac_crit_interrupt_q & an_ac_perf_interrupt_q; + +tspr_cspr_gpir_match <= '1' when cspr_tspr_dbell_pirtag = gpir_do(51 to 64) else '0'; + +-- MSR Override +with cspr_tspr_msrovride_en select + mux_msr_pr <= msrovride_pr_q when '1', + spr_msr_pr when others; + +with cspr_tspr_msrovride_en select + mux_msr_gs <= msrovride_gs_q when '1', + spr_msr_gs when others; + +with cspr_tspr_msrovride_en select + mux_msr_de <= msrovride_de_q when '1', + spr_msr_de when others; + + +mux_msr_gs_d <= (others=>mux_msr_gs); +mux_msr_pr_d <= (others=>mux_msr_pr); + +udec_en <= ram_mode_q or spr_tcr_ud; + +-- FP Precise Mode +tspr_fp_precise <= fp_precise; +fp_precise <= (spr_msr_fe0 or spr_msr_fe1); + +-- IO signal assignments +tspr_msr_de <= mux_msr_de; +tspr_msr_cm <= spr_msr_cm; +tspr_msr_is <= spr_msr_is; +tspr_msr_gs <= mux_msr_gs_q(3); +tspr_msr_pr <= mux_msr_pr_q(0); +tspr_msr_ee <= spr_msr_ee; +tspr_msr_ce <= spr_msr_ce; +tspr_msr_me <= spr_msr_me; +tspr_epcr_extgs <= spr_epcr_extgs; +dbsr_event <= or_reduce(dbsr_q(45 to 63)); +spr_cpl_dbsr_ide <= spr_dbsr_ide and dbsr_event; +single_instr_mode_d <= spr_ccr3_si or (fp_precise and msr_q(MSR_FP)) or instr_trace_mode; +xu_iu_single_instr_mode <= single_instr_mode_2_q; +machine_check_d <= or_reduce(mcsr_q); +ac_tc_machine_check <= machine_check_q; + +-- Debug +tspr_debug <= ex6_int_q & + ex6_gint_q & + ex6_cint_q & + ex6_mcint_q & + ex6_esr_update_q & + ex6_dbsr_update_q & + ex6_dear_update_q & + ex6_dear_save_q & + ex6_dear_update_saved_q & + an_ac_crit_interrupt_q & + an_ac_perf_interrupt_q & + an_ac_ext_interrupt_q; + + +spr_byp_ex4_is_mtxer <= ex4_is_mtxer_q; +spr_byp_ex4_is_mfxer <= ex4_is_mfxer_q; +ex3_is_mfxer_d <= ex2_is_mfspr and ex2_xer_rdec; +ex3_is_mtxer_d <= ex2_is_mtspr and ex2_xer_rdec; + +ex2_srr0_re2 <= ex2_rfi_q; +ex2_gsrr0_re2 <= ex2_rfgi_q; +ex2_csrr0_re2 <= ex2_rfci_q; +ex2_mcsrr0_re2 <= ex2_rfmci_q; + +readmux_00 : if a2mode = 0 and hvmode = 0 generate +ex3_tspr_rt_d <= + (ccr3_do(DO'range) and (DO'range => ex2_ccr3_re )) or + (dbcr0_do(DO'range) and (DO'range => ex2_dbcr0_re )) or + (dbcr1_do(DO'range) and (DO'range => ex2_dbcr1_re )) or + (dbsr_do(DO'range) and (DO'range => ex2_dbsr_re )) or + (dear_do(DO'range) and (DO'range => ex2_dear_re )) or + (dec_do(DO'range) and (DO'range => ex2_dec_re )) or + (esr_do(DO'range) and (DO'range => ex2_esr_re )) or + (msr_do(DO'range) and (DO'range => ex2_is_mfmsr )) or + (srr0_do(DO'range) and (DO'range => (ex2_srr0_re or ex2_srr0_re2))) or + (srr1_do(DO'range) and (DO'range => ex2_srr1_re )) or + (xucr1_do(DO'range) and (DO'range => ex2_xucr1_re )); +end generate; +readmux_01 : if a2mode = 0 and hvmode = 1 generate +ex3_tspr_rt_d <= + (ccr3_do(DO'range) and (DO'range => ex2_ccr3_re )) or + (dbcr0_do(DO'range) and (DO'range => ex2_dbcr0_re )) or + (dbcr1_do(DO'range) and (DO'range => ex2_dbcr1_re )) or + (dbsr_do(DO'range) and (DO'range => ex2_dbsr_re )) or + (dear_do(DO'range) and (DO'range => ex2_dear_re )) or + (dec_do(DO'range) and (DO'range => ex2_dec_re )) or + (epcr_do(DO'range) and (DO'range => ex2_epcr_re )) or + (esr_do(DO'range) and (DO'range => ex2_esr_re )) or + (gdear_do(DO'range) and (DO'range => ex2_gdear_re )) or + (gesr_do(DO'range) and (DO'range => ex2_gesr_re )) or + (gpir_do(DO'range) and (DO'range => ex2_gpir_re )) or + (gsrr0_do(DO'range) and (DO'range => (ex2_gsrr0_re or ex2_gsrr0_re2))) or + (gsrr1_do(DO'range) and (DO'range => ex2_gsrr1_re )) or + (hacop_do(DO'range) and (DO'range => ex2_hacop_re )) or + (msr_do(DO'range) and (DO'range => ex2_is_mfmsr )) or + (msrp_do(DO'range) and (DO'range => ex2_msrp_re )) or + (srr0_do(DO'range) and (DO'range => (ex2_srr0_re or ex2_srr0_re2))) or + (srr1_do(DO'range) and (DO'range => ex2_srr1_re )) or + (xucr1_do(DO'range) and (DO'range => ex2_xucr1_re )); +end generate; +readmux_10 : if a2mode = 1 and hvmode = 0 generate +ex3_tspr_rt_d <= + (acop_do(DO'range) and (DO'range => ex2_acop_re )) or + (ccr3_do(DO'range) and (DO'range => ex2_ccr3_re )) or + (csrr0_do(DO'range) and (DO'range => (ex2_csrr0_re or ex2_csrr0_re2))) or + (csrr1_do(DO'range) and (DO'range => ex2_csrr1_re )) or + (dbcr0_do(DO'range) and (DO'range => ex2_dbcr0_re )) or + (dbcr1_do(DO'range) and (DO'range => ex2_dbcr1_re )) or + (dbsr_do(DO'range) and (DO'range => ex2_dbsr_re )) or + (dear_do(DO'range) and (DO'range => ex2_dear_re )) or + (dec_do(DO'range) and (DO'range => ex2_dec_re )) or + (decar_do(DO'range) and (DO'range => ex2_decar_re )) or + (esr_do(DO'range) and (DO'range => ex2_esr_re )) or + (mcsr_do(DO'range) and (DO'range => ex2_mcsr_re )) or + (mcsrr0_do(DO'range) and (DO'range => (ex2_mcsrr0_re or ex2_mcsrr0_re2))) or + (mcsrr1_do(DO'range) and (DO'range => ex2_mcsrr1_re )) or + (msr_do(DO'range) and (DO'range => ex2_is_mfmsr )) or + (srr0_do(DO'range) and (DO'range => (ex2_srr0_re or ex2_srr0_re2))) or + (srr1_do(DO'range) and (DO'range => ex2_srr1_re )) or + (tcr_do(DO'range) and (DO'range => ex2_tcr_re )) or + (tsr_do(DO'range) and (DO'range => ex2_tsr_re )) or + (udec_do(DO'range) and (DO'range => ex2_udec_re )) or + (xucr1_do(DO'range) and (DO'range => ex2_xucr1_re )); +end generate; +readmux_11 : if a2mode = 1 and hvmode = 1 generate +ex3_tspr_rt_d <= + (acop_do(DO'range) and (DO'range => ex2_acop_re )) or + (ccr3_do(DO'range) and (DO'range => ex2_ccr3_re )) or + (csrr0_do(DO'range) and (DO'range => (ex2_csrr0_re or ex2_csrr0_re2))) or + (csrr1_do(DO'range) and (DO'range => ex2_csrr1_re )) or + (dbcr0_do(DO'range) and (DO'range => ex2_dbcr0_re )) or + (dbcr1_do(DO'range) and (DO'range => ex2_dbcr1_re )) or + (dbsr_do(DO'range) and (DO'range => ex2_dbsr_re )) or + (dear_do(DO'range) and (DO'range => ex2_dear_re )) or + (dec_do(DO'range) and (DO'range => ex2_dec_re )) or + (decar_do(DO'range) and (DO'range => ex2_decar_re )) or + (epcr_do(DO'range) and (DO'range => ex2_epcr_re )) or + (esr_do(DO'range) and (DO'range => ex2_esr_re )) or + (gdear_do(DO'range) and (DO'range => ex2_gdear_re )) or + (gesr_do(DO'range) and (DO'range => ex2_gesr_re )) or + (gpir_do(DO'range) and (DO'range => ex2_gpir_re )) or + (gsrr0_do(DO'range) and (DO'range => (ex2_gsrr0_re or ex2_gsrr0_re2))) or + (gsrr1_do(DO'range) and (DO'range => ex2_gsrr1_re )) or + (hacop_do(DO'range) and (DO'range => ex2_hacop_re )) or + (mcsr_do(DO'range) and (DO'range => ex2_mcsr_re )) or + (mcsrr0_do(DO'range) and (DO'range => (ex2_mcsrr0_re or ex2_mcsrr0_re2))) or + (mcsrr1_do(DO'range) and (DO'range => ex2_mcsrr1_re )) or + (msr_do(DO'range) and (DO'range => ex2_is_mfmsr )) or + (msrp_do(DO'range) and (DO'range => ex2_msrp_re )) or + (srr0_do(DO'range) and (DO'range => (ex2_srr0_re or ex2_srr0_re2))) or + (srr1_do(DO'range) and (DO'range => ex2_srr1_re )) or + (tcr_do(DO'range) and (DO'range => ex2_tcr_re )) or + (tsr_do(DO'range) and (DO'range => ex2_tsr_re )) or + (udec_do(DO'range) and (DO'range => ex2_udec_re )) or + (xucr1_do(DO'range) and (DO'range => ex2_xucr1_re )); +end generate; + +tspr_cspr_ex3_tspr_rt <= ex3_tspr_rt_q and fanout(ex3_tid_rpwr_q,regsize); + +ex2_pir_rdec <= (ex2_instr(11 to 20) = "1111001000"); -- 286 +ex2_acop_rdec <= (ex2_instr(11 to 20) = "1111100000"); -- 31 +ex2_ccr3_rdec <= (ex2_instr(11 to 20) = "1010111111"); -- 1013 +ex2_csrr0_rdec <= (ex2_instr(11 to 20) = "1101000001"); -- 58 +ex2_csrr1_rdec <= (ex2_instr(11 to 20) = "1101100001"); -- 59 +ex2_ctr_rdec <= (ex2_instr(11 to 20) = "0100100000"); -- 9 +ex2_dbcr0_rdec <= (ex2_instr(11 to 20) = "1010001001"); -- 308 +ex2_dbcr1_rdec <= (ex2_instr(11 to 20) = "1010101001"); -- 309 +ex2_dbcr2_rdec <= (ex2_instr(11 to 20) = "1011001001"); -- 310 +ex2_dbcr3_rdec <= (ex2_instr(11 to 20) = "1000011010"); -- 848 +ex2_dbsr_rdec <= (ex2_instr(11 to 20) = "1000001001"); -- 304 +ex2_dear_rdec <= (ex2_instr(11 to 20) = "1110100001"); -- 61 +ex2_dec_rdec <= (ex2_instr(11 to 20) = "1011000000"); -- 22 +ex2_decar_rdec <= (ex2_instr(11 to 20) = "1011000001"); -- 54 +ex2_epcr_rdec <= (ex2_instr(11 to 20) = "1001101001"); -- 307 +ex2_esr_rdec <= (ex2_instr(11 to 20) = "1111000001"); -- 62 +ex2_gdear_rdec <= (ex2_instr(11 to 20) = "1110101011"); -- 381 +ex2_gesr_rdec <= (ex2_instr(11 to 20) = "1111101011"); -- 383 +ex2_gpir_rdec <= (ex2_instr(11 to 20) = "1111001011"); -- 382 +ex2_gsrr0_rdec <= (ex2_instr(11 to 20) = "1101001011"); -- 378 +ex2_gsrr1_rdec <= (ex2_instr(11 to 20) = "1101101011"); -- 379 +ex2_hacop_rdec <= (ex2_instr(11 to 20) = "1111101010"); -- 351 +ex2_iar_rdec <= (ex2_instr(11 to 20) = "1001011011"); -- 882 +ex2_lr_rdec <= (ex2_instr(11 to 20) = "0100000000"); -- 8 +ex2_mcsr_rdec <= (ex2_instr(11 to 20) = "1110010001"); -- 572 +ex2_mcsrr0_rdec <= (ex2_instr(11 to 20) = "1101010001"); -- 570 +ex2_mcsrr1_rdec <= (ex2_instr(11 to 20) = "1101110001"); -- 571 +ex2_msrp_rdec <= (ex2_instr(11 to 20) = "1011101001"); -- 311 +ex2_srr0_rdec <= (ex2_instr(11 to 20) = "1101000000"); -- 26 +ex2_srr1_rdec <= (ex2_instr(11 to 20) = "1101100000"); -- 27 +ex2_tcr_rdec <= (ex2_instr(11 to 20) = "1010001010"); -- 340 +ex2_tsr_rdec <= (ex2_instr(11 to 20) = "1000001010"); -- 336 +ex2_udec_rdec <= udec_en and + (ex2_instr(11 to 20) = "0011010001"); -- 550 +ex2_xer_rdec <= (ex2_instr(11 to 20) = "0000100000"); -- 1 +ex2_xucr1_rdec <= (ex2_instr(11 to 20) = "1001111010"); -- 851 +ex2_acop_re <= ex2_acop_rdec; +ex2_ccr3_re <= ex2_ccr3_rdec; +ex2_csrr0_re <= ex2_csrr0_rdec; +ex2_csrr1_re <= ex2_csrr1_rdec; +ex2_ctr_re <= ex2_ctr_rdec; +ex2_dbcr0_re <= ex2_dbcr0_rdec; +ex2_dbcr1_re <= ex2_dbcr1_rdec; +ex2_dbcr2_re <= ex2_dbcr2_rdec; +ex2_dbcr3_re <= ex2_dbcr3_rdec; +ex2_dbsr_re <= ex2_dbsr_rdec; +ex2_dear_re <= ex2_dear_rdec and not mux_msr_gs_q(0); +ex2_dec_re <= ex2_dec_rdec; +ex2_decar_re <= ex2_decar_rdec; +ex2_epcr_re <= ex2_epcr_rdec; +ex2_esr_re <= ex2_esr_rdec and not mux_msr_gs_q(0); +ex2_gdear_re <= (ex2_gdear_rdec or (ex2_dear_rdec and mux_msr_gs_q(0))); +ex2_gesr_re <= (ex2_gesr_rdec or (ex2_esr_rdec and mux_msr_gs_q(0))); +ex2_gpir_re <= (ex2_gpir_rdec or (ex2_pir_rdec and mux_msr_gs_q(0))); +ex2_gsrr0_re <= (ex2_gsrr0_rdec or (ex2_srr0_rdec and mux_msr_gs_q(0))); +ex2_gsrr1_re <= (ex2_gsrr1_rdec or (ex2_srr1_rdec and mux_msr_gs_q(0))); +ex2_hacop_re <= ex2_hacop_rdec; +ex2_iar_re <= ex2_iar_rdec; +ex2_lr_re <= ex2_lr_rdec; +ex2_mcsr_re <= ex2_mcsr_rdec; +ex2_mcsrr0_re <= ex2_mcsrr0_rdec; +ex2_mcsrr1_re <= ex2_mcsrr1_rdec; +ex2_msrp_re <= ex2_msrp_rdec; +ex2_srr0_re <= ex2_srr0_rdec and not mux_msr_gs_q(0); +ex2_srr1_re <= ex2_srr1_rdec and not mux_msr_gs_q(0); +ex2_tcr_re <= ex2_tcr_rdec; +ex2_tsr_re <= ex2_tsr_rdec; +ex2_udec_re <= ex2_udec_rdec; +ex2_xer_re <= ex2_xer_rdec; +ex2_xucr1_re <= ex2_xucr1_rdec; + +ex2_acop_wdec <= ex2_acop_rdec; +ex2_ccr3_wdec <= ex2_ccr3_rdec; +ex2_csrr0_wdec <= ex2_csrr0_rdec; +ex2_csrr1_wdec <= ex2_csrr1_rdec; +ex2_ctr_wdec <= ex2_ctr_rdec; +ex2_dbcr0_wdec <= ex2_dbcr0_rdec; +ex2_dbcr1_wdec <= ex2_dbcr1_rdec; +ex2_dbcr2_wdec <= ex2_dbcr2_rdec; +ex2_dbcr3_wdec <= ex2_dbcr3_rdec; +ex2_dbsr_wdec <= ex2_dbsr_rdec; +ex2_dbsrwr_wdec <= (ex2_instr(11 to 20) = "1001001001"); -- 306 +ex2_dear_wdec <= ex2_dear_rdec; +ex2_dec_wdec <= ex2_dec_rdec; +ex2_decar_wdec <= ex2_decar_rdec; +ex2_epcr_wdec <= ex2_epcr_rdec; +ex2_esr_wdec <= ex2_esr_rdec; +ex2_gdear_wdec <= ex2_gdear_rdec; +ex2_gesr_wdec <= ex2_gesr_rdec; +ex2_gpir_wdec <= (ex2_instr(11 to 20) = "1111001011"); -- 382 +ex2_gsrr0_wdec <= ex2_gsrr0_rdec; +ex2_gsrr1_wdec <= ex2_gsrr1_rdec; +ex2_hacop_wdec <= (ex2_instr(11 to 20) = "1111101010"); -- 351 +ex2_iar_wdec <= ex2_iar_rdec; +ex2_lr_wdec <= ex2_lr_rdec; +ex2_mcsr_wdec <= ex2_mcsr_rdec; +ex2_mcsrr0_wdec <= ex2_mcsrr0_rdec; +ex2_mcsrr1_wdec <= ex2_mcsrr1_rdec; +ex2_msrp_wdec <= ex2_msrp_rdec; +ex2_srr0_wdec <= ex2_srr0_rdec; +ex2_srr1_wdec <= ex2_srr1_rdec; +ex2_tcr_wdec <= ex2_tcr_rdec; +ex2_tsr_wdec <= ex2_tsr_rdec; +ex2_udec_wdec <= udec_en and + ex2_udec_rdec; +ex2_xer_wdec <= ex2_xer_rdec; +ex2_xucr1_wdec <= ex2_xucr1_rdec; +ex2_acop_we <= ex2_acop_wdec; +ex2_ccr3_we <= ex2_ccr3_wdec; +ex2_csrr0_we <= ex2_csrr0_wdec; +ex2_csrr1_we <= ex2_csrr1_wdec; +ex2_ctr_we <= ex2_ctr_wdec; +ex2_dbcr0_we <= ex2_dbcr0_wdec; +ex2_dbcr1_we <= ex2_dbcr1_wdec; +ex2_dbcr2_we <= ex2_dbcr2_wdec; +ex2_dbcr3_we <= ex2_dbcr3_wdec; +ex2_dbsr_we <= ex2_dbsr_wdec; +ex2_dbsrwr_we <= ex2_dbsrwr_wdec; +ex2_dear_we <= ex2_dear_wdec and not mux_msr_gs_q(1); +ex2_dec_we <= ex2_dec_wdec; +ex2_decar_we <= ex2_decar_wdec; +ex2_epcr_we <= ex2_epcr_wdec; +ex2_esr_we <= ex2_esr_wdec and not mux_msr_gs_q(1); +ex2_gdear_we <= (ex2_gdear_wdec or (ex2_dear_wdec and mux_msr_gs_q(1))); +ex2_gesr_we <= (ex2_gesr_wdec or (ex2_esr_wdec and mux_msr_gs_q(1))); +ex2_gpir_we <= ex2_gpir_wdec; +ex2_gsrr0_we <= (ex2_gsrr0_wdec or (ex2_srr0_wdec and mux_msr_gs_q(1))); +ex2_gsrr1_we <= (ex2_gsrr1_wdec or (ex2_srr1_wdec and mux_msr_gs_q(1))); +ex2_hacop_we <= ex2_hacop_wdec; +ex2_iar_we <= ex2_iar_wdec; +ex2_lr_we <= ex2_lr_wdec; +ex2_mcsr_we <= ex2_mcsr_wdec; +ex2_mcsrr0_we <= ex2_mcsrr0_wdec; +ex2_mcsrr1_we <= ex2_mcsrr1_wdec; +ex2_msrp_we <= ex2_msrp_wdec; +ex2_srr0_we <= ex2_srr0_wdec and not mux_msr_gs_q(1); +ex2_srr1_we <= ex2_srr1_wdec and not mux_msr_gs_q(1); +ex2_tcr_we <= ex2_tcr_wdec; +ex2_tsr_we <= ex2_tsr_wdec; +ex2_udec_we <= ex2_udec_wdec; +ex2_xer_we <= ex2_xer_wdec; +ex2_xucr1_we <= ex2_xucr1_wdec; + +ex6_acop_wdec <= (ex6_instr(11 to 20) = "1111100000"); -- 31 +ex6_ccr3_wdec <= (ex6_instr(11 to 20) = "1010111111"); -- 1013 +ex6_csrr0_wdec <= (ex6_instr(11 to 20) = "1101000001"); -- 58 +ex6_csrr1_wdec <= (ex6_instr(11 to 20) = "1101100001"); -- 59 +ex6_dbcr0_wdec <= (ex6_instr(11 to 20) = "1010001001"); -- 308 +ex6_dbcr1_wdec <= (ex6_instr(11 to 20) = "1010101001"); -- 309 +ex6_dbsr_wdec <= (ex6_instr(11 to 20) = "1000001001"); -- 304 +ex6_dbsrwr_wdec <= (ex6_instr(11 to 20) = "1001001001"); -- 306 +ex6_dear_wdec <= (ex6_instr(11 to 20) = "1110100001"); -- 61 +ex6_dec_wdec <= (ex6_instr(11 to 20) = "1011000000"); -- 22 +ex6_decar_wdec <= (ex6_instr(11 to 20) = "1011000001"); -- 54 +ex6_epcr_wdec <= (ex6_instr(11 to 20) = "1001101001"); -- 307 +ex6_esr_wdec <= (ex6_instr(11 to 20) = "1111000001"); -- 62 +ex6_gdear_wdec <= (ex6_instr(11 to 20) = "1110101011"); -- 381 +ex6_gesr_wdec <= (ex6_instr(11 to 20) = "1111101011"); -- 383 +ex6_gpir_wdec <= (ex6_instr(11 to 20) = "1111001011"); -- 382 +ex6_gsrr0_wdec <= (ex6_instr(11 to 20) = "1101001011"); -- 378 +ex6_gsrr1_wdec <= (ex6_instr(11 to 20) = "1101101011"); -- 379 +ex6_hacop_wdec <= (ex6_instr(11 to 20) = "1111101010"); -- 351 +ex6_mcsr_wdec <= (ex6_instr(11 to 20) = "1110010001"); -- 572 +ex6_mcsrr0_wdec <= (ex6_instr(11 to 20) = "1101010001"); -- 570 +ex6_mcsrr1_wdec <= (ex6_instr(11 to 20) = "1101110001"); -- 571 +ex6_msr_wdec <= ex6_is_mtmsr; +ex6_msrp_wdec <= (ex6_instr(11 to 20) = "1011101001"); -- 311 +ex6_srr0_wdec <= (ex6_instr(11 to 20) = "1101000000"); -- 26 +ex6_srr1_wdec <= (ex6_instr(11 to 20) = "1101100000"); -- 27 +ex6_tcr_wdec <= (ex6_instr(11 to 20) = "1010001010"); -- 340 +ex6_tsr_wdec <= (ex6_instr(11 to 20) = "1000001010"); -- 336 +ex6_udec_wdec <= udec_en and + (ex6_instr(11 to 20) = "0011010001"); -- 550 +ex6_xucr1_wdec <= (ex6_instr(11 to 20) = "1001111010"); -- 851 +ex6_acop_we <= ex6_val and ex6_is_mtspr and ex6_acop_wdec; +ex6_ccr3_we <= ex6_val and ex6_is_mtspr and ex6_ccr3_wdec; +ex6_csrr0_we <= ex6_val and ex6_is_mtspr and ex6_csrr0_wdec; +ex6_csrr1_we <= ex6_val and ex6_is_mtspr and ex6_csrr1_wdec; +ex6_dbcr0_we <= ex6_val and ex6_is_mtspr and ex6_dbcr0_wdec; +ex6_dbcr1_we <= ex6_val and ex6_is_mtspr and ex6_dbcr1_wdec; +ex6_dbsr_we <= ex6_val and ex6_is_mtspr and ex6_dbsr_wdec; +ex6_dbsrwr_we <= ex6_val and ex6_is_mtspr and ex6_dbsrwr_wdec; +ex6_dear_we <= ex6_val and ex6_is_mtspr and ex6_dear_wdec and not mux_msr_gs_q(2); +ex6_dec_we <= ex6_val and ex6_is_mtspr and ex6_dec_wdec; +ex6_decar_we <= ex6_val and ex6_is_mtspr and ex6_decar_wdec; +ex6_epcr_we <= ex6_val and ex6_is_mtspr and ex6_epcr_wdec; +ex6_esr_we <= ex6_val and ex6_is_mtspr and ex6_esr_wdec and not mux_msr_gs_q(2); +ex6_gdear_we <= ex6_val and ex6_is_mtspr and (ex6_gdear_wdec or (ex6_dear_wdec and mux_msr_gs_q(2))); +ex6_gesr_we <= ex6_val and ex6_is_mtspr and (ex6_gesr_wdec or (ex6_esr_wdec and mux_msr_gs_q(2))); +ex6_gpir_we <= ex6_val and ex6_is_mtspr and ex6_gpir_wdec; +ex6_gsrr0_we <= ex6_val and ex6_is_mtspr and (ex6_gsrr0_wdec or (ex6_srr0_wdec and mux_msr_gs_q(2))); +ex6_gsrr1_we <= ex6_val and ex6_is_mtspr and (ex6_gsrr1_wdec or (ex6_srr1_wdec and mux_msr_gs_q(2))); +ex6_hacop_we <= ex6_val and ex6_is_mtspr and ex6_hacop_wdec; +ex6_mcsr_we <= ex6_val and ex6_is_mtspr and ex6_mcsr_wdec; +ex6_mcsrr0_we <= ex6_val and ex6_is_mtspr and ex6_mcsrr0_wdec; +ex6_mcsrr1_we <= ex6_val and ex6_is_mtspr and ex6_mcsrr1_wdec; +ex6_msr_we <= ex6_val and ex6_msr_wdec; +ex6_msrp_we <= ex6_val and ex6_is_mtspr and ex6_msrp_wdec; +ex6_srr0_we <= ex6_val and ex6_is_mtspr and ex6_srr0_wdec and not mux_msr_gs_q(2); +ex6_srr1_we <= ex6_val and ex6_is_mtspr and ex6_srr1_wdec and not mux_msr_gs_q(2); +ex6_tcr_we <= ex6_val and ex6_is_mtspr and ex6_tcr_wdec; +ex6_tsr_we <= ex6_val and ex6_is_mtspr and ex6_tsr_wdec; +ex6_udec_we <= ex6_val and ex6_is_mtspr and ex6_udec_wdec; +ex6_xucr1_we <= ex6_val and ex6_is_mtspr and ex6_xucr1_wdec; + +-- Illegal SPR checks +ill_spr_00 : if a2mode = 0 and hvmode = 0 generate +tspr_cspr_illeg_mtspr_b <= + ex2_ccr3_wdec or ex2_ctr_wdec or ex2_dbcr0_wdec + or ex2_dbcr1_wdec or ex2_dbcr3_wdec or ex2_dbsr_wdec + or ex2_dear_wdec or ex2_dec_wdec or ex2_esr_wdec + or ex2_iar_wdec or ex2_lr_wdec or ex2_srr0_wdec + or ex2_srr1_wdec or ex2_xer_wdec or ex2_xucr1_wdec ; + +tspr_cspr_illeg_mfspr_b <= + ex2_ccr3_rdec or ex2_ctr_rdec or ex2_dbcr0_rdec + or ex2_dbcr1_rdec or ex2_dbcr3_rdec or ex2_dbsr_rdec + or ex2_dear_rdec or ex2_dec_rdec or ex2_esr_rdec + or ex2_iar_rdec or ex2_lr_rdec or ex2_srr0_rdec + or ex2_srr1_rdec or ex2_xer_rdec or ex2_xucr1_rdec ; + +tspr_cspr_hypv_mtspr <= + ex2_ccr3_we or ex2_dbcr0_we or ex2_dbcr1_we + or ex2_dbcr3_we or ex2_dbsr_we or ex2_dec_we + or ex2_iar_we or ex2_xucr1_we ; + +tspr_cspr_hypv_mfspr <= + ex2_ccr3_re or ex2_dbcr0_re or ex2_dbcr1_re + or ex2_dbcr3_re or ex2_dbsr_re or ex2_dec_re + or ex2_iar_re or ex2_xucr1_re ; + +end generate; +ill_spr_01 : if a2mode = 0 and hvmode = 1 generate +tspr_cspr_illeg_mtspr_b <= + ex2_ccr3_wdec or ex2_ctr_wdec or ex2_dbcr0_wdec + or ex2_dbcr1_wdec or ex2_dbcr3_wdec or ex2_dbsr_wdec + or ex2_dbsrwr_wdec or ex2_dear_wdec or ex2_dec_wdec + or ex2_epcr_wdec or ex2_esr_wdec or ex2_gdear_wdec + or ex2_gesr_wdec or ex2_gpir_wdec or ex2_gsrr0_wdec + or ex2_gsrr1_wdec or ex2_hacop_wdec or ex2_iar_wdec + or ex2_lr_wdec or ex2_msrp_wdec or ex2_srr0_wdec + or ex2_srr1_wdec or ex2_xer_wdec or ex2_xucr1_wdec ; + +tspr_cspr_illeg_mfspr_b <= + ex2_ccr3_rdec or ex2_ctr_rdec or ex2_dbcr0_rdec + or ex2_dbcr1_rdec or ex2_dbcr3_rdec or ex2_dbsr_rdec + or ex2_dear_rdec or ex2_dec_rdec or ex2_epcr_rdec + or ex2_esr_rdec or ex2_gdear_rdec or ex2_gesr_rdec + or ex2_gpir_rdec or ex2_gsrr0_rdec or ex2_gsrr1_rdec + or ex2_hacop_rdec or ex2_iar_rdec or ex2_lr_rdec + or ex2_msrp_rdec or ex2_srr0_rdec or ex2_srr1_rdec + or ex2_xer_rdec or ex2_xucr1_rdec ; + +tspr_cspr_hypv_mtspr <= + ex2_ccr3_we or ex2_dbcr0_we or ex2_dbcr1_we + or ex2_dbcr3_we or ex2_dbsr_we or ex2_dbsrwr_we + or ex2_dec_we or ex2_epcr_we or ex2_gpir_we + or ex2_hacop_we or ex2_iar_we or ex2_msrp_we + or ex2_xucr1_we ; + +tspr_cspr_hypv_mfspr <= + ex2_ccr3_re or ex2_dbcr0_re or ex2_dbcr1_re + or ex2_dbcr3_re or ex2_dbsr_re or ex2_dec_re + or ex2_epcr_re or ex2_iar_re or ex2_msrp_re + or ex2_xucr1_re ; + +end generate; +ill_spr_10 : if a2mode = 1 and hvmode = 0 generate +tspr_cspr_illeg_mtspr_b <= + ex2_acop_wdec or ex2_ccr3_wdec or ex2_csrr0_wdec + or ex2_csrr1_wdec or ex2_ctr_wdec or ex2_dbcr0_wdec + or ex2_dbcr1_wdec or ex2_dbcr2_wdec or ex2_dbcr3_wdec + or ex2_dbsr_wdec or ex2_dear_wdec or ex2_dec_wdec + or ex2_decar_wdec or ex2_esr_wdec or ex2_iar_wdec + or ex2_lr_wdec or ex2_mcsr_wdec or ex2_mcsrr0_wdec + or ex2_mcsrr1_wdec or ex2_srr0_wdec or ex2_srr1_wdec + or ex2_tcr_wdec or ex2_tsr_wdec or ex2_udec_wdec + or ex2_xer_wdec or ex2_xucr1_wdec ; + +tspr_cspr_illeg_mfspr_b <= + ex2_acop_rdec or ex2_ccr3_rdec or ex2_csrr0_rdec + or ex2_csrr1_rdec or ex2_ctr_rdec or ex2_dbcr0_rdec + or ex2_dbcr1_rdec or ex2_dbcr2_rdec or ex2_dbcr3_rdec + or ex2_dbsr_rdec or ex2_dear_rdec or ex2_dec_rdec + or ex2_decar_rdec or ex2_esr_rdec or ex2_iar_rdec + or ex2_lr_rdec or ex2_mcsr_rdec or ex2_mcsrr0_rdec + or ex2_mcsrr1_rdec or ex2_srr0_rdec or ex2_srr1_rdec + or ex2_tcr_rdec or ex2_tsr_rdec or ex2_udec_rdec + or ex2_xer_rdec or ex2_xucr1_rdec ; + +tspr_cspr_hypv_mtspr <= + ex2_ccr3_we or ex2_csrr0_we or ex2_csrr1_we + or ex2_dbcr0_we or ex2_dbcr1_we or ex2_dbcr2_we + or ex2_dbcr3_we or ex2_dbsr_we or ex2_dec_we + or ex2_decar_we or ex2_iar_we or ex2_mcsr_we + or ex2_mcsrr0_we or ex2_mcsrr1_we or ex2_tcr_we + or ex2_tsr_we or ex2_xucr1_we ; + +tspr_cspr_hypv_mfspr <= + ex2_ccr3_re or ex2_csrr0_re or ex2_csrr1_re + or ex2_dbcr0_re or ex2_dbcr1_re or ex2_dbcr2_re + or ex2_dbcr3_re or ex2_dbsr_re or ex2_dec_re + or ex2_decar_re or ex2_iar_re or ex2_mcsr_re + or ex2_mcsrr0_re or ex2_mcsrr1_re or ex2_tcr_re + or ex2_tsr_re or ex2_xucr1_re ; + +end generate; +ill_spr_11 : if a2mode = 1 and hvmode = 1 generate +tspr_cspr_illeg_mtspr_b <= + ex2_acop_wdec or ex2_ccr3_wdec or ex2_csrr0_wdec + or ex2_csrr1_wdec or ex2_ctr_wdec or ex2_dbcr0_wdec + or ex2_dbcr1_wdec or ex2_dbcr2_wdec or ex2_dbcr3_wdec + or ex2_dbsr_wdec or ex2_dbsrwr_wdec or ex2_dear_wdec + or ex2_dec_wdec or ex2_decar_wdec or ex2_epcr_wdec + or ex2_esr_wdec or ex2_gdear_wdec or ex2_gesr_wdec + or ex2_gpir_wdec or ex2_gsrr0_wdec or ex2_gsrr1_wdec + or ex2_hacop_wdec or ex2_iar_wdec or ex2_lr_wdec + or ex2_mcsr_wdec or ex2_mcsrr0_wdec or ex2_mcsrr1_wdec + or ex2_msrp_wdec or ex2_srr0_wdec or ex2_srr1_wdec + or ex2_tcr_wdec or ex2_tsr_wdec or ex2_udec_wdec + or ex2_xer_wdec or ex2_xucr1_wdec ; + +tspr_cspr_illeg_mfspr_b <= + ex2_acop_rdec or ex2_ccr3_rdec or ex2_csrr0_rdec + or ex2_csrr1_rdec or ex2_ctr_rdec or ex2_dbcr0_rdec + or ex2_dbcr1_rdec or ex2_dbcr2_rdec or ex2_dbcr3_rdec + or ex2_dbsr_rdec or ex2_dear_rdec or ex2_dec_rdec + or ex2_decar_rdec or ex2_epcr_rdec or ex2_esr_rdec + or ex2_gdear_rdec or ex2_gesr_rdec or ex2_gpir_rdec + or ex2_gsrr0_rdec or ex2_gsrr1_rdec or ex2_hacop_rdec + or ex2_iar_rdec or ex2_lr_rdec or ex2_mcsr_rdec + or ex2_mcsrr0_rdec or ex2_mcsrr1_rdec or ex2_msrp_rdec + or ex2_srr0_rdec or ex2_srr1_rdec or ex2_tcr_rdec + or ex2_tsr_rdec or ex2_udec_rdec or ex2_xer_rdec + or ex2_xucr1_rdec ; + +tspr_cspr_hypv_mtspr <= + ex2_ccr3_we or ex2_csrr0_we or ex2_csrr1_we + or ex2_dbcr0_we or ex2_dbcr1_we or ex2_dbcr2_we + or ex2_dbcr3_we or ex2_dbsr_we or ex2_dbsrwr_we + or ex2_dec_we or ex2_decar_we or ex2_epcr_we + or ex2_gpir_we or ex2_hacop_we or ex2_iar_we + or ex2_mcsr_we or ex2_mcsrr0_we or ex2_mcsrr1_we + or ex2_msrp_we or ex2_tcr_we or ex2_tsr_we + or ex2_xucr1_we ; + +tspr_cspr_hypv_mfspr <= + ex2_ccr3_re or ex2_csrr0_re or ex2_csrr1_re + or ex2_dbcr0_re or ex2_dbcr1_re or ex2_dbcr2_re + or ex2_dbcr3_re or ex2_dbsr_re or ex2_dec_re + or ex2_decar_re or ex2_epcr_re or ex2_iar_re + or ex2_mcsr_re or ex2_mcsrr0_re or ex2_mcsrr1_re + or ex2_msrp_re or ex2_tcr_re or ex2_tsr_re + or ex2_xucr1_re ; + +end generate; + +spr_acop_ct <= acop_q(32 to 63); +spr_ccr3_en_eepri <= ccr3_q(62); +spr_ccr3_si <= ccr3_q(63); +spr_dbcr0_idm <= dbcr0_q(43); +spr_dbcr0_rst <= dbcr0_q(44 to 45); +spr_dbcr0_icmp <= dbcr0_q(46); +spr_dbcr0_brt <= dbcr0_q(47); +spr_dbcr0_irpt <= dbcr0_q(48); +spr_dbcr0_trap <= dbcr0_q(49); +spr_dbcr0_iac1 <= dbcr0_q(50); +spr_dbcr0_iac2 <= dbcr0_q(51); +spr_dbcr0_iac3 <= dbcr0_q(52); +spr_dbcr0_iac4 <= dbcr0_q(53); +spr_dbcr0_dac1 <= dbcr0_q(54 to 55); +spr_dbcr0_dac2 <= dbcr0_q(56 to 57); +spr_dbcr0_ret <= dbcr0_q(58); +spr_dbcr0_dac3 <= dbcr0_q(59 to 60); +spr_dbcr0_dac4 <= dbcr0_q(61 to 62); +spr_dbcr0_ft <= dbcr0_q(63); +spr_dbcr1_iac1us <= dbcr1_q(46 to 47); +spr_dbcr1_iac1er <= dbcr1_q(48 to 49); +spr_dbcr1_iac2us <= dbcr1_q(50 to 51); +spr_dbcr1_iac2er <= dbcr1_q(52 to 53); +spr_dbcr1_iac12m <= dbcr1_q(54); +spr_dbcr1_iac3us <= dbcr1_q(55 to 56); +spr_dbcr1_iac3er <= dbcr1_q(57 to 58); +spr_dbcr1_iac4us <= dbcr1_q(59 to 60); +spr_dbcr1_iac4er <= dbcr1_q(61 to 62); +spr_dbcr1_iac34m <= dbcr1_q(63); +spr_dbsr_ide <= dbsr_q(44); +spr_epcr_extgs <= epcr_q(54); +spr_epcr_dtlbgs <= epcr_q(55); +spr_epcr_itlbgs <= epcr_q(56); +spr_epcr_dsigs <= epcr_q(57); +spr_epcr_isigs <= epcr_q(58); +spr_epcr_duvd <= epcr_q(59); +spr_epcr_icm <= epcr_q(60); +spr_epcr_gicm <= epcr_q(61); +spr_epcr_dgtmi <= epcr_q(62); +xu_mm_spr_epcr_dmiuh <= epcr_q(63); +spr_hacop_ct <= hacop_q(32 to 63); +spr_msr_cm <= msr_q(50); +spr_msr_gs <= msr_q(51); +spr_msr_ucle <= msr_q(52); +spr_msr_spv <= msr_q(53); +spr_msr_ce <= msr_q(54); +spr_msr_ee <= msr_q(55); +spr_msr_pr <= msr_q(56); +spr_msr_fp <= msr_q(57); +spr_msr_me <= msr_q(58); +spr_msr_fe0 <= msr_q(59); +spr_msr_de <= msr_q(60); +spr_msr_fe1 <= msr_q(61); +spr_msr_is <= msr_q(62); +spr_msr_ds <= msr_q(63); +spr_msrp_uclep <= msrp_q(62); +spr_tcr_wp <= tcr_q(52 to 53); +spr_tcr_wrc <= tcr_q(54 to 55); +spr_tcr_wie <= tcr_q(56); +spr_tcr_die <= tcr_q(57); +spr_tcr_fp <= tcr_q(58 to 59); +spr_tcr_fie <= tcr_q(60); +spr_tcr_are <= tcr_q(61); +spr_tcr_udie <= tcr_q(62); +spr_tcr_ud <= tcr_q(63); +spr_tsr_enw <= tsr_q(59); +spr_tsr_wis <= tsr_q(60); +spr_tsr_dis <= tsr_q(61); +spr_tsr_fis <= tsr_q(62); +spr_tsr_udis <= tsr_q(63); +spr_xucr1_ll_tb_sel <= xucr1_q(59 to 61); +spr_xucr1_ll_sel <= xucr1_q(62); +spr_xucr1_ll_en <= xucr1_q(63); + +-- ACOP +ex6_acop_di <= ex6_spr_wd(32 to 63) ; --CT +acop_do <= tidn(0 to 0) & + tidn(0 to 31) & --/// + acop_q(32 to 63) ; --CT +-- CCR3 +ex6_ccr3_di <= ex6_spr_wd(62 to 62) & --EN_EEPRI + ex6_spr_wd(63 to 63) ; --SI +ccr3_do <= tidn(0 to 0) & + tidn(0 to 31) & --/// + tidn(32 to 61) & --/// + ccr3_q(62 to 62) & --EN_EEPRI + ccr3_q(63 to 63) ; --SI +-- CSRR0 +ex6_csrr0_di <= ex6_spr_wd(62-(eff_ifar) to 61) ; --SRR0 +csrr0_do <= tidn(0 to 62-(eff_ifar)) & + csrr0_q(64-(eff_ifar) to 63) & --SRR0 + tidn(62 to 63) ; --/// +-- CSRR1 +ex6_csrr1_di <= ex6_spr_wd(32 to 32) & --CM + ex6_spr_wd(35 to 35) & --GS + ex6_spr_wd(37 to 37) & --UCLE + ex6_spr_wd(38 to 38) & --SPV + ex6_spr_wd(46 to 46) & --CE + ex6_spr_wd(48 to 48) & --EE + ex6_spr_wd(49 to 49) & --PR + ex6_spr_wd(50 to 50) & --FP + ex6_spr_wd(51 to 51) & --ME + ex6_spr_wd(52 to 52) & --FE0 + ex6_spr_wd(54 to 54) & --DE + ex6_spr_wd(55 to 55) & --FE1 + ex6_spr_wd(58 to 58) & --IS + ex6_spr_wd(59 to 59) ; --DS +csrr1_do <= tidn(0 to 0) & + tidn(0 to 31) & --/// + csrr1_q(50 to 50) & --CM + tidn(33 to 34) & --/// + csrr1_q(51 to 51) & --GS + tidn(36 to 36) & --/// + csrr1_q(52 to 52) & --UCLE + csrr1_q(53 to 53) & --SPV + tidn(39 to 45) & --/// + csrr1_q(54 to 54) & --CE + tidn(47 to 47) & --/// + csrr1_q(55 to 55) & --EE + csrr1_q(56 to 56) & --PR + csrr1_q(57 to 57) & --FP + csrr1_q(58 to 58) & --ME + csrr1_q(59 to 59) & --FE0 + tidn(53 to 53) & --/// + csrr1_q(60 to 60) & --DE + csrr1_q(61 to 61) & --FE1 + tidn(56 to 57) & --/// + csrr1_q(62 to 62) & --IS + csrr1_q(63 to 63) & --DS + tidn(60 to 63) ; --/// +-- DBCR0 +ex6_dbcr0_di <= ex6_spr_wd(33 to 33) & --IDM + ex6_spr_wd(34 to 35) & --RST + ex6_spr_wd(36 to 36) & --ICMP + ex6_spr_wd(37 to 37) & --BRT + ex6_spr_wd(38 to 38) & --IRPT + ex6_spr_wd(39 to 39) & --TRAP + ex6_spr_wd(40 to 40) & --IAC1 + ex6_spr_wd(41 to 41) & --IAC2 + ex6_spr_wd(42 to 42) & --IAC3 + ex6_spr_wd(43 to 43) & --IAC4 + ex6_spr_wd(44 to 45) & --DAC1 + ex6_spr_wd(46 to 47) & --DAC2 + ex6_spr_wd(48 to 48) & --RET + ex6_spr_wd(59 to 60) & --DAC3 + ex6_spr_wd(61 to 62) & --DAC4 + ex6_spr_wd(63 to 63) ; --FT +dbcr0_do <= tidn(0 to 0) & + tidn(0 to 31) & --/// + cpl_spr_dbcr0_edm & --EDM + dbcr0_q(43 to 43) & --IDM + dbcr0_q(44 to 45) & --RST + dbcr0_q(46 to 46) & --ICMP + dbcr0_q(47 to 47) & --BRT + dbcr0_q(48 to 48) & --IRPT + dbcr0_q(49 to 49) & --TRAP + dbcr0_q(50 to 50) & --IAC1 + dbcr0_q(51 to 51) & --IAC2 + dbcr0_q(52 to 52) & --IAC3 + dbcr0_q(53 to 53) & --IAC4 + dbcr0_q(54 to 55) & --DAC1 + dbcr0_q(56 to 57) & --DAC2 + dbcr0_q(58 to 58) & --RET + tidn(49 to 58) & --/// + dbcr0_q(59 to 60) & --DAC3 + dbcr0_q(61 to 62) & --DAC4 + dbcr0_q(63 to 63) ; --FT +-- DBCR1 +ex6_dbcr1_di <= ex6_spr_wd(32 to 33) & --IAC1US + ex6_spr_wd(34 to 35) & --IAC1ER + ex6_spr_wd(36 to 37) & --IAC2US + ex6_spr_wd(38 to 39) & --IAC2ER + ex6_spr_wd(41 to 41) & --IAC12M + ex6_spr_wd(48 to 49) & --IAC3US + ex6_spr_wd(50 to 51) & --IAC3ER + ex6_spr_wd(52 to 53) & --IAC4US + ex6_spr_wd(54 to 55) & --IAC4ER + ex6_spr_wd(57 to 57) ; --IAC34M +dbcr1_do <= tidn(0 to 0) & + tidn(0 to 31) & --/// + dbcr1_q(46 to 47) & --IAC1US + dbcr1_q(48 to 49) & --IAC1ER + dbcr1_q(50 to 51) & --IAC2US + dbcr1_q(52 to 53) & --IAC2ER + tidn(40 to 40) & --/// + dbcr1_q(54 to 54) & --IAC12M + tidn(42 to 47) & --/// + dbcr1_q(55 to 56) & --IAC3US + dbcr1_q(57 to 58) & --IAC3ER + dbcr1_q(59 to 60) & --IAC4US + dbcr1_q(61 to 62) & --IAC4ER + tidn(56 to 56) & --/// + dbcr1_q(63 to 63) & --IAC34M + tidn(58 to 63) ; --/// +-- DBSR +ex6_dbsr_di <= ex6_spr_wd(32 to 32) & --IDE + ex6_spr_wd(33 to 33) & --UDE + ex6_spr_wd(36 to 36) & --ICMP + ex6_spr_wd(37 to 37) & --BRT + ex6_spr_wd(38 to 38) & --IRPT + ex6_spr_wd(39 to 39) & --TRAP + ex6_spr_wd(40 to 40) & --IAC1 + ex6_spr_wd(41 to 41) & --IAC2 + ex6_spr_wd(42 to 42) & --IAC3 + ex6_spr_wd(43 to 43) & --IAC4 + ex6_spr_wd(44 to 44) & --DAC1R + ex6_spr_wd(45 to 45) & --DAC1W + ex6_spr_wd(46 to 46) & --DAC2R + ex6_spr_wd(47 to 47) & --DAC2W + ex6_spr_wd(48 to 48) & --RET + ex6_spr_wd(59 to 59) & --DAC3R + ex6_spr_wd(60 to 60) & --DAC3W + ex6_spr_wd(61 to 61) & --DAC4R + ex6_spr_wd(62 to 62) & --DAC4W + ex6_spr_wd(63 to 63) ; --IVC +dbsr_do <= tidn(0 to 0) & + tidn(0 to 31) & --/// + dbsr_q(44 to 44) & --IDE + dbsr_q(45 to 45) & --UDE + dbsr_mrr_q(0 to 1) & --MRR + dbsr_q(46 to 46) & --ICMP + dbsr_q(47 to 47) & --BRT + dbsr_q(48 to 48) & --IRPT + dbsr_q(49 to 49) & --TRAP + dbsr_q(50 to 50) & --IAC1 + dbsr_q(51 to 51) & --IAC2 + dbsr_q(52 to 52) & --IAC3 + dbsr_q(53 to 53) & --IAC4 + dbsr_q(54 to 54) & --DAC1R + dbsr_q(55 to 55) & --DAC1W + dbsr_q(56 to 56) & --DAC2R + dbsr_q(57 to 57) & --DAC2W + dbsr_q(58 to 58) & --RET + tidn(49 to 58) & --/// + dbsr_q(59 to 59) & --DAC3R + dbsr_q(60 to 60) & --DAC3W + dbsr_q(61 to 61) & --DAC4R + dbsr_q(62 to 62) & --DAC4W + dbsr_q(63 to 63) ; --IVC +-- DEAR +ex6_dear_di <= ex6_spr_wd(64-(regsize) to 63) ; --DEAR +dear_do <= tidn(0 to 64-(regsize)) & + dear_q(64-(regsize) to 63) ; --DEAR +-- DEC +ex6_dec_di <= ex6_spr_wd(32 to 63) ; --DEC +dec_do <= tidn(0 to 0) & + tidn(0 to 31) & --/// + dec_q(32 to 63) ; --DEC +-- DECAR +ex6_decar_di <= ex6_spr_wd(32 to 63) ; --DECAR +decar_do <= tidn(0 to 0) & + tidn(0 to 31) & --/// + decar_q(32 to 63) ; --DECAR +-- EPCR +ex6_epcr_di <= ex6_spr_wd(32 to 32) & --EXTGS + ex6_spr_wd(33 to 33) & --DTLBGS + ex6_spr_wd(34 to 34) & --ITLBGS + ex6_spr_wd(35 to 35) & --DSIGS + ex6_spr_wd(36 to 36) & --ISIGS + ex6_spr_wd(37 to 37) & --DUVD + ex6_spr_wd(38 to 38) & --ICM + ex6_spr_wd(39 to 39) & --GICM + ex6_spr_wd(40 to 40) & --DGTMI + ex6_spr_wd(41 to 41) ; --DMIUH +epcr_do <= tidn(0 to 0) & + tidn(0 to 31) & --/// + epcr_q(54 to 54) & --EXTGS + epcr_q(55 to 55) & --DTLBGS + epcr_q(56 to 56) & --ITLBGS + epcr_q(57 to 57) & --DSIGS + epcr_q(58 to 58) & --ISIGS + epcr_q(59 to 59) & --DUVD + epcr_q(60 to 60) & --ICM + epcr_q(61 to 61) & --GICM + epcr_q(62 to 62) & --DGTMI + epcr_q(63 to 63) & --DMIUH + tidn(42 to 63) ; --/// +-- ESR +ex6_esr_di <= ex6_spr_wd(36 to 36) & --PIL + ex6_spr_wd(37 to 37) & --PPR + ex6_spr_wd(38 to 38) & --PTR + ex6_spr_wd(39 to 39) & --FP + ex6_spr_wd(40 to 40) & --ST + ex6_spr_wd(42 to 42) & --DLK0 + ex6_spr_wd(43 to 43) & --DLK1 + ex6_spr_wd(44 to 44) & --AP + ex6_spr_wd(45 to 45) & --PUO + ex6_spr_wd(46 to 46) & --BO + ex6_spr_wd(47 to 47) & --PIE + ex6_spr_wd(49 to 49) & --UCT + ex6_spr_wd(53 to 53) & --DATA + ex6_spr_wd(54 to 54) & --TLBI + ex6_spr_wd(55 to 55) & --PT + ex6_spr_wd(56 to 56) & --SPV + ex6_spr_wd(57 to 57) ; --EPID +esr_do <= tidn(0 to 0) & + tidn(0 to 31) & --/// + tidn(32 to 35) & --/// + esr_q(47 to 47) & --PIL + esr_q(48 to 48) & --PPR + esr_q(49 to 49) & --PTR + esr_q(50 to 50) & --FP + esr_q(51 to 51) & --ST + tidn(41 to 41) & --/// + esr_q(52 to 52) & --DLK0 + esr_q(53 to 53) & --DLK1 + esr_q(54 to 54) & --AP + esr_q(55 to 55) & --PUO + esr_q(56 to 56) & --BO + esr_q(57 to 57) & --PIE + tidn(48 to 48) & --/// + esr_q(58 to 58) & --UCT + tidn(50 to 52) & --/// + esr_q(59 to 59) & --DATA + esr_q(60 to 60) & --TLBI + esr_q(61 to 61) & --PT + esr_q(62 to 62) & --SPV + esr_q(63 to 63) & --EPID + tidn(58 to 63) ; --/// +-- GDEAR +ex6_gdear_di <= ex6_spr_wd(64-(regsize) to 63) ; --GDEAR +gdear_do <= tidn(0 to 64-(regsize)) & + gdear_q(64-(regsize) to 63) ; --GDEAR +-- GESR +ex6_gesr_di <= ex6_spr_wd(36 to 36) & --PIL + ex6_spr_wd(37 to 37) & --PPR + ex6_spr_wd(38 to 38) & --PTR + ex6_spr_wd(39 to 39) & --FP + ex6_spr_wd(40 to 40) & --ST + ex6_spr_wd(42 to 42) & --DLK0 + ex6_spr_wd(43 to 43) & --DLK1 + ex6_spr_wd(44 to 44) & --AP + ex6_spr_wd(45 to 45) & --PUO + ex6_spr_wd(46 to 46) & --BO + ex6_spr_wd(47 to 47) & --PIE + ex6_spr_wd(49 to 49) & --UCT + ex6_spr_wd(53 to 53) & --DATA + ex6_spr_wd(54 to 54) & --TLBI + ex6_spr_wd(55 to 55) & --PT + ex6_spr_wd(56 to 56) & --SPV + ex6_spr_wd(57 to 57) ; --EPID +gesr_do <= tidn(0 to 0) & + tidn(0 to 31) & --/// + tidn(32 to 35) & --/// + gesr_q(47 to 47) & --PIL + gesr_q(48 to 48) & --PPR + gesr_q(49 to 49) & --PTR + gesr_q(50 to 50) & --FP + gesr_q(51 to 51) & --ST + tidn(41 to 41) & --/// + gesr_q(52 to 52) & --DLK0 + gesr_q(53 to 53) & --DLK1 + gesr_q(54 to 54) & --AP + gesr_q(55 to 55) & --PUO + gesr_q(56 to 56) & --BO + gesr_q(57 to 57) & --PIE + tidn(48 to 48) & --/// + gesr_q(58 to 58) & --UCT + tidn(50 to 52) & --/// + gesr_q(59 to 59) & --DATA + gesr_q(60 to 60) & --TLBI + gesr_q(61 to 61) & --PT + gesr_q(62 to 62) & --SPV + gesr_q(63 to 63) & --EPID + tidn(58 to 63) ; --/// +-- GPIR +ex6_gpir_di <= ex6_spr_wd(32 to 49) & --VPTAG + ex6_spr_wd(50 to 63) ; --DBTAG +gpir_do <= tidn(0 to 0) & + tidn(0 to 31) & --/// + gpir_q(32 to 49) & --VPTAG + gpir_q(50 to 63) ; --DBTAG +-- GSRR0 +ex6_gsrr0_di <= ex6_spr_wd(62-(eff_ifar) to 61) ; --GSRR0 +gsrr0_do <= tidn(0 to 62-(eff_ifar)) & + gsrr0_q(64-(eff_ifar) to 63) & --GSRR0 + tidn(62 to 63) ; --/// +-- GSRR1 +ex6_gsrr1_di <= ex6_spr_wd(32 to 32) & --CM + ex6_spr_wd(35 to 35) & --GS + ex6_spr_wd(37 to 37) & --UCLE + ex6_spr_wd(38 to 38) & --SPV + ex6_spr_wd(46 to 46) & --CE + ex6_spr_wd(48 to 48) & --EE + ex6_spr_wd(49 to 49) & --PR + ex6_spr_wd(50 to 50) & --FP + ex6_spr_wd(51 to 51) & --ME + ex6_spr_wd(52 to 52) & --FE0 + ex6_spr_wd(54 to 54) & --DE + ex6_spr_wd(55 to 55) & --FE1 + ex6_spr_wd(58 to 58) & --IS + ex6_spr_wd(59 to 59) ; --DS +gsrr1_do <= tidn(0 to 0) & + tidn(0 to 31) & --/// + gsrr1_q(50 to 50) & --CM + tidn(33 to 34) & --/// + gsrr1_q(51 to 51) & --GS + tidn(36 to 36) & --/// + gsrr1_q(52 to 52) & --UCLE + gsrr1_q(53 to 53) & --SPV + tidn(39 to 45) & --/// + gsrr1_q(54 to 54) & --CE + tidn(47 to 47) & --/// + gsrr1_q(55 to 55) & --EE + gsrr1_q(56 to 56) & --PR + gsrr1_q(57 to 57) & --FP + gsrr1_q(58 to 58) & --ME + gsrr1_q(59 to 59) & --FE0 + tidn(53 to 53) & --/// + gsrr1_q(60 to 60) & --DE + gsrr1_q(61 to 61) & --FE1 + tidn(56 to 57) & --/// + gsrr1_q(62 to 62) & --IS + gsrr1_q(63 to 63) & --DS + tidn(60 to 63) ; --/// +-- HACOP +ex6_hacop_di <= ex6_spr_wd(32 to 63) ; --CT +hacop_do <= tidn(0 to 0) & + tidn(0 to 31) & --/// + hacop_q(32 to 63) ; --CT +-- MCSR +ex6_mcsr_di <= ex6_spr_wd(48 to 48) & --DPOVR + ex6_spr_wd(49 to 49) & --DDMH + ex6_spr_wd(50 to 50) & --TLBIVAXSR + ex6_spr_wd(51 to 51) & --TLBLRUPE + ex6_spr_wd(52 to 52) & --IL2ECC + ex6_spr_wd(53 to 53) & --DL2ECC + ex6_spr_wd(54 to 54) & --DDPE + ex6_spr_wd(55 to 55) & --EXT + ex6_spr_wd(56 to 56) & --DCPE + ex6_spr_wd(57 to 57) & --IEMH + ex6_spr_wd(58 to 58) & --DEMH + ex6_spr_wd(59 to 59) & --TLBMH + ex6_spr_wd(60 to 60) & --IEPE + ex6_spr_wd(61 to 61) & --DEPE + ex6_spr_wd(62 to 62) ; --TLBPE +mcsr_do <= tidn(0 to 0) & + tidn(0 to 31) & --/// + tidn(32 to 47) & --/// + mcsr_q(49 to 49) & --DPOVR + mcsr_q(50 to 50) & --DDMH + mcsr_q(51 to 51) & --TLBIVAXSR + mcsr_q(52 to 52) & --TLBLRUPE + mcsr_q(53 to 53) & --IL2ECC + mcsr_q(54 to 54) & --DL2ECC + mcsr_q(55 to 55) & --DDPE + mcsr_q(56 to 56) & --EXT + mcsr_q(57 to 57) & --DCPE + mcsr_q(58 to 58) & --IEMH + mcsr_q(59 to 59) & --DEMH + mcsr_q(60 to 60) & --TLBMH + mcsr_q(61 to 61) & --IEPE + mcsr_q(62 to 62) & --DEPE + mcsr_q(63 to 63) & --TLBPE + tidn(63 to 63) ; --/// +-- MCSRR0 +ex6_mcsrr0_di <= ex6_spr_wd(62-(eff_ifar) to 61) ; --SRR0 +mcsrr0_do <= tidn(0 to 62-(eff_ifar)) & + mcsrr0_q(64-(eff_ifar) to 63) & --SRR0 + tidn(62 to 63) ; --/// +-- MCSRR1 +ex6_mcsrr1_di <= ex6_spr_wd(32 to 32) & --CM + ex6_spr_wd(35 to 35) & --GS + ex6_spr_wd(37 to 37) & --UCLE + ex6_spr_wd(38 to 38) & --SPV + ex6_spr_wd(46 to 46) & --CE + ex6_spr_wd(48 to 48) & --EE + ex6_spr_wd(49 to 49) & --PR + ex6_spr_wd(50 to 50) & --FP + ex6_spr_wd(51 to 51) & --ME + ex6_spr_wd(52 to 52) & --FE0 + ex6_spr_wd(54 to 54) & --DE + ex6_spr_wd(55 to 55) & --FE1 + ex6_spr_wd(58 to 58) & --IS + ex6_spr_wd(59 to 59) ; --DS +mcsrr1_do <= tidn(0 to 0) & + tidn(0 to 31) & --/// + mcsrr1_q(50 to 50) & --CM + tidn(33 to 34) & --/// + mcsrr1_q(51 to 51) & --GS + tidn(36 to 36) & --/// + mcsrr1_q(52 to 52) & --UCLE + mcsrr1_q(53 to 53) & --SPV + tidn(39 to 45) & --/// + mcsrr1_q(54 to 54) & --CE + tidn(47 to 47) & --/// + mcsrr1_q(55 to 55) & --EE + mcsrr1_q(56 to 56) & --PR + mcsrr1_q(57 to 57) & --FP + mcsrr1_q(58 to 58) & --ME + mcsrr1_q(59 to 59) & --FE0 + tidn(53 to 53) & --/// + mcsrr1_q(60 to 60) & --DE + mcsrr1_q(61 to 61) & --FE1 + tidn(56 to 57) & --/// + mcsrr1_q(62 to 62) & --IS + mcsrr1_q(63 to 63) & --DS + tidn(60 to 63) ; --/// +-- MSR +ex6_msr_di <= ex6_spr_wd(32 to 32) & --CM + ex6_spr_wd(35 to 35) & --GS + ex6_spr_wd(37 to 37) & --UCLE + ex6_spr_wd(38 to 38) & --SPV + ex6_spr_wd(46 to 46) & --CE + ex6_spr_wd(48 to 48) & --EE + ex6_spr_wd(49 to 49) & --PR + ex6_spr_wd(50 to 50) & --FP + ex6_spr_wd(51 to 51) & --ME + ex6_spr_wd(52 to 52) & --FE0 + ex6_spr_wd(54 to 54) & --DE + ex6_spr_wd(55 to 55) & --FE1 + ex6_spr_wd(58 to 58) & --IS + ex6_spr_wd(59 to 59) ; --DS +msr_do <= tidn(0 to 0) & + tidn(0 to 31) & --/// + msr_q(50 to 50) & --CM + tidn(33 to 34) & --/// + msr_q(51 to 51) & --GS + tidn(36 to 36) & --/// + msr_q(52 to 52) & --UCLE + msr_q(53 to 53) & --SPV + tidn(39 to 45) & --/// + msr_q(54 to 54) & --CE + tidn(47 to 47) & --/// + msr_q(55 to 55) & --EE + msr_q(56 to 56) & --PR + msr_q(57 to 57) & --FP + msr_q(58 to 58) & --ME + msr_q(59 to 59) & --FE0 + tidn(53 to 53) & --/// + msr_q(60 to 60) & --DE + msr_q(61 to 61) & --FE1 + tidn(56 to 57) & --/// + msr_q(62 to 62) & --IS + msr_q(63 to 63) & --DS + tidn(60 to 63) ; --/// +-- MSRP +ex6_msrp_di <= ex6_spr_wd(37 to 37) & --UCLEP + ex6_spr_wd(54 to 54) ; --DEP +msrp_do <= tidn(0 to 0) & + tidn(0 to 31) & --/// + tidn(32 to 36) & --/// + msrp_q(62 to 62) & --UCLEP + tidn(38 to 53) & --/// + msrp_q(63 to 63) & --DEP + tidn(55 to 63) ; --/// +-- SRR0 +ex6_srr0_di <= ex6_spr_wd(62-(eff_ifar) to 61) ; --SRR0 +srr0_do <= tidn(0 to 62-(eff_ifar)) & + srr0_q(64-(eff_ifar) to 63) & --SRR0 + tidn(62 to 63) ; --/// +-- SRR1 +ex6_srr1_di <= ex6_spr_wd(32 to 32) & --CM + ex6_spr_wd(35 to 35) & --GS + ex6_spr_wd(37 to 37) & --UCLE + ex6_spr_wd(38 to 38) & --SPV + ex6_spr_wd(46 to 46) & --CE + ex6_spr_wd(48 to 48) & --EE + ex6_spr_wd(49 to 49) & --PR + ex6_spr_wd(50 to 50) & --FP + ex6_spr_wd(51 to 51) & --ME + ex6_spr_wd(52 to 52) & --FE0 + ex6_spr_wd(54 to 54) & --DE + ex6_spr_wd(55 to 55) & --FE1 + ex6_spr_wd(58 to 58) & --IS + ex6_spr_wd(59 to 59) ; --DS +srr1_do <= tidn(0 to 0) & + tidn(0 to 31) & --/// + srr1_q(50 to 50) & --CM + tidn(33 to 34) & --/// + srr1_q(51 to 51) & --GS + tidn(36 to 36) & --/// + srr1_q(52 to 52) & --UCLE + srr1_q(53 to 53) & --SPV + tidn(39 to 45) & --/// + srr1_q(54 to 54) & --CE + tidn(47 to 47) & --/// + srr1_q(55 to 55) & --EE + srr1_q(56 to 56) & --PR + srr1_q(57 to 57) & --FP + srr1_q(58 to 58) & --ME + srr1_q(59 to 59) & --FE0 + tidn(53 to 53) & --/// + srr1_q(60 to 60) & --DE + srr1_q(61 to 61) & --FE1 + tidn(56 to 57) & --/// + srr1_q(62 to 62) & --IS + srr1_q(63 to 63) & --DS + tidn(60 to 63) ; --/// +-- TCR +ex6_tcr_di <= ex6_spr_wd(32 to 33) & --WP + ex6_spr_wd(34 to 35) & --WRC + ex6_spr_wd(36 to 36) & --WIE + ex6_spr_wd(37 to 37) & --DIE + ex6_spr_wd(38 to 39) & --FP + ex6_spr_wd(40 to 40) & --FIE + ex6_spr_wd(41 to 41) & --ARE + ex6_spr_wd(42 to 42) & --UDIE + ex6_spr_wd(51 to 51) ; --UD +tcr_do <= tidn(0 to 0) & + tidn(0 to 31) & --/// + tcr_q(52 to 53) & --WP + tcr_q(54 to 55) & --WRC + tcr_q(56 to 56) & --WIE + tcr_q(57 to 57) & --DIE + tcr_q(58 to 59) & --FP + tcr_q(60 to 60) & --FIE + tcr_q(61 to 61) & --ARE + tcr_q(62 to 62) & --UDIE + tidn(43 to 50) & --/// + tcr_q(63 to 63) & --UD + tidn(52 to 63) ; --/// +-- TSR +ex6_tsr_di <= ex6_spr_wd(32 to 32) & --ENW + ex6_spr_wd(33 to 33) & --WIS + ex6_spr_wd(36 to 36) & --DIS + ex6_spr_wd(37 to 37) & --FIS + ex6_spr_wd(38 to 38) ; --UDIS +tsr_do <= tidn(0 to 0) & + tidn(0 to 31) & --/// + tsr_q(59 to 59) & --ENW + tsr_q(60 to 60) & --WIS + tsr_wrs_q(0 to 1) & --WRS + tsr_q(61 to 61) & --DIS + tsr_q(62 to 62) & --FIS + tsr_q(63 to 63) & --UDIS + tidn(39 to 63) ; --/// +-- UDEC +ex6_udec_di <= ex6_spr_wd(32 to 63) ; --UDEC +udec_do <= tidn(0 to 0) & + tidn(0 to 31) & --/// + udec_q(32 to 63) ; --UDEC +-- XUCR1 +ex6_xucr1_di <= ex6_spr_wd(57 to 59) & --LL_TB_SEL + ex6_spr_wd(62 to 62) & --LL_SEL + ex6_spr_wd(63 to 63) ; --LL_EN +xucr1_do <= tidn(0 to 0) & + tidn(0 to 31) & --/// + tidn(32 to 56) & --/// + xucr1_q(59 to 61) & --LL_TB_SEL + llstate(0 to 1) & --LL_STATE + xucr1_q(62 to 62) & --LL_SEL + xucr1_q(63 to 63) ; --LL_EN + +-- Unused Signals +mark_unused(acop_do(0 to 64-regsize)); +mark_unused(ccr3_do(0 to 64-regsize)); +mark_unused(csrr0_do(0 to 64-regsize)); +mark_unused(csrr1_do(0 to 64-regsize)); +mark_unused(dbcr0_do(0 to 64-regsize)); +mark_unused(dbcr1_do(0 to 64-regsize)); +mark_unused(dbsr_do(0 to 64-regsize)); +mark_unused(dear_do(0 to 64-regsize)); +mark_unused(dec_do(0 to 64-regsize)); +mark_unused(decar_do(0 to 64-regsize)); +mark_unused(epcr_do(0 to 64-regsize)); +mark_unused(esr_do(0 to 64-regsize)); +mark_unused(gdear_do(0 to 64-regsize)); +mark_unused(gesr_do(0 to 64-regsize)); +mark_unused(gpir_do(0 to 64-regsize)); +mark_unused(gsrr0_do(0 to 64-regsize)); +mark_unused(gsrr1_do(0 to 64-regsize)); +mark_unused(hacop_do(0 to 64-regsize)); +mark_unused(mcsr_do(0 to 64-regsize)); +mark_unused(mcsrr0_do(0 to 64-regsize)); +mark_unused(mcsrr1_do(0 to 64-regsize)); +mark_unused(msr_do(0 to 64-regsize)); +mark_unused(msrp_do(0 to 64-regsize)); +mark_unused(srr0_do(0 to 64-regsize)); +mark_unused(srr1_do(0 to 64-regsize)); +mark_unused(tcr_do(0 to 64-regsize)); +mark_unused(tsr_do(0 to 64-regsize)); +mark_unused(udec_do(0 to 64-regsize)); +mark_unused(xucr1_do(0 to 64-regsize)); +mark_unused(ex2_ctr_re); +mark_unused(ex2_lr_re); +mark_unused(ex2_xer_re); +mark_unused(ex2_acop_we); +mark_unused(ex2_ctr_we); +mark_unused(ex2_dear_we); +mark_unused(ex2_dec_we); +mark_unused(ex2_esr_we); +mark_unused(ex2_gdear_we); +mark_unused(ex2_gesr_we); +mark_unused(ex2_gsrr0_we); +mark_unused(ex2_gsrr1_we); +mark_unused(ex2_lr_we); +mark_unused(ex2_srr0_we); +mark_unused(ex2_srr1_we); +mark_unused(ex2_udec_we); +mark_unused(ex2_xer_we); +mark_unused(ex2_rs2_q(48 to 49)); +mark_unused(cspr_tspr_ex1_instr(6 to 10)); +mark_unused(cspr_tspr_ex1_instr(31)); +mark_unused(ex6_gdear_di); +mark_unused(exx_act_data(1)); +mark_unused(exx_act_data(3 to 4)); +mark_unused(mchk_int_q); + +-- SPR Latch Instances +acop_latch_gen : if a2mode = 1 generate +acop_latch : tri_ser_rlmreg_p +generic map(width => acop_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => acop_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(acop_offset to acop_offset + acop_q'length-1), + scout => sov(acop_offset to acop_offset + acop_q'length-1), + din => acop_d, + dout => acop_q); +end generate; +acop_latch_tie : if a2mode = 0 generate + acop_q <= (others=>'0'); +end generate; +ccr3_latch : tri_ser_rlmreg_p +generic map(width => ccr3_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => ccr3_act, + forcee => ccfg_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => ccfg_sl_thold_0_b, + sg => sg_0, + scin => siv_ccfg(ccr3_offset_ccfg to ccr3_offset_ccfg + ccr3_q'length-1), + scout => sov_ccfg(ccr3_offset_ccfg to ccr3_offset_ccfg + ccr3_q'length-1), + din => ccr3_d, + dout => ccr3_q); +csrr0_latch_gen : if a2mode = 1 generate +csrr0_latch : tri_ser_rlmreg_p +generic map(width => csrr0_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => csrr0_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(csrr0_offset to csrr0_offset + csrr0_q'length-1), + scout => sov(csrr0_offset to csrr0_offset + csrr0_q'length-1), + din => csrr0_d, + dout => csrr0_q); +end generate; +csrr0_latch_tie : if a2mode = 0 generate + csrr0_q <= (others=>'0'); +end generate; +csrr1_latch_gen : if a2mode = 1 generate +csrr1_latch : tri_ser_rlmreg_p +generic map(width => csrr1_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => csrr1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(csrr1_offset to csrr1_offset + csrr1_q'length-1), + scout => sov(csrr1_offset to csrr1_offset + csrr1_q'length-1), + din => csrr1_d, + dout => csrr1_q); +end generate; +csrr1_latch_tie : if a2mode = 0 generate + csrr1_q <= (others=>'0'); +end generate; +dbcr0_latch : tri_ser_rlmreg_p +generic map(width => dbcr0_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => dbcr0_act, + forcee => dcfg_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => dcfg_sl_thold_0_b, + sg => sg_0, + scin => siv_dcfg(dbcr0_offset_dcfg to dbcr0_offset_dcfg + dbcr0_q'length-1), + scout => sov_dcfg(dbcr0_offset_dcfg to dbcr0_offset_dcfg + dbcr0_q'length-1), + din => dbcr0_d, + dout => dbcr0_q); +dbcr1_latch : tri_ser_rlmreg_p +generic map(width => dbcr1_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => dbcr1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dbcr1_offset to dbcr1_offset + dbcr1_q'length-1), + scout => sov(dbcr1_offset to dbcr1_offset + dbcr1_q'length-1), + din => dbcr1_d, + dout => dbcr1_q); +dbsr_latch : tri_ser_rlmreg_p +generic map(width => dbsr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => dbsr_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dbsr_offset to dbsr_offset + dbsr_q'length-1), + scout => sov(dbsr_offset to dbsr_offset + dbsr_q'length-1), + din => dbsr_d, + dout => dbsr_q); +dear_latch : tri_ser_rlmreg_p +generic map(width => dear_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => dear_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dear_offset to dear_offset + dear_q'length-1), + scout => sov(dear_offset to dear_offset + dear_q'length-1), + din => dear_d, + dout => dear_q); +dec_latch : tri_ser_rlmreg_p +generic map(width => dec_q'length, init => 2147483647, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => dec_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(dec_offset to dec_offset + dec_q'length-1), + scout => sov(dec_offset to dec_offset + dec_q'length-1), + din => dec_d, + dout => dec_q); +decar_latch_gen : if a2mode = 1 generate +decar_latch : tri_ser_rlmreg_p +generic map(width => decar_q'length, init => 2147483647, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => decar_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(decar_offset to decar_offset + decar_q'length-1), + scout => sov(decar_offset to decar_offset + decar_q'length-1), + din => decar_d, + dout => decar_q); +end generate; +decar_latch_tie : if a2mode = 0 generate + decar_q <= (others=>'0'); +end generate; +epcr_latch_gen : if hvmode = 1 generate +epcr_latch : tri_ser_rlmreg_p +generic map(width => epcr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => epcr_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(epcr_offset to epcr_offset + epcr_q'length-1), + scout => sov(epcr_offset to epcr_offset + epcr_q'length-1), + din => epcr_d, + dout => epcr_q); +end generate; +epcr_latch_tie : if hvmode = 0 generate + epcr_q <= (others=>'0'); +end generate; +esr_latch : tri_ser_rlmreg_p +generic map(width => esr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => esr_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(esr_offset to esr_offset + esr_q'length-1), + scout => sov(esr_offset to esr_offset + esr_q'length-1), + din => esr_d, + dout => esr_q); +gdear_latch_gen : if hvmode = 1 generate +gdear_latch : tri_ser_rlmreg_p +generic map(width => gdear_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => gdear_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(gdear_offset to gdear_offset + gdear_q'length-1), + scout => sov(gdear_offset to gdear_offset + gdear_q'length-1), + din => gdear_d, + dout => gdear_q); +end generate; +gdear_latch_tie : if hvmode = 0 generate + gdear_q <= (others=>'0'); +end generate; +gesr_latch_gen : if hvmode = 1 generate +gesr_latch : tri_ser_rlmreg_p +generic map(width => gesr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => gesr_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(gesr_offset to gesr_offset + gesr_q'length-1), + scout => sov(gesr_offset to gesr_offset + gesr_q'length-1), + din => gesr_d, + dout => gesr_q); +end generate; +gesr_latch_tie : if hvmode = 0 generate + gesr_q <= (others=>'0'); +end generate; +gpir_latch_gen : if hvmode = 1 generate +gpir_latch : tri_ser_rlmreg_p +generic map(width => gpir_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => gpir_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(gpir_offset to gpir_offset + gpir_q'length-1), + scout => sov(gpir_offset to gpir_offset + gpir_q'length-1), + din => gpir_d, + dout => gpir_q); +end generate; +gpir_latch_tie : if hvmode = 0 generate + gpir_q <= (others=>'0'); +end generate; +gsrr0_latch_gen : if hvmode = 1 generate +gsrr0_latch : tri_ser_rlmreg_p +generic map(width => gsrr0_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => gsrr0_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(gsrr0_offset to gsrr0_offset + gsrr0_q'length-1), + scout => sov(gsrr0_offset to gsrr0_offset + gsrr0_q'length-1), + din => gsrr0_d, + dout => gsrr0_q); +end generate; +gsrr0_latch_tie : if hvmode = 0 generate + gsrr0_q <= (others=>'0'); +end generate; +gsrr1_latch_gen : if hvmode = 1 generate +gsrr1_latch : tri_ser_rlmreg_p +generic map(width => gsrr1_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => gsrr1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(gsrr1_offset to gsrr1_offset + gsrr1_q'length-1), + scout => sov(gsrr1_offset to gsrr1_offset + gsrr1_q'length-1), + din => gsrr1_d, + dout => gsrr1_q); +end generate; +gsrr1_latch_tie : if hvmode = 0 generate + gsrr1_q <= (others=>'0'); +end generate; +hacop_latch_gen : if hvmode = 1 generate +hacop_latch : tri_ser_rlmreg_p +generic map(width => hacop_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => hacop_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(hacop_offset to hacop_offset + hacop_q'length-1), + scout => sov(hacop_offset to hacop_offset + hacop_q'length-1), + din => hacop_d, + dout => hacop_q); +end generate; +hacop_latch_tie : if hvmode = 0 generate + hacop_q <= (others=>'0'); +end generate; +mcsr_latch_gen : if a2mode = 1 generate +mcsr_latch : tri_ser_rlmreg_p +generic map(width => mcsr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => mcsr_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(mcsr_offset to mcsr_offset + mcsr_q'length-1), + scout => sov(mcsr_offset to mcsr_offset + mcsr_q'length-1), + din => mcsr_d, + dout => mcsr_q); +end generate; +mcsr_latch_tie : if a2mode = 0 generate + mcsr_q <= (others=>'0'); +end generate; +mcsrr0_latch_gen : if a2mode = 1 generate +mcsrr0_latch : tri_ser_rlmreg_p +generic map(width => mcsrr0_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => mcsrr0_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(mcsrr0_offset to mcsrr0_offset + mcsrr0_q'length-1), + scout => sov(mcsrr0_offset to mcsrr0_offset + mcsrr0_q'length-1), + din => mcsrr0_d, + dout => mcsrr0_q); +end generate; +mcsrr0_latch_tie : if a2mode = 0 generate + mcsrr0_q <= (others=>'0'); +end generate; +mcsrr1_latch_gen : if a2mode = 1 generate +mcsrr1_latch : tri_ser_rlmreg_p +generic map(width => mcsrr1_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => mcsrr1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(mcsrr1_offset to mcsrr1_offset + mcsrr1_q'length-1), + scout => sov(mcsrr1_offset to mcsrr1_offset + mcsrr1_q'length-1), + din => mcsrr1_d, + dout => mcsrr1_q); +end generate; +mcsrr1_latch_tie : if a2mode = 0 generate + mcsrr1_q <= (others=>'0'); +end generate; +msr_latch : tri_ser_rlmreg_p +generic map(width => msr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => msr_act, + forcee => ccfg_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => ccfg_sl_thold_0_b, + sg => sg_0, + scin => siv_ccfg(msr_offset_ccfg to msr_offset_ccfg + msr_q'length-1), + scout => sov_ccfg(msr_offset_ccfg to msr_offset_ccfg + msr_q'length-1), + din => msr_d, + dout => msr_q); +msrp_latch_gen : if hvmode = 1 generate +msrp_latch : tri_ser_rlmreg_p +generic map(width => msrp_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => msrp_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(msrp_offset to msrp_offset + msrp_q'length-1), + scout => sov(msrp_offset to msrp_offset + msrp_q'length-1), + din => msrp_d, + dout => msrp_q); +end generate; +msrp_latch_tie : if hvmode = 0 generate + msrp_q <= (others=>'0'); +end generate; +srr0_latch : tri_ser_rlmreg_p +generic map(width => srr0_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => srr0_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(srr0_offset to srr0_offset + srr0_q'length-1), + scout => sov(srr0_offset to srr0_offset + srr0_q'length-1), + din => srr0_d, + dout => srr0_q); +srr1_latch : tri_ser_rlmreg_p +generic map(width => srr1_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => srr1_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(srr1_offset to srr1_offset + srr1_q'length-1), + scout => sov(srr1_offset to srr1_offset + srr1_q'length-1), + din => srr1_d, + dout => srr1_q); +tcr_latch_gen : if a2mode = 1 generate +tcr_latch : tri_ser_rlmreg_p +generic map(width => tcr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => tcr_act, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(tcr_offset to tcr_offset + tcr_q'length-1), + scout => sov(tcr_offset to tcr_offset + tcr_q'length-1), + din => tcr_d, + dout => tcr_q); +end generate; +tcr_latch_tie : if a2mode = 0 generate + tcr_q <= (others=>'0'); +end generate; +tsr_latch_gen : if a2mode = 1 generate +tsr_latch : tri_ser_rlmreg_p +generic map(width => tsr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => tsr_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(tsr_offset to tsr_offset + tsr_q'length-1), + scout => sov(tsr_offset to tsr_offset + tsr_q'length-1), + din => tsr_d, + dout => tsr_q); +end generate; +tsr_latch_tie : if a2mode = 0 generate + tsr_q <= (others=>'0'); +end generate; +udec_latch_gen : if a2mode = 1 generate +udec_latch : tri_ser_rlmreg_p +generic map(width => udec_q'length, init => 2147483647, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => udec_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(udec_offset to udec_offset + udec_q'length-1), + scout => sov(udec_offset to udec_offset + udec_q'length-1), + din => udec_d, + dout => udec_q); +end generate; +udec_latch_tie : if a2mode = 0 generate + udec_q <= (others=>'0'); +end generate; +xucr1_latch : tri_ser_rlmreg_p +generic map(width => xucr1_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map(nclk => nclk, vd => vdd, gd => gnd, + act => xucr1_act, + forcee => ccfg_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DWR), + mpw1_b => mpw1_dc_b(DWR), mpw2_b => mpw2_dc_b, + thold_b => ccfg_sl_thold_0_b, + sg => sg_0, + scin => siv_ccfg(xucr1_offset_ccfg to xucr1_offset_ccfg + xucr1_q'length-1), + scout => sov_ccfg(xucr1_offset_ccfg to xucr1_offset_ccfg + xucr1_q'length-1), + din => xucr1_d, + dout => xucr1_q); + + +-- Latch Instances +exx_act_latch : tri_rlmreg_p + generic map (width => exx_act_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(exx_act_offset to exx_act_offset + exx_act_q'length-1), + scout => sov(exx_act_offset to exx_act_offset + exx_act_q'length-1), + din => exx_act_d, + dout => exx_act_q); +ex2_is_mfspr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_mfspr, + dout(0) => ex2_is_mfspr_q); +ex2_is_mtspr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_mtspr, + dout(0) => ex2_is_mtspr_q); +ex2_is_mfmsr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_mfmsr, + dout(0) => ex2_is_mfmsr_q); +ex2_instr_latch : tri_regk + generic map (width => ex2_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex2_instr_d, + dout => ex2_instr_q); +ex3_is_mtxer_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_mtxer_offset), + scout => sov(ex3_is_mtxer_offset), + din => ex3_is_mtxer_d, + dout => ex3_is_mtxer_q); +ex3_is_mfxer_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_is_mfxer_offset), + scout => sov(ex3_is_mfxer_offset), + din => ex3_is_mfxer_d, + dout => ex3_is_mfxer_q); +ex2_rfi_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_rfi_d, + dout(0) => ex2_rfi_q); +ex2_rfgi_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex2_rfgi_d, + dout(0) => ex2_rfgi_q); +ex2_rfci_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_rfci, + dout(0) => ex2_rfci_q); +ex2_rfmci_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex1_is_rfmci, + dout(0) => ex2_rfmci_q); +ex3_rfi_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_rfi_offset), + scout => sov(ex3_rfi_offset), + din => ex2_rfi_q , + dout => ex3_rfi_q); +ex3_rfgi_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_rfgi_offset), + scout => sov(ex3_rfgi_offset), + din => ex2_rfgi_q , + dout => ex3_rfgi_q); +ex3_rfci_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_rfci_offset), + scout => sov(ex3_rfci_offset), + din => ex2_rfci_q , + dout => ex3_rfci_q); +ex3_rfmci_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_rfmci_offset), + scout => sov(ex3_rfmci_offset), + din => ex2_rfmci_q , + dout => ex3_rfmci_q); +ex4_is_mfxer_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX4), + mpw1_b => mpw1_dc_b(DEX4), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_is_mfxer_q , + dout(0) => ex4_is_mfxer_q); +ex4_is_mtxer_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX4), + mpw1_b => mpw1_dc_b(DEX4), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_is_mtxer_q , + dout(0) => ex4_is_mtxer_q); +ex4_rfi_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX4), + mpw1_b => mpw1_dc_b(DEX4), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_rfi_q , + dout(0) => ex4_rfi_q); +ex4_rfgi_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX4), + mpw1_b => mpw1_dc_b(DEX4), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_rfgi_q , + dout(0) => ex4_rfgi_q); +ex4_rfci_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX4), + mpw1_b => mpw1_dc_b(DEX4), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_rfci_q , + dout(0) => ex4_rfci_q); +ex4_rfmci_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(3) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX4), + mpw1_b => mpw1_dc_b(DEX4), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex3_rfmci_q , + dout(0) => ex4_rfmci_q); +ex5_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX5), + mpw1_b => mpw1_dc_b(DEX5), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_val_offset), + scout => sov(ex5_val_offset), + din => ex4_val, + dout => ex5_val_q); +ex5_rfi_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX5), + mpw1_b => mpw1_dc_b(DEX5), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_rfi_offset), + scout => sov(ex5_rfi_offset), + din => ex4_rfi_q , + dout => ex5_rfi_q); +ex5_rfgi_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX5), + mpw1_b => mpw1_dc_b(DEX5), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_rfgi_offset), + scout => sov(ex5_rfgi_offset), + din => ex4_rfgi_q , + dout => ex5_rfgi_q); +ex5_rfci_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX5), + mpw1_b => mpw1_dc_b(DEX5), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_rfci_offset), + scout => sov(ex5_rfci_offset), + din => ex4_rfci_q , + dout => ex5_rfci_q); +ex5_rfmci_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(4) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX5), + mpw1_b => mpw1_dc_b(DEX5), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex5_rfmci_offset), + scout => sov(ex5_rfmci_offset), + din => ex4_rfmci_q , + dout => ex5_rfmci_q); +ex6_val_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex6_val_offset), + scout => sov(ex6_val_offset), + din => ex5_val, + dout => ex6_val_q); +ex6_rfi_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(5) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex5_rfi_q , + dout(0) => ex6_rfi_q); +ex6_rfgi_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(5) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex5_rfgi_q , + dout(0) => ex6_rfgi_q); +ex6_rfci_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(5) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex5_rfci_q , + dout(0) => ex6_rfci_q); +ex6_rfmci_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(5) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => ex5_rfmci_q , + dout(0) => ex6_rfmci_q); +ex6_wrtee_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(5) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => cspr_tspr_ex5_is_wrtee , + dout(0) => ex6_wrtee_q); +ex6_wrteei_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(5) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => cspr_tspr_ex5_is_wrteei , + dout(0) => ex6_wrteei_q); +ex6_is_mtmsr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(5) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => cspr_tspr_ex5_is_mtmsr , + dout(0) => ex6_is_mtmsr_q); +ex6_is_mtspr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(5) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => cspr_tspr_ex5_is_mtspr , + dout(0) => ex6_is_mtspr_q); +ex6_instr_latch : tri_regk + generic map (width => ex6_instr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(5) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => cspr_tspr_ex5_instr , + dout => ex6_instr_q); +ex6_int_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex5_int_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => cpl_spr_ex5_int , + dout(0) => ex6_int_q); +ex6_gint_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex5_int_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => cpl_spr_ex5_gint , + dout(0) => ex6_gint_q); +ex6_cint_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex5_int_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => cpl_spr_ex5_cint , + dout(0) => ex6_cint_q); +ex6_mcint_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex5_int_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => cpl_spr_ex5_mcint , + dout(0) => ex6_mcint_q); +ex6_nia_latch : tri_regk + generic map (width => ex6_nia_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex5_int_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => cpl_spr_ex5_nia , + dout => ex6_nia_q); +ex6_esr_latch : tri_regk + generic map (width => ex6_esr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => cpl_spr_ex5_esr_update , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => cpl_spr_ex5_esr , + dout => ex6_esr_q); +ex6_mcsr_latch : tri_regk + generic map (width => ex6_mcsr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex5_int_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => cpl_spr_ex5_mcsr , + dout => ex6_mcsr_q); +ex6_dbsr_latch : tri_regk + generic map (width => ex6_dbsr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => cpl_spr_ex5_dbsr_update , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => cpl_spr_ex5_dbsr , + dout => ex6_dbsr_q); +ex6_dear_save_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => cpl_spr_ex5_dear_save , + dout(0) => ex6_dear_save_q); +ex6_dear_update_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => cpl_spr_ex5_dear_update , + dout(0) => ex6_dear_update_q); +ex6_dear_update_saved_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => cpl_spr_ex5_dear_update_saved, + dout(0) => ex6_dear_update_saved_q); +ex6_dbsr_update_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => cpl_spr_ex5_dbsr_update , + dout(0) => ex6_dbsr_update_q); +ex6_esr_update_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => cpl_spr_ex5_esr_update , + dout(0) => ex6_esr_update_q); +ex6_srr0_dec_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => cpl_spr_ex5_srr0_dec , + dout(0) => ex6_srr0_dec_q); +ex6_force_gsrr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex5_int_act , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => cpl_spr_ex5_force_gsrr , + dout(0) => ex6_force_gsrr_q); +ex6_dbsr_ide_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex5_int_act, + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => cpl_spr_ex5_dbsr_ide, + dout(0) => ex6_dbsr_ide_q); +ex6_spr_wd_latch : tri_regk + generic map (width => ex6_spr_wd_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act_data(5), + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX6), + mpw1_b => mpw1_dc_b(DEX6), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => ex5_spr_wd , + dout => ex6_spr_wd_q); +fit_tb_tap_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(fit_tb_tap_offset), + scout => sov(fit_tb_tap_offset), + din => fit_tb_tap_d, + dout => fit_tb_tap_q); +wdog_tb_tap_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(wdog_tb_tap_offset), + scout => sov(wdog_tb_tap_offset), + din => wdog_tb_tap_d, + dout => wdog_tb_tap_q); +hang_pulse_latch : tri_rlmreg_p + generic map (width => hang_pulse_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(hang_pulse_offset to hang_pulse_offset + hang_pulse_q'length-1), + scout => sov(hang_pulse_offset to hang_pulse_offset + hang_pulse_q'length-1), + din => hang_pulse_d, + dout => hang_pulse_q); +lltap_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(lltap_offset), + scout => sov(lltap_offset), + din => lltap_d, + dout => lltap_q); +llcnt_latch : tri_rlmreg_p + generic map (width => llcnt_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(llcnt_offset to llcnt_offset + llcnt_q'length-1), + scout => sov(llcnt_offset to llcnt_offset + llcnt_q'length-1), + din => llcnt_d, + dout => llcnt_q); +msrovride_pr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(msrovride_pr_offset), + scout => sov(msrovride_pr_offset), + din => pc_xu_msrovride_pr , + dout => msrovride_pr_q); +msrovride_gs_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(msrovride_gs_offset), + scout => sov(msrovride_gs_offset), + din => pc_xu_msrovride_gs , + dout => msrovride_gs_q); +msrovride_de_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(msrovride_de_offset), + scout => sov(msrovride_de_offset), + din => pc_xu_msrovride_de, + dout => msrovride_de_q); +an_ac_ext_interrupt_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(an_ac_ext_interrupt_offset), + scout => sov(an_ac_ext_interrupt_offset), + din => an_ac_ext_interrupt , + dout => an_ac_ext_interrupt_q); +an_ac_crit_interrupt_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(an_ac_crit_interrupt_offset), + scout => sov(an_ac_crit_interrupt_offset), + din => an_ac_crit_interrupt , + dout => an_ac_crit_interrupt_q); +an_ac_perf_interrupt_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(an_ac_perf_interrupt_offset), + scout => sov(an_ac_perf_interrupt_offset), + din => an_ac_perf_interrupt , + dout => an_ac_perf_interrupt_q); +dear_tmp_latch : tri_rlmreg_p + generic map (width => dear_tmp_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => ex6_dear_save_q, + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dear_tmp_offset to dear_tmp_offset + dear_tmp_q'length-1), + scout => sov(dear_tmp_offset to dear_tmp_offset + dear_tmp_q'length-1), + din => dear_tmp_d, + dout => dear_tmp_q); +mux_msr_gs_latch : tri_rlmreg_p + generic map (width => mux_msr_gs_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(mux_msr_gs_offset to mux_msr_gs_offset + mux_msr_gs_q'length-1), + scout => sov(mux_msr_gs_offset to mux_msr_gs_offset + mux_msr_gs_q'length-1), + din => mux_msr_gs_d, + dout => mux_msr_gs_q); +mux_msr_pr_latch : tri_rlmreg_p + generic map (width => mux_msr_pr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(mux_msr_pr_offset to mux_msr_pr_offset + mux_msr_pr_q'length-1), + scout => sov(mux_msr_pr_offset to mux_msr_pr_offset + mux_msr_pr_q'length-1), + din => mux_msr_pr_d, + dout => mux_msr_pr_q); +ex3_tspr_rt_latch : tri_rlmreg_p + generic map (width => ex3_tspr_rt_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act_data(2), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_tspr_rt_offset to ex3_tspr_rt_offset + ex3_tspr_rt_q'length-1), + scout => sov(ex3_tspr_rt_offset to ex3_tspr_rt_offset + ex3_tspr_rt_q'length-1), + din => ex3_tspr_rt_d, + dout => ex3_tspr_rt_q); +err_llbust_attempt_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(err_llbust_attempt_offset), + scout => sov(err_llbust_attempt_offset), + din => err_llbust_attempt_d, + dout => err_llbust_attempt_q); +err_llbust_failed_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(err_llbust_failed_offset), + scout => sov(err_llbust_failed_offset), + din => err_llbust_failed_d, + dout => err_llbust_failed_q); +inj_llbust_attempt_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(inj_llbust_attempt_offset), + scout => sov(inj_llbust_attempt_offset), + din => pc_xu_inj_llbust_attempt , + dout => inj_llbust_attempt_q); +inj_llbust_failed_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(inj_llbust_failed_offset), + scout => sov(inj_llbust_failed_offset), + din => pc_xu_inj_llbust_failed , + dout => inj_llbust_failed_q); +ex2_rs2_latch : tri_regk + generic map (width => ex2_rs2_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din => fxu_spr_ex1_rs2 , + dout => ex2_rs2_q); +ex3_ct_latch : tri_rlmreg_p + generic map (width => ex3_ct_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2) , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_ct_offset to ex3_ct_offset + ex3_ct_q'length-1), + scout => sov(ex3_ct_offset to ex3_ct_offset + ex3_ct_q'length-1), + din => ex3_ct_d, + dout => ex3_ct_q); +an_ac_external_mchk_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(an_ac_external_mchk_offset), + scout => sov(an_ac_external_mchk_offset), + din => an_ac_external_mchk , + dout => an_ac_external_mchk_q); +mchk_int_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(mchk_int_offset), + scout => sov(mchk_int_offset), + din => mchk_int, + dout => mchk_int_q); +mchk_interrupt_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(mchk_interrupt_offset), + scout => sov(mchk_interrupt_offset), + din => mchk_interrupt, + dout => mchk_interrupt_q); +crit_interrupt_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(crit_interrupt_offset), + scout => sov(crit_interrupt_offset), + din => crit_interrupt, + dout => crit_interrupt_q); +wdog_interrupt_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(wdog_interrupt_offset), + scout => sov(wdog_interrupt_offset), + din => wdog_interrupt, + dout => wdog_interrupt_q); +dec_interrupt_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(dec_interrupt_offset), + scout => sov(dec_interrupt_offset), + din => dec_interrupt, + dout => dec_interrupt_q); +udec_interrupt_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(udec_interrupt_offset), + scout => sov(udec_interrupt_offset), + din => udec_interrupt, + dout => udec_interrupt_q); +perf_interrupt_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(perf_interrupt_offset), + scout => sov(perf_interrupt_offset), + din => perf_interrupt, + dout => perf_interrupt_q); +fit_interrupt_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(fit_interrupt_offset), + scout => sov(fit_interrupt_offset), + din => fit_interrupt, + dout => fit_interrupt_q); +ext_interrupt_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ext_interrupt_offset), + scout => sov(ext_interrupt_offset), + din => ext_interrupt, + dout => ext_interrupt_q); +single_instr_mode_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(single_instr_mode_offset), + scout => sov(single_instr_mode_offset), + din => single_instr_mode_d, + dout => single_instr_mode_q); +single_instr_mode_2_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(single_instr_mode_2_offset), + scout => sov(single_instr_mode_2_offset), + din => single_instr_mode_q , + dout => single_instr_mode_2_q); +machine_check_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(machine_check_offset), + scout => sov(machine_check_offset), + din => machine_check_d, + dout => machine_check_q); +raise_iss_pri_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(raise_iss_pri_offset), + scout => sov(raise_iss_pri_offset), + din => raise_iss_pri_d, + dout => raise_iss_pri_q); +raise_iss_pri_2_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(raise_iss_pri_2_offset), + scout => sov(raise_iss_pri_2_offset), + din => raise_iss_pri_q , + dout => raise_iss_pri_2_q); +epsc_egs_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(epsc_egs_offset), + scout => sov(epsc_egs_offset), + din => lsu_xu_spr_epsc_egs , + dout => epsc_egs_q); +epsc_epr_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(epsc_epr_offset), + scout => sov(epsc_epr_offset), + din => lsu_xu_spr_epsc_epr , + dout => epsc_epr_q); +ex2_epid_instr_latch : tri_regk + generic map (width => 1, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(1) , + forcee => func_nsl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX2), + mpw1_b => mpw1_dc_b(DEX2), mpw2_b => mpw2_dc_b, + thold_b => func_nsl_thold_0_b, + din(0) => dec_spr_ex1_epid_instr , + dout(0) => ex2_epid_instr_q); +pc_xu_inj_wdt_reset_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(pc_xu_inj_wdt_reset_offset), + scout => sov(pc_xu_inj_wdt_reset_offset), + din => pc_xu_inj_wdt_reset , + dout => pc_xu_inj_wdt_reset_q); +err_wdt_reset_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(err_wdt_reset_offset), + scout => sov(err_wdt_reset_offset), + din => err_wdt_reset_d, + dout => err_wdt_reset_q); +ex3_tid_rpwr_latch : tri_rlmreg_p + generic map (width => ex3_tid_rpwr_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => exx_act(2), + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DEX3), + mpw1_b => mpw1_dc_b(DEX3), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_tid_rpwr_offset to ex3_tid_rpwr_offset + ex3_tid_rpwr_q'length-1), + scout => sov(ex3_tid_rpwr_offset to ex3_tid_rpwr_offset + ex3_tid_rpwr_q'length-1), + din => ex3_tid_rpwr_d, + dout => ex3_tid_rpwr_q); +ram_mode_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(ram_mode_offset), + scout => sov(ram_mode_offset), + din => cspr_tspr_ram_mode , + dout => ram_mode_q); +timebase_taps_latch : tri_rlmreg_p + generic map (width => timebase_taps_q'length, init => 0, expand_type => expand_type, needs_sreset => 0) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_slp_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(timebase_taps_offset to timebase_taps_offset + timebase_taps_q'length-1), + scout => sov(timebase_taps_offset to timebase_taps_offset + timebase_taps_q'length-1), + din => cspr_tspr_timebase_taps , + dout => timebase_taps_q); +dbsr_mrr_latch : tri_rlmreg_p + generic map (width => dbsr_mrr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => dbsr_mrr_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(dbsr_mrr_offset to dbsr_mrr_offset + dbsr_mrr_q'length-1), + scout => sov(dbsr_mrr_offset to dbsr_mrr_offset + dbsr_mrr_q'length-1), + din => dbsr_mrr_d, + dout => dbsr_mrr_q); +tsr_wrs_latch : tri_rlmreg_p + generic map (width => tsr_wrs_q'length, init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tsr_wrs_act , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(tsr_wrs_offset to tsr_wrs_offset + tsr_wrs_q'length-1), + scout => sov(tsr_wrs_offset to tsr_wrs_offset + tsr_wrs_q'length-1), + din => tsr_wrs_d, + dout => tsr_wrs_q); +iac1_en_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(iac1_en_offset), + scout => sov(iac1_en_offset), + din => iac1_en_d, + dout => iac1_en_q); +iac2_en_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(iac2_en_offset), + scout => sov(iac2_en_offset), + din => iac2_en_d, + dout => iac2_en_q); +iac3_en_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(iac3_en_offset), + scout => sov(iac3_en_offset), + din => iac3_en_d, + dout => iac3_en_q); +iac4_en_latch : tri_rlmlatch_p + generic map (init => 0, expand_type => expand_type, needs_sreset => 1) + port map (nclk => nclk, vd => vdd, gd => gnd, + act => tiup , + forcee => func_sl_force, + d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(iac4_en_offset), + scout => sov(iac4_en_offset), + din => iac4_en_d, + dout => iac4_en_q); + + +spare_0_lcb: entity tri.tri_lcbnd(tri_lcbnd) + port map(vd => vdd, + gd => gnd, + act => tidn(0), + nclk => nclk, + forcee => func_sl_force, + thold_b => func_sl_thold_0_b, + delay_lclkr => delay_lclkr_dc(DX), + mpw1_b => mpw1_dc_b(DX), + mpw2_b => mpw2_dc_b, + sg => sg_0, + lclk => spare_0_lclk, + d1clk => spare_0_d1clk, + d2clk => spare_0_d2clk); +spare_0_latch : entity tri.tri_inv_nlats(tri_inv_nlats) + generic map (width => spare_0_q'length, expand_type => expand_type, btr => "NLI0001_X2_A12TH", init=>(spare_0_q'range=>'0')) + port map (vd => vdd, gd => gnd, + LCLK => spare_0_lclk, + D1CLK => spare_0_d1clk, + D2CLK => spare_0_d2clk, + SCANIN => siv(spare_0_offset to spare_0_offset + spare_0_q'length-1), + SCANOUT => sov(spare_0_offset to spare_0_offset + spare_0_q'length-1), + D => spare_0_d, + QB => spare_0_q); +spare_0_d <= not spare_0_q; +mark_unused(spare_0_q); + + +siv(0 to scan_right-1) <= sov(1 to scan_right-1) & scan_in; +scan_out <= sov(0); + + +ccfg_l : if sov_ccfg'length > 1 generate +siv_ccfg(0 to scan_right_ccfg-1) <= sov_ccfg(1 to scan_right_ccfg-1) & ccfg_scan_in; +ccfg_scan_out <= sov_ccfg(0); +end generate; +ccfg_s : if sov_ccfg'length <= 1 generate +ccfg_scan_out <= ccfg_scan_in; +sov_ccfg <= (others=>'0'); +siv_ccfg <= (others=>'0'); +end generate; + +dcfg_l : if sov_dcfg'length > 1 generate +siv_dcfg(0 to scan_right_dcfg-1) <= sov_dcfg(1 to scan_right_dcfg-1) & dcfg_scan_in; +dcfg_scan_out <= sov_dcfg(0); +end generate; +dcfg_s : if sov_dcfg'length <= 1 generate +dcfg_scan_out <= dcfg_scan_in; +sov_dcfg <= (others=>'0'); +siv_dcfg <= (others=>'0'); +end generate; + + +end architecture xuq_spr_tspr;